diff --git a/Makefile b/Makefile index 3d25e46cdec7..b83cf8c0c86e 100644 --- a/Makefile +++ b/Makefile @@ -525,40 +525,13 @@ endif ifneq ($(GCC_TOOLCHAIN),) CLANG_FLAGS += --gcc-toolchain=$(GCC_TOOLCHAIN) endif -KBUILD_CPPFLAGS += $(call cc-option,-Qunused-arguments,) -KBUILD_CFLAGS += $(call cc-disable-warning, unused-variable) -KBUILD_CFLAGS += $(call cc-disable-warning, format-invalid-specifier) -KBUILD_CFLAGS += $(call cc-disable-warning, gnu) -KBUILD_CFLAGS += $(call cc-disable-warning, address-of-packed-member) -KBUILD_CFLAGS += $(call cc-disable-warning, duplicate-decl-specifier) -KBUILD_CFLAGS += -Wno-undefined-optimized -KBUILD_CFLAGS += -Wno-tautological-constant-out-of-range-compare -KBUILD_CFLAGS += $(call cc-option, -Wno-sometimes-uninitialized) -KBUILD_CFLAGS += -Wno-asm-operand-widths -KBUILD_CFLAGS += -Wno-initializer-overrides -KBUILD_CFLAGS += -fno-builtin - -# Quiet clang warning: comparison of unsigned expression < 0 is always false - -KBUILD_CFLAGS += $(call cc-disable-warning, tautological-compare) -# CLANG uses a _MergedGlobals as optimization, but this breaks modpost, as the -# source of a reference will be _MergedGlobals and not on of the whitelisted names. -# See modpost pattern 2 -KBUILD_CFLAGS += $(call cc-option, -mno-global-merge,) -KBUILD_CFLAGS += $(call cc-option, -fcatch-undefined-behavior) CLANG_FLAGS += -no-integrated-as CLANG_FLAGS += -Werror=unknown-warning-option KBUILD_CFLAGS += $(CLANG_FLAGS) KBUILD_AFLAGS += $(CLANG_FLAGS) -else - -KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks,) -# These warnings generated too much noise in a regular build. -# Use make W=1 to enable them (see scripts/Makefile.build) -KBUILD_CFLAGS += $(call cc-disable-warning, unused-but-set-variable) -KBUILD_CFLAGS += $(call cc-disable-warning, unused-const-variable) endif + ifeq ($(mixed-targets),1) # =========================================================================== # We're called with mixed targets (*config and build targets). @@ -704,7 +677,6 @@ KBUILD_CFLAGS += $(call cc-disable-warning, format-overflow) KBUILD_CFLAGS += $(call cc-disable-warning, int-in-bool-context) KBUILD_CFLAGS += $(call cc-disable-warning, address-of-packed-member) KBUILD_CFLAGS += $(call cc-disable-warning, attribute-alias) -KBUILD_CFLAGS += $(call cc-disable-warning, address-of-packed-member) ifdef CONFIG_LD_DEAD_CODE_DATA_ELIMINATION KBUILD_CFLAGS += $(call cc-option,-ffunction-sections,) diff --git a/arch/arm/boot/dts/qcom/sdxpoorwills.dtsi b/arch/arm/boot/dts/qcom/sdxpoorwills.dtsi index 0caad4c03c2f..75716613f0e0 100644 --- a/arch/arm/boot/dts/qcom/sdxpoorwills.dtsi +++ b/arch/arm/boot/dts/qcom/sdxpoorwills.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -641,10 +641,8 @@ restart_pshold: restart@c264000 { compatible = "qcom,pshold"; reg = <0x0c264000 0x4>, - <0x01fd3000 0x4>, - <0x00786070 0x4>; - reg-names = "pshold-base", "tcsr-boot-misc-detect", - "boot-config"; + <0x01fd3000 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; }; tsens0: tsens@c222000 { diff --git a/arch/arm/configs/ranchu_defconfig b/arch/arm/configs/ranchu_defconfig index 74ad6aecddc8..f59f38cd1288 100644 --- a/arch/arm/configs/ranchu_defconfig +++ b/arch/arm/configs/ranchu_defconfig @@ -106,7 +106,6 @@ CONFIG_NETFILTER_XT_MATCH_MARK=y CONFIG_NETFILTER_XT_MATCH_OWNER=y CONFIG_NETFILTER_XT_MATCH_POLICY=y CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y -CONFIG_NETFILTER_XT_MATCH_QTAGUID=y CONFIG_NETFILTER_XT_MATCH_QUOTA=y CONFIG_NETFILTER_XT_MATCH_QUOTA2=y CONFIG_NETFILTER_XT_MATCH_SOCKET=y diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h index 3a5bff8a5dcc..1d85857771fd 100644 --- a/arch/arm/include/asm/arch_timer.h +++ b/arch/arm/include/asm/arch_timer.h @@ -113,7 +113,6 @@ static inline u32 arch_timer_get_cntkctl(void) static inline void arch_timer_set_cntkctl(u32 cntkctl) { asm volatile("mcr p15, 0, %0, c14, c1, 0" : : "r" (cntkctl)); - isb(); } #endif diff --git a/arch/arm/kernel/topology.c b/arch/arm/kernel/topology.c index e35b625c3366..aa8fc3f03ed5 100644 --- a/arch/arm/kernel/topology.c +++ b/arch/arm/kernel/topology.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include diff --git a/arch/arm64/boot/dts/qcom/batterydata-d5-atl-3400mAh.dtsi b/arch/arm64/boot/dts/qcom/batterydata-d5-atl-3400mAh.dtsi index e8126e43d8db..bb4f0fccef6a 100644 --- a/arch/arm64/boot/dts/qcom/batterydata-d5-atl-3400mAh.dtsi +++ b/arch/arm64/boot/dts/qcom/batterydata-d5-atl-3400mAh.dtsi @@ -2,85 +2,80 @@ qcom,d5_atl_3400mah { /* #2957455_Xiaomi_D5scud_3400mAh_averaged_MasterSlave_Jun6th2017*/ qcom,max-voltage-uv = <4400000>; - qcom,fastchg-current-ma = <3300>; + qcom,fastchg-current-ma = <3300>; qcom,nom-batt-capacity-mah = <3400>; qcom,fg-cc-cv-threshold-mv = <4390>; qcom,batt-id-kohm = <68>; qcom,battery-beta = <3380>; qcom,battery-type = "d5_atl"; - qcom,jeita-fcc-ranges = <0 50 330000 - 51 100 990000 - 101 150 990000 - 151 450 3300000 - 451 600 1650000>; - qcom,jeita-fv-ranges = <0 50 4400000 - 51 100 4400000 - 101 150 4400000 - 151 450 4400000 - 451 600 4100000>; - qcom,dynamic-fv-ranges = <0 100 4400000 - 101 200 4380000 - 201 300 4360000 - 301 400 4340000 - 401 500 4340000>; + qcom,jeita-fcc-ranges = <0 50 330000 + 51 100 990000 + 101 150 990000 + 151 450 3300000 + 451 600 1650000>; + qcom,jeita-fv-ranges = <0 50 4400000 + 51 100 4400000 + 101 150 4400000 + 151 450 4400000 + 451 600 4100000>; qcom,checksum = <0x8E3D>; qcom,gui-version = "PMI8998GUI - 2.0.0.58"; qcom,fg-profile-data = [ - 0A 1F 3A 06 - 00 0A C7 06 - D4 1C 0C 02 - 98 0D C7 0A - 95 17 D6 23 - 7F 44 31 5A - 6F 00 00 00 - 11 00 00 00 - 00 00 D8 BB - 61 CD DF A2 - 26 00 08 00 - AB EA 51 EC - D1 FC BB F3 - 58 0C F3 FA - 62 06 BB 32 - 1F 06 09 20 - 27 00 14 00 - 18 20 25 05 - D4 0A F4 05 - C8 1C ED 02 - 1A 0C 19 12 - 91 18 AC 23 - 20 44 D6 5A - 6E 00 00 00 - 0E 00 00 00 - 00 00 86 D5 - 3E CA 24 CA - 1E 00 00 00 - 5B F2 51 EC - 7B F4 22 EB - 7A 07 87 FB - 69 BA BC 1B - AB 33 CC FF - 07 10 00 00 - 3E 0D 66 46 - 1E 00 40 00 - 66 01 0A FA - FF 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 + 0A 1F 3A 06 + 00 0A C7 06 + D4 1C 0C 02 + 98 0D C7 0A + 95 17 D6 23 + 7F 44 31 5A + 6F 00 00 00 + 11 00 00 00 + 00 00 D8 BB + 61 CD DF A2 + 26 00 08 00 + AB EA 51 EC + D1 FC BB F3 + 58 0C F3 FA + 62 06 BB 32 + 1F 06 09 20 + 27 00 14 00 + 18 20 25 05 + D4 0A F4 05 + C8 1C ED 02 + 1A 0C 19 12 + 91 18 AC 23 + 20 44 D6 5A + 6E 00 00 00 + 0E 00 00 00 + 00 00 86 D5 + 3E CA 24 CA + 1E 00 00 00 + 5B F2 51 EC + 7B F4 22 EB + 7A 07 87 FB + 69 BA BC 1B + AB 33 CC FF + 07 10 00 00 + 3E 0D 66 46 + 1E 00 40 00 + 66 01 0A FA + FF 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 ]; }; diff --git a/arch/arm64/boot/dts/qcom/batterydata-d5-cos-3400mAh.dtsi b/arch/arm64/boot/dts/qcom/batterydata-d5-cos-3400mAh.dtsi index 21f3690da1f6..7a449f0fece9 100644 --- a/arch/arm64/boot/dts/qcom/batterydata-d5-cos-3400mAh.dtsi +++ b/arch/arm64/boot/dts/qcom/batterydata-d5-cos-3400mAh.dtsi @@ -1,85 +1,81 @@ qcom,d5_cos_3400mah { + /* #2957479_Xiaomi_D5cos_3400mAh_averaged_MasterSlave_Jun6th2017*/ qcom,max-voltage-uv = <4400000>; - qcom,fastchg-current-ma = <3300>; + qcom,fastchg-current-ma = <3300>; qcom,nom-batt-capacity-mah = <3400>; qcom,fg-cc-cv-threshold-mv = <4390>; qcom,batt-id-kohm = <100>; qcom,battery-beta = <3380>; qcom,battery-type = "d5_cos"; - qcom,jeita-fcc-ranges = <0 50 330000 - 51 100 990000 + qcom,jeita-fcc-ranges = <0 50 330000 + 51 100 990000 101 150 990000 - 151 450 3300000 - 451 600 1650000>; - qcom,jeita-fv-ranges = <0 50 4400000 - 51 100 4400000 + 151 450 3300000 + 451 600 1650000>; + qcom,jeita-fv-ranges = <0 50 4400000 + 51 100 4400000 101 150 4400000 - 151 450 4400000 - 451 600 4100000>; - qcom,dynamic-fv-ranges = <0 100 4400000 - 101 200 4380000 - 201 300 4360000 - 301 400 4340000 - 401 500 4340000>; + 151 450 4400000 + 451 600 4100000>; qcom,checksum = <0x1313>; qcom,gui-version = "PMI8998GUI - 2.0.0.58"; qcom,fg-profile-data = [ - A1 20 86 04 - 28 0B C6 05 - 01 1D 7B 01 - 47 05 43 03 - A3 17 C6 23 - A1 44 0E 5A - 8C 00 00 00 - 11 00 00 00 - 00 00 FB BC - CA CD D1 BA - 26 00 08 00 - A2 DB AA E4 - 43 FC 28 01 - 61 0C 6C 01 - 5C 06 41 32 - 21 06 09 20 - 27 00 14 00 - 96 20 97 04 - 34 0B A3 05 - D8 1C AD 02 - 9A 0C 98 0B - 90 18 B6 23 - 11 44 E1 5A - 76 00 00 00 - 0E 00 00 00 - 00 00 AE D5 - 2A CA 82 C3 - 1E 00 00 00 - 6E EA AA E4 - 8F FD B2 00 - 44 ED 03 03 - BD 03 48 22 - C3 33 CC FF - 07 10 00 00 - 33 0D 66 46 - 1E 00 40 00 - 60 01 0A FA - FF 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 + A1 20 86 04 + 28 0B C6 05 + 01 1D 7B 01 + 47 05 43 03 + A3 17 C6 23 + A1 44 0E 5A + 8C 00 00 00 + 11 00 00 00 + 00 00 FB BC + CA CD D1 BA + 26 00 08 00 + A2 DB AA E4 + 43 FC 28 01 + 61 0C 6C 01 + 5C 06 41 32 + 21 06 09 20 + 27 00 14 00 + 96 20 97 04 + 34 0B A3 05 + D8 1C AD 02 + 9A 0C 98 0B + 90 18 B6 23 + 11 44 E1 5A + 76 00 00 00 + 0E 00 00 00 + 00 00 AE D5 + 2A CA 82 C3 + 1E 00 00 00 + 6E EA AA E4 + 8F FD B2 00 + 44 ED 03 03 + BD 03 48 22 + C3 33 CC FF + 07 10 00 00 + 33 0D 66 46 + 1E 00 40 00 + 60 01 0A FA + FF 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 ]; }; diff --git a/arch/arm64/boot/dts/qcom/batterydata-e1-atl-3070mAh.dtsi b/arch/arm64/boot/dts/qcom/batterydata-e1-atl-3070mAh.dtsi index 13010ac50081..bf4bab293eae 100644 --- a/arch/arm64/boot/dts/qcom/batterydata-e1-atl-3070mAh.dtsi +++ b/arch/arm64/boot/dts/qcom/batterydata-e1-atl-3070mAh.dtsi @@ -1,78 +1,79 @@ qcom,e1_scud_3070mAh { + /* #3151767_Xiaomi_E1scud_3170mAh_averaged_MasterSlave_Oct18th2017*/ qcom,max-voltage-uv = <4400000>; - qcom,fastchg-current-ma = <3300>; + qcom,fastchg-current-ma = <3300>; qcom,nom-batt-capacity-mah = <3400>; qcom,fg-cc-cv-threshold-mv = <4390>; qcom,batt-id-kohm = <68>; qcom,battery-beta = <3380>; qcom,battery-type = "e1_scud"; - qcom,jeita-fcc-ranges = <0 50 330000 - 51 150 990000 - 151 450 3300000 - 451 600 1650000>; - qcom,jeita-fv-ranges = <0 50 4400000 - 51 150 4400000 - 151 450 4400000 - 451 600 4100000>; + qcom,jeita-fcc-ranges = <0 50 330000 + 51 150 990000 + 151 450 3300000 + 451 600 1650000>; + qcom,jeita-fv-ranges = <0 50 4400000 + 51 150 4400000 + 151 450 4400000 + 451 600 4100000>; qcom,checksum = <0x6E77>; qcom,gui-version = "PMI8998GUI - 2.0.0.58"; qcom,fg-profile-data = [ - 86 1F 90 05 - 94 0A 27 06 - 71 1D AD F5 - 1C 12 6A 14 - 8E 19 EC 1B - 5D 3D 62 4A - 52 00 00 00 - 16 00 00 00 - 00 00 4A BD - EA CD 2E C2 - 23 00 08 00 - E5 E2 F2 EC - E7 06 3E F2 - 8D 01 C3 12 - 6A 00 17 32 - 1E 06 09 20 - 27 00 14 00 - FE 1F 3D 05 - C4 0A 04 06 - 39 1D 33 FA - C9 F3 DA 0D - 34 19 CD 22 - 96 45 D1 52 - 59 00 00 00 - 0D 00 00 00 - 00 00 BD CC - 00 9C 9D C3 - 1D 00 00 00 - 56 F2 F2 EC - 58 07 BC E3 - 0F EC 33 02 - F9 EA D3 1A - AD 33 CC FF - 07 10 00 00 - 2F 0C 66 46 - 1D 00 40 00 - 5D 01 0A FA - FF 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 + 86 1F 90 05 + 94 0A 27 06 + 71 1D AD F5 + 1C 12 6A 14 + 8E 19 EC 1B + 5D 3D 62 4A + 52 00 00 00 + 16 00 00 00 + 00 00 4A BD + EA CD 2E C2 + 23 00 08 00 + E5 E2 F2 EC + E7 06 3E F2 + 8D 01 C3 12 + 6A 00 17 32 + 1E 06 09 20 + 27 00 14 00 + FE 1F 3D 05 + C4 0A 04 06 + 39 1D 33 FA + C9 F3 DA 0D + 34 19 CD 22 + 96 45 D1 52 + 59 00 00 00 + 0D 00 00 00 + 00 00 BD CC + 00 9C 9D C3 + 1D 00 00 00 + 56 F2 F2 EC + 58 07 BC E3 + 0F EC 33 02 + F9 EA D3 1A + AD 33 CC FF + 07 10 00 00 + 2F 0C 66 46 + 1D 00 40 00 + 5D 01 0A FA + FF 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 ]; }; diff --git a/arch/arm64/boot/dts/qcom/batterydata-e1-atl-3400mAh.dtsi b/arch/arm64/boot/dts/qcom/batterydata-e1-atl-3400mAh.dtsi index c8e06b8fad6e..b382a6f387d6 100644 --- a/arch/arm64/boot/dts/qcom/batterydata-e1-atl-3400mAh.dtsi +++ b/arch/arm64/boot/dts/qcom/batterydata-e1-atl-3400mAh.dtsi @@ -1,5 +1,6 @@ qcom,e1_atl_3400mAh { qcom, = <24>; + /* #3331499_Xiaomi_BM3Escud_3400mAh_averaged_MasterSlave_Feb20th2018*/ qcom,max-voltage-uv = <4400000>; qcom,nom-batt-capacity-mah = <3400>; qcom,batt-id-kohm = <68>; @@ -8,24 +9,19 @@ qcom,e1_atl_3400mAh { qcom,battery-type = "e1_atl_3400mAh"; qcom,fastchg-current-ma = <3300>; qcom,jeita-fcc-ranges = <0 50 330000 - 51 100 990000 - 101 150 1650000 - 151 450 3300000 - 451 600 1650000>; + 51 100 990000 + 101 150 1650000 + 151 450 3300000 + 451 600 1650000>; qcom,jeita-fv-ranges = <0 50 4400000 - 51 100 4400000 - 101 150 4400000 - 151 450 4400000 - 451 600 4100000>; - qcom,dynamic-fv-ranges = <0 100 4400000 - 101 200 4380000 - 201 300 4360000 - 301 400 4340000 - 401 500 4340000>; + 51 100 4400000 + 101 150 4400000 + 151 450 4400000 + 451 600 4100000>; qcom,checksum = <0xC3C7>; qcom,gui-version = "PMI8998GUI - 2.0.0.58"; qcom,fg-profile-data = [ - F0 1E 58 06 + F0 1E 58 06 CB 03 B7 FD D9 1C 03 02 9C 0D C5 0A diff --git a/arch/arm64/boot/dts/qcom/batterydata-e1-coslight-3070mAh.dtsi b/arch/arm64/boot/dts/qcom/batterydata-e1-coslight-3070mAh.dtsi index 3f04921a6e21..f598d3d46292 100644 --- a/arch/arm64/boot/dts/qcom/batterydata-e1-coslight-3070mAh.dtsi +++ b/arch/arm64/boot/dts/qcom/batterydata-e1-coslight-3070mAh.dtsi @@ -1,78 +1,79 @@ qcom,e1_coslight_3070mAh { + /* #3124728_Xiaomi_E1cos_3170mAh_averaged_MasterSlave_Sept25th2017*/ qcom,max-voltage-uv = <4400000>; - qcom,fastchg-current-ma = <3300>; + qcom,fastchg-current-ma = <3300>; qcom,nom-batt-capacity-mah = <3400>; qcom,fg-cc-cv-threshold-mv = <4390>; qcom,batt-id-kohm = <100>; qcom,battery-beta = <3380>; qcom,battery-type = "e1_coslight"; - qcom,jeita-fcc-ranges = <0 50 330000 - 51 150 990000 - 151 450 3300000 - 451 600 1650000>; - qcom,jeita-fv-ranges = <0 50 4400000 - 51 150 4400000 - 151 450 4400000 - 451 600 4100000>; + qcom,jeita-fcc-ranges = <0 50 330000 + 51 150 990000 + 151 450 3300000 + 451 600 1650000>; + qcom,jeita-fv-ranges = <0 50 4400000 + 51 150 4400000 + 151 450 4400000 + 451 600 4100000>; qcom,checksum = <0xDF1B>; qcom,gui-version = "PMI8998GUI - 2.0.0.58"; qcom,fg-profile-data = [ - 40 1F F1 05 - 35 0A 25 FD - 6C 1D 6D F5 - 39 12 2E 14 - 80 18 26 23 - 41 45 46 53 - 55 00 00 00 - 0E 00 00 00 - 00 00 8F C3 - 2D CC 00 AC - 35 00 08 00 - F1 DA B3 E4 - 29 05 A3 FB - 89 0D EF 03 - 52 E5 BD 23 - 39 06 09 20 - 27 00 14 00 - AA 1F C3 05 - 40 0A 33 FD - 57 1D 95 EB - 73 0A 34 15 - 18 19 F0 22 - 67 45 1E 53 - 55 00 00 00 - 0D 00 00 00 - 00 00 B0 CC - 27 C3 0F BC - 23 00 00 00 - 91 EA B3 E4 - D1 FC CF 00 - 55 F5 F3 01 - 63 02 E9 23 - CB 33 CC FF - 07 10 00 00 - 71 0C 66 46 - 23 00 40 00 - 5E 01 0A FA - FF 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 + 40 1F F1 05 + 35 0A 25 FD + 6C 1D 6D F5 + 39 12 2E 14 + 80 18 26 23 + 41 45 46 53 + 55 00 00 00 + 0E 00 00 00 + 00 00 8F C3 + 2D CC 00 AC + 35 00 08 00 + F1 DA B3 E4 + 29 05 A3 FB + 89 0D EF 03 + 52 E5 BD 23 + 39 06 09 20 + 27 00 14 00 + AA 1F C3 05 + 40 0A 33 FD + 57 1D 95 EB + 73 0A 34 15 + 18 19 F0 22 + 67 45 1E 53 + 55 00 00 00 + 0D 00 00 00 + 00 00 B0 CC + 27 C3 0F BC + 23 00 00 00 + 91 EA B3 E4 + D1 FC CF 00 + 55 F5 F3 01 + 63 02 E9 23 + CB 33 CC FF + 07 10 00 00 + 71 0C 66 46 + 23 00 40 00 + 5E 01 0A FA + FF 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 ]; }; diff --git a/arch/arm64/boot/dts/qcom/batterydata-e1-coslight-3400mAh.dtsi b/arch/arm64/boot/dts/qcom/batterydata-e1-coslight-3400mAh.dtsi index b87378493572..8dc6d7da3408 100644 --- a/arch/arm64/boot/dts/qcom/batterydata-e1-coslight-3400mAh.dtsi +++ b/arch/arm64/boot/dts/qcom/batterydata-e1-coslight-3400mAh.dtsi @@ -1,5 +1,6 @@ qcom,e1_coslight_3400mAh { qcom, = <24>; + /* #3351164_Xiaomi_BM3Ecos_3400mAh_averaged_MasterSlave_Feb20th2018*/ qcom,max-voltage-uv = <4400000>; qcom,nom-batt-capacity-mah = <3400>; qcom,batt-id-kohm = <100>; @@ -8,24 +9,19 @@ qcom,e1_coslight_3400mAh { qcom,battery-type = "e1_coslight_3400mAh"; qcom,fastchg-current-ma = <3300>; qcom,jeita-fcc-ranges = <0 50 330000 - 51 100 990000 - 101 150 1650000 - 151 450 3300000 - 451 600 1650000>; + 51 100 990000 + 101 150 1650000 + 151 450 3300000 + 451 600 1650000>; qcom,jeita-fv-ranges = <0 50 4400000 - 51 100 4400000 - 101 150 4400000 - 151 450 4400000 - 451 600 4100000>; - qcom,dynamic-fv-ranges = <0 100 4400000 - 101 200 4380000 - 201 300 4360000 - 301 400 4340000 - 401 500 4340000>; + 51 100 4400000 + 101 150 4400000 + 151 450 4400000 + 451 600 4100000>; qcom,checksum = <0xF35D>; qcom,gui-version = "PMI8998GUI - 2.0.0.58"; qcom,fg-profile-data = [ - E4 1E CB FC + E4 1E CB FC AC 03 EF 06 D7 1C 10 02 79 0D EF 0A diff --git a/arch/arm64/boot/dts/qcom/batterydata-e10-atl-4000mAh.dtsi b/arch/arm64/boot/dts/qcom/batterydata-e10-atl-4000mAh.dtsi index 87acf4569cea..bfc1cadb850c 100644 --- a/arch/arm64/boot/dts/qcom/batterydata-e10-atl-4000mAh.dtsi +++ b/arch/arm64/boot/dts/qcom/batterydata-e10-atl-4000mAh.dtsi @@ -1,5 +1,6 @@ qcom,e10_atl_4000mah { qcom, = <24>; + /* #3410356_Xiaomi_E10atl_4000mAh_averaged_MasterSlave_Apr10th2018*/ qcom,max-voltage-uv = <4400000>; qcom,fastchg-current-ma = <2800>; qcom,nom-batt-capacity-mah = <4000>; @@ -17,70 +18,65 @@ qcom,e10_atl_4000mah { 101 150 4400000 151 450 4400000 451 600 4100000>; - qcom,dynamic-fv-ranges = <0 100 4400000 - 101 200 4380000 - 201 300 4360000 - 301 400 4340000 - 401 500 4340000>; qcom,checksum = <0xA0E7>; qcom,gui-version = "PMI8998GUI - 2.0.0.58"; qcom,fg-profile-data = [ - A1 1E 8B FD - 10 03 44 07 - D6 1C 18 02 - 6D 0D 05 0B - F1 17 CE 23 - 4F 44 74 5A - 67 00 00 00 - 10 00 00 00 - 00 00 27 B2 - 74 CD EC BA - 1C 00 08 00 - F4 E2 7F ED - 41 06 15 FA - 64 0D 31 0A - E2 EC 57 32 - 24 06 09 20 - 27 00 14 00 - 94 1F D2 05 - 42 0A 8B 06 - AE 1C 4F 03 - AB 15 8C 12 - 73 18 0E 2A - 95 4D F3 5B - 65 00 00 00 - 0D 00 00 00 - 00 00 EC D5 - 6C CA 47 8B - 15 00 00 00 - 8A EB 7F ED - FF FD CF EB - EF EC C0 02 - C7 F4 00 1B - A1 33 CC FF - 07 10 00 00 - 94 0F 66 46 - 15 00 40 00 - 91 01 0A FA - FF 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 + A1 1E 8B FD + 10 03 44 07 + D6 1C 18 02 + 6D 0D 05 0B + F1 17 CE 23 + 4F 44 74 5A + 67 00 00 00 + 10 00 00 00 + 00 00 27 B2 + 74 CD EC BA + 1C 00 08 00 + F4 E2 7F ED + 41 06 15 FA + 64 0D 31 0A + E2 EC 57 32 + 24 06 09 20 + 27 00 14 00 + 94 1F D2 05 + 42 0A 8B 06 + AE 1C 4F 03 + AB 15 8C 12 + 73 18 0E 2A + 95 4D F3 5B + 65 00 00 00 + 0D 00 00 00 + 00 00 EC D5 + 6C CA 47 8B + 15 00 00 00 + 8A EB 7F ED + FF FD CF EB + EF EC C0 02 + C7 F4 00 1B + A1 33 CC FF + 07 10 00 00 + 94 0F 66 46 + 15 00 40 00 + 91 01 0A FA + FF 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 ]; }; diff --git a/arch/arm64/boot/dts/qcom/batterydata-e10-cos-4000mAh.dtsi b/arch/arm64/boot/dts/qcom/batterydata-e10-cos-4000mAh.dtsi index 3486d403fdb9..b900183d329e 100644 --- a/arch/arm64/boot/dts/qcom/batterydata-e10-cos-4000mAh.dtsi +++ b/arch/arm64/boot/dts/qcom/batterydata-e10-cos-4000mAh.dtsi @@ -1,5 +1,6 @@ qcom,e10_cos_4000mah { qcom, = <24>; + /* #3434841_Xiaomi_E10cos_4000mAh_averaged_MasterSlave_Apr24th2018*/ qcom,max-voltage-uv = <4400000>; qcom,fastchg-current-ma = <2800>; qcom,nom-batt-capacity-mah = <4000>; @@ -8,79 +9,74 @@ qcom,e10_cos_4000mah { qcom,battery-beta = <3380>; qcom,battery-type = "e10_cos_4000mAh"; qcom,jeita-fcc-ranges = <0 50 390000 - 51 100 1170000 - 101 150 1170000 - 151 450 2800000 - 451 600 1950000>; + 51 100 1170000 + 101 150 1170000 + 151 450 2800000 + 451 600 1950000>; qcom,jeita-fv-ranges = <0 50 4400000 - 51 100 4400000 - 101 150 4400000 - 151 450 4400000 - 451 600 4100000>; - qcom,dynamic-fv-ranges = <0 100 4400000 - 101 200 4380000 - 201 300 4360000 - 301 400 4340000 - 401 500 4340000>; + 51 100 4400000 + 101 150 4400000 + 151 450 4400000 + 451 600 4100000>; qcom,checksum = <0x0920>; qcom,gui-version = "PMI8998GUI - 2.0.0.58"; qcom,fg-profile-data = [ - 3F 1F FC 05 - 29 0A A5 06 - E8 1C E4 01 - D0 0D 8D 0A - 98 17 0E 2A - 00 44 A9 5A - 73 00 00 00 - 10 00 00 00 - 00 00 AC C5 - 64 C4 96 C2 - 20 00 08 00 - 0C DB 6E E5 - 68 05 D2 01 - E2 14 F6 05 - 11 EC E7 23 - 31 06 09 20 - 27 00 14 00 - E0 1F 63 05 - A4 0A 24 06 - C1 1C 11 03 - E0 15 53 12 - 82 18 F8 23 - C0 4D 8B 5B - 69 00 00 00 - 0D 00 00 00 - 00 00 40 CC - 10 CA 78 BC - 17 00 00 00 - 9F E3 6E E5 - 6D 06 04 01 - D7 06 8F FB - EE F2 BC 1B - BA 33 CC FF - 07 10 00 00 - 9C 0F 66 46 - 17 00 40 00 - 6E 01 0A FA - FF 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 + 3F 1F FC 05 + 29 0A A5 06 + E8 1C E4 01 + D0 0D 8D 0A + 98 17 0E 2A + 00 44 A9 5A + 73 00 00 00 + 10 00 00 00 + 00 00 AC C5 + 64 C4 96 C2 + 20 00 08 00 + 0C DB 6E E5 + 68 05 D2 01 + E2 14 F6 05 + 11 EC E7 23 + 31 06 09 20 + 27 00 14 00 + E0 1F 63 05 + A4 0A 24 06 + C1 1C 11 03 + E0 15 53 12 + 82 18 F8 23 + C0 4D 8B 5B + 69 00 00 00 + 0D 00 00 00 + 00 00 40 CC + 10 CA 78 BC + 17 00 00 00 + 9F E3 6E E5 + 6D 06 04 01 + D7 06 8F FB + EE F2 BC 1B + BA 33 CC FF + 07 10 00 00 + 9C 0F 66 46 + 17 00 40 00 + 6E 01 0A FA + FF 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 ]; }; diff --git a/arch/arm64/boot/dts/qcom/batterydata-e5-cos-3200mAh.dtsi b/arch/arm64/boot/dts/qcom/batterydata-e5-cos-3200mAh.dtsi index 3682066908fe..b177d21308fa 100644 --- a/arch/arm64/boot/dts/qcom/batterydata-e5-cos-3200mAh.dtsi +++ b/arch/arm64/boot/dts/qcom/batterydata-e5-cos-3200mAh.dtsi @@ -1,5 +1,6 @@ qcom,e5_cos_3200mAh { qcom, = <24>; + /* #3543435_Xiaomi_E5cos_3200mAh_averaged_MasterSlave_Jul23rd2018*/ qcom,max-voltage-uv = <4400000>; qcom,fg-cc-cv-threshold-mv = <4390>; qcom,nom-batt-capacity-mah = <3200>; @@ -9,78 +10,73 @@ qcom,e5_cos_3200mAh { qcom,battery-type = "e5_cos_3200mAh"; qcom,fastchg-current-ma = <3100>; qcom,jeita-fcc-ranges = <0 50 310000 - 51 100 930000 - 101 150 2170000 - 151 450 3100000 - 451 600 1550000>; + 51 100 930000 + 101 150 2170000 + 151 450 3100000 + 451 600 1550000>; qcom,jeita-fv-ranges = <0 50 4400000 - 51 100 4400000 - 101 150 4400000 - 151 450 4400000 - 451 600 4100000>; - qcom,dynamic-fv-ranges = <0 100 4400000 - 101 200 4380000 - 201 300 4360000 - 301 400 4340000 - 401 500 4340000>; + 51 100 4400000 + 101 150 4400000 + 151 450 4400000 + 451 600 4100000>; qcom,checksum = <0x6F2A>; qcom,gui-version = "PMI8998GUI - 2.0.0.58"; qcom,fg-profile-data = [ - CB 1E 45 FD - 15 03 66 F5 - E4 1C E2 01 - D9 0D 7B 0A - 8F 17 FF 23 - 3A 44 6F 5A - 70 00 00 00 - 10 00 00 00 - 00 00 3D B5 - 4D CD 89 BB - 1D 00 08 00 - A6 DA C7 07 - 13 FC 58 01 - E7 F5 65 12 - 7D 06 D0 2A - 2E 06 09 20 - 27 00 14 00 - 5F 1F 43 FC - D8 03 ED FD - B4 1C 2C 03 - C8 15 6A 12 - 75 18 D7 23 - E8 4D 2D 5B - 65 00 00 00 - 0E 00 00 00 - 00 00 40 CC - 5F CA 78 BC - 17 00 00 00 - 5D 00 C7 07 - 7D FD C9 00 - 9A EC BD 02 - 17 02 76 23 - CB 33 CC FF - 07 10 00 00 - 76 0C 66 46 - 17 00 40 00 - 71 01 0A FA - FF 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 + CB 1E 45 FD + 15 03 66 F5 + E4 1C E2 01 + D9 0D 7B 0A + 8F 17 FF 23 + 3A 44 6F 5A + 70 00 00 00 + 10 00 00 00 + 00 00 3D B5 + 4D CD 89 BB + 1D 00 08 00 + A6 DA C7 07 + 13 FC 58 01 + E7 F5 65 12 + 7D 06 D0 2A + 2E 06 09 20 + 27 00 14 00 + 5F 1F 43 FC + D8 03 ED FD + B4 1C 2C 03 + C8 15 6A 12 + 75 18 D7 23 + E8 4D 2D 5B + 65 00 00 00 + 0E 00 00 00 + 00 00 40 CC + 5F CA 78 BC + 17 00 00 00 + 5D 00 C7 07 + 7D FD C9 00 + 9A EC BD 02 + 17 02 76 23 + CB 33 CC FF + 07 10 00 00 + 76 0C 66 46 + 17 00 40 00 + 71 01 0A FA + FF 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 ]; }; diff --git a/arch/arm64/boot/dts/qcom/batterydata-e5-sun-3200mAh.dtsi b/arch/arm64/boot/dts/qcom/batterydata-e5-sun-3200mAh.dtsi index c3b5e4f81180..7c8db9118f34 100644 --- a/arch/arm64/boot/dts/qcom/batterydata-e5-sun-3200mAh.dtsi +++ b/arch/arm64/boot/dts/qcom/batterydata-e5-sun-3200mAh.dtsi @@ -1,5 +1,6 @@ qcom,e5_sun_3200mAh { qcom, = <24>; + /* #3529269_Xiaomi_E5sun_3220mAh_averaged_MasterSlave_Jul18th2018*/ qcom,max-voltage-uv = <4400000>; qcom,fg-cc-cv-threshold-mv = <4390>; qcom,nom-batt-capacity-mah = <3200>; @@ -9,78 +10,73 @@ qcom,e5_sun_3200mAh { qcom,battery-type = "e5_sun_3200mAh"; qcom,fastchg-current-ma = <3100>; qcom,jeita-fcc-ranges = <0 50 310000 - 51 100 930000 - 101 150 2170000 - 151 450 3100000 - 451 600 1550000>; + 51 100 930000 + 101 150 2170000 + 151 450 3100000 + 451 600 1550000>; qcom,jeita-fv-ranges = <0 50 4400000 - 51 100 4400000 - 101 150 4400000 - 151 450 4400000 - 451 600 4100000>; - qcom,dynamic-fv-ranges = <0 100 4400000 - 101 200 4380000 - 201 300 4360000 - 301 400 4340000 - 401 500 4340000>; + 51 100 4400000 + 101 150 4400000 + 151 450 4400000 + 451 600 4100000>; qcom,checksum = <0x2DDD>; qcom,gui-version = "PMI8998GUI - 2.0.0.58"; qcom,fg-profile-data = [ - DB 1E 15 FD - 73 03 3B F4 - E7 1C A9 FB - 10 04 4C 0A - 5F 17 03 2A - 4F 44 50 5A - 72 00 00 00 - 11 00 00 00 - 00 00 E1 BC - 64 C4 89 C2 - 21 00 08 00 - F8 DA FE ED - DD FC CF F3 - 2B FA 5D 13 - 81 FD 6A 2A - 24 06 09 20 - 27 00 14 00 - 51 1F 53 FC - 06 0A 79 FD - CB 1C DF 02 - 2C 0C 1C 12 - 7F 18 82 23 - 8A 44 5E 5A - 67 00 00 00 - 0F 00 00 00 - 00 00 F9 07 - 96 C2 47 8B - 1B 00 00 00 - 69 00 FE ED - 03 F4 12 F2 - E1 06 09 FB - 25 00 FD 1A - AE 33 CC FF - 07 10 00 00 - 50 0C 66 46 - 1B 00 40 00 - 7D 01 0A FA - FF 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 + DB 1E 15 FD + 73 03 3B F4 + E7 1C A9 FB + 10 04 4C 0A + 5F 17 03 2A + 4F 44 50 5A + 72 00 00 00 + 11 00 00 00 + 00 00 E1 BC + 64 C4 89 C2 + 21 00 08 00 + F8 DA FE ED + DD FC CF F3 + 2B FA 5D 13 + 81 FD 6A 2A + 24 06 09 20 + 27 00 14 00 + 51 1F 53 FC + 06 0A 79 FD + CB 1C DF 02 + 2C 0C 1C 12 + 7F 18 82 23 + 8A 44 5E 5A + 67 00 00 00 + 0F 00 00 00 + 00 00 F9 07 + 96 C2 47 8B + 1B 00 00 00 + 69 00 FE ED + 03 F4 12 F2 + E1 06 09 FB + 25 00 FD 1A + AE 33 CC FF + 07 10 00 00 + 50 0C 66 46 + 1B 00 40 00 + 7D 01 0A FA + FF 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 ]; }; diff --git a/arch/arm64/boot/dts/qcom/batterydata-e8-atl-3000mAh.dtsi b/arch/arm64/boot/dts/qcom/batterydata-e8-atl-3000mAh.dtsi index 0e76711884a7..f15075997a36 100644 --- a/arch/arm64/boot/dts/qcom/batterydata-e8-atl-3000mAh.dtsi +++ b/arch/arm64/boot/dts/qcom/batterydata-e8-atl-3000mAh.dtsi @@ -1,6 +1,7 @@ qcom,e1_atl_3000mAh { qcom, = <24>; + /* #3378762_Xiaomi_E8atl_3000mAh_averaged_MasterSlave_Mar26th2018*/ qcom,max-voltage-uv = <4400000>; qcom,nom-batt-capacity-mah = <3000>; qcom,batt-id-kohm = <68>; @@ -9,78 +10,73 @@ qcom,e1_atl_3000mAh { qcom,battery-type = "e8_atl_3000mAh"; qcom,fastchg-current-ma = <2900>; qcom,jeita-fcc-ranges = <0 50 290000 - 51 100 870000 - 101 150 1450000 - 151 450 2900000 - 451 600 1450000>; + 51 100 870000 + 101 150 1450000 + 151 450 2900000 + 451 600 1450000>; qcom,jeita-fv-ranges = <0 50 4400000 - 51 100 4400000 - 101 150 4400000 - 151 450 4400000 - 451 600 4100000>; - qcom,dynamic-fv-ranges = <0 100 4400000 - 101 200 4380000 - 201 300 4360000 - 301 400 4340000 - 401 500 4340000>; - qcom,checksum = <0x572F>; + 51 100 4400000 + 101 150 4400000 + 151 450 4400000 + 451 600 4100000>; + qcom,checksum = <0x2D2B>; qcom,gui-version = "PMI8998GUI - 2.0.0.58"; qcom,fg-profile-data = [ - 7F 1F D5 05 - 34 0A A9 06 - F5 1C A8 01 - B9 04 CD 03 - D6 17 B9 23 - 96 44 24 5A - 7F 00 00 00 - 11 00 00 00 - 00 00 EE C5 - 64 C4 6F BB - 25 00 08 00 - EA E2 A5 07 - 63 FD A9 00 - 84 0D C6 0B - 10 05 68 32 - 1C 06 09 20 - 27 00 14 00 - 61 1F 0B 06 - 1D 0A 57 FD - B6 1C 31 03 - BF 15 82 12 - 76 18 D8 23 - E7 4D 2E 5B - 63 00 00 00 - 0E 00 00 00 - 00 00 F9 07 - 5B C3 47 8B - 1F 00 00 00 - 1F F2 A5 07 - 9F F4 A1 EA - 13 F4 31 FA - 03 00 A6 1A - AA 33 CC FF - 07 10 00 00 - B7 0B 66 46 - 1F 00 40 00 - 4E 01 0A FA - FF 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 + 7F 1F D5 05 + 34 0A A9 06 + F5 1C A8 01 + B9 04 CD 03 + D6 17 B9 23 + 96 44 24 5A + 7F 00 00 00 + 11 00 00 00 + 00 00 EE C5 + 64 C4 6F BB + 25 00 08 00 + EA E2 A5 07 + 63 FD A9 00 + 32 0C 59 FB + 10 05 68 32 + 1C 06 09 20 + 27 00 14 00 + 61 1F 0B 06 + 1D 0A 57 FD + B6 1C 31 03 + BF 15 82 12 + 76 18 D8 23 + E7 4D 2E 5B + 63 00 00 00 + 0E 00 00 00 + 00 00 F9 07 + 5B C3 47 8B + 1F 00 00 00 + 1F F2 A5 07 + 9F F4 A1 EA + 13 F4 31 FA + 03 00 A6 1A + AA 33 CC FF + 07 10 00 00 + B7 0B 66 46 + 1F 00 40 00 + 4E 01 0A FA + FF 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 ]; }; diff --git a/arch/arm64/boot/dts/qcom/batterydata-e8-coslight-3000mAh.dtsi b/arch/arm64/boot/dts/qcom/batterydata-e8-coslight-3000mAh.dtsi index f19460a81bfe..d363770a250e 100644 --- a/arch/arm64/boot/dts/qcom/batterydata-e8-coslight-3000mAh.dtsi +++ b/arch/arm64/boot/dts/qcom/batterydata-e8-coslight-3000mAh.dtsi @@ -1,5 +1,6 @@ qcom,e1_coslight_3070mAh { + /* #3124728_Xiaomi_E1cos_3170mAh_averaged_MasterSlave_Sept25th2017*/ qcom,max-voltage-uv = <4400000>; qcom,nom-batt-capacity-mah = <3000>; qcom,batt-id-kohm = <100>; @@ -8,78 +9,73 @@ qcom,e1_coslight_3070mAh { qcom,battery-type = "e8_coslight_3000mAh"; qcom,fastchg-current-ma = <2900>; qcom,jeita-fcc-ranges = <0 50 290000 - 51 100 870000 - 101 150 1450000 - 151 450 2900000 - 451 600 1450000>; + 51 100 870000 + 101 150 1450000 + 151 450 2900000 + 451 600 1450000>; qcom,jeita-fv-ranges = <0 50 4400000 - 51 100 4400000 - 101 150 4400000 - 151 450 4400000 - 451 600 4100000>; - qcom,dynamic-fv-ranges = <0 100 4400000 - 101 200 4380000 - 201 300 4360000 - 301 400 4340000 - 401 500 4340000>; - qcom,checksum = <0x572F>; + 51 100 4400000 + 101 150 4400000 + 151 450 4400000 + 451 600 4100000>; + qcom,checksum = <0xDF1B>; qcom,gui-version = "PMI8998GUI - 2.0.0.58"; qcom,fg-profile-data = [ - 7F 1F D5 05 - 34 0A A9 06 - F5 1C A8 01 - B9 04 CD 03 - D6 17 B9 23 - 96 44 24 5A - 7F 00 00 00 - 11 00 00 00 - 00 00 EE C5 - 64 C4 6F BB - 25 00 08 00 - EA E2 A5 07 - 63 FD A9 00 - 84 0D C6 0B - 10 05 68 32 - 1C 06 09 20 - 27 00 14 00 - 61 1F 0B 06 - 1D 0A 57 FD - B6 1C 31 03 - BF 15 82 12 - 76 18 D8 23 - E7 4D 2E 5B - 63 00 00 00 - 0E 00 00 00 - 00 00 F9 07 - 5B C3 47 8B - 1F 00 00 00 - 1F F2 A5 07 - 9F F4 A1 EA - 13 F4 31 FA - 03 00 A6 1A - AA 33 CC FF - 07 10 00 00 - B7 0B 66 46 - 1F 00 40 00 - 4E 01 0A FA - FF 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 + 40 1F F1 05 + 35 0A 25 FD + 6C 1D 6D F5 + 39 12 2E 14 + 80 18 26 23 + 41 45 46 53 + 55 00 00 00 + 0E 00 00 00 + 00 00 8F C3 + 2D CC 00 AC + 35 00 08 00 + F1 DA B3 E4 + 29 05 A3 FB + 89 0D EF 03 + 52 E5 BD 23 + 39 06 09 20 + 27 00 14 00 + AA 1F C3 05 + 40 0A 33 FD + 57 1D 95 EB + 73 0A 34 15 + 18 19 F0 22 + 67 45 1E 53 + 55 00 00 00 + 0D 00 00 00 + 00 00 B0 CC + 27 C3 0F BC + 23 00 00 00 + 91 EA B3 E4 + D1 FC CF 00 + 55 F5 F3 01 + 63 02 E9 23 + CB 33 CC FF + 07 10 00 00 + 71 0C 66 46 + 23 00 40 00 + 5E 01 0A FA + FF 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 ]; }; diff --git a/arch/arm64/boot/dts/qcom/batterydata-itech-3020mAh.dtsi b/arch/arm64/boot/dts/qcom/batterydata-itech-3020mAh.dtsi index 4f71ff9d1b6b..8bae4f902a6c 100644 --- a/arch/arm64/boot/dts/qcom/batterydata-itech-3020mAh.dtsi +++ b/arch/arm64/boot/dts/qcom/batterydata-itech-3020mAh.dtsi @@ -1,4 +1,5 @@ /* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -19,73 +20,73 @@ qcom,itech-3020mah { qcom,battery-beta = <3380>; qcom,battery-type = "itech_3000mah"; qcom,jeita-fcc-ranges = <0 50 300000 - 51 100 925000 - 101 150 1550000 - 151 450 3100000 - 451 600 1550000>; + 51 100 925000 + 101 150 1550000 + 151 450 3100000 + 451 600 1550000>; qcom,jeita-fv-ranges = <0 50 4400000 - 51 100 4400000 - 101 150 4400000 - 151 450 4400000 - 451 600 4100000>; + 51 100 4400000 + 101 150 4400000 + 151 450 4400000 + 451 600 4100000>; qcom,checksum = <0x8E3D>; qcom,gui-version = "PMI8998GUI - 2.0.0.58"; qcom,fg-profile-data = [ - 0A 1F 3A 06 - 00 0A C7 06 - D4 1C 0C 02 - 98 0D C7 0A - 95 17 D6 23 - 7F 44 31 5A - 6F 00 00 00 - 11 00 00 00 - 00 00 D8 BB - 61 CD DF A2 - 26 00 08 00 - AB EA 51 EC - D1 FC BB F3 - 58 0C F3 FA - 62 06 BB 32 - 1F 06 09 20 - 27 00 14 00 - 18 20 25 05 - D4 0A F4 05 - C8 1C ED 02 - 1A 0C 19 12 - 91 18 AC 23 - 20 44 D6 5A - 6E 00 00 00 - 0E 00 00 00 - 00 00 86 D5 - 3E CA 24 CA - 1E 00 00 00 - 5B F2 51 EC - 7B F4 22 EB - 7A 07 87 FB - 69 BA BC 1B - AB 33 CC FF - 07 10 00 00 - 3E 0D 66 46 - 1E 00 40 00 - 66 01 0A FA - FF 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 - 00 00 00 00 + 0A 1F 3A 06 + 00 0A C7 06 + D4 1C 0C 02 + 98 0D C7 0A + 95 17 D6 23 + 7F 44 31 5A + 6F 00 00 00 + 11 00 00 00 + 00 00 D8 BB + 61 CD DF A2 + 26 00 08 00 + AB EA 51 EC + D1 FC BB F3 + 58 0C F3 FA + 62 06 BB 32 + 1F 06 09 20 + 27 00 14 00 + 18 20 25 05 + D4 0A F4 05 + C8 1C ED 02 + 1A 0C 19 12 + 91 18 AC 23 + 20 44 D6 5A + 6E 00 00 00 + 0E 00 00 00 + 00 00 86 D5 + 3E CA 24 CA + 1E 00 00 00 + 5B F2 51 EC + 7B F4 22 EB + 7A 07 87 FB + 69 BA BC 1B + AB 33 CC FF + 07 10 00 00 + 3E 0D 66 46 + 1E 00 40 00 + 66 01 0A FA + FF 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 + 00 00 00 00 ]; }; diff --git a/arch/arm64/boot/dts/qcom/beryllium-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/beryllium-audio-overlay.dtsi index 86db315b8d8d..7a16948a2568 100644 --- a/arch/arm64/boot/dts/qcom/beryllium-audio-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/beryllium-audio-overlay.dtsi @@ -53,25 +53,6 @@ qcom,lpi-gpios; }; -&slim_aud { - tavil_codec { - swr_master { - wsa881x_0211: wsa881x@20170211 { - status = "disabled"; - }; - wsa881x_0212: wsa881x@20170212 { - status = "disabled"; - }; - wsa881x_0213: wsa881x@21170213 { - status = "disabled"; - }; - wsa881x_0214: wsa881x@21170214 { - status = "disabled"; - }; - }; - }; -}; - &soc { sbu_uart_en: msm_cdc_pinctrl@49 { compatible = "qcom,msm-cdc-pinctrl"; diff --git a/arch/arm64/boot/dts/qcom/beryllium-p0.dtsi b/arch/arm64/boot/dts/qcom/beryllium-p0.dtsi index 5238f30fb16e..ebc1769a41aa 100644 --- a/arch/arm64/boot/dts/qcom/beryllium-p0.dtsi +++ b/arch/arm64/boot/dts/qcom/beryllium-p0.dtsi @@ -16,6 +16,7 @@ #include "sdm845-pmic-overlay.dtsi" #include "sdm845-pinctrl-overlay.dtsi" #include "sdm845-xiaomi-common.dtsi" +//#include "beryllium-camera-sensor-mtp.dtsi" #include "beryllium-p0-camera-sensor-mtp.dtsi" &qupv3_se10_i2c { @@ -192,20 +193,20 @@ }; &pmi8998_haptics { - qcom,vmax-mv = <2812>; - qcom,lra-auto-mode; - qcom,overdrive; - qcom,wave-play-rate-us = <4878>; - qcom,wave-shape = "sine"; - qcom,lra-high-z = "opt1"; - qcom,lra-auto-res-mode = "qwd"; - qcom,lra-res-cal-period = <4>; - qcom,effect-max = <3>; - qcom,effect-arry = [3e 3e be a0 00 00 00 00 - 3e 3e 3e be be 00 00 00 - 3e 3e 3e 3e be be a0 90]; - qcom,play-mode = "buffer"; - status = "okay"; + qcom,vmax-mv = <2812>; + qcom,lra-auto-mode; + qcom,overdrive; + qcom,wave-play-rate-us = <4878>; + qcom,wave-shape = "sine"; + qcom,lra-high-z = "opt1"; + qcom,lra-auto-res-mode = "qwd"; + qcom,lra-res-cal-period = <4>; + qcom,effect-max = <3>; + qcom,effect-arry = [3e 3e be a0 00 00 00 00 + 3e 3e 3e be be 00 00 00 + 3e 3e 3e 3e be be a0 90]; + qcom,play-mode = "buffer"; + status = "okay"; }; &mdss_mdp { @@ -273,9 +274,9 @@ }; &pmi8998_switch2 { - pinctrl-names = "led_enable", "led_disable"; - pinctrl-0 = <&flash_led3_iris_en>; - pinctrl-1 = <&flash_led3_iris_dis>; + pinctrl-names = "led_enable", "led_disable"; + pinctrl-0 = <&flash_led3_iris_en>; + pinctrl-1 = <&flash_led3_iris_dis>; }; &vendor{ @@ -297,6 +298,15 @@ &pmi8998_gpios { lm3644_pwm { lm3644_pwm_default: lm3644_pwm_default { + //pins = "gpio2"; + //function = "func1"; + //bias-disable; + //output-low; + //input-disable; + //drive-push-pull; + //qcom,drive-strength = <2>; + //power-source = <0>; + //temply disable it pins = "gpio2"; function = "normal"; bias-high-impedance; @@ -317,8 +327,7 @@ qcom,fcc-hot-temp-delta = <1400000>; qcom,fcc-cool-temp-delta = <1960000>; qcom,auto-recharge-soc; - qcom,sw-jeita-enable; - qcom,dynamic-fv-enable; + qcom,sw-jeita-enable; qcom,thermal-mitigation = <1800000 1600000 1400000 1200000 1000000 1000000 1000000>; qcom,thermal-mitigation-dcp @@ -353,8 +362,6 @@ qcom,fg-esr-clamp-mohms = <60>; qcom,fg-batt-temp-delta = <6>; qcom,battery-data = <&mtp_batterydata>; - qcom,slope-limit-temp-threshold = <100>; - qcom,slope-limit-coeffs = <10 11 12 13>; }; &pmi8998_pwm_1 { @@ -399,37 +406,53 @@ interrupts = <63 0>; interrupt-names = "nfc_irq"; pinctrl-names = "nfc_active", "nfc_suspend"; - pinctrl-0 = <&nfc_int_active - &nfc_enable_active - &nfc_clk_default>; + pinctrl-0 = <&nfc_int_active + &nfc_enable_active + &nfc_clk_default>; pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; clocks = <&clock_rpmh RPMH_LN_BB_CLK3>; clock-names = "ref_clk"; - status = "disabled"; }; }; &qupv3_se5_i2c { + status = "ok"; + /*smart PA*/ + tas2559@4c{ + compatible = "ti,tas2559"; + reg = <0x4c>; + ti,tas2559-reset-gpio = <&tlmm 12 0>; + ti,tas2560-reset-gpio = <&tlmm 76 0>; + ti,tas2559-irq-gpio = <&tlmm 11 0>; + ti,tas2560-irq-gpio = <&tlmm 30 0>; + ti,tas2559-addr = <0x4c>; + ti,tas2560-addr = <0x4d>; + ti,tas2559-channel = <0>; /* 0, left; 1, right */ + ti,tas2560-channel = <1>; /* 0, left; 1, right */ + ti,ycrc-enable = <1>; /* 0, disable; non-zero, enable */ + ti,echo-ref = <0>; /* 0, left channel; 1, right channel; 2, both */ + ti,bit-rate = <16>; /* 16, 20, 24, 32 */ + status = "ok"; + }; + +}; +/* +&qupv3_se10_i2c { status = "ok"; - /*smart PA*/ - tas2559@4c{ - compatible = "ti,tas2559"; - reg = <0x4c>; - ti,tas2559-reset-gpio = <&tlmm 12 0>; - ti,tas2560-reset-gpio = <&tlmm 76 0>; - ti,tas2559-irq-gpio = <&tlmm 11 0>; - ti,tas2560-irq-gpio = <&tlmm 30 0>; - ti,tas2559-addr = <0x4c>; - ti,tas2560-addr = <0x4d>; - ti,tas2559-channel = <0>; /* 0, left; 1, right */ - ti,tas2560-channel = <1>; /* 0, left; 1, right */ - ti,ycrc-enable = <1>; /* 0, disable; non-zero, enable */ - ti,echo-ref = <0>; /* 0, left channel; 1, right channel; 2, both */ - ti,bit-rate = <16>; /* 16, 20, 24, 32 */ - status = "ok"; + idtp9220@61 { + compatible = "idt,p9220"; + reg = <0x61>; + idt,irq = <&tlmm 78 0x00>; + //idt,enable = <&tlmm 36 0x00>; + interrupt-parent = <&tlmm>; + interrupts = <78 0>; + interrupt-names = "idt_irq"; + pinctrl-names = "idt_active", "idt_suspend"; + pinctrl-0 = <&idt_int_active &idt_enable_active>; + pinctrl-1 = <&idt_int_suspend &idt_enable_suspend>; }; - }; +*/ &qupv3_se10_i2c { status = "ok"; @@ -490,7 +513,7 @@ /*novatek,mp-support-dt;*/ }; focaltech@38 { - compatible = "focaltech,focal"; + compatible = "focaltech,fts"; reg = <0x38>; interrupt-parent = <&tlmm>; interrupts = <31 0>; @@ -503,10 +526,6 @@ focaltech,irq-gpio = <&tlmm 31 0x02>; focaltech,max-touch-number = <10>; focaltech,display-coords = <0 0 1080 2246>; - focaltech,project-name = "e10"; - focaltech,lockdown-info-addr = <0x1FA0>; - focaltech,timeout-read-reg = <1000>; - focaltech,cutoff-power; pinctrl-names = "pmx_ts_active", "pmx_ts_suspend"; pinctrl-0 = <&ts_int_active &ts_reset_active>; pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; diff --git a/arch/arm64/boot/dts/qcom/dipper-p0.dtsi b/arch/arm64/boot/dts/qcom/dipper-p0.dtsi index 9fe999a50a23..678a66fd49d9 100644 --- a/arch/arm64/boot/dts/qcom/dipper-p0.dtsi +++ b/arch/arm64/boot/dts/qcom/dipper-p0.dtsi @@ -16,6 +16,7 @@ #include "sdm845-pmic-overlay.dtsi" #include "sdm845-pinctrl-overlay.dtsi" #include "sdm845-xiaomi-common.dtsi" +//#include "dipper-camera-sensor-mtp.dtsi" #include "dipper-p0-camera-sensor-mtp.dtsi" &qupv3_se10_i2c { @@ -31,11 +32,11 @@ }; &reserved_memory { - ramdump_fb_mem: ramdump_fb_region@af000000 { - compatible = "removed-dma-pool"; - no-map; - reg = <0 0xaf000000 0 0x1000000>; - }; + ramdump_fb_mem: ramdump_fb_region@af000000 { + compatible = "removed-dma-pool"; + no-map; + reg = <0 0xaf000000 0 0x1000000>; + }; }; &vendor { @@ -159,6 +160,7 @@ status = "ok"; touch,name = "xiaomi-touch"; }; + }; &labibb { @@ -172,71 +174,45 @@ qcom,mdss-dsi-bl-max-level = <1023>; qcom,platform-reset-gpio = <&tlmm 6 0>; qcom,platform-te-gpio = <&tlmm 10 0>; - qcom,esd-err-irq-gpio = <&tlmm 52 0x2002>; /* trig-flags: falling-0x0002 rasing-0x0001*/ - qcom,mdss-dsi-display-timings { - timing@0{ - qcom,mdss-dsi-on-command = [ - 05 01 00 00 0a 00 02 11 00 - 39 00 00 00 00 00 05 2B 00 00 08 c7 - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 08 EF F0 31 00 33 31 14 35 - 39 00 00 00 00 00 02 B0 01 - 39 00 00 00 00 00 02 BB 03 - 39 00 00 00 00 00 02 B0 4F - 39 00 00 00 00 00 02 CB 00 - 39 00 00 00 00 00 02 B0 6B - 39 00 00 00 00 00 02 CB 00 - 39 00 00 00 00 00 02 F7 03 - 39 00 00 00 00 00 02 B0 05 - 39 00 00 00 00 00 02 B1 10 - 39 00 00 00 00 00 02 B0 02 - 39 00 00 00 00 00 05 D5 02 17 54 14 - 39 01 00 00 00 00 03 F0 A5 A5 - 39 00 00 00 00 00 02 35 00 - 39 00 00 00 00 00 03 51 00 00 - 39 00 00 00 00 00 02 53 20 - 39 01 00 00 6E 00 02 55 00 - 05 01 00 00 00 00 02 29 00]; - }; - }; }; + &dsi_dual_nt35597_video { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; - qcom,panel-mode-gpio = <&tlmm 52 0>; - qcom,platform-reset-gpio = <&tlmm 6 0>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-mode-gpio = <&tlmm 52 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; }; &dsi_dual_nt35597_cmd { - qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <4095>; - qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; - qcom,panel-mode-gpio = <&tlmm 52 0>; - qcom,platform-reset-gpio = <&tlmm 6 0>; - qcom,platform-te-gpio = <&tlmm 10 0>; + qcom,panel-supply-entries = <&dsi_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-dsi-mode-sel-gpio-state = "dual_port"; + qcom,panel-mode-gpio = <&tlmm 52 0>; + qcom,platform-reset-gpio = <&tlmm 6 0>; + qcom,platform-te-gpio = <&tlmm 10 0>; }; &dsi_gvo_fhd_rm69299_cmd { - qcom,panel-supply-entries = <&dsi_amoled_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <1023>; - qcom,platform-reset-gpio = <&tlmm 6 0>; - qcom,platform-te-gpio = <&tlmm 10 0>; + qcom,panel-supply-entries = <&dsi_amoled_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-reset-gpio = <&tlmm 6 0>; + qcom,platform-te-gpio = <&tlmm 10 0>; }; &dsi_tianma_fhd_rm69299_cmd { - qcom,panel-supply-entries = <&dsi_amoled_panel_pwr_supply>; - qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; - qcom,mdss-dsi-bl-min-level = <1>; - qcom,mdss-dsi-bl-max-level = <1023>; - qcom,platform-reset-gpio = <&tlmm 6 0>; - qcom,platform-te-gpio = <&tlmm 10 0>; + qcom,panel-supply-entries = <&dsi_amoled_panel_pwr_supply>; + qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_dcs"; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <1023>; + qcom,platform-reset-gpio = <&tlmm 6 0>; + qcom,platform-te-gpio = <&tlmm 10 0>; }; &dsi_sim_vid { @@ -254,20 +230,20 @@ }; &pmi8998_haptics { - qcom,vmax-mv = <3100>; - qcom,lra-auto-mode; - qcom,overdrive; - qcom,wave-play-rate-us = <4878>; - qcom,wave-shape = "sine"; - qcom,lra-high-z = "opt1"; - qcom,lra-auto-res-mode = "qwd"; - qcom,lra-res-cal-period = <4>; - qcom,effect-max = <3>; - qcom,effect-arry = [3e 3e be 00 00 00 00 00 - 3e 3e 3e 3e be be a0 00 - 3e 3e 3e 3e 3e be be be]; - qcom,play-mode = "buffer"; - status = "okay"; + qcom,vmax-mv = <3100>; + qcom,lra-auto-mode; + qcom,overdrive; + qcom,wave-play-rate-us = <4878>; + qcom,wave-shape = "sine"; + qcom,lra-high-z = "opt1"; + qcom,lra-auto-res-mode = "qwd"; + qcom,lra-res-cal-period = <4>; + qcom,effect-max = <3>; + qcom,effect-arry = [3e 3e be 00 00 00 00 00 + 3e 3e 3e 3e be be a0 00 + 3e 3e 3e 3e 3e be be be]; + qcom,play-mode = "buffer"; + status = "okay"; }; &mdss_mdp { @@ -336,9 +312,9 @@ }; &pmi8998_switch2 { - pinctrl-names = "led_enable", "led_disable"; - pinctrl-0 = <&flash_led3_iris_en>; - pinctrl-1 = <&flash_led3_iris_dis>; + pinctrl-names = "led_enable", "led_disable"; + pinctrl-0 = <&flash_led3_iris_en>; + pinctrl-1 = <&flash_led3_iris_dis>; }; &vendor{ @@ -385,8 +361,7 @@ qcom,fcc-hot-temp-delta = <1650000>; qcom,fcc-cool-temp-delta = <2310000>; qcom,auto-recharge-soc; - qcom,sw-jeita-enable; - qcom,dynamic-fv-enable; + qcom,sw-jeita-enable; qcom,thermal-mitigation = <1800000 1600000 1400000 1200000 1000000 1000000 1000000>; qcom,thermal-mitigation-dcp @@ -421,8 +396,6 @@ qcom,fg-esr-clamp-mohms = <60>; qcom,fg-batt-temp-delta = <6>; qcom,battery-data = <&mtp_batterydata>; - qcom,slope-limit-temp-threshold = <100>; - qcom,slope-limit-coeffs = <10 11 12 13>; }; &pmi8998_pwm_1 { @@ -468,9 +441,9 @@ interrupts = <63 0>; interrupt-names = "nfc_irq"; pinctrl-names = "nfc_active", "nfc_suspend"; - pinctrl-0 = <&nfc_int_active - &nfc_enable_active - &nfc_clk_default>; + pinctrl-0 = <&nfc_int_active + &nfc_enable_active + &nfc_clk_default>; pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; clocks = <&clock_rpmh RPMH_LN_BB_CLK3>; clock-names = "ref_clk"; @@ -539,18 +512,6 @@ // fts,y-offset = <300>; // fts,y-skip = <240>; fts,config-array-size = <1>; - fts,default-fw-name = "st_fts_e1.ftb"; - fts,touch-up-threshold-min = <20>; - fts,touch-up-threshold-max = <50>; - fts,touch-up-threshold-def = <20>; - fts,touch-tolerance-min = <5>; - fts,touch-tolerance-max = <15>; - fts,touch-tolerance-def = <5>; - fts,edgefilter-leftrigt-def = <30>; - fts,edgefilter-topbottom-def = <30>; - fts,edgefilter-area-step1 = <100>; - fts,edgefilter-area-step2 = <150>; - fts,edgefilter-area-step3 = <250>; fts,cfg_0 { fts,tp-vendor = <0x48>; fts,fw-name = "st_fts_e1.ftb"; @@ -971,10 +932,6 @@ pinctrl-names = "atest_usb13_suspend","atest_usb13_active"; pinctrl-0 = <&atest_usb13_suspend>; pinctrl-1 = <&atest_usb13_active>; - mi,efuse-pll-bias; - mi,efuse-pll-bias-seq = <1 0x23>; - mi,efuse-pll-bias-host; - mi,efuse-pll-bias-seq-host = <1 0x24 2 0x24 3 0x24 4 0x23 5 0x22 6 0x22 7 0x21>; }; &pmi8998_pdphy { diff --git a/arch/arm64/boot/dts/qcom/dsi-panel-samsung-fhd-ea8076-cmd.dtsi b/arch/arm64/boot/dts/qcom/dsi-panel-samsung-fhd-ea8076-cmd.dtsi index ee54aa87ae14..81d3a2d82934 100644 --- a/arch/arm64/boot/dts/qcom/dsi-panel-samsung-fhd-ea8076-cmd.dtsi +++ b/arch/arm64/boot/dts/qcom/dsi-panel-samsung-fhd-ea8076-cmd.dtsi @@ -58,13 +58,13 @@ qcom,mdss-dsi-panel-blackness-level = <3230>; qcom,dispparam-enabled; - qcom,mdss-panel-on-dimming-delay = <200>; + qcom,mdss-panel-on-dimming-delay = <120>; qcom,disp-doze-backlight-threshold = <8>; /* IRQF_ONESHOT | IRQF_TRIGGER_HIGH */ /* qcom,esd-err-irq-gpio = <&tlmm 52 0x2004>; */ qcom,bl-update-flag = "delay_until_first_frame"; - qcom,mdss-dsi-panel-dc-threshold = <610>; + qcom,mdss-dsi-display-timings { timing@0{ qcom,mdss-dsi-panel-width = <1080>; @@ -116,14 +116,7 @@ /* Display On */ 05 01 00 00 00 00 02 29 00]; qcom,mdss-dsi-off-command = [ - /* Display Off */ - 05 01 00 00 11 00 02 28 00 - /* LTPS Off Setting */ - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 02 B0 4F - 39 00 00 00 00 00 02 B9 58 - 39 01 00 00 11 00 03 F0 A5 A5 - /* Sleep in */ + 05 01 00 00 00 00 02 28 00 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; @@ -173,8 +166,7 @@ qcom,mdss-dsi-dispparam-dimmingon-command = [39 01 00 00 01 00 02 53 28]; qcom,mdss-dsi-dispparam-dimmingon-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-dispparam-dimmingoff-command = [39 01 00 00 01 00 02 53 20]; - qcom,mdss-dsi-dispparam-dimmingoff-command-state = "dsi_lp_mode"; + qcom,mdss-dsi-dispparam-crc-srgb-on-command = [ /* CRC Enable + sRGB mode */ 39 01 00 00 00 00 02 81 90 diff --git a/arch/arm64/boot/dts/qcom/dsi-panel-ss-fhd-ea8074-cmd.dtsi b/arch/arm64/boot/dts/qcom/dsi-panel-ss-fhd-ea8074-cmd.dtsi index c7f1266a5e18..f29033dcb41c 100644 --- a/arch/arm64/boot/dts/qcom/dsi-panel-ss-fhd-ea8074-cmd.dtsi +++ b/arch/arm64/boot/dts/qcom/dsi-panel-ss-fhd-ea8074-cmd.dtsi @@ -38,7 +38,7 @@ qcom,mdss-dsi-lane-3-state; qcom,mdss-dsi-t-clk-post = <0x0e>; qcom,mdss-dsi-t-clk-pre = <0x31>; - qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-min-level = <1>; qcom,mdss-dsi-bl-max-level = <1023>; qcom,mdss-brightness-max-level = <1023>; qcom,mdss-dsi-dma-trigger = "trigger_sw"; @@ -61,6 +61,7 @@ qcom,mdss-dsi-panel-blackness-level = <3230>; qcom,mdss-dsi-on-command-tuning; qcom,dispparam-enabled; + /* qcom,esd-err-irq-gpio = <&tlmm 52 0>; */ qcom,mdss-dsi-display-timings { timing@0{ qcom,mdss-dsi-panel-width = <1080>; @@ -78,31 +79,31 @@ qcom,mdss-dsi-v-bottom-border = <0>; qcom,mdss-dsi-panel-framerate = <60>; qcom,mdss-dsi-on-command = [ - 05 01 00 00 0a 00 02 11 00 - 39 00 00 00 00 00 05 2B 00 00 08 6f - 39 00 00 00 00 00 03 F0 5A 5A - 39 00 00 00 00 00 02 B0 04 - 39 00 00 00 00 00 02 B2 00 - 39 00 00 00 00 00 02 F7 03 - 39 00 00 00 00 00 03 F0 A5 A5 - 39 00 00 00 00 00 02 35 00 - 39 00 00 00 00 00 03 51 00 00 - 39 00 00 00 00 00 02 53 25 - 39 01 00 00 6E 00 02 55 00 - 05 01 00 00 00 00 02 29 00]; + 05 01 00 00 0a 00 02 11 00 + 39 00 00 00 00 00 05 2B 00 00 08 6f + 39 00 00 00 00 00 03 F0 5A 5A + 39 00 00 00 00 00 02 B0 04 + 39 00 00 00 00 00 02 B2 00 + 39 00 00 00 00 00 02 F7 03 + 39 00 00 00 00 00 03 F0 A5 A5 + 39 00 00 00 00 00 02 35 00 + 39 00 00 00 00 00 03 51 00 00 + 39 00 00 00 00 00 02 53 25 + 39 01 00 00 6E 00 02 55 00 + 05 01 00 00 00 00 02 29 00]; qcom,mdss-dsi-off-command = [ 05 01 00 00 00 00 02 28 00 05 01 00 00 78 00 02 10 00]; qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; qcom,mdss-dsi-doze-hbm-command = [ - 39 01 00 00 00 00 03 51 00 01 - 39 01 00 00 01 00 02 53 22]; + 39 01 00 00 00 00 03 51 00 01 + 39 01 00 00 01 00 02 53 22]; qcom,mdss-dsi-doze-lbm-command = [ - 39 01 00 00 00 00 03 51 00 01 - 39 01 00 00 01 00 02 53 23]; + 39 01 00 00 00 00 03 51 00 01 + 39 01 00 00 01 00 02 53 23]; qcom,mdss-dsi-nolp-command = [ - 39 01 00 00 00 00 02 53 25]; + 39 01 00 00 00 00 02 53 25]; qcom,mdss-dsi-doze-hbm-command-state = "dsi_lp_mode"; qcom,mdss-dsi-doze-lbm-command-state = "dsi_lp_mode"; qcom,mdss-dsi-nolp-command-state = "dsi_lp_mode"; diff --git a/arch/arm64/boot/dts/qcom/dsi-panel-ss-notch-fhd-ea8074-cmd.dtsi b/arch/arm64/boot/dts/qcom/dsi-panel-ss-notch-fhd-ea8074-cmd.dtsi index 5a7ac420b1d2..1b1cb841ecc6 100644 --- a/arch/arm64/boot/dts/qcom/dsi-panel-ss-notch-fhd-ea8074-cmd.dtsi +++ b/arch/arm64/boot/dts/qcom/dsi-panel-ss-notch-fhd-ea8074-cmd.dtsi @@ -38,7 +38,7 @@ qcom,mdss-dsi-lane-1-state; qcom,mdss-dsi-lane-2-state; qcom,mdss-dsi-lane-3-state; - qcom,mdss-brightness-max-level = <1023>; + qcom,mdss-brightness-max-level = <255>; qcom,mdss-dsi-dma-trigger = "trigger_sw"; qcom,mdss-dsi-mdp-trigger = "none"; qcom,mdss-dsi-bl-dcs-type-ss; @@ -56,7 +56,7 @@ qcom,mdss-dsi-panel-hdr-enabled; qcom,mdss-dsi-panel-hdr-color-primaries = <14500 15500 32000 17000 15500 30000 8000 3000>; - qcom,mdss-dsi-panel-peak-brightness = <4300000>; + qcom,mdss-dsi-panel-peak-brightness = <5530000>; qcom,mdss-dsi-panel-blackness-level = <3230>; qcom,dispparam-enabled; qcom,mdss-dsi-init-delay-us = <5000>; diff --git a/arch/arm64/boot/dts/qcom/dsi-panel-visionox-fhd-r66455-cmd.dtsi b/arch/arm64/boot/dts/qcom/dsi-panel-visionox-fhd-r66455-cmd.dtsi index bd128fd8fc90..d3ede147340b 100644 --- a/arch/arm64/boot/dts/qcom/dsi-panel-visionox-fhd-r66455-cmd.dtsi +++ b/arch/arm64/boot/dts/qcom/dsi-panel-visionox-fhd-r66455-cmd.dtsi @@ -36,9 +36,9 @@ qcom,mdss-dsi-lane-1-state; qcom,mdss-dsi-lane-2-state; qcom,mdss-dsi-lane-3-state; - qcom,mdss-brightness-remap; - qcom,mdss-doze-brightness-variable; - qcom,mdss-brightness-max-level = <2047>; + qcom,mdss-dsi-bl-min-level = <1>; + qcom,mdss-dsi-bl-max-level = <4095>; + qcom,mdss-brightness-max-level = <4095>; qcom,mdss-dsi-dma-trigger = "trigger_sw"; qcom,mdss-dsi-mdp-trigger = "none"; qcom,mdss-dsi-reset-sequence = <0 2>, <1 10>; @@ -58,14 +58,13 @@ qcom,mdss-dsi-bl-dcs-type-ss; /* qcom,mdss-dsi-on-command-tuning; */ - qcom,dispparam-enabled; - qcom,mdss-panel-on-dimming-delay = <120>; - qcom,disp-doze-backlight-threshold = <8>;/*2047(8), 4096(16) */ + /* qcom,dispparam-enabled; */ + /* qcom,mdss-panel-on-dimming-delay = <120>; */ + /* qcom,disp-doze-backlight-threshold = <8>; */ /* IRQF_ONESHOT | IRQF_TRIGGER_HIGH */ /* qcom,esd-err-irq-gpio = <&tlmm 52 0x2004>; */ - qcom,bl-update-flag = "delay_until_first_frame"; - qcom,bl-update-delay = <28>; + /* qcom,bl-update-flag = "delay_until_first_frame"; */ qcom,mdss-dsi-display-timings { timing@0{ @@ -88,64 +87,23 @@ 39 01 00 00 00 00 02 B0 00 /* mode switch 00:CMD mode 01:VDO mode */ 39 01 00 00 00 00 02 B3 00 - 39 01 00 00 00 00 02 FA 9F - 39 01 00 00 00 00 0F C1 F0 61 00 00 00 00 00 20 02 00 00 00 00 81 - /* SET Column Start Adress */ - 39 01 00 00 00 00 05 2A 00 00 04 37 - /* SET Row Start Adress */ - 39 01 00 00 00 00 05 2B 00 00 09 23 /* Bank 1 */ 39 01 00 00 00 00 02 B0 80 - 39 01 00 00 00 00 02 E4 FE /* NVM load control */ 39 01 00 00 00 00 02 E6 00 /* brightness control */ - 39 01 00 00 00 00 03 51 01 00 + 39 01 00 00 00 00 03 51 04 00 /* TE Control*/ 39 01 00 00 00 00 02 35 00 - /* Bank 0 */ - 39 01 00 00 00 00 02 B0 00 /* display on */ - 05 01 00 00 00 00 02 29 00 + 05 01 00 00 78 00 02 29 00 /* sleep out */ - 05 01 00 00 64 00 02 11 00]; + 05 01 00 00 78 00 02 11 00]; qcom,mdss-dsi-off-command = [ 05 01 00 00 00 00 02 28 00 - 05 01 00 00 78 00 02 10 00]; - qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-off-command-state = "dsi_lp_mode"; - - qcom,mdss-dsi-doze-hbm-command = [ - /* AOD ON Sequence (Normal To AOD HBM) */ - 05 01 00 00 00 00 02 39 00 - 39 01 00 00 00 00 03 51 00 FF]; - qcom,mdss-dsi-doze-lbm-command = [ - /* AOD ON Sequence (Normal To AOD LBM) */ - 05 01 00 00 00 00 02 39 00 - 39 01 00 00 00 00 03 51 00 00]; - qcom,mdss-dsi-nolp-command = [ - /* AOD OFF Sequence (AOD To Normal) */ - 05 01 00 00 00 00 02 38 00]; - qcom,mdss-dsi-doze-hbm-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-doze-lbm-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-nolp-command-state = "dsi_lp_mode"; - - qcom,mdss-dsi-dispparam-acl-off-command = [39 01 00 00 00 00 02 55 00]; - qcom,mdss-dsi-dispparam-acl-off-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-dispparam-acl-l1-command = [39 01 00 00 00 00 02 55 03];/* 40% */ - qcom,mdss-dsi-dispparam-acl-l1-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-dispparam-acl-l2-command = [39 01 00 00 00 00 02 55 02];/* 30% */ - qcom,mdss-dsi-dispparam-acl-l2-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-dispparam-acl-l3-command = [39 01 00 00 00 00 02 55 01];/* 15% */ - qcom,mdss-dsi-dispparam-acl-l3-command-state = "dsi_lp_mode"; - - qcom,mdss-dsi-dispparam-hbm-off-command = [39 01 00 00 00 00 02 53 28]; - qcom,mdss-dsi-dispparam-hbm-off-command-state = "dsi_lp_mode"; - qcom,mdss-dsi-dispparam-hbm-on-command = [39 01 00 00 00 00 02 53 E8]; - qcom,mdss-dsi-dispparam-hbm-on-command-state = "dsi_lp_mode"; - - qcom,mdss-dsi-dispparam-dimmingon-command = [39 01 00 00 00 00 02 53 28]; - qcom,mdss-dsi-dispparam-dimmingon-command-state = "dsi_lp_mode"; + 05 01 00 00 55 00 02 10 00]; + qcom,mdss-dsi-on-command-state = "dsi_hs_mode"; + qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; }; }; }; diff --git a/arch/arm64/boot/dts/qcom/pmi8998.dtsi b/arch/arm64/boot/dts/qcom/pmi8998.dtsi index f262d34546c6..f75bba52246b 100644 --- a/arch/arm64/boot/dts/qcom/pmi8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8998.dtsi @@ -285,7 +285,6 @@ qcom,fg-esr-timer-asleep = <256 256>; qcom,fg-esr-timer-charging = <0 96>; qcom,cycle-counter-en; - qcom,hold-soc-while-full; qcom,fg-auto-recharge-soc; qcom,fg-recharge-soc-thr = <98>; status = "okay"; @@ -876,7 +875,6 @@ polling-delay = <0>; thermal-sensors = <&pmi8998_tz>; wake-capable-sensor; - disable-thermal-zone; trips { pmi8998_trip0: pmi8998-trip0 { diff --git a/arch/arm64/boot/dts/qcom/polaris-audio-overlay.dtsi b/arch/arm64/boot/dts/qcom/polaris-audio-overlay.dtsi index dd0c092b9299..ecab0a2f1ba6 100644 --- a/arch/arm64/boot/dts/qcom/polaris-audio-overlay.dtsi +++ b/arch/arm64/boot/dts/qcom/polaris-audio-overlay.dtsi @@ -33,7 +33,6 @@ "MIC BIAS4", "Analog Mic5"; qcom,wsa-max-devs = <0>; - qcom,euro-us-hw-auto-switch; qcom,hw-auto-sw-en-gpio = <&sbu_mic_oe>; qcom,uart-audio-sw-gpio = <&sbu_uart_en>; qcom,adc2-switch-gpio = <&adc2_switch_gpio>; diff --git a/arch/arm64/boot/dts/qcom/polaris-p0.dtsi b/arch/arm64/boot/dts/qcom/polaris-p0.dtsi index 02358f34d588..b0f315c0a48a 100644 --- a/arch/arm64/boot/dts/qcom/polaris-p0.dtsi +++ b/arch/arm64/boot/dts/qcom/polaris-p0.dtsi @@ -139,12 +139,12 @@ }; tp_vddio_vreg: tp_vddio_vreg { - compatible = "regulator-fixed"; - regulator-name = "tp_vddio_vreg"; - startup-delay-us = <4000>; - enable-active-high; - regulator-boot-on; - gpio = <&tlmm 23 0>; + compatible = "regulator-fixed"; + regulator-name = "tp_vddio_vreg"; + startup-delay-us = <4000>; + enable-active-high; + regulator-boot-on; + gpio = <&tlmm 23 0>; }; thermal-message { @@ -200,18 +200,18 @@ }; &pmi8998_haptics { - qcom,vmax-mv = <2552>; - qcom,lra-auto-mode; - qcom,wave-play-rate-us = <4878>; - qcom,wave-shape = "sine"; - qcom,lra-high-z = "opt1"; - qcom,lra-auto-res-mode = "qwd"; - qcom,lra-res-cal-period = <4>; - qcom,effect-max = <3>; - qcom,effect-arry = [3e 3e be a0 00 00 00 00 - 3e 3e 3e be be 00 00 00 - 3e 3e 3e 3e be be a0 90]; - status = "okay"; + qcom,vmax-mv = <2552>; + qcom,lra-auto-mode; + qcom,wave-play-rate-us = <4878>; + qcom,wave-shape = "sine"; + qcom,lra-high-z = "opt1"; + qcom,lra-auto-res-mode = "qwd"; + qcom,lra-res-cal-period = <4>; + qcom,effect-max = <3>; + qcom,effect-arry = [3e 3e be a0 00 00 00 00 + 3e 3e 3e be be 00 00 00 + 3e 3e 3e 3e be be a0 90]; + status = "okay"; }; &mdss_mdp { @@ -279,9 +279,9 @@ }; &pmi8998_switch2 { - pinctrl-names = "led_enable", "led_disable"; - pinctrl-0 = <&flash_led3_iris_en>; - pinctrl-1 = <&flash_led3_iris_dis>; + pinctrl-names = "led_enable", "led_disable"; + pinctrl-0 = <&flash_led3_iris_en>; + pinctrl-1 = <&flash_led3_iris_dis>; }; &vendor{ @@ -308,8 +308,7 @@ qcom,fcc-hot-temp-delta = <1650000>; qcom,fcc-cool-temp-delta = <2310000>; qcom,auto-recharge-soc; - qcom,sw-jeita-enable; - qcom,dynamic-fv-enable; + qcom,sw-jeita-enable; qcom,wireless-flag; qcom,wireless-support; qcom,thermal-mitigation @@ -359,8 +358,6 @@ qcom,fg-esr-clamp-mohms = <60>; qcom,fg-batt-temp-delta = <6>; qcom,battery-data = <&mtp_batterydata>; - qcom,slope-limit-temp-threshold = <100>; - qcom,slope-limit-coeffs = <10 11 12 13>; }; &smb1355_charger_0 { @@ -394,9 +391,9 @@ interrupts = <63 0>; interrupt-names = "nfc_irq"; pinctrl-names = "nfc_active", "nfc_suspend"; - pinctrl-0 = <&nfc_int_active - &nfc_enable_active - &nfc_clk_default>; + pinctrl-0 = <&nfc_int_active + &nfc_enable_active + &nfc_clk_default>; pinctrl-1 = <&nfc_int_suspend &nfc_enable_suspend>; clocks = <&clock_rpmh RPMH_LN_BB_CLK3>; clock-names = "ref_clk"; @@ -404,24 +401,24 @@ }; &qupv3_se5_i2c { - status = "ok"; - /*smart PA*/ - tas2559@4c{ - compatible = "ti,tas2559"; - reg = <0x4c>; - ti,tas2559-reset-gpio = <&tlmm 8 0>; - ti,tas2560-reset-gpio = <&tlmm 25 0>; - ti,tas2559-irq-gpio = <&tlmm 24 0>; - ti,tas2560-irq-gpio = <&tlmm 30 0>; - ti,tas2559-addr = <0x4c>; - ti,tas2560-addr = <0x4d>; - ti,tas2559-channel = <0>; /* 0, left; 1, right */ - ti,tas2560-channel = <1>; /* 0, left; 1, right */ - ti,ycrc-enable = <1>; /* 0, disable; non-zero, enable */ - ti,echo-ref = <0>; /* 0, left channel; 1, right channel; 2, both */ - ti,bit-rate = <16>; /* 16, 20, 24, 32 */ - status = "ok"; - }; + status = "ok"; + /*smart PA*/ + tas2559@4c{ + compatible = "ti,tas2559"; + reg = <0x4c>; + ti,tas2559-reset-gpio = <&tlmm 8 0>; + ti,tas2560-reset-gpio = <&tlmm 25 0>; + ti,tas2559-irq-gpio = <&tlmm 24 0>; + ti,tas2560-irq-gpio = <&tlmm 30 0>; + ti,tas2559-addr = <0x4c>; + ti,tas2560-addr = <0x4d>; + ti,tas2559-channel = <0>; /* 0, left; 1, right */ + ti,tas2560-channel = <1>; /* 0, left; 1, right */ + ti,ycrc-enable = <1>; /* 0, disable; non-zero, enable */ + ti,echo-ref = <0>; /* 0, left channel; 1, right channel; 2, both */ + ti,bit-rate = <16>; /* 16, 20, 24, 32 */ + status = "ok"; + }; }; diff --git a/arch/arm64/boot/dts/qcom/qcs605-lc-mtp.dtsi b/arch/arm64/boot/dts/qcom/qcs605-lc-mtp.dtsi index d5a40fd4b070..1ae339ed7e81 100644 --- a/arch/arm64/boot/dts/qcom/qcs605-lc-mtp.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs605-lc-mtp.dtsi @@ -1,4 +1,4 @@ -/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. +/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -85,11 +85,3 @@ status = "ok"; }; - -&pm660_l12 { - regulator-boot-on; -}; - -<9611_vcc_eldo { - regulator-boot-on; -}; diff --git a/arch/arm64/boot/dts/qcom/sdm845-670-usb-common.dtsi b/arch/arm64/boot/dts/qcom/sdm845-670-usb-common.dtsi index 59425d09f923..2b3a384e9f68 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-670-usb-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-670-usb-common.dtsi @@ -1,5 +1,6 @@ /* * Copyright (c) 2016-2018, 2020, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/arch/arm64/boot/dts/qcom/sdm845-pcie.dtsi b/arch/arm64/boot/dts/qcom/sdm845-pcie.dtsi index c00c264649c7..95488baad72e 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-pcie.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-pcie.dtsi @@ -1,5 +1,6 @@ /* * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -474,7 +475,6 @@ qcom,vreg-cx-voltage-level = ; - qcom,l1-supported; qcom,l1ss-supported; qcom,aux-clk-sync; diff --git a/arch/arm64/boot/dts/qcom/sdm845-sde.dtsi b/arch/arm64/boot/dts/qcom/sdm845-sde.dtsi index 14fd8e71d124..6132722a562b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-sde.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-sde.dtsi @@ -387,9 +387,6 @@ qcom,mdss-inline-rot-danger-lut = <0x0055aaff 0x0000ffff>; qcom,mdss-inline-rot-safe-lut = <0x0000f000 0x0000ff00>; - qcom,mdss-rot-qos-cpu-mask = <0xf>; - qcom,mdss-rot-qos-cpu-dma-latency = <75>; - qcom,mdss-default-ot-rd-limit = <32>; qcom,mdss-default-ot-wr-limit = <32>; diff --git a/arch/arm64/boot/dts/qcom/sdm845-v2.dtsi b/arch/arm64/boot/dts/qcom/sdm845-v2.dtsi index ecabd5f89f61..cad9b0288abd 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-v2.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-v2.dtsi @@ -410,23 +410,23 @@ &energy_costs { CPU_COST_0: core-cost0 { busy-cost-data = < - 300000 21 - 403200 26 - 480000 31 - 576000 36 - 652800 41 - 748800 46 - 825600 53 - 902400 59 - 979200 64 - 1056000 70 - 1132800 79 - 1228800 89 - 1324800 99 - 1420800 108 - 1516800 118 - 1612800 134 - 1689600 143 + 300000 12 + 403200 17 + 480000 21 + 576000 27 + 652800 31 + 748800 37 + 825600 42 + 902400 47 + 979200 52 + 1056000 57 + 1132800 62 + 1228800 70 + 1324800 78 + 1420800 89 + 1516800 103 + 1612800 122 + 1689600 141 1766400 160 >; idle-cost-data = < @@ -435,43 +435,45 @@ }; CPU_COST_1: core-cost1 { busy-cost-data = < - 300000 90 - 403200 113 - 480000 135 - 576000 157 - 652800 175 - 748800 198 - 825600 210 - 902400 233 - 979200 263 - 1056000 285 - 1132800 322 - 1209600 341 - 1286400 379 - 1363200 410 - 1459200 462 - 1536000 503 - 1612800 542 - 1689600 600 - 1766400 649 - 1843200 717 - 1920000 813 - 1996800 866 - 2092800 1025 - 2169600 1054 - 2246400 1130 - 2323200 1254 - 2400000 1356 - 2476800 1503 - 2553600 1745 - 2649600 2106 - 2745600 2200 - 2764800 2300 - 2784000 2350 - 2803200 2400 + 300000 189 + 403200 523 + 480000 763 + 576000 1052 + 652800 1273 + 748800 1536 + 825600 1736 + 902400 1926 + 979200 2108 + 1056000 2284 + 1132800 2456 + 1209600 2628 + 1286400 2804 + 1363200 2992 + 1459200 3255 + 1536000 3499 + 1612800 3786 + 1689600 4128 + 1766400 4535 + 1843200 5019 + 1920000 5583 + 1996800 6226 + 2092800 7120 + 2169600 7876 + 2246400 8628 + 2323200 9344 + 2400000 10030 + 2476800 10806 + 2553600 12045 + 2649600 15686 + 2745600 25586 + 2764800 30000 + 2784000 35000 + 2803200 40000 + 2841600 50000 + 2956800 60000 >; idle-cost-data = < - 25 20 15 10 + 100 80 60 40 >; }; CLUSTER_COST_0: cluster-cost0 { diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 435af430e833..1b4a62957597 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -662,7 +662,7 @@ alloc-ranges = <0 0x00000000 0 0xffffffff>; reusable; alignment = <0 0x400000>; - size = <0 0x8000000>; + size = <0 0x2000000>; linux,cma-default; }; }; @@ -1435,7 +1435,7 @@ /* PM QoS */ qcom,pm-qos-cpu-groups = <0x0f 0xf0>; - qcom,pm-qos-cpu-group-latency-us = <100 100>; + qcom,pm-qos-cpu-group-latency-us = <70 70>; qcom,pm-qos-default-cpu = <0>; pinctrl-names = "dev-reset-assert", "dev-reset-deassert"; diff --git a/arch/arm64/configs/beryllium_defconfig b/arch/arm64/configs/beryllium_defconfig index 811a4fc0b14b..6d9ec6a077d8 100644 --- a/arch/arm64/configs/beryllium_defconfig +++ b/arch/arm64/configs/beryllium_defconfig @@ -1,748 +1,113 @@ -# -# Automatically generated file; DO NOT EDIT. -# Linux/arm64 4.9.191 Kernel Configuration -# -CONFIG_ARM64=y -CONFIG_64BIT=y -CONFIG_ARCH_PHYS_ADDR_T_64BIT=y -CONFIG_MMU=y -CONFIG_DEBUG_RODATA=y -CONFIG_ARM64_PAGE_SHIFT=12 -CONFIG_ARM64_CONT_SHIFT=4 -CONFIG_ARCH_MMAP_RND_BITS_MIN=18 -CONFIG_ARCH_MMAP_RND_BITS_MAX=24 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=11 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_RWSEM_XCHGADD_ALGORITHM=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CSUM=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_ZONE_DMA=y -CONFIG_HAVE_GENERIC_RCU_GUP=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_SMP=y -CONFIG_SWIOTLB=y -CONFIG_IOMMU_HELPER=y -CONFIG_KERNEL_MODE_NEON=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_PGTABLE_LEVELS=3 -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" -CONFIG_IRQ_WORK=y -CONFIG_BUILDTIME_EXTABLE_SORT=y -CONFIG_THREAD_INFO_IN_TASK=y - -# -# General setup -# -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_CROSS_COMPILE="" -# CONFIG_COMPILE_TEST is not set -CONFIG_LOCALVERSION="-LawRun-t6@negrroo" -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_DEFAULT_HOSTNAME="(none)" -CONFIG_SWAP=y -# CONFIG_SYSVIPC is not set -# CONFIG_POSIX_MQUEUE is not set -CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_LOCALVERSION="-perf" # CONFIG_FHANDLE is not set -# CONFIG_USELIB is not set -# CONFIG_AUDIT is not set -CONFIG_HAVE_ARCH_AUDITSYSCALL=y - -# -# IRQ subsystem -# -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_SHOW_LEVEL=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_HANDLE_DOMAIN_IRQ=y -# CONFIG_IRQ_DOMAIN_DEBUG is not set -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_SPARSE_IRQ=y -CONFIG_ARCH_CLOCKSOURCE_DATA=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_ARCH_HAS_TICK_BROADCAST=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y - -# -# Timers subsystem -# -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ_COMMON=y -# CONFIG_HZ_PERIODIC is not set -# CONFIG_NO_HZ_IDLE is not set -CONFIG_NO_HZ_FULL=y -CONFIG_NO_HZ_FULL_ALL=y -CONFIG_NO_HZ_FULL_SYSIDLE=y -CONFIG_NO_HZ_FULL_SYSIDLE_SMALL=8 +CONFIG_AUDIT=y +# CONFIG_AUDITSYSCALL is not set CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y - -# -# CPU/Task time and stats accounting -# -CONFIG_VIRT_CPU_ACCOUNTING=y -CONFIG_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_IRQ_TIME_ACCOUNTING=y CONFIG_SCHED_WALT=y -# CONFIG_BSD_PROCESS_ACCT is not set CONFIG_TASKSTATS=y -# CONFIG_TASK_DELAY_ACCT is not set CONFIG_TASK_XACCT=y CONFIG_TASK_IO_ACCOUNTING=y - -# -# RCU Subsystem -# -CONFIG_PREEMPT_RCU=y CONFIG_RCU_EXPERT=y -CONFIG_SRCU=y -# CONFIG_TASKS_RCU is not set -CONFIG_RCU_STALL_COMMON=y -CONFIG_CONTEXT_TRACKING=y -# CONFIG_CONTEXT_TRACKING_FORCE is not set -CONFIG_RCU_FANOUT=64 -CONFIG_RCU_FANOUT_LEAF=16 CONFIG_RCU_FAST_NO_HZ=y -# CONFIG_TREE_RCU_TRACE is not set -# CONFIG_RCU_BOOST is not set -CONFIG_RCU_KTHREAD_PRIO=1 CONFIG_RCU_NOCB_CPU=y -# CONFIG_RCU_NOCB_CPU_NONE is not set -# CONFIG_RCU_NOCB_CPU_ZERO is not set CONFIG_RCU_NOCB_CPU_ALL=y -CONFIG_BUILD_BIN2C=y CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=21 -# CONFIG_CONSOLE_FLUSH_ON_HOTPLUG is not set CONFIG_LOG_CPU_MAX_BUF_SHIFT=17 -CONFIG_GENERIC_SCHED_CLOCK=y -CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y -CONFIG_CGROUPS=y -# CONFIG_CGROUP_DEBUG is not set CONFIG_CGROUP_FREEZER=y -# CONFIG_CGROUP_PIDS is not set -# CONFIG_CGROUP_DEVICE is not set CONFIG_CPUSETS=y -CONFIG_PROC_PID_CPUSET=y CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_SCHEDTUNE=y -# CONFIG_MEMCG is not set -CONFIG_BLK_CGROUP=y -# CONFIG_DEBUG_BLK_CGROUP is not set -CONFIG_CGROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y -# CONFIG_CFS_BANDWIDTH is not set CONFIG_RT_GROUP_SCHED=y -# CONFIG_CGROUP_PERF is not set CONFIG_CGROUP_BPF=y -CONFIG_SOCK_CGROUP_DATA=y CONFIG_SCHED_CORE_CTL=y -# CONFIG_SCHED_CORE_ROTATE is not set -# CONFIG_CHECKPOINT_RESTORE is not set +CONFIG_SCHED_CORE_ROTATE=y CONFIG_NAMESPACES=y # CONFIG_UTS_NS is not set -# CONFIG_USER_NS is not set # CONFIG_PID_NS is not set -CONFIG_NET_NS=y -# CONFIG_SCHED_AUTOGROUP is not set +CONFIG_SCHED_AUTOGROUP=y CONFIG_SCHED_TUNE=y -CONFIG_DYNAMIC_STUNE_BOOST=y CONFIG_DEFAULT_USE_ENERGY_AWARE=y -# CONFIG_SYSFS_DEPRECATED is not set -# CONFIG_RELAY is not set CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_RD_GZIP=y -CONFIG_RD_BZIP2=y -CONFIG_RD_LZMA=y # CONFIG_RD_XZ is not set # CONFIG_RD_LZO is not set # CONFIG_RD_LZ4 is not set -CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SYSCTL=y -CONFIG_ANON_INODES=y -CONFIG_HAVE_UID16=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_BPF=y -CONFIG_EXPERT=y -CONFIG_UID16=y -CONFIG_MULTIUSER=y -# CONFIG_SGETMASK_SYSCALL is not set -CONFIG_SYSFS_SYSCALL=y -# CONFIG_SYSCTL_SYSCALL is not set -CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y -# CONFIG_KALLSYMS_ABSOLUTE_PERCPU is not set -CONFIG_KALLSYMS_BASE_RELATIVE=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y CONFIG_BPF_SYSCALL=y -CONFIG_SHMEM=y -CONFIG_AIO=y -CONFIG_ADVISE_SYSCALLS=y -# CONFIG_USERFAULTFD is not set -CONFIG_PCI_QUIRKS=y -# CONFIG_MEMBARRIER is not set CONFIG_EMBEDDED=y -CONFIG_HAVE_PERF_EVENTS=y - -# -# Kernel Performance Events And Counters -# -CONFIG_PERF_EVENTS=y -# CONFIG_PERF_USER_SHARE is not set -# CONFIG_DEBUG_PERF_USE_VMALLOC is not set -CONFIG_VM_EVENT_COUNTERS=y # CONFIG_SLUB_DEBUG is not set # CONFIG_COMPAT_BRK is not set -# CONFIG_SLAB is not set -CONFIG_SLUB=y -# CONFIG_SLOB is not set -# CONFIG_SLAB_FREELIST_RANDOM is not set -CONFIG_SLUB_CPU_PARTIAL=y -# CONFIG_SYSTEM_DATA_VERIFICATION is not set CONFIG_PROFILING=y -CONFIG_TRACEPOINTS=y -# CONFIG_JUMP_LABEL is not set -# CONFIG_UPROBES is not set -# CONFIG_HAVE_64BIT_ALIGNED_ACCESS is not set -CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -CONFIG_HAVE_DMA_CONTIGUOUS=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_GENERIC_IDLE_POLL_SETUP=y -CONFIG_ARCH_HAS_FORTIFY_SOURCE=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_CLK=y -CONFIG_HAVE_DMA_API_DEBUG=y -CONFIG_HAVE_HW_BREAKPOINT=y -CONFIG_HAVE_PERF_REGS=y -CONFIG_HAVE_PERF_USER_STACK_DUMP=y -CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_HAVE_RCU_TABLE_FREE=y -CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y -CONFIG_HAVE_CMPXCHG_LOCAL=y -CONFIG_HAVE_CMPXCHG_DOUBLE=y -CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y -CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -CONFIG_SECCOMP_FILTER=y -CONFIG_HAVE_GCC_PLUGINS=y -# CONFIG_GCC_PLUGINS is not set -CONFIG_HAVE_CC_STACKPROTECTOR=y -CONFIG_CC_STACKPROTECTOR=y -# CONFIG_CC_STACKPROTECTOR_NONE is not set -# CONFIG_CC_STACKPROTECTOR_REGULAR is not set CONFIG_CC_STACKPROTECTOR_STRONG=y -# CONFIG_LTO is not set -CONFIG_ARCH_SUPPORTS_LTO_CLANG=y -CONFIG_LTO_NONE=y -# CONFIG_LTO_CLANG is not set -CONFIG_HAVE_CONTEXT_TRACKING=y -CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y -CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y -CONFIG_HAVE_ARCH_HUGE_VMAP=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -CONFIG_HAVE_ARCH_MMAP_RND_BITS=y -CONFIG_ARCH_MMAP_RND_BITS=18 -CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y CONFIG_ARCH_MMAP_RND_COMPAT_BITS=16 -# CONFIG_HAVE_ARCH_HASH is not set -# CONFIG_ISA_BUS_API is not set -CONFIG_CLONE_BACKWARDS=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_COMPAT_OLD_SIGACTION=y -# CONFIG_CPU_NO_EFFICIENT_FFS is not set -# CONFIG_HAVE_ARCH_VMAP_STACK is not set - -# -# GCOV-based kernel profiling -# -# CONFIG_GCOV_KERNEL is not set -CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y -CONFIG_HAVE_GENERIC_DMA_COHERENT=y -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -# CONFIG_MODULES is not set -CONFIG_MODULES_TREE_LOOKUP=y -CONFIG_BLOCK=y -CONFIG_BLK_DEV_BSG=y -# CONFIG_BLK_DEV_BSGLIB is not set -# CONFIG_BLK_DEV_INTEGRITY is not set -# CONFIG_BLK_DEV_THROTTLING is not set -# CONFIG_BLK_CMDLINE_PARSER is not set - -# -# Partition Types -# +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_AIX_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -# CONFIG_MAC_PARTITION is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_BSD_DISKLABEL is not set -# CONFIG_MINIX_SUBPARTITION is not set -# CONFIG_SOLARIS_X86_PARTITION is not set -# CONFIG_UNIXWARE_DISKLABEL is not set -# CONFIG_LDM_PARTITION is not set -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_KARMA_PARTITION is not set -CONFIG_EFI_PARTITION=y -# CONFIG_SYSV68_PARTITION is not set -# CONFIG_CMDLINE_PARTITION is not set -CONFIG_BLOCK_COMPAT=y -CONFIG_BLK_MQ_PCI=y - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_CFQ_GROUP_IOSCHED=y -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="cfq" -CONFIG_UNINLINE_SPIN_UNLOCK=y -CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_ARCH_USE_QUEUED_RWLOCKS=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_FREEZER=y - -# -# Platform selection -# -# CONFIG_ARCH_SUNXI is not set -# CONFIG_ARCH_ALPINE is not set -# CONFIG_ARCH_BCM2835 is not set -# CONFIG_ARCH_BCM_IPROC is not set -# CONFIG_ARCH_BERLIN is not set -# CONFIG_ARCH_BRCMSTB is not set -# CONFIG_ARCH_EXYNOS is not set -# CONFIG_ARCH_LAYERSCAPE is not set -# CONFIG_ARCH_LG1K is not set -# CONFIG_ARCH_HISI is not set -# CONFIG_ARCH_MEDIATEK is not set -# CONFIG_ARCH_MESON is not set -# CONFIG_ARCH_MVEBU is not set CONFIG_ARCH_QCOM=y CONFIG_ARCH_SDM845=y -# CONFIG_ARCH_SDM670 is not set -# CONFIG_ARCH_MSM8953 is not set -# CONFIG_ARCH_MSM8937 is not set -# CONFIG_ARCH_MSM8940 is not set -# CONFIG_ARCH_MSM8917 is not set -# CONFIG_ARCH_QM215 is not set -# CONFIG_ARCH_SDM450 is not set -# CONFIG_ARCH_SDM632 is not set -# CONFIG_ARCH_SDM429 is not set -# CONFIG_ARCH_SDM439 is not set -# CONFIG_ARCH_ROCKCHIP is not set -# CONFIG_ARCH_SEATTLE is not set -# CONFIG_ARCH_RENESAS is not set -# CONFIG_ARCH_STRATIX10 is not set -# CONFIG_ARCH_TEGRA is not set -# CONFIG_ARCH_SPRD is not set -# CONFIG_ARCH_THUNDER is not set -# CONFIG_ARCH_UNIPHIER is not set -# CONFIG_ARCH_VEXPRESS is not set -# CONFIG_ARCH_VULCAN is not set -# CONFIG_ARCH_XGENE is not set -# CONFIG_ARCH_ZX is not set -# CONFIG_ARCH_ZYNQMP is not set - -# -# Bus support -# CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -CONFIG_PCI_DOMAINS_GENERIC=y -CONFIG_PCI_SYSCALL=y -# CONFIG_PCIEPORTBUS is not set -CONFIG_PCI_BUS_ADDR_T_64BIT=y -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -# CONFIG_PCI_DEBUG is not set -# CONFIG_PCI_REALLOC_ENABLE_AUTO is not set -# CONFIG_PCI_STUB is not set -# CONFIG_PCI_IOV is not set -# CONFIG_PCI_PRI is not set -# CONFIG_PCI_PASID is not set CONFIG_PCI_MSM=y -# CONFIG_HOTPLUG_PCI is not set - -# -# PCI host controller drivers -# -# CONFIG_PCIE_DW_PLAT is not set -# CONFIG_PCI_HOST_GENERIC is not set -# CONFIG_PCI_HISI is not set -# CONFIG_PCIE_QCOM is not set -# CONFIG_PCI_HOST_THUNDER_PEM is not set -# CONFIG_PCI_HOST_THUNDER_ECAM is not set - -# -# Kernel Features -# - -# -# ARM errata workarounds via the alternatives framework -# -CONFIG_ARM64_ERRATUM_826319=y -CONFIG_ARM64_ERRATUM_827319=y -CONFIG_ARM64_ERRATUM_824069=y -CONFIG_ARM64_ERRATUM_819472=y -CONFIG_ARM64_ERRATUM_832075=y -CONFIG_ARM64_ERRATUM_845719=y -CONFIG_ARM64_ERRATUM_843419=y -CONFIG_ARM64_ERRATUM_1024718=y -CONFIG_CAVIUM_ERRATUM_22375=y -CONFIG_CAVIUM_ERRATUM_23154=y -CONFIG_CAVIUM_ERRATUM_27456=y -CONFIG_QCOM_QDF2400_ERRATUM_0065=y -CONFIG_ARM64_4K_PAGES=y -# CONFIG_ARM64_16K_PAGES is not set -# CONFIG_ARM64_64K_PAGES is not set -CONFIG_ARM64_VA_BITS_39=y -# CONFIG_ARM64_VA_BITS_48 is not set -CONFIG_ARM64_VA_BITS=39 -# CONFIG_CPU_BIG_ENDIAN is not set CONFIG_SCHED_MC=y -# CONFIG_SCHED_SMT is not set CONFIG_NR_CPUS=8 -CONFIG_HOTPLUG_CPU=y -CONFIG_ARCH_NR_GPIO=1280 -# CONFIG_NUMA is not set -# CONFIG_PREEMPT_NONE is not set -# CONFIG_PREEMPT_VOLUNTARY is not set CONFIG_PREEMPT=y -CONFIG_PREEMPT_COUNT=y CONFIG_HZ_100=y -# CONFIG_HZ_250 is not set -# CONFIG_HZ_300 is not set -# CONFIG_HZ_1000 is not set -CONFIG_HZ=100 -CONFIG_SCHED_HRTICK=y -CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y -CONFIG_ARCH_HAS_HOLES_MEMORYMODEL=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SPARSEMEM_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y -CONFIG_HAVE_ARCH_PFN_VALID=y -CONFIG_HW_PERF_EVENTS=y -CONFIG_SYS_SUPPORTS_HUGETLBFS=y -CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y -CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_SPARSEMEM_MANUAL=y -CONFIG_SPARSEMEM=y -CONFIG_HAVE_MEMORY_PRESENT=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_HAVE_MEMBLOCK=y -CONFIG_NO_BOOTMEM=y -CONFIG_MEMORY_ISOLATION=y -# CONFIG_HAVE_BOOTMEM_INFO_NODE is not set -CONFIG_SPLIT_PTLOCK_CPUS=4 -CONFIG_COMPACTION=y -CONFIG_MIGRATION=y -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_BOUNCE=y -# CONFIG_KSM is not set -CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 -# CONFIG_TRANSPARENT_HUGEPAGE is not set -# CONFIG_CLEANCACHE is not set -# CONFIG_FRONTSWAP is not set CONFIG_CMA=y -# CONFIG_CMA_DEBUG is not set -# CONFIG_CMA_DEBUGFS is not set -CONFIG_CMA_AREAS=7 -# CONFIG_ZPOOL is not set -# CONFIG_ZBUD is not set CONFIG_ZSMALLOC=y -# CONFIG_PGTABLE_MAPPING is not set -# CONFIG_ZSMALLOC_STAT is not set -CONFIG_VMAP_LAZY_PURGING_FACTOR=32 -CONFIG_GENERIC_EARLY_IOREMAP=y CONFIG_BALANCE_ANON_FILE_RECLAIM=y -# CONFIG_IDLE_PAGE_TRACKING is not set -# CONFIG_FORCE_ALLOC_FROM_DMA_ZONE is not set -CONFIG_PROCESS_RECLAIM=y -CONFIG_ARCH_SUPPORTS_SPECULATIVE_PAGE_FAULT=y -CONFIG_SPECULATIVE_PAGE_FAULT=y -CONFIG_VM_MAX_READAHEAD=128 -CONFIG_ARM64_DMA_USE_IOMMU=y -CONFIG_ARM64_DMA_IOMMU_ALIGNMENT=9 CONFIG_SECCOMP=y -# CONFIG_PARAVIRT is not set -# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set -# CONFIG_KEXEC is not set -# CONFIG_XEN is not set -CONFIG_FORCE_MAX_ZONEORDER=11 -CONFIG_UNMAP_KERNEL_AT_EL0=y CONFIG_HARDEN_BRANCH_PREDICTOR=y CONFIG_PSCI_BP_HARDENING=y -CONFIG_ARM64_SSBD=y CONFIG_ARMV8_DEPRECATED=y CONFIG_SWP_EMULATION=y CONFIG_CP15_BARRIER_EMULATION=y CONFIG_SETEND_EMULATION=y -# CONFIG_ARM64_SW_TTBR0_PAN is not set - -# -# ARMv8.1 architectural features -# -CONFIG_ARM64_HW_AFDBM=y -CONFIG_ARM64_PAN=y -# CONFIG_ARM64_LSE_ATOMICS is not set +CONFIG_ARM64_SW_TTBR0_PAN=y # CONFIG_ARM64_VHE is not set - -# -# ARMv8.2 architectural features -# -CONFIG_ARM64_UAO=y -CONFIG_RELOCATABLE=y CONFIG_RANDOMIZE_BASE=y # CONFIG_RANDOMIZE_MODULE_REGION_FULL is not set - -# -# Boot options -# -CONFIG_CMDLINE="" -CONFIG_BOOT_INFO=y # CONFIG_EFI is not set CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y -CONFIG_IMG_GZ_DTB=y -# CONFIG_IMG_DTB is not set -CONFIG_BUILD_ARM64_APPENDED_KERNEL_IMAGE_NAME="Image.gz-dtb" -CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE_NAMES="" -CONFIG_BUILD_ARM64_KERNEL_COMPRESSION_GZIP=y -# CONFIG_BUILD_ARM64_UNCOMPRESSED_KERNEL is not set -# CONFIG_BUILD_ARM64_DT_OVERLAY is not set - -# -# Userspace binary formats -# -CONFIG_BINFMT_ELF=y -CONFIG_COMPAT_BINFMT_ELF=y -CONFIG_ELFCORE=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -CONFIG_BINFMT_SCRIPT=y -# CONFIG_HAVE_AOUT is not set -# CONFIG_BINFMT_MISC is not set -CONFIG_COREDUMP=y CONFIG_COMPAT=y -CONFIG_KUSER_HELPERS=y -CONFIG_KEYS_COMPAT=y -# CONFIG_COMPAT_VDSO is not set -CONFIG_CROSS_COMPILE_ARM32="" - -# -# Power management options -# -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -# CONFIG_SUSPEND_SKIP_SYNC is not set -# CONFIG_HIBERNATION is not set -CONFIG_PM_SLEEP=y -CONFIG_PM_SLEEP_SMP=y -CONFIG_PM_AUTOSLEEP=y +CONFIG_COMPAT_VDSO=y CONFIG_PM_WAKELOCKS=y CONFIG_PM_WAKELOCKS_LIMIT=0 # CONFIG_PM_WAKELOCKS_GC is not set -CONFIG_PM=y -# CONFIG_PM_DEBUG is not set -CONFIG_PM_OPP=y -CONFIG_PM_CLK=y -CONFIG_PM_GENERIC_DOMAINS=y -CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y -CONFIG_PM_GENERIC_DOMAINS_SLEEP=y -CONFIG_PM_GENERIC_DOMAINS_OF=y -CONFIG_CPU_PM=y -CONFIG_BOEFFLA_WL_BLOCKER=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y - -# -# CPU Power Management -# - -# -# CPU Idle -# CONFIG_CPU_IDLE=y -CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y -# CONFIG_CPU_IDLE_GOV_LADDER is not set -CONFIG_CPU_IDLE_GOV_MENU=y - -# -# ARM CPU Idle Drivers -# -# CONFIG_ARM_CPUIDLE is not set -# CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED is not set - -# -# CPU Frequency scaling -# CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y CONFIG_CPU_FREQ_STAT=y -# CONFIG_CPU_FREQ_STAT_DETAILS is not set -CONFIG_CPU_FREQ_TIMES=y -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_INTERACTIVE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_GOV_POWERSAVE is not set -# CONFIG_CPU_FREQ_GOV_USERSPACE is not set -# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set -# CONFIG_CPU_FREQ_GOV_INTERACTIVE is not set -# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set -# CONFIG_CPU_BOOST is not set +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +CONFIG_CPU_BOOST=y CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y -CONFIG_CPU_INPUT_BOOST=y -CONFIG_INPUT_BOOST_DURATION_MS=100 -CONFIG_WAKE_BOOST_DURATION_MS=1000 -CONFIG_INPUT_BOOST_FREQ_LP=825600 -CONFIG_INPUT_BOOST_FREQ_PERF=979200 -CONFIG_REMOVE_INPUT_BOOST_FREQ_LP=300000 -CONFIG_REMOVE_INPUT_BOOST_FREQ_PERF=825600 - -# -# CPU frequency scaling drivers -# -# CONFIG_CPUFREQ_DT is not set -# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set -# CONFIG_ARM_KIRKWOOD_CPUFREQ is not set -# CONFIG_CPU_FREQ_MSM is not set CONFIG_NET=y -CONFIG_COMPAT_NETLINK_MESSAGES=y -CONFIG_NET_INGRESS=y -CONFIG_NET_EGRESS=y - -# -# Networking options -# CONFIG_PACKET=y -# CONFIG_PACKET_DIAG is not set CONFIG_UNIX=y -# CONFIG_UNIX_DIAG is not set -CONFIG_XFRM=y -CONFIG_XFRM_ALGO=y CONFIG_XFRM_USER=y -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set +CONFIG_XFRM_INTERFACE=y CONFIG_XFRM_STATISTICS=y -CONFIG_XFRM_IPCOMP=y CONFIG_NET_KEY=y -# CONFIG_NET_KEY_MIGRATE is not set CONFIG_INET=y -CONFIG_WIREGUARD=y -# CONFIG_WIREGUARD_DEBUG is not set CONFIG_IP_MULTICAST=y CONFIG_IP_ADVANCED_ROUTER=y -# CONFIG_IP_FIB_TRIE_STATS is not set CONFIG_IP_MULTIPLE_TABLES=y -# CONFIG_IP_ROUTE_MULTIPATH is not set CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y -# CONFIG_IP_PNP_BOOTP is not set -# CONFIG_IP_PNP_RARP is not set -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE_DEMUX is not set -CONFIG_NET_IP_TUNNEL=y -# CONFIG_IP_MROUTE is not set -# CONFIG_SYN_COOKIES is not set +CONFIG_NET_IPGRE_DEMUX=y CONFIG_NET_IPVTI=y -CONFIG_NET_UDP_TUNNEL=y -# CONFIG_NET_FOU is not set -# CONFIG_NET_FOU_IP_TUNNELS is not set CONFIG_INET_AH=y CONFIG_INET_ESP=y CONFIG_INET_IPCOMP=y -CONFIG_INET_XFRM_TUNNEL=y -CONFIG_INET_TUNNEL=y -CONFIG_INET_XFRM_MODE_TRANSPORT=y -CONFIG_INET_XFRM_MODE_TUNNEL=y -CONFIG_INET_XFRM_MODE_BEET=y -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y CONFIG_INET_UDP_DIAG=y CONFIG_INET_DIAG_DESTROY=y -CONFIG_TCP_CONG_ADVANCED=y -CONFIG_TCP_CONG_BIC=y -CONFIG_TCP_CONG_CUBIC=y -CONFIG_TCP_CONG_WESTWOOD=y -CONFIG_TCP_CONG_HTCP=y -CONFIG_TCP_CONG_HSTCP=y -CONFIG_TCP_CONG_HYBLA=y -CONFIG_TCP_CONG_VEGAS=y -# CONFIG_TCP_CONG_NV is not set -CONFIG_TCP_CONG_SCALABLE=y -CONFIG_TCP_CONG_LP=y -CONFIG_TCP_CONG_VENO=y -CONFIG_TCP_CONG_YEAH=y -CONFIG_TCP_CONG_ILLINOIS=y -CONFIG_TCP_CONG_DCTCP=y -CONFIG_TCP_CONG_CDG=y -CONFIG_TCP_CONG_BBR=y -# CONFIG_DEFAULT_BIC is not set -# CONFIG_DEFAULT_CUBIC is not set -# CONFIG_DEFAULT_HTCP is not set -# CONFIG_DEFAULT_HYBLA is not set -# CONFIG_DEFAULT_VEGAS is not set -# CONFIG_DEFAULT_VENO is not set -CONFIG_DEFAULT_WESTWOOD=y -# CONFIG_DEFAULT_DCTCP is not set -# CONFIG_DEFAULT_CDG is not set -# CONFIG_DEFAULT_BBR is not set -# CONFIG_DEFAULT_RENO is not set -CONFIG_DEFAULT_TCP_CONG="westwood" -# CONFIG_TCP_MD5SIG is not set -CONFIG_IPV6=y CONFIG_IPV6_ROUTER_PREF=y CONFIG_IPV6_ROUTE_INFO=y CONFIG_IPV6_OPTIMISTIC_DAD=y @@ -750,141 +115,50 @@ CONFIG_INET6_AH=y CONFIG_INET6_ESP=y CONFIG_INET6_IPCOMP=y CONFIG_IPV6_MIP6=y -# CONFIG_IPV6_ILA is not set -CONFIG_INET6_XFRM_TUNNEL=y -CONFIG_INET6_TUNNEL=y -CONFIG_INET6_XFRM_MODE_TRANSPORT=y -CONFIG_INET6_XFRM_MODE_TUNNEL=y -CONFIG_INET6_XFRM_MODE_BEET=y -# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set CONFIG_IPV6_VTI=y -CONFIG_IPV6_SIT=y -# CONFIG_IPV6_SIT_6RD is not set -CONFIG_IPV6_NDISC_NODETYPE=y -CONFIG_IPV6_TUNNEL=y -# CONFIG_IPV6_FOU is not set -# CONFIG_IPV6_FOU_TUNNEL is not set CONFIG_IPV6_MULTIPLE_TABLES=y CONFIG_IPV6_SUBTREES=y -# CONFIG_IPV6_MROUTE is not set -CONFIG_NETLABEL=y -CONFIG_ANDROID_PARANOID_NETWORK=y -CONFIG_NETWORK_SECMARK=y -# CONFIG_NET_PTP_CLASSIFY is not set -# CONFIG_NETWORK_PHY_TIMESTAMPING is not set CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set -CONFIG_NETFILTER_ADVANCED=y # CONFIG_BRIDGE_NETFILTER is not set - -# -# Core Netfilter Configuration -# -CONFIG_NETFILTER_INGRESS=y -CONFIG_NETFILTER_NETLINK=y -# CONFIG_NETFILTER_NETLINK_ACCT is not set -CONFIG_NETFILTER_NETLINK_QUEUE=y -CONFIG_NETFILTER_NETLINK_LOG=y CONFIG_NF_CONNTRACK=y -CONFIG_NF_LOG_COMMON=y -CONFIG_NF_CONNTRACK_MARK=y CONFIG_NF_CONNTRACK_SECMARK=y -# CONFIG_NF_CONNTRACK_ZONES is not set -CONFIG_NF_CONNTRACK_PROCFS=y CONFIG_NF_CONNTRACK_EVENTS=y -# CONFIG_NF_CONNTRACK_TIMEOUT is not set -# CONFIG_NF_CONNTRACK_TIMESTAMP is not set CONFIG_NF_CT_PROTO_DCCP=y -CONFIG_NF_CT_PROTO_GRE=y CONFIG_NF_CT_PROTO_SCTP=y CONFIG_NF_CT_PROTO_UDPLITE=y CONFIG_NF_CONNTRACK_AMANDA=y CONFIG_NF_CONNTRACK_FTP=y CONFIG_NF_CONNTRACK_H323=y CONFIG_NF_CONNTRACK_IRC=y -CONFIG_NF_CONNTRACK_BROADCAST=y CONFIG_NF_CONNTRACK_NETBIOS_NS=y -# CONFIG_NF_CONNTRACK_SNMP is not set CONFIG_NF_CONNTRACK_PPTP=y CONFIG_NF_CONNTRACK_SANE=y -# CONFIG_NF_CONNTRACK_SIP is not set CONFIG_NF_CONNTRACK_TFTP=y CONFIG_NF_CT_NETLINK=y -# CONFIG_NF_CT_NETLINK_TIMEOUT is not set -# CONFIG_NETFILTER_NETLINK_GLUE_CT is not set -CONFIG_NF_NAT=y -CONFIG_NF_NAT_NEEDED=y -CONFIG_NF_NAT_PROTO_DCCP=y -CONFIG_NF_NAT_PROTO_UDPLITE=y -CONFIG_NF_NAT_PROTO_SCTP=y -CONFIG_NF_NAT_AMANDA=y -CONFIG_NF_NAT_FTP=y -CONFIG_NF_NAT_IRC=y -# CONFIG_NF_NAT_SIP is not set -CONFIG_NF_NAT_TFTP=y -CONFIG_NF_NAT_REDIRECT=y -# CONFIG_NF_TABLES is not set -CONFIG_NETFILTER_XTABLES=y - -# -# Xtables combined modules -# -CONFIG_NETFILTER_XT_MARK=y -CONFIG_NETFILTER_XT_CONNMARK=y - -# -# Xtables targets -# -# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set CONFIG_NETFILTER_XT_TARGET_CLASSIFY=y CONFIG_NETFILTER_XT_TARGET_CONNMARK=y CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=y -CONFIG_NETFILTER_XT_TARGET_CT=y -# CONFIG_NETFILTER_XT_TARGET_DSCP is not set -CONFIG_NETFILTER_XT_TARGET_HL=y -# CONFIG_NETFILTER_XT_TARGET_HMARK is not set CONFIG_NETFILTER_XT_TARGET_IDLETIMER=y CONFIG_NETFILTER_XT_TARGET_HARDIDLETIMER=y -# CONFIG_NETFILTER_XT_TARGET_LED is not set CONFIG_NETFILTER_XT_TARGET_LOG=y CONFIG_NETFILTER_XT_TARGET_MARK=y -CONFIG_NETFILTER_XT_NAT=y -CONFIG_NETFILTER_XT_TARGET_NETMAP=y CONFIG_NETFILTER_XT_TARGET_NFLOG=y CONFIG_NETFILTER_XT_TARGET_NFQUEUE=y CONFIG_NETFILTER_XT_TARGET_NOTRACK=y -# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set -CONFIG_NETFILTER_XT_TARGET_REDIRECT=y CONFIG_NETFILTER_XT_TARGET_TEE=y CONFIG_NETFILTER_XT_TARGET_TPROXY=y CONFIG_NETFILTER_XT_TARGET_TRACE=y CONFIG_NETFILTER_XT_TARGET_SECMARK=y CONFIG_NETFILTER_XT_TARGET_TCPMSS=y -# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set - -# -# Xtables matches -# -# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set CONFIG_NETFILTER_XT_MATCH_BPF=y -# CONFIG_NETFILTER_XT_MATCH_CGROUP is not set -# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set CONFIG_NETFILTER_XT_MATCH_COMMENT=y -# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set -# CONFIG_NETFILTER_XT_MATCH_CONNLABEL is not set CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=y CONFIG_NETFILTER_XT_MATCH_CONNMARK=y CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y -# CONFIG_NETFILTER_XT_MATCH_CPU is not set -# CONFIG_NETFILTER_XT_MATCH_DCCP is not set -# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set CONFIG_NETFILTER_XT_MATCH_DSCP=y -CONFIG_NETFILTER_XT_MATCH_ECN=y CONFIG_NETFILTER_XT_MATCH_ESP=y CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=y CONFIG_NETFILTER_XT_MATCH_HELPER=y -CONFIG_NETFILTER_XT_MATCH_HL=y -# CONFIG_NETFILTER_XT_MATCH_IPCOMP is not set CONFIG_NETFILTER_XT_MATCH_IPRANGE=y # CONFIG_NETFILTER_XT_MATCH_L2TP is not set CONFIG_NETFILTER_XT_MATCH_LENGTH=y @@ -892,43 +166,18 @@ CONFIG_NETFILTER_XT_MATCH_LIMIT=y CONFIG_NETFILTER_XT_MATCH_MAC=y CONFIG_NETFILTER_XT_MATCH_MARK=y CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y -# CONFIG_NETFILTER_XT_MATCH_NFACCT is not set -# CONFIG_NETFILTER_XT_MATCH_OSF is not set -# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +CONFIG_NETFILTER_XT_MATCH_OWNER=y CONFIG_NETFILTER_XT_MATCH_POLICY=y CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y -CONFIG_NETFILTER_XT_MATCH_QTAGUID=y CONFIG_NETFILTER_XT_MATCH_QUOTA=y CONFIG_NETFILTER_XT_MATCH_QUOTA2=y -# CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG is not set -# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set -# CONFIG_NETFILTER_XT_MATCH_REALM is not set -# CONFIG_NETFILTER_XT_MATCH_RECENT is not set -# CONFIG_NETFILTER_XT_MATCH_SCTP is not set CONFIG_NETFILTER_XT_MATCH_SOCKET=y CONFIG_NETFILTER_XT_MATCH_STATE=y CONFIG_NETFILTER_XT_MATCH_STATISTIC=y CONFIG_NETFILTER_XT_MATCH_STRING=y -# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set CONFIG_NETFILTER_XT_MATCH_TIME=y CONFIG_NETFILTER_XT_MATCH_U32=y -# CONFIG_IP_SET is not set -# CONFIG_IP_VS is not set - -# -# IP: Netfilter Configuration -# -CONFIG_NF_DEFRAG_IPV4=y CONFIG_NF_CONNTRACK_IPV4=y -CONFIG_NF_DUP_IPV4=y -# CONFIG_NF_LOG_ARP is not set -CONFIG_NF_LOG_IPV4=y -CONFIG_NF_REJECT_IPV4=y -CONFIG_NF_NAT_IPV4=y -CONFIG_NF_NAT_MASQUERADE_IPV4=y -CONFIG_NF_NAT_PROTO_GRE=y -CONFIG_NF_NAT_PPTP=y -CONFIG_NF_NAT_H323=y CONFIG_IP_NF_IPTABLES=y CONFIG_IP_NF_MATCH_AH=y CONFIG_IP_NF_MATCH_ECN=y @@ -936,858 +185,97 @@ CONFIG_IP_NF_MATCH_RPFILTER=y CONFIG_IP_NF_MATCH_TTL=y CONFIG_IP_NF_FILTER=y CONFIG_IP_NF_TARGET_REJECT=y -# CONFIG_IP_NF_TARGET_SYNPROXY is not set CONFIG_IP_NF_NAT=y CONFIG_IP_NF_TARGET_MASQUERADE=y -# CONFIG_IP_NF_TARGET_NATTYPE_MODULE is not set CONFIG_IP_NF_TARGET_NETMAP=y CONFIG_IP_NF_TARGET_REDIRECT=y CONFIG_IP_NF_MANGLE=y -# CONFIG_IP_NF_TARGET_CLUSTERIP is not set -# CONFIG_IP_NF_TARGET_ECN is not set -CONFIG_IP_NF_TARGET_TTL=y CONFIG_IP_NF_RAW=y CONFIG_IP_NF_SECURITY=y CONFIG_IP_NF_ARPTABLES=y CONFIG_IP_NF_ARPFILTER=y CONFIG_IP_NF_ARP_MANGLE=y - -# -# IPv6: Netfilter Configuration -# -CONFIG_NF_DEFRAG_IPV6=y CONFIG_NF_CONNTRACK_IPV6=y -CONFIG_NF_DUP_IPV6=y -CONFIG_NF_REJECT_IPV6=y -CONFIG_NF_LOG_IPV6=y -# CONFIG_NF_NAT_IPV6 is not set CONFIG_IP6_NF_IPTABLES=y CONFIG_IP6_NF_IPTABLES_128=y -# CONFIG_IP6_NF_MATCH_AH is not set -# CONFIG_IP6_NF_MATCH_EUI64 is not set -# CONFIG_IP6_NF_MATCH_FRAG is not set -# CONFIG_IP6_NF_MATCH_OPTS is not set -# CONFIG_IP6_NF_MATCH_HL is not set -# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set -# CONFIG_IP6_NF_MATCH_MH is not set CONFIG_IP6_NF_MATCH_RPFILTER=y -# CONFIG_IP6_NF_MATCH_RT is not set -# CONFIG_IP6_NF_TARGET_HL is not set CONFIG_IP6_NF_FILTER=y CONFIG_IP6_NF_TARGET_REJECT=y -# CONFIG_IP6_NF_TARGET_SYNPROXY is not set CONFIG_IP6_NF_MANGLE=y CONFIG_IP6_NF_RAW=y -# CONFIG_IP6_NF_SECURITY is not set -# CONFIG_IP6_NF_NAT is not set CONFIG_BRIDGE_NF_EBTABLES=y CONFIG_BRIDGE_EBT_BROUTE=y -# CONFIG_BRIDGE_EBT_T_FILTER is not set -# CONFIG_BRIDGE_EBT_T_NAT is not set -# CONFIG_BRIDGE_EBT_802_3 is not set -# CONFIG_BRIDGE_EBT_AMONG is not set -# CONFIG_BRIDGE_EBT_ARP is not set -# CONFIG_BRIDGE_EBT_IP is not set -# CONFIG_BRIDGE_EBT_IP6 is not set -# CONFIG_BRIDGE_EBT_LIMIT is not set -# CONFIG_BRIDGE_EBT_MARK is not set -# CONFIG_BRIDGE_EBT_PKTTYPE is not set -# CONFIG_BRIDGE_EBT_STP is not set -# CONFIG_BRIDGE_EBT_VLAN is not set -# CONFIG_BRIDGE_EBT_ARPREPLY is not set -# CONFIG_BRIDGE_EBT_DNAT is not set -# CONFIG_BRIDGE_EBT_MARK_T is not set -# CONFIG_BRIDGE_EBT_REDIRECT is not set -# CONFIG_BRIDGE_EBT_SNAT is not set -# CONFIG_BRIDGE_EBT_LOG is not set -# CONFIG_BRIDGE_EBT_NFLOG is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_RDS is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set CONFIG_L2TP=y -# CONFIG_L2TP_DEBUGFS is not set CONFIG_L2TP_V3=y CONFIG_L2TP_IP=y CONFIG_L2TP_ETH=y -CONFIG_STP=y CONFIG_BRIDGE=y -CONFIG_BRIDGE_IGMP_SNOOPING=y -CONFIG_HAVE_NET_DSA=y -# CONFIG_NET_DSA is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -CONFIG_LLC=y -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_PHONET is not set -# CONFIG_6LOWPAN is not set -# CONFIG_IEEE802154 is not set CONFIG_NET_SCHED=y - -# -# Queueing/Scheduling -# -# CONFIG_NET_SCH_CBQ is not set CONFIG_NET_SCH_HTB=y -# CONFIG_NET_SCH_HFSC is not set CONFIG_NET_SCH_PRIO=y CONFIG_NET_SCH_MULTIQ=y -# CONFIG_NET_SCH_RED is not set -# CONFIG_NET_SCH_SFB is not set -# CONFIG_NET_SCH_SFQ is not set -# CONFIG_NET_SCH_TEQL is not set -# CONFIG_NET_SCH_TBF is not set -# CONFIG_NET_SCH_GRED is not set -# CONFIG_NET_SCH_DSMARK is not set -# CONFIG_NET_SCH_NETEM is not set -# CONFIG_NET_SCH_DRR is not set -# CONFIG_NET_SCH_MQPRIO is not set -# CONFIG_NET_SCH_CHOKE is not set -# CONFIG_NET_SCH_QFQ is not set -# CONFIG_NET_SCH_CODEL is not set -# CONFIG_NET_SCH_FQ_CODEL is not set -# CONFIG_NET_SCH_FQ is not set -# CONFIG_NET_SCH_HHF is not set -# CONFIG_NET_SCH_PIE is not set CONFIG_NET_SCH_INGRESS=y -# CONFIG_NET_SCH_PLUG is not set - -# -# Classification -# -CONFIG_NET_CLS=y -# CONFIG_NET_CLS_BASIC is not set -# CONFIG_NET_CLS_TCINDEX is not set -# CONFIG_NET_CLS_ROUTE4 is not set CONFIG_NET_CLS_FW=y CONFIG_NET_CLS_U32=y -# CONFIG_CLS_U32_PERF is not set -# CONFIG_CLS_U32_MARK is not set -# CONFIG_NET_CLS_RSVP is not set -# CONFIG_NET_CLS_RSVP6 is not set -# CONFIG_NET_CLS_FLOW is not set -# CONFIG_NET_CLS_CGROUP is not set -# CONFIG_NET_CLS_BPF is not set -# CONFIG_NET_CLS_FLOWER is not set -# CONFIG_NET_CLS_MATCHALL is not set +CONFIG_NET_CLS_BPF=y CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_STACK=32 CONFIG_NET_EMATCH_CMP=y CONFIG_NET_EMATCH_NBYTE=y CONFIG_NET_EMATCH_U32=y CONFIG_NET_EMATCH_META=y CONFIG_NET_EMATCH_TEXT=y CONFIG_NET_CLS_ACT=y -# CONFIG_NET_ACT_POLICE is not set CONFIG_NET_ACT_GACT=y -# CONFIG_GACT_PROB is not set CONFIG_NET_ACT_MIRRED=y -# CONFIG_NET_ACT_IPT is not set -# CONFIG_NET_ACT_NAT is not set -# CONFIG_NET_ACT_PEDIT is not set -# CONFIG_NET_ACT_SIMP is not set CONFIG_NET_ACT_SKBEDIT=y -# CONFIG_NET_ACT_CSUM is not set -# CONFIG_NET_ACT_VLAN is not set -# CONFIG_NET_ACT_BPF is not set -# CONFIG_NET_ACT_CONNMARK is not set -# CONFIG_NET_ACT_SKBMOD is not set -# CONFIG_NET_ACT_IFE is not set -# CONFIG_NET_ACT_TUNNEL_KEY is not set -# CONFIG_NET_CLS_IND is not set -CONFIG_NET_SCH_FIFO=y -# CONFIG_DCB is not set -# CONFIG_DNS_RESOLVER is not set -# CONFIG_BATMAN_ADV is not set -# CONFIG_OPENVSWITCH is not set -# CONFIG_VSOCKETS is not set -# CONFIG_NETLINK_DIAG is not set -# CONFIG_MPLS is not set -# CONFIG_HSR is not set -# CONFIG_NET_SWITCHDEV is not set -# CONFIG_NET_L3_MASTER_DEV is not set -# CONFIG_QRTR is not set -# CONFIG_NET_NCSI is not set CONFIG_RMNET_DATA=y CONFIG_RMNET_DATA_FC=y -# CONFIG_RMNET_DATA_DEBUG_PKT is not set -CONFIG_RPS=y -CONFIG_RFS_ACCEL=y -CONFIG_XPS=y -# CONFIG_CGROUP_NET_PRIO is not set -# CONFIG_CGROUP_NET_CLASSID is not set -CONFIG_NET_RX_BUSY_POLL=y -CONFIG_BQL=y -CONFIG_NET_FLOW_LIMIT=y CONFIG_SOCKEV_NLMCAST=y - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NET_DROP_MONITOR is not set -# CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set -# CONFIG_IRDA is not set CONFIG_BT=y -CONFIG_BT_BREDR=y -# CONFIG_BT_RFCOMM is not set -# CONFIG_BT_BNEP is not set -# CONFIG_BT_HIDP is not set -CONFIG_BT_HS=y -CONFIG_BT_LE=y -# CONFIG_BT_LEDS is not set -# CONFIG_BT_SELFTEST is not set -CONFIG_BT_DEBUGFS=y - -# -# Bluetooth device drivers -# -# CONFIG_BT_HCIBTUSB is not set -# CONFIG_BT_HCIBTSDIO is not set -# CONFIG_BT_HCIUART is not set -# CONFIG_BT_HCIBCM203X is not set -# CONFIG_BT_HCIBFUSB is not set -# CONFIG_BT_HCIVHCI is not set -# CONFIG_BT_MRVL is not set CONFIG_MSM_BT_POWER=y -CONFIG_BTFM_SLIM=y -CONFIG_BTFM_SLIM_WCN3990=y -# CONFIG_AF_RXRPC is not set -# CONFIG_AF_KCM is not set -# CONFIG_STREAM_PARSER is not set -CONFIG_FIB_RULES=y -CONFIG_WIRELESS=y -CONFIG_WIRELESS_EXT=y -CONFIG_WEXT_CORE=y -CONFIG_WEXT_PROC=y -CONFIG_WEXT_SPY=y -CONFIG_WEXT_PRIV=y CONFIG_CFG80211=y -CONFIG_NL80211_TESTMODE=y -# CONFIG_CFG80211_DEVELOPER_WARNINGS is not set CONFIG_CFG80211_CERTIFICATION_ONUS=y CONFIG_CFG80211_REG_CELLULAR_HINTS=y -# CONFIG_CFG80211_REG_RELAX_NO_IR is not set -CONFIG_CFG80211_DEFAULT_PS=y -# CONFIG_CFG80211_DEBUGFS is not set CONFIG_CFG80211_INTERNAL_REGDB=y -CONFIG_CFG80211_CRDA_SUPPORT=y -# CONFIG_CFG80211_WEXT is not set -# CONFIG_LIB80211 is not set -# CONFIG_MAC80211 is not set -CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 -# CONFIG_WIMAX is not set CONFIG_RFKILL=y -CONFIG_RFKILL_PM=y -CONFIG_RFKILL_LEDS=y -# CONFIG_RFKILL_INPUT is not set -# CONFIG_RFKILL_REGULATOR is not set -# CONFIG_RFKILL_GPIO is not set -# CONFIG_NET_9P is not set -# CONFIG_CAIF is not set -# CONFIG_CEPH_LIB is not set -# CONFIG_NFC is not set CONFIG_NFC_NQ=y -# CONFIG_LWTUNNEL is not set -CONFIG_DST_CACHE=y -# CONFIG_NET_DEVLINK is not set -CONFIG_MAY_USE_DEVLINK=y CONFIG_IPC_ROUTER=y CONFIG_IPC_ROUTER_SECURITY=y -CONFIG_IPC_ROUTER_NODE_ID=1 -# CONFIG_IPC_ROUTER_FIFO_XPRT is not set -CONFIG_HAVE_EBPF_JIT=y - -# -# Device Drivers -# -CONFIG_ARM_AMBA=y - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER=y -CONFIG_UEVENT_HELPER_PATH="" -# CONFIG_DEVTMPFS is not set -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=y -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_EXTRA_FIRMWARE="" -CONFIG_FW_LOADER_USER_HELPER=y CONFIG_FW_LOADER_USER_HELPER_FALLBACK=y -# CONFIG_FW_CACHE is not set -CONFIG_ALLOW_DEV_COREDUMP=y -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_GENERIC_CPU_DEVICES is not set -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_SOC_BUS=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y -CONFIG_REGMAP_SPI=y -CONFIG_REGMAP_SPMI=y -CONFIG_REGMAP_MMIO=y -# CONFIG_AQT_REGMAP is not set -# CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS is not set -# CONFIG_REGMAP_SND_DIGCDC is not set -CONFIG_DMA_SHARED_BUFFER=y -# CONFIG_FENCE_TRACE is not set +CONFIG_REGMAP_SWR=y CONFIG_DMA_CMA=y - -# -# Default contiguous memory area size: -# -CONFIG_CMA_SIZE_MBYTES=16 -CONFIG_CMA_SIZE_SEL_MBYTES=y -# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set -# CONFIG_CMA_SIZE_SEL_MIN is not set -# CONFIG_CMA_SIZE_SEL_MAX is not set -CONFIG_CMA_ALIGNMENT=8 - -# -# Bus devices -# -# CONFIG_ARM_CCI400_PMU is not set -# CONFIG_ARM_CCI5xx_PMU is not set -# CONFIG_ARM_CCN is not set -# CONFIG_QCOM_EBI2 is not set -# CONFIG_VEXPRESS_CONFIG is not set -# CONFIG_CONNECTOR is not set -# CONFIG_MTD is not set -CONFIG_DTC=y -CONFIG_OF=y -# CONFIG_OF_UNITTEST is not set -CONFIG_OF_FLATTREE=y -CONFIG_OF_EARLY_FLATTREE=y -CONFIG_OF_KOBJ=y -CONFIG_OF_ADDRESS=y -CONFIG_OF_ADDRESS_PCI=y -CONFIG_OF_IRQ=y -CONFIG_OF_NET=y -CONFIG_OF_MDIO=y -CONFIG_OF_PCI=y -CONFIG_OF_PCI_IRQ=y -CONFIG_OF_RESERVED_MEM=y -CONFIG_OF_SLIMBUS=y -# CONFIG_OF_OVERLAY is not set -CONFIG_OF_BATTERYDATA=y -# CONFIG_PARPORT is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_NULL_BLK is not set -# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set CONFIG_ZRAM=y -CONFIG_ZRAM_WRITEBACK=y -# CONFIG_ZRAM_MEMORY_TRACKING is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_DRBD is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SKD is not set -# CONFIG_BLK_DEV_SX8 is not set +CONFIG_BLK_DEV_LOOP_MIN_COUNT=16 CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=8192 -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_BLK_DEV_RBD is not set -# CONFIG_BLK_DEV_RSXX is not set -# CONFIG_BLK_DEV_NVME is not set -# CONFIG_NVME_TARGET is not set - -# -# Misc devices -# -# CONFIG_SENSORS_LIS3LV02D is not set -# CONFIG_AD525X_DPOT is not set -# CONFIG_DUMMY_IRQ is not set -# CONFIG_PHANTOM is not set -# CONFIG_SGI_IOC4 is not set -# CONFIG_TIFM_CORE is not set -# CONFIG_ICS932S401 is not set -# CONFIG_ENCLOSURE_SERVICES is not set -# CONFIG_HP_ILO is not set -# CONFIG_QCOM_COINCELL is not set -# CONFIG_APDS9802ALS is not set -# CONFIG_ISL29003 is not set -# CONFIG_ISL29020 is not set -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_SENSORS_BH1770 is not set -# CONFIG_SENSORS_APDS990X is not set -# CONFIG_HMC6352 is not set -# CONFIG_DS1682 is not set -# CONFIG_TI_DAC7512 is not set -# CONFIG_USB_SWITCH_FSA9480 is not set -# CONFIG_LATTICE_ECP3_CONFIG is not set -# CONFIG_SRAM is not set -CONFIG_HDCP_QSEECOM=y CONFIG_QSEECOM=y CONFIG_UID_SYS_STATS=y -# CONFIG_UID_SYS_STATS_DEBUG is not set CONFIG_MEMORY_STATE_TIME=y -# CONFIG_QPNP_MISC is not set -# CONFIG_RTMV20 is not set -# CONFIG_C2PORT is not set - -# -# EEPROM support -# -# CONFIG_EEPROM_AT24 is not set -# CONFIG_EEPROM_AT25 is not set -# CONFIG_EEPROM_LEGACY is not set -# CONFIG_EEPROM_MAX6875 is not set -# CONFIG_EEPROM_93CX6 is not set -# CONFIG_EEPROM_93XX46 is not set -# CONFIG_CB710_CORE is not set - -# -# Texas Instruments shared transport line discipline -# -# CONFIG_TI_ST is not set -# CONFIG_SENSORS_LIS3_SPI is not set -# CONFIG_SENSORS_LIS3_I2C is not set - -# -# Altera FPGA firmware download module -# -# CONFIG_ALTERA_STAPL is not set - -# -# Intel MIC Bus Driver -# - -# -# SCIF Bus Driver -# - -# -# VOP Bus Driver -# - -# -# Intel MIC Host Driver -# - -# -# Intel MIC Card Driver -# - -# -# SCIF Driver -# - -# -# Intel MIC Coprocessor State Management (COSM) Drivers -# - -# -# VOP Driver -# -# CONFIG_GENWQE is not set -# CONFIG_ECHO is not set -# CONFIG_CXL_BASE is not set -# CONFIG_CXL_AFU_DRIVER_OPS is not set - -# -# FingerprintCard fingerprint driver -# -# CONFIG_FPR_FPC is not set - -# -# SCSI device support -# -CONFIG_SCSI_MOD=y -# CONFIG_RAID_ATTRS is not set CONFIG_SCSI=y -CONFIG_SCSI_DMA=y -# CONFIG_SCSI_NETLINK is not set -# CONFIG_SCSI_MQ_DEFAULT is not set -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -# CONFIG_BLK_DEV_SR is not set CONFIG_CHR_DEV_SG=y CONFIG_CHR_DEV_SCH=y CONFIG_SCSI_CONSTANTS=y -# CONFIG_SCSI_LOGGING is not set CONFIG_SCSI_SCAN_ASYNC=y - -# -# SCSI Transports -# -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_SAS_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -CONFIG_SCSI_LOWLEVEL=y -# CONFIG_ISCSI_TCP is not set -# CONFIG_ISCSI_BOOT_SYSFS is not set -# CONFIG_SCSI_CXGB3_ISCSI is not set -# CONFIG_SCSI_CXGB4_ISCSI is not set -# CONFIG_SCSI_BNX2_ISCSI is not set -# CONFIG_BE2ISCSI is not set -# CONFIG_BLK_DEV_3W_XXXX_RAID is not set -# CONFIG_SCSI_HPSA is not set -# CONFIG_SCSI_3W_9XXX is not set -# CONFIG_SCSI_3W_SAS is not set -# CONFIG_SCSI_ACARD is not set -# CONFIG_SCSI_AACRAID is not set -# CONFIG_SCSI_AIC7XXX is not set -# CONFIG_SCSI_AIC79XX is not set -# CONFIG_SCSI_AIC94XX is not set -# CONFIG_SCSI_HISI_SAS is not set -# CONFIG_SCSI_MVSAS is not set -# CONFIG_SCSI_MVUMI is not set -# CONFIG_SCSI_ADVANSYS is not set -# CONFIG_SCSI_ARCMSR is not set -# CONFIG_SCSI_ESAS2R is not set -# CONFIG_MEGARAID_NEWGEN is not set -# CONFIG_MEGARAID_LEGACY is not set -# CONFIG_MEGARAID_SAS is not set -# CONFIG_SCSI_MPT3SAS is not set -# CONFIG_SCSI_MPT2SAS is not set -# CONFIG_SCSI_SMARTPQI is not set CONFIG_SCSI_UFSHCD=y -# CONFIG_SCSI_UFSHCD_PCI is not set CONFIG_SCSI_UFSHCD_PLATFORM=y CONFIG_SCSI_UFS_QCOM=y CONFIG_SCSI_UFS_QCOM_ICE=y -# CONFIG_SCSI_UFSHCD_CMD_LOGGING is not set -CONFIG_SCSI_UFSHCD_HPB_ACTIVATE=1 -# CONFIG_SCSI_HPTIOP is not set -# CONFIG_SCSI_SNIC is not set -# CONFIG_SCSI_DMX3191D is not set -# CONFIG_SCSI_FUTURE_DOMAIN is not set -# CONFIG_SCSI_IPS is not set -# CONFIG_SCSI_INITIO is not set -# CONFIG_SCSI_INIA100 is not set -# CONFIG_SCSI_STEX is not set -# CONFIG_SCSI_SYM53C8XX_2 is not set -# CONFIG_SCSI_QLOGIC_1280 is not set -# CONFIG_SCSI_QLA_ISCSI is not set -# CONFIG_SCSI_DC395x is not set -# CONFIG_SCSI_AM53C974 is not set -# CONFIG_SCSI_WD719X is not set -# CONFIG_SCSI_DEBUG is not set -# CONFIG_SCSI_PMCRAID is not set -# CONFIG_SCSI_PM8001 is not set -# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set -# CONFIG_SCSI_DH is not set -# CONFIG_SCSI_OSD_INITIATOR is not set -CONFIG_HAVE_PATA_PLATFORM=y -# CONFIG_ATA is not set CONFIG_MD=y -# CONFIG_BLK_DEV_MD is not set -# CONFIG_BCACHE is not set -CONFIG_BLK_DEV_DM_BUILTIN=y CONFIG_BLK_DEV_DM=y -# CONFIG_DM_MQ_DEFAULT is not set -# CONFIG_DM_DEBUG is not set -CONFIG_DM_BUFIO=y -# CONFIG_DM_DEBUG_BLOCK_STACK_TRACING is not set CONFIG_DM_CRYPT=y CONFIG_DM_REQ_CRYPT=y -# CONFIG_DM_DEFAULT_KEY is not set -# CONFIG_DM_SNAPSHOT is not set -# CONFIG_DM_THIN_PROVISIONING is not set -# CONFIG_DM_CACHE is not set -# CONFIG_DM_ERA is not set -# CONFIG_DM_MIRROR is not set -# CONFIG_DM_RAID is not set -# CONFIG_DM_ZERO is not set -# CONFIG_DM_MULTIPATH is not set -# CONFIG_DM_DELAY is not set CONFIG_DM_UEVENT=y -# CONFIG_DM_FLAKEY is not set CONFIG_DM_VERITY=y -CONFIG_DM_VERITY_HASH_PREFETCH_MIN_SIZE_128=y -CONFIG_DM_VERITY_HASH_PREFETCH_MIN_SIZE=1 CONFIG_DM_VERITY_FEC=y -# CONFIG_DM_SWITCH is not set -# CONFIG_DM_LOG_WRITES is not set -# CONFIG_DM_ANDROID_VERITY_AT_MOST_ONCE_DEFAULT_ENABLED is not set -# CONFIG_TARGET_CORE is not set -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_FIREWIRE is not set -# CONFIG_FIREWIRE_NOSY is not set +CONFIG_DM_BOW=y CONFIG_NETDEVICES=y -CONFIG_MII=y -CONFIG_NET_CORE=y CONFIG_BONDING=y CONFIG_DUMMY=y -# CONFIG_EQUALIZER is not set -# CONFIG_NET_FC is not set -# CONFIG_IFB is not set -# CONFIG_NET_TEAM is not set -# CONFIG_MACVLAN is not set -# CONFIG_VXLAN is not set -# CONFIG_GENEVE is not set -# CONFIG_GTP is not set -# CONFIG_MACSEC is not set -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_RMNET_IPLO is not set CONFIG_TUN=y -# CONFIG_TUN_VNET_CROSS_LE is not set -# CONFIG_VETH is not set -# CONFIG_NLMON is not set -# CONFIG_ARCNET is not set - -# -# CAIF transport drivers -# - -# -# Distributed Switch Architecture drivers -# -CONFIG_ETHERNET=y -CONFIG_NET_VENDOR_3COM=y -# CONFIG_VORTEX is not set -# CONFIG_TYPHOON is not set -CONFIG_NET_VENDOR_ADAPTEC=y -# CONFIG_ADAPTEC_STARFIRE is not set -CONFIG_NET_VENDOR_AGERE=y -# CONFIG_ET131X is not set -CONFIG_NET_VENDOR_ALTEON=y -# CONFIG_ACENIC is not set -# CONFIG_ALTERA_TSE is not set -CONFIG_NET_VENDOR_AMAZON=y -CONFIG_NET_VENDOR_AMD=y -# CONFIG_AMD8111_ETH is not set -# CONFIG_PCNET32 is not set -# CONFIG_AMD_XGBE is not set -CONFIG_NET_VENDOR_ARC=y -# CONFIG_ARC_EMAC is not set -# CONFIG_EMAC_ROCKCHIP is not set -CONFIG_NET_VENDOR_ATHEROS=y -# CONFIG_ATL2 is not set -# CONFIG_ATL1 is not set -# CONFIG_ATL1E is not set -# CONFIG_ATL1C is not set -# CONFIG_ALX is not set -# CONFIG_NET_VENDOR_AURORA is not set -CONFIG_NET_CADENCE=y -# CONFIG_MACB is not set -CONFIG_NET_VENDOR_BROADCOM=y -# CONFIG_B44 is not set -# CONFIG_BCMGENET is not set -# CONFIG_BNX2 is not set -# CONFIG_CNIC is not set -# CONFIG_TIGON3 is not set -# CONFIG_BNX2X is not set -# CONFIG_SYSTEMPORT is not set -# CONFIG_BNXT is not set -CONFIG_NET_VENDOR_BROCADE=y -# CONFIG_BNA is not set -CONFIG_NET_VENDOR_CAVIUM=y -# CONFIG_THUNDER_NIC_PF is not set -# CONFIG_THUNDER_NIC_VF is not set -# CONFIG_THUNDER_NIC_BGX is not set -# CONFIG_THUNDER_NIC_RGX is not set -# CONFIG_LIQUIDIO is not set -CONFIG_NET_VENDOR_CHELSIO=y -# CONFIG_CHELSIO_T1 is not set -# CONFIG_CHELSIO_T3 is not set -# CONFIG_CHELSIO_T4 is not set -# CONFIG_CHELSIO_T4VF is not set -CONFIG_NET_VENDOR_CISCO=y -# CONFIG_ENIC is not set -# CONFIG_DNET is not set -CONFIG_NET_VENDOR_DEC=y -# CONFIG_NET_TULIP is not set -CONFIG_NET_VENDOR_DLINK=y -# CONFIG_DL2K is not set -# CONFIG_SUNDANCE is not set -CONFIG_NET_VENDOR_EMULEX=y -# CONFIG_BE2NET is not set -CONFIG_NET_VENDOR_EZCHIP=y -# CONFIG_EZCHIP_NPS_MANAGEMENT_ENET is not set -CONFIG_NET_VENDOR_EXAR=y -# CONFIG_S2IO is not set -# CONFIG_VXGE is not set -CONFIG_NET_VENDOR_HISILICON=y -# CONFIG_HIX5HD2_GMAC is not set -# CONFIG_HISI_FEMAC is not set -# CONFIG_HIP04_ETH is not set -# CONFIG_HNS is not set -# CONFIG_HNS_DSAF is not set -# CONFIG_HNS_ENET is not set -CONFIG_NET_VENDOR_HP=y -# CONFIG_HP100 is not set -CONFIG_NET_VENDOR_INTEL=y -# CONFIG_E100 is not set -# CONFIG_E1000 is not set -# CONFIG_E1000E is not set -# CONFIG_IGB is not set -# CONFIG_IGBVF is not set -# CONFIG_IXGB is not set -# CONFIG_IXGBE is not set -# CONFIG_IXGBEVF is not set -# CONFIG_I40E is not set -# CONFIG_I40EVF is not set -# CONFIG_FM10K is not set -CONFIG_NET_VENDOR_I825XX=y -# CONFIG_JME is not set -CONFIG_NET_VENDOR_MARVELL=y -# CONFIG_MVMDIO is not set -# CONFIG_MVNETA_BM is not set -# CONFIG_SKGE is not set CONFIG_SKY2=y -# CONFIG_SKY2_DEBUG is not set -CONFIG_NET_VENDOR_MELLANOX=y -# CONFIG_MLX4_EN is not set -# CONFIG_MLX4_CORE is not set -# CONFIG_MLX5_CORE is not set -# CONFIG_MLXSW_CORE is not set -CONFIG_NET_VENDOR_MICREL=y -# CONFIG_KS8842 is not set -# CONFIG_KS8851 is not set -# CONFIG_KS8851_MLL is not set -# CONFIG_KSZ884X_PCI is not set -CONFIG_NET_VENDOR_MICROCHIP=y -# CONFIG_ENC28J60 is not set -# CONFIG_ENCX24J600 is not set -CONFIG_NET_VENDOR_MYRI=y -# CONFIG_MYRI10GE is not set -# CONFIG_FEALNX is not set -CONFIG_NET_VENDOR_NATSEMI=y -# CONFIG_NATSEMI is not set -# CONFIG_NS83820 is not set -CONFIG_NET_VENDOR_NETRONOME=y -# CONFIG_NFP_NETVF is not set -CONFIG_NET_VENDOR_8390=y -# CONFIG_NE2K_PCI is not set -CONFIG_NET_VENDOR_NVIDIA=y -# CONFIG_FORCEDETH is not set -CONFIG_NET_VENDOR_OKI=y -# CONFIG_ETHOC is not set -CONFIG_NET_PACKET_ENGINE=y -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -CONFIG_NET_VENDOR_QLOGIC=y -# CONFIG_QLA3XXX is not set -# CONFIG_QLCNIC is not set -# CONFIG_QLGE is not set -# CONFIG_NETXEN_NIC is not set -# CONFIG_QED is not set -CONFIG_NET_VENDOR_QUALCOMM=y -# CONFIG_QCA7000 is not set -# CONFIG_QCOM_EMAC is not set -CONFIG_NET_VENDOR_REALTEK=y -# CONFIG_8139CP is not set -# CONFIG_8139TOO is not set -# CONFIG_R8169 is not set -CONFIG_NET_VENDOR_RENESAS=y -CONFIG_NET_VENDOR_RDC=y -# CONFIG_R6040 is not set -CONFIG_NET_VENDOR_ROCKER=y -CONFIG_NET_VENDOR_SAMSUNG=y -# CONFIG_SXGBE_ETH is not set -CONFIG_NET_VENDOR_SEEQ=y -CONFIG_NET_VENDOR_SILAN=y -# CONFIG_SC92031 is not set -CONFIG_NET_VENDOR_SIS=y -# CONFIG_SIS900 is not set -# CONFIG_SIS190 is not set -# CONFIG_SFC is not set -CONFIG_NET_VENDOR_SMSC=y -# CONFIG_SMC91X is not set -# CONFIG_EPIC100 is not set CONFIG_SMSC911X=y -# CONFIG_SMSC911X_ARCH_HOOKS is not set -# CONFIG_SMSC9420 is not set -CONFIG_NET_VENDOR_STMICRO=y -# CONFIG_STMMAC_ETH is not set -CONFIG_NET_VENDOR_SUN=y -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_CASSINI is not set -# CONFIG_NIU is not set -CONFIG_NET_VENDOR_SYNOPSYS=y -# CONFIG_SYNOPSYS_DWC_ETH_QOS is not set -CONFIG_NET_VENDOR_TEHUTI=y -# CONFIG_TEHUTI is not set -CONFIG_NET_VENDOR_TI=y -# CONFIG_TI_CPSW_ALE is not set -# CONFIG_TLAN is not set -CONFIG_NET_VENDOR_VIA=y -# CONFIG_VIA_RHINE is not set -# CONFIG_VIA_VELOCITY is not set -CONFIG_NET_VENDOR_WIZNET=y -# CONFIG_WIZNET_W5100 is not set -# CONFIG_WIZNET_W5300 is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -CONFIG_PHYLIB=y -CONFIG_SWPHY=y - -# -# MDIO bus device drivers -# -# CONFIG_MDIO_BCM_UNIMAC is not set -# CONFIG_MDIO_BITBANG is not set -# CONFIG_MDIO_BUS_MUX_GPIO is not set -# CONFIG_MDIO_BUS_MUX_MMIOREG is not set -# CONFIG_MDIO_HISI_FEMAC is not set -# CONFIG_MDIO_OCTEON is not set -# CONFIG_MDIO_THUNDER is not set - -# -# MII PHY device drivers -# -# CONFIG_AMD_PHY is not set -# CONFIG_AQUANTIA_PHY is not set -# CONFIG_AT803X_PHY is not set -# CONFIG_BCM7XXX_PHY is not set -# CONFIG_BCM87XX_PHY is not set -# CONFIG_BROADCOM_PHY is not set -# CONFIG_CICADA_PHY is not set -# CONFIG_DAVICOM_PHY is not set -# CONFIG_DP83848_PHY is not set -# CONFIG_DP83867_PHY is not set -CONFIG_FIXED_PHY=y -# CONFIG_ICPLUS_PHY is not set -# CONFIG_INTEL_XWAY_PHY is not set -# CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_LXT_PHY is not set -# CONFIG_MARVELL_PHY is not set -# CONFIG_MICREL_PHY is not set -# CONFIG_MICROCHIP_PHY is not set -# CONFIG_MICROSEMI_PHY is not set -# CONFIG_NATIONAL_PHY is not set -# CONFIG_QSEMI_PHY is not set -# CONFIG_REALTEK_PHY is not set -# CONFIG_SMSC_PHY is not set -# CONFIG_STE10XP is not set -# CONFIG_TERANETICS_PHY is not set -# CONFIG_VITESSE_PHY is not set -# CONFIG_XILINX_GMII2RGMII is not set -# CONFIG_MICREL_KS8995MA is not set CONFIG_PPP=y CONFIG_PPP_BSDCOMP=y CONFIG_PPP_DEFLATE=y @@ -1795,2460 +283,202 @@ CONFIG_PPP_FILTER=y CONFIG_PPP_MPPE=y CONFIG_PPP_MULTILINK=y CONFIG_PPPOE=y +CONFIG_PPTP=y CONFIG_PPPOL2TP=y CONFIG_PPPOLAC=y CONFIG_PPPOPNS=y CONFIG_PPP_ASYNC=y CONFIG_PPP_SYNC_TTY=y -# CONFIG_SLIP is not set -CONFIG_SLHC=y -CONFIG_USB_NET_DRIVERS=y -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_RTL8150 is not set -# CONFIG_USB_RTL8152 is not set -# CONFIG_USB_LAN78XX is not set CONFIG_USB_USBNET=y -CONFIG_USB_NET_AX8817X=y -CONFIG_USB_NET_AX88179_178A=y -CONFIG_USB_NET_CDCETHER=y -# CONFIG_USB_NET_CDC_EEM is not set -CONFIG_USB_NET_CDC_NCM=y -# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set -# CONFIG_USB_NET_CDC_MBIM is not set -# CONFIG_USB_NET_DM9601 is not set -# CONFIG_USB_NET_SR9700 is not set -# CONFIG_USB_NET_SR9800 is not set -# CONFIG_USB_NET_SMSC75XX is not set -# CONFIG_USB_NET_SMSC95XX is not set -# CONFIG_USB_NET_GL620A is not set -CONFIG_USB_NET_NET1080=y -# CONFIG_USB_NET_PLUSB is not set -# CONFIG_USB_NET_MCS7830 is not set -# CONFIG_USB_NET_RNDIS_HOST is not set -CONFIG_USB_NET_CDC_SUBSET_ENABLE=y -CONFIG_USB_NET_CDC_SUBSET=y -# CONFIG_USB_ALI_M5632 is not set -# CONFIG_USB_AN2720 is not set -CONFIG_USB_BELKIN=y -CONFIG_USB_ARMLINUX=y -# CONFIG_USB_EPSON2888 is not set -# CONFIG_USB_KC2190 is not set -CONFIG_USB_NET_ZAURUS=y -# CONFIG_USB_NET_CX82310_ETH is not set -# CONFIG_USB_NET_KALMIA is not set -# CONFIG_USB_NET_QMI_WWAN is not set -# CONFIG_USB_HSO is not set -# CONFIG_USB_NET_INT51X1 is not set -# CONFIG_USB_IPHETH is not set -# CONFIG_USB_SIERRA_NET is not set -# CONFIG_USB_VL600 is not set -# CONFIG_USB_NET_CH9200 is not set -CONFIG_WLAN=y -CONFIG_WLAN_VENDOR_ADMTEK=y -CONFIG_WLAN_VENDOR_ATH=y -# CONFIG_ATH_DEBUG is not set -# CONFIG_ATH_REG_DYNAMIC_USER_REG_HINTS is not set -# CONFIG_ATH5K_PCI is not set -# CONFIG_ATH6KL is not set -# CONFIG_WIL6210 is not set -CONFIG_WLAN_VENDOR_ATMEL=y -# CONFIG_ATMEL is not set -CONFIG_WLAN_VENDOR_BROADCOM=y -# CONFIG_BRCMFMAC is not set -CONFIG_WLAN_VENDOR_CISCO=y -CONFIG_WLAN_VENDOR_INTEL=y -# CONFIG_IPW2100 is not set -# CONFIG_IPW2200 is not set -CONFIG_WLAN_VENDOR_INTERSIL=y -# CONFIG_HOSTAP is not set -# CONFIG_HERMES is not set -# CONFIG_PRISM54 is not set -CONFIG_WLAN_VENDOR_MARVELL=y -# CONFIG_LIBERTAS is not set -# CONFIG_MWIFIEX is not set -CONFIG_WLAN_VENDOR_MEDIATEK=y -CONFIG_WLAN_VENDOR_RALINK=y -CONFIG_WLAN_VENDOR_REALTEK=y -CONFIG_WLAN_VENDOR_RSI=y -CONFIG_WLAN_VENDOR_ST=y -CONFIG_WLAN_VENDOR_TI=y -CONFIG_WLAN_VENDOR_ZYDAS=y -# CONFIG_USB_ZD1201 is not set -# CONFIG_USB_NET_RNDIS_WLAN is not set CONFIG_WCNSS_MEM_PRE_ALLOC=y -# CONFIG_CNSS2 is not set -# CONFIG_CNSS_QCA6290 is not set -# CONFIG_CNSS_QCA6390 is not set -# CONFIG_CNSS_EMULATION is not set -# CONFIG_CNSS is not set -# CONFIG_CLD_DEBUG is not set -# CONFIG_CLD_USB_CORE is not set -# CONFIG_CLD_HL_SDIO_CORE is not set CONFIG_CLD_LL_CORE=y -# CONFIG_CNSS_LOGGER is not set -# CONFIG_WLAN_FEATURE_RX_WAKELOCK is not set -CONFIG_CNSS_UTILS=y CONFIG_CNSS_GENL=y -# CONFIG_QCA402X is not set - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# -# CONFIG_WAN is not set -# CONFIG_VMXNET3 is not set -# CONFIG_ISDN is not set -# CONFIG_NVM is not set - -# -# Input device support -# -CONFIG_INPUT=y -CONFIG_INPUT_LEDS=y -CONFIG_INPUT_FF_MEMLESS=y -# CONFIG_INPUT_POLLDEV is not set -# CONFIG_INPUT_SPARSEKMAP is not set -# CONFIG_INPUT_MATRIXKMAP is not set - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_EVBUG is not set -# CONFIG_INPUT_KEYRESET is not set -# CONFIG_INPUT_KEYCOMBO is not set - -# -# Input Device Drivers -# -CONFIG_INPUT_KEYBOARD=y -# CONFIG_KEYBOARD_ADC is not set -# CONFIG_KEYBOARD_ADP5588 is not set -# CONFIG_KEYBOARD_ADP5589 is not set -CONFIG_KEYBOARD_ATKBD=y -# CONFIG_KEYBOARD_QT1070 is not set -# CONFIG_KEYBOARD_QT2160 is not set -# CONFIG_KEYBOARD_LKKBD is not set CONFIG_KEYBOARD_GPIO=y -# CONFIG_KEYBOARD_GPIO_POLLED is not set -# CONFIG_KEYBOARD_TCA6416 is not set -# CONFIG_KEYBOARD_TCA8418 is not set -# CONFIG_KEYBOARD_MATRIX is not set -# CONFIG_KEYBOARD_LM8323 is not set -# CONFIG_KEYBOARD_LM8333 is not set -# CONFIG_KEYBOARD_MAX7359 is not set -# CONFIG_KEYBOARD_MCS is not set -# CONFIG_KEYBOARD_MPR121 is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_OPENCORES is not set -# CONFIG_KEYBOARD_SAMSUNG is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_OMAP4 is not set -# CONFIG_KEYBOARD_XTKBD is not set -# CONFIG_KEYBOARD_CAP11XX is not set -# CONFIG_KEYBOARD_BCM is not set # CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_JOYSTICK=y -# CONFIG_JOYSTICK_ANALOG is not set -# CONFIG_JOYSTICK_A3D is not set -# CONFIG_JOYSTICK_ADI is not set -# CONFIG_JOYSTICK_COBRA is not set -# CONFIG_JOYSTICK_GF2K is not set -# CONFIG_JOYSTICK_GRIP is not set -# CONFIG_JOYSTICK_GRIP_MP is not set -# CONFIG_JOYSTICK_GUILLEMOT is not set -# CONFIG_JOYSTICK_INTERACT is not set -# CONFIG_JOYSTICK_SIDEWINDER is not set -# CONFIG_JOYSTICK_TMDC is not set -# CONFIG_JOYSTICK_IFORCE is not set -# CONFIG_JOYSTICK_WARRIOR is not set -# CONFIG_JOYSTICK_MAGELLAN is not set -# CONFIG_JOYSTICK_SPACEORB is not set -# CONFIG_JOYSTICK_SPACEBALL is not set -# CONFIG_JOYSTICK_STINGER is not set -# CONFIG_JOYSTICK_TWIDJOY is not set -# CONFIG_JOYSTICK_ZHENHUA is not set -# CONFIG_JOYSTICK_AS5011 is not set -# CONFIG_JOYSTICK_JOYDUMP is not set -CONFIG_JOYSTICK_XPAD=y -CONFIG_JOYSTICK_XPAD_FF=y -CONFIG_JOYSTICK_XPAD_LEDS=y -# CONFIG_INPUT_TABLET is not set CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_CONFIG_TOUCHSCREEN_ST_FTS=y -# CONFIG_TOUCHSCREEN_ST_CORE is not set -# CONFIG_TOUCHSCREEN_ST_FTS_V521 is not set -CONFIG_TOUCHSCREEN_NT36XXX=y -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_v26=y -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_I2C_v26=y -# CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_SPI_v26 is not set -# CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI_HID_I2C_v26 is not set -# CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE_v26 is not set -# CONFIG_SECURE_TOUCH_SYNAPTICS_DSX_V26 is not set -CONFIG_TOUCHSCREEN_PROPERTIES=y -# CONFIG_TOUCHSCREEN_ADS7846 is not set -# CONFIG_TOUCHSCREEN_AD7877 is not set -# CONFIG_TOUCHSCREEN_AD7879 is not set -# CONFIG_TOUCHSCREEN_AR1021_I2C is not set -# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set -# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set -# CONFIG_TOUCHSCREEN_BU21013 is not set -# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set -# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set -# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set -# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set -# CONFIG_TOUCHSCREEN_DYNAPRO is not set -# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set -# CONFIG_TOUCHSCREEN_EETI is not set -# CONFIG_TOUCHSCREEN_EGALAX is not set -# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set -# CONFIG_TOUCHSCREEN_FUJITSU is not set -# CONFIG_TOUCHSCREEN_GOODIX is not set -# CONFIG_TOUCHSCREEN_ILI210X is not set -# CONFIG_TOUCHSCREEN_GUNZE is not set -# CONFIG_TOUCHSCREEN_EKTF2127 is not set -# CONFIG_TOUCHSCREEN_ELAN is not set -# CONFIG_TOUCHSCREEN_ELO is not set -# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set -# CONFIG_TOUCHSCREEN_WACOM_I2C is not set -# CONFIG_TOUCHSCREEN_MAX11801 is not set -# CONFIG_TOUCHSCREEN_MCS5000 is not set -# CONFIG_TOUCHSCREEN_MMS114 is not set -# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set -# CONFIG_TOUCHSCREEN_MTOUCH is not set -# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set -# CONFIG_TOUCHSCREEN_INEXIO is not set -# CONFIG_TOUCHSCREEN_MK712 is not set -# CONFIG_TOUCHSCREEN_PENMOUNT is not set -# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set -# CONFIG_TOUCHSCREEN_ST_FTS is not set -# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set -# CONFIG_TOUCHSCREEN_TOUCHWIN is not set -# CONFIG_TOUCHSCREEN_PIXCIR is not set -# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set -# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set -# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set -# CONFIG_TOUCHSCREEN_TSC_SERIO is not set -# CONFIG_TOUCHSCREEN_TSC2004 is not set -# CONFIG_TOUCHSCREEN_TSC2005 is not set -# CONFIG_TOUCHSCREEN_TSC2007 is not set -# CONFIG_TOUCHSCREEN_RM_TS is not set -# CONFIG_TOUCHSCREEN_SILEAD is not set -# CONFIG_TOUCHSCREEN_SIS_I2C is not set -# CONFIG_TOUCHSCREEN_ST1232 is not set -# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set -# CONFIG_TOUCHSCREEN_SX8654 is not set -# CONFIG_TOUCHSCREEN_TPS6507X is not set -# CONFIG_TOUCHSCREEN_ZFORCE is not set -# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX=y -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_I2C=y -# CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_SPI is not set -# CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI_HID_I2C is not set -# CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE is not set -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_FORCE=y -CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_I2C_FORCE=y -# CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_SPI_FORCE is not set -# CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_RMI_HID_I2C_FORCE is not set -# CONFIG_TOUCHSCREEN_SYNAPTICS_DSX_CORE_FORCE is not set -# CONFIG_TOUCH_DEBUG_FS is not set CONFIG_TOUCHSCREEN_FTS=y -CONFIG_TOUCHSCREEN_FTS_DIRECTORY="focaltech_touch" -# CONFIG_TOUCHSCREEN_FT5X46 is not set -# CONFIG_TOUCHSCREEN_FT5X46_I2C is not set -# CONFIG_TOUCHSCREEN_FT5X46_SPI is not set -# CONFIG_TOUCHSCREEN_FT5X06 is not set -# CONFIG_TOUCHSCREEN_GEN_VKEYS is not set -# CONFIG_TOUCHSCREEN_GT9XX_v28 is not set -# CONFIG_TOUCHSCREEN_HIMAX_CHIPSET is not set -# CONFIG_TOUCHSCREEN_EKTF3XXX_CHIPSET is not set -# CONFIG_INPUT_PRESS_NDT is not set CONFIG_INPUT_MISC=y -# CONFIG_INPUT_AD714X is not set -# CONFIG_INPUT_ATMEL_CAPTOUCH is not set -# CONFIG_INPUT_BMA150 is not set -# CONFIG_INPUT_E3X0_BUTTON is not set -# CONFIG_INPUT_HBTP_INPUT is not set -# CONFIG_INPUT_PM8941_PWRKEY is not set CONFIG_INPUT_QPNP_POWER_ON=y -# CONFIG_INPUT_QTI_HAPTICS is not set -# CONFIG_INPUT_MMA8450 is not set -# CONFIG_INPUT_MPU3050 is not set -# CONFIG_INPUT_GP2A is not set -# CONFIG_INPUT_GPIO_BEEPER is not set -# CONFIG_INPUT_GPIO_TILT_POLLED is not set -# CONFIG_INPUT_GPIO_DECODER is not set -# CONFIG_INPUT_ATI_REMOTE2 is not set -# CONFIG_INPUT_KEYCHORD is not set -# CONFIG_STMVL53L0X is not set -# CONFIG_INPUT_KEYSPAN_REMOTE is not set -# CONFIG_INPUT_KXTJ9 is not set -# CONFIG_INPUT_POWERMATE is not set -# CONFIG_INPUT_YEALINK is not set -# CONFIG_INPUT_CM109 is not set -# CONFIG_INPUT_REGULATOR_HAPTIC is not set CONFIG_INPUT_UINPUT=y -# CONFIG_INPUT_GPIO is not set -# CONFIG_INPUT_PCF8574 is not set -# CONFIG_INPUT_PWM_BEEPER is not set -# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set -# CONFIG_INPUT_ADXL34X is not set -# CONFIG_INPUT_IMS_PCU is not set -# CONFIG_INPUT_CMA3000 is not set -# CONFIG_INPUT_SOC_BUTTON_ARRAY is not set -# CONFIG_INPUT_DRV260X_HAPTICS is not set -# CONFIG_INPUT_DRV2665_HAPTICS is not set -# CONFIG_INPUT_DRV2667_HAPTICS is not set -# CONFIG_RMI4_CORE is not set -# CONFIG_FINGERPRINT_FP_VREG_CONTROL is not set CONFIG_INPUT_FINGERPRINT=y CONFIG_FINGERPRINT_FPC_TEE=y -# CONFIG_FINGERPRINT_FPC_SCREEN_NOTIFY is not set CONFIG_FINGERPRINT_GOODIX_TA=y -# CONFIG_FINGERPRINT_SYNAPTICS4302 is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y # CONFIG_SERIO_SERPORT is not set -# CONFIG_SERIO_AMBAKMI is not set -# CONFIG_SERIO_PCIPS2 is not set -CONFIG_SERIO_LIBPS2=y -# CONFIG_SERIO_RAW is not set -# CONFIG_SERIO_ALTERA_PS2 is not set -# CONFIG_SERIO_PS2MULT is not set -# CONFIG_SERIO_ARC_PS2 is not set -# CONFIG_SERIO_APBPS2 is not set -# CONFIG_USERIO is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_TTY=y # CONFIG_VT is not set -CONFIG_UNIX98_PTYS=y # CONFIG_LEGACY_PTYS is not set -# CONFIG_SERIAL_NONSTANDARD is not set -# CONFIG_NOZOMI is not set -# CONFIG_N_GSM is not set -# CONFIG_TRACE_SINK is not set -CONFIG_LDISC_AUTOLOAD=y # CONFIG_DEVMEM is not set # CONFIG_DEVKMEM is not set - -# -# Serial drivers -# -# CONFIG_SERIAL_8250 is not set - -# -# Non-8250 serial port support -# -# CONFIG_SERIAL_AMBA_PL010 is not set -# CONFIG_SERIAL_AMBA_PL011 is not set -# CONFIG_SERIAL_EARLYCON_ARM_SEMIHOST is not set -# CONFIG_SERIAL_MAX3100 is not set -# CONFIG_SERIAL_MAX310X is not set -# CONFIG_SERIAL_UARTLITE is not set -CONFIG_SERIAL_CORE=y -# CONFIG_SERIAL_JSM is not set -# CONFIG_SERIAL_MSM is not set CONFIG_SERIAL_MSM_GENI=y -# CONFIG_SERIAL_MSM_GENI_CONSOLE is not set -# CONFIG_SERIAL_MSM_HS is not set -# CONFIG_SERIAL_SCCNXP is not set -# CONFIG_SERIAL_SC16IS7XX is not set -# CONFIG_SERIAL_ALTERA_JTAGUART is not set -# CONFIG_SERIAL_ALTERA_UART is not set -# CONFIG_SERIAL_IFX6X60 is not set -# CONFIG_SERIAL_XILINX_PS_UART is not set -# CONFIG_SERIAL_ARC is not set -# CONFIG_SERIAL_RP2 is not set -# CONFIG_SERIAL_FSL_LPUART is not set -# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set - -# -# Diag Support -# CONFIG_DIAG_CHAR=y -CONFIG_DIAG_OVER_USB=y -# CONFIG_TTY_PRINTK is not set -# CONFIG_HVC_DCC is not set -# CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=y -# CONFIG_HW_RANDOM_TIMERIOMEM is not set -# CONFIG_HW_RANDOM_MSM is not set CONFIG_HW_RANDOM_MSM_LEGACY=y -CONFIG_HW_RANDOM_CAVIUM=y -# CONFIG_APPLICOM is not set - -# -# PCMCIA character devices -# -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set # CONFIG_DEVPORT is not set -# CONFIG_XILLYBUS is not set CONFIG_MSM_ADSPRPC=y -# CONFIG_MSM_RDBG is not set - -# -# I2C support -# -CONFIG_I2C=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y CONFIG_I2C_CHARDEV=y -CONFIG_I2C_MUX=y - -# -# Multiplexer I2C Chip support -# -# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set -# CONFIG_I2C_MUX_GPIO is not set -# CONFIG_I2C_MUX_PCA9541 is not set -# CONFIG_I2C_MUX_PCA954x is not set -# CONFIG_I2C_MUX_PINCTRL is not set -# CONFIG_I2C_MUX_REG is not set -# CONFIG_I2C_DEMUX_PINCTRL is not set -CONFIG_I2C_HELPER_AUTO=y -CONFIG_I2C_ALGOBIT=y - -# -# I2C Hardware Bus support -# - -# -# PC SMBus host controller drivers -# -# CONFIG_I2C_ALI1535 is not set -# CONFIG_I2C_ALI1563 is not set -# CONFIG_I2C_ALI15X3 is not set -# CONFIG_I2C_AMD756 is not set -# CONFIG_I2C_AMD8111 is not set -# CONFIG_I2C_I801 is not set -# CONFIG_I2C_ISCH is not set -# CONFIG_I2C_PIIX4 is not set -# CONFIG_I2C_NFORCE2 is not set -# CONFIG_I2C_SIS5595 is not set -# CONFIG_I2C_SIS630 is not set -# CONFIG_I2C_SIS96X is not set -# CONFIG_I2C_VIA is not set -# CONFIG_I2C_VIAPRO is not set - -# -# I2C system bus drivers (mostly embedded / system-on-chip) -# -# CONFIG_I2C_CADENCE is not set -# CONFIG_I2C_CBUS_GPIO is not set -# CONFIG_I2C_DESIGNWARE_PLATFORM is not set -# CONFIG_I2C_DESIGNWARE_PCI is not set -# CONFIG_I2C_EMEV2 is not set -# CONFIG_I2C_GPIO is not set -# CONFIG_I2C_NOMADIK is not set -# CONFIG_I2C_OCORES is not set -# CONFIG_I2C_PCA_PLATFORM is not set -# CONFIG_I2C_PXA_PCI is not set -# CONFIG_I2C_QUP is not set CONFIG_I2C_QCOM_GENI=y -# CONFIG_I2C_RK3X is not set -# CONFIG_I2C_SIMTEC is not set -# CONFIG_I2C_THUNDERX is not set -# CONFIG_I2C_XILINX is not set - -# -# External I2C/SMBus adapter drivers -# -# CONFIG_I2C_DIOLAN_U2C is not set -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_ROBOTFUZZ_OSIF is not set -# CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_TINY_USB is not set - -# -# Other I2C/SMBus bus drivers -# -# CONFIG_I2C_MSM_V2 is not set -# CONFIG_I2C_SLAVE is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set CONFIG_SPI=y -# CONFIG_SPI_DEBUG is not set -CONFIG_SPI_MASTER=y - -# -# SPI Master Controller Drivers -# -# CONFIG_SPI_ALTERA is not set -# CONFIG_SPI_AXI_SPI_ENGINE is not set -# CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_CADENCE is not set -# CONFIG_SPI_DESIGNWARE is not set -# CONFIG_SPI_GPIO is not set -# CONFIG_SPI_FSL_SPI is not set -# CONFIG_SPI_OC_TINY is not set -# CONFIG_SPI_PL022 is not set -# CONFIG_SPI_PXA2XX is not set -# CONFIG_SPI_PXA2XX_PCI is not set -# CONFIG_SPI_ROCKCHIP is not set CONFIG_SPI_QUP=y CONFIG_SPI_QCOM_GENI=y -# CONFIG_SPI_SC18IS602 is not set -# CONFIG_SPI_THUNDERX is not set -# CONFIG_SPI_XCOMM is not set -# CONFIG_SPI_XILINX is not set -# CONFIG_SPI_ZYNQMP_GQSPI is not set - -# -# SPI Protocol Masters -# CONFIG_SPI_SPIDEV=y -# CONFIG_SPI_TLE62X0 is not set -CONFIG_SLIMBUS=y -# CONFIG_SLIMBUS_MSM_CTRL is not set CONFIG_SLIMBUS_MSM_NGD=y CONFIG_SPMI=y -CONFIG_SPMI_MSM_PMIC_ARB=y -# CONFIG_SPMI_MSM_PMIC_ARB_DEBUG is not set -# CONFIG_HSI is not set - -# -# PPS support -# -# CONFIG_PPS is not set - -# -# PPS generators support -# - -# -# PTP clock support -# -# CONFIG_PTP_1588_CLOCK is not set - -# -# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. -# -CONFIG_PINCTRL=y - -# -# Pin controllers -# -CONFIG_PINMUX=y -CONFIG_PINCONF=y -CONFIG_GENERIC_PINCONF=y -# CONFIG_DEBUG_PINCTRL is not set -# CONFIG_PINCTRL_AMD is not set -# CONFIG_PINCTRL_SINGLE is not set -CONFIG_PINCTRL_MSM=y -# CONFIG_PINCTRL_APQ8064 is not set -# CONFIG_PINCTRL_APQ8084 is not set -# CONFIG_PINCTRL_IPQ4019 is not set -# CONFIG_PINCTRL_IPQ8064 is not set -# CONFIG_PINCTRL_MSM8660 is not set -# CONFIG_PINCTRL_MSM8960 is not set -# CONFIG_PINCTRL_MDM9615 is not set -# CONFIG_PINCTRL_MDM9650 is not set -# CONFIG_PINCTRL_MDM9607 is not set -# CONFIG_PINCTRL_MSM8X74 is not set -# CONFIG_PINCTRL_MSM8916 is not set -# CONFIG_PINCTRL_MSM8953 is not set -# CONFIG_PINCTRL_MSM8937 is not set -# CONFIG_PINCTRL_MSM8917 is not set -# CONFIG_PINCTRL_MSM8940 is not set CONFIG_PINCTRL_SDM845=y -# CONFIG_PINCTRL_SDM670 is not set -# CONFIG_PINCTRL_SDXPOORWILLS is not set -# CONFIG_PINCTRL_MSM8996 is not set CONFIG_PINCTRL_QCOM_SPMI_PMIC=y -# CONFIG_PINCTRL_QCOM_SSBI_PMIC is not set CONFIG_GPIOLIB=y -CONFIG_OF_GPIO=y -CONFIG_GPIOLIB_IRQCHIP=y -# CONFIG_DEBUG_GPIO is not set CONFIG_GPIO_SYSFS=y - -# -# Memory mapped GPIO drivers -# -# CONFIG_GPIO_74XX_MMIO is not set -# CONFIG_GPIO_ALTERA is not set -# CONFIG_GPIO_DWAPB is not set -# CONFIG_GPIO_GENERIC_PLATFORM is not set -# CONFIG_GPIO_GRGPIO is not set -# CONFIG_GPIO_MOCKUP is not set -# CONFIG_GPIO_PL061 is not set -# CONFIG_GPIO_QPNP_PIN is not set -# CONFIG_GPIO_SYSCON is not set -# CONFIG_GPIO_VX855 is not set -# CONFIG_GPIO_XGENE is not set -# CONFIG_GPIO_XILINX is not set -# CONFIG_GPIO_ZX is not set - -# -# I2C GPIO expanders -# -# CONFIG_GPIO_ADP5588 is not set -# CONFIG_GPIO_ADNP is not set -# CONFIG_GPIO_MAX7300 is not set -# CONFIG_GPIO_MAX732X is not set -# CONFIG_GPIO_PCA953X is not set -# CONFIG_GPIO_PCF857X is not set -# CONFIG_GPIO_SX150X is not set -# CONFIG_GPIO_TPIC2810 is not set -# CONFIG_GPIO_TS4900 is not set - -# -# MFD GPIO expanders -# - -# -# PCI GPIO expanders -# -# CONFIG_GPIO_AMD8111 is not set -# CONFIG_GPIO_BT8XX is not set -# CONFIG_GPIO_ML_IOH is not set -# CONFIG_GPIO_RDC321X is not set - -# -# SPI GPIO expanders -# -# CONFIG_GPIO_74X164 is not set -# CONFIG_GPIO_MAX7301 is not set -# CONFIG_GPIO_MC33880 is not set -# CONFIG_GPIO_PISOSR is not set - -# -# SPI or I2C GPIO expanders -# -# CONFIG_GPIO_MCP23S08 is not set - -# -# USB GPIO expanders -# -# CONFIG_W1 is not set -# CONFIG_POWER_AVS is not set -CONFIG_POWER_RESET=y -# CONFIG_POWER_RESET_GPIO is not set -# CONFIG_POWER_RESET_GPIO_RESTART is not set -# CONFIG_POWER_RESET_LTC2952 is not set CONFIG_POWER_RESET_QCOM=y CONFIG_QCOM_DLOAD_MODE=y -CONFIG_QCOM_PRESERVE_MEM=y -# CONFIG_POWER_RESET_RESTART is not set CONFIG_POWER_RESET_XGENE=y CONFIG_POWER_RESET_SYSCON=y -# CONFIG_POWER_RESET_SYSCON_POWEROFF is not set -# CONFIG_SYSCON_REBOOT_MODE is not set -CONFIG_POWER_SUPPLY=y -# CONFIG_POWER_SUPPLY_DEBUG is not set -# CONFIG_PDA_POWER is not set -# CONFIG_GENERIC_ADC_BATTERY is not set -# CONFIG_TEST_POWER is not set -# CONFIG_BATTERY_DS2780 is not set -# CONFIG_BATTERY_DS2781 is not set -# CONFIG_BATTERY_DS2782 is not set -# CONFIG_BATTERY_SBS is not set -# CONFIG_BATTERY_BQ27XXX is not set -# CONFIG_BATTERY_MAX17040 is not set -# CONFIG_BATTERY_MAX17042 is not set -# CONFIG_CHARGER_ISP1704 is not set -# CONFIG_CHARGER_MAX8903 is not set -# CONFIG_CHARGER_LP8727 is not set -# CONFIG_CHARGER_GPIO is not set -# CONFIG_CHARGER_MANAGER is not set -# CONFIG_CHARGER_QCOM_SMBB is not set -# CONFIG_CHARGER_BQ2415X is not set -# CONFIG_CHARGER_BQ24190 is not set -# CONFIG_CHARGER_BQ24257 is not set -# CONFIG_CHARGER_BQ24735 is not set -# CONFIG_CHARGER_BQ25890 is not set -# CONFIG_CHARGER_SMB347 is not set -# CONFIG_BATTERY_GAUGE_LTC2941 is not set -# CONFIG_CHARGER_RT9455 is not set -# CONFIG_NX30P6093 is not set - -# -# Qualcomm Technologies Inc Charger and Fuel Gauge support -# -# CONFIG_QPNP_FG is not set CONFIG_QPNP_FG_GEN3=y -# CONFIG_SMB135X_CHARGER is not set -# CONFIG_SMB1360_CHARGER_FG is not set CONFIG_SMB1355_SLAVE_CHARGER=y -CONFIG_IDT_P9220=y -# CONFIG_SMB1351_USB_CHARGER is not set CONFIG_QPNP_SMB2=y -# CONFIG_QPNP_SMB5 is not set -# CONFIG_SMB138X_CHARGER is not set -# CONFIG_QPNP_SMBCHARGER is not set CONFIG_QPNP_QNOVO=y -# CONFIG_QPNP_VM_BMS is not set -# CONFIG_QPNP_LINEAR_CHARGER is not set -# CONFIG_QPNP_TYPEC is not set -# CONFIG_QPNP_QG is not set -CONFIG_SMB1390_CHARGE_PUMP=y - -# -# Miscellaneous Qualcomm Technologies, Inc. power support -# -# CONFIG_MSM_APM is not set -CONFIG_HWMON=y -# CONFIG_HWMON_VID is not set -# CONFIG_HWMON_DEBUG_CHIP is not set - -# -# Native drivers -# -# CONFIG_SENSORS_AD7314 is not set -# CONFIG_SENSORS_AD7414 is not set -# CONFIG_SENSORS_AD7418 is not set -# CONFIG_SENSORS_ADM1021 is not set -# CONFIG_SENSORS_ADM1025 is not set -# CONFIG_SENSORS_ADM1026 is not set -# CONFIG_SENSORS_ADM1029 is not set -# CONFIG_SENSORS_ADM1031 is not set -# CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_ADT7310 is not set -# CONFIG_SENSORS_ADT7410 is not set -# CONFIG_SENSORS_ADT7411 is not set -# CONFIG_SENSORS_ADT7462 is not set -# CONFIG_SENSORS_ADT7470 is not set -# CONFIG_SENSORS_ADT7475 is not set -# CONFIG_SENSORS_ASC7621 is not set -# CONFIG_SENSORS_ATXP1 is not set -# CONFIG_SENSORS_DS620 is not set -# CONFIG_SENSORS_DS1621 is not set -# CONFIG_SENSORS_I5K_AMB is not set -# CONFIG_SENSORS_F71805F is not set -# CONFIG_SENSORS_F71882FG is not set -# CONFIG_SENSORS_F75375S is not set -# CONFIG_SENSORS_GL518SM is not set -# CONFIG_SENSORS_GL520SM is not set -# CONFIG_SENSORS_G760A is not set -# CONFIG_SENSORS_G762 is not set -# CONFIG_SENSORS_GPIO_FAN is not set -# CONFIG_SENSORS_HIH6130 is not set -# CONFIG_SENSORS_IIO_HWMON is not set -# CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_JC42 is not set -# CONFIG_SENSORS_POWR1220 is not set -# CONFIG_SENSORS_LINEAGE is not set -# CONFIG_SENSORS_LTC2945 is not set -# CONFIG_SENSORS_LTC2990 is not set -# CONFIG_SENSORS_LTC4151 is not set -# CONFIG_SENSORS_LTC4215 is not set -# CONFIG_SENSORS_LTC4222 is not set -# CONFIG_SENSORS_LTC4245 is not set -# CONFIG_SENSORS_LTC4260 is not set -# CONFIG_SENSORS_LTC4261 is not set -# CONFIG_SENSORS_MAX1111 is not set -# CONFIG_SENSORS_MAX16065 is not set -# CONFIG_SENSORS_MAX1619 is not set -# CONFIG_SENSORS_MAX1668 is not set -# CONFIG_SENSORS_MAX197 is not set -# CONFIG_SENSORS_MAX31722 is not set -# CONFIG_SENSORS_MAX6639 is not set -# CONFIG_SENSORS_MAX6642 is not set -# CONFIG_SENSORS_MAX6650 is not set -# CONFIG_SENSORS_MAX6697 is not set -# CONFIG_SENSORS_MAX31790 is not set -# CONFIG_SENSORS_MCP3021 is not set -# CONFIG_SENSORS_ADCXX is not set -# CONFIG_SENSORS_LM63 is not set -# CONFIG_SENSORS_LM70 is not set -# CONFIG_SENSORS_LM73 is not set -# CONFIG_SENSORS_LM75 is not set -# CONFIG_SENSORS_LM77 is not set -# CONFIG_SENSORS_LM78 is not set -# CONFIG_SENSORS_LM80 is not set -# CONFIG_SENSORS_LM83 is not set -# CONFIG_SENSORS_LM85 is not set -# CONFIG_SENSORS_LM87 is not set -# CONFIG_SENSORS_LM90 is not set -# CONFIG_SENSORS_LM92 is not set -# CONFIG_SENSORS_LM93 is not set -# CONFIG_SENSORS_LM95234 is not set -# CONFIG_SENSORS_LM95241 is not set -# CONFIG_SENSORS_LM95245 is not set -# CONFIG_SENSORS_PC87360 is not set -# CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_NTC_THERMISTOR is not set -# CONFIG_SENSORS_NCT6683 is not set -# CONFIG_SENSORS_NCT6775 is not set -# CONFIG_SENSORS_NCT7802 is not set -# CONFIG_SENSORS_NCT7904 is not set -# CONFIG_SENSORS_PCF8591 is not set CONFIG_SENSORS_QPNP_ADC_VOLTAGE=y -# CONFIG_SENSORS_QPNP_ADC_CURRENT is not set -# CONFIG_PMBUS is not set -# CONFIG_SENSORS_PWM_FAN is not set -# CONFIG_SENSORS_SHT15 is not set -# CONFIG_SENSORS_SHT21 is not set -# CONFIG_SENSORS_SHT3x is not set -# CONFIG_SENSORS_SHTC1 is not set -# CONFIG_SENSORS_SIS5595 is not set -# CONFIG_SENSORS_DME1737 is not set -# CONFIG_SENSORS_EMC1403 is not set -# CONFIG_SENSORS_EMC2103 is not set -# CONFIG_SENSORS_EMC6W201 is not set -# CONFIG_SENSORS_SMSC47M1 is not set -# CONFIG_SENSORS_SMSC47M192 is not set -# CONFIG_SENSORS_SMSC47B397 is not set -# CONFIG_SENSORS_SCH56XX_COMMON is not set -# CONFIG_SENSORS_SMM665 is not set -# CONFIG_SENSORS_ADC128D818 is not set -# CONFIG_SENSORS_ADS1015 is not set -# CONFIG_SENSORS_ADS7828 is not set -# CONFIG_SENSORS_ADS7871 is not set -# CONFIG_SENSORS_AMC6821 is not set -# CONFIG_SENSORS_INA209 is not set -# CONFIG_SENSORS_INA2XX is not set -# CONFIG_SENSORS_INA3221 is not set -# CONFIG_SENSORS_TC74 is not set -# CONFIG_SENSORS_THMC50 is not set -# CONFIG_SENSORS_TMP102 is not set -# CONFIG_SENSORS_TMP103 is not set -# CONFIG_SENSORS_TMP401 is not set -# CONFIG_SENSORS_TMP421 is not set -# CONFIG_SENSORS_VIA686A is not set -# CONFIG_SENSORS_VT1211 is not set -# CONFIG_SENSORS_VT8231 is not set -# CONFIG_SENSORS_W83781D is not set -# CONFIG_SENSORS_W83791D is not set -# CONFIG_SENSORS_W83792D is not set -# CONFIG_SENSORS_W83793 is not set -# CONFIG_SENSORS_W83795 is not set -# CONFIG_SENSORS_W83L785TS is not set -# CONFIG_SENSORS_W83L786NG is not set -# CONFIG_SENSORS_W83627HF is not set -# CONFIG_SENSORS_W83627EHF is not set CONFIG_THERMAL=y -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_OF=y CONFIG_THERMAL_WRITABLE_TRIPS=y -# CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE is not set -# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE=y -# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set -# CONFIG_THERMAL_GOV_FAIR_SHARE is not set CONFIG_THERMAL_GOV_STEP_WISE=y -# CONFIG_THERMAL_GOV_BANG_BANG is not set -CONFIG_THERMAL_GOV_USER_SPACE=y CONFIG_THERMAL_GOV_LOW_LIMITS=y -# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set CONFIG_CPU_THERMAL=y -# CONFIG_CLOCK_THERMAL is not set CONFIG_DEVFREQ_THERMAL=y -# CONFIG_THERMAL_EMULATION is not set -# CONFIG_QORIQ_THERMAL is not set - -# -# ACPI INT340X thermal drivers -# CONFIG_QCOM_SPMI_TEMP_ALARM=y CONFIG_THERMAL_QPNP=y -# CONFIG_GENERIC_ADC_THERMAL is not set CONFIG_THERMAL_QPNP_ADC_TM=y CONFIG_THERMAL_TSENS=y - -# -# Qualcomm thermal drivers -# CONFIG_MSM_BCL_PERIPHERAL_CTL=y CONFIG_QTI_THERMAL_LIMITS_DCVS=y CONFIG_QTI_VIRTUAL_SENSOR=y CONFIG_QTI_AOP_REG_COOLING_DEVICE=y CONFIG_QTI_QMI_COOLING_DEVICE=y CONFIG_REGULATOR_COOLING_DEVICE=y -# CONFIG_QTI_BCL_PMIC5 is not set -# CONFIG_QTI_BCL_SOC_DRIVER is not set -# CONFIG_WATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -# CONFIG_SSB is not set -CONFIG_BCMA_POSSIBLE=y - -# -# Broadcom specific AMBA -# -# CONFIG_BCMA is not set - -# -# Multifunction device drivers -# -CONFIG_MFD_CORE=y -# CONFIG_MFD_ACT8945A is not set -# CONFIG_MFD_AS3711 is not set -# CONFIG_MFD_AS3722 is not set -# CONFIG_PMIC_ADP5520 is not set -# CONFIG_MFD_AAT2870_CORE is not set -# CONFIG_MFD_ATMEL_FLEXCOM is not set -# CONFIG_MFD_ATMEL_HLCDC is not set -# CONFIG_MFD_BCM590XX is not set -# CONFIG_MFD_AXP20X_I2C is not set -# CONFIG_MFD_CROS_EC is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_MFD_DA9052_SPI is not set -# CONFIG_MFD_DA9052_I2C is not set -# CONFIG_MFD_DA9055 is not set -# CONFIG_MFD_DA9062 is not set -# CONFIG_MFD_DA9063 is not set -# CONFIG_MFD_DA9150 is not set -# CONFIG_MFD_DLN2 is not set -# CONFIG_MFD_EXYNOS_LPASS is not set -# CONFIG_MFD_MC13XXX_SPI is not set -# CONFIG_MFD_MC13XXX_I2C is not set -# CONFIG_MFD_HI6421_PMIC is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_HTC_I2CPLD is not set -# CONFIG_LPC_ICH is not set -# CONFIG_LPC_SCH is not set -# CONFIG_INTEL_SOC_PMIC is not set -# CONFIG_MFD_JANZ_CMODIO is not set -# CONFIG_MFD_KEMPLD is not set -# CONFIG_MFD_88PM800 is not set -# CONFIG_MFD_88PM805 is not set -# CONFIG_MFD_88PM860X is not set -# CONFIG_MFD_MAX14577 is not set -# CONFIG_MFD_MAX77620 is not set -# CONFIG_MFD_MAX77686 is not set -# CONFIG_MFD_MAX77693 is not set -# CONFIG_MFD_MAX77843 is not set -# CONFIG_MFD_MAX8907 is not set -# CONFIG_MFD_MAX8925 is not set -# CONFIG_MFD_MAX8997 is not set -# CONFIG_MFD_MAX8998 is not set -# CONFIG_MFD_MT6397 is not set -# CONFIG_MFD_MENF21BMC is not set -# CONFIG_EZX_PCAP is not set -# CONFIG_MFD_VIPERBOARD is not set -# CONFIG_MFD_RETU is not set -# CONFIG_MFD_PCF50633 is not set CONFIG_MFD_I2C_PMIC=y -# CONFIG_MFD_QCOM_RPM is not set CONFIG_MFD_SPMI_PMIC=y -# CONFIG_MFD_RDC321X is not set -# CONFIG_MFD_RTSX_PCI is not set -# CONFIG_MFD_RT5033 is not set -# CONFIG_MFD_RTSX_USB is not set -# CONFIG_MFD_RC5T583 is not set -# CONFIG_MFD_RK808 is not set -# CONFIG_MFD_RN5T618 is not set -# CONFIG_MFD_SEC_CORE is not set -# CONFIG_MFD_SI476X_CORE is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_MFD_SKY81452 is not set -# CONFIG_MFD_SMSC is not set -# CONFIG_ABX500_CORE is not set -# CONFIG_MFD_STMPE is not set -CONFIG_MFD_SYSCON=y -# CONFIG_MFD_TI_AM335X_TSCADC is not set -# CONFIG_MFD_LP3943 is not set -# CONFIG_MFD_LP8788 is not set -# CONFIG_MFD_PALMAS is not set -# CONFIG_TPS6105X is not set -# CONFIG_TPS65010 is not set -# CONFIG_TPS6507X is not set -# CONFIG_MFD_TPS65086 is not set -# CONFIG_MFD_TPS65090 is not set -# CONFIG_MFD_TPS65217 is not set -# CONFIG_MFD_TI_LP873X is not set -# CONFIG_MFD_TPS65218 is not set -# CONFIG_MFD_TPS6586X is not set -# CONFIG_MFD_TPS65910 is not set -# CONFIG_MFD_TPS65912_I2C is not set -# CONFIG_MFD_TPS65912_SPI is not set -# CONFIG_MFD_TPS80031 is not set -# CONFIG_TWL4030_CORE is not set -# CONFIG_TWL6040_CORE is not set -# CONFIG_MFD_WL1273_CORE is not set -# CONFIG_MFD_LM3533 is not set -# CONFIG_MFD_TC3589X is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_MFD_VX855 is not set -# CONFIG_MFD_ARIZONA_I2C is not set -# CONFIG_MFD_ARIZONA_SPI is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM831X_I2C is not set -# CONFIG_MFD_WM831X_SPI is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_WM8994 is not set -# CONFIG_MSM_CDC_PINCTRL is not set -# CONFIG_MSM_CDC_SUPPLY is not set -CONFIG_REGULATOR=y -# CONFIG_REGULATOR_DEBUG is not set +CONFIG_MSM_CDC_PINCTRL=y CONFIG_REGULATOR_FIXED_VOLTAGE=y -# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set -# CONFIG_REGULATOR_USERSPACE_CONSUMER is not set CONFIG_REGULATOR_PROXY_CONSUMER=y -# CONFIG_REGULATOR_ACT8865 is not set -# CONFIG_REGULATOR_AD5398 is not set -# CONFIG_REGULATOR_ANATOP is not set -# CONFIG_REGULATOR_DA9210 is not set -# CONFIG_REGULATOR_DA9211 is not set -# CONFIG_REGULATOR_FAN53555 is not set -# CONFIG_REGULATOR_GPIO is not set -# CONFIG_REGULATOR_ISL9305 is not set -# CONFIG_REGULATOR_ISL6271A is not set -# CONFIG_REGULATOR_LP3971 is not set -# CONFIG_REGULATOR_LP3972 is not set -# CONFIG_REGULATOR_LP872X is not set -# CONFIG_REGULATOR_LP8755 is not set -# CONFIG_REGULATOR_LTC3589 is not set -# CONFIG_REGULATOR_LTC3676 is not set -# CONFIG_REGULATOR_MAX1586 is not set -# CONFIG_REGULATOR_MAX8649 is not set -# CONFIG_REGULATOR_MAX8660 is not set -# CONFIG_REGULATOR_MAX8952 is not set -# CONFIG_REGULATOR_MAX8973 is not set -# CONFIG_REGULATOR_MT6311 is not set -# CONFIG_REGULATOR_PFUZE100 is not set -# CONFIG_REGULATOR_PV88060 is not set -# CONFIG_REGULATOR_PV88080 is not set -# CONFIG_REGULATOR_PV88090 is not set -# CONFIG_REGULATOR_PWM is not set -# CONFIG_REGULATOR_QCOM_SPMI is not set -# CONFIG_REGULATOR_TPS51632 is not set -# CONFIG_REGULATOR_TPS62360 is not set -# CONFIG_REGULATOR_TPS65023 is not set -# CONFIG_REGULATOR_TPS6507X is not set -# CONFIG_REGULATOR_TPS6524X is not set -# CONFIG_REGULATOR_CPR is not set -# CONFIG_REGULATOR_CPR3 is not set -# CONFIG_REGULATOR_CPR3_HMSS is not set -# CONFIG_REGULATOR_CPR3_MMSS is not set -# CONFIG_REGULATOR_CPR4_APSS is not set -# CONFIG_REGULATOR_CPR4_MMSS_LDO is not set -# CONFIG_REGULATOR_CPRH_KBSS is not set -# CONFIG_REGULATOR_KRYO is not set -# CONFIG_REGULATOR_MEM_ACC is not set -# CONFIG_REGULATOR_MSM_GFX_LDO is not set CONFIG_REGULATOR_QPNP_LABIBB=y -# CONFIG_REGULATOR_QPNP_LCDB is not set -# CONFIG_REGULATOR_QPNP_OLEDB is not set CONFIG_REGULATOR_QPNP=y CONFIG_REGULATOR_REFGEN=y CONFIG_REGULATOR_RPMH=y -# CONFIG_REGULATOR_SPM is not set CONFIG_REGULATOR_STUB=y CONFIG_MEDIA_SUPPORT=y - -# -# Multimedia core support -# CONFIG_MEDIA_CAMERA_SUPPORT=y -# CONFIG_MEDIA_ANALOG_TV_SUPPORT is not set CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y -# CONFIG_MEDIA_RADIO_SUPPORT is not set -# CONFIG_MEDIA_SDR_SUPPORT is not set -# CONFIG_MEDIA_RC_SUPPORT is not set CONFIG_MEDIA_CONTROLLER=y -# CONFIG_MEDIA_CONTROLLER_DVB is not set -CONFIG_VIDEO_DEV=y CONFIG_VIDEO_V4L2_SUBDEV_API=y -CONFIG_VIDEO_V4L2=y -# CONFIG_VIDEO_ADV_DEBUG is not set CONFIG_VIDEO_FIXED_MINOR_RANGES=y -CONFIG_V4L2_MEM2MEM_DEV=y -CONFIG_VIDEOBUF2_CORE=y -CONFIG_DVB_CORE=y -CONFIG_DVB_NET=y -# CONFIG_TTPCI_EEPROM is not set -CONFIG_DVB_MAX_ADAPTERS=8 -# CONFIG_DVB_DYNAMIC_MINORS is not set - -# -# Media drivers -# -# CONFIG_MEDIA_USB_SUPPORT is not set -# CONFIG_MEDIA_PCI_SUPPORT is not set CONFIG_V4L_PLATFORM_DRIVERS=y -# CONFIG_VIDEO_CAFE_CCIC is not set -# CONFIG_SOC_CAMERA is not set -# CONFIG_VIDEO_XILINX is not set - -# -# Qualcomm Technologies, Inc. MSM Camera And Video -# CONFIG_SPECTRA_CAMERA=y -# CONFIG_MSM_CAMERA is not set -# CONFIG_MSMB_CAMERA is not set CONFIG_USE_BU64748=y -# CONFIG_USE_ROHM_BU64753 is not set -# CONFIG_SPECTRA2_CAMERA is not set -# CONFIG_MSM_VIDC_3X_V4L2 is not set CONFIG_MSM_VIDC_V4L2=y CONFIG_MSM_VIDC_GOVERNORS=y CONFIG_MSM_SDE_ROTATOR=y -# CONFIG_MSM_SDE_ROTATOR_EVTLOG_DEBUG is not set -# CONFIG_DVB_MPQ is not set -# CONFIG_TSPP is not set -# CONFIG_V4L_MEM2MEM_DRIVERS is not set -# CONFIG_V4L_TEST_DRIVERS is not set -# CONFIG_DVB_PLATFORM_DRIVERS is not set - -# -# Qualcomm Technologies, Inc. MSM Camera And Video -# - -# -# Supported MMC/SDIO adapters -# -# CONFIG_SMS_SDIO_DRV is not set -# CONFIG_RADIO_IRIS is not set -# CONFIG_CYPRESS_FIRMWARE is not set - -# -# Media ancillary drivers (tuners, sensors, i2c, spi, frontends) -# -CONFIG_MEDIA_SUBDRV_AUTOSELECT=y - -# -# Audio decoders, processors and mixers -# - -# -# RDS decoders -# - -# -# Video decoders -# - -# -# Video and audio decoders -# - -# -# Video encoders -# - -# -# Camera sensor devices -# - -# -# Flash devices -# - -# -# Video improvement chips -# - -# -# Audio/Video compression chips -# - -# -# Miscellaneous helper chips -# - -# -# Sensors used on soc_camera driver -# -CONFIG_MEDIA_TUNER=y -CONFIG_MEDIA_TUNER_SIMPLE=y -CONFIG_MEDIA_TUNER_TDA8290=y -CONFIG_MEDIA_TUNER_TDA827X=y -CONFIG_MEDIA_TUNER_TDA18271=y -CONFIG_MEDIA_TUNER_TDA9887=y -CONFIG_MEDIA_TUNER_MT20XX=y -CONFIG_MEDIA_TUNER_XC2028=y -CONFIG_MEDIA_TUNER_XC5000=y -CONFIG_MEDIA_TUNER_XC4000=y -CONFIG_MEDIA_TUNER_MC44S803=y - -# -# Multistandard (satellite) frontends -# - -# -# Multistandard (cable + terrestrial) frontends -# - -# -# DVB-S (satellite) frontends -# - -# -# DVB-T (terrestrial) frontends -# -# CONFIG_DVB_AS102_FE is not set -# CONFIG_DVB_GP8PSK_FE is not set - -# -# DVB-C (cable) frontends -# - -# -# ATSC (North American/Korean Terrestrial/Cable DTV) frontends -# - -# -# ISDB-T (terrestrial) frontends -# - -# -# ISDB-S (satellite) & ISDB-T (terrestrial) frontends -# - -# -# Digital terrestrial only tuners/PLL -# - -# -# SEC control devices for DVB-S -# - -# -# Tools to develop new frontends -# -# CONFIG_DVB_DUMMY_FE is not set - -# -# Graphics support -# -CONFIG_VGA_ARB=y -CONFIG_VGA_ARB_MAX_GPUS=16 CONFIG_QCOM_KGSL=y -CONFIG_QCOM_ADRENO_DEFAULT_GOVERNOR="msm-adreno-tz" -CONFIG_QCOM_KGSL_IOMMU=y CONFIG_DRM=y -CONFIG_DRM_MIPI_DSI=y -# CONFIG_DRM_DP_AUX_CHARDEV is not set -CONFIG_DRM_KMS_HELPER=y -# CONFIG_DRM_FBDEV_EMULATION is not set -# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set - -# -# I2C encoder or helper chips -# -# CONFIG_DRM_I2C_CH7006 is not set -# CONFIG_DRM_I2C_SIL164 is not set -# CONFIG_DRM_I2C_NXP_TDA998X is not set -# CONFIG_DRM_HDLCD is not set -# CONFIG_DRM_MALI_DISPLAY is not set -# CONFIG_DRM_RADEON is not set -# CONFIG_DRM_AMDGPU is not set - -# -# ACP (Audio CoProcessor) Configuration -# -# CONFIG_DRM_NOUVEAU is not set -# CONFIG_DRM_VGEM is not set -# CONFIG_DRM_UDL is not set -# CONFIG_DRM_AST is not set -# CONFIG_DRM_MGAG200 is not set -# CONFIG_DRM_CIRRUS_QEMU is not set -# CONFIG_DRM_QXL is not set -# CONFIG_DRM_BOCHS is not set -CONFIG_DRM_MSM=y -# CONFIG_DRM_MSM_REGISTER_LOGGING is not set -# CONFIG_DRM_MSM_HDMI_HDCP is not set -# CONFIG_DRM_MSM_HDMI is not set -# CONFIG_DRM_MSM_DSI is not set -CONFIG_DRM_MSM_DSI_STAGING=y -# CONFIG_DRM_MSM_MDP5 is not set -# CONFIG_DRM_MSM_MDP4 is not set -# CONFIG_DRM_MSM_HDCP is not set -CONFIG_DRM_SDE_WB=y -# CONFIG_DRM_SDE_EVTLOG_DEBUG is not set CONFIG_DRM_SDE_RSC=y -# CONFIG_DRM_SDE_XLOG_DEBUG is not set -CONFIG_KLAPSE=y -CONFIG_DRM_PANEL=y - -# -# Display Panels -# -# CONFIG_DRM_PANEL_SIMPLE is not set -# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set -# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set -# CONFIG_DRM_PANEL_LG_LG4573 is not set -# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set -# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set -# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set -# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set -CONFIG_DRM_BRIDGE=y - -# -# Display Interface Bridges -# -# CONFIG_DRM_ANALOGIX_ANX78XX is not set -# CONFIG_DRM_DUMB_VGA_DAC is not set -# CONFIG_DRM_NXP_PTN3460 is not set -# CONFIG_DRM_PARADE_PS8622 is not set -# CONFIG_DRM_SII902X is not set -# CONFIG_DRM_TOSHIBA_TC358767 is not set -# CONFIG_DRM_LT_LT9611 is not set -# CONFIG_DRM_I2C_ADV7511 is not set -# CONFIG_DRM_ARCPGU is not set -# CONFIG_DRM_HISI_KIRIN is not set -# CONFIG_DRM_LEGACY is not set - -# -# Frame buffer Devices -# -CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -CONFIG_FB_CMDLINE=y -CONFIG_FB_NOTIFY=y -# CONFIG_FB_DDC is not set -# CONFIG_FB_BOOT_VESA_SUPPORT is not set -# CONFIG_FB_CFB_FILLRECT is not set -# CONFIG_FB_CFB_COPYAREA is not set -# CONFIG_FB_CFB_IMAGEBLIT is not set -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -CONFIG_FB_SYS_FILLRECT=y -CONFIG_FB_SYS_COPYAREA=y -CONFIG_FB_SYS_IMAGEBLIT=y -# CONFIG_FB_FOREIGN_ENDIAN is not set -CONFIG_FB_SYS_FOPS=y -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_MACMODES is not set -# CONFIG_FB_BACKLIGHT is not set -# CONFIG_FB_MODE_HELPERS is not set -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# -# CONFIG_FB_CIRRUS is not set -# CONFIG_FB_PM2 is not set -# CONFIG_FB_ARMCLCD is not set -# CONFIG_FB_CYBER2000 is not set -# CONFIG_FB_ASILIANT is not set -# CONFIG_FB_IMSTT is not set -# CONFIG_FB_OPENCORES is not set -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_NVIDIA is not set -# CONFIG_FB_RIVA is not set -# CONFIG_FB_I740 is not set -# CONFIG_FB_MATROX is not set -# CONFIG_FB_RADEON is not set -# CONFIG_FB_ATY128 is not set -# CONFIG_FB_ATY is not set -# CONFIG_FB_S3 is not set -# CONFIG_FB_SAVAGE is not set -# CONFIG_FB_SIS is not set -# CONFIG_FB_NEOMAGIC is not set -# CONFIG_FB_KYRO is not set -# CONFIG_FB_3DFX is not set -# CONFIG_FB_VOODOO1 is not set -# CONFIG_FB_VT8623 is not set -# CONFIG_FB_TRIDENT is not set -# CONFIG_FB_ARK is not set -# CONFIG_FB_PM3 is not set -# CONFIG_FB_CARMINE is not set -# CONFIG_FB_SMSCUFX is not set -# CONFIG_FB_UDL is not set -# CONFIG_FB_IBM_GXT4500 is not set CONFIG_FB_VIRTUAL=y -# CONFIG_FB_METRONOME is not set -# CONFIG_FB_MB862XX is not set -# CONFIG_FB_MSM is not set -# CONFIG_FB_BROADSHEET is not set -# CONFIG_FB_AUO_K190X is not set -# CONFIG_FB_SIMPLE is not set -# CONFIG_MSM_DBA is not set -# CONFIG_FB_SSD1307 is not set -# CONFIG_FB_SM712 is not set CONFIG_BACKLIGHT_LCD_SUPPORT=y # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_GENERIC=y -# CONFIG_BACKLIGHT_PWM is not set -# CONFIG_BACKLIGHT_PM8941_WLED is not set -# CONFIG_BACKLIGHT_ADP8860 is not set -# CONFIG_BACKLIGHT_ADP8870 is not set -# CONFIG_BACKLIGHT_LM3630A is not set -# CONFIG_BACKLIGHT_LM3639 is not set -# CONFIG_BACKLIGHT_LP855X is not set -# CONFIG_BACKLIGHT_GPIO is not set -# CONFIG_BACKLIGHT_LV5207LP is not set -# CONFIG_BACKLIGHT_BD6107 is not set -# CONFIG_VGASTATE is not set -CONFIG_HDMI=y CONFIG_LOGO=y # CONFIG_LOGO_LINUX_MONO is not set # CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_LOGO_LINUX_CLUT224=y CONFIG_SOUND=y -# CONFIG_SOUND_OSS_CORE is not set CONFIG_SND=y -CONFIG_SND_TIMER=y -CONFIG_SND_PCM=y -CONFIG_SND_PCM_ELD=y -CONFIG_SND_PCM_IEC958=y -CONFIG_SND_HWDEP=y -CONFIG_SND_RAWMIDI=y -CONFIG_SND_COMPRESS_OFFLOAD=y -CONFIG_SND_JACK=y -CONFIG_SND_JACK_INPUT_DEV=y -# CONFIG_SND_SEQUENCER is not set -# CONFIG_SND_MIXER_OSS is not set -# CONFIG_SND_PCM_OSS is not set -CONFIG_SND_PCM_TIMER=y -# CONFIG_SND_HRTIMER is not set CONFIG_SND_DYNAMIC_MINORS=y -CONFIG_SND_MAX_CARDS=32 -CONFIG_SND_SUPPORT_OLD_API=y -CONFIG_SND_PROC_FS=y -CONFIG_SND_VERBOSE_PROCFS=y -# CONFIG_SND_VERBOSE_PRINTK is not set -# CONFIG_SND_DEBUG is not set -# CONFIG_SND_RAWMIDI_SEQ is not set -# CONFIG_SND_OPL3_LIB_SEQ is not set -# CONFIG_SND_OPL4_LIB_SEQ is not set -# CONFIG_SND_SBAWE_SEQ is not set -# CONFIG_SND_EMU10K1_SEQ is not set -CONFIG_SND_DRIVERS=y -# CONFIG_SND_DUMMY is not set -# CONFIG_SND_ALOOP is not set -# CONFIG_SND_MTPAV is not set -# CONFIG_SND_SERIAL_U16550 is not set -# CONFIG_SND_MPU401 is not set -CONFIG_SND_PCI=y -# CONFIG_SND_AD1889 is not set -# CONFIG_SND_ALS300 is not set -# CONFIG_SND_ALI5451 is not set -# CONFIG_SND_ATIIXP is not set -# CONFIG_SND_ATIIXP_MODEM is not set -# CONFIG_SND_AU8810 is not set -# CONFIG_SND_AU8820 is not set -# CONFIG_SND_AU8830 is not set -# CONFIG_SND_AW2 is not set -# CONFIG_SND_AZT3328 is not set -# CONFIG_SND_BT87X is not set -# CONFIG_SND_CA0106 is not set -# CONFIG_SND_CMIPCI is not set -# CONFIG_SND_OXYGEN is not set -# CONFIG_SND_CS4281 is not set -# CONFIG_SND_CS46XX is not set -# CONFIG_SND_CTXFI is not set -# CONFIG_SND_DARLA20 is not set -# CONFIG_SND_GINA20 is not set -# CONFIG_SND_LAYLA20 is not set -# CONFIG_SND_DARLA24 is not set -# CONFIG_SND_GINA24 is not set -# CONFIG_SND_LAYLA24 is not set -# CONFIG_SND_MONA is not set -# CONFIG_SND_MIA is not set -# CONFIG_SND_ECHO3G is not set -# CONFIG_SND_INDIGO is not set -# CONFIG_SND_INDIGOIO is not set -# CONFIG_SND_INDIGODJ is not set -# CONFIG_SND_INDIGOIOX is not set -# CONFIG_SND_INDIGODJX is not set -# CONFIG_SND_EMU10K1 is not set -# CONFIG_SND_EMU10K1X is not set -# CONFIG_SND_ENS1370 is not set -# CONFIG_SND_ENS1371 is not set -# CONFIG_SND_ES1938 is not set -# CONFIG_SND_ES1968 is not set -# CONFIG_SND_FM801 is not set -# CONFIG_SND_HDSP is not set -# CONFIG_SND_HDSPM is not set -# CONFIG_SND_ICE1712 is not set -# CONFIG_SND_ICE1724 is not set -# CONFIG_SND_INTEL8X0 is not set -# CONFIG_SND_INTEL8X0M is not set -# CONFIG_SND_KORG1212 is not set -# CONFIG_SND_LOLA is not set -# CONFIG_SND_LX6464ES is not set -# CONFIG_SND_MAESTRO3 is not set -# CONFIG_SND_MIXART is not set -# CONFIG_SND_NM256 is not set -# CONFIG_SND_PCXHR is not set -# CONFIG_SND_RIPTIDE is not set -# CONFIG_SND_RME32 is not set -# CONFIG_SND_RME96 is not set -# CONFIG_SND_RME9652 is not set -# CONFIG_SND_SE6X is not set -# CONFIG_SND_SONICVIBES is not set -# CONFIG_SND_TRIDENT is not set -# CONFIG_SND_VIA82XX is not set -# CONFIG_SND_VIA82XX_MODEM is not set -# CONFIG_SND_VIRTUOSO is not set -# CONFIG_SND_VX222 is not set -# CONFIG_SND_YMFPCI is not set - -# -# HD-Audio -# -# CONFIG_SND_HDA_INTEL is not set -CONFIG_SND_HDA_PREALLOC_SIZE=64 -CONFIG_SND_SPI=y -CONFIG_SND_USB=y CONFIG_SND_USB_AUDIO=y -# CONFIG_SND_USB_UA101 is not set -# CONFIG_SND_USB_CAIAQ is not set -# CONFIG_SND_USB_6FIRE is not set -# CONFIG_SND_USB_HIFACE is not set -# CONFIG_SND_BCD2000 is not set -# CONFIG_SND_USB_POD is not set -# CONFIG_SND_USB_PODHD is not set -# CONFIG_SND_USB_TONEPORT is not set -# CONFIG_SND_USB_VARIAX is not set CONFIG_SND_USB_AUDIO_QMI=y CONFIG_SND_SOC=y -CONFIG_SND_SOC_COMPRESS=y -# CONFIG_SND_SOC_AMD_ACP is not set -# CONFIG_SND_ATMEL_SOC is not set -# CONFIG_SND_DESIGNWARE_I2S is not set - -# -# SoC Audio for Freescale CPUs -# - -# -# Common SoC Audio options for Freescale CPUs: -# -# CONFIG_SND_SOC_FSL_ASRC is not set -# CONFIG_SND_SOC_FSL_SAI is not set -# CONFIG_SND_SOC_FSL_SSI is not set -# CONFIG_SND_SOC_FSL_SPDIF is not set -# CONFIG_SND_SOC_FSL_ESAI is not set -# CONFIG_SND_SOC_IMX_AUDMUX is not set -# CONFIG_SND_SOC_IMG is not set -# CONFIG_SND_SOC_QCOM is not set -# CONFIG_SND_SOC_XTFPGA_I2S is not set -CONFIG_SND_SOC_I2C_AND_SPI=y - -# -# CODEC drivers -# -# CONFIG_SND_SOC_AC97_CODEC is not set -# CONFIG_SND_SOC_ADAU1701 is not set -# CONFIG_SND_SOC_ADAU7002 is not set -# CONFIG_SND_SOC_AK4104 is not set -# CONFIG_SND_SOC_AK4554 is not set -# CONFIG_SND_SOC_AK4613 is not set -# CONFIG_SND_SOC_AK4642 is not set -# CONFIG_SND_SOC_AK5386 is not set -# CONFIG_SND_SOC_ALC5623 is not set -# CONFIG_SND_SOC_BT_SCO is not set -# CONFIG_SND_SOC_CS35L32 is not set -# CONFIG_SND_SOC_CS35L33 is not set -# CONFIG_SND_SOC_CS42L51_I2C is not set -# CONFIG_SND_SOC_CS42L52 is not set -# CONFIG_SND_SOC_CS42L56 is not set -# CONFIG_SND_SOC_CS42L73 is not set -# CONFIG_SND_SOC_CS4265 is not set -# CONFIG_SND_SOC_CS4270 is not set -# CONFIG_SND_SOC_CS4271_I2C is not set -# CONFIG_SND_SOC_CS4271_SPI is not set -# CONFIG_SND_SOC_CS42XX8_I2C is not set -# CONFIG_SND_SOC_CS4349 is not set -# CONFIG_SND_SOC_CS53L30 is not set -CONFIG_SND_SOC_HDMI_CODEC=y -# CONFIG_SND_SOC_ES8328 is not set -# CONFIG_SND_SOC_GTM601 is not set -# CONFIG_SND_SOC_INNO_RK3036 is not set -# CONFIG_SND_SOC_MAX98504 is not set -# CONFIG_SND_SOC_MAX9860 is not set -# CONFIG_SND_SOC_PCM1681 is not set -# CONFIG_SND_SOC_PCM179X_I2C is not set -# CONFIG_SND_SOC_PCM179X_SPI is not set -# CONFIG_SND_SOC_PCM3168A_I2C is not set -# CONFIG_SND_SOC_PCM3168A_SPI is not set -# CONFIG_SND_SOC_PCM512x_I2C is not set -# CONFIG_SND_SOC_PCM512x_SPI is not set -# CONFIG_SND_SOC_RT5616 is not set -# CONFIG_SND_SOC_RT5631 is not set -# CONFIG_SND_SOC_RT5677_SPI is not set -# CONFIG_SND_SOC_SGTL5000 is not set -# CONFIG_SND_SOC_SIRF_AUDIO_CODEC is not set -# CONFIG_SND_SOC_SPDIF is not set -# CONFIG_SND_SOC_SSM2602_SPI is not set -# CONFIG_SND_SOC_SSM2602_I2C is not set -# CONFIG_SND_SOC_SSM4567 is not set -# CONFIG_SND_SOC_STA32X is not set -# CONFIG_SND_SOC_STA350 is not set -# CONFIG_SND_SOC_STI_SAS is not set -# CONFIG_SND_SOC_TAS2552 is not set -# CONFIG_SND_SOC_TAS5086 is not set -# CONFIG_SND_SOC_TAS571X is not set -# CONFIG_SND_SOC_TAS5720 is not set -# CONFIG_SND_SOC_TFA9879 is not set -# CONFIG_SND_SOC_TLV320AIC23_I2C is not set -# CONFIG_SND_SOC_TLV320AIC23_SPI is not set -# CONFIG_SND_SOC_TLV320AIC31XX is not set -# CONFIG_SND_SOC_TLV320AIC3X is not set -# CONFIG_SND_SOC_TS3A227E is not set -# CONFIG_SND_SOC_WM8510 is not set -# CONFIG_SND_SOC_WM8523 is not set -# CONFIG_SND_SOC_WM8580 is not set -# CONFIG_SND_SOC_WM8711 is not set -# CONFIG_SND_SOC_WM8728 is not set -# CONFIG_SND_SOC_WM8731 is not set -# CONFIG_SND_SOC_WM8737 is not set -# CONFIG_SND_SOC_WM8741 is not set -# CONFIG_SND_SOC_WM8750 is not set -# CONFIG_SND_SOC_WM8753 is not set -# CONFIG_SND_SOC_WM8770 is not set -# CONFIG_SND_SOC_WM8776 is not set -# CONFIG_SND_SOC_WM8804_I2C is not set -# CONFIG_SND_SOC_WM8804_SPI is not set -# CONFIG_SND_SOC_WM8903 is not set -# CONFIG_SND_SOC_WM8960 is not set -# CONFIG_SND_SOC_WM8962 is not set -# CONFIG_SND_SOC_WM8974 is not set -# CONFIG_SND_SOC_WM8978 is not set -# CONFIG_SND_SOC_WM8985 is not set -# CONFIG_SND_SOC_NAU8810 is not set -# CONFIG_SND_SOC_TPA6130A2 is not set -# CONFIG_SND_SIMPLE_CARD is not set -# CONFIG_SND_SIMPLE_SCU_CARD is not set -# CONFIG_SOUND_PRIME is not set - -# -# HID support -# -CONFIG_HID=y -# CONFIG_HID_BATTERY_STRENGTH is not set -# CONFIG_HIDRAW is not set CONFIG_UHID=y -CONFIG_HID_GENERIC=y - -# -# Special HID drivers -# -# CONFIG_HID_A4TECH is not set -# CONFIG_HID_ACRUX is not set CONFIG_HID_APPLE=y -# CONFIG_HID_APPLEIR is not set -# CONFIG_HID_AUREAL is not set -# CONFIG_HID_BELKIN is not set -# CONFIG_HID_BETOP_FF is not set -# CONFIG_HID_CHERRY is not set -# CONFIG_HID_CHICONY is not set -# CONFIG_HID_CORSAIR is not set -# CONFIG_HID_PRODIKEYS is not set -# CONFIG_HID_CMEDIA is not set -# CONFIG_HID_CP2112 is not set -# CONFIG_HID_CYPRESS is not set -CONFIG_HID_DRAGONRISE=y -# CONFIG_DRAGONRISE_FF is not set -# CONFIG_HID_EMS_FF is not set CONFIG_HID_ELECOM=y -# CONFIG_HID_ELO is not set -# CONFIG_HID_EZKEY is not set -# CONFIG_HID_GEMBIRD is not set -# CONFIG_HID_GFRM is not set -# CONFIG_HID_HOLTEK is not set -# CONFIG_HID_GT683R is not set -# CONFIG_HID_KEYTOUCH is not set -# CONFIG_HID_KYE is not set -# CONFIG_HID_UCLOGIC is not set -# CONFIG_HID_WALTOP is not set -# CONFIG_HID_GYRATION is not set -# CONFIG_HID_ICADE is not set -# CONFIG_HID_TWINHAN is not set -# CONFIG_HID_KENSINGTON is not set -# CONFIG_HID_LCPOWER is not set -# CONFIG_HID_LED is not set -# CONFIG_HID_LENOVO is not set -# CONFIG_HID_LOGITECH is not set CONFIG_HID_MAGICMOUSE=y CONFIG_HID_MICROSOFT=y -# CONFIG_HID_MONTEREY is not set CONFIG_HID_MULTITOUCH=y -# CONFIG_HID_NTRIG is not set -# CONFIG_HID_ORTEK is not set -CONFIG_HID_PANTHERLORD=y -CONFIG_PANTHERLORD_FF=y -# CONFIG_HID_PENMOUNT is not set -# CONFIG_HID_PETALYNX is not set -# CONFIG_HID_PICOLCD is not set CONFIG_HID_PLANTRONICS=y -# CONFIG_HID_PRIMAX is not set -# CONFIG_HID_ROCCAT is not set -# CONFIG_HID_SAITEK is not set -# CONFIG_HID_SAMSUNG is not set -# CONFIG_HID_SONY is not set -# CONFIG_HID_SPEEDLINK is not set -# CONFIG_HID_STEELSERIES is not set -# CONFIG_HID_SUNPLUS is not set -# CONFIG_HID_RMI is not set -CONFIG_HID_GREENASIA=y -CONFIG_GREENASIA_FF=y -# CONFIG_HID_SMARTJOYPLUS is not set -# CONFIG_HID_TIVO is not set -# CONFIG_HID_TOPSEED is not set -# CONFIG_HID_THINGM is not set -# CONFIG_HID_THRUSTMASTER is not set -# CONFIG_HID_WACOM is not set -CONFIG_HID_WIIMOTE=y -# CONFIG_HID_XINMO is not set -# CONFIG_HID_ZEROPLUS is not set -# CONFIG_HID_ZYDACRON is not set -# CONFIG_HID_SENSOR_HUB is not set -# CONFIG_HID_ALPS is not set - -# -# USB HID support -# -CONFIG_USB_HID=y -# CONFIG_HID_PID is not set -CONFIG_USB_HIDDEV=y - -# -# I2C HID support -# -# CONFIG_I2C_HID is not set -CONFIG_USB_OHCI_LITTLE_ENDIAN=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_COMMON=y -CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_HID_SONY=y CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y - -# -# Miscellaneous USB options -# -CONFIG_USB_DEFAULT_PERSIST=y -# CONFIG_USB_DYNAMIC_MINORS is not set -# CONFIG_USB_OTG is not set -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set -# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set -# CONFIG_USB_MON is not set -# CONFIG_USB_WUSB_CBAF is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_C67X00_HCD is not set CONFIG_USB_XHCI_HCD=y -CONFIG_USB_XHCI_PCI=y -CONFIG_USB_XHCI_PLATFORM=y CONFIG_USB_EHCI_HCD=y -# CONFIG_USB_EHCI_ROOT_HUB_TT is not set -CONFIG_USB_EHCI_TT_NEWSCHED=y -CONFIG_USB_EHCI_PCI=y -# CONFIG_USB_EHCI_MSM is not set CONFIG_USB_EHCI_HCD_PLATFORM=y -# CONFIG_USB_OXU210HP_HCD is not set -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_ISP1362_HCD is not set -# CONFIG_USB_FOTG210_HCD is not set -# CONFIG_USB_MAX3421_HCD is not set CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PCI=y CONFIG_USB_OHCI_HCD_PLATFORM=y -# CONFIG_USB_UHCI_HCD is not set -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_HCD_TEST_MODE is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set -# CONFIG_USB_WDM is not set -# CONFIG_USB_TMC is not set - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# - -# -# also be needed; see USB_STORAGE Help for more info -# +CONFIG_USB_ACM=y CONFIG_USB_STORAGE=y -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_REALTEK is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_ONETOUCH is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set -# CONFIG_USB_STORAGE_ENE_UB6250 is not set -# CONFIG_USB_UAS is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USBIP_CORE is not set -# CONFIG_USB_MUSB_HDRC is not set CONFIG_USB_DWC3=y -# CONFIG_USB_DWC3_HOST is not set -# CONFIG_USB_DWC3_GADGET is not set -CONFIG_USB_DWC3_DUAL_ROLE=y - -# -# Platform Glue Driver Support -# -CONFIG_USB_DWC3_PCI=y -CONFIG_USB_DWC3_OF_SIMPLE=y CONFIG_USB_DWC3_MSM=y -# CONFIG_USB_DWC2 is not set -# CONFIG_USB_CHIPIDEA is not set CONFIG_USB_ISP1760=y -CONFIG_USB_ISP1760_HCD=y CONFIG_USB_ISP1760_HOST_ROLE=y -# CONFIG_USB_ISP1760_GADGET_ROLE is not set -# CONFIG_USB_ISP1760_DUAL_ROLE is not set - -# -# USB Power Delivery -# -CONFIG_USB_PD=y CONFIG_USB_PD_POLICY=y CONFIG_QPNP_USB_PDPHY=y - -# -# USB port drivers -# -# CONFIG_USB_SERIAL is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_SEVSEG is not set -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_FTDI_ELAN is not set -# CONFIG_USB_APPLEDISPLAY is not set -# CONFIG_USB_SISUSBVGA is not set -# CONFIG_USB_LD is not set -# CONFIG_USB_TRANCEVIBRATOR is not set -# CONFIG_USB_IOWARRIOR is not set -# CONFIG_USB_TEST is not set CONFIG_USB_EHSET_TEST_FIXTURE=y -# CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_YUREX is not set -# CONFIG_USB_EZUSB_FX2 is not set -# CONFIG_USB_HSIC_USB3503 is not set -# CONFIG_USB_HSIC_USB4604 is not set CONFIG_USB_LINK_LAYER_TEST=y -# CONFIG_USB_CHAOSKEY is not set - -# -# USB Physical Layer drivers -# -CONFIG_USB_PHY=y -# CONFIG_USB_OTG_WAKELOCK is not set CONFIG_NOP_USB_XCEIV=y -# CONFIG_USB_GPIO_VBUS is not set -# CONFIG_USB_ISP1301 is not set -# CONFIG_QCOM_USB_MSM_OTG is not set -# CONFIG_USB_QCOM_8X16_PHY is not set -# CONFIG_USB_ULPI is not set CONFIG_DUAL_ROLE_USB_INTF=y CONFIG_USB_MSM_SSPHY_QMP=y CONFIG_MSM_QUSB_PHY=y -# CONFIG_MSM_HSUSB_PHY is not set -# CONFIG_USB_MSM_OTG is not set CONFIG_USB_GADGET=y -# CONFIG_USB_GADGET_DEBUG is not set -# CONFIG_USB_GADGET_DEBUG_FILES is not set -# CONFIG_USB_GADGET_DEBUG_FS is not set CONFIG_USB_GADGET_VBUS_DRAW=500 -CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2 - -# -# USB Peripheral Controller -# -# CONFIG_USB_FOTG210_UDC is not set -# CONFIG_USB_GR_UDC is not set -# CONFIG_USB_R8A66597 is not set -# CONFIG_USB_PXA27X is not set -# CONFIG_USB_MV_UDC is not set -# CONFIG_USB_MV_U3D is not set -# CONFIG_USB_M66592 is not set -# CONFIG_USB_BDC_UDC is not set -# CONFIG_USB_AMD5536UDC is not set -# CONFIG_USB_NET2272 is not set -# CONFIG_USB_NET2280 is not set -# CONFIG_USB_GOKU is not set -# CONFIG_USB_EG20T is not set -# CONFIG_USB_GADGET_XILINX is not set -# CONFIG_USB_CI13XXX_MSM is not set -# CONFIG_USB_DUMMY_HCD is not set -CONFIG_USB_LIBCOMPOSITE=y -CONFIG_USB_U_ETHER=y -CONFIG_USB_F_NCM=y -CONFIG_USB_F_MASS_STORAGE=y -CONFIG_USB_F_FS=y -CONFIG_USB_F_MIDI=y -CONFIG_USB_F_HID=y -CONFIG_USB_F_MTP=y -CONFIG_USB_F_PTP=y -CONFIG_USB_F_AUDIO_SRC=y -CONFIG_USB_F_ACC=y -CONFIG_USB_F_DIAG=y -CONFIG_USB_F_CDEV=y -CONFIG_USB_F_CCID=y -CONFIG_USB_F_GSI=y -CONFIG_USB_F_QDSS=y CONFIG_USB_CONFIGFS=y -# CONFIG_USB_CONFIGFS_SERIAL is not set -# CONFIG_USB_CONFIGFS_ACM is not set -# CONFIG_USB_CONFIGFS_OBEX is not set CONFIG_USB_CONFIGFS_NCM=y -# CONFIG_USB_CONFIGFS_ECM is not set -# CONFIG_USB_CONFIGFS_ECM_SUBSET is not set -# CONFIG_USB_CONFIGFS_QCRNDIS is not set -# CONFIG_USB_CONFIGFS_RNDIS is not set -# CONFIG_USB_CONFIGFS_EEM is not set CONFIG_USB_CONFIGFS_MASS_STORAGE=y -# CONFIG_USB_CONFIGFS_F_LB_SS is not set CONFIG_USB_CONFIGFS_F_FS=y CONFIG_USB_CONFIGFS_F_MTP=y CONFIG_USB_CONFIGFS_F_PTP=y CONFIG_USB_CONFIGFS_F_ACC=y CONFIG_USB_CONFIGFS_F_AUDIO_SRC=y CONFIG_USB_CONFIGFS_UEVENT=y -# CONFIG_USB_CONFIGFS_F_UAC1 is not set -# CONFIG_USB_CONFIGFS_F_UAC2 is not set CONFIG_USB_CONFIGFS_F_MIDI=y CONFIG_USB_CONFIGFS_F_HID=y -# CONFIG_USB_CONFIGFS_F_UVC is not set -# CONFIG_USB_CONFIGFS_F_PRINTER is not set CONFIG_USB_CONFIGFS_F_DIAG=y CONFIG_USB_CONFIGFS_F_CDEV=y CONFIG_USB_CONFIGFS_F_CCID=y CONFIG_USB_CONFIGFS_F_GSI=y CONFIG_USB_CONFIGFS_F_QDSS=y -# CONFIG_USB_LED_TRIG is not set -# CONFIG_USB_ULPI_BUS is not set -# CONFIG_UWB is not set CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set CONFIG_MMC_PERF_PROFILING=y -CONFIG_PWRSEQ_EMMC=y -CONFIG_PWRSEQ_SIMPLE=y -# CONFIG_MMC_RING_BUFFER is not set -# CONFIG_MMC_EMBEDDED_SDIO is not set CONFIG_MMC_PARANOID_SD_INIT=y CONFIG_MMC_CLKGATE=y - -# -# MMC/SD/SDIO Card Drivers -# -CONFIG_MMC_BLOCK=y CONFIG_MMC_BLOCK_MINORS=32 -CONFIG_MMC_BLOCK_BOUNCE=y CONFIG_MMC_BLOCK_DEFERRED_RESUME=y -# CONFIG_SDIO_UART is not set -# CONFIG_MMC_TEST is not set -# CONFIG_MMC_SIMULATE_MAX_SPEED is not set - -# -# MMC/SD/SDIO Host Controller Drivers -# -# CONFIG_MMC_ARMMMCI is not set CONFIG_MMC_SDHCI=y -# CONFIG_MMC_SDHCI_PCI is not set CONFIG_MMC_SDHCI_PLTFM=y -# CONFIG_MMC_SDHCI_OF_ARASAN is not set -# CONFIG_MMC_SDHCI_OF_AT91 is not set -# CONFIG_MMC_SDHCI_F_SDH30 is not set CONFIG_MMC_SDHCI_MSM=y -# CONFIG_MMC_SDHCI_MSM_ICE is not set -# CONFIG_MMC_TIFM_SD is not set -# CONFIG_MMC_SPI is not set -# CONFIG_MMC_CB710 is not set -# CONFIG_MMC_VIA_SDMMC is not set -# CONFIG_MMC_DW is not set -# CONFIG_MMC_VUB300 is not set -# CONFIG_MMC_USHC is not set -# CONFIG_MMC_USDHI6ROL0 is not set -# CONFIG_MMC_CQ_HCI is not set -# CONFIG_MMC_TOSHIBA_PCI is not set -# CONFIG_MMC_MTK is not set -# CONFIG_MEMSTICK is not set CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y -# CONFIG_LEDS_CLASS_FLASH is not set - -# -# LED drivers -# -# CONFIG_LEDS_BCM6328 is not set -# CONFIG_LEDS_BCM6358 is not set -# CONFIG_LEDS_LM3530 is not set -# CONFIG_LEDS_LM3642 is not set CONFIG_LEDS_LM3644=y -# CONFIG_LEDS_PCA9532 is not set -# CONFIG_LEDS_GPIO is not set -# CONFIG_LEDS_LP3944 is not set -# CONFIG_LEDS_LP5521 is not set -# CONFIG_LEDS_LP5523 is not set -# CONFIG_LEDS_LP5562 is not set -# CONFIG_LEDS_LP8501 is not set -# CONFIG_LEDS_LP8860 is not set -# CONFIG_LEDS_PCA955X is not set -# CONFIG_LEDS_PCA963X is not set -# CONFIG_LEDS_DAC124S085 is not set -# CONFIG_LEDS_PWM is not set -# CONFIG_LEDS_REGULATOR is not set -# CONFIG_LEDS_BD2802 is not set -# CONFIG_LEDS_LT3593 is not set -# CONFIG_LEDS_TCA6507 is not set -# CONFIG_LEDS_TLC591XX is not set -# CONFIG_LEDS_LM355x is not set -# CONFIG_LEDS_IS31FL319X is not set -# CONFIG_LEDS_IS31FL32XX is not set - -# -# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) -# -# CONFIG_LEDS_BLINKM is not set -# CONFIG_LEDS_QTI_TRI_LED is not set -# CONFIG_LEDS_SYSCON is not set CONFIG_LEDS_QPNP=y -# CONFIG_LEDS_QPNP_FLASH is not set CONFIG_LEDS_QPNP_FLASH_V2=y CONFIG_LEDS_QPNP_WLED=y CONFIG_LEDS_QPNP_HAPTICS=y -# CONFIG_LEDS_QPNP_VIBRATOR_LDO is not set -# CONFIG_LEDS_QPNP_VIBRATOR is not set - -# -# LED Triggers -# CONFIG_LEDS_TRIGGERS=y -# CONFIG_LEDS_TRIGGER_TIMER is not set -# CONFIG_LEDS_TRIGGER_ONESHOT is not set -# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set -# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set -# CONFIG_LEDS_TRIGGER_CPU is not set -# CONFIG_LEDS_TRIGGER_GPIO is not set -# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set - -# -# iptables trigger is under Netfilter config (LED target) -# -# CONFIG_LEDS_TRIGGER_TRANSIENT is not set -# CONFIG_LEDS_TRIGGER_CAMERA is not set -# CONFIG_LEDS_TRIGGER_PANIC is not set -# CONFIG_ACCESSIBILITY is not set -# CONFIG_INFINIBAND is not set -CONFIG_EDAC_SUPPORT=y -# CONFIG_EDAC is not set -CONFIG_RTC_LIB=y CONFIG_RTC_CLASS=y -CONFIG_RTC_HCTOSYS=y -CONFIG_RTC_HCTOSYS_DEVICE="rtc0" -CONFIG_RTC_SYSTOHC=y -CONFIG_RTC_SYSTOHC_DEVICE="rtc0" -# CONFIG_RTC_DEBUG is not set - -# -# RTC interfaces -# -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_DEV=y -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -# CONFIG_RTC_DRV_TEST is not set - -# -# I2C RTC drivers -# -# CONFIG_RTC_DRV_ABB5ZES3 is not set -# CONFIG_RTC_DRV_ABX80X is not set -# CONFIG_RTC_DRV_DS1307 is not set -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_HYM8563 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_ISL12022 is not set -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF8523 is not set -# CONFIG_RTC_DRV_PCF85063 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_M41T80 is not set -# CONFIG_RTC_DRV_BQ32K is not set -# CONFIG_RTC_DRV_S35390A is not set -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_RX8010 is not set -# CONFIG_RTC_DRV_RX8581 is not set -# CONFIG_RTC_DRV_RX8025 is not set -# CONFIG_RTC_DRV_EM3027 is not set -# CONFIG_RTC_DRV_RV8803 is not set - -# -# SPI RTC drivers -# -# CONFIG_RTC_DRV_M41T93 is not set -# CONFIG_RTC_DRV_M41T94 is not set -# CONFIG_RTC_DRV_DS1302 is not set -# CONFIG_RTC_DRV_DS1305 is not set -# CONFIG_RTC_DRV_DS1343 is not set -# CONFIG_RTC_DRV_DS1347 is not set -# CONFIG_RTC_DRV_DS1390 is not set -# CONFIG_RTC_DRV_MAX6916 is not set -# CONFIG_RTC_DRV_R9701 is not set -# CONFIG_RTC_DRV_RX4581 is not set -# CONFIG_RTC_DRV_RX6110 is not set -# CONFIG_RTC_DRV_RS5C348 is not set -# CONFIG_RTC_DRV_MAX6902 is not set -# CONFIG_RTC_DRV_PCF2123 is not set -# CONFIG_RTC_DRV_MCP795 is not set -CONFIG_RTC_I2C_AND_SPI=y - -# -# SPI and I2C RTC drivers -# -# CONFIG_RTC_DRV_DS3232 is not set -# CONFIG_RTC_DRV_PCF2127 is not set -# CONFIG_RTC_DRV_RV3029C2 is not set - -# -# Platform RTC drivers -# -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1685_FAMILY is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_DS2404 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_MSM6242 is not set -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_RP5C01 is not set -# CONFIG_RTC_DRV_V3020 is not set -# CONFIG_RTC_DRV_ZYNQMP is not set - -# -# on-CPU RTC drivers -# -# CONFIG_RTC_DRV_PL030 is not set -# CONFIG_RTC_DRV_PL031 is not set -# CONFIG_RTC_DRV_PM8XXX is not set CONFIG_RTC_DRV_QPNP=y -# CONFIG_RTC_DRV_SNVS is not set - -# -# HID Sensor RTC drivers -# -# CONFIG_RTC_DRV_HID_SENSOR_TIME is not set -CONFIG_ESOC=y -CONFIG_ESOC_DEV=y -CONFIG_ESOC_CLIENT=y -# CONFIG_ESOC_DEBUG is not set -CONFIG_ESOC_MDM_4x=y -CONFIG_ESOC_MDM_DRV=y -CONFIG_ESOC_MDM_DBG_ENG=y -# CONFIG_MDM_DBG_REQ_ENG is not set CONFIG_DMADEVICES=y -# CONFIG_DMADEVICES_DEBUG is not set - -# -# DMA Devices -# -CONFIG_DMA_ENGINE=y -CONFIG_DMA_VIRTUAL_CHANNELS=y -CONFIG_DMA_OF=y -# CONFIG_AMBA_PL08X is not set -# CONFIG_FSL_EDMA is not set -# CONFIG_INTEL_IDMA64 is not set -# CONFIG_MV_XOR_V2 is not set -# CONFIG_PL330_DMA is not set -# CONFIG_QCOM_SPS_DMA is not set -# CONFIG_XILINX_DMA is not set -# CONFIG_XILINX_ZYNQMP_DMA is not set -# CONFIG_QCOM_BAM_DMA is not set -# CONFIG_QCOM_HIDMA_MGMT is not set -# CONFIG_QCOM_HIDMA is not set CONFIG_QCOM_GPI_DMA=y -# CONFIG_QCOM_GPI_DMA_DEBUG is not set -# CONFIG_DW_DMAC is not set -# CONFIG_DW_DMAC_PCI is not set - -# -# DMA Clients -# -# CONFIG_ASYNC_TX_DMA is not set -# CONFIG_DMATEST is not set - -# -# DMABUF options -# -CONFIG_SYNC_FILE=y -# CONFIG_SW_SYNC is not set -# CONFIG_AUXDISPLAY is not set CONFIG_UIO=y -# CONFIG_UIO_CIF is not set -# CONFIG_UIO_PDRV_GENIRQ is not set -# CONFIG_UIO_DMEM_GENIRQ is not set -# CONFIG_UIO_AEC is not set -# CONFIG_UIO_SERCOS3 is not set -# CONFIG_UIO_PCI_GENERIC is not set -# CONFIG_UIO_NETX is not set -# CONFIG_UIO_PRUSS is not set -# CONFIG_UIO_MF624 is not set CONFIG_UIO_MSM_SHAREDMEM=y -# CONFIG_VFIO is not set -# CONFIG_VIRT_DRIVERS is not set - -# -# Virtio drivers -# -# CONFIG_VIRTIO_PCI is not set -# CONFIG_VIRTIO_MMIO is not set - -# -# Microsoft Hyper-V guest support -# CONFIG_STAGING=y -# CONFIG_PRISM2_USB is not set -# CONFIG_R8712U is not set -# CONFIG_R8188EU is not set -# CONFIG_RTS5208 is not set - -# -# IIO staging drivers -# - -# -# Accelerometers -# -# CONFIG_ADIS16201 is not set -# CONFIG_ADIS16203 is not set -# CONFIG_ADIS16209 is not set -# CONFIG_ADIS16240 is not set - -# -# Analog to digital converters -# -# CONFIG_AD7606 is not set -# CONFIG_AD7780 is not set -# CONFIG_AD7816 is not set -# CONFIG_AD7192 is not set -# CONFIG_AD7280 is not set - -# -# Analog digital bi-direction converters -# -# CONFIG_ADT7316 is not set - -# -# Capacitance to digital converters -# -# CONFIG_AD7150 is not set -# CONFIG_AD7152 is not set -# CONFIG_AD7746 is not set - -# -# Direct Digital Synthesis -# -# CONFIG_AD9832 is not set -# CONFIG_AD9834 is not set - -# -# Digital gyroscope sensors -# -# CONFIG_ADIS16060 is not set - -# -# Network Analyzer, Impedance Converters -# -# CONFIG_AD5933 is not set - -# -# Light sensors -# -# CONFIG_SENSORS_ISL29018 is not set -# CONFIG_SENSORS_ISL29028 is not set -# CONFIG_TSL2583 is not set -# CONFIG_TSL2x7x is not set - -# -# Active energy metering IC -# -# CONFIG_ADE7753 is not set -# CONFIG_ADE7754 is not set -# CONFIG_ADE7758 is not set -# CONFIG_ADE7759 is not set -# CONFIG_ADE7854 is not set - -# -# Resolver to digital converters -# -# CONFIG_AD2S90 is not set -# CONFIG_AD2S1200 is not set -# CONFIG_AD2S1210 is not set - -# -# Triggers - standalone -# -# CONFIG_FB_SM750 is not set -# CONFIG_FB_XGI is not set - -# -# Speakup console speech -# -# CONFIG_STAGING_MEDIA is not set - -# -# Android -# CONFIG_ASHMEM=y CONFIG_ANDROID_LOW_MEMORY_KILLER=y -CONFIG_ANDROID_LOW_MEMORY_KILLER_AUTODETECT_OOM_ADJ_VALUES=y -# CONFIG_ANDROID_VSOC is not set CONFIG_ION=y -# CONFIG_ION_TEST is not set -# CONFIG_ION_DUMMY is not set CONFIG_ION_MSM=y -# CONFIG_ALLOC_BUFFERS_IN_4K_CHUNKS is not set -# CONFIG_FIQ_DEBUGGER is not set -# CONFIG_FIQ_WATCHDOG is not set -# CONFIG_STAGING_BOARD is not set -# CONFIG_DGNC is not set -# CONFIG_GS_FPGABOOT is not set -# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set -# CONFIG_FB_TFT is not set -# CONFIG_FSL_MC_BUS is not set -# CONFIG_WILC1000_SDIO is not set -# CONFIG_WILC1000_SPI is not set -# CONFIG_MOST is not set -# CONFIG_KS7010 is not set -# CONFIG_GREYBUS is not set - -# -# Qualcomm Atheros CLD WLAN module -# CONFIG_QCA_CLD_WLAN=y -CONFIG_QCACLD_WLAN_LFR3=y -CONFIG_PRIMA_WLAN_11AC_HIGH_TP=y -CONFIG_WLAN_FEATURE_11W=y -CONFIG_WLAN_FEATURE_LPSS=y -CONFIG_QCOM_VOWIFI_11R=y -CONFIG_QCACLD_FEATURE_NAN=y -CONFIG_WLAN_FEATURE_NAN_DATAPATH=y -CONFIG_QCACLD_FEATURE_GREEN_AP=y -CONFIG_HELIUMPLUS=y -CONFIG_64BIT_PADDR=y -CONFIG_QCOM_TDLS=y -CONFIG_QCOM_LTE_COEX=y -CONFIG_MPC_UT_FRAMEWORK=y -CONFIG_WLAN_OFFLOAD_PACKETS=y -CONFIG_FEATURE_TSO=y -# CONFIG_FEATURE_TSO_DEBUG is not set -CONFIG_WLAN_FASTPATH=y -CONFIG_WLAN_NAPI=y -# CONFIG_WLAN_NAPI_DEBUG is not set -CONFIG_WLAN_TX_FLOW_CONTROL_V2=y -CONFIG_WLAN_SYNC_TSF=y -CONFIG_LFR_SUBNET_DETECTION=y -CONFIG_MCC_TO_SCC_SWITCH=y -CONFIG_QCACLD_WLAN_LFR2=y -CONFIG_WLAN_FEATURE_DISA=y -CONFIG_ICMP_DISABLE_PS=y -CONFIG_BUILD_TIMESTAMP=y -# CONFIG_WLAN_FEATURE_SARV1_TO_SARV2 is not set -CONFIG_WLAN_FEATURE_FILS=y -# CONFIG_WLAN_FEATURE_OWE is not set -# CONFIG_WLAN_FEATURE_GMAC is not set -# CONFIG_WLAN_FEATURE_SAE is not set -CONFIG_QCACLD_FEATURE_METERING=y -# CONFIG_QCA_CLD_DEBUG is not set -# CONFIG_GOLDFISH is not set -# CONFIG_CHROME_PLATFORMS is not set - -# -# Qualcomm technologies inc. MSM specific device drivers -# -# CONFIG_IPA is not set CONFIG_GSI=y CONFIG_IPA3=y -# CONFIG_IPA_WDI_UNIFIED_API is not set CONFIG_RMNET_IPA3=y -# CONFIG_ECM_IPA is not set CONFIG_RNDIS_IPA=y CONFIG_IPA_UT=y CONFIG_SPS=y -# CONFIG_SPS_SUPPORT_BAMDMA is not set CONFIG_SPS_SUPPORT_NDP_BAM=y -# CONFIG_EP_PCIE is not set CONFIG_QPNP_COINCELL=y CONFIG_QPNP_REVID=y -# CONFIG_GPIO_USB_DETECT is not set CONFIG_USB_BAM=y -# CONFIG_MSM_11AD is not set CONFIG_SEEMP_CORE=y CONFIG_QCOM_GENI_SE=y -CONFIG_MSM_EXT_DISPLAY=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_HAVE_CLK_PREPARE=y -CONFIG_COMMON_CLK=y - -# -# Common Clock Framework -# -# CONFIG_COMMON_CLK_VERSATILE is not set -# CONFIG_COMMON_CLK_SI5351 is not set -# CONFIG_COMMON_CLK_SI514 is not set -# CONFIG_COMMON_CLK_SI570 is not set -# CONFIG_COMMON_CLK_CDCE706 is not set -# CONFIG_COMMON_CLK_CDCE925 is not set -# CONFIG_COMMON_CLK_CS2000_CP is not set -# CONFIG_CLK_QORIQ is not set -CONFIG_COMMON_CLK_XGENE=y -# CONFIG_COMMON_CLK_NXP is not set -# CONFIG_COMMON_CLK_PWM is not set -# CONFIG_COMMON_CLK_PXA is not set -# CONFIG_COMMON_CLK_PIC32 is not set -CONFIG_QCOM_GDSC=y -CONFIG_COMMON_CLK_QCOM=y -# CONFIG_APQ_GCC_8084 is not set -# CONFIG_APQ_MMCC_8084 is not set -# CONFIG_IPQ_GCC_4019 is not set -# CONFIG_IPQ_GCC_806X is not set -# CONFIG_IPQ_LCC_806X is not set -# CONFIG_MSM_GCC_8660 is not set -# CONFIG_MSM_GCC_8916 is not set -# CONFIG_MSM_GCC_8960 is not set -# CONFIG_MSM_LCC_8960 is not set -# CONFIG_MDM_GCC_9615 is not set -# CONFIG_MDM_LCC_9615 is not set -# CONFIG_MSM_MMCC_8960 is not set -# CONFIG_MSM_GCC_8974 is not set -# CONFIG_MSM_MMCC_8974 is not set -# CONFIG_MSM_GCC_8996 is not set -# CONFIG_MSM_MMCC_8996 is not set CONFIG_MSM_GCC_SDM845=y CONFIG_MSM_VIDEOCC_SDM845=y CONFIG_MSM_CAMCC_SDM845=y @@ -4258,118 +488,27 @@ CONFIG_MSM_CLK_RPMH=y CONFIG_CLOCK_CPU_OSM=y CONFIG_MSM_GPUCC_SDM845=y CONFIG_MSM_CLK_AOP_QMP=y -# CONFIG_MDM_GCC_SDXPOORWILLS is not set -# CONFIG_MDM_CLOCK_CPU_SDXPOORWILLS is not set -# CONFIG_MDM_DEBUGCC_SDXPOORWILLS is not set CONFIG_QCOM_MDSS_PLL=y -# CONFIG_COMMON_CLK_MSM is not set -# CONFIG_MSM_MDSS_PLL is not set -CONFIG_HWSPINLOCK=y - -# -# Hardware Spinlock drivers -# -# CONFIG_HWSPINLOCK_QCOM is not set CONFIG_REMOTE_SPINLOCK_MSM=y - -# -# Clock Source drivers -# -CONFIG_CLKSRC_OF=y -CONFIG_CLKSRC_PROBE=y -CONFIG_ARM_ARCH_TIMER=y -CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y -# CONFIG_ARM_ARCH_TIMER_VCT_ACCESS is not set -CONFIG_FSL_ERRATUM_A008585=y -# CONFIG_MSM_TIMER_LEAP is not set -# CONFIG_ARM_TIMER_SP804 is not set -# CONFIG_ATMEL_PIT is not set -# CONFIG_SH_TIMER_CMT is not set -# CONFIG_SH_TIMER_MTU2 is not set -# CONFIG_SH_TIMER_TMU is not set -# CONFIG_EM_TIMER_STI is not set -CONFIG_MAILBOX=y -# CONFIG_ARM_MHU is not set -# CONFIG_PLATFORM_MHU is not set -# CONFIG_PL320_MBOX is not set -# CONFIG_ALTERA_MBOX is not set -# CONFIG_MAILBOX_TEST is not set -# CONFIG_BCM_PDC_MBOX is not set -CONFIG_QTI_RPMH_MBOX=y CONFIG_MSM_QMP=y -CONFIG_IOMMU_API=y -CONFIG_IOMMU_SUPPORT=y - -# -# Generic IOMMU Pagetable Support -# -CONFIG_IOMMU_IO_PGTABLE=y -CONFIG_IOMMU_IO_PGTABLE_LPAE=y -# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set -# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set CONFIG_IOMMU_IO_PGTABLE_FAST=y -# CONFIG_IOMMU_IO_PGTABLE_FAST_SELFTEST is not set -# CONFIG_IOMMU_IO_PGTABLE_FAST_PROVE_TLB is not set -CONFIG_IOMMU_IOVA=y -CONFIG_OF_IOMMU=y -CONFIG_IOMMU_DMA=y CONFIG_ARM_SMMU=y -# CONFIG_ARM_SMMU_V3 is not set CONFIG_QCOM_LAZY_MAPPING=y -# CONFIG_IOMMU_DEBUG is not set - -# -# Remoteproc drivers -# -# CONFIG_STE_MODEM_RPROC is not set - -# -# Rpmsg drivers -# - -# -# SOC (System On Chip) specific Drivers -# - -# -# Broadcom SoC drivers -# -# CONFIG_QCOM_CPUSS_DUMP is not set CONFIG_QCOM_RUN_QUEUE_STATS=y -# CONFIG_QCOM_GSBI is not set CONFIG_QCOM_LLCC=y CONFIG_QCOM_SDM845_LLCC=y -# CONFIG_QCOM_SDM670_LLCC is not set -# CONFIG_QCOM_QCS605_LLCC is not set -# CONFIG_QCOM_LLCC_AMON is not set -# CONFIG_QCOM_LLCC_PERFMON is not set -# CONFIG_QCOM_SMEM is not set CONFIG_MSM_SERVICE_LOCATOR=y CONFIG_MSM_SERVICE_NOTIFIER=y -# CONFIG_MSM_SPM is not set -# CONFIG_MSM_L2_SPM is not set -CONFIG_QCOM_SCM=y -# CONFIG_SETUP_SSR_NOTIF_TIMEOUTS is not set CONFIG_MSM_BOOT_STATS=y -# CONFIG_MSM_CORE_HANG_DETECT is not set -# CONFIG_MSM_GLADIATOR_HANG_DETECT is not set -# CONFIG_MSM_GLADIATOR_ERP is not set CONFIG_QCOM_EUD=y CONFIG_QCOM_WATCHDOG_V2=y -# CONFIG_QCOM_WDOG_IPI_ENABLE is not set -# CONFIG_QPNP_PBS is not set CONFIG_QCOM_MEMORY_DUMP_V2=y -# CONFIG_MSM_DEBUG_LAR_UNLOCK is not set -# CONFIG_QCOM_MINIDUMP is not set -# CONFIG_MSM_RPM_SMD is not set CONFIG_QCOM_BUS_SCALING=y CONFIG_QCOM_BUS_CONFIG_RPMH=y CONFIG_QCOM_SECURE_BUFFER=y CONFIG_QCOM_EARLY_RANDOM=y CONFIG_MSM_SMEM=y -# CONFIG_MSM_SMD is not set CONFIG_MSM_GLINK=y -# CONFIG_MSM_TZ_SMMU is not set CONFIG_MSM_GLINK_LOOPBACK_SERVER=y CONFIG_MSM_GLINK_SMEM_NATIVE_XPRT=y CONFIG_MSM_GLINK_SPI_XPRT=y @@ -4377,1147 +516,140 @@ CONFIG_MSM_SPCOM=y CONFIG_MSM_SPSS_UTILS=y CONFIG_TRACER_PKT=y CONFIG_QTI_RPMH_API=y -CONFIG_QTI_SYSTEM_PM=y CONFIG_MSM_SMP2P=y CONFIG_MSM_IPC_ROUTER_GLINK_XPRT=y CONFIG_MSM_QMI_INTERFACE=y CONFIG_MSM_GLINK_PKT=y -# CONFIG_MSM_SYSTEM_HEALTH_MONITOR is not set CONFIG_MSM_SUBSYSTEM_RESTART=y CONFIG_MSM_PIL=y CONFIG_MSM_SYSMON_GLINK_COMM=y CONFIG_MSM_PIL_SSR_GENERIC=y CONFIG_MSM_PIL_MSS_QDSP6V5=y CONFIG_ICNSS=y -# CONFIG_ICNSS_DEBUG is not set CONFIG_QCOM_COMMAND_DB=y CONFIG_MSM_PERFORMANCE=y CONFIG_MSM_CDSP_LOADER=y CONFIG_QCOM_SMCINVOKE=y CONFIG_MSM_EVENT_TIMER=y -# CONFIG_MSM_AVTIMER is not set +CONFIG_MSM_AVTIMER=y CONFIG_MSM_PM=y -# CONFIG_MSM_PM_LEGACY is not set -# CONFIG_MSM_QBT1000 is not set -CONFIG_MSM_IDLE_STATS=y -CONFIG_MSM_IDLE_STATS_FIRST_BUCKET=62500 -CONFIG_MSM_IDLE_STATS_BUCKET_SHIFT=2 -CONFIG_MSM_IDLE_STATS_BUCKET_COUNT=10 -CONFIG_MSM_SUSPEND_STATS_FIRST_BUCKET=1000000000 -CONFIG_QCOM_DCC_V2=y -# CONFIG_QCOM_DCC is not set CONFIG_QTI_RPM_STATS_LOG=y CONFIG_QCOM_FORCE_WDOG_BITE_ON_PANIC=y CONFIG_QMP_DEBUGFS_CLIENT=y CONFIG_MEM_SHARE_QMI_SERVICE=y -# CONFIG_MSM_REMOTEQDSS is not set CONFIG_QSEE_IPC_IRQ_BRIDGE=y -# CONFIG_MSM_JTAGV8 is not set -# CONFIG_MSM_BAM_DMUX is not set -# CONFIG_MSM_BGRSB is not set -# CONFIG_MSM_PIL_SSR_BG is not set -# CONFIG_MSM_BGCOM is not set -# CONFIG_WCNSS_CORE is not set -# CONFIG_CNSS_CRYPTO is not set -# CONFIG_BIG_CLUSTER_MIN_FREQ_ADJUST is not set -# CONFIG_SUNXI_SRAM is not set -# CONFIG_SOC_TI is not set -CONFIG_PM_DEVFREQ=y - -# -# DEVFREQ Governors -# -CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y -CONFIG_DEVFREQ_GOV_PERFORMANCE=y -CONFIG_DEVFREQ_GOV_POWERSAVE=y -CONFIG_DEVFREQ_GOV_USERSPACE=y -# CONFIG_DEVFREQ_GOV_PASSIVE is not set -CONFIG_DEVFREQ_GOV_CPUFREQ=y CONFIG_QCOM_BIMC_BWMON=y CONFIG_ARM_MEMLAT_MON=y CONFIG_QCOMCCI_HWMON=y CONFIG_QCOM_M4M_HWMON=y CONFIG_DEVFREQ_GOV_QCOM_BW_HWMON=y CONFIG_DEVFREQ_GOV_QCOM_CACHE_HWMON=y -# CONFIG_DEVFREQ_GOV_SPDM_HYP is not set CONFIG_DEVFREQ_GOV_MEMLAT=y - -# -# DEVFREQ Drivers -# -CONFIG_DEVFREQ_GOV_QCOM_ADRENO_TZ=y -CONFIG_DEVFREQ_GOV_QCOM_GPUBW_MON=y CONFIG_DEVFREQ_SIMPLE_DEV=y CONFIG_QCOM_DEVFREQ_DEVBW=y -# CONFIG_DEVFREQ_SPDM is not set -CONFIG_DEVFREQ_BOOST=y -CONFIG_DEVFREQ_INPUT_BOOST_DURATION_MS=100 -CONFIG_DEVFREQ_WAKE_BOOST_DURATION_MS=1000 -CONFIG_DEVFREQ_MSM_CPUBW_BOOST_FREQ=4577 -# CONFIG_PM_DEVFREQ_EVENT is not set -CONFIG_EXTCON=y - -# -# Extcon Device Drivers -# -# CONFIG_EXTCON_ADC_JACK is not set -CONFIG_EXTCON_GPIO=y -# CONFIG_EXTCON_MAX3355 is not set -# CONFIG_EXTCON_QCOM_SPMI_MISC is not set -# CONFIG_EXTCON_RT8973A is not set -# CONFIG_EXTCON_SM5502 is not set CONFIG_EXTCON_USB_GPIO=y -# CONFIG_MEMORY is not set CONFIG_IIO=y -# CONFIG_IIO_BUFFER is not set -# CONFIG_IIO_CONFIGFS is not set -# CONFIG_IIO_TRIGGER is not set -# CONFIG_IIO_SW_DEVICE is not set -# CONFIG_IIO_SW_TRIGGER is not set - -# -# Accelerometers -# -# CONFIG_BMA180 is not set -# CONFIG_BMA220 is not set -# CONFIG_BMC150_ACCEL is not set -# CONFIG_DMARD06 is not set -# CONFIG_DMARD09 is not set -# CONFIG_IIO_ST_ACCEL_3AXIS is not set -# CONFIG_KXSD9 is not set -# CONFIG_KXCJK1013 is not set -# CONFIG_MC3230 is not set -# CONFIG_MMA7455_I2C is not set -# CONFIG_MMA7455_SPI is not set -# CONFIG_MMA7660 is not set -# CONFIG_MMA8452 is not set -# CONFIG_MMA9551 is not set -# CONFIG_MMA9553 is not set -# CONFIG_MXC4005 is not set -# CONFIG_MXC6255 is not set -# CONFIG_STK8312 is not set -# CONFIG_STK8BA50 is not set - -# -# Analog to digital converters -# -# CONFIG_AD7266 is not set -# CONFIG_AD7291 is not set -# CONFIG_AD7298 is not set -# CONFIG_AD7476 is not set -# CONFIG_AD7791 is not set -# CONFIG_AD7793 is not set -# CONFIG_AD7887 is not set -# CONFIG_AD7923 is not set -# CONFIG_AD799X is not set -# CONFIG_CC10001_ADC is not set -# CONFIG_HI8435 is not set -# CONFIG_INA2XX_ADC is not set -# CONFIG_LTC2485 is not set -# CONFIG_MAX1027 is not set -# CONFIG_MAX1363 is not set -# CONFIG_MCP320X is not set -# CONFIG_MCP3422 is not set -# CONFIG_NAU7802 is not set -# CONFIG_QCOM_SPMI_IADC is not set -# CONFIG_QCOM_SPMI_VADC is not set -# CONFIG_QCOM_TADC is not set CONFIG_QCOM_RRADC=y -# CONFIG_TI_ADC081C is not set -# CONFIG_TI_ADC0832 is not set -# CONFIG_TI_ADC12138 is not set -# CONFIG_TI_ADC128S052 is not set -# CONFIG_TI_ADC161S626 is not set -# CONFIG_TI_ADS1015 is not set -# CONFIG_TI_ADS8688 is not set -# CONFIG_VF610_ADC is not set - -# -# Amplifiers -# -# CONFIG_AD8366 is not set - -# -# Chemical Sensors -# -# CONFIG_ATLAS_PH_SENSOR is not set -# CONFIG_IAQCORE is not set -# CONFIG_VZ89X is not set - -# -# Hid Sensor IIO Common -# - -# -# SSP Sensor Common -# -# CONFIG_IIO_SSP_SENSORHUB is not set - -# -# Digital to analog converters -# -# CONFIG_AD5064 is not set -# CONFIG_AD5360 is not set -# CONFIG_AD5380 is not set -# CONFIG_AD5421 is not set -# CONFIG_AD5446 is not set -# CONFIG_AD5449 is not set -# CONFIG_AD5592R is not set -# CONFIG_AD5593R is not set -# CONFIG_AD5504 is not set -# CONFIG_AD5624R_SPI is not set -# CONFIG_AD5686 is not set -# CONFIG_AD5755 is not set -# CONFIG_AD5761 is not set -# CONFIG_AD5764 is not set -# CONFIG_AD5791 is not set -# CONFIG_AD7303 is not set -# CONFIG_AD8801 is not set -# CONFIG_M62332 is not set -# CONFIG_MAX517 is not set -# CONFIG_MAX5821 is not set -# CONFIG_MCP4725 is not set -# CONFIG_MCP4922 is not set -# CONFIG_VF610_DAC is not set - -# -# IIO dummy driver -# - -# -# Frequency Synthesizers DDS/PLL -# - -# -# Clock Generator/Distribution -# -# CONFIG_AD9523 is not set - -# -# Phase-Locked Loop (PLL) frequency synthesizers -# -# CONFIG_ADF4350 is not set - -# -# Digital gyroscope sensors -# -# CONFIG_ADIS16080 is not set -# CONFIG_ADIS16130 is not set -# CONFIG_ADIS16136 is not set -# CONFIG_ADIS16260 is not set -# CONFIG_ADXRS450 is not set -# CONFIG_BMG160 is not set -# CONFIG_IIO_ST_GYRO_3AXIS is not set -# CONFIG_ITG3200 is not set - -# -# Health Sensors -# - -# -# Heart Rate Monitors -# -# CONFIG_AFE4403 is not set -# CONFIG_AFE4404 is not set -# CONFIG_MAX30100 is not set - -# -# Humidity sensors -# -# CONFIG_AM2315 is not set -# CONFIG_DHT11 is not set -# CONFIG_HDC100X is not set -# CONFIG_HTU21 is not set -# CONFIG_SI7005 is not set -# CONFIG_SI7020 is not set - -# -# Inertial measurement units -# -# CONFIG_ADIS16400 is not set -# CONFIG_ADIS16480 is not set -# CONFIG_BMI160_I2C is not set -# CONFIG_BMI160_SPI is not set -# CONFIG_KMX61 is not set -# CONFIG_INV_MPU6050_I2C is not set -# CONFIG_INV_MPU6050_SPI is not set -# CONFIG_INV_ICM20602_IIO is not set - -# -# Light sensors -# -# CONFIG_ADJD_S311 is not set -# CONFIG_AL3320A is not set -# CONFIG_APDS9300 is not set -# CONFIG_APDS9960 is not set -# CONFIG_BH1750 is not set -# CONFIG_BH1780 is not set -# CONFIG_CM32181 is not set -# CONFIG_CM3232 is not set -# CONFIG_CM3323 is not set -# CONFIG_CM36651 is not set -# CONFIG_GP2AP020A00F is not set -# CONFIG_ISL29125 is not set -# CONFIG_JSA1212 is not set -# CONFIG_RPR0521 is not set -# CONFIG_LTR501 is not set -# CONFIG_MAX44000 is not set -# CONFIG_OPT3001 is not set -# CONFIG_PA12203001 is not set -# CONFIG_SI1145 is not set -# CONFIG_STK3310 is not set -# CONFIG_TCS3414 is not set -# CONFIG_TCS3472 is not set -# CONFIG_SENSORS_TSL2563 is not set -# CONFIG_TSL4531 is not set -# CONFIG_US5182D is not set -# CONFIG_VCNL4000 is not set -# CONFIG_VEML6070 is not set - -# -# Magnetometer sensors -# -# CONFIG_AK8974 is not set -# CONFIG_AK8975 is not set -# CONFIG_AK09911 is not set -# CONFIG_BMC150_MAGN_I2C is not set -# CONFIG_BMC150_MAGN_SPI is not set -# CONFIG_MAG3110 is not set -# CONFIG_MMC35240 is not set -# CONFIG_IIO_ST_MAGN_3AXIS is not set -# CONFIG_SENSORS_HMC5843_I2C is not set -# CONFIG_SENSORS_HMC5843_SPI is not set - -# -# Inclinometer sensors -# - -# -# Digital potentiometers -# -# CONFIG_DS1803 is not set -# CONFIG_MAX5487 is not set -# CONFIG_MCP4131 is not set -# CONFIG_MCP4531 is not set -# CONFIG_TPL0102 is not set - -# -# Pressure sensors -# -# CONFIG_BMP280 is not set -# CONFIG_HP03 is not set -# CONFIG_MPL115_I2C is not set -# CONFIG_MPL115_SPI is not set -# CONFIG_MPL3115 is not set -# CONFIG_MS5611 is not set -# CONFIG_MS5637 is not set -# CONFIG_IIO_ST_PRESS is not set -# CONFIG_T5403 is not set -# CONFIG_HP206C is not set -# CONFIG_ZPA2326 is not set - -# -# Lightning sensors -# -# CONFIG_AS3935 is not set - -# -# Proximity sensors -# -# CONFIG_LIDAR_LITE_V2 is not set -# CONFIG_SX9500 is not set - -# -# Temperature sensors -# -# CONFIG_MAXIM_THERMOCOUPLE is not set -# CONFIG_MLX90614 is not set -# CONFIG_TMP006 is not set -# CONFIG_TSYS01 is not set -# CONFIG_TSYS02D is not set -# CONFIG_NTB is not set -# CONFIG_VME_BUS is not set CONFIG_PWM=y -CONFIG_PWM_SYSFS=y -# CONFIG_PWM_FSL_FTM is not set -# CONFIG_PWM_PCA9685 is not set CONFIG_PWM_QPNP=y -# CONFIG_PWM_QTI_LPG is not set -CONFIG_IRQCHIP=y -CONFIG_ARM_GIC=y -CONFIG_ARM_GIC_MAX_NR=1 -CONFIG_ARM_GIC_V2M=y -CONFIG_ARM_GIC_V3=y -CONFIG_ARM_GIC_V3_ITS=y CONFIG_ARM_GIC_V3_ACL=y -CONFIG_QCOM_SHOW_RESUME_IRQ=y -CONFIG_PARTITION_PERCPU=y -CONFIG_QTI_PDC=y -CONFIG_QTI_PDC_SDM845=y -# CONFIG_QTI_PDC_SDM670 is not set -# CONFIG_QTI_PDC_SDXPOORWILLS is not set -# CONFIG_QTI_MPM is not set -# CONFIG_IPACK_BUS is not set -CONFIG_RESET_CONTROLLER=y -# CONFIG_RESET_ATH79 is not set -# CONFIG_RESET_BERLIN is not set -# CONFIG_RESET_LPC18XX is not set -# CONFIG_RESET_MESON is not set -# CONFIG_RESET_PISTACHIO is not set -# CONFIG_RESET_SOCFPGA is not set -# CONFIG_RESET_STM32 is not set -# CONFIG_RESET_SUNXI is not set -# CONFIG_TI_SYSCON_RESET is not set -# CONFIG_RESET_ZYNQ is not set -# CONFIG_FMC is not set - -# -# PHY Subsystem -# -CONFIG_GENERIC_PHY=y -# CONFIG_PHY_PXA_28NM_HSIC is not set -# CONFIG_PHY_PXA_28NM_USB2 is not set -# CONFIG_BCM_KONA_USB2_PHY is not set -# CONFIG_PHY_QCOM_APQ8064_SATA is not set -# CONFIG_PHY_QCOM_IPQ806X_SATA is not set -# CONFIG_PHY_XGENE is not set -CONFIG_PHY_QCOM_UFS=y -# CONFIG_POWERCAP is not set -# CONFIG_MCB is not set - -# -# Performance monitor support -# -CONFIG_ARM_PMU=y -# CONFIG_RAS is not set -# CONFIG_THUNDERBOLT is not set - -# -# Android -# CONFIG_ANDROID=y CONFIG_ANDROID_BINDER_IPC=y -CONFIG_ANDROID_BINDER_DEVICES="binder,hwbinder,vndbinder" -# CONFIG_ANDROID_BINDER_IPC_SELFTEST is not set -# CONFIG_LIBNVDIMM is not set -# CONFIG_NVMEM is not set -CONFIG_STM=y -# CONFIG_STM_DUMMY is not set -# CONFIG_STM_SOURCE_CONSOLE is not set -# CONFIG_STM_SOURCE_HEARTBEAT is not set -# CONFIG_INTEL_TH is not set - -# -# FPGA Configuration Support -# -# CONFIG_FPGA is not set CONFIG_SENSORS_SSC=y -# CONFIG_TEE is not set -# CONFIG_BCM_GPS_SPI_DRIVER is not set - -# -# Halls -# -# CONFIG_HALLS is not set - -# -# Firmware Drivers -# -CONFIG_ARM_PSCI_FW=y -# CONFIG_ARM_SCPI_PROTOCOL is not set -# CONFIG_FIRMWARE_MEMMAP is not set -# CONFIG_FW_CFG_SYSFS is not set -CONFIG_QCOM_SCM_64=y -CONFIG_HAVE_ARM_SMCCC=y -# CONFIG_MESON_SM is not set CONFIG_MSM_TZ_LOG=y -# CONFIG_ACPI is not set - -# -# File systems -# -CONFIG_DCACHE_WORD_ACCESS=y -# CONFIG_EXT2_FS is not set -# CONFIG_EXT3_FS is not set CONFIG_EXT4_FS=y -CONFIG_EXT4_USE_FOR_EXT2=y -# CONFIG_EXT4_FS_POSIX_ACL is not set CONFIG_EXT4_FS_SECURITY=y CONFIG_EXT4_ENCRYPTION=y CONFIG_EXT4_FS_ENCRYPTION=y CONFIG_EXT4_FS_ICE_ENCRYPTION=y -# CONFIG_EXT4_DEBUG is not set -CONFIG_JBD2=y -# CONFIG_JBD2_DEBUG is not set -CONFIG_FS_MBCACHE=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set -# CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -# CONFIG_NILFS2_FS is not set CONFIG_F2FS_FS=y -CONFIG_F2FS_STAT_FS=y -CONFIG_F2FS_FS_XATTR=y -CONFIG_F2FS_FS_POSIX_ACL=y CONFIG_F2FS_FS_SECURITY=y -# CONFIG_F2FS_CHECK_FS is not set CONFIG_F2FS_FS_ENCRYPTION=y -# CONFIG_F2FS_FAULT_INJECTION is not set -# CONFIG_FS_DAX is not set -CONFIG_FS_POSIX_ACL=y -# CONFIG_EXPORTFS_BLOCK_OPS is not set -CONFIG_FILE_LOCKING=y -CONFIG_MANDATORY_FILE_LOCKING=y -CONFIG_FS_ENCRYPTION=y -CONFIG_FSNOTIFY=y -CONFIG_DNOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_FANOTIFY is not set CONFIG_QUOTA=y CONFIG_QUOTA_NETLINK_INTERFACE=y -CONFIG_PRINT_QUOTA_WARNING=y -# CONFIG_QUOTA_DEBUG is not set -CONFIG_QUOTA_TREE=y -# CONFIG_QFMT_V1 is not set CONFIG_QFMT_V2=y -CONFIG_QUOTACTL=y -# CONFIG_AUTOFS4_FS is not set CONFIG_FUSE_FS=y -# CONFIG_CUSE is not set -# CONFIG_OVERLAY_FS is not set - -# -# Caches -# -# CONFIG_FSCACHE is not set - -# -# CD-ROM/DVD Filesystems -# -# CONFIG_ISO9660_FS is not set -# CONFIG_UDF_FS is not set - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=y +CONFIG_OVERLAY_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 CONFIG_FAT_DEFAULT_IOCHARSET="utf8" -# CONFIG_FAT_DEFAULT_UTF8 is not set -CONFIG_SDFAT_FS=y -CONFIG_SDFAT_USE_FOR_EXFAT=y -CONFIG_SDFAT_DELAYED_META_DIRTY=y CONFIG_SDFAT_SUPPORT_DIR_SYNC=y -CONFIG_SDFAT_DEFAULT_CODEPAGE=437 -CONFIG_SDFAT_DEFAULT_IOCHARSET="utf8" CONFIG_SDFAT_CHECK_RO_ATTR=y -CONFIG_SDFAT_ALIGNED_MPAGE_WRITE=y -CONFIG_SDFAT_VIRTUAL_XATTR=y -CONFIG_SDFAT_VIRTUAL_XATTR_SELINUX_LABEL="u:object_r:sdcard_external:s0" # CONFIG_SDFAT_DEBUG is not set -CONFIG_SDFAT_STATISTICS=y -CONFIG_NTFS_FS=y -# CONFIG_NTFS_DEBUG is not set -CONFIG_NTFS_RW=y - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -# CONFIG_PROC_KCORE is not set -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -# CONFIG_PROC_CHILDREN is not set -CONFIG_PROC_UID=y -CONFIG_KERNFS=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y -CONFIG_TMPFS_XATTR=y -# CONFIG_HUGETLBFS is not set -# CONFIG_HUGETLB_PAGE is not set -CONFIG_ARCH_HAS_GIGANTIC_PAGE=y -CONFIG_CONFIGFS_FS=y -CONFIG_MISC_FILESYSTEMS=y -# CONFIG_ORANGEFS_FS is not set -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set CONFIG_ECRYPT_FS=y CONFIG_ECRYPT_FS_MESSAGING=y CONFIG_SDCARD_FS=y -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_LOGFS is not set -# CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_QNX6FS_FS is not set -# CONFIG_ROMFS_FS is not set CONFIG_PSTORE=y -CONFIG_PSTORE_ZLIB_COMPRESS=y -# CONFIG_PSTORE_LZO_COMPRESS is not set -# CONFIG_PSTORE_LZ4_COMPRESS is not set CONFIG_PSTORE_CONSOLE=y CONFIG_PSTORE_PMSG=y CONFIG_PSTORE_RAM=y -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y -# CONFIG_NFS_FS is not set -# CONFIG_NFSD is not set -# CONFIG_CEPH_FS is not set CONFIG_CIFS=y -# CONFIG_CIFS_STATS is not set -# CONFIG_CIFS_WEAK_PW_HASH is not set -# CONFIG_CIFS_UPCALL is not set -# CONFIG_CIFS_XATTR is not set -# CONFIG_CIFS_DEBUG is not set -# CONFIG_CIFS_DFS_UPCALL is not set -# CONFIG_CIFS_SMB2 is not set -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set CONFIG_NLS_CODEPAGE_936=y CONFIG_NLS_CODEPAGE_950=y -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_MAC_ROMAN is not set -# CONFIG_NLS_MAC_CELTIC is not set -# CONFIG_NLS_MAC_CENTEURO is not set -# CONFIG_NLS_MAC_CROATIAN is not set -# CONFIG_NLS_MAC_CYRILLIC is not set -# CONFIG_NLS_MAC_GAELIC is not set -# CONFIG_NLS_MAC_GREEK is not set -# CONFIG_NLS_MAC_ICELAND is not set -# CONFIG_NLS_MAC_INUIT is not set -# CONFIG_NLS_MAC_ROMANIAN is not set -# CONFIG_NLS_MAC_TURKISH is not set -CONFIG_NLS_UTF8=y -# CONFIG_DLM is not set -# CONFIG_VIRTUALIZATION is not set - -# -# Kernel hacking -# - -# -# printk and dmesg options -# CONFIG_PRINTK_TIME=y -CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 -# CONFIG_BOOT_PRINTK_DELAY is not set -CONFIG_DYNAMIC_DEBUG=y -# CONFIG_DEBUG_MODULE_LOAD_INFO is not set - -# -# Compile-time checks and compiler options -# -# CONFIG_DEBUG_INFO is not set -CONFIG_ENABLE_WARN_DEPRECATED=y -CONFIG_ENABLE_MUST_CHECK=y -CONFIG_FRAME_WARN=2048 -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_READABLE_ASM is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_PAGE_OWNER is not set -CONFIG_DEBUG_FS=y -# CONFIG_HEADERS_CHECK is not set -# CONFIG_DEBUG_SECTION_MISMATCH is not set -CONFIG_SECTION_MISMATCH_WARN_ONLY=y -CONFIG_ARCH_WANT_FRAME_POINTERS=y -CONFIG_FRAME_POINTER=y -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +CONFIG_DEBUG_INFO=y CONFIG_MAGIC_SYSRQ=y -CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 -CONFIG_DEBUG_KERNEL=y - -# -# Memory Debugging -# -# CONFIG_PAGE_EXTENSION is not set -# CONFIG_DEBUG_PAGEALLOC is not set -# CONFIG_PAGE_POISONING is not set -# CONFIG_DEBUG_PAGE_REF is not set -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_SLUB_STATS is not set -CONFIG_HAVE_DEBUG_KMEMLEAK=y -# CONFIG_DEBUG_KMEMLEAK is not set -# CONFIG_DEBUG_STACK_USAGE is not set -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_PER_CPU_MAPS is not set -CONFIG_HAVE_ARCH_KASAN=y -# CONFIG_KASAN is not set -# CONFIG_DEBUG_REFCOUNT is not set -CONFIG_ARCH_HAS_KCOV=y -# CONFIG_KCOV is not set -# CONFIG_DEBUG_SHIRQ is not set - -# -# Debug Lockups and Hangs -# -# CONFIG_LOCKUP_DETECTOR is not set -# CONFIG_PANIC_ON_RECURSIVE_FAULT is not set -# CONFIG_DETECT_HUNG_TASK is not set -# CONFIG_WQ_WATCHDOG is not set -# CONFIG_PANIC_ON_OOPS is not set -CONFIG_PANIC_ON_OOPS_VALUE=0 CONFIG_PANIC_TIMEOUT=1 -# CONFIG_SCHED_DEBUG is not set -# CONFIG_SCHED_INFO is not set -# CONFIG_PANIC_ON_SCHED_BUG is not set -# CONFIG_PANIC_ON_RT_THROTTLING is not set -# CONFIG_SCHEDSTATS is not set -# CONFIG_SCHED_STACK_END_CHECK is not set -# CONFIG_DEBUG_TIMEKEEPING is not set +CONFIG_SCHEDSTATS=y # CONFIG_DEBUG_PREEMPT is not set - -# -# Lock Debugging (spinlocks, mutexes, etc...) -# -# CONFIG_DEBUG_RT_MUTEXES is not set -# CONFIG_DEBUG_SPINLOCK is not set -# CONFIG_DEBUG_MUTEXES is not set -# CONFIG_DEBUG_WW_MUTEX_SLOWPATH is not set -# CONFIG_DEBUG_LOCK_ALLOC is not set -# CONFIG_PROVE_LOCKING is not set -# CONFIG_LOCK_STAT is not set -# CONFIG_DEBUG_ATOMIC_SLEEP is not set -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_LOCK_TORTURE_TEST is not set -CONFIG_STACKTRACE=y -# CONFIG_DEBUG_KOBJECT is not set -CONFIG_HAVE_DEBUG_BUGVERBOSE=y -CONFIG_DEBUG_BUGVERBOSE=y -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_PI_LIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_DEBUG_CREDENTIALS is not set - -# -# RCU Debugging -# -# CONFIG_PROVE_RCU is not set -# CONFIG_SPARSE_RCU_POINTER is not set -# CONFIG_TORTURE_TEST is not set -# CONFIG_RCU_PERF_TEST is not set -# CONFIG_RCU_TORTURE_TEST is not set -CONFIG_RCU_CPU_STALL_TIMEOUT=21 -CONFIG_RCU_PANIC_ON_STALL=0 -# CONFIG_RCU_TRACE is not set -# CONFIG_RCU_EQS_DEBUG is not set -# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set -# CONFIG_NOTIFIER_ERROR_INJECTION is not set -# CONFIG_FAULT_INJECTION is not set -# CONFIG_LATENCYTOP is not set -CONFIG_NOP_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_TRACE_CLOCK=y -CONFIG_RING_BUFFER=y -CONFIG_EVENT_TRACING=y -CONFIG_CONTEXT_SWITCH_TRACER=y -# CONFIG_IPC_LOGGING is not set -# CONFIG_QCOM_RTB is not set -CONFIG_TRACING=y -CONFIG_GENERIC_TRACER=y -CONFIG_TRACING_SUPPORT=y -CONFIG_FTRACE=y -# CONFIG_FUNCTION_TRACER is not set -# CONFIG_PREEMPTIRQ_EVENTS is not set -# CONFIG_IRQSOFF_TRACER is not set -# CONFIG_PREEMPT_TRACER is not set -# CONFIG_SCHED_TRACER is not set -# CONFIG_HWLAT_TRACER is not set -# CONFIG_FTRACE_SYSCALLS is not set -# CONFIG_TRACER_SNAPSHOT is not set -CONFIG_BRANCH_PROFILE_NONE=y -# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -# CONFIG_PROFILE_ALL_BRANCHES is not set -# CONFIG_STACK_TRACER is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_PROBE_EVENTS is not set +CONFIG_IPC_LOGGING=y CONFIG_CPU_FREQ_SWITCH_PROFILER=y -# CONFIG_FTRACE_STARTUP_TEST is not set -# CONFIG_TRACEPOINT_BENCHMARK is not set -# CONFIG_RING_BUFFER_BENCHMARK is not set -# CONFIG_RING_BUFFER_STARTUP_TEST is not set -# CONFIG_TRACE_ENUM_MAP_FILE is not set -CONFIG_TRACING_EVENTS_GPIO=y - -# -# Runtime Testing -# -# CONFIG_LKDTM is not set -# CONFIG_TEST_LIST_SORT is not set -# CONFIG_BACKTRACE_SELF_TEST is not set -# CONFIG_RBTREE_TEST is not set -# CONFIG_ATOMIC64_SELFTEST is not set -# CONFIG_TEST_HEXDUMP is not set -# CONFIG_TEST_STRING_HELPERS is not set -# CONFIG_TEST_KSTRTOX is not set -# CONFIG_TEST_PRINTF is not set -# CONFIG_TEST_BITMAP is not set -# CONFIG_TEST_UUID is not set -# CONFIG_TEST_RHASHTABLE is not set -# CONFIG_TEST_HASH is not set -# CONFIG_DMA_API_DEBUG is not set -# CONFIG_TEST_FIRMWARE is not set -# CONFIG_TEST_UDELAY is not set -# CONFIG_MEMTEST is not set -# CONFIG_PANIC_ON_DATA_CORRUPTION is not set -# CONFIG_CC_WERROR is not set -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -# CONFIG_KGDB is not set -CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y -# CONFIG_ARCH_WANTS_UBSAN_NO_NULL is not set -# CONFIG_UBSAN is not set -CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y -# CONFIG_STRICT_DEVMEM is not set -# CONFIG_ARM64_PTDUMP is not set -# CONFIG_PID_IN_CONTEXTIDR is not set -# CONFIG_ARM64_RANDOMIZE_TEXT_OFFSET is not set +CONFIG_CC_WERROR=y CONFIG_DEBUG_ALIGN_RODATA=y -# CONFIG_ARM64_STRICT_BREAK_BEFORE_MAKE is not set -# CONFIG_CORESIGHT is not set - -# -# Security options -# -CONFIG_KEYS=y -# CONFIG_PERSISTENT_KEYRINGS is not set -# CONFIG_BIG_KEYS is not set -# CONFIG_ENCRYPTED_KEYS is not set -# CONFIG_KEY_DH_OPERATIONS is not set - -# -# Qualcomm Technologies, Inc Per File Encryption security device drivers -# -# CONFIG_PFT is not set CONFIG_PFK=y -# CONFIG_SECURITY_DMESG_RESTRICT is not set CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y CONFIG_SECURITY=y -# CONFIG_SECURITY_WRITABLE_HOOKS is not set -# CONFIG_SECURITYFS is not set -CONFIG_SECURITY_NETWORK=y -# CONFIG_SECURITY_NETWORK_XFRM is not set -# CONFIG_SECURITY_PATH is not set -CONFIG_LSM_MMAP_MIN_ADDR=32768 -CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y -CONFIG_HAVE_ARCH_HARDENED_USERCOPY=y CONFIG_HARDENED_USERCOPY=y -# CONFIG_HARDENED_USERCOPY_PAGESPAN is not set CONFIG_FORTIFY_SOURCE=y CONFIG_SECURITY_SELINUX=y -# CONFIG_SECURITY_SELINUX_BOOTPARAM is not set -# CONFIG_SECURITY_SELINUX_DISABLE is not set -CONFIG_SECURITY_SELINUX_DEVELOP=y -CONFIG_SECURITY_SELINUX_AVC_STATS=y -CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=0 CONFIG_SECURITY_SMACK=y -# CONFIG_SECURITY_SMACK_BRINGUP is not set -# CONFIG_SECURITY_SMACK_NETFILTER is not set -# CONFIG_SECURITY_SMACK_APPEND_SIGNALS is not set -# CONFIG_SECURITY_TOMOYO is not set -# CONFIG_SECURITY_APPARMOR is not set -# CONFIG_SECURITY_LOADPIN is not set -# CONFIG_SECURITY_YAMA is not set -CONFIG_INTEGRITY=y -# CONFIG_INTEGRITY_SIGNATURE is not set -# CONFIG_IMA is not set -# CONFIG_EVM is not set -CONFIG_DEFAULT_SECURITY_SELINUX=y -# CONFIG_DEFAULT_SECURITY_SMACK is not set -# CONFIG_DEFAULT_SECURITY_DAC is not set -CONFIG_DEFAULT_SECURITY="selinux" -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_AEAD=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_AKCIPHER2=y -CONFIG_CRYPTO_KPP2=y -CONFIG_CRYPTO_ACOMP2=y -# CONFIG_CRYPTO_RSA is not set -# CONFIG_CRYPTO_DH is not set -# CONFIG_CRYPTO_ECDH is not set -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -# CONFIG_CRYPTO_USER is not set -CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y -CONFIG_CRYPTO_GF128MUL=y -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_NULL2=y -# CONFIG_CRYPTO_PCRYPT is not set -CONFIG_CRYPTO_WORKQUEUE=y -CONFIG_CRYPTO_CRYPTD=y -# CONFIG_CRYPTO_MCRYPTD is not set -CONFIG_CRYPTO_AUTHENC=y -CONFIG_CRYPTO_ABLK_HELPER=y - -# -# Authenticated Encryption with Associated Data -# -# CONFIG_CRYPTO_CCM is not set CONFIG_CRYPTO_GCM=y -# CONFIG_CRYPTO_CHACHA20POLY1305 is not set -CONFIG_CRYPTO_SEQIV=y -CONFIG_CRYPTO_ECHAINIV=y - -# -# Block modes -# -CONFIG_CRYPTO_CBC=y -CONFIG_CRYPTO_CTR=y -CONFIG_CRYPTO_CTS=y -CONFIG_CRYPTO_ECB=y -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_PCBC is not set -CONFIG_CRYPTO_XTS=y -# CONFIG_CRYPTO_KEYWRAP is not set - -# -# Hash modes -# -CONFIG_CRYPTO_CMAC=y -CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_XCBC=y -# CONFIG_CRYPTO_VMAC is not set - -# -# Digest -# -CONFIG_CRYPTO_CRC32C=y -CONFIG_CRYPTO_CRC32=y -# CONFIG_CRYPTO_CRCT10DIF is not set -CONFIG_CRYPTO_GHASH=y -# CONFIG_CRYPTO_POLY1305 is not set -CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_MD5=y -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set -# CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y -# CONFIG_CRYPTO_SHA3 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_WP512 is not set - -# -# Ciphers -# -CONFIG_CRYPTO_AES=y -# CONFIG_CRYPTO_ANUBIS is not set -CONFIG_CRYPTO_ARC4=y -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -CONFIG_CRYPTO_DES=y -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set -# CONFIG_CRYPTO_SALSA20 is not set -# CONFIG_CRYPTO_CHACHA20 is not set -# CONFIG_CRYPTO_SEED is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_SPECK is not set -# CONFIG_CRYPTO_TEA is not set CONFIG_CRYPTO_TWOFISH=y -CONFIG_CRYPTO_TWOFISH_COMMON=y - -# -# Compression -# -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_LZO=y -# CONFIG_CRYPTO_842 is not set -CONFIG_CRYPTO_LZ4=y -# CONFIG_CRYPTO_LZ4HC is not set - -# -# Random Number Generation -# CONFIG_CRYPTO_ANSI_CPRNG=y -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_DRBG_HMAC=y -CONFIG_CRYPTO_DRBG_HASH=y -CONFIG_CRYPTO_DRBG_CTR=y -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_JITTERENTROPY=y -# CONFIG_CRYPTO_USER_API_HASH is not set -# CONFIG_CRYPTO_USER_API_SKCIPHER is not set -# CONFIG_CRYPTO_USER_API_RNG is not set -# CONFIG_CRYPTO_USER_API_AEAD is not set -CONFIG_CRYPTO_HW=y -# CONFIG_CRYPTO_DEV_CCP is not set -# CONFIG_CRYPTO_DEV_QCE is not set CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y CONFIG_CRYPTO_DEV_QCRYPTO=y CONFIG_CRYPTO_DEV_QCEDEV=y -# CONFIG_CRYPTO_DEV_OTA_CRYPTO is not set CONFIG_CRYPTO_DEV_QCOM_ICE=y -# CONFIG_ASYMMETRIC_KEY_TYPE is not set - -# -# Certificates for signature checking -# CONFIG_ARM64_CRYPTO=y CONFIG_CRYPTO_SHA1_ARM64_CE=y CONFIG_CRYPTO_SHA2_ARM64_CE=y CONFIG_CRYPTO_GHASH_ARM64_CE=y -CONFIG_CRYPTO_AES_ARM64_CE=y CONFIG_CRYPTO_AES_ARM64_CE_CCM=y CONFIG_CRYPTO_AES_ARM64_CE_BLK=y CONFIG_CRYPTO_AES_ARM64_NEON_BLK=y CONFIG_CRYPTO_CRC32_ARM64=y -# CONFIG_CRYPTO_SPECK_NEON is not set -CONFIG_BINARY_PRINTF=y - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_HAVE_ARCH_BITREVERSE=y -CONFIG_RATIONAL=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_NET_UTILS=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_IO=y -CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y -CONFIG_CRC_CCITT=y -CONFIG_CRC16=y -# CONFIG_CRC_T10DIF is not set -# CONFIG_CRC_ITU_T is not set -CONFIG_CRC32=y -# CONFIG_CRC32_SELFTEST is not set -CONFIG_CRC32_SLICEBY8=y -# CONFIG_CRC32_SLICEBY4 is not set -# CONFIG_CRC32_SARWATE is not set -# CONFIG_CRC32_BIT is not set -# CONFIG_CRC7 is not set -CONFIG_LIBCRC32C=y -# CONFIG_CRC8 is not set -CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y -# CONFIG_RANDOM32_SELFTEST is not set -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_LZ4_COMPRESS=y -CONFIG_LZ4_DECOMPRESS=y -# CONFIG_XZ_DEC is not set -# CONFIG_XZ_DEC_BCJ is not set -CONFIG_DECOMPRESS_GZIP=y -CONFIG_DECOMPRESS_BZIP2=y -CONFIG_DECOMPRESS_LZMA=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_REED_SOLOMON=y -CONFIG_REED_SOLOMON_ENC8=y -CONFIG_REED_SOLOMON_DEC8=y -CONFIG_TEXTSEARCH=y -CONFIG_TEXTSEARCH_KMP=y -CONFIG_TEXTSEARCH_BM=y -CONFIG_TEXTSEARCH_FSM=y -CONFIG_ASSOCIATIVE_ARRAY=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAS_DMA=y -CONFIG_CPU_RMAP=y -CONFIG_DQL=y -CONFIG_NLATTR=y -# CONFIG_CORDIC is not set -# CONFIG_DDR is not set -# CONFIG_IRQ_POLL is not set -CONFIG_LIBFDT=y -# CONFIG_SG_SPLIT is not set -CONFIG_SG_POOL=y -CONFIG_ARCH_HAS_SG_CHAIN=y -CONFIG_SBITMAP=y CONFIG_QMI_ENCDEC=y -# CONFIG_QMI_ENCDEC_DEBUG is not set - -# -# Xiaomi configuration options -# -CONFIG_MACH_XIAOMI=y -CONFIG_MACH_XIAOMI_SDM845=y - -# -# Xiaomi board selection -# -# CONFIG_MACH_XIAOMI_D5X is not set -# CONFIG_MACH_XIAOMI_E1N is not set +CONFIG_MSM_ADSP_LOADER=y +CONFIG_MSM_QDSP6_APRV2_GLINK=y +CONFIG_MSM_QDSP6_NOTIFIER=y +CONFIG_MSM_QDSP6_PDR=y +CONFIG_MSM_QDSP6_SSR=y +CONFIG_MSM_QDSP6V2_CODECS=y +CONFIG_PINCTRL_WCD=y +CONFIG_QTI_PP=y +CONFIG_SND_HWDEP_ROUTING=y +CONFIG_SND_SOC_MACHINE_SDM845=y +CONFIG_SND_SOC_MSM_HDMI_CODEC_RX=y +CONFIG_SND_SOC_MSM_HOSTLESS_PCM=y +CONFIG_SND_SOC_MSM_QDSP6V2_INTF=y +CONFIG_SND_SOC_MSM_STUB=y +CONFIG_SND_SOC_QDSP6V2=y +CONFIG_SND_SOC_SDM845=y +CONFIG_SND_SOC_TAS2559=y +CONFIG_SND_SOC_WCD934X=y +CONFIG_SND_SOC_WCD934X_DSD=y +CONFIG_SND_SOC_WCD934X_MBHC=y +CONFIG_SND_SOC_WCD9XXX_V2=y +CONFIG_SND_SOC_WCD_MBHC=y +CONFIG_SND_SOC_WCD_MBHC_ADC=y +CONFIG_SND_SOC_WCD_SPI=y +CONFIG_SND_SOC_WSA881X=y +CONFIG_SOUNDWIRE=y +CONFIG_SOUNDWIRE_WCD_CTRL=y +CONFIG_WCD9XXX_CODEC_CORE=y +CONFIG_WCD_DSP_GLINK=y +CONFIG_WCD_SPI_AC=y CONFIG_MACH_XIAOMI_E10=y -# CONFIG_MACH_XIAOMI_E1S is not set -# CONFIG_MACH_XIAOMI_E8 is not set -# CONFIG_MACH_XIAOMI_E5 is not set diff --git a/arch/arm64/configs/polaris_defconfig b/arch/arm64/configs/polaris_defconfig index 5287b14f34d7..68be342bd700 100644 --- a/arch/arm64/configs/polaris_defconfig +++ b/arch/arm64/configs/polaris_defconfig @@ -166,9 +166,9 @@ CONFIG_NETFILTER_XT_MATCH_LIMIT=y CONFIG_NETFILTER_XT_MATCH_MAC=y CONFIG_NETFILTER_XT_MATCH_MARK=y CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +CONFIG_NETFILTER_XT_MATCH_OWNER=y CONFIG_NETFILTER_XT_MATCH_POLICY=y CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y -CONFIG_NETFILTER_XT_MATCH_QTAGUID=y CONFIG_NETFILTER_XT_MATCH_QUOTA=y CONFIG_NETFILTER_XT_MATCH_QUOTA2=y CONFIG_NETFILTER_XT_MATCH_SOCKET=y diff --git a/arch/arm64/configs/ranchu64_defconfig b/arch/arm64/configs/ranchu64_defconfig index 3799e518e26f..4195a35be91c 100644 --- a/arch/arm64/configs/ranchu64_defconfig +++ b/arch/arm64/configs/ranchu64_defconfig @@ -108,7 +108,6 @@ CONFIG_NETFILTER_XT_MATCH_MARK=y CONFIG_NETFILTER_XT_MATCH_OWNER=y CONFIG_NETFILTER_XT_MATCH_POLICY=y CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y -CONFIG_NETFILTER_XT_MATCH_QTAGUID=y CONFIG_NETFILTER_XT_MATCH_QUOTA=y CONFIG_NETFILTER_XT_MATCH_QUOTA2=y CONFIG_NETFILTER_XT_MATCH_SOCKET=y diff --git a/arch/arm64/configs/sdm670-perf_defconfig b/arch/arm64/configs/sdm670-perf_defconfig index f774ab18cae7..2d3985659aee 100755 --- a/arch/arm64/configs/sdm670-perf_defconfig +++ b/arch/arm64/configs/sdm670-perf_defconfig @@ -37,7 +37,6 @@ CONFIG_BLK_DEV_INITRD=y # CONFIG_RD_LZ4 is not set CONFIG_KALLSYMS_ALL=y CONFIG_BPF_SYSCALL=y -# CONFIG_MEMBARRIER is not set CONFIG_EMBEDDED=y # CONFIG_SLUB_DEBUG is not set # CONFIG_COMPAT_BRK is not set @@ -56,7 +55,6 @@ CONFIG_CFQ_GROUP_IOSCHED=y CONFIG_ARCH_QCOM=y CONFIG_ARCH_SDM670=y CONFIG_PCI=y -CONFIG_PCI_MSM=y CONFIG_SCHED_MC=y CONFIG_NR_CPUS=8 CONFIG_PREEMPT=y @@ -72,14 +70,12 @@ CONFIG_ARMV8_DEPRECATED=y CONFIG_SWP_EMULATION=y CONFIG_CP15_BARRIER_EMULATION=y CONFIG_SETEND_EMULATION=y +CONFIG_ARM64_SW_TTBR0_PAN=y # CONFIG_ARM64_VHE is not set CONFIG_RANDOMIZE_BASE=y # CONFIG_EFI is not set -CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y -CONFIG_BUILD_ARM64_UNCOMPRESSED_KERNEL=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_COMPAT=y -CONFIG_PM_AUTOSLEEP=y CONFIG_PM_WAKELOCKS=y CONFIG_PM_WAKELOCKS_LIMIT=0 # CONFIG_PM_WAKELOCKS_GC is not set @@ -96,6 +92,7 @@ CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y CONFIG_XFRM_USER=y +CONFIG_XFRM_INTERFACE=y CONFIG_XFRM_STATISTICS=y CONFIG_NET_KEY=y CONFIG_INET=y @@ -106,6 +103,7 @@ CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_NET_IPGRE_DEMUX=y +CONFIG_SYN_COOKIES=y CONFIG_NET_IPVTI=y CONFIG_INET_AH=y CONFIG_INET_ESP=y @@ -127,7 +125,6 @@ CONFIG_NF_CONNTRACK=y CONFIG_NF_CONNTRACK_SECMARK=y CONFIG_NF_CONNTRACK_EVENTS=y CONFIG_NF_CT_PROTO_DCCP=y -CONFIG_NF_CT_PROTO_SCTP=y CONFIG_NF_CT_PROTO_UDPLITE=y CONFIG_NF_CONNTRACK_AMANDA=y CONFIG_NF_CONNTRACK_FTP=y @@ -174,6 +171,7 @@ CONFIG_NETFILTER_XT_MATCH_POLICY=y CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y CONFIG_NETFILTER_XT_MATCH_QUOTA=y CONFIG_NETFILTER_XT_MATCH_QUOTA2=y +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set CONFIG_NETFILTER_XT_MATCH_SOCKET=y CONFIG_NETFILTER_XT_MATCH_STATE=y CONFIG_NETFILTER_XT_MATCH_STATISTIC=y @@ -207,6 +205,7 @@ CONFIG_IP6_NF_MANGLE=y CONFIG_IP6_NF_RAW=y CONFIG_BRIDGE_NF_EBTABLES=y CONFIG_BRIDGE_EBT_BROUTE=y +CONFIG_IP_SCTP=y CONFIG_L2TP=y CONFIG_L2TP_V3=y CONFIG_L2TP_IP=y @@ -251,6 +250,7 @@ CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y CONFIG_DMA_CMA=y CONFIG_ZRAM=y CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=16 CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_QSEECOM=y @@ -278,6 +278,7 @@ CONFIG_DM_DEFAULT_KEY=y CONFIG_DM_UEVENT=y CONFIG_DM_VERITY=y CONFIG_DM_VERITY_FEC=y +CONFIG_DM_BOW=y CONFIG_NETDEVICES=y CONFIG_BONDING=y CONFIG_DUMMY=y @@ -297,6 +298,7 @@ CONFIG_PPPOLAC=y CONFIG_PPPOPNS=y CONFIG_PPP_ASYNC=y CONFIG_PPP_SYNC_TTY=y +CONFIG_USB_RTL8152=y CONFIG_USB_LAN78XX=y CONFIG_USB_USBNET=y CONFIG_WCNSS_MEM_PRE_ALLOC=y @@ -413,6 +415,7 @@ CONFIG_HID_MAGICMOUSE=y CONFIG_HID_MICROSOFT=y CONFIG_HID_MULTITOUCH=y CONFIG_HID_PLANTRONICS=y +CONFIG_HID_SONY=y CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y CONFIG_USB_XHCI_HCD=y @@ -494,7 +497,6 @@ CONFIG_SPS_SUPPORT_NDP_BAM=y CONFIG_QPNP_COINCELL=y CONFIG_QPNP_REVID=y CONFIG_USB_BAM=y -CONFIG_MSM_11AD=m CONFIG_SEEMP_CORE=y CONFIG_QCOM_GENI_SE=y CONFIG_MSM_GCC_SDM845=y @@ -582,6 +584,7 @@ CONFIG_ARM_GIC_V3_ACL=y CONFIG_ANDROID=y CONFIG_ANDROID_BINDER_IPC=y CONFIG_NVMEM=y +# CONFIG_NVMEM_SYSFS is not set CONFIG_QCOM_QFPROM=y CONFIG_SENSORS_SSC=y CONFIG_MSM_TZ_LOG=y @@ -597,6 +600,7 @@ CONFIG_QUOTA=y CONFIG_QUOTA_NETLINK_INTERFACE=y CONFIG_QFMT_V2=y CONFIG_FUSE_FS=y +CONFIG_OVERLAY_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS_POSIX_ACL=y diff --git a/arch/arm64/configs/sdm670_defconfig b/arch/arm64/configs/sdm670_defconfig index 51fa804c5466..ccfcf65f9608 100755 --- a/arch/arm64/configs/sdm670_defconfig +++ b/arch/arm64/configs/sdm670_defconfig @@ -39,7 +39,6 @@ CONFIG_BLK_DEV_INITRD=y # CONFIG_RD_LZ4 is not set CONFIG_KALLSYMS_ALL=y CONFIG_BPF_SYSCALL=y -# CONFIG_MEMBARRIER is not set CONFIG_EMBEDDED=y # CONFIG_COMPAT_BRK is not set CONFIG_PROFILING=y @@ -59,7 +58,6 @@ CONFIG_CFQ_GROUP_IOSCHED=y CONFIG_ARCH_QCOM=y CONFIG_ARCH_SDM670=y CONFIG_PCI=y -CONFIG_PCI_MSM=y CONFIG_SCHED_MC=y CONFIG_NR_CPUS=8 CONFIG_PREEMPT=y @@ -77,13 +75,11 @@ CONFIG_ARMV8_DEPRECATED=y CONFIG_SWP_EMULATION=y CONFIG_CP15_BARRIER_EMULATION=y CONFIG_SETEND_EMULATION=y +CONFIG_ARM64_SW_TTBR0_PAN=y # CONFIG_ARM64_VHE is not set CONFIG_RANDOMIZE_BASE=y -CONFIG_BUILD_ARM64_APPENDED_DTB_IMAGE=y -CONFIG_BUILD_ARM64_UNCOMPRESSED_KERNEL=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set CONFIG_COMPAT=y -CONFIG_PM_AUTOSLEEP=y CONFIG_PM_WAKELOCKS=y CONFIG_PM_WAKELOCKS_LIMIT=0 # CONFIG_PM_WAKELOCKS_GC is not set @@ -101,6 +97,7 @@ CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y CONFIG_XFRM_USER=y +CONFIG_XFRM_INTERFACE=y CONFIG_XFRM_STATISTICS=y CONFIG_NET_KEY=y CONFIG_INET=y @@ -111,6 +108,7 @@ CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_NET_IPGRE_DEMUX=y +CONFIG_SYN_COOKIES=y CONFIG_NET_IPVTI=y CONFIG_INET_AH=y CONFIG_INET_ESP=y @@ -132,7 +130,6 @@ CONFIG_NF_CONNTRACK=y CONFIG_NF_CONNTRACK_SECMARK=y CONFIG_NF_CONNTRACK_EVENTS=y CONFIG_NF_CT_PROTO_DCCP=y -CONFIG_NF_CT_PROTO_SCTP=y CONFIG_NF_CT_PROTO_UDPLITE=y CONFIG_NF_CONNTRACK_AMANDA=y CONFIG_NF_CONNTRACK_FTP=y @@ -180,6 +177,7 @@ CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y CONFIG_NETFILTER_XT_MATCH_QUOTA=y CONFIG_NETFILTER_XT_MATCH_QUOTA2=y CONFIG_NETFILTER_XT_MATCH_QUOTA2_LOG=y +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set CONFIG_NETFILTER_XT_MATCH_SOCKET=y CONFIG_NETFILTER_XT_MATCH_STATE=y CONFIG_NETFILTER_XT_MATCH_STATISTIC=y @@ -213,6 +211,7 @@ CONFIG_IP6_NF_MANGLE=y CONFIG_IP6_NF_RAW=y CONFIG_BRIDGE_NF_EBTABLES=y CONFIG_BRIDGE_EBT_BROUTE=y +CONFIG_IP_SCTP=y CONFIG_L2TP=y CONFIG_L2TP_DEBUGFS=y CONFIG_L2TP_V3=y @@ -260,6 +259,7 @@ CONFIG_REGMAP_ALLOW_WRITE_DEBUGFS=y CONFIG_DMA_CMA=y CONFIG_ZRAM=y CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=16 CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_SIZE=8192 CONFIG_QSEECOM=y @@ -286,6 +286,7 @@ CONFIG_DM_DEFAULT_KEY=y CONFIG_DM_UEVENT=y CONFIG_DM_VERITY=y CONFIG_DM_VERITY_FEC=y +CONFIG_DM_BOW=y CONFIG_NETDEVICES=y CONFIG_BONDING=y CONFIG_DUMMY=y @@ -303,6 +304,7 @@ CONFIG_PPPOLAC=y CONFIG_PPPOPNS=y CONFIG_PPP_ASYNC=y CONFIG_PPP_SYNC_TTY=y +CONFIG_USB_RTL8152=y CONFIG_USB_LAN78XX=y CONFIG_USB_USBNET=y CONFIG_WCNSS_MEM_PRE_ALLOC=y @@ -421,6 +423,7 @@ CONFIG_HID_MAGICMOUSE=y CONFIG_HID_MICROSOFT=y CONFIG_HID_MULTITOUCH=y CONFIG_HID_PLANTRONICS=y +CONFIG_HID_SONY=y CONFIG_USB=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_EHCI_HCD=y @@ -507,7 +510,6 @@ CONFIG_SPS_SUPPORT_NDP_BAM=y CONFIG_QPNP_COINCELL=y CONFIG_QPNP_REVID=y CONFIG_USB_BAM=y -CONFIG_MSM_11AD=m CONFIG_SEEMP_CORE=y CONFIG_QCOM_GENI_SE=y CONFIG_MSM_GCC_SDM845=y @@ -602,6 +604,7 @@ CONFIG_PHY_XGENE=y CONFIG_ANDROID=y CONFIG_ANDROID_BINDER_IPC=y CONFIG_NVMEM=y +# CONFIG_NVMEM_SYSFS is not set CONFIG_QCOM_QFPROM=y CONFIG_SENSORS_SSC=y CONFIG_MSM_TZ_LOG=y @@ -617,6 +620,7 @@ CONFIG_QUOTA=y CONFIG_QUOTA_NETLINK_INTERFACE=y CONFIG_QFMT_V2=y CONFIG_FUSE_FS=y +CONFIG_OVERLAY_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y CONFIG_TMPFS_POSIX_ACL=y diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h index 0e0841d8c279..f95235abc841 100644 --- a/arch/arm64/include/asm/arch_timer.h +++ b/arch/arm64/include/asm/arch_timer.h @@ -135,7 +135,6 @@ static inline u32 arch_timer_get_cntkctl(void) static inline void arch_timer_set_cntkctl(u32 cntkctl) { write_sysreg(cntkctl, cntkctl_el1); - isb(); } static inline u64 arch_counter_get_cntpct(void) diff --git a/arch/arm64/kernel/bpi.S b/arch/arm64/kernel/bpi.S index ee9684e97394..746a2032d473 100644 --- a/arch/arm64/kernel/bpi.S +++ b/arch/arm64/kernel/bpi.S @@ -98,3 +98,4 @@ ENTRY(__smccc_workaround_1_smc_end) ENTRY(__smccc_workaround_1_hvc_start) smccc_workaround_1 hvc ENTRY(__smccc_workaround_1_hvc_end) +.#endif diff --git a/arch/arm64/kernel/psci.c b/arch/arm64/kernel/psci.c index 3856d51c645b..35e0e6464e62 100644 --- a/arch/arm64/kernel/psci.c +++ b/arch/arm64/kernel/psci.c @@ -100,7 +100,7 @@ static int cpu_psci_cpu_kill(unsigned int cpu) do { err = psci_ops.affinity_info(cpu_logical_map(cpu), 0); if (err == PSCI_0_2_AFFINITY_LEVEL_OFF) { - pr_info("CPU%d killed (polled %d ms)\n", cpu, + pr_debug("CPU%d killed (polled %d ms)\n", cpu, jiffies_to_msecs(jiffies - start)); return 0; } diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index 0920a04124c2..e3bc87826c18 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include diff --git a/arch/arm64/kernel/vdso.c b/arch/arm64/kernel/vdso.c index 069fcbbd73e7..70695e6dae65 100644 --- a/arch/arm64/kernel/vdso.c +++ b/arch/arm64/kernel/vdso.c @@ -193,8 +193,6 @@ static int __init vdso_mappings_init(const char *name, if (vdso_pagelist == NULL) return -ENOMEM; - kmemleak_not_leak(vdso_pagelist); - /* Grab the vDSO data page. */ vdso_pagelist[0] = phys_to_page(__pa_symbol(vdso_data)); diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c index 290be3ff9351..c38c08ee630d 100644 --- a/arch/arm64/mm/dma-mapping.c +++ b/arch/arm64/mm/dma-mapping.c @@ -2253,7 +2253,12 @@ void arm_iommu_detach_device(struct device *dev) iommu_domain_get_attr(mapping->domain, DOMAIN_ATTR_S1_BYPASS, &s1_bypass); - msm_dma_unmap_all_for_dev(dev); + /* + * ION defers dma_unmap calls. Ensure they have all completed prior to + * setting dma_ops to NULL. + */ + if (msm_dma_unmap_all_for_dev(dev)) + dev_warn(dev, "IOMMU detach with outstanding mappings\n"); iommu_detach_group(mapping->domain, dev->iommu_group); dev->archdata.mapping = NULL; diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c index 0f80614c42b4..9c6f3fd58059 100644 --- a/arch/powerpc/kernel/smp.c +++ b/arch/powerpc/kernel/smp.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/s390/kernel/topology.c b/arch/s390/kernel/topology.c index 3984a5313224..69ac47241b19 100644 --- a/arch/s390/kernel/topology.c +++ b/arch/s390/kernel/topology.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include diff --git a/arch/x86/configs/i386_ranchu_defconfig b/arch/x86/configs/i386_ranchu_defconfig index 6a22d94f0da2..f691e2e975c4 100644 --- a/arch/x86/configs/i386_ranchu_defconfig +++ b/arch/x86/configs/i386_ranchu_defconfig @@ -140,7 +140,6 @@ CONFIG_NETFILTER_XT_MATCH_MARK=y CONFIG_NETFILTER_XT_MATCH_OWNER=y CONFIG_NETFILTER_XT_MATCH_POLICY=y CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y -CONFIG_NETFILTER_XT_MATCH_QTAGUID=y CONFIG_NETFILTER_XT_MATCH_QUOTA=y CONFIG_NETFILTER_XT_MATCH_QUOTA2=y CONFIG_NETFILTER_XT_MATCH_SOCKET=y diff --git a/arch/x86/configs/x86_64_cuttlefish_defconfig b/arch/x86/configs/x86_64_cuttlefish_defconfig index 77c24e1b86d5..58e62a20541b 100644 --- a/arch/x86/configs/x86_64_cuttlefish_defconfig +++ b/arch/x86/configs/x86_64_cuttlefish_defconfig @@ -167,7 +167,6 @@ CONFIG_NETFILTER_XT_MATCH_MARK=y CONFIG_NETFILTER_XT_MATCH_OWNER=y CONFIG_NETFILTER_XT_MATCH_POLICY=y CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y -CONFIG_NETFILTER_XT_MATCH_QTAGUID=y CONFIG_NETFILTER_XT_MATCH_QUOTA=y CONFIG_NETFILTER_XT_MATCH_QUOTA2=y CONFIG_NETFILTER_XT_MATCH_SOCKET=y diff --git a/arch/x86/configs/x86_64_ranchu_defconfig b/arch/x86/configs/x86_64_ranchu_defconfig index 0eb5490fc0e3..cafa3dfe63ad 100644 --- a/arch/x86/configs/x86_64_ranchu_defconfig +++ b/arch/x86/configs/x86_64_ranchu_defconfig @@ -138,7 +138,6 @@ CONFIG_NETFILTER_XT_MATCH_MARK=y CONFIG_NETFILTER_XT_MATCH_OWNER=y CONFIG_NETFILTER_XT_MATCH_POLICY=y CONFIG_NETFILTER_XT_MATCH_PKTTYPE=y -CONFIG_NETFILTER_XT_MATCH_QTAGUID=y CONFIG_NETFILTER_XT_MATCH_QUOTA=y CONFIG_NETFILTER_XT_MATCH_QUOTA2=y CONFIG_NETFILTER_XT_MATCH_SOCKET=y diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c index 1c0597d41e4a..ef38bc1d1c00 100644 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -45,7 +45,6 @@ #include #include #include -#include #include #include #include diff --git a/block/bio.c b/block/bio.c index b8bfeefaf3a9..1b7b9812ba7c 100644 --- a/block/bio.c +++ b/block/bio.c @@ -907,25 +907,6 @@ int submit_bio_wait(struct bio *bio) } EXPORT_SYMBOL(submit_bio_wait); -static void submit_bio_nowait_endio(struct bio *bio) -{ - bio_put(bio); -} - -/** - * submit_bio_nowait - submit a bio for fire-and-forget - * @bio: The &struct bio which describes the I/O - * - * Simple wrapper around submit_bio() that takes care of bio_put() on completion - */ -void submit_bio_nowait(struct bio *bio) -{ - bio->bi_end_io = submit_bio_nowait_endio; - bio->bi_opf |= REQ_SYNC; - submit_bio(bio); -} -EXPORT_SYMBOL(submit_bio_nowait); - /** * bio_advance - increment/complete a bio by some number of bytes * @bio: bio to advance diff --git a/block/blk-core.c b/block/blk-core.c index a61752ed3f36..f05e9bbf2ddc 100644 --- a/block/blk-core.c +++ b/block/blk-core.c @@ -309,9 +309,7 @@ inline void __blk_run_queue_uncond(struct request_queue *q) * can wait until all these request_fn calls have finished. */ q->request_fn_active++; - preempt_disable(); q->request_fn(q); - preempt_enable(); q->request_fn_active--; } EXPORT_SYMBOL_GPL(__blk_run_queue_uncond); diff --git a/block/blk-mq.c b/block/blk-mq.c index 3f603e49f2ba..098279a84549 100644 --- a/block/blk-mq.c +++ b/block/blk-mq.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include diff --git a/block/blk-softirq.c b/block/blk-softirq.c index 87b7df4851bf..06cf9807f49a 100644 --- a/block/blk-softirq.c +++ b/block/blk-softirq.c @@ -9,7 +9,6 @@ #include #include #include -#include #include "blk.h" diff --git a/crypto/Kconfig b/crypto/Kconfig index d51b73151563..60ece1b8bfd3 100644 --- a/crypto/Kconfig +++ b/crypto/Kconfig @@ -102,15 +102,6 @@ config CRYPTO_KPP select CRYPTO_ALGAPI select CRYPTO_KPP2 -config CRYPTO_ACOMP2 - tristate - select CRYPTO_ALGAPI2 - -config CRYPTO_ACOMP - tristate - select CRYPTO_ALGAPI - select CRYPTO_ACOMP2 - config CRYPTO_RSA tristate "RSA algorithm" select CRYPTO_AKCIPHER @@ -147,7 +138,6 @@ config CRYPTO_MANAGER2 select CRYPTO_BLKCIPHER2 select CRYPTO_AKCIPHER2 select CRYPTO_KPP2 - select CRYPTO_ACOMP2 config CRYPTO_USER tristate "Userspace cryptographic algorithm configuration" @@ -1641,7 +1631,6 @@ config CRYPTO_842 config CRYPTO_LZ4 tristate "LZ4 compression algorithm" select CRYPTO_ALGAPI - select CRYPTO_ACOMP2 select LZ4_COMPRESS select LZ4_DECOMPRESS help @@ -1650,7 +1639,6 @@ config CRYPTO_LZ4 config CRYPTO_LZ4HC tristate "LZ4HC compression algorithm" select CRYPTO_ALGAPI - select CRYPTO_ACOMP2 select LZ4HC_COMPRESS select LZ4_DECOMPRESS help diff --git a/crypto/Makefile b/crypto/Makefile index 9cb27f163f09..bb20d35a26ee 100644 --- a/crypto/Makefile +++ b/crypto/Makefile @@ -51,9 +51,6 @@ rsa_generic-y += rsa_helper.o rsa_generic-y += rsa-pkcs1pad.o obj-$(CONFIG_CRYPTO_RSA) += rsa_generic.o -obj-$(CONFIG_CRYPTO_ACOMP2) += acompress.o -obj-$(CONFIG_CRYPTO_ACOMP2) += scompress.o - cryptomgr-y := algboss.o testmgr.o obj-$(CONFIG_CRYPTO_MANAGER2) += cryptomgr.o diff --git a/crypto/acompress.c b/crypto/acompress.c deleted file mode 100644 index 887783d8e9a9..000000000000 --- a/crypto/acompress.c +++ /dev/null @@ -1,169 +0,0 @@ -/* - * Asynchronous Compression operations - * - * Copyright (c) 2016, Intel Corporation - * Authors: Weigang Li - * Giovanni Cabiddu - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) - * any later version. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "internal.h" - -static const struct crypto_type crypto_acomp_type; - -#ifdef CONFIG_NET -static int crypto_acomp_report(struct sk_buff *skb, struct crypto_alg *alg) -{ - struct crypto_report_acomp racomp; - - strncpy(racomp.type, "acomp", sizeof(racomp.type)); - - if (nla_put(skb, CRYPTOCFGA_REPORT_ACOMP, - sizeof(struct crypto_report_acomp), &racomp)) - goto nla_put_failure; - return 0; - -nla_put_failure: - return -EMSGSIZE; -} -#else -static int crypto_acomp_report(struct sk_buff *skb, struct crypto_alg *alg) -{ - return -ENOSYS; -} -#endif - -static void crypto_acomp_show(struct seq_file *m, struct crypto_alg *alg) - __attribute__ ((unused)); - -static void crypto_acomp_show(struct seq_file *m, struct crypto_alg *alg) -{ - seq_puts(m, "type : acomp\n"); -} - -static void crypto_acomp_exit_tfm(struct crypto_tfm *tfm) -{ - struct crypto_acomp *acomp = __crypto_acomp_tfm(tfm); - struct acomp_alg *alg = crypto_acomp_alg(acomp); - - alg->exit(acomp); -} - -static int crypto_acomp_init_tfm(struct crypto_tfm *tfm) -{ - struct crypto_acomp *acomp = __crypto_acomp_tfm(tfm); - struct acomp_alg *alg = crypto_acomp_alg(acomp); - - if (tfm->__crt_alg->cra_type != &crypto_acomp_type) - return crypto_init_scomp_ops_async(tfm); - - acomp->compress = alg->compress; - acomp->decompress = alg->decompress; - acomp->dst_free = alg->dst_free; - acomp->reqsize = alg->reqsize; - - if (alg->exit) - acomp->base.exit = crypto_acomp_exit_tfm; - - if (alg->init) - return alg->init(acomp); - - return 0; -} - -static unsigned int crypto_acomp_extsize(struct crypto_alg *alg) -{ - int extsize = crypto_alg_extsize(alg); - - if (alg->cra_type != &crypto_acomp_type) - extsize += sizeof(struct crypto_scomp *); - - return extsize; -} - -static const struct crypto_type crypto_acomp_type = { - .extsize = crypto_acomp_extsize, - .init_tfm = crypto_acomp_init_tfm, -#ifdef CONFIG_PROC_FS - .show = crypto_acomp_show, -#endif - .report = crypto_acomp_report, - .maskclear = ~CRYPTO_ALG_TYPE_MASK, - .maskset = CRYPTO_ALG_TYPE_ACOMPRESS_MASK, - .type = CRYPTO_ALG_TYPE_ACOMPRESS, - .tfmsize = offsetof(struct crypto_acomp, base), -}; - -struct crypto_acomp *crypto_alloc_acomp(const char *alg_name, u32 type, - u32 mask) -{ - return crypto_alloc_tfm(alg_name, &crypto_acomp_type, type, mask); -} -EXPORT_SYMBOL_GPL(crypto_alloc_acomp); - -struct acomp_req *acomp_request_alloc(struct crypto_acomp *acomp) -{ - struct crypto_tfm *tfm = crypto_acomp_tfm(acomp); - struct acomp_req *req; - - req = __acomp_request_alloc(acomp); - if (req && (tfm->__crt_alg->cra_type != &crypto_acomp_type)) - return crypto_acomp_scomp_alloc_ctx(req); - - return req; -} -EXPORT_SYMBOL_GPL(acomp_request_alloc); - -void acomp_request_free(struct acomp_req *req) -{ - struct crypto_acomp *acomp = crypto_acomp_reqtfm(req); - struct crypto_tfm *tfm = crypto_acomp_tfm(acomp); - - if (tfm->__crt_alg->cra_type != &crypto_acomp_type) - crypto_acomp_scomp_free_ctx(req); - - if (req->flags & CRYPTO_ACOMP_ALLOC_OUTPUT) { - acomp->dst_free(req->dst); - req->dst = NULL; - } - - __acomp_request_free(req); -} -EXPORT_SYMBOL_GPL(acomp_request_free); - -int crypto_register_acomp(struct acomp_alg *alg) -{ - struct crypto_alg *base = &alg->base; - - base->cra_type = &crypto_acomp_type; - base->cra_flags &= ~CRYPTO_ALG_TYPE_MASK; - base->cra_flags |= CRYPTO_ALG_TYPE_ACOMPRESS; - - return crypto_register_alg(base); -} -EXPORT_SYMBOL_GPL(crypto_register_acomp); - -int crypto_unregister_acomp(struct acomp_alg *alg) -{ - return crypto_unregister_alg(&alg->base); -} -EXPORT_SYMBOL_GPL(crypto_unregister_acomp); - -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("Asynchronous compression type"); diff --git a/crypto/crypto_user.c b/crypto/crypto_user.c index 6b90d30b972c..810be7a9e3c4 100644 --- a/crypto/crypto_user.c +++ b/crypto/crypto_user.c @@ -115,21 +115,6 @@ static int crypto_report_comp(struct sk_buff *skb, struct crypto_alg *alg) return -EMSGSIZE; } -static int crypto_report_acomp(struct sk_buff *skb, struct crypto_alg *alg) -{ - struct crypto_report_acomp racomp; - - strncpy(racomp.type, "acomp", sizeof(racomp.type)); - - if (nla_put(skb, CRYPTOCFGA_REPORT_ACOMP, - sizeof(struct crypto_report_acomp), &racomp)) - goto nla_put_failure; - return 0; - -nla_put_failure: - return -EMSGSIZE; -} - static int crypto_report_akcipher(struct sk_buff *skb, struct crypto_alg *alg) { struct crypto_report_akcipher rakcipher; @@ -204,11 +189,7 @@ static int crypto_report_one(struct crypto_alg *alg, goto nla_put_failure; break; - case CRYPTO_ALG_TYPE_ACOMPRESS: - if (crypto_report_acomp(skb, alg)) - goto nla_put_failure; - break; case CRYPTO_ALG_TYPE_AKCIPHER: if (crypto_report_akcipher(skb, alg)) goto nla_put_failure; diff --git a/crypto/lz4.c b/crypto/lz4.c index 99c1b2cc2976..aefbceaf3104 100644 --- a/crypto/lz4.c +++ b/crypto/lz4.c @@ -23,53 +23,36 @@ #include #include #include -#include struct lz4_ctx { void *lz4_comp_mem; }; -static void *lz4_alloc_ctx(struct crypto_scomp *tfm) -{ - void *ctx; - - ctx = vmalloc(LZ4_MEM_COMPRESS); - if (!ctx) - return ERR_PTR(-ENOMEM); - - return ctx; -} - static int lz4_init(struct crypto_tfm *tfm) { struct lz4_ctx *ctx = crypto_tfm_ctx(tfm); - ctx->lz4_comp_mem = lz4_alloc_ctx(NULL); - if (IS_ERR(ctx->lz4_comp_mem)) + ctx->lz4_comp_mem = vmalloc(LZ4_MEM_COMPRESS); + if (!ctx->lz4_comp_mem) return -ENOMEM; return 0; } -static void lz4_free_ctx(struct crypto_scomp *tfm, void *ctx) -{ - vfree(ctx); -} - static void lz4_exit(struct crypto_tfm *tfm) { struct lz4_ctx *ctx = crypto_tfm_ctx(tfm); - - lz4_free_ctx(NULL, ctx->lz4_comp_mem); + vfree(ctx->lz4_comp_mem); } -static int __lz4_compress_crypto(const u8 *src, unsigned int slen, - u8 *dst, unsigned int *dlen, void *ctx) +static int lz4_compress_crypto(struct crypto_tfm *tfm, const u8 *src, + unsigned int slen, u8 *dst, unsigned int *dlen) { + struct lz4_ctx *ctx = crypto_tfm_ctx(tfm); size_t tmp_len = *dlen; int err; - err = lz4_compress(src, slen, dst, &tmp_len, ctx); + err = lz4_compress(src, slen, dst, &tmp_len, ctx->lz4_comp_mem); if (err < 0) return -EINVAL; @@ -78,23 +61,8 @@ static int __lz4_compress_crypto(const u8 *src, unsigned int slen, return 0; } -static int lz4_scompress(struct crypto_scomp *tfm, const u8 *src, - unsigned int slen, u8 *dst, unsigned int *dlen, - void *ctx) -{ - return __lz4_compress_crypto(src, slen, dst, dlen, ctx); -} - -static int lz4_compress_crypto(struct crypto_tfm *tfm, const u8 *src, - unsigned int slen, u8 *dst, unsigned int *dlen) -{ - struct lz4_ctx *ctx = crypto_tfm_ctx(tfm); - - return __lz4_compress_crypto(src, slen, dst, dlen, ctx->lz4_comp_mem); -} - -static int __lz4_decompress_crypto(const u8 *src, unsigned int slen, - u8 *dst, unsigned int *dlen, void *ctx) +static int lz4_decompress_crypto(struct crypto_tfm *tfm, const u8 *src, + unsigned int slen, u8 *dst, unsigned int *dlen) { int err; size_t tmp_len = *dlen; @@ -108,20 +76,6 @@ static int __lz4_decompress_crypto(const u8 *src, unsigned int slen, return err; } -static int lz4_sdecompress(struct crypto_scomp *tfm, const u8 *src, - unsigned int slen, u8 *dst, unsigned int *dlen, - void *ctx) -{ - return __lz4_decompress_crypto(src, slen, dst, dlen, NULL); -} - -static int lz4_decompress_crypto(struct crypto_tfm *tfm, const u8 *src, - unsigned int slen, u8 *dst, - unsigned int *dlen) -{ - return __lz4_decompress_crypto(src, slen, dst, dlen, NULL); -} - static struct crypto_alg alg_lz4 = { .cra_name = "lz4", .cra_flags = CRYPTO_ALG_TYPE_COMPRESS, @@ -135,39 +89,14 @@ static struct crypto_alg alg_lz4 = { .coa_decompress = lz4_decompress_crypto } } }; -static struct scomp_alg scomp = { - .alloc_ctx = lz4_alloc_ctx, - .free_ctx = lz4_free_ctx, - .compress = lz4_scompress, - .decompress = lz4_sdecompress, - .base = { - .cra_name = "lz4", - .cra_driver_name = "lz4-scomp", - .cra_module = THIS_MODULE, - } -}; - static int __init lz4_mod_init(void) { - int ret; - - ret = crypto_register_alg(&alg_lz4); - if (ret) - return ret; - - ret = crypto_register_scomp(&scomp); - if (ret) { - crypto_unregister_alg(&alg_lz4); - return ret; - } - - return ret; + return crypto_register_alg(&alg_lz4); } static void __exit lz4_mod_fini(void) { crypto_unregister_alg(&alg_lz4); - crypto_unregister_scomp(&scomp); } module_init(lz4_mod_init); diff --git a/crypto/lz4hc.c b/crypto/lz4hc.c index 75ffc4a3f786..a1d3b5bd3d85 100644 --- a/crypto/lz4hc.c +++ b/crypto/lz4hc.c @@ -22,53 +22,37 @@ #include #include #include -#include struct lz4hc_ctx { void *lz4hc_comp_mem; }; -static void *lz4hc_alloc_ctx(struct crypto_scomp *tfm) -{ - void *ctx; - - ctx = vmalloc(LZ4HC_MEM_COMPRESS); - if (!ctx) - return ERR_PTR(-ENOMEM); - - return ctx; -} - static int lz4hc_init(struct crypto_tfm *tfm) { struct lz4hc_ctx *ctx = crypto_tfm_ctx(tfm); - ctx->lz4hc_comp_mem = lz4hc_alloc_ctx(NULL); - if (IS_ERR(ctx->lz4hc_comp_mem)) + ctx->lz4hc_comp_mem = vmalloc(LZ4HC_MEM_COMPRESS); + if (!ctx->lz4hc_comp_mem) return -ENOMEM; return 0; } -static void lz4hc_free_ctx(struct crypto_scomp *tfm, void *ctx) -{ - vfree(ctx); -} - static void lz4hc_exit(struct crypto_tfm *tfm) { struct lz4hc_ctx *ctx = crypto_tfm_ctx(tfm); - lz4hc_free_ctx(NULL, ctx->lz4hc_comp_mem); + vfree(ctx->lz4hc_comp_mem); } -static int __lz4hc_compress_crypto(const u8 *src, unsigned int slen, - u8 *dst, unsigned int *dlen, void *ctx) +static int lz4hc_compress_crypto(struct crypto_tfm *tfm, const u8 *src, + unsigned int slen, u8 *dst, unsigned int *dlen) { + struct lz4hc_ctx *ctx = crypto_tfm_ctx(tfm); size_t tmp_len = *dlen; int err; - err = lz4hc_compress(src, slen, dst, &tmp_len, ctx); + err = lz4hc_compress(src, slen, dst, &tmp_len, ctx->lz4hc_comp_mem); if (err < 0) return -EINVAL; @@ -77,25 +61,8 @@ static int __lz4hc_compress_crypto(const u8 *src, unsigned int slen, return 0; } -static int lz4hc_scompress(struct crypto_scomp *tfm, const u8 *src, - unsigned int slen, u8 *dst, unsigned int *dlen, - void *ctx) -{ - return __lz4hc_compress_crypto(src, slen, dst, dlen, ctx); -} - -static int lz4hc_compress_crypto(struct crypto_tfm *tfm, const u8 *src, - unsigned int slen, u8 *dst, - unsigned int *dlen) -{ - struct lz4hc_ctx *ctx = crypto_tfm_ctx(tfm); - - return __lz4hc_compress_crypto(src, slen, dst, dlen, - ctx->lz4hc_comp_mem); -} - -static int __lz4hc_decompress_crypto(const u8 *src, unsigned int slen, - u8 *dst, unsigned int *dlen, void *ctx) +static int lz4hc_decompress_crypto(struct crypto_tfm *tfm, const u8 *src, + unsigned int slen, u8 *dst, unsigned int *dlen) { int err; size_t tmp_len = *dlen; @@ -109,20 +76,6 @@ static int __lz4hc_decompress_crypto(const u8 *src, unsigned int slen, return err; } -static int lz4hc_sdecompress(struct crypto_scomp *tfm, const u8 *src, - unsigned int slen, u8 *dst, unsigned int *dlen, - void *ctx) -{ - return __lz4hc_decompress_crypto(src, slen, dst, dlen, NULL); -} - -static int lz4hc_decompress_crypto(struct crypto_tfm *tfm, const u8 *src, - unsigned int slen, u8 *dst, - unsigned int *dlen) -{ - return __lz4hc_decompress_crypto(src, slen, dst, dlen, NULL); -} - static struct crypto_alg alg_lz4hc = { .cra_name = "lz4hc", .cra_flags = CRYPTO_ALG_TYPE_COMPRESS, @@ -136,39 +89,14 @@ static struct crypto_alg alg_lz4hc = { .coa_decompress = lz4hc_decompress_crypto } } }; -static struct scomp_alg scomp = { - .alloc_ctx = lz4hc_alloc_ctx, - .free_ctx = lz4hc_free_ctx, - .compress = lz4hc_scompress, - .decompress = lz4hc_sdecompress, - .base = { - .cra_name = "lz4hc", - .cra_driver_name = "lz4hc-scomp", - .cra_module = THIS_MODULE, - } -}; - static int __init lz4hc_mod_init(void) { - int ret; - - ret = crypto_register_alg(&alg_lz4hc); - if (ret) - return ret; - - ret = crypto_register_scomp(&scomp); - if (ret) { - crypto_unregister_alg(&alg_lz4hc); - return ret; - } - - return ret; + return crypto_register_alg(&alg_lz4hc); } static void __exit lz4hc_mod_fini(void) { crypto_unregister_alg(&alg_lz4hc); - crypto_unregister_scomp(&scomp); } module_init(lz4hc_mod_init); diff --git a/crypto/scompress.c b/crypto/scompress.c deleted file mode 100644 index 35e396d154b7..000000000000 --- a/crypto/scompress.c +++ /dev/null @@ -1,356 +0,0 @@ -/* - * Synchronous Compression operations - * - * Copyright 2015 LG Electronics Inc. - * Copyright (c) 2016, Intel Corporation - * Author: Giovanni Cabiddu - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) - * any later version. - * - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "internal.h" - -static const struct crypto_type crypto_scomp_type; -static void * __percpu *scomp_src_scratches; -static void * __percpu *scomp_dst_scratches; -static int scomp_scratch_users; -static DEFINE_MUTEX(scomp_lock); - -#ifdef CONFIG_NET -static int crypto_scomp_report(struct sk_buff *skb, struct crypto_alg *alg) -{ - struct crypto_report_comp rscomp; - - strncpy(rscomp.type, "scomp", sizeof(rscomp.type)); - - if (nla_put(skb, CRYPTOCFGA_REPORT_COMPRESS, - sizeof(struct crypto_report_comp), &rscomp)) - goto nla_put_failure; - return 0; - -nla_put_failure: - return -EMSGSIZE; -} -#else -static int crypto_scomp_report(struct sk_buff *skb, struct crypto_alg *alg) -{ - return -ENOSYS; -} -#endif - -static void crypto_scomp_show(struct seq_file *m, struct crypto_alg *alg) - __attribute__ ((unused)); - -static void crypto_scomp_show(struct seq_file *m, struct crypto_alg *alg) -{ - seq_puts(m, "type : scomp\n"); -} - -static int crypto_scomp_init_tfm(struct crypto_tfm *tfm) -{ - return 0; -} - -static void crypto_scomp_free_scratches(void * __percpu *scratches) -{ - int i; - - if (!scratches) - return; - - for_each_possible_cpu(i) - vfree(*per_cpu_ptr(scratches, i)); - - free_percpu(scratches); -} - -static void * __percpu *crypto_scomp_alloc_scratches(void) -{ - void * __percpu *scratches; - int i; - - scratches = alloc_percpu(void *); - if (!scratches) - return NULL; - - for_each_possible_cpu(i) { - void *scratch; - - scratch = vmalloc_node(SCOMP_SCRATCH_SIZE, cpu_to_node(i)); - if (!scratch) - goto error; - *per_cpu_ptr(scratches, i) = scratch; - } - - return scratches; - -error: - crypto_scomp_free_scratches(scratches); - return NULL; -} - -static void crypto_scomp_free_all_scratches(void) -{ - if (!--scomp_scratch_users) { - crypto_scomp_free_scratches(scomp_src_scratches); - crypto_scomp_free_scratches(scomp_dst_scratches); - scomp_src_scratches = NULL; - scomp_dst_scratches = NULL; - } -} - -static int crypto_scomp_alloc_all_scratches(void) -{ - if (!scomp_scratch_users++) { - scomp_src_scratches = crypto_scomp_alloc_scratches(); - if (!scomp_src_scratches) - return -ENOMEM; - scomp_dst_scratches = crypto_scomp_alloc_scratches(); - if (!scomp_dst_scratches) - return -ENOMEM; - } - return 0; -} - -static void crypto_scomp_sg_free(struct scatterlist *sgl) -{ - int i, n; - struct page *page; - - if (!sgl) - return; - - n = sg_nents(sgl); - for_each_sg(sgl, sgl, n, i) { - page = sg_page(sgl); - if (page) - __free_page(page); - } - - kfree(sgl); -} - -static struct scatterlist *crypto_scomp_sg_alloc(size_t size, gfp_t gfp) -{ - struct scatterlist *sgl; - struct page *page; - int i, n; - - n = ((size - 1) >> PAGE_SHIFT) + 1; - - sgl = kmalloc_array(n, sizeof(struct scatterlist), gfp); - if (!sgl) - return NULL; - - sg_init_table(sgl, n); - - for (i = 0; i < n; i++) { - page = alloc_page(gfp); - if (!page) - goto err; - sg_set_page(sgl + i, page, PAGE_SIZE, 0); - } - - return sgl; - -err: - sg_mark_end(sgl + i); - crypto_scomp_sg_free(sgl); - return NULL; -} - -static int scomp_acomp_comp_decomp(struct acomp_req *req, int dir) -{ - struct crypto_acomp *tfm = crypto_acomp_reqtfm(req); - void **tfm_ctx = acomp_tfm_ctx(tfm); - struct crypto_scomp *scomp = *tfm_ctx; - void **ctx = acomp_request_ctx(req); - const int cpu = get_cpu(); - u8 *scratch_src = *per_cpu_ptr(scomp_src_scratches, cpu); - u8 *scratch_dst = *per_cpu_ptr(scomp_dst_scratches, cpu); - int ret; - - if (!req->src || !req->slen || req->slen > SCOMP_SCRATCH_SIZE) { - ret = -EINVAL; - goto out; - } - - if (req->dst && !req->dlen) { - ret = -EINVAL; - goto out; - } - - if (!req->dlen || req->dlen > SCOMP_SCRATCH_SIZE) - req->dlen = SCOMP_SCRATCH_SIZE; - - scatterwalk_map_and_copy(scratch_src, req->src, 0, req->slen, 0); - if (dir) - ret = crypto_scomp_compress(scomp, scratch_src, req->slen, - scratch_dst, &req->dlen, *ctx); - else - ret = crypto_scomp_decompress(scomp, scratch_src, req->slen, - scratch_dst, &req->dlen, *ctx); - if (!ret) { - if (!req->dst) { - req->dst = crypto_scomp_sg_alloc(req->dlen, - req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP ? - GFP_KERNEL : GFP_ATOMIC); - if (!req->dst) - goto out; - } - scatterwalk_map_and_copy(scratch_dst, req->dst, 0, req->dlen, - 1); - } -out: - put_cpu(); - return ret; -} - -static int scomp_acomp_compress(struct acomp_req *req) -{ - return scomp_acomp_comp_decomp(req, 1); -} - -static int scomp_acomp_decompress(struct acomp_req *req) -{ - return scomp_acomp_comp_decomp(req, 0); -} - -static void crypto_exit_scomp_ops_async(struct crypto_tfm *tfm) -{ - struct crypto_scomp **ctx = crypto_tfm_ctx(tfm); - - crypto_free_scomp(*ctx); -} - -int crypto_init_scomp_ops_async(struct crypto_tfm *tfm) -{ - struct crypto_alg *calg = tfm->__crt_alg; - struct crypto_acomp *crt = __crypto_acomp_tfm(tfm); - struct crypto_scomp **ctx = crypto_tfm_ctx(tfm); - struct crypto_scomp *scomp; - - if (!crypto_mod_get(calg)) - return -EAGAIN; - - scomp = crypto_create_tfm(calg, &crypto_scomp_type); - if (IS_ERR(scomp)) { - crypto_mod_put(calg); - return PTR_ERR(scomp); - } - - *ctx = scomp; - tfm->exit = crypto_exit_scomp_ops_async; - - crt->compress = scomp_acomp_compress; - crt->decompress = scomp_acomp_decompress; - crt->dst_free = crypto_scomp_sg_free; - crt->reqsize = sizeof(void *); - - return 0; -} - -struct acomp_req *crypto_acomp_scomp_alloc_ctx(struct acomp_req *req) -{ - struct crypto_acomp *acomp = crypto_acomp_reqtfm(req); - struct crypto_tfm *tfm = crypto_acomp_tfm(acomp); - struct crypto_scomp **tfm_ctx = crypto_tfm_ctx(tfm); - struct crypto_scomp *scomp = *tfm_ctx; - void *ctx; - - ctx = crypto_scomp_alloc_ctx(scomp); - if (IS_ERR(ctx)) { - kfree(req); - return NULL; - } - - *req->__ctx = ctx; - - return req; -} - -void crypto_acomp_scomp_free_ctx(struct acomp_req *req) -{ - struct crypto_acomp *acomp = crypto_acomp_reqtfm(req); - struct crypto_tfm *tfm = crypto_acomp_tfm(acomp); - struct crypto_scomp **tfm_ctx = crypto_tfm_ctx(tfm); - struct crypto_scomp *scomp = *tfm_ctx; - void *ctx = *req->__ctx; - - if (ctx) - crypto_scomp_free_ctx(scomp, ctx); -} - -static const struct crypto_type crypto_scomp_type = { - .extsize = crypto_alg_extsize, - .init_tfm = crypto_scomp_init_tfm, -#ifdef CONFIG_PROC_FS - .show = crypto_scomp_show, -#endif - .report = crypto_scomp_report, - .maskclear = ~CRYPTO_ALG_TYPE_MASK, - .maskset = CRYPTO_ALG_TYPE_MASK, - .type = CRYPTO_ALG_TYPE_SCOMPRESS, - .tfmsize = offsetof(struct crypto_scomp, base), -}; - -int crypto_register_scomp(struct scomp_alg *alg) -{ - struct crypto_alg *base = &alg->base; - int ret = -ENOMEM; - - mutex_lock(&scomp_lock); - if (crypto_scomp_alloc_all_scratches()) - goto error; - - base->cra_type = &crypto_scomp_type; - base->cra_flags &= ~CRYPTO_ALG_TYPE_MASK; - base->cra_flags |= CRYPTO_ALG_TYPE_SCOMPRESS; - - ret = crypto_register_alg(base); - if (ret) - goto error; - - mutex_unlock(&scomp_lock); - return ret; - -error: - crypto_scomp_free_all_scratches(); - mutex_unlock(&scomp_lock); - return ret; -} -EXPORT_SYMBOL_GPL(crypto_register_scomp); - -int crypto_unregister_scomp(struct scomp_alg *alg) -{ - int ret; - - mutex_lock(&scomp_lock); - ret = crypto_unregister_alg(&alg->base); - crypto_scomp_free_all_scratches(); - mutex_unlock(&scomp_lock); - - return ret; -} -EXPORT_SYMBOL_GPL(crypto_unregister_scomp); - -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("Synchronous compression type"); diff --git a/drivers/Kconfig b/drivers/Kconfig index 358dbd4ccca9..26d0e2e106bb 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -216,6 +216,8 @@ source "drivers/tee/Kconfig" source "drivers/gps/Kconfig" +source "drivers/halls/Kconfig" + source "drivers/dts_eagle/Kconfig" endmenu diff --git a/drivers/Makefile b/drivers/Makefile index 3400289e9219..cc7b4e1e13e6 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -183,6 +183,7 @@ obj-$(CONFIG_FPGA) += fpga/ obj-$(CONFIG_SENSORS_SSC) += sensors/ obj-$(CONFIG_TEE) += tee/ obj-$(CONFIG_BCM_GPS_SPI_DRIVER) += gps/ +obj-$(CONFIG_HALLS) += halls/ # DTS_EAGLE START obj-$(CONFIG_AINUR_DTS_SW) += dts_eagle/ diff --git a/drivers/android/binder.c b/drivers/android/binder.c index 57a64b11bb63..f7f9a20d5d98 100644 --- a/drivers/android/binder.c +++ b/drivers/android/binder.c @@ -134,7 +134,8 @@ enum { BINDER_DEBUG_PRIORITY_CAP = 1U << 13, BINDER_DEBUG_SPINLOCKS = 1U << 14, }; -static uint32_t binder_debug_mask = 0; +static uint32_t binder_debug_mask = BINDER_DEBUG_USER_ERROR | + BINDER_DEBUG_FAILED_TRANSACTION | BINDER_DEBUG_DEAD_TRANSACTION; module_param_named(debug_mask, binder_debug_mask, uint, 0644); static char *binder_devices_param = CONFIG_ANDROID_BINDER_DEVICES; diff --git a/drivers/base/core.c b/drivers/base/core.c index 80a1d3a6f846..ee783abc1c96 100644 --- a/drivers/base/core.c +++ b/drivers/base/core.c @@ -717,8 +717,6 @@ void device_initialize(struct device *dev) #ifdef CONFIG_GENERIC_MSI_IRQ INIT_LIST_HEAD(&dev->msi_list); #endif - INIT_LIST_HEAD(&dev->iommu_map_list); - mutex_init(&dev->iommu_map_lock); } EXPORT_SYMBOL_GPL(device_initialize); diff --git a/drivers/base/power/main.c b/drivers/base/power/main.c index 1f6406a1f60d..76373148385c 100644 --- a/drivers/base/power/main.c +++ b/drivers/base/power/main.c @@ -672,10 +672,6 @@ void dpm_resume_early(pm_message_t state) struct device *dev; ktime_t starttime = ktime_get(); -#ifdef CONFIG_BOEFFLA_WL_BLOCKER - pm_print_active_wakeup_sources(); -#endif - trace_suspend_resume(TPS("dpm_resume_early"), state.event, true); mutex_lock(&dpm_list_mtx); pm_transition = state; diff --git a/drivers/base/power/wakeup.c b/drivers/base/power/wakeup.c index 6f769bcb9e90..39676b3f3fb9 100644 --- a/drivers/base/power/wakeup.c +++ b/drivers/base/power/wakeup.c @@ -22,16 +22,6 @@ #include "power.h" -#ifdef CONFIG_BOEFFLA_WL_BLOCKER -#include "boeffla_wl_blocker.h" - -char list_wl_search[LENGTH_LIST_WL_SEARCH] = {0}; -bool wl_blocker_active = false; -bool wl_blocker_debug = false; - -static void wakeup_source_deactivate(struct wakeup_source *ws); -#endif - /* * If set, the suspend/hibernate code will abort transitions to a sleep state * if wakeup events are registered during or immediately before the transition. @@ -564,77 +554,19 @@ static void wakeup_source_activate(struct wakeup_source *ws) trace_wakeup_source_activate(ws->name, cec); } -#ifdef CONFIG_BOEFFLA_WL_BLOCKER -// AP: Function to check if a wakelock is on the wakelock blocker list -static bool check_for_block(struct wakeup_source *ws) -{ - char wakelock_name[52] = {0}; - int length; - - // if debug mode on, print every wakelock requested - if (wl_blocker_debug) - printk("Boeffla WL blocker: %s requested\n", ws->name); - - // if there is no list of wakelocks to be blocked, exit without futher checking - if (!wl_blocker_active) - return false; - - // only if ws structure is valid - if (ws) - { - // wake lock names handled have maximum length=50 and minimum=1 - length = strlen(ws->name); - if ((length > 50) || (length < 1)) - return false; - - // check if wakelock is in wake lock list to be blocked - sprintf(wakelock_name, ";%s;", ws->name); - - if(strstr(list_wl_search, wakelock_name) == NULL) - return false; - - // wake lock is in list, print it if debug mode on - if (wl_blocker_debug) - printk("Boeffla WL blocker: %s blocked\n", ws->name); - - // if it is currently active, deactivate it immediately + log in debug mode - if (ws->active) - { - wakeup_source_deactivate(ws); - - if (wl_blocker_debug) - printk("Boeffla WL blocker: %s killed\n", ws->name); - } - - // finally block it - return true; - } - - // there was no valid ws structure, do not block by default - return false; -} -#endif - /** * wakeup_source_report_event - Report wakeup event using the given source. * @ws: Wakeup source to report the event for. */ static void wakeup_source_report_event(struct wakeup_source *ws) { -#ifdef CONFIG_BOEFFLA_WL_BLOCKER - if (!check_for_block(ws)) // AP: check if wakelock is on wakelock blocker list - { -#endif - ws->event_count++; - /* This is racy, but the counter is approximate anyway. */ - if (events_check_enabled) - ws->wakeup_count++; - - if (!ws->active) - wakeup_source_activate(ws); -#ifdef CONFIG_BOEFFLA_WL_BLOCKER - } -#endif + ws->event_count++; + /* This is racy, but the counter is approximate anyway. */ + if (events_check_enabled) + ws->wakeup_count++; + + if (!ws->active) + wakeup_source_activate(ws); } /** @@ -923,10 +855,7 @@ void pm_print_active_wakeup_sources(void) list_for_each_entry_rcu(ws, &wakeup_sources, entry) { if (ws->active) { pr_info("active wakeup source: %s\n", ws->name); -#ifdef CONFIG_BOEFFLA_WL_BLOCKER - if (!check_for_block(ws)) // AP: check if wakelock is on wakelock blocker list -#endif - active = 1; + active = 1; } else if (!active && (!last_activity_ws || ktime_to_ns(ws->last_time) > diff --git a/drivers/block/zram/zram_drv.c b/drivers/block/zram/zram_drv.c index 389120ffe61c..853b63108346 100644 --- a/drivers/block/zram/zram_drv.c +++ b/drivers/block/zram/zram_drv.c @@ -40,11 +40,7 @@ static DEFINE_IDR(zram_index_idr); static DEFINE_MUTEX(zram_index_mutex); static int zram_major; -#ifdef CONFIG_CRYPTO_LZ4 -static const char *default_compressor = "lz4"; -#else static const char *default_compressor = "lzo"; -#endif /* Module params (documentation at end) */ static unsigned int num_devices = 1; diff --git a/drivers/char/Makefile b/drivers/char/Makefile index b7835fe4c2e9..a00142ae018a 100644 --- a/drivers/char/Makefile +++ b/drivers/char/Makefile @@ -2,7 +2,7 @@ # Makefile for the kernel character device drivers. # -obj-y += mem.o random.o frandom.o +obj-y += mem.o random.o obj-$(CONFIG_TTY_PRINTK) += ttyprintk.o obj-y += misc.o obj-$(CONFIG_ATARI_DSP56K) += dsp56k.o diff --git a/drivers/char/adsprpc.c b/drivers/char/adsprpc.c index a8d3aa833f54..9033c23625ac 100644 --- a/drivers/char/adsprpc.c +++ b/drivers/char/adsprpc.c @@ -806,7 +806,7 @@ static int fastrpc_mmap_create(struct fastrpc_file *fl, int fd, struct fastrpc_session_ctx *sess; struct fastrpc_apps *apps = fl->apps; int cid = fl->cid; - struct fastrpc_channel_ctx *chan = NULL; + struct fastrpc_channel_ctx *chan = &apps->channel[cid]; struct fastrpc_mmap *map = NULL; unsigned long attrs; dma_addr_t region_phys = 0; @@ -814,11 +814,6 @@ static int fastrpc_mmap_create(struct fastrpc_file *fl, int fd, unsigned long flags; int err = 0, vmid; - VERIFY(err, cid >= 0 && cid < NUM_CHANNELS); - if (err) - goto bail; - chan = &apps->channel[cid]; - if (!fastrpc_mmap_find(fl, fd, va, len, mflags, 1, ppmap)) return 0; map = kzalloc(sizeof(*map), GFP_KERNEL); @@ -2377,9 +2372,6 @@ static int fastrpc_release_current_dsp_process(struct fastrpc_file *fl) ioctl.crc = NULL; VERIFY(err, 0 == (err = fastrpc_internal_invoke(fl, FASTRPC_MODE_PARALLEL, 1, &ioctl))); - if (err) - pr_err("adsprpc: %s: releasing DSP process failed for %s, returned 0x%x", - __func__, current->comm, err); bail: return err; } diff --git a/drivers/char/diag/diag_masks.c b/drivers/char/diag/diag_masks.c index afb3f8adb09e..4335ad47cc14 100644 --- a/drivers/char/diag/diag_masks.c +++ b/drivers/char/diag/diag_masks.c @@ -1196,7 +1196,7 @@ static int diag_cmd_get_log_mask(unsigned char *src_buf, int src_len, int rsp_header_len = sizeof(struct diag_log_config_rsp_t); uint32_t mask_size = 0; struct diag_log_mask_t *log_item = NULL; - struct diag_log_config_req_t *req; + struct diag_log_config_get_req_t *req; struct diag_log_config_rsp_t rsp; struct diag_mask_info *mask_info = NULL; struct diag_md_session_t *info = NULL; @@ -1206,7 +1206,7 @@ static int diag_cmd_get_log_mask(unsigned char *src_buf, int src_len, mask_info = (!info) ? &log_mask : info->log_mask; if (!src_buf || !dest_buf || dest_len <= 0 || !mask_info || - src_len < sizeof(struct diag_log_config_req_t)) { + src_len < sizeof(struct diag_log_config_get_req_t)) { pr_err("diag: Invalid input in %s, src_buf: %pK, src_len: %d, dest_buf: %pK, dest_len: %d, mask_info: %pK\n", __func__, src_buf, src_len, dest_buf, dest_len, mask_info); @@ -1225,7 +1225,7 @@ static int diag_cmd_get_log_mask(unsigned char *src_buf, int src_len, return 0; } - req = (struct diag_log_config_req_t *)src_buf; + req = (struct diag_log_config_get_req_t *)src_buf; read_len += req_header_len; rsp.cmd_code = DIAG_CMD_LOG_CONFIG; @@ -2303,6 +2303,8 @@ int diag_process_apps_masks(unsigned char *buf, int len, int pid) return -EINVAL; if (*buf == DIAG_CMD_LOG_CONFIG) { + if (len < (2 * sizeof(int))) + return -EINVAL; sub_cmd = *(int *)(buf + sizeof(int)); switch (sub_cmd) { case DIAG_CMD_OP_LOG_DISABLE: @@ -2320,6 +2322,8 @@ int diag_process_apps_masks(unsigned char *buf, int len, int pid) break; } } else if (*buf == DIAG_CMD_MSG_CONFIG) { + if (len < (2 * sizeof(uint8_t))) + return -EINVAL; sub_cmd = *(uint8_t *)(buf + sizeof(uint8_t)); switch (sub_cmd) { case DIAG_CMD_OP_GET_SSID_RANGE: @@ -2401,4 +2405,3 @@ void diag_masks_exit(void) diag_event_mask_exit(); kfree(driver->buf_feature_mask_update); } - diff --git a/drivers/char/diag/diag_pcie.c b/drivers/char/diag/diag_pcie.c index dbb20f951e15..bf048c1e0b27 100644 --- a/drivers/char/diag/diag_pcie.c +++ b/drivers/char/diag/diag_pcie.c @@ -593,6 +593,7 @@ void diag_pcie_disconnect_all(void) void diag_pcie_close_work_fn(struct work_struct *work) { + int rc = 0; struct diag_pcie_info *pcie_info = container_of(work, struct diag_pcie_info, open_work); @@ -601,10 +602,10 @@ void diag_pcie_close_work_fn(struct work_struct *work) return; mutex_lock(&pcie_info->out_chan_lock); mutex_lock(&pcie_info->in_chan_lock); - mhi_dev_close_channel(pcie_info->in_handle); + rc = mhi_dev_close_channel(pcie_info->in_handle); DIAG_LOG(DIAG_DEBUG_MUX, " closed in bound channel %d", pcie_info->in_chan); - mhi_dev_close_channel(pcie_info->out_handle); + rc = mhi_dev_close_channel(pcie_info->out_handle); DIAG_LOG(DIAG_DEBUG_MUX, " closed out bound channel %d", pcie_info->out_chan); mutex_unlock(&pcie_info->in_chan_lock); @@ -656,4 +657,3 @@ int diag_pcie_register(int id, int ctxt, struct diag_mux_ops *ops) } return 0; } - diff --git a/drivers/char/diag/diagfwd_socket.h b/drivers/char/diag/diagfwd_socket.h index 9a2e7b7f2d5e..af64dcd04ac1 100644 --- a/drivers/char/diag/diagfwd_socket.h +++ b/drivers/char/diag/diagfwd_socket.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2015-2017, 2019, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2017, 2019-2020, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -37,7 +37,7 @@ enum { SOCKET_ADSP, SOCKET_WCNSS, SOCKET_SLPI, - SOCKET_CDSP, + SOCKET_CDSP = 5, SOCKET_APPS, NUM_SOCKET_SUBSYSTEMS, }; @@ -109,4 +109,3 @@ void diag_socket_early_exit(void); void diag_socket_invalidate(void *ctxt, struct diagfwd_info *fwd_ctxt); int diag_socket_check_state(void *ctxt); #endif - diff --git a/drivers/char/frandom.c b/drivers/char/frandom.c deleted file mode 100644 index b80548275f61..000000000000 --- a/drivers/char/frandom.c +++ /dev/null @@ -1,415 +0,0 @@ -/* -** frandom.c -** Fast pseudo-random generator -** -** (c) Copyright 2003-2011 Eli Billauer -** http://www.billauer.co.il -** -** This program is free software; you can redistribute it and/or modify -** it under the terms of the GNU General Public License as published by -** the Free Software Foundation; either version 2 of the License, or -** (at your option) any later version. -** -** -*/ - -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#define INTERNAL_SEED 0 -#define EXTERNAL_SEED 1 - -#define FRANDOM_MAJOR 235 -#define FRANDOM_MINOR 11 -#define ERANDOM_MINOR 12 - -static struct file_operations frandom_fops; /* Values assigned below */ - -static int erandom_seeded = 0; /* Internal flag */ - -static int frandom_major = FRANDOM_MAJOR; -static int frandom_minor = FRANDOM_MINOR; -static int erandom_minor = ERANDOM_MINOR; -static int frandom_bufsize = 256; -static int frandom_chunklimit = 0; /* =0 means unlimited */ - -static struct cdev frandom_cdev; -static struct cdev erandom_cdev; -static struct class *frandom_class; -struct device *frandom_device; -struct device *erandom_device; - -MODULE_DESCRIPTION("Fast pseudo-random number generator"); -MODULE_LICENSE("GPL"); -MODULE_AUTHOR("Eli Billauer"); -module_param(frandom_major, int, 0); -module_param(frandom_minor, int, 0); -module_param(erandom_minor, int, 0); -module_param(frandom_bufsize, int, 0); -module_param(frandom_chunklimit, int, 0); - -MODULE_PARM_DESC(frandom_major,"Major number of /dev/frandom and /dev/erandom"); -MODULE_PARM_DESC(frandom_minor,"Minor number of /dev/frandom"); -MODULE_PARM_DESC(erandom_minor,"Minor number of /dev/erandom"); -MODULE_PARM_DESC(frandom_bufsize,"Internal buffer size in bytes. Default is 256. Must be >= 256"); -MODULE_PARM_DESC(frandom_chunklimit,"Limit for read() blocks size. 0 (default) is unlimited, otherwise must be >= 256"); - -struct frandom_state -{ - struct semaphore sem; /* Semaphore on the state structure */ - - u8 S[256]; /* The state array */ - u8 i; - u8 j; - - char *buf; -}; - -static struct frandom_state *erandom_state; - -static inline void swap_byte(u8 *a, u8 *b) -{ - u8 swapByte; - - swapByte = *a; - *a = *b; - *b = swapByte; -} - -static void init_rand_state(struct frandom_state *state, int seedflag); - -void erandom_get_random_bytes(char *buf, size_t count) -{ - struct frandom_state *state = erandom_state; - int k; - - unsigned int i; - unsigned int j; - u8 *S; - - /* If we fail to get the semaphore, we revert to external random data. - Since semaphore blocking is expected to be very rare, and interrupts - during these rare and very short periods of time even less frequent, - we take the better-safe-than-sorry approach, and fill the buffer - some expensive random data, in case the caller wasn't aware of this - possibility, and expects random data anyhow. - */ - - if (down_interruptible(&state->sem)) { - get_random_bytes(buf, count); - return; - } - - /* We seed erandom as late as possible, hoping that the kernel's main - RNG is already restored in the boot sequence (not critical, but - better. - */ - - if (!erandom_seeded) { - erandom_seeded = 1; - init_rand_state(state, EXTERNAL_SEED); - printk(KERN_INFO "frandom: Seeded global generator now (used by erandom)\n"); - } - - i = state->i; - j = state->j; - S = state->S; - - for (k=0; ki = i; - state->j = j; - - up(&state->sem); -} - -static void init_rand_state(struct frandom_state *state, int seedflag) -{ - unsigned int i, j, k; - u8 *S; - u8 *seed = state->buf; - - if (seedflag == INTERNAL_SEED) - erandom_get_random_bytes(seed, 256); - else - get_random_bytes(seed, 256); - - S = state->S; - for (i=0; i<256; i++) - *S++=i; - - j=0; - S = state->S; - - for (i=0; i<256; i++) { - j = (j + S[i] + *seed++) & 0xff; - swap_byte(&S[i], &S[j]); - } - - /* It's considered good practice to discard the first 256 bytes - generated. So we do it: - */ - - i=0; j=0; - for (k=0; k<256; k++) { - i = (i + 1) & 0xff; - j = (j + S[i]) & 0xff; - swap_byte(&S[i], &S[j]); - } - - state->i = i; /* Save state */ - state->j = j; -} - -static int frandom_open(struct inode *inode, struct file *filp) -{ - - struct frandom_state *state; - - int num = iminor(inode); - - /* This should never happen, now when the minors are regsitered - * explicitly - */ - if ((num != frandom_minor) && (num != erandom_minor)) return -ENODEV; - - state = kmalloc(sizeof(struct frandom_state), GFP_KERNEL); - if (!state) - return -ENOMEM; - - state->buf = kmalloc(frandom_bufsize, GFP_KERNEL); - if (!state->buf) { - kfree(state); - return -ENOMEM; - } - - sema_init(&state->sem, 1); /* Init semaphore as a mutex */ - - if (num == frandom_minor) - init_rand_state(state, EXTERNAL_SEED); - else - init_rand_state(state, INTERNAL_SEED); - - filp->private_data = state; - - return 0; /* Success */ -} - -static int frandom_release(struct inode *inode, struct file *filp) -{ - - struct frandom_state *state = filp->private_data; - - kfree(state->buf); - kfree(state); - - return 0; -} - -static ssize_t frandom_read(struct file *filp, char *buf, size_t count, - loff_t *f_pos) -{ - struct frandom_state *state = filp->private_data; - ssize_t ret; - int dobytes, k; - char *localbuf; - - unsigned int i; - unsigned int j; - u8 *S; - - if (down_interruptible(&state->sem)) - return -ERESTARTSYS; - - if ((frandom_chunklimit > 0) && (count > frandom_chunklimit)) - count = frandom_chunklimit; - - ret = count; /* It's either everything or an error... */ - - i = state->i; - j = state->j; - S = state->S; - - while (count) { - if (count > frandom_bufsize) - dobytes = frandom_bufsize; - else - dobytes = count; - - localbuf = state->buf; - - for (k=0; kbuf, dobytes)) { - ret = -EFAULT; - goto out; - } - - buf += dobytes; - count -= dobytes; - } - - out: - state->i = i; - state->j = j; - - up(&state->sem); - return ret; -} - -static struct file_operations frandom_fops = { - read: frandom_read, - open: frandom_open, - release: frandom_release, -}; - -static void frandom_cleanup_module(void) { - unregister_chrdev_region(MKDEV(frandom_major, erandom_minor), 1); - cdev_del(&erandom_cdev); - device_destroy(frandom_class, MKDEV(frandom_major, erandom_minor)); - - unregister_chrdev_region(MKDEV(frandom_major, frandom_minor), 1); - cdev_del(&frandom_cdev); - device_destroy(frandom_class, MKDEV(frandom_major, frandom_minor)); - class_destroy(frandom_class); - - kfree(erandom_state->buf); - kfree(erandom_state); -} - - -static int frandom_init_module(void) -{ - int result; - - /* The buffer size MUST be at least 256 bytes, because we assume that - minimal length in init_rand_state(). - */ - if (frandom_bufsize < 256) { - printk(KERN_ERR "frandom: Refused to load because frandom_bufsize=%d < 256\n",frandom_bufsize); - return -EINVAL; - } - if ((frandom_chunklimit != 0) && (frandom_chunklimit < 256)) { - printk(KERN_ERR "frandom: Refused to load because frandom_chunklimit=%d < 256 and != 0\n",frandom_chunklimit); - return -EINVAL; - } - - erandom_state = kmalloc(sizeof(struct frandom_state), GFP_KERNEL); - if (!erandom_state) - return -ENOMEM; - - /* This specific buffer is only used for seeding, so we need - 256 bytes exactly */ - erandom_state->buf = kmalloc(256, GFP_KERNEL); - if (!erandom_state->buf) { - kfree(erandom_state); - return -ENOMEM; - } - - sema_init(&erandom_state->sem, 1); /* Init semaphore as a mutex */ - - erandom_seeded = 0; - - frandom_class = class_create(THIS_MODULE, "fastrng"); - if (IS_ERR(frandom_class)) { - result = PTR_ERR(frandom_class); - printk(KERN_WARNING "frandom: Failed to register class fastrng\n"); - goto error0; - } - - /* - * Register your major, and accept a dynamic number. This is the - * first thing to do, in order to avoid releasing other module's - * fops in frandom_cleanup_module() - */ - - cdev_init(&frandom_cdev, &frandom_fops); - frandom_cdev.owner = THIS_MODULE; - result = cdev_add(&frandom_cdev, MKDEV(frandom_major, frandom_minor), 1); - if (result) { - printk(KERN_WARNING "frandom: Failed to add cdev for /dev/frandom\n"); - goto error1; - } - - result = register_chrdev_region(MKDEV(frandom_major, frandom_minor), 1, "/dev/frandom"); - if (result < 0) { - printk(KERN_WARNING "frandom: can't get major/minor %d/%d\n", frandom_major, frandom_minor); - goto error2; - } - - frandom_device = device_create(frandom_class, NULL, MKDEV(frandom_major, frandom_minor), NULL, "frandom"); - - if (IS_ERR(frandom_device)) { - printk(KERN_WARNING "frandom: Failed to create frandom device\n"); - goto error3; - } - - cdev_init(&erandom_cdev, &frandom_fops); - erandom_cdev.owner = THIS_MODULE; - result = cdev_add(&erandom_cdev, MKDEV(frandom_major, erandom_minor), 1); - if (result) { - printk(KERN_WARNING "frandom: Failed to add cdev for /dev/erandom\n"); - goto error4; - } - - result = register_chrdev_region(MKDEV(frandom_major, erandom_minor), 1, "/dev/erandom"); - if (result < 0) { - printk(KERN_WARNING "frandom: can't get major/minor %d/%d\n", frandom_major, erandom_minor); - goto error5; - } - - erandom_device = device_create(frandom_class, NULL, MKDEV(frandom_major, erandom_minor), NULL, "erandom"); - - if (IS_ERR(erandom_device)) { - printk(KERN_WARNING "frandom: Failed to create erandom device\n"); - goto error6; - } - return 0; /* succeed */ - - error6: - unregister_chrdev_region(MKDEV(frandom_major, erandom_minor), 1); - error5: - cdev_del(&erandom_cdev); - error4: - device_destroy(frandom_class, MKDEV(frandom_major, frandom_minor)); - error3: - unregister_chrdev_region(MKDEV(frandom_major, frandom_minor), 1); - error2: - cdev_del(&frandom_cdev); - error1: - class_destroy(frandom_class); - error0: - kfree(erandom_state->buf); - kfree(erandom_state); - - return result; -} - -module_init(frandom_init_module); -module_exit(frandom_cleanup_module); - -EXPORT_SYMBOL(erandom_get_random_bytes); diff --git a/drivers/char/random.c b/drivers/char/random.c index 4b0edcdc78ef..2636f495603c 100755 --- a/drivers/char/random.c +++ b/drivers/char/random.c @@ -2119,8 +2119,8 @@ struct batched_entropy { /* * Get a random word for internal kernel use only. The quality of the random - * number is either as good as RDRAND or as good as /dev/urandom, with the - * goal of being quite fast and not depleting entropy. + * number is good as /dev/urandom, but there is no backtrack protection, with + * the goal of being quite fast and not depleting entropy. */ static DEFINE_PER_CPU(struct batched_entropy, batched_entropy_u64); u64 get_random_u64(void) @@ -2128,15 +2128,6 @@ u64 get_random_u64(void) u64 ret; struct batched_entropy *batch; -#if BITS_PER_LONG == 64 - if (arch_get_random_long((unsigned long *)&ret)) - return ret; -#else - if (arch_get_random_long((unsigned long *)&ret) && - arch_get_random_long((unsigned long *)&ret + 1)) - return ret; -#endif - batch = &get_cpu_var(batched_entropy_u64); if (batch->position % ARRAY_SIZE(batch->entropy_u64) == 0) { extract_crng((u8 *)batch->entropy_u64); @@ -2154,9 +2145,6 @@ u32 get_random_u32(void) u32 ret; struct batched_entropy *batch; - if (arch_get_random_int(&ret)) - return ret; - batch = &get_cpu_var(batched_entropy_u32); if (batch->position % ARRAY_SIZE(batch->entropy_u32) == 0) { extract_crng((u8 *)batch->entropy_u32); diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c index 3f40eafff39c..80b2e06d973d 100644 --- a/drivers/clk/qcom/clk-rcg2.c +++ b/drivers/clk/qcom/clk-rcg2.c @@ -128,7 +128,7 @@ static int update_config(struct clk_rcg2 *rcg) udelay(1); } - WARN(1, "%s: rcg didn't update its configuration.", name); + WARN(1, "clk: %s: rcg didn't update its configuration.", name); return -EBUSY; } @@ -1468,4 +1468,3 @@ int clk_rcg2_get_dfs_clock_rate(struct clk_rcg2 *clk, struct device *dev, err: return ret; } - diff --git a/drivers/cpufreq/cpu-boost.c b/drivers/cpufreq/cpu-boost.c index c13c7aa02baf..6a4008c1c526 100644 --- a/drivers/cpufreq/cpu-boost.c +++ b/drivers/cpufreq/cpu-boost.c @@ -1,6 +1,5 @@ /* * Copyright (c) 2013-2015,2017, The Linux Foundation. All rights reserved. - * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -28,33 +27,21 @@ struct cpu_sync { int cpu; unsigned int input_boost_min; unsigned int input_boost_freq; - unsigned int powerkey_input_boost_freq; -}; - -enum input_boost_type { - default_input_boost, - powerkey_input_boost }; static DEFINE_PER_CPU(struct cpu_sync, sync_info); static struct workqueue_struct *cpu_boost_wq; static struct work_struct input_boost_work; -static struct work_struct powerkey_input_boost_work; + static bool input_boost_enabled; static unsigned int input_boost_ms = 40; module_param(input_boost_ms, uint, 0644); -static unsigned int powerkey_input_boost_ms = 400; -module_param(powerkey_input_boost_ms, uint, 0644); - static unsigned int sched_boost_on_input; module_param(sched_boost_on_input, uint, 0644); -static bool sched_boost_on_powerkey_input = true; -module_param(sched_boost_on_powerkey_input, bool, 0644); - static bool sched_boost_active; static struct delayed_work input_boost_rem; @@ -67,12 +54,6 @@ static int set_input_boost_freq(const char *buf, const struct kernel_param *kp) unsigned int val, cpu; const char *cp = buf; bool enabled = false; - enum input_boost_type type; - - if (strstr(kp->name, "input_boost_freq")) - type = default_input_boost; - if (strstr(kp->name, "powerkey_input_boost_freq")) - type = powerkey_input_boost; while ((cp = strpbrk(cp + 1, " :"))) ntokens++; @@ -81,12 +62,8 @@ static int set_input_boost_freq(const char *buf, const struct kernel_param *kp) if (!ntokens) { if (sscanf(buf, "%u\n", &val) != 1) return -EINVAL; - for_each_possible_cpu(i) { - if (type == default_input_boost) - per_cpu(sync_info, i).input_boost_freq = val; - else if (type == powerkey_input_boost) - per_cpu(sync_info, i).powerkey_input_boost_freq = val; - } + for_each_possible_cpu(i) + per_cpu(sync_info, i).input_boost_freq = val; goto check_enable; } @@ -101,18 +78,14 @@ static int set_input_boost_freq(const char *buf, const struct kernel_param *kp) if (cpu >= num_possible_cpus()) return -EINVAL; - if (type == default_input_boost) - per_cpu(sync_info, cpu).input_boost_freq = val; - else if (type == powerkey_input_boost) - per_cpu(sync_info, cpu).powerkey_input_boost_freq = val; + per_cpu(sync_info, cpu).input_boost_freq = val; cp = strchr(cp, ' '); cp++; } check_enable: for_each_possible_cpu(i) { - if (per_cpu(sync_info, i).input_boost_freq - || per_cpu(sync_info, i).powerkey_input_boost_freq) { + if (per_cpu(sync_info, i).input_boost_freq) { enabled = true; break; } @@ -126,22 +99,11 @@ static int get_input_boost_freq(char *buf, const struct kernel_param *kp) { int cnt = 0, cpu; struct cpu_sync *s; - unsigned int boost_freq = 0; - enum input_boost_type type; - - if (strstr(kp->name, "input_boost_freq")) - type = default_input_boost; - if (strstr(kp->name, "powerkey_input_boost_freq")) - type = powerkey_input_boost; for_each_possible_cpu(cpu) { s = &per_cpu(sync_info, cpu); - if (type == default_input_boost) - boost_freq = s->input_boost_freq; - else if (type == powerkey_input_boost) - boost_freq = s->powerkey_input_boost_freq; cnt += snprintf(buf + cnt, PAGE_SIZE - cnt, - "%d:%u ", cpu, boost_freq); + "%d:%u ", cpu, s->input_boost_freq); } cnt += snprintf(buf + cnt, PAGE_SIZE - cnt, "\n"); return cnt; @@ -153,8 +115,6 @@ static const struct kernel_param_ops param_ops_input_boost_freq = { }; module_param_cb(input_boost_freq, ¶m_ops_input_boost_freq, NULL, 0644); -module_param_cb(powerkey_input_boost_freq, ¶m_ops_input_boost_freq, NULL, 0644); - /* * The CPUFREQ_ADJUST notifier is used to override the current policy min to * make sure policy min >= boost_min. The cpufreq framework then does the job @@ -261,40 +221,6 @@ static void do_input_boost(struct work_struct *work) msecs_to_jiffies(input_boost_ms)); } -static void do_powerkey_input_boost(struct work_struct *work) -{ - - unsigned int i, ret; - struct cpu_sync *i_sync_info; - cancel_delayed_work_sync(&input_boost_rem); - if (sched_boost_active) { - sched_set_boost(0); - sched_boost_active = false; - } - - /* Set the powerkey_input_boost_min for all CPUs in the system */ - pr_debug("Setting powerkey input boost min for all CPUs\n"); - for_each_possible_cpu(i) { - i_sync_info = &per_cpu(sync_info, i); - i_sync_info->input_boost_min = i_sync_info->powerkey_input_boost_freq; - } - - /* Update policies for all online CPUs */ - update_policy_online(); - - /* Enable scheduler boost to migrate tasks to big cluster */ - if (sched_boost_on_powerkey_input) { - ret = sched_set_boost(1); - if (ret) - pr_err("cpu-boost: HMP boost enable failed\n"); - else - sched_boost_active = true; - } - - queue_delayed_work(cpu_boost_wq, &input_boost_rem, - msecs_to_jiffies(powerkey_input_boost_ms)); -} - static void cpuboost_input_event(struct input_handle *handle, unsigned int type, unsigned int code, int value) { @@ -310,11 +236,7 @@ static void cpuboost_input_event(struct input_handle *handle, if (work_pending(&input_boost_work)) return; - if (type == EV_KEY && code == KEY_POWER) { - queue_work(cpu_boost_wq, &powerkey_input_boost_work); - } else { - queue_work(cpu_boost_wq, &input_boost_work); - } + queue_work(cpu_boost_wq, &input_boost_work); last_input_time = ktime_to_us(ktime_get()); } @@ -399,7 +321,6 @@ static int cpu_boost_init(void) return -EFAULT; INIT_WORK(&input_boost_work, do_input_boost); - INIT_WORK(&powerkey_input_boost_work, do_powerkey_input_boost); INIT_DELAYED_WORK(&input_boost_rem, do_input_boost_rem); for_each_possible_cpu(cpu) { diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c index fa6b0110479b..1667bc0e7b50 100644 --- a/drivers/cpufreq/cpufreq.c +++ b/drivers/cpufreq/cpufreq.c @@ -2,7 +2,6 @@ * linux/drivers/cpufreq/cpufreq.c * * Copyright (C) 2001 Russell King - * Copyright (C) 2018 XiaoMi, Inc. * (C) 2002 - 2003 Dominik Brodowski * (C) 2013 Viresh Kumar * @@ -778,9 +777,6 @@ static ssize_t store_##file_name \ new_policy.max = policy->user_policy.max; \ \ new_policy.min = new_policy.user_policy.min; \ - new_policy.max = new_policy.user_policy.max; \ - \ - new_policy.min = new_policy.user_policy.min; \ new_policy.max = new_policy.user_policy.max; \ \ ret = sscanf(buf, "%u", &new_policy.object); \ diff --git a/drivers/cpuidle/cpuidle.c b/drivers/cpuidle/cpuidle.c index edc9875c96c8..3eddf4375929 100644 --- a/drivers/cpuidle/cpuidle.c +++ b/drivers/cpuidle/cpuidle.c @@ -218,17 +218,17 @@ int cpuidle_enter_state(struct cpuidle_device *dev, struct cpuidle_driver *drv, if (!cpuidle_state_is_coupled(drv, index)) local_irq_enable(); + diff = ktime_us_delta(time_end, time_start); + if (diff > INT_MAX) + diff = INT_MAX; + + dev->last_residency = (int) diff; + if (entered_state >= 0) { - /* - * Update cpuidle counters - * This can be moved to within driver enter routine, + /* Update cpuidle counters */ + /* This can be moved to within driver enter routine * but that results in multiple copies of same code. */ - diff = ktime_us_delta(time_end, time_start); - if (diff > INT_MAX) - diff = INT_MAX; - - dev->last_residency = (int)diff; dev->states_usage[entered_state].time += dev->last_residency; dev->states_usage[entered_state].usage++; } else { diff --git a/drivers/cpuidle/lpm-levels.c b/drivers/cpuidle/lpm-levels.c index 4d074204cdd9..88d061d11cd2 100644 --- a/drivers/cpuidle/lpm-levels.c +++ b/drivers/cpuidle/lpm-levels.c @@ -39,6 +39,7 @@ #include #include #include +#include #include #include #include @@ -57,6 +58,30 @@ #define PSCI_AFFINITY_LEVEL(lvl) ((lvl & 0x3) << 24) #define BIAS_HYST (bias_hyst * NSEC_PER_MSEC) +enum { + MSM_LPM_LVL_DBG_SUSPEND_LIMITS = BIT(0), + MSM_LPM_LVL_DBG_IDLE_LIMITS = BIT(1), +}; + +enum debug_event { + CPU_ENTER, + CPU_EXIT, + CLUSTER_ENTER, + CLUSTER_EXIT, + CPU_HP_STARTING, + CPU_HP_DYING, +}; + +struct lpm_debug { + cycle_t time; + enum debug_event evt; + int cpu; + uint32_t arg1; + uint32_t arg2; + uint32_t arg3; + uint32_t arg4; +}; + static struct system_pm_ops *sys_pm_ops; static DEFINE_SPINLOCK(bc_timer_lock); @@ -86,6 +111,9 @@ static DEFINE_PER_CPU(struct lpm_cpu*, cpu_lpm); static bool suspend_in_progress; static struct hrtimer lpm_hrtimer; static DEFINE_PER_CPU(struct hrtimer, histtimer); +static struct lpm_debug *lpm_debug; +static phys_addr_t lpm_debug_phys; +static const int num_dbg_elements = 0x100; static void cluster_unprepare(struct lpm_cluster *cluster, const struct cpumask *cpu, int child_idx, bool from_idle, @@ -100,9 +128,6 @@ module_param_named(print_parsed_dt, print_parsed_dt, bool, 0664); static bool sleep_disabled; module_param_named(sleep_disabled, sleep_disabled, bool, 0664); -static bool sleep_disabled_touch; -module_param_named(sleep_disabled_touch, sleep_disabled_touch, bool, 0664); - /** * msm_cpuidle_get_deep_idle_latency - Get deep idle latency value * @@ -124,13 +149,6 @@ uint32_t register_system_pm_ops(struct system_pm_ops *pm_ops) return 0; } -void lpm_disable_for_input(bool on) -{ - sleep_disabled_touch = !!on; - return; -} -EXPORT_SYMBOL(lpm_disable_for_input); - static uint32_t least_cluster_latency(struct lpm_cluster *cluster, struct latency_level *lat_level) { @@ -267,10 +285,38 @@ int lpm_get_latency(struct latency_level *level, uint32_t *latency) } EXPORT_SYMBOL(lpm_get_latency); +static void update_debug_pc_event(enum debug_event event, uint32_t arg1, + uint32_t arg2, uint32_t arg3, uint32_t arg4) +{ + struct lpm_debug *dbg; + int idx; + static DEFINE_SPINLOCK(debug_lock); + static int pc_event_index; + + if (!lpm_debug) + return; + + spin_lock(&debug_lock); + idx = pc_event_index++; + dbg = &lpm_debug[idx & (num_dbg_elements - 1)]; + + dbg->evt = event; + dbg->time = arch_counter_get_cntvct(); + dbg->cpu = raw_smp_processor_id(); + dbg->arg1 = arg1; + dbg->arg2 = arg2; + dbg->arg3 = arg3; + dbg->arg4 = arg4; + spin_unlock(&debug_lock); +} + static int lpm_dying_cpu(unsigned int cpu) { struct lpm_cluster *cluster = per_cpu(cpu_lpm, cpu)->parent; + update_debug_pc_event(CPU_HP_DYING, cpu, + cluster->num_children_in_sync.bits[0], + cluster->child_cpus.bits[0], false); cluster_prepare(cluster, get_cpu_mask(cpu), NR_LPM_LEVELS, false, 0); return 0; } @@ -279,6 +325,9 @@ static int lpm_starting_cpu(unsigned int cpu) { struct lpm_cluster *cluster = per_cpu(cpu_lpm, cpu)->parent; + update_debug_pc_event(CPU_HP_STARTING, cpu, + cluster->num_children_in_sync.bits[0], + cluster->child_cpus.bits[0], false); cluster_unprepare(cluster, get_cpu_mask(cpu), NR_LPM_LEVELS, false, 0, true); return 0; @@ -572,7 +621,7 @@ static int cpu_power_select(struct cpuidle_device *dev, uint32_t *min_residency = get_per_cpu_min_residency(dev->cpu); uint32_t *max_residency = get_per_cpu_max_residency(dev->cpu); - if (((sleep_disabled || sleep_disabled_touch) && !cpu_isolated(dev->cpu)) || sleep_us < 0) + if ((sleep_disabled && !cpu_isolated(dev->cpu)) || sleep_us < 0) return best_level; idx_restrict = cpu->nlevels + 1; @@ -992,6 +1041,9 @@ static int cluster_configure(struct lpm_cluster *cluster, int idx, } if (idx != cluster->default_level) { + update_debug_pc_event(CLUSTER_ENTER, idx, + cluster->num_children_in_sync.bits[0], + cluster->child_cpus.bits[0], from_idle); trace_cluster_enter(cluster->cluster_name, idx, cluster->num_children_in_sync.bits[0], cluster->child_cpus.bits[0], from_idle); @@ -1162,6 +1214,9 @@ static void cluster_unprepare(struct lpm_cluster *cluster, spin_unlock(&bc_timer_lock); } + update_debug_pc_event(CLUSTER_EXIT, cluster->last_level, + cluster->num_children_in_sync.bits[0], + cluster->child_cpus.bits[0], from_idle); trace_cluster_exit(cluster->cluster_name, cluster->last_level, cluster->num_children_in_sync.bits[0], cluster->child_cpus.bits[0], from_idle); @@ -1284,11 +1339,15 @@ static bool psci_enter_sleep(struct lpm_cpu *cpu, int idx, bool from_idle) affinity_level = PSCI_AFFINITY_LEVEL(affinity_level); state_id += power_state + affinity_level + cpu->levels[idx].psci_id; + update_debug_pc_event(CPU_ENTER, state_id, + 0xdeaffeed, 0xdeaffeed, from_idle); stop_critical_timings(); success = !arm_cpuidle_suspend(state_id); start_critical_timings(); + update_debug_pc_event(CPU_EXIT, state_id, + success, 0xdeaffeed, from_idle); if (from_idle && cpu->levels[idx].use_bc_timer) tick_broadcast_exit(); @@ -1649,9 +1708,11 @@ static const struct platform_freeze_ops lpm_freeze_ops = { static int lpm_probe(struct platform_device *pdev) { int ret; + int size; unsigned int cpu; struct hrtimer *cpu_histtimer; struct kobject *module_kobj = NULL; + struct md_region md_entry; get_online_cpus(); lpm_root_node = lpm_of_parse_cluster(pdev); @@ -1681,6 +1742,10 @@ static int lpm_probe(struct platform_device *pdev) cluster_timer_init(lpm_root_node); + size = num_dbg_elements * sizeof(struct lpm_debug); + lpm_debug = dma_alloc_coherent(&pdev->dev, size, + &lpm_debug_phys, GFP_KERNEL); + register_cluster_lpm_stats(lpm_root_node, NULL); ret = cluster_cpuidle_register(lpm_root_node); @@ -1709,6 +1774,14 @@ static int lpm_probe(struct platform_device *pdev) goto failed; } + /* Add lpm_debug to Minidump*/ + strlcpy(md_entry.name, "KLPMDEBUG", sizeof(md_entry.name)); + md_entry.virt_addr = (uintptr_t)lpm_debug; + md_entry.phys_addr = lpm_debug_phys; + md_entry.size = size; + if (msm_minidump_add_region(&md_entry) < 0) + pr_info("Failed to add lpm_debug in Minidump\n"); + return 0; failed: free_cluster_node(lpm_root_node); diff --git a/drivers/crypto/msm/qce50.c b/drivers/crypto/msm/qce50.c index 0fd3bbf0961e..1ef53821060c 100644 --- a/drivers/crypto/msm/qce50.c +++ b/drivers/crypto/msm/qce50.c @@ -4680,7 +4680,7 @@ static int select_mode(struct qce_device *pce_dev, pce_dev->intr_cadence = 0; atomic_set(&pce_dev->bunch_cmd_seq, 0); atomic_set(&pce_dev->last_intr_seq, 0); - pce_dev->cadence_flag = !pce_dev->cadence_flag; + pce_dev->cadence_flag = ~pce_dev->cadence_flag; } } diff --git a/drivers/gps/bbd.c b/drivers/gps/bbd.c index 37e8f618de10..097e7a1769c3 100644 --- a/drivers/gps/bbd.c +++ b/drivers/gps/bbd.c @@ -39,6 +39,7 @@ #ifdef CONFIG_SENSORS_SSP #include + extern struct spi_driver *pssp_driver; extern bool ssp_dbg; extern bool ssp_pkt_dbg; @@ -50,17 +51,19 @@ static struct spi_device dummy_spi = { }; #endif +#ifdef CONFIG_BCM_GPS_SPI_DRIVER extern bool ssi_dbg; extern bool ssi_dbg_pzc; extern bool ssi_dbg_rng; +#endif void bbd_log_hex(const char*, const unsigned char*, unsigned long); -//-------------------------------------------------------------- -// -// BBD device struct -// -//-------------------------------------------------------------- + + + + + #define BBD_BUFF_SIZE (PAGE_SIZE*2) struct bbd_cdev_priv { const char *name; @@ -94,15 +97,15 @@ static const char *bbd_dev_name[BBD_DEVICE_INDEX] = { "bbd_sensor", "bbd_control", "bbd_patch", + }; static dev_t devno; -//-------------------------------------------------------------- -// -// Globals -// -//-------------------------------------------------------------- + + + + /* * The global BBD device which has all necessary information. * It's not beautiful but useful when we debug by Trace32. @@ -112,6 +115,11 @@ static struct bbd_device bbd; * Embedded patch file provided as /dev/bbd_patch */ static unsigned char bbd_patch[] = { +#ifdef CONFIG_POP + +#else + +#endif }; #ifdef CONFIG_SENSORS_BBD_LEGACY_PATCH @@ -128,11 +136,11 @@ static unsigned char legacy_bbd_patch[] = { ssize_t bbd_on_read(unsigned int minor, const unsigned char *buf, size_t size); -//-------------------------------------------------------------- -// -// SHMD Interface Functions -// -//-------------------------------------------------------------- + + + + + /** * bbd_register -Interface function called from SHMD @@ -163,7 +171,7 @@ EXPORT_SYMBOL(bbd_register); */ struct sensor_pkt { unsigned short size; - unsigned char buf[1022]; /* We assume max SSP packet less than 1KB */ + unsigned char buf[1022]; /*We assume max SSP packet less than 1KB */ } __attribute__((__packed__)) ss_pkt; ssize_t bbd_send_packet(unsigned char *buf, size_t size) @@ -251,11 +259,11 @@ EXPORT_SYMBOL(bbd_mcu_reset); -//-------------------------------------------------------------- -// -// BBD device struct -// -//-------------------------------------------------------------- + + + + + /** * bbd_control - Handles command string from lhd @@ -270,13 +278,17 @@ ssize_t bbd_control(const char *buf, ssize_t len) if (bbd.ssp_cb && bbd.ssp_cb->on_mcu_ready) bbd.ssp_cb->on_mcu_ready(bbd.ssp_priv, true); +#ifdef CONFIG_BCM_GPS_SPI_DRIVER bcm477x_debug_info(ESW_CTRL_READY); +#endif } else if (strnstr(buf, ESW_CTRL_NOTREADY, strlen(buf))) { struct circ_buf *circ = &bbd.priv[BBD_MINOR_SENSOR].read_buf; circ->head = circ->tail = 0; if (bbd.ssp_cb && bbd.ssp_cb->on_mcu_ready) bbd.ssp_cb->on_mcu_ready(bbd.ssp_priv, false); +#ifdef CONFIG_BCM_GPS_SPI_DRIVER bcm477x_debug_info(ESW_CTRL_NOTREADY); +#endif } else if (strnstr(buf, ESW_CTRL_CRASHED, strlen(buf))) { struct circ_buf *circ = &bbd.priv[BBD_MINOR_SENSOR].read_buf; circ->head = circ->tail = 0; @@ -286,7 +298,13 @@ ssize_t bbd_control(const char *buf, ssize_t len) if (bbd.ssp_cb && bbd.ssp_cb->on_control) bbd.ssp_cb->on_control(bbd.ssp_priv, buf); +#ifdef CONFIG_BCM_GPS_SPI_DRIVER bcm477x_debug_info(ESW_CTRL_CRASHED); +#endif +#if 0 + } else if (strnstr(buf, BBD_CTRL_DEBUG_ON, strlen(buf))) { + bbd.db = true; +#endif } else if (strnstr(buf, BBD_CTRL_DEBUG_OFF, strlen(buf))) { bbd.db = false; #ifdef CONFIG_SENSORS_SSP @@ -297,6 +315,7 @@ ssize_t bbd_control(const char *buf, ssize_t len) ssp_dbg = false; ssp_pkt_dbg = false; #endif +#ifdef CONFIG_BCM_GPS_SPI_DRIVER } else if (strnstr(buf, SSI_DEBUG_ON, strlen(buf))) { ssi_dbg = true; } else if (strnstr(buf, SSI_DEBUG_OFF, strlen(buf))) { @@ -309,6 +328,7 @@ ssize_t bbd_control(const char *buf, ssize_t len) ssi_dbg_rng = true; } else if (strnstr(buf, RNG_DEBUG_OFF, strlen(buf))) { ssi_dbg_rng = false; +#endif } else if (bbd.ssp_cb && bbd.ssp_cb->on_control) { /* Tell SHMD about the unknown control string */ bbd.ssp_cb->on_control(bbd.ssp_priv, buf); @@ -319,11 +339,11 @@ ssize_t bbd_control(const char *buf, ssize_t len) -//-------------------------------------------------------------- -// -// BBD Common File Functions -// -//-------------------------------------------------------------- + + + + + /** * bbd_common_open - Common open function for BBD devices @@ -362,6 +382,7 @@ static int bbd_common_release(struct inode *inode, struct file *filp) { unsigned int minor = iminor(inode); + pr_info("%s++\n", __func__); BUG_ON(minor >= BBD_DEVICE_INDEX); @@ -383,6 +404,7 @@ static ssize_t bbd_common_read(struct file *filp, char __user *buf, size_t size, loff_t *ppos) { unsigned int minor = iminor(filp->f_path.dentry->d_inode); + struct circ_buf *circ = &bbd.priv[minor].read_buf; size_t rd_size = 0; @@ -427,6 +449,7 @@ static ssize_t bbd_common_write(struct file *filp, { unsigned int minor = iminor(filp->f_path.dentry->d_inode); + BUG_ON(size >= BBD_BUFF_SIZE); WARN_ON(copy_from_user(bbd.priv[minor].write_buf, buf, size)); @@ -441,6 +464,7 @@ static ssize_t bbd_common_write(struct file *filp, static unsigned int bbd_common_poll(struct file *filp, poll_table *wait) { unsigned int minor = iminor(filp->f_path.dentry->d_inode); + struct circ_buf *circ = &bbd.priv[minor].read_buf; unsigned int mask = 0; @@ -457,11 +481,11 @@ static unsigned int bbd_common_poll(struct file *filp, poll_table *wait) -//-------------------------------------------------------------- -// -// BBD Device Specific File Functions -// -//-------------------------------------------------------------- + + + + + /** * bbd_sensor_write - BBD's RPC calls this function to send sensor packet @@ -499,6 +523,7 @@ ssize_t bbd_control_write(struct file *filp, const char __user *buf, { unsigned int minor = iminor(filp->f_path.dentry->d_inode); + /* get command string first */ ssize_t len = bbd_common_write(filp, buf, size, ppos); if (len <= 0) @@ -539,11 +564,11 @@ ssize_t bbd_patch_read(struct file *filp, char __user *buf, return rd_size; } -//-------------------------------------------------------------- -// -// Sysfs -// -//-------------------------------------------------------------- + + + + + static ssize_t store_sysfs_bbd_control(struct device *dev, struct device_attribute *attr, const char *buf, size_t len) @@ -573,11 +598,11 @@ static const struct attribute_group bbd_group = { }; -//-------------------------------------------------------------- -// -// Misc Functions -// -//-------------------------------------------------------------- + + + + + void bbd_log_hex(const char *pIntroduction, const unsigned char *pData, unsigned long ulDataLen) @@ -672,14 +697,14 @@ ssize_t bbd_request_mcu(bool on) } EXPORT_SYMBOL(bbd_request_mcu); -//-------------------------------------------------------------- -// -// PM operation -// -//-------------------------------------------------------------- + + + + + static int bbd_suspend(pm_message_t state) { - pr_info("[SSPBBD]: %s ++\n", __func__); + pr_info("[SSPBBD]: %s ++ \n", __func__); #ifdef CONFIG_SENSORS_SSP /* Call SSP suspend */ @@ -688,7 +713,7 @@ static int bbd_suspend(pm_message_t state) #endif mdelay(20); - pr_info("[SSPBBD]: %s --\n", __func__); + pr_info("[SSPBBD]: %s -- \n", __func__); return 0; } @@ -725,11 +750,11 @@ static struct notifier_block bbd_notifier_block = { .notifier_call = bbd_notifier, }; -//-------------------------------------------------------------- -// -// BBD Device Init and Exit -// -//-------------------------------------------------------------- + + + + + static const struct file_operations bbd_fops[BBD_DEVICE_INDEX] = { @@ -764,6 +789,16 @@ static const struct file_operations bbd_fops[BBD_DEVICE_INDEX] = { .write = NULL, /* /dev/bbd_patch is read-only */ .poll = NULL, }, + /* bbd ssi spi debug operations + { + .owner = THIS_MODULE, + .open = bbd_common_open, + .release = bbd_common_release, + .read = NULL, + .write = bbd_ssi_spi_debug_write, + .poll = NULL, + } + */ }; @@ -815,8 +850,7 @@ int bbd_init(struct device *dev, bool legacy_patch) } /* Register cdev which relates above device - * number with this BBD device - */ + * number with this BBD device */ cdev_init(cdev, &bbd_fops[minor]); cdev->owner = THIS_MODULE; cdev->ops = &bbd_fops[minor]; @@ -837,6 +871,7 @@ int bbd_init(struct device *dev, bool legacy_patch) cdev_del(&bbd.priv[minor].dev); goto free_class; } + } /* Register sysfs entry */ @@ -911,6 +946,7 @@ static void __exit bbd_exit(void) device_destroy(bbd.class, devno); cdev_del(cdev); unregister_chrdev_region(devno, 1); + } /* Remove class */ @@ -921,3 +957,5 @@ static void __exit bbd_exit(void) MODULE_AUTHOR("Broadcom"); MODULE_LICENSE("Dual BSD/GPL"); + + diff --git a/drivers/gps/bbd.h b/drivers/gps/bbd.h index 49fd66235964..caf7a8101089 100644 --- a/drivers/gps/bbd.h +++ b/drivers/gps/bbd.h @@ -25,6 +25,7 @@ #define __BBD_H__ #pragma pack(4) + #include union long_union_t { @@ -37,11 +38,14 @@ union short_union_t { unsigned short us; }; #pragma pack() + + enum { BBD_MINOR_SHMD = 0, BBD_MINOR_SENSOR = 1, BBD_MINOR_CONTROL = 2, BBD_MINOR_PATCH = 3, + BBD_DEVICE_INDEX }; @@ -66,6 +70,7 @@ enum { #define GPSD_SENSOR_ON "GPSD:SENSOR_ON" #define GPSD_SENSOR_OFF "GPSD:SENSOR_OFF" + #define HSI_RNGDMA_RX_BASE_ADDR 0x40104040 #define HSI_RNGDMA_RX_SW_ADDR_OFFSET 0x40104050 #define HSI_RNGDMA_TX_BASE_ADDR 0x40104060 @@ -94,8 +99,9 @@ extern void bbd_parse_asic_data(unsigned char *pucData, unsigned short len, void *priv), void *priv); -extern void bcm_on_packet_received(void *_priv, unsigned char - *data, size_t size); + +#ifdef CONFIG_BCM_GPS_SPI_DRIVER extern void bcm477x_debug_info(const char *buf); +#endif #endif /* __BBD_H__ */ diff --git a/drivers/gps/bbd_rpc_lh.c b/drivers/gps/bbd_rpc_lh.c index 94c4e7955cf5..ff377817bc8f 100644 --- a/drivers/gps/bbd_rpc_lh.c +++ b/drivers/gps/bbd_rpc_lh.c @@ -1,6 +1,6 @@ /* * Copyright 2015 Broadcom Corporation - * Copyright (C) 2019 XiaoMi, Inc. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, version 2, as @@ -32,9 +32,12 @@ #include #include "bbd.h" + ssize_t bbd_sensor_write(const char *buf, unsigned int size); +void bcm_on_packet_received(void *_priv, unsigned char *data, size_t size); #else + #include #include #include @@ -64,39 +67,39 @@ ssize_t bbd_sensor_write(const unsigned char *buf, size_t size) * Note that you can also define these value from your makefile directly */ -/// if defined to 1, the reliable channel will be enabled. -// If defined to 0, it -// will be disabled and compiled out + + + #ifndef TLCUST_ENABLE_RELIABLE_PL #define TLCUST_ENABLE_RELIABLE_PL 1 #endif -// Defines the max size of outgoing packet. -// That should match the max size of incoming packet from the remote TL + + #ifndef TLCUST_MAX_OUTGOING_PACKET_SIZE #define TLCUST_MAX_OUTGOING_PACKET_SIZE 2048 #endif -// Defines the max size of incoming packet. That should match -// the max size of outgoing packet from the remote TL + + #ifndef TLCUST_MAX_INCOMING_PACKET_SIZE #define TLCUST_MAX_INCOMING_PACKET_SIZE 2048 #endif -// Defines the number of millisecond before retrying a reliable -// packet when no acknowledgment is received. + + #ifndef TLCUST_RELIABLE_RETRY_TIMEOUT_MS #define TLCUST_RELIABLE_RETRY_TIMEOUT_MS 1000 #endif -// Defines the number of retries before declaring a communication error + #ifndef TLCUST_RELIABLE_MAX_RETRY #define TLCUST_RELIABLE_MAX_RETRY 10 #endif -// Defines the maximum number of reliable packets -// that can be in transit(MAX is 255) + + #ifndef TLCUST_RELIABLE_MAX_PACKETS #define TLCUST_RELIABLE_MAX_PACKETS 150 #endif @@ -134,37 +137,37 @@ static const unsigned char ESCAPED_XOFF_CHARACTER = 0x05; * The following are the bit field definition for the flags */ static const unsigned short FLAG_PACKET_ACK = (1<<0); -// ACK of a received packet. Flag detail contains the ACK SeqId + static const unsigned short FLAG_RELIABLE_PACKET = (1<<1); -// Indicates that this is a reliable packet. Flag detail contains -// the remote reliable seqId + + static const unsigned short FLAG_RELIABLE_ACK = (1<<2); -// A reliable SeqId was Acked. Flag detail -// contains the acked reliable seqId + + static const unsigned short FLAG_RELIABLE_NACK = (1<<3); -// A reliable SeqId error was detected. -//Flag detail contains the last remote reliable seqId + + static const unsigned short FLAG_MSG_LOST = (1<<4); -// Remote PacketLayer detected lost packets (jumps in SeqId). -//The flag details contains the last remote seqId + + static const unsigned short FLAG_MSG_GARBAGE = (1<<5); -// Garbage bytes detected. The Flag details will contains -//the number of garbage bytes (capped to 255) + + static const unsigned short FLAG_SIZE_EXTENDED = (1<<6); -// Size of packet will have one byte -//extension (MSB), contained in the Flags detail + + static const unsigned short FLAG_EXTENDED = (1<<7); -// If set, then the flag details will contains -// a Byte representing the MSB of the 16bit flags + + static const unsigned short FLAG_INTERNAL_PACKET = (1<<8); -// Packet in that message is internal, -// and should be processed by the TL + + static const unsigned short FLAG_IGNORE_SEQID = (1<<9); -// Remote side requested to ignore the seqId, -//i.e. error should not be accounted for in the stats + + /* Enumeration of all the RPCs for the codec. DO NOT CHANGE THE ORDER, * DELETE, or INSERT anything to keep backward compatibility. @@ -219,7 +222,7 @@ enum { , RPC_DEFINITION(IRpcSensorResponse, Data) }; -/// enumeration for the state + enum { WAIT_FOR_ESC_SOP = 0 , WAIT_FOR_SOP @@ -232,11 +235,11 @@ typedef struct stTransportLayerStats { unsigned int ulRxGarbageBytes; unsigned int ulRxPacketLost; unsigned int ulRemotePacketLost; - // this is approximate as it is reported and the report could be lost. + unsigned int ulRemoteGarbage; - // this is approximate as it is reported and the report could be lost. + unsigned int ulPacketSent; - // number of normal packet sent + unsigned int ulPacketReceived; unsigned int ulAckReceived; unsigned int ulReliablePacketSent; @@ -265,6 +268,30 @@ static unsigned char m_ucReliableCrc; static unsigned short m_usReliableLen; static bool m_bOngoingSync; + + + + + + + + + + + + + + + + + + + + + + + + /** * CRC table - from GlUtlCrc::ucCrcTable * @@ -306,6 +333,7 @@ static const unsigned char crc_table[] = { static inline unsigned char crc_calc(unsigned char *m_ucCrcState, unsigned char ucData) + { *m_ucCrcState = crc_table[*m_ucCrcState ^ ucData]; return *m_ucCrcState; @@ -422,6 +450,7 @@ static int BbdBridge_OnPacketReceived(unsigned char *pucData, } else { WARN_ON(1); } + return (sensor > 0); } @@ -554,10 +583,9 @@ static bool TransportLayer_PacketReceived(void *priv) if (!bAckReceived || usLen > 0) { bool bDelayedEnough = (++m_ucDelayAckCount > 200); ++m_otCurrentStats.ulPacketReceived; - /* if this is a payload packet, we need to acknowledge it. - * But don't clog the wires with power-hungry simple - * acks unless we have too many (200) outstanding. - */ + + + if (bDelayedEnough) { pr_debug("Skip averted/%d %s %s\n", __LINE__, (bAckReceived) ? "ACK" : "!ack", @@ -625,6 +653,7 @@ static bool TransportLayer_PacketReceived(void *priv) bcm_on_packet_received(priv, m_aucRxEscapedBuf, m_uiEscLen); } } else { + bcm_on_packet_received(priv, m_aucRxEscapedBuf, m_uiEscLen); } return true; @@ -666,8 +695,8 @@ void bbd_parse_asic_data(unsigned char *pucData, m_uiParserState = WAIT_FOR_SOP; m_otCurrentStats.ulRxGarbageBytes += (m_ulByteCntSinceLastValidPacket - 1); - // if we had only one byte, then there is - // no garbage, any extra is garbage + + m_ulByteCntSinceLastValidPacket = 1; } } @@ -707,6 +736,7 @@ void bbd_parse_asic_data(unsigned char *pucData, if (ucData == EOP_CHARACTER) { if (TransportLayer_PacketReceived(priv)) { m_ulByteCntSinceLastValidPacket = 0; + } m_uiEscLen = 0; m_uiParserState = WAIT_FOR_ESC_SOP; @@ -732,12 +762,17 @@ void bbd_parse_asic_data(unsigned char *pucData, m_uiParserState = WAIT_FOR_ESC_SOP; } } else if (ucData == (SOP_CHARACTER - 1)) { + + m_uiParserState = WAIT_FOR_MESSAGE_COMPLETE; + m_uiRxLen = 0; m_uiEscLen = 0; m_otCurrentStats.ulRxGarbageBytes += (m_ulByteCntSinceLastValidPacket-2); + + m_ulByteCntSinceLastValidPacket = 2; } else if (ucData == ESCAPE_CHARACTER) { m_uiParserState = WAIT_FOR_SOP; @@ -757,6 +792,8 @@ EXPORT_SYMBOL(bbd_parse_asic_data); #ifndef __KERNEL__ + + unsigned char sample1[] = { 0x00, 0x2E, 0xB0, 0x00, 0x85, 0x26, 0x00, 0x21, 0x24, 0x22, 0x00, 0x02, 0x00, 0x1E, 0x00, 0x37, 0x0E, 0xD3, @@ -769,6 +806,7 @@ unsigned char sample1[] = { 0x00, 0x2E, 0xB0, 0x00, 0x85, 0x26, int main(void) { + bbd_parse_asic_data(sample1, sizeof(sample1), NULL, NULL); return 0; } diff --git a/drivers/gps/bcm_gps_spi.c b/drivers/gps/bcm_gps_spi.c index e4a644edb670..14391dfd3ea5 100644 --- a/drivers/gps/bcm_gps_spi.c +++ b/drivers/gps/bcm_gps_spi.c @@ -29,9 +29,12 @@ #include #include #include + #include #include + #include + #include #include #include @@ -39,6 +42,9 @@ #include #include #include + + + #include "bbd.h" #define WORD_BURST_SIZE 4 @@ -88,6 +94,8 @@ #define DEBUG_TIME_STAT #define CONFIG_TRANSFER_STAT + + #define CONFIG_PACKET_RECEIVED (31*1024) bool ssi_dbg = true; @@ -96,11 +104,18 @@ bool ssi_dbg_rng = true; int g_bcm_bitrate = 12000; + int ssi_mode = 1; + int ssi_len = 2; int ssi_fc = 3; + + int ssi_tx_fail = 1; + + int ssi_tx_fc_retries = 1; + int ssi_tx_fc_retry_errors = 1; @@ -123,15 +138,16 @@ struct bcm_spi_transfer_stat { } __attribute__((__packed__)); #endif -//-------------------------------------------------------------- -// -// Structures -// -//-------------------------------------------------------------- + + + + + #define BCM_SPI_READ_BUF_SIZE (8*PAGE_SIZE) #define BCM_SPI_WRITE_BUF_SIZE (8*PAGE_SIZE) + #define MIN_SPI_FRAME_LEN 254 #define MAX_SPI_FRAME_LEN (BCM_SPI_READ_BUF_SIZE / 2) @@ -176,6 +192,7 @@ struct bcm_spi_priv { struct workqueue_struct *serial_wq; atomic_t suspending; + /* SPI tx/rx buf */ struct bcm_ssi_tx_frame *tx_buf; struct bcm_ssi_rx_frame *rx_buf; @@ -184,6 +201,10 @@ struct bcm_spi_priv { struct bcm_spi_strm_protocol tx_strm; struct bcm_spi_strm_protocol rx_strm; + +#ifdef CONFIG_TRANSFER_STAT + struct bcm_spi_transfer_stat trans_stat[2]; +#endif struct pinctrl *ts_pinctrl; struct pinctrl_state *gpio_state_active; struct pinctrl_state *gpio_state_suspend; @@ -232,27 +253,82 @@ static ssize_t bcm_4775_nstandby_store(struct device *dev, static DEVICE_ATTR(nstandby, 0660, bcm_4775_nstandby_show, bcm_4775_nstandby_store); + +static void bcm_ssi_clear_trans_stat(struct bcm_spi_priv *priv) +{ + memset(priv->trans_stat, 0, sizeof(priv->trans_stat)); +} + +static void bcm_ssi_print_trans_stat(struct bcm_spi_priv *priv) +{ + return; + /*char buf[512]; + char *p = buf; + + struct bcm_spi_transfer_stat *trans = &priv->trans_stat[0]; + p = buf; + + p += snprintf(p, sizeof(buf), + "SSPBBD TX:<255B=%d <1K=%d,<8K=%d,<32K=%d,<64K=%d", + trans->len_255, trans->len_1K, trans->len_8K, + trans->len_32K, trans->len_64K); + //pr_info("%s\n",buf); + + trans = &priv->trans_stat[1]; + p = buf; + p += snprintf(p, sizeof(buf), + "SSPBBD:RX: <255B=%d,<1K=%d,<8K=%d,<32K=%d,<64K=%d", + trans->len_255, trans->len_1K, + trans->len_8K, trans->len_32K, trans->len_64K); + + //pr_info("%s\n",buf); + + if (priv->tx_strm.ctrl_byte & SSI_FLOW_CONTROL_ENABLED) { + p = buf; + p += snprintf(p, sizeof(buf), + "SSPBBD fail=%d,retries=%d,retry errors=%d", + ssi_tx_fail-1, + ssi_tx_fc_retries-1, + ssi_tx_fc_retry_errors-1); + //pr_info("%s\n",buf); + }*/ +} + +static void bcm_ssi_calc_trans_stat(struct bcm_spi_transfer_stat *trans, + unsigned short length) +{ + if (length <= 255) + trans->len_255++; + else if (length <= 1024) + trans->len_1K++; + else if (length <= (8*1024)) + trans->len_8K++; + else if (length <= (32*1024)) + trans->len_32K++; + else + trans->len_64K++; +} #endif unsigned long m_ulRxBufferBlockSize[4] = {32, 256, 1024 * 2, 1024 * 16}; -//-------------------------------------------------------------- -// -// File Operations -// -//-------------------------------------------------------------- + + + + + static int bcm_spi_open(struct inode *inode, struct file *filp) { /* Initially, */ struct bcm_spi_priv *priv = container_of(filp->private_data, struct bcm_spi_priv, misc); struct bcm_spi_strm_protocol *strm; - unsigned long flags; + unsigned long int flags; unsigned char fc_mask, len_mask, duplex_mask; - //char buf[512]; - //char *p = buf; - //pr_info("%s++\n", __func__); + + + if (priv->busy) return -EBUSY; @@ -290,13 +366,13 @@ static int bcm_spi_open(struct inode *inode, struct file *filp) } else if (ssi_mode == 0) { strm->pckt_len = 0; } - strm->ctrl_len = strm->pckt_len + strm->fc_len + 1; // 1 for tx cmd byte + strm->ctrl_len = strm->pckt_len + strm->fc_len + 1; strm->frame_len = ssi_len == 2 ? MAX_SPI_FRAME_LEN : MIN_SPI_FRAME_LEN; strm->ctrl_byte = duplex_mask | SSI_MODE_STREAM | len_mask | SSI_WRITE_TRANS | fc_mask; - // TX SPI Streaming Protocol in details + /*p = buf; snprintf(p, sizeof(buf), "[SSPBBD]: tx ctrl %02X: total %d = len %d + fc %d + cmd 1", @@ -316,7 +392,7 @@ static int bcm_spi_open(struct inode *inode, struct file *filp) (ssi_mode == SSI_MODE_FULL_DUPLEX ? SSI_WRITE_TRANS : SSI_READ_TRANS); - // RX SPI Streaming Protocol in details + /*p = buf; snprintf(p, sizeof(buf), "[SSPBBD]: rx ctrl %02X: total %d = len %d + fc %d + stat 1", @@ -343,6 +419,9 @@ static int bcm_spi_open(struct inode *inode, struct file *filp) //pr_info("%s\n",buf);*/ } +#ifdef CONFIG_TRANSFER_STAT + bcm_ssi_clear_trans_stat(priv); +#endif ssi_tx_fail = 1; ssi_tx_fc_retries = 1; ssi_tx_fc_retry_errors = 1; @@ -354,10 +433,15 @@ static int bcm_spi_open(struct inode *inode, struct file *filp) static int bcm_spi_release(struct inode *inode, struct file *filp) { struct bcm_spi_priv *priv = filp->private_data; - unsigned long flags; + unsigned long int flags; + priv->busy = false; +#ifdef CONFIG_TRANSFER_STAT + bcm_ssi_print_trans_stat(priv); +#endif + /* Disable irq */ spin_lock_irqsave(&priv->irq_lock, flags); if (atomic_xchg(&priv->irq_enabled, 0)) @@ -367,6 +451,7 @@ static int bcm_spi_release(struct inode *inode, struct file *filp) disable_irq_wake(priv->spi->irq); + return 0; } @@ -378,6 +463,8 @@ static ssize_t bcm_spi_read(struct file *filp, char __user *buf, struct circ_buf *circ = &priv->read_buf; size_t rd_size = 0; + + mutex_lock(&priv->rlock); /* Copy from circ buffer to user @@ -399,6 +486,8 @@ static ssize_t bcm_spi_read(struct file *filp, char __user *buf, CIRC_CNT(circ->head, circ->tail, BCM_SPI_READ_BUF_SIZE)); mutex_unlock(&priv->rlock); + + return rd_size; } @@ -411,6 +500,8 @@ static ssize_t bcm_spi_write(struct file *filp, const char __user *buf, size_t wr_size = 0; bool rxtx_work_run = true; + + mutex_lock(&priv->wlock); /* Copy from user into circ buffer * We may require 2 copies from [tail..end] and [end..head] @@ -421,6 +512,7 @@ static ssize_t bcm_spi_write(struct file *filp, const char __user *buf, BCM_SPI_WRITE_BUF_SIZE); size_t copied = min(space_to_end, size); + WARN_ON(copy_from_user((void *) circ->buf + circ->head, buf + wr_size, @@ -433,12 +525,13 @@ static ssize_t bcm_spi_write(struct file *filp, const char __user *buf, mutex_unlock(&priv->wlock); + + /* kick start rxtx thread */ /* we don't want to queue work in suspending and shutdown */ if (!atomic_read(&priv->suspending)) { /* Disable irq */ - unsigned long flags; - + unsigned long int flags; spin_lock_irqsave(&priv->irq_lock, flags); if (atomic_xchg(&priv->irq_enabled, 0)) disable_irq_nosync(priv->spi->irq); @@ -447,8 +540,11 @@ static ssize_t bcm_spi_write(struct file *filp, const char __user *buf, spin_unlock_irqrestore(&priv->irq_lock, flags); - if (rxtx_work_run == true) + if (rxtx_work_run == true) { + queue_work(priv->serial_wq, &(priv->rxtx_work)); + + } } return wr_size; } @@ -483,11 +579,11 @@ static const struct file_operations bcm_spi_fops = { -//-------------------------------------------------------------- -// -// Misc. functions -// -//-------------------------------------------------------------- + + + + + /* @@ -530,11 +626,11 @@ static void bcm477x_bye(struct bcm_spi_priv *priv) gpio_set_value(priv->mcu_req, 0); } -//-------------------------------------------------------------- -// -// SSI tx/rx functions -// -//-------------------------------------------------------------- + + + + + static unsigned short bcm_ssi_get_len(unsigned char ctrl_byte, unsigned char *data) @@ -587,8 +683,10 @@ static int bcm_spi_sync(struct bcm_spi_priv *priv, void *tx_buf, xfer.rx_buf = rx_buf; /* Sync */ + ret = spi_sync(msg.spi, &msg); + if (ret) pr_err("[SSPBBD} spi_sync error, return=%d\n", ret); @@ -653,16 +751,24 @@ static int bcm_ssi_tx(struct bcm_spi_priv *priv, int length) /* Call BBD */ if (bytes_to_write != 0) bbd_parse_asic_data(data_p, Nread, NULL, priv); + +#ifdef CONFIG_TRANSFER_STAT + bcm_ssi_calc_trans_stat(&priv->trans_stat[1], + Mwrite+Nread); +#endif } + if (strm->fc_len != 0) { Bwritten = bcm_ssi_get_len(strm->ctrl_byte, &rx->data[strm->pckt_len + Mwrite]); if (Mwrite != Bwritten) { + ssi_tx_fc_retries++; if (Mwrite < Bwritten) { + ssi_tx_fc_retry_errors++; pr_err("[SSPBBD]: %s @ FC error %d\n", __func__, @@ -682,6 +788,11 @@ static int bcm_ssi_tx(struct bcm_spi_priv *priv, int length) } } while (--retry_ctr > 0); + +#ifdef CONFIG_TRANSFER_STAT + bcm_ssi_calc_trans_stat(&priv->trans_stat[0], length); +#endif + return ret; } @@ -694,6 +805,13 @@ static int bcm_ssi_rx(struct bcm_spi_priv *priv, size_t *length) unsigned short ctrl_len = strm->pckt_len+1; unsigned short payload_len; + +#ifdef CONFIG_TRANSFER_STAT + bcm_ssi_calc_trans_stat(&priv->trans_stat[1], *length); +#endif + + + bcm_ssi_clr_len(strm->ctrl_byte, tx->data); tx->cmd = strm->ctrl_byte; rx->status = 0; @@ -710,6 +828,8 @@ static int bcm_ssi_rx(struct bcm_spi_priv *priv, size_t *length) payload_len = bcm_ssi_get_len(strm->ctrl_byte, rx->data); + + if (payload_len == 0) { payload_len = MIN_SPI_FRAME_LEN; pr_err("[SSPBBD] rx->len is still read to 0. set %d\n", @@ -718,6 +838,7 @@ static int bcm_ssi_rx(struct bcm_spi_priv *priv, size_t *length) /* TODO: limit max payload to 254 because of exynos3 bug */ { + *length = min((unsigned short)(strm->frame_len-ctrl_len), payload_len); memset(tx->data, 0, *length + ctrl_len - 1); @@ -737,16 +858,22 @@ static int bcm_ssi_rx(struct bcm_spi_priv *priv, size_t *length) if (payload_len < *length) *length = payload_len; +#ifdef CONFIG_TRANSFER_STAT + bcm_ssi_calc_trans_stat(&priv->trans_stat[1], *length); +#endif + return 0; } -void bcm_on_packet_received(void *_priv, unsigned char - *data, size_t size) +void bcm_on_packet_received(void *_priv, unsigned char *data, + unsigned int size) { struct bcm_spi_priv *priv = (struct bcm_spi_priv *)_priv; struct circ_buf *rd_circ = &priv->read_buf; size_t written = 0, avail = size; + + /* Copy into circ buffer */ mutex_lock(&priv->rlock); do { size_t space_to_end = CIRC_SPACE_TO_END(rd_circ->head, @@ -780,9 +907,13 @@ static void bcm_start_tx_work(struct work_struct *work) spin_lock(&priv->irq_lock); + + + queue_work(priv->serial_wq, &priv->rxtx_work); spin_unlock(&priv->irq_lock); + } @@ -800,6 +931,8 @@ static void bcm_rxtx_work(struct work_struct *work) return; } + + do { int ret; size_t avail = 0; @@ -807,11 +940,14 @@ static void bcm_rxtx_work(struct work_struct *work) /* Read first */ ret = gpio_get_value(priv->host_req); + + if (ret) { /* Receive SSI frame */ if (bcm_ssi_rx(priv, &avail)) break; /* Call BBD */ + bbd_parse_asic_data(priv->rx_buf->data + rx_pckt_len, avail, NULL, priv); } @@ -820,6 +956,8 @@ static void bcm_rxtx_work(struct work_struct *work) avail = CIRC_CNT(wr_circ->head, wr_circ->tail, BCM_SPI_WRITE_BUF_SIZE); + + if (avail) { size_t written = 0; @@ -846,6 +984,7 @@ static void bcm_rxtx_work(struct work_struct *work) (BCM_SPI_WRITE_BUF_SIZE-1); } while (avail > 0); + /* Transmit SSI frame */ ret = bcm_ssi_tx(priv, written); mutex_unlock(&priv->wlock); @@ -864,7 +1003,7 @@ static void bcm_rxtx_work(struct work_struct *work) /* Enable irq */ { - unsigned long flags; + unsigned long int flags; spin_lock_irqsave(&priv->irq_lock, flags); @@ -875,14 +1014,16 @@ static void bcm_rxtx_work(struct work_struct *work) spin_unlock_irqrestore(&priv->irq_lock, flags); } + + } -//-------------------------------------------------------------- -// -// IRQ Handler -// -//-------------------------------------------------------------- + + + + + static irqreturn_t bcm_irq_handler(int irq, void *pdata) { struct bcm_spi_priv *priv = @@ -898,8 +1039,10 @@ static irqreturn_t bcm_irq_handler(int irq, void *pdata) spin_unlock(&priv->irq_lock); /* we don't want to queue work in suspending and shutdown */ - if (!atomic_read(&priv->suspending)) + if (!atomic_read(&priv->suspending)) { + queue_work(priv->serial_wq, &priv->rxtx_work); + } return IRQ_HANDLED; } @@ -962,17 +1105,17 @@ static int gps_pinctrl_select(struct bcm_spi_priv *data, bool on) -//-------------------------------------------------------------- -// -// SPI driver operations -// -//-------------------------------------------------------------- + + + + + static int bcm_spi_suspend(struct device *dev, pm_message_t state) { struct spi_device *spi = to_spi_device(dev); struct bcm_spi_priv *priv = (struct bcm_spi_priv *) spi_get_drvdata(spi); - unsigned long flags; + unsigned long int flags; atomic_set(&priv->suspending, 1); /* Disable irq */ @@ -989,7 +1132,7 @@ static int bcm_spi_resume(struct device *dev) struct spi_device *spi = to_spi_device(dev); struct bcm_spi_priv *priv = (struct bcm_spi_priv *) spi_get_drvdata(spi); - unsigned long flags; + unsigned long int flags; atomic_set(&priv->suspending, 0); @@ -1005,7 +1148,7 @@ static void bcm_spi_shutdown(struct spi_device *spi) { struct bcm_spi_priv *priv = (struct bcm_spi_priv *) spi_get_drvdata(spi); - unsigned long flags; + unsigned long int flags; atomic_set(&priv->suspending, 1); /* Disable irq */ @@ -1028,10 +1171,14 @@ static int bcm_spi_probe(struct spi_device *spi) int error = 0; /* Check GPIO# */ +#ifndef CONFIG_OF + +#else if (!spi->dev.of_node) { pr_err("[SSPBBD]: Failed to find of_node\n"); goto err_exit; } +#endif host_req = of_get_named_gpio(spi->dev.of_node, "ssp-host-req", 0); mcu_req = of_get_named_gpio(spi->dev.of_node, "ssp-mcu-req", 0); @@ -1172,6 +1319,7 @@ static int bcm_spi_probe(struct spi_device *spi) mutex_init(&priv->rlock); mutex_init(&priv->wlock); + priv->busy = false; /* Init - work */ @@ -1189,6 +1337,9 @@ static int bcm_spi_probe(struct spi_device *spi) priv->mcu_resp = mcu_resp; priv->nstandby = nstandby; + /* Init - etc */ + + g_bcm_gps = priv; /* Init BBD & SSP */ bbd_init(&spi->dev, legacy_patch); @@ -1216,7 +1367,9 @@ static int bcm_spi_remove(struct spi_device *spi) { struct bcm_spi_priv *priv = (struct bcm_spi_priv *) spi_get_drvdata(spi); - unsigned long flags; + unsigned long int flags; + + atomic_set(&priv->suspending, 1); @@ -1236,6 +1389,7 @@ static int bcm_spi_remove(struct spi_device *spi) } /* Free everything */ + free_irq(spi->irq, priv); device_remove_file(&priv->spi->dev, &dev_attr_nstandby); kfree(priv->tx_buf); @@ -1292,11 +1446,11 @@ static struct spi_driver bcm_spi_driver = { }; -//-------------------------------------------------------------- -// -// Module init/exit -// -//-------------------------------------------------------------- + + + + + static int __init bcm_spi_init(void) { return spi_register_driver(&bcm_spi_driver); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c index 26afdffab5a0..0c2ed1254585 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c @@ -336,17 +336,9 @@ bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device * path_size += le16_to_cpu(path->usSize); if (device_support & le16_to_cpu(path->usDeviceTag)) { - uint8_t con_obj_id, con_obj_num, con_obj_type; - - con_obj_id = + uint8_t con_obj_id = (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; - con_obj_num = - (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK) - >> ENUM_ID_SHIFT; - con_obj_type = - (le16_to_cpu(path->usConnObjectId) & - OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; /* Skip TV/CV support */ if ((le16_to_cpu(path->usDeviceTag) == @@ -371,15 +363,7 @@ bool amdgpu_atombios_get_connector_info_from_object_table(struct amdgpu_device * router.ddc_valid = false; router.cd_valid = false; for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) { - uint8_t grph_obj_id, grph_obj_num, grph_obj_type; - - grph_obj_id = - (le16_to_cpu(path->usGraphicObjIds[j]) & - OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; - grph_obj_num = - (le16_to_cpu(path->usGraphicObjIds[j]) & - ENUM_ID_MASK) >> ENUM_ID_SHIFT; - grph_obj_type = + uint8_t grph_obj_type = (le16_to_cpu(path->usGraphicObjIds[j]) & OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT; diff --git a/drivers/gpu/drm/bridge/lt9611.c b/drivers/gpu/drm/bridge/lt9611.c index fc01ae7233af..8583b5b32d5c 100644 --- a/drivers/gpu/drm/bridge/lt9611.c +++ b/drivers/gpu/drm/bridge/lt9611.c @@ -168,8 +168,6 @@ static struct lt9611_timing_info lt9611_supp_timing_cfg[] = { {0xffff, 0xffff, 0xff, 0xff, 0xff}, }; -static int cont_splash_en; - static struct lt9611 *bridge_to_lt9611(struct drm_bridge *bridge) { return container_of(bridge, struct lt9611, bridge); @@ -482,7 +480,7 @@ static int lt9611_gpio_configure(struct lt9611 *pdata, bool on) goto error; } - ret = gpio_direction_output(pdata->reset_gpio, 1); + ret = gpio_direction_output(pdata->reset_gpio, 0); if (ret) { pr_err("lt9611 reset gpio direction failed\n"); goto reset_error; @@ -1219,16 +1217,14 @@ static int lt9611_config_vreg(struct device *dev, goto vreg_get_fail; } - if (!cont_splash_en) { - rc = regulator_set_voltage( - curr_vreg->vreg, - curr_vreg->min_voltage, - curr_vreg->max_voltage); - if (rc < 0) { - pr_err("%s set vltg fail\n", - curr_vreg->vreg_name); - goto vreg_set_voltage_fail; - } + rc = regulator_set_voltage( + curr_vreg->vreg, + curr_vreg->min_voltage, + curr_vreg->max_voltage); + if (rc < 0) { + pr_err("%s set vltg fail\n", + curr_vreg->vreg_name); + goto vreg_set_voltage_fail; } } } else { @@ -2082,8 +2078,7 @@ static int lt9611_probe(struct i2c_client *client, goto err_dt_supply; } - if (!cont_splash_en) - lt9611_reset(pdata); + lt9611_reset(pdata); ret = lt9611_read_device_rev(pdata); if (ret) { @@ -2200,9 +2195,6 @@ static void __exit lt9611_exit(void) i2c_del_driver(<9611_driver); } -module_param(cont_splash_en, int, 0600); -MODULE_PARM_DESC(cont_splash_en, - "lt9611.cont_splash_en=1 or 0; where 1 represent enabled and 0 for disabled"); module_init(lt9611_init); module_exit(lt9611_exit); diff --git a/drivers/gpu/drm/drm_dp_mst_topology.c b/drivers/gpu/drm/drm_dp_mst_topology.c index db545bd069f8..41e67e983a7f 100644 --- a/drivers/gpu/drm/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/drm_dp_mst_topology.c @@ -981,20 +981,9 @@ static struct drm_dp_mst_port *drm_dp_mst_get_port_ref_locked(struct drm_dp_mst_ static struct drm_dp_mst_port *drm_dp_get_validated_port_ref(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port) { struct drm_dp_mst_port *rport = NULL; - mutex_lock(&mgr->lock); - /* - * Port may or may not be 'valid' but we don't care about that when - * destroying the port and we are guaranteed that the port pointer - * will be valid until we've finished - */ - if (current_work() == &mgr->destroy_connector_work) { - kref_get(&port->kref); - rport = port; - } else if (mgr->mst_primary) { - rport = drm_dp_mst_get_port_ref_locked(mgr->mst_primary, - port); - } + if (mgr->mst_primary) + rport = drm_dp_mst_get_port_ref_locked(mgr->mst_primary, port); mutex_unlock(&mgr->lock); return rport; } diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c index 5ba527a14b75..a5deca6df7c6 100644 --- a/drivers/gpu/drm/drm_edid.c +++ b/drivers/gpu/drm/drm_edid.c @@ -2763,6 +2763,7 @@ add_detailed_modes(struct drm_connector *connector, struct edid *edid, #define VENDOR_BLOCK 0x03 #define SPEAKER_BLOCK 0x04 #define HDR_STATIC_METADATA_EXTENDED_DATA_BLOCK 0x06 +#define COLORIMETRY_EXTENDED_DATA_BLOCK 0x05 #define EXTENDED_TAG 0x07 #define VIDEO_CAPABILITY_BLOCK 0x07 #define Y420_VIDEO_DATA_BLOCK 0x0E @@ -3602,11 +3603,15 @@ drm_extract_vcdb_info(struct drm_connector *connector, const u8 *db) (db[2] & (BIT(3) | BIT(2))) >> 2; connector->ce_scan_info = db[2] & (BIT(1) | BIT(0)); + connector->rgb_qs = db[2] & BIT(6); + connector->yuv_qs = db[2] & BIT(7); DRM_DEBUG_KMS("Scan Info (pt|it|ce): (%d|%d|%d)", (int) connector->pt_scan_info, (int) connector->it_scan_info, (int) connector->ce_scan_info); + DRM_DEBUG_KMS("rgb_quant_range_select %d", connector->rgb_qs); + DRM_DEBUG_KMS("ycc_quant_range_select %d", connector->yuv_qs); } static bool drm_edid_is_luminance_value_present( @@ -3662,6 +3667,49 @@ drm_extract_hdr_db(struct drm_connector *connector, const u8 *db) DRM_DEBUG_KMS("min luminance %d\n", connector->hdr_min_luminance); } +/** + * drm_extract_colorimetry_db - Parse the HDMI colorimetry extended block + * @connector: connector corresponding to the HDMI sink + * @db: start of the HDMI colorimetry extended block + * + * Parses the HDMI colorimetry block to extract sink info for @connector. + */ +static void +drm_extract_colorimetry_db(struct drm_connector *connector, const u8 *db) +{ + + if (!db) { + DRM_ERROR("invalid db\n"); + return; + } + + if (db[2] & BIT(0)) + connector->color_enc_fmt |= DRM_EDID_COLORIMETRY_xvYCC_601; + + if (db[2] & BIT(1)) + connector->color_enc_fmt |= DRM_EDID_COLORIMETRY_xvYCC_709; + + if (db[2] & BIT(2)) + connector->color_enc_fmt |= DRM_EDID_COLORIMETRY_sYCC_601; + + if (db[2] & BIT(3)) + connector->color_enc_fmt |= DRM_EDID_COLORIMETRY_ADBYCC_601; + + if (db[2] & BIT(4)) + connector->color_enc_fmt |= DRM_EDID_COLORIMETRY_ADB_RGB; + + if (db[2] & BIT(5)) + connector->color_enc_fmt |= DRM_EDID_COLORIMETRY_BT2020_CYCC; + + if (db[2] & BIT(6)) + connector->color_enc_fmt |= DRM_EDID_COLORIMETRY_BT2020_YCC; + + if (db[2] & BIT(7)) + connector->color_enc_fmt |= DRM_EDID_COLORIMETRY_BT2020_RGB; + + DRM_DEBUG_KMS("colorimetry fmt 0x%x\n", connector->color_enc_fmt); +} + /* * drm_hdmi_extract_extended_blk_info - Parse the HDMI extended tag blocks * @connector: connector corresponding to the HDMI sink @@ -3694,6 +3742,10 @@ struct edid *edid) case HDR_STATIC_METADATA_EXTENDED_DATA_BLOCK: drm_extract_hdr_db(connector, db); break; + case COLORIMETRY_EXTENDED_DATA_BLOCK: + drm_extract_colorimetry_db(connector, + db); + break; default: break; } diff --git a/drivers/gpu/drm/drm_property.c b/drivers/gpu/drm/drm_property.c index 3494f3931594..12b02fb6baa2 100644 --- a/drivers/gpu/drm/drm_property.c +++ b/drivers/gpu/drm/drm_property.c @@ -559,7 +559,7 @@ drm_property_create_blob(struct drm_device *dev, size_t length, if (!length || length > MAX_BLOB_PROP_SIZE - sizeof(struct drm_property_blob)) - return ERR_PTR(-EINVAL); + return ERR_PTR(-EINVAL); blob = vzalloc(sizeof(struct drm_property_blob)+length); if (!blob) diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c index e07cb1fe4860..2b6c04acb24f 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c @@ -1775,8 +1775,9 @@ static int exynos_dsi_probe(struct platform_device *pdev) ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies), dsi->supplies); if (ret) { - dev_info(dev, "failed to get regulators: %d\n", ret); - return -EPROBE_DEFER; + if (ret != -EPROBE_DEFER) + dev_info(dev, "failed to get regulators: %d\n", ret); + return ret; } dsi->clks = devm_kzalloc(dev, @@ -1789,9 +1790,10 @@ static int exynos_dsi_probe(struct platform_device *pdev) dsi->clks[i] = devm_clk_get(dev, clk_names[i]); if (IS_ERR(dsi->clks[i])) { if (strcmp(clk_names[i], "sclk_mipi") == 0) { - strcpy(clk_names[i], OLD_SCLK_MIPI_CLK_NAME); - i--; - continue; + dsi->clks[i] = devm_clk_get(dev, + OLD_SCLK_MIPI_CLK_NAME); + if (!IS_ERR(dsi->clks[i])) + continue; } dev_info(dev, "failed to get the clock: %s\n", diff --git a/drivers/gpu/drm/gma500/framebuffer.c b/drivers/gpu/drm/gma500/framebuffer.c index 3a44e705db53..d224fc12b757 100644 --- a/drivers/gpu/drm/gma500/framebuffer.c +++ b/drivers/gpu/drm/gma500/framebuffer.c @@ -516,6 +516,7 @@ static int psbfb_probe(struct drm_fb_helper *helper, container_of(helper, struct psb_fbdev, psb_fb_helper); struct drm_device *dev = psb_fbdev->psb_fb_helper.dev; struct drm_psb_private *dev_priv = dev->dev_private; + unsigned int fb_size; int bytespp; bytespp = sizes->surface_bpp / 8; @@ -525,8 +526,11 @@ static int psbfb_probe(struct drm_fb_helper *helper, /* If the mode will not fit in 32bit then switch to 16bit to get a console on full resolution. The X mode setting server will allocate its own 32bit GEM framebuffer */ - if (ALIGN(sizes->fb_width * bytespp, 64) * sizes->fb_height > - dev_priv->vram_stolen_size) { + fb_size = ALIGN(sizes->surface_width * bytespp, 64) * + sizes->surface_height; + fb_size = ALIGN(fb_size, PAGE_SIZE); + + if (fb_size > dev_priv->vram_stolen_size) { sizes->surface_bpp = 16; sizes->surface_depth = 16; } diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index 01a21dd835b5..1ed60da76a0c 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -306,6 +306,7 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc) static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) { struct drm_device *drm = mtk_crtc->base.dev; + struct drm_crtc *crtc = &mtk_crtc->base; int i; DRM_DEBUG_DRIVER("%s\n", __func__); @@ -327,6 +328,13 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc) mtk_disp_mutex_unprepare(mtk_crtc->mutex); pm_runtime_put(drm->dev); + + if (crtc->state->event && !crtc->state->active) { + spin_lock_irq(&crtc->dev->event_lock); + drm_crtc_send_vblank_event(crtc, crtc->state->event); + crtc->state->event = NULL; + spin_unlock_irq(&crtc->dev->event_lock); + } } static void mtk_drm_crtc_enable(struct drm_crtc *crtc) diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c index a0f562c0a569..ace0facf97f8 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c @@ -124,7 +124,7 @@ static ssize_t debugfs_state_info_read(struct file *file, if (len > count) len = count; - /* TODO: make sure that this does not exceed 4K */ + len = min_t(size_t, len, SZ_4K); if (copy_to_user(buff, buf, len)) { kfree(buf); return -EFAULT; @@ -182,7 +182,7 @@ static ssize_t debugfs_reg_dump_read(struct file *file, if (len > count) len = count; - /* TODO: make sure that this does not exceed 4K */ + len = min_t(size_t, len, SZ_4K); if (copy_to_user(buff, buf, len)) { kfree(buf); return -EFAULT; @@ -3505,4 +3505,3 @@ void dsi_ctrl_drv_unregister(void) { platform_driver_unregister(&dsi_ctrl_driver); } - diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c index 73d3f5b9504d..89452777bc71 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_display.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_display.c @@ -67,14 +67,6 @@ static const struct of_device_id dsi_display_dt_match[] = { static struct dsi_display *primary_display; static struct dsi_display *secondary_display; -const char *dsi_get_display_name(void) -{ - if (primary_display) - return primary_display->name; - else - return NULL; -} - static void dsi_display_mask_ctrl_error_interrupts(struct dsi_display *display, u32 mask, bool enable) { @@ -203,8 +195,6 @@ int dsi_display_set_backlight(void *display, u32 bl_lvl) rc = dsi_panel_enable_doze_backlight(panel, (u32)bl_temp); if (rc) pr_err("unable to enable doze backlight\n"); - } else if (drm_dev && drm_dev->doze_state == DRM_BLANK_LP2) { - pr_err("unable to set doze backlight in LP2 state:%u\n", (u32)bl_temp); } else { drm_dev->doze_brightness = DOZE_BRIGHTNESS_INVALID; rc = dsi_panel_set_backlight(panel, (u32)bl_temp); @@ -4653,6 +4643,12 @@ int dsi_display_cont_splash_config(void *dsi_display) return -EINVAL; } + /* Continuous splash not supported by external bridge */ + if (dsi_display_has_ext_bridge(display)) { + display->is_cont_splash_enabled = false; + return 0; + } + mutex_lock(&display->display_lock); /* Vote for gdsc required to read register address space */ @@ -4696,19 +4692,14 @@ int dsi_display_cont_splash_config(void *dsi_display) goto clk_manager_update; } - /* For external bridge, regulators are managed by bridge driver */ - if (!dsi_display_has_ext_bridge(display)) { - /* Vote on panel regulator will be removed - * during suspend path - */ - rc = dsi_pwr_enable_regulator(&display->panel->power_info, - true); - if (rc) { - pr_err("[%s] failed to enable vregs, rc=%d\n", - display->panel->name, rc); - goto clks_disabled; - } + /* Vote on panel regulator will be removed during suspend path */ + rc = dsi_pwr_enable_regulator(&display->panel->power_info, true); + if (rc) { + pr_err("[%s] failed to enable vregs, rc=%d\n", + display->panel->name, rc); + goto clks_disabled; } + dsi_config_host_engine_state_for_cont_splash(display); mutex_unlock(&display->display_lock); diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_phy_timing_v3_0.c b/drivers/gpu/drm/msm/dsi-staging/dsi_phy_timing_v3_0.c index 6f09af0bb11e..c169a435981b 100644 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_phy_timing_v3_0.c +++ b/drivers/gpu/drm/msm/dsi-staging/dsi_phy_timing_v3_0.c @@ -18,7 +18,7 @@ void dsi_phy_hw_v3_0_get_default_phy_params( struct phy_clk_params *params) { params->clk_prep_buf = 50; - params->clk_zero_buf = 0; + params->clk_zero_buf = 2; params->clk_trail_buf = 30; params->hs_prep_buf = 50; params->hs_zero_buf = 10; diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c index c8d1f19c9a6d..d46b9e75a847 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c @@ -306,7 +306,7 @@ static int dsi_mgr_connector_get_modes(struct drm_connector *connector) return num; } -static int dsi_mgr_connector_mode_valid(struct drm_connector *connector, +static enum drm_mode_status dsi_mgr_connector_mode_valid(struct drm_connector *connector, struct drm_display_mode *mode) { int id = dsi_mgr_connector_get_id(connector); @@ -438,6 +438,7 @@ static void dsi_mgr_bridge_post_disable(struct drm_bridge *bridge) struct msm_dsi *msm_dsi1 = dsi_mgr_get_dsi(DSI_1); struct mipi_dsi_host *host = msm_dsi->host; struct drm_panel *panel = msm_dsi->panel; + struct msm_dsi_pll *src_pll; bool is_dual_dsi = IS_DUAL_DSI(); int ret; @@ -471,6 +472,10 @@ static void dsi_mgr_bridge_post_disable(struct drm_bridge *bridge) id, ret); } + /* Save PLL status if it is a clock source */ + src_pll = msm_dsi_phy_get_pll(msm_dsi->phy); + msm_dsi_pll_save_state(src_pll); + ret = msm_dsi_host_power_off(host); if (ret) pr_err("%s: host %d power off failed,%d\n", __func__, id, ret); diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 3e6506947d6f..9387459e5611 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -530,6 +530,14 @@ static int msm_drm_init(struct device *dev, struct drm_driver *drv) if (ret) goto fail; + if (!dev->dma_parms) { + dev->dma_parms = devm_kzalloc(dev, sizeof(*dev->dma_parms), + GFP_KERNEL); + if (!dev->dma_parms) + return -ENOMEM; + } + dma_set_max_seg_size(dev, DMA_BIT_MASK(32)); + switch (get_mdp_ver(pdev)) { case KMS_MDP4: kms = mdp4_kms_init(ddev); diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c index 103ed5cb89c0..aa7a062adab0 100755 --- a/drivers/gpu/drm/msm/msm_gem.c +++ b/drivers/gpu/drm/msm/msm_gem.c @@ -45,46 +45,6 @@ static bool use_pages(struct drm_gem_object *obj) return !msm_obj->vram_node; } -/* - * Cache sync.. this is a bit over-complicated, to fit dma-mapping - * API. Really GPU cache is out of scope here (handled on cmdstream) - * and all we need to do is invalidate newly allocated pages before - * mapping to CPU as uncached/writecombine. - * - * On top of this, we have the added headache, that depending on - * display generation, the display's iommu may be wired up to either - * the toplevel drm device (mdss), or to the mdp sub-node, meaning - * that here we either have dma-direct or iommu ops. - * - * Let this be a cautionary tail of abstraction gone wrong. - */ - -static void sync_for_device(struct msm_gem_object *msm_obj) -{ - struct device *dev = msm_obj->base.dev->dev; - - if (get_dma_ops(dev)) { - dma_sync_sg_for_device(dev, msm_obj->sgt->sgl, - msm_obj->sgt->nents, DMA_BIDIRECTIONAL); - } else { - dma_map_sg(dev, msm_obj->sgt->sgl, - msm_obj->sgt->nents, DMA_BIDIRECTIONAL); - } -} - -static void sync_for_cpu(struct msm_gem_object *msm_obj) -{ - struct device *dev = msm_obj->base.dev->dev; - - if (get_dma_ops(dev)) { - dma_sync_sg_for_cpu(dev, msm_obj->sgt->sgl, - msm_obj->sgt->nents, DMA_BIDIRECTIONAL); - } else { - dma_unmap_sg(dev, msm_obj->sgt->sgl, - msm_obj->sgt->nents, DMA_BIDIRECTIONAL); - } -} - /* allocate pages from VRAM carveout, used when no IOMMU: */ static struct page **get_pages_vram(struct drm_gem_object *obj, int npages) @@ -155,7 +115,8 @@ static struct page **get_pages(struct drm_gem_object *obj) * so we don't get ourselves into trouble with a dirty cache */ if (msm_obj->flags & (MSM_BO_WC|MSM_BO_UNCACHED)) - sync_for_device(msm_obj); + dma_sync_sg_for_device(dev->dev, msm_obj->sgt->sgl, + msm_obj->sgt->nents, DMA_BIDIRECTIONAL); } return msm_obj->pages; @@ -167,14 +128,6 @@ static void put_pages(struct drm_gem_object *obj) if (msm_obj->pages) { if (msm_obj->sgt) { - - /* For non-cached buffers, ensure the new - * pages are clean because display controller, - * GPU, etc. are not coherent: - */ - if (msm_obj->flags & (MSM_BO_WC|MSM_BO_UNCACHED)) - sync_for_cpu(msm_obj); - sg_free_table(msm_obj->sgt); kfree(msm_obj->sgt); } @@ -1102,4 +1055,3 @@ struct drm_gem_object *msm_gem_import(struct drm_device *dev, drm_gem_object_unreference_unlocked(obj); return ERR_PTR(ret); } - diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h index f5f68533643d..efd6a774fdae 100644 --- a/drivers/gpu/drm/msm/msm_kms.h +++ b/drivers/gpu/drm/msm/msm_kms.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. * Copyright (C) 2013 Red Hat * Author: Rob Clark * @@ -41,6 +41,25 @@ /* Request to switch the bit clk */ #define MSM_MODE_FLAG_SEAMLESS_DYN_CLK (1<<4) +/* + * We need setting some flags in bridge, and using them in encoder. Add them in + * private_flags would be better for use. DRM_MODE_FLAG_SUPPORTS_RGB/YUV are + * flags that indicating the SINK supported color formats read from EDID. While, + * these flags defined here indicate the best color/bit depth foramt we choosed + * that would be better for display. For example the best mode display like: + * RGB+RGB_DC,YUV+YUV_DC, RGB,YUV. And we could not set RGB and YUV format at + * the same time. And also RGB_DC only set when RGB format is set,the same for + * YUV_DC. + */ +/* Enable RGB444 30 bit deep color */ +#define MSM_MODE_FLAG_RGB444_DC_ENABLE (1<<5) +/* Enable YUV420 30 bit deep color */ +#define MSM_MODE_FLAG_YUV420_DC_ENABLE (1<<6) +/* Choose RGB444 format to display */ +#define MSM_MODE_FLAG_COLOR_FORMAT_RGB444 (1<<7) +/* Choose YUV420 format to display */ +#define MSM_MODE_FLAG_COLOR_FORMAT_YCBCR420 (1<<8) + /* As there are different display controller blocks depending on the * snapdragon version, the kms support is split out and the appropriate * implementation is loaded at runtime. The kms module is responsible diff --git a/drivers/gpu/drm/msm/sde/sde_connector.c b/drivers/gpu/drm/msm/sde/sde_connector.c index 6bd014c81c56..e3ceadb15615 100644 --- a/drivers/gpu/drm/msm/sde/sde_connector.c +++ b/drivers/gpu/drm/msm/sde/sde_connector.c @@ -1313,17 +1313,24 @@ void sde_connector_commit_reset(struct drm_connector *connector, ktime_t ts) static void sde_connector_update_hdr_props(struct drm_connector *connector) { struct sde_connector *c_conn = to_sde_connector(connector); - struct drm_msm_ext_hdr_properties hdr = {0}; + struct drm_msm_ext_hdr_properties hdr = {}; - hdr.hdr_metadata_type_one = connector->hdr_metadata_type_one ? 1 : 0; - hdr.hdr_supported = connector->hdr_supported ? 1 : 0; - hdr.hdr_eotf = connector->hdr_eotf; - hdr.hdr_max_luminance = connector->hdr_max_luminance; - hdr.hdr_avg_luminance = connector->hdr_avg_luminance; - hdr.hdr_min_luminance = connector->hdr_min_luminance; + hdr.hdr_supported = connector->hdr_supported; - msm_property_set_blob(&c_conn->property_info, &c_conn->blob_ext_hdr, - &hdr, sizeof(hdr), CONNECTOR_PROP_EXT_HDR_INFO); + if (hdr.hdr_supported) { + hdr.hdr_eotf = connector->hdr_eotf; + hdr.hdr_metadata_type_one = connector->hdr_metadata_type_one; + hdr.hdr_max_luminance = connector->hdr_max_luminance; + hdr.hdr_avg_luminance = connector->hdr_avg_luminance; + hdr.hdr_min_luminance = connector->hdr_min_luminance; + + msm_property_set_blob(&c_conn->property_info, + &c_conn->blob_ext_hdr, + &hdr, + sizeof(hdr), + CONNECTOR_PROP_EXT_HDR_INFO); + + } } static enum drm_connector_status @@ -1765,8 +1772,7 @@ static int sde_connector_get_modes(struct drm_connector *connector) return 0; } - if (c_conn->hdr_capable) - sde_connector_update_hdr_props(connector); + sde_connector_update_hdr_props(connector); return mode_count; } @@ -2346,8 +2352,6 @@ struct drm_connector *sde_connector_init(struct drm_device *dev, if (connector_type == DRM_MODE_CONNECTOR_DisplayPort) { struct drm_msm_ext_hdr_properties hdr = {0}; - c_conn->hdr_capable = true; - msm_property_install_blob(&c_conn->property_info, "ext_hdr_properties", DRM_MODE_PROP_IMMUTABLE, diff --git a/drivers/gpu/drm/msm/sde/sde_connector.h b/drivers/gpu/drm/msm/sde/sde_connector.h index af212c203141..933822eabf1a 100644 --- a/drivers/gpu/drm/msm/sde/sde_connector.h +++ b/drivers/gpu/drm/msm/sde/sde_connector.h @@ -332,7 +332,6 @@ struct sde_connector_evt { * @unset_bl_level: BL level that needs to be set later * @allow_bl_update: Flag to indicate if BL update is allowed currently or not * @last_cmd_tx_sts: status of the last command transfer - * @hdr_capable: external hdr support present */ struct sde_connector { struct drm_connector base; @@ -380,7 +379,6 @@ struct sde_connector { bool allow_bl_update; bool last_cmd_tx_sts; - bool hdr_capable; bool panel_dead_skip; }; diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.c b/drivers/gpu/drm/msm/sde/sde_crtc.c index c6823a6aa2d3..da38e7c6d646 100644 --- a/drivers/gpu/drm/msm/sde/sde_crtc.c +++ b/drivers/gpu/drm/msm/sde/sde_crtc.c @@ -181,6 +181,7 @@ static void sde_crtc_calc_fps(struct sde_crtc *sde_crtc) sde_crtc->fps_info.time_buf[sde_crtc->fps_info.next_time_index++] = ktime_get(); sde_crtc->fps_info.next_time_index %= MAX_FRAME_COUNT; + } /** @@ -4432,6 +4433,17 @@ static void sde_crtc_disable(struct drm_crtc *crtc) } sde_crtc->enabled = false; + /* Below parameters are for fps calculation for sysfs node */ + sde_crtc->fps_info.fps_periodic_duration = DEFAULT_FPS_PERIOD_1_SEC; + sde_crtc->fps_info.time_buf = kmalloc_array(MAX_FRAME_COUNT, + sizeof(sde_crtc->fps_info.time_buf), GFP_KERNEL); + + if (!sde_crtc->fps_info.time_buf) + SDE_ERROR("invalid buffer\n"); + else + memset(sde_crtc->fps_info.time_buf, 0, + sizeof(*(sde_crtc->fps_info.time_buf))); + if (atomic_read(&sde_crtc->frame_pending)) { SDE_ERROR("crtc%d frame_pending%d\n", crtc->base.id, atomic_read(&sde_crtc->frame_pending)); @@ -6319,17 +6331,6 @@ struct drm_crtc *sde_crtc_init(struct drm_device *dev, struct drm_plane *plane) sde_crtc->enabled = false; - /* Below parameters are for fps calculation for sysfs node */ - sde_crtc->fps_info.fps_periodic_duration = DEFAULT_FPS_PERIOD_1_SEC; - sde_crtc->fps_info.time_buf = kmalloc_array(MAX_FRAME_COUNT, - sizeof(sde_crtc->fps_info.time_buf), GFP_KERNEL); - - if (!sde_crtc->fps_info.time_buf) - SDE_ERROR("invalid buffer\n"); - else - memset(sde_crtc->fps_info.time_buf, 0, - sizeof(*(sde_crtc->fps_info.time_buf))); - INIT_LIST_HEAD(&sde_crtc->frame_event_list); INIT_LIST_HEAD(&sde_crtc->user_event_list); for (i = 0; i < ARRAY_SIZE(sde_crtc->frame_events); i++) { diff --git a/drivers/gpu/drm/msm/sde/sde_crtc.h b/drivers/gpu/drm/msm/sde/sde_crtc.h index 889475da8dbf..ad824c4f8dc3 100644 --- a/drivers/gpu/drm/msm/sde/sde_crtc.h +++ b/drivers/gpu/drm/msm/sde/sde_crtc.h @@ -147,6 +147,7 @@ struct sde_crtc_event { void (*cb_func)(struct drm_crtc *crtc, void *usr); void *usr; }; + /** * struct sde_crtc_fps_info - structure for measuring fps periodicity * @frame_count : Total frames during configured periodic duration @@ -158,6 +159,7 @@ struct sde_crtc_event { * @time_buf : Buffer for storing ktime of the commits * @next_time_index : index into time_buf for storing ktime for next commit */ + struct sde_crtc_fps_info { u32 frame_count; ktime_t last_sampled_time_us; diff --git a/drivers/gpu/drm/msm/sde/sde_hw_dspp.c b/drivers/gpu/drm/msm/sde/sde_hw_dspp.c index 92fea0dc49ca..4451301cb4e2 100644 --- a/drivers/gpu/drm/msm/sde/sde_hw_dspp.c +++ b/drivers/gpu/drm/msm/sde/sde_hw_dspp.c @@ -60,13 +60,11 @@ static void _setup_dspp_ops(struct sde_hw_dspp *c, unsigned long features) c->ops.setup_pcc = sde_setup_dspp_pcc_v1_7; else if (c->cap->sblk->pcc.version == (SDE_COLOR_PROCESS_VER(0x4, 0x0))) { -#if 0 ret = reg_dmav1_init_dspp_op_v4(i, c->idx); if (!ret) c->ops.setup_pcc = reg_dmav1_setup_dspp_pccv4; else -#endif c->ops.setup_pcc = sde_setup_dspp_pccv4; } diff --git a/drivers/gpu/drm/msm/sde/sde_hw_mdss.h b/drivers/gpu/drm/msm/sde/sde_hw_mdss.h index 7174a5d303d9..9b4e03d65098 100644 --- a/drivers/gpu/drm/msm/sde/sde_hw_mdss.h +++ b/drivers/gpu/drm/msm/sde/sde_hw_mdss.h @@ -89,11 +89,11 @@ enum sde_format_flags { #define SDE_VSYNC_SOURCE_INTF_1 4 #define SDE_VSYNC_SOURCE_INTF_2 5 #define SDE_VSYNC_SOURCE_INTF_3 6 -#define SDE_VSYNC_SOURCE_WD_TIMER_4 0x11 -#define SDE_VSYNC_SOURCE_WD_TIMER_3 0x12 -#define SDE_VSYNC_SOURCE_WD_TIMER_2 0x13 -#define SDE_VSYNC_SOURCE_WD_TIMER_1 0x14 -#define SDE_VSYNC_SOURCE_WD_TIMER_0 0x15 +#define SDE_VSYNC_SOURCE_WD_TIMER_4 11 +#define SDE_VSYNC_SOURCE_WD_TIMER_3 12 +#define SDE_VSYNC_SOURCE_WD_TIMER_2 13 +#define SDE_VSYNC_SOURCE_WD_TIMER_1 14 +#define SDE_VSYNC_SOURCE_WD_TIMER_0 15 enum sde_hw_blk_type { SDE_HW_BLK_TOP = 0, diff --git a/drivers/gpu/drm/msm/sde/sde_kms.c b/drivers/gpu/drm/msm/sde/sde_kms.c index 4871e8dc7b4b..847baeb9e02b 100644 --- a/drivers/gpu/drm/msm/sde/sde_kms.c +++ b/drivers/gpu/drm/msm/sde/sde_kms.c @@ -1330,7 +1330,7 @@ static int _sde_kms_setup_displays(struct drm_device *dev, .get_dst_format = dsi_display_get_dst_format, .enable_event = dsi_conn_enable_event, .cmd_transfer = NULL, - .cont_splash_config = dsi_display_cont_splash_config, + .cont_splash_config = NULL, }; struct msm_display_info info; struct drm_encoder *encoder; diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c b/drivers/gpu/drm/nouveau/nouveau_fence.c index 4bb9ab892ae1..78e521d00251 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fence.c +++ b/drivers/gpu/drm/nouveau/nouveau_fence.c @@ -158,7 +158,7 @@ nouveau_fence_wait_uevent_handler(struct nvif_notify *notify) fence = list_entry(fctx->pending.next, typeof(*fence), head); chan = rcu_dereference_protected(fence->channel, lockdep_is_held(&fctx->lock)); - if (nouveau_fence_update(fence->channel, fctx)) + if (nouveau_fence_update(chan, fctx)) ret = NVIF_NOTIFY_DROP; } spin_unlock_irqrestore(&fctx->lock, flags); diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c index 9d90d8b4b7e6..f5a8db1bb8b7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c @@ -72,6 +72,8 @@ nv50_disp_chan_mthd(struct nv50_disp_chan *chan, int debug) if (debug > subdev->debug) return; + if (!mthd) + return; for (i = 0; (list = mthd->data[i].mthd) != NULL; i++) { u32 base = chan->head * mthd->addr; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c index de8b806b88fd..7618b2eb4fdf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c @@ -143,23 +143,24 @@ gk20a_gr_av_to_method(struct gf100_gr *gr, const char *fw_name, nent = (fuc.size / sizeof(struct gk20a_fw_av)); - pack = vzalloc((sizeof(*pack) * max_classes) + - (sizeof(*init) * (nent + 1))); + pack = vzalloc((sizeof(*pack) * (max_classes + 1)) + + (sizeof(*init) * (nent + max_classes + 1))); if (!pack) { ret = -ENOMEM; goto end; } - init = (void *)(pack + max_classes); + init = (void *)(pack + max_classes + 1); - for (i = 0; i < nent; i++) { - struct gf100_gr_init *ent = &init[i]; + for (i = 0; i < nent; i++, init++) { struct gk20a_fw_av *av = &((struct gk20a_fw_av *)fuc.data)[i]; u32 class = av->addr & 0xffff; u32 addr = (av->addr & 0xffff0000) >> 14; if (prevclass != class) { - pack[classidx].init = ent; + if (prevclass) /* Add terminator to the method list. */ + init++; + pack[classidx].init = init; pack[classidx].type = class; prevclass = class; if (++classidx >= max_classes) { @@ -169,10 +170,10 @@ gk20a_gr_av_to_method(struct gf100_gr *gr, const char *fw_name, } } - ent->addr = addr; - ent->data = av->data; - ent->count = 1; - ent->pitch = 1; + init->addr = addr; + init->data = av->data; + init->count = 1; + init->pitch = 1; } *ppack = pack; diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index 8b6f8aa23806..432ad7d73cb9 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -110,6 +110,8 @@ static void dce5_crtc_load_lut(struct drm_crtc *crtc) DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id); + msleep(10); + WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset, (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) | NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS))); diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf_res.c b/drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf_res.c index 1f013d45c9e9..0c7c3005594c 100644 --- a/drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf_res.c +++ b/drivers/gpu/drm/vmwgfx/vmwgfx_cmdbuf_res.c @@ -210,8 +210,10 @@ int vmw_cmdbuf_res_add(struct vmw_cmdbuf_res_manager *man, cres->hash.key = user_key | (res_type << 24); ret = drm_ht_insert_item(&man->resources, &cres->hash); - if (unlikely(ret != 0)) + if (unlikely(ret != 0)) { + kfree(cres); goto out_invalid_key; + } cres->state = VMW_CMDBUF_RES_ADD; cres->res = vmw_resource_reference(res); diff --git a/drivers/gpu/msm/Makefile b/drivers/gpu/msm/Makefile index 3bb25dee7ff8..005822672101 100644 --- a/drivers/gpu/msm/Makefile +++ b/drivers/gpu/msm/Makefile @@ -28,8 +28,16 @@ msm_adreno-y += \ adreno_snapshot.o \ adreno_coresight.o \ adreno_trace.o \ + adreno_a3xx.o \ + adreno_a4xx.o \ + adreno_a5xx.o \ adreno_a6xx.o \ + adreno_a3xx_snapshot.o \ + adreno_a4xx_snapshot.o \ + adreno_a5xx_snapshot.o \ adreno_a6xx_snapshot.o \ + adreno_a4xx_preempt.o \ + adreno_a5xx_preempt.o \ adreno_a6xx_preempt.o \ adreno_sysfs.o \ adreno.o \ diff --git a/drivers/gpu/msm/adreno-gpulist.h b/drivers/gpu/msm/adreno-gpulist.h index 2b988742fd70..0a5933432399 100644 --- a/drivers/gpu/msm/adreno-gpulist.h +++ b/drivers/gpu/msm/adreno-gpulist.h @@ -14,6 +14,348 @@ #define ANY_ID (~0) static const struct adreno_gpu_core adreno_gpulist[] = { + { + .gpurev = ADRENO_REV_A306, + .core = 3, + .major = 0, + .minor = 6, + .patchid = 0x00, + .features = ADRENO_SOFT_FAULT_DETECT, + .pm4fw_name = "a300_pm4.fw", + .pfpfw_name = "a300_pfp.fw", + .gpudev = &adreno_a3xx_gpudev, + .gmem_size = SZ_128K, + .busy_mask = 0x7FFFFFFE, + }, + { + .gpurev = ADRENO_REV_A306A, + .core = 3, + .major = 0, + .minor = 6, + .patchid = 0x20, + .features = ADRENO_SOFT_FAULT_DETECT, + .pm4fw_name = "a300_pm4.fw", + .pfpfw_name = "a300_pfp.fw", + .gpudev = &adreno_a3xx_gpudev, + .gmem_size = SZ_128K, + .busy_mask = 0x7FFFFFFE, + }, + { + .gpurev = ADRENO_REV_A304, + .core = 3, + .major = 0, + .minor = 4, + .patchid = 0x00, + .features = ADRENO_SOFT_FAULT_DETECT, + .pm4fw_name = "a300_pm4.fw", + .pfpfw_name = "a300_pfp.fw", + .gpudev = &adreno_a3xx_gpudev, + .gmem_size = (SZ_64K + SZ_32K), + .busy_mask = 0x7FFFFFFE, + }, + { + .gpurev = ADRENO_REV_A405, + .core = 4, + .major = 0, + .minor = 5, + .patchid = ANY_ID, + .features = ADRENO_SOFT_FAULT_DETECT, + .pm4fw_name = "a420_pm4.fw", + .pfpfw_name = "a420_pfp.fw", + .gpudev = &adreno_a4xx_gpudev, + .gmem_size = SZ_256K, + .busy_mask = 0x7FFFFFFE, + }, + { + .gpurev = ADRENO_REV_A420, + .core = 4, + .major = 2, + .minor = 0, + .patchid = ANY_ID, + .features = ADRENO_USES_OCMEM | ADRENO_WARM_START | + ADRENO_USE_BOOTSTRAP | ADRENO_SOFT_FAULT_DETECT, + .pm4fw_name = "a420_pm4.fw", + .pfpfw_name = "a420_pfp.fw", + .gpudev = &adreno_a4xx_gpudev, + .gmem_size = (SZ_1M + SZ_512K), + .pm4_jt_idx = 0x901, + .pm4_jt_addr = 0x300, + .pfp_jt_idx = 0x401, + .pfp_jt_addr = 0x400, + .pm4_bstrp_size = 0x06, + .pfp_bstrp_size = 0x28, + .pfp_bstrp_ver = 0x4ff083, + .busy_mask = 0x7FFFFFFE, + }, + { + .gpurev = ADRENO_REV_A430, + .core = 4, + .major = 3, + .minor = 0, + .patchid = ANY_ID, + .features = ADRENO_USES_OCMEM | ADRENO_WARM_START | + ADRENO_USE_BOOTSTRAP | ADRENO_SPTP_PC | ADRENO_PPD | + ADRENO_CONTENT_PROTECTION | ADRENO_PREEMPTION | + ADRENO_SOFT_FAULT_DETECT, + .pm4fw_name = "a420_pm4.fw", + .pfpfw_name = "a420_pfp.fw", + .gpudev = &adreno_a4xx_gpudev, + .gmem_size = (SZ_1M + SZ_512K), + .pm4_jt_idx = 0x901, + .pm4_jt_addr = 0x300, + .pfp_jt_idx = 0x401, + .pfp_jt_addr = 0x400, + .pm4_bstrp_size = 0x06, + .pfp_bstrp_size = 0x28, + .pfp_bstrp_ver = 0x4ff083, + .shader_offset = 0x20000, + .shader_size = 0x10000, + .num_protected_regs = 0x18, + .busy_mask = 0x7FFFFFFE, + }, + { + .gpurev = ADRENO_REV_A418, + .core = 4, + .major = 1, + .minor = 8, + .patchid = ANY_ID, + .features = ADRENO_USES_OCMEM | ADRENO_WARM_START | + ADRENO_USE_BOOTSTRAP | ADRENO_SPTP_PC | + ADRENO_SOFT_FAULT_DETECT, + .pm4fw_name = "a420_pm4.fw", + .pfpfw_name = "a420_pfp.fw", + .gpudev = &adreno_a4xx_gpudev, + .gmem_size = (SZ_512K), + .pm4_jt_idx = 0x901, + .pm4_jt_addr = 0x300, + .pfp_jt_idx = 0x401, + .pfp_jt_addr = 0x400, + .pm4_bstrp_size = 0x06, + .pfp_bstrp_size = 0x28, + .pfp_bstrp_ver = 0x4ff083, + .shader_offset = 0x20000, /* SP and TP addresses */ + .shader_size = 0x10000, + .num_protected_regs = 0x18, + .busy_mask = 0x7FFFFFFE, + }, + { + .gpurev = ADRENO_REV_A530, + .core = 5, + .major = 3, + .minor = 0, + .patchid = 0, + .pm4fw_name = "a530v1_pm4.fw", + .pfpfw_name = "a530v1_pfp.fw", + .gpudev = &adreno_a5xx_gpudev, + .gmem_size = SZ_1M, + .num_protected_regs = 0x20, + .busy_mask = 0xFFFFFFFE, + }, + { + .gpurev = ADRENO_REV_A530, + .core = 5, + .major = 3, + .minor = 0, + .patchid = 1, + .features = ADRENO_GPMU | ADRENO_SPTP_PC | ADRENO_LM | + ADRENO_PREEMPTION | ADRENO_64BIT | + ADRENO_CONTENT_PROTECTION, + .pm4fw_name = "a530_pm4.fw", + .pfpfw_name = "a530_pfp.fw", + .zap_name = "a530_zap", + .gpudev = &adreno_a5xx_gpudev, + .gmem_size = SZ_1M, + .num_protected_regs = 0x20, + .gpmufw_name = "a530_gpmu.fw2", + .gpmu_major = 1, + .gpmu_minor = 0, + .busy_mask = 0xFFFFFFFE, + .lm_major = 3, + .lm_minor = 0, + .gpmu_tsens = 0x00060007, + .max_power = 5448, + .regfw_name = "a530v2_seq.fw2", + }, + { + .gpurev = ADRENO_REV_A530, + .core = 5, + .major = 3, + .minor = 0, + .patchid = ANY_ID, + .features = ADRENO_GPMU | ADRENO_SPTP_PC | ADRENO_LM | + ADRENO_PREEMPTION | ADRENO_64BIT | + ADRENO_CONTENT_PROTECTION, + .pm4fw_name = "a530_pm4.fw", + .pfpfw_name = "a530_pfp.fw", + .zap_name = "a530_zap", + .gpudev = &adreno_a5xx_gpudev, + .gmem_size = SZ_1M, + .num_protected_regs = 0x20, + .gpmufw_name = "a530v3_gpmu.fw2", + .gpmu_major = 1, + .gpmu_minor = 0, + .busy_mask = 0xFFFFFFFE, + .lm_major = 1, + .lm_minor = 0, + .gpmu_tsens = 0x00060007, + .max_power = 5448, + .regfw_name = "a530v3_seq.fw2", + }, + { + .gpurev = ADRENO_REV_A504, + .core = 5, + .major = 0, + .minor = 4, + .patchid = ANY_ID, + .features = ADRENO_PREEMPTION | ADRENO_64BIT, + .pm4fw_name = "a530_pm4.fw", + .pfpfw_name = "a530_pfp.fw", + .gpudev = &adreno_a5xx_gpudev, + .gmem_size = (SZ_128K + SZ_8K), + .num_protected_regs = 0x20, + .busy_mask = 0xFFFFFFFE, + }, + { + .gpurev = ADRENO_REV_A505, + .core = 5, + .major = 0, + .minor = 5, + .patchid = ANY_ID, + .features = ADRENO_PREEMPTION | ADRENO_64BIT | + ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION, + .pm4fw_name = "a530_pm4.fw", + .pfpfw_name = "a530_pfp.fw", + .zap_name = "a506_zap", + .gpudev = &adreno_a5xx_gpudev, + .gmem_size = (SZ_128K + SZ_8K), + .num_protected_regs = 0x20, + .busy_mask = 0xFFFFFFFE, + }, + { + .gpurev = ADRENO_REV_A506, + .core = 5, + .major = 0, + .minor = 6, + .patchid = ANY_ID, + .features = ADRENO_PREEMPTION | ADRENO_64BIT | + ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION, + .pm4fw_name = "a530_pm4.fw", + .pfpfw_name = "a530_pfp.fw", + .zap_name = "a506_zap", + .gpudev = &adreno_a5xx_gpudev, + .gmem_size = (SZ_128K + SZ_8K), + .num_protected_regs = 0x20, + .busy_mask = 0xFFFFFFFE, + }, + { + .gpurev = ADRENO_REV_A510, + .core = 5, + .major = 1, + .minor = 0, + .patchid = ANY_ID, + .pm4fw_name = "a530_pm4.fw", + .pfpfw_name = "a530_pfp.fw", + .gpudev = &adreno_a5xx_gpudev, + .gmem_size = SZ_256K, + .num_protected_regs = 0x20, + .busy_mask = 0xFFFFFFFE, + }, + { + .gpurev = ADRENO_REV_A540, + .core = 5, + .major = 4, + .minor = 0, + .patchid = 0, + .features = ADRENO_PREEMPTION | ADRENO_64BIT | + ADRENO_CONTENT_PROTECTION | + ADRENO_GPMU | ADRENO_SPTP_PC, + .pm4fw_name = "a530_pm4.fw", + .pfpfw_name = "a530_pfp.fw", + .zap_name = "a540_zap", + .gpudev = &adreno_a5xx_gpudev, + .gmem_size = SZ_1M, + .num_protected_regs = 0x20, + .busy_mask = 0xFFFFFFFE, + .gpmufw_name = "a540_gpmu.fw2", + .gpmu_major = 3, + .gpmu_minor = 0, + .gpmu_tsens = 0x000C000D, + .max_power = 5448, + }, + { + .gpurev = ADRENO_REV_A540, + .core = 5, + .major = 4, + .minor = 0, + .patchid = ANY_ID, + .features = ADRENO_PREEMPTION | ADRENO_64BIT | + ADRENO_CONTENT_PROTECTION | + ADRENO_GPMU | ADRENO_SPTP_PC, + .pm4fw_name = "a530_pm4.fw", + .pfpfw_name = "a530_pfp.fw", + .zap_name = "a540_zap", + .gpudev = &adreno_a5xx_gpudev, + .gmem_size = SZ_1M, + .num_protected_regs = 0x20, + .busy_mask = 0xFFFFFFFE, + .gpmufw_name = "a540_gpmu.fw2", + .gpmu_major = 3, + .gpmu_minor = 0, + .gpmu_tsens = 0x000C000D, + .max_power = 5448, + }, + { + .gpurev = ADRENO_REV_A512, + .core = 5, + .major = 1, + .minor = 2, + .patchid = ANY_ID, + .features = ADRENO_PREEMPTION | ADRENO_64BIT | + ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION, + .pm4fw_name = "a530_pm4.fw", + .pfpfw_name = "a530_pfp.fw", + .zap_name = "a512_zap", + .gpudev = &adreno_a5xx_gpudev, + .gmem_size = (SZ_256K + SZ_16K), + .num_protected_regs = 0x20, + .busy_mask = 0xFFFFFFFE, + }, + { + .gpurev = ADRENO_REV_A508, + .core = 5, + .major = 0, + .minor = 8, + .patchid = ANY_ID, + .features = ADRENO_PREEMPTION | ADRENO_64BIT | + ADRENO_CONTENT_PROTECTION | ADRENO_CPZ_RETENTION, + .pm4fw_name = "a530_pm4.fw", + .pfpfw_name = "a530_pfp.fw", + .zap_name = "a508_zap", + .gpudev = &adreno_a5xx_gpudev, + .gmem_size = (SZ_128K + SZ_8K), + .num_protected_regs = 0x20, + .busy_mask = 0xFFFFFFFE, + }, + { + .gpurev = ADRENO_REV_A630, + .core = 6, + .major = 3, + .minor = 0, + .patchid = 0, + .features = ADRENO_64BIT | ADRENO_RPMH | + ADRENO_GPMU | ADRENO_CONTENT_PROTECTION | ADRENO_LM, + .sqefw_name = "a630_sqe.fw", + .zap_name = "a630_zap", + .gpudev = &adreno_a6xx_gpudev, + .gmem_size = SZ_1M, + .num_protected_regs = 0x20, + .busy_mask = 0xFFFFFFFE, + .gpmufw_name = "a630_gmu.bin", + .gpmu_major = 0x1, + .gpmu_minor = 0x003, + .gpmu_tsens = 0x000C000D, + .max_power = 5448, + }, { .gpurev = ADRENO_REV_A630, .core = 6, diff --git a/drivers/gpu/msm/adreno.c b/drivers/gpu/msm/adreno.c index a1879dabefc2..ea2240cb1609 100644 --- a/drivers/gpu/msm/adreno.c +++ b/drivers/gpu/msm/adreno.c @@ -1184,7 +1184,7 @@ static int adreno_of_get_power(struct adreno_device *adreno_dev, device->pwrctrl.pm_qos_wakeup_latency = 101; if (of_property_read_u32(node, "qcom,idle-timeout", &timeout)) - timeout = 64; + timeout = 80; device->pwrctrl.interval_timeout = msecs_to_jiffies(timeout); @@ -1786,6 +1786,13 @@ int adreno_set_unsecured_mode(struct adreno_device *adreno_dev, if (!adreno_is_a5xx(adreno_dev) && !adreno_is_a6xx(adreno_dev)) return -EINVAL; + if (ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_CRITICAL_PACKETS) && + adreno_is_a5xx(adreno_dev)) { + ret = a5xx_critical_packet_submit(adreno_dev, rb); + if (ret) + return ret; + } + /* GPU comes up in secured mode, make it unsecured by default */ if (adreno_dev->zap_loaded) ret = adreno_switch_to_unsecure_mode(adreno_dev, rb); @@ -3062,9 +3069,6 @@ int adreno_spin_idle(struct adreno_device *adreno_dev, unsigned int timeout) if (adreno_isidle(KGSL_DEVICE(adreno_dev))) return 0; - /* relax tight loop */ - cond_resched(); - } while (time_before(jiffies, wait)); /* diff --git a/drivers/gpu/msm/adreno.h b/drivers/gpu/msm/adreno.h index 5cdc5571a5e2..3b5dd88d63f8 100644 --- a/drivers/gpu/msm/adreno.h +++ b/drivers/gpu/msm/adreno.h @@ -1088,6 +1088,9 @@ extern unsigned int *adreno_ft_regs; extern unsigned int adreno_ft_regs_num; extern unsigned int *adreno_ft_regs_val; +extern struct adreno_gpudev adreno_a3xx_gpudev; +extern struct adreno_gpudev adreno_a4xx_gpudev; +extern struct adreno_gpudev adreno_a5xx_gpudev; extern struct adreno_gpudev adreno_a6xx_gpudev; extern int adreno_wake_nice; diff --git a/drivers/gpu/msm/adreno_cp_parser.h b/drivers/gpu/msm/adreno_cp_parser.h index d879e5079f7c..1fa46c147c3c 100644 --- a/drivers/gpu/msm/adreno_cp_parser.h +++ b/drivers/gpu/msm/adreno_cp_parser.h @@ -15,6 +15,9 @@ #include "adreno.h" +extern const unsigned int a3xx_cp_addr_regs[]; +extern const unsigned int a4xx_cp_addr_regs[]; + /* * struct adreno_ib_object - Structure containing information about an * address range found in an IB @@ -131,7 +134,15 @@ static inline void adreno_ib_init_ib_obj(uint64_t gpuaddr, static inline int adreno_cp_parser_getreg(struct adreno_device *adreno_dev, enum adreno_cp_addr_regs reg_enum) { - return -EEXIST; + if (reg_enum == ADRENO_CP_ADDR_MAX) + return -EEXIST; + + if (adreno_is_a3xx(adreno_dev)) + return a3xx_cp_addr_regs[reg_enum]; + else if (adreno_is_a4xx(adreno_dev)) + return a4xx_cp_addr_regs[reg_enum]; + else + return -EEXIST; } /* @@ -149,6 +160,19 @@ static inline int adreno_cp_parser_regindex(struct adreno_device *adreno_dev, enum adreno_cp_addr_regs start, enum adreno_cp_addr_regs end) { + int i; + const unsigned int *regs; + + if (adreno_is_a4xx(adreno_dev)) + regs = a4xx_cp_addr_regs; + else if (adreno_is_a3xx(adreno_dev)) + regs = a3xx_cp_addr_regs; + else + return -EEXIST; + + for (i = start; i <= end && i < ADRENO_CP_ADDR_MAX; i++) + if (regs[i] == offset) + return i; return -EEXIST; } diff --git a/drivers/gpu/msm/adreno_snapshot.c b/drivers/gpu/msm/adreno_snapshot.c index 5a006fdbc259..178369171cb0 100644 --- a/drivers/gpu/msm/adreno_snapshot.c +++ b/drivers/gpu/msm/adreno_snapshot.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -910,17 +910,34 @@ void adreno_snapshot(struct kgsl_device *device, struct kgsl_snapshot *snapshot, * The problem is that IB size from the register is the unprocessed size * of the buffer not the original size, so if we didn't catch this * buffer being directly used in the RB, then we might not be able to - * dump the whole thing. Print a warning message so we can try to + * dump the whole thing. Try to dump the maximum possible size from the + * IB1 base address till the end of memdesc size so that we dont miss + * what we are interested in. Print a warning message so we can try to * figure how often this really happens. */ if (-ENOENT == find_object(snapshot->ib1base, snapshot->process) && snapshot->ib1size) { - kgsl_snapshot_push_object(snapshot->process, snapshot->ib1base, - snapshot->ib1size); - KGSL_CORE_ERR( - "CP_IB1_BASE not found in the ringbuffer.Dumping %x dwords of the buffer.\n", - snapshot->ib1size); + struct kgsl_mem_entry *entry; + u64 ibsize; + + entry = kgsl_sharedmem_find(snapshot->process, + snapshot->ib1base); + if (entry == NULL) { + KGSL_CORE_ERR( + "Can't find a memory entry containing IB1BASE %16llx\n", + snapshot->ib1base); + } else { + ibsize = entry->memdesc.size - + (snapshot->ib1base - entry->memdesc.gpuaddr); + kgsl_mem_entry_put(entry); + + kgsl_snapshot_push_object(snapshot->process, + snapshot->ib1base, ibsize >> 2); + KGSL_CORE_ERR( + "CP_IB1_BASE is not found in the ringbuffer. Dumping %llx dwords of the buffer\n", + ibsize >> 2); + } } /* @@ -1228,4 +1245,3 @@ void adreno_snapshot_vbif_registers(struct kgsl_device *device, snapshot, kgsl_snapshot_dump_registers, ®s); } } - diff --git a/drivers/gpu/msm/kgsl.c b/drivers/gpu/msm/kgsl.c index e07905449fcd..66102af23356 100644 --- a/drivers/gpu/msm/kgsl.c +++ b/drivers/gpu/msm/kgsl.c @@ -4898,7 +4898,7 @@ static void kgsl_core_exit(void) static int __init kgsl_core_init(void) { int result = 0; - struct sched_param param = { .sched_priority = 16 }; + struct sched_param param = { .sched_priority = 2 }; /* alloc major and minor device numbers */ result = alloc_chrdev_region(&kgsl_driver.major, 0, KGSL_DEVICE_MAX, diff --git a/drivers/gpu/msm/kgsl_debugfs.c b/drivers/gpu/msm/kgsl_debugfs.c index 43baf851227b..834706a973d2 100644 --- a/drivers/gpu/msm/kgsl_debugfs.c +++ b/drivers/gpu/msm/kgsl_debugfs.c @@ -410,6 +410,8 @@ void kgsl_process_init_debugfs(struct kgsl_process_private *private) */ if (IS_ERR_OR_NULL(private->debug_root)) { + WARN((private->debug_root == NULL), + "Unable to create debugfs dir for %s\n", name); private->debug_root = NULL; return; } diff --git a/drivers/gpu/msm/kgsl_pwrctrl.c b/drivers/gpu/msm/kgsl_pwrctrl.c index a8971c4bea19..85e1bf8531ea 100644 --- a/drivers/gpu/msm/kgsl_pwrctrl.c +++ b/drivers/gpu/msm/kgsl_pwrctrl.c @@ -2473,9 +2473,8 @@ void kgsl_idle_check(struct work_struct *work) requested_state = device->requested_state; - if ((requested_state != KGSL_STATE_NONE) && - (device->state == KGSL_STATE_ACTIVE - || device->state == KGSL_STATE_NAP)) { + if (device->state == KGSL_STATE_ACTIVE + || device->state == KGSL_STATE_NAP) { if (!atomic_read(&device->active_cnt)) { spin_lock(&device->submit_lock); diff --git a/drivers/gpu/msm/kgsl_pwrctrl.h b/drivers/gpu/msm/kgsl_pwrctrl.h index afa5e50f799e..23fbc2ec1883 100644 --- a/drivers/gpu/msm/kgsl_pwrctrl.h +++ b/drivers/gpu/msm/kgsl_pwrctrl.h @@ -55,9 +55,9 @@ /* * The effective duration of qos request in usecs at queue time. * After timeout, qos request is cancelled automatically. - * Kept 64ms default, inline with default GPU idle time. + * Kept 80ms default, inline with default GPU idle time. */ -#define KGSL_L2PC_QUEUE_TIMEOUT (64 * 1000) +#define KGSL_L2PC_QUEUE_TIMEOUT (80 * 1000) /* * The effective duration of qos request in usecs at wakeup time. diff --git a/drivers/halls/halls.c b/drivers/halls/halls.c index d5794ecda3c3..a87618f8bf35 100644 --- a/drivers/halls/halls.c +++ b/drivers/halls/halls.c @@ -1,308 +1,174 @@ #include -#include -#include -#include #include -#include #include #include #include -#include #include #include +#include -#include +#define HALLS_DEVICE_NAME "halls" +#define HALLS_GPIO_FIRST 49 +#define HALLS_GPIO_SECOND 113 -#define HALLS_LOG printk - -#define LOGTAG "halls " -#define DEF_HALLS_DEVICE_NAME "halls" - -#define DEF_HALLS_IOCTRL_READ_HALL_1 1000 -#define DEF_HALLS_IOCTRL_READ_HALL_2 2000 -#define DEF_HALLS_IOCTRL_FLUSH 3000 +enum { + KEYCODE_SLIDER_UP = 594, + KEYCODE_SLIDER_DOWN, +}; -#define DEF_HALLS_IOCTRL_STEUP 4000 -#define DEF_HALLS_IOCTRL_RELEASE 5000 +enum { + STATE_SLIDER_UP = 0, + STATE_SLIDER_DOWN, + STATE_SLIDER_SLIDING, +}; -#define DEF_HALL_IRQ_1_FIRED "h-1" -#define DEF_HALL_IRQ_2_FIRED "h-2" -#define DEF_HALL_FLUSH "flu" +struct halls_data { + struct delayed_work notify_work; + struct wakeup_source *wakelock; + struct input_dev *input; -#define DEF_HALL_GPIO_1 49 -#define DEF_HALL_GPIO_2 113 + int first_gpio; + int second_gpio; +}; extern int elliptic_set_hall_state(int state); +static void halls_send_input(struct halls_data *hdata, int state) { + int keycode; + + if (state == STATE_SLIDER_UP) + keycode = KEYCODE_SLIDER_UP; + else if (state == STATE_SLIDER_DOWN) + keycode = KEYCODE_SLIDER_DOWN; + else + return; + + input_report_key(hdata->input, keycode, 1); + input_sync(hdata->input); + input_report_key(hdata->input, keycode, 0); + input_sync(hdata->input); +} -static int g_gpio_1_irq; -static int g_gpio_2_irq; -static int g_in_firedirq; -static int g_in_end; -static int g_in_flush; - -static int g_in_opencounter; +static void halls_notify_work_func(struct work_struct *work) { + struct halls_data *hdata = container_of(to_delayed_work(work), + struct halls_data, notify_work); + int first_value, second_value; + int state; -struct _hall_device { - struct miscdevice miscdev; - struct delayed_work notify_work; - struct wakeup_source *hall_wakelock; - int hall_status; -}; + first_value = gpio_get_value_cansleep(hdata->first_gpio); + second_value = gpio_get_value_cansleep(hdata->second_gpio); -struct _hall_device *g_st_halls; -struct semaphore g_st_semhallirq; - -static void hall_notify_work_func(struct work_struct *work) -{ - int iRet1 = 0, iRet2 = 0; - iRet1 = gpio_get_value_cansleep(DEF_HALL_GPIO_1); - iRet2 = gpio_get_value_cansleep(DEF_HALL_GPIO_2); - HALLS_LOG(LOGTAG "g_in_firedirq %d, g_gpio_1_irq %d, g_gpio_2_irq %d", - g_in_firedirq, g_gpio_1_irq, g_gpio_2_irq); - HALLS_LOG(LOGTAG " iRet1 %d iRet2 %d", iRet1, iRet2); - if (iRet1 == 0 && iRet2 == 1) { - g_st_halls->hall_status = 1; - } else if (iRet1 == 1 && iRet2 == 0) { - g_st_halls->hall_status = 0; - } else { - g_st_halls->hall_status = 2; - } + if (first_value == 1 && second_value == 0) + state = STATE_SLIDER_UP; + else if (first_value == 0 && second_value == 1) + state = STATE_SLIDER_DOWN; + else + state = STATE_SLIDER_SLIDING; - HALLS_LOG(LOGTAG "hall_notify_work_func notify audio hall_status: %d!", - g_st_halls->hall_status); - elliptic_set_hall_state(g_st_halls->hall_status); + elliptic_set_hall_state(state); + halls_send_input(hdata, state); } -static irqreturn_t halls_irq_handler(int irqno, void *dev_id) -{ - HALLS_LOG(LOGTAG "Entered halls_irq_handler irqno %d\n", irqno); - __pm_wakeup_event(g_st_halls->hall_wakelock, 20); - g_in_firedirq = irqno; - up(&g_st_semhallirq); - schedule_delayed_work(&g_st_halls->notify_work, 0); +static irqreturn_t halls_irq_handler(int irqno, void *dev_id) { + struct halls_data *hdata = dev_id; + __pm_wakeup_event(hdata->wakelock, 20); + schedule_delayed_work(&hdata->notify_work, 0); return 0; } -static int halls_configurate_input(int in_GPIO, const char *ch_mark) -{ - int iRet = 0; +static int halls_configure_irq(struct halls_data *hdata, int gpio, const char *label) { + int ret, irq; - iRet = gpio_request(in_GPIO, ch_mark); - if (iRet) - pr_err("%d is being used!\n", in_GPIO); + ret = gpio_request(gpio, label); + if (ret) { + pr_err("%s: failed to request GPIO %d\n", __func__, gpio); + return ret; + } - iRet = gpio_direction_input(in_GPIO); - if (iRet) - pr_err("Setting hall gpio direction failed! iRet %d\n", iRet); + ret = gpio_direction_input(gpio); + if (ret) { + pr_err("%s: failed to set GPIO %d direction to input\n", __func__, gpio); + return ret; + } - return iRet; -} + irq = gpio_to_irq(gpio); + ret = request_irq(irq, halls_irq_handler, + IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING + | IRQF_ONESHOT, label, hdata); + if (ret) { + pr_err("%s: failed to configure GPIO %d IRQ\n", __func__, gpio); + return ret; + } -static int halls_configurate_irq(int in_GPIO, - const char *ch_mark, void *arg, int *out_irq) -{ - int iRet = 0, in_IRQ = 0; - - in_IRQ = gpio_to_irq(in_GPIO); - *out_irq = in_IRQ; - HALLS_LOG(LOGTAG "in_GPIO %d, IRQ %d\n", in_GPIO, in_IRQ); - iRet = request_irq(in_IRQ, halls_irq_handler, - IRQF_TRIGGER_RISING - | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, ch_mark, arg); - if (iRet) - pr_err("request_irq failed! iRet %d\n", iRet); - irq_set_irq_wake(in_IRQ, 1); - - HALLS_LOG(LOGTAG "request_irq return %d\n", iRet); - return iRet; + irq_set_irq_wake(irq, 1); + + return 0; } -static ssize_t halls_read(struct file *file, - char __user *buf, size_t count, loff_t *ppos) -{ - int iRead = 0; +static int __init halls_init(void) { + struct halls_data *hdata; + int ret; - HALLS_LOG(LOGTAG "Entereed halls_read count %d", (int)count); - if (down_interruptible(&g_st_semhallirq)) { - HALLS_LOG(LOGTAG "down_interruptible failed!"); - } - if (g_in_end == 1) { - HALLS_LOG(LOGTAG "Ending... "); - return -EPERM; - } - HALLS_LOG(LOGTAG "g_in_firedirq %d, g_gpio_1_irq %d, g_gpio_2_irq %d", - g_in_firedirq, g_gpio_1_irq, g_gpio_2_irq); - if (g_in_flush == 1) { - g_in_flush = 0; - iRead = - copy_to_user(buf, DEF_HALL_FLUSH, strlen(DEF_HALL_FLUSH)); - HALLS_LOG(LOGTAG "End of copy_to_user flash... "); - } else if (g_in_firedirq == g_gpio_1_irq) { - iRead = copy_to_user(buf, DEF_HALL_IRQ_1_FIRED, - strlen(DEF_HALL_IRQ_1_FIRED)); - HALLS_LOG(LOGTAG "End of copy_to_user 1... "); - } else if (g_in_firedirq == g_gpio_2_irq) { - iRead = copy_to_user(buf, DEF_HALL_IRQ_2_FIRED, - strlen(DEF_HALL_IRQ_2_FIRED)); - HALLS_LOG(LOGTAG "End of copy_to_user 2... "); + hdata = kzalloc(sizeof(*hdata), GFP_KERNEL); + if (!hdata) { + pr_err("%s: failed to allocate memory for driver data\n", __func__); + ret = -ENOMEM; + goto exit; } - return iRead; -} -long halls_in_ioctl(struct file *file, unsigned int cmd, unsigned long arg) -{ - int iRet = 0; - void *p_ReadValue = (void *)arg; - char ch_data[10] = { 0 }; - - HALLS_LOG(LOGTAG "Enter halls_in_ioctl cmd %d", cmd); - switch (cmd) { - case DEF_HALLS_IOCTRL_READ_HALL_1: - { - iRet = gpio_get_value_cansleep(DEF_HALL_GPIO_1); - HALLS_LOG(LOGTAG "Read HALL_1 %d", iRet); - snprintf(ch_data, sizeof(ch_data), "%d", iRet); - iRet = - copy_to_user(p_ReadValue, ch_data, strlen(ch_data)); - break; - } - case DEF_HALLS_IOCTRL_READ_HALL_2: - { - iRet = gpio_get_value_cansleep(DEF_HALL_GPIO_2); - HALLS_LOG(LOGTAG "Read HALL_2 %d", iRet); - snprintf(ch_data, sizeof(ch_data), "%d", iRet); - iRet = - copy_to_user(p_ReadValue, ch_data, strlen(ch_data)); - break; - } - case DEF_HALLS_IOCTRL_FLUSH: - { - g_in_flush = 1; - up(&g_st_semhallirq); - schedule_delayed_work(&g_st_halls->notify_work, 0); - break; - } - case DEF_HALLS_IOCTRL_STEUP: - { - if (g_in_opencounter == 0) { - g_in_end = 0; - sema_init(&g_st_semhallirq, 0); - iRet = - halls_configurate_irq(DEF_HALL_GPIO_1, - "hall-1", - (void *)g_st_halls, - &g_gpio_1_irq); - if (iRet) - pr_err - ("halls_configurate_irq failed!%d, iRet %d\n", - DEF_HALL_GPIO_1, iRet); - g_in_firedirq = g_gpio_1_irq; - - iRet = - halls_configurate_irq(DEF_HALL_GPIO_2, - "hall-2", - (void *)g_st_halls, - &g_gpio_2_irq); - if (iRet) - pr_err - ("halls_configurate_irq failed! %d iRet %d\n", - DEF_HALL_GPIO_2, iRet); - - HALLS_LOG(LOGTAG - "g_gpio_2_irq %d, g_gpio_2_irq %d\n", - g_gpio_1_irq, g_gpio_2_irq); - g_in_opencounter = 1; - } - break; - } - case DEF_HALLS_IOCTRL_RELEASE: - { - g_in_end = 1; - up(&g_st_semhallirq); - if (g_gpio_1_irq > 0) - free_irq(g_gpio_1_irq, g_st_halls); - - if (g_gpio_2_irq > 0) - free_irq(g_gpio_2_irq, g_st_halls); - g_in_opencounter = 0; - break; - } - default: - iRet = -1; + hdata->input = input_allocate_device(); + if (!hdata->input) { + pr_err("%s: failed to allocate memory for input device\n", __func__); + ret = -ENOMEM; + goto free_halls; } - HALLS_LOG(LOGTAG "read value cmd %d, iRet %d", cmd, iRet); - return iRet; -} -int halls_flush(struct file *file, fl_owner_t id) -{ - HALLS_LOG(LOGTAG " Entered halls_flush \n"); - return 0; -} + hdata->input->name = HALLS_DEVICE_NAME; + input_set_drvdata(hdata->input, hdata); -int halls_open(struct inode *node, struct file *file) -{ - int iRet = 0; + set_bit(EV_KEY, hdata->input->evbit); + set_bit(KEYCODE_SLIDER_UP, hdata->input->keybit); + set_bit(KEYCODE_SLIDER_DOWN, hdata->input->keybit); - return iRet; -} + ret = input_register_device(hdata->input); + if (ret) { + pr_err("%s: failed to register input device\n", __func__); + goto free_input; + } -static const struct file_operations halls_fops = { - .owner = THIS_MODULE, - .read = halls_read, - .unlocked_ioctl = halls_in_ioctl, - .flush = halls_flush, - .open = halls_open -}; + hdata->first_gpio = HALLS_GPIO_FIRST; + hdata->second_gpio = HALLS_GPIO_SECOND; -static int __init halls_init(void) -{ - int ret; - g_st_halls = kzalloc(sizeof(struct _hall_device), GFP_KERNEL); - if (!g_st_halls) - return -ENOMEM; - g_st_halls->miscdev.fops = &halls_fops; - g_st_halls->miscdev.minor = MISC_DYNAMIC_MINOR; - g_st_halls->miscdev.name = DEF_HALLS_DEVICE_NAME; - ret = misc_register(&g_st_halls->miscdev); - if (ret < 0) { - kfree(g_st_halls); - return ret; - } - ret = halls_configurate_input(DEF_HALL_GPIO_1, "hall-1"); + ret = halls_configure_irq(hdata, hdata->first_gpio, "halls-first"); if (ret) { - pr_err("halls_configurate_input failed!%d, ret %d\n", - DEF_HALL_GPIO_1, ret); - gpio_free(DEF_HALL_GPIO_1); - return ret; + goto unregister_input; } - ret = halls_configurate_input(DEF_HALL_GPIO_2, "hall-2"); + + ret = halls_configure_irq(hdata, hdata->second_gpio, "halls-second"); if (ret) { - pr_err("halls_configurate_input failed! %d ret %d\n", - DEF_HALL_GPIO_2, ret); - gpio_free(DEF_HALL_GPIO_2); - return ret; + goto unregister_input; } - g_st_halls->hall_status = 0; - INIT_DELAYED_WORK(&g_st_halls->notify_work, hall_notify_work_func); + INIT_DELAYED_WORK(&hdata->notify_work, halls_notify_work_func); - g_st_halls->hall_wakelock = wakeup_source_register("dual_hall_ws"); - if (!g_st_halls->hall_wakelock) { - pr_err("g_st_halls wakeup_source_register failed!\n"); - return ret; + hdata->wakelock = wakeup_source_register("halls-ws"); + if (!hdata->wakelock) { + pr_err("%s: failed to register wakeup source\n", __func__); + ret = -EINVAL; + goto unregister_input; } + return 0; + +unregister_input: + input_unregister_device(hdata->input); +free_input: + input_free_device(hdata->input); +free_halls: + kfree(hdata); +exit: return ret; } device_initcall(halls_init); -static void __exit halls_exit(void) -{ - gpio_free(DEF_HALL_GPIO_1); - gpio_free(DEF_HALL_GPIO_2); -} - -module_exit(halls_exit); MODULE_LICENSE("GPL v2"); diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig index da7eb28d6524..086ab8e91744 100644 --- a/drivers/input/Kconfig +++ b/drivers/input/Kconfig @@ -200,14 +200,6 @@ config INPUT_KEYCOMBO ---help--- Say Y here if you want to take action when some keys are pressed; -config POCKET_JUDGE - bool "Pocket Judge" - depends on INPUT - default n - help - Enables and disables interrupts based on pocket state to optimize - battery consumption in-pocket. - comment "Input Device Drivers" source "drivers/input/keyboard/Kconfig" diff --git a/drivers/input/Makefile b/drivers/input/Makefile index 14a92b1c9082..3352867f6738 100644 --- a/drivers/input/Makefile +++ b/drivers/input/Makefile @@ -5,7 +5,6 @@ # Each configuration option enables a list of files. obj-$(CONFIG_INPUT) += input-core.o -obj-$(CONFIG_POCKET_JUDGE) += pocket-judge.o input-core-y := input.o input-compat.o input-mt.o ff-core.o obj-$(CONFIG_INPUT_FF_MEMLESS) += ff-memless.o diff --git a/drivers/input/fingerprint/fpc_tee/fpc1020_tee.c b/drivers/input/fingerprint/fpc_tee/fpc1020_tee.c index d0b55d4cd74f..8c8b3577c5eb 100644 --- a/drivers/input/fingerprint/fpc_tee/fpc1020_tee.c +++ b/drivers/input/fingerprint/fpc_tee/fpc1020_tee.c @@ -68,7 +68,7 @@ struct vreg_config { int ua_load; }; -static const struct vreg_config vreg_conf[] = { +static const struct vreg_config const vreg_conf[] = { { "vdd_ana", 1800000UL, 1800000UL, 6000, }, { "fp_vdd_vreg", 3000000UL, 3000000UL, 6000, }, /*{ "vcc_spi", 1800000UL, 1800000UL, 10, },*/ diff --git a/drivers/input/fingerprint/goodix_ta/gf_spi.c b/drivers/input/fingerprint/goodix_ta/gf_spi.c index 8bf18d7fc253..fb3a9bf72e3b 100644 --- a/drivers/input/fingerprint/goodix_ta/gf_spi.c +++ b/drivers/input/fingerprint/goodix_ta/gf_spi.c @@ -680,6 +680,38 @@ static const struct file_operations gf_fops = { #endif }; +static ssize_t proximity_state_set(struct device *dev, + struct device_attribute *attr, const char *buf, size_t count) +{ + struct gf_dev *gf_dev = dev_get_drvdata(dev); + int rc, val; + + rc = kstrtoint(buf, 10, &val); + if (rc) + return -EINVAL; + + gf_dev->proximity_state = !!val; + + if (gf_dev->proximity_state) { + gf_disable_irq(gf_dev); + } else { + gf_enable_irq(gf_dev); + } + + return count; +} + +static DEVICE_ATTR(proximity_state, S_IWUSR, NULL, proximity_state_set); + +static struct attribute *attributes[] = { + &dev_attr_proximity_state.attr, + NULL +}; + +static const struct attribute_group attribute_group = { + .attrs = attributes, +}; + static int goodix_fb_state_chg_callback(struct notifier_block *nb, unsigned long val, void *data) { @@ -743,6 +775,7 @@ static int gf_probe(struct platform_device *pdev) #endif { struct gf_dev *gf_dev = &gf; + struct device *dev = &pdev->dev; int status = -EINVAL; unsigned long minor; int i; @@ -827,6 +860,14 @@ static int gf_probe(struct platform_device *pdev) gf_dev->irq = gf_irq_num(gf_dev); + dev_set_drvdata(dev, gf_dev); + + status = sysfs_create_group(&dev->kobj, &attribute_group); + if (status) { + dev_err(dev, "could not create sysfs\n"); + goto error_hw; + } + wakeup_source_init(&fp_wakelock, "fp_wakelock"); pr_debug("version V%d.%d.%02d\n", VER_MAJOR, VER_MINOR, PATCH_LEVEL); diff --git a/drivers/input/fingerprint/goodix_ta/gf_spi.h b/drivers/input/fingerprint/goodix_ta/gf_spi.h index 7bd6574b9ed6..7a1eeec30620 100644 --- a/drivers/input/fingerprint/goodix_ta/gf_spi.h +++ b/drivers/input/fingerprint/goodix_ta/gf_spi.h @@ -143,6 +143,7 @@ struct gf_dev { #ifdef CONFIG_FINGERPRINT_FP_VREG_CONTROL struct regulator *vreg; #endif + int proximity_state; /* 0:far 1:near */ }; int gf_parse_dts(struct gf_dev *gf_dev); diff --git a/drivers/input/pocket-judge.c b/drivers/input/pocket-judge.c deleted file mode 100644 index 01cb8ebfc3dd..000000000000 --- a/drivers/input/pocket-judge.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright 2017 Paranoid Android - * - * The code contained herein is licensed under the GNU General Public - * License. You may obtain a copy of the GNU General Public License - * Version 2 or later at the following locations: - * - * http://www.opensource.org/licenses/gpl-license.html - * http://www.gnu.org/copyleft/gpl.html - */ -#include -#include -#include -#include -#include - -#include "touchscreen/synaptics_driver_s3320_custom.h" -#include "fingerprint/fpc/fpc1020_tee_custom.h" - -/** - * This driver maintains a sysfs interface used by the pocket bridge system - * service. It enables and disables interrupts based on pocket state to - * optimize battery consumption in-pocket. - * - * @author Chris Lahaye - * @hide - */ - -static bool pocket_judge_inpocket = false; -EXPORT_SYMBOL(pocket_judge_inpocket); - -static void pocket_judge_update(void) -{ - synaptics_s3320_enable_global(!pocket_judge_inpocket); - fpc1020_enable_global(!pocket_judge_inpocket); -} - -static ssize_t inpocket_show(struct device *dev, struct device_attribute *attr, - char *buf) -{ - return sprintf(buf, "%u\n", pocket_judge_inpocket); -} - -static ssize_t inpocket_store(struct device *dev, struct device_attribute *attr, - const char *buf, size_t size) -{ - bool state; - ssize_t ret; - - ret = strtobool(buf, &state); - if (ret) - return size; - - if (pocket_judge_inpocket != state) { - pocket_judge_inpocket = state; - pocket_judge_update(); - } - - return size; -} - -static DEVICE_ATTR_RW(inpocket); - -static struct attribute *pocket_judge_class_attrs[] = { - &dev_attr_inpocket.attr, - NULL, -}; - -static const struct attribute_group pocket_judge_attr_group = { - .attrs = pocket_judge_class_attrs, -}; - -static struct kobject *pocket_judge_kobj; - -static int __init pocket_judge_init(void) -{ - ssize_t ret; - - pocket_judge_kobj = kobject_create_and_add("pocket_judge", kernel_kobj); - if (!pocket_judge_kobj) - return -ENOMEM; - - ret = sysfs_create_group(pocket_judge_kobj, &pocket_judge_attr_group); - if (ret) - kobject_put(pocket_judge_kobj); - - return ret; -} - -static void __exit pocket_judge_exit (void) -{ - kobject_put(pocket_judge_kobj); -} - -module_init(pocket_judge_init); -module_exit(pocket_judge_exit); diff --git a/drivers/input/touchscreen/atmel_mxt_ts.c b/drivers/input/touchscreen/atmel_mxt_ts.c index 463f6da2ea02..de67bdaac5b9 100644 --- a/drivers/input/touchscreen/atmel_mxt_ts.c +++ b/drivers/input/touchscreen/atmel_mxt_ts.c @@ -6819,6 +6819,8 @@ static int mxt_remove(struct i2c_client *client) g_mxt_data = NULL; + disable_irq(data->irq); + return 0; } diff --git a/drivers/input/touchscreen/cyttsp4_core.c b/drivers/input/touchscreen/cyttsp4_core.c index 44deca88c579..c1c29d7487bf 100644 --- a/drivers/input/touchscreen/cyttsp4_core.c +++ b/drivers/input/touchscreen/cyttsp4_core.c @@ -1972,11 +1972,6 @@ static int cyttsp4_mt_probe(struct cyttsp4 *cd) /* get sysinfo */ md->si = &cd->sysinfo; - if (!md->si) { - dev_err(dev, "%s: Fail get sysinfo pointer from core p=%p\n", - __func__, md->si); - goto error_get_sysinfo; - } rc = cyttsp4_setup_input_device(cd); if (rc) @@ -1986,8 +1981,6 @@ static int cyttsp4_mt_probe(struct cyttsp4 *cd) error_init_input: input_free_device(md->input); -error_get_sysinfo: - input_set_drvdata(md->input, NULL); error_alloc_failed: dev_err(dev, "%s failed.\n", __func__); return rc; diff --git a/drivers/input/touchscreen/focaltech_touch/focaltech_common.h b/drivers/input/touchscreen/focaltech_touch/focaltech_common.h index b2a90c14a239..25b00928dc90 100644 --- a/drivers/input/touchscreen/focaltech_touch/focaltech_common.h +++ b/drivers/input/touchscreen/focaltech_touch/focaltech_common.h @@ -55,10 +55,7 @@ #define FTS_CHIP_IDC ((FTS_CHIP_TYPE & FLAGBIT(FLAG_IDC_BIT)) == FLAGBIT(FLAG_IDC_BIT)) #define FTS_HID_SUPPORTTED ((FTS_CHIP_TYPE & FLAGBIT(FLAG_HID_BIT)) == FLAGBIT(FLAG_HID_BIT)) -#define FTS_CHIP_TYPE_MAPPING {\ - {0x0D, 0x87, 0x19, 0x87, 0x19, 0x87, 0xA9, 0x87, 0xB9},\ - {0x81, 0x54, 0x52, 0x54, 0x52, 0x00, 0x00, 0x54, 0x5c},\ -} +#define FTS_CHIP_TYPE_MAPPING {{0x0D,0x87, 0x19, 0x87, 0x19, 0x87, 0xA9, 0x87, 0xB9}} #define I2C_BUFFER_LENGTH_MAXINUM 256 #define FILE_NAME_LENGTH 128 @@ -98,12 +95,6 @@ #define FTS_REG_MODULE_ID 0xE3 #define FTS_REG_LIC_VER 0xE4 #define FTS_REG_ESD_SATURATE 0xED -#define FTS_REG_SENSIVITY 0x81 -#define FTS_REG_THDIFF 0x85 -#define FTS_REG_MONITOR_MODE 0x86 -#define FTS_REG_REPORT_RATE 0x88 -#define FTS_REG_EDGE_FILTER_ORIENTATION 0x8C -#define FTS_REG_EDGE_FILTER_LEVEL 0x8D #define FTS_SYSFS_ECHO_ON(buf) (buf[0] == '1') #define FTS_SYSFS_ECHO_OFF(buf) (buf[0] == '0') diff --git a/drivers/input/touchscreen/focaltech_touch/focaltech_config.h b/drivers/input/touchscreen/focaltech_touch/focaltech_config.h index 34e0847e4593..d397030f5683 100644 --- a/drivers/input/touchscreen/focaltech_touch/focaltech_config.h +++ b/drivers/input/touchscreen/focaltech_touch/focaltech_config.h @@ -114,7 +114,7 @@ * Report Pressure in multitouch * 1:enable(default),0:disable */ -#define FTS_REPORT_PRESSURE_EN 0 +#define FTS_REPORT_PRESSURE_EN 1 /* * Gesture function enable @@ -128,12 +128,6 @@ */ #define FTS_ESDCHECK_EN 0 -/* - * Production test enable - * 1: enable, 0:disable(default) - */ -#define FTS_TEST_EN 1 - /* * Glove mode enable * 1: enable, 0:disable(default) @@ -148,7 +142,7 @@ * Charger enable * 1: enable, 0:disable(default) */ -#define FTS_CHARGER_EN 1 +#define FTS_CHARGER_EN 0 /* * Nodes for tools, please keep enable @@ -187,8 +181,7 @@ * 0:No check vendor_id (default) * 1/2/3: Check vendor_id for vendor compatibility */ -#define FTS_PROJECT_NAME "e10" -#define FTS_PROJECT_NAME1 "e5" +#define FTS_GET_VENDOR_ID_NUM 0 /* * vendor_id(s) for vendor(s) to be compatible with. @@ -208,8 +201,7 @@ * define your own fw_file, the sample one to be replaced is invalid * NOTE: if FTS_GET_VENDOR_ID_NUM > 1, it's the fw corresponding with FTS_VENDOR_ID */ -#define FTS_UPGRADE_FW_FILE_E10 "include/firmware/fw_ft8719_e10.i" -#define FTS_UPGRADE_FW_FILE_E5 "include/firmware/fw_ft3518_e5.i" +#define FTS_UPGRADE_FW_FILE "include/firmware/fw_ft8719_e10.i" /* * if FTS_GET_VENDOR_ID_NUM >= 2, fw corrsponding with FTS_VENDOR_ID2 diff --git a/drivers/input/touchscreen/focaltech_touch/focaltech_core.c b/drivers/input/touchscreen/focaltech_touch/focaltech_core.c index 0be17c1b6b20..f610f4622a30 100644 --- a/drivers/input/touchscreen/focaltech_touch/focaltech_core.c +++ b/drivers/input/touchscreen/focaltech_touch/focaltech_core.c @@ -42,9 +42,6 @@ #define FTS_SUSPEND_LEVEL 1 /* Early-suspend level */ #endif #include -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE -#include "../xiaomi/xiaomi_touch.h" -#endif /***************************************************************************** * Private constant and macro definitions using #define @@ -89,27 +86,10 @@ static int fts_ts_suspend(struct device *dev); static int fts_ts_resume(struct device *dev); static void fts_resume_work(struct work_struct *work); static void fts_suspend_work(struct work_struct *work); -extern const char *dsi_get_display_name(void); -#if FTS_CHARGER_EN -extern int fts_charger_mode_set(struct i2c_client *client, bool on); -#endif -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_SENSOR -static int fts_palm_enable(struct fts_ts_data *fts_data, int on); -static int fts_read_palm_data(void); -#endif - -struct device *fts_get_dev(void) -{ - if (!fts_data) - return NULL; - else - return &(fts_data->client->dev); -} /***************************************************************************** * Name: fts_wait_tp_to_valid * Brief: Read chip id until TP FW become valid(Timeout: TIMEOUT_READ_REG), -* this threshold is read from devicetree, pdata->timeout_read_reg * need call when reset/power on/resume... * Input: * Output: @@ -132,7 +112,7 @@ int fts_wait_tp_to_valid(struct i2c_client *client) } cnt++; msleep(INTERVAL_READ_REG); - } while ((cnt * INTERVAL_READ_REG) < fts_data->pdata->timeout_read_reg); + } while ((cnt * INTERVAL_READ_REG) < TIMEOUT_READ_REG); return -EIO; } @@ -209,9 +189,9 @@ static int fts_get_ic_information(struct fts_ts_data *ts_data) cnt++; msleep(INTERVAL_READ_REG); - } while ((cnt * INTERVAL_READ_REG) < fts_data->pdata->timeout_read_reg); + } while ((cnt * INTERVAL_READ_REG) < TIMEOUT_READ_REG); - if ((cnt * INTERVAL_READ_REG) >= fts_data->pdata->timeout_read_reg) { + if ((cnt * INTERVAL_READ_REG) >= TIMEOUT_READ_REG) { FTS_INFO("fw is invalid, need read boot id"); if (ts_data->ic_info.hid_supported) { fts_i2c_hid2std(client); @@ -385,13 +365,6 @@ static int fts_power_source_init(struct fts_ts_data *data) } } - data->avdd = regulator_get(&data->client->dev, "avdd"); - if (IS_ERR(data->avdd)) { - ret = PTR_ERR(data->avdd); - FTS_ERROR("get vddio regulator failed,ret=%d", ret); - return ret; - } - data->vsp = regulator_get(&data->client->dev, "lab"); if (IS_ERR(data->vsp)) { ret = PTR_ERR(data->vsp); @@ -439,10 +412,6 @@ static int fts_power_source_ctrl(struct fts_ts_data *data, int enable) FTS_FUNC_ENTER(); if (enable) { if (data->power_disabled) { - ret = regulator_enable(data->avdd); - if (ret) { - FTS_ERROR("enable avdd regulator failed,ret=%d", ret); - } ret = regulator_enable(data->vddio); if (ret) { FTS_ERROR("enable vddio regulator failed,ret=%d", ret); @@ -461,10 +430,6 @@ static int fts_power_source_ctrl(struct fts_ts_data *data, int enable) } } else { if (!data->power_disabled) { - ret = regulator_disable(data->avdd); - if (ret) { - FTS_ERROR("disable avdd regulator failed,ret=%d", ret); - } ret = regulator_disable(data->vddio); if (ret) { FTS_ERROR("disable vddio regulator failed,ret=%d", ret); @@ -856,10 +821,6 @@ static int fts_read_touchdata(struct fts_ts_data *data) #if FTS_POINT_REPORT_CHECK_EN fts_prc_queue_work(data); #endif -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_SENSOR - if (data->palm_sensor_switch) - fts_read_palm_data(); -#endif data->point_num = 0; data->touch_point = 0; @@ -1224,308 +1185,6 @@ static int fts_gpio_configure(struct fts_ts_data *data) FTS_FUNC_EXIT(); return ret; } -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE -static struct xiaomi_touch_interface xiaomi_touch_interfaces; -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_SENSOR -static int fts_read_palm_data(void) -{ - int ret; - u8 reg_value; - - ret = fts_i2c_read_reg(fts_data->client, 0x9b, ®_value); - if (ret < 0) { - FTS_ERROR("read palm reg error"); - return ret; - } else - update_palm_sensor_value(!!reg_value); - return 0; -} - -static int fts_palm_enable(struct fts_ts_data *fts_data, int on) -{ - int retval; - unsigned char enable; - unsigned char palm_on = 0x05; - unsigned char palm_off = 0x00; - - enable = on > 0 ? 1 : 0; - - FTS_INFO("%s on:%d\n", __func__, on); - - if (on) - retval = fts_i2c_write_reg(fts_data->client, 0x9A, palm_on); - else - retval = fts_i2c_write_reg(fts_data->client, 0x9A, palm_off); - - if (retval < 0) - return -EINVAL; - - return 0; -} - -static int fts_palmsensor_enable(int on) -{ - int ret = 0; - - if (!fts_data) - return -EINVAL; - fts_data->palm_sensor_switch = on; - if (fts_data->suspended) { - FTS_ERROR("%s tp has suspended\n", __func__); - fts_data->palm_sensor_changed = false; - return 0; - } - - ret = fts_palm_enable(fts_data, on); - if (!ret) - fts_data->palm_sensor_changed = true; - return ret; -} -#endif - -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_GAMEMODE -static void fts_init_touchmode_data(void) -{ - int i; - int ret; - u8 reg_value; - - /* Touch Game Mode Switch */ - xiaomi_touch_interfaces.touch_mode[Touch_Game_Mode][GET_DEF_VALUE] = 0; - xiaomi_touch_interfaces.touch_mode[Touch_Game_Mode][GET_MAX_VALUE] = 1; - xiaomi_touch_interfaces.touch_mode[Touch_Game_Mode][GET_MIN_VALUE] = 0; - xiaomi_touch_interfaces.touch_mode[Touch_Game_Mode][SET_CUR_VALUE] = 0; - xiaomi_touch_interfaces.touch_mode[Touch_Game_Mode][GET_CUR_VALUE] = 0; - - /* Acitve Mode */ - xiaomi_touch_interfaces.touch_mode[Touch_Active_MODE][GET_MAX_VALUE] = 1; - xiaomi_touch_interfaces.touch_mode[Touch_Active_MODE][GET_MIN_VALUE] = 0; - xiaomi_touch_interfaces.touch_mode[Touch_Active_MODE][GET_DEF_VALUE] = 0; - xiaomi_touch_interfaces.touch_mode[Touch_Active_MODE][SET_CUR_VALUE] = 0; - xiaomi_touch_interfaces.touch_mode[Touch_Active_MODE][GET_CUR_VALUE] = 0; - - /* sensivity */ - ret = fts_i2c_read_reg(fts_data->client, FTS_REG_SENSIVITY, ®_value); - if (ret < 0) { - FTS_ERROR("read sensivity reg error"); - } - xiaomi_touch_interfaces.touch_mode[Touch_UP_THRESHOLD][GET_MAX_VALUE] = 50; - xiaomi_touch_interfaces.touch_mode[Touch_UP_THRESHOLD][GET_MIN_VALUE] = 35; - xiaomi_touch_interfaces.touch_mode[Touch_UP_THRESHOLD][GET_DEF_VALUE] = reg_value; - xiaomi_touch_interfaces.touch_mode[Touch_UP_THRESHOLD][SET_CUR_VALUE] = 0; - xiaomi_touch_interfaces.touch_mode[Touch_UP_THRESHOLD][GET_CUR_VALUE] = reg_value; - - /* Tolerance */ - ret = fts_i2c_read_reg(fts_data->client, FTS_REG_THDIFF, ®_value); - if (ret < 0) { - FTS_ERROR("read reg thdiff error"); - } - xiaomi_touch_interfaces.touch_mode[Touch_Tolerance][GET_MAX_VALUE] = 255; - xiaomi_touch_interfaces.touch_mode[Touch_Tolerance][GET_MIN_VALUE] = 64; - xiaomi_touch_interfaces.touch_mode[Touch_Tolerance][GET_DEF_VALUE] = reg_value; - xiaomi_touch_interfaces.touch_mode[Touch_Tolerance][SET_CUR_VALUE] = 0; - xiaomi_touch_interfaces.touch_mode[Touch_Tolerance][GET_CUR_VALUE] = reg_value; - /* edge filter orientation*/ - xiaomi_touch_interfaces.touch_mode[Touch_Panel_Orientation][GET_MAX_VALUE] = 3; - xiaomi_touch_interfaces.touch_mode[Touch_Panel_Orientation][GET_MIN_VALUE] = 0; - xiaomi_touch_interfaces.touch_mode[Touch_Panel_Orientation][GET_DEF_VALUE] = 0; - xiaomi_touch_interfaces.touch_mode[Touch_Panel_Orientation][SET_CUR_VALUE] = 0; - xiaomi_touch_interfaces.touch_mode[Touch_Panel_Orientation][GET_CUR_VALUE] = 0; - - /* edge filter area*/ - xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][GET_MAX_VALUE] = 3; - xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][GET_MIN_VALUE] = 0; - xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][GET_DEF_VALUE] = 0; - xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][SET_CUR_VALUE] = 0; - xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][GET_CUR_VALUE] = 0; - - - for (i = 0; i < Touch_Mode_NUM; i++) { - FTS_INFO("mode:%d, set cur:%d, get cur:%d, def:%d min:%d max:%d\n", - i, - xiaomi_touch_interfaces.touch_mode[i][SET_CUR_VALUE], - xiaomi_touch_interfaces.touch_mode[i][GET_CUR_VALUE], - xiaomi_touch_interfaces.touch_mode[i][GET_DEF_VALUE], - xiaomi_touch_interfaces.touch_mode[i][GET_MIN_VALUE], - xiaomi_touch_interfaces.touch_mode[i][GET_MAX_VALUE]); - } - - return; -} - -static void fts_update_touchmode_data(int mode) -{ - u8 temp_value; - int ret; - - if (xiaomi_touch_interfaces.touch_mode[mode][GET_CUR_VALUE] != - xiaomi_touch_interfaces.touch_mode[mode][SET_CUR_VALUE]) { - - xiaomi_touch_interfaces.touch_mode[mode][GET_CUR_VALUE] = - xiaomi_touch_interfaces.touch_mode[mode][SET_CUR_VALUE]; - FTS_ERROR("%s: mode:%d changed, value:%d\n", __func__, mode, - xiaomi_touch_interfaces.touch_mode[mode][SET_CUR_VALUE]); - } else { - FTS_ERROR("%s: mode:%d not changed, set_value:%d, get_value:%d\n", __func__, mode, - xiaomi_touch_interfaces.touch_mode[mode][SET_CUR_VALUE], xiaomi_touch_interfaces.touch_mode[mode][GET_CUR_VALUE]); - return; - } - temp_value = (u8)xiaomi_touch_interfaces.touch_mode[mode][SET_CUR_VALUE]; - switch (mode) { - case Touch_Game_Mode: - /*enable touch game mode,set tp into active mode, set high report rate*/ - if (temp_value == 1) { - ret = fts_i2c_write_reg(fts_data->client, FTS_REG_MONITOR_MODE, 0); - if (ret < 0) - FTS_ERROR("disable monitor mode error, ret=%d\n", ret); - fts_data->gamemode_enabled = true; - } else { - /*restore touch parameters */ - ret = fts_i2c_write_reg(fts_data->client, FTS_REG_MONITOR_MODE, 1); - if (ret < 0) - FTS_ERROR("restore monitor mode error, ret=%d\n", ret); - ret = fts_i2c_write_reg(fts_data->client, FTS_REG_SENSIVITY, (u8)xiaomi_touch_interfaces.touch_mode[Touch_UP_THRESHOLD][GET_DEF_VALUE]); - if (ret < 0) - FTS_ERROR("restore sensitivity error, ret=%d\n", ret); - ret = fts_i2c_write_reg(fts_data->client, FTS_REG_THDIFF, (u8)xiaomi_touch_interfaces.touch_mode[Touch_Tolerance][GET_DEF_VALUE]); - if (ret < 0) - FTS_ERROR("restore touch smooth error, ret=%d\n", ret); - ret = fts_i2c_write_reg(fts_data->client, FTS_REG_EDGE_FILTER_ORIENTATION, (u8)xiaomi_touch_interfaces.touch_mode[Touch_Panel_Orientation][GET_DEF_VALUE]); - if (ret < 0) - FTS_ERROR("restore orientation error, ret=%d\n", ret); - ret = fts_i2c_write_reg(fts_data->client, FTS_REG_EDGE_FILTER_LEVEL, (u8)xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][GET_DEF_VALUE]); - if (ret < 0) - FTS_ERROR("restore orientation error, ret=%d\n", ret); - fts_data->gamemode_enabled = false; - } - break; - case Touch_Active_MODE: - break; - case Touch_UP_THRESHOLD: - if (fts_data->gamemode_enabled) { - ret = fts_i2c_write_reg(fts_data->client, FTS_REG_SENSIVITY, temp_value); - if (ret < 0) - FTS_ERROR("write sensitivity error, ret=%d\n", ret); - } - break; - case Touch_Tolerance: - if (fts_data->gamemode_enabled) { - ret = fts_i2c_write_reg(fts_data->client, FTS_REG_THDIFF, temp_value); - if (ret < 0) - FTS_ERROR("write touch smooth error, ret=%d\n", ret); - } - break; - case Touch_Panel_Orientation: - if (temp_value == 0 || temp_value == 2) { - ret = fts_i2c_write_reg(fts_data->client, FTS_REG_EDGE_FILTER_ORIENTATION, 0); - if (ret < 0) - FTS_ERROR("write orientation error, ret=%d\n", ret); - } - if (temp_value == 1) { - ret = fts_i2c_write_reg(fts_data->client, FTS_REG_EDGE_FILTER_ORIENTATION, 1); - if (ret < 0) - FTS_ERROR("write orientation error, ret=%d\n", ret); - } - if (temp_value == 3) { - ret = fts_i2c_write_reg(fts_data->client, FTS_REG_EDGE_FILTER_ORIENTATION, 2); - if (ret < 0) - FTS_ERROR("write orientation error, ret=%d\n", ret); - } - break; - case Touch_Edge_Filter: - if (fts_data->gamemode_enabled) { - ret = fts_i2c_write_reg(fts_data->client, FTS_REG_EDGE_FILTER_LEVEL, temp_value); - if (ret < 0) - FTS_ERROR("write edge filter level error, ret=%d\n", ret); - } - break; - case Touch_Report_Rate: - break; - default: - break; - } -} - -static int fts_set_cur_value(int mode, int value) -{ - - if (mode < Touch_Mode_NUM) { - - xiaomi_touch_interfaces.touch_mode[mode][SET_CUR_VALUE] = value; - - if (xiaomi_touch_interfaces.touch_mode[mode][SET_CUR_VALUE] > - xiaomi_touch_interfaces.touch_mode[mode][GET_MAX_VALUE]) { - - xiaomi_touch_interfaces.touch_mode[mode][SET_CUR_VALUE] = - xiaomi_touch_interfaces.touch_mode[mode][GET_MAX_VALUE]; - - } else if (xiaomi_touch_interfaces.touch_mode[mode][SET_CUR_VALUE] < - xiaomi_touch_interfaces.touch_mode[mode][GET_MIN_VALUE]) { - - xiaomi_touch_interfaces.touch_mode[mode][SET_CUR_VALUE] = - xiaomi_touch_interfaces.touch_mode[mode][GET_MIN_VALUE]; - } - } else { - FTS_ERROR("%s, don't support\n", __func__); - } - FTS_INFO("%s, mode:%d, value:%d\n", __func__, mode, value); - - fts_update_touchmode_data(mode); - - return 0; -} - -static int fts_get_mode_value(int mode, int value_type) -{ - int value = -1; - - if (mode < Touch_Mode_NUM) - value = xiaomi_touch_interfaces.touch_mode[mode][value_type]; - else - FTS_ERROR("%s, don't support\n", __func__); - - return value; -} - -static int fts_get_mode_all(int mode, int *value) -{ - if (mode < Touch_Mode_NUM) { - value[0] = xiaomi_touch_interfaces.touch_mode[mode][GET_CUR_VALUE]; - value[1] = xiaomi_touch_interfaces.touch_mode[mode][GET_DEF_VALUE]; - value[2] = xiaomi_touch_interfaces.touch_mode[mode][GET_MIN_VALUE]; - value[3] = xiaomi_touch_interfaces.touch_mode[mode][GET_MAX_VALUE]; - } else { - FTS_ERROR("%s, don't support\n", __func__); - } - FTS_INFO("%s, mode:%d, value:%d:%d:%d:%d\n", __func__, mode, value[0], - value[1], value[2], value[3]); - - return 0; -} - -static int fts_reset_mode(int mode) -{ - int i = 0; - - if (mode < Touch_Mode_NUM && mode) { - xiaomi_touch_interfaces.touch_mode[mode][SET_CUR_VALUE] = - xiaomi_touch_interfaces.touch_mode[mode][GET_DEF_VALUE]; - } else if (mode == 0) { - for (i = 0; i < Touch_Mode_NUM; i++) { - xiaomi_touch_interfaces.touch_mode[i][SET_CUR_VALUE] = - xiaomi_touch_interfaces.touch_mode[i][GET_DEF_VALUE]; - } - } else { - FTS_ERROR("%s, don't support\n", __func__); - } - - FTS_ERROR("%s, mode:%d\n", __func__, mode); - fts_update_touchmode_data(mode); - - return 0; -} -#endif -#endif /***************************************************************************** * Name: fts_get_dt_coords @@ -1593,10 +1252,6 @@ static int fts_parse_dt(struct device *dev, struct fts_ts_platform_data *pdata) if (ret < 0) FTS_ERROR("Unable to get display-coords"); - ret = of_property_read_u32(np, "focaltech,timeout-read-reg", &pdata->timeout_read_reg); - if (ret) - FTS_ERROR("timeout-read_reg limit undefined!"); - /* key */ pdata->have_key = of_property_read_bool(np, "focaltech,have-key"); if (pdata->have_key) { @@ -1647,23 +1302,6 @@ static int fts_parse_dt(struct device *dev, struct fts_ts_platform_data *pdata) FTS_INFO("max touch number:%d, irq gpio:%d, reset gpio:%d", pdata->max_touch_number, pdata->irq_gpio, pdata->reset_gpio); - ret = of_property_read_string(np, "focaltech,project-name", &pdata->project_name); - if (!ret) - FTS_ERROR("Unable to get project name"); - else { - FTS_INFO("project name:%s\n", pdata->project_name); - } - ret = of_property_read_u32(np, "focaltech,lockdown-info-addr", &pdata->lockdown_info_addr); - if (!ret) - FTS_ERROR("Unable to get lockdown-info-addr"); - ret = of_property_read_u32(np, "focaltech,open-min", &pdata->open_min); - if (ret) - FTS_ERROR("selftest open min undefined!"); - - pdata->reset_when_resume = of_property_read_bool(np, "focaltech,reset-when-resume"); - pdata->check_display_name = of_property_read_bool(np, "focaltech,check-display-name"); - pdata->cutoff_power = of_property_read_bool(np, "focaltech,cutoff-power"); - FTS_FUNC_EXIT(); return 0; @@ -1868,36 +1506,6 @@ static const struct file_operations tpdbg_operations = { .release = tpdbg_release, }; -#ifdef CONFIG_TOUCHSCREEN_FTS_POWER_SUPPLY -static void fts_power_supply_work(struct work_struct *work) -{ - struct fts_ts_data *ts_data = container_of(work, struct fts_ts_data, power_supply_work); - int usb_charger; - - usb_charger = !!power_supply_is_system_supplied(); - if (usb_charger != ts_data->is_usb_exist || ts_data->is_usb_exist < 0) { - ts_data->is_usb_exist = usb_charger; - FTS_INFO("%s power supply is USB%d\n", __func__, usb_charger); - if (usb_charger) { - FTS_INFO("%s USB is exist\n", __func__); - fts_charger_mode_set(ts_data->client, true); - } else { - FTS_INFO("%s USB is not exist\n", __func__); - fts_charger_mode_set(ts_data->client, false); - } - } -} - -static int fts_power_supply_event(struct notifier_block *nb, unsigned long event, void *ptr) -{ - struct fts_ts_data *ts_data = container_of(nb, struct fts_ts_data, power_supply_notifier); - if (!ts_data) - return 0; - queue_work(ts_data->event_wq, &ts_data->power_supply_work); - return 0; -} -#endif - #ifdef CONFIG_DRM /***************************************************************************** * Name: fb_notifier_callback @@ -2005,7 +1613,6 @@ static int fts_ts_probe(struct i2c_client *client, const struct i2c_device_id *i struct fts_ts_platform_data *pdata; struct fts_ts_data *ts_data; struct dentry *tp_debugfs; - const char *display_name; FTS_FUNC_ENTER(); if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { @@ -2030,16 +1637,6 @@ static int fts_ts_probe(struct i2c_client *client, const struct i2c_device_id *i FTS_ERROR("no ts platform data found"); return -EINVAL; } - if (pdata->check_display_name) { - display_name = dsi_get_display_name(); - if (display_name) { - FTS_INFO("display_name:%s\n", display_name); - if (strncmp(display_name, "dsi_visionox", 12)) { - FTS_ERROR("not the right display, do not need to do probe\n"); - return -EINVAL; - } - } - } ts_data = devm_kzalloc(&client->dev, sizeof(*ts_data), GFP_KERNEL); if (!ts_data) { @@ -2103,7 +1700,6 @@ static int fts_ts_probe(struct i2c_client *client, const struct i2c_device_id *i ts_data->fw_forceupdate = true; else { FTS_ERROR("No focal touch found"); - ret = -ENODEV; goto err_irq_req; } } @@ -2181,10 +1777,6 @@ static int fts_ts_probe(struct i2c_client *client, const struct i2c_device_id *i } INIT_WORK(&ts_data->resume_work, fts_resume_work); INIT_WORK(&ts_data->suspend_work, fts_suspend_work); -#ifdef CONFIG_TOUCHSCREEN_FTS_POWER_SUPPLY - INIT_WORK(&ts_data->power_supply_work, fts_power_supply_work); - ts_data->is_usb_exist = -1; -#endif ret = fts_irq_registration(ts_data); if (ret) { @@ -2202,11 +1794,6 @@ static int fts_ts_probe(struct i2c_client *client, const struct i2c_device_id *i ts_data->dev_pm_suspend = false; init_completion(&ts_data->dev_pm_suspend_completion); -#ifdef CONFIG_TOUCHSCREEN_FTS_POWER_SUPPLY - ts_data->power_supply_notifier.notifier_call = fts_power_supply_event; - power_supply_reg_notifier(&ts_data->power_supply_notifier); -#endif - #ifdef CONFIG_DRM ts_data->fb_notif.notifier_call = fb_notifier_callback; ret = drm_register_client(&ts_data->fb_notif); @@ -2219,23 +1806,8 @@ static int fts_ts_probe(struct i2c_client *client, const struct i2c_device_id *i ts_data->early_suspend.resume = fts_ts_late_resume; register_early_suspend(&ts_data->early_suspend); #endif -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE - memset(&xiaomi_touch_interfaces, 0x00, sizeof(struct xiaomi_touch_interface)); -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_GAMEMODE - xiaomi_touch_interfaces.getModeValue = fts_get_mode_value; - xiaomi_touch_interfaces.setModeValue = fts_set_cur_value; - xiaomi_touch_interfaces.resetMode = fts_reset_mode; - xiaomi_touch_interfaces.getModeAll = fts_get_mode_all; - fts_init_touchmode_data(); -#endif -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_SENSOR - ts_data->tp_class = get_xiaomi_touch_class(); - if (ts_data->tp_class) { - xiaomi_touch_interfaces.palm_sensor_write = fts_palmsensor_enable; - } -#endif - xiaomitouch_register_modedata(&xiaomi_touch_interfaces); -#endif + update_hardware_info(TYPE_TOUCH, 3); + update_hardware_info(TYPE_TP_MAKER, ts_data->lockdown_info[0] - 0x30); FTS_FUNC_EXIT(); return 0; @@ -2376,14 +1948,7 @@ static int fts_ts_suspend(struct device *dev) #endif fts_irq_disable_sync(); - fts_release_all_finger(); -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_SENSOR - if (ts_data->palm_sensor_switch) { - update_palm_sensor_value(0); - fts_palm_enable(ts_data, 0); - fts_data->palm_sensor_switch = false; - } -#endif + #if FTS_GESTURE_EN if (fts_gesture_suspend(ts_data->client) == 0) { ts_data->suspended = true; @@ -2393,16 +1958,9 @@ static int fts_ts_suspend(struct device *dev) #endif #if FTS_POWER_SOURCE_CUST_EN - if (ts_data->pdata->cutoff_power) { - ret = fts_power_source_ctrl(ts_data, DISABLE); - if (ret < 0) { - FTS_ERROR("power off fail, ret=%d", ret); - } - } else { - /* TP enter sleep mode */ - ret = fts_i2c_write_reg(ts_data->client, FTS_REG_POWER_MODE, FTS_REG_POWER_MODE_SLEEP_VALUE); - if (ret < 0) - FTS_ERROR("set TP to sleep mode fail, ret=%d", ret); + ret = fts_power_source_ctrl(ts_data, DISABLE); + if (ret < 0) { + FTS_ERROR("power off fail, ret=%d", ret); } #if FTS_PINCTRL_EN fts_pinctrl_select_suspend(ts_data); @@ -2439,15 +1997,13 @@ static int fts_ts_resume(struct device *dev) fts_release_all_finger(); #if FTS_POWER_SOURCE_CUST_EN - if (ts_data->pdata->cutoff_power) - fts_power_source_ctrl(ts_data, ENABLE); + fts_power_source_ctrl(ts_data, ENABLE); #if FTS_PINCTRL_EN fts_pinctrl_select_normal(ts_data); #endif #endif - if (!ts_data->ic_info.is_incell || ts_data->pdata->reset_when_resume) { - FTS_INFO("reset when resume"); + if (!ts_data->ic_info.is_incell) { fts_reset_proc(200); } @@ -2460,23 +2016,11 @@ static int fts_ts_resume(struct device *dev) #if FTS_GESTURE_EN if (fts_gesture_resume(ts_data->client) == 0) { ts_data->suspended = false; -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_SENSOR - if (ts_data->palm_sensor_switch && !ts_data->palm_sensor_changed) { - fts_palm_enable(ts_data, 1); - ts_data->palm_sensor_changed = true; - } -#endif return 0; } #endif ts_data->suspended = false; -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_SENSOR - if (ts_data->palm_sensor_switch && !ts_data->palm_sensor_changed) { - fts_palm_enable(ts_data, 1); - ts_data->palm_sensor_changed = true; - } -#endif fts_irq_enable(); FTS_FUNC_EXIT(); @@ -2552,7 +2096,7 @@ static const struct i2c_device_id fts_ts_id[] = { MODULE_DEVICE_TABLE(i2c, fts_ts_id); static struct of_device_id fts_match_table[] = { - {.compatible = "focaltech,focal",}, + {.compatible = "focaltech,fts",}, {}, }; diff --git a/drivers/input/touchscreen/focaltech_touch/focaltech_core.h b/drivers/input/touchscreen/focaltech_touch/focaltech_core.h index 1291d6e29f01..0ee6f1c48ebc 100644 --- a/drivers/input/touchscreen/focaltech_touch/focaltech_core.h +++ b/drivers/input/touchscreen/focaltech_touch/focaltech_core.h @@ -67,8 +67,6 @@ #include #include #include "focaltech_common.h" -#include -#include /***************************************************************************** * Private constant and macro definitions using #define @@ -102,6 +100,7 @@ #define TOUCH_IN_KEY(x, key_x) TOUCH_IN_RANGE(x, key_x, FTS_KEY_WIDTH) #define FTS_LOCKDOWN_INFO_SIZE 8 +#define LOCKDOWN_INFO_ADDR 0x1FA0 /***************************************************************************** * Private enumerations, structures and unions using typedef *****************************************************************************/ @@ -120,13 +119,6 @@ struct fts_ts_platform_data { u32 x_min; u32 y_min; u32 max_touch_number; - u32 timeout_read_reg; - const char *project_name; - u32 open_min; - bool reset_when_resume; - u32 lockdown_info_addr; - bool check_display_name; - bool cutoff_power; }; struct ts_event { @@ -150,7 +142,6 @@ struct fts_ts_data { struct regulator *vsp; struct regulator *vsn; struct regulator *vddio; - struct regulator *avdd; spinlock_t irq_lock; struct mutex report_mutex; int irq; @@ -179,10 +170,6 @@ struct fts_ts_data { bool fw_forceupdate; struct work_struct suspend_work; struct work_struct resume_work; -#ifdef CONFIG_TOUCHSCREEN_FTS_POWER_SUPPLY - struct work_struct power_supply_work; - int is_usb_exist; -#endif struct workqueue_struct *event_wq; struct completion dev_pm_suspend_completion; #if FTS_PINCTRL_EN @@ -195,21 +182,12 @@ struct fts_ts_data { struct notifier_block fb_notif; #elif defined(CONFIG_HAS_EARLYSUSPEND) struct early_suspend early_suspend; -#endif -#ifdef CONFIG_TOUCHSCREEN_FTS_POWER_SUPPLY - struct notifier_block power_supply_notifier; #endif struct dentry *debugfs; struct proc_dir_entry *tp_selftest_proc; struct proc_dir_entry *tp_data_dump_proc; struct proc_dir_entry *tp_fw_version_proc; struct proc_dir_entry *tp_lockdown_info_proc; -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE - bool palm_sensor_switch; - bool palm_sensor_changed; - struct class *tp_class; - bool gamemode_enabled; -#endif }; @@ -266,12 +244,6 @@ int fts_esdcheck_suspend(void); int fts_esdcheck_resume(void); #endif -/* Production test */ -#if FTS_TEST_EN -int fts_test_init(struct i2c_client *client); -int fts_test_exit(struct i2c_client *client); -#endif - /* Point Report Check*/ #if FTS_POINT_REPORT_CHECK_EN int fts_point_report_check_init(struct fts_ts_data *ts_data); diff --git a/drivers/input/touchscreen/focaltech_touch/focaltech_ex_fun.c b/drivers/input/touchscreen/focaltech_touch/focaltech_ex_fun.c index 952aa7ec73eb..0991b41bfe14 100644 --- a/drivers/input/touchscreen/focaltech_touch/focaltech_ex_fun.c +++ b/drivers/input/touchscreen/focaltech_touch/focaltech_ex_fun.c @@ -145,7 +145,7 @@ static ssize_t fts_debug_write(struct file *filp, const char __user *buff, size_ break; case PROC_HW_RESET: - snprintf(tmp, sizeof(tmp), "%s", writebuf + 1); + snprintf(tmp, PAGE_SIZE, "%s", writebuf + 1); tmp[buflen - 1] = '\0'; if (strncmp(tmp, "focal_driver", 12) == 0) { FTS_INFO("APK execute HW Reset"); @@ -815,7 +815,7 @@ static ssize_t fts_fwupgradebin_store(struct device *dev, struct device_attribut return -EINVAL; } memset(fwname, 0, sizeof(fwname)); - snprintf(fwname, sizeof(fwname), "%s", buf); + snprintf(fwname, PAGE_SIZE, "%s", buf); fwname[count - 1] = '\0'; FTS_INFO("upgrade with bin file through sysfs node"); @@ -858,7 +858,7 @@ static ssize_t fts_fwforceupg_store(struct device *dev, struct device_attribute return -EINVAL; } memset(fwname, 0, sizeof(fwname)); - snprintf(fwname, sizeof(fwname), "%s", buf); + snprintf(fwname, PAGE_SIZE, "%s", buf); fwname[count - 1] = '\0'; FTS_INFO("force upgrade through sysfs node"); diff --git a/drivers/input/touchscreen/focaltech_touch/focaltech_ex_mode.c b/drivers/input/touchscreen/focaltech_touch/focaltech_ex_mode.c index dc5964662447..b987679e9a8a 100644 --- a/drivers/input/touchscreen/focaltech_touch/focaltech_ex_mode.c +++ b/drivers/input/touchscreen/focaltech_touch/focaltech_ex_mode.c @@ -230,29 +230,6 @@ static DEVICE_ATTR(fts_cover_mode, S_IRUGO | S_IWUSR, fts_touch_cover_show, fts_ #endif #if FTS_CHARGER_EN - -int fts_charger_mode_set(struct i2c_client *client, bool on) -{ - int ret = 0; - - if (on && !g_fts_mode_flag.fts_charger_mode_flag) { - FTS_INFO("[Mode]enter charger mode"); - ret = fts_enter_charger_mode(client, true); - if (ret >= 0) { - g_fts_mode_flag.fts_charger_mode_flag = true; - } - } - - if (!on && g_fts_mode_flag.fts_charger_mode_flag) { - FTS_INFO("[Mode]exit charger mode"); - ret = fts_enter_charger_mode(client, false); - if (ret >= 0) { - g_fts_mode_flag.fts_charger_mode_flag = false; - } - } - return ret; -} - static ssize_t fts_touch_charger_show(struct device *dev, struct device_attribute *attr, char *buf) { int count; diff --git a/drivers/input/touchscreen/focaltech_touch/focaltech_flash.c b/drivers/input/touchscreen/focaltech_touch/focaltech_flash.c index 3012aaf0796f..fa254c542510 100644 --- a/drivers/input/touchscreen/focaltech_touch/focaltech_flash.c +++ b/drivers/input/touchscreen/focaltech_touch/focaltech_flash.c @@ -45,23 +45,28 @@ *****************************************************************************/ /* Upgrade FW/PRAMBOOT/LCD CFG */ u8 fw_file[] = { -#include FTS_UPGRADE_FW_FILE_E10 +#include FTS_UPGRADE_FW_FILE }; u8 fw_file2[] = { -#include FTS_UPGRADE_FW_FILE_E5 +#include FTS_UPGRADE_FW2_FILE +}; + +u8 fw_file3[] = { +#include FTS_UPGRADE_FW3_FILE }; struct upgrade_fw fw_list[] = { - {FTS_PROJECT_NAME, FTS_VENDOR_ID, fw_file, sizeof(fw_file)} + {FTS_VENDOR_ID, fw_file, sizeof(fw_file)} , - {FTS_PROJECT_NAME1, FTS_VENDOR_ID2, fw_file2, sizeof(fw_file2)} + {FTS_VENDOR_ID2, fw_file2, sizeof(fw_file2)} + , + {FTS_VENDOR_ID3, fw_file3, sizeof(fw_file3)} , }; struct upgrade_func *upgrade_func_list[] = { &upgrade_func_ft8719, - &upgrade_func_ft5452, }; struct fts_upgrade *fwupgrade; @@ -1695,41 +1700,31 @@ static int fts_fwupg_get_fw_file(struct fts_ts_data *ts_data) { struct upgrade_fw *fw = &fw_list[0]; struct fts_upgrade *upg = fwupgrade; - int i = 0; - int len = 0; -#ifdef FW_UPDATE_BY_VENDOR_ID + +#if (FTS_GET_VENDOR_ID_NUM > 1) int ret = 0; + int i = 0; u16 vendor_id = 0; -#endif /* support multi vendor, must read correct vendor id */ -#ifdef FW_UPDATE_BY_VENDOR_ID ret = fts_fwupg_get_vendorid(ts_data, &vendor_id); if (ret < 0) { FTS_ERROR("get vendor id failed"); return ret; } FTS_INFO("success to read vendor id:%04x", vendor_id); -#endif - for (i = 0; i < sizeof(fw_list)/sizeof(fw_list[0]); i++) { + for (i = 0; i < FTS_GET_VENDOR_ID_NUM; i++) { fw = &fw_list[i]; - len = strlen(ts_data->pdata->project_name) > strlen(fw->project_name) ? strlen(ts_data->pdata->project_name) : strlen(fw->project_name); -#ifdef FW_UPDATE_BY_VENDOR_ID - if (ts_data->pdata->project_name && !strncmp(ts_data->pdata->project_name, fw->project_name, len) && vendor_id == fw->vendor_id) { - FTS_INFO("project id and vendor id match, get fw file successfully"); - break; - } -#else - if (ts_data->pdata->project_name && !strncmp(ts_data->pdata->project_name, fw->project_name, strlen(ts_data->pdata->project_name))) { + if (vendor_id == fw->vendor_id) { FTS_INFO("vendor id match, get fw file successfully"); break; } -#endif } - if (i >= sizeof(fw_list)/sizeof(fw_list[0])) { - FTS_ERROR("no vendor id or project id match, don't get file"); + if (i >= FTS_GET_VENDOR_ID_NUM) { + FTS_ERROR("no vendor id match, don't get file"); return -ENODATA; } +#endif if (upg) { upg->fw = fw->fw_file; @@ -1796,11 +1791,12 @@ static void fts_fwupg_work(struct work_struct *work) static int fts_get_lockdown_info(struct fts_ts_data *ts_data) { - int i, ret = -EINVAL; + int i, ret; char buf[128]; memset(ts_data->lockdown_info, 0x00, FTS_LOCKDOWN_INFO_SIZE); - ret = fts_flash_read(ts_data->client, ts_data->pdata->lockdown_info_addr, ts_data->lockdown_info, FTS_LOCKDOWN_INFO_SIZE); + + ret = fts_flash_read(ts_data->client, LOCKDOWN_INFO_ADDR, ts_data->lockdown_info, FTS_LOCKDOWN_INFO_SIZE); if (ret < 0) { FTS_ERROR("fail to get lockdown info"); return ret; diff --git a/drivers/input/touchscreen/focaltech_touch/focaltech_flash.h b/drivers/input/touchscreen/focaltech_touch/focaltech_flash.h index ca92d71da1bf..d4d983c02cbe 100644 --- a/drivers/input/touchscreen/focaltech_touch/focaltech_flash.h +++ b/drivers/input/touchscreen/focaltech_touch/focaltech_flash.h @@ -140,7 +140,6 @@ struct fts_upgrade { }; struct upgrade_fw { - u8 *project_name; u16 vendor_id; u8 *fw_file; u32 fw_len; @@ -151,7 +150,6 @@ struct upgrade_fw { *****************************************************************************/ extern struct fts_upgrade *fwupgrade; extern struct upgrade_func upgrade_func_ft8719; -extern struct upgrade_func upgrade_func_ft5452; /***************************************************************************** * Static function prototypes diff --git a/drivers/input/touchscreen/focaltech_touch/focaltech_flash/Makefile b/drivers/input/touchscreen/focaltech_touch/focaltech_flash/Makefile index 462b96dcd299..9a27096ad991 100644 --- a/drivers/input/touchscreen/focaltech_touch/focaltech_flash/Makefile +++ b/drivers/input/touchscreen/focaltech_touch/focaltech_flash/Makefile @@ -5,5 +5,14 @@ # Each configuration option enables a list of files. +#obj-$(CONFIG_TOUCHSCREEN_FTS) += focaltech_upgrade_ft5x46.o +#obj-$(CONFIG_TOUCHSCREEN_FTS) += focaltech_upgrade_ft5822.o +#obj-$(CONFIG_TOUCHSCREEN_FTS) += focaltech_upgrade_ft6336gu.o +#obj-$(CONFIG_TOUCHSCREEN_FTS) += focaltech_upgrade_ft8006.o +#obj-$(CONFIG_TOUCHSCREEN_FTS) += focaltech_upgrade_ft8606.o +#obj-$(CONFIG_TOUCHSCREEN_FTS) += focaltech_upgrade_ft8607.o +#obj-$(CONFIG_TOUCHSCREEN_FTS) += focaltech_upgrade_ft8716.o obj-$(CONFIG_TOUCHSCREEN_FTS) += focaltech_upgrade_ft8719.o -obj-$(CONFIG_TOUCHSCREEN_FTS) += focaltech_upgrade_ft5452.o +#obj-$(CONFIG_TOUCHSCREEN_FTS) += focaltech_upgrade_ft8736.o +#obj-$(CONFIG_TOUCHSCREEN_FTS) += focaltech_upgrade_idc.o +#obj-$(CONFIG_TOUCHSCREEN_FTS) += focaltech_upgrade_test.o diff --git a/drivers/input/touchscreen/focaltech_touch/focaltech_flash/focaltech_upgrade_ft5452.c b/drivers/input/touchscreen/focaltech_touch/focaltech_flash/focaltech_upgrade_ft5452.c deleted file mode 100644 index 8cf6679d4c49..000000000000 --- a/drivers/input/touchscreen/focaltech_touch/focaltech_flash/focaltech_upgrade_ft5452.c +++ /dev/null @@ -1,187 +0,0 @@ -/* - * - * FocalTech fts TouchScreen driver. - * - * Copyright (c) 2010-2018, Focaltech Ltd. All rights reserved. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -/***************************************************************************** -* -* File Name: focaltech_upgrade_ft5452.c -* -* Author: Focaltech Driver Team -* -* Created: 2016-08-15 -* -* Abstract: -* -* Reference: -* -*****************************************************************************/ -/***************************************************************************** -* 1.Included header files -*****************************************************************************/ -#include "../focaltech_core.h" -#include "../focaltech_flash.h" - -/************************************************************************ -* Name: fts_ft5452_upgrade -* Brief: -* Input: -* Output: -* Return: return 0 if success, otherwise return error code -***********************************************************************/ -static int fts_ft5452_upgrade(struct i2c_client *client, u8 *buf, u32 len) -{ - int ret = 0; - u32 start_addr = 0; - u8 cmd[4] = { 0 }; - int ecc_in_host = 0; - int ecc_in_tp = 0; - - int i = 0; - u8 wbuf[7] = { 0 }; - u8 reg_val[4] = {0}; - - if (NULL == buf) { - FTS_ERROR("fw buf is null"); - return -EINVAL; - } - - if ((len < FTS_MIN_LEN) || (len > (128 * 1024))) { - FTS_ERROR("fw buffer len(%x) fail", len); - return -EINVAL; - } - - /* enter into upgrade environment */ - ret = fts_fwupg_enter_into_boot(client); - if (ret < 0) { - FTS_ERROR("enter into pramboot/bootloader fail,ret=%d", ret); - goto fw_reset; - } - - cmd[0] = FTS_CMD_FLASH_MODE; - cmd[1] = FLASH_MODE_UPGRADE_VALUE; - ret = fts_i2c_write(client, cmd, 2); - if (ret < 0) { - FTS_ERROR("upgrade mode(09) cmd write fail"); - goto fw_reset; - } - - cmd[0] = FTS_CMD_DATA_LEN; - cmd[1] = BYTE_OFF_16(len); - cmd[2] = BYTE_OFF_8(len); - cmd[3] = BYTE_OFF_0(len); - ret = fts_i2c_write(client, cmd, FTS_CMD_DATA_LEN_LEN); - if (ret < 0) { - FTS_ERROR("data len cmd write fail"); - goto fw_reset; - } - - ret = fts_fwupg_erase(client, FTS_REASE_APP_DELAY); - if (ret < 0) { - FTS_ERROR("erase cmd write fail"); - goto fw_reset; - } - - /* write app */ - start_addr = upgrade_func_ft5452.appoff; - ecc_in_host = fts_flash_write_buf(client, start_addr, buf, len, 1); - if (ecc_in_host < 0) { - FTS_ERROR("lcd initial code write fail"); - goto fw_reset; - } - - FTS_INFO("**********read out checksum**********"); - - /* check sum init */ - wbuf[0] = FTS_CMD_ECC_INIT; - ret = fts_i2c_write(client, wbuf, 1); - if (ret < 0) { - FTS_ERROR("ecc init cmd write fail"); - return ret; - } - - /* send commond to start checksum */ - wbuf[0] = FTS_CMD_ECC_CAL; - wbuf[1] = BYTE_OFF_16(start_addr); - wbuf[2] = BYTE_OFF_8(start_addr); - wbuf[3] = BYTE_OFF_0(start_addr); - - wbuf[4] = BYTE_OFF_16(len); - wbuf[5] = BYTE_OFF_8(len); - wbuf[6] = BYTE_OFF_0(len); - - FTS_DEBUG("ecc calc startaddr:0x%04x, len:%d", start_addr, len); - ret = fts_i2c_write(client, wbuf, 7); - if (ret < 0) { - FTS_ERROR("ecc calc cmd write fail"); - return ret; - } - - msleep(len / 256); - - /* read status if check sum is finished */ - for (i = 0; i < FTS_RETRIES_ECC_CAL; i++) { - wbuf[0] = FTS_CMD_FLASH_STATUS; - reg_val[0] = reg_val[1] = 0x00; - fts_i2c_read(client, wbuf, 1, reg_val, 2); - FTS_DEBUG("[UPGRADE]: reg_val[0]=%02x reg_val[0]=%02x!!", reg_val[0], reg_val[1]); - if ((0xF0 == reg_val[0]) && (0x55 == reg_val[1])) { - break; - } - msleep(FTS_RETRIES_DELAY_ECC_CAL); - } - - /* read out check sum */ - wbuf[0] = FTS_CMD_ECC_READ; - ret = fts_i2c_read(client, wbuf, 1, reg_val, 1); - if (ret < 0) { - FTS_ERROR("ecc read cmd write fail"); - return ret; - } - ecc_in_tp = reg_val[0]; - - FTS_INFO("ecc in tp:%x, host:%x", ecc_in_tp, ecc_in_host); - if (ecc_in_tp != ecc_in_host) { - FTS_ERROR("ecc check fail"); - goto fw_reset; - } - - FTS_INFO("upgrade success, reset to normal boot"); - ret = fts_fwupg_reset_in_boot(client); - if (ret < 0) { - FTS_ERROR("reset to normal boot fail"); - } - - msleep(200); - return 0; - -fw_reset: - FTS_INFO("upgrade fail, reset to normal boot"); - ret = fts_fwupg_reset_in_boot(client); - if (ret < 0) { - FTS_ERROR("reset to normal boot fail"); - } - return -EIO; -} - -struct upgrade_func upgrade_func_ft5452 = { - .ctype = {0x81}, - .fwveroff = 0x010E, - .fwcfgoff = 0x1FFB0, - .appoff = 0x0000, - .pramboot_supported = false, - .hid_supported = true, - .upgrade = fts_ft5452_upgrade, -}; diff --git a/drivers/input/touchscreen/focaltech_touch/focaltech_flash/focaltech_upgrade_ft8719.c b/drivers/input/touchscreen/focaltech_touch/focaltech_flash/focaltech_upgrade_ft8719.c index 8cb1bdaf77fb..27182d415c69 100644 --- a/drivers/input/touchscreen/focaltech_touch/focaltech_flash/focaltech_upgrade_ft8719.c +++ b/drivers/input/touchscreen/focaltech_touch/focaltech_flash/focaltech_upgrade_ft8719.c @@ -3,6 +3,7 @@ * FocalTech fts TouchScreen driver. * * Copyright (c) 2010-2017, Focaltech Ltd. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and diff --git a/drivers/input/touchscreen/focaltech_touch/include/firmware/fw_ft3518_e5.i b/drivers/input/touchscreen/focaltech_touch/include/firmware/fw_ft3518_e5.i deleted file mode 100644 index f4f53981f4d3..000000000000 --- a/drivers/input/touchscreen/focaltech_touch/include/firmware/fw_ft3518_e5.i +++ /dev/null @@ -1,3323 +0,0 @@ -0x2, 0x1e,0x63,0x2, 0xc6,0x1d,0xe4,0x2, 0x19,0xdd,0x22,0x2, 0x0, 0x72,0xb4,0x2, -0x4, 0xa9,0xb7,0xea,0x22,0x24,0xff,0xa9,0x97,0xea,0x22,0x2, 0xc5,0xf1,0x12,0x18, -0x6b,0x2, 0x1c,0x6, 0x22,0xeb,0xaa,0x8, 0x2, 0x27,0xf8,0x2, 0x6c,0xda,0x7f,0x60, -0xa9,0xc2,0xea,0x74,0x1, 0x12,0x1c,0xe3,0x7f,0x6, 0x12,0xd, 0x0, 0x7f,0x6, 0x2, -0x13,0xbe,0x22,0x2, 0x6c,0xf6,0xc2,0xf, 0x22,0x22,0x22,0x2, 0x0, 0xff,0x1, 0x2, -0x4, 0x8, 0x10,0x20,0x40,0x80,0xd2,0x4, 0x2, 0x3d,0x2c,0x2, 0x19,0x28,0x0, 0x0, -0x0, 0x0, 0x0, 0x0, 0x7e,0x34,0xd, 0xac,0x2, 0x62,0xe7,0x2, 0xf, 0xfe,0xa2,0x12, -0x22,0x22,0x32,0x2, 0x1a,0xe1,0xca,0xf8,0x7c,0xfb,0x7e,0x34,0x0, 0x1, 0x7e,0xf, -0x36,0x20,0x79,0x30,0x0, 0x10,0xc2,0x1b,0xe4,0x7a,0xb3,0x36,0x17,0x5e,0xf0,0x3, -0x74,0x3, 0x12,0x1c,0x86,0x74,0x1, 0x12,0x19,0xdd,0xa, 0x2f,0x5e,0x24,0x0, 0x3, -0x3e,0x24,0x7e,0xf, 0x3, 0xd9,0xb, 0xa, 0x30,0x5e,0x70,0xf9,0x4d,0x32,0x1b,0xa, -0x30,0x7e,0xf, 0x3, 0xd9,0xb, 0xa, 0x30,0x4e,0x70,0x1, 0x1b,0xa, 0x30,0x7e,0xf, -0x3, 0xd9,0xb, 0xa, 0x30,0x5e,0x34,0x0, 0x1, 0x78,0xf3,0x2e,0x14,0x0, 0x9e,0xb, -0xa, 0x30,0x4e,0x70,0x20,0x1b,0xa, 0x30,0x74,0x1, 0x12,0x1c,0x86,0x7e,0xf, 0x36, -0x20,0xb, 0xa, 0x30,0x4e,0x70,0xc, 0x1b,0xa, 0x30,0xa9,0xd3,0xcd,0x7e,0xf, 0x36, -0x20,0xb, 0x15,0xb, 0xa, 0x30,0x4e,0x70,0x1, 0x1b,0xa, 0x30,0xda,0xf8,0x22,0x32, -0xcf,0xb0,0x30,0x4f,0xb5,0x10,0x4a,0xef,0x12,0x5a,0xed,0xa5,0xe4,0x1b,0x5, 0xfa, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0x52,0x49,0xf2,0x29,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xbe,0x8, 0x0, 0x0, 0x78,0x2, 0x61,0x94,0xbe,0xb0,0x3, 0x40,0x2, 0x61,0x94,0x60, -0x2, 0x41,0x2, 0xb, 0xa, 0x30,0x7e,0x2f,0x3, 0xe1,0x79,0x32,0x0, 0x46,0x69,0x30, -0x0, 0x2, 0x7e,0x2f,0x3, 0xe1,0x79,0x32,0x0, 0x40,0x29,0x70,0x0, 0x4, 0xa, 0x27, -0x5e,0x24,0x0, 0x3, 0x7e,0x2f,0x3, 0xe1,0x2e,0x54,0x0, 0x4c,0xb, 0x2a,0x30,0x5e, -0x70,0xfc,0x4d,0x32,0x1b,0x2a,0x30,0x29,0x70,0x0, 0x5, 0xa, 0x27,0x5e,0x24,0x0, -0x7f,0x7c,0x45,0x6c,0x55,0x7e,0x2f,0x3, 0xe1,0x2e,0x54,0x0, 0x12,0xb, 0x2a,0x30, -0x5e,0x60,0x80,0x4d,0x32,0x1b,0x2a,0x30,0x29,0x70,0x0, 0xe, 0xa, 0x27,0x7c,0x45, -0x6c,0x55,0x7e,0x2f,0x3, 0xe1,0x2e,0x54,0x0, 0x16,0xb, 0x2a,0x30,0x6c,0x66,0x4d, -0x32,0x1b,0x2a,0x30,0x29,0x70,0x0, 0xf, 0xa, 0x27,0x7c,0x45,0x6c,0x55,0x7e,0x2f, -0x3, 0xe1,0x2e,0x54,0x0, 0x22,0xb, 0x2a,0x30,0x6c,0x66,0x4d,0x32,0x1b,0x2a,0x30, -0x69,0x30,0x0, 0x6, 0x7e,0x2f,0x3, 0xe1,0x79,0x32,0x0, 0x50,0x69,0x30,0x0, 0x8, -0x7e,0x2f,0x3, 0xe1,0x79,0x32,0x0, 0x56,0x69,0x30,0x0, 0xa, 0x7e,0x2f,0x3, 0xe1, -0x79,0x32,0x0, 0x5c,0x69,0x30,0x0, 0xc, 0x7e,0x2f,0x3, 0xe1,0x79,0x32,0x0, 0x62, -0x61,0x5c,0xb4,0x1, 0x2, 0x80,0x2, 0x41,0xc8,0xb, 0xa, 0x30,0x7e,0x2f,0x3, 0xe1, -0x79,0x32,0x0, 0x48,0x69,0x30,0x0, 0x2, 0x7e,0x2f,0x3, 0xe1,0x79,0x32,0x0, 0x42, -0x29,0x70,0x0, 0x4, 0xa, 0x27,0x5e,0x24,0x0, 0x3, 0x3e,0x24,0x3e,0x24,0x7e,0x2f, -0x3, 0xe1,0x2e,0x54,0x0, 0x4c,0xb, 0x2a,0x30,0x5e,0x70,0xf3,0x4d,0x32,0x1b,0x2a, -0x30,0x29,0x70,0x0, 0x5, 0xa, 0x27,0x5e,0x24,0x0, 0x7f,0x7e,0x2f,0x3, 0xe1,0x2e, -0x54,0x0, 0x4e,0xb, 0x2a,0x30,0x5e,0x70,0x80,0x4d,0x32,0x1b,0x2a,0x30,0x29,0x70, -0x0, 0xe, 0xa, 0x27,0x7c,0x45,0x6c,0x55,0x7e,0x2f,0x3, 0xe1,0x2e,0x54,0x0, 0x16, -0xb, 0x2a,0x30,0x6c,0x66,0x4d,0x32,0x1b,0x2a,0x30,0x29,0x70,0x0, 0xf, 0xa, 0x27, -0x7c,0x45,0x6c,0x55,0x7e,0x2f,0x3, 0xe1,0x2e,0x54,0x0, 0x22,0xb, 0x2a,0x30,0x6c, -0x66,0x4d,0x32,0x1b,0x2a,0x30,0x69,0x30,0x0, 0x6, 0x7e,0x2f,0x3, 0xe1,0x79,0x32, -0x0, 0x52,0x69,0x30,0x0, 0x8, 0x7e,0x2f,0x3, 0xe1,0x79,0x32,0x0, 0x58,0x69,0x30, -0x0, 0xa, 0x7e,0x2f,0x3, 0xe1,0x79,0x32,0x0, 0x5e,0x69,0x30,0x0, 0xc, 0x7e,0x2f, -0x3, 0xe1,0x79,0x32,0x0, 0x64,0x61,0x5c,0xb4,0x2, 0x2, 0x80,0x2, 0x61,0x5c,0xb, -0xa, 0x30,0x7e,0x2f,0x3, 0xe1,0x79,0x32,0x0, 0x4a,0x69,0x30,0x0, 0x2, 0x7e,0x2f, -0x3, 0xe1,0x79,0x32,0x0, 0x44,0x29,0x70,0x0, 0x4, 0xa, 0x27,0x5e,0x24,0x0, 0x3, -0x3e,0x24,0x3e,0x24,0x3e,0x24,0x3e,0x24,0x7e,0x2f,0x3, 0xe1,0x2e,0x54,0x0, 0x4c, -0xb, 0x2a,0x30,0x5e,0x70,0xcf,0x4d,0x32,0x1b,0x2a,0x30,0x29,0x70,0x0, 0x5, 0xa, -0x27,0x5e,0x24,0x0, 0x7f,0x7c,0x45,0x6c,0x55,0x7e,0x2f,0x3, 0xe1,0x2e,0x54,0x0, -0x4e,0xb, 0x2a,0x30,0x5e,0x60,0x80,0x4d,0x32,0x1b,0x2a,0x30,0x69,0x30,0x0, 0x6, -0x7e,0x2f,0x3, 0xe1,0x79,0x32,0x0, 0x54,0x69,0x30,0x0, 0x8, 0x7e,0x2f,0x3, 0xe1, -0x79,0x32,0x0, 0x5a,0x69,0x30,0x0, 0xa, 0x7e,0x2f,0x3, 0xe1,0x79,0x32,0x0, 0x60, -0x69,0x30,0x0, 0xc, 0x7e,0x2f,0x3, 0xe1,0x79,0x32,0x0, 0x66,0x29,0x70,0x0, 0xe, -0xa, 0x27,0x7c,0x45,0x6c,0x55,0x7e,0x2f,0x3, 0xe1,0x2e,0x54,0x0, 0x16,0xb, 0x2a, -0x30,0x6c,0x66,0x4d,0x32,0x1b,0x2a,0x30,0x29,0x70,0x0, 0xf, 0xa, 0x27,0x7c,0x45, -0x6c,0x55,0x7e,0xf, 0x3, 0xe1,0x2e,0x14,0x0, 0x22,0xb, 0xa, 0x30,0x6c,0x66,0x4d, -0x32,0x1b,0xa, 0x30,0x22,0xca,0x79,0x7f,0x70,0x74,0x1, 0x12,0x1d,0x14,0x29,0xe7, -0x1, 0xf, 0x29,0x77,0x0, 0xb5,0x29,0x27,0x0, 0xb6,0x29,0x67,0x1, 0x10,0x7a,0x63, -0x3, 0xea,0x29,0x67,0x1, 0x12,0x7a,0x63,0x3, 0xf8,0x29,0x67,0x1, 0x11,0x7a,0x63, -0x3, 0xeb,0xbe,0x70,0x3, 0x38,0x2, 0x61,0xcb,0x6c,0x77,0xbe,0x20,0x40,0x38,0x2, -0x61,0xd5,0x7e,0x20,0x40,0xa, 0xe, 0x7e,0x6f,0x3, 0xe1,0x79,0x6, 0x0, 0xa, 0xa, -0x7, 0x9, 0xf0,0x3, 0xe5,0xa, 0x42,0x5e,0x44,0x0, 0x7f,0x7e,0x1f,0x3, 0xe1,0x2e, -0x34,0x0, 0x12,0xb, 0x1a,0x0, 0x5e,0x10,0x80,0x4d,0x4, 0x1b,0x1a,0x0, 0x7c,0x7e, -0xac,0x7f,0xa, 0x22,0x12,0x1d,0x4a,0x7c,0xb7,0xa, 0xb, 0x7e,0x1f,0x3, 0xe1,0x79, -0x1, 0x0, 0x14,0xa, 0x2f,0xa, 0x32,0x12,0x1d,0x4a,0x7d,0x43,0x29,0xb7,0x0, 0xb7, -0x70,0x2, 0x81,0x7c,0x7c,0x7e,0xac,0x7f,0x29,0x37,0x1, 0x10,0xa, 0x23,0xad,0x32, -0xa, 0x22,0x8d,0x32,0x7d,0x3, 0x7c,0x7e,0xac,0x7f,0xa, 0x22,0x12,0x1d,0x4a,0x7c, -0xa7,0x7c,0x21,0x2c,0xa2,0xbe,0xa0,0xd, 0x40,0x2, 0x81,0x4f,0x7e,0xa0,0xd, 0x7e, -0x30,0xc, 0xa, 0x2a,0x9e,0x24,0x0, 0xd, 0x2e,0x24,0x0, 0xc, 0x6c,0x44,0x7e,0x6f, -0x3, 0xe1,0x2e,0xd4,0x0, 0x22,0xb, 0x6a,0x30,0x6c,0x77,0x4d,0x32,0x1b,0x6a,0x30, -0xa, 0x2a,0x9e,0x24,0x0, 0xd, 0x2e,0x24,0x0, 0x18,0x81,0xb2,0x29,0x77,0x1, 0x12, -0xa, 0x57,0x2e,0x54,0x0, 0xd, 0x7c,0xab,0x6c,0x33,0xa, 0x2a,0x9e,0x24,0x0, 0xd, -0x2e,0x24,0x0, 0xc, 0x6c,0x44,0x7e,0x6f,0x3, 0xe1,0x2e,0xd4,0x0, 0x22,0xb, 0x6a, -0x30,0x6c,0x77,0x4d,0x32,0x1b,0x6a,0x30,0xa, 0x2a,0x9e,0x24,0x0, 0xd, 0x2e,0x24, -0x0, 0xc, 0x6c,0x44,0x7e,0x6f,0x3, 0xe1,0x2e,0xd4,0x0, 0x16,0xb, 0x6a,0x30,0x6c, -0x77,0x4d,0x32,0x1b,0x6a,0x30,0xa, 0x3a,0xad,0x34,0x7d,0x23,0xb, 0x24,0xbe,0x24, -0x2, 0x0, 0x50,0x2, 0x81,0xda,0x7e,0x24,0x1, 0xff,0x1e,0x24,0x6c,0x44,0x7e,0x6f, -0x3, 0xe1,0x2e,0xd4,0x0, 0xc, 0xb, 0x6a,0x30,0x6c,0x77,0x4d,0x32,0x1b,0x6a,0x30, -0x29,0x27,0x1, 0x11,0x7e,0x10,0x2, 0xac,0x12,0xa, 0x33,0xad,0x34,0x2d,0x30,0x29, -0x27,0x1, 0x14,0xa, 0x22,0xb, 0x24,0x3e,0x24,0x2d,0x23,0x69,0x37,0x1, 0x15,0xbe, -0x34,0x0, 0x0, 0x38,0x2, 0xa1,0x19,0xb, 0x25,0xb, 0x24,0xbe,0x24,0x2, 0x0, 0x50, -0x2, 0xa1,0x27,0x7e,0x24,0x1, 0xff,0x1e,0x24,0x7c,0x45,0x6c,0x55,0x7e,0x7f,0x3, -0xe1,0x2e,0xf4,0x0, 0xc, 0xb, 0x7a,0x30,0x6c,0x66,0x4d,0x32,0x1b,0x7a,0x30,0xda, -0x79,0x22,0xca,0x3b,0x7c,0x57,0x7c,0x4b,0xbe,0x40,0x3, 0x40,0x2, 0x6c,0x44,0x69, -0x30,0x0, 0x4, 0x5e,0x60,0xf, 0x6c,0xaa,0x7e,0x90,0x2, 0xac,0x9a,0x69,0xd0,0x0, -0xe, 0x69,0xc0,0x0, 0xc, 0x2d,0xd4,0x29,0xb6,0x0, 0x1, 0xa, 0xfb,0x7d,0x4f,0x7c, -0x89,0x6c,0x99,0x7d,0xf4,0x7e,0x6b,0xb0,0xa, 0x4b,0x4d,0x4f,0x7e,0xd0,0x34,0xac, -0xd5,0x7e,0xf0,0x2, 0xac,0xfa,0x7d,0xf7,0x2d,0xf6,0xa, 0xc4,0x7e,0xd4,0x1, 0x38, -0xad,0xdc,0x2d,0xdf,0x7e,0x7f,0x36,0x1c,0x2d,0xfd,0x79,0x47,0x0, 0x10,0xb, 0xa0, -0xbe,0xa0,0x6, 0x78,0xb3,0x6c,0xaa,0x7e,0x90,0x2, 0xac,0x9a,0x69,0xd0,0x0, 0xa, -0x69,0xc0,0x0, 0x8, 0x2d,0xd4,0x29,0xb6,0x0, 0x1, 0xa, 0xfb,0x7d,0x4f,0x7c,0x89, -0x6c,0x99,0x7d,0xf4,0x7e,0x6b,0xb0,0xa, 0x4b,0x4d,0x4f,0x7e,0xd0,0x34,0xac,0xd5, -0x7e,0xf0,0x2, 0xac,0xfa,0x7d,0xf7,0x2d,0xf6,0xa, 0xc4,0x7e,0xd4,0x1, 0x38,0xad, -0xdc,0x2d,0xdf,0x7e,0x7f,0x36,0x1c,0x2d,0xfd,0x79,0x47,0x0, 0x1c,0xb, 0xa0,0xbe, -0xa0,0xc, 0x78,0xb3,0x6c,0xaa,0x7e,0x90,0x2, 0xac,0x9a,0x69,0xf0,0x0, 0x2, 0xb, -0xa, 0xe0,0x2d,0xf4,0xb, 0x7a,0x40,0x7e,0xd0,0x34,0xac,0xd5,0x7e,0xf0,0x2, 0xac, -0xfa,0x7d,0xf7,0x2d,0xf6,0xa, 0xc4,0x7e,0xd4,0x1, 0x38,0xad,0xdc,0x2d,0xdf,0x7e, -0x7f,0x36,0x1c,0x2d,0xfd,0x1b,0x7a,0x40,0xb, 0xa0,0xbe,0xa0,0x5, 0x40,0xc7,0x6d, -0x44,0xa, 0xe4,0x7e,0xf4,0x1, 0x38,0xad,0xfe,0x74,0x34,0xac,0xb5,0x2d,0x5f,0x7e, -0x7f,0x36,0x1c,0x2d,0xf5,0x79,0x47,0x0, 0xa, 0xa, 0xe4,0x7e,0xf4,0x1, 0x38,0xad, -0xfe,0x74,0x34,0xac,0xb5,0x2d,0xf5,0x7e,0x2f,0x36,0x1c,0x2d,0x5f,0x79,0x32,0x0, -0xc, 0x69,0x30,0x0, 0x6, 0xa, 0x4, 0x7e,0x14,0x1, 0x38,0xad,0x10,0x74,0x34,0xac, -0x5b,0x2d,0x21,0x7e,0xf, 0x36,0x1c,0x2d,0x12,0x79,0x30,0x0, 0xe, 0xda,0x3b,0x22, -0xca,0x79,0x7e,0x6f,0x3, 0xe1,0x69,0x26,0x0, 0xa, 0x69,0x6, 0x0, 0x2, 0x1e,0x4, -0x1e,0x4, 0x1e,0x4, 0x1e,0x4, 0x1e,0x4, 0x1e,0x4, 0x1e,0x4, 0x5e,0x4, 0x0, 0x3, -0x9, 0x0, 0x3, 0xe5,0x69,0x76,0x0, 0x12,0x5e,0x74,0x0, 0x7f,0x69,0x36,0x0, 0x14, -0x69,0xa6,0x0, 0xc, 0x7d,0xba,0x5e,0xb4,0x0, 0xff,0x3e,0xb4,0x7d,0x4a,0xa, 0x48, -0x3e,0x44,0x69,0x56,0x0, 0x16,0x7c,0x1b,0x69,0x56,0x0, 0x22,0x7c,0xab,0xac,0x50, -0xac,0x7f,0xbd,0x32,0x78,0x2, 0xc1,0xde,0x7e,0x34,0x0, 0x81,0xe1,0xa5,0xa, 0x20, -0xa, 0x3f,0x12,0x1d,0x4a,0x4d,0x22,0x78,0x2, 0xc1,0xf1,0x7e,0x34,0x0, 0x82,0xe1, -0xa5,0xa, 0xf0,0xad,0xfb,0xa, 0x2f,0x7d,0x3f,0x8d,0x32,0xbe,0x70,0xd, 0x40,0x2, -0xe1,0x8, 0x7e,0x34,0x0, 0x83,0xe1,0xa5,0x7c,0x57,0xac,0x5f,0xbd,0x2f,0x78,0x2, -0xe1,0x18,0x7e,0x34,0x0, 0x84,0xe1,0xa5,0x7e,0x50,0xc, 0xac,0x5f,0xa, 0xe0,0x7d, -0xf2,0x8d,0xfe,0x7d,0x2f,0x69,0xf6,0x0, 0x2a,0x7d,0xef,0x1e,0xe4,0x1e,0xe4,0x1e, -0xe4,0x1e,0xe4,0x1e,0xe4,0x1e,0xe4,0x5e,0xe4,0x3, 0xff,0xbe,0xe4,0x0, 0x0, 0x38, -0x2, 0xe1,0x49,0x7e,0x14,0x0, 0x2, 0xe1,0x4b,0x6d,0x11,0x5e,0xf4,0x0, 0x3f,0xb, -0xf4,0x3e,0xf4,0x2d,0x21,0x2d,0x2f,0xbd,0x24,0x78,0x2, 0xe1,0x63,0x7e,0x34,0x0, -0x85,0xe1,0xa5,0x7e,0xb3,0x3, 0xd7,0x70,0x2, 0xe1,0x7f,0xa, 0x47,0x2e,0x44,0x0, -0xb, 0xa, 0x21,0xbd,0x24,0x78,0x2, 0xe1,0x91,0x7e,0x34,0x0, 0x86,0xe1,0xa5,0xa, -0x27,0x1b,0x24,0xa, 0x1, 0xbd,0x2, 0x78,0x2, 0xe1,0x91,0x7e,0x34,0x0, 0x87,0xe1, -0xa5,0xa, 0x37,0x1b,0x34,0xa, 0xa, 0xbd,0x3, 0x78,0x2, 0xe1,0xa3,0x7e,0x34,0x0, -0x88,0xe1,0xa5,0x6d,0x33,0xda,0x79,0x22,0x7f,0x10,0xa9,0xd6,0xcb,0x69,0x11,0x0, -0x2, 0x7e,0x2f,0x36,0x51,0x79,0x12,0x0, 0x4, 0x69,0x11,0x0, 0x4, 0x7e,0x2f,0x36, -0x51,0x79,0x12,0x0, 0x6, 0x69,0x11,0x0, 0x6, 0x7e,0x2f,0x36,0x51,0x79,0x12,0x0, -0x8, 0x7e,0x1b,0x30,0xa, 0x3, 0x7e,0x14,0x1, 0x0, 0xad,0x10,0x29,0x71,0x0, 0x1, -0xa, 0x37,0x2d,0x31,0x7e,0xf, 0x36,0x51,0x79,0x30,0x0, 0xc, 0x6d,0x11,0x7e,0x1f, -0x36,0x51,0x1b,0x1a,0x10,0x7e,0x34,0x0, 0x60,0x12,0x19,0x84,0xa9,0xc6,0xcb,0x22, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff, -0x29,0x70,0x0, 0xa6,0x29,0x90,0x0, 0xa8,0x29,0x60,0x0, 0xa7,0x29,0x80,0x0, 0x9d, -0xbe,0x80,0x4, 0x28,0x2, 0xa1,0x1b,0x6c,0xaa,0xa1,0x42,0xbe,0x80,0x8, 0x28,0x2, -0xa1,0x27,0x7e,0xa0,0x1, 0xa1,0x42,0xbe,0x80,0x10,0x28,0x2, 0xa1,0x33,0x7e,0xa0, -0x2, 0xa1,0x42,0xbe,0x80,0x20,0x28,0x2, 0xa1,0x3f,0x7e,0xa0,0x3, 0xa1,0x42,0x7e, -0xa0,0x4, 0xbe,0x90,0x3, 0x38,0x2, 0xa1,0x4c,0x7e,0x90,0x3, 0xbe,0x80,0x3f,0x38, -0x2, 0xa1,0x56,0x7e,0x80,0x3f,0xbe,0x60,0x1, 0x38,0x2, 0xa1,0x60,0x7e,0x60,0x1, -0xbe,0x70,0x2, 0x38,0x2, 0xa1,0x69,0x6c,0x77,0xa, 0x28,0x3e,0x24,0x3e,0x24,0x3e, -0x24,0x3e,0x24,0x3e,0x24,0x7c,0x89,0x6c,0x99,0x3e,0x44,0x3e,0x44,0x3e,0x44,0x2d, -0x42,0xa, 0x26,0x3e,0x24,0x3e,0x24,0x3e,0x24,0x3e,0x24,0x2d,0x24,0xa, 0x37,0x3e, -0x34,0x3e,0x34,0x2d,0x32,0x7e,0x7f,0x36,0x20,0x79,0x37,0x0, 0x2, 0x29,0xb0,0x0, -0x9c,0x7c,0x4b,0x6c,0x55,0x29,0xb0,0x0, 0x9b,0xa, 0x3b,0x2d,0x32,0x7e,0x7f,0x3, -0xd9,0x79,0x37,0x0, 0x9a,0x69,0x30,0x0, 0xb2,0x7e,0x7f,0x36,0x20,0x79,0x37,0x0, -0xc, 0x69,0x20,0x0, 0xb0,0x7d,0x32,0x7e,0x7f,0x36,0x20,0x79,0x37,0x0, 0xe, 0x69, -0x30,0x0, 0xae,0x5e,0x34,0xe0,0xf, 0x29,0xb0,0x0, 0x9c,0xa, 0x2b,0x1b,0x24,0x3e, -0x24,0x3e,0x24,0x3e,0x24,0x3e,0x24,0x2d,0x32,0x7e,0x7f,0x3, 0xd9,0x79,0x37,0x0, -0x9c,0xa, 0x2a,0x3e,0x24,0x3e,0x24,0x3e,0x24,0x3e,0x24,0x29,0xb0,0x0, 0xa9,0xa, -0x3b,0x2d,0x32,0x7e,0x7f,0x36,0x20,0x79,0x37,0x0, 0x6, 0x69,0x30,0x0, 0xac,0x7e, -0x7f,0x36,0x20,0x79,0x37,0x0, 0x8, 0x69,0x30,0x0, 0xaa,0x7e,0xf, 0x36,0x20,0x79, -0x30,0x0, 0xa, 0x22,0xca,0x79,0x7c,0x57,0x7c,0x7b,0x6c,0x66,0x80,0x17,0x7e,0xf0, -0x2, 0xac,0xf6,0x7e,0x7f,0x36,0x18,0x2d,0xf7,0xb, 0x7a,0x40,0x7f,0x70,0x2d,0xf7, -0x1b,0x7a,0x40,0xb, 0x60,0xbc,0x56,0x38,0xe5,0x6c,0x66,0x80,0x20,0x7e,0x90,0x2, -0xac,0x96,0x7e,0x7f,0x36,0x18,0x2d,0xf4,0x69,0x47,0x0, 0x48,0xa, 0xe5,0xa, 0xf6, -0x2d,0xfe,0x3e,0xf4,0x2d,0xf1,0x7d,0xe0,0x1b,0x7a,0x40,0xb, 0x60,0xbc,0x76,0x38, -0xdc,0x7e,0x7f,0x36,0x20,0x69,0x47,0x0, 0x4, 0x5e,0x44,0x0, 0x1, 0x78,0x2, 0xe1, -0x3f,0xa, 0x45,0xa, 0x57,0x2d,0x54,0x7c,0xab,0x6c,0x66,0x80,0x20,0x7e,0x90,0x2, -0xac,0x96,0x7e,0x7f,0x36,0x18,0x2d,0xf4,0x69,0x47,0x0, 0x8e,0xa, 0xe6,0xa, 0xfa, -0x2d,0xfe,0x3e,0xf4,0x2d,0xf1,0x7d,0xe0,0x1b,0x7a,0x40,0xb, 0x60,0xbc,0x56,0x38, -0xdc,0x2c,0xa5,0x6c,0x66,0x80,0x20,0x7e,0x90,0x2, 0xac,0x96,0x7e,0x7f,0x36,0x18, -0x2d,0xf4,0x69,0x47,0x0, 0xd6,0xa, 0xe6,0xa, 0xfa,0x2d,0xfe,0x3e,0xf4,0x2d,0xf1, -0x7d,0xe0,0x1b,0x7a,0x40,0xb, 0x60,0xbc,0x76,0x38,0xdc,0x7e,0x7f,0x36,0x20,0x69, -0x47,0x0, 0x4, 0x1e,0x44,0x5e,0x44,0x0, 0x1, 0x78,0x54,0x2c,0xa7,0x6c,0x66,0x80, -0x20,0x7e,0x90,0x2, 0xac,0x96,0x7e,0x7f,0x36,0x18,0x2d,0xf4,0x69,0x47,0x1, 0x1c, -0xa, 0xe6,0xa, 0xfa,0x2d,0xfe,0x3e,0xf4,0x2d,0xf1,0x7d,0xe0,0x1b,0x7a,0x40,0xb, -0x60,0xbc,0x56,0x38,0xdc,0x2c,0xa5,0x6c,0x66,0x80,0x20,0x7e,0x50,0x2, 0xac,0x56, -0x7e,0x7f,0x36,0x18,0x2d,0xf2,0x69,0x27,0x1, 0x64,0xa, 0xf6,0xa, 0x4a,0x2d,0x4f, -0x3e,0x44,0x7f,0x70,0x2d,0xf4,0x1b,0x7a,0x20,0xb, 0x60,0xbc,0x76,0x38,0xdc,0xda, -0x79,0x22,0xbe,0x8, 0x0, 0x0, 0x78,0x2, 0xe1,0xf4,0xbe,0x18,0x0, 0x0, 0x78,0x2, -0xe1,0xf4,0x29,0xb1,0x0, 0x2, 0xbe,0xb0,0x3, 0x28,0x5, 0xe4,0x39,0xb1,0x0, 0x2, -0x29,0xb1,0x0, 0x3, 0xbe,0xb0,0x40,0x28,0x6, 0x74,0x40,0x39,0xb1,0x0, 0x3, 0x29, -0xb1,0x0, 0x2, 0xa, 0x4b,0x9, 0xa4,0x3, 0xe5,0x39,0xb0,0x0, 0x4, 0x29,0x91,0x0, -0x3, 0x39,0x90,0x0, 0x5, 0xb4,0x3, 0xf, 0xb, 0x1a,0xf0,0x7e,0xe4,0x0, 0x6, 0x8d, -0xfe,0x79,0xf0,0x0, 0x2, 0x80,0x7, 0xb, 0x1a,0x40,0x79,0x40,0x0, 0x2, 0xb, 0x1a, -0x40,0x1e,0x44,0x29,0xb1,0x0, 0x4, 0xa, 0xeb,0x7d,0xf4,0x9d,0xfe,0x79,0xf0,0x0, -0x6, 0x1b,0x45,0x79,0x40,0x0, 0x8, 0xb, 0x1a,0xf0,0x1e,0xf4,0x69,0x41,0x0, 0x5, -0x9d,0xf4,0x9e,0xf4,0x0, 0xa, 0x79,0xf0,0x0, 0xa, 0x79,0x40,0x0, 0xc, 0x29,0xb1, -0x0, 0x7, 0x39,0xb0,0x0, 0xe, 0x39,0xb0,0x0, 0xf, 0xa, 0x3b,0x29,0xb0,0x0, 0xe, -0xa, 0x2b,0x2d,0x23,0x29,0xb0,0x0, 0x5, 0xa, 0x3b,0xad,0x32,0xa, 0x2a,0x12,0x1d, -0x4a,0x1b,0xa, 0x30,0x22,0x12,0x44,0x16,0x12,0x62,0xf4,0x2, 0x24,0x74,0x32,0xff, -0xca,0x3b,0x7f,0x30,0x7e,0x3b,0xb0,0xf5,0x2a,0x29,0xb3,0x0, 0x1, 0xbe,0xb1,0x2a, -0x28,0x2, 0xf5,0x2a,0x69,0x13,0x0, 0x6, 0x6d,0x0, 0x7e,0x34,0x0, 0xf2,0x74,0xff, -0x12,0x20,0x12,0x7f,0x3, 0x12,0x7, 0xa8,0xa9,0xd6,0xcb,0x75,0x28,0x0, 0x80,0x33, -0x75,0x29,0x0, 0x80,0x23,0x7e,0x11,0x28,0x74,0xb, 0xac,0x1b,0xe5,0x29,0xa, 0x1b, -0x2d,0x1, 0x3e,0x4, 0x69,0x13,0x0, 0x6, 0x2d,0x10,0x6d,0x0, 0xb, 0xa, 0x30,0x6e, -0x34,0xff,0xff,0x1b,0xa, 0x30,0x5, 0x29,0x29,0x73,0x0, 0x1, 0xbe,0x71,0x29,0x38, -0xd4,0x5, 0x28,0x7e,0x3b,0x70,0xbe,0x71,0x28,0x38,0xc5,0x69,0x33,0x0, 0x6, 0x7e, -0xf, 0x36,0x51,0x79,0x30,0x0, 0x4, 0xe5,0x2a,0xa, 0x2b,0x7d,0x32,0x7c,0x67,0x6c, -0x77,0x2d,0x32,0x7e,0xf, 0x36,0x51,0x79,0x30,0x0, 0xc, 0x6d,0x11,0x7e,0x1f,0x36, -0x51,0x1b,0x1a,0x10,0x7e,0x34,0x0, 0xd0,0x12,0x19,0x84,0x75,0x28,0x0, 0xe5,0x28, -0xbe,0xb0,0x4, 0x50,0x17,0x7e,0xa1,0x28,0x74,0x4, 0xa4,0x7e,0x1f,0x36,0x51,0x69, -0x11,0x0, 0x26,0x60,0x44,0x1e,0x14,0x14,0x78,0xfb,0x80,0x3d,0xe5,0x28,0xbe,0xb0, -0x8, 0x50,0x1b,0xe5,0x28,0xa, 0x5b,0x1b,0x56,0x3e,0x54,0x3e,0x54,0x7e,0x1f,0x36, -0x51,0x69,0x11,0x0, 0x28,0x60,0x22,0x1e,0x14,0x14,0x78,0xfb,0x80,0x1b,0xe5,0x28, -0xa, 0x5b,0x9e,0x54,0x0, 0x8, 0x3e,0x54,0x3e,0x54,0x7e,0x1f,0x36,0x51,0x69,0x11, -0x0, 0x2a,0x60,0x5, 0x1e,0x14,0x14,0x78,0xfb,0x5e,0x14,0x0, 0xf, 0x7e,0xa1,0x28, -0x74,0x2, 0xa4,0x69,0x33,0x0, 0x6, 0x2d,0x35,0x6d,0x22,0x1b,0x1a,0x10,0x5, 0x28, -0xe5,0x28,0xbe,0xb0,0xb, 0x40,0x87,0xa9,0xc6,0xcb,0xda,0x3b,0x22,0xca,0x3b,0x7f, -0x30,0x74,0x1, 0x12,0x1d,0x14,0x29,0x73,0x1, 0xd, 0x2e,0x70,0xff,0x92,0x4, 0x29, -0xb3,0x1, 0xe, 0x12,0x1c,0xfc,0x7f,0x3, 0x12,0x16,0x52,0x7f,0x3, 0x12,0x3, 0x95, -0x29,0x73,0x0, 0xa, 0xa, 0x37,0x7e,0xf, 0x3, 0xe1,0x79,0x30,0x0, 0x24,0x29,0x73, -0x0, 0xb5,0xa, 0x27,0x3e,0x24,0x3e,0x24,0x3e,0x24,0x3e,0x24,0x3e,0x24,0x3e,0x24, -0x3e,0x24,0x69,0x33,0x1, 0x19,0x4d,0x32,0x7e,0xf, 0x3, 0xe1,0x79,0x30,0x0, 0x2, -0x29,0x73,0x0, 0xa, 0xa, 0x47,0x29,0x73,0x0, 0x1, 0xa, 0x57,0x9d,0x54,0xf5,0x32, -0x7f,0x3, 0x12,0x14,0x6a,0x29,0x73,0x0, 0xb7,0x2e,0x70,0xff,0x92,0x4, 0x7f,0x3, -0xe5,0x32,0x12,0x15,0xb8,0x69,0x23,0x1, 0x15,0x3e,0x24,0x3e,0x24,0x3e,0x24,0x3e, -0x24,0x3e,0x24,0x3e,0x24,0x29,0x73,0x1, 0x14,0xa, 0x37,0x2d,0x32,0x7e,0xf, 0x3, -0xe1,0x79,0x30,0x0, 0x2a,0x29,0x73,0x1, 0x13,0xa, 0x37,0x7e,0xf, 0x3, 0xe1,0x79, -0x30,0x0, 0x2c,0x7e,0x34,0x0, 0x1, 0x7e,0xf, 0x3, 0xe1,0x79,0x30,0x0, 0x34,0x7e, -0x34,0x1, 0xb, 0x7e,0xf, 0x3, 0xe1,0x79,0x30,0x0, 0x2e,0x29,0x73,0x0, 0x1, 0xa, -0x37,0x7e,0xf, 0x3, 0xe1,0x79,0x30,0x0, 0x10,0x29,0x73,0x0, 0xb9,0x7e,0x60,0x1, -0x7e,0xf, 0x3, 0xe1,0x79,0x30,0x0, 0x1a,0x69,0x33,0x0, 0xba,0x7e,0xf, 0x3, 0xe1, -0x79,0x30,0x0, 0x1c,0x69,0x33,0x0, 0xbc,0x7e,0xf, 0x3, 0xe1,0x79,0x30,0x0, 0x1e, -0x7f,0x3, 0x12,0x12,0xf5,0xda,0x3b,0x22,0x7f,0x21,0xa9,0xd6,0xcb,0x69,0x30,0x0, -0x4, 0x7e,0x7f,0x36,0x51,0x79,0x37,0x0, 0x4, 0x69,0x30,0x0, 0x8, 0x7e,0x7f,0x36, -0x51,0x79,0x37,0x0, 0x6, 0x69,0x30,0x0, 0x6, 0x7e,0x7f,0x36,0x51,0x79,0x37,0x0, -0x8, 0x29,0x70,0x0, 0x1, 0x7c,0x47,0x6c,0x55,0x7e,0xb, 0x70,0xa, 0x37,0x2d,0x32, -0x7e,0x7f,0x36,0x51,0x79,0x37,0x0, 0xc, 0x29,0x70,0x0, 0x2, 0xa, 0x37,0x1b,0x34, -0x7e,0x7f,0x36,0x51,0x79,0x37,0x0, 0xa, 0x69,0x30,0x0, 0xa, 0x7e,0x7f,0x36,0x51, -0x79,0x37,0x0, 0xe, 0x69,0x30,0x0, 0xc, 0x7e,0x7f,0x36,0x51,0x79,0x37,0x0, 0x10, -0x69,0x30,0x0, 0xe, 0x7e,0x7f,0x36,0x51,0x79,0x37,0x0, 0x12,0x69,0x30,0x0, 0x10, -0x7e,0x7f,0x36,0x51,0x79,0x37,0x0, 0x30,0x29,0x70,0x0, 0x3, 0x7c,0x27,0x6c,0x33, -0x7e,0x1f,0x36,0x51,0x1b,0x1a,0x10,0x7e,0x34,0x0, 0xa0,0x12,0x19,0x84,0x7e,0x1f, -0x36,0x51,0x69,0x11,0x0, 0x1a,0x7a,0x2b,0x30,0x69,0x11,0x0, 0x1c,0x39,0x32,0x0, -0x1, 0x69,0x11,0x0, 0x16,0x79,0x12,0x0, 0x2, 0x69,0x11,0x0, 0x18,0x79,0x12,0x0, -0x4, 0x69,0x11,0x0, 0x22,0x79,0x12,0x0, 0x6, 0x69,0x11,0x0, 0x24,0x79,0x12,0x0, -0x8, 0x69,0x11,0x0, 0x1e,0x79,0x12,0x0, 0xa, 0x69,0x31,0x0, 0x20,0x79,0x32,0x0, -0xc, 0xa9,0xc6,0xcb,0x22,0xca,0x79,0x7f,0x60,0x29,0x76,0x1, 0x1e,0xa, 0x27,0x5e, -0x24,0x0, 0x1, 0x3e,0x24,0x3e,0x24,0x3e,0x24,0x3e,0x24,0x3e,0x24,0x3e,0x24,0x7e, -0xf, 0x3, 0xe1,0xb, 0x15,0xb, 0xa, 0x30,0x5e,0x70,0xbf,0x4d,0x32,0x1b,0xa, 0x30, -0x29,0x76,0x1, 0x1f,0x7c,0xf7,0xbe,0xf0,0x3, 0x38,0x4, 0x7c,0xf7,0x80,0x3, 0x7e, -0xf0,0x3, 0xa, 0x3f,0x5e,0x34,0x0, 0x3, 0x7d,0x23,0x7c,0x45,0x6c,0x55,0x3e,0x24, -0x3e,0x24,0x3e,0x24,0x7e,0xf, 0x3, 0xe1,0xb, 0x15,0xb, 0xa, 0x30,0x5e,0x60,0xe7, -0x4d,0x32,0x1b,0xa, 0x30,0x29,0x76,0x0, 0xb8,0x7a,0x73,0x2, 0xa3,0x69,0x36,0x1, -0x17,0x7a,0x37,0x2, 0xa4,0x29,0x76,0x1, 0x31,0x7a,0x73,0x2, 0xa6,0x6c,0xee,0x80, -0x46,0x74,0x5, 0xac,0xbe,0x7f,0x16,0x2d,0x35,0x69,0x31,0x1, 0x21,0x7a,0x37,0x2, -0x9f,0x74,0x5, 0xac,0xbe,0x7f,0x16,0x2d,0x35,0x29,0x71,0x1, 0x23,0x7a,0x73,0x2, -0xa1,0x74,0x5, 0xac,0xbe,0x7f,0x16,0x2d,0x35,0x29,0x71,0x1, 0x24,0x7a,0x73,0x2, -0xa2,0x7e,0x8, 0x2, 0x8f,0x7e,0x18,0x2, 0x9f,0x12,0xf, 0x42,0x7e,0x8, 0x2, 0x8f, -0x7c,0xbe,0x12,0x1, 0x30,0xb, 0xe0,0xbc,0xfe,0x38,0xb6,0xda,0x79,0x22,0xca,0x79, -0x29,0x70,0x0, 0xb, 0xa, 0x27,0x7e,0xb, 0x70,0xa, 0x37,0x2d,0x32,0x6d,0x44,0x6c, -0xaa,0x7e,0x50,0x2, 0xac,0x5a,0x7e,0x7f,0x3, 0xd9,0x2d,0xf2,0x79,0x47,0x0, 0x2, -0xb, 0xa0,0xbe,0xa0,0x23,0x78,0xea,0x6c,0xaa,0x80,0x4f,0xa, 0x2a,0x7f,0x70,0x2d, -0xf2,0x29,0x67,0x0, 0x54,0xbe,0x60,0x23,0x50,0x1d,0x29,0xb7,0x0, 0xc6,0x7c,0x8b, -0x6c,0x99,0x7e,0x50,0x2, 0xac,0x56,0x7e,0x7f,0x3, 0xd9,0x2d,0xf2,0xb, 0xf5,0xb, -0x7a,0x20,0x4d,0x24,0x1b,0x7a,0x20,0xa, 0x2a,0x7f,0x70,0x2d,0xf2,0x29,0xb7,0x0, -0x54,0xa, 0x4b,0x7e,0x50,0x2, 0xac,0x5a,0x7e,0x7f,0x3, 0xd9,0x2d,0xf2,0xb, 0xf5, -0xb, 0x7a,0x20,0x4d,0x24,0x1b,0x7a,0x20,0xb, 0xa0,0xbc,0x7a,0x38,0xad,0x6c,0xaa, -0x80,0x1d,0xa, 0x3a,0x2d,0x31,0x7d,0x20,0x29,0xb1,0x0, 0x77,0xa, 0x4b,0x7e,0xf0, -0x2, 0xac,0xfa,0x7e,0x1f,0x3, 0xd9,0x2d,0x37,0x79,0x41,0x0, 0x52,0xb, 0xa0,0x29, -0xb0,0x0, 0x1, 0xbc,0xba,0x38,0xdb,0xda,0x79,0x22,0xca,0x3b,0x7f,0x30,0xe4,0x12, -0x19,0xdd,0x6c,0xaa,0x7e,0x50,0x2, 0xac,0x5a,0x69,0x13,0x1, 0x1b,0x2d,0x12,0x7e, -0x4, 0x0, 0xff,0xb, 0xa, 0x30,0x7e,0xf, 0x36,0x1c,0x2d,0x12,0x79,0x30,0x3, 0xd4, -0xb, 0xa0,0xbe,0xa0,0xc, 0x78,0xdd,0x29,0x73,0x1, 0x1d,0xa, 0x37,0x7e,0xf, 0x36, -0x1c,0x79,0x30,0x3, 0xf2,0x6c,0xaa,0x7e,0x50,0x2, 0xac,0x5a,0x69,0x13,0x1, 0x2f, -0x2d,0x12,0x7e,0x4, 0x0, 0xff,0xb, 0xa, 0x30,0x7e,0xf, 0x36,0x1c,0x2d,0x12,0x79, -0x30,0x3, 0xf4,0xb, 0xa0,0xbe,0xa0,0xc, 0x78,0xdd,0x29,0x73,0x1, 0x31,0xa, 0x37, -0x7e,0xf, 0x36,0x1c,0x79,0x30,0x4, 0x12,0x29,0xb3,0x1, 0x32,0x70,0x2, 0x81,0xf6, -0x7e,0x34,0xff,0xff,0x7e,0xf, 0x36,0x1c,0x79,0x30,0x4, 0xc, 0x7e,0xf, 0x36,0x1c, -0x79,0x30,0x4, 0xe, 0xa1,0x8, 0x6d,0x33,0x7e,0xf, 0x36,0x1c,0x79,0x30,0x4, 0xc, -0x7e,0xf, 0x36,0x1c,0x79,0x30,0x4, 0xe, 0x7e,0xf, 0x36,0x1c,0x79,0x30,0x4, 0x10, -0xda,0x3b,0x22,0x7c,0xab,0x6c,0x77,0x7e,0x50,0x3, 0xac,0x57,0x7d,0x42,0x2e,0x44, -0x1f,0x90,0x7a,0x91,0x82,0x7a,0x81,0x83,0xe4,0x93,0xbc,0xba,0x78,0x23,0x7d,0x42, -0x2e,0x44,0x1f,0x91,0x7a,0x91,0x82,0x7a,0x81,0x83,0xe4,0x93,0x7a,0xb, 0xb0,0x2e, -0x24,0x1f,0x92,0x7a,0x51,0x82,0x7a,0x41,0x83,0xe4,0x93,0x39,0xb0,0x0, 0x1, 0x80, -0x7, 0xb, 0x70,0xbe,0x70,0x2, 0x28,0xbf,0xbe,0x70,0x2, 0x28,0x25,0x7e,0x34,0x1f, -0x4e,0x79,0x30,0x0, 0x2, 0x7e,0x34,0x1f,0x6, 0x79,0x30,0x0, 0x4, 0xbe,0xa0,0x81, -0x78,0x9, 0x74,0x23,0x7a,0xb, 0xb0,0x74,0x24,0x80,0x38,0x74,0x1, 0x7a,0xb, 0xb0, -0x80,0x31,0x2e,0xa0,0xf4,0x68,0x4, 0xb, 0xa0,0x78,0x11,0x7e,0x34,0x1f,0x71,0x79, -0x30,0x0, 0x2, 0x7e,0x34,0x1f,0x2a,0x79,0x30,0x0, 0x4, 0x22,0x7e,0x34,0x1f,0x4e, -0x79,0x30,0x0, 0x2, 0x7e,0x34,0x1f,0x6, 0x79,0x30,0x0, 0x4, 0x74,0x23,0x7a,0xb, -0xb0,0x74,0x24,0x39,0xb0,0x0, 0x1, 0x22,0xca,0x79,0x7c,0xeb,0x7a,0xd, 0x33,0x7e, -0x1f,0x36,0x1c,0x2e,0x34,0x3, 0xec,0x7a,0x1d,0x38,0x7e,0x8, 0x2, 0x8f,0x7e,0x34, -0x0, 0x6, 0xe4,0x12,0x20,0x12,0xa2,0x4, 0xe4,0x33,0x7e,0x1d,0x33,0x39,0xb1,0x0, -0xb7,0x7e,0x1d,0x33,0x29,0x71,0x0, 0xb7,0x7a,0x73,0x3, 0xd7,0x30,0x4, 0x3d,0x6c, -0xff,0x80,0x35,0xa, 0x5f,0x1e,0x54,0x1e,0x54,0x1e,0x54,0x1e,0x54,0x7c,0xab,0xa, -0x3f,0x7e,0x24,0x0, 0x10,0x12,0x1d,0x4a,0x7c,0xb5,0x7e,0x44,0x0, 0x1, 0x60,0x5, -0x3e,0x44,0x14,0x78,0xfb,0x7e,0x50,0x2, 0xac,0x5a,0x2e,0x24,0x2, 0x8f,0xb, 0x28, -0x30,0x4d,0x34,0x1b,0x28,0x30,0xb, 0xf0,0xbc,0xef,0x38,0xc7,0x7e,0xd, 0x33,0x12, -0x3, 0x95,0xe4,0x12,0x19,0xdd,0x6c,0xff,0x74,0x2, 0xac,0xbf,0x49,0x15,0x2, 0x8f, -0x7e,0x1d,0x38,0x2d,0x35,0x1b,0x1a,0x10,0xb, 0xf0,0xbe,0xf0,0x3, 0x40,0xe9,0xda, -0x79,0x22,0x69,0x30,0x0, 0xc0,0x29,0xb0,0x0, 0xb5,0xb4,0x3, 0x12,0x7e,0x44,0x0, -0x6, 0x7d,0x53,0x8d,0x54,0x7e,0x7f,0x3, 0xe1,0x79,0x57,0x0, 0x6, 0x80,0x8, 0x7e, -0x2f,0x3, 0xe1,0x79,0x32,0x0, 0x6, 0x29,0x50,0x0, 0xb8,0xa, 0x55,0x7d,0x23,0x1e, -0x24,0x9d,0x25,0x7e,0x2f,0x3, 0xe1,0x79,0x22,0x0, 0x18,0x7d,0x23,0x1e,0x24,0x1b, -0x25,0x7e,0x2f,0x3, 0xe1,0x79,0x22,0x0, 0x38,0x69,0x20,0x1, 0x17,0x1e,0x34,0x9d, -0x32,0x9e,0x34,0x0, 0xa, 0x7e,0x2f,0x3, 0xe1,0x79,0x32,0x0, 0x26,0x69,0x30,0x1, -0x17,0x7e,0x2f,0x3, 0xe1,0x79,0x32,0x0, 0x28,0x29,0x70,0x0, 0xb9,0xa, 0x37,0x7e, -0x60,0x1, 0x7e,0x2f,0x3, 0xe1,0x79,0x32,0x0, 0x1a,0x29,0x70,0x0, 0xb, 0xa, 0x27, -0x7e,0xb, 0x70,0xa, 0x37,0x2d,0x32,0x7e,0x2f,0x3, 0xe1,0x79,0x32,0x0, 0x8, 0x2, -0x13,0xbe,0xa9,0xd6,0xcb,0x69,0x20,0x0, 0x4, 0x7e,0x7f,0x36,0x51,0x79,0x27,0x0, -0x4, 0x69,0x20,0x0, 0x6, 0x7e,0x7f,0x36,0x51,0x79,0x27,0x0, 0x6, 0x69,0x20,0x0, -0x8, 0x7e,0x7f,0x36,0x51,0x79,0x27,0x0, 0x8, 0x6d,0x22,0x7e,0x7f,0x36,0x51,0x79, -0x27,0x0, 0xe, 0x7c,0x4b,0x7c,0x64,0x7e,0x2f,0x36,0x51,0x79,0x32,0x0, 0x10,0x7e, -0x2f,0x36,0x51,0x2e,0x54,0x0, 0xe, 0xb, 0x2a,0x30,0x6d,0x33,0x7e,0x2f,0x36,0x51, -0x79,0x32,0x0, 0xa, 0x7e,0xb, 0x70,0x7c,0x47,0x29,0x70,0x0, 0x1, 0x2d,0x32,0x7e, -0xf, 0x36,0x51,0x79,0x30,0x0, 0xc, 0x6d,0x11,0x7e,0x1f,0x36,0x51,0x1b,0x1a,0x10, -0x7e,0x34,0x0, 0x30,0x12,0x19,0x84,0xa9,0xc6,0xcb,0x22,0xa9,0xd6,0xcb,0x69,0x30, -0x0, 0x6, 0x7e,0x2f,0x36,0x51,0x79,0x32,0x0, 0x4, 0x69,0x30,0x0, 0x8, 0x7e,0x2f, -0x36,0x51,0x79,0x32,0x0, 0x8, 0x29,0x70,0x0, 0x2, 0x7c,0x47,0x6c,0x55,0x29,0x70, -0x0, 0x3, 0xa, 0x37,0x2d,0x32,0x7e,0x2f,0x36,0x51,0x79,0x32,0x0, 0xc, 0x7e,0xb, -0x70,0x7c,0x47,0x29,0x70,0x0, 0x1, 0xa, 0x37,0x2d,0x32,0x7e,0x2f,0x36,0x51,0x79, -0x32,0x0, 0xa, 0x29,0x70,0x0, 0x4, 0xa, 0x37,0x7e,0x2f,0x36,0x51,0x79,0x32,0x0, -0xe, 0x29,0xb0,0x0, 0x5, 0x54,0x1, 0x7c,0x2b,0x6c,0x33,0x7e,0x1f,0x36,0x51,0x1b, -0x1a,0x10,0x7e,0x34,0x0, 0xc0,0x12,0x19,0x84,0xa9,0xc6,0xcb,0x22,0x2e,0x34,0x4, -0x0, 0x7e,0xf, 0x3, 0xe1,0x79,0x30,0x0, 0x80,0x7e,0x34,0x4, 0x0, 0x9d,0x32,0x7e, -0xf, 0x3, 0xe1,0x79,0x30,0x0, 0x82,0x7e,0x34,0x0, 0x1, 0x7e,0xf, 0x3, 0xe1,0x79, -0x30,0x0, 0x84,0xa, 0x3b,0x7e,0xf, 0x3, 0xe1,0x79,0x30,0x0, 0x86,0x22,0xff,0xff, -0xa9,0xd6,0xcb,0xc2,0x1a,0x69,0x30,0x0, 0x4, 0x7e,0x2f,0x36,0x51,0x79,0x32,0x0, -0x4, 0x69,0x30,0x0, 0x6, 0x7e,0x2f,0x36,0x51,0x79,0x32,0x0, 0x6, 0x69,0x30,0x0, -0x8, 0x7e,0x2f,0x36,0x51,0x79,0x32,0x0, 0x8, 0x7e,0xb, 0x70,0x7c,0x47,0x6c,0x55, -0x29,0x70,0x0, 0x1, 0xa, 0x37,0x2d,0x32,0x7e,0x2f,0x36,0x51,0x79,0x32,0x0, 0xc, -0x29,0x70,0x0, 0x2, 0xa, 0x37,0x7e,0x2f,0x36,0x51,0x79,0x32,0x0, 0xe, 0x29,0xb0, -0x0, 0x3, 0x54,0x1, 0xa, 0x5b,0x7c,0xab,0xe4,0x7e,0x1f,0x36,0x51,0x1b,0x1a,0x50, -0x69,0x30,0x0, 0xa, 0x12,0x19,0x84,0xa9,0xc6,0xcb,0x22,0x74,0x3, 0x12,0x1c,0x86, -0x74,0x1, 0x12,0x19,0xdd,0xa9,0xd1,0xc4,0x7e,0xf, 0x3, 0xd9,0x2e,0x14,0x0, 0x9e, -0xb, 0xa, 0x30,0x4e,0x70,0x20,0x1b,0xa, 0x30,0x7e,0xf, 0x3, 0xd9,0xb, 0xa, 0x30, -0x5e,0x70,0xf9,0x1b,0xa, 0x30,0x7e,0xf, 0x3, 0xd9,0xb, 0xa, 0x30,0x4e,0x70,0x1, -0x1b,0xa, 0x30,0x7e,0xf, 0x3, 0xe1,0xb, 0x16,0xb, 0xa, 0x30,0x4e,0x70,0x1, 0x1b, -0xa, 0x30,0xc2,0xb, 0xe4,0x7a,0xb3,0x3, 0xf9,0x7e,0x1f,0x3, 0xd9,0xb, 0x1a,0x30, -0x5e,0x34,0x0, 0x1, 0x78,0xf3,0x74,0x2, 0x2, 0x1c,0x86,0xa9,0xd6,0xcb,0x69,0x20, -0x0, 0x4, 0x7e,0x2f,0x36,0x51,0x79,0x22,0x0, 0x4, 0x69,0x20,0x0, 0x8, 0x7e,0x2f, -0x36,0x51,0x79,0x22,0x0, 0x8, 0x7e,0xb, 0x50,0xa, 0x55,0x7c,0xab,0xe4,0x29,0x50, -0x0, 0x1, 0xa, 0x25,0x2d,0x25,0x7e,0x2f,0x36,0x51,0x79,0x22,0x0, 0xc, 0x29,0x50, -0x0, 0x2, 0xa, 0x25,0x7e,0xf, 0x36,0x51,0x79,0x20,0x0, 0xe, 0x7e,0xf, 0x36,0x51, -0x79,0x30,0x0, 0xa, 0x6d,0x11,0x7e,0x1f,0x36,0x51,0x1b,0x1a,0x10,0x7e,0x34,0x0, -0x40,0x12,0x19,0x84,0xa9,0xc6,0xcb,0x22,0xca,0x7b,0xca,0x6b,0xca,0x5b,0xca,0x4b, -0xca,0x2b,0xca,0x1b,0xca,0xb, 0xc0,0xd0,0xc0,0x83,0xc0,0x82,0xd2,0xb, 0x7e,0xf, -0x3, 0xe1,0x69,0x30,0x0, 0x4, 0x7a,0x73,0x3, 0xf9,0x7e,0x73,0x3, 0xf9,0xa, 0x37, -0x5e,0x34,0x0, 0x4, 0x68,0x4, 0xd2,0xa, 0x80,0x2, 0xc2,0xa, 0x7e,0x34,0x0, 0x1f, -0x79,0x30,0x0, 0x4, 0xc2,0xc3,0x12,0x1c,0xc9,0x12,0x71,0x41,0xa9,0xc1,0xc4,0xd0, -0x82,0xd0,0x83,0xd0,0xd0,0xda,0xb, 0xda,0x1b,0xda,0x2b,0xda,0x4b,0xda,0x5b,0xda, -0x6b,0xda,0x7b,0x32,0xa9,0xd7,0xcb,0x7d,0x23,0x4e,0x50,0x1, 0x7e,0xf, 0x36,0x51, -0xb, 0xa, 0x30,0x4d,0x32,0x1b,0xa, 0x30,0x80,0x1e,0x7e,0xf, 0x36,0x51,0xb, 0xa, -0x30,0x7d,0x23,0x5e,0x24,0x0, 0x8, 0xbe,0x24,0x0, 0x8, 0x78,0xb, 0xa9,0xd7,0xcb, -0x4e,0x70,0x4, 0x1b,0xa, 0x30,0xd2,0x1a,0x7e,0xf, 0x36,0x51,0x69,0x30,0x0, 0x38, -0x5e,0x34,0x80,0x0, 0xbe,0x34,0x80,0x0, 0x78,0xd0,0xb, 0xa, 0x30,0x4e,0x60,0x40, -0x1b,0xa, 0x30,0x6d,0x11,0x7e,0x1f,0x36,0x51,0x1b,0x1a,0x10,0x22,0x7c,0xab,0xbe, -0xa0,0x2, 0x78,0x1b,0x7e,0x1f,0x3, 0xd9,0xb, 0x1a,0x30,0x1e,0x34,0x1e,0x34,0x1e, -0x34,0x5e,0x34,0x0, 0x1, 0x78,0x6, 0x74,0x1, 0x7c,0xab,0x80,0x2, 0x6c,0xaa,0xa, -0x2a,0x5e,0x24,0x0, 0x1, 0x3e,0x24,0x3e,0x24,0x3e,0x24,0x7e,0xf, 0x3, 0xd9,0xb, -0xa, 0x30,0x5e,0x70,0xf7,0x4d,0x32,0x1b,0xa, 0x30,0x7e,0x1f,0x3, 0xd9,0xb, 0x1a, -0x20,0x1e,0x24,0x1e,0x24,0x1e,0x24,0x1e,0x24,0x5e,0x24,0x0, 0x1, 0xa, 0x3a,0xbd, -0x23,0x78,0xe7,0x22,0xca,0xf8,0x7c,0xfb,0x7f,0x71,0x7f,0x60,0xe5,0x24,0x7e,0x8, -0x0, 0x25,0x12,0x15,0x13,0xbe,0xf0,0x23,0x28,0x3, 0x7e,0xf0,0x23,0x6c,0xaa,0x80, -0x33,0xa, 0x3a,0x2d,0x3f,0x7d,0x2e,0x7e,0x1b,0x70,0xbe,0x71,0x25,0x40,0xd, 0x74, -0x23,0xa, 0x4a,0x7f,0x6, 0x2d,0x14,0x7a,0xb, 0xb0,0x80,0x16,0xa, 0x37,0x2e,0x35, -0x27,0x7a,0x71,0x82,0x7a,0x61,0x83,0xe4,0x93,0xa, 0x4a,0x7f,0x16,0x2d,0x34,0x7a, -0x1b,0xb0,0xb, 0xa0,0xbc,0xfa,0x38,0xc9,0xda,0xf8,0x22,0x6c,0xaa,0x7e,0x50,0x2, -0xac,0x5a,0x69,0xf0,0x0, 0xe, 0x69,0xe0,0x0, 0xc, 0x2d,0xf2,0x29,0xb7,0x0, 0x1, -0x7c,0x8b,0x6c,0x99,0x7e,0x7b,0xb0,0xa, 0x3b,0x4d,0x34,0x7e,0x7f,0x36,0x1c,0x2d, -0xf2,0x79,0x37,0x3, 0xb0,0xb, 0xa0,0xbe,0xa0,0x12,0x40,0xd1,0x7e,0x34,0xff,0xff, -0x7e,0xf, 0x36,0x1c,0x79,0x30,0x3, 0xa8,0x7e,0xf, 0x36,0x1c,0x79,0x30,0x3, 0xaa, -0x7e,0xf, 0x36,0x1c,0x79,0x30,0x3, 0xac,0x7e,0xf, 0x36,0x1c,0x79,0x30,0x3, 0xae, -0x22,0xca,0x7b,0xca,0x6b,0xca,0x5b,0xca,0x4b,0xca,0x2b,0xca,0x1b,0xca,0xb, 0xc0, -0xd0,0xc0,0x83,0xc0,0x82,0xd2,0x1b,0x7e,0xf, 0x36,0x20,0xb, 0xa, 0x30,0x7c,0x57, -0x7a,0x53,0x36,0x17,0x4e,0x70,0xc, 0x1b,0xa, 0x30,0xc2,0xc6,0x6d,0x33,0x7e,0xf, -0x36,0x20,0x79,0x30,0x0, 0x10,0x12,0x1c,0xc9,0x12,0x71,0x41,0xd0,0x82,0xd0,0x83, -0xd0,0xd0,0xda,0xb, 0xda,0x1b,0xda,0x2b,0xda,0x4b,0xda,0x5b,0xda,0x6b,0xda,0x7b, -0x32,0xca,0xf8,0x7c,0xfb,0x7f,0x71,0x7f,0x60,0xe5,0x24,0x7e,0x8, 0x0, 0x25,0x12, -0x15,0x13,0x6c,0xaa,0x80,0x33,0xa, 0x3a,0x2d,0x3f,0x7d,0x2e,0x7e,0x1b,0x70,0xbe, -0x71,0x26,0x40,0xd, 0x74,0x24,0xa, 0x4a,0x7f,0x6, 0x2d,0x14,0x7a,0xb, 0xb0,0x80, -0x16,0xa, 0x37,0x2e,0x35,0x29,0x7a,0x71,0x82,0x7a,0x61,0x83,0xe4,0x93,0xa, 0x4a, -0x7f,0x16,0x2d,0x34,0x7a,0x1b,0xb0,0xb, 0xa0,0xbc,0xfa,0x38,0xc9,0xda,0xf8,0x22, -0xca,0x79,0x7c,0x6b,0x6c,0xaa,0x7e,0x90,0x2, 0xac,0x9a,0x7f,0x60,0x2d,0xd4,0x29, -0xb6,0x0, 0x1, 0xa, 0xfb,0x7d,0x2f,0x7c,0x45,0x6c,0x55,0x7d,0xf2,0x7e,0x6b,0xb0, -0xa, 0x2b,0x4d,0x2f,0x7e,0xf0,0x34,0xac,0xf7,0x2d,0x47,0xa, 0xe6,0x7e,0xf4,0x1, -0x38,0xad,0xfe,0x2d,0x4f,0x7e,0x7f,0x36,0x1c,0x2d,0xf4,0x79,0x27,0x0, 0x1c,0xb, -0xa0,0xbe,0xa0,0xc, 0x40,0xc0,0xda,0x79,0x22,0x7c,0x6b,0xa9,0xd6,0xcb,0xbe,0x60, -0x23,0x28,0x3, 0x7e,0x60,0x23,0xbe,0x70,0x24,0x28,0x3, 0x7e,0x70,0x24,0x7e,0x14, -0x0, 0x5, 0x7e,0x2f,0x36,0x51,0x79,0x12,0x0, 0x2, 0x7c,0x26,0x6c,0x33,0xa, 0x37, -0x2d,0x31,0x7e,0xf, 0x36,0x51,0x79,0x30,0x0, 0x32,0x7e,0xf, 0x36,0x51,0x79,0x20, -0x0, 0x14,0xa9,0xc6,0xcb,0x22,0x7e,0x34,0x0, 0x1f,0x7e,0xf, 0x3, 0xe1,0x79,0x30, -0x0, 0x4, 0xa9,0xd2,0xcd,0x7e,0xb3,0x3, 0xe9,0xb4,0x1, 0x7, 0x12,0x6, 0x80,0x7a, -0x73,0x3, 0xd8,0x7e,0xf, 0x3, 0xe1,0xb, 0xa, 0x30,0x4e,0x70,0x1, 0x1b,0xa, 0x30, -0x22,0x7c,0xa5,0xbe,0x34,0x0, 0x0, 0x28,0x10,0xa, 0x1b,0x3e,0x14,0x7d,0x23,0x7c, -0x45,0x6c,0x55,0x2d,0x21,0xa, 0x3a,0x80,0x8, 0xa, 0x2b,0x3e,0x24,0x7c,0x67,0x6c, -0x77,0x2d,0x32,0x7e,0xf, 0x36,0x20,0x79,0x30,0x0, 0x4, 0x22,0x7c,0xa7,0x7e,0x1f, -0x3, 0xd9,0x69,0x41,0x0, 0xa4,0x5e,0x44,0x10,0xf, 0xa, 0x1a,0x3e,0x14,0x3e,0x14, -0x3e,0x14,0x3e,0x14,0xa, 0x5b,0xc4,0x23,0x54,0xe0,0x7c,0xab,0xe4,0x2d,0x51,0x4d, -0x45,0x79,0x41,0x0, 0xa4,0x22,0x7e,0xf, 0x3, 0xd9,0x69,0x30,0x0, 0x9e,0x5e,0x70, -0xe7,0x1b,0xb1,0x68,0xc, 0x14,0x68,0xc, 0xb, 0xb1,0x78,0x5, 0x4e,0x70,0x10,0x80, -0x3, 0x4e,0x70,0x8, 0x79,0x30,0x0, 0x9e,0x22,0xa, 0x5b,0x5e,0x54,0x0, 0x1, 0xc4, -0x54,0xf0,0x7c,0xab,0xe4,0x7e,0xf, 0x3, 0xd9,0x2e,0x14,0x0, 0xa4,0xb, 0xa, 0x30, -0x5e,0x60,0xef,0x4d,0x35,0x1b,0xa, 0x30,0x22,0x7e,0xf, 0x3, 0xd9,0x2e,0x14,0x0, -0x9e,0xb, 0xa, 0x30,0x5e,0x70,0xdf,0x1b,0xa, 0x30,0x74,0x3, 0x12,0x1c,0x86,0xe4, -0x2, 0x1c,0x86,0xbe,0xb0,0x0, 0x28,0xa, 0xa9,0xd7,0xca,0xa9,0xd3,0xcb,0xa9,0xd2, -0xcb,0x22,0xa9,0xc7,0xca,0xa9,0xc3,0xcb,0xa9,0xc2,0xcb,0x22,0x30,0x4, 0xa, 0x54, -0x3, 0xa, 0x3b,0x2e,0x34,0x2, 0x0, 0x80,0x2, 0x6d,0x33,0x7e,0xf, 0x3, 0xe1,0x79, -0x30,0x0, 0x3a,0x22,0xbe,0xb0,0x0, 0x28,0x9, 0xa9,0xd6,0xca,0xd2,0xcd,0xa9,0xd1, -0xcb,0x22,0xa9,0xc6,0xca,0xc2,0xcd,0xa9,0xc1,0xcb,0x22,0x7e,0x34,0x0, 0xf, 0x7e, -0xf, 0x3, 0xe1,0x79,0x30,0x0, 0x4, 0xc2,0xc3,0xd2,0xeb,0x22,0x7d,0x13,0x7e,0x1f, -0x36,0x20,0x1b,0x1a,0x10,0xc2,0xc6,0xd2,0xee,0x22,0xc2,0xd5,0x7c,0xb4,0x30,0xe7, -0x8, 0xb2,0xd5,0x6e,0x24,0xff,0xff,0xb, 0x24,0x7c,0xb6,0x30,0xe7,0x12,0xb2,0xd5, -0x6e,0x34,0xff,0xff,0xb, 0x34,0x8d,0x32,0x6e,0x24,0xff,0xff,0xb, 0x24,0x80,0x2, -0x8d,0x32,0x30,0xd5,0x6, 0x6e,0x34,0xff,0xff,0xb, 0x34,0x22,0x7d,0x51,0xad,0x3, -0x7d,0x2, 0x7d,0x21,0xad,0x5, 0x2d,0x12,0xad,0x35,0x2d,0x21,0x22,0x7d,0x2, 0xad, -0x31,0xad,0x10,0x2d,0x21,0x22,0x6d,0x0, 0x74,0x10,0x4d,0x0, 0x78,0xb, 0x4d,0x22, -0x78,0x27,0x8d,0x31,0x7d,0x12,0x6d,0x22,0x22,0x7d,0x43,0x7d,0x32,0x6d,0x22,0x2f, -0x11,0x2d,0x44,0x50,0x2, 0xa5,0xf, 0xbf,0x10,0x40,0x4, 0x9f,0x10,0xb, 0x90,0x14, -0x78,0xed,0x7f,0x1, 0x6d,0x22,0x7d,0x34,0x22,0x7d,0x41,0x7d,0x13,0x8d,0x24,0x7d, -0x2, 0x2f,0x0, 0x40,0x4, 0xbd,0x4, 0x40,0x4, 0x9d,0x4, 0xb, 0x14,0x14,0x78,0xf1, -0x7d,0x23,0x7d,0x31,0x7d,0x10,0x6d,0x0, 0x22,0xc2,0xd5,0x7c,0xb0,0x30,0xe7,0x8, -0xb2,0xd5,0x9f,0x22,0x9f,0x20,0x7f,0x2, 0x7c,0xb4,0x30,0xe7,0x13,0xb2,0xd5,0x9f, -0x22,0x9f,0x21,0x7f,0x12,0x12,0x1d,0x98,0x9f,0x22,0x9f,0x20,0x7f,0x2, 0x80,0x3, -0x12,0x1d,0x98,0x30,0xd5,0x6, 0x9f,0x22,0x9f,0x21,0x7f,0x12,0x22,0x6c,0xaa,0x4d, -0x11,0x68,0x1a,0x1e,0x54,0x68,0xe, 0xb, 0x38,0x20,0x1b,0x18,0x20,0xb, 0x35,0xb, -0x15,0x1b,0x54,0x78,0xf2,0x50,0x6, 0x7e,0x39,0x40,0x7a,0x19,0x40,0x22,0x6c,0xaa, -0x4d,0x11,0x68,0x1e,0x1e,0x54,0x50,0xc, 0x7e,0x1b,0x0, 0x7a,0x19,0x0, 0x68,0x12, -0xb, 0x1c,0xb, 0x14,0xb, 0x1a,0x0, 0x1b,0x18,0x0, 0xb, 0x1d,0xb, 0x15,0x1b,0x54, -0x78,0xf2,0x22,0x75,0x84,0x1, 0x7e,0x44,0x47,0xef,0xe4,0x7a,0x49,0xb0,0x1b,0x44, -0x78,0xf9,0x7e,0xf8,0x3a,0xca,0x75,0xc, 0x0, 0x75,0xd, 0x0, 0x75,0xe, 0x2, 0x75, -0xf, 0x0, 0xc2,0x6, 0xc2,0x7, 0x75,0x1f,0x0, 0xc2,0xc, 0x75,0x64,0x47,0x75,0x65, -0xf0,0xd2,0xd, 0xc2,0xe, 0xc2,0x8, 0xc2,0xf, 0x75,0x66,0x3, 0x75,0x67,0x0, 0xc2, -0x11,0x75,0x68,0x0, 0xc2,0x12,0x75,0x69,0x0, 0xc2,0x13,0xc2,0x14,0x75,0x6a,0x0, -0xc2,0x15,0x75,0x14,0x0, 0x75,0x15,0x0, 0x75,0x16,0x0, 0x75,0x17,0x0, 0x75,0x18, -0x0, 0x75,0x19,0x0, 0x75,0x1a,0x64,0xc2,0x17,0xc2,0x19,0x75,0x6b,0x0, 0xd2,0x0, -0xd2,0x1, 0xd2,0x2, 0xc2,0xa, 0xd2,0xb, 0xd2,0x1b,0x7e,0x4, 0x0, 0xff,0x7e,0x14, -0x20,0x64,0xb, 0xa, 0x40,0x5d,0x44,0x68,0x1a,0x69,0x20,0x0, 0x2, 0xb, 0xe, 0xb, -0x44,0x80,0xa, 0x7e,0xb, 0xb0,0x7a,0x29,0xb0,0xb, 0x24,0xb, 0xc, 0x1b,0x44,0x78, -0xf2,0x80,0xdf,0x2, 0x23,0xa9,0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, -0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19, -0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,0x20,0x21,0x22,0x23,0x0, 0x1, 0x2, 0x3, 0x4, 0x5, -0x6, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x10,0x11,0x12,0x13,0x14,0x15, -0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,0x20,0x21,0x22,0x23,0x0, 0x1, -0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x10,0x11, -0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,0x20,0x21, -0x22,0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, -0xf, 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e, -0x0, 0x1, 0x1, 0xb, 0x1f,0x24,0xc, 0x1f,0x24,0x0, 0x0, 0x0, 0x47,0x0, 0xcb,0x1, -0x0, 0x0, 0x10,0xfd,0xc7,0xfb,0x7e,0xfb,0xfb,0x1, 0xbb,0xc, 0x9e,0x19,0x0, 0x21, -0x45,0x7, 0x46,0x15,0x97,0x22,0x68,0x22,0x68,0x15,0x97,0x7, 0x46,0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, -0x7, 0x8, 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x10,0x11,0x12,0x13,0x14,0x15,0x16, -0x17,0x18,0x19,0x1a,0x1b,0x1c,0x1d,0x1e,0x1f,0x20,0x21,0x22,0x23,0xca,0xf8,0x7f, -0x20,0x80,0xa, 0x7e,0x1b,0xf0,0x7a,0x2b,0xf0,0xb, 0x34,0xb, 0x54,0x69,0xff,0xff, -0xfc,0x7d,0xef,0x1b,0xe4,0x79,0xef,0xff,0xfc,0x4d,0xff,0x78,0xe6,0x7f,0x10,0xda, -0xf8,0x22,0x7d,0x43,0x7f,0x10,0x80,0x7, 0x1b,0x44,0x7a,0xb, 0xb0,0xb, 0x14,0x4d, -0x44,0x78,0xf5,0x22,0x2, 0x63,0x31,0x20,0x18,0x13,0xf, 0xd, 0xc, 0xa, 0x9, 0x8, -0x6, 0x6, 0x5, 0x4, 0x32,0x1, 0x19,0x1, 0x0, 0x2, 0xf8,0x4, 0xe7,0x5, 0xce,0x6, -0xc2,0x7, 0xb5,0x8, 0xff,0x0, 0x1, 0x2, 0x0, 0xff,0x1, 0x2, 0x0, 0x1, 0xff,0x2, -0x0, 0x1, 0x2, 0xff,0x7d,0x23,0xbe,0x24,0x0, 0x0, 0x48,0x3, 0x7d,0x32,0x22,0x6d, -0x33,0x9d,0x32,0x22,0x0, 0x2, 0x1e,0x85,0x0, 0x1, 0x0, 0x48,0x1e,0x87,0x0, 0x0, -0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x1e,0xcf,0x0, 0x0, 0x4, 0x23,0x12,0x0, -0x0, 0x0, 0x0, 0x0, 0x48,0x24,0x39,0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, -0x1, 0x32,0x5d,0x1, 0x0, 0x1, 0x16,0xc9,0x1, 0x0, 0x1, 0x1c,0x54,0x0, 0x0, 0x1, -0x35,0x40,0x0, 0x0, 0x2, 0x35,0x92,0x0, 0x0, 0x0, 0x2, 0x35,0x94,0x0, 0x0, 0x0, -0x1, 0x35,0x96,0x0, 0x0, 0x1, 0x34,0xe0,0xff,0x0, 0xa, 0x30,0x78,0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x2, 0x0, 0x1b,0x39,0x47,0x0, 0x2, 0x0, -0x1d,0x39,0x59,0x0, 0x1, 0x35,0xd6,0x0, 0x0, 0x1, 0x35,0xd7,0x0, 0x0, 0x1, 0x32, -0x5e,0x0, 0x0, 0x1, 0x36,0x3b,0x0, 0x0, 0x1, 0x36,0x3c,0x0, 0x0, 0x1, 0x36,0x3d, -0x0, 0x0, 0x1, 0x36,0x3e,0x0, 0x0, 0x1, 0x36,0x3f,0x0, 0x0, 0x2, 0x2e,0x62,0x0, -0x0, 0x0, 0x1, 0x2f,0x8a,0x0, 0x0, 0x1, 0x2f,0x8b,0x0, 0x0, 0x1, 0x33,0xf6,0x1, -0x0, 0x2, 0x33,0xf9,0x0, 0x0, 0x0, 0x2, 0x32,0xf0,0x0, 0x0, 0x0, 0x1, 0x32,0x5f, -0x0, 0x0, 0x1, 0x0, 0x6c,0x0, 0x0, 0x1, 0x0, 0x6d,0x0, 0x0, 0x1, 0x0, 0x6e,0x0, -0x0, 0x1, 0x2, 0x8e,0x0, 0x0, 0x1, 0x33,0xfd,0x1, 0x0, 0x1, 0x36,0x55,0x0, 0x0, -0x6, 0x36,0x40,0x30,0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x32,0x11,0x0, 0x0, 0x1, -0x32,0x48,0x64,0x0, 0x1, 0x32,0x49,0x64,0x0, 0x2, 0x32,0x4a,0x0, 0x0, 0x0, 0x1, -0x36,0x46,0x0, 0x0, 0x1, 0x36,0x47,0x0, 0x0, 0x1, 0x36,0x48,0x0, 0x0, 0x1, 0x36, -0x49,0x0, 0x0, 0x1, 0x36,0x4a,0x0, 0x0, 0x1, 0x36,0x4b,0x0, 0x0, 0x1, 0x32,0xf5, -0x0, 0x0, 0x2, 0x33,0x1e,0x0, 0x0, 0x0, 0x4, 0x34,0x76,0x0, 0x0, 0x0, 0x0, 0x0, -0x1, 0x30,0xaa,0x0, 0x0, 0x1, 0x30,0xb5,0x0, 0x0, 0x1, 0x30,0xb6,0x0, 0x0, 0x1, -0x30,0xb7,0x0, 0x0, 0x1, 0x30,0xc2,0x0, 0x0, 0x1, 0x31,0x95,0x0, 0x0, 0x1, 0x31, -0x96,0x0, 0x0, 0x1, 0x31,0x97,0x0, 0x0, 0x1, 0x31,0xa2,0x0, 0x0, 0x1, 0x36,0x2f, -0x0, 0x0, 0x1, 0x36,0x30,0x0, 0x0, 0x2, 0x36,0x31,0x0, 0x0, 0x0, 0x2, 0x36,0x33, -0x0, 0x0, 0x0, 0x1, 0x36,0x35,0x64,0x0, 0x1, 0x36,0x36,0x0, 0x0, 0x2, 0x36,0x37, -0x0, 0x0, 0x0, 0x1, 0x36,0x56,0x0, 0x0, 0x1, 0x3, 0xfe,0x0, 0x0, 0x1, 0x3, 0xff, -0x0, 0x0, 0x2, 0x2a,0x5e,0x2a,0x64,0x0, 0x1, 0x2e,0x24,0x2, 0x0, 0x1, 0x2e,0x4d, -0x0, 0x0, 0x1, 0x36,0x24,0x0, 0x0, 0x4, 0x36,0x51,0x0, 0x0, 0xb0,0x0, 0x0, 0x1, -0x3, 0xd7,0x1, 0x0, 0x1, 0x3, 0xd8,0x0, 0x0, 0x4, 0x3, 0xd9,0x0, 0x0, 0xbc,0x0, -0x0, 0x4, 0x3, 0xdd,0x0, 0x0, 0xb8,0xc0,0x0, 0x4, 0x3, 0xe1,0x0, 0x0, 0xb8,0x0, -0x0, 0x4, 0x3, 0xe5,0x4, 0x8, 0x10,0x6, 0x0, 0x1, 0x3, 0xe9,0x0, 0x0, 0x4, 0x3, -0xfa,0x0, 0x0, 0x80,0x0, 0x0, 0x4, 0x36,0x18,0x0, 0x0, 0x80,0x0, 0x0, 0x4, 0x36, -0x1c,0x0, 0x0, 0x90,0x0, 0x0, 0x4, 0x36,0x20,0x0, 0x0, 0xb4,0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, -0x3, 0xe8,0x0, 0xc, 0x1, 0xf4,0x3, 0x20,0x0, 0xa, 0x1, 0x4a,0x2, 0xbc,0x0, 0x9, -0x0, 0xc8,0x1, 0xf4,0x0, 0x9, 0x0, 0xa0,0x1, 0x2c,0x0, 0x8, 0x0, 0x64,0x0, 0x64, -0x0, 0x6, 0x0, 0x3c,0x0, 0x50,0x0, 0x6, 0x0, 0x0, 0x0, 0xd, 0x19,0x23,0x0, 0xc, -0x18,0x23,0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, -0x0, 0x3, 0x84,0x0, 0x64,0x2, 0x58,0x0, 0x50,0x0, 0x0, 0x0, 0x32,0x7e,0x34,0xc, -0xff,0x7e,0x24,0x0, 0xff,0x7e,0x1b,0xb0,0xbe,0xb0,0xff,0x68,0x1b,0x7e,0x34,0x8, -0x0, 0x7e,0x24,0x0, 0xff,0x6d,0x11,0x7e,0x4, 0xff,0xff,0x1b,0x1a,0x0, 0xb, 0x14, -0xb, 0x35,0xbe,0x14,0x2, 0x80,0x78,0xef,0x22,0x71,0x7d,0xd1,0x58,0x12,0x63,0x19, -0x12,0x6a,0x6d,0x12,0x53,0x95,0x71,0xcd,0x7e,0xb3,0x35,0x8, 0x24,0xfd,0x68,0x9, -0xb, 0xb1,0x78,0xf4,0x12,0x47,0x68,0x80,0xef,0xd1,0x7d,0x80,0xeb,0x12,0x41,0x4c, -0x12,0xf, 0xf5,0x91,0x8a,0x61,0xd7,0xca,0x3b,0x7c,0xfb,0x6c,0xee,0xe4,0x7a,0xb3, -0x34,0x9, 0x6c,0xdd,0x7e,0x73,0x34,0x9, 0xbe,0x70,0x4, 0x40,0x2, 0x80,0x19,0xbe, -0x70,0x0, 0x28,0x19,0x74,0x5, 0xac,0xb7,0x9, 0x65,0x17,0xce,0xbc,0x6f,0x78,0xd, -0xa, 0x37,0xbe,0x34,0x0, 0x3, 0x78,0x5, 0xe4,0x7a,0xb3,0x34,0x9, 0xe4,0x7a,0xb3, -0x1d,0xfd,0x7e,0xc3,0x34,0x9, 0x80,0x43,0x7e,0xb3,0x34,0x9, 0x4, 0x7a,0xb3,0x34, -0x9, 0x74,0x5, 0xac,0xbc,0x9, 0x75,0x17,0xce,0xbc,0x7f,0x68,0x2c,0xa, 0x2d,0x19, -0xc2,0x34,0xd, 0x74,0x5, 0xac,0xbd,0x19,0x75,0x1d,0xff,0x74,0x5, 0xac,0xbd,0x9, -0xb5,0x1d,0xff,0x7c,0x7d,0x12,0x69,0x72,0x74,0x5, 0xac,0xbd,0x59,0x35,0x1e,0x0, -0xb, 0xd0,0xb, 0xe0,0xbe,0xe0,0x3, 0x50,0x7, 0xb, 0xc0,0xbe,0xc0,0x4, 0x40,0xb8, -0xe4,0x7a,0xb3,0x1d,0xfe,0x7e,0x8, 0x1c,0xdf,0x12,0x12,0xf5,0xe4,0x7a,0xb3,0x34, -0xa, 0xda,0x3b,0x22,0x30,0xf, 0x8, 0x12,0x67,0xf, 0x12,0x65,0x22,0xc2,0xf, 0x22, -0x12,0xaf,0xab,0x74,0x1, 0x7a,0xb3,0x33,0xfd,0x22,0x91,0xae,0x91,0xb9,0x91,0x80, -0x7e,0xb3,0x1d,0x93,0x22,0x12,0x0, 0x64,0x12,0x63,0x19,0x12,0x53,0x95,0x12,0x41, -0x4c,0x12,0x0, 0x64,0x12,0xf, 0xf5,0x12,0xce,0x1c,0x91,0x8a,0x61,0xd7,0x12,0x71, -0x5, 0x12,0x71,0x13,0xf1,0xcb,0xd2,0xd, 0x22,0x12,0x70,0xbe,0xe4,0x7a,0xb3,0x36, -0x2, 0x7a,0xb3,0x36,0x1, 0x12,0x71,0x21,0xb4,0x1, 0x4, 0x74,0x1, 0x80,0x2, 0x74, -0x3, 0x7a,0xb3,0x36,0x2, 0x22,0xe5,0xc, 0x70,0x2, 0xa1,0x5c,0xe5,0xc, 0x30,0xe2, -0x35,0x53,0xc, 0xfb,0x7e,0xb3,0x1d,0x96,0x60,0x9, 0x7e,0x8, 0x1c,0xdf,0x12,0x3, -0x95,0x80,0xb, 0x7e,0xb3,0x1d,0xf1,0x7e,0x73,0x1d,0xf0,0x12,0x0, 0x24,0x7e,0x73, -0x1d,0x96,0x2e,0x70,0xff,0x92,0x4, 0x7e,0x8, 0x1c,0xdf,0x7e,0xb3,0x38,0x51,0x9e, -0xb3,0x1c,0xe9,0x12,0x15,0xb8,0xe5,0xc, 0x30,0xe3,0x32,0x53,0xc, 0xf7,0x7e,0x73, -0x35,0x73,0x7a,0x73,0x1d,0x93,0x12,0x51,0x26,0x7e,0x8, 0x1c,0xdf,0x12,0x16,0x52, -0x7e,0x73,0x35,0x74,0xbe,0x73,0x1d,0xee,0x68,0x6, 0x7a,0x73,0x1d,0xee,0xd2,0xc, -0x30,0xc, 0x6, 0x12,0x53,0x86,0x12,0x0, 0xa, 0x91,0x8e,0x71,0xd7,0xe5,0xc, 0x30, -0xe5,0xa, 0x53,0xc, 0xdf,0x7e,0xb3,0x35,0x4b,0x2, 0x4f,0xfa,0x22,0xca,0x3b,0x12, -0x71,0xac,0x50,0xfb,0x7e,0xf3,0x1d,0x93,0x7c,0xbf,0x12,0xbf,0x55,0x12,0x31,0x54, -0x12,0x30,0x7c,0x7e,0xb3,0x1d,0xa3,0xf5,0x27,0x7e,0xc3,0x1d,0xa4,0x7e,0xb3,0x35, -0x8, 0xb4,0x1, 0xe, 0x12,0x50,0xa9,0x7e,0xb3,0x16,0xbf,0x70,0x5, 0x91,0xb9,0xc3, -0xc1,0x55,0xd1,0x70,0x2d,0x32,0x3e,0x34,0xca,0x39,0x7e,0x18,0x6, 0x84,0x7e,0x8, -0x4, 0x6a,0x12,0x1f,0xed,0x1b,0xfd,0xd1,0x70,0x2d,0x32,0x3e,0x34,0xca,0x39,0x7e, -0x18,0x7, 0xc2,0x7e,0x8, 0x4, 0x0, 0x12,0x1f,0xed,0x1b,0xfd,0x7e,0xb3,0x35,0x8, -0xb4,0x3, 0x7, 0x12,0xa8,0xfe,0x7a,0x37,0x35,0x88,0x74,0x1, 0x7a,0xb3,0x16,0xbe, -0x12,0xf, 0xf5,0x12,0xa8,0xcb,0x91,0xb9,0x7e,0x8, 0x4, 0x6a,0x7a,0xd, 0x28,0x7e, -0x18,0x6, 0x12,0x7e,0xb3,0x1e,0x14,0x12,0xcb,0x1, 0x7e,0x8, 0x4, 0x0, 0x7a,0xd, -0x28,0x7e,0x18,0x5, 0xa8,0x7e,0xb3,0x16,0xc3,0x12,0xcb,0x1, 0x7e,0xd3,0x1d,0xa3, -0x7e,0xe3,0x1d,0xa4,0xe5,0x27,0x7a,0xb3,0x1d,0xa3,0x7a,0xc3,0x1d,0xa4,0x7e,0x34, -0x9, 0x14,0x7e,0x4, 0xe, 0x3c,0x7d,0x20,0x7d,0x10,0x12,0x2f,0xfc,0x7a,0xd3,0x1d, -0xa3,0x7a,0xe3,0x1d,0xa4,0x7c,0xbf,0x12,0x65,0xc7,0x12,0x31,0x73,0x7e,0xb3,0x36, -0x36,0x4, 0x7a,0xb3,0x36,0x36,0x7e,0x73,0x36,0x36,0xbe,0x70,0xfa,0x28,0x6, 0x74, -0x64,0x7a,0xb3,0x36,0x36,0x7e,0xb3,0x16,0xbe,0x60,0x9, 0x7e,0xb3,0x16,0xbf,0x60, -0x3, 0xd3,0x80,0x1, 0xc3,0xda,0x3b,0x22,0x7e,0x34,0x2, 0xcb,0xca,0x39,0x7e,0x34, -0x60,0x0, 0x7e,0x24,0x0, 0xff,0x7e,0x8, 0x38,0x0, 0x12,0x1f,0xed,0x1b,0xfd,0x22, -0x7e,0x73,0x1c,0xe6,0xa, 0x27,0x7e,0x73,0x1c,0xe5,0xa, 0x37,0x22,0x12,0x3f,0xd6, -0x7e,0xb3,0x35,0x8, 0xb4,0x3, 0x68,0x12,0xc7,0x8e,0x12,0x62,0xe3,0x12,0x38,0x32, -0x12,0x40,0x3, 0x7e,0xb3,0x35,0x41,0x30,0xe7,0xe6,0xb1,0x5d,0xd1,0x70,0x2d,0x32, -0x3e,0x34,0xca,0x39,0x7e,0x18,0x4, 0x0, 0x7e,0x8, 0x4, 0xd4,0x12,0x1f,0xed,0x1b, -0xfd,0x7e,0x73,0x1c,0xe6,0xa, 0x37,0x3e,0x34,0xca,0x39,0x7e,0x18,0x4, 0x6a,0x7e, -0x8, 0x5, 0x3e,0x12,0x1f,0xed,0x1b,0xfd,0x7e,0xb3,0x1d,0xa1,0xb4,0x1, 0x11,0x12, -0x9b,0x30,0x12,0x46,0x95,0x12,0x35,0xee,0x12,0xa1,0x48,0xf1,0xd, 0x12,0x48,0x6a, -0x12,0x4b,0xe3,0x7e,0xb3,0x35,0x41,0x54,0x7f,0x7a,0xb3,0x35,0x41,0x80,0x91,0x12, -0x71,0xb7,0xc1,0xf4,0x7e,0xb3,0x1c,0x54,0xb4,0x1, 0x6, 0xe4,0x7a,0xb3,0x1c,0x54, -0x22,0xe1,0x3, 0xe4,0x7a,0xb3,0x1d,0x84,0x7a,0xb3,0x1d,0xa2,0x22,0x12,0x6d,0x99, -0xf1,0x70,0xf1,0x70,0x12,0x4b,0xfd,0xf1,0x70,0x12,0x73,0x8a,0xf1,0x70,0x12,0xa4, -0x47,0xe1,0x23,0x7e,0x33,0x1a,0xb5,0xe4,0x7a,0xb3,0x2e,0x82,0x6c,0x22,0x80,0x3b, -0x74,0x2, 0xac,0xb2,0x9, 0x15,0x18,0x96,0x7e,0x0, 0x1, 0x6c,0x99,0x80,0x26,0xbc, -0x92,0x68,0x20,0x74,0x2, 0xac,0xb9,0x9, 0x85,0x18,0x96,0xa, 0x28,0xa, 0x31,0x12, -0x83,0xe8,0x18,0x2, 0xb, 0x0, 0xbe,0x0, 0x2, 0x40,0x8, 0x74,0x2, 0x7a,0xb3,0x2e, -0x82,0x80,0x6, 0xb, 0x90,0xbc,0x39,0x38,0xd6,0xb, 0x20,0xbc,0x32,0x38,0xc1,0x22, -0xca,0x79,0x6c,0xff,0x6c,0xee,0x80,0x47,0x7c,0xbe,0x12,0x4f,0xad,0x60,0x3e,0x7e, -0x34,0x0, 0x2, 0xca,0x39,0xac,0x7e,0x2e,0x34,0x18,0x95,0x6d,0x22,0x7e,0x30,0x2, -0xac,0x3f,0x2e,0x14,0x18,0x95,0x6d,0x0, 0x12,0x1f,0xed,0x1b,0xfd,0x7e,0x34,0x0, -0x5, 0xca,0x39,0xac,0x7e,0x2e,0x34,0x18,0xd1,0x6d,0x22,0x12,0xce,0xbc,0x12,0x1f, -0xed,0x1b,0xfd,0x7c,0xbf,0x7e,0x70,0x1, 0x12,0x28,0xdd,0xb, 0xf0,0xb, 0xe0,0x12, -0x4f,0xc3,0x38,0xb4,0x7a,0xf3,0x1a,0xb5,0xda,0x79,0x22,0x7e,0x34,0x0, 0x3, 0x6d, -0x22,0xe1,0xd3,0x7d,0x43,0x7e,0xb3,0x36,0x0, 0xbe,0xb0,0x5, 0x50,0x18,0x7e,0x70, -0x4, 0xac,0xb7,0x59,0x45,0x36,0x3, 0x59,0x25,0x36,0x5, 0x7e,0xb3,0x36,0x0, 0x4, -0x7a,0xb3,0x36,0x0, 0xc3,0x22,0xd3,0x22,0x12,0xcf,0x28,0x50,0x1c,0x7e,0xb3,0x1c, -0xdb,0x70,0x6, 0x6d,0x22,0x7a,0x27,0x36,0x33,0x7e,0x27,0x36,0x33,0xbe,0x24,0xe, -0x52,0x40,0x6, 0x74,0x1, 0x7a,0xb3,0x32,0x11,0x7e,0xb3,0x35,0x31,0xb4,0x1, 0x5, -0xe4,0x7a,0xb3,0x32,0x11,0xbe,0x34,0x55,0xf0,0x40,0x1e,0x7e,0xb3,0x32,0x11,0x70, -0x18,0x6d,0x33,0x7a,0x37,0x36,0x37,0x7a,0x37,0x36,0x33,0xe4,0x7a,0xb3,0x32,0x11, -0x7a,0xb3,0x1c,0xda,0x7a,0xb3,0x35,0x21,0x22,0x11,0x80,0x7e,0xb3,0x1a,0xd9,0x70, -0x7, 0x7e,0x34,0x3e,0x80,0xe4,0x80,0x6, 0x7e,0x34,0x3e,0x80,0x74,0x1, 0x12,0x55, -0x79,0x12,0x4f,0xd9,0x38,0xe, 0x7e,0x73,0x18,0x20,0xbe,0x70,0x0, 0x38,0x5, 0x12, -0xb3,0x83,0x28,0x9, 0x7e,0xb3,0x1c,0xdb,0x60,0x3, 0xd2,0x14,0x22,0xc2,0x14,0x22, -0xc2,0x3, 0x12,0xcf,0x28,0x50,0x52,0x7e,0xb3,0x32,0x11,0x70,0x4c,0x6c,0x33,0x80, -0x3a,0x74,0x2, 0xac,0xb3,0x9, 0x25,0x18,0x95,0x9, 0x15,0x18,0x96,0x4c,0x22,0x68, -0x20,0x7e,0x3, 0x1c,0xe1,0xa, 0x20,0x1b,0x24,0xa, 0x32,0xbd,0x23,0x68,0x12,0x4c, -0x11,0x68,0xe, 0x7e,0x3, 0x1c,0xe2,0xa, 0x20,0x1b,0x24,0xa, 0x31,0xbd,0x23,0x78, -0x8, 0x7c,0xb3,0x6c,0x77,0x11,0xdd,0xd2,0x3, 0xb, 0x30,0x7e,0x3, 0x1a,0xb5,0xbc, -0x3, 0x38,0xbe,0x30,0x3, 0x3, 0x2, 0x27,0x70,0x22,0x7e,0x70,0x1, 0x7c,0x57,0x7c, -0xab,0xc4,0x23,0x54,0x1f,0x7c,0x4b,0x7c,0xba,0x12,0x4f,0xf1,0x12,0x66,0x2d,0x4c, -0x55,0x68,0xf, 0xa, 0x34,0x2e,0x34,0x19,0xa3,0x7e,0x39,0xa0,0x4c,0xba,0x7a,0x39, -0xb0,0x22,0x64,0xff,0xa, 0x24,0x2e,0x24,0x19,0xa3,0x7e,0x29,0x70,0x5c,0x7b,0x7a, -0x29,0x70,0x22,0x6c,0x99,0x80,0x9, 0xe4,0xa, 0x39,0x19,0xb3,0x19,0xa3,0xb, 0x90, -0x7e,0xb3,0x38,0xa2,0x12,0x77,0x50,0xb, 0x24,0xa, 0x39,0xbd,0x32,0x48,0xe8,0xe4, -0x7a,0xb3,0x1a,0xb5,0x7a,0xb3,0x1a,0xb6,0x6d,0x33,0x7a,0x37,0x1a,0xb7,0x7a,0x37, -0x1a,0xb9,0x7a,0x37,0x1a,0xbb,0x7a,0x37,0x1a,0xbf,0x7e,0xd4,0x2, 0x91,0x5e,0xd4, -0xff,0xfe,0x6d,0xcc,0x7e,0x1f,0x13,0x68,0x7a,0x37,0x2, 0xd1,0x7d,0x3d,0x7a,0x37, -0x2, 0xd5,0x7e,0x34,0x15,0xcc,0x7a,0x37,0x2, 0xd3,0x7e,0x73,0x1c,0xdf,0x7a,0x73, -0x2, 0xce,0x7e,0x73,0x1c,0xe0,0x7a,0x73,0x2, 0xcd,0x7e,0x37,0x1c,0xce,0x7a,0x37, -0x2, 0xd7,0x7e,0x37,0x1c,0xd0,0x7a,0x37,0x2, 0xd9,0x7e,0x37,0x1c,0xd2,0x7a,0x37, -0x2, 0xdb,0x6d,0x33,0x9e,0x37,0x1c,0xd2,0x7a,0x37,0x2, 0xdd,0x7e,0x73,0x38,0xa2, -0x7a,0x73,0x2, 0xcf,0x7e,0x73,0x3, 0xff,0x7a,0x73,0x2, 0xd0,0x7e,0x8, 0x2, 0xcd, -0x7e,0x18,0x2, 0xdf,0x12,0x12,0x18,0x7e,0x73,0x2, 0xdf,0x7a,0x73,0x1a,0xb5,0x7e, -0x73,0x2, 0xe0,0x7a,0x73,0x1a,0xb6,0x7e,0x37,0x2, 0xe1,0x7a,0x37,0x1a,0xb7,0x7e, -0x37,0x2, 0xe3,0x7a,0x37,0x1a,0xb9,0x7e,0x37,0x2, 0xe9,0x7a,0x37,0x1a,0xbb,0x7e, -0x37,0x2, 0xeb,0x7c,0x57,0x7a,0x53,0x1a,0xbd,0xa, 0x36,0x7a,0x73,0x1a,0xbe,0x7e, -0x37,0x2, 0xe5,0x7a,0x37,0x1a,0xbf,0x7e,0x37,0x2, 0xe7,0x7c,0x57,0x7a,0x53,0x1a, -0xc1,0xa, 0x36,0x7a,0x73,0x1a,0xc2,0x6c,0x99,0x61,0x2b,0x7c,0xb9,0x11,0xda,0x74, -0x2, 0xac,0xb9,0x49,0x35,0x15,0xcc,0xa, 0x26,0x7c,0x85,0x19,0x85,0x18,0x95,0x7c, -0x87,0x19,0x85,0x18,0x96,0x7e,0x80,0x1, 0x74,0x5, 0xac,0xb9,0x19,0x85,0x18,0xd1, -0x7c,0xb9,0x12,0x4c,0xa3,0x7d,0xf3,0xe, 0xf4,0xe, 0xf4,0xe, 0xf4,0xbe,0xf4,0x0, -0x3c,0x8, 0x4, 0x7e,0xf4,0x0, 0x3c,0xf1,0xbd,0x80,0x20,0xa, 0x58,0x1b,0x54,0x71, -0x6d,0xbd,0x3f,0x8, 0xe, 0xa, 0x58,0x1b,0x54,0x71,0x5e,0xbd,0xe3,0x18,0x4, 0x1b, -0x80,0x80,0x8, 0xf1,0xe1,0x78,0x9, 0x1b,0x80,0x80,0x5, 0xbe,0x80,0x0, 0x38,0xdb, -0x74,0x5, 0xac,0xb9,0x19,0x85,0x18,0xd2,0xf1,0xbd,0x80,0x20,0xa, 0x58,0xb, 0x54, -0x71,0x6d,0xbd,0x3f,0x8, 0xe, 0xa, 0x58,0xb, 0x54,0x71,0x5e,0xbd,0xe3,0x18,0x4, -0xb, 0x80,0x80,0x8, 0xf1,0xe1,0x78,0xc, 0xb, 0x80,0x80,0x8, 0x7e,0x73,0x1c,0xe1, -0xf1,0xcf,0x48,0xd8,0x74,0x5, 0xac,0xb9,0x19,0x85,0x18,0xd3,0x74,0x2, 0xac,0xb9, -0x9, 0x85,0x18,0x96,0x80,0x26,0x71,0x81,0xa, 0x38,0x1b,0x34,0x71,0x76,0xbd,0x3f, -0x8, 0x10,0x71,0x81,0xa, 0x38,0x1b,0x34,0x71,0x7d,0xf1,0x90,0x18,0x4, 0x1b,0x80, -0x80,0xa, 0xf1,0xc6,0xbc,0x78,0x78,0x9, 0x1b,0x80,0x80,0x5, 0xbe,0x80,0x0, 0x38, -0xd5,0x74,0x5, 0xac,0xb9,0x19,0x85,0x18,0xd4,0x74,0x2, 0xac,0xb9,0x9, 0x85,0x18, -0x96,0x80,0x26,0x71,0x81,0xa, 0x38,0xb, 0x34,0x71,0x76,0xbd,0x3f,0x8, 0x10,0x71, -0x81,0xa, 0x38,0xb, 0x34,0x71,0x7d,0xf1,0x90,0x18,0x4, 0xb, 0x80,0x80,0xa, 0xf1, -0xc6,0xbc,0x78,0x78,0xc, 0xb, 0x80,0x80,0x8, 0x7e,0x73,0x1c,0xe2,0xf1,0xcf,0x48, -0xd2,0x74,0x5, 0xac,0xb9,0x19,0x85,0x18,0xd5,0xb, 0x90,0x12,0x4f,0xca,0x28,0x2, -0x41,0xb, 0x6c,0x99,0x80,0x1f,0x74,0x2, 0xac,0xb9,0x7f,0x16,0x2d,0x35,0xb, 0x1a, -0x30,0xa, 0x26,0x7c,0x85,0x19,0x85,0x19,0x67,0x7c,0x87,0x74,0x2, 0xac,0xb9,0x19, -0x85,0x19,0x68,0xb, 0x90,0x7e,0x83,0x1a,0xb6,0xbc,0x89,0x38,0xd9,0x22,0x7e,0x70, -0x2, 0xac,0x79,0x9, 0x73,0x18,0x96,0x71,0x76,0x7d,0xe3,0x7c,0xb8,0x7e,0x70,0x2, -0xac,0x79,0x9, 0x73,0x18,0x96,0x12,0xa6,0xad,0xb, 0x1a,0x30,0x22,0x71,0x76,0x7d, -0xe3,0x74,0x2, 0xac,0xb9,0x9, 0xb5,0x18,0x95,0x22,0xca,0x3b,0x6d,0xee,0x7e,0xb3, -0x1c,0xe0,0xf5,0x25,0x7e,0xc3,0x1c,0xdf,0x7e,0xb3,0x35,0x31,0xb4,0x1, 0x3, 0xe4, -0x81,0xa8,0x7e,0xb3,0x1a,0xb5,0x70,0x2, 0x81,0x2b,0x7e,0xb3,0x1c,0x48,0x60,0x2, -0x80,0x79,0x7e,0xf3,0x18,0x95,0x7e,0xa3,0x18,0x96,0x7a,0xa1,0x24,0x6c,0xdd,0x6d, -0xff,0x6c,0xee,0xa, 0x4a,0x80,0x1c,0xd1,0xf3,0x8, 0x1e,0xb, 0xd0,0xbe,0xf0,0x0, -0x28,0x7, 0x7c,0xbf,0x14,0x91,0xae,0xb, 0xe0,0xf1,0xd8,0x58,0x4, 0x91,0xab,0xb, -0xe0,0x1b,0x44,0xbe,0x44,0x0, 0x0, 0x58,0xde,0xe5,0x24,0xa, 0x4b,0x80,0x1a,0xd1, -0xf3,0x8, 0x24,0xb, 0xd0,0xbe,0xf0,0x0, 0x28,0x7, 0x7c,0xbf,0x14,0x91,0xae,0xb, -0xe0,0xf1,0xd8,0x58,0x4, 0x91,0xab,0xb, 0xe0,0x7d,0x34,0xb, 0x34,0x7d,0x43,0xe5, -0x25,0xa, 0x5b,0xbd,0x35,0x48,0xd8,0xbe,0xd0,0x3, 0x50,0x2, 0x80,0xd, 0xa, 0x2e, -0x7d,0x3f,0x12,0x1d,0x4a,0xbe,0x34,0x0, 0x28,0x8, 0x7, 0xe4,0x7a,0xb3,0x2f,0x8a, -0x80,0x76,0x6d,0xdd,0xbe,0xf0,0x0, 0x28,0x7, 0x7c,0xbf,0x14,0xd1,0xdb,0x7d,0xd3, -0xa, 0xcc,0x1b,0xc4,0xa, 0x5f,0xbd,0x5c,0x58,0x7, 0x7c,0xbf,0x4, 0xd1,0xdb,0x2d, -0xd3,0x7e,0x70,0x8, 0x80,0x1b,0x7e,0x50,0x2, 0xac,0x57,0x7d,0x52,0x2e,0x54,0x20, -0x34,0xf1,0xec,0xbd,0x5d,0x8, 0xa, 0x7d,0x52,0x2e,0x54,0x20,0x35,0xf1,0xec,0x2d, -0xe5,0x7c,0x67,0x1b,0x70,0xa5,0xbe,0x0, 0xdd,0x7c,0xbf,0xd1,0xdb,0x12,0x20,0x54, -0xbe,0x34,0xa, 0xf0,0x8, 0x4, 0x2e,0xe4,0x0, 0x28,0xbe,0xe4,0x0, 0xfa,0x28,0x4, -0x7e,0xe4,0x0, 0xfa,0x7e,0x73,0x2f,0x8a,0xa, 0x57,0xbd,0x5e,0x50,0x6, 0x7d,0x3e, -0x7a,0x73,0x2f,0x8a,0x7e,0xb3,0x2f,0x8a,0xda,0x3b,0x22,0x7c,0xbf,0x4, 0x7c,0x79, -0x71,0x76,0x2d,0xf3,0x22,0xca,0x3b,0x7f,0x70,0x7d,0x42,0x7c,0xd6,0x7c,0xf7,0x7c, -0xeb,0x7e,0xb3,0x38,0x50,0xf5,0x2d,0x7c,0xcf,0x80,0xc, 0x7c,0xbc,0xd1,0xec,0x48, -0x4, 0x7c,0xfc,0x80,0x6, 0xb, 0xc0,0xbc,0xdc,0x58,0xf0,0xa, 0x6f,0x1b,0x64,0x7c, -0xcd,0x80,0x8, 0x7c,0xbc,0xd1,0xec,0x48,0x7, 0x1b,0xc0,0xbe,0xc0,0x0, 0x58,0xf3, -0xbe,0xc0,0x0, 0x58,0x2, 0x6c,0xcc,0x7a,0x7b,0xc0,0xa, 0x6f,0xb, 0x64,0x7c,0xcd, -0x80,0x8, 0x7c,0xbc,0xd1,0xec,0x48,0x8, 0xb, 0xc0,0xe5,0x2d,0xbc,0xbc,0x18,0xf2, -0xe5,0x2d,0xbc,0xbc,0x18,0x8, 0xe5,0x2d,0xa, 0x6b,0x1b,0x64,0x7c,0xcd,0x7e,0x1d, -0x29,0x7a,0x1b,0xc0,0x7e,0x7b,0x70,0xa, 0x47,0x7e,0x1d,0x29,0x7e,0x1b,0x70,0xa, -0x57,0x9d,0x54,0xb, 0x54,0xda,0x3b,0x22,0xca,0x3b,0x7f,0x60,0x7e,0xb3,0x1a,0xb5, -0xf5,0x24,0x6c,0xee,0x7e,0xd0,0x1, 0x80,0x1a,0xa, 0x3e,0x2d,0x3d,0x7d,0x2c,0x7e, -0x1b,0x60,0xa, 0x2d,0x7f,0x6, 0x2d,0x12,0x7e,0xb, 0x70,0xbc,0x76,0x40,0x2, 0x7c, -0xed,0xb, 0xd0,0xe5,0x24,0xbc,0xbd,0x38,0xe0,0xa, 0x3e,0x2d,0x3d,0x7d,0x2c,0x7e, -0x1b,0xe0,0x6c,0xff,0x7e,0xd0,0x1, 0xc1,0xd0,0x75,0x25,0x0, 0x6d,0x33,0x7a,0x35, -0x26,0x7a,0x35,0x28,0x9f,0x44,0x7f,0x54,0xe4,0x7a,0xb3,0x2, 0xcb,0x74,0xff,0x7a, -0xb3,0x2, 0xcc,0xe4,0x7a,0xb3,0x2, 0xcd,0x74,0xff,0x7a,0xb3,0x2, 0xce,0xe4,0x7a, -0xb3,0x2, 0xcf,0x6c,0xcc,0xc1,0x46,0x74,0x2, 0xac,0xbc,0x9, 0x95,0x18,0x95,0x9, -0x85,0x18,0x96,0xa, 0x5c,0x7f,0x16,0x2d,0x35,0x7e,0x1b,0x70,0xbc,0x7d,0x68,0x2, -0xc1,0x44,0x5, 0x25,0x7c,0xb9,0x7c,0x78,0x71,0x76,0x7d,0x53,0x2e,0x55,0x26,0x7a, -0x55,0x26,0xd1,0xfe,0xa, 0x39,0x6d,0x22,0x12,0x1d,0x7c,0x2f,0x51,0xd1,0xfe,0xa, -0x38,0x6d,0x22,0x12,0x1d,0x7c,0x2f,0x41,0x7c,0xb9,0x7c,0x78,0x71,0x76,0xbe,0x35, -0x28,0x8, 0x9, 0x7c,0xb9,0x7c,0x78,0x71,0x76,0x7a,0x35,0x28,0x74,0x5, 0xac,0xbc, -0x9, 0x75,0x18,0xd1,0x2e,0x73,0x2, 0xcb,0x7a,0x73,0x2, 0xcb,0x9, 0x75,0x18,0xd2, -0xbe,0x73,0x2, 0xcc,0x50,0x4, 0x7a,0x73,0x2, 0xcc,0x9, 0x75,0x18,0xd3,0xbe,0x73, -0x2, 0xcd,0x28,0x4, 0x7a,0x73,0x2, 0xcd,0x9, 0x75,0x18,0xd4,0xbe,0x73,0x2, 0xce, -0x50,0x4, 0x7a,0x73,0x2, 0xce,0x9, 0x75,0x18,0xd5,0xbe,0x73,0x2, 0xcf,0x28,0x4, -0x7a,0x73,0x2, 0xcf,0xb, 0xc0,0xe5,0x24,0xbc,0xbc,0x28,0x2, 0xa1,0xa7,0xe5,0x25, -0xbe,0xb0,0x0, 0x28,0x79,0x7e,0xf5,0x26,0x12,0x83,0xd5,0x7e,0x8, 0x0, 0x2, 0x12, -0x1d,0xe9,0x2f,0x51,0x2f,0x41,0xf1,0xb6,0x7f,0x15,0x12,0x1d,0xe9,0x7f,0x51,0xf1, -0xb6,0x7f,0x14,0x12,0x1d,0xe9,0x7f,0x41,0x7d,0x3b,0x74,0x2, 0xac,0xbf,0x19,0x75, -0x33,0x40,0x7d,0x39,0x74,0x2, 0xac,0xbf,0x19,0x75,0x33,0x41,0x7e,0x34,0x0, 0x5, -0xca,0x39,0x12,0xce,0xbc,0x6d,0x0, 0x7e,0x18,0x2, 0xcb,0x12,0x1f,0xed,0x1b,0xfd, -0x7e,0x37,0x1a,0xbb,0xbe,0x35,0x28,0x78,0xc, 0x7d,0x3b,0x7a,0x73,0x1a,0xbd,0x7d, -0x39,0x7a,0x73,0x1a,0xbe,0x7e,0x37,0x33,0x1e,0x4d,0x33,0x68,0xf, 0x7e,0x25,0x28, -0x7e,0x70,0x2, 0xac,0x7f,0x2e,0x37,0x33,0x1e,0x1b,0x38,0x20,0xb, 0xf0,0xb, 0xd0, -0xbc,0xed,0x40,0x2, 0xa1,0x79,0x7c,0xbf,0xda,0x3b,0x22,0x7e,0x71,0x24,0x61,0x76, -0xa, 0x5d,0x1b,0x54,0x7c,0x7e,0x71,0x76,0x7d,0x43,0x7c,0xbd,0x7c,0x7e,0x71,0x76, -0xbd,0x34,0x22,0x7c,0xbf,0x7c,0x79,0x71,0x76,0xbe,0x34,0x0, 0x96,0x22,0x7c,0xb9, -0x7c,0x78,0x71,0x76,0x7d,0x13,0x1a,0x2, 0x1a,0x0, 0x22,0xca,0x3b,0x7c,0x3b,0x6c, -0xff,0x7e,0xc7,0x1a,0xbb,0x7e,0xd4,0x0, 0x5, 0xad,0xdc,0xe, 0xd4,0xe, 0xd4,0xe, -0xd4,0x74,0x2, 0xac,0xb3,0x9, 0x65,0x18,0x95,0x9, 0xe5,0x18,0x96,0x7a,0xe1,0x24, -0x7e,0xb3,0x36,0x3b,0x60,0x1c,0x7e,0xd4,0x0, 0xc8,0xbe,0x60,0x2, 0x48,0x10,0x7e, -0x73,0x1c,0xe1,0xa, 0x27,0x9e,0x24,0x0, 0x3, 0x1a,0xc6,0xbd,0xc2,0x8, 0x3, 0xe4, -0x80,0x3b,0x7e,0x8, 0x0, 0x25,0x7a,0xd, 0x29,0x7c,0xbe,0x7c,0x76,0x7d,0x2d,0x7e, -0x8, 0x0, 0x26,0x91,0xb5,0x85,0x26,0x27,0x7e,0xc1,0x25,0x1b,0xe0,0xbe,0xe0,0x0, -0x48,0x4, 0xf1,0x97,0x38,0xf5,0x7e,0xe1,0x24,0x85,0x27,0x26,0x7a,0xc1,0x25,0xb, -0xe0,0xe5,0x28,0xbc,0xbe,0x8, 0x4, 0xf1,0x97,0x38,0xf4,0x7c,0xbf,0xda,0x3b,0x22, -0x7c,0x78,0x71,0x76,0xbd,0xe3,0x22,0x7e,0x18,0x0, 0x25,0x7a,0x1d,0x29,0x7c,0xbe, -0x7e,0x71,0x26,0x7e,0x61,0x25,0x7d,0x2d,0x7e,0x8, 0x0, 0x26,0x91,0xb5,0x7c,0xdb, -0x2c,0xfd,0xbe,0xd0,0x3, 0x22,0x7d,0x1f,0x1a,0x2, 0x1a,0x0, 0x22,0x74,0x2, 0xac, -0xb9,0x9, 0x85,0x18,0x95,0x22,0x74,0x2, 0xac,0xb9,0x9, 0x75,0x18,0x96,0x22,0xa, -0xe7,0x1b,0xe4,0xa, 0x58,0xbd,0x5e,0x22,0xa, 0x3c,0x1b,0x34,0xa, 0x5f,0xbd,0x53, -0x22,0x74,0x2, 0xac,0xb9,0x9, 0x75,0x18,0x95,0xbc,0x78,0x22,0x7a,0xb1,0x82,0x7a, -0xa1,0x83,0xe4,0x93,0x1a,0x5b,0x22,0x7e,0x71,0x27,0x61,0x76,0x7e,0xb3,0x1c,0xdf, -0xca,0xf8,0x7c,0xfb,0x7d,0xe0,0x7d,0xf1,0x7d,0xd2,0x7d,0xc3,0x7a,0xf3,0x2, 0x8f, -0x7e,0x73,0x1c,0xe2,0x7a,0x73,0x2, 0x90,0xe4,0x7a,0xb3,0x2, 0x92,0x74,0x6, 0x7a, -0xb3,0x2, 0x91,0x7a,0xf7,0x2, 0x93,0x7a,0xf7,0x2, 0x97,0x7e,0x8, 0x2, 0x8f,0x7e, -0x73,0x1d,0xa3,0xa, 0x37,0x12,0x18,0xcb,0x7a,0xe7,0x2, 0x97,0xe4,0x7a,0xb3,0x2, -0x91,0x31,0x20,0x7a,0xf3,0x2, 0x8f,0x7e,0xb3,0x1d,0xa1,0x70,0xf, 0xe4,0x7a,0xb3, -0x2, 0x92,0x7a,0xf7,0x2, 0x93,0x7e,0x34,0x0, 0x20,0x80,0x10,0x74,0x1, 0x7a,0xb3, -0x2, 0x92,0x7a,0xc7,0x2, 0x93,0x7a,0xd7,0x2, 0x95,0x6d,0x33,0x7a,0x37,0x2, 0x99, -0x11,0x75,0xda,0xf8,0x22,0x7e,0x8, 0x2, 0x8f,0x2, 0x18,0x0, 0xca,0x79,0x7e,0xe3, -0x1c,0xe0,0x7e,0x73,0x34,0xa, 0x4c,0x77,0x78,0x2, 0x21,0x1d,0x7e,0xa4,0x2, 0x9d, -0x1e,0xa4,0x3e,0xa4,0x7a,0x73,0x2, 0x8f,0x31,0x20,0x7d,0xba,0x7a,0xb7,0x2, 0x97, -0x31,0x4a,0x7e,0x73,0x38,0x99,0x12,0xce,0x9c,0xa, 0x3e,0xad,0x32,0x7d,0xb3,0x3e, -0xb4,0x7e,0x1f,0x3, 0xfa,0x2d,0x3b,0x7d,0xb3,0x7a,0xb7,0x2, 0x93,0x7e,0xb4,0x0, -0x20,0x7a,0xb7,0x2, 0x99,0x11,0x75,0x6c,0xff,0x80,0x19,0x7c,0x3f,0xac,0x3e,0x3e, -0x14,0x2d,0x1a,0x6d,0x0, 0x7c,0xbe,0x12,0xaf,0xd7,0x74,0x2, 0xac,0xbf,0x59,0x35, -0x3, 0x63,0xb, 0xf0,0x7e,0x73,0x34,0xa, 0xbc,0x7f,0x38,0xdf,0x6c,0xff,0x80,0x25, -0xbe,0xf0,0x4, 0x50,0x28,0xa, 0x3f,0x9, 0x63,0x34,0xd, 0xbe,0x60,0x4, 0x50,0x13, -0x74,0x2, 0xac,0xbf,0x49,0x45,0x3, 0x63,0x7e,0x70,0xc, 0x7c,0xb6,0xac,0xb7,0x59, -0x45,0x34,0x19,0xb, 0xf0,0x7e,0x73,0x34,0xa, 0xbc,0x7f,0x38,0xd3,0xda,0x79,0x22, -0x7e,0x73,0x1c,0xe0,0x7a,0x73,0x2, 0x90,0x22,0x7c,0x5b,0x7d,0x13,0x7a,0x53,0x2, -0x8f,0x31,0x20,0x7a,0x17,0x2, 0x97,0x31,0x4a,0x7e,0x34,0x80,0x0, 0x7a,0x37,0x2, -0x93,0x31,0xa4,0x7e,0x8, 0x2, 0x8f,0x2, 0x18,0x0, 0xe4,0x7a,0xb3,0x2, 0x91,0x7a, -0xb3,0x2, 0x92,0x22,0xa9,0xd1,0xcb,0x74,0x1, 0x12,0x0, 0xe, 0x7e,0x34,0xe, 0x3c, -0x7e,0xb3,0x1c,0xdf,0x31,0x29,0xb1,0xb6,0x7a,0x37,0x3, 0xf6,0x74,0x1, 0x7a,0xb3, -0x16,0xbf,0x22,0x7e,0xb3,0x1d,0xa1,0xb4,0x1, 0x29,0x12,0xca,0xfa,0x7e,0x1f,0x3, -0xfa,0x7a,0x37,0x2, 0x97,0x7e,0x34,0xe, 0x3c,0x7a,0x37,0x2, 0x93,0x71,0xef,0x31, -0x20,0xe4,0x7a,0xb3,0x2, 0x92,0x31,0xa4,0x7a,0xb3,0x2, 0x91,0x7e,0x8, 0x2, 0x8f, -0x2, 0x18,0x0, 0x22,0x7e,0x34,0x0, 0x20,0x7a,0x37,0x2, 0x99,0x22,0x7e,0x8, 0x2, -0x8f,0x12,0xcf,0x5, 0x31,0x20,0x71,0xef,0xa9,0xd1,0xcb,0x12,0xcf,0x8d,0x7a,0x37, -0x2, 0x93,0x7e,0x1f,0x3, 0xfa,0x7a,0x37,0x2, 0x95,0x7e,0x1f,0x13,0x64,0x7a,0x37, -0x2, 0x97,0x6d,0x33,0x7a,0x37,0x2, 0x99,0x7e,0x8, 0x2, 0x8f,0x2, 0x18,0x0, 0x12, -0xac,0xdb,0x31,0xad,0x2, 0x0, 0x46,0x7c,0x1b,0xa5,0xb9,0xf, 0x5, 0x7e,0xb3,0x24, -0x38,0x22,0xbe,0x10,0x34,0x38,0x2, 0x41,0xe9,0xa5,0xb9,0x35,0x5, 0x7e,0xb3,0x1d, -0x94,0x22,0xbe,0x10,0x36,0x68,0x4, 0xa5,0xb9,0x37,0x19,0x7e,0x15,0x8, 0x7d,0x31, -0xb, 0x34,0x7a,0x35,0x8, 0x2e,0x17,0x23,0x10,0x7e,0x19,0xb0,0xa5,0xb9,0x37,0x3, -0x75,0x63,0x36,0x22,0xbe,0x10,0x38,0x68,0x4, 0xa5,0xb9,0x39,0x19,0x7e,0x3, 0x35, -0x65,0x7c,0xb0,0x4, 0x7a,0xb3,0x35,0x65,0xa5,0xb9,0x39,0x3, 0x75,0x63,0x38,0xa, -0x30,0x9, 0xb3,0x1d,0xa5,0x22,0xbe,0x10,0x3a,0x68,0x4, 0xa5,0xb9,0x3b,0x19,0x7e, -0x3, 0x35,0x67,0x7c,0xb0,0x4, 0x7a,0xb3,0x35,0x67,0xa5,0xb9,0x3b,0x3, 0x75,0x63, -0x3a,0xa, 0x30,0x9, 0xb3,0x1d,0xc8,0x22,0xa5,0xb9,0xfb,0x5, 0x7e,0xb3,0x1d,0x96, -0x22,0xa5,0xb9,0x5e,0x26,0x7e,0x7f,0x3, 0xd9,0x69,0x17,0x0, 0xa8,0xa, 0x32,0x12, -0xb4,0x56,0x7c,0x17,0x5e,0x10,0x1, 0x7c,0xb1,0x3, 0x3, 0x54,0xc0,0x7c,0x1b,0xa, -0x52,0x54,0x3, 0x4c,0x1b,0x4e,0x10,0x80,0x7c,0xb1,0x22,0xbe,0x10,0x3c,0x68,0x4, -0xa5,0xb9,0x3d,0x19,0x7e,0x3, 0x35,0x69,0x7c,0xb0,0x4, 0x7a,0xb3,0x35,0x69,0xa5, -0xb9,0x3d,0x3, 0x75,0x63,0x3c,0xa, 0x30,0x9, 0xb3,0x1c,0xec,0x22,0xbe,0x10,0x3e, -0x68,0x4, 0xa5,0xb9,0x3f,0x19,0x7e,0x3, 0x35,0x6b,0x7c,0xb0,0x4, 0x7a,0xb3,0x35, -0x6b,0xa5,0xb9,0x3f,0x3, 0x75,0x63,0x3e,0xa, 0x30,0x9, 0xb3,0x1d,0xf, 0x22,0xbe, -0x10,0x40,0x40,0xc, 0xbe,0x10,0x4d,0x38,0x7, 0xa, 0x31,0x9, 0xb3,0x35,0x41,0x22, -0xbe,0x10,0x4e,0x68,0x4, 0xa5,0xb9,0x4f,0x1c,0x7e,0x3, 0x35,0x86,0x7c,0xb0,0x4, -0x7a,0xb3,0x35,0x86,0xa5,0xb9,0x4f,0x3, 0x75,0x63,0x4e,0xa, 0x30,0x2e,0x37,0x22, -0xae,0x7e,0x39,0xb0,0x22,0xbe,0x10,0x51,0x68,0x4, 0xa5,0xb9,0x52,0x1e,0x7e,0x34, -0x38,0x0, 0x7e,0xb3,0x35,0x91,0xa, 0x1b,0x2d,0x13,0x7e,0x19,0xa0,0x4, 0x7a,0xb3, -0x35,0x91,0xa5,0xb9,0x52,0x3, 0x75,0x63,0x51,0x7c,0xba,0x22,0xbe,0x10,0x60,0x40, -0xc, 0xbe,0x10,0x6c,0x38,0x7, 0xa, 0x31,0x9, 0xb3,0x31,0xf0,0x22,0xa5,0xb9,0x5b, -0x3, 0xe5,0xe, 0x22,0xa5,0xb9,0x5a,0x5, 0x7e,0x57,0x1e,0x85,0x22,0xbe,0x10,0x58, -0x68,0x4, 0xa5,0xb9,0x59,0x20,0xa5,0xb9,0x59,0x5, 0x75,0x63,0x58,0x80,0x5, 0xe4, -0x7a,0xb3,0x1e,0xcf,0x7e,0x13,0x1e,0xcf,0x7c,0xb1,0x4, 0x7a,0xb3,0x1e,0xcf,0xa, -0x31,0x9, 0xb3,0x1e,0x87,0x22,0xbe,0x10,0xf4,0x68,0x4, 0xa5,0xb9,0xf5,0x16,0x7e, -0x15,0xa, 0x7d,0x31,0xb, 0x34,0x7a,0x35,0xa, 0x9, 0xb1,0x23,0x16,0xa5,0xb9,0xf5, -0x3, 0x75,0x63,0xf4,0x22,0xbe,0x10,0xf0,0x68,0x4, 0xa5,0xb9,0xf1,0x6, 0x2e,0x10, -0x20,0xa5,0xe7,0x22,0xbe,0x10,0xf2,0x68,0x4, 0xa5,0xb9,0xf3,0x16,0x7e,0x15,0x10, -0x3e,0x14,0x7e,0x1f,0x23,0x12,0x2d,0x31,0xb, 0x1a,0x50,0xa5,0xb9,0xf2,0x3, 0xa, -0x5a,0x22,0x22,0xa5,0xb9,0xf6,0x3, 0xe5,0xf, 0x22,0xa5,0xb9,0xf7,0x3, 0x74,0x50, -0x22,0xa5,0xb9,0xfd,0x2, 0xe4,0x22,0xa5,0xb9,0xff,0x2, 0xe4,0x22,0xe4,0x22,0x7e, -0x73,0x1c,0xdf,0x7a,0x73,0x2, 0x8f,0x22,0x7c,0xab,0x6c,0x77,0xb1,0xae,0x78,0x9, -0x7c,0xba,0x12,0x6f,0xd4,0x7c,0x7b,0x80,0x9, 0xb4,0x4, 0x6, 0x7c,0xba,0x31,0xe7, -0x7c,0x7b,0x7c,0xb7,0x22,0x30,0x90,0x1b,0xc2,0x90,0xe5,0x61,0x70,0x9, 0x75,0x61, -0x1, 0xe5,0x91,0xf5,0x63,0x80,0x13,0x7e,0x71,0x91,0xe5,0x63,0x91,0x41,0x5, 0x63, -0x75,0x61,0x2, 0x30,0x91,0xa, 0xc2,0x91,0x5, 0x63,0xe5,0x63,0x71,0xf8,0xf5,0x91, -0x22,0x7c,0xa7,0x7c,0x7b,0xb1,0xae,0x78,0x7, 0x7c,0xb7,0x7c,0x7a,0x2, 0x6d,0x2c, -0xb4,0x4, 0x6, 0x7c,0xb7,0x7c,0x7a,0x81,0x5a,0x22,0x7c,0xa7,0x7c,0xb, 0xa5,0xb8, -0x0, 0x8, 0x7c,0xba,0x12,0x6c,0xfd,0xd2,0x6, 0x22,0xa5,0xb8,0x1, 0x3f,0x7a,0xa3, -0x35,0x42,0xbe,0xa0,0xad,0x78,0x2, 0x80,0x30,0xbe,0xa0,0xae,0x78,0x3, 0xd2,0x7, -0x22,0xbe,0xa0,0xaa,0x78,0x5, 0x12,0xcf,0x5d,0x80,0x1e,0xbe,0xa0,0xab,0x78,0xa, -0x7e,0x34,0x5, 0x3e,0x7a,0x37,0x23,0x10,0x80,0xf, 0xbe,0xa0,0xac,0x68,0x2, 0xa1, -0xa6,0x7e,0x34,0x4, 0xd4,0x7a,0x37,0x23,0x10,0x6d,0x33,0xa1,0x2e,0xbe,0x0, 0x4, -0x40,0x1e,0xbe,0x0, 0x8, 0x38,0x19,0xd2,0x6, 0xb1,0xa7,0xa5,0xb8,0x7, 0x6, 0x6d, -0x33,0x7a,0x35,0xa, 0x22,0xa5,0xb8,0x8, 0x2, 0x80,0x2, 0xa1,0xa6,0x2, 0x38,0x1e, -0xa5,0xb8,0xa, 0x8, 0x43,0xc, 0x20,0x7a,0xa3,0x35,0x4b,0x22,0xa5,0xb8,0xb, 0x7, -0xd2,0x6, 0xb1,0xa7,0x2, 0x38,0x28,0xa5,0xb8,0xf, 0x2, 0x80,0x26,0xbe,0x0, 0x1b, -0x40,0x7, 0xbe,0x0, 0x1c,0x38,0x2, 0x80,0x1a,0xbe,0x0, 0x1e,0x40,0xb, 0xbe,0x0, -0x23,0x38,0x6, 0xb1,0xa7,0x43,0xc, 0x40,0x22,0xbe,0x0, 0x24,0x40,0x7, 0xbe,0x0, -0x2c,0x38,0x2, 0xa1,0xa7,0xa5,0xb8,0x2d,0x19,0xb1,0xa7,0x20,0x7, 0x2, 0xa1,0xa6, -0x7e,0xb3,0x35,0x6d,0x7c,0x4b,0x6c,0x55,0xa, 0x3a,0x2d,0x32,0x3e,0x34,0x7a,0x35, -0x8, 0x22,0xa5,0xb8,0x44,0x4, 0xb1,0xa7,0xc1,0x5e,0xa5,0xb8,0x5b,0x4, 0x7a,0xa1, -0xe, 0x22,0xbe,0x0, 0x58,0x68,0x4, 0xa5,0xb8,0x59,0x20,0xa5,0xb8,0x59,0x5, 0x75, -0x63,0x58,0x80,0x5, 0xe4,0x7a,0xb3,0x1e,0xcf,0x7e,0x73,0x1e,0xcf,0x7c,0xb7,0x4, -0x7a,0xb3,0x1e,0xcf,0xa, 0x37,0x19,0xa3,0x1e,0x87,0x22,0xa5,0xb8,0x5a,0x7, 0xa, -0x3a,0x7a,0x37,0x1e,0x85,0x22,0xbe,0x0, 0xf0,0x40,0x24,0xbe,0x0, 0xf3,0x38,0x1f, -0x7c,0x10,0x2e,0x10,0x20,0x7c,0xba,0xa5,0xf7,0xa5,0xb8,0xf3,0x19,0x7e,0x15,0x12, -0x7e,0x5, 0x10,0x3e,0x4, 0x7e,0x1f,0x23,0x12,0x2d,0x30,0x1b,0x1a,0x10,0x22,0xa5, -0xb8,0xf6,0x3, 0x7a,0xa1,0xf, 0x22,0xa, 0x30,0x19,0xa3,0x35,0x41,0x22,0x7e,0xb3, -0x35,0x41,0xc4,0x54,0x7, 0x22,0x6d,0x33,0x7e,0x53,0x38,0x99,0xbe,0x50,0x0, 0x28, -0x5, 0x12,0xca,0x9, 0x80,0xc, 0x7e,0x53,0x38,0x9a,0xbe,0x50,0x0, 0x28,0x3, 0x12, -0xc9,0x75,0x6d,0x22,0x7e,0x33,0x1d,0xa3,0xa, 0x13,0x6d,0x0, 0x12,0x1d,0x7c,0x74, -0x6, 0x1e,0x34,0x1e,0x24,0x50,0x3, 0x4e,0x60,0x80,0x14,0x78,0xf4,0x22,0x12,0x4c, -0xb4,0x12,0xa9,0xc0,0xd1,0x2e,0x7e,0xb3,0x35,0x6, 0xb4,0x1, 0xc, 0x7e,0x34,0x0, -0x5, 0x7a,0x37,0x1a,0xd2,0x7a,0x37,0x1a,0xd4,0x7e,0xb3,0x32,0x5e,0x60,0x7, 0x14, -0x7a,0xb3,0x32,0x5e,0x80,0x6, 0x7e,0xb3,0x1a,0xdd,0x60,0x5, 0x31,0xdf,0x12,0xbf, -0x2c,0x7e,0xb3,0x1a,0xde,0x60,0x6, 0x12,0xcb,0x51,0x2, 0xca,0xa5,0x22,0x12,0xb3, -0x94,0x60,0x14,0xd1,0x57,0x7e,0x37,0x1a,0xd2,0x3e,0x34,0x7a,0x37,0x1a,0xd2,0x7e, -0x37,0x1a,0xd4,0x3e,0x34,0x80,0xb, 0x12,0xb2,0xd9,0xe4,0x33,0xb4,0x1, 0x7, 0x12, -0xcf,0x31,0x7a,0x37,0x1a,0xd4,0x22,0x74,0x1, 0x7a,0xb3,0x1a,0xde,0x22,0x7e,0xb3, -0x35,0x85,0xb4,0x1, 0x20,0x7e,0x34,0x0, 0x4, 0xca,0x39,0x7e,0x18,0x16,0xc1,0x7e, -0x8, 0x35,0x81,0x12,0x1f,0xed,0x1b,0xfd,0x12,0xcf,0x54,0x7e,0x1f,0x16,0xc5,0x7e, -0xf, 0x16,0xc1,0x80,0x23,0x7e,0x34,0x0, 0x4, 0xca,0x39,0x7e,0x18,0x1e,0x12,0x7e, -0x8, 0x35,0x81,0x12,0x1f,0xed,0x1b,0xfd,0x7e,0x37,0x1e,0x18,0x7a,0x37,0x22,0xae, -0x7e,0x1f,0x1e,0x16,0x7e,0xf, 0x1e,0x12,0xc1,0xaa,0x7a,0x1f,0x1d,0x7e,0x7a,0xf, -0x1d,0x7a,0x22,0x7c,0x7b,0x7a,0x73,0x1d,0x82,0xa5,0xbf,0x0, 0x18,0x7e,0x1f,0x1e, -0x16,0x7e,0xf, 0x1e,0x12,0xd1,0xaa,0x7e,0x18,0x6, 0x12,0x7a,0x1f,0x6, 0x7c,0x7e, -0x18,0x4, 0x6a,0x80,0x11,0xa5,0xbf,0x1, 0x11,0x7e,0x1f,0x16,0xc5,0x7e,0xf, 0x16, -0xc1,0xd1,0xaa,0x12,0xce,0x78,0x7a,0x1f,0x6, 0x80,0x22,0x74,0x1, 0x12,0x0, 0x6, -0xe4,0xd1,0xb3,0xd1,0xff,0xe4,0x12,0x0, 0x6, 0x74,0x1, 0xd1,0xb3,0xc1,0xff,0xca, -0x3b,0x7e,0xb3,0x1c,0xe5,0xf5,0x26,0x7e,0xf3,0x1c,0xe6,0x7e,0x8, 0x2, 0x9f,0x7e, -0x34,0x0, 0x90,0x74,0x3f,0x12,0x20,0x12,0x7e,0x8, 0x3, 0x2f,0x7e,0x34,0x0, 0x48, -0x12,0x20,0x12,0x7e,0x8, 0x3, 0x77,0x12,0xcf,0x5, 0x7e,0x8, 0x3, 0x83,0x7e,0x34, -0x0, 0xc, 0x12,0x20,0x12,0x7e,0xb3,0x1d,0x7e,0xf5,0x25,0x12,0xcf,0x6d,0x7e,0x18, -0x3, 0x77,0x12,0xce,0x85,0x12,0xc8,0xc6,0x6c,0xcc,0x80,0x26,0x7a,0xc1,0x24,0xa, -0x3c,0x9, 0xe3,0x1d,0x56,0xa, 0x3e,0x12,0x66,0x29,0x7c,0xeb,0xbe,0xe0,0x24,0x50, -0xf, 0xa, 0xe, 0x12,0xce,0x43,0xa, 0x3e,0x8d,0x32,0x12,0x44,0x68,0x12,0xce,0x91, -0xb, 0xc0,0xbc,0xfc,0x38,0xd6,0x6c,0xcc,0x80,0x25,0xa, 0x4c,0xa, 0x5f,0x2d,0x54, -0xf5,0x24,0xa, 0x3c,0x9, 0xe3,0x1d,0x33,0xbe,0xe0,0x23,0x50,0x10,0xa, 0x5e,0x12, -0xce,0x36,0xa, 0x2e,0x12,0xce,0xfc,0x12,0x44,0x68,0x12,0xce,0x91,0xb, 0xc0,0xe5, -0x26,0xbc,0xbc,0x38,0xd5,0x7e,0xb3,0x1d,0x7f,0x60,0xf, 0x12,0xcf,0x6d,0x7e,0x18, -0x3, 0x8f,0x12,0xce,0x85,0x12,0xc8,0x11,0x80,0xc, 0x7e,0x8, 0x3, 0x8f,0x7e,0x34, -0x0, 0x48,0xe4,0x12,0x20,0x12,0x6c,0xcc,0x7e,0x70,0xc, 0xac,0x7c,0x2e,0x34,0x3, -0x8f,0x6d,0x22,0x7a,0x1f,0x2, 0x8f,0x74,0x2, 0xac,0xbc,0x49,0x35,0x3, 0x77,0x7a, -0x37,0x2, 0x93,0x74,0x2, 0xac,0xbc,0x49,0x35,0x3, 0x83,0x7a,0x37,0x2, 0x95,0x7e, -0x70,0x18,0xac,0x7c,0x2e,0x34,0x2, 0x9f,0x7a,0x1f,0x2, 0x97,0x7e,0x70,0xc, 0xac, -0x7c,0x2e,0x34,0x3, 0x2f,0x7a,0x1f,0x2, 0x9b,0x7e,0x8, 0x2, 0x8f,0xe5,0x25,0x7c, -0x7c,0x12,0x5, 0x42,0xb, 0xc0,0xbe,0xc0,0x6, 0x40,0xad,0xda,0x3b,0x22,0x20,0x86, -0x3, 0xd3,0x80,0x1, 0xc3,0x92,0x86,0x22,0x20,0x82,0x3, 0xd3,0x80,0x1, 0xc3,0x92, -0x82,0x22,0x30,0x6, 0x2d,0xc2,0x6, 0x7e,0x73,0x35,0x46,0x7a,0x73,0x1c,0xbf,0x7e, -0x73,0x35,0x47,0x7a,0x73,0x1d,0xa1,0x7e,0x73,0x35,0x47,0x7a,0x73,0x1d,0x83,0x7e, -0x73,0x35,0x48,0x4c,0x77,0x68,0xb, 0xa, 0x37,0x1b,0x34,0x11,0x65,0xe4,0x7a,0xb3, -0x35,0x48,0x2, 0x24,0xd6,0xca,0x3b,0x7d,0xf3,0x6c,0xdd,0x7e,0x73,0x38,0x50,0x7e, -0x63,0x38,0x51,0xa, 0x26,0xa, 0x37,0x2d,0x32,0x7c,0xe7,0x12,0x47,0xfc,0x12,0x0, -0x64,0x7e,0x8, 0x23,0x16,0x7e,0x34,0x1, 0x22,0xe4,0x12,0x20,0x12,0x12,0x71,0xac, -0x50,0xfb,0x7e,0x1f,0x3, 0xd9,0x69,0xc1,0x0, 0x9e,0x69,0xd1,0x0, 0xaa,0x7e,0x1f, -0x3, 0xe1,0x69,0xe1,0x0, 0x2e,0xa9,0xd0,0xc4,0xa9,0xd5,0xcb,0x74,0x7, 0x91,0x2a, -0xf5,0x24,0x74,0x7, 0x7e,0x70,0xf, 0x71,0x40,0x71,0xa5,0x74,0x1, 0x12,0x1d,0x14, -0x7e,0x34,0x4, 0xb0,0x7e,0xf, 0x3, 0xdd,0x79,0x30,0x0, 0x6, 0x7e,0x34,0x0, 0x80, -0x7e,0xf, 0x3, 0xdd,0x79,0x30,0x0, 0x8, 0x7e,0x34,0x0, 0x10,0x7e,0xf, 0x3, 0xdd, -0x79,0x30,0x0, 0x12,0x6d,0x33,0x91,0xc6,0x7e,0xf, 0x3, 0xe1,0x2e,0x14,0x0, 0x2e, -0xb, 0xa, 0x30,0x5e,0x60,0xfe,0x1b,0xa, 0x30,0x6d,0x33,0x12,0xcf,0xd, 0x91,0x21, -0xb, 0xa, 0x30,0x4e,0x70,0x20,0x1b,0xa, 0x30,0x91,0x21,0xb, 0xa, 0x30,0x5e,0x34, -0xfe,0x7f,0x1b,0xa, 0x30,0x7e,0x27,0x1e,0x85,0x5e,0x24,0x0, 0x3, 0x12,0xc4,0x97, -0x91,0x21,0x91,0xb4,0x7e,0x34,0xff,0xff,0x7e,0xf, 0x3, 0xd9,0x79,0x30,0x0, 0xac, -0x7e,0xf, 0x3, 0xd9,0x79,0x30,0x0, 0xae,0x7e,0x34,0x0, 0xf, 0x7e,0xf, 0x3, 0xd9, -0x79,0x30,0x0, 0xb0,0x91,0x21,0xb, 0xa, 0x30,0x4e,0x60,0x88,0x1b,0xa, 0x30,0xbe, -0xf4,0x0, 0x3, 0x78,0x23,0x7e,0x1f,0x3, 0xdd,0x2e,0x34,0x0, 0xe, 0xb, 0x1a,0xf0, -0x4e,0xf4,0x0, 0x1, 0x1b,0x1a,0xf0,0x7e,0x1f,0x3, 0xdd,0x2e,0x34,0x0, 0xe, 0xb, -0x1a,0xf0,0x5e,0xf4,0x0, 0xf, 0x80,0x17,0xbe,0xf4,0x0, 0x4, 0x78,0x1c,0x7e,0xf4, -0x0, 0x2, 0x91,0xda,0x2e,0x34,0x0, 0xe, 0xb, 0x1a,0xf0,0x4e,0xf4,0x0, 0x8, 0x1b, -0x1a,0xf0,0x51,0xeb,0x7a,0x37,0x23,0x16,0x41,0x83,0x7e,0x34,0x0, 0x10,0x91,0xc6, -0x7d,0x2f,0x3e,0x24,0x3e,0x24,0x7e,0xf, 0x3, 0xdd,0x2e,0x14,0x0, 0xe, 0x91,0xb4, -0xe5,0xe, 0x60,0x7, 0xe5,0xe, 0xbe,0xb0,0x64,0x28,0x6, 0x7e,0x34,0x0, 0x2, 0x80, -0x4, 0xe5,0xe, 0xa, 0x3b,0x51,0xcd,0x4d,0xff,0x78,0x16,0x6c,0xdd,0x80,0xc, 0xa, -0x3d,0x9, 0x73,0x24,0x3a,0x91,0xbd,0x51,0xf5,0x91,0xcf,0xbc,0xed,0x38,0xf0,0x41, -0x76,0xbe,0xf4,0x0, 0x2, 0x78,0x20,0x7e,0xe3,0x1e,0x87,0x6c,0xdd,0x80,0x12,0xa, -0x3d,0x9, 0xc3,0x1e,0x88,0xa, 0x3c,0x9, 0x73,0x24,0x39,0x91,0xbd,0x51,0xf5,0x91, -0xcf,0xbc,0xed,0x38,0xea,0x80,0x6f,0xbe,0xf4,0x0, 0x1, 0x78,0x69,0x6c,0x99,0x7e, -0xe3,0x1e,0x87,0x7e,0xf0,0x1, 0x80,0x58,0xa, 0xff,0x9, 0xcf,0x1e,0x87,0xb, 0xf4, -0x7d,0x3f,0x7c,0xd7,0x80,0x44,0xa, 0xfd,0x9, 0x8f,0x1e,0x87,0xbc,0x8c,0x68,0x38, -0xbe,0x90,0x8f,0x38,0x39,0xa, 0x5c,0x9, 0x75,0x24,0x39,0xa, 0xf7,0x7d,0x3f,0x7c, -0x67,0x6c,0x77,0x7d,0xf3,0xa, 0x58,0x9, 0x75,0x24,0x39,0xa, 0x57,0x4d,0x5f,0x7e, -0x1f,0x3, 0xdd,0x79,0x51,0x0, 0x10,0x51,0xf5,0x7c,0x49,0xb, 0x90,0x7e,0x50,0x2, -0x7c,0xb4,0xac,0xb5,0x59,0x35,0x23,0x16,0xb, 0xd0,0xbc,0xed,0x50,0xb8,0xb, 0xf0, -0xbc,0xef,0x38,0xa4,0x7c,0xd9,0x51,0xeb,0x7e,0x50,0x2, 0x7c,0xbd,0xac,0xb5,0x59, -0x35,0x23,0x16,0xa9,0xd5,0xcb,0x74,0x7, 0x7e,0x71,0x24,0x71,0x40,0x71,0xa5,0xa9, -0xc0,0xc4,0x7e,0x1f,0x3, 0xd9,0x79,0xc1,0x0, 0x9e,0x7e,0x1f,0x3, 0xd9,0x79,0xd1, -0x0, 0xaa,0x7e,0x1f,0x3, 0xe1,0x79,0xe1,0x0, 0x2e,0x6d,0xff,0x7e,0x1f,0x3, 0xdd, -0x79,0xf1,0x0, 0x6, 0x7e,0x1f,0x3, 0xdd,0x79,0xf1,0x0, 0x8, 0x7e,0x1f,0x3, 0xdd, -0x79,0xf1,0x0, 0x12,0x91,0xda,0x79,0xf1,0x0, 0x10,0xda,0x3b,0x22,0x7d,0x23,0x80, -0x11,0x7e,0x30,0x4, 0x80,0x4, 0x74,0xfa,0x91,0xe7,0x7c,0x23,0x1b,0x30,0xa5,0xba, -0x0, 0xf4,0x7d,0x32,0x1b,0x24,0x4d,0x33,0x78,0xe7,0x22,0x6d,0xff,0x7e,0x1f,0x3, -0xdd,0x79,0xf1,0x0, 0x10,0x7e,0x34,0x0, 0x2, 0x51,0xcd,0x7e,0x34,0x0, 0x1, 0x7e, -0xf, 0x3, 0xdd,0x79,0x30,0x0, 0x4, 0x7e,0xf, 0x3, 0xdd,0x69,0x30,0x0, 0x14,0x5e, -0x34,0x0, 0x1, 0x68,0xf2,0x7e,0x34,0x0, 0x1, 0x79,0x30,0x0, 0x14,0x7e,0xf, 0x3, -0xdd,0x69,0x30,0x0, 0xa, 0x7d,0x23,0x6d,0x33,0x69,0x10,0x0, 0xc, 0x6d,0x0, 0x2f, -0x10,0x74,0x7, 0x1e,0x34,0x1e,0x24,0x50,0x3, 0x4e,0x60,0x80,0x14,0x78,0xf4,0x22, -0x7c,0xa7,0xf5,0xfd,0x7a,0xa1,0xfe,0x22,0x6d,0x33,0x7e,0x8, 0x0, 0x24,0x7e,0x24, -0x0, 0x12,0x12,0x6a,0xd6,0xa9,0xd5,0xcb,0x74,0x8, 0x7e,0x71,0x2c,0x71,0x40,0x74, -0x9, 0x7e,0x71,0x2d,0x71,0x40,0xe5,0x33,0xb4,0x1, 0x15,0x7e,0x71,0x31,0x5e,0x70, -0x1f,0x3e,0x70,0x3e,0x70,0x74,0xa, 0x71,0x40,0x74,0xb, 0x7e,0x71,0x32,0x71,0x40, -0x74,0xc, 0x7e,0x71,0x30,0x71,0x40,0x74,0x2, 0x7e,0x71,0x26,0x71,0x40,0x74,0x3, -0x7e,0x71,0x27,0x71,0x40,0x74,0x4, 0x7e,0x71,0x28,0x71,0x40,0x74,0x5, 0x7e,0x71, -0x29,0x71,0x40,0x61,0xa5,0x75,0xfd,0xff,0xa9,0xc5,0xcb,0x22,0xa9,0xd5,0xcb,0x74, -0x2, 0x7e,0x70,0x3f,0x71,0x40,0x74,0x3, 0x7e,0x70,0x1f,0x71,0x40,0xa9,0xd0,0xce, -0xa9,0xd6,0xc9,0x74,0x5, 0x91,0x2a,0x7c,0x7b,0x5e,0x70,0xe0,0x4e,0x70,0x1d,0x74, -0x5, 0x71,0x40,0x74,0xa, 0x7e,0x70,0x24,0x71,0x40,0x74,0xb, 0x7e,0x70,0xc, 0x71, -0x40,0x74,0xc, 0x7e,0x70,0x2, 0x71,0x40,0x7e,0x71,0xc1,0x5e,0x70,0xe0,0x4e,0x70, -0x2, 0x7a,0x71,0xc1,0x7e,0x71,0xc2,0x5e,0x70,0xe0,0x4e,0x70,0x4, 0x7a,0x71,0xc2, -0x74,0xc, 0x91,0x2a,0x54,0x7f,0x68,0x7, 0x74,0xc, 0x7e,0x70,0xf8,0x71,0x40,0x75, -0xcf,0x90,0x74,0x7, 0x91,0x2a,0x7c,0x7b,0x5e,0x70,0xfb,0x74,0x7, 0x71,0x40,0x61, -0xa5,0x7e,0xf, 0x3, 0xd9,0x2e,0x14,0x0, 0x9e,0x22,0x7c,0x7b,0x7a,0x71,0xfd,0xe5, -0xfe,0x22,0x7f,0x71,0x12,0xcf,0xa4,0xc2,0x3, 0x12,0xc6,0xf7,0xc2,0x5, 0xb1,0x23, -0xc2,0x3, 0x12,0xc7,0x79,0xa9,0xd5,0xcb,0x74,0xf, 0x91,0x2a,0x7a,0x7b,0xb0,0x74, -0xf, 0x6c,0x77,0x71,0x40,0xe5,0xfc,0x7a,0xb, 0xb0,0x43,0xfc,0x10,0x61,0xa5,0x7c, -0x7b,0x2e,0x70,0xab,0x68,0x13,0x2e,0x70,0xef,0x68,0x21,0x2e,0x70,0xde,0x68,0x2d, -0x2e,0x70,0xde,0x78,0x38,0x74,0x5, 0x80,0x36,0x7e,0xb3,0x32,0x5d,0xb4,0x5, 0x33, -0x7e,0x34,0x0, 0x1, 0x51,0xcd,0x12,0xc6,0xaf,0x2, 0xc7,0x63,0x7e,0xb3,0x32,0x5d, -0xb4,0x5, 0x20,0x7e,0x34,0x0, 0x1, 0x51,0xcd,0x75,0xe9,0xff,0x22,0x7e,0xb3,0x32, -0x5d,0xb4,0x5, 0xf, 0x7e,0x34,0x0, 0x1, 0x51,0xcd,0x2, 0xc7,0x5e,0x74,0x1, 0x7a, -0xb3,0x32,0x5d,0x22,0xb, 0xa, 0x30,0x4d,0x32,0x1b,0xa, 0x30,0x22,0x7e,0xf, 0x3, -0xdd,0x79,0x30,0x0, 0x10,0x22,0x7e,0xf, 0x3, 0xdd,0x79,0x30,0x0, 0xe, 0x22,0x74, -0x2, 0xac,0xbd,0x59,0x35,0x23,0x16,0xb, 0xd0,0x22,0x7e,0x1f,0x3, 0xdd,0x79,0xf1, -0x0, 0xe, 0x7e,0x1f,0x3, 0xdd,0x22,0x7c,0x7b,0x80,0xe, 0x7e,0x60,0x3, 0x80,0x1, -0x0, 0x7c,0xa6,0x1b,0x60,0x4c,0xaa,0x78,0xf7,0x7c,0xa7,0x1b,0x70,0x4c,0xaa,0x78, -0xea,0x22,0x7c,0xa7,0x7c,0x6b,0xa9,0xd5,0xcb,0x74,0xf, 0x7c,0x7a,0x71,0x40,0x7a, -0x61,0xfc,0x71,0xa5,0xf1,0x9d,0xd2,0x3, 0x12,0xc7,0x79,0xf1,0x7e,0x12,0x1d,0x14, -0x2, 0x1c,0xe3,0xa9,0xd0,0xce,0xa2,0x5, 0xa9,0x91,0xc9,0x22,0x30,0x4, 0x5, 0xf1, -0x7e,0x2, 0x1c,0xe3,0x12,0xcf,0xa4,0xc2,0x5, 0xa1,0x23,0xca,0x3b,0x7e,0xb3,0x35, -0x6, 0xb4,0x1, 0x2, 0x80,0x2, 0xc1,0x92,0x6c,0xdd,0xc2,0x3, 0x7e,0xb3,0x35,0x31, -0xb4,0x1, 0x2, 0x80,0x0, 0x7e,0xe0,0xa, 0x7e,0xf0,0x64,0x12,0x9e,0x8e,0x7d,0x43, -0x12,0x71,0xac,0xe4,0x33,0x68,0xf9,0x74,0x1, 0x7a,0xb3,0x36,0x4f,0x12,0x36,0xb3, -0x12,0xcf,0x9d,0x74,0xa, 0x91,0xe7,0x12,0xcf,0x43,0x7e,0x1f,0x1d,0x8f,0x7a,0x1d, -0x25,0x7e,0xb3,0x1d,0x7c,0xf5,0x24,0x74,0x4, 0x7a,0xb3,0x1d,0x7c,0x12,0x45,0x1b, -0x7a,0x47,0x1d,0x89,0x12,0xce,0x27,0x12,0x42,0x2d,0x12,0x9e,0xc4,0xc1,0x6c,0xd2, -0x4, 0xb1,0x2c,0x12,0x62,0xe3,0x30,0xe, 0x2, 0xc1,0x76,0x7e,0xb3,0x35,0x8, 0xb4, -0x1, 0x2, 0x80,0x2, 0xc1,0x76,0x7c,0xbe,0x12,0x67,0x3, 0xe4,0x12,0x1d,0x14,0x12, -0x41,0x87,0x12,0x45,0x8b,0xa9,0xd1,0xcb,0x12,0x44,0xd5,0xc2,0x3, 0x80,0x46,0x30, -0x1b,0x38,0x20,0x3, 0x35,0xd2,0x4, 0xb1,0x2c,0x12,0x9d,0x74,0xd2,0x3, 0x6d,0x33, -0x9e,0x37,0x1c,0xc5,0xbe,0x37,0x9, 0x6, 0x8, 0x5, 0xe4,0x7a,0xb3,0x36,0x4e,0xd1, -0x95,0x68,0x6, 0x7e,0xb3,0x36,0x4e,0x60,0x2c,0xc2,0x4, 0xb1,0x2c,0x80,0xb, 0xd1, -0xdc,0xe4,0xf1,0x37,0x20,0x3, 0x3, 0x20,0x1b,0x3, 0x20,0x93,0xf2,0x30,0x1b,0x3, -0x30,0x3, 0x2, 0xd1,0xa0,0x7e,0xb3,0x35,0x8, 0xb4,0x1, 0x6, 0x30,0x19,0xb0,0x30, -0x3, 0xad,0x30,0x1b,0xaa,0x7e,0xa3,0x36,0x4e,0x4c,0xaa,0x78,0x6, 0x74,0x1, 0x7a, -0xb3,0x36,0x4f,0x4c,0xaa,0x68,0xb, 0x7e,0xb3,0x35,0x31,0x70,0x5, 0xe4,0x7a,0xb3, -0x36,0x4e,0xd1,0x95,0x78,0x15,0x7e,0xb3,0x36,0x4e,0x60,0xf, 0xe4,0x7a,0xb3,0x36, -0x4e,0x7a,0xb3,0x1c,0x47,0x7a,0xb3,0x1c,0x48,0x80,0x1b,0xd1,0x95,0x68,0xd, 0x7e, -0xb3,0x36,0x4e,0x70,0x7, 0xe4,0x7a,0xb3,0x35,0x6, 0x80,0xa, 0x7c,0xad,0xb, 0xd0, -0xbc,0xaf,0x50,0x2, 0xa1,0x9f,0xe4,0x7a,0xb3,0x1d,0x86,0x7e,0x1d,0x25,0x7a,0x1f, -0x1d,0x8f,0xe5,0x24,0x7a,0xb3,0x1d,0x7c,0xd2,0x4, 0xb1,0x2c,0xa9,0xd1,0xcb,0x12, -0x24,0xb9,0xda,0x3b,0x22,0x7e,0x73,0x36,0x17,0xa, 0x37,0x5e,0x34,0x0, 0x2, 0x22, -0x30,0x19,0x3, 0x20,0x1b,0x35,0x30,0x1b,0x4, 0xc2,0x4, 0xb1,0x2c,0xa9,0xd1,0xcd, -0xa9,0xc5,0xea,0xa9,0xd3,0xcd,0xa9,0xd2,0xcd,0xa9,0xd0,0xce,0xa9,0xc4,0xc9,0xd1, -0xdc,0x74,0x2, 0xf1,0x37,0xa9,0xd0,0xce,0xa9,0xd4,0xc9,0xa9,0xc1,0xcd,0xa9,0xc3, -0xcd,0xa9,0xc2,0xcd,0x30,0x1b,0x4, 0xc2,0x4, 0xa1,0x2c,0x22,0x74,0x81,0x7a,0xb3, -0x36,0x2f,0x22,0xd1,0xdc,0x12,0x9e,0x85,0x75,0xcd,0x0, 0xa9,0xd6,0xeb,0xa9,0xd7, -0xcd,0xc2,0xce,0x12,0xaf,0x6e,0x91,0x32,0x74,0x1, 0xf1,0x37,0xa9,0xc6,0xeb,0xa9, -0xc7,0xcd,0xd2,0xce,0xe5,0x25,0x7e,0x71,0x24,0xa1,0x2, 0x80,0x1a,0xd1,0xdc,0x12, -0x5f,0xf2,0x68,0x4, 0xc2,0x4, 0xb1,0x2c,0x7e,0xb3,0x36,0x2, 0xbe,0xb0,0x2, 0x68, -0x15,0x20,0x19,0x12,0xe4,0xf1,0x37,0x20,0x93,0xe3,0xd1,0xdc,0xa9,0xd1,0xcd,0xa9, -0xc5,0xea,0x74,0x2, 0xe1,0x37,0x22,0x7c,0xab,0x7e,0xb3,0x36,0x2f,0xb4,0x81,0x38, -0x4c,0xaa,0x78,0x5, 0xa9,0xd0,0x87,0x80,0x29,0xbe,0xa0,0x1, 0x78,0xf, 0xc2,0xaf, -0xa9,0xd0,0xce,0xa9,0xc7,0xc9,0xa9,0xd1,0x87,0xd2,0xaf,0x80,0x15,0xbe,0xa0,0x2, -0x78,0x16,0xc2,0xaf,0x20,0x93,0x9, 0xa9,0xd0,0xce,0xa9,0xd7,0xc9,0xa9,0xd1,0x87, -0xd2,0xaf,0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xe4,0x7a,0xb3,0x36,0x2f,0x22,0xd2,0x5, -0xb1,0x23,0x74,0x1, 0x22,0xd2,0x3, 0x80,0x10,0x30,0x3, 0xb, 0x12,0x5f,0xf2,0x68, -0x6, 0xc2,0x3, 0xc2,0x4, 0xb1,0x2c,0xf1,0xb, 0x30,0x19,0xed,0x22,0xca,0xf8,0xa2, -0xaf,0xe4,0x33,0x7c,0xfb,0xd2,0x3, 0x12,0xc6,0xf7,0xa9,0xd0,0xcb,0xc2,0xaf,0xa9, -0xd0,0x9e,0x75,0x9d,0x0, 0xa9,0xd0,0x9e,0x75,0x9c,0x54,0xa9,0xd0,0x9e,0xa9,0xd4, -0x9e,0xa9,0xd0,0xcd,0x74,0x41,0x91,0xe7,0xa9,0xd0,0x9e,0xa9,0xd7,0x9e,0x2e,0xf0, -0xff,0x92,0xaf,0xda,0xf8,0x22,0x12,0x71,0xac,0x50,0xfb,0x12,0xcf,0x5d,0x12,0xcf, -0x54,0x6d,0x33,0x7a,0x35,0xa, 0x12,0xcd,0x62,0x74,0x50,0x7a,0xb3,0x35,0x75,0x7e, -0x24,0x3, 0x20,0x12,0xcf,0x66,0xe4,0x12,0xce,0x1e,0x6d,0x33,0x7a,0x37,0x36,0x31, -0x2, 0x24,0xb9,0x7e,0xb3,0x35,0x50,0x14,0x68,0x13,0x14,0x68,0x2c,0xb, 0xb1,0x68, -0x2, 0x1, 0xbd,0xe4,0x7a,0xb3,0x24,0x81,0x7a,0xb3,0x24,0x38,0x22,0x7e,0xb3,0x24, -0x81,0xbe,0xb0,0x1, 0x68,0xc, 0x53,0xeb,0x5f,0x53,0xac,0x5f,0x74,0x1, 0x7a,0xb3, -0x24,0x81,0xe5,0x80,0x7a,0xb3,0x24,0x38,0x22,0x7e,0xb3,0x24,0x81,0xbe,0xb0,0x2, -0x68,0x1d,0x53,0xeb,0x5f,0x53,0xac,0x5f,0x7e,0x8, 0x24,0x82,0x11,0xbe,0x74,0x2, -0x7a,0xb3,0x24,0x81,0xe4,0x7a,0xb3,0x24,0x38,0xe5,0x80,0x7a,0xb3,0x24,0x8a,0x7e, -0xa1,0x80,0x6c,0x77,0xa, 0x27,0x9, 0x62,0x24,0x82,0xbe,0x60,0xff,0x50,0x44,0x7e, -0x44,0x0, 0x1, 0x7c,0xb7,0x60,0x5, 0x3e,0x44,0x14,0x78,0xfb,0x7e,0xb3,0x24,0x8a, -0x6c,0xba,0xa, 0x2b,0x5d,0x24,0x68,0x2b,0xa, 0x27,0x2e,0x24,0x24,0x82,0x7e,0x29, -0x60,0x7c,0xb6,0x4, 0x7a,0x29,0xb0,0xbe,0x60,0x5, 0x40,0x17,0x7e,0x44,0x0, 0x1, -0x7c,0xb7,0x60,0x5, 0x3e,0x44,0x14,0x78,0xfb,0x7c,0x69,0x4e,0x63,0x24,0x38,0x7a, -0x63,0x24,0x38,0xb, 0x70,0xa5,0xbf,0x8, 0xab,0x7a,0xa3,0x24,0x8a,0x22,0x7e,0x34, -0x0, 0x8, 0xe4,0x2, 0x20,0x12,0xca,0xf8,0x7e,0xf3,0x38,0x51,0x7e,0x8, 0x2, 0x8f, -0x11,0xbe,0x7e,0x8, 0x2, 0x97,0x7e,0x34,0x0, 0x24,0x74,0x3f,0x12,0x20,0x12,0xd2, -0x3, 0x7e,0x8, 0x1d,0x56,0x7c,0xbf,0x12,0xc7,0xe5,0x7e,0x8, 0x2, 0x8f,0x7a,0xf, -0x2, 0xbb,0x7f,0x1, 0x6d,0x0, 0x7a,0x17,0x2, 0xbf,0x7d,0x32,0x7a,0x37,0x2, 0xc1, -0x7e,0x18,0x2, 0x97,0x7a,0x1f,0x2, 0xc7,0x6c,0x77,0x80,0x15,0x31,0x7f,0xbe,0x60, -0x24,0x50,0xc, 0xa, 0x27,0x9, 0x52,0x1d,0xc8,0xa, 0x16,0x19,0x51,0x2, 0x97,0xb, -0x70,0xbc,0xf7,0x38,0xe7,0x31,0x36,0x6d,0x33,0x7a,0x37,0x2, 0xbf,0x7a,0x37,0x2, -0xc1,0x31,0x36,0xda,0xf8,0x22,0xa9,0xc6,0xea,0x7e,0x8, 0x2, 0xbb,0xe4,0x12,0x1a, -0x8b,0xa9,0xd6,0xea,0x7e,0x8, 0x2, 0xbb,0xe4,0x2, 0x1a,0x8b,0x74,0x1, 0x7a,0xb3, -0x35,0x8, 0x12,0x53,0x88,0x12,0x0, 0xa, 0x12,0x1d,0x2b,0x11,0xc6,0x7e,0x24,0x3, -0xd4,0x12,0xcf,0x66,0x74,0x1, 0x12,0x36,0xb3,0xd1,0x33,0x7e,0x34,0xd0,0xc, 0x12, -0x1d,0x3c,0x12,0x36,0xeb,0x7e,0x34,0x0, 0x1, 0xe4,0x6c,0x55,0x2, 0x1c,0x31,0xa, -0x27,0x9, 0x62,0x1d,0x56,0x22,0xe4,0x12,0x0, 0xe, 0x74,0x6, 0x7e,0x70,0x9b,0x12, -0x1c,0x5c,0x6c,0x77,0x80,0x1b,0x31,0x7f,0xa, 0x26,0x12,0x70,0xb1,0x7c,0x6b,0xa, -0x26,0x74,0x2, 0xac,0xb7,0x7e,0xf, 0x3, 0xd9,0x2d,0x15,0x79,0x20,0x0, 0x52,0xb, -0x70,0x7e,0x53,0x1c,0xe6,0xbc,0x57,0x38,0xdd,0x22,0xca,0x3b,0xf5,0x2c,0x7a,0x1d, -0x28,0x7f,0x30,0x7e,0x1d,0x28,0x12,0x6c,0xa1,0xd1,0x33,0xe5,0x2c,0x7e,0x70,0x1, -0x51,0x2d,0x75,0x2d,0x0, 0x31,0x86,0x91,0xd5,0x30,0x1b,0xfd,0x74,0x1, 0x12,0x0, -0xe, 0x7f,0x3, 0x12,0x71,0xa1,0x75,0x2e,0x0, 0x80,0x15,0x51,0x18,0x7f,0x13,0x2d, -0x35,0xb, 0x1a,0x20,0x51,0x18,0x7e,0xd, 0x28,0x2d,0x15,0x12,0xcf,0x3a,0x5, 0x2e, -0x71,0x27,0x2d,0x23,0xe5,0x2e,0xa, 0x3b,0xbd,0x32,0x48,0xdf,0x5, 0x2d,0xe5,0x2d, -0xbe,0xb0,0x1, 0x40,0xc0,0xda,0x3b,0x22,0x7e,0x71,0x2e,0x74,0x2, 0xac,0xb7,0x22, -0x7e,0x8, 0x1c,0xdf,0x12,0xd, 0x0, 0x7e,0xb3,0x1d,0x7c,0x6c,0x77,0x7c,0xa7,0x4c, -0xaa,0x78,0x8, 0x7e,0x34,0x0, 0x1, 0x71,0xfe,0x80,0x15,0x12,0xc9,0x65,0x7c,0x7b, -0xa, 0x17,0x6d,0x0, 0x7e,0x18,0x80,0x0, 0x12,0x1d,0x98,0x71,0xfe,0x4e,0x70,0xb0, -0x1b,0xa, 0x30,0x22,0xca,0x3b,0x7e,0xe3,0x1c,0xe6,0x7e,0xf3,0x1d,0x7c,0x74,0x1, -0x7a,0xb3,0x1d,0x7c,0x51,0x20,0x12,0xcf,0x43,0x7e,0x8, 0x2, 0x8f,0x7e,0x34,0x0, -0x6a,0x12,0x20,0x12,0x7e,0xd0,0x8, 0x12,0x62,0xe3,0x6c,0xcc,0x80,0x1b,0x7e,0x44, -0x0, 0x1, 0x7c,0xbd,0x60,0x5, 0x3e,0x44,0x14,0x78,0xfb,0x7e,0x50,0x2, 0xac,0x5c, -0x71,0xd8,0x4d,0x34,0x1b,0x28,0x30,0xb, 0xc0,0x71,0x27,0x2d,0x23,0xa, 0x3c,0xbd, -0x32,0x48,0xdb,0x7e,0x34,0x0, 0x6a,0xca,0x39,0x71,0xe0,0x12,0x1f,0xed,0x1b,0xfd, -0x71,0xc8,0x31,0x86,0xb1,0x8b,0x91,0xd5,0x30,0x1b,0xfd,0x74,0x1, 0x12,0x0, 0xe, -0x7e,0x8, 0x6, 0x84,0x7e,0xb3,0x1c,0xe5,0x7c,0x7e,0x12,0xe, 0x24,0x6c,0xcc,0x80, -0x2b,0x7e,0x50,0x2, 0xac,0x5c,0x49,0x32,0x6, 0x84,0xbe,0x34,0x15,0x40,0x50,0x1a, -0x7e,0x34,0x0, 0x1, 0x7c,0xbd,0x60,0x5, 0x3e,0x34,0x14,0x78,0xfb,0x7d,0x13,0x6e, -0x14,0xff,0xff,0x71,0xd8,0x5d,0x31,0x1b,0x28,0x30,0xb, 0xc0,0x71,0x27,0x2d,0x23, -0xa, 0x3c,0xbd,0x32,0x48,0xcb,0x1b,0xd0,0xbe,0xd0,0x0, 0x48,0x2, 0x41,0x77,0x7e, -0x34,0x0, 0x6a,0xca,0x39,0x71,0xe0,0x12,0x1f,0xed,0x1b,0xfd,0x71,0xc8,0x7a,0xf3, -0x1d,0x7c,0x51,0x20,0xda,0x3b,0x22,0x7e,0x73,0x1c,0xe6,0xa, 0x37,0x7e,0x53,0x1c, -0xe5,0xa, 0x25,0x22,0xca,0x3b,0x7c,0xfb,0x7e,0x8, 0x2, 0xf9,0x7e,0x34,0x0, 0x90, -0x74,0x3e,0x12,0xcf,0x75,0xf5,0x29,0x7e,0xb3,0x1c,0xe6,0xf5,0x2a,0x6c,0xee,0x80, -0x24,0x7a,0xe1,0x28,0xa, 0x3e,0x9, 0xd3,0x1d,0x56,0xa, 0x3d,0x12,0x66,0x29,0x7c, -0xdb,0xbe,0xd0,0x24,0x50,0xd, 0xa, 0xd, 0x12,0xce,0x43,0xa, 0x3d,0x8d,0x32,0x71, -0xeb,0x91,0x7a,0xb, 0xe0,0xe5,0x2a,0xbc,0xbe,0x38,0xd6,0x6c,0xee,0x80,0x25,0xa, -0x4e,0xe5,0x2a,0xa, 0x5b,0x2d,0x54,0xf5,0x28,0xa, 0x3e,0x9, 0xd3,0x1d,0x33,0xbe, -0xd0,0x23,0x50,0xe, 0xa, 0x5d,0x12,0xce,0x36,0xa, 0x2d,0x12,0xce,0xfc,0x71,0xeb, -0x91,0x7a,0xb, 0xe0,0xe5,0x29,0xbc,0xbe,0x38,0xd5,0x6c,0xee,0x7e,0x30,0x18,0xac, -0x3e,0x2e,0x14,0x2, 0xf9,0x6d,0x0, 0x7c,0xbf,0x7c,0x7e,0x12,0x1b,0x80,0xb, 0xe0, -0xbe,0xe0,0x6, 0x40,0xe7,0xda,0x3b,0x22,0x74,0x2, 0x12,0x0, 0x6, 0x7e,0xb3,0x1d, -0x7e,0x71,0x34,0x74,0x2, 0x2, 0x0, 0x6, 0x2e,0x24,0x2, 0x8f,0xb, 0x28,0x30,0x22, -0x7e,0x17,0x1d,0x80,0x6d,0x0, 0x7e,0x18,0x2, 0x8f,0x22,0x2d,0x31,0x7c,0xc7,0x7e, -0x30,0x2, 0xac,0x3c,0x2e,0x14,0x2, 0xf9,0x6d,0x0, 0x7e,0x71,0x28,0x22,0x7e,0xf, -0x36,0x20,0x79,0x30,0x0, 0x12,0x7e,0xf, 0x36,0x20,0x2e,0x14,0x0, 0x6, 0xb, 0xa, -0x30,0x5e,0x34,0xfe,0xf, 0x22,0x7e,0xb3,0x1d,0x84,0x70,0x3a,0x12,0x71,0xac,0xe4, -0x33,0x68,0xf9,0xe4,0x6c,0x77,0x91,0x57,0x7e,0x8, 0x6, 0x84,0x7e,0x1f,0x6, 0x7c, -0x7e,0xb3,0x1e,0x14,0x31,0xba,0x74,0x1, 0x7e,0x70,0x1, 0x91,0x57,0x7e,0x8, 0x7, -0xc2,0x7e,0x1f,0x6, 0x7c,0x7e,0xb3,0x16,0xc3,0x31,0xba,0x74,0x2, 0x7a,0xb3,0x1d, -0x84,0xe4,0x7a,0xb3,0x16,0xbe,0x22,0x7c,0xa7,0x12,0x36,0xb3,0x7c,0xba,0x12,0x1c, -0xa9,0x74,0xa, 0x12,0x3c,0xe7,0x41,0x54,0x2d,0x31,0x7c,0xd7,0x7e,0x30,0x2, 0xac, -0x3d,0x2e,0x14,0x2, 0x9f,0x6d,0x0, 0x7e,0x71,0x24,0x74,0x2, 0xac,0x7b,0x2e,0x37, -0x1d,0x80,0x6d,0x22,0x74,0x1, 0x7c,0x9b,0x7f,0x61,0x7f,0x70,0x6c,0x88,0x80,0x40, -0x74,0x2, 0xac,0xb8,0x7f,0x16,0x2d,0x35,0xb, 0x1a,0xb0,0x5e,0xb4,0x1, 0xff,0xbe, -0xb4,0x0, 0xff,0x28,0xc, 0x7d,0x9b,0x9e,0x94,0x0, 0xff,0x7e,0xa4,0x0, 0xff,0x80, -0x4, 0x6d,0x99,0x7d,0xab,0x7d,0x39,0x7c,0x37,0x7f,0x17,0x2d,0x35,0x7a,0x1b,0x30, -0x7d,0x3a,0x74,0x2, 0xac,0xb8,0x7f,0x7, 0x2d,0x15,0x39,0x70,0x0, 0x1, 0xb, 0x80, -0xbc,0x98,0x38,0xbc,0x22,0x7e,0xb3,0x1d,0x7e,0x2, 0x0, 0x76,0xca,0xf8,0x7c,0xfb, -0x7e,0x6f,0x1d,0x8f,0xbe,0xf0,0x1, 0x28,0x3, 0xe4,0x80,0x2c,0x7c,0xbf,0xb1,0xbc, -0x4c,0xff,0x78,0x2, 0xb1,0x1b,0xa2,0xd, 0xe4,0x33,0x78,0x2, 0xb1,0x1b,0x12,0xce, -0x27,0x51,0x2d,0x7a,0x6f,0x1d,0x8f,0x7e,0x73,0x1d,0x7c,0xb1,0x29,0xe4,0x7e,0x50, -0x1, 0x12,0x1c,0x31,0x91,0xd5,0x74,0x1, 0xda,0xf8,0x22,0x7e,0x1f,0x1d,0x8f,0x6d, -0x22,0x5e,0x60,0x1, 0x7a,0x1f,0x1d,0x8f,0x22,0xa, 0x37,0x3e,0x34,0x3e,0x34,0x22, -0x7e,0x73,0x34,0xe1,0xb1,0x29,0x7a,0x37,0x1c,0xcc,0x7e,0x73,0x34,0xe2,0xb1,0x29, -0x7a,0x37,0x1c,0xce,0x6d,0x33,0x9e,0x37,0x1c,0xce,0x7a,0x37,0x1c,0xd0,0x7e,0x73, -0x34,0xe3,0xa, 0x37,0xb1,0x82,0x7a,0x37,0x1c,0xc1,0x7e,0x73,0x34,0xe4,0xa, 0x37, -0xb1,0x82,0x7a,0x37,0x1c,0xc3,0x7e,0x73,0x34,0xe5,0xa, 0x37,0xb1,0x82,0x7a,0x37, -0x1c,0xc5,0x22,0x7e,0xf, 0x3, 0xd9,0x69,0x20,0x0, 0xa0,0x5e,0x50,0x1f,0xa, 0x37, -0x3e,0x34,0x3e,0x34,0x3e,0x34,0x3e,0x34,0x3e,0x34,0x22,0x7e,0x33,0x1d,0x7a,0x7e, -0x23,0x1d,0x7b,0xa, 0x32,0x6d,0x22,0xa, 0x13,0x6d,0x0, 0x2f,0x1, 0x74,0x4, 0x2f, -0x0, 0x14,0x78,0xfb,0x2e,0x8, 0x0, 0x2a,0x12,0x69,0xe0,0x12,0xce,0xd0,0x28,0x3, -0x7e,0x70,0x7, 0xb1,0x73,0x2d,0x32,0x79,0x30,0x0, 0xa0,0x22,0x7c,0xab,0x12,0x6c, -0x7d,0x7c,0xba,0x12,0xcf,0x9d,0xa1,0x8b,0x7c,0xbf,0x6c,0x77,0xca,0x69,0xca,0xf8, -0x7c,0x5b,0x6c,0xff,0x74,0x9, 0xac,0xb5,0x49,0x45,0x31,0x3b,0x7a,0x45,0x26,0x49, -0x65,0x31,0x3d,0x7d,0x36,0x12,0x8f,0x9, 0x50,0x3, 0x7e,0xf0,0x6, 0x7e,0x35,0x26, -0x12,0x5c,0x82,0x50,0x3, 0x7e,0xf0,0x6, 0x7e,0x35,0x26,0x7e,0x24,0x2, 0x0, 0x12, -0x5c,0x86,0x50,0x28,0x7e,0x73,0x38,0x51,0xa, 0x37,0x1b,0x35,0xb1,0x80,0xb1,0x84, -0xbd,0x36,0x28,0x6, 0xbe,0x64,0x2, 0x0, 0x38,0x12,0x7e,0x73,0x30,0xb7,0xbe,0x70, -0x0, 0x38,0x6, 0x7e,0xb3,0x31,0x96,0x60,0x3, 0x4e,0xf0,0x1, 0x7c,0xbf,0xda,0xf8, -0xda,0x69,0x22,0x7e,0x8, 0x1c,0xdf,0x2, 0x0, 0x2e,0xb1,0x30,0xd1,0x7f,0x7e,0xb3, -0x3, 0xfe,0xc1,0x44,0x7c,0x7b,0xa5,0xbf,0x1, 0x34,0x7e,0xb3,0x1c,0xda,0xb4,0x1, -0x2d,0x7e,0x73,0x1a,0xb5,0x6c,0x66,0x80,0x21,0x74,0x2, 0xac,0xb6,0x9, 0x55,0x18, -0x96,0x7e,0x43,0x1c,0xe0,0xa, 0x4, 0x1b,0x4, 0xa, 0x15,0xbd,0x10,0x78,0x9, 0x7e, -0x34,0x0, 0x3c,0x7a,0x37,0x1c,0xc3,0x22,0xb, 0x60,0xbc,0x76,0x38,0xdb,0x22,0x7e, -0xb3,0x1c,0xda,0xb4,0x1, 0x3, 0x2, 0xb2,0xb4,0x22,0x7e,0xb3,0x1c,0xda,0x60,0x4, -0xd1,0x3a,0xc1,0xaa,0x22,0xd1,0x8a,0x12,0x0, 0x28,0xd1,0xf7,0x7e,0xb3,0x1c,0xdb, -0x70,0x7, 0xe4,0x7a,0xb3,0x3, 0xfe,0xc1,0xaa,0x22,0xe4,0x7a,0xb3,0x1a,0xc4,0x12, -0x29,0x13,0x7e,0xb3,0x16,0xbf,0xb4,0x1, 0x8, 0x7e,0x73,0x1a,0xb5,0x7a,0x73,0x1a, -0xc3,0x7e,0x18,0x4, 0xd4,0x7a,0x1f,0x6, 0x80,0x7e,0x18,0x5, 0xa8,0x7a,0x1f,0x6, -0x7c,0x12,0xcb,0xd6,0x12,0x75,0x45,0x7e,0xb3,0x16,0xbe,0xb4,0x1, 0x18,0x7e,0x73, -0x18,0x1e,0x7a,0x73,0x18,0x8e,0x7e,0x73,0x18,0x20,0x7a,0x73,0x18,0x90,0x7e,0x73, -0x18,0x1f,0x7a,0x73,0x18,0x8f,0x22,0xb1,0x30,0x7e,0xb3,0x34,0x8, 0xb4,0x1, 0x10, -0x7e,0x34,0x1, 0x40,0x7a,0x37,0x1c,0xcc,0x7e,0x34,0x1, 0x18,0x7a,0x37,0x1c,0xce, -0x12,0xb2,0xab,0x7e,0xb3,0x1a,0xd9,0xb4,0x1, 0x24,0x7e,0x34,0x1, 0x5e,0x7a,0x37, -0x1c,0xcc,0x7e,0x34,0x1, 0x2c,0x7a,0x37,0x1c,0xce,0x7a,0x37,0x1c,0xc1,0x7e,0x34, -0x0, 0xc8,0x7a,0x37,0x1c,0xc3,0x7e,0x34,0x0, 0xfa,0x7a,0x37,0x1c,0xc5,0x7e,0xb3, -0x1c,0x47,0x70,0x23,0x7e,0x27,0x1c,0xcc,0x7d,0x32,0x7e,0x14,0x0, 0x4, 0xad,0x13, -0x7d,0x31,0x12,0xb4,0x56,0x1e,0x34,0xbe,0x34,0x0, 0x50,0x28,0x4, 0x7e,0x34,0x0, -0x50,0x2d,0x32,0x7a,0x37,0x1c,0xcc,0x22,0x12,0x58,0x6d,0xe4,0x7a,0xb3,0x1e,0x84, -0x12,0x6c,0xca,0x7e,0xb3,0x35,0x8, 0xb4,0x1, 0x5d,0x12,0xc7,0x8e,0x12,0x59,0x35, -0x12,0x66,0xc0,0x12,0x87,0xfa,0x12,0x25,0x5d,0x50,0xe5,0x12,0x90,0x40,0x12,0x9b, -0x30,0x7e,0xb3,0x35,0x5, 0xb4,0x1, 0x3, 0xe4,0xf1,0xf0,0xd1,0x95,0xf1,0xe7,0x68, -0xcf,0x12,0x35,0xee,0xf1,0xe7,0x68,0xc8,0x12,0xa1,0x48,0x12,0x27,0xd, 0x12,0x87, -0xf8,0x12,0x9e,0x13,0x12,0x0, 0x42,0x12,0x97,0x55,0x12,0x89,0x7d,0x12,0x93,0xfa, -0x12,0x0, 0x71,0x12,0x5a,0x2f,0x12,0x5d,0x31,0x12,0x90,0x7e,0x12,0x58,0x35,0x12, -0x59,0x3c,0x12,0x57,0xfc,0x80,0x99,0x12,0x71,0xb7,0xe1,0xdc,0x7e,0xb3,0x35,0x5, -0xb4,0x1, 0x3, 0xe4,0xe1,0xf0,0x22,0x12,0x58,0x55,0xe4,0x33,0xbe,0xb0,0x1, 0x22, -0x7c,0x7b,0xa5,0xbf,0x0, 0x3, 0xd2,0x86,0x22,0xc2,0x86,0x22,0x7e,0xa3,0x38,0x50, -0x7e,0xb3,0x38,0x51,0xa, 0x2b,0xa, 0x3a,0x2d,0x32,0xb, 0x34,0x7e,0x60,0x1, 0x80, -0x43,0xa5,0xbe,0x0, 0x5, 0xe4,0x11,0x59,0x80,0x38,0xbc,0xa6,0x40,0x18,0xa, 0x26, -0x9, 0xb2,0x1d,0x32,0x19,0xb2,0x24,0x39,0xbe,0xb0,0x23,0x40,0x4, 0x74,0x22,0x11, -0x59,0x11,0x60,0x4, 0x80,0x19,0xa, 0x1a,0xa, 0x26,0x9d,0x21,0x9, 0xb2,0x1d,0x55, -0x11,0x59,0xbe,0xb0,0x24,0x40,0x4, 0x74,0x23,0x11,0x59,0x11,0x60,0x24,0x24,0x7a, -0x29,0xb0,0xb, 0x60,0xbc,0x76,0x38,0xb9,0x22,0xa, 0x26,0x19,0xb2,0x24,0x39,0x22, -0xa, 0x26,0x2e,0x24,0x24,0x39,0x7e,0x29,0xb0,0x22,0xca,0x3b,0x7e,0xb3,0x35,0x5c, -0xb4,0x1, 0x2, 0x80,0x2, 0x21,0x24,0x7e,0x73,0x35,0x5d,0xbe,0x70,0x0, 0x38,0x2, -0x21,0x24,0x12,0x25,0x5d,0x7e,0x8, 0x22,0xb0,0x31,0x32,0x7e,0x64,0x1, 0xef,0x7e, -0x8, 0x1e,0xd0,0x7e,0x34,0x3, 0xde,0x12,0x20,0x12,0x75,0x24,0x0, 0x80,0x56,0x12, -0x62,0xe3,0x12,0x25,0x5d,0x6d,0x33,0x80,0x1c,0x7e,0x35,0x25,0x3e,0x34,0x49,0x33, -0xe, 0x3c,0x31,0x27,0x49,0x23,0x1e,0xd0,0xbd,0x27,0x58,0x4, 0x59,0x73,0x1e,0xd0, -0x7e,0x35,0x25,0xb, 0x34,0x7a,0x35,0x25,0xbe,0x65,0x25,0x38,0xdc,0x6d,0x33,0x7a, -0x35,0x25,0x7e,0x35,0x25,0x31,0x3c,0x31,0x27,0x49,0x23,0x22,0xb0,0xbd,0x27,0x58, -0x4, 0x59,0x73,0x22,0xb0,0x7e,0x35,0x25,0xb, 0x34,0x7a,0x35,0x25,0xbe,0x34,0x0, -0x30,0x78,0xdf,0x5, 0x24,0x7e,0x73,0x35,0x5d,0xbe,0x71,0x24,0x38,0xa1,0x7d,0x36, -0x3e,0x34,0xca,0x39,0x7e,0x18,0x1e,0xd0,0x7e,0x8, 0xe, 0x3c,0x12,0x1f,0xed,0x1b, -0xfd,0x7e,0x34,0x0, 0x60,0xca,0x39,0x7e,0x18,0x22,0xb0,0x7e,0x8, 0x4, 0xd4,0x12, -0x1f,0xed,0x1b,0xfd,0xda,0x3b,0x22,0x12,0x20,0x54,0x7d,0x73,0x7e,0x35,0x25,0x3e, -0x34,0x22,0x7e,0x34,0x0, 0x60,0xe4,0x2, 0x20,0x12,0x2d,0x32,0x3e,0x34,0x49,0x33, -0x4, 0xd4,0x22,0x7e,0x3, 0x33,0x20,0x7e,0x13,0x33,0x21,0x7e,0x23,0x1c,0xe2,0xa, -0x22,0xa, 0x30,0x31,0x3a,0xe, 0x34,0x6c,0x33,0x80,0xc, 0x51,0x53,0x8, 0x6, 0x7a, -0x33,0x32,0xf6,0x80,0x6, 0xb, 0x30,0xbc,0x3, 0x50,0xf0,0x7c,0x30,0x80,0x24,0x51, -0x53,0x58,0x6, 0x7a,0x33,0x32,0xf7,0x80,0x22,0x7e,0x3, 0x1c,0xe1,0xa, 0x40,0x1b, -0x44,0xa, 0x53,0xbd,0x54,0x78,0xa, 0xa, 0x50,0x1b,0x54,0x7c,0xb, 0x7a,0x3, 0x32, -0xf7,0xb, 0x30,0x7e,0x3, 0x1c,0xe1,0xbc,0x3, 0x38,0xd4,0x12,0xb3,0x8b,0xe, 0x34, -0x6c,0x33,0x80,0x10,0x74,0x2, 0xac,0xb3,0x51,0x59,0x8, 0x6, 0x7a,0x33,0x32,0xf8, -0x80,0x6, 0xb, 0x30,0xbc,0x13,0x50,0xec,0x7c,0x31,0x80,0x26,0x74,0x2, 0xac,0xb3, -0x49,0x5, 0x4, 0xd4,0xbd,0x3, 0x58,0x6, 0x7a,0x33,0x32,0xf9,0x80,0x18,0x7d,0x52, -0x1b,0x54,0xa, 0x3, 0xbd,0x5, 0x78,0x8, 0xa, 0x2, 0x1b,0x4, 0x7a,0x13,0x32,0xf9, -0xb, 0x30,0xbc,0x23,0x38,0xd6,0x7e,0xb3,0x33,0x7c,0xb4,0x1, 0x65,0x7e,0xb3,0x32, -0xf6,0xbe,0xb0,0x1, 0x40,0x3, 0x14,0x80,0x1, 0xe4,0x7a,0xb3,0x32,0xf6,0x7e,0xb3, -0x32,0xf7,0xa, 0x4b,0xb, 0x44,0x7e,0xa3,0x1c,0xe1,0xa, 0x3a,0xbd,0x43,0x48,0xc, -0xa, 0x3a,0x1b,0x34,0x7c,0xa7,0x7a,0xa3,0x32,0xf7,0x80,0x5, 0x4, 0x7a,0xb3,0x32, -0xf7,0x7e,0xb3,0x32,0xf8,0xbe,0xb0,0x1, 0x40,0x3, 0x14,0x80,0x1, 0xe4,0x7a,0xb3, -0x32,0xf8,0x7e,0xb3,0x32,0xf9,0xa, 0x3b,0xb, 0x34,0xbd,0x32,0x48,0xf, 0x7e,0xa3, -0x1c,0xe2,0xa, 0x3a,0x1b,0x34,0x7c,0xa7,0x7a,0xa3,0x32,0xf9,0x22,0x4, 0x7a,0xb3, -0x32,0xf9,0x22,0xa, 0x53,0x2d,0x52,0x3e,0x54,0x49,0x55,0x4, 0xd4,0xbd,0x53,0x22, -0x7e,0xa3,0x1a,0xb5,0x4c,0xaa,0x68,0xb, 0x7e,0xb3,0x32,0xf4,0x70,0x8, 0xbe,0xa0, -0x1, 0x28,0x3, 0xe4,0x80,0x7f,0xbe,0xa0,0x1, 0x68,0x2, 0x61,0x49,0x7e,0xb3,0x32, -0xfc,0xbe,0xb0,0x2, 0x40,0x2, 0x61,0x49,0x70,0x23,0x7e,0x73,0x18,0x95,0x7a,0x73, -0x33,0x20,0x7e,0x73,0x18,0x96,0x7a,0x73,0x33,0x21,0x7e,0xb3,0x32,0xff,0x4, 0x7a, -0xb3,0x32,0xff,0x71,0x4a,0x74,0x1, 0x7a,0xb3,0x32,0xfc,0x21,0x43,0x7e,0x73,0x32, -0xf6,0xbe,0x73,0x18,0x95,0x38,0x3c,0x7e,0x73,0x32,0xf7,0xbe,0x73,0x18,0x95,0x40, -0x32,0x7e,0x73,0x32,0xf8,0xbe,0x73,0x18,0x96,0x38,0x28,0x7e,0x73,0x32,0xf9,0xbe, -0x73,0x18,0x96,0x40,0x1e,0x7e,0x37,0x32,0xfa,0xbe,0x37,0x9, 0x2, 0x58,0x2, 0x71, -0x4a,0x31,0x43,0x7e,0xb3,0x32,0xff,0xbe,0xb0,0x14,0x38,0x38,0x4, 0x7a,0xb3,0x32, -0xff,0x80,0x31,0x74,0x2, 0x7a,0xb3,0x32,0xfc,0xe4,0x7a,0xb3,0x32,0xf4,0x6d,0x33, -0x7a,0x37,0x32,0xfa,0x7a,0xb3,0x33,0x7c,0x7a,0xb3,0x32,0xff,0x7e,0x8, 0x33,0x20, -0x7e,0x34,0x0, 0x2, 0x74,0xff,0x12,0x20,0x12,0x7e,0x8, 0x32,0xf6,0x7e,0x34,0x0, -0x4, 0x2, 0x20,0x12,0x7e,0x73,0x32,0xff,0xbe,0x70,0x14,0x40,0x1c,0x7e,0xb3,0x32, -0xf4,0x70,0x16,0x74,0x1, 0x7a,0xb3,0x32,0xf4,0x7e,0x37,0x32,0xfa,0xbe,0x34,0x9, -0xc4,0x58,0x6, 0x74,0x1, 0x7a,0xb3,0x33,0x7c,0x22,0x7e,0x37,0x9, 0x2, 0x7a,0x37, -0x32,0xfa,0x22,0xca,0x3b,0x7e,0xf3,0x1c,0xe6,0x12,0x0, 0x6e,0x40,0x78,0x6d,0x33, -0x9e,0x37,0x1c,0xc1,0x3e,0x34,0xbe,0x37,0x9, 0x0, 0x18,0x6a,0x7e,0xb3,0x16,0xc0, -0x70,0x64,0x7e,0xb3,0x1a,0xd9,0xb4,0x1, 0x4e,0x7e,0x37,0x1c,0xc3,0x7a,0x35,0x26, -0x7e,0x67,0x1c,0xc5,0x6c,0xee,0x80,0x3b,0x7c,0xbe,0xf1,0xad,0x60,0x33,0x71,0xd9, -0xf5,0x24,0x9, 0xb3,0x18,0x96,0xf5,0x25,0x7e,0x70,0x2, 0xac,0xb7,0x49,0x35,0x4, -0xd4,0xbd,0x36,0x48,0xd, 0xe5,0x24,0xa, 0x2b,0xa, 0x3f,0x31,0x3a,0xbe,0x35,0x26, -0x58,0xf, 0x7c,0xbe,0x6c,0x77,0x12,0x28,0xdd,0x71,0xd9,0x9, 0x73,0x18,0x96,0xf1, -0x60,0xb, 0xe0,0xf1,0xc3,0x38,0xc1,0x7e,0xb3,0x1c,0xda,0x70,0x9, 0x7e,0xb3,0x1c, -0xdd,0x70,0x3, 0x12,0xa7,0x4f,0xda,0x3b,0x22,0x7e,0x70,0x2, 0xac,0x7e,0x9, 0xb3, -0x18,0x95,0x22,0xa2,0xa, 0xe4,0x33,0x7a,0xb3,0x35,0x6f,0x7e,0x73,0x35,0x73,0xbe, -0x73,0x1d,0x93,0x68,0x7, 0xe5,0xc, 0x70,0x3, 0x12,0xcd,0x62,0x22,0x12,0xa7,0x38, -0xd1,0xd4,0x71,0x53,0x81,0x6, 0xca,0x3b,0x12,0x27,0x70,0x7e,0xb3,0x1a,0xb5,0x60, -0x6, 0x7e,0xb3,0x33,0xf6,0x60,0x9, 0xe4,0x7a,0xb3,0x33,0xf8,0x7a,0xb3,0x33,0x7d, -0x7e,0xb3,0x33,0xf6,0x70,0x5a,0x6c,0x99,0x80,0x52,0x12,0x2f,0xbd,0x9, 0xf5,0x18, -0x96,0x7c,0xb9,0x12,0xbf,0xa, 0x40,0x42,0x6c,0xee,0x80,0x36,0x74,0x2, 0xac,0xbe, -0x9, 0xd5,0x33,0x7e,0x9, 0xc5,0x33,0x7f,0xa, 0x28,0x12,0xbe,0x93,0x4d,0x33,0x78, -0x1f,0xa, 0x2f,0xa, 0x3c,0x9d,0x32,0x12,0x20,0x54,0x4d,0x33,0x78,0x12,0x7c,0xb9, -0x91,0xa3,0xbe,0x34,0x3, 0x20,0x58,0x8, 0xf1,0x59,0x7c,0xb8,0x7c,0x7f,0xf1,0x60, -0xb, 0xe0,0x7e,0x73,0x33,0xf8,0xbc,0x7e,0x38,0xc2,0xb, 0x90,0xf1,0xca,0x38,0xaa, -0x7e,0x73,0x33,0x7d,0x7a,0x73,0x33,0xf8,0xa, 0x37,0x3e,0x34,0xca,0x39,0x7e,0x18, -0x33,0xba,0x7e,0x8, 0x33,0x7e,0x12,0x1f,0xed,0x1b,0xfd,0xe4,0x7a,0xb3,0x33,0xf6, -0xda,0x3b,0x22,0x7c,0x7b,0x74,0x2, 0xac,0x7b,0x9, 0xb3,0x18,0x95,0x9, 0x73,0x18, -0x96,0x2, 0x2b,0x76,0xca,0x79,0x7e,0x73,0x1c,0xe0,0x7e,0x47,0x1a,0xca,0xe4,0x7a, -0xb3,0x1a,0xd7,0x7a,0xb3,0x36,0x4b,0x7e,0x63,0x18,0x8b,0xbe,0x60,0x0, 0x28,0x4f, -0x7e,0x63,0x1a,0xb6,0xbe,0x60,0x0, 0x28,0x46,0x6c,0xff,0x80,0x3e,0x74,0x2, 0xac, -0xbf,0x9, 0x55,0x19,0x67,0x9, 0xe5,0x19,0x68,0x74,0x2, 0xac,0xbe,0x49,0x15,0x4, -0xd4,0x6d,0x55,0x9e,0x57,0x1c,0xc5,0xbd,0x15,0x58,0x1e,0xa, 0x15,0xa, 0x57,0x2d, -0x51,0x3e,0x54,0x49,0x15,0x4, 0xd4,0x6d,0x55,0x9e,0x57,0x1c,0xc3,0xbd,0x15,0x58, -0x8, 0x74,0x1, 0x7a,0xb3,0x1a,0xd7,0x80,0x6, 0xb, 0xf0,0xbc,0x6f,0x38,0xbe,0xe4, -0x7a,0xb3,0x1a,0xd8,0x7e,0xb3,0x18,0x1e,0x70,0x3e,0xf1,0xd9,0x28,0x3a,0x6c,0xff, -0x80,0x32,0x74,0x2, 0xac,0xbf,0x9, 0xe5,0x18,0x96,0x74,0x2, 0xac,0xbe,0x49,0x25, -0x5, 0x3e,0x6d,0x55,0x9d,0x54,0xbd,0x25,0x58,0x18,0x74,0x1, 0x7a,0xb3,0x1a,0xd8, -0x7e,0x57,0x36,0x31,0xbe,0x54,0xb, 0xb8,0x50,0xe, 0x74,0x16,0x7a,0xb3,0x36,0x4b, -0x80,0x6, 0xb, 0xf0,0xbc,0x7f,0x38,0xca,0x12,0xb4,0x67,0xe4,0x7a,0xb3,0x1a,0xda, -0x7e,0x37,0x1a,0xb9,0x2e,0x37,0x1a,0xb7,0xbe,0x37,0x1a,0xd0,0x28,0x6, 0x74,0x1, -0x7a,0xb3,0x1a,0xda,0x74,0x1, 0x7a,0xb3,0x1a,0xdb,0x6c,0xff,0x80,0x1e,0xb1,0xc3, -0x49,0x25,0x16,0xca,0x7d,0x43,0x9d,0x42,0x7d,0x34,0x12,0x20,0x54,0xbe,0x37,0x1a, -0xce,0x8, 0x7, 0xe4,0x7a,0xb3,0x1a,0xdb,0x80,0x6, 0xb, 0xf0,0xb1,0xcc,0x38,0xde, -0x6c,0xff,0x80,0x8, 0xb1,0xc3,0x59,0x35,0x16,0xca,0xb, 0xf0,0xb1,0xcc,0x38,0xf4, -0xda,0x79,0x22,0x7c,0xbf,0x91,0xa3,0x74,0x2, 0xac,0xbf,0x22,0x7e,0x73,0x1a,0xb5, -0xbc,0x7f,0x22,0xca,0x3b,0x7e,0xa3,0x1a,0xb5,0xbe,0xa0,0x0, 0x38,0x2, 0xc1,0x8e, -0x7e,0xb3,0x0, 0x6f,0x70,0x36,0x7a,0xa3,0x0, 0x6f,0xe4,0x7a,0xb3,0x0, 0x71,0x6c, -0xff,0x80,0x23,0xd1,0x98,0x74,0x2, 0xac,0xbf,0x9, 0xc5,0x18,0x95,0x9, 0xd5,0x18, -0x96,0x7a,0x49,0xc0,0x19,0xd4,0x0, 0x1, 0x74,0x1, 0x19,0xb4,0x0, 0x8, 0xd1,0xa2, -0x59,0x34,0x0, 0x2, 0xb, 0xf0,0xb1,0xcc,0x38,0xd9,0x80,0x77,0x7e,0xe3,0x0, 0x6f, -0x6c,0xff,0x80,0x2e,0xd1,0x98,0x7e,0x49,0xc0,0x9, 0xd4,0x0, 0x1, 0x9, 0xb4,0x0, -0x8, 0x70,0x4, 0x1b,0xe0,0x80,0x19,0xd1,0xa2,0x7d,0x23,0x49,0x34,0x0, 0x2, 0xf1, -0xe1,0xbe,0xf4,0x0, 0x23,0x8, 0x9, 0x74,0x5, 0x19,0xb4,0x0, 0x8, 0x75,0x69,0x1, -0xb, 0xf0,0xbc,0xef,0x38,0xce,0x4c,0xee,0x78,0x2, 0x80,0x25,0x7e,0x73,0x0, 0x71, -0xbe,0x70,0x4, 0x40,0x20,0x6c,0xff,0x80,0xd, 0xd1,0x98,0x9, 0xb4,0x0, 0x8, 0xbe, -0xb0,0x5, 0x68,0x6, 0xb, 0xf0,0xbc,0xef,0x38,0xef,0xbc,0xef,0x78,0x3, 0x75,0x69, -0x0, 0xd1,0xa9,0x80,0xe, 0x7c,0xb7,0x4, 0x7a,0xb3,0x0, 0x71,0x80,0x5, 0xd1,0xa9, -0x75,0x69,0x0, 0xe5,0x69,0xda,0x3b,0x22,0x7e,0x90,0x9, 0xac,0x9f,0x2e,0x44,0x0, -0x72,0x22,0x7c,0xbc,0x7c,0x7d,0x2, 0x2b,0x76,0xe4,0x7a,0xb3,0x0, 0x70,0x7a,0xb3, -0x0, 0x6f,0x7a,0xb3,0x0, 0x71,0x22,0x6c,0x99,0x80,0xe, 0x7c,0xb9,0x91,0xa3,0xbe, -0x37,0x1c,0xce,0x58,0x2, 0xf1,0x59,0xb, 0x90,0x7e,0x83,0x1a,0xb5,0xbc,0x89,0x38, -0xea,0x2, 0x27,0x70,0x7e,0xd7,0x1c,0xce,0xf1,0x7f,0x7d,0xc3,0x3e,0x34,0x3e,0x34, -0x7e,0x44,0x0, 0xa, 0x7d,0x24,0x12,0x1d,0x4a,0x7e,0xa3,0x1a,0xd9,0x4c,0xaa,0x68, -0x13,0x7e,0x27,0x33,0xf9,0xbd,0x2c,0x48,0xb, 0x7d,0x32,0x3e,0x34,0x3e,0x34,0x7d, -0x24,0x12,0x1d,0x4a,0xbe,0xc4,0x2, 0x58,0x8, 0x8, 0x4c,0xaa,0x68,0x4, 0x74,0xa, -0x80,0x11,0x4c,0xaa,0x68,0xc, 0x7e,0xb3,0x33,0xf7,0xbe,0xb0,0x0, 0x28,0x8, 0x14, -0x80,0x1, 0xe4,0x7a,0xb3,0x33,0xf7,0x7e,0x27,0x1c,0xce,0x7d,0x12,0x3e,0x14,0x7e, -0x13,0x33,0xf7,0xbe,0x10,0x0, 0x28,0x12,0xbd,0x13,0x58,0x4, 0x7d,0x31,0x80,0x6, -0xbd,0x23,0x8, 0x2, 0x7d,0x32,0x7a,0x37,0x1c,0xce,0xf1,0xd1,0x28,0x2, 0xd1,0xb7, -0x7a,0xc7,0x33,0xf9,0x7a,0xd7,0x1c,0xce,0x22,0x7c,0xb9,0x6c,0x77,0x2, 0x28,0xdd, -0x7c,0x57,0x7c,0x7b,0x7e,0xb3,0x33,0x7d,0x7e,0x60,0x2, 0xac,0xb6,0x19,0x75,0x33, -0xba,0x19,0x55,0x33,0xbb,0x7e,0xb3,0x33,0x7d,0x4, 0x7a,0xb3,0x33,0x7d,0x22,0xca, -0x3b,0x6d,0x44,0x7e,0xf3,0x1a,0xb5,0x6c,0xee,0x80,0x19,0x7c,0xbe,0xf1,0xad,0x60, -0x11,0x12,0xcf,0x1f,0x9, 0xc5,0x18,0x96,0x7c,0xbd,0xf1,0xe9,0xbd,0x4f,0x58,0x2, -0x7d,0x4f,0xb, 0xe0,0xbc,0xfe,0x38,0xe3,0x7d,0x34,0xda,0x3b,0x22,0x7c,0x5b,0xc4, -0x23,0x54,0x1f,0xa, 0x3b,0x9, 0x43,0x19,0xa3,0x7c,0xb5,0xf1,0xf1,0x12,0x66,0x2d, -0x5c,0xb4,0x22,0x7e,0x73,0x1a,0xb5,0xbc,0x7e,0x22,0x7e,0x73,0x1a,0xb5,0xbc,0x79, -0x22,0x7e,0x73,0x1a,0xb5,0xbe,0x70,0x1, 0x22,0x7e,0x73,0x1a,0xb5,0xbe,0x70,0x0, -0x22,0x9d,0x32,0x12,0x20,0x54,0x7d,0xf3,0x22,0x7c,0x7c,0x12,0x2b,0x76,0x7d,0xf3, -0x22,0x54,0x7, 0xa, 0x3b,0x2e,0x34,0x0, 0x4e,0x22,0xca,0xd8,0xca,0x79,0x7c,0xfb, -0xbe,0xf0,0x80,0x78,0x16,0x7e,0xd0,0xff,0x6c,0xee,0x11,0x5b,0x38,0x4, 0x7c,0xd7, -0x7c,0xfe,0xb, 0xe0,0xbe,0xe0,0x4, 0x78,0xf1,0x80,0x18,0xbe,0xf0,0x81,0x78,0x13, -0x6c,0xdd,0x6c,0xee,0x11,0x5b,0x40,0x4, 0x7c,0xd7,0x7c,0xfe,0xb, 0xe0,0xbe,0xe0, -0x4, 0x78,0xf1,0xbe,0xf0,0x4, 0x40,0x2, 0x6c,0xff,0x7c,0xbf,0x11,0x66,0x12,0xce, -0xe1,0x12,0xce,0xea,0x12,0xce,0xf3,0x7e,0x73,0x1d,0x93,0x7a,0x73,0x35,0x73,0x12, -0xcd,0x82,0x7a,0xf3,0x35,0x4b,0xda,0x79,0xda,0xd8,0x22,0x74,0x5, 0xac,0xbe,0x9, -0x75,0x17,0xce,0xbc,0x7d,0x22,0xca,0x79,0x7c,0xfb,0x74,0x5, 0xac,0xfb,0x9, 0x77, -0x17,0xce,0x7a,0x73,0x1d,0x93,0x9, 0x77,0x17,0xcf,0x7a,0x73,0x1d,0x98,0x9, 0x77, -0x17,0xd0,0x7a,0x73,0x1d,0xa3,0x9, 0x77,0x17,0xd1,0x7a,0x73,0x1d,0xa4,0x31,0x26, -0x9, 0xb7,0x17,0xd2,0x71,0x6d,0x7e,0xb3,0x1d,0x93,0x12,0x23,0xd7,0xe4,0x7a,0xb3, -0x16,0xbf,0x7a,0xb3,0x34,0x73,0xda,0x79,0x22,0x7e,0xb3,0x33,0xfd,0x60,0x6, 0x14, -0x7a,0xb3,0x33,0xfd,0x22,0x7e,0xb3,0x34,0xec,0x70,0xc, 0x7e,0xb3,0x36,0x55,0xb4, -0x1, 0x5, 0xe4,0x11,0x66,0xf1,0xf2,0x11,0xf2,0x12,0xad,0xfe,0x7c,0xab,0x7e,0xb3, -0x36,0x55,0x70,0xc, 0x7e,0xb3,0x34,0xec,0xb4,0x1, 0x5, 0xe4,0x7a,0xb3,0x1e,0x84, -0x7e,0xb3,0x34,0xec,0x7a,0xb3,0x36,0x55,0xbe,0xa0,0xff,0x68,0x4, 0x7c,0xba,0x1, -0x66,0x22,0xf1,0xb, 0x1, 0xf6,0x7e,0x73,0x34,0xe6,0xa, 0x37,0x12,0x45,0x82,0x7e, -0xb3,0x34,0x0, 0x60,0x6, 0x74,0x1, 0x7a,0xb3,0x34,0x8, 0x7e,0xb3,0x34,0x8, 0xb4, -0x1, 0xa, 0x74,0x3, 0x7a,0xb3,0x2e,0x8e,0x3e,0x34,0x80,0x5, 0xe4,0x7a,0xb3,0x2e, -0x8e,0x7a,0x37,0x1c,0xd4,0x22,0x31,0x2d,0x7a,0x37,0x1d,0x9f,0x22,0xca,0x79,0x7e, -0x23,0x1d,0x93,0x7e,0x33,0x35,0x72,0xac,0x23,0x12,0x69,0xd5,0x50,0x4, 0x7e,0x14, -0x0, 0xa, 0x7e,0xe3,0x1d,0x94,0xbe,0x14,0xb, 0xb8,0x40,0x4, 0x7e,0x14,0xb, 0xb8, -0xbe,0x14,0x9, 0x60,0x28,0x3, 0xe4,0x80,0x16,0xbe,0x14,0x5, 0xdc,0x40,0x4, 0x74, -0x3, 0x80,0xc, 0xbe,0x14,0x2, 0xee,0x40,0x4, 0x74,0x1, 0x80,0x2, 0x74,0x2, 0x7a, -0xb3,0x1d,0x94,0x7e,0xf3,0x1d,0x94,0xbe,0xf0,0x3, 0x78,0x5, 0x12,0x69,0xeb,0x80, -0x2, 0x74,0x20,0x7a,0xb3,0x1d,0x95,0xbc,0xfe,0x68,0x2, 0xd2,0xc, 0x7e,0x24,0x1, -0xf4,0x7d,0x31,0x8d,0x32,0x7c,0x17,0xbe,0x10,0x7, 0x28,0x3, 0x7e,0x10,0x7, 0x7e, -0x1f,0x3, 0xd9,0x69,0x51,0x0, 0xa0,0x54,0x1f,0xa, 0x1, 0x3e,0x4, 0x3e,0x4, 0x3e, -0x4, 0x3e,0x4, 0x3e,0x4, 0x2d,0x5, 0x79,0x1, 0x0, 0xa0,0x12,0x69,0xde,0xda,0x79, -0x22,0x7c,0x7b,0x7a,0x73,0x1d,0x93,0x31,0x26,0x30,0xc, 0x5, 0x71,0x86,0x12,0x0, -0xa, 0xa2,0x3, 0xe4,0x33,0xb4,0x1, 0xa, 0x12,0xaf,0xab,0x7e,0xb3,0x1d,0x93,0x2, -0x23,0xd7,0x22,0xca,0x79,0x7e,0xa3,0x38,0x50,0x7e,0xf3,0x38,0x51,0x7e,0xb3,0x1c, -0xe6,0xbc,0xbf,0x28,0x4, 0x7c,0xeb,0x80,0x2, 0x7c,0xef,0x7a,0xa3,0x1c,0xdf,0x7a, -0xf3,0x1c,0xe0,0x7a,0xa3,0x1c,0xe3,0x7a,0xf3,0x1c,0xe4,0x7a,0xa3,0x1c,0xe5,0x7a, -0xf3,0x1c,0xe6,0xe4,0x7a,0xb3,0x1c,0xe9,0x7a,0xa3,0x1c,0xe1,0x7a,0xf3,0x1c,0xe2, -0x7e,0xb3,0x38,0x99,0x7a,0xb3,0x1c,0xea,0x7e,0xb3,0x38,0x9c,0x7a,0xb3,0x1c,0xeb, -0xa, 0x3a,0xca,0x39,0x7e,0x18,0x38,0x52,0x7e,0x8, 0x1c,0xec,0x12,0x1f,0xed,0x1b, -0xfd,0xa, 0x3e,0xca,0x39,0x7e,0x18,0x38,0x75,0x7e,0x8, 0x1d,0xf, 0x12,0x1f,0xed, -0x1b,0xfd,0x7e,0x34,0x0, 0x23,0xca,0x39,0x7e,0x18,0x38,0xe0,0x7e,0x8, 0x1d,0xa5, -0x12,0x1f,0xed,0x1b,0xfd,0x12,0xaf,0x19,0x12,0x6c,0x34,0x12,0x68,0x5f,0x74,0x1, -0x12,0x36,0xb3,0xe4,0x7a,0xb3,0x1d,0x83,0x7a,0xb3,0x1d,0x84,0x12,0x6a,0x10,0x7a, -0x1f,0x1d,0x8f,0x74,0x3, 0x7a,0xb3,0x1d,0x85,0xe4,0x7a,0xb3,0x1d,0x86,0x74,0x2, -0x7a,0xb3,0x1d,0x87,0x7e,0x34,0x0, 0xb4,0x7a,0x37,0x1d,0x89,0x74,0x4, 0x7a,0xb3, -0x1d,0x88,0x7e,0x34,0x0, 0xf, 0x7a,0x37,0x1d,0x8b,0x7e,0x34,0x20,0x5f,0x7a,0x37, -0x1d,0x8d,0x74,0x20,0x7a,0xb3,0x1d,0xee,0x74,0x1, 0x7a,0xb3,0x1d,0x94,0x74,0x20, -0x7a,0xb3,0x1d,0x95,0x74,0x4, 0x7a,0xb3,0x1d,0x97,0x74,0x2a,0x7a,0xb3,0x1d,0x93, -0x31,0x26,0xe4,0x7a,0xb3,0x1d,0xa1,0x7a,0xb3,0x1d,0xa2,0x7e,0x34,0x1, 0xf4,0x7a, -0x37,0x1d,0x9d,0x74,0x1, 0x7a,0xb3,0x1d,0x96,0x12,0xce,0xda,0x74,0x27,0x7a,0xb3, -0x1d,0xa3,0x6d,0x33,0x7a,0x37,0x1d,0x99,0x7a,0x37,0x1d,0x9b,0xe4,0x7a,0xb3,0x1d, -0x98,0x7e,0x24,0x0, 0x30,0x7a,0x27,0x1d,0xf6,0x74,0x3, 0x7a,0xb3,0x1d,0xf3,0x7a, -0x37,0x1d,0xf4,0xe4,0x7a,0xb3,0x1d,0xf2,0x7e,0x34,0x4, 0x2d,0x7a,0x37,0x1d,0xf8, -0x7a,0xb3,0x1d,0xef,0x7a,0xb3,0x1d,0xf0,0x7a,0xb3,0x1d,0xf1,0x74,0x1, 0x7a,0xb3, -0x1d,0xec,0xe4,0x7a,0xb3,0x1d,0xed,0x7e,0x34,0x1f,0x99,0x7a,0x37,0x1d,0xfa,0x74, -0x18,0x7a,0xb3,0x1d,0xfc,0x7e,0x34,0x1f,0xb1,0x7a,0x37,0x1e,0xe, 0x74,0x6, 0x7a, -0xb3,0x1e,0x10,0x74,0x1, 0x7a,0xb3,0x1e,0x11,0xa, 0x3f,0xca,0x39,0x7e,0x18,0x39, -0x3, 0x7e,0x8, 0x1d,0xc8,0x12,0x1f,0xed,0x1b,0xfd,0xda,0x79,0x22,0x7c,0x6b,0x7e, -0x73,0x1d,0xee,0xbc,0x76,0x68,0x6, 0x7a,0x63,0x1d,0xee,0xd2,0xc, 0x30,0xc, 0x5, -0x71,0x86,0x2, 0x0, 0xa, 0x22,0xc2,0xc, 0x7e,0x8, 0x1c,0xdf,0x12,0x11,0x1d,0x7e, -0x8, 0x1c,0xdf,0xe4,0x22,0x12,0x68,0xa9,0x31,0xe3,0x12,0x0, 0x49,0x12,0xce,0x78, -0x7a,0x1f,0x6, 0x80,0x7e,0xf, 0x6, 0x80,0x7e,0x1f,0x6, 0x7c,0x12,0x6c,0xa1,0x7e, -0x18,0x9, 0x14,0x7a,0x1f,0x13,0x64,0x7e,0x18,0xe, 0x3c,0x7a,0x1f,0x13,0x68,0x7e, -0xf, 0x13,0x68,0x7e,0x1f,0x13,0x64,0xd1,0xa2,0xd1,0x2f,0x12,0x67,0xee,0x12,0x6c, -0x0, 0xd1,0x80,0x12,0x71,0x5, 0x61,0xd8,0xe4,0x7a,0xb3,0x32,0x10,0x7a,0xb3,0x32, -0xf, 0x7e,0x8, 0x32,0x34,0x12,0xa1,0xd8,0x7e,0x8, 0x32,0x12,0x7e,0x34,0x0, 0x21, -0x12,0x20,0x12,0x7e,0x8, 0x31,0xe5,0x7e,0x34,0x0, 0x28,0x12,0x20,0x12,0x7e,0x8, -0x31,0xa3,0x7e,0x34,0x0, 0x42,0x2, 0x20,0x12,0xca,0xf8,0x7c,0xfb,0x7e,0x73,0x32, -0x10,0xa5,0xbf,0x0, 0x1f,0x7e,0x63,0x1a,0xbd,0xa, 0x27,0x19,0x62,0x32,0x34,0x7e, -0x47,0x1a,0xbb,0x7e,0xb3,0x32,0x10,0x7e,0x60,0x2, 0xac,0xb6,0x59,0x45,0x31,0xe5, -0x74,0x1, 0x80,0x2d,0x7e,0xb3,0x1a,0xbd,0x7e,0x8, 0x32,0x34,0xb1,0x57,0x70,0x25, -0x7e,0x73,0x1a,0xbd,0x7e,0x63,0x32,0x10,0xa, 0x26,0x19,0x72,0x32,0x34,0x7e,0x47, -0x1a,0xbb,0x7e,0x73,0x32,0x10,0x74,0x2, 0xac,0xb7,0x59,0x45,0x31,0xe5,0x7c,0xb7, -0x4, 0x7a,0xb3,0x32,0x10,0x7e,0x73,0x32,0xf, 0xa5,0xbf,0x0, 0x1f,0x7e,0x63,0x1a, -0xbe,0xa, 0x27,0x19,0x62,0x32,0x12,0x7e,0x47,0x1a,0xbb,0x7e,0xb3,0x32,0xf, 0x7e, -0x60,0x2, 0xac,0xb6,0x59,0x45,0x31,0xa3,0x74,0x1, 0x80,0x2d,0x7e,0xb3,0x1a,0xbe, -0x7e,0x8, 0x32,0x12,0xb1,0x57,0x70,0x25,0x7e,0x73,0x1a,0xbe,0x7e,0x63,0x32,0xf, -0xa, 0x26,0x19,0x72,0x32,0x12,0x7e,0x47,0x1a,0xbb,0x7e,0x73,0x32,0xf, 0x74,0x2, -0xac,0xb7,0x59,0x45,0x31,0xa3,0x7c,0xb7,0x4, 0x7a,0xb3,0x32,0xf, 0x7e,0xb3,0x32, -0x10,0xbc,0xbf,0x40,0x4, 0xb1,0xc, 0x40,0x39,0x7e,0xb3,0x32,0xf, 0xbc,0xbf,0x40, -0x8, 0x7e,0x8, 0x31,0xa3,0xb1,0x10,0x40,0x29,0x7e,0x50,0x3, 0xac,0x5f,0xe, 0x24, -0x7e,0x73,0x32,0xf, 0xa, 0x17,0x7e,0xb3,0x32,0x10,0xa, 0x3b,0x2d,0x31,0xbd,0x32, -0x48,0x16,0xb1,0xc, 0x50,0x12,0x7e,0x8, 0x31,0xa3,0x7e,0xb3,0x32,0xf, 0xb1,0x10, -0x50,0x6, 0x71,0xd8,0x74,0x1, 0x80,0x1, 0xe4,0xda,0xf8,0x22,0x7e,0x8, 0x31,0xe5, -0x7c,0x9b,0x7e,0x34,0x7f,0xff,0x7e,0xf4,0x0, 0x1, 0x7e,0x80,0x1, 0x80,0x19,0x74, -0x2, 0xac,0xb8,0x7f,0x60,0x2d,0xd5,0xb, 0x6a,0x20,0xbd,0x23,0x58,0x2, 0x7d,0x32, -0xbd,0x2f,0x8, 0x2, 0x7d,0xf2,0xb, 0x80,0xbc,0x98,0x38,0xe3,0x1a,0x26,0x1a,0x24, -0x7e,0x14,0x0, 0x64,0x12,0x1d,0x8d,0x12,0x2f,0xb6,0x12,0x1d,0xe9,0xbe,0x18,0x0, -0x50,0x8, 0x2, 0xd3,0x22,0xc3,0x22,0x7c,0xa7,0x7f,0x70,0x7c,0x1b,0x6c,0x0, 0x80, -0x12,0xa, 0x10,0x7f,0x17,0x2d,0x31,0x7e,0x1b,0xb0,0xbc,0xb1,0x78,0x3, 0x74,0x1, -0x22,0xb, 0x0, 0xbc,0xa0,0x38,0xea,0xe4,0x22,0xca,0x3b,0x7c,0xfb,0x7d,0xb3,0x6c, -0xdd,0x6c,0xee,0x7e,0xb3,0x1a,0xb5,0x70,0xf, 0x71,0xd8,0x7e,0xb3,0x32,0x33,0x60, -0x16,0x14,0x7a,0xb3,0x32,0x33,0x80,0xf, 0x7e,0x34,0x1, 0x90,0x7e,0x14,0x3, 0xe8, -0x7d,0x21,0x12,0xb2,0xdc,0x7c,0xdb,0x7e,0xb3,0x1c,0xda,0xb4,0x1, 0x79,0x7e,0xb3, -0x1c,0xdb,0x70,0x38,0xbe,0xd0,0x0, 0x28,0x73,0x7e,0xb3,0x32,0x33,0x60,0x7, 0x14, -0x7a,0xb3,0x32,0x33,0x80,0x66,0xbe,0xd0,0x4, 0x78,0x2, 0x80,0xc, 0xbe,0xd0,0x3, -0x78,0x2, 0x80,0x5, 0xbe,0xd0,0x2, 0x78,0x5, 0x7e,0xc0,0x6, 0x80,0x3, 0x7e,0xc0, -0x8, 0x7c,0xbc,0x91,0x9, 0xb4,0x1, 0x44,0x74,0x2, 0x80,0x3c,0xbe,0xd0,0x0, 0x28, -0xc, 0x74,0x2, 0x7a,0xb3,0x1c,0xdb,0x7a,0xb7,0x32,0xd, 0x80,0x1d,0x7e,0xb3,0x1a, -0xb5,0x60,0xc, 0x7e,0xb3,0x18,0x20,0x60,0x6, 0x7e,0xb3,0x18,0x1f,0x70,0x8, 0x74, -0x1, 0x7a,0xb3,0x1c,0xdb,0x80,0x3, 0x7e,0xe0,0x1, 0xbe,0xe0,0x1, 0x68,0x5, 0xbe, -0xf0,0x1, 0x78,0x8, 0xe4,0x80,0x1, 0xe4,0x7a,0xb3,0x1c,0xdb,0xda,0x3b,0x22,0xc1, -0x31,0x7e,0x34,0x0, 0xc8,0x7a,0x37,0x1a,0xc6,0x7e,0x34,0x1, 0x2c,0x7a,0x37,0x1a, -0xca,0x7e,0x34,0x0, 0x64,0x7a,0x37,0x1a,0xc8,0x7e,0x34,0x0, 0x96,0x7a,0x37,0x1a, -0xcc,0x7e,0x34,0x0, 0x50,0x7a,0x37,0x1a,0xce,0x7e,0x34,0x0, 0x3d,0x7a,0x37,0x1a, -0xd0,0x12,0xcf,0x31,0x7a,0x37,0x1a,0xd4,0x74,0x1, 0x7a,0xb3,0x1a,0xd6,0xe4,0x7a, -0xb3,0x1a,0xd9,0x7e,0x73,0x38,0xa2,0x3e,0x34,0x7e,0x8, 0x16,0xca,0x2, 0x20,0x12, -0x7e,0x8, 0x1a,0xdf,0x7e,0x34,0x1, 0xe, 0x74,0xff,0x12,0x20,0x12,0x12,0xa4,0x3b, -0x7e,0x8, 0x1b,0xed,0xd1,0xd3,0x7e,0x8, 0x1c,0x47,0x7e,0x34,0x0, 0xd, 0xe4,0x2, -0x20,0x12,0x7f,0x71,0x7f,0x60,0x7e,0xb3,0x1c,0xdf,0x7e,0x73,0x1c,0xe0,0xac,0xb7, -0x7d,0xb5,0x3e,0xb4,0x7f,0x7, 0x7d,0x3b,0xe4,0x12,0x20,0x12,0x7f,0x6, 0x7d,0x3b, -0x12,0x20,0x12,0x7a,0xb3,0x16,0xbf,0xc1,0xc9,0x7e,0x8, 0x17,0xba,0x12,0xcd,0xd4, -0x2, 0x20,0x12,0x7f,0x70,0x6c,0x77,0x74,0x3, 0xa, 0x27,0x7f,0x7, 0x2d,0x12,0x7a, -0xb, 0xb0,0x7f,0x7, 0x2d,0x12,0x39,0xb0,0x0, 0xa, 0x7e,0x44,0x7f,0xff,0xf1,0x2, -0x79,0x40,0x0, 0x14,0xf1,0x2, 0x79,0x40,0x0, 0x28,0xb, 0x70,0xbe,0x70,0xa, 0x40, -0xd6,0x22,0x74,0x2, 0xac,0xb7,0x7f,0x7, 0x2d,0x15,0x22,0x7e,0x27,0x3, 0xf6,0xbe, -0x24,0x0, 0x64,0x28,0x7, 0xe4,0x7a,0xb3,0x33,0xfe,0xf1,0xeb,0xbe,0x24,0x0, 0xc8, -0x28,0x7, 0xe4,0x7a,0xb3,0x33,0xfe,0xf1,0x80,0x7e,0x37,0x34,0x6, 0xbd,0x32,0x50, -0x4, 0x7a,0x27,0x34,0x6, 0x12,0xaf,0x11,0x38,0xa, 0x12,0xaf,0x9, 0x38,0x5, 0x12, -0xaf,0x1, 0x28,0x32,0xf1,0x87,0xbe,0x24,0x0, 0x32,0x50,0x20,0x7e,0xb3,0x33,0xfe, -0x4, 0x7a,0xb3,0x33,0xfe,0x7e,0x73,0x33,0xfe,0xbe,0x70,0x32,0x28,0x13,0x74,0x32, -0x7a,0xb3,0x33,0xfe,0xf1,0xf2,0x7a,0xb3,0x34,0x73,0x80,0x5, 0xe4,0x7a,0xb3,0x33, -0xfe,0x7d,0x32,0x2, 0xad,0x19,0xe1,0x78,0xf1,0xe1,0xe4,0x7a,0xb3,0x34,0xc, 0x22, -0x74,0x2, 0x7a,0xb3,0x34,0x0, 0x22,0x7e,0xb3,0x34,0xc, 0xb4,0x1, 0x2, 0xe1,0x80, -0x7e,0xb3,0x34,0x72,0x4, 0x7a,0xb3,0x34,0x72,0x7e,0xb3,0x34,0x0, 0xb4,0x2, 0x1f, -0x12,0xce,0xc6,0x7e,0x37,0x3, 0xf6,0xbe,0x34,0x1, 0x2c,0x28,0x3, 0x12,0xce,0xc6, -0x7e,0xb3,0x34,0x71,0xb4,0x1, 0x6, 0x74,0x1, 0x7a,0xb3,0x34,0x72,0xf1,0xeb,0x7e, -0x73,0x34,0x71,0xbe,0x70,0x3, 0x40,0xd, 0x74,0x1, 0x7a,0xb3,0x34,0xc, 0xf1,0x80, -0x12,0xb0,0x87,0xf1,0xe1,0x7e,0x73,0x34,0x72,0xbe,0x70,0xa, 0x28,0x2, 0xe1,0xe1, -0x22,0xe4,0x7a,0xb3,0x34,0x72,0x7a,0xb3,0x34,0x71,0x22,0x74,0x1, 0x7a,0xb3,0x34, -0x0, 0x22,0xe4,0x7a,0xb3,0x34,0x0, 0x7a,0xb3,0x34,0x8, 0x22,0x7e,0x8, 0x36,0x39, -0x11,0x18,0x7e,0xb3,0x1c,0xdb,0x60,0x6, 0x7e,0x8, 0x32,0xd, 0x11,0x18,0x11,0x2f, -0x1, 0x12,0x7e,0x8, 0x36,0x2d,0x1, 0x18,0x7f,0x70,0xb, 0x7a,0x30,0xe5,0x6b,0xa, -0x2b,0xbd,0x32,0x28,0x4, 0x9d,0x32,0x80,0x2, 0x6d,0x33,0x1b,0x7a,0x30,0x22,0x7e, -0x8, 0x2a,0x5c,0x1, 0x18,0x7e,0x73,0x1a,0xc4,0x7a,0x73,0x1a,0xc5,0x7e,0x73,0x31, -0xa2,0xa, 0x27,0x7e,0x73,0x1c,0x47,0xa, 0x37,0x2d,0x32,0x7a,0x73,0x1c,0x48,0xe4, -0x7a,0xb3,0x1c,0x4b,0x22,0xc2,0x3, 0x7e,0xb3,0x16,0xbf,0x60,0x6, 0x7e,0xb3,0x16, -0xbe,0x70,0x7, 0x12,0x4f,0xd1,0x28,0x2, 0xd2,0x3, 0xa2,0x3, 0x22,0x12,0x71,0xac, -0x50,0xfb,0x12,0xce,0x1c,0x11,0x84,0x7a,0x37,0x36,0x31,0x12,0x0, 0x64,0x12,0xf, -0xf5,0x2, 0x24,0xb9,0x6d,0x33,0x7a,0x37,0x36,0x4c,0x22,0x7e,0xb3,0x35,0x6, 0x14, -0x68,0x57,0x14,0x78,0x2, 0x21,0x21,0x14,0x68,0x65,0x24,0x3, 0x78,0x7c,0x31,0x2d, -0x38,0xb, 0xa2,0x10,0xe4,0x33,0xb4,0x1, 0xd, 0xf1,0xc9,0x68,0x9, 0x11,0x84,0xe4, -0x7a,0xb3,0x36,0x4e,0x80,0x6b,0x7e,0xb3,0x34,0xe7,0x30,0xe0,0x64,0x7e,0x73,0x34, -0xe8,0xa, 0x27,0x7e,0x34,0x4, 0x0, 0xad,0x32,0x7e,0xb3,0x35,0x31,0xb4,0x1, 0x8, -0x7e,0x37,0x3a,0x86,0x2e,0x34,0x4, 0x0, 0xbe,0x37,0x36,0x4c,0x50,0x43,0x11,0x84, -0x31,0x26,0xe4,0x7a,0xb3,0x36,0x50,0x80,0x38,0x31,0x2d,0x28,0x2f,0xe4,0x7a,0xb3, -0x35,0x6, 0x7e,0xb3,0x36,0x4e,0xb4,0x1, 0x2, 0x31,0x26,0xd2,0x19,0x80,0x1d,0x74, -0xff,0x7a,0xb3,0x34,0xe0,0x31,0x35,0x12,0x3e,0xe3,0x12,0x24,0x95,0xe4,0x7a,0xb3, -0x35,0x6, 0x7a,0xb3,0x36,0x36,0xd2,0x19,0x80,0x7, 0x31,0x26,0xe4,0x7a,0xb3,0x36, -0x36,0x31,0x5a,0x2, 0x3d,0x3b,0x74,0x1, 0x7a,0xb3,0x35,0x6, 0x22,0x7e,0x73,0x1c, -0x47,0xbe,0x70,0x0, 0x22,0x7e,0x34,0x0, 0xc8,0x2, 0x62,0xe7,0x11,0x8b,0x7e,0x73, -0x34,0xe0,0xbe,0x70,0xff,0x68,0x12,0xbe,0x73,0x35,0x6, 0x68,0xc, 0x7a,0x73,0x35, -0x6, 0x74,0xff,0x7a,0xb3,0x34,0xe0,0x1, 0x8b,0x22,0x74,0x1, 0x31,0x7a,0x20,0x19, -0x6, 0x12,0x3f,0x85,0x12,0x0, 0x56,0x7e,0xb3,0x36,0x2, 0xb4,0x1, 0x9, 0xf1,0xdc, -0x50,0x5, 0x31,0x85,0x12,0x0, 0x56,0xe4,0x21,0x7a,0x7c,0x7b,0xbe,0x70,0x8, 0x50, -0x3, 0x12,0xcf,0x16,0x22,0x74,0xc8,0x7a,0xb3,0x36,0x35,0xc2,0x19,0x80,0xa, 0x12, -0x3f,0xb, 0x30,0x19,0x4, 0x75,0xe9,0xff,0x22,0xf1,0xf2,0x68,0xf2,0x22,0x7e,0xa3, -0x1c,0x47,0x7e,0x73,0x1c,0x48,0x6d,0x22,0x9e,0x27,0x1c,0xc1,0xbe,0x27,0x9, 0x0, -0x8, 0x17,0x6d,0x22,0x9e,0x27,0x1c,0xcc,0xbe,0x27,0x1a,0xbf,0x8, 0xb, 0x6d,0x22, -0x7a,0x27,0x36,0x4c,0xe4,0x51,0x26,0x80,0x2c,0xbe,0xa0,0x1, 0x38,0x1f,0xbe,0x70, -0x1, 0x38,0x1a,0x7e,0x27,0x1a,0xb7,0xbe,0x24,0x0, 0x1e,0x28,0x2, 0x80,0xe, 0x7e, -0xb3,0x2e,0x25,0x60,0x10,0x7e,0x27,0x2a,0x5c,0x4d,0x22,0x78,0x8, 0x11,0x84,0x74, -0x1, 0x51,0x26,0x80,0x10,0x4c,0xaa,0x78,0xf, 0xa5,0xbf,0x1, 0xb, 0x7e,0x37,0x2a, -0x5c,0x7a,0x37,0x2e,0x27,0x2, 0xcd,0x28,0x7e,0xb3,0x2e,0x25,0x70,0x17,0xa5,0xbf, -0x0, 0x13,0xbe,0xa0,0x1, 0x78,0xe, 0x74,0x1, 0x7a,0xb3,0x2e,0x25,0x7e,0x37,0x3a, -0xb4,0x7a,0x37,0x2a,0x5c,0x22,0x7a,0xb3,0x36,0x4e,0x7a,0xb3,0x35,0x6, 0x22,0x7e, -0xb3,0x35,0x31,0x70,0x4, 0xf1,0xdf,0xe1,0xe5,0x31,0x9e,0x51,0x4e,0x7c,0x7b,0x4c, -0x77,0x68,0xa, 0x7a,0x73,0x35,0x34,0x74,0x1, 0x7a,0xb3,0x1c,0x4d,0x22,0xca,0x79, -0x6c,0xaa,0x6d,0x0, 0x7d,0x40,0x7e,0xe3,0x1c,0x47,0x7e,0xf3,0x1c,0x48,0x7e,0xb3, -0x36,0x24,0x60,0x11,0x7e,0x17,0x36,0x2d,0x4d,0x11,0x78,0x2, 0x61,0x22,0xbe,0xe0, -0x1, 0x28,0x2, 0x61,0x22,0xbe,0xe0,0x1, 0x78,0x1d,0xbe,0xb0,0x4, 0x78,0x2, 0x61, -0x22,0x7e,0x47,0x1b,0x39,0x7e,0x7, 0x1b,0x3b,0x7d,0x34,0x7d,0x20,0x12,0xcd,0x34, -0xbe,0xb0,0x1, 0x78,0x2, 0x61,0x22,0x7e,0x73,0x36,0x24,0x7c,0xb7,0x14,0x68,0x20, -0x14,0x68,0x49,0x14,0x68,0x1a,0x14,0x68,0x76,0xb, 0xb2,0x78,0x75,0xbe,0xe0,0x1, -0x78,0x7f,0x4c,0xff,0x78,0x7b,0x74,0x1, 0x7a,0xb3,0x36,0x24,0x71,0x35,0x80,0x55, -0x4c,0xee,0x78,0x1c,0xa5,0xbf,0x1, 0xc, 0x74,0x2, 0x7a,0xb3,0x36,0x24,0x7e,0xe7, -0x3a,0x86,0x80,0x45,0x74,0x4, 0x7a,0xb3,0x36,0x24,0x7e,0xe7,0x3a,0x8a,0x80,0x39, -0x71,0x3e,0x7e,0xb3,0x3a,0x79,0x71,0x47,0x68,0x38,0x80,0x45,0xbe,0xe0,0x1, 0x78, -0x40,0x4c,0xff,0x78,0x3c,0x71,0x3e,0x7e,0x17,0x3a,0x86,0x9e,0x17,0x3a,0x82,0xbe, -0x17,0x36,0x2d,0x40,0x1d,0x7e,0xb3,0x3a,0x78,0x71,0x47,0x68,0x15,0x71,0x35,0x74, -0x3, 0x7a,0xb3,0x36,0x24,0x7e,0xe7,0x3a,0x86,0x7a,0xe7,0x36,0x2d,0x80,0x12,0x7e, -0xa0,0x24,0xe4,0x7a,0xb3,0x36,0x24,0x6d,0xee,0x7a,0xe7,0x36,0x2d,0x7c,0xba,0x80, -0x1, 0xe4,0xda,0x79,0x22,0x7a,0x47,0x36,0x25,0x7a,0x7, 0x36,0x27,0x22,0x7a,0x47, -0x36,0x29,0x7a,0x7, 0x36,0x2b,0x22,0xa, 0x3b,0x71,0x50,0xa, 0xfb,0x4d,0xff,0x22, -0x7d,0x13,0x3e,0x14,0x3e,0x14,0x3e,0x14,0x7e,0x37,0x36,0x29,0x9e,0x37,0x36,0x25, -0x12,0x20,0x54,0xbd,0x31,0x38,0x12,0x7e,0x37,0x36,0x2b,0x9e,0x37,0x36,0x27,0x12, -0x20,0x54,0xbd,0x31,0x38,0x3, 0x74,0x1, 0x22,0xe4,0x22,0xca,0x69,0xca,0xf8,0x7c, -0xfb,0x7e,0x70,0x9, 0xac,0x7f,0x9, 0xb3,0x31,0x42,0x9, 0x73,0x31,0x43,0x12,0x2b, -0x76,0x7d,0x63,0x7e,0x73,0x1c,0x51,0xbe,0x70,0x0, 0x28,0x3, 0xe4,0x81,0x79,0x12, -0x45,0xc8,0x30,0xe0,0x9, 0x7e,0xb3,0x30,0xc2,0x60,0x3, 0xe4,0x81,0x79,0x7e,0x73, -0x30,0xaa,0xbe,0x70,0x1, 0x28,0xb, 0x12,0x8f,0xe9,0xbe,0x44,0xd, 0x0, 0x28,0x2, -0x91,0x7e,0x7e,0xa3,0x30,0xc2,0x4c,0xaa,0x68,0x9, 0xbe,0x64,0x0, 0x21,0x8, 0x3, -0xe4,0x81,0x79,0xa, 0x4f,0x9, 0xb4,0x30,0xc3,0xbe,0xb0,0x58,0x50,0x1f,0x9, 0xb4, -0x31,0x98,0xbe,0xb0,0x5, 0x28,0x16,0x9, 0xb4,0x30,0xb8,0xbe,0xb0,0x7, 0x38,0xa, -0xbe,0x64,0x0, 0x2c,0x18,0x4, 0x4c,0xaa,0x68,0x3, 0xe4,0x80,0x7c,0x9, 0x74,0x30, -0xb8,0xbe,0x70,0x3c,0x50,0x72,0xbe,0x70,0x0, 0x40,0x6d,0x7e,0x57,0x1c,0xcc,0xbd, -0x56,0x8, 0x65,0x31,0x2d,0x38,0x6, 0x7e,0xb3,0x31,0x96,0x60,0x4b,0x7e,0x73,0x30, -0xb5,0xbe,0x70,0xc8,0x50,0x42,0x7e,0x70,0x9, 0xac,0x7f,0x49,0x13,0x30,0xcd,0xbe, -0x14,0x2, 0x0, 0x40,0x15,0x7e,0x43,0x38,0x50,0x7e,0x50,0x40,0xac,0x45,0x9e,0x24, -0x0, 0x80,0x3e,0x24,0x3e,0x24,0xbd,0x12,0x28,0x1e,0x7e,0x53,0x38,0x51,0xa, 0x25, -0x1b,0x25,0x12,0xc4,0x97,0x3e,0x24,0x49,0x53,0x30,0xcf,0xbd,0x52,0x38,0x6, 0xbe, -0x54,0x2, 0x0, 0x50,0x3, 0xe4,0x80,0x11,0x9, 0x74,0x31,0x31,0xbe,0x70,0x3, 0x28, -0x3, 0xe4,0x80,0x5, 0x74,0x1, 0x80,0x1, 0xe4,0xda,0xf8,0xda,0x69,0x22,0x49,0x35, -0x30,0xcd,0x7e,0x24,0x0, 0xa0,0x7d,0x13,0xbd,0x21,0x38,0x13,0x7e,0x3, 0x38,0x50, -0x7e,0x10,0x40,0xac,0x1, 0x3e,0x4, 0x3e,0x4, 0x9d,0x2, 0xbd,0x1, 0x50,0x2, 0xd3, -0x22,0xc3,0x22,0xca,0x79,0x7c,0xe7,0x7c,0xfb,0xb1,0x2a,0xb4,0x1, 0x78,0x9, 0xb3, -0x31,0x27,0xb4,0x2, 0x71,0x74,0x1, 0x19,0xb3,0x31,0x27,0x7c,0xbf,0x71,0x7b,0x60, -0x65,0x7e,0x23,0x1c,0x47,0xbe,0x20,0xa, 0x50,0x5c,0xe4,0xa, 0x3e,0xf1,0xd3,0x12, -0x8f,0xf2,0x7e,0x30,0x9, 0xac,0x23,0x12,0x8f,0xc8,0x7e,0x73,0x1c,0x47,0x74,0x9, -0xac,0xb7,0x19,0xe5,0x1a,0xe3,0x7c,0xb7,0x4, 0x7a,0xb3,0x1c,0x47,0x7e,0x73,0x1c, -0x47,0x80,0x19,0x7e,0x50,0x9, 0xac,0x57,0x9, 0x62,0x1a,0xe3,0xbc,0x6f,0x68,0x4, -0xbc,0x6e,0x78,0x6, 0x74,0xff,0x19,0xb2,0x1a,0xe3,0xb, 0x70,0xbe,0x70,0xa, 0x40, -0xe2,0x7e,0x73,0x2e,0x8d,0xa, 0x2e,0x19,0x72,0x2e,0x83,0xe4,0xa, 0x3f,0x19,0xb3, -0x30,0xb8,0x74,0x1, 0x80,0x1, 0xe4,0xda,0x79,0x22,0xa, 0x3f,0x9, 0xb3,0x1b,0xed, -0x22,0xca,0x3b,0x7e,0xb3,0x35,0x31,0x60,0x2, 0xc1,0xd3,0x7e,0x63,0x1c,0x47,0xbe, -0x60,0x5, 0x28,0x1e,0x7e,0x8, 0x30,0x78,0x12,0xcd,0xd4,0x12,0x20,0x12,0x6c,0x77, -0x6d,0x44,0x74,0x2, 0xac,0xb7,0x59,0x45,0x17,0xba,0xb, 0x70,0xa5,0xbf,0xa, 0xf2, -0xc1,0xd3,0x6c,0xee,0xc1,0xc9,0x74,0x9, 0xac,0xbe,0x9, 0xf5,0x1b,0x3d,0xbe,0xf0, -0xff,0x78,0x2, 0xc1,0xc7,0xa, 0x3f,0x2e,0x34,0x30,0x78,0x6d,0x22,0x7a,0x1d,0x24, -0xb1,0x2a,0x70,0x5, 0xd1,0xd6,0x7a,0x1b,0xb0,0x74,0x2, 0xac,0xbf,0x49,0x35,0x17, -0xba,0x1b,0x34,0x68,0x40,0x1b,0x34,0x78,0x2, 0xc1,0xac,0xb, 0x35,0x68,0x2, 0xc1, -0xc2,0x7e,0x30,0x12,0xac,0x3f,0x2e,0x14,0x17,0x6, 0x6d,0x0, 0x7e,0x34,0x0, 0x12, -0x74,0xff,0x12,0x20,0x12,0xb1,0x2a,0x60,0x2, 0xc1,0xc7,0xe4,0x7e,0x1d,0x24,0x7a, -0x1b,0xb0,0x7e,0x34,0x0, 0x9, 0xca,0x39,0xd1,0xe5,0x12,0x1f,0xed,0x1b,0xfd,0x7e, -0x44,0x0, 0x1, 0xc1,0x9c,0xa, 0x3f,0x9, 0xd3,0x1b,0xed,0xbe,0xd0,0x2, 0x78,0x59, -0x7e,0x1d,0x24,0x7e,0x1b,0x70,0xbe,0x70,0x2, 0x50,0xa, 0x7e,0x34,0x0, 0x9, 0xca, -0x39,0xd1,0xe5,0x80,0x2f,0x7e,0x34,0x0, 0x9, 0xca,0x39,0x7e,0x30,0x12,0xac,0x3f, -0x7d,0x31,0x2e,0x34,0x17,0xf, 0x6d,0x22,0x2e,0x14,0x17,0x6, 0x6d,0x0, 0x12,0x1f, -0xed,0x1b,0xfd,0x7e,0x34,0x0, 0x9, 0xca,0x39,0xf1,0x6, 0x7e,0x30,0x12,0xac,0x3f, -0x2e,0x14,0x17,0xf, 0x12,0x1f,0xed,0x1b,0xfd,0x7e,0x1d,0x24,0x7e,0x1b,0xb0,0xbe, -0xb0,0xa, 0x40,0x2, 0xc1,0xc7,0x4, 0xc1,0xc4,0xbe,0xd0,0x1, 0x78,0x6a,0x7e,0x1d, -0x24,0x7e,0x1b,0x70,0xbe,0x70,0x3, 0x28,0x5b,0x74,0x12,0xac,0xbf,0x49,0x35,0x17, -0x6, 0x49,0x45,0x17,0xf, 0x9d,0x43,0x7a,0x45,0x28,0x49,0x35,0x17,0x8, 0x49,0x65, -0x17,0x11,0x9d,0x63,0x7d,0x36,0x12,0x20,0x54,0x7d,0x13,0x7e,0x35,0x28,0x12,0x20, -0x54,0x2d,0x31,0x7a,0x35,0x2a,0xbe,0x34,0x0, 0x14,0x48,0x24,0x7e,0x45,0x28,0x74, -0x2, 0xac,0xbf,0x59,0x45,0x30,0x82,0x59,0x65,0x30,0x96,0x49,0x35,0x30,0x82,0x49, -0x25,0x30,0x96,0x7c,0xbf,0x12,0x88,0x1f,0x7e,0x44,0x0, 0x2, 0xf1,0xf, 0x80,0x27, -0xd1,0xd6,0x80,0x20,0xd1,0xd6,0x80,0x1c,0xd1,0xd6,0x80,0x18,0x6d,0x44,0xf1,0xf, -0x74,0x1, 0xf1,0xd1,0x7e,0xb3,0x1c,0x47,0x70,0x2, 0xf1,0xeb,0xe4,0x7e,0x1d,0x24, -0x80,0x2, 0xd1,0xd6,0x7a,0x1b,0xb0,0xb, 0xe0,0x7e,0x73,0x1c,0xbf,0xbc,0x7e,0x28, -0x2, 0xa1,0x66,0xda,0x3b,0x22,0x6d,0x44,0x74,0x2, 0xac,0xbf,0x59,0x45,0x17,0xba, -0xe4,0x7e,0x1d,0x24,0x22,0x7e,0x1d,0x24,0x7e,0x1b,0x0, 0x7c,0xb0,0x4, 0x7a,0x1b, -0xb0,0x7e,0x10,0x9, 0xac,0x1, 0x7e,0x30,0x12,0xac,0x3f,0x2d,0x10,0x2e,0x14,0x17, -0x6, 0x6d,0x0, 0x7e,0x70,0x9, 0xac,0x7e,0x2e,0x34,0x1b,0x39,0x6d,0x22,0x22,0x74, -0x2, 0xac,0xbf,0x59,0x45,0x17,0xba,0x22,0xca,0x3b,0x6c,0xcc,0x7e,0xf0,0x9, 0x7e, -0xa3,0x1c,0x47,0x7c,0xda,0xe4,0x7a,0xb3,0x31,0xa2,0x4c,0xaa,0x78,0xf, 0x12,0x8f, -0xe1,0x28,0x5, 0x14,0x7a,0xb3,0x30,0xc2,0xe4,0x7a,0xb3,0x30,0xb5,0xf1,0xc9,0x78, -0x2, 0xe1,0xc6,0x6c,0xee,0x80,0x10,0x7c,0xbe,0x12,0xc5,0x59,0x70,0x2, 0xb, 0xe0, -0xbe,0xc0,0xa, 0x38,0xa, 0xb, 0xc0,0x7e,0x73,0x1c,0x47,0xbc,0x7e,0x38,0xe8,0x7e, -0x73,0x31,0xa2,0xa, 0x27,0xa, 0x3d,0x9d,0x32,0x7a,0x73,0x30,0xb7,0x6c,0xee,0x80, -0x2, 0x1b,0xf0,0xb1,0x2a,0xbe,0xb0,0x3, 0x68,0x5, 0xbe,0xf0,0x0, 0x38,0xf2,0x7c, -0xbe,0x7c,0x7f,0x91,0xa3,0x60,0x6, 0x4c,0xff,0x68,0x9, 0x1b,0xf0,0xb, 0xe0,0xbe, -0xe0,0xa, 0x40,0xdf,0x7e,0xa3,0x31,0xa2,0x4c,0xaa,0x78,0x9, 0xc2,0x18,0xe4,0x7a, -0xb3,0x30,0xaa,0x80,0xe, 0x7e,0xb3,0x30,0xaa,0xbe,0xb3,0x31,0xa2,0x50,0x4, 0x7a, -0xa3,0x30,0xaa,0x7e,0x73,0x1c,0x47,0x7a,0x73,0x30,0xb6,0x7e,0xb3,0x31,0x96,0x60, -0x5, 0x14,0x7a,0xb3,0x31,0x96,0xda,0x3b,0x22,0x7e,0xb3,0x35,0x31,0xbe,0xb0,0x1, -0x22,0xa, 0x3f,0x19,0xb3,0x1b,0xed,0x19,0xb3,0x1b,0xf7,0x22,0xa2,0xd, 0x22,0xe4, -0x7a,0xb3,0x2e,0x25,0x22,0xe4,0x7a,0xb3,0x36,0x24,0x22,0x74,0x1, 0x7a,0xb3,0x1c, -0x4c,0x22,0x7e,0xb3,0x36,0x2, 0xbe,0xb0,0x1, 0x22,0x2, 0x62,0xcb,0x2, 0x64,0x77, -0x70,0x8f,0x0, 0xff,0xe4,0x1b,0xe4,0x1b,0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, -0x51,0x41,0x32,0x1, 0x45,0x35,0x31,0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, -0x5, 0xfa,0x30,0x30,0x31,0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, -0xf, 0x21,0x1, 0xf, 0x3, 0x0, 0x4, 0x5, 0x6, 0x7, 0x9, 0xc, 0xa, 0xd, 0x2, 0xb, -0x8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, 0x0, 0x9, 0x1, 0x4, 0x7, 0x0, 0x3, 0x12,0x5, 0x2, 0xa, 0x8, -0xe, 0x6, 0xb, 0xd, 0xf, 0x11,0x10,0x16,0x14,0x15,0x1a,0x19,0x1e,0x1b,0x22,0x1d, -0x23,0x1f,0x21,0x1c,0x20,0x17,0x0, 0x0, 0x0, 0x5, 0x0, 0x4, 0xff,0x14,0x21,0x2, -0x94,0xa, 0x1e,0xa, 0x64,0x2d,0x10,0x0, 0x4, 0x1, 0x90,0xd, 0xac,0x0, 0xc8,0x0, -0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x1, 0x19,0x2a,0x1, 0xf4, -0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64, -0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64, -0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64, -0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64,0x64, -0x64,0x73,0x64,0x64,0x64,0x64,0x64,0x0, 0x6, 0x27,0x20,0x1, 0x20,0x0, 0x0, 0x0, -0x0, 0x0, 0x1, 0xf4,0x40,0x40,0xf, 0x21,0x30,0xe, 0x10,0x3, 0x78,0xe, 0x10,0x3, -0x98,0x22,0x1d,0x6, 0x40,0x1, 0x0, 0x2f,0xa0,0x7, 0x80,0x2, 0x1c,0x6, 0xf2,0x6, -0x9f,0x6, 0x22,0x0, 0x93,0x0, 0x62,0x0, 0x48,0x2f,0x9e,0x10,0x80,0x4, 0x92,0xf, -0xfe,0xf, 0xa1,0xf, 0x20,0x0, 0x83,0x0, 0x5f,0x0, 0x47,0x0, 0xc8,0x0, 0xb4,0x0, -0xb4,0x0, 0xc8,0x0, 0xc8,0x0, 0xb4,0x0, 0xb4,0x8, 0x0, 0x0, 0xfa,0xa, 0xa, 0x64, -0x64,0x1, 0x1e,0xf, 0x1e,0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x52,0xb, 0x0, 0x1, 0x54,0x1, -0x0, 0x5, 0x1, 0xe4,0x1, 0x1, 0x0, 0xe4,0x1, 0x1, 0x1, 0x0, 0x5, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x55,0x1, 0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, -0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x64,0x1, 0x2c,0x0, 0x50, -0x0, 0x3d,0x0, 0x1, 0x0, 0x1, 0x1, 0x4, 0x1, 0x90,0x0, 0xc8,0x0, 0x50,0x1, 0x90, -0x0, 0x96,0x1, 0x2c,0x1, 0x2c,0x4, 0x2a,0x0, 0x27,0x40,0x20,0x20,0x1, 0x21,0x40, -0x20,0x37,0x0, 0x2a,0x40,0x20,0x3d,0x0, 0x2a,0x40,0x20,0x2a,0x0, 0x27,0x40,0x20, -0x2a,0x0, 0x27,0x40,0x20,0x2a,0x0, 0x27,0x40,0x20,0x2a,0x0, 0x27,0x40,0x20,0x4, -0x5, 0x10,0x11,0x12,0x13,0x14,0x4, 0x0, 0x96,0x1, 0x90,0x64,0x0, 0x96,0x1, 0x5e, -0x0, 0x64,0x0, 0x96,0x0, 0x96,0x0, 0x64,0xb, 0xb8,0x8, 0x5, 0x6, 0x80,0x1, 0x90, -0x1, 0x2c,0x1, 0xc2,0x3, 0x20,0xf, 0xa0,0x1, 0x3, 0x20,0x4, 0xb0,0x3, 0x20,0x1, -0x2, 0x2, 0x4, 0x4, 0x6, 0x40,0x1, 0x40,0x1, 0x18,0x1, 0x54,0x1, 0x2c,0x1, 0x54, -0x1, 0x5e,0x1, 0x2c,0x1, 0x2c,0x0, 0xc8,0x0, 0xfa,0x0, 0x50,0x0, 0x46,0x0, 0x5a, -0x0, 0x64,0x0, 0x5a,0x1, 0x18,0x1, 0x18,0x16,0xa, 0x0, 0x50,0x3, 0xe8,0x0, 0x50, -0x8, 0xd4,0x0, 0x32,0x1, 0xf4,0x1, 0xf4,0x3, 0x20,0x0, 0x14,0x0, 0x48,0x0, 0x1e, -0x0, 0x80,0x1, 0xe, 0x1, 0x24,0x0, 0x3c,0x3, 0xe8,0x2, 0x49,0x0, 0x87,0x0, 0x3c, -0x3, 0xe8,0x0, 0x0, 0x4, 0x38,0x0, 0x0, 0x9, 0x24,0x2, 0x1c,0x3, 0xc, 0x0, 0x64, -0x0, 0xa0,0x0, 0xa0,0x1, 0xfe,0x1, 0x2c,0x0, 0xa0,0x0, 0xa0,0x10,0x0, 0xc, 0x0, -0xf, 0xd, 0x5, 0x6, 0xa, 0x9, 0x6, 0x6, 0xc, 0x64,0xc8,0x7e,0x37,0x32,0x4c,0xb, -0x34,0x7a,0x37,0x32,0x4c,0x7e,0x37,0x32,0x4e,0xbe,0x37,0x32,0x4c,0x28,0x3, 0x2, -0xc6,0x9b,0x22,0x7e,0x34,0x3, 0xe8,0x7d,0x23,0x6d,0x33,0x7a,0x37,0x32,0x4c,0x7a, -0x27,0x32,0x4e,0x22,0x7e,0xb3,0x1d,0xa2,0x70,0x1e,0x51,0xe3,0x12,0x71,0xac,0xe4, -0x33,0x68,0xf9,0xf1,0xf, 0x12,0x0, 0x46,0x20,0xf, 0x2, 0xb1,0x22,0x74,0x2, 0x7a, -0xb3,0x1d,0xa2,0xe4,0x7a,0xb3,0x16,0xbf,0x22,0xe4,0x91,0x91,0x12,0xc7,0x0, 0x51, -0xe3,0x12,0xc7,0x72,0x12,0x3b,0xac,0x12,0xc6,0xa5,0x12,0xc7,0x17,0x12,0x0, 0x4a, -0x12,0xc7,0x23,0x91,0x46,0xc2,0xae,0x12,0xc7,0x33,0xd2,0xaf,0x91,0xc4,0x71,0x5c, -0x12,0x3b,0x48,0x12,0x3f,0x9d,0x7e,0x8, 0x32,0x50,0x12,0xc7,0xa7,0x7e,0xb3,0x38, -0x50,0x7e,0x73,0x38,0x51,0x7e,0x24,0xff,0xff,0x2, 0x1b,0xc9,0xd2,0xc8,0x43,0xed, -0xf, 0xc2,0xea,0x75,0xb3,0x13,0xa9,0xd1,0xb4,0xa9,0xc0,0xb4,0x12,0xc7,0xd5,0xe4, -0x71,0x7d,0x61,0x74,0xa9,0xc5,0xca,0xe4,0x7a,0xb3,0x36,0x56,0x22,0xca,0xf8,0x7c, -0xfb,0x74,0x2, 0x71,0xec,0x4c,0xff,0x78,0x5, 0x5e,0x70,0xdf,0x80,0x3, 0x4e,0x70, -0x20,0x74,0x2, 0x71,0x98,0xda,0xf8,0x22,0x7d,0x43,0x7c,0x5b,0xa, 0x58,0x7c,0xab, -0x7d,0x34,0x7c,0x47,0x7e,0xb3,0x36,0x56,0xb4,0xa5,0x39,0x91,0x3f,0x75,0xb5,0x1, -0xa9,0x36,0xb3,0xfc,0x71,0xe5,0xa9,0x36,0xb3,0xfc,0x71,0xe5,0xa9,0x36,0xb3,0xfc, -0xa9,0xc6,0xb3,0x7a,0x51,0xb5,0xa9,0x36,0xb3,0xfc,0xa9,0xc6,0xb3,0x7a,0xa1,0xb5, -0xa9,0x36,0xb3,0xfc,0xa9,0xc6,0xb3,0x7a,0x41,0xb5,0xa9,0x36,0xb3,0xfc,0xa9,0xc6, -0xb3,0xa9,0xd2,0xb4,0x22,0xa9,0xc6,0xb3,0x75,0xb5,0x0, 0x22,0x7c,0xab,0x6c,0x66, -0x6c,0x77,0x7e,0xb3,0x36,0x56,0xb4,0xa5,0x41,0x91,0x3f,0x75,0xb5,0x5, 0xa9,0x36, -0xb3,0xfc,0x71,0xe5,0xa9,0x36,0xb3,0xfc,0x71,0xe5,0xa9,0x36,0xb3,0xfc,0xa9,0xc6, -0xb3,0x7a,0xa1,0xb5,0xa9,0x36,0xb3,0xfc,0x71,0xe5,0xa9,0x36,0xb3,0xfc,0x71,0xe5, -0xa9,0x36,0xb3,0xfc,0xa9,0xc6,0xb3,0x7e,0x61,0xb5,0x75,0xb5,0x0, 0xa9,0x36,0xb3, -0xfc,0xa9,0xc6,0xb3,0x7e,0x71,0xb5,0xa9,0xd2,0xb4,0x7c,0x46,0x7c,0x64,0x22,0xa9, -0xc2,0xb4,0xa9,0xc6,0xb3,0x22,0xe4,0x7a,0xb3,0x35,0x41,0x7e,0x8, 0x2f,0xa0,0x12, -0x93,0xa, 0x7e,0x8, 0x2f,0xde,0x7e,0x34,0x0, 0x3e,0x12,0x20,0x12,0x7e,0x34,0x2f, -0xde,0x7a,0x37,0x30,0x1c,0x12,0x5f,0xfd,0x81,0x6a,0x75,0x61,0x0, 0x75,0x63,0x0, -0x7e,0xb3,0x35,0x41,0xf5,0x91,0x22,0x7e,0xb3,0x38,0x0, 0x54,0xfe,0x75,0x91,0x0, -0xc2,0x90,0xc2,0x91,0xc2,0xc9,0x54,0xfe,0xf5,0x92,0xd2,0xe8,0xc2,0xc0,0xd2,0xad, -0x22,0x7c,0x7b,0xa9,0xc4,0xca,0xa9,0xc5,0xca,0xbe,0x70,0x8, 0x50,0x3, 0x12,0xcf, -0x16,0xa9,0xd0,0xce,0xa9,0xc0,0xc9,0xd2,0x5, 0x12,0x3d,0x23,0xa9,0xc2,0xea,0x75, -0xc1,0x6, 0x75,0xc2,0xc, 0xd2,0x3, 0x12,0xc7,0x79,0xa9,0xc1,0xc4,0xa9,0xd2,0xc4, -0xa9,0xc2,0xe1,0x22,0xd2,0xcd,0x7e,0x34,0x0, 0xed,0x12,0xcf,0xd, 0x7e,0x34,0x20, -0x5f,0x7e,0xf, 0x3, 0xd9,0x79,0x30,0x0, 0x9c,0x7e,0x34,0x21,0x0, 0x7e,0xf, 0x3, -0xd9,0x79,0x30,0x0, 0xaa,0x7e,0x34,0x84,0xc0,0x7e,0xf, 0x3, 0xd9,0x79,0x30,0x0, -0xa0,0x7e,0x34,0x4, 0x8e,0x7e,0xf, 0x3, 0xd9,0x79,0x30,0x0, 0xa2,0x7e,0x34,0x29, -0x90,0x7e,0xf, 0x3, 0xd9,0x79,0x30,0x0, 0xa4,0x7e,0x34,0x6c,0xd1,0x7e,0xf, 0x3, -0xd9,0x79,0x30,0x0, 0xa6,0x7e,0x34,0x3, 0x64,0x7e,0xf, 0x3, 0xd9,0x79,0x30,0x0, -0xa8,0x22,0xca,0x3b,0x7e,0xb3,0x1d,0x93,0x7a,0xb3,0x2a,0x5b,0x7e,0xf3,0x1d,0xee, -0xb1,0xaa,0x7c,0xdb,0xbe,0xd0,0xff,0x68,0x6e,0x6c,0xcc,0x74,0x5, 0xac,0xbc,0x9, -0xb5,0x17,0xce,0xf5,0x28,0x7e,0x73,0x1d,0x93,0xbe,0x71,0x28,0x68,0x3b,0x7e,0x70, -0x4, 0xac,0x7d,0xa, 0x2c,0x2d,0x32,0x2e,0x34,0x20,0x44,0xd1,0x2d,0x7c,0xeb,0xbe, -0xe0,0x2, 0x38,0x43,0xa, 0xe, 0x7e,0x14,0x1, 0xf0,0xad,0x10,0x2e,0x14,0x24,0x8b, -0x6d,0x0, 0x7a,0xd, 0x29,0x7e,0x70,0x22,0xac,0x7e,0x2e,0x34,0x34,0x7a,0x6d,0x22, -0x7a,0x1f,0x34,0x76,0x7c,0xbc,0x12,0xb0,0xa5,0xb, 0xc0,0xbe,0xc0,0x4, 0x40,0xab, -0x7e,0x73,0x1d,0xee,0xbc,0x7f,0x68,0x6, 0x7a,0xf3,0x1d,0xee,0xd2,0xc, 0xd2,0x3, -0x7e,0xb3,0x2a,0x5b,0x12,0x51,0xc1,0xda,0x3b,0x22,0x7c,0x6b,0x6c,0x77,0x74,0x5, -0xac,0xb7,0x9, 0x55,0x17,0xce,0xbc,0x56,0x78,0x3, 0x7c,0xb7,0x22,0xb, 0x70,0xbe, -0x70,0x4, 0x40,0xea,0x74,0xff,0x22,0x7c,0x4b,0x7e,0xb3,0x2a,0x5b,0xbc,0x4b,0x68, -0x57,0xb1,0xaa,0x7c,0x3b,0x7c,0xb4,0xb1,0xaa,0x7c,0x5b,0xbe,0x30,0xff,0x68,0x48, -0xbe,0x50,0xff,0x68,0x43,0x7e,0x70,0x4, 0xac,0x73,0xa, 0x25,0x2d,0x32,0x2e,0x34, -0x20,0x44,0xd1,0x2d,0xbe,0xb0,0x2, 0x38,0x2f,0xa, 0x2b,0x7e,0x34,0x1, 0xf0,0xad, -0x32,0x2e,0x34,0x24,0x8b,0x6d,0x22,0x30,0x17,0x2, 0xc1,0x36,0x7e,0xb3,0x1d,0xa1, -0xb4,0x1, 0x15,0x7e,0xb3,0x1c,0xe0,0x7e,0x33,0x1c,0xdf,0xac,0xb3,0x7a,0x55,0x28, -0x7e,0x8, 0xe, 0x3c,0x74,0x1, 0xc1,0x6b,0x22,0x2e,0x34,0x1f,0xc9,0x7a,0x71,0x82, -0x7a,0x61,0x83,0xe4,0x93,0x22,0x7c,0xab,0x7e,0xb3,0x38,0x9b,0xa, 0x3b,0x7e,0xb3, -0x1c,0xe3,0xa, 0x2b,0x2d,0x23,0x7e,0xb3,0x1c,0xe0,0xa, 0x3b,0xad,0x32,0x7d,0x43, -0x3e,0x44,0x7e,0xf, 0x3, 0xfa,0x2d,0x14,0xa, 0x3b,0x7a,0x35,0x28,0x7e,0x70,0x22, -0xac,0x7a,0x2e,0x34,0x34,0x7a,0x6d,0x22,0xe4,0xc1,0x6b,0x7c,0xab,0x7f,0x71,0x7f, -0x60,0x6d,0x44,0x80,0x25,0x4c,0xaa,0x68,0xf, 0xd1,0xae,0x60,0x5, 0x3e,0x24,0x14, -0x78,0xfb,0xd1,0xa2,0x2d,0x32,0x80,0xd, 0xd1,0xae,0x60,0x5, 0x3e,0x24,0x14,0x78, -0xfb,0xd1,0xa2,0x9d,0x32,0x1b,0xa, 0x30,0xb, 0x44,0x7e,0x35,0x28,0xbd,0x34,0x38, -0xd4,0x22,0x7d,0x34,0x3e,0x34,0x7f,0x6, 0x2d,0x13,0xb, 0xa, 0x30,0x22,0x7f,0x17, -0x2d,0x34,0x7e,0x1b,0xb0,0x1a,0x2b,0x7f,0x7, 0x2e,0x15,0x28,0x7e,0xb, 0xb0,0x22, -0x7e,0xb3,0x35,0x6, 0x70,0x2d,0x7e,0x73,0x34,0xe9,0xbe,0x70,0x10,0x40,0x2, 0x6c, -0x77,0x7e,0xb3,0x35,0x31,0xb4,0x1, 0x3, 0x7e,0x70,0x6, 0xa, 0x37,0x2e,0x34,0x20, -0x24,0xd1,0x2d,0x7c,0xab,0xe5,0x6b,0xa, 0x3b,0x2e,0x37,0x36,0x4c,0x7a,0x37,0x36, -0x4c,0x80,0xc, 0x7e,0xa3,0x34,0xea,0xbe,0xa0,0x7f,0x28,0x3, 0x7e,0xa0,0x7f,0x7c, -0xba,0xe1,0x3, 0x7c,0x7b,0x75,0x6b,0x0, 0x7a,0x73,0x36,0x35,0xc2,0x19,0x22,0x7e, -0xf, 0x13,0x68,0x7e,0x18,0x9, 0x14,0xca,0x3b,0x7a,0x1d,0x28,0x7f,0x30,0x12,0xb2, -0x44,0x7a,0x55,0x30,0x7e,0xb3,0x1d,0xa1,0xf5,0x2d,0xe4,0x7a,0xb3,0x1d,0xa1,0x7f, -0x3, 0x7e,0x1d,0x28,0x12,0x56,0xa2,0xf1,0xd3,0x7e,0x8, 0x1c,0xdf,0x12,0x16,0x52, -0x75,0x2c,0x0, 0xe4,0x12,0x0, 0xe, 0x74,0x1, 0x7e,0x70,0x99,0x12,0x1c,0x5c,0xf1, -0xa4,0x12,0x0, 0x1e,0x30,0xb, 0xfd,0x74,0x1, 0x12,0xcf,0x8d,0x7e,0x14,0x80,0x0, -0x7d,0x21,0x7d,0x7, 0x12,0x2f,0xfc,0x12,0xb2,0x5e,0x6d,0x33,0x80,0x19,0x7e,0x35, -0x2e,0x3e,0x34,0x7f,0x3, 0x2d,0x13,0xb, 0xa, 0x20,0x7e,0xd, 0x28,0x2d,0x13,0x12, -0xcf,0x3a,0x7e,0x35,0x2e,0xb, 0x34,0x7a,0x35,0x2e,0x7e,0x35,0x30,0xbe,0x35,0x2e, -0x38,0xdc,0x5, 0x2c,0xe5,0x2c,0xbe,0xb0,0x1, 0x40,0xa8,0xe5,0x2d,0x7a,0xb3,0x1d, -0xa1,0xda,0x3b,0x22,0x7e,0x63,0x1d,0x93,0x7e,0x73,0x35,0x72,0xac,0x67,0x2e,0x34, -0x1, 0xf4,0x12,0xce,0xd0,0x28,0x3, 0x7e,0x70,0x7, 0x12,0x45,0x73,0x2d,0x32,0x79, -0x30,0x0, 0xa0,0x22,0xf1,0xd3,0xe4,0x12,0x0, 0xe, 0x7e,0x8, 0x1c,0xdf,0x12,0x16, -0x52,0xe1,0xa4,0x74,0x1, 0x12,0x1d,0x14,0xe4,0x2, 0x0, 0x6, 0x7c,0x7b,0xa5,0xbf, -0x3, 0x4, 0xf1,0xc4,0x80,0x2, 0xe4,0x22,0x12,0xb2,0x53,0x74,0x1, 0x22,0x74,0xa, -0x7a,0xb3,0x1c,0xbf,0x74,0x10,0x7a,0xb3,0x1c,0xc0,0x7e,0x34,0x0, 0xc8,0x7a,0x37, -0x1c,0xc1,0x7e,0x24,0x0, 0xb4,0x7a,0x27,0x1c,0xc3,0x7a,0x27,0x1c,0xc5,0x7a,0x27, -0x1c,0xc7,0x74,0x2d,0x7a,0xb3,0x1c,0xcb,0x7a,0x37,0x1c,0xcc,0x7e,0x34,0x0, 0xb4, -0x7a,0x37,0x1c,0xce,0x7e,0x34,0xff,0x4c,0x7a,0x37,0x1c,0xd0,0x7e,0x34,0x0, 0x96, -0x7a,0x37,0x1c,0xd2,0xe4,0x7a,0xb3,0x1c,0xd6,0x74,0x4, 0x7a,0xb3,0x1c,0xd7,0x7e, -0x34,0x1, 0x90,0x7a,0x37,0x1c,0xd8,0x7e,0x34,0x8, 0x0, 0x7a,0x37,0x1c,0xd4,0x74, -0x1, 0x7a,0xb3,0x1c,0xda,0xe4,0x7a,0xb3,0x1c,0xdb,0x7a,0xb3,0x16,0xc0,0x22,0x7e, -0x34,0x0, 0x4, 0xca,0x39,0x7e,0x18,0x39,0x3d,0x7e,0x8, 0x1e,0x12,0x12,0x1f,0xed, -0x1b,0xfd,0x7e,0x34,0x1c,0x55,0x7a,0x37,0x1e,0x18,0xe4,0x7a,0xb3,0x1e,0x16,0x7a, -0xb3,0x1e,0x17,0x7e,0x34,0x0, 0x4, 0xca,0x39,0x7e,0x18,0x39,0x39,0x7e,0x8, 0x16, -0xc1,0x12,0x1f,0xed,0x1b,0xfd,0x7e,0x34,0x1e,0x1a,0x7a,0x37,0x16,0xc7,0x74,0x1, -0x7a,0xb3,0x16,0xc5,0x7a,0xb3,0x16,0xc6,0x22,0xe4,0x7a,0xb3,0x35,0x41,0x7a,0xb3, -0x35,0x42,0x7e,0x73,0x38,0x50,0x7a,0x73,0x35,0x43,0x7e,0x73,0x38,0x51,0x7a,0x73, -0x35,0x44,0x7a,0xb3,0x35,0x45,0x74,0xa, 0x7a,0xb3,0x35,0x46,0xe4,0x7a,0xb3,0x35, -0x47,0x7a,0xb3,0x35,0x48,0x74,0x1, 0x7a,0xb3,0x35,0x4a,0x74,0x32,0x7a,0xb3,0x35, -0x4e,0x7a,0xb3,0x35,0x4f,0x74,0x41,0x7a,0xb3,0x35,0x60,0x74,0x6, 0x7a,0xb3,0x35, -0x61,0xe4,0x7a,0xb3,0x35,0x4d,0x74,0x27,0x7a,0xb3,0x35,0x63,0x74,0x40,0x7a,0xb3, -0x35,0x62,0xe4,0x7a,0xb3,0x35,0x64,0x74,0x40,0x7a,0xb3,0x35,0x5f,0x74,0x1, 0x7a, -0xb3,0x35,0x5b,0xe4,0x7a,0xb3,0x35,0x5c,0x7a,0xb3,0x35,0x5d,0x7e,0x8, 0x35,0x65, -0x7e,0x34,0x0, 0x2c,0x12,0x20,0x12,0x74,0x1, 0x7a,0xb3,0x35,0x70,0x74,0xf4,0x7a, -0xb3,0x35,0x71,0x74,0x19,0x7a,0xb3,0x35,0x72,0x74,0x2a,0x7a,0xb3,0x35,0x73,0x7e, -0x34,0x0, 0x4, 0xca,0x39,0x7e,0x18,0x39,0x39,0x7e,0x8, 0x35,0x81,0x12,0x1f,0xed, -0x1b,0xfd,0x74,0x6, 0x7a,0xb3,0x35,0x8e,0x74,0x1, 0x7a,0xb3,0x35,0x85,0x7e,0x34, -0x0, 0x28,0xca,0x39,0x7e,0x18,0x39,0xf7,0x7e,0x8, 0x17,0xce,0x12,0x1f,0xed,0x1b, -0xfd,0x22,0xca,0x79,0x7c,0xf7,0x7c,0xab,0x7e,0x33,0x35,0x72,0xac,0x3a,0x31,0xd5, -0x50,0x4, 0x7e,0x14,0x0, 0xa, 0xbe,0x14,0xb, 0xb8,0x40,0x4, 0x7e,0x14,0xb, 0xb8, -0xbe,0x14,0x9, 0x60,0x28,0x4, 0x6c,0x77,0x80,0x19,0xbe,0x14,0x5, 0xdc,0x40,0x5, -0x7e,0x70,0x3, 0x80,0xe, 0xbe,0x14,0x2, 0xee,0x40,0x5, 0x7e,0x70,0x1, 0x80,0x3, -0x7e,0x70,0x2, 0x74,0x5, 0xac,0xbf,0x19,0x75,0x1e,0x2, 0x74,0x5, 0xac,0xfb,0x9, -0xb7,0x1e,0x2, 0xb4,0x3, 0x4, 0x31,0xeb,0x80,0x2, 0x74,0x20,0x19,0xb7,0x1e,0x3, -0x31,0xde,0xda,0x79,0x22,0x2e,0x14,0x1, 0xf4,0xbe,0x14,0x0, 0xa, 0x22,0x6d,0x0, -0x7e,0x34,0xd0,0x0, 0x7e,0x24,0x0, 0x7, 0x2, 0x1d,0xe9,0x6d,0x0, 0x7e,0xf4,0xd0, -0x0, 0x7e,0xe4,0x0, 0x7, 0x7f,0x17,0x12,0x1d,0xe9,0xb, 0x34,0x7e,0x14,0x0, 0x6, -0x8d,0x31,0xad,0x13,0x6d,0x0, 0x7f,0x17,0x12,0x1d,0xe9,0x7d,0x13,0x74,0x30,0x22, -0x9f,0x11,0x6c,0x33,0x80,0x23,0xa, 0x3, 0x9, 0x20,0x1d,0x56,0x7e,0xa0,0x3, 0x7c, -0xb2,0x84,0x7c,0x2a,0x74,0x3, 0xac,0xb2,0xa, 0x2, 0xb, 0x4, 0x60,0x5, 0x3e,0x4, -0x14,0x78,0xfb,0x7d,0x50,0x4d,0x35,0xb, 0x30,0x7e,0x13,0x1c,0xe6,0xbc,0x13,0x38, -0xd5,0x6c,0x33,0x80,0x1f,0xa, 0x3, 0x9, 0x20,0x1d,0x33,0xbe,0x20,0xb, 0x38,0x5, -0x4e,0x60,0x8, 0x80,0xd, 0xbe,0x20,0x17,0x38,0x5, 0x4e,0x60,0x50,0x80,0x3, 0x4e, -0x50,0x6, 0xb, 0x30,0x7e,0x23,0x1c,0xe5,0xbc,0x23,0x38,0xd9,0x22,0x7e,0x54,0x0, -0x5e,0x7e,0x44,0x0, 0xff,0x69,0x32,0x0, 0x4, 0x69,0x22,0x0, 0x2, 0xb, 0x2a,0x10, -0x7a,0x1d,0x26,0x7a,0x15,0x24,0x7e,0x34,0x0, 0x20,0x7e,0x8, 0x0, 0x24,0x7e,0x24, -0x0, 0x6, 0x51,0xd6,0x74,0x32,0x7a,0xb3,0x34,0xe1,0x74,0x2d,0x7a,0xb3,0x34,0xe2, -0x74,0xc, 0x7a,0xb3,0x34,0xe3,0x74,0xb, 0x7a,0xb3,0x34,0xe4,0x7a,0xb3,0x34,0xe5, -0x74,0x80,0x7a,0xb3,0x34,0xe6,0x7e,0x34,0x0, 0x59,0xca,0x39,0x7e,0x18,0x39,0x81, -0x7e,0x8, 0x34,0xe7,0x12,0x1f,0xed,0x1b,0xfd,0xe5,0x25,0x7a,0xb3,0x35,0x12,0xe5, -0x28,0x7a,0xb3,0x35,0x1, 0x22,0x7f,0x20,0x41,0xda,0x7f,0x70,0x7d,0xd3,0x71,0x48, -0x24,0xe4,0x68,0xe, 0x24,0x54,0x68,0x10,0x24,0xd9,0x78,0x12,0x7d,0x3d,0x7f,0x7, -0x41,0xff,0x7d,0x3d,0x7f,0x7, 0x61,0xb3,0x7d,0x3d,0x7f,0x7, 0x61,0x38,0x22,0x7d, -0xf2,0x7f,0x60,0x6d,0x22,0x2e,0x18,0x10,0x0, 0x71,0xe8,0x74,0x48,0x61,0xf, 0x71, -0x2a,0xe5,0x38,0x71,0x2a,0xe5,0x37,0x71,0x2a,0xe5,0x36,0x71,0x2a,0xe4,0x71,0x2a, -0x7f,0x6, 0x7d,0x3f,0x71,0x95,0xa9,0xd2,0xb4,0x22,0x7c,0x7b,0x7a,0x71,0xb5,0xa9, -0x36,0xb3,0xfc,0xa9,0xc6,0xb3,0xd3,0x22,0x7d,0xf2,0x7f,0x60,0x6d,0x22,0x2e,0x18, -0x4, 0x0, 0x71,0xe8,0x74,0x4b,0x61,0xf, 0xa9,0xc2,0xb4,0x74,0x90,0x71,0x2a,0xe4, -0x71,0x2a,0x71,0x2a,0x71,0x2a,0x7e,0x8, 0x0, 0x36,0x7e,0x34,0x0, 0x1, 0x71,0x24, -0xe5,0x36,0x22,0x7f,0x70,0x7f,0x1, 0x7d,0x30,0x7d,0x53,0xf5,0x3a,0x7c,0x72,0x7c, -0x61,0xa, 0x20,0x7d,0x53,0xf5,0x39,0x7d,0x51,0xf5,0x38,0xa9,0xc2,0xb4,0x74,0x3, -0x71,0x2a,0xe5,0x3a,0x71,0x2a,0xe5,0x39,0x71,0x2a,0xe5,0x38,0x71,0x2a,0x7f,0x7, -0x7e,0x35,0x36,0x61,0x24,0x7d,0x43,0x6d,0x33,0x80,0x13,0x75,0xb5,0x0, 0xa9,0x36, -0xb3,0xfc,0xa9,0xc6,0xb3,0xe5,0xb5,0x7a,0xb, 0xb0,0xb, 0x14,0xb, 0x34,0xbd,0x43, -0x38,0xe9,0x22,0x7d,0x42,0x7f,0x70,0x7d,0x53,0x7d,0x15,0x6d,0x0, 0xb, 0x4, 0x2e, -0x8, 0xf0,0x0, 0x74,0x1, 0x71,0xd3,0x7a,0x45,0x36,0x7f,0x10,0x7f,0x7, 0x71,0x63, -0xe4,0x61,0xd3,0x7c,0x7b,0xa9,0xc2,0xb4,0x4c,0x77,0x68,0x4, 0x74,0x3a,0x80,0x2, -0x74,0x4, 0x71,0x2a,0xa9,0xd2,0xb4,0x22,0x7d,0x12,0x7d,0x51,0xf5,0x38,0x7c,0x36, -0x7c,0x25,0xa, 0x4, 0x7d,0x51,0xf5,0x37,0x7d,0x53,0xf5,0x36,0xa9,0xc2,0xb4,0x22, -0x7e,0x8, 0x17,0xf6,0x7e,0x34,0x2, 0xd0,0xe4,0x12,0x20,0x12,0x7e,0x8, 0x18,0x27, -0x7e,0x34,0x0, 0xc8,0x74,0xff,0x12,0x20,0x12,0x7e,0x8, 0x18,0x4f,0x7e,0x34,0x0, -0xc8,0x12,0x20,0x12,0x7e,0x63,0x38,0xa2,0x7e,0x70,0x9, 0xac,0x67,0x7e,0x8, 0x19, -0xa7,0x2, 0x20,0x12,0xca,0xf8,0x7e,0x73,0x1c,0xea,0xa, 0x47,0x7e,0x73,0x1c,0xe3, -0xa, 0x57,0x2d,0x54,0x7e,0xa3,0x1c,0xe5,0xbc,0xab,0x28,0x2, 0x7c,0xba,0x7e,0xf3, -0x1c,0xe4,0x7e,0xa3,0x1c,0xe6,0xbc,0xaf,0x28,0x2, 0x7c,0xfa,0x75,0x24,0xb, 0x7e, -0x8, 0x1d,0x33,0x7e,0x18,0x1c,0xec,0x12,0x1a,0x34,0x75,0x24,0xb, 0x7e,0x8, 0x1d, -0x56,0x7e,0x18,0x1d,0xf, 0x7c,0xbf,0x12,0x1b,0x31,0xda,0xf8,0x22,0x7c,0x7b,0x7a, -0x73,0x1d,0x82,0xa5,0xbf,0x0, 0xa, 0x7e,0x1f,0x1e,0x16,0x7e,0xf, 0x1e,0x12,0x80, -0xc, 0xa5,0xbf,0x1, 0xb, 0x7e,0x1f,0x16,0xc5,0x7e,0xf, 0x16,0xc1,0x12,0x36,0xaa, -0x22,0x7f,0x71,0x7f,0x60,0x7e,0x73,0x1c,0xe6,0xa, 0x47,0x7e,0x73,0x1c,0xe5,0xa, -0x57,0x2d,0x54,0x3e,0x54,0x7c,0xab,0xe4,0x7a,0xb3,0x16,0xbe,0x7f,0x7, 0xa, 0x3a, -0x12,0x20,0x12,0x7f,0x6, 0xa, 0x3a,0x2, 0x20,0x12,0x7e,0xa3,0x35,0x40,0x7c,0xba, -0x4, 0x7a,0xb3,0x35,0x40,0x7a,0xa3,0x34,0xf2,0x22,0xca,0x7b,0xca,0x2b,0xca,0x1b, -0xca,0xb, 0xc0,0x83,0xc0,0x82,0x12,0x34,0x15,0xd0,0x82,0xd0,0x83,0xda,0xb, 0xda, -0x1b,0xda,0x2b,0xda,0x7b,0x32,0xa9,0xc0,0x93,0x75,0x61,0x0, 0x32,0x7c,0x7b,0x7a, -0x73,0x35,0x41,0x7c,0xb7,0xc4,0x54,0x7, 0xbe,0xb0,0x4, 0x68,0x3, 0xb4,0x2, 0x4, -0x74,0x3, 0x80,0x7, 0x60,0x3, 0xb4,0x1, 0x7, 0x74,0x1, 0x7a,0xb3,0x35,0x8, 0x22, -0x74,0x1, 0x7a,0xb3,0x35,0x8, 0xe4,0x7a,0xb3,0x35,0x41,0x22,0x7c,0x47,0x7c,0x5b, -0xa5,0xbd,0x9a,0x6, 0xb1,0x88,0x7a,0x43,0x36,0x3b,0xa5,0xbd,0x0, 0x6, 0x7c,0xb4, -0x91,0xfd,0x80,0x34,0xbe,0x50,0xeb,0x68,0x4, 0xa5,0xbd,0xec,0x8, 0x7c,0xb5,0x7c, -0x74,0xf1,0x75,0x80,0x23,0xa5,0xbd,0xee,0x6, 0x7a,0x43,0x1c,0x54,0x80,0x19,0xbe, -0x50,0x80,0x40,0x14,0xbe,0x50,0xdf,0x38,0xf, 0x7c,0xb5,0x24,0x80,0x7c,0x74,0xf1, -0x45,0xa5,0xbd,0x8f,0x3, 0x75,0x62,0x1, 0xa5,0xbd,0xfc,0x5, 0x7c,0xb4,0x2, 0x3c, -0x5f,0x74,0x1, 0x7a,0xb3,0x32,0x5d,0x22,0xe4,0x7a,0xb3,0x36,0x3c,0x74,0xa, 0x7a, -0xb3,0x36,0x3e,0xe4,0x7a,0xb3,0x36,0x3f,0x22,0xca,0xd8,0xca,0x79,0x6c,0xff,0x7e, -0xb3,0x1a,0xb5,0x70,0x28,0x7e,0xa3,0x36,0x3d,0xbe,0xa0,0x0, 0x28,0x1b,0x7e,0xb3, -0x36,0x3b,0x60,0x2, 0x80,0xa, 0x7e,0x37,0x1a,0xb9,0xbe,0x34,0x0, 0x14,0x50,0xd, -0x7c,0xba,0x14,0x7a,0xb3,0x36,0x3d,0x80,0x4, 0xc2,0x10,0xb1,0x88,0x6c,0xee,0x80, -0x16,0x7c,0xbe,0x12,0x4f,0xad,0x60,0xd, 0x7c,0xbe,0x12,0x2f,0xb, 0x7c,0xdb,0xbc, -0xdf,0x28,0x2, 0x7c,0xfd,0xb, 0xe0,0x12,0x4f,0xc3,0x38,0xe5,0x7c,0xbf,0xd1,0x14, -0xf1,0x1d,0x30,0x10,0x2, 0xd1,0xc9,0xb1,0xfe,0xda,0x79,0xda,0xd8,0x22,0x30,0x10, -0x12,0xd1,0xc1,0x68,0x6, 0x7e,0xb3,0x36,0x49,0x60,0x8, 0x7e,0x34,0xb, 0xb8,0x7a, -0x37,0x36,0x39,0x22,0x7c,0xab,0x7e,0xb3,0x36,0x3b,0x60,0xd, 0xbe,0xa0,0x1e,0x28, -0x2, 0x80,0x23,0x4c,0xaa,0x78,0x25,0x80,0x16,0xbe,0xa0,0x32,0x38,0x18,0x7e,0xb3, -0x36,0x3d,0x60,0x7, 0xbe,0xa0,0x23,0x28,0x2, 0x80,0xb, 0x4c,0xaa,0x78,0x3, 0xe4, -0x80,0x6, 0xd1,0x60,0x60,0x6, 0x74,0x14,0x7a,0xb3,0x36,0x3d,0x7e,0x73,0x36,0x3d, -0xbe,0x70,0x0, 0x28,0x8, 0xe4,0x7a,0xb3,0x1a,0xb5,0xd2,0x10,0x22,0xc2,0x10,0x22, -0x6c,0x77,0x7e,0x63,0x1c,0xe0,0x7e,0x53,0x1c,0xdf,0xac,0x56,0x7d,0x2, 0x1e,0x4, -0x7e,0x17,0x1a,0xbb,0xbe,0x14,0x2, 0xbc,0x58,0xc, 0x7d,0x10,0x3e,0x14,0xd1,0xba, -0x7d,0x1, 0x9e,0x4, 0x0, 0xa, 0x7e,0x17,0x1a,0xb9,0x2e,0x17,0x1a,0xb7,0xbd,0x10, -0x38,0xa, 0x1e,0x24,0x1e,0x24,0xbe,0x27,0x1a,0xb7,0x50,0x1b,0x7e,0x63,0x38,0x51, -0x1e,0x60,0xbe,0x63,0x18,0x92,0x50,0xf, 0x7e,0x63,0x38,0x50,0x1e,0x60,0xbe,0x63, -0x18,0x91,0x50,0x3, 0x7e,0x70,0x1, 0x7c,0xb7,0x22,0x7e,0x4, 0x0, 0x3, 0x8d,0x10, -0x22,0x7e,0xb3,0x1a,0xd9,0xbe,0xb0,0x1, 0x22,0x7e,0xb3,0x36,0x3b,0x60,0x18,0x7e, -0xb3,0x36,0x3c,0x70,0x12,0x7e,0xb3,0x36,0x3f,0x70,0xc, 0x74,0x1, 0x7a,0xb3,0x36, -0x3f,0x74,0xa, 0x7a,0xb3,0x36,0x3e,0x22,0xf1,0xa, 0x50,0x3, 0x6d,0x33,0x22,0x7e, -0x37,0x1a,0xbb,0xf1,0x16,0x7e,0x17,0x1c,0xcc,0xd1,0xba,0x7d,0x21,0x3e,0x24,0x2e, -0x27,0x1c,0xcc,0xbd,0x23,0x50,0x2, 0x7d,0x32,0x22,0x7e,0x73,0x1a,0xb5,0xbe,0x70, -0x2, 0x22,0x2d,0x30,0xb, 0x34,0x7e,0x24,0x0, 0x2, 0x2, 0x1d,0x4a,0x7e,0xb3,0x36, -0x3b,0x60,0x21,0x7e,0xb3,0x36,0x3c,0x70,0x1b,0x7e,0xb3,0x36,0x3f,0xb4,0x1, 0x14, -0x7e,0xb3,0x36,0x3e,0x14,0x7a,0xb3,0x36,0x3e,0x70,0x9, 0x74,0x1, 0x7a,0xb3,0x36, -0x3c,0x2, 0x47,0xf0,0x22,0x7c,0xa7,0x7c,0x7b,0x2e,0x70,0xdd,0x68,0x26,0x2e,0x70, -0xfd,0x68,0x21,0x1b,0x71,0x68,0x1d,0x1b,0x72,0x68,0x19,0x1b,0x71,0x68,0x15,0x1b, -0x70,0x68,0x11,0x2e,0x70,0xa, 0x78,0x4, 0x7a,0xa3,0x34,0xe0,0xa, 0x3b,0x19,0xa3, -0x34,0xe1,0xd2,0xe, 0x22,0x7c,0xa7,0xbe,0xb0,0xeb,0x68,0x3, 0xb4,0xec,0x35,0x7e, -0x37,0x35,0x94,0x4d,0x33,0x78,0xf, 0xbe,0xa0,0xaa,0x78,0xa, 0x7e,0x34,0x0, 0x1, -0x7a,0x37,0x35,0x94,0x15,0x63,0x7e,0x37,0x35,0x94,0xbe,0x34,0x0, 0x1, 0x78,0x11, -0xbe,0xa0,0x9, 0x78,0x6, 0x7e,0x34,0x0, 0x2, 0x80,0x2, 0x6d,0x33,0x7a,0x37,0x35, -0x94,0x75,0x63,0xea,0x22,0x7e,0xb3,0x35,0x96,0x4, 0x7a,0xb3,0x35,0x96,0xe5,0x62, -0xb4,0x1, 0x8, 0xe4,0x7a,0xb3,0x35,0x96,0x75,0x62,0x0, 0x7e,0x73,0x35,0x96,0x7a, -0x73,0x34,0xf0,0x22,0x7c,0x5b,0xa5,0xbd,0x9a,0x5, 0x7e,0xb3,0x36,0x3b,0x22,0xa5, -0xbd,0x9b,0x5, 0x7e,0xb3,0x36,0x3c,0x22,0xa5,0xbd,0x0, 0x5, 0x7e,0xb3,0x35,0x41, -0x22,0xbe,0x50,0x3, 0x38,0x16,0x75,0x1f,0x0, 0x30,0x9, 0x6, 0x7e,0x34,0x2f,0xa0, -0x80,0x4, 0x7e,0x34,0x2f,0xde,0x7a,0x37,0x30,0x1c,0x80,0x8, 0xbe,0x50,0x5e,0x38, -0xe, 0x75,0x1f,0x0, 0xa, 0x35,0x2e,0x37,0x30,0x1c,0x9, 0xb3,0xff,0xff,0x22,0xa5, -0xbd,0xa0,0x3, 0x74,0xb, 0x22,0xbe,0x50,0x80,0x40,0xc, 0xbe,0x50,0xdf,0x38,0x7, -0xa, 0x35,0x9, 0xb3,0x34,0x61,0x22,0xbe,0x50,0xeb,0x68,0x4, 0xa5,0xbd,0xec,0x4, -0x7c,0xb5,0x1, 0x7d,0xa5,0xbd,0xee,0x5, 0x7e,0xb3,0x1c,0x54,0x22,0xa5,0xbd,0xfc, -0x5, 0x7e,0xb3,0x35,0x8, 0x22,0xa5,0xbd,0xfd,0x17,0x6c,0xaa,0x7e,0xb3,0x1a,0xd9, -0x60,0x3, 0x7e,0xa0,0x1, 0x7e,0xb3,0x34,0x8, 0x60,0x3, 0x4e,0xa0,0x2, 0x7c,0xba, -0x22,0xa5,0xbd,0xfe,0x5, 0x7e,0xb3,0x1d,0x93,0x22,0x74,0xff,0x22,0x7c,0x7b,0xa5, -0xbf,0xeb,0x5, 0xe4,0x7a,0xb3,0x35,0x97,0x7e,0x73,0x35,0x97,0xa, 0x27,0x2e,0x24, -0x0, 0x25,0x11,0xb5,0x7c,0xab,0x7c,0xb7,0x4, 0x7a,0xb3,0x35,0x97,0xb4,0x3, 0xb, -0xe4,0x7a,0xb3,0x35,0x97,0x6d,0x33,0x7a,0x37,0x35,0x94,0x75,0x63,0xeb,0x7c,0xba, -0x22,0x2e,0x24,0x1f,0xc9,0x7a,0x51,0x82,0x7a,0x41,0x83,0xe4,0x93,0x22,0xd2,0x4, -0x7e,0xb3,0x34,0xe9,0xb4,0x12,0x1a,0x7e,0x73,0x1c,0x48,0xbe,0x70,0x0, 0x28,0x11, -0x7e,0xb3,0x18,0x94,0x70,0xb, 0x7e,0x73,0x18,0x92,0xbe,0x70,0x14,0x50,0x2, 0xc2, -0x4, 0xa2,0xd, 0x30,0x4, 0x1, 0xb3,0x50,0x12,0x30,0x4, 0x3, 0x2, 0x24,0xae,0x31, -0x5, 0x11,0xfc,0x12,0x27,0xd3,0x12,0x27,0xcb,0xc2,0xd, 0x22,0x7e,0x34,0x0, 0x1, -0x7e,0x24,0x7, 0xc2,0x22,0xe4,0x7a,0xb3,0x36,0x0, 0x7a,0xb3,0x36,0x1, 0x7a,0xb3, -0x36,0x2, 0x22,0x6d,0x33,0x7e,0x24,0x6, 0x84,0x12,0x27,0xd3,0x11,0xfc,0x2, 0x27, -0xd3,0x31,0x38,0x38,0x2, 0xe4,0x22,0x31,0x97,0x49,0x55,0x36,0x3, 0xbe,0xb0,0x2, -0x38,0x3, 0x2, 0x44,0xdc,0x2, 0x67,0xdc,0x7e,0x73,0x36,0x0, 0xbe,0x73,0x36,0x1, -0x22,0x30,0x1b,0x8, 0x74,0x6, 0x7e,0x70,0x99,0x12,0x1c,0x5c,0x7e,0xb3,0x36,0x2, -0xb4,0x1, 0x43,0x31,0x97,0x49,0x35,0x36,0x3, 0x49,0x15,0x36,0x5, 0x6d,0x0, 0xbe, -0x8, 0x0, 0x0, 0x68,0x11,0xbe,0x70,0x0, 0x40,0xc, 0xbe,0x70,0x2, 0x38,0x7, 0x74, -0x1, 0x12,0x0, 0xe, 0x31,0xa1,0x7e,0xb3,0x36,0x1, 0x4, 0x7a,0xb3,0x36,0x1, 0x31, -0x38,0x28,0xd, 0x31,0x21,0xb4,0x1, 0x4, 0x74,0x1, 0x80,0x6, 0x74,0x3, 0x80,0x2, -0x74,0x2, 0x7a,0xb3,0x36,0x2, 0x22,0x7e,0xb3,0x36,0x1, 0x7e,0x70,0x4, 0xac,0xb7, -0x22,0x7e,0xb3,0x1c,0xe5,0x7e,0x73,0x1c,0xe6,0x2, 0xe, 0x24,0x7e,0xb3,0x36,0x2, -0xb4,0x1, 0x2, 0xc3,0x22,0xd3,0x22,0x31,0xac,0x50,0xfc,0x22,0x7c,0xbf,0x7c,0x7d, -0x7c,0x6e,0xca,0x79,0x7c,0x36,0x7c,0x27,0x7c,0x1b,0x7e,0x0, 0xff,0x6c,0x99,0x80, -0x2c,0xbc,0x91,0x68,0x26,0x12,0x2f,0xbd,0xa, 0x28,0x51,0x11,0x7c,0x87,0x12,0x2f, -0xc6,0xa, 0x27,0x71,0x83,0x7c,0xf7,0xbc,0xf8,0x50,0x4, 0x7c,0xe8,0x80,0x2, 0x7c, -0xef,0xbc,0xe, 0x28,0x2, 0x7c,0xe, 0x4c,0xee,0x68,0x7, 0xb, 0x90,0x12,0x4f,0xca, -0x38,0xcf,0x7c,0xb0,0xda,0x79,0x22,0x7e,0x23,0x18,0x97,0xa, 0x22,0x7e,0x23,0x18, -0x95,0xa, 0x32,0x9d,0x32,0x2, 0x20,0x54,0x7e,0x33,0x1a,0xb5,0xa5,0xbb,0x2, 0x2, -0x80,0x2, 0x41,0xea,0x7e,0xb3,0x32,0xfe,0x60,0x2, 0x41,0xea,0xe5,0x19,0x70,0x2e, -0x51,0x7, 0xbe,0x34,0x0, 0x1, 0x18,0xf, 0x71,0x11,0x7e,0x23,0x18,0x96,0x51,0x11, -0x71,0x2b,0x75,0x14,0x1, 0x80,0x55,0x71,0x11,0x7e,0x23,0x18,0x96,0x51,0x11,0xbe, -0x34,0x0, 0x1, 0x18,0x47,0x51,0x7, 0x71,0x2b,0x75,0x15,0x1, 0x80,0x3e,0xe5,0x14, -0xb4,0x1, 0x1a,0x51,0x7, 0xbe,0x34,0x0, 0x1, 0x18,0x10,0x71,0x11,0x7e,0x23,0x18, -0x96,0x51,0x11,0x7c,0xb7,0xf5,0x18,0x5, 0x16,0x80,0x2, 0x71,0x18,0xe5,0x15,0xb4, -0x1, 0x1a,0x71,0x11,0x7e,0x23,0x18,0x96,0x51,0x11,0xbe,0x34,0x0, 0x1, 0x18,0xa, -0x51,0x7, 0x7c,0xb7,0xf5,0x18,0x5, 0x16,0x80,0x2, 0x71,0x18,0xe5,0x16,0xbe,0xb0, -0x14,0x28,0x3, 0x75,0x16,0x14,0xe5,0x17,0xbe,0xb0,0x5, 0x28,0x5, 0x7e,0xa0,0x4, -0x80,0x1a,0xe5,0x17,0xbe,0xb0,0x3, 0x28,0x5, 0x7e,0xa0,0x2, 0x80,0xe, 0xe5,0x17, -0xbe,0xb0,0x1, 0x28,0x5, 0x7e,0xa0,0x1, 0x80,0x2, 0x6c,0xaa,0xe5,0x16,0xbe,0xb0, -0x5, 0x28,0x3d,0xa, 0x3a,0xe5,0x17,0xa, 0x2b,0x9d,0x23,0xe5,0x18,0xa, 0x3b,0xbd, -0x32,0x18,0x2d,0x74,0x1, 0x7a,0xb3,0x32,0xfe,0x22,0x4c,0x33,0x68,0x5, 0xbe,0x30, -0x2, 0x28,0x7, 0xe4,0x7a,0xb3,0x32,0xfe,0x61,0x18,0xa5,0xbb,0x1, 0x12,0x7e,0xb3, -0x32,0xfe,0x70,0xc, 0xf5,0x17,0xf5,0x18,0xf5,0x16,0xf5,0x19,0xf5,0x15,0xf5,0x14, -0x22,0x7e,0x23,0x18,0x98,0xa, 0x22,0x22,0x75,0x17,0x0, 0x75,0x18,0x0, 0x75,0x16, -0x0, 0x75,0x19,0x0, 0x75,0x15,0x0, 0x75,0x14,0x0, 0x22,0x7c,0xb7,0xf5,0x17,0x75, -0x19,0x1, 0x22,0x7c,0xa6,0x7c,0x37,0x7c,0x2b,0xe4,0x6c,0x11,0x80,0x3c,0xbc,0xa1, -0x68,0x36,0x1a,0x41,0x3e,0x44,0x9, 0x4, 0x18,0x96,0xa, 0x20,0x71,0x83,0x7c,0x7, -0x1a,0x41,0x3e,0x44,0x9, 0x74,0x18,0x95,0xa, 0x27,0x51,0x11,0x7c,0x97,0xbe,0x90, -0x1, 0x18,0x8, 0xbe,0x0, 0x1, 0x18,0x3, 0x74,0x1, 0x22,0xbe,0x90,0x2, 0x18,0x8, -0xbe,0x0, 0x2, 0x18,0x3, 0x74,0x2, 0x22,0xb, 0x10,0x7e,0x83,0x1a,0xb5,0xbc,0x81, -0x18,0xbc,0x22,0xa, 0x33,0x9d,0x32,0x2, 0x20,0x54,0xca,0x3b,0x6c,0xdd,0x6c,0xcc, -0xc2,0x3, 0x7e,0xe0,0x3, 0xb1,0x45,0x7e,0xa3,0x18,0x1f,0xbe,0xa0,0x1, 0x78,0xc, -0x7e,0xb3,0x18,0x20,0xbe,0xb0,0x1, 0x28,0x3, 0x7e,0xd0,0x1, 0x7e,0xb3,0x18,0x20, -0xb4,0x1, 0x8, 0xbe,0xa0,0x1, 0x28,0x3, 0x7e,0xc0,0x1, 0xbe,0xd0,0x1, 0x68,0x5, -0xbe,0xc0,0x1, 0x78,0x7f,0x6c,0xff,0x7e,0x70,0x7, 0xac,0x7f,0x9, 0xb3,0x2e,0xfd, -0xbe,0xb0,0xff,0x68,0x68,0xbe,0xd0,0x1, 0x78,0x31,0x9, 0xb3,0x2f,0x2, 0xbe,0xb0, -0x0, 0x8, 0xa, 0x7d,0x23,0x2e,0x24,0x2f,0x2, 0x14,0x7a,0x29,0xb0,0x9, 0xb3,0x2f, -0x0, 0x1a,0x1b,0x7e,0xa3,0x1c,0xe1,0xa, 0x2a,0x1b,0x24,0xbd,0x12,0x58,0x3e,0x7d, -0x23,0x2e,0x24,0x2f,0x0, 0x4, 0x7a,0x29,0xb0,0x80,0x32,0xbe,0xc0,0x1, 0x78,0x2d, -0x9, 0xb3,0x2f,0x3, 0xbe,0xb0,0x0, 0x8, 0xa, 0x7d,0x23,0x2e,0x24,0x2f,0x3, 0x14, -0x7a,0x29,0xb0,0x9, 0xb3,0x2f,0x1, 0x1a,0x1b,0x7e,0xa3,0x1c,0xe2,0xa, 0x2a,0x1b, -0x24,0xbd,0x12,0x58,0x8, 0x2e,0x34,0x2f,0x1, 0x4, 0x7a,0x39,0xb0,0xb, 0xf0,0xbe, -0xf0,0xa, 0x78,0x83,0x7e,0x34,0x0, 0x1e,0xca,0x39,0x7e,0x18,0x0, 0xff,0x7e,0x8, -0x33,0x22,0x12,0x1f,0xed,0x1b,0xfd,0x6c,0xff,0x80,0xd, 0x7c,0xbf,0x12,0x84,0x5a, -0xa, 0x3f,0x19,0xb3,0x33,0x22,0xb, 0xf0,0x12,0x4d,0xcc,0x38,0xee,0x7e,0xd3,0x1c, -0x48,0x7e,0x24,0x2, 0x8f,0x7a,0x27,0x33,0x1e,0xbe,0x70,0x1, 0x38,0x2, 0xa1,0x3a, -0x74,0x3, 0x12,0xb6,0x3f,0x4c,0xdd,0x68,0xe, 0x7e,0xa3,0x32,0xf2,0x4c,0xaa,0x78, -0xa, 0x7e,0xb3,0x32,0xf3,0x70,0x4, 0xd2,0x3, 0x80,0x22,0xbe,0xd0,0x1, 0x28,0xb, -0xe5,0x1a,0xbe,0xb0,0x8, 0x28,0x4, 0xd2,0x3, 0x80,0x12,0xd2,0x3, 0x7e,0xb3,0x1a, -0xb5,0xbc,0xbd,0x78,0x8, 0x4c,0xaa,0x78,0x4, 0x6c,0xee,0xc2,0x3, 0x20,0x3, 0x5, -0x7c,0xbe,0x12,0xb6,0x3f,0x7e,0x8, 0x33,0x0, 0x12,0x2d,0x38,0x7a,0xb3,0x32,0xfd, -0xbe,0xb3,0x1a,0xb5,0x50,0x41,0x7e,0x33,0x32,0xfd,0x80,0x2d,0x7e,0x70,0x2, 0xac, -0x73,0x9, 0x23,0x33,0x40,0x9, 0x13,0x33,0x41,0x2e,0x37,0x33,0x1e,0xb, 0x38,0x40, -0x7e,0xb3,0x1c,0xe0,0xac,0xb2,0xa, 0x31,0x2d,0x53,0x3e,0x54,0xf1,0xc4,0x1b,0x1a, -0x40,0x7c,0xb3,0x7e,0x70,0x1, 0x12,0x28,0xdd,0x7c,0x3, 0x1b,0x30,0xa5,0xb8,0x0, -0xcb,0x74,0x1, 0x7a,0xb3,0x32,0xf5,0x7e,0xb3,0x32,0xfd,0x7a,0xb3,0x1a,0xb5,0x7e, -0x70,0x2, 0xac,0xb7,0xca,0x59,0x7e,0x18,0x33,0x40,0x7e,0x8, 0x18,0x95,0x12,0x1f, -0xed,0x1b,0xfd,0x12,0xa6,0xc7,0xf5,0x1a,0x80,0x3, 0x75,0x1a,0x64,0x51,0x18,0x12, -0x4a,0x60,0xda,0x3b,0x22,0x7e,0x8, 0x18,0x21,0x7e,0x34,0x0, 0x3, 0xe4,0x12,0x20, -0x12,0x7e,0x8, 0x18,0x24,0x7e,0x34,0x0, 0x3, 0x12,0x20,0x12,0x7a,0xb3,0x18,0x1e, -0x7a,0xb3,0x18,0x1f,0x7a,0xb3,0x18,0x20,0x7a,0xb3,0x18,0x8b,0x7a,0xb3,0x18,0x8c, -0x7a,0xb3,0x18,0x8d,0x7e,0x18,0x18,0xa, 0xf1,0x6b,0x6c,0x55,0xd1,0x3, 0x7a,0xb3, -0x18,0x20,0x7e,0x18,0x17,0xf6,0xf1,0xa7,0x6c,0x55,0xd1,0x3, 0x7a,0xb3,0x18,0x1f, -0x6c,0x77,0x80,0x15,0xf1,0x57,0x60,0x5, 0x3e,0x24,0x14,0x78,0xfb,0x7c,0xa5,0x7c, -0xb7,0xf1,0x50,0x2e,0x24,0x18,0x21,0xf1,0x60,0x7e,0x63,0x18,0x1f,0xbc,0x67,0x38, -0xe3,0x6c,0x77,0x80,0x15,0xf1,0x57,0x60,0x5, 0x3e,0x24,0x14,0x78,0xfb,0x7c,0xa5, -0x7c,0xb7,0xf1,0x50,0x2e,0x24,0x18,0x24,0xf1,0x60,0x7e,0xa3,0x18,0x20,0xbc,0xa7, -0x38,0xe3,0x7e,0xb3,0x18,0x1f,0xa4,0x7a,0xb3,0x18,0x1e,0x7e,0x18,0x18,0x81,0xf1, -0x6b,0x7e,0x50,0x1, 0xd1,0x3, 0x7a,0xb3,0x18,0x8d,0x7e,0x18,0x18,0x77,0xf1,0xa7, -0x7e,0x50,0x1, 0xd1,0x3, 0x7a,0xb3,0x18,0x8c,0x7e,0xa3,0x18,0x8d,0xa4,0x7a,0xb3, -0x18,0x8b,0x22,0xca,0x79,0x7c,0xe5,0x7d,0xd3,0x7c,0xfb,0x7f,0x70,0x6c,0x33,0x6d, -0xcc,0x6c,0x22,0xe1,0x3c,0x74,0x2, 0xac,0xb2,0x7f,0x57,0x2d,0xb5,0xb, 0x5a,0x0, -0x4c,0xee,0x68,0x6, 0x6e,0x4, 0xff,0xff,0xb, 0x4, 0xbd,0xd0,0x48,0x2, 0xe1,0x3a, -0xa5,0xba,0x0, 0x8, 0x6d,0x44,0x69,0xc7,0x0, 0x2, 0x80,0x16,0xa, 0x3f,0x1b,0x34, -0xa, 0x52,0xbd,0x53,0x78,0x6, 0xf1,0x8b,0x6d,0xcc,0x80,0x6, 0xf1,0x8b,0x69,0xc5, -0x0, 0x2, 0x4c,0xee,0x68,0xc, 0x6e,0x44,0xff,0xff,0xb, 0x44,0x6e,0xc4,0xff,0xff, -0xb, 0xc4,0xbd,0x40,0x48,0x2, 0xe1,0x3a,0xbd,0xc0,0x8, 0x2, 0xe1,0x3a,0x75,0x2a, -0x1, 0x4c,0xee,0x68,0x2, 0xe1,0x21,0xf1,0x9c,0x12,0x1d,0x4a,0xbd,0x3c,0x58,0x2c, -0xa, 0x3f,0x1b,0x34,0xa, 0x52,0xb, 0x55,0xbd,0x53,0x18,0x20,0x69,0x35,0x0, 0x4, -0xbd,0x3c,0x8, 0x18,0xbd,0x3d,0x8, 0x14,0x12,0x6f,0x12,0x79,0x35,0x0, 0x2, 0xf1, -0x47,0x69,0xc1,0x0, 0x2, 0xbd,0xc0,0x8, 0x3, 0x75,0x2a,0x0, 0xf1,0x9c,0x12,0x1d, -0x4a,0xbd,0x34,0x58,0x2e,0xbe,0x20,0x2, 0x40,0x29,0xf1,0x47,0x1b,0x36,0xb, 0x1a, -0x30,0xbd,0x34,0x8, 0x1e,0xbd,0x3d,0x8, 0x1a,0x12,0x6f,0x12,0x7d,0x43,0xf1,0x47, -0x1b,0x35,0x1b,0x1a,0x40,0xf1,0x47,0x1b,0x35,0xb, 0x1a,0x40,0xbd,0x40,0x8, 0x3, -0x75,0x2a,0x0, 0x75,0x29,0x0, 0x80,0x2e,0x7e,0x73,0x1c,0xdf,0xbc,0x7f,0x78,0xe, -0xf1,0x7b,0x9, 0x75,0x18,0x95,0xf1,0x93,0xbe,0x34,0x0, 0x3, 0x48,0x1c,0x7e,0x73, -0x1c,0xe0,0xbc,0x7f,0x78,0xe, 0xf1,0x7b,0x9, 0x75,0x18,0x96,0xf1,0x93,0xbe,0x34, -0x0, 0x3, 0x48,0x6, 0x5, 0x29,0xf1,0x83,0x38,0xce,0xf1,0x83,0x38,0x3, 0x75,0x2a, -0x0, 0xe5,0x2a,0xb4,0x1, 0xc, 0xa, 0x53,0x7e,0x1d,0x24,0x2d,0x35,0x7a,0x1b,0x20, -0xb, 0x30,0x7e,0x73,0x38,0xa3,0xbc,0x73,0x28,0x8, 0xb, 0x20,0xbc,0xf2,0x28,0x2, -0xc1,0x15,0x7c,0xb3,0xda,0x79,0x22,0x74,0x2, 0xac,0xb2,0x7f,0x17,0x2d,0x35,0x22, -0xc4,0x23,0x54,0x1f,0xa, 0x2b,0x22,0x7c,0xb7,0x54,0x7, 0x7e,0x24,0x0, 0x1, 0x22, -0x7e,0x29,0x60,0x4c,0x6a,0x7a,0x29,0x60,0xb, 0x70,0x22,0x7a,0x1d,0x24,0x7e,0xf, -0x6, 0x80,0x7e,0xb3,0x1c,0xe0,0x7e,0x37,0x1c,0xc5,0x22,0x7e,0x71,0x29,0x74,0x2, -0xac,0xb7,0x22,0x7e,0x73,0x1a,0xb5,0xbe,0x71,0x29,0x22,0x7f,0x15,0x1b,0x35,0xb, -0x1a,0x40,0x22,0xa, 0x37,0xa, 0x22,0x9d,0x32,0x2, 0x20,0x54,0x7e,0x34,0x0, 0x3, -0xad,0x30,0x7e,0x24,0x0, 0x4, 0x22,0x7a,0x1d,0x24,0x7e,0xb3,0x1c,0xe0,0x7e,0x70, -0x2, 0xac,0xb7,0x7e,0xf, 0x6, 0x80,0x2d,0x15,0x7e,0xb3,0x1c,0xdf,0x7e,0x37,0x1c, -0xc3,0x22,0x2d,0x53,0x7e,0x1f,0x13,0x68,0x2d,0x35,0x22,0xca,0x3b,0x7c,0xfb,0x75, -0x2a,0x0, 0x75,0x2b,0x0, 0x7e,0x34,0x22,0xdf,0x7e,0x24,0x0, 0xff,0x7e,0x14,0x3, -0x32,0x74,0x51,0x12,0x1e,0x3e,0x12,0xce,0xb2,0xf5,0x2c,0x9, 0xc3,0x18,0x96,0x12, -0x4f,0xe9,0xb, 0xf4,0x7d,0xef,0xe, 0xe4,0xe, 0xe4,0x7d,0xdf,0xe, 0xd4,0xe, 0xd4, -0xe, 0xd4,0xbe,0xd4,0x0, 0x50,0x8, 0x4, 0x7e,0xd4,0x0, 0x50,0xe5,0x2c,0xa, 0x3b, -0xb, 0x36,0x7e,0xa3,0x1c,0xdf,0xa, 0xca,0xbd,0x3c,0x58,0xc, 0xe5,0x2c,0xa, 0xcb, -0xb, 0xc6,0x7d,0x3c,0x7c,0xb7,0x80,0x4, 0xa, 0x5a,0x1b,0x54,0xf5,0x2d,0xe5,0x2c, -0xbe,0xb0,0x4, 0x40,0x8, 0xe5,0x2c,0xa, 0x5b,0x1b,0x56,0x80,0x1, 0xe4,0xf5,0x2e, -0xa, 0x3c,0xb, 0x36,0x7e,0xa3,0x1c,0xe0,0xa, 0xca,0xbd,0x3c,0x58,0xa, 0xa, 0xcc, -0xb, 0xc6,0x7d,0x3c,0x7c,0xb7,0x80,0x4, 0xa, 0x5a,0x1b,0x54,0xf5,0x2f,0xbe,0xc0, -0x4, 0x40,0x6, 0xa, 0x5c,0x1b,0x56,0x80,0x1, 0xe4,0xf5,0x30,0x74,0x2, 0x7a,0xb3, -0x3, 0x5a,0x7e,0xc7,0x1a,0xbb,0xbe,0xc4,0x2, 0xee,0x58,0xa, 0x7e,0xc7,0x1a,0xbf, -0xbe,0xc4,0xff,0x9c,0x48,0xa, 0x7e,0xc7,0x1a,0xbf,0xbe,0xc4,0xff,0x38,0x58,0x3, -0x75,0x2b,0x1, 0xe5,0x2c,0xa, 0xcb,0xb, 0xc4,0x7d,0x3c,0x7c,0xd7,0x41,0x35,0xe5, -0x2c,0xa, 0x2b,0xa, 0x3d,0x9d,0x32,0x7a,0x71,0x31,0xbc,0x7c,0x50,0xa, 0xe5,0x31, -0xa, 0x4b,0xa, 0x5c,0x9d,0x54,0x80,0x1, 0xe4,0xf5,0x32,0xe5,0x31,0x12,0xcd,0xc3, -0x58,0x7, 0xe5,0x31,0x12,0xce,0xa7,0x80,0x4, 0xa, 0x5a,0x1b,0x54,0xf5,0x33,0x7e, -0xe1,0x32,0x41,0x2b,0x12,0x71,0xbc,0xf5,0x3d,0x75,0x3e,0x0, 0x12,0xcd,0xf9,0x7d, -0x5c,0x9d,0x54,0xf5,0x3f,0x12,0xcd,0xf0,0x9d,0x52,0xf5,0x40,0x12,0xbe,0x88,0xbd, -0x3c,0x8, 0x8, 0xe5,0x2c,0xa, 0x2b,0xa, 0x3d,0x80,0x4, 0xa, 0x2c,0xa, 0x3e,0x12, -0xce,0x2, 0xf5,0x41,0x12,0xcd,0xb5,0x9, 0xac,0x3, 0x32,0x7a,0xa1,0x42,0x9, 0xbc, -0x3, 0x29,0xf5,0x43,0xbe,0xa0,0x0, 0x28,0x2, 0x41,0x29,0x12,0xcd,0x5b,0xbd,0x3d, -0x58,0x2, 0x41,0x29,0x12,0xcd,0x5b,0xbd,0x3f,0x48,0x2, 0x41,0x29,0xe5,0x3d,0x70, -0x2, 0x41,0x29,0xe5,0x3d,0xbe,0xb0,0x4, 0x28,0xc, 0xe5,0x2b,0xb4,0x1, 0x7, 0x12, -0x4f,0xd1,0x28,0x2, 0x41,0x6, 0xe5,0x43,0xbe,0xb0,0x0, 0x28,0x7, 0x12,0x2e,0xe0, -0x58,0x2, 0x41,0x6, 0xe5,0x43,0xb4,0x2, 0x9, 0xe5,0x41,0xbe,0xb1,0x3d,0x50,0x2, -0x41,0x6, 0xe5,0x32,0xbc,0xbe,0x78,0x4d,0x12,0xcd,0xb5,0x9, 0xbc,0x3, 0x33,0xf5, -0x44,0x9, 0xbc,0x3, 0x2a,0xf5,0x45,0x12,0xce,0xa, 0x7d,0x43,0x12,0x2e,0xec,0x18, -0x7, 0xe5,0x44,0xbe,0xb0,0x0, 0x38,0x7e,0x12,0xce,0x50,0xb, 0x34,0x12,0x2e,0xe6, -0x18,0x9, 0xe5,0x45,0xbe,0xb0,0x0, 0x28,0x2, 0x80,0x6b,0xe5,0x44,0xbe,0xb0,0x2, -0x68,0x5, 0xe5,0x45,0xb4,0x2, 0x62,0xe5,0x41,0xbe,0xb1,0x3d,0x50,0x5b,0xe5,0x2b, -0xb4,0x1, 0x56,0x80,0x51,0xe5,0x33,0xbc,0xbe,0x78,0x4e,0x12,0xcd,0xb5,0x9, 0xbc, -0x3, 0x31,0xf5,0x44,0x9, 0xbc,0x3, 0x28,0xf5,0x45,0x12,0xce,0x13,0x7d,0x43,0x12, -0x2e,0xec,0x18,0x7, 0xe5,0x44,0xbe,0xb0,0x0, 0x38,0x2b,0x12,0xce,0x50,0x1b,0x34, -0x12,0x2e,0xe6,0x18,0x9, 0xe5,0x45,0xbe,0xb0,0x0, 0x28,0x2, 0x80,0x18,0xe5,0x44, -0xbe,0xb0,0x2, 0x68,0x5, 0xe5,0x45,0xb4,0x2, 0xf, 0xe5,0x41,0xbe,0xb1,0x3d,0x50, -0x8, 0xe5,0x2b,0xb4,0x1, 0x3, 0x75,0x3e,0x1, 0xe5,0x3e,0xb4,0x1, 0x1b,0x12,0xcd, -0x5b,0xbd,0x3e,0x8, 0x5, 0x7e,0x70,0x2, 0x80,0x3, 0x7e,0x70,0x1, 0x7e,0x51,0x3f, -0x74,0x9, 0xac,0x5b,0xe5,0x40,0x12,0xcd,0xe7,0xb, 0xe0,0xe5,0x33,0xbc,0xbe,0x40, -0x2, 0x1, 0xd4,0xb, 0xd0,0xe5,0x2d,0xbc,0xbd,0x40,0x2, 0x1, 0x9f,0xe5,0x2c,0xbe, -0xb0,0x0, 0x38,0x2, 0x61,0xfa,0xe5,0x2c,0xa, 0xcb,0x1b,0xc4,0x7d,0x3c,0x7c,0xd7, -0x61,0xf2,0xa, 0x2d,0xe5,0x2c,0xa, 0x3b,0x9d,0x32,0x7a,0x71,0x34,0xbc,0x7c,0x50, -0xa, 0xe5,0x34,0xa, 0x4b,0xa, 0x5c,0x9d,0x54,0x80,0x1, 0xe4,0xf5,0x35,0xe5,0x34, -0x12,0xcd,0xc3,0x58,0x7, 0xe5,0x34,0x12,0xce,0xa7,0x80,0x4, 0xa, 0x5a,0x1b,0x54, -0xf5,0x36,0x7e,0xe1,0x35,0x61,0xe2,0x12,0x71,0xbc,0xf5,0x46,0x75,0x47,0x0, 0x12, -0xcd,0xf9,0x7d,0x5c,0x9d,0x54,0xf5,0x48,0x12,0xcd,0xf0,0x9d,0x52,0xf5,0x49,0x12, -0xbe,0x88,0xbd,0x3c,0x8, 0x8, 0xe5,0x2c,0xa, 0x2b,0xa, 0x3d,0x80,0x4, 0xa, 0x2c, -0xa, 0x3e,0x12,0xce,0x2, 0xf5,0x4a,0x12,0xcd,0xa7,0x9, 0xac,0x3, 0x32,0x7a,0xa1, -0x4b,0x9, 0xbc,0x3, 0x3b,0xf5,0x4c,0xbe,0xa0,0x0, 0x28,0x2, 0x61,0xe0,0x12,0xcd, -0x5b,0xbd,0x3d,0x58,0x2, 0x61,0xe0,0x12,0xcd,0x5b,0xbd,0x3f,0x48,0x2, 0x61,0xe0, -0xe5,0x46,0x70,0x2, 0x61,0xe0,0xe5,0x46,0xbe,0xb0,0x4, 0x28,0xc, 0xe5,0x2b,0xb4, -0x1, 0x7, 0x12,0x4f,0xd1,0x28,0x2, 0x61,0xbd,0xe5,0x4c,0xbe,0xb0,0x0, 0x28,0xb, -0xa, 0x5d,0xb, 0x54,0x12,0x2e,0xe4,0x58,0x2, 0x61,0xbd,0xe5,0x4c,0xb4,0x2, 0x9, -0xe5,0x4a,0xbe,0xb1,0x46,0x50,0x2, 0x61,0xbd,0xe5,0x35,0xbc,0xbe,0x78,0x4d,0x12, -0xcd,0xa7,0x9, 0xbc,0x3, 0x33,0xf5,0x4d,0x9, 0xbc,0x3, 0x3c,0xf5,0x4e,0x12,0xce, -0xa, 0x7d,0x43,0x12,0x2e,0xec,0x18,0x7, 0xe5,0x4d,0xbe,0xb0,0x0, 0x38,0x7e,0x12, -0xce,0x57,0xb, 0x34,0x12,0x2e,0xe6,0x18,0x9, 0xe5,0x4e,0xbe,0xb0,0x0, 0x28,0x2, -0x80,0x6b,0xe5,0x4d,0xbe,0xb0,0x2, 0x68,0x5, 0xe5,0x4e,0xb4,0x2, 0x62,0xe5,0x4a, -0xbe,0xb1,0x46,0x50,0x5b,0xe5,0x2b,0xb4,0x1, 0x56,0x80,0x51,0xe5,0x36,0xbc,0xbe, -0x78,0x4e,0x12,0xcd,0xa7,0x9, 0xbc,0x3, 0x31,0xf5,0x4d,0x9, 0xbc,0x3, 0x3a,0xf5, -0x4e,0x12,0xce,0x13,0x7d,0x43,0x12,0x2e,0xec,0x18,0x7, 0xe5,0x4d,0xbe,0xb0,0x0, -0x38,0x2b,0x12,0xce,0x57,0x1b,0x34,0x12,0x2e,0xe6,0x18,0x9, 0xe5,0x4e,0xbe,0xb0, -0x0, 0x28,0x2, 0x80,0x18,0xe5,0x4d,0xbe,0xb0,0x2, 0x68,0x5, 0xe5,0x4e,0xb4,0x2, -0xf, 0xe5,0x4a,0xbe,0xb1,0x46,0x50,0x8, 0xe5,0x2b,0xb4,0x1, 0x3, 0x75,0x47,0x1, -0xe5,0x47,0xb4,0x1, 0x1b,0x12,0xcd,0x5b,0xbd,0x3e,0x8, 0x5, 0x7e,0x70,0x2, 0x80, -0x3, 0x7e,0x70,0x1, 0x7e,0x51,0x48,0x74,0x9, 0xac,0x5b,0xe5,0x49,0x12,0xcd,0xe7, -0xb, 0xe0,0xe5,0x36,0xbc,0xbe,0x40,0x2, 0x41,0x87,0xe5,0x2e,0xbc,0xbd,0x68,0xa, -0x1b,0xd0,0xe5,0x2e,0xbc,0xbd,0x38,0x2, 0x41,0x52,0xa, 0xcc,0xb, 0xc4,0x7d,0x3c, -0x7c,0xe7,0xa1,0x98,0xa, 0x2c,0xa, 0x3e,0x9d,0x32,0x7a,0x71,0x37,0xbe,0x71,0x2c, -0x50,0x7, 0xe5,0x37,0x12,0xcf,0x4b,0x80,0x1, 0xe4,0xf5,0x38,0xe5,0x37,0x12,0xce, -0x6b,0x12,0xcd,0xcd,0x58,0x7, 0xe5,0x37,0x12,0xce,0x5e,0x80,0x4, 0xa, 0x5a,0x1b, -0x54,0xf5,0x39,0x7e,0xd1,0x38,0xa1,0x8e,0x12,0x71,0xbc,0xf5,0x4f,0x75,0x50,0x0, -0x12,0xcd,0xf9,0x7d,0x5c,0x9d,0x54,0xf5,0x51,0x12,0xcd,0xf0,0x9d,0x52,0xf5,0x52, -0x12,0xbe,0x88,0xbd,0x3c,0x8, 0x8, 0xe5,0x2c,0xa, 0x2b,0xa, 0x3d,0x80,0x4, 0xa, -0x2c,0xa, 0x3e,0x12,0xce,0x2, 0xf5,0x53,0x12,0xcd,0x99,0x9, 0xac,0x3, 0x32,0x7a, -0xa1,0x54,0x9, 0xbc,0x3, 0x31,0xf5,0x55,0xbe,0xa0,0x0, 0x28,0x2, 0xa1,0x8c,0x12, -0xcd,0x5b,0xbd,0x3d,0x58,0x2, 0xa1,0x8c,0x12,0xcd,0x5b,0xbd,0x3f,0x48,0x2, 0xa1, -0x8c,0xe5,0x4f,0x70,0x2, 0xa1,0x8c,0xe5,0x4f,0xbe,0xb0,0x4, 0x28,0xc, 0xe5,0x2b, -0xb4,0x1, 0x7, 0x12,0x4f,0xd1,0x28,0x2, 0xa1,0x69,0xe5,0x55,0xbe,0xb0,0x0, 0x28, -0xc, 0x12,0xce,0x13,0x7d,0x43,0x12,0x2e,0xec,0x58,0x2, 0xa1,0x69,0xe5,0x55,0xb4, -0x2, 0x9, 0xe5,0x53,0xbe,0xb1,0x4f,0x50,0x2, 0xa1,0x69,0xe5,0x38,0xbc,0xbd,0x78, -0x4c,0x12,0xcd,0x99,0x9, 0xbc,0x3, 0x3b,0xf5,0x56,0x9, 0xbc,0x3, 0x3a,0xf5,0x57, -0xa, 0x5d,0xb, 0x54,0x12,0x2e,0xe4,0x18,0x7, 0xe5,0x55,0xbe,0xb0,0x0, 0x38,0x79, -0x12,0xce,0x57,0x1b,0x34,0x12,0x2e,0xe6,0x18,0x9, 0xe5,0x57,0xbe,0xb0,0x0, 0x28, -0x2, 0x80,0x66,0xe5,0x56,0xbe,0xb0,0x2, 0x68,0x5, 0xe5,0x57,0xb4,0x2, 0x5d,0xe5, -0x53,0xbe,0xb1,0x4f,0x50,0x56,0xe5,0x2b,0xb4,0x1, 0x51,0x80,0x4c,0xe5,0x39,0xbc, -0xbd,0x78,0x49,0x12,0xcd,0x99,0x9, 0xbc,0x3, 0x29,0xf5,0x55,0x9, 0xbc,0x3, 0x28, -0xf5,0x57,0x12,0x2e,0xe0,0x18,0x7, 0xe5,0x55,0xbe,0xb0,0x0, 0x38,0x2b,0x12,0xce, -0x50,0x1b,0x34,0x12,0x2e,0xe6,0x18,0x9, 0xe5,0x57,0xbe,0xb0,0x0, 0x28,0x2, 0x80, -0x18,0xe5,0x56,0xbe,0xb0,0x2, 0x68,0x5, 0xe5,0x57,0xb4,0x2, 0xf, 0xe5,0x53,0xbe, -0xb1,0x4f,0x50,0x8, 0xe5,0x2b,0xb4,0x1, 0x3, 0x75,0x50,0x1, 0xe5,0x50,0xb4,0x1, -0x1b,0x12,0xcd,0x5b,0xbd,0x3e,0x8, 0x5, 0x7e,0x70,0x2, 0x80,0x3, 0x7e,0x70,0x1, -0x7e,0x51,0x51,0x74,0x9, 0xac,0x5b,0xe5,0x52,0x12,0xcd,0xe7,0xb, 0xd0,0xe5,0x39, -0xbc,0xbd,0x40,0x2, 0x81,0x38,0xb, 0xe0,0xe5,0x2f,0xbc,0xbe,0x40,0x2, 0x81,0x4, -0xbe,0xc0,0x0, 0x38,0x2, 0xe1,0x53,0xa, 0xcc,0x1b,0xc4,0x7d,0x3c,0x7c,0xe7,0xe1, -0x4b,0xa, 0x2e,0xa, 0x3c,0x9d,0x32,0x7a,0x71,0x3a,0xbe,0x71,0x2c,0x50,0x7, 0xe5, -0x3a,0x12,0xcf,0x4b,0x80,0x1, 0xe4,0xf5,0x3b,0xe5,0x3a,0x12,0xce,0x6b,0x12,0xcd, -0xcd,0x58,0x7, 0xe5,0x3a,0x12,0xce,0x5e,0x80,0x4, 0xa, 0x5a,0x1b,0x54,0xf5,0x3c, -0x7e,0xd1,0x3b,0xe1,0x3b,0x12,0x71,0xbc,0xf5,0x58,0x75,0x59,0x0, 0x12,0xcd,0xf9, -0x7d,0x5c,0x9d,0x54,0xf5,0x5a,0x12,0xcd,0xf0,0x9d,0x52,0xf5,0x5b,0x12,0xbe,0x88, -0xbd,0x3c,0x8, 0x8, 0xe5,0x2c,0xa, 0x2b,0xa, 0x3d,0x80,0x4, 0xa, 0x2c,0xa, 0x3e, -0x12,0xce,0x2, 0xf5,0x5c,0x12,0xcd,0x8b,0x9, 0xac,0x3, 0x32,0x7a,0xa1,0x5d,0x9, -0xbc,0x3, 0x33,0xf5,0x5e,0xbe,0xa0,0x0, 0x28,0x2, 0xe1,0x39,0x12,0xcd,0x5b,0xbd, -0x3d,0x58,0x2, 0xe1,0x39,0x12,0xcd,0x5b,0xbd,0x3f,0x48,0x2, 0xe1,0x39,0xe5,0x58, -0x70,0x2, 0xe1,0x39,0xe5,0x58,0xbe,0xb0,0x4, 0x28,0xc, 0xe5,0x2b,0xb4,0x1, 0x7, -0x12,0x4f,0xd1,0x28,0x2, 0xe1,0x16,0xe5,0x5e,0xbe,0xb0,0x0, 0x28,0xc, 0x12,0xce, -0xa, 0x7d,0x43,0x12,0x2e,0xec,0x58,0x2, 0xe1,0x16,0xe5,0x5e,0xb4,0x2, 0x9, 0xe5, -0x5c,0xbe,0xb1,0x58,0x50,0x2, 0xe1,0x16,0xe5,0x3b,0xbc,0xbd,0x78,0x4c,0x12,0xcd, -0x8b,0x9, 0xbc,0x3, 0x3b,0xf5,0x5f,0x9, 0xbc,0x3, 0x3c,0xf5,0x60,0xa, 0x5d,0xb, -0x54,0x12,0x2e,0xe4,0x18,0x7, 0xe5,0x5e,0xbe,0xb0,0x0, 0x38,0x79,0x12,0xce,0x57, -0xb, 0x34,0x12,0x2e,0xe6,0x18,0x9, 0xe5,0x60,0xbe,0xb0,0x0, 0x28,0x2, 0x80,0x66, -0xe5,0x5f,0xbe,0xb0,0x2, 0x68,0x5, 0xe5,0x60,0xb4,0x2, 0x5d,0xe5,0x5c,0xbe,0xb1, -0x58,0x50,0x56,0xe5,0x2b,0xb4,0x1, 0x51,0x80,0x4c,0xe5,0x3c,0xbc,0xbd,0x78,0x49, -0x12,0xcd,0x8b,0x9, 0xbc,0x3, 0x29,0xf5,0x5e,0x9, 0xbc,0x3, 0x2a,0xf5,0x60,0x12, -0x2e,0xe0,0x18,0x7, 0xe5,0x5e,0xbe,0xb0,0x0, 0x38,0x2b,0x12,0xce,0x50,0xb, 0x34, -0x12,0x2e,0xe6,0x18,0x9, 0xe5,0x60,0xbe,0xb0,0x0, 0x28,0x2, 0x80,0x18,0xe5,0x5f, -0xbe,0xb0,0x2, 0x68,0x5, 0xe5,0x60,0xb4,0x2, 0xf, 0xe5,0x5c,0xbe,0xb1,0x58,0x50, -0x8, 0xe5,0x2b,0xb4,0x1, 0x3, 0x75,0x59,0x1, 0xe5,0x59,0xb4,0x1, 0x1b,0x12,0xcd, -0x5b,0xbd,0x3e,0x8, 0x5, 0x7e,0x70,0x2, 0x80,0x3, 0x7e,0x70,0x1, 0x7e,0x51,0x5a, -0x74,0x9, 0xac,0x5b,0xe5,0x5b,0x12,0xcd,0xe7,0xb, 0xd0,0xe5,0x3c,0xbc,0xbd,0x40, -0x2, 0xa1,0xe5,0xe5,0x30,0xbc,0xbe,0x68,0xa, 0x1b,0xe0,0xe5,0x30,0xbc,0xbe,0x38, -0x2, 0xa1,0xb1,0x7e,0x51,0x2c,0x7e,0x70,0x7, 0xac,0x7f,0x19,0x53,0x2f,0x2, 0xe5, -0x2c,0x19,0xb3,0x2f,0x0, 0x19,0xc3,0x2f,0x3, 0x19,0xc3,0x2f,0x1, 0x7e,0xd1,0x2e, -0x80,0x7e,0x7e,0xe1,0x30,0x80,0x71,0xe5,0x2c,0xa, 0x3b,0xa, 0x2d,0x9d,0x23,0x7e, -0x34,0x0, 0x9, 0xad,0x32,0xa, 0x2c,0xa, 0x4e,0x9d,0x42,0x2d,0x43,0x9, 0xb4,0x3, -0x5a,0x70,0x16,0x6d,0xee,0x7e,0x73,0x1c,0xe0,0xac,0x7d,0x3e,0x34,0x74,0x2, 0xac, -0xbe,0x12,0x77,0xc2,0x1b,0x1a,0xe0,0x80,0x3d,0x9, 0xb4,0x3, 0x5a,0xb4,0x2, 0x2, -0x5, 0x2a,0x74,0x7, 0xac,0xbf,0x9, 0x75,0x2f,0x2, 0xbc,0x7d,0x28,0x4, 0x19,0xd5, -0x2f,0x2, 0x9, 0x75,0x2f,0x0, 0xbc,0x7d,0x50,0x4, 0x19,0xd5,0x2f,0x0, 0x9, 0x75, -0x2f,0x3, 0xbc,0x7e,0x28,0x4, 0x19,0xe5,0x2f,0x3, 0x9, 0x75,0x2f,0x1, 0xbc,0x7e, -0x50,0x4, 0x19,0xe5,0x2f,0x1, 0xb, 0xe0,0xe5,0x2f,0xbc,0xbe,0x50,0x89,0xb, 0xd0, -0xe5,0x2d,0xbc,0xbd,0x40,0x2, 0xe1,0x72,0x7e,0x71,0x2a,0x74,0x9, 0xac,0xbf,0x19, -0x75,0x19,0xad,0x7d,0x3f,0xe, 0x34,0xe, 0x34,0xe, 0x34,0xe, 0x34,0x74,0x9, 0xac, -0xbf,0x19,0x75,0x19,0xac,0xda,0x3b,0x22,0xca,0x3b,0x31,0x8f,0x7a,0xd1,0x2a,0x80, -0x32,0x7a,0xf1,0x2b,0x80,0x26,0xe5,0x2a,0x7e,0x71,0x2b,0x12,0x2b,0x76,0x7d,0x43, -0x31,0x9a,0x3e,0x34,0x7e,0x51,0x2b,0x74,0x2, 0xac,0xb5,0x2d,0x53,0x7f,0x17,0x2d, -0x35,0x74,0x2, 0xac,0xbf,0x9d,0x35,0x1b,0x1a,0x40,0x5, 0x2b,0xbe,0xe1,0x2b,0x50, -0xd5,0x5, 0x2a,0xbe,0xc1,0x2a,0x50,0xc9,0xda,0x3b,0x22,0xca,0x3b,0x6c,0xff,0x7e, -0xb3,0x1c,0xe1,0xf5,0x26,0x7e,0xe3,0x1c,0xe2,0x6c,0xdd,0x7e,0xb3,0x1c,0xdb,0x60, -0x3, 0x7e,0xd0,0x1, 0x7e,0xb3,0x16,0xbf,0xbe,0xb0,0x1, 0x68,0xf, 0x60,0x2, 0x21, -0x37,0x7e,0xb3,0x1a,0xb5,0xb4,0x1, 0x2, 0x80,0x2, 0x21,0x37,0x6c,0xcc,0x21,0x29, -0x7e,0x70,0x2, 0xac,0x7c,0x9, 0xa3,0x18,0x95,0x7a,0xa1,0x24,0x9, 0xb3,0x18,0x96, -0xf5,0x25,0xbe,0xa0,0x4, 0x28,0x8, 0xe5,0x24,0xa, 0x3b,0x1b,0x36,0x80,0x2, 0x6c, -0x77,0x7a,0x73,0x2, 0x8f,0xe5,0x26,0xa, 0x2b,0x1b,0x26,0xe5,0x24,0xa, 0x3b,0xbd, -0x32,0x58,0x8, 0xe5,0x24,0xa, 0x5b,0xb, 0x56,0x80,0x6, 0xe5,0x26,0xa, 0x5b,0x1b, -0x54,0xf5,0x27,0xe5,0x25,0xbe,0xb0,0x4, 0x28,0x8, 0xe5,0x25,0xa, 0x5b,0x1b,0x56, -0x80,0x1, 0xe4,0xf5,0x28,0xa, 0x2e,0x1b,0x26,0xe5,0x25,0xa, 0x3b,0xbd,0x32,0x58, -0x8, 0xe5,0x25,0xa, 0x2b,0xb, 0x26,0x80,0x4, 0xa, 0x2e,0x1b,0x24,0x7a,0x51,0x29, -0x31,0x3a,0x7e,0x8, 0x2, 0x90,0x11,0x18,0x7c,0xbc,0x12,0x77,0xcb,0x74,0x4, 0x7e, -0x70,0x4, 0x7c,0x6c,0x7c,0x5f,0x7c,0x4d,0x31,0xad,0x31,0x3a,0x7e,0x51,0x29,0x7e, -0x8, 0x2, 0x90,0x31,0x45,0xb, 0xf0,0xb, 0xc0,0x7e,0x73,0x1a,0xb5,0xbc,0x7c,0x28, -0x2, 0x1, 0x90,0x7a,0xf3,0x1a,0xb5,0xda,0x3b,0x22,0x7e,0xb3,0x2, 0x8f,0x7e,0x71, -0x27,0x7e,0x61,0x28,0x22,0xca,0x3b,0x31,0x8f,0x7a,0xd1,0x2a,0x80,0x39,0x7a,0xf1, -0x2b,0x80,0x2d,0x31,0x9a,0x7d,0x23,0x3e,0x24,0x7e,0x71,0x2b,0x74,0x2, 0xac,0x7b, -0x2d,0x23,0x7f,0x7, 0x2d,0x12,0xac,0xbf,0x9d,0x15,0xb, 0xa, 0x40,0x7e,0xb3,0x1c, -0xe0,0x7e,0x51,0x2a,0xac,0xb5,0x3e,0x54,0x12,0x77,0xc2,0x1b,0x1a,0x40,0x5, 0x2b, -0xbe,0xe1,0x2b,0x50,0xce,0x5, 0x2a,0xbe,0xc1,0x2a,0x50,0xc2,0xda,0x3b,0x22,0x7f, -0x70,0x7c,0xe5,0x7c,0xf6,0x7c,0xc7,0x7c,0xdb,0x22,0xa, 0x2f,0xa, 0x3e,0x9d,0x32, -0xb, 0x34,0xa, 0x1d,0xe5,0x2a,0xa, 0x2b,0x9d,0x21,0xad,0x32,0x22,0xca,0x3b,0x7a, -0x41,0x2a,0x7c,0xc5,0x7c,0xf6,0x7c,0xe7,0x7c,0xdb,0x7e,0x70,0x9, 0xac,0x7c,0x2e, -0x34,0x19,0xa7,0x6d,0x22,0x7a,0x1d,0x4e,0x12,0xce,0xb2,0xf5,0x3d,0x9, 0xb3,0x18, -0x96,0xf5,0x3e,0x7e,0x73,0x1c,0xe0,0x7c,0x6e,0x7e,0x8, 0x0, 0x42,0x91,0x8, 0xf5, -0x3f,0xe5,0x3d,0x7e,0x73,0x1c,0xdf,0x7c,0x6d,0x7e,0x8, 0x0, 0x41,0x91,0x8, 0x7c, -0x7b,0x7a,0x71,0x40,0xe5,0x41,0x2e,0x71,0x41,0x1b,0x70,0xb1,0x4e,0xe5,0x41,0x7e, -0x71,0x42,0x12,0xa6,0xad,0x7a,0x35,0x4a,0x7e,0x34,0x15,0xcc,0x7a,0x35,0x4c,0x85, -0x41,0x44,0x85,0x42,0x45,0x85,0x40,0x46,0x85,0x3f,0x47,0x7e,0xb3,0x1c,0xcb,0xf5, -0x48,0x75,0x49,0x0, 0xe5,0x2a,0xb4,0x1, 0x8, 0xe5,0x48,0x1e,0xb0,0x1e,0xb0,0xf5, -0x48,0x7e,0x8, 0x0, 0x44,0x12,0x17,0x5b,0x7e,0x37,0x15,0xcc,0x7d,0x3, 0x6d,0x11, -0x7e,0x37,0x15,0xce,0x6d,0x22,0x2f,0x10,0x7a,0x1d,0x2b,0x7e,0x17,0x15,0xd0,0x7d, -0x41,0x6d,0x55,0x7e,0x17,0x15,0xd2,0x6d,0x0, 0x2f,0x2, 0x7a,0xd, 0x2f,0x7e,0x17, -0x15,0xd4,0x6d,0x0, 0x7d,0x41,0x7e,0x17,0x15,0xd6,0x2f,0x2, 0x7a,0xd, 0x37,0x7a, -0x1d,0x33,0xa, 0x4d,0xe5,0x3d,0x9d,0x54,0xf5,0x3b,0x61,0x43,0xa, 0x4e,0xe5,0x3e, -0xa, 0x5b,0x9d,0x54,0xf5,0x3c,0x61,0x32,0xe5,0x3b,0xbe,0xb0,0x0, 0x58,0x2, 0x61, -0x30,0x7e,0x73,0x1c,0xdf,0xbe,0x71,0x3b,0x18,0x2, 0x61,0x30,0xe5,0x3c,0xbe,0xb0, -0x0, 0x58,0x2, 0x61,0x30,0x7e,0x73,0x1c,0xe0,0xbe,0x71,0x3c,0x18,0x2, 0x61,0x30, -0xe5,0x3b,0x7e,0x71,0x3c,0x12,0x2b,0x76,0x7e,0x53,0x1c,0xcb,0xa, 0x25,0x7d,0xf3, -0x9d,0xf2,0xbe,0xf4,0x0, 0x0, 0x8, 0x68,0xe5,0x3d,0xa, 0x2b,0xe5,0x3b,0x71,0xe6, -0x18,0xa, 0xe5,0x3e,0xa, 0x2b,0xe5,0x3c,0x71,0xe6,0x8, 0x54,0xe5,0x3b,0x7e,0x71, -0x3c,0x7c,0x6f,0x12,0x73,0x33,0xf5,0x43,0xb4,0x2, 0x6, 0x7d,0xef,0xe, 0xe4,0x9d, -0xfe,0xe5,0x43,0xbe,0xb0,0x2, 0x68,0x5, 0xe5,0x43,0xb4,0x1, 0x33,0x71,0xd5,0xe5, -0x3b,0x71,0xdc,0x7e,0x1d,0x2f,0x9f,0x10,0x7a,0x1d,0x2f,0x71,0xd5,0xe5,0x3c,0x71, -0xdc,0x7e,0x1d,0x37,0x9f,0x10,0x7a,0x1d,0x37,0x12,0x2f,0xb6,0x7e,0x1d,0x2b,0x9f, -0x10,0x7a,0x1d,0x2b,0x1a,0x2, 0x1a,0x0, 0x7e,0x1d,0x33,0x9f,0x10,0x7a,0x1d,0x33, -0x5, 0x3c,0xa, 0x2e,0xe5,0x3e,0xa, 0x3b,0x2d,0x32,0xbe,0x71,0x3c,0x48,0x2, 0x41, -0x88,0x5, 0x3b,0xa, 0x2d,0xe5,0x3d,0xa, 0x3b,0x2d,0x32,0xbe,0x71,0x3b,0x48,0x2, -0x41,0x7c,0x7e,0x1d,0x2b,0xbe,0x18,0x0, 0x0, 0x78,0x5, 0xb, 0x1c,0x7a,0x1d,0x2b, -0x7e,0x1d,0x33,0xbe,0x18,0x0, 0x0, 0x78,0x5, 0xb, 0x1c,0x7a,0x1d,0x33,0x7e,0x1d, -0x2f,0x7e,0xd, 0x2b,0x71,0xf2,0x7d,0x13,0x7e,0x1d,0x4e,0x1b,0x1a,0x10,0x7e,0x1d, -0x37,0x7e,0xd, 0x33,0x71,0xf2,0x7e,0xd, 0x4e,0x79,0x30,0x0, 0x2, 0x7e,0xb3,0x1c, -0xd7,0x7e,0x1d,0x33,0x60,0xc, 0x1e,0x34,0x1e,0x24,0x50,0x3, 0x4e,0x60,0x80,0x14, -0x78,0xf4,0x7a,0x1d,0x33,0xbe,0x18,0x0, 0x7f,0x28,0x7, 0x7e,0x18,0x0, 0x7f,0x7a, -0x1d,0x33,0x7e,0x1d,0x33,0x7e,0xd, 0x4e,0x39,0x70,0x0, 0x5, 0x7e,0x71,0x3d,0x74, -0x9, 0xac,0xbc,0x19,0x75,0x19,0xae,0x7e,0x71,0x3e,0x74,0x9, 0xac,0xbc,0x19,0x75, -0x19,0xaf,0xda,0x3b,0x22,0x7d,0x3f,0x1a,0x26,0x1a,0x24,0x22,0x1a,0x1b,0x1a,0x2, -0x12,0x1d,0x7c,0x7f,0x1, 0x22,0x1a,0x3b,0x9d,0x32,0x12,0x20,0x54,0xbe,0x34,0x0, -0x1, 0x22,0x7f,0x70,0x7f,0x1, 0x7c,0x41,0x7c,0x52,0x7c,0x63,0x6c,0x77,0x7f,0x7, -0x12,0x1d,0x98,0x2e,0x18,0x0, 0x80,0x22,0xca,0x79,0x7f,0x70,0x7c,0x36,0x7c,0x17, -0x7c,0x2b,0xa, 0x23,0x7d,0x32,0x3e,0x34,0xb, 0x34,0x7c,0x7, 0xbc,0x32,0x38,0x14, -0xa, 0x51,0x1b,0x54,0xa, 0x33,0x9d,0x53,0xa, 0x32,0xbd,0x35,0x18,0x6, 0x7c,0xf0, -0xa, 0x32,0x80,0x1c,0xbc,0x32,0x28,0xe, 0xa, 0x32,0xa, 0x73,0x2d,0x73,0xb, 0x74, -0xe4,0x7a,0x7b,0xb0,0x80,0xf, 0xa, 0x33,0xa, 0x71,0x2d,0x73,0xa, 0x32,0x9d,0x73, -0x9d,0x32,0x7a,0x7b,0x70,0x7c,0xbf,0xda,0x79,0x22,0xca,0xf8,0x7c,0x6b,0x6c,0x22, -0x7e,0x30,0xff,0x74,0x2, 0xac,0xb6,0x9, 0x15,0x18,0x95,0x9, 0x5, 0x18,0x96,0x7e, -0xb3,0x1c,0x48,0x70,0x4, 0x74,0xff,0xa1,0x2b,0x7e,0x73,0x1a,0xb5,0xbc,0x76,0x38, -0x4, 0x74,0xff,0xa1,0x2b,0x6c,0x99,0x6c,0x88,0x7e,0x70,0x7, 0xac,0x79,0x9, 0xf3, -0x2e,0xfd,0xbe,0xf0,0xff,0x78,0x2, 0xa1,0x20,0x9, 0x53,0x2f,0x0, 0xbc,0x51,0x40, -0x72,0x9, 0x53,0x2f,0x2, 0xbc,0x51,0x38,0x6a,0x9, 0x53,0x2f,0x1, 0xbc,0x50,0x40, -0x62,0x9, 0x53,0x2f,0x3, 0xbc,0x50,0x38,0x5a,0x9, 0xa3,0x2e,0xfe,0xbc,0xa1,0x78, -0xd, 0x9, 0xb3,0x2e,0xff,0xbc,0xb0,0x78,0x5, 0x7e,0x80,0x4, 0x80,0x30,0xa, 0x2a, -0xa, 0x31,0x71,0xe8,0x18,0xd, 0xb1,0x2e,0xbe,0x34,0x0, 0x1, 0x18,0x5, 0x7e,0x80, -0x3, 0x80,0x1b,0xb1,0x3f,0x12,0x20,0x54,0xbe,0x34,0x0, 0x2, 0x18,0xd, 0xb1,0x2e, -0xbe,0x34,0x0, 0x2, 0x18,0x5, 0x7e,0x80,0x2, 0x80,0x3, 0x7e,0x80,0x1, 0xb1,0x2e, -0x7d,0xf3,0xb1,0x3f,0x12,0x20,0x54,0x7d,0x53,0x2d,0x5f,0xbe,0x54,0x0, 0x8, 0x8, -0x2, 0x6c,0x88,0xbc,0x28,0x50,0x4, 0x7c,0x28,0x7c,0x39,0xbe,0x20,0x4, 0x68,0x9, -0xb, 0x90,0xbe,0x90,0xa, 0x50,0x2, 0x81,0x87,0x7c,0xb3,0xda,0xf8,0x22,0x74,0x7, -0xac,0xb9,0x9, 0x75,0x2e,0xff,0xa, 0x27,0xa, 0x30,0x9d,0x32,0x2, 0x20,0x54,0x74, -0x7, 0xac,0xb9,0x9, 0x75,0x2e,0xfe,0xa, 0x27,0xa, 0x31,0x9d,0x32,0x22,0xca,0xd8, -0xca,0x79,0x7c,0xf7,0x7c,0xab,0x7e,0xe3,0x1c,0xe2,0x7c,0xda,0x80,0x26,0xb1,0x8d, -0x60,0x5, 0x2f,0x11,0x14,0x78,0xfb,0x5e,0x37,0x32,0x62,0x5e,0x27,0x32,0x60,0x4d, -0x23,0x78,0xf, 0xd2,0x3, 0xb1,0x94,0xb1,0x8d,0x60,0x5, 0x2f,0x11,0x14,0x78,0xfb, -0xf1,0xdb,0xb, 0xd0,0xbc,0xfd,0x50,0xd6,0xda,0x79,0xda,0xd8,0x22,0x7e,0x18,0x0, -0x1, 0x7c,0xbd,0x22,0x7c,0xbd,0x7c,0x7e,0xca,0xf8,0x7c,0xf7,0x7c,0x9b,0xc2,0x4, -0x7e,0x34,0x23,0x71,0x7e,0x24,0x0, 0xff,0x7e,0x14,0x3, 0x32,0x74,0xc, 0x12,0x1e, -0x3e,0x7e,0x73,0x38,0x51,0xac,0x79,0x3e,0x34,0x7e,0x5f,0x13,0x68,0x2d,0xb3,0x74, -0x2, 0xac,0xb9,0x49,0x95,0x32,0x64,0x49,0x85,0x32,0xaa,0x20,0x3, 0xa, 0xbe,0x94, -0x0, 0x14,0x58,0x4, 0x6d,0x33,0xc1,0xbc,0xbe,0x94,0x4, 0xb0,0x8, 0x2, 0xd2,0x4, -0x6c,0x77,0x74,0x4, 0xac,0xb7,0x49,0x45,0x3, 0x32,0xbd,0x49,0x58,0x6, 0x49,0x95, -0x3, 0x34,0x80,0x7, 0xb, 0x70,0xbe,0x70,0x3, 0x40,0xe7,0xa5,0xbf,0x3, 0x4, 0x6d, -0x33,0xc1,0xbc,0xbd,0x89,0x8, 0x5, 0x30,0x4, 0x2, 0x7d,0x98,0x7e,0xb3,0x1c,0xda, -0xb4,0x1, 0xb, 0x7e,0x24,0x0, 0x2, 0x7d,0x39,0x12,0x1d,0x4a,0x7d,0x93,0x7a,0xf1, -0x52,0x6d,0x33,0x7a,0x35,0x53,0x7a,0x35,0x55,0x7a,0x35,0x57,0x7e,0x24,0x0, 0x1, -0x7a,0x25,0x59,0x7a,0x35,0x5b,0xf1,0x9e,0xd1,0xbf,0x7a,0xf1,0x52,0x7e,0x37,0x32, -0xf0,0x7a,0x35,0x53,0x6d,0x33,0x9e,0x37,0x32,0xf0,0x7a,0x35,0x55,0x6d,0x33,0x7a, -0x35,0x57,0x7a,0x35,0x59,0x7a,0x35,0x5b,0x7e,0x34,0x0, 0x2, 0xf1,0x9e,0xd1,0xbf, -0x7e,0x37,0x32,0xf0,0xbe,0x34,0x7f,0xff,0x78,0x1f,0xb, 0x5a,0x30,0xbe,0x34,0x0, -0x0, 0x58,0xa, 0x6d,0x22,0x9d,0x28,0x7a,0x27,0x32,0xf0,0x80,0x28,0xbe,0x34,0x0, -0x0, 0x8, 0x22,0x7a,0x87,0x32,0xf0,0x80,0x1c,0x7e,0x87,0x32,0xf0,0xbd,0x89,0x8, -0x6, 0x7a,0x97,0x32,0xf0,0x80,0xe, 0x6d,0x33,0x9d,0x39,0xbe,0x37,0x32,0xf0,0x8, -0x4, 0x7a,0x37,0x32,0xf0,0x7a,0x5d,0x52,0x7a,0xf1,0x57,0x6d,0x33,0x7a,0x35,0x58, -0x7a,0x35,0x5a,0xf1,0xa1,0x12,0xa8,0x71,0x7e,0x37,0x32,0xf0,0xda,0xf8,0x22,0x7f, -0x71,0x7f,0x60,0x7e,0x45,0x5d,0xa9,0xd6,0xcb,0xf1,0xe8,0x79,0x30,0x0, 0x38,0x7d, -0x3d,0x12,0xa8,0xbc,0x79,0x30,0x0, 0x8, 0x7e,0x35,0x53,0x7e,0xf, 0x36,0x51,0x79, -0x30,0x0, 0xe, 0x7e,0x35,0x55,0x7e,0xf, 0x36,0x51,0x79,0x30,0x0, 0x10,0x7c,0x6b, -0xe5,0x52,0x7c,0xa6,0x7e,0x1f,0x36,0x51,0x79,0x51,0x0, 0xc, 0x5e,0x44,0x0, 0x3, -0x7d,0x14,0x7c,0x23,0x6c,0x33,0x3e,0x14,0x3e,0x14,0x3e,0x14,0x7e,0x1f,0x36,0x51, -0x2e,0x34,0x0, 0x38,0xf1,0x95,0x7e,0x15,0x5b,0x7c,0x23,0x6c,0x33,0xf1,0x91,0x7e, -0x55,0x59,0x7d,0x15,0x7c,0x23,0x6c,0x33,0xf1,0x8f,0x7e,0x55,0x57,0x7d,0x15,0x7c, -0x23,0x6c,0x33,0x3e,0x14,0xf1,0x8f,0x7e,0x1f,0x36,0x51,0x7e,0x1f,0x36,0x51,0xb, -0x1a,0x50,0x4e,0xa0,0x80,0x1b,0x1a,0x50,0xe1,0x4a,0xa9,0xd7,0xcb,0x12,0xa8,0x69, -0x4e,0x70,0x1, 0x80,0x12,0x12,0xa8,0x69,0x7d,0x23,0x5e,0x24,0x0, 0x8, 0xbe,0x24, -0x0, 0x8, 0x78,0x6, 0x4e,0x70,0x4, 0x1b,0xa, 0x30,0x7e,0xf, 0x36,0x51,0x69,0x30, -0x0, 0x38,0x5e,0x34,0x80,0x0, 0xbe,0x34,0x80,0x0, 0x78,0xd9,0xb, 0xa, 0x30,0x4e, -0x60,0x40,0x1b,0xa, 0x30,0xf1,0xe8,0x79,0x30,0x0, 0x38,0xa9,0xc6,0xcb,0x22,0x3e, -0x14,0x7e,0x1f,0x36,0x51,0xb, 0x1a,0x50,0x4d,0x51,0x1b,0x1a,0x50,0x22,0x7a,0x35, -0x5d,0x7f,0x5, 0x7e,0x18,0x32,0xf0,0x74,0x1, 0x22,0xca,0xd8,0xca,0x79,0x7e,0xf3, -0x1c,0xe1,0x7e,0xe3,0x1c,0xe2,0x12,0xa7,0x9c,0x6c,0xdd,0x80,0x15,0xc2,0x3, 0xb1, -0x94,0x4d,0x33,0x68,0xb, 0xb1,0x8d,0x60,0x5, 0x2f,0x11,0x14,0x78,0xfb,0xf1,0xdb, -0xb, 0xd0,0xbc,0xfd,0x38,0xe7,0xda,0x79,0xda,0xd8,0x22,0x4e,0x37,0x32,0x62,0x4e, -0x27,0x32,0x60,0x7a,0x1f,0x32,0x60,0x22,0x6d,0x11,0x7e,0x1f,0x36,0x51,0x1b,0x1a, -0x10,0x6d,0x33,0x7e,0xf, 0x36,0x51,0x22,0x1, 0x5b,0x7e,0x24,0x34,0xe1,0x30,0xe, -0x1d,0xc2,0xe, 0x9, 0x72,0x0, 0x5, 0xa, 0x37,0x12,0x45,0x82,0x7a,0x37,0x1c,0xd4, -0x9, 0x72,0x0, 0x40,0xbe,0x73,0x1c,0xda,0x68,0x4, 0x7a,0x73,0x1c,0xda,0x22,0xca, -0x69,0xca,0xf8,0x7c,0xfb,0x7d,0xf2,0x7d,0xe3,0x7d,0xbe,0x1a,0x36,0x7d,0x3f,0x7d, -0x9f,0x1a,0x36,0x7e,0xd0,0x12,0xac,0xdf,0x49,0xd6,0x17,0xf, 0x2d,0xde,0x49,0xc6, -0x17,0x11,0x2d,0xcf,0xbe,0xd4,0x0, 0x0, 0x58,0x8, 0x49,0x36,0x17,0xf, 0x31,0x1e, -0x80,0x12,0xbe,0xd4,0x4, 0x38,0x48,0x1d,0x49,0x16,0x17,0xf, 0x6d,0x0, 0x7e,0x18, -0x4, 0x38,0x9f,0x10,0x12,0x2f,0xb6,0x12,0x1d,0x7c,0x7d,0x1e,0x1a,0x2, 0x1a,0x0, -0x12,0x1d,0xe9,0x7f,0x41,0xbe,0xc4,0x0, 0x0, 0x58,0x8, 0x49,0x36,0x17,0x11,0x31, -0x1e,0x80,0x12,0xbe,0xc4,0x9, 0x24,0x48,0x1d,0x49,0x16,0x17,0x11,0x6d,0x0, 0x7e, -0x18,0x9, 0x24,0x9f,0x10,0x7d,0x1e,0x1a,0x2, 0x1a,0x0, 0x12,0x1d,0x7c,0x12,0x2f, -0xb6,0x12,0x1d,0xe9,0x7f,0x51,0x49,0xd6,0x17,0x11,0x7d,0xc9,0x2d,0xcd,0x49,0x36, -0x17,0xf, 0x7d,0xdb,0x2d,0xd3,0xbe,0xc4,0x0, 0x0, 0x58,0x4, 0x6d,0xcc,0x80,0xa, -0xbe,0xc4,0x9, 0x24,0x48,0x4, 0x7e,0xc4,0x9, 0x23,0xbe,0xd4,0x0, 0x0, 0x58,0x4, -0x6d,0xdd,0x80,0xa, 0xbe,0xd4,0x4, 0x38,0x48,0x4, 0x7e,0xd4,0x4, 0x37,0x6c,0x77, -0x80,0x1a,0x74,0x9, 0xac,0xb7,0x9, 0x65,0x1b,0x3d,0xbc,0x6f,0x78,0xc, 0x59,0xd5, -0x1b,0x39,0x74,0x9, 0xac,0xb7,0x59,0xc5,0x1b,0x3b,0xb, 0x70,0x7e,0x63,0x1c,0xbf, -0xbc,0x67,0x38,0xde,0x74,0x2, 0x12,0x5f,0xd1,0x7e,0xb3,0x1c,0x47,0x4, 0x7a,0xb3, -0x1c,0x47,0x31,0x29,0xe4,0x7a,0xb3,0x1c,0x4c,0xda,0xf8,0xda,0x69,0x22,0x6e,0x34, -0xff,0xff,0x7e,0x24,0xff,0xff,0xb, 0x1c,0x22,0x74,0x1, 0x7a,0xb3,0x1c,0x50,0x22, -0xca,0xf8,0x7e,0xf3,0x1c,0x47,0x7c,0xbf,0x7e,0x73,0x2f,0x6b,0x12,0xa1,0x50,0x7c, -0xbf,0x12,0xa1,0xdf,0x7e,0xb3,0x2f,0x6b,0x70,0x15,0x7e,0x34,0x0, 0x5a,0xca,0x39, -0x7e,0x18,0x1a,0xdf,0x7e,0x8, 0x1b,0x93,0x12,0x1f,0xed,0x1b,0xfd,0x80,0xb, 0x7e, -0xb3,0x1c,0x4e,0x70,0x5, 0x7c,0xbf,0x12,0x96,0xa5,0x7c,0xbf,0x12,0xa3,0x28,0xbe, -0xf0,0x0, 0x28,0x2, 0x31,0x29,0x7a,0xf3,0x2f,0x6b,0xda,0xf8,0x22,0x7e,0xb3,0x35, -0x31,0x70,0x3, 0x12,0x9f,0x14,0x31,0x93,0x12,0xa3,0xb6,0x12,0x5f,0x18,0x12,0x9e, -0xdb,0x21,0x30,0xca,0x3b,0x6c,0xcc,0x6c,0xff,0x7e,0x8, 0x2e,0xfd,0x7e,0x34,0x0, -0x46,0x74,0xff,0x12,0x20,0x12,0x6c,0x77,0x80,0x6a,0x74,0x7, 0xac,0xb7,0x19,0x75, -0x2e,0xfd,0x74,0x2, 0xac,0xb7,0x9, 0x65,0x18,0x95,0x74,0x7, 0xac,0xb7,0x19,0x65, -0x2e,0xfe,0x74,0x2, 0xac,0xb7,0x9, 0x65,0x18,0x96,0x74,0x7, 0xac,0xb7,0x19,0x65, -0x2e,0xff,0x74,0x5, 0xac,0xb7,0x9, 0x65,0x18,0xd2,0x74,0x7, 0xac,0xb7,0x19,0x65, -0x2f,0x2, 0x74,0x5, 0xac,0xb7,0x9, 0x65,0x18,0xd3,0x74,0x7, 0xac,0xb7,0x19,0x65, -0x2f,0x0, 0x74,0x5, 0xac,0xb7,0x9, 0x65,0x18,0xd4,0x74,0x7, 0xac,0xb7,0x19,0x65, -0x2f,0x3, 0x74,0x5, 0xac,0xb7,0x9, 0x65,0x18,0xd5,0x74,0x7, 0xac,0xb7,0x19,0x65, -0x2f,0x1, 0xb, 0x70,0x7e,0x63,0x1a,0xb5,0xbc,0x67,0x38,0x8e,0x6c,0x77,0x7e,0x90, -0x9, 0xac,0x97,0x9, 0x64,0x1a,0xe3,0xbe,0x60,0xff,0x78,0x2, 0x61,0xbe,0xa, 0x26, -0x9, 0xb2,0x1b,0xed,0xbe,0xb0,0x1, 0x78,0x2, 0x61,0xbe,0x6c,0xdd,0x74,0x9, 0xac, -0xbd,0x9, 0x55,0x2e,0x93,0xbc,0x56,0x68,0x7, 0xb, 0xd0,0xbe,0xd0,0xa, 0x40,0xed, -0xbe,0xd0,0xa, 0x40,0x6, 0x6c,0xcc,0x6c,0xff,0x80,0x2b,0x74,0x5, 0xac,0xb7,0x9, -0xb5,0x18,0xd1,0xb4,0x1, 0x20,0x74,0x9, 0xac,0xbd,0x49,0x15,0x2e,0x8f,0x49,0x24, -0x1a,0xdf,0x9d,0x21,0xa, 0x24,0x7c,0xc5,0x49,0x55,0x2e,0x91,0x49,0x24,0x1a,0xe1, -0x9d,0x25,0x7d,0x72,0xa, 0x7e,0x4c,0xcc,0x78,0x2, 0x61,0x28,0x7e,0x50,0x7, 0xac, -0x57,0x2e,0x24,0x2f,0x0, 0xf1,0x52,0x7e,0x50,0x7, 0xac,0x57,0x2e,0x24,0x2f,0x2, -0xf1,0x52,0x74,0x7, 0xac,0xb7,0x9, 0x55,0x2f,0x0, 0x1a,0x15,0x7e,0x43,0x1c,0xe1, -0x71,0xf1,0x8, 0x8, 0x71,0xe4,0x19,0x45,0x2f,0x0, 0x80,0xb, 0xbe,0x50,0x0, 0x58, -0x6, 0x71,0xdd,0x19,0x55,0x2f,0x0, 0x74,0x7, 0xac,0xb7,0x9, 0x55,0x2f,0x2, 0x1a, -0x15,0x7e,0x43,0x1c,0xe1,0x71,0xf1,0x8, 0x8, 0x71,0xe4,0x19,0x45,0x2f,0x2, 0x80, -0xb, 0xbe,0x50,0x0, 0x58,0x6, 0x71,0xdd,0x19,0x55,0x2f,0x2, 0x7e,0x30,0x7, 0xac, -0x37,0x9, 0x51,0x2e,0xfe,0x1a,0x5, 0x1a,0xfc,0x2d,0xf0,0x7e,0x53,0x1c,0xe1,0xa, -0x55,0x1b,0x54,0xbd,0xf5,0x8, 0x6, 0xa, 0x25,0x1b,0x24,0x80,0x17,0x1a,0x2c,0xf1, -0x40,0x58,0x7, 0xe4,0x19,0xb1,0x2e,0xfe,0x80,0xe, 0x9, 0x51,0x2e,0xfe,0x1a,0x5, -0x1a,0x2c,0x2d,0x20,0x19,0x51,0x2e,0xfe,0x4c,0xff,0x78,0x2, 0x61,0xbe,0x7e,0x50, -0x7, 0xac,0x57,0x2e,0x24,0x2f,0x1, 0xf1,0x49,0x7e,0x50,0x7, 0xac,0x57,0x2e,0x24, -0x2f,0x3, 0xf1,0x49,0x74,0x7, 0xac,0xb7,0x9, 0x55,0x2f,0x1, 0x71,0xeb,0x8, 0x8, -0x71,0xe4,0x19,0x45,0x2f,0x1, 0x80,0xb, 0xbe,0x50,0x0, 0x58,0x6, 0x71,0xdd,0x19, -0x55,0x2f,0x1, 0x74,0x7, 0xac,0xb7,0x9, 0x55,0x2f,0x3, 0x71,0xeb,0x8, 0x8, 0x71, -0xe4,0x19,0x45,0x2f,0x3, 0x80,0xb, 0xbe,0x50,0x0, 0x58,0x6, 0x71,0xdd,0x19,0x55, -0x2f,0x3, 0x7e,0x30,0x7, 0xac,0x37,0x9, 0x51,0x2e,0xff,0x1a,0x5, 0x1a,0xff,0x2d, -0xf0,0x7e,0x53,0x1c,0xe2,0xa, 0x55,0x1b,0x54,0xbd,0xf5,0x8, 0x6, 0xa, 0x25,0x1b, -0x24,0x80,0x17,0x1a,0x2f,0xf1,0x40,0x58,0x7, 0xe4,0x19,0xb1,0x2e,0xff,0x80,0xe, -0x9, 0x51,0x2e,0xff,0x1a,0x5, 0x1a,0x2f,0x2d,0x20,0x19,0x51,0x2e,0xff,0xb, 0x70, -0xbe,0x70,0xa, 0x50,0x2, 0x41,0x1e,0x7e,0x34,0x0, 0x5a,0xca,0x39,0x7e,0x18,0x1a, -0xdf,0x7e,0x8, 0x2e,0x8f,0x12,0x1f,0xed,0x1b,0xfd,0xda,0x3b,0x22,0x6c,0x55,0x74, -0x7, 0xac,0xb7,0x22,0x7c,0x4b,0x74,0x7, 0xac,0xb7,0x22,0x1a,0x15,0x7e,0x43,0x1c, -0xe2,0xa, 0x54,0x1b,0x54,0xbd,0x15,0x22,0xca,0x3b,0x7c,0xf7,0x7c,0xeb,0x6c,0xdd, -0xa, 0x3f,0x9, 0xb3,0x31,0x27,0xbe,0xb0,0x2, 0x68,0x63,0x74,0x9, 0xac,0xbe,0x49, -0x35,0x1a,0xdf,0x49,0x25,0x1a,0xe1,0x74,0x9, 0xac,0xbf,0x49,0x15,0x31,0x3b,0x49, -0x5, 0x31,0x3d,0x12,0xa3,0x76,0xbe,0x34,0x0, 0xa0,0x28,0x14,0xf1,0x0, 0x7e,0x24, -0x1, 0x0, 0x12,0x5c,0x86,0x40,0x9, 0x74,0x16,0x7a,0xb3,0x30,0xc2,0xe4,0x80,0x13, -0xf1,0xe1,0x28,0x5, 0x14,0x7a,0xb3,0x30,0xc2,0x7e,0xb3,0x30,0xb5,0xbe,0xb0,0xc8, -0x50,0x5, 0x4, 0x7a,0xb3,0x30,0xb5,0xf1,0x6f,0xac,0x3f,0xf1,0x25,0xa, 0x3f,0x9, -0xb3,0x31,0x27,0x70,0x6, 0x74,0x14,0x7a,0xb3,0x31,0x96,0xe4,0xc1,0xf4,0xf1,0x6f, -0xac,0x3f,0xf1,0x25,0xa, 0x3f,0x9, 0xb3,0x30,0xb8,0xbe,0xb0,0xff,0x50,0x8, 0x2e, -0x34,0x30,0xb8,0x4, 0x7a,0x39,0xb0,0x7c,0xbe,0x7c,0x7f,0x6c,0x66,0x12,0xc0,0xbe, -0x7c,0xcb,0xbe,0xc0,0x0, 0x28,0x35,0xbe,0xc0,0x3, 0x50,0x30,0xf1,0x0, 0x7e,0xb3, -0x30,0xc2,0x60,0x6, 0x7e,0x24,0x0, 0x8, 0x80,0x2, 0x6d,0x22,0xf1,0x37,0x12,0x5c, -0x86,0x40,0x16,0xd1,0xf7,0x7e,0xb3,0x30,0xc2,0x60,0x6, 0x7e,0x24,0x0, 0x8, 0x80, -0x2, 0x6d,0x22,0xf1,0x37,0xf1,0xd, 0x50,0x3, 0x7e,0xc0,0x3, 0x4c,0xcc,0x68,0x17, -0xf1,0x2e,0xbe,0x44,0x2, 0x0, 0x50,0xf, 0x49,0x25,0x31,0x3b,0x12,0x97,0x38,0xbe, -0x34,0x1, 0x0, 0x8, 0x2, 0x6c,0xcc,0x4c,0xcc,0x68,0x26,0xf1,0x1e,0x1b,0x35,0x12, -0x45,0x80,0x12,0x45,0x84,0xf1,0x2e,0xbd,0x43,0x28,0x16,0x49,0x35,0x31,0x3b,0x74, -0x9, 0xac,0xbe,0x49,0x25,0x1a,0xdf,0x9d,0x32,0xbe,0x34,0x1, 0x0, 0x8, 0x2, 0x6c, -0xcc,0x4c,0xcc,0x68,0x1e,0xf1,0xe9,0xbe,0x44,0x2, 0x0, 0x50,0x16,0x49,0x25,0x31, -0x3d,0x74,0x9, 0xac,0xbe,0x49,0x35,0x1a,0xe1,0x9d,0x32,0xbe,0x34,0x1, 0x0, 0x8, -0x2, 0x6c,0xcc,0x12,0x45,0xc8,0xf5,0x25,0x30,0xe1,0x5, 0x7e,0xc0,0x3, 0x80,0xb, -0xe5,0x25,0x30,0xe2,0x6, 0x7e,0xc0,0x2, 0x7e,0xd0,0x1, 0x7e,0x70,0x9, 0xac,0x7f, -0x9, 0xb3,0x30,0xd4,0xf1,0x17,0xbe,0x34,0x0, 0x6e,0x58,0x7b,0x7e,0xb3,0x30,0xc2, -0x70,0x75,0x6d,0x44,0x7d,0xf4,0xf1,0x65,0xbe,0xa0,0x0, 0x28,0xd, 0x9, 0xb3,0x30, -0xd4,0xa, 0x3a,0x1b,0x34,0x12,0x2b,0x76,0x7d,0xf3,0xf1,0x65,0xa, 0xea,0x7e,0xb3, -0x38,0x51,0xa, 0x2b,0x1b,0x24,0xbd,0xe2,0x58,0xd, 0x9, 0xb3,0x30,0xd4,0xa, 0x3a, -0xb, 0x34,0x12,0x2b,0x76,0x2d,0xf3,0x74,0xb, 0xac,0xbc,0x2d,0x5f,0xbe,0x54,0x0, -0xdc,0x58,0x2, 0x6c,0xcc,0xf1,0x5b,0xbe,0x50,0x0, 0x28,0x8, 0xa, 0x55,0x1b,0x54, -0xf1,0x17,0x7d,0x43,0xf1,0x5b,0xa, 0x15,0x7e,0x43,0x38,0x50,0x71,0xf1,0x58,0x8, -0xa, 0x55,0xb, 0x54,0xf1,0x17,0x2d,0x43,0x7e,0x70,0xb, 0xac,0x7c,0x2d,0x34,0xbe, -0x34,0x0, 0xdc,0x58,0x2, 0x6c,0xcc,0xa, 0xff,0x9, 0x7f,0x30,0xab,0xbe,0x70,0xf, -0x28,0x2, 0xc1,0x65,0xbe,0xc0,0x2, 0x38,0x7c,0xe5,0x25,0x20,0xe2,0x30,0x9, 0x7f, -0x31,0x31,0xbe,0x70,0x5, 0x50,0x27,0x9, 0x7f,0x30,0xb8,0xbe,0x70,0xf, 0x50,0x1e, -0xf1,0x0, 0x7e,0x24,0x1, 0x40,0x12,0x5c,0x86,0x40,0x13,0xd1,0xf7,0x7e,0x24,0x1, -0x40,0xf1,0xd, 0x40,0x9, 0xe4,0xa, 0xef,0x19,0xbe,0x30,0xab,0x80,0x52,0xa, 0xef, -0x9, 0x7e,0x31,0x31,0xbe,0x70,0x4, 0x50,0x47,0x7e,0xb3,0x30,0xc2,0x70,0x41,0x74, -0x9, 0xac,0xbf,0x12,0x5c,0x7e,0x40,0x8, 0xd1,0xf7,0xf1,0x9, 0x40,0x2, 0x80,0x20, -0x7e,0xe4,0x1, 0x0, 0x7c,0xbf,0x12,0xc5,0x83,0x50,0x4, 0x7e,0xe4,0x2, 0x0, 0xf1, -0x0, 0x7d,0x2e,0x12,0x5c,0x86,0x40,0x18,0xd1,0xf7,0x7d,0x2e,0xf1,0xd, 0x40,0x10, -0x7e,0xd0,0x1, 0x80,0xb, 0xbe,0xc0,0x0, 0x28,0x6, 0x74,0xf, 0x19,0xbf,0x30,0xab, -0x4c,0xcc,0x78,0x2, 0xf1,0xd1,0xa, 0x3f,0x9, 0xb3,0x30,0xab,0x60,0x20,0x70,0x4, -0xf5,0x24,0x80,0x1d,0x75,0x24,0x1, 0xf1,0xd9,0x50,0x16,0x12,0x6f,0xa, 0x50,0x11, -0x74,0x9, 0xac,0xbf,0x12,0x5c,0x7e,0x40,0x8, 0x7e,0xd0,0x1, 0x80,0x3, 0x75,0x24, -0x0, 0xa, 0x4f,0x9, 0xb4,0x30,0xab,0xbe,0xb0,0x0, 0x28,0xb, 0x7d,0x34,0x2e,0x34, -0x30,0xab,0x9c,0xbd,0x7a,0x39,0xb0,0xe5,0x24,0x60,0x1c,0xd1,0xf7,0x7e,0x53,0x38, -0x51,0xa, 0x5, 0x7e,0x14,0x1, 0x0, 0xad,0x10,0x7d,0x51,0xe, 0x54,0xbd,0x35,0x28, -0x2, 0xd2,0x18,0xf1,0xba,0x80,0x1d,0x7e,0x73,0x2e,0x8d,0x19,0x74,0x2e,0x83,0x74, -0x3, 0x19,0xb4,0x31,0x27,0xf1,0xf2,0xf1,0xc3,0xe4,0x12,0x5f,0xd1,0x74,0x3, 0x19, -0xb3,0x2e,0x64,0xe4,0xda,0x3b,0x22,0x74,0x9, 0xac,0xbf,0x49,0x35,0x31,0x3d,0x22, -0x74,0x9, 0xac,0xbf,0x49,0x35,0x31,0x3b,0x22,0x7e,0x24,0x0, 0xa0,0x7d,0x13,0xbd, -0x21,0x28,0x2, 0xd3,0x22,0xc3,0x22,0x9, 0x73,0x30,0xd5,0x2, 0x2b,0x76,0x7e,0x73, -0x38,0x50,0xa, 0x37,0x22,0x2e,0x14,0x31,0x3b,0x74,0x9, 0x2, 0x1e,0x1d,0x74,0x9, -0xac,0xbf,0x49,0x45,0x30,0xcd,0x22,0x3e,0x24,0x3e,0x24,0x2e,0x24,0x0, 0xa0,0x22, -0x6e,0x24,0xff,0xff,0xb, 0x24,0xbd,0x2, 0x22,0x7e,0x29,0xb0,0x2c,0xbf,0x7a,0x29, -0xb0,0x22,0x7e,0x29,0xb0,0x2c,0xbc,0x7a,0x29,0xb0,0x22,0x7e,0x70,0x9, 0xac,0x7f, -0x9, 0x53,0x30,0xd4,0x22,0x7e,0x70,0x9, 0xac,0x7f,0x9, 0xa3,0x30,0xd5,0x22,0x7e, -0x70,0x9, 0xac,0x7e,0x2e,0x34,0x1a,0xdf,0x7e,0x30,0x9, 0x22,0x7c,0x17,0x7c,0xb, -0x7e,0xb3,0x1c,0x47,0x14,0x7a,0xb3,0x1c,0x47,0x7e,0x63,0x1c,0x47,0x7e,0x70,0x9, -0xac,0x67,0xf1,0x74,0xac,0x30,0xf1,0xc8,0x7e,0x0, 0xff,0x7e,0xb3,0x1c,0x47,0x7e, -0x70,0x9, 0xac,0xb7,0x19,0x5, 0x1a,0xe3,0x74,0x3, 0xa, 0x31,0x19,0xb3,0x1b,0xed, -0x7e,0xb3,0x31,0xa2,0x4, 0x7a,0xb3,0x31,0xa2,0x22,0x7c,0xbe,0x7c,0x7f,0xf1,0x7c, -0x74,0x1, 0x22,0x7e,0x30,0x9, 0xac,0x3e,0x2e,0x14,0x1a,0xdf,0x74,0x9, 0x2, 0x1e, -0x1d,0xe4,0xa, 0x3f,0x19,0xb3,0x30,0xab,0x22,0x9, 0x73,0x31,0x31,0xbe,0x70,0x3, -0x22,0x7e,0xb3,0x30,0xc2,0xbe,0xb0,0x0, 0x22,0x74,0x9, 0xac,0xbf,0x49,0x45,0x30, -0xcf,0x22,0x7e,0x70,0x9, 0xac,0x7f,0x2e,0x34,0x30,0xcd,0x22,0x7c,0xab,0x7f,0x71, -0x7f,0x60,0x7e,0x7b,0xb0,0x70,0x7, 0x7e,0x6b,0xa0,0x7a,0x7b,0xa0,0x22,0xa, 0x2b, -0x7e,0x6b,0xb0,0xa, 0x3b,0x9d,0x32,0x12,0x20,0x54,0xe5,0x2d,0xa, 0x2b,0xbd,0x32, -0x8, 0x17,0x7e,0x7b,0x70,0x7e,0x6b,0x60,0xbc,0x67,0x28,0x6, 0x7c,0xb7,0x2c,0xba, -0x80,0x4, 0x7c,0xb7,0x9c,0xba,0x7a,0x7b,0xb0,0x7e,0x7b,0x70,0x7a,0x6b,0x70,0x22, -0x30,0x8, 0x2c,0x7e,0x10,0x6, 0x30,0x9, 0x6, 0x7e,0x34,0x2f,0xa0,0x80,0x4, 0x7e, -0x34,0x2f,0xde,0xbe,0x37,0x30,0x1c,0x68,0x7, 0x7e,0x34,0x0, 0x1, 0x12,0x3a,0xcd, -0x1b,0x10,0x78,0xe2,0x7e,0x34,0x0, 0x1, 0x12,0x3a,0xcd,0x11,0x70,0xc2,0x8, 0x22, -0x20,0x9, 0x3, 0xd3,0x80,0x1, 0xc3,0x92,0x9, 0x74,0x1, 0x2, 0x47,0xf0,0xca,0xd8, -0xca,0x79,0x75,0x24,0x0, 0x6c,0xff,0x75,0x25,0x0, 0x75,0x26,0x0, 0x75,0x28,0x3, -0x6c,0xee,0x7e,0x48,0x1b,0xed,0x7e,0xb3,0x1c,0x50,0x70,0xe, 0x7e,0xb3,0x1c,0x4c, -0x70,0x8, 0x7e,0xb3,0x1c,0x4d,0x70,0x2, 0x41,0xc3,0x30,0x9, 0x6, 0x7e,0x58,0x2f, -0xde,0x80,0x4, 0x7e,0x58,0x2f,0xa0,0x7f,0x5, 0x71,0xa, 0x7e,0x73,0x1c,0x49,0x7a, -0x5b,0x70,0x6c,0x88,0x41,0x4d,0x74,0x9, 0xac,0xb8,0x9, 0xd5,0x1b,0x3d,0x7c,0xbd, -0x54,0xf, 0xa, 0x3b,0x51,0xf0,0xf5,0x28,0x7c,0xbd,0x54,0xf0,0xbe,0xb0,0x0, 0x28, -0x2, 0x41,0x4b,0xe5,0x28,0xbe,0xb0,0x3, 0x78,0x2, 0x41,0x4b,0x7e,0x8, 0x0, 0x28, -0x7c,0xbd,0x71,0x13,0x50,0x2, 0x41,0x4b,0x74,0x9, 0xac,0xb8,0x9, 0xb5,0x1b,0x3e, -0xf5,0x25,0x74,0x9, 0xac,0xb8,0x9, 0xb5,0x1b,0x3f,0xf5,0x26,0xbe,0xb0,0xf, 0x28, -0x3, 0x75,0x26,0xf, 0xe5,0x26,0xc4,0x54,0xf0,0xf5,0x26,0x7e,0x93,0x1c,0xbf,0xbc, -0x9d,0x28,0x56,0x7e,0xb3,0x1c,0x4e,0x70,0x2a,0x75,0x2d,0xf, 0x7e,0x8, 0x0, 0x25, -0xa, 0x3d,0x2e,0x34,0x2f,0x8c,0x6d,0x22,0x74,0x1, 0x12,0x8f,0xfc,0x75,0x2d,0x20, -0x7e,0x8, 0x0, 0x26,0xa, 0x3d,0x2e,0x34,0x2f,0x96,0x6d,0x22,0x74,0x10,0x12,0x8f, -0xfc,0x80,0xe, 0xa, 0x3d,0x9, 0xb3,0x2f,0x8c,0xf5,0x25,0x9, 0xb3,0x2f,0x96,0xf5, -0x26,0xa, 0x3d,0x51,0xf0,0xb4,0x1, 0x11,0xe4,0xa, 0x3d,0x19,0xb3,0x2f,0x8c,0x19, -0xb3,0x2f,0x96,0x75,0x25,0x0, 0x75,0x26,0x0, 0x7e,0xb3,0x1c,0xd6,0xb4,0xff,0x13, -0x75,0x25,0x0, 0x74,0x9, 0xac,0xb8,0x9, 0xb5,0x1b,0x3d,0xbe,0xb0,0xff,0x68,0x3, -0x75,0x25,0x1, 0x7e,0x70,0x9, 0xac,0x78,0x49,0x23,0x1b,0x39,0x7a,0x25,0x29,0x49, -0x23,0x1b,0x3b,0x7a,0x25,0x2b,0xe5,0x28,0xb4,0x1, 0x2d,0x75,0x27,0x0, 0x7e,0x51, -0x27,0x74,0x9, 0xac,0x5b,0x9, 0xb2,0x30,0x22,0x54,0xf, 0xbc,0xbd,0x78,0x10,0x49, -0x12,0x30,0x1e,0x7a,0x15,0x29,0x49,0x22,0x30,0x20,0x7a,0x25,0x2b,0x80,0x9, 0x5, -0x27,0xe5,0x27,0xbe,0xb0,0xa, 0x40,0xd6,0x7e,0x25,0x29,0x5e,0x40,0xf, 0x7a,0x25, -0x29,0x7e,0x25,0x2b,0x5e,0x40,0xf, 0x7a,0x25,0x2b,0x9, 0x93,0x1b,0x3d,0xa, 0x59, -0xc4,0x54,0xf0,0x7c,0xab,0xe4,0x2e,0x55,0x2b,0x7a,0x55,0x2b,0xbe,0x90,0xff,0x68, -0x1d,0xe5,0x28,0xbe,0xb0,0x1, 0x68,0x2, 0x5, 0x24,0xb, 0xf0,0xe5,0x28,0xa, 0x5b, -0x3, 0x3, 0x54,0xc0,0x7c,0xab,0xe4,0x7d,0x35,0x2e,0x35,0x29,0x80,0x7, 0x7e,0x35, -0x29,0x2e,0x34,0xc0,0x0, 0x7a,0x35,0x29,0x71,0x1, 0x79,0x30,0x0, 0x2, 0x7e,0x35, -0x2b,0x71,0x1, 0x79,0x30,0x0, 0x4, 0x7e,0x91,0x25,0x51,0xf8,0x39,0x91,0x0, 0x6, -0x7e,0x91,0x26,0x51,0xf8,0x39,0x91,0x0, 0x7, 0xb, 0xe0,0xb, 0x80,0x7e,0x93,0x1c, -0xbf,0xbc,0x98,0x28,0x2, 0x1, 0xc6,0xe5,0x24,0x39,0xb5,0x0, 0x1, 0x7e,0xb3,0x35, -0x31,0xb4,0x1, 0x11,0x7e,0xb3,0x1c,0x4d,0xb4,0x1, 0x34,0x12,0x6f,0xb5,0x74,0x1, -0x12,0x47,0xf0,0x80,0x2a,0xbe,0xf0,0x0, 0x38,0xc, 0x7e,0xb3,0x1c,0x4d,0x70,0x6, -0x7e,0xb3,0x1c,0x53,0x60,0x19,0x30,0x9, 0x6, 0x7e,0x34,0x2f,0xa0,0x80,0x4, 0x7e, -0x34,0x2f,0xde,0xbe,0x37,0x30,0x1c,0x68,0x4, 0xd2,0x8, 0x80,0x2, 0x11,0x70,0x7e, -0xb3,0x1c,0x4c,0x60,0xb, 0x7e,0xb3,0x31,0xa2,0x70,0x5, 0x7f,0x4, 0x12,0x56,0xd3, -0xe4,0x7a,0xb3,0x1c,0x50,0x7a,0xb3,0x1c,0x4c,0x7a,0xb3,0x1c,0x4d,0x7a,0xb3,0x1c, -0x53,0x80,0x4, 0xe4,0x12,0x47,0xf0,0x7e,0x34,0x0, 0x5a,0xca,0x39,0x7e,0x18,0x1b, -0x39,0x7e,0x8, 0x30,0x1e,0x12,0x1f,0xed,0x1b,0xfd,0x4c,0xff,0x78,0xd, 0x7e,0x8, -0x30,0x1e,0x7e,0x34,0x0, 0x5a,0x74,0xff,0x12,0x20,0x12,0xda,0x79,0xda,0xd8,0x22, -0x2d,0x39,0x7d,0x28,0x7e,0x1b,0xb0,0x22,0x74,0x6, 0xac,0xbe,0x7f,0x15,0x2d,0x35, -0x22,0x74,0x6, 0xac,0xbe,0x7f,0x5, 0x2d,0x15,0x22,0x7e,0x34,0x0, 0x3e,0x74,0xff, -0x2, 0x20,0x12,0x7c,0x9b,0x7e,0xb, 0xb0,0x60,0x3, 0xb4,0x2, 0x2f,0xa, 0x39,0x9, -0xa3,0x2e,0x83,0xbe,0xa3,0x2e,0x8d,0x50,0xe, 0x7d,0x23,0x2e,0x24,0x2e,0x83,0x7c, -0xba,0x4, 0x7a,0x29,0xb0,0xd3,0x22,0xbe,0xa3,0x2e,0x8d,0x40,0x9, 0xbe,0xa0,0xff, -0x68,0x4, 0xe4,0x7a,0xb, 0xb0,0x74,0xff,0xa, 0x39,0x80,0x13,0xa, 0x39,0x9, 0xb3, -0x2e,0x83,0xbe,0xb0,0xff,0x68,0x7, 0xe4,0x19,0xb3,0x2e,0x83,0xd3,0x22,0xe4,0x19, -0xb3,0x2e,0x83,0xc3,0x22,0x7d,0x52,0x7d,0x43,0x49,0x35,0x0, 0x4, 0x1b,0x34,0x91, -0x62,0x7f,0x71,0x6d,0x33,0x7d,0x23,0x3e,0x24,0x2d,0x25,0x49,0x22,0x0, 0x6, 0xbd, -0x24,0x28,0x8, 0xb, 0x34,0xbe,0x34,0x0, 0x3, 0x48,0xea,0xbe,0x34,0x0, 0x3, 0x58, -0xb, 0xb, 0x58,0x10,0xad,0x13,0x6d,0x0, 0x9f,0x70,0x80,0x4, 0x9f,0x77,0x6d,0x22, -0x4d,0x33,0x78,0x4, 0x7f,0x17,0x80,0x17,0x1b,0x34,0x3e,0x34,0x2d,0x35,0x49,0x13, -0x0, 0xc, 0x6d,0x0, 0x7d,0x34,0x9d,0x32,0x6d,0x22,0x12,0x1d,0x7c,0x2f,0x17,0x2e, -0x18,0x0, 0x7f,0x7c,0x76,0x7c,0x65,0xa, 0x24,0x22,0x7d,0xd2,0x7d,0x23,0x49,0x3d, -0x0, 0x2, 0xbd,0x32,0x38,0x9, 0x9d,0x23,0x7d,0x32,0x71,0xea,0x2d,0x32,0x22,0x1b, -0x34,0x9d,0x32,0x71,0xea,0x1b,0x34,0x9d,0x32,0x22,0x7d,0x2d,0x71,0x65,0x7d,0x23, -0x49,0x3d,0x0, 0x4, 0x22,0x7e,0x25,0x1b,0x61,0xca,0xca,0xf8,0x7e,0xa3,0x1c,0x47, -0x4c,0xaa,0x78,0xe, 0x7e,0xb3,0x1c,0x48,0xbe,0xb0,0x0, 0x28,0xd, 0x12,0x5f,0xeb, -0x80,0x8, 0xbe,0xa0,0x0, 0x28,0x3, 0x12,0x89,0x29,0x7e,0x34,0x0, 0x5a,0xca,0x39, -0x7e,0x18,0x1a,0xdf,0x7e,0x8, 0x1b,0x39,0x12,0x1f,0xed,0x1b,0xfd,0x6c,0xff,0x74, -0x9, 0xac,0xbf,0x49,0xc5,0x1a,0xdf,0x49,0xb5,0x1a,0xe1,0x7d,0x3c,0x71,0xf5,0x7d, -0xa3,0x7d,0x3b,0x91,0x5d,0x7d,0x93,0x74,0x9, 0xac,0xbf,0x59,0xa5,0x1b,0x39,0x59, -0x95,0x1b,0x3b,0xb, 0xf0,0xbe,0xf0,0xa, 0x40,0xd5,0xda,0xf8,0x22,0x7e,0x25,0x1d, -0x61,0xca,0x6d,0x22,0x7c,0x56,0x7c,0x67,0x6c,0x77,0x22,0xca,0xd8,0xca,0x79,0x7c, -0xf4,0x7c,0xd5,0x7c,0xeb,0x7d,0xe3,0x7c,0xbf,0x7c,0x5d,0xd1,0x2e,0x7d,0xf3,0x7e, -0x70,0x9, 0xac,0x7d,0x9, 0x53,0x19,0xad,0xbe,0x50,0x7, 0x28,0x16,0xa, 0x2f,0x9, -0xb2,0x2e,0x64,0x70,0xe, 0xd1,0x15,0xbe,0x24,0x0, 0xfa,0x50,0x6, 0x6d,0x22,0x59, -0x25,0x2e,0x6e,0xd1,0x15,0xbe,0x24,0x0, 0xa, 0x50,0x6, 0x7e,0x44,0x3, 0x0, 0x80, -0x4, 0x7e,0x44,0x0, 0xf0,0x7a,0x45,0x66,0xbd,0x4e,0x28,0x23,0xbe,0x24,0x0, 0xfa, -0x50,0x1d,0xbe,0xf4,0x0, 0x6, 0x28,0x17,0xbe,0x24,0x0, 0xa, 0x50,0xb, 0x7d,0x45, -0x2e,0x44,0x2e,0x6e,0xb, 0x24,0x1b,0x48,0x20,0x7e,0xf4,0x0, 0x6, 0x80,0x8, 0x7e, -0x24,0x0, 0xfa,0x59,0x25,0x2e,0x6e,0xbe,0xf4,0x0, 0x40,0x50,0x12,0xad,0xff,0x2e, -0xf4,0x0, 0x20,0x1e,0xf4,0x1e,0xf4,0x1e,0xf4,0x1e,0xf4,0x1e,0xf4,0x1e,0xf4,0x74, -0x9, 0xac,0xbe,0xf1,0x43,0x12,0x20,0x54,0x7d,0xe3,0x74,0x9, 0xac,0xbe,0x49,0x25, -0x1b,0x93,0x74,0x9, 0xac,0xbd,0xf1,0x3c,0x12,0x20,0x54,0x7d,0xd3,0x7d,0x4e,0x2d, -0x4d,0x74,0x2, 0xac,0xbf,0x49,0x35,0x2f,0x57,0x12,0x20,0x54,0x7d,0x13,0x74,0x2, -0xac,0xbf,0x49,0x35,0x2f,0x43,0x12,0x20,0x54,0x2d,0x31,0xbe,0x34,0x4, 0x0, 0x50, -0x69,0x7e,0xb3,0x35,0x31,0x70,0x63,0x7d,0x13,0xad,0x13,0x2e,0x8, 0x2, 0x0, 0x74, -0xa, 0x1e,0x14,0x1e,0x4, 0x50,0x3, 0x4e,0x20,0x80,0x14,0x78,0xf4,0x7d,0x21,0xa, -0x5f,0x9, 0x35,0x2e,0x64,0xbe,0x30,0x0, 0x28,0x18,0x7d,0xc4,0x1e,0xc4,0x1e,0xc4, -0x1e,0xc4,0x1e,0xc4,0x1e,0xc4,0xbe,0x24,0x0, 0x20,0x50,0x13,0x7e,0x24,0x0, 0x20, -0x80,0xd, 0x7d,0x14,0xf1,0x4e,0x1e,0x14,0x1e,0x14,0x12,0x6e,0xba,0x7d,0xc1,0xbe, -0xc4,0x0, 0x80,0x28,0x4, 0x7e,0xc4,0x0, 0x80,0x2d,0x2c,0x2d,0x32,0x91,0x62,0x7d, -0x14,0x12,0x1d,0x96,0xbd,0x3f,0x50,0x2, 0x7d,0xf3,0x7d,0x4d,0xd1,0x1e,0x7e,0x50, -0x9, 0xac,0x5e,0x49,0x32,0x1b,0x93,0x74,0x9, 0xac,0xbd,0x49,0x55,0x1a,0xdf,0xbd, -0x53,0x28,0xf, 0x7d,0x52,0x2e,0x54,0x1b,0x93,0x7d,0xd3,0x2d,0xd4,0x1b,0x58,0xd0, -0x80,0xd, 0x7d,0xd2,0x2e,0xd4,0x1b,0x93,0x7d,0x53,0x9d,0x54,0x1b,0xd8,0x50,0x7d, -0x4e,0xd1,0x1e,0x7e,0x70,0x9, 0xac,0x7e,0x49,0xd3,0x1b,0x95,0x74,0x9, 0xac,0xbd, -0x49,0x25,0x1a,0xe1,0xbd,0x2d,0x28,0xf, 0x7d,0x53,0x2e,0x54,0x1b,0x95,0x7d,0x2d, -0x2d,0x24,0x1b,0x58,0x20,0x80,0x9, 0x2e,0x34,0x1b,0x95,0x9d,0xd4,0x1b,0x38,0xd0, -0xda,0x79,0xda,0xd8,0x22,0x74,0x2, 0xac,0xbf,0x49,0x25,0x2e,0x6e,0x22,0x7d,0x3f, -0xad,0x34,0x7c,0x76,0x7c,0x65,0xa, 0x24,0x7d,0x43,0x5e,0x90,0xfc,0x22,0xca,0xf8, -0x7c,0xfb,0x7d,0x43,0x7d,0xf4,0x7e,0x17,0x1c,0xd4,0x74,0x9, 0xac,0xb5,0x9, 0x75, -0x1a,0xe5,0xbe,0x70,0xa, 0x28,0x14,0xa, 0x37,0x9e,0x34,0x0, 0xa, 0x7d,0x21,0x1e, -0x24,0x1e,0x24,0x1e,0x24,0x1e,0x24,0xad,0x32,0x2d,0x13,0xbd,0x14,0x38,0x6, 0x7e, -0x34,0x1, 0x0, 0x80,0x11,0x7d,0x34,0x91,0x62,0x12,0x1d,0x96,0xbe,0x34,0x0, 0x10, -0x50,0x4, 0x7e,0x34,0x0, 0x10,0x74,0x2, 0xac,0xbf,0x49,0x25,0x2e,0xe9,0xbd,0x2f, -0x28,0xc, 0xbe,0x24,0x0, 0x40,0x28,0x6, 0x49,0x35,0x2e,0x4e,0x80,0x4, 0x59,0x35, -0x2e,0x4e,0x59,0xf5,0x2e,0xe9,0xbe,0x34,0x1, 0x0, 0x28,0x4, 0x7e,0x34,0x1, 0x0, -0xda,0xf8,0x22,0x81,0x6b,0xca,0x3b,0x7c,0xfb,0x6c,0xee,0x80,0x4e,0x6c,0xcc,0x74, -0x9, 0xac,0xbc,0x9, 0x45,0x1b,0x97,0x7e,0x70,0x9, 0xac,0x7e,0x9, 0x53,0x1a,0xe3, -0xbc,0x45,0x68,0x7, 0xb, 0xc0,0xbe,0xc0,0xa, 0x40,0xe4,0xbe,0xc0,0xa, 0x50,0x60, -0x74,0x9, 0xac,0xbc,0x9, 0xd5,0x1b,0x97,0xf1,0x43,0x12,0x20,0x54,0x7d,0x43,0x74, -0x9, 0xac,0xbc,0x49,0x25,0x1b,0x93,0xf1,0x38,0x12,0x20,0x54,0x2d,0x34,0x7a,0x35, -0x24,0x7c,0xbc,0x7c,0x5e,0x7c,0x4d,0xd1,0xa3,0xb, 0xe0,0xbc,0xfe,0x38,0xae,0x80, -0x2f,0x74,0x9, 0xac,0xbe,0x9, 0xd5,0x1a,0xe3,0xbe,0xd0,0xa, 0x50,0x20,0xa, 0x3d, -0x9, 0xb3,0x1b,0xed,0xb4,0x1, 0x17,0xe4,0x19,0xb3,0x2e,0x64,0x6d,0x44,0x74,0x2, -0xac,0xbd,0x59,0x45,0x2e,0x4e,0x59,0x45,0x2e,0xe9,0x59,0x45,0x2e,0x6e,0xb, 0xe0, -0xbe,0xe0,0xa, 0x40,0xcc,0xda,0x3b,0x22,0x74,0x9, 0xac,0xbe,0x49,0x35,0x1a,0xdf, -0x9d,0x32,0x22,0x49,0x25,0x1b,0x95,0x49,0x33,0x1a,0xe1,0x9d,0x32,0x22,0x1e,0x14, -0x1e,0x14,0x1e,0x14,0x22,0xca,0xe8,0x7e,0x18,0x1b,0xed,0x7a,0x1d,0x24,0x6c,0x77, -0x7e,0x60,0xff,0x12,0x9a,0xd4,0xe4,0xa, 0x27,0x19,0xb2,0x2, 0x8f,0x74,0xff,0x19, -0xb2,0x2, 0xa1,0x19,0xb2,0x2, 0xab,0xb, 0x70,0xa5,0xbf,0xa, 0xe3,0x7e,0x63,0x1c, -0x47,0xa5,0xbe,0x0, 0x32,0x7e,0xb3,0x35,0xd7,0x70,0x3, 0x2, 0x9a,0x14,0x6c,0x77, -0x7e,0x24,0x7f,0xff,0x12,0x9a,0x95,0x79,0x20,0x0, 0x14,0x12,0x9a,0x95,0x79,0x20, -0x0, 0x28,0x74,0x2, 0xac,0xb7,0x59,0x25,0x35,0xd8,0x59,0x25,0x35,0xec,0xb, 0x70, -0xa5,0xbf,0xa, 0xdc,0x2, 0x9a,0x14,0x7e,0xb3,0x35,0xd7,0x70,0x4a,0xbe,0x60,0x0, -0x28,0x45,0x6c,0x77,0x80,0x37,0x74,0x9, 0xac,0xb7,0x49,0x45,0x1a,0xdf,0x12,0x9a, -0x95,0x79,0x40,0x0, 0x14,0x74,0x9, 0xac,0xb7,0x49,0x45,0x1a,0xe1,0x12,0x9a,0x95, -0x79,0x40,0x0, 0x28,0x12,0x9a,0x95,0x12,0x9a,0xdd,0xac,0xb7,0x59,0x45,0x35,0xec, -0x74,0x1, 0xa, 0x27,0x12,0x9a,0xcb,0x19,0x75,0x1a,0xe3,0xb, 0x70,0x7e,0x63,0x1c, -0x47,0xbc,0x67,0x38,0xc1,0x41,0x14,0x6c,0x77,0x7e,0x44,0x7f,0xff,0x51,0xb1,0x59, -0x45,0x15,0x7e,0x59,0x45,0x15,0xa4,0x59,0x45,0x15,0xa6,0xb, 0x70,0xa5,0xbf,0xa, -0xe8,0x7e,0x63,0x35,0xd7,0xbe,0x63,0x1c,0x47,0x28,0xd, 0xbe,0x60,0x2, 0x40,0x8, -0x74,0x1, 0x7a,0xb3,0x35,0xd6,0x80,0x5, 0xe4,0x7a,0xb3,0x35,0xd6,0x6c,0x77,0x1, -0xf6,0x6c,0xee,0x7e,0x50,0x2, 0xac,0x5e,0x7e,0x7d,0x24,0x2d,0xf2,0x69,0x7, 0x0, -0x14,0xbe,0x4, 0x7f,0xff,0x78,0x2, 0x1, 0xeb,0xa, 0x1e,0x9, 0xb1,0x2, 0xab,0xb4, -0xff,0x2, 0x80,0x2, 0x1, 0xeb,0x7e,0xb3,0x35,0xd6,0xb4,0x1, 0x5e,0x49,0x52,0x35, -0xd8,0xbe,0x54,0x7f,0xff,0x68,0x54,0x49,0x22,0x35,0xd8,0x69,0x57,0x0, 0x14,0x7d, -0x45,0x9d,0x42,0x2d,0x45,0x74,0x2, 0xac,0xbe,0x49,0xd5,0x35,0xec,0x69,0x57,0x0, -0x28,0x7d,0x25,0x9d,0x2d,0x2d,0x25,0xbe,0x44,0x0, 0x80,0x58,0x4, 0x7e,0x44,0x0, -0x80,0xbe,0x24,0x0, 0x80,0x58,0x4, 0x7e,0x24,0x0, 0x80,0x7e,0x63,0x1c,0xe1,0x51, -0xbc,0xbd,0x54,0x58,0x2, 0x7d,0x45,0x7e,0x63,0x1c,0xe2,0x51,0xbc,0xbd,0x52,0x58, -0x2, 0x7d,0x25,0x51,0xb1,0x59,0x25,0x15,0x7e,0x80,0x12,0x74,0x2, 0xac,0xb7,0x3e, -0x54,0x59,0x5, 0x15,0x7c,0x69,0x7, 0x0, 0x28,0x59,0x5, 0x15,0x7e,0xa, 0x7, 0x19, -0xe0,0x2, 0xa1,0x74,0x1, 0x19,0xb1,0x2, 0xab,0x80,0x9, 0xb, 0xe0,0xbe,0xe0,0xa, -0x50,0x2, 0x1, 0x43,0xb, 0x70,0x7e,0x63,0x35,0xd7,0xbc,0x67,0x28,0x2, 0x1, 0x41, -0x6c,0x77,0x51,0x95,0x51,0xdd,0xac,0xb7,0x59,0x45,0x35,0xec,0xb, 0x70,0xa5,0xbf, -0xa, 0xf0,0x6c,0x77,0xa, 0x27,0x9, 0xb2,0x2, 0xa1,0xb4,0xff,0x20,0x6c,0xee,0xa, -0x2e,0x9, 0xb2,0x2, 0xab,0xb4,0xff,0xe, 0xa, 0x17,0x19,0xe1,0x2, 0xa1,0x74,0x1, -0x19,0xb2,0x2, 0xab,0x80,0x7, 0xb, 0xe0,0xbe,0xe0,0xa, 0x40,0xe2,0xb, 0x70,0xa5, -0xbf,0xa, 0xd1,0x6c,0x77,0x80,0x1e,0x7e,0x10,0x9, 0xac,0x17,0x49,0x40,0x1a,0xdf, -0x7e,0x30,0x2, 0xac,0x37,0x3e,0x14,0x59,0x41,0x15,0xa4,0x49,0x20,0x1a,0xe1,0x59, -0x21,0x15,0xa6,0xb, 0x70,0x7e,0x63,0x1c,0x47,0xbc,0x67,0x38,0xda,0x7e,0x34,0x15, -0x7c,0x7a,0x37,0x2, 0x9b,0x7e,0x34,0x15,0xa4,0x7a,0x37,0x2, 0x9d,0x7e,0x34,0x15, -0xcc,0x7a,0x37,0x2, 0x9f,0x7e,0x73,0x35,0xd7,0x7a,0x73,0x2, 0x99,0x7e,0x73,0x1c, -0x47,0x7a,0x73,0x2, 0x9a,0x7e,0x8, 0x2, 0x99,0x12,0x10,0x0, 0x6c,0x77,0x80,0x49, -0x7e,0x60,0xff,0x6c,0xee,0x74,0x2, 0xac,0xbe,0x49,0x15,0x15,0xcc,0xa, 0x27,0xbd, -0x21,0x78,0x8, 0xa, 0x2e,0x9, 0x62,0x2, 0xa1,0x80,0x7, 0xb, 0xe0,0xbe,0xe0,0xa, -0x40,0xe3,0xbe,0x60,0xff,0x68,0x20,0x51,0xd4,0x74,0x1, 0xa, 0x26,0x51,0xcb,0x49, -0x25,0x1a,0xdf,0x51,0xa7,0x79,0x20,0x0, 0x14,0x74,0x9, 0xac,0xb7,0x49,0x25,0x1a, -0xe1,0x51,0xa7,0x79,0x20,0x0, 0x28,0xb, 0x70,0x7e,0x53,0x1c,0x47,0xbc,0x57,0x38, -0xaf,0x6c,0x77,0xa, 0x27,0x9, 0xb2,0x2, 0x8f,0xbe,0xb0,0x1, 0x68,0x10,0x7e,0x44, -0x7f,0xff,0x51,0x95,0x79,0x40,0x0, 0x14,0x51,0x95,0x79,0x40,0x0, 0x28,0xb, 0x70, -0xa5,0xbf,0xa, 0xdf,0x7e,0xe3,0x1c,0x47,0x7a,0xe3,0x35,0xd7,0x6c,0x77,0xa, 0x27, -0x9, 0xb2,0x2, 0x8f,0xb4,0x1, 0x35,0x51,0x9f,0x29,0xb0,0x0, 0xa, 0xb4,0x1, 0x6, -0x74,0x3, 0x39,0xb0,0x0, 0xa, 0x51,0x9f,0x29,0x60,0x0, 0xa, 0xa5,0xbe,0x3, 0x6, -0xe4,0x7a,0xb, 0xb0,0x80,0x3c,0xa5,0xbe,0x0, 0x7, 0x74,0x2, 0x7a,0xb, 0xb0,0x80, -0x31,0xa5,0xbe,0x2, 0x2d,0x74,0x2, 0x7a,0xb, 0xb0,0x80,0x26,0x51,0x9f,0x29,0xb0, -0x0, 0xa, 0xbe,0xb0,0x2, 0x68,0x2, 0x70,0x14,0x74,0x1, 0x7a,0xb, 0xb0,0x7c,0xae, -0xb, 0xe0,0x7e,0x60,0x9, 0xac,0xa6,0x19,0x75,0x1a,0xe3,0x80,0x5, 0x74,0x3, 0x7a, -0xb, 0xb0,0x51,0x9f,0x7e,0xb, 0x60,0x39,0x60,0x0, 0xa, 0xb, 0x70,0xbe,0x70,0xa, -0x40,0x8c,0xda,0xe8,0x22,0x74,0x2, 0xac,0xb7,0x7e,0xd, 0x24,0x2d,0x15,0x22,0xa, -0x27,0x7e,0xd, 0x24,0x2d,0x12,0x22,0x74,0x2, 0xac,0xb6,0x7e,0xd, 0x24,0x2d,0x15, -0x22,0x74,0x2, 0xac,0xb7,0x3e,0x54,0x59,0x45,0x15,0x7c,0x22,0xa, 0xc6,0x7e,0xd4, -0x1, 0x0, 0xad,0xdc,0x7d,0x5d,0x9e,0x54,0x0, 0x80,0x22,0x19,0xb2,0x2, 0x8f,0x74, -0x9, 0xac,0xb7,0x22,0x74,0x9, 0xac,0xb7,0x19,0x65,0x1a,0xe3,0x22,0x69,0x20,0x0, -0x14,0x59,0x25,0x35,0xd8,0x69,0x40,0x0, 0x28,0x74,0x2, 0x22,0xca,0x79,0x7a,0x1d, -0x28,0x7a,0xd, 0x24,0x7e,0x75,0x2c,0x7e,0xb3,0x1c,0xdb,0x60,0x14,0x7e,0xb3,0x34, -0x8, 0x70,0xe, 0x7e,0xb3,0x34,0xec,0x70,0x8, 0x7e,0xb3,0x36,0x48,0x70,0x2, 0xe, -0x74,0x7a,0x75,0x2e,0x7e,0xd, 0x24,0x7e,0x1d,0x28,0x71,0x70,0x30,0x3, 0xe, 0x7a, -0x75,0x2e,0xb1,0xfa,0x51,0x97,0x7e,0x1d,0x28,0x2d,0x35,0x91,0x34,0xda,0x79,0x22, -0x7e,0x37,0x1c,0xc1,0x1e,0x34,0x7a,0x35,0x2c,0xd2,0x3, 0x7e,0x8, 0x4, 0xd4,0x7e, -0x18,0x4, 0x0, 0x51,0xec,0x7e,0x37,0x1a,0xca,0xe, 0x34,0x7a,0x35,0x2c,0xc2,0x3, -0x7e,0x8, 0x5, 0x3e,0x7e,0x18,0x4, 0x6a,0x51,0xec,0x12,0x87,0xaa,0x61,0x5f,0xe4, -0x7a,0xb3,0x3, 0xff,0x7e,0xb3,0x1a,0xd9,0x60,0x5, 0xe4,0x7a,0xb3,0x3, 0xff,0x22, -0xca,0x3b,0x7f,0x61,0x7f,0x50,0x7e,0x73,0x1c,0xe0,0xa, 0x37,0x3e,0x34,0xca,0x39, -0x7f,0x16,0x7f,0x5, 0x12,0x1f,0xed,0x1b,0xfd,0x6c,0xdd,0xb1,0x51,0x7a,0xb3,0x2, -0xd1,0x6c,0xcc,0x80,0x4f,0xb1,0x2d,0x78,0x49,0x91,0x2b,0xb, 0x1a,0x40,0x7d,0x3f, -0x12,0x20,0x54,0x7d,0x53,0x7d,0x34,0x12,0x20,0x54,0xbd,0x35,0x58,0x2, 0x7d,0xf4, -0xbe,0x45,0x2e,0x8, 0x5, 0x7e,0x45,0x2e,0x80,0xb, 0x6d,0x55,0x9e,0x55,0x2e,0xbd, -0x54,0x8, 0x2, 0x7d,0x45,0x7d,0x34,0x1a,0x26,0x1a,0x24,0x2f,0x41,0x7e,0xb3,0x2, -0xd1,0x4, 0x7a,0xb3,0x2, 0xd1,0xbe,0x44,0x0, 0x0, 0x48,0x4, 0x5, 0x30,0x80,0x2, -0x15,0x30,0xb, 0xc0,0x7e,0x73,0x1c,0xe2,0xbc,0x7c,0x38,0xa9,0x7e,0x73,0x2, 0xd1, -0x4c,0x77,0x68,0x2b,0xb1,0x5c,0x8, 0xe, 0xb1,0x40,0x7e,0x53,0x2, 0xd1,0xa, 0x25, -0xbd,0x32,0x78,0x2, 0x7d,0x7f,0x6c,0xcc,0x80,0xd, 0xb1,0x2d,0x78,0x7, 0x91,0x2b, -0xb1,0x47,0x1b,0x1a,0xe0,0xb, 0xc0,0x7e,0x73,0x1c,0xe2,0xbc,0x7c,0x38,0xeb,0xb, -0xd0,0xbe,0xd0,0x3, 0x50,0x2, 0x61,0x8b,0xda,0x3b,0x22,0x74,0x2, 0xac,0xbc,0x7f, -0x16,0x2d,0x35,0x22,0xca,0x3b,0x7f,0x61,0x7f,0x50,0x7e,0x14,0x23,0x5a,0x7e,0x4, -0x0, 0xff,0xd1,0x2, 0x7a,0x1d,0x31,0xd1,0xa, 0xca,0x39,0x7f,0x16,0x7f,0x5, 0x12, -0x1f,0xed,0x1b,0xfd,0x6c,0xdd,0xb1,0x51,0x7a,0xb3,0x2, 0x8f,0x6c,0xcc,0x80,0x53, -0xb1,0x1d,0x40,0x4d,0xb1,0x13,0x50,0x49,0x91,0x2b,0xb, 0x1a,0x10,0x7d,0x3f,0x12, -0x20,0x54,0x7d,0x3, 0x7d,0x31,0x12,0x20,0x54,0xbd,0x30,0x58,0x2, 0x7d,0xf1,0xbe, -0x15,0x2e,0x8, 0x5, 0x7e,0x15,0x2e,0x80,0xb, 0x6d,0x0, 0x9e,0x5, 0x2e,0xbd,0x1, -0x8, 0x2, 0x7d,0x10,0x7d,0x31,0x1a,0x26,0x1a,0x24,0x2f,0x41,0x7e,0xb3,0x2, 0x8f, -0x4, 0x7a,0xb3,0x2, 0x8f,0xbe,0x14,0x0, 0x0, 0x48,0x4, 0x5, 0x30,0x80,0x2, 0x15, -0x30,0xb, 0xc0,0x7e,0x73,0x1c,0xe1,0xbc,0x7c,0x38,0xa5,0x7e,0x73,0x2, 0x8f,0x4c, -0x77,0x68,0x44,0xb1,0x5c,0x8, 0xe, 0xb1,0x40,0x7e,0x53,0x2, 0x8f,0xa, 0x25,0xbd, -0x32,0x78,0x2, 0x7d,0x7f,0xbe,0x75,0x2e,0x8, 0x5, 0x7e,0x75,0x2e,0x80,0xb, 0x6d, -0xee,0x9e,0xe5,0x2e,0xbd,0xe7,0x8, 0x2, 0x7d,0x7e,0x6c,0xcc,0x80,0x11,0xb1,0x1d, -0x40,0xb, 0xb1,0x13,0x50,0x7, 0x91,0x2b,0xb1,0x47,0x1b,0x1a,0xe0,0xb, 0xc0,0x7e, -0x73,0x1c,0xe1,0xbc,0x7c,0x38,0xe7,0xb, 0xd0,0xbe,0xd0,0x3, 0x50,0x2, 0x81,0x56, -0xda,0x3b,0x22,0x7c,0x1d,0x2e,0x10,0x32,0xa5,0xe7,0xbc,0xab,0x22,0xa, 0xec,0x9, -0xae,0x1d,0x33,0x7c,0x1d,0x2e,0x10,0x31,0xa5,0xe7,0xbc,0xab,0x22,0xa, 0xec,0x9, -0x7e,0x1d,0x56,0xa, 0x37,0x7e,0x24,0x0, 0x3, 0x8d,0x32,0xa, 0xed,0xbd,0x2e,0x22, -0xe5,0x30,0x1a,0x3b,0x2, 0x20,0x54,0xb, 0x1a,0xe0,0x9d,0xe7,0x7f,0x15,0x2d,0x35, -0x22,0x7e,0xf4,0x7f,0xff,0x75,0x30,0x0, 0x9f,0x44,0xe4,0x22,0xa, 0x17,0x6d,0x0, -0x7f,0x14,0x12,0x1d,0xe9,0x7d,0x73,0x12,0x20,0x54,0x7d,0xe3,0x7d,0x3f,0x12,0x20, -0x54,0xbd,0x3e,0x22,0xca,0x79,0x7e,0x8, 0x2, 0x8f,0x7e,0x34,0x0, 0x42,0xe4,0x12, -0x20,0x12,0x6d,0x77,0xa9,0xd1,0xcb,0x74,0x1, 0x12,0x0, 0xe, 0x6c,0x33,0x80,0x19, -0x74,0x2, 0xac,0xb3,0x49,0x25,0x5, 0xa8,0x7e,0x7f,0x36,0x18,0x2d,0xf5,0xb, 0x7a, -0x30,0x9d,0x32,0x59,0x35,0x2, 0x8f,0xb, 0x30,0x7e,0x23,0x1c,0xe0,0xbc,0x23,0x38, -0xdf,0xa9,0xc1,0xcb,0x7e,0x34,0x0, 0xb4,0x7a,0x35,0x2e,0x7e,0x18,0x2, 0x8f,0x7f, -0x1, 0x71,0x70,0x6c,0x33,0x80,0xc, 0xb1,0xef,0xbd,0x37,0x28,0x4, 0xb1,0xef,0x7d, -0x73,0xb, 0x30,0x7e,0x23,0x1c,0xe0,0xbc,0x23,0x38,0xec,0xa9,0xc1,0xcb,0x7e,0x37, -0x1d,0x89,0xbd,0x37,0x50,0x6, 0x74,0x2, 0x7a,0xb3,0x36,0x17,0xda,0x79,0x22,0x74, -0x2, 0xac,0xb3,0x49,0x35,0x2, 0x8f,0x2, 0x20,0x54,0x7e,0xb3,0x1c,0xe6,0x7e,0x70, -0x2, 0x22,0x69,0x30,0x0, 0x2, 0xb, 0xa, 0x20,0x22,0x7e,0x73,0x1c,0xdf,0xa, 0x37, -0x3e,0x34,0x22,0xc1,0x15,0xca,0x79,0x6c,0xff,0x7e,0xd7,0x1c,0xcc,0x6c,0xee,0x80, -0x54,0x7c,0xbe,0x12,0x4c,0xa3,0xbd,0x3d,0x48,0x49,0x7c,0xbe,0x12,0x4f,0xad,0x60, -0x42,0x7e,0xc4,0x0, 0x9, 0xca,0xc9,0x7e,0x70,0x9, 0xac,0x7e,0x2e,0x34,0x19,0xa7, -0x6d,0x22,0x7e,0x30,0x9, 0xac,0x3f,0x2e,0x14,0x1a,0xdf,0x6d,0x0, 0x12,0x1f,0xed, -0x1b,0xfd,0x7e,0xc4,0x0, 0x7, 0xca,0xc9,0x7e,0x70,0x7, 0xac,0x7e,0x2e,0x34,0x2e, -0xfd,0x6d,0x22,0x7e,0x30,0x7, 0xac,0x3f,0x2e,0x14,0x2e,0xfd,0x12,0x1f,0xed,0x1b, -0xfd,0xb, 0xf0,0xb, 0xe0,0x12,0x4f,0xc3,0x38,0xa7,0x7a,0x73,0x1a,0xc4,0x7a,0xf3, -0x1c,0x47,0xda,0x79,0x22,0x12,0x5f,0xf2,0x68,0xfb,0x20,0x93,0xfd,0x22,0x7e,0x24, -0x0, 0x64,0xd1,0x9d,0x50,0x4, 0x7e,0x24,0x0, 0x32,0x7d,0x32,0x22,0xc2,0x4, 0x7e, -0xb3,0x1c,0xdd,0xbe,0xb0,0x1, 0x68,0x7, 0x7e,0xb3,0x1c,0xda,0xb4,0x1, 0x12,0x7e, -0xb3,0x34,0x8, 0x70,0xc, 0x7e,0x37,0x1a,0xbb,0xbe,0x34,0x1, 0x90,0x58,0x2, 0xd2, -0x4, 0xa2,0x4, 0x22,0xd1,0x9d,0x50,0x12,0x7e,0x37,0x1d,0x89,0xbe,0x34,0x1, 0x2c, -0x28,0x8, 0x7e,0x34,0x1, 0x2c,0x7a,0x37,0x1d,0x89,0x22,0x7e,0xa3,0x1c,0x48,0xbe, -0xa0,0x0, 0x38,0x2f,0xbe,0xa3,0x1c,0x47,0x50,0x19,0x7e,0xb3,0x1c,0x51,0xbe,0xb3, -0x2f,0x8b,0x28,0x14,0x7e,0xb3,0x2f,0x8b,0x4, 0x7a,0xb3,0x2f,0x8b,0x7a,0xa3,0x1c, -0x47,0x80,0x5, 0xe4,0x7a,0xb3,0x2f,0x8b,0x7e,0xb3,0x1c,0x47,0x70,0x5, 0xe4,0x7a, -0xb3,0x1c,0x50,0x22,0xca,0x3b,0x7e,0xd3,0x35,0x24,0x5e,0xd0,0x1, 0x7e,0xe3,0x1c, -0x47,0x4c,0xee,0x78,0x20,0x6c,0xff,0x6d,0x33,0x7e,0x50,0x2, 0xac,0x5f,0x12,0xa0, -0xf0,0x74,0x9, 0xac,0xbf,0x12,0xa0,0xf8,0xa, 0x3f,0x19,0xb3,0x2f,0x80,0xb, 0xf0, -0xbe,0xf0,0xa, 0x78,0xe2,0x12,0xa1,0x12,0x7e,0xd4,0x0, 0x50,0xad,0xd3,0x2e,0xd4, -0xc, 0x80,0x6c,0xff,0x2, 0xa0,0xdd,0x74,0x9, 0xac,0xbf,0x9, 0xb5,0x1a,0xe3,0x54, -0xf, 0xf5,0x25,0xbe,0xb0,0xa, 0x40,0x3, 0x2, 0xa0,0xdb,0xe5,0x25,0xa, 0xcb,0x9, -0xbc,0x1b,0xed,0xbe,0xb0,0x1, 0x78,0x3, 0x2, 0xa0,0xc3,0x75,0x24,0x0, 0x12,0xcf, -0x95,0x9, 0xc5,0x2e,0x93,0xbe,0xc1,0x25,0x68,0x3, 0x2, 0xa0,0xb5,0x49,0x25,0x2e, -0x91,0x74,0x9, 0xac,0xbf,0x49,0x35,0x1a,0xe1,0x12,0x4f,0xe1,0x12,0xcf,0x95,0x49, -0x25,0x2e,0x8f,0x74,0x9, 0xac,0xbf,0x12,0x97,0x3c,0x12,0x20,0x54,0x2d,0xf3,0xe5, -0x25,0x7e,0x91,0x24,0x7e,0xa0,0x9, 0xac,0x9a,0x49,0x14,0x2e,0x8f,0x7e,0x50,0x9, -0xac,0x5f,0x49,0x32,0x1a,0xdf,0x9d,0x31,0x49,0x14,0x2e,0x91,0x49,0x22,0x1a,0xe1, -0x9d,0x21,0x12,0xa4,0x1, 0xbe,0xf4,0x9, 0x60,0x38,0x73,0xa, 0x3c,0x9, 0x53,0x2f, -0x80,0xbe,0x50,0x0, 0x28,0x1a,0x74,0x2, 0xac,0xbc,0x59,0xf5,0x2f,0x6c,0xa, 0x3c, -0x2e,0x34,0x2f,0x80,0x7c,0xb5,0x14,0x7a,0x39,0xb0,0x4c,0xdd,0x78,0x2, 0x1, 0xdb, -0x74,0x2, 0xac,0xbc,0x49,0x45,0x2f,0x6c,0xbe,0x44,0x0, 0xc8,0x28,0x8, 0x7d,0x34, -0x2d,0x3d,0xbd,0x3f,0x40,0x2d,0xbe,0xd0,0x1, 0x68,0x28,0x31,0x9, 0x40,0x6, 0x7e, -0xe4,0x0, 0x96,0x80,0x4, 0x7e,0xe4,0x1, 0x2c,0xbd,0x4e,0x28,0x6, 0xbd,0xef,0x50, -0x2, 0x80,0x7c,0x7d,0x34,0x2e,0x34,0x0, 0xc8,0xbd,0x3f,0x50,0x6, 0xbd,0x4e,0x28, -0x2, 0x80,0x6c,0x7e,0x73,0x16,0xc0,0xbe,0x70,0x0, 0x28,0x2, 0x1, 0xdb,0xbe,0xf4, -0x3, 0x20,0x38,0xb, 0xbe,0xd0,0x1, 0x78,0x52,0xbe,0xf4,0x1, 0x90,0x28,0x4c,0xe5, -0x25,0xa, 0x3b,0x9, 0xb3,0x1b,0xed,0x70,0x4, 0x74,0x3, 0x80,0x2, 0x74,0x1, 0x19, -0xb3,0x1b,0xed,0x74,0x3, 0xa, 0x3c,0x19,0xb3,0x1b,0xf7,0xbe,0xe0,0x0, 0x28,0x5b, -0x1b,0xe0,0x7e,0x70,0x9, 0xac,0x7f,0x2e,0x34,0x1a,0xdf,0x7e,0x14,0x2, 0x8f,0x74, -0x9, 0x12,0x1e,0x1d,0x12,0x8f,0x6f,0xac,0x3f,0x12,0x8f,0xc8,0x7e,0x34,0x2, 0x8f, -0x12,0x8f,0xc3,0x1b,0xf0,0x74,0x2, 0xac,0xbc,0x80,0x4, 0x74,0x2, 0xac,0xbc,0x59, -0xf5,0x2f,0x6c,0x80,0x26,0x5, 0x24,0xe5,0x24,0xbe,0xb0,0xa, 0x50,0x3, 0x2, 0x9f, -0x7e,0x80,0x18,0x6d,0x33,0x7e,0x51,0x25,0x74,0x2, 0xac,0x5b,0x11,0xf0,0x7e,0x61, -0x25,0x74,0x9, 0xac,0xb6,0x11,0xf8,0x19,0xbc,0x2f,0x80,0xb, 0xf0,0xbc,0xef,0x28, -0x3, 0x2, 0x9f,0x57,0xe4,0x7a,0xb3,0x16,0xc0,0x7a,0xe3,0x1c,0x47,0xda,0x3b,0x22, -0x59,0x32,0x2f,0x6c,0x7e,0x70,0xff,0x22,0x19,0x75,0x2e,0x93,0x6d,0x33,0x59,0x32, -0x2f,0x57,0x59,0x32,0x2f,0x43,0x74,0x2, 0x22,0x7e,0x37,0x2e,0x62,0xbe,0x34,0x0, -0x14,0x22,0x7e,0x73,0x1c,0x48,0xbe,0x73,0x1c,0x47,0x78,0x11,0x7e,0x73,0x1c,0x47, -0xbe,0x70,0x1, 0x40,0x8, 0x31,0x9, 0x38,0xe, 0xb, 0x34,0x80,0x6, 0x7e,0x37,0x2e, -0x62,0x1e,0x34,0x7a,0x37,0x2e,0x62,0x7e,0xb3,0x1c,0x47,0x70,0x6, 0x6d,0x33,0x7a, -0x37,0x2e,0x62,0x7e,0x37,0x2e,0x62,0x22,0x12,0x2b,0x8a,0x7a,0xb3,0x1c,0x51,0x22, -0xca,0xf8,0x7c,0x27,0x7c,0x3b,0xa5,0xbb,0x0, 0x15,0xbe,0x20,0x0, 0x28,0xc, 0x12, -0x5f,0xeb,0xe4,0x7a,0xb3,0x1c,0x4e,0x7a,0xb3,0x1c,0x4f,0x31,0xbb,0x80,0x3e,0xa5, -0xba,0x0, 0x1a,0x6c,0xff,0x7e,0x20,0xff,0x74,0x9, 0xac,0xbf,0x19,0x25,0x1b,0x97, -0xb, 0xf0,0xbe,0xf0,0xa, 0x78,0xf1,0x74,0x1, 0x7a,0xb3,0x1c,0x4b,0x6c,0xff,0x80, -0x18,0x7e,0x50,0x9, 0xac,0x5f,0x2e,0x24,0x1a,0xdf,0x31,0xb0,0x7e,0x50,0x9, 0xac, -0x5f,0x2e,0x24,0x1a,0xe1,0x31,0xb0,0xb, 0xf0,0xbc,0x3f,0x38,0xe4,0xda,0xf8,0x22, -0xb, 0x28,0x30,0x3e,0x34,0x3e,0x34,0x1b,0x28,0x30,0x22,0x7e,0x8, 0x2e,0xe9,0x7e, -0x34,0x0, 0x14,0xe4,0x12,0x20,0x12,0x7e,0x8, 0x2e,0x6e,0x31,0xd8,0x7e,0x8, 0x2e, -0x4e,0x7e,0x34,0x0, 0x14,0x2, 0x20,0x12,0x7e,0x34,0x0, 0x14,0x2, 0x20,0x12,0xca, -0x79,0x7c,0xfb,0x6c,0x11,0x7e,0x0, 0xff,0x74,0x9, 0xac,0xb1,0x19,0x5, 0x2, 0x93, -0x7e,0x44,0x7f,0xff,0x74,0x9, 0xac,0xb1,0x59,0x45,0x2, 0x8f,0x74,0x9, 0xac,0xb1, -0x59,0x45,0x2, 0x91,0xb, 0x10,0xa5,0xb9,0xa, 0xdb,0xe4,0x6c,0x77,0x7c,0x6f,0x51, -0x70,0x7c,0x7f,0x7e,0x60,0xa, 0x51,0x70,0x7c,0x1b,0x6c,0x0, 0x6c,0xee,0x80,0x16, -0x74,0x9, 0xac,0xbe,0x9, 0x65,0x2, 0x93,0x74,0x9, 0xac,0xb0,0x9, 0x75,0x1a,0xe3, -0xbc,0x76,0x68,0x6, 0xb, 0xe0,0xbc,0x1e,0x38,0xe6,0xbc,0x1e,0x78,0x15,0x7e,0x70, -0x9, 0xac,0x70,0x12,0x8f,0x74,0xac,0x31,0x2e,0x14,0x2, 0x8f,0x74,0x9, 0x12,0x1e, -0x1d,0xb, 0x10,0xb, 0x0, 0xbe,0x0, 0xa, 0x40,0xc2,0x7e,0x34,0x0, 0x5a,0xca,0x39, -0x7e,0x18,0x2, 0x8f,0x7e,0x8, 0x1b,0x93,0x12,0x1f,0xed,0x1b,0xfd,0xda,0x79,0x22, -0x7e,0x8, 0x2, 0x8f,0xca,0xd8,0xca,0x79,0x7f,0x70,0x7c,0xe6,0x7c,0xd7,0x7c,0xfb, -0x6c,0x77,0x7a,0xd1,0x24,0x80,0x7b,0x7e,0x50,0x9, 0xac,0x57,0x9, 0x62,0x1b,0x97, -0x7a,0x61,0x25,0x7e,0x31,0x24,0x74,0x9, 0xac,0xb3,0x9, 0x35,0x1a,0xe3,0xbe,0x31, -0x25,0x78,0x5d,0xe5,0x25,0xbe,0xb0,0xff,0x68,0x56,0x71,0x17,0x39,0x60,0x0, 0x4, -0xe5,0x25,0xa, 0x2b,0x9, 0xb2,0x1b,0xed,0x70,0xc, 0x71,0x20,0x7d,0xd5,0x2e,0xd4, -0x1a,0xdf,0x6d,0xcc,0x80,0xc, 0x74,0x9, 0xac,0xb7,0x7d,0xd5,0x2e,0xd4,0x1b,0x93, -0x6d,0xcc,0xb, 0x6a,0x40,0x71,0x17,0x1b,0xa, 0x40,0x69,0x46,0x0, 0x2, 0x71,0x17, -0x79,0x40,0x0, 0x2, 0x71,0x20,0x9, 0x65,0x1a,0xe4,0x71,0x17,0x39,0x60,0x0, 0x5, -0x71,0x20,0x9, 0x65,0x1a,0xe5,0x71,0x17,0x39,0x60,0x0, 0x6, 0xb, 0xf0,0x80,0x7, -0x5, 0x24,0xbe,0xe1,0x24,0x38,0x80,0xb, 0x70,0xbe,0x70,0xa, 0x50,0x2, 0x41,0x82, -0x7c,0xbf,0xda,0x79,0xda,0xd8,0x22,0x74,0x9, 0xac,0xbf,0x7f,0x7, 0x2d,0x15,0x22, -0x7e,0x61,0x24,0x74,0x9, 0xac,0xb6,0x22,0x6c,0x77,0x74,0x9, 0xac,0xb7,0x49,0x25, -0x1b,0x93,0x1e,0x24,0x1e,0x24,0x59,0x25,0x1a,0xdf,0x74,0x9, 0xac,0xb7,0x49,0x25, -0x1b,0x95,0x1e,0x24,0x1e,0x24,0x59,0x25,0x1a,0xe1,0x74,0x9, 0xac,0xb7,0x9, 0x65, -0x1b,0x97,0x19,0x65,0x1a,0xe3,0x74,0x9, 0xac,0xb7,0x9, 0x65,0x1b,0x98,0x19,0x65, -0x1a,0xe4,0x74,0x9, 0xac,0xb7,0x9, 0x65,0x1b,0x99,0x19,0x65,0x1a,0xe5,0xb, 0x70, -0xbe,0x70,0xa, 0x40,0xb5,0x22,0x7d,0x43,0x7e,0x34,0x15,0x7c,0x7a,0x37,0x2, 0x91, -0x7e,0x34,0x15,0xa4,0x7a,0x37,0x2, 0x93,0x7e,0x34,0x15,0xcc,0x7a,0x37,0x2, 0x95, -0x74,0x1, 0x7a,0xb3,0x2, 0x8f,0x7a,0xb3,0x2, 0x90,0x7a,0x47,0x15,0x7c,0x7a,0x27, -0x15,0x7e,0x7a,0x17,0x15,0xa4,0x7a,0x7, 0x15,0xa6,0x7e,0x8, 0x2, 0x8f,0x12,0x7, -0xa8,0x7e,0x37,0x15,0xcc,0x22,0x7e,0xa3,0x1c,0x47,0xbe,0xa0,0x0, 0x28,0xe, 0x7e, -0xb3,0x1e,0x84,0xbe,0xb0,0xf, 0x50,0x5, 0x4, 0x7a,0xb3,0x1e,0x84,0x7e,0xb3,0x2e, -0x82,0xb4,0x2, 0x12,0xbe,0xa0,0x1, 0x28,0xd, 0x7e,0x73,0x1e,0x84,0xbe,0x70,0xf, -0x50,0x4, 0x74,0x1, 0x80,0x1, 0xe4,0x7a,0xb3,0x2e,0x8d,0x7e,0xb3,0x2e,0x82,0xb4, -0x2, 0xe, 0x7e,0x73,0x2e,0x8e,0xbe,0x73,0x2e,0x8d,0x28,0x4, 0x7a,0x73,0x2e,0x8d, -0x22,0x7d,0x12,0x7d,0x3, 0x7c,0x5b,0x3e,0x4, 0x3e,0x4, 0x3e,0x14,0x3e,0x14,0x74, -0x2, 0xac,0xb5,0x49,0x45,0x2f,0x43,0x4d,0x44,0x78,0xb, 0x78,0x9, 0x59,0x5, 0x2f, -0x43,0x59,0x15,0x2f,0x57,0x22,0x2d,0x4, 0xe, 0x4, 0x59,0x5, 0x2f,0x43,0x49,0x35, -0x2f,0x57,0x2d,0x31,0xe, 0x34,0x59,0x35,0x2f,0x57,0x22,0x7e,0x8, 0x2e,0x82,0x7e, -0x34,0x0, 0xd, 0xe4,0x2, 0x20,0x12,0xca,0x3b,0x75,0x25,0x0, 0x6c,0xcc,0xe4,0x7a, -0xb3,0x3, 0x7, 0x7e,0xe3,0x1a,0xb5,0xa, 0xce,0x3e,0xc4,0xca,0xc9,0x7e,0x18,0x18, -0x95,0x7e,0x8, 0x2, 0x8f,0x12,0x1f,0xed,0x1b,0xfd,0x75,0x24,0x0, 0x6c,0xdd,0xa1, -0xf, 0x7e,0x44,0x3, 0xff,0x7e,0xc0,0xff,0x6c,0xff,0x80,0x4a,0x74,0x2, 0xac,0xbf, -0x9, 0xb5,0x2, 0x8f,0xbe,0xb0,0xff,0x68,0x3b,0x7c,0xbf,0x12,0x4f,0xad,0x60,0x34, -0x74,0x2, 0xac,0xbf,0x9, 0x75,0x2, 0x90,0xa, 0x27,0x74,0x2, 0xac,0xbd,0x9, 0x75, -0x35,0x9b,0xd1,0xa6,0x7d,0xc3,0x74,0x2, 0xac,0xbf,0x9, 0x75,0x2, 0x8f,0xa, 0x27, -0x74,0x2, 0xac,0xbd,0x9, 0x75,0x35,0x9a,0xd1,0xa6,0x2d,0xc3,0xbd,0x4c,0x28,0x4, -0x7d,0x4c,0x7c,0xcf,0xb, 0xf0,0xbc,0xef,0x38,0xb2,0xbe,0xc0,0xff,0x68,0x3e,0x7e, -0x70,0x2, 0xac,0x7c,0x9, 0xb3,0x2, 0x8f,0x9, 0x73,0x2, 0x90,0x12,0x2b,0x76,0xbe, -0x37,0x1c,0xcc,0x48,0x28,0x7e,0x70,0x2, 0xac,0x7c,0x9, 0x53,0x2, 0x8f,0x7e,0xb3, -0x3, 0x7, 0x7e,0x40,0x2, 0xac,0xb4,0x19,0x55,0x2, 0xcb,0x9, 0x53,0x2, 0x90,0x19, -0x55,0x2, 0xcc,0x74,0xff,0x19,0xb3,0x2, 0x8f,0x5, 0x24,0xd1,0x92,0xb, 0xd0,0x7e, -0x73,0x35,0x99,0xbc,0x7d,0x28,0x2, 0x81,0x71,0x7e,0xd1,0x24,0xa1,0xa3,0x7e,0x90, -0xff,0x12,0x6e,0xe8,0x7d,0xd3,0x6c,0xff,0x80,0x4d,0x7c,0xbf,0x12,0x4f,0xad,0x60, -0x44,0xd1,0x9c,0xbe,0xb0,0xff,0x68,0x3d,0x9, 0x73,0x2, 0x90,0xd1,0xad,0x7f,0x71, -0xb, 0x7a,0xc0,0xbe,0xc4,0x0, 0x0, 0x58,0x5, 0x6d,0xcc,0x1b,0x7a,0xc0,0x7e,0xb3, -0x1c,0xdb,0x60,0xe, 0x7e,0xc7,0x1a,0xbb,0xbe,0xc4,0x1, 0x90,0x58,0x4, 0x7e,0xd4, -0x0, 0x3c,0xb, 0x7a,0xc0,0xbd,0xcd,0x8, 0xc, 0xd1,0x9c,0xf5,0x25,0x9, 0xc3,0x2, -0x90,0x7d,0xdc,0x7c,0x9f,0xb, 0xf0,0xbc,0xef,0x38,0xaf,0xbe,0x90,0xff,0x68,0x21, -0x7e,0x81,0x25,0x7e,0xb3,0x3, 0x7, 0x7e,0x70,0x2, 0xac,0xb7,0x19,0x85,0x2, 0xcb, -0x19,0xc5,0x2, 0xcc,0x7e,0x80,0xff,0x74,0x2, 0xac,0xb9,0x19,0x85,0x2, 0x8f,0xd1, -0x92,0xb, 0xd0,0xbe,0xd0,0xa, 0x50,0x2, 0xa1,0x1e,0x7e,0xb3,0x38,0xa2,0x7e,0x70, -0x2, 0xac,0xb7,0xca,0x59,0x7e,0x18,0x2, 0xcb,0x7e,0x8, 0x2, 0x8f,0x12,0x1f,0xed, -0x1b,0xfd,0x7e,0xe3,0x3, 0x7, 0x7e,0x8, 0x35,0x9a,0x7e,0x34,0x0, 0x14,0x74,0xff, -0x12,0x20,0x12,0xbe,0xe0,0x0, 0x38,0x2, 0xc1,0x78,0x6c,0xdd,0x80,0x4e,0x6c,0xff, -0x80,0x43,0x7e,0x90,0x2, 0xac,0x9d,0x9, 0x64,0x2, 0x8f,0x74,0x2, 0xac,0xbf,0x9, -0x75,0x18,0x95,0xbc,0x76,0x78,0x2c,0x9, 0x64,0x2, 0x90,0x9, 0x75,0x18,0x96,0xbc, -0x76,0x78,0x20,0x7e,0x34,0x0, 0x5, 0xca,0x39,0xac,0x7f,0x2e,0x34,0x18,0xd1,0x6d, -0x22,0x7e,0x30,0x5, 0xac,0x3d,0x2e,0x14,0x3, 0x8, 0x6d,0x0, 0x12,0x1f,0xed,0x1b, -0xfd,0x80,0x7, 0xb, 0xf0,0x12,0x4d,0xcc,0x38,0xb8,0xb, 0xd0,0xbc,0xed,0x38,0xae, -0x74,0x5, 0xac,0xbe,0xca,0x59,0x7e,0x18,0x3, 0x8, 0x7e,0x8, 0x18,0xd1,0x12,0x1f, -0xed,0x1b,0xfd,0xa, 0x3e,0x3e,0x34,0xca,0x39,0x7e,0x18,0x2, 0x8f,0x7e,0x8, 0x18, -0x95,0x12,0x1f,0xed,0x1b,0xfd,0xa, 0x3e,0x3e,0x34,0xca,0x39,0x7e,0x18,0x2, 0x8f, -0x7e,0x8, 0x35,0x9a,0x12,0x1f,0xed,0x1b,0xfd,0x6c,0xdd,0x80,0x7, 0x7c,0xbd,0x12, -0x28,0xda,0xb, 0xd0,0xbc,0xed,0x38,0xf5,0x7a,0xe3,0x35,0x99,0x7a,0xe3,0x1a,0xb5, -0x7e,0x73,0x1a,0xb5,0xbe,0x70,0xa, 0x28,0x6, 0x74,0xa, 0x7a,0xb3,0x1a,0xb5,0xda, -0x3b,0x22,0x7e,0xb3,0x3, 0x7, 0x4, 0x7a,0xb3,0x3, 0x7, 0x22,0x7e,0x70,0x2, 0xac, -0x7f,0x9, 0xb3,0x2, 0x8f,0x22,0xa, 0x37,0x9d,0x32,0x2, 0x20,0x54,0x7c,0xa7,0x7c, -0x1b,0x7e,0x3, 0x1c,0xe0,0xac,0x10,0x3e,0x4, 0x7e,0x30,0x2, 0xac,0x3a,0x2d,0x10, -0x7e,0x1f,0x13,0x68,0x2d,0x31,0x22,0xca,0xf8,0x7e,0x20,0x64,0x7e,0x10,0x64,0x6c, -0x0, 0x80,0x42,0xa, 0x40,0xb, 0x44,0x80,0x35,0x12,0x2f,0xbd,0xa, 0x28,0x74,0x2, -0xac,0xb0,0x9, 0x85,0x18,0x95,0xa, 0x38,0x9d,0x32,0x12,0x20,0x54,0x7c,0x87,0x12, -0x2f,0xc6,0xa, 0x27,0x74,0x2, 0xac,0xb0,0x9, 0x75,0x18,0x96,0xd1,0xa6,0x7c,0xf7, -0xbc,0x28,0x28,0x2, 0x7c,0x28,0xbc,0x1f,0x28,0x2, 0x7c,0x1f,0xb, 0x90,0x12,0x4f, -0xca,0x38,0xc6,0xb, 0x0, 0x7e,0x83,0x1a,0xb5,0xbc,0x80,0x38,0xb6,0xa5,0xba,0x64, -0x2, 0x6c,0x22,0xa5,0xb9,0x64,0x2, 0x6c,0x11,0xbc,0x12,0x28,0x4, 0x7c,0x31,0x80, -0x2, 0x7c,0x32,0x7c,0xb3,0xda,0xf8,0x22,0xe4,0x7a,0xb3,0x33,0x7d,0x7e,0xb3,0x1a, -0xb5,0x60,0x6, 0x7e,0xb3,0x33,0xf6,0x60,0x5, 0xe4,0x7a,0xb3,0x33,0xf8,0x22,0x7e, -0xa0,0x1, 0x7e,0x37,0x1c,0xc1,0x7e,0xb3,0x1a,0xb5,0xbe,0xb0,0x0, 0x28,0x35,0x6d, -0x22,0x9d,0x23,0xbe,0x27,0x9, 0x0, 0x58,0x2b,0x12,0x6f,0x16,0xbe,0x37,0x9, 0x2, -0x8, 0x22,0xe4,0x7a,0xb3,0x1a,0xb5,0x7e,0xb3,0x1c,0x48,0x70,0x17,0x7e,0xb3,0x35, -0x8, 0xb4,0x1, 0x10,0x6c,0xaa,0x5, 0x68,0xe5,0x68,0xbe,0xb0,0x10,0x28,0x5, 0xd2, -0x11,0x75,0x68,0x0, 0x4c,0xaa,0x68,0x3, 0x75,0x68,0x0, 0x22,0xf1,0xc3,0x7e,0xf, -0x13,0x68,0x7e,0x18,0x32,0x64,0x7e,0xb3,0x38,0x50,0xf1,0xea,0xf1,0xc3,0x7e,0xf, -0x13,0x68,0x7e,0x18,0x32,0xaa,0x7e,0xb3,0x38,0x50,0xf1,0xd9,0x9f,0x11,0x7a,0x1f, -0x32,0x60,0x22,0x7e,0xb3,0x38,0x51,0xf5,0x24,0x6d,0x33,0x7a,0x35,0x25,0x7e,0x24, -0x0, 0x1, 0x7a,0x25,0x27,0x7a,0x35,0x29,0x22,0xf1,0xfb,0x4e,0x70,0x10,0x12,0xa8, -0x66,0x4e,0x60,0x80,0x1b,0xa, 0x30,0x2, 0x87,0x4a,0xf1,0xfb,0x4e,0x70,0x20,0x12, -0xa8,0x66,0x4e,0x60,0x80,0x1b,0xa, 0x30,0x2, 0x87,0x4a,0x7f,0x71,0xa9,0xd6,0xcb, -0x7d,0x31,0x7e,0xf, 0x36,0x51,0x79,0x30,0x0, 0x4, 0x7d,0x3f,0x7e,0xf, 0x36,0x51, -0x79,0x30,0x0, 0x8, 0x7c,0x4b,0x6c,0x55,0xe5,0x24,0xa, 0x3b,0x4d,0x32,0x7e,0xf, -0x36,0x51,0x79,0x30,0x0, 0xc, 0x7e,0x25,0x29,0x7c,0x45,0x6c,0x55,0x7e,0xf, 0x36, -0x51,0xb, 0xa, 0x30,0x4d,0x32,0x1b,0xa, 0x30,0x7e,0x35,0x27,0x7d,0x23,0x7c,0x45, -0x6c,0x55,0x3e,0x24,0x7e,0xf, 0x36,0x51,0xb, 0xa, 0x30,0x4d,0x32,0x1b,0xa, 0x30, -0x7e,0x35,0x25,0x7d,0x23,0x7c,0x45,0x6c,0x55,0x3e,0x24,0x3e,0x24,0x7e,0xf, 0x36, -0x51,0xb, 0xa, 0x30,0x4d,0x32,0x1b,0xa, 0x30,0x7e,0xf, 0x36,0x51,0xb, 0xa, 0x30, -0x22,0x7f,0x71,0xa9,0xd6,0xcb,0x7d,0x31,0x11,0xbc,0x79,0x30,0x0, 0x6, 0x7e,0x1d, -0x52,0x7e,0xf, 0x36,0x51,0x79,0x30,0x0, 0x8, 0x7c,0x4b,0x6c,0x55,0xe5,0x57,0xa, -0x3b,0x4d,0x32,0x7e,0xf, 0x36,0x51,0x79,0x30,0x0, 0xc, 0x7e,0x25,0x5a,0x7c,0x45, -0x6c,0x55,0x11,0x69,0x4d,0x32,0x1b,0xa, 0x30,0x7e,0x35,0x58,0x11,0x53,0x4e,0x70, -0x30,0x11,0x66,0x4e,0x60,0x80,0x1b,0xa, 0x30,0x2, 0x87,0x4a,0x7e,0xf, 0x36,0x51, -0x79,0x30,0x0, 0x4, 0x7d,0x3f,0x7e,0xf, 0x36,0x51,0x22,0x11,0xfe,0xbe,0x34,0x1, -0x90,0x28,0xc, 0x7e,0xb3,0x32,0x5f,0xbe,0xb0,0x6, 0x50,0x11,0x4, 0x80,0xa, 0x7e, -0xb3,0x32,0x5f,0xbe,0xb0,0x0, 0x28,0x5, 0x14,0x7a,0xb3,0x32,0x5f,0x7e,0xb3,0x32, -0x5f,0xbe,0xb0,0x3, 0x40,0x3, 0xd2,0x12,0x22,0x70,0x2, 0xc2,0x12,0x22,0xca,0xf8, -0x6d,0x44,0x7e,0x73,0x1c,0xe6,0xa, 0x17,0x7e,0x73,0x1c,0xe5,0xa, 0x7, 0x2d,0x1, -0x7c,0x1, 0x74,0x1, 0x12,0x0, 0xe, 0x7e,0x30,0x2, 0xac,0x30,0x2e,0x14,0x6, 0x84, -0x7e,0x10,0x4, 0xac,0x1, 0x2e,0x4, 0x6, 0x84,0x6c,0xff,0x80,0x40,0x7e,0x70,0x2, -0xac,0x7f,0x7d,0x23,0x2d,0x20,0xb, 0x28,0x20,0x2d,0x31,0xb, 0x38,0x30,0x12,0x4f, -0xe1,0xbd,0x4f,0x50,0x2, 0x7d,0x4f,0x74,0x2, 0xac,0xbf,0x7d,0xe5,0x2d,0xe1,0xb, -0xe8,0xe0,0xbe,0xe4,0x7f,0xff,0x78,0x4, 0x7e,0x44,0x7f,0xff,0x2d,0x50,0xb, 0x58, -0x50,0xbe,0x54,0x7f,0xff,0x78,0x4, 0x7e,0x44,0x7f,0xff,0xb, 0xf0,0x7e,0x73,0x1c, -0xe6,0xbc,0x7f,0x38,0xb8,0x7d,0x34,0xda,0xf8,0x22,0x7e,0xa0,0x1, 0x7e,0x37,0x9, -0x0, 0xbe,0x34,0xfd,0xa8,0x58,0x12,0x7e,0xb3,0x1a,0xdd,0x60,0x7, 0xe4,0x7a,0xb3, -0x1a,0xde,0x80,0x29,0x7e,0xa0,0x5, 0x80,0x24,0xbe,0x34,0xfe,0xc, 0x58,0x5, 0x7e, -0xa0,0x4, 0x80,0x19,0xbe,0x34,0xfe,0x70,0x58,0x5, 0x7e,0xa0,0x3, 0x80,0xe, 0xbe, -0x34,0xfe,0xd4,0x58,0x5, 0x7e,0xa0,0x2, 0x80,0x3, 0x7e,0xa0,0x1, 0x7c,0xba,0x22, -0xca,0xf8,0x7e,0x90,0x1, 0x7e,0xf4,0x0, 0x1, 0x71,0xa6,0xe4,0x7a,0xb3,0x1a,0xdd, -0x12,0x36,0x57,0x12,0x5f,0xdc,0x40,0x17,0x71,0x9b,0x38,0xc, 0x7e,0xf7,0x9, 0x6, -0xbe,0xf4,0x0, 0xc8,0x58,0x2, 0x61,0x98,0xe4,0x7a,0xb3,0x1a,0xde,0x61,0x98,0x7e, -0xc4,0xfd,0xa8,0x7e,0xd4,0xfe,0xd4,0x7e,0xb3,0x1c,0xda,0xb4,0x1, 0x6, 0x7e,0xe4, -0x0, 0xc8,0x80,0x4, 0x7e,0xe4,0x1, 0x90,0x6c,0xff,0x6c,0x88,0x80,0x2e,0x74,0x2, -0xac,0xb8,0x9, 0x75,0x18,0x95,0x9, 0x65,0x18,0x96,0x91,0x44,0xbe,0x24,0x0, 0xc8, -0x48,0x18,0xa, 0x57,0x7e,0x53,0x1c,0xe0,0xa, 0x25,0x2d,0x25,0x3e,0x24,0x49,0x22, -0x4, 0xd4,0xbe,0x24,0x0, 0xc8,0x48,0x2, 0xb, 0xf0,0xb, 0x80,0x7e,0x53,0x1a,0xb5, -0xbc,0x58,0x38,0xca,0x7e,0xf7,0x9, 0x6, 0xbd,0xfc,0x58,0x1a,0x7e,0xc7,0x9, 0x4, -0xbd,0xcd,0x58,0x12,0x6d,0xcc,0x9e,0xc7,0x1c,0xcc,0xbe,0xc7,0x1a,0xbf,0x8, 0x32, -0x71,0xa3,0x60,0x2e,0x80,0x2a,0x7e,0xc7,0x1c,0xcc,0x3e,0xc4,0x6e,0xc4,0xff,0xff, -0xb, 0xc4,0xbe,0xc7,0x1a,0xbf,0x8, 0x1a,0xbe,0xf4,0xff,0x38,0x58,0x14,0x6d,0xff, -0x9d,0xfe,0xbe,0xf7,0x9, 0x4, 0x8, 0xa, 0x4c,0xff,0x78,0x6, 0x71,0xa3,0x60,0x2, -0x71,0xbd,0x91,0xa6,0xe4,0x33,0x78,0x5, 0xe4,0x7a,0xb3,0x1a,0xd9,0x12,0x6e,0xc1, -0x68,0x6, 0x7e,0xb3,0x36,0x49,0x60,0xd, 0x7e,0xb3,0x36,0x4b,0x70,0x7, 0xe4,0x7a, -0xb3,0x1a,0xde,0x61,0x3a,0x71,0x9b,0x28,0x5, 0xe4,0x7a,0xb3,0x1a,0xde,0x30,0x10, -0x5, 0xe4,0x7a,0xb3,0x1a,0xde,0x71,0xf6,0x50,0x7, 0x12,0x36,0x57,0x31,0x7a,0x7c, -0x9b,0x7e,0xb3,0x18,0x1f,0x70,0x3b,0x7e,0xb3,0x18,0x20,0x70,0x35,0x71,0x9b,0x28, -0x31,0x7e,0xb3,0x2, 0x8e,0xbe,0xb0,0x32,0x50,0x5, 0x4, 0x7a,0xb3,0x2, 0x8e,0x7e, -0x83,0x2, 0x8e,0xbe,0x80,0x5, 0x40,0x1f,0x7e,0x90,0x3, 0x12,0x36,0x57,0x7e,0xf7, -0x9, 0xe, 0xbe,0xf4,0xfc,0xe0,0x58,0xf, 0x7e,0xb3,0x1a,0xdb,0x60,0x9, 0x71,0xbd, -0x80,0x5, 0xe4,0x7a,0xb3,0x2, 0x8e,0x7e,0xf7,0x9, 0x2, 0xbe,0xf4,0x5, 0xdc,0x8, -0x15,0x71,0x9b,0x28,0x11,0x7e,0xf7,0x1a,0xbf,0xbe,0xf4,0xff,0x38,0x8, 0x7, 0x71, -0xaf,0xe4,0x7a,0xb3,0x1a,0xde,0xa, 0xf9,0x71,0xa6,0x12,0x0, 0x6e,0x50,0xc, 0xe4, -0x7a,0xb3,0x1a,0xde,0x12,0x4f,0xd9,0x28,0x2, 0x71,0xaf,0x7e,0xf7,0x1a,0xbb,0xbe, -0xf4,0x0, 0xc8,0x8, 0x14,0x7e,0xf7,0x1a,0xbf,0xbe,0xf4,0xff,0x9c,0x8, 0xa, 0x12, -0x0, 0x6e,0x50,0x5, 0xe4,0x7a,0xb3,0x1a,0xde,0x12,0x4d,0xd3,0xb4,0x1, 0x5, 0xe4, -0x7a,0xb3,0x1a,0xde,0x91,0x4d,0x7e,0xb3,0x0, 0x6c,0xbe,0xb0,0x0, 0x28,0x19,0x14, -0x7a,0xb3,0x0, 0x6c,0x70,0x12,0xe4,0x7a,0xb3,0x1a,0xde,0x74,0x1, 0x7a,0xb3,0x1a, -0xdd,0xe4,0x71,0xe6,0x68,0x2, 0x71,0xdc,0xda,0xf8,0x22,0x7e,0x83,0x1a,0xb5,0xbe, -0x80,0x0, 0x22,0x74,0x1, 0x22,0x7a,0xf7,0x1a,0xd2,0x7a,0xf7,0x1a,0xd4,0x22,0xe4, -0x7a,0xb3,0x0, 0x6c,0x7a,0xb3,0x1a,0xdd,0x74,0x2, 0x2, 0x27,0x4, 0x7e,0x73,0x0, -0x6c,0xbe,0x70,0x0, 0x38,0x15,0x74,0x2, 0x7a,0xb3,0x0, 0x6c,0x74,0x1, 0x7a,0xb3, -0x1a,0xdd,0x12,0x27,0x3, 0x71,0xe6,0x68,0x2, 0x71,0xdc,0x22,0xe4,0x7a,0xb3,0x1a, -0xb5,0x7a,0xb3,0x18,0x1e,0x22,0x7a,0xb3,0x16,0xbf,0x7a,0xb3,0x16,0xbe,0x7e,0xb3, -0x32,0xf4,0xbe,0xb0,0x1, 0x22,0x7e,0x53,0x1c,0xe1,0x7e,0x73,0x1c,0xe2,0x7e,0x60, -0x1, 0x80,0x1a,0xa, 0x6, 0x7e,0x43,0x1c,0xe0,0xa, 0x14,0x2d,0x10,0x3e,0x14,0x49, -0x11,0x4, 0xd4,0xbe,0x14,0xff,0x4c,0x58,0x2, 0xd3,0x22,0xb, 0x60,0xa, 0x5, 0x1b, -0x4, 0xa, 0x16,0xbd,0x10,0x48,0xdc,0x7e,0x60,0x2, 0x80,0xc, 0x91,0x44,0xbe,0x24, -0xff,0x4c,0x58,0x2, 0xd3,0x22,0xb, 0x60,0xa, 0x17,0x1b,0x15,0xa, 0x26,0xbd,0x21, -0x48,0xea,0xc3,0x22,0x74,0x2, 0xac,0xb6,0x49,0x25,0x4, 0xd4,0x22,0x7e,0x60,0x4, -0x7e,0x27,0x36,0x31,0xbe,0x24,0x3, 0xe8,0x28,0x3, 0x7e,0x60,0x8, 0x7e,0xb3,0x1a, -0xdd,0xb4,0x1, 0x19,0x7e,0x73,0x0, 0x6d,0xbc,0x76,0x50,0xe, 0xe4,0x7a,0xb3,0x1a, -0xde,0x71,0xaf,0x7e,0xb3,0x0, 0x6d,0x4, 0x80,0x4, 0xe4,0x80,0x1, 0xe4,0x7a,0xb3, -0x0, 0x6d,0x7e,0xb3,0x1a,0xde,0xb4,0x1, 0x17,0x7e,0xa3,0x0, 0x6e,0xbe,0xa0,0x5, -0x50,0xa, 0xe4,0x7a,0xb3,0x1a,0xde,0x7c,0xba,0x4, 0x80,0x5, 0x74,0x5, 0x80,0x1, -0xe4,0x7a,0xb3,0x0, 0x6e,0x22,0xd2,0x3, 0x6c,0x77,0x6c,0x55,0x80,0x14,0x7c,0x45, -0x74,0x2, 0xac,0xb4,0x49,0x15,0x5, 0x3e,0xbe,0x14,0xfe,0x70,0x58,0x2, 0xb, 0x70, -0xb, 0x50,0x7e,0x63,0x1c,0xe0,0xbc,0x65,0x38,0xe4,0xa, 0x26,0x1e,0x24,0x1e,0x24, -0xa, 0x37,0xbd,0x32,0x8, 0x2, 0xc2,0x3, 0xa2,0x3, 0x22,0x6c,0x77,0x80,0x25,0x74, -0x2, 0xac,0xb7,0x49,0x25,0x5, 0xa8,0x49,0x45,0x4, 0x0, 0x2d,0x42,0x59,0x45,0x5, -0xa8,0x30,0x1, 0xe, 0x49,0x45,0x4, 0x6a,0x49,0x25,0x6, 0x12,0x2d,0x24,0x59,0x25, -0x6, 0x12,0xb, 0x70,0x7e,0x63,0x1c,0xe6,0xa, 0x6, 0x7e,0x63,0x1c,0xe5,0xa, 0x16, -0x2d,0x10,0xa, 0x27,0xbd,0x21,0x48,0xc7,0x22,0x7d,0x23,0xbe,0x24,0x1, 0xf4,0x28, -0xd, 0x7e,0x73,0x34,0x73,0xbe,0x70,0x8, 0x50,0x3a,0x74,0x8, 0x80,0x32,0xbe,0x24, -0x1, 0x90,0x28,0xd, 0x7e,0x73,0x34,0x73,0xbe,0x70,0x6, 0x50,0x27,0x74,0x6, 0x80, -0x1f,0xbe,0x24,0x1, 0x2c,0x28,0x8, 0xb1,0x82,0x50,0x19,0x74,0x4, 0x80,0x11,0xbe, -0x24,0x0, 0xc8,0x28,0xf, 0x7e,0x73,0x34,0x73,0xbe,0x70,0x2, 0x50,0x6, 0x74,0x2, -0x7a,0xb3,0x34,0x73,0x7e,0xb3,0x34,0x73,0xbe,0xb0,0x0, 0x28,0x14,0x14,0x7a,0xb3, -0x34,0x73,0x74,0x1, 0x7a,0xb3,0x16,0xc0,0xb1,0x82,0x28,0x5, 0xe4,0x7a,0xb3,0x16, -0xbf,0x22,0x7e,0x73,0x34,0x73,0xbe,0x70,0x4, 0x22,0xca,0x79,0x7c,0x3b,0x7e,0x44, -0xff,0xff,0x6c,0x22,0x80,0x1a,0xb1,0xf1,0x68,0x14,0x74,0xc, 0xac,0xb2,0x49,0x5, -0x34,0x19,0x49,0x35,0x34,0x15,0xbd,0x30,0x50,0x4, 0x59,0x5, 0x34,0x15,0xb, 0x20, -0xbc,0x32,0x50,0xe2,0x6c,0xff,0x6c,0x22,0x80,0x28,0xb1,0xf1,0x78,0x12,0xa, 0x2, -0xb, 0x4, 0x7c,0xe1,0xbc,0x3e,0x50,0x18,0xa, 0x33,0xb, 0x34,0x9c,0xe7,0x80,0x10, -0x74,0xc, 0xac,0xb2,0x49,0x5, 0x34,0x15,0xbd,0x4, 0x50,0x4, 0x7d,0x40,0x7c,0xf2, -0xb, 0x20,0xbc,0x32,0x50,0xd4,0x4d,0x44,0x78,0x2, 0x7c,0xfe,0x7c,0xbf,0xda,0x79, -0x22,0x74,0x5, 0xac,0xb2,0x9, 0x75,0x17,0xce,0xbe,0x73,0x1d,0x93,0x22,0xca,0xf8, -0x7e,0xf0,0xff,0x7e,0xb3,0x34,0x2, 0xb4,0x1, 0x8, 0x12,0x31,0xdf,0xe4,0x7a,0xb3, -0x34,0x2, 0x7e,0xb3,0x34,0x0, 0xb4,0x2, 0x2, 0x80,0x2, 0xc1,0xe9,0xf1,0x11,0x38, -0x10,0xf1,0x9, 0x38,0xc, 0xf1,0x1, 0x38,0x8, 0x7e,0xb3,0x16,0xbf,0x60,0x2, 0xc1, -0xe9,0x74,0x3, 0xb1,0x8a,0x7c,0x5b,0x7e,0xb3,0x33,0xff,0x4, 0x7a,0xb3,0x33,0xff, -0x74,0x3, 0xb1,0x8a,0x7c,0x4b,0xbe,0x40,0xff,0x68,0x28,0xbe,0x50,0xff,0x68,0x21, -0x7e,0x30,0xc, 0xac,0x35,0x49,0x41,0x34,0x15,0xbe,0x44,0x1, 0x90,0x28,0x14,0x74, -0xc, 0xac,0xb4,0x49,0x35,0x34,0x15,0x3e,0x34,0xbd,0x43,0x28,0x6, 0x7c,0x54,0x80, -0x2, 0x7c,0x54,0xa5,0xbd,0xff,0x11,0xe4,0x7a,0xb3,0x33,0xff,0x7a,0xb3,0x34,0x0, -0x7a,0xb3,0x34,0xc, 0x74,0xff,0x80,0x76,0x7e,0x43,0x33,0xff,0xbe,0x40,0x4, 0x38, -0xb, 0xbe,0x40,0x2, 0x28,0x53,0x7e,0xb3,0x16,0xbf,0x70,0x4d,0x74,0xc, 0xac,0xb5, -0x49,0x35,0x34,0x15,0xbe,0x34,0x1, 0x90,0x40,0x6, 0x7e,0xb3,0x16,0xbf,0x70,0x31, -0x7e,0x37,0x34,0x6, 0xbe,0x34,0x1, 0x2c,0x28,0x27,0x74,0x5, 0xac,0xb5,0x9, 0x45, -0x17,0xce,0xbe,0x43,0x1d,0x93,0x68,0x19,0x7c,0xf5,0xbe,0xf0,0x4, 0x50,0xc, 0x7e, -0xb3,0x1d,0x93,0x12,0x65,0xaa,0xbe,0xb0,0x4, 0x40,0x6, 0x74,0x1, 0x7a,0xb3,0x34, -0x2, 0xe4,0x7a,0xb3,0x34,0xc, 0x12,0x57,0xeb,0xbe,0xf0,0xff,0x68,0xe, 0xe4,0x7a, -0xb3,0x33,0xff,0x12,0x57,0xeb,0x6d,0x33,0x7a,0x37,0x34,0x6, 0x7c,0xbf,0xda,0xf8, -0x22,0x7e,0x73,0x18,0x90,0xbe,0x70,0x0, 0x22,0x7e,0x73,0x18,0x8f,0xbe,0x70,0x0, -0x22,0x7e,0x73,0x1a,0xc3,0xbe,0x70,0x0, 0x22,0xf1,0x6e,0xf1,0x77,0x12,0x8f,0x1e, -0x7d,0x13,0x2e,0x14,0x1c,0xec,0x6d,0x0, 0x9, 0xb3,0x1c,0xeb,0x7e,0x34,0x0, 0x2, -0x12,0x20,0x12,0x12,0x8f,0x1e,0x7d,0x13,0x2e,0x14,0x1d,0xa5,0x9, 0xb3,0x1d,0xa4, -0x7e,0x34,0x0, 0x2, 0xf1,0x64,0x2e,0x14,0x1c,0xee,0xf1,0x5b,0xe5,0x25,0xf1,0x64, -0x2e,0x14,0x1d,0xa7,0xf1,0x5b,0xe5,0x24,0x2, 0x20,0x12,0x7e,0x73,0x38,0x99,0xa, -0x37,0x1b,0x35,0x22,0x12,0x20,0x12,0x7e,0x73,0x38,0x50,0xa, 0x17,0x22,0x7e,0x8, -0x0, 0x25,0x7e,0x18,0x0, 0x24,0x22,0x7f,0x71,0x6c,0x77,0x6c,0x66,0x80,0xc, 0xa, -0x26,0x9, 0x52,0x1c,0xec,0xbc,0x57,0x68,0xa, 0xb, 0x60,0x7e,0x53,0x38,0x50,0xbc, -0x56,0x38,0xec,0x7e,0x53,0x38,0x50,0xbc,0x56,0x68,0x7, 0xb, 0x70,0xbe,0x70,0x23, -0x40,0xd9,0x7a,0xb, 0x70,0x74,0x6e,0x7a,0x7b,0xb0,0x22,0x7e,0x8, 0x34,0x11,0x12, -0x49,0x32,0x6c,0x77,0x7e,0x44,0xff,0xff,0x74,0xc, 0xac,0xb7,0x59,0x45,0x34,0x13, -0x59,0x45,0x34,0x1b,0xb, 0x70,0xbe,0x70,0x8, 0x40,0xe9,0x7e,0x8, 0x33,0xff,0x7e, -0x34,0x0, 0xd, 0xe4,0x2, 0x20,0x12,0xca,0xd8,0xca,0x79,0x7c,0xfb,0x7f,0x70,0x6c, -0xdd,0x6d,0xcc,0x7d,0x4c,0x7d,0xdc,0x9f,0x44,0x7f,0x14,0x6c,0xee,0x80,0xe, 0x12, -0xb0,0x7e,0xb, 0xa, 0x10,0x1a,0x2, 0x1a,0x0, 0x2f,0x10,0xb, 0xe0,0xbc,0xfe,0x38, -0xee,0xa, 0x1f,0x11,0x6a,0x7f,0x14,0x6c,0xee,0x80,0x15,0x11,0x7e,0xb, 0xa, 0xb0, -0xbd,0x4b,0x8, 0xa, 0x7d,0x1b,0x1a,0x2, 0x1a,0x0, 0x2f,0x10,0xb, 0xd0,0xb, 0xe0, -0xbc,0xfe,0x38,0xe7,0x7d,0x4c,0xbe,0xd0,0x0, 0x28,0x4, 0xa, 0x1d,0x11,0x6a,0x6c, -0xee,0x80,0x12,0x74,0x2, 0xac,0xbe,0x7f,0x17,0x2d,0x35,0xb, 0x1a,0x50,0x9d,0x54, -0x1b,0x1a,0x50,0xb, 0xe0,0xbc,0xfe,0x38,0xea,0x6c,0xee,0x80,0x12,0x11,0x72,0x12, -0x20,0x54,0xbd,0x3d,0x8, 0x7, 0x11,0x72,0x12,0x20,0x54,0x7d,0xd3,0xb, 0xe0,0xbc, -0xfe,0x38,0xea,0x7d,0x3d,0xda,0x79,0xda,0xd8,0x22,0x6d,0x0, 0x12,0x1d,0xe9,0x7d, -0x43,0x22,0x74,0x2, 0xac,0xbe,0x7f,0x17,0x2d,0x35,0xb, 0x1a,0x30,0x22,0x74,0x2, -0xac,0xbe,0x7f,0x7, 0x2d,0x15,0x22,0xe4,0x7a,0xb3,0x33,0xfe,0x6d,0x44,0x6c,0x77, -0x74,0xc, 0xac,0xb7,0x59,0x45,0x34,0x15,0xb, 0x70,0xbe,0x70,0x4, 0x40,0xf1,0xe4, -0x7a,0xb3,0x33,0xff,0x22,0xca,0x3b,0x7f,0x30,0x7c,0x6b,0x7e,0xb3,0x1d,0xa1,0xf5, -0x2d,0x7e,0xb3,0x1d,0x93,0xf5,0x2e,0x7e,0xb3,0x1d,0x98,0xf5,0x2f,0x7e,0xb3,0x1d, -0xa3,0xf5,0x30,0x7e,0xb3,0x1d,0xa4,0xf5,0x31,0x74,0x1, 0x7a,0xb3,0x1d,0xa1,0x74, -0x5, 0xac,0xb6,0x9, 0x75,0x17,0xcf,0x7a,0x73,0x1d,0x98,0x74,0x5, 0xac,0xb6,0x9, -0x75,0x17,0xd0,0x7a,0x73,0x1d,0xa3,0x74,0x5, 0xac,0xb6,0x9, 0x75,0x17,0xd1,0x7a, -0x73,0x1d,0xa4,0x74,0x5, 0xac,0xb6,0x9, 0x75,0x17,0xd2,0xbe,0x73,0x1d,0xee,0x68, -0x6, 0x7a,0x73,0x1d,0xee,0xd2,0xc, 0xc2,0x3, 0x74,0x5, 0xac,0xb6,0x9, 0xb5,0x17, -0xce,0x12,0x51,0xc1,0x7e,0x8, 0x1c,0xdf,0x12,0x16,0x52,0x51,0x4f,0x30,0xb, 0xfd, -0x74,0x1, 0x12,0x0, 0xe, 0x7e,0x14,0x80,0x0, 0x7d,0x31,0x7e,0x2f,0x13,0x64,0x7d, -0x25,0x7e,0x4, 0xe, 0x3c,0x12,0x2f,0xfc,0x51,0x44,0x7a,0x55,0x32,0x7f,0x3, 0x7e, -0x18,0xe, 0x3c,0x31,0xad,0x31,0x68,0xe5,0x2d,0x7a,0xb3,0x1d,0xa1,0xe5,0x2e,0x7a, -0xb3,0x1d,0x93,0xe5,0x2f,0x7a,0xb3,0x1d,0x98,0xe5,0x30,0x7a,0xb3,0x1d,0xa3,0xe5, -0x31,0x7a,0xb3,0x1d,0xa4,0xda,0x3b,0x22,0x7e,0x73,0x38,0x9b,0xa, 0x17,0x7e,0x73, -0x1c,0xe3,0x51,0x3b,0xa, 0x47,0x7d,0x10,0xad,0x14,0x7d,0x21,0x6c,0x66,0x80,0x1c, -0xa, 0x56,0x2d,0x52,0x51,0x32,0xb, 0xa, 0xf0,0x7e,0x30,0x2, 0xac,0x36,0x49,0x1, -0x13,0x6c,0x7d,0x5f,0x9d,0x50,0x59,0x51,0x2, 0x8f,0xb, 0x60,0xbc,0x76,0x38,0xe0, -0x7a,0x45,0x32,0x7e,0xf, 0x34,0x76,0x7e,0x18,0x2, 0x8f,0x21,0xad,0x7f,0x71,0x7f, -0x60,0x6d,0x0, 0x6c,0xaa,0x6d,0x11,0x80,0x1e,0x7d,0x31,0x3e,0x34,0x2d,0x3f,0x7d, -0x2e,0xb, 0x1a,0x30,0x12,0x20,0x54,0xbd,0x30,0x48,0xa, 0x51,0x29,0xb, 0x1a,0x30, -0x12,0x20,0x54,0x7d,0x3, 0xb, 0x14,0x7e,0x35,0x32,0xbd,0x31,0x38,0xdb,0x80,0x7, -0xb, 0xa0,0xbe,0xa0,0x8, 0x50,0x11,0x7c,0xba,0x7d,0x40,0x60,0x5, 0xe, 0x44,0x14, -0x78,0xfb,0xbe,0x44,0x0, 0x7f,0x18,0xe8,0x7f,0x16,0x2e,0x35,0x32,0x7a,0x1b,0xa0, -0x6d,0x11,0x80,0x1d,0x51,0x29,0xb, 0x1a,0x0, 0x7f,0x16,0x2e,0x35,0x32,0x7e,0x1b, -0xb0,0x60,0x5, 0xe, 0x4, 0x14,0x78,0xfb,0x7f,0x16,0x2d,0x31,0x7a,0x1b,0x10,0xb, -0x14,0x7e,0x5, 0x32,0xbd,0x1, 0x38,0xdc,0x22,0x7d,0x1, 0x3e,0x4, 0x7f,0x17,0x2d, -0x30,0x22,0x3e,0x54,0x7e,0xf, 0x3, 0xfa,0x2d,0x15,0x22,0xa, 0x7, 0x2d,0x1, 0x7e, -0x73,0x1c,0xe0,0x22,0x7e,0xb3,0x1c,0xe0,0x7e,0x73,0x1c,0xdf,0xac,0xb7,0x22,0xe4, -0x12,0x0, 0xe, 0x74,0x1, 0x7e,0x70,0x99,0x12,0x1c,0x5c,0x2, 0x0, 0x1e,0xca,0xf8, -0x7e,0xf3,0x1c,0xe0,0xa, 0x3f,0x3e,0x34,0x7e,0x8, 0x13,0x6c,0xe4,0x12,0x20,0x12, -0x7e,0x73,0x38,0x9b,0xa, 0x37,0x7e,0x53,0x1c,0xe3,0xa, 0x25,0x2d,0x23,0xa, 0x3f, -0xad,0x32,0x7d,0x43,0x6c,0x77,0x80,0x1c,0xa, 0x57,0x2d,0x54,0x51,0x32,0xb, 0xa, -0x10,0x7e,0x50,0x2, 0xac,0x57,0x2e,0x24,0x13,0x6c,0xb, 0x28,0x50,0x2d,0x51,0x1b, -0x28,0x50,0xb, 0x70,0xbc,0xf7,0x38,0xe0,0xda,0xf8,0x22,0x7e,0xb3,0x1c,0xdb,0x60, -0x2, 0x41,0xb4,0x22,0x7e,0x34,0x0, 0x50,0x7a,0x37,0x1c,0xcc,0x7e,0x34,0x0, 0x46, -0x7a,0x37,0x1c,0xce,0x7e,0x34,0x0, 0x5a,0x7a,0x37,0x1c,0xc1,0x7e,0x24,0x0, 0x64, -0x7a,0x27,0x1c,0xc3,0x7a,0x37,0x1c,0xc5,0x22,0xa2,0x14,0x22,0x7d,0x41,0x7d,0x13, -0x7e,0x3, 0x18,0x20,0xbe,0x0, 0x0, 0x28,0x18,0x6c,0x11,0x80,0xa, 0x71,0x8b,0xbd, -0x32,0x8, 0x2, 0x80,0x52,0xb, 0x10,0x7e,0x3, 0x1c,0xe0,0xbc,0x1, 0x38,0xee,0x80, -0x2, 0xe4,0x22,0x71,0x83,0x28,0x22,0x6c,0x11,0x80,0x14,0xa, 0x31,0xa, 0x50,0x2d, -0x53,0x3e,0x54,0x49,0x55,0x4, 0xd4,0xbd,0x54,0x8, 0x2, 0x80,0x2a,0xb, 0x10,0x7e, -0x73,0x1c,0xdf,0xbc,0x71,0x38,0xe4,0x80,0x2, 0xe4,0x22,0x7e,0x3, 0x1a,0xb5,0xbe, -0x0, 0x0, 0x28,0x4d,0x7e,0x37,0x1a,0xbb,0xbd,0x31,0x18,0xb, 0xbe,0x0, 0x4, 0x40, -0xe, 0x7e,0xb3,0x1c,0xdb,0x70,0x8, 0x74,0xa, 0x7a,0xb3,0x32,0x33,0xe4,0x22,0x7e, -0x27,0x1c,0xce,0x7d,0x32,0x3e,0x34,0xbe,0x37,0x1a,0xbb,0x48,0x3, 0x74,0x1, 0x22, -0x7d,0x32,0x3e,0x34,0x3e,0x34,0xbe,0x37,0x1a,0xbb,0x48,0x3, 0x74,0x2, 0x22,0x7e, -0x34,0x0, 0x6, 0xad,0x32,0xbe,0x37,0x1a,0xbb,0x48,0x3, 0x74,0x3, 0x22,0x74,0x4, -0x22,0xe4,0x22,0x7e,0x73,0x18,0x1f,0xbe,0x70,0x0, 0x22,0x74,0x2, 0xac,0xb1,0x49, -0x35,0x4, 0xd4,0x22,0x6d,0x33,0x7d,0x23,0x7d,0x3, 0x6c,0x33,0x80,0x45,0x6c,0x22, -0x80,0x37,0x7e,0x93,0x1c,0xe0,0xac,0x93,0xa, 0x52,0x2d,0x45,0x7d,0x54,0x3e,0x54, -0x7e,0x7f,0x13,0x68,0x2d,0xf5,0xb, 0x7a,0x50,0xbe,0x54,0x0, 0x32,0x8, 0x8, 0xbe, -0x54,0x2, 0x58,0x58,0x2, 0xb, 0x24,0xbe,0x54,0xff,0xce,0x58,0x8, 0xbe,0x54,0xfd, -0xa8,0x8, 0x2, 0xb, 0x4, 0xb, 0x34,0xb, 0x21,0x7e,0xb3,0x1c,0xe0,0xbc,0xb2,0x38, -0xc1,0xb, 0x31,0x7e,0xb3,0x1c,0xdf,0xbc,0xb3,0x38,0xb3,0x7e,0x54,0x0, 0x6, 0xad, -0x53,0x7d,0x15,0x12,0x97,0x4e,0x91,0x56,0xbd,0x12,0x50,0x22,0xbd,0x30,0x28,0x1e, -0xe4,0x7a,0xb3,0x36,0x46,0x7e,0xb3,0x36,0x47,0xbe,0xb0,0x5, 0x50,0x7, 0x4, 0x7a, -0xb3,0x36,0x47,0x80,0x3c,0xe4,0x7a,0xb3,0x36,0x47,0x74,0x1, 0x80,0x2f,0xbd,0x10, -0x50,0x22,0xbd,0x32,0x28,0x1e,0xe4,0x7a,0xb3,0x36,0x47,0x7e,0xb3,0x36,0x46,0xbe, -0xb0,0x5, 0x50,0x7, 0x4, 0x7a,0xb3,0x36,0x46,0x80,0x16,0xe4,0x7a,0xb3,0x36,0x46, -0x74,0x2, 0x80,0x9, 0xe4,0x7a,0xb3,0x36,0x46,0x7a,0xb3,0x36,0x47,0x7a,0xb3,0x36, -0x48,0x7e,0xb3,0x36,0x48,0x22,0x1e,0x34,0x1e,0x34,0x1e,0x34,0x22,0xe4,0x7a,0xb3, -0x1a,0xd9,0x7a,0xb3,0x36,0x49,0x22,0xca,0xd8,0xca,0x79,0xc2,0x3, 0x6c,0xdd,0x7e, -0x57,0x1a,0xca,0x7d,0xf5,0x7e,0xe7,0x1a,0xc8,0x7e,0x37,0x36,0x39,0x4d,0x33,0x68, -0x4, 0x7d,0xf5,0xe, 0xf4,0x6c,0x88,0x7e,0xa3,0x1c,0xe0,0x7c,0xfa,0x7e,0xb3,0x1a, -0xd6,0x14,0x68,0x21,0x14,0x68,0x14,0x24,0xc2,0x68,0x8, 0x24,0xfb,0x68,0x16,0x24, -0x45,0x78,0x10,0x7c,0x8a,0x7e,0xf3,0x1c,0xdf,0x80,0xa, 0x7e,0x73,0x1c,0xdf,0x2c, -0xf7,0x80,0x2, 0x6c,0xff,0x6c,0x99,0x80,0xf, 0x7c,0xb9,0x12,0x4c,0xa3,0xbe,0x34, -0x2, 0x58,0x8, 0x2, 0xb, 0xd0,0xb, 0x90,0x7e,0x13,0x1a,0xb5,0xbc,0x19,0x38,0xe9, -0xbe,0xd0,0x3, 0x40,0x2, 0xc1,0x3a,0x7e,0x33,0x1a,0xb6,0xbe,0x30,0x0, 0x38,0xb, -0xbe,0x10,0x0, 0x28,0x37,0x7e,0xb3,0x18,0x1e,0x70,0x31,0x6c,0x99,0x80,0x29,0xa, -0x39,0xa, 0x58,0x2d,0x53,0x3e,0x54,0x49,0x35,0x5, 0x3e,0xbd,0x3f,0x8, 0x17,0x49, -0xd5,0x4, 0xd4,0xbd,0xde,0x58,0xf, 0x6d,0x33,0x9d,0x3e,0x12,0x6f,0x16,0xbd,0xd3, -0x8, 0x4, 0xd2,0x3, 0x80,0x6, 0xb, 0x90,0xbc,0xf9,0x38,0xd3,0x6d,0x55,0x9e,0x57, -0x1c,0xc1,0xbe,0x57,0x9, 0x0, 0x8, 0x2, 0xc2,0x3, 0x30,0x3, 0x20,0x7e,0xb3,0x36, -0x49,0x4, 0x7a,0xb3,0x36,0x49,0x7e,0x23,0x36,0x49,0xbe,0x20,0xa, 0x28,0x1d,0x74, -0xa, 0x7a,0xb3,0x36,0x49,0x74,0x1, 0x7a,0xb3,0x1a,0xd9,0x80,0xf, 0x7e,0x23,0x36, -0x49,0xbe,0x20,0x0, 0x28,0x6, 0x1e,0x20,0x7a,0x23,0x36,0x49,0x6c,0xee,0xbe,0x10, -0x0, 0x38,0x5, 0xbe,0x30,0x0, 0x28,0x5d,0x7e,0xb3,0x1a,0xd8,0xb4,0x1, 0x9, 0x7e, -0xb3,0x1a,0xdb,0xbe,0xb0,0x1, 0x68,0x4d,0x7e,0xb3,0x1a,0xd9,0xb4,0x1, 0x46,0x6c, -0x99,0x80,0x1b,0x74,0x2, 0xac,0xb9,0x9, 0x25,0x18,0x96,0x74,0x2, 0xac,0xb2,0x49, -0x55,0x5, 0x3e,0xbd,0x5f,0x8, 0x5, 0x7e,0xe0,0x1, 0x80,0x6, 0xb, 0x90,0xbc,0x19, -0x38,0xe1,0x6c,0x99,0x80,0x1b,0x74,0x2, 0xac,0xb9,0x9, 0x25,0x19,0x68,0x74,0x2, -0xac,0xb2,0x49,0x5, 0x5, 0x3e,0xbd,0xf, 0x8, 0x5, 0x7e,0xe0,0x1, 0x80,0x6, 0xb, -0x90,0xbc,0x39,0x38,0xe1,0x6c,0x99,0x80,0x2a,0xa, 0x19,0xa, 0x8, 0x2d,0x1, 0x3e, -0x4, 0x49,0x10,0x5, 0x3e,0xbd,0x1f,0x8, 0x18,0x49,0x10,0x4, 0xd4,0xbd,0x1e,0x58, -0x10,0x6d,0x33,0x9d,0x3e,0x12,0x6f,0x16,0xbd,0x13,0x8, 0x5, 0x7e,0xe0,0x1, 0x80, -0x6, 0xb, 0x90,0xbc,0xf9,0x38,0xd2,0x4c,0xee,0x78,0x24,0x7e,0xb3,0x36,0x4a,0x4, -0x7a,0xb3,0x36,0x4a,0x7e,0x73,0x36,0x4a,0xbe,0x70,0x5, 0x28,0x21,0x74,0x5, 0x7a, -0xb3,0x36,0x4a,0x7e,0xb3,0x1a,0xd9,0x60,0x2, 0xd2,0x15,0x91,0x5d,0x80,0xf, 0x7e, -0x73,0x36,0x4a,0xbe,0x70,0x0, 0x28,0x6, 0x1e,0x70,0x7a,0x73,0x36,0x4a,0x7e,0x57, -0x9, 0xe, 0xbe,0x54,0x0, 0x0, 0x48,0x2, 0x91,0x5d,0xda,0x79,0xda,0xd8,0x22,0xca, -0x3b,0x7c,0xfb,0x12,0xc4,0x90,0x7e,0xb3,0x1c,0xe1,0xf5,0x41,0x7e,0xb3,0x1c,0xe2, -0xf5,0x42,0x75,0x43,0x28,0x7e,0xb3,0x1a,0xb5,0xf5,0x28,0xe4,0x7a,0xb3,0x32,0xfd, -0x7a,0xb3,0x32,0xf2,0x7a,0xb3,0x32,0xf3,0x7e,0x8, 0x33,0x0, 0x7e,0x73,0x38,0xa2, -0xa, 0x37,0x12,0x20,0x12,0x7e,0x73,0x38,0xa2,0xa, 0x37,0x3e,0x34,0x7e,0x8, 0x33, -0x40,0x12,0x20,0x12,0x7e,0x14,0x1, 0x5e,0x7d,0x21,0x7e,0x37,0x9, 0xa, 0xbd,0x31, -0x48,0x8, 0x7e,0x37,0x9, 0x8, 0xbd,0x32,0x58,0x6, 0x7e,0xb3,0x1c,0xdb,0x70,0x0, -0xe5,0x28,0xbe,0xb0,0x2, 0x50,0x3, 0x2, 0xbe,0x41,0x6c,0xee,0x2, 0xbe,0x38,0x12, -0xcf,0x1f,0x9, 0x25,0x18,0x96,0x7a,0x23,0x2, 0xcb,0x7e,0x33,0x1c,0xe0,0x7e,0x90, -0x2, 0xac,0x93,0x7e,0x10,0x2, 0xac,0x1d,0x2d,0x4, 0x7e,0x1f,0x6, 0x80,0x7f,0x21, -0x2d,0x50,0xb, 0x2a,0x0, 0x7a,0x7, 0x2, 0xcc,0x7e,0x30,0x2, 0x7c,0xb2,0xac,0xb3, -0x2d,0x35,0xb, 0x1a,0x30,0x7a,0x37,0x2, 0xce,0x4c,0xee,0x68,0x5, 0x12,0xbe,0x44, -0x70,0xa, 0xa, 0x3e,0xb, 0x34,0xa, 0x2e,0x19,0x72,0x33,0x0, 0xe5,0x28,0xa, 0x2b, -0x1b,0x24,0xa, 0x3e,0xbd,0x32,0x78,0x3, 0x2, 0xbe,0x41,0xa, 0x5e,0xb, 0x54,0xf5, -0x29,0x2, 0xbe,0x2c,0x75,0x50,0x0, 0x74,0xff,0x7a,0xb3,0x2, 0xd0,0x7a,0xb3,0x2, -0xd1,0x12,0x77,0x7b,0x9, 0xc5,0x18,0x95,0x9, 0x75,0x18,0x96,0x7a,0x73,0x2, 0xd2, -0xa, 0x2c,0x12,0xbe,0x93,0x7a,0x73,0x2, 0xd3,0x12,0xbe,0x66,0x12,0xa6,0xa6,0x7a, -0x73,0x2, 0xd4,0x7e,0x73,0x2, 0xd3,0xbe,0x70,0x6, 0x40,0x3, 0x2, 0xbe,0x2a,0x12, -0xcf,0x7d,0x40,0x3, 0x2, 0xbe,0x2a,0x7e,0xb3,0x2, 0xcb,0xf5,0x54,0x7a,0xc1,0x55, -0x7e,0xb3,0x2, 0xd2,0xf5,0x56,0x7e,0x8, 0x0, 0x2f,0x7e,0x18,0x0, 0x31,0x7c,0xbd, -0x12,0xbe,0xb5,0x12,0xc4,0x90,0x75,0x2e,0x0, 0x7c,0xbd,0x7e,0x73,0x2, 0xcb,0x12, -0x2b,0x76,0x7a,0x35,0x33,0x7c,0xbc,0x7e,0x73,0x2, 0xd2,0x12,0x2b,0x76,0x7a,0x35, -0x35,0x7e,0x35,0x33,0xbe,0x35,0x35,0x8, 0x5, 0x7e,0x35,0x35,0x80,0x3, 0x7e,0x35, -0x33,0x7a,0x35,0x39,0xe, 0x34,0x7a,0x35,0x37,0x7e,0xa3,0x2, 0xd3,0xbe,0xa0,0x1, -0x38,0x10,0x12,0xcf,0x85,0x38,0xb, 0x7c,0xbf,0x30,0xe1,0x6, 0x75,0x2e,0x1, 0x2, -0xbb,0x46,0xbe,0xa0,0x1, 0x38,0x8, 0x12,0xcf,0x85,0x38,0x3, 0x2, 0xbb,0x46,0xbe, -0xa0,0x6, 0x40,0x3, 0x2, 0xbb,0x46,0x12,0xcf,0x7d,0x40,0x3, 0x2, 0xbb,0x46,0x7c, -0xbf,0x20,0xe0,0x3, 0x2, 0xbb,0x46,0x6d,0x88,0x7d,0x98,0x75,0x51,0x0, 0x75,0x52, -0x0, 0xc2,0x4, 0xc2,0x5, 0xbc,0xcd,0x28,0x4, 0x7c,0xbd,0x80,0x2, 0x7c,0xbc,0xf5, -0x24,0xbc,0xcd,0x50,0x4, 0x7c,0xbd,0x80,0x2, 0x7c,0xbc,0xf5,0x26,0x7e,0xa3,0x2, -0xd2,0xbe,0xa3,0x2, 0xcb,0x28,0x6, 0x7e,0xb3,0x2, 0xcb,0x80,0x4, 0x7e,0xb3,0x2, -0xd2,0xf5,0x25,0xbe,0xa3,0x2, 0xcb,0x50,0x6, 0x7e,0xb3,0x2, 0xcb,0x80,0x4, 0x7e, -0xb3,0x2, 0xd2,0xf5,0x27,0xe5,0x41,0xa, 0xeb,0x1b,0xe4,0xe5,0x26,0xa, 0x4b,0xbd, -0x4e,0x58,0x8, 0xe5,0x26,0xa, 0x5b,0xb, 0x54,0x80,0x2, 0xe5,0x26,0xf5,0x4c,0xe5, -0x24,0xbe,0xb0,0x0, 0x28,0x8, 0xe5,0x24,0xa, 0x5b,0x1b,0x54,0x80,0x2, 0xe5,0x24, -0xf5,0x4d,0xe5,0x42,0xa, 0x3b,0x1b,0x34,0xe5,0x27,0xa, 0xfb,0xbd,0xf3,0x58,0x8, -0xe5,0x27,0xa, 0x5b,0xb, 0x54,0x80,0x2, 0xe5,0x27,0xf5,0x4e,0xe5,0x25,0xbe,0xb0, -0x0, 0x28,0x8, 0xe5,0x25,0xa, 0x5b,0x1b,0x54,0x80,0x2, 0xe5,0x25,0xf5,0x4f,0x75, -0x2a,0x0, 0x80,0x75,0xbe,0xe1,0x2a,0x68,0x6e,0xe5,0x29,0xbe,0xb1,0x2a,0x68,0x67, -0x7e,0x71,0x2a,0x74,0x2, 0xac,0x7b,0x9, 0xa3,0x18,0x95,0xbe,0xa1,0x4c,0x78,0x11, -0x7d,0x14,0xb, 0x14,0xe5,0x4c,0xa, 0x2b,0xbd,0x21,0x78,0x5, 0x85,0x26,0x4c,0x80, -0x16,0xbe,0xa1,0x4d,0x78,0x11,0xe5,0x4d,0xa, 0x1b,0xb, 0x14,0xe5,0x24,0xa, 0x2b, -0xbd,0x12,0x78,0x3, 0x85,0x24,0x4d,0x9, 0xa3,0x18,0x96,0xbe,0xa1,0x4e,0x78,0x11, -0x7d,0x1f,0xb, 0x14,0xe5,0x4e,0xa, 0x2b,0xbd,0x21,0x78,0x5, 0x85,0x27,0x4e,0x80, -0x16,0xbe,0xa1,0x4f,0x78,0x11,0xe5,0x4f,0xa, 0x3b,0xb, 0x34,0xe5,0x25,0xa, 0x5b, -0xbd,0x35,0x78,0x3, 0x85,0x25,0x4f,0x5, 0x2a,0xe5,0x28,0xbe,0xb1,0x2a,0x38,0x84, -0xe5,0x26,0xbe,0xb1,0x24,0x78,0x1f,0xd2,0x4, 0xe5,0x24,0x60,0x8, 0xe5,0x24,0xa, -0x5b,0xbd,0x5e,0x78,0x2, 0xd2,0x5, 0xe5,0x24,0xbe,0xb0,0x0, 0x28,0x2, 0x15,0x24, -0xbd,0x4e,0x58,0x2, 0x5, 0x26,0xe5,0x27,0xbe,0xb1,0x25,0x78,0x2b,0xd2,0x4, 0xe5, -0x25,0x60,0xe, 0xe5,0x42,0xa, 0xeb,0x1b,0xe4,0xe5,0x25,0xa, 0x5b,0xbd,0x5e,0x78, -0x2, 0xd2,0x5, 0xe5,0x25,0xbe,0xb0,0x0, 0x28,0x2, 0x15,0x25,0xe5,0x42,0xa, 0x5b, -0x1b,0x54,0xbd,0xf5,0x58,0x2, 0x5, 0x27,0x75,0x2c,0x0, 0x75,0x2d,0x0, 0x75,0x2b, -0x0, 0x80,0x16,0xe5,0x2b,0xa, 0x5b,0x9, 0x75,0x17,0xf6,0xbe,0x71,0x4c,0x38,0x7, -0xbe,0x71,0x4d,0x40,0x2, 0x5, 0x2c,0x5, 0x2b,0x7e,0x73,0x18,0x1f,0xbe,0x71,0x2b, -0x38,0xe1,0x75,0x2b,0x0, 0x80,0x16,0xe5,0x2b,0xa, 0x5b,0x9, 0x75,0x18,0xa, 0xbe, -0x71,0x4e,0x38,0x7, 0xbe,0x71,0x4f,0x40,0x2, 0x5, 0x2d,0x5, 0x2b,0x7e,0x73,0x18, -0x20,0xbe,0x71,0x2b,0x38,0xe1,0x85,0x24,0x3d,0x80,0x53,0x85,0x25,0x3e,0x80,0x45, -0xe5,0x3d,0x7e,0x71,0x3e,0x12,0x2b,0x76,0x7a,0x35,0x3f,0xe5,0x24,0xbe,0xb1,0x3d, -0x68,0x15,0xe5,0x26,0xbe,0xb1,0x3d,0x68,0xe, 0xe5,0x25,0xbe,0xb1,0x3e,0x68,0x7, -0xe5,0x27,0xbe,0xb1,0x3e,0x78,0x9, 0x7e,0x55,0x3f,0x2d,0x95,0x5, 0x51,0x80,0x13, -0x5, 0x52,0x7e,0x55,0x3f,0x2d,0x85,0x7e,0x55,0x31,0xbe,0x55,0x3f,0x58,0x2, 0x5, -0x3b,0x5, 0x3c,0x5, 0x3e,0xe5,0x27,0xbe,0xb1,0x3e,0x50,0xb4,0x5, 0x3d,0xe5,0x26, -0xbe,0xb1,0x3d,0x50,0xa6,0xe5,0x26,0xd1,0x53,0xe5,0x24,0x12,0x2f,0xf7,0x9d,0x93, -0xe5,0x24,0xd1,0x53,0xe5,0x26,0x12,0x2f,0xf7,0x9d,0x93,0x7e,0x55,0x35,0x2e,0x55, -0x33,0x7a,0x55,0x37,0x30,0x4, 0xa, 0x20,0x5, 0x7, 0x9e,0x95,0x37,0x15,0x51,0x15, -0x51,0xe5,0x51,0xbe,0xb0,0x4, 0x28,0x6, 0xe5,0x51,0x24,0xfc,0xf5,0x51,0xbe,0x94, -0x0, 0x0, 0x58,0x2, 0x6d,0x99,0x75,0x43,0x22,0xe5,0x41,0xa, 0xeb,0x1b,0xe4,0xa, -0x5d,0xbd,0xe5,0x68,0x66,0xa, 0x5c,0xbd,0xe5,0x68,0x60,0x4c,0xdd,0x68,0x5c,0x4c, -0xcc,0x68,0x58,0xe5,0x2d,0x7e,0x71,0x2c,0xac,0xb7,0xbe,0x54,0x0, 0x1, 0x78,0x4b, -0x7e,0x73,0x18,0x1f,0xbe,0x70,0x1, 0x28,0x16,0x7e,0xb3,0x18,0x20,0xb4,0x1, 0xf, -0xd1,0x66,0x12,0xa6,0xa6,0x7d,0x53,0xa, 0x2c,0xd1,0x93,0xbd,0x35,0x48,0x1f,0x7e, -0xb3,0x18,0x1f,0xb4,0x1, 0x25,0x7e,0x73,0x18,0x20,0xbe,0x70,0x1, 0x28,0x1c,0xd1, -0x66,0x12,0xa6,0xa6,0x7d,0x53,0xa, 0x2c,0xd1,0x93,0xbd,0x35,0x8, 0xd, 0xe5,0x43, -0xa, 0x3b,0x12,0x6f,0x16,0x7c,0xb7,0x25,0x43,0xf5,0x43,0x7d,0x18,0x1a,0x2, 0x1a, -0x0, 0x7d,0x39,0x1a,0x26,0x1a,0x24,0x2f,0x10,0xe5,0x43,0xa, 0x1b,0x6d,0x0, 0x12, -0x1d,0x7c,0x7a,0x1d,0x44,0x7e,0x15,0x37,0x1a,0x2, 0x1a,0x0, 0x7e,0x35,0x2f,0x1a, -0x26,0x1a,0x24,0x12,0x1d,0x7c,0xe5,0x52,0xa, 0xdb,0x6d,0xcc,0xe5,0x51,0xa, 0x1b, -0x6d,0x0, 0x2f,0x6, 0x12,0x1d,0x7c,0x7f,0x1, 0x7a,0xd, 0x48,0x7e,0x1d,0x44,0xbf, -0x10,0x8, 0x3, 0x75,0x2e,0x2, 0x7e,0xb3,0x1c,0xdb,0x70,0x7, 0x7e,0xb3,0x1c,0xdd, -0xb4,0x1, 0x23,0x7e,0x73,0x2, 0xd3,0xbe,0x70,0x2, 0x38,0x9, 0x7e,0x63,0x2, 0xd4, -0xbe,0x60,0x3, 0x28,0xe, 0xbe,0x70,0x3, 0x38,0xc, 0x7e,0x73,0x2, 0xd4,0xbe,0x70, -0x2, 0x38,0x3, 0x75,0x2e,0x2, 0x12,0x0, 0x6e,0x50,0x2, 0x81,0x92,0x7e,0xb3,0x18, -0x1f,0xb4,0x2, 0x2, 0x80,0x2, 0x61,0xe4,0x7e,0xb3,0x18,0x20,0xb4,0x1, 0x2, 0x80, -0x2, 0x61,0xe4,0x7e,0x73,0x17,0xf6,0xa, 0x57,0xb, 0x54,0xf5,0x2a,0x80,0x12,0xd1, -0x9a,0x69,0xe0,0x0, 0x2, 0xbe,0xe4,0x0, 0x50,0x48,0xf, 0xd1,0x4b,0x18,0xb, 0x5, -0x2a,0x7e,0x73,0x17,0xf7,0xbe,0x71,0x2a,0x38,0xe5,0xe5,0x2a,0x7a,0xb3,0x2, 0xd0, -0x7e,0x73,0x17,0xf7,0xa, 0x57,0x1b,0x54,0xf5,0x2a,0x80,0xc, 0xd1,0x9a,0xd1,0x5c, -0x48,0xf, 0xd1,0x4b,0x18,0xb, 0x15,0x2a,0x7e,0x73,0x17,0xf6,0xbe,0x71,0x2a,0x40, -0xeb,0xd1,0x71,0xbc,0x7d,0x40,0xc, 0x7e,0x63,0x2, 0xd1,0xbc,0x6c,0x38,0x4, 0xbc, -0xdc,0x40,0x16,0xbc,0x7c,0x50,0x2, 0x81,0x92,0x7e,0x73,0x2, 0xd1,0xbc,0x7d,0x28, -0x2, 0x81,0x92,0xbc,0xcd,0x40,0x2, 0x81,0x92,0xe5,0x2e,0xb4,0x2, 0x2, 0x80,0x2, -0x81,0x92,0x81,0x8f,0x7e,0xb3,0x18,0x20,0xb4,0x2, 0x2, 0x80,0x2, 0x81,0x92,0x7e, -0xb3,0x18,0x1f,0xb4,0x1, 0x2, 0x80,0x2, 0x81,0x92,0x7e,0x73,0x18,0xa, 0xa, 0x57, -0xb, 0x54,0xf5,0x2a,0x80,0x17,0xd1,0x7c,0x2d,0x35,0x69,0xe1,0x0, 0x2, 0xbe,0xe4, -0x0, 0x50,0x48,0x12,0xb, 0x1a,0x50,0xbd,0xe5,0x18,0xb, 0x5, 0x2a,0x7e,0x73,0x18, -0xb, 0xbe,0x71,0x2a,0x38,0xe0,0xe5,0x2a,0x7a,0xb3,0x2, 0xd0,0x7e,0x73,0x18,0xb, -0xa, 0x57,0x1b,0x54,0xf5,0x2a,0x80,0x13,0xd1,0x7c,0x2d,0x35,0x7f,0x1, 0xd1,0x5c, -0x48,0x12,0xb, 0x1a,0x50,0xbd,0xe5,0x18,0xb, 0x15,0x2a,0x7e,0x73,0x18,0xa, 0xbe, -0x71,0x2a,0x40,0xe4,0xd1,0x71,0xbe,0x73,0x2, 0xcb,0x40,0x14,0x7e,0x63,0x2, 0xd1, -0xbe,0x63,0x2, 0xd2,0x38,0xa, 0x7e,0x63,0x2, 0xcb,0xbe,0x63,0x2, 0xd2,0x40,0x1a, -0xbe,0x73,0x2, 0xd2,0x40,0x1c,0x7e,0x73,0x2, 0xd1,0xbe,0x73,0x2, 0xcb,0x38,0x12, -0x7e,0x73,0x2, 0xd2,0xbe,0x73,0x2, 0xcb,0x50,0x8, 0xe5,0x2e,0xb4,0x2, 0x3, 0x75, -0x2e,0x0, 0x7e,0xb3,0x1c,0x48,0x60,0x2f,0x7e,0xb3,0x32,0xfe,0x70,0x29,0xa, 0x5e, -0x9, 0x65,0x33,0x22,0xbe,0x60,0xff,0x68,0x1e,0xe5,0x29,0xa, 0x2b,0x9, 0x72,0x33, -0x22,0xbe,0x70,0xff,0x68,0x11,0xbc,0x67,0x78,0x5, 0x75,0x2e,0x2, 0x80,0x8, 0xe5, -0x2e,0xb4,0x2, 0x3, 0x75,0x2e,0x0, 0x12,0x0, 0x6e,0x40,0x1c,0x7e,0x73,0x18,0x20, -0xbe,0x71,0x28,0x50,0x9, 0x7e,0x73,0x18,0x1f,0xbe,0x71,0x28,0x40,0xa, 0xe5,0x2e, -0xbe,0xb0,0x1, 0x28,0x3, 0x75,0x2e,0x0, 0xe5,0x2e,0xbe,0xb0,0x1, 0x38,0x2, 0xa1, -0x7b,0x7e,0xb3,0x32,0xf4,0xb4,0x1, 0x2, 0x80,0x2, 0xa1,0xc7,0x7e,0xb3,0x32,0xfe, -0x60,0x2, 0xa1,0xc7,0x7e,0x43,0x32,0xf6,0xbc,0x4d,0x50,0x34,0x7e,0x63,0x32,0xf7, -0xbc,0x6d,0x28,0x2c,0x7e,0x73,0x32,0xf8,0xbe,0x73,0x2, 0xcb,0x50,0x22,0x7e,0x53, -0x32,0xf9,0xbe,0x53,0x2, 0xcb,0x28,0x18,0xbc,0x4c,0x38,0x4a,0xbc,0x6c,0x40,0x46, -0xbe,0x73,0x2, 0xd2,0x38,0x40,0xbe,0x53,0x2, 0xd2,0x40,0x2, 0xa1,0xc7,0x80,0x36, -0xbc,0x4c,0x40,0x2, 0xa1,0xc7,0x7e,0x53,0x32,0xf7,0xbc,0x5c,0x28,0x79,0x7e,0x63, -0x32,0xf8,0xbe,0x63,0x2, 0xd2,0x50,0x6f,0x7e,0x73,0x32,0xf9,0xbe,0x73,0x2, 0xd2, -0x28,0x65,0xbc,0x4d,0x38,0x10,0xbc,0x5d,0x40,0xc, 0xbe,0x63,0x2, 0xcb,0x38,0x6, -0xbe,0x73,0x2, 0xcb,0x50,0x51,0x75,0x2e,0x0, 0x80,0x4c,0xe5,0x2e,0x70,0x48,0x7e, -0xb3,0x32,0xf4,0xb4,0x1, 0x41,0x7e,0xb3,0x32,0xfe,0x70,0x3b,0x7e,0x43,0x32,0xf6, -0xbc,0x4d,0x50,0x33,0x7e,0x53,0x32,0xf7,0xbc,0x5d,0x28,0x2b,0x7e,0x63,0x32,0xf8, -0xbe,0x63,0x2, 0xcb,0x50,0x21,0x7e,0x73,0x32,0xf9,0xbe,0x73,0x2, 0xcb,0x28,0x17, -0xbc,0x4c,0x50,0x13,0xbc,0x5c,0x28,0xf, 0xbe,0x63,0x2, 0xd2,0x50,0x9, 0xbe,0x73, -0x2, 0xd2,0x28,0x3, 0x75,0x2e,0x2, 0xe5,0x2e,0xbe,0xb0,0x0, 0x28,0x5c,0xe5,0x2e, -0xa, 0xeb,0x2e,0xe4,0x32,0xf1,0x7e,0xe9,0xb0,0x4, 0x7a,0xe9,0xb0,0xe5,0x29,0xa, -0xeb,0x9, 0xae,0x33,0x0, 0x4c,0xaa,0x78,0x8, 0xd1,0x44,0x19,0xbe,0x33,0x0, 0x80, -0x39,0xd1,0x44,0xf5,0x53,0xbc,0xba,0x28,0x3, 0x7a,0xa1,0x53,0x75,0x2a,0x0, 0x80, -0x22,0x9, 0x5e,0x33,0x0, 0xe5,0x2a,0xa, 0x3b,0x9, 0x43,0x33,0x0, 0xbc,0x45,0x68, -0xa, 0xa, 0x5e,0x9, 0x55,0x33,0x0, 0xbc,0x45,0x78,0x6, 0xe5,0x53,0x19,0xb3,0x33, -0x0, 0x5, 0x2a,0xe5,0x28,0xbe,0xb1,0x2a,0x38,0xd7,0x5, 0x29,0xe5,0x28,0xbe,0xb1, -0x29,0x28,0x3, 0x2, 0xb7,0x14,0xb, 0xe0,0xe5,0x28,0xbc,0xbe,0x28,0x3, 0x2, 0xb6, -0xaf,0xda,0x3b,0x22,0xa, 0x3e,0x9, 0xb3,0x33,0x0, 0x22,0x2d,0x35,0xb, 0x1a,0x50, -0xbd,0xe5,0x22,0x7e,0x71,0x25,0x12,0x2b,0x76,0x9d,0x93,0x22,0x1b,0x15,0xb, 0xa, -0xe0,0xbe,0xe4,0x0, 0x50,0x22,0x7e,0x73,0x2, 0xd2,0xa, 0x27,0x7e,0x73,0x2, 0xcb, -0x22,0xe5,0x2a,0x7a,0xb3,0x2, 0xd1,0x7e,0x73,0x2, 0xd0,0x22,0x7e,0x71,0x2a,0x74, -0x2, 0xac,0xb7,0x7e,0x1f,0x6, 0x80,0x22,0x9d,0x32,0x12,0x20,0x54,0x7d,0xc3,0xe5, -0x2c,0xa, 0x2b,0xa, 0x3d,0x9d,0x32,0x2, 0x20,0x54,0x7e,0x63,0x1c,0xe0,0x7e,0x70, -0x2, 0xac,0x67,0x7e,0x51,0x2a,0x74,0x2, 0xac,0xb5,0x2d,0x53,0x7e,0x1f,0x6, 0x80, -0x7f,0x1, 0x2d,0x15,0x22,0x7c,0x9b,0x7f,0x71,0x7f,0x60,0x7e,0x34,0x23,0x30,0x7e, -0x24,0x0, 0xff,0x7e,0x14,0x2, 0xd5,0x74,0x2a,0x12,0x1e,0x3e,0x7e,0x58,0x2, 0xd5, -0x7c,0xb9,0x7e,0x71,0x54,0x12,0x2b,0x76,0x7d,0x43,0xe5,0x55,0x7e,0x71,0x56,0x12, -0x2b,0x76,0x2d,0x34,0xe, 0x34,0x7f,0x5, 0x7e,0x50,0x7, 0xb, 0xa, 0x50,0xbd,0x53, -0x58,0xf, 0x69,0x30,0x0, 0x2, 0x1b,0x6a,0x30,0x69,0x30,0x0, 0x4, 0x1b,0x7a,0x30, -0x22,0x2e,0x14,0x0, 0x6, 0x1b,0x50,0x78,0xe2,0x22,0x7c,0x7b,0x74,0x2, 0xac,0xb7, -0x9, 0x55,0x18,0x95,0x9, 0x65,0x18,0x96,0x7e,0x73,0x1a,0xbd,0xbc,0x75,0x78,0xa, -0x7e,0x73,0x1a,0xbe,0xbc,0x76,0x78,0x2, 0xd3,0x22,0xc3,0x22,0x6c,0x77,0x80,0x1c, -0x7e,0x30,0x2, 0xac,0x37,0x49,0x1, 0x13,0xae,0x49,0x21,0x13,0x6c,0xbd,0x20,0x28, -0x9, 0x2e,0x14,0x13,0x6c,0x9d,0x20,0x1b,0x18,0x20,0xb, 0x70,0x7e,0x63,0x1c,0xe0, -0xbc,0x67,0x38,0xdc,0x22,0x7c,0xab,0xa9,0xd1,0xcb,0x74,0x1, 0x12,0x0, 0xe, 0xd2, -0x17,0x7c,0xba,0x12,0x65,0xc7,0xc2,0x17,0x22,0xe1,0x6b,0xca,0x3b,0x7c,0xa5,0x7c, -0x96,0x7c,0x87,0x7c,0xfb,0x7e,0xf, 0x13,0x68,0x7e,0xe3,0x38,0x51,0x7e,0xd0,0xff, -0x7e,0xc0,0xff,0x7c,0x79,0xac,0x7e,0xa, 0x8a,0x7d,0xc3,0x2d,0xc8,0x3e,0xc4,0x7f, -0x10,0x2d,0x3c,0xb, 0x1a,0xc0,0x7c,0x7f,0xac,0x7e,0xa, 0x28,0x12,0xc0,0x7b,0xb, -0x7a,0xb0,0xbd,0xbc,0x58,0x6, 0x7d,0xdb,0xe, 0xd4,0x80,0x4, 0x7d,0xdc,0xe, 0xd4, -0xbe,0xd4,0x1, 0xf4,0x8, 0x4, 0x7e,0xd4,0x1, 0xf4,0x7e,0xb3,0x1c,0x48,0xbe,0xb0, -0x1, 0x38,0x2e,0xbe,0xd4,0x1, 0x2c,0x8, 0x4, 0x7e,0xd4,0x1, 0x2c,0x7d,0x38,0x9d, -0x32,0x12,0x20,0x54,0xbe,0x34,0x0, 0x8, 0x8, 0x4, 0x7e,0xd4,0x0, 0x64,0xa, 0x28, -0xa, 0x3a,0x9d,0x32,0x12,0x20,0x54,0xbe,0x34,0x0, 0x6, 0x8, 0x4, 0x7e,0xd4,0x0, -0x78,0xbc,0x8a,0x28,0x3, 0x7e,0xc0,0x1, 0xbc,0xf9,0x28,0x3, 0x7e,0xd0,0x1, 0x6d, -0xcc,0x11,0x64,0x78,0x38,0xbc,0xf9,0x68,0x56,0x1a,0x3d,0xa, 0x29,0x2d,0x23,0xa, -0x3e,0xad,0x32,0xa, 0x2a,0x11,0x7b,0xb, 0x7a,0xc0,0x7c,0x79,0xac,0x7e,0x1a,0xbc, -0x2d,0xb2,0x2d,0xb3,0x3e,0xb4,0x7f,0x10,0x2d,0x3b,0xb, 0x1a,0xb0,0xbd,0xcb,0x58, -0x6, 0x7d,0xab,0x2c,0xac,0x80,0x21,0x7d,0xac,0x2c,0x9d,0x80,0x1b,0x11,0x64,0x8, -0x4, 0x2c,0x9d,0x80,0x2, 0x2c,0xac,0x7c,0x79,0xac,0x7e,0xa, 0xaa,0x2d,0xa3,0x3e, -0xa4,0x7f,0x10,0x2d,0x3a,0xb, 0x1a,0xa0,0xbd,0xda,0x8, 0xa3,0xe4,0x80,0x2, 0x74, -0x1, 0xda,0x3b,0x22,0xa, 0x28,0xa, 0x3a,0x9d,0x32,0x12,0x20,0x54,0x7d,0xf3,0xa, -0x2f,0xa, 0x39,0x9d,0x32,0x12,0x20,0x54,0xbd,0x3f,0x22,0x2d,0x32,0x3e,0x34,0x7f, -0x70,0x2d,0xf3,0x22,0xca,0xd8,0xca,0x79,0x7c,0xf7,0x7c,0xeb,0x6c,0xdd,0xa, 0x3d, -0x9, 0xb3,0x31,0x27,0xb4,0x2, 0x1a,0x7c,0xbe,0x7c,0x7f,0x7e,0x50,0x9, 0xac,0x5d, -0x9, 0x62,0x31,0x42,0x9, 0x52,0x31,0x43,0x12,0xbf,0x69,0x60,0x4, 0x74,0x1, 0x80, -0x8, 0xb, 0xd0,0xbe,0xd0,0xa, 0x40,0xd6,0xe4,0xda,0x79,0xda,0xd8,0x22,0xca,0x3b, -0x7c,0xf6,0x7c,0xe7,0x7c,0x3b,0x7e,0xd0,0x1, 0x6d,0x33,0x7a,0x35,0x2e,0x7a,0x35, -0x30,0x7a,0x35,0x32,0x7a,0x35,0x34,0x75,0x36,0x0, 0x75,0x37,0x0, 0x75,0x38,0x0, -0x75,0x39,0x0, 0x75,0x3a,0x0, 0x91,0x90,0x74,0x9, 0xac,0xb3,0x9, 0xc5,0x1a,0xe6, -0x9, 0xb5,0x1a,0xe7,0xf5,0x27,0xa, 0x3c,0x1b,0x36,0x7c,0x27,0x7a,0x21,0x29,0xa, -0x5c,0xb, 0x56,0xf5,0x2b,0xbe,0x20,0x0, 0x58,0x8, 0x75,0x29,0x0, 0x75,0x2b,0x8, -0x80,0x1d,0x7e,0x23,0x38,0x50,0xa, 0x32,0x1b,0x34,0xe5,0x2b,0x1a,0x2b,0xbd,0x23, -0x8, 0xd, 0x7c,0x27,0x7a,0x21,0x2b,0x1a,0x52,0x9e,0x54,0x0, 0x8, 0xf5,0x29,0xe5, -0x27,0xa, 0x5b,0x7d,0x45,0x1b,0x46,0x7c,0x29,0x7a,0x21,0x28,0xb, 0x56,0xf5,0x2a, -0xbe,0x20,0x0, 0x58,0x8, 0x75,0x28,0x0, 0x75,0x2a,0x8, 0x80,0x1d,0x7e,0x23,0x38, -0x51,0xa, 0x32,0x1b,0x34,0xe5,0x2a,0x1a,0x2b,0xbd,0x23,0x8, 0x10,0x7c,0x27,0x7a, -0x21,0x2a,0x1a,0x52,0x9e,0x54,0x0, 0x8, 0xf5,0x28,0x75,0x38,0x1, 0xe5,0x38,0x60, -0x4a,0x74,0x9, 0xac,0xb3,0x49,0x25,0x1a,0xdf,0xbe,0x24,0x1, 0x80,0x40,0x16,0x7e, -0x23,0x38,0x50,0xa, 0x42,0x7e,0x54,0x1, 0x0, 0xad,0x54,0x7d,0x35,0x9e,0x34,0x1, -0x80,0xbd,0x23,0x28,0x26,0x7e,0x23,0x38,0x51,0xa, 0x22,0x1b,0x24,0x91,0x97,0x3e, -0x24,0x74,0x9, 0xac,0xb3,0x49,0x35,0x1a,0xe1,0xbd,0x32,0x38,0x6, 0xbe,0x34,0x1, -0x0, 0x50,0x5, 0x7e,0xd0,0x3, 0x80,0x3, 0x7e,0xd0,0x2, 0xbe,0xc0,0x2, 0x28,0x1a, -0x7e,0x73,0x38,0x50,0xa, 0x27,0x9e,0x24,0x0, 0x3, 0xa, 0x3c,0xbd,0x32,0x58,0xa, -0xe5,0x27,0xbe,0xb0,0x2, 0x28,0x3, 0xe4,0x81,0x7d,0xe5,0x38,0x70,0x10,0x4c,0xff, -0x68,0xc, 0x7c,0xbc,0x7e,0x71,0x27,0x11,0x84,0x60,0x3, 0x7e,0xd0,0x3, 0xbe,0xc0, -0x3, 0x40,0x10,0x7e,0x73,0x38,0x50,0xa, 0x27,0x1b,0x26,0xa, 0x3c,0xbd,0x32,0x18, -0x2, 0x41,0x89,0xbe,0xc0,0x3, 0x50,0x7, 0x6c,0xcc,0x75,0x36,0x1, 0x80,0x17,0x12, -0xaf,0x67,0x1b,0x16,0xa, 0x2c,0xbd,0x21,0x8, 0xc, 0xa, 0x37,0x1b,0x34,0x7c,0xc7, -0xa, 0x5c,0x1b,0x54,0xf5,0x36,0x85,0x28,0x26,0x80,0x57,0x7c,0xbc,0x91,0x80,0x7a, -0x35,0x2c,0x2e,0x35,0x2e,0x7a,0x35,0x2e,0xe5,0x36,0x91,0x80,0x2e,0x35,0x30,0x7a, -0x35,0x30,0x7e,0x35,0x2c,0xbe,0x34,0x0, 0xa5,0x8, 0x4, 0x4c,0xff,0x68,0x1f,0xbe, -0x34,0x0, 0x4d,0x8, 0xa, 0x7e,0x25,0x30,0x3e,0x24,0xbe,0x25,0x2e,0x48,0xf, 0xbe, -0x34,0x0, 0x37,0x8, 0xd, 0x7e,0x25,0x30,0xbe,0x24,0x0, 0xb, 0x58,0x4, 0x5, 0x39, -0x80,0xe, 0xbe,0x34,0x0, 0x4d,0x58,0x8, 0xbe,0x34,0x0, 0x21,0x8, 0x2, 0x5, 0x3b, -0x5, 0x26,0xe5,0x2a,0xbe,0xb1,0x26,0x58,0xa2,0xe5,0x27,0xbe,0xb0,0x3, 0x50,0x7d, -0xe5,0x27,0xbe,0xb0,0x3, 0x50,0x6, 0x75,0x27,0x0, 0x75,0x37,0x1, 0x85,0x29,0x26, -0x80,0x64,0xe5,0x26,0x12,0x2f,0xf7,0x7d,0x43,0x9e,0x44,0x0, 0x21,0x7d,0x54,0x2e, -0x55,0x32,0x7a,0x55,0x32,0xe5,0x26,0x7e,0x71,0x37,0x12,0x2b,0x76,0x7d,0x53,0x9e, -0x54,0x0, 0x21,0x2e,0x55,0x34,0x7a,0x55,0x34,0xbe,0x44,0x0, 0xa5,0x8, 0x4, 0x4c, -0xff,0x68,0x1f,0xbe,0x44,0x0, 0x4d,0x8, 0xa, 0x7e,0x55,0x34,0x3e,0x54,0xbe,0x55, -0x32,0x48,0xf, 0xbe,0x44,0x0, 0x37,0x8, 0xd, 0x7e,0x55,0x34,0xbe,0x54,0x0, 0xb, -0x58,0x4, 0x5, 0x3a,0x80,0xe, 0xbe,0x44,0x0, 0x4d,0x58,0x8, 0xbe,0x44,0x0, 0x21, -0x8, 0x2, 0x5, 0x3c,0x5, 0x26,0xe5,0x2b,0xbe,0xb1,0x26,0x58,0x95,0x7c,0xbc,0x12, -0x2f,0xf7,0x7a,0x35,0x2c,0xa, 0x2e,0x9, 0x72,0x30,0xc3,0x12,0x45,0x29,0xbe,0x35, -0x2c,0x58,0x46,0x7e,0x35,0x2c,0xbe,0x34,0x4, 0x0, 0x48,0x8, 0x74,0xff,0x19,0xb2, -0x30,0xc3,0x80,0x8, 0xe, 0x34,0xe, 0x34,0x19,0x72,0x30,0xc3,0xbe,0xc0,0x3, 0x28, -0xb, 0x12,0xaf,0x67,0x1b,0x16,0xa, 0x3c,0xbd,0x31,0x48,0x8, 0xe5,0x39,0xa, 0x1b, -0xe5,0x3b,0x80,0xd, 0xe5,0x27,0xbe,0xb0,0x3, 0x38,0xe, 0xe5,0x3a,0xa, 0x1b,0xe5, -0x3c,0xa, 0x3b,0x2d,0x31,0x19,0x72,0x31,0x98,0xe5,0x39,0xbe,0xb0,0x5, 0x38,0x7, -0xe5,0x3a,0xbe,0xb0,0x5, 0x28,0x2, 0xb, 0xd0,0xe5,0x39,0xbe,0xb0,0x6, 0x38,0x7, -0xe5,0x3a,0xbe,0xb0,0x6, 0x28,0x2, 0xb, 0xd0,0xe5,0x39,0xbe,0xb0,0x7, 0x38,0x7, -0xe5,0x3a,0xbe,0xb0,0x7, 0x28,0x2, 0xb, 0xd0,0x7e,0x35,0x30,0xbe,0x34,0x0, 0x0, -0x18,0x5, 0x6d,0x33,0x7a,0x35,0x30,0x7e,0x35,0x2e,0x7d,0x23,0xe, 0x24,0xe, 0x24, -0xbe,0x25,0x30,0x8, 0x16,0x4c,0xff,0x78,0x12,0xe5,0x38,0x70,0xe, 0x7e,0x25,0x30, -0x2e,0x25,0x2e,0xbe,0x24,0x5, 0x28,0x8, 0x2, 0xb, 0xd0,0xe, 0x34,0xbe,0x35,0x30, -0x8, 0xe, 0x7e,0x35,0x30,0x2e,0x35,0x2e,0xbe,0x34,0xc, 0xe4,0x8, 0x2, 0xb, 0xd0, -0xa, 0x2f,0xb, 0x26,0xe5,0x39,0xa, 0x3b,0xbd,0x32,0x8, 0x2, 0xb, 0xd0,0xe5,0x39, -0x70,0x6, 0xe5,0x3a,0x70,0x2, 0x6c,0xdd,0xe5,0x38,0x60,0x48,0x6c,0x99,0x4c,0xcc, -0x78,0xe, 0x7c,0xac,0xa, 0x3c,0x2e,0x34,0x0, 0x5, 0x7c,0xb7,0xf5,0x3d,0x80,0xb, -0xa, 0x5c,0x9e,0x54,0x0, 0x5, 0x7c,0xab,0x7a,0xc1,0x3d,0x7a,0xa1,0x26,0x80,0xf, -0xe5,0x26,0x12,0x2f,0xf7,0xbe,0x34,0x1, 0x4a,0x8, 0x2, 0xb, 0x90,0x5, 0x26,0xe5, -0x3d,0xbe,0xb1,0x26,0x18,0xea,0xbe,0x90,0x2, 0x28,0x9, 0xe5,0x39,0xbe,0xb0,0x2, -0x28,0x2, 0xb, 0xd0,0x4c,0xff,0x68,0x4, 0xa, 0x3e,0x80,0xa, 0xa, 0x3e,0x9, 0x53, -0x31,0x31,0xbc,0x5d,0x50,0x4, 0x19,0xd3,0x31,0x31,0x4c,0xdd,0x78,0xa, 0xa, 0x3e, -0x12,0x8f,0xd9,0x28,0x3, 0x7e,0xd0,0x1, 0xbe,0xd0,0x2, 0x50,0xe, 0xa, 0x3e,0x9, -0x73,0x31,0x31,0xbe,0x70,0x4, 0x28,0x3, 0x7e,0xd0,0x2, 0x7c,0xbd,0xda,0x3b,0x22, -0x7e,0x71,0x26,0x12,0x2b,0x76,0x9e,0x34,0x0, 0x21,0x22,0x7e,0x60,0x1, 0x1, 0xbe, -0x75,0x3b,0x0, 0x75,0x3c,0x0, 0x22,0x3e,0x24,0x3e,0x24,0x3e,0x24,0x3e,0x24,0x3e, -0x24,0x3e,0x24,0x3e,0x24,0x22,0xca,0x79,0x7c,0xf7,0x7c,0xeb,0x12,0x8f,0x6f,0xac, -0x3f,0x2e,0x14,0x30,0xcd,0x74,0x9, 0x12,0x1e,0x1d,0x7e,0x30,0x9, 0xac,0x3f,0x7d, -0x31,0x2e,0x34,0x30,0xcd,0x12,0x8f,0x25,0x12,0x8f,0xd1,0x19,0xb3,0x31,0x98,0x19, -0xb3,0x30,0xc3,0x7c,0xbe,0x91,0x8b,0x60,0x5, 0x7e,0x70,0x2, 0x80,0x2, 0x6c,0x77, -0xa, 0x2f,0x19,0x72,0x31,0x27,0x7c,0xbf,0x7e,0x70,0x1, 0x12,0x45,0xcc,0x60,0x8, -0x74,0x2, 0xa, 0x3f,0x19,0xb3,0x31,0x27,0xa, 0x4f,0x9, 0xb4,0x31,0x27,0x70,0x34, -0x74,0x9, 0xac,0xbf,0x49,0x25,0x31,0x3b,0xbe,0x24,0x0, 0xa0,0x40,0x20,0x7e,0x73, -0x38,0x50,0xa, 0x7, 0x7e,0x14,0x1, 0x0, 0xad,0x10,0x7d,0x31,0x9e,0x34,0x0, 0xa0, -0xbd,0x23,0x38,0xa, 0x49,0x55,0x31,0x3d,0xbe,0x54,0x0, 0xa0,0x50,0x6, 0x74,0x2, -0x19,0xb4,0x31,0x27,0xe4,0x19,0xb4,0x30,0xb8,0x19,0xb4,0x31,0x31,0x9, 0xb4,0x31, -0x27,0xb4,0x2, 0x6, 0x74,0xf, 0x19,0xb4,0x30,0xab,0x9, 0xb4,0x30,0xab,0x60,0x5, -0x12,0x8f,0xba,0x80,0x1, 0xe4,0xda,0x79,0x22,0x7c,0x5b,0x74,0x9, 0xac,0xb5,0x9, -0x75,0x1a,0xe3,0x5e,0x70,0xf, 0xa, 0x17,0x9, 0xb1,0x1b,0xed,0xbe,0x70,0xa, 0x40, -0x2, 0xe4,0x22,0x70,0x4, 0x7c,0xb5,0x81,0xa6,0xb4,0x2, 0x5, 0x7c,0xb5,0x2, 0x8b, -0xf8,0xe4,0x22,0xca,0xf8,0x7c,0x3b,0x7e,0x23,0x1c,0x47,0xbe,0x20,0x2, 0x50,0x3, -0xc3,0x80,0x51,0x74,0x9, 0xac,0xb3,0x49,0x45,0x31,0x3b,0x49,0x5, 0x31,0x3d,0x6c, -0x22,0x80,0x38,0x7e,0x70,0x9, 0xac,0x72,0x9, 0xf3,0x1a,0xe3,0x5e,0xf0,0xf, 0xbc, -0x3f,0x68,0x26,0xa, 0x2f,0x9, 0xb2,0x31,0x27,0xbe,0xb0,0x2, 0x68,0x1b,0x49,0x23, -0x1a,0xdf,0x7d,0x34,0xb1,0xe7,0x58,0x11,0x74,0x9, 0xac,0xb2,0x49,0x25,0x1a,0xe1, -0x7d,0x30,0xb1,0xe7,0x58,0x3, 0xd3,0x80,0xb, 0xb, 0x20,0x7e,0x73,0x1c,0x47,0xbc, -0x72,0x38,0xc0,0xc3,0xda,0xf8,0x22,0x9d,0x32,0x12,0x20,0x54,0xbe,0x34,0x3, 0x0, -0x22,0xca,0x7b,0xca,0x6b,0xca,0x5b,0xca,0x4b,0xca,0x2b,0xca,0x1b,0xca,0xb, 0xc0, -0xd0,0xc0,0x83,0xc0,0x82,0x12,0x5f,0xfa,0xd0,0x82,0xd0,0x83,0xd0,0xd0,0xda,0xb, -0xda,0x1b,0xda,0x2b,0xda,0x4b,0xda,0x5b,0xda,0x6b,0xda,0x7b,0x32,0xca,0xb8,0xca, -0x39,0xa9,0x31,0xe5,0x6, 0xa9,0xd5,0xea,0xa9,0xc5,0xea,0xa9,0x30,0xe5,0x42,0x7e, -0xb3,0x1c,0xda,0xb4,0x1, 0x20,0x7e,0x37,0x36,0x37,0xbe,0x34,0x75,0x30,0x50,0x6, -0xb, 0x34,0x7a,0x37,0x36,0x37,0x7e,0x37,0x36,0x33,0xbe,0x34,0x75,0x30,0x50,0x6, -0xb, 0x34,0x7a,0x37,0x36,0x33,0xa9,0xd0,0x9e,0xa9,0xd4,0x9e,0x5, 0x6b,0x5, 0x6b, -0x7e,0x73,0x36,0x35,0xbe,0x71,0x6b,0x38,0x2, 0xd2,0x19,0xa9,0xd0,0x9e,0xa9,0xd7, -0x9e,0xa9,0x34,0xe5,0x5, 0xa9,0xc4,0xcd,0xc2,0x95,0xa9,0x32,0xe5,0x3, 0xa9,0xc2, -0xcd,0xa9,0x33,0xe5,0x3, 0xa9,0xc3,0xcd,0xa9,0x37,0xe5,0x3, 0xa9,0xc7,0xcd,0xa9, -0x36,0xe5,0x3, 0xa9,0xc6,0xcd,0xda,0x39,0xda,0xb8,0x32,0xe5,0x9a,0x60,0x5, 0xd2, -0x9c,0xa9,0xd6,0xdf,0x22,0xc2,0x9a,0xa9,0xd4,0xa6,0xc2,0x88,0xd2,0xa8,0x22,0x7e, -0x14,0xd7,0xe8,0x7e,0x4, 0x0, 0xff,0x7e,0x34,0x47,0x52,0x7e,0x24,0x55,0x50,0x79, -0x30,0x0, 0x2, 0x1b,0xa, 0x20,0x7e,0x34,0x45,0x20,0x7e,0x24,0x41,0x44,0x79,0x30, -0x0, 0x6, 0x79,0x20,0x0, 0x4, 0x7e,0x34,0x99,0x33,0x7e,0x24,0x66,0xcc,0x79,0x30, -0x0, 0xa, 0x79,0x20,0x0, 0x8, 0x7e,0x34,0x41,0x47,0x7e,0x24,0x46,0x4c,0x79,0x30, -0x0, 0xe, 0x79,0x20,0x0, 0xc, 0x22,0xa9,0xd0,0xce,0xa2,0x3, 0xa9,0x95,0xc9,0x22, -0xa9,0xc6,0xeb,0xa9,0xd6,0xac,0xa9,0xd6,0xec,0xd2,0x86,0xa9,0xc2,0xeb,0xa9,0xd2, -0xac,0xa9,0xd2,0xec,0xd2,0x82,0x22,0x75,0x9a,0x2f,0xa9,0xd1,0x99,0xd2,0x9c,0xa9, -0xd6,0xdf,0x22,0xc2,0x8e,0x43,0x89,0x20,0x75,0x8d,0x1, 0x75,0x8b,0x0, 0xd2,0x8e, -0xd2,0xab,0x22,0x75,0xb7,0x0, 0x75,0xb8,0x0, 0x75,0xf7,0x0, 0x75,0xf8,0x0, 0xa9, -0xd0,0xb7,0xd2,0xb8,0xa9,0xd5,0xb7,0xd2,0xbd,0xa9,0xd0,0xf7,0xd2,0xf8,0xa9,0xc1, -0xb7,0xc2,0xb9,0xa9,0xc3,0xb7,0xc2,0xbb,0xa9,0xc6,0xb7,0xc2,0xbe,0x22,0x75,0xe7, -0x6b,0xe1,0x63,0xe4,0x6d,0x33,0x7e,0x24,0x0, 0xff,0x7a,0x1b,0xb0,0x75,0xe9,0xff, -0x80,0xfe,0xa9,0xd0,0x99,0xa9,0xc6,0xdf,0x22,0xa2,0x3, 0xa9,0x97,0xc1,0xa2,0x3, -0xa9,0x95,0xc1,0xa2,0x3, 0xa9,0x97,0xc2,0xa2,0x3, 0xa9,0x96,0xc2,0x22,0x7e,0x37, -0x36,0x31,0xb, 0x34,0x7a,0x37,0x36,0x31,0xbe,0x34,0xff,0x0, 0x40,0x8, 0x7e,0x34, -0xff,0x0, 0x7a,0x37,0x36,0x31,0x22,0x7f,0x70,0xd2,0xc9,0x75,0xf2,0x30,0x75,0xf3, -0x80,0x75,0xf4,0xc, 0x75,0xf5,0x1, 0x6c,0xaa,0xe5,0xf5,0x54,0x80,0xb4,0x80,0xf9, -0xe5,0xf6,0xa, 0x4a,0x7f,0x17,0x2d,0x34,0x7a,0x1b,0xb0,0xb, 0xa0,0xbe,0xa0,0xd, -0x40,0xe7,0xc2,0xc9,0x22,0xa9,0xd5,0xca,0xa9,0xd1,0xea,0xa9,0xc1,0xea,0x74,0xa5, -0x7a,0xb3,0x36,0x56,0x22,0x7c,0xab,0x7f,0x70,0x9f,0x11,0x30,0x3, 0x22,0x6c,0x33, -0x80,0x1a,0xa, 0x3, 0x7f,0x67,0x2d,0xd0,0x7e,0x6b,0xb0,0x7e,0x68,0x0, 0x1, 0x60, -0x5, 0x2f,0x66,0x14,0x78,0xfb,0x4d,0x3d,0x4d,0x2c,0xb, 0x30,0xbc,0xa3,0x38,0xe2, -0x22,0xca,0xc8,0xca,0x79,0x7f,0x70,0x7e,0xd, 0x2b,0x7e,0x34,0x0, 0x48,0x74,0xff, -0x12,0x20,0x12,0x80,0x62,0xa, 0x1c,0x7e,0x1d,0x27,0x2d,0x31,0x7e,0x1b,0x30,0xa, -0x33,0x12,0x66,0x29,0x7c,0x3b,0xa, 0x33,0x11,0xbf,0x7c,0xa5,0x7a,0xa1,0x2f,0x11, -0xa2,0x7c,0xb2,0x60,0x5, 0x3e,0x4, 0x14,0x78,0xfb,0x6e,0x4, 0xff,0xff,0x7e,0x70, -0x6, 0xac,0x7a,0x11,0x8c,0xbc,0xec,0x38,0xcc,0xa, 0x3c,0x2d,0x3f,0x7d,0x2e,0x7e, -0x1b,0x30,0xa, 0x53,0x31,0x5a,0xf5,0x2f,0x2e,0x30,0x24,0x11,0xa2,0x7c,0xb2,0x60, -0x5, 0x3e,0x4, 0x14,0x78,0xfb,0x6e,0x4, 0xff,0xff,0x7e,0x71,0x2f,0x74,0x6, 0xac, -0x7b,0x11,0x8c,0xbc,0xfc,0x38,0xd2,0xda,0x79,0xda,0xc8,0x22,0xa, 0x29,0x2d,0x32, -0x3e,0x34,0x7e,0x2d,0x2b,0x2d,0x53,0xb, 0x2a,0x30,0x5d,0x30,0x1b,0x2a,0x30,0xb, -0xc0,0x22,0xa, 0x43,0x1e,0x44,0x1e,0x44,0x1e,0x44,0x1e,0x44,0x7a,0x91,0x30,0xa, -0x33,0x7e,0x24,0x0, 0x10,0x12,0x1d,0x4a,0x7c,0x25,0x7e,0x4, 0x0, 0x1, 0x22,0x7e, -0x24,0x0, 0x3, 0x2, 0x1d,0x4a,0xca,0x79,0x7f,0x70,0x7c,0xf7,0x7c,0xeb,0x6c,0x33, -0x80,0x38,0xa, 0x3, 0x7e,0x1d,0x27,0x2d,0x30,0x7e,0x1b,0x20,0xa, 0x32,0x12,0x66, -0x29,0x7c,0x2b,0xa, 0x32,0x11,0xbf,0x7c,0x65,0x7a,0x61,0x30,0xa, 0x52,0x7e,0x44, -0x0, 0x3, 0x8d,0x54,0xf5,0x2f,0x7e,0x44,0x0, 0x1, 0x60,0x5, 0x3e,0x44,0x14,0x78, -0xfb,0x7e,0x70,0x2, 0x7c,0xb6,0xac,0xb7,0x31,0x4a,0xbc,0xf3,0x38,0xc4,0x6c,0x33, -0x80,0x31,0xa, 0x33,0x2d,0x3f,0x7d,0x2e,0x7e,0x1b,0x20,0xa, 0x52,0x31,0x5a,0x7c, -0xab,0x7a,0xa1,0x30,0xa, 0x32,0x7e,0x24,0x0, 0xc, 0x12,0x1d,0x4a,0x7c,0xb5,0xf5, -0x2f,0x7e,0x44,0x0, 0x1, 0x60,0x5, 0x3e,0x44,0x14,0x78,0xfb,0x7e,0x70,0x2, 0xac, -0xa7,0x31,0x4a,0xbc,0xe3,0x38,0xcb,0xda,0x79,0x22,0x7e,0x1d,0x2b,0x2d,0x35,0xb, -0x1a,0x0, 0x4d,0x4, 0x1b,0x1a,0x0, 0xb, 0x30,0x22,0x7e,0x44,0x0, 0xc, 0x8d,0x54, -0x2e,0x54,0x0, 0x3, 0x22,0x7c,0xab,0x4c,0xaa,0x78,0x3, 0x74,0x10,0x22,0x7c,0xba, -0xc4,0x3, 0x54,0xf8,0x22,0xca,0x69,0xca,0xf8,0x6d,0x0, 0x7d,0x40,0x7e,0x33,0x1c, -0xe0,0xa, 0xd3,0x7e,0xb3,0x38,0x9c,0xb4,0xff,0x2c,0x7e,0x78,0x13,0x6c,0x6c,0xff, -0x80,0x18,0x7e,0x70,0x2, 0xac,0x7f,0x49,0x23,0x13,0xf0,0x7f,0x57,0x2d,0xb3,0xb, -0x5a,0x50,0x9d,0x52,0x59,0x53,0x13,0xae,0xb, 0xf0,0xbc,0x3f,0x38,0xe4,0x7e,0xd3, -0x38,0x9a,0x6d,0xdd,0x80,0xc, 0x7e,0x78,0x13,0xf0,0x7e,0x23,0x38,0x9a,0xa, 0x62, -0x1b,0x64,0x6c,0x22,0x80,0x38,0x6c,0xff,0x80,0x28,0xa, 0x5f,0x7d,0xc5,0x2d,0xc0, -0x3e,0xc4,0x49,0xcc,0x13,0xf0,0x2d,0x5d,0x3e,0x54,0x7f,0x17,0x2d,0x35,0xb, 0x1a, -0xb0,0x7d,0x3c,0x9d,0x3b,0x12,0x20,0x54,0x7d,0xa3,0xbd,0x4a,0x58,0x2, 0x7d,0x4a, -0xb, 0xf0,0xbc,0x3f,0x38,0xd4,0xa, 0x53,0x2d,0x5, 0x2d,0xd5,0xb, 0x20,0xbc,0xd2, -0x38,0xc4,0x7d,0x34,0xda,0xf8,0xda,0x69,0x22,0xca,0xf8,0x6d,0x44,0x7e,0x33,0x1c, -0xe0,0x7e,0x23,0x38,0x9b,0xa, 0x32,0x7e,0x23,0x1c,0xdf,0xa, 0x22,0x2d,0x23,0xa, -0x33,0xad,0x32,0x7d,0x3, 0xa, 0x33,0x2d,0x30,0x7e,0xb3,0x38,0x9c,0xb4,0xff,0x30, -0x7e,0x78,0x13,0x6c,0x6c,0xff,0x80,0x22,0xa, 0x2f,0x2d,0x20,0x3e,0x24,0x7e,0x6f, -0x3, 0xfa,0x2d,0xd2,0xb, 0x6a,0xd0,0x74,0x2, 0xac,0xbf,0x7f,0x57,0x2d,0xb5,0xb, -0x5a,0x20,0x9d,0x2d,0x59,0x25,0x13,0xae,0xb, 0xf0,0xbc,0x3f,0x38,0xda,0x80,0x4, -0x7d,0x53,0x51,0x9c,0x6c,0xff,0x80,0x2b,0xa, 0x5f,0x2d,0x50,0x3e,0x54,0x7e,0x1f, -0x3, 0xfa,0x2d,0x35,0xb, 0x1a,0xd0,0x74,0x2, 0xac,0xbf,0x7f,0x17,0x2d,0x35,0xb, -0x1a,0xc0,0x7d,0x3d,0x9d,0x3c,0x12,0x20,0x54,0x7d,0xb3,0xbd,0x4b,0x58,0x2, 0x7d, -0x4b,0xb, 0xf0,0xbc,0x3f,0x38,0xd1,0x7d,0x34,0xda,0xf8,0x22,0x3e,0x54,0x7e,0x7f, -0x3, 0xfa,0x2d,0xf5,0x22,0x7e,0x53,0x1c,0xe0,0x7e,0x43,0x1c,0xdf,0x7c,0x34,0xac, -0x35,0x7e,0x37,0x1a,0xd2,0x51,0xfa,0x6d,0x0, 0x80,0x12,0x7d,0x50,0x51,0x9c,0xb, -0x7a,0x50,0x6e,0x54,0xff,0xff,0xb, 0x54,0x1b,0x7a,0x50,0xb, 0x4, 0xbd,0x10,0x38, -0xea,0x7e,0xf, 0x3, 0xfa,0x7a,0x17,0x2, 0x93,0x7e,0x14,0x9, 0x14,0x7a,0x17,0x2, -0x95,0x7e,0x14,0x9, 0x14,0x7a,0x17,0x2, 0x97,0x7a,0x43,0x2, 0x8f,0x7a,0x53,0x2, -0x90,0x7e,0x8, 0x2, 0x8f,0x7c,0xb7,0x2, 0x16,0xe2,0xa9,0xd1,0xcb,0xe4,0x2, 0x0, -0xe, 0xca,0x79,0x7f,0x51,0x7f,0x60,0x7e,0x73,0x1c,0xe6,0xa, 0x37,0x7e,0x53,0x1c, -0xe5,0xa, 0x75,0x2d,0x73,0xa, 0x3f,0x3e,0x34,0xca,0x39,0x7e,0x1d,0x28,0x7f,0x6, -0x12,0x1f,0xed,0x1b,0xfd,0x7e,0xb3,0x1d,0x83,0xb4,0x1, 0x22,0x6c,0x77,0x80,0x1a, -0x7e,0x90,0x2, 0xac,0x97,0x7f,0x5, 0x2d,0x14,0xb, 0xa, 0x50,0x7f,0x6, 0x2d,0x14, -0xb, 0xa, 0x20,0x9d,0x25,0x1b,0xa, 0x20,0xb, 0x70,0xbc,0xf7,0x38,0xe2,0xda,0x79, -0x22,0x7e,0x47,0x1a,0xd4,0x6d,0xff,0x9d,0xf4,0x6c,0x77,0x80,0x64,0x30,0x0, 0x2e, -0x7e,0x50,0x2, 0xac,0x57,0x49,0xe2,0x5, 0xa8,0x49,0x12,0x4, 0x0, 0xbd,0x14,0x8, -0x11,0x7e,0xb3,0x16,0xc9,0xb4,0x1, 0x16,0x7d,0x4, 0x2d,0xe, 0x59,0x2, 0x5, 0xa8, -0x80,0xc, 0xbd,0x1f,0x58,0x8, 0x7d,0x5e,0x9d,0x54,0x59,0x52,0x5, 0xa8,0x30,0x2, -0x2e,0x7e,0x50,0x2, 0xac,0x57,0x49,0xe2,0x6, 0x12,0x49,0x12,0x4, 0x6a,0xbd,0x14, -0x8, 0x11,0x7e,0xb3,0x16,0xc9,0xb4,0x1, 0x16,0x7d,0x4, 0x2d,0xe, 0x59,0x2, 0x6, -0x12,0x80,0xc, 0xbd,0x1f,0x58,0x8, 0x7d,0x5e,0x9d,0x54,0x59,0x52,0x6, 0x12,0xb, -0x70,0x7e,0x63,0x1c,0xe6,0xa, 0x56,0x7e,0x63,0x1c,0xe5,0xa, 0x26,0x2d,0x25,0xa, -0x57,0xbd,0x52,0x48,0x88,0x22,0xca,0xf8,0x7e,0xd4,0x7f,0xff,0x7d,0x2d,0x7d,0x1d, -0x6d,0xcc,0x7d,0x4c,0x7d,0x3c,0x6c,0xff,0x6c,0x11,0x7e,0x78,0x4, 0xd4,0x7e,0x58, -0x5, 0x3e,0xe4,0x7a,0xb3,0x9, 0x12,0x7a,0xb3,0x9, 0x13,0x7a,0xb3,0x18,0x91,0x7a, -0xb3,0x18,0x93,0x7a,0xb3,0x18,0x92,0x7a,0xb3,0x18,0x94,0x6c,0x0, 0x80,0x6d,0xb1, -0x1f,0xb, 0x4a,0x50,0xbd,0x52,0x58,0x2, 0x7d,0x25,0xbd,0x54,0x8, 0x2, 0x7d,0x45, -0x74,0x2, 0xac,0xb0,0x7f,0x45,0x2d,0x95,0xb, 0x4a,0x50,0xbd,0x5d,0x58,0x2, 0x7d, -0xd5,0xbd,0x5c,0x8, 0x2, 0x7d,0xc5,0xb1,0x1f,0xb, 0x4a,0x50,0x7e,0x87,0x1c,0xc5, -0x7e,0x94,0x0, 0x3, 0xad,0x98,0xbd,0x59,0x8, 0x2, 0xb, 0xf0,0xb1,0x1f,0xb, 0x4a, -0x50,0xbe,0x57,0x3a,0x32,0x8, 0xb, 0x7e,0xb3,0x18,0x92,0x4, 0x7a,0xb3,0x18,0x92, -0x80,0x18,0xb1,0x1f,0xb, 0x4a,0x90,0x6d,0x55,0x9e,0x57,0x3a,0x32,0xbd,0x95,0x58, -0x9, 0x7e,0xb3,0x18,0x94,0x4, 0x7a,0xb3,0x18,0x94,0xb, 0x0, 0x7e,0xb3,0x1c,0xe6, -0xbc,0xb0,0x38,0x8b,0x7a,0x27,0x9, 0x6, 0x7a,0x47,0x9, 0xa, 0x7a,0xf3,0x9, 0x13, -0x7a,0xc7,0x9, 0x10,0x7a,0xd7,0x9, 0xe, 0x7e,0xb3,0x1c,0xe6,0x7e,0x0, 0x2, 0xac, -0xb0,0x2d,0xf5,0x6c,0x0, 0x80,0x4d,0x74,0x2, 0xac,0xb0,0x7f,0x67,0x2d,0xd5,0xb, -0x6a,0xd0,0xbd,0xd1,0x58,0x2, 0x7d,0x1d,0xbd,0xd3,0x8, 0x2, 0x7d,0x3d,0x7e,0xa7, -0x1c,0xc3,0x7e,0xb4,0x0, 0x3, 0xad,0xba,0xbd,0xdb,0x8, 0x2, 0xb, 0x10,0xbe,0xd7, -0x3a,0x32,0x8, 0xb, 0x7e,0xb3,0x18,0x91,0x4, 0x7a,0xb3,0x18,0x91,0x80,0x13,0x6d, -0x55,0x9e,0x57,0x3a,0x32,0xbd,0xd5,0x58,0x9, 0x7e,0xb3,0x18,0x93,0x4, 0x7a,0xb3, -0x18,0x93,0xb, 0x0, 0x7e,0xb3,0x1c,0xe5,0xbc,0xb0,0x38,0xab,0x7a,0x17,0x9, 0x4, -0x7a,0x37,0x9, 0x8, 0x7a,0x13,0x9, 0x12,0xbd,0x12,0x58,0x2, 0x7d,0x21,0x7a,0x27, -0x9, 0x0, 0xbd,0x43,0x58,0x2, 0x7d,0x43,0x7a,0x47,0x9, 0x2, 0xda,0xf8,0x22,0x74, -0x2, 0xac,0xb0,0x7f,0x47,0x2d,0x95,0x22,0x74,0xfe,0x7a,0xb3,0x35,0x34,0xe4,0x7a, -0xb3,0x2e,0x25,0x22,0x7d,0x13,0x7e,0x37,0x3a,0x7a,0xbd,0x31,0x50,0x1a,0x7e,0x37, -0x3a,0x7c,0xbd,0x31,0x28,0x12,0x7e,0x37,0x3a,0x7e,0xbd,0x32,0x50,0xa, 0x7e,0x37, -0x3a,0x80,0xbd,0x32,0x28,0x2, 0xe4,0x22,0x74,0x1, 0x22,0x7c,0xbd,0x7c,0x7e,0x2, -0x2b,0x76,0x7e,0x73,0x1d,0x93,0x7a,0x73,0x35,0x73,0x7e,0x73,0x1d,0xa3,0x7a,0x73, -0x35,0x63,0x7e,0x73,0x1d,0xa4,0x7a,0x73,0x35,0x62,0x7e,0x73,0x1d,0x98,0x7a,0x73, -0x35,0x64,0x7e,0x73,0x1d,0xee,0x7a,0x73,0x35,0x74,0x22,0x7e,0x71,0x5a,0x74,0x9, -0xac,0x7b,0xe5,0x5b,0xa, 0xcb,0x2d,0xc3,0x22,0x7e,0x71,0x51,0x74,0x9, 0xac,0x7b, -0xe5,0x52,0xa, 0xcb,0x2d,0xc3,0x22,0x7e,0x71,0x48,0x74,0x9, 0xac,0x7b,0xe5,0x49, -0xa, 0xcb,0x2d,0xc3,0x22,0x7e,0x71,0x3f,0x74,0x9, 0xac,0x7b,0xe5,0x40,0xa, 0xcb, -0x2d,0xc3,0x22,0xa, 0x2b,0xa, 0x3c,0x2d,0x32,0x7e,0xa3,0x1c,0xe0,0xa, 0xca,0x1b, -0xc4,0xbd,0x3c,0x22,0x7e,0x34,0x0, 0xa, 0xe4,0x12,0x20,0x12,0x7e,0x8, 0x17,0x6, -0x7e,0x34,0x0, 0xb4,0x74,0xff,0x22,0xa, 0xcb,0x2d,0xc2,0x19,0x7c,0x3, 0x32,0x22, -0xa, 0x3e,0x7d,0x53,0xb, 0x56,0xa, 0x2c,0x22,0xa, 0xcd,0xb, 0xc6,0xe5,0x2c,0xa, -0x4b,0x22,0x9d,0x32,0x12,0x20,0x54,0x7c,0xb7,0x22,0x7c,0xbd,0xa, 0x3e,0xb, 0x34, -0x2, 0x2b,0x76,0x7c,0xbd,0xa, 0x3e,0x1b,0x34,0x2, 0x2b,0x76,0x74,0x1, 0x7a,0xb3, -0x1d,0x83,0x7a,0xb3,0x1d,0xa1,0x22,0x7e,0x8, 0x1c,0xdf,0x12,0xd, 0x0, 0x7e,0xb3, -0x1d,0x7c,0x7e,0x70,0x1, 0x22,0x7e,0x34,0x0, 0xc, 0x8d,0x53,0x7e,0x14,0x0, 0xc, -0xad,0x15,0x22,0x7e,0x24,0x0, 0x3, 0x8d,0x2, 0x7e,0x14,0x0, 0xc, 0xad,0x10,0x22, -0xa, 0x5d,0x1b,0x54,0xa, 0x3e,0x22,0xa, 0x5d,0xb, 0x54,0xa, 0x3e,0x22,0xa, 0x4b, -0xe5,0x2c,0xa, 0xcb,0x2d,0xc4,0x7d,0x3c,0x7c,0xb7,0x22,0xa, 0x2b,0xe5,0x2c,0xa, -0x3b,0x2d,0x32,0x7e,0xa3,0x1c,0xdf,0x22,0x7e,0x18,0x5, 0xa8,0x7a,0x1f,0x6, 0x7c, -0x7e,0x18,0x4, 0x0, 0x22,0x7a,0x1d,0x2b,0xe5,0x26,0x7c,0x7f,0x7e,0x8, 0x1d,0x33, -0x22,0x7e,0x73,0x1d,0x7d,0xa, 0x2d,0x19,0x72,0x3, 0x2f,0x22,0xa, 0x37,0x7e,0x53, -0x1c,0xdf,0xa, 0x25,0x2d,0x23,0x22,0xa, 0x3b,0xa, 0xcc,0x2d,0xc3,0x7d,0x3c,0x7c, -0xb7,0x22,0x7e,0x70,0x2, 0xac,0x7f,0x9, 0xb3,0x18,0x95,0x22,0x7e,0x30,0x5, 0xac, -0x3f,0x2e,0x14,0x18,0xd1,0x22,0x7e,0xb3,0x34,0x71,0x4, 0x7a,0xb3,0x34,0x71,0x22, -0x7e,0x24,0x1, 0xf4,0x8d,0x32,0xbe,0x70,0x7, 0x22,0x74,0x40,0x7a,0xb3,0x1d,0xa4, -0x22,0x7e,0x73,0x1d,0x98,0x7a,0x73,0x35,0x64,0x22,0x7e,0x73,0x1d,0xa3,0x7a,0x73, -0x35,0x63,0x22,0x7e,0x73,0x1d,0xa4,0x7a,0x73,0x35,0x62,0x22,0x8d,0x23,0x7d,0x32, -0x2e,0x34,0x0, 0x24,0x22,0x7e,0x34,0x0, 0xc, 0xe4,0x2, 0x20,0x12,0x7e,0xf, 0x3, -0xd9,0x79,0x30,0x0, 0x9e,0x22,0xa, 0x57,0x2e,0x54,0x0, 0x8, 0xf5,0xcc,0x22,0x74, -0x2, 0xac,0xbe,0x9, 0xd5,0x18,0x95,0x22,0x7e,0x37,0x36,0x37,0xbe,0x34,0x55,0xf0, -0x22,0x7e,0x34,0x0, 0x1, 0x7a,0x37,0x1a,0xd2,0x22,0xb, 0xa, 0x30,0x2d,0x32,0x1b, -0xa, 0x30,0x22,0x6d,0x33,0xe4,0x6c,0x55,0x2, 0x1c,0x31,0xa, 0x4b,0xe5,0x2c,0xa, -0x5b,0x9d,0x54,0x22,0x7e,0x37,0x16,0xc7,0x7a,0x37,0x22,0xae,0x22,0x7e,0x34,0xe, -0x3c,0x7a,0x37,0x23,0x10,0x22,0x7d,0x32,0x74,0xfa,0x2, 0x17,0xcd,0x7e,0x18,0x1d, -0x56,0x7a,0x1d,0x27,0x22,0x12,0x20,0x12,0x7e,0xb3,0x1c,0xe5,0x22,0x7e,0x73,0x2, -0xd4,0xbe,0x70,0x6, 0x22,0x7e,0xb3,0x2, 0xd4,0xbe,0xb0,0x1, 0x22,0x12,0x0, 0xe, -0x7e,0x1f,0x13,0x64,0x22,0x7e,0x71,0x24,0x74,0x9, 0xac,0xb7,0x22,0x12,0x1c,0xa9, -0xe4,0x2, 0x0, 0xe, 0xe4,0x12,0x1d,0x14,0x2, 0x1c,0xe3,0xff,0xff,0xff,0xff,0xff, diff --git a/drivers/input/touchscreen/ft5x46/ft5x46_ts.c b/drivers/input/touchscreen/ft5x46/ft5x46_ts.c index 5e2815b33b65..4b243debab67 100644 --- a/drivers/input/touchscreen/ft5x46/ft5x46_ts.c +++ b/drivers/input/touchscreen/ft5x46/ft5x46_ts.c @@ -16,9 +16,6 @@ #include #include "ft8716_pramboot.h" -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE -#include <../xiaomi/xiaomi_touch.h> -#endif /* #define FT5X46_DEBUG_PERMISSION */ #define FT5X46_APK_DEBUG_CHANNEL @@ -192,9 +189,6 @@ static bool lcd_need_reset; static unsigned char proc_operate_mode = FT5X46_PROC_UPGRADE; static struct proc_dir_entry *ft5x46_proc_entry; #endif -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_SENSOR -static int ft5x46_palm_enable(struct ft5x46_data *ft5x46, int on); -#endif struct ft5x46_packet { u8 magic1; u8 magic2; @@ -1267,7 +1261,6 @@ static int ft8716_load_firmware(struct ft5x46_data *ft5x46, u32 check_off = 0x20; u32 start_addr = 0x00; u8 packet_buf[16 + FT5X0X_PACKET_LENGTH]; - u8 *tp_maker = NULL; const struct firmware *fw; int packet_num; @@ -1306,10 +1299,7 @@ static int ft8716_load_firmware(struct ft5x46_data *ft5x46, ft8716_reset_firmware(ft5x46); return error; } - - if (tp_maker == NULL) - dev_err(ft5x46->dev, "fail to alloc vendor name memory\n"); - + update_hardware_info(TYPE_TP_MAKER, ft5x46->lockdown_info[0] - 0x30); ft5x46->lockdown_info_acquired = true; wake_up(&ft5x46->lockdown_info_acquired_wq); } @@ -1773,18 +1763,7 @@ static irqreturn_t ft5x46_interrupt(int irq, void *dev_id) u8 val = 0; mutex_lock(&ft5x46->mutex); -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_SENSOR - if (ft5x46->palm_enabled) { - error = ft5x46_read_byte(ft5x46, 0x9B, &val); - if (error) { - dev_err(ft5x46->dev, "Error reading register 0x9B\n"); - goto out; - } - update_palm_sensor_value(!!val); - if (val) - goto out; - } -#endif + if (ft5x46->wakeup_mode && ft5x46->in_suspend) { error = ft5x46_read_byte(ft5x46, 0xD0, &val); if (error) @@ -1831,13 +1810,6 @@ int ft5x46_suspend(struct ft5x46_data *ft5x46) ft5x46_clear_touch_event(ft5x46); mutex_unlock(&ft5x46->mutex); -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_SENSOR - if (ft5x46->palm_enabled) { - update_palm_sensor_value(0); - ft5x46_palm_enable(ft5x46, 0); - ft5x46->palm_enabled = false; - } -#endif cancel_delayed_work_sync(&ft5x46->noise_filter_delayed_work); cancel_delayed_work_sync(&ft5x46->lcd_esdcheck_work); @@ -1906,12 +1878,6 @@ int ft5x46_resume(struct ft5x46_data *ft5x46) mutex_lock(&ft5x46->mutex); ft5x46->in_suspend = false; -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_SENSOR - if (ft5x46->palm_enabled && !ft5x46->palm_sensor_changed) { - ft5x46_palm_enable(ft5x46, 1); - ft5x46->palm_sensor_changed = true; - } -#endif schedule_delayed_work(&ft5x46->lcd_esdcheck_work, msecs_to_jiffies(FT5X46_ESD_CHECK_PERIOD)); @@ -1922,6 +1888,7 @@ int ft5x46_resume(struct ft5x46_data *ft5x46) #ifdef CONFIG_TOUCHSCREEN_FT5X46P_PROXIMITY wake_up(&ft5x46->resume_wq); #endif + return 0; } EXPORT_SYMBOL_GPL(ft5x46_resume); @@ -2740,54 +2707,6 @@ static ssize_t ft5x46_lcd_esd_test(struct device *dev, return error ? : count; } -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE -static struct xiaomi_touch_interface xiaomi_touch_interfaces; -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_SENSOR -static int ft5x46_palm_enable(struct ft5x46_data *ft5x46, int on) -{ - int retval; - unsigned char enable; - unsigned char palm_on = 0x05; - unsigned char palm_off = 0x00; - - enable = on > 0 ? 1 : 0; - - dev_info(ft5x46->dev, "%s: on:%d\n", __func__, on); - - if (on) - retval = ft5x46_write_byte(ft5x46, 0x9A, palm_on); - else - retval = ft5x46_write_byte(ft5x46, 0x9A, palm_off); - - if (retval < 0) - return -EINVAL; - - return 0; -} - -static int ft5x46_palmsensor_enable(int on) -{ - struct ft5x46_data *ft5x46 = ft_data; - int ret = 0; - - if (!ft5x46) - return -EINVAL; - ft5x46->palm_enabled = on; - if (ft5x46->in_suspend) { - dev_err(ft5x46->dev, "%s tp has suspended\n", __func__); - ft5x46->palm_sensor_changed = false; - return 0; - } - - ret = ft5x46_palm_enable(ft5x46, on); - if (!ret) - ft5x46->palm_sensor_changed = true; - return ret; -} - -#endif -#endif - /* sysfs */ #ifdef FT5X46_DEBUG_PERMISSION static DEVICE_ATTR(tpfwver, 0666, ft5x46_tpfwver_show, NULL); @@ -4368,17 +4287,6 @@ struct ft5x46_data *ft5x46_probe(struct device *dev, ft5x46->hw_is_ready = false; init_waitqueue_head(&ft5x46->lockdown_info_acquired_wq); schedule_work(&ft5x46->work); - -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE - dev_err(dev, "ft5x46 register touch screen palm_enable\n"); - memset(&xiaomi_touch_interfaces, 0x00, sizeof(struct xiaomi_touch_interface)); -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_SENSOR - xiaomi_touch_interfaces.palm_sensor_write = ft5x46_palmsensor_enable; - xiaomitouch_register_modedata(&xiaomi_touch_interfaces); - ft5x46->tp_class = get_xiaomi_touch_class(); -#endif -#endif - return ft5x46; #ifdef FT5X46_APK_DEBUG_CHANNEL diff --git a/drivers/input/touchscreen/ft5x46/ft8716_pramboot.h b/drivers/input/touchscreen/ft5x46/ft8716_pramboot.h index 90d7c00ed244..39e0fb8e01d6 100644 --- a/drivers/input/touchscreen/ft5x46/ft8716_pramboot.h +++ b/drivers/input/touchscreen/ft5x46/ft8716_pramboot.h @@ -17,219 +17,219 @@ #define FT8716_PRAMBOOT_H unsigned char ft8716_pramboot[] = { - 0x2, 0x7, 0x67, 0xca, 0x39, 0x12, 0xd, 0x28, 0xda, 0x39, 0x32, 0x2, 0x0, 0x3, 0x6d, 0x22, - 0x80, 0x13, 0x75, 0xb5, 0x0, 0xa9, 0x36, 0xb3, 0xfc, 0xa9, 0xc6, 0xb3, 0xe5, 0xb5, 0x7a, 0xb, - 0xb0, 0xb, 0x14, 0xb, 0x24, 0xbd, 0x32, 0x38, 0xe9, 0x22, 0xff, 0x2, 0xb, 0x46, 0xe5, 0x32, - 0xb4, 0xc, 0xf, 0xc2, 0x86, 0xc2, 0x87, 0x7e, 0x34, 0x0, 0x64, 0x12, 0xc, 0x72, 0xd2, 0x86, - 0xd2, 0x87, 0x22, 0x2, 0x0, 0xf9, 0xca, 0x3b, 0x7a, 0xd, 0x8, 0x7f, 0x31, 0xe5, 0x23, 0xb4, - 0x80, 0x2, 0x80, 0x3, 0x2, 0x0, 0xdc, 0x7f, 0x13, 0x5e, 0x34, 0x0, 0x7f, 0x7d, 0x23, 0x7e, - 0x34, 0x0, 0x80, 0x9d, 0x32, 0x7a, 0x35, 0xe, 0x7e, 0x35, 0xc, 0xbe, 0x35, 0xe, 0x38, 0x2, - 0x80, 0x5d, 0x7e, 0x35, 0xe, 0x7a, 0x35, 0x10, 0x7f, 0x13, 0x7e, 0xd, 0x8, 0x12, 0x9, 0x6e, - 0x7e, 0x35, 0xc, 0x9e, 0x35, 0xe, 0x7a, 0x35, 0xc, 0x7e, 0x35, 0xe, 0x6d, 0x22, 0x2f, 0x31, - 0x7e, 0x1d, 0x8, 0x2e, 0x35, 0xe, 0x7a, 0x1d, 0x8, 0x80, 0x27, 0x7e, 0x34, 0x0, 0x80, 0x7a, - 0x35, 0x10, 0x7f, 0x13, 0x7e, 0xd, 0x8, 0x12, 0x9, 0x6e, 0x7e, 0x35, 0xc, 0x9e, 0x34, 0x0, - 0x80, 0x7a, 0x35, 0xc, 0x7e, 0x1d, 0x8, 0x2e, 0x34, 0x0, 0x80, 0x7a, 0x1d, 0x8, 0x2e, 0x38, - 0x0, 0x80, 0x7e, 0x35, 0xc, 0xbe, 0x34, 0x0, 0x80, 0x50, 0xd0, 0x4d, 0x33, 0x68, 0x26, 0x7a, - 0x35, 0x10, 0x7f, 0x13, 0x7e, 0xd, 0x8, 0x12, 0x9, 0x6e, 0x80, 0x19, 0x74, 0x2, 0x12, 0x8, - 0xb8, 0x5e, 0x70, 0xf4, 0x12, 0xa, 0xbd, 0x7e, 0x35, 0xc, 0x7a, 0x35, 0x10, 0x7f, 0x13, 0x7e, - 0xd, 0x8, 0x12, 0x6, 0x42, 0xd3, 0xda, 0x3b, 0x22, 0xa9, 0xc0, 0x93, 0x75, 0x38, 0x0, 0x32, - 0xd, 0x46, 0xf2, 0xb9, 0x32, 0xcf, 0xcd, 0x30, 0xa5, 0x21, 0x5a, 0xde, 0xff, 0x0, 0xff, 0x0, - 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0x7c, 0x6b, 0xc2, 0x2, 0xe5, 0x21, 0x14, 0x78, 0x3, 0x2, 0x2, 0xbf, 0x1b, 0xb1, 0x78, 0x3, - 0x2, 0x2, 0x30, 0x1b, 0xb1, 0x78, 0x3, 0x2, 0x2, 0x7c, 0x1b, 0xb1, 0x78, 0x3, 0x2, 0x2, - 0x8d, 0x1b, 0xb1, 0x78, 0x3, 0x2, 0x2, 0xa6, 0x24, 0xf9, 0x78, 0x3, 0x2, 0x2, 0xbb, 0x24, - 0xaf, 0x78, 0x3, 0x2, 0x3, 0x29, 0x24, 0xfd, 0x68, 0x2d, 0x14, 0x78, 0x3, 0x2, 0x2, 0xc2, - 0x14, 0x78, 0x3, 0x2, 0x2, 0xbf, 0x1b, 0xb2, 0x78, 0x3, 0x2, 0x2, 0xbf, 0x24, 0xda, 0x68, - 0x19, 0x24, 0xe6, 0x68, 0x12, 0x24, 0xeb, 0x68, 0x2e, 0x24, 0xf3, 0x78, 0x3, 0x2, 0x2, 0xbf, - 0x24, 0x77, 0x68, 0x3, 0x2, 0x3, 0x33, 0x2, 0x3, 0x30, 0xbe, 0x60, 0x4, 0x50, 0xc, 0x75, - 0x16, 0x0, 0x7c, 0x16, 0x2e, 0x10, 0x24, 0x7c, 0xb7, 0xa5, 0xf7, 0xa5, 0xbe, 0x0, 0x2, 0x80, - 0x3, 0x2, 0x3, 0x33, 0xd2, 0x2, 0x22, 0x7c, 0xb6, 0x24, 0x0, 0x78, 0x3, 0x2, 0x3, 0x33, - 0x1b, 0xb1, 0x68, 0x1e, 0x14, 0x68, 0x1e, 0x14, 0x68, 0x1e, 0x14, 0x68, 0x1e, 0xb, 0xb2, 0x78, - 0x33, 0x30, 0x1, 0x7, 0x7e, 0x8, 0x0, 0x3e, 0x2, 0x2, 0x4d, 0x7e, 0x8, 0x1, 0x4a, 0x2, - 0x2, 0x4d, 0x2, 0x2, 0xe7, 0x2, 0x2, 0xee, 0x2, 0x3, 0x6, 0xa, 0x27, 0x7e, 0xd, 0x39, - 0xb, 0x16, 0xb, 0xa, 0x30, 0x2d, 0x32, 0x1b, 0xa, 0x30, 0x6d, 0x33, 0x7e, 0xd, 0x39, 0x79, - 0x30, 0x0, 0x6, 0x22, 0x7c, 0xb7, 0x62, 0x16, 0x7e, 0x2d, 0x39, 0x2e, 0x54, 0x0, 0x6, 0xb, - 0x2a, 0x20, 0x7d, 0x12, 0xb, 0x14, 0x1b, 0x2a, 0x10, 0x7e, 0xd, 0x39, 0x2d, 0x12, 0x39, 0x70, - 0x0, 0x8, 0x7e, 0xd, 0x39, 0x69, 0x50, 0x0, 0x4, 0x69, 0x20, 0x0, 0x6, 0xbd, 0x25, 0x50, - 0x3, 0x2, 0x3, 0x33, 0xb2, 0x1, 0x7a, 0xd, 0x33, 0x7e, 0x34, 0x0, 0x2, 0x2, 0x3, 0x25, - 0x7c, 0xb6, 0x1b, 0xb1, 0x68, 0x1d, 0x14, 0x68, 0x1d, 0xb, 0xb1, 0x68, 0x3, 0x2, 0x3, 0x33, - 0x30, 0x1, 0x6, 0x7e, 0x8, 0x0, 0x3e, 0x80, 0x4, 0x7e, 0x8, 0x1, 0x4a, 0x7a, 0xd, 0x39, - 0x2, 0x2, 0xd6, 0x2, 0x2, 0xe7, 0xa, 0x57, 0x6d, 0x44, 0x7e, 0xd, 0x39, 0x69, 0x30, 0x0, - 0x2, 0xb, 0xa, 0x20, 0x2f, 0x12, 0x79, 0x30, 0x0, 0x2, 0x1b, 0xa, 0x20, 0x7e, 0x1d, 0x39, - 0x7a, 0x1d, 0x33, 0xd2, 0x2, 0x7e, 0x34, 0x0, 0x1, 0x2, 0x3, 0x25, 0xbe, 0x60, 0x1, 0x68, - 0x9, 0xa5, 0xbe, 0x2, 0x5, 0x7a, 0x71, 0x3d, 0xd2, 0x3, 0xd2, 0x2, 0x22, 0x75, 0xe6, 0x0, - 0xe4, 0x7e, 0x34, 0x1, 0x4, 0x7e, 0x24, 0x0, 0xff, 0x7a, 0x1b, 0xb0, 0x7e, 0x34, 0x1, 0x5, - 0x7a, 0x1b, 0xb0, 0xd2, 0x4, 0x22, 0xa5, 0xbe, 0x1, 0x4, 0x7a, 0x71, 0x37, 0x22, 0xa5, 0xbe, - 0x2, 0x2, 0x80, 0x3, 0x2, 0x3, 0x33, 0x7a, 0x71, 0x22, 0x22, 0x7a, 0x71, 0x32, 0x22, 0xd2, - 0x2, 0x22, 0x1b, 0x61, 0x68, 0x21, 0x1b, 0x60, 0x68, 0x24, 0x1b, 0x60, 0x68, 0x38, 0x1b, 0x60, - 0x68, 0x40, 0xb, 0x62, 0x78, 0x5d, 0xa, 0x37, 0x7d, 0x3, 0x6d, 0x11, 0x7e, 0x1d, 0x39, 0x79, - 0x11, 0x0, 0x2, 0x1b, 0x1a, 0x0, 0x22, 0xa, 0x57, 0x7c, 0xab, 0xe4, 0x80, 0x2, 0xa, 0x57, - 0x6d, 0x44, 0x7e, 0xd, 0x39, 0x69, 0x30, 0x0, 0x2, 0xb, 0xa, 0x20, 0x2f, 0x12, 0x79, 0x30, - 0x0, 0x2, 0x1b, 0xa, 0x20, 0x22, 0x7c, 0x67, 0x6c, 0x77, 0x7e, 0xd, 0x39, 0x79, 0x30, 0x0, - 0x4, 0x22, 0xa, 0x27, 0x7e, 0xd, 0x39, 0xb, 0x16, 0xb, 0xa, 0x30, 0x2d, 0x32, 0x1b, 0xa, - 0x30, 0x7e, 0x34, 0x0, 0x3, 0x7a, 0x35, 0x2e, 0x22, 0x7e, 0x34, 0x0, 0x4, 0x7a, 0x35, 0x2e, - 0x75, 0x16, 0x0, 0x22, 0xca, 0x3b, 0x7a, 0x15, 0x8, 0x7f, 0x31, 0x7e, 0x35, 0x8, 0xbe, 0x34, - 0x0, 0x0, 0x38, 0x4f, 0x7e, 0x34, 0xff, 0xff, 0x7a, 0x35, 0x8, 0x75, 0xe, 0x1, 0x80, 0x43, - 0x7e, 0x34, 0x0, 0x80, 0x7a, 0x35, 0x11, 0x7f, 0x13, 0x7e, 0x8, 0x2, 0x56, 0x12, 0xc, 0xde, - 0x7e, 0x35, 0x8, 0x9e, 0x34, 0x0, 0x80, 0x7a, 0x35, 0x8, 0x2e, 0x38, 0x0, 0x80, 0x6d, 0x33, - 0x7a, 0x35, 0xf, 0x7e, 0x35, 0xf, 0x9, 0x63, 0x2, 0x56, 0x7e, 0xd, 0xa, 0x7e, 0xb, 0x70, - 0x6c, 0x76, 0x7a, 0xb, 0x70, 0x7e, 0x35, 0xf, 0xb, 0x34, 0x7a, 0x35, 0xf, 0xbe, 0x34, 0x0, - 0x80, 0x78, 0xe0, 0x7e, 0x35, 0x8, 0xbe, 0x34, 0x0, 0x80, 0x38, 0xb4, 0xe5, 0xe, 0x60, 0x5, - 0xb, 0x34, 0x7a, 0x35, 0x8, 0x7e, 0x35, 0x8, 0x7a, 0x35, 0x11, 0x7f, 0x13, 0x7e, 0x8, 0x2, - 0x56, 0x12, 0xc, 0xde, 0x6d, 0x33, 0x80, 0x17, 0x7e, 0x35, 0xf, 0x9, 0x63, 0x2, 0x56, 0x7e, - 0xd, 0xa, 0x7e, 0xb, 0x70, 0x6c, 0x76, 0x7a, 0xb, 0x70, 0x7e, 0x35, 0xf, 0xb, 0x34, 0x7a, - 0x35, 0xf, 0x7e, 0x35, 0x8, 0xbe, 0x35, 0xf, 0x38, 0xde, 0xda, 0x3b, 0x22, 0x12, 0xc, 0x95, - 0x12, 0x9, 0xc3, 0xa9, 0xa6, 0x94, 0xb3, 0x92, 0x6, 0x30, 0x6, 0x6, 0x12, 0xd, 0x7, 0x12, - 0xb, 0xb9, 0x12, 0x9, 0x15, 0x12, 0xc, 0xec, 0xd2, 0xaf, 0x30, 0x3, 0xfd, 0x2, 0xd, 0x31, - 0x56, 0x30, 0x2e, 0x32, 0x41, 0x70, 0x72, 0x20, 0x32, 0x31, 0x20, 0x32, 0x30, 0x31, 0x36, 0x0, - 0x46, 0x54, 0x53, 0x38, 0x37, 0x31, 0x36, 0x5f, 0x70, 0x72, 0x61, 0x6d, 0x62, 0x6f, 0x6f, 0x74, - 0x12, 0x3, 0xdd, 0x2, 0x5, 0x66, 0x7e, 0x35, 0x2e, 0x1b, 0x34, 0x68, 0x57, 0x1b, 0x35, 0x78, - 0x3, 0x2, 0x4, 0xb3, 0x1b, 0x34, 0x78, 0x3, 0x2, 0x4, 0xdd, 0xb, 0x35, 0x68, 0x3, 0x2, - 0x5, 0x52, 0x6d, 0x33, 0x7a, 0x35, 0x2e, 0x7a, 0x35, 0x30, 0x30, 0x5, 0x5, 0x12, 0x0, 0x2e, - 0xc2, 0x5, 0x7e, 0xd, 0x33, 0x69, 0x30, 0x0, 0x4, 0x7a, 0x35, 0xc, 0x69, 0x30, 0x0, 0x2, - 0xb, 0xa, 0x20, 0x2e, 0x14, 0x0, 0x8, 0x12, 0x0, 0x46, 0xd2, 0x5, 0x7e, 0x2d, 0x33, 0x69, - 0x12, 0x0, 0x4, 0x69, 0x32, 0x0, 0x2, 0xb, 0x2a, 0x20, 0x12, 0xa, 0x6a, 0x2e, 0x34, 0x10, - 0x0, 0x2, 0x5, 0x4f, 0x6d, 0x33, 0x7a, 0x35, 0x2e, 0x7e, 0x34, 0x1, 0x0, 0x7a, 0x35, 0x11, - 0x7e, 0xd, 0x33, 0x69, 0x30, 0x0, 0x2, 0xb, 0xa, 0x20, 0x2e, 0x14, 0x0, 0x8, 0x12, 0xc, - 0xde, 0x20, 0x0, 0x3, 0x2, 0x5, 0x52, 0x7e, 0x1d, 0x33, 0x29, 0xb1, 0x0, 0x8, 0xf5, 0x91, - 0x2, 0x5, 0x52, 0x6d, 0x33, 0x7a, 0x35, 0x2e, 0x7a, 0x35, 0x30, 0x7e, 0x18, 0x0, 0x16, 0x7a, - 0x1d, 0xa, 0x7e, 0xd, 0x33, 0x69, 0x30, 0x0, 0x2, 0xb, 0xa, 0x20, 0x69, 0x10, 0x0, 0x4, - 0x12, 0x3, 0x34, 0x12, 0x0, 0x2e, 0x7e, 0x34, 0xf0, 0x55, 0x2, 0x5, 0x4f, 0x6d, 0x33, 0x7a, - 0x35, 0x2e, 0x7a, 0x35, 0x30, 0xe5, 0x37, 0xb4, 0xa, 0x15, 0xe5, 0x23, 0xb4, 0x80, 0xb, 0xe4, - 0x12, 0xb, 0x8, 0x74, 0x1, 0x12, 0xb, 0x8, 0x80, 0x4e, 0x12, 0x6, 0xd8, 0x80, 0x49, 0xe5, - 0x37, 0xb4, 0xb, 0x27, 0xe5, 0x23, 0xb4, 0x80, 0x11, 0x7e, 0xf0, 0x1, 0x7c, 0xbf, 0x12, 0x5, - 0x6d, 0xb, 0xf0, 0xbe, 0xf0, 0x11, 0x78, 0xf4, 0x80, 0x2e, 0x7e, 0xf0, 0x4, 0x7c, 0xbf, 0x12, - 0x5, 0x6d, 0xb, 0xf0, 0xbe, 0xf0, 0x40, 0x78, 0xf4, 0x80, 0x1d, 0xe5, 0x37, 0xa, 0x3b, 0x9e, - 0x34, 0x0, 0x80, 0x7c, 0xe7, 0x6c, 0xdd, 0x80, 0x9, 0x7c, 0xbe, 0x12, 0x5, 0x6d, 0xb, 0xe0, - 0xb, 0xd0, 0xe5, 0x22, 0xbc, 0xbd, 0x38, 0xf1, 0x12, 0x0, 0x2e, 0x7e, 0x34, 0xf0, 0xaa, 0x7a, - 0x35, 0x30, 0x30, 0x4, 0x11, 0x7e, 0x34, 0x13, 0x88, 0x12, 0xc, 0x72, 0x7e, 0x34, 0x13, 0x88, - 0x12, 0xc, 0x72, 0x75, 0xe9, 0xff, 0x30, 0x6, 0x3, 0x2, 0x4, 0x26, 0x22, 0xca, 0xf8, 0x7c, - 0xfb, 0xe5, 0x23, 0xb4, 0x80, 0x4a, 0xd2, 0x7, 0x12, 0xc, 0xcb, 0x74, 0x20, 0xca, 0xb8, 0xa, - 0x3f, 0x6d, 0x22, 0x74, 0xc, 0x2f, 0x11, 0x14, 0x78, 0xfb, 0xda, 0xb8, 0x12, 0xc, 0x1a, 0xa9, - 0xd2, 0xb4, 0x12, 0xd, 0x1e, 0x12, 0xc, 0xb6, 0x50, 0x9, 0x7e, 0x35, 0x19, 0xbe, 0x34, 0x1, - 0xf4, 0x28, 0xf2, 0x7e, 0x35, 0x19, 0xbe, 0x34, 0x1, 0xf4, 0x38, 0x6, 0x12, 0xd, 0x39, 0x2, - 0x6, 0x3f, 0xc2, 0x86, 0x7e, 0x34, 0x13, 0x88, 0x12, 0xc, 0x72, 0xd2, 0x86, 0x2, 0x6, 0x3f, - 0x74, 0x1, 0x12, 0x8, 0x50, 0x74, 0x1, 0x6d, 0x33, 0x12, 0xa, 0xbd, 0xe4, 0x12, 0x8, 0xb8, - 0x5e, 0x34, 0x80, 0x0, 0x7c, 0x4f, 0x6c, 0x55, 0x3e, 0x24, 0x4d, 0x32, 0x12, 0xa, 0xbd, 0x74, - 0x4, 0x6d, 0x33, 0x12, 0xa, 0xbd, 0x7e, 0x34, 0x0, 0x50, 0x12, 0xa, 0xbd, 0x7e, 0x34, 0x0, - 0x19, 0x12, 0xc, 0x72, 0x74, 0x4, 0x7e, 0x34, 0x0, 0x51, 0x12, 0xa, 0xbd, 0x7e, 0x34, 0xa2, - 0x1c, 0x12, 0xc, 0x72, 0x74, 0x4, 0x7e, 0x34, 0x0, 0x11, 0x12, 0xa, 0xbd, 0x7e, 0x34, 0x0, - 0x19, 0x12, 0xc, 0x72, 0x74, 0x4, 0x7e, 0x34, 0x0, 0x10, 0x12, 0xa, 0xbd, 0x7e, 0x34, 0x0, - 0x19, 0x12, 0xc, 0x72, 0x74, 0x4, 0x6d, 0x33, 0x12, 0xa, 0xbd, 0x7e, 0x34, 0x0, 0x5, 0x12, - 0xc, 0x72, 0xe4, 0x12, 0x8, 0x50, 0x74, 0x4, 0x7e, 0x34, 0xff, 0xf7, 0x12, 0xa, 0xbd, 0xda, - 0xf8, 0x22, 0xca, 0x3b, 0x7f, 0x30, 0x7c, 0xb6, 0xf5, 0x12, 0x7c, 0xb7, 0xf5, 0x13, 0x74, 0x1, - 0x7e, 0x35, 0x10, 0x1e, 0x34, 0x1b, 0x34, 0x4e, 0x60, 0x80, 0x12, 0xa, 0xbd, 0x12, 0x8, 0x50, - 0xa9, 0xc2, 0xb4, 0xa9, 0xc6, 0xb3, 0x75, 0xb5, 0x2, 0xa9, 0x36, 0xb3, 0xfc, 0xa9, 0xc6, 0xb3, - 0x75, 0xb5, 0x0, 0xa9, 0x36, 0xb3, 0xfc, 0xa9, 0xc6, 0xb3, 0x85, 0x12, 0xb5, 0xa9, 0x36, 0xb3, - 0xfc, 0xa9, 0xc6, 0xb3, 0x85, 0x13, 0xb5, 0xa9, 0x36, 0xb3, 0xfc, 0xa9, 0xc6, 0xb3, 0x6d, 0x33, - 0x80, 0x2a, 0x7f, 0x13, 0x2e, 0x35, 0x14, 0x7e, 0x1b, 0xb0, 0xf5, 0xb5, 0xa9, 0x36, 0xb3, 0xfc, - 0xa9, 0xc6, 0xb3, 0x7e, 0x35, 0x14, 0x5e, 0x34, 0x0, 0x1, 0xbe, 0x34, 0x0, 0x1, 0x78, 0x7, - 0x7e, 0x34, 0x0, 0x78, 0x12, 0xc, 0x72, 0x7e, 0x35, 0x14, 0xb, 0x34, 0x7a, 0x35, 0x14, 0x7e, - 0x35, 0x10, 0xbe, 0x35, 0x14, 0x38, 0xcb, 0xa9, 0xd2, 0xb4, 0x7e, 0x34, 0x0, 0x5, 0x12, 0xc, - 0x72, 0xe4, 0x12, 0x8, 0x50, 0xda, 0x3b, 0x22, 0xe5, 0x23, 0xb4, 0x80, 0x16, 0xd2, 0x7, 0x12, - 0xc, 0xcb, 0xa9, 0xc2, 0xb4, 0x74, 0x60, 0x12, 0xd, 0x13, 0xa9, 0xd2, 0xb4, 0x12, 0xc, 0xb6, - 0x40, 0xfb, 0x22, 0x74, 0x1, 0x12, 0x8, 0x50, 0xe4, 0x6d, 0x33, 0x12, 0xa, 0xbd, 0x74, 0x1, - 0x6d, 0x33, 0x12, 0xa, 0xbd, 0x74, 0x4, 0x6d, 0x33, 0x12, 0xa, 0xbd, 0x7e, 0x34, 0x0, 0x54, - 0x12, 0xa, 0xbd, 0x7e, 0x34, 0x0, 0x19, 0x12, 0xc, 0x72, 0x74, 0x4, 0x7e, 0x34, 0x0, 0x55, - 0x12, 0xa, 0xbd, 0x7e, 0x34, 0xa2, 0x1c, 0x12, 0xc, 0x72, 0x74, 0x4, 0x7e, 0x34, 0x0, 0x15, - 0x12, 0xa, 0xbd, 0x7e, 0x34, 0x0, 0xa0, 0x12, 0xc, 0x72, 0x74, 0x4, 0x7e, 0x34, 0x0, 0x14, - 0x12, 0xa, 0xbd, 0x7e, 0x34, 0x0, 0x19, 0x12, 0xc, 0x72, 0x74, 0x4, 0x7e, 0x34, 0x0, 0x4, - 0x12, 0xa, 0xbd, 0x7e, 0x34, 0x0, 0x5, 0x12, 0xc, 0x72, 0xe4, 0x12, 0x8, 0x50, 0x74, 0x4, - 0x7e, 0x34, 0xff, 0xf7, 0x2, 0xa, 0xbd, 0x75, 0x84, 0x1, 0x7e, 0x44, 0x1f, 0xff, 0xe4, 0x7a, - 0x49, 0xb0, 0x1b, 0x44, 0x78, 0xf9, 0x7e, 0xf8, 0x2, 0xd9, 0xd2, 0x5, 0xc2, 0x6, 0x75, 0x16, - 0x0, 0x75, 0x17, 0x87, 0x75, 0x18, 0xa6, 0x75, 0x19, 0x0, 0x75, 0x1a, 0x0, 0xd2, 0x0, 0xc2, - 0x2, 0xc2, 0x3, 0xc2, 0x4, 0x75, 0x21, 0x0, 0x75, 0x22, 0x0, 0x75, 0x23, 0x80, 0x75, 0x2e, - 0x0, 0x75, 0x2f, 0x0, 0x75, 0x30, 0x0, 0x75, 0x31, 0x0, 0x75, 0x32, 0x0, 0x75, 0x37, 0xb, - 0x75, 0x38, 0x0, 0x75, 0x3d, 0x1, 0x7e, 0x4, 0x0, 0xff, 0x7e, 0x14, 0xd, 0x3c, 0xb, 0xa, - 0x40, 0x5d, 0x44, 0x68, 0x1a, 0x69, 0x20, 0x0, 0x2, 0xb, 0xe, 0xb, 0x44, 0x80, 0xa, 0x7e, - 0xb, 0xb0, 0x7a, 0x29, 0xb0, 0xb, 0x24, 0xb, 0xc, 0x1b, 0x44, 0x78, 0xf2, 0x80, 0xdf, 0x2, - 0x4, 0x20, 0x7c, 0x7b, 0x7e, 0xa0, 0xef, 0xe5, 0x21, 0x24, 0xfd, 0x68, 0x38, 0x1b, 0xb1, 0x68, - 0x22, 0x24, 0x9f, 0x68, 0x3d, 0x1b, 0xb2, 0x68, 0x3e, 0x24, 0x9e, 0x68, 0x35, 0x24, 0x3c, 0x78, - 0x4c, 0xa5, 0xbf, 0x0, 0x5, 0x7e, 0xa1, 0x17, 0x80, 0x43, 0xa5, 0xbf, 0x1, 0x3f, 0x7e, 0xa1, - 0x18, 0x80, 0x3a, 0xa5, 0xbf, 0x0, 0x5, 0x7e, 0xa1, 0x23, 0x80, 0x31, 0xa5, 0xbf, 0x1, 0x2d, - 0x7e, 0xa1, 0x3d, 0x80, 0x28, 0xa, 0x17, 0x7e, 0x1d, 0x39, 0x2d, 0x31, 0x29, 0xa1, 0x0, 0x8, - 0x80, 0x1b, 0x7e, 0xa1, 0x16, 0x80, 0x16, 0xa5, 0xbf, 0x0, 0x9, 0x7e, 0x35, 0x30, 0xa, 0x56, - 0x7c, 0xab, 0x80, 0x9, 0xa5, 0xbf, 0x1, 0x5, 0x7e, 0x55, 0x30, 0x7c, 0xab, 0x7c, 0xba, 0x22, - 0xca, 0x79, 0xbe, 0xb0, 0x0, 0x28, 0x2e, 0x74, 0x6, 0x12, 0x8, 0xb8, 0x7d, 0x73, 0x6c, 0xff, - 0x7e, 0xf0, 0xa5, 0x7d, 0x37, 0x12, 0xa, 0xbd, 0x6c, 0xff, 0x7e, 0xf0, 0xf, 0x7d, 0x37, 0x12, - 0xa, 0xbd, 0x6c, 0xff, 0x7e, 0xf0, 0x6a, 0x7d, 0x37, 0x12, 0xa, 0xbd, 0x7e, 0x34, 0x0, 0x5, - 0x12, 0xc, 0x72, 0x80, 0x30, 0x74, 0x1, 0x7e, 0x34, 0xdf, 0xff, 0x12, 0xa, 0xbd, 0x74, 0x6, - 0x12, 0x8, 0xb8, 0x7d, 0x73, 0x6c, 0xff, 0x7d, 0x37, 0x12, 0xa, 0xbd, 0x7d, 0x37, 0x12, 0xa, - 0xbd, 0x7d, 0x37, 0x12, 0xa, 0xbd, 0x74, 0x2, 0x12, 0x8, 0xb8, 0x7d, 0x73, 0x4e, 0xf0, 0x1, - 0x7d, 0x37, 0x12, 0xa, 0xbd, 0xda, 0x79, 0x22, 0xa9, 0xc2, 0xb4, 0xa9, 0xc6, 0xb3, 0x75, 0xb5, - 0x5, 0xa9, 0x36, 0xb3, 0xfc, 0xa9, 0xc6, 0xb3, 0x75, 0xb5, 0x0, 0xa9, 0x36, 0xb3, 0xfc, 0xa9, - 0xc6, 0xb3, 0x75, 0xb5, 0x0, 0xa9, 0x36, 0xb3, 0xfc, 0xa9, 0xc6, 0xb3, 0xf5, 0xb5, 0xa9, 0x36, - 0xb3, 0xfc, 0xa9, 0xc6, 0xb3, 0x75, 0xb5, 0x0, 0xa9, 0x36, 0xb3, 0xfc, 0xa9, 0xc6, 0xb3, 0x75, - 0xb5, 0x0, 0xa9, 0x36, 0xb3, 0xfc, 0xa9, 0xc6, 0xb3, 0x7e, 0x71, 0xb5, 0x75, 0xb5, 0x0, 0xa9, - 0x36, 0xb3, 0xfc, 0xa9, 0xc6, 0xb3, 0x7e, 0xa1, 0xb5, 0xa9, 0xd2, 0xb4, 0x7c, 0x47, 0x6c, 0x55, - 0xa, 0x3a, 0x4d, 0x32, 0x22, 0xca, 0xf8, 0x7e, 0xf0, 0x70, 0x75, 0x91, 0x0, 0xc2, 0x90, 0xc2, - 0x91, 0x20, 0x87, 0x3, 0x7e, 0xf1, 0xe4, 0x30, 0x6, 0x30, 0x7e, 0x34, 0x0, 0x2, 0x7a, 0x35, - 0x11, 0x7e, 0x18, 0x7, 0x80, 0x7e, 0x8, 0x0, 0x8, 0x12, 0xc, 0xde, 0xe5, 0x8, 0xbe, 0xb0, - 0xff, 0x68, 0x17, 0xe5, 0x8, 0x60, 0x13, 0xe5, 0x9, 0xa, 0x2b, 0xe5, 0x8, 0xa, 0x3b, 0x2d, - 0x32, 0xbe, 0x34, 0x0, 0xff, 0x78, 0x3, 0x7e, 0xf1, 0x8, 0x5e, 0xf0, 0xfe, 0x7a, 0xf1, 0x92, - 0xd2, 0xe8, 0xc2, 0xc0, 0xa9, 0xd5, 0xb7, 0xd2, 0xbd, 0xd2, 0xad, 0xda, 0xf8, 0x22, 0x7f, 0x70, - 0xd2, 0x7, 0x12, 0xc, 0xcb, 0x74, 0x2, 0x12, 0xc, 0x1a, 0x6d, 0x33, 0x80, 0x12, 0x7f, 0x7, - 0x2d, 0x13, 0x7e, 0xb, 0xb0, 0xf5, 0xb5, 0xa9, 0x36, 0xb3, 0xfc, 0xa9, 0xc6, 0xb3, 0xb, 0x34, - 0x7e, 0x25, 0x10, 0xbd, 0x23, 0x38, 0xe7, 0xa9, 0xd2, 0xb4, 0x12, 0xd, 0x1e, 0x12, 0xc, 0xb6, - 0x50, 0x9, 0x7e, 0x35, 0x19, 0xbe, 0x34, 0x1, 0xf4, 0x28, 0xf2, 0x7e, 0x35, 0x19, 0xbe, 0x34, - 0x1, 0xf4, 0x38, 0x3, 0x2, 0xd, 0x39, 0xc2, 0x86, 0x7e, 0x34, 0x13, 0x88, 0x12, 0xc, 0x72, - 0xd2, 0x86, 0x22, 0xa9, 0xd1, 0xcb, 0xd2, 0xcc, 0x7e, 0x34, 0x0, 0x4, 0x7e, 0x8, 0x2, 0x56, - 0x74, 0xc, 0x12, 0xa, 0x17, 0xa9, 0xd1, 0xcb, 0xc2, 0xcc, 0x6c, 0xaa, 0x7e, 0x70, 0x2, 0xac, - 0x7a, 0x7e, 0x8, 0x2, 0x56, 0x2d, 0x13, 0xb, 0xa, 0x30, 0x7d, 0x23, 0x7c, 0x45, 0x6c, 0x55, - 0xa, 0x36, 0x4d, 0x32, 0x1b, 0xa, 0x30, 0xb, 0xa0, 0xbe, 0xa0, 0xc, 0x78, 0xde, 0x7e, 0x37, - 0x2, 0x66, 0x7d, 0x23, 0xa, 0x54, 0x7c, 0xa7, 0xb4, 0xe7, 0xb, 0xbe, 0xa0, 0x16, 0x78, 0x6, - 0x75, 0x17, 0xe7, 0x75, 0x18, 0xa6, 0x22, 0x7e, 0x24, 0x0, 0x1, 0x7e, 0x7f, 0x2, 0xd6, 0x79, - 0x27, 0x0, 0x6, 0x7e, 0x7f, 0x2, 0xd6, 0x69, 0x27, 0x0, 0x6, 0x4d, 0x22, 0x78, 0xf4, 0x5e, - 0x60, 0x7f, 0x1b, 0x7a, 0x30, 0x7e, 0x1f, 0x2, 0xd6, 0x69, 0x31, 0x0, 0x8, 0x4d, 0x33, 0x68, - 0xf4, 0x6c, 0xaa, 0x80, 0x20, 0x6d, 0x44, 0x7e, 0x1f, 0x2, 0xd6, 0x1b, 0x1a, 0x40, 0x7e, 0x1f, - 0x2, 0xd6, 0x69, 0x41, 0x0, 0x8, 0x4d, 0x44, 0x68, 0xf4, 0x69, 0x41, 0x0, 0x2, 0x1b, 0xa, - 0x40, 0xb, 0x15, 0xb, 0xa0, 0xbc, 0xba, 0x38, 0xdc, 0x22, 0x6d, 0x0, 0x74, 0x10, 0x4d, 0x0, - 0x78, 0xb, 0x4d, 0x22, 0x78, 0x27, 0x8d, 0x31, 0x7d, 0x12, 0x6d, 0x22, 0x22, 0x7d, 0x43, 0x7d, - 0x32, 0x6d, 0x22, 0x2f, 0x11, 0x2d, 0x44, 0x50, 0x2, 0xa5, 0xf, 0xbf, 0x10, 0x40, 0x4, 0x9f, - 0x10, 0xb, 0x90, 0x14, 0x78, 0xed, 0x7f, 0x1, 0x6d, 0x22, 0x7d, 0x34, 0x22, 0x7d, 0x41, 0x7d, - 0x13, 0x8d, 0x24, 0x7d, 0x2, 0x2f, 0x0, 0x40, 0x4, 0xbd, 0x4, 0x40, 0x4, 0x9d, 0x4, 0xb, - 0x14, 0x14, 0x78, 0xf1, 0x7d, 0x23, 0x7d, 0x31, 0x7d, 0x10, 0x6d, 0x0, 0x22, 0x7d, 0x23, 0xa, - 0x36, 0x7c, 0xa5, 0xa9, 0xc2, 0xb4, 0xa9, 0xc6, 0xb3, 0x75, 0xb5, 0x1, 0xa9, 0x36, 0xb3, 0xfc, - 0xa9, 0xc6, 0xb3, 0x75, 0xb5, 0x0, 0xa9, 0x36, 0xb3, 0xfc, 0xa9, 0xc6, 0xb3, 0x75, 0xb5, 0x0, - 0xa9, 0x36, 0xb3, 0xfc, 0xa9, 0xc6, 0xb3, 0xf5, 0xb5, 0xa9, 0x36, 0xb3, 0xfc, 0xa9, 0xc6, 0xb3, - 0x7a, 0x71, 0xb5, 0xa9, 0x36, 0xb3, 0xfc, 0xa9, 0xc6, 0xb3, 0x7a, 0xa1, 0xb5, 0xa9, 0x36, 0xb3, - 0xfc, 0xa9, 0xc6, 0xb3, 0xa9, 0xd2, 0xb4, 0x22, 0x7c, 0xab, 0xd2, 0x7, 0x12, 0xc, 0xcb, 0x74, - 0xd8, 0xa, 0x3a, 0x7d, 0x23, 0x6d, 0x33, 0x12, 0xc, 0x1a, 0xa9, 0xd2, 0xb4, 0x12, 0xd, 0x1e, - 0x12, 0xc, 0xb6, 0x50, 0x9, 0x7e, 0x35, 0x19, 0xbe, 0x34, 0x5, 0xdc, 0x28, 0xf2, 0x7e, 0x35, - 0x19, 0xbe, 0x34, 0x5, 0xdc, 0x38, 0x3, 0x2, 0xd, 0x39, 0xc2, 0x86, 0x7e, 0x34, 0x13, 0x88, - 0x12, 0xc, 0x72, 0xd2, 0x86, 0x22, 0xca, 0x2b, 0xca, 0x1b, 0xca, 0xb, 0xd2, 0x0, 0x30, 0x90, - 0x1c, 0xc2, 0x90, 0x7e, 0x71, 0x91, 0xe5, 0x38, 0x70, 0x3, 0x7a, 0x71, 0x21, 0xe5, 0x38, 0x12, - 0x1, 0x20, 0x5, 0x38, 0x30, 0x2, 0x6, 0xe4, 0x12, 0x7, 0xe2, 0xf5, 0x91, 0x30, 0x91, 0xb, - 0xc2, 0x91, 0x5, 0x38, 0xe5, 0x38, 0x12, 0x7, 0xe2, 0xf5, 0x91, 0xda, 0xb, 0xda, 0x1b, 0xda, - 0x2b, 0x32, 0xca, 0xf8, 0x7c, 0xfb, 0xe5, 0x23, 0xb4, 0x81, 0x23, 0x74, 0x2, 0x12, 0x8, 0xb8, - 0x4c, 0xff, 0x78, 0x8, 0xa9, 0xc0, 0xca, 0x5e, 0x70, 0xdf, 0x80, 0x6, 0xa9, 0xd0, 0xca, 0x4e, - 0x70, 0x20, 0x74, 0x2, 0x12, 0xa, 0xbd, 0x74, 0x2, 0x12, 0x8, 0xb8, 0x80, 0x8, 0xe5, 0x23, - 0xb4, 0x80, 0x3, 0x12, 0xb, 0xec, 0xda, 0xf8, 0x22, 0xd2, 0x7, 0x12, 0xc, 0xcb, 0xa9, 0xc2, - 0xb4, 0x74, 0x9f, 0x12, 0xd, 0x13, 0x12, 0xc, 0xfa, 0xa9, 0xd2, 0xb4, 0x60, 0x3, 0xb4, 0xff, - 0x1a, 0x75, 0x23, 0x81, 0xa9, 0xd5, 0xca, 0xa9, 0xd0, 0xca, 0x75, 0xed, 0x9f, 0x75, 0xad, 0x20, - 0xa9, 0xd1, 0xea, 0xa9, 0xc1, 0xea, 0x74, 0x1, 0x2, 0xb, 0x82, 0x22, 0xd2, 0x7, 0x12, 0xc, - 0xcb, 0xa9, 0xc2, 0xb4, 0x74, 0x5, 0x12, 0xd, 0x13, 0x12, 0xc, 0xfa, 0x7c, 0xab, 0xa9, 0xd2, - 0xb4, 0x5e, 0xa0, 0xe3, 0xa9, 0xc2, 0xb4, 0x74, 0x1, 0x12, 0xd, 0x13, 0x7c, 0xba, 0x12, 0xd, - 0x13, 0xa9, 0xd2, 0xb4, 0x12, 0xc, 0xb6, 0x40, 0xfb, 0x22, 0x7c, 0xab, 0x7d, 0x12, 0x7c, 0xb3, - 0xf5, 0x14, 0x7c, 0x36, 0x7c, 0x25, 0xa, 0x4, 0x7c, 0xb3, 0xf5, 0x13, 0x7c, 0xb7, 0xf5, 0x12, - 0xa9, 0xc2, 0xb4, 0x7c, 0xba, 0x12, 0xd, 0x13, 0xe5, 0x14, 0x12, 0xd, 0x13, 0xe5, 0x13, 0x12, - 0xd, 0x13, 0xe5, 0x12, 0x2, 0xd, 0x13, 0x7d, 0x52, 0xf5, 0x15, 0x7c, 0xb6, 0x7c, 0xa5, 0xa, - 0x44, 0xf5, 0x14, 0x7f, 0x21, 0xf5, 0x13, 0xa9, 0xc2, 0xb4, 0x74, 0xb, 0x12, 0xd, 0x13, 0xe5, - 0x15, 0x12, 0xd, 0x13, 0xe5, 0x14, 0x12, 0xd, 0x13, 0xe5, 0x13, 0x12, 0xd, 0x13, 0xe4, 0x2, - 0xd, 0x13, 0x80, 0x18, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xe5, 0x3d, - 0x70, 0xa, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7d, 0x23, 0x1b, 0x34, - 0x4d, 0x22, 0x78, 0xe0, 0x22, 0xd2, 0xcf, 0x85, 0x3d, 0xcc, 0x75, 0xec, 0xff, 0x75, 0xee, 0xff, - 0x75, 0xeb, 0x3, 0x75, 0xac, 0xc0, 0xa9, 0xc5, 0xca, 0x75, 0xed, 0xf, 0x75, 0xad, 0xb0, 0xa9, - 0xd7, 0x94, 0xa9, 0xd4, 0x94, 0x22, 0xa9, 0xc2, 0xb4, 0x74, 0x5, 0x12, 0xd, 0x13, 0x12, 0xc, - 0xfa, 0xa9, 0xd2, 0xb4, 0x30, 0xe0, 0x2, 0xd3, 0x22, 0xc3, 0x22, 0xa9, 0xc2, 0xb4, 0x30, 0x7, - 0x4, 0x74, 0x6, 0x80, 0x2, 0x74, 0x4, 0x12, 0xd, 0x13, 0xa9, 0xd2, 0xb4, 0x22, 0x12, 0xc, - 0x47, 0x7e, 0x35, 0x11, 0x12, 0x0, 0xe, 0xa9, 0xd2, 0xb4, 0xd3, 0x22, 0xc2, 0x8c, 0x43, 0x89, - 0x2, 0x75, 0x8c, 0x1, 0x75, 0x8a, 0x0, 0xd2, 0xa9, 0x22, 0x75, 0xb5, 0x0, 0xa9, 0x36, 0xb3, - 0xfc, 0xa9, 0xc6, 0xb3, 0xe5, 0xb5, 0x22, 0xd2, 0xc8, 0x75, 0xb3, 0x13, 0xa9, 0xd1, 0xb4, 0xa9, - 0xc0, 0xb4, 0x22, 0xf5, 0xb5, 0xa9, 0x36, 0xb3, 0xfc, 0xa9, 0xc6, 0xb3, 0xd3, 0x22, 0xc2, 0x8c, - 0x6d, 0x33, 0x7a, 0x35, 0x19, 0xd2, 0x8c, 0x22, 0x7e, 0x35, 0x19, 0xb, 0x34, 0x7a, 0x35, 0x19, - 0x22, 0x85, 0x3d, 0xcc, 0xe5, 0x3d, 0x2, 0xb, 0x82, 0x2, 0xd, 0x28, 0x0, 0x4, 0x2, 0xd6, - 0x0, 0x0, 0x9c, 0x0, 0x0, 0x0, +0x2, 0x7, 0x67, 0xca, 0x39, 0x12, 0xd, 0x28, 0xda, 0x39, 0x32, 0x2, 0x0, 0x3, 0x6d, 0x22, +0x80, 0x13, 0x75, 0xb5, 0x0, 0xa9, 0x36, 0xb3, 0xfc, 0xa9, 0xc6, 0xb3, 0xe5, 0xb5, 0x7a, 0xb, +0xb0, 0xb, 0x14, 0xb, 0x24, 0xbd, 0x32, 0x38, 0xe9, 0x22, 0xff, 0x2, 0xb, 0x46, 0xe5, 0x32, +0xb4, 0xc, 0xf, 0xc2, 0x86, 0xc2, 0x87, 0x7e, 0x34, 0x0, 0x64, 0x12, 0xc, 0x72, 0xd2, 0x86, +0xd2, 0x87, 0x22, 0x2, 0x0, 0xf9, 0xca, 0x3b, 0x7a, 0xd, 0x8, 0x7f, 0x31, 0xe5, 0x23, 0xb4, +0x80, 0x2, 0x80, 0x3, 0x2, 0x0, 0xdc, 0x7f, 0x13, 0x5e, 0x34, 0x0, 0x7f, 0x7d, 0x23, 0x7e, +0x34, 0x0, 0x80, 0x9d, 0x32, 0x7a, 0x35, 0xe, 0x7e, 0x35, 0xc, 0xbe, 0x35, 0xe, 0x38, 0x2, +0x80, 0x5d, 0x7e, 0x35, 0xe, 0x7a, 0x35, 0x10, 0x7f, 0x13, 0x7e, 0xd, 0x8, 0x12, 0x9, 0x6e, +0x7e, 0x35, 0xc, 0x9e, 0x35, 0xe, 0x7a, 0x35, 0xc, 0x7e, 0x35, 0xe, 0x6d, 0x22, 0x2f, 0x31, +0x7e, 0x1d, 0x8, 0x2e, 0x35, 0xe, 0x7a, 0x1d, 0x8, 0x80, 0x27, 0x7e, 0x34, 0x0, 0x80, 0x7a, +0x35, 0x10, 0x7f, 0x13, 0x7e, 0xd, 0x8, 0x12, 0x9, 0x6e, 0x7e, 0x35, 0xc, 0x9e, 0x34, 0x0, +0x80, 0x7a, 0x35, 0xc, 0x7e, 0x1d, 0x8, 0x2e, 0x34, 0x0, 0x80, 0x7a, 0x1d, 0x8, 0x2e, 0x38, +0x0, 0x80, 0x7e, 0x35, 0xc, 0xbe, 0x34, 0x0, 0x80, 0x50, 0xd0, 0x4d, 0x33, 0x68, 0x26, 0x7a, +0x35, 0x10, 0x7f, 0x13, 0x7e, 0xd, 0x8, 0x12, 0x9, 0x6e, 0x80, 0x19, 0x74, 0x2, 0x12, 0x8, +0xb8, 0x5e, 0x70, 0xf4, 0x12, 0xa, 0xbd, 0x7e, 0x35, 0xc, 0x7a, 0x35, 0x10, 0x7f, 0x13, 0x7e, +0xd, 0x8, 0x12, 0x6, 0x42, 0xd3, 0xda, 0x3b, 0x22, 0xa9, 0xc0, 0x93, 0x75, 0x38, 0x0, 0x32, +0xd, 0x46, 0xf2, 0xb9, 0x32, 0xcf, 0xcd, 0x30, 0xa5, 0x21, 0x5a, 0xde, 0xff, 0x0, 0xff, 0x0, +0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, +0x7c, 0x6b, 0xc2, 0x2, 0xe5, 0x21, 0x14, 0x78, 0x3, 0x2, 0x2, 0xbf, 0x1b, 0xb1, 0x78, 0x3, +0x2, 0x2, 0x30, 0x1b, 0xb1, 0x78, 0x3, 0x2, 0x2, 0x7c, 0x1b, 0xb1, 0x78, 0x3, 0x2, 0x2, +0x8d, 0x1b, 0xb1, 0x78, 0x3, 0x2, 0x2, 0xa6, 0x24, 0xf9, 0x78, 0x3, 0x2, 0x2, 0xbb, 0x24, +0xaf, 0x78, 0x3, 0x2, 0x3, 0x29, 0x24, 0xfd, 0x68, 0x2d, 0x14, 0x78, 0x3, 0x2, 0x2, 0xc2, +0x14, 0x78, 0x3, 0x2, 0x2, 0xbf, 0x1b, 0xb2, 0x78, 0x3, 0x2, 0x2, 0xbf, 0x24, 0xda, 0x68, +0x19, 0x24, 0xe6, 0x68, 0x12, 0x24, 0xeb, 0x68, 0x2e, 0x24, 0xf3, 0x78, 0x3, 0x2, 0x2, 0xbf, +0x24, 0x77, 0x68, 0x3, 0x2, 0x3, 0x33, 0x2, 0x3, 0x30, 0xbe, 0x60, 0x4, 0x50, 0xc, 0x75, +0x16, 0x0, 0x7c, 0x16, 0x2e, 0x10, 0x24, 0x7c, 0xb7, 0xa5, 0xf7, 0xa5, 0xbe, 0x0, 0x2, 0x80, +0x3, 0x2, 0x3, 0x33, 0xd2, 0x2, 0x22, 0x7c, 0xb6, 0x24, 0x0, 0x78, 0x3, 0x2, 0x3, 0x33, +0x1b, 0xb1, 0x68, 0x1e, 0x14, 0x68, 0x1e, 0x14, 0x68, 0x1e, 0x14, 0x68, 0x1e, 0xb, 0xb2, 0x78, +0x33, 0x30, 0x1, 0x7, 0x7e, 0x8, 0x0, 0x3e, 0x2, 0x2, 0x4d, 0x7e, 0x8, 0x1, 0x4a, 0x2, +0x2, 0x4d, 0x2, 0x2, 0xe7, 0x2, 0x2, 0xee, 0x2, 0x3, 0x6, 0xa, 0x27, 0x7e, 0xd, 0x39, +0xb, 0x16, 0xb, 0xa, 0x30, 0x2d, 0x32, 0x1b, 0xa, 0x30, 0x6d, 0x33, 0x7e, 0xd, 0x39, 0x79, +0x30, 0x0, 0x6, 0x22, 0x7c, 0xb7, 0x62, 0x16, 0x7e, 0x2d, 0x39, 0x2e, 0x54, 0x0, 0x6, 0xb, +0x2a, 0x20, 0x7d, 0x12, 0xb, 0x14, 0x1b, 0x2a, 0x10, 0x7e, 0xd, 0x39, 0x2d, 0x12, 0x39, 0x70, +0x0, 0x8, 0x7e, 0xd, 0x39, 0x69, 0x50, 0x0, 0x4, 0x69, 0x20, 0x0, 0x6, 0xbd, 0x25, 0x50, +0x3, 0x2, 0x3, 0x33, 0xb2, 0x1, 0x7a, 0xd, 0x33, 0x7e, 0x34, 0x0, 0x2, 0x2, 0x3, 0x25, +0x7c, 0xb6, 0x1b, 0xb1, 0x68, 0x1d, 0x14, 0x68, 0x1d, 0xb, 0xb1, 0x68, 0x3, 0x2, 0x3, 0x33, +0x30, 0x1, 0x6, 0x7e, 0x8, 0x0, 0x3e, 0x80, 0x4, 0x7e, 0x8, 0x1, 0x4a, 0x7a, 0xd, 0x39, +0x2, 0x2, 0xd6, 0x2, 0x2, 0xe7, 0xa, 0x57, 0x6d, 0x44, 0x7e, 0xd, 0x39, 0x69, 0x30, 0x0, +0x2, 0xb, 0xa, 0x20, 0x2f, 0x12, 0x79, 0x30, 0x0, 0x2, 0x1b, 0xa, 0x20, 0x7e, 0x1d, 0x39, +0x7a, 0x1d, 0x33, 0xd2, 0x2, 0x7e, 0x34, 0x0, 0x1, 0x2, 0x3, 0x25, 0xbe, 0x60, 0x1, 0x68, +0x9, 0xa5, 0xbe, 0x2, 0x5, 0x7a, 0x71, 0x3d, 0xd2, 0x3, 0xd2, 0x2, 0x22, 0x75, 0xe6, 0x0, +0xe4, 0x7e, 0x34, 0x1, 0x4, 0x7e, 0x24, 0x0, 0xff, 0x7a, 0x1b, 0xb0, 0x7e, 0x34, 0x1, 0x5, +0x7a, 0x1b, 0xb0, 0xd2, 0x4, 0x22, 0xa5, 0xbe, 0x1, 0x4, 0x7a, 0x71, 0x37, 0x22, 0xa5, 0xbe, +0x2, 0x2, 0x80, 0x3, 0x2, 0x3, 0x33, 0x7a, 0x71, 0x22, 0x22, 0x7a, 0x71, 0x32, 0x22, 0xd2, +0x2, 0x22, 0x1b, 0x61, 0x68, 0x21, 0x1b, 0x60, 0x68, 0x24, 0x1b, 0x60, 0x68, 0x38, 0x1b, 0x60, +0x68, 0x40, 0xb, 0x62, 0x78, 0x5d, 0xa, 0x37, 0x7d, 0x3, 0x6d, 0x11, 0x7e, 0x1d, 0x39, 0x79, +0x11, 0x0, 0x2, 0x1b, 0x1a, 0x0, 0x22, 0xa, 0x57, 0x7c, 0xab, 0xe4, 0x80, 0x2, 0xa, 0x57, +0x6d, 0x44, 0x7e, 0xd, 0x39, 0x69, 0x30, 0x0, 0x2, 0xb, 0xa, 0x20, 0x2f, 0x12, 0x79, 0x30, +0x0, 0x2, 0x1b, 0xa, 0x20, 0x22, 0x7c, 0x67, 0x6c, 0x77, 0x7e, 0xd, 0x39, 0x79, 0x30, 0x0, +0x4, 0x22, 0xa, 0x27, 0x7e, 0xd, 0x39, 0xb, 0x16, 0xb, 0xa, 0x30, 0x2d, 0x32, 0x1b, 0xa, +0x30, 0x7e, 0x34, 0x0, 0x3, 0x7a, 0x35, 0x2e, 0x22, 0x7e, 0x34, 0x0, 0x4, 0x7a, 0x35, 0x2e, +0x75, 0x16, 0x0, 0x22, 0xca, 0x3b, 0x7a, 0x15, 0x8, 0x7f, 0x31, 0x7e, 0x35, 0x8, 0xbe, 0x34, +0x0, 0x0, 0x38, 0x4f, 0x7e, 0x34, 0xff, 0xff, 0x7a, 0x35, 0x8, 0x75, 0xe, 0x1, 0x80, 0x43, +0x7e, 0x34, 0x0, 0x80, 0x7a, 0x35, 0x11, 0x7f, 0x13, 0x7e, 0x8, 0x2, 0x56, 0x12, 0xc, 0xde, +0x7e, 0x35, 0x8, 0x9e, 0x34, 0x0, 0x80, 0x7a, 0x35, 0x8, 0x2e, 0x38, 0x0, 0x80, 0x6d, 0x33, +0x7a, 0x35, 0xf, 0x7e, 0x35, 0xf, 0x9, 0x63, 0x2, 0x56, 0x7e, 0xd, 0xa, 0x7e, 0xb, 0x70, +0x6c, 0x76, 0x7a, 0xb, 0x70, 0x7e, 0x35, 0xf, 0xb, 0x34, 0x7a, 0x35, 0xf, 0xbe, 0x34, 0x0, +0x80, 0x78, 0xe0, 0x7e, 0x35, 0x8, 0xbe, 0x34, 0x0, 0x80, 0x38, 0xb4, 0xe5, 0xe, 0x60, 0x5, +0xb, 0x34, 0x7a, 0x35, 0x8, 0x7e, 0x35, 0x8, 0x7a, 0x35, 0x11, 0x7f, 0x13, 0x7e, 0x8, 0x2, +0x56, 0x12, 0xc, 0xde, 0x6d, 0x33, 0x80, 0x17, 0x7e, 0x35, 0xf, 0x9, 0x63, 0x2, 0x56, 0x7e, +0xd, 0xa, 0x7e, 0xb, 0x70, 0x6c, 0x76, 0x7a, 0xb, 0x70, 0x7e, 0x35, 0xf, 0xb, 0x34, 0x7a, +0x35, 0xf, 0x7e, 0x35, 0x8, 0xbe, 0x35, 0xf, 0x38, 0xde, 0xda, 0x3b, 0x22, 0x12, 0xc, 0x95, +0x12, 0x9, 0xc3, 0xa9, 0xa6, 0x94, 0xb3, 0x92, 0x6, 0x30, 0x6, 0x6, 0x12, 0xd, 0x7, 0x12, +0xb, 0xb9, 0x12, 0x9, 0x15, 0x12, 0xc, 0xec, 0xd2, 0xaf, 0x30, 0x3, 0xfd, 0x2, 0xd, 0x31, +0x56, 0x30, 0x2e, 0x32, 0x41, 0x70, 0x72, 0x20, 0x32, 0x31, 0x20, 0x32, 0x30, 0x31, 0x36, 0x0, +0x46, 0x54, 0x53, 0x38, 0x37, 0x31, 0x36, 0x5f, 0x70, 0x72, 0x61, 0x6d, 0x62, 0x6f, 0x6f, 0x74, +0x12, 0x3, 0xdd, 0x2, 0x5, 0x66, 0x7e, 0x35, 0x2e, 0x1b, 0x34, 0x68, 0x57, 0x1b, 0x35, 0x78, +0x3, 0x2, 0x4, 0xb3, 0x1b, 0x34, 0x78, 0x3, 0x2, 0x4, 0xdd, 0xb, 0x35, 0x68, 0x3, 0x2, +0x5, 0x52, 0x6d, 0x33, 0x7a, 0x35, 0x2e, 0x7a, 0x35, 0x30, 0x30, 0x5, 0x5, 0x12, 0x0, 0x2e, +0xc2, 0x5, 0x7e, 0xd, 0x33, 0x69, 0x30, 0x0, 0x4, 0x7a, 0x35, 0xc, 0x69, 0x30, 0x0, 0x2, +0xb, 0xa, 0x20, 0x2e, 0x14, 0x0, 0x8, 0x12, 0x0, 0x46, 0xd2, 0x5, 0x7e, 0x2d, 0x33, 0x69, +0x12, 0x0, 0x4, 0x69, 0x32, 0x0, 0x2, 0xb, 0x2a, 0x20, 0x12, 0xa, 0x6a, 0x2e, 0x34, 0x10, +0x0, 0x2, 0x5, 0x4f, 0x6d, 0x33, 0x7a, 0x35, 0x2e, 0x7e, 0x34, 0x1, 0x0, 0x7a, 0x35, 0x11, +0x7e, 0xd, 0x33, 0x69, 0x30, 0x0, 0x2, 0xb, 0xa, 0x20, 0x2e, 0x14, 0x0, 0x8, 0x12, 0xc, +0xde, 0x20, 0x0, 0x3, 0x2, 0x5, 0x52, 0x7e, 0x1d, 0x33, 0x29, 0xb1, 0x0, 0x8, 0xf5, 0x91, +0x2, 0x5, 0x52, 0x6d, 0x33, 0x7a, 0x35, 0x2e, 0x7a, 0x35, 0x30, 0x7e, 0x18, 0x0, 0x16, 0x7a, +0x1d, 0xa, 0x7e, 0xd, 0x33, 0x69, 0x30, 0x0, 0x2, 0xb, 0xa, 0x20, 0x69, 0x10, 0x0, 0x4, +0x12, 0x3, 0x34, 0x12, 0x0, 0x2e, 0x7e, 0x34, 0xf0, 0x55, 0x2, 0x5, 0x4f, 0x6d, 0x33, 0x7a, +0x35, 0x2e, 0x7a, 0x35, 0x30, 0xe5, 0x37, 0xb4, 0xa, 0x15, 0xe5, 0x23, 0xb4, 0x80, 0xb, 0xe4, +0x12, 0xb, 0x8, 0x74, 0x1, 0x12, 0xb, 0x8, 0x80, 0x4e, 0x12, 0x6, 0xd8, 0x80, 0x49, 0xe5, +0x37, 0xb4, 0xb, 0x27, 0xe5, 0x23, 0xb4, 0x80, 0x11, 0x7e, 0xf0, 0x1, 0x7c, 0xbf, 0x12, 0x5, +0x6d, 0xb, 0xf0, 0xbe, 0xf0, 0x11, 0x78, 0xf4, 0x80, 0x2e, 0x7e, 0xf0, 0x4, 0x7c, 0xbf, 0x12, +0x5, 0x6d, 0xb, 0xf0, 0xbe, 0xf0, 0x40, 0x78, 0xf4, 0x80, 0x1d, 0xe5, 0x37, 0xa, 0x3b, 0x9e, +0x34, 0x0, 0x80, 0x7c, 0xe7, 0x6c, 0xdd, 0x80, 0x9, 0x7c, 0xbe, 0x12, 0x5, 0x6d, 0xb, 0xe0, +0xb, 0xd0, 0xe5, 0x22, 0xbc, 0xbd, 0x38, 0xf1, 0x12, 0x0, 0x2e, 0x7e, 0x34, 0xf0, 0xaa, 0x7a, +0x35, 0x30, 0x30, 0x4, 0x11, 0x7e, 0x34, 0x13, 0x88, 0x12, 0xc, 0x72, 0x7e, 0x34, 0x13, 0x88, +0x12, 0xc, 0x72, 0x75, 0xe9, 0xff, 0x30, 0x6, 0x3, 0x2, 0x4, 0x26, 0x22, 0xca, 0xf8, 0x7c, +0xfb, 0xe5, 0x23, 0xb4, 0x80, 0x4a, 0xd2, 0x7, 0x12, 0xc, 0xcb, 0x74, 0x20, 0xca, 0xb8, 0xa, +0x3f, 0x6d, 0x22, 0x74, 0xc, 0x2f, 0x11, 0x14, 0x78, 0xfb, 0xda, 0xb8, 0x12, 0xc, 0x1a, 0xa9, +0xd2, 0xb4, 0x12, 0xd, 0x1e, 0x12, 0xc, 0xb6, 0x50, 0x9, 0x7e, 0x35, 0x19, 0xbe, 0x34, 0x1, +0xf4, 0x28, 0xf2, 0x7e, 0x35, 0x19, 0xbe, 0x34, 0x1, 0xf4, 0x38, 0x6, 0x12, 0xd, 0x39, 0x2, +0x6, 0x3f, 0xc2, 0x86, 0x7e, 0x34, 0x13, 0x88, 0x12, 0xc, 0x72, 0xd2, 0x86, 0x2, 0x6, 0x3f, +0x74, 0x1, 0x12, 0x8, 0x50, 0x74, 0x1, 0x6d, 0x33, 0x12, 0xa, 0xbd, 0xe4, 0x12, 0x8, 0xb8, +0x5e, 0x34, 0x80, 0x0, 0x7c, 0x4f, 0x6c, 0x55, 0x3e, 0x24, 0x4d, 0x32, 0x12, 0xa, 0xbd, 0x74, +0x4, 0x6d, 0x33, 0x12, 0xa, 0xbd, 0x7e, 0x34, 0x0, 0x50, 0x12, 0xa, 0xbd, 0x7e, 0x34, 0x0, +0x19, 0x12, 0xc, 0x72, 0x74, 0x4, 0x7e, 0x34, 0x0, 0x51, 0x12, 0xa, 0xbd, 0x7e, 0x34, 0xa2, +0x1c, 0x12, 0xc, 0x72, 0x74, 0x4, 0x7e, 0x34, 0x0, 0x11, 0x12, 0xa, 0xbd, 0x7e, 0x34, 0x0, +0x19, 0x12, 0xc, 0x72, 0x74, 0x4, 0x7e, 0x34, 0x0, 0x10, 0x12, 0xa, 0xbd, 0x7e, 0x34, 0x0, +0x19, 0x12, 0xc, 0x72, 0x74, 0x4, 0x6d, 0x33, 0x12, 0xa, 0xbd, 0x7e, 0x34, 0x0, 0x5, 0x12, +0xc, 0x72, 0xe4, 0x12, 0x8, 0x50, 0x74, 0x4, 0x7e, 0x34, 0xff, 0xf7, 0x12, 0xa, 0xbd, 0xda, +0xf8, 0x22, 0xca, 0x3b, 0x7f, 0x30, 0x7c, 0xb6, 0xf5, 0x12, 0x7c, 0xb7, 0xf5, 0x13, 0x74, 0x1, +0x7e, 0x35, 0x10, 0x1e, 0x34, 0x1b, 0x34, 0x4e, 0x60, 0x80, 0x12, 0xa, 0xbd, 0x12, 0x8, 0x50, +0xa9, 0xc2, 0xb4, 0xa9, 0xc6, 0xb3, 0x75, 0xb5, 0x2, 0xa9, 0x36, 0xb3, 0xfc, 0xa9, 0xc6, 0xb3, +0x75, 0xb5, 0x0, 0xa9, 0x36, 0xb3, 0xfc, 0xa9, 0xc6, 0xb3, 0x85, 0x12, 0xb5, 0xa9, 0x36, 0xb3, +0xfc, 0xa9, 0xc6, 0xb3, 0x85, 0x13, 0xb5, 0xa9, 0x36, 0xb3, 0xfc, 0xa9, 0xc6, 0xb3, 0x6d, 0x33, +0x80, 0x2a, 0x7f, 0x13, 0x2e, 0x35, 0x14, 0x7e, 0x1b, 0xb0, 0xf5, 0xb5, 0xa9, 0x36, 0xb3, 0xfc, +0xa9, 0xc6, 0xb3, 0x7e, 0x35, 0x14, 0x5e, 0x34, 0x0, 0x1, 0xbe, 0x34, 0x0, 0x1, 0x78, 0x7, +0x7e, 0x34, 0x0, 0x78, 0x12, 0xc, 0x72, 0x7e, 0x35, 0x14, 0xb, 0x34, 0x7a, 0x35, 0x14, 0x7e, +0x35, 0x10, 0xbe, 0x35, 0x14, 0x38, 0xcb, 0xa9, 0xd2, 0xb4, 0x7e, 0x34, 0x0, 0x5, 0x12, 0xc, +0x72, 0xe4, 0x12, 0x8, 0x50, 0xda, 0x3b, 0x22, 0xe5, 0x23, 0xb4, 0x80, 0x16, 0xd2, 0x7, 0x12, +0xc, 0xcb, 0xa9, 0xc2, 0xb4, 0x74, 0x60, 0x12, 0xd, 0x13, 0xa9, 0xd2, 0xb4, 0x12, 0xc, 0xb6, +0x40, 0xfb, 0x22, 0x74, 0x1, 0x12, 0x8, 0x50, 0xe4, 0x6d, 0x33, 0x12, 0xa, 0xbd, 0x74, 0x1, +0x6d, 0x33, 0x12, 0xa, 0xbd, 0x74, 0x4, 0x6d, 0x33, 0x12, 0xa, 0xbd, 0x7e, 0x34, 0x0, 0x54, +0x12, 0xa, 0xbd, 0x7e, 0x34, 0x0, 0x19, 0x12, 0xc, 0x72, 0x74, 0x4, 0x7e, 0x34, 0x0, 0x55, +0x12, 0xa, 0xbd, 0x7e, 0x34, 0xa2, 0x1c, 0x12, 0xc, 0x72, 0x74, 0x4, 0x7e, 0x34, 0x0, 0x15, +0x12, 0xa, 0xbd, 0x7e, 0x34, 0x0, 0xa0, 0x12, 0xc, 0x72, 0x74, 0x4, 0x7e, 0x34, 0x0, 0x14, +0x12, 0xa, 0xbd, 0x7e, 0x34, 0x0, 0x19, 0x12, 0xc, 0x72, 0x74, 0x4, 0x7e, 0x34, 0x0, 0x4, +0x12, 0xa, 0xbd, 0x7e, 0x34, 0x0, 0x5, 0x12, 0xc, 0x72, 0xe4, 0x12, 0x8, 0x50, 0x74, 0x4, +0x7e, 0x34, 0xff, 0xf7, 0x2, 0xa, 0xbd, 0x75, 0x84, 0x1, 0x7e, 0x44, 0x1f, 0xff, 0xe4, 0x7a, +0x49, 0xb0, 0x1b, 0x44, 0x78, 0xf9, 0x7e, 0xf8, 0x2, 0xd9, 0xd2, 0x5, 0xc2, 0x6, 0x75, 0x16, +0x0, 0x75, 0x17, 0x87, 0x75, 0x18, 0xa6, 0x75, 0x19, 0x0, 0x75, 0x1a, 0x0, 0xd2, 0x0, 0xc2, +0x2, 0xc2, 0x3, 0xc2, 0x4, 0x75, 0x21, 0x0, 0x75, 0x22, 0x0, 0x75, 0x23, 0x80, 0x75, 0x2e, +0x0, 0x75, 0x2f, 0x0, 0x75, 0x30, 0x0, 0x75, 0x31, 0x0, 0x75, 0x32, 0x0, 0x75, 0x37, 0xb, +0x75, 0x38, 0x0, 0x75, 0x3d, 0x1, 0x7e, 0x4, 0x0, 0xff, 0x7e, 0x14, 0xd, 0x3c, 0xb, 0xa, +0x40, 0x5d, 0x44, 0x68, 0x1a, 0x69, 0x20, 0x0, 0x2, 0xb, 0xe, 0xb, 0x44, 0x80, 0xa, 0x7e, +0xb, 0xb0, 0x7a, 0x29, 0xb0, 0xb, 0x24, 0xb, 0xc, 0x1b, 0x44, 0x78, 0xf2, 0x80, 0xdf, 0x2, +0x4, 0x20, 0x7c, 0x7b, 0x7e, 0xa0, 0xef, 0xe5, 0x21, 0x24, 0xfd, 0x68, 0x38, 0x1b, 0xb1, 0x68, +0x22, 0x24, 0x9f, 0x68, 0x3d, 0x1b, 0xb2, 0x68, 0x3e, 0x24, 0x9e, 0x68, 0x35, 0x24, 0x3c, 0x78, +0x4c, 0xa5, 0xbf, 0x0, 0x5, 0x7e, 0xa1, 0x17, 0x80, 0x43, 0xa5, 0xbf, 0x1, 0x3f, 0x7e, 0xa1, +0x18, 0x80, 0x3a, 0xa5, 0xbf, 0x0, 0x5, 0x7e, 0xa1, 0x23, 0x80, 0x31, 0xa5, 0xbf, 0x1, 0x2d, +0x7e, 0xa1, 0x3d, 0x80, 0x28, 0xa, 0x17, 0x7e, 0x1d, 0x39, 0x2d, 0x31, 0x29, 0xa1, 0x0, 0x8, +0x80, 0x1b, 0x7e, 0xa1, 0x16, 0x80, 0x16, 0xa5, 0xbf, 0x0, 0x9, 0x7e, 0x35, 0x30, 0xa, 0x56, +0x7c, 0xab, 0x80, 0x9, 0xa5, 0xbf, 0x1, 0x5, 0x7e, 0x55, 0x30, 0x7c, 0xab, 0x7c, 0xba, 0x22, +0xca, 0x79, 0xbe, 0xb0, 0x0, 0x28, 0x2e, 0x74, 0x6, 0x12, 0x8, 0xb8, 0x7d, 0x73, 0x6c, 0xff, +0x7e, 0xf0, 0xa5, 0x7d, 0x37, 0x12, 0xa, 0xbd, 0x6c, 0xff, 0x7e, 0xf0, 0xf, 0x7d, 0x37, 0x12, +0xa, 0xbd, 0x6c, 0xff, 0x7e, 0xf0, 0x6a, 0x7d, 0x37, 0x12, 0xa, 0xbd, 0x7e, 0x34, 0x0, 0x5, +0x12, 0xc, 0x72, 0x80, 0x30, 0x74, 0x1, 0x7e, 0x34, 0xdf, 0xff, 0x12, 0xa, 0xbd, 0x74, 0x6, +0x12, 0x8, 0xb8, 0x7d, 0x73, 0x6c, 0xff, 0x7d, 0x37, 0x12, 0xa, 0xbd, 0x7d, 0x37, 0x12, 0xa, +0xbd, 0x7d, 0x37, 0x12, 0xa, 0xbd, 0x74, 0x2, 0x12, 0x8, 0xb8, 0x7d, 0x73, 0x4e, 0xf0, 0x1, +0x7d, 0x37, 0x12, 0xa, 0xbd, 0xda, 0x79, 0x22, 0xa9, 0xc2, 0xb4, 0xa9, 0xc6, 0xb3, 0x75, 0xb5, +0x5, 0xa9, 0x36, 0xb3, 0xfc, 0xa9, 0xc6, 0xb3, 0x75, 0xb5, 0x0, 0xa9, 0x36, 0xb3, 0xfc, 0xa9, +0xc6, 0xb3, 0x75, 0xb5, 0x0, 0xa9, 0x36, 0xb3, 0xfc, 0xa9, 0xc6, 0xb3, 0xf5, 0xb5, 0xa9, 0x36, +0xb3, 0xfc, 0xa9, 0xc6, 0xb3, 0x75, 0xb5, 0x0, 0xa9, 0x36, 0xb3, 0xfc, 0xa9, 0xc6, 0xb3, 0x75, +0xb5, 0x0, 0xa9, 0x36, 0xb3, 0xfc, 0xa9, 0xc6, 0xb3, 0x7e, 0x71, 0xb5, 0x75, 0xb5, 0x0, 0xa9, +0x36, 0xb3, 0xfc, 0xa9, 0xc6, 0xb3, 0x7e, 0xa1, 0xb5, 0xa9, 0xd2, 0xb4, 0x7c, 0x47, 0x6c, 0x55, +0xa, 0x3a, 0x4d, 0x32, 0x22, 0xca, 0xf8, 0x7e, 0xf0, 0x70, 0x75, 0x91, 0x0, 0xc2, 0x90, 0xc2, +0x91, 0x20, 0x87, 0x3, 0x7e, 0xf1, 0xe4, 0x30, 0x6, 0x30, 0x7e, 0x34, 0x0, 0x2, 0x7a, 0x35, +0x11, 0x7e, 0x18, 0x7, 0x80, 0x7e, 0x8, 0x0, 0x8, 0x12, 0xc, 0xde, 0xe5, 0x8, 0xbe, 0xb0, +0xff, 0x68, 0x17, 0xe5, 0x8, 0x60, 0x13, 0xe5, 0x9, 0xa, 0x2b, 0xe5, 0x8, 0xa, 0x3b, 0x2d, +0x32, 0xbe, 0x34, 0x0, 0xff, 0x78, 0x3, 0x7e, 0xf1, 0x8, 0x5e, 0xf0, 0xfe, 0x7a, 0xf1, 0x92, +0xd2, 0xe8, 0xc2, 0xc0, 0xa9, 0xd5, 0xb7, 0xd2, 0xbd, 0xd2, 0xad, 0xda, 0xf8, 0x22, 0x7f, 0x70, +0xd2, 0x7, 0x12, 0xc, 0xcb, 0x74, 0x2, 0x12, 0xc, 0x1a, 0x6d, 0x33, 0x80, 0x12, 0x7f, 0x7, +0x2d, 0x13, 0x7e, 0xb, 0xb0, 0xf5, 0xb5, 0xa9, 0x36, 0xb3, 0xfc, 0xa9, 0xc6, 0xb3, 0xb, 0x34, +0x7e, 0x25, 0x10, 0xbd, 0x23, 0x38, 0xe7, 0xa9, 0xd2, 0xb4, 0x12, 0xd, 0x1e, 0x12, 0xc, 0xb6, +0x50, 0x9, 0x7e, 0x35, 0x19, 0xbe, 0x34, 0x1, 0xf4, 0x28, 0xf2, 0x7e, 0x35, 0x19, 0xbe, 0x34, +0x1, 0xf4, 0x38, 0x3, 0x2, 0xd, 0x39, 0xc2, 0x86, 0x7e, 0x34, 0x13, 0x88, 0x12, 0xc, 0x72, +0xd2, 0x86, 0x22, 0xa9, 0xd1, 0xcb, 0xd2, 0xcc, 0x7e, 0x34, 0x0, 0x4, 0x7e, 0x8, 0x2, 0x56, +0x74, 0xc, 0x12, 0xa, 0x17, 0xa9, 0xd1, 0xcb, 0xc2, 0xcc, 0x6c, 0xaa, 0x7e, 0x70, 0x2, 0xac, +0x7a, 0x7e, 0x8, 0x2, 0x56, 0x2d, 0x13, 0xb, 0xa, 0x30, 0x7d, 0x23, 0x7c, 0x45, 0x6c, 0x55, +0xa, 0x36, 0x4d, 0x32, 0x1b, 0xa, 0x30, 0xb, 0xa0, 0xbe, 0xa0, 0xc, 0x78, 0xde, 0x7e, 0x37, +0x2, 0x66, 0x7d, 0x23, 0xa, 0x54, 0x7c, 0xa7, 0xb4, 0xe7, 0xb, 0xbe, 0xa0, 0x16, 0x78, 0x6, +0x75, 0x17, 0xe7, 0x75, 0x18, 0xa6, 0x22, 0x7e, 0x24, 0x0, 0x1, 0x7e, 0x7f, 0x2, 0xd6, 0x79, +0x27, 0x0, 0x6, 0x7e, 0x7f, 0x2, 0xd6, 0x69, 0x27, 0x0, 0x6, 0x4d, 0x22, 0x78, 0xf4, 0x5e, +0x60, 0x7f, 0x1b, 0x7a, 0x30, 0x7e, 0x1f, 0x2, 0xd6, 0x69, 0x31, 0x0, 0x8, 0x4d, 0x33, 0x68, +0xf4, 0x6c, 0xaa, 0x80, 0x20, 0x6d, 0x44, 0x7e, 0x1f, 0x2, 0xd6, 0x1b, 0x1a, 0x40, 0x7e, 0x1f, +0x2, 0xd6, 0x69, 0x41, 0x0, 0x8, 0x4d, 0x44, 0x68, 0xf4, 0x69, 0x41, 0x0, 0x2, 0x1b, 0xa, +0x40, 0xb, 0x15, 0xb, 0xa0, 0xbc, 0xba, 0x38, 0xdc, 0x22, 0x6d, 0x0, 0x74, 0x10, 0x4d, 0x0, +0x78, 0xb, 0x4d, 0x22, 0x78, 0x27, 0x8d, 0x31, 0x7d, 0x12, 0x6d, 0x22, 0x22, 0x7d, 0x43, 0x7d, +0x32, 0x6d, 0x22, 0x2f, 0x11, 0x2d, 0x44, 0x50, 0x2, 0xa5, 0xf, 0xbf, 0x10, 0x40, 0x4, 0x9f, +0x10, 0xb, 0x90, 0x14, 0x78, 0xed, 0x7f, 0x1, 0x6d, 0x22, 0x7d, 0x34, 0x22, 0x7d, 0x41, 0x7d, +0x13, 0x8d, 0x24, 0x7d, 0x2, 0x2f, 0x0, 0x40, 0x4, 0xbd, 0x4, 0x40, 0x4, 0x9d, 0x4, 0xb, +0x14, 0x14, 0x78, 0xf1, 0x7d, 0x23, 0x7d, 0x31, 0x7d, 0x10, 0x6d, 0x0, 0x22, 0x7d, 0x23, 0xa, +0x36, 0x7c, 0xa5, 0xa9, 0xc2, 0xb4, 0xa9, 0xc6, 0xb3, 0x75, 0xb5, 0x1, 0xa9, 0x36, 0xb3, 0xfc, +0xa9, 0xc6, 0xb3, 0x75, 0xb5, 0x0, 0xa9, 0x36, 0xb3, 0xfc, 0xa9, 0xc6, 0xb3, 0x75, 0xb5, 0x0, +0xa9, 0x36, 0xb3, 0xfc, 0xa9, 0xc6, 0xb3, 0xf5, 0xb5, 0xa9, 0x36, 0xb3, 0xfc, 0xa9, 0xc6, 0xb3, +0x7a, 0x71, 0xb5, 0xa9, 0x36, 0xb3, 0xfc, 0xa9, 0xc6, 0xb3, 0x7a, 0xa1, 0xb5, 0xa9, 0x36, 0xb3, +0xfc, 0xa9, 0xc6, 0xb3, 0xa9, 0xd2, 0xb4, 0x22, 0x7c, 0xab, 0xd2, 0x7, 0x12, 0xc, 0xcb, 0x74, +0xd8, 0xa, 0x3a, 0x7d, 0x23, 0x6d, 0x33, 0x12, 0xc, 0x1a, 0xa9, 0xd2, 0xb4, 0x12, 0xd, 0x1e, +0x12, 0xc, 0xb6, 0x50, 0x9, 0x7e, 0x35, 0x19, 0xbe, 0x34, 0x5, 0xdc, 0x28, 0xf2, 0x7e, 0x35, +0x19, 0xbe, 0x34, 0x5, 0xdc, 0x38, 0x3, 0x2, 0xd, 0x39, 0xc2, 0x86, 0x7e, 0x34, 0x13, 0x88, +0x12, 0xc, 0x72, 0xd2, 0x86, 0x22, 0xca, 0x2b, 0xca, 0x1b, 0xca, 0xb, 0xd2, 0x0, 0x30, 0x90, +0x1c, 0xc2, 0x90, 0x7e, 0x71, 0x91, 0xe5, 0x38, 0x70, 0x3, 0x7a, 0x71, 0x21, 0xe5, 0x38, 0x12, +0x1, 0x20, 0x5, 0x38, 0x30, 0x2, 0x6, 0xe4, 0x12, 0x7, 0xe2, 0xf5, 0x91, 0x30, 0x91, 0xb, +0xc2, 0x91, 0x5, 0x38, 0xe5, 0x38, 0x12, 0x7, 0xe2, 0xf5, 0x91, 0xda, 0xb, 0xda, 0x1b, 0xda, +0x2b, 0x32, 0xca, 0xf8, 0x7c, 0xfb, 0xe5, 0x23, 0xb4, 0x81, 0x23, 0x74, 0x2, 0x12, 0x8, 0xb8, +0x4c, 0xff, 0x78, 0x8, 0xa9, 0xc0, 0xca, 0x5e, 0x70, 0xdf, 0x80, 0x6, 0xa9, 0xd0, 0xca, 0x4e, +0x70, 0x20, 0x74, 0x2, 0x12, 0xa, 0xbd, 0x74, 0x2, 0x12, 0x8, 0xb8, 0x80, 0x8, 0xe5, 0x23, +0xb4, 0x80, 0x3, 0x12, 0xb, 0xec, 0xda, 0xf8, 0x22, 0xd2, 0x7, 0x12, 0xc, 0xcb, 0xa9, 0xc2, +0xb4, 0x74, 0x9f, 0x12, 0xd, 0x13, 0x12, 0xc, 0xfa, 0xa9, 0xd2, 0xb4, 0x60, 0x3, 0xb4, 0xff, +0x1a, 0x75, 0x23, 0x81, 0xa9, 0xd5, 0xca, 0xa9, 0xd0, 0xca, 0x75, 0xed, 0x9f, 0x75, 0xad, 0x20, +0xa9, 0xd1, 0xea, 0xa9, 0xc1, 0xea, 0x74, 0x1, 0x2, 0xb, 0x82, 0x22, 0xd2, 0x7, 0x12, 0xc, +0xcb, 0xa9, 0xc2, 0xb4, 0x74, 0x5, 0x12, 0xd, 0x13, 0x12, 0xc, 0xfa, 0x7c, 0xab, 0xa9, 0xd2, +0xb4, 0x5e, 0xa0, 0xe3, 0xa9, 0xc2, 0xb4, 0x74, 0x1, 0x12, 0xd, 0x13, 0x7c, 0xba, 0x12, 0xd, +0x13, 0xa9, 0xd2, 0xb4, 0x12, 0xc, 0xb6, 0x40, 0xfb, 0x22, 0x7c, 0xab, 0x7d, 0x12, 0x7c, 0xb3, +0xf5, 0x14, 0x7c, 0x36, 0x7c, 0x25, 0xa, 0x4, 0x7c, 0xb3, 0xf5, 0x13, 0x7c, 0xb7, 0xf5, 0x12, +0xa9, 0xc2, 0xb4, 0x7c, 0xba, 0x12, 0xd, 0x13, 0xe5, 0x14, 0x12, 0xd, 0x13, 0xe5, 0x13, 0x12, +0xd, 0x13, 0xe5, 0x12, 0x2, 0xd, 0x13, 0x7d, 0x52, 0xf5, 0x15, 0x7c, 0xb6, 0x7c, 0xa5, 0xa, +0x44, 0xf5, 0x14, 0x7f, 0x21, 0xf5, 0x13, 0xa9, 0xc2, 0xb4, 0x74, 0xb, 0x12, 0xd, 0x13, 0xe5, +0x15, 0x12, 0xd, 0x13, 0xe5, 0x14, 0x12, 0xd, 0x13, 0xe5, 0x13, 0x12, 0xd, 0x13, 0xe4, 0x2, +0xd, 0x13, 0x80, 0x18, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0xe5, 0x3d, +0x70, 0xa, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x7d, 0x23, 0x1b, 0x34, +0x4d, 0x22, 0x78, 0xe0, 0x22, 0xd2, 0xcf, 0x85, 0x3d, 0xcc, 0x75, 0xec, 0xff, 0x75, 0xee, 0xff, +0x75, 0xeb, 0x3, 0x75, 0xac, 0xc0, 0xa9, 0xc5, 0xca, 0x75, 0xed, 0xf, 0x75, 0xad, 0xb0, 0xa9, +0xd7, 0x94, 0xa9, 0xd4, 0x94, 0x22, 0xa9, 0xc2, 0xb4, 0x74, 0x5, 0x12, 0xd, 0x13, 0x12, 0xc, +0xfa, 0xa9, 0xd2, 0xb4, 0x30, 0xe0, 0x2, 0xd3, 0x22, 0xc3, 0x22, 0xa9, 0xc2, 0xb4, 0x30, 0x7, +0x4, 0x74, 0x6, 0x80, 0x2, 0x74, 0x4, 0x12, 0xd, 0x13, 0xa9, 0xd2, 0xb4, 0x22, 0x12, 0xc, +0x47, 0x7e, 0x35, 0x11, 0x12, 0x0, 0xe, 0xa9, 0xd2, 0xb4, 0xd3, 0x22, 0xc2, 0x8c, 0x43, 0x89, +0x2, 0x75, 0x8c, 0x1, 0x75, 0x8a, 0x0, 0xd2, 0xa9, 0x22, 0x75, 0xb5, 0x0, 0xa9, 0x36, 0xb3, +0xfc, 0xa9, 0xc6, 0xb3, 0xe5, 0xb5, 0x22, 0xd2, 0xc8, 0x75, 0xb3, 0x13, 0xa9, 0xd1, 0xb4, 0xa9, +0xc0, 0xb4, 0x22, 0xf5, 0xb5, 0xa9, 0x36, 0xb3, 0xfc, 0xa9, 0xc6, 0xb3, 0xd3, 0x22, 0xc2, 0x8c, +0x6d, 0x33, 0x7a, 0x35, 0x19, 0xd2, 0x8c, 0x22, 0x7e, 0x35, 0x19, 0xb, 0x34, 0x7a, 0x35, 0x19, +0x22, 0x85, 0x3d, 0xcc, 0xe5, 0x3d, 0x2, 0xb, 0x82, 0x2, 0xd, 0x28, 0x0, 0x4, 0x2, 0xd6, +0x0, 0x0, 0x9c, 0x0, 0x0, 0x0, }; #endif diff --git a/drivers/input/touchscreen/fts_521/fts.c b/drivers/input/touchscreen/fts_521/fts.c index 43148c582f30..09a7857dc5d7 100644 --- a/drivers/input/touchscreen/fts_521/fts.c +++ b/drivers/input/touchscreen/fts_521/fts.c @@ -44,11 +44,6 @@ #include #include #include -#ifdef CONFIG_SECURE_TOUCH -#include -#include -#include -#endif #include #include @@ -58,14 +53,12 @@ #ifdef CONFIG_DRM #include #endif -#include - #include #include #include #include -#include + #ifdef KERNEL_ABOVE_2_6_38 #include #endif @@ -84,9 +77,6 @@ #ifdef CONFIG_INPUT_PRESS_NDT #include "./../ndt_core.h" #endif -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE -#include "../xiaomi/xiaomi_touch.h" -#endif /** * Event handler installer helpers @@ -151,7 +141,7 @@ static u8 key_mask; #ifdef CONFIG_INPUT_PRESS_NDT bool fts_fod_status; #endif -extern void lpm_disable_for_input(bool on); + extern spinlock_t fts_int; struct fts_ts_info *fts_info; @@ -159,11 +149,6 @@ static int fts_init_sensing(struct fts_ts_info *info); static int fts_mode_handler(struct fts_ts_info *info, int force); static int fts_chip_initialization(struct fts_ts_info *info, int init_type); static const char *fts_get_limit(struct fts_ts_info *info); -extern const char *dsi_get_display_name(void); - -static irqreturn_t fts_event_handler(int irq, void *ts_info); -bool wait_queue_complete; - /** * Release all the touches in the linux input subsystem @@ -186,7 +171,6 @@ void release_all_touches(struct fts_ts_info *info) input_report_abs(info->input_dev, ABS_MT_TRACKING_ID, -1); } input_sync(info->input_dev); - lpm_disable_for_input(false); info->touch_id = 0; #ifdef STYLUS_MODE info->stylus_id = 0; @@ -2219,11 +2203,11 @@ static ssize_t fts_doze_time_store(struct device *dev, /*reg value * 10 represents of the num of frames ,one frame is about 8ms, the input value is ms*/ reg_val = (info->doze_time / 8 - 1) / 10; cmd[3] = reg_val; - ret = fts_write_dma_safe(cmd, ARRAY_SIZE(cmd)); + ret = fts_write(cmd, ARRAY_SIZE(cmd)); if (ret < OK) { logError(1, "%s %s: write failed...ERROR %08X !\n", tag, __func__, ret); - return -EPERM; + return ret; } return count; } @@ -2247,887 +2231,42 @@ static ssize_t fts_grip_enable_store(struct device *dev, pr_info("%s,buf:%s,count:%zu\n", __func__, buf, count); sscanf(buf, "%u", &info->grip_enabled); cmd[2] = info->grip_enabled; - ret = fts_write_dma_safe(cmd, ARRAY_SIZE(cmd)); + ret = fts_write(cmd, ARRAY_SIZE(cmd)); if (ret < OK) { logError(1, "%s %s: write failed...ERROR %08X !\n", tag, __func__, ret); - return -EPERM; - } - return count; -} - -static ssize_t fts_grip_area_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct fts_ts_info *info = dev_get_drvdata(dev); - - return snprintf(buf, TSP_BUF_SIZE, "%d\n", info->grip_pixel); -} - -static ssize_t fts_grip_area_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - u8 cmd[4] = {FTS_CMD_CUSTOM, 0x01, 0x01, 0x00}; - int ret = 0; - struct fts_ts_info *info = dev_get_drvdata(dev); -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_GAMEMODE - return -EPERM; -#endif - logError(1, " %s %s,buf:%s,count:%zu\n", tag, __func__, buf, count); - sscanf(buf, "%u", &info->grip_pixel); - cmd[3] = info->grip_pixel; - if (atomic_read(&info->system_is_resetting)) { - logError(1, "%s %s system is resetting ,wait reset done\n", tag, __func__); - ret = wait_for_completion_timeout(&info->tp_reset_completion, msecs_to_jiffies(40)); - if (!ret) { - logError(1, "%s %s wait tp reset timeout, wrtie grip area error\n", tag, __func__); - return count; - } - } - ret = fts_write_dma_safe(cmd, ARRAY_SIZE(cmd)); - if (ret < OK) { - logError(1, "%s %s: write failed...ERROR %08X !\n", tag, - __func__, ret); - return -EPERM; - } - return count; -} - -static ssize_t fts_fod_status_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct fts_ts_info *info = dev_get_drvdata(dev); - - return snprintf(buf, TSP_BUF_SIZE, "%d\n", info->fod_status); -} - -static ssize_t fts_fod_status_store(struct device *dev, - struct device_attribute *attr, - const char *buf, size_t count) -{ - struct fts_ts_info *info = dev_get_drvdata(dev); - - logError(1, " %s %s,buf:%s,count:%zu\n", tag, __func__, buf, count); - sscanf(buf, "%u", &info->fod_status); - return count; -} - -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE -static struct xiaomi_touch_interface xiaomi_touch_interfaces; -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_GAMEMODE -static ssize_t fts_touchgame_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - u8 get_value[7] = {0x0,}; - u8 get_cmd[2] = {0xc1, 0x05}; - u8 grip_rcmd[2] = {0xc1, 0x08}; - u8 grip_value[7] = {0x0,}; - int ret; - - ret = fts_writeRead(get_cmd, sizeof(get_cmd) / sizeof(u8), get_value, - sizeof(get_value) / sizeof(u8)); - if (ret < OK) { - logError(1, - "%s %s: error while reading touchmode data ERROR %08X\n", - tag, __func__, ret); - } - ret = fts_writeRead(grip_rcmd, sizeof(grip_rcmd) / sizeof(u8), grip_value, - sizeof(grip_value) / sizeof(u8)); - if (ret < OK) { - logError(1, - "%s %s: error while reading edge filter data ERROR %08X\n", - tag, __func__, ret); - } - - return snprintf(buf, PAGE_SIZE, "game mode:%d,%d,%d,%d,%d,%d,%d\n" - "grip mode:0x%x, 0x%x, 0x%x, %d, %d, %d, %d\n", - get_value[0], get_value[1], get_value[2], get_value[3], - get_value[4], get_value[5], get_value[6], - grip_value[0], grip_value[1], grip_value[2], grip_value[3], - grip_value[4], grip_value[5], grip_value[6]); -} - -static int fts_read_touchmode_data(void) -{ - int ret = 0; - u8 get_cmd[2] = {0xc1, 0x05}; - u8 get_value[Touch_Mode_NUM] = {0x0,}; - u8 grip_cmd[2] = {0xc1, 0x08}; - u8 grip_value[Touch_Mode_NUM] = {0x0,}; - int readBytes = 7; - int i; - - ret = fts_writeRead(get_cmd, sizeof(get_cmd) / sizeof(u8), get_value, - readBytes); - if (ret < OK) { - logError(1, - "%s %s: error while reading touchmode data ERROR %08X\n", - tag, __func__, ret); - return -EINVAL; - } - ret = fts_writeRead(grip_cmd, sizeof(grip_cmd) / sizeof(u8), grip_value, - readBytes); - if (ret < OK) { - logError(1, - "%s %s: error while reading edge filter data ERROR %08X\n", - tag, __func__, ret); - return -EINVAL; - } - - for (i = 0; i < Touch_Mode_NUM; i++) { - if (i == Touch_Edge_Filter) - xiaomi_touch_interfaces.touch_mode[i][GET_CUR_VALUE] = grip_value[0]; - else - xiaomi_touch_interfaces.touch_mode[i][GET_CUR_VALUE] = get_value[i]; - } - - for (i = 0; i < 7; i++) { - xiaomi_touch_interfaces.touch_edge[i] = grip_value[i]; - } - - logError(1, - "%s %s: game_mode:%d, active_mode:%d, up_threshold:%d, landlock:%d, wgh:%d, %d, %d\n", - tag, __func__, get_value[0], get_value[1], get_value[2], get_value[3], - get_value[4], get_value[5], get_value[6]); - logError(1, - "%s %s: grip:0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", - tag, __func__, grip_value[0], grip_value[1], grip_value[2], grip_value[3], - grip_value[4], grip_value[5], grip_value[6]); - - return ret; -} - -static void fts_init_touchmode_data(void) -{ - int i; - struct fts_hw_platform_data *bdata = NULL; - - if (!fts_info) - return; - else - bdata = fts_info->board; - - /* default value should equl the first initial value */ - for (i = 0; i < Touch_Mode_NUM; i++) { - xiaomi_touch_interfaces.touch_mode[i][GET_DEF_VALUE] = - xiaomi_touch_interfaces.touch_mode[i][GET_CUR_VALUE]; - xiaomi_touch_interfaces.touch_mode[i][SET_CUR_VALUE] = - xiaomi_touch_interfaces.touch_mode[i][GET_CUR_VALUE]; - } - /* Touch Game Mode Switch */ - xiaomi_touch_interfaces.touch_mode[Touch_Game_Mode][GET_MAX_VALUE] = 1; - xiaomi_touch_interfaces.touch_mode[Touch_Game_Mode][GET_MIN_VALUE] = 0; - xiaomi_touch_interfaces.touch_mode[Touch_Game_Mode][GET_DEF_VALUE] = 0; - - /* Acitve Mode */ - xiaomi_touch_interfaces.touch_mode[Touch_Active_MODE][GET_MAX_VALUE] = 1; - xiaomi_touch_interfaces.touch_mode[Touch_Active_MODE][GET_MIN_VALUE] = 0; - xiaomi_touch_interfaces.touch_mode[Touch_Active_MODE][GET_DEF_VALUE] = 0; - - /* finger hysteresis */ - xiaomi_touch_interfaces.touch_mode[Touch_UP_THRESHOLD][GET_DEF_VALUE] = bdata->touch_up_threshold_def; - xiaomi_touch_interfaces.touch_mode[Touch_UP_THRESHOLD][SET_CUR_VALUE] = bdata->touch_up_threshold_def; - xiaomi_touch_interfaces.touch_mode[Touch_UP_THRESHOLD][GET_CUR_VALUE] = bdata->touch_up_threshold_def; - xiaomi_touch_interfaces.touch_mode[Touch_UP_THRESHOLD][GET_MAX_VALUE] = bdata->touch_up_threshold_max; - xiaomi_touch_interfaces.touch_mode[Touch_UP_THRESHOLD][GET_MIN_VALUE] = bdata->touch_up_threshold_min; - - /* Tolerance */ - xiaomi_touch_interfaces.touch_mode[Touch_Tolerance][GET_DEF_VALUE] = bdata->touch_tolerance_def; - xiaomi_touch_interfaces.touch_mode[Touch_Tolerance][GET_MAX_VALUE] = bdata->touch_tolerance_max; - xiaomi_touch_interfaces.touch_mode[Touch_Tolerance][GET_MIN_VALUE] = bdata->touch_tolerance_min; - xiaomi_touch_interfaces.touch_mode[Touch_Tolerance][SET_CUR_VALUE] = bdata->touch_tolerance_def; - xiaomi_touch_interfaces.touch_mode[Touch_Tolerance][GET_CUR_VALUE] = bdata->touch_tolerance_def; - - /* Wgh Min */ - xiaomi_touch_interfaces.touch_mode[Touch_Wgh_Min][GET_DEF_VALUE] = 1; - xiaomi_touch_interfaces.touch_mode[Touch_Wgh_Min][GET_CUR_VALUE] = 1; - xiaomi_touch_interfaces.touch_mode[Touch_Wgh_Min][SET_CUR_VALUE] = 1; - xiaomi_touch_interfaces.touch_mode[Touch_Wgh_Min][GET_MAX_VALUE] = 15; - xiaomi_touch_interfaces.touch_mode[Touch_Wgh_Min][GET_MIN_VALUE] = 0; - - /* Wgh Max */ - xiaomi_touch_interfaces.touch_mode[Touch_Wgh_Max][GET_DEF_VALUE] = 5; - xiaomi_touch_interfaces.touch_mode[Touch_Wgh_Max][GET_CUR_VALUE] = 5; - xiaomi_touch_interfaces.touch_mode[Touch_Wgh_Max][SET_CUR_VALUE] = 5; - xiaomi_touch_interfaces.touch_mode[Touch_Wgh_Max][GET_MAX_VALUE] = 15; - xiaomi_touch_interfaces.touch_mode[Touch_Wgh_Max][GET_MIN_VALUE] = 0; - - /* Wgh Step */ - xiaomi_touch_interfaces.touch_mode[Touch_Wgh_Step][GET_DEF_VALUE] = 1; - xiaomi_touch_interfaces.touch_mode[Touch_Wgh_Step][GET_CUR_VALUE] = 1; - xiaomi_touch_interfaces.touch_mode[Touch_Wgh_Step][SET_CUR_VALUE] = 1; - xiaomi_touch_interfaces.touch_mode[Touch_Wgh_Step][GET_MAX_VALUE] = 2; - xiaomi_touch_interfaces.touch_mode[Touch_Wgh_Step][GET_MIN_VALUE] = 0; - - /* edge filter */ - xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][GET_MAX_VALUE] = 3; - xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][GET_MIN_VALUE] = 0; - xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][GET_DEF_VALUE] = 2; - xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][SET_CUR_VALUE] = 2; - xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][GET_CUR_VALUE] = 2; - - /* Orientation */ - xiaomi_touch_interfaces.touch_mode[Touch_Panel_Orientation][GET_MAX_VALUE] = 3; - xiaomi_touch_interfaces.touch_mode[Touch_Panel_Orientation][GET_MIN_VALUE] = 0; - xiaomi_touch_interfaces.touch_mode[Touch_Panel_Orientation][GET_DEF_VALUE] = 0; - xiaomi_touch_interfaces.touch_mode[Touch_Panel_Orientation][SET_CUR_VALUE] = 0; - xiaomi_touch_interfaces.touch_mode[Touch_Panel_Orientation][GET_CUR_VALUE] = 0; - - for (i = 0; i < Touch_Mode_NUM; i++) { - logError(1, - "%s %s: mode:%d, set cur:%d, get cur:%d, def:%d min:%d max:%d\n", - tag, __func__, - i, - xiaomi_touch_interfaces.touch_mode[i][SET_CUR_VALUE], - xiaomi_touch_interfaces.touch_mode[i][GET_CUR_VALUE], - xiaomi_touch_interfaces.touch_mode[i][GET_DEF_VALUE], - xiaomi_touch_interfaces.touch_mode[i][GET_MIN_VALUE], - xiaomi_touch_interfaces.touch_mode[i][GET_MAX_VALUE]); - } - - return; -} - -static void fts_edge_rejection(bool on, int value) -{ - /* the fixed edge_reject is 65 */ - int ret = 0; - u8 edge_of_leftright[4] = {0xc0, 0x01, 0x00, 0x00}; - u8 edge_of_topbottom[4] = {0xc0, 0x01, 0x01, 0x00}; - struct fts_hw_platform_data *pdata = NULL; - - if (!fts_info) - return; - else - pdata = fts_info->board; - - if (on) { - edge_of_topbottom[3] = value; - edge_of_leftright[3] = 0; - } else { - edge_of_leftright[3] = pdata->edgefilter_leftright_def; - edge_of_topbottom[3] = pdata->edgefilter_topbottom_def; - } - - ret = fts_write(edge_of_leftright, sizeof(edge_of_leftright) / sizeof(u8)); - if (ret < OK) { - logError(1, - "%s %s: error while writing edge left/right data ERROR %08X\n", - tag, __func__, ret); - return; - } - - ret = fts_write(edge_of_topbottom, sizeof(edge_of_topbottom) / sizeof(u8)); - if (ret < OK) { - logError(1, - "%s %s: error while writing edge top/bottom data ERROR %08X\n", - tag, __func__, ret); - return; - } - logError(1, "%s %s: on:%d, value:%d\n", - tag, __func__, on, value); - - return; -} - -static void fts_update_grip_mode(void) -{ - int i, ret; - u8 grip_cmd[9] = {0xc0, 0x08, 0x00,}; - u8 grip_rcmd[2] = {0xc1, 0x08}; - u8 grip_value[7] = {0x0,}; - int temp_value = 0; - bool topbottom_edge_filter = false; - int direction = 0; - struct fts_hw_platform_data *pdata = NULL; - - if (!fts_info) - return; - else - pdata = fts_info->board; - - logError(1, - "%s %s: value:%d\n", - tag, __func__, xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][SET_CUR_VALUE]); - switch (xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][SET_CUR_VALUE]) { - case 0: - temp_value = 0; - break; - case 1: - temp_value = pdata->edgefilter_area_step1; - break; - case 2: - temp_value = pdata->edgefilter_area_step2; - break; - case 3: - temp_value = pdata->edgefilter_area_step3; - break; - default: - temp_value = 0; - logError(1, - "%s %s: no support value %08d\n", - tag, __func__, temp_value); - break; - } - - direction = xiaomi_touch_interfaces.touch_mode[Touch_Panel_Orientation][SET_CUR_VALUE]; - - switch (direction) { - case 0: - case 2: - /* 0 and 180, filter the leftright edge */ - topbottom_edge_filter = false; - xiaomi_touch_interfaces.touch_edge[0] = 0; - xiaomi_touch_interfaces.touch_edge[1] = 0x0f; - xiaomi_touch_interfaces.touch_edge[2] = 0x00; - xiaomi_touch_interfaces.touch_edge[3] = 0; - xiaomi_touch_interfaces.touch_edge[4] = 0; - xiaomi_touch_interfaces.touch_edge[5] = 0; - xiaomi_touch_interfaces.touch_edge[6] = 0; - break; - case 1: - topbottom_edge_filter = true; - xiaomi_touch_interfaces.touch_edge[0] = 1; - xiaomi_touch_interfaces.touch_edge[1] = 0x0f; - xiaomi_touch_interfaces.touch_edge[2] = 0x00; - xiaomi_touch_interfaces.touch_edge[3] = temp_value; - xiaomi_touch_interfaces.touch_edge[4] = temp_value; - xiaomi_touch_interfaces.touch_edge[5] = 0; - xiaomi_touch_interfaces.touch_edge[6] = 0; - break; - case 3: - topbottom_edge_filter = true; - xiaomi_touch_interfaces.touch_edge[0] = 1; - xiaomi_touch_interfaces.touch_edge[1] = 0x0f; - xiaomi_touch_interfaces.touch_edge[2] = 0x00; - xiaomi_touch_interfaces.touch_edge[3] = 0; - xiaomi_touch_interfaces.touch_edge[4] = 0; - xiaomi_touch_interfaces.touch_edge[5] = temp_value; - xiaomi_touch_interfaces.touch_edge[6] = temp_value; - break; - default: - /* Dont't support */ - break; - }; - - if (!xiaomi_touch_interfaces.touch_mode[Touch_Game_Mode][GET_CUR_VALUE] || !topbottom_edge_filter) { - logError(1, - "%s %s: touch game mode off or portrait\n", - tag, __func__); - fts_edge_rejection(false, 0); - } - - xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][GET_CUR_VALUE] = - xiaomi_touch_interfaces.touch_mode[Touch_Edge_Filter][SET_CUR_VALUE]; - - for (i = 0; i < 7; i++) { - grip_cmd[2 + i] = (u8)(xiaomi_touch_interfaces.touch_edge[i]); - } - logError(1, - "%s %s: write grip:0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", - tag, __func__, grip_cmd[0], grip_cmd[1], grip_cmd[2], grip_cmd[3], - grip_cmd[4], grip_cmd[5], grip_cmd[6], grip_cmd[7], grip_cmd[8]); - - ret = fts_write(grip_cmd, sizeof(grip_cmd) / sizeof(u8)); - if (ret < OK) { - logError(1, - "%s %s: error while writing touchmode data ERROR %08X\n", - tag, __func__, ret); - return; - } - msleep(10); - ret = fts_writeRead(grip_rcmd, sizeof(grip_rcmd) / sizeof(u8), grip_value, - sizeof(grip_value) / sizeof(u8)); - if (ret < OK) { - logError(1, - "%s %s: error while reading edge filter data ERROR %08X\n", - tag, __func__, ret); - return; - } - logError(1, - "%s %s: read grip:0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n", - tag, __func__, grip_value[0], grip_value[1], grip_value[2], grip_value[3], - grip_value[4], grip_value[5], grip_value[6]); - - logError(1, - "%s %s: grip enable:%d, direction:%d\n", - tag, __func__, grip_value[0], direction); - - return; -} - -static void fts_update_touchmode_data(void) -{ - bool update = false; - int i, j, ret = 0; - u8 set_cmd[9] = {0xc0, 0x05, 0,}; - u8 get_cmd[2] = {0xc1, 0x05}; - u8 get_value[7] = {0x0,}; - int temp_value = 0; - - ret = wait_event_interruptible_timeout(fts_info->wait_queue, !(fts_info->irq_status), msecs_to_jiffies(500)); - - if (ret <= 0) { - logError(1, "%s %s: wait touch irq status timeout\n", tag, __func__); - return; - } - - mutex_lock(&fts_info->cmd_update_mutex); - for (i = 0; i < Touch_Mode_NUM; i++) { - if (xiaomi_touch_interfaces.touch_mode[i][GET_CUR_VALUE] != - xiaomi_touch_interfaces.touch_mode[i][SET_CUR_VALUE]) { - - xiaomi_touch_interfaces.touch_mode[i][GET_CUR_VALUE] = - xiaomi_touch_interfaces.touch_mode[i][SET_CUR_VALUE]; - logError(1, "%s %s: mode:%d changed, value:%d\n", tag, __func__, i, - xiaomi_touch_interfaces.touch_mode[i][SET_CUR_VALUE]); - update = true; - } - } - - if (update) { - for (j = 2; j < sizeof(set_cmd) / sizeof(u8); j++) { - if (j - 2 == Touch_UP_THRESHOLD || - j - 2 == Touch_Tolerance) - temp_value = xiaomi_touch_interfaces.touch_mode[j - 2][GET_MAX_VALUE] - - xiaomi_touch_interfaces.touch_mode[j - 2][GET_CUR_VALUE] + xiaomi_touch_interfaces.touch_mode[j - 2][GET_MIN_VALUE]; - else - temp_value = (xiaomi_touch_interfaces.touch_mode[j - 2][GET_CUR_VALUE]); - - set_cmd[j] = (u8)temp_value; - } - logError(1, - "%s %s: write game:0x%x, 0x%x, %d, %d, %d, %d, %d, %d, %d\n", - tag, __func__, set_cmd[0], set_cmd[1], set_cmd[2], set_cmd[3], - set_cmd[4], set_cmd[5], set_cmd[6], set_cmd[7], set_cmd[8]); - - ret = fts_write(set_cmd, sizeof(set_cmd) / sizeof(u8)); - if (ret < OK) { - logError(1, - "%s %s: error while writing touchmode data ERROR %08X\n", - tag, __func__, ret); - goto end; - } - - ret = fts_writeRead(get_cmd, sizeof(get_cmd) / sizeof(u8), get_value, - sizeof(get_value) / sizeof(u8)); - if (ret < OK) { - logError(1, - "%s %s: error while reading touchmode data ERROR %08X\n", - tag, __func__, ret); - goto end; - } - - logError(1, - "%s %s: read game:%d, active_mode:%d, up_threshold:%d, landlock:%d, wgh:%d, %d, %d\n", - tag, __func__, get_value[0], get_value[1], get_value[2], get_value[3], - get_value[4], get_value[5], get_value[6]); - fts_update_grip_mode(); - } else { - logError(1, "%s %s: no update\n", tag, __func__); - } - -end: - mutex_unlock(&fts_info->cmd_update_mutex); - return; -} - -static void fts_cmd_update_work(struct work_struct *work) -{ - fts_update_touchmode_data(); - - return; -} - -static int fts_set_cur_value(int mode, int value) -{ - - if (mode < Touch_Mode_NUM && mode >= 0) { - - xiaomi_touch_interfaces.touch_mode[mode][SET_CUR_VALUE] = value; - - if (xiaomi_touch_interfaces.touch_mode[mode][SET_CUR_VALUE] > - xiaomi_touch_interfaces.touch_mode[mode][GET_MAX_VALUE]) { - - xiaomi_touch_interfaces.touch_mode[mode][SET_CUR_VALUE] = - xiaomi_touch_interfaces.touch_mode[mode][GET_MAX_VALUE]; - - } else if (xiaomi_touch_interfaces.touch_mode[mode][SET_CUR_VALUE] < - xiaomi_touch_interfaces.touch_mode[mode][GET_MIN_VALUE]) { - - xiaomi_touch_interfaces.touch_mode[mode][SET_CUR_VALUE] = - xiaomi_touch_interfaces.touch_mode[mode][GET_MIN_VALUE]; - } - } else { - logError(1, "%s %s, don't support\n", tag, __func__); - } - logError(1, "%s %s, mode:%d, value:%d\n", tag, __func__, mode, value); - - queue_work(fts_info->touch_feature_wq, &fts_info->cmd_update_work); - - return 0; -} - -static int fts_get_mode_value(int mode, int value_type) -{ - int value = -1; - - if (mode < Touch_Mode_NUM && mode >= 0) - value = xiaomi_touch_interfaces.touch_mode[mode][value_type]; - else - logError(1, "%s, %s, don't support\n", tag, __func__); - - return value; -} - -static int fts_get_mode_all(int mode, int *value) -{ - if (mode < Touch_Mode_NUM && mode >= 0) { - value[0] = xiaomi_touch_interfaces.touch_mode[mode][GET_CUR_VALUE]; - value[1] = xiaomi_touch_interfaces.touch_mode[mode][GET_DEF_VALUE]; - value[2] = xiaomi_touch_interfaces.touch_mode[mode][GET_MIN_VALUE]; - value[3] = xiaomi_touch_interfaces.touch_mode[mode][GET_MAX_VALUE]; - } else { - logError(1, "%s %s, don't support\n", tag, __func__); - } - logError(1, "%s %s, mode:%d, value:%d:%d:%d:%d\n", tag, __func__, mode, value[0], - value[1], value[2], value[3]); - - return 0; -} - -static int fts_reset_mode(int mode) -{ - int i = 0; - - if (mode < Touch_Mode_NUM && mode > 0) { - xiaomi_touch_interfaces.touch_mode[mode][SET_CUR_VALUE] = - xiaomi_touch_interfaces.touch_mode[mode][GET_DEF_VALUE]; - } else if (mode == 0) { - for (i = 0; i < Touch_Mode_NUM; i++) { - xiaomi_touch_interfaces.touch_mode[i][SET_CUR_VALUE] = - xiaomi_touch_interfaces.touch_mode[i][GET_DEF_VALUE]; - } - } else { - logError(1, "%s %s, don't support\n", tag, __func__); - } - - logError(1, "%s %s, mode:%d\n", tag, __func__, mode); - - queue_work(fts_info->event_wq, &fts_info->cmd_update_work); - - return 0; -} -#endif - -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_SENSOR -static int fts_finger_report_disable(struct fts_ts_info *info, bool enable) -{ - u8 cmd[4] = {0xc0, 0x09, 0x00, 0x00}; - - if (enable) - cmd[2] = 0x01; - else - cmd[2] = 0x00; - return fts_write(cmd, ARRAY_SIZE(cmd)); -} - -static int fts_p_sensor_cmd(int on) -{ - int ret = 0; - u8 cmd_on[] = {0xa0, 0x00, 0x05}; - u8 cmd_off[] = {0xa0, 0x00, 0x01}; - u8 hover_on[] = {0xc0, 0x03, 0x01, 0x24}; - u8 hover_off[] = {0xc0, 0x03, 0x00, 0x00}; - - if (on) { - ret = fts_write_dma_safe(cmd_on, sizeof(cmd_on)); - ret = fts_write_dma_safe(hover_on, sizeof(hover_on)); - } else { - ret = fts_write_dma_safe(cmd_off, sizeof(cmd_off)); - ret = fts_write_dma_safe(hover_off, sizeof(hover_off)); - } - - if (ret < OK) { - logError(1, "%s %s: write ear det cmd on...ERROR %08X !\n", tag, - __func__, ret); - return -EINVAL; - } - logError(1, "%s %s: on:%d\n", tag, __func__, on); - if (!on) { - ret = fts_finger_report_disable(fts_info, false); - if (ret < OK) - logError(1, "%s %s: enable finger report error\n", tag, __func__); - else - logError(1, "%s %s: enable finger report\n", tag, __func__); - } - return 0; -} - -static int fts_p_sensor_write(int on) -{ - int ret = 0; - - fts_info->p_sensor_switch = on; - if (fts_info->sensor_sleep) { - fts_info->p_sensor_changed = false; - return 0; - } - ret = fts_p_sensor_cmd(on); - - if (!ret) - fts_info->p_sensor_changed = true; - return ret; -} - -static int fts_palm_sensor_cmd(int on) -{ - int ret; - u8 cmd_on[] = {0xc0, 0x07, 0x01}; - u8 cmd_off[] = {0xc0, 0x07, 0x00}; - - if (on) { - ret = fts_write(cmd_on, sizeof(cmd_on)); - } else { - ret = fts_write(cmd_off, sizeof(cmd_off)); - } - - if (ret < OK) { - logError(1, "%s %s: write anti mis-touch cmd on...ERROR %08X !\n", tag, - __func__, ret); - return -EINVAL; - } - logError(1, "%s %s %d\n", tag, __func__, on); - - return 0; -} - -static int fts_palm_sensor_write(int value) -{ - int ret = 0; - fts_info->palm_sensor_switch = value; - - if (fts_info->sensor_sleep) { - fts_info->palm_sensor_changed = false; - return 0; - } - ret = fts_palm_sensor_cmd(value); - - if (!ret) - fts_info->palm_sensor_changed = true; - - return ret; -} -#endif -#endif - -#ifdef CONFIG_SECURE_TOUCH -static void fts_secure_touch_notify (struct fts_ts_info *info) -{ - /*might sleep*/ - sysfs_notify(&info->dev->kobj, NULL, "secure_touch"); - logError(1, "%s %s SECURE_NOTIFY:notify secure_touch\n", tag, __func__); -} - -static int fts_secure_stop(struct fts_ts_info *info, bool block) -{ - struct fts_secure_info *scr_info = info->secure_info; - - logError(1, "%s %s SECURE_STOP: block = %d\n", tag, __func__, (int)block); - if (atomic_read(&scr_info->st_enabled) == 0) { - logError(1, "%s %s secure touch is already disabled\n", tag, __func__); - return OK; - } - - atomic_set(&scr_info->st_pending_irqs, -1); - fts_secure_touch_notify(info); - if (block) { - if (wait_for_completion_interruptible(&scr_info->st_powerdown) == -ERESTARTSYS) { - logError(1, "%s %s SECURE_STOP:st_powerdown be interrupted\n", - tag, __func__); - } else { - logError(1, "%s %s SECURE_STOP:st_powerdown be completed\n", tag, __func__); - } - } - return OK; -} - -static void fts_secure_work(struct fts_secure_info *scr_info) -{ - struct fts_ts_info *info = (struct fts_ts_info *)scr_info->fts_info; - - - fts_secure_touch_notify(info); - atomic_set(&scr_info->st_1st_complete, 1); - if (wait_for_completion_interruptible(&scr_info->st_irq_processed) == -ERESTARTSYS) { - logError(1, "%s %s SECURE_FILTER:st_irq_processed be interrupted\n", tag, __func__); - } else { - logError(1, "%s %s SECURE_FILTER:st_irq_processed be completed\n", tag, __func__); - } - - fts_enableInterrupt(); - logError(1, "%s %s SECURE_FILTER:enable irq\n", tag, __func__); -} - -/* -static void fts_palm_store_delay(struct fts_secure_info *scr_info) -{ - int ret; - struct fts_ts_info *info = scr_info->fts_info; - - logError(1, "%s %s IN", tag, __func__); - ret = fts_palm_sensor_cmd(scr_info->scr_delay.palm_value); - if (!ret) - info->palm_sensor_changed = true; - logError(1, "%s %s OUT", tag, __func__); -} - - -static void fts_flush_delay_task(struct fts_secure_info *scr_info) -{ - if (scr_info->scr_delay.palm_pending) { - fts_palm_store_delay(scr_info); - scr_info->scr_delay.palm_pending = false; - } -} -*/ - -static int fts_secure_filter_interrupt(struct fts_ts_info *info) -{ - struct fts_secure_info *scr_info = info->secure_info; - - /*inited and enable first*/ - if (!scr_info->secure_inited || atomic_read(&scr_info->st_enabled) == 0) { - return -EPERM; - } - - fts_disableInterruptNoSync(); - logError(1, "%s %s SECURE_FILTER:disable irq\n", tag, __func__); - /*check and change irq pending state - *change irq pending here, secure_touch_show, secure_touch_enable_store - *completion st_irq_processed at secure_touch_show, secure_touch_enable_stroe - */ - logError(1, "%s %s SECURE_FILTER:st_pending_irqs = %d\n", - tag, __func__, atomic_read(&scr_info->st_pending_irqs)); - if (atomic_cmpxchg(&scr_info->st_pending_irqs, 0, 1) == 0) { - fts_secure_work(scr_info); - logError(1, "%s %s SECURE_FILTER:secure_work return\n", tag, __func__); - } - - return 0; -} - -static ssize_t fts_secure_touch_enable_show (struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct fts_ts_info *info = dev_get_drvdata(dev); - struct fts_secure_info *scr_info = info->secure_info; - - logError(1, "%s %s SECURE_TOUCH_ENABLE[R]:st_enabled = %d\n", tag, __func__, atomic_read(&scr_info->st_enabled)); - return scnprintf(buf, PAGE_SIZE, "%d", atomic_read(&scr_info->st_enabled)); -} - -/* echo 0 > secure_touch_enable to disable secure touch - * echo 1 > secure_touch_enable to enable secure touch - */ -static ssize_t fts_secure_touch_enable_store (struct device *dev, struct device_attribute *attr, - const char *buf, size_t count) -{ - int ret; - unsigned long value; - struct fts_ts_info *info = dev_get_drvdata(dev); - struct fts_secure_info *scr_info = info->secure_info; - - atomic_set(&scr_info->st_1st_complete, 0); - logError(1, "%s %s SECURE_TOUCH_ENABLE[W]:st_1st_complete=0\n", tag, __func__); - logError(1, "%s %s SECURE_TOUCH_ENABLE[W]:parse parameter\n", tag, __func__); - /*check and get cmd*/ - if (count > 2) - return -EINVAL; - ret = kstrtoul(buf, 10, &value); - if (ret != 0) return ret; - - if (!scr_info->secure_inited) - return -EIO; - - ret = count; - - logError(1, "%s %s SECURE_TOUCH_ENABLE[W]:st_enabled = %d\n", tag, __func__, value); - switch (value) { - case 0: - if (atomic_read(&scr_info->st_enabled) == 0) { - logError(1, "%s %s secure touch is already disabled\n", - tag, __func__); - return ret; - } -// mutex_lock(&scr_info->palm_lock); - atomic_set(&scr_info->st_enabled, 0); - fts_secure_touch_notify(info); - complete(&scr_info->st_irq_processed); - fts_event_handler(info->client->irq, info); - complete(&scr_info->st_powerdown); -// fts_flush_delay_task(scr_info); -// mutex_unlock(&scr_info->palm_lock); - logError(1, "%s %s SECURE_TOUCH_ENABLE[W]:disable secure touch successful\n", - tag, __func__); - break; - case 1: - if (atomic_read(&scr_info->st_enabled) == 1) { - logError(1, "%s %s secure touch is already enabled\n", - tag, __func__); - return ret; - } -// mutex_lock(&scr_info->palm_lock); - /*wait until finish process all normal irq*/ - synchronize_irq(info->client->irq); - - /*enable secure touch*/ - reinit_completion(&scr_info->st_powerdown); - reinit_completion(&scr_info->st_irq_processed); - atomic_set(&scr_info->st_pending_irqs, 0); - atomic_set(&scr_info->st_enabled, 1); -// mutex_unlock(&scr_info->palm_lock); - logError(1, "%s %s SECURE_TOUCH_ENABLE[W]:enable secure touch successful\n", - tag, __func__); - break; - default: - logError(1, "%s %s %d in secure_touch_enable is not support\n", - tag, __func__, value); - break; } - return ret; + return count; } -static ssize_t fts_secure_touch_show (struct device *dev, struct device_attribute *attr, char *buf) +static ssize_t fts_grip_area_show(struct device *dev, + struct device_attribute *attr, char *buf) { struct fts_ts_info *info = dev_get_drvdata(dev); - struct fts_secure_info *scr_info = info->secure_info; - int value = 0; - logError(1, "%s %s SECURE_TOUCH[R]:st_1st_complete = %d\n", - tag, __func__, atomic_read(&scr_info->st_1st_complete)); - logError(1, "%s %s SECURE_TOUCH[R]:st_pending_irqs = %d\n", - tag, __func__, atomic_read(&scr_info->st_pending_irqs)); - - if (atomic_read(&scr_info->st_enabled) == 0) { - return -EBADF; - } + return snprintf(buf, TSP_BUF_SIZE, "%d\n", info->grip_pixel); +} - if (atomic_cmpxchg(&scr_info->st_pending_irqs, -1, 0) == -1) - return -EINVAL; +static ssize_t fts_grip_area_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + u8 cmd[4] = {FTS_CMD_CUSTOM, 0x01, 0x01, 0x00}; + int ret = 0; + struct fts_ts_info *info = dev_get_drvdata(dev); - if (atomic_cmpxchg(&scr_info->st_pending_irqs, 1, 0) == 1) { - value = 1; - } else if (atomic_cmpxchg(&scr_info->st_1st_complete, 1, 0) == 1) { - complete(&scr_info->st_irq_processed); - logError(1, "%s %s SECURE_TOUCH[R]:comlpetion st_irq_processed\n", tag, __func__); + pr_info("%s,buf:%s,count:%zu\n", __func__, buf, count); + sscanf(buf, "%u", &info->grip_pixel); + cmd[3] = info->grip_pixel; + ret = fts_write(cmd, ARRAY_SIZE(cmd)); + if (ret < OK) { + logError(1, "%s %s: write failed...ERROR %08X !\n", tag, + __func__, ret); + return ret; } - return scnprintf(buf, PAGE_SIZE, "%d", value); + return count; } -#endif - static DEVICE_ATTR(fts_lockdown, (S_IRUGO | S_IWUSR | S_IWGRP), fts_lockdown_show, fts_lockdown_store); @@ -3192,10 +2331,6 @@ static DEVICE_ATTR(grip_enable, (S_IRUGO | S_IWUSR | S_IWGRP), fts_grip_enable_show, fts_grip_enable_store); static DEVICE_ATTR(grip_area, (S_IRUGO | S_IWUSR | S_IWGRP), fts_grip_area_show, fts_grip_area_store); -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_GAMEMODE -static DEVICE_ATTR(touchgame, (S_IRUGO | S_IWUSR | S_IWGRP), - fts_touchgame_show, NULL); -#endif static struct attribute *fts_attr_group[] = { &dev_attr_fwupdate.attr, @@ -3240,20 +2375,10 @@ static struct attribute *fts_attr_group[] = { &dev_attr_doze_time.attr, &dev_attr_grip_enable.attr, &dev_attr_grip_area.attr, -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_GAMEMODE - &dev_attr_touchgame.attr, -#endif + NULL, }; -static DEVICE_ATTR(fod_status, (S_IRUGO | S_IWUSR | S_IWGRP), - fts_fod_status_show, fts_fod_status_store); - - -#ifdef CONFIG_SECURE_TOUCH -DEVICE_ATTR(secure_touch_enable, (S_IRUGO | S_IWUSR | S_IWGRP), fts_secure_touch_enable_show, fts_secure_touch_enable_store); -DEVICE_ATTR(secure_touch, (S_IRUGO | S_IWUSR | S_IWGRP), fts_secure_touch_show, NULL); -#endif /**@}*/ /**@}*/ @@ -3493,7 +2618,6 @@ static void fts_leave_pointer_event_handler(struct fts_ts_info *info, input_report_key(info->input_dev, BTN_TOUCH, touch_condition); if (!touch_condition) input_report_key(info->input_dev, BTN_TOOL_FINGER, 0); - lpm_disable_for_input(false); } input_report_abs(info->input_dev, ABS_MT_TRACKING_ID, -1); dev_dbg(info->dev, @@ -3747,15 +2871,6 @@ static void fts_status_event_handler(struct fts_ts_info *info, tag, __func__, event[2], event[3], event[4], event[5], event[6], event[7]); break; -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_SENSOR - case EVT_TYPE_STATUS_POCKET: - if (event[0] == 0x43 && event[2] == 0x01) { - update_palm_sensor_value(1); - } else if (event[0] == 0x43 && event[2] == 0x00) { - update_palm_sensor_value(0); - } - break; -#endif default: logError(1, @@ -3843,7 +2958,7 @@ static void fts_gesture_event_handler(struct fts_ts_info *info, if (event[0] == EVT_ID_USER_REPORT && event[1] == EVT_TYPE_USER_GESTURE) { needCoords = 1; #ifdef CONFIG_INPUT_PRESS_NDT - if (event[2] == GEST_ID_LONG_PRESS && info->fod_status) { + if (event[2] == GEST_ID_LONG_PRESS) { fts_fod_status = true; if (fts_is_in_fodarea(x, y)) { if (!finger_report_flag) { @@ -4026,20 +3141,6 @@ static void fts_user_report_event_handler(struct fts_ts_info *info, case EVT_TYPE_USER_GESTURE: fts_gesture_event_handler(info, event); break; -#endif -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_SENSOR - case EVT_TYPE_USER_EARDET: - if (event[2] == 0xAA) { - logError(1, "%s %s eardet enter\n", tag, __func__); - update_p_sensor_value(1); - } else if (event[2] == 0xBB) { - logError(1, "%s %s eardet leave\n", tag, __func__); - update_p_sensor_value(0); - } else if (event[2] == 0xCC) { - logError(1, "%s %s eardet hover enter\n", tag, __func__); - update_p_sensor_value(2); - } - break; #endif default: logError(1, @@ -4056,9 +3157,9 @@ static void fts_user_report_event_handler(struct fts_ts_info *info, * This handler is called each time there is at least one new event in the FIFO and the interrupt pin of the IC goes low. * It will read all the events from the FIFO and dispatch them to the proper event handler according the event ID */ -static irqreturn_t fts_event_handler(int irq, void *ts_info) +static void fts_event_handler(struct work_struct *work) { - struct fts_ts_info *info = ts_info; + struct fts_ts_info *info; int error = 0, count = 0; unsigned char regAdd = FIFO_CMD_READALL; unsigned char data[FIFO_EVENT_SIZE * FIFO_DEPTH] = {0}; @@ -4067,24 +3168,10 @@ static irqreturn_t fts_event_handler(int irq, void *ts_info) const unsigned char EVENTS_REMAINING_MASK = 0x1F; unsigned char events_remaining = 0; unsigned char *evt_data; - event_dispatch_handler_t event_handler; -#ifdef CONFIG_SECURE_TOUCH - if (!fts_secure_filter_interrupt(info)) { - return IRQ_HANDLED; - } -#endif + event_dispatch_handler_t event_handler; - lpm_disable_for_input(true); - if (info->dev_pm_suspend) { - error = wait_for_completion_timeout(&info->dev_pm_suspend_completion, msecs_to_jiffies(700)); - if (!error) { - logError(1, "%s system(i2c) can't finished resuming procedure, skip it", tag); - lpm_disable_for_input(false); - return IRQ_HANDLED; - } - } - info->irq_status = true; + info = container_of(work, struct fts_ts_info, work); error = fts_writeReadU8UX(regAdd, 0, 0, data, FIFO_EVENT_SIZE, DUMMY_FIFO); events_remaining = data[EVENTS_REMAINING_POS] & EVENTS_REMAINING_MASK; @@ -4116,16 +3203,7 @@ static irqreturn_t fts_event_handler(int irq, void *ts_info) } } input_sync(info->input_dev); - info->irq_status = false; - if (!info->touch_id) - lpm_disable_for_input(false); -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_GAMEMODE - if (wait_queue_complete) - wake_up(&info->wait_queue); - else - logError(1, "%s: haven't complete init wait_queue", tag); -#endif - return IRQ_HANDLED; + enable_irq(info->client->irq); } /**@}*/ @@ -4384,6 +3462,25 @@ static int fts_chip_initialization(struct fts_ts_info *info, int init_type) return ret2; } +/** + * @addtogroup isr + * @{ + */ +/** +* Top half Interrupt handler function +* Respond to the interrupt and schedule the bottom half interrupt handler in its work queue +* @see fts_event_handler() +*/ +static irqreturn_t fts_interrupt_handler(int irq, void *handle) +{ + struct fts_ts_info *info = handle; + + disable_irq_nosync(info->client->irq); + queue_work(info->event_wq, &info->work); + + return IRQ_HANDLED; +} + /** * Initialize the dispatch table with the event handlers for any possible event ID and the interrupt routine behavior (triggered when the IRQ pin is low and associating the top half interrupt handler function). * @see fts_interrupt_handler() @@ -4414,8 +3511,8 @@ static int fts_interrupt_install(struct fts_ts_info *info) /* disable interrupts in any case */ error = fts_disableInterrupt(); logError(1, "%s Interrupt Mode\n", tag); - if (request_threaded_irq(info->client->irq, NULL, fts_event_handler, info->board->irq_flags, - FTS_TS_DRV_NAME, info)) { + if (request_irq(info->client->irq, fts_interrupt_handler, info->board->irq_flags, + FTS_TS_DRV_NAME, info)) { logError(1, "%s Request irq failed\n", tag); kfree(info->event_dispatch_table); error = -EBUSY; @@ -4488,7 +3585,7 @@ int fts_chip_powercycle(struct fts_ts_info *info) logError(1, "%s %s: Power Cycle Starting... \n", tag, __func__); logError(1, "%s %s: Disabling IRQ... \n", tag, __func__); - fts_disableInterruptNoSync(); + fts_disableInterrupt(); if (info->vdd_reg) { error = regulator_disable(info->vdd_reg); @@ -4570,6 +3667,27 @@ static int fts_init_sensing(struct fts_ts_info *info) return error; } +#define MAX_REG_LEN 10 +void fts_restore_regvalues(void) +{ + char *temp_buf; + + if (fts_info == NULL) + return; + logError(1, "%s\n", tag, __func__); + if (fts_info->grip_pixel != fts_info->grip_pixel_def) { + temp_buf = (char *)kzalloc(MAX_REG_LEN, GFP_KERNEL); + if (temp_buf == NULL) { + logError(1, "%s %s alloc temp buf error\n", tag, __func__); + } else { + snprintf(temp_buf, MAX_REG_LEN, "%u", fts_info->grip_pixel); + fts_grip_area_store(fts_info->dev, NULL, temp_buf, strlen(temp_buf)); + memset(temp_buf, 0, MAX_REG_LEN); + kfree(temp_buf); + temp_buf = NULL; + } + } +} /** * @ingroup mode_section @@ -4604,26 +3722,21 @@ static int fts_mode_handler(struct fts_ts_info *info, int force) #endif #ifdef CONFIG_INPUT_PRESS_NDT logError(1, "%s %s,send long press and gesture cmd\n", tag, __func__); - res = fts_write_dma_safe(gesture_cmd, ARRAY_SIZE(gesture_cmd)); + res = fts_write(gesture_cmd, ARRAY_SIZE(gesture_cmd)); if (res < OK) logError(1, "%s %s: enter gesture and longpress failed! ERROR %08X recovery in senseOff...\n", tag, __func__, res); res = setScanMode(SCAN_MODE_LOW_POWER, 0); res |= ret; if (info->gesture_enabled == 1) { - res = fts_write_dma_safe(single_double_cmd, ARRAY_SIZE(single_double_cmd)); + res = fts_write(single_double_cmd, ARRAY_SIZE(single_double_cmd)); if (res < OK) logError(1, "%s %s: set single and double tap delay time failed! ERROR %08X\n", tag, __func__, res); } else { - res = fts_write_dma_safe(single_only_cmd, ARRAY_SIZE(single_only_cmd)); + res = fts_write(single_only_cmd, ARRAY_SIZE(single_only_cmd)); if (res < OK) logError(1, "%s %s: set single only delay time failed! ERROR %08X\n", tag, __func__, res); } - ret = fts_enableInterrupt(); - if (ret < OK) - logError(1, "%s enterGestureMode: fts_enableInterrupt ERROR %08X\n", tag, res | ERROR_ENABLE_INTER); - else - logError(1, "%s enterGestureMode: fts_enableInterrupt\n", tag); #else if (info->gesture_enabled == 1) { logError(0, "%s %s: enter in gesture mode ! \n", tag, @@ -4763,11 +3876,15 @@ static int fts_mode_handler(struct fts_ts_info *info, int force) res |= setScanMode(SCAN_MODE_ACTIVE, 0x00); logError(1, "%s %s: Sense ON without cal \n", tag, __func__); res |= setScanMode(SCAN_MODE_ACTIVE, 0x20); - } else { + } + else { logError(1, "%s %s: Sense ON\n", tag, __func__); res |= setScanMode(SCAN_MODE_ACTIVE, 0x01); } #else + if (info && isSystemResettedUp()) { + fts_restore_regvalues(); + } settings[0] = 0x01; logError(1, "%s %s: Sense ON! \n", tag, __func__); res |= setScanMode(SCAN_MODE_ACTIVE, settings[0]); @@ -4790,33 +3907,19 @@ static int fts_mode_handler(struct fts_ts_info *info, int force) } +static void fts_reg_restore_work(struct work_struct *work) +{ + fts_restore_regvalues(); +} + /** * Resume work function which perform a system reset, clean all the touches from the linux input system and prepare the ground for enabling the sensing */ static void fts_resume_work(struct work_struct *work) { struct fts_ts_info *info; -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_SENSOR - int res; -#endif - info = container_of(work, struct fts_ts_info, resume_work); - -#ifdef CONFIG_SECURE_TOUCH - fts_secure_stop(info, true); -#endif -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_SENSOR - res = fts_finger_report_disable(info, false); - if (res < OK) - logError(1, "%s %s: enable finger report error\n", tag, __func__); - else - logError(1, "%s %s: enable finger report\n", tag, __func__); - - if (!info->sensor_sleep || info->resume_bit) { - logError(1, "%s %s: skip resume\n", tag, __func__); - return; - } -#endif + info = container_of(work, struct fts_ts_info, resume_work); info->resume_bit = 1; #ifdef CONFIG_INPUT_PRESS_NDT @@ -4832,16 +3935,7 @@ static void fts_resume_work(struct work_struct *work) info->sensor_sleep = false; fts_enableInterrupt(); -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_SENSOR - if (info->palm_sensor_switch && !info->palm_sensor_changed) { - fts_palm_sensor_cmd(info->palm_sensor_switch); - info->palm_sensor_changed = true; - } - if (info->p_sensor_switch && !info->p_sensor_changed) { - fts_p_sensor_cmd(info->p_sensor_switch); - info->p_sensor_changed = true; - } -#endif + schedule_delayed_work(&info->reg_restore_work, msecs_to_jiffies(500)); } /** @@ -4850,39 +3944,17 @@ static void fts_resume_work(struct work_struct *work) static void fts_suspend_work(struct work_struct *work) { struct fts_ts_info *info; -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_SENSOR - int res; -#endif - info = container_of(work, struct fts_ts_info, suspend_work); -#ifdef CONFIG_SECURE_TOUCH - fts_secure_stop(info, true); -#endif + info = container_of(work, struct fts_ts_info, suspend_work); -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_SENSOR - if (fts_info->p_sensor_switch) { - res = fts_finger_report_disable(info, true); - if (res < OK) - logError(1, "%s %s: disable finger report error\n", tag, __func__); - else - logError(1, "%s %s: disable finger report\n", tag, __func__); - logError(0, "%s %s: eardet enabled, disable finger report and skip suspend\n", tag, __func__); - return; - } - if (info->palm_sensor_switch) { - logError(1, "%s %s: palm sensor on status, switch to off\n", tag, - __func__); - update_palm_sensor_value(0); - fts_palm_sensor_cmd(0); - info->palm_sensor_switch = false; - } -#endif info->resume_bit = 0; fts_mode_handler(info, 0); release_all_touches(info); info->sensor_sleep = true; + + fts_enableInterrupt(); } #ifdef CONFIG_DRM @@ -4908,21 +3980,21 @@ static int fts_drm_state_chg_callback(struct notifier_block *nb, logError(1, "%s %s: val:%lu,blank:%u\n", tag, __func__, val, blank); flush_workqueue(info->event_wq); + if (val == DRM_EARLY_EVENT_BLANK && blank == DRM_BLANK_POWERDOWN) { if (info->sensor_sleep) return NOTIFY_OK; - logError(1, "%s %s: FB_BLANK_POWERDOWN\n", tag, __func__); + logError(1, "%s %s: FB_BLANK_POWERDOWN\n", tag, + __func__); + queue_work(info->event_wq, &info->suspend_work); } else if (val == DRM_EVENT_BLANK && blank == DRM_BLANK_UNBLANK) { -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_SENSOR - if (!info->sensor_sleep && !info->p_sensor_switch) - return NOTIFY_OK; -#else if (!info->sensor_sleep) return NOTIFY_OK; -#endif - logError(1, "%s %s: FB_BLANK_UNBLANK\n", tag, __func__); + + logError(1, "%s %s: FB_BLANK_UNBLANK\n", tag, + __func__); queue_work(info->event_wq, &info->resume_work); } @@ -4935,52 +4007,6 @@ static struct notifier_block fts_noti_block = { }; #endif -static int fts_bl_state_chg_callback(struct notifier_block *nb, - unsigned long val, void *data) -{ - struct fts_ts_info *info = container_of(nb, struct fts_ts_info, bl_notifier); - unsigned int blank; - int ret; - - if (val != BACKLIGHT_UPDATED) - return NOTIFY_OK; - if (data && info) { - blank = *(int *)(data); - logError(1, "%s %s: val:%lu,blank:%u\n", tag, __func__, val, blank); - flush_workqueue(info->event_wq); - if (blank == BACKLIGHT_OFF) { -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_SENSOR - if (info->p_sensor_switch) { - logError(1, "%s eardet enabled, skip disableirq\n", tag, __func__); - return NOTIFY_OK; - } -#endif - if (info->sensor_sleep) - return NOTIFY_OK; - logError(1, "%s %s: BL_EVENT_BLANK\n", tag, __func__); - ret = fts_disableInterrupt(); - if (ret < OK) - logError(1, "%s fts_disableInterrupt ERROR %08X\n", tag, ret | ERROR_ENABLE_INTER); - else - logError(1, "%s fts_disableInterrupt\n", tag, ret | ERROR_ENABLE_INTER); - } else if (blank == BACKLIGHT_ON) { - logError(1, "%s %s: BL_EVENT_UNBLANK\n", tag, __func__); - if (!info->sensor_sleep) { - ret = fts_enableInterrupt(); - if (ret < OK) - logError(1, "%s fts_enableInterrupt ERROR %08X\n", tag, ret | ERROR_ENABLE_INTER); - else - logError(1, "%s fts_enableInterrupt\n", tag, ret | ERROR_ENABLE_INTER); - } - } - } - return NOTIFY_OK; -} - -static struct notifier_block fts_bl_noti_block = { - .notifier_call = fts_bl_state_chg_callback, -}; - /** * From the name of the power regulator get/put the actual regulator structs (copying their references into fts_ts_info variable) * @param info pointer to fts_ts_info which contains info about the device and its hw setup @@ -5199,73 +4225,6 @@ static int fts_pinctrl_init(struct fts_ts_info *info) return retval; } -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_GAMEMODE -static int parse_gamemode_dt(struct device *dev, struct fts_hw_platform_data *bdata) -{ - int retval; - u32 temp_val; - struct device_node *np = dev->of_node; - - retval = of_property_read_u32(np, "fts,touch-up-threshold-min", &temp_val); - if (retval < 0) - return retval; - else - bdata->touch_up_threshold_min = temp_val; - retval = of_property_read_u32(np, "fts,touch-up-threshold-max", &temp_val); - if (retval < 0) - return retval; - else - bdata->touch_up_threshold_max = temp_val; - retval = of_property_read_u32(np, "fts,touch-up-threshold-def", &temp_val); - if (retval < 0) - return retval; - else - bdata->touch_up_threshold_def = temp_val; - retval = of_property_read_u32(np, "fts,touch-tolerance-min", &temp_val); - if (retval < 0) - return retval; - else - bdata->touch_tolerance_min = temp_val; - retval = of_property_read_u32(np, "fts,touch-tolerance-max", &temp_val); - if (retval < 0) - return retval; - else - bdata->touch_tolerance_max = temp_val; - retval = of_property_read_u32(np, "fts,touch-tolerance-def", &temp_val); - if (retval < 0) - return retval; - else - bdata->touch_tolerance_def = temp_val; - retval = of_property_read_u32(np, "fts,edgefilter-leftrigt-def", &temp_val); - if (retval < 0) - return retval; - else - bdata->edgefilter_leftright_def = temp_val; - retval = of_property_read_u32(np, "fts,edgefilter-topbottom-def", &temp_val); - if (retval < 0) - return retval; - else - bdata->edgefilter_topbottom_def = temp_val; - retval = of_property_read_u32(np, "fts,edgefilter-area-step1", &temp_val); - if (retval < 0) - return retval; - else - bdata->edgefilter_area_step1 = temp_val; - retval = of_property_read_u32(np, "fts,edgefilter-area-step2", &temp_val); - if (retval < 0) - return retval; - else - bdata->edgefilter_area_step2 = temp_val; - retval = of_property_read_u32(np, "fts,edgefilter-area-step3", &temp_val); - if (retval < 0) - return retval; - else - bdata->edgefilter_area_step3 = temp_val; - return retval; - -} -#endif - /** * Retrieve and parse the hw information from the device tree node defined in the system. * the most important information to obtain are: IRQ and RESET gpio numbers, power regulator names @@ -5330,11 +4289,6 @@ static int parse_dt(struct device *dev, struct fts_hw_platform_data *bdata) bdata->y_max = temp_val; retval = of_property_read_string(np, "fts,default-fw-name", &bdata->default_fw_name); -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_GAMEMODE - retval = parse_gamemode_dt(dev, bdata); - if (retval < 0) - logError(1, "%s Unable to parse gamemode parameters\n", tag); -#endif retval = of_property_read_u32(np, "fts,config-array-size", @@ -5354,8 +4308,6 @@ static int parse_dt(struct device *dev, struct fts_hw_platform_data *bdata) return -ENOMEM; } - bdata->check_display_name = of_property_read_bool(np, "fts,check-display-name"); - config_info = bdata->config_array; for_each_child_of_node(np, temp) { retval = of_property_read_u32(temp, "fts,tp-vendor", &temp_val); @@ -5785,7 +4737,6 @@ static int fts_pm_suspend(struct device *dev) { struct fts_ts_info *info = dev_get_drvdata(dev); - info->dev_pm_suspend = true; #ifndef CONFIG_INPUT_PRESS_NDT if (device_may_wakeup(dev) && info->gesture_enabled) { logError(1, "%s enable touch irq wake\n", tag); @@ -5794,7 +4745,6 @@ static int fts_pm_suspend(struct device *dev) #else enable_irq_wake(info->client->irq); #endif - reinit_completion(&info->dev_pm_suspend_completion); return 0; @@ -5804,7 +4754,6 @@ static int fts_pm_resume(struct device *dev) { struct fts_ts_info *info = dev_get_drvdata(dev); - info->dev_pm_suspend = false; #ifndef CONFIG_INPUT_PRESS_NDT if (device_may_wakeup(dev) && info->gesture_enabled) { logError(1, "%s disable touch irq wake\n", tag); @@ -5813,7 +4762,6 @@ static int fts_pm_resume(struct device *dev) #else disable_irq_wake(info->client->irq); #endif - complete(&info->dev_pm_suspend_completion); return 0; } @@ -5932,63 +4880,6 @@ static const struct file_operations tpdbg_operations = { }; #endif -#ifdef CONFIG_SECURE_TOUCH -int fts_secure_init(struct fts_ts_info *info) -{ - int ret; - struct fts_secure_info *scr_info = kmalloc(sizeof(*scr_info), GFP_KERNEL); - if (!scr_info) { - logError(1, "%s %s alloc fts_secure_info failed\n", tag, __func__); - return -ENOMEM; - } - - logError(1, "%s fts_secure_init\n", tag); - -// mutex_init(&scr_info->palm_lock); - - init_completion(&scr_info->st_powerdown); - init_completion(&scr_info->st_irq_processed); - - atomic_set(&scr_info->st_enabled, 0); - atomic_set(&scr_info->st_pending_irqs, 0); - - info->secure_info = scr_info; - - ret = sysfs_create_file(&info->dev->kobj, &dev_attr_secure_touch_enable.attr); - if (ret < 0) { - logError(1, "%s %s create sysfs attribute secure_touch_enable failed\n", tag, __func__); - goto err; - } - - ret = sysfs_create_file(&info->dev->kobj, &dev_attr_secure_touch.attr); - if (ret < 0) { - logError(1, "%s %s create sysfs attribute secure_touch failed\n", tag, __func__); - goto err; - } - - scr_info->fts_info = info; - scr_info->secure_inited = true; - - return 0; - -err: - kfree(scr_info); - info->secure_info = NULL; - return ret; -} - -void fts_secure_remove(struct fts_ts_info *info) -{ - struct fts_secure_info *scr_info = info->secure_info; - - sysfs_remove_file(&info->dev->kobj, &dev_attr_secure_touch_enable.attr); - sysfs_remove_file(&info->dev->kobj, &dev_attr_secure_touch.attr); - kfree(scr_info); -} - -#endif - - /** * Probe function, called when the driver it is matched with a device with the same name compatible name * This function allocate, initialize and define all the most important function and flow that are used by the driver to operate with the IC. @@ -6009,7 +4900,6 @@ static int fts_probe(struct spi_device *client) int skip_5_1 = 0; u16 bus_type; u8 *tp_maker; - const char *display_name; logError(1, "%s %s: driver ver: %s\n", tag, __func__, FTS_TS_DRV_VERSION); @@ -6067,23 +4957,12 @@ static int fts_probe(struct spi_device *client) } parse_dt(&client->dev, info->board); } - if (info->board->check_display_name) { - display_name = dsi_get_display_name(); - if (display_name) { - logError(1, "%s display_name:%s\n", tag, display_name); - if (strncmp(display_name, "dsi_samsung", 11)) { - logError(1, "%s not the right display, do not need to do probe%s\n", tag); - return -EINVAL; - } - } - } logError(0, "%s SET Regulators: \n", tag); retval = fts_get_reg(info, true); if (retval < 0) { logError(1, "%s ERROR: %s: Failed to get regulators\n", tag, __func__); - error = -EINVAL; goto ProbeErrorExit_1; } @@ -6099,7 +4978,6 @@ static int fts_probe(struct spi_device *client) if (retval < 0) { logError(1, "%s %s: ERROR Failed to set up GPIO's\n", tag, __func__); - error = -EINVAL; goto ProbeErrorExit_2; } @@ -6131,9 +5009,10 @@ static int fts_probe(struct spi_device *client) error = -ENOMEM; goto ProbeErrorExit_4; } + INIT_WORK(&info->work, fts_event_handler); INIT_WORK(&info->resume_work, fts_resume_work); INIT_WORK(&info->suspend_work, fts_suspend_work); - init_completion(&info->tp_reset_completion); + logError(0, "%s SET Input Device Property: \n", tag); info->dev = &info->client->dev; info->input_dev = input_allocate_device(); @@ -6255,7 +5134,6 @@ static int fts_probe(struct spi_device *client) #ifdef CONFIG_DRM info->notifier = fts_noti_block; #endif - info->bl_notifier = fts_bl_noti_block; logError(0, "%s Init Core Lib: \n", tag); initCore(info); /* init hardware device */ @@ -6267,38 +5145,8 @@ static int fts_probe(struct spi_device *client) error = -ENODEV; goto ProbeErrorExit_6; } + /*update_hardware_info(TYPE_TOUCH, 4);*/ -#ifdef CONFIG_SECURE_TOUCH - logError(1, "%s %s create secure touch file...\n", tag, __func__); - error = fts_secure_init(info); - if (error < 0) { - logError(1, "%s %s init secure touch failed\n", tag, __func__); - goto ProbeErrorExit_7; - } - logError(1, "%s %s create secure touch file successful\n", tag, __func__); - fts_secure_stop(info, 1); -#endif - -#ifdef CONFIG_I2C_BY_DMA - /*dma buf init*/ - info->dma_buf = (struct fts_dma_buf *)kzalloc(sizeof(*info->dma_buf), GFP_KERNEL); - if (!info->dma_buf) { - logError(1, "%s %s:ERROR alloc mem failed!", tag, __func__); - goto ProbeErrorExit_7; - } - mutex_init(&info->dma_buf->dmaBufLock); - info->dma_buf->rdBuf = kzalloc(PAGE_SIZE, GFP_KERNEL); - if (!info->dma_buf->rdBuf) { - logError(1, "%s %s:ERROR alloc mem failed!", tag, __func__); - goto ProbeErrorExit_7; - } - info->dma_buf->wrBuf = kzalloc(PAGE_SIZE, GFP_KERNEL); - if (!info->dma_buf->wrBuf) { - logError(1, "%s %s:ERROR alloc mem failed!", tag, __func__); - goto ProbeErrorExit_7; - } -#endif - fts_info = info; error = fts_get_lockdown_info(info->lockdown_info, info); if (error < OK) @@ -6311,6 +5159,7 @@ static int fts_probe(struct spi_device *client) info->lockdown_info[4], info->lockdown_info[5], info->lockdown_info[6], info->lockdown_info[7]); info->lockdown_is_ok = true; + /*update_hardware_info(TYPE_TP_MAKER, info->lockdown_info[0] - 0x30); */ } #ifdef FW_UPDATE_ON_PROBE @@ -6334,6 +5183,7 @@ static int fts_probe(struct spi_device *client) } INIT_DELAYED_WORK(&info->fwu_work, fts_fw_update_auto); #endif + INIT_DELAYED_WORK(&info->reg_restore_work, fts_reg_restore_work); logError(0, "%s SET Device File Nodes: \n", tag); /* sysfs stuff */ @@ -6345,52 +5195,19 @@ static int fts_probe(struct spi_device *client) goto ProbeErrorExit_7; } - + fts_info = info; error = fts_proc_init(); if (error < OK) logError(1, "%s Error: can not create /proc file! \n", tag); - info->dbclick_count = 0; tp_maker = kzalloc(20, GFP_KERNEL); if (tp_maker == NULL) logError(1, "%s fail to alloc vendor name memory\n", tag); - - device_init_wakeup(&client->dev, 1); -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE - memset(&xiaomi_touch_interfaces, 0x00, sizeof(struct xiaomi_touch_interface)); -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_GAMEMODE - INIT_WORK(&info->cmd_update_work, fts_cmd_update_work); - mutex_init(&info->cmd_update_mutex); - xiaomi_touch_interfaces.getModeValue = fts_get_mode_value; - xiaomi_touch_interfaces.setModeValue = fts_set_cur_value; - xiaomi_touch_interfaces.resetMode = fts_reset_mode; - xiaomi_touch_interfaces.getModeAll = fts_get_mode_all; - info->touch_feature_wq = - alloc_workqueue("fts-touch-feature", - WQ_UNBOUND | WQ_HIGHPRI | WQ_CPU_INTENSIVE, 1); - if (!info->touch_feature_wq) { - logError(1, "%s Cannot create touch feature work thread\n", tag); - goto ProbeErrorExit_8; - } - init_waitqueue_head(&info->wait_queue); - wait_queue_complete = true; - - fts_read_touchmode_data(); - fts_init_touchmode_data(); -#endif -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_SENSOR - xiaomi_touch_interfaces.p_sensor_write = fts_p_sensor_write; - xiaomi_touch_interfaces.palm_sensor_write = fts_palm_sensor_write; -#endif - xiaomitouch_register_modedata(&xiaomi_touch_interfaces); -#endif - - info->dev_pm_suspend = false; - init_completion(&info->dev_pm_suspend_completion); - - if (backlight_register_notifier(&info->bl_notifier) < 0) { - logError(1, "%s ERROR: register bl_notifier failed!\n", tag); + else { + kfree(tp_maker); + tp_maker = NULL; } + device_init_wakeup(&client->dev, 1); #ifdef CONFIG_TOUCHSCREEN_ST_DEBUG_FS info->debugfs = debugfs_create_dir("tp_debug", NULL); @@ -6399,30 +5216,6 @@ static int fts_probe(struct spi_device *client) &tpdbg_operations); } #endif - if (info->fts_tp_class == NULL) -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE - info->fts_tp_class = get_xiaomi_touch_class(); -#else - info->fts_tp_class = class_create(THIS_MODULE, "touch"); -#endif - info->fts_touch_dev = - device_create(info->fts_tp_class, NULL, 0x49, info, "tp_dev"); - - if (IS_ERR(info->fts_touch_dev)) { - logError(1, - "%s ERROR: Failed to create device for the sysfs!\n", - tag); - goto ProbeErrorExit_8; - } - - dev_set_drvdata(info->fts_touch_dev, info); - - error = - sysfs_create_file(&info->fts_touch_dev->kobj, - &dev_attr_fod_status.attr); - if (error) { - logError(1, "%s ERROR: Failed to create fod_status sysfs group!\n", tag); - } info->tp_lockdown_info_proc = proc_create("tp_lockdown_info", 0, NULL, &fts_lockdown_info_ops); info->tp_selftest_proc = @@ -6439,24 +5232,7 @@ static int fts_probe(struct spi_device *client) logError(1, "%s Probe Finished! \n", tag); return OK; - -ProbeErrorExit_8: - device_destroy(info->fts_tp_class, 0x49); - class_destroy(info->fts_tp_class); - info->fts_tp_class = NULL; - ProbeErrorExit_7: -#ifdef CONFIG_SECURE_TOUCH - fts_secure_remove(info); -#endif -#ifdef CONFIG_I2C_BY_DMA - if (info->dma_buf) - kfree(info->dma_buf); - if (info->dma_buf->rdBuf) - kfree(info->dma_buf->rdBuf); - if (info->dma_buf->wrBuf) - kfree(info->dma_buf->wrBuf); -#endif #ifdef CONFIG_DRM drm_unregister_client(&info->notifier); #endif @@ -6503,9 +5279,10 @@ static int fts_remove(struct spi_device *client) fts_proc_remove(); /* sysfs stuff */ sysfs_remove_group(&client->dev.kobj, &info->attrs); + /* remove interrupt and event handlers */ fts_interrupt_uninstall(info); - backlight_unregister_notifier(&info->bl_notifier); + #ifdef CONFIG_DRM drm_unregister_client(&info->notifier); #endif @@ -6518,16 +5295,11 @@ static int fts_remove(struct spi_device *client) #ifndef FW_UPDATE_ON_PROBE destroy_workqueue(info->fwu_workqueue); #endif -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_GAMEMODE - destroy_workqueue(info->touch_feature_wq); -#endif fts_enable_reg(info, false); fts_get_reg(info, false); fts_info = NULL; -#ifdef CONFIG_SECURE_TOUCH - fts_secure_remove(info); -#endif + /* free all */ kfree(info); diff --git a/drivers/input/touchscreen/fts_521/fts.h b/drivers/input/touchscreen/fts_521/fts.h index b06d33217a0b..cfeab468e069 100644 --- a/drivers/input/touchscreen/fts_521/fts.h +++ b/drivers/input/touchscreen/fts_521/fts.h @@ -38,7 +38,6 @@ #include #include "fts_lib/ftsSoftware.h" #include "fts_lib/ftsHardware.h" -#include /****************** CONFIGURATION SECTION ******************/ /** @defgroup conf_section Driver Configuration Section * Settings of the driver code in order to suit the HW set up and the application behavior @@ -149,12 +148,6 @@ do {\ #define TSP_BUF_SIZE PAGE_SIZE -#define CONFIG_FTS_TOUCH_COUNT_DUMP - -#ifdef CONFIG_FTS_TOUCH_COUNT_DUMP -#define TOUCH_COUNT_FILE_MAXSIZE 50 -#endif - /** * Struct which contains information about the HW platform and set up */ @@ -169,9 +162,6 @@ struct fts_config_info { u8 tp_hw_version; const char *fts_cfg_name; const char *fts_limit_name; -#ifdef CONFIG_FTS_TOUCH_COUNT_DUMP - const char *clicknum_file_name; -#endif }; struct fts_hw_platform_data { @@ -190,25 +180,8 @@ struct fts_hw_platform_data { #ifdef PHONE_KEY size_t nbuttons; int *key_code; -#endif -#ifdef CONFIG_FTS_TOUCH_COUNT_DUMP - bool dump_click_count; #endif unsigned long keystates; - bool check_display_name; -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_GAMEMODE - u32 touch_up_threshold_min; - u32 touch_up_threshold_max; - u32 touch_up_threshold_def; - u32 touch_tolerance_min; - u32 touch_tolerance_max; - u32 touch_tolerance_def; - u32 edgefilter_leftright_def; - u32 edgefilter_topbottom_def; - u32 edgefilter_area_step1; - u32 edgefilter_area_step2; - u32 edgefilter_area_step3; -#endif }; /* @@ -223,35 +196,6 @@ extern char tag[8]; typedef void (*event_dispatch_handler_t) (struct fts_ts_info *info, unsigned char *data); -#ifdef CONFIG_SECURE_TOUCH -/* -struct fts_secure_delay { - bool palm_pending; - int palm_value; -}; -*/ - -struct fts_secure_info { - bool secure_inited; - atomic_t st_1st_complete; - atomic_t st_enabled; - atomic_t st_pending_irqs; - struct completion st_irq_processed; - struct completion st_powerdown; -// struct fts_secure_delay scr_delay; -// struct mutex palm_lock; - void *fts_info; -}; -#endif - -#ifdef CONFIG_I2C_BY_DMA -struct fts_dma_buf { - struct mutex dmaBufLock; - u8 *rdBuf; - u8 *wrBuf; -}; -#endif - /** * FTS capacitive touch screen device information * - dev Pointer to the structure device \n @@ -289,14 +233,13 @@ struct fts_ts_info { struct work_struct work; struct work_struct suspend_work; struct work_struct resume_work; - struct work_struct cmd_update_work; struct workqueue_struct *event_wq; - struct workqueue_struct *touch_feature_wq; #ifndef FW_UPDATE_ON_PROBE struct delayed_work fwu_work; struct workqueue_struct *fwu_workqueue; #endif + struct delayed_work reg_restore_work; event_dispatch_handler_t *event_dispatch_table; struct attribute_group attrs; @@ -314,7 +257,6 @@ struct fts_ts_info { int fwupdate_stat; struct notifier_block notifier; - struct notifier_block bl_notifier; bool sensor_sleep; struct pinctrl *ts_pinctrl; struct pinctrl_state *pinctrl_state_active; @@ -328,7 +270,6 @@ struct fts_ts_info { /* input lock */ struct mutex input_report_mutex; - struct mutex cmd_update_mutex; int gesture_enabled; int glove_enabled; int charger_enabled; @@ -341,38 +282,8 @@ struct fts_ts_info { unsigned int doze_time_def; #ifdef CONFIG_TOUCHSCREEN_ST_DEBUG_FS struct dentry *debugfs; -#endif - int dbclick_count; -#ifdef CONFIG_FTS_TOUCH_COUNT_DUMP - struct class *fts_tp_class; - struct device *fts_touch_dev; - char *current_clicknum_file; -#endif -#ifdef CONFIG_SECURE_TOUCH - struct fts_secure_info *secure_info; -#endif -#ifdef CONFIG_I2C_BY_DMA - struct fts_dma_buf *dma_buf; #endif bool lockdown_is_ok; - struct completion tp_reset_completion; - atomic_t system_is_resetting; - unsigned int fod_status; - bool irq_status; -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_SENSOR - bool p_sensor_switch; - bool p_sensor_changed; - - int palm_sensor_switch; - bool palm_sensor_changed; -#endif -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_GAMEMODE - wait_queue_head_t wait_queue; -#endif -#endif - bool dev_pm_suspend; - struct completion dev_pm_suspend_completion; }; struct fts_mode_switch { diff --git a/drivers/input/touchscreen/fts_521/fts_lib/ftsCore.c b/drivers/input/touchscreen/fts_521/fts_lib/ftsCore.c index 0163b2c35005..15cff0d8b91c 100644 --- a/drivers/input/touchscreen/fts_521/fts_lib/ftsCore.c +++ b/drivers/input/touchscreen/fts_521/fts_lib/ftsCore.c @@ -31,7 +31,6 @@ #include "ftsTime.h" #include "ftsTool.h" -extern struct fts_ts_info *fts_info; /** @addtogroup system_info * @{ */ @@ -90,14 +89,10 @@ int fts_system_reset(void) u8 data[1] = { SYSTEM_RESET_VALUE }; event_to_search = (int)EVT_ID_CONTROLLER_READY; - logError(1, "%s System resetting...\n", tag); - if (fts_info) { - reinit_completion(&fts_info->tp_reset_completion); - atomic_set(&fts_info->system_is_resetting, 1); - } + logError(0, "%s System resetting...\n", tag); for (i = 0; i < RETRY_SYSTEM_RESET && res < 0; i++) { resetErrorList(); - fts_disableInterruptNoSync(); + fts_disableInterrupt(); if (reset_gpio == GPIO_NOT_DEFINED) { res = @@ -114,6 +109,7 @@ int fts_system_reset(void) logError(1, "%s fts_system_reset: ERROR %08X\n", tag, ERROR_BUS_W); } else { + fts_restore_regvalues(); res = pollForEvent(&event_to_search, 1, readData, GENERAL_TIMEOUT); @@ -123,17 +119,13 @@ int fts_system_reset(void) } } } - if (fts_info) { - complete(&fts_info->tp_reset_completion); - atomic_set(&fts_info->system_is_resetting, 0); - } if (res < OK) { logError(1, "%s fts_system_reset...failed after 3 attempts: ERROR %08X\n", tag, (res | ERROR_SYSTEM_RESET_FAIL)); return (res | ERROR_SYSTEM_RESET_FAIL); } else { - logError(1, "%s System reset DONE!\n", tag); + logError(0, "%s System reset DONE!\n", tag); system_reseted_down = 1; system_reseted_up = 1; return OK; @@ -343,7 +335,7 @@ int setScanMode(u8 mode, u8 settings) tag, __func__, mode, settings); if (mode == SCAN_MODE_LOW_POWER) size = 2; - ret = fts_write_dma_safe(cmd, size); + ret = fts_write(cmd, size); if (ret < OK) { logError(1, "%s %s: write failed...ERROR %08X !\n", tag, __func__, ret); @@ -380,7 +372,7 @@ int setFeatures(u8 feat, u8 *settings, int size) logError(0, "%02X ", settings[i]); } logError(0, "\n"); - ret = fts_write_dma_safe(cmd, 2 + size); + ret = fts_write(cmd, 2 + size); if (ret < OK) { logError(1, "%s %s: write failed...ERROR %08X !\n", tag, __func__, ret); @@ -792,7 +784,7 @@ int fts_disableInterruptNoSync(void) disable_irq_count++; } - spin_unlock_irq(&fts_int); + spin_unlock(&fts_int); logError(0, "%s Interrupt No Sync Disabled!\n", tag); return OK; } else { @@ -948,7 +940,7 @@ int requestSyncFrame(u8 type) logError(0, "%s %s: Requesting frame %02X attempt = %d \n", tag, __func__, type, retry2 + 1); - ret = fts_write_dma_safe(request, ARRAY_SIZE(request)); + ret = fts_write(request, ARRAY_SIZE(request)); if (ret >= OK) { logError(0, "%s %s: Polling for new count... \n", tag, @@ -1121,7 +1113,7 @@ int writeLockDownInfo(u8 *data, int size, u8 lock_id) continue; } mdelay(10); - ret = fts_write_dma_safe(lockdown_save, 3); + ret = fts_write(lockdown_save, 3); mdelay(5); ret = checkEcho(lockdown_save, 3); if (ret < OK) { @@ -1193,7 +1185,7 @@ int readLockDownInfo(u8 *lockData, u8 lock_id, int size) } loaded_cnt = (int)((temp[3] & 0xFF) << 8) + (temp[2] & 0xFF); cmd_lockdown[2] = lock_id; - fts_write_dma_safe(cmd_lockdown, 3); + fts_write(cmd_lockdown, 3); mdelay(10); ret = checkEcho(cmd_lockdown, 3); if (ret < OK) { @@ -1296,7 +1288,7 @@ int fts_get_lockdown_info(u8 *lockData, struct fts_ts_info *info) } loaded_cnt = (int)((temp[3] & 0xFF) << 8) + (temp[2] & 0xFF); cmd_lockdown[2] = lock_id; - fts_write_dma_safe(cmd_lockdown, 3); + fts_write(cmd_lockdown, 3); mdelay(10); ret = checkEcho(cmd_lockdown, 3); if (ret < OK) { diff --git a/drivers/input/touchscreen/fts_521/fts_lib/ftsFlash.c b/drivers/input/touchscreen/fts_521/fts_lib/ftsFlash.c index 2d025684ea72..70331c639cb3 100644 --- a/drivers/input/touchscreen/fts_521/fts_lib/ftsFlash.c +++ b/drivers/input/touchscreen/fts_521/fts_lib/ftsFlash.c @@ -252,7 +252,7 @@ int wait_for_flash_ready(u8 type) logError(0, "%s Waiting for flash ready ... \n", tag); for (i = 0; i < FLASH_RETRY_COUNT && res != 0; i++) { - res = fts_writeRead_dma_safe(cmd, ARRAY_SIZE(cmd), readData, 2); + res = fts_writeRead(cmd, ARRAY_SIZE(cmd), readData, 2); if (res < OK) { logError(1, "%s wait_for_flash_ready: ERROR % 08X\n", tag, ERROR_BUS_W); @@ -529,7 +529,7 @@ int flash_unlock(void) }; logError(0, "%s Command unlock ... \n", tag); - if (fts_write_dma_safe(cmd, ARRAY_SIZE(cmd)) < OK) { + if (fts_write(cmd, ARRAY_SIZE(cmd)) < OK) { logError(1, "%s flash_unlock: ERROR %08X\n", tag, ERROR_BUS_W); return ERROR_BUS_W; } @@ -554,7 +554,7 @@ int flash_erase_unlock(void) logError(0, "%s Try to erase unlock flash... \n", tag); logError(0, "%s Command erase unlock ... \n", tag); - if (fts_write_dma_safe(cmd, ARRAY_SIZE(cmd)) < 0) { + if (fts_write(cmd, ARRAY_SIZE(cmd)) < 0) { logError(1, "%s flash_erase_unlock: ERROR %08X\n", tag, ERROR_BUS_W); return ERROR_BUS_W; @@ -579,14 +579,14 @@ int flash_full_erase(void) FLASH_ERASE_CODE1 }; - if (fts_write_dma_safe(cmd1, ARRAY_SIZE(cmd1)) < OK) { + if (fts_write(cmd1, ARRAY_SIZE(cmd1)) < OK) { logError(1, "%s flash_erase_page_by_page: ERROR %08X\n", tag, ERROR_BUS_W); return ERROR_BUS_W; } logError(0, "%s Command full erase sent ... \n", tag); - if (fts_write_dma_safe(cmd, ARRAY_SIZE(cmd)) < OK) { + if (fts_write(cmd, ARRAY_SIZE(cmd)) < OK) { logError(1, "%s flash_full_erase: ERROR %08X\n", tag, ERROR_BUS_W); return ERROR_BUS_W; @@ -639,14 +639,14 @@ int flash_erase_page_by_page(ErasePage keep_cx) } logError(0, "\n%s Writing page mask... \n", tag); - if (fts_write_dma_safe(cmd2, ARRAY_SIZE(cmd2)) < OK) { + if (fts_write(cmd2, ARRAY_SIZE(cmd2)) < OK) { logError(1, "%s flash_erase_page_by_page: Page mask ERROR %08X\n", tag, ERROR_BUS_W); return ERROR_BUS_W; } - if (fts_write_dma_safe(cmd1, ARRAY_SIZE(cmd1)) < OK) { + if (fts_write(cmd1, ARRAY_SIZE(cmd1)) < OK) { logError(1, "%s flash_erase_page_by_page: Disable info ERROR %08X\n", tag, ERROR_BUS_W); @@ -654,7 +654,7 @@ int flash_erase_page_by_page(ErasePage keep_cx) } logError(0, "%s Command erase pages sent ... \n", tag); - if (fts_write_dma_safe(cmd, ARRAY_SIZE(cmd)) < OK) { + if (fts_write(cmd, ARRAY_SIZE(cmd)) < OK) { logError(1, "%s flash_erase_page_by_page: Erase ERROR %08X\n", tag, ERROR_BUS_W); return ERROR_BUS_W; @@ -685,7 +685,7 @@ int start_flash_dma(void) u8 cmd[6] = { FLASH_CMD_WRITE_REGISTER, 0x20, 0x00, 0x00, FLASH_DMA_CODE0, FLASH_DMA_CODE1 }; logError(0, "%s Command flash DMA ... \n", tag); - if (fts_write_dma_safe(cmd, ARRAY_SIZE(cmd)) < OK) { + if (fts_write(cmd, ARRAY_SIZE(cmd)) < OK) { logError(1, "%s start_flash_dma: ERROR %08X\n", tag, ERROR_BUS_W); return ERROR_BUS_W; @@ -768,7 +768,7 @@ int fillFlash(u32 address, u8 *data, int size) buff[index++] = (u8) (addr & 0x000000FF); memcpy(&buff[index], data, toWrite); - if (fts_write_dma_safe(buff, index + toWrite) < OK) { + if (fts_write(buff, index + toWrite) < OK) { logError(1, "%s fillFlash: ERROR %08X\n", tag, ERROR_BUS_W); kfree(buff); @@ -801,7 +801,7 @@ int fillFlash(u32 address, u8 *data, int size) tag, buff2[0], buff2[8], buff2[7], buff2[10], buff2[9]); - if (fts_write_dma_safe(buff2, index) < OK) { + if (fts_write(buff2, index) < OK) { logError(1, "%s Error during filling Flash! ERROR %08X \n", tag, ERROR_BUS_W); diff --git a/drivers/input/touchscreen/fts_521/fts_lib/ftsGesture.c b/drivers/input/touchscreen/fts_521/fts_lib/ftsGesture.c index 3a4e2a66bf9e..3567c0eb95c4 100644 --- a/drivers/input/touchscreen/fts_521/fts_lib/ftsGesture.c +++ b/drivers/input/touchscreen/fts_521/fts_lib/ftsGesture.c @@ -206,7 +206,7 @@ int enterGestureMode(int reload) { int res, ret; - res = fts_disableInterruptNoSync(); + res = fts_disableInterrupt(); if (res < OK) { logError(1, "%s enterGestureMode: ERROR %08X \n", tag, res | ERROR_DISABLE_INTER); diff --git a/drivers/input/touchscreen/fts_521/fts_lib/ftsIO.c b/drivers/input/touchscreen/fts_521/fts_lib/ftsIO.c index 6c1ededa020e..687e4967cf5c 100644 --- a/drivers/input/touchscreen/fts_521/fts_lib/ftsIO.c +++ b/drivers/input/touchscreen/fts_521/fts_lib/ftsIO.c @@ -44,8 +44,6 @@ static void *client; #include "ftsHardware.h" #include "ftsIO.h" -extern struct fts_ts_info *fts_info; - /** * Initialize the static client variable of the fts_lib library in order to allow any i2c/spi transaction in the driver. (Must be called in the probe) * @param clt pointer to i2c_client or spi_device struct which identify the bus slave device @@ -294,160 +292,6 @@ int fts_write(u8 *cmd, int cmdLength) return OK; } -#ifdef CONFIG_I2C_BY_DMA -/** - * same as above but can be used when enable DMA. - */ -int fts_read_dma_safe(u8 *outBuf, int byteToRead) -{ - - int ret; - struct fts_dma_buf *dma = fts_info->dma_buf; - u8 *malcBuf = dma->rdBuf; - u8 *tmpBuf = NULL; - u8 *finalBuf; - - mutex_lock(&dma->dmaBufLock); - /*use malloc buf*/ - if (byteToRead > 1) { - /*extend malloc buf*/ - if (unlikely(byteToRead > PAGE_SIZE)) { - tmpBuf = kzalloc(byteToRead, GFP_KERNEL); - if (!tmpBuf) { - logError(1, "%s %s:ERROR alloc mem failed!", tag, __func__); - mutex_unlock(&dma->dmaBufLock); - return ERROR_ALLOC; - } - finalBuf = tmpBuf; - } else { - finalBuf = malcBuf; - } - } else { - finalBuf = outBuf; - } - - ret = fts_read(finalBuf, byteToRead); - if ((ret == OK) && (byteToRead > 1)) { - memcpy(outBuf, finalBuf, byteToRead); - } - if (unlikely(tmpBuf)) - kfree(tmpBuf); - mutex_unlock(&dma->dmaBufLock); - - return ret; -} - -int fts_writeRead_dma_safe(u8 *cmd, int cmdLength, u8 *outBuf, int byteToRead) -{ - int ret; - struct fts_dma_buf *dma = fts_info->dma_buf; - u8 *malcRdBuf = dma->rdBuf; - u8 *malcWrBuf = dma->wrBuf; - u8 *rdBuf, *tmpRdBuf = NULL; - u8 *wrBuf, *tmpWrBuf = NULL; - - mutex_lock(&dma->dmaBufLock); - if (cmdLength > 1) { - if (unlikely(cmdLength > PAGE_SIZE)) { - tmpWrBuf = kzalloc(cmdLength, GFP_KERNEL); - if (!tmpWrBuf) { - logError(1, "%s %s:ERROR alloc mem failed!", tag, __func__); - mutex_unlock(&dma->dmaBufLock); - return ERROR_ALLOC; - } - wrBuf = tmpWrBuf; - } else { - wrBuf = malcWrBuf; - } - memcpy(wrBuf, cmd, cmdLength); - } else { - wrBuf = cmd; - } - - if (byteToRead > 1) { - if (unlikely(byteToRead > PAGE_SIZE)) { - tmpRdBuf = kzalloc(byteToRead, GFP_KERNEL); - if (!tmpRdBuf) { - logError(1, "%s %s:ERROR alloc mem failed!", tag, __func__); - if (tmpWrBuf) - kfree(tmpWrBuf); - mutex_unlock(&dma->dmaBufLock); - return ERROR_ALLOC; - } - rdBuf = tmpRdBuf; - } else { - rdBuf = malcRdBuf; - } - } else { - rdBuf = outBuf; - } - - ret = fts_writeRead(wrBuf, cmdLength, rdBuf, byteToRead); - if ((ret == OK) && (byteToRead > 1)) - memcpy(outBuf, rdBuf, byteToRead); - - if (unlikely(tmpRdBuf)) - kfree(tmpRdBuf); - if (unlikely(tmpWrBuf)) - kfree(tmpWrBuf); - mutex_unlock(&dma->dmaBufLock); - - return ret; -} - -int fts_write_dma_safe(u8 *cmd, int cmdLength) -{ - int ret; - struct fts_dma_buf *dma = fts_info->dma_buf; - u8 *malcBuf = dma->wrBuf; - u8 *tmpBuf = NULL; - u8 *finalBuf; - - mutex_lock(&dma->dmaBufLock); - /*use malloc buf*/ - if (cmdLength > 1) { - /*extend malloc buf*/ - if (unlikely(cmdLength > PAGE_SIZE)) { - tmpBuf = kzalloc(cmdLength, GFP_KERNEL); - if (!tmpBuf) { - logError(1, "%s %s:ERROR alloc mem failed!", tag, __func__); - mutex_unlock(&dma->dmaBufLock); - return ERROR_ALLOC; - } - finalBuf = tmpBuf; - } else { - finalBuf = malcBuf; - } - memcpy(finalBuf, cmd, cmdLength); - } else { - finalBuf = cmd; - } - - ret = fts_write(finalBuf, cmdLength); - - if (unlikely(tmpBuf)) - kfree(tmpBuf); - mutex_unlock(&dma->dmaBufLock); - - - return ret; -} -#else -int fts_read_dma_safe(u8 *outBuf, int byteToRead) -{ - return fts_read(outBuf, byteToRead); -} -int fts_writeRead_dma_safe(u8 *cmd, int cmdLength, u8 *outBuf, int byteToRead) -{ - return fts_writeRead(cmd, cmdLength, outBuf, byteToRead); -} -int fts_write_dma_safe(u8 *cmd, int cmdLength) -{ - return fts_write(cmd, cmdLength); -} -#endif - - /** * Write a FW command to the IC and check automatically the echo event * @param cmd byte array containing the command to send diff --git a/drivers/input/touchscreen/fts_521/fts_lib/ftsIO.h b/drivers/input/touchscreen/fts_521/fts_lib/ftsIO.h index 954c2f5148de..f5ef57c3d0ea 100644 --- a/drivers/input/touchscreen/fts_521/fts_lib/ftsIO.h +++ b/drivers/input/touchscreen/fts_521/fts_lib/ftsIO.h @@ -46,9 +46,6 @@ int changeSAD(u8 sad); int fts_read(u8 *outBuf, int byteToRead); int fts_writeRead(u8 *cmd, int cmdLength, u8 *outBuf, int byteToRead); int fts_write(u8 *cmd, int cmdLength); -int fts_read_dma_safe(u8 *outBuf, int byteToRead); -int fts_writeRead_dma_safe(u8 *cmd, int cmdLength, u8 *outBuf, int byteToRead); -int fts_write_dma_safe(u8 *cmd, int cmdLength); int fts_writeFwCmd(u8 *cmd, int cmdLenght); int fts_writeThenWriteRead(u8 *writeCmd1, int writeCmdLength, u8 *readCmd1, int readCmdLength, u8 *outBuf, int byteToRead); diff --git a/drivers/input/touchscreen/fts_521/fts_lib/ftsSoftware.h b/drivers/input/touchscreen/fts_521/fts_lib/ftsSoftware.h index 26bf07efcec5..9e85f654fa75 100644 --- a/drivers/input/touchscreen/fts_521/fts_lib/ftsSoftware.h +++ b/drivers/input/touchscreen/fts_521/fts_lib/ftsSoftware.h @@ -290,7 +290,6 @@ typedef enum { #define EVT_TYPE_STATUS_FORCE_CAL 0x05 /*Force Calibration has triggered*/ #define EVT_TYPE_STATUS_WATER 0x06 /*Water Mode*/ #define EVT_TYPE_STATUS_SS_RAW_SAT 0x07 /*Self Sense data saturated*/ -#define EVT_TYPE_STATUS_POCKET 0x09 /** @} */ /** @defgroup user_type User Event Types @@ -301,8 +300,6 @@ typedef enum { #define EVT_TYPE_USER_KEY 0x00 /*Keys pressed/relesed event report*/ #define EVT_TYPE_USER_PROXIMITY 0x01 /*Proximity detection event report*/ #define EVT_TYPE_USER_GESTURE 0x02 /*Gesture detection event report*/ -#define EVT_TYPE_USER_EARDET 0x03 /*ear detection event report*/ - /** @}*/ /** @defgroup error_type Error Event Types diff --git a/drivers/input/touchscreen/fts_521/fts_proc.c b/drivers/input/touchscreen/fts_521/fts_proc.c index 34057fa5e748..f5bcb95e8b9e 100644 --- a/drivers/input/touchscreen/fts_521/fts_proc.c +++ b/drivers/input/touchscreen/fts_521/fts_proc.c @@ -593,7 +593,7 @@ static ssize_t fts_driver_test_write(struct file *file, const char __user *buf, (u8 *) kmalloc((byteToRead + mess.dummy) * sizeof(u8), GFP_KERNEL); res = - fts_writeRead_dma_safe(&cmd[1], temp, readData, + fts_writeRead(&cmd[1], temp, readData, byteToRead + mess.dummy); size += (byteToRead * sizeof(u8)); @@ -608,7 +608,7 @@ static ssize_t fts_driver_test_write(struct file *file, const char __user *buf, case CMD_WRITE_BYTE: if (numberParam >= 2) { temp = numberParam - 1; - res = fts_write_dma_safe(&cmd[1], temp); + res = fts_write(&cmd[1], temp); } else { logError(1, "%s Wrong number of parameters! \n", diff --git a/drivers/input/touchscreen/goodix.c b/drivers/input/touchscreen/goodix.c index c599b5a2373b..6a02e7301297 100644 --- a/drivers/input/touchscreen/goodix.c +++ b/drivers/input/touchscreen/goodix.c @@ -89,6 +89,15 @@ static const unsigned long goodix_irq_flags[] = { */ static const struct dmi_system_id rotated_screen[] = { #if defined(CONFIG_DMI) && defined(CONFIG_X86) + { + .ident = "Teclast X89", + .matches = { + /* tPAD is too generic, also match on bios date */ + DMI_MATCH(DMI_BOARD_VENDOR, "TECLAST"), + DMI_MATCH(DMI_BOARD_NAME, "tPAD"), + DMI_MATCH(DMI_BIOS_DATE, "12/19/2014"), + }, + }, { .ident = "WinBook TW100", .matches = { diff --git a/drivers/input/touchscreen/nt36xxx/Kconfig b/drivers/input/touchscreen/nt36xxx/Kconfig index 89afbf41e2ee..029ad065cbd3 100644 --- a/drivers/input/touchscreen/nt36xxx/Kconfig +++ b/drivers/input/touchscreen/nt36xxx/Kconfig @@ -3,9 +3,21 @@ # config TOUCHSCREEN_NT36XXX bool "Novatek NT36XXX" + depends on I2C default y help Say Y here if you have a Novatek NT36xxx touchscreen connected to your system. If unsure, say N. + +config TOUCHSCREEN_NT36XXX_MPCTRL + bool "Novatek NT36xxx MPCTRL" + depends on TOUCHSCREEN_NT36XXX + default n + help + Say Y here to enable NT36xxx MPCTRL, this option intended for + Manufacturer Testing and grabbing RawTouch and checking the + calibration CSV in Pre-Production devices. + + If unsure, say N. \ No newline at end of file diff --git a/drivers/input/touchscreen/nt36xxx/Makefile b/drivers/input/touchscreen/nt36xxx/Makefile index 477de656e425..0fadb58f4059 100644 --- a/drivers/input/touchscreen/nt36xxx/Makefile +++ b/drivers/input/touchscreen/nt36xxx/Makefile @@ -4,4 +4,5 @@ # Each configuration option enables a list of files. -obj-$(CONFIG_TOUCHSCREEN_NT36XXX) += nt36xxx.o nt36xxx_fw_update.o nt36xxx_ext_proc.o nt36xxx_mp_ctrlram.o +obj-$(CONFIG_TOUCHSCREEN_NT36XXX) += nt36xxx.o nt36xxx_fw_update.o nt36xxx_ext_proc.o +obj-$(CONFIG_TOUCHSCREEN_NT36XXX_MPCTRL) += nt36xxx_mp_ctrlram.o \ No newline at end of file diff --git a/drivers/input/touchscreen/nt36xxx/nt36xxx.c b/drivers/input/touchscreen/nt36xxx/nt36xxx.c index 9e97a1a09fff..038816a676a8 100644 --- a/drivers/input/touchscreen/nt36xxx/nt36xxx.c +++ b/drivers/input/touchscreen/nt36xxx/nt36xxx.c @@ -39,18 +39,7 @@ #include #include "nt36xxx.h" -#if NVT_TOUCH_ESD_PROTECT -#include -#endif /* #if NVT_TOUCH_ESD_PROTECT */ - -#if NVT_TOUCH_ESD_PROTECT -static struct delayed_work nvt_esd_check_work; -static struct workqueue_struct *nvt_esd_check_wq; -static unsigned long irq_timer; -uint8_t esd_check; -uint8_t esd_retry; -uint8_t esd_retry_max = 5; -#endif /* #if NVT_TOUCH_ESD_PROTECT */ + #if NVT_TOUCH_EXT_PROC extern int32_t nvt_extra_proc_init(void); @@ -72,9 +61,6 @@ static void nvt_resume_work(struct work_struct *work); #if defined(CONFIG_DRM) static int drm_notifier_callback(struct notifier_block *self, unsigned long event, void *data); -#elif defined(CONFIG_HAS_EARLYSUSPEND) -static void nvt_ts_early_suspend(struct early_suspend *h); -static void nvt_ts_late_resume(struct early_suspend *h); #endif #define INPUT_EVENT_START 0 @@ -94,6 +80,8 @@ static void nvt_ts_late_resume(struct early_suspend *h); #define INPUT_EVENT_PALM_ON 13 #define INPUT_EVENT_END 13 +#define PROC_SYMLINK_PATH "touchpanel" + #if TOUCH_KEY_NUM > 0 const uint16_t touch_key_array[TOUCH_KEY_NUM] = { KEY_BACK, @@ -135,6 +123,8 @@ int32_t CTP_I2C_READ(struct i2c_client *client, uint16_t address, uint8_t *buf, int32_t ret = -1; int32_t retries = 0; + mutex_lock(&ts->xbuf_lock); + msgs[0].flags = !I2C_M_RD; msgs[0].addr = address; msgs[0].len = 1; @@ -143,11 +133,12 @@ int32_t CTP_I2C_READ(struct i2c_client *client, uint16_t address, uint8_t *buf, msgs[1].flags = I2C_M_RD; msgs[1].addr = address; msgs[1].len = len - 1; - msgs[1].buf = &buf[1]; + msgs[1].buf = ts->xbuf; while (retries < 5) { ret = i2c_transfer(client->adapter, msgs, 2); - if (ret == 2) break; + if (ret == 2) + break; retries++; msleep(20); NVT_ERR("error, retry=%d\n", retries); @@ -157,6 +148,9 @@ int32_t CTP_I2C_READ(struct i2c_client *client, uint16_t address, uint8_t *buf, NVT_ERR("error, ret=%d\n", ret); ret = -EIO; } + memcpy(buf + 1, ts->xbuf, len - 1); + + mutex_unlock(&ts->xbuf_lock); return ret; } @@ -173,15 +167,17 @@ int32_t CTP_I2C_WRITE(struct i2c_client *client, uint16_t address, uint8_t *buf, struct i2c_msg msg; int32_t ret = -1; int32_t retries = 0; + mutex_lock(&ts->xbuf_lock); msg.flags = !I2C_M_RD; msg.addr = address; msg.len = len; - msg.buf = buf; - + memcpy(ts->xbuf, buf, len); + msg.buf = ts->xbuf; while (retries < 5) { ret = i2c_transfer(client->adapter, &msg, 1); - if (ret == 1) break; + if (ret == 1) + break; retries++; msleep(20); NVT_ERR("error, retry=%d\n", retries); @@ -192,6 +188,8 @@ int32_t CTP_I2C_WRITE(struct i2c_client *client, uint16_t address, uint8_t *buf, ret = -EIO; } + mutex_unlock(&ts->xbuf_lock); + return ret; } @@ -206,11 +204,11 @@ int32_t CTP_I2C_WRITE(struct i2c_client *client, uint16_t address, uint8_t *buf, *******************************************************/ void nvt_sw_reset_idle(void) { - uint8_t buf[4]={0}; + uint8_t buf[4] = {0}; /*---write i2c cmds to reset idle---*/ - buf[0]=0x00; - buf[1]=0xA5; + buf[0] = 0x00; + buf[1] = 0xA5; CTP_I2C_WRITE(ts->client, I2C_HW_Address, buf, 2); msleep(15); @@ -316,7 +314,7 @@ int32_t nvt_check_fw_status(void) if (i >= retry) { NVT_ERR("failed, i=%d, buf[1]=0x%02X\n", i, buf[1]); - return -EPERM; + return -1; } else { return 0; } @@ -484,11 +482,6 @@ static ssize_t nvt_flash_read(struct file *file, char __user *buff, size_t count return -EFAULT; } -#if NVT_TOUCH_ESD_PROTECT - cancel_delayed_work_sync(&nvt_esd_check_work); - nvt_esd_check_enable(false); -#endif /* #if NVT_TOUCH_ESD_PROTECT */ - i2c_wr = str[0] >> 7; if (i2c_wr == 0) { /*I2C write*/ @@ -593,7 +586,7 @@ static const struct file_operations nvt_flash_fops = { *******************************************************/ static int32_t nvt_flash_proc_init(void) { - NVT_proc_entry = proc_create(DEVICE_NAME, 0444, NULL,&nvt_flash_fops); + NVT_proc_entry = proc_create(DEVICE_NAME, 0444, NULL, &nvt_flash_fops); if (NVT_proc_entry == NULL) { NVT_ERR("Failed!\n"); return -ENOMEM; @@ -653,7 +646,7 @@ void nvt_ts_wakeup_gesture_report(uint8_t gesture_id, uint8_t *data) NVT_LOG("gesture_id = %d\n", gesture_id); - switch (gesture_id) { + switch (gesture_id) { case GESTURE_WORD_C: NVT_LOG("Gesture : Word-C.\n"); keycode = gesture_key_array[0]; @@ -708,7 +701,7 @@ void nvt_ts_wakeup_gesture_report(uint8_t gesture_id, uint8_t *data) break; default: break; - } + } if (keycode > 0) { input_report_key(ts->input_dev, keycode, 1); @@ -774,13 +767,8 @@ static int nvt_parse_dt(struct device *dev) NVT_LOG("ibb_reg_name = %s\n", name); } -#ifdef NVT_TOUCH_COUNT_DUMP - ts->dump_click_count = - of_property_read_bool(np, "novatek,dump-click-count"); -#endif - retval = of_property_read_u32(np, "novatek,config-array-size", - (u32 *) & ts->config_array_size); + (u32 *) &ts->config_array_size); if (retval) { NVT_LOG("Unable to get array size\n"); return retval; @@ -865,6 +853,7 @@ static const char *nvt_get_config(struct nvt_ts_data *ts) NVT_LOG("Choose config %d: %s", i, ts->config_array[i].nvt_cfg_name); ts->current_index = i; + return ts->config_array[i].nvt_cfg_name; } @@ -1013,69 +1002,16 @@ static int nvt_gpio_config(struct nvt_ts_data *ts) return ret; } -#if NVT_TOUCH_ESD_PROTECT -void nvt_esd_check_enable(uint8_t enable) -{ - /* enable/disable esd check flag */ - esd_check = enable; - /* update interrupt timer */ - irq_timer = jiffies; - /* clear esd_retry counter, if protect function is enabled */ - esd_retry = enable ? 0 : esd_retry; -} - -static uint8_t nvt_fw_recovery(uint8_t *point_data) -{ - uint8_t i = 0; - uint8_t detected = true; - - /* check pattern */ - for (i=1 ; i<7 ; i++) { - if (point_data[i] != 0x77) { - detected = false; - break; - } - } - - return detected; -} - -static void nvt_esd_check_func(struct work_struct *work) -{ - unsigned int timer = jiffies_to_msecs(jiffies - irq_timer); - - /* - *NVT_ERR("esd_check = %d (retry %d/%d)\n", esd_check, esd_retry, esd_retry_max); //DEBUG - */ - if (esd_retry >= esd_retry_max) - nvt_esd_check_enable(false); - - if ((timer > NVT_TOUCH_ESD_CHECK_PERIOD) && esd_check) { - NVT_ERR("do ESD recovery, timer = %d, retry = %d\n", timer, esd_retry); - /* do esd recovery, bootloader reset */ - nvt_bootloader_reset(); - /* update interrupt timer */ - irq_timer = jiffies; - /* update esd_retry counter */ - esd_retry++; - } - - queue_delayed_work(nvt_esd_check_wq, &nvt_esd_check_work, - msecs_to_jiffies(NVT_TOUCH_ESD_CHECK_PERIOD)); -} -#endif /* #if NVT_TOUCH_ESD_PROTECT */ - static void nvt_switch_mode_work(struct work_struct *work) { struct nvt_mode_switch *ms = container_of(work, struct nvt_mode_switch, switch_mode_work); struct nvt_ts_data *data = ms->nvt_data; unsigned char value = ms->mode; - if (value >= INPUT_EVENT_WAKUP_MODE_OFF && value <= INPUT_EVENT_WAKUP_MODE_ON) { + if (value >= INPUT_EVENT_WAKUP_MODE_OFF && value <= INPUT_EVENT_WAKUP_MODE_ON) data->gesture_enabled = value - INPUT_EVENT_WAKUP_MODE_OFF; - } else { + else NVT_ERR("Does not support touch mode %d\n", value); - } if (ms != NULL) { kfree(ms); @@ -1120,7 +1056,7 @@ static int nvt_input_event(struct input_dev *dev, unsigned int type, unsigned in return: n.a. *******************************************************/ -static void nvt_ts_work_func(struct work_struct *work) +static void nvt_ts_work_func(void) { int32_t ret = -1; uint8_t point_data[POINT_DATA_LEN + 1] = {0}; @@ -1151,27 +1087,12 @@ static void nvt_ts_work_func(struct work_struct *work) NVT_ERR("CTP_I2C_READ failed.(%d)\n", ret); goto XFER_ERROR; } -/* - //--- dump I2C buf --- - for (i = 0; i < 10; i++) { - printk("%02X %02X %02X %02X %02X %02X ", point_data[1+i*6], point_data[2+i*6], point_data[3+i*6], point_data[4+i*6], point_data[5+i*6], point_data[6+i*6]); - } - printk("\n"); -*/ - -#if NVT_TOUCH_ESD_PROTECT - if (nvt_fw_recovery(point_data)) { - nvt_esd_check_enable(true); - goto XFER_ERROR; - } -#endif /* #if NVT_TOUCH_ESD_PROTECT */ #if WAKEUP_GESTURE - if (bTouchIsAwake == 0) { + if (unlikely(bTouchIsAwake == 0)) { input_id = (uint8_t)(point_data[1] >> 3); nvt_ts_wakeup_gesture_report(input_id, point_data); - enable_irq(ts->client->irq); - mutex_unlock(&ts->lock); + goto XFER_ERROR; return; } #endif @@ -1185,10 +1106,6 @@ static void nvt_ts_work_func(struct work_struct *work) continue; if (((point_data[position] & 0x07) == 0x01) || ((point_data[position] & 0x07) == 0x02)) { /*finger down (enter & moving)*/ -#if NVT_TOUCH_ESD_PROTECT - /* update interrupt timer */ - irq_timer = jiffies; -#endif /* #if NVT_TOUCH_ESD_PROTECT */ input_x = (uint32_t)(point_data[position + 1] << 4) + (uint32_t) (point_data[position + 3] >> 4); input_y = (uint32_t)(point_data[position + 2] << 4) + (uint32_t) (point_data[position + 3] & 0x0F); if ((input_x < 0) || (input_y < 0)) @@ -1251,19 +1168,19 @@ static void nvt_ts_work_func(struct work_struct *work) #if TOUCH_KEY_NUM > 0 if (point_data[61] == 0xF8) { - for (i = 0; i < ts->max_button_num; i++) { - input_report_key(ts->input_dev, touch_key_array[i], ((point_data[62] >> i) & 0x01)); - } + for (i = 0; i < ts->max_button_num; i++) + input_report_key( + ts->input_dev, touch_key_array[i], + ((point_data[62] >> i) & 0x01)); } else { - for (i = 0; i < ts->max_button_num; i++) { + for (i = 0; i < ts->max_button_num; i++) input_report_key(ts->input_dev, touch_key_array[i], 0); - } } #endif +XFER_ERROR: input_sync(ts->input_dev); -XFER_ERROR: enable_irq(ts->client->irq); mutex_unlock(&ts->lock); @@ -1282,7 +1199,10 @@ static irqreturn_t nvt_ts_irq_handler(int32_t irq, void *dev_id) if (bTouchIsAwake == 0) { dev_dbg(&ts->client->dev, "%s gesture wakeup\n", __func__); } - queue_work(nvt_wq, &ts->nvt_work); + + pm_qos_update_request(&ts->pm_qos_req, 100); + nvt_ts_work_func(); + pm_qos_update_request(&ts->pm_qos_req, PM_QOS_DEFAULT_VALUE); return IRQ_HANDLED; } @@ -1318,13 +1238,13 @@ void nvt_stop_crc_reboot(void) for (retry = 5; retry > 0; retry--) { /*---write i2c cmds to reset idle : 1st---*/ - buf[0]=0x00; - buf[1]=0xA5; + buf[0] = 0x00; + buf[1] = 0xA5; CTP_I2C_WRITE(ts->client, I2C_HW_Address, buf, 2); /*---write i2c cmds to reset idle : 2rd---*/ - buf[0]=0x00; - buf[1]=0xA5; + buf[0] = 0x00; + buf[1] = 0xA5; CTP_I2C_WRITE(ts->client, I2C_HW_Address, buf, 2); msleep(1); @@ -1445,14 +1365,6 @@ static int8_t nvt_ts_check_chip_ver_trim(void) return ret; } -#ifdef NVT_TOUCH_COUNT_DUMP -static ssize_t nvt_touch_suspend_notify_show(struct device *dev, struct device_attribute *attr, - char *buf) -{ - return snprintf(buf, PAGE_SIZE, "%d\n", !bTouchIsAwake); -} -static DEVICE_ATTR(touch_suspend_notify, (S_IRUGO | S_IRGRP), nvt_touch_suspend_notify_show, NULL); -#endif static int32_t nvt_ts_suspend(struct device *dev); static int32_t nvt_ts_resume(struct device *dev); @@ -1510,7 +1422,7 @@ static ssize_t tpdbg_write(struct file *file, const char __user *buf, size_t siz cmd[size] = '\0'; if (!strncmp(cmd, "irq-disable", 11)) - disable_irq(ts->client->irq); + disable_irq_nosync(ts->client->irq); else if (!strncmp(cmd, "irq-enable", 10)) enable_irq(ts->client->irq); else if (!strncmp(cmd, "tp-sd-en", 8)) @@ -1585,29 +1497,30 @@ static int nvt_pinctrl_init(struct nvt_ts_data *nvt_data) static ssize_t nvt_panel_color_show(struct device *dev, struct device_attribute *attr, char *buf) { - return snprintf(buf, PAGE_SIZE, "%c\n", ts->lockdown_info[2]); + return scnprintf(buf, PAGE_SIZE, "%c\n", ts->lockdown_info[2]); } static ssize_t nvt_panel_vendor_show(struct device *dev, struct device_attribute *attr, char *buf) { - return snprintf(buf, PAGE_SIZE, "%c\n", ts->lockdown_info[6]); + return scnprintf(buf, PAGE_SIZE, "%c\n", ts->lockdown_info[6]); } static ssize_t nvt_panel_display_show(struct device *dev, struct device_attribute *attr, char *buf) { - return snprintf(buf, PAGE_SIZE, "%c\n", ts->lockdown_info[1]); + return scnprintf(buf, PAGE_SIZE, "%c\n", ts->lockdown_info[1]); } -static DEVICE_ATTR(panel_vendor, (S_IRUGO), nvt_panel_vendor_show, NULL); -static DEVICE_ATTR(panel_color, (S_IRUGO), nvt_panel_color_show, NULL); -static DEVICE_ATTR(panel_display, (S_IRUGO), nvt_panel_display_show, NULL); +static DEVICE_ATTR(panel_vendor, (0444), nvt_panel_vendor_show, NULL); +static DEVICE_ATTR(panel_color, (0444), nvt_panel_color_show, NULL); +static DEVICE_ATTR(panel_display, (0444), nvt_panel_display_show, NULL); static struct attribute *nvt_attr_group[] = { &dev_attr_panel_vendor.attr, &dev_attr_panel_color.attr, &dev_attr_panel_display.attr, + NULL, }; /******************************************************* @@ -1623,7 +1536,6 @@ static int32_t nvt_ts_probe(struct i2c_client *client, const struct i2c_device_i #if ((TOUCH_KEY_NUM > 0) || WAKEUP_GESTURE) int32_t retry = 0; #endif - char *tp_maker = NULL; NVT_LOG("start\n"); @@ -1634,6 +1546,7 @@ static int32_t nvt_ts_probe(struct i2c_client *client, const struct i2c_device_i } ts->client = client; + ts->input_proc = NULL; i2c_set_clientdata(client, ts); /*---parse dts---*/ @@ -1667,6 +1580,7 @@ static int32_t nvt_ts_probe(struct i2c_client *client, const struct i2c_device_i /* need 10ms delay after POR(power on reset) */ msleep(10); + mutex_init(&ts->xbuf_lock); /*---check chip version trim---*/ ret = nvt_ts_check_chip_ver_trim(); @@ -1686,13 +1600,15 @@ static int32_t nvt_ts_probe(struct i2c_client *client, const struct i2c_device_i mutex_unlock(&ts->lock); /*---create workqueue---*/ - nvt_wq = create_workqueue("nvt_wq"); + nvt_wq = alloc_workqueue("nvt_wq", + WQ_HIGHPRI | WQ_UNBOUND | WQ_FREEZABLE | + WQ_MEM_RECLAIM, 0); if (!nvt_wq) { NVT_ERR("nvt_wq create workqueue failed\n"); ret = -ENOMEM; goto err_create_nvt_wq_failed; } - INIT_WORK(&ts->nvt_work, nvt_ts_work_func); + /*---allocate input device---*/ ts->input_dev = input_allocate_device(); if (ts->input_dev == NULL) { @@ -1710,7 +1626,7 @@ static int32_t nvt_ts_probe(struct i2c_client *client, const struct i2c_device_i ts->int_trigger_type = INT_TRIGGER_TYPE; /*---set input device info.---*/ - ts->input_dev->evbit[0] = BIT_MASK(EV_SYN) | BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS) ; + ts->input_dev->evbit[0] = BIT_MASK(EV_SYN) | BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS); ts->input_dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH); ts->input_dev->propbit[0] = BIT(INPUT_PROP_DIRECT); @@ -1739,12 +1655,12 @@ static int32_t nvt_ts_probe(struct i2c_client *client, const struct i2c_device_i #endif #if WAKEUP_GESTURE - for (retry = 0; retry < (sizeof(gesture_key_array) / sizeof(gesture_key_array[0])); retry++) { + for (retry = 0; retry < (ARRAY_SIZE(gesture_key_array)); retry++) { input_set_capability(ts->input_dev, EV_KEY, gesture_key_array[retry]); } #endif - sprintf(ts->phys, "input/ts"); + scnprintf(ts->phys, PAGE_SIZE, "input/ts"); ts->input_dev->name = NVT_TS_NAME; ts->input_dev->phys = ts->phys; ts->input_dev->id.bustype = BUS_I2C; @@ -1764,13 +1680,16 @@ static int32_t nvt_ts_probe(struct i2c_client *client, const struct i2c_device_i /* we should enable the reg for lpwg mode */ /*nvt_enable_reg(ts, true);*/ + pm_qos_add_request(&ts->pm_qos_req, PM_QOS_CPU_DMA_LATENCY, + PM_QOS_DEFAULT_VALUE); + /*---set int-pin & request irq---*/ client->irq = gpio_to_irq(ts->irq_gpio); if (client->irq) { NVT_LOG("int_trigger_type=%d\n", ts->int_trigger_type); #if WAKEUP_GESTURE - ret = request_irq(client->irq, nvt_ts_irq_handler, ts->int_trigger_type | IRQF_ONESHOT, client->name, ts); + ret = request_threaded_irq(client->irq, NULL, nvt_ts_irq_handler, ts->int_trigger_type | IRQF_ONESHOT, client->name, ts); #else ret = request_irq(client->irq, nvt_ts_irq_handler, ts->int_trigger_type, client->name, ts); #endif @@ -1778,10 +1697,11 @@ static int32_t nvt_ts_probe(struct i2c_client *client, const struct i2c_device_i NVT_ERR("request irq failed. ret=%d\n", ret); goto err_int_request_failed; } else { - disable_irq(client->irq); + disable_irq_nosync(client->irq); NVT_LOG("request irq %d succeed\n", client->irq); } } + update_hardware_info(TYPE_TOUCH, 5); ret = nvt_get_lockdown_info(ts->lockdown_info); @@ -1791,13 +1711,10 @@ static int32_t nvt_ts_probe(struct i2c_client *client, const struct i2c_device_i NVT_ERR("Lockdown:0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x,0x%02x\n", ts->lockdown_info[0], ts->lockdown_info[1], ts->lockdown_info[2], ts->lockdown_info[3], ts->lockdown_info[4], ts->lockdown_info[5], ts->lockdown_info[6], ts->lockdown_info[7]); + update_hardware_info(TYPE_TP_MAKER, ts->lockdown_info[0] - 0x30); } ts->fw_name = nvt_get_config(ts); - tp_maker = kzalloc(20, GFP_KERNEL); - if (tp_maker == NULL) - NVT_ERR("fail to alloc vendor name memory\n"); - device_init_wakeup(&client->dev, 1); ts->dev_pm_suspend = false; init_completion(&ts->dev_pm_suspend_completion); @@ -1814,13 +1731,6 @@ static int32_t nvt_ts_probe(struct i2c_client *client, const struct i2c_device_i queue_delayed_work(nvt_fwu_wq, &ts->nvt_fwu_work, msecs_to_jiffies(14000)); #endif -#if NVT_TOUCH_ESD_PROTECT - INIT_DELAYED_WORK(&nvt_esd_check_work, nvt_esd_check_func); - nvt_esd_check_wq = create_workqueue("nvt_esd_check_wq"); - queue_delayed_work(nvt_esd_check_wq, &nvt_esd_check_work, - msecs_to_jiffies(NVT_TOUCH_ESD_CHECK_PERIOD)); -#endif /* #if NVT_TOUCH_ESD_PROTECT */ - /*---set device node---*/ #if NVT_TOUCH_PROC ret = nvt_flash_proc_init(); @@ -1853,15 +1763,6 @@ static int32_t nvt_ts_probe(struct i2c_client *client, const struct i2c_device_i NVT_ERR("register drm_notifier failed. ret=%d\n", ret); goto err_register_drm_notif_failed; } -#elif defined(CONFIG_HAS_EARLYSUSPEND) - ts->early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN + 1; - ts->early_suspend.suspend = nvt_ts_early_suspend; - ts->early_suspend.resume = nvt_ts_late_resume; - ret = register_early_suspend(&ts->early_suspend); - if (ret) { - NVT_ERR("register early suspend failed. ret=%d\n", ret); - goto err_register_early_suspend_failed; - } #endif ts->attrs.attrs = nvt_attr_group; @@ -1870,29 +1771,11 @@ static int32_t nvt_ts_probe(struct i2c_client *client, const struct i2c_device_i NVT_ERR("Cannot create sysfs structure!\n"); } -#ifdef NVT_TOUCH_COUNT_DUMP - if (ts->nvt_tp_class == NULL) - ts->nvt_tp_class = class_create(THIS_MODULE, "touch"); - ts->nvt_touch_dev = device_create(ts->nvt_tp_class, NULL, 0x62, ts, "touch_suspend_notify"); - - if (IS_ERR(ts->nvt_touch_dev)) { - NVT_ERR("ERROR: Failed to create device for the sysfs!\n"); - goto err_register_tp_class; - } - - dev_set_drvdata(ts->nvt_touch_dev, ts); - ret = sysfs_create_file(&ts->nvt_touch_dev->kobj, &dev_attr_touch_suspend_notify.attr); - - if (ret) { - NVT_ERR("ERROR: Failed to create sysfs group!\n"); - goto err_register_tp_class; - } -#endif ts->event_wq = alloc_workqueue("nvt-event-queue", WQ_UNBOUND | WQ_HIGHPRI | WQ_CPU_INTENSIVE, 1); if (!ts->event_wq) { NVT_ERR("ERROR: Cannot create work thread\n"); - goto err_register_tp_class; + goto err_register_drm_notif_failed; } INIT_WORK(&ts->resume_work, nvt_resume_work); @@ -1914,22 +1797,15 @@ static int32_t nvt_ts_probe(struct i2c_client *client, const struct i2c_device_i err_pm_workqueue: destroy_workqueue(ts->event_wq); -#ifdef NVT_TOUCH_COUNT_DUMP -err_register_tp_class: - device_destroy(ts->nvt_tp_class, 0x62); - class_destroy(ts->nvt_tp_class); - ts->nvt_tp_class = NULL; -#endif #if defined(CONFIG_DRM) err_register_drm_notif_failed: drm_unregister_client(&ts->notifier); -#elif defined(CONFIG_HAS_EARLYSUSPEND) -err_register_early_suspend_failed: #endif #if (NVT_TOUCH_PROC || NVT_TOUCH_EXT_PROC || NVT_TOUCH_MP) err_init_NVT_ts: #endif + pm_qos_remove_request(&ts->pm_qos_req); free_irq(client->irq, ts); #if BOOT_UPDATE_FIRMWARE err_create_nvt_fwu_wq_failed: @@ -1965,19 +1841,6 @@ static int32_t nvt_ts_remove(struct i2c_client *client) #if defined(CONFIG_DRM) if (drm_unregister_client(&ts->notifier)) NVT_ERR("Error occurred while unregistering drm_notifier.\n"); -#elif defined(CONFIG_HAS_EARLYSUSPEND) - unregister_early_suspend(&ts->early_suspend); -#endif -#ifdef NVT_TOUCH_COUNT_DUMP - if (ts->dump_click_count && !ts->current_clicknum_file) { - kfree(ts->current_clicknum_file); - ts->current_clicknum_file = NULL; - } - sysfs_remove_file(&ts->nvt_touch_dev->kobj, - &dev_attr_touch_suspend_notify.attr); - device_destroy(ts->nvt_tp_class, 0x62); - class_destroy(ts->nvt_tp_class); - ts->nvt_tp_class = NULL; #endif destroy_workqueue(ts->event_wq); @@ -1989,6 +1852,8 @@ static int32_t nvt_ts_remove(struct i2c_client *client) NVT_LOG("Removing driver...\n"); + pm_qos_remove_request(&ts->pm_qos_req); + free_irq(client->irq, ts); input_unregister_device(ts->input_dev); i2c_set_clientdata(client, NULL); @@ -2023,25 +1888,14 @@ static int32_t nvt_ts_suspend(struct device *dev) bTouchIsAwake = 0; -#if NVT_TOUCH_ESD_PROTECT - cancel_delayed_work_sync(&nvt_esd_check_work); - nvt_esd_check_enable(false); -#endif /* #if NVT_TOUCH_ESD_PROTECT */ - if (ts->gesture_enabled) { /*---write i2c command to enter "wakeup gesture mode"---*/ buf[0] = EVENT_MAP_HOST_CMD; buf[1] = 0x13; -#if 0 /* Do not set 0xFF first, ToDo */ - buf[2] = 0xFF; - buf[3] = 0xFF; - CTP_I2C_WRITE(ts->client, I2C_FW_Address, buf, 4); -#else CTP_I2C_WRITE(ts->client, I2C_FW_Address, buf, 2); -#endif NVT_LOG("Enabled touch wakeup gesture\n"); } else { - disable_irq(ts->client->irq); + disable_irq_nosync(ts->client->irq); /*---write i2c command to enter "deep sleep mode"---*/ buf[0] = EVENT_MAP_HOST_CMD; buf[1] = 0x11; @@ -2052,7 +1906,7 @@ static int32_t nvt_ts_suspend(struct device *dev) if (ret < 0) { NVT_ERR("Failed to select %s pinstate %d\n", - PINCTRL_STATE_ACTIVE, ret); + PINCTRL_STATE_SUSPEND, ret); } } else { NVT_ERR("Failed to init pinctrl\n"); @@ -2121,10 +1975,6 @@ static int32_t nvt_ts_resume(struct device *dev) } } -#if NVT_TOUCH_ESD_PROTECT - queue_delayed_work(nvt_esd_check_wq, &nvt_esd_check_work, - msecs_to_jiffies(NVT_TOUCH_ESD_CHECK_PERIOD)); -#endif /* #if NVT_TOUCH_ESD_PROTECT */ bTouchIsAwake = 1; @@ -2159,13 +2009,7 @@ static int drm_notifier_callback(struct notifier_block *self, unsigned long even /*drm_dsi_ulps_enable(true);*/ /*drm_dsi_ulps_suspend_enable(true);*/ } - flush_workqueue(ts->event_wq); nvt_ts_suspend(&ts->client->dev); -#ifdef NVT_TOUCH_COUNT_DUMP - sysfs_notify(&ts->nvt_touch_dev->kobj, NULL, - "touch_suspend_notify"); -#endif - } else if (*blank == DRM_BLANK_UNBLANK) { if (ts->gesture_enabled) { gpio_direction_output(ts->reset_tddi, 0); @@ -2183,12 +2027,7 @@ static int drm_notifier_callback(struct notifier_block *self, unsigned long even /*drm_dsi_ulps_suspend_enable(false);*/ nvt_enable_reg(ts, false); } - flush_workqueue(ts->event_wq); - queue_work(ts->event_wq, &ts->resume_work); -#ifdef NVT_TOUCH_COUNT_DUMP - sysfs_notify(&ts->nvt_touch_dev->kobj, NULL, - "touch_suspend_notify"); -#endif + nvt_ts_resume(&ts->client->dev); } } @@ -2222,37 +2061,6 @@ static const struct dev_pm_ops nvt_dev_pm_ops = { .suspend = nvt_pm_suspend, .resume = nvt_pm_resume, }; -#elif defined(CONFIG_HAS_EARLYSUSPEND) -/******************************************************* -Description: - Novatek touchscreen driver early suspend function. - -return: - n.a. -*******************************************************/ -static void nvt_ts_early_suspend(struct early_suspend *h) -{ - nvt_ts_suspend(ts->client, PMSG_SUSPEND); -} - -/******************************************************* -Description: - Novatek touchscreen driver late resume function. - -return: - n.a. -*******************************************************/ -static void nvt_ts_late_resume(struct early_suspend *h) -{ - nvt_ts_resume(ts->client); -} -#endif - -#if 0 -static const struct dev_pm_ops nvt_ts_dev_pm_ops = { - .suspend = nvt_ts_suspend, - .resume = nvt_ts_resume, -}; #endif static const struct i2c_device_id nvt_ts_id[] = { @@ -2335,11 +2143,6 @@ static void __exit nvt_driver_exit(void) if (nvt_fwu_wq) destroy_workqueue(nvt_fwu_wq); #endif - -#if NVT_TOUCH_ESD_PROTECT - if (nvt_esd_check_wq) - destroy_workqueue(nvt_esd_check_wq); -#endif /* #if NVT_TOUCH_ESD_PROTECT */ } /*late_initcall(nvt_driver_init);*/ diff --git a/drivers/input/touchscreen/nt36xxx/nt36xxx.h b/drivers/input/touchscreen/nt36xxx/nt36xxx.h index fffbbe76615c..8f451de397d8 100644 --- a/drivers/input/touchscreen/nt36xxx/nt36xxx.h +++ b/drivers/input/touchscreen/nt36xxx/nt36xxx.h @@ -22,17 +22,16 @@ #include #include -#ifdef CONFIG_HAS_EARLYSUSPEND -#include -#endif + +#include #include "nt36xxx_mem_map.h" #define PINCTRL_STATE_ACTIVE "pmx_ts_active" #define PINCTRL_STATE_SUSPEND "pmx_ts_suspend" #define PINCTRL_STATE_RELEASE "pmx_ts_release" - -#define NVT_DEBUG 1 +#define NVT_COORDS_ARR_SIZE 2 +#define NVT_DEBUG 0 /*---GPIO number---*/ #define NVTTOUCH_INT_PIN 943 @@ -74,7 +73,13 @@ extern const uint16_t touch_key_array[TOUCH_KEY_NUM]; /*---Customerized func.---*/ #define NVT_TOUCH_PROC 1 #define NVT_TOUCH_EXT_PROC 1 + +#ifdef CONFIG_TOUCHSCREEN_NT36XXX_MPCTRL #define NVT_TOUCH_MP 1 +#else +#define NVT_TOUCH_MP 0 +#endif + #define MT_PROTOCOL_B 1 #define WAKEUP_GESTURE 1 #if WAKEUP_GESTURE @@ -83,31 +88,19 @@ extern const uint16_t gesture_key_array[]; #define BOOT_UPDATE_FIRMWARE 1 #define BOOT_UPDATE_FIRMWARE_NAME "novatek_nt36672_e10.fw" -/*---ESD Protect.---*/ -#define NVT_TOUCH_ESD_PROTECT 0 -#define NVT_TOUCH_ESD_CHECK_PERIOD 1500 /* ms */ #define NVT_LOCKDOWN_SIZE 8 -#define NVT_TOUCH_COUNT_DUMP -#ifdef NVT_TOUCH_COUNT_DUMP -#define TOUCH_COUNT_FILE_MAXSIZE 50 -#endif - struct nvt_config_info { u8 tp_vendor; u8 tp_color; u8 tp_hw_version; const char *nvt_cfg_name; const char *nvt_limit_name; -#ifdef NVT_TOUCH_COUNT_DUMP - const char *clicknum_file_name; -#endif }; struct nvt_ts_data { struct i2c_client *client; struct input_dev *input_dev; - struct work_struct nvt_work; struct delayed_work nvt_fwu_work; struct regulator *vddio_reg; struct regulator *lab_reg; @@ -130,8 +123,6 @@ struct nvt_ts_data { int8_t phys[32]; #if defined(CONFIG_DRM) struct notifier_block notifier; -#elif defined(CONFIG_HAS_EARLYSUSPEND) - struct early_suspend early_suspend; #endif uint8_t fw_ver; uint8_t x_num; @@ -151,6 +142,8 @@ struct nvt_ts_data { const struct nvt_ts_mem_map *mmap; uint8_t carrier_system; uint16_t nvt_pid; + uint8_t xbuf[1025]; + struct mutex xbuf_lock; int gesture_enabled; int glove_enabled; @@ -158,21 +151,15 @@ struct nvt_ts_data { int stylus_enabled; int cover_enabled; int grip_enabled; - int dbclick_count; size_t config_array_size; int current_index; bool dev_pm_suspend; - struct work_struct suspend_work; + struct completion dev_pm_suspend_completion; struct work_struct resume_work; struct workqueue_struct *event_wq; - struct completion dev_pm_suspend_completion; -#ifdef NVT_TOUCH_COUNT_DUMP - struct class *nvt_tp_class; - struct device *nvt_touch_dev; - bool dump_click_count; - char *current_clicknum_file; -#endif + struct pm_qos_request pm_qos_req; + struct proc_dir_entry *input_proc; }; struct nvt_mode_switch { @@ -182,7 +169,7 @@ struct nvt_mode_switch { }; #if NVT_TOUCH_PROC -struct nvt_flash_data{ +struct nvt_flash_data { rwlock_t lock; struct i2c_client *client; }; @@ -197,11 +184,11 @@ typedef enum { } RST_COMPLETE_STATE; typedef enum { - EVENT_MAP_HOST_CMD = 0x50, - EVENT_MAP_HANDSHAKING_or_SUB_CMD_BYTE = 0x51, - EVENT_MAP_RESET_COMPLETE = 0x60, - EVENT_MAP_FWINFO = 0x78, - EVENT_MAP_PROJECTID = 0x9A, + EVENT_MAP_HOST_CMD = 0x50, + EVENT_MAP_HANDSHAKING_or_SUB_CMD_BYTE = 0x51, + EVENT_MAP_RESET_COMPLETE = 0x60, + EVENT_MAP_FWINFO = 0x78, + EVENT_MAP_PROJECTID = 0x9A, } I2C_EVENT_MAP; /*---extern structures---*/ @@ -216,9 +203,6 @@ extern int32_t nvt_check_fw_reset_state(RST_COMPLETE_STATE check_reset_state); extern int32_t nvt_get_fw_info(void); extern int32_t nvt_clear_fw_status(void); extern int32_t nvt_check_fw_status(void); -#if NVT_TOUCH_ESD_PROTECT -extern void nvt_esd_check_enable(uint8_t enable); -#endif /* #if NVT_TOUCH_ESD_PROTECT */ extern void nvt_stop_crc_reboot(void); extern int32_t nvt_get_lockdown_info(char *lockdata); diff --git a/drivers/input/touchscreen/nt36xxx/nt36xxx_ext_proc.c b/drivers/input/touchscreen/nt36xxx/nt36xxx_ext_proc.c index 1c7785e55b81..5d3a3ac14cbc 100644 --- a/drivers/input/touchscreen/nt36xxx/nt36xxx_ext_proc.c +++ b/drivers/input/touchscreen/nt36xxx/nt36xxx_ext_proc.c @@ -108,7 +108,7 @@ void nvt_change_mode(uint8_t mode) *******************************************************/ uint8_t nvt_get_fw_pipe(void) { - uint8_t buf[8]= {0}; + uint8_t buf[8] = {0}; /*---set xdata index to EVENT BUF ADDR---*/ buf[0] = 0xFF; @@ -392,10 +392,6 @@ static int32_t nvt_fw_version_open(struct inode *inode, struct file *file) NVT_LOG("++\n"); -#if NVT_TOUCH_ESD_PROTECT - nvt_esd_check_enable(false); -#endif /* #if NVT_TOUCH_ESD_PROTECT */ - if (nvt_get_fw_info()) { mutex_unlock(&ts->lock); return -EAGAIN; @@ -431,10 +427,6 @@ static int32_t nvt_baseline_open(struct inode *inode, struct file *file) NVT_LOG("++\n"); -#if NVT_TOUCH_ESD_PROTECT - nvt_esd_check_enable(false); -#endif /* #if NVT_TOUCH_ESD_PROTECT */ - if (nvt_clear_fw_status()) { mutex_unlock(&ts->lock); return -EAGAIN; @@ -491,10 +483,6 @@ static int32_t nvt_raw_open(struct inode *inode, struct file *file) NVT_LOG("++\n"); -#if NVT_TOUCH_ESD_PROTECT - nvt_esd_check_enable(false); -#endif /* #if NVT_TOUCH_ESD_PROTECT */ - if (nvt_clear_fw_status()) { mutex_unlock(&ts->lock); return -EAGAIN; @@ -558,10 +546,6 @@ static int32_t nvt_diff_open(struct inode *inode, struct file *file) NVT_LOG("++\n"); -#if NVT_TOUCH_ESD_PROTECT - nvt_esd_check_enable(false); -#endif /* #if NVT_TOUCH_ESD_PROTECT */ - if (nvt_clear_fw_status()) { mutex_unlock(&ts->lock); return -EAGAIN; @@ -629,10 +613,6 @@ static int32_t nvt_xiaomi_config_info_open(struct inode *inode, struct file *fil NVT_LOG("++\n"); -#if NVT_TOUCH_ESD_PROTECT - nvt_esd_check_enable(false); -#endif /* #if NVT_TOUCH_ESD_PROTECT */ - /*---set xdata index to EVENT BUF ADDR---*/ buf[0] = 0xFF; buf[1] = (ts->mmap->EVENT_BUF_ADDR >> 16) & 0xFF; @@ -840,10 +820,6 @@ static int32_t nvt_xiaomi_lockdown_info_open(struct inode *inode, struct file *f NVT_LOG("++\n"); -#if NVT_TOUCH_ESD_PROTECT - nvt_esd_check_enable(false); -#endif /* #if NVT_TOUCH_ESD_PROTECT */ - if (nvt_get_xiaomi_lockdown_info()) { mutex_unlock(&ts->lock); return -EAGAIN; @@ -878,10 +854,6 @@ int32_t nvt_get_lockdown_info(char *lockdata) return -ERESTARTSYS; } -#if NVT_TOUCH_ESD_PROTECT - nvt_esd_check_enable(false); -#endif /* #if NVT_TOUCH_ESD_PROTECT */ - ret = nvt_get_oem_data(data_buf, 0x1E000, 8); if (ret < 0) { @@ -909,7 +881,7 @@ int32_t nvt_get_lockdown_info(char *lockdata) *******************************************************/ int32_t nvt_extra_proc_init(void) { - NVT_proc_fw_version_entry = proc_create(NVT_FW_VERSION, 0444, NULL,&nvt_fw_version_fops); + NVT_proc_fw_version_entry = proc_create(NVT_FW_VERSION, 0444, NULL, &nvt_fw_version_fops); if (NVT_proc_fw_version_entry == NULL) { NVT_ERR("create proc/nvt_fw_version Failed!\n"); return -ENOMEM; @@ -917,7 +889,7 @@ int32_t nvt_extra_proc_init(void) NVT_LOG("create proc/nvt_fw_version Succeeded!\n"); } - NVT_proc_baseline_entry = proc_create(NVT_BASELINE, 0444, NULL,&nvt_baseline_fops); + NVT_proc_baseline_entry = proc_create(NVT_BASELINE, 0444, NULL, &nvt_baseline_fops); if (NVT_proc_baseline_entry == NULL) { NVT_ERR("create proc/nvt_baseline Failed!\n"); return -ENOMEM; @@ -925,7 +897,7 @@ int32_t nvt_extra_proc_init(void) NVT_LOG("create proc/nvt_baseline Succeeded!\n"); } - NVT_proc_raw_entry = proc_create(NVT_RAW, 0444, NULL,&nvt_raw_fops); + NVT_proc_raw_entry = proc_create(NVT_RAW, 0444, NULL, &nvt_raw_fops); if (NVT_proc_raw_entry == NULL) { NVT_ERR("create proc/nvt_raw Failed!\n"); return -ENOMEM; @@ -933,7 +905,7 @@ int32_t nvt_extra_proc_init(void) NVT_LOG("create proc/nvt_raw Succeeded!\n"); } - NVT_proc_diff_entry = proc_create(NVT_DIFF, 0444, NULL,&nvt_diff_fops); + NVT_proc_diff_entry = proc_create(NVT_DIFF, 0444, NULL, &nvt_diff_fops); if (NVT_proc_diff_entry == NULL) { NVT_ERR("create proc/nvt_diff Failed!\n"); return -ENOMEM; diff --git a/drivers/input/touchscreen/nt36xxx/nt36xxx_fw_update.c b/drivers/input/touchscreen/nt36xxx/nt36xxx_fw_update.c index 0f77554be0a0..0680c733e31c 100644 --- a/drivers/input/touchscreen/nt36xxx/nt36xxx_fw_update.c +++ b/drivers/input/touchscreen/nt36xxx/nt36xxx_fw_update.c @@ -1,6 +1,6 @@ /* * Copyright (C) 2010 - 2017 Novatek, Inc. - * Copyright (C) 2019 XiaoMi, Inc. + * Copyright (C) 2018 XiaoMi, Inc. * * $Revision: 21600 $ * $Date: 2018-01-12 15:21:45 +0800 (週五, 12 一月 2018) $ @@ -45,8 +45,8 @@ int32_t update_firmware_request(char *filename) { int32_t ret = 0; - if (NULL == filename) { - return -EPERM; + if (filename == NULL) { + return -1; } NVT_LOG("filename is %s\n", filename); @@ -85,7 +85,7 @@ void update_firmware_release(void) if (fw_entry) { release_firmware(fw_entry); } - fw_entry=NULL; + fw_entry = NULL; } /******************************************************* @@ -163,7 +163,7 @@ int32_t Resume_PD(void) /* Check 0xAA (Resume Command) */ retry = 0; - while(1) { + while (1) { msleep(1); buf[0] = 0x00; buf[1] = 0x00; @@ -178,7 +178,7 @@ int32_t Resume_PD(void) retry++; if (unlikely(retry > 20)) { NVT_ERR("Check 0xAA (Resume Command) error!! status=0x%02X\n", buf[1]); - return -EPERM; + return -1; } } msleep(10); @@ -211,7 +211,7 @@ int32_t Check_CheckSum(void) if (Resume_PD()) { NVT_ERR("Resume PD error!!\n"); - return -EPERM; + return -1; } fw_bin_size = fw_entry->size; @@ -256,7 +256,7 @@ int32_t Check_CheckSum(void) retry++; if (unlikely(retry > 5)) { NVT_ERR("Check 0xAA (Fast Read Command) failed, buf[1]=0x%02X, retry=%d\n", buf[1], retry); - return -EPERM; + return -1; } } /* Read Checksum (write addr high byte & middle byte) */ @@ -321,7 +321,7 @@ int32_t Init_BootLoader(void) /* Check 0xAA (Initiate Flash Block) */ retry = 0; - while(1) { + while (1) { msleep(1); buf[0] = 0x00; buf[1] = 0x00; @@ -336,11 +336,11 @@ int32_t Init_BootLoader(void) retry++; if (unlikely(retry > 20)) { NVT_ERR("Check 0xAA (Inittial Flash Block) error!! status=0x%02X\n", buf[1]); - return -EPERM; + return -1; } } - NVT_LOG("Init OK \n"); + NVT_LOG("Init OK\n"); msleep(20); return 0; @@ -388,7 +388,7 @@ int32_t Erase_Flash(void) retry++; if (unlikely(retry > 20)) { NVT_ERR("Check 0xAA (Write Enable for Write Status Register) error!! status=0x%02X\n", buf[1]); - return -EPERM; + return -1; } } @@ -418,7 +418,7 @@ int32_t Erase_Flash(void) retry++; if (unlikely(retry > 20)) { NVT_ERR("Check 0xAA (Write Status Register) error!! status=0x%02X\n", buf[1]); - return -EPERM; + return -1; } } @@ -449,7 +449,7 @@ int32_t Erase_Flash(void) retry++; if (unlikely(retry > 100)) { NVT_ERR("Check 0xAA (Read Status for Write Status Register) failed, buf[1]=0x%02X, buf[2]=0x%02X, retry=%d\n", buf[1], buf[2], retry); - return -EPERM; + return -1; } } @@ -484,7 +484,7 @@ int32_t Erase_Flash(void) retry++; if (unlikely(retry > 20)) { NVT_ERR("Check 0xAA (Write Enable) error!! status=0x%02X\n", buf[1]); - return -EPERM; + return -1; } } @@ -518,7 +518,7 @@ int32_t Erase_Flash(void) retry++; if (unlikely(retry > 20)) { NVT_ERR("Check 0xAA (Sector Erase) failed, buf[1]=0x%02X, retry=%d\n", buf[1], retry); - return -EPERM; + return -1; } } @@ -549,12 +549,12 @@ int32_t Erase_Flash(void) retry++; if (unlikely(retry > 100)) { NVT_ERR("Check 0xAA (Read Status) failed, buf[1]=0x%02X, buf[2]=0x%02X, retry=%d\n", buf[1], buf[2], retry); - return -EPERM; + return -1; } } } - NVT_LOG("Erase OK \n"); + NVT_LOG("Erase OK\n"); return 0; } @@ -619,7 +619,7 @@ int32_t Write_Flash(void) retry++; if (unlikely(retry > 20)) { NVT_ERR("Check 0xAA (Write Enable) error!! status=0x%02X\n", buf[1]); - return -EPERM; + return -1; } } @@ -636,11 +636,11 @@ int32_t Write_Flash(void) } } if (fw_entry->size - Flash_Address >= 256) - tmpvalue=(Flash_Address >> 16) + ((Flash_Address >> 8) & 0xFF) + (Flash_Address & 0xFF) + 0x00 + (255); + tmpvalue = (Flash_Address >> 16) + ((Flash_Address >> 8) & 0xFF) + (Flash_Address & 0xFF) + 0x00 + (255); else - tmpvalue=(Flash_Address >> 16) + ((Flash_Address >> 8) & 0xFF) + (Flash_Address & 0xFF) + 0x00 + (fw_entry->size - Flash_Address - 1); + tmpvalue = (Flash_Address >> 16) + ((Flash_Address >> 8) & 0xFF) + (Flash_Address & 0xFF) + 0x00 + (fw_entry->size - Flash_Address - 1); - for (k = 0;k < min(fw_entry->size - Flash_Address,(size_t)256); k++) + for (k = 0; k < min(fw_entry->size - Flash_Address, (size_t)256); k++) tmpvalue += fw_entry->data[Flash_Address + k]; tmpvalue = 255 - tmpvalue + 1; @@ -652,7 +652,7 @@ int32_t Write_Flash(void) buf[3] = ((Flash_Address >> 8) & 0xFF); buf[4] = (Flash_Address & 0xFF); buf[5] = 0x00; - buf[6] = min(fw_entry->size - Flash_Address,(size_t)256) - 1; + buf[6] = min(fw_entry->size - Flash_Address, (size_t)256) - 1; buf[7] = tmpvalue; ret = CTP_I2C_WRITE(ts->client, I2C_HW_Address, buf, 8); if (ret < 0) { @@ -676,7 +676,7 @@ int32_t Write_Flash(void) retry++; if (unlikely(retry > 20)) { NVT_ERR("Check 0xAA (Page Program) failed, buf[1]=0x%02X, retry=%d\n", buf[1], retry); - return -EPERM; + return -1; } } if (buf[1] == 0xEA) { @@ -711,7 +711,7 @@ int32_t Write_Flash(void) retry++; if (unlikely(retry > 100)) { NVT_ERR("Check 0xAA (Read Status) failed, buf[1]=0x%02X, buf[2]=0x%02X, retry=%d\n", buf[1], buf[2], retry); - return -EPERM; + return -1; } } if (buf[1] == 0xEA) { @@ -723,7 +723,7 @@ int32_t Write_Flash(void) } NVT_LOG("Programming...%2d%%\n", 100); - NVT_LOG("Program OK \n"); + NVT_LOG("Program OK \n"); return 0; } @@ -790,7 +790,7 @@ int32_t Verify_Flash(void) retry++; if (unlikely(retry > 5)) { NVT_ERR("Check 0xAA (Fast Read Command) failed, buf[1]=0x%02X, retry=%d\n", buf[1], retry); - return -EPERM; + return -1; } } /* Read Checksum (write addr high byte & middle byte) */ @@ -816,12 +816,12 @@ int32_t Verify_Flash(void) if (WR_Filechksum[i] != RD_Filechksum[i]) { NVT_ERR("Verify Fail%d!!\n", i); NVT_ERR("RD_Filechksum[%d]=0x%04X, WR_Filechksum[%d]=0x%04X\n", i, RD_Filechksum[i], i, WR_Filechksum[i]); - return -EPERM; + return -1; } } } - NVT_LOG("Verify OK \n"); + NVT_LOG("Verify OK\n"); return 0; } @@ -938,7 +938,7 @@ int32_t nvt_check_flash_end_flag(void) } if (buf[1] != 0xAA) { NVT_ERR("Check 0xAA (Read Command) error!! status=0x%02X\n", buf[1]); - return -EPERM; + return -1; } msleep(10); @@ -1002,10 +1002,6 @@ void Boot_Update_Firmware(struct work_struct *work) mutex_lock(&ts->lock); -#if NVT_TOUCH_ESD_PROTECT - nvt_esd_check_enable(false); -#endif /* #if NVT_TOUCH_ESD_PROTECT */ - nvt_sw_reset_idle(); ret = Check_CheckSum(); diff --git a/drivers/input/touchscreen/nt36xxx/nt36xxx_mem_map.h b/drivers/input/touchscreen/nt36xxx/nt36xxx_mem_map.h index c717e0958998..175f1d4715c7 100644 --- a/drivers/input/touchscreen/nt36xxx/nt36xxx_mem_map.h +++ b/drivers/input/touchscreen/nt36xxx/nt36xxx_mem_map.h @@ -1,6 +1,6 @@ /* * Copyright (C) 2010 - 2017 Novatek, Inc. - * Copyright (C) 2019 XiaoMi, Inc. + * Copyright (C) 2018 XiaoMi, Inc. * * $Revision: 20544 $ * $Date: 2017-12-20 11:08:15 +0800 (週三, 20 十二月 2017) $ diff --git a/drivers/input/touchscreen/nt36xxx/nt36xxx_mp_ctrlram.c b/drivers/input/touchscreen/nt36xxx/nt36xxx_mp_ctrlram.c index faa343818819..0acc2b299619 100644 --- a/drivers/input/touchscreen/nt36xxx/nt36xxx_mp_ctrlram.c +++ b/drivers/input/touchscreen/nt36xxx/nt36xxx_mp_ctrlram.c @@ -47,44 +47,44 @@ printk(fmt, ##args); \ } while (0) -static uint8_t *RecordResult_Short; -static uint8_t *RecordResult_Short_Diff; -static uint8_t *RecordResult_Short_Base; -static uint8_t *RecordResult_Open; -static uint8_t *RecordResult_FWMutual; -static uint8_t *RecordResult_FW_CC; -static uint8_t *RecordResult_FW_CC_I; -static uint8_t *RecordResult_FW_CC_Q; -static uint8_t *RecordResult_FW_DiffMax; -static uint8_t *RecordResult_FW_DiffMin; - -static int32_t TestResult_Short; -static int32_t TestResult_Short_Diff; -static int32_t TestResult_Short_Base; -static int32_t TestResult_Open; -static int32_t TestResult_FW_Rawdata; -static int32_t TestResult_FWMutual; -static int32_t TestResult_FW_CC; -static int32_t TestResult_FW_CC_I; -static int32_t TestResult_FW_CC_Q; -static int32_t TestResult_Noise; -static int32_t TestResult_FW_DiffMax; -static int32_t TestResult_FW_DiffMin; - -static int32_t *RawData_Short; -static int32_t *RawData_Short_Diff; -static int32_t *RawData_Short_Base; -static int32_t *RawData_Open; -static int32_t *RawData_Diff; -static int32_t *RawData_Diff_Min; -static int32_t *RawData_Diff_Max; -static int32_t *RawData_FWMutual; -static int32_t *RawData_FW_CC; -static int32_t *RawData_FW_CC_I; -static int32_t *RawData_FW_CC_Q; - -static struct proc_dir_entry *NVT_proc_selftest_entry; -static int8_t nvt_mp_test_result_printed; +static uint8_t *RecordResult_Short = NULL; +static uint8_t *RecordResult_Short_Diff = NULL; +static uint8_t *RecordResult_Short_Base = NULL; +static uint8_t *RecordResult_Open = NULL; +static uint8_t *RecordResult_FWMutual = NULL; +static uint8_t *RecordResult_FW_CC = NULL; +static uint8_t *RecordResult_FW_CC_I = NULL; +static uint8_t *RecordResult_FW_CC_Q = NULL; +static uint8_t *RecordResult_FW_DiffMax = NULL; +static uint8_t *RecordResult_FW_DiffMin = NULL; + +static int32_t TestResult_Short = 0; +static int32_t TestResult_Short_Diff = 0; +static int32_t TestResult_Short_Base = 0; +static int32_t TestResult_Open = 0; +static int32_t TestResult_FW_Rawdata = 0; +static int32_t TestResult_FWMutual = 0; +static int32_t TestResult_FW_CC = 0; +static int32_t TestResult_FW_CC_I = 0; +static int32_t TestResult_FW_CC_Q = 0; +static int32_t TestResult_Noise = 0; +static int32_t TestResult_FW_DiffMax = 0; +static int32_t TestResult_FW_DiffMin = 0; + +static int32_t *RawData_Short = NULL; +static int32_t *RawData_Short_Diff = NULL; +static int32_t *RawData_Short_Base = NULL; +static int32_t *RawData_Open = NULL; +static int32_t *RawData_Diff = NULL; +static int32_t *RawData_Diff_Min = NULL; +static int32_t *RawData_Diff_Max = NULL; +static int32_t *RawData_FWMutual = NULL; +static int32_t *RawData_FW_CC = NULL; +static int32_t *RawData_FW_CC_I = NULL; +static int32_t *RawData_FW_CC_Q = NULL; + +static struct proc_dir_entry *NVT_proc_selftest_entry = NULL; +static int8_t nvt_mp_test_result_printed = 0; extern void nvt_change_mode(uint8_t mode); extern uint8_t nvt_get_fw_pipe(void); @@ -324,12 +324,6 @@ static void nvt_print_criteria(void) NVT_LOG("--\n"); } -static int32_t nvt_save_rawdata_to_csv(int32_t *rawdata, uint8_t x_ch, - uint8_t y_ch, const char *file_path, uint32_t offset) -{ - return 0; -} - static int32_t nvt_polling_hand_shake_status(void) { uint8_t buf[8] = {0}; @@ -372,7 +366,7 @@ static int32_t nvt_polling_hand_shake_status(void) CTP_I2C_READ(ts->client, I2C_FW_Address, buf, 6); NVT_ERR("Read back 5 bytes from offset EVENT_MAP_HOST_CMD: 0x%02X, 0x%02X, 0x%02X, 0x%02X, 0x%02X\n", buf[1], buf[2], buf[3], buf[4], buf[5]); - return -EPERM; + return -1; } else { return 0; } @@ -457,11 +451,6 @@ static int32_t nvt_read_baseline(int32_t *xdata) #endif /* #if TOUCH_KEY_NUM > 0 */ printk("%s:\n", __func__); - /* Save Rawdata to CSV file */ - if (nvt_save_rawdata_to_csv(xdata, X_Channel, Y_Channel, FW_RAWDATA_CSV_FILE, 0) < 0) { - NVT_ERR("save rawdata to CSV file failed\n"); - return -EAGAIN; - } NVT_LOG("--\n"); @@ -518,28 +507,12 @@ static int32_t nvt_read_CC(int32_t *xdata) printk("%s:\n", __func__); if (ts->carrier_system) { printk("%s:RawData_CC_I:\n", __func__); - /* Save Rawdata to CSV file */ - if (nvt_save_rawdata_to_csv(RawData_FW_CC_I, X_Channel, Y_Channel, FW_CC_CSV_FILE, 0) < 0) { - NVT_ERR("save rawdata to CSV file failed\n"); - return -EAGAIN; - } + #if TOUCH_KEY_NUM > 0 rawdata_cc_q_offset = Y_Channel * X_Channel * 7 + Y_Channel * 2 + Key_Channel * 7 + 2; #else rawdata_cc_q_offset = Y_Channel * X_Channel * 7 + Y_Channel * 2; #endif /* #if TOUCH_KEY_NUM > 0 */ - printk("%s:RawData_CC_Q:\n", __func__); - /* Save Rawdata to CSV file */ - if (nvt_save_rawdata_to_csv(RawData_FW_CC_Q, X_Channel, Y_Channel, FW_CC_CSV_FILE, rawdata_cc_q_offset) < 0) { - NVT_ERR("save rawdata to CSV file failed\n"); - return -EAGAIN; - } - } else { - /* Save Rawdata to CSV file */ - if (nvt_save_rawdata_to_csv(xdata, X_Channel, Y_Channel, FW_CC_CSV_FILE, 0) < 0) { - NVT_ERR("save rawdata to CSV file failed\n"); - return -EAGAIN; - } } NVT_LOG("--\n"); @@ -638,11 +611,6 @@ static int32_t nvt_read_fw_noise(int32_t *xdata) nvt_change_mode(NORMAL_MODE); printk("%s:RawData_Diff_Max:\n", __func__); - /* Save Rawdata to CSV file */ - if (nvt_save_rawdata_to_csv(RawData_Diff_Max, X_Channel, Y_Channel, NOISE_TEST_CSV_FILE, 0) < 0) { - NVT_ERR("save rawdata to CSV file failed\n"); - return -EAGAIN; - } if (!ts->carrier_system) { #if TOUCH_KEY_NUM > 0 @@ -651,11 +619,7 @@ static int32_t nvt_read_fw_noise(int32_t *xdata) rawdata_diff_min_offset = Y_Channel * X_Channel * 7 + Y_Channel * 2; #endif /* #if TOUCH_KEY_NUM > 0 */ printk("%s:RawData_Diff_Min:\n", __func__); - /* Save Rawdata to CSV file */ - if (nvt_save_rawdata_to_csv(RawData_Diff_Min, X_Channel, Y_Channel, NOISE_TEST_CSV_FILE, rawdata_diff_min_offset) < 0) { - NVT_ERR("save rawdata to CSV file failed\n"); - return -EAGAIN; - } + } NVT_LOG("--\n"); @@ -788,14 +752,7 @@ static int32_t nvt_read_fw_open(int32_t *xdata) /*---Leave Test Mode---*/ nvt_change_mode(NORMAL_MODE); - - printk("%s:RawData_Open\n", __func__); - /* Save RawData to CSV file */ - if (nvt_save_rawdata_to_csv(xdata, X_Channel, Y_Channel, OPEN_TEST_CSV_FILE, 0) < 0) { - NVT_ERR("save rawdata to CSV file failed\n"); - return -EAGAIN; - } NVT_LOG("--\n"); @@ -830,9 +787,9 @@ static int32_t nvt_read_fw_short(int32_t *xdata) } #if TOUCH_KEY_NUM > 0 - rawdata_buf = (uint8_t *)kzalloc((X_Channel * Y_Channel + Key_Channel) * 2, GFP_KERNEL); + rawdata_buf = (uint8_t *)kzalloc((X_Channel * Y_Channel + Key_Channel) * 2, GFP_KERNEL); #else - rawdata_buf = (uint8_t *)kzalloc(X_Channel * Y_Channel * 2, GFP_KERNEL); + rawdata_buf = (uint8_t *)kzalloc(X_Channel * Y_Channel * 2, GFP_KERNEL); #endif /* #if TOUCH_KEY_NUM > 0 */ if (!rawdata_buf) { NVT_ERR("kzalloc for rawdata_buf failed!\n"); @@ -870,7 +827,7 @@ static int32_t nvt_read_fw_short(int32_t *xdata) raw_btn_pipe_addr = ts->mmap->RAW_BTN_PIPE1_ADDR; } - /*---change xdata index---*/ + /*---change xdata index---*/ buf[0] = 0xFF; buf[1] = (uint8_t)((raw_btn_pipe_addr >> 16) & 0xFF); buf[2] = (uint8_t)((raw_btn_pipe_addr >> 8) & 0xFF); @@ -911,8 +868,7 @@ static int32_t nvt_read_fw_short(int32_t *xdata) #if TOUCH_KEY_NUM > 0 /* to get button short baseline rawdata at pipe1 */ raw_btn_pipe_addr = ts->mmap->RAW_BTN_PIPE1_ADDR; - - /*---change xdata index---*/ + /*---change xdata index---*/ buf[0] = 0xFF; buf[1] = (uint8_t)((raw_btn_pipe_addr >> 16) & 0xFF); buf[2] = (uint8_t)((raw_btn_pipe_addr >> 8) & 0xFF); @@ -948,11 +904,7 @@ static int32_t nvt_read_fw_short(int32_t *xdata) printk("%s:RawData_Short_Diff:\n", __func__); else printk("%s:RawData_Short\n", __func__); - /* Save Rawdata to CSV file */ - if (nvt_save_rawdata_to_csv(xdata, X_Channel, Y_Channel, SHORT_TEST_CSV_FILE, 0) < 0) { - NVT_ERR("save rawdata to CSV file failed\n"); - return -EAGAIN; - } + if (ts->carrier_system) { #if TOUCH_KEY_NUM > 0 rawdata_short_base_offset = Y_Channel * X_Channel * 7 + Y_Channel * 2 + Key_Channel * 7 + 2; @@ -960,11 +912,7 @@ static int32_t nvt_read_fw_short(int32_t *xdata) rawdata_short_base_offset = Y_Channel * X_Channel * 7 + Y_Channel * 2; #endif /* #if TOUCH_KEY_NUM > 0 */ printk("%s:RawData_Short_Base:\n", __func__); - /* Save Rawdata to CSV file */ - if (nvt_save_rawdata_to_csv(RawData_Short_Base, X_Channel, Y_Channel, SHORT_TEST_CSV_FILE, rawdata_short_base_offset) < 0) { - NVT_ERR("save rawdata to CSV file failed\n"); - return -EAGAIN; - } + } NVT_LOG("--\n"); @@ -984,7 +932,7 @@ static int32_t RawDataTest_SinglePoint_Sub(int32_t rawdata[], uint8_t RecordResu int32_t i = 0; int32_t j = 0; #if TOUCH_KEY_NUM > 0 - int32_t k = 0; + int32_t k = 0; #endif /* #if TOUCH_KEY_NUM > 0 */ int32_t iArrayIndex = 0; bool isPass = true; @@ -1036,7 +984,7 @@ static int32_t RawDataTest_SinglePoint_Sub(int32_t rawdata[], uint8_t RecordResu #endif /* #if TOUCH_KEY_NUM > 0 */ if (isPass == false) { - return -EPERM; /* FAIL */ + return -1; /* FAIL */ } else { return 0; /* PASS */ } @@ -1059,48 +1007,59 @@ void print_selftest_result(struct seq_file *m, int32_t TestResult, uint8_t Recor #endif /* #if TOUCH_KEY_NUM > 0 */ switch (TestResult) { - case 0: - nvt_mp_seq_printf(m, " PASS!\n"); - break; + case 0: + nvt_mp_seq_printf(m, " PASS!\n"); + break; - case 1: - nvt_mp_seq_printf(m, " ERROR! Read Data FAIL!\n"); - break; + case 1: + nvt_mp_seq_printf(m, " ERROR! Read Data FAIL!\n"); + break; - case -1: - nvt_mp_seq_printf(m, " FAIL!\n"); - nvt_mp_seq_printf(m, "RecordResult:\n"); - for (i = 0; i < y_len; i++) { - for (j = 0; j < x_len; j++) { - iArrayIndex = i * x_len + j; - nvt_mp_seq_printf(m, "0x%02X, ", RecordResult[iArrayIndex]); - } - nvt_mp_seq_printf(m, "\n"); - } -#if TOUCH_KEY_NUM > 0 - for (k = 0; k < Key_Channel; k++) { - iArrayIndex = y_len * x_len + k; + case -1: + nvt_mp_seq_printf(m, " FAIL!\n"); + nvt_mp_seq_printf(m, "RecordResult:\n"); + + for (i = 0; i < y_len; i++) { + for (j = 0; j < x_len; j++) { + iArrayIndex = i * x_len + j; nvt_mp_seq_printf(m, "0x%02X, ", RecordResult[iArrayIndex]); } + nvt_mp_seq_printf(m, "\n"); -#endif /* #if TOUCH_KEY_NUM > 0 */ - nvt_mp_seq_printf(m, "ReadData:\n"); - for (i = 0; i < y_len; i++) { - for (j = 0; j < x_len; j++) { - iArrayIndex = i * x_len + j; - nvt_mp_seq_printf(m, "%5d, ", rawdata[iArrayIndex]); - } - nvt_mp_seq_printf(m, "\n"); - } + } + #if TOUCH_KEY_NUM > 0 - for (k = 0; k < Key_Channel; k++) { - iArrayIndex = y_len * x_len + k; + + for (k = 0; k < Key_Channel; k++) { + iArrayIndex = y_len * x_len + k; + nvt_mp_seq_printf(m, "0x%02X, ", RecordResult[iArrayIndex]); + } + + nvt_mp_seq_printf(m, "\n"); +#endif /* #if TOUCH_KEY_NUM > 0 */ + nvt_mp_seq_printf(m, "ReadData:\n"); + + for (i = 0; i < y_len; i++) { + for (j = 0; j < x_len; j++) { + iArrayIndex = i * x_len + j; nvt_mp_seq_printf(m, "%5d, ", rawdata[iArrayIndex]); } + nvt_mp_seq_printf(m, "\n"); + } + +#if TOUCH_KEY_NUM > 0 + + for (k = 0; k < Key_Channel; k++) { + iArrayIndex = y_len * x_len + k; + nvt_mp_seq_printf(m, "%5d, ", rawdata[iArrayIndex]); + } + + nvt_mp_seq_printf(m, "\n"); #endif /* #if TOUCH_KEY_NUM > 0 */ - break; + break; } + nvt_mp_seq_printf(m, "\n"); } @@ -1185,8 +1144,7 @@ static int32_t c_show_selftest(struct seq_file *m, void *v) nvt_mp_test_result_printed = 1; NVT_LOG("--\n"); - - return 0; + return 0; } /******************************************************* @@ -1270,10 +1228,6 @@ static int32_t nvt_selftest_open(struct inode *inode, struct file *file) return -ERESTARTSYS; } -#if NVT_TOUCH_ESD_PROTECT - nvt_esd_check_enable(false); -#endif /* #if NVT_TOUCH_ESD_PROTECT */ - if (nvt_get_fw_info()) { mutex_unlock(&ts->lock); NVT_ERR("get fw info failed!\n"); @@ -1290,7 +1244,7 @@ static int32_t nvt_selftest_open(struct inode *inode, struct file *file) * Ex. nvt_pid = 500A * mpcriteria = "novatek-mp-criteria-500A" */ - snprintf(mpcriteria, PAGE_SIZE, "novatek-mp-criteria-%04X", ts->nvt_pid); + snprintf(mpcriteria, sizeof(mpcriteria), "novatek-mp-criteria-%04X", ts->nvt_pid); nvt_mp_parse_dt(np, mpcriteria); } else { @@ -1685,10 +1639,6 @@ static int nvt_short_test(void) return -ERESTARTSYS; } -#if NVT_TOUCH_ESD_PROTECT - nvt_esd_check_enable(false); -#endif /* #if NVT_TOUCH_ESD_PROTECT */ - if (nvt_get_fw_info()) { mutex_unlock(&ts->lock); NVT_ERR("get fw info failed!\n"); @@ -1772,10 +1722,6 @@ static int nvt_open_test(void) return -ERESTARTSYS; } -#if NVT_TOUCH_ESD_PROTECT - nvt_esd_check_enable(false); -#endif /* #if NVT_TOUCH_ESD_PROTECT */ - if (nvt_get_fw_info()) { mutex_unlock(&ts->lock); NVT_ERR("get fw info failed!\n"); @@ -1898,11 +1844,11 @@ int32_t nvt_mp_proc_init(void) NVT_proc_selftest_entry = proc_create("nvt_selftest", 0444, NULL, &nvt_selftest_fops); if (NVT_proc_selftest_entry == NULL) { NVT_ERR("create /proc/nvt_selftest Failed!\n"); - return -EPERM; + return -1; } else { if (nvt_mp_buffer_init()) { NVT_ERR("Allocate mp memory failed\n"); - return -EPERM; + return -1; } else { NVT_LOG("create /proc/nvt_selftest Succeeded!\n"); diff --git a/drivers/input/touchscreen/nt36xxx/nt36xxx_mp_ctrlram.h b/drivers/input/touchscreen/nt36xxx/nt36xxx_mp_ctrlram.h index 45c8a8c9fe72..214e5c13c1d6 100644 --- a/drivers/input/touchscreen/nt36xxx/nt36xxx_mp_ctrlram.h +++ b/drivers/input/touchscreen/nt36xxx/nt36xxx_mp_ctrlram.h @@ -2,8 +2,8 @@ * Copyright (C) 2010 - 2017 Novatek, Inc. * Copyright (C) 2019 XiaoMi, Inc. * - * $Revision: 28342 $ - * $Date: 2018-05-18 10:47:10 +0800 (Fri, 18 May 2018) $ + * $Revision: 28670 $ + * $Date: 2018-05-25 15:59:17 +0800 (週五, 25 五月 2018) $ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,17 +20,17 @@ #if NVT_TOUCH_MP static uint32_t IC_X_CFG_SIZE = 18; -static uint32_t IC_Y_CFG_SIZE = 34; +static uint32_t IC_Y_CFG_SIZE = 36; static uint32_t IC_KEY_CFG_SIZE = 4; static uint32_t X_Channel = 18; -static uint32_t Y_Channel = 34; +static uint32_t Y_Channel = 36; static uint32_t Key_Channel = TOUCH_KEY_NUM; static uint8_t AIN_X[40] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 }; static uint8_t AIN_Y[40] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, - 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33 + 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35 }; #if TOUCH_KEY_NUM > 0 @@ -40,148 +40,156 @@ static uint8_t AIN_KEY[8] = { #endif /* #if TOUCH_KEY_NUM > 0 */ static int32_t PS_Config_Lmt_Short_Rawdata_P[40 * 40] = { - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, - 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, 14000, + 14000, 14000, 14000, 14000, 14000, 14000, 14000, #if TOUCH_KEY_NUM > 0 20000, 20000, 20000, #endif /* #if TOUCH_KEY_NUM > 0 */ }; static int32_t PS_Config_Lmt_Short_Rawdata_N[40 * 40] = { - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, - 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, 11000, + 11000, 11000, 11000, 11000, 11000, 11000, 11000, #if TOUCH_KEY_NUM > 0 11550, 11550, 11550, #endif /* #if TOUCH_KEY_NUM > 0 */ @@ -366,226 +374,238 @@ static int32_t PS_Config_Lmt_Short_Base_P[40 * 40] = { }; static int32_t PS_Config_Lmt_Short_Base_N[40 * 40] = { - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, - -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, -2000, + -2000, -2000, -2000, -2000, -2000, -2000, -2000, #if TOUCH_KEY_NUM > 0 -2000, -2000, -2000, #endif /* #if TOUCH_KEY_NUM > 0 */ }; static int32_t PS_Config_Lmt_Open_Rawdata_P[40 * 40] = { - 2667, 2658, 3303, 2676, 2778, 5120, 5120, 5120, 5120, 5120, 5120, 5120, - 5120, 3048, 2949, 3313, 2696, 2713, - 3219, 3223, 3222, 3507, 3467, 3008, 2988, 2977, 2972, 2754, 2758, 2777, - 2796, 3225, 3250, 3535, 3511, 3477, - 3121, 3107, 3108, 3104, 3107, 3086, 3083, 3064, 3054, 3097, 3100, 3121, - 3110, 3124, 3133, 3154, 3157, 3188, - 3088, 3076, 3085, 3081, 3082, 3060, 3056, 3038, 3030, 3064, 3068, 3092, - 3083, 3097, 3108, 3125, 3130, 3157, - 3127, 3114, 3119, 3115, 3113, 3091, 3088, 3068, 3060, 3103, 3106, 3124, - 3118, 3129, 3143, 3161, 3163, 3187, - 3098, 3085, 3091, 3085, 3083, 3062, 3057, 3038, 3032, 3074, 3077, 3093, - 3089, 3100, 3113, 3128, 3132, 3153, - 3135, 3125, 3120, 3114, 3121, 3100, 3093, 3074, 3072, 3110, 3112, 3119, - 3118, 3137, 3149, 3164, 3167, 3188, - 3105, 3095, 3098, 3090, 3090, 3066, 3062, 3043, 3045, 3081, 3084, 3096, - 3094, 3108, 3119, 3131, 3136, 3154, - 3137, 3131, 3131, 3122, 3122, 3098, 3095, 3073, 3077, 3116, 3119, 3130, - 3131, 3145, 3158, 3168, 3172, 3186, - 3104, 3098, 3098, 3088, 3090, 3065, 3061, 3043, 3044, 3089, 3091, 3095, - 3090, 3112, 3124, 3131, 3137, 3150, - 3136, 3132, 3134, 3122, 3115, 3091, 3094, 3078, 3077, 3126, 3127, 3133, - 3127, 3142, 3156, 3169, 3173, 3183, - 3132, 3128, 3129, 3117, 3116, 3093, 3091, 3078, 3078, 3125, 3128, 3129, - 3123, 3141, 3153, 3159, 3163, 3173, - 3165, 3163, 3165, 3150, 3151, 3128, 3123, 3114, 3113, 3165, 3162, 3164, - 3163, 3182, 3190, 3195, 3200, 3207, - 3092, 3087, 3095, 3082, 3081, 3056, 3048, 3041, 3043, 3087, 3081, 3089, - 3087, 3107, 3116, 3117, 3117, 3130, - 3121, 3116, 3126, 3112, 3110, 3085, 3087, 3076, 3073, 3120, 3115, 3122, - 3122, 3143, 3150, 3157, 3154, 3161, - 3081, 3076, 3085, 3071, 3068, 3044, 3047, 3044, 3033, 3082, 3075, 3085, - 3083, 3106, 3110, 3117, 3113, 3118, - 3105, 3105, 3114, 3101, 3094, 3072, 3075, 3069, 3057, 3112, 3106, 3115, - 3115, 3139, 3141, 3149, 3144, 3143, - 3066, 3065, 3071, 3057, 3051, 3031, 3034, 3028, 3024, 3069, 3061, 3070, - 3071, 3095, 3095, 3102, 3099, 3104, - 3099, 3097, 3104, 3091, 3083, 3063, 3068, 3061, 3060, 3104, 3099, 3104, - 3106, 3129, 3129, 3136, 3131, 3141, - 3059, 3055, 3061, 3048, 3040, 3022, 3026, 3019, 3023, 3061, 3057, 3064, - 3064, 3087, 3087, 3094, 3088, 3098, - 3084, 3080, 3091, 3078, 3069, 3050, 3058, 3048, 3051, 3084, 3078, 3093, - 3093, 3116, 3115, 3123, 3115, 3126, - 3046, 3040, 3045, 3032, 3023, 3006, 3012, 3005, 3006, 3047, 3039, 3049, - 3049, 3072, 3070, 3078, 3074, 3082, - 3109, 3101, 3105, 3092, 3084, 3067, 3077, 3073, 3071, 3109, 3101, 3110, - 3109, 3130, 3129, 3136, 3133, 3143, - 3063, 3055, 3055, 3043, 3040, 3025, 3035, 3031, 3029, 3066, 3062, 3069, - 3072, 3091, 3088, 3095, 3090, 3101, - 3058, 3050, 3055, 3041, 3034, 3018, 3028, 3022, 3020, 3052, 3046, 3062, - 3062, 3081, 3080, 3083, 3077, 3087, - 2785, 2776, 2782, 2772, 2769, 2756, 2761, 2755, 2752, 2780, 2777, 2793, - 2796, 2807, 2808, 2809, 2805, 2822, - 2810, 2800, 2806, 2797, 2793, 2780, 2787, 2778, 2778, 2805, 2802, 2818, - 2822, 2832, 2833, 2835, 2831, 2848, - 2771, 2759, 2765, 2755, 2748, 2736, 2747, 2737, 2738, 2766, 2763, 2778, - 2781, 2789, 2790, 2795, 2793, 2810, - 2794, 2782, 2786, 2777, 2774, 2761, 2769, 2759, 2758, 2790, 2788, 2801, - 2805, 2815, 2816, 2819, 2818, 2835, - 2752, 2739, 2743, 2733, 2730, 2718, 2728, 2717, 2716, 2748, 2746, 2758, - 2762, 2773, 2773, 2776, 2777, 2793, - 2776, 2763, 2767, 2757, 2755, 2743, 2752, 2740, 2741, 2771, 2771, 2782, - 2786, 2796, 2797, 2798, 2799, 2817, - 2732, 2719, 2723, 2714, 2711, 2699, 2711, 2698, 2697, 2728, 2727, 2737, - 2741, 2753, 2752, 2756, 2758, 2775, - 2373, 2878, 2879, 2875, 2872, 2858, 2873, 2857, 2856, 2887, 2887, 2898, - 2902, 2914, 2913, 2916, 2916, 2403, - 2421, 3029, 3103, 2897, 2901, 2878, 2870, 2857, 2857, 2888, 2892, 2912, - 2904, 2925, 2923, 2923, 2855, 2258, + 2857, 3296, 3307, 3308, 3294, 3532, 5120, 5120, 5120, 5120, 5120, 5120, + 3262, 3071, 3081, 3095, 3102, 2936, + 3030, 3023, 3011, 3018, 3017, 3008, 2978, 2566, 2531, 2552, 2585, 3008, + 3347, 3352, 3349, 3321, 3311, 3299, + 2948, 2935, 2924, 2929, 2927, 2923, 2923, 2906, 2892, 2936, 2942, 2965, + 2965, 2968, 2977, 2993, 2999, 3022, + 2954, 2940, 2931, 2934, 2933, 2928, 2928, 2908, 2897, 2934, 2941, 2960, + 2965, 2965, 2978, 2990, 2997, 3016, + 2969, 2958, 2950, 2954, 2948, 2943, 2943, 2925, 2912, 2950, 2957, 2975, + 2982, 2981, 2996, 3006, 3013, 3027, + 2958, 2946, 2940, 2942, 2936, 2931, 2930, 2909, 2901, 2933, 2940, 2957, + 2966, 2964, 2980, 2989, 2998, 3007, + 2959, 2947, 2940, 2940, 2936, 2932, 2930, 2908, 2904, 2944, 2949, 2965, + 2976, 2976, 2988, 2997, 3005, 3017, + 2964, 2951, 2946, 2945, 2942, 2936, 2933, 2911, 2908, 2949, 2955, 2970, + 2981, 2983, 2993, 3001, 3011, 3021, + 2961, 2950, 2944, 2943, 2940, 2935, 2932, 2908, 2906, 2951, 2957, 2971, + 2985, 2986, 2995, 3004, 3011, 3020, + 2960, 2950, 2945, 2942, 2939, 2934, 2930, 2910, 2905, 2935, 2940, 2947, + 2955, 2965, 2974, 2981, 2990, 2996, + 2969, 2962, 2960, 2954, 2951, 2947, 2942, 2921, 2916, 2953, 2957, 2966, + 2974, 2983, 2994, 3000, 3007, 3013, + 2982, 2977, 2975, 2970, 2967, 2963, 2955, 2935, 2932, 2944, 2946, 2955, + 2964, 2972, 2982, 2988, 2995, 2999, + 2944, 2941, 2938, 2933, 2931, 2926, 2918, 2898, 2896, 2953, 2950, 2961, + 2972, 2981, 2988, 2994, 3001, 3005, + 2975, 2971, 2969, 2963, 2961, 2956, 2947, 2933, 2928, 2962, 2959, 2970, + 2982, 2990, 2996, 3001, 3008, 3010, + 2963, 2956, 2959, 2953, 2950, 2945, 2938, 2927, 2919, 2971, 2968, 2980, + 2989, 2997, 3004, 3010, 3013, 3016, + 2958, 2952, 2955, 2948, 2946, 2940, 2936, 2923, 2916, 2971, 2967, 2980, + 2989, 2997, 3003, 3009, 3010, 3014, + 2939, 2933, 2936, 2928, 2927, 2921, 2917, 2911, 2895, 2931, 2928, 2942, + 2951, 2958, 2965, 2970, 2970, 2970, + 2949, 2946, 2949, 2943, 2939, 2933, 2930, 2922, 2910, 2961, 2957, 2972, + 2980, 2989, 2993, 2999, 2999, 3000, + 2932, 2929, 2929, 2922, 2921, 2915, 2910, 2903, 2894, 2932, 2926, 2941, + 2952, 2959, 2962, 2968, 2968, 2969, + 2924, 2919, 2921, 2915, 2911, 2906, 2904, 2895, 2889, 2937, 2935, 2948, + 2957, 2963, 2965, 2971, 2971, 2976, + 2935, 2930, 2932, 2924, 2922, 2917, 2913, 2904, 2904, 2927, 2923, 2941, + 2943, 2950, 2954, 2960, 2957, 2965, + 2912, 2907, 2908, 2901, 2897, 2893, 2891, 2880, 2878, 2918, 2914, 2933, + 2934, 2941, 2942, 2950, 2946, 2955, + 2903, 2896, 2897, 2889, 2886, 2881, 2880, 2872, 2869, 2914, 2909, 2927, + 2929, 2935, 2936, 2943, 2943, 2950, + 2653, 2648, 2652, 2647, 2640, 2633, 2636, 2631, 2626, 2659, 2654, 2666, + 2671, 2680, 2683, 2689, 2684, 2693, + 2663, 2658, 2663, 2659, 2653, 2647, 2651, 2645, 2639, 2644, 2640, 2655, + 2658, 2666, 2670, 2672, 2668, 2676, + 2645, 2639, 2644, 2640, 2635, 2628, 2633, 2627, 2622, 2653, 2652, 2668, + 2670, 2678, 2679, 2683, 2680, 2689, + 2656, 2650, 2652, 2647, 2642, 2637, 2642, 2638, 2632, 2635, 2635, 2652, + 2653, 2660, 2664, 2666, 2666, 2673, + 2641, 2633, 2635, 2630, 2626, 2623, 2627, 2622, 2616, 2637, 2637, 2655, + 2654, 2661, 2665, 2668, 2668, 2677, + 2625, 2618, 2619, 2614, 2609, 2607, 2612, 2605, 2599, 2624, 2624, 2642, + 2641, 2649, 2652, 2656, 2656, 2664, + 2628, 2618, 2620, 2615, 2610, 2608, 2613, 2606, 2600, 2618, 2618, 2637, + 2636, 2643, 2646, 2649, 2651, 2660, + 2624, 2615, 2614, 2609, 2606, 2603, 2607, 2600, 2595, 2592, 2593, 2611, + 2610, 2616, 2619, 2623, 2625, 2635, + 2598, 2588, 2587, 2582, 2579, 2575, 2581, 2573, 2569, 2598, 2599, 2616, + 2615, 2623, 2625, 2630, 2632, 2642, + 2583, 2573, 2572, 2568, 2564, 2560, 2568, 2560, 2554, 2578, 2581, 2596, + 2596, 2602, 2604, 2609, 2612, 2622, + 2555, 2544, 2544, 2541, 2538, 2534, 2543, 2533, 2528, 2576, 2577, 2592, + 2593, 2602, 2602, 2606, 2610, 2620, + 2652, 2654, 2654, 2653, 2651, 2645, 2657, 2643, 2637, 2652, 2654, 2669, + 2672, 2681, 2681, 2683, 2687, 2698, + 2436, 2635, 2630, 2630, 2631, 2621, 2624, 2615, 2610, 2656, 2665, 2686, + 2664, 2674, 2670, 2674, 2678, 2260, #if TOUCH_KEY_NUM > 0 13000, 13000, 13000, #endif /* #if TOUCH_KEY_NUM > 0 */ }; static int32_t PS_Config_Lmt_Open_Rawdata_N[40 * 40] = { - 1533, 1528, 1898, 1538, 1597, 50, 50, 50, 50, 50, 50, 50, 50, 1752, - 1695, 1904, 1550, 1560, - 1850, 1853, 1852, 2016, 1993, 1729, 1717, 1711, 1708, 1583, 1585, 1596, - 1607, 1854, 1868, 2032, 2018, 1999, - 1794, 1786, 1786, 1784, 1786, 1774, 1772, 1761, 1756, 1780, 1782, 1794, - 1787, 1796, 1801, 1813, 1814, 1833, - 1775, 1768, 1773, 1771, 1771, 1759, 1757, 1746, 1742, 1761, 1763, 1777, - 1772, 1780, 1786, 1797, 1799, 1815, - 1797, 1790, 1793, 1791, 1789, 1777, 1775, 1764, 1759, 1784, 1786, 1796, - 1792, 1799, 1807, 1817, 1818, 1832, - 1781, 1773, 1776, 1773, 1772, 1760, 1757, 1746, 1743, 1767, 1769, 1778, - 1775, 1782, 1789, 1798, 1800, 1812, - 1802, 1796, 1794, 1790, 1794, 1782, 1778, 1767, 1766, 1788, 1789, 1793, - 1792, 1803, 1810, 1818, 1821, 1832, - 1785, 1779, 1781, 1776, 1776, 1762, 1760, 1749, 1751, 1771, 1773, 1779, - 1778, 1786, 1793, 1800, 1803, 1813, - 1803, 1799, 1800, 1794, 1795, 1781, 1779, 1766, 1769, 1791, 1793, 1799, - 1800, 1808, 1815, 1821, 1823, 1831, - 1784, 1781, 1781, 1775, 1776, 1762, 1760, 1749, 1750, 1776, 1777, 1779, - 1776, 1789, 1796, 1800, 1803, 1811, - 1802, 1800, 1801, 1795, 1791, 1777, 1778, 1769, 1769, 1797, 1797, 1801, - 1798, 1806, 1814, 1822, 1824, 1830, - 1800, 1798, 1799, 1792, 1791, 1778, 1777, 1769, 1769, 1796, 1798, 1798, - 1795, 1806, 1812, 1816, 1818, 1824, - 1819, 1818, 1819, 1811, 1811, 1798, 1795, 1790, 1790, 1819, 1818, 1819, - 1818, 1829, 1834, 1837, 1840, 1844, - 1777, 1774, 1779, 1771, 1771, 1757, 1752, 1748, 1749, 1774, 1771, 1776, - 1774, 1786, 1791, 1792, 1792, 1799, - 1794, 1791, 1797, 1789, 1788, 1773, 1774, 1768, 1766, 1794, 1791, 1795, - 1794, 1806, 1811, 1814, 1813, 1817, - 1771, 1768, 1773, 1765, 1764, 1750, 1751, 1750, 1744, 1771, 1767, 1773, - 1772, 1785, 1788, 1792, 1789, 1792, - 1785, 1785, 1790, 1782, 1778, 1766, 1767, 1764, 1757, 1789, 1786, 1790, - 1791, 1805, 1806, 1810, 1807, 1806, - 1762, 1762, 1765, 1757, 1754, 1742, 1744, 1740, 1738, 1764, 1760, 1765, - 1765, 1779, 1779, 1783, 1781, 1784, - 1781, 1780, 1784, 1777, 1772, 1761, 1763, 1760, 1759, 1784, 1781, 1784, - 1785, 1799, 1798, 1803, 1800, 1805, - 1758, 1756, 1760, 1752, 1747, 1737, 1740, 1736, 1738, 1759, 1757, 1761, - 1761, 1774, 1774, 1779, 1775, 1781, - 1773, 1771, 1777, 1769, 1764, 1753, 1758, 1752, 1754, 1773, 1769, 1778, - 1778, 1791, 1791, 1795, 1790, 1797, - 1751, 1747, 1750, 1743, 1738, 1728, 1732, 1728, 1728, 1751, 1747, 1753, - 1753, 1766, 1765, 1769, 1767, 1772, - 1787, 1782, 1784, 1777, 1773, 1763, 1768, 1766, 1765, 1787, 1782, 1788, - 1787, 1799, 1798, 1803, 1801, 1807, - 1761, 1756, 1756, 1749, 1747, 1739, 1745, 1742, 1741, 1762, 1760, 1764, - 1766, 1777, 1775, 1779, 1776, 1782, - 1758, 1753, 1756, 1748, 1744, 1735, 1740, 1737, 1736, 1754, 1751, 1760, - 1760, 1771, 1770, 1772, 1769, 1775, - 1601, 1595, 1599, 1594, 1592, 1584, 1587, 1584, 1582, 1598, 1596, 1605, - 1607, 1613, 1614, 1615, 1612, 1622, - 1615, 1610, 1613, 1608, 1606, 1598, 1602, 1597, 1597, 1612, 1611, 1620, - 1622, 1628, 1629, 1629, 1627, 1637, - 1593, 1586, 1589, 1584, 1580, 1573, 1579, 1573, 1574, 1590, 1588, 1597, - 1599, 1603, 1604, 1607, 1606, 1615, - 1606, 1599, 1601, 1596, 1594, 1587, 1592, 1586, 1585, 1604, 1603, 1610, - 1612, 1618, 1619, 1620, 1620, 1629, - 1582, 1574, 1576, 1571, 1569, 1563, 1568, 1562, 1561, 1580, 1579, 1585, - 1587, 1594, 1594, 1596, 1596, 1606, - 1596, 1588, 1590, 1585, 1583, 1576, 1582, 1575, 1576, 1593, 1593, 1599, - 1601, 1607, 1608, 1609, 1609, 1619, - 1571, 1563, 1565, 1560, 1558, 1551, 1558, 1551, 1550, 1568, 1568, 1573, - 1576, 1582, 1582, 1584, 1585, 1595, - 1364, 1654, 1655, 1652, 1651, 1643, 1652, 1642, 1642, 1659, 1659, 1666, - 1668, 1675, 1675, 1676, 1676, 1381, - 1392, 1741, 1784, 1665, 1668, 1654, 1649, 1642, 1642, 1660, 1662, 1674, - 1669, 1681, 1680, 1680, 1641, 1298, + 1642, 1894, 1901, 1901, 1893, 2030, 50, 50, 50, 50, 50, 50, 1875, 1765, + 1771, 1779, 1783, 1688, + 1741, 1738, 1731, 1735, 1734, 1729, 1712, 1475, 1455, 1467, 1486, 1729, + 1924, 1927, 1925, 1909, 1903, 1896, + 1694, 1687, 1681, 1683, 1682, 1680, 1680, 1670, 1662, 1688, 1691, 1704, + 1704, 1706, 1711, 1720, 1724, 1737, + 1698, 1690, 1685, 1686, 1686, 1683, 1683, 1672, 1665, 1686, 1691, 1701, + 1704, 1704, 1712, 1718, 1723, 1733, + 1707, 1700, 1696, 1698, 1694, 1692, 1692, 1681, 1674, 1696, 1699, 1710, + 1714, 1713, 1722, 1728, 1732, 1740, + 1700, 1693, 1690, 1691, 1688, 1685, 1684, 1672, 1667, 1686, 1690, 1700, + 1705, 1704, 1713, 1718, 1723, 1729, + 1701, 1694, 1690, 1690, 1688, 1685, 1684, 1672, 1669, 1692, 1695, 1704, + 1710, 1710, 1717, 1723, 1727, 1734, + 1704, 1696, 1693, 1693, 1691, 1688, 1686, 1673, 1672, 1695, 1699, 1707, + 1714, 1715, 1720, 1725, 1731, 1737, + 1702, 1696, 1692, 1691, 1690, 1687, 1685, 1671, 1670, 1696, 1699, 1708, + 1716, 1716, 1722, 1727, 1731, 1736, + 1701, 1696, 1693, 1691, 1689, 1687, 1684, 1673, 1670, 1687, 1690, 1694, + 1699, 1704, 1709, 1713, 1718, 1722, + 1707, 1703, 1702, 1698, 1696, 1694, 1691, 1679, 1676, 1697, 1699, 1705, + 1710, 1715, 1721, 1724, 1729, 1732, + 1714, 1711, 1710, 1707, 1705, 1703, 1699, 1687, 1685, 1692, 1693, 1699, + 1704, 1709, 1714, 1717, 1722, 1724, + 1692, 1690, 1689, 1686, 1685, 1682, 1677, 1666, 1664, 1697, 1696, 1702, + 1708, 1714, 1717, 1721, 1725, 1727, + 1710, 1708, 1706, 1703, 1702, 1699, 1694, 1686, 1683, 1703, 1701, 1707, + 1714, 1718, 1722, 1725, 1729, 1730, + 1703, 1699, 1701, 1697, 1696, 1693, 1689, 1682, 1678, 1708, 1706, 1713, + 1718, 1723, 1727, 1730, 1732, 1734, + 1700, 1697, 1698, 1695, 1693, 1690, 1688, 1680, 1676, 1708, 1706, 1713, + 1718, 1723, 1726, 1729, 1730, 1732, + 1689, 1686, 1688, 1683, 1682, 1679, 1677, 1673, 1664, 1685, 1683, 1691, + 1696, 1700, 1704, 1707, 1707, 1707, + 1695, 1694, 1695, 1691, 1689, 1686, 1684, 1679, 1673, 1702, 1700, 1708, + 1713, 1718, 1720, 1724, 1724, 1724, + 1685, 1683, 1684, 1680, 1679, 1676, 1673, 1668, 1664, 1685, 1682, 1691, + 1697, 1701, 1703, 1706, 1706, 1706, + 1680, 1678, 1679, 1676, 1673, 1670, 1669, 1664, 1661, 1688, 1687, 1695, + 1700, 1703, 1704, 1708, 1708, 1711, + 1687, 1684, 1686, 1681, 1680, 1676, 1675, 1669, 1669, 1682, 1680, 1690, + 1691, 1696, 1698, 1702, 1700, 1704, + 1674, 1671, 1672, 1668, 1665, 1663, 1662, 1656, 1655, 1677, 1675, 1686, + 1686, 1690, 1691, 1695, 1694, 1699, + 1669, 1665, 1665, 1661, 1659, 1656, 1656, 1651, 1649, 1675, 1672, 1683, + 1684, 1687, 1688, 1692, 1692, 1696, + 1525, 1522, 1525, 1521, 1517, 1514, 1515, 1512, 1510, 1528, 1525, 1533, + 1535, 1540, 1542, 1546, 1543, 1548, + 1531, 1528, 1531, 1529, 1525, 1521, 1524, 1520, 1517, 1520, 1518, 1526, + 1528, 1532, 1535, 1536, 1533, 1538, + 1521, 1517, 1520, 1517, 1514, 1510, 1514, 1510, 1507, 1525, 1524, 1533, + 1534, 1539, 1540, 1542, 1540, 1546, + 1527, 1523, 1524, 1522, 1519, 1516, 1519, 1516, 1513, 1515, 1515, 1525, + 1525, 1529, 1531, 1532, 1532, 1536, + 1518, 1514, 1515, 1512, 1509, 1508, 1510, 1507, 1504, 1515, 1516, 1526, + 1526, 1530, 1532, 1533, 1534, 1539, + 1509, 1505, 1505, 1503, 1500, 1498, 1501, 1497, 1494, 1508, 1508, 1519, + 1518, 1522, 1525, 1527, 1527, 1531, + 1510, 1505, 1506, 1503, 1500, 1499, 1502, 1498, 1495, 1505, 1505, 1516, + 1515, 1519, 1521, 1523, 1524, 1529, + 1509, 1503, 1502, 1500, 1498, 1496, 1498, 1495, 1492, 1490, 1490, 1501, + 1500, 1504, 1505, 1508, 1509, 1514, + 1494, 1488, 1487, 1484, 1482, 1480, 1484, 1479, 1477, 1493, 1494, 1504, + 1503, 1508, 1509, 1512, 1513, 1519, + 1485, 1479, 1478, 1476, 1474, 1472, 1476, 1472, 1468, 1482, 1483, 1492, + 1492, 1496, 1497, 1499, 1502, 1507, + 1469, 1462, 1462, 1460, 1459, 1456, 1462, 1456, 1453, 1481, 1481, 1490, + 1490, 1496, 1496, 1498, 1500, 1506, + 1524, 1526, 1526, 1525, 1524, 1520, 1527, 1519, 1516, 1524, 1526, 1534, + 1536, 1541, 1541, 1542, 1545, 1551, + 1400, 1515, 1512, 1512, 1512, 1507, 1508, 1503, 1501, 1527, 1532, 1544, + 1531, 1537, 1535, 1537, 1539, 1299, #if TOUCH_KEY_NUM > 0 6500, 6500, 6500, #endif /* #if TOUCH_KEY_NUM > 0 */ }; static int32_t PS_Config_Lmt_FW_Rawdata_P[40 * 40] = { - 1750, 1750, 1750, 1750, 1750, 4096, 4096, 4096, 4096, 4096, 4096, 4096, - 4096, 1750, 1750, 1750, 1750, 1750, + 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, + 1750, 1750, 1750, 1750, 1750, 1750, + 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, + 1750, 1750, 1750, 1750, 1750, 1750, + 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, + 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, 1750, @@ -658,188 +678,198 @@ static int32_t PS_Config_Lmt_FW_Rawdata_P[40 * 40] = { }; static int32_t PS_Config_Lmt_FW_Rawdata_N[40 * 40] = { - 650, 650, 650, 650, 650, 0, 0, 0, 0, 0, 0, 0, 0, 650, 650, 650, 650, - 650, - 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, - 650, 650, 650, 650, - 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, - 650, 650, 650, 650, - 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, - 650, 650, 650, 650, - 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, - 650, 650, 650, 650, - 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, - 650, 650, 650, 650, - 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, - 650, 650, 650, 650, - 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, - 650, 650, 650, 650, - 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, - 650, 650, 650, 650, - 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, - 650, 650, 650, 650, - 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, - 650, 650, 650, 650, - 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, - 650, 650, 650, 650, - 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, - 650, 650, 650, 650, - 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, - 650, 650, 650, 650, - 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, - 650, 650, 650, 650, - 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, - 650, 650, 650, 650, - 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, - 650, 650, 650, 650, - 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, - 650, 650, 650, 650, - 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, - 650, 650, 650, 650, - 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, - 650, 650, 650, 650, - 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, - 650, 650, 650, 650, - 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, - 650, 650, 650, 650, - 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, - 650, 650, 650, 650, - 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, - 650, 650, 650, 650, - 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, - 650, 650, 650, 650, - 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, - 650, 650, 650, 650, - 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, - 650, 650, 650, 650, - 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, - 650, 650, 650, 650, - 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, - 650, 650, 650, 650, - 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, - 650, 650, 650, 650, - 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, - 650, 650, 650, 650, - 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, - 650, 650, 650, 650, - 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, - 650, 650, 650, 650, - 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, - 650, 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, + 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, 650, + 650, 650, 650, #if TOUCH_KEY_NUM > 0 400, 400, 400, #endif /* #if TOUCH_KEY_NUM > 0 */ }; static int32_t PS_Config_Lmt_FW_CC_P[40 * 40] = { - 116, 116, 120, 112, 114, 511, 511, 511, 511, 511, 511, 511, 511, 119, - 117, 118, 114, 115, - 124, 119, 118, 118, 118, 117, 120, 122, 117, 118, 123, 120, 118, 119, - 118, 120, 121, 127, - 121, 116, 116, 115, 115, 115, 115, 116, 116, 117, 122, 119, 117, 116, - 116, 116, 115, 119, - 121, 117, 116, 115, 116, 116, 115, 117, 117, 118, 122, 119, 119, 117, - 116, 116, 116, 119, - 120, 116, 116, 115, 115, 116, 116, 117, 116, 118, 122, 119, 119, 117, - 117, 117, 116, 119, - 122, 118, 117, 117, 117, 118, 117, 119, 118, 119, 123, 120, 120, 118, - 118, 118, 118, 121, - 119, 115, 115, 115, 115, 115, 115, 116, 116, 117, 120, 118, 118, 116, - 116, 116, 115, 118, - 121, 116, 116, 116, 116, 117, 116, 118, 117, 119, 122, 119, 119, 117, - 117, 117, 117, 120, - 120, 116, 116, 116, 116, 116, 116, 117, 117, 118, 122, 119, 119, 117, - 117, 117, 116, 119, - 122, 118, 117, 118, 118, 118, 118, 119, 119, 122, 123, 120, 120, 118, - 118, 118, 118, 121, - 120, 115, 115, 115, 115, 116, 116, 117, 117, 124, 121, 118, 118, 116, - 116, 116, 116, 119, - 120, 115, 115, 115, 115, 117, 116, 118, 117, 125, 120, 118, 118, 116, - 116, 116, 116, 119, - 122, 118, 118, 118, 118, 120, 119, 122, 120, 128, 122, 120, 121, 119, - 119, 119, 118, 122, - 118, 115, 115, 115, 115, 116, 116, 120, 116, 126, 119, 117, 118, 116, - 116, 116, 116, 119, - 120, 117, 117, 117, 117, 118, 118, 122, 119, 127, 121, 119, 119, 118, - 117, 117, 117, 121, - 119, 116, 116, 116, 116, 117, 117, 119, 117, 127, 121, 119, 119, 117, - 117, 117, 117, 120, - 121, 117, 118, 118, 118, 119, 119, 121, 119, 128, 123, 120, 120, 119, - 119, 119, 119, 122, - 119, 115, 115, 115, 116, 117, 116, 118, 117, 125, 120, 117, 118, 116, - 116, 116, 116, 119, - 120, 116, 117, 117, 117, 118, 117, 119, 120, 126, 121, 119, 119, 118, - 117, 117, 117, 121, - 120, 116, 116, 116, 117, 118, 118, 119, 118, 126, 122, 118, 119, 117, - 117, 117, 117, 121, - 121, 118, 118, 118, 118, 120, 120, 120, 119, 127, 123, 120, 121, 119, - 119, 119, 119, 123, - 118, 115, 115, 115, 115, 117, 116, 118, 116, 124, 121, 117, 117, 117, - 116, 116, 116, 120, - 120, 116, 117, 117, 117, 119, 118, 120, 118, 125, 121, 118, 118, 118, - 117, 118, 118, 122, - 121, 117, 118, 118, 118, 120, 119, 122, 119, 124, 121, 119, 120, 119, - 119, 119, 119, 124, - 119, 116, 116, 115, 116, 118, 117, 120, 117, 121, 119, 117, 118, 117, - 117, 117, 117, 122, - 118, 115, 116, 115, 116, 117, 117, 121, 117, 120, 118, 117, 117, 117, - 116, 117, 117, 122, - 118, 115, 115, 115, 115, 117, 117, 120, 116, 119, 118, 117, 117, 116, - 116, 116, 117, 121, - 120, 116, 117, 117, 117, 119, 118, 121, 118, 120, 119, 118, 119, 118, - 118, 118, 119, 123, - 117, 114, 114, 114, 115, 116, 115, 118, 115, 118, 117, 116, 116, 115, - 115, 116, 116, 121, - 119, 115, 116, 115, 116, 118, 117, 120, 117, 119, 118, 117, 117, 117, - 117, 117, 118, 122, - 119, 116, 116, 116, 116, 117, 118, 121, 117, 119, 118, 117, 118, 116, - 116, 117, 118, 122, - 120, 116, 117, 117, 117, 119, 120, 122, 118, 120, 119, 118, 118, 118, - 118, 119, 120, 124, - 115, 114, 113, 116, 116, 117, 119, 120, 117, 118, 118, 116, 117, 116, - 116, 117, 118, 119, - 113, 115, 115, 116, 117, 118, 116, 118, 118, 117, 122, 120, 118, 116, - 115, 117, 117, 114, + 116, 113, 112, 112, 112, 114, 512, 512, 512, 512, 512, 512, 112, 110, 111, + 110, 112, 113, + 121, 113, 112, 111, 111, 111, 110, 110, 109, 111, 116, 116, 111, 112, 112, + 113, 115, 124, + 119, 112, 111, 110, 109, 109, 108, 108, 107, 108, 112, 112, 110, 110, 110, + 110, 111, 114, + 119, 113, 111, 110, 110, 110, 109, 109, 108, 110, 114, 113, 112, 112, 112, + 112, 113, 116, + 118, 112, 111, 110, 110, 109, 108, 108, 108, 108, 112, 111, 111, 110, 111, + 111, 111, 115, + 119, 112, 111, 111, 110, 110, 109, 108, 108, 109, 113, 112, 111, 111, 111, + 112, 113, 116, + 117, 111, 109, 109, 108, 108, 107, 106, 106, 108, 111, 111, 111, 110, 111, + 111, 111, 114, + 119, 113, 112, 111, 111, 110, 110, 109, 109, 109, 112, 111, 111, 111, 111, + 111, 111, 115, + 117, 112, 110, 110, 109, 109, 109, 107, 107, 110, 114, 113, 113, 112, 113, + 113, 113, 116, + 120, 114, 113, 113, 112, 112, 112, 111, 110, 113, 114, 113, 113, 112, 113, + 113, 113, 117, + 117, 111, 110, 110, 110, 109, 109, 108, 108, 115, 112, 112, 111, 111, 111, + 112, 112, 115, + 117, 112, 111, 111, 110, 110, 109, 109, 109, 115, 111, 111, 111, 110, 111, + 111, 111, 115, + 117, 112, 111, 111, 110, 110, 110, 109, 108, 117, 110, 112, 111, 110, 112, + 112, 112, 115, + 119, 114, 113, 113, 112, 112, 112, 112, 110, 121, 114, 114, 114, 114, 115, + 115, 115, 119, + 116, 111, 111, 110, 110, 110, 109, 111, 108, 117, 111, 111, 111, 111, 111, + 112, 112, 116, + 116, 112, 112, 111, 110, 110, 111, 112, 109, 119, 112, 112, 112, 112, 113, + 113, 113, 117, + 118, 113, 113, 113, 112, 112, 112, 113, 110, 117, 111, 111, 111, 111, 112, + 112, 112, 116, + 119, 114, 114, 114, 113, 112, 113, 113, 111, 119, 114, 113, 113, 113, 114, + 114, 114, 119, + 115, 111, 110, 110, 110, 110, 109, 110, 107, 115, 110, 110, 110, 110, 111, + 111, 111, 115, + 115, 111, 111, 111, 110, 110, 110, 110, 110, 117, 113, 112, 112, 111, 112, + 112, 113, 117, + 116, 112, 111, 111, 111, 111, 111, 110, 109, 117, 113, 111, 111, 111, 113, + 113, 113, 117, + 117, 114, 113, 113, 112, 113, 112, 112, 111, 118, 113, 113, 113, 113, 114, + 114, 115, 120, + 115, 112, 111, 111, 110, 111, 110, 110, 108, 117, 113, 112, 112, 112, 113, + 113, 113, 118, + 115, 112, 111, 111, 110, 111, 111, 111, 109, 116, 111, 111, 111, 112, 112, + 112, 113, 118, + 116, 113, 112, 112, 111, 112, 112, 112, 110, 115, 111, 112, 112, 112, 113, + 113, 113, 119, + 117, 114, 114, 113, 113, 113, 113, 114, 111, 115, 112, 113, 113, 114, 114, + 115, 115, 121, + 115, 112, 112, 111, 111, 112, 112, 112, 109, 112, 109, 111, 111, 111, 112, + 112, 113, 118, + 116, 113, 113, 112, 112, 112, 112, 115, 110, 113, 111, 112, 112, 113, 113, + 114, 115, 120, + 115, 113, 112, 112, 111, 112, 112, 113, 109, 112, 111, 112, 112, 112, 114, + 114, 115, 121, + 117, 114, 114, 114, 114, 114, 114, 115, 112, 113, 112, 113, 114, 114, 115, + 115, 117, 123, + 116, 113, 112, 112, 112, 112, 112, 113, 109, 110, 109, 110, 111, 112, 112, + 113, 114, 120, + 116, 113, 113, 113, 112, 113, 113, 113, 110, 112, 110, 111, 112, 113, 114, + 114, 116, 122, + 115, 113, 112, 112, 112, 112, 113, 113, 110, 111, 111, 112, 112, 113, 114, + 114, 116, 122, + 117, 114, 114, 114, 115, 114, 116, 115, 112, 114, 114, 114, 115, 116, 116, + 117, 118, 125, + 118, 112, 112, 112, 112, 112, 115, 113, 110, 111, 110, 110, 112, 113, 113, + 115, 115, 122, + 113, 112, 109, 108, 109, 108, 107, 108, 106, 108, 113, 114, 114, 114, 115, + 115, 115, 116, #if TOUCH_KEY_NUM > 0 38, 38, 38, #endif /* #if TOUCH_KEY_NUM > 0 */ }; static int32_t PS_Config_Lmt_FW_CC_N[40 * 40] = { - 71, 71, 74, 69, 70, 10, 10, 10, 10, 10, 10, 10, 10, 73, 72, 72, 70, 70, - 76, 73, 72, 72, 72, 72, 73, 75, 72, 72, 75, 74, 72, 73, 72, 74, 74, 78, - 74, 71, 71, 70, 70, 71, 70, 71, 71, 72, 75, 73, 72, 71, 71, 71, 71, 73, - 74, 71, 71, 71, 71, 71, 71, 72, 72, 72, 75, 73, 73, 72, 71, 71, 71, 73, - 74, 71, 71, 71, 71, 71, 71, 72, 71, 72, 75, 73, 73, 72, 71, 72, 71, 73, - 75, 72, 72, 72, 72, 72, 72, 73, 72, 73, 75, 73, 74, 72, 72, 72, 72, 74, - 73, 71, 70, 70, 70, 71, 70, 71, 71, 72, 74, 72, 72, 71, 71, 71, 71, 72, - 74, 71, 71, 71, 71, 72, 71, 72, 72, 73, 75, 73, 73, 72, 71, 72, 71, 73, - 74, 71, 71, 71, 71, 71, 71, 72, 72, 73, 74, 73, 73, 72, 71, 72, 71, 73, - 75, 72, 72, 72, 72, 72, 73, 73, 73, 75, 75, 74, 74, 73, 72, 72, 72, 74, - 73, 71, 71, 71, 71, 71, 71, 72, 71, 76, 74, 72, 72, 71, 71, 71, 71, 73, - 73, 71, 71, 71, 71, 71, 71, 72, 72, 77, 74, 72, 72, 71, 71, 71, 71, 73, - 75, 72, 72, 72, 72, 73, 73, 75, 73, 79, 75, 74, 74, 73, 73, 73, 73, 75, - 73, 70, 70, 70, 71, 71, 71, 74, 71, 77, 73, 72, 72, 71, 71, 71, 71, 73, - 74, 71, 72, 72, 72, 72, 72, 75, 73, 78, 74, 73, 73, 72, 72, 72, 72, 74, - 73, 71, 71, 71, 71, 72, 72, 73, 72, 78, 74, 73, 73, 72, 72, 72, 72, 74, - 74, 72, 72, 72, 72, 73, 73, 74, 73, 78, 75, 74, 74, 73, 73, 73, 73, 75, - 73, 71, 71, 71, 71, 71, 71, 72, 72, 77, 73, 72, 72, 71, 71, 71, 71, 73, - 73, 71, 72, 72, 72, 72, 72, 73, 73, 77, 74, 73, 73, 72, 72, 72, 72, 74, - 73, 71, 71, 71, 71, 72, 72, 73, 72, 77, 75, 72, 73, 72, 72, 72, 72, 74, - 74, 72, 73, 72, 72, 74, 73, 74, 73, 78, 75, 74, 74, 73, 73, 73, 73, 75, - 72, 71, 71, 71, 71, 72, 71, 72, 71, 76, 74, 72, 72, 72, 71, 71, 71, 74, - 73, 71, 72, 71, 72, 73, 72, 74, 72, 77, 74, 73, 73, 72, 72, 72, 72, 75, - 74, 72, 72, 72, 72, 74, 73, 75, 73, 76, 74, 73, 73, 73, 73, 73, 73, 76, - 73, 71, 71, 71, 71, 72, 72, 73, 72, 74, 73, 72, 72, 72, 72, 72, 72, 75, - 73, 71, 71, 71, 71, 72, 72, 74, 71, 73, 73, 72, 72, 72, 71, 71, 72, 74, - 73, 71, 71, 71, 71, 72, 72, 73, 71, 73, 72, 72, 72, 71, 71, 71, 72, 74, - 74, 71, 72, 72, 72, 73, 72, 74, 72, 74, 73, 72, 73, 72, 72, 72, 73, 75, - 72, 70, 70, 70, 70, 71, 71, 73, 71, 72, 72, 71, 71, 71, 71, 71, 71, 74, - 73, 71, 71, 71, 71, 72, 72, 74, 72, 73, 72, 72, 72, 72, 71, 72, 72, 75, - 73, 71, 71, 71, 71, 72, 72, 74, 71, 73, 72, 71, 72, 71, 71, 72, 72, 75, - 74, 71, 72, 72, 72, 73, 73, 75, 72, 74, 73, 72, 73, 73, 72, 73, 73, 76, - 71, 70, 69, 71, 71, 72, 73, 74, 71, 72, 72, 71, 72, 71, 71, 72, 72, 73, - 69, 70, 70, 71, 71, 72, 71, 72, 72, 71, 75, 73, 72, 71, 71, 72, 72, 70, + 71, 69, 69, 69, 68, 70, 10, 10, 10, 10, 10, 10, 69, 68, 68, 68, 68, 69, + 74, 70, 68, 68, 68, 68, 67, 67, 67, 68, 71, 71, 68, 69, 69, 69, 71, 76, + 73, 69, 68, 67, 67, 67, 66, 66, 66, 66, 69, 69, 67, 67, 68, 68, 68, 70, + 73, 69, 68, 68, 68, 68, 67, 67, 66, 67, 70, 69, 68, 68, 69, 69, 69, 71, + 72, 69, 68, 68, 67, 67, 66, 66, 66, 66, 69, 68, 68, 68, 68, 68, 68, 70, + 73, 69, 68, 68, 67, 67, 67, 66, 66, 67, 69, 69, 68, 68, 68, 69, 69, 71, + 71, 68, 67, 67, 66, 66, 66, 65, 65, 66, 68, 68, 68, 68, 68, 68, 68, 70, + 73, 69, 68, 68, 68, 67, 67, 67, 67, 67, 69, 68, 68, 68, 68, 68, 68, 70, + 72, 68, 67, 67, 67, 67, 67, 66, 66, 68, 70, 69, 69, 69, 69, 69, 69, 71, + 73, 70, 69, 69, 69, 68, 68, 68, 68, 70, 70, 69, 69, 69, 69, 69, 70, 72, + 72, 68, 68, 68, 67, 67, 67, 66, 66, 70, 69, 68, 68, 68, 68, 69, 69, 71, + 72, 69, 68, 68, 68, 67, 67, 67, 67, 71, 68, 68, 68, 68, 68, 68, 68, 71, + 72, 69, 68, 68, 68, 67, 67, 67, 66, 71, 68, 68, 68, 68, 68, 69, 69, 71, + 73, 70, 69, 69, 69, 69, 69, 69, 68, 74, 70, 70, 70, 70, 70, 70, 71, 73, + 71, 68, 68, 68, 67, 67, 67, 68, 66, 72, 68, 68, 68, 68, 68, 69, 69, 71, + 71, 69, 68, 68, 68, 68, 68, 68, 67, 73, 69, 69, 69, 69, 69, 69, 69, 72, + 72, 69, 69, 69, 69, 69, 69, 69, 68, 72, 68, 68, 68, 68, 68, 69, 69, 71, + 73, 70, 70, 70, 69, 69, 69, 69, 68, 73, 70, 69, 69, 69, 70, 70, 70, 73, + 70, 68, 68, 67, 67, 67, 67, 67, 66, 71, 68, 67, 67, 67, 68, 68, 68, 71, + 71, 68, 68, 68, 68, 68, 67, 68, 67, 72, 69, 68, 68, 68, 69, 69, 69, 72, + 71, 69, 68, 68, 68, 68, 68, 68, 67, 72, 69, 68, 68, 68, 69, 69, 69, 72, + 72, 70, 69, 69, 69, 69, 69, 69, 68, 72, 70, 69, 69, 69, 70, 70, 70, 73, + 70, 68, 68, 68, 67, 68, 67, 67, 66, 72, 69, 69, 69, 69, 69, 69, 69, 72, + 71, 68, 68, 68, 68, 68, 68, 68, 67, 71, 68, 68, 68, 69, 69, 69, 69, 72, + 71, 69, 69, 69, 68, 69, 69, 69, 67, 71, 68, 68, 68, 69, 69, 69, 70, 73, + 72, 70, 70, 69, 69, 69, 69, 70, 68, 71, 69, 69, 69, 70, 70, 70, 70, 74, + 70, 69, 68, 68, 68, 68, 68, 69, 67, 69, 67, 68, 68, 68, 69, 69, 69, 72, + 71, 69, 69, 69, 69, 69, 69, 70, 68, 69, 68, 69, 69, 69, 69, 70, 70, 74, + 71, 69, 68, 68, 68, 68, 69, 69, 67, 69, 68, 69, 69, 69, 70, 70, 70, 74, + 72, 70, 70, 70, 70, 70, 70, 70, 68, 69, 69, 69, 70, 70, 70, 71, 72, 75, + 71, 69, 69, 69, 69, 69, 69, 69, 67, 67, 67, 67, 68, 68, 69, 69, 70, 74, + 71, 69, 69, 69, 69, 69, 69, 69, 68, 69, 68, 68, 69, 69, 70, 70, 71, 75, + 71, 69, 69, 69, 69, 69, 69, 69, 67, 68, 68, 69, 69, 69, 70, 70, 71, 75, + 72, 70, 70, 70, 70, 70, 71, 71, 69, 70, 70, 70, 70, 71, 71, 72, 72, 76, + 73, 69, 69, 69, 69, 69, 71, 69, 67, 68, 68, 68, 69, 69, 69, 70, 71, 75, + 69, 68, 67, 66, 67, 66, 66, 66, 65, 66, 69, 70, 70, 70, 70, 70, 71, 71, #if TOUCH_KEY_NUM > 0 9, 9, 9, #endif /* #if TOUCH_KEY_NUM > 0 */ @@ -998,8 +1028,9 @@ static int32_t PS_Config_Lmt_FW_CC_Q_N[40 * 40] = { }; static int32_t PS_Config_Lmt_FW_Diff_P[40 * 40] = { - 50, 50, 50, 50, 50, 127, 127, 127, 127, 127, 127, 127, 127, 50, 50, 50, - 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, + 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, 50, @@ -1039,74 +1070,78 @@ static int32_t PS_Config_Lmt_FW_Diff_P[40 * 40] = { }; static int32_t PS_Config_Lmt_FW_Diff_N[40 * 40] = { - -50, -50, -50, -50, -50, -127, -127, -127, -127, -127, -127, -127, -127, - -50, -50, -50, -50, -50, - -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, - -50, -50, -50, -50, - -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, - -50, -50, -50, -50, - -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, - -50, -50, -50, -50, - -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, - -50, -50, -50, -50, - -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, - -50, -50, -50, -50, - -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, - -50, -50, -50, -50, - -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, - -50, -50, -50, -50, - -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, - -50, -50, -50, -50, - -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, - -50, -50, -50, -50, - -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, - -50, -50, -50, -50, - -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, - -50, -50, -50, -50, - -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, - -50, -50, -50, -50, - -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, - -50, -50, -50, -50, - -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, - -50, -50, -50, -50, - -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, - -50, -50, -50, -50, - -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, - -50, -50, -50, -50, - -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, - -50, -50, -50, -50, - -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, - -50, -50, -50, -50, - -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, - -50, -50, -50, -50, - -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, - -50, -50, -50, -50, - -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, - -50, -50, -50, -50, - -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, - -50, -50, -50, -50, - -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, - -50, -50, -50, -50, - -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, - -50, -50, -50, -50, - -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, - -50, -50, -50, -50, - -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, - -50, -50, -50, -50, - -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, - -50, -50, -50, -50, - -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, - -50, -50, -50, -50, - -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, - -50, -50, -50, -50, - -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, - -50, -50, -50, -50, - -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, - -50, -50, -50, -50, - -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, - -50, -50, -50, -50, - -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, - -50, -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, + -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, -50, + -50, -50, -50, #if TOUCH_KEY_NUM > 0 -35, -35, -35, #endif /* #if TOUCH_KEY_NUM > 0 */ diff --git a/drivers/input/touchscreen/xiaomi/xiaomi_touch.h b/drivers/input/touchscreen/xiaomi/xiaomi_touch.h index bbde0ab09fbf..cac2a39886df 100644 --- a/drivers/input/touchscreen/xiaomi/xiaomi_touch.h +++ b/drivers/input/touchscreen/xiaomi/xiaomi_touch.h @@ -46,7 +46,6 @@ enum MODE_TYPE { Touch_Panel_Orientation = 8, Touch_Report_Rate = 9, Touch_Mode_NUM = 10, - Touch_Resist_RF = 12, }; struct xiaomi_touch_interface { diff --git a/drivers/iommu/msm_dma_iommu_mapping.c b/drivers/iommu/msm_dma_iommu_mapping.c index 5095a2961e8b..05ed3117a093 100644 --- a/drivers/iommu/msm_dma_iommu_mapping.c +++ b/drivers/iommu/msm_dma_iommu_mapping.c @@ -11,130 +11,444 @@ * */ -#include -#include -#include +#include +#include #include +#include +#include +#include #include +#include + +/** + * struct msm_iommu_map - represents a mapping of an ion buffer to an iommu + * @lnode - list node to exist in the buffer's list of iommu mappings + * @dev - Device this is mapped to. Used as key + * @sgl - The scatterlist for this mapping + * @nents - Number of entries in sgl + * @dir - The direction for the map. + * @meta - Backpointer to the meta this guy belongs to. + * @ref - for reference counting this mapping + * @map_attrs - dma mapping attributes + * @buf_start_addr - address of start of buffer + * + * Represents a mapping of one dma_buf buffer to a particular device + * and address range. There may exist other mappings of this buffer in + * different devices. All mappings will have the same cacheability and security. + */ struct msm_iommu_map { + struct list_head lnode; + struct rb_node node; struct device *dev; - struct msm_iommu_data *data; - struct list_head data_node; - struct list_head dev_node; - struct scatterlist sg; + struct scatterlist *sgl; + unsigned int nents; enum dma_data_direction dir; - int nents; - int refcount; + struct msm_iommu_meta *meta; + struct kref ref; + unsigned long map_attrs; + dma_addr_t buf_start_addr; +}; + +struct msm_iommu_meta { + struct rb_node node; + struct list_head iommu_maps; + struct kref ref; + struct mutex lock; + void *buffer; }; -static struct msm_iommu_map *msm_iommu_map_lookup(struct msm_iommu_data *data, - struct device *dev) +static struct rb_root iommu_root; +static DEFINE_MUTEX(msm_iommu_map_mutex); + +static void msm_iommu_meta_add(struct msm_iommu_meta *meta) { - struct msm_iommu_map *map; + struct rb_root *root = &iommu_root; + struct rb_node **p = &root->rb_node; + struct rb_node *parent = NULL; + struct msm_iommu_meta *entry; + + while (*p) { + parent = *p; + entry = rb_entry(parent, struct msm_iommu_meta, node); - list_for_each_entry(map, &data->map_list, data_node) { - if (map->dev == dev) - return map; + if (meta->buffer < entry->buffer) + p = &(*p)->rb_left; + else if (meta->buffer > entry->buffer) + p = &(*p)->rb_right; + else + pr_err("%s: dma_buf %p already exists\n", __func__, + entry->buffer); + } + + rb_link_node(&meta->node, parent, p); + rb_insert_color(&meta->node, root); +} + +static struct msm_iommu_meta *msm_iommu_meta_lookup(void *buffer) +{ + struct rb_root *root = &iommu_root; + struct rb_node **p = &root->rb_node; + struct rb_node *parent = NULL; + struct msm_iommu_meta *entry = NULL; + + while (*p) { + parent = *p; + entry = rb_entry(parent, struct msm_iommu_meta, node); + + if (buffer < entry->buffer) + p = &(*p)->rb_left; + else if (buffer > entry->buffer) + p = &(*p)->rb_right; + else + return entry; } return NULL; } -static void msm_iommu_map_free(struct msm_iommu_map *map) +static void msm_iommu_add(struct msm_iommu_meta *meta, + struct msm_iommu_map *iommu) { - list_del(&map->data_node); - list_del(&map->dev_node); - dma_unmap_sg(map->dev, &map->sg, map->nents, map->dir); - kfree(map); + INIT_LIST_HEAD(&iommu->lnode); + list_add(&iommu->lnode, &meta->iommu_maps); } -int msm_dma_map_sg_attrs(struct device *dev, struct scatterlist *sg, int nents, - enum dma_data_direction dir, struct dma_buf *dmabuf, - unsigned long attrs) + +static struct msm_iommu_map *msm_iommu_lookup(struct msm_iommu_meta *meta, + struct device *dev) { - int not_lazy = (attrs & DMA_ATTR_NO_DELAYED_UNMAP); - struct msm_iommu_data *data = dmabuf->priv; - struct msm_iommu_map *map; - - mutex_lock(&dev->iommu_map_lock); - mutex_lock(&data->lock); - map = msm_iommu_map_lookup(data, dev); - if (map) { - map->refcount++; - sg->dma_address = map->sg.dma_address; - sg->dma_length = map->sg.dma_length; - if (is_device_dma_coherent(dev)) - dmb(ish); + struct msm_iommu_map *entry; + + list_for_each_entry(entry, &meta->iommu_maps, lnode) { + if (entry->dev == dev) + return entry; + } + + return NULL; +} + +static struct msm_iommu_meta *msm_iommu_meta_create(struct dma_buf *dma_buf) +{ + struct msm_iommu_meta *meta; + + meta = kzalloc(sizeof(*meta), GFP_KERNEL); + + if (!meta) + return ERR_PTR(-ENOMEM); + + INIT_LIST_HEAD(&meta->iommu_maps); + meta->buffer = dma_buf->priv; + kref_init(&meta->ref); + mutex_init(&meta->lock); + msm_iommu_meta_add(meta); + + return meta; +} + +static void msm_iommu_meta_put(struct msm_iommu_meta *meta); + +static struct scatterlist *clone_sgl(struct scatterlist *sg, int nents) +{ + struct scatterlist *next, *s; + int i; + struct sg_table table; + + if (sg_alloc_table(&table, nents, GFP_KERNEL)) + return NULL; + next = table.sgl; + for_each_sg(sg, s, nents, i) { + *next = *s; + next = sg_next(next); + } + return table.sgl; +} + +static inline int __msm_dma_map_sg(struct device *dev, struct scatterlist *sg, + int nents, enum dma_data_direction dir, + struct dma_buf *dma_buf, + unsigned long attrs) +{ + struct msm_iommu_map *iommu_map; + struct msm_iommu_meta *iommu_meta = NULL; + int ret = 0; + bool extra_meta_ref_taken = false; + int late_unmap = !(attrs & DMA_ATTR_NO_DELAYED_UNMAP); + + mutex_lock(&msm_iommu_map_mutex); + iommu_meta = msm_iommu_meta_lookup(dma_buf->priv); + + if (!iommu_meta) { + iommu_meta = msm_iommu_meta_create(dma_buf); + + if (IS_ERR(iommu_meta)) { + mutex_unlock(&msm_iommu_map_mutex); + ret = PTR_ERR(iommu_meta); + goto out; + } + if (late_unmap) { + kref_get(&iommu_meta->ref); + extra_meta_ref_taken = true; + } + } else { + kref_get(&iommu_meta->ref); + } + + mutex_unlock(&msm_iommu_map_mutex); + + mutex_lock(&iommu_meta->lock); + iommu_map = msm_iommu_lookup(iommu_meta, dev); + if (!iommu_map) { + iommu_map = kmalloc(sizeof(*iommu_map), GFP_KERNEL); + + if (!iommu_map) { + ret = -ENOMEM; + goto out_unlock; + } + + ret = dma_map_sg_attrs(dev, sg, nents, dir, attrs); + if (!ret) { + kfree(iommu_map); + goto out_unlock; + } + + iommu_map->sgl = clone_sgl(sg, nents); + if (!iommu_map->sgl) { + kfree(iommu_map); + ret = -ENOMEM; + goto out_unlock; + } + iommu_map->nents = nents; + iommu_map->dev = dev; + + kref_init(&iommu_map->ref); + if (late_unmap) + kref_get(&iommu_map->ref); + iommu_map->meta = iommu_meta; + iommu_map->dir = dir; + iommu_map->map_attrs = attrs; + iommu_map->buf_start_addr = sg_phys(sg); + msm_iommu_add(iommu_meta, iommu_map); + } else { - nents = dma_map_sg_attrs(dev, sg, nents, dir, attrs); - if (nents) { - map = kmalloc(sizeof(*map), GFP_KERNEL | __GFP_NOFAIL); - map->data = data; - map->dev = dev; - map->dir = dir; - map->nents = nents; - map->refcount = 2 - not_lazy; - map->sg.dma_address = sg->dma_address; - map->sg.dma_length = sg->dma_length; - list_add(&map->data_node, &data->map_list); - list_add(&map->dev_node, &dev->iommu_map_list); + if (nents == iommu_map->nents && + dir == iommu_map->dir && + attrs == iommu_map->map_attrs && + sg_phys(sg) == iommu_map->buf_start_addr) { + sg->dma_address = iommu_map->sgl->dma_address; + sg->dma_length = iommu_map->sgl->dma_length; + + kref_get(&iommu_map->ref); + if (is_device_dma_coherent(dev)) + /* + * Ensure all outstanding changes for coherent + * buffers are applied to the cache before any + * DMA occurs. + */ + dmb(ish); + ret = nents; + } else { + bool start_diff = (sg_phys(sg) != + iommu_map->buf_start_addr); + + dev_err(dev, "lazy map request differs:\n" + "req dir:%d, original dir:%d\n" + "req nents:%d, original nents:%d\n" + "req map attrs:%lu, original map attrs:%lu\n" + "req buffer start address differs:%d\n", + dir, iommu_map->dir, nents, + iommu_map->nents, attrs, iommu_map->map_attrs, + start_diff); + ret = -EINVAL; } } - mutex_unlock(&data->lock); - mutex_unlock(&dev->iommu_map_lock); + mutex_unlock(&iommu_meta->lock); + return ret; + +out_unlock: + mutex_unlock(&iommu_meta->lock); +out: + if (!IS_ERR(iommu_meta)) { + if (extra_meta_ref_taken) + msm_iommu_meta_put(iommu_meta); + msm_iommu_meta_put(iommu_meta); + } + return ret; - return nents; } -void msm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, - enum dma_data_direction dir, struct dma_buf *dmabuf) +/* + * We are not taking a reference to the dma_buf here. It is expected that + * clients hold reference to the dma_buf until they are done with mapping and + * unmapping. + */ +int msm_dma_map_sg_attrs(struct device *dev, struct scatterlist *sg, int nents, + enum dma_data_direction dir, struct dma_buf *dma_buf, + unsigned long attrs) { - struct msm_iommu_data *data = dmabuf->priv; - struct msm_iommu_map *map; - - mutex_lock(&dev->iommu_map_lock); - mutex_lock(&data->lock); - map = msm_iommu_map_lookup(data, dev); - if (map && !--map->refcount) - msm_iommu_map_free(map); - mutex_unlock(&data->lock); - mutex_unlock(&dev->iommu_map_lock); + int ret; + + if (IS_ERR_OR_NULL(dev)) { + pr_err("%s: dev pointer is invalid\n", __func__); + return -EINVAL; + } + + if (IS_ERR_OR_NULL(sg)) { + pr_err("%s: sg table pointer is invalid\n", __func__); + return -EINVAL; + } + + if (IS_ERR_OR_NULL(dma_buf)) { + pr_err("%s: dma_buf pointer is invalid\n", __func__); + return -EINVAL; + } + + ret = __msm_dma_map_sg(dev, sg, nents, dir, dma_buf, attrs); + + return ret; } +EXPORT_SYMBOL(msm_dma_map_sg_attrs); -void msm_dma_unmap_all_for_dev(struct device *dev) +static void msm_iommu_meta_destroy(struct kref *kref) { - struct msm_iommu_map *map, *tmp; + struct msm_iommu_meta *meta = container_of(kref, struct msm_iommu_meta, + ref); - mutex_lock(&dev->iommu_map_lock); - list_for_each_entry_safe(map, tmp, &dev->iommu_map_list, dev_node) { - struct msm_iommu_data *data = map->data; + if (!list_empty(&meta->iommu_maps)) { + WARN(1, "%s: DMA Buffer %p being destroyed with outstanding iommu mappins!\n", + __func__, meta->buffer); + } + rb_erase(&meta->node, &iommu_root); + kfree(meta); +} - mutex_lock(&data->lock); - msm_iommu_map_free(map); - mutex_unlock(&data->lock); +static void msm_iommu_meta_put(struct msm_iommu_meta *meta) +{ + /* + * Need to lock here to prevent race against map/unmap + */ + mutex_lock(&msm_iommu_map_mutex); + kref_put(&meta->ref, msm_iommu_meta_destroy); + mutex_unlock(&msm_iommu_map_mutex); +} + +static void msm_iommu_map_release(struct kref *kref) +{ + struct msm_iommu_map *map = container_of(kref, struct msm_iommu_map, + ref); + struct sg_table table; + + table.nents = table.orig_nents = map->nents; + table.sgl = map->sgl; + list_del(&map->lnode); + + dma_unmap_sg(map->dev, map->sgl, map->nents, map->dir); + sg_free_table(&table); + kfree(map); +} + +void msm_dma_unmap_sg(struct device *dev, struct scatterlist *sgl, int nents, + enum dma_data_direction dir, struct dma_buf *dma_buf) +{ + struct msm_iommu_map *iommu_map; + struct msm_iommu_meta *meta; + + mutex_lock(&msm_iommu_map_mutex); + meta = msm_iommu_meta_lookup(dma_buf->priv); + if (!meta) { + WARN(1, "%s: (%p) was never mapped\n", __func__, dma_buf); + mutex_unlock(&msm_iommu_map_mutex); + goto out; + + } + mutex_unlock(&msm_iommu_map_mutex); + + mutex_lock(&meta->lock); + iommu_map = msm_iommu_lookup(meta, dev); + + if (!iommu_map) { + WARN(1, "%s: (%p) was never mapped for device %p\n", __func__, + dma_buf, dev); + mutex_unlock(&meta->lock); + goto out; } - mutex_unlock(&dev->iommu_map_lock); + + if (dir != iommu_map->dir) + WARN(1, "%s: (%pK) dir:%d differs from original dir:%d\n", + __func__, dma_buf, dir, iommu_map->dir); + + kref_put(&iommu_map->ref, msm_iommu_map_release); + mutex_unlock(&meta->lock); + + msm_iommu_meta_put(meta); + +out: + return; } +EXPORT_SYMBOL(msm_dma_unmap_sg); -void msm_dma_buf_freed(struct msm_iommu_data *data) +int msm_dma_unmap_all_for_dev(struct device *dev) { - struct msm_iommu_map *map, *tmp; - int retry = 0; + int ret = 0; + struct msm_iommu_meta *meta; + struct rb_root *root; + struct rb_node *meta_node; - do { - mutex_lock(&data->lock); - list_for_each_entry_safe(map, tmp, &data->map_list, data_node) { - struct device *dev = map->dev; + mutex_lock(&msm_iommu_map_mutex); + root = &iommu_root; + meta_node = rb_first(root); + while (meta_node) { + struct msm_iommu_map *iommu_map; + struct msm_iommu_map *iommu_map_next; - if (!mutex_trylock(&dev->iommu_map_lock)) { - retry = 1; - break; - } + meta = rb_entry(meta_node, struct msm_iommu_meta, node); + mutex_lock(&meta->lock); + list_for_each_entry_safe(iommu_map, iommu_map_next, + &meta->iommu_maps, lnode) + if (iommu_map->dev == dev) + if (!kref_put(&iommu_map->ref, + msm_iommu_map_release)) + ret = -EINVAL; - msm_iommu_map_free(map); - mutex_unlock(&dev->iommu_map_lock); - } - mutex_unlock(&data->lock); - } while (retry--); + mutex_unlock(&meta->lock); + meta_node = rb_next(meta_node); + } + mutex_unlock(&msm_iommu_map_mutex); + + return ret; +} + +/* + * Only to be called by ION code when a buffer is freed + */ +void msm_dma_buf_freed(void *buffer) +{ + struct msm_iommu_map *iommu_map; + struct msm_iommu_map *iommu_map_next; + struct msm_iommu_meta *meta; + + mutex_lock(&msm_iommu_map_mutex); + meta = msm_iommu_meta_lookup(buffer); + if (!meta) { + /* Already unmapped (assuming no late unmapping) */ + mutex_unlock(&msm_iommu_map_mutex); + return; + } + mutex_unlock(&msm_iommu_map_mutex); + + mutex_lock(&meta->lock); + + list_for_each_entry_safe(iommu_map, iommu_map_next, &meta->iommu_maps, + lnode) + kref_put(&iommu_map->ref, msm_iommu_map_release); + + if (!list_empty(&meta->iommu_maps)) { + WARN(1, "%s: DMA buffer %p destroyed with outstanding iommu mappings\n", + __func__, meta->buffer); + } + + INIT_LIST_HEAD(&meta->iommu_maps); + mutex_unlock(&meta->lock); + + msm_iommu_meta_put(meta); } diff --git a/drivers/leds/leds-qpnp-haptics.c b/drivers/leds/leds-qpnp-haptics.c index 453df1399b28..23398c94f981 100644 --- a/drivers/leds/leds-qpnp-haptics.c +++ b/drivers/leds/leds-qpnp-haptics.c @@ -93,10 +93,6 @@ #define HAP_VMAX_SHIFT 1 #define HAP_VMAX_MIN_MV 116 #define HAP_VMAX_MAX_MV 3596 -#define HAP_VMAX_MAX_MV_STRONG 3596 -#define HAP_VMAX_MAX_MV_USER 500 -#define HAP_MIN_TIME_STRONG 100 -#define HAP_MIN_TIME_CALL 1000 #define HAP_ILIM_CFG_REG(chip) (chip->base + 0x52) #define HAP_ILIM_SEL_MASK BIT(0) @@ -362,15 +358,8 @@ struct hap_chip { bool lra_auto_mode; bool play_irq_en; bool auto_res_err_recovery_hw; - int vmax_override; - u32 vmax_mv_strong; - u32 vmax_mv_call; - u32 vmax_mv_user; - u32 min_time_strong; }; -struct hap_chip *gchip; - static int qpnp_haptics_parse_buffer_dt(struct hap_chip *chip); static int qpnp_haptics_parse_pwm_dt(struct hap_chip *chip); @@ -1326,34 +1315,6 @@ static int qpnp_haptics_auto_mode_config(struct hap_chip *chip, int time_ms) return 0; } -void set_vibrate(int val) -{ - int rc; - - if (val > gchip->max_play_time_ms) - return; - - mutex_lock(&gchip->param_lock); - rc = qpnp_haptics_auto_mode_config(gchip, val); - if (rc < 0) { - pr_err("Unable to do auto mode config\n"); - mutex_unlock(&gchip->param_lock); - return; - } - - gchip->play_time_ms = val; - mutex_unlock(&gchip->param_lock); - - hrtimer_cancel(&gchip->stop_timer); - if (is_sw_lra_auto_resonance_control(gchip)) - hrtimer_cancel(&gchip->auto_res_err_poll_timer); - cancel_work_sync(&gchip->haptics_work); - - atomic_set(&gchip->state, 1); - schedule_work(&gchip->haptics_work); - - } - static irqreturn_t qpnp_haptics_play_irq_handler(int irq, void *data) { struct hap_chip *chip = data; @@ -1508,7 +1469,7 @@ static ssize_t qpnp_haptics_store_duration(struct device *dev, { struct led_classdev *cdev = dev_get_drvdata(dev); struct hap_chip *chip = container_of(cdev, struct hap_chip, cdev); - u32 val, old_vmax_mv; + u32 val; int rc; rc = kstrtouint(buf, 0, &val); @@ -1522,22 +1483,6 @@ static ssize_t qpnp_haptics_store_duration(struct device *dev, if (val > chip->max_play_time_ms) return -EINVAL; - if (chip->vmax_override) { - old_vmax_mv = chip->vmax_mv; - if (val >= HAP_MIN_TIME_CALL) - chip->vmax_mv = chip->vmax_mv_call; - else if (val >= HAP_MIN_TIME_STRONG) - chip->vmax_mv = chip->vmax_mv_strong; - else - chip->vmax_mv = chip->vmax_mv_user; - - rc = qpnp_haptics_vmax_config(chip, chip->vmax_mv, false); - if (rc < 0) { - chip->vmax_mv = old_vmax_mv; - return rc; - } - } - mutex_lock(&chip->param_lock); rc = qpnp_haptics_auto_mode_config(chip, val); if (rc < 0) { @@ -1605,9 +1550,6 @@ static ssize_t qpnp_haptics_store_activate(struct device *dev, if (val != 0 && val != 1) return count; - if (chip->vmax_mv <= HAP_VMAX_MIN_MV && (val != 0)) - return count; - if (val) { hrtimer_cancel(&chip->stop_timer); if (is_sw_lra_auto_resonance_control(chip)) @@ -1926,9 +1868,6 @@ static ssize_t qpnp_haptics_store_vmax(struct device *dev, if (rc < 0) return rc; - if (chip->vmax_override) - return count; - old_vmax_mv = chip->vmax_mv; chip->vmax_mv = data; rc = qpnp_haptics_vmax_config(chip, chip->vmax_mv, false); @@ -1940,127 +1879,6 @@ static ssize_t qpnp_haptics_store_vmax(struct device *dev, return count; } - static ssize_t qpnp_haptics_show_vmax_mv_user(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct led_classdev *cdev = dev_get_drvdata(dev); - struct hap_chip *chip = container_of(cdev, struct hap_chip, cdev); - - return snprintf(buf, PAGE_SIZE, "%d\n", chip->vmax_mv_user); -} - - static ssize_t qpnp_haptics_store_vmax_mv_user(struct device *dev, - struct device_attribute *attr, const char *buf, size_t count) -{ - struct led_classdev *cdev = dev_get_drvdata(dev); - struct hap_chip *chip = container_of(cdev, struct hap_chip, cdev); - int data, rc, old_vmax_mv; - - rc = kstrtoint(buf, 10, &data); - if (rc < 0) - return rc; - - old_vmax_mv = chip->vmax_mv_user; - chip->vmax_mv_user = data; - rc = qpnp_haptics_vmax_config(chip, chip->vmax_mv_user, false); - if (rc < 0) { - chip->vmax_mv_user = old_vmax_mv; - return rc; - } - - return count; -} - - -static ssize_t qpnp_haptics_show_vmax_mv_strong(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct led_classdev *cdev = dev_get_drvdata(dev); - struct hap_chip *chip = container_of(cdev, struct hap_chip, cdev); - - return snprintf(buf, PAGE_SIZE, "%d\n", chip->vmax_mv_strong); -} - - static ssize_t qpnp_haptics_store_vmax_mv_strong(struct device *dev, - struct device_attribute *attr, const char *buf, size_t count) -{ - struct led_classdev *cdev = dev_get_drvdata(dev); - struct hap_chip *chip = container_of(cdev, struct hap_chip, cdev); - int data, rc, old_vmax_mv; - - rc = kstrtoint(buf, 10, &data); - if (rc < 0) - return rc; - - old_vmax_mv = chip->vmax_mv_strong; - chip->vmax_mv_strong = data; - rc = qpnp_haptics_vmax_config(chip, chip->vmax_mv_strong, false); - if (rc < 0) { - chip->vmax_mv_strong = old_vmax_mv; - return rc; - } - return count; -} - -static ssize_t qpnp_haptics_show_vmax_mv_call(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct led_classdev *cdev = dev_get_drvdata(dev); - struct hap_chip *chip = container_of(cdev, struct hap_chip, cdev); - - return snprintf(buf, PAGE_SIZE, "%d\n", chip->vmax_mv_call); -} - - static ssize_t qpnp_haptics_store_vmax_mv_call(struct device *dev, - struct device_attribute *attr, const char *buf, size_t count) -{ - struct led_classdev *cdev = dev_get_drvdata(dev); - struct hap_chip *chip = container_of(cdev, struct hap_chip, cdev); - int data, rc, old_vmax_mv; - - rc = kstrtoint(buf, 10, &data); - if (rc < 0) - return rc; - - old_vmax_mv = chip->vmax_mv_call; - chip->vmax_mv_call = data; - rc = qpnp_haptics_vmax_config(chip, chip->vmax_mv_call, false); - if (rc < 0) { - chip->vmax_mv_call = old_vmax_mv; - return rc; - } - - return count; -} - -static ssize_t qpnp_haptics_show_vmax_override(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct led_classdev *cdev = dev_get_drvdata(dev); - struct hap_chip *chip = container_of(cdev, struct hap_chip, cdev); - - return snprintf(buf, PAGE_SIZE, "%d\n", chip->vmax_override); -} - - static ssize_t qpnp_haptics_store_vmax_override(struct device *dev, - struct device_attribute *attr, const char *buf, size_t count) -{ - struct led_classdev *cdev = dev_get_drvdata(dev); - struct hap_chip *chip = container_of(cdev, struct hap_chip, cdev); - int data, rc; - - rc = kstrtoint(buf, 10, &data); - if (rc < 0) - return rc; - - if (data != 0 && data != 1) - return count; - - chip->vmax_override = !!data; - - return count; -} - static ssize_t qpnp_haptics_show_lra_auto_mode(struct device *dev, struct device_attribute *attr, char *buf) { @@ -2109,10 +1927,6 @@ static struct device_attribute qpnp_haptics_attrs[] = { __ATTR(wf_s_rep_count, 0664, qpnp_haptics_show_wf_s_rep_count, qpnp_haptics_store_wf_s_rep_count), __ATTR(vmax_mv, 0664, qpnp_haptics_show_vmax, qpnp_haptics_store_vmax), - __ATTR(vmax_override, 0664, qpnp_haptics_show_vmax_override, qpnp_haptics_store_vmax_override), - __ATTR(vmax_mv_user, 0664, qpnp_haptics_show_vmax_mv_user, qpnp_haptics_store_vmax_mv_user), - __ATTR(vmax_mv_strong, 0664, qpnp_haptics_show_vmax_mv_strong, qpnp_haptics_store_vmax_mv_strong), - __ATTR(vmax_mv_call, 0664, qpnp_haptics_show_vmax_mv_call, qpnp_haptics_store_vmax_mv_call), __ATTR(lra_auto_mode, 0664, qpnp_haptics_show_lra_auto_mode, qpnp_haptics_store_lra_auto_mode), }; @@ -2518,9 +2332,6 @@ static int qpnp_haptics_parse_dt(struct hap_chip *chip) return rc; } - chip->vmax_mv_call = HAP_VMAX_MAX_MV_STRONG; - chip->vmax_mv_strong = HAP_VMAX_MAX_MV_STRONG; - chip->vmax_mv_user = HAP_VMAX_MAX_MV_USER; chip->vmax_mv = HAP_VMAX_MAX_MV; rc = of_property_read_u32(node, "qcom,vmax-mv", &temp); if (!rc) { @@ -2804,8 +2615,6 @@ static int qpnp_haptics_probe(struct platform_device *pdev) pr_info("haptic probe succeed\n"); - gchip = chip; - return 0; sysfs_fail: diff --git a/drivers/md/dm.c b/drivers/md/dm.c index 1388bcb492a1..e96c32d49523 100644 --- a/drivers/md/dm.c +++ b/drivers/md/dm.c @@ -1464,7 +1464,6 @@ void dm_init_md_queue(struct mapped_device *md) * - must do so here (in alloc_dev callchain) before queue is used */ md->queue->queuedata = md; - md->queue->backing_dev_info->congested_data = md; } void dm_init_normal_md_queue(struct mapped_device *md) @@ -1475,8 +1474,8 @@ void dm_init_normal_md_queue(struct mapped_device *md) /* * Initialize aspects of queue that aren't relevant for blk-mq */ + md->queue->backing_dev_info->congested_data = md; md->queue->backing_dev_info->congested_fn = dm_any_congested; - blk_queue_bounce_limit(md->queue, BLK_BOUNCE_ANY); } diff --git a/drivers/media/platform/msm/camera/cam_core/cam_hw_mgr_intf.h b/drivers/media/platform/msm/camera/cam_core/cam_hw_mgr_intf.h index dda2e82b04f1..c48665f60d1c 100644 --- a/drivers/media/platform/msm/camera/cam_core/cam_hw_mgr_intf.h +++ b/drivers/media/platform/msm/camera/cam_core/cam_hw_mgr_intf.h @@ -259,7 +259,6 @@ struct cam_hw_reset_args { enum cam_hw_mgr_command { CAM_HW_MGR_CMD_INTERNAL, CAM_HW_MGR_CMD_DUMP_PF_INFO, - CAM_HW_MGR_CMD_GET_TIMESTAMP_TH, }; /** @@ -277,7 +276,6 @@ struct cam_hw_cmd_args { union { void *internal_args; struct cam_hw_dump_pf_args pf_args; - uint64_t irq_timestamps_th; } u; }; diff --git a/drivers/media/platform/msm/camera/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c b/drivers/media/platform/msm/camera/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c index 852f05dfe4d2..2f546c02b22f 100644 --- a/drivers/media/platform/msm/camera/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c +++ b/drivers/media/platform/msm/camera/cam_icp/icp_hw/icp_hw_mgr/cam_icp_hw_mgr.c @@ -4640,7 +4640,7 @@ static int cam_icp_mgr_create_wq(void) goto debugfs_create_failed; icp_hw_mgr.icp_pc_flag = true; - icp_hw_mgr.ipe_bps_pc_flag = false; + icp_hw_mgr.ipe_bps_pc_flag = true; for (i = 0; i < ICP_WORKQ_NUM_TASK; i++) icp_hw_mgr.msg_work->task.pool[i].payload = diff --git a/drivers/media/platform/msm/camera/cam_isp/cam_isp_context.c b/drivers/media/platform/msm/camera/cam_isp/cam_isp_context.c index 2204ecf2abff..98fe0801db53 100644 --- a/drivers/media/platform/msm/camera/cam_isp/cam_isp_context.c +++ b/drivers/media/platform/msm/camera/cam_isp/cam_isp_context.c @@ -361,16 +361,7 @@ static int __cam_isp_ctx_handle_buf_done_in_activated_state( trace_cam_buf_done("ISP", ctx, req); - ctx_isp->irq_delay_detect = 0; req_isp = (struct cam_isp_ctx_req *) req->req_priv; - if (ctx_isp->frame_id == 1) - ctx_isp->irq_timestamps = done->irq_mono_boot_time; - else if (done->irq_mono_boot_time - - ctx_isp->irq_timestamps > ctx_isp->irq_timestamps_th) - ctx_isp->irq_delay_detect = 1; - - ctx_isp->irq_timestamps = done->irq_mono_boot_time; - for (i = 0; i < done->num_handles; i++) { for (j = 0; j < req_isp->num_fence_map_out; j++) { if (done->resource_handle[i] == @@ -471,26 +462,6 @@ static int __cam_isp_ctx_handle_buf_done_in_activated_state( req->request_id, ctx_isp->active_req_cnt); } - if (ctx_isp->active_req_cnt && ctx_isp->irq_delay_detect) { - CAM_ERR(CAM_ISP, "isp req[%lld] IRQ buf done got delayed", - req->request_id); - req = list_first_entry(&ctx->active_req_list, - struct cam_ctx_request, list); - req_isp = (struct cam_isp_ctx_req *) req->req_priv; - - for (j = 0; j < req_isp->num_fence_map_out; j++) { - rc = cam_sync_signal(req_isp->fence_map_out[j].sync_id, - CAM_SYNC_STATE_SIGNALED_ERROR); - if (rc) - CAM_DBG(CAM_ISP, "Sync failed with rc = %d", - rc); - req_isp->fence_map_out[j].sync_id = -1; - } - list_del_init(&req->list); - list_add_tail(&req->list, &ctx->free_req_list); - ctx_isp->active_req_cnt--; - } - ctx_isp->irq_delay_detect = 0; end: __cam_isp_ctx_update_state_monitor_array(ctx_isp, CAM_ISP_STATE_CHANGE_TRIGGER_DONE, @@ -558,21 +529,12 @@ static void __cam_isp_ctx_send_sof_timestamp( static int __cam_isp_ctx_reg_upd_in_epoch_state( struct cam_isp_context *ctx_isp, void *evt_data) { - struct cam_isp_hw_reg_update_event_data *rup_event_data = evt_data; - if (ctx_isp->frame_id == 1) CAM_DBG(CAM_ISP, "Reg update for early PCR"); else CAM_WARN(CAM_ISP, "Unexpected reg update in activated substate:%d for frame_id:%lld", ctx_isp->substate_activated, ctx_isp->frame_id); - if (ctx_isp->frame_id == 1) - ctx_isp->irq_timestamps = rup_event_data->irq_mono_boot_time; - else if (rup_event_data->irq_mono_boot_time - - ctx_isp->irq_timestamps > ctx_isp->irq_timestamps_th) - ctx_isp->irq_delay_detect = 1; - - ctx_isp->irq_timestamps = rup_event_data->irq_mono_boot_time; return 0; } @@ -583,7 +545,6 @@ static int __cam_isp_ctx_reg_upd_in_activated_state( struct cam_ctx_request *req; struct cam_context *ctx = ctx_isp->base; struct cam_isp_ctx_req *req_isp; - struct cam_isp_hw_reg_update_event_data *rup_event_data = evt_data; if (list_empty(&ctx->wait_req_list)) { CAM_ERR(CAM_ISP, "Reg upd ack with no waiting request"); @@ -613,13 +574,6 @@ static int __cam_isp_ctx_reg_upd_in_activated_state( */ ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_EPOCH; CAM_DBG(CAM_ISP, "next substate %d", ctx_isp->substate_activated); - if (ctx_isp->frame_id == 1) - ctx_isp->irq_timestamps = rup_event_data->irq_mono_boot_time; - else if (rup_event_data->irq_mono_boot_time - - ctx_isp->irq_timestamps > ctx_isp->irq_timestamps_th) - ctx_isp->irq_delay_detect = 1; - - ctx_isp->irq_timestamps = rup_event_data->irq_mono_boot_time; end: return rc; @@ -729,12 +683,6 @@ static int __cam_isp_ctx_sof_in_activated_state( ctx_isp->frame_id++; ctx_isp->sof_timestamp_val = sof_event_data->timestamp; ctx_isp->boot_timestamp = sof_event_data->boot_time; - if (ctx_isp->frame_id == 1) - ctx_isp->irq_timestamps = sof_event_data->irq_mono_boot_time; - else if (sof_event_data->irq_mono_boot_time - - ctx_isp->irq_timestamps > ctx_isp->irq_timestamps_th) - ctx_isp->irq_delay_detect = 1; - ctx_isp->irq_timestamps = sof_event_data->irq_mono_boot_time; __cam_isp_ctx_update_state_monitor_array(ctx_isp, CAM_ISP_STATE_CHANGE_TRIGGER_SOF, req->request_id); CAM_DBG(CAM_ISP, "frame id: %lld time stamp:0x%llx", @@ -750,7 +698,6 @@ static int __cam_isp_ctx_reg_upd_in_sof(struct cam_isp_context *ctx_isp, struct cam_ctx_request *req = NULL; struct cam_isp_ctx_req *req_isp; struct cam_context *ctx = ctx_isp->base; - struct cam_isp_hw_reg_update_event_data *rup_event_data = evt_data; if (ctx->state != CAM_CTX_ACTIVATED && ctx_isp->frame_id > 1) { CAM_DBG(CAM_ISP, "invalid RUP"); @@ -777,12 +724,6 @@ static int __cam_isp_ctx_reg_upd_in_sof(struct cam_isp_context *ctx_isp, CAM_ISP_STATE_CHANGE_TRIGGER_REG_UPDATE, req->request_id); } - if (ctx_isp->frame_id == 1) - ctx_isp->irq_timestamps = rup_event_data->irq_mono_boot_time; - else if (rup_event_data->irq_mono_boot_time - - ctx_isp->irq_timestamps > ctx_isp->irq_timestamps_th) - ctx_isp->irq_delay_detect = 1; - ctx_isp->irq_timestamps = rup_event_data->irq_mono_boot_time; end: return rc; } @@ -794,7 +735,6 @@ static int __cam_isp_ctx_epoch_in_applied(struct cam_isp_context *ctx_isp, struct cam_isp_ctx_req *req_isp; struct cam_context *ctx = ctx_isp->base; uint64_t request_id = 0; - struct cam_isp_hw_epoch_event_data *epoch_hw_event_data = evt_data; if (list_empty(&ctx->wait_req_list)) { /* @@ -863,13 +803,6 @@ static int __cam_isp_ctx_epoch_in_applied(struct cam_isp_context *ctx_isp, __cam_isp_ctx_update_state_monitor_array(ctx_isp, CAM_ISP_STATE_CHANGE_TRIGGER_EPOCH, request_id); } - if (ctx_isp->frame_id == 1) - ctx_isp->irq_timestamps = - epoch_hw_event_data->irq_mono_boot_time; - else if (epoch_hw_event_data->irq_mono_boot_time - - ctx_isp->irq_timestamps > ctx_isp->irq_timestamps_th) - ctx_isp->irq_delay_detect = 1; - ctx_isp->irq_timestamps = epoch_hw_event_data->irq_mono_boot_time; return 0; } @@ -903,13 +836,6 @@ static int __cam_isp_ctx_sof_in_epoch(struct cam_isp_context *ctx_isp, ctx_isp->sof_timestamp_val = sof_event_data->timestamp; ctx_isp->boot_timestamp = sof_event_data->boot_time; - if (ctx_isp->frame_id == 1) - ctx_isp->irq_timestamps = sof_event_data->irq_mono_boot_time; - else if (sof_event_data->irq_mono_boot_time - - ctx_isp->irq_timestamps > ctx_isp->irq_timestamps_th) - ctx_isp->irq_delay_detect = 1; - ctx_isp->irq_timestamps = sof_event_data->irq_mono_boot_time; - if (list_empty(&ctx->active_req_list)) ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_SOF; else @@ -1679,15 +1605,6 @@ static int __cam_isp_ctx_rdi_only_sof_in_top_state( CAM_DBG(CAM_ISP, "next substate %d", ctx_isp->substate_activated); - - - if (ctx_isp->frame_id == 1) - ctx_isp->irq_timestamps = sof_event_data->irq_mono_boot_time; - else if (sof_event_data->irq_mono_boot_time - - ctx_isp->irq_timestamps > ctx_isp->irq_timestamps_th) - ctx_isp->irq_delay_detect = 1; - ctx_isp->irq_timestamps = sof_event_data->irq_mono_boot_time; - return rc; } @@ -1710,13 +1627,6 @@ static int __cam_isp_ctx_rdi_only_sof_in_applied_state( ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_BUBBLE_APPLIED; CAM_DBG(CAM_ISP, "next substate %d", ctx_isp->substate_activated); - if (ctx_isp->frame_id == 1) - ctx_isp->irq_timestamps = sof_event_data->irq_mono_boot_time; - else if (sof_event_data->irq_mono_boot_time - - ctx_isp->irq_timestamps > ctx_isp->irq_timestamps_th) - ctx_isp->irq_delay_detect = 1; - ctx_isp->irq_timestamps = sof_event_data->irq_mono_boot_time; - return 0; } @@ -1807,14 +1717,6 @@ static int __cam_isp_ctx_rdi_only_sof_in_bubble_applied( /* change the state to bubble, as reg update has not come */ ctx_isp->substate_activated = CAM_ISP_CTX_ACTIVATED_BUBBLE; - - if (ctx_isp->frame_id == 1) - ctx_isp->irq_timestamps = sof_event_data->irq_mono_boot_time; - else if (sof_event_data->irq_mono_boot_time - - ctx_isp->irq_timestamps > ctx_isp->irq_timestamps_th) - ctx_isp->irq_delay_detect = 1; - ctx_isp->irq_timestamps = sof_event_data->irq_mono_boot_time; - CAM_DBG(CAM_ISP, "next substate %d", ctx_isp->substate_activated); end: return 0; @@ -1888,12 +1790,6 @@ static int __cam_isp_ctx_rdi_only_sof_in_bubble_state( CAM_DBG(CAM_ISP, "next substate %d", ctx_isp->substate_activated); - if (ctx_isp->frame_id == 1) - ctx_isp->irq_timestamps = sof_event_data->irq_mono_boot_time; - else if (sof_event_data->irq_mono_boot_time - - ctx_isp->irq_timestamps > ctx_isp->irq_timestamps_th) - ctx_isp->irq_delay_detect = 1; - ctx_isp->irq_timestamps = sof_event_data->irq_mono_boot_time; return 0; } @@ -2533,7 +2429,6 @@ static int __cam_isp_ctx_start_dev_in_ready(struct cam_context *ctx, struct cam_isp_ctx_req *req_isp; struct cam_isp_context *ctx_isp = (struct cam_isp_context *) ctx->ctx_priv; - struct cam_hw_cmd_args hw_cmd_args; if (cmd->session_handle != ctx->session_hdl || cmd->dev_handle != ctx->dev_hdl) { @@ -2581,16 +2476,6 @@ static int __cam_isp_ctx_start_dev_in_ready(struct cam_context *ctx, * irq handling comes early */ ctx->state = CAM_CTX_ACTIVATED; - /* get the initial timer threashold */ - hw_cmd_args.ctxt_to_hw_map = ctx_isp->hw_ctx; - hw_cmd_args.cmd_type = CAM_HW_MGR_CMD_GET_TIMESTAMP_TH; - ctx->hw_mgr_intf->hw_cmd(ctx->hw_mgr_intf->hw_mgr_priv, - &hw_cmd_args); - if (!rc) { - ctx_isp->irq_timestamps_th = hw_cmd_args.u.irq_timestamps_th; - CAM_DBG(CAM_ISP, "strat_dev timestamp %llu", - ctx_isp->irq_timestamps_th); - } trace_cam_context_state("ISP", ctx); rc = ctx->hw_mgr_intf->hw_start(ctx->hw_mgr_intf->hw_mgr_priv, &start_isp); diff --git a/drivers/media/platform/msm/camera/cam_isp/cam_isp_context.h b/drivers/media/platform/msm/camera/cam_isp/cam_isp_context.h index 5c8519dd4826..f96e6bd8d756 100644 --- a/drivers/media/platform/msm/camera/cam_isp/cam_isp_context.h +++ b/drivers/media/platform/msm/camera/cam_isp/cam_isp_context.h @@ -186,9 +186,6 @@ struct cam_isp_context { struct cam_isp_context_state_monitor cam_isp_ctx_state_monitor[ CAM_ISP_CTX_STATE_MONITOR_MAX_ENTRIES]; bool rdi_only_context; - bool irq_delay_detect; - uint64_t irq_timestamps; - uint64_t irq_timestamps_th; }; /** diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c index b6370e1187b3..8d454cb64512 100644 --- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c +++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c @@ -32,7 +32,6 @@ #include "cam_common_util.h" #define CAM_IFE_HW_ENTRIES_MAX 20 -#define CAM_IFE_BUF_DONE_DELAY_TH 33000 #define TZ_SVC_SMMU_PROGRAM 0x15 #define TZ_SAFE_SYSCALL_ID 0x3 @@ -44,7 +43,7 @@ (CAM_ISP_PACKET_META_GENERIC_BLOB_COMMON + 1) #define CAM_ISP_GENERIC_BLOB_TYPE_MAX \ - (CAM_ISP_GENERIC_BLOB_TYPE_FPS_CONFIG + 1) + (CAM_ISP_GENERIC_BLOB_TYPE_BW_CONFIG + 1) static uint32_t blob_type_hw_cmd_map[CAM_ISP_GENERIC_BLOB_TYPE_MAX] = { CAM_ISP_HW_CMD_GET_HFR_UPDATE, @@ -1941,6 +1940,11 @@ static int cam_ife_mgr_pause_hw(struct cam_ife_hw_mgr_ctx *ctx) return cam_ife_mgr_bw_control(ctx, CAM_VFE_BW_CONTROL_EXCLUDE); } +static int cam_ife_mgr_resume_hw(struct cam_ife_hw_mgr_ctx *ctx) +{ + return cam_ife_mgr_bw_control(ctx, CAM_VFE_BW_CONTROL_INCLUDE); +} + /* entry function: stop_hw */ static int cam_ife_mgr_stop_hw(void *hw_mgr_priv, void *stop_hw_args) { @@ -2160,6 +2164,7 @@ static int cam_ife_mgr_restart_hw(void *start_hw_args) } CAM_DBG(CAM_ISP, "START CID SRC ... in ctx id:%d", ctx->ctx_index); + ctx->dual_ife_irq_mismatch_cnt = 0; /* Start IFE root node: do nothing */ CAM_DBG(CAM_ISP, "Exit...(success)"); return 0; @@ -2345,6 +2350,42 @@ static int cam_ife_mgr_write(void *hw_mgr_priv, void *write_args) return -EPERM; } +static int cam_ife_mgr_reset(void *hw_mgr_priv, void *hw_reset_args) +{ + struct cam_ife_hw_mgr *hw_mgr = hw_mgr_priv; + struct cam_hw_reset_args *reset_args = hw_reset_args; + struct cam_ife_hw_mgr_ctx *ctx; + struct cam_ife_hw_mgr_res *hw_mgr_res; + uint32_t i; + int rc = 0; + + if (!hw_mgr_priv || !hw_reset_args) { + CAM_ERR(CAM_ISP, "Invalid arguments"); + return -EINVAL; + } + + ctx = (struct cam_ife_hw_mgr_ctx *)reset_args->ctxt_to_hw_map; + if (!ctx || !ctx->ctx_in_use) { + CAM_ERR(CAM_ISP, "Invalid context is used"); + return -EPERM; + } + CAM_DBG(CAM_ISP, "reset csid and vfe hw"); + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_csid, + list) { + rc = cam_ife_hw_mgr_reset_csid_res(hw_mgr_res); + if (rc) { + CAM_ERR(CAM_ISP, "Failed RESET (%d) rc:%d", + hw_mgr_res->res_id, rc); + goto end; + } + } + + for (i = 0; i < ctx->num_base; i++) + rc = cam_ife_mgr_reset_vfe_hw(hw_mgr, ctx->base[i].idx); +end: + return rc; +} + static int cam_ife_mgr_release_hw(void *hw_mgr_priv, void *release_hw_args) { @@ -2379,6 +2420,7 @@ static int cam_ife_mgr_release_hw(void *hw_mgr_priv, memset(ctx->base, 0, sizeof(ctx->base)); /* release cdm handle */ + ctx->dual_ife_irq_mismatch_cnt = 0; cam_cdm_release(ctx->cdm_handle); /* clean context */ @@ -2497,18 +2539,6 @@ static int cam_isp_blob_hfr_update( return rc; } -static int cam_isp_blob_fps_update( - uint32_t blob_type, - struct cam_isp_generic_blob_info *blob_info, - struct cam_isp_fps_config *fps_config, - struct cam_hw_prepare_update_args *prepare) -{ - int rc = 0; - - CAM_DBG(CAM_ISP, "fps = %u", fps_config->fps); - g_ife_hw_mgr.debug_cfg.ife_timestamps_th = fps_config->fps; - return rc; -} static int cam_isp_blob_clock_update( uint32_t blob_type, struct cam_isp_generic_blob_info *blob_info, @@ -2714,15 +2744,6 @@ static int cam_isp_packet_generic_blob_handler(void *user_data, bw_config, sizeof(prepare_hw_data->bw_config[0])); prepare_hw_data->bw_config_valid[bw_config->usage_type] = true; - } - break; - case CAM_ISP_GENERIC_BLOB_TYPE_FPS_CONFIG: { - struct cam_isp_fps_config *fsp_config = - (struct cam_isp_fps_config *)blob_data; - rc = cam_isp_blob_fps_update(blob_type, blob_info, - fsp_config, prepare); - if (rc) - CAM_ERR(CAM_ISP, "FPS Update Failed"); } break; default: @@ -2876,11 +2897,6 @@ static int cam_ife_mgr_prepare_hw_update(void *hw_mgr_priv, return rc; } -static int cam_ife_mgr_resume_hw(struct cam_ife_hw_mgr_ctx *ctx) -{ - return cam_ife_mgr_bw_control(ctx, CAM_VFE_BW_CONTROL_INCLUDE); -} - static int cam_ife_mgr_sof_irq_debug( struct cam_ife_hw_mgr_ctx *ctx, uint32_t sof_irq_enable) @@ -2990,6 +3006,36 @@ static void cam_ife_mgr_print_io_bufs(struct cam_packet *packet, } } +static void cam_ife_mgr_ctx_irq_dump(struct cam_ife_hw_mgr_ctx *ctx) +{ + struct cam_ife_hw_mgr_res *hw_mgr_res; + struct cam_hw_intf *hw_intf; + struct cam_isp_hw_get_cmd_update cmd_update; + int i = 0; + + list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_src, list) { + if (hw_mgr_res->res_type == CAM_IFE_HW_MGR_RES_UNINIT) + continue; + for (i = 0; i < CAM_ISP_HW_SPLIT_MAX; i++) { + if (!hw_mgr_res->hw_res[i]) + continue; + switch (hw_mgr_res->hw_res[i]->res_id) { + case CAM_ISP_HW_VFE_IN_CAMIF: + hw_intf = hw_mgr_res->hw_res[i]->hw_intf; + cmd_update.res = hw_mgr_res->hw_res[i]; + cmd_update.cmd_type = + CAM_ISP_HW_CMD_GET_IRQ_REGISTER_DUMP; + hw_intf->hw_ops.process_cmd(hw_intf->hw_priv, + CAM_ISP_HW_CMD_GET_IRQ_REGISTER_DUMP, + &cmd_update, sizeof(cmd_update)); + break; + default: + break; + } + } + } +} + static int cam_ife_mgr_cmd(void *hw_mgr_priv, void *cmd_args) { int rc = 0; @@ -3047,10 +3093,6 @@ static int cam_ife_mgr_cmd(void *hw_mgr_priv, void *cmd_args) hw_cmd_args->u.pf_args.buf_info, hw_cmd_args->u.pf_args.mem_found); break; - case CAM_HW_MGR_CMD_GET_TIMESTAMP_TH: - hw_cmd_args->u.irq_timestamps_th = - g_ife_hw_mgr.debug_cfg.ife_timestamps_th; - break; default: CAM_ERR(CAM_ISP, "Invalid cmd"); } @@ -3558,8 +3600,6 @@ static int cam_ife_hw_mgr_handle_reg_update( break; if (!rup_status) { - rup_event_data.irq_mono_boot_time = - evt_payload->ts.time_usecs; ife_hwr_irq_rup_cb( ife_hwr_mgr_ctx->common.cb_priv, CAM_ISP_HW_EVENT_REG_UPDATE, @@ -3588,8 +3628,6 @@ static int cam_ife_hw_mgr_handle_reg_update( if (atomic_read(&ife_hwr_mgr_ctx->overflow_pending)) break; if (!rup_status) { - rup_event_data.irq_mono_boot_time = - evt_payload->ts.time_usecs; /* Send the Reg update hw event */ ife_hwr_irq_rup_cb( ife_hwr_mgr_ctx->common.cb_priv, @@ -3648,11 +3686,26 @@ static int cam_ife_hw_mgr_check_irq_for_dual_vfe( (event_cnt[core_idx1] && (event_cnt[core_idx1] - event_cnt[core_idx0] > 1))) { + if (ife_hw_mgr_ctx->dual_ife_irq_mismatch_cnt > 10) { + rc = -1; + return rc; + } + CAM_ERR_RATE_LIMIT(CAM_ISP, - "One of the VFE cound not generate hw event %d", + "One of the VFE could not generate hw event %d", hw_event_type); - rc = -1; - return rc; + if (event_cnt[core_idx0] >= 2) { + event_cnt[core_idx0]--; + ife_hw_mgr_ctx->dual_ife_irq_mismatch_cnt++; + } + if (event_cnt[core_idx1] >= 2) { + event_cnt[core_idx1]--; + ife_hw_mgr_ctx->dual_ife_irq_mismatch_cnt++; + } + + if (ife_hw_mgr_ctx->dual_ife_irq_mismatch_cnt == 1) + cam_ife_mgr_ctx_irq_dump(ife_hw_mgr_ctx); + rc = 0; } CAM_DBG(CAM_ISP, "Only one core_index has given hw event %d", @@ -3932,8 +3985,6 @@ static int cam_ife_hw_mgr_handle_sof( ife_hw_mgr_ctx, &sof_done_event_data.timestamp, &sof_done_event_data.boot_time); - sof_done_event_data.irq_mono_boot_time = - evt_payload->ts.time_usecs; ife_hw_irq_sof_cb( ife_hw_mgr_ctx->common.cb_priv, @@ -3956,8 +4007,6 @@ static int cam_ife_hw_mgr_handle_sof( ife_hw_mgr_ctx, &sof_done_event_data.timestamp, &sof_done_event_data.boot_time); - sof_done_event_data.irq_mono_boot_time = - evt_payload->ts.time_usecs; ife_hw_irq_sof_cb( ife_hw_mgr_ctx->common.cb_priv, @@ -4041,14 +4090,11 @@ static int cam_ife_hw_mgr_handle_eof_for_camif_hw_res( if (atomic_read( &ife_hwr_mgr_ctx->overflow_pending)) break; - if (!eof_status) { - eof_done_event_data.irq_mono_boot_time = - evt_payload->ts.time_usecs; + if (!eof_status) ife_hwr_irq_eof_cb( ife_hwr_mgr_ctx->common.cb_priv, CAM_ISP_HW_EVENT_EOF, &eof_done_event_data); - } } break; @@ -4091,14 +4137,11 @@ static int cam_ife_hw_mgr_handle_eof_for_camif_hw_res( if (atomic_read(&ife_hwr_mgr_ctx->overflow_pending)) break; - if (!rc) { - eof_done_event_data.irq_mono_boot_time = - evt_payload->ts.time_usecs; + if (!rc) ife_hwr_irq_eof_cb( ife_hwr_mgr_ctx->common.cb_priv, CAM_ISP_HW_EVENT_EOF, &eof_done_event_data); - } break; @@ -4198,8 +4241,6 @@ static int cam_ife_hw_mgr_handle_buf_done_for_hw_res( if (atomic_read(&ife_hwr_mgr_ctx->overflow_pending)) break; - buf_done_event_data.irq_mono_boot_time = - evt_payload->ts.time_usecs; /* Report for Successful buf_done event if any */ if (buf_done_event_data.num_handles > 0 && ife_hwr_irq_wm_done_cb) { @@ -4635,12 +4676,11 @@ int cam_ife_hw_mgr_init(struct cam_hw_mgr_intf *hw_mgr_intf, int *iommu_hdl) hw_mgr_intf->hw_prepare_update = cam_ife_mgr_prepare_hw_update; hw_mgr_intf->hw_config = cam_ife_mgr_config_hw; hw_mgr_intf->hw_cmd = cam_ife_mgr_cmd; + hw_mgr_intf->hw_reset = cam_ife_mgr_reset; if (iommu_hdl) *iommu_hdl = g_ife_hw_mgr.mgr_common.img_iommu_hdl; - g_ife_hw_mgr.debug_cfg.ife_timestamps_th = - CAM_IFE_BUF_DONE_DELAY_TH; cam_ife_hw_mgr_debug_register(); CAM_DBG(CAM_ISP, "Exit"); @@ -4666,4 +4706,3 @@ int cam_ife_hw_mgr_init(struct cam_hw_mgr_intf *hw_mgr_intf, int *iommu_hdl) g_ife_hw_mgr.mgr_common.img_iommu_hdl = -1; return rc; } - diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h index fa31d3aadcc1..b952bf13cc20 100644 --- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h +++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h @@ -92,7 +92,6 @@ struct cam_ife_hw_mgr_debug { uint64_t csid_debug; uint32_t enable_recovery; uint32_t camif_debug; - uint32_t ife_timestamps_th; }; /** diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h index 41c31e524312..1586216f2073 100644 --- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h +++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/include/cam_isp_hw_mgr_intf.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -131,7 +131,6 @@ struct cam_isp_prepare_hw_update_data { struct cam_isp_hw_sof_event_data { uint64_t timestamp; uint64_t boot_time; - uint64_t irq_mono_boot_time; }; /** @@ -143,7 +142,6 @@ struct cam_isp_hw_sof_event_data { */ struct cam_isp_hw_reg_update_event_data { uint64_t timestamp; - uint64_t irq_mono_boot_time; }; /** @@ -154,7 +152,6 @@ struct cam_isp_hw_reg_update_event_data { */ struct cam_isp_hw_epoch_event_data { uint64_t timestamp; - uint64_t irq_mono_boot_time; }; /** @@ -170,7 +167,6 @@ struct cam_isp_hw_done_event_data { uint32_t resource_handle[ CAM_NUM_OUT_PER_COMP_IRQ_MAX]; uint64_t timestamp; - uint64_t irq_mono_boot_time; }; /** @@ -181,7 +177,6 @@ struct cam_isp_hw_done_event_data { */ struct cam_isp_hw_eof_event_data { uint64_t timestamp; - uint64_t irq_mono_boot_time; }; /** @@ -202,7 +197,6 @@ enum cam_isp_hw_mgr_command { CAM_ISP_HW_MGR_CMD_PAUSE_HW, CAM_ISP_HW_MGR_CMD_RESUME_HW, CAM_ISP_HW_MGR_CMD_SOF_DEBUG, - CAM_ISP_HW_MGR_CMD_GET_TIMESTAMP_TH, CAM_ISP_HW_MGR_CMD_MAX, }; diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h index 69bc51f9caa4..2b814ac27d02 100644 --- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h +++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h @@ -31,7 +31,6 @@ struct cam_isp_timestamp { struct timeval mono_time; struct timeval vt_time; uint64_t ticks; - uint64_t time_usecs; }; /* @@ -98,7 +97,7 @@ enum cam_isp_hw_cmd_type { CAM_ISP_HW_CMD_GET_REG_DUMP, CAM_ISP_HW_CMD_SOF_IRQ_DEBUG, CAM_ISP_HW_CMD_SET_CAMIF_DEBUG, - CAM_ISP_HW_CMD_FPS_UPDATE, + CAM_ISP_HW_CMD_GET_IRQ_REGISTER_DUMP, CAM_ISP_HW_CMD_MAX, }; @@ -224,4 +223,3 @@ struct cam_isp_hw_dual_isp_update_args { struct cam_isp_dual_config *dual_cfg; }; #endif /* _CAM_ISP_HW_H_ */ - diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c index 7560c8b43378..fd4ef42be701 100644 --- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c +++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c @@ -426,8 +426,6 @@ void cam_isp_hw_get_timestamp(struct cam_isp_timestamp *time_stamp) get_monotonic_boottime(&ts); time_stamp->mono_time.tv_sec = ts.tv_sec; time_stamp->mono_time.tv_usec = ts.tv_nsec/1000; - time_stamp->time_usecs = ts.tv_sec * 1000000 + - time_stamp->mono_time.tv_usec; } static int cam_vfe_irq_top_half(uint32_t evt_id, @@ -710,6 +708,7 @@ int cam_vfe_process_cmd(void *hw_priv, uint32_t cmd_type, case CAM_ISP_HW_CMD_CLOCK_UPDATE: case CAM_ISP_HW_CMD_BW_UPDATE: case CAM_ISP_HW_CMD_BW_CONTROL: + case CAM_ISP_HW_CMD_GET_IRQ_REGISTER_DUMP: rc = core_info->vfe_top->hw_ops.process_cmd( core_info->vfe_top->top_priv, cmd_type, cmd_args, arg_size); @@ -833,4 +832,3 @@ int cam_vfe_core_deinit(struct cam_vfe_hw_core_info *core_info, return rc; } - diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.c b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.c index 3ffd0717a3c7..770dd3d4bfa5 100644 --- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.c +++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_camif_ver2.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -378,6 +378,40 @@ static int cam_vfe_camif_reg_dump( return rc; } +static int cam_vfe_camif_irq_reg_dump( + struct cam_isp_resource_node *camif_res) +{ + struct cam_vfe_mux_camif_data *camif_priv; + struct cam_vfe_soc_private *soc_private; + int rc = 0; + + if (!camif_res) { + CAM_ERR(CAM_ISP, "Error! Invalid input arguments\n"); + return -EINVAL; + } + + if ((camif_res->res_state == CAM_ISP_RESOURCE_STATE_RESERVED) || + (camif_res->res_state == CAM_ISP_RESOURCE_STATE_AVAILABLE)) { + CAM_ERR(CAM_ISP, "Error! Invalid state\n"); + return 0; + } + + camif_priv = (struct cam_vfe_mux_camif_data *)camif_res->res_priv; + soc_private = camif_priv->soc_info->soc_private; + + CAM_INFO(CAM_ISP, + "Core Id =%d Mask reg: offset 0x%x val 0x%x offset 0x%x val 0x%x", + camif_priv->hw_intf->hw_idx, + 0x5c, cam_io_r_mb(camif_priv->mem_base + 0x5c), + 0x60, cam_io_r_mb(camif_priv->mem_base + 0x60)); + CAM_INFO(CAM_ISP, + "Core Id =%d Status reg: offset 0x%x val 0x%x offset 0x%x val 0x%x", + camif_priv->hw_intf->hw_idx, + 0x6c, cam_io_r_mb(camif_priv->mem_base + 0x6c), + 0x70, cam_io_r_mb(camif_priv->mem_base + 0x70)); + return rc; +} + static int cam_vfe_camif_resource_stop( struct cam_isp_resource_node *camif_res) { @@ -465,6 +499,9 @@ static int cam_vfe_camif_process_cmd(struct cam_isp_resource_node *rsrc_node, (struct cam_vfe_mux_camif_data *)rsrc_node->res_priv; camif_priv->camif_debug = *((uint32_t *)cmd_args); break; + case CAM_ISP_HW_CMD_GET_IRQ_REGISTER_DUMP: + rc = cam_vfe_camif_irq_reg_dump(rsrc_node); + break; default: CAM_ERR(CAM_ISP, "unsupported process command:%d", cmd_type); @@ -574,6 +611,7 @@ static int cam_vfe_camif_handle_irq_bottom_half(void *handler_priv, ~(camif_priv->reg_data->error_irq_mask0); payload->irq_reg_val[CAM_IFE_IRQ_CAMIF_REG_STATUS1] &= ~(camif_priv->reg_data->error_irq_mask1); + cam_vfe_put_evt_payload(payload->core_info, &payload); } if (camif_priv->camif_debug & @@ -650,4 +688,3 @@ int cam_vfe_camif_ver2_deinit( return 0; } - diff --git a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c index dc4417ca709b..7ec11e8c5007 100644 --- a/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c +++ b/drivers/media/platform/msm/camera/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_top/cam_vfe_top_ver2.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -379,6 +379,19 @@ static int cam_vfe_top_mux_get_reg_update( return -EINVAL; } +static int cam_vfe_get_irq_register_dump( + struct cam_vfe_top_ver2_priv *top_priv, + void *cmd_args, uint32_t arg_size) +{ + struct cam_isp_hw_get_cmd_update *cmd_update = cmd_args; + + if (cmd_update->res->process_cmd) + cmd_update->res->process_cmd(cmd_update->res, + CAM_ISP_HW_CMD_GET_IRQ_REGISTER_DUMP, cmd_args, arg_size); + + return 0; +} + int cam_vfe_top_get_hw_caps(void *device_priv, void *get_hw_cap_args, uint32_t arg_size) { @@ -657,6 +670,10 @@ int cam_vfe_top_process_cmd(void *device_priv, uint32_t cmd_type, case CAM_ISP_HW_CMD_BW_CONTROL: rc = cam_vfe_top_bw_control(top_priv, cmd_args, arg_size); break; + case CAM_ISP_HW_CMD_GET_IRQ_REGISTER_DUMP: + rc = cam_vfe_get_irq_register_dump(top_priv, + cmd_args, arg_size); + break; default: rc = -EINVAL; CAM_ERR(CAM_ISP, "Error! Invalid cmd:%d", cmd_type); @@ -820,4 +837,3 @@ int cam_vfe_top_ver2_deinit(struct cam_vfe_top **vfe_top_ptr) return rc; } - diff --git a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c index f6f45190a5b9..b00486412ebd 100644 --- a/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c +++ b/drivers/media/platform/msm/camera/cam_jpeg/jpeg_hw/cam_jpeg_hw_mgr.c @@ -1513,8 +1513,8 @@ int cam_jpeg_hw_mgr_init(struct device_node *of_node, uint64_t *hw_mgr_hdl, int *iommu_hdl) { int i, rc; - uint32_t num_dev = 0; - uint32_t num_dma_dev = 0; + uint32_t num_dev; + uint32_t num_dma_dev; struct cam_hw_mgr_intf *hw_mgr_intf; struct cam_iommu_handle cdm_handles; diff --git a/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.c b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.c index bda54a7b089a..84d3292b5a7c 100644 --- a/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.c +++ b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2016-2018,2019, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -49,7 +49,6 @@ static void cam_req_mgr_core_link_reset(struct cam_req_mgr_core_link *link) link->sync_link_sof_skip = false; link->open_req_cnt = 0; link->last_flush_id = 0; - link->num_sof_src = 0; } void cam_req_mgr_handle_core_shutdown(void) @@ -2111,8 +2110,6 @@ static int cam_req_mgr_cb_notify_trigger( struct cam_req_mgr_core_link *link = NULL; struct cam_req_mgr_trigger_notify *notify_trigger; struct crm_task_payload *task_data; - bool send_sof = true; - int i = 0; if (!trigger_data) { CAM_ERR(CAM_CRM, "sof_data is NULL"); @@ -2127,24 +2124,6 @@ static int cam_req_mgr_cb_notify_trigger( rc = -EINVAL; goto end; } - for (i = 0; i < link->num_sof_src; i++) { - if (link->dev_sof_evt[i].dev_hdl == trigger_data->dev_hdl) { - if (link->dev_sof_evt[i].sof_done == false) - link->dev_sof_evt[i].sof_done = true; - else - CAM_DBG(CAM_CRM, "Received Surious SOF"); - - } else if (link->dev_sof_evt[i].sof_done == false) { - send_sof = false; - } - - } - - if (!send_sof) - return 0; - - for (i = 0; i < link->num_sof_src; i++) - link->dev_sof_evt[i].sof_done = false; spin_lock_bh(&link->link_state_spin_lock); if (link->state < CAM_CRM_LINK_STATE_READY) { @@ -2257,12 +2236,6 @@ static int __cam_req_mgr_setup_link_info(struct cam_req_mgr_core_link *link, subscribe_event |= (uint32_t)dev->dev_info.trigger; } - if (dev->dev_info.dev_id == CAM_REQ_MGR_DEVICE_IFE) { - link->dev_sof_evt[link->num_sof_src].dev_hdl = - dev->dev_hdl; - link->dev_sof_evt[link->num_sof_src].sof_done = false; - link->num_sof_src++; - } } link->subscribe_event = subscribe_event; @@ -2955,4 +2928,3 @@ int cam_req_mgr_core_device_deinit(void) return 0; } - diff --git a/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.h b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.h index b7942db62b6d..fe2752cfcbec 100644 --- a/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.h +++ b/drivers/media/platform/msm/camera/cam_req_mgr/cam_req_mgr_core.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2016-2018,2019 The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -275,16 +275,6 @@ struct cam_req_mgr_connected_device { void *parent; }; -/* * - * struct cam_req_mgr_ife_sof_evt - * - Track SOF Events from IFE - * @ dev_hdl : device handle - * @ sof_done : tracks sof for individual IFE - */ -struct cam_req_mgr_dev_sof_evt { - int32_t dev_hdl; - bool sof_done; -}; /** * struct cam_req_mgr_core_link * - Link Properties @@ -347,8 +337,6 @@ struct cam_req_mgr_core_link { bool sync_link_sof_skip; int64_t sync_trigger_frame_id; int32_t open_req_cnt; - int32_t num_sof_src; - struct cam_req_mgr_dev_sof_evt dev_sof_evt[3]; uint32_t last_flush_id; atomic_t is_used; }; @@ -479,4 +467,3 @@ int cam_req_mgr_link_control(struct cam_req_mgr_link_control *control); #endif - diff --git a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_core.c b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_core.c index 79b1b6bbeb67..ef333345a477 100644 --- a/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_core.c +++ b/drivers/media/platform/msm/camera/cam_sensor_module/cam_sensor/cam_sensor_core.c @@ -1225,7 +1225,6 @@ int cam_sensor_apply_settings(struct cam_sensor_ctrl_t *s_ctrl, struct i2c_settings_list *i2c_list; if (req_id == 0) { - CAM_DBG(CAM_SENSOR,"[CDBG] opcode: %d", opcode); switch (opcode) { case CAM_SENSOR_PACKET_OPCODE_SENSOR_STREAMON: { i2c_set = &s_ctrl->i2c_data.streamon_settings; diff --git a/drivers/media/platform/msm/sde/rotator/sde_rotator_core.c b/drivers/media/platform/msm/sde/rotator/sde_rotator_core.c index 1779019dc60c..ca3b010c95c6 100644 --- a/drivers/media/platform/msm/sde/rotator/sde_rotator_core.c +++ b/drivers/media/platform/msm/sde/rotator/sde_rotator_core.c @@ -2842,7 +2842,7 @@ static int sde_rotator_get_dt_vreg_data(struct device *dev, mp->vreg_config[i].enable_load, mp->vreg_config[i].disable_load); } - return 0; + return rc; error: if (mp->vreg_config) { diff --git a/drivers/media/platform/msm/vidc/msm_vidc_clocks.c b/drivers/media/platform/msm/vidc/msm_vidc_clocks.c index c62cc4980b74..63a7d136bc01 100644 --- a/drivers/media/platform/msm/vidc/msm_vidc_clocks.c +++ b/drivers/media/platform/msm/vidc/msm_vidc_clocks.c @@ -1091,8 +1091,7 @@ int msm_vidc_decide_work_mode(struct msm_vidc_inst *inst) if (rc_mode == V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_VBR_VFR || rc_mode == V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_VBR_CFR || rc_mode == V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_MBR_CFR || - rc_mode == V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_MBR_VFR || - rc_mode == V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_OFF) + rc_mode == V4L2_CID_MPEG_VIDC_VIDEO_RATE_CONTROL_MBR_VFR) pdata.video_work_mode = VIDC_WORK_MODE_2; } else { return -EINVAL; diff --git a/drivers/media/platform/msm/vidc/msm_vidc_debug.c b/drivers/media/platform/msm/vidc/msm_vidc_debug.c index 7250a0662e6a..74fa3d554842 100644 --- a/drivers/media/platform/msm/vidc/msm_vidc_debug.c +++ b/drivers/media/platform/msm/vidc/msm_vidc_debug.c @@ -16,7 +16,7 @@ #include "msm_vidc_debug.h" #include "vidc_hfi_api.h" -int msm_vidc_debug = 0; +int msm_vidc_debug = VIDC_ERR | VIDC_WARN; EXPORT_SYMBOL(msm_vidc_debug); int msm_vidc_debug_out = VIDC_OUT_PRINTK; diff --git a/drivers/media/platform/msm/vidc_3x/hfi_response_handler.c b/drivers/media/platform/msm/vidc_3x/hfi_response_handler.c index 97220a85c305..74d995f3486d 100644 --- a/drivers/media/platform/msm/vidc_3x/hfi_response_handler.c +++ b/drivers/media/platform/msm/vidc_3x/hfi_response_handler.c @@ -1382,13 +1382,7 @@ static int hfi_process_session_prop_info(u32 device_id, cmd_done.status = VIDC_ERR_NONE; cmd_done.data.property.buf_req = buff_req; cmd_done.size = sizeof(buff_req); - - *info = (struct msm_vidc_cb_info) { - .response_type = HAL_SESSION_PROPERTY_INFO, - .response.cmd = cmd_done, - }; - - return 0; + break; case HFI_PROPERTY_PARAM_PROFILE_LEVEL_CURRENT: hfi_process_sess_get_prop_profile_level(pkt, &profile_level); cmd_done.device_id = device_id; @@ -1400,12 +1394,7 @@ static int hfi_process_session_prop_info(u32 device_id, .level = profile_level.level, }; cmd_done.size = sizeof(struct hal_profile_level); - - *info = (struct msm_vidc_cb_info) { - .response_type = HAL_SESSION_PROPERTY_INFO, - .response.cmd = cmd_done, - }; - return 0; + break; case HFI_PROPERTY_CONFIG_VDEC_ENTROPY: hfi_process_sess_get_prop_dec_entropy(pkt, &entropy); cmd_done.device_id = device_id; @@ -1413,18 +1402,19 @@ static int hfi_process_session_prop_info(u32 device_id, cmd_done.status = VIDC_ERR_NONE; cmd_done.data.property.h264_entropy = entropy; cmd_done.size = sizeof(enum hal_h264_entropy); - - *info = (struct msm_vidc_cb_info) { - .response_type = HAL_SESSION_PROPERTY_INFO, - .response.cmd = cmd_done, - }; - return 0; + break; default: dprintk(VIDC_DBG, "hal_process_session_prop_info: unknown_prop_id: %x\n", pkt->rg_property_data[0]); return -ENOTSUPP; } + *info = (struct msm_vidc_cb_info) { + .response_type = HAL_SESSION_PROPERTY_INFO, + .response.cmd = cmd_done, + }; + return 0; + } static int hfi_process_session_init_done(u32 device_id, @@ -1835,12 +1825,8 @@ static int hfi_process_session_rel_buf_done(u32 device_id, cmd_done.size = sizeof(struct msm_vidc_cb_cmd_done); cmd_done.session_id = (void *)(uintptr_t)pkt->session_id; cmd_done.status = hfi_map_err_status(pkt->error_type); - if (pkt->rg_buffer_info) { - cmd_done.data.buffer_info.buffer_addr = *pkt->rg_buffer_info; - cmd_done.size = sizeof(struct hal_buffer_info); - } else { - dprintk(VIDC_ERR, "invalid payload in rel_buff_done\n"); - } + cmd_done.data.buffer_info.buffer_addr = *pkt->rg_buffer_info; + cmd_done.size = sizeof(struct hal_buffer_info); *info = (struct msm_vidc_cb_info) { .response_type = HAL_SESSION_RELEASE_BUFFER_DONE, @@ -2110,4 +2096,3 @@ int hfi_process_msg_packet(u32 device_id, struct vidc_hal_msg_pkt_hdr *msg_hdr, return pkt_func ? pkt_func(device_id, (void *)msg_hdr, info) : -ENOTSUPP; } - diff --git a/drivers/misc/qseecom.c b/drivers/misc/qseecom.c index a0cac7526bd2..a64e44589c73 100644 --- a/drivers/misc/qseecom.c +++ b/drivers/misc/qseecom.c @@ -1,7 +1,7 @@ /* * QTI Secure Execution Environment Communicator (QSEECOM) driver * - * Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -146,6 +146,11 @@ enum qseecom_listener_unregister_kthread_state { LSNR_UNREG_KT_WAKEUP, }; +enum qseecom_unload_app_kthread_state { + UNLOAD_APP_KT_SLEEP = 0, + UNLOAD_APP_KT_WAKEUP, +}; + static struct class *driver_class; static dev_t qseecom_device_no; @@ -153,6 +158,7 @@ static DEFINE_MUTEX(qsee_bw_mutex); static DEFINE_MUTEX(app_access_lock); static DEFINE_MUTEX(clk_access_lock); static DEFINE_MUTEX(listener_access_lock); +static DEFINE_MUTEX(unload_app_pending_list_lock); struct sglist_info { @@ -307,6 +313,16 @@ struct qseecom_control { struct task_struct *unregister_lsnr_kthread_task; wait_queue_head_t unregister_lsnr_kthread_wq; atomic_t unregister_lsnr_kthread_state; + + struct list_head unload_app_pending_list_head; + struct task_struct *unload_app_kthread_task; + wait_queue_head_t unload_app_kthread_wq; + atomic_t unload_app_kthread_state; +}; + +struct qseecom_unload_app_pending_list { + struct list_head list; + struct qseecom_dev_handle *data; }; struct qseecom_sec_buf_fd_info { @@ -331,6 +347,8 @@ struct qseecom_client_handle { char app_name[MAX_APP_NAME_SIZE]; u32 app_arch; struct qseecom_sec_buf_fd_info sec_buf_fd[MAX_ION_FD]; + bool from_smcinvoke; + bool unload_pending; }; struct qseecom_listener_handle { @@ -408,6 +426,8 @@ static int qseecom_free_ce_info(struct qseecom_dev_handle *data, void __user *argp); static int qseecom_query_ce_info(struct qseecom_dev_handle *data, void __user *argp); +static int __qseecom_unload_app(struct qseecom_dev_handle *data, + uint32_t app_id); static int get_qseecom_keymaster_status(char *str) { @@ -1219,8 +1239,6 @@ static int qseecom_register_listener(struct qseecom_dev_handle *data, rcvd_lstnr.sb_size)) return -EFAULT; - data->listener.id = rcvd_lstnr.listener_id; - ptr_svc = __qseecom_find_svc(rcvd_lstnr.listener_id); if (ptr_svc) { if (ptr_svc->unregister_pending == false) { @@ -1233,7 +1251,7 @@ static int qseecom_register_listener(struct qseecom_dev_handle *data, pr_debug("register %d has to wait\n", rcvd_lstnr.listener_id); mutex_unlock(&listener_access_lock); - ret = wait_event_freezable( + ret = wait_event_interruptible( qseecom.register_lsnr_pending_wq, list_empty( &qseecom.unregister_lsnr_pending_list_head)); @@ -1268,7 +1286,8 @@ static int qseecom_register_listener(struct qseecom_dev_handle *data, new_entry->listener_in_use = false; list_add_tail(&new_entry->list, &qseecom.registered_listener_list_head); - pr_warn("Service %d is registered\n", rcvd_lstnr.listener_id); + data->listener.id = rcvd_lstnr.listener_id; + pr_debug("Service %d is registered\n", rcvd_lstnr.listener_id); return ret; } @@ -1308,7 +1327,7 @@ static int __qseecom_unregister_listener(struct qseecom_dev_handle *data, } while (atomic_read(&data->ioctl_count) > 1) { - if (wait_event_freezable(data->abort_wq, + if (wait_event_interruptible(data->abort_wq, atomic_read(&data->ioctl_count) <= 1)) { pr_err("Interrupted from abort\n"); ret = -ERESTARTSYS; @@ -1327,7 +1346,7 @@ static int __qseecom_unregister_listener(struct qseecom_dev_handle *data, kzfree(ptr_svc); data->released = true; - pr_warn("Service %d is unregistered\n", data->listener.id); + pr_debug("Service %d is unregistered\n", data->listener.id); return ret; } @@ -1336,6 +1355,11 @@ static int qseecom_unregister_listener(struct qseecom_dev_handle *data) struct qseecom_registered_listener_list *ptr_svc = NULL; struct qseecom_unregister_pending_list *entry = NULL; + if (data->released) { + pr_err("Don't unregister lsnr %d\n", data->listener.id); + return -EINVAL; + } + ptr_svc = __qseecom_find_svc(data->listener.id); if (!ptr_svc) { pr_err("Unregiser invalid listener ID %d\n", data->listener.id); @@ -1416,7 +1440,7 @@ static void __wakeup_unregister_listener_kthread(void) static int __qseecom_unregister_listener_kthread_func(void *data) { while (!kthread_should_stop()) { - wait_event_freezable( + wait_event_interruptible( qseecom.unregister_lsnr_kthread_wq, atomic_read(&qseecom.unregister_lsnr_kthread_state) == LSNR_UNREG_KT_WAKEUP); @@ -1496,20 +1520,17 @@ static int __qseecom_decrease_clk_ref_count(enum qseecom_ce_hw_instance ce) else qclk = &qseecom.ce_drv; - if (qclk->clk_access_cnt > 2) { + if (qclk->clk_access_cnt > 0) { + qclk->clk_access_cnt--; + } else { pr_err("Invalid clock ref count %d\n", qclk->clk_access_cnt); ret = -EINVAL; - goto err_dec_ref_cnt; } - if (qclk->clk_access_cnt == 2) - qclk->clk_access_cnt--; -err_dec_ref_cnt: mutex_unlock(&clk_access_lock); return ret; } - static int qseecom_scale_bus_bandwidth_timer(uint32_t mode) { int32_t ret = 0; @@ -1793,6 +1814,16 @@ static int __qseecom_process_incomplete_cmd(struct qseecom_dev_handle *data, if (ptr_svc->svc.listener_id == lstnr) { ptr_svc->listener_in_use = true; ptr_svc->rcv_req_flag = 1; + rc = msm_ion_do_cache_op(qseecom.ion_clnt, + ptr_svc->ihandle, + ptr_svc->sb_virt, + ptr_svc->sb_length, + ION_IOC_INV_CACHES); + if (rc) { + pr_err("cache opp failed %d\n", rc); + status = QSEOS_RESULT_FAILURE; + goto err_resp; + } wake_up_interruptible(&ptr_svc->rcv_req_wq); break; } @@ -1844,14 +1875,14 @@ static int __qseecom_process_incomplete_cmd(struct qseecom_dev_handle *data, * send_resp_flag. */ if (!qseecom.qsee_reentrancy_support && - !wait_event_freezable(qseecom.send_resp_wq, + !wait_event_interruptible(qseecom.send_resp_wq, __qseecom_listener_has_sent_rsp( data, ptr_svc))) { break; } if (qseecom.qsee_reentrancy_support && - !wait_event_freezable(qseecom.send_resp_wq, + !wait_event_interruptible(qseecom.send_resp_wq, __qseecom_reentrancy_listener_has_sent_rsp( data, ptr_svc))) { break; @@ -1952,6 +1983,7 @@ static int __qseecom_process_incomplete_cmd(struct qseecom_dev_handle *data, } qseecom.app_block_ref_cnt--; + wake_up_interruptible_all(&qseecom.app_block_wq); if (rc) return rc; @@ -1972,6 +2004,7 @@ static int __qseecom_process_reentrancy_blocked_on_listener( sigset_t old_sigset; unsigned long flags; bool found_app = false; + struct qseecom_registered_app_list dummy_app_entry = { {NULL} }; if (!resp || !data) { pr_err("invalid resp or data pointer\n"); @@ -1980,25 +2013,32 @@ static int __qseecom_process_reentrancy_blocked_on_listener( } /* find app_id & img_name from list */ - if (!ptr_app && data->client.app_arch != ELFCLASSNONE) { - spin_lock_irqsave(&qseecom.registered_app_list_lock, flags); - list_for_each_entry(ptr_app, &qseecom.registered_app_list_head, - list) { - if ((ptr_app->app_id == data->client.app_id) && - (!strcmp(ptr_app->app_name, + if (!ptr_app) { + if (data->client.from_smcinvoke) { + pr_debug("This request is from smcinvoke\n"); + ptr_app = &dummy_app_entry; + ptr_app->app_id = data->client.app_id; + } else { + spin_lock_irqsave(&qseecom.registered_app_list_lock, + flags); + list_for_each_entry(ptr_app, + &qseecom.registered_app_list_head, list) { + if ((ptr_app->app_id == data->client.app_id) && + (!strcmp(ptr_app->app_name, data->client.app_name))) { - found_app = true; - break; + found_app = true; + break; + } + } + spin_unlock_irqrestore( + &qseecom.registered_app_list_lock, flags); + if (!found_app) { + pr_err("app_id %d (%s) is not found\n", + data->client.app_id, + (char *)data->client.app_name); + ret = -ENOENT; + goto exit; } - } - spin_unlock_irqrestore(&qseecom.registered_app_list_lock, - flags); - if (!found_app) { - pr_err("app_id %d (%s) is not found\n", - data->client.app_id, - (char *)data->client.app_name); - ret = -ENOENT; - goto exit; } } @@ -2027,7 +2067,7 @@ static int __qseecom_process_reentrancy_blocked_on_listener( ptr_app->app_blocked = true; mutex_unlock(&listener_access_lock); mutex_unlock(&app_access_lock); - wait_event_freezable( + wait_event_interruptible( list_ptr->listener_block_app_wq, !list_ptr->listener_in_use); mutex_lock(&app_access_lock); @@ -2112,6 +2152,16 @@ static int __qseecom_reentrancy_process_incomplete_cmd( if (ptr_svc->svc.listener_id == lstnr) { ptr_svc->listener_in_use = true; ptr_svc->rcv_req_flag = 1; + rc = msm_ion_do_cache_op(qseecom.ion_clnt, + ptr_svc->ihandle, + ptr_svc->sb_virt, + ptr_svc->sb_length, + ION_IOC_INV_CACHES); + if (rc) { + pr_err("cache opp failed %d\n", rc); + status = QSEOS_RESULT_FAILURE; + goto err_resp; + } wake_up_interruptible(&ptr_svc->rcv_req_wq); break; } @@ -2160,7 +2210,7 @@ static int __qseecom_reentrancy_process_incomplete_cmd( mutex_unlock(&listener_access_lock); mutex_unlock(&app_access_lock); do { - if (!wait_event_freezable(qseecom.send_resp_wq, + if (!wait_event_interruptible(qseecom.send_resp_wq, __qseecom_reentrancy_listener_has_sent_rsp( data, ptr_svc))) { break; @@ -2296,23 +2346,15 @@ static int __qseecom_reentrancy_process_incomplete_cmd( */ static void __qseecom_reentrancy_check_if_no_app_blocked(uint32_t smc_id) { - sigset_t new_sigset, old_sigset; - if (qseecom.qsee_reentrancy_support > QSEE_REENTRANCY_PHASE_0 && qseecom.qsee_reentrancy_support < QSEE_REENTRANCY_PHASE_3 && IS_OWNER_TRUSTED_OS(TZ_SYSCALL_OWNER_ID(smc_id))) { /* thread sleep until this app unblocked */ while (qseecom.app_block_ref_cnt > 0) { - sigfillset(&new_sigset); - sigprocmask(SIG_SETMASK, &new_sigset, &old_sigset); mutex_unlock(&app_access_lock); - do { - if (!wait_event_freezable(qseecom.app_block_wq, - (qseecom.app_block_ref_cnt == 0))) - break; - } while (1); + wait_event_interruptible(qseecom.app_block_wq, + (!qseecom.app_block_ref_cnt)); mutex_lock(&app_access_lock); - sigprocmask(SIG_SETMASK, &old_sigset, NULL); } } } @@ -2325,23 +2367,15 @@ static void __qseecom_reentrancy_check_if_no_app_blocked(uint32_t smc_id) static void __qseecom_reentrancy_check_if_this_app_blocked( struct qseecom_registered_app_list *ptr_app) { - sigset_t new_sigset, old_sigset; - if (qseecom.qsee_reentrancy_support) { ptr_app->check_block++; while (ptr_app->app_blocked || qseecom.app_block_ref_cnt > 1) { /* thread sleep until this app unblocked */ - sigfillset(&new_sigset); - sigprocmask(SIG_SETMASK, &new_sigset, &old_sigset); mutex_unlock(&app_access_lock); - do { - if (!wait_event_freezable(qseecom.app_block_wq, - (!ptr_app->app_blocked && - qseecom.app_block_ref_cnt <= 1))) - break; - } while (1); + wait_event_interruptible(qseecom.app_block_wq, + (!ptr_app->app_blocked && + qseecom.app_block_ref_cnt <= 1)); mutex_lock(&app_access_lock); - sigprocmask(SIG_SETMASK, &old_sigset, NULL); } ptr_app->check_block--; } @@ -2570,8 +2604,11 @@ static int qseecom_load_app(struct qseecom_dev_handle *data, void __user *argp) if (resp.result == QSEOS_RESULT_INCOMPLETE) { ret = __qseecom_process_incomplete_cmd(data, &resp); if (ret) { - pr_err("process_incomplete_cmd failed err: %d\n", - ret); + /* TZ has created app_id, need to unload it */ + pr_err("incomp_cmd err %d, %d, unload %d %s\n", + ret, resp.result, resp.data, + load_img_req.img_name); + __qseecom_unload_app(data, resp.data); if (!IS_ERR_OR_NULL(ihandle)) ion_free(qseecom.ion_clnt, ihandle); ret = -EFAULT; @@ -2666,7 +2703,7 @@ static int __qseecom_cleanup_app(struct qseecom_dev_handle *data) if (qseecom.qsee_reentrancy_support) mutex_unlock(&app_access_lock); while (atomic_read(&data->ioctl_count) > 1) { - if (wait_event_freezable(data->abort_wq, + if (wait_event_interruptible(data->abort_wq, atomic_read(&data->ioctl_count) <= 1)) { pr_err("Interrupted from abort\n"); ret = -ERESTARTSYS; @@ -2691,18 +2728,61 @@ static int qseecom_unmap_ion_allocated_memory(struct qseecom_dev_handle *data) return ret; } +static int __qseecom_unload_app(struct qseecom_dev_handle *data, + uint32_t app_id) +{ + struct qseecom_unload_app_ireq req; + struct qseecom_command_scm_resp resp; + int ret = 0; + + /* Populate the structure for sending scm call to load image */ + req.qsee_cmd_id = QSEOS_APP_SHUTDOWN_COMMAND; + req.app_id = app_id; + + /* SCM_CALL to unload the app */ + ret = qseecom_scm_call(SCM_SVC_TZSCHEDULER, 1, &req, + sizeof(struct qseecom_unload_app_ireq), + &resp, sizeof(resp)); + if (ret) { + pr_err("scm_call to unload app (id = %d) failed\n", app_id); + return -EFAULT; + } + switch (resp.result) { + case QSEOS_RESULT_SUCCESS: + pr_warn("App (%d) is unloaded\n", app_id); + break; + case QSEOS_RESULT_INCOMPLETE: + ret = __qseecom_process_incomplete_cmd(data, &resp); + if (ret) + pr_err("unload app %d fail proc incom cmd: %d,%d,%d\n", + app_id, ret, resp.result, resp.data); + else + pr_warn("App (%d) is unloaded\n", app_id); + break; + case QSEOS_RESULT_FAILURE: + pr_err("app (%d) unload_failed!!\n", app_id); + ret = -EFAULT; + break; + default: + pr_err("unload app %d get unknown resp.result %d\n", + app_id, resp.result); + ret = -EFAULT; + break; + } + return ret; +} + static int qseecom_unload_app(struct qseecom_dev_handle *data, bool app_crash) { unsigned long flags; unsigned long flags1; int ret = 0; - struct qseecom_command_scm_resp resp; struct qseecom_registered_app_list *ptr_app = NULL; bool unload = false; bool found_app = false; bool found_dead_app = false; - bool scm_called = false; + bool doublecheck = false; if (!data) { pr_err("Invalid/uninitialized device handle\n"); @@ -2752,48 +2832,9 @@ static int qseecom_unload_app(struct qseecom_dev_handle *data, (char *)data->client.app_name); if (unload) { - struct qseecom_unload_app_ireq req; - /* Populate the structure for sending scm call to load image */ - req.qsee_cmd_id = QSEOS_APP_SHUTDOWN_COMMAND; - req.app_id = data->client.app_id; - - /* SCM_CALL to unload the app */ - ret = qseecom_scm_call(SCM_SVC_TZSCHEDULER, 1, &req, - sizeof(struct qseecom_unload_app_ireq), - &resp, sizeof(resp)); - scm_called = true; - if (ret) { - pr_err("scm_call to unload app (id = %d) failed\n", - req.app_id); - ret = -EFAULT; - goto scm_exit; - } else { - pr_warn("App id %d now unloaded\n", req.app_id); - } - if (resp.result == QSEOS_RESULT_FAILURE) { - pr_err("app (%d) unload_failed!!\n", - data->client.app_id); - ret = -EFAULT; - goto scm_exit; - } - if (resp.result == QSEOS_RESULT_SUCCESS) - pr_debug("App (%d) is unloaded!!\n", - data->client.app_id); - if (resp.result == QSEOS_RESULT_INCOMPLETE) { - ret = __qseecom_process_incomplete_cmd(data, &resp); - if (ret) { - pr_err("process_incomplete_cmd fail err: %d\n", - ret); - goto scm_exit; - } - } - } + ret = __qseecom_unload_app(data, data->client.app_id); -scm_exit: - if (scm_called) { /* double check if this app_entry still exists */ - bool doublecheck = false; - spin_lock_irqsave(&qseecom.registered_app_list_lock, flags1); list_for_each_entry(ptr_app, &qseecom.registered_app_list_head, list) { @@ -2813,6 +2854,7 @@ static int qseecom_unload_app(struct qseecom_dev_handle *data, found_app = false; } } + unload_exit: if (found_app) { spin_lock_irqsave(&qseecom.registered_app_list_lock, flags1); @@ -2841,6 +2883,100 @@ static int qseecom_unload_app(struct qseecom_dev_handle *data, return ret; } + +static int qseecom_prepare_unload_app(struct qseecom_dev_handle *data) +{ + struct qseecom_unload_app_pending_list *entry = NULL; + + pr_debug("prepare to unload app(%d)(%s), pending %d\n", + data->client.app_id, data->client.app_name, + data->client.unload_pending); + if (data->client.unload_pending) + return 0; + entry = kzalloc(sizeof(*entry), GFP_KERNEL); + if (!entry) + return -ENOMEM; + entry->data = data; + list_add_tail(&entry->list, + &qseecom.unload_app_pending_list_head); + data->client.unload_pending = true; + pr_debug("unload ta %d pending\n", data->client.app_id); + return 0; +} + +static void __wakeup_unload_app_kthread(void) +{ + atomic_set(&qseecom.unload_app_kthread_state, + UNLOAD_APP_KT_WAKEUP); + wake_up_interruptible(&qseecom.unload_app_kthread_wq); +} + +static bool __qseecom_find_pending_unload_app(uint32_t app_id, char *app_name) +{ + struct qseecom_unload_app_pending_list *entry = NULL; + bool found = false; + + mutex_lock(&unload_app_pending_list_lock); + list_for_each_entry(entry, &qseecom.unload_app_pending_list_head, + list) { + if ((entry->data->client.app_id == app_id) && + (!strcmp(entry->data->client.app_name, app_name))) { + found = true; + break; + } + } + mutex_unlock(&unload_app_pending_list_lock); + return found; +} + +static void __qseecom_processing_pending_unload_app(void) +{ + struct qseecom_unload_app_pending_list *entry = NULL; + struct list_head *pos; + int ret = 0; + + mutex_lock(&unload_app_pending_list_lock); + while (!list_empty(&qseecom.unload_app_pending_list_head)) { + pos = qseecom.unload_app_pending_list_head.next; + entry = list_entry(pos, + struct qseecom_unload_app_pending_list, list); + if (entry && entry->data) { + pr_debug("process pending unload app %d (%s)\n", + entry->data->client.app_id, + entry->data->client.app_name); + mutex_unlock(&unload_app_pending_list_lock); + mutex_lock(&app_access_lock); + ret = qseecom_unload_app(entry->data, true); + if (ret) + pr_err("unload app %d pending failed %d\n", + entry->data->client.app_id, ret); + mutex_unlock(&app_access_lock); + mutex_lock(&unload_app_pending_list_lock); + kzfree(entry->data); + } + list_del(pos); + kzfree(entry); + } + mutex_unlock(&unload_app_pending_list_lock); +} + +static int __qseecom_unload_app_kthread_func(void *data) +{ + while (!kthread_should_stop()) { + wait_event_interruptible( + qseecom.unload_app_kthread_wq, + atomic_read(&qseecom.unload_app_kthread_state) + == UNLOAD_APP_KT_WAKEUP); + pr_debug("kthread to unload app is called, state %d\n", + atomic_read(&qseecom.unload_app_kthread_state)); + __qseecom_processing_pending_unload_app(); + atomic_set(&qseecom.unload_app_kthread_state, + UNLOAD_APP_KT_SLEEP); + } + pr_warn("kthread to unload app stopped\n"); + return 0; +} + static phys_addr_t __qseecom_uvirt_to_kphys(struct qseecom_dev_handle *data, unsigned long virt) { @@ -3244,7 +3380,7 @@ int __qseecom_process_reentrancy(struct qseecom_command_scm_resp *resp, ret = __qseecom_reentrancy_process_incomplete_cmd(data, resp); ptr_app->app_blocked = false; qseecom.app_block_ref_cnt--; - wake_up_interruptible(&qseecom.app_block_wq); + wake_up_interruptible_all(&qseecom.app_block_wq); if (ret) pr_err("process_incomplete_cmd failed err: %d\n", ret); @@ -3293,6 +3429,13 @@ static int __qseecom_send_cmd(struct qseecom_dev_handle *data, return -ENOENT; } + if (__qseecom_find_pending_unload_app(data->client.app_id, + data->client.app_name)) { + pr_err("app %d (%s) unload is pending\n", + data->client.app_id, data->client.app_name); + return -ENOENT; + } + if (qseecom.qsee_version < QSEE_VERSION_40) { send_data_req.app_id = data->client.app_id; send_data_req.req_ptr = (uint32_t)(__qseecom_uvirt_to_kphys( @@ -3444,6 +3587,33 @@ int __boundary_checks_offset(struct qseecom_send_modfd_cmd_req *req, return 0; } +static int __boundary_checks_offset_64(struct qseecom_send_modfd_cmd_req *req, + struct qseecom_send_modfd_listener_resp *lstnr_resp, + struct qseecom_dev_handle *data, int i) +{ + + if ((data->type != QSEECOM_LISTENER_SERVICE) && + (req->ifd_data[i].fd > 0)) { + if ((req->cmd_req_len < sizeof(uint64_t)) || + (req->ifd_data[i].cmd_buf_offset > + req->cmd_req_len - sizeof(uint64_t))) { + pr_err("Invalid offset (req len) 0x%x\n", + req->ifd_data[i].cmd_buf_offset); + return -EINVAL; + } + } else if ((data->type == QSEECOM_LISTENER_SERVICE) && + (lstnr_resp->ifd_data[i].fd > 0)) { + if ((lstnr_resp->resp_len < sizeof(uint64_t)) || + (lstnr_resp->ifd_data[i].cmd_buf_offset > + lstnr_resp->resp_len - sizeof(uint64_t))) { + pr_err("Invalid offset (lstnr resp len) 0x%x\n", + lstnr_resp->ifd_data[i].cmd_buf_offset); + return -EINVAL; + } + } + return 0; +} + static int __qseecom_update_cmd_buf(void *msg, bool cleanup, struct qseecom_dev_handle *data) { @@ -3803,7 +3973,8 @@ static int __qseecom_update_cmd_buf_64(void *msg, bool cleanup, if (sg_ptr->nents == 1) { uint64_t *update_64bit; - if (__boundary_checks_offset(req, lstnr_resp, data, i)) + if (__boundary_checks_offset_64(req, lstnr_resp, + data, i)) goto err; /* 64bit app uses 64bit address */ update_64bit = (uint64_t *) field; @@ -4006,10 +4177,10 @@ static int qseecom_receive_req(struct qseecom_dev_handle *data) mutex_unlock(&listener_access_lock); while (1) { - if (wait_event_freezable(this_lstnr->rcv_req_wq, + if (wait_event_interruptible(this_lstnr->rcv_req_wq, __qseecom_listener_has_rcvd_req(data, this_lstnr))) { - pr_warn("Interrupted: exiting Listener Service = %d\n", + pr_debug("Interrupted: exiting Listener Service = %d\n", (uint32_t)data->listener.id); /* woken up for different reason */ return -ERESTARTSYS; @@ -4411,10 +4582,14 @@ static int __qseecom_load_fw(struct qseecom_dev_handle *data, char *appname, break; case QSEOS_RESULT_INCOMPLETE: ret = __qseecom_process_incomplete_cmd(data, &resp); - if (ret) - pr_err("process_incomplete_cmd FAILED\n"); - else + if (ret) { + pr_err("incomp_cmd err %d, %d, unload %d %s\n", + ret, resp.result, resp.data, appname); + __qseecom_unload_app(data, resp.data); + ret = -EFAULT; + } else { *app_id = resp.data; + } break; case QSEOS_RESULT_FAILURE: pr_err("scm call failed with response QSEOS_RESULT FAILURE\n"); @@ -4611,6 +4786,7 @@ int qseecom_start_app(struct qseecom_handle **handle, uint32_t app_id = 0; __wakeup_unregister_listener_kthread(); + __wakeup_unload_app_kthread(); if (atomic_read(&qseecom.qseecom_state) != QSEECOM_STATE_READY) { pr_err("Not allowed to be called in %d state\n", @@ -4751,6 +4927,7 @@ int qseecom_start_app(struct qseecom_handle **handle, spin_unlock_irqrestore(&qseecom.registered_kclient_list_lock, flags); mutex_unlock(&app_access_lock); + __wakeup_unload_app_kthread(); return 0; exit_ion_unmap_kernel: @@ -4771,6 +4948,7 @@ int qseecom_start_app(struct qseecom_handle **handle, kfree(*handle); *handle = NULL; } + __wakeup_unload_app_kthread(); return ret; } EXPORT_SYMBOL(qseecom_start_app); @@ -4785,6 +4963,7 @@ int qseecom_shutdown_app(struct qseecom_handle **handle) bool found_handle = false; __wakeup_unregister_listener_kthread(); + __wakeup_unload_app_kthread(); if (atomic_read(&qseecom.qseecom_state) != QSEECOM_STATE_READY) { pr_err("Not allowed to be called in %d state\n", @@ -4821,7 +5000,7 @@ int qseecom_shutdown_app(struct qseecom_handle **handle) kzfree(kclient); *handle = NULL; } - + __wakeup_unload_app_kthread(); return ret; } EXPORT_SYMBOL(qseecom_shutdown_app); @@ -4835,6 +5014,7 @@ int qseecom_send_command(struct qseecom_handle *handle, void *send_buf, bool perf_enabled = false; __wakeup_unregister_listener_kthread(); + __wakeup_unload_app_kthread(); if (atomic_read(&qseecom.qseecom_state) != QSEECOM_STATE_READY) { pr_err("Not allowed to be called in %d state\n", @@ -4883,8 +5063,10 @@ int qseecom_send_command(struct qseecom_handle *handle, void *send_buf, } perf_enabled = true; } - if (!strcmp(data->client.app_name, "securemm")) + if (!strcmp(data->client.app_name, "securemm") || + !strcmp(data->client.app_name, "bgapp")) { data->use_legacy_cmd = true; + } ret = __qseecom_send_cmd(data, &req); data->use_legacy_cmd = false; @@ -4959,6 +5141,7 @@ int qseecom_process_listener_from_smcinvoke(struct scm_desc *desc) resp.data = desc->ret[2]; /*listener_id*/ dummy_private_data.client.app_id = desc->ret[1]; + dummy_private_data.client.from_smcinvoke = true; dummy_app_entry.app_id = desc->ret[1]; mutex_lock(&app_access_lock); @@ -6798,6 +6981,12 @@ static int __qseecom_qteec_issue_cmd(struct qseecom_dev_handle *data, (char *)data->client.app_name); return -ENOENT; } + if (__qseecom_find_pending_unload_app(data->client.app_id, + data->client.app_name)) { + pr_err("app %d (%s) unload is pending\n", + data->client.app_id, data->client.app_name); + return -ENOENT; + } req->req_ptr = (void *)__qseecom_uvirt_to_kvirt(data, (uintptr_t)req->req_ptr); @@ -7001,6 +7190,12 @@ static int qseecom_qteec_invoke_modfd_cmd(struct qseecom_dev_handle *data, (char *)data->client.app_name); return -ENOENT; } + if (__qseecom_find_pending_unload_app(data->client.app_id, + data->client.app_name)) { + pr_err("app %d (%s) unload is pending\n", + data->client.app_id, data->client.app_name); + return -ENOENT; + } /* validate offsets */ for (i = 0; i < MAX_ION_FD; i++) { @@ -7153,6 +7348,7 @@ static long qseecom_ioctl(struct file *file, cmd != QSEECOM_IOCTL_SEND_MODFD_RESP && cmd != QSEECOM_IOCTL_SEND_MODFD_RESP_64) __wakeup_unregister_listener_kthread(); + __wakeup_unload_app_kthread(); switch (cmd) { case QSEECOM_IOCTL_REGISTER_LISTENER_REQ: { @@ -7405,6 +7601,7 @@ static long qseecom_ioctl(struct file *file, mutex_unlock(&app_access_lock); if (ret) pr_err("failed load_app request: %d\n", ret); + __wakeup_unload_app_kthread(); break; } case QSEECOM_IOCTL_UNLOAD_APP_REQ: { @@ -7423,6 +7620,7 @@ static long qseecom_ioctl(struct file *file, mutex_unlock(&app_access_lock); if (ret) pr_err("failed unload_app request: %d\n", ret); + __wakeup_unload_app_kthread(); break; } case QSEECOM_IOCTL_GET_QSEOS_VERSION_REQ: { @@ -7868,28 +8066,57 @@ static int qseecom_open(struct inode *inode, struct file *file) return ret; } +static void __qseecom_release_disable_clk(struct qseecom_dev_handle *data) +{ + if (qseecom.no_clock_support) + return; + if (qseecom.support_bus_scaling) { + mutex_lock(&qsee_bw_mutex); + if (data->mode != INACTIVE) { + qseecom_unregister_bus_bandwidth_needs(data); + if (qseecom.cumulative_mode == INACTIVE) + __qseecom_set_msm_bus_request(INACTIVE); + } + mutex_unlock(&qsee_bw_mutex); + } else { + if (data->fast_load_enabled) + qsee_disable_clock_vote(data, CLK_SFPB); + if (data->perf_enabled) + qsee_disable_clock_vote(data, CLK_DFAB); + } +} + static int qseecom_release(struct inode *inode, struct file *file) { struct qseecom_dev_handle *data = file->private_data; int ret = 0; bool free_private_data = true; - if (data->released == false) { + __qseecom_release_disable_clk(data); + if (!data->released) { pr_debug("data: released=false, type=%d, mode=%d, data=0x%pK\n", data->type, data->mode, data); switch (data->type) { case QSEECOM_LISTENER_SERVICE: pr_debug("release lsnr svc %d\n", data->listener.id); - free_private_data = false; mutex_lock(&listener_access_lock); ret = qseecom_unregister_listener(data); + if (!ret) + free_private_data = false; data->listener.release_called = true; mutex_unlock(&listener_access_lock); + __wakeup_unregister_listener_kthread(); break; case QSEECOM_CLIENT_APP: - mutex_lock(&app_access_lock); - ret = qseecom_unload_app(data, true); - mutex_unlock(&app_access_lock); + pr_debug("release app %d (%s)\n", + data->client.app_id, data->client.app_name); + if (data->client.app_id) { + free_private_data = false; + mutex_lock(&unload_app_pending_list_lock); + ret = qseecom_prepare_unload_app(data); + mutex_unlock(&unload_app_pending_list_lock); + __wakeup_unload_app_kthread(); + } break; case QSEECOM_SECURE_SERVICE: case QSEECOM_GENERIC: @@ -7906,24 +8133,6 @@ static int qseecom_release(struct inode *inode, struct file *file) } } - if (qseecom.support_bus_scaling) { - mutex_lock(&qsee_bw_mutex); - if (data->mode != INACTIVE) { - qseecom_unregister_bus_bandwidth_needs(data); - if (qseecom.cumulative_mode == INACTIVE) { - ret = __qseecom_set_msm_bus_request(INACTIVE); - if (ret) - pr_err("Fail to scale down bus\n"); - } - } - mutex_unlock(&qsee_bw_mutex); - } else { - if (data->fast_load_enabled == true) - qsee_disable_clock_vote(data, CLK_SFPB); - if (data->perf_enabled == true) - qsee_disable_clock_vote(data, CLK_DFAB); - } - if (free_private_data) kfree(data); return ret; @@ -8760,6 +8969,8 @@ static int qseecom_probe(struct platform_device *pdev) init_waitqueue_head(&qseecom.send_resp_wq); init_waitqueue_head(&qseecom.register_lsnr_pending_wq); init_waitqueue_head(&qseecom.unregister_lsnr_kthread_wq); + INIT_LIST_HEAD(&qseecom.unload_app_pending_list_head); + init_waitqueue_head(&qseecom.unload_app_kthread_wq); qseecom.send_resp_flag = 0; qseecom.qsee_version = QSEEE_VERSION_00; @@ -8975,9 +9186,25 @@ static int qseecom_probe(struct platform_device *pdev) } atomic_set(&qseecom.unregister_lsnr_kthread_state, LSNR_UNREG_KT_SLEEP); + + /*create a kthread to process pending ta unloading task */ + qseecom.unload_app_kthread_task = kthread_run( + __qseecom_unload_app_kthread_func, + NULL, "qseecom-unload-ta"); + if (IS_ERR(qseecom.unload_app_kthread_task)) { + pr_err("failed to create kthread to unload ta\n"); + rc = -EINVAL; + goto exit_kill_unreg_lsnr_kthread; + } + atomic_set(&qseecom.unload_app_kthread_state, + UNLOAD_APP_KT_SLEEP); + atomic_set(&qseecom.qseecom_state, QSEECOM_STATE_READY); return 0; +exit_kill_unreg_lsnr_kthread: + kthread_stop(qseecom.unregister_lsnr_kthread_task); + exit_deinit_clock: __qseecom_deinit_clk(CLK_QSEE); if ((qseecom.qsee.instance != qseecom.ce_drv.instance) && @@ -9091,6 +9318,8 @@ static int qseecom_remove(struct platform_device *pdev) ion_client_destroy(qseecom.ion_clnt); + kthread_stop(qseecom.unload_app_kthread_task); + kthread_stop(qseecom.unregister_lsnr_kthread_task); cdev_del(&qseecom.cdev); @@ -9259,4 +9488,3 @@ MODULE_DESCRIPTION("QTI Secure Execution Environment Communicator"); module_init(qseecom_init); module_exit(qseecom_exit); - diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c index ab11f2b469ca..9312a6eed963 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c @@ -71,7 +71,7 @@ static const unsigned freqs[] = { 400000, 300000, 200000, 100000 }; * performance cost, and for other reasons may not always be desired. * So we allow it it to be disabled. */ -bool use_spi_crc = 0; +bool use_spi_crc = 1; module_param(use_spi_crc, bool, 0644); static int mmc_schedule_delayed_work(struct delayed_work *work, diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c index 4b5f5e0ecb1d..d2c512671b78 100644 --- a/drivers/net/phy/micrel.c +++ b/drivers/net/phy/micrel.c @@ -28,9 +28,9 @@ #include #include #include +#include #include #include -#include /* Operation Mode Strap Override */ #define MII_KSZPHY_OMSO 0x16 @@ -1238,4 +1238,3 @@ static struct mdio_device_id __maybe_unused micrel_tbl[] = { }; MODULE_DEVICE_TABLE(mdio, micrel_tbl); - diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig index 02da745119cc..000a96a0379b 100644 --- a/drivers/of/Kconfig +++ b/drivers/of/Kconfig @@ -132,6 +132,7 @@ config OF_BATTERYDATA def_bool y help OpenFirmware BatteryData accessors + config OF_DMA_DEFAULT_COHERENT # arches should select this if DMA is coherent by default for OF devices bool diff --git a/drivers/pci/host/pci-msm.c b/drivers/pci/host/pci-msm.c index 34490d128d55..c0da01ff390c 100644 --- a/drivers/pci/host/pci-msm.c +++ b/drivers/pci/host/pci-msm.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2014-2020, The Linux Foundation. All rights reserved. +/* Copyright (c) 2014-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -517,6 +517,7 @@ struct msm_pcie_dev_t { struct platform_device *pdev; struct pci_dev *dev; struct regulator *gdsc; + struct regulator *vreg_pcie; struct regulator *gdsc_smmu; struct msm_pcie_vreg_info_t vreg[MSM_PCIE_MAX_VREG]; struct msm_pcie_gpio_info_t gpio[MSM_PCIE_MAX_GPIO]; @@ -3424,6 +3425,18 @@ static int msm_pcie_get_resources(struct msm_pcie_dev_t *dev, } } + dev->vreg_pcie = devm_regulator_get(&pdev->dev, "vreg-pcie"); + + if (IS_ERR(dev->vreg_pcie)) { + PCIE_ERR(dev, "PCIe: RC%d Failed to get %s VREG_PCIE:%ld\n", + dev->rc_idx, dev->pdev->name, PTR_ERR(dev->gdsc)); + if (PTR_ERR(dev->vreg_pcie) == -EPROBE_DEFER) + PCIE_DBG(dev, "PCIe: EPROBE_DEFER for %s VREG_PCIE\n", + dev->pdev->name); + ret = PTR_ERR(dev->vreg_pcie); + goto out; + } + dev->gdsc = devm_regulator_get(&pdev->dev, "gdsc-vdd"); if (IS_ERR(dev->gdsc)) { @@ -4289,6 +4302,19 @@ int msm_pcie_enumerate(u32 rc_idx) } if (!dev->enumerated) { + + /*Open the PCIE VCC before enable the pcie */ + if (dev->vreg_pcie) { + ret = regulator_enable(dev->vreg_pcie); + + if (ret) { + PCIE_ERR(dev, + "PCIe: fail to open vcc for RC%d (%s)\n", + dev->rc_idx, dev->pdev->name); + return ret; + } + } + ret = msm_pcie_enable(dev, PM_ALL); /* kick start ARM PCI configuration framework */ @@ -5522,7 +5548,7 @@ static void msm_pcie_config_link_pm_rc(struct msm_pcie_dev_t *dev, { bool child_l0s_enable = 0, child_l1_enable = 0, child_l1ss_enable = 0; - if (!pdev->subordinate || !(&pdev->subordinate->devices)) { + if (!pdev->subordinate || list_empty(&pdev->subordinate->devices)) { PCIE_DBG(dev, "PCIe: RC%d: no device connected to root complex\n", dev->rc_idx); @@ -6109,6 +6135,15 @@ static int msm_pcie_remove(struct platform_device *pdev) msm_pcie_gpio_deinit(&msm_pcie_dev[rc_idx]); msm_pcie_release_resources(&msm_pcie_dev[rc_idx]); + /*Close the PCIE VCC when remove the pcie*/ + if (msm_pcie_dev[rc_idx].vreg_pcie) { + ret = regulator_disable(msm_pcie_dev[rc_idx].vreg_pcie); + + if (ret) + pr_err("%s: PCIe: fail to close VCC.\n", __func__); + + } + out: mutex_unlock(&pcie_drv.drv_lock); diff --git a/drivers/platform/msm/ep_pcie/ep_pcie.c b/drivers/platform/msm/ep_pcie/ep_pcie.c index 0ac3d6d32b6d..ecff4c4e32be 100644 --- a/drivers/platform/msm/ep_pcie/ep_pcie.c +++ b/drivers/platform/msm/ep_pcie/ep_pcie.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2015, 2017-2019, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015, 2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -170,11 +170,10 @@ int ep_pcie_trigger_msi(struct ep_pcie_hw *phandle, u32 idx) } EXPORT_SYMBOL(ep_pcie_trigger_msi); -int ep_pcie_wakeup_host(struct ep_pcie_hw *phandle, - enum ep_pcie_event event) +int ep_pcie_wakeup_host(struct ep_pcie_hw *phandle) { if (phandle) - return phandle->wakeup_host(event); + return phandle->wakeup_host(); pr_err("ep_pcie:%s: the input driver handle is NULL.", __func__); diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_core.c b/drivers/platform/msm/ep_pcie/ep_pcie_core.c index 319f3eba0a7b..1478e8bda69f 100644 --- a/drivers/platform/msm/ep_pcie/ep_pcie_core.c +++ b/drivers/platform/msm/ep_pcie/ep_pcie_core.c @@ -557,6 +557,7 @@ static void ep_pcie_config_mmio(struct ep_pcie_dev_t *dev) ep_pcie_write_reg(dev->mmio, PCIE20_MHIVER, 0x1000000); ep_pcie_write_reg(dev->mmio, PCIE20_BHI_VERSION_LOWER, 0x2); ep_pcie_write_reg(dev->mmio, PCIE20_BHI_VERSION_UPPER, 0x1); + ep_pcie_write_reg(dev->mmio, PCIE20_BHI_INTVEC, 0xffffffff); dev->config_mmio_init = true; } @@ -614,7 +615,7 @@ static void ep_pcie_core_init(struct ep_pcie_dev_t *dev, bool configured) EP_PCIE_DBG2(dev, "PCIe V%d: Enable L1.\n", dev->rev); ep_pcie_write_mask(dev->parf + PCIE20_PARF_PM_CTRL, BIT(5), 0); - ep_pcie_write_reg(dev->parf + PCIE20_PARF_SLV_ADDR_MSB_CTRL, + ep_pcie_write_mask(dev->parf + PCIE20_PARF_SLV_ADDR_MSB_CTRL, 0, BIT(0)); ep_pcie_write_reg(dev->parf, PCIE20_PARF_SLV_ADDR_SPACE_SIZE_HI, 0x200); @@ -1973,10 +1974,6 @@ static irqreturn_t ep_pcie_handle_perst_irq(int irq, void *data) } out: - /* Set trigger type based on the next expected value of perst gpio */ - irq_set_irq_type(gpio_to_irq(dev->gpio[EP_PCIE_GPIO_PERST].num), - (perst ? IRQF_TRIGGER_LOW : IRQF_TRIGGER_HIGH)); - spin_unlock_irqrestore(&dev->isr_lock, irqsave_flags); return IRQ_HANDLED; @@ -2160,18 +2157,11 @@ int32_t ep_pcie_irq_init(struct ep_pcie_dev_t *dev) } perst_irq: - /* - * Check initial state of perst gpio to set the trigger type - * based on the next expected level of the gpio - */ - if (gpio_get_value(dev->gpio[EP_PCIE_GPIO_PERST].num) == 1) - dev->perst_deast = true; - /* register handler for PERST interrupt */ perst_irq = gpio_to_irq(dev->gpio[EP_PCIE_GPIO_PERST].num); ret = devm_request_irq(pdev, perst_irq, ep_pcie_handle_perst_irq, - (dev->perst_deast ? IRQF_TRIGGER_LOW : IRQF_TRIGGER_HIGH), + IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, "ep_pcie_perst", dev); if (ret) { EP_PCIE_ERR(dev, @@ -2515,37 +2505,10 @@ int ep_pcie_core_trigger_msi(u32 idx) return EP_PCIE_ERROR; } -static void ep_pcie_core_issue_inband_pme(void) -{ - struct ep_pcie_dev_t *dev = &ep_pcie_dev; - unsigned long irqsave_flags; - u32 pm_ctrl = 0; - - spin_lock_irqsave(&dev->isr_lock, irqsave_flags); - - EP_PCIE_DBG(dev, - "PCIe V%d: request to assert inband wake\n", - dev->rev); - - pm_ctrl = readl_relaxed(dev->parf + PCIE20_PARF_PM_CTRL); - ep_pcie_write_reg(dev->parf, PCIE20_PARF_PM_CTRL, - (pm_ctrl | BIT(4))); - ep_pcie_write_reg(dev->parf, PCIE20_PARF_PM_CTRL, pm_ctrl); - - EP_PCIE_DBG(dev, - "PCIe V%d: completed assert for inband wake\n", - dev->rev); - - spin_unlock_irqrestore(&dev->isr_lock, irqsave_flags); -} - -static int ep_pcie_core_wakeup_host(enum ep_pcie_event event) +int ep_pcie_core_wakeup_host(void) { struct ep_pcie_dev_t *dev = &ep_pcie_dev; - if (event == EP_PCIE_EVENT_PM_D3_HOT) - ep_pcie_core_issue_inband_pme(); - if (dev->perst_deast && !dev->l23_ready) { EP_PCIE_ERR(dev, "PCIe V%d: request to assert WAKE# when PERST is de-asserted and D3hot is not received.\n", diff --git a/drivers/platform/msm/ep_pcie/ep_pcie_dbg.c b/drivers/platform/msm/ep_pcie/ep_pcie_dbg.c index 9bf08e8101ba..a6ec33f4827c 100644 --- a/drivers/platform/msm/ep_pcie/ep_pcie_dbg.c +++ b/drivers/platform/msm/ep_pcie/ep_pcie_dbg.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2017, 2019 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -357,7 +357,7 @@ static ssize_t ep_pcie_cmd_debug(struct file *file, ep_pcie_config_outbound_iatu(phandle, entries, 2); break; case 13: /* wake up the host */ - ep_pcie_wakeup_host(phandle, EP_PCIE_EVENT_PM_D3_HOT); + ep_pcie_wakeup_host(phandle); break; case 14: /* Configure routing of doorbells */ ep_pcie_config_db_routing(phandle, chdb_cfg, erdb_cfg); diff --git a/drivers/platform/msm/ipa/ipa_clients/ipa_uc_offload.c b/drivers/platform/msm/ipa/ipa_clients/ipa_uc_offload.c index 793d13c003cf..b16cc0c64904 100644 --- a/drivers/platform/msm/ipa/ipa_clients/ipa_uc_offload.c +++ b/drivers/platform/msm/ipa/ipa_clients/ipa_uc_offload.c @@ -671,10 +671,9 @@ static int ipa_uc_ntn_disconn_pipes(struct ipa_uc_offload_ctx *ntn_ctx) ret); return -EFAULT; } - if (ntn_ctx->conn.dl.smmu_enabled) { + if (ntn_ctx->conn.dl.smmu_enabled) ipa_uc_ntn_free_conn_smmu_info(&ntn_ctx->conn.dl); ipa_uc_ntn_free_conn_smmu_info(&ntn_ctx->conn.ul); - } return ret; } diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c b/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c index f7cb81f10d42..3a7b25d38f4c 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_dp.c @@ -276,7 +276,7 @@ int ipa3_send(struct ipa3_sys_context *sys, struct ipa3_desc *desc, bool in_atomic) { - struct ipa3_tx_pkt_wrapper *tx_pkt, *tx_pkt_first = NULL; + struct ipa3_tx_pkt_wrapper *tx_pkt, *tx_pkt_first; struct ipahal_imm_cmd_pyld *tag_pyld_ret = NULL; struct ipa3_tx_pkt_wrapper *next_pkt; struct gsi_xfer_elem *gsi_xfer_elem_array = NULL; diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.c b/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.c index a7aecdb3643d..1d19e001e332 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_qmi_service.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2020, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -25,6 +25,8 @@ #include "ipa_qmi_service.h" +#include + #define IPA_Q6_SVC_VERS 1 #define IPA_A5_SVC_VERS 1 #define Q6_QMI_COMPLETION_TIMEOUT (60*HZ) @@ -606,6 +608,9 @@ static int ipa3_qmi_init_modem_send_sync_msg(void) &resp_desc, &resp, sizeof(resp), QMI_SEND_REQ_TIMEOUT_MS); pr_info("QMI_IPA_INIT_MODEM_DRIVER_REQ_V01 response received\n"); + + place_marker("M - QMI ready for commands"); + return ipa3_check_qmi_response(rc, QMI_IPA_INIT_MODEM_DRIVER_REQ_V01, resp.resp.result, resp.resp.error, "ipa_init_modem_driver_resp_msg_v01"); @@ -1670,4 +1675,3 @@ void ipa3_qmi_cleanup(void) mutex_destroy(&ipa3_qmi_lock); } - diff --git a/drivers/platform/msm/mhi_dev/mhi.c b/drivers/platform/msm/mhi_dev/mhi.c index bf43e257900e..42e3997c968a 100644 --- a/drivers/platform/msm/mhi_dev/mhi.c +++ b/drivers/platform/msm/mhi_dev/mhi.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2020, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -28,6 +28,7 @@ #include #include #include +#include #include "mhi.h" #include "mhi_hwio.h" @@ -44,7 +45,6 @@ #define MHI_RING_PRIMARY_EVT_ID 1 #define MHI_1K_SIZE 0x1000 /* Updated Specification for event start is NER - 2 and end - NER -1 */ -#define MHI_HW_ACC_EVT_RING_START 3 #define MHI_HW_ACC_EVT_RING_END 1 #define MHI_HOST_REGION_NUM 2 @@ -64,6 +64,10 @@ #define TR_RING_ELEMENT_SZ sizeof(struct mhi_dev_transfer_ring_element) #define RING_ELEMENT_TYPE_SZ sizeof(union mhi_dev_ring_element_type) +#define MHI_DEV_CH_CLOSE_TIMEOUT_MIN 5000 +#define MHI_DEV_CH_CLOSE_TIMEOUT_MAX 5100 +#define MHI_DEV_CH_CLOSE_TIMEOUT_COUNT 30 + uint32_t bhi_imgtxdb; enum mhi_msg_level mhi_msg_lvl = MHI_MSG_ERROR; enum mhi_msg_level mhi_ipc_msg_lvl = MHI_MSG_VERBOSE; @@ -306,7 +310,7 @@ static void mhi_dev_get_erdb_db_cfg(struct mhi_dev *mhi, break; default: erdb_cfg->base = mhi->cfg.event_rings - - MHI_HW_ACC_EVT_RING_START; + (mhi->cfg.hw_event_rings); erdb_cfg->end = mhi->cfg.event_rings - MHI_HW_ACC_EVT_RING_END; break; @@ -458,6 +462,8 @@ static void mhi_hwc_cb(void *priv, enum ipa_mhi_event_type event, } mhi_update_state_info(MHI_DEV_UEVENT_CTRL, MHI_STATE_CONNECTED); + mhi_log(MHI_MSG_CRITICAL, "Device in M0 State\n"); + place_marker("MHI - Device in M0 State\n"); if (!mhi_ctx->mhi_int) ep_pcie_mask_irq_event(mhi_ctx->phandle, @@ -496,17 +502,32 @@ static int mhi_hwc_chcmd(struct mhi_dev *mhi, uint chid, case MHI_DEV_RING_EL_START: connect_params.channel_id = chid; connect_params.sys.skip_ep_cfg = true; - if (chid == MHI_CLIENT_ADPL_IN) + + switch (chid) { + case MHI_CLIENT_ADPL_IN: connect_params.sys.client = IPA_CLIENT_MHI_DPL_CONS; - else if ((chid % 2) == 0x0) + break; + case MHI_CLIENT_IP_HW_0_OUT: connect_params.sys.client = IPA_CLIENT_MHI_PROD; - else + break; + case MHI_CLIENT_IP_HW_0_IN: connect_params.sys.client = IPA_CLIENT_MHI_CONS; + break; + case MHI_CLIENT_IP_HW_1_OUT: + connect_params.sys.client = IPA_CLIENT_MHI2_PROD; + break; + case MHI_CLIENT_IP_HW_1_IN: + connect_params.sys.client = IPA_CLIENT_MHI2_CONS; + break; + default: + pr_err("Invalid channel = 0x%X\n", chid); + return -EINVAL; + } rc = ipa_mhi_connect_pipe(&connect_params, &mhi->ipa_clnt_hndl[chid-HW_CHANNEL_BASE]); if (rc) - pr_err("HW Channel%d start failed 0x%X\n", + pr_err("HW Channel%d start failed : %d\n", chid, rc); break; case MHI_DEV_RING_EL_INVALID: @@ -899,7 +920,7 @@ static int mhi_dev_process_stop_cmd(struct mhi_dev_ring *ring, uint32_t ch_id, return 0; } else if (mhi->ch_ctx_cache[ch_id].ch_type == MHI_DEV_CH_TYPE_INBOUND_CHANNEL && - mhi->ch[ch_id].wr_request_active) { + (mhi->ch[ch_id].pend_wr_count > 0)) { mhi_log(MHI_MSG_INFO, "Pending inbound transaction\n"); return 0; } @@ -1439,9 +1460,23 @@ static void mhi_dev_transfer_completion_cb(void *mreq) rd_offset = req->rd_offset; ch->curr_ereq->context = ch; + if (mhi->ch_ctx_cache[ch->ch_id].ch_type == + MHI_DEV_CH_TYPE_INBOUND_CHANNEL) + ch->pend_wr_count--; + dma_unmap_single(&mhi_ctx->pdev->dev, req->dma, req->len, DMA_FROM_DEVICE); + /* + * Channel got closed with transfers pending + * Do not trigger callback or send cmpl to host + */ + if (ch->state == MHI_DEV_CH_CLOSED) { + mhi_log(MHI_MSG_DBG, "Ch %d closed with %d writes pending\n", + ch->ch_id, ch->pend_wr_count + 1); + return; + } + /* Trigger client call back */ req->client_cb(req); @@ -1995,25 +2030,61 @@ int mhi_dev_channel_isempty(struct mhi_dev_client *handle) } EXPORT_SYMBOL(mhi_dev_channel_isempty); -void mhi_dev_close_channel(struct mhi_dev_client *handle) +bool mhi_dev_channel_has_pending_write(struct mhi_dev_client *handle) { struct mhi_dev_channel *ch; if (!handle) { - mhi_log(MHI_MSG_ERROR, "Invalid channel access:%d\n", -ENODEV); - return; + mhi_log(MHI_MSG_ERROR, "Invalid channel access\n"); + return -EINVAL; } ch = handle->channel; + if (!ch) + return -EINVAL; + + return ch->pend_wr_count ? true : false; +} +EXPORT_SYMBOL(mhi_dev_channel_has_pending_write); + +int mhi_dev_close_channel(struct mhi_dev_client *handle) +{ + struct mhi_dev_channel *ch; + int count = 0; + int rc = 0; + + ch = handle->channel; + + do { + if (ch->pend_wr_count) { + usleep_range(MHI_DEV_CH_CLOSE_TIMEOUT_MIN, + MHI_DEV_CH_CLOSE_TIMEOUT_MAX); + } else + break; + } while (++count < MHI_DEV_CH_CLOSE_TIMEOUT_COUNT); mutex_lock(&ch->ch_lock); - if (ch->state != MHI_DEV_CH_PENDING_START) + if (ch->pend_wr_count) + mhi_log(MHI_MSG_ERROR, "%d writes pending for channel %d\n", + ch->pend_wr_count, ch->ch_id); + + if (ch->state != MHI_DEV_CH_PENDING_START) { if ((ch->ch_type == MHI_DEV_CH_TYPE_OUTBOUND_CHANNEL && - !mhi_dev_channel_isempty(handle)) || ch->tre_loc) + !mhi_dev_channel_isempty(handle)) || ch->tre_loc) { mhi_log(MHI_MSG_DBG, "Trying to close an active channel (%d)\n", ch->ch_id); + rc = -EAGAIN; + goto exit; + } else if (ch->tre_loc) { + mhi_log(MHI_MSG_ERROR, + "Trying to close channel (%d) when a TRE is active", + ch->ch_id); + rc = -EAGAIN; + goto exit; + } + } ch->state = MHI_DEV_CH_CLOSED; ch->active_client = NULL; @@ -2022,9 +2093,9 @@ void mhi_dev_close_channel(struct mhi_dev_client *handle) ch->ereqs = NULL; ch->tr_events = NULL; kfree(handle); - +exit: mutex_unlock(&ch->ch_lock); - return; + return rc; } EXPORT_SYMBOL(mhi_dev_close_channel); @@ -2218,6 +2289,7 @@ int mhi_dev_write_channel(struct mhi_req *wreq) size_t bytes_to_write = 0; size_t bytes_written = 0; uint32_t tre_len = 0, suspend_wait_timeout = 0; + bool async_wr_sched = false; if (!wreq || !wreq->client || !wreq->buf) { pr_err("%s: invalid parameters\n", __func__); @@ -2261,12 +2333,12 @@ int mhi_dev_write_channel(struct mhi_req *wreq) handle_client = wreq->client; ch = handle_client->channel; - ch->wr_request_active = true; ring = ch->ring; mutex_lock(&ch->ch_lock); + ch->pend_wr_count++; if (ch->state == MHI_DEV_CH_STOPPED) { mhi_log(MHI_MSG_ERROR, "channel %d already stopped\n", wreq->chan); @@ -2317,7 +2389,8 @@ int mhi_dev_write_channel(struct mhi_req *wreq) "Error while writing chan (%d) rc %d\n", wreq->chan, rc); goto exit; - } + } else if (wreq->mode == DMA_ASYNC) + async_wr_sched = true; bytes_written += bytes_to_write; usr_buf_remaining -= bytes_to_write; @@ -2357,7 +2430,8 @@ int mhi_dev_write_channel(struct mhi_req *wreq) } } exit: - ch->wr_request_active = false; + if (wreq->mode == DMA_SYNC || !async_wr_sched) + ch->pend_wr_count--; mutex_unlock(&ch->ch_lock); mutex_unlock(&mhi_ctx->mhi_write_test); return bytes_written; @@ -3201,4 +3275,3 @@ module_exit(mhi_dev_exit); MODULE_DESCRIPTION("MHI device driver"); MODULE_LICENSE("GPL v2"); - diff --git a/drivers/platform/msm/mhi_dev/mhi_sm.c b/drivers/platform/msm/mhi_dev/mhi_sm.c index 4a012e0c876c..4ec1c02e1111 100644 --- a/drivers/platform/msm/mhi_dev/mhi_sm.c +++ b/drivers/platform/msm/mhi_dev/mhi_sm.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -17,7 +17,6 @@ #include #include #include -#include #include "mhi_hwio.h" #include "mhi_sm.h" #include @@ -598,22 +597,15 @@ static int mhi_sm_change_to_M3(void) static int mhi_sm_wakeup_host(enum mhi_dev_event event) { int res = 0; - enum ep_pcie_event pcie_event; MHI_SM_FUNC_ENTRY(); if (mhi_sm_ctx->mhi_state == MHI_DEV_M3_STATE) { /* - * Check and send D3_HOT to enable waking up the host - * using inband PME. - */ - if (mhi_sm_ctx->d_state == MHI_SM_EP_PCIE_D3_HOT_STATE) - pcie_event = EP_PCIE_EVENT_PM_D3_HOT; - else - pcie_event = EP_PCIE_EVENT_PM_D3_COLD; - - res = ep_pcie_wakeup_host(mhi_sm_ctx->mhi_dev->phandle, - pcie_event); + * ep_pcie driver is responsible to send the right wakeup + * event, assert WAKE#, according to Link state + */ + res = ep_pcie_wakeup_host(mhi_sm_ctx->mhi_dev->phandle); if (res) { MHI_SM_ERR("Failed to wakeup MHI host, returned %d\n", res); diff --git a/drivers/platform/msm/mhi_dev/mhi_uci.c b/drivers/platform/msm/mhi_dev/mhi_uci.c index 4306d8bf74ad..e3221e356d42 100644 --- a/drivers/platform/msm/mhi_dev/mhi_uci.c +++ b/drivers/platform/msm/mhi_dev/mhi_uci.c @@ -38,6 +38,7 @@ #define MAX_NR_TRBS_PER_CHAN 9 #define MHI_QTI_IFACE_ID 4 #define MHI_ADPL_IFACE_ID 5 +#define MHI_CV2X_IFACE_ID 6 #define DEVICE_NAME "mhi" #define MAX_DEVICE_NAME_SIZE 80 @@ -46,6 +47,10 @@ #define MHI_UCI_AT_CTRL_READ_TIMEOUT msecs_to_jiffies(1000) #define MHI_UCI_WRITE_REQ_AVAIL_TIMEOUT msecs_to_jiffies(1000) +#define MHI_UCI_RELEASE_TIMEOUT_MIN 5000 +#define MHI_UCI_RELEASE_TIMEOUT_MAX 5100 +#define MHI_UCI_RELEASE_TIMEOUT_COUNT 30 + enum uci_dbg_level { UCI_DBG_VERBOSE = 0x0, UCI_DBG_INFO = 0x1, @@ -87,6 +92,8 @@ struct chan_attr { bool wr_cmpl; /* Uevent broadcast of channel state */ bool state_bcast; + /* Skip node creation if not needed */ + bool skip_node; /* Number of write request structs to allocate */ u32 num_wr_reqs; @@ -219,6 +226,29 @@ static const struct chan_attr uci_chan_attr_table[] = { NULL, true }, + { + MHI_CLIENT_DCI_OUT, + TRB_MAX_DATA_SIZE, + MAX_NR_TRBS_PER_CHAN, + MHI_DIR_OUT, + NULL, + NULL, + NULL, + false, + true + }, + { + MHI_CLIENT_DCI_IN, + TRB_MAX_DATA_SIZE, + MAX_NR_TRBS_PER_CHAN, + MHI_DIR_IN, + NULL, + NULL, + NULL, + false, + false, + true + }, { MHI_CLIENT_DUN_OUT, TRB_MAX_DATA_SIZE, @@ -237,6 +267,7 @@ static const struct chan_attr uci_chan_attr_table[] = { NULL, false, false, + false, 50 }, { @@ -372,43 +403,6 @@ static unsigned int mhi_uci_client_poll(struct file *file, poll_table *wait); static unsigned int mhi_uci_ctrl_poll(struct file *file, poll_table *wait); static struct mhi_uci_ctxt_t uci_ctxt; -static bool mhi_uci_are_channels_connected(struct uci_client *uci_client) -{ - uint32_t info_ch_in, info_ch_out; - int rc; - - /* - * Check channel states and return true only if channel - * information is available and in connected state. - * For all other failure conditions return false. - */ - rc = mhi_ctrl_state_info(uci_client->in_chan, &info_ch_in); - if (rc) { - uci_log(UCI_DBG_DBG, - "Channels %d is not available with %d\n", - uci_client->out_chan, rc); - return false; - } - - rc = mhi_ctrl_state_info(uci_client->out_chan, &info_ch_out); - if (rc) { - uci_log(UCI_DBG_DBG, - "Channels %d is not available with %d\n", - uci_client->out_chan, rc); - return false; - } - - if ((info_ch_in != MHI_STATE_CONNECTED) || - (info_ch_out != MHI_STATE_CONNECTED)) { - uci_log(UCI_DBG_DBG, - "Channels %d or %d are not connected\n", - uci_client->in_chan, uci_client->out_chan); - return false; - } - - return true; -} - static int mhi_init_read_chan(struct uci_client *client_handle, enum mhi_client_channel chan) { @@ -660,15 +654,6 @@ static unsigned int mhi_uci_client_poll(struct file *file, poll_table *wait) poll_wait(file, &uci_handle->read_wq, wait); poll_wait(file, &uci_handle->write_wq, wait); - /* - * Check if the channels on which the clients are trying - * to poll are in connected state and return with the - * appropriate mask if channels are disconnected. - */ - if (!mhi_uci_are_channels_connected(uci_handle)) { - mask = POLLHUP; - return mask; - } mask = uci_handle->at_ctrl_mask; if (!atomic_read(&uci_ctxt.mhi_disabled) && !mhi_dev_channel_isempty(uci_handle->in_handle)) { @@ -812,9 +797,6 @@ static int open_client_mhi_channels(struct uci_client *uci_client) { int rc = 0; - if (!mhi_uci_are_channels_connected(uci_client)) - return -ENODEV; - uci_log(UCI_DBG_DBG, "Starting channels %d %d.\n", uci_client->out_chan, @@ -929,39 +911,55 @@ static int mhi_uci_client_release(struct inode *mhi_inode, struct file *file_handle) { struct uci_client *uci_handle = file_handle->private_data; + int count = 0; if (!uci_handle) return -EINVAL; - if (atomic_sub_return(1, &uci_handle->ref_count) == 0) { - uci_log(UCI_DBG_DBG, - "Last client left, closing channel 0x%x\n", - iminor(mhi_inode)); - if (atomic_read(&uci_handle->mhi_chans_open)) { - atomic_set(&uci_handle->mhi_chans_open, 0); + if (atomic_sub_return(1, &uci_handle->ref_count)) { + uci_log(UCI_DBG_DBG, "Client close chan %d, ref count 0x%x\n", + iminor(mhi_inode), + atomic_read(&uci_handle->ref_count)); + return 0; + } - if (!(uci_handle->f_flags & O_SYNC)) - kfree(uci_handle->wreqs); - mutex_lock(&uci_handle->out_chan_lock); - mhi_dev_close_channel(uci_handle->out_handle); - wake_up(&uci_handle->write_wq); - mutex_unlock(&uci_handle->out_chan_lock); + uci_log(UCI_DBG_DBG, + "Last client left, closing channel 0x%x\n", + iminor(mhi_inode)); - mutex_lock(&uci_handle->in_chan_lock); - mhi_dev_close_channel(uci_handle->in_handle); - wake_up(&uci_handle->read_wq); - mutex_unlock(&uci_handle->in_chan_lock); + do { + if (mhi_dev_channel_has_pending_write(uci_handle->out_handle)) + usleep_range(MHI_UCI_RELEASE_TIMEOUT_MIN, + MHI_UCI_RELEASE_TIMEOUT_MAX); + else + break; + } while (++count < MHI_UCI_RELEASE_TIMEOUT_COUNT); - } - atomic_set(&uci_handle->read_data_ready, 0); - atomic_set(&uci_handle->write_data_ready, 0); - file_handle->private_data = NULL; - } else { - uci_log(UCI_DBG_DBG, - "Client close chan %d, ref count 0x%x\n", - iminor(mhi_inode), - atomic_read(&uci_handle->ref_count)); + if (count == MHI_UCI_RELEASE_TIMEOUT_COUNT) { + uci_log(UCI_DBG_DBG, "Channel %d has pending writes\n", + iminor(mhi_inode)); } + + if (atomic_read(&uci_handle->mhi_chans_open)) { + atomic_set(&uci_handle->mhi_chans_open, 0); + + if (!(uci_handle->f_flags & O_SYNC)) + kfree(uci_handle->wreqs); + mutex_lock(&uci_handle->out_chan_lock); + mhi_dev_close_channel(uci_handle->out_handle); + wake_up(&uci_handle->write_wq); + mutex_unlock(&uci_handle->out_chan_lock); + + mutex_lock(&uci_handle->in_chan_lock); + mhi_dev_close_channel(uci_handle->in_handle); + wake_up(&uci_handle->read_wq); + mutex_unlock(&uci_handle->in_chan_lock); + } + + atomic_set(&uci_handle->read_data_ready, 0); + atomic_set(&uci_handle->write_data_ready, 0); + file_handle->private_data = NULL; + return 0; } @@ -1017,6 +1015,15 @@ static int mhi_state_uevent(struct device *dev, struct kobj_uevent_env *env) mhi_parse_state(buf, &nbytes, info); add_uevent_var(env, "MHI_CHANNEL_STATE_12=%s", buf); + rc = mhi_ctrl_state_info(MHI_CLIENT_DCI_OUT, &info); + if (rc) { + pr_err("Failed to obtain channel 20 state\n"); + return -EINVAL; + } + nbytes = 0; + mhi_parse_state(buf, &nbytes, info); + add_uevent_var(env, "MHI_CHANNEL_STATE_20=%s", buf); + return 0; } @@ -1313,13 +1320,6 @@ void mhi_uci_chan_state_notify(struct mhi_dev *mhi, uci_log(UCI_DBG_ERROR, "Sending uevent failed for chan %d\n", ch_id); - if (ch_state == MHI_STATE_DISCONNECTED && - !atomic_read(&uci_handle->ref_count)) { - /* Issue wake only if there is an active client */ - wake_up(&uci_handle->read_wq); - wake_up(&uci_handle->write_wq); - } - kfree(buf[0]); } EXPORT_SYMBOL(mhi_uci_chan_state_notify); @@ -1605,6 +1605,29 @@ static long mhi_uci_client_ioctl(struct file *file, unsigned int cmd, uci_log(UCI_DBG_DBG, "DPL ipa_prod_idx:%d\n", epinfo.ipa_ep_pair.prod_pipe_num); + rc = copy_to_user((void __user *)arg, &epinfo, + sizeof(epinfo)); + if (rc) + uci_log(UCI_DBG_ERROR, "copying to user space failed"); + } else if (cmd == MHI_UCI_CV2X_EP_LOOKUP) { + uci_log(UCI_DBG_DBG, "CV2X EP_LOOKUP for client:%d\n", + uci_handle->client_index); + epinfo.ph_ep_info.ep_type = DATA_EP_TYPE_PCIE; + epinfo.ph_ep_info.peripheral_iface_id = MHI_CV2X_IFACE_ID; + epinfo.ipa_ep_pair.cons_pipe_num = + ipa_get_ep_mapping(IPA_CLIENT_MHI2_PROD); + epinfo.ipa_ep_pair.prod_pipe_num = + ipa_get_ep_mapping(IPA_CLIENT_MHI2_CONS); + + uci_log(UCI_DBG_DBG, "client:%d ep_type:%d intf:%d\n", + uci_handle->client_index, + epinfo.ph_ep_info.ep_type, + epinfo.ph_ep_info.peripheral_iface_id); + + uci_log(UCI_DBG_DBG, "ipa_cons2_idx:%d ipa_prod2_idx:%d\n", + epinfo.ipa_ep_pair.cons_pipe_num, + epinfo.ipa_ep_pair.prod_pipe_num); + rc = copy_to_user((void __user *)arg, &epinfo, sizeof(epinfo)); if (rc) @@ -1750,8 +1773,16 @@ static void mhi_uci_at_ctrl_client_cb(struct mhi_dev_client_cb_data *cb_data) uci_ctxt.at_ctrl_wq = NULL; if (!(client->f_flags & O_SYNC)) kfree(client->wreqs); - mhi_dev_close_channel(client->out_handle); - mhi_dev_close_channel(client->in_handle); + rc = mhi_dev_close_channel(client->out_handle); + if (rc) + uci_log(UCI_DBG_INFO, + "Failed to close channel %d ret %d\n", + client->out_chan, rc); + rc = mhi_dev_close_channel(client->in_handle); + if (rc) + uci_log(UCI_DBG_INFO, + "Failed to close channel %d ret %d\n", + client->in_chan, rc); } } @@ -1882,7 +1913,8 @@ int mhi_uci_init(void) * this client's channels is called by the MHI driver, * if one is registered. */ - if (mhi_client->in_chan_attr->chan_state_cb) + if (mhi_client->in_chan_attr->chan_state_cb || + mhi_client->in_chan_attr->skip_node) continue; ret_val = uci_device_create(mhi_client); if (ret_val) @@ -1936,4 +1968,3 @@ int mhi_uci_init(void) failed_char_alloc: return r; } - diff --git a/drivers/power/reset/msm-poweroff.c b/drivers/power/reset/msm-poweroff.c index e995708bd370..6593ad97d0b1 100644 --- a/drivers/power/reset/msm-poweroff.c +++ b/drivers/power/reset/msm-poweroff.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2020, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -45,24 +45,19 @@ #define SCM_WDOG_DEBUG_BOOT_PART 0x9 #define SCM_DLOAD_FULLDUMP 0X10 #define SCM_EDLOAD_MODE 0X01 -#define SCM_EDLOAD_PCI_MODE 0X04 #define SCM_DLOAD_CMD 0x10 #define SCM_DLOAD_MINIDUMP 0X20 #define SCM_DLOAD_BOTHDUMPS (SCM_DLOAD_MINIDUMP | SCM_DLOAD_FULLDUMP) -#define BOOT_CONFIG_SHIFT 3 - static int restart_mode; static void *restart_reason; static bool scm_pmic_arbiter_disable_supported; static bool scm_deassert_ps_hold_supported; /* Download mode master kill-switch */ static void __iomem *msm_ps_hold; -static void __iomem *boot_config; static phys_addr_t tcsr_boot_misc_detect; static void scm_disable_sdi(void); static bool force_warm_reboot; -static bool early_pcie_init_enable; #ifdef CONFIG_QCOM_DLOAD_MODE /* Runtime could be only changed value once. @@ -191,10 +186,7 @@ static void enable_emergency_dload_mode(void) mb(); } - if (early_pcie_init_enable) - ret = scm_set_dload_mode(SCM_EDLOAD_PCI_MODE, 0); - else - ret = scm_set_dload_mode(SCM_EDLOAD_MODE, 0); + ret = scm_set_dload_mode(SCM_EDLOAD_MODE, 0); if (ret) pr_err("Failed to set secure EDLOAD mode: %d\n", ret); } @@ -296,7 +288,8 @@ static void msm_restart_prepare(const char *cmd) * Kill download mode if master-kill switch is set */ - set_dload_mode(false); + set_dload_mode(download_mode && + (in_panic || restart_mode == RESTART_DLOAD)); #endif if (qpnp_pon_check_hard_reset_stored()) { @@ -310,10 +303,6 @@ static void msm_restart_prepare(const char *cmd) (cmd != NULL && cmd[0] != '\0')); } -#ifdef CONFIG_QCOM_PRESERVE_MEM - need_warm_reset = true; -#endif - if (force_warm_reboot) pr_info("Forcing a warm reset of the system\n"); @@ -596,7 +585,6 @@ static int msm_restart_probe(struct platform_device *pdev) struct device *dev = &pdev->dev; struct resource *mem; struct device_node *np; - uint32_t read_val; int ret = 0; #ifdef CONFIG_QCOM_DLOAD_MODE @@ -694,22 +682,6 @@ static int msm_restart_probe(struct platform_device *pdev) if (mem) tcsr_boot_misc_detect = mem->start; - - early_pcie_init_enable = 0; - mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "boot-config"); - if (mem) { - boot_config = devm_ioremap_resource(dev, mem); - if (IS_ERR(boot_config)) { - pr_err("unable to ioremap boot config offset\n"); - return PTR_ERR(boot_config); - } - - read_val = __raw_readl(boot_config); - - /* Bit 3 of the BOOT_CONFIG is used as the PCIe_EARLY_INIT_EN */ - early_pcie_init_enable = (read_val >> BOOT_CONFIG_SHIFT) & 1; - } - pm_power_off = do_msm_poweroff; arm_pm_restart = do_msm_restart; @@ -755,4 +727,3 @@ static int __init msm_restart_init(void) return platform_driver_register(&msm_restart_driver); } pure_initcall(msm_restart_init); - diff --git a/drivers/power/supply/power_supply_sysfs.c b/drivers/power/supply/power_supply_sysfs.c index db8ee9f653c8..0b20171b7214 100644 --- a/drivers/power/supply/power_supply_sysfs.c +++ b/drivers/power/supply/power_supply_sysfs.c @@ -327,14 +327,11 @@ static struct device_attribute power_supply_attrs[] = { POWER_SUPPLY_ATTR(ctm_current_max), POWER_SUPPLY_ATTR(hw_current_max), POWER_SUPPLY_ATTR(real_type), - POWER_SUPPLY_ATTR(hvdcp3_type), - POWER_SUPPLY_ATTR(quick_charge_type), POWER_SUPPLY_ATTR(dc_adapter), POWER_SUPPLY_ATTR(pr_swap), POWER_SUPPLY_ATTR(cc_step), POWER_SUPPLY_ATTR(cc_step_sel), POWER_SUPPLY_ATTR(sw_jeita_enabled), - POWER_SUPPLY_ATTR(dynamic_fv_enabled), POWER_SUPPLY_ATTR(pd_voltage_max), POWER_SUPPLY_ATTR(pd_voltage_min), POWER_SUPPLY_ATTR(sdp_current_max), diff --git a/drivers/power/supply/qcom/battery.c b/drivers/power/supply/qcom/battery.c index 2f7d47fba276..7cd74e411aae 100644 --- a/drivers/power/supply/qcom/battery.c +++ b/drivers/power/supply/qcom/battery.c @@ -1,4 +1,5 @@ /* Copyright (c) 2018,2019 The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/drivers/power/supply/qcom/qpnp-fg-gen3.c b/drivers/power/supply/qcom/qpnp-fg-gen3.c index 7b4c3290fe54..792295acc068 100644 --- a/drivers/power/supply/qcom/qpnp-fg-gen3.c +++ b/drivers/power/supply/qcom/qpnp-fg-gen3.c @@ -1,4 +1,5 @@ /* Copyright (c) 2016-2020, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -673,8 +674,11 @@ static int fg_get_battery_temp(struct fg_chip *chip, int *val) temp = ((buf[1] & BATT_TEMP_MSB_MASK) << 8) | (buf[0] & BATT_TEMP_LSB_MASK); - /* Value is in 0.25Kelvin; Convert it to deciDegC */ - *val = DIV_ROUND_CLOSEST((temp - 273*4) * 10, 4); + temp = DIV_ROUND_CLOSEST(temp, 4); + + /* Value is in Kelvin; Convert it to deciDegC */ + temp = (temp - 273) * 10; + *val = temp; return 0; } @@ -1903,9 +1907,7 @@ static int fg_charge_full_update(struct fg_chip *chip) msoc, bsoc, chip->health, chip->charge_status, chip->charge_full); if (chip->charge_done && !chip->charge_full) { - if (msoc >= 99 && (chip->health == POWER_SUPPLY_HEALTH_GOOD - || chip->health == POWER_SUPPLY_HEALTH_COOL - || chip->health == POWER_SUPPLY_HEALTH_WARM)) { + if (msoc >= 99 && chip->health == POWER_SUPPLY_HEALTH_GOOD) { fg_dbg(chip, FG_STATUS, "Setting charge_full to true\n"); chip->charge_full = true; /* diff --git a/drivers/power/supply/qcom/qpnp-smb2.c b/drivers/power/supply/qcom/qpnp-smb2.c index 53246e1adf5e..4cdf33d217db 100644 --- a/drivers/power/supply/qcom/qpnp-smb2.c +++ b/drivers/power/supply/qcom/qpnp-smb2.c @@ -251,9 +251,6 @@ static int smb2_parse_dt(struct smb2 *chip) chg->wireless_support = of_property_read_bool(node, "qcom,wireless-support"); - chg->dynamic_fv_enabled = of_property_read_bool(node, - "qcom,dynamic-fv-enable"); - rc = of_property_read_u32(node, "qcom,wd-bark-time-secs", &chip->dt.wd_bark_time); if (rc < 0 || chip->dt.wd_bark_time < MIN_WD_BARK_TIME) @@ -460,13 +457,11 @@ static int smb2_parse_dt(struct smb2 *chip) rc = of_property_read_u32(node, "qcom,otg-deglitch-time-ms", &chg->otg_delay_ms); - if (rc < 0) { + if (rc < 0) chg->otg_delay_ms = OTG_DEFAULT_DEGLITCH_TIME_MS; rc = of_property_read_u32(node, "qcom,fcc-low-temp-delta", &chip->dt.jeita_low_cc_delta); - } - if (rc < 0) chip->dt.jeita_low_cc_delta = DEFAULT_CRITICAL_JEITA_CCOMP; chg->jeita_ccomp_low_delta = chip->dt.jeita_low_cc_delta; @@ -505,7 +500,6 @@ static enum power_supply_property smb2_usb_props[] = { POWER_SUPPLY_PROP_VOLTAGE_MAX, POWER_SUPPLY_PROP_VOLTAGE_MAX_DESIGN, POWER_SUPPLY_PROP_VOLTAGE_NOW, - POWER_SUPPLY_PROP_QUICK_CHARGE_TYPE, POWER_SUPPLY_PROP_PD_CURRENT_MAX, POWER_SUPPLY_PROP_CURRENT_MAX, POWER_SUPPLY_PROP_TYPE, @@ -521,7 +515,6 @@ static enum power_supply_property smb2_usb_props[] = { POWER_SUPPLY_PROP_CTM_CURRENT_MAX, POWER_SUPPLY_PROP_HW_CURRENT_MAX, POWER_SUPPLY_PROP_REAL_TYPE, - POWER_SUPPLY_PROP_HVDCP3_TYPE, POWER_SUPPLY_PROP_PR_SWAP, POWER_SUPPLY_PROP_PD_VOLTAGE_MAX, POWER_SUPPLY_PROP_PD_VOLTAGE_MIN, @@ -590,15 +583,6 @@ static int smb2_usb_get_prop(struct power_supply *psy, else val->intval = chg->real_charger_type; break; - case POWER_SUPPLY_PROP_HVDCP3_TYPE: - if (chg->real_charger_type == POWER_SUPPLY_TYPE_USB_HVDCP_3) - val->intval = HVDCP3_CLASSA_18W; - else - val->intval = HVDCP3_NONE; - break; - case POWER_SUPPLY_PROP_QUICK_CHARGE_TYPE: - val->intval = smblib_get_quick_charge_type(chg); - break; case POWER_SUPPLY_PROP_TYPEC_MODE: if (chg->connector_type == POWER_SUPPLY_CONNECTOR_MICRO_USB) val->intval = POWER_SUPPLY_TYPEC_NONE; @@ -1330,7 +1314,6 @@ static enum power_supply_property smb2_batt_props[] = { POWER_SUPPLY_PROP_TECHNOLOGY, POWER_SUPPLY_PROP_STEP_CHARGING_ENABLED, POWER_SUPPLY_PROP_SW_JEITA_ENABLED, - POWER_SUPPLY_PROP_DYNAMIC_FV_ENABLED, POWER_SUPPLY_PROP_CHARGE_DONE, POWER_SUPPLY_PROP_PARALLEL_DISABLE, POWER_SUPPLY_PROP_SET_SHIP_MODE, @@ -1405,9 +1388,6 @@ static int smb2_batt_get_prop(struct power_supply *psy, case POWER_SUPPLY_PROP_SW_JEITA_ENABLED: val->intval = chg->sw_jeita_enabled; break; - case POWER_SUPPLY_PROP_DYNAMIC_FV_ENABLED: - val->intval = chg->dynamic_fv_enabled; - break; case POWER_SUPPLY_PROP_VOLTAGE_MAX: val->intval = get_client_vote(chg->fv_votable, BATT_PROFILE_VOTER); @@ -1547,9 +1527,6 @@ static int smb2_batt_set_prop(struct power_supply *psy, chg->sw_jeita_enabled = !!val->intval; } break; - case POWER_SUPPLY_PROP_DYNAMIC_FV_ENABLED: - chg->dynamic_fv_enabled = !!val->intval; - break; case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX: chg->batt_profile_fcc_ua = val->intval; vote(chg->fcc_votable, BATT_PROFILE_VOTER, true, val->intval); @@ -1605,8 +1582,6 @@ static int smb2_batt_prop_is_writeable(struct power_supply *psy, case POWER_SUPPLY_PROP_SW_JEITA_ENABLED: case POWER_SUPPLY_PROP_DIE_HEALTH: case POWER_SUPPLY_PROP_DC_THERMAL_LEVELS: - case POWER_SUPPLY_PROP_VOLTAGE_MAX: - case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX: return 1; default: break; diff --git a/drivers/power/supply/qcom/smb-lib.c b/drivers/power/supply/qcom/smb-lib.c index ac98fea5cfc3..2d777eafe443 100644 --- a/drivers/power/supply/qcom/smb-lib.c +++ b/drivers/power/supply/qcom/smb-lib.c @@ -1,4 +1,5 @@ /* Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -25,10 +26,6 @@ #include "step-chg-jeita.h" #include "storm-watch.h" -#ifdef CONFIG_FORCE_FAST_CHARGE -#include -#endif - #define smblib_err(chg, fmt, ...) \ pr_err("%s: %s: " fmt, chg->name, \ __func__, ##__VA_ARGS__) \ @@ -296,7 +293,7 @@ enum { MAX_TYPES }; -static const struct apsd_result smblib_apsd_results[] = { +static const struct apsd_result const smblib_apsd_results[] = { [UNKNOWN] = { .name = "UNKNOWN", .bit = 0, @@ -1101,13 +1098,6 @@ static int set_sdp_current(struct smb_charger *chg, int icl_ua) u8 icl_options; const struct apsd_result *apsd_result = smblib_get_apsd_result(chg); -#ifdef CONFIG_FORCE_FAST_CHARGE - if (force_fast_charge > 0 && icl_ua == USBIN_500MA) - { - icl_ua = USBIN_900MA; - } -#endif - /* power source is SDP */ switch (icl_ua) { case USBIN_100MA: @@ -3030,11 +3020,6 @@ int smblib_get_prop_usb_online(struct smb_charger *chg, return rc; } - if (get_client_vote_locked(chg->usb_icl_votable, JEITA_VOTER) == 0) { - val->intval = true; - return rc; - } - if (chg->typec_en_dis_active) { val->intval = 1; return 0; @@ -4648,51 +4633,6 @@ static void smblib_hvdcp_adaptive_voltage_change(struct smb_charger *chg) } } -struct quick_charge adapter_cap[10] = { - { POWER_SUPPLY_TYPE_USB, QUICK_CHARGE_NORMAL }, - { POWER_SUPPLY_TYPE_USB_DCP, QUICK_CHARGE_NORMAL }, - { POWER_SUPPLY_TYPE_USB_CDP, QUICK_CHARGE_NORMAL }, - { POWER_SUPPLY_TYPE_USB_ACA, QUICK_CHARGE_NORMAL }, - { POWER_SUPPLY_TYPE_USB_FLOAT, QUICK_CHARGE_NORMAL }, - { POWER_SUPPLY_TYPE_USB_PD, QUICK_CHARGE_FAST }, - { POWER_SUPPLY_TYPE_USB_HVDCP, QUICK_CHARGE_FAST }, - { POWER_SUPPLY_TYPE_USB_HVDCP_3, QUICK_CHARGE_FAST }, - { POWER_SUPPLY_TYPE_WIRELESS, QUICK_CHARGE_FAST }, - {0, 0}, -}; - -int smblib_get_quick_charge_type(struct smb_charger *chg) -{ - int i = 0, rc; - union power_supply_propval pval = {0, }; - - if (!chg) { - dev_err(chg->dev, "get quick charge type faied\n"); - return -EINVAL; - } - - rc = smblib_get_prop_batt_status(chg, &pval); - if (rc < 0) - return -EINVAL; - - if (pval.intval == POWER_SUPPLY_STATUS_DISCHARGING) - return 0; - - if ((chg->real_charger_type == POWER_SUPPLY_TYPE_USB_PD) && chg->pd_verifed) - return QUICK_CHARGE_TURBE; - - if (chg->is_qc_class_b) - return QUICK_CHARGE_FLASH; - - while (adapter_cap[i].adap_type != 0) { - if (chg->real_charger_type == adapter_cap[i].adap_type) - return adapter_cap[i].adap_cap; - i++; - } - - return 0; -} - /* triggers when HVDCP 3.0 authentication has finished */ static void smblib_handle_hvdcp_3p0_auth_done(struct smb_charger *chg, bool rising) @@ -5515,13 +5455,10 @@ static void smblib_handle_typec_cc_state_change(struct smb_charger *chg) smblib_wireless_set_enable(chg, false); } smblib_handle_typec_insertion(chg); - schedule_delayed_work(&chg->charger_type_recheck, - msecs_to_jiffies(20000)); - schedule_delayed_work(&chg->connector_health_work, 0); + schedule_delayed_work(&chg->charger_type_recheck, msecs_to_jiffies(20000)); } else if (chg->typec_present && chg->typec_mode == POWER_SUPPLY_TYPEC_NONE) { cancel_delayed_work_sync(&chg->charger_type_recheck); - flush_delayed_work(&chg->connector_health_work); chg->ignore_recheck_flag = false; chg->typec_present = false; smblib_dbg(chg, PR_MISC, "TypeC removal\n"); @@ -6217,56 +6154,6 @@ static void smblib_legacy_detection_work(struct work_struct *work) smblib_usb_typec_change(chg); mutex_unlock(&chg->lock); } -#define CONNECTOR_HEALTH_TIME_20S 20000 -#define CONNECTOR_HEALTH_TIME_5S 5000 -#define CONNECTOR_HEALTH_COUNT 6 - -static void smblib_connector_health_work(struct work_struct *work) -{ - struct smb_charger *chg = container_of(work, struct smb_charger, - connector_health_work.work); - union power_supply_propval val; - int check_time, rc; - static int count, overheat; - - if (!chg->pl.psy) { - chg->pl.psy = power_supply_get_by_name("parallel"); - if (!chg->pl.psy) - return; - } - - rc = smblib_get_prop_usb_online(chg, &val); - if (rc < 0) { - smblib_err(chg, "Couldn't get usb present rc = %d\n", rc); - return; - } - - if (!val.intval) { - count = 0; - overheat = false; - power_supply_changed(chg->pl.psy); - return; - } - - if (count > CONNECTOR_HEALTH_COUNT) - check_time = CONNECTOR_HEALTH_TIME_20S; - else - check_time = CONNECTOR_HEALTH_TIME_5S; - - count++; - - power_supply_get_property(chg->pl.psy, - POWER_SUPPLY_PROP_CONNECTOR_HEALTH, &val); - - if (val.intval == POWER_SUPPLY_HEALTH_OVERHEAT || overheat) { - check_time = CONNECTOR_HEALTH_TIME_5S; - power_supply_changed(chg->pl.psy); - overheat = true; - } - - schedule_delayed_work(&chg->connector_health_work, - msecs_to_jiffies(check_time)); -} #define TYPE_RECHECK_TIME_20S 20000 #define TYPE_RECHECK_TIME_5S 5000 @@ -6605,8 +6492,6 @@ int smblib_init(struct smb_charger *chg) INIT_DELAYED_WORK(&chg->cc_float_charge_work, smblib_cc_float_charge_work); INIT_DELAYED_WORK(&chg->typec_reenable_work, smblib_typec_reenable_work); INIT_DELAYED_WORK(&chg->charger_type_recheck, smblib_charger_type_recheck); - INIT_DELAYED_WORK(&chg->connector_health_work, - smblib_connector_health_work); INIT_DELAYED_WORK(&chg->dc_input_current_work, smblib_dc_input_current_work); INIT_DELAYED_WORK(&chg->check_vbus_work, smblib_check_vbus_work); @@ -6688,7 +6573,6 @@ int smblib_deinit(struct smb_charger *chg) cancel_delayed_work_sync(&chg->bb_removal_work); cancel_delayed_work_sync(&chg->typec_reenable_work); cancel_delayed_work_sync(&chg->charger_type_recheck); - cancel_delayed_work_sync(&chg->connector_health_work); cancel_delayed_work_sync(&chg->dc_input_current_work); chg->ignore_recheck_flag = false; cancel_delayed_work_sync(&chg->check_vbus_work); diff --git a/drivers/power/supply/qcom/smb-lib.h b/drivers/power/supply/qcom/smb-lib.h index fd6a07076063..3db68a38d6b6 100644 --- a/drivers/power/supply/qcom/smb-lib.h +++ b/drivers/power/supply/qcom/smb-lib.h @@ -34,14 +34,6 @@ enum print_reason { PR_OEM = BIT(5), }; -enum hvdcp3_type { - HVDCP3_NONE = 0, - HVDCP3_CLASSA_18W, - HVDCP3_CLASSB_27W, - USB_PD, - HVDCP2_TYPE, -}; - #define DEFAULT_VOTER "DEFAULT_VOTER" #define USER_VOTER "USER_VOTER" #define PD_VOTER "PD_VOTER" @@ -71,7 +63,6 @@ enum hvdcp3_type { #define PL_DELAY_VOTER "PL_DELAY_VOTER" #define CTM_VOTER "CTM_VOTER" #define SW_QC3_VOTER "SW_QC3_VOTER" -#define JEITA_VOTER "JEITA_VOTER" #define AICL_RERUN_VOTER "AICL_RERUN_VOTER" #define LEGACY_UNKNOWN_VOTER "LEGACY_UNKNOWN_VOTER" #define CC2_WA_VOTER "CC2_WA_VOTER" @@ -85,7 +76,7 @@ enum hvdcp3_type { #define DCIN_ADAPTER_VOTER "DCIN_ADAPTER_VOTER" #define CHG_AWAKE_VOTER "CHG_AWAKE_VOTER" #define DC_AWAKE_VOTER "DC_AWAKE_VOTER" -#define CC_FLOAT_VOTER "CC_FLOAT_VOTER" +#define CC_FLOAT_VOTER "CC_FLOAT_VOTER" #define WBC_VOTER "WBC_VOTER" #define MOISTURE_VOTER "MOISTURE_VOTER" #define HVDCP2_ICL_VOTER "HVDCP2_ICL_VOTER" @@ -95,7 +86,6 @@ enum hvdcp3_type { #define PD_NOT_SUPPORTED_VOTER "PD_NOT_SUPPORTED_VOTER" #define DCIN_USER_VOTER "DCIN_USER_VOTER" #define UNSTANDARD_QC2_VOTER "UNSTANDARD_QC2_VOTER" -#define PD_NOT_SUPPORTED_VOTER "PD_NOT_SUPPORTED_VOTER" #define VCONN_MAX_ATTEMPTS 3 #define OTG_MAX_ATTEMPTS 3 @@ -365,11 +355,10 @@ struct smb_charger { struct delayed_work reg_work; struct delayed_work uusb_otg_work; struct delayed_work bb_removal_work; - struct delayed_work monitor_low_temp_work; + struct delayed_work monitor_low_temp_work; struct delayed_work cc_float_charge_work; struct delayed_work typec_reenable_work; - struct delayed_work charger_type_recheck; - struct delayed_work connector_health_work; + struct delayed_work charger_type_recheck; struct delayed_work dc_input_current_work; struct delayed_work check_vbus_work; @@ -400,7 +389,6 @@ struct smb_charger { int fake_batt_status; bool step_chg_enabled; bool sw_jeita_enabled; - bool dynamic_fv_enabled; bool wireless_charging_flag; bool wireless_support; bool is_hdc; @@ -410,8 +398,6 @@ struct smb_charger { bool vconn_en; bool suspend_input_on_debug_batt; bool legacy; - bool pd_verifed; - bool is_qc_class_b; int otg_attempts; int vconn_attempts; int default_icl_ua; @@ -475,18 +461,7 @@ struct smb_charger { int precheck_charger_type; }; -enum quick_charge_type { - QUICK_CHARGE_NORMAL = 0, - QUICK_CHARGE_FAST, - QUICK_CHARGE_FLASH, - QUICK_CHARGE_TURBE, - QUICK_CHARGE_MAX, -}; -struct quick_charge { - enum power_supply_type adap_type; - enum quick_charge_type adap_cap; -}; int smblib_read(struct smb_charger *chg, u16 addr, u8 *val); int smblib_masked_write(struct smb_charger *chg, u16 addr, u8 mask, u8 val); int smblib_write(struct smb_charger *chg, u16 addr, u8 val); @@ -666,13 +641,12 @@ int smblib_set_prop_pr_swap_in_progress(struct smb_charger *chg, const union power_supply_propval *val); int smblib_stat_sw_override_cfg(struct smb_charger *chg, bool override); void smblib_usb_typec_change(struct smb_charger *chg); -int smblib_get_quick_charge_type(struct smb_charger *chg); int smblib_set_prop_rerun_apsd(struct smb_charger *chg, const union power_supply_propval *val); int smblib_toggle_stat(struct smb_charger *chg, int reset); +int smblib_force_ufp(struct smb_charger *chg); int smblib_set_prop_wireless_wakelock(struct smb_charger *chg, const union power_supply_propval *val); -int smblib_force_ufp(struct smb_charger *chg); int smblib_init(struct smb_charger *chg); int smblib_deinit(struct smb_charger *chg); diff --git a/drivers/power/supply/qcom/smb1355-charger.c b/drivers/power/supply/qcom/smb1355-charger.c index 9c8d5552e7af..48c15a23d3ab 100644 --- a/drivers/power/supply/qcom/smb1355-charger.c +++ b/drivers/power/supply/qcom/smb1355-charger.c @@ -1,5 +1,5 @@ /* Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. - * Copyright (C) 2019 XiaoMi, Inc. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -578,41 +578,25 @@ static int smb1355_get_prop_batt_charge_type(struct smb1355 *chip, static int smb1355_get_prop_online(struct smb1355 *chip, union power_supply_propval *val) { - int rc; - u8 stat; + int rc; + u8 stat; - rc = smb1355_read(chip, POWER_PATH_STATUS_REG, &stat); - if (rc < 0) { - pr_err("Couldn't read power path status rc=%d\n", rc); - return rc; - } + rc = smb1355_read(chip, POWER_PATH_STATUS_REG, &stat); + if (rc < 0) { + pr_err("Couldn't read power path status rc=%d\n", rc); + return rc; + } - val->intval = (stat & USE_USBIN_BIT) && - (stat & VALID_INPUT_POWER_SOURCE_STS_BIT); + val->intval = (stat & USE_USBIN_BIT) && + (stat & VALID_INPUT_POWER_SOURCE_STS_BIT); - return rc; + return rc; } static int smb1355_get_prop_health(struct smb1355 *chip, int type) { u8 temp; int rc, shift; - u8 stat = 0; - int usb_present = 0; - static int overheat; - - rc = smb1355_read(chip, POWER_PATH_STATUS_REG, &stat); - if (rc < 0) { - pr_err("Couldn't read power path status rc=%d\n", rc); - return POWER_SUPPLY_HEALTH_COOL; - } - usb_present = (stat & USE_USBIN_BIT) && - (stat & VALID_INPUT_POWER_SOURCE_STS_BIT); - - if (type == CONNECTOR_TEMP && !usb_present) { - overheat = 0; - return POWER_SUPPLY_HEALTH_COOL; - } /* Connector-temp uses skin-temp configuration */ shift = (type == CONNECTOR_TEMP) ? SKIN_TEMP_SHIFT : 0; @@ -626,22 +610,8 @@ static int smb1355_get_prop_health(struct smb1355 *chip, int type) return POWER_SUPPLY_HEALTH_UNKNOWN; } - if (temp & (TEMP_RST_HOT_BIT << shift)) { - if (type == CONNECTOR_TEMP) { - if (overheat > 5) { - pr_info("%s: ntc is overheat:%x!\n", __func__, temp); - return POWER_SUPPLY_HEALTH_OVERHEAT; - } else { - pr_info("%s overheat count:%d\n", __func__, overheat); - overheat++; - return POWER_SUPPLY_HEALTH_HOT; - } - } else { - return POWER_SUPPLY_HEALTH_OVERHEAT; - } - } - if (type == CONNECTOR_TEMP) - overheat = 0; + if (temp & (TEMP_RST_HOT_BIT << shift)) + return POWER_SUPPLY_HEALTH_OVERHEAT; if (temp & (TEMP_UB_HOT_BIT << shift)) return POWER_SUPPLY_HEALTH_HOT; @@ -1050,7 +1020,8 @@ static int smb1355_tskin_sensor_config(struct smb1355 *chip) } rc = smb1355_masked_write(chip, BATIF_C1_REG_CFG, - 0xff, 0); + 0xff, + 0); if (rc < 0) { pr_err("Couldn't set BATIF_CFG_SMISC_BATID rc=%d\n", rc); diff --git a/drivers/power/supply/qcom/step-chg-jeita.c b/drivers/power/supply/qcom/step-chg-jeita.c index b1ff010a376e..60a761bf75db 100644 --- a/drivers/power/supply/qcom/step-chg-jeita.c +++ b/drivers/power/supply/qcom/step-chg-jeita.c @@ -24,7 +24,6 @@ #define MAX_STEP_CHG_ENTRIES 5 #define STEP_CHG_VOTER "STEP_CHG_VOTER" #define JEITA_VOTER "JEITA_VOTER" -#define DYNAMIC_FV_VOTER "DYNAMIC_FV_VOTER" #define is_between(left, right, value) \ (((left) >= (right) && (left) >= (value) \ @@ -59,35 +58,25 @@ struct jeita_fv_cfg { struct range_data fv_cfg[MAX_STEP_CHG_ENTRIES]; }; -struct dynamic_fv_cfg { - char *prop_name; - struct range_data fv_cfg[MAX_STEP_CHG_ENTRIES]; -}; - struct step_chg_info { struct device *dev; ktime_t step_last_update_time; ktime_t jeita_last_update_time; - ktime_t dynamic_fv_last_update_time; bool step_chg_enable; bool sw_jeita_enable; - bool dynamic_fv_enable; bool config_is_read; bool step_chg_cfg_valid; bool sw_jeita_cfg_valid; - bool dynamic_fv_cfg_valid; bool soc_based_step_chg; bool batt_missing; int jeita_fcc_index; int jeita_fv_index; - int dynamic_fv_index; int step_index; int get_config_retry_count; struct step_chg_cfg *step_chg_config; struct jeita_fcc_cfg *jeita_fcc_config; struct jeita_fv_cfg *jeita_fv_config; - struct dynamic_fv_cfg *dynamic_fv_config; struct votable *fcc_votable; struct votable *fv_votable; @@ -318,17 +307,6 @@ static int get_step_chg_jeita_setting_from_profile(struct step_chg_info *chip) chip->sw_jeita_cfg_valid = false; } - chip->dynamic_fv_cfg_valid = true; - rc = read_range_data_from_node(profile_node, - "qcom,dynamic-fv-ranges", - chip->dynamic_fv_config->fv_cfg, - BATT_HOT_DECIDEGREE_MAX, max_fv_uv); - if (rc < 0) { - pr_debug("Read qcom,dynamic-fv-ranges failed from battery profile, rc=%d\n", - rc); - chip->dynamic_fv_cfg_valid = false; - } - return rc; } @@ -369,11 +347,7 @@ static void get_config_work(struct work_struct *work) chip->jeita_fv_config->fv_cfg[i].low_threshold, chip->jeita_fv_config->fv_cfg[i].high_threshold, chip->jeita_fv_config->fv_cfg[i].value); - for (i = 0; i < MAX_STEP_CHG_ENTRIES; i++) - pr_debug("dynamic-fv-cfg: %d(count) ~ %d(coutn), %duV\n", - chip->dynamic_fv_config->fv_cfg[i].low_threshold, - chip->dynamic_fv_config->fv_cfg[i].high_threshold, - chip->dynamic_fv_config->fv_cfg[i].value); + return; reschedule: @@ -535,87 +509,6 @@ static int handle_step_chg_config(struct step_chg_info *chip) } #define JEITA_SUSPEND_HYST_UV 50000 -static int handle_dynamic_fv(struct step_chg_info *chip) -{ - union power_supply_propval pval = {0, }; - int rc = 0, fv_uv, cycle_count; - u64 elapsed_us; - int batt_vol = 0; - - rc = power_supply_get_property(chip->batt_psy, - POWER_SUPPLY_PROP_DYNAMIC_FV_ENABLED, &pval); - if (rc < 0) - chip->dynamic_fv_enable = 0; - else - chip->dynamic_fv_enable = pval.intval; - - if (!chip->dynamic_fv_enable || !chip->dynamic_fv_cfg_valid) { - /*need recovery some setting*/ - if (chip->fv_votable) - vote(chip->fv_votable, DYNAMIC_FV_VOTER, false, 0); - return 0; - } - - elapsed_us = ktime_us_delta(ktime_get(), chip->dynamic_fv_last_update_time); - if (elapsed_us < STEP_CHG_HYSTERISIS_DELAY_US) - goto reschedule; - - rc = power_supply_get_property(chip->bms_psy, - POWER_SUPPLY_PROP_CYCLE_COUNT, &pval); - if (rc < 0) { - pr_err("Couldn't read %s property rc=%d\n", - chip->dynamic_fv_config->prop_name, rc); - return rc; - } - cycle_count = pval.intval; - - rc = get_val(chip->dynamic_fv_config->fv_cfg, - 0, - chip->dynamic_fv_index, - cycle_count, - &chip->dynamic_fv_index, - &fv_uv); - if (rc < 0) { - /* remove the vote if no step-based fv is found */ - if (chip->fv_votable) - vote(chip->fv_votable, DYNAMIC_FV_VOTER, false, 0); - goto update_time; - } - - power_supply_get_property(chip->batt_psy, - POWER_SUPPLY_PROP_VOLTAGE_NOW, &pval); - batt_vol = pval.intval; - if (batt_vol >= fv_uv) - goto update_time; - - chip->fv_votable = find_votable("FV"); - if (!chip->fv_votable) - goto update_time; - - vote(chip->fv_votable, DYNAMIC_FV_VOTER, true, fv_uv); - - /*set battery full voltage to FLOAT VOLTAGE - 10mV*/ - pval.intval = fv_uv - 10000; - rc = power_supply_set_property(chip->bms_psy, - POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE, &pval); - if (rc < 0) { - pr_err("Couldn't set CONSTANT VOLTAGE property rc=%d\n", rc); - return rc; - } - - pr_debug("%s:cycle_count:%d,Batt_full:%d,fv:%d,\n", - __func__, cycle_count, pval.intval, fv_uv); - -update_time: - chip->dynamic_fv_last_update_time = ktime_get(); - return 0; - -reschedule: - /* reschedule 1000uS after the remaining time */ - return (STEP_CHG_HYSTERISIS_DELAY_US - elapsed_us + 1000); -} - - static int handle_jeita(struct step_chg_info *chip) { union power_supply_propval pval = {0, }; @@ -748,7 +641,6 @@ static int handle_battery_insertion(struct step_chg_info *chip) if (chip->batt_missing) { chip->step_chg_cfg_valid = false; chip->sw_jeita_cfg_valid = false; - chip->dynamic_fv_cfg_valid = false; chip->get_config_retry_count = 0; } else { /* @@ -772,7 +664,6 @@ static void status_change_work(struct work_struct *work) int reschedule_jeita_work_us = 0; int reschedule_step_work_us = 0; union power_supply_propval prop = {0, }; - int reschedule_dynamic_fv_work_us = 0; if (!is_batt_available(chip)) goto exit_work; @@ -784,13 +675,7 @@ static void status_change_work(struct work_struct *work) if (rc > 0) reschedule_jeita_work_us = rc; else if (rc < 0) - pr_err("Couldn't handle sw dynamic fv rc = %d\n", rc); - - rc = handle_dynamic_fv(chip); - if (rc > 0) - reschedule_dynamic_fv_work_us = rc; - else if (rc < 0) - pr_err("Couldn't handle sw rc = %d\n", rc); + pr_err("Couldn't handle sw jeita rc = %d\n", rc); rc = handle_step_chg_config(chip); if (rc > 0) @@ -811,7 +696,6 @@ static void status_change_work(struct work_struct *work) } reschedule_us = min(reschedule_jeita_work_us, reschedule_step_work_us); - reschedule_us = min(reschedule_dynamic_fv_work_us, reschedule_us); if (reschedule_us == 0) goto exit_work; else @@ -887,7 +771,6 @@ int qcom_step_chg_init(struct device *dev, chip->step_index = -EINVAL; chip->jeita_fcc_index = -EINVAL; chip->jeita_fv_index = -EINVAL; - chip->dynamic_fv_index = -EINVAL; chip->step_chg_config = devm_kzalloc(dev, sizeof(struct step_chg_cfg), GFP_KERNEL); @@ -902,9 +785,7 @@ int qcom_step_chg_init(struct device *dev, sizeof(struct jeita_fcc_cfg), GFP_KERNEL); chip->jeita_fv_config = devm_kzalloc(dev, sizeof(struct jeita_fv_cfg), GFP_KERNEL); - chip->dynamic_fv_config = devm_kzalloc(dev, - sizeof(struct dynamic_fv_cfg), GFP_KERNEL); - if (!chip->jeita_fcc_config || !chip->jeita_fv_config || !chip->dynamic_fv_config) + if (!chip->jeita_fcc_config || !chip->jeita_fv_config) return -ENOMEM; chip->jeita_fcc_config->psy_prop = POWER_SUPPLY_PROP_TEMP; @@ -914,8 +795,6 @@ int qcom_step_chg_init(struct device *dev, chip->jeita_fv_config->prop_name = "BATT_TEMP"; chip->jeita_fv_config->hysteresis = 5; - chip->dynamic_fv_config->prop_name = "BATT_CYCLE_COUNT"; - INIT_DELAYED_WORK(&chip->status_change_work, status_change_work); INIT_DELAYED_WORK(&chip->get_config_work, get_config_work); diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c index a040e83c6f97..cae8ddca9b79 100755 --- a/drivers/scsi/ufs/ufshcd.c +++ b/drivers/scsi/ufs/ufshcd.c @@ -1572,6 +1572,11 @@ int ufshcd_hold(struct ufs_hba *hba, bool async) */ if (ufshcd_can_hibern8_during_gating(hba) && ufshcd_is_link_hibern8(hba)) { + if (async) { + rc = -EAGAIN; + hba->clk_gating.active_reqs--; + break; + } spin_unlock_irqrestore(hba->host->host_lock, flags); flush_work(&hba->clk_gating.ungate_work); spin_lock_irqsave(hba->host->host_lock, flags); diff --git a/drivers/soc/qcom/glink.c b/drivers/soc/qcom/glink.c index cf8a096ca1d3..c976f1711a37 100644 --- a/drivers/soc/qcom/glink.c +++ b/drivers/soc/qcom/glink.c @@ -5832,7 +5832,7 @@ static void glink_pm_qos_unvote(struct glink_core_xprt_ctx *xprt_ptr) xprt_ptr->tx_path_activity = false; if (xprt_ptr->qos_req_active) { GLINK_PERF("%s: qos unvote\n", __func__); - queue_delayed_work(system_power_efficient_wq, &xprt_ptr->pm_qos_work, + schedule_delayed_work(&xprt_ptr->pm_qos_work, msecs_to_jiffies(GLINK_PM_QOS_HOLDOFF_MS)); } } diff --git a/drivers/soc/qcom/msm-pm.c b/drivers/soc/qcom/msm-pm.c index 13dc7477b7e5..129ebceae579 100644 --- a/drivers/soc/qcom/msm-pm.c +++ b/drivers/soc/qcom/msm-pm.c @@ -51,7 +51,7 @@ #define MAX_BUF_SIZE 1024 -static int msm_pm_debug_mask = 0; +static int msm_pm_debug_mask = 1; module_param_named( debug_mask, msm_pm_debug_mask, int, 0664 ); diff --git a/drivers/soc/qcom/msm_bus/msm_bus_arb_adhoc.c b/drivers/soc/qcom/msm_bus/msm_bus_arb_adhoc.c index cb215a22791e..b6104f09ed91 100644 --- a/drivers/soc/qcom/msm_bus/msm_bus_arb_adhoc.c +++ b/drivers/soc/qcom/msm_bus/msm_bus_arb_adhoc.c @@ -25,8 +25,6 @@ #define NUM_LNODES 3 #define MAX_STR_CL 50 -#define DEBUG_REC_TRANSACTION 0 - struct bus_search_type { struct list_head link; struct list_head node_list; @@ -1256,8 +1254,7 @@ static int update_bw_adhoc(struct msm_bus_client_handle *cl, u64 ab, u64 ib) if (!strcmp(test_cl, cl->name)) log_transaction = true; - if (DEBUG_REC_TRANSACTION) - msm_bus_dbg_rec_transaction(cl, ab, ib); + msm_bus_dbg_rec_transaction(cl, ab, ib); if ((cl->cur_act_ib == ib) && (cl->cur_act_ab == ab)) { MSM_BUS_DBG("%s:no change in request", cl->name); @@ -1318,9 +1315,7 @@ static int update_bw_context(struct msm_bus_client_handle *cl, u64 act_ab, if (!slp_ab && !slp_ib) cl->active_only = true; - if (DEBUG_REC_TRANSACTION) - msm_bus_dbg_rec_transaction(cl, cl->cur_act_ab, - cl->cur_dual_ib); + msm_bus_dbg_rec_transaction(cl, cl->cur_act_ab, cl->cur_dual_ib); ret = update_path(cl->mas_dev, cl->slv, act_ib, act_ab, slp_ib, slp_ab, cl->cur_act_ab, cl->cur_act_ab, cl->first_hop, cl->active_only); diff --git a/drivers/soc/qcom/peripheral-loader.c b/drivers/soc/qcom/peripheral-loader.c index a597e48b73ba..c5bfec093579 100644 --- a/drivers/soc/qcom/peripheral-loader.c +++ b/drivers/soc/qcom/peripheral-loader.c @@ -148,7 +148,7 @@ struct pil_priv { static int pil_do_minidump(struct pil_desc *desc, void *ramdump_dev) { struct md_ss_region __iomem *region_info_ss; - struct md_ss_region __iomem *region_info_pdr = NULL; + struct md_ss_region __iomem *region_info_pdr; struct ramdump_segment *ramdump_segs, *s; struct pil_priv *priv = desc->priv; void __iomem *subsys_segtable_base_ss; diff --git a/drivers/staging/android/ion/ion.c b/drivers/staging/android/ion/ion.c index 69ec3212ff58..a34829caef03 100644 --- a/drivers/staging/android/ion/ion.c +++ b/drivers/staging/android/ion/ion.c @@ -197,8 +197,6 @@ static struct ion_buffer *ion_buffer_create(struct ion_heap *heap, if (!buffer) return ERR_PTR(-ENOMEM); - INIT_LIST_HEAD(&buffer->iommu_data.map_list); - mutex_init(&buffer->iommu_data.lock); buffer->heap = heap; buffer->flags = flags; kref_init(&buffer->ref); @@ -301,7 +299,7 @@ static void _ion_buffer_destroy(struct kref *kref) struct ion_heap *heap = buffer->heap; struct ion_device *dev = buffer->dev; - msm_dma_buf_freed(&buffer->iommu_data); + msm_dma_buf_freed(buffer); mutex_lock(&dev->buffer_lock); rb_erase(&buffer->node, &dev->buffers); @@ -1175,7 +1173,7 @@ static struct sg_table *ion_map_dma_buf(struct dma_buf_attachment *attachment, enum dma_data_direction direction) { struct dma_buf *dmabuf = attachment->dmabuf; - struct ion_buffer *buffer = container_of(dmabuf->priv, typeof(*buffer), iommu_data); + struct ion_buffer *buffer = dmabuf->priv; struct sg_table *table; table = ion_dupe_sg_table(buffer->sg_table); @@ -1307,7 +1305,7 @@ static const struct vm_operations_struct ion_vma_ops = { static int ion_mmap(struct dma_buf *dmabuf, struct vm_area_struct *vma) { - struct ion_buffer *buffer = container_of(dmabuf->priv, typeof(*buffer), iommu_data); + struct ion_buffer *buffer = dmabuf->priv; int ret = 0; if (!buffer->heap->ops->map_user) { @@ -1343,14 +1341,14 @@ static int ion_mmap(struct dma_buf *dmabuf, struct vm_area_struct *vma) static void ion_dma_buf_release(struct dma_buf *dmabuf) { - struct ion_buffer *buffer = container_of(dmabuf->priv, typeof(*buffer), iommu_data); + struct ion_buffer *buffer = dmabuf->priv; ion_buffer_put(buffer); } static void *ion_dma_buf_kmap(struct dma_buf *dmabuf, unsigned long offset) { - struct ion_buffer *buffer = container_of(dmabuf->priv, typeof(*buffer), iommu_data); + struct ion_buffer *buffer = dmabuf->priv; return buffer->vaddr + offset * PAGE_SIZE; } @@ -1363,7 +1361,7 @@ static void ion_dma_buf_kunmap(struct dma_buf *dmabuf, unsigned long offset, static int ion_dma_buf_begin_cpu_access(struct dma_buf *dmabuf, enum dma_data_direction direction) { - struct ion_buffer *buffer = container_of(dmabuf->priv, typeof(*buffer), iommu_data); + struct ion_buffer *buffer = dmabuf->priv; void *vaddr; if (!buffer->heap->ops->map_kernel) { @@ -1381,7 +1379,7 @@ static int ion_dma_buf_begin_cpu_access(struct dma_buf *dmabuf, static int ion_dma_buf_end_cpu_access(struct dma_buf *dmabuf, enum dma_data_direction direction) { - struct ion_buffer *buffer = container_of(dmabuf->priv, typeof(*buffer), iommu_data); + struct ion_buffer *buffer = dmabuf->priv; mutex_lock(&buffer->lock); ion_buffer_kmap_put(buffer); @@ -1429,7 +1427,7 @@ static struct dma_buf *__ion_share_dma_buf(struct ion_client *client, exp_info.ops = &dma_buf_ops; exp_info.size = buffer->size; exp_info.flags = O_RDWR; - exp_info.priv = &buffer->iommu_data; + exp_info.priv = buffer; dmabuf = dma_buf_export(&exp_info); if (IS_ERR(dmabuf)) { @@ -1489,7 +1487,7 @@ static struct ion_handle *__ion_import_dma_buf(struct ion_client *client, __func__); return ERR_PTR(-EINVAL); } - buffer = container_of(dmabuf->priv, typeof(*buffer), iommu_data); + buffer = dmabuf->priv; if (lock_client) mutex_lock(&client->lock); @@ -1573,7 +1571,7 @@ static int ion_sync_for_device(struct ion_client *client, int fd) dma_buf_put(dmabuf); return -EINVAL; } - buffer = container_of(dmabuf->priv, typeof(*buffer), iommu_data); + buffer = dmabuf->priv; if (!is_buffer_hlos_assigned(buffer)) { pr_err("%s: cannot sync a secure dmabuf\n", __func__); diff --git a/drivers/staging/android/ion/ion_priv.h b/drivers/staging/android/ion/ion_priv.h index 45cac81c37f2..3f662df7b9b6 100644 --- a/drivers/staging/android/ion/ion_priv.h +++ b/drivers/staging/android/ion/ion_priv.h @@ -34,7 +34,6 @@ #include #endif #include -#include #include "ion.h" @@ -112,7 +111,6 @@ struct ion_buffer { int handle_count; char task_comm[TASK_COMM_LEN]; pid_t pid; - struct msm_iommu_data iommu_data; }; void ion_buffer_destroy(struct ion_buffer *buffer); diff --git a/drivers/staging/android/lowmemorykiller.c b/drivers/staging/android/lowmemorykiller.c index 439dcbd9c6cc..39738229ed26 100755 --- a/drivers/staging/android/lowmemorykiller.c +++ b/drivers/staging/android/lowmemorykiller.c @@ -49,14 +49,9 @@ #include #include #include -#include -#include -#include -#include #define CREATE_TRACE_POINTS #include -#include "trace/lowmemorykiller.h" #include #ifdef CONFIG_HIGHMEM @@ -64,6 +59,13 @@ #else #define _ZONE ZONE_NORMAL #endif +#include +#include +#include +#include + +#define CREATE_TRACE_POINTS +#include "trace/lowmemorykiller.h" /* to enable lowmemorykiller */ static int enable_lmk = 1; @@ -767,6 +769,7 @@ static unsigned long lowmem_scan(struct shrinker *s, struct shrink_control *sc) lowmem_deathpending_timeout = jiffies + HZ; rem += selected_tasksize; + rcu_read_unlock(); /* give the system time to free up the memory */ msleep_interruptible(20); diff --git a/drivers/staging/fw-api/fw/htt.h b/drivers/staging/fw-api/fw/htt.h index 74102299d56f..63d8f785bb9f 100644 --- a/drivers/staging/fw-api/fw/htt.h +++ b/drivers/staging/fw-api/fw/htt.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2020 The Linux Foundation. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -195,9 +195,14 @@ * htt_tx_data_hdr_information * 3.73 Add channel pre-calibration data upload and download messages defs for * HTT_T2H_MSG_TYPE_CHAN_CALDATA and HTT_H2T_MSG_TYPE_CHAN_CALDATA + * 3.74 Add HTT_T2H_MSG_TYPE_RX_FISA_CFG msg. + * 3.75 Add fp_ndp and mo_ndp flags in HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG. + * 3.76 Add HTT_H2T_MSG_TYPE_3_TUPLE_HASH_CFG msg. + * 3.77 Add HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE msg. + * 3.78 Add htt_ppdu_id def. */ #define HTT_CURRENT_VERSION_MAJOR 3 -#define HTT_CURRENT_VERSION_MINOR 73 +#define HTT_CURRENT_VERSION_MINOR 78 #define HTT_NUM_TX_FRAG_DESC 1024 @@ -539,6 +544,9 @@ enum htt_h2t_msg_type { HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG = 0x12, HTT_H2T_MSG_TYPE_RX_FSE_OPERATION_CFG = 0x13, HTT_H2T_MSG_TYPE_CHAN_CALDATA = 0x14, + HTT_H2T_MSG_TYPE_RX_FISA_CFG = 0x15, + HTT_H2T_MSG_TYPE_3_TUPLE_HASH_CFG = 0x16, + HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE = 0x17, /* keep this last */ HTT_H2T_NUM_MSGS @@ -2223,6 +2231,7 @@ typedef enum { HTT_TX_FW2WBM_REINJECT_REASON_MCAST, HTT_TX_FW2WBM_REINJECT_REASON_ARP, HTT_TX_FW2WBM_REINJECT_REASON_DHCP, + HTT_TX_FW2WBM_REINJECT_REASON_FLOW_CONTROL, HTT_TX_FW2WBM_REINJECT_REASON_MAX, } htt_tx_fw2wbm_reinject_reason_t; @@ -4818,8 +4827,8 @@ enum htt_srng_ring_id { * * The message would appear as follows: * - * |31 28|27|26|25|24|23 16|15 |9 8|7 0| - * |-----+--+--+--+--+----------------+------------+---+---------------| + * |31 28|27|26|25|24|23 16|15 | 11| 10|9 8|7 0| + * |-----+--+--+--+--+----------------+----+---+---+---+---------------| * |rsvd1|DT|OV|PS|SS| ring_id | pdev_id | msg_type | * |-------------------------------------------------------------------| * | rsvd2 | ring_buffer_size | @@ -4842,7 +4851,8 @@ enum htt_srng_ring_id { * |-------------------------------------------------------------------| * | rsvd3 | rx_attention_offset | * |-------------------------------------------------------------------| - * | rsvd4 | rx_drop_threshold | + * | rsvd4 | mo| fp| rx_drop_threshold | + * | |ndp|ndp| | * |-------------------------------------------------------------------| * Where: * PS = pkt_swap @@ -4936,6 +4946,10 @@ enum htt_srng_ring_id { * to source rings. Consumer drops packets if the available * words in the ring falls below the configured threshold * value. + * - b'10 - fp_ndp: Flag to indicate FP NDP status tlv is subscribed + * by host. 1 -> subscribed + * - b`11 - mo_ndp: Flag to indicate MO NDP status tlv is subscribed + * by host. 1 -> subscribed */ PREPACK struct htt_rx_ring_selection_cfg_t { A_UINT32 msg_type: 8, @@ -4962,7 +4976,9 @@ PREPACK struct htt_rx_ring_selection_cfg_t { A_UINT32 rx_attn_offset: 16, rsvd3: 16; A_UINT32 rx_drop_threshold: 10, - rsvd4: 22; + fp_ndp: 1, + mo_ndp: 1, + rsvd4: 20; } POSTPACK; #define HTT_RX_RING_SELECTION_CFG_SZ (sizeof(struct htt_rx_ring_selection_cfg_t)) @@ -5187,6 +5203,29 @@ PREPACK struct htt_rx_ring_selection_cfg_t { ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_RX_DROP_THRESHOLD_S)); \ } while (0) +#define HTT_RX_RING_SELECTION_CFG_FP_NDP_M 0x00000400 +#define HTT_RX_RING_SELECTION_CFG_FP_NDP_S 10 +#define HTT_RX_RING_SELECTION_CFG_FP_NDP_GET(_var) \ + (((_var) & HTT_RX_RING_SELECTION_CFG_FP_NDP_M) >> \ + HTT_RX_RING_SELECTION_CFG_FP_NDP_S) +#define HTT_RX_RING_SELECTION_CFG_FP_NDP_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_FP_NDP, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_FP_NDP_S)); \ + } while (0) + +#define HTT_RX_RING_SELECTION_CFG_MO_NDP_M 0x00000800 +#define HTT_RX_RING_SELECTION_CFG_MO_NDP_S 11 +#define HTT_RX_RING_SELECTION_CFG_MO_NDP_GET(_var) \ + (((_var) & HTT_RX_RING_SELECTION_CFG_MO_NDP_M) >> \ + HTT_RX_RING_SELECTION_CFG_MO_NDP_S) +#define HTT_RX_RING_SELECTION_CFG_MO_NDP_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_RING_SELECTION_CFG_MO_NDP, _val); \ + ((_var) |= ((_val) << HTT_RX_RING_SELECTION_CFG_MO_NDP_S)); \ + } while (0) + + /* * Subtype based MGMT frames enable bits. * FP: Filter_Pass, MD: Monitor_Direct MO: Monitor_Other @@ -5925,6 +5964,310 @@ enum htt_ip_da_sa_prefix { HTT_RX_IPV6_64FF9B, }; + +/** + * @brief Host-->target HTT RX FISA configure and enable + * @details + * The host will send this command down to configure and enable the FISA + * operational params. + * Configure RXOLE_RXOLE_R0_FISA_CTRL and RXOLE_RXOLE_R0_FISA_TIMEOUT_THRESH + * register. + * Should configure both the MACs. + * + * dword0 - b'7:0 - msg_type: This will be set to HTT_H2T_MSG_TYPE_RX_FISA_CFG + * + * b'15:8 - pdev_id: 0 indicates msg is for all LMAC rings, i.e. soc + * 1, 2, 3 indicates pdev_id 0,1,2 and the msg is for that + * pdev's LMAC ring. + * b'31:16 - reserved : Reserved for future use + * + * dword1 - b'0 - enable: Global FISA Enable, 0-FISA Disable, 1-Enable + * b'1 - IPSEC_SKIP_SEARCH: Flow search will be skipped for IP_SEC + * packets. 1 flow search will be skipped + * b'2 - NON_TCP_SKIP_SEARCH: Flow search will be skipped for Non + * tcp,udp packets + * b'3 - ADD_IPV4_FIXED_HDR_LEN: Add IPV4 Fixed HDR to length + * calculation + * b'4 - ADD_IPV6_FIXED_HDR_LEN: Add IPV6 Fixed HDR to length + * calculation + * b'5 - ADD_TCP_FIXED_HDR_LEN: Add TCP Fixed HDR to length + * calculation + * b'6 - ADD_UDP_HDR_LEN: Add UDP HDR to length calculation + * b'7 - CHKSUM_CUM_IP_LEN_EN: IPV4 hdr Checksum over cumulative IP + * length + * 0 L4 checksum will be provided in the RX_MSDU_END tlv + * 1 IPV4 hdr checksum after adjusting for cumulative IP + * length + * b'8 - DISABLE_TID_CHECK: 1- Disable TID check for MPDU Sequence + * num jump + * b'9 - DISABLE_TA_CHECK: 1- Disable TA check for MPDU Sequence + * num jump + * b'10 - DISABLE_QOS_CHECK: 1- Disable checking if qos/nonqos + * data type switch has happend for MPDU Sequence num jump + * b'11 - DISABLE_RAW_CHECK: 1- Disable checking for raw packet type + * for MPDU Sequence num jump + * b'12 - DISABLE_DECRYPT_ERR_CHECK: 1- Disable fisa cache commands + * for decrypt errors + * b'13 - DISABLE_MSDU_DROP_CHECK: 1- Ignore checking of msdu drop + * while aggregating a msdu + * b'17:14 - LIMIT, Aggregtion limit for number of MSDUs. + * The aggregation is done until (number of MSDUs aggregated + * < LIMIT + 1) + * b'31:18 - Reserved + * + * fisa_control_value - 32bit value FW can write to register + * + * dword2 - b'31:0 - FISA_TIMEOUT_THRESH, Timeout threshold for aggregation + * Threshold value for FISA timeout (units are microseconds). + * When the global timestamp exceeds this threshold, FISA + * aggregation will be restarted. + * A value of 0 means timeout is disabled. + * Compare the threshold register with timestamp field in + * flow entry to generate timeout for the flow. + * + * |31 18 |17 16|15 8|7 0| + * |-------------------------------------------------------------| + * | reserved | pdev_mask | msg type | + * |-------------------------------------------------------------| + * | reserved | FISA_CTRL | + * |-------------------------------------------------------------| + * | FISA_TIMEOUT_THRESH | + * |-------------------------------------------------------------| + */ +PREPACK struct htt_h2t_msg_type_fisa_config_t { + A_UINT32 msg_type:8, + pdev_id:8, + reserved0:16; + + /** + * @brief fisa_control - RXOLE_RXOLE_R0_FISA_CTRL FISA control register + * [17:0] + */ + union { + struct { + A_UINT32 fisa_enable: 1, + ipsec_skip_search: 1, + nontcp_skip_search: 1, + add_ipv4_fixed_hdr_len: 1, + add_ipv6_fixed_hdr_len: 1, + add_tcp_fixed_hdr_len: 1, + add_udp_hdr_len: 1, + chksum_cum_ip_len_en: 1, + disable_tid_check: 1, + disable_ta_check: 1, + disable_qos_check: 1, + disable_raw_check: 1, + disable_decrypt_err_check: 1, + disable_msdu_drop_check: 1, + fisa_aggr_limit: 4, + reserved: 14; + } fisa_control_bits; + + A_UINT32 fisa_control_value; + } u_fisa_control; + + /** + * @brief fisa_timeout_threshold - RXOLE_RXOLE_R0_FISA_TIMEOUT_THRESH FISA + * timeout threshold for aggregation. Unit in usec. + * [31:0] + */ + A_UINT32 fisa_timeout_threshold; +} POSTPACK; + + +/* DWord 0: pdev-ID */ +#define HTT_RX_FISA_CONFIG_PDEV_ID_M 0x0000ff00 +#define HTT_RX_FISA_CONFIG_PDEV_ID_S 8 +#define HTT_RX_FISA_CONFIG_PDEV_ID_GET(_var) \ + (((_var) & HTT_RX_FISA_CONFIG_PDEV_ID_M) >> \ + HTT_RX_FISA_CONFIG_PDEV_ID_S) +#define HTT_RX_FISA_CONFIG_PDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_PDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_PDEV_ID_S)); \ + } while (0) + +/* Dword 1: fisa_control_value fisa config */ +#define HTT_RX_FISA_CONFIG_FISA_ENABLE_M 0x00000001 +#define HTT_RX_FISA_CONFIG_FISA_ENABLE_S 0 +#define HTT_RX_FISA_CONFIG_FISA_ENABLE_GET(_var) \ + (((_var) & HTT_RX_FISA_CONFIG_FISA_ENABLE_M) >> \ + HTT_RX_FISA_CONFIG_FISA_ENABLE_S) +#define HTT_RX_FISA_CONFIG_FISA_ENABLE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_FISA_ENABLE, _val); \ + ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_FISA_ENABLE_S)); \ + } while (0) + +/* Dword 1: fisa_control_value ipsec_skip_search */ +#define HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_M 0x00000002 +#define HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_S 1 +#define HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_GET(_var) \ + (((_var) & HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_M) >> \ + HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_S) +#define HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH, _val); \ + ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_IPSEC_SKIP_SEARCH_S)); \ + } while (0) + +/* Dword 1: fisa_control_value non_tcp_skip_search */ +#define HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_M 0x00000004 +#define HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_S 2 +#define HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_GET(_var) \ + (((_var) & HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_M) >> \ + HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_S) +#define HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH, _val); \ + ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_NON_TCP_SKIP_SEARCH_S)); \ + } while (0) + +/* Dword 1: fisa_control_value add_ipv4_fixed_hdr */ +#define HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_M 0x00000008 +#define HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_S 3 +#define HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_GET(_var) \ + (((_var) & HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_M) >> \ + HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_S) +#define HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN, _val); \ + ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_ADD_IPV4_FIXED_HDR_LEN_S)); \ + } while (0) + +/* Dword 1: fisa_control_value add_ipv6_fixed_hdr */ +#define HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_M 0x00000010 +#define HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_S 4 +#define HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_GET(_var) \ + (((_var) & HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_M) >> \ + HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_S) +#define HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN, _val); \ + ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_ADD_IPV6_FIXED_HDR_LEN_S)); \ + } while (0) + +/* Dword 1: fisa_control_value tcp_fixed_hdr_len */ +#define HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_M 0x00000020 +#define HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_S 5 +#define HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_GET(_var) \ + (((_var) & HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_M) >> \ + HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_S) +#define HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN, _val); \ + ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_ADD_TCP_FIXED_HDR_LEN_S)); \ + } while (0) + +/* Dword 1: fisa_control_value add_udp_hdr_len */ +#define HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_M 0x00000040 +#define HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_S 6 +#define HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_GET(_var) \ + (((_var) & HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_M) >> \ + HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_S) +#define HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN, _val); \ + ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_ADD_UDP_HDR_LEN_S)); \ + } while (0) + +/* Dword 1: fisa_control_value chksum_cum_ip_len_en */ +#define HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_M 0x00000080 +#define HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_S 7 +#define HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_GET(_var) \ + (((_var) & HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_M) >> \ + HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_S) +#define HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN, _val); \ + ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_CHKSUM_CUM_IP_LEN_EN_S)); \ + } while (0) + +/* Dword 1: fisa_control_value disable_tid_check */ +#define HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_M 0x00000100 +#define HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_S 8 +#define HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_GET(_var) \ + (((_var) & HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_M) >> \ + HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_S) +#define HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK, _val); \ + ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_TID_CHECK_S)); \ + } while (0) + +/* Dword 1: fisa_control_value disable_ta_check */ +#define HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_M 0x00000200 +#define HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_S 9 +#define HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_GET(_var) \ + (((_var) & HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_M) >> \ + HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_S) +#define HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK, _val); \ + ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_TA_CHECK_S)); \ + } while (0) + +/* Dword 1: fisa_control_value disable_qos_check */ +#define HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_M 0x00000400 +#define HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_S 10 +#define HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_GET(_var) \ + (((_var) & HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_M) >> \ + HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_S) +#define HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK, _val); \ + ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_QOS_CHECK_S)); \ + } while (0) + +/* Dword 1: fisa_control_value disable_raw_check */ +#define HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_M 0x00000800 +#define HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_S 11 +#define HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_GET(_var) \ + (((_var) & HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_M) >> \ + HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_S) +#define HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK, _val); \ + ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_RAW_CHECK_S)); \ + } while (0) + +/* Dword 1: fisa_control_value disable_decrypt_err_check */ +#define HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_M 0x00001000 +#define HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_S 12 +#define HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_GET(_var) \ + (((_var) & HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_M) >> \ + HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_S) +#define HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK, _val); \ + ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_DECRYPT_ERR_CHECK_S)); \ + } while (0) + +/* Dword 1: fisa_control_value disable_msdu_drop_check */ +#define HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_M 0x00002000 +#define HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_S 13 +#define HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_GET(_var) \ + (((_var) & HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_M) >> \ + HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_S) +#define HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK, _val); \ + ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_DISABLE_MSDU_DROP_CHECK_S)); \ + } while (0) + +/* Dword 1: fisa_control_value fisa_aggr_limit */ +#define HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_M 0x0003c000 +#define HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_S 14 +#define HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_GET(_var) \ + (((_var) & HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_M) >> \ + HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_S) +#define HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT, _val); \ + ((_var) |= ((_val) << HTT_RX_FISA_CONFIG_FISA_AGGR_LIMIT_S)); \ + } while (0) + + PREPACK struct htt_h2t_msg_rx_fse_setup_t { A_UINT32 msg_type:8, /* HTT_H2T_MSG_TYPE_RX_FSE_SETUP_CFG */ pdev_id:8, @@ -5950,6 +6293,7 @@ PREPACK struct htt_h2t_msg_rx_fse_setup_t { #define HTT_RX_FSE_SETUP_SZ (sizeof(struct htt_h2t_msg_rx_fse_setup_t)) #define HTT_RX_FSE_OPERATION_SZ (sizeof(struct htt_h2t_msg_rx_fse_operation_t)) +#define HTT_RX_FISA_CONFIG_SZ (sizeof(struct htt_h2t_msg_type_fisa_config_t)) #define HTT_RX_FSE_SETUP_HASH_314_288_M 0x07ffffff #define HTT_RX_FSE_SETUP_HASH_314_288_S 0 @@ -6171,6 +6515,135 @@ PREPACK struct htt_h2t_msg_rx_fse_operation_t { reserved:24; } POSTPACK; +/** + * @brief Host-->target HTT RX Full monitor mode register configuration message + * @details + * The host will send this Full monitor mode register configuration message. + * This message can be sent per SOC or per PDEV which is differentiated + * by pdev id values. + * + * |31 16|15 11|10 8|7 3|2|1|0| + * |-------------------------------------------------------------| + * | reserved | pdev_id | MSG_TYPE | + * |-------------------------------------------------------------| + * | reserved |Release Ring |N|Z|E| + * |-------------------------------------------------------------| + * + * where E is 1-bit full monitor mode enable/disable. + * Z is 1-bit additional descriptor for zero mpdu enable/disable + * N is 1-bit additional descriptor for non zero mdpu enable/disable + * + * The following field definitions describe the format of the full monitor + * mode configuration message sent from the host to target for each pdev. + * + * Header fields: + * dword0 - b'7:0 - msg_type: This will be set to + * HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE. + * b'15:8 - pdev_id: 0 indicates msg is for all LMAC rings, i.e. soc + * 1, 2, 3 indicates pdev_id 0,1,2 and the msg is for the + * specified pdev's LMAC ring. + * b'31:16 - reserved : Reserved for future use. + * dword1 - b'0 - full_monitor_mode enable: This indicates that the full + * monitor mode rxdma register is to be enabled or disabled. + * b'1 - addnl_descs_zero_mpdus_end: This indicates that the + * additional descriptors at ppdu end for zero mpdus + * enabled or disabled. + * b'2 - addnl_descs_non_zero_mpdus_end: This indicates that the + * additional descriptors at ppdu end for non zero mpdus + * enabled or disabled. + * b'10:3 - release_ring: This indicates the destination ring + * selection for the descriptor at the end of PPDU + * 0 - REO ring select + * 1 - FW ring select + * 2 - SW ring select + * 3 - Release ring select + * Refer to htt_rx_full_mon_release_ring. + * b'31:11 - reserved for future use + */ +PREPACK struct htt_h2t_msg_rx_full_monitor_mode_t { + A_UINT32 msg_type:8, + pdev_id:8, + reserved0:16; + A_UINT32 full_monitor_mode_enable:1, + addnl_descs_zero_mpdus_end:1, + addnl_descs_non_zero_mpdus_end:1, + release_ring:8, + reserved1:21; +} POSTPACK; + +/** + * Enumeration for full monitor mode destination ring select + * 0 - REO destination ring select + * 1 - FW destination ring select + * 2 - SW destination ring select + * 3 - Release destination ring select + */ +enum htt_rx_full_mon_release_ring { + HTT_RX_MON_RING_REO, + HTT_RX_MON_RING_FW, + HTT_RX_MON_RING_SW, + HTT_RX_MON_RING_RELEASE, +}; + +#define HTT_RX_FULL_MONITOR_MODE_SETUP_SZ (sizeof(struct htt_h2t_msg_rx_full_monitor_mode_t)) +/* DWORD 0: Pdev ID */ +#define HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_M 0x0000ff00 +#define HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_S 8 +#define HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_GET(_var) \ + (((_var) & HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_M) >> \ + HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_S) +#define HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_RX_FULL_MONITOR_MODE_OPERATION_PDEV_ID_S)); \ + } while (0) + +/* DWORD 1:ENABLE */ +#define HTT_RX_FULL_MONITOR_MODE_ENABLE_M 0x00000001 +#define HTT_RX_FULL_MONITOR_MODE_ENABLE_S 0 + +#define HTT_RX_FULL_MONITOR_MODE_ENABLE_SET(word, enable) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_FULL_MONITOR_MODE_ENABLE, enable); \ + (word) |= ((enable) << HTT_RX_FULL_MONITOR_MODE_ENABLE_S); \ + } while (0) +#define HTT_RX_FULL_MONITOR_MODE_ENABLE_GET(word) \ + (((word) & HTT_RX_FULL_MONITOR_MODE_ENABLE_M) >> HTT_RX_FULL_MONITOR_MODE_ENABLE_S) + +/* DWORD 1:ZERO_MPDU */ +#define HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_M 0x00000002 +#define HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_S 1 +#define HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_SET(word, zerompdu) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU, zerompdu); \ + (word) |= ((zerompdu) << HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_S); \ + } while (0) +#define HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_GET(word) \ + (((word) & HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_M) >> HTT_RX_FULL_MONITOR_MODE_ZERO_MPDU_S) + + +/* DWORD 1:NON_ZERO_MPDU */ +#define HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_M 0x00000004 +#define HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_S 2 +#define HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_SET(word, nonzerompdu) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU, nonzerompdu); \ + (word) |= ((nonzerompdu) << HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_S); \ + } while (0) +#define HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_GET(word) \ + (((word) & HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_M) >> HTT_RX_FULL_MONITOR_MODE_NON_ZERO_MPDU_S) + +/* DWORD 1:RELEASE_RINGS */ +#define HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_M 0x000007f8 +#define HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_S 3 +#define HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_SET(word, releaserings) \ + do { \ + HTT_CHECK_SET_VAL(HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS, releaserings); \ + (word) |= ((releaserings) << HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_S); \ + } while (0) +#define HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_GET(word) \ + (((word) & HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_M) >> HTT_RX_FULL_MONITOR_MODE_RELEASE_RINGS_S) + /** * Enumeration for IP Protocol or IPSEC Protocol * IPsec describes the framework for providing security at IP layer. @@ -6295,6 +6768,98 @@ enum htt_rx_fse_operation { (((word) & HTT_RX_FSE_L4_PROTO_M) >> HTT_RX_FSE_L4_PROTO_S) +/** + * @brief HTT_H2T_MSG_TYPE_3_TUPLE_HASH_CFG + * host --> target Receive to configure the RxOLE 3-tuple Hash + * + * |31 24|23 |15 8|7 2|1|0| + * |----------------+----------------+----------------+----------------| + * | reserved | pdev_id | msg_type | + * |---------------------------------+----------------+----------------| + * | reserved |E|F| + * |---------------------------------+----------------+----------------| + * Where E = Configure the target to provide the 3-tuple hash value in + * toeplitz_hash_2_or_4 field of rx_msdu_start tlv + * F = Configure the target to provide the 3-tuple hash value in + * flow_id_toeplitz field of rx_msdu_start tlv + * + * The following field definitions describe the format of the 3 tuple hash value + * message sent from the host to target as part of initialization sequence. + * + * Header fields: + * dword0 - b'7:0 - msg_type: This will be set to + * HTT_H2T_MSG_TYPE_3_TUPLE_HASH_CFG + * b'15:8 - pdev_id: 0 indicates msg is for all LMAC rings, i.e. soc + * 1, 2, 3 indicates pdev_id 0,1,2 and the msg is for the + * specified pdev's LMAC ring. + * b'31:16 - reserved : Reserved for future use + * dword1 - b'0 - flow_id_toeplitz_field_enable + * b'1 - toeplitz_hash_2_or_4_field_enable + * b'31:2 - reserved : Reserved for future use + * ---------+------+---------------------------------------------------------- + * bit1 | bit0 | Functionality + * ---------+------+---------------------------------------------------------- + * 0 | 1 | Configure the target to provide the 3 tuple hash value + * | | in flow_id_toeplitz field + * ---------+------+---------------------------------------------------------- + * 1 | 0 | Configure the target to provide the 3 tuple hash value + * | | in toeplitz_hash_2_or_4 field + * ---------+------+---------------------------------------------------------- + * 1 | 1 | Configure the target to provide the 3 tuple hash value + * | | in both flow_id_toeplitz & toeplitz_hash_2_or_4 field + * ---------+------+---------------------------------------------------------- + * 0 | 0 | Configure the target to provide the 5 tuple hash value + * | | in flow_id_toeplitz field 2 or 4 tuple has value in + * | | toeplitz_hash_2_or_4 field + *---------------------------------------------------------------------------- + */ +PREPACK struct htt_h2t_msg_rx_3_tuple_hash_cfg_t { + A_UINT32 msg_type :8, + pdev_id :8, + reserved0 :16; + A_UINT32 flow_id_toeplitz_field_enable :1, + toeplitz_hash_2_or_4_field_enable :1, + reserved1 :30; +} POSTPACK; + +/* DWORD0 : pdev_id configuration Macros */ +#define HTT_H2T_3_TUPLE_HASH_PDEV_ID_M 0xff00 +#define HTT_H2T_3_TUPLE_HASH_PDEV_ID_S 8 +#define HTT_RX_3_TUPLE_HASH_PDEV_ID_GET(_var) \ + (((_var) & HTT_H2T_3_TUPLE_HASH_PDEV_ID_M) >> \ + HTT_H2T_3_TUPLE_HASH_PDEV_ID_S) +#define HTT_RX_3_TUPLE_HASH_PDEV_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_3_TUPLE_HASH_PDEV_ID, _val); \ + ((_var) |= ((_val) << HTT_H2T_3_TUPLE_HASH_PDEV_ID_S)); \ + } while (0) + +/* DWORD1: rx 3 tuple hash value reception field configuration Macros */ +#define HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG_M 0x1 +#define HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG_S 0 +#define HTT_FLOW_ID_TOEPLITZ_FIELD_CONFIG_GET(_var) \ + (((_var) & HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG_M) >> \ + HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG_S) +#define HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG, _val); \ + ((_var) |= ((_val) << HTT_H2T_FLOW_ID_TOEPLITZ_FIELD_CONFIG_S)); \ + } while (0) + +#define HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG_M 0x2 +#define HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG_S 1 +#define HTT_TOEPLITZ_2_OR_4_FIELD_CONFIG_GET(_var) \ + (((_var) & HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG_M) >> \ + HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG_S) +#define HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG, _val); \ + ((_var) |= ((_val) << HTT_H2T_TOEPLITZ_2_OR_4_FIELD_CONFIG_S)); \ + } while (0) + +#define HTT_3_TUPLE_HASH_CFG_REQ_BYTES 8 + + /*=== target -> host messages ===============================================*/ @@ -13437,4 +14002,117 @@ PREPACK struct htt_chan_caldata_msg { ((_var) |= ((_val) << HTT_CHAN_CALDATA_MSG_FREQ2_S)); \ } while (0) + +/** + * @brief - HTT PPDU ID format + * + * @details + * The following field definitions describe the format of the PPDU ID. + * The PPDU ID is truncated to 24 bits for TLVs from TQM. + * + * |31 30|29 24| 23| 22|21 19|18 17|16 12|11 0| + * +--------------------------------------------------------------------------- + * |rsvd |seq_cmd_type|tqm_cmd| rsvd |seq_idx|mac_id| hwq_ id | sch id | + * +--------------------------------------------------------------------------- + * + * sch id :Schedule command id + * Bits [11 : 0] : monotonically increasing counter to track the + * PPDU posted to a specific transmit queue. + * + * hwq_id: Hardware Queue ID. + * Bits [16 : 12] : Indicates the queue id in the hardware transmit queue. + * + * mac_id: MAC ID + * Bits [18 : 17] : LMAC ID obtained from the whal_mac_struct + * + * seq_idx: Sequence index. + * Bits [21 : 19] : Sequence index indicates all the PPDU belonging to + * a particular TXOP. + * + * tqm_cmd: HWSCH/TQM flag. + * Bit [23] : Always set to 0. + * + * seq_cmd_type: Sequence command type. + * Bit [29 : 24] : Indicates the frame type for the current sequence. + * Refer to enum HTT_STATS_FTYPE for values. + */ +PREPACK struct htt_ppdu_id { + A_UINT32 + sch_id: 12, + hwq_id: 5, + mac_id: 2, + seq_idx: 3, + reserved1: 1, + tqm_cmd: 1, + seq_cmd_type: 6, + reserved2: 2; +} POSTPACK; + +#define HTT_PPDU_ID_SCH_ID_S 0 +#define HTT_PPDU_ID_SCH_ID_M 0x00000fff +#define HTT_PPDU_ID_SCH_ID_GET(_var) \ + (((_var) & HTT_PPDU_ID_SCH_ID_M) >> HTT_PPDU_ID_SCH_ID_S) + +#define HTT_PPDU_ID_SCH_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PPDU_ID_SCH_ID, _val); \ + ((_var) |= ((_val) << HTT_PPDU_ID_SCH_ID_S)); \ + } while (0) + +#define HTT_PPDU_ID_HWQ_ID_S 12 +#define HTT_PPDU_ID_HWQ_ID_M 0x0001f000 +#define HTT_PPDU_ID_HWQ_ID_GET(_var) \ + (((_var) & HTT_PPDU_ID_HWQ_ID_M) >> HTT_PPDU_ID_HWQ_ID_S) + +#define HTT_PPDU_ID_HWQ_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PPDU_ID_HWQ_ID, _val); \ + ((_var) |= ((_val) << HTT_PPDU_ID_HWQ_ID_S)); \ + } while (0) + +#define HTT_PPDU_ID_MAC_ID_S 17 +#define HTT_PPDU_ID_MAC_ID_M 0x00060000 +#define HTT_PPDU_ID_MAC_ID_GET(_var) \ + (((_var) & HTT_PPDU_ID_MAC_ID_M) >> HTT_PPDU_ID_MAC_ID_S) + +#define HTT_PPDU_ID_MAC_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PPDU_ID_MAC_ID, _val); \ + ((_var) |= ((_val) << HTT_PPDU_ID_MAC_ID_S)); \ + } while (0) + +#define HTT_PPDU_ID_SEQ_IDX_S 19 +#define HTT_PPDU_ID_SEQ_IDX_M 0x00380000 +#define HTT_PPDU_ID_SEQ_IDX_GET(_var) \ + (((_var) & HTT_PPDU_ID_SEQ_IDX_M) >> HTT_PPDU_ID_SEQ_IDX_S) + +#define HTT_PPDU_ID_SEQ_IDX_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PPDU_ID_SEQ_IDX, _val); \ + ((_var) |= ((_val) << HTT_PPDU_ID_SEQ_IDX_S)); \ + } while (0) + +#define HTT_PPDU_ID_TQM_CMD_S 23 +#define HTT_PPDU_ID_TQM_CMD_M 0x00800000 +#define HTT_PPDU_ID_TQM_CMD_GET(_var) \ + (((_var) & HTT_PPDU_ID_TQM_CMD_M) >> HTT_PPDU_ID_TQM_CMD_S) + +#define HTT_PPDU_ID_TQM_CMD_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PPDU_ID_TQM_CMD, _val); \ + ((_var) |= ((_val) << HTT_PPDU_ID_TQM_CMD_S)); \ + } while (0) + +#define HTT_PPDU_ID_SEQ_CMD_TYPE_S 24 +#define HTT_PPDU_ID_SEQ_CMD_TYPE_M 0x3f000000 +#define HTT_PPDU_ID_SEQ_CMD_TYPE_GET(_var) \ + (((_var) & HTT_PPDU_ID_SEQ_CMD_TYPE_M) >> HTT_PPDU_ID_SEQ_CMD_TYPE_S) + +#define HTT_PPDU_ID_SEQ_CMD_TYPE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PPDU_ID_SEQ_CMD_TYPE, _val); \ + ((_var) |= ((_val) << HTT_PPDU_ID_SEQ_CMD_TYPE_S)); \ + } while (0) + + #endif diff --git a/drivers/staging/fw-api/fw/htt_ppdu_stats.h b/drivers/staging/fw-api/fw/htt_ppdu_stats.h index 253a534ba836..a02e7ade062b 100644 --- a/drivers/staging/fw-api/fw/htt_ppdu_stats.h +++ b/drivers/staging/fw-api/fw/htt_ppdu_stats.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -32,20 +32,21 @@ #define HTT_BA_64_BIT_MAP_SIZE_DWORDS 2 #define HTT_BA_256_BIT_MAP_SIZE_DWORDS 8 enum htt_ppdu_stats_tlv_tag { - HTT_PPDU_STATS_COMMON_TLV, - HTT_PPDU_STATS_USR_COMMON_TLV, - HTT_PPDU_STATS_USR_RATE_TLV, - HTT_PPDU_STATS_USR_MPDU_ENQ_BITMAP_64_TLV, - HTT_PPDU_STATS_USR_MPDU_ENQ_BITMAP_256_TLV, - HTT_PPDU_STATS_SCH_CMD_STATUS_TLV, - HTT_PPDU_STATS_USR_COMPLTN_COMMON_TLV, - HTT_PPDU_STATS_USR_COMPLTN_BA_BITMAP_64_TLV, - HTT_PPDU_STATS_USR_COMPLTN_BA_BITMAP_256_TLV, - HTT_PPDU_STATS_USR_COMPLTN_ACK_BA_STATUS_TLV, - HTT_PPDU_STATS_USR_COMPLTN_FLUSH_TLV, - HTT_PPDU_STATS_USR_COMMON_ARRAY_TLV, - HTT_PPDU_STATS_INFO_TLV, - HTT_PPDU_STATS_TX_MGMTCTRL_PAYLOAD_TLV, + HTT_PPDU_STATS_COMMON_TLV, /* htt_ppdu_stats_common_tlv */ + HTT_PPDU_STATS_USR_COMMON_TLV, /* htt_ppdu_stats_user_common_tlv */ + HTT_PPDU_STATS_USR_RATE_TLV, /* htt_ppdu_stats_user_rate_tlv */ + HTT_PPDU_STATS_USR_MPDU_ENQ_BITMAP_64_TLV, /* htt_ppdu_stats_enq_mpdu_bitmap_64_tlv */ + HTT_PPDU_STATS_USR_MPDU_ENQ_BITMAP_256_TLV, /* htt_ppdu_stats_enq_mpdu_bitmap_256_tlv */ + HTT_PPDU_STATS_SCH_CMD_STATUS_TLV, /* htt_ppdu_stats_sch_cmd_tlv_v */ + HTT_PPDU_STATS_USR_COMPLTN_COMMON_TLV, /* htt_ppdu_stats_user_cmpltn_common_tlv */ + HTT_PPDU_STATS_USR_COMPLTN_BA_BITMAP_64_TLV, /* htt_ppdu_stats_user_cmpltn_ba_bitmap_64_tlv */ + HTT_PPDU_STATS_USR_COMPLTN_BA_BITMAP_256_TLV, /* htt_ppdu_stats_user_cmpltn_ba_bitmap_256_tlv */ + HTT_PPDU_STATS_USR_COMPLTN_ACK_BA_STATUS_TLV, /* htt_ppdu_stats_user_cmpltn_ack_ba_status_tlv */ + HTT_PPDU_STATS_USR_COMPLTN_FLUSH_TLV, /* htt_ppdu_stats_flush_tlv */ + HTT_PPDU_STATS_USR_COMMON_ARRAY_TLV, /* htt_ppdu_stats_usr_common_array_tlv_v */ + HTT_PPDU_STATS_INFO_TLV, /* htt_ppdu_stats_info */ + HTT_PPDU_STATS_TX_MGMTCTRL_PAYLOAD_TLV, /* htt_ppdu_stats_tx_mgmtctrl_payload_tlv */ + HTT_PPDU_STATS_USERS_INFO_TLV, /* htt_ppdu_stats_users_info_tlv */ /* New TLV's are added above to this line */ HTT_PPDU_STATS_MAX_TAG, @@ -412,6 +413,19 @@ enum HTT_PPDU_STATS_BW { }; typedef enum HTT_PPDU_STATS_BW HTT_PPDU_STATS_BW; +#define HTT_PPDU_STATS_COMMON_TLV_BW_M 0x000f0000 +#define HTT_PPDU_STATS_COMMON_TLV_BW_S 16 + +#define HTT_PPDU_STATS_COMMON_TLV_BW_GET(_var) \ + (((_var) & HTT_PPDU_STATS_COMMON_TLV_BW_M) >> \ + HTT_PPDU_STATS_COMMON_TLV_BW_S) + +#define HTT_PPDU_STATS_COMMON_TLV_BW_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PPDU_STATS_COMMON_TLV_BW, _val); \ + ((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_BW_S)); \ + } while (0) + enum HTT_PPDU_STATS_SEQ_TYPE { HTT_SEQTYPE_UNSPECIFIED = 0, HTT_SEQTYPE_SU = 1, @@ -426,8 +440,8 @@ enum HTT_PPDU_STATS_SEQ_TYPE { }; typedef enum HTT_PPDU_STATS_SEQ_TYPE HTT_PPDU_STATS_SEQ_TYPE; -#define HTT_PPDU_STATS_COMMON_TLV_PPDU_SEQ_TYPE_M 0x00ff0000 -#define HTT_PPDU_STATS_COMMON_TLV_PPDU_SEQ_TYPE_S 16 +#define HTT_PPDU_STATS_COMMON_TLV_PPDU_SEQ_TYPE_M 0x0ff00000 +#define HTT_PPDU_STATS_COMMON_TLV_PPDU_SEQ_TYPE_S 20 #define HTT_PPDU_STATS_COMMON_TLV_PPDU_SEQ_TYPE_GET(_var) \ (((_var) & HTT_PPDU_STATS_COMMON_TLV_PPDU_SEQ_TYPE_M) >> \ @@ -439,17 +453,22 @@ typedef enum HTT_PPDU_STATS_SEQ_TYPE HTT_PPDU_STATS_SEQ_TYPE; ((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_PPDU_SEQ_TYPE_S)); \ } while (0) -#define HTT_PPDU_STATS_COMMON_TLV_BW_M 0x000f0000 -#define HTT_PPDU_STATS_COMMON_TLV_BW_S 16 +/* + * MPROT_TYPE enum values: refer to enum + * pcu_ppdu_setup_init__medium_prot_type__e + * defined in tlv_enum.h + */ +#define HTT_PPDU_STATS_COMMON_TLV_MPROT_TYPE_M 0xf0000000 +#define HTT_PPDU_STATS_COMMON_TLV_MPROT_TYPE_S 28 -#define HTT_PPDU_STATS_COMMON_TLV_BW_GET(_var) \ - (((_var) & HTT_PPDU_STATS_COMMON_TLV_BW_M) >> \ - HTT_PPDU_STATS_COMMON_TLV_BW_S) +#define HTT_PPDU_STATS_COMMON_TLV_MPROT_TYPE_GET(_var) \ + (((_var) & HTT_PPDU_STATS_COMMON_TLV_MPROT_TYPE_M) >> \ + HTT_PPDU_STATS_COMMON_TLV_MPROT_TYPE_S) -#define HTT_PPDU_STATS_COMMON_TLV_BW_SET(_var, _val) \ +#define HTT_PPDU_STATS_COMMON_TLV_MPROT_TYPE_SET(_var, _val) \ do { \ - HTT_CHECK_SET_VAL(HTT_PPDU_STATS_COMMON_TLV_BW, _val); \ - ((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_BW_S)); \ + HTT_CHECK_SET_VAL(HTT_PPDU_STATS_COMMON_TLV_MPROT_TYPE, _val); \ + ((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_BW_S)); \ } while (0) #define HTT_PPDU_STATS_COMMON_TLV_PHY_MODE_M 0x0000ffff @@ -478,6 +497,93 @@ typedef enum HTT_PPDU_STATS_SEQ_TYPE HTT_PPDU_STATS_SEQ_TYPE; ((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_CHAN_MHZ_S)); \ } while (0) +#define HTT_PPDU_STATS_COMMON_TLV_PHY_PPDU_TX_TIME_US_M 0x0000ffff +#define HTT_PPDU_STATS_COMMON_TLV_PHY_PPDU_TX_TIME_US_S 0 + +#define HTT_PPDU_STATS_COMMON_TLV_PHY_PPDU_TX_TIME_US_GET(_var) \ + (((_var) & HTT_PPDU_STATS_COMMON_TLV_PHY_PPDU_TX_TIME_US_M) >> \ + HTT_PPDU_STATS_COMMON_TLV_PHY_PPDU_TX_TIME_US_S ) + +#define HTT_PPDU_STATS_COMMON_TLV_PHY_PPDU_TX_TIME_US_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PPDU_STATS_COMMON_TLV_PHY_PPDU_TX_TIME_US, _val); \ + ((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_PHY_PPDU_TX_TIME_US_S)); \ + } while (0) + +#define HTT_PPDU_STATS_COMMON_TLV_NUM_UL_EXPECTED_USERS_M 0x00ff0000 +#define HTT_PPDU_STATS_COMMON_TLV_NUM_UL_EXPECTED_USERS_S 16 + +#define HTT_PPDU_STATS_COMMON_TLV_NUM_UL_EXPECTED_USERS_GET(_var) \ + (((_var) & HTT_PPDU_STATS_COMMON_TLV_NUM_UL_EXPECTED_USERS_M) >> \ + HTT_PPDU_STATS_COMMON_TLV_NUM_UL_EXPECTED_USERS_S) + +#define HTT_PPDU_STATS_COMMON_TLV_NUM_UL_EXPECTED_USERS_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PPDU_STATS_COMMON_TLV_NUM_UL_EXPECTED_USERS, _val); \ + ((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_NUM_UL_EXPECTED_USERS_S)); \ + } while(0); + +#define HTT_PPDU_STATS_COMMON_TLV_BEAM_CHANGE_M 0x01000000 +#define HTT_PPDU_STATS_COMMON_TLV_BEAM_CHANGE_S 24 + +#define HTT_PPDU_STATS_COMMON_TLV_BEAM_CHANGE_GET(_var) \ + (((_var) & HTT_PPDU_STATS_COMMON_TLV_BEAM_CHANGE_M) >> \ + HTT_PPDU_STATS_COMMON_TLV_BEAM_CHANGE_S) + +#define HTT_PPDU_STATS_COMMON_TLV_BEAM_CHANGE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PPDU_STATS_COMMON_TLV_BEAM_CHANGE, _val); \ + ((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_BEAM_CHANGE_S)); \ + } while (0) + +#define HTT_PPDU_STATS_COMMON_TLV_DOPPLER_INDICATION_M 0x02000000 +#define HTT_PPDU_STATS_COMMON_TLV_DOPPLER_INDICATION_S 25 + +#define HTT_PPDU_STATS_COMMON_TLV_DOPPLER_INDICATION_GET(_var) \ + (((_var) & HTT_PPDU_STATS_COMMON_TLV_DOPPLER_INDICATION_M) >> \ + HTT_PPDU_STATS_COMMON_TLV_DOPPLER_INDICATION_S) + +#define HTT_PPDU_STATS_COMMON_TLV_DOPPLER_INDICATION_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PPDU_STATS_COMMON_TLV_DOPPLER_INDICATION, _val); \ + ((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_DOPPLER_INDICATION_S)); \ + } while (0) + +enum HTT_PPDU_STATS_SPATIAL_REUSE { + HTT_SRP_DISALLOW = 0, + /* values 1-12 are reserved */ + HTT_SR_RESTRICTED = 13, + HTT_SR_DELAY = 14, + HTT_SRP_AND_NON_SRG_OBSS_PD_PROHIBITED = 15, +}; +typedef enum HTT_PPDU_STATS_SPATIAL_REUSE HTT_PPDU_STATS_SPATIAL_REUSE; + +#define HTT_PPDU_STATS_COMMON_TLV_SPATIAL_REUSE_M 0x3c000000 +#define HTT_PPDU_STATS_COMMON_TLV_SPATIAL_REUSE_S 26 + +#define HTT_PPDU_STATS_COMMON_TLV_SPATIAL_REUSE_GET(_var) \ + (((_var) & HTT_PPDU_STATS_COMMON_TLV_SPATIAL_REUSE_M) >> \ + HTT_PPDU_STATS_COMMON_TLV_SPATIAL_REUSE_S) + +#define HTT_PPDU_STATS_COMMON_TLV_SPATIAL_REUSE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PPDU_STATS_COMMON_TLV_SPATIAL_REUSE, _val); \ + ((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_SPATIAL_REUSE_S)); \ + } while (0) + +#define HTT_PPDU_STATS_COMMON_TLV_BSS_COLOR_ID_M 0x0000003f +#define HTT_PPDU_STATS_COMMON_TLV_BSS_COLOR_ID_S 0 + +#define HTT_PPDU_STATS_COMMON_TLV_BSS_COLOR_ID_GET(_var) \ + (((_var) & HTT_PPDU_STATS_COMMON_TLV_BSS_COLOR_ID_M) >> \ + HTT_PPDU_STATS_COMMON_TLV_BSS_COLOR_ID_S) + +#define HTT_PPDU_STATS_COMMON_TLV_BSS_COLOR_ID_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PPDU_STATS_COMMON_TLV_BSS_COLOR_ID, _val); \ + ((_var) |= ((_val) << HTT_PPDU_STATS_COMMON_TLV_BSS_COLOR_ID_S)); \ + } while (0) + typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -498,17 +604,18 @@ typedef struct { * BIT [ 15: 8] :- queue_type - HTT_TX_QUEUE_TYPE * BIT [ 19: 16] :- bw - HTT_PPDU_STATS_BW * BIT [ 27: 20] :- ppdu_seq_type - HTT_PPDU_STATS_SEQ_TYPE - * BIT [ 31: 28] :- reserved + * BIT [ 31: 28] :- mprot_type */ union { A_UINT32 bw__queue_type__frame_type; A_UINT32 ppdu_seq_type__bw__queue_type__frame_type; + A_UINT32 mprot_type__ppdu_seq_type__bw__queue_type__frame_type; struct { A_UINT32 frame_type: 8, queue_type: 8, bw: 4, ppdu_seq_type: 8, - reserved0: 4; + mprot_type: 4; }; }; A_UINT32 chain_mask; @@ -562,6 +669,60 @@ typedef struct { * latency. */ A_UINT32 txfrm_delta_time_us; + + /* + * The phy_ppdu_tx_time_us reports the time it took to transmit + * a PPDU by itself + * BIT [15 : 0] - phy_ppdu_tx_time_us reports the time it took to + * transmit by itself (not including response time) + * BIT [23 : 16] - num_ul_expected_users reports the number of users + * that are expected to respond to this transmission + * BIT [24 : 24] - beam_change reports the beam forming pattern + * between non-HE and HE portion. + * If we apply TxBF starting from legacy preamble, + * then beam_change = 0. + * If we apply TxBF only starting from HE portion, + * then beam_change = 1. + * BIT [25 : 25] - doppler_indication + * BIT [29 : 26] - spatial_reuse for HE_SU,HE_MU and HE_EXT_SU format PPDU + * HTT_PPDU_STATS_SPATIAL_REUSE + * BIT [31 : 30] - reserved + */ + union { + A_UINT32 reserved__ppdu_tx_time_us; + A_UINT32 reserved__num_ul_expected_users__ppdu_tx_time_us; + A_UINT32 reserved__spatial_reuse__doppler_indication__beam_change__num_ul_expected_users__ppdu_tx_time_us; + struct { + A_UINT32 phy_ppdu_tx_time_us: 16, + num_ul_expected_users: 8, + beam_change: 1, + doppler_indication: 1, + spatial_reuse: 4, + reserved1: 2; + }; + }; + + /* ppdu_start_tstmp_u32_us: + * Upper 32 bits of the PPDU start timestamp. + * This field can be combined with the ppdu_start_tstmp_us field's + * lower 32 bits of the PPDU start timestamp to form a 64-bit timestamp. + */ + A_UINT32 ppdu_start_tstmp_u32_us; + + /* + * BIT [5 : 0] - bss_color_id indicates he_bss_color which is an identifier + * of the BSS and is used to assist a receiving STA in + * identifying the BSS from which a PPDU originates. + * Value in the range 0 to 63 + * BIT [31 : 6] -reserved + */ + union { + A_UINT32 reserved__bss_color_id; + struct { + A_UINT32 bss_color_id: 6, + reserved2: 26; + }; + }; } htt_ppdu_stats_common_tlv; #define HTT_PPDU_STATS_USER_COMMON_TLV_TID_NUM_M 0x000000ff @@ -655,6 +816,19 @@ typedef struct { ((_var) |= ((_val) << HTT_PPDU_STATS_USER_COMMON_TLV_DELAYED_BA_S)); \ } while (0) +#define HTT_PPDU_STATS_USER_COMMON_TLV_NUM_FRAMES_M 0xffff0000 +#define HTT_PPDU_STATS_USER_COMMON_TLV_NUM_FRAMES_S 16 + +#define HTT_PPDU_STATS_USER_COMMON_TLV_NUM_FRAMES_GET(_var) \ + (((_var) & HTT_PPDU_STATS_USER_COMMON_TLV_NUM_FRAMES_M) >> \ + HTT_PPDU_STATS_USER_COMMON_TLV_NUM_FRAMES_S) + +#define HTT_PPDU_STATS_USER_COMMON_TLV_NUM_FRAMES_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PPDU_STATS_USER_COMMON_TLV_NUM_FRAMES, _val); \ + ((_var) |= ((_val) << HTT_PPDU_STATS_USER_COMMON_TLV_NUM_FRAMES_S)); \ + } while (0) + #define HTT_PPDU_STATS_USER_COMMON_TLV_FRAME_CTRL_M 0x0000ffff #define HTT_PPDU_STATS_USER_COMMON_TLV_FRAME_CTRL_S 0 @@ -700,8 +874,9 @@ typedef struct { /* BIT [ 0 : 0] :- mcast * BIT [ 9 : 1] :- mpdus_tried * BIT [ 13: 10] :- bw - HTT_PPDU_STATS_BW - * BIT [ 14: 14] : - delayed_ba - * BIT [ 31: 15] :- rsvd + * BIT [ 14: 14] :- delayed_ba + * BIT [ 15: 15] :- rsvd + * BIT [ 31: 16] :- num_frames - num of MSDUs + num of MPDUs */ union { A_UINT32 bw__mpdus_tried__mcast; @@ -710,7 +885,8 @@ typedef struct { mpdus_tried: 9, bw: 4, delayed_ba: 1, - reserved0: 17; + reserved0: 1, + num_frames: 16; }; }; @@ -755,6 +931,11 @@ typedef struct { is_standalone: 1, is_buffer_addr_info_valid: 1, reserved1: 13; + + /* qdepth bytes : Contains Number of bytes of TIDQ depth */ + A_UINT32 qdepth_bytes; + A_UINT32 full_aid : 12, + reserved : 20; } htt_ppdu_stats_user_common_tlv; #define HTT_PPDU_STATS_USER_RATE_TLV_TID_NUM_M 0x000000ff @@ -2078,5 +2259,49 @@ typedef struct { A_UINT32 payload[1]; } htt_ppdu_stats_tx_mgmtctrl_payload_tlv; +#define HTT_PPDU_STATS_USERS_INFO_TLV_MAX_USERS_M 0x000000ff +#define HTT_PPDU_STATS_USERS_INFO_TLV_MAX_USERS_S 0 + +#define HTT_PPDU_STATS_USERS_INFO_TLV_MAX_USERS_GET(_var) \ + (((_var) & HTT_PPDU_STATS_USERS_INFO_TLV_MAX_USERS_M) >> \ + HTT_PPDU_STATS_USERS_INFO_TLV_MAX_USERS_S) + +#define HTT_PPDU_STATS_USERS_INFO_TLV_MAX_USERS_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PPDU_STATS_USERS_INFO_TLV_MAX_USERS, _val); \ + ((_var) |= ((_val) << HTT_PPDU_STATS_USERS_INFO_TLV_MAX_USERS_S)); \ + } while (0) + +#define HTT_PPDU_STATS_USERS_INFO_TLV_FRAME_TYPE_M 0x0000ff00 +#define HTT_PPDU_STATS_USERS_INFO_TLV_FRAME_TYPE_S 8 + +#define HTT_PPDU_STATS_USERS_INFO_TLV_FRAME_TYPE_GET(_var) \ + (((_var) & HTT_PPDU_STATS_USERS_INFO_TLV_FRAME_TYPE_M) >> \ + HTT_PPDU_STATS_USERS_INFO_TLV_FRAME_TYPE_S) + +#define HTT_PPDU_STATS_USERS_INFO_TLV_FRAME_TYPE_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_PPDU_STATS_USERS_INFO_TLV_FRAME_TYPE, _val); \ + ((_var) |= ((_val) << HTT_PPDU_STATS_USERS_INFO_TLV_FRAME_TYPE_S)); \ + } while (0) + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + + /* + * BIT [ 7 : 0] :- max_users + * BIT [ 15 : 8] :- frame_type (HTT_STATS_FTYPE) + * BIT [ 31 : 16] :- reserved1 + */ + union { + A_UINT32 rsvd__frame_type__max_users; + struct { + A_UINT32 max_users: 8, + frame_type: 8, + reserved1: 16; + }; + }; +} htt_ppdu_stats_users_info_tlv; + #endif //__HTT_PPDU_STATS_H__ diff --git a/drivers/staging/fw-api/fw/htt_stats.h b/drivers/staging/fw-api/fw/htt_stats.h index c2f4e8d648dc..cd6ebae7df09 100644 --- a/drivers/staging/fw-api/fw/htt_stats.h +++ b/drivers/staging/fw-api/fw/htt_stats.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -319,6 +319,36 @@ enum htt_dbg_ext_stats_type { */ HTT_DBG_EXT_STATS_FSE_RX = 28, + /* HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS + * PARAMS: + * - config_param0: [Bit0] : [1] for mac_addr based request + * - config_param1: [Bit31 : Bit0] mac_addr31to0 + * - config_param2: [Bit15 : Bit0] mac_addr47to32 + * RESP MSG: + * - htt_ctrl_path_txrx_stats_t + */ + HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS = 29, + + /* HTT_DBG_EXT_STATS_PDEV_RX_RATE_EXT + * PARAMS: + * - No Params + * RESP MSG: + * - htt_rx_pdev_rate_ext_stats_t + */ + HTT_DBG_EXT_STATS_PDEV_RX_RATE_EXT = 30, + + /* HTT_DBG_EXT_STATS_PDEV_TX_RATE_TXBF + * PARAMS: + * - No Params + * RESP MSG: + * - htt_tx_pdev_rate_txbf_stats_t + */ + HTT_DBG_EXT_STATS_PDEV_TX_RATE_TXBF = 31, + + /* HTT_DBG_EXT_STATS_TXBF_OFDMA + */ + HTT_DBG_EXT_STATS_TXBF_OFDMA = 32, + /* keep this last */ HTT_DBG_NUM_EXT_STATS = 256, }; @@ -340,6 +370,8 @@ enum htt_dbg_ext_stats_type { ((_var) |= ((_val) << HTT_DBG_EXT_PEER_STATS_RESET_S)); \ } while (0) +#define HTT_STATS_SUBTYPE_MAX 16 + typedef enum { HTT_STATS_TX_PDEV_CMN_TAG = 0, /* htt_tx_pdev_stats_cmn_tlv */ HTT_STATS_TX_PDEV_UNDERRUN_TAG = 1, /* htt_tx_pdev_stats_urrn_tlv_v */ @@ -441,10 +473,49 @@ typedef enum { HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_STATS_TAG = 97, /* htt_rx_pdev_ul_mumimo_trig_stats_tlv */ HTT_STATS_RX_FSE_STATS_TAG = 98, /* htt_rx_fse_stats_tlv */ HTT_STATS_PEER_SCHED_STATS_TAG = 99, /* htt_peer_sched_stats_tlv */ + HTT_STATS_SCHED_TXQ_SUPERCYCLE_TRIGGER_TAG = 100, /* htt_sched_txq_supercycle_triggers_tlv_v */ + HTT_STATS_PEER_CTRL_PATH_TXRX_STATS_TAG = 101, /* htt_peer_ctrl_path_txrx_stats_tlv */ + HTT_STATS_PDEV_CTRL_PATH_TX_STATS_TAG = 102, /* htt_pdev_ctrl_path_tx_stats_tlv */ + HTT_STATS_RX_PDEV_RATE_EXT_STATS_TAG = 103, /* htt_rx_pdev_rate_ext_stats_tlv */ + HTT_STATS_TX_PDEV_DL_MU_MIMO_STATS_TAG = 104, /* htt_tx_pdev_dl_mu_mimo_sch_stats_tlv */ + HTT_STATS_TX_PDEV_UL_MU_MIMO_STATS_TAG = 105, /* htt_tx_pdev_ul_mu_mimo_sch_stats_tlv */ + HTT_STATS_TX_PDEV_DL_MU_OFDMA_STATS_TAG = 106, /* htt_tx_pdev_dl_mu_ofdma_sch_stats_tlv */ + HTT_STATS_TX_PDEV_UL_MU_OFDMA_STATS_TAG = 107, /* htt_tx_pdev_ul_mu_ofdma_sch_stats_tlv */ + HTT_STATS_PDEV_TX_RATE_TXBF_STATS_TAG = 108, /* htt_tx_peer_rate_txbf_stats_tlv */ + HTT_STATS_UNSUPPORTED_ERROR_STATS_TAG = 109, /* htt_stats_error_tlv_v */ + HTT_STATS_UNAVAILABLE_ERROR_STATS_TAG = 110, /* htt_stats_error_tlv_v */ + HTT_STATS_TX_SELFGEN_AC_SCHED_STATUS_STATS_TAG = 111, /* htt_tx_selfgen_ac_sched_status_stats_tlv */ + HTT_STATS_TX_SELFGEN_AX_SCHED_STATUS_STATS_TAG = 112, /* htt_tx_selfgen_ax_sched_status_stats_tlv */ + HTT_STATS_TXBF_OFDMA_NDPA_STATS_TAG = 113, /* htt_txbf_ofdma_ndpa_stats_tlv */ + HTT_STATS_TXBF_OFDMA_NDP_STATS_TAG = 114, /* htt_txbf_ofdma_ndp_stats_tlv */ + HTT_STATS_TXBF_OFDMA_BRP_STATS_TAG = 115, /* htt_txbf_ofdma_brp_stats_tlv */ + HTT_STATS_TXBF_OFDMA_STEER_STATS_TAG = 116, /* htt_txbf_ofdma_steer_stats_tlv */ HTT_STATS_MAX_TAG, } htt_tlv_tag_t; +/* htt_mu_stats_upload_t + * Enumerations for specifying whether to upload all MU stats in response to + * HTT_DBG_EXT_STATS_PDEV_TX_MU, or if not all, then which subset. + */ +typedef enum { + /* HTT_UPLOAD_MU_STATS: upload all MU stats: + * UL MU-MIMO + DL MU-MIMO + UL MU-OFDMA + DL MU-OFDMA + */ + HTT_UPLOAD_MU_STATS, + + /* HTT_UPLOAD_MU_MIMO_STATS: upload UL MU-MIMO + DL MU-MIMO stats */ + HTT_UPLOAD_MU_MIMO_STATS, + + /* HTT_UPLOAD_MU_OFDMA_STATS: upload UL MU-OFDMA + DL MU-OFDMA stats */ + HTT_UPLOAD_MU_OFDMA_STATS, + + HTT_UPLOAD_DL_MU_MIMO_STATS, + HTT_UPLOAD_UL_MU_MIMO_STATS, + HTT_UPLOAD_DL_MU_OFDMA_STATS, + HTT_UPLOAD_UL_MU_OFDMA_STATS, +} htt_mu_stats_upload_t; + #define HTT_STATS_TLV_TAG_M 0x00000fff #define HTT_STATS_TLV_TAG_S 0 #define HTT_STATS_TLV_LENGTH_M 0x00fff000 @@ -509,6 +580,9 @@ typedef enum { #define HTT_TX_PDEV_MAX_SIFS_BURST_STATS 9 #define HTT_TX_PDEV_MAX_SIFS_BURST_HIST_STATS 10 #define HTT_TX_PDEV_MAX_PHY_ERR_STATS 18 +/* HTT_TX_PDEV_SCHED_TX_MODE_MAX: + * DEPRECATED - num sched tx mode max is 8 + */ #define HTT_TX_PDEV_SCHED_TX_MODE_MAX 4 #define HTT_TX_PDEV_NUM_SCHED_ORDER_LOG 20 @@ -672,6 +746,10 @@ typedef struct { A_UINT32 next_seq_cancel; /* Num of times fes offset was misaligned */ A_UINT32 fes_offsets_err_cnt; + /* Num of times peer blacklisted for MU-MIMO transmission */ + A_UINT32 num_mu_peer_blacklisted; + /* Num of times mu_ofdma seq posted */ + A_UINT32 mu_ofdma_seq_posted; } htt_tx_pdev_stats_cmn_tlv; #define HTT_TX_PDEV_STATS_URRN_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) @@ -738,6 +816,12 @@ typedef struct { A_UINT32 tried_mpdu_cnt_hist[1]; /* HTT_TX_PDEV_TRIED_MPDU_CNT_HIST */ } htt_tx_pdev_stats_tried_mpdu_cnt_hist_tlv_v; +typedef struct { + htt_tlv_hdr_t tlv_hdr; + /* Num MGMT MPDU transmitted by the target */ + A_UINT32 fw_tx_mgmt_subtype[HTT_STATS_SUBTYPE_MAX]; +} htt_pdev_ctrl_path_tx_stats_tlv_v; + /* STATS_TYPE: HTT_DBG_EXT_STATS_PDEV_TX * TLV_TAGS: * - HTT_STATS_TX_PDEV_CMN_TAG @@ -748,6 +832,7 @@ typedef struct { * - HTT_STATS_TX_PDEV_SIFS_HIST_TAG * - HTT_STATS_TX_PDEV_TX_PPDU_STATS_TAG * - HTT_STATS_TX_PDEV_TRIED_MPDU_CNT_HIST_TAG + * - HTT_STATS_PDEV_CTRL_PATH_TX_STATS_TAG */ /* NOTE: * This structure is for documentation, and cannot be safely used directly. @@ -762,6 +847,7 @@ typedef struct _htt_tx_pdev_stats { htt_tx_pdev_stats_sifs_hist_tlv_v sifs_hist_tlv; htt_tx_pdev_stats_tx_ppdu_stats_tlv_v tx_su_tlv; htt_tx_pdev_stats_tried_mpdu_cnt_hist_tlv_v tried_mpdu_cnt_hist_tlv; + htt_pdev_ctrl_path_tx_stats_tlv_v ctrl_path_tx_tlv; } htt_tx_pdev_stats_t; /* == SOC ERROR STATS == */ @@ -1216,7 +1302,8 @@ typedef enum { HTT_STATS_PREAM_COUNT, } HTT_STATS_PREAM_TYPE; -#define HTT_TX_PEER_STATS_NUM_MCS_COUNTERS 12 +#define HTT_TX_PEER_STATS_NUM_MCS_COUNTERS 12 /* 0-11 */ +#define HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS 2 /* 12, 13 */ /* HTT_TX_PEER_STATS_NUM_GI_COUNTERS: * GI Index 0: WHAL_GI_800 * GI Index 1: WHAL_GI_400 @@ -1239,6 +1326,7 @@ typedef enum { * bw index 7 (bw ext index 3): rssi_ext80_high20_chain0 */ #define HTT_RX_PEER_STATS_NUM_BW_EXT_COUNTERS 4 +#define HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS 4 #define HTT_TX_PEER_STATS_NUM_SPATIAL_STREAMS 8 #define HTT_TX_PEER_STATS_NUM_PREAMBLE_TYPES HTT_STATS_PREAM_COUNT @@ -1265,9 +1353,17 @@ typedef struct _htt_tx_peer_rate_stats_tlv { /* Counters to track packets in dcm mcs (MCS 0, 1, 3, 4) */ A_UINT32 tx_dcm[HTT_TX_PEER_STATS_NUM_DCM_COUNTERS]; + + /* Stats for MCS 12/13 */ + A_UINT32 tx_mcs_ext[HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS]; + A_UINT32 tx_su_mcs_ext[HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS]; + A_UINT32 tx_mu_mcs_ext[HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS]; + A_UINT32 tx_stbc_ext[HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS]; + A_UINT32 tx_gi_ext[HTT_TX_PEER_STATS_NUM_GI_COUNTERS][HTT_TX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS]; } htt_tx_peer_rate_stats_tlv; -#define HTT_RX_PEER_STATS_NUM_MCS_COUNTERS 12 +#define HTT_RX_PEER_STATS_NUM_MCS_COUNTERS 12 /* 0-11 */ +#define HTT_RX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS 2 /* 12, 13 */ #define HTT_RX_PEER_STATS_NUM_GI_COUNTERS 4 #define HTT_RX_PEER_STATS_NUM_DCM_COUNTERS 5 #define HTT_RX_PEER_STATS_NUM_BW_COUNTERS 4 @@ -1319,6 +1415,11 @@ typedef struct _htt_rx_peer_rate_stats_tlv { A_UINT32 rx_ulmumimo_mpdu_fail; /* mpdu level */ A_UINT8 rssi_chain_ext[HTT_RX_PEER_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PEER_STATS_NUM_BW_EXT_COUNTERS]; /* units = dB above noise floor */ + + /* Stats for MCS 12/13 */ + A_UINT32 rx_mcs_ext[HTT_RX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS]; + A_UINT32 rx_stbc_ext[HTT_RX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS]; + A_UINT32 rx_gi_ext[HTT_RX_PEER_STATS_NUM_GI_COUNTERS][HTT_RX_PEER_STATS_NUM_EXTRA_MCS_COUNTERS]; } htt_rx_peer_rate_stats_tlv; typedef enum { @@ -1353,9 +1454,31 @@ typedef struct { /* Peer RX time */ A_UINT32 peer_rx_active_dur_us_low; A_UINT32 peer_rx_active_dur_us_high; + A_UINT32 peer_curr_rate_kbps; } htt_peer_sched_stats_tlv; /* config_param0 */ + +#define HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_MAC_ADDR_M 0x00000001 +#define HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_MAC_ADDR_S 0 + +#define HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_MAC_ADDR_GET(_var) \ + (((_var) & HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_MAC_ADDR_M) >> \ + HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_MAC_ADDR_S) + +#define HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_MAC_ADDR_SET(_var, _val) \ + do { \ + HTT_CHECK_SET_VAL(HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_MAC_ADDR, _val); \ + ((_var) |= ((_val) << HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_MAC_ADDR_S)); \ + } while (0) +/* DEPRECATED + * The old IS_peer_MAC_ADDR_SET macro name is being retained for now, + * as an alias for the corrected macro name. + * If/when all references to the old name are removed, the definition of + * the old name will also be removed. + */ +#define HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_peer_MAC_ADDR_SET HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS_IS_MAC_ADDR_SET + #define HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_M 0x00000001 #define HTT_DBG_EXT_STATS_PEER_INFO_IS_MAC_ADDR_S 0 @@ -1692,6 +1815,43 @@ typedef struct _htt_tx_hwq_stats { ((_var) |= ((_val) << HTT_TX_SELFGEN_CMN_STATS_MAC_ID_S)); \ } while (0) +typedef enum { + HTT_TXERR_NONE, + HTT_TXERR_RESP, /* response timeout, mismatch, + * BW mismatch, mimo ctrl mismatch, + * CRC error.. */ + HTT_TXERR_FILT, /* blocked by tx filtering */ + HTT_TXERR_FIFO, /* fifo, misc errors in HW */ + HTT_TXERR_SWABORT, /* software initialted abort (TX_ABORT) */ + + HTT_TXERR_RESERVED1, + HTT_TXERR_RESERVED2, + HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS = 7, + + HTT_TXERR_INVALID = 0xff, +} htt_tx_err_status_t; + + +/* Matching enum for htt_tx_selfgen_sch_tsflag_error_stats */ +typedef enum { + HTT_TX_SELFGEN_SCH_TSFLAG_FLUSH_RCVD_ERR, + HTT_TX_SELFGEN_SCH_TSFLAG_FILT_SCHED_CMD_ERR, + HTT_TX_SELFGEN_SCH_TSFLAG_RESP_MISMATCH_ERR, + HTT_TX_SELFGEN_SCH_TSFLAG_RESP_CBF_MIMO_CTRL_MISMATCH_ERR, + HTT_TX_SELFGEN_SCH_TSFLAG_RESP_CBF_BW_MISMATCH_ERR, + HTT_TX_SELFGEN_SCH_TSFLAG_RETRY_COUNT_FAIL_ERR, + HTT_TX_SELFGEN_SCH_TSFLAG_RESP_TOO_LATE_RECEIVED_ERR, + HTT_TX_SELFGEN_SCH_TSFLAG_ERR_RESERVED, + + HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS = 8, /* includes RESERVED */ + HTT_TX_SELFGEN_SCH_TSFLAG_ERROR_STATS_VALID = 7 /* not incl. RESERVED */ +} htt_tx_selfgen_sch_tsflag_error_stats; + +#define HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS 4 +#define HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS 8 +#define HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS 74 +#define HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS 8 + typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -1710,11 +1870,17 @@ typedef struct { A_UINT32 delayed_bar_5; /* MU user 5 */ A_UINT32 delayed_bar_6; /* MU user 6 */ A_UINT32 delayed_bar_7; /* MU user 7 */ + A_UINT32 bar_with_tqm_head_seq_num; + A_UINT32 bar_with_tid_seq_num; } htt_tx_selfgen_cmn_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - /* 11AC */ + /* 11AC + * + * Fields with suffix as tried -> Selfgen frames tried out in the air, + * Fields with suffix as queued -> Selfgen frames queued to hw + */ A_UINT32 ac_su_ndpa; A_UINT32 ac_su_ndp; A_UINT32 ac_mu_mimo_ndpa; @@ -1722,32 +1888,116 @@ typedef struct { A_UINT32 ac_mu_mimo_brpoll_1; /* MU user 1 */ A_UINT32 ac_mu_mimo_brpoll_2; /* MU user 2 */ A_UINT32 ac_mu_mimo_brpoll_3; /* MU user 3 */ + A_UINT32 ac_su_ndpa_queued; + A_UINT32 ac_su_ndp_queued; + A_UINT32 ac_mu_mimo_ndpa_queued; + A_UINT32 ac_mu_mimo_ndp_queued; + A_UINT32 ac_mu_mimo_brpoll_1_queued; + A_UINT32 ac_mu_mimo_brpoll_2_queued; + A_UINT32 ac_mu_mimo_brpoll_3_queued; } htt_tx_selfgen_ac_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - /* 11AX */ + /* 11AX + * + * Fields with suffix as tried -> Selfgen frames tried out in the air, + * Fields with suffix as queued -> Selfgen frames queued to hw + */ A_UINT32 ax_su_ndpa; A_UINT32 ax_su_ndp; A_UINT32 ax_mu_mimo_ndpa; A_UINT32 ax_mu_mimo_ndp; - A_UINT32 ax_mu_mimo_brpoll_1; /* MU user 1 */ - A_UINT32 ax_mu_mimo_brpoll_2; /* MU user 2 */ - A_UINT32 ax_mu_mimo_brpoll_3; /* MU user 3 */ - A_UINT32 ax_mu_mimo_brpoll_4; /* MU user 4 */ - A_UINT32 ax_mu_mimo_brpoll_5; /* MU user 5 */ - A_UINT32 ax_mu_mimo_brpoll_6; /* MU user 6 */ - A_UINT32 ax_mu_mimo_brpoll_7; /* MU user 7 */ + union { + struct { + /* deprecated old names */ + A_UINT32 ax_mu_mimo_brpoll_1; /* MU user 1 */ + A_UINT32 ax_mu_mimo_brpoll_2; /* MU user 2 */ + A_UINT32 ax_mu_mimo_brpoll_3; /* MU user 3 */ + A_UINT32 ax_mu_mimo_brpoll_4; /* MU user 4 */ + A_UINT32 ax_mu_mimo_brpoll_5; /* MU user 5 */ + A_UINT32 ax_mu_mimo_brpoll_6; /* MU user 6 */ + A_UINT32 ax_mu_mimo_brpoll_7; /* MU user 7 */ + }; + /* MU users 1-7 */ + A_UINT32 ax_mu_mimo_brpoll[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS - 1]; + }; A_UINT32 ax_basic_trigger; A_UINT32 ax_bsr_trigger; A_UINT32 ax_mu_bar_trigger; A_UINT32 ax_mu_rts_trigger; A_UINT32 ax_ulmumimo_trigger; + A_UINT32 ax_su_ndpa_queued; + A_UINT32 ax_su_ndp_queued; + A_UINT32 ax_mu_mimo_ndpa_queued; + A_UINT32 ax_mu_mimo_ndp_queued; + A_UINT32 ax_mu_mimo_brpoll_queued[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS - 1]; } htt_tx_selfgen_ax_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - /* 11AC error stats */ + + A_UINT32 ax_ofdma_ndpa_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + A_UINT32 ax_ofdma_ndpa_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + A_UINT32 ax_ofdma_ndpa_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + A_UINT32 ax_ofdma_ndpa_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; +} htt_txbf_ofdma_ndpa_stats_tlv; + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + + A_UINT32 ax_ofdma_ndp_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + A_UINT32 ax_ofdma_ndp_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + A_UINT32 ax_ofdma_ndp_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + A_UINT32 ax_ofdma_ndp_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; +} htt_txbf_ofdma_ndp_stats_tlv; + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + + A_UINT32 ax_ofdma_brpoll_queued[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + A_UINT32 ax_ofdma_brpoll_tried[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + A_UINT32 ax_ofdma_brpoll_flushed[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + A_UINT32 ax_ofdma_brp_err[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + A_UINT32 ax_ofdma_brp_err_num_cbf_rcvd[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS+1]; +} htt_txbf_ofdma_brp_stats_tlv; + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + + A_UINT32 ax_ofdma_num_ppdu_steer[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + A_UINT32 ax_ofdma_num_ppdu_ol[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + A_UINT32 ax_ofdma_num_usrs_prefetch[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + A_UINT32 ax_ofdma_num_usrs_sound[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + A_UINT32 ax_ofdma_num_usrs_force_sound[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; +} htt_txbf_ofdma_steer_stats_tlv; + +/* STATS_TYPE : HTT_DBG_EXT_STATS_TXBF_OFDMA + * TLV_TAGS: + * - HTT_STATS_TXBF_OFDMA_NDPA_STATS_TAG + * - HTT_STATS_TXBF_OFDMA_NDP_STATS_TAG + * - HTT_STATS_TXBF_OFDMA_BRP_STATS_TAG + * - HTT_STATS_TXBF_OFDMA_STEER_STATS_TAG + */ +/* NOTE: + * This structure is for documentation, and cannot be safely used directly. + * Instead, use the constituent TLV structures to fill/parse. + */ +typedef struct { + htt_txbf_ofdma_ndpa_stats_tlv ofdma_ndpa_tlv; + htt_txbf_ofdma_ndp_stats_tlv ofdma_ndp_tlv; + htt_txbf_ofdma_brp_stats_tlv ofdma_brp_tlv; + htt_txbf_ofdma_steer_stats_tlv ofdma_steer_tlv; +} htt_tx_pdev_txbf_ofdma_stats_t; + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + /* 11AC error stats + * + * Fields with suffix as err -> Selfgen frames failed after being tried out, + * Fields with suffix as flushed - Selfgen frames flushed out from hw queue + * due to various reasons + */ A_UINT32 ac_su_ndp_err; A_UINT32 ac_su_ndpa_err; A_UINT32 ac_mu_mimo_ndpa_err; @@ -1755,29 +2005,83 @@ typedef struct { A_UINT32 ac_mu_mimo_brp1_err; A_UINT32 ac_mu_mimo_brp2_err; A_UINT32 ac_mu_mimo_brp3_err; + A_UINT32 ac_su_ndpa_flushed; + A_UINT32 ac_su_ndp_flushed; + A_UINT32 ac_mu_mimo_ndpa_flushed; + A_UINT32 ac_mu_mimo_ndp_flushed; + A_UINT32 ac_mu_mimo_brpoll1_flushed; + A_UINT32 ac_mu_mimo_brpoll2_flushed; + A_UINT32 ac_mu_mimo_brpoll3_flushed; } htt_tx_selfgen_ac_err_stats_tlv; typedef struct { htt_tlv_hdr_t tlv_hdr; - /* 11AX error stats */ + /* 11AX error stats + * + * Fields with suffix as err -> Selfgen frames failed after being tried out, + * Fields with suffix as flushed - Selfgen frames flushed out from hw queue + * due to various reasons + */ A_UINT32 ax_su_ndp_err; A_UINT32 ax_su_ndpa_err; A_UINT32 ax_mu_mimo_ndpa_err; A_UINT32 ax_mu_mimo_ndp_err; - A_UINT32 ax_mu_mimo_brp1_err; - A_UINT32 ax_mu_mimo_brp2_err; - A_UINT32 ax_mu_mimo_brp3_err; - A_UINT32 ax_mu_mimo_brp4_err; - A_UINT32 ax_mu_mimo_brp5_err; - A_UINT32 ax_mu_mimo_brp6_err; - A_UINT32 ax_mu_mimo_brp7_err; + union { + struct { + /* deprecated old names */ + A_UINT32 ax_mu_mimo_brp1_err; + A_UINT32 ax_mu_mimo_brp2_err; + A_UINT32 ax_mu_mimo_brp3_err; + A_UINT32 ax_mu_mimo_brp4_err; + A_UINT32 ax_mu_mimo_brp5_err; + A_UINT32 ax_mu_mimo_brp6_err; + A_UINT32 ax_mu_mimo_brp7_err; + }; + A_UINT32 ax_mu_mimo_brp_err[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS - 1]; + }; A_UINT32 ax_basic_trigger_err; A_UINT32 ax_bsr_trigger_err; A_UINT32 ax_mu_bar_trigger_err; A_UINT32 ax_mu_rts_trigger_err; A_UINT32 ax_ulmumimo_trigger_err; + A_UINT32 ax_mu_mimo_brp_err_num_cbf_received[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; + A_UINT32 ax_su_ndpa_flushed; + A_UINT32 ax_su_ndp_flushed; + A_UINT32 ax_mu_mimo_ndpa_flushed; + A_UINT32 ax_mu_mimo_ndp_flushed; + A_UINT32 ax_mu_mimo_brpoll_flushed[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS - 1]; } htt_tx_selfgen_ax_err_stats_tlv; +typedef struct { + htt_tlv_hdr_t tlv_hdr; + /* 11AC sched status stats */ + A_UINT32 ac_su_ndpa_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; + A_UINT32 ac_su_ndp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; + A_UINT32 ac_su_ndp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; + A_UINT32 ac_mu_mimo_ndpa_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; + A_UINT32 ac_mu_mimo_ndp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; + A_UINT32 ac_mu_mimo_ndp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; + A_UINT32 ac_mu_mimo_brp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; + A_UINT32 ac_mu_mimo_brp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; +} htt_tx_selfgen_ac_sched_status_stats_tlv; + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + /* 11AX error stats */ + A_UINT32 ax_su_ndpa_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; + A_UINT32 ax_su_ndp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; + A_UINT32 ax_su_ndp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; + A_UINT32 ax_mu_mimo_ndpa_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; + A_UINT32 ax_mu_mimo_ndp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; + A_UINT32 ax_mu_mimo_ndp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; + A_UINT32 ax_mu_brp_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; + A_UINT32 ax_mu_brp_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; + A_UINT32 ax_mu_bar_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; + A_UINT32 ax_mu_bar_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; + A_UINT32 ax_basic_trig_sch_status[HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; + A_UINT32 ax_basic_trig_sch_flag_err[HTT_TX_SELFGEN_NUM_SCH_TSFLAG_ERROR_STATS]; +} htt_tx_selfgen_ax_sched_status_stats_tlv; + /* STATS_TYPE : HTT_DBG_EXT_STATS_TX_SELFGEN_INFO * TLV_TAGS: * - HTT_STATS_TX_SELFGEN_CMN_STATS_TAG @@ -1800,15 +2104,14 @@ typedef struct { htt_tx_selfgen_ac_err_stats_tlv ac_err_tlv; /* 11AX error stats */ htt_tx_selfgen_ax_err_stats_tlv ax_err_tlv; + /* 11AC sched stats */ + htt_tx_selfgen_ac_sched_status_stats_tlv ac_sched_status_tlv; + /* 11AX sched stats */ + htt_tx_selfgen_ax_sched_status_stats_tlv ax_sched_status_tlv; } htt_tx_pdev_selfgen_stats_t; /* == TX MU STATS == */ -#define HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS 4 -#define HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS 8 -#define HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS 74 -#define HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS 8 - typedef struct { htt_tlv_hdr_t tlv_hdr; /* mu-mimo sw sched cmd stats */ @@ -1841,8 +2144,73 @@ typedef struct { * for (i+1) users */ A_UINT32 ax_ul_mumimo_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; + A_UINT32 ac_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; + A_UINT32 ax_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; } htt_tx_pdev_mu_mimo_sch_stats_tlv; +typedef struct { + htt_tlv_hdr_t tlv_hdr; + /* mu-mimo sw sched cmd stats */ + A_UINT32 mu_mimo_sch_posted; + A_UINT32 mu_mimo_sch_failed; + /* MU PPDU stats per hwQ */ + A_UINT32 mu_mimo_ppdu_posted; + /* + * Counts the number of users in each transmission of + * the given TX mode. + * + * Index is the number of users - 1. + */ + A_UINT32 ac_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; + A_UINT32 ax_mu_mimo_sch_nusers[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; + A_UINT32 ac_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_AC_MUMIMO_USER_STATS]; + A_UINT32 ax_mu_mimo_sch_posted_per_grp_sz[HTT_TX_PDEV_STATS_NUM_AX_MUMIMO_USER_STATS]; +} htt_tx_pdev_dl_mu_mimo_sch_stats_tlv; + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + A_UINT32 ax_mu_ofdma_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; +} htt_tx_pdev_dl_mu_ofdma_sch_stats_tlv; + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + A_UINT32 ax_ul_mu_ofdma_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + A_UINT32 ax_ul_mu_ofdma_bsr_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + A_UINT32 ax_ul_mu_ofdma_bar_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; + A_UINT32 ax_ul_mu_ofdma_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_OFDMA_USER_STATS]; +} htt_tx_pdev_ul_mu_ofdma_sch_stats_tlv; + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + /* UL MUMIMO */ + /* + * ax_ul_mu_mimo_basic_sch_nusers[i] is the number of basic triggers sent + * for (i+1) users + */ + A_UINT32 ax_ul_mu_mimo_basic_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; + /* + * ax_ul_mu_mimo_brp_sch_nusers[i] is the number of brp triggers sent + * for (i+1) users + */ + A_UINT32 ax_ul_mu_mimo_brp_sch_nusers[HTT_TX_PDEV_STATS_NUM_UL_MUMIMO_USER_STATS]; +} htt_tx_pdev_ul_mu_mimo_sch_stats_tlv; + + + + + + + + + + + + + + + + + typedef struct { htt_tlv_hdr_t tlv_hdr; /* mu-mimo mpdu level stats */ @@ -1904,6 +2272,10 @@ typedef struct { */ typedef struct { htt_tx_pdev_mu_mimo_sch_stats_tlv mu_mimo_sch_stats_tlv[1]; /* WAL_TX_STATS_MAX_GROUP_SIZE */ + htt_tx_pdev_dl_mu_mimo_sch_stats_tlv dl_mu_mimo_sch_stats_tlv[1]; + htt_tx_pdev_ul_mu_mimo_sch_stats_tlv ul_mu_mimo_sch_stats_tlv[1]; + htt_tx_pdev_dl_mu_ofdma_sch_stats_tlv dl_mu_ofdma_sch_stats_tlv[1]; + htt_tx_pdev_ul_mu_ofdma_sch_stats_tlv ul_mu_ofdma_sch_stats_tlv[1]; /* * Note that though mu_mimo_mpdu_stats_tlv is named MU-MIMO, * it can also hold MU-OFDMA stats. @@ -1919,7 +2291,7 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; /* Scheduler command posted per tx_mode */ - A_UINT32 sched_cmd_posted[1]; /* HTT_TX_PDEV_SCHED_TX_MODE_MAX */ + A_UINT32 sched_cmd_posted[1/* length = num tx modes */]; } htt_sched_txq_cmd_posted_tlv_v; #define HTT_SCHED_TXQ_CMD_REAPED_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) @@ -1928,7 +2300,7 @@ typedef struct { typedef struct { htt_tlv_hdr_t tlv_hdr; /* Scheduler command reaped per tx_mode */ - A_UINT32 sched_cmd_reaped[1]; /* HTT_TX_PDEV_SCHED_TX_MODE_MAX */ + A_UINT32 sched_cmd_reaped[1/* length = num tx modes */]; } htt_sched_txq_cmd_reaped_tlv_v; #define HTT_SCHED_TXQ_SCHED_ORDER_SU_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) @@ -1946,6 +2318,11 @@ typedef struct { A_UINT32 sched_order_su[1]; /* HTT_TX_PDEV_NUM_SCHED_ORDER_LOG */ } htt_sched_txq_sched_order_su_tlv_v; +typedef struct { + htt_tlv_hdr_t tlv_hdr; + A_UINT32 htt_stats_type; +} htt_stats_error_tlv_v; + typedef enum { HTT_SCHED_TID_SKIP_SCHED_MASK_DISABLED = 0, /* Skip the tid when WAL_TID_DISABLE_TX_SCHED_MASK is true */ HTT_SCHED_TID_SKIP_NOTIFY_MPDU, /* Skip the tid's 2nd sched_cmd when 1st cmd is ongoing */ @@ -1955,16 +2332,29 @@ typedef enum { HTT_SCHED_TID_SKIP_SECOND_SU_SCHEDULE, /* Skip tid from 2nd SU schedule when any of the following flag is set WAL_TX_TID(SEND_BAR | TQM_MPDU_STATE_VALID | SEND_QOS_NULL | TQM_NOTIFY_MPDU | SENDN_PENDING) */ HTT_SCHED_TID_SKIP_CMD_SLOT_NOT_AVAIL, /* Skip the tid when command slot is not available */ - HTT_SCHED_TID_SKIP_NO_ENQ, /* Skip the tid when num_frames is zero with g_disable_remove_tid as true */ + HTT_SCHED_TID_SKIP_NO_DATA, /* Skip tid without data */ + HTT_SCHED_TID_SKIP_NO_ENQ = HTT_SCHED_TID_SKIP_NO_DATA, /* deprecated old name */ HTT_SCHED_TID_SKIP_LOW_ENQ, /* Skip the tid when enqueue is low */ HTT_SCHED_TID_SKIP_PAUSED, /* Skipping the paused tid(sendn-frames) */ - HTT_SCHED_TID_SKIP_UL, /* UL tid skip */ + HTT_SCHED_TID_SKIP_UL_RESP, /* skip UL response tid */ + HTT_SCHED_TID_SKIP_UL = HTT_SCHED_TID_SKIP_UL_RESP, /* deprecated old name */ HTT_SCHED_TID_REMOVE_PAUSED, /* Removing the paused tid when number of sendn frames is zero */ HTT_SCHED_TID_REMOVE_NO_ENQ, /* Remove tid with zero queue depth */ - HTT_SCHED_TID_REMOVE_UL, /* UL tid remove */ + HTT_SCHED_TID_REMOVE_UL_RESP, /* Remove tid UL response */ + HTT_SCHED_TID_REMOVE_UL = HTT_SCHED_TID_REMOVE_UL_RESP, /* deprecated old name */ HTT_SCHED_TID_QUERY, /* Moving to next user and adding tid in prepend list when qstats update is pending */ HTT_SCHED_TID_SU_ONLY, /* Tid is eligible and TX_SCHED_SU_ONLY is true */ HTT_SCHED_TID_ELIGIBLE, /* Tid is eligible for scheduling */ + HTT_SCHED_TID_SKIP_EXCEPT_EAPOL, /* skip tid except eapol */ + HTT_SCHED_TID_SU_LOW_PRI_ONLY, /* su low priority tid only */ + HTT_SCHED_TID_SKIP_SOUND_IN_PROGRESS, /* skip tid sound in progress */ + HTT_SCHED_TID_SKIP_NO_UL_DATA, /* skip ul tid when no ul data */ + HTT_SCHED_TID_REMOVE_UL_NOT_CAPABLE, /* Remove tid that are not UL capable */ + HTT_SCHED_TID_UL_ELIGIBLE, /* Tid is eligible for UL scheduling */ + HTT_SCHED_TID_FALLBACK_TO_PREV_DECISION, /* Fall back to previous decision */ + HTT_SCHED_TID_SKIP_PEER_ALREADY_IN_TXQ, /* skip tid, peer is already available in the txq */ + HTT_SCHED_TID_SKIP_DELAY_UL_SCHED, /* skip tid delay UL schedule */ + HTT_SCHED_INELIGIBILITY_MAX, } htt_sched_txq_sched_ineligibility_tlv_enum; @@ -1977,6 +2367,35 @@ typedef struct { A_UINT32 sched_ineligibility[1]; /* indexed by htt_sched_txq_sched_ineligibility_tlv_enum */ } htt_sched_txq_sched_ineligibility_tlv_v; +typedef enum { + HTT_SCHED_SUPERCYCLE_TRIGGER_NONE = 0, /* Supercycle not triggerd */ + HTT_SCHED_SUPERCYCLE_TRIGGER_FORCED, /* forced supercycle trigger */ + HTT_SCHED_SUPERCYCLE_TRIGGER_LESS_NUM_TIDQ_ENTRIES, /* Num tidq entries is less than max_client threshold */ + HTT_SCHED_SUPERCYCLE_TRIGGER_LESS_NUM_ACTIVE_TIDS, /* Num active tids is less than max_client threshold */ + HTT_SCHED_SUPERCYCLE_TRIGGER_MAX_ITR_REACHED, /* max sched iteration reached */ + HTT_SCHED_SUPERCYCLE_TRIGGER_DUR_THRESHOLD_REACHED, /* duration threshold reached */ + HTT_SCHED_SUPERCYCLE_TRIGGER_TWT_TRIGGER, /* TWT supercycle trigger */ + HTT_SCHED_SUPERCYCLE_TRIGGER_MAX, +} htt_sched_txq_supercycle_triggers_tlv_enum; + +#define HTT_SCHED_TXQ_SUPERCYCLE_TRIGGERS_TLV_SZ(_num_elems) (sizeof(A_UINT32) * (_num_elems)) + +/* NOTE: Variable length TLV, use length spec to infer array size */ +typedef struct { + htt_tlv_hdr_t tlv_hdr; + /* + * supercycle_triggers[] is a histogram that counts the number of + * occurrences of each different reason for a transmit scheduler + * supercycle to be triggered. + * The htt_sched_txq_supercycle_triggers_tlv_enum is used to index + * supercycle_triggers[], e.g. supercycle_triggers[1] holds the number + * of times a supercycle has been forced. + * These supercycle trigger counts are not automatically reset, but + * are reset upon request. + */ + A_UINT32 supercycle_triggers[1/*HTT_SCHED_SUPERCYCLE_TRIGGER_MAX*/]; +} htt_sched_txq_supercycle_triggers_tlv_v; + #define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID_M 0x000000ff #define HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID_S 0 @@ -2101,6 +2520,7 @@ typedef struct { * - HTT_STATS_SCHED_TXQ_CMD_REAPED_TAG * - HTT_STATS_SCHED_TXQ_SCHED_ORDER_SU_TAG * - HTT_STATS_SCHED_TXQ_SCHED_INELIGIBILITY_TAG + * - HTT_STATS_SCHED_TXQ_SUPERCYCLE_TRIGGER_TAG */ /* NOTE: * This structure is for documentation, and cannot be safely used directly. @@ -2114,6 +2534,7 @@ typedef struct { htt_sched_txq_cmd_reaped_tlv_v cmd_reaped_tlv; htt_sched_txq_sched_order_su_tlv_v sched_order_su_tlv; htt_sched_txq_sched_ineligibility_tlv_v sched_ineligibility_tlv; + htt_sched_txq_supercycle_triggers_tlv_v sched_supercycle_trigger_tlv; } txq[1]; } htt_stats_tx_sched_t; @@ -3008,7 +3429,8 @@ typedef struct { /* == PDEV TX RATE CTRL STATS == */ -#define HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS 12 +#define HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS 12 /* 0-11 */ +#define HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS 2 /* 12, 13 */ #define HTT_TX_PDEV_STATS_NUM_GI_COUNTERS 4 #define HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS 5 #define HTT_TX_PDEV_STATS_NUM_BW_COUNTERS 4 @@ -3111,6 +3533,15 @@ typedef struct { A_UINT32 ofdma_tx_gi[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; A_UINT32 trigger_type_11ax[HTT_TX_PDEV_STATS_NUM_11AX_TRIGGER_TYPES]; A_UINT32 tx_11ax_su_ext; + + /* Stats for MCS 12/13 */ + A_UINT32 tx_mcs_ext[HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; + A_UINT32 tx_stbc_ext[HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; + A_UINT32 tx_gi_ext[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; + A_UINT32 ax_mu_mimo_tx_mcs_ext[HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; + A_UINT32 ofdma_tx_mcs_ext[HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; + A_UINT32 ax_mu_mimo_tx_gi_ext[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; + A_UINT32 ofdma_tx_gi_ext[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; } htt_tx_pdev_rate_stats_tlv; /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_TX_RATE @@ -3129,7 +3560,9 @@ typedef struct { #define HTT_RX_PDEV_STATS_NUM_LEGACY_CCK_STATS 4 #define HTT_RX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8 -#define HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS 12 +#define HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS 12 /* 0-11 */ +#define HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS 2 /* 12, 13 */ +#define HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT 14 /* 0-13 */ #define HTT_RX_PDEV_STATS_NUM_GI_COUNTERS 4 #define HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS 5 #define HTT_RX_PDEV_STATS_NUM_BW_COUNTERS 4 @@ -3260,6 +3693,14 @@ typedef struct { A_UINT32 rx_ulmumimo_mpdu_fail[HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; /* mpdu level */ A_UINT32 rx_ulofdma_non_data_nusers[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; A_UINT32 rx_ulofdma_data_nusers[HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; + + /* + * NOTE - this TLV is already large enough that it causes the HTT message + * carrying it to be nearly at the message size limit that applies to + * many targets/hosts. + * No further fields should be added to this TLV without very careful + * review to ensure the size increase is acceptable. + */ } htt_rx_pdev_rate_stats_tlv; /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_RX_RATE @@ -3274,6 +3715,38 @@ typedef struct { htt_rx_pdev_rate_stats_tlv rate_tlv; } htt_rx_pdev_rate_stats_t; +typedef struct { + htt_tlv_hdr_t tlv_hdr; + A_UINT8 rssi_chain_ext[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS]; /* units = dB above noise floor */ + A_INT8 rx_per_chain_rssi_ext_in_dbm[HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS][HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS]; + A_INT32 rssi_mcast_in_dbm; /* rx mcast signal strength value in dBm unit */ + A_INT32 rssi_mgmt_in_dbm; /* rx mgmt packet signal Strength value in dBm unit */ + /* + * Stats for MCS 0-13 since rx_pdev_rate_stats_tlv cannot be updated, + * due to message size limitations. + */ + A_UINT32 rx_mcs_ext[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; + A_UINT32 rx_stbc_ext[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; + A_UINT32 rx_gi_ext[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; + A_UINT32 ul_ofdma_rx_mcs_ext[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; + A_UINT32 ul_ofdma_rx_gi_ext[HTT_TX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; + A_UINT32 rx_11ax_su_txbf_mcs_ext[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; + A_UINT32 rx_11ax_mu_txbf_mcs_ext[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; + A_UINT32 rx_11ax_dl_ofdma_mcs_ext[HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; +} htt_rx_pdev_rate_ext_stats_tlv; + +/* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_RX_RATE_EXT + * TLV_TAGS: + * - HTT_STATS_RX_PDEV_RATE_EXT_STATS_TAG + */ +/* NOTE: + * This structure is for documentation, and cannot be safely used directly. + * Instead, use the constituent TLV structures to fill/parse. + */ +typedef struct { + htt_rx_pdev_rate_ext_stats_tlv rate_tlv; +} htt_rx_pdev_rate_ext_stats_t; + #define HTT_STATS_CMN_MAC_ID_M 0x000000ff #define HTT_STATS_CMN_MAC_ID_S 0 @@ -3311,7 +3784,6 @@ typedef struct { */ A_UINT32 rx_ulofdma_data_ru_size_ppdu[HTT_RX_PDEV_STATS_NUM_RU_SIZE_160MHZ_CNTRS]; /* ppdu level */ A_UINT32 rx_ulofdma_non_data_ru_size_ppdu[HTT_RX_PDEV_STATS_NUM_RU_SIZE_160MHZ_CNTRS]; /* ppdu level */ - } htt_rx_pdev_ul_trigger_stats_tlv; /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_UL_TRIG_STATS @@ -3368,6 +3840,10 @@ typedef struct { A_UINT32 ul_mumimo_rx_bw[HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; A_UINT32 ul_mumimo_rx_stbc; A_UINT32 ul_mumimo_rx_ldpc; + + /* Stats for MCS 12/13 */ + A_UINT32 ul_mumimo_rx_mcs_ext[HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; + A_UINT32 ul_mumimo_rx_gi_ext[HTT_RX_PDEV_STATS_NUM_GI_COUNTERS][HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; } htt_rx_pdev_ul_mumimo_trig_stats_tlv; /* STATS_TYPE : HTT_DBG_EXT_STATS_PDEV_UL_MUMIMO_TRIG_STATS @@ -3535,8 +4011,6 @@ typedef struct { ((_var) |= ((_val) << HTT_RX_PDEV_FW_STATS_MAC_ID_S)); \ } while (0) -#define HTT_STATS_SUBTYPE_MAX 16 - typedef struct { htt_tlv_hdr_t tlv_hdr; @@ -3640,6 +4114,16 @@ typedef struct { A_UINT32 rx_recovery_reset_cnt; } htt_rx_pdev_fw_stats_tlv; +typedef struct { + htt_tlv_hdr_t tlv_hdr; + /* peer mac address */ + htt_mac_addr peer_mac_addr; + /* Num of tx mgmt frames with subtype on peer level */ + A_UINT32 peer_tx_mgmt_subtype[HTT_STATS_SUBTYPE_MAX]; + /* Num of rx mgmt frames with subtype on peer level */ + A_UINT32 peer_rx_mgmt_subtype[HTT_STATS_SUBTYPE_MAX]; +} htt_peer_ctrl_path_txrx_stats_tlv; + #define HTT_STATS_PHY_ERR_MAX 43 typedef struct { @@ -3741,6 +4225,15 @@ typedef struct { htt_rx_pdev_fw_stats_phy_err_tlv fw_stats_phy_err_tlv; } htt_rx_pdev_stats_t; +/* STATS_TYPE : HTT_DBG_EXT_PEER_CTRL_PATH_TXRX_STATS + * TLV_TAGS: + * - HTT_STATS_PEER_CTRL_PATH_TXRX_STATS_TAG + * + */ +typedef struct { + htt_peer_ctrl_path_txrx_stats_tlv peer_ctrl_path_txrx_stats_tlv; +} htt_ctrl_path_txrx_stats_t; + #define HTT_PDEV_CCA_STATS_TX_FRAME_INFO_PRESENT (0x1) #define HTT_PDEV_CCA_STATS_RX_FRAME_INFO_PRESENT (0x2) #define HTT_PDEV_CCA_STATS_RX_CLEAR_INFO_PRESENT (0x4) @@ -4070,11 +4563,24 @@ typedef struct { A_UINT32 num_sr_tx_transmissions; /* CORRECTED - use this one */ A_UINT32 num_sr_tx_tranmissions; /* DEPRECATED - has typo in name */ }; - /* num_sr_rx_ge_pd_rssi_thr - * counter of rx from other BSS for which RSSI was above the - * packet-detection threshold specified for enabling spatial reuse - */ - A_UINT32 num_sr_rx_ge_pd_rssi_thr; + union { + /* + * Count the number of times the RSSI from an other-BSS signal + * is below the spatial reuse power threshold, thus providing an + * opportunity for spatial reuse since OBSS interference will be + * inconsequential. + */ + A_UINT32 num_spatial_reuse_opportunities; + + /* DEPRECATED: num_sr_rx_ge_pd_rssi_thr + * This old name has been deprecated because it does not + * clearly and accurately reflect the information stored within + * this field. + * Use the new name (num_spatial_reuse_opportunities) instead of + * the deprecated old name (num_sr_rx_ge_pd_rssi_thr). + */ + A_UINT32 num_sr_rx_ge_pd_rssi_thr; + }; } htt_pdev_obss_pd_stats_tlv; /* NOTE: @@ -4316,5 +4822,29 @@ typedef struct { htt_rx_fse_stats_tlv rx_fse_stats; } htt_rx_fse_stats_t; +#define HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS 14 +#define HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS 5 /* 20, 40, 80, 160, 320 */ + +typedef struct { + htt_tlv_hdr_t tlv_hdr; + /* Counters to track TxBF and OL separately */ + A_UINT32 tx_su_txbf_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS]; + A_UINT32 tx_su_ibf_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS]; + A_UINT32 tx_su_ol_mcs[HTT_TX_TXBF_RATE_STATS_NUM_MCS_COUNTERS]; + A_UINT32 tx_su_txbf_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; + A_UINT32 tx_su_ibf_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; + A_UINT32 tx_su_ol_nss[HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; + A_UINT32 tx_su_txbf_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; + A_UINT32 tx_su_ibf_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; + A_UINT32 tx_su_ol_bw[HTT_TX_TXBF_RATE_STATS_NUM_BW_COUNTERS]; +} htt_tx_pdev_txbf_rate_stats_tlv; + +/* NOTE: + * This structure is for documentation, and cannot be safely used directly. + * Instead, use the constituent TLV structures to fill/parse. + */ +typedef struct { + htt_tx_pdev_txbf_rate_stats_tlv txbf_rate_stats; +} htt_pdev_txbf_rate_stats_t; #endif /* __HTT_STATS_H__ */ diff --git a/drivers/staging/fw-api/fw/wlan_module_ids.h b/drivers/staging/fw-api/fw/wlan_module_ids.h index 1bb9d0196a69..13f5b1d9a38f 100644 --- a/drivers/staging/fw-api/fw/wlan_module_ids.h +++ b/drivers/staging/fw-api/fw/wlan_module_ids.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2020 The Linux Foundation. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -114,6 +114,8 @@ typedef enum { WLAN_MODULE_HPCS_PULSE, /* 0x50 */ WLAN_MODULE_DTF, /* 0x51 */ /* Deterministic Test Framework */ WLAN_MODULE_QUIET_IE, /* 0x52 */ + WLAN_MODULE_SHMEM_MGR, /* 0x53 */ + WLAN_MODULE_CFIR, /* 0x54 */ /* Channel Capture */ WLAN_MODULE_ID_MAX, WLAN_MODULE_ID_INVALID = WLAN_MODULE_ID_MAX, diff --git a/drivers/staging/fw-api/fw/wmi_services.h b/drivers/staging/fw-api/fw/wmi_services.h index e695fa87b44a..da9fbbecc405 100644 --- a/drivers/staging/fw-api/fw/wmi_services.h +++ b/drivers/staging/fw-api/fw/wmi_services.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2020 The Linux Foundation. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -415,6 +415,19 @@ typedef enum { WMI_SERVICE_QMI_STATS_SUPPORT = 225, WMI_SERVICE_CFR_CAPTURE_FILTER_SUPPORT = 226, /* Indicate FW Supports Channel Frequency Response (CFR) via WMI_CFR_CAPTURE_FILTER_CMDID */ WMI_SERVICE_STA_BSS_MAX_IDLE_TIME = 227, /* Indicate FW supports BSS Max Idle time feature via WMI_VDEV_BSS_MAX_IDLE_TIME_CMDID */ + WMI_SERVICE_BIP_CIPHER_SUPPORT = 228, /* FW supports new BIP_CIPHER suites (WMI_CIPHER_BIP_xxx) */ + WMI_SERVICE_BW_165MHZ_SUPPORT = 229, /* Indicate FW supports bandwidth 165MHz (i.e. 6 GHz in addition to 2.4 and 5) */ + WMI_SERVICE_BW_RESTRICTED_80P80_SUPPORT = WMI_SERVICE_BW_165MHZ_SUPPORT, + WMI_SERVICE_NAN_NDI_SAP_SAP_SCC_SUPPORT = 230, /* Support SAP + SAP + NAN discovery + NDI concurrency in SCC mode */ + WMI_SERVICE_NAN_VDEV_SUPPORT = 231, /* indicates firmware is dependent on host to create NAN vdev */ + WMI_SERVICE_AUDIO_SYNC_SUPPORT = 232, /* Indicate FW supports Audio sync feature */ + WMI_SERVICE_DUAL_STA_ROAM_SUPPORT = 233, /* Indidate FW support dual STA roaming */ + WMI_SERVICE_PEER_CREATE_CONF = 234, /* Target will send WMI_PEER_CREATE_CONF_EVENTID after WMI_PEER_CREATE_CMDID is processed */ + WMI_SERVICE_MULTIPLE_VDEV_RESTART_RESPONSE_SUPPORT = 235, /* indicates firmware supports Multiple vdev restart response */ + WMI_SERVICE_ROAM_SCAN_CHANNEL_LIST_TO_HOST_SUPPORT = 236, /* Indicates firmware supports sending roam scan channel list to host */ + WMI_SERVICE_PEER_DELETE_NO_PEER_FLUSH_TIDS_CMD = 237, /* Host should not send WMI_PEER_FLUSH_TIDS_CMD as part of peer delete */ + WMI_SERVICE_NSS_RATIO_TO_HOST_SUPPORT = 238, /* Indicates firmware supports sending NSS ratio info to host */ + WMI_SERVICE_WPA3_SUITEB_ROAM_SUPPORT = 239, /* Indicates FW supports WPA3 SUITE B roaming */ /******* ADD NEW SERVICES HERE *******/ diff --git a/drivers/staging/fw-api/fw/wmi_tlv_defs.h b/drivers/staging/fw-api/fw/wmi_tlv_defs.h index d5929cdc6dc6..f36aee254151 100644 --- a/drivers/staging/fw-api/fw/wmi_tlv_defs.h +++ b/drivers/staging/fw-api/fw/wmi_tlv_defs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2010-2020 The Linux Foundation. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -1012,6 +1012,43 @@ typedef enum { WMITLV_TAG_STRUC_wmi_cfr_filter_group_config, WMITLV_TAG_STRUC_wmi_fd_tmpl_cmd_fixed_param, WMITLV_TAG_STRUC_wmi_vdev_bss_max_idle_time_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_atf_ssid_grp_request_fixed_param, + WMITLV_TAG_STRUC_wmi_atf_group_info, + WMITLV_TAG_STRUC_wmi_atf_grp_wmm_ac_cfg_request_fixed_param, + WMITLV_TAG_STRUC_wmi_atf_group_wmm_ac_info, + WMITLV_TAG_STRUC_wmi_peer_atf_ext_request_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_atf_ext_info, + WMITLV_TAG_STRUC_wmi_get_channel_ani_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_channel_ani_info_tlv_param, + WMITLV_TAG_STRUC_wmi_get_channel_ani_event_fixed_param, + WMITLV_TAG_STRUC_wmi_oem_data_event_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_config_vlan_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_roam_stats_event_fixed_param, + WMITLV_TAG_STRUC_wmi_roam_trigger_reason_tlv_param, + WMITLV_TAG_STRUC_wmi_roam_scan_info_tlv_param, + WMITLV_TAG_STRUC_wmi_roam_scan_channel_info_tlv_param, + WMITLV_TAG_STRUC_wmi_roam_ap_info_tlv_param, + WMITLV_TAG_STRUC_wmi_roam_result_tlv_param, + WMITLV_TAG_STRUC_wmi_roam_neighbor_report_info_tlv_param, + WMITLV_TAG_STRUC_wmi_roam_neighbor_report_channel_info_tlv_param, + WMITLV_TAG_STRUC_wmi_set_ocl_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_audio_aggr_set_group_auto_rate, + WMITLV_TAG_STRUC_wmi_audio_aggr_set_group_probe, + WMITLV_TAG_STRUC_wmi_audio_aggr_update_sta_group_info, + WMITLV_TAG_STRUC_wmi_audio_sync_trigger_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_audio_sync_qtimer_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_audio_sync_start_stop_event_fixed_param, + WMITLV_TAG_STRUC_wmi_audio_sync_q_master_slave_offset_event_fixed_param, + WMITLV_TAG_STRUC_wmi_audio_sync_q_master_slave_times, + WMITLV_TAG_STRUC_wmi_roam_frame_info_tlv_param, + WMITLV_TAG_STRUC_wmi_vdev_set_pcl_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_peer_create_conf_event_fixed_param, + WMITLV_TAG_STRUC_wmi_pdev_multiple_vdev_restart_resp_event_fixed_param, + WMITLV_TAG_STRUC_wmi_roam_get_scan_channel_list_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_roam_scan_channel_list_event_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_get_big_data_cmd_fixed_param, + WMITLV_TAG_STRUC_wmi_vdev_send_big_data_event_fixed_param, + WMITLV_TAG_STRUC_wmi_nan_dmesg_event_fixed_param, } WMITLV_TAG_ID; /* @@ -1424,9 +1461,23 @@ typedef enum { OP(WMI_AUDIO_AGGR_DEL_GROUP_CMDID) \ OP(WMI_AUDIO_AGGR_SET_GROUP_RATE_CMDID) \ OP(WMI_AUDIO_AGGR_SET_GROUP_RETRY_CMDID) \ + OP(WMI_AUDIO_AGGR_UPDATE_STA_GROUP_INFO_CMDID) \ OP(WMI_CFR_CAPTURE_FILTER_CMDID) \ OP(WMI_FD_TMPL_CMDID) \ OP(WMI_VDEV_BSS_MAX_IDLE_TIME_CMDID) \ + OP(WMI_ATF_SSID_GROUPING_REQUEST_CMDID) \ + OP(WMI_ATF_GROUP_WMM_AC_CONFIG_REQUEST_CMDID) \ + OP(WMI_PEER_ATF_EXT_REQUEST_CMDID) \ + OP(WMI_GET_CHANNEL_ANI_CMDID) \ + OP(WMI_PEER_CONFIG_VLAN_CMDID) \ + OP(WMI_SET_OCL_CMDID) \ + OP(WMI_AUDIO_AGGR_SET_GROUP_AUTO_RATE_CMDID) \ + OP(WMI_AUDIO_AGGR_SET_GROUP_PROBE_CMDID) \ + OP(WMI_VDEV_AUDIO_SYNC_TRIGGER_CMDID) \ + OP(WMI_VDEV_AUDIO_SYNC_QTIMER_CMDID) \ + OP(WMI_VDEV_SET_PCL_CMDID) \ + OP(WMI_ROAM_GET_SCAN_CHANNEL_LIST_CMDID) \ + OP(WMI_VDEV_GET_BIG_DATA_CMDID) \ /* add new CMD_LIST elements above this line */ @@ -1615,6 +1666,7 @@ typedef enum { OP(WMI_PDEV_DIV_RSSI_ANTID_EVENTID) \ OP(WMI_OEM_DMA_RING_CFG_RSP_EVENTID) \ OP(WMI_OEM_DMA_BUF_RELEASE_EVENTID) \ + OP(WMI_OEM_DATA_EVENTID) \ OP(WMI_PDEV_BSS_CHAN_INFO_EVENTID) \ OP(WMI_UNIT_TEST_EVENTID) \ OP(WMI_PDEV_UPDATE_CTLTABLE_EVENTID) \ @@ -1663,6 +1715,15 @@ typedef enum { OP(WMI_ROAM_PREAUTH_START_EVENTID) \ OP(WMI_GET_ELNA_BYPASS_EVENTID) \ OP(WMI_ROAM_PMKID_REQUEST_EVENTID) \ + OP(WMI_GET_CHANNEL_ANI_EVENTID) \ + OP(WMI_ROAM_STATS_EVENTID) \ + OP(WMI_VDEV_AUDIO_SYNC_START_STOP_EVENTID) \ + OP(WMI_VDEV_AUDIO_SYNC_Q_MASTER_SLAVE_OFFSET_EVENTID) \ + OP(WMI_PEER_CREATE_CONF_EVENTID) \ + OP(WMI_PDEV_MULTIPLE_VDEV_RESTART_RESP_EVENTID) \ + OP(WMI_ROAM_SCAN_CHANNEL_LIST_EVENTID) \ + OP(WMI_VDEV_SEND_BIG_DATA_EVENTID) \ + OP(WMI_NAN_DMESG_EVENTID) \ /* add new EVT_LIST elements above this line */ @@ -3774,6 +3835,24 @@ WMITLV_CREATE_PARAM_STRUC(WMI_FWTEST_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_atf_peer_info, peer_info, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ATF_REQUEST_CMDID); +/* ATF Group Request commands */ +#define WMITLV_TABLE_WMI_ATF_SSID_GROUPING_REQUEST_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_atf_ssid_grp_request_fixed_param, wmi_atf_ssid_grp_request_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_atf_group_info, group_info, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_ATF_SSID_GROUPING_REQUEST_CMDID); + +/* ATF Group WMM Request commands */ +#define WMITLV_TABLE_WMI_ATF_GROUP_WMM_AC_CONFIG_REQUEST_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_atf_grp_wmm_ac_cfg_request_fixed_param, wmi_atf_grp_wmm_ac_cfg_request_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_atf_group_wmm_ac_info, group_info, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_ATF_GROUP_WMM_AC_CONFIG_REQUEST_CMDID); + +/* ATF EXTENDED PEER REQUEST commands */ +#define WMITLV_TABLE_WMI_PEER_ATF_EXT_REQUEST_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_atf_ext_request_fixed_param, wmi_peer_atf_ext_request_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_peer_atf_ext_info, peer_ext_info, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ATF_EXT_REQUEST_CMDID); + /* enable/disable and set the periodicity of periodic channel stats */ #define WMITLV_TABLE_WMI_SET_PERIODIC_CHANNEL_STATS_CONFIG_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_set_periodic_channel_stats_config_fixed_param, wmi_set_periodic_channel_stats_config_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -3892,7 +3971,8 @@ WMITLV_CREATE_PARAM_STRUC(WMI_HW_DATA_FILTER_CMDID); #define WMITLV_TABLE_WMI_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_multiple_vdev_restart_request_cmd_fixed_param, wmi_pdev_multiple_vdev_restart_request_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, vdev_ids, WMITLV_SIZE_VAR) \ - WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_channel, wmi_channel, chan, WMITLV_SIZE_FIX) + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_channel, wmi_channel, chan, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, phymode_list, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMDID); #define WMITLV_TABLE_WMI_PDEV_UPDATE_PKT_ROUTING_CMDID(id,op,buf,len) \ @@ -3950,6 +4030,19 @@ WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_BTM_CONFIG_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_wlm_config_cmd_fixed_param, wmi_wlm_config_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_WLM_CONFIG_CMDID); +/* Event to send roam stats */ +#define WMITLV_TABLE_WMI_ROAM_STATS_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_stats_event_fixed_param, wmi_roam_stats_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_trigger_reason, roam_trigger_reason, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_scan_info, roam_scan_info, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_scan_channel_info, roam_scan_chan_info, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_ap_info, roam_ap_info, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_result, roam_result, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_neighbor_report_info, roam_neighbor_report_info, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_neighbor_report_channel_info, roam_neighbor_report_chan_info, WMITLV_SIZE_VAR) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_roam_frame_info, roam_frame_info, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_STATS_EVENTID); + /* Motion detection cmd */ #define WMITLV_TABLE_WMI_MOTION_DET_CONFIG_PARAM_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_motion_det_config_params_cmd_fixed_param, wmi_motion_det_config_params_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -4108,6 +4201,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_SET_RAP_CONFIG_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, oem_data, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_OEM_DATA_CMDID); +/* Set OCL cmd */ +#define WMITLV_TABLE_WMI_SET_OCL_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_set_ocl_cmd_fixed_param, wmi_set_ocl_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_SET_OCL_CMDID); + /* Set ELNA BYPASS cmd */ #define WMITLV_TABLE_WMI_SET_ELNA_BYPASS_CMDID(id,op,buf,len) \ WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_set_elna_bypass_cmd_fixed_param, wmi_set_elna_bypass_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -4118,6 +4216,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_SET_ELNA_BYPASS_CMDID); WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_get_elna_bypass_cmd_fixed_param, wmi_get_elna_bypass_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_GET_ELNA_BYPASS_CMDID); +/* Get channel ANI level cmd */ +#define WMITLV_TABLE_WMI_GET_CHANNEL_ANI_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_get_channel_ani_cmd_fixed_param, wmi_get_channel_ani_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, channel_list, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_GET_CHANNEL_ANI_CMDID); + /* Audio aggr config cmd */ #define WMITLV_TABLE_WMI_AUDIO_AGGR_ENABLE_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_audio_aggr_enable_cmd_fixed_param, wmi_audio_aggr_enable_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -4141,12 +4245,54 @@ WMITLV_CREATE_PARAM_STRUC(WMI_AUDIO_AGGR_SET_GROUP_RATE_CMDID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_audio_aggr_set_group_retry, wmi_audio_aggr_set_group_retry_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_AUDIO_AGGR_SET_GROUP_RETRY_CMDID); +#define WMITLV_TABLE_WMI_AUDIO_AGGR_SET_GROUP_AUTO_RATE_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_audio_aggr_set_group_auto_rate, wmi_audio_aggr_set_group_auto_rate_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_AUDIO_AGGR_SET_GROUP_AUTO_RATE_CMDID); + +#define WMITLV_TABLE_WMI_AUDIO_AGGR_SET_GROUP_PROBE_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_audio_aggr_set_group_probe, wmi_audio_aggr_set_group_probe_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_AUDIO_AGGR_SET_GROUP_PROBE_CMDID); + +#define WMITLV_TABLE_WMI_AUDIO_AGGR_UPDATE_STA_GROUP_INFO_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_audio_aggr_update_sta_group_info, wmi_audio_aggr_update_sta_group_info_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_FIXED_STRUC, wmi_mac_addr, au_groups, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_AUDIO_AGGR_UPDATE_STA_GROUP_INFO_CMDID); + /* CFR Capture Filter cmd */ #define WMITLV_TABLE_WMI_CFR_CAPTURE_FILTER_CMDID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_cfr_capture_filter_cmd_fixed_param, wmi_cfr_capture_filter_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_cfr_filter_group_config, filter_group_config, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_CFR_CAPTURE_FILTER_CMDID); +/* VLAN config */ +#define WMITLV_TABLE_WMI_PEER_CONFIG_VLAN_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_config_vlan_cmd_fixed_param, wmi_peer_config_vlan_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_PEER_CONFIG_VLAN_CMDID); + +#define WMITLV_TABLE_WMI_VDEV_AUDIO_SYNC_TRIGGER_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_audio_sync_trigger_cmd_fixed_param, wmi_audio_sync_trigger_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_AUDIO_SYNC_TRIGGER_CMDID); + +#define WMITLV_TABLE_WMI_VDEV_AUDIO_SYNC_QTIMER_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_audio_sync_qtimer_cmd_fixed_param, wmi_audio_sync_qtimer_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_AUDIO_SYNC_QTIMER_CMDID); + +/* Preferred channel list for vdev */ +#define WMITLV_TABLE_WMI_VDEV_SET_PCL_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_set_pcl_cmd_fixed_param, wmi_vdev_set_pcl_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, channel_weight, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SET_PCL_CMDID); + +/* Get roam scan channel list */ +#define WMITLV_TABLE_WMI_ROAM_GET_SCAN_CHANNEL_LIST_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_get_scan_channel_list_cmd_fixed_param, wmi_roam_get_scan_channel_list_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_GET_SCAN_CHANNEL_LIST_CMDID); + +/* Get per vdev BIG DATA stats */ +#define WMITLV_TABLE_WMI_VDEV_GET_BIG_DATA_CMDID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_get_big_data_cmd_fixed_param, wmi_vdev_get_big_data_cmd_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_GET_BIG_DATA_CMDID); + /************************** TLV definitions of WMI events *******************************/ @@ -4376,7 +4522,9 @@ WMITLV_CREATE_PARAM_STRUC(WMI_MGMT_RX_EVENTID); /* TBTT offset Event */ #define WMITLV_TABLE_WMI_TBTTOFFSET_UPDATE_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_tbtt_offset_event_fixed_param, wmi_tbtt_offset_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ - WMITLV_FXAR(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, tbttoffset_list, WMITLV_SIZE_FIX, WMI_MAX_AP_VDEV) + WMITLV_FXAR(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, tbttoffset_list, WMITLV_SIZE_FIX, WMI_MAX_AP_VDEV) \ + WMITLV_FXAR(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, tbtt_qtime_low_us_list, WMITLV_SIZE_FIX, WMI_MAX_AP_VDEV) \ + WMITLV_FXAR(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, tbtt_qtime_high_us_list, WMITLV_SIZE_FIX, WMI_MAX_AP_VDEV) WMITLV_CREATE_PARAM_STRUC(WMI_TBTTOFFSET_UPDATE_EVENTID); /* TBTT EXT offset Event */ @@ -4598,6 +4746,12 @@ WMITLV_CREATE_PARAM_STRUC(WMI_OEM_RESPONSE_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_oem_dma_buf_release_entry, entries, WMITLV_SIZE_VAR) WMITLV_CREATE_PARAM_STRUC(WMI_OEM_DMA_BUF_RELEASE_EVENTID); +/* oem data event */ +#define WMITLV_TABLE_WMI_OEM_DATA_EVENTID(id,op, buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_oem_data_event_fixed_param, wmi_oem_data_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, data, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_OEM_DATA_EVENTID); + /* HOST SWBA Event */ #define WMITLV_TABLE_WMI_HOST_SWBA_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_host_swba_event_fixed_param, wmi_host_swba_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ @@ -5012,6 +5166,11 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_DELETE_ALL_PEER_RESP_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_assoc_conf_event_fixed_param, wmi_peer_assoc_conf_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_PEER_ASSOC_CONF_EVENTID); +/* peer create conf Event */ +#define WMITLV_TABLE_WMI_PEER_CREATE_CONF_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_peer_create_conf_event_fixed_param, wmi_peer_create_conf_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_PEER_CREATE_CONF_EVENTID); + /* D0-WOW Disable Ack event */ #define WMITLV_TABLE_WMI_D0_WOW_DISABLE_ACK_EVENTID(id,op,buf,len) \ WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_d0_wow_disable_ack_event_fixed_param, wmi_d0_wow_disable_ack_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) @@ -5276,6 +5435,15 @@ WMITLV_CREATE_PARAM_STRUC(WMI_RADIO_TX_POWER_LEVEL_STATS_EVENTID); WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_rmc_manual_leader_event_fixed_param, wmi_rmc_manual_leader_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_RMC_NEW_LEADER_EVENTID); +#define WMITLV_TABLE_WMI_VDEV_AUDIO_SYNC_START_STOP_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_audio_sync_start_stop_event_fixed_param, wmi_audio_sync_start_stop_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_AUDIO_SYNC_START_STOP_EVENTID); + +#define WMITLV_TABLE_WMI_VDEV_AUDIO_SYNC_Q_MASTER_SLAVE_OFFSET_EVENTID(id, op, buf, len) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_STRUC_wmi_audio_sync_q_master_slave_offset_event_fixed_param, wmi_audio_sync_q_master_slave_offset_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_audio_sync_q_master_slave_times, audio_sync_q_master_slave_times, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_AUDIO_SYNC_Q_MASTER_SLAVE_OFFSET_EVENTID); + /* Layout of WMI_REPORT_STATS_EVENTID message: * fixed_param; * wmi_chan_cca_stats chan_cca_stats[]; Array length is specified by num_chan_cca_stats @@ -5588,6 +5756,33 @@ WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_MGMT_OFFLOAD_EVENTID); WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_elna_bypass_event_fixed_param, wmi_get_elna_bypass_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) WMITLV_CREATE_PARAM_STRUC(WMI_GET_ELNA_BYPASS_EVENTID); +/* channel ANI event */ +#define WMITLV_TABLE_WMI_GET_CHANNEL_ANI_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_get_channel_ani_event_fixed_param, wmi_get_channel_ani_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_STRUC, wmi_channel_ani_info_tlv_param, ani_info, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_GET_CHANNEL_ANI_EVENTID); + +/* Multiple Vdev Restart response event */ +#define WMITLV_TABLE_WMI_PDEV_MULTIPLE_VDEV_RESTART_RESP_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_pdev_multiple_vdev_restart_resp_event_fixed_param, wmi_pdev_multiple_vdev_restart_resp_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, vdev_ids_bitmap, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_PDEV_MULTIPLE_VDEV_RESTART_RESP_EVENTID); + +/* Roam scan channel list event */ +#define WMITLV_TABLE_WMI_ROAM_SCAN_CHANNEL_LIST_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_roam_scan_channel_list_event_fixed_param, wmi_roam_scan_channel_list_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id, op, buf, len, WMITLV_TAG_ARRAY_UINT32, A_UINT32, channel_list, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_ROAM_SCAN_CHANNEL_LIST_EVENTID); + +/* send BIG DATA event to host */ +#define WMITLV_TABLE_WMI_VDEV_SEND_BIG_DATA_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_vdev_send_big_data_event_fixed_param, wmi_vdev_send_big_data_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) +WMITLV_CREATE_PARAM_STRUC(WMI_VDEV_SEND_BIG_DATA_EVENTID); + +#define WMITLV_TABLE_WMI_NAN_DMESG_EVENTID(id,op,buf,len) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_STRUC_wmi_nan_dmesg_event_fixed_param, wmi_nan_dmesg_event_fixed_param, fixed_param, WMITLV_SIZE_FIX) \ + WMITLV_ELEM(id,op,buf,len, WMITLV_TAG_ARRAY_BYTE, A_UINT8, msg, WMITLV_SIZE_VAR) +WMITLV_CREATE_PARAM_STRUC(WMI_NAN_DMESG_EVENTID); #ifdef __cplusplus } diff --git a/drivers/staging/fw-api/fw/wmi_unified.h b/drivers/staging/fw-api/fw/wmi_unified.h index 58624016b3b2..bd3713ac08ff 100644 --- a/drivers/staging/fw-api/fw/wmi_unified.h +++ b/drivers/staging/fw-api/fw/wmi_unified.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2010-2020 The Linux Foundation. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -259,6 +259,7 @@ typedef enum { WMI_GRP_HPCS_PULSE, /* 0x42 */ WMI_GRP_AUDIO, /* 0x43 */ WMI_GRP_CFR_CAPTURE, /* 0x44 */ + WMI_GRP_ATM, /* 0x45 ATM (Air Time Management group) */ } WMI_GRP_ID; #define WMI_CMD_GRP_START_ID(grp_id) (((grp_id) << 12) | 0x1) @@ -486,6 +487,14 @@ typedef enum { WMI_VDEV_DELETE_ALL_PEER_CMDID, /* To set bss max idle time related parameters */ WMI_VDEV_BSS_MAX_IDLE_TIME_CMDID, + /** Indicates FW to trigger Audio sync */ + WMI_VDEV_AUDIO_SYNC_TRIGGER_CMDID, + /** Gives Qtimer value to FW */ + WMI_VDEV_AUDIO_SYNC_QTIMER_CMDID, + /** Preferred channel list for each vdev */ + WMI_VDEV_SET_PCL_CMDID, + /** Get per vdev BIG DATA stats */ + WMI_VDEV_GET_BIG_DATA_CMDID, /* peer specific commands */ @@ -586,6 +595,11 @@ typedef enum { /** unmap response with peer ids */ WMI_PEER_UNMAP_RESPONSE_CMDID, + /** WMI command for per-peer configuration of VLAN header operations + * during TX and RX + */ + WMI_PEER_CONFIG_VLAN_CMDID, + /* beacon/management specific commands */ @@ -716,6 +730,8 @@ typedef enum { WMI_ROAM_ENABLE_DISABLE_TRIGGER_REASON_CMDID, /** Pre-Authentication completion status command */ WMI_ROAM_PREAUTH_STATUS_CMDID, + /** Command to get roam scan channels list */ + WMI_ROAM_GET_SCAN_CHANNEL_LIST_CMDID, /** offload scan specific commands */ /** set offload scan AP profile */ @@ -997,6 +1013,10 @@ typedef enum { WMI_SET_ELNA_BYPASS_CMDID, /** get ELNA BYPASS status */ WMI_GET_ELNA_BYPASS_CMDID, + /** get ANI level of the channels */ + WMI_GET_CHANNEL_ANI_CMDID, + /** set OCL (One Chain Listen) mode */ + WMI_SET_OCL_CMDID, /* Offload 11k related requests */ WMI_11K_OFFLOAD_REPORT_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_11K_OFFLOAD), @@ -1254,9 +1274,20 @@ typedef enum { WMI_AUDIO_AGGR_DEL_GROUP_CMDID, WMI_AUDIO_AGGR_SET_GROUP_RATE_CMDID, WMI_AUDIO_AGGR_SET_GROUP_RETRY_CMDID, + WMI_AUDIO_AGGR_SET_GROUP_AUTO_RATE_CMDID, + WMI_AUDIO_AGGR_SET_GROUP_PROBE_CMDID, + WMI_AUDIO_AGGR_UPDATE_STA_GROUP_INFO_CMDID, /** WMI commands related to Channel Frequency Response Capture **/ WMI_CFR_CAPTURE_FILTER_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_CFR_CAPTURE), + + /** WMI commands related to Air Time Management feature **/ + /** ATF SSID GROUPING REQUEST command */ + WMI_ATF_SSID_GROUPING_REQUEST_CMDID = WMI_CMD_GRP_START_ID(WMI_GRP_ATM), + /** WMM ATF Configuration for groups */ + WMI_ATF_GROUP_WMM_AC_CONFIG_REQUEST_CMDID, + /** ATF Peer Extended Request command */ + WMI_PEER_ATF_EXT_REQUEST_CMDID, } WMI_CMD_ID; typedef enum { @@ -1370,6 +1401,12 @@ typedef enum { /** 2nd extension of SERVICE_READY msg with extra target capability info */ WMI_SERVICE_READY_EXT2_EVENTID, + /** + * vdev restart response for multiple vdevs in response to + * MULTIPLE_VDEV_RESTART_REQUEST + */ + WMI_PDEV_MULTIPLE_VDEV_RESTART_RESP_EVENTID, + /* VDEV specific events */ /** VDEV started event in response to VDEV_START request */ WMI_VDEV_START_RESP_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_VDEV), @@ -1426,6 +1463,13 @@ typedef enum { /* FW response to Host for delete all peer cmdid */ WMI_VDEV_DELETE_ALL_PEER_RESP_EVENTID, + /** Indicates host to start/stop strobing for QTIMER periodically */ + WMI_VDEV_AUDIO_SYNC_START_STOP_EVENTID, + /** Sends the final offset in the QTIMERs of both master and slave */ + WMI_VDEV_AUDIO_SYNC_Q_MASTER_SLAVE_OFFSET_EVENTID, + /* send BIG DATA stats to host */ + WMI_VDEV_SEND_BIG_DATA_EVENTID, + /* peer specific events */ /** FW reauet to kick out the station for reasons like inactivity,lack of response ..etc */ @@ -1492,6 +1536,11 @@ typedef enum { WMI_PEER_CFR_CAPTURE_EVENTID, + /* Peer Create Conf event to confirm fw had received WMI_PEER_CREATE_CMDID + * and status of WMI_PEER_CREATE_CMDID. + */ + WMI_PEER_CREATE_CONF_EVENTID, + /* beacon/mgmt specific events */ /** RX management frame. the entire frame is carried along with the event. */ WMI_MGMT_RX_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_MGMT), @@ -1558,6 +1607,10 @@ typedef enum { WMI_ROAM_PREAUTH_START_EVENTID, /** Roaming PMKID request event */ WMI_ROAM_PMKID_REQUEST_EVENTID, + /** roam stats */ + WMI_ROAM_STATS_EVENTID, + /** Roam scan channels list */ + WMI_ROAM_SCAN_CHANNEL_LIST_EVENTID, /** P2P disc found */ WMI_P2P_DISC_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_P2P), @@ -1763,6 +1816,9 @@ typedef enum { /** event to get ELNA BYPASS status */ WMI_GET_ELNA_BYPASS_EVENTID, + /** event to report ANI level of the channels */ + WMI_GET_CHANNEL_ANI_EVENTID, + /* GPIO Event */ WMI_GPIO_INPUT_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_GPIO), /** upload H_CV info WMI event @@ -1796,6 +1852,7 @@ typedef enum { WMI_OEM_RESPONSE_EVENTID, WMI_OEM_DMA_RING_CFG_RSP_EVENTID, WMI_OEM_DMA_BUF_RELEASE_EVENTID, + WMI_OEM_DATA_EVENTID, /* NAN Event */ WMI_NAN_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_NAN), @@ -1803,6 +1860,7 @@ typedef enum { WMI_NAN_DISC_IFACE_DELETED_EVENTID, WMI_NAN_STARTED_CLUSTER_EVENTID, WMI_NAN_JOINED_CLUSTER_EVENTID, + WMI_NAN_DMESG_EVENTID, /* Coex Event */ WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_COEX), @@ -2159,6 +2217,20 @@ typedef enum { */ #define WMI_HE_MAX_MCS_4_SS_MASK(r,ss) ((3 & (r)) << (((ss) - 1) << 1)) +/* + * index ranges from 0 to 15, and is used for checking if MCS 12/13 is enabled + * for a particular NSS. + * The lower 8 bits (indices 0-7) within the 16 bits indicate MCS 12/13 + * enablement for BW <= 80MHz; the upper 8 bits (indices 8-15) within + * the 16 bits indicate MCS 12/13 enablement for BW > 80MHz. + * The 16 bits for the index values are within the upper bits (bits 31:16) + * of a 32-bit word. + */ +#define WMI_HE_EXTRA_MCS_SS_GET(he_mcs_map_ext, index) \ + WMI_GET_BITS(he_mcs_map_ext, 16 + index, 1) +#define WMI_HE_EXTRA_MCS_SS_SET(he_mcs_map_ext, index, value) \ + WMI_SET_BITS(he_mcs_map_ext, 16 + index, 1, value) + /* fragmentation support field value */ enum { WMI_HE_FRAG_SUPPORT_LEVEL0, /* No Fragmentation support */ @@ -3225,6 +3297,20 @@ typedef struct { #define WMI_RSRC_CFG_FLAG_BSS_MAX_IDLE_TIME_SUPPORT_S 28 #define WMI_RSRC_CFG_FLAG_BSS_MAX_IDLE_TIME_SUPPORT_M 0x10000000 + /* + * If this bit is set, then target should use the audio sync feature. + * Host should only set this bit if the target has indicated via the + * WMI_SERVICE_AUDIO_SYNC_SUPPORT flag that it supports audio sync. + */ + #define WMI_RSRC_CFG_FLAG_AUDIO_SYNC_SUPPORT_S 29 + #define WMI_RSRC_CFG_FLAG_AUDIO_SYNC_SUPPORT_M 0x20000000 + + /* + * If this BIT is set, then the target should disable IPA + */ + #define WMI_RSRC_CFG_FLAG_IPA_DISABLE_S 30 + #define WMI_RSRC_CFG_FLAG_IPA_DISABLE_M 0x40000000 + A_UINT32 flag1; /** @brief smart_ant_cap - Smart Antenna capabilities information @@ -3392,6 +3478,41 @@ typedef struct { * are used to read and write these bitfields. */ A_UINT32 msdu_flow_override_config1; + + /** @brief flags2 - contains flags used for the following purposes: + * Configure 11ax uplink ofdma/MU-MIMO feature in FW, when chipsets + * are brought up in Repeater/STA mode. + * + * @details + * Bits 3:0 + * Enable UL MU-OFDMA/MIMO for PDEVs WIFI0, WIFI1, WIFI2 + * This flags should only be set when a pdev has STA VAP + * in repeater/self-organizing-network modes. + * E.g. to enable UL RESP for 5G and 2G radios, value shall be + * 0b00000000000000000000000000000011 = 0x3. + * Host shall use UCI config for a radio to populate this value, + * each radio entry shall have "config re_ul_resp 1" value set. + * Hence this can be configured dynamically. + * + * Refer to the below WMI_RSRC_CFG_FLAGS2_RE_ULRESP_PDEV_CFG_GET/SET + * macros. + * Bits 31:4 - Reserved + */ + A_UINT32 flags2; + /** @brief host_service_flags - can be used by Host to indicate + * services that host can support. + * + * @details + * Bit 0 + * The bit will be set when Host HDD supports seperate iface creation + * for NAN. More specifically Host can support creation of NAN vdev + * in firmware. + * + * Refer to WMI_RSRC_CFG_HOST_SERVICE_FLAG_NAN_IFACE_SUPPORT_GET/SET + * macros defined below. + * Bits 31:1 - Reserved + */ + A_UINT32 host_service_flags; } wmi_resource_config; #define WMI_MSDU_FLOW_AST_ENABLE_GET(msdu_flow_config0, ast_x) \ @@ -3576,6 +3697,26 @@ typedef struct { #define WMI_RSRC_CFG_FLAG_BSS_MAX_IDLE_TIME_SUPPORT_GET(word32) \ WMI_RSRC_CFG_FLAG_GET((word32), BSS_MAX_IDLE_TIME_SUPPORT) +#define WMI_RSRC_CFG_FLAG_AUDIO_SYNC_SUPPORT_SET(word32, value) \ + WMI_RSRC_CFG_FLAG_SET((word32), AUDIO_SYNC_SUPPORT, (value)) +#define WMI_RSRC_CFG_FLAG_AUDIO_SYNC_SUPPORT_GET(word32) \ + WMI_RSRC_CFG_FLAG_GET((word32), AUDIO_SYNC_SUPPORT) + +#define WMI_RSRC_CFG_FLAG_IPA_DISABLE_SET(word32, value) \ + WMI_RSRC_CFG_FLAG_SET((word32), IPA_DISABLE, (value)) +#define WMI_RSRC_CFG_FLAG_IPA_DISABLE_GET(word32) \ + WMI_RSRC_CFG_FLAG_GET((word32), IPA_DISABLE) + +#define WMI_RSRC_CFG_FLAGS2_RE_ULRESP_PDEV_CFG_GET(flags2, pdev_id) \ + WMI_GET_BITS(flags2, pdev_id, 1) +#define WMI_RSRC_CFG_FLAGS2_RE_ULRESP_PDEV_CFG_SET(flags2, pdev_id, value) \ + WMI_SET_BITS(flags2, pdev_id, 1, value) + +#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_NAN_IFACE_SUPPORT_GET(host_service_flags) \ + WMI_GET_BITS(host_service_flags, 0, 1) +#define WMI_RSRC_CFG_HOST_SERVICE_FLAG_NAN_IFACE_SUPPORT_SET(host_service_flags, val) \ + WMI_SET_BITS(host_service_flags, 0, 1, val) + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_init_cmd_fixed_param */ @@ -3866,6 +4007,10 @@ typedef struct { * as a passive channel */ A_UINT32 dwell_time_passive_6ghz; + /** + * Offset time is in milliseconds per channel. + */ + A_UINT32 scan_start_offset; /** * TLV (tag length value) parameters follow the scan_cmd @@ -5356,6 +5501,12 @@ typedef struct { wmi_mac_addr base_macaddr; } wmi_pdev_set_base_macaddr_cmd_fixed_param; + +enum wmi_spectral_scan_mode { + WMI_SPECTRAL_SCAN_NORMAL_MODE, + WMI_SPECTRAL_SCAN_AGILE_MODE, +}; + /* * For now, the spectral configuration is global rather than * per-vdev. The vdev is a placeholder and will be ignored @@ -5382,6 +5533,14 @@ typedef struct { A_UINT32 spectral_scan_bin_scale; A_UINT32 spectral_scan_dBm_adj; A_UINT32 spectral_scan_chn_mask; + /* See enum wmi_spectral_scan_mode */ + A_UINT32 spectral_scan_mode; + /* agile span center frequency (MHz), 0 for normal scan*/ + A_UINT32 spectral_scan_center_freq; + /* agile span primary channel frequency (MHz), 0 for normal scan*/ + A_UINT32 spectral_scan_chan_freq; + /* agile scan bandwidth (20, 40, 80, 80+80, 160), enum wmi_channel_width */ + A_UINT32 spectral_scan_chan_width; } wmi_vdev_spectral_configure_cmd_fixed_param; /* @@ -5397,6 +5556,8 @@ typedef struct { A_UINT32 trigger_cmd; /* 0 - ignore; 1 - enable, 2 - disable */ A_UINT32 enable_cmd; + /* See enum wmi_spectral_scan_mode */ + A_UINT32 spectral_scan_mode; } wmi_vdev_spectral_enable_cmd_fixed_param; typedef struct { @@ -5467,8 +5628,10 @@ typedef enum { WMI_CSA_IE_PRESENT = 0x00000001, WMI_XCSA_IE_PRESENT = 0x00000002, WMI_WBW_IE_PRESENT = 0x00000004, - WMI_CSWARP_IE_PRESENT = 0x00000008, + WMI_CSWRAP_IE_PRESENT = 0x00000008, + WMI_CSWARP_IE_PRESENT = WMI_CSWRAP_IE_PRESENT, /* deprecated: typo */ WMI_QSBW_ISE_PRESENT = 0x00000010, + WMI_CSWRAP_IE_EXTENDED_PRESENT = 0x00000020, /* Added bitmask to verify if the additional information is filled in */ } WMI_CSA_EVENT_IES_PRESENT_FLAG; /* wmi CSA receive event from beacon frame */ @@ -5482,9 +5645,23 @@ typedef struct { A_UINT32 csa_ie[2]; A_UINT32 xcsa_ie[2]; A_UINT32 wb_ie[2]; - A_UINT32 cswarp_ie; + union { + A_UINT32 cswrap_ie; /* use this */ + A_UINT32 cswarp_ie; /* deprecated (typo) */ + }; A_UINT32 ies_present_flag; /* WMI_CSA_EVENT_IES_PRESENT_FLAG */ A_UINT32 qsbw_ise; + /* cswrap_ie_extended: + * Stores full IEEE80211_ELEMID_CHAN_SWITCH_WRAP information element. + * The first two octets host the Element ID and Length fields. + * The IE comprises New Country Subelement (optional and max length 6), + * Wide Bandwidth Channel Subelement (optional and max length 5) and + * New Transmit Power Envelope subelement (optional and max length 7) + * The 4-byte words within cswrap_ie_extended[] use little endian ordering; + * the first octect of the IE resides in bits 7:0 of cswrap_ie_extended[0], + * the second octet resides in bits 15:8 of cswrap_ie_extended[0] and so on. + */ + A_UINT32 cswrap_ie_extended[5]; } wmi_csa_event_fixed_param; typedef enum { @@ -6255,6 +6432,42 @@ typedef enum { */ WMI_PDEV_PARAM_ENABLE_FW_DYNAMIC_HE_EDCA, + /* + * Parameter used to set default 6 GHz rate. + * Applies to all non data transmissions in 6 GHz unless + * overwritten by respective VDEV params. + */ + WMI_PDEV_PARAM_DEFAULT_6GHZ_RATE, + + /* + * Configures the duration (in seconds) to delay the channel avoidance + * indication at WLAN firmware before indicating it to WLAN host, + * when WWAN (LTE/5GNR) PCC is in conflict due to WWAN-WLAN coexistence. + * Default value is 60 seconds. + * If set to zero, FW sends channel avoidance indcation immediately to Host. + */ + WMI_PDEV_PARAM_MWSCOEX_PCC_CHAVD_DELAY, + + /* + * Configures the duration (in seconds) to delay the channel avoidance + * indication at WLAN firmware before indicating it to WLAN host, + * when WWAN (LTE/5GNR) SCC is in conflict due to WWAN-WLAN coexistence. + * Default value is 120 seconds. + * If set to zero, FW sends channel avoidance indcation immediately to Host. + */ + WMI_PDEV_PARAM_MWSCOEX_SCC_CHAVD_DELAY, + + /* + * Parameter used to set ageout timer value from host (units = seconds). + * If not set, FW use default value 2 seconds. + * ageout time: the time upto which DFS channel information such as + * beacon found is remembered + */ + WMI_PDEV_PARAM_SET_DFS_CHAN_AGEOUT_TIME, + + /* Parameter used for enabling/disabling xlna bypass for SAP mode*/ + WMI_PDEV_PARAM_SET_SAP_XLNA_BYPASS, + } WMI_PDEV_PARAM; #define WMI_PDEV_ONLY_BSR_TRIG_IS_ENABLED(trig_type) WMI_GET_BITS(trig_type, 0, 1) @@ -6378,6 +6591,7 @@ typedef struct { typedef struct { A_UINT32 tlv_header; /* WMITLV_TAG_STRUC_wmi_pdev_bss_chan_info_request_fixed_param */ A_UINT32 param; /* 1 = read only, 2= read and clear */ + A_UINT32 pdev_id; /* pdev_id for identifying mac */ } wmi_pdev_bss_chan_info_request_fixed_param; typedef struct { @@ -6544,6 +6758,14 @@ typedef struct { * the noise floor. */ A_UINT32 ack_rssi; + /* xmit rate in kbps */ + A_UINT32 tx_rate; + /* phy mode WLAN_PHY_MODE of the channel defined in wlan_defs.h */ + A_UINT32 peer_phymode; + A_UINT32 retries_count; + /* current 64 bit TSF timestamp */ + A_UINT32 tx_tsf_l32; + A_UINT32 tx_tsf_u32; } wmi_mgmt_tx_compl_event_fixed_param; typedef struct { @@ -6666,6 +6888,7 @@ typedef struct { A_UINT32 rx_bss_cycle_count_low; /* low 31 bits of rx cycle cnt for my bss in 64bits format */ A_UINT32 rx_bss_cycle_count_high; /* high 31 bits of rx_cycle cnt for my bss in 64bits format */ + A_UINT32 pdev_id; /* pdev_id for identifying the MAC */ } wmi_pdev_bss_chan_info_event_fixed_param; typedef struct { @@ -9472,6 +9695,10 @@ typedef struct { #define WMI_CIPHER_AES_GCM 0x9 #define WMI_CIPHER_AES_GMAC 0xa #define WMI_CIPHER_WAPI_GCM_SM4 0xb +#define WMI_CIPHER_BIP_CMAC_128 0xc +#define WMI_CIPHER_BIP_CMAC_256 0xd +#define WMI_CIPHER_BIP_GMAC_128 0xe +#define WMI_CIPHER_BIP_GMAC_256 0xf typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_install_key_cmd_fixed_param */ @@ -9545,9 +9772,9 @@ typedef enum { /* Control to enable/disable FILS discovery frame tx in non-HT duplicate */ #define WMI_VDEV_6GHZ_BITMAP_NON_HT_DUPLICATE_FD_FRAME 0x4 /* Control to enable/disable periodic FILS discovery frame transmission */ -#define WMI_VDEV_6GHZ_BITMAP_FD_FRAME 0x8 +#define WMI_VDEV_6GHZ_BITMAP_FD_FRAME 0x8 /* deprecated */ /* Control to enable/disable periodic broadcast probe response transmission */ -#define WMI_VDEV_6GHZ_BITMAP_BCAST_PROBE_RSP 0x10 +#define WMI_VDEV_6GHZ_BITMAP_BCAST_PROBE_RSP 0x10 /* deprecated */ /** the definition of different VDEV parameters */ typedef enum { @@ -9929,7 +10156,8 @@ typedef enum { WMI_VDEV_PARAM_DISABLE_DYN_BW_RTS, /* 0x68 */ /** per ssid (vdev) based ATF strict/fair scheduling policy - * param values are WMI_ATF_SSID_FAIR_SCHED or WMI_ATF_SSID_STRICT_SCHED + * param values are WMI_ATF_SSID_FAIR_SCHED, WMI_ATF_SSID_STRICT_SCHED, + * or WMI_ATF_SSID_FAIR_SCHED_WITH_UB */ WMI_VDEV_PARAM_ATF_SSID_SCHED_POLICY, /* 0x69 */ @@ -10287,6 +10515,35 @@ typedef enum { */ WMI_VDEV_PARAM_6GHZ_PARAMS, /* 0x99 */ + /** + * VDEV parameter to enable or disable RTT initiator role + * Default : Enabled + * valid values: 0-Disable initiator role, 1-Enable initiator role. + */ + WMI_VDEV_PARAM_ENABLE_DISABLE_RTT_INITIATOR_ROLE, /* 0x9A */ + + /** + * To configure duration of how many seconds to wait to kickout peer + * if peer is not reachable + */ + WMI_VDEV_PARAM_NDP_KEEPALIVE_TIMEOUT, /* 0x9B*/ + + /** + * To support discovery of NAN cluster with Master Preference (MP) as 0 + * when a new device is enabling NAN + */ + WMI_VDEV_PARAM_ALLOW_NAN_INITIAL_DISCOVERY_OF_MP0_CLUSTER, /* 0x9C */ + + /** + * VDEV parameter to enable or disable roaming reason VSIE in + * re-association request + * + * Default : Disabled + * valid values: 0 - Disable 1 - Enable + */ + WMI_VDEV_PARAM_ENABLE_DISABLE_ROAM_REASON_VSIE, /* 0x9D */ + + /*=== ADD NEW VDEV PARAM TYPES ABOVE THIS LINE === * The below vdev param types are used for prototyping, and are * prone to change. @@ -10505,16 +10762,22 @@ typedef struct { /** Upto 8 bits are available for Roaming module to be sent along with WMI_VDEV_PARAM_ROAM_FW_OFFLOAD WMI_VDEV_PARAM **/ -/* Enable Roaming FW offload LFR1.5/LFR2.0 implementation */ +/* Bit 0: Enable Roaming FW offload LFR1.5/LFR2.0 implementation */ #define WMI_ROAM_FW_OFFLOAD_ENABLE_FLAG 0x1 -/* Enable Roaming module in FW to do scan based on Final BMISS */ +/* Bit 1: Enable Roaming module in FW to do scan based on Final BMISS */ #define WMI_ROAM_BMISS_FINAL_SCAN_ENABLE_FLAG 0x2 -/** +/* Bit 2: * To enable/disable EAPOL_4WAY_HANDSHAKE process while roaming. * param value = 0 --> Enable EAPOL 4way handshake * param value = 1 --> Skip EAPOL 4way handshake */ #define WMI_VDEV_PARAM_SKIP_ROAM_EAPOL_4WAY_HANDSHAKE 0x4 +/* Bit 3: + * Scan type when WMI_ROAM_BMISS_FINAL_SCAN_ENABLE_FLAG is set: + * value = 0 --> Chanmap scan followed by one full scan if no candidate found. + * value = 1 --> Chanmap scan only + */ +#define WMI_ROAM_BMISS_FINAL_SCAN_TYPE_FLAG 0x8 /** slot time long */ #define WMI_VDEV_SLOT_TIME_LONG 0x1 @@ -11365,9 +11628,16 @@ typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_tbtt_offset_event_fixed_param */ /** bimtap of VDEVs that has tbtt offset updated */ A_UINT32 vdev_map; -/* The TLVs for tbttoffset_list will follow this TLV. - * tbtt offset list in the order of the LSB to MSB in the vdev_map bitmap +/* The TLVs for tbttoffset_list, tbtt_qtime_low_us_list, and + * tbtt_qtime_high_us_list will follow this TLV. + * - tbtt offset list in the order of the LSb to MSb in the vdev_map bitmap * A_UINT32 tbttoffset_list[WMI_MAX_AP_VDEV]; + * - tbtt qtime_low_us list(Lower 32 bit of qtime us) in the order of the + * LSb to MSb in the vdev_map bitmap + * A_UINT32 tbtt_qtime_low_us_list[WMI_MAX_AP_VDEV]; + * - tbtt qtime_high_us list(Higher 32 bit of qtime us) in the order of the + * LSb to MSb in the vdev_map bitmap + * A_UINT32 tbtt_qtime_high_us_list[WMI_MAX_AP_VDEV]; */ } wmi_tbtt_offset_event_fixed_param; @@ -11377,6 +11647,9 @@ typedef struct { A_UINT32 vdev_id; /** tbttoffset in TUs */ A_UINT32 tbttoffset; + /** absolute tbtt time in qtime us */ + A_UINT32 tbtt_qtime_low_us; /* bits 31:0 of qtime */ + A_UINT32 tbtt_qtime_high_us; /* bits 63:32 of qtime */ } wmi_tbtt_offset_info; /** Use this event if number of vdevs > 32 */ @@ -11809,6 +12082,12 @@ typedef struct { /* Per peer MISC stats enable or disable */ #define WMI_PEER_PARAM_MISC_STATS_ENABLE 0x22 +/* Per peer FW congestion enable or disable: + * A parameter value of 1 will disable FW tx congestion control for the peer, + * a parameter value 0f 0 will enable FW tx congestion control for the peer. + */ +#define WMI_PEER_PARAM_FW_CONGESTION_DISABLE 0x23 + /** mimo ps values for the parameter WMI_PEER_MIMO_PS_STATE */ #define WMI_PEER_MIMO_PS_NONE 0x0 #define WMI_PEER_MIMO_PS_STATIC 0x1 @@ -11954,7 +12233,16 @@ typedef struct { * value 1 - MCS 0-9 enabled for this NSS * value 2 - MCS 0-11 enabled for this NSS * value 3 - NSS disabled - * - WMI_HE_MAX_MCS_4_SS_MASK macro can be used for encoding this info + * WMI_HE_MAX_MCS_4_SS_MASK macro can be used for encoding this info + * + * - 8 bits x 2 are used for each Nss value for 2 categories of bandwidths, + * to indicate whether MCS 12 and 13 are enabled. + * Bits [16:23] used for checking if MCS 12/13 is enabled for a + * particular NSS (BW <= 80MHz) + * Bits [24:31] used for checking if MCS 12/13 is enabled for a + * particular NSS (BW > 80MHz) + * The WMI_HE_EXTRA_MCS_SS_[GET,SET] macros can be used for accessing + * these bit-fields. */ A_UINT32 tx_mcs_set; /* Negotiated TX HE rates(i.e. rate this node can TX to peer) */ } wmi_he_rate_set; @@ -11971,6 +12259,7 @@ typedef struct { #define WMI_PEER_APSD 0x00000800 /* U-APSD power save enabled */ #define WMI_PEER_HT 0x00001000 /* HT enabled */ #define WMI_PEER_40MHZ 0x00002000 /* 40MHz enabld */ +#define WMI_PEER_INTER_BSS_PEER 0x00004000 /* Inter BSS peer */ #define WMI_PEER_STBC 0x00008000 /* STBC Enabled */ #define WMI_PEER_LDPC 0x00010000 /* LDPC ENabled */ #define WMI_PEER_DYN_MIMOPS 0x00020000 /* Dynamic MIMO PS Enabled */ @@ -12095,6 +12384,12 @@ typedef struct { /* min data rate to be used in Mbps */ A_UINT32 min_data_rate; + /** HE 6 GHz Band Capabilities of the peer. + * (Defined in 9.4.2.261 HE 6GHz Band Capabilities element in 802.11ax_D5.0) + * valid when WMI_PEER_HE is set and WMI_PEER_VHT/HT are not set. + */ + A_UINT32 peer_he_caps_6ghz; + /* Following this struct are the TLV's: * A_UINT8 peer_legacy_rates[]; * A_UINT8 peer_ht_rates[]; @@ -12189,6 +12484,11 @@ typedef struct { A_UINT32 mac_clk_mhz; /** unique id identifying the VDEV */ A_UINT32 vdev_id; + /** + * Noise Floor value for all chain in dBm. + * If per_chain_noise_floor value is 0 then it should be ignored. + */ + A_UINT32 per_chain_noise_floor[WMI_MAX_CHAINS]; } wmi_chan_info_event_fixed_param; /** @@ -12571,6 +12871,10 @@ typedef struct { #define WMI_ROAM_SCAN_CHAN_LIST_TYPE_NONE 0x1 #define WMI_ROAM_SCAN_CHAN_LIST_TYPE_STATIC 0x2 #define WMI_ROAM_SCAN_CHAN_LIST_TYPE_DYNAMIC 0x3 + +#define WMI_ROAM_SCAN_LIST_FLAG_FLUSH_STATIC 0x1 /* Flush static roam scan channel list in FW */ +#define WMI_ROAM_SCAN_LIST_FLAG_FLUSH_DYNAMIC 0x2 /* Flush dynamic roam scan channel list in FW */ + /** * TLV for roaming channel list */ @@ -12582,6 +12886,7 @@ typedef struct { A_UINT32 chan_list_type; /** # if channels to scan */ A_UINT32 num_chan; + A_UINT32 flags; /* refer to WMI_ROAM_SCAN_LIST_FLAG_xxx defs */ /** * TLV (tag length value) parameters follow the wmi_roam_chan_list * structure. The TLV's are: @@ -12884,6 +13189,12 @@ typedef struct { A_UINT32 roam_score_delta_mask; /* Vendor specific roam score algorithm ID from WMI_VENDOR_ROAM_SCORE_ALGORITHM_ID enum */ A_UINT32 vendor_roam_score_algorithm_id; + /* + * During CU and low rssi based roam triggers, consider AP as + * roam candidate only if its roam score is better than connected AP score + * by at least candidate_min_roam_score_delta. + */ + A_UINT32 candidate_min_roam_score_delta; } wmi_roam_cnd_scoring_param; typedef struct { @@ -13072,6 +13383,13 @@ typedef struct wmi_fd_send_from_host { A_UINT32 frame_ctrl; /* frame ctrl to setup PPDU desc */ } wmi_fd_send_from_host_cmd_fixed_param; +/* + * Control to send broadcast probe response instead of FD frames. + * When this flag is not set then FD frame will be transmitted when + * fd_period is non-zero + */ +#define WMI_FILS_FLAGS_BITMAP_BCAST_PROBE_RSP 0x1 + /* * WMI command structure for FILS feature enable/disable */ @@ -13079,7 +13397,9 @@ typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_enable_fils_cmd_fixed_param */ /* VDEV identifier */ A_UINT32 vdev_id; - A_UINT32 fd_period; /* non-zero - enable Fils Discovery frames with this period (in TU), 0 - disable FD frames */ + A_UINT32 fd_period; /* non-zero - enable Fils Discovery frames or broadcast probe response with this period (in TU), + * 0 - disable FD and broadcast probe response frames */ + A_UINT32 flags; /* WMI_FILS_FLAGS_BITMAP flags */ } wmi_enable_fils_cmd_fixed_param; /* @@ -13172,7 +13492,8 @@ typedef struct { /* flags for 11i offload */ #define WMI_ROAM_OFFLOAD_FLAG_OKC_ENABLED 0 /* okc is enabled */ #define WMI_ROAM_OFFLOAD_FLAG_PMK_CACHE_DISABLED 1 /* pmk caching is disabled */ -/* from bit 2 to bit 31 are reserved */ +#define WMI_ROAM_OFFLOAD_FLAG_SAE_SAME_PMKID 2 /* Use same PMKID for WPA3 SAE roaming */ +/* from bit 3 to bit 31 are reserved */ #define WMI_SET_ROAM_OFFLOAD_OKC_ENABLED(flag) do { \ (flag) |= (1 << WMI_ROAM_OFFLOAD_FLAG_OKC_ENABLED); \ @@ -14058,6 +14379,7 @@ typedef enum wake_reason_e { WOW_REASON_PAGE_FAULT, /* Host wake up due to page fault */ WOW_REASON_ROAM_PREAUTH_START, WOW_REASON_ROAM_PMKID_REQUEST, + WOW_REASON_RFKILL, /* add new WOW_REASON_ defs before this line */ WOW_REASON_MAX, @@ -15914,7 +16236,17 @@ typedef struct { A_UINT32 max_duration_ms; /* in milliseconds */ A_UINT32 chan_freq; /* in MHz */ A_UINT32 chan_width; /* in MHz */ - A_UINT32 center_freq; /* in MHz */ + /* + * Two center frequencies are required since agile channel switch + * has to support 160/165 MHz for products like Pine. + * For agile which supports only up to 80MHz (HK), + * freq2 will be 0 and ignored. + */ + union { + A_UINT32 center_freq; /* in MHz */ /* old name */ + A_UINT32 center_freq1; /* in MHz */ /* new name */ + }; + A_UINT32 center_freq2; /* in MHz */ } wmi_vdev_adfs_ch_cfg_cmd_fixed_param; typedef struct { @@ -15952,8 +16284,18 @@ typedef struct { A_UINT32 vdev_id; A_UINT32 chan_freq; /* in MHz */ A_UINT32 chan_width; /* in MHz */ - A_UINT32 center_freq; /* in MHz */ + /* + * Two center frequencies are required since agile channel switch + * has to support 160/165 MHz for products like Pine. + * For agile which supports only up to 80MHz (HK), + * freq2 will be 0 and ignored. + */ + union { + A_UINT32 center_freq; /* in MHz */ /* old name */ + A_UINT32 center_freq1; /* in MHz */ /* new name */ + }; A_UINT32 status; /* WMI_VDEV_OCAC_COMPLETE_STATUS */ + A_UINT32 center_freq2; /* in MHz */ } wmi_vdev_adfs_ocac_complete_event_fixed_param; typedef struct { @@ -17958,11 +18300,22 @@ typedef struct { */ } wmi_nan_cmd_param; +#define WMI_NAN_GET_RANGING_INITIATOR_ROLE(flag) WMI_GET_BITS(flag, 0, 1) +#define WMI_NAN_SET_RANGING_INITIATOR_ROLE(flag, val) WMI_SET_BITS(flag, 0, 1, val) +#define WMI_NAN_GET_RANGING_RESPONDER_ROLE(flag) WMI_GET_BITS(flag, 1, 1) +#define WMI_NAN_SET_RANGING_RESPONDER_ROLE(flag, val) WMI_SET_BITS(flag, 1, 1, val) + typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_host_config_param */ A_UINT32 nan_2g_disc_disable:1; /** This bit when set to 1 indicate NAN 2G discovery should be disabled */ A_UINT32 nan_5g_disc_disable:1; /** This bit when set to 1 indicate NAN 5G discovery should be disabled */ A_UINT32 reserved:30; + /** Flags: refer to WMI_NAN_GET/SET macros + * Bit 0 -> Nan ranging initiator role (0 - Disable, 1 - Enable) + * Bit 1 -> Nan ranging responder role (0 - Disable, 1 - Enable) + * Bits 2-31 -> Reserved + */ + A_UINT32 flags; } wmi_nan_host_config_param_PROTOTYPE; #define wmi_nan_host_config_param wmi_nan_host_config_param_PROTOTYPE @@ -17981,6 +18334,7 @@ typedef struct { A_UINT32 mac_id; /* MAC ID associated with NAN primary discovery channel; Valid only for NAN enable resp message identified by NAN_MSG_ID_ENABLE_RSP */ A_UINT32 status:1; /** This bit when set to 0 indicates status is successful; Valid only for NAN enable resp message identified by NAN_MSG_ID_ENABLE_RSP */ A_UINT32 reserved:31; + A_UINT32 vdev_id; /** Unique id identifying the vdev with type OPMODE_NAN; Valid only for NAN enable resp message identified by NAN_MSG_ID_ENABLE_RSP */ } wmi_nan_event_info_PROTOTYPE; #define wmi_nan_event_info wmi_nan_event_info_PROTOTYPE @@ -18039,6 +18393,17 @@ typedef struct { #define wmi_nan_joined_cluster_event_fixed_param wmi_nan_joined_cluster_event_fixed_param_PROTOTYPE +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_nan_dmesg_event_fixed_param */ + A_UINT32 tlv_header; + /** length in byte of msg[]. */ + A_UINT32 msg_len; + /* Following this structure is the TLV: + * A_UINT8 msg[]; <-- length in byte given by field data_len. + * This data contains the string message which will be given to Host to dump it to kernel logs. + */ +} wmi_nan_dmesg_event_fixed_param; + /** NAN DATA CMD's */ /** @@ -19000,6 +19365,18 @@ typedef struct { wmi_mac_addr peer_macaddr; } wmi_peer_assoc_conf_event_fixed_param; +typedef struct { + /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_create_conf_event_fixed_param */ + A_UINT32 tlv_header; + /* unique id identifying the VDEV, generated by the caller */ + A_UINT32 vdev_id; + /* peer MAC address */ + wmi_mac_addr peer_macaddr; + /* 0: OK. + * 1: FAIL - same bss peer exist already. */ + A_UINT32 status; +} wmi_peer_create_conf_event_fixed_param; + enum { WMI_2G4_HT40_OBSS_SCAN_PASSIVE = 0, /** scan_type: passive */ WMI_2G4_HT40_OBSS_SCAN_ACTIVE, /** scan_type: active */ @@ -22480,8 +22857,9 @@ typedef struct { #define WMI_ATF_DENOMINATION 1000 /* Expressed in 1 part in 1000 (permille) */ -#define WMI_ATF_SSID_FAIR_SCHED 0 /** fair ATF scheduling for vdev */ -#define WMI_ATF_SSID_STRICT_SCHED 1 /** strict ATF scheduling for vdev */ +#define WMI_ATF_SSID_FAIR_SCHED 0 /** fair ATF scheduling for vdev */ +#define WMI_ATF_SSID_STRICT_SCHED 1 /** strict ATF scheduling for vdev */ +#define WMI_ATF_SSID_FAIR_SCHED_WITH_UB 2 /** fair ATF scheduling with upper bound for VDEV */ typedef struct { /** TLV tag and len; tag equals @@ -22504,6 +22882,104 @@ typedef struct { */ } wmi_peer_atf_request_fixed_param; +#define WMI_ATF_GROUP_SCHED_POLICY_BIT_POS 0 +#define WMI_ATF_GROUP_SCHED_POLICY_NUM_BITS 4 + +#define WMI_ATF_GROUP_GET_GROUP_SCHED_POLICY(atf_group_flags) \ + WMI_GET_BITS(atf_group_flags,WMI_ATF_GROUP_SCHED_POLICY_BIT_POS,WMI_ATF_GROUP_SCHED_POLICY_NUM_BITS) + +#define WMI_ATF_GROUP_SET_GROUP_SCHED_POLICY(atf_group_flags,val) \ + WMI_SET_BITS(atf_group_flags,WMI_ATF_GROUP_SCHED_POLICY_BIT_POS,WMI_ATF_GROUP_SCHED_POLICY_NUM_BITS,val) + +typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_atf_group_info */ + A_UINT32 tlv_header; + A_UINT32 atf_group_id; /* ID of the Air Time Management group */ + /* atf_group_units + * Fraction of air time allowed for the group, in per mille units + * (from 0-1000). + * For example, to indicate that the group can use 12.3% of the air time, + * the atf_group_units setting would be 123. + */ + A_UINT32 atf_group_units; + /* atf_group_flags + * Bits 4-31 - Reserved (Shall be zero) + * Bits 0-3 - Group Schedule Policy (Fair/Strict/Fair with upper bound) + * Refer to WMI_ATF_SSID_ definitions + */ + A_UINT32 atf_group_flags; +} wmi_atf_group_info; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_atf_ssid_grp_request_fixed_param */ + A_UINT32 pdev_id; + /* + * Following this structure is the TLV: + * struct wmi_atf_group_info group_info[]; + */ +} wmi_atf_ssid_grp_request_fixed_param; + +/* ATF Configurations for WMM ACs of a group, value for each AC shall be in + * percentage (0-100). + * This perecentage is relative to the residual airtime (derived by FW) + * configured for the group. + * When WMM ATF is not configured for a peer all values shall be 0. + */ +typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_atf_group_wmm_ac_info + */ + A_UINT32 tlv_header; + A_UINT32 atf_group_id; /* ID of the Air Time Management group */ + A_UINT32 atf_units_be; + A_UINT32 atf_units_bk; + A_UINT32 atf_units_vi; + A_UINT32 atf_units_vo; +} wmi_atf_group_wmm_ac_info; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_atf_grp_wmm_ac_cfg_request_fixed_param */ + A_UINT32 pdev_id; + /* + * Following this structure is the TLV: + * struct wmi_atf_group_wmm_ac_info group_info[]; + */ +} wmi_atf_grp_wmm_ac_cfg_request_fixed_param; + +#define WMI_ATF_GROUP_CFG_PEER_BIT_POS 0 +#define WMI_ATF_GROUP_CFG_PEER_NUM_BITS 1 + +#define WMI_ATF_GROUP_GET_CFG_PEER_BIT(atf_peer_flags) \ + WMI_GET_BITS(atf_peer_flags,WMI_ATF_GROUP_CFG_PEER_BIT_POS,WMI_ATF_GROUP_CFG_PEER_NUM_BITS) + +#define WMI_ATF_GROUP_SET_CFG_PEER_BIT(atf_peer_flags,val) \ + WMI_SET_BITS(atf_peer_flags,WMI_ATF_GROUP_CFG_PEER_BIT_POS,WMI_ATF_GROUP_CFG_PEER_NUM_BITS,val) + +typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_peer_atf_ext_info */ + A_UINT32 tlv_header; + wmi_mac_addr peer_macaddr; + A_UINT32 atf_group_id; /* Group Id of the peers for ATF SSID grouping */ + /* atf_peer_flags + * Bits 1-31 - Reserved (Shall be zero) + * Bit 0 - Configured Peer Indication (0/1), this bit would be set by + * host to indicate that the peer has airtime % configured + * explicitly by user. + */ + A_UINT32 atf_peer_flags; +} wmi_peer_atf_ext_info; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_peer_atf_ext_request_fixed_param */ + A_UINT32 pdev_id; + /* + * Following this structure is the TLV: + * struct wmi_peer_atf_ext_info peer_ext_info[]; + */ +} wmi_peer_atf_ext_request_fixed_param; + /* Structure for Bandwidth Fairness peer information */ typedef struct { /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_bwf_peer_info */ @@ -23340,6 +23816,10 @@ typedef enum wmi_coex_config_type { * config BTC separate chain mode or shared mode */ WMI_COEX_CONFIG_BTCOEX_SEPARATE_CHAIN_MODE = 44, + /* WMI_COEX_CONFIG_ENABLE_TPUT_SHAPING + * enable WLAN throughput shaping while BT scanning + */ + WMI_COEX_CONFIG_ENABLE_TPUT_SHAPING = 45, } WMI_COEX_CONFIG_TYPE; typedef struct { @@ -23556,6 +24036,71 @@ typedef struct { wmi_mac_addr leader_mac_addr; } wmi_rmc_manual_leader_event_fixed_param; +typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_audio_sync_start_event_fixed_param + */ + A_UINT32 tlv_header; + /* VDEV identifier */ + A_UINT32 vdev_id; + /* periodicity: + * How frequently (in msec) FW wants host to capture the Q_TIMER. + * periodicity = 0 indicates to the host to stop capturing the QTIMERs. + */ + A_UINT32 periodicity; + /* No of Qtimer captures FW wants */ + A_UINT32 reads_needed; + /* Lower 32 bits of the mac timer. Value is valid only if periodicity = 0 */ + A_UINT32 mac_timer_l32; + /* Upper 32 bits of the mac timer. Value is valid only if periodicity = 0 */ + A_UINT32 mac_timer_u32; + /* Lower 32 bits of the Qtimer. Value is valid only if periodicity = 0 */ + A_UINT32 qtimer_l32; + /* Upper 32 bits of the Qtimer. Value is valid only if periodicity = 0 */ + A_UINT32 qtimer_u32; +} wmi_audio_sync_start_stop_event_fixed_param; + +typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_audio_sync_q_mac_relation_event_fixed_param */ + A_UINT32 tlv_header; + /* VDEV identifier */ + A_UINT32 vdev_id; + /* Lower 32 bits of the offset between Qmaster and Qslave */ + A_UINT32 offset_l32; + /* Upper 32 bits of the offset between Qmaster and Qslave */ + A_UINT32 offset_u32; +} wmi_audio_sync_q_master_slave_offset_event_fixed_param; + +typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_audio_sync_q_mac_relation_event_fixed_param */ + A_UINT32 tlv_header; + /* Lower 32 bits of the Qtimer of master */ + A_UINT32 qmaster_l32; + /* Upper 32 bits of the Qtimer of master */ + A_UINT32 qmaster_u32; + /* Lower 32 bits of the Qtimer of slave*/ + A_UINT32 qslave_l32; + /* Upper 32 bits of the Qtimer of slave*/ + A_UINT32 qslave_u32; +} wmi_audio_sync_q_master_slave_times; + +/** Set Preferred Channel List **/ +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_set_pcl_cmd_fixed_param */ + /** vdev_id */ + A_UINT32 vdev_id; +/** + * TLV (tag length value) parameters follow the wmi_vdev_set_pcl_cmd + * structure. The TLV's are: + * + * A_UINT32 channel_weight[]; + * values definied by enum 'wmi_pcl_chan_weight' + * channel order & size will be as per the list provided in WMI_SCAN_CHAN_LIST_CMDID + **/ +} wmi_vdev_set_pcl_cmd_fixed_param; + typedef enum { WLAN_2G_CAPABILITY = 0x1, WLAN_5G_CAPABILITY = 0x2, @@ -23598,6 +24143,74 @@ typedef enum wmi_hw_mode_config_type { #define WMI_MAX_MUBFEE_GET(flags) WMI_GET_BITS(flags, 28, 4) #define WMI_MAX_MUBFEE_SET(flags, value) WMI_SET_BITS(flags, 28, 4, value) +/* + * +-----------------------------+------------------------------------+ + * | Transmitted VHT Capablities | NSS Support of STA | + * | Information Field | transmitted VHT Capablites | + * +---------------+-------------+------+------+------+------+--------+ + * | Supported | Extended | | | | | | + * | Channel | NSS BW | | | | | | + * | WidthSet | Suppport |20 Mhz|40 Mhz|80 Mhz|160Mhz|80+80Mhz| + * +---------------+-------------+------+------+------+------+--------+ + * | 0 | 0 | 1 | 1 | 1 | | | + * +---------------+-------------+------+------+------+------+--------+ + * | 0 | 1 | 1 | 1 | 1 | 1/2 | | + * +---------------+-------------+------+------+------+------+--------+ + * | 0 | 2 | 1 | 1 | 1 | 1/2 | 1/2 | + * +---------------+-------------+------+------+------+------+--------+ + * | 0 | 3 | 1 | 1 | 1 | 3/4 | 3/4 | + * +---------------+-------------+------+------+------+------+--------+ + * | 1 | 0 | 1 | 1 | 1 | 1 | | + * +---------------+-------------+------+------+------+------+--------+ + * | 1 | 1 | 1 | 1 | 1 | 1 | 1/2 | + * +---------------+-------------+------+------+------+------+--------+ + * | 1 | 2 | 1 | 1 | 1 | 1 | 3/4 | + * +---------------+-------------+------+------+------+------+--------+ + * | 1 | 3 | 2 | 2 | 2 | 2 | 1 | + * +---------------+-------------+------+------+------+------+--------+ + * | 2 | 0 | 1 | 1 | 1 | 1 | 1 | + * +---------------+-------------+------+------+------+------+--------+ + * | 2 | 3 | 2 | 2 | 2 | 1 | 1 | + * +---------------+-------------+------+------+------+------+--------+ + */ + +/* + * [0] : WMI_NSS_RATIO_ENABLE_DISABLE_BITPOS + * [4:1] : WMI_NSS_RATIO_INFO_BITPOS + */ +#define WMI_NSS_RATIO_ENABLE_DISABLE_BITPOS 0x0 +#define WMI_NSS_RATIO_INFO_BITPOS 0x1 + +/* + * WMI_NSS_RATIO_ENABLE_DISABLE values: + * [0] : 0 - WMI_NSS_RATIO_DISABLE + * [0] : 1 - WMI_NSS_RATIO_ENABLE + */ +#define WMI_NSS_RATIO_DISABLE 0x0 +#define WMI_NSS_RATIO_ENABLE 0x1 + +/* + * WMI_NSS_RATIO_INFO values: + * [4:1] : 0000 - WMI_NSS_RATIO_1BY2_NSS + * [4:1] : 0001 - WMI_NSS_RATIO_3BY4_NSS + * [4:1] : 0010 - WMI_NSS_RATIO_1_NSS + * [4:1] : 0011 - WMI_NSS_RATIO_2_NSS + */ +#define WMI_NSS_RATIO_1BY2_NSS 0x0 +#define WMI_NSS_RATIO_3BY4_NSS 0x1 +#define WMI_NSS_RATIO_1_NSS 0x2 +#define WMI_NSS_RATIO_2_NSS 0x3 + +#define WMI_NSS_RATIO_ENABLE_DISABLE_SET(param, value) \ + WMI_SET_BITS(param, WMI_NSS_RATIO_ENABLE_DISABLE_BITPOS, 1, value) +#define WMI_NSS_RATIO_ENABLE_DISABLE_GET(dword) \ + WMI_GET_BITS(dword, WMI_NSS_RATIO_ENABLE_DISABLE_BITPOS, 1) + +#define WMI_NSS_RATIO_INFO_SET(param, value) \ + WMI_SET_BITS(param, WMI_NSS_RATIO_INFO_BITPOS, 4, value) +#define WMI_NSS_RATIO_INFO_GET(dword) \ + WMI_GET_BITS(dword, WMI_NSS_RATIO_INFO_BITPOS, 4) + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_WMI_MAC_PHY_CAPABILITIES */ /* hw_mode_id - identify a particular set of HW characteristics, as specified @@ -23749,6 +24362,23 @@ typedef struct { A_UINT32 high_2ghz_chan_freq; /* units = MHz */ A_UINT32 low_5ghz_chan_freq; /* units = MHz */ A_UINT32 high_5ghz_chan_freq; /* units = MHz */ + + /* + * NSS ratio to be sent to Host during boot-up capabilities negotiation + * + * Bit 0 - refer to WMI_NSS_RATIO_ENABLE_DISABLE_ definitions + * [0] : 0 - WMI_NSS_RATIO_DISABLE + * [0] : 1 - WMI_NSS_RATIO_ENABLE + * + * Bits 4:1 - refer to WMI_NSS_RATIO_INFO_ definitions + * [4:1] : 0000 - WMI_NSS_RATIO_1BY2_NSS + * [4:1] : 0001 - WMI_NSS_RATIO_3BY4_NSS + * [4:1] : 0010 - WMI_NSS_RATIO_1_NSS + * [4:1] : 0011 - WMI_NSS_RATIO_2_NSS + * + * [31:5] : Reserved + */ + A_UINT32 nss_ratio; } WMI_MAC_PHY_CAPABILITIES; typedef struct { @@ -23790,6 +24420,15 @@ typedef struct { #define WMI_SUPPORT_CHAN_WIDTH_80P80_GET(flags) WMI_GET_BITS(flags, 4, 1) #define WMI_SUPPORT_CHAN_WIDTH_80P80_SET(flags, value) WMI_SET_BITS(flags, 4, 1, value) +#define WMI_SUPPORT_AGILE_SPECTRAL_GET(flags) WMI_GET_BITS(flags, 5, 1) +#define WMI_SUPPORT_AGILE_SPECTRAL_SET(flags, value) WMI_SET_BITS(flags, 5, 1, value) + +#define WMI_SUPPORT_AGILE_SPECTRAL_160_GET(flags) WMI_GET_BITS(flags, 6, 1) +#define WMI_SUPPORT_AGILE_SPECTRAL_160_SET(flags, value) WMI_SET_BITS(flags, 6, 1, value) + +#define WMI_SUPPORT_ADFS_160_GET(flags) WMI_GET_BITS(flags, 7, 1) +#define WMI_SUPPORT_ADFS_160_SET(flags, value) WMI_SET_BITS(flags, 7, 1, value) + #define WMI_SUPPORT_CHAIN_MASK_2G_GET(flags) WMI_GET_BITS(flags, 27, 1) #define WMI_SUPPORT_CHAIN_MASK_2G_SET(flags, value) WMI_SET_BITS(flags, 27, 1, value) @@ -23816,7 +24455,10 @@ typedef struct { supports_chan_width_80:1, supports_chan_width_160:1, supports_chan_width_80P80:1, - reserved:22, /* bits 26:5 */ + supports_agile_spectral:1, + supports_agile_spectral_160:1, + supports_aDFS_160:1, + reserved:19, /* bits 26:8 */ chain_mask_2G:1, chain_mask_5G:1, chain_mask_tx:1, @@ -24716,7 +25358,19 @@ static INLINE A_UINT8 *wmi_id_to_name(A_UINT32 wmi_command) WMI_RETURN_STRING(WMI_AUDIO_AGGR_DEL_GROUP_CMDID); WMI_RETURN_STRING(WMI_AUDIO_AGGR_SET_GROUP_RATE_CMDID); WMI_RETURN_STRING(WMI_AUDIO_AGGR_SET_GROUP_RETRY_CMDID); + WMI_RETURN_STRING(WMI_AUDIO_AGGR_UPDATE_STA_GROUP_INFO_CMDID); WMI_RETURN_STRING(WMI_CFR_CAPTURE_FILTER_CMDID); + WMI_RETURN_STRING(WMI_ATF_SSID_GROUPING_REQUEST_CMDID); + WMI_RETURN_STRING(WMI_ATF_GROUP_WMM_AC_CONFIG_REQUEST_CMDID); + WMI_RETURN_STRING(WMI_PEER_ATF_EXT_REQUEST_CMDID); + WMI_RETURN_STRING(WMI_GET_CHANNEL_ANI_CMDID); + WMI_RETURN_STRING(WMI_SET_OCL_CMDID); + WMI_RETURN_STRING(WMI_AUDIO_AGGR_SET_GROUP_AUTO_RATE_CMDID); + WMI_RETURN_STRING(WMI_AUDIO_AGGR_SET_GROUP_PROBE_CMDID); + WMI_RETURN_STRING(WMI_VDEV_AUDIO_SYNC_TRIGGER_CMDID); + WMI_RETURN_STRING(WMI_VDEV_AUDIO_SYNC_QTIMER_CMDID); + WMI_RETURN_STRING(WMI_ROAM_GET_SCAN_CHANNEL_LIST_CMDID); + WMI_RETURN_STRING(WMI_VDEV_GET_BIG_DATA_CMDID); } return "Invalid WMI cmd"; @@ -24971,6 +25625,16 @@ typedef struct { A_UINT32 hw_filter_bitmap; /* see WMI_HW_DATA_FILTER_BITMAP_TYPE */ } wmi_hw_data_filter_cmd_fixed_param; +/** values for multiple_vdev_restart_request flags */ +/* Host is expecting consolidated Multiple Vdev Restart Response(MVRR) event. */ +#define WMI_MULTIPLE_VDEV_RESTART_FLAG_IS_MVRR_EVENT_SUPPORT(flag) WMI_GET_BITS(flag, 0, 1) +#define WMI_MULTIPLE_VDEV_RESTART_FLAG_SET_MVRR_EVENT_SUPPORT(flag,val) WMI_SET_BITS(flag, 0, 1, val) +/* Host is sending phymode_list for each vdev. */ +#define WMI_MULTIPLE_VDEV_RESTART_FLAG_IS_PHYMODE_PRESENT(flag) WMI_GET_BITS(flag, 1, 1) +#define WMI_MULTIPLE_VDEV_RESTART_FLAG_SET_PHYMODE_PRESENT(flag,val) WMI_SET_BITS(flag, 1, 1, val) +#define WMI_MULTIPLE_VDEV_RESTART_FLAG_GET_PHYMODE(phymode) WMI_GET_BITS(phymode, 0, 6) +#define WMI_MULTIPLE_VDEV_RESTART_FLAG_SET_PHYMODE(phymode, val) WMI_SET_BITS(phymode, 0, 6, val) + /* This command is used whenever host wants to restart multiple * VDEVs using single command and the VDEV that are restarted will * need to have same properties they had before restart except for the @@ -24992,10 +25656,20 @@ typedef struct { /* Determine the duration of CAC on the given channel 'chan' */ A_UINT32 cac_duration_ms; A_UINT32 num_vdevs; + /* + * Flags to indicate which parameters are sent as part of the request. + * This field is filled with the bitwise combination of the flag values + * defined by WMI_MULTIPLE_VDEV_RESTART_FLAG_xxx + */ + A_UINT32 flags; /* The TLVs follows this structure: * A_UINT32 vdev_ids[]; <--- Array of VDEV ids. * wmi_channel chan; <------ WMI channel + * A_UINT32 phymode_list[]; <-- Array of Phymode list, with + * each phymode value stored in bits 5:0 of the A_UINT32. + * Use the WMI_MULTIPLE_VDEV_RESTART_FLAG_GET/SET_PHYMODE macros + * to access the phymode value from within each A_UINT32 element. */ } wmi_pdev_multiple_vdev_restart_request_cmd_fixed_param; @@ -25910,9 +26584,29 @@ typedef enum { WMI_ROAM_TRIGGER_REASON_BSS_LOAD, WMI_ROAM_TRIGGER_REASON_DEAUTH, WMI_ROAM_TRIGGER_REASON_IDLE, + /* + * NOTE: don't add any more ROAM_TRIGGER_REASON values here. + * There are checks in the FW that require the value of + * WMI_ROAM_TRIGGER_REASON_MAX to be < 16. + * Add new ROAM_TRIGGER_REASON values below, inside the + * WMI_ROAM_TRIGGER_EXT_REASON_ID enum. + */ WMI_ROAM_TRIGGER_REASON_MAX, } WMI_ROAM_TRIGGER_REASON_ID; +/* + * The WMI_ROAM_TRIGGER_REASON_ID enum cannot be expanded with new values, + * due to checks in the FW that require WMI_ROAM_TRIGGER_REASON_MAX to be + * less than 16. + * The WMI_ROAM_TRIGGER_EXT_REASON_ID enum is used to hold further roam + * trigger reasons. + */ +typedef enum { + WMI_ROAM_TRIGGER_REASON_STA_KICKOUT = WMI_ROAM_TRIGGER_REASON_MAX, + + WMI_ROAM_TRIGGER_EXT_REASON_MAX +} WMI_ROAM_TRIGGER_EXT_REASON_ID; + /* value for DENSE roam trigger */ #define WMI_RX_TRAFFIC_ABOVE_THRESHOLD 0x1 #define WMI_TX_TRAFFIC_ABOVE_THRESHOLD 0x2 @@ -26171,6 +26865,306 @@ typedef struct { */ } wmi_roam_scan_stats_event_fixed_param; +typedef enum { + WMI_ROAM_TRIGGER_SUB_REASON_PERIODIC_TIMER = 1, /* Roam scan triggered due to periodic timer expiry */ + WMI_ROAM_TRIGGER_SUB_REASON_INACTIVITY_TIMER, /* Roam scan triggered due to inactivity detection */ + WMI_ROAM_TRIGGER_SUB_REASON_BTM_DI_TIMER, /* Roam scan triggered due to BTM Disassoc Imminent timeout */ + WMI_ROAM_TRIGGER_SUB_REASON_FULL_SCAN, /* Roam scan triggered due to partial scan failure */ + WMI_ROAM_TRIGGER_SUB_REASON_LOW_RSSI_PERIODIC, /* Roam scan triggered due to Low rssi periodic timer */ + WMI_ROAM_TRIGGER_SUB_REASON_CU_PERIODIC, /* Roam scan triggered due to CU periodic timer */ +} WMI_ROAM_TRIGGER_SUB_REASON_ID; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_trigger_reason_tlv_param */ + /* + * timestamp is the absolute time w.r.t host timer which is synchronized + * between the host and target. + * This timestamp indicates the time when roam trigger happened. + */ + A_UINT32 timestamp; /* Timestamp in milli seconds */ + /* trigger_reason: + * Roam trigger reason from WMI_ROAM_TRIGGER_REASON_ID + */ + A_UINT32 trigger_reason; + /* trigger_sub_reason: + * Reason for each roam scan from WMI_ROAM_TRIGGER_SUB_REASON_ID, + * if multiple scans are triggered for a single roam trigger. + */ + A_UINT32 trigger_sub_reason; + A_UINT32 current_rssi; /* Connected AP rssi in dBm */ + /* roam_rssi_threshold: + * RSSI threshold value in dBm for low RSSI roam trigger. + */ + A_UINT32 roam_rssi_threshold; + A_UINT32 cu_load; /* Connected AP CU load percentage (0-100) */ + /* deauth_type: + * 1 -> De-authentication + * 2 -> Disassociation + */ + A_UINT32 deauth_type; + /* deauth_reason: + * De-authentication or disassociation reason. + * De-authentication / disassociation Values are enumerated in the + * 802.11 spec. + */ + A_UINT32 deauth_reason; + /* btm_request_mode: + * Mode Values are enumerated in the 802.11 spec. + */ + A_UINT32 btm_request_mode; + A_UINT32 disassoc_imminent_timer; /* in Milli seconds */ + /* validity_internal: + * Preferred candidate list validity interval in Milli seconds. + */ + A_UINT32 validity_internal; + /* candidate_list_count: + * Number of preferred candidates from BTM request. + */ + A_UINT32 candidate_list_count; + /* btm_response_status_code: + * Response status Values are enumerated in the 802.11 spec. + */ + A_UINT32 btm_response_status_code; +} wmi_roam_trigger_reason; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_scan_info_tlv_param */ + /* roam_scan_type: + * 0 -> Partial roam scan + * 1 -> Full roam scan + */ + A_UINT32 roam_scan_type; + /* next_rssi_trigger_threshold: + * Updated RSSI threshold value in dBm for next roam trigger. + */ + A_UINT32 next_rssi_trigger_threshold; + A_UINT32 roam_scan_channel_count; /* Number of channels scanned during roam scan */ + A_UINT32 roam_ap_count; /* Number of roamable APs */ + A_UINT32 frame_info_count; /* Number of frame info */ +} wmi_roam_scan_info; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_scan_channel_info_tlv_param */ + A_UINT32 channel; /* Channel frequency in MHz */ +} wmi_roam_scan_channel_info; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_ap_info_tlv_param */ + /* + * timestamp is the absolute time w.r.t host timer which is synchronized + * between the host and target. + * This timestamp indicates the time when candidate AP is found + * during roam scan. + */ + A_UINT32 timestamp; /* Timestamp in milli seconds */ + A_UINT32 candidate_type; /* 0 - Candidate AP, 1 - Connected AP */ + wmi_mac_addr bssid; /* AP MAC address */ + A_UINT32 channel; /* AP channel frequency in MHz */ + A_UINT32 rssi; /* AP current rssi in dBm */ + A_UINT32 cu_load; /* AP current cu load percentage (0-100) */ + /* + * The score fields below don't have a pre-determined range, + * but use the sense that a higher score indicates a better + * roam candidate. + */ + A_UINT32 rssi_score; /* AP current rssi score */ + A_UINT32 cu_score; /* AP current cu score */ + A_UINT32 total_score; /* AP total score */ + A_UINT32 etp; /* AP Estimated Throughput (ETP) value in mbps */ +} wmi_roam_ap_info; + +typedef enum { + /* Failures reasons for not triggering roaming */ + WMI_ROAM_FAIL_REASON_NO_SCAN_START = 1, /* Roam scan not started */ + WMI_ROAM_FAIL_REASON_SCAN_NOT_ALLOWED = WMI_ROAM_FAIL_REASON_NO_SCAN_START, /* Roam scan is not allowed to start */ + WMI_ROAM_FAIL_REASON_NO_AP_FOUND, /* No roamable APs found during roam scan */ + WMI_ROAM_FAIL_REASON_NO_CAND_AP_FOUND, /* No candidate APs found during roam scan */ + + /* Failure reasons after roaming is triggered */ + WMI_ROAM_FAIL_REASON_HOST, /* Roam fail due to VDEV STOP issued from Host */ + WMI_ROAM_FAIL_REASON_AUTH_SEND, /* Unable to send auth request frame */ + WMI_ROAM_FAIL_REASON_AUTH_RECV, /* Received auth response with error status code */ + WMI_ROAM_FAIL_REASON_NO_AUTH_RESP, /* Not receiving auth response frame */ + WMI_ROAM_FAIL_REASON_REASSOC_SEND, /* Unable to send reassoc request frame */ + WMI_ROAM_FAIL_REASON_REASSOC_RECV, /* Received reassoc response with error status code */ + WMI_ROAM_FAIL_REASON_NO_REASSOC_RESP, /* Not receiving reassoc response frame */ + WMI_ROAM_FAIL_REASON_EAPOL_TIMEOUT, /* EAPOL TIMEOUT */ + WMI_ROAM_FAIL_REASON_EAPOL_M1_TIMEOUT = WMI_ROAM_FAIL_REASON_EAPOL_TIMEOUT, /* EAPOL M1 is not received */ + WMI_ROAM_FAIL_REASON_MLME, /* MLME internal error */ + WMI_ROAM_FAIL_REASON_INTERNAL_ABORT, /* Internal abort */ + WMI_ROAM_FAIL_REASON_SCAN_START, /* Unable to start roam scan */ + WMI_ROAM_FAIL_REASON_AUTH_NO_ACK, /* No ACK is received for Auth request */ + WMI_ROAM_FAIL_REASON_AUTH_INTERNAL_DROP, /* Auth request is dropped internally */ + WMI_ROAM_FAIL_REASON_REASSOC_NO_ACK, /* No ACK is received for Reassoc request */ + WMI_ROAM_FAIL_REASON_REASSOC_INTERNAL_DROP, /* Reassoc request is dropped internally */ + WMI_ROAM_FAIL_REASON_EAPOL_M2_SEND, /* Unable to send EAPOL M2 frame */ + WMI_ROAM_FAIL_REASON_EAPOL_M2_INTERNAL_DROP, /* EAPOL M2 frame dropped internally */ + WMI_ROAM_FAIL_REASON_EAPOL_M2_NO_ACK, /* No Ack is recieved for EAPOL M2 frame */ + WMI_ROAM_FAIL_REASON_EAPOL_M3_TIMEOUT, /* M3 is not received */ + WMI_ROAM_FAIL_REASON_EAPOL_M4_SEND, /* Unable to send EAPOL M4 frame */ + WMI_ROAM_FAIL_REASON_EAPOL_M4_INTERNAL_DROP, /* EAPOL M4 frame dropped internally */ + WMI_ROAM_FAIL_REASON_EAPOL_M4_NO_ACK, /* No Ack is recieved for EAPOL M4 frame */ + + + WMI_ROAM_FAIL_REASON_UNKNOWN = 255, +} WMI_ROAM_FAIL_REASON_ID; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_result_tlv_param */ + /* + * timestamp is the absolute time w.r.t host timer which is synchronized + * between the host and target. + * This timestamp indicates the time when roaming is completed. + */ + A_UINT32 timestamp; /* Timestamp in milli seconds */ + A_UINT32 roam_status; /* 0 - Roaming is success, 1 - Roaming is failed */ + A_UINT32 roam_fail_reason; /* from WMI_ROAM_FAIL_REASON_ID */ +} wmi_roam_result; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_neighbor_report_info_tlv_param */ + /* request_type: + * 1 -> BTM query + * 2 -> 11K neighbor report request + */ + A_UINT32 request_type; + /* neighbor_report_request_timestamp: + * timestamp is the absolute time w.r.t host timer which is synchronized + * between the host and target. + * This timestamp indicates the time when neighbor report request + * is received. + */ + A_UINT32 neighbor_report_request_timestamp; /* in milli seconds */ + /* neighbor_report_response_timestamp: + * This timestamp indicates the time when neighbor report response is sent. + */ + A_UINT32 neighbor_report_response_timestamp; /* in milli seconds */ + A_UINT32 neighbor_report_channel_count; /* Number of channels received in neighbor report response */ +} wmi_roam_neighbor_report_info; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_neighbor_report_channel_info_tlv_param */ + A_UINT32 channel; /* Channel frequency in MHz */ +} wmi_roam_neighbor_report_channel_info; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_frame_info_tlv_param */ + /* timestamp is the absolute time w.r.t host timer which is synchronized between the host and target */ + A_UINT32 timestamp; /* Timestamp when frame is sent or received */ + /* + * frame_info = frame_type | (frame_subtype << 2) | (request_or_response << 6)| (seq_num << 16) + * frame_type(2 bits), frame_subtype(4 bits) are from 802.11 spec. + * request_or_response(1 bit) - Valid if frame_subtype is authentication. + * 0 - Authentication request 1 - Authentication response + * seq_num(16 bits) - frame sequence number + */ + A_UINT32 frame_info; + A_UINT32 status_code; /* Status code from 802.11 spec, section 9.4.1.9 */ +} wmi_roam_frame_info; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_stats_event_fixed_param */ + A_UINT32 vdev_id; + A_UINT32 roam_scan_trigger_count; /* Number of roam scans triggered */ +} wmi_roam_stats_event_fixed_param; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_get_scan_channel_list_cmd_fixed_param */ + A_UINT32 vdev_id; +} wmi_roam_get_scan_channel_list_cmd_fixed_param; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_roam_scan_channel_list_event_fixed_param */ + A_UINT32 vdev_id; + wmi_ssid ssid; /* SSID of connected AP */ + /* + * This event can be sent as a response to + * WMI_ROAM_GET_SCAN_CHANNEL_LIST_CMDID or + * can be sent asynchronously during disconnection. + * command_response = 1, when it is sent as a response to + * WMI_ROAM_GET_SCAN_CHANNEL_LIST_CMDID + * = 0, for other cases + */ + A_UINT32 command_response; +/* + * This fixed_param TLV is followed by the below TLVs: + * + * List of roam scan channel frequencies in MHz + * A_UINT32 channel_list[]; + */ +} wmi_roam_scan_channel_list_event_fixed_param; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_get_big_data_cmd_fixed_param */ + A_UINT32 vdev_id; +} wmi_vdev_get_big_data_cmd_fixed_param; + +typedef struct { + A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_vdev_send_big_data_event_fixed_param */ + A_UINT32 vdev_id; + /** param list **/ + /* Target power (dBm units) - 2.4G/5G */ + A_UINT32 target_power_2g_dsss; + A_UINT32 target_power_2g_ofdm; + A_UINT32 target_power_2g_mcs0; + A_UINT32 target_power_5g_ofdm; + A_UINT32 target_power_5g_mcs0; + + /* ANI level from hal-phy */ + A_UINT32 ani_level; + + /* Number of probe requests sent while roaming after BMISS */ + A_UINT32 tx_probe_req; + + /* Number of probe responses received while roaming after BMISS */ + A_UINT32 rx_probe_response; + + /* + * Number of retries (both by HW and FW) for tx data MPDUs sent by this vdev + */ + A_UINT32 num_data_retries; + + /* Number of tx data MPDUs dropped from this vdev due to tx retry limit */ + A_UINT32 num_tx_data_fail; + + /* Number of aggregated unicast tx expecting response ppdu */ + A_UINT32 data_tx_ppdu_count; + + /* Number of aggregated unicast tx expecting response mpdu */ + A_UINT32 data_tx_mpdu_count; + + /* number of rx frames with good PCLP */ + A_UINT32 rx_frame_good_pclp_count; + + /* Number of occasions that no valid delimiter is detected by ampdu parser */ + A_UINT32 invalid_delimiter_count; + + /* Number of frames for which the CRC check failed in the MAC */ + A_UINT32 rx_crc_check_fail_count; + + /* tx fifo overflows count for transmissions by this vdev */ + A_UINT32 txpcu_fifo_overflows_count; + + /* Number of ucast ACKS received good FCS (doesn't include block acks) */ + A_UINT32 successful_acks_count; + + /* + * RX BlockACK Counts + * Note that this counts the number of block acks received by this vdev, + * not the number of MPDUs acked by block acks. + */ + A_UINT32 rx_block_ack_count; + + /* Beacons received from member of BSS */ + A_UINT32 member_bss_beacon_count; + + /* Beacons received from other BSS */ + A_UINT32 non_bss_beacon_count; + + /* Number of RX Data multicast frames dropped by the HW */ + A_UINT32 rx_data_mc_frame_filtered_count; +} wmi_vdev_send_big_data_event_fixed_param; + typedef struct { A_UINT32 tlv_header; /* TLV tag and len; tag equals wmi_txpower_query_cmd_fixed_param */ A_UINT32 request_id; /* unique request ID to distinguish the command / event set */ @@ -27795,33 +28789,76 @@ typedef struct { A_UINT32 en_dis; } wmi_get_elna_bypass_event_fixed_param; +typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_get_channel_ani_cmd_fixed_param + */ + A_UINT32 tlv_header; + /** + * TLV (tag length value) parameters follow the + * structure. The TLV's are: + * list of channels (center freq of primary 20 MHz of the channel, in MHz) + * A_UINT32 channel_list[]; + */ +} wmi_get_channel_ani_cmd_fixed_param; + +typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_get_channel_ani_event_fixed_param + */ + A_UINT32 tlv_header; + /** + * TLV (tag length value) parameters follow the + * structure. The TLV's are: + * wmi_channel_ani_info_tlv_param ani_info[]; + */ +} wmi_get_channel_ani_event_fixed_param; + +typedef struct { + /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_channel_ani_info_tlv_param */ + A_UINT32 tlv_header; + /** channel freq (center of 20 MHz primary channel) in MHz */ + A_UINT32 chan_freq; + /** + * ANI (noise interference) level corresponding to the channel. + * Values range from [0-9], with higher values indicating more + * noise interference. + */ + A_UINT32 ani_level; +} wmi_channel_ani_info_tlv_param; + /* This command is to specify to enable/disable audio frame aggr */ typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_audio_aggr_enable_cmd_fixed_param */ A_UINT32 aggr_enable; /* enable aggregation for audio frame */ A_UINT32 tbd_enable; /* enable time_based discarding for audio frame */ + A_UINT32 vdev_id; } wmi_audio_aggr_enable_cmd_fixed_param; typedef struct wmi_audio_aggr_rate_set_s { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_audio_aggr_rate_set */ A_UINT32 mcs; A_UINT32 bandwidth; /* 0 for 20M, 1 for 40M and 2 for 80M, etc. */ + A_UINT32 vdev_id; } WMI_AUDIO_AGGR_RATE_SET_T; typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_audio_aggr_add_group */ A_UINT32 group_id; /* id of audio group */ wmi_mac_addr multicast_addr; /* multicast address of audio group */ + A_UINT32 vdev_id; } wmi_audio_aggr_add_group_cmd_fixed_param; typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_audio_aggr_del_group */ A_UINT32 group_id; + A_UINT32 vdev_id; } wmi_audio_aggr_del_group_cmd_fixed_param; typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_audio_aggr_set_group_rate */ A_UINT32 group_id; + A_UINT32 vdev_id; /** * TLV (tag length value) parameters follow the * structure. The TLV's are: @@ -27833,8 +28870,84 @@ typedef struct { A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_audio_aggr_set_group_retry */ A_UINT32 group_id; A_UINT32 retry_thresh; + A_UINT32 vdev_id; } wmi_audio_aggr_set_group_retry_cmd_fixed_param; +typedef struct { + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 group_id; + /* + * bit0: if set, Enable HT20 + * bit1: if set, Enable HT40 + * bit2, bit3: Reserved + * bit4: if set, Enable VHT20 + * bit5: if set, Enable VHT40 + * bit6: if set, Enable VHT80 + * bit7 ~ bit31: Reserved + */ + A_UINT32 bw; + A_UINT32 mcs_min; + A_UINT32 mcs_max; + A_UINT32 mcs_offset; + A_UINT32 nss; +} wmi_audio_aggr_set_group_auto_rate_cmd_fixed_param; + +typedef struct { + A_UINT32 tlv_header; + A_UINT32 vdev_id; + A_UINT32 group_id; + A_UINT32 interval; +} wmi_audio_aggr_set_group_probe_cmd_fixed_param; + +typedef struct { + /** + * TLV tag and len; + * tag equals WMITLV_TAG_STRUC_wmi_audio_aggr_update_sta_group_info */ + A_UINT32 tlv_header; + + /* vdev id */ + A_UINT32 vdev_id; /* which STA/vdev's group membership is being specified */ + + /* bitmap that indicates which groups this sta belongs to */ + A_UINT32 group_bmap; + +/* + * This fixed_param struct is followed by a TLV array of wmi_mac_addr, + * which specifies the multi-cast MAC address used for each group. + * The number of elements within the TLV array matches the number of bits + * set within group_bmap. + */ +} wmi_audio_aggr_update_sta_group_info_cmd_fixed_param; + +typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_set_ocl_cmd_fixed_param */ + A_UINT32 tlv_header; + /* VDEV identifier */ + A_UINT32 vdev_id; + /** enable/disable OCL, 1 - enable, 0 - disable*/ + A_UINT32 en_dis_chain; +} wmi_set_ocl_cmd_fixed_param; + +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_audio_sync_qtimer */ + A_UINT32 vdev_id; + A_UINT32 qtimer_l32; + A_UINT32 qtimer_u32; +} wmi_audio_sync_qtimer_cmd_fixed_param; + +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_audio_sync_trigger */ + A_UINT32 vdev_id; + /* agg_relation: + * indicates whether host needs only one pair of Qmaster and Qslave, + * or Qmaster and Qslave pairs derived for each FTM frame exchange. + * 0 indicates one pair for each FTM frame exchanged + * 1 indicates only one pair of Qmaster and Qslave times. + */ + A_UINT32 agg_relation; +} wmi_audio_sync_trigger_cmd_fixed_param; #define WMI_CFR_GROUP_TA_ADDR_VALID_BIT_POS 0 #define WMI_CFR_GROUP_TA_ADDR_MASK_VALID_BIT_POS 1 @@ -27926,6 +29039,9 @@ typedef struct { WMI_GET_BITS(param, WMI_CFR_GROUP_NSS_BIT_POS, WMI_CFR_GROUP_NSS_MASK_NUM_BITS) typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_cfr_filter_group_config */ + A_UINT32 tlv_header; /* Filter group number for which the below filters needs to be applied */ A_UINT32 filter_group_id; /* Indicates which of the below filter's value is valid @@ -28040,7 +29156,8 @@ typedef struct { #define WMI_CFR_NDPA_NDP_ALL_EN_SET(param, value) \ WMI_SET_BITS(param, WMI_CFR_NDPA_NDP_ALL_EN_BIT_POS, 1, value) -#define WWMI_CFR_NDPA_NDP_ALL_EN_GET(param) \ +#define WWMI_CFR_NDPA_NDP_ALL_EN_GET WMI_CFR_NDPA_NDP_ALL_EN_GET +#define WMI_CFR_NDPA_NDP_ALL_EN_GET(param) \ WMI_GET_BITS(param, WMI_CFR_NDPA_NDP_ALL_EN_BIT_POS, 1) #define WMI_CFR_TA_RA_TYPE_FILTER_EN_SET(param, value) \ @@ -28049,7 +29166,8 @@ typedef struct { #define WMI_CFR_TA_RA_TYPE_FILTER_EN_GET(param) \ WMI_GET_BITS(param, WMI_CFR_TA_RA_TYPE_FILTER_EN_BIT_POS, 1) -#define WWMI_CFR_ALL_PACKET_EN_SET(param, value) \ +#define WWMI_CFR_ALL_PACKET_EN_SET WMI_CFR_ALL_PACKET_EN_SET +#define WMI_CFR_ALL_PACKET_EN_SET(param, value) \ WMI_SET_BITS(param, WMI_CFR_ALL_PACKET_EN_BIT_POS, 1, value) #define WMI_CFR_ALL_PACKET_EN_GET(param) \ @@ -28163,6 +29281,151 @@ typedef struct { */ } wmi_cfr_capture_filter_cmd_fixed_param; +typedef struct { + A_UINT32 tlv_header; /** TLV tag and len; tag equals WMITLV_TAG_STRUC_wmi_oem_data_event_fixed_param */ + A_UINT32 data_len; /** length in byte of data[]. */ +/* Following this structure is the TLV: + * A_UINT8 data[]; <-- length in byte given by field data_len. + * This data array contains OEM data, the payload begins with a field to tell the HOST regarding the kind of the OEM data. + */ +} wmi_oem_data_event_fixed_param; + +#define WMI_VLAN_TX_BIT_POS 0 +#define WMI_VLAN_RX_BIT_POS 1 +#define WMI_TX_INSERT_OR_STRIP_BIT_POS 2 +#define WMI_TX_STRIP_INSERT_VLAN_INNER_BIT_POS 3 +#define WMI_TX_STRIP_INSERT_VLAN_OUTER_BIT_POS 4 +#define WMI_RX_STRIP_VLAN_C_TAG_BIT_POS 5 +#define WMI_RX_STRIP_VLAN_S_TAG_BIT_POS 6 +#define WMI_RX_INSERT_VLAN_C_TAG_BIT_POS 7 +#define WMI_RX_INSERT_VLAN_S_TAG_BIT_POS 8 + +#define WMI_TX_INSERT_VLAN_INNER_TCI_NUM_BITS 16 +#define WMI_TX_INSERT_VLAN_INNER_TCI_BIT_POS 0 + +#define WMI_TX_INSERT_VLAN_OUTER_TCI_NUM_BITS 16 +#define WMI_TX_INSERT_VLAN_OUTER_TCI_BIT_POS 16 + + +#define WMI_VLAN_TX_SET(param, value) \ + WMI_SET_BITS(param, WMI_VLAN_TX_BIT_POS, 1, value) + +#define WMI_VLAN_TX_GET(param) \ + WMI_GET_BITS(param, WMI_VLAN_TX_BIT_POS, 1) + +#define WMI_VLAN_RX_SET(param, value) \ + WMI_SET_BITS(param, WMI_VLAN_RX_BIT_POS, 1, value) + +#define WMI_VLAN_RX_GET(param) \ + WMI_GET_BITS(param, WMI_VLAN_RX_BIT_POS, 1) + +#define WMI_TX_INSERT_OR_STRIP_SET(param, value) \ + WMI_SET_BITS(param, WMI_TX_INSERT_OR_STRIP_BIT_POS, 1, value) + +#define WMI_TX_INSERT_OR_STRIP_GET(param) \ + WMI_GET_BITS(param, WMI_TX_INSERT_OR_STRIP_BIT_POS, 1) + +#define WMI_TX_STRIP_INSERT_VLAN_INNER_SET(param, value) \ + WMI_SET_BITS(param, WMI_TX_STRIP_INSERT_VLAN_INNER_BIT_POS, 1, value) + +#define WMI_TX_STRIP_INSERT_VLAN_INNER_GET(param) \ + WMI_GET_BITS(param, WMI_TX_STRIP_INSERT_VLAN_INNER_BIT_POS, 1) + +#define WMI_TX_STRIP_INSERT_VLAN_OUTER_SET(param, value) \ + WMI_SET_BITS(param, WMI_TX_STRIP_INSERT_VLAN_OUTER_BIT_POS, 1, value) + +#define WMI_TX_STRIP_INSERT_VLAN_OUTER_GET(param) \ + WMI_GET_BITS(param, WMI_TX_STRIP_INSERT_VLAN_OUTER_BIT_POS, 1) + +#define WMI_RX_STRIP_VLAN_C_TAG_SET(param, value) \ + WMI_SET_BITS(param, WMI_RX_STRIP_VLAN_C_TAG_BIT_POS, 1, value) + +#define WMI_RX_STRIP_VLAN_C_TAG_GET(param) \ + WMI_GET_BITS(param, WMI_RX_STRIP_VLAN_C_TAG_BIT_POS, 1) + +#define WMI_RX_STRIP_VLAN_S_TAG_SET(param, value) \ + WMI_SET_BITS(param, WMI_RX_STRIP_VLAN_S_TAG_BIT_POS, 1, value) + +#define WMI_RX_STRIP_VLAN_S_TAG_GET(param) \ + WMI_GET_BITS(param, WMI_RX_STRIP_VLAN_S_TAG_BIT_POS, 1) + +#define WMI_RX_INSERT_VLAN_C_TAG_SET(param, value) \ + WMI_SET_BITS(param, WMI_RX_INSERT_VLAN_C_TAG_BIT_POS, 1, value) + +#define WMI_RX_INSERT_VLAN_C_TAG_GET(param) \ + WMI_GET_BITS(param, WMI_RX_INSERT_VLAN_C_TAG_BIT_POS, 1) + +#define WMI_RX_INSERT_VLAN_S_TAG_SET(param, value) \ + WMI_SET_BITS(param, WMI_RX_INSERT_VLAN_S_TAG_BIT_POS, 1, value) + +#define WMI_RX_INSERT_VLAN_S_TAG_GET(param) \ + WMI_GET_BITS(param, WMI_RX_INSERT_VLAN_S_TAG_BIT_POS, 1) + +#define WMI_TX_INSERT_VLAN_INNER_TCI_SET(param, value) \ + WMI_SET_BITS(param, WMI_TX_INSERT_VLAN_INNER_TCI_BIT_POS, WMI_TX_INSERT_VLAN_INNER_TCI_NUM_BITS, value) + +#define WMI_TX_INSERT_VLAN_INNER_TCI_GET(param) \ + WMI_GET_BITS(param, WMI_TX_INSERT_VLAN_INNER_TCI_BIT_POS, WMI_TX_INSERT_VLAN_INNER_TCI_NUM_BITS) + +#define WMI_TX_INSERT_VLAN_OUTER_TCI_SET(param, value) \ + WMI_SET_BITS(param, WMI_TX_INSERT_VLAN_OUTER_TCI_BIT_POS, WMI_TX_INSERT_VLAN_OUTER_TCI_NUM_BITS, value) + +#define WMI_TX_INSERT_VLAN_OUTER_TCI_GET(param) \ + WMI_GET_BITS(param, WMI_TX_INSERT_VLAN_OUTER_TCI_BIT_POS, WMI_TX_INSERT_VLAN_OUTER_TCI_NUM_BITS) + +typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_peer_config_vlan_cmd_fixed_param */ + A_UINT32 tlv_header; + /** peer MAC address */ + wmi_mac_addr peer_macaddr; + /* peer_vlan_config_mask: + * Field indicates VLAN settings that need to set in RX and TX peer + * Bit 0: Indicates if the settings are present for TX peer + * [1 - present for TX peer] + * Bit 1: Indicates if the settings are present for RX peer + * [1 - present for RX peer] + * Bit 2: Setting the insert_or_strip bit in TX peer + * [0 - Strip, 1 - Insert] + * Bit 3: Setting the strip_insert_vlan_inner bit in TX peer + * [0 - Strip, 1 - Insert] + * Bit 4: Setting the strip_insert_vlan_outer bit in TX peer + * [0 - Strip, 1 - Insert] + * Bit 5: Setting the strip_vlan_c_tag_decap bit in RX peer [1 - Strip] + * Bit 6: Setting the strip_vlan_s_tag_decap bit in RX peer [1 - Strip] + * Bit 7: Setting the rx_insert_vlan_c_tag_padding bit in RX peer + * [1 - Insert] + * Bit 8: Setting the rx_insert_vlan_s_tag_padding bit in RX peer + * [1 - Insert] + */ + A_UINT32 peer_vlan_config_mask; + + /* insert_vlan_tci: + * Field indicates the word that needs to be inserted in the + * inner or outer tag, if insertion is enabled by the + * TX peer strip_insert_vlan_{inner,outer} fields along with + * insert_or_strip field + * Bits 0:15 insert_vlan_inner_tci + * Bits 16:31 insert_vlan_outer_tci + */ + A_UINT32 insert_vlan_tci; + /* VDEV identifier */ + A_UINT32 vdev_id; +} wmi_peer_config_vlan_cmd_fixed_param; + +typedef struct { + /** TLV tag and len; tag equals + * WMITLV_TAG_STRUC_wmi_pdev_multiple_vdev_restart_resp_event_fixed_param */ + A_UINT32 tlv_header; + A_UINT32 pdev_id; /* ID of the pdev this response belongs to */ + A_UINT32 requestor_id; + /** Return status. As per WMI_VDEV_START_RESPONSE_XXXXX */ + A_UINT32 status; + + /* The TLVs follows this structure: + * A_UINT32 vdev_ids_bitmap[]; <--- Array of VDEV id bitmap. + */ +} wmi_pdev_multiple_vdev_restart_resp_event_fixed_param; /* ADD NEW DEFS HERE */ diff --git a/drivers/staging/fw-api/fw/wmi_version.h b/drivers/staging/fw-api/fw/wmi_version.h index 7f450e8ae63f..91e462d6d8d3 100644 --- a/drivers/staging/fw-api/fw/wmi_version.h +++ b/drivers/staging/fw-api/fw/wmi_version.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. * * Previously licensed under the ISC license by Qualcomm Atheros, Inc. * @@ -36,7 +36,7 @@ #define __WMI_VER_MINOR_ 0 /** WMI revision number has to be incremented when there is a * change that may or may not break compatibility. */ -#define __WMI_REVISION_ 725 +#define __WMI_REVISION_ 780 /** The Version Namespace should not be normally changed. Only * host and firmware of the same WMI namespace will work diff --git a/drivers/staging/fw-api/hw/qca6490/v1/rx_flow_search_entry.h b/drivers/staging/fw-api/hw/qca6490/v1/rx_flow_search_entry.h new file mode 100644 index 000000000000..e85786e9397f --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6490/v1/rx_flow_search_entry.h @@ -0,0 +1,789 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_FLOW_SEARCH_ENTRY_H_ +#define _RX_FLOW_SEARCH_ENTRY_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 src_ip_127_96[31:0] +// 1 src_ip_95_64[31:0] +// 2 src_ip_63_32[31:0] +// 3 src_ip_31_0[31:0] +// 4 dest_ip_127_96[31:0] +// 5 dest_ip_95_64[31:0] +// 6 dest_ip_63_32[31:0] +// 7 dest_ip_31_0[31:0] +// 8 src_port[15:0], dest_port[31:16] +// 9 l4_protocol[7:0], valid[8], reserved_9[23:9], reo_destination_indication[28:24], msdu_drop[29], reo_destination_handler[31:30] +// 10 metadata[31:0] +// 11 aggregation_count[6:0], lro_eligible[7], msdu_count[31:8] +// 12 msdu_byte_count[31:0] +// 13 timestamp[31:0] +// 14 cumulative_l4_checksum[15:0], cumulative_ip_length[31:16] +// 15 tcp_sequence_number[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_FLOW_SEARCH_ENTRY 16 + +struct rx_flow_search_entry { + uint32_t src_ip_127_96 : 32; //[31:0] + uint32_t src_ip_95_64 : 32; //[31:0] + uint32_t src_ip_63_32 : 32; //[31:0] + uint32_t src_ip_31_0 : 32; //[31:0] + uint32_t dest_ip_127_96 : 32; //[31:0] + uint32_t dest_ip_95_64 : 32; //[31:0] + uint32_t dest_ip_63_32 : 32; //[31:0] + uint32_t dest_ip_31_0 : 32; //[31:0] + uint32_t src_port : 16, //[15:0] + dest_port : 16; //[31:16] + uint32_t l4_protocol : 8, //[7:0] + valid : 1, //[8] + reserved_9 : 15, //[23:9] + reo_destination_indication : 5, //[28:24] + msdu_drop : 1, //[29] + reo_destination_handler : 2; //[31:30] + uint32_t metadata : 32; //[31:0] + uint32_t aggregation_count : 7, //[6:0] + lro_eligible : 1, //[7] + msdu_count : 24; //[31:8] + uint32_t msdu_byte_count : 32; //[31:0] + uint32_t timestamp : 32; //[31:0] + uint32_t cumulative_l4_checksum : 16, //[15:0] + cumulative_ip_length : 16; //[31:16] + uint32_t tcp_sequence_number : 32; //[31:0] +}; + +/* + +src_ip_127_96 + + Uppermost 32 bits of source IPv6 address or prefix as + per Common Parser register field IP_DA_SA_PREFIX (with the + first byte in the MSB and the last byte in the LSB, i.e. + requiring a byte-swap for little-endian SW w.r.t. the byte + order in an IPv6 packet) + + + +src_ip_95_64 + + Next 32 bits of source IPv6 address or prefix (requiring + a byte-swap for little-endian SW) + +src_ip_63_32 + + Next 32 bits of source IPv6 address or lowest 32 bits of + prefix (requiring a byte-swap for little-endian SW) + + + +src_ip_31_0 + + Lowest 32 bits of source IPv6 address, or source IPv4 + address (requiring a byte-swap for little-endian SW w.r.t. + the byte order in an Ipv6 or IPv4 packet) + + + +dest_ip_127_96 + + Uppermost 32 bits of destination IPv6 address or prefix + as per Common Parser register field IP_DA_SA_PREFIX (with + the first byte in the MSB and the last byte in the LSB, i.e. + requiring a byte-swap for little-endian SW w.r.t. the byte + order as in an IPv6 packet) + + + +dest_ip_95_64 + + Next 32 bits of destination IPv6 address or prefix + (requiring a byte-swap for little-endian SW) + + + +dest_ip_63_32 + + Next 32 bits of destination IPv6 address or lowest 32 + bits of prefix (requiring a byte-swap for little-endian SW) + + + +dest_ip_31_0 + + Lowest 32 bits of destination IPv6 address, or + destination IPv4 address (requiring a byte-swap for + little-endian SW w.r.t. the byte order in an Ipv6 or IPv4 + packet) + + + +src_port + + LSB of SPI in case of ESP/AH + + else source port in case of TCP/UDP without IPsec, + + else zeros in case of ICMP (with the first/third byte in + the MSB and the second/fourth byte in the LSB, i.e. + requiring a byte-swap for little-endian SW w.r.t. the byte + order as in an Ipv6 or IPv4 packet) + +dest_port + + MSB of SPI in case of ESP/AH + + else destination port in case of TCP/UDP without IPsec, + + else zeros in case of ICMP (with the first byte in the + MSB and the second byte in the LSB, i.e. requiring a + byte-swap for little-endian SW w.r.t. the byte order as in + an Ipv6 or IPv4 packet) + + + +l4_protocol + + IPsec or L4 protocol + + + + + + + + + + + + + + + + + +valid + + Indicates validity of entry + + + +reserved_9 + + + +reo_destination_indication + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW2 ring + + Reo will push the frame + into the REO2SW3 ring + + Reo will push the frame + into the REO2SW4 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + Reo will push the frame + into the REO2SW5 ring + + Reo will push the frame + into the REO2SW6 ring + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + + +msdu_drop + + Overriding indication to REO to forward to REO release + ring + + + +reo_destination_handler + + Indicates how to decide the REO destination indication + + Follow this entry + + Use address search+peer table + entry + + Follow this entry + + Use CCE super-rule + + + +metadata + + Value to be passed to SW if this flow search entry + matches + + + +aggregation_count + + FISA: Number'of MSDU's aggregated so far + + + + Set to zero in chips not supporting FISA, e.g. Pine + + + +lro_eligible + + FISA: To indicate whether the previous MSDU for this + flow is eligible for LRO/FISA + + + + Set to zero in chips not supporting FISA, e.g. Pine + + + +msdu_count + + Number of Rx MSDUs matching this flow + + + +msdu_byte_count + + Number of bytes in Rx MSDUs matching this flow + + + +timestamp + + Time of last reception (as measured at Rx OLE) matching + this flow + + + +cumulative_l4_checksum + + FISA: checksum 'or MSDU's that is part of this flow + aggregated so far + + + + Set to zero in chips not supporting FISA, e.g. Pine + + + +cumulative_ip_length + + FISA: Total MSDU length that is part of this flow + aggregated so far + + + + Set to zero in chips not supporting FISA, e.g. Pine + + + +tcp_sequence_number + + FISA: TCP Sequence number of the last packet in this + flow to detect sequence number jump + + + + Set to zero in chips not supporting FISA, e.g. Pine + + +*/ + + +/* Description RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96 + + Uppermost 32 bits of source IPv6 address or prefix as + per Common Parser register field IP_DA_SA_PREFIX (with the + first byte in the MSB and the last byte in the LSB, i.e. + requiring a byte-swap for little-endian SW w.r.t. the byte + order in an IPv6 packet) + + +*/ +#define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_OFFSET 0x00000000 +#define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_0_SRC_IP_127_96_MASK 0xffffffff + +/* Description RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64 + + Next 32 bits of source IPv6 address or prefix (requiring + a byte-swap for little-endian SW) +*/ +#define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_OFFSET 0x00000004 +#define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_1_SRC_IP_95_64_MASK 0xffffffff + +/* Description RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32 + + Next 32 bits of source IPv6 address or lowest 32 bits of + prefix (requiring a byte-swap for little-endian SW) + + +*/ +#define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_OFFSET 0x00000008 +#define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_2_SRC_IP_63_32_MASK 0xffffffff + +/* Description RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0 + + Lowest 32 bits of source IPv6 address, or source IPv4 + address (requiring a byte-swap for little-endian SW w.r.t. + the byte order in an Ipv6 or IPv4 packet) + + +*/ +#define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_OFFSET 0x0000000c +#define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_3_SRC_IP_31_0_MASK 0xffffffff + +/* Description RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96 + + Uppermost 32 bits of destination IPv6 address or prefix + as per Common Parser register field IP_DA_SA_PREFIX (with + the first byte in the MSB and the last byte in the LSB, i.e. + requiring a byte-swap for little-endian SW w.r.t. the byte + order as in an IPv6 packet) + + +*/ +#define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_OFFSET 0x00000010 +#define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_4_DEST_IP_127_96_MASK 0xffffffff + +/* Description RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64 + + Next 32 bits of destination IPv6 address or prefix + (requiring a byte-swap for little-endian SW) + + +*/ +#define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_OFFSET 0x00000014 +#define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_5_DEST_IP_95_64_MASK 0xffffffff + +/* Description RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32 + + Next 32 bits of destination IPv6 address or lowest 32 + bits of prefix (requiring a byte-swap for little-endian SW) + + +*/ +#define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_OFFSET 0x00000018 +#define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_6_DEST_IP_63_32_MASK 0xffffffff + +/* Description RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0 + + Lowest 32 bits of destination IPv6 address, or + destination IPv4 address (requiring a byte-swap for + little-endian SW w.r.t. the byte order in an Ipv6 or IPv4 + packet) + + +*/ +#define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_OFFSET 0x0000001c +#define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_7_DEST_IP_31_0_MASK 0xffffffff + +/* Description RX_FLOW_SEARCH_ENTRY_8_SRC_PORT + + LSB of SPI in case of ESP/AH + + else source port in case of TCP/UDP without IPsec, + + else zeros in case of ICMP (with the first/third byte in + the MSB and the second/fourth byte in the LSB, i.e. + requiring a byte-swap for little-endian SW w.r.t. the byte + order as in an Ipv6 or IPv4 packet) +*/ +#define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_OFFSET 0x00000020 +#define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_8_SRC_PORT_MASK 0x0000ffff + +/* Description RX_FLOW_SEARCH_ENTRY_8_DEST_PORT + + MSB of SPI in case of ESP/AH + + else destination port in case of TCP/UDP without IPsec, + + else zeros in case of ICMP (with the first byte in the + MSB and the second byte in the LSB, i.e. requiring a + byte-swap for little-endian SW w.r.t. the byte order as in + an Ipv6 or IPv4 packet) + + +*/ +#define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_OFFSET 0x00000020 +#define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_LSB 16 +#define RX_FLOW_SEARCH_ENTRY_8_DEST_PORT_MASK 0xffff0000 + +/* Description RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL + + IPsec or L4 protocol + + + + + + + + + + + + + + + + +*/ +#define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_9_L4_PROTOCOL_MASK 0x000000ff + +/* Description RX_FLOW_SEARCH_ENTRY_9_VALID + + Indicates validity of entry + + +*/ +#define RX_FLOW_SEARCH_ENTRY_9_VALID_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_9_VALID_LSB 8 +#define RX_FLOW_SEARCH_ENTRY_9_VALID_MASK 0x00000100 + +/* Description RX_FLOW_SEARCH_ENTRY_9_RESERVED_9 + + +*/ +#define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_LSB 9 +#define RX_FLOW_SEARCH_ENTRY_9_RESERVED_9_MASK 0x00fffe00 + +/* Description RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW2 ring + + Reo will push the frame + into the REO2SW3 ring + + Reo will push the frame + into the REO2SW4 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + Reo will push the frame + into the REO2SW5 ring + + Reo will push the frame + into the REO2SW6 ring + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + +*/ +#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_LSB 24 +#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_INDICATION_MASK 0x1f000000 + +/* Description RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP + + Overriding indication to REO to forward to REO release + ring + + +*/ +#define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_LSB 29 +#define RX_FLOW_SEARCH_ENTRY_9_MSDU_DROP_MASK 0x20000000 + +/* Description RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER + + Indicates how to decide the REO destination indication + + Follow this entry + + Use address search+peer table + entry + + Follow this entry + + Use CCE super-rule + + +*/ +#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_OFFSET 0x00000024 +#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_LSB 30 +#define RX_FLOW_SEARCH_ENTRY_9_REO_DESTINATION_HANDLER_MASK 0xc0000000 + +/* Description RX_FLOW_SEARCH_ENTRY_10_METADATA + + Value to be passed to SW if this flow search entry + matches + + +*/ +#define RX_FLOW_SEARCH_ENTRY_10_METADATA_OFFSET 0x00000028 +#define RX_FLOW_SEARCH_ENTRY_10_METADATA_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_10_METADATA_MASK 0xffffffff + +/* Description RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT + + FISA: Number'of MSDU's aggregated so far + + + + Set to zero in chips not supporting FISA, e.g. Pine + + +*/ +#define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_OFFSET 0x0000002c +#define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_11_AGGREGATION_COUNT_MASK 0x0000007f + +/* Description RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE + + FISA: To indicate whether the previous MSDU for this + flow is eligible for LRO/FISA + + + + Set to zero in chips not supporting FISA, e.g. Pine + + +*/ +#define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_OFFSET 0x0000002c +#define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_LSB 7 +#define RX_FLOW_SEARCH_ENTRY_11_LRO_ELIGIBLE_MASK 0x00000080 + +/* Description RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT + + Number of Rx MSDUs matching this flow + + +*/ +#define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_OFFSET 0x0000002c +#define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_LSB 8 +#define RX_FLOW_SEARCH_ENTRY_11_MSDU_COUNT_MASK 0xffffff00 + +/* Description RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT + + Number of bytes in Rx MSDUs matching this flow + + +*/ +#define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_OFFSET 0x00000030 +#define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_12_MSDU_BYTE_COUNT_MASK 0xffffffff + +/* Description RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP + + Time of last reception (as measured at Rx OLE) matching + this flow + + +*/ +#define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_OFFSET 0x00000034 +#define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_13_TIMESTAMP_MASK 0xffffffff + +/* Description RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM + + FISA: checksum 'or MSDU's that is part of this flow + aggregated so far + + + + Set to zero in chips not supporting FISA, e.g. Pine + + +*/ +#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_OFFSET 0x00000038 +#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_L4_CHECKSUM_MASK 0x0000ffff + +/* Description RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH + + FISA: Total MSDU length that is part of this flow + aggregated so far + + + + Set to zero in chips not supporting FISA, e.g. Pine + + +*/ +#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_OFFSET 0x00000038 +#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_LSB 16 +#define RX_FLOW_SEARCH_ENTRY_14_CUMULATIVE_IP_LENGTH_MASK 0xffff0000 + +/* Description RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER + + FISA: TCP Sequence number of the last packet in this + flow to detect sequence number jump + + + + Set to zero in chips not supporting FISA, e.g. Pine + + +*/ +#define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_OFFSET 0x0000003c +#define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_LSB 0 +#define RX_FLOW_SEARCH_ENTRY_15_TCP_SEQUENCE_NUMBER_MASK 0xffffffff + + +#endif // _RX_FLOW_SEARCH_ENTRY_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/HALcomdef.h b/drivers/staging/fw-api/hw/qca6750/v1/HALcomdef.h new file mode 100644 index 000000000000..305080d3f1b8 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/HALcomdef.h @@ -0,0 +1,131 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef HAL_COMDEF_H +#define HAL_COMDEF_H +/* +============================================================================== + +FILE: HALcomdef.h + +DESCRIPTION: + +============================================================================== + + Edit History + +$Header: //depot/prj/qca/lithium/HWS/Q5_2p1/include/hwio/qca649x/E3R52/include/HALcomdef.h#1 $ + +when who what, where, why +-------- --- ----------------------------------------------------------- +06/17/10 sc Included com_dtypes.h and cleaned up typedefs +05/15/08 gfr Added HAL_ENUM_32BITS macro. +02/14/08 gfr Added bool32 type. +11/13/07 gfr Removed dependency on comdef.h +01/08/07 hxw Created + +*/ + + +/* + * Assembly wrapper + */ +#ifndef _ARM_ASM_ + +/* + * C++ wrapper + */ +#ifdef __cplusplus +extern "C" { +#endif + +#include "com_dtypes.h" + +/* ----------------------------------------------------------------------- +** Types +** ----------------------------------------------------------------------- */ + +/* + * Standard integer types. + * + * bool32 - boolean, 32 bit (TRUE or FALSE) + */ +#ifndef _BOOL32_DEFINED +typedef unsigned long int bool32; +#define _BOOL32_DEFINED +#endif + +/* + * Macro to allow forcing an enum to 32 bits. The argument should be + * an identifier in the namespace of the enumeration in question, i.e. + * for the clk HAL we might use HAL_ENUM_32BITS(CLK_xxx). + */ +#define HAL_ENUM_32BITS(x) HAL_##x##_FORCE32BITS = 0x7FFFFFFF + +/*=========================================================================== + +FUNCTION inp, outp, inpw, outpw, inpdw, outpdw + +DESCRIPTION + IN/OUT port macros for byte and word ports, typically inlined by compilers + which support these routines + +PARAMETERS + inp( xx_addr ) + inpw( xx_addr ) + inpdw( xx_addr ) + outp( xx_addr, xx_byte_val ) + outpw( xx_addr, xx_word_val ) + outpdw( xx_addr, xx_dword_val ) + xx_addr - Address of port to read or write (may be memory mapped) + xx_byte_val - 8 bit value to write + xx_word_val - 16 bit value to write + xx_dword_val - 32 bit value to write + +DEPENDENCIES + None + +RETURN VALUE + inp/inpw/inpdw: the byte, word or dword read from the given address + outp/outpw/outpdw: the byte, word or dword written to the given address + +SIDE EFFECTS + None. + +===========================================================================*/ + + /* ARM based targets use memory mapped i/o, so the inp/outp calls are + ** macroized to access memory directly + */ + + #define inp(port) (*((volatile byte *) (port))) + #define inpw(port) (*((volatile word *) (port))) + #define inpdw(port) (*((volatile dword *)(port))) + + #define outp(port, val) (*((volatile byte *) (port)) = ((byte) (val))) + #define outpw(port, val) (*((volatile word *) (port)) = ((word) (val))) + #define outpdw(port, val) (*((volatile dword *) (port)) = ((dword) (val))) + +#ifdef __cplusplus +} +#endif + +#endif /* !_ARM_ASM_ */ + +#endif /* HAL_COMDEF_H */ + diff --git a/drivers/staging/fw-api/hw/qca6750/v1/HALhwio.h b/drivers/staging/fw-api/hw/qca6750/v1/HALhwio.h new file mode 100644 index 000000000000..1c57ef434efe --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/HALhwio.h @@ -0,0 +1,491 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef HAL_HWIO_H +#define HAL_HWIO_H +/* +=========================================================================== +*/ +/** + @file HALhwio.h + + Public interface include file for accessing the HWIO HAL definitions. + + The HALhwio.h file is the public API interface to the HW I/O (HWIO) + register access definitions. +*/ + +/*========================================================================= + Include Files +==========================================================================*/ + + +/* + * Common types. + */ +#include "HALcomdef.h" + +#define SEQ_WCSS_WCMN_OFFSET SEQ_WCSS_TOP_CMN_OFFSET +#define SEQ_WCSS_PMM_OFFSET SEQ_WCSS_PMM_TOP_OFFSET + +/* ----------------------------------------------------------------------- +** Macros +** ----------------------------------------------------------------------- */ + +/** + @addtogroup macros + @{ +*/ + +/** + * Map a base name to the pointer to access the base. + * + * This macro maps a base name to the pointer to access the base. + * This is generally just used internally. + * + */ +#define HWIO_BASE_PTR(base) base##_BASE_PTR + + +/** + * Declare a HWIO base pointer. + * + * This macro will declare a HWIO base pointer data structure. The pointer + * will always be declared as a weak symbol so multiple declarations will + * resolve correctly to the same data at link-time. + */ +#ifdef __ARMCC_VERSION + #define DECLARE_HWIO_BASE_PTR(base) __weak uint8 *HWIO_BASE_PTR(base) +#else + #define DECLARE_HWIO_BASE_PTR(base) uint8 *HWIO_BASE_PTR(base) +#endif + +/** + @} +*/ + + +/** + @addtogroup hwio_macros + @{ +*/ + +/** + * @name Address Macros + * + * Macros for getting register addresses. + * These macros are used for retrieving the address of a register. + * HWIO_ADDR* will return the directly accessible address (virtual or physical based + * on environment), HWIO_PHYS* will always return the physical address. + * The offset from the base region can be retrieved using HWIO_OFFS*. + * The "X" extension is used for explicit addressing where the base address of + * the module in question is provided as an argument to the macro. + * + * @{ + */ +#define HWIO_ADDR(hwiosym) __msmhwio_addr(hwiosym) +#define HWIO_ADDRI(hwiosym, index) __msmhwio_addri(hwiosym, index) +#define HWIO_ADDRI2(hwiosym, index1, index2) __msmhwio_addri2(hwiosym, index1, index2) +#define HWIO_ADDRI3(hwiosym, index1, index2, index3) __msmhwio_addri3(hwiosym, index1, index2, index3) + +#define HWIO_ADDRX(base, hwiosym) __msmhwio_addrx(base, hwiosym) +#define HWIO_ADDRXI(base, hwiosym, index) __msmhwio_addrxi(base, hwiosym, index) +#define HWIO_ADDRXI2(base, hwiosym, index1, index2) __msmhwio_addrxi2(base, hwiosym, index1, index2) +#define HWIO_ADDRXI3(base, hwiosym, index1, index2, index3) __msmhwio_addrxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_PHYS(hwiosym) __msmhwio_phys(hwiosym) +#define HWIO_PHYSI(hwiosym, index) __msmhwio_physi(hwiosym, index) +#define HWIO_PHYSI2(hwiosym, index1, index2) __msmhwio_physi2(hwiosym, index1, index2) +#define HWIO_PHYSI3(hwiosym, index1, index2, index3) __msmhwio_physi3(hwiosym, index1, index2, index3) + +#define HWIO_PHYSX(base, hwiosym) __msmhwio_physx(base, hwiosym) +#define HWIO_PHYSXI(base, hwiosym, index) __msmhwio_physxi(base, hwiosym, index) +#define HWIO_PHYSXI2(base, hwiosym, index1, index2) __msmhwio_physxi2(base, hwiosym, index1, index2) +#define HWIO_PHYSXI3(base, hwiosym, index1, index2, index3) __msmhwio_physxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_OFFS(hwiosym) __msmhwio_offs(hwiosym) +#define HWIO_OFFSI(hwiosym, index) __msmhwio_offsi(hwiosym, index) +#define HWIO_OFFSI2(hwiosym, index1, index2) __msmhwio_offsi2(hwiosym, index1, index2) +#define HWIO_OFFSI3(hwiosym, index1, index2, index3) __msmhwio_offsi3(hwiosym, index1, index2, index3) +/** @} */ + +/** + * @name Input Macros + * + * These macros are used for reading from a named hardware register. Register + * arrays ("indexed") use the macros with the "I" suffix. The "M" suffix + * indicates that the input will be masked with the supplied mask. The HWIO_INF* + * macros take a field name and will do the appropriate masking and shifting + * to return just the value of that field. + * The "X" extension is used for explicit addressing where the base address of + * the module in question is provided as an argument to the macro. + * + * Generally you want to use either HWIO_IN or HWIO_INF (with required indexing). + * + * @{ + */ +#define HWIO_IN(hwiosym) __msmhwio_in(hwiosym) +#define HWIO_INI(hwiosym, index) __msmhwio_ini(hwiosym, index) +#define HWIO_INI2(hwiosym, index1, index2) __msmhwio_ini2(hwiosym, index1, index2) +#define HWIO_INI3(hwiosym, index1, index2, index3) __msmhwio_ini3(hwiosym, index1, index2, index3) + +#define HWIO_INM(hwiosym, mask) __msmhwio_inm(hwiosym, mask) +#define HWIO_INMI(hwiosym, index, mask) __msmhwio_inmi(hwiosym, index, mask) +#define HWIO_INMI2(hwiosym, index1, index2, mask) __msmhwio_inmi2(hwiosym, index1, index2, mask) +#define HWIO_INMI3(hwiosym, index1, index2, index3, mask) __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) + +#define HWIO_INF(io, field) (HWIO_INM(io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI(io, index, field) (HWIO_INMI(io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI2(io, index1, index2, field) (HWIO_INMI2(io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INFI3(io, index1, index2, index3, field) (HWIO_INMI3(io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) + +#define HWIO_INX(base, hwiosym) __msmhwio_inx(base, hwiosym) +#define HWIO_INXI(base, hwiosym, index) __msmhwio_inxi(base, hwiosym, index) +#define HWIO_INXI2(base, hwiosym, index1, index2) __msmhwio_inxi2(base, hwiosym, index1, index2) +#define HWIO_INXI3(base, hwiosym, index1, index2, index3) __msmhwio_inxi3(base, hwiosym, index1, index2, index3) + +#define HWIO_INXM(base, hwiosym, mask) __msmhwio_inxm(base, hwiosym, mask) +#define HWIO_INXMI(base, hwiosym, index, mask) __msmhwio_inxmi(base, hwiosym, index, mask) +#define HWIO_INXMI2(base, hwiosym, index1, index2, mask) __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) +#define HWIO_INXMI3(base, hwiosym, index1, index2, index3, mask) __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) + +#define HWIO_INXF(base, io, field) (HWIO_INXM(base, io, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI(base, io, index, field) (HWIO_INXMI(base, io, index, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI2(base, io, index1, index2, field) (HWIO_INXMI2(base, io, index1, index2, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +#define HWIO_INXFI3(base, io, index1, index2, index3, field) (HWIO_INXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field)) >> HWIO_SHFT(io, field)) +/** @} */ + +/** + * @name Output Macros + * + * These macros are used for writing to a named hardware register. Register + * arrays ("indexed") use the macros with the "I" suffix. The "M" suffix + * indicates that the output will be masked with the supplied mask (meaning these + * macros do a read first, mask in the supplied data, then write it back). + * The "X" extension is used for explicit addressing where the base address of + * the module in question is provided as an argument to the macro. + * The HWIO_OUTF* macros take a field name and will do the appropriate masking + * and shifting to output just the value of that field. + * HWIO_OUTV* registers take a named value instead of a numeric value and + * do the same masking/shifting as HWIO_OUTF. + * + * Generally you want to use either HWIO_OUT or HWIO_OUTF (with required indexing). + * + * @{ + */ +#define HWIO_OUT(hwiosym, val) __msmhwio_out(hwiosym, val) +#define HWIO_OUTI(hwiosym, index, val) __msmhwio_outi(hwiosym, index, val) +#define HWIO_OUTI2(hwiosym, index1, index2, val) __msmhwio_outi2(hwiosym, index1, index2, val) +#define HWIO_OUTI3(hwiosym, index1, index2, index3, val) __msmhwio_outi3(hwiosym, index1, index2, index3, val) + +#define HWIO_OUTM(hwiosym, mask, val) __msmhwio_outm(hwiosym, mask, val) +#define HWIO_OUTMI(hwiosym, index, mask, val) __msmhwio_outmi(hwiosym, index, mask, val) +#define HWIO_OUTMI2(hwiosym, index1, index2, mask, val) __msmhwio_outmi2(hwiosym, index1, index2, mask, val) +#define HWIO_OUTMI3(hwiosym, index1, index2, index3, mask, val) __msmhwio_outmi3(hwiosym, index1, index2, index3, mask, val) + +#define HWIO_OUTF(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTFI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) + +#define HWIO_OUTV(io, field, val) HWIO_OUTM(io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI(io, index, field, val) HWIO_OUTMI(io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI2(io, index1, index2, field, val) HWIO_OUTMI2(io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTVI3(io, index1, index2, index3, field, val) HWIO_OUTMI3(io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) + +#define HWIO_OUTX(base, hwiosym, val) __msmhwio_outx(base, hwiosym, val) +#define HWIO_OUTXI(base, hwiosym, index, val) __msmhwio_outxi(base, hwiosym, index, val) +#define HWIO_OUTXI2(base, hwiosym, index1, index2, val) __msmhwio_outxi2(base, hwiosym, index1, index2, val) +#define HWIO_OUTXI3(base, hwiosym, index1, index2, index3, val) __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) + +#define HWIO_OUTXM(base, hwiosym, mask, val) __msmhwio_outxm(base, hwiosym, mask, val) +#define HWIO_OUTXM2(base, hwiosym, mask1, mask2, val1, val2) __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) +#define HWIO_OUTXM3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) +#define HWIO_OUTXM4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) +#define HWIO_OUTXMI(base, hwiosym, index, mask, val) __msmhwio_outxmi(base, hwiosym, index, mask, val) +#define HWIO_OUTXMI2(base, hwiosym, index1, index2, mask, val) __msmhwio_outxmi2(base, hwiosym, index1, index2, mask, val) +#define HWIO_OUTXMI3(base, hwiosym, index1, index2, index3, mask, val) __msmhwio_outxmi3(base, hwiosym, index1, index2, index3, mask, val) + +#define HWIO_OUTXF(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTX2F(base, io, field1, field2, val1, val2) HWIO_OUTXM2(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), (uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2)) +#define HWIO_OUTX3F(base, io, field1, field2, field3, val1, val2, val3) HWIO_OUTXM3(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3),(uint32)(val1) << HWIO_SHFT(io, field1), (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3) ) +#define HWIO_OUTX4F(base, io, field1, field2, field3, field4, val1, val2, val3, val4) HWIO_OUTXM4(base, io, HWIO_FMSK(io, field1), HWIO_FMSK(io, field2), HWIO_FMSK(io, field3), HWIO_FMSK(io, field4), (uint32)(val1) << HWIO_SHFT(io, field1) , (uint32)(val2) << HWIO_SHFT(io, field2), (uint32)(val3) << HWIO_SHFT(io, field3), (uint32)(val4) << HWIO_SHFT(io, field4) ) + +#define HWIO_OUTXFI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTXFI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) +#define HWIO_OUTXFI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(val) << HWIO_SHFT(io, field)) + +#define HWIO_OUTXV(base, io, field, val) HWIO_OUTXM(base, io, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI(base, io, index, field, val) HWIO_OUTXMI(base, io, index, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI2(base, io, index1, index2, field, val) HWIO_OUTXMI2(base, io, index1, index2, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +#define HWIO_OUTXVI3(base, io, index1, index2, index3, field, val) HWIO_OUTXMI3(base, io, index1, index2, index3, HWIO_FMSK(io, field), (uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) +/** @} */ + +/** + * @name Shift and Mask Macros + * + * Macros for getting shift and mask values for fields and registers. + * HWIO_RMSK: The mask value for accessing an entire register. For example: + * @code + * HWIO_RMSK(REG) -> 0xFFFFFFFF + * @endcode + * HWIO_RSHFT: The right-shift value for an entire register (rarely necessary).\n + * HWIO_SHFT: The right-shift value for accessing a field in a register. For example: + * @code + * HWIO_SHFT(REG, FLD) -> 8 + * @endcode + * HWIO_FMSK: The mask value for accessing a field in a register. For example: + * @code + * HWIO_FMSK(REG, FLD) -> 0xFF00 + * @endcode + * HWIO_VAL: The value for a field in a register. For example: + * @code + * HWIO_VAL(REG, FLD, ON) -> 0x1 + * @endcode + * HWIO_FVAL: This macro takes a numerical value and will shift and mask it into + * the given field position. For example: + * @code + * HWIO_FVAL(REG, FLD, 0x1) -> 0x100 + * @endcode + * HWIO_FVALV: This macro takes a logical (named) value and will shift and mask it + * into the given field position. For example: + * @code + * HWIO_FVALV(REG, FLD, ON) -> 0x100 + * @endcode + * + * @{ + */ +#define HWIO_RMSK(hwiosym) __msmhwio_rmsk(hwiosym) +#define HWIO_RMSKI(hwiosym, index) __msmhwio_rmski(hwiosym, index) +#define HWIO_RSHFT(hwiosym) __msmhwio_rshft(hwiosym) +#define HWIO_SHFT(hwio_regsym, hwio_fldsym) __msmhwio_shft(hwio_regsym, hwio_fldsym) +#define HWIO_FMSK(hwio_regsym, hwio_fldsym) __msmhwio_fmsk(hwio_regsym, hwio_fldsym) +#define HWIO_VAL(io, field, val) __msmhwio_val(io, field, val) +#define HWIO_FVAL(io, field, val) (((uint32)(val) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) +#define HWIO_FVALV(io, field, val) (((uint32)(HWIO_VAL(io, field, val)) << HWIO_SHFT(io, field)) & HWIO_FMSK(io, field)) +/** @} */ + +/** + * @name Shadow Register Macros + * + * These macros are used for directly reading the value stored in a + * shadow register. + * Shadow registers are defined for write-only registers. Generally these + * macros should not be necessary as HWIO_OUTM* macros will automatically use + * the shadow values internally. + * + * @{ + */ +#define HWIO_SHDW(hwiosym) __msmhwio_shdw(hwiosym) +#define HWIO_SHDWI(hwiosym, index) __msmhwio_shdwi(hwiosym, index) +/** @} */ + +/** + @} +*/ /* end_group */ + + +/** @cond */ + +/* + * Map to final symbols. This remapping is done to allow register + * redefinitions. If we just define HWIO_IN(xreg) as HWIO_##xreg##_IN + * then remappings like "#define xreg xregnew" do not work as expected. + */ +#define __msmhwio_in(hwiosym) HWIO_##hwiosym##_IN +#define __msmhwio_ini(hwiosym, index) HWIO_##hwiosym##_INI(index) +#define __msmhwio_ini2(hwiosym, index1, index2) HWIO_##hwiosym##_INI2(index1, index2) +#define __msmhwio_ini3(hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(index1, index2, index3) +#define __msmhwio_inm(hwiosym, mask) HWIO_##hwiosym##_INM(mask) +#define __msmhwio_inmi(hwiosym, index, mask) HWIO_##hwiosym##_INMI(index, mask) +#define __msmhwio_inmi2(hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(index1, index2, mask) +#define __msmhwio_inmi3(hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(index1, index2, index3, mask) +#define __msmhwio_out(hwiosym, val) HWIO_##hwiosym##_OUT(val) +#define __msmhwio_outi(hwiosym, index, val) HWIO_##hwiosym##_OUTI(index,val) +#define __msmhwio_outi2(hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(index1, index2, val) +#define __msmhwio_outi3(hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(index1, index2, index3, val) +#define __msmhwio_outm(hwiosym, mask, val) HWIO_##hwiosym##_OUTM(mask, val) +#define __msmhwio_outmi(hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(index, mask, val) +#define __msmhwio_outmi2(hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(idx1, idx2, mask, val) +#define __msmhwio_outmi3(hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(idx1, idx2, idx3, mask, val) +#define __msmhwio_addr(hwiosym) HWIO_##hwiosym##_ADDR +#define __msmhwio_addri(hwiosym, index) HWIO_##hwiosym##_ADDR(index) +#define __msmhwio_addri2(hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(idx1, idx2) +#define __msmhwio_addri3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(idx1, idx2, idx3) +#define __msmhwio_phys(hwiosym) HWIO_##hwiosym##_PHYS +#define __msmhwio_physi(hwiosym, index) HWIO_##hwiosym##_PHYS(index) +#define __msmhwio_physi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(idx1, idx2) +#define __msmhwio_physi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(idx1, idx2, idx3) +#define __msmhwio_offs(hwiosym) HWIO_##hwiosym##_OFFS +#define __msmhwio_offsi(hwiosym, index) HWIO_##hwiosym##_OFFS(index) +#define __msmhwio_offsi2(hwiosym, idx1, idx2) HWIO_##hwiosym##_OFFS(idx1, idx2) +#define __msmhwio_offsi3(hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_OFFS(idx1, idx2, idx3) +#define __msmhwio_rmsk(hwiosym) HWIO_##hwiosym##_RMSK +#define __msmhwio_rmski(hwiosym, index) HWIO_##hwiosym##_RMSK(index) +#define __msmhwio_fmsk(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_BMSK +#define __msmhwio_rshft(hwiosym) HWIO_##hwiosym##_SHFT +#define __msmhwio_shft(hwiosym, hwiofldsym) HWIO_##hwiosym##_##hwiofldsym##_SHFT +#define __msmhwio_shdw(hwiosym) HWIO_##hwiosym##_shadow +#define __msmhwio_shdwi(hwiosym, index) HWIO_##hwiosym##_SHDW(index) +#define __msmhwio_val(hwiosym, hwiofld, hwioval) HWIO_##hwiosym##_##hwiofld##_##hwioval##_FVAL + +#define __msmhwio_inx(base, hwiosym) HWIO_##hwiosym##_IN(base) +#define __msmhwio_inxi(base, hwiosym, index) HWIO_##hwiosym##_INI(base, index) +#define __msmhwio_inxi2(base, hwiosym, index1, index2) HWIO_##hwiosym##_INI2(base, index1, index2) +#define __msmhwio_inxi3(base, hwiosym, index1, index2, index3) HWIO_##hwiosym##_INI3(base, index1, index2, index3) +#define __msmhwio_inxm(base, hwiosym, mask) HWIO_##hwiosym##_INM(base, mask) +#define __msmhwio_inxmi(base, hwiosym, index, mask) HWIO_##hwiosym##_INMI(base, index, mask) +#define __msmhwio_inxmi2(base, hwiosym, index1, index2, mask) HWIO_##hwiosym##_INMI2(base, index1, index2, mask) +#define __msmhwio_inxmi3(base, hwiosym, index1, index2, index3, mask) HWIO_##hwiosym##_INMI3(base, index1, index2, index3, mask) +#define __msmhwio_outx(base, hwiosym, val) HWIO_##hwiosym##_OUT(base, val) +#define __msmhwio_outxi(base, hwiosym, index, val) HWIO_##hwiosym##_OUTI(base, index,val) +#define __msmhwio_outxi2(base, hwiosym, index1, index2, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, val) +#define __msmhwio_outxi3(base, hwiosym, index1, index2, index3, val) HWIO_##hwiosym##_OUTI2(base, index1, index2, index3, val) +#define __msmhwio_outxm(base, hwiosym, mask, val) HWIO_##hwiosym##_OUTM(base, mask, val) +#define __msmhwio_outxm2(base, hwiosym, mask1, mask2, val1, val2) { \ + HWIO_##hwiosym##_OUTM(base, mask1, val1); \ + HWIO_##hwiosym##_OUTM(base, mask2, val2); \ + } +#define __msmhwio_outxm3(base, hwiosym, mask1, mask2, mask3, val1, val2, val3) { \ + HWIO_##hwiosym##_OUTM(base, mask1, val1); \ + HWIO_##hwiosym##_OUTM(base, mask2, val2); \ + HWIO_##hwiosym##_OUTM(base, mask3, val3); \ + } +#define __msmhwio_outxm4(base, hwiosym, mask1, mask2, mask3, mask4, val1, val2, val3, val4) { \ + HWIO_##hwiosym##_OUTM(base, mask1, val1); \ + HWIO_##hwiosym##_OUTM(base, mask2, val2); \ + HWIO_##hwiosym##_OUTM(base, mask3, val3); \ + HWIO_##hwiosym##_OUTM(base, mask4, val4); \ + } + + +#define __msmhwio_outxmi(base, hwiosym, index, mask, val) HWIO_##hwiosym##_OUTMI(base, index, mask, val) +#define __msmhwio_outxmi2(base, hwiosym, idx1, idx2, mask, val) HWIO_##hwiosym##_OUTMI2(base, idx1, idx2, mask, val) +#define __msmhwio_outxmi3(base, hwiosym, idx1, idx2, idx3, mask, val) HWIO_##hwiosym##_OUTMI3(base, idx1, idx2, idx3, mask, val) +#define __msmhwio_addrx(base, hwiosym) HWIO_##hwiosym##_ADDR(base) +#define __msmhwio_addrxi(base, hwiosym, index) HWIO_##hwiosym##_ADDR(base, index) +#define __msmhwio_addrxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_ADDR(base, idx1, idx2) +#define __msmhwio_addrxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_ADDR(base, idx1, idx2, idx3) +#define __msmhwio_physx(base, hwiosym) HWIO_##hwiosym##_PHYS(base) +#define __msmhwio_physxi(base, hwiosym, index) HWIO_##hwiosym##_PHYS(base, index) +#define __msmhwio_physxi2(base, hwiosym, idx1, idx2) HWIO_##hwiosym##_PHYS(base, idx1, idx2) +#define __msmhwio_physxi3(base, hwiosym, idx1, idx2, idx3) HWIO_##hwiosym##_PHYS(base, idx1, idx2, idx3) + + +/* + * HWIO_INTLOCK + * + * Macro used by autogenerated code for mutual exclusion around + * read-mask-write operations. This is not supported in HAL + * code but can be overridden by non-HAL code. + */ +#define HWIO_INTLOCK() +#define HWIO_INTFREE() + + +/* + * Input/output port macros for memory mapped IO. + */ +#define __inp(port) (*((volatile uint8 *) (port))) +#define __inpw(port) (*((volatile uint16 *) (port))) +#define __inpdw(port) (*((volatile uint32 *) (port))) +#define __outp(port, val) (*((volatile uint8 *) (port)) = ((uint8) (val))) +#define __outpw(port, val) (*((volatile uint16 *) (port)) = ((uint16) (val))) +#define __outpdw(port, val) (*((volatile uint32 *) (port)) = ((uint32) (val))) + + +#ifdef HAL_HWIO_EXTERNAL + +/* + * Replace macros with externally supplied functions. + */ +#undef __inp +#undef __inpw +#undef __inpdw +#undef __outp +#undef __outpw +#undef __outpdw + +#define __inp(port) __inp_extern(port) +#define __inpw(port) __inpw_extern(port) +#define __inpdw(port) __inpdw_extern(port) +#define __outp(port, val) __outp_extern(port, val) +#define __outpw(port, val) __outpw_extern(port, val) +#define __outpdw(port, val) __outpdw_extern(port, val) + +extern uint8 __inp_extern ( uint32 nAddr ); +extern uint16 __inpw_extern ( uint32 nAddr ); +extern uint32 __inpdw_extern ( uint32 nAddr ); +extern void __outp_extern ( uint32 nAddr, uint8 nData ); +extern void __outpw_extern ( uint32 nAddr, uint16 nData ); +extern void __outpdw_extern ( uint32 nAddr, uint32 nData ); + +#endif /* HAL_HWIO_EXTERNAL */ + + +/* + * Base 8-bit byte accessing macros. + */ +#define in_byte(addr) (__inp(addr)) +#define in_byte_masked(addr, mask) (__inp(addr & (mask)) +#define out_byte(addr, val) __outp(addr,val) +#define out_byte_masked(io, mask, val, shadow) \ + HWIO_INTLOCK(); \ + out_byte( io, shadow); \ + shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ + HWIO_INTFREE() +#define out_byte_masked_ns(io, mask, val, current_reg_content) \ + out_byte( io, ((current_reg_content & (uint16)(~(mask))) | \ + ((uint16)((val) & (mask)))) ) + + +/* + * Base 16-bit word accessing macros. + */ +#define in_word(addr) (__inpw(addr)) +#define in_word_masked(addr, mask) (__inpw(addr) & (mask)) +#define out_word(addr, val) __outpw(addr,val) +#define out_word_masked(io, mask, val, shadow) \ + HWIO_INTLOCK( ); \ + shadow = (shadow & (uint16)(~(mask))) | ((uint16)((val) & (mask))); \ + out_word( io, shadow); \ + HWIO_INTFREE( ) +#define out_word_masked_ns(io, mask, val, current_reg_content) \ + out_word( io, ((current_reg_content & (uint16)(~(mask))) | \ + ((uint16)((val) & (mask)))) ) + + +/* + * Base 32-bit double-word accessing macros. + */ +#define in_dword(addr) (__inpdw(addr)) +#define in_dword_masked(addr, mask) (__inpdw(addr) & (mask)) +#define out_dword(addr, val) __outpdw(addr,val) +#define out_dword_masked(io, mask, val, shadow) \ + HWIO_INTLOCK(); \ + shadow = (shadow & (uint32)(~(mask))) | ((uint32)((val) & (mask))); \ + out_dword( io, shadow); \ + HWIO_INTFREE() +#define out_dword_masked_ns(io, mask, val, current_reg_content) \ + out_dword( io, ((current_reg_content & (uint32)(~(mask))) | \ + ((uint32)((val) & (mask)))) ) + +/** @endcond */ + +#endif /* HAL_HWIO_H */ + diff --git a/drivers/staging/fw-api/hw/qca6750/v1/buffer_addr_info.h b/drivers/staging/fw-api/hw/qca6750/v1/buffer_addr_info.h new file mode 100644 index 000000000000..76d86b9ad0e3 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/buffer_addr_info.h @@ -0,0 +1,348 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _BUFFER_ADDR_INFO_H_ +#define _BUFFER_ADDR_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 buffer_addr_31_0[31:0] +// 1 buffer_addr_39_32[7:0], return_buffer_manager[10:8], sw_buffer_cookie[31:11] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_BUFFER_ADDR_INFO 2 + +struct buffer_addr_info { + uint32_t buffer_addr_31_0 : 32; //[31:0] + uint32_t buffer_addr_39_32 : 8, //[7:0] + return_buffer_manager : 3, //[10:8] + sw_buffer_cookie : 21; //[31:11] +}; + +/* + +buffer_addr_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + + +buffer_addr_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + + +return_buffer_manager + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + + +sw_buffer_cookie + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ + + +/* Description BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 0 +#define BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 0 +#define BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + +*/ +#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 8 +#define BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ +#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 11 +#define BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 0xfffff800 + + +#endif // _BUFFER_ADDR_INFO_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/ce_src_desc.h b/drivers/staging/fw-api/hw/qca6750/v1/ce_src_desc.h new file mode 100644 index 000000000000..35a6e44f2b43 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/ce_src_desc.h @@ -0,0 +1,359 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _CE_SRC_DESC_H_ +#define _CE_SRC_DESC_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 src_buffer_low[31:0] +// 1 src_buffer_high[7:0], toeplitz_en[8], src_swap[9], dest_swap[10], gather[11], ce_res_0[15:12], length[31:16] +// 2 fw_metadata[15:0], ce_res_1[31:16] +// 3 ce_res_2[19:0], ring_id[27:20], looping_count[31:28] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_CE_SRC_DESC 4 + +struct ce_src_desc { + uint32_t src_buffer_low : 32; //[31:0] + uint32_t src_buffer_high : 8, //[7:0] + toeplitz_en : 1, //[8] + src_swap : 1, //[9] + dest_swap : 1, //[10] + gather : 1, //[11] + ce_res_0 : 4, //[15:12] + length : 16; //[31:16] + uint32_t fw_metadata : 16, //[15:0] + ce_res_1 : 16; //[31:16] + uint32_t ce_res_2 : 20, //[19:0] + ring_id : 8, //[27:20] + looping_count : 4; //[31:28] +}; + +/* + +src_buffer_low + + LSB 32 bits of the 40 Bit Pointer to the source buffer + + + +src_buffer_high + + MSB 8 bits of the 40 Bit Pointer to the source buffer + + + +toeplitz_en + + Enable generation of 32-bit Toeplitz-LFSR hash for the + data transfer + + In case of gather field in first source ring entry of + the gather copy cycle in taken into account. + + + +src_swap + + Treats source memory organization as big-endian. For + each dword read (4 bytes), the byte 0 is swapped with byte 3 + and byte 1 is swapped with byte 2. + + In case of gather field in first source ring entry of + the gather copy cycle in taken into account. + + + +dest_swap + + Treats destination memory organization as big-endian. + For each dword write (4 bytes), the byte 0 is swapped with + byte 3 and byte 1 is swapped with byte 2. + + In case of gather field in first source ring entry of + the gather copy cycle in taken into account. + + + +gather + + Enables gather of multiple copy engine source + descriptors to one destination. + + + +ce_res_0 + + Reserved + + + +length + + Length of the buffer in units of octets of the current + descriptor + + + +fw_metadata + + Meta data used by FW + + In case of gather field in first source ring entry of + the gather copy cycle in taken into account. + + + +ce_res_1 + + Reserved + + + +ce_res_2 + + Reserved + + + +ring_id + + The buffer pointer ring ID. + + 0 refers to the IDLE ring + + 1 - N refers to other rings + + + + Helps with debugging when dumping ring contents. + + + +looping_count + + A count value that indicates the number of times the + producer of entries into the Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ + + +/* Description CE_SRC_DESC_0_SRC_BUFFER_LOW + + LSB 32 bits of the 40 Bit Pointer to the source buffer + + +*/ +#define CE_SRC_DESC_0_SRC_BUFFER_LOW_OFFSET 0x00000000 +#define CE_SRC_DESC_0_SRC_BUFFER_LOW_LSB 0 +#define CE_SRC_DESC_0_SRC_BUFFER_LOW_MASK 0xffffffff + +/* Description CE_SRC_DESC_1_SRC_BUFFER_HIGH + + MSB 8 bits of the 40 Bit Pointer to the source buffer + + +*/ +#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_OFFSET 0x00000004 +#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_LSB 0 +#define CE_SRC_DESC_1_SRC_BUFFER_HIGH_MASK 0x000000ff + +/* Description CE_SRC_DESC_1_TOEPLITZ_EN + + Enable generation of 32-bit Toeplitz-LFSR hash for the + data transfer + + In case of gather field in first source ring entry of + the gather copy cycle in taken into account. + + +*/ +#define CE_SRC_DESC_1_TOEPLITZ_EN_OFFSET 0x00000004 +#define CE_SRC_DESC_1_TOEPLITZ_EN_LSB 8 +#define CE_SRC_DESC_1_TOEPLITZ_EN_MASK 0x00000100 + +/* Description CE_SRC_DESC_1_SRC_SWAP + + Treats source memory organization as big-endian. For + each dword read (4 bytes), the byte 0 is swapped with byte 3 + and byte 1 is swapped with byte 2. + + In case of gather field in first source ring entry of + the gather copy cycle in taken into account. + + +*/ +#define CE_SRC_DESC_1_SRC_SWAP_OFFSET 0x00000004 +#define CE_SRC_DESC_1_SRC_SWAP_LSB 9 +#define CE_SRC_DESC_1_SRC_SWAP_MASK 0x00000200 + +/* Description CE_SRC_DESC_1_DEST_SWAP + + Treats destination memory organization as big-endian. + For each dword write (4 bytes), the byte 0 is swapped with + byte 3 and byte 1 is swapped with byte 2. + + In case of gather field in first source ring entry of + the gather copy cycle in taken into account. + + +*/ +#define CE_SRC_DESC_1_DEST_SWAP_OFFSET 0x00000004 +#define CE_SRC_DESC_1_DEST_SWAP_LSB 10 +#define CE_SRC_DESC_1_DEST_SWAP_MASK 0x00000400 + +/* Description CE_SRC_DESC_1_GATHER + + Enables gather of multiple copy engine source + descriptors to one destination. + + +*/ +#define CE_SRC_DESC_1_GATHER_OFFSET 0x00000004 +#define CE_SRC_DESC_1_GATHER_LSB 11 +#define CE_SRC_DESC_1_GATHER_MASK 0x00000800 + +/* Description CE_SRC_DESC_1_CE_RES_0 + + Reserved + + +*/ +#define CE_SRC_DESC_1_CE_RES_0_OFFSET 0x00000004 +#define CE_SRC_DESC_1_CE_RES_0_LSB 12 +#define CE_SRC_DESC_1_CE_RES_0_MASK 0x0000f000 + +/* Description CE_SRC_DESC_1_LENGTH + + Length of the buffer in units of octets of the current + descriptor + + +*/ +#define CE_SRC_DESC_1_LENGTH_OFFSET 0x00000004 +#define CE_SRC_DESC_1_LENGTH_LSB 16 +#define CE_SRC_DESC_1_LENGTH_MASK 0xffff0000 + +/* Description CE_SRC_DESC_2_FW_METADATA + + Meta data used by FW + + In case of gather field in first source ring entry of + the gather copy cycle in taken into account. + + +*/ +#define CE_SRC_DESC_2_FW_METADATA_OFFSET 0x00000008 +#define CE_SRC_DESC_2_FW_METADATA_LSB 0 +#define CE_SRC_DESC_2_FW_METADATA_MASK 0x0000ffff + +/* Description CE_SRC_DESC_2_CE_RES_1 + + Reserved + + +*/ +#define CE_SRC_DESC_2_CE_RES_1_OFFSET 0x00000008 +#define CE_SRC_DESC_2_CE_RES_1_LSB 16 +#define CE_SRC_DESC_2_CE_RES_1_MASK 0xffff0000 + +/* Description CE_SRC_DESC_3_CE_RES_2 + + Reserved + + +*/ +#define CE_SRC_DESC_3_CE_RES_2_OFFSET 0x0000000c +#define CE_SRC_DESC_3_CE_RES_2_LSB 0 +#define CE_SRC_DESC_3_CE_RES_2_MASK 0x000fffff + +/* Description CE_SRC_DESC_3_RING_ID + + The buffer pointer ring ID. + + 0 refers to the IDLE ring + + 1 - N refers to other rings + + + + Helps with debugging when dumping ring contents. + + +*/ +#define CE_SRC_DESC_3_RING_ID_OFFSET 0x0000000c +#define CE_SRC_DESC_3_RING_ID_LSB 20 +#define CE_SRC_DESC_3_RING_ID_MASK 0x0ff00000 + +/* Description CE_SRC_DESC_3_LOOPING_COUNT + + A count value that indicates the number of times the + producer of entries into the Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ +#define CE_SRC_DESC_3_LOOPING_COUNT_OFFSET 0x0000000c +#define CE_SRC_DESC_3_LOOPING_COUNT_LSB 28 +#define CE_SRC_DESC_3_LOOPING_COUNT_MASK 0xf0000000 + + +#endif // _CE_SRC_DESC_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/ce_stat_desc.h b/drivers/staging/fw-api/hw/qca6750/v1/ce_stat_desc.h new file mode 100644 index 000000000000..c8a6890dec53 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/ce_stat_desc.h @@ -0,0 +1,329 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _CE_STAT_DESC_H_ +#define _CE_STAT_DESC_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 ce_res_5[7:0], toeplitz_en[8], src_swap[9], dest_swap[10], gather[11], ce_res_6[15:12], length[31:16] +// 1 toeplitz_hash_0[31:0] +// 2 toeplitz_hash_1[31:0] +// 3 fw_metadata[15:0], ce_res_7[19:16], ring_id[27:20], looping_count[31:28] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_CE_STAT_DESC 4 + +struct ce_stat_desc { + uint32_t ce_res_5 : 8, //[7:0] + toeplitz_en : 1, //[8] + src_swap : 1, //[9] + dest_swap : 1, //[10] + gather : 1, //[11] + ce_res_6 : 4, //[15:12] + length : 16; //[31:16] + uint32_t toeplitz_hash_0 : 32; //[31:0] + uint32_t toeplitz_hash_1 : 32; //[31:0] + uint32_t fw_metadata : 16, //[15:0] + ce_res_7 : 4, //[19:16] + ring_id : 8, //[27:20] + looping_count : 4; //[31:28] +}; + +/* + +ce_res_5 + + Reserved + + + +toeplitz_en + + + + +src_swap + + Source memory buffer swapped + + + +dest_swap + + Destination memory buffer swapped + + + +gather + + Gather of multiple copy engine source descriptors to one + destination enabled + + + +ce_res_6 + + Reserved + + + +length + + Sum of all the Lengths of the source descriptor in the + gather chain + + + +toeplitz_hash_0 + + 32 LS bits of 64 bit Toeplitz LFSR hash result + + + +toeplitz_hash_1 + + 32 MS bits of 64 bit Toeplitz LFSR hash result + + + +fw_metadata + + Meta data used by FW + + In case of gather field in first source ring entry of + the gather copy cycle in taken into account. + + + +ce_res_7 + + Reserved + + + +ring_id + + The buffer pointer ring ID. + + 0 refers to the IDLE ring + + 1 - N refers to other rings + + + + Helps with debugging when dumping ring contents. + + + +looping_count + + A count value that indicates the number of times the + producer of entries into the Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ + + +/* Description CE_STAT_DESC_0_CE_RES_5 + + Reserved + + +*/ +#define CE_STAT_DESC_0_CE_RES_5_OFFSET 0x00000000 +#define CE_STAT_DESC_0_CE_RES_5_LSB 0 +#define CE_STAT_DESC_0_CE_RES_5_MASK 0x000000ff + +/* Description CE_STAT_DESC_0_TOEPLITZ_EN + + + +*/ +#define CE_STAT_DESC_0_TOEPLITZ_EN_OFFSET 0x00000000 +#define CE_STAT_DESC_0_TOEPLITZ_EN_LSB 8 +#define CE_STAT_DESC_0_TOEPLITZ_EN_MASK 0x00000100 + +/* Description CE_STAT_DESC_0_SRC_SWAP + + Source memory buffer swapped + + +*/ +#define CE_STAT_DESC_0_SRC_SWAP_OFFSET 0x00000000 +#define CE_STAT_DESC_0_SRC_SWAP_LSB 9 +#define CE_STAT_DESC_0_SRC_SWAP_MASK 0x00000200 + +/* Description CE_STAT_DESC_0_DEST_SWAP + + Destination memory buffer swapped + + +*/ +#define CE_STAT_DESC_0_DEST_SWAP_OFFSET 0x00000000 +#define CE_STAT_DESC_0_DEST_SWAP_LSB 10 +#define CE_STAT_DESC_0_DEST_SWAP_MASK 0x00000400 + +/* Description CE_STAT_DESC_0_GATHER + + Gather of multiple copy engine source descriptors to one + destination enabled + + +*/ +#define CE_STAT_DESC_0_GATHER_OFFSET 0x00000000 +#define CE_STAT_DESC_0_GATHER_LSB 11 +#define CE_STAT_DESC_0_GATHER_MASK 0x00000800 + +/* Description CE_STAT_DESC_0_CE_RES_6 + + Reserved + + +*/ +#define CE_STAT_DESC_0_CE_RES_6_OFFSET 0x00000000 +#define CE_STAT_DESC_0_CE_RES_6_LSB 12 +#define CE_STAT_DESC_0_CE_RES_6_MASK 0x0000f000 + +/* Description CE_STAT_DESC_0_LENGTH + + Sum of all the Lengths of the source descriptor in the + gather chain + + +*/ +#define CE_STAT_DESC_0_LENGTH_OFFSET 0x00000000 +#define CE_STAT_DESC_0_LENGTH_LSB 16 +#define CE_STAT_DESC_0_LENGTH_MASK 0xffff0000 + +/* Description CE_STAT_DESC_1_TOEPLITZ_HASH_0 + + 32 LS bits of 64 bit Toeplitz LFSR hash result + + +*/ +#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_OFFSET 0x00000004 +#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_LSB 0 +#define CE_STAT_DESC_1_TOEPLITZ_HASH_0_MASK 0xffffffff + +/* Description CE_STAT_DESC_2_TOEPLITZ_HASH_1 + + 32 MS bits of 64 bit Toeplitz LFSR hash result + + +*/ +#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_OFFSET 0x00000008 +#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_LSB 0 +#define CE_STAT_DESC_2_TOEPLITZ_HASH_1_MASK 0xffffffff + +/* Description CE_STAT_DESC_3_FW_METADATA + + Meta data used by FW + + In case of gather field in first source ring entry of + the gather copy cycle in taken into account. + + +*/ +#define CE_STAT_DESC_3_FW_METADATA_OFFSET 0x0000000c +#define CE_STAT_DESC_3_FW_METADATA_LSB 0 +#define CE_STAT_DESC_3_FW_METADATA_MASK 0x0000ffff + +/* Description CE_STAT_DESC_3_CE_RES_7 + + Reserved + + +*/ +#define CE_STAT_DESC_3_CE_RES_7_OFFSET 0x0000000c +#define CE_STAT_DESC_3_CE_RES_7_LSB 16 +#define CE_STAT_DESC_3_CE_RES_7_MASK 0x000f0000 + +/* Description CE_STAT_DESC_3_RING_ID + + The buffer pointer ring ID. + + 0 refers to the IDLE ring + + 1 - N refers to other rings + + + + Helps with debugging when dumping ring contents. + + +*/ +#define CE_STAT_DESC_3_RING_ID_OFFSET 0x0000000c +#define CE_STAT_DESC_3_RING_ID_LSB 20 +#define CE_STAT_DESC_3_RING_ID_MASK 0x0ff00000 + +/* Description CE_STAT_DESC_3_LOOPING_COUNT + + A count value that indicates the number of times the + producer of entries into the Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ +#define CE_STAT_DESC_3_LOOPING_COUNT_OFFSET 0x0000000c +#define CE_STAT_DESC_3_LOOPING_COUNT_LSB 28 +#define CE_STAT_DESC_3_LOOPING_COUNT_MASK 0xf0000000 + + +#endif // _CE_STAT_DESC_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/com_dtypes.h b/drivers/staging/fw-api/hw/qca6750/v1/com_dtypes.h new file mode 100644 index 000000000000..c577a20c78fa --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/com_dtypes.h @@ -0,0 +1,300 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef COM_DTYPES_H +#define COM_DTYPES_H + +/** + @file com_dtypes.h + @brief This header file contains general data types that are of use to all + modules. + +*/ +/*=========================================================================== +NOTE: The @brief description and any detailed descriptions above do not appear + in the PDF. + + The Utility_Services_API_mainpage.dox file contains all file/group + descriptions that are in the output PDF generated using Doxygen and + Latex. To edit or update any of the file/group text in the PDF, edit + the Utility_Services_API_mainpage.dox file or contact Tech Pubs. + + The above description for this file is part of the "utils_services" + group description in the Utility_Services_API_mainpage.dox file. +===========================================================================*/ +/*=========================================================================== + + S T A N D A R D D E C L A R A T I O N S + +DESCRIPTION + This header file contains general data types that are of use to all modules. + The values or definitions are dependent on the specified + target. T_WINNT specifies Windows NT based targets, otherwise the + default is for ARM targets. + + T_WINNT Software is hosted on an NT platforn, triggers macro and + type definitions, unlike definition above which triggers + actual OS calls + +===========================================================================*/ + + +/*=========================================================================== + + EDIT HISTORY FOR FILE + +This section contains comments describing changes made to this file. +Notice that changes are listed in reverse chronological order. + +$Header: //depot/prj/qca/lithium/HWS/Q5_2p1/include/hwio/qca649x/E3R52/include/com_dtypes.h#1 $ + +when who what, where, why +-------- --- ---------------------------------------------------------- +03/21/11 llg (Tech Pubs) Edited/added Doxygen comments and markup. +11/09/10 EBR Doxygenated file. +09/15/09 pc Created file. +===========================================================================*/ + + +/*=========================================================================== + + Data Declarations + +===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + +/* For NT apps we want to use the Win32 definitions and/or those + supplied by the Win32 compiler for things like NULL, MAX, MIN + abs, labs, etc. +*/ +#ifdef T_WINNT + #ifndef WIN32 + #define WIN32 + #endif + #include +#endif + +/* ------------------------------------------------------------------------ +** Constants +** ------------------------------------------------------------------------ */ + +#ifdef TRUE +#undef TRUE +#endif + +#ifdef FALSE +#undef FALSE +#endif + +/** @addtogroup utils_services +@{ */ + +/** @name Macros for Common Data Types +@{ */ +#define TRUE 1 /**< Boolean TRUE value. */ +#define FALSE 0 /**< Boolean FALSE value. */ + +#define ON 1 /**< ON value. */ +#define OFF 0 /**< OFF value. */ + +#ifndef NULL + #define NULL 0 /**< NULL value. */ +#endif +/** @} */ /* end_name_group Macros for Common Data Types */ + +/* ----------------------------------------------------------------------- +** Standard Types +** ----------------------------------------------------------------------- */ + +/** @} */ /* end_addtogroup utils_services */ + +/* The following definitions are the same across platforms. This first + group are the sanctioned types. +*/ +#ifndef _ARM_ASM_ +#ifndef _BOOLEAN_DEFINED + +/** @addtogroup utils_services +@{ */ +/** Boolean value type. +*/ +typedef unsigned char boolean; +#define _BOOLEAN_DEFINED +#endif + +/** @cond +*/ +#if defined(DALSTDDEF_H) /* guards against a known re-definer */ +#define _BOOLEAN_DEFINED +#define _UINT32_DEFINED +#define _UINT16_DEFINED +#define _UINT8_DEFINED +#define _INT32_DEFINED +#define _INT16_DEFINED +#define _INT8_DEFINED +#define _UINT64_DEFINED +#define _INT64_DEFINED +#define _BYTE_DEFINED +#endif /* #if !defined(DALSTDDEF_H) */ +/** @endcond */ + +#ifndef _UINT32_DEFINED +/** Unsigned 32-bit value. +*/ +typedef unsigned long int uint32; +#define _UINT32_DEFINED +#endif + +#ifndef _UINT16_DEFINED +/** Unsigned 16-bit value. +*/ +typedef unsigned short uint16; +#define _UINT16_DEFINED +#endif + +#ifndef _UINT8_DEFINED +/** Unsigned 8-bit value. +*/ +typedef unsigned char uint8; +#define _UINT8_DEFINED +#endif + +#ifndef _INT32_DEFINED +/** Signed 32-bit value. +*/ +typedef signed long int int32; +#define _INT32_DEFINED +#endif + +#ifndef _INT16_DEFINED +/** Signed 16-bit value. +*/ +typedef signed short int16; +#define _INT16_DEFINED +#endif + +#ifndef _INT8_DEFINED +/** Signed 8-bit value. +*/ +typedef signed char int8; +#define _INT8_DEFINED +#endif + +/** @cond +*/ +/* This group are the deprecated types. Their use should be +** discontinued and new code should use the types above +*/ +#ifndef _BYTE_DEFINED +/** DEPRECATED: Unsigned 8 bit value type. +*/ +typedef unsigned char byte; +#define _BYTE_DEFINED +#endif + +/** DEPRECATED: Unsinged 16 bit value type. +*/ +typedef unsigned short word; +/** DEPRECATED: Unsigned 32 bit value type. +*/ +typedef unsigned long dword; + +/** DEPRECATED: Unsigned 8 bit value type. +*/ +typedef unsigned char uint1; +/** DEPRECATED: Unsigned 16 bit value type. +*/ +typedef unsigned short uint2; +/** DEPRECATED: Unsigned 32 bit value type. +*/ +typedef unsigned long uint4; + +/** DEPRECATED: Signed 8 bit value type. +*/ +typedef signed char int1; +/** DEPRECATED: Signed 16 bit value type. +*/ +typedef signed short int2; +/** DEPRECATED: Signed 32 bit value type. +*/ +typedef long int int4; + +/** DEPRECATED: Signed 32 bit value. +*/ +typedef signed long sint31; +/** DEPRECATED: Signed 16 bit value. +*/ +typedef signed short sint15; +/** DEPRECATED: Signed 8 bit value. +*/ +typedef signed char sint7; + +typedef uint16 UWord16 ; +typedef uint32 UWord32 ; +typedef int32 Word32 ; +typedef int16 Word16 ; +typedef uint8 UWord8 ; +typedef int8 Word8 ; +typedef int32 Vect32 ; +/** @endcond */ + +#if (! defined T_WINNT) && (! defined __GNUC__) + /* Non WinNT Targets */ + #ifndef _INT64_DEFINED + /** Signed 64-bit value. + */ + typedef long long int64; + #define _INT64_DEFINED + #endif + #ifndef _UINT64_DEFINED + /** Unsigned 64-bit value. + */ + typedef unsigned long long uint64; + #define _UINT64_DEFINED + #endif +#else /* T_WINNT || TARGET_OS_SOLARIS || __GNUC__ */ + /* WINNT or SOLARIS based targets */ + #if (defined __GNUC__) + #ifndef _INT64_DEFINED + typedef long long int64; + #define _INT64_DEFINED + #endif + #ifndef _UINT64_DEFINED + typedef unsigned long long uint64; + #define _UINT64_DEFINED + #endif + #else + typedef __int64 int64; /* Signed 64-bit value */ + #ifndef _UINT64_DEFINED + typedef unsigned __int64 uint64; /* Unsigned 64-bit value */ + #define _UINT64_DEFINED + #endif + #endif +#endif /* T_WINNT */ + +#endif /* _ARM_ASM_ */ + +#ifdef __cplusplus +} +#endif + +/** @} */ /* end_addtogroup utils_services */ +#endif /* COM_DTYPES_H */ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/he_sig_a_mu_dl_info.h b/drivers/staging/fw-api/hw/qca6750/v1/he_sig_a_mu_dl_info.h new file mode 100644 index 000000000000..f89b29e8c7fd --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/he_sig_a_mu_dl_info.h @@ -0,0 +1,697 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _HE_SIG_A_MU_DL_INFO_H_ +#define _HE_SIG_A_MU_DL_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 dl_ul_flag[0], mcs_of_sig_b[3:1], dcm_of_sig_b[4], bss_color_id[10:5], spatial_reuse[14:11], transmit_bw[17:15], num_sig_b_symbols[21:18], comp_mode_sig_b[22], cp_ltf_size[24:23], doppler_indication[25], reserved_0a[31:26] +// 1 txop_duration[6:0], reserved_1a[7], num_ltf_symbols[10:8], ldpc_extra_symbol[11], stbc[12], packet_extension_a_factor[14:13], packet_extension_pe_disambiguity[15], crc[19:16], tail[25:20], reserved_1b[31:26] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_HE_SIG_A_MU_DL_INFO 2 + +struct he_sig_a_mu_dl_info { + uint32_t dl_ul_flag : 1, //[0] + mcs_of_sig_b : 3, //[3:1] + dcm_of_sig_b : 1, //[4] + bss_color_id : 6, //[10:5] + spatial_reuse : 4, //[14:11] + transmit_bw : 3, //[17:15] + num_sig_b_symbols : 4, //[21:18] + comp_mode_sig_b : 1, //[22] + cp_ltf_size : 2, //[24:23] + doppler_indication : 1, //[25] + reserved_0a : 6; //[31:26] + uint32_t txop_duration : 7, //[6:0] + reserved_1a : 1, //[7] + num_ltf_symbols : 3, //[10:8] + ldpc_extra_symbol : 1, //[11] + stbc : 1, //[12] + packet_extension_a_factor : 2, //[14:13] + packet_extension_pe_disambiguity: 1, //[15] + crc : 4, //[19:16] + tail : 6, //[25:20] + reserved_1b : 6; //[31:26] +}; + +/* + +dl_ul_flag + + Differentiates between DL and UL transmission + + + + + + + + NOTE: This is unsupported for HE MU format (including + MU_SU) Tx in Napier and Hastings80. + + + +mcs_of_sig_b + + Indicates the MCS of HE-SIG-B + + + +dcm_of_sig_b + + Indicates whether dual sub-carrier modulation is applied + to HE-SIG-B + + + + 0: No DCM for HE_SIG_B + + 1: DCM for HE_SIG_B + + + +bss_color_id + + BSS color ID + + + + Field Used by MAC HW + + + +spatial_reuse + + Spatial reuse + + + + For 20MHz one SR field corresponding to entire 20MHz + (other 3 fields indicate identical values) + + For 40MHz two SR fields for each 20MHz (other 2 fields + indicate identical values) + + For 80MHz four SR fields for each 20MHz + + For 160MHz four SR fields for each 40MHz + + + +transmit_bw + + Bandwidth of the PPDU. + + + + 20 Mhz + + 40 Mhz + + 80 MHz non-preamble + puncturing mode + + 160 MHz and 80+80 MHz + non-preamble puncturing mode + + for preamble + puncturing in 80 MHz, where in the preamble only the + secondary 20 MHz is punctured + + for + preamble puncturing in 80 MHz, where in the preamble only + one of the two 20 MHz sub-channels in secondary 40 MHz is + punctured. + + for preamble + puncturing in 160 MHz or 80+80 MHz, where in the primary 80 + MHz of the preamble only the secondary 20 MHz is punctured. + + for + preamble puncturing in 160 MHz or 80+80 MHz, where in the + primary 80 MHz of the preamble the primary 40 MHz is + present. + + + + On RX side, Field Used by MAC HW + + + +num_sig_b_symbols + + Number of symbols + + + + For OFDMA, the actual number of symbols is 1 larger then + indicated in this field. + + + + For MU-MIMO this is equal to the number of users - 1: + the following encoding is used: + + 1 => 2 users + + 2 => 3 users + + Etc. + + + + + +comp_mode_sig_b + + Indicates the compression mode of HE-SIG-B + + + + 0: Regular [uncomp mode] + + 1: compressed mode (full-BW MU-MIMO only) + + + +cp_ltf_size + + Indicates the CP and HE-LTF type + + + + 4xLTF + 0.8 us CP + + 2x LTF + 0.8 µs CP + + 2x LTF + 1.6 µs CP + + 4x LTF + 3.2 µs CP + + + + NOTE: for MU no proprietary modes (for now) + + + + + +doppler_indication + + 0: No Doppler support + + 1: Doppler support + + + +reserved_0a + + + +txop_duration + + Indicates the remaining time in the current TXOP + + + + Field Used by MAC HW + + + +reserved_1a + + Note: spec indicates this shall be set to 1 + + + +num_ltf_symbols + + Indicates the number of HE-LTF symbols + + + + 0: 1 LTF + + 1: 2 LTFs + + 2: 4 LTFs + + 3: 6 LTFs + + 4: 8 LTFs + + + + + +ldpc_extra_symbol + + If LDPC, + + 0: LDPC extra symbol not present + + 1: LDPC extra symbol present + + Else + + Set to 1 + + + +stbc + + Indicates whether STBC is applied + + 0: No STBC + + 1: STBC + + + +packet_extension_a_factor + + the packet extension duration of the trigger-based PPDU + response with these two bits indicating the a-factor + + + + + + + + + + + + + + + +packet_extension_pe_disambiguity + + the packet extension duration of the trigger-based PPDU + response with this bit indicating the PE-Disambiguity + + + +crc + + CRC for HE-SIG-A contents. + + + +tail + + + +reserved_1b + + +*/ + + +/* Description HE_SIG_A_MU_DL_INFO_0_DL_UL_FLAG + + Differentiates between DL and UL transmission + + + + + + + + NOTE: This is unsupported for HE MU format (including + MU_SU) Tx in Napier and Hastings80. + + +*/ +#define HE_SIG_A_MU_DL_INFO_0_DL_UL_FLAG_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_DL_UL_FLAG_LSB 0 +#define HE_SIG_A_MU_DL_INFO_0_DL_UL_FLAG_MASK 0x00000001 + +/* Description HE_SIG_A_MU_DL_INFO_0_MCS_OF_SIG_B + + Indicates the MCS of HE-SIG-B + + +*/ +#define HE_SIG_A_MU_DL_INFO_0_MCS_OF_SIG_B_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_MCS_OF_SIG_B_LSB 1 +#define HE_SIG_A_MU_DL_INFO_0_MCS_OF_SIG_B_MASK 0x0000000e + +/* Description HE_SIG_A_MU_DL_INFO_0_DCM_OF_SIG_B + + Indicates whether dual sub-carrier modulation is applied + to HE-SIG-B + + + + 0: No DCM for HE_SIG_B + + 1: DCM for HE_SIG_B + + +*/ +#define HE_SIG_A_MU_DL_INFO_0_DCM_OF_SIG_B_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_DCM_OF_SIG_B_LSB 4 +#define HE_SIG_A_MU_DL_INFO_0_DCM_OF_SIG_B_MASK 0x00000010 + +/* Description HE_SIG_A_MU_DL_INFO_0_BSS_COLOR_ID + + BSS color ID + + + + Field Used by MAC HW + + +*/ +#define HE_SIG_A_MU_DL_INFO_0_BSS_COLOR_ID_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_BSS_COLOR_ID_LSB 5 +#define HE_SIG_A_MU_DL_INFO_0_BSS_COLOR_ID_MASK 0x000007e0 + +/* Description HE_SIG_A_MU_DL_INFO_0_SPATIAL_REUSE + + Spatial reuse + + + + For 20MHz one SR field corresponding to entire 20MHz + (other 3 fields indicate identical values) + + For 40MHz two SR fields for each 20MHz (other 2 fields + indicate identical values) + + For 80MHz four SR fields for each 20MHz + + For 160MHz four SR fields for each 40MHz + + +*/ +#define HE_SIG_A_MU_DL_INFO_0_SPATIAL_REUSE_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_SPATIAL_REUSE_LSB 11 +#define HE_SIG_A_MU_DL_INFO_0_SPATIAL_REUSE_MASK 0x00007800 + +/* Description HE_SIG_A_MU_DL_INFO_0_TRANSMIT_BW + + Bandwidth of the PPDU. + + + + 20 Mhz + + 40 Mhz + + 80 MHz non-preamble + puncturing mode + + 160 MHz and 80+80 MHz + non-preamble puncturing mode + + for preamble + puncturing in 80 MHz, where in the preamble only the + secondary 20 MHz is punctured + + for + preamble puncturing in 80 MHz, where in the preamble only + one of the two 20 MHz sub-channels in secondary 40 MHz is + punctured. + + for preamble + puncturing in 160 MHz or 80+80 MHz, where in the primary 80 + MHz of the preamble only the secondary 20 MHz is punctured. + + for + preamble puncturing in 160 MHz or 80+80 MHz, where in the + primary 80 MHz of the preamble the primary 40 MHz is + present. + + + + On RX side, Field Used by MAC HW + + +*/ +#define HE_SIG_A_MU_DL_INFO_0_TRANSMIT_BW_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_TRANSMIT_BW_LSB 15 +#define HE_SIG_A_MU_DL_INFO_0_TRANSMIT_BW_MASK 0x00038000 + +/* Description HE_SIG_A_MU_DL_INFO_0_NUM_SIG_B_SYMBOLS + + Number of symbols + + + + For OFDMA, the actual number of symbols is 1 larger then + indicated in this field. + + + + For MU-MIMO this is equal to the number of users - 1: + the following encoding is used: + + 1 => 2 users + + 2 => 3 users + + Etc. + + + + +*/ +#define HE_SIG_A_MU_DL_INFO_0_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_NUM_SIG_B_SYMBOLS_LSB 18 +#define HE_SIG_A_MU_DL_INFO_0_NUM_SIG_B_SYMBOLS_MASK 0x003c0000 + +/* Description HE_SIG_A_MU_DL_INFO_0_COMP_MODE_SIG_B + + Indicates the compression mode of HE-SIG-B + + + + 0: Regular [uncomp mode] + + 1: compressed mode (full-BW MU-MIMO only) + + +*/ +#define HE_SIG_A_MU_DL_INFO_0_COMP_MODE_SIG_B_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_COMP_MODE_SIG_B_LSB 22 +#define HE_SIG_A_MU_DL_INFO_0_COMP_MODE_SIG_B_MASK 0x00400000 + +/* Description HE_SIG_A_MU_DL_INFO_0_CP_LTF_SIZE + + Indicates the CP and HE-LTF type + + + + 4xLTF + 0.8 us CP + + 2x LTF + 0.8 µs CP + + 2x LTF + 1.6 µs CP + + 4x LTF + 3.2 µs CP + + + + NOTE: for MU no proprietary modes (for now) + + + + +*/ +#define HE_SIG_A_MU_DL_INFO_0_CP_LTF_SIZE_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_CP_LTF_SIZE_LSB 23 +#define HE_SIG_A_MU_DL_INFO_0_CP_LTF_SIZE_MASK 0x01800000 + +/* Description HE_SIG_A_MU_DL_INFO_0_DOPPLER_INDICATION + + 0: No Doppler support + + 1: Doppler support + + +*/ +#define HE_SIG_A_MU_DL_INFO_0_DOPPLER_INDICATION_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_DOPPLER_INDICATION_LSB 25 +#define HE_SIG_A_MU_DL_INFO_0_DOPPLER_INDICATION_MASK 0x02000000 + +/* Description HE_SIG_A_MU_DL_INFO_0_RESERVED_0A + + +*/ +#define HE_SIG_A_MU_DL_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_A_MU_DL_INFO_0_RESERVED_0A_LSB 26 +#define HE_SIG_A_MU_DL_INFO_0_RESERVED_0A_MASK 0xfc000000 + +/* Description HE_SIG_A_MU_DL_INFO_1_TXOP_DURATION + + Indicates the remaining time in the current TXOP + + + + Field Used by MAC HW + + +*/ +#define HE_SIG_A_MU_DL_INFO_1_TXOP_DURATION_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_TXOP_DURATION_LSB 0 +#define HE_SIG_A_MU_DL_INFO_1_TXOP_DURATION_MASK 0x0000007f + +/* Description HE_SIG_A_MU_DL_INFO_1_RESERVED_1A + + Note: spec indicates this shall be set to 1 + + +*/ +#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1A_LSB 7 +#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1A_MASK 0x00000080 + +/* Description HE_SIG_A_MU_DL_INFO_1_NUM_LTF_SYMBOLS + + Indicates the number of HE-LTF symbols + + + + 0: 1 LTF + + 1: 2 LTFs + + 2: 4 LTFs + + 3: 6 LTFs + + 4: 8 LTFs + + + + +*/ +#define HE_SIG_A_MU_DL_INFO_1_NUM_LTF_SYMBOLS_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_NUM_LTF_SYMBOLS_LSB 8 +#define HE_SIG_A_MU_DL_INFO_1_NUM_LTF_SYMBOLS_MASK 0x00000700 + +/* Description HE_SIG_A_MU_DL_INFO_1_LDPC_EXTRA_SYMBOL + + If LDPC, + + 0: LDPC extra symbol not present + + 1: LDPC extra symbol present + + Else + + Set to 1 + + +*/ +#define HE_SIG_A_MU_DL_INFO_1_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_LDPC_EXTRA_SYMBOL_LSB 11 +#define HE_SIG_A_MU_DL_INFO_1_LDPC_EXTRA_SYMBOL_MASK 0x00000800 + +/* Description HE_SIG_A_MU_DL_INFO_1_STBC + + Indicates whether STBC is applied + + 0: No STBC + + 1: STBC + + +*/ +#define HE_SIG_A_MU_DL_INFO_1_STBC_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_STBC_LSB 12 +#define HE_SIG_A_MU_DL_INFO_1_STBC_MASK 0x00001000 + +/* Description HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_A_FACTOR + + the packet extension duration of the trigger-based PPDU + response with these two bits indicating the a-factor + + + + + + + + + + + + + + +*/ +#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_A_FACTOR_LSB 13 +#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000 + +/* Description HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY + + the packet extension duration of the trigger-based PPDU + response with this bit indicating the PE-Disambiguity + + +*/ +#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15 +#define HE_SIG_A_MU_DL_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000 + +/* Description HE_SIG_A_MU_DL_INFO_1_CRC + + CRC for HE-SIG-A contents. + + +*/ +#define HE_SIG_A_MU_DL_INFO_1_CRC_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_CRC_LSB 16 +#define HE_SIG_A_MU_DL_INFO_1_CRC_MASK 0x000f0000 + +/* Description HE_SIG_A_MU_DL_INFO_1_TAIL + + +*/ +#define HE_SIG_A_MU_DL_INFO_1_TAIL_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_TAIL_LSB 20 +#define HE_SIG_A_MU_DL_INFO_1_TAIL_MASK 0x03f00000 + +/* Description HE_SIG_A_MU_DL_INFO_1_RESERVED_1B + + +*/ +#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1B_OFFSET 0x00000004 +#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1B_LSB 26 +#define HE_SIG_A_MU_DL_INFO_1_RESERVED_1B_MASK 0xfc000000 + + +#endif // _HE_SIG_A_MU_DL_INFO_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/he_sig_a_mu_ul_info.h b/drivers/staging/fw-api/hw/qca6750/v1/he_sig_a_mu_ul_info.h new file mode 100644 index 000000000000..9a05afd98b52 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/he_sig_a_mu_ul_info.h @@ -0,0 +1,273 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _HE_SIG_A_MU_UL_INFO_H_ +#define _HE_SIG_A_MU_UL_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 format_indication[0], bss_color_id[6:1], spatial_reuse[22:7], reserved_0a[23], transmit_bw[25:24], reserved_0b[31:26] +// 1 txop_duration[6:0], reserved_1a[15:7], crc[19:16], tail[25:20], reserved_1b[31:26] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_HE_SIG_A_MU_UL_INFO 2 + +struct he_sig_a_mu_ul_info { + uint32_t format_indication : 1, //[0] + bss_color_id : 6, //[6:1] + spatial_reuse : 16, //[22:7] + reserved_0a : 1, //[23] + transmit_bw : 2, //[25:24] + reserved_0b : 6; //[31:26] + uint32_t txop_duration : 7, //[6:0] + reserved_1a : 9, //[15:7] + crc : 4, //[19:16] + tail : 6, //[25:20] + reserved_1b : 6; //[31:26] +}; + +/* + +format_indication + + Indicates whether the transmission is SU PPDU or a + trigger based UL MU PDDU + + + + + + + +bss_color_id + + BSS color ID + + + +spatial_reuse + + Spatial reuse + + + + + +reserved_0a + + Note: spec indicates this shall be set to 1 + + + +transmit_bw + + Bandwidth of the PPDU. + + + + 20 Mhz + + 40 Mhz + + 80 Mhz + + 160 MHz or 80+80 MHz + + + + On RX side, Field Used by MAC HW + + + +reserved_0b + + + +txop_duration + + Indicates the remaining time in the current TXOP + +reserved_1a + + Set to value indicated in the trigger frame + + + +crc + + CRC for HE-SIG-A contents. + + This CRC may also cover some fields of L-SIG (TBD) + + + +tail + + BCC encoding (similar to VHT-SIG-A) with 6 tail bits is + used + + + +reserved_1b + + +*/ + + +/* Description HE_SIG_A_MU_UL_INFO_0_FORMAT_INDICATION + + Indicates whether the transmission is SU PPDU or a + trigger based UL MU PDDU + + + + + + +*/ +#define HE_SIG_A_MU_UL_INFO_0_FORMAT_INDICATION_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_0_FORMAT_INDICATION_LSB 0 +#define HE_SIG_A_MU_UL_INFO_0_FORMAT_INDICATION_MASK 0x00000001 + +/* Description HE_SIG_A_MU_UL_INFO_0_BSS_COLOR_ID + + BSS color ID + + +*/ +#define HE_SIG_A_MU_UL_INFO_0_BSS_COLOR_ID_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_0_BSS_COLOR_ID_LSB 1 +#define HE_SIG_A_MU_UL_INFO_0_BSS_COLOR_ID_MASK 0x0000007e + +/* Description HE_SIG_A_MU_UL_INFO_0_SPATIAL_REUSE + + Spatial reuse + + + + +*/ +#define HE_SIG_A_MU_UL_INFO_0_SPATIAL_REUSE_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_0_SPATIAL_REUSE_LSB 7 +#define HE_SIG_A_MU_UL_INFO_0_SPATIAL_REUSE_MASK 0x007fff80 + +/* Description HE_SIG_A_MU_UL_INFO_0_RESERVED_0A + + Note: spec indicates this shall be set to 1 + + +*/ +#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0A_LSB 23 +#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0A_MASK 0x00800000 + +/* Description HE_SIG_A_MU_UL_INFO_0_TRANSMIT_BW + + Bandwidth of the PPDU. + + + + 20 Mhz + + 40 Mhz + + 80 Mhz + + 160 MHz or 80+80 MHz + + + + On RX side, Field Used by MAC HW + + +*/ +#define HE_SIG_A_MU_UL_INFO_0_TRANSMIT_BW_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_0_TRANSMIT_BW_LSB 24 +#define HE_SIG_A_MU_UL_INFO_0_TRANSMIT_BW_MASK 0x03000000 + +/* Description HE_SIG_A_MU_UL_INFO_0_RESERVED_0B + + +*/ +#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0B_OFFSET 0x00000000 +#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0B_LSB 26 +#define HE_SIG_A_MU_UL_INFO_0_RESERVED_0B_MASK 0xfc000000 + +/* Description HE_SIG_A_MU_UL_INFO_1_TXOP_DURATION + + Indicates the remaining time in the current TXOP +*/ +#define HE_SIG_A_MU_UL_INFO_1_TXOP_DURATION_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_1_TXOP_DURATION_LSB 0 +#define HE_SIG_A_MU_UL_INFO_1_TXOP_DURATION_MASK 0x0000007f + +/* Description HE_SIG_A_MU_UL_INFO_1_RESERVED_1A + + Set to value indicated in the trigger frame + + +*/ +#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1A_LSB 7 +#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1A_MASK 0x0000ff80 + +/* Description HE_SIG_A_MU_UL_INFO_1_CRC + + CRC for HE-SIG-A contents. + + This CRC may also cover some fields of L-SIG (TBD) + + +*/ +#define HE_SIG_A_MU_UL_INFO_1_CRC_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_1_CRC_LSB 16 +#define HE_SIG_A_MU_UL_INFO_1_CRC_MASK 0x000f0000 + +/* Description HE_SIG_A_MU_UL_INFO_1_TAIL + + BCC encoding (similar to VHT-SIG-A) with 6 tail bits is + used + + +*/ +#define HE_SIG_A_MU_UL_INFO_1_TAIL_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_1_TAIL_LSB 20 +#define HE_SIG_A_MU_UL_INFO_1_TAIL_MASK 0x03f00000 + +/* Description HE_SIG_A_MU_UL_INFO_1_RESERVED_1B + + +*/ +#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1B_OFFSET 0x00000004 +#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1B_LSB 26 +#define HE_SIG_A_MU_UL_INFO_1_RESERVED_1B_MASK 0xfc000000 + + +#endif // _HE_SIG_A_MU_UL_INFO_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/he_sig_a_su_info.h b/drivers/staging/fw-api/hw/qca6750/v1/he_sig_a_su_info.h new file mode 100644 index 000000000000..5b528e662cda --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/he_sig_a_su_info.h @@ -0,0 +1,866 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _HE_SIG_A_SU_INFO_H_ +#define _HE_SIG_A_SU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 format_indication[0], beam_change[1], dl_ul_flag[2], transmit_mcs[6:3], dcm[7], bss_color_id[13:8], reserved_0a[14], spatial_reuse[18:15], transmit_bw[20:19], cp_ltf_size[22:21], nsts[25:23], reserved_0b[31:26] +// 1 txop_duration[6:0], coding[7], ldpc_extra_symbol[8], stbc[9], txbf[10], packet_extension_a_factor[12:11], packet_extension_pe_disambiguity[13], reserved_1a[14], doppler_indication[15], crc[19:16], tail[25:20], dot11ax_su_extended[26], dot11ax_ext_ru_size[30:27], rx_ndp[31] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_HE_SIG_A_SU_INFO 2 + +struct he_sig_a_su_info { + uint32_t format_indication : 1, //[0] + beam_change : 1, //[1] + dl_ul_flag : 1, //[2] + transmit_mcs : 4, //[6:3] + dcm : 1, //[7] + bss_color_id : 6, //[13:8] + reserved_0a : 1, //[14] + spatial_reuse : 4, //[18:15] + transmit_bw : 2, //[20:19] + cp_ltf_size : 2, //[22:21] + nsts : 3, //[25:23] + reserved_0b : 6; //[31:26] + uint32_t txop_duration : 7, //[6:0] + coding : 1, //[7] + ldpc_extra_symbol : 1, //[8] + stbc : 1, //[9] + txbf : 1, //[10] + packet_extension_a_factor : 2, //[12:11] + packet_extension_pe_disambiguity: 1, //[13] + reserved_1a : 1, //[14] + doppler_indication : 1, //[15] + crc : 4, //[19:16] + tail : 6, //[25:20] + dot11ax_su_extended : 1, //[26] + dot11ax_ext_ru_size : 4, //[30:27] + rx_ndp : 1; //[31] +}; + +/* + +format_indication + + + + + + + +beam_change + + Indicates whether spatial mapping is changed between + legacy and HE portion of preamble. If not, channel + estimation can include legacy preamble to improve accuracy + + + +dl_ul_flag + + Differentiates between DL and UL transmission + + + + + + + + + +transmit_mcs + + Indicates the data MCS + + + + Field Used by MAC HW + + + +dcm + + + 0: No DCM + + 1:DCM + + + +bss_color_id + + BSS color ID + + + + Field Used by MAC HW + + + +reserved_0a + + Note: spec indicates this shall be set to 1 + + + +spatial_reuse + + Spatial reuse + + + + For 20MHz one SR field corresponding to entire 20MHz + (other 3 fields indicate identical values) + + For 40MHz two SR fields for each 20MHz (other 2 fields + indicate identical values) + + For 80MHz four SR fields for each 20MHz + + For 160MHz four SR fields for each 40MHz + + + +transmit_bw + + Bandwidth of the PPDU. + + + + For HE SU PPDU + + + 20 Mhz + + 40 Mhz + + 80 Mhz + + 160 MHz or 80+80 MHz + + + + For HE Extended Range SU PPDU + + Set to 0 for 242-tone RU + Set to 1 for right 106-tone RU within the primary 20 MHz + + + + On RX side, Field Used by MAC HW + + + +cp_ltf_size + + Indicates the CP and HE-LTF type + + + + 1xLTF + 0.8 us CP (See note for + proprietary mode) + + 2x LTF + 0.8 µs CP (See note + for proprietary mode) + + 2x LTF + 1.6 µs CP (See note + for proprietary mode) + + + + + + When DCM == 0 OR STBC == 0: 4x LTF + 3.2 µs CP + + When DCM == 1 AND STBC == 1: 4x LTF + 0.8 µs CP. Note: + In this scenario, Neither DCM nor STBC is applied to HE data + field. + + (See note for proprietary mode) + + + + NOTE: + + For QCA proprietary mode + + If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0) + + 0 = 1xLTF + 0.4 usec + + 1 = 2xLTF + 0.4 usec + + 2~3 = Reserved + + + + + +nsts + + + + + For HE SU PPDU + + + + For HE Extended Range PPDU + + + +reserved_0b + + + +txop_duration + + Indicates the remaining time in the current TXOP + + + + Field Used by MAC HW + + + +coding + + Distinguishes between BCC and LDPC coding. + + + + 0: BCC + + 1: LDPC + + + +ldpc_extra_symbol + + If LDPC, + + 0: LDPC extra symbol not present + + 1: LDPC extra symbol present + + Else + + Set to 1 + + + +stbc + + Indicates whether STBC is applied + + 0: No STBC + + 1: STBC + + + +txbf + + Indicates whether beamforming is applied + + 0: No beamforming + + 1: beamforming + + + +packet_extension_a_factor + + Common trigger info + + + + the packet extension duration of the trigger-based PPDU + response with these two bits indicating the a-factor + + + + + + + + + + + + + + + +packet_extension_pe_disambiguity + + Common trigger info + + + + the packet extension duration of the trigger-based PPDU + response with this bit indicating the PE-Disambiguity + + + +reserved_1a + + Note: per standard, set to 1 + + + +doppler_indication + + 0: No Doppler support + + 1: Doppler support + + + +crc + + CRC for HE-SIG-A contents. + + + +tail + + + +dot11ax_su_extended + + TX side: + + Set to 0 + + + + RX side: + + On RX side, evaluated by MAC HW. This is the only way + for MAC RX to know that this was an HE_SIG_A_SU received in + 'extended' format + + + + + + +dot11ax_ext_ru_size + + TX side: + + Set to 0 + + + + RX side: + + Field only contains valid info when dot11ax_su_extended + is set. + + + + On RX side, evaluated by MAC HW. This is the only way + for MAC RX to know what the number of based RUs was in this + extended range reception. It is used by the MAC to determine + the RU size for the response... + + + +rx_ndp + + TX side: + + Set to 0 + + + + RX side:Valid on RX side only, and looked at by MAC HW + + + + When set, PHY has received (expected) NDP frame + + +*/ + + +/* Description HE_SIG_A_SU_INFO_0_FORMAT_INDICATION + + + + + + +*/ +#define HE_SIG_A_SU_INFO_0_FORMAT_INDICATION_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_FORMAT_INDICATION_LSB 0 +#define HE_SIG_A_SU_INFO_0_FORMAT_INDICATION_MASK 0x00000001 + +/* Description HE_SIG_A_SU_INFO_0_BEAM_CHANGE + + Indicates whether spatial mapping is changed between + legacy and HE portion of preamble. If not, channel + estimation can include legacy preamble to improve accuracy + + +*/ +#define HE_SIG_A_SU_INFO_0_BEAM_CHANGE_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_BEAM_CHANGE_LSB 1 +#define HE_SIG_A_SU_INFO_0_BEAM_CHANGE_MASK 0x00000002 + +/* Description HE_SIG_A_SU_INFO_0_DL_UL_FLAG + + Differentiates between DL and UL transmission + + + + + + + + +*/ +#define HE_SIG_A_SU_INFO_0_DL_UL_FLAG_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_DL_UL_FLAG_LSB 2 +#define HE_SIG_A_SU_INFO_0_DL_UL_FLAG_MASK 0x00000004 + +/* Description HE_SIG_A_SU_INFO_0_TRANSMIT_MCS + + Indicates the data MCS + + + + Field Used by MAC HW + + +*/ +#define HE_SIG_A_SU_INFO_0_TRANSMIT_MCS_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_TRANSMIT_MCS_LSB 3 +#define HE_SIG_A_SU_INFO_0_TRANSMIT_MCS_MASK 0x00000078 + +/* Description HE_SIG_A_SU_INFO_0_DCM + + + 0: No DCM + + 1:DCM + + +*/ +#define HE_SIG_A_SU_INFO_0_DCM_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_DCM_LSB 7 +#define HE_SIG_A_SU_INFO_0_DCM_MASK 0x00000080 + +/* Description HE_SIG_A_SU_INFO_0_BSS_COLOR_ID + + BSS color ID + + + + Field Used by MAC HW + + +*/ +#define HE_SIG_A_SU_INFO_0_BSS_COLOR_ID_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_BSS_COLOR_ID_LSB 8 +#define HE_SIG_A_SU_INFO_0_BSS_COLOR_ID_MASK 0x00003f00 + +/* Description HE_SIG_A_SU_INFO_0_RESERVED_0A + + Note: spec indicates this shall be set to 1 + + +*/ +#define HE_SIG_A_SU_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_RESERVED_0A_LSB 14 +#define HE_SIG_A_SU_INFO_0_RESERVED_0A_MASK 0x00004000 + +/* Description HE_SIG_A_SU_INFO_0_SPATIAL_REUSE + + Spatial reuse + + + + For 20MHz one SR field corresponding to entire 20MHz + (other 3 fields indicate identical values) + + For 40MHz two SR fields for each 20MHz (other 2 fields + indicate identical values) + + For 80MHz four SR fields for each 20MHz + + For 160MHz four SR fields for each 40MHz + + +*/ +#define HE_SIG_A_SU_INFO_0_SPATIAL_REUSE_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_SPATIAL_REUSE_LSB 15 +#define HE_SIG_A_SU_INFO_0_SPATIAL_REUSE_MASK 0x00078000 + +/* Description HE_SIG_A_SU_INFO_0_TRANSMIT_BW + + Bandwidth of the PPDU. + + + + For HE SU PPDU + + + 20 Mhz + + 40 Mhz + + 80 Mhz + + 160 MHz or 80+80 MHz + + + + For HE Extended Range SU PPDU + + Set to 0 for 242-tone RU + Set to 1 for right 106-tone RU within the primary 20 MHz + + + + On RX side, Field Used by MAC HW + + +*/ +#define HE_SIG_A_SU_INFO_0_TRANSMIT_BW_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_TRANSMIT_BW_LSB 19 +#define HE_SIG_A_SU_INFO_0_TRANSMIT_BW_MASK 0x00180000 + +/* Description HE_SIG_A_SU_INFO_0_CP_LTF_SIZE + + Indicates the CP and HE-LTF type + + + + 1xLTF + 0.8 us CP (See note for + proprietary mode) + + 2x LTF + 0.8 µs CP (See note + for proprietary mode) + + 2x LTF + 1.6 µs CP (See note + for proprietary mode) + + + + + + When DCM == 0 OR STBC == 0: 4x LTF + 3.2 µs CP + + When DCM == 1 AND STBC == 1: 4x LTF + 0.8 µs CP. Note: + In this scenario, Neither DCM nor STBC is applied to HE data + field. + + (See note for proprietary mode) + + + + NOTE: + + For QCA proprietary mode + + If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0) + + 0 = 1xLTF + 0.4 usec + + 1 = 2xLTF + 0.4 usec + + 2~3 = Reserved + + + + +*/ +#define HE_SIG_A_SU_INFO_0_CP_LTF_SIZE_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_CP_LTF_SIZE_LSB 21 +#define HE_SIG_A_SU_INFO_0_CP_LTF_SIZE_MASK 0x00600000 + +/* Description HE_SIG_A_SU_INFO_0_NSTS + + + + + For HE SU PPDU + + + + For HE Extended Range PPDU + + +*/ +#define HE_SIG_A_SU_INFO_0_NSTS_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_NSTS_LSB 23 +#define HE_SIG_A_SU_INFO_0_NSTS_MASK 0x03800000 + +/* Description HE_SIG_A_SU_INFO_0_RESERVED_0B + + +*/ +#define HE_SIG_A_SU_INFO_0_RESERVED_0B_OFFSET 0x00000000 +#define HE_SIG_A_SU_INFO_0_RESERVED_0B_LSB 26 +#define HE_SIG_A_SU_INFO_0_RESERVED_0B_MASK 0xfc000000 + +/* Description HE_SIG_A_SU_INFO_1_TXOP_DURATION + + Indicates the remaining time in the current TXOP + + + + Field Used by MAC HW + + +*/ +#define HE_SIG_A_SU_INFO_1_TXOP_DURATION_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_TXOP_DURATION_LSB 0 +#define HE_SIG_A_SU_INFO_1_TXOP_DURATION_MASK 0x0000007f + +/* Description HE_SIG_A_SU_INFO_1_CODING + + Distinguishes between BCC and LDPC coding. + + + + 0: BCC + + 1: LDPC + + +*/ +#define HE_SIG_A_SU_INFO_1_CODING_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_CODING_LSB 7 +#define HE_SIG_A_SU_INFO_1_CODING_MASK 0x00000080 + +/* Description HE_SIG_A_SU_INFO_1_LDPC_EXTRA_SYMBOL + + If LDPC, + + 0: LDPC extra symbol not present + + 1: LDPC extra symbol present + + Else + + Set to 1 + + +*/ +#define HE_SIG_A_SU_INFO_1_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_LDPC_EXTRA_SYMBOL_LSB 8 +#define HE_SIG_A_SU_INFO_1_LDPC_EXTRA_SYMBOL_MASK 0x00000100 + +/* Description HE_SIG_A_SU_INFO_1_STBC + + Indicates whether STBC is applied + + 0: No STBC + + 1: STBC + + +*/ +#define HE_SIG_A_SU_INFO_1_STBC_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_STBC_LSB 9 +#define HE_SIG_A_SU_INFO_1_STBC_MASK 0x00000200 + +/* Description HE_SIG_A_SU_INFO_1_TXBF + + Indicates whether beamforming is applied + + 0: No beamforming + + 1: beamforming + + +*/ +#define HE_SIG_A_SU_INFO_1_TXBF_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_TXBF_LSB 10 +#define HE_SIG_A_SU_INFO_1_TXBF_MASK 0x00000400 + +/* Description HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_A_FACTOR + + Common trigger info + + + + the packet extension duration of the trigger-based PPDU + response with these two bits indicating the a-factor + + + + + + + + + + + + + + +*/ +#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_A_FACTOR_LSB 11 +#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800 + +/* Description HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY + + Common trigger info + + + + the packet extension duration of the trigger-based PPDU + response with this bit indicating the PE-Disambiguity + + +*/ +#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13 +#define HE_SIG_A_SU_INFO_1_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000 + +/* Description HE_SIG_A_SU_INFO_1_RESERVED_1A + + Note: per standard, set to 1 + + +*/ +#define HE_SIG_A_SU_INFO_1_RESERVED_1A_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_RESERVED_1A_LSB 14 +#define HE_SIG_A_SU_INFO_1_RESERVED_1A_MASK 0x00004000 + +/* Description HE_SIG_A_SU_INFO_1_DOPPLER_INDICATION + + 0: No Doppler support + + 1: Doppler support + + +*/ +#define HE_SIG_A_SU_INFO_1_DOPPLER_INDICATION_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_DOPPLER_INDICATION_LSB 15 +#define HE_SIG_A_SU_INFO_1_DOPPLER_INDICATION_MASK 0x00008000 + +/* Description HE_SIG_A_SU_INFO_1_CRC + + CRC for HE-SIG-A contents. + + +*/ +#define HE_SIG_A_SU_INFO_1_CRC_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_CRC_LSB 16 +#define HE_SIG_A_SU_INFO_1_CRC_MASK 0x000f0000 + +/* Description HE_SIG_A_SU_INFO_1_TAIL + + +*/ +#define HE_SIG_A_SU_INFO_1_TAIL_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_TAIL_LSB 20 +#define HE_SIG_A_SU_INFO_1_TAIL_MASK 0x03f00000 + +/* Description HE_SIG_A_SU_INFO_1_DOT11AX_SU_EXTENDED + + TX side: + + Set to 0 + + + + RX side: + + On RX side, evaluated by MAC HW. This is the only way + for MAC RX to know that this was an HE_SIG_A_SU received in + 'extended' format + + + + + +*/ +#define HE_SIG_A_SU_INFO_1_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_DOT11AX_SU_EXTENDED_LSB 26 +#define HE_SIG_A_SU_INFO_1_DOT11AX_SU_EXTENDED_MASK 0x04000000 + +/* Description HE_SIG_A_SU_INFO_1_DOT11AX_EXT_RU_SIZE + + TX side: + + Set to 0 + + + + RX side: + + Field only contains valid info when dot11ax_su_extended + is set. + + + + On RX side, evaluated by MAC HW. This is the only way + for MAC RX to know what the number of based RUs was in this + extended range reception. It is used by the MAC to determine + the RU size for the response... + + +*/ +#define HE_SIG_A_SU_INFO_1_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_DOT11AX_EXT_RU_SIZE_LSB 27 +#define HE_SIG_A_SU_INFO_1_DOT11AX_EXT_RU_SIZE_MASK 0x78000000 + +/* Description HE_SIG_A_SU_INFO_1_RX_NDP + + TX side: + + Set to 0 + + + + RX side:Valid on RX side only, and looked at by MAC HW + + + + When set, PHY has received (expected) NDP frame + + +*/ +#define HE_SIG_A_SU_INFO_1_RX_NDP_OFFSET 0x00000004 +#define HE_SIG_A_SU_INFO_1_RX_NDP_LSB 31 +#define HE_SIG_A_SU_INFO_1_RX_NDP_MASK 0x80000000 + + +#endif // _HE_SIG_A_SU_INFO_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/he_sig_b1_mu_info.h b/drivers/staging/fw-api/hw/qca6750/v1/he_sig_b1_mu_info.h new file mode 100644 index 000000000000..8e0c108c04f5 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/he_sig_b1_mu_info.h @@ -0,0 +1,87 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _HE_SIG_B1_MU_INFO_H_ +#define _HE_SIG_B1_MU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 ru_allocation[7:0], reserved_0[31:8] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_HE_SIG_B1_MU_INFO 1 + +struct he_sig_b1_mu_info { + uint32_t ru_allocation : 8, //[7:0] + reserved_0 : 24; //[31:8] +}; + +/* + +ru_allocation + + RU allocation for the user(s) following this common + portion of the SIG + + + + For details, refer to RU_TYPE description + + + +reserved_0 + + +*/ + + +/* Description HE_SIG_B1_MU_INFO_0_RU_ALLOCATION + + RU allocation for the user(s) following this common + portion of the SIG + + + + For details, refer to RU_TYPE description + + +*/ +#define HE_SIG_B1_MU_INFO_0_RU_ALLOCATION_OFFSET 0x00000000 +#define HE_SIG_B1_MU_INFO_0_RU_ALLOCATION_LSB 0 +#define HE_SIG_B1_MU_INFO_0_RU_ALLOCATION_MASK 0x000000ff + +/* Description HE_SIG_B1_MU_INFO_0_RESERVED_0 + + +*/ +#define HE_SIG_B1_MU_INFO_0_RESERVED_0_OFFSET 0x00000000 +#define HE_SIG_B1_MU_INFO_0_RESERVED_0_LSB 8 +#define HE_SIG_B1_MU_INFO_0_RESERVED_0_MASK 0xffffff00 + + +#endif // _HE_SIG_B1_MU_INFO_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/he_sig_b2_mu_info.h b/drivers/staging/fw-api/hw/qca6750/v1/he_sig_b2_mu_info.h new file mode 100644 index 000000000000..8dd866dd8f00 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/he_sig_b2_mu_info.h @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _HE_SIG_B2_MU_INFO_H_ +#define _HE_SIG_B2_MU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 sta_id[10:0], sta_spatial_config[14:11], sta_mcs[18:15], reserved_set_to_1[19], sta_coding[20], reserved_0a[28:21], nsts[31:29] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_HE_SIG_B2_MU_INFO 1 + +struct he_sig_b2_mu_info { + uint32_t sta_id : 11, //[10:0] + sta_spatial_config : 4, //[14:11] + sta_mcs : 4, //[18:15] + reserved_set_to_1 : 1, //[19] + sta_coding : 1, //[20] + reserved_0a : 8, //[28:21] + nsts : 3; //[31:29] +}; + +/* + +sta_id + + Identifies the STA that is addressed. Details of STA ID + are TBD + +sta_spatial_config + + Number of assigned spatial streams and their + corresponding index. + + Total number of spatial streams assigned for the MU-MIMO + allocation is also signaled. + +sta_mcs + + Indicates the data MCS + +reserved_set_to_1 + + + +sta_coding + + Distinguishes between BCC/LDPC + + + + 0: BCC + + 1: LDPC + + + +reserved_0a + + + +nsts + + MAC RX side usage only: + + Needed by RXPCU. Provided by PHY so that RXPCU does not + need to have the RU number decoding logic. + + + + Number of spatial streams for this user + + + + Single spatial stream + + 2 spatial streams + + 3 spatial streams + + 4 spatial streams + + 5 spatial streams + + 6 spatial streams + + 7 spatial streams + + 8 spatial streams +*/ + + +/* Description HE_SIG_B2_MU_INFO_0_STA_ID + + Identifies the STA that is addressed. Details of STA ID + are TBD +*/ +#define HE_SIG_B2_MU_INFO_0_STA_ID_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_0_STA_ID_LSB 0 +#define HE_SIG_B2_MU_INFO_0_STA_ID_MASK 0x000007ff + +/* Description HE_SIG_B2_MU_INFO_0_STA_SPATIAL_CONFIG + + Number of assigned spatial streams and their + corresponding index. + + Total number of spatial streams assigned for the MU-MIMO + allocation is also signaled. +*/ +#define HE_SIG_B2_MU_INFO_0_STA_SPATIAL_CONFIG_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_0_STA_SPATIAL_CONFIG_LSB 11 +#define HE_SIG_B2_MU_INFO_0_STA_SPATIAL_CONFIG_MASK 0x00007800 + +/* Description HE_SIG_B2_MU_INFO_0_STA_MCS + + Indicates the data MCS +*/ +#define HE_SIG_B2_MU_INFO_0_STA_MCS_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_0_STA_MCS_LSB 15 +#define HE_SIG_B2_MU_INFO_0_STA_MCS_MASK 0x00078000 + +/* Description HE_SIG_B2_MU_INFO_0_RESERVED_SET_TO_1 + + +*/ +#define HE_SIG_B2_MU_INFO_0_RESERVED_SET_TO_1_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_0_RESERVED_SET_TO_1_LSB 19 +#define HE_SIG_B2_MU_INFO_0_RESERVED_SET_TO_1_MASK 0x00080000 + +/* Description HE_SIG_B2_MU_INFO_0_STA_CODING + + Distinguishes between BCC/LDPC + + + + 0: BCC + + 1: LDPC + + +*/ +#define HE_SIG_B2_MU_INFO_0_STA_CODING_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_0_STA_CODING_LSB 20 +#define HE_SIG_B2_MU_INFO_0_STA_CODING_MASK 0x00100000 + +/* Description HE_SIG_B2_MU_INFO_0_RESERVED_0A + + +*/ +#define HE_SIG_B2_MU_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_0_RESERVED_0A_LSB 21 +#define HE_SIG_B2_MU_INFO_0_RESERVED_0A_MASK 0x1fe00000 + +/* Description HE_SIG_B2_MU_INFO_0_NSTS + + MAC RX side usage only: + + Needed by RXPCU. Provided by PHY so that RXPCU does not + need to have the RU number decoding logic. + + + + Number of spatial streams for this user + + + + Single spatial stream + + 2 spatial streams + + 3 spatial streams + + 4 spatial streams + + 5 spatial streams + + 6 spatial streams + + 7 spatial streams + + 8 spatial streams +*/ +#define HE_SIG_B2_MU_INFO_0_NSTS_OFFSET 0x00000000 +#define HE_SIG_B2_MU_INFO_0_NSTS_LSB 29 +#define HE_SIG_B2_MU_INFO_0_NSTS_MASK 0xe0000000 + + +#endif // _HE_SIG_B2_MU_INFO_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/he_sig_b2_ofdma_info.h b/drivers/staging/fw-api/hw/qca6750/v1/he_sig_b2_ofdma_info.h new file mode 100644 index 000000000000..0a9efeccbd3e --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/he_sig_b2_ofdma_info.h @@ -0,0 +1,222 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _HE_SIG_B2_OFDMA_INFO_H_ +#define _HE_SIG_B2_OFDMA_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 sta_id[10:0], nsts[13:11], txbf[14], sta_mcs[18:15], sta_dcm[19], sta_coding[20], reserved_0[31:21] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_HE_SIG_B2_OFDMA_INFO 1 + +struct he_sig_b2_ofdma_info { + uint32_t sta_id : 11, //[10:0] + nsts : 3, //[13:11] + txbf : 1, //[14] + sta_mcs : 4, //[18:15] + sta_dcm : 1, //[19] + sta_coding : 1, //[20] + reserved_0 : 11; //[31:21] +}; + +/* + +sta_id + + Identifies the STA that is addressed. Details of STA ID + are TBD + +nsts + + MAC RX side usage only: + + + + Number of spatial streams for this user + + + + Single spatial stream + + 2 spatial streams + + 3 spatial streams + + 4 spatial streams + + 5 spatial streams + + 6 spatial streams + + 7 spatial streams + + 8 spatial streams + +txbf + + Indicates whether beamforming is applied + + 0: No beamforming + + 1: beamforming + + + +sta_mcs + + Indicates the data MCS + +sta_dcm + + + 0: No DCM + + 1:DCM + + + +sta_coding + + Distinguishes between BCC/LDPC + + + + 0: BCC + + 1: LDPC + + + +reserved_0 + + +*/ + + +/* Description HE_SIG_B2_OFDMA_INFO_0_STA_ID + + Identifies the STA that is addressed. Details of STA ID + are TBD +*/ +#define HE_SIG_B2_OFDMA_INFO_0_STA_ID_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_0_STA_ID_LSB 0 +#define HE_SIG_B2_OFDMA_INFO_0_STA_ID_MASK 0x000007ff + +/* Description HE_SIG_B2_OFDMA_INFO_0_NSTS + + MAC RX side usage only: + + + + Number of spatial streams for this user + + + + Single spatial stream + + 2 spatial streams + + 3 spatial streams + + 4 spatial streams + + 5 spatial streams + + 6 spatial streams + + 7 spatial streams + + 8 spatial streams +*/ +#define HE_SIG_B2_OFDMA_INFO_0_NSTS_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_0_NSTS_LSB 11 +#define HE_SIG_B2_OFDMA_INFO_0_NSTS_MASK 0x00003800 + +/* Description HE_SIG_B2_OFDMA_INFO_0_TXBF + + Indicates whether beamforming is applied + + 0: No beamforming + + 1: beamforming + + +*/ +#define HE_SIG_B2_OFDMA_INFO_0_TXBF_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_0_TXBF_LSB 14 +#define HE_SIG_B2_OFDMA_INFO_0_TXBF_MASK 0x00004000 + +/* Description HE_SIG_B2_OFDMA_INFO_0_STA_MCS + + Indicates the data MCS +*/ +#define HE_SIG_B2_OFDMA_INFO_0_STA_MCS_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_0_STA_MCS_LSB 15 +#define HE_SIG_B2_OFDMA_INFO_0_STA_MCS_MASK 0x00078000 + +/* Description HE_SIG_B2_OFDMA_INFO_0_STA_DCM + + + 0: No DCM + + 1:DCM + + +*/ +#define HE_SIG_B2_OFDMA_INFO_0_STA_DCM_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_0_STA_DCM_LSB 19 +#define HE_SIG_B2_OFDMA_INFO_0_STA_DCM_MASK 0x00080000 + +/* Description HE_SIG_B2_OFDMA_INFO_0_STA_CODING + + Distinguishes between BCC/LDPC + + + + 0: BCC + + 1: LDPC + + +*/ +#define HE_SIG_B2_OFDMA_INFO_0_STA_CODING_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_0_STA_CODING_LSB 20 +#define HE_SIG_B2_OFDMA_INFO_0_STA_CODING_MASK 0x00100000 + +/* Description HE_SIG_B2_OFDMA_INFO_0_RESERVED_0 + + +*/ +#define HE_SIG_B2_OFDMA_INFO_0_RESERVED_0_OFFSET 0x00000000 +#define HE_SIG_B2_OFDMA_INFO_0_RESERVED_0_LSB 21 +#define HE_SIG_B2_OFDMA_INFO_0_RESERVED_0_MASK 0xffe00000 + + +#endif // _HE_SIG_B2_OFDMA_INFO_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/ht_sig_info.h b/drivers/staging/fw-api/hw/qca6750/v1/ht_sig_info.h new file mode 100644 index 000000000000..84c88df1e306 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/ht_sig_info.h @@ -0,0 +1,395 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _HT_SIG_INFO_H_ +#define _HT_SIG_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 mcs[6:0], cbw[7], length[23:8], reserved_0[31:24] +// 1 smoothing[0], not_sounding[1], ht_reserved[2], aggregation[3], stbc[5:4], fec_coding[6], short_gi[7], num_ext_sp_str[9:8], crc[17:10], signal_tail[23:18], reserved_1[31:24] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_HT_SIG_INFO 2 + +struct ht_sig_info { + uint32_t mcs : 7, //[6:0] + cbw : 1, //[7] + length : 16, //[23:8] + reserved_0 : 8; //[31:24] + uint32_t smoothing : 1, //[0] + not_sounding : 1, //[1] + ht_reserved : 1, //[2] + aggregation : 1, //[3] + stbc : 2, //[5:4] + fec_coding : 1, //[6] + short_gi : 1, //[7] + num_ext_sp_str : 2, //[9:8] + crc : 8, //[17:10] + signal_tail : 6, //[23:18] + reserved_1 : 8; //[31:24] +}; + +/* + +mcs + + Modulation Coding Scheme: + + 0-7 are used for single stream + + 8-15 are used for 2 streams + + 16-23 are used for 3 streams + + 24-31 are used for 4 streams + + 32 is used for duplicate HT20 (unsupported) + + 33-76 is used for unequal modulation (unsupported) + + 77-127 is reserved. + + + +cbw + + Packet bandwidth: + + + + + + + +length + + This is the MPDU or A-MPDU length in octets of the PPDU + + + +reserved_0 + + This field is not part of HT-SIG + + Reserved: Should be set to 0 by the MAC and ignored by + the PHY + +smoothing + + Field indicates if smoothing is needed + + E_num 0 do_smoothing Unsupported setting: indicates + smoothing is often used for beamforming + + + + +not_sounding + + E_num 0 sounding Unsupported setting: indicates + sounding is used + + Indicates no sounding is used + + + +ht_reserved + + Reserved: Should be set to 1 by the MAC and ignored by + the PHY + + + +aggregation + + Indicates MPDU format + + Indicates A-MPDU format + + + +stbc + + Indicates no STBC + + Indicates 1 stream STBC + + E_num 2 2_str_stbc Indicates 2 stream STBC + (Unsupported) + + + +fec_coding + + Indicates BCC coding + + Indicates LDPC coding + + + +short_gi + + Indicates normal guard + interval + + + + +num_ext_sp_str + + Number of extension spatial streams: (Used for TxBF) + + No extension spatial streams + + E_num 1 1_ext_sp_str Not supported: 1 extension + spatial streams + + E_num 2 2_ext_sp_str Not supported: 2 extension + spatial streams + + + +crc + + The CRC protects the HT-SIG (HT-SIG[0][23:0] and + HT-SIG[1][9:0]. The generator polynomial is G(D) = D8 + D2 + + D + 1. + +signal_tail + + The 6 bits of tail is always set to 0 is used to flush + the BCC encoder and decoder. + +reserved_1 + + This field is not part of HT-SIG: + + Reserved: Should be set to 0 by the MAC and ignored by + the PHY. +*/ + + +/* Description HT_SIG_INFO_0_MCS + + Modulation Coding Scheme: + + 0-7 are used for single stream + + 8-15 are used for 2 streams + + 16-23 are used for 3 streams + + 24-31 are used for 4 streams + + 32 is used for duplicate HT20 (unsupported) + + 33-76 is used for unequal modulation (unsupported) + + 77-127 is reserved. + + +*/ +#define HT_SIG_INFO_0_MCS_OFFSET 0x00000000 +#define HT_SIG_INFO_0_MCS_LSB 0 +#define HT_SIG_INFO_0_MCS_MASK 0x0000007f + +/* Description HT_SIG_INFO_0_CBW + + Packet bandwidth: + + + + + + +*/ +#define HT_SIG_INFO_0_CBW_OFFSET 0x00000000 +#define HT_SIG_INFO_0_CBW_LSB 7 +#define HT_SIG_INFO_0_CBW_MASK 0x00000080 + +/* Description HT_SIG_INFO_0_LENGTH + + This is the MPDU or A-MPDU length in octets of the PPDU + + +*/ +#define HT_SIG_INFO_0_LENGTH_OFFSET 0x00000000 +#define HT_SIG_INFO_0_LENGTH_LSB 8 +#define HT_SIG_INFO_0_LENGTH_MASK 0x00ffff00 + +/* Description HT_SIG_INFO_0_RESERVED_0 + + This field is not part of HT-SIG + + Reserved: Should be set to 0 by the MAC and ignored by + the PHY +*/ +#define HT_SIG_INFO_0_RESERVED_0_OFFSET 0x00000000 +#define HT_SIG_INFO_0_RESERVED_0_LSB 24 +#define HT_SIG_INFO_0_RESERVED_0_MASK 0xff000000 + +/* Description HT_SIG_INFO_1_SMOOTHING + + Field indicates if smoothing is needed + + E_num 0 do_smoothing Unsupported setting: indicates + smoothing is often used for beamforming + + + +*/ +#define HT_SIG_INFO_1_SMOOTHING_OFFSET 0x00000004 +#define HT_SIG_INFO_1_SMOOTHING_LSB 0 +#define HT_SIG_INFO_1_SMOOTHING_MASK 0x00000001 + +/* Description HT_SIG_INFO_1_NOT_SOUNDING + + E_num 0 sounding Unsupported setting: indicates + sounding is used + + Indicates no sounding is used + + +*/ +#define HT_SIG_INFO_1_NOT_SOUNDING_OFFSET 0x00000004 +#define HT_SIG_INFO_1_NOT_SOUNDING_LSB 1 +#define HT_SIG_INFO_1_NOT_SOUNDING_MASK 0x00000002 + +/* Description HT_SIG_INFO_1_HT_RESERVED + + Reserved: Should be set to 1 by the MAC and ignored by + the PHY + + +*/ +#define HT_SIG_INFO_1_HT_RESERVED_OFFSET 0x00000004 +#define HT_SIG_INFO_1_HT_RESERVED_LSB 2 +#define HT_SIG_INFO_1_HT_RESERVED_MASK 0x00000004 + +/* Description HT_SIG_INFO_1_AGGREGATION + + Indicates MPDU format + + Indicates A-MPDU format + + +*/ +#define HT_SIG_INFO_1_AGGREGATION_OFFSET 0x00000004 +#define HT_SIG_INFO_1_AGGREGATION_LSB 3 +#define HT_SIG_INFO_1_AGGREGATION_MASK 0x00000008 + +/* Description HT_SIG_INFO_1_STBC + + Indicates no STBC + + Indicates 1 stream STBC + + E_num 2 2_str_stbc Indicates 2 stream STBC + (Unsupported) + + +*/ +#define HT_SIG_INFO_1_STBC_OFFSET 0x00000004 +#define HT_SIG_INFO_1_STBC_LSB 4 +#define HT_SIG_INFO_1_STBC_MASK 0x00000030 + +/* Description HT_SIG_INFO_1_FEC_CODING + + Indicates BCC coding + + Indicates LDPC coding + + +*/ +#define HT_SIG_INFO_1_FEC_CODING_OFFSET 0x00000004 +#define HT_SIG_INFO_1_FEC_CODING_LSB 6 +#define HT_SIG_INFO_1_FEC_CODING_MASK 0x00000040 + +/* Description HT_SIG_INFO_1_SHORT_GI + + Indicates normal guard + interval + + + +*/ +#define HT_SIG_INFO_1_SHORT_GI_OFFSET 0x00000004 +#define HT_SIG_INFO_1_SHORT_GI_LSB 7 +#define HT_SIG_INFO_1_SHORT_GI_MASK 0x00000080 + +/* Description HT_SIG_INFO_1_NUM_EXT_SP_STR + + Number of extension spatial streams: (Used for TxBF) + + No extension spatial streams + + E_num 1 1_ext_sp_str Not supported: 1 extension + spatial streams + + E_num 2 2_ext_sp_str Not supported: 2 extension + spatial streams + + +*/ +#define HT_SIG_INFO_1_NUM_EXT_SP_STR_OFFSET 0x00000004 +#define HT_SIG_INFO_1_NUM_EXT_SP_STR_LSB 8 +#define HT_SIG_INFO_1_NUM_EXT_SP_STR_MASK 0x00000300 + +/* Description HT_SIG_INFO_1_CRC + + The CRC protects the HT-SIG (HT-SIG[0][23:0] and + HT-SIG[1][9:0]. The generator polynomial is G(D) = D8 + D2 + + D + 1. +*/ +#define HT_SIG_INFO_1_CRC_OFFSET 0x00000004 +#define HT_SIG_INFO_1_CRC_LSB 10 +#define HT_SIG_INFO_1_CRC_MASK 0x0003fc00 + +/* Description HT_SIG_INFO_1_SIGNAL_TAIL + + The 6 bits of tail is always set to 0 is used to flush + the BCC encoder and decoder. +*/ +#define HT_SIG_INFO_1_SIGNAL_TAIL_OFFSET 0x00000004 +#define HT_SIG_INFO_1_SIGNAL_TAIL_LSB 18 +#define HT_SIG_INFO_1_SIGNAL_TAIL_MASK 0x00fc0000 + +/* Description HT_SIG_INFO_1_RESERVED_1 + + This field is not part of HT-SIG: + + Reserved: Should be set to 0 by the MAC and ignored by + the PHY. +*/ +#define HT_SIG_INFO_1_RESERVED_1_OFFSET 0x00000004 +#define HT_SIG_INFO_1_RESERVED_1_LSB 24 +#define HT_SIG_INFO_1_RESERVED_1_MASK 0xff000000 + + +#endif // _HT_SIG_INFO_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/hwio.h b/drivers/staging/fw-api/hw/qca6750/v1/hwio.h new file mode 100644 index 000000000000..56cfc7e572b2 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/hwio.h @@ -0,0 +1,2555 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef __HWIO_H__ +#define __HWIO_H__ +/* +=========================================================================== +*/ +/** + @file hwio.h + @brief Auto-generated HWIO interface include file. + + Reference chip release: + WCN6750 (Moselle) [MOSELLE_TOP_P3R9_20200202] + + This file contains HWIO register definitions for the following modules: + HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG + HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG + HOST_SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG + HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG + HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG + + + Generation parameters: + { 'filename': 'hwio.h', + 'module-filter-exclude': {}, + 'module-filter-include': {}, + 'modules': [ 'HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG', + 'HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG', + 'HOST_SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG', + 'HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG', + 'HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG']} +*/ +/* + =========================================================================== + + $Header: $ + $DateTime: $ + $Author: $ + + =========================================================================== +*/ + +/*---------------------------------------------------------------------------- + * MODULE: HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG + *--------------------------------------------------------------------------*/ + +#define HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE (HOST_SOC_WFSS_CE_REG_BASE + 0x00000000) +#define HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000 +#define HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE_USED 0x404 + +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000000) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ + in_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000004) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ + in_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000008) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN \ + in_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x0000000c) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN \ + in_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000010) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN \ + in_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x0000001c) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN \ + in_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000020) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN \ + in_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000030) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN \ + in_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000034) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN \ + in_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000038) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN \ + in_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x0000003c) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN \ + in_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000040) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN \ + in_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000044) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN \ + in_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000048) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN \ + in_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x0000004c) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN \ + in_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000050) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN \ + in_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000054) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN \ + in_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000058) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN \ + in_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x0000005c) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN \ + in_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000060) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN \ + in_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10 +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000400) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN \ + in_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR (HOST_SOC_CE_0_SRC_WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE + 0x00000404) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN \ + in_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN) +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_HOST_SOC_CE_0_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0 + +/*---------------------------------------------------------------------------- + * MODULE: HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG + *--------------------------------------------------------------------------*/ + +#define HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE (HOST_SOC_WFSS_CE_REG_BASE + 0x00001000) +#define HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000 +#define HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE_USED 0x40c + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000000) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000004) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000008) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x0000000c) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000010) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x0000001c) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000020) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000030) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000034) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000038) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x0000003c) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000040) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000044) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000048) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x0000004c) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000050) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000054) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000058) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x0000005c) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000060) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000064) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000068) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x0000006c) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000070) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x0000007c) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000080) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000084) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x000000a0) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x000000a4) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x000000a8) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x000000ac) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x000000b0) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x000000b4) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x000000b8) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000400) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000404) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x00000408) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR (HOST_SOC_CE_0_DST_WFSS_CE_0_CHANNEL_DST_REG_REG_BASE + 0x0000040c) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN \ + in_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN) +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 + +/*---------------------------------------------------------------------------- + * MODULE: HOST_SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG + *--------------------------------------------------------------------------*/ + +#define HOST_SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE (HOST_SOC_WFSS_CE_REG_BASE + 0x00002000) +#define HOST_SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_SIZE 0x1000 +#define HOST_SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE_USED 0x404 + +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR (HOST_SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000000) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN \ + in_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR, m) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,v) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR,m,v,HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_IN) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR (HOST_SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000004) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN \ + in_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR, m) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,v) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_ADDR,m,v,HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_IN) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR (HOST_SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000008) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_RMSK 0xff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN \ + in_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR, m) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,v) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ADDR,m,v,HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_IN) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR (HOST_SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x0000000c) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_IN \ + in_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_ADDR, m) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR (HOST_SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000010) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RMSK 0x3fffff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN \ + in_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR, m) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,v) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_ADDR,m,v,HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_IN) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR (HOST_SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x0000001c) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN \ + in_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR, m) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,v) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_IN) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR (HOST_SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000020) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN \ + in_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR, m) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,v) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_IN) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR (HOST_SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000030) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN \ + in_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_IN) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR (HOST_SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000034) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN \ + in_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_IN) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR (HOST_SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000038) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_IN \ + in_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_ADDR, m) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR (HOST_SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x0000003c) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN \ + in_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_IN) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR (HOST_SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000040) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN \ + in_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_IN) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR (HOST_SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000044) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_IN \ + in_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR (HOST_SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000048) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN \ + in_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_IN) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR (HOST_SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x0000004c) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN \ + in_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_IN) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR (HOST_SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000050) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN \ + in_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR, m) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,v) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_ADDR,m,v,HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_IN) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR (HOST_SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000054) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN \ + in_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR (HOST_SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000058) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RMSK 0x1f +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN \ + in_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR, m) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,v) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_ADDR,m,v,HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_IN) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_BMSK 0x10 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_FLUSH_SHFT 0x4 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_BMSK 0x8 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_STAT_SHFT 0x3 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_BMSK 0x4 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_RNG_HALT_SHFT 0x2 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_BMSK 0x2 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_CE_PRIORITY_SHFT 0x1 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_BMSK 0x1 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_SRC_CTRL_SRC_RING_BYTE_SWAP_EN_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR (HOST_SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x0000005c) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_RMSK 0x1f +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN \ + in_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR, m) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,v) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_ADDR,m,v,HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_IN) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_BMSK 0x10 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_WDG_ERR_SHFT 0x4 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_BMSK 0x8 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_LEN_ZERO_ERR_SHFT 0x3 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_BMSK 0x4 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_BUF_RD_AXI_ERR_SHFT 0x2 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_BMSK 0x2 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_SRC_SW_INT_SHFT 0x1 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_BMSK 0x1 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_CH_SRC_IS_REG_ERR_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR (HOST_SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000060) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN \ + in_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR, m) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,v) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_ADDR,m,v,HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_IN) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_STATUS_SHFT 0x10 +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_BMSK 0xffff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R0_CE_WATCHDOG_LIMIT_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR (HOST_SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000400) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_RMSK 0xffff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN \ + in_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR, m) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,v) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR,m,v,HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_IN) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR (HOST_SOC_CE_1_SRC_WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE + 0x00000404) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_RMSK 0xffff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN \ + in_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR, m) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,v) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_ADDR,m,v,HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_IN) +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_HOST_SOC_CE_1_SRC_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_TP_TAIL_PTR_SHFT 0x0 + +/*---------------------------------------------------------------------------- + * MODULE: HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG + *--------------------------------------------------------------------------*/ + +#define HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE (HOST_SOC_WFSS_CE_REG_BASE + 0x00003000) +#define HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_SIZE 0x1000 +#define HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE_USED 0x40c + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000000) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,v) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR,m,v,HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_IN) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000004) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,v) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_ADDR,m,v,HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_IN) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000008) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_RMSK 0xff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,v) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ADDR,m,v,HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_IN) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x0000000c) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000010) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RMSK 0x3fffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,v) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_ADDR,m,v,HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_IN) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x0000001c) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,v) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_ADDR,m,v,HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_IN) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000020) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_RMSK 0xff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,v) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_ADDR,m,v,HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_IN) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000030) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,v) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_ADDR,m,v,HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_IN) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000034) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_RMSK 0xffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,v) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_ADDR,m,v,HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_IN) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0xffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000038) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x0000003c) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x3ff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,v) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_ADDR,m,v,HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_IN) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x3ff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000040) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x7 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,v) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_ADDR,m,v,HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_IN) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x7 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000044) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_RMSK 0xffffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0xff0000 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0xffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000048) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_IN) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x0000004c) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_IN) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000050) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,v) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_ADDR,m,v,HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_IN) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000054) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000058) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,v) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR,m,v,HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_IN) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x0000005c) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RMSK 0xffffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,v) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_ADDR,m,v,HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_IN) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0xffff00 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0xff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000060) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RMSK 0xffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,v) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ADDR,m,v,HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_IN) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_BMSK 0xff00 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_RING_ID_SHFT 0x8 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_BMSK 0xff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000064) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0xffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000068) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RMSK 0x3ffffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,v) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_ADDR,m,v,HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_IN) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_BMSK 0x3c00000 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x3fc000 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x3000 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0xf00 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x80 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x40 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x20 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x10 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x8 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x4 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x2 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x1 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x0000006c) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,v) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_ADDR,m,v,HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_IN) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000070) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_RMSK 0xff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,v) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_ADDR,m,v,HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_IN) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0xff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x0000007c) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,v) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_ADDR,m,v,HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_IN) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x8000 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x7fff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000080) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x8000 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x7fff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000084) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x3ff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,v) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR,m,v,HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_IN) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x3ff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x000000a0) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,v) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR,m,v,HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_IN) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x000000a4) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_RMSK 0x1ff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,v) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR,m,v,HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_IN) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x100 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0xff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x000000a8) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,v) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_ADDR,m,v,HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_IN) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x000000ac) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0xffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,v) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_ADDR,m,v,HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_IN) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0xffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x000000b0) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_RMSK 0x1ffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,v) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR,m,v,HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_IN) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_BMSK 0x10000 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DST_RING_BYTE_SWAP_EN_SHFT 0x10 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK 0xffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x000000b4) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_RMSK 0x3f +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,v) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_ADDR,m,v,HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_IN) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_BMSK 0x20 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_WDG_ERR_SHFT 0x5 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_BMSK 0x10 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_MAX_LEN_ERR_SHFT 0x4 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_BMSK 0x8 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_BUF_WR_AXI_ERR_SHFT 0x3 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_BMSK 0x4 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_STS_SW_INT_SHFT 0x2 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_BMSK 0x2 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_DST_SW_INT_SHFT 0x1 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_BMSK 0x1 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DST_IS_REG_ERR_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x000000b8) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RMSK 0xf +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,v) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_ADDR,m,v,HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_IN) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_BMSK 0x8 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_STAT_FLUSH_SHFT 0x3 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_BMSK 0x4 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_DST_FLUSH_SHFT 0x2 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_BMSK 0x2 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_STAT_SHFT 0x1 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_BMSK 0x1 +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R0_CE_CH_DEST_CTRL2_RNG_HALT_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000400) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_RMSK 0xffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,v) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR,m,v,HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_IN) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000404) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_RMSK 0xffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,v) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_ADDR,m,v,HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_IN) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_DEST_RING_TP_TAIL_PTR_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x00000408) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_RMSK 0xffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,v) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR,m,v,HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_IN) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_BMSK 0xffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR (HOST_SOC_CE_1_DST_WFSS_CE_1_CHANNEL_DST_REG_REG_BASE + 0x0000040c) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_RMSK 0xffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN \ + in_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR, m) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,v) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_ADDR,m,v,HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_IN) +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_BMSK 0xffff +#define HWIO_HOST_SOC_CE_1_DST_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 + +/*---------------------------------------------------------------------------- + * MODULE: HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG + *--------------------------------------------------------------------------*/ + +#define HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE (HOST_SOC_WFSS_CE_REG_BASE + 0x00018000) +#define HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_SIZE 0x1000 +#define HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE_USED 0x418 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000000) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_VALUE_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_LOWER_VALUE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000004) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_RMSK 0xff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_VALUE_BMSK 0xff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TESTBUS_UPPER_VALUE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000008) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_RMSK 0xfff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0xe00 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x1f0 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 0x4 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0xf +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x0000000c) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_RMSK 0x1 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR,v) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_ADDR,m,v,HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_IN) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000010) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RMSK 0x80000fff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR,v) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_ADDR,m,v,HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_IN) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_SPARE_BMSK 0x800 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_SPARE_SHFT 0xb +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WDOG_CTR_BMSK 0x400 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WDOG_CTR_SHFT 0xa +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_FIFO_BMSK 0x200 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_FIFO_SHFT 0x9 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_FIFO_BMSK 0x100 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_FIFO_SHFT 0x8 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_BMSK 0x80 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_SHFT 0x7 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_AXI_MAS_BMSK 0x40 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_AXI_MAS_SHFT 0x6 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_BMSK 0x20 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_SHFT 0x5 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_BMSK 0x10 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_SHFT 0x4 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_CMD_BMSK 0x8 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_DATA_CMD_SHFT 0x3 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_CMD_BMSK 0x4 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_WR_ADDR_CMD_SHFT 0x2 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_CMD_BMSK 0x2 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_RD_CMD_SHFT 0x1 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CORE_BMSK 0x1 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLOCK_GATE_DISABLE_CORE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000014) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_RMSK 0x1010101 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x1000000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x10000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 0x10 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x100 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 0x8 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x1 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000018) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_RMSK 0x3f3f3f +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x3f0000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x3f00 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 0x8 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x3f +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x0000001c) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR,v) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_ADDR,m,v,HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_IN) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0xff0000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 0x10 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x3f00 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 0x8 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x3f +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000020) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR,v) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_ADDR,m,v,HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_IN) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0xff0000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 0x10 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x3f00 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 0x8 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x3f +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000024) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_RMSK 0xfffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR,v) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_ADDR,m,v,HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_IN) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_BMSK 0x8000000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_SHFT 0x1b +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_BMSK 0x4000000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_SHFT 0x1a +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_BMSK 0x2000000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_SHFT 0x19 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_BMSK 0x1000000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_SHFT 0x18 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_BMSK 0x800000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_SHFT 0x17 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x700000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0xe0000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 0x11 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x1fe00 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 0x9 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x1fe +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 0x1 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x1 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000028) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_RMSK 0xffff0001 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR,v) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_ADDR,m,v,HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_IN) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x1 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x0000002c) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_RMSK 0xffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0xffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000030) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0xffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000034) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_RMSK 0xfffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR,v) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_ADDR,m,v,HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_IN) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0xe0000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x10000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0xffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000038) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_RMSK 0xfffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR,v) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_ADDR,m,v,HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_IN) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0xe0000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x10000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0xffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x0000003c) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR,v) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR,m,v,HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_IN) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000040) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR,v) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR,m,v,HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_IN) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000044) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR,v) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR,m,v,HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_IN) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000048) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR,v) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR,m,v,HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_IN) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x0000004c) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_RMSK 0x1ffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR,v) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_ADDR,m,v,HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_IN) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_MISC_IE_BMSK 0x1000000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_MISC_IE_SHFT 0x18 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_BMSK 0xfff000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_DST_RING_IE_SHFT 0xc +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_BMSK 0xfff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_0_SRC_RING_IE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000050) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_RMSK 0xfff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR,v) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_ADDR,m,v,HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_IN) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_BMSK 0xfff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_HOST_IE_1_STS_RING_IE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000054) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_RMSK 0xffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR,v) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_ADDR,m,v,HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_IN) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_DEST_BMSK 0xfff000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_DEST_SHFT 0xc +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_SRC_BMSK 0xfff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_SECURITY_SRC_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000058) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_RMSK 0x1ffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR,v) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_ADDR,m,v,HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_IN) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_MISC_IE_BMSK 0x1000000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_MISC_IE_SHFT 0x18 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_DST_RING_IE_BMSK 0xfff000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_DST_RING_IE_SHFT 0xc +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SRC_RING_IE_BMSK 0xfff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_0_SRC_RING_IE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x0000005c) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_RMSK 0xfff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR,v) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_ADDR,m,v,HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_IN) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_BMSK 0xfff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TARGET_IE_1_STS_RING_IE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000060) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR,v) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_ADDR,m,v,HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_IN) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_0_SEED_0_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000064) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR,v) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_ADDR,m,v,HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_IN) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_1_SEED_1_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000068) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_RMSK 0x1 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR,v) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_ADDR,m,v,HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_IN) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_SEED_2_BMSK 0x1 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_LFSR_SEED_2_SEED_2_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x0000006c) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR,v) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_ADDR,m,v,HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_IN) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POLY_0_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_0_POLY_0_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000070) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR,v) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_ADDR,m,v,HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_IN) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POLY_1_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_1_POLY_1_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000074) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_RMSK 0x1 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR,v) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_ADDR,m,v,HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_IN) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_POLY_2_BMSK 0x1 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_TOEPLITZ_POLY_2_POLY_2_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000078) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_0_VALUE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x0000007c) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_1_VALUE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000080) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_2_VALUE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000084) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_DEBUG_DMA_3_VALUE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000088) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_RMSK 0xfffdffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR,v) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_ADDR,m,v,HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IN) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CLK_EXTEND_BMSK 0x80000000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CLK_EXTEND_SHFT 0x1f +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_WRAPPER_REG_CLK_BMSK 0x40000000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_WRAPPER_REG_CLK_SHFT 0x1e +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_REG_CLK_BMSK 0x3ffc0000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_REG_CLK_SHFT 0x12 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IC_CLK_BMSK 0x10000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_IC_CLK_SHFT 0x10 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_DMA_CLK_BMSK 0xf000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_DMA_CLK_SHFT 0xc +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_CORE_CLK_BMSK 0xfff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_0_CSM_CORE_CLK_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x0000008c) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_RMSK 0xffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR,v) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_ADDR,m,v,HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_IN) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_DST_SRNG_CLK_BMSK 0xfff000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_DST_SRNG_CLK_SHFT 0xc +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_SRC_SRNG_CLK_BMSK 0xfff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_1_SRC_SRNG_CLK_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000090) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_RMSK 0x1fff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR,v) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_ADDR,m,v,HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_IN) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_TZ_CLK_BMSK 0x1000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_TZ_CLK_SHFT 0xc +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_STS_SRNG_CLK_BMSK 0xfff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_CLK_GATE_DIS_2_STS_SRNG_CLK_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000094) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_RMSK 0xfff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR,v) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_ADDR,m,v,HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IN) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IDLE_CFG_BMSK 0xfff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_IDLE_CONFIG_IDLE_CFG_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000098) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_VALUE_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_INVALID_APB_ACC_ADDR_VALUE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x0000009c) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR,v) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_ADDR,m,v,HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_IN) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_VAL_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R0_CE_S_PARE_REGISTER_VAL_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000400) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_RMSK 0x100ff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR,v) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_ADDR,m,v,HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_IN) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK 0x10000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT 0x10 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_GXI_TESTBUS_SELECT_BMSK 0xff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_CTRL_GXI_TESTBUS_SELECT_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000404) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR,v) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_ADDR,m,v,HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_IN) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_MASK_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_0_MASK_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000408) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR,v) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_ADDR,m,v,HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_IN) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_MASK_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_EVENTMASK_IX_1_MASK_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x0000040c) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_VAL_BMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_LOW_VAL_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000410) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_RMSK 0xff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_VAL_BMSK 0xff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_TESTBUS_HIGH_VAL_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000414) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR,v) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR,m,v,HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_IN) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 0x11 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x1fffc +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 0x2 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x2 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 0x1 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x1 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0x0 + +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR (HOST_SOC_CE_COMMON_WFSS_CE_COMMON_REG_REG_BASE + 0x00000418) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_RMSK 0x1 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_IN \ + in_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_INM(m) \ + in_dword_masked(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR, m) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OUT(v) \ + out_dword(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR,v) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_OUTM(m,v) \ + out_dword_masked_ns(HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_ADDR,m,v,HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_IN) +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x1 +#define HWIO_HOST_SOC_CE_COMMON_WFSS_CE_COMMON_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 + + +#endif /* __HWIO_H__ */ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/l_sig_a_info.h b/drivers/staging/fw-api/hw/qca6750/v1/l_sig_a_info.h new file mode 100644 index 000000000000..9540d85731ba --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/l_sig_a_info.h @@ -0,0 +1,283 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _L_SIG_A_INFO_H_ +#define _L_SIG_A_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 rate[3:0], lsig_reserved[4], length[16:5], parity[17], tail[23:18], pkt_type[27:24], captured_implicit_sounding[28], reserved[31:29] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_L_SIG_A_INFO 1 + +struct l_sig_a_info { + uint32_t rate : 4, //[3:0] + lsig_reserved : 1, //[4] + length : 12, //[16:5] + parity : 1, //[17] + tail : 6, //[23:18] + pkt_type : 4, //[27:24] + captured_implicit_sounding : 1, //[28] + reserved : 3; //[31:29] +}; + +/* + +rate + + This format is originally defined for OFDM as a 4 bit + field but the 5th bit was added to indicate 11b formatted + frames. In the standard bit [4] is specified as reserved. + For 11b frames this L-SIG is transformed in the PHY into the + 11b preamble format. The following are the rates: + + 64-QAM 2/3 (48 Mbps) + + 16-QAM 1/2 (24 Mbps) + + QPSK 1/2 (12 Mbps) + + BPSK 1/2 (6 Mbps) + + 64-QAM 3/4 (54 Mbps) + + 16-QAM 3/4 (36 Mbps) + + QPSK 1/2 (18 Mbps) + + BPSK 3/4 (9 Mbps) + + + +lsig_reserved + + Reserved: Should be set to 0 by the MAC and ignored by + the PHY + + + +length + + The length indicates the number of octets in this MPDU. + Note that when using mixed mode 11n preamble this length + provides the spoofed length for the PPDU. This length + provides part of the information to derive the actually PPDU + length. For legacy OFDM and 11B frames the maximum length + is + + + +parity + + 11a/n/ac TX: This field provides even parity over the + first 18 bits of the signal field which means that the sum + of 1s in the signal field will always be even on + + 11a/n/ac RX: this field contains the received parity + field from the L-SIG symbol for the current packet. + + + +tail + + The 6 bits of tail is always set to 0 is used to flush + the BCC encoder and decoder. + +pkt_type + + Only used on the RX side. + + Note: This is not really part of L-SIG + + + + Packet type: + + 802.11a PPDU type + + 802.11b PPDU type + + 802.11n Mixed Mode PPDU type + + 802.11ac PPDU type + + 802.11ax PPDU type + + 802.11ba (WUR) PPDU type + +captured_implicit_sounding + + Only used on the RX side. + + Note: This is not really part of L-SIG + + + + This indicates that the PHY has captured implicit + sounding. + +reserved + + Reserved: Should be set to 0 by the transmitting MAC and + ignored by the PHY +*/ + + +/* Description L_SIG_A_INFO_0_RATE + + This format is originally defined for OFDM as a 4 bit + field but the 5th bit was added to indicate 11b formatted + frames. In the standard bit [4] is specified as reserved. + For 11b frames this L-SIG is transformed in the PHY into the + 11b preamble format. The following are the rates: + + 64-QAM 2/3 (48 Mbps) + + 16-QAM 1/2 (24 Mbps) + + QPSK 1/2 (12 Mbps) + + BPSK 1/2 (6 Mbps) + + 64-QAM 3/4 (54 Mbps) + + 16-QAM 3/4 (36 Mbps) + + QPSK 1/2 (18 Mbps) + + BPSK 3/4 (9 Mbps) + + +*/ +#define L_SIG_A_INFO_0_RATE_OFFSET 0x00000000 +#define L_SIG_A_INFO_0_RATE_LSB 0 +#define L_SIG_A_INFO_0_RATE_MASK 0x0000000f + +/* Description L_SIG_A_INFO_0_LSIG_RESERVED + + Reserved: Should be set to 0 by the MAC and ignored by + the PHY + + +*/ +#define L_SIG_A_INFO_0_LSIG_RESERVED_OFFSET 0x00000000 +#define L_SIG_A_INFO_0_LSIG_RESERVED_LSB 4 +#define L_SIG_A_INFO_0_LSIG_RESERVED_MASK 0x00000010 + +/* Description L_SIG_A_INFO_0_LENGTH + + The length indicates the number of octets in this MPDU. + Note that when using mixed mode 11n preamble this length + provides the spoofed length for the PPDU. This length + provides part of the information to derive the actually PPDU + length. For legacy OFDM and 11B frames the maximum length + is + + +*/ +#define L_SIG_A_INFO_0_LENGTH_OFFSET 0x00000000 +#define L_SIG_A_INFO_0_LENGTH_LSB 5 +#define L_SIG_A_INFO_0_LENGTH_MASK 0x0001ffe0 + +/* Description L_SIG_A_INFO_0_PARITY + + 11a/n/ac TX: This field provides even parity over the + first 18 bits of the signal field which means that the sum + of 1s in the signal field will always be even on + + 11a/n/ac RX: this field contains the received parity + field from the L-SIG symbol for the current packet. + + +*/ +#define L_SIG_A_INFO_0_PARITY_OFFSET 0x00000000 +#define L_SIG_A_INFO_0_PARITY_LSB 17 +#define L_SIG_A_INFO_0_PARITY_MASK 0x00020000 + +/* Description L_SIG_A_INFO_0_TAIL + + The 6 bits of tail is always set to 0 is used to flush + the BCC encoder and decoder. +*/ +#define L_SIG_A_INFO_0_TAIL_OFFSET 0x00000000 +#define L_SIG_A_INFO_0_TAIL_LSB 18 +#define L_SIG_A_INFO_0_TAIL_MASK 0x00fc0000 + +/* Description L_SIG_A_INFO_0_PKT_TYPE + + Only used on the RX side. + + Note: This is not really part of L-SIG + + + + Packet type: + + 802.11a PPDU type + + 802.11b PPDU type + + 802.11n Mixed Mode PPDU type + + 802.11ac PPDU type + + 802.11ax PPDU type + + 802.11ba (WUR) PPDU type +*/ +#define L_SIG_A_INFO_0_PKT_TYPE_OFFSET 0x00000000 +#define L_SIG_A_INFO_0_PKT_TYPE_LSB 24 +#define L_SIG_A_INFO_0_PKT_TYPE_MASK 0x0f000000 + +/* Description L_SIG_A_INFO_0_CAPTURED_IMPLICIT_SOUNDING + + Only used on the RX side. + + Note: This is not really part of L-SIG + + + + This indicates that the PHY has captured implicit + sounding. +*/ +#define L_SIG_A_INFO_0_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000 +#define L_SIG_A_INFO_0_CAPTURED_IMPLICIT_SOUNDING_LSB 28 +#define L_SIG_A_INFO_0_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000 + +/* Description L_SIG_A_INFO_0_RESERVED + + Reserved: Should be set to 0 by the transmitting MAC and + ignored by the PHY +*/ +#define L_SIG_A_INFO_0_RESERVED_OFFSET 0x00000000 +#define L_SIG_A_INFO_0_RESERVED_LSB 29 +#define L_SIG_A_INFO_0_RESERVED_MASK 0xe0000000 + + +#endif // _L_SIG_A_INFO_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/l_sig_b_info.h b/drivers/staging/fw-api/hw/qca6750/v1/l_sig_b_info.h new file mode 100644 index 000000000000..8c1f8d2e52c9 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/l_sig_b_info.h @@ -0,0 +1,120 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _L_SIG_B_INFO_H_ +#define _L_SIG_B_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 rate[3:0], length[15:4], reserved[31:16] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_L_SIG_B_INFO 1 + +struct l_sig_b_info { + uint32_t rate : 4, //[3:0] + length : 12, //[15:4] + reserved : 16; //[31:16] +}; + +/* + +rate + + DSSS 1 Mbps long + + DSSS 2 Mbps long + + CCK 5.5 Mbps long + + CCK 11 Mbps long + + DSSS 2 Mbps short + + CCK 5.5 Mbps short + + CCK 11 Mbps short + + + +length + + The length indicates the number of octets in this MPDU. + + + +reserved + + Reserved: Should be set to 0 by the transmitting MAC and + ignored by the PHY +*/ + + +/* Description L_SIG_B_INFO_0_RATE + + DSSS 1 Mbps long + + DSSS 2 Mbps long + + CCK 5.5 Mbps long + + CCK 11 Mbps long + + DSSS 2 Mbps short + + CCK 5.5 Mbps short + + CCK 11 Mbps short + + +*/ +#define L_SIG_B_INFO_0_RATE_OFFSET 0x00000000 +#define L_SIG_B_INFO_0_RATE_LSB 0 +#define L_SIG_B_INFO_0_RATE_MASK 0x0000000f + +/* Description L_SIG_B_INFO_0_LENGTH + + The length indicates the number of octets in this MPDU. + + +*/ +#define L_SIG_B_INFO_0_LENGTH_OFFSET 0x00000000 +#define L_SIG_B_INFO_0_LENGTH_LSB 4 +#define L_SIG_B_INFO_0_LENGTH_MASK 0x0000fff0 + +/* Description L_SIG_B_INFO_0_RESERVED + + Reserved: Should be set to 0 by the transmitting MAC and + ignored by the PHY +*/ +#define L_SIG_B_INFO_0_RESERVED_OFFSET 0x00000000 +#define L_SIG_B_INFO_0_RESERVED_LSB 16 +#define L_SIG_B_INFO_0_RESERVED_MASK 0xffff0000 + + +#endif // _L_SIG_B_INFO_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/lithium_top_reg.h b/drivers/staging/fw-api/hw/qca6750/v1/lithium_top_reg.h new file mode 100644 index 000000000000..f1ca3294736c --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/lithium_top_reg.h @@ -0,0 +1,415779 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +////////////////////////////////////////////////////////////////////////////// +// lithium_top_reg.h generated by: GenArmCHeader.pl +////////////////////////////////////////////////////////////////////////////// +// **** W A R N I N G **** THIS FILE IS AUTO GENERATED!! PLEASE DO NOT EDIT!! +////////////////////////////////////////////////////////////////////////////// +// +// RCS File : -USE CVS LOG- +// Revision : -USE CVS LOG- +// Last Check In : -USE CVS LOG- +////////////////////////////////////////////////////////////////////////////// +// Description : Constants related to Hardware Registers +// +// Byte Addresses are used for all BASES and ADDRESSES +////////////////////////////////////////////////////////////////////////////// +#ifndef LITHIUM_TOP_REG_H + +#define LITHIUM_TOP_REG_H + +enum QCSR_REG_TYPE {QCSR_REG_RO, QCSR_REG_WO, QCSR_REG_RW, QCSR_REG_COMMAND}; + + + +#define PHYA (0x00300000) + +#define PHYA_PCSS_PDMEM_PDMEM_L_n(n) (0x00300000+0x8*(n)) +#define PHYA_PCSS_PDMEM_PDMEM_L_n_nMIN 0 +#define PHYA_PCSS_PDMEM_PDMEM_L_n_nMAX 0 +#define PHYA_PCSS_PDMEM_PDMEM_L_n_ELEM 1 +#define PHYA_PCSS_PDMEM_PDMEM_L_n___RWC QCSR_REG_RW +#define PHYA_PCSS_PDMEM_PDMEM_L_n___POR 0x00000000 +#define PHYA_PCSS_PDMEM_PDMEM_L_n__PDMEM_LOW___POR 0x00000000 +#define PHYA_PCSS_PDMEM_PDMEM_L_n__PDMEM_LOW___M 0xFFFFFFFF +#define PHYA_PCSS_PDMEM_PDMEM_L_n__PDMEM_LOW___S 0 +#define PHYA_PCSS_PDMEM_PDMEM_L_n___M 0xFFFFFFFF +#define PHYA_PCSS_PDMEM_PDMEM_L_n___S 0 +#define PHYA_PCSS_PDMEM_PDMEM_L_0 (0x00300000) +#define PHYA_PCSS_PDMEM_PDMEM_L_0___RWC QCSR_REG_RW +#define PHYA_PCSS_PDMEM_PDMEM_L_0__PDMEM_LOW___M 0xFFFFFFFF +#define PHYA_PCSS_PDMEM_PDMEM_L_0__PDMEM_LOW___S 0 + +#define PHYA_PCSS_PDMEM_PDMEM_U_n(n) (0x00300004+0x8*(n)) +#define PHYA_PCSS_PDMEM_PDMEM_U_n_nMIN 0 +#define PHYA_PCSS_PDMEM_PDMEM_U_n_nMAX 0 +#define PHYA_PCSS_PDMEM_PDMEM_U_n_ELEM 1 +#define PHYA_PCSS_PDMEM_PDMEM_U_n___RWC QCSR_REG_RW +#define PHYA_PCSS_PDMEM_PDMEM_U_n___POR 0x00000000 +#define PHYA_PCSS_PDMEM_PDMEM_U_n__PDMEM_HIGH___POR 0x00000000 +#define PHYA_PCSS_PDMEM_PDMEM_U_n__PDMEM_HIGH___M 0xFFFFFFFF +#define PHYA_PCSS_PDMEM_PDMEM_U_n__PDMEM_HIGH___S 0 +#define PHYA_PCSS_PDMEM_PDMEM_U_n___M 0xFFFFFFFF +#define PHYA_PCSS_PDMEM_PDMEM_U_n___S 0 +#define PHYA_PCSS_PDMEM_PDMEM_U_0 (0x00300004) +#define PHYA_PCSS_PDMEM_PDMEM_U_0___RWC QCSR_REG_RW +#define PHYA_PCSS_PDMEM_PDMEM_U_0__PDMEM_HIGH___M 0xFFFFFFFF +#define PHYA_PCSS_PDMEM_PDMEM_U_0__PDMEM_HIGH___S 0 + +#define PHYA_PCSS_GLOBAL_CONFIG_L (0x00380000) +#define PHYA_PCSS_GLOBAL_CONFIG_L___RWC QCSR_REG_RW +#define PHYA_PCSS_GLOBAL_CONFIG_L___POR 0x00000000 +#define PHYA_PCSS_GLOBAL_CONFIG_L__DIG_MIX_MODE_165___POR 0x0 +#define PHYA_PCSS_GLOBAL_CONFIG_L__DYN_PRI_CHN___POR 0x0 +#define PHYA_PCSS_GLOBAL_CONFIG_L__CF_RESET_NOC___POR 0x0 +#define PHYA_PCSS_GLOBAL_CONFIG_L__DISABLE_DYN_CLOCK_GATING___POR 0x0 +#define PHYA_PCSS_GLOBAL_CONFIG_L__EN_TURBO_MODE___POR 0x0 +#define PHYA_PCSS_GLOBAL_CONFIG_L__CF_ACTIVE___POR 0x0 +#define PHYA_PCSS_GLOBAL_CONFIG_L__ADC_BW___POR 0x0 +#define PHYA_PCSS_GLOBAL_CONFIG_L__DAC_BW___POR 0x0 +#define PHYA_PCSS_GLOBAL_CONFIG_L__EN_165___POR 0x0 +#define PHYA_PCSS_GLOBAL_CONFIG_L__EN_NONCONTIG___POR 0x0 +#define PHYA_PCSS_GLOBAL_CONFIG_L__DYN_BW___POR 0x0 +#define PHYA_PCSS_GLOBAL_CONFIG_L__QUARTER_RATE___POR 0x0 +#define PHYA_PCSS_GLOBAL_CONFIG_L__HALF_RATE___POR 0x0 +#define PHYA_PCSS_GLOBAL_CONFIG_L__DIG_MIX_MODE_165___M 0x00040000 +#define PHYA_PCSS_GLOBAL_CONFIG_L__DIG_MIX_MODE_165___S 18 +#define PHYA_PCSS_GLOBAL_CONFIG_L__DYN_PRI_CHN___M 0x00038000 +#define PHYA_PCSS_GLOBAL_CONFIG_L__DYN_PRI_CHN___S 15 +#define PHYA_PCSS_GLOBAL_CONFIG_L__CF_RESET_NOC___M 0x00004000 +#define PHYA_PCSS_GLOBAL_CONFIG_L__CF_RESET_NOC___S 14 +#define PHYA_PCSS_GLOBAL_CONFIG_L__DISABLE_DYN_CLOCK_GATING___M 0x00002000 +#define PHYA_PCSS_GLOBAL_CONFIG_L__DISABLE_DYN_CLOCK_GATING___S 13 +#define PHYA_PCSS_GLOBAL_CONFIG_L__EN_TURBO_MODE___M 0x00001000 +#define PHYA_PCSS_GLOBAL_CONFIG_L__EN_TURBO_MODE___S 12 +#define PHYA_PCSS_GLOBAL_CONFIG_L__CF_ACTIVE___M 0x00000800 +#define PHYA_PCSS_GLOBAL_CONFIG_L__CF_ACTIVE___S 11 +#define PHYA_PCSS_GLOBAL_CONFIG_L__ADC_BW___M 0x00000700 +#define PHYA_PCSS_GLOBAL_CONFIG_L__ADC_BW___S 8 +#define PHYA_PCSS_GLOBAL_CONFIG_L__DAC_BW___M 0x000000C0 +#define PHYA_PCSS_GLOBAL_CONFIG_L__DAC_BW___S 6 +#define PHYA_PCSS_GLOBAL_CONFIG_L__EN_165___M 0x00000020 +#define PHYA_PCSS_GLOBAL_CONFIG_L__EN_165___S 5 +#define PHYA_PCSS_GLOBAL_CONFIG_L__EN_NONCONTIG___M 0x00000010 +#define PHYA_PCSS_GLOBAL_CONFIG_L__EN_NONCONTIG___S 4 +#define PHYA_PCSS_GLOBAL_CONFIG_L__DYN_BW___M 0x0000000C +#define PHYA_PCSS_GLOBAL_CONFIG_L__DYN_BW___S 2 +#define PHYA_PCSS_GLOBAL_CONFIG_L__QUARTER_RATE___M 0x00000002 +#define PHYA_PCSS_GLOBAL_CONFIG_L__QUARTER_RATE___S 1 +#define PHYA_PCSS_GLOBAL_CONFIG_L__HALF_RATE___M 0x00000001 +#define PHYA_PCSS_GLOBAL_CONFIG_L__HALF_RATE___S 0 +#define PHYA_PCSS_GLOBAL_CONFIG_L___M 0x0007FFFF +#define PHYA_PCSS_GLOBAL_CONFIG_L___S 0 + +#define PHYA_PCSS_M3_STATUS_L (0x00380008) +#define PHYA_PCSS_M3_STATUS_L___RWC QCSR_REG_RO +#define PHYA_PCSS_M3_STATUS_L___POR 0x00000000 +#define PHYA_PCSS_M3_STATUS_L__M3_STS___POR 0x0 +#define PHYA_PCSS_M3_STATUS_L__M3_STS___M 0x00000007 +#define PHYA_PCSS_M3_STATUS_L__M3_STS___S 0 +#define PHYA_PCSS_M3_STATUS_L___M 0x00000007 +#define PHYA_PCSS_M3_STATUS_L___S 0 + +#define PHYA_PCSS_M3_CTRL_L (0x00380010) +#define PHYA_PCSS_M3_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PCSS_M3_CTRL_L___POR 0x00000000 +#define PHYA_PCSS_M3_CTRL_L__WD_TIMER_CLK_EN___POR 0x0 +#define PHYA_PCSS_M3_CTRL_L__M3_640_EN___POR 0x0 +#define PHYA_PCSS_M3_CTRL_L__DBG_CLK_EN___POR 0x0 +#define PHYA_PCSS_M3_CTRL_L__DAP_DISABLE___POR 0x0 +#define PHYA_PCSS_M3_CTRL_L__CROSS_TRIG_DISABLE___POR 0x0 +#define PHYA_PCSS_M3_CTRL_L__ITM_DISABLE___POR 0x0 +#define PHYA_PCSS_M3_CTRL_L__ETM_DISABLE___POR 0x0 +#define PHYA_PCSS_M3_CTRL_L__M3_ENABLE___POR 0x0 +#define PHYA_PCSS_M3_CTRL_L__PCSS_ENABLE___POR 0x0 +#define PHYA_PCSS_M3_CTRL_L__WD_TIMER_CLK_EN___M 0x00000100 +#define PHYA_PCSS_M3_CTRL_L__WD_TIMER_CLK_EN___S 8 +#define PHYA_PCSS_M3_CTRL_L__M3_640_EN___M 0x00000080 +#define PHYA_PCSS_M3_CTRL_L__M3_640_EN___S 7 +#define PHYA_PCSS_M3_CTRL_L__DBG_CLK_EN___M 0x00000040 +#define PHYA_PCSS_M3_CTRL_L__DBG_CLK_EN___S 6 +#define PHYA_PCSS_M3_CTRL_L__DAP_DISABLE___M 0x00000020 +#define PHYA_PCSS_M3_CTRL_L__DAP_DISABLE___S 5 +#define PHYA_PCSS_M3_CTRL_L__CROSS_TRIG_DISABLE___M 0x00000010 +#define PHYA_PCSS_M3_CTRL_L__CROSS_TRIG_DISABLE___S 4 +#define PHYA_PCSS_M3_CTRL_L__ITM_DISABLE___M 0x00000008 +#define PHYA_PCSS_M3_CTRL_L__ITM_DISABLE___S 3 +#define PHYA_PCSS_M3_CTRL_L__ETM_DISABLE___M 0x00000004 +#define PHYA_PCSS_M3_CTRL_L__ETM_DISABLE___S 2 +#define PHYA_PCSS_M3_CTRL_L__M3_ENABLE___M 0x00000002 +#define PHYA_PCSS_M3_CTRL_L__M3_ENABLE___S 1 +#define PHYA_PCSS_M3_CTRL_L__PCSS_ENABLE___M 0x00000001 +#define PHYA_PCSS_M3_CTRL_L__PCSS_ENABLE___S 0 +#define PHYA_PCSS_M3_CTRL_L___M 0x000001FF +#define PHYA_PCSS_M3_CTRL_L___S 0 + +#define PHYA_PCSS_M3_BP_L (0x00380018) +#define PHYA_PCSS_M3_BP_L___RWC QCSR_REG_RW +#define PHYA_PCSS_M3_BP_L___POR 0x00000000 +#define PHYA_PCSS_M3_BP_L__BP_DBG_CMD___POR 0x00000000 +#define PHYA_PCSS_M3_BP_L__BP_DBG_CMD___M 0xFFFFFFFF +#define PHYA_PCSS_M3_BP_L__BP_DBG_CMD___S 0 +#define PHYA_PCSS_M3_BP_L___M 0xFFFFFFFF +#define PHYA_PCSS_M3_BP_L___S 0 + +#define PHYA_PCSS_M3_BP_U (0x0038001C) +#define PHYA_PCSS_M3_BP_U___RWC QCSR_REG_RW +#define PHYA_PCSS_M3_BP_U___POR 0x00000000 +#define PHYA_PCSS_M3_BP_U__BREAKPOINT___POR 0x0 +#define PHYA_PCSS_M3_BP_U__BREAKPOINT___M 0x00000001 +#define PHYA_PCSS_M3_BP_U__BREAKPOINT___S 0 +#define PHYA_PCSS_M3_BP_U___M 0x00000001 +#define PHYA_PCSS_M3_BP_U___S 0 + +#define PHYA_PCSS_M3_IPCREG_L (0x00380020) +#define PHYA_PCSS_M3_IPCREG_L___RWC QCSR_REG_RW +#define PHYA_PCSS_M3_IPCREG_L___POR 0x00000000 +#define PHYA_PCSS_M3_IPCREG_L__M3_TO_Q6_ADDR_PTR___POR 0x0000000 +#define PHYA_PCSS_M3_IPCREG_L__M3_TO_Q6_IPC___POR 0x0 +#define PHYA_PCSS_M3_IPCREG_L__M3_TO_Q6_ADDR_PTR___M 0xFFFFFFF0 +#define PHYA_PCSS_M3_IPCREG_L__M3_TO_Q6_ADDR_PTR___S 4 +#define PHYA_PCSS_M3_IPCREG_L__M3_TO_Q6_IPC___M 0x0000000F +#define PHYA_PCSS_M3_IPCREG_L__M3_TO_Q6_IPC___S 0 +#define PHYA_PCSS_M3_IPCREG_L___M 0xFFFFFFFF +#define PHYA_PCSS_M3_IPCREG_L___S 0 + +#define PHYA_PCSS_M3_IPCREG_U (0x00380024) +#define PHYA_PCSS_M3_IPCREG_U___RWC QCSR_REG_RW +#define PHYA_PCSS_M3_IPCREG_U___POR 0x00000000 +#define PHYA_PCSS_M3_IPCREG_U__Q6_TO_M3_ADDR_PTR___POR 0x0000000 +#define PHYA_PCSS_M3_IPCREG_U__Q6_TO_M3_IPC___POR 0x0 +#define PHYA_PCSS_M3_IPCREG_U__Q6_TO_M3_ADDR_PTR___M 0xFFFFFFF0 +#define PHYA_PCSS_M3_IPCREG_U__Q6_TO_M3_ADDR_PTR___S 4 +#define PHYA_PCSS_M3_IPCREG_U__Q6_TO_M3_IPC___M 0x0000000F +#define PHYA_PCSS_M3_IPCREG_U__Q6_TO_M3_IPC___S 0 +#define PHYA_PCSS_M3_IPCREG_U___M 0xFFFFFFFF +#define PHYA_PCSS_M3_IPCREG_U___S 0 + +#define PHYA_PCSS_M3_M3_IPCREG_L (0x00380028) +#define PHYA_PCSS_M3_M3_IPCREG_L___RWC QCSR_REG_RW +#define PHYA_PCSS_M3_M3_IPCREG_L___POR 0x00000000 +#define PHYA_PCSS_M3_M3_IPCREG_L__M3_TO_M3_ADDR_PTR___POR 0x0000000 +#define PHYA_PCSS_M3_M3_IPCREG_L__M3_TO_M3_IPC___POR 0x0 +#define PHYA_PCSS_M3_M3_IPCREG_L__M3_TO_M3_ADDR_PTR___M 0xFFFFFFF0 +#define PHYA_PCSS_M3_M3_IPCREG_L__M3_TO_M3_ADDR_PTR___S 4 +#define PHYA_PCSS_M3_M3_IPCREG_L__M3_TO_M3_IPC___M 0x0000000F +#define PHYA_PCSS_M3_M3_IPCREG_L__M3_TO_M3_IPC___S 0 +#define PHYA_PCSS_M3_M3_IPCREG_L___M 0xFFFFFFFF +#define PHYA_PCSS_M3_M3_IPCREG_L___S 0 + +#define PHYA_PCSS_M3_SW_LOG_0_L (0x00380030) +#define PHYA_PCSS_M3_SW_LOG_0_L___RWC QCSR_REG_RW +#define PHYA_PCSS_M3_SW_LOG_0_L___POR 0x00000000 +#define PHYA_PCSS_M3_SW_LOG_0_L__SW_LOG_0___POR 0x00000000 +#define PHYA_PCSS_M3_SW_LOG_0_L__SW_LOG_0___M 0xFFFFFFFF +#define PHYA_PCSS_M3_SW_LOG_0_L__SW_LOG_0___S 0 +#define PHYA_PCSS_M3_SW_LOG_0_L___M 0xFFFFFFFF +#define PHYA_PCSS_M3_SW_LOG_0_L___S 0 + +#define PHYA_PCSS_M3_SW_LOG_0_U (0x00380034) +#define PHYA_PCSS_M3_SW_LOG_0_U___RWC QCSR_REG_RW +#define PHYA_PCSS_M3_SW_LOG_0_U___POR 0x00000000 +#define PHYA_PCSS_M3_SW_LOG_0_U__SW_LOG_1___POR 0x00000000 +#define PHYA_PCSS_M3_SW_LOG_0_U__SW_LOG_1___M 0xFFFFFFFF +#define PHYA_PCSS_M3_SW_LOG_0_U__SW_LOG_1___S 0 +#define PHYA_PCSS_M3_SW_LOG_0_U___M 0xFFFFFFFF +#define PHYA_PCSS_M3_SW_LOG_0_U___S 0 + +#define PHYA_PCSS_M3_SW_LOG_1_L (0x00380038) +#define PHYA_PCSS_M3_SW_LOG_1_L___RWC QCSR_REG_RW +#define PHYA_PCSS_M3_SW_LOG_1_L___POR 0x00000000 +#define PHYA_PCSS_M3_SW_LOG_1_L__SW_LOG2_0___POR 0x00000000 +#define PHYA_PCSS_M3_SW_LOG_1_L__SW_LOG2_0___M 0xFFFFFFFF +#define PHYA_PCSS_M3_SW_LOG_1_L__SW_LOG2_0___S 0 +#define PHYA_PCSS_M3_SW_LOG_1_L___M 0xFFFFFFFF +#define PHYA_PCSS_M3_SW_LOG_1_L___S 0 + +#define PHYA_PCSS_M3_SW_LOG_1_U (0x0038003C) +#define PHYA_PCSS_M3_SW_LOG_1_U___RWC QCSR_REG_RW +#define PHYA_PCSS_M3_SW_LOG_1_U___POR 0x00000000 +#define PHYA_PCSS_M3_SW_LOG_1_U__SW_LOG2_1___POR 0x00000000 +#define PHYA_PCSS_M3_SW_LOG_1_U__SW_LOG2_1___M 0xFFFFFFFF +#define PHYA_PCSS_M3_SW_LOG_1_U__SW_LOG2_1___S 0 +#define PHYA_PCSS_M3_SW_LOG_1_U___M 0xFFFFFFFF +#define PHYA_PCSS_M3_SW_LOG_1_U___S 0 + +#define PHYA_PCSS_CRC_CTRL_L (0x00380040) +#define PHYA_PCSS_CRC_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PCSS_CRC_CTRL_L___POR 0x00000000 +#define PHYA_PCSS_CRC_CTRL_L__CRC_INIT_ALLONE___POR 0x0 +#define PHYA_PCSS_CRC_CTRL_L__CRC_BIT_REVERSE___POR 0x0 +#define PHYA_PCSS_CRC_CTRL_L__CRC_START___POR 0x0 +#define PHYA_PCSS_CRC_CTRL_L__CRC_8BIT___POR 0x0 +#define PHYA_PCSS_CRC_CTRL_L__CRC_DATA_SIZE___POR 0x0 +#define PHYA_PCSS_CRC_CTRL_L__CRC_INIT_ALLONE___M 0x00000020 +#define PHYA_PCSS_CRC_CTRL_L__CRC_INIT_ALLONE___S 5 +#define PHYA_PCSS_CRC_CTRL_L__CRC_BIT_REVERSE___M 0x00000010 +#define PHYA_PCSS_CRC_CTRL_L__CRC_BIT_REVERSE___S 4 +#define PHYA_PCSS_CRC_CTRL_L__CRC_START___M 0x00000008 +#define PHYA_PCSS_CRC_CTRL_L__CRC_START___S 3 +#define PHYA_PCSS_CRC_CTRL_L__CRC_8BIT___M 0x00000004 +#define PHYA_PCSS_CRC_CTRL_L__CRC_8BIT___S 2 +#define PHYA_PCSS_CRC_CTRL_L__CRC_DATA_SIZE___M 0x00000003 +#define PHYA_PCSS_CRC_CTRL_L__CRC_DATA_SIZE___S 0 +#define PHYA_PCSS_CRC_CTRL_L___M 0x0000003F +#define PHYA_PCSS_CRC_CTRL_L___S 0 + +#define PHYA_PCSS_CRC_DATA0_L (0x00380048) +#define PHYA_PCSS_CRC_DATA0_L___RWC QCSR_REG_RW +#define PHYA_PCSS_CRC_DATA0_L___POR 0x00000000 +#define PHYA_PCSS_CRC_DATA0_L__CRC_DATA_0_0___POR 0x00000000 +#define PHYA_PCSS_CRC_DATA0_L__CRC_DATA_0_0___M 0xFFFFFFFF +#define PHYA_PCSS_CRC_DATA0_L__CRC_DATA_0_0___S 0 +#define PHYA_PCSS_CRC_DATA0_L___M 0xFFFFFFFF +#define PHYA_PCSS_CRC_DATA0_L___S 0 + +#define PHYA_PCSS_CRC_DATA0_U (0x0038004C) +#define PHYA_PCSS_CRC_DATA0_U___RWC QCSR_REG_RW +#define PHYA_PCSS_CRC_DATA0_U___POR 0x00000000 +#define PHYA_PCSS_CRC_DATA0_U__CRC_DATA_1_0___POR 0x00000000 +#define PHYA_PCSS_CRC_DATA0_U__CRC_DATA_1_0___M 0xFFFFFFFF +#define PHYA_PCSS_CRC_DATA0_U__CRC_DATA_1_0___S 0 +#define PHYA_PCSS_CRC_DATA0_U___M 0xFFFFFFFF +#define PHYA_PCSS_CRC_DATA0_U___S 0 + +#define PHYA_PCSS_CRC_DATA1_L (0x00380050) +#define PHYA_PCSS_CRC_DATA1_L___RWC QCSR_REG_RW +#define PHYA_PCSS_CRC_DATA1_L___POR 0x00000000 +#define PHYA_PCSS_CRC_DATA1_L__CRC_DATA_0_1___POR 0x00000000 +#define PHYA_PCSS_CRC_DATA1_L__CRC_DATA_0_1___M 0xFFFFFFFF +#define PHYA_PCSS_CRC_DATA1_L__CRC_DATA_0_1___S 0 +#define PHYA_PCSS_CRC_DATA1_L___M 0xFFFFFFFF +#define PHYA_PCSS_CRC_DATA1_L___S 0 + +#define PHYA_PCSS_CRC_DATA1_U (0x00380054) +#define PHYA_PCSS_CRC_DATA1_U___RWC QCSR_REG_RW +#define PHYA_PCSS_CRC_DATA1_U___POR 0x00000000 +#define PHYA_PCSS_CRC_DATA1_U__CRC_DATA_1_1___POR 0x00000000 +#define PHYA_PCSS_CRC_DATA1_U__CRC_DATA_1_1___M 0xFFFFFFFF +#define PHYA_PCSS_CRC_DATA1_U__CRC_DATA_1_1___S 0 +#define PHYA_PCSS_CRC_DATA1_U___M 0xFFFFFFFF +#define PHYA_PCSS_CRC_DATA1_U___S 0 + +#define PHYA_PCSS_CRC_RESULT_L (0x00380058) +#define PHYA_PCSS_CRC_RESULT_L___RWC QCSR_REG_RO +#define PHYA_PCSS_CRC_RESULT_L___POR 0x000000FF +#define PHYA_PCSS_CRC_RESULT_L__CRC_RESULT___POR 0xFF +#define PHYA_PCSS_CRC_RESULT_L__CRC_RESULT___M 0x000000FF +#define PHYA_PCSS_CRC_RESULT_L__CRC_RESULT___S 0 +#define PHYA_PCSS_CRC_RESULT_L___M 0x000000FF +#define PHYA_PCSS_CRC_RESULT_L___S 0 + +#define PHYA_PCSS_RRI_CTRL_0_L (0x00380060) +#define PHYA_PCSS_RRI_CTRL_0_L___RWC QCSR_REG_RW +#define PHYA_PCSS_RRI_CTRL_0_L___POR 0x00000000 +#define PHYA_PCSS_RRI_CTRL_0_L__RRI_INIT_DONE_INTR___POR 0x0 +#define PHYA_PCSS_RRI_CTRL_0_L__RRI_INIT_DONE_INTR___M 0x00000001 +#define PHYA_PCSS_RRI_CTRL_0_L__RRI_INIT_DONE_INTR___S 0 +#define PHYA_PCSS_RRI_CTRL_0_L___M 0x00000001 +#define PHYA_PCSS_RRI_CTRL_0_L___S 0 + +#define PHYA_PCSS_RRI_CTRL_0_U (0x00380064) +#define PHYA_PCSS_RRI_CTRL_0_U___RWC QCSR_REG_RW +#define PHYA_PCSS_RRI_CTRL_0_U___POR 0x00000000 +#define PHYA_PCSS_RRI_CTRL_0_U__RRI_REG_SAVE_ADDR___POR 0x000000 +#define PHYA_PCSS_RRI_CTRL_0_U__RRI_REG_SAVE_ADDR___M 0x00FFFFFF +#define PHYA_PCSS_RRI_CTRL_0_U__RRI_REG_SAVE_ADDR___S 0 +#define PHYA_PCSS_RRI_CTRL_0_U___M 0x00FFFFFF +#define PHYA_PCSS_RRI_CTRL_0_U___S 0 + +#define PHYA_PCSS_RRI_CTRL_1_L (0x00380068) +#define PHYA_PCSS_RRI_CTRL_1_L___RWC QCSR_REG_RW +#define PHYA_PCSS_RRI_CTRL_1_L___POR 0x00000000 +#define PHYA_PCSS_RRI_CTRL_1_L__RRI_REG_RESTORE_ADDR___POR 0x000000 +#define PHYA_PCSS_RRI_CTRL_1_L__RRI_REG_RESTORE_ADDR___M 0x00FFFFFF +#define PHYA_PCSS_RRI_CTRL_1_L__RRI_REG_RESTORE_ADDR___S 0 +#define PHYA_PCSS_RRI_CTRL_1_L___M 0x00FFFFFF +#define PHYA_PCSS_RRI_CTRL_1_L___S 0 + +#define PHYA_PCSS_CORE_RESET_L (0x00380070) +#define PHYA_PCSS_CORE_RESET_L___RWC QCSR_REG_WO +#define PHYA_PCSS_CORE_RESET_L___POR 0x00000000 +#define PHYA_PCSS_CORE_RESET_L__LDPC_CAL_SYNC_RST___POR 0x0 +#define PHYA_PCSS_CORE_RESET_L__CBF_SYNC_RST___POR 0x0 +#define PHYA_PCSS_CORE_RESET_L__TXBFER_SYNC_RST___POR 0x0 +#define PHYA_PCSS_CORE_RESET_L__MPI_SYNC_RST___POR 0x0 +#define PHYA_PCSS_CORE_RESET_L__DEMF_SYNC_RST_MTNP___POR 0x0 +#define PHYA_PCSS_CORE_RESET_L__FFT_SYNC_RST___POR 0x0 +#define PHYA_PCSS_CORE_RESET_L__ROBE_SYNC_RST___POR 0x0 +#define PHYA_PCSS_CORE_RESET_L__TXFD_SYNC_RST___POR 0x0 +#define PHYA_PCSS_CORE_RESET_L__DEMF_SYNC_RST___POR 0x0 +#define PHYA_PCSS_CORE_RESET_L__TXTD_SYNC_RST___POR 0x0 +#define PHYA_PCSS_CORE_RESET_L__RXTD_SYNC_RST___POR 0x0 +#define PHYA_PCSS_CORE_RESET_L__PHYRF_SYNC_RST___POR 0x0 +#define PHYA_PCSS_CORE_RESET_L__LDPC_CAL_SYNC_RST___M 0x00000800 +#define PHYA_PCSS_CORE_RESET_L__LDPC_CAL_SYNC_RST___S 11 +#define PHYA_PCSS_CORE_RESET_L__CBF_SYNC_RST___M 0x00000400 +#define PHYA_PCSS_CORE_RESET_L__CBF_SYNC_RST___S 10 +#define PHYA_PCSS_CORE_RESET_L__TXBFER_SYNC_RST___M 0x00000200 +#define PHYA_PCSS_CORE_RESET_L__TXBFER_SYNC_RST___S 9 +#define PHYA_PCSS_CORE_RESET_L__MPI_SYNC_RST___M 0x00000100 +#define PHYA_PCSS_CORE_RESET_L__MPI_SYNC_RST___S 8 +#define PHYA_PCSS_CORE_RESET_L__DEMF_SYNC_RST_MTNP___M 0x00000080 +#define PHYA_PCSS_CORE_RESET_L__DEMF_SYNC_RST_MTNP___S 7 +#define PHYA_PCSS_CORE_RESET_L__FFT_SYNC_RST___M 0x00000040 +#define PHYA_PCSS_CORE_RESET_L__FFT_SYNC_RST___S 6 +#define PHYA_PCSS_CORE_RESET_L__ROBE_SYNC_RST___M 0x00000020 +#define PHYA_PCSS_CORE_RESET_L__ROBE_SYNC_RST___S 5 +#define PHYA_PCSS_CORE_RESET_L__TXFD_SYNC_RST___M 0x00000010 +#define PHYA_PCSS_CORE_RESET_L__TXFD_SYNC_RST___S 4 +#define PHYA_PCSS_CORE_RESET_L__DEMF_SYNC_RST___M 0x00000008 +#define PHYA_PCSS_CORE_RESET_L__DEMF_SYNC_RST___S 3 +#define PHYA_PCSS_CORE_RESET_L__TXTD_SYNC_RST___M 0x00000004 +#define PHYA_PCSS_CORE_RESET_L__TXTD_SYNC_RST___S 2 +#define PHYA_PCSS_CORE_RESET_L__RXTD_SYNC_RST___M 0x00000002 +#define PHYA_PCSS_CORE_RESET_L__RXTD_SYNC_RST___S 1 +#define PHYA_PCSS_CORE_RESET_L__PHYRF_SYNC_RST___M 0x00000001 +#define PHYA_PCSS_CORE_RESET_L__PHYRF_SYNC_RST___S 0 +#define PHYA_PCSS_CORE_RESET_L___M 0x00000FFF +#define PHYA_PCSS_CORE_RESET_L___S 0 + +#define PHYA_PCSS_PHY_VER_REG_L (0x00380078) +#define PHYA_PCSS_PHY_VER_REG_L___RWC QCSR_REG_RO +#define PHYA_PCSS_PHY_VER_REG_L___POR 0x00080000 +#define PHYA_PCSS_PHY_VER_REG_L__MINOR___POR 0x008 +#define PHYA_PCSS_PHY_VER_REG_L__STEP___POR 0x0000 +#define PHYA_PCSS_PHY_VER_REG_L__MINOR___M 0x0FFF0000 +#define PHYA_PCSS_PHY_VER_REG_L__MINOR___S 16 +#define PHYA_PCSS_PHY_VER_REG_L__STEP___M 0x0000FFFF +#define PHYA_PCSS_PHY_VER_REG_L__STEP___S 0 +#define PHYA_PCSS_PHY_VER_REG_L___M 0x0FFFFFFF +#define PHYA_PCSS_PHY_VER_REG_L___S 0 + +#define PHYA_PCSS_PHY_VER_REG_U (0x0038007C) +#define PHYA_PCSS_PHY_VER_REG_U___RWC QCSR_REG_RO +#define PHYA_PCSS_PHY_VER_REG_U___POR 0x00000001 +#define PHYA_PCSS_PHY_VER_REG_U__SEG_ID___POR 0x0 +#define PHYA_PCSS_PHY_VER_REG_U__MAJOR___POR 0x1 +#define PHYA_PCSS_PHY_VER_REG_U__SEG_ID___M 0x00000300 +#define PHYA_PCSS_PHY_VER_REG_U__SEG_ID___S 8 +#define PHYA_PCSS_PHY_VER_REG_U__MAJOR___M 0x0000000F +#define PHYA_PCSS_PHY_VER_REG_U__MAJOR___S 0 +#define PHYA_PCSS_PHY_VER_REG_U___M 0x0000030F +#define PHYA_PCSS_PHY_VER_REG_U___S 0 + +#define PHYA_PCSS_PHY_OTP_L (0x00380080) +#define PHYA_PCSS_PHY_OTP_L___RWC QCSR_REG_RO +#define PHYA_PCSS_PHY_OTP_L___POR 0x00000000 +#define PHYA_PCSS_PHY_OTP_L__PHY_OTP___POR 0x00000000 +#define PHYA_PCSS_PHY_OTP_L__PHY_OTP___M 0xFFFFFFFF +#define PHYA_PCSS_PHY_OTP_L__PHY_OTP___S 0 +#define PHYA_PCSS_PHY_OTP_L___M 0xFFFFFFFF +#define PHYA_PCSS_PHY_OTP_L___S 0 + +#define PHYA_PCSS_NTS_CTRL_L (0x00380088) +#define PHYA_PCSS_NTS_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PCSS_NTS_CTRL_L___POR 0x00000000 +#define PHYA_PCSS_NTS_CTRL_L__NTS_ACK___POR 0x0 +#define PHYA_PCSS_NTS_CTRL_L__NTS_EN___POR 0x0 +#define PHYA_PCSS_NTS_CTRL_L__NTS_ACK___M 0x00000002 +#define PHYA_PCSS_NTS_CTRL_L__NTS_ACK___S 1 +#define PHYA_PCSS_NTS_CTRL_L__NTS_EN___M 0x00000001 +#define PHYA_PCSS_NTS_CTRL_L__NTS_EN___S 0 +#define PHYA_PCSS_NTS_CTRL_L___M 0x00000003 +#define PHYA_PCSS_NTS_CTRL_L___S 0 + +#define PHYA_PCSS_TIMER_WDOG_CLK_EN_L (0x00380090) +#define PHYA_PCSS_TIMER_WDOG_CLK_EN_L___RWC QCSR_REG_RW +#define PHYA_PCSS_TIMER_WDOG_CLK_EN_L___POR 0x00000000 +#define PHYA_PCSS_TIMER_WDOG_CLK_EN_L__TIMER4_CLK_EN___POR 0x0 +#define PHYA_PCSS_TIMER_WDOG_CLK_EN_L__TIMER3_CLK_EN___POR 0x0 +#define PHYA_PCSS_TIMER_WDOG_CLK_EN_L__ECO_REV_NO___POR 0x0 +#define PHYA_PCSS_TIMER_WDOG_CLK_EN_L__WDOG_CLK_EN___POR 0x0 +#define PHYA_PCSS_TIMER_WDOG_CLK_EN_L__TIMER2_CLK_EN___POR 0x0 +#define PHYA_PCSS_TIMER_WDOG_CLK_EN_L__TIMER1_CLK_EN___POR 0x0 +#define PHYA_PCSS_TIMER_WDOG_CLK_EN_L__TIMER4_CLK_EN___M 0x00000100 +#define PHYA_PCSS_TIMER_WDOG_CLK_EN_L__TIMER4_CLK_EN___S 8 +#define PHYA_PCSS_TIMER_WDOG_CLK_EN_L__TIMER3_CLK_EN___M 0x00000080 +#define PHYA_PCSS_TIMER_WDOG_CLK_EN_L__TIMER3_CLK_EN___S 7 +#define PHYA_PCSS_TIMER_WDOG_CLK_EN_L__ECO_REV_NO___M 0x00000078 +#define PHYA_PCSS_TIMER_WDOG_CLK_EN_L__ECO_REV_NO___S 3 +#define PHYA_PCSS_TIMER_WDOG_CLK_EN_L__WDOG_CLK_EN___M 0x00000004 +#define PHYA_PCSS_TIMER_WDOG_CLK_EN_L__WDOG_CLK_EN___S 2 +#define PHYA_PCSS_TIMER_WDOG_CLK_EN_L__TIMER2_CLK_EN___M 0x00000002 +#define PHYA_PCSS_TIMER_WDOG_CLK_EN_L__TIMER2_CLK_EN___S 1 +#define PHYA_PCSS_TIMER_WDOG_CLK_EN_L__TIMER1_CLK_EN___M 0x00000001 +#define PHYA_PCSS_TIMER_WDOG_CLK_EN_L__TIMER1_CLK_EN___S 0 +#define PHYA_PCSS_TIMER_WDOG_CLK_EN_L___M 0x000001FF +#define PHYA_PCSS_TIMER_WDOG_CLK_EN_L___S 0 + +#define PHYA_PCSS_LDPC_CONFIG_0_L (0x00380098) +#define PHYA_PCSS_LDPC_CONFIG_0_L___RWC QCSR_REG_RW +#define PHYA_PCSS_LDPC_CONFIG_0_L___POR 0x00000000 +#define PHYA_PCSS_LDPC_CONFIG_0_L__PKT_TYPE___POR 0x0 +#define PHYA_PCSS_LDPC_CONFIG_0_L__PKT_TYPE___M 0x0000000F +#define PHYA_PCSS_LDPC_CONFIG_0_L__PKT_TYPE___S 0 +#define PHYA_PCSS_LDPC_CONFIG_0_L___M 0x0000000F +#define PHYA_PCSS_LDPC_CONFIG_0_L___S 0 + +#define PHYA_PCSS_LDPC_CONFIG_0_U (0x0038009C) +#define PHYA_PCSS_LDPC_CONFIG_0_U___RWC QCSR_REG_RW +#define PHYA_PCSS_LDPC_CONFIG_0_U___POR 0x00000000 +#define PHYA_PCSS_LDPC_CONFIG_0_U__PSDU_LENGTH___POR 0x000000 +#define PHYA_PCSS_LDPC_CONFIG_0_U__PSDU_LENGTH___M 0x003FFFFF +#define PHYA_PCSS_LDPC_CONFIG_0_U__PSDU_LENGTH___S 0 +#define PHYA_PCSS_LDPC_CONFIG_0_U___M 0x003FFFFF +#define PHYA_PCSS_LDPC_CONFIG_0_U___S 0 + +#define PHYA_PCSS_LDPC_CONFIG_1_L (0x003800A0) +#define PHYA_PCSS_LDPC_CONFIG_1_L___RWC QCSR_REG_RW +#define PHYA_PCSS_LDPC_CONFIG_1_L___POR 0x00000000 +#define PHYA_PCSS_LDPC_CONFIG_1_L__NUM_SYM___POR 0x000000 +#define PHYA_PCSS_LDPC_CONFIG_1_L__NUM_SYM___M 0x00FFFFFF +#define PHYA_PCSS_LDPC_CONFIG_1_L__NUM_SYM___S 0 +#define PHYA_PCSS_LDPC_CONFIG_1_L___M 0x00FFFFFF +#define PHYA_PCSS_LDPC_CONFIG_1_L___S 0 + +#define PHYA_PCSS_LDPC_CONFIG_1_U (0x003800A4) +#define PHYA_PCSS_LDPC_CONFIG_1_U___RWC QCSR_REG_RW +#define PHYA_PCSS_LDPC_CONFIG_1_U___POR 0x00000000 +#define PHYA_PCSS_LDPC_CONFIG_1_U__NDBPS___POR 0x00000 +#define PHYA_PCSS_LDPC_CONFIG_1_U__NDBPS___M 0x0001FFFF +#define PHYA_PCSS_LDPC_CONFIG_1_U__NDBPS___S 0 +#define PHYA_PCSS_LDPC_CONFIG_1_U___M 0x0001FFFF +#define PHYA_PCSS_LDPC_CONFIG_1_U___S 0 + +#define PHYA_PCSS_LDPC_CONFIG_2_L (0x003800A8) +#define PHYA_PCSS_LDPC_CONFIG_2_L___RWC QCSR_REG_RW +#define PHYA_PCSS_LDPC_CONFIG_2_L___POR 0x00000000 +#define PHYA_PCSS_LDPC_CONFIG_2_L__NCBPS___POR 0x00000 +#define PHYA_PCSS_LDPC_CONFIG_2_L__NCBPS___M 0x0001FFFF +#define PHYA_PCSS_LDPC_CONFIG_2_L__NCBPS___S 0 +#define PHYA_PCSS_LDPC_CONFIG_2_L___M 0x0001FFFF +#define PHYA_PCSS_LDPC_CONFIG_2_L___S 0 + +#define PHYA_PCSS_LDPC_CONFIG_2_U (0x003800AC) +#define PHYA_PCSS_LDPC_CONFIG_2_U___RWC QCSR_REG_RW +#define PHYA_PCSS_LDPC_CONFIG_2_U___POR 0x00000000 +#define PHYA_PCSS_LDPC_CONFIG_2_U__NDBPS_SHORT___POR 0x00000 +#define PHYA_PCSS_LDPC_CONFIG_2_U__NDBPS_SHORT___M 0x0001FFFF +#define PHYA_PCSS_LDPC_CONFIG_2_U__NDBPS_SHORT___S 0 +#define PHYA_PCSS_LDPC_CONFIG_2_U___M 0x0001FFFF +#define PHYA_PCSS_LDPC_CONFIG_2_U___S 0 + +#define PHYA_PCSS_LDPC_CONFIG_3_L (0x003800B0) +#define PHYA_PCSS_LDPC_CONFIG_3_L___RWC QCSR_REG_RW +#define PHYA_PCSS_LDPC_CONFIG_3_L___POR 0x00000000 +#define PHYA_PCSS_LDPC_CONFIG_3_L__NCBPS_SHORT___POR 0x00000 +#define PHYA_PCSS_LDPC_CONFIG_3_L__NCBPS_SHORT___M 0x0001FFFF +#define PHYA_PCSS_LDPC_CONFIG_3_L__NCBPS_SHORT___S 0 +#define PHYA_PCSS_LDPC_CONFIG_3_L___M 0x0001FFFF +#define PHYA_PCSS_LDPC_CONFIG_3_L___S 0 + +#define PHYA_PCSS_LDPC_CONFIG_3_U (0x003800B4) +#define PHYA_PCSS_LDPC_CONFIG_3_U___RWC QCSR_REG_RW +#define PHYA_PCSS_LDPC_CONFIG_3_U___POR 0x00000000 +#define PHYA_PCSS_LDPC_CONFIG_3_U__STBC_EN___POR 0x0 +#define PHYA_PCSS_LDPC_CONFIG_3_U__EXTRA_SYMBOL___POR 0x0 +#define PHYA_PCSS_LDPC_CONFIG_3_U__ALPHA_FACTOR___POR 0x0 +#define PHYA_PCSS_LDPC_CONFIG_3_U__CODE_RATE___POR 0x0 +#define PHYA_PCSS_LDPC_CONFIG_3_U__STBC_EN___M 0x01000000 +#define PHYA_PCSS_LDPC_CONFIG_3_U__STBC_EN___S 24 +#define PHYA_PCSS_LDPC_CONFIG_3_U__EXTRA_SYMBOL___M 0x00010000 +#define PHYA_PCSS_LDPC_CONFIG_3_U__EXTRA_SYMBOL___S 16 +#define PHYA_PCSS_LDPC_CONFIG_3_U__ALPHA_FACTOR___M 0x00000300 +#define PHYA_PCSS_LDPC_CONFIG_3_U__ALPHA_FACTOR___S 8 +#define PHYA_PCSS_LDPC_CONFIG_3_U__CODE_RATE___M 0x00000007 +#define PHYA_PCSS_LDPC_CONFIG_3_U__CODE_RATE___S 0 +#define PHYA_PCSS_LDPC_CONFIG_3_U___M 0x01010307 +#define PHYA_PCSS_LDPC_CONFIG_3_U___S 0 + +#define PHYA_PCSS_LDPC_CONFIG_4_L (0x003800B8) +#define PHYA_PCSS_LDPC_CONFIG_4_L___RWC QCSR_REG_RW +#define PHYA_PCSS_LDPC_CONFIG_4_L___POR 0x00000000 +#define PHYA_PCSS_LDPC_CONFIG_4_L__START___POR 0x0 +#define PHYA_PCSS_LDPC_CONFIG_4_L__START___M 0x00000001 +#define PHYA_PCSS_LDPC_CONFIG_4_L__START___S 0 +#define PHYA_PCSS_LDPC_CONFIG_4_L___M 0x00000001 +#define PHYA_PCSS_LDPC_CONFIG_4_L___S 0 + +#define PHYA_PCSS_LDPC_STATUS_L (0x003800C0) +#define PHYA_PCSS_LDPC_STATUS_L___RWC QCSR_REG_RO +#define PHYA_PCSS_LDPC_STATUS_L___POR 0x00000000 +#define PHYA_PCSS_LDPC_STATUS_L__READY___POR 0x0 +#define PHYA_PCSS_LDPC_STATUS_L__READY___M 0x00000001 +#define PHYA_PCSS_LDPC_STATUS_L__READY___S 0 +#define PHYA_PCSS_LDPC_STATUS_L___M 0x00000001 +#define PHYA_PCSS_LDPC_STATUS_L___S 0 + +#define PHYA_PCSS_LDPC_PARAM_0_L (0x003800C8) +#define PHYA_PCSS_LDPC_PARAM_0_L___RWC QCSR_REG_RO +#define PHYA_PCSS_LDPC_PARAM_0_L___POR 0x00000001 +#define PHYA_PCSS_LDPC_PARAM_0_L__NSHRT_PLUS1___POR 0x0000 +#define PHYA_PCSS_LDPC_PARAM_0_L__CODE_LENGTH___POR 0x0 +#define PHYA_PCSS_LDPC_PARAM_0_L__NPUNC_REPEAT___POR 0x1 +#define PHYA_PCSS_LDPC_PARAM_0_L__NSHRT_PLUS1___M 0xFFFF0000 +#define PHYA_PCSS_LDPC_PARAM_0_L__NSHRT_PLUS1___S 16 +#define PHYA_PCSS_LDPC_PARAM_0_L__CODE_LENGTH___M 0x00000300 +#define PHYA_PCSS_LDPC_PARAM_0_L__CODE_LENGTH___S 8 +#define PHYA_PCSS_LDPC_PARAM_0_L__NPUNC_REPEAT___M 0x00000001 +#define PHYA_PCSS_LDPC_PARAM_0_L__NPUNC_REPEAT___S 0 +#define PHYA_PCSS_LDPC_PARAM_0_L___M 0xFFFF0301 +#define PHYA_PCSS_LDPC_PARAM_0_L___S 0 + +#define PHYA_PCSS_LDPC_PARAM_0_U (0x003800CC) +#define PHYA_PCSS_LDPC_PARAM_0_U___RWC QCSR_REG_RO +#define PHYA_PCSS_LDPC_PARAM_0_U___POR 0x00000000 +#define PHYA_PCSS_LDPC_PARAM_0_U__NPUNC_PLUS1___POR 0x0000 +#define PHYA_PCSS_LDPC_PARAM_0_U__NUM_CW___POR 0x0000 +#define PHYA_PCSS_LDPC_PARAM_0_U__NPUNC_PLUS1___M 0xFFFF0000 +#define PHYA_PCSS_LDPC_PARAM_0_U__NPUNC_PLUS1___S 16 +#define PHYA_PCSS_LDPC_PARAM_0_U__NUM_CW___M 0x0000FFFF +#define PHYA_PCSS_LDPC_PARAM_0_U__NUM_CW___S 0 +#define PHYA_PCSS_LDPC_PARAM_0_U___M 0xFFFFFFFF +#define PHYA_PCSS_LDPC_PARAM_0_U___S 0 + +#define PHYA_PCSS_LDPC_PARAM_1_L (0x003800D0) +#define PHYA_PCSS_LDPC_PARAM_1_L___RWC QCSR_REG_RO +#define PHYA_PCSS_LDPC_PARAM_1_L___POR 0x00000000 +#define PHYA_PCSS_LDPC_PARAM_1_L__NPUNC___POR 0x0000 +#define PHYA_PCSS_LDPC_PARAM_1_L__NSHRT___POR 0x000 +#define PHYA_PCSS_LDPC_PARAM_1_L__NPUNC___M 0xFFFF0000 +#define PHYA_PCSS_LDPC_PARAM_1_L__NPUNC___S 16 +#define PHYA_PCSS_LDPC_PARAM_1_L__NSHRT___M 0x000007FF +#define PHYA_PCSS_LDPC_PARAM_1_L__NSHRT___S 0 +#define PHYA_PCSS_LDPC_PARAM_1_L___M 0xFFFF07FF +#define PHYA_PCSS_LDPC_PARAM_1_L___S 0 + +#define PHYA_PCSS_LDPC_PARAM_1_U (0x003800D4) +#define PHYA_PCSS_LDPC_PARAM_1_U___RWC QCSR_REG_RO +#define PHYA_PCSS_LDPC_PARAM_1_U___POR 0x00000000 +#define PHYA_PCSS_LDPC_PARAM_1_U__NUM_SYM_OUT___POR 0x0000000 +#define PHYA_PCSS_LDPC_PARAM_1_U__NUM_SYM_OUT___M 0x03FFFFFF +#define PHYA_PCSS_LDPC_PARAM_1_U__NUM_SYM_OUT___S 0 +#define PHYA_PCSS_LDPC_PARAM_1_U___M 0x03FFFFFF +#define PHYA_PCSS_LDPC_PARAM_1_U___S 0 + +#define PHYA_PCSS_LDPC_PARAM_2_L (0x003800D8) +#define PHYA_PCSS_LDPC_PARAM_2_L___RWC QCSR_REG_RO +#define PHYA_PCSS_LDPC_PARAM_2_L___POR 0x00000000 +#define PHYA_PCSS_LDPC_PARAM_2_L__NPLD_BITS___POR 0x0000000 +#define PHYA_PCSS_LDPC_PARAM_2_L__NPLD_BITS___M 0x01FFFFFF +#define PHYA_PCSS_LDPC_PARAM_2_L__NPLD_BITS___S 0 +#define PHYA_PCSS_LDPC_PARAM_2_L___M 0x01FFFFFF +#define PHYA_PCSS_LDPC_PARAM_2_L___S 0 + +#define PHYA_PCSS_LDPC_CALC_DEBUG_L (0x003800E0) +#define PHYA_PCSS_LDPC_CALC_DEBUG_L___RWC QCSR_REG_RO +#define PHYA_PCSS_LDPC_CALC_DEBUG_L___POR 0x00000000 +#define PHYA_PCSS_LDPC_CALC_DEBUG_L__DBG_LDP_PARAM_CAL_PS___POR 0x0 +#define PHYA_PCSS_LDPC_CALC_DEBUG_L__LDP_PARAM_CALC_HANG_ERROR___POR 0x0 +#define PHYA_PCSS_LDPC_CALC_DEBUG_L__DBG_LDP_PARAM_CAL_PS___M 0x00000F00 +#define PHYA_PCSS_LDPC_CALC_DEBUG_L__DBG_LDP_PARAM_CAL_PS___S 8 +#define PHYA_PCSS_LDPC_CALC_DEBUG_L__LDP_PARAM_CALC_HANG_ERROR___M 0x00000001 +#define PHYA_PCSS_LDPC_CALC_DEBUG_L__LDP_PARAM_CALC_HANG_ERROR___S 0 +#define PHYA_PCSS_LDPC_CALC_DEBUG_L___M 0x00000F01 +#define PHYA_PCSS_LDPC_CALC_DEBUG_L___S 0 + +#define PHYA_PCSS_NOC_SMARTMUX_MASK_L (0x003800E8) +#define PHYA_PCSS_NOC_SMARTMUX_MASK_L___RWC QCSR_REG_RW +#define PHYA_PCSS_NOC_SMARTMUX_MASK_L___POR 0x00000000 +#define PHYA_PCSS_NOC_SMARTMUX_MASK_L__NOC_SMARTMUX_MASK___POR 0x00 +#define PHYA_PCSS_NOC_SMARTMUX_MASK_L__NOC_SMARTMUX_MASK___M 0x000000FF +#define PHYA_PCSS_NOC_SMARTMUX_MASK_L__NOC_SMARTMUX_MASK___S 0 +#define PHYA_PCSS_NOC_SMARTMUX_MASK_L___M 0x000000FF +#define PHYA_PCSS_NOC_SMARTMUX_MASK_L___S 0 + +#define PHYA_PCSS_WATCHDOG_CONFIG_REG_L (0x003800F0) +#define PHYA_PCSS_WATCHDOG_CONFIG_REG_L___RWC QCSR_REG_RW +#define PHYA_PCSS_WATCHDOG_CONFIG_REG_L___POR 0x00000000 +#define PHYA_PCSS_WATCHDOG_CONFIG_REG_L__WATCHDOG_CONFIG_REG_0___POR 0x00000000 +#define PHYA_PCSS_WATCHDOG_CONFIG_REG_L__WATCHDOG_CONFIG_REG_0___M 0xFFFFFFFF +#define PHYA_PCSS_WATCHDOG_CONFIG_REG_L__WATCHDOG_CONFIG_REG_0___S 0 +#define PHYA_PCSS_WATCHDOG_CONFIG_REG_L___M 0xFFFFFFFF +#define PHYA_PCSS_WATCHDOG_CONFIG_REG_L___S 0 + +#define PHYA_PCSS_WATCHDOG_CONFIG_REG_U (0x003800F4) +#define PHYA_PCSS_WATCHDOG_CONFIG_REG_U___RWC QCSR_REG_RW +#define PHYA_PCSS_WATCHDOG_CONFIG_REG_U___POR 0x00000000 +#define PHYA_PCSS_WATCHDOG_CONFIG_REG_U__WATCHDOG_CONFIG_REG_1___POR 0x00000000 +#define PHYA_PCSS_WATCHDOG_CONFIG_REG_U__WATCHDOG_CONFIG_REG_1___M 0xFFFFFFFF +#define PHYA_PCSS_WATCHDOG_CONFIG_REG_U__WATCHDOG_CONFIG_REG_1___S 0 +#define PHYA_PCSS_WATCHDOG_CONFIG_REG_U___M 0xFFFFFFFF +#define PHYA_PCSS_WATCHDOG_CONFIG_REG_U___S 0 + +#define PHYA_PCSS_WATCHDOG_STATUS_REG0_L (0x003800F8) +#define PHYA_PCSS_WATCHDOG_STATUS_REG0_L___RWC QCSR_REG_RO +#define PHYA_PCSS_WATCHDOG_STATUS_REG0_L___POR 0x00000000 +#define PHYA_PCSS_WATCHDOG_STATUS_REG0_L__WATCHDOG_STATUS_REG_0_0___POR 0x00000000 +#define PHYA_PCSS_WATCHDOG_STATUS_REG0_L__WATCHDOG_STATUS_REG_0_0___M 0xFFFFFFFF +#define PHYA_PCSS_WATCHDOG_STATUS_REG0_L__WATCHDOG_STATUS_REG_0_0___S 0 +#define PHYA_PCSS_WATCHDOG_STATUS_REG0_L___M 0xFFFFFFFF +#define PHYA_PCSS_WATCHDOG_STATUS_REG0_L___S 0 + +#define PHYA_PCSS_WATCHDOG_STATUS_REG0_U (0x003800FC) +#define PHYA_PCSS_WATCHDOG_STATUS_REG0_U___RWC QCSR_REG_RO +#define PHYA_PCSS_WATCHDOG_STATUS_REG0_U___POR 0x00000000 +#define PHYA_PCSS_WATCHDOG_STATUS_REG0_U__WATCHDOG_STATUS_REG_1_0___POR 0x00000000 +#define PHYA_PCSS_WATCHDOG_STATUS_REG0_U__WATCHDOG_STATUS_REG_1_0___M 0xFFFFFFFF +#define PHYA_PCSS_WATCHDOG_STATUS_REG0_U__WATCHDOG_STATUS_REG_1_0___S 0 +#define PHYA_PCSS_WATCHDOG_STATUS_REG0_U___M 0xFFFFFFFF +#define PHYA_PCSS_WATCHDOG_STATUS_REG0_U___S 0 + +#define PHYA_PCSS_WATCHDOG_STATUS_REG1_L (0x00380100) +#define PHYA_PCSS_WATCHDOG_STATUS_REG1_L___RWC QCSR_REG_RO +#define PHYA_PCSS_WATCHDOG_STATUS_REG1_L___POR 0x00000000 +#define PHYA_PCSS_WATCHDOG_STATUS_REG1_L__WATCHDOG_STATUS_REG_0_1___POR 0x00000000 +#define PHYA_PCSS_WATCHDOG_STATUS_REG1_L__WATCHDOG_STATUS_REG_0_1___M 0xFFFFFFFF +#define PHYA_PCSS_WATCHDOG_STATUS_REG1_L__WATCHDOG_STATUS_REG_0_1___S 0 +#define PHYA_PCSS_WATCHDOG_STATUS_REG1_L___M 0xFFFFFFFF +#define PHYA_PCSS_WATCHDOG_STATUS_REG1_L___S 0 + +#define PHYA_PCSS_WATCHDOG_STATUS_REG1_U (0x00380104) +#define PHYA_PCSS_WATCHDOG_STATUS_REG1_U___RWC QCSR_REG_RO +#define PHYA_PCSS_WATCHDOG_STATUS_REG1_U___POR 0x00000000 +#define PHYA_PCSS_WATCHDOG_STATUS_REG1_U__WATCHDOG_STATUS_REG_1_1___POR 0x00000000 +#define PHYA_PCSS_WATCHDOG_STATUS_REG1_U__WATCHDOG_STATUS_REG_1_1___M 0xFFFFFFFF +#define PHYA_PCSS_WATCHDOG_STATUS_REG1_U__WATCHDOG_STATUS_REG_1_1___S 0 +#define PHYA_PCSS_WATCHDOG_STATUS_REG1_U___M 0xFFFFFFFF +#define PHYA_PCSS_WATCHDOG_STATUS_REG1_U___S 0 + +#define PHYA_PCSS_PCSS_SPARE_L (0x00380108) +#define PHYA_PCSS_PCSS_SPARE_L___RWC QCSR_REG_RW +#define PHYA_PCSS_PCSS_SPARE_L___POR 0x00000000 +#define PHYA_PCSS_PCSS_SPARE_L__PCSS_SPARE_0___POR 0x00000000 +#define PHYA_PCSS_PCSS_SPARE_L__PCSS_SPARE_0___M 0xFFFFFFFF +#define PHYA_PCSS_PCSS_SPARE_L__PCSS_SPARE_0___S 0 +#define PHYA_PCSS_PCSS_SPARE_L___M 0xFFFFFFFF +#define PHYA_PCSS_PCSS_SPARE_L___S 0 + +#define PHYA_PCSS_PCSS_SPARE_U (0x0038010C) +#define PHYA_PCSS_PCSS_SPARE_U___RWC QCSR_REG_RW +#define PHYA_PCSS_PCSS_SPARE_U___POR 0x00000000 +#define PHYA_PCSS_PCSS_SPARE_U__PCSS_SPARE_1___POR 0x00000000 +#define PHYA_PCSS_PCSS_SPARE_U__PCSS_SPARE_1___M 0xFFFFFFFF +#define PHYA_PCSS_PCSS_SPARE_U__PCSS_SPARE_1___S 0 +#define PHYA_PCSS_PCSS_SPARE_U___M 0xFFFFFFFF +#define PHYA_PCSS_PCSS_SPARE_U___S 0 + +#define PHYA_PCSS_PCSS_ECO_L (0x00380110) +#define PHYA_PCSS_PCSS_ECO_L___RWC QCSR_REG_RW +#define PHYA_PCSS_PCSS_ECO_L___POR 0x00000000 +#define PHYA_PCSS_PCSS_ECO_L__PCSS_ECO_0___POR 0x00000000 +#define PHYA_PCSS_PCSS_ECO_L__PCSS_ECO_0___M 0xFFFFFFFF +#define PHYA_PCSS_PCSS_ECO_L__PCSS_ECO_0___S 0 +#define PHYA_PCSS_PCSS_ECO_L___M 0xFFFFFFFF +#define PHYA_PCSS_PCSS_ECO_L___S 0 + +#define PHYA_PCSS_PCSS_ECO_U (0x00380114) +#define PHYA_PCSS_PCSS_ECO_U___RWC QCSR_REG_RW +#define PHYA_PCSS_PCSS_ECO_U___POR 0x00000000 +#define PHYA_PCSS_PCSS_ECO_U__PCSS_ECO_1___POR 0x00000000 +#define PHYA_PCSS_PCSS_ECO_U__PCSS_ECO_1___M 0xFFFFFFFF +#define PHYA_PCSS_PCSS_ECO_U__PCSS_ECO_1___S 0 +#define PHYA_PCSS_PCSS_ECO_U___M 0xFFFFFFFF +#define PHYA_PCSS_PCSS_ECO_U___S 0 + +#define PHYA_PCSS_AXI_SLAVE_TIMEOUT_STATUS_L (0x00380118) +#define PHYA_PCSS_AXI_SLAVE_TIMEOUT_STATUS_L___RWC QCSR_REG_RW +#define PHYA_PCSS_AXI_SLAVE_TIMEOUT_STATUS_L___POR 0x00000000 +#define PHYA_PCSS_AXI_SLAVE_TIMEOUT_STATUS_L__AXI_SLAVE_TIMEOUT_STATUS___POR 0x00 +#define PHYA_PCSS_AXI_SLAVE_TIMEOUT_STATUS_L__AXI_SLAVE_TIMEOUT_STATUS___M 0x000000FF +#define PHYA_PCSS_AXI_SLAVE_TIMEOUT_STATUS_L__AXI_SLAVE_TIMEOUT_STATUS___S 0 +#define PHYA_PCSS_AXI_SLAVE_TIMEOUT_STATUS_L___M 0x000000FF +#define PHYA_PCSS_AXI_SLAVE_TIMEOUT_STATUS_L___S 0 + +#define PHYA_PCSS_AXI_SLAVE_TIMEOUT_ENABLE_L (0x00380120) +#define PHYA_PCSS_AXI_SLAVE_TIMEOUT_ENABLE_L___RWC QCSR_REG_RW +#define PHYA_PCSS_AXI_SLAVE_TIMEOUT_ENABLE_L___POR 0x00000000 +#define PHYA_PCSS_AXI_SLAVE_TIMEOUT_ENABLE_L__AXI_SLAVE_TIMEOUT_ENABLE___POR 0x00 +#define PHYA_PCSS_AXI_SLAVE_TIMEOUT_ENABLE_L__AXI_SLAVE_TIMEOUT_ENABLE___M 0x000000FF +#define PHYA_PCSS_AXI_SLAVE_TIMEOUT_ENABLE_L__AXI_SLAVE_TIMEOUT_ENABLE___S 0 +#define PHYA_PCSS_AXI_SLAVE_TIMEOUT_ENABLE_L___M 0x000000FF +#define PHYA_PCSS_AXI_SLAVE_TIMEOUT_ENABLE_L___S 0 + +#define PHYA_PCSS_TIMEOUT_DEBUG0_L (0x00380128) +#define PHYA_PCSS_TIMEOUT_DEBUG0_L___RWC QCSR_REG_RW +#define PHYA_PCSS_TIMEOUT_DEBUG0_L___POR 0x00000000 +#define PHYA_PCSS_TIMEOUT_DEBUG0_L__TIMEOUT_VALUE_0___POR 0x0000 +#define PHYA_PCSS_TIMEOUT_DEBUG0_L__INTERRUPT_INDEX_0___POR 0x00 +#define PHYA_PCSS_TIMEOUT_DEBUG0_L__TIMEOUT_VALUE_0___M 0x00FFFF00 +#define PHYA_PCSS_TIMEOUT_DEBUG0_L__TIMEOUT_VALUE_0___S 8 +#define PHYA_PCSS_TIMEOUT_DEBUG0_L__INTERRUPT_INDEX_0___M 0x000000FF +#define PHYA_PCSS_TIMEOUT_DEBUG0_L__INTERRUPT_INDEX_0___S 0 +#define PHYA_PCSS_TIMEOUT_DEBUG0_L___M 0x00FFFFFF +#define PHYA_PCSS_TIMEOUT_DEBUG0_L___S 0 + +#define PHYA_PCSS_TIMEOUT_DEBUG0_U (0x0038012C) +#define PHYA_PCSS_TIMEOUT_DEBUG0_U___RWC QCSR_REG_RW +#define PHYA_PCSS_TIMEOUT_DEBUG0_U___POR 0x00040000 +#define PHYA_PCSS_TIMEOUT_DEBUG0_U__TIMEOUT_MASK_0___POR 0x1 +#define PHYA_PCSS_TIMEOUT_DEBUG0_U__TIMEOUT_ERROR_0___POR 0x0 +#define PHYA_PCSS_TIMEOUT_DEBUG0_U__TIMEOUT_STATUS_0___POR 0x0 +#define PHYA_PCSS_TIMEOUT_DEBUG0_U__TIMEOUT_COUNT_0___POR 0x0000 +#define PHYA_PCSS_TIMEOUT_DEBUG0_U__TIMEOUT_MASK_0___M 0x00040000 +#define PHYA_PCSS_TIMEOUT_DEBUG0_U__TIMEOUT_MASK_0___S 18 +#define PHYA_PCSS_TIMEOUT_DEBUG0_U__TIMEOUT_ERROR_0___M 0x00020000 +#define PHYA_PCSS_TIMEOUT_DEBUG0_U__TIMEOUT_ERROR_0___S 17 +#define PHYA_PCSS_TIMEOUT_DEBUG0_U__TIMEOUT_STATUS_0___M 0x00010000 +#define PHYA_PCSS_TIMEOUT_DEBUG0_U__TIMEOUT_STATUS_0___S 16 +#define PHYA_PCSS_TIMEOUT_DEBUG0_U__TIMEOUT_COUNT_0___M 0x0000FFFF +#define PHYA_PCSS_TIMEOUT_DEBUG0_U__TIMEOUT_COUNT_0___S 0 +#define PHYA_PCSS_TIMEOUT_DEBUG0_U___M 0x0007FFFF +#define PHYA_PCSS_TIMEOUT_DEBUG0_U___S 0 + +#define PHYA_PCSS_TIMEOUT_DEBUG1_L (0x00380130) +#define PHYA_PCSS_TIMEOUT_DEBUG1_L___RWC QCSR_REG_RW +#define PHYA_PCSS_TIMEOUT_DEBUG1_L___POR 0x00000000 +#define PHYA_PCSS_TIMEOUT_DEBUG1_L__TIMEOUT_VALUE_1___POR 0x0000 +#define PHYA_PCSS_TIMEOUT_DEBUG1_L__INTERRUPT_INDEX_1___POR 0x00 +#define PHYA_PCSS_TIMEOUT_DEBUG1_L__TIMEOUT_VALUE_1___M 0x00FFFF00 +#define PHYA_PCSS_TIMEOUT_DEBUG1_L__TIMEOUT_VALUE_1___S 8 +#define PHYA_PCSS_TIMEOUT_DEBUG1_L__INTERRUPT_INDEX_1___M 0x000000FF +#define PHYA_PCSS_TIMEOUT_DEBUG1_L__INTERRUPT_INDEX_1___S 0 +#define PHYA_PCSS_TIMEOUT_DEBUG1_L___M 0x00FFFFFF +#define PHYA_PCSS_TIMEOUT_DEBUG1_L___S 0 + +#define PHYA_PCSS_TIMEOUT_DEBUG1_U (0x00380134) +#define PHYA_PCSS_TIMEOUT_DEBUG1_U___RWC QCSR_REG_RW +#define PHYA_PCSS_TIMEOUT_DEBUG1_U___POR 0x00040000 +#define PHYA_PCSS_TIMEOUT_DEBUG1_U__TIMEOUT_MASK_1___POR 0x1 +#define PHYA_PCSS_TIMEOUT_DEBUG1_U__TIMEOUT_ERROR_1___POR 0x0 +#define PHYA_PCSS_TIMEOUT_DEBUG1_U__TIMEOUT_STATUS_1___POR 0x0 +#define PHYA_PCSS_TIMEOUT_DEBUG1_U__TIMEOUT_COUNT_1___POR 0x0000 +#define PHYA_PCSS_TIMEOUT_DEBUG1_U__TIMEOUT_MASK_1___M 0x00040000 +#define PHYA_PCSS_TIMEOUT_DEBUG1_U__TIMEOUT_MASK_1___S 18 +#define PHYA_PCSS_TIMEOUT_DEBUG1_U__TIMEOUT_ERROR_1___M 0x00020000 +#define PHYA_PCSS_TIMEOUT_DEBUG1_U__TIMEOUT_ERROR_1___S 17 +#define PHYA_PCSS_TIMEOUT_DEBUG1_U__TIMEOUT_STATUS_1___M 0x00010000 +#define PHYA_PCSS_TIMEOUT_DEBUG1_U__TIMEOUT_STATUS_1___S 16 +#define PHYA_PCSS_TIMEOUT_DEBUG1_U__TIMEOUT_COUNT_1___M 0x0000FFFF +#define PHYA_PCSS_TIMEOUT_DEBUG1_U__TIMEOUT_COUNT_1___S 0 +#define PHYA_PCSS_TIMEOUT_DEBUG1_U___M 0x0007FFFF +#define PHYA_PCSS_TIMEOUT_DEBUG1_U___S 0 + +#define PHYA_PCSS_TIMEOUT_DEBUG2_L (0x00380138) +#define PHYA_PCSS_TIMEOUT_DEBUG2_L___RWC QCSR_REG_RW +#define PHYA_PCSS_TIMEOUT_DEBUG2_L___POR 0x00000000 +#define PHYA_PCSS_TIMEOUT_DEBUG2_L__TIMEOUT_VALUE_2___POR 0x0000 +#define PHYA_PCSS_TIMEOUT_DEBUG2_L__INTERRUPT_INDEX_2___POR 0x00 +#define PHYA_PCSS_TIMEOUT_DEBUG2_L__TIMEOUT_VALUE_2___M 0x00FFFF00 +#define PHYA_PCSS_TIMEOUT_DEBUG2_L__TIMEOUT_VALUE_2___S 8 +#define PHYA_PCSS_TIMEOUT_DEBUG2_L__INTERRUPT_INDEX_2___M 0x000000FF +#define PHYA_PCSS_TIMEOUT_DEBUG2_L__INTERRUPT_INDEX_2___S 0 +#define PHYA_PCSS_TIMEOUT_DEBUG2_L___M 0x00FFFFFF +#define PHYA_PCSS_TIMEOUT_DEBUG2_L___S 0 + +#define PHYA_PCSS_TIMEOUT_DEBUG2_U (0x0038013C) +#define PHYA_PCSS_TIMEOUT_DEBUG2_U___RWC QCSR_REG_RW +#define PHYA_PCSS_TIMEOUT_DEBUG2_U___POR 0x00040000 +#define PHYA_PCSS_TIMEOUT_DEBUG2_U__TIMEOUT_MASK_2___POR 0x1 +#define PHYA_PCSS_TIMEOUT_DEBUG2_U__TIMEOUT_ERROR_2___POR 0x0 +#define PHYA_PCSS_TIMEOUT_DEBUG2_U__TIMEOUT_STATUS_2___POR 0x0 +#define PHYA_PCSS_TIMEOUT_DEBUG2_U__TIMEOUT_COUNT_2___POR 0x0000 +#define PHYA_PCSS_TIMEOUT_DEBUG2_U__TIMEOUT_MASK_2___M 0x00040000 +#define PHYA_PCSS_TIMEOUT_DEBUG2_U__TIMEOUT_MASK_2___S 18 +#define PHYA_PCSS_TIMEOUT_DEBUG2_U__TIMEOUT_ERROR_2___M 0x00020000 +#define PHYA_PCSS_TIMEOUT_DEBUG2_U__TIMEOUT_ERROR_2___S 17 +#define PHYA_PCSS_TIMEOUT_DEBUG2_U__TIMEOUT_STATUS_2___M 0x00010000 +#define PHYA_PCSS_TIMEOUT_DEBUG2_U__TIMEOUT_STATUS_2___S 16 +#define PHYA_PCSS_TIMEOUT_DEBUG2_U__TIMEOUT_COUNT_2___M 0x0000FFFF +#define PHYA_PCSS_TIMEOUT_DEBUG2_U__TIMEOUT_COUNT_2___S 0 +#define PHYA_PCSS_TIMEOUT_DEBUG2_U___M 0x0007FFFF +#define PHYA_PCSS_TIMEOUT_DEBUG2_U___S 0 + +#define PHYA_PCSS_TIMEOUT_DEBUG3_L (0x00380140) +#define PHYA_PCSS_TIMEOUT_DEBUG3_L___RWC QCSR_REG_RW +#define PHYA_PCSS_TIMEOUT_DEBUG3_L___POR 0x00000000 +#define PHYA_PCSS_TIMEOUT_DEBUG3_L__TIMEOUT_VALUE_3___POR 0x0000 +#define PHYA_PCSS_TIMEOUT_DEBUG3_L__INTERRUPT_INDEX_3___POR 0x00 +#define PHYA_PCSS_TIMEOUT_DEBUG3_L__TIMEOUT_VALUE_3___M 0x00FFFF00 +#define PHYA_PCSS_TIMEOUT_DEBUG3_L__TIMEOUT_VALUE_3___S 8 +#define PHYA_PCSS_TIMEOUT_DEBUG3_L__INTERRUPT_INDEX_3___M 0x000000FF +#define PHYA_PCSS_TIMEOUT_DEBUG3_L__INTERRUPT_INDEX_3___S 0 +#define PHYA_PCSS_TIMEOUT_DEBUG3_L___M 0x00FFFFFF +#define PHYA_PCSS_TIMEOUT_DEBUG3_L___S 0 + +#define PHYA_PCSS_TIMEOUT_DEBUG3_U (0x00380144) +#define PHYA_PCSS_TIMEOUT_DEBUG3_U___RWC QCSR_REG_RW +#define PHYA_PCSS_TIMEOUT_DEBUG3_U___POR 0x00040000 +#define PHYA_PCSS_TIMEOUT_DEBUG3_U__TIMEOUT_MASK_3___POR 0x1 +#define PHYA_PCSS_TIMEOUT_DEBUG3_U__TIMEOUT_ERROR_3___POR 0x0 +#define PHYA_PCSS_TIMEOUT_DEBUG3_U__TIMEOUT_STATUS_3___POR 0x0 +#define PHYA_PCSS_TIMEOUT_DEBUG3_U__TIMEOUT_COUNT_3___POR 0x0000 +#define PHYA_PCSS_TIMEOUT_DEBUG3_U__TIMEOUT_MASK_3___M 0x00040000 +#define PHYA_PCSS_TIMEOUT_DEBUG3_U__TIMEOUT_MASK_3___S 18 +#define PHYA_PCSS_TIMEOUT_DEBUG3_U__TIMEOUT_ERROR_3___M 0x00020000 +#define PHYA_PCSS_TIMEOUT_DEBUG3_U__TIMEOUT_ERROR_3___S 17 +#define PHYA_PCSS_TIMEOUT_DEBUG3_U__TIMEOUT_STATUS_3___M 0x00010000 +#define PHYA_PCSS_TIMEOUT_DEBUG3_U__TIMEOUT_STATUS_3___S 16 +#define PHYA_PCSS_TIMEOUT_DEBUG3_U__TIMEOUT_COUNT_3___M 0x0000FFFF +#define PHYA_PCSS_TIMEOUT_DEBUG3_U__TIMEOUT_COUNT_3___S 0 +#define PHYA_PCSS_TIMEOUT_DEBUG3_U___M 0x0007FFFF +#define PHYA_PCSS_TIMEOUT_DEBUG3_U___S 0 + +#define PHYA_PCSS_TIMEOUT_DEBUG4_L (0x00380148) +#define PHYA_PCSS_TIMEOUT_DEBUG4_L___RWC QCSR_REG_RW +#define PHYA_PCSS_TIMEOUT_DEBUG4_L___POR 0x00000000 +#define PHYA_PCSS_TIMEOUT_DEBUG4_L__TIMEOUT_VALUE_4___POR 0x0000 +#define PHYA_PCSS_TIMEOUT_DEBUG4_L__INTERRUPT_INDEX_4___POR 0x00 +#define PHYA_PCSS_TIMEOUT_DEBUG4_L__TIMEOUT_VALUE_4___M 0x00FFFF00 +#define PHYA_PCSS_TIMEOUT_DEBUG4_L__TIMEOUT_VALUE_4___S 8 +#define PHYA_PCSS_TIMEOUT_DEBUG4_L__INTERRUPT_INDEX_4___M 0x000000FF +#define PHYA_PCSS_TIMEOUT_DEBUG4_L__INTERRUPT_INDEX_4___S 0 +#define PHYA_PCSS_TIMEOUT_DEBUG4_L___M 0x00FFFFFF +#define PHYA_PCSS_TIMEOUT_DEBUG4_L___S 0 + +#define PHYA_PCSS_TIMEOUT_DEBUG4_U (0x0038014C) +#define PHYA_PCSS_TIMEOUT_DEBUG4_U___RWC QCSR_REG_RW +#define PHYA_PCSS_TIMEOUT_DEBUG4_U___POR 0x00040000 +#define PHYA_PCSS_TIMEOUT_DEBUG4_U__TIMEOUT_MASK_4___POR 0x1 +#define PHYA_PCSS_TIMEOUT_DEBUG4_U__TIMEOUT_ERROR_4___POR 0x0 +#define PHYA_PCSS_TIMEOUT_DEBUG4_U__TIMEOUT_STATUS_4___POR 0x0 +#define PHYA_PCSS_TIMEOUT_DEBUG4_U__TIMEOUT_COUNT_4___POR 0x0000 +#define PHYA_PCSS_TIMEOUT_DEBUG4_U__TIMEOUT_MASK_4___M 0x00040000 +#define PHYA_PCSS_TIMEOUT_DEBUG4_U__TIMEOUT_MASK_4___S 18 +#define PHYA_PCSS_TIMEOUT_DEBUG4_U__TIMEOUT_ERROR_4___M 0x00020000 +#define PHYA_PCSS_TIMEOUT_DEBUG4_U__TIMEOUT_ERROR_4___S 17 +#define PHYA_PCSS_TIMEOUT_DEBUG4_U__TIMEOUT_STATUS_4___M 0x00010000 +#define PHYA_PCSS_TIMEOUT_DEBUG4_U__TIMEOUT_STATUS_4___S 16 +#define PHYA_PCSS_TIMEOUT_DEBUG4_U__TIMEOUT_COUNT_4___M 0x0000FFFF +#define PHYA_PCSS_TIMEOUT_DEBUG4_U__TIMEOUT_COUNT_4___S 0 +#define PHYA_PCSS_TIMEOUT_DEBUG4_U___M 0x0007FFFF +#define PHYA_PCSS_TIMEOUT_DEBUG4_U___S 0 + +#define PHYA_PCSS_TIMEOUT_DEBUG5_L (0x00380150) +#define PHYA_PCSS_TIMEOUT_DEBUG5_L___RWC QCSR_REG_RW +#define PHYA_PCSS_TIMEOUT_DEBUG5_L___POR 0x00000000 +#define PHYA_PCSS_TIMEOUT_DEBUG5_L__TIMEOUT_VALUE_5___POR 0x0000 +#define PHYA_PCSS_TIMEOUT_DEBUG5_L__INTERRUPT_INDEX_5___POR 0x00 +#define PHYA_PCSS_TIMEOUT_DEBUG5_L__TIMEOUT_VALUE_5___M 0x00FFFF00 +#define PHYA_PCSS_TIMEOUT_DEBUG5_L__TIMEOUT_VALUE_5___S 8 +#define PHYA_PCSS_TIMEOUT_DEBUG5_L__INTERRUPT_INDEX_5___M 0x000000FF +#define PHYA_PCSS_TIMEOUT_DEBUG5_L__INTERRUPT_INDEX_5___S 0 +#define PHYA_PCSS_TIMEOUT_DEBUG5_L___M 0x00FFFFFF +#define PHYA_PCSS_TIMEOUT_DEBUG5_L___S 0 + +#define PHYA_PCSS_TIMEOUT_DEBUG5_U (0x00380154) +#define PHYA_PCSS_TIMEOUT_DEBUG5_U___RWC QCSR_REG_RW +#define PHYA_PCSS_TIMEOUT_DEBUG5_U___POR 0x00040000 +#define PHYA_PCSS_TIMEOUT_DEBUG5_U__TIMEOUT_MASK_5___POR 0x1 +#define PHYA_PCSS_TIMEOUT_DEBUG5_U__TIMEOUT_ERROR_5___POR 0x0 +#define PHYA_PCSS_TIMEOUT_DEBUG5_U__TIMEOUT_STATUS_5___POR 0x0 +#define PHYA_PCSS_TIMEOUT_DEBUG5_U__TIMEOUT_COUNT_5___POR 0x0000 +#define PHYA_PCSS_TIMEOUT_DEBUG5_U__TIMEOUT_MASK_5___M 0x00040000 +#define PHYA_PCSS_TIMEOUT_DEBUG5_U__TIMEOUT_MASK_5___S 18 +#define PHYA_PCSS_TIMEOUT_DEBUG5_U__TIMEOUT_ERROR_5___M 0x00020000 +#define PHYA_PCSS_TIMEOUT_DEBUG5_U__TIMEOUT_ERROR_5___S 17 +#define PHYA_PCSS_TIMEOUT_DEBUG5_U__TIMEOUT_STATUS_5___M 0x00010000 +#define PHYA_PCSS_TIMEOUT_DEBUG5_U__TIMEOUT_STATUS_5___S 16 +#define PHYA_PCSS_TIMEOUT_DEBUG5_U__TIMEOUT_COUNT_5___M 0x0000FFFF +#define PHYA_PCSS_TIMEOUT_DEBUG5_U__TIMEOUT_COUNT_5___S 0 +#define PHYA_PCSS_TIMEOUT_DEBUG5_U___M 0x0007FFFF +#define PHYA_PCSS_TIMEOUT_DEBUG5_U___S 0 + +#define PHYA_PCSS_TIMEOUT_DEBUG6_L (0x00380158) +#define PHYA_PCSS_TIMEOUT_DEBUG6_L___RWC QCSR_REG_RW +#define PHYA_PCSS_TIMEOUT_DEBUG6_L___POR 0x00000000 +#define PHYA_PCSS_TIMEOUT_DEBUG6_L__TIMEOUT_VALUE_6___POR 0x0000 +#define PHYA_PCSS_TIMEOUT_DEBUG6_L__INTERRUPT_INDEX_6___POR 0x00 +#define PHYA_PCSS_TIMEOUT_DEBUG6_L__TIMEOUT_VALUE_6___M 0x00FFFF00 +#define PHYA_PCSS_TIMEOUT_DEBUG6_L__TIMEOUT_VALUE_6___S 8 +#define PHYA_PCSS_TIMEOUT_DEBUG6_L__INTERRUPT_INDEX_6___M 0x000000FF +#define PHYA_PCSS_TIMEOUT_DEBUG6_L__INTERRUPT_INDEX_6___S 0 +#define PHYA_PCSS_TIMEOUT_DEBUG6_L___M 0x00FFFFFF +#define PHYA_PCSS_TIMEOUT_DEBUG6_L___S 0 + +#define PHYA_PCSS_TIMEOUT_DEBUG6_U (0x0038015C) +#define PHYA_PCSS_TIMEOUT_DEBUG6_U___RWC QCSR_REG_RW +#define PHYA_PCSS_TIMEOUT_DEBUG6_U___POR 0x00040000 +#define PHYA_PCSS_TIMEOUT_DEBUG6_U__TIMEOUT_MASK_6___POR 0x1 +#define PHYA_PCSS_TIMEOUT_DEBUG6_U__TIMEOUT_ERROR_6___POR 0x0 +#define PHYA_PCSS_TIMEOUT_DEBUG6_U__TIMEOUT_STATUS_6___POR 0x0 +#define PHYA_PCSS_TIMEOUT_DEBUG6_U__TIMEOUT_COUNT_6___POR 0x0000 +#define PHYA_PCSS_TIMEOUT_DEBUG6_U__TIMEOUT_MASK_6___M 0x00040000 +#define PHYA_PCSS_TIMEOUT_DEBUG6_U__TIMEOUT_MASK_6___S 18 +#define PHYA_PCSS_TIMEOUT_DEBUG6_U__TIMEOUT_ERROR_6___M 0x00020000 +#define PHYA_PCSS_TIMEOUT_DEBUG6_U__TIMEOUT_ERROR_6___S 17 +#define PHYA_PCSS_TIMEOUT_DEBUG6_U__TIMEOUT_STATUS_6___M 0x00010000 +#define PHYA_PCSS_TIMEOUT_DEBUG6_U__TIMEOUT_STATUS_6___S 16 +#define PHYA_PCSS_TIMEOUT_DEBUG6_U__TIMEOUT_COUNT_6___M 0x0000FFFF +#define PHYA_PCSS_TIMEOUT_DEBUG6_U__TIMEOUT_COUNT_6___S 0 +#define PHYA_PCSS_TIMEOUT_DEBUG6_U___M 0x0007FFFF +#define PHYA_PCSS_TIMEOUT_DEBUG6_U___S 0 + +#define PHYA_PCSS_NOC_SLAVE_TIMEOUT_L (0x00380160) +#define PHYA_PCSS_NOC_SLAVE_TIMEOUT_L___RWC QCSR_REG_RW +#define PHYA_PCSS_NOC_SLAVE_TIMEOUT_L___POR 0x00010001 +#define PHYA_PCSS_NOC_SLAVE_TIMEOUT_L__NOC_PHY_SLV_TIMEOUT_CLK_EN___POR 0x1 +#define PHYA_PCSS_NOC_SLAVE_TIMEOUT_L__NOC_PHY_SLV_TIMEOUT_CLK_DIV___POR 0x0001 +#define PHYA_PCSS_NOC_SLAVE_TIMEOUT_L__NOC_PHY_SLV_TIMEOUT_CLK_EN___M 0x00010000 +#define PHYA_PCSS_NOC_SLAVE_TIMEOUT_L__NOC_PHY_SLV_TIMEOUT_CLK_EN___S 16 +#define PHYA_PCSS_NOC_SLAVE_TIMEOUT_L__NOC_PHY_SLV_TIMEOUT_CLK_DIV___M 0x0000FFFF +#define PHYA_PCSS_NOC_SLAVE_TIMEOUT_L__NOC_PHY_SLV_TIMEOUT_CLK_DIV___S 0 +#define PHYA_PCSS_NOC_SLAVE_TIMEOUT_L___M 0x0001FFFF +#define PHYA_PCSS_NOC_SLAVE_TIMEOUT_L___S 0 + +#define PHYA_PCSS_NOC_SLAVE_TIMEOUT_U (0x00380164) +#define PHYA_PCSS_NOC_SLAVE_TIMEOUT_U___RWC QCSR_REG_RW +#define PHYA_PCSS_NOC_SLAVE_TIMEOUT_U___POR 0x00010138 +#define PHYA_PCSS_NOC_SLAVE_TIMEOUT_U__NOC_UMAC_SLV_TIMEOUT_CLK_EN___POR 0x1 +#define PHYA_PCSS_NOC_SLAVE_TIMEOUT_U__NOC_UMAC_SLV_TIMEOUT_CLK_DIV___POR 0x0138 +#define PHYA_PCSS_NOC_SLAVE_TIMEOUT_U__NOC_UMAC_SLV_TIMEOUT_CLK_EN___M 0x00010000 +#define PHYA_PCSS_NOC_SLAVE_TIMEOUT_U__NOC_UMAC_SLV_TIMEOUT_CLK_EN___S 16 +#define PHYA_PCSS_NOC_SLAVE_TIMEOUT_U__NOC_UMAC_SLV_TIMEOUT_CLK_DIV___M 0x0000FFFF +#define PHYA_PCSS_NOC_SLAVE_TIMEOUT_U__NOC_UMAC_SLV_TIMEOUT_CLK_DIV___S 0 +#define PHYA_PCSS_NOC_SLAVE_TIMEOUT_U___M 0x0001FFFF +#define PHYA_PCSS_NOC_SLAVE_TIMEOUT_U___S 0 + +#define PHYA_PCSS_NOC_CFG_STS_0_L (0x00380168) +#define PHYA_PCSS_NOC_CFG_STS_0_L___RWC QCSR_REG_RW +#define PHYA_PCSS_NOC_CFG_STS_0_L___POR 0x01900028 +#define PHYA_PCSS_NOC_CFG_STS_0_L__NOC_BUS_REQ_RDY_EXT_TIMEOUT___POR 0x0190 +#define PHYA_PCSS_NOC_CFG_STS_0_L__NOC_BUS_REQ_RDY_INT_TIMEOUT___POR 0x0028 +#define PHYA_PCSS_NOC_CFG_STS_0_L__NOC_BUS_REQ_RDY_EXT_TIMEOUT___M 0xFFFF0000 +#define PHYA_PCSS_NOC_CFG_STS_0_L__NOC_BUS_REQ_RDY_EXT_TIMEOUT___S 16 +#define PHYA_PCSS_NOC_CFG_STS_0_L__NOC_BUS_REQ_RDY_INT_TIMEOUT___M 0x0000FFFF +#define PHYA_PCSS_NOC_CFG_STS_0_L__NOC_BUS_REQ_RDY_INT_TIMEOUT___S 0 +#define PHYA_PCSS_NOC_CFG_STS_0_L___M 0xFFFFFFFF +#define PHYA_PCSS_NOC_CFG_STS_0_L___S 0 + +#define PHYA_PCSS_NOC_CFG_STS_0_U (0x0038016C) +#define PHYA_PCSS_NOC_CFG_STS_0_U___RWC QCSR_REG_RW +#define PHYA_PCSS_NOC_CFG_STS_0_U___POR 0x00030014 +#define PHYA_PCSS_NOC_CFG_STS_0_U__NOC_STATUS_CLR___POR 0x0 +#define PHYA_PCSS_NOC_CFG_STS_0_U__NOC_AOOOWR_EN___POR 0x3 +#define PHYA_PCSS_NOC_CFG_STS_0_U__NOC_BUS_RESP_RDY_TIMEOUT___POR 0x0014 +#define PHYA_PCSS_NOC_CFG_STS_0_U__NOC_STATUS_CLR___M 0x01000000 +#define PHYA_PCSS_NOC_CFG_STS_0_U__NOC_STATUS_CLR___S 24 +#define PHYA_PCSS_NOC_CFG_STS_0_U__NOC_AOOOWR_EN___M 0x00030000 +#define PHYA_PCSS_NOC_CFG_STS_0_U__NOC_AOOOWR_EN___S 16 +#define PHYA_PCSS_NOC_CFG_STS_0_U__NOC_BUS_RESP_RDY_TIMEOUT___M 0x0000FFFF +#define PHYA_PCSS_NOC_CFG_STS_0_U__NOC_BUS_RESP_RDY_TIMEOUT___S 0 +#define PHYA_PCSS_NOC_CFG_STS_0_U___M 0x0103FFFF +#define PHYA_PCSS_NOC_CFG_STS_0_U___S 0 + +#define PHYA_PCSS_NOC_CFG_STS_1_L (0x00380170) +#define PHYA_PCSS_NOC_CFG_STS_1_L___RWC QCSR_REG_RO +#define PHYA_PCSS_NOC_CFG_STS_1_L___POR 0x00000000 +#define PHYA_PCSS_NOC_CFG_STS_1_L__NOC_SLAVE_PENDING_TRANS___POR 0x0000 +#define PHYA_PCSS_NOC_CFG_STS_1_L__NOC_MASTER_PENDING_TRANS___POR 0x0000 +#define PHYA_PCSS_NOC_CFG_STS_1_L__NOC_SLAVE_PENDING_TRANS___M 0xFFFF0000 +#define PHYA_PCSS_NOC_CFG_STS_1_L__NOC_SLAVE_PENDING_TRANS___S 16 +#define PHYA_PCSS_NOC_CFG_STS_1_L__NOC_MASTER_PENDING_TRANS___M 0x0000FFFF +#define PHYA_PCSS_NOC_CFG_STS_1_L__NOC_MASTER_PENDING_TRANS___S 0 +#define PHYA_PCSS_NOC_CFG_STS_1_L___M 0xFFFFFFFF +#define PHYA_PCSS_NOC_CFG_STS_1_L___S 0 + +#define PHYA_PCSS_NOC_CFG_STS_1_U (0x00380174) +#define PHYA_PCSS_NOC_CFG_STS_1_U___RWC QCSR_REG_RO +#define PHYA_PCSS_NOC_CFG_STS_1_U___POR 0x00000000 +#define PHYA_PCSS_NOC_CFG_STS_1_U__NOC_M3_NO_CLK_ACCESS___POR 0x0 +#define PHYA_PCSS_NOC_CFG_STS_1_U__NOC_M3_NO_CLK_ACCESS___M 0x00000001 +#define PHYA_PCSS_NOC_CFG_STS_1_U__NOC_M3_NO_CLK_ACCESS___S 0 +#define PHYA_PCSS_NOC_CFG_STS_1_U___M 0x00000001 +#define PHYA_PCSS_NOC_CFG_STS_1_U___S 0 + +#define PHYA_PCSS_NOC_CFG_STS_2_L (0x00380178) +#define PHYA_PCSS_NOC_CFG_STS_2_L___RWC QCSR_REG_RO +#define PHYA_PCSS_NOC_CFG_STS_2_L___POR 0x00000000 +#define PHYA_PCSS_NOC_CFG_STS_2_L__NOC_BUS_TIMEOUT_0___POR 0x00000000 +#define PHYA_PCSS_NOC_CFG_STS_2_L__NOC_BUS_TIMEOUT_0___M 0xFFFFFFFF +#define PHYA_PCSS_NOC_CFG_STS_2_L__NOC_BUS_TIMEOUT_0___S 0 +#define PHYA_PCSS_NOC_CFG_STS_2_L___M 0xFFFFFFFF +#define PHYA_PCSS_NOC_CFG_STS_2_L___S 0 + +#define PHYA_PCSS_NOC_CFG_STS_2_U (0x0038017C) +#define PHYA_PCSS_NOC_CFG_STS_2_U___RWC QCSR_REG_RO +#define PHYA_PCSS_NOC_CFG_STS_2_U___POR 0x00000000 +#define PHYA_PCSS_NOC_CFG_STS_2_U__NOC_BUS_TIMEOUT_1___POR 0x00000000 +#define PHYA_PCSS_NOC_CFG_STS_2_U__NOC_BUS_TIMEOUT_1___M 0xFFFFFFFF +#define PHYA_PCSS_NOC_CFG_STS_2_U__NOC_BUS_TIMEOUT_1___S 0 +#define PHYA_PCSS_NOC_CFG_STS_2_U___M 0xFFFFFFFF +#define PHYA_PCSS_NOC_CFG_STS_2_U___S 0 + +#define PHYA_PCSS_DMA_AXI_CTRL_L (0x00380180) +#define PHYA_PCSS_DMA_AXI_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMA_AXI_CTRL_L___POR 0x00000020 +#define PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_6___POR 0x0 +#define PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_5___POR 0x1 +#define PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_4___POR 0x0 +#define PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_3___POR 0x0 +#define PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_2___POR 0x0 +#define PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_1___POR 0x0 +#define PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_0___POR 0x0 +#define PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_6___M 0x00000040 +#define PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_6___S 6 +#define PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_5___M 0x00000020 +#define PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_5___S 5 +#define PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_4___M 0x00000010 +#define PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_4___S 4 +#define PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_3___M 0x00000008 +#define PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_3___S 3 +#define PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_2___M 0x00000004 +#define PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_2___S 2 +#define PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_1___M 0x00000002 +#define PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_1___S 1 +#define PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_0___M 0x00000001 +#define PHYA_PCSS_DMA_AXI_CTRL_L__DMA_AXI_RD_ACCESS_MODE_0___S 0 +#define PHYA_PCSS_DMA_AXI_CTRL_L___M 0x0000007F +#define PHYA_PCSS_DMA_AXI_CTRL_L___S 0 + +#define PHYA_PCSS_DUMMY_L (0x00380200) +#define PHYA_PCSS_DUMMY_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DUMMY_L___POR 0x00000000 +#define PHYA_PCSS_DUMMY_L__DUMMY___POR 0x0 +#define PHYA_PCSS_DUMMY_L__DUMMY___M 0x00000001 +#define PHYA_PCSS_DUMMY_L__DUMMY___S 0 +#define PHYA_PCSS_DUMMY_L___M 0x00000001 +#define PHYA_PCSS_DUMMY_L___S 0 + +#define PHYA_PCSS_DMAC0_TRIGGER_REG0_L (0x00380400) +#define PHYA_PCSS_DMAC0_TRIGGER_REG0_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_TRIGGER_REG0_L___POR 0x00000000 +#define PHYA_PCSS_DMAC0_TRIGGER_REG0_L__TRIGGER_0___POR 0x0 +#define PHYA_PCSS_DMAC0_TRIGGER_REG0_L__TRIGGER_0___M 0x00000001 +#define PHYA_PCSS_DMAC0_TRIGGER_REG0_L__TRIGGER_0___S 0 +#define PHYA_PCSS_DMAC0_TRIGGER_REG0_L___M 0x00000001 +#define PHYA_PCSS_DMAC0_TRIGGER_REG0_L___S 0 + +#define PHYA_PCSS_DMAC0_TRIGGER_REG1_L (0x00380408) +#define PHYA_PCSS_DMAC0_TRIGGER_REG1_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_TRIGGER_REG1_L___POR 0x00000000 +#define PHYA_PCSS_DMAC0_TRIGGER_REG1_L__TRIGGER_1___POR 0x0 +#define PHYA_PCSS_DMAC0_TRIGGER_REG1_L__TRIGGER_1___M 0x00000001 +#define PHYA_PCSS_DMAC0_TRIGGER_REG1_L__TRIGGER_1___S 0 +#define PHYA_PCSS_DMAC0_TRIGGER_REG1_L___M 0x00000001 +#define PHYA_PCSS_DMAC0_TRIGGER_REG1_L___S 0 + +#define PHYA_PCSS_DMAC0_TRIGGER_REG2_L (0x00380410) +#define PHYA_PCSS_DMAC0_TRIGGER_REG2_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_TRIGGER_REG2_L___POR 0x00000000 +#define PHYA_PCSS_DMAC0_TRIGGER_REG2_L__TRIGGER_2___POR 0x0 +#define PHYA_PCSS_DMAC0_TRIGGER_REG2_L__TRIGGER_2___M 0x00000001 +#define PHYA_PCSS_DMAC0_TRIGGER_REG2_L__TRIGGER_2___S 0 +#define PHYA_PCSS_DMAC0_TRIGGER_REG2_L___M 0x00000001 +#define PHYA_PCSS_DMAC0_TRIGGER_REG2_L___S 0 + +#define PHYA_PCSS_DMAC0_TRIGGER_REG3_L (0x00380418) +#define PHYA_PCSS_DMAC0_TRIGGER_REG3_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_TRIGGER_REG3_L___POR 0x00000000 +#define PHYA_PCSS_DMAC0_TRIGGER_REG3_L__TRIGGER_3___POR 0x0 +#define PHYA_PCSS_DMAC0_TRIGGER_REG3_L__TRIGGER_3___M 0x00000001 +#define PHYA_PCSS_DMAC0_TRIGGER_REG3_L__TRIGGER_3___S 0 +#define PHYA_PCSS_DMAC0_TRIGGER_REG3_L___M 0x00000001 +#define PHYA_PCSS_DMAC0_TRIGGER_REG3_L___S 0 + +#define PHYA_PCSS_DMAC0_TRIGGER_REG4_L (0x00380420) +#define PHYA_PCSS_DMAC0_TRIGGER_REG4_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_TRIGGER_REG4_L___POR 0x00000000 +#define PHYA_PCSS_DMAC0_TRIGGER_REG4_L__TRIGGER_4___POR 0x0 +#define PHYA_PCSS_DMAC0_TRIGGER_REG4_L__TRIGGER_4___M 0x00000001 +#define PHYA_PCSS_DMAC0_TRIGGER_REG4_L__TRIGGER_4___S 0 +#define PHYA_PCSS_DMAC0_TRIGGER_REG4_L___M 0x00000001 +#define PHYA_PCSS_DMAC0_TRIGGER_REG4_L___S 0 + +#define PHYA_PCSS_DMAC0_TRIGGER_REG5_L (0x00380428) +#define PHYA_PCSS_DMAC0_TRIGGER_REG5_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_TRIGGER_REG5_L___POR 0x00000000 +#define PHYA_PCSS_DMAC0_TRIGGER_REG5_L__TRIGGER_5___POR 0x0 +#define PHYA_PCSS_DMAC0_TRIGGER_REG5_L__TRIGGER_5___M 0x00000001 +#define PHYA_PCSS_DMAC0_TRIGGER_REG5_L__TRIGGER_5___S 0 +#define PHYA_PCSS_DMAC0_TRIGGER_REG5_L___M 0x00000001 +#define PHYA_PCSS_DMAC0_TRIGGER_REG5_L___S 0 + +#define PHYA_PCSS_DMAC0_TRIGGER_REG6_L (0x00380430) +#define PHYA_PCSS_DMAC0_TRIGGER_REG6_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_TRIGGER_REG6_L___POR 0x00000000 +#define PHYA_PCSS_DMAC0_TRIGGER_REG6_L__TRIGGER_6___POR 0x0 +#define PHYA_PCSS_DMAC0_TRIGGER_REG6_L__TRIGGER_6___M 0x00000001 +#define PHYA_PCSS_DMAC0_TRIGGER_REG6_L__TRIGGER_6___S 0 +#define PHYA_PCSS_DMAC0_TRIGGER_REG6_L___M 0x00000001 +#define PHYA_PCSS_DMAC0_TRIGGER_REG6_L___S 0 + +#define PHYA_PCSS_DMAC0_TRIGGER_REG7_L (0x00380438) +#define PHYA_PCSS_DMAC0_TRIGGER_REG7_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_TRIGGER_REG7_L___POR 0x00000000 +#define PHYA_PCSS_DMAC0_TRIGGER_REG7_L__TRIGGER_7___POR 0x0 +#define PHYA_PCSS_DMAC0_TRIGGER_REG7_L__TRIGGER_7___M 0x00000001 +#define PHYA_PCSS_DMAC0_TRIGGER_REG7_L__TRIGGER_7___S 0 +#define PHYA_PCSS_DMAC0_TRIGGER_REG7_L___M 0x00000001 +#define PHYA_PCSS_DMAC0_TRIGGER_REG7_L___S 0 + +#define PHYA_PCSS_DMAC0_DUMMY2_REG0_L (0x00380440) +#define PHYA_PCSS_DMAC0_DUMMY2_REG0_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DUMMY2_REG0_L___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DUMMY2_REG0_L__DUMMY2_0___POR 0x0 +#define PHYA_PCSS_DMAC0_DUMMY2_REG0_L__DUMMY2_0___M 0x00000001 +#define PHYA_PCSS_DMAC0_DUMMY2_REG0_L__DUMMY2_0___S 0 +#define PHYA_PCSS_DMAC0_DUMMY2_REG0_L___M 0x00000001 +#define PHYA_PCSS_DMAC0_DUMMY2_REG0_L___S 0 + +#define PHYA_PCSS_DMAC0_DUMMY2_REG1_L (0x00380448) +#define PHYA_PCSS_DMAC0_DUMMY2_REG1_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DUMMY2_REG1_L___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DUMMY2_REG1_L__DUMMY2_1___POR 0x0 +#define PHYA_PCSS_DMAC0_DUMMY2_REG1_L__DUMMY2_1___M 0x00000001 +#define PHYA_PCSS_DMAC0_DUMMY2_REG1_L__DUMMY2_1___S 0 +#define PHYA_PCSS_DMAC0_DUMMY2_REG1_L___M 0x00000001 +#define PHYA_PCSS_DMAC0_DUMMY2_REG1_L___S 0 + +#define PHYA_PCSS_DMAC0_DUMMY2_REG2_L (0x00380450) +#define PHYA_PCSS_DMAC0_DUMMY2_REG2_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DUMMY2_REG2_L___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DUMMY2_REG2_L__DUMMY2_2___POR 0x0 +#define PHYA_PCSS_DMAC0_DUMMY2_REG2_L__DUMMY2_2___M 0x00000001 +#define PHYA_PCSS_DMAC0_DUMMY2_REG2_L__DUMMY2_2___S 0 +#define PHYA_PCSS_DMAC0_DUMMY2_REG2_L___M 0x00000001 +#define PHYA_PCSS_DMAC0_DUMMY2_REG2_L___S 0 + +#define PHYA_PCSS_DMAC0_DUMMY2_REG3_L (0x00380458) +#define PHYA_PCSS_DMAC0_DUMMY2_REG3_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DUMMY2_REG3_L___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DUMMY2_REG3_L__DUMMY2_3___POR 0x0 +#define PHYA_PCSS_DMAC0_DUMMY2_REG3_L__DUMMY2_3___M 0x00000001 +#define PHYA_PCSS_DMAC0_DUMMY2_REG3_L__DUMMY2_3___S 0 +#define PHYA_PCSS_DMAC0_DUMMY2_REG3_L___M 0x00000001 +#define PHYA_PCSS_DMAC0_DUMMY2_REG3_L___S 0 + +#define PHYA_PCSS_DMAC0_DUMMY2_REG4_L (0x00380460) +#define PHYA_PCSS_DMAC0_DUMMY2_REG4_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DUMMY2_REG4_L___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DUMMY2_REG4_L__DUMMY2_4___POR 0x0 +#define PHYA_PCSS_DMAC0_DUMMY2_REG4_L__DUMMY2_4___M 0x00000001 +#define PHYA_PCSS_DMAC0_DUMMY2_REG4_L__DUMMY2_4___S 0 +#define PHYA_PCSS_DMAC0_DUMMY2_REG4_L___M 0x00000001 +#define PHYA_PCSS_DMAC0_DUMMY2_REG4_L___S 0 + +#define PHYA_PCSS_DMAC0_DUMMY2_REG5_L (0x00380468) +#define PHYA_PCSS_DMAC0_DUMMY2_REG5_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DUMMY2_REG5_L___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DUMMY2_REG5_L__DUMMY2_5___POR 0x0 +#define PHYA_PCSS_DMAC0_DUMMY2_REG5_L__DUMMY2_5___M 0x00000001 +#define PHYA_PCSS_DMAC0_DUMMY2_REG5_L__DUMMY2_5___S 0 +#define PHYA_PCSS_DMAC0_DUMMY2_REG5_L___M 0x00000001 +#define PHYA_PCSS_DMAC0_DUMMY2_REG5_L___S 0 + +#define PHYA_PCSS_DMAC0_DUMMY2_REG6_L (0x00380470) +#define PHYA_PCSS_DMAC0_DUMMY2_REG6_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DUMMY2_REG6_L___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DUMMY2_REG6_L__DUMMY2_6___POR 0x0 +#define PHYA_PCSS_DMAC0_DUMMY2_REG6_L__DUMMY2_6___M 0x00000001 +#define PHYA_PCSS_DMAC0_DUMMY2_REG6_L__DUMMY2_6___S 0 +#define PHYA_PCSS_DMAC0_DUMMY2_REG6_L___M 0x00000001 +#define PHYA_PCSS_DMAC0_DUMMY2_REG6_L___S 0 + +#define PHYA_PCSS_DMAC0_DUMMY2_REG7_L (0x00380478) +#define PHYA_PCSS_DMAC0_DUMMY2_REG7_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DUMMY2_REG7_L___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DUMMY2_REG7_L__DUMMY2_7___POR 0x0 +#define PHYA_PCSS_DMAC0_DUMMY2_REG7_L__DUMMY2_7___M 0x00000001 +#define PHYA_PCSS_DMAC0_DUMMY2_REG7_L__DUMMY2_7___S 0 +#define PHYA_PCSS_DMAC0_DUMMY2_REG7_L___M 0x00000001 +#define PHYA_PCSS_DMAC0_DUMMY2_REG7_L___S 0 + +#define PHYA_PCSS_DMAC0_DMA_CTRL_L (0x00380480) +#define PHYA_PCSS_DMAC0_DMA_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DMA_CTRL_L___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DMA_CTRL_L__DMAC_EN___POR 0x0 +#define PHYA_PCSS_DMAC0_DMA_CTRL_L__DMAC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC0_DMA_CTRL_L__DMAC_EN___S 0 +#define PHYA_PCSS_DMAC0_DMA_CTRL_L___M 0x00000001 +#define PHYA_PCSS_DMAC0_DMA_CTRL_L___S 0 + +#define PHYA_PCSS_DMAC0_DMA_CTRL_U (0x00380484) +#define PHYA_PCSS_DMAC0_DMA_CTRL_U___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DMA_CTRL_U___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DMA_CTRL_U__EVTI_XFER_STOP___POR 0x00 +#define PHYA_PCSS_DMAC0_DMA_CTRL_U__EVTI_XFER_STOP___M 0x0000003F +#define PHYA_PCSS_DMAC0_DMA_CTRL_U__EVTI_XFER_STOP___S 0 +#define PHYA_PCSS_DMAC0_DMA_CTRL_U___M 0x0000003F +#define PHYA_PCSS_DMAC0_DMA_CTRL_U___S 0 + +#define PHYA_PCSS_DMAC0_DMA_STATUS_0_L (0x00380488) +#define PHYA_PCSS_DMAC0_DMA_STATUS_0_L___RWC QCSR_REG_RO +#define PHYA_PCSS_DMAC0_DMA_STATUS_0_L___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DMA_STATUS_0_L__CTRL_FSM_STATE___POR 0x0 +#define PHYA_PCSS_DMAC0_DMA_STATUS_0_L__DESC_LAST___POR 0x0 +#define PHYA_PCSS_DMAC0_DMA_STATUS_0_L__DESC_ACTIVE___POR 0x0 +#define PHYA_PCSS_DMAC0_DMA_STATUS_0_L__DMAC_ACTIVE___POR 0x0 +#define PHYA_PCSS_DMAC0_DMA_STATUS_0_L__CTRL_FSM_STATE___M 0x0F000000 +#define PHYA_PCSS_DMAC0_DMA_STATUS_0_L__CTRL_FSM_STATE___S 24 +#define PHYA_PCSS_DMAC0_DMA_STATUS_0_L__DESC_LAST___M 0x000F0000 +#define PHYA_PCSS_DMAC0_DMA_STATUS_0_L__DESC_LAST___S 16 +#define PHYA_PCSS_DMAC0_DMA_STATUS_0_L__DESC_ACTIVE___M 0x00000F00 +#define PHYA_PCSS_DMAC0_DMA_STATUS_0_L__DESC_ACTIVE___S 8 +#define PHYA_PCSS_DMAC0_DMA_STATUS_0_L__DMAC_ACTIVE___M 0x00000001 +#define PHYA_PCSS_DMAC0_DMA_STATUS_0_L__DMAC_ACTIVE___S 0 +#define PHYA_PCSS_DMAC0_DMA_STATUS_0_L___M 0x0F0F0F01 +#define PHYA_PCSS_DMAC0_DMA_STATUS_0_L___S 0 + +#define PHYA_PCSS_DMAC0_DMA_STATUS_0_U (0x0038048C) +#define PHYA_PCSS_DMAC0_DMA_STATUS_0_U___RWC QCSR_REG_RO +#define PHYA_PCSS_DMAC0_DMA_STATUS_0_U___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DMA_STATUS_0_U__XFER_FIFO_OCC___POR 0x000 +#define PHYA_PCSS_DMAC0_DMA_STATUS_0_U__ALEN_FIFO_OCC___POR 0x0 +#define PHYA_PCSS_DMAC0_DMA_STATUS_0_U__DP_FSM_STATE___POR 0x0 +#define PHYA_PCSS_DMAC0_DMA_STATUS_0_U__XFER_FIFO_OCC___M 0x01FF0000 +#define PHYA_PCSS_DMAC0_DMA_STATUS_0_U__XFER_FIFO_OCC___S 16 +#define PHYA_PCSS_DMAC0_DMA_STATUS_0_U__ALEN_FIFO_OCC___M 0x00000F00 +#define PHYA_PCSS_DMAC0_DMA_STATUS_0_U__ALEN_FIFO_OCC___S 8 +#define PHYA_PCSS_DMAC0_DMA_STATUS_0_U__DP_FSM_STATE___M 0x0000000F +#define PHYA_PCSS_DMAC0_DMA_STATUS_0_U__DP_FSM_STATE___S 0 +#define PHYA_PCSS_DMAC0_DMA_STATUS_0_U___M 0x01FF0F0F +#define PHYA_PCSS_DMAC0_DMA_STATUS_0_U___S 0 + +#define PHYA_PCSS_DMAC0_DMA_STATUS_1_L (0x00380490) +#define PHYA_PCSS_DMAC0_DMA_STATUS_1_L___RWC QCSR_REG_RO +#define PHYA_PCSS_DMAC0_DMA_STATUS_1_L___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DMA_STATUS_1_L__XFER_LEN_PEND___POR 0x000000 +#define PHYA_PCSS_DMAC0_DMA_STATUS_1_L__XFER_LEN_PEND___M 0x00FFFFFF +#define PHYA_PCSS_DMAC0_DMA_STATUS_1_L__XFER_LEN_PEND___S 0 +#define PHYA_PCSS_DMAC0_DMA_STATUS_1_L___M 0x00FFFFFF +#define PHYA_PCSS_DMAC0_DMA_STATUS_1_L___S 0 + +#define PHYA_PCSS_DMAC0_DMA_EVT_LATCH_L (0x00380498) +#define PHYA_PCSS_DMAC0_DMA_EVT_LATCH_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DMA_EVT_LATCH_L___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___S 0 +#define PHYA_PCSS_DMAC0_DMA_EVT_LATCH_L___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DMA_EVT_LATCH_L___S 0 + +#define PHYA_PCSS_DMAC0_DMA_EVT_LATCH_U (0x0038049C) +#define PHYA_PCSS_DMAC0_DMA_EVT_LATCH_U___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DMA_EVT_LATCH_U___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___S 0 +#define PHYA_PCSS_DMAC0_DMA_EVT_LATCH_U___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DMA_EVT_LATCH_U___S 0 + +#define PHYA_PCSS_DMAC0_DMA_EVT_TRIG_L (0x003804A0) +#define PHYA_PCSS_DMAC0_DMA_EVT_TRIG_L___RWC QCSR_REG_RO +#define PHYA_PCSS_DMAC0_DMA_EVT_TRIG_L___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DMA_EVT_TRIG_L__CUR_EVT_TRIG___POR 0x00 +#define PHYA_PCSS_DMAC0_DMA_EVT_TRIG_L__LAST_EVT_TRIG___POR 0x00 +#define PHYA_PCSS_DMAC0_DMA_EVT_TRIG_L__CUR_EVT_TRIG___M 0x0000FF00 +#define PHYA_PCSS_DMAC0_DMA_EVT_TRIG_L__CUR_EVT_TRIG___S 8 +#define PHYA_PCSS_DMAC0_DMA_EVT_TRIG_L__LAST_EVT_TRIG___M 0x000000FF +#define PHYA_PCSS_DMAC0_DMA_EVT_TRIG_L__LAST_EVT_TRIG___S 0 +#define PHYA_PCSS_DMAC0_DMA_EVT_TRIG_L___M 0x0000FFFF +#define PHYA_PCSS_DMAC0_DMA_EVT_TRIG_L___S 0 + +#define PHYA_PCSS_DMAC0_DMA_XFER_CTRL_L (0x003804A8) +#define PHYA_PCSS_DMAC0_DMA_XFER_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DMA_XFER_CTRL_L___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___POR 0x0 +#define PHYA_PCSS_DMAC0_DMA_XFER_CTRL_L__PAUSE_XFER___POR 0x0 +#define PHYA_PCSS_DMAC0_DMA_XFER_CTRL_L__STOP_XFER_MASK___POR 0x00 +#define PHYA_PCSS_DMAC0_DMA_XFER_CTRL_L__STOP_XFER___POR 0x0 +#define PHYA_PCSS_DMAC0_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___M 0x00040000 +#define PHYA_PCSS_DMAC0_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___S 18 +#define PHYA_PCSS_DMAC0_DMA_XFER_CTRL_L__PAUSE_XFER___M 0x00020000 +#define PHYA_PCSS_DMAC0_DMA_XFER_CTRL_L__PAUSE_XFER___S 17 +#define PHYA_PCSS_DMAC0_DMA_XFER_CTRL_L__STOP_XFER_MASK___M 0x000001FE +#define PHYA_PCSS_DMAC0_DMA_XFER_CTRL_L__STOP_XFER_MASK___S 1 +#define PHYA_PCSS_DMAC0_DMA_XFER_CTRL_L__STOP_XFER___M 0x00000001 +#define PHYA_PCSS_DMAC0_DMA_XFER_CTRL_L__STOP_XFER___S 0 +#define PHYA_PCSS_DMAC0_DMA_XFER_CTRL_L___M 0x000601FF +#define PHYA_PCSS_DMAC0_DMA_XFER_CTRL_L___S 0 + +#define PHYA_PCSS_DMAC0_DMA_SPARE_L (0x003804B0) +#define PHYA_PCSS_DMAC0_DMA_SPARE_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DMA_SPARE_L___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DMA_SPARE_L__DMA_SPARE_0___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DMA_SPARE_L__DMA_SPARE_0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DMA_SPARE_L__DMA_SPARE_0___S 0 +#define PHYA_PCSS_DMAC0_DMA_SPARE_L___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DMA_SPARE_L___S 0 + +#define PHYA_PCSS_DMAC0_DMA_SPARE_U (0x003804B4) +#define PHYA_PCSS_DMAC0_DMA_SPARE_U___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DMA_SPARE_U___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DMA_SPARE_U__DMA_SPARE_1___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DMA_SPARE_U__DMA_SPARE_1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DMA_SPARE_U__DMA_SPARE_1___S 0 +#define PHYA_PCSS_DMAC0_DMA_SPARE_U___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DMA_SPARE_U___S 0 + +#define PHYA_PCSS_DMAC0_DMA_ECO_L (0x003804B8) +#define PHYA_PCSS_DMAC0_DMA_ECO_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DMA_ECO_L___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DMA_ECO_L__DMA_ECO_0___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DMA_ECO_L__DMA_ECO_0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DMA_ECO_L__DMA_ECO_0___S 0 +#define PHYA_PCSS_DMAC0_DMA_ECO_L___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DMA_ECO_L___S 0 + +#define PHYA_PCSS_DMAC0_DMA_ECO_U (0x003804BC) +#define PHYA_PCSS_DMAC0_DMA_ECO_U___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DMA_ECO_U___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DMA_ECO_U__DMA_ECO_1___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DMA_ECO_U__DMA_ECO_1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DMA_ECO_U__DMA_ECO_1___S 0 +#define PHYA_PCSS_DMAC0_DMA_ECO_U___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DMA_ECO_U___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B0 (0x003804C0) +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B0__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B0__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B0__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B0___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B1 (0x003804D8) +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B1__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B1__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B1__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B1___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B2 (0x003804F0) +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B2__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B2__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B2__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B2___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B3 (0x00380508) +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B3__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B3__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B3__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B3___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B4 (0x00380520) +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B4__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B4__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B4__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B4___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B5 (0x00380538) +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B5__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B5__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B5__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B5___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B6 (0x00380550) +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B6__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B6__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B6__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B6___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B7 (0x00380568) +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B7__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B7__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B7__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_0_L_B7___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B0 (0x003804C4) +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B0__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B0__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B0__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B0__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B0__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B0__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B0___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B1 (0x003804DC) +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B1__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B1__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B1__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B1__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B1__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B1__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B1___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B2 (0x003804F4) +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B2__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B2__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B2__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B2__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B2__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B2__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B2___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B3 (0x0038050C) +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B3__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B3__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B3__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B3__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B3__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B3__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B3___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B4 (0x00380524) +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B4__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B4__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B4__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B4__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B4__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B4__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B4___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B5 (0x0038053C) +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B5__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B5__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B5__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B5__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B5__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B5__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B5___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B6 (0x00380554) +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B6__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B6__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B6__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B6__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B6__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B6__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B6___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B7 (0x0038056C) +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B7__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B7__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B7__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B7__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B7__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B7__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_0_U_B7___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B0 (0x003804C8) +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B0__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B0__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B0__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B0___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B1 (0x003804E0) +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B1__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B1__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B1__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B1___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B2 (0x003804F8) +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B2__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B2__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B2__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B2___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B3 (0x00380510) +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B3__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B3__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B3__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B3___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B4 (0x00380528) +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B4__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B4__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B4__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B4___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B5 (0x00380540) +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B5__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B5__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B5__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B5___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B6 (0x00380558) +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B6__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B6__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B6__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B6___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B7 (0x00380570) +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B7__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B7__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B7__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_1_L_B7___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B0 (0x003804CC) +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B0__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B0__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B0__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B0___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B1 (0x003804E4) +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B1__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B1__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B1__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B1___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B2 (0x003804FC) +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B2__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B2__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B2__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B2___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B3 (0x00380514) +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B3__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B3__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B3__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B3___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B4 (0x0038052C) +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B4__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B4__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B4__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B4___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B5 (0x00380544) +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B5__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B5__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B5__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B5___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B6 (0x0038055C) +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B6__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B6__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B6__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B6___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B7 (0x00380574) +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B7__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B7__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B7__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_1_U_B7___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B0 (0x003804D0) +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B0__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B0__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B0__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B0___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B1 (0x003804E8) +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B1__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B1__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B1__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B1___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B2 (0x00380500) +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B2__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B2__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B2__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B2___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B3 (0x00380518) +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B3__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B3__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B3__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B3___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B4 (0x00380530) +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B4__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B4__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B4__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B4___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B5 (0x00380548) +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B5__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B5__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B5__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B5___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B6 (0x00380560) +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B6__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B6__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B6__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B6___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B7 (0x00380578) +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B7__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B7__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B7__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_2_L_B7___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0 (0x003804D4) +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__FRZDST___S 6 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__FRZSRC___S 5 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__DATSRC___S 2 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0__DESC_EN___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B0___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1 (0x003804EC) +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__FRZDST___S 6 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__FRZSRC___S 5 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__DATSRC___S 2 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1__DESC_EN___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B1___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2 (0x00380504) +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__FRZDST___S 6 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__FRZSRC___S 5 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__DATSRC___S 2 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2__DESC_EN___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B2___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3 (0x0038051C) +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__FRZDST___S 6 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__FRZSRC___S 5 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__DATSRC___S 2 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3__DESC_EN___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B3___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4 (0x00380534) +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__FRZDST___S 6 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__FRZSRC___S 5 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__DATSRC___S 2 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4__DESC_EN___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B4___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5 (0x0038054C) +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__FRZDST___S 6 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__FRZSRC___S 5 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__DATSRC___S 2 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5__DESC_EN___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B5___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6 (0x00380564) +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__FRZDST___S 6 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__FRZSRC___S 5 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__DATSRC___S 2 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6__DESC_EN___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B6___S 0 + +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7 (0x0038057C) +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__FRZDST___S 6 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__FRZSRC___S 5 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__DATSRC___S 2 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7__DESC_EN___S 0 +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC0_DESC_REG_2_U_B7___S 0 + +#define PHYA_PCSS_DMAC0_DMAC2PHYDBG_EN_REG_L (0x00380580) +#define PHYA_PCSS_DMAC0_DMAC2PHYDBG_EN_REG_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DMAC2PHYDBG_EN_REG_L___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___POR 0x00 +#define PHYA_PCSS_DMAC0_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___M 0x000000FF +#define PHYA_PCSS_DMAC0_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___S 0 +#define PHYA_PCSS_DMAC0_DMAC2PHYDBG_EN_REG_L___M 0x000000FF +#define PHYA_PCSS_DMAC0_DMAC2PHYDBG_EN_REG_L___S 0 + +#define PHYA_PCSS_DMAC0_DUMMY_L (0x00380648) +#define PHYA_PCSS_DMAC0_DUMMY_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC0_DUMMY_L___POR 0x00000000 +#define PHYA_PCSS_DMAC0_DUMMY_L__DUMMY___POR 0x0 +#define PHYA_PCSS_DMAC0_DUMMY_L__DUMMY___M 0x00000001 +#define PHYA_PCSS_DMAC0_DUMMY_L__DUMMY___S 0 +#define PHYA_PCSS_DMAC0_DUMMY_L___M 0x00000001 +#define PHYA_PCSS_DMAC0_DUMMY_L___S 0 + +#define PHYA_PCSS_DMAC1_TRIGGER_REG0_L (0x00380800) +#define PHYA_PCSS_DMAC1_TRIGGER_REG0_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_TRIGGER_REG0_L___POR 0x00000000 +#define PHYA_PCSS_DMAC1_TRIGGER_REG0_L__TRIGGER_0___POR 0x0 +#define PHYA_PCSS_DMAC1_TRIGGER_REG0_L__TRIGGER_0___M 0x00000001 +#define PHYA_PCSS_DMAC1_TRIGGER_REG0_L__TRIGGER_0___S 0 +#define PHYA_PCSS_DMAC1_TRIGGER_REG0_L___M 0x00000001 +#define PHYA_PCSS_DMAC1_TRIGGER_REG0_L___S 0 + +#define PHYA_PCSS_DMAC1_TRIGGER_REG1_L (0x00380808) +#define PHYA_PCSS_DMAC1_TRIGGER_REG1_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_TRIGGER_REG1_L___POR 0x00000000 +#define PHYA_PCSS_DMAC1_TRIGGER_REG1_L__TRIGGER_1___POR 0x0 +#define PHYA_PCSS_DMAC1_TRIGGER_REG1_L__TRIGGER_1___M 0x00000001 +#define PHYA_PCSS_DMAC1_TRIGGER_REG1_L__TRIGGER_1___S 0 +#define PHYA_PCSS_DMAC1_TRIGGER_REG1_L___M 0x00000001 +#define PHYA_PCSS_DMAC1_TRIGGER_REG1_L___S 0 + +#define PHYA_PCSS_DMAC1_TRIGGER_REG2_L (0x00380810) +#define PHYA_PCSS_DMAC1_TRIGGER_REG2_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_TRIGGER_REG2_L___POR 0x00000000 +#define PHYA_PCSS_DMAC1_TRIGGER_REG2_L__TRIGGER_2___POR 0x0 +#define PHYA_PCSS_DMAC1_TRIGGER_REG2_L__TRIGGER_2___M 0x00000001 +#define PHYA_PCSS_DMAC1_TRIGGER_REG2_L__TRIGGER_2___S 0 +#define PHYA_PCSS_DMAC1_TRIGGER_REG2_L___M 0x00000001 +#define PHYA_PCSS_DMAC1_TRIGGER_REG2_L___S 0 + +#define PHYA_PCSS_DMAC1_TRIGGER_REG3_L (0x00380818) +#define PHYA_PCSS_DMAC1_TRIGGER_REG3_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_TRIGGER_REG3_L___POR 0x00000000 +#define PHYA_PCSS_DMAC1_TRIGGER_REG3_L__TRIGGER_3___POR 0x0 +#define PHYA_PCSS_DMAC1_TRIGGER_REG3_L__TRIGGER_3___M 0x00000001 +#define PHYA_PCSS_DMAC1_TRIGGER_REG3_L__TRIGGER_3___S 0 +#define PHYA_PCSS_DMAC1_TRIGGER_REG3_L___M 0x00000001 +#define PHYA_PCSS_DMAC1_TRIGGER_REG3_L___S 0 + +#define PHYA_PCSS_DMAC1_TRIGGER_REG4_L (0x00380820) +#define PHYA_PCSS_DMAC1_TRIGGER_REG4_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_TRIGGER_REG4_L___POR 0x00000000 +#define PHYA_PCSS_DMAC1_TRIGGER_REG4_L__TRIGGER_4___POR 0x0 +#define PHYA_PCSS_DMAC1_TRIGGER_REG4_L__TRIGGER_4___M 0x00000001 +#define PHYA_PCSS_DMAC1_TRIGGER_REG4_L__TRIGGER_4___S 0 +#define PHYA_PCSS_DMAC1_TRIGGER_REG4_L___M 0x00000001 +#define PHYA_PCSS_DMAC1_TRIGGER_REG4_L___S 0 + +#define PHYA_PCSS_DMAC1_TRIGGER_REG5_L (0x00380828) +#define PHYA_PCSS_DMAC1_TRIGGER_REG5_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_TRIGGER_REG5_L___POR 0x00000000 +#define PHYA_PCSS_DMAC1_TRIGGER_REG5_L__TRIGGER_5___POR 0x0 +#define PHYA_PCSS_DMAC1_TRIGGER_REG5_L__TRIGGER_5___M 0x00000001 +#define PHYA_PCSS_DMAC1_TRIGGER_REG5_L__TRIGGER_5___S 0 +#define PHYA_PCSS_DMAC1_TRIGGER_REG5_L___M 0x00000001 +#define PHYA_PCSS_DMAC1_TRIGGER_REG5_L___S 0 + +#define PHYA_PCSS_DMAC1_TRIGGER_REG6_L (0x00380830) +#define PHYA_PCSS_DMAC1_TRIGGER_REG6_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_TRIGGER_REG6_L___POR 0x00000000 +#define PHYA_PCSS_DMAC1_TRIGGER_REG6_L__TRIGGER_6___POR 0x0 +#define PHYA_PCSS_DMAC1_TRIGGER_REG6_L__TRIGGER_6___M 0x00000001 +#define PHYA_PCSS_DMAC1_TRIGGER_REG6_L__TRIGGER_6___S 0 +#define PHYA_PCSS_DMAC1_TRIGGER_REG6_L___M 0x00000001 +#define PHYA_PCSS_DMAC1_TRIGGER_REG6_L___S 0 + +#define PHYA_PCSS_DMAC1_TRIGGER_REG7_L (0x00380838) +#define PHYA_PCSS_DMAC1_TRIGGER_REG7_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_TRIGGER_REG7_L___POR 0x00000000 +#define PHYA_PCSS_DMAC1_TRIGGER_REG7_L__TRIGGER_7___POR 0x0 +#define PHYA_PCSS_DMAC1_TRIGGER_REG7_L__TRIGGER_7___M 0x00000001 +#define PHYA_PCSS_DMAC1_TRIGGER_REG7_L__TRIGGER_7___S 0 +#define PHYA_PCSS_DMAC1_TRIGGER_REG7_L___M 0x00000001 +#define PHYA_PCSS_DMAC1_TRIGGER_REG7_L___S 0 + +#define PHYA_PCSS_DMAC1_DUMMY2_REG0_L (0x00380840) +#define PHYA_PCSS_DMAC1_DUMMY2_REG0_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DUMMY2_REG0_L___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DUMMY2_REG0_L__DUMMY2_0___POR 0x0 +#define PHYA_PCSS_DMAC1_DUMMY2_REG0_L__DUMMY2_0___M 0x00000001 +#define PHYA_PCSS_DMAC1_DUMMY2_REG0_L__DUMMY2_0___S 0 +#define PHYA_PCSS_DMAC1_DUMMY2_REG0_L___M 0x00000001 +#define PHYA_PCSS_DMAC1_DUMMY2_REG0_L___S 0 + +#define PHYA_PCSS_DMAC1_DUMMY2_REG1_L (0x00380848) +#define PHYA_PCSS_DMAC1_DUMMY2_REG1_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DUMMY2_REG1_L___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DUMMY2_REG1_L__DUMMY2_1___POR 0x0 +#define PHYA_PCSS_DMAC1_DUMMY2_REG1_L__DUMMY2_1___M 0x00000001 +#define PHYA_PCSS_DMAC1_DUMMY2_REG1_L__DUMMY2_1___S 0 +#define PHYA_PCSS_DMAC1_DUMMY2_REG1_L___M 0x00000001 +#define PHYA_PCSS_DMAC1_DUMMY2_REG1_L___S 0 + +#define PHYA_PCSS_DMAC1_DUMMY2_REG2_L (0x00380850) +#define PHYA_PCSS_DMAC1_DUMMY2_REG2_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DUMMY2_REG2_L___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DUMMY2_REG2_L__DUMMY2_2___POR 0x0 +#define PHYA_PCSS_DMAC1_DUMMY2_REG2_L__DUMMY2_2___M 0x00000001 +#define PHYA_PCSS_DMAC1_DUMMY2_REG2_L__DUMMY2_2___S 0 +#define PHYA_PCSS_DMAC1_DUMMY2_REG2_L___M 0x00000001 +#define PHYA_PCSS_DMAC1_DUMMY2_REG2_L___S 0 + +#define PHYA_PCSS_DMAC1_DUMMY2_REG3_L (0x00380858) +#define PHYA_PCSS_DMAC1_DUMMY2_REG3_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DUMMY2_REG3_L___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DUMMY2_REG3_L__DUMMY2_3___POR 0x0 +#define PHYA_PCSS_DMAC1_DUMMY2_REG3_L__DUMMY2_3___M 0x00000001 +#define PHYA_PCSS_DMAC1_DUMMY2_REG3_L__DUMMY2_3___S 0 +#define PHYA_PCSS_DMAC1_DUMMY2_REG3_L___M 0x00000001 +#define PHYA_PCSS_DMAC1_DUMMY2_REG3_L___S 0 + +#define PHYA_PCSS_DMAC1_DUMMY2_REG4_L (0x00380860) +#define PHYA_PCSS_DMAC1_DUMMY2_REG4_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DUMMY2_REG4_L___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DUMMY2_REG4_L__DUMMY2_4___POR 0x0 +#define PHYA_PCSS_DMAC1_DUMMY2_REG4_L__DUMMY2_4___M 0x00000001 +#define PHYA_PCSS_DMAC1_DUMMY2_REG4_L__DUMMY2_4___S 0 +#define PHYA_PCSS_DMAC1_DUMMY2_REG4_L___M 0x00000001 +#define PHYA_PCSS_DMAC1_DUMMY2_REG4_L___S 0 + +#define PHYA_PCSS_DMAC1_DUMMY2_REG5_L (0x00380868) +#define PHYA_PCSS_DMAC1_DUMMY2_REG5_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DUMMY2_REG5_L___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DUMMY2_REG5_L__DUMMY2_5___POR 0x0 +#define PHYA_PCSS_DMAC1_DUMMY2_REG5_L__DUMMY2_5___M 0x00000001 +#define PHYA_PCSS_DMAC1_DUMMY2_REG5_L__DUMMY2_5___S 0 +#define PHYA_PCSS_DMAC1_DUMMY2_REG5_L___M 0x00000001 +#define PHYA_PCSS_DMAC1_DUMMY2_REG5_L___S 0 + +#define PHYA_PCSS_DMAC1_DUMMY2_REG6_L (0x00380870) +#define PHYA_PCSS_DMAC1_DUMMY2_REG6_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DUMMY2_REG6_L___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DUMMY2_REG6_L__DUMMY2_6___POR 0x0 +#define PHYA_PCSS_DMAC1_DUMMY2_REG6_L__DUMMY2_6___M 0x00000001 +#define PHYA_PCSS_DMAC1_DUMMY2_REG6_L__DUMMY2_6___S 0 +#define PHYA_PCSS_DMAC1_DUMMY2_REG6_L___M 0x00000001 +#define PHYA_PCSS_DMAC1_DUMMY2_REG6_L___S 0 + +#define PHYA_PCSS_DMAC1_DUMMY2_REG7_L (0x00380878) +#define PHYA_PCSS_DMAC1_DUMMY2_REG7_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DUMMY2_REG7_L___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DUMMY2_REG7_L__DUMMY2_7___POR 0x0 +#define PHYA_PCSS_DMAC1_DUMMY2_REG7_L__DUMMY2_7___M 0x00000001 +#define PHYA_PCSS_DMAC1_DUMMY2_REG7_L__DUMMY2_7___S 0 +#define PHYA_PCSS_DMAC1_DUMMY2_REG7_L___M 0x00000001 +#define PHYA_PCSS_DMAC1_DUMMY2_REG7_L___S 0 + +#define PHYA_PCSS_DMAC1_DMA_CTRL_L (0x00380880) +#define PHYA_PCSS_DMAC1_DMA_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DMA_CTRL_L___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DMA_CTRL_L__DMAC_EN___POR 0x0 +#define PHYA_PCSS_DMAC1_DMA_CTRL_L__DMAC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC1_DMA_CTRL_L__DMAC_EN___S 0 +#define PHYA_PCSS_DMAC1_DMA_CTRL_L___M 0x00000001 +#define PHYA_PCSS_DMAC1_DMA_CTRL_L___S 0 + +#define PHYA_PCSS_DMAC1_DMA_CTRL_U (0x00380884) +#define PHYA_PCSS_DMAC1_DMA_CTRL_U___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DMA_CTRL_U___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DMA_CTRL_U__EVTI_XFER_STOP___POR 0x00 +#define PHYA_PCSS_DMAC1_DMA_CTRL_U__EVTI_XFER_STOP___M 0x0000003F +#define PHYA_PCSS_DMAC1_DMA_CTRL_U__EVTI_XFER_STOP___S 0 +#define PHYA_PCSS_DMAC1_DMA_CTRL_U___M 0x0000003F +#define PHYA_PCSS_DMAC1_DMA_CTRL_U___S 0 + +#define PHYA_PCSS_DMAC1_DMA_STATUS_0_L (0x00380888) +#define PHYA_PCSS_DMAC1_DMA_STATUS_0_L___RWC QCSR_REG_RO +#define PHYA_PCSS_DMAC1_DMA_STATUS_0_L___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DMA_STATUS_0_L__CTRL_FSM_STATE___POR 0x0 +#define PHYA_PCSS_DMAC1_DMA_STATUS_0_L__DESC_LAST___POR 0x0 +#define PHYA_PCSS_DMAC1_DMA_STATUS_0_L__DESC_ACTIVE___POR 0x0 +#define PHYA_PCSS_DMAC1_DMA_STATUS_0_L__DMAC_ACTIVE___POR 0x0 +#define PHYA_PCSS_DMAC1_DMA_STATUS_0_L__CTRL_FSM_STATE___M 0x0F000000 +#define PHYA_PCSS_DMAC1_DMA_STATUS_0_L__CTRL_FSM_STATE___S 24 +#define PHYA_PCSS_DMAC1_DMA_STATUS_0_L__DESC_LAST___M 0x000F0000 +#define PHYA_PCSS_DMAC1_DMA_STATUS_0_L__DESC_LAST___S 16 +#define PHYA_PCSS_DMAC1_DMA_STATUS_0_L__DESC_ACTIVE___M 0x00000F00 +#define PHYA_PCSS_DMAC1_DMA_STATUS_0_L__DESC_ACTIVE___S 8 +#define PHYA_PCSS_DMAC1_DMA_STATUS_0_L__DMAC_ACTIVE___M 0x00000001 +#define PHYA_PCSS_DMAC1_DMA_STATUS_0_L__DMAC_ACTIVE___S 0 +#define PHYA_PCSS_DMAC1_DMA_STATUS_0_L___M 0x0F0F0F01 +#define PHYA_PCSS_DMAC1_DMA_STATUS_0_L___S 0 + +#define PHYA_PCSS_DMAC1_DMA_STATUS_0_U (0x0038088C) +#define PHYA_PCSS_DMAC1_DMA_STATUS_0_U___RWC QCSR_REG_RO +#define PHYA_PCSS_DMAC1_DMA_STATUS_0_U___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DMA_STATUS_0_U__XFER_FIFO_OCC___POR 0x000 +#define PHYA_PCSS_DMAC1_DMA_STATUS_0_U__ALEN_FIFO_OCC___POR 0x0 +#define PHYA_PCSS_DMAC1_DMA_STATUS_0_U__DP_FSM_STATE___POR 0x0 +#define PHYA_PCSS_DMAC1_DMA_STATUS_0_U__XFER_FIFO_OCC___M 0x01FF0000 +#define PHYA_PCSS_DMAC1_DMA_STATUS_0_U__XFER_FIFO_OCC___S 16 +#define PHYA_PCSS_DMAC1_DMA_STATUS_0_U__ALEN_FIFO_OCC___M 0x00000F00 +#define PHYA_PCSS_DMAC1_DMA_STATUS_0_U__ALEN_FIFO_OCC___S 8 +#define PHYA_PCSS_DMAC1_DMA_STATUS_0_U__DP_FSM_STATE___M 0x0000000F +#define PHYA_PCSS_DMAC1_DMA_STATUS_0_U__DP_FSM_STATE___S 0 +#define PHYA_PCSS_DMAC1_DMA_STATUS_0_U___M 0x01FF0F0F +#define PHYA_PCSS_DMAC1_DMA_STATUS_0_U___S 0 + +#define PHYA_PCSS_DMAC1_DMA_STATUS_1_L (0x00380890) +#define PHYA_PCSS_DMAC1_DMA_STATUS_1_L___RWC QCSR_REG_RO +#define PHYA_PCSS_DMAC1_DMA_STATUS_1_L___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DMA_STATUS_1_L__XFER_LEN_PEND___POR 0x000000 +#define PHYA_PCSS_DMAC1_DMA_STATUS_1_L__XFER_LEN_PEND___M 0x00FFFFFF +#define PHYA_PCSS_DMAC1_DMA_STATUS_1_L__XFER_LEN_PEND___S 0 +#define PHYA_PCSS_DMAC1_DMA_STATUS_1_L___M 0x00FFFFFF +#define PHYA_PCSS_DMAC1_DMA_STATUS_1_L___S 0 + +#define PHYA_PCSS_DMAC1_DMA_EVT_LATCH_L (0x00380898) +#define PHYA_PCSS_DMAC1_DMA_EVT_LATCH_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DMA_EVT_LATCH_L___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___S 0 +#define PHYA_PCSS_DMAC1_DMA_EVT_LATCH_L___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DMA_EVT_LATCH_L___S 0 + +#define PHYA_PCSS_DMAC1_DMA_EVT_LATCH_U (0x0038089C) +#define PHYA_PCSS_DMAC1_DMA_EVT_LATCH_U___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DMA_EVT_LATCH_U___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___S 0 +#define PHYA_PCSS_DMAC1_DMA_EVT_LATCH_U___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DMA_EVT_LATCH_U___S 0 + +#define PHYA_PCSS_DMAC1_DMA_EVT_TRIG_L (0x003808A0) +#define PHYA_PCSS_DMAC1_DMA_EVT_TRIG_L___RWC QCSR_REG_RO +#define PHYA_PCSS_DMAC1_DMA_EVT_TRIG_L___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DMA_EVT_TRIG_L__CUR_EVT_TRIG___POR 0x00 +#define PHYA_PCSS_DMAC1_DMA_EVT_TRIG_L__LAST_EVT_TRIG___POR 0x00 +#define PHYA_PCSS_DMAC1_DMA_EVT_TRIG_L__CUR_EVT_TRIG___M 0x0000FF00 +#define PHYA_PCSS_DMAC1_DMA_EVT_TRIG_L__CUR_EVT_TRIG___S 8 +#define PHYA_PCSS_DMAC1_DMA_EVT_TRIG_L__LAST_EVT_TRIG___M 0x000000FF +#define PHYA_PCSS_DMAC1_DMA_EVT_TRIG_L__LAST_EVT_TRIG___S 0 +#define PHYA_PCSS_DMAC1_DMA_EVT_TRIG_L___M 0x0000FFFF +#define PHYA_PCSS_DMAC1_DMA_EVT_TRIG_L___S 0 + +#define PHYA_PCSS_DMAC1_DMA_XFER_CTRL_L (0x003808A8) +#define PHYA_PCSS_DMAC1_DMA_XFER_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DMA_XFER_CTRL_L___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___POR 0x0 +#define PHYA_PCSS_DMAC1_DMA_XFER_CTRL_L__PAUSE_XFER___POR 0x0 +#define PHYA_PCSS_DMAC1_DMA_XFER_CTRL_L__STOP_XFER_MASK___POR 0x00 +#define PHYA_PCSS_DMAC1_DMA_XFER_CTRL_L__STOP_XFER___POR 0x0 +#define PHYA_PCSS_DMAC1_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___M 0x00040000 +#define PHYA_PCSS_DMAC1_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___S 18 +#define PHYA_PCSS_DMAC1_DMA_XFER_CTRL_L__PAUSE_XFER___M 0x00020000 +#define PHYA_PCSS_DMAC1_DMA_XFER_CTRL_L__PAUSE_XFER___S 17 +#define PHYA_PCSS_DMAC1_DMA_XFER_CTRL_L__STOP_XFER_MASK___M 0x000001FE +#define PHYA_PCSS_DMAC1_DMA_XFER_CTRL_L__STOP_XFER_MASK___S 1 +#define PHYA_PCSS_DMAC1_DMA_XFER_CTRL_L__STOP_XFER___M 0x00000001 +#define PHYA_PCSS_DMAC1_DMA_XFER_CTRL_L__STOP_XFER___S 0 +#define PHYA_PCSS_DMAC1_DMA_XFER_CTRL_L___M 0x000601FF +#define PHYA_PCSS_DMAC1_DMA_XFER_CTRL_L___S 0 + +#define PHYA_PCSS_DMAC1_DMA_SPARE_L (0x003808B0) +#define PHYA_PCSS_DMAC1_DMA_SPARE_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DMA_SPARE_L___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DMA_SPARE_L__DMA_SPARE_0___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DMA_SPARE_L__DMA_SPARE_0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DMA_SPARE_L__DMA_SPARE_0___S 0 +#define PHYA_PCSS_DMAC1_DMA_SPARE_L___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DMA_SPARE_L___S 0 + +#define PHYA_PCSS_DMAC1_DMA_SPARE_U (0x003808B4) +#define PHYA_PCSS_DMAC1_DMA_SPARE_U___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DMA_SPARE_U___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DMA_SPARE_U__DMA_SPARE_1___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DMA_SPARE_U__DMA_SPARE_1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DMA_SPARE_U__DMA_SPARE_1___S 0 +#define PHYA_PCSS_DMAC1_DMA_SPARE_U___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DMA_SPARE_U___S 0 + +#define PHYA_PCSS_DMAC1_DMA_ECO_L (0x003808B8) +#define PHYA_PCSS_DMAC1_DMA_ECO_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DMA_ECO_L___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DMA_ECO_L__DMA_ECO_0___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DMA_ECO_L__DMA_ECO_0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DMA_ECO_L__DMA_ECO_0___S 0 +#define PHYA_PCSS_DMAC1_DMA_ECO_L___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DMA_ECO_L___S 0 + +#define PHYA_PCSS_DMAC1_DMA_ECO_U (0x003808BC) +#define PHYA_PCSS_DMAC1_DMA_ECO_U___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DMA_ECO_U___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DMA_ECO_U__DMA_ECO_1___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DMA_ECO_U__DMA_ECO_1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DMA_ECO_U__DMA_ECO_1___S 0 +#define PHYA_PCSS_DMAC1_DMA_ECO_U___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DMA_ECO_U___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B0 (0x003808C0) +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B0__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B0__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B0__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B0___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B1 (0x003808D8) +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B1__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B1__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B1__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B1___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B2 (0x003808F0) +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B2__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B2__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B2__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B2___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B3 (0x00380908) +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B3__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B3__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B3__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B3___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B4 (0x00380920) +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B4__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B4__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B4__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B4___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B5 (0x00380938) +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B5__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B5__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B5__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B5___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B6 (0x00380950) +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B6__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B6__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B6__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B6___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B7 (0x00380968) +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B7__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B7__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B7__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_0_L_B7___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B0 (0x003808C4) +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B0__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B0__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B0__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B0__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B0__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B0__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B0___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B1 (0x003808DC) +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B1__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B1__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B1__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B1__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B1__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B1__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B1___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B2 (0x003808F4) +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B2__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B2__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B2__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B2__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B2__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B2__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B2___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B3 (0x0038090C) +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B3__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B3__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B3__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B3__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B3__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B3__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B3___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B4 (0x00380924) +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B4__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B4__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B4__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B4__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B4__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B4__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B4___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B5 (0x0038093C) +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B5__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B5__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B5__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B5__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B5__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B5__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B5___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B6 (0x00380954) +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B6__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B6__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B6__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B6__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B6__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B6__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B6___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B7 (0x0038096C) +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B7__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B7__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B7__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B7__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B7__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B7__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_0_U_B7___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B0 (0x003808C8) +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B0__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B0__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B0__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B0___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B1 (0x003808E0) +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B1__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B1__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B1__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B1___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B2 (0x003808F8) +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B2__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B2__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B2__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B2___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B3 (0x00380910) +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B3__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B3__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B3__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B3___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B4 (0x00380928) +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B4__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B4__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B4__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B4___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B5 (0x00380940) +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B5__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B5__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B5__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B5___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B6 (0x00380958) +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B6__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B6__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B6__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B6___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B7 (0x00380970) +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B7__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B7__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B7__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_1_L_B7___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B0 (0x003808CC) +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B0__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B0__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B0__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B0___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B1 (0x003808E4) +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B1__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B1__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B1__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B1___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B2 (0x003808FC) +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B2__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B2__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B2__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B2___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B3 (0x00380914) +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B3__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B3__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B3__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B3___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B4 (0x0038092C) +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B4__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B4__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B4__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B4___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B5 (0x00380944) +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B5__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B5__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B5__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B5___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B6 (0x0038095C) +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B6__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B6__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B6__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B6___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B7 (0x00380974) +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B7__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B7__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B7__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_1_U_B7___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B0 (0x003808D0) +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B0__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B0__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B0__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B0___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B1 (0x003808E8) +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B1__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B1__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B1__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B1___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B2 (0x00380900) +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B2__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B2__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B2__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B2___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B3 (0x00380918) +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B3__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B3__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B3__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B3___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B4 (0x00380930) +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B4__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B4__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B4__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B4___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B5 (0x00380948) +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B5__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B5__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B5__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B5___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B6 (0x00380960) +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B6__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B6__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B6__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B6___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B7 (0x00380978) +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B7__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B7__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B7__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_2_L_B7___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0 (0x003808D4) +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__FRZDST___S 6 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__FRZSRC___S 5 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__DATSRC___S 2 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0__DESC_EN___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B0___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1 (0x003808EC) +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__FRZDST___S 6 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__FRZSRC___S 5 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__DATSRC___S 2 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1__DESC_EN___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B1___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2 (0x00380904) +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__FRZDST___S 6 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__FRZSRC___S 5 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__DATSRC___S 2 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2__DESC_EN___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B2___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3 (0x0038091C) +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__FRZDST___S 6 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__FRZSRC___S 5 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__DATSRC___S 2 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3__DESC_EN___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B3___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4 (0x00380934) +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__FRZDST___S 6 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__FRZSRC___S 5 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__DATSRC___S 2 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4__DESC_EN___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B4___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5 (0x0038094C) +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__FRZDST___S 6 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__FRZSRC___S 5 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__DATSRC___S 2 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5__DESC_EN___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B5___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6 (0x00380964) +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__FRZDST___S 6 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__FRZSRC___S 5 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__DATSRC___S 2 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6__DESC_EN___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B6___S 0 + +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7 (0x0038097C) +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__FRZDST___S 6 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__FRZSRC___S 5 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__DATSRC___S 2 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7__DESC_EN___S 0 +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC1_DESC_REG_2_U_B7___S 0 + +#define PHYA_PCSS_DMAC1_DMAC2PHYDBG_EN_REG_L (0x00380980) +#define PHYA_PCSS_DMAC1_DMAC2PHYDBG_EN_REG_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DMAC2PHYDBG_EN_REG_L___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___POR 0x00 +#define PHYA_PCSS_DMAC1_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___M 0x000000FF +#define PHYA_PCSS_DMAC1_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___S 0 +#define PHYA_PCSS_DMAC1_DMAC2PHYDBG_EN_REG_L___M 0x000000FF +#define PHYA_PCSS_DMAC1_DMAC2PHYDBG_EN_REG_L___S 0 + +#define PHYA_PCSS_DMAC1_DUMMY_L (0x00380A48) +#define PHYA_PCSS_DMAC1_DUMMY_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC1_DUMMY_L___POR 0x00000000 +#define PHYA_PCSS_DMAC1_DUMMY_L__DUMMY___POR 0x0 +#define PHYA_PCSS_DMAC1_DUMMY_L__DUMMY___M 0x00000001 +#define PHYA_PCSS_DMAC1_DUMMY_L__DUMMY___S 0 +#define PHYA_PCSS_DMAC1_DUMMY_L___M 0x00000001 +#define PHYA_PCSS_DMAC1_DUMMY_L___S 0 + +#define PHYA_PCSS_DMAC2_TRIGGER_REG0_L (0x00380C00) +#define PHYA_PCSS_DMAC2_TRIGGER_REG0_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_TRIGGER_REG0_L___POR 0x00000000 +#define PHYA_PCSS_DMAC2_TRIGGER_REG0_L__TRIGGER_0___POR 0x0 +#define PHYA_PCSS_DMAC2_TRIGGER_REG0_L__TRIGGER_0___M 0x00000001 +#define PHYA_PCSS_DMAC2_TRIGGER_REG0_L__TRIGGER_0___S 0 +#define PHYA_PCSS_DMAC2_TRIGGER_REG0_L___M 0x00000001 +#define PHYA_PCSS_DMAC2_TRIGGER_REG0_L___S 0 + +#define PHYA_PCSS_DMAC2_TRIGGER_REG1_L (0x00380C08) +#define PHYA_PCSS_DMAC2_TRIGGER_REG1_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_TRIGGER_REG1_L___POR 0x00000000 +#define PHYA_PCSS_DMAC2_TRIGGER_REG1_L__TRIGGER_1___POR 0x0 +#define PHYA_PCSS_DMAC2_TRIGGER_REG1_L__TRIGGER_1___M 0x00000001 +#define PHYA_PCSS_DMAC2_TRIGGER_REG1_L__TRIGGER_1___S 0 +#define PHYA_PCSS_DMAC2_TRIGGER_REG1_L___M 0x00000001 +#define PHYA_PCSS_DMAC2_TRIGGER_REG1_L___S 0 + +#define PHYA_PCSS_DMAC2_TRIGGER_REG2_L (0x00380C10) +#define PHYA_PCSS_DMAC2_TRIGGER_REG2_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_TRIGGER_REG2_L___POR 0x00000000 +#define PHYA_PCSS_DMAC2_TRIGGER_REG2_L__TRIGGER_2___POR 0x0 +#define PHYA_PCSS_DMAC2_TRIGGER_REG2_L__TRIGGER_2___M 0x00000001 +#define PHYA_PCSS_DMAC2_TRIGGER_REG2_L__TRIGGER_2___S 0 +#define PHYA_PCSS_DMAC2_TRIGGER_REG2_L___M 0x00000001 +#define PHYA_PCSS_DMAC2_TRIGGER_REG2_L___S 0 + +#define PHYA_PCSS_DMAC2_TRIGGER_REG3_L (0x00380C18) +#define PHYA_PCSS_DMAC2_TRIGGER_REG3_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_TRIGGER_REG3_L___POR 0x00000000 +#define PHYA_PCSS_DMAC2_TRIGGER_REG3_L__TRIGGER_3___POR 0x0 +#define PHYA_PCSS_DMAC2_TRIGGER_REG3_L__TRIGGER_3___M 0x00000001 +#define PHYA_PCSS_DMAC2_TRIGGER_REG3_L__TRIGGER_3___S 0 +#define PHYA_PCSS_DMAC2_TRIGGER_REG3_L___M 0x00000001 +#define PHYA_PCSS_DMAC2_TRIGGER_REG3_L___S 0 + +#define PHYA_PCSS_DMAC2_TRIGGER_REG4_L (0x00380C20) +#define PHYA_PCSS_DMAC2_TRIGGER_REG4_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_TRIGGER_REG4_L___POR 0x00000000 +#define PHYA_PCSS_DMAC2_TRIGGER_REG4_L__TRIGGER_4___POR 0x0 +#define PHYA_PCSS_DMAC2_TRIGGER_REG4_L__TRIGGER_4___M 0x00000001 +#define PHYA_PCSS_DMAC2_TRIGGER_REG4_L__TRIGGER_4___S 0 +#define PHYA_PCSS_DMAC2_TRIGGER_REG4_L___M 0x00000001 +#define PHYA_PCSS_DMAC2_TRIGGER_REG4_L___S 0 + +#define PHYA_PCSS_DMAC2_TRIGGER_REG5_L (0x00380C28) +#define PHYA_PCSS_DMAC2_TRIGGER_REG5_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_TRIGGER_REG5_L___POR 0x00000000 +#define PHYA_PCSS_DMAC2_TRIGGER_REG5_L__TRIGGER_5___POR 0x0 +#define PHYA_PCSS_DMAC2_TRIGGER_REG5_L__TRIGGER_5___M 0x00000001 +#define PHYA_PCSS_DMAC2_TRIGGER_REG5_L__TRIGGER_5___S 0 +#define PHYA_PCSS_DMAC2_TRIGGER_REG5_L___M 0x00000001 +#define PHYA_PCSS_DMAC2_TRIGGER_REG5_L___S 0 + +#define PHYA_PCSS_DMAC2_TRIGGER_REG6_L (0x00380C30) +#define PHYA_PCSS_DMAC2_TRIGGER_REG6_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_TRIGGER_REG6_L___POR 0x00000000 +#define PHYA_PCSS_DMAC2_TRIGGER_REG6_L__TRIGGER_6___POR 0x0 +#define PHYA_PCSS_DMAC2_TRIGGER_REG6_L__TRIGGER_6___M 0x00000001 +#define PHYA_PCSS_DMAC2_TRIGGER_REG6_L__TRIGGER_6___S 0 +#define PHYA_PCSS_DMAC2_TRIGGER_REG6_L___M 0x00000001 +#define PHYA_PCSS_DMAC2_TRIGGER_REG6_L___S 0 + +#define PHYA_PCSS_DMAC2_TRIGGER_REG7_L (0x00380C38) +#define PHYA_PCSS_DMAC2_TRIGGER_REG7_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_TRIGGER_REG7_L___POR 0x00000000 +#define PHYA_PCSS_DMAC2_TRIGGER_REG7_L__TRIGGER_7___POR 0x0 +#define PHYA_PCSS_DMAC2_TRIGGER_REG7_L__TRIGGER_7___M 0x00000001 +#define PHYA_PCSS_DMAC2_TRIGGER_REG7_L__TRIGGER_7___S 0 +#define PHYA_PCSS_DMAC2_TRIGGER_REG7_L___M 0x00000001 +#define PHYA_PCSS_DMAC2_TRIGGER_REG7_L___S 0 + +#define PHYA_PCSS_DMAC2_DUMMY2_REG0_L (0x00380C40) +#define PHYA_PCSS_DMAC2_DUMMY2_REG0_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DUMMY2_REG0_L___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DUMMY2_REG0_L__DUMMY2_0___POR 0x0 +#define PHYA_PCSS_DMAC2_DUMMY2_REG0_L__DUMMY2_0___M 0x00000001 +#define PHYA_PCSS_DMAC2_DUMMY2_REG0_L__DUMMY2_0___S 0 +#define PHYA_PCSS_DMAC2_DUMMY2_REG0_L___M 0x00000001 +#define PHYA_PCSS_DMAC2_DUMMY2_REG0_L___S 0 + +#define PHYA_PCSS_DMAC2_DUMMY2_REG1_L (0x00380C48) +#define PHYA_PCSS_DMAC2_DUMMY2_REG1_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DUMMY2_REG1_L___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DUMMY2_REG1_L__DUMMY2_1___POR 0x0 +#define PHYA_PCSS_DMAC2_DUMMY2_REG1_L__DUMMY2_1___M 0x00000001 +#define PHYA_PCSS_DMAC2_DUMMY2_REG1_L__DUMMY2_1___S 0 +#define PHYA_PCSS_DMAC2_DUMMY2_REG1_L___M 0x00000001 +#define PHYA_PCSS_DMAC2_DUMMY2_REG1_L___S 0 + +#define PHYA_PCSS_DMAC2_DUMMY2_REG2_L (0x00380C50) +#define PHYA_PCSS_DMAC2_DUMMY2_REG2_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DUMMY2_REG2_L___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DUMMY2_REG2_L__DUMMY2_2___POR 0x0 +#define PHYA_PCSS_DMAC2_DUMMY2_REG2_L__DUMMY2_2___M 0x00000001 +#define PHYA_PCSS_DMAC2_DUMMY2_REG2_L__DUMMY2_2___S 0 +#define PHYA_PCSS_DMAC2_DUMMY2_REG2_L___M 0x00000001 +#define PHYA_PCSS_DMAC2_DUMMY2_REG2_L___S 0 + +#define PHYA_PCSS_DMAC2_DUMMY2_REG3_L (0x00380C58) +#define PHYA_PCSS_DMAC2_DUMMY2_REG3_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DUMMY2_REG3_L___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DUMMY2_REG3_L__DUMMY2_3___POR 0x0 +#define PHYA_PCSS_DMAC2_DUMMY2_REG3_L__DUMMY2_3___M 0x00000001 +#define PHYA_PCSS_DMAC2_DUMMY2_REG3_L__DUMMY2_3___S 0 +#define PHYA_PCSS_DMAC2_DUMMY2_REG3_L___M 0x00000001 +#define PHYA_PCSS_DMAC2_DUMMY2_REG3_L___S 0 + +#define PHYA_PCSS_DMAC2_DUMMY2_REG4_L (0x00380C60) +#define PHYA_PCSS_DMAC2_DUMMY2_REG4_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DUMMY2_REG4_L___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DUMMY2_REG4_L__DUMMY2_4___POR 0x0 +#define PHYA_PCSS_DMAC2_DUMMY2_REG4_L__DUMMY2_4___M 0x00000001 +#define PHYA_PCSS_DMAC2_DUMMY2_REG4_L__DUMMY2_4___S 0 +#define PHYA_PCSS_DMAC2_DUMMY2_REG4_L___M 0x00000001 +#define PHYA_PCSS_DMAC2_DUMMY2_REG4_L___S 0 + +#define PHYA_PCSS_DMAC2_DUMMY2_REG5_L (0x00380C68) +#define PHYA_PCSS_DMAC2_DUMMY2_REG5_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DUMMY2_REG5_L___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DUMMY2_REG5_L__DUMMY2_5___POR 0x0 +#define PHYA_PCSS_DMAC2_DUMMY2_REG5_L__DUMMY2_5___M 0x00000001 +#define PHYA_PCSS_DMAC2_DUMMY2_REG5_L__DUMMY2_5___S 0 +#define PHYA_PCSS_DMAC2_DUMMY2_REG5_L___M 0x00000001 +#define PHYA_PCSS_DMAC2_DUMMY2_REG5_L___S 0 + +#define PHYA_PCSS_DMAC2_DUMMY2_REG6_L (0x00380C70) +#define PHYA_PCSS_DMAC2_DUMMY2_REG6_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DUMMY2_REG6_L___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DUMMY2_REG6_L__DUMMY2_6___POR 0x0 +#define PHYA_PCSS_DMAC2_DUMMY2_REG6_L__DUMMY2_6___M 0x00000001 +#define PHYA_PCSS_DMAC2_DUMMY2_REG6_L__DUMMY2_6___S 0 +#define PHYA_PCSS_DMAC2_DUMMY2_REG6_L___M 0x00000001 +#define PHYA_PCSS_DMAC2_DUMMY2_REG6_L___S 0 + +#define PHYA_PCSS_DMAC2_DUMMY2_REG7_L (0x00380C78) +#define PHYA_PCSS_DMAC2_DUMMY2_REG7_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DUMMY2_REG7_L___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DUMMY2_REG7_L__DUMMY2_7___POR 0x0 +#define PHYA_PCSS_DMAC2_DUMMY2_REG7_L__DUMMY2_7___M 0x00000001 +#define PHYA_PCSS_DMAC2_DUMMY2_REG7_L__DUMMY2_7___S 0 +#define PHYA_PCSS_DMAC2_DUMMY2_REG7_L___M 0x00000001 +#define PHYA_PCSS_DMAC2_DUMMY2_REG7_L___S 0 + +#define PHYA_PCSS_DMAC2_DMA_CTRL_L (0x00380C80) +#define PHYA_PCSS_DMAC2_DMA_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DMA_CTRL_L___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DMA_CTRL_L__DMAC_EN___POR 0x0 +#define PHYA_PCSS_DMAC2_DMA_CTRL_L__DMAC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC2_DMA_CTRL_L__DMAC_EN___S 0 +#define PHYA_PCSS_DMAC2_DMA_CTRL_L___M 0x00000001 +#define PHYA_PCSS_DMAC2_DMA_CTRL_L___S 0 + +#define PHYA_PCSS_DMAC2_DMA_CTRL_U (0x00380C84) +#define PHYA_PCSS_DMAC2_DMA_CTRL_U___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DMA_CTRL_U___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DMA_CTRL_U__EVTI_XFER_STOP___POR 0x00 +#define PHYA_PCSS_DMAC2_DMA_CTRL_U__EVTI_XFER_STOP___M 0x0000003F +#define PHYA_PCSS_DMAC2_DMA_CTRL_U__EVTI_XFER_STOP___S 0 +#define PHYA_PCSS_DMAC2_DMA_CTRL_U___M 0x0000003F +#define PHYA_PCSS_DMAC2_DMA_CTRL_U___S 0 + +#define PHYA_PCSS_DMAC2_DMA_STATUS_0_L (0x00380C88) +#define PHYA_PCSS_DMAC2_DMA_STATUS_0_L___RWC QCSR_REG_RO +#define PHYA_PCSS_DMAC2_DMA_STATUS_0_L___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DMA_STATUS_0_L__CTRL_FSM_STATE___POR 0x0 +#define PHYA_PCSS_DMAC2_DMA_STATUS_0_L__DESC_LAST___POR 0x0 +#define PHYA_PCSS_DMAC2_DMA_STATUS_0_L__DESC_ACTIVE___POR 0x0 +#define PHYA_PCSS_DMAC2_DMA_STATUS_0_L__DMAC_ACTIVE___POR 0x0 +#define PHYA_PCSS_DMAC2_DMA_STATUS_0_L__CTRL_FSM_STATE___M 0x0F000000 +#define PHYA_PCSS_DMAC2_DMA_STATUS_0_L__CTRL_FSM_STATE___S 24 +#define PHYA_PCSS_DMAC2_DMA_STATUS_0_L__DESC_LAST___M 0x000F0000 +#define PHYA_PCSS_DMAC2_DMA_STATUS_0_L__DESC_LAST___S 16 +#define PHYA_PCSS_DMAC2_DMA_STATUS_0_L__DESC_ACTIVE___M 0x00000F00 +#define PHYA_PCSS_DMAC2_DMA_STATUS_0_L__DESC_ACTIVE___S 8 +#define PHYA_PCSS_DMAC2_DMA_STATUS_0_L__DMAC_ACTIVE___M 0x00000001 +#define PHYA_PCSS_DMAC2_DMA_STATUS_0_L__DMAC_ACTIVE___S 0 +#define PHYA_PCSS_DMAC2_DMA_STATUS_0_L___M 0x0F0F0F01 +#define PHYA_PCSS_DMAC2_DMA_STATUS_0_L___S 0 + +#define PHYA_PCSS_DMAC2_DMA_STATUS_0_U (0x00380C8C) +#define PHYA_PCSS_DMAC2_DMA_STATUS_0_U___RWC QCSR_REG_RO +#define PHYA_PCSS_DMAC2_DMA_STATUS_0_U___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DMA_STATUS_0_U__XFER_FIFO_OCC___POR 0x000 +#define PHYA_PCSS_DMAC2_DMA_STATUS_0_U__ALEN_FIFO_OCC___POR 0x0 +#define PHYA_PCSS_DMAC2_DMA_STATUS_0_U__DP_FSM_STATE___POR 0x0 +#define PHYA_PCSS_DMAC2_DMA_STATUS_0_U__XFER_FIFO_OCC___M 0x01FF0000 +#define PHYA_PCSS_DMAC2_DMA_STATUS_0_U__XFER_FIFO_OCC___S 16 +#define PHYA_PCSS_DMAC2_DMA_STATUS_0_U__ALEN_FIFO_OCC___M 0x00000F00 +#define PHYA_PCSS_DMAC2_DMA_STATUS_0_U__ALEN_FIFO_OCC___S 8 +#define PHYA_PCSS_DMAC2_DMA_STATUS_0_U__DP_FSM_STATE___M 0x0000000F +#define PHYA_PCSS_DMAC2_DMA_STATUS_0_U__DP_FSM_STATE___S 0 +#define PHYA_PCSS_DMAC2_DMA_STATUS_0_U___M 0x01FF0F0F +#define PHYA_PCSS_DMAC2_DMA_STATUS_0_U___S 0 + +#define PHYA_PCSS_DMAC2_DMA_STATUS_1_L (0x00380C90) +#define PHYA_PCSS_DMAC2_DMA_STATUS_1_L___RWC QCSR_REG_RO +#define PHYA_PCSS_DMAC2_DMA_STATUS_1_L___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DMA_STATUS_1_L__XFER_LEN_PEND___POR 0x000000 +#define PHYA_PCSS_DMAC2_DMA_STATUS_1_L__XFER_LEN_PEND___M 0x00FFFFFF +#define PHYA_PCSS_DMAC2_DMA_STATUS_1_L__XFER_LEN_PEND___S 0 +#define PHYA_PCSS_DMAC2_DMA_STATUS_1_L___M 0x00FFFFFF +#define PHYA_PCSS_DMAC2_DMA_STATUS_1_L___S 0 + +#define PHYA_PCSS_DMAC2_DMA_EVT_LATCH_L (0x00380C98) +#define PHYA_PCSS_DMAC2_DMA_EVT_LATCH_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DMA_EVT_LATCH_L___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___S 0 +#define PHYA_PCSS_DMAC2_DMA_EVT_LATCH_L___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DMA_EVT_LATCH_L___S 0 + +#define PHYA_PCSS_DMAC2_DMA_EVT_LATCH_U (0x00380C9C) +#define PHYA_PCSS_DMAC2_DMA_EVT_LATCH_U___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DMA_EVT_LATCH_U___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___S 0 +#define PHYA_PCSS_DMAC2_DMA_EVT_LATCH_U___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DMA_EVT_LATCH_U___S 0 + +#define PHYA_PCSS_DMAC2_DMA_EVT_TRIG_L (0x00380CA0) +#define PHYA_PCSS_DMAC2_DMA_EVT_TRIG_L___RWC QCSR_REG_RO +#define PHYA_PCSS_DMAC2_DMA_EVT_TRIG_L___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DMA_EVT_TRIG_L__CUR_EVT_TRIG___POR 0x00 +#define PHYA_PCSS_DMAC2_DMA_EVT_TRIG_L__LAST_EVT_TRIG___POR 0x00 +#define PHYA_PCSS_DMAC2_DMA_EVT_TRIG_L__CUR_EVT_TRIG___M 0x0000FF00 +#define PHYA_PCSS_DMAC2_DMA_EVT_TRIG_L__CUR_EVT_TRIG___S 8 +#define PHYA_PCSS_DMAC2_DMA_EVT_TRIG_L__LAST_EVT_TRIG___M 0x000000FF +#define PHYA_PCSS_DMAC2_DMA_EVT_TRIG_L__LAST_EVT_TRIG___S 0 +#define PHYA_PCSS_DMAC2_DMA_EVT_TRIG_L___M 0x0000FFFF +#define PHYA_PCSS_DMAC2_DMA_EVT_TRIG_L___S 0 + +#define PHYA_PCSS_DMAC2_DMA_XFER_CTRL_L (0x00380CA8) +#define PHYA_PCSS_DMAC2_DMA_XFER_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DMA_XFER_CTRL_L___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___POR 0x0 +#define PHYA_PCSS_DMAC2_DMA_XFER_CTRL_L__PAUSE_XFER___POR 0x0 +#define PHYA_PCSS_DMAC2_DMA_XFER_CTRL_L__STOP_XFER_MASK___POR 0x00 +#define PHYA_PCSS_DMAC2_DMA_XFER_CTRL_L__STOP_XFER___POR 0x0 +#define PHYA_PCSS_DMAC2_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___M 0x00040000 +#define PHYA_PCSS_DMAC2_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___S 18 +#define PHYA_PCSS_DMAC2_DMA_XFER_CTRL_L__PAUSE_XFER___M 0x00020000 +#define PHYA_PCSS_DMAC2_DMA_XFER_CTRL_L__PAUSE_XFER___S 17 +#define PHYA_PCSS_DMAC2_DMA_XFER_CTRL_L__STOP_XFER_MASK___M 0x000001FE +#define PHYA_PCSS_DMAC2_DMA_XFER_CTRL_L__STOP_XFER_MASK___S 1 +#define PHYA_PCSS_DMAC2_DMA_XFER_CTRL_L__STOP_XFER___M 0x00000001 +#define PHYA_PCSS_DMAC2_DMA_XFER_CTRL_L__STOP_XFER___S 0 +#define PHYA_PCSS_DMAC2_DMA_XFER_CTRL_L___M 0x000601FF +#define PHYA_PCSS_DMAC2_DMA_XFER_CTRL_L___S 0 + +#define PHYA_PCSS_DMAC2_DMA_SPARE_L (0x00380CB0) +#define PHYA_PCSS_DMAC2_DMA_SPARE_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DMA_SPARE_L___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DMA_SPARE_L__DMA_SPARE_0___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DMA_SPARE_L__DMA_SPARE_0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DMA_SPARE_L__DMA_SPARE_0___S 0 +#define PHYA_PCSS_DMAC2_DMA_SPARE_L___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DMA_SPARE_L___S 0 + +#define PHYA_PCSS_DMAC2_DMA_SPARE_U (0x00380CB4) +#define PHYA_PCSS_DMAC2_DMA_SPARE_U___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DMA_SPARE_U___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DMA_SPARE_U__DMA_SPARE_1___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DMA_SPARE_U__DMA_SPARE_1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DMA_SPARE_U__DMA_SPARE_1___S 0 +#define PHYA_PCSS_DMAC2_DMA_SPARE_U___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DMA_SPARE_U___S 0 + +#define PHYA_PCSS_DMAC2_DMA_ECO_L (0x00380CB8) +#define PHYA_PCSS_DMAC2_DMA_ECO_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DMA_ECO_L___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DMA_ECO_L__DMA_ECO_0___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DMA_ECO_L__DMA_ECO_0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DMA_ECO_L__DMA_ECO_0___S 0 +#define PHYA_PCSS_DMAC2_DMA_ECO_L___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DMA_ECO_L___S 0 + +#define PHYA_PCSS_DMAC2_DMA_ECO_U (0x00380CBC) +#define PHYA_PCSS_DMAC2_DMA_ECO_U___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DMA_ECO_U___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DMA_ECO_U__DMA_ECO_1___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DMA_ECO_U__DMA_ECO_1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DMA_ECO_U__DMA_ECO_1___S 0 +#define PHYA_PCSS_DMAC2_DMA_ECO_U___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DMA_ECO_U___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B0 (0x00380CC0) +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B0__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B0__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B0__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B0___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B1 (0x00380CD8) +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B1__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B1__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B1__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B1___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B2 (0x00380CF0) +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B2__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B2__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B2__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B2___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B3 (0x00380D08) +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B3__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B3__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B3__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B3___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B4 (0x00380D20) +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B4__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B4__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B4__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B4___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B5 (0x00380D38) +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B5__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B5__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B5__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B5___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B6 (0x00380D50) +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B6__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B6__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B6__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B6___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B7 (0x00380D68) +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B7__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B7__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B7__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_0_L_B7___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B0 (0x00380CC4) +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B0__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B0__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B0__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B0__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B0__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B0__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B0___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B1 (0x00380CDC) +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B1__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B1__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B1__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B1__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B1__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B1__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B1___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B2 (0x00380CF4) +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B2__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B2__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B2__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B2__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B2__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B2__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B2___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B3 (0x00380D0C) +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B3__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B3__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B3__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B3__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B3__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B3__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B3___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B4 (0x00380D24) +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B4__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B4__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B4__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B4__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B4__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B4__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B4___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B5 (0x00380D3C) +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B5__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B5__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B5__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B5__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B5__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B5__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B5___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B6 (0x00380D54) +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B6__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B6__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B6__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B6__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B6__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B6__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B6___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B7 (0x00380D6C) +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B7__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B7__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B7__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B7__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B7__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B7__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_0_U_B7___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B0 (0x00380CC8) +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B0__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B0__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B0__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B0___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B1 (0x00380CE0) +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B1__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B1__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B1__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B1___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B2 (0x00380CF8) +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B2__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B2__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B2__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B2___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B3 (0x00380D10) +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B3__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B3__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B3__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B3___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B4 (0x00380D28) +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B4__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B4__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B4__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B4___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B5 (0x00380D40) +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B5__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B5__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B5__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B5___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B6 (0x00380D58) +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B6__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B6__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B6__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B6___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B7 (0x00380D70) +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B7__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B7__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B7__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_1_L_B7___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B0 (0x00380CCC) +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B0__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B0__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B0__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B0___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B1 (0x00380CE4) +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B1__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B1__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B1__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B1___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B2 (0x00380CFC) +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B2__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B2__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B2__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B2___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B3 (0x00380D14) +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B3__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B3__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B3__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B3___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B4 (0x00380D2C) +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B4__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B4__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B4__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B4___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B5 (0x00380D44) +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B5__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B5__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B5__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B5___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B6 (0x00380D5C) +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B6__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B6__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B6__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B6___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B7 (0x00380D74) +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B7__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B7__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B7__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_1_U_B7___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B0 (0x00380CD0) +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B0__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B0__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B0__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B0___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B1 (0x00380CE8) +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B1__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B1__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B1__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B1___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B2 (0x00380D00) +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B2__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B2__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B2__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B2___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B3 (0x00380D18) +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B3__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B3__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B3__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B3___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B4 (0x00380D30) +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B4__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B4__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B4__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B4___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B5 (0x00380D48) +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B5__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B5__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B5__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B5___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B6 (0x00380D60) +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B6__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B6__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B6__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B6___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B7 (0x00380D78) +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B7__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B7__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B7__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_2_L_B7___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0 (0x00380CD4) +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__FRZDST___S 6 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__FRZSRC___S 5 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__DATSRC___S 2 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0__DESC_EN___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B0___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1 (0x00380CEC) +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__FRZDST___S 6 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__FRZSRC___S 5 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__DATSRC___S 2 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1__DESC_EN___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B1___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2 (0x00380D04) +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__FRZDST___S 6 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__FRZSRC___S 5 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__DATSRC___S 2 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2__DESC_EN___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B2___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3 (0x00380D1C) +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__FRZDST___S 6 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__FRZSRC___S 5 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__DATSRC___S 2 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3__DESC_EN___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B3___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4 (0x00380D34) +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__FRZDST___S 6 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__FRZSRC___S 5 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__DATSRC___S 2 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4__DESC_EN___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B4___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5 (0x00380D4C) +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__FRZDST___S 6 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__FRZSRC___S 5 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__DATSRC___S 2 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5__DESC_EN___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B5___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6 (0x00380D64) +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__FRZDST___S 6 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__FRZSRC___S 5 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__DATSRC___S 2 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6__DESC_EN___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B6___S 0 + +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7 (0x00380D7C) +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__FRZDST___S 6 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__FRZSRC___S 5 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__DATSRC___S 2 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7__DESC_EN___S 0 +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC2_DESC_REG_2_U_B7___S 0 + +#define PHYA_PCSS_DMAC2_DMAC2PHYDBG_EN_REG_L (0x00380D80) +#define PHYA_PCSS_DMAC2_DMAC2PHYDBG_EN_REG_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DMAC2PHYDBG_EN_REG_L___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___POR 0x00 +#define PHYA_PCSS_DMAC2_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___M 0x000000FF +#define PHYA_PCSS_DMAC2_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___S 0 +#define PHYA_PCSS_DMAC2_DMAC2PHYDBG_EN_REG_L___M 0x000000FF +#define PHYA_PCSS_DMAC2_DMAC2PHYDBG_EN_REG_L___S 0 + +#define PHYA_PCSS_DMAC2_DUMMY_L (0x00380E48) +#define PHYA_PCSS_DMAC2_DUMMY_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC2_DUMMY_L___POR 0x00000000 +#define PHYA_PCSS_DMAC2_DUMMY_L__DUMMY___POR 0x0 +#define PHYA_PCSS_DMAC2_DUMMY_L__DUMMY___M 0x00000001 +#define PHYA_PCSS_DMAC2_DUMMY_L__DUMMY___S 0 +#define PHYA_PCSS_DMAC2_DUMMY_L___M 0x00000001 +#define PHYA_PCSS_DMAC2_DUMMY_L___S 0 + +#define PHYA_PCSS_DMAC3_TRIGGER_REG0_L (0x00381000) +#define PHYA_PCSS_DMAC3_TRIGGER_REG0_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_TRIGGER_REG0_L___POR 0x00000000 +#define PHYA_PCSS_DMAC3_TRIGGER_REG0_L__TRIGGER_0___POR 0x0 +#define PHYA_PCSS_DMAC3_TRIGGER_REG0_L__TRIGGER_0___M 0x00000001 +#define PHYA_PCSS_DMAC3_TRIGGER_REG0_L__TRIGGER_0___S 0 +#define PHYA_PCSS_DMAC3_TRIGGER_REG0_L___M 0x00000001 +#define PHYA_PCSS_DMAC3_TRIGGER_REG0_L___S 0 + +#define PHYA_PCSS_DMAC3_TRIGGER_REG1_L (0x00381008) +#define PHYA_PCSS_DMAC3_TRIGGER_REG1_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_TRIGGER_REG1_L___POR 0x00000000 +#define PHYA_PCSS_DMAC3_TRIGGER_REG1_L__TRIGGER_1___POR 0x0 +#define PHYA_PCSS_DMAC3_TRIGGER_REG1_L__TRIGGER_1___M 0x00000001 +#define PHYA_PCSS_DMAC3_TRIGGER_REG1_L__TRIGGER_1___S 0 +#define PHYA_PCSS_DMAC3_TRIGGER_REG1_L___M 0x00000001 +#define PHYA_PCSS_DMAC3_TRIGGER_REG1_L___S 0 + +#define PHYA_PCSS_DMAC3_TRIGGER_REG2_L (0x00381010) +#define PHYA_PCSS_DMAC3_TRIGGER_REG2_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_TRIGGER_REG2_L___POR 0x00000000 +#define PHYA_PCSS_DMAC3_TRIGGER_REG2_L__TRIGGER_2___POR 0x0 +#define PHYA_PCSS_DMAC3_TRIGGER_REG2_L__TRIGGER_2___M 0x00000001 +#define PHYA_PCSS_DMAC3_TRIGGER_REG2_L__TRIGGER_2___S 0 +#define PHYA_PCSS_DMAC3_TRIGGER_REG2_L___M 0x00000001 +#define PHYA_PCSS_DMAC3_TRIGGER_REG2_L___S 0 + +#define PHYA_PCSS_DMAC3_TRIGGER_REG3_L (0x00381018) +#define PHYA_PCSS_DMAC3_TRIGGER_REG3_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_TRIGGER_REG3_L___POR 0x00000000 +#define PHYA_PCSS_DMAC3_TRIGGER_REG3_L__TRIGGER_3___POR 0x0 +#define PHYA_PCSS_DMAC3_TRIGGER_REG3_L__TRIGGER_3___M 0x00000001 +#define PHYA_PCSS_DMAC3_TRIGGER_REG3_L__TRIGGER_3___S 0 +#define PHYA_PCSS_DMAC3_TRIGGER_REG3_L___M 0x00000001 +#define PHYA_PCSS_DMAC3_TRIGGER_REG3_L___S 0 + +#define PHYA_PCSS_DMAC3_TRIGGER_REG4_L (0x00381020) +#define PHYA_PCSS_DMAC3_TRIGGER_REG4_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_TRIGGER_REG4_L___POR 0x00000000 +#define PHYA_PCSS_DMAC3_TRIGGER_REG4_L__TRIGGER_4___POR 0x0 +#define PHYA_PCSS_DMAC3_TRIGGER_REG4_L__TRIGGER_4___M 0x00000001 +#define PHYA_PCSS_DMAC3_TRIGGER_REG4_L__TRIGGER_4___S 0 +#define PHYA_PCSS_DMAC3_TRIGGER_REG4_L___M 0x00000001 +#define PHYA_PCSS_DMAC3_TRIGGER_REG4_L___S 0 + +#define PHYA_PCSS_DMAC3_TRIGGER_REG5_L (0x00381028) +#define PHYA_PCSS_DMAC3_TRIGGER_REG5_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_TRIGGER_REG5_L___POR 0x00000000 +#define PHYA_PCSS_DMAC3_TRIGGER_REG5_L__TRIGGER_5___POR 0x0 +#define PHYA_PCSS_DMAC3_TRIGGER_REG5_L__TRIGGER_5___M 0x00000001 +#define PHYA_PCSS_DMAC3_TRIGGER_REG5_L__TRIGGER_5___S 0 +#define PHYA_PCSS_DMAC3_TRIGGER_REG5_L___M 0x00000001 +#define PHYA_PCSS_DMAC3_TRIGGER_REG5_L___S 0 + +#define PHYA_PCSS_DMAC3_TRIGGER_REG6_L (0x00381030) +#define PHYA_PCSS_DMAC3_TRIGGER_REG6_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_TRIGGER_REG6_L___POR 0x00000000 +#define PHYA_PCSS_DMAC3_TRIGGER_REG6_L__TRIGGER_6___POR 0x0 +#define PHYA_PCSS_DMAC3_TRIGGER_REG6_L__TRIGGER_6___M 0x00000001 +#define PHYA_PCSS_DMAC3_TRIGGER_REG6_L__TRIGGER_6___S 0 +#define PHYA_PCSS_DMAC3_TRIGGER_REG6_L___M 0x00000001 +#define PHYA_PCSS_DMAC3_TRIGGER_REG6_L___S 0 + +#define PHYA_PCSS_DMAC3_TRIGGER_REG7_L (0x00381038) +#define PHYA_PCSS_DMAC3_TRIGGER_REG7_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_TRIGGER_REG7_L___POR 0x00000000 +#define PHYA_PCSS_DMAC3_TRIGGER_REG7_L__TRIGGER_7___POR 0x0 +#define PHYA_PCSS_DMAC3_TRIGGER_REG7_L__TRIGGER_7___M 0x00000001 +#define PHYA_PCSS_DMAC3_TRIGGER_REG7_L__TRIGGER_7___S 0 +#define PHYA_PCSS_DMAC3_TRIGGER_REG7_L___M 0x00000001 +#define PHYA_PCSS_DMAC3_TRIGGER_REG7_L___S 0 + +#define PHYA_PCSS_DMAC3_DUMMY2_REG0_L (0x00381040) +#define PHYA_PCSS_DMAC3_DUMMY2_REG0_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DUMMY2_REG0_L___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DUMMY2_REG0_L__DUMMY2_0___POR 0x0 +#define PHYA_PCSS_DMAC3_DUMMY2_REG0_L__DUMMY2_0___M 0x00000001 +#define PHYA_PCSS_DMAC3_DUMMY2_REG0_L__DUMMY2_0___S 0 +#define PHYA_PCSS_DMAC3_DUMMY2_REG0_L___M 0x00000001 +#define PHYA_PCSS_DMAC3_DUMMY2_REG0_L___S 0 + +#define PHYA_PCSS_DMAC3_DUMMY2_REG1_L (0x00381048) +#define PHYA_PCSS_DMAC3_DUMMY2_REG1_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DUMMY2_REG1_L___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DUMMY2_REG1_L__DUMMY2_1___POR 0x0 +#define PHYA_PCSS_DMAC3_DUMMY2_REG1_L__DUMMY2_1___M 0x00000001 +#define PHYA_PCSS_DMAC3_DUMMY2_REG1_L__DUMMY2_1___S 0 +#define PHYA_PCSS_DMAC3_DUMMY2_REG1_L___M 0x00000001 +#define PHYA_PCSS_DMAC3_DUMMY2_REG1_L___S 0 + +#define PHYA_PCSS_DMAC3_DUMMY2_REG2_L (0x00381050) +#define PHYA_PCSS_DMAC3_DUMMY2_REG2_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DUMMY2_REG2_L___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DUMMY2_REG2_L__DUMMY2_2___POR 0x0 +#define PHYA_PCSS_DMAC3_DUMMY2_REG2_L__DUMMY2_2___M 0x00000001 +#define PHYA_PCSS_DMAC3_DUMMY2_REG2_L__DUMMY2_2___S 0 +#define PHYA_PCSS_DMAC3_DUMMY2_REG2_L___M 0x00000001 +#define PHYA_PCSS_DMAC3_DUMMY2_REG2_L___S 0 + +#define PHYA_PCSS_DMAC3_DUMMY2_REG3_L (0x00381058) +#define PHYA_PCSS_DMAC3_DUMMY2_REG3_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DUMMY2_REG3_L___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DUMMY2_REG3_L__DUMMY2_3___POR 0x0 +#define PHYA_PCSS_DMAC3_DUMMY2_REG3_L__DUMMY2_3___M 0x00000001 +#define PHYA_PCSS_DMAC3_DUMMY2_REG3_L__DUMMY2_3___S 0 +#define PHYA_PCSS_DMAC3_DUMMY2_REG3_L___M 0x00000001 +#define PHYA_PCSS_DMAC3_DUMMY2_REG3_L___S 0 + +#define PHYA_PCSS_DMAC3_DUMMY2_REG4_L (0x00381060) +#define PHYA_PCSS_DMAC3_DUMMY2_REG4_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DUMMY2_REG4_L___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DUMMY2_REG4_L__DUMMY2_4___POR 0x0 +#define PHYA_PCSS_DMAC3_DUMMY2_REG4_L__DUMMY2_4___M 0x00000001 +#define PHYA_PCSS_DMAC3_DUMMY2_REG4_L__DUMMY2_4___S 0 +#define PHYA_PCSS_DMAC3_DUMMY2_REG4_L___M 0x00000001 +#define PHYA_PCSS_DMAC3_DUMMY2_REG4_L___S 0 + +#define PHYA_PCSS_DMAC3_DUMMY2_REG5_L (0x00381068) +#define PHYA_PCSS_DMAC3_DUMMY2_REG5_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DUMMY2_REG5_L___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DUMMY2_REG5_L__DUMMY2_5___POR 0x0 +#define PHYA_PCSS_DMAC3_DUMMY2_REG5_L__DUMMY2_5___M 0x00000001 +#define PHYA_PCSS_DMAC3_DUMMY2_REG5_L__DUMMY2_5___S 0 +#define PHYA_PCSS_DMAC3_DUMMY2_REG5_L___M 0x00000001 +#define PHYA_PCSS_DMAC3_DUMMY2_REG5_L___S 0 + +#define PHYA_PCSS_DMAC3_DUMMY2_REG6_L (0x00381070) +#define PHYA_PCSS_DMAC3_DUMMY2_REG6_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DUMMY2_REG6_L___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DUMMY2_REG6_L__DUMMY2_6___POR 0x0 +#define PHYA_PCSS_DMAC3_DUMMY2_REG6_L__DUMMY2_6___M 0x00000001 +#define PHYA_PCSS_DMAC3_DUMMY2_REG6_L__DUMMY2_6___S 0 +#define PHYA_PCSS_DMAC3_DUMMY2_REG6_L___M 0x00000001 +#define PHYA_PCSS_DMAC3_DUMMY2_REG6_L___S 0 + +#define PHYA_PCSS_DMAC3_DUMMY2_REG7_L (0x00381078) +#define PHYA_PCSS_DMAC3_DUMMY2_REG7_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DUMMY2_REG7_L___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DUMMY2_REG7_L__DUMMY2_7___POR 0x0 +#define PHYA_PCSS_DMAC3_DUMMY2_REG7_L__DUMMY2_7___M 0x00000001 +#define PHYA_PCSS_DMAC3_DUMMY2_REG7_L__DUMMY2_7___S 0 +#define PHYA_PCSS_DMAC3_DUMMY2_REG7_L___M 0x00000001 +#define PHYA_PCSS_DMAC3_DUMMY2_REG7_L___S 0 + +#define PHYA_PCSS_DMAC3_DMA_CTRL_L (0x00381080) +#define PHYA_PCSS_DMAC3_DMA_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DMA_CTRL_L___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DMA_CTRL_L__DMAC_EN___POR 0x0 +#define PHYA_PCSS_DMAC3_DMA_CTRL_L__DMAC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC3_DMA_CTRL_L__DMAC_EN___S 0 +#define PHYA_PCSS_DMAC3_DMA_CTRL_L___M 0x00000001 +#define PHYA_PCSS_DMAC3_DMA_CTRL_L___S 0 + +#define PHYA_PCSS_DMAC3_DMA_CTRL_U (0x00381084) +#define PHYA_PCSS_DMAC3_DMA_CTRL_U___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DMA_CTRL_U___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DMA_CTRL_U__EVTI_XFER_STOP___POR 0x00 +#define PHYA_PCSS_DMAC3_DMA_CTRL_U__EVTI_XFER_STOP___M 0x0000003F +#define PHYA_PCSS_DMAC3_DMA_CTRL_U__EVTI_XFER_STOP___S 0 +#define PHYA_PCSS_DMAC3_DMA_CTRL_U___M 0x0000003F +#define PHYA_PCSS_DMAC3_DMA_CTRL_U___S 0 + +#define PHYA_PCSS_DMAC3_DMA_STATUS_0_L (0x00381088) +#define PHYA_PCSS_DMAC3_DMA_STATUS_0_L___RWC QCSR_REG_RO +#define PHYA_PCSS_DMAC3_DMA_STATUS_0_L___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DMA_STATUS_0_L__CTRL_FSM_STATE___POR 0x0 +#define PHYA_PCSS_DMAC3_DMA_STATUS_0_L__DESC_LAST___POR 0x0 +#define PHYA_PCSS_DMAC3_DMA_STATUS_0_L__DESC_ACTIVE___POR 0x0 +#define PHYA_PCSS_DMAC3_DMA_STATUS_0_L__DMAC_ACTIVE___POR 0x0 +#define PHYA_PCSS_DMAC3_DMA_STATUS_0_L__CTRL_FSM_STATE___M 0x0F000000 +#define PHYA_PCSS_DMAC3_DMA_STATUS_0_L__CTRL_FSM_STATE___S 24 +#define PHYA_PCSS_DMAC3_DMA_STATUS_0_L__DESC_LAST___M 0x000F0000 +#define PHYA_PCSS_DMAC3_DMA_STATUS_0_L__DESC_LAST___S 16 +#define PHYA_PCSS_DMAC3_DMA_STATUS_0_L__DESC_ACTIVE___M 0x00000F00 +#define PHYA_PCSS_DMAC3_DMA_STATUS_0_L__DESC_ACTIVE___S 8 +#define PHYA_PCSS_DMAC3_DMA_STATUS_0_L__DMAC_ACTIVE___M 0x00000001 +#define PHYA_PCSS_DMAC3_DMA_STATUS_0_L__DMAC_ACTIVE___S 0 +#define PHYA_PCSS_DMAC3_DMA_STATUS_0_L___M 0x0F0F0F01 +#define PHYA_PCSS_DMAC3_DMA_STATUS_0_L___S 0 + +#define PHYA_PCSS_DMAC3_DMA_STATUS_0_U (0x0038108C) +#define PHYA_PCSS_DMAC3_DMA_STATUS_0_U___RWC QCSR_REG_RO +#define PHYA_PCSS_DMAC3_DMA_STATUS_0_U___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DMA_STATUS_0_U__XFER_FIFO_OCC___POR 0x000 +#define PHYA_PCSS_DMAC3_DMA_STATUS_0_U__ALEN_FIFO_OCC___POR 0x0 +#define PHYA_PCSS_DMAC3_DMA_STATUS_0_U__DP_FSM_STATE___POR 0x0 +#define PHYA_PCSS_DMAC3_DMA_STATUS_0_U__XFER_FIFO_OCC___M 0x01FF0000 +#define PHYA_PCSS_DMAC3_DMA_STATUS_0_U__XFER_FIFO_OCC___S 16 +#define PHYA_PCSS_DMAC3_DMA_STATUS_0_U__ALEN_FIFO_OCC___M 0x00000F00 +#define PHYA_PCSS_DMAC3_DMA_STATUS_0_U__ALEN_FIFO_OCC___S 8 +#define PHYA_PCSS_DMAC3_DMA_STATUS_0_U__DP_FSM_STATE___M 0x0000000F +#define PHYA_PCSS_DMAC3_DMA_STATUS_0_U__DP_FSM_STATE___S 0 +#define PHYA_PCSS_DMAC3_DMA_STATUS_0_U___M 0x01FF0F0F +#define PHYA_PCSS_DMAC3_DMA_STATUS_0_U___S 0 + +#define PHYA_PCSS_DMAC3_DMA_STATUS_1_L (0x00381090) +#define PHYA_PCSS_DMAC3_DMA_STATUS_1_L___RWC QCSR_REG_RO +#define PHYA_PCSS_DMAC3_DMA_STATUS_1_L___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DMA_STATUS_1_L__XFER_LEN_PEND___POR 0x000000 +#define PHYA_PCSS_DMAC3_DMA_STATUS_1_L__XFER_LEN_PEND___M 0x00FFFFFF +#define PHYA_PCSS_DMAC3_DMA_STATUS_1_L__XFER_LEN_PEND___S 0 +#define PHYA_PCSS_DMAC3_DMA_STATUS_1_L___M 0x00FFFFFF +#define PHYA_PCSS_DMAC3_DMA_STATUS_1_L___S 0 + +#define PHYA_PCSS_DMAC3_DMA_EVT_LATCH_L (0x00381098) +#define PHYA_PCSS_DMAC3_DMA_EVT_LATCH_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DMA_EVT_LATCH_L___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___S 0 +#define PHYA_PCSS_DMAC3_DMA_EVT_LATCH_L___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DMA_EVT_LATCH_L___S 0 + +#define PHYA_PCSS_DMAC3_DMA_EVT_LATCH_U (0x0038109C) +#define PHYA_PCSS_DMAC3_DMA_EVT_LATCH_U___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DMA_EVT_LATCH_U___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___S 0 +#define PHYA_PCSS_DMAC3_DMA_EVT_LATCH_U___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DMA_EVT_LATCH_U___S 0 + +#define PHYA_PCSS_DMAC3_DMA_EVT_TRIG_L (0x003810A0) +#define PHYA_PCSS_DMAC3_DMA_EVT_TRIG_L___RWC QCSR_REG_RO +#define PHYA_PCSS_DMAC3_DMA_EVT_TRIG_L___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DMA_EVT_TRIG_L__CUR_EVT_TRIG___POR 0x00 +#define PHYA_PCSS_DMAC3_DMA_EVT_TRIG_L__LAST_EVT_TRIG___POR 0x00 +#define PHYA_PCSS_DMAC3_DMA_EVT_TRIG_L__CUR_EVT_TRIG___M 0x0000FF00 +#define PHYA_PCSS_DMAC3_DMA_EVT_TRIG_L__CUR_EVT_TRIG___S 8 +#define PHYA_PCSS_DMAC3_DMA_EVT_TRIG_L__LAST_EVT_TRIG___M 0x000000FF +#define PHYA_PCSS_DMAC3_DMA_EVT_TRIG_L__LAST_EVT_TRIG___S 0 +#define PHYA_PCSS_DMAC3_DMA_EVT_TRIG_L___M 0x0000FFFF +#define PHYA_PCSS_DMAC3_DMA_EVT_TRIG_L___S 0 + +#define PHYA_PCSS_DMAC3_DMA_XFER_CTRL_L (0x003810A8) +#define PHYA_PCSS_DMAC3_DMA_XFER_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DMA_XFER_CTRL_L___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___POR 0x0 +#define PHYA_PCSS_DMAC3_DMA_XFER_CTRL_L__PAUSE_XFER___POR 0x0 +#define PHYA_PCSS_DMAC3_DMA_XFER_CTRL_L__STOP_XFER_MASK___POR 0x00 +#define PHYA_PCSS_DMAC3_DMA_XFER_CTRL_L__STOP_XFER___POR 0x0 +#define PHYA_PCSS_DMAC3_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___M 0x00040000 +#define PHYA_PCSS_DMAC3_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___S 18 +#define PHYA_PCSS_DMAC3_DMA_XFER_CTRL_L__PAUSE_XFER___M 0x00020000 +#define PHYA_PCSS_DMAC3_DMA_XFER_CTRL_L__PAUSE_XFER___S 17 +#define PHYA_PCSS_DMAC3_DMA_XFER_CTRL_L__STOP_XFER_MASK___M 0x000001FE +#define PHYA_PCSS_DMAC3_DMA_XFER_CTRL_L__STOP_XFER_MASK___S 1 +#define PHYA_PCSS_DMAC3_DMA_XFER_CTRL_L__STOP_XFER___M 0x00000001 +#define PHYA_PCSS_DMAC3_DMA_XFER_CTRL_L__STOP_XFER___S 0 +#define PHYA_PCSS_DMAC3_DMA_XFER_CTRL_L___M 0x000601FF +#define PHYA_PCSS_DMAC3_DMA_XFER_CTRL_L___S 0 + +#define PHYA_PCSS_DMAC3_DMA_SPARE_L (0x003810B0) +#define PHYA_PCSS_DMAC3_DMA_SPARE_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DMA_SPARE_L___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DMA_SPARE_L__DMA_SPARE_0___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DMA_SPARE_L__DMA_SPARE_0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DMA_SPARE_L__DMA_SPARE_0___S 0 +#define PHYA_PCSS_DMAC3_DMA_SPARE_L___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DMA_SPARE_L___S 0 + +#define PHYA_PCSS_DMAC3_DMA_SPARE_U (0x003810B4) +#define PHYA_PCSS_DMAC3_DMA_SPARE_U___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DMA_SPARE_U___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DMA_SPARE_U__DMA_SPARE_1___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DMA_SPARE_U__DMA_SPARE_1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DMA_SPARE_U__DMA_SPARE_1___S 0 +#define PHYA_PCSS_DMAC3_DMA_SPARE_U___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DMA_SPARE_U___S 0 + +#define PHYA_PCSS_DMAC3_DMA_ECO_L (0x003810B8) +#define PHYA_PCSS_DMAC3_DMA_ECO_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DMA_ECO_L___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DMA_ECO_L__DMA_ECO_0___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DMA_ECO_L__DMA_ECO_0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DMA_ECO_L__DMA_ECO_0___S 0 +#define PHYA_PCSS_DMAC3_DMA_ECO_L___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DMA_ECO_L___S 0 + +#define PHYA_PCSS_DMAC3_DMA_ECO_U (0x003810BC) +#define PHYA_PCSS_DMAC3_DMA_ECO_U___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DMA_ECO_U___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DMA_ECO_U__DMA_ECO_1___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DMA_ECO_U__DMA_ECO_1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DMA_ECO_U__DMA_ECO_1___S 0 +#define PHYA_PCSS_DMAC3_DMA_ECO_U___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DMA_ECO_U___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B0 (0x003810C0) +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B0__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B0__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B0__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B0___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B1 (0x003810D8) +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B1__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B1__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B1__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B1___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B2 (0x003810F0) +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B2__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B2__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B2__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B2___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B3 (0x00381108) +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B3__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B3__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B3__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B3___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B4 (0x00381120) +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B4__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B4__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B4__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B4___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B5 (0x00381138) +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B5__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B5__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B5__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B5___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B6 (0x00381150) +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B6__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B6__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B6__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B6___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B7 (0x00381168) +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B7__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B7__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B7__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_0_L_B7___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B0 (0x003810C4) +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B0__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B0__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B0__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B0__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B0__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B0__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B0___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B1 (0x003810DC) +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B1__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B1__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B1__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B1__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B1__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B1__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B1___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B2 (0x003810F4) +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B2__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B2__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B2__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B2__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B2__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B2__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B2___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B3 (0x0038110C) +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B3__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B3__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B3__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B3__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B3__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B3__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B3___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B4 (0x00381124) +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B4__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B4__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B4__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B4__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B4__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B4__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B4___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B5 (0x0038113C) +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B5__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B5__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B5__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B5__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B5__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B5__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B5___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B6 (0x00381154) +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B6__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B6__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B6__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B6__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B6__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B6__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B6___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B7 (0x0038116C) +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B7__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B7__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B7__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B7__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B7__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B7__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_0_U_B7___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B0 (0x003810C8) +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B0__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B0__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B0__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B0___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B1 (0x003810E0) +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B1__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B1__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B1__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B1___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B2 (0x003810F8) +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B2__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B2__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B2__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B2___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B3 (0x00381110) +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B3__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B3__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B3__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B3___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B4 (0x00381128) +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B4__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B4__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B4__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B4___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B5 (0x00381140) +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B5__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B5__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B5__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B5___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B6 (0x00381158) +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B6__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B6__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B6__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B6___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B7 (0x00381170) +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B7__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B7__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B7__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_1_L_B7___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B0 (0x003810CC) +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B0__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B0__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B0__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B0___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B1 (0x003810E4) +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B1__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B1__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B1__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B1___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B2 (0x003810FC) +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B2__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B2__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B2__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B2___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B3 (0x00381114) +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B3__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B3__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B3__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B3___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B4 (0x0038112C) +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B4__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B4__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B4__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B4___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B5 (0x00381144) +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B5__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B5__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B5__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B5___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B6 (0x0038115C) +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B6__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B6__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B6__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B6___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B7 (0x00381174) +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B7__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B7__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B7__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_1_U_B7___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B0 (0x003810D0) +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B0__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B0__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B0__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B0___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B1 (0x003810E8) +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B1__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B1__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B1__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B1___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B2 (0x00381100) +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B2__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B2__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B2__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B2___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B3 (0x00381118) +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B3__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B3__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B3__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B3___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B4 (0x00381130) +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B4__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B4__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B4__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B4___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B5 (0x00381148) +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B5__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B5__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B5__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B5___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B6 (0x00381160) +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B6__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B6__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B6__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B6___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B7 (0x00381178) +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B7__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B7__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B7__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_2_L_B7___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0 (0x003810D4) +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__FRZDST___S 6 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__FRZSRC___S 5 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__DATSRC___S 2 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0__DESC_EN___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B0___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1 (0x003810EC) +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__FRZDST___S 6 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__FRZSRC___S 5 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__DATSRC___S 2 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1__DESC_EN___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B1___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2 (0x00381104) +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__FRZDST___S 6 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__FRZSRC___S 5 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__DATSRC___S 2 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2__DESC_EN___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B2___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3 (0x0038111C) +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__FRZDST___S 6 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__FRZSRC___S 5 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__DATSRC___S 2 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3__DESC_EN___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B3___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4 (0x00381134) +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__FRZDST___S 6 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__FRZSRC___S 5 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__DATSRC___S 2 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4__DESC_EN___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B4___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5 (0x0038114C) +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__FRZDST___S 6 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__FRZSRC___S 5 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__DATSRC___S 2 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5__DESC_EN___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B5___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6 (0x00381164) +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__FRZDST___S 6 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__FRZSRC___S 5 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__DATSRC___S 2 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6__DESC_EN___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B6___S 0 + +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7 (0x0038117C) +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__FRZDST___S 6 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__FRZSRC___S 5 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__DATSRC___S 2 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7__DESC_EN___S 0 +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC3_DESC_REG_2_U_B7___S 0 + +#define PHYA_PCSS_DMAC3_DMAC2PHYDBG_EN_REG_L (0x00381180) +#define PHYA_PCSS_DMAC3_DMAC2PHYDBG_EN_REG_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DMAC2PHYDBG_EN_REG_L___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___POR 0x00 +#define PHYA_PCSS_DMAC3_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___M 0x000000FF +#define PHYA_PCSS_DMAC3_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___S 0 +#define PHYA_PCSS_DMAC3_DMAC2PHYDBG_EN_REG_L___M 0x000000FF +#define PHYA_PCSS_DMAC3_DMAC2PHYDBG_EN_REG_L___S 0 + +#define PHYA_PCSS_DMAC3_DUMMY_L (0x00381248) +#define PHYA_PCSS_DMAC3_DUMMY_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC3_DUMMY_L___POR 0x00000000 +#define PHYA_PCSS_DMAC3_DUMMY_L__DUMMY___POR 0x0 +#define PHYA_PCSS_DMAC3_DUMMY_L__DUMMY___M 0x00000001 +#define PHYA_PCSS_DMAC3_DUMMY_L__DUMMY___S 0 +#define PHYA_PCSS_DMAC3_DUMMY_L___M 0x00000001 +#define PHYA_PCSS_DMAC3_DUMMY_L___S 0 + +#define PHYA_PCSS_DMAC4_TRIGGER_REG0_L (0x00381400) +#define PHYA_PCSS_DMAC4_TRIGGER_REG0_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_TRIGGER_REG0_L___POR 0x00000000 +#define PHYA_PCSS_DMAC4_TRIGGER_REG0_L__TRIGGER_0___POR 0x0 +#define PHYA_PCSS_DMAC4_TRIGGER_REG0_L__TRIGGER_0___M 0x00000001 +#define PHYA_PCSS_DMAC4_TRIGGER_REG0_L__TRIGGER_0___S 0 +#define PHYA_PCSS_DMAC4_TRIGGER_REG0_L___M 0x00000001 +#define PHYA_PCSS_DMAC4_TRIGGER_REG0_L___S 0 + +#define PHYA_PCSS_DMAC4_TRIGGER_REG1_L (0x00381408) +#define PHYA_PCSS_DMAC4_TRIGGER_REG1_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_TRIGGER_REG1_L___POR 0x00000000 +#define PHYA_PCSS_DMAC4_TRIGGER_REG1_L__TRIGGER_1___POR 0x0 +#define PHYA_PCSS_DMAC4_TRIGGER_REG1_L__TRIGGER_1___M 0x00000001 +#define PHYA_PCSS_DMAC4_TRIGGER_REG1_L__TRIGGER_1___S 0 +#define PHYA_PCSS_DMAC4_TRIGGER_REG1_L___M 0x00000001 +#define PHYA_PCSS_DMAC4_TRIGGER_REG1_L___S 0 + +#define PHYA_PCSS_DMAC4_TRIGGER_REG2_L (0x00381410) +#define PHYA_PCSS_DMAC4_TRIGGER_REG2_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_TRIGGER_REG2_L___POR 0x00000000 +#define PHYA_PCSS_DMAC4_TRIGGER_REG2_L__TRIGGER_2___POR 0x0 +#define PHYA_PCSS_DMAC4_TRIGGER_REG2_L__TRIGGER_2___M 0x00000001 +#define PHYA_PCSS_DMAC4_TRIGGER_REG2_L__TRIGGER_2___S 0 +#define PHYA_PCSS_DMAC4_TRIGGER_REG2_L___M 0x00000001 +#define PHYA_PCSS_DMAC4_TRIGGER_REG2_L___S 0 + +#define PHYA_PCSS_DMAC4_TRIGGER_REG3_L (0x00381418) +#define PHYA_PCSS_DMAC4_TRIGGER_REG3_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_TRIGGER_REG3_L___POR 0x00000000 +#define PHYA_PCSS_DMAC4_TRIGGER_REG3_L__TRIGGER_3___POR 0x0 +#define PHYA_PCSS_DMAC4_TRIGGER_REG3_L__TRIGGER_3___M 0x00000001 +#define PHYA_PCSS_DMAC4_TRIGGER_REG3_L__TRIGGER_3___S 0 +#define PHYA_PCSS_DMAC4_TRIGGER_REG3_L___M 0x00000001 +#define PHYA_PCSS_DMAC4_TRIGGER_REG3_L___S 0 + +#define PHYA_PCSS_DMAC4_TRIGGER_REG4_L (0x00381420) +#define PHYA_PCSS_DMAC4_TRIGGER_REG4_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_TRIGGER_REG4_L___POR 0x00000000 +#define PHYA_PCSS_DMAC4_TRIGGER_REG4_L__TRIGGER_4___POR 0x0 +#define PHYA_PCSS_DMAC4_TRIGGER_REG4_L__TRIGGER_4___M 0x00000001 +#define PHYA_PCSS_DMAC4_TRIGGER_REG4_L__TRIGGER_4___S 0 +#define PHYA_PCSS_DMAC4_TRIGGER_REG4_L___M 0x00000001 +#define PHYA_PCSS_DMAC4_TRIGGER_REG4_L___S 0 + +#define PHYA_PCSS_DMAC4_TRIGGER_REG5_L (0x00381428) +#define PHYA_PCSS_DMAC4_TRIGGER_REG5_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_TRIGGER_REG5_L___POR 0x00000000 +#define PHYA_PCSS_DMAC4_TRIGGER_REG5_L__TRIGGER_5___POR 0x0 +#define PHYA_PCSS_DMAC4_TRIGGER_REG5_L__TRIGGER_5___M 0x00000001 +#define PHYA_PCSS_DMAC4_TRIGGER_REG5_L__TRIGGER_5___S 0 +#define PHYA_PCSS_DMAC4_TRIGGER_REG5_L___M 0x00000001 +#define PHYA_PCSS_DMAC4_TRIGGER_REG5_L___S 0 + +#define PHYA_PCSS_DMAC4_TRIGGER_REG6_L (0x00381430) +#define PHYA_PCSS_DMAC4_TRIGGER_REG6_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_TRIGGER_REG6_L___POR 0x00000000 +#define PHYA_PCSS_DMAC4_TRIGGER_REG6_L__TRIGGER_6___POR 0x0 +#define PHYA_PCSS_DMAC4_TRIGGER_REG6_L__TRIGGER_6___M 0x00000001 +#define PHYA_PCSS_DMAC4_TRIGGER_REG6_L__TRIGGER_6___S 0 +#define PHYA_PCSS_DMAC4_TRIGGER_REG6_L___M 0x00000001 +#define PHYA_PCSS_DMAC4_TRIGGER_REG6_L___S 0 + +#define PHYA_PCSS_DMAC4_TRIGGER_REG7_L (0x00381438) +#define PHYA_PCSS_DMAC4_TRIGGER_REG7_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_TRIGGER_REG7_L___POR 0x00000000 +#define PHYA_PCSS_DMAC4_TRIGGER_REG7_L__TRIGGER_7___POR 0x0 +#define PHYA_PCSS_DMAC4_TRIGGER_REG7_L__TRIGGER_7___M 0x00000001 +#define PHYA_PCSS_DMAC4_TRIGGER_REG7_L__TRIGGER_7___S 0 +#define PHYA_PCSS_DMAC4_TRIGGER_REG7_L___M 0x00000001 +#define PHYA_PCSS_DMAC4_TRIGGER_REG7_L___S 0 + +#define PHYA_PCSS_DMAC4_DUMMY2_REG0_L (0x00381440) +#define PHYA_PCSS_DMAC4_DUMMY2_REG0_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DUMMY2_REG0_L___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DUMMY2_REG0_L__DUMMY2_0___POR 0x0 +#define PHYA_PCSS_DMAC4_DUMMY2_REG0_L__DUMMY2_0___M 0x00000001 +#define PHYA_PCSS_DMAC4_DUMMY2_REG0_L__DUMMY2_0___S 0 +#define PHYA_PCSS_DMAC4_DUMMY2_REG0_L___M 0x00000001 +#define PHYA_PCSS_DMAC4_DUMMY2_REG0_L___S 0 + +#define PHYA_PCSS_DMAC4_DUMMY2_REG1_L (0x00381448) +#define PHYA_PCSS_DMAC4_DUMMY2_REG1_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DUMMY2_REG1_L___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DUMMY2_REG1_L__DUMMY2_1___POR 0x0 +#define PHYA_PCSS_DMAC4_DUMMY2_REG1_L__DUMMY2_1___M 0x00000001 +#define PHYA_PCSS_DMAC4_DUMMY2_REG1_L__DUMMY2_1___S 0 +#define PHYA_PCSS_DMAC4_DUMMY2_REG1_L___M 0x00000001 +#define PHYA_PCSS_DMAC4_DUMMY2_REG1_L___S 0 + +#define PHYA_PCSS_DMAC4_DUMMY2_REG2_L (0x00381450) +#define PHYA_PCSS_DMAC4_DUMMY2_REG2_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DUMMY2_REG2_L___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DUMMY2_REG2_L__DUMMY2_2___POR 0x0 +#define PHYA_PCSS_DMAC4_DUMMY2_REG2_L__DUMMY2_2___M 0x00000001 +#define PHYA_PCSS_DMAC4_DUMMY2_REG2_L__DUMMY2_2___S 0 +#define PHYA_PCSS_DMAC4_DUMMY2_REG2_L___M 0x00000001 +#define PHYA_PCSS_DMAC4_DUMMY2_REG2_L___S 0 + +#define PHYA_PCSS_DMAC4_DUMMY2_REG3_L (0x00381458) +#define PHYA_PCSS_DMAC4_DUMMY2_REG3_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DUMMY2_REG3_L___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DUMMY2_REG3_L__DUMMY2_3___POR 0x0 +#define PHYA_PCSS_DMAC4_DUMMY2_REG3_L__DUMMY2_3___M 0x00000001 +#define PHYA_PCSS_DMAC4_DUMMY2_REG3_L__DUMMY2_3___S 0 +#define PHYA_PCSS_DMAC4_DUMMY2_REG3_L___M 0x00000001 +#define PHYA_PCSS_DMAC4_DUMMY2_REG3_L___S 0 + +#define PHYA_PCSS_DMAC4_DUMMY2_REG4_L (0x00381460) +#define PHYA_PCSS_DMAC4_DUMMY2_REG4_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DUMMY2_REG4_L___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DUMMY2_REG4_L__DUMMY2_4___POR 0x0 +#define PHYA_PCSS_DMAC4_DUMMY2_REG4_L__DUMMY2_4___M 0x00000001 +#define PHYA_PCSS_DMAC4_DUMMY2_REG4_L__DUMMY2_4___S 0 +#define PHYA_PCSS_DMAC4_DUMMY2_REG4_L___M 0x00000001 +#define PHYA_PCSS_DMAC4_DUMMY2_REG4_L___S 0 + +#define PHYA_PCSS_DMAC4_DUMMY2_REG5_L (0x00381468) +#define PHYA_PCSS_DMAC4_DUMMY2_REG5_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DUMMY2_REG5_L___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DUMMY2_REG5_L__DUMMY2_5___POR 0x0 +#define PHYA_PCSS_DMAC4_DUMMY2_REG5_L__DUMMY2_5___M 0x00000001 +#define PHYA_PCSS_DMAC4_DUMMY2_REG5_L__DUMMY2_5___S 0 +#define PHYA_PCSS_DMAC4_DUMMY2_REG5_L___M 0x00000001 +#define PHYA_PCSS_DMAC4_DUMMY2_REG5_L___S 0 + +#define PHYA_PCSS_DMAC4_DUMMY2_REG6_L (0x00381470) +#define PHYA_PCSS_DMAC4_DUMMY2_REG6_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DUMMY2_REG6_L___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DUMMY2_REG6_L__DUMMY2_6___POR 0x0 +#define PHYA_PCSS_DMAC4_DUMMY2_REG6_L__DUMMY2_6___M 0x00000001 +#define PHYA_PCSS_DMAC4_DUMMY2_REG6_L__DUMMY2_6___S 0 +#define PHYA_PCSS_DMAC4_DUMMY2_REG6_L___M 0x00000001 +#define PHYA_PCSS_DMAC4_DUMMY2_REG6_L___S 0 + +#define PHYA_PCSS_DMAC4_DUMMY2_REG7_L (0x00381478) +#define PHYA_PCSS_DMAC4_DUMMY2_REG7_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DUMMY2_REG7_L___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DUMMY2_REG7_L__DUMMY2_7___POR 0x0 +#define PHYA_PCSS_DMAC4_DUMMY2_REG7_L__DUMMY2_7___M 0x00000001 +#define PHYA_PCSS_DMAC4_DUMMY2_REG7_L__DUMMY2_7___S 0 +#define PHYA_PCSS_DMAC4_DUMMY2_REG7_L___M 0x00000001 +#define PHYA_PCSS_DMAC4_DUMMY2_REG7_L___S 0 + +#define PHYA_PCSS_DMAC4_DMA_CTRL_L (0x00381480) +#define PHYA_PCSS_DMAC4_DMA_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DMA_CTRL_L___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DMA_CTRL_L__DMAC_EN___POR 0x0 +#define PHYA_PCSS_DMAC4_DMA_CTRL_L__DMAC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC4_DMA_CTRL_L__DMAC_EN___S 0 +#define PHYA_PCSS_DMAC4_DMA_CTRL_L___M 0x00000001 +#define PHYA_PCSS_DMAC4_DMA_CTRL_L___S 0 + +#define PHYA_PCSS_DMAC4_DMA_CTRL_U (0x00381484) +#define PHYA_PCSS_DMAC4_DMA_CTRL_U___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DMA_CTRL_U___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DMA_CTRL_U__EVTI_XFER_STOP___POR 0x00 +#define PHYA_PCSS_DMAC4_DMA_CTRL_U__EVTI_XFER_STOP___M 0x0000003F +#define PHYA_PCSS_DMAC4_DMA_CTRL_U__EVTI_XFER_STOP___S 0 +#define PHYA_PCSS_DMAC4_DMA_CTRL_U___M 0x0000003F +#define PHYA_PCSS_DMAC4_DMA_CTRL_U___S 0 + +#define PHYA_PCSS_DMAC4_DMA_STATUS_0_L (0x00381488) +#define PHYA_PCSS_DMAC4_DMA_STATUS_0_L___RWC QCSR_REG_RO +#define PHYA_PCSS_DMAC4_DMA_STATUS_0_L___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DMA_STATUS_0_L__CTRL_FSM_STATE___POR 0x0 +#define PHYA_PCSS_DMAC4_DMA_STATUS_0_L__DESC_LAST___POR 0x0 +#define PHYA_PCSS_DMAC4_DMA_STATUS_0_L__DESC_ACTIVE___POR 0x0 +#define PHYA_PCSS_DMAC4_DMA_STATUS_0_L__DMAC_ACTIVE___POR 0x0 +#define PHYA_PCSS_DMAC4_DMA_STATUS_0_L__CTRL_FSM_STATE___M 0x0F000000 +#define PHYA_PCSS_DMAC4_DMA_STATUS_0_L__CTRL_FSM_STATE___S 24 +#define PHYA_PCSS_DMAC4_DMA_STATUS_0_L__DESC_LAST___M 0x000F0000 +#define PHYA_PCSS_DMAC4_DMA_STATUS_0_L__DESC_LAST___S 16 +#define PHYA_PCSS_DMAC4_DMA_STATUS_0_L__DESC_ACTIVE___M 0x00000F00 +#define PHYA_PCSS_DMAC4_DMA_STATUS_0_L__DESC_ACTIVE___S 8 +#define PHYA_PCSS_DMAC4_DMA_STATUS_0_L__DMAC_ACTIVE___M 0x00000001 +#define PHYA_PCSS_DMAC4_DMA_STATUS_0_L__DMAC_ACTIVE___S 0 +#define PHYA_PCSS_DMAC4_DMA_STATUS_0_L___M 0x0F0F0F01 +#define PHYA_PCSS_DMAC4_DMA_STATUS_0_L___S 0 + +#define PHYA_PCSS_DMAC4_DMA_STATUS_0_U (0x0038148C) +#define PHYA_PCSS_DMAC4_DMA_STATUS_0_U___RWC QCSR_REG_RO +#define PHYA_PCSS_DMAC4_DMA_STATUS_0_U___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DMA_STATUS_0_U__XFER_FIFO_OCC___POR 0x000 +#define PHYA_PCSS_DMAC4_DMA_STATUS_0_U__ALEN_FIFO_OCC___POR 0x0 +#define PHYA_PCSS_DMAC4_DMA_STATUS_0_U__DP_FSM_STATE___POR 0x0 +#define PHYA_PCSS_DMAC4_DMA_STATUS_0_U__XFER_FIFO_OCC___M 0x01FF0000 +#define PHYA_PCSS_DMAC4_DMA_STATUS_0_U__XFER_FIFO_OCC___S 16 +#define PHYA_PCSS_DMAC4_DMA_STATUS_0_U__ALEN_FIFO_OCC___M 0x00000F00 +#define PHYA_PCSS_DMAC4_DMA_STATUS_0_U__ALEN_FIFO_OCC___S 8 +#define PHYA_PCSS_DMAC4_DMA_STATUS_0_U__DP_FSM_STATE___M 0x0000000F +#define PHYA_PCSS_DMAC4_DMA_STATUS_0_U__DP_FSM_STATE___S 0 +#define PHYA_PCSS_DMAC4_DMA_STATUS_0_U___M 0x01FF0F0F +#define PHYA_PCSS_DMAC4_DMA_STATUS_0_U___S 0 + +#define PHYA_PCSS_DMAC4_DMA_STATUS_1_L (0x00381490) +#define PHYA_PCSS_DMAC4_DMA_STATUS_1_L___RWC QCSR_REG_RO +#define PHYA_PCSS_DMAC4_DMA_STATUS_1_L___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DMA_STATUS_1_L__XFER_LEN_PEND___POR 0x000000 +#define PHYA_PCSS_DMAC4_DMA_STATUS_1_L__XFER_LEN_PEND___M 0x00FFFFFF +#define PHYA_PCSS_DMAC4_DMA_STATUS_1_L__XFER_LEN_PEND___S 0 +#define PHYA_PCSS_DMAC4_DMA_STATUS_1_L___M 0x00FFFFFF +#define PHYA_PCSS_DMAC4_DMA_STATUS_1_L___S 0 + +#define PHYA_PCSS_DMAC4_DMA_EVT_LATCH_L (0x00381498) +#define PHYA_PCSS_DMAC4_DMA_EVT_LATCH_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DMA_EVT_LATCH_L___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___S 0 +#define PHYA_PCSS_DMAC4_DMA_EVT_LATCH_L___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DMA_EVT_LATCH_L___S 0 + +#define PHYA_PCSS_DMAC4_DMA_EVT_LATCH_U (0x0038149C) +#define PHYA_PCSS_DMAC4_DMA_EVT_LATCH_U___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DMA_EVT_LATCH_U___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___S 0 +#define PHYA_PCSS_DMAC4_DMA_EVT_LATCH_U___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DMA_EVT_LATCH_U___S 0 + +#define PHYA_PCSS_DMAC4_DMA_EVT_TRIG_L (0x003814A0) +#define PHYA_PCSS_DMAC4_DMA_EVT_TRIG_L___RWC QCSR_REG_RO +#define PHYA_PCSS_DMAC4_DMA_EVT_TRIG_L___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DMA_EVT_TRIG_L__CUR_EVT_TRIG___POR 0x00 +#define PHYA_PCSS_DMAC4_DMA_EVT_TRIG_L__LAST_EVT_TRIG___POR 0x00 +#define PHYA_PCSS_DMAC4_DMA_EVT_TRIG_L__CUR_EVT_TRIG___M 0x0000FF00 +#define PHYA_PCSS_DMAC4_DMA_EVT_TRIG_L__CUR_EVT_TRIG___S 8 +#define PHYA_PCSS_DMAC4_DMA_EVT_TRIG_L__LAST_EVT_TRIG___M 0x000000FF +#define PHYA_PCSS_DMAC4_DMA_EVT_TRIG_L__LAST_EVT_TRIG___S 0 +#define PHYA_PCSS_DMAC4_DMA_EVT_TRIG_L___M 0x0000FFFF +#define PHYA_PCSS_DMAC4_DMA_EVT_TRIG_L___S 0 + +#define PHYA_PCSS_DMAC4_DMA_XFER_CTRL_L (0x003814A8) +#define PHYA_PCSS_DMAC4_DMA_XFER_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DMA_XFER_CTRL_L___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___POR 0x0 +#define PHYA_PCSS_DMAC4_DMA_XFER_CTRL_L__PAUSE_XFER___POR 0x0 +#define PHYA_PCSS_DMAC4_DMA_XFER_CTRL_L__STOP_XFER_MASK___POR 0x00 +#define PHYA_PCSS_DMAC4_DMA_XFER_CTRL_L__STOP_XFER___POR 0x0 +#define PHYA_PCSS_DMAC4_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___M 0x00040000 +#define PHYA_PCSS_DMAC4_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___S 18 +#define PHYA_PCSS_DMAC4_DMA_XFER_CTRL_L__PAUSE_XFER___M 0x00020000 +#define PHYA_PCSS_DMAC4_DMA_XFER_CTRL_L__PAUSE_XFER___S 17 +#define PHYA_PCSS_DMAC4_DMA_XFER_CTRL_L__STOP_XFER_MASK___M 0x000001FE +#define PHYA_PCSS_DMAC4_DMA_XFER_CTRL_L__STOP_XFER_MASK___S 1 +#define PHYA_PCSS_DMAC4_DMA_XFER_CTRL_L__STOP_XFER___M 0x00000001 +#define PHYA_PCSS_DMAC4_DMA_XFER_CTRL_L__STOP_XFER___S 0 +#define PHYA_PCSS_DMAC4_DMA_XFER_CTRL_L___M 0x000601FF +#define PHYA_PCSS_DMAC4_DMA_XFER_CTRL_L___S 0 + +#define PHYA_PCSS_DMAC4_DMA_SPARE_L (0x003814B0) +#define PHYA_PCSS_DMAC4_DMA_SPARE_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DMA_SPARE_L___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DMA_SPARE_L__DMA_SPARE_0___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DMA_SPARE_L__DMA_SPARE_0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DMA_SPARE_L__DMA_SPARE_0___S 0 +#define PHYA_PCSS_DMAC4_DMA_SPARE_L___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DMA_SPARE_L___S 0 + +#define PHYA_PCSS_DMAC4_DMA_SPARE_U (0x003814B4) +#define PHYA_PCSS_DMAC4_DMA_SPARE_U___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DMA_SPARE_U___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DMA_SPARE_U__DMA_SPARE_1___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DMA_SPARE_U__DMA_SPARE_1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DMA_SPARE_U__DMA_SPARE_1___S 0 +#define PHYA_PCSS_DMAC4_DMA_SPARE_U___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DMA_SPARE_U___S 0 + +#define PHYA_PCSS_DMAC4_DMA_ECO_L (0x003814B8) +#define PHYA_PCSS_DMAC4_DMA_ECO_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DMA_ECO_L___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DMA_ECO_L__DMA_ECO_0___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DMA_ECO_L__DMA_ECO_0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DMA_ECO_L__DMA_ECO_0___S 0 +#define PHYA_PCSS_DMAC4_DMA_ECO_L___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DMA_ECO_L___S 0 + +#define PHYA_PCSS_DMAC4_DMA_ECO_U (0x003814BC) +#define PHYA_PCSS_DMAC4_DMA_ECO_U___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DMA_ECO_U___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DMA_ECO_U__DMA_ECO_1___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DMA_ECO_U__DMA_ECO_1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DMA_ECO_U__DMA_ECO_1___S 0 +#define PHYA_PCSS_DMAC4_DMA_ECO_U___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DMA_ECO_U___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B0 (0x003814C0) +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B0__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B0__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B0__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B0___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B1 (0x003814D8) +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B1__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B1__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B1__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B1___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B2 (0x003814F0) +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B2__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B2__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B2__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B2___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B3 (0x00381508) +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B3__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B3__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B3__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B3___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B4 (0x00381520) +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B4__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B4__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B4__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B4___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B5 (0x00381538) +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B5__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B5__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B5__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B5___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B6 (0x00381550) +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B6__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B6__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B6__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B6___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B7 (0x00381568) +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B7__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B7__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B7__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_0_L_B7___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B0 (0x003814C4) +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B0__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B0__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B0__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B0__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B0__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B0__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B0___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B1 (0x003814DC) +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B1__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B1__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B1__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B1__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B1__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B1__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B1___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B2 (0x003814F4) +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B2__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B2__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B2__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B2__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B2__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B2__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B2___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B3 (0x0038150C) +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B3__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B3__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B3__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B3__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B3__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B3__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B3___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B4 (0x00381524) +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B4__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B4__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B4__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B4__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B4__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B4__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B4___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B5 (0x0038153C) +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B5__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B5__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B5__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B5__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B5__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B5__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B5___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B6 (0x00381554) +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B6__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B6__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B6__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B6__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B6__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B6__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B6___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B7 (0x0038156C) +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B7__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B7__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B7__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B7__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B7__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B7__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_0_U_B7___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B0 (0x003814C8) +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B0__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B0__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B0__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B0___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B1 (0x003814E0) +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B1__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B1__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B1__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B1___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B2 (0x003814F8) +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B2__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B2__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B2__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B2___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B3 (0x00381510) +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B3__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B3__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B3__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B3___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B4 (0x00381528) +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B4__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B4__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B4__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B4___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B5 (0x00381540) +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B5__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B5__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B5__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B5___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B6 (0x00381558) +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B6__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B6__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B6__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B6___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B7 (0x00381570) +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B7__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B7__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B7__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_1_L_B7___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B0 (0x003814CC) +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B0__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B0__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B0__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B0___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B1 (0x003814E4) +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B1__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B1__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B1__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B1___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B2 (0x003814FC) +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B2__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B2__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B2__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B2___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B3 (0x00381514) +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B3__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B3__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B3__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B3___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B4 (0x0038152C) +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B4__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B4__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B4__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B4___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B5 (0x00381544) +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B5__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B5__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B5__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B5___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B6 (0x0038155C) +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B6__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B6__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B6__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B6___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B7 (0x00381574) +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B7__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B7__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B7__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_1_U_B7___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B0 (0x003814D0) +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B0__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B0__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B0__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B0___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B1 (0x003814E8) +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B1__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B1__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B1__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B1___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B2 (0x00381500) +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B2__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B2__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B2__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B2___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B3 (0x00381518) +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B3__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B3__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B3__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B3___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B4 (0x00381530) +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B4__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B4__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B4__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B4___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B5 (0x00381548) +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B5__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B5__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B5__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B5___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B6 (0x00381560) +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B6__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B6__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B6__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B6___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B7 (0x00381578) +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B7__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B7__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B7__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_2_L_B7___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0 (0x003814D4) +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__FRZDST___S 6 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__FRZSRC___S 5 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__DATSRC___S 2 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0__DESC_EN___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B0___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1 (0x003814EC) +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__FRZDST___S 6 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__FRZSRC___S 5 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__DATSRC___S 2 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1__DESC_EN___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B1___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2 (0x00381504) +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__FRZDST___S 6 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__FRZSRC___S 5 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__DATSRC___S 2 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2__DESC_EN___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B2___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3 (0x0038151C) +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__FRZDST___S 6 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__FRZSRC___S 5 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__DATSRC___S 2 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3__DESC_EN___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B3___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4 (0x00381534) +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__FRZDST___S 6 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__FRZSRC___S 5 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__DATSRC___S 2 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4__DESC_EN___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B4___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5 (0x0038154C) +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__FRZDST___S 6 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__FRZSRC___S 5 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__DATSRC___S 2 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5__DESC_EN___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B5___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6 (0x00381564) +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__FRZDST___S 6 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__FRZSRC___S 5 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__DATSRC___S 2 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6__DESC_EN___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B6___S 0 + +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7 (0x0038157C) +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__FRZDST___S 6 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__FRZSRC___S 5 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__DATSRC___S 2 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7__DESC_EN___S 0 +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC4_DESC_REG_2_U_B7___S 0 + +#define PHYA_PCSS_DMAC4_DMAC2PHYDBG_EN_REG_L (0x00381580) +#define PHYA_PCSS_DMAC4_DMAC2PHYDBG_EN_REG_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DMAC2PHYDBG_EN_REG_L___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___POR 0x00 +#define PHYA_PCSS_DMAC4_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___M 0x000000FF +#define PHYA_PCSS_DMAC4_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___S 0 +#define PHYA_PCSS_DMAC4_DMAC2PHYDBG_EN_REG_L___M 0x000000FF +#define PHYA_PCSS_DMAC4_DMAC2PHYDBG_EN_REG_L___S 0 + +#define PHYA_PCSS_DMAC4_DUMMY_L (0x00381648) +#define PHYA_PCSS_DMAC4_DUMMY_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC4_DUMMY_L___POR 0x00000000 +#define PHYA_PCSS_DMAC4_DUMMY_L__DUMMY___POR 0x0 +#define PHYA_PCSS_DMAC4_DUMMY_L__DUMMY___M 0x00000001 +#define PHYA_PCSS_DMAC4_DUMMY_L__DUMMY___S 0 +#define PHYA_PCSS_DMAC4_DUMMY_L___M 0x00000001 +#define PHYA_PCSS_DMAC4_DUMMY_L___S 0 + +#define PHYA_PCSS_DUALT_TIMER0_LOAD_VALUE_L (0x00381800) +#define PHYA_PCSS_DUALT_TIMER0_LOAD_VALUE_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DUALT_TIMER0_LOAD_VALUE_L___POR 0x00000000 +#define PHYA_PCSS_DUALT_TIMER0_LOAD_VALUE_L__TIMER0_TIMERLOAD___POR 0x00000000 +#define PHYA_PCSS_DUALT_TIMER0_LOAD_VALUE_L__TIMER0_TIMERLOAD___M 0xFFFFFFFF +#define PHYA_PCSS_DUALT_TIMER0_LOAD_VALUE_L__TIMER0_TIMERLOAD___S 0 +#define PHYA_PCSS_DUALT_TIMER0_LOAD_VALUE_L___M 0xFFFFFFFF +#define PHYA_PCSS_DUALT_TIMER0_LOAD_VALUE_L___S 0 + +#define PHYA_PCSS_DUALT_TIMER0_LOAD_VALUE_U (0x00381804) +#define PHYA_PCSS_DUALT_TIMER0_LOAD_VALUE_U___RWC QCSR_REG_RO +#define PHYA_PCSS_DUALT_TIMER0_LOAD_VALUE_U___POR 0xFFFFFFFF +#define PHYA_PCSS_DUALT_TIMER0_LOAD_VALUE_U__TIMER0_TIMERVALUE___POR 0xFFFFFFFF +#define PHYA_PCSS_DUALT_TIMER0_LOAD_VALUE_U__TIMER0_TIMERVALUE___M 0xFFFFFFFF +#define PHYA_PCSS_DUALT_TIMER0_LOAD_VALUE_U__TIMER0_TIMERVALUE___S 0 +#define PHYA_PCSS_DUALT_TIMER0_LOAD_VALUE_U___M 0xFFFFFFFF +#define PHYA_PCSS_DUALT_TIMER0_LOAD_VALUE_U___S 0 + +#define PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L (0x00381808) +#define PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L___POR 0x00000020 +#define PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_TIMER_EN___POR 0x0 +#define PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_TIMER_MODE___POR 0x0 +#define PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_INTERRUPT_EN___POR 0x1 +#define PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_TIMER_PRE___POR 0x0 +#define PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_TIMER_SIZE___POR 0x0 +#define PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_ONE_SHOT_COUNT___POR 0x0 +#define PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_TIMER_EN___M 0x00000080 +#define PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_TIMER_EN___S 7 +#define PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_TIMER_MODE___M 0x00000040 +#define PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_TIMER_MODE___S 6 +#define PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_INTERRUPT_EN___M 0x00000020 +#define PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_INTERRUPT_EN___S 5 +#define PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_TIMER_PRE___M 0x0000000C +#define PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_TIMER_PRE___S 2 +#define PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_TIMER_SIZE___M 0x00000002 +#define PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_TIMER_SIZE___S 1 +#define PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_ONE_SHOT_COUNT___M 0x00000001 +#define PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L__TIMER0_ONE_SHOT_COUNT___S 0 +#define PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L___M 0x000000EF +#define PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_L___S 0 + +#define PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_U (0x0038180C) +#define PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_U___RWC QCSR_REG_WO +#define PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_U___POR 0x00000000 +#define PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_U__TIMER0_TIMERINTCLR___POR 0x00000000 +#define PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_U__TIMER0_TIMERINTCLR___M 0xFFFFFFFF +#define PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_U__TIMER0_TIMERINTCLR___S 0 +#define PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_U___M 0xFFFFFFFF +#define PHYA_PCSS_DUALT_TIMER0_CONTROL_CLR_U___S 0 + +#define PHYA_PCSS_DUALT_TIMER0_INTR_STATUS_L (0x00381810) +#define PHYA_PCSS_DUALT_TIMER0_INTR_STATUS_L___RWC QCSR_REG_RO +#define PHYA_PCSS_DUALT_TIMER0_INTR_STATUS_L___POR 0x00000000 +#define PHYA_PCSS_DUALT_TIMER0_INTR_STATUS_L__TIMER0_TIMERRIS___POR 0x0 +#define PHYA_PCSS_DUALT_TIMER0_INTR_STATUS_L__TIMER0_TIMERRIS___M 0x00000001 +#define PHYA_PCSS_DUALT_TIMER0_INTR_STATUS_L__TIMER0_TIMERRIS___S 0 +#define PHYA_PCSS_DUALT_TIMER0_INTR_STATUS_L___M 0x00000001 +#define PHYA_PCSS_DUALT_TIMER0_INTR_STATUS_L___S 0 + +#define PHYA_PCSS_DUALT_TIMER0_INTR_STATUS_U (0x00381814) +#define PHYA_PCSS_DUALT_TIMER0_INTR_STATUS_U___RWC QCSR_REG_RO +#define PHYA_PCSS_DUALT_TIMER0_INTR_STATUS_U___POR 0x00000000 +#define PHYA_PCSS_DUALT_TIMER0_INTR_STATUS_U__TIMER0_TIMERMIS___POR 0x0 +#define PHYA_PCSS_DUALT_TIMER0_INTR_STATUS_U__TIMER0_TIMERMIS___M 0x00000001 +#define PHYA_PCSS_DUALT_TIMER0_INTR_STATUS_U__TIMER0_TIMERMIS___S 0 +#define PHYA_PCSS_DUALT_TIMER0_INTR_STATUS_U___M 0x00000001 +#define PHYA_PCSS_DUALT_TIMER0_INTR_STATUS_U___S 0 + +#define PHYA_PCSS_DUALT_TIMER0_BG_LOAD_L (0x00381818) +#define PHYA_PCSS_DUALT_TIMER0_BG_LOAD_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DUALT_TIMER0_BG_LOAD_L___POR 0x00000000 +#define PHYA_PCSS_DUALT_TIMER0_BG_LOAD_L__TIMER0_TIMERBGLOAD___POR 0x00000000 +#define PHYA_PCSS_DUALT_TIMER0_BG_LOAD_L__TIMER0_TIMERBGLOAD___M 0xFFFFFFFF +#define PHYA_PCSS_DUALT_TIMER0_BG_LOAD_L__TIMER0_TIMERBGLOAD___S 0 +#define PHYA_PCSS_DUALT_TIMER0_BG_LOAD_L___M 0xFFFFFFFF +#define PHYA_PCSS_DUALT_TIMER0_BG_LOAD_L___S 0 + +#define PHYA_PCSS_DUALT_TIMER1_LOAD_VALUE_L (0x00381820) +#define PHYA_PCSS_DUALT_TIMER1_LOAD_VALUE_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DUALT_TIMER1_LOAD_VALUE_L___POR 0x00000000 +#define PHYA_PCSS_DUALT_TIMER1_LOAD_VALUE_L__TIMER1_TIMERLOAD___POR 0x00000000 +#define PHYA_PCSS_DUALT_TIMER1_LOAD_VALUE_L__TIMER1_TIMERLOAD___M 0xFFFFFFFF +#define PHYA_PCSS_DUALT_TIMER1_LOAD_VALUE_L__TIMER1_TIMERLOAD___S 0 +#define PHYA_PCSS_DUALT_TIMER1_LOAD_VALUE_L___M 0xFFFFFFFF +#define PHYA_PCSS_DUALT_TIMER1_LOAD_VALUE_L___S 0 + +#define PHYA_PCSS_DUALT_TIMER1_LOAD_VALUE_U (0x00381824) +#define PHYA_PCSS_DUALT_TIMER1_LOAD_VALUE_U___RWC QCSR_REG_RO +#define PHYA_PCSS_DUALT_TIMER1_LOAD_VALUE_U___POR 0xFFFFFFFF +#define PHYA_PCSS_DUALT_TIMER1_LOAD_VALUE_U__TIMER1_TIMERVALUE___POR 0xFFFFFFFF +#define PHYA_PCSS_DUALT_TIMER1_LOAD_VALUE_U__TIMER1_TIMERVALUE___M 0xFFFFFFFF +#define PHYA_PCSS_DUALT_TIMER1_LOAD_VALUE_U__TIMER1_TIMERVALUE___S 0 +#define PHYA_PCSS_DUALT_TIMER1_LOAD_VALUE_U___M 0xFFFFFFFF +#define PHYA_PCSS_DUALT_TIMER1_LOAD_VALUE_U___S 0 + +#define PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L (0x00381828) +#define PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L___POR 0x00000020 +#define PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_TIMER_EN___POR 0x0 +#define PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_TIMER_MODE___POR 0x0 +#define PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_INTERRUPT_EN___POR 0x1 +#define PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_TIMER_PRE___POR 0x0 +#define PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_TIMER_SIZE___POR 0x0 +#define PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_ONE_SHOT_COUNT___POR 0x0 +#define PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_TIMER_EN___M 0x00000080 +#define PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_TIMER_EN___S 7 +#define PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_TIMER_MODE___M 0x00000040 +#define PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_TIMER_MODE___S 6 +#define PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_INTERRUPT_EN___M 0x00000020 +#define PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_INTERRUPT_EN___S 5 +#define PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_TIMER_PRE___M 0x0000000C +#define PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_TIMER_PRE___S 2 +#define PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_TIMER_SIZE___M 0x00000002 +#define PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_TIMER_SIZE___S 1 +#define PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_ONE_SHOT_COUNT___M 0x00000001 +#define PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L__TIMER1_ONE_SHOT_COUNT___S 0 +#define PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L___M 0x000000EF +#define PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_L___S 0 + +#define PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_U (0x0038182C) +#define PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_U___RWC QCSR_REG_WO +#define PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_U___POR 0x00000000 +#define PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_U__TIMER1_TIMERINTCLR___POR 0x00000000 +#define PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_U__TIMER1_TIMERINTCLR___M 0xFFFFFFFF +#define PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_U__TIMER1_TIMERINTCLR___S 0 +#define PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_U___M 0xFFFFFFFF +#define PHYA_PCSS_DUALT_TIMER1_CONTROL_CLR_U___S 0 + +#define PHYA_PCSS_DUALT_TIMER1_INTR_STATUS_L (0x00381830) +#define PHYA_PCSS_DUALT_TIMER1_INTR_STATUS_L___RWC QCSR_REG_RO +#define PHYA_PCSS_DUALT_TIMER1_INTR_STATUS_L___POR 0x00000000 +#define PHYA_PCSS_DUALT_TIMER1_INTR_STATUS_L__TIMER1_TIMERRIS___POR 0x0 +#define PHYA_PCSS_DUALT_TIMER1_INTR_STATUS_L__TIMER1_TIMERRIS___M 0x00000001 +#define PHYA_PCSS_DUALT_TIMER1_INTR_STATUS_L__TIMER1_TIMERRIS___S 0 +#define PHYA_PCSS_DUALT_TIMER1_INTR_STATUS_L___M 0x00000001 +#define PHYA_PCSS_DUALT_TIMER1_INTR_STATUS_L___S 0 + +#define PHYA_PCSS_DUALT_TIMER1_INTR_STATUS_U (0x00381834) +#define PHYA_PCSS_DUALT_TIMER1_INTR_STATUS_U___RWC QCSR_REG_RO +#define PHYA_PCSS_DUALT_TIMER1_INTR_STATUS_U___POR 0x00000000 +#define PHYA_PCSS_DUALT_TIMER1_INTR_STATUS_U__TIMER1_TIMERMIS___POR 0x0 +#define PHYA_PCSS_DUALT_TIMER1_INTR_STATUS_U__TIMER1_TIMERMIS___M 0x00000001 +#define PHYA_PCSS_DUALT_TIMER1_INTR_STATUS_U__TIMER1_TIMERMIS___S 0 +#define PHYA_PCSS_DUALT_TIMER1_INTR_STATUS_U___M 0x00000001 +#define PHYA_PCSS_DUALT_TIMER1_INTR_STATUS_U___S 0 + +#define PHYA_PCSS_DUALT_TIMER1_BG_LOAD_L (0x00381838) +#define PHYA_PCSS_DUALT_TIMER1_BG_LOAD_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DUALT_TIMER1_BG_LOAD_L___POR 0x00000000 +#define PHYA_PCSS_DUALT_TIMER1_BG_LOAD_L__TIMER1_TIMERBGLOAD___POR 0x00000000 +#define PHYA_PCSS_DUALT_TIMER1_BG_LOAD_L__TIMER1_TIMERBGLOAD___M 0xFFFFFFFF +#define PHYA_PCSS_DUALT_TIMER1_BG_LOAD_L__TIMER1_TIMERBGLOAD___S 0 +#define PHYA_PCSS_DUALT_TIMER1_BG_LOAD_L___M 0xFFFFFFFF +#define PHYA_PCSS_DUALT_TIMER1_BG_LOAD_L___S 0 + +#define PHYA_PCSS_WDOG_WDOGLOAD_L (0x00381C00) +#define PHYA_PCSS_WDOG_WDOGLOAD_L___RWC QCSR_REG_RW +#define PHYA_PCSS_WDOG_WDOGLOAD_L___POR 0xFFFFFFFF +#define PHYA_PCSS_WDOG_WDOGLOAD_L__WDOGLOAD___POR 0xFFFFFFFF +#define PHYA_PCSS_WDOG_WDOGLOAD_L__WDOGLOAD___M 0xFFFFFFFF +#define PHYA_PCSS_WDOG_WDOGLOAD_L__WDOGLOAD___S 0 +#define PHYA_PCSS_WDOG_WDOGLOAD_L___M 0xFFFFFFFF +#define PHYA_PCSS_WDOG_WDOGLOAD_L___S 0 + +#define PHYA_PCSS_WDOG_WDOGLOAD_U (0x00381C04) +#define PHYA_PCSS_WDOG_WDOGLOAD_U___RWC QCSR_REG_RO +#define PHYA_PCSS_WDOG_WDOGLOAD_U___POR 0xFFFFFFFF +#define PHYA_PCSS_WDOG_WDOGLOAD_U__WDOGVALUE___POR 0xFFFFFFFF +#define PHYA_PCSS_WDOG_WDOGLOAD_U__WDOGVALUE___M 0xFFFFFFFF +#define PHYA_PCSS_WDOG_WDOGLOAD_U__WDOGVALUE___S 0 +#define PHYA_PCSS_WDOG_WDOGLOAD_U___M 0xFFFFFFFF +#define PHYA_PCSS_WDOG_WDOGLOAD_U___S 0 + +#define PHYA_PCSS_WDOG_CONTROL_CLR_0_L (0x00381C08) +#define PHYA_PCSS_WDOG_CONTROL_CLR_0_L___RWC QCSR_REG_RW +#define PHYA_PCSS_WDOG_CONTROL_CLR_0_L___POR 0x00000000 +#define PHYA_PCSS_WDOG_CONTROL_CLR_0_L__INTEN___POR 0x0 +#define PHYA_PCSS_WDOG_CONTROL_CLR_0_L__RESEN___POR 0x0 +#define PHYA_PCSS_WDOG_CONTROL_CLR_0_L__INTEN___M 0x00000002 +#define PHYA_PCSS_WDOG_CONTROL_CLR_0_L__INTEN___S 1 +#define PHYA_PCSS_WDOG_CONTROL_CLR_0_L__RESEN___M 0x00000001 +#define PHYA_PCSS_WDOG_CONTROL_CLR_0_L__RESEN___S 0 +#define PHYA_PCSS_WDOG_CONTROL_CLR_0_L___M 0x00000003 +#define PHYA_PCSS_WDOG_CONTROL_CLR_0_L___S 0 + +#define PHYA_PCSS_WDOG_CONTROL_CLR_0_U (0x00381C0C) +#define PHYA_PCSS_WDOG_CONTROL_CLR_0_U___RWC QCSR_REG_WO +#define PHYA_PCSS_WDOG_CONTROL_CLR_0_U___POR 0x00000000 +#define PHYA_PCSS_WDOG_CONTROL_CLR_0_U__WDOGINTCLR___POR 0x0 +#define PHYA_PCSS_WDOG_CONTROL_CLR_0_U__WDOGINTCLR___M 0x00000001 +#define PHYA_PCSS_WDOG_CONTROL_CLR_0_U__WDOGINTCLR___S 0 +#define PHYA_PCSS_WDOG_CONTROL_CLR_0_U___M 0x00000001 +#define PHYA_PCSS_WDOG_CONTROL_CLR_0_U___S 0 + +#define PHYA_PCSS_WDOG_CONTROL_CLR_1_L (0x00381C10) +#define PHYA_PCSS_WDOG_CONTROL_CLR_1_L___RWC QCSR_REG_RO +#define PHYA_PCSS_WDOG_CONTROL_CLR_1_L___POR 0x00000000 +#define PHYA_PCSS_WDOG_CONTROL_CLR_1_L__WDOGRIS___POR 0x0 +#define PHYA_PCSS_WDOG_CONTROL_CLR_1_L__WDOGRIS___M 0x00000001 +#define PHYA_PCSS_WDOG_CONTROL_CLR_1_L__WDOGRIS___S 0 +#define PHYA_PCSS_WDOG_CONTROL_CLR_1_L___M 0x00000001 +#define PHYA_PCSS_WDOG_CONTROL_CLR_1_L___S 0 + +#define PHYA_PCSS_WDOG_CONTROL_CLR_1_U (0x00381C14) +#define PHYA_PCSS_WDOG_CONTROL_CLR_1_U___RWC QCSR_REG_RO +#define PHYA_PCSS_WDOG_CONTROL_CLR_1_U___POR 0x00000000 +#define PHYA_PCSS_WDOG_CONTROL_CLR_1_U__WDOGMIS___POR 0x0 +#define PHYA_PCSS_WDOG_CONTROL_CLR_1_U__WDOGMIS___M 0x00000001 +#define PHYA_PCSS_WDOG_CONTROL_CLR_1_U__WDOGMIS___S 0 +#define PHYA_PCSS_WDOG_CONTROL_CLR_1_U___M 0x00000001 +#define PHYA_PCSS_WDOG_CONTROL_CLR_1_U___S 0 + +#define PHYA_PCSS_WDOG_CONTROL_CLR_2_L (0x00382800) +#define PHYA_PCSS_WDOG_CONTROL_CLR_2_L___RWC QCSR_REG_RW +#define PHYA_PCSS_WDOG_CONTROL_CLR_2_L___POR 0x00000000 +#define PHYA_PCSS_WDOG_CONTROL_CLR_2_L__WDOGLOCK___POR 0x00000000 +#define PHYA_PCSS_WDOG_CONTROL_CLR_2_L__WDOGLOCK___M 0xFFFFFFFF +#define PHYA_PCSS_WDOG_CONTROL_CLR_2_L__WDOGLOCK___S 0 +#define PHYA_PCSS_WDOG_CONTROL_CLR_2_L___M 0xFFFFFFFF +#define PHYA_PCSS_WDOG_CONTROL_CLR_2_L___S 0 + +#define PHYA_PCSS_DMAC5_TRIGGER_REG0_L (0x00382C00) +#define PHYA_PCSS_DMAC5_TRIGGER_REG0_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_TRIGGER_REG0_L___POR 0x00000000 +#define PHYA_PCSS_DMAC5_TRIGGER_REG0_L__TRIGGER_0___POR 0x0 +#define PHYA_PCSS_DMAC5_TRIGGER_REG0_L__TRIGGER_0___M 0x00000001 +#define PHYA_PCSS_DMAC5_TRIGGER_REG0_L__TRIGGER_0___S 0 +#define PHYA_PCSS_DMAC5_TRIGGER_REG0_L___M 0x00000001 +#define PHYA_PCSS_DMAC5_TRIGGER_REG0_L___S 0 + +#define PHYA_PCSS_DMAC5_TRIGGER_REG1_L (0x00382C08) +#define PHYA_PCSS_DMAC5_TRIGGER_REG1_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_TRIGGER_REG1_L___POR 0x00000000 +#define PHYA_PCSS_DMAC5_TRIGGER_REG1_L__TRIGGER_1___POR 0x0 +#define PHYA_PCSS_DMAC5_TRIGGER_REG1_L__TRIGGER_1___M 0x00000001 +#define PHYA_PCSS_DMAC5_TRIGGER_REG1_L__TRIGGER_1___S 0 +#define PHYA_PCSS_DMAC5_TRIGGER_REG1_L___M 0x00000001 +#define PHYA_PCSS_DMAC5_TRIGGER_REG1_L___S 0 + +#define PHYA_PCSS_DMAC5_TRIGGER_REG2_L (0x00382C10) +#define PHYA_PCSS_DMAC5_TRIGGER_REG2_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_TRIGGER_REG2_L___POR 0x00000000 +#define PHYA_PCSS_DMAC5_TRIGGER_REG2_L__TRIGGER_2___POR 0x0 +#define PHYA_PCSS_DMAC5_TRIGGER_REG2_L__TRIGGER_2___M 0x00000001 +#define PHYA_PCSS_DMAC5_TRIGGER_REG2_L__TRIGGER_2___S 0 +#define PHYA_PCSS_DMAC5_TRIGGER_REG2_L___M 0x00000001 +#define PHYA_PCSS_DMAC5_TRIGGER_REG2_L___S 0 + +#define PHYA_PCSS_DMAC5_TRIGGER_REG3_L (0x00382C18) +#define PHYA_PCSS_DMAC5_TRIGGER_REG3_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_TRIGGER_REG3_L___POR 0x00000000 +#define PHYA_PCSS_DMAC5_TRIGGER_REG3_L__TRIGGER_3___POR 0x0 +#define PHYA_PCSS_DMAC5_TRIGGER_REG3_L__TRIGGER_3___M 0x00000001 +#define PHYA_PCSS_DMAC5_TRIGGER_REG3_L__TRIGGER_3___S 0 +#define PHYA_PCSS_DMAC5_TRIGGER_REG3_L___M 0x00000001 +#define PHYA_PCSS_DMAC5_TRIGGER_REG3_L___S 0 + +#define PHYA_PCSS_DMAC5_TRIGGER_REG4_L (0x00382C20) +#define PHYA_PCSS_DMAC5_TRIGGER_REG4_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_TRIGGER_REG4_L___POR 0x00000000 +#define PHYA_PCSS_DMAC5_TRIGGER_REG4_L__TRIGGER_4___POR 0x0 +#define PHYA_PCSS_DMAC5_TRIGGER_REG4_L__TRIGGER_4___M 0x00000001 +#define PHYA_PCSS_DMAC5_TRIGGER_REG4_L__TRIGGER_4___S 0 +#define PHYA_PCSS_DMAC5_TRIGGER_REG4_L___M 0x00000001 +#define PHYA_PCSS_DMAC5_TRIGGER_REG4_L___S 0 + +#define PHYA_PCSS_DMAC5_TRIGGER_REG5_L (0x00382C28) +#define PHYA_PCSS_DMAC5_TRIGGER_REG5_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_TRIGGER_REG5_L___POR 0x00000000 +#define PHYA_PCSS_DMAC5_TRIGGER_REG5_L__TRIGGER_5___POR 0x0 +#define PHYA_PCSS_DMAC5_TRIGGER_REG5_L__TRIGGER_5___M 0x00000001 +#define PHYA_PCSS_DMAC5_TRIGGER_REG5_L__TRIGGER_5___S 0 +#define PHYA_PCSS_DMAC5_TRIGGER_REG5_L___M 0x00000001 +#define PHYA_PCSS_DMAC5_TRIGGER_REG5_L___S 0 + +#define PHYA_PCSS_DMAC5_TRIGGER_REG6_L (0x00382C30) +#define PHYA_PCSS_DMAC5_TRIGGER_REG6_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_TRIGGER_REG6_L___POR 0x00000000 +#define PHYA_PCSS_DMAC5_TRIGGER_REG6_L__TRIGGER_6___POR 0x0 +#define PHYA_PCSS_DMAC5_TRIGGER_REG6_L__TRIGGER_6___M 0x00000001 +#define PHYA_PCSS_DMAC5_TRIGGER_REG6_L__TRIGGER_6___S 0 +#define PHYA_PCSS_DMAC5_TRIGGER_REG6_L___M 0x00000001 +#define PHYA_PCSS_DMAC5_TRIGGER_REG6_L___S 0 + +#define PHYA_PCSS_DMAC5_TRIGGER_REG7_L (0x00382C38) +#define PHYA_PCSS_DMAC5_TRIGGER_REG7_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_TRIGGER_REG7_L___POR 0x00000000 +#define PHYA_PCSS_DMAC5_TRIGGER_REG7_L__TRIGGER_7___POR 0x0 +#define PHYA_PCSS_DMAC5_TRIGGER_REG7_L__TRIGGER_7___M 0x00000001 +#define PHYA_PCSS_DMAC5_TRIGGER_REG7_L__TRIGGER_7___S 0 +#define PHYA_PCSS_DMAC5_TRIGGER_REG7_L___M 0x00000001 +#define PHYA_PCSS_DMAC5_TRIGGER_REG7_L___S 0 + +#define PHYA_PCSS_DMAC5_TRIGGER_REG8_L (0x00382C40) +#define PHYA_PCSS_DMAC5_TRIGGER_REG8_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_TRIGGER_REG8_L___POR 0x00000000 +#define PHYA_PCSS_DMAC5_TRIGGER_REG8_L__TRIGGER_8___POR 0x0 +#define PHYA_PCSS_DMAC5_TRIGGER_REG8_L__TRIGGER_8___M 0x00000001 +#define PHYA_PCSS_DMAC5_TRIGGER_REG8_L__TRIGGER_8___S 0 +#define PHYA_PCSS_DMAC5_TRIGGER_REG8_L___M 0x00000001 +#define PHYA_PCSS_DMAC5_TRIGGER_REG8_L___S 0 + +#define PHYA_PCSS_DMAC5_TRIGGER_REG9_L (0x00382C48) +#define PHYA_PCSS_DMAC5_TRIGGER_REG9_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_TRIGGER_REG9_L___POR 0x00000000 +#define PHYA_PCSS_DMAC5_TRIGGER_REG9_L__TRIGGER_9___POR 0x0 +#define PHYA_PCSS_DMAC5_TRIGGER_REG9_L__TRIGGER_9___M 0x00000001 +#define PHYA_PCSS_DMAC5_TRIGGER_REG9_L__TRIGGER_9___S 0 +#define PHYA_PCSS_DMAC5_TRIGGER_REG9_L___M 0x00000001 +#define PHYA_PCSS_DMAC5_TRIGGER_REG9_L___S 0 + +#define PHYA_PCSS_DMAC5_TRIGGER_REG10_L (0x00382C50) +#define PHYA_PCSS_DMAC5_TRIGGER_REG10_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_TRIGGER_REG10_L___POR 0x00000000 +#define PHYA_PCSS_DMAC5_TRIGGER_REG10_L__TRIGGER_10___POR 0x0 +#define PHYA_PCSS_DMAC5_TRIGGER_REG10_L__TRIGGER_10___M 0x00000001 +#define PHYA_PCSS_DMAC5_TRIGGER_REG10_L__TRIGGER_10___S 0 +#define PHYA_PCSS_DMAC5_TRIGGER_REG10_L___M 0x00000001 +#define PHYA_PCSS_DMAC5_TRIGGER_REG10_L___S 0 + +#define PHYA_PCSS_DMAC5_TRIGGER_REG11_L (0x00382C58) +#define PHYA_PCSS_DMAC5_TRIGGER_REG11_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_TRIGGER_REG11_L___POR 0x00000000 +#define PHYA_PCSS_DMAC5_TRIGGER_REG11_L__TRIGGER_11___POR 0x0 +#define PHYA_PCSS_DMAC5_TRIGGER_REG11_L__TRIGGER_11___M 0x00000001 +#define PHYA_PCSS_DMAC5_TRIGGER_REG11_L__TRIGGER_11___S 0 +#define PHYA_PCSS_DMAC5_TRIGGER_REG11_L___M 0x00000001 +#define PHYA_PCSS_DMAC5_TRIGGER_REG11_L___S 0 + +#define PHYA_PCSS_DMAC5_TRIGGER_REG12_L (0x00382C60) +#define PHYA_PCSS_DMAC5_TRIGGER_REG12_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_TRIGGER_REG12_L___POR 0x00000000 +#define PHYA_PCSS_DMAC5_TRIGGER_REG12_L__TRIGGER_12___POR 0x0 +#define PHYA_PCSS_DMAC5_TRIGGER_REG12_L__TRIGGER_12___M 0x00000001 +#define PHYA_PCSS_DMAC5_TRIGGER_REG12_L__TRIGGER_12___S 0 +#define PHYA_PCSS_DMAC5_TRIGGER_REG12_L___M 0x00000001 +#define PHYA_PCSS_DMAC5_TRIGGER_REG12_L___S 0 + +#define PHYA_PCSS_DMAC5_TRIGGER_REG13_L (0x00382C68) +#define PHYA_PCSS_DMAC5_TRIGGER_REG13_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_TRIGGER_REG13_L___POR 0x00000000 +#define PHYA_PCSS_DMAC5_TRIGGER_REG13_L__TRIGGER_13___POR 0x0 +#define PHYA_PCSS_DMAC5_TRIGGER_REG13_L__TRIGGER_13___M 0x00000001 +#define PHYA_PCSS_DMAC5_TRIGGER_REG13_L__TRIGGER_13___S 0 +#define PHYA_PCSS_DMAC5_TRIGGER_REG13_L___M 0x00000001 +#define PHYA_PCSS_DMAC5_TRIGGER_REG13_L___S 0 + +#define PHYA_PCSS_DMAC5_TRIGGER_REG14_L (0x00382C70) +#define PHYA_PCSS_DMAC5_TRIGGER_REG14_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_TRIGGER_REG14_L___POR 0x00000000 +#define PHYA_PCSS_DMAC5_TRIGGER_REG14_L__TRIGGER_14___POR 0x0 +#define PHYA_PCSS_DMAC5_TRIGGER_REG14_L__TRIGGER_14___M 0x00000001 +#define PHYA_PCSS_DMAC5_TRIGGER_REG14_L__TRIGGER_14___S 0 +#define PHYA_PCSS_DMAC5_TRIGGER_REG14_L___M 0x00000001 +#define PHYA_PCSS_DMAC5_TRIGGER_REG14_L___S 0 + +#define PHYA_PCSS_DMAC5_TRIGGER_REG15_L (0x00382C78) +#define PHYA_PCSS_DMAC5_TRIGGER_REG15_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_TRIGGER_REG15_L___POR 0x00000000 +#define PHYA_PCSS_DMAC5_TRIGGER_REG15_L__TRIGGER_15___POR 0x0 +#define PHYA_PCSS_DMAC5_TRIGGER_REG15_L__TRIGGER_15___M 0x00000001 +#define PHYA_PCSS_DMAC5_TRIGGER_REG15_L__TRIGGER_15___S 0 +#define PHYA_PCSS_DMAC5_TRIGGER_REG15_L___M 0x00000001 +#define PHYA_PCSS_DMAC5_TRIGGER_REG15_L___S 0 + +#define PHYA_PCSS_DMAC5_DMA_CTRL_L (0x00382C80) +#define PHYA_PCSS_DMAC5_DMA_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DMA_CTRL_L___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DMA_CTRL_L__DMAC_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DMA_CTRL_L__DMAC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC5_DMA_CTRL_L__DMAC_EN___S 0 +#define PHYA_PCSS_DMAC5_DMA_CTRL_L___M 0x00000001 +#define PHYA_PCSS_DMAC5_DMA_CTRL_L___S 0 + +#define PHYA_PCSS_DMAC5_DMA_CTRL_U (0x00382C84) +#define PHYA_PCSS_DMAC5_DMA_CTRL_U___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DMA_CTRL_U___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DMA_CTRL_U__EVTI_XFER_STOP___POR 0x00 +#define PHYA_PCSS_DMAC5_DMA_CTRL_U__EVTI_XFER_STOP___M 0x0000003F +#define PHYA_PCSS_DMAC5_DMA_CTRL_U__EVTI_XFER_STOP___S 0 +#define PHYA_PCSS_DMAC5_DMA_CTRL_U___M 0x0000003F +#define PHYA_PCSS_DMAC5_DMA_CTRL_U___S 0 + +#define PHYA_PCSS_DMAC5_DMA_STATUS_0_L (0x00382C88) +#define PHYA_PCSS_DMAC5_DMA_STATUS_0_L___RWC QCSR_REG_RO +#define PHYA_PCSS_DMAC5_DMA_STATUS_0_L___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DMA_STATUS_0_L__CTRL_FSM_STATE___POR 0x0 +#define PHYA_PCSS_DMAC5_DMA_STATUS_0_L__DESC_LAST___POR 0x0 +#define PHYA_PCSS_DMAC5_DMA_STATUS_0_L__DESC_ACTIVE___POR 0x0 +#define PHYA_PCSS_DMAC5_DMA_STATUS_0_L__DMAC_ACTIVE___POR 0x0 +#define PHYA_PCSS_DMAC5_DMA_STATUS_0_L__CTRL_FSM_STATE___M 0x0F000000 +#define PHYA_PCSS_DMAC5_DMA_STATUS_0_L__CTRL_FSM_STATE___S 24 +#define PHYA_PCSS_DMAC5_DMA_STATUS_0_L__DESC_LAST___M 0x000F0000 +#define PHYA_PCSS_DMAC5_DMA_STATUS_0_L__DESC_LAST___S 16 +#define PHYA_PCSS_DMAC5_DMA_STATUS_0_L__DESC_ACTIVE___M 0x00000F00 +#define PHYA_PCSS_DMAC5_DMA_STATUS_0_L__DESC_ACTIVE___S 8 +#define PHYA_PCSS_DMAC5_DMA_STATUS_0_L__DMAC_ACTIVE___M 0x00000001 +#define PHYA_PCSS_DMAC5_DMA_STATUS_0_L__DMAC_ACTIVE___S 0 +#define PHYA_PCSS_DMAC5_DMA_STATUS_0_L___M 0x0F0F0F01 +#define PHYA_PCSS_DMAC5_DMA_STATUS_0_L___S 0 + +#define PHYA_PCSS_DMAC5_DMA_STATUS_0_U (0x00382C8C) +#define PHYA_PCSS_DMAC5_DMA_STATUS_0_U___RWC QCSR_REG_RO +#define PHYA_PCSS_DMAC5_DMA_STATUS_0_U___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DMA_STATUS_0_U__XFER_FIFO_OCC___POR 0x000 +#define PHYA_PCSS_DMAC5_DMA_STATUS_0_U__ALEN_FIFO_OCC___POR 0x0 +#define PHYA_PCSS_DMAC5_DMA_STATUS_0_U__DP_FSM_STATE___POR 0x0 +#define PHYA_PCSS_DMAC5_DMA_STATUS_0_U__XFER_FIFO_OCC___M 0x01FF0000 +#define PHYA_PCSS_DMAC5_DMA_STATUS_0_U__XFER_FIFO_OCC___S 16 +#define PHYA_PCSS_DMAC5_DMA_STATUS_0_U__ALEN_FIFO_OCC___M 0x00000F00 +#define PHYA_PCSS_DMAC5_DMA_STATUS_0_U__ALEN_FIFO_OCC___S 8 +#define PHYA_PCSS_DMAC5_DMA_STATUS_0_U__DP_FSM_STATE___M 0x0000000F +#define PHYA_PCSS_DMAC5_DMA_STATUS_0_U__DP_FSM_STATE___S 0 +#define PHYA_PCSS_DMAC5_DMA_STATUS_0_U___M 0x01FF0F0F +#define PHYA_PCSS_DMAC5_DMA_STATUS_0_U___S 0 + +#define PHYA_PCSS_DMAC5_DMA_STATUS_1_L (0x00382C90) +#define PHYA_PCSS_DMAC5_DMA_STATUS_1_L___RWC QCSR_REG_RO +#define PHYA_PCSS_DMAC5_DMA_STATUS_1_L___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DMA_STATUS_1_L__XFER_LEN_PEND___POR 0x000000 +#define PHYA_PCSS_DMAC5_DMA_STATUS_1_L__XFER_LEN_PEND___M 0x00FFFFFF +#define PHYA_PCSS_DMAC5_DMA_STATUS_1_L__XFER_LEN_PEND___S 0 +#define PHYA_PCSS_DMAC5_DMA_STATUS_1_L___M 0x00FFFFFF +#define PHYA_PCSS_DMAC5_DMA_STATUS_1_L___S 0 + +#define PHYA_PCSS_DMAC5_DMA_EVT_LATCH_L (0x00382C98) +#define PHYA_PCSS_DMAC5_DMA_EVT_LATCH_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DMA_EVT_LATCH_L___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___S 0 +#define PHYA_PCSS_DMAC5_DMA_EVT_LATCH_L___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DMA_EVT_LATCH_L___S 0 + +#define PHYA_PCSS_DMAC5_DMA_EVT_LATCH_U (0x00382C9C) +#define PHYA_PCSS_DMAC5_DMA_EVT_LATCH_U___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DMA_EVT_LATCH_U___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___S 0 +#define PHYA_PCSS_DMAC5_DMA_EVT_LATCH_U___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DMA_EVT_LATCH_U___S 0 + +#define PHYA_PCSS_DMAC5_DMA_EVT_TRIG_L (0x00382CA0) +#define PHYA_PCSS_DMAC5_DMA_EVT_TRIG_L___RWC QCSR_REG_RO +#define PHYA_PCSS_DMAC5_DMA_EVT_TRIG_L___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DMA_EVT_TRIG_L__CUR_EVT_TRIG___POR 0x00 +#define PHYA_PCSS_DMAC5_DMA_EVT_TRIG_L__LAST_EVT_TRIG___POR 0x00 +#define PHYA_PCSS_DMAC5_DMA_EVT_TRIG_L__CUR_EVT_TRIG___M 0x0000FF00 +#define PHYA_PCSS_DMAC5_DMA_EVT_TRIG_L__CUR_EVT_TRIG___S 8 +#define PHYA_PCSS_DMAC5_DMA_EVT_TRIG_L__LAST_EVT_TRIG___M 0x000000FF +#define PHYA_PCSS_DMAC5_DMA_EVT_TRIG_L__LAST_EVT_TRIG___S 0 +#define PHYA_PCSS_DMAC5_DMA_EVT_TRIG_L___M 0x0000FFFF +#define PHYA_PCSS_DMAC5_DMA_EVT_TRIG_L___S 0 + +#define PHYA_PCSS_DMAC5_DMA_XFER_CTRL_L (0x00382CA8) +#define PHYA_PCSS_DMAC5_DMA_XFER_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DMA_XFER_CTRL_L___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___POR 0x0 +#define PHYA_PCSS_DMAC5_DMA_XFER_CTRL_L__PAUSE_XFER___POR 0x0 +#define PHYA_PCSS_DMAC5_DMA_XFER_CTRL_L__STOP_XFER_MASK___POR 0x0000 +#define PHYA_PCSS_DMAC5_DMA_XFER_CTRL_L__STOP_XFER___POR 0x0 +#define PHYA_PCSS_DMAC5_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___M 0x00040000 +#define PHYA_PCSS_DMAC5_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___S 18 +#define PHYA_PCSS_DMAC5_DMA_XFER_CTRL_L__PAUSE_XFER___M 0x00020000 +#define PHYA_PCSS_DMAC5_DMA_XFER_CTRL_L__PAUSE_XFER___S 17 +#define PHYA_PCSS_DMAC5_DMA_XFER_CTRL_L__STOP_XFER_MASK___M 0x0001FFFE +#define PHYA_PCSS_DMAC5_DMA_XFER_CTRL_L__STOP_XFER_MASK___S 1 +#define PHYA_PCSS_DMAC5_DMA_XFER_CTRL_L__STOP_XFER___M 0x00000001 +#define PHYA_PCSS_DMAC5_DMA_XFER_CTRL_L__STOP_XFER___S 0 +#define PHYA_PCSS_DMAC5_DMA_XFER_CTRL_L___M 0x0007FFFF +#define PHYA_PCSS_DMAC5_DMA_XFER_CTRL_L___S 0 + +#define PHYA_PCSS_DMAC5_DMA_SPARE_L (0x00382CB0) +#define PHYA_PCSS_DMAC5_DMA_SPARE_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DMA_SPARE_L___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DMA_SPARE_L__DMA_SPARE_0___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DMA_SPARE_L__DMA_SPARE_0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DMA_SPARE_L__DMA_SPARE_0___S 0 +#define PHYA_PCSS_DMAC5_DMA_SPARE_L___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DMA_SPARE_L___S 0 + +#define PHYA_PCSS_DMAC5_DMA_SPARE_U (0x00382CB4) +#define PHYA_PCSS_DMAC5_DMA_SPARE_U___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DMA_SPARE_U___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DMA_SPARE_U__DMA_SPARE_1___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DMA_SPARE_U__DMA_SPARE_1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DMA_SPARE_U__DMA_SPARE_1___S 0 +#define PHYA_PCSS_DMAC5_DMA_SPARE_U___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DMA_SPARE_U___S 0 + +#define PHYA_PCSS_DMAC5_DMA_ECO_L (0x00382CB8) +#define PHYA_PCSS_DMAC5_DMA_ECO_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DMA_ECO_L___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DMA_ECO_L__DMA_ECO_0___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DMA_ECO_L__DMA_ECO_0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DMA_ECO_L__DMA_ECO_0___S 0 +#define PHYA_PCSS_DMAC5_DMA_ECO_L___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DMA_ECO_L___S 0 + +#define PHYA_PCSS_DMAC5_DMA_ECO_U (0x00382CBC) +#define PHYA_PCSS_DMAC5_DMA_ECO_U___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DMA_ECO_U___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DMA_ECO_U__DMA_ECO_1___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DMA_ECO_U__DMA_ECO_1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DMA_ECO_U__DMA_ECO_1___S 0 +#define PHYA_PCSS_DMAC5_DMA_ECO_U___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DMA_ECO_U___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B0 (0x00382CC0) +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B0__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B0__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B0__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B0___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B1 (0x00382CD8) +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B1__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B1__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B1__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B1___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B2 (0x00382CF0) +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B2__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B2__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B2__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B2___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B3 (0x00382D08) +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B3__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B3__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B3__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B3___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B4 (0x00382D20) +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B4__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B4__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B4__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B4___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B5 (0x00382D38) +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B5__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B5__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B5__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B5___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B6 (0x00382D50) +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B6__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B6__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B6__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B6___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B7 (0x00382D68) +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B7__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B7__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B7__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B7___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B8 (0x00382D80) +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B8___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B8___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B8__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B8__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B8__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B8__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B8__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B8__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B8__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B8__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B8__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B8___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B8___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B9 (0x00382D98) +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B9___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B9___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B9__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B9__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B9__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B9__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B9__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B9__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B9__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B9__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B9__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B9___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B9___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B10 (0x00382DB0) +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B10___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B10___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B10__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B10__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B10__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B10__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B10__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B10__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B10__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B10__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B10__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B10___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B10___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B11 (0x00382DC8) +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B11___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B11___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B11__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B11__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B11__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B11__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B11__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B11__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B11__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B11__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B11__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B11___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B11___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B12 (0x00382DE0) +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B12___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B12___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B12__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B12__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B12__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B12__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B12__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B12__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B12__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B12__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B12__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B12___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B12___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B13 (0x00382DF8) +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B13___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B13___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B13__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B13__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B13__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B13__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B13__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B13__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B13__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B13__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B13__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B13___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B13___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B14 (0x00382E10) +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B14___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B14___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B14__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B14__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B14__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B14__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B14__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B14__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B14__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B14__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B14__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B14___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B14___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B15 (0x00382E28) +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B15___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B15___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B15__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B15__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B15__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B15__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B15__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B15__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B15__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B15__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B15__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B15___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_0_L_B15___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B0 (0x00382CC4) +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B0__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B0__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B0__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B0__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B0__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B0__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B0___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B1 (0x00382CDC) +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B1__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B1__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B1__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B1__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B1__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B1__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B1___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B2 (0x00382CF4) +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B2__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B2__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B2__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B2__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B2__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B2__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B2___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B3 (0x00382D0C) +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B3__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B3__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B3__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B3__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B3__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B3__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B3___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B4 (0x00382D24) +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B4__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B4__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B4__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B4__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B4__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B4__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B4___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B5 (0x00382D3C) +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B5__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B5__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B5__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B5__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B5__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B5__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B5___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B6 (0x00382D54) +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B6__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B6__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B6__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B6__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B6__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B6__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B6___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B7 (0x00382D6C) +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B7__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B7__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B7__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B7__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B7__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B7__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B7___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B8 (0x00382D84) +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B8___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B8___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B8__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B8__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B8__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B8__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B8__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B8__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B8__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B8__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B8__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B8___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B8___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B9 (0x00382D9C) +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B9___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B9___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B9__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B9__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B9__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B9__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B9__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B9__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B9__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B9__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B9__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B9___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B9___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B10 (0x00382DB4) +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B10___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B10___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B10__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B10__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B10__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B10__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B10__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B10__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B10__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B10__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B10__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B10___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B10___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B11 (0x00382DCC) +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B11___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B11___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B11__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B11__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B11__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B11__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B11__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B11__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B11__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B11__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B11__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B11___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B11___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B12 (0x00382DE4) +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B12___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B12___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B12__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B12__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B12__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B12__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B12__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B12__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B12__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B12__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B12__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B12___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B12___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B13 (0x00382DFC) +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B13___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B13___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B13__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B13__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B13__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B13__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B13__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B13__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B13__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B13__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B13__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B13___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B13___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B14 (0x00382E14) +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B14___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B14___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B14__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B14__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B14__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B14__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B14__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B14__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B14__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B14__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B14__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B14___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B14___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B15 (0x00382E2C) +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B15___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B15___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B15__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B15__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B15__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B15__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B15__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B15__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B15__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B15__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B15__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B15___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_0_U_B15___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B0 (0x00382CC8) +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B0__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B0__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B0__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B0___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B1 (0x00382CE0) +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B1__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B1__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B1__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B1___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B2 (0x00382CF8) +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B2__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B2__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B2__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B2___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B3 (0x00382D10) +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B3__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B3__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B3__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B3___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B4 (0x00382D28) +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B4__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B4__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B4__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B4___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B5 (0x00382D40) +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B5__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B5__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B5__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B5___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B6 (0x00382D58) +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B6__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B6__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B6__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B6___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B7 (0x00382D70) +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B7__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B7__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B7__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B7___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B8 (0x00382D88) +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B8___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B8___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B8__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B8__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B8__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B8___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B8___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B9 (0x00382DA0) +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B9___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B9___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B9__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B9__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B9__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B9___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B9___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B10 (0x00382DB8) +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B10___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B10___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B10__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B10__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B10__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B10___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B10___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B11 (0x00382DD0) +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B11___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B11___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B11__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B11__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B11__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B11___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B11___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B12 (0x00382DE8) +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B12___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B12___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B12__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B12__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B12__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B12___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B12___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B13 (0x00382E00) +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B13___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B13___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B13__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B13__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B13__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B13___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B13___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B14 (0x00382E18) +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B14___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B14___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B14__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B14__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B14__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B14___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B14___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B15 (0x00382E30) +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B15___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B15___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B15__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B15__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B15__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B15___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_L_B15___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B0 (0x00382CCC) +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B0__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B0__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B0__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B0___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B1 (0x00382CE4) +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B1__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B1__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B1__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B1___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B2 (0x00382CFC) +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B2__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B2__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B2__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B2___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B3 (0x00382D14) +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B3__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B3__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B3__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B3___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B4 (0x00382D2C) +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B4__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B4__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B4__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B4___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B5 (0x00382D44) +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B5__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B5__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B5__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B5___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B6 (0x00382D5C) +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B6__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B6__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B6__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B6___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B7 (0x00382D74) +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B7__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B7__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B7__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B7___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B8 (0x00382D8C) +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B8___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B8___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B8__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B8__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B8__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B8___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B8___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B9 (0x00382DA4) +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B9___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B9___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B9__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B9__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B9__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B9___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B9___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B10 (0x00382DBC) +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B10___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B10___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B10__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B10__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B10__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B10___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B10___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B11 (0x00382DD4) +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B11___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B11___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B11__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B11__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B11__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B11___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B11___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B12 (0x00382DEC) +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B12___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B12___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B12__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B12__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B12__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B12___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B12___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B13 (0x00382E04) +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B13___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B13___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B13__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B13__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B13__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B13___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B13___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B14 (0x00382E1C) +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B14___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B14___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B14__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B14__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B14__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B14___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B14___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B15 (0x00382E34) +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B15___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B15___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B15__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B15__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B15__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B15___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_1_U_B15___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B0 (0x00382CD0) +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B0__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B0__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B0__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B0___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B1 (0x00382CE8) +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B1__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B1__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B1__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B1___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B2 (0x00382D00) +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B2__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B2__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B2__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B2___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B3 (0x00382D18) +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B3__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B3__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B3__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B3___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B4 (0x00382D30) +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B4__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B4__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B4__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B4___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B5 (0x00382D48) +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B5__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B5__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B5__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B5___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B6 (0x00382D60) +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B6__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B6__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B6__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B6___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B7 (0x00382D78) +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B7__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B7__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B7__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B7___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B8 (0x00382D90) +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B8___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B8___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B8__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B8__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B8__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B8___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B8___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B9 (0x00382DA8) +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B9___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B9___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B9__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B9__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B9__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B9___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B9___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B10 (0x00382DC0) +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B10___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B10___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B10__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B10__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B10__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B10___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B10___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B11 (0x00382DD8) +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B11___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B11___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B11__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B11__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B11__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B11___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B11___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B12 (0x00382DF0) +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B12___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B12___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B12__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B12__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B12__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B12___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B12___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B13 (0x00382E08) +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B13___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B13___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B13__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B13__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B13__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B13___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B13___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B14 (0x00382E20) +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B14___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B14___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B14__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B14__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B14__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B14___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B14___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B15 (0x00382E38) +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B15___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B15___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B15__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B15__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B15__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B15___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_L_B15___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0 (0x00382CD4) +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__FRZDST___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__FRZSRC___S 5 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__DATSRC___S 2 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0__DESC_EN___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B0___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1 (0x00382CEC) +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__FRZDST___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__FRZSRC___S 5 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__DATSRC___S 2 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1__DESC_EN___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B1___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2 (0x00382D04) +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__FRZDST___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__FRZSRC___S 5 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__DATSRC___S 2 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2__DESC_EN___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B2___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3 (0x00382D1C) +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__FRZDST___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__FRZSRC___S 5 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__DATSRC___S 2 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3__DESC_EN___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B3___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4 (0x00382D34) +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__FRZDST___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__FRZSRC___S 5 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__DATSRC___S 2 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4__DESC_EN___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B4___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5 (0x00382D4C) +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__FRZDST___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__FRZSRC___S 5 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__DATSRC___S 2 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5__DESC_EN___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B5___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6 (0x00382D64) +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__FRZDST___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__FRZSRC___S 5 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__DATSRC___S 2 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6__DESC_EN___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B6___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7 (0x00382D7C) +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__FRZDST___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__FRZSRC___S 5 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__DATSRC___S 2 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7__DESC_EN___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B7___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8 (0x00382D94) +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__FRZDST___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__FRZSRC___S 5 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__DATSRC___S 2 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8__DESC_EN___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B8___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9 (0x00382DAC) +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__FRZDST___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__FRZSRC___S 5 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__DATSRC___S 2 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9__DESC_EN___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B9___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10 (0x00382DC4) +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__FRZDST___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__FRZSRC___S 5 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__DATSRC___S 2 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10__DESC_EN___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B10___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11 (0x00382DDC) +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__FRZDST___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__FRZSRC___S 5 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__DATSRC___S 2 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11__DESC_EN___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B11___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12 (0x00382DF4) +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__FRZDST___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__FRZSRC___S 5 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__DATSRC___S 2 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12__DESC_EN___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B12___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13 (0x00382E0C) +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__FRZDST___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__FRZSRC___S 5 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__DATSRC___S 2 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13__DESC_EN___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B13___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14 (0x00382E24) +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__FRZDST___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__FRZSRC___S 5 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__DATSRC___S 2 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14__DESC_EN___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B14___S 0 + +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15 (0x00382E3C) +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__FRZDST___S 6 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__FRZSRC___S 5 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__DATSRC___S 2 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15__DESC_EN___S 0 +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC5_DESC_REG_2_U_B15___S 0 + +#define PHYA_PCSS_DMAC5_DMAC2PHYDBG_EN_REG_L (0x00382E40) +#define PHYA_PCSS_DMAC5_DMAC2PHYDBG_EN_REG_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DMAC2PHYDBG_EN_REG_L___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___POR 0x0000 +#define PHYA_PCSS_DMAC5_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___M 0x0000FFFF +#define PHYA_PCSS_DMAC5_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___S 0 +#define PHYA_PCSS_DMAC5_DMAC2PHYDBG_EN_REG_L___M 0x0000FFFF +#define PHYA_PCSS_DMAC5_DMAC2PHYDBG_EN_REG_L___S 0 + +#define PHYA_PCSS_DMAC5_DUMMY_L (0x00382E48) +#define PHYA_PCSS_DMAC5_DUMMY_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC5_DUMMY_L___POR 0x00000000 +#define PHYA_PCSS_DMAC5_DUMMY_L__DUMMY___POR 0x0 +#define PHYA_PCSS_DMAC5_DUMMY_L__DUMMY___M 0x00000001 +#define PHYA_PCSS_DMAC5_DUMMY_L__DUMMY___S 0 +#define PHYA_PCSS_DMAC5_DUMMY_L___M 0x00000001 +#define PHYA_PCSS_DMAC5_DUMMY_L___S 0 + +#define PHYA_PCSS_DMAC6_TRIGGER_REG0_L (0x00383000) +#define PHYA_PCSS_DMAC6_TRIGGER_REG0_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_TRIGGER_REG0_L___POR 0x00000000 +#define PHYA_PCSS_DMAC6_TRIGGER_REG0_L__TRIGGER_0___POR 0x0 +#define PHYA_PCSS_DMAC6_TRIGGER_REG0_L__TRIGGER_0___M 0x00000001 +#define PHYA_PCSS_DMAC6_TRIGGER_REG0_L__TRIGGER_0___S 0 +#define PHYA_PCSS_DMAC6_TRIGGER_REG0_L___M 0x00000001 +#define PHYA_PCSS_DMAC6_TRIGGER_REG0_L___S 0 + +#define PHYA_PCSS_DMAC6_TRIGGER_REG1_L (0x00383008) +#define PHYA_PCSS_DMAC6_TRIGGER_REG1_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_TRIGGER_REG1_L___POR 0x00000000 +#define PHYA_PCSS_DMAC6_TRIGGER_REG1_L__TRIGGER_1___POR 0x0 +#define PHYA_PCSS_DMAC6_TRIGGER_REG1_L__TRIGGER_1___M 0x00000001 +#define PHYA_PCSS_DMAC6_TRIGGER_REG1_L__TRIGGER_1___S 0 +#define PHYA_PCSS_DMAC6_TRIGGER_REG1_L___M 0x00000001 +#define PHYA_PCSS_DMAC6_TRIGGER_REG1_L___S 0 + +#define PHYA_PCSS_DMAC6_TRIGGER_REG2_L (0x00383010) +#define PHYA_PCSS_DMAC6_TRIGGER_REG2_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_TRIGGER_REG2_L___POR 0x00000000 +#define PHYA_PCSS_DMAC6_TRIGGER_REG2_L__TRIGGER_2___POR 0x0 +#define PHYA_PCSS_DMAC6_TRIGGER_REG2_L__TRIGGER_2___M 0x00000001 +#define PHYA_PCSS_DMAC6_TRIGGER_REG2_L__TRIGGER_2___S 0 +#define PHYA_PCSS_DMAC6_TRIGGER_REG2_L___M 0x00000001 +#define PHYA_PCSS_DMAC6_TRIGGER_REG2_L___S 0 + +#define PHYA_PCSS_DMAC6_TRIGGER_REG3_L (0x00383018) +#define PHYA_PCSS_DMAC6_TRIGGER_REG3_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_TRIGGER_REG3_L___POR 0x00000000 +#define PHYA_PCSS_DMAC6_TRIGGER_REG3_L__TRIGGER_3___POR 0x0 +#define PHYA_PCSS_DMAC6_TRIGGER_REG3_L__TRIGGER_3___M 0x00000001 +#define PHYA_PCSS_DMAC6_TRIGGER_REG3_L__TRIGGER_3___S 0 +#define PHYA_PCSS_DMAC6_TRIGGER_REG3_L___M 0x00000001 +#define PHYA_PCSS_DMAC6_TRIGGER_REG3_L___S 0 + +#define PHYA_PCSS_DMAC6_TRIGGER_REG4_L (0x00383020) +#define PHYA_PCSS_DMAC6_TRIGGER_REG4_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_TRIGGER_REG4_L___POR 0x00000000 +#define PHYA_PCSS_DMAC6_TRIGGER_REG4_L__TRIGGER_4___POR 0x0 +#define PHYA_PCSS_DMAC6_TRIGGER_REG4_L__TRIGGER_4___M 0x00000001 +#define PHYA_PCSS_DMAC6_TRIGGER_REG4_L__TRIGGER_4___S 0 +#define PHYA_PCSS_DMAC6_TRIGGER_REG4_L___M 0x00000001 +#define PHYA_PCSS_DMAC6_TRIGGER_REG4_L___S 0 + +#define PHYA_PCSS_DMAC6_TRIGGER_REG5_L (0x00383028) +#define PHYA_PCSS_DMAC6_TRIGGER_REG5_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_TRIGGER_REG5_L___POR 0x00000000 +#define PHYA_PCSS_DMAC6_TRIGGER_REG5_L__TRIGGER_5___POR 0x0 +#define PHYA_PCSS_DMAC6_TRIGGER_REG5_L__TRIGGER_5___M 0x00000001 +#define PHYA_PCSS_DMAC6_TRIGGER_REG5_L__TRIGGER_5___S 0 +#define PHYA_PCSS_DMAC6_TRIGGER_REG5_L___M 0x00000001 +#define PHYA_PCSS_DMAC6_TRIGGER_REG5_L___S 0 + +#define PHYA_PCSS_DMAC6_TRIGGER_REG6_L (0x00383030) +#define PHYA_PCSS_DMAC6_TRIGGER_REG6_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_TRIGGER_REG6_L___POR 0x00000000 +#define PHYA_PCSS_DMAC6_TRIGGER_REG6_L__TRIGGER_6___POR 0x0 +#define PHYA_PCSS_DMAC6_TRIGGER_REG6_L__TRIGGER_6___M 0x00000001 +#define PHYA_PCSS_DMAC6_TRIGGER_REG6_L__TRIGGER_6___S 0 +#define PHYA_PCSS_DMAC6_TRIGGER_REG6_L___M 0x00000001 +#define PHYA_PCSS_DMAC6_TRIGGER_REG6_L___S 0 + +#define PHYA_PCSS_DMAC6_TRIGGER_REG7_L (0x00383038) +#define PHYA_PCSS_DMAC6_TRIGGER_REG7_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_TRIGGER_REG7_L___POR 0x00000000 +#define PHYA_PCSS_DMAC6_TRIGGER_REG7_L__TRIGGER_7___POR 0x0 +#define PHYA_PCSS_DMAC6_TRIGGER_REG7_L__TRIGGER_7___M 0x00000001 +#define PHYA_PCSS_DMAC6_TRIGGER_REG7_L__TRIGGER_7___S 0 +#define PHYA_PCSS_DMAC6_TRIGGER_REG7_L___M 0x00000001 +#define PHYA_PCSS_DMAC6_TRIGGER_REG7_L___S 0 + +#define PHYA_PCSS_DMAC6_TRIGGER_REG8_L (0x00383040) +#define PHYA_PCSS_DMAC6_TRIGGER_REG8_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_TRIGGER_REG8_L___POR 0x00000000 +#define PHYA_PCSS_DMAC6_TRIGGER_REG8_L__TRIGGER_8___POR 0x0 +#define PHYA_PCSS_DMAC6_TRIGGER_REG8_L__TRIGGER_8___M 0x00000001 +#define PHYA_PCSS_DMAC6_TRIGGER_REG8_L__TRIGGER_8___S 0 +#define PHYA_PCSS_DMAC6_TRIGGER_REG8_L___M 0x00000001 +#define PHYA_PCSS_DMAC6_TRIGGER_REG8_L___S 0 + +#define PHYA_PCSS_DMAC6_TRIGGER_REG9_L (0x00383048) +#define PHYA_PCSS_DMAC6_TRIGGER_REG9_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_TRIGGER_REG9_L___POR 0x00000000 +#define PHYA_PCSS_DMAC6_TRIGGER_REG9_L__TRIGGER_9___POR 0x0 +#define PHYA_PCSS_DMAC6_TRIGGER_REG9_L__TRIGGER_9___M 0x00000001 +#define PHYA_PCSS_DMAC6_TRIGGER_REG9_L__TRIGGER_9___S 0 +#define PHYA_PCSS_DMAC6_TRIGGER_REG9_L___M 0x00000001 +#define PHYA_PCSS_DMAC6_TRIGGER_REG9_L___S 0 + +#define PHYA_PCSS_DMAC6_TRIGGER_REG10_L (0x00383050) +#define PHYA_PCSS_DMAC6_TRIGGER_REG10_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_TRIGGER_REG10_L___POR 0x00000000 +#define PHYA_PCSS_DMAC6_TRIGGER_REG10_L__TRIGGER_10___POR 0x0 +#define PHYA_PCSS_DMAC6_TRIGGER_REG10_L__TRIGGER_10___M 0x00000001 +#define PHYA_PCSS_DMAC6_TRIGGER_REG10_L__TRIGGER_10___S 0 +#define PHYA_PCSS_DMAC6_TRIGGER_REG10_L___M 0x00000001 +#define PHYA_PCSS_DMAC6_TRIGGER_REG10_L___S 0 + +#define PHYA_PCSS_DMAC6_TRIGGER_REG11_L (0x00383058) +#define PHYA_PCSS_DMAC6_TRIGGER_REG11_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_TRIGGER_REG11_L___POR 0x00000000 +#define PHYA_PCSS_DMAC6_TRIGGER_REG11_L__TRIGGER_11___POR 0x0 +#define PHYA_PCSS_DMAC6_TRIGGER_REG11_L__TRIGGER_11___M 0x00000001 +#define PHYA_PCSS_DMAC6_TRIGGER_REG11_L__TRIGGER_11___S 0 +#define PHYA_PCSS_DMAC6_TRIGGER_REG11_L___M 0x00000001 +#define PHYA_PCSS_DMAC6_TRIGGER_REG11_L___S 0 + +#define PHYA_PCSS_DMAC6_TRIGGER_REG12_L (0x00383060) +#define PHYA_PCSS_DMAC6_TRIGGER_REG12_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_TRIGGER_REG12_L___POR 0x00000000 +#define PHYA_PCSS_DMAC6_TRIGGER_REG12_L__TRIGGER_12___POR 0x0 +#define PHYA_PCSS_DMAC6_TRIGGER_REG12_L__TRIGGER_12___M 0x00000001 +#define PHYA_PCSS_DMAC6_TRIGGER_REG12_L__TRIGGER_12___S 0 +#define PHYA_PCSS_DMAC6_TRIGGER_REG12_L___M 0x00000001 +#define PHYA_PCSS_DMAC6_TRIGGER_REG12_L___S 0 + +#define PHYA_PCSS_DMAC6_TRIGGER_REG13_L (0x00383068) +#define PHYA_PCSS_DMAC6_TRIGGER_REG13_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_TRIGGER_REG13_L___POR 0x00000000 +#define PHYA_PCSS_DMAC6_TRIGGER_REG13_L__TRIGGER_13___POR 0x0 +#define PHYA_PCSS_DMAC6_TRIGGER_REG13_L__TRIGGER_13___M 0x00000001 +#define PHYA_PCSS_DMAC6_TRIGGER_REG13_L__TRIGGER_13___S 0 +#define PHYA_PCSS_DMAC6_TRIGGER_REG13_L___M 0x00000001 +#define PHYA_PCSS_DMAC6_TRIGGER_REG13_L___S 0 + +#define PHYA_PCSS_DMAC6_TRIGGER_REG14_L (0x00383070) +#define PHYA_PCSS_DMAC6_TRIGGER_REG14_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_TRIGGER_REG14_L___POR 0x00000000 +#define PHYA_PCSS_DMAC6_TRIGGER_REG14_L__TRIGGER_14___POR 0x0 +#define PHYA_PCSS_DMAC6_TRIGGER_REG14_L__TRIGGER_14___M 0x00000001 +#define PHYA_PCSS_DMAC6_TRIGGER_REG14_L__TRIGGER_14___S 0 +#define PHYA_PCSS_DMAC6_TRIGGER_REG14_L___M 0x00000001 +#define PHYA_PCSS_DMAC6_TRIGGER_REG14_L___S 0 + +#define PHYA_PCSS_DMAC6_TRIGGER_REG15_L (0x00383078) +#define PHYA_PCSS_DMAC6_TRIGGER_REG15_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_TRIGGER_REG15_L___POR 0x00000000 +#define PHYA_PCSS_DMAC6_TRIGGER_REG15_L__TRIGGER_15___POR 0x0 +#define PHYA_PCSS_DMAC6_TRIGGER_REG15_L__TRIGGER_15___M 0x00000001 +#define PHYA_PCSS_DMAC6_TRIGGER_REG15_L__TRIGGER_15___S 0 +#define PHYA_PCSS_DMAC6_TRIGGER_REG15_L___M 0x00000001 +#define PHYA_PCSS_DMAC6_TRIGGER_REG15_L___S 0 + +#define PHYA_PCSS_DMAC6_DMA_CTRL_L (0x00383080) +#define PHYA_PCSS_DMAC6_DMA_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DMA_CTRL_L___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DMA_CTRL_L__DMAC_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DMA_CTRL_L__DMAC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC6_DMA_CTRL_L__DMAC_EN___S 0 +#define PHYA_PCSS_DMAC6_DMA_CTRL_L___M 0x00000001 +#define PHYA_PCSS_DMAC6_DMA_CTRL_L___S 0 + +#define PHYA_PCSS_DMAC6_DMA_CTRL_U (0x00383084) +#define PHYA_PCSS_DMAC6_DMA_CTRL_U___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DMA_CTRL_U___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DMA_CTRL_U__EVTI_XFER_STOP___POR 0x00 +#define PHYA_PCSS_DMAC6_DMA_CTRL_U__EVTI_XFER_STOP___M 0x0000003F +#define PHYA_PCSS_DMAC6_DMA_CTRL_U__EVTI_XFER_STOP___S 0 +#define PHYA_PCSS_DMAC6_DMA_CTRL_U___M 0x0000003F +#define PHYA_PCSS_DMAC6_DMA_CTRL_U___S 0 + +#define PHYA_PCSS_DMAC6_DMA_STATUS_0_L (0x00383088) +#define PHYA_PCSS_DMAC6_DMA_STATUS_0_L___RWC QCSR_REG_RO +#define PHYA_PCSS_DMAC6_DMA_STATUS_0_L___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DMA_STATUS_0_L__CTRL_FSM_STATE___POR 0x0 +#define PHYA_PCSS_DMAC6_DMA_STATUS_0_L__DESC_LAST___POR 0x0 +#define PHYA_PCSS_DMAC6_DMA_STATUS_0_L__DESC_ACTIVE___POR 0x0 +#define PHYA_PCSS_DMAC6_DMA_STATUS_0_L__DMAC_ACTIVE___POR 0x0 +#define PHYA_PCSS_DMAC6_DMA_STATUS_0_L__CTRL_FSM_STATE___M 0x0F000000 +#define PHYA_PCSS_DMAC6_DMA_STATUS_0_L__CTRL_FSM_STATE___S 24 +#define PHYA_PCSS_DMAC6_DMA_STATUS_0_L__DESC_LAST___M 0x000F0000 +#define PHYA_PCSS_DMAC6_DMA_STATUS_0_L__DESC_LAST___S 16 +#define PHYA_PCSS_DMAC6_DMA_STATUS_0_L__DESC_ACTIVE___M 0x00000F00 +#define PHYA_PCSS_DMAC6_DMA_STATUS_0_L__DESC_ACTIVE___S 8 +#define PHYA_PCSS_DMAC6_DMA_STATUS_0_L__DMAC_ACTIVE___M 0x00000001 +#define PHYA_PCSS_DMAC6_DMA_STATUS_0_L__DMAC_ACTIVE___S 0 +#define PHYA_PCSS_DMAC6_DMA_STATUS_0_L___M 0x0F0F0F01 +#define PHYA_PCSS_DMAC6_DMA_STATUS_0_L___S 0 + +#define PHYA_PCSS_DMAC6_DMA_STATUS_0_U (0x0038308C) +#define PHYA_PCSS_DMAC6_DMA_STATUS_0_U___RWC QCSR_REG_RO +#define PHYA_PCSS_DMAC6_DMA_STATUS_0_U___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DMA_STATUS_0_U__XFER_FIFO_OCC___POR 0x000 +#define PHYA_PCSS_DMAC6_DMA_STATUS_0_U__ALEN_FIFO_OCC___POR 0x0 +#define PHYA_PCSS_DMAC6_DMA_STATUS_0_U__DP_FSM_STATE___POR 0x0 +#define PHYA_PCSS_DMAC6_DMA_STATUS_0_U__XFER_FIFO_OCC___M 0x01FF0000 +#define PHYA_PCSS_DMAC6_DMA_STATUS_0_U__XFER_FIFO_OCC___S 16 +#define PHYA_PCSS_DMAC6_DMA_STATUS_0_U__ALEN_FIFO_OCC___M 0x00000F00 +#define PHYA_PCSS_DMAC6_DMA_STATUS_0_U__ALEN_FIFO_OCC___S 8 +#define PHYA_PCSS_DMAC6_DMA_STATUS_0_U__DP_FSM_STATE___M 0x0000000F +#define PHYA_PCSS_DMAC6_DMA_STATUS_0_U__DP_FSM_STATE___S 0 +#define PHYA_PCSS_DMAC6_DMA_STATUS_0_U___M 0x01FF0F0F +#define PHYA_PCSS_DMAC6_DMA_STATUS_0_U___S 0 + +#define PHYA_PCSS_DMAC6_DMA_STATUS_1_L (0x00383090) +#define PHYA_PCSS_DMAC6_DMA_STATUS_1_L___RWC QCSR_REG_RO +#define PHYA_PCSS_DMAC6_DMA_STATUS_1_L___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DMA_STATUS_1_L__XFER_LEN_PEND___POR 0x000000 +#define PHYA_PCSS_DMAC6_DMA_STATUS_1_L__XFER_LEN_PEND___M 0x00FFFFFF +#define PHYA_PCSS_DMAC6_DMA_STATUS_1_L__XFER_LEN_PEND___S 0 +#define PHYA_PCSS_DMAC6_DMA_STATUS_1_L___M 0x00FFFFFF +#define PHYA_PCSS_DMAC6_DMA_STATUS_1_L___S 0 + +#define PHYA_PCSS_DMAC6_DMA_EVT_LATCH_L (0x00383098) +#define PHYA_PCSS_DMAC6_DMA_EVT_LATCH_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DMA_EVT_LATCH_L___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DMA_EVT_LATCH_L__DMA_EVT_LATCH_LSB___S 0 +#define PHYA_PCSS_DMAC6_DMA_EVT_LATCH_L___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DMA_EVT_LATCH_L___S 0 + +#define PHYA_PCSS_DMAC6_DMA_EVT_LATCH_U (0x0038309C) +#define PHYA_PCSS_DMAC6_DMA_EVT_LATCH_U___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DMA_EVT_LATCH_U___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DMA_EVT_LATCH_U__DMA_EVT_LATCH_MSB___S 0 +#define PHYA_PCSS_DMAC6_DMA_EVT_LATCH_U___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DMA_EVT_LATCH_U___S 0 + +#define PHYA_PCSS_DMAC6_DMA_EVT_TRIG_L (0x003830A0) +#define PHYA_PCSS_DMAC6_DMA_EVT_TRIG_L___RWC QCSR_REG_RO +#define PHYA_PCSS_DMAC6_DMA_EVT_TRIG_L___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DMA_EVT_TRIG_L__CUR_EVT_TRIG___POR 0x00 +#define PHYA_PCSS_DMAC6_DMA_EVT_TRIG_L__LAST_EVT_TRIG___POR 0x00 +#define PHYA_PCSS_DMAC6_DMA_EVT_TRIG_L__CUR_EVT_TRIG___M 0x0000FF00 +#define PHYA_PCSS_DMAC6_DMA_EVT_TRIG_L__CUR_EVT_TRIG___S 8 +#define PHYA_PCSS_DMAC6_DMA_EVT_TRIG_L__LAST_EVT_TRIG___M 0x000000FF +#define PHYA_PCSS_DMAC6_DMA_EVT_TRIG_L__LAST_EVT_TRIG___S 0 +#define PHYA_PCSS_DMAC6_DMA_EVT_TRIG_L___M 0x0000FFFF +#define PHYA_PCSS_DMAC6_DMA_EVT_TRIG_L___S 0 + +#define PHYA_PCSS_DMAC6_DMA_XFER_CTRL_L (0x003830A8) +#define PHYA_PCSS_DMAC6_DMA_XFER_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DMA_XFER_CTRL_L___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___POR 0x0 +#define PHYA_PCSS_DMAC6_DMA_XFER_CTRL_L__PAUSE_XFER___POR 0x0 +#define PHYA_PCSS_DMAC6_DMA_XFER_CTRL_L__STOP_XFER_MASK___POR 0x0000 +#define PHYA_PCSS_DMAC6_DMA_XFER_CTRL_L__STOP_XFER___POR 0x0 +#define PHYA_PCSS_DMAC6_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___M 0x00040000 +#define PHYA_PCSS_DMAC6_DMA_XFER_CTRL_L__PAUSE_XFER_ACK___S 18 +#define PHYA_PCSS_DMAC6_DMA_XFER_CTRL_L__PAUSE_XFER___M 0x00020000 +#define PHYA_PCSS_DMAC6_DMA_XFER_CTRL_L__PAUSE_XFER___S 17 +#define PHYA_PCSS_DMAC6_DMA_XFER_CTRL_L__STOP_XFER_MASK___M 0x0001FFFE +#define PHYA_PCSS_DMAC6_DMA_XFER_CTRL_L__STOP_XFER_MASK___S 1 +#define PHYA_PCSS_DMAC6_DMA_XFER_CTRL_L__STOP_XFER___M 0x00000001 +#define PHYA_PCSS_DMAC6_DMA_XFER_CTRL_L__STOP_XFER___S 0 +#define PHYA_PCSS_DMAC6_DMA_XFER_CTRL_L___M 0x0007FFFF +#define PHYA_PCSS_DMAC6_DMA_XFER_CTRL_L___S 0 + +#define PHYA_PCSS_DMAC6_DMA_SPARE_L (0x003830B0) +#define PHYA_PCSS_DMAC6_DMA_SPARE_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DMA_SPARE_L___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DMA_SPARE_L__DMA_SPARE_0___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DMA_SPARE_L__DMA_SPARE_0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DMA_SPARE_L__DMA_SPARE_0___S 0 +#define PHYA_PCSS_DMAC6_DMA_SPARE_L___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DMA_SPARE_L___S 0 + +#define PHYA_PCSS_DMAC6_DMA_SPARE_U (0x003830B4) +#define PHYA_PCSS_DMAC6_DMA_SPARE_U___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DMA_SPARE_U___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DMA_SPARE_U__DMA_SPARE_1___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DMA_SPARE_U__DMA_SPARE_1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DMA_SPARE_U__DMA_SPARE_1___S 0 +#define PHYA_PCSS_DMAC6_DMA_SPARE_U___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DMA_SPARE_U___S 0 + +#define PHYA_PCSS_DMAC6_DMA_ECO_L (0x003830B8) +#define PHYA_PCSS_DMAC6_DMA_ECO_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DMA_ECO_L___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DMA_ECO_L__DMA_ECO_0___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DMA_ECO_L__DMA_ECO_0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DMA_ECO_L__DMA_ECO_0___S 0 +#define PHYA_PCSS_DMAC6_DMA_ECO_L___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DMA_ECO_L___S 0 + +#define PHYA_PCSS_DMAC6_DMA_ECO_U (0x003830BC) +#define PHYA_PCSS_DMAC6_DMA_ECO_U___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DMA_ECO_U___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DMA_ECO_U__DMA_ECO_1___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DMA_ECO_U__DMA_ECO_1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DMA_ECO_U__DMA_ECO_1___S 0 +#define PHYA_PCSS_DMAC6_DMA_ECO_U___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DMA_ECO_U___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B0 (0x003830C0) +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B0__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B0__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B0__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B0__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B0__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B0___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B1 (0x003830D8) +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B1__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B1__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B1__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B1__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B1__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B1___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B2 (0x003830F0) +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B2__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B2__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B2__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B2__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B2__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B2___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B3 (0x00383108) +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B3__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B3__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B3__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B3__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B3__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B3___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B4 (0x00383120) +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B4__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B4__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B4__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B4__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B4__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B4___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B5 (0x00383138) +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B5__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B5__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B5__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B5__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B5__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B5___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B6 (0x00383150) +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B6__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B6__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B6__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B6__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B6__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B6___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B7 (0x00383168) +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B7__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B7__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B7__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B7__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B7__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B7___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B8 (0x00383180) +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B8___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B8___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B8__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B8__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B8__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B8__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B8__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B8__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B8__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B8__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B8__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B8___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B8___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B9 (0x00383198) +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B9___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B9___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B9__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B9__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B9__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B9__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B9__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B9__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B9__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B9__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B9__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B9___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B9___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B10 (0x003831B0) +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B10___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B10___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B10__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B10__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B10__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B10__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B10__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B10__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B10__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B10__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B10__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B10___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B10___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B11 (0x003831C8) +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B11___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B11___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B11__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B11__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B11__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B11__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B11__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B11__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B11__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B11__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B11__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B11___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B11___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B12 (0x003831E0) +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B12___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B12___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B12__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B12__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B12__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B12__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B12__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B12__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B12__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B12__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B12__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B12___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B12___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B13 (0x003831F8) +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B13___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B13___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B13__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B13__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B13__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B13__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B13__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B13__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B13__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B13__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B13__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B13___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B13___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B14 (0x00383210) +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B14___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B14___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B14__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B14__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B14__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B14__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B14__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B14__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B14__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B14__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B14__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B14___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B14___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B15 (0x00383228) +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B15___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B15___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B15__DMAC_SRC_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B15__DMAC_SRC_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B15__DMAC_SRC_MSB___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B15__DMAC_SRC_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B15__DMAC_SRC_STRIDE___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B15__DMAC_SRC_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B15__DMAC_SRC_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B15__DMAC_SRC_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B15__DMAC_SRC_MSB___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B15___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_0_L_B15___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B0 (0x003830C4) +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B0__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B0__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B0__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B0__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B0__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B0__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B0__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B0___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B1 (0x003830DC) +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B1__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B1__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B1__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B1__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B1__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B1__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B1__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B1___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B2 (0x003830F4) +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B2__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B2__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B2__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B2__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B2__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B2__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B2__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B2___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B3 (0x0038310C) +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B3__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B3__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B3__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B3__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B3__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B3__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B3__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B3___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B4 (0x00383124) +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B4__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B4__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B4__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B4__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B4__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B4__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B4__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B4___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B5 (0x0038313C) +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B5__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B5__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B5__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B5__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B5__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B5__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B5__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B5___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B6 (0x00383154) +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B6__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B6__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B6__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B6__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B6__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B6__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B6__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B6___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B7 (0x0038316C) +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B7__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B7__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B7__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B7__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B7__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B7__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B7__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B7___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B8 (0x00383184) +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B8___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B8___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B8__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B8__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B8__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B8__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B8__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B8__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B8__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B8__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B8__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B8___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B8___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B9 (0x0038319C) +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B9___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B9___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B9__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B9__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B9__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B9__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B9__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B9__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B9__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B9__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B9__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B9___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B9___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B10 (0x003831B4) +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B10___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B10___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B10__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B10__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B10__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B10__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B10__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B10__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B10__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B10__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B10__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B10___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B10___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B11 (0x003831CC) +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B11___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B11___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B11__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B11__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B11__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B11__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B11__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B11__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B11__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B11__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B11__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B11___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B11___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B12 (0x003831E4) +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B12___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B12___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B12__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B12__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B12__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B12__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B12__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B12__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B12__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B12__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B12__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B12___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B12___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B13 (0x003831FC) +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B13___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B13___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B13__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B13__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B13__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B13__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B13__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B13__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B13__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B13__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B13__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B13___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B13___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B14 (0x00383214) +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B14___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B14___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B14__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B14__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B14__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B14__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B14__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B14__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B14__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B14__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B14__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B14___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B14___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B15 (0x0038322C) +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B15___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B15___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B15__DMAC_DST_STRIDE___POR 0x00000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B15__DMAC_DST_DAT_STRIDE___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B15__DMAC_DST_MSB___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B15__DMAC_DST_STRIDE___M 0xFFFFC000 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B15__DMAC_DST_STRIDE___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B15__DMAC_DST_DAT_STRIDE___M 0x00003FC0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B15__DMAC_DST_DAT_STRIDE___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B15__DMAC_DST_MSB___M 0x0000003F +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B15__DMAC_DST_MSB___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B15___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_0_U_B15___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B0 (0x003830C8) +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B0__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B0__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B0__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B0___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B1 (0x003830E0) +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B1__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B1__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B1__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B1___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B2 (0x003830F8) +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B2__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B2__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B2__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B2___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B3 (0x00383110) +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B3__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B3__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B3__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B3___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B4 (0x00383128) +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B4__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B4__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B4__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B4___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B5 (0x00383140) +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B5__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B5__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B5__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B5___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B6 (0x00383158) +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B6__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B6__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B6__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B6___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B7 (0x00383170) +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B7__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B7__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B7__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B7___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B8 (0x00383188) +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B8___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B8___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B8__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B8__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B8__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B8___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B8___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B9 (0x003831A0) +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B9___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B9___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B9__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B9__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B9__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B9___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B9___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B10 (0x003831B8) +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B10___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B10___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B10__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B10__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B10__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B10___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B10___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B11 (0x003831D0) +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B11___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B11___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B11__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B11__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B11__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B11___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B11___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B12 (0x003831E8) +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B12___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B12___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B12__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B12__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B12__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B12___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B12___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B13 (0x00383200) +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B13___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B13___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B13__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B13__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B13__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B13___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B13___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B14 (0x00383218) +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B14___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B14___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B14__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B14__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B14__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B14___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B14___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B15 (0x00383230) +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B15___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B15___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B15__DMAC_DST___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B15__DMAC_DST___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B15__DMAC_DST___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B15___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_L_B15___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B0 (0x003830CC) +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B0__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B0__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B0__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B0___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B1 (0x003830E4) +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B1__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B1__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B1__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B1___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B2 (0x003830FC) +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B2__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B2__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B2__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B2___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B3 (0x00383114) +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B3__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B3__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B3__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B3___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B4 (0x0038312C) +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B4__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B4__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B4__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B4___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B5 (0x00383144) +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B5__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B5__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B5__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B5___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B6 (0x0038315C) +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B6__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B6__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B6__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B6___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B7 (0x00383174) +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B7__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B7__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B7__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B7___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B8 (0x0038318C) +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B8___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B8___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B8__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B8__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B8__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B8___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B8___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B9 (0x003831A4) +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B9___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B9___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B9__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B9__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B9__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B9___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B9___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B10 (0x003831BC) +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B10___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B10___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B10__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B10__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B10__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B10___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B10___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B11 (0x003831D4) +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B11___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B11___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B11__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B11__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B11__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B11___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B11___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B12 (0x003831EC) +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B12___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B12___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B12__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B12__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B12__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B12___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B12___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B13 (0x00383204) +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B13___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B13___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B13__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B13__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B13__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B13___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B13___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B14 (0x0038321C) +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B14___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B14___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B14__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B14__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B14__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B14___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B14___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B15 (0x00383234) +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B15___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B15___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B15__DMAC_LNK___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B15__DMAC_LNK___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B15__DMAC_LNK___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B15___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_1_U_B15___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B0 (0x003830D0) +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B0__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B0__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B0__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B0___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B1 (0x003830E8) +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B1__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B1__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B1__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B1___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B2 (0x00383100) +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B2__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B2__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B2__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B2___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B3 (0x00383118) +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B3__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B3__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B3__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B3___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B4 (0x00383130) +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B4__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B4__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B4__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B4___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B5 (0x00383148) +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B5__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B5__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B5__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B5___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B6 (0x00383160) +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B6__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B6__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B6__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B6___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B7 (0x00383178) +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B7__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B7__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B7__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B7___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B8 (0x00383190) +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B8___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B8___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B8__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B8__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B8__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B8___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B8___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B9 (0x003831A8) +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B9___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B9___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B9__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B9__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B9__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B9___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B9___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B10 (0x003831C0) +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B10___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B10___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B10__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B10__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B10__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B10___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B10___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B11 (0x003831D8) +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B11___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B11___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B11__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B11__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B11__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B11___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B11___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B12 (0x003831F0) +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B12___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B12___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B12__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B12__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B12__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B12___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B12___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B13 (0x00383208) +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B13___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B13___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B13__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B13__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B13__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B13___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B13___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B14 (0x00383220) +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B14___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B14___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B14__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B14__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B14__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B14___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B14___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B15 (0x00383238) +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B15___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B15___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B15__DMAC_SRC___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B15__DMAC_SRC___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B15__DMAC_SRC___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B15___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_L_B15___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0 (0x003830D4) +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__FRZDST___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__FRZSRC___S 5 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__DATSRC___S 2 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0__DESC_EN___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B0___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1 (0x003830EC) +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__FRZDST___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__FRZSRC___S 5 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__DATSRC___S 2 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1__DESC_EN___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B1___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2 (0x00383104) +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__FRZDST___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__FRZSRC___S 5 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__DATSRC___S 2 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2__DESC_EN___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B2___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3 (0x0038311C) +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__FRZDST___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__FRZSRC___S 5 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__DATSRC___S 2 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3__DESC_EN___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B3___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4 (0x00383134) +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__FRZDST___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__FRZSRC___S 5 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__DATSRC___S 2 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4__DESC_EN___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B4___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5 (0x0038314C) +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__FRZDST___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__FRZSRC___S 5 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__DATSRC___S 2 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5__DESC_EN___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B5___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6 (0x00383164) +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__FRZDST___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__FRZSRC___S 5 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__DATSRC___S 2 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6__DESC_EN___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B6___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7 (0x0038317C) +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__FRZDST___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__FRZSRC___S 5 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__DATSRC___S 2 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7__DESC_EN___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B7___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8 (0x00383194) +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__FRZDST___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__FRZSRC___S 5 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__DATSRC___S 2 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8__DESC_EN___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B8___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9 (0x003831AC) +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__FRZDST___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__FRZSRC___S 5 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__DATSRC___S 2 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9__DESC_EN___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B9___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10 (0x003831C4) +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__FRZDST___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__FRZSRC___S 5 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__DATSRC___S 2 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10__DESC_EN___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B10___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11 (0x003831DC) +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__FRZDST___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__FRZSRC___S 5 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__DATSRC___S 2 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11__DESC_EN___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B11___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12 (0x003831F4) +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__FRZDST___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__FRZSRC___S 5 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__DATSRC___S 2 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12__DESC_EN___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B12___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13 (0x0038320C) +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__FRZDST___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__FRZSRC___S 5 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__DATSRC___S 2 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13__DESC_EN___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B13___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14 (0x00383224) +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__FRZDST___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__FRZSRC___S 5 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__DATSRC___S 2 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14__DESC_EN___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B14___S 0 + +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15 (0x0038323C) +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__XFER_LEN___POR 0x000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__EVTI_CFG___POR 0x00 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__NO_BURST_DST___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__NO_BURST_SRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__USE_TRIGGER___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__XFER_EN_32BIT___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__XFER_LEN_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__USE_DST_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__USE_SRC_STRIDE___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__FRZDST___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__FRZSRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__EVTO_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__NEW_DESC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__DATSRC___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__WAIT_EVT___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__DESC_EN___POR 0x0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__XFER_LEN___M 0xFFF00000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__XFER_LEN___S 20 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__EVTI_CFG___M 0x000FC000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__EVTI_CFG___S 14 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__NO_BURST_DST___M 0x00002000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__NO_BURST_DST___S 13 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__NO_BURST_SRC___M 0x00001000 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__NO_BURST_SRC___S 12 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__USE_TRIGGER___M 0x00000800 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__USE_TRIGGER___S 11 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__XFER_EN_32BIT___M 0x00000400 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__XFER_EN_32BIT___S 10 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__XFER_LEN_EN___M 0x00000200 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__XFER_LEN_EN___S 9 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__USE_DST_STRIDE___M 0x00000100 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__USE_DST_STRIDE___S 8 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__USE_SRC_STRIDE___M 0x00000080 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__USE_SRC_STRIDE___S 7 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__FRZDST___M 0x00000040 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__FRZDST___S 6 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__FRZSRC___M 0x00000020 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__FRZSRC___S 5 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__EVTO_EN___M 0x00000010 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__EVTO_EN___S 4 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__NEW_DESC___M 0x00000008 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__NEW_DESC___S 3 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__DATSRC___M 0x00000004 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__DATSRC___S 2 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__WAIT_EVT___M 0x00000002 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__WAIT_EVT___S 1 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__DESC_EN___M 0x00000001 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15__DESC_EN___S 0 +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15___M 0xFFFFFFFF +#define PHYA_PCSS_DMAC6_DESC_REG_2_U_B15___S 0 + +#define PHYA_PCSS_DMAC6_DMAC2PHYDBG_EN_REG_L (0x00383240) +#define PHYA_PCSS_DMAC6_DMAC2PHYDBG_EN_REG_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DMAC2PHYDBG_EN_REG_L___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___POR 0x0000 +#define PHYA_PCSS_DMAC6_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___M 0x0000FFFF +#define PHYA_PCSS_DMAC6_DMAC2PHYDBG_EN_REG_L__DMAC2PHYDBG_EN___S 0 +#define PHYA_PCSS_DMAC6_DMAC2PHYDBG_EN_REG_L___M 0x0000FFFF +#define PHYA_PCSS_DMAC6_DMAC2PHYDBG_EN_REG_L___S 0 + +#define PHYA_PCSS_DMAC6_DUMMY_L (0x00383248) +#define PHYA_PCSS_DMAC6_DUMMY_L___RWC QCSR_REG_RW +#define PHYA_PCSS_DMAC6_DUMMY_L___POR 0x00000000 +#define PHYA_PCSS_DMAC6_DUMMY_L__DUMMY___POR 0x0 +#define PHYA_PCSS_DMAC6_DUMMY_L__DUMMY___M 0x00000001 +#define PHYA_PCSS_DMAC6_DUMMY_L__DUMMY___S 0 +#define PHYA_PCSS_DMAC6_DUMMY_L___M 0x00000001 +#define PHYA_PCSS_DMAC6_DUMMY_L___S 0 + +#define PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_LOW (0x00388000) +#define PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_LOW___POR 0x00021F1B +#define PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_LOW__UNITTYPEID___POR 0x02 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_LOW__UNITCONFID___POR 0x1F1B +#define PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_LOW__UNITTYPEID___S 16 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_LOW__UNITCONFID___S 0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_LOW___M 0x00FFFFFF +#define PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_HIGH (0x00388004) +#define PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_HIGH___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_HIGH___POR 0xA8AF23E2 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_HIGH__QNOCID___S 0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_HIGH___M 0xFFFFFFFF +#define PHYA_NOC_PHYA_NOC_EC_PRB0_SWID_HIGH___S 0 + +#define PHYA_NOC_PHYA_NOC_EC_PRB0_MAINCTL_LOW (0x00388008) +#define PHYA_NOC_PHYA_NOC_EC_PRB0_MAINCTL_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_EC_PRB0_MAINCTL_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_MAINCTL_LOW__DUMPEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_MAINCTL_LOW__GLBEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000004 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_MAINCTL_LOW__IGNORECTITRIGIN0___S 2 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_MAINCTL_LOW__DUMPEN___M 0x00000002 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_MAINCTL_LOW__DUMPEN___S 1 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_MAINCTL_LOW__GLBEN___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_MAINCTL_LOW__GLBEN___S 0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_MAINCTL_LOW___M 0x00000007 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_MAINCTL_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPGO_LOW (0x00388010) +#define PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPGO_LOW___RWC QCSR_REG_WO +#define PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPGO_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPGO_LOW__DUMPGO___POR 0x0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPGO_LOW__DUMPGO___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPGO_LOW__DUMPGO___S 0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPGO_LOW___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPGO_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPPERIOD_LOW (0x00388018) +#define PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPPERIOD_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPPERIOD_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPPERIOD_LOW__DUMPPERIOD___POR 0x00 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPPERIOD_LOW__DUMPPERIOD___M 0x0000001F +#define PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPPERIOD_LOW__DUMPPERIOD___S 0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPPERIOD_LOW___M 0x0000001F +#define PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPPERIOD_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPTHR_LOW (0x00388020) +#define PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPTHR_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPTHR_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPTHR_LOW__DUMPTHR___POR 0x0000 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPTHR_LOW__DUMPTHR___M 0x0000FFFF +#define PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPTHR_LOW__DUMPTHR___S 0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPTHR_LOW___M 0x0000FFFF +#define PHYA_NOC_PHYA_NOC_EC_PRB0_DUMPTHR_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMMIN_LOW (0x00388028) +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMMIN_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMMIN_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMMIN_LOW__ALARMMIN___POR 0x0000 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMMIN_LOW__ALARMMIN___M 0x0000FFFF +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMMIN_LOW__ALARMMIN___S 0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMMIN_LOW___M 0x0000FFFF +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMMIN_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMMAX_LOW (0x00388030) +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMMAX_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMMAX_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMMAX_LOW__ALARMMAX___POR 0x0000 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMMAX_LOW__ALARMMAX___M 0x0000FFFF +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMMAX_LOW__ALARMMAX___S 0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMMAX_LOW___M 0x0000FFFF +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMMAX_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMSTATUS_LOW (0x00388038) +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMSTATUS_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMSTATUS_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMSTATUS_LOW__ALARMSTATUS___POR 0x0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMSTATUS_LOW__ALARMSTATUS___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMSTATUS_LOW__ALARMSTATUS___S 0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMSTATUS_LOW___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMSTATUS_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMCLR_LOW (0x00388040) +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMCLR_LOW___RWC QCSR_REG_WO +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMCLR_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMCLR_LOW__ALARMCLR___POR 0x0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMCLR_LOW__ALARMCLR___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMCLR_LOW__ALARMCLR___S 0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMCLR_LOW___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMCLR_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMEN_LOW (0x00388048) +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMEN_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMEN_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMEN_LOW__ALARMEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMEN_LOW__ALARMEN___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMEN_LOW__ALARMEN___S 0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMEN_LOW___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_ALARMEN_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW (0x00388100) +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW___POR 0x0000007F +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__ALARMMODE___POR 0x0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__DUMPTHREN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__EVENTSRC___POR 0x7F +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__ALARMMODE___M 0x00000600 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__ALARMMODE___S 9 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__DUMPTHREN___M 0x00000100 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__DUMPTHREN___S 8 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__EVENTSRC___M 0x0000007F +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__EVENTSRC___S 0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW___M 0x0000077F +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0VAL_LOW (0x00388140) +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0VAL_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0VAL_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0VAL_LOW__COUNTER0VAL___POR 0x0000 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0VAL_LOW__COUNTER0VAL___M 0x0000FFFF +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0VAL_LOW__COUNTER0VAL___S 0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0VAL_LOW___M 0x0000FFFF +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER0VAL_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW (0x00388180) +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW___POR 0x0000007F +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__ALARMMODE___POR 0x0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__DUMPTHREN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__EVENTSRC___POR 0x7F +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__ALARMMODE___M 0x00000600 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__ALARMMODE___S 9 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__DUMPTHREN___M 0x00000100 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__DUMPTHREN___S 8 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__EVENTSRC___M 0x0000007F +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__EVENTSRC___S 0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW___M 0x0000077F +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1VAL_LOW (0x003881C0) +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1VAL_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1VAL_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1VAL_LOW__COUNTER1VAL___POR 0x0000 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1VAL_LOW__COUNTER1VAL___M 0x0000FFFF +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1VAL_LOW__COUNTER1VAL___S 0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1VAL_LOW___M 0x0000FFFF +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER1VAL_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW (0x00388200) +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW___POR 0x0000007F +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__ALARMMODE___POR 0x0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__DUMPTHREN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__EVENTSRC___POR 0x7F +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__ALARMMODE___M 0x00000600 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__ALARMMODE___S 9 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__DUMPTHREN___M 0x00000100 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__DUMPTHREN___S 8 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__EVENTSRC___M 0x0000007F +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__EVENTSRC___S 0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW___M 0x0000077F +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2VAL_LOW (0x00388240) +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2VAL_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2VAL_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2VAL_LOW__COUNTER2VAL___POR 0x0000 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2VAL_LOW__COUNTER2VAL___M 0x0000FFFF +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2VAL_LOW__COUNTER2VAL___S 0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2VAL_LOW___M 0x0000FFFF +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER2VAL_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW (0x00388280) +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW___POR 0x0000007F +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__ALARMMODE___POR 0x0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__DUMPTHREN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__EVENTSRC___POR 0x7F +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__ALARMMODE___M 0x00000600 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__ALARMMODE___S 9 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__DUMPTHREN___M 0x00000100 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__DUMPTHREN___S 8 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__EVENTSRC___M 0x0000007F +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__EVENTSRC___S 0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW___M 0x0000077F +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3VAL_LOW (0x003882C0) +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3VAL_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3VAL_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3VAL_LOW__COUNTER3VAL___POR 0x0000 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3VAL_LOW__COUNTER3VAL___M 0x0000FFFF +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3VAL_LOW__COUNTER3VAL___S 0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3VAL_LOW___M 0x0000FFFF +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER3VAL_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW (0x00388300) +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW___POR 0x0000007F +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__ALARMMODE___POR 0x0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__DUMPTHREN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__EVENTSRC___POR 0x7F +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__ALARMMODE___M 0x00000600 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__ALARMMODE___S 9 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__DUMPTHREN___M 0x00000100 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__DUMPTHREN___S 8 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__EVENTSRC___M 0x0000007F +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__EVENTSRC___S 0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW___M 0x0000077F +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4VAL_LOW (0x00388340) +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4VAL_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4VAL_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4VAL_LOW__COUNTER4VAL___POR 0x0000 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4VAL_LOW__COUNTER4VAL___M 0x0000FFFF +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4VAL_LOW__COUNTER4VAL___S 0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4VAL_LOW___M 0x0000FFFF +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER4VAL_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW (0x00388380) +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW___POR 0x0000007F +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__ALARMMODE___POR 0x0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__DUMPTHREN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__EVENTSRC___POR 0x7F +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__ALARMMODE___M 0x00000600 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__ALARMMODE___S 9 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__DUMPTHREN___M 0x00000100 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__DUMPTHREN___S 8 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__EVENTSRC___M 0x0000007F +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__EVENTSRC___S 0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW___M 0x0000077F +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5VAL_LOW (0x003883C0) +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5VAL_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5VAL_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5VAL_LOW__COUNTER5VAL___POR 0x0000 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5VAL_LOW__COUNTER5VAL___M 0x0000FFFF +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5VAL_LOW__COUNTER5VAL___S 0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5VAL_LOW___M 0x0000FFFF +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER5VAL_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW (0x00388400) +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW___POR 0x0000007F +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__ALARMMODE___POR 0x0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__DUMPTHREN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__EVENTSRC___POR 0x7F +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__ALARMMODE___M 0x00000600 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__ALARMMODE___S 9 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__DUMPTHREN___M 0x00000100 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__DUMPTHREN___S 8 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__EVENTSRC___M 0x0000007F +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__EVENTSRC___S 0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW___M 0x0000077F +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6VAL_LOW (0x00388440) +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6VAL_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6VAL_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6VAL_LOW__COUNTER6VAL___POR 0x0000 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6VAL_LOW__COUNTER6VAL___M 0x0000FFFF +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6VAL_LOW__COUNTER6VAL___S 0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6VAL_LOW___M 0x0000FFFF +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER6VAL_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW (0x00388480) +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW___POR 0x0000007F +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__ALARMMODE___POR 0x0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__DUMPTHREN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__EVENTSRC___POR 0x7F +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__ALARMMODE___M 0x00000600 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__ALARMMODE___S 9 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__DUMPTHREN___M 0x00000100 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__DUMPTHREN___S 8 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__EVENTSRC___M 0x0000007F +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__EVENTSRC___S 0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW___M 0x0000077F +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7VAL_LOW (0x003884C0) +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7VAL_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7VAL_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7VAL_LOW__COUNTER7VAL___POR 0x0000 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7VAL_LOW__COUNTER7VAL___M 0x0000FFFF +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7VAL_LOW__COUNTER7VAL___S 0 +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7VAL_LOW___M 0x0000FFFF +#define PHYA_NOC_PHYA_NOC_EC_PRB0_COUNTER7VAL_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_LOW (0x00389000) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_LOW___POR 0x001237AA +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_LOW__UNITTYPEID___POR 0x12 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_LOW__UNITCONFID___POR 0x37AA +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_LOW__UNITTYPEID___S 16 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_LOW__UNITCONFID___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_LOW___M 0x00FFFFFF +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_HIGH (0x00389004) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_HIGH___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_HIGH___POR 0xA8AF23E2 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_HIGH__QNOCID___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_HIGH___M 0xFFFFFFFF +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_SWID_HIGH___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW (0x00389008) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__DUMPFORMAT___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__ALARMEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__DUMPEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__GLBEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__IGNORECTITRIGIN0___S 5 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__DUMPFORMAT___M 0x00000008 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__DUMPFORMAT___S 3 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__ALARMEN___M 0x00000004 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__ALARMEN___S 2 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__DUMPEN___M 0x00000002 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__DUMPEN___S 1 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__GLBEN___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__GLBEN___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW___M 0x0000002F +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW (0x00389010) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW__PLA___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW__FILTER___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW__PLA___M 0x80000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW__PLA___S 31 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW__FILTER___M 0x00000003 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW__FILTER___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW___M 0x80000003 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW (0x00389018) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW__PLA___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW__FILTER___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW__PLA___M 0x80000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW__PLA___S 31 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW__FILTER___M 0x00000003 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW__FILTER___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW___M 0x80000003 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW (0x00389020) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW___RWC QCSR_REG_WO +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW__PLA___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW__FILTER___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW__PLA___M 0x80000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW__PLA___S 31 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW__FILTER___M 0x00000003 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW__FILTER___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW___M 0x80000003 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ANDINV_LOW (0x00389028) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ANDINV_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ANDINV_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ANDINV_LOW__PLA___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ANDINV_LOW__FILTER___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ANDINV_LOW__PLA___M 0x80000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ANDINV_LOW__PLA___S 31 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ANDINV_LOW__FILTER___M 0x00000003 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ANDINV_LOW__FILTER___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ANDINV_LOW___M 0x80000003 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_ANDINV_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_PORTSEL_LOW (0x00389030) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_PORTSEL_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_PORTSEL_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_PORTSEL_LOW__PORTSEL___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_PORTSEL_LOW__PORTSEL___M 0x00000007 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_PORTSEL_LOW__PORTSEL___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_PORTSEL_LOW___M 0x00000007 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_PORTSEL_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_LOW (0x00389120) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___POR 0x0000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFFC0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___S 6 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_LOW___M 0xFFFFFFC0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_LOW___S 6 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_HIGH (0x00389124) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_HIGH___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_HIGH___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000003F +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_HIGH___M 0x0000003F +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_HIGH___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_LOW (0x00389128) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___POR 0x0000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFFC0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___S 6 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_LOW___M 0xFFFFFFC0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_LOW___S 6 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_HIGH (0x0038912C) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_HIGH___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_HIGH___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000003F +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_HIGH___M 0x0000003F +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_HIGH___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW (0x00389138) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__ATOMEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__CMEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__EXCLEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__WREN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__RDEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__ATOMEN___M 0x00000010 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__ATOMEN___S 4 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__CMEN___M 0x00000008 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__CMEN___S 3 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__EXCLEN___M 0x00000004 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__EXCLEN___S 2 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__WREN___M 0x00000002 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__WREN___S 1 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__RDEN___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__RDEN___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW___M 0x0000001F +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW (0x00389140) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__FAILEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__RSPEEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__ERREN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__REQRSPEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__FAILEN___M 0x00000008 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__FAILEN___S 3 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__RSPEEN___M 0x00000004 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__RSPEEN___S 2 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__ERREN___M 0x00000002 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__ERREN___S 1 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__REQRSPEN___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__REQRSPEN___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW___M 0x0000000F +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_BASE_LOW (0x00389178) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_BASE_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_BASE_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_BASE_LOW__FILTERS_0_EXTID_BASE___POR 0x000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_BASE_LOW__FILTERS_0_EXTID_BASE___M 0x000003FF +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_BASE_LOW__FILTERS_0_EXTID_BASE___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_BASE_LOW___M 0x000003FF +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_BASE_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_MASK_LOW (0x00389180) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_MASK_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_MASK_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_MASK_LOW__FILTERS_0_EXTID_MASK___POR 0x000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_MASK_LOW__FILTERS_0_EXTID_MASK___M 0x000003FF +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_MASK_LOW__FILTERS_0_EXTID_MASK___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_MASK_LOW___M 0x000003FF +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_MASK_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_URGENCY_LOW (0x00389190) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_URGENCY_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_URGENCY_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_URGENCY_LOW__FILTERS_0_URGENCY___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_URGENCY_LOW__FILTERS_0_URGENCY___M 0x00000003 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_URGENCY_LOW__FILTERS_0_URGENCY___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_URGENCY_LOW___M 0x00000003 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_0_URGENCY_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_LOW (0x00389220) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___POR 0x0000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFFC0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___S 6 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_LOW___M 0xFFFFFFC0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_LOW___S 6 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_HIGH (0x00389224) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_HIGH___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_HIGH___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000003F +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_HIGH___M 0x0000003F +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_HIGH___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_LOW (0x00389228) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___POR 0x0000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFFC0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___S 6 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_LOW___M 0xFFFFFFC0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_LOW___S 6 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_HIGH (0x0038922C) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_HIGH___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_HIGH___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000003F +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_HIGH___M 0x0000003F +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_HIGH___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW (0x00389238) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__ATOMEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__CMEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__EXCLEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__WREN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__RDEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__ATOMEN___M 0x00000010 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__ATOMEN___S 4 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__CMEN___M 0x00000008 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__CMEN___S 3 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__EXCLEN___M 0x00000004 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__EXCLEN___S 2 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__WREN___M 0x00000002 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__WREN___S 1 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__RDEN___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__RDEN___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW___M 0x0000001F +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW (0x00389240) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__FAILEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__RSPEEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__ERREN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__REQRSPEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__FAILEN___M 0x00000008 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__FAILEN___S 3 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__RSPEEN___M 0x00000004 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__RSPEEN___S 2 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__ERREN___M 0x00000002 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__ERREN___S 1 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__REQRSPEN___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__REQRSPEN___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW___M 0x0000000F +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_BASE_LOW (0x00389278) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_BASE_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_BASE_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_BASE_LOW__FILTERS_1_EXTID_BASE___POR 0x000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_BASE_LOW__FILTERS_1_EXTID_BASE___M 0x000003FF +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_BASE_LOW__FILTERS_1_EXTID_BASE___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_BASE_LOW___M 0x000003FF +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_BASE_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_MASK_LOW (0x00389280) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_MASK_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_MASK_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_MASK_LOW__FILTERS_1_EXTID_MASK___POR 0x000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_MASK_LOW__FILTERS_1_EXTID_MASK___M 0x000003FF +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_MASK_LOW__FILTERS_1_EXTID_MASK___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_MASK_LOW___M 0x000003FF +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_MASK_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_URGENCY_LOW (0x00389290) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_URGENCY_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_URGENCY_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_URGENCY_LOW__FILTERS_1_URGENCY___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_URGENCY_LOW__FILTERS_1_URGENCY___M 0x00000003 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_URGENCY_LOW__FILTERS_1_URGENCY___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_URGENCY_LOW___M 0x00000003 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB0_FILTERS_1_URGENCY_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_LOW (0x00389400) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_LOW___POR 0x0012C2E1 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_LOW__UNITTYPEID___POR 0x12 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_LOW__UNITCONFID___POR 0xC2E1 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_LOW__UNITTYPEID___S 16 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_LOW__UNITCONFID___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_LOW___M 0x00FFFFFF +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_HIGH (0x00389404) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_HIGH___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_HIGH___POR 0xA8AF23E2 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_HIGH__QNOCID___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_HIGH___M 0xFFFFFFFF +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_SWID_HIGH___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW (0x00389408) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__DUMPFORMAT___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__ALARMEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__DUMPEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__GLBEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__IGNORECTITRIGIN0___S 5 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__DUMPFORMAT___M 0x00000008 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__DUMPFORMAT___S 3 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__ALARMEN___M 0x00000004 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__ALARMEN___S 2 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__DUMPEN___M 0x00000002 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__DUMPEN___S 1 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__GLBEN___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__GLBEN___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW___M 0x0000002F +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW (0x00389410) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW__PLA___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW__FILTER___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW__PLA___M 0x80000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW__PLA___S 31 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW__FILTER___M 0x00000003 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW__FILTER___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW___M 0x80000003 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW (0x00389418) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW__PLA___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW__FILTER___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW__PLA___M 0x80000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW__PLA___S 31 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW__FILTER___M 0x00000003 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW__FILTER___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW___M 0x80000003 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW (0x00389420) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW___RWC QCSR_REG_WO +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW__PLA___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW__FILTER___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW__PLA___M 0x80000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW__PLA___S 31 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW__FILTER___M 0x00000003 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW__FILTER___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW___M 0x80000003 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW (0x00389428) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW__PLA___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW__FILTER___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW__PLA___M 0x80000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW__PLA___S 31 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW__FILTER___M 0x00000003 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW__FILTER___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW___M 0x80000003 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_PORTSEL_LOW (0x00389430) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_PORTSEL_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_PORTSEL_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_PORTSEL_LOW__PORTSEL___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_PORTSEL_LOW__PORTSEL___M 0x00000007 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_PORTSEL_LOW__PORTSEL___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_PORTSEL_LOW___M 0x00000007 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_PORTSEL_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_LOW (0x00389520) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___POR 0x0000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFFC0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___S 6 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_LOW___M 0xFFFFFFC0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_LOW___S 6 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_HIGH (0x00389524) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_HIGH___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_HIGH___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000003F +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_HIGH___M 0x0000003F +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_HIGH___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_LOW (0x00389528) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___POR 0x0000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFFC0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___S 6 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_LOW___M 0xFFFFFFC0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_LOW___S 6 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_HIGH (0x0038952C) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_HIGH___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_HIGH___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000003F +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_HIGH___M 0x0000003F +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_HIGH___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW (0x00389538) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__ATOMEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__CMEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__EXCLEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__WREN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__RDEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__ATOMEN___M 0x00000010 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__ATOMEN___S 4 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__CMEN___M 0x00000008 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__CMEN___S 3 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__EXCLEN___M 0x00000004 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__EXCLEN___S 2 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__WREN___M 0x00000002 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__WREN___S 1 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__RDEN___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__RDEN___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW___M 0x0000001F +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW (0x00389540) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__FAILEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__RSPEEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__ERREN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__REQRSPEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__FAILEN___M 0x00000008 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__FAILEN___S 3 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__RSPEEN___M 0x00000004 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__RSPEEN___S 2 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__ERREN___M 0x00000002 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__ERREN___S 1 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__REQRSPEN___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__REQRSPEN___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW___M 0x0000000F +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_BASE_LOW (0x00389578) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_BASE_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_BASE_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_BASE_LOW__FILTERS_0_EXTID_BASE___POR 0x000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_BASE_LOW__FILTERS_0_EXTID_BASE___M 0x000003FF +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_BASE_LOW__FILTERS_0_EXTID_BASE___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_BASE_LOW___M 0x000003FF +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_BASE_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_MASK_LOW (0x00389580) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_MASK_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_MASK_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_MASK_LOW__FILTERS_0_EXTID_MASK___POR 0x000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_MASK_LOW__FILTERS_0_EXTID_MASK___M 0x000003FF +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_MASK_LOW__FILTERS_0_EXTID_MASK___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_MASK_LOW___M 0x000003FF +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_MASK_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_URGENCY_LOW (0x00389590) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_URGENCY_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_URGENCY_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_URGENCY_LOW__FILTERS_0_URGENCY___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_URGENCY_LOW__FILTERS_0_URGENCY___M 0x00000003 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_URGENCY_LOW__FILTERS_0_URGENCY___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_URGENCY_LOW___M 0x00000003 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_0_URGENCY_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_LOW (0x00389620) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___POR 0x0000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFFC0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___S 6 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_LOW___M 0xFFFFFFC0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_LOW___S 6 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_HIGH (0x00389624) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_HIGH___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_HIGH___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000003F +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_HIGH___M 0x0000003F +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_HIGH___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_LOW (0x00389628) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___POR 0x0000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFFC0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___S 6 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_LOW___M 0xFFFFFFC0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_LOW___S 6 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_HIGH (0x0038962C) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_HIGH___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_HIGH___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000003F +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_HIGH___M 0x0000003F +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_HIGH___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW (0x00389638) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__ATOMEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__CMEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__EXCLEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__WREN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__RDEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__ATOMEN___M 0x00000010 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__ATOMEN___S 4 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__CMEN___M 0x00000008 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__CMEN___S 3 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__EXCLEN___M 0x00000004 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__EXCLEN___S 2 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__WREN___M 0x00000002 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__WREN___S 1 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__RDEN___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__RDEN___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW___M 0x0000001F +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW (0x00389640) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__FAILEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__RSPEEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__ERREN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__REQRSPEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__FAILEN___M 0x00000008 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__FAILEN___S 3 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__RSPEEN___M 0x00000004 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__RSPEEN___S 2 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__ERREN___M 0x00000002 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__ERREN___S 1 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__REQRSPEN___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__REQRSPEN___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW___M 0x0000000F +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_BASE_LOW (0x00389678) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_BASE_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_BASE_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_BASE_LOW__FILTERS_1_EXTID_BASE___POR 0x000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_BASE_LOW__FILTERS_1_EXTID_BASE___M 0x000003FF +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_BASE_LOW__FILTERS_1_EXTID_BASE___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_BASE_LOW___M 0x000003FF +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_BASE_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_MASK_LOW (0x00389680) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_MASK_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_MASK_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_MASK_LOW__FILTERS_1_EXTID_MASK___POR 0x000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_MASK_LOW__FILTERS_1_EXTID_MASK___M 0x000003FF +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_MASK_LOW__FILTERS_1_EXTID_MASK___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_MASK_LOW___M 0x000003FF +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_MASK_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_URGENCY_LOW (0x00389690) +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_URGENCY_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_URGENCY_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_URGENCY_LOW__FILTERS_1_URGENCY___POR 0x0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_URGENCY_LOW__FILTERS_1_URGENCY___M 0x00000003 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_URGENCY_LOW__FILTERS_1_URGENCY___S 0 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_URGENCY_LOW___M 0x00000003 +#define PHYA_NOC_PHYA_NOC_TRACE_PRB_1_FILTERS_1_URGENCY_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW (0x00389800) +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW___POR 0x000341AC +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW__UNITTYPEID___POR 0x03 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW__UNITCONFID___POR 0x41AC +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW__UNITTYPEID___S 16 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW__UNITCONFID___S 0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW___M 0x00FFFFFF +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_HIGH (0x00389804) +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_HIGH___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_HIGH___POR 0xA8AF23E2 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_HIGH__QNOCID___S 0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_HIGH___M 0xFFFFFFFF +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_SWID_HIGH___S 0 + +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW (0x00389808) +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__SCALEEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__DUMPEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__MODE___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___M 0x00000300 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___S 8 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___S 5 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___M 0x00000010 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___S 4 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__SCALEEN___M 0x00000008 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__SCALEEN___S 3 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__DUMPEN___M 0x00000004 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__DUMPEN___S 2 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__MODE___M 0x00000003 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__MODE___S 0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW___M 0x0000033F +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_DUMPGO_LOW (0x00389810) +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_DUMPGO_LOW___RWC QCSR_REG_WO +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_DUMPGO_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_DUMPGO_LOW__DUMPGO___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_DUMPGO_LOW__DUMPGO___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_DUMPGO_LOW__DUMPGO___S 0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_DUMPGO_LOW___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_DUMPGO_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_DUMPTHR_LOW (0x00389818) +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_DUMPTHR_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_DUMPTHR_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_DUMPTHR_LOW__DUMPTHR___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_DUMPTHR_LOW__DUMPTHR___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_DUMPTHR_LOW__DUMPTHR___S 0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_DUMPTHR_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_DUMPTHR_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW (0x00389820) +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW___POR 0x01400000 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__NOMINALFREQ___POR 0x140 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__OFFSET___POR 0x00 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__WIDTH___POR 0x00 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__NOMINALFREQ___M 0x0FFF0000 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__NOMINALFREQ___S 16 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__OFFSET___M 0x0000FF00 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__OFFSET___S 8 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__WIDTH___M 0x000000FF +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__WIDTH___S 0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW___M 0x0FFFFFFF +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_LOW (0x00389828) +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_LOW__LATSUM___POR 0x0000000 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_LOW__LATSUM___M 0x0FFFFFFF +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_LOW__LATSUM___S 0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_LOW___M 0x0FFFFFFF +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_HIGH (0x0038982C) +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_HIGH___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_HIGH___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_HIGH__TRCNT___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_HIGH__TRCNT___M 0x000FFF00 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_HIGH__TRCNT___S 8 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_HIGH___M 0x000FFF00 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_HIGH___S 8 + +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN0_LOW (0x00389840) +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN0_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN0_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN0_LOW__HISTBIN0___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN0_LOW__HISTBIN0___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN0_LOW__HISTBIN0___S 0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN0_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN0_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN1_LOW (0x00389848) +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN1_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN1_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN1_LOW__HISTBIN1___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN1_LOW__HISTBIN1___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN1_LOW__HISTBIN1___S 0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN1_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN1_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN2_LOW (0x00389850) +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN2_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN2_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN2_LOW__HISTBIN2___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN2_LOW__HISTBIN2___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN2_LOW__HISTBIN2___S 0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN2_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN2_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN3_LOW (0x00389858) +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN3_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN3_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN3_LOW__HISTBIN3___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN3_LOW__HISTBIN3___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN3_LOW__HISTBIN3___S 0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN3_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN3_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN4_LOW (0x00389860) +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN4_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN4_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN4_LOW__HISTBIN4___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN4_LOW__HISTBIN4___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN4_LOW__HISTBIN4___S 0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN4_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN4_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN5_LOW (0x00389868) +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN5_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN5_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN5_LOW__HISTBIN5___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN5_LOW__HISTBIN5___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN5_LOW__HISTBIN5___S 0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN5_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN5_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN6_LOW (0x00389870) +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN6_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN6_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN6_LOW__HISTBIN6___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN6_LOW__HISTBIN6___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN6_LOW__HISTBIN6___S 0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN6_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN6_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN7_LOW (0x00389878) +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN7_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN7_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN7_LOW__HISTBIN7___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN7_LOW__HISTBIN7___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN7_LOW__HISTBIN7___S 0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN7_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN7_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_LATMAX_LOW (0x00389880) +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_LATMAX_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_LATMAX_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_LATMAX_LOW__LATMAX___POR 0x00 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_LATMAX_LOW__LATMAX___M 0x000000FF +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_LATMAX_LOW__LATMAX___S 0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_LATMAX_LOW___M 0x000000FF +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_LATMAX_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MIN_LOW (0x00389920) +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MIN_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MIN_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE___POR 0x000000 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE___M 0xFFFFFC00 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE___S 10 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MIN_LOW___M 0xFFFFFC00 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MIN_LOW___S 10 + +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MAX_LOW (0x00389928) +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MAX_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MAX_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE___POR 0x000000 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE___M 0xFFFFFC00 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE___S 10 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MAX_LOW___M 0xFFFFFC00 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MAX_LOW___S 10 + +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW (0x00389938) +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__CMEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__WREN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__RDEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___M 0x00000010 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___S 4 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__CMEN___M 0x00000008 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__CMEN___S 3 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___M 0x00000004 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___S 2 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__WREN___M 0x00000002 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__WREN___S 1 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__RDEN___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__RDEN___S 0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW___M 0x0000001F +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW (0x00389968) +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__SHAREDEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__CACHEDEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__NORMALEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__DEVEEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__DEVNEEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__SHAREDEN___M 0x00000010 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__SHAREDEN___S 4 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__CACHEDEN___M 0x00000008 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__CACHEDEN___S 3 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__NORMALEN___M 0x00000004 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__NORMALEN___S 2 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__DEVEEN___M 0x00000002 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__DEVEEN___S 1 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__DEVNEEN___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__DEVNEEN___S 0 +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW___M 0x0000001F +#define PHYA_NOC_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW (0x0038A000) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW___POR 0x00039006 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW__UNITTYPEID___POR 0x03 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW__UNITCONFID___POR 0x9006 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW__UNITTYPEID___S 16 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW__UNITCONFID___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW___M 0x00FFFFFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_HIGH (0x0038A004) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_HIGH___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_HIGH___POR 0xA8AF23E2 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_HIGH__QNOCID___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_HIGH___M 0xFFFFFFFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_HIGH___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW (0x0038A008) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__SCALEEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__DUMPEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__MODE___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___M 0x00000300 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___S 8 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___S 5 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___M 0x00000010 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___S 4 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__SCALEEN___M 0x00000008 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__SCALEEN___S 3 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__DUMPEN___M 0x00000004 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__DUMPEN___S 2 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__MODE___M 0x00000003 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__MODE___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW___M 0x0000033F +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPGO_LOW (0x0038A010) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPGO_LOW___RWC QCSR_REG_WO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPGO_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPGO_LOW__DUMPGO___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPGO_LOW__DUMPGO___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPGO_LOW__DUMPGO___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPGO_LOW___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPGO_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPTHR_LOW (0x0038A018) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPTHR_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPTHR_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPTHR_LOW__DUMPTHR___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPTHR_LOW__DUMPTHR___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPTHR_LOW__DUMPTHR___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPTHR_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPTHR_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW (0x0038A020) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW___POR 0x01400000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__NOMINALFREQ___POR 0x140 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__OFFSET___POR 0x00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__WIDTH___POR 0x00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__NOMINALFREQ___M 0x0FFF0000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__NOMINALFREQ___S 16 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__OFFSET___M 0x0000FF00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__OFFSET___S 8 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__WIDTH___M 0x000000FF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__WIDTH___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW___M 0x0FFFFFFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_LOW (0x0038A028) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_LOW__LATSUM___POR 0x0000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_LOW__LATSUM___M 0x0FFFFFFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_LOW__LATSUM___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_LOW___M 0x0FFFFFFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_HIGH (0x0038A02C) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_HIGH___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_HIGH___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_HIGH__TRCNT___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_HIGH__TRCNT___M 0x000FFF00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_HIGH__TRCNT___S 8 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_HIGH___M 0x000FFF00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_HIGH___S 8 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN0_LOW (0x0038A040) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN0_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN0_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN0_LOW__HISTBIN0___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN0_LOW__HISTBIN0___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN0_LOW__HISTBIN0___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN0_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN0_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN1_LOW (0x0038A048) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN1_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN1_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN1_LOW__HISTBIN1___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN1_LOW__HISTBIN1___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN1_LOW__HISTBIN1___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN1_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN1_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN2_LOW (0x0038A050) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN2_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN2_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN2_LOW__HISTBIN2___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN2_LOW__HISTBIN2___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN2_LOW__HISTBIN2___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN2_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN2_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN3_LOW (0x0038A058) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN3_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN3_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN3_LOW__HISTBIN3___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN3_LOW__HISTBIN3___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN3_LOW__HISTBIN3___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN3_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN3_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN4_LOW (0x0038A060) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN4_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN4_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN4_LOW__HISTBIN4___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN4_LOW__HISTBIN4___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN4_LOW__HISTBIN4___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN4_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN4_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN5_LOW (0x0038A068) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN5_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN5_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN5_LOW__HISTBIN5___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN5_LOW__HISTBIN5___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN5_LOW__HISTBIN5___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN5_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN5_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN6_LOW (0x0038A070) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN6_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN6_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN6_LOW__HISTBIN6___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN6_LOW__HISTBIN6___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN6_LOW__HISTBIN6___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN6_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN6_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN7_LOW (0x0038A078) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN7_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN7_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN7_LOW__HISTBIN7___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN7_LOW__HISTBIN7___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN7_LOW__HISTBIN7___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN7_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN7_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_LATMAX_LOW (0x0038A080) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_LATMAX_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_LATMAX_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_LATMAX_LOW__LATMAX___POR 0x00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_LATMAX_LOW__LATMAX___M 0x000000FF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_LATMAX_LOW__LATMAX___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_LATMAX_LOW___M 0x000000FF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_LATMAX_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_LOW (0x0038A120) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___POR 0x000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFC00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___S 10 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_LOW___M 0xFFFFFC00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_LOW___S 10 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH (0x0038A124) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000003F +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH___M 0x0000003F +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_LOW (0x0038A128) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___POR 0x000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFC00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___S 10 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_LOW___M 0xFFFFFC00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_LOW___S 10 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH (0x0038A12C) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000003F +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH___M 0x0000003F +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW (0x0038A138) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__CMEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__WREN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__RDEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___M 0x00000010 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___S 4 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__CMEN___M 0x00000008 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__CMEN___S 3 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___M 0x00000004 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___S 2 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__WREN___M 0x00000002 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__WREN___S 1 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__RDEN___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__RDEN___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW___M 0x0000001F +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW (0x0038A200) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW___POR 0x00039006 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW__UNITTYPEID___POR 0x03 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW__UNITCONFID___POR 0x9006 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW__UNITTYPEID___S 16 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW__UNITCONFID___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW___M 0x00FFFFFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_HIGH (0x0038A204) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_HIGH___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_HIGH___POR 0xA8AF23E2 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_HIGH__QNOCID___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_HIGH___M 0xFFFFFFFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_HIGH___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW (0x0038A208) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__SCALEEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__DUMPEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__MODE___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___M 0x00000300 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___S 8 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___S 5 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___M 0x00000010 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___S 4 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__SCALEEN___M 0x00000008 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__SCALEEN___S 3 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__DUMPEN___M 0x00000004 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__DUMPEN___S 2 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__MODE___M 0x00000003 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__MODE___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW___M 0x0000033F +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPGO_LOW (0x0038A210) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPGO_LOW___RWC QCSR_REG_WO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPGO_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPGO_LOW__DUMPGO___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPGO_LOW__DUMPGO___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPGO_LOW__DUMPGO___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPGO_LOW___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPGO_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPTHR_LOW (0x0038A218) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPTHR_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPTHR_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPTHR_LOW__DUMPTHR___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPTHR_LOW__DUMPTHR___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPTHR_LOW__DUMPTHR___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPTHR_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPTHR_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW (0x0038A220) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW___POR 0x01400000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__NOMINALFREQ___POR 0x140 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__OFFSET___POR 0x00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__WIDTH___POR 0x00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__NOMINALFREQ___M 0x0FFF0000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__NOMINALFREQ___S 16 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__OFFSET___M 0x0000FF00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__OFFSET___S 8 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__WIDTH___M 0x000000FF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__WIDTH___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW___M 0x0FFFFFFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_LOW (0x0038A228) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_LOW__LATSUM___POR 0x0000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_LOW__LATSUM___M 0x0FFFFFFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_LOW__LATSUM___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_LOW___M 0x0FFFFFFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_HIGH (0x0038A22C) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_HIGH___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_HIGH___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_HIGH__TRCNT___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_HIGH__TRCNT___M 0x000FFF00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_HIGH__TRCNT___S 8 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_HIGH___M 0x000FFF00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_HIGH___S 8 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN0_LOW (0x0038A240) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN0_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN0_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN0_LOW__HISTBIN0___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN0_LOW__HISTBIN0___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN0_LOW__HISTBIN0___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN0_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN0_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN1_LOW (0x0038A248) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN1_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN1_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN1_LOW__HISTBIN1___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN1_LOW__HISTBIN1___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN1_LOW__HISTBIN1___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN1_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN1_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN2_LOW (0x0038A250) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN2_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN2_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN2_LOW__HISTBIN2___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN2_LOW__HISTBIN2___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN2_LOW__HISTBIN2___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN2_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN2_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN3_LOW (0x0038A258) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN3_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN3_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN3_LOW__HISTBIN3___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN3_LOW__HISTBIN3___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN3_LOW__HISTBIN3___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN3_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN3_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN4_LOW (0x0038A260) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN4_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN4_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN4_LOW__HISTBIN4___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN4_LOW__HISTBIN4___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN4_LOW__HISTBIN4___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN4_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN4_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN5_LOW (0x0038A268) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN5_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN5_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN5_LOW__HISTBIN5___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN5_LOW__HISTBIN5___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN5_LOW__HISTBIN5___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN5_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN5_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN6_LOW (0x0038A270) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN6_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN6_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN6_LOW__HISTBIN6___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN6_LOW__HISTBIN6___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN6_LOW__HISTBIN6___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN6_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN6_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN7_LOW (0x0038A278) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN7_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN7_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN7_LOW__HISTBIN7___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN7_LOW__HISTBIN7___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN7_LOW__HISTBIN7___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN7_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN7_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_LATMAX_LOW (0x0038A280) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_LATMAX_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_LATMAX_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_LATMAX_LOW__LATMAX___POR 0x00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_LATMAX_LOW__LATMAX___M 0x000000FF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_LATMAX_LOW__LATMAX___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_LATMAX_LOW___M 0x000000FF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_LATMAX_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_LOW (0x0038A320) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___POR 0x000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFC00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___S 10 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_LOW___M 0xFFFFFC00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_LOW___S 10 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH (0x0038A324) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000003F +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH___M 0x0000003F +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_LOW (0x0038A328) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___POR 0x000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFC00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___S 10 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_LOW___M 0xFFFFFC00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_LOW___S 10 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH (0x0038A32C) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000003F +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH___M 0x0000003F +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW (0x0038A338) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__CMEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__WREN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__RDEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___M 0x00000010 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___S 4 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__CMEN___M 0x00000008 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__CMEN___S 3 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___M 0x00000004 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___S 2 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__WREN___M 0x00000002 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__WREN___S 1 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__RDEN___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__RDEN___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW___M 0x0000001F +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW (0x0038A400) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW___POR 0x00039006 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW__UNITTYPEID___POR 0x03 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW__UNITCONFID___POR 0x9006 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW__UNITTYPEID___S 16 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW__UNITCONFID___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW___M 0x00FFFFFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_HIGH (0x0038A404) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_HIGH___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_HIGH___POR 0xA8AF23E2 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_HIGH__QNOCID___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_HIGH___M 0xFFFFFFFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_HIGH___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW (0x0038A408) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__SCALEEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__DUMPEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__MODE___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___M 0x00000300 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___S 8 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___S 5 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___M 0x00000010 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___S 4 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__SCALEEN___M 0x00000008 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__SCALEEN___S 3 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__DUMPEN___M 0x00000004 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__DUMPEN___S 2 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__MODE___M 0x00000003 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__MODE___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW___M 0x0000033F +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPGO_LOW (0x0038A410) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPGO_LOW___RWC QCSR_REG_WO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPGO_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPGO_LOW__DUMPGO___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPGO_LOW__DUMPGO___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPGO_LOW__DUMPGO___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPGO_LOW___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPGO_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPTHR_LOW (0x0038A418) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPTHR_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPTHR_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPTHR_LOW__DUMPTHR___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPTHR_LOW__DUMPTHR___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPTHR_LOW__DUMPTHR___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPTHR_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPTHR_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW (0x0038A420) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW___POR 0x01400000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__NOMINALFREQ___POR 0x140 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__OFFSET___POR 0x00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__WIDTH___POR 0x00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__NOMINALFREQ___M 0x0FFF0000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__NOMINALFREQ___S 16 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__OFFSET___M 0x0000FF00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__OFFSET___S 8 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__WIDTH___M 0x000000FF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__WIDTH___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW___M 0x0FFFFFFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_LOW (0x0038A428) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_LOW__LATSUM___POR 0x0000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_LOW__LATSUM___M 0x0FFFFFFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_LOW__LATSUM___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_LOW___M 0x0FFFFFFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_HIGH (0x0038A42C) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_HIGH___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_HIGH___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_HIGH__TRCNT___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_HIGH__TRCNT___M 0x000FFF00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_HIGH__TRCNT___S 8 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_HIGH___M 0x000FFF00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_HIGH___S 8 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN0_LOW (0x0038A440) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN0_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN0_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN0_LOW__HISTBIN0___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN0_LOW__HISTBIN0___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN0_LOW__HISTBIN0___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN0_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN0_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN1_LOW (0x0038A448) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN1_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN1_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN1_LOW__HISTBIN1___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN1_LOW__HISTBIN1___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN1_LOW__HISTBIN1___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN1_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN1_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN2_LOW (0x0038A450) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN2_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN2_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN2_LOW__HISTBIN2___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN2_LOW__HISTBIN2___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN2_LOW__HISTBIN2___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN2_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN2_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN3_LOW (0x0038A458) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN3_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN3_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN3_LOW__HISTBIN3___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN3_LOW__HISTBIN3___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN3_LOW__HISTBIN3___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN3_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN3_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN4_LOW (0x0038A460) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN4_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN4_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN4_LOW__HISTBIN4___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN4_LOW__HISTBIN4___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN4_LOW__HISTBIN4___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN4_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN4_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN5_LOW (0x0038A468) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN5_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN5_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN5_LOW__HISTBIN5___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN5_LOW__HISTBIN5___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN5_LOW__HISTBIN5___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN5_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN5_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN6_LOW (0x0038A470) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN6_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN6_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN6_LOW__HISTBIN6___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN6_LOW__HISTBIN6___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN6_LOW__HISTBIN6___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN6_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN6_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN7_LOW (0x0038A478) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN7_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN7_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN7_LOW__HISTBIN7___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN7_LOW__HISTBIN7___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN7_LOW__HISTBIN7___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN7_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN7_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_LATMAX_LOW (0x0038A480) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_LATMAX_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_LATMAX_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_LATMAX_LOW__LATMAX___POR 0x00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_LATMAX_LOW__LATMAX___M 0x000000FF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_LATMAX_LOW__LATMAX___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_LATMAX_LOW___M 0x000000FF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_LATMAX_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_LOW (0x0038A520) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___POR 0x000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFC00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___S 10 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_LOW___M 0xFFFFFC00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_LOW___S 10 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH (0x0038A524) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000003F +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH___M 0x0000003F +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_LOW (0x0038A528) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___POR 0x000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFC00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___S 10 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_LOW___M 0xFFFFFC00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_LOW___S 10 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH (0x0038A52C) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000003F +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH___M 0x0000003F +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW (0x0038A538) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__CMEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__WREN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__RDEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___M 0x00000010 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___S 4 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__CMEN___M 0x00000008 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__CMEN___S 3 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___M 0x00000004 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___S 2 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__WREN___M 0x00000002 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__WREN___S 1 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__RDEN___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__RDEN___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW___M 0x0000001F +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW (0x0038A600) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW___POR 0x00039006 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW__UNITTYPEID___POR 0x03 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW__UNITCONFID___POR 0x9006 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW__UNITTYPEID___S 16 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW__UNITCONFID___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW___M 0x00FFFFFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_HIGH (0x0038A604) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_HIGH___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_HIGH___POR 0xA8AF23E2 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_HIGH__QNOCID___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_HIGH___M 0xFFFFFFFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_HIGH___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW (0x0038A608) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__SCALEEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__DUMPEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__MODE___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___M 0x00000300 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___S 8 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___S 5 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___M 0x00000010 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___S 4 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__SCALEEN___M 0x00000008 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__SCALEEN___S 3 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__DUMPEN___M 0x00000004 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__DUMPEN___S 2 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__MODE___M 0x00000003 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__MODE___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW___M 0x0000033F +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPGO_LOW (0x0038A610) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPGO_LOW___RWC QCSR_REG_WO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPGO_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPGO_LOW__DUMPGO___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPGO_LOW__DUMPGO___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPGO_LOW__DUMPGO___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPGO_LOW___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPGO_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPTHR_LOW (0x0038A618) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPTHR_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPTHR_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPTHR_LOW__DUMPTHR___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPTHR_LOW__DUMPTHR___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPTHR_LOW__DUMPTHR___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPTHR_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPTHR_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW (0x0038A620) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW___POR 0x01400000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__NOMINALFREQ___POR 0x140 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__OFFSET___POR 0x00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__WIDTH___POR 0x00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__NOMINALFREQ___M 0x0FFF0000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__NOMINALFREQ___S 16 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__OFFSET___M 0x0000FF00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__OFFSET___S 8 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__WIDTH___M 0x000000FF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__WIDTH___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW___M 0x0FFFFFFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_LOW (0x0038A628) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_LOW__LATSUM___POR 0x0000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_LOW__LATSUM___M 0x0FFFFFFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_LOW__LATSUM___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_LOW___M 0x0FFFFFFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_HIGH (0x0038A62C) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_HIGH___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_HIGH___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_HIGH__TRCNT___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_HIGH__TRCNT___M 0x000FFF00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_HIGH__TRCNT___S 8 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_HIGH___M 0x000FFF00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_HIGH___S 8 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN0_LOW (0x0038A640) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN0_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN0_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN0_LOW__HISTBIN0___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN0_LOW__HISTBIN0___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN0_LOW__HISTBIN0___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN0_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN0_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN1_LOW (0x0038A648) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN1_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN1_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN1_LOW__HISTBIN1___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN1_LOW__HISTBIN1___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN1_LOW__HISTBIN1___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN1_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN1_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN2_LOW (0x0038A650) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN2_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN2_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN2_LOW__HISTBIN2___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN2_LOW__HISTBIN2___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN2_LOW__HISTBIN2___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN2_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN2_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN3_LOW (0x0038A658) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN3_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN3_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN3_LOW__HISTBIN3___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN3_LOW__HISTBIN3___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN3_LOW__HISTBIN3___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN3_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN3_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN4_LOW (0x0038A660) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN4_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN4_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN4_LOW__HISTBIN4___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN4_LOW__HISTBIN4___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN4_LOW__HISTBIN4___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN4_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN4_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN5_LOW (0x0038A668) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN5_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN5_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN5_LOW__HISTBIN5___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN5_LOW__HISTBIN5___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN5_LOW__HISTBIN5___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN5_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN5_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN6_LOW (0x0038A670) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN6_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN6_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN6_LOW__HISTBIN6___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN6_LOW__HISTBIN6___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN6_LOW__HISTBIN6___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN6_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN6_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN7_LOW (0x0038A678) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN7_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN7_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN7_LOW__HISTBIN7___POR 0x000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN7_LOW__HISTBIN7___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN7_LOW__HISTBIN7___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN7_LOW___M 0x00000FFF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN7_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_LATMAX_LOW (0x0038A680) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_LATMAX_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_LATMAX_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_LATMAX_LOW__LATMAX___POR 0x00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_LATMAX_LOW__LATMAX___M 0x000000FF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_LATMAX_LOW__LATMAX___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_LATMAX_LOW___M 0x000000FF +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_LATMAX_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_LOW (0x0038A720) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___POR 0x000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFC00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___S 10 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_LOW___M 0xFFFFFC00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_LOW___S 10 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH (0x0038A724) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000003F +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH___M 0x0000003F +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_LOW (0x0038A728) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___POR 0x000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFC00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___S 10 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_LOW___M 0xFFFFFC00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_LOW___S 10 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH (0x0038A72C) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000003F +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH___M 0x0000003F +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH___S 0 + +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW (0x0038A738) +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__CMEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__WREN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__RDEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___M 0x00000010 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___S 4 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__CMEN___M 0x00000008 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__CMEN___S 3 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___M 0x00000004 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___S 2 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__WREN___M 0x00000002 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__WREN___S 1 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__RDEN___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__RDEN___S 0 +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW___M 0x0000001F +#define PHYA_NOC_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_STP_SWID_LOW (0x0038A800) +#define PHYA_NOC_PHYA_NOC_STP_SWID_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_STP_SWID_LOW___POR 0x000CE93B +#define PHYA_NOC_PHYA_NOC_STP_SWID_LOW__UNITTYPEID___POR 0x0C +#define PHYA_NOC_PHYA_NOC_STP_SWID_LOW__UNITCONFID___POR 0xE93B +#define PHYA_NOC_PHYA_NOC_STP_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define PHYA_NOC_PHYA_NOC_STP_SWID_LOW__UNITTYPEID___S 16 +#define PHYA_NOC_PHYA_NOC_STP_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define PHYA_NOC_PHYA_NOC_STP_SWID_LOW__UNITCONFID___S 0 +#define PHYA_NOC_PHYA_NOC_STP_SWID_LOW___M 0x00FFFFFF +#define PHYA_NOC_PHYA_NOC_STP_SWID_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_STP_SWID_HIGH (0x0038A804) +#define PHYA_NOC_PHYA_NOC_STP_SWID_HIGH___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_STP_SWID_HIGH___POR 0xA8AF23E2 +#define PHYA_NOC_PHYA_NOC_STP_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define PHYA_NOC_PHYA_NOC_STP_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define PHYA_NOC_PHYA_NOC_STP_SWID_HIGH__QNOCID___S 0 +#define PHYA_NOC_PHYA_NOC_STP_SWID_HIGH___M 0xFFFFFFFF +#define PHYA_NOC_PHYA_NOC_STP_SWID_HIGH___S 0 + +#define PHYA_NOC_PHYA_NOC_STP_ATBEN_LOW (0x0038A808) +#define PHYA_NOC_PHYA_NOC_STP_ATBEN_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_STP_ATBEN_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_STP_ATBEN_LOW__ATBEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_STP_ATBEN_LOW__ATBEN___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_STP_ATBEN_LOW__ATBEN___S 0 +#define PHYA_NOC_PHYA_NOC_STP_ATBEN_LOW___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_STP_ATBEN_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_STP_ATBID_LOW (0x0038A810) +#define PHYA_NOC_PHYA_NOC_STP_ATBID_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_STP_ATBID_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_STP_ATBID_LOW__ATBID___POR 0x00 +#define PHYA_NOC_PHYA_NOC_STP_ATBID_LOW__ATBID___M 0x0000007F +#define PHYA_NOC_PHYA_NOC_STP_ATBID_LOW__ATBID___S 0 +#define PHYA_NOC_PHYA_NOC_STP_ATBID_LOW___M 0x0000007F +#define PHYA_NOC_PHYA_NOC_STP_ATBID_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_STP_SYNCOUTPERIOD_LOW (0x0038A818) +#define PHYA_NOC_PHYA_NOC_STP_SYNCOUTPERIOD_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_STP_SYNCOUTPERIOD_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_STP_SYNCOUTPERIOD_LOW__SYNCOUTPERIOD___POR 0x000 +#define PHYA_NOC_PHYA_NOC_STP_SYNCOUTPERIOD_LOW__SYNCOUTPERIOD___M 0x000003FF +#define PHYA_NOC_PHYA_NOC_STP_SYNCOUTPERIOD_LOW__SYNCOUTPERIOD___S 0 +#define PHYA_NOC_PHYA_NOC_STP_SYNCOUTPERIOD_LOW___M 0x000003FF +#define PHYA_NOC_PHYA_NOC_STP_SYNCOUTPERIOD_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_ERL_SWID_LOW (0x0038A900) +#define PHYA_NOC_PHYA_NOC_ERL_SWID_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_ERL_SWID_LOW___POR 0x0001E93B +#define PHYA_NOC_PHYA_NOC_ERL_SWID_LOW__UNITTYPEID___POR 0x01 +#define PHYA_NOC_PHYA_NOC_ERL_SWID_LOW__UNITCONFID___POR 0xE93B +#define PHYA_NOC_PHYA_NOC_ERL_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define PHYA_NOC_PHYA_NOC_ERL_SWID_LOW__UNITTYPEID___S 16 +#define PHYA_NOC_PHYA_NOC_ERL_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define PHYA_NOC_PHYA_NOC_ERL_SWID_LOW__UNITCONFID___S 0 +#define PHYA_NOC_PHYA_NOC_ERL_SWID_LOW___M 0x00FFFFFF +#define PHYA_NOC_PHYA_NOC_ERL_SWID_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_ERL_SWID_HIGH (0x0038A904) +#define PHYA_NOC_PHYA_NOC_ERL_SWID_HIGH___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_ERL_SWID_HIGH___POR 0xA8AF23E2 +#define PHYA_NOC_PHYA_NOC_ERL_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define PHYA_NOC_PHYA_NOC_ERL_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define PHYA_NOC_PHYA_NOC_ERL_SWID_HIGH__QNOCID___S 0 +#define PHYA_NOC_PHYA_NOC_ERL_SWID_HIGH___M 0xFFFFFFFF +#define PHYA_NOC_PHYA_NOC_ERL_SWID_HIGH___S 0 + +#define PHYA_NOC_PHYA_NOC_ERL_MAINCTL_LOW (0x0038A908) +#define PHYA_NOC_PHYA_NOC_ERL_MAINCTL_LOW___RWC QCSR_REG_RW +#define PHYA_NOC_PHYA_NOC_ERL_MAINCTL_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_ERL_MAINCTL_LOW__STALLEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_ERL_MAINCTL_LOW__FAULTEN___POR 0x0 +#define PHYA_NOC_PHYA_NOC_ERL_MAINCTL_LOW__STALLEN___M 0x00000002 +#define PHYA_NOC_PHYA_NOC_ERL_MAINCTL_LOW__STALLEN___S 1 +#define PHYA_NOC_PHYA_NOC_ERL_MAINCTL_LOW__FAULTEN___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_ERL_MAINCTL_LOW__FAULTEN___S 0 +#define PHYA_NOC_PHYA_NOC_ERL_MAINCTL_LOW___M 0x00000003 +#define PHYA_NOC_PHYA_NOC_ERL_MAINCTL_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_ERL_ERRVLD_LOW (0x0038A910) +#define PHYA_NOC_PHYA_NOC_ERL_ERRVLD_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_ERL_ERRVLD_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_ERL_ERRVLD_LOW__ERRVLD___POR 0x0 +#define PHYA_NOC_PHYA_NOC_ERL_ERRVLD_LOW__ERRVLD___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_ERL_ERRVLD_LOW__ERRVLD___S 0 +#define PHYA_NOC_PHYA_NOC_ERL_ERRVLD_LOW___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_ERL_ERRVLD_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_ERL_ERRCLR_LOW (0x0038A918) +#define PHYA_NOC_PHYA_NOC_ERL_ERRCLR_LOW___RWC QCSR_REG_WO +#define PHYA_NOC_PHYA_NOC_ERL_ERRCLR_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_ERL_ERRCLR_LOW__ERRCLR___POR 0x0 +#define PHYA_NOC_PHYA_NOC_ERL_ERRCLR_LOW__ERRCLR___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_ERL_ERRCLR_LOW__ERRCLR___S 0 +#define PHYA_NOC_PHYA_NOC_ERL_ERRCLR_LOW___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_ERL_ERRCLR_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW (0x0038A920) +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__ATOPC___POR 0x0 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__ADDRSPACE___POR 0x00 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__TRTYPE___POR 0x0 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__ERRCODE___POR 0x0 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__OPC___POR 0x0 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__NONSECURE___POR 0x0 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__WORDERROR___POR 0x0 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__LOGINFOVLD___POR 0x0 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__ATOPC___M 0x0F000000 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__ATOPC___S 24 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__ADDRSPACE___M 0x003F0000 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__ADDRSPACE___S 16 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__TRTYPE___M 0x00007000 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__TRTYPE___S 12 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__ERRCODE___M 0x00000700 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__ERRCODE___S 8 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__OPC___M 0x00000070 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__OPC___S 4 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__NONSECURE___M 0x00000004 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__NONSECURE___S 2 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__WORDERROR___M 0x00000002 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__WORDERROR___S 1 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__LOGINFOVLD___M 0x00000001 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW__LOGINFOVLD___S 0 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW___M 0x0F3F7777 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_HIGH (0x0038A924) +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_HIGH___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_HIGH___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_HIGH__REDIRECT___POR 0x00 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_HIGH__LEN1___POR 0x000 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_HIGH__REDIRECT___M 0x00FF0000 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_HIGH__REDIRECT___S 16 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_HIGH__LEN1___M 0x000003FF +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_HIGH__LEN1___S 0 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_HIGH___M 0x00FF03FF +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG0_HIGH___S 0 + +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG1_LOW (0x0038A928) +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG1_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG1_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG1_LOW__PATH___POR 0x0000 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG1_LOW__PATH___M 0x0000FFFF +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG1_LOW__PATH___S 0 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG1_LOW___M 0x0000FFFF +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG1_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG1_HIGH (0x0038A92C) +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG1_HIGH___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG1_HIGH___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG1_HIGH__EXTID___POR 0x00000 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG1_HIGH__EXTID___M 0x0003FFFF +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG1_HIGH__EXTID___S 0 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG1_HIGH___M 0x0003FFFF +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG1_HIGH___S 0 + +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG2_LOW (0x0038A930) +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG2_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG2_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG2_LOW__ERRLOG2_LSB___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG2_LOW__ERRLOG2_LSB___M 0xFFFFFFFF +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG2_LOW__ERRLOG2_LSB___S 0 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG2_LOW___M 0xFFFFFFFF +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG2_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG2_HIGH (0x0038A934) +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG2_HIGH___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG2_HIGH___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___POR 0x00000 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___M 0x0001FFFF +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___S 0 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG2_HIGH___M 0x0001FFFF +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG2_HIGH___S 0 + +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG3_LOW (0x0038A938) +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG3_LOW___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG3_LOW___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG3_LOW__ERRLOG3_LSB___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG3_LOW__ERRLOG3_LSB___M 0xFFFFFFFF +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG3_LOW__ERRLOG3_LSB___S 0 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG3_LOW___M 0xFFFFFFFF +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG3_LOW___S 0 + +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG3_HIGH (0x0038A93C) +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG3_HIGH___RWC QCSR_REG_RO +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG3_HIGH___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___POR 0x00000000 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___M 0xFFFFFFFF +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___S 0 +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG3_HIGH___M 0xFFFFFFFF +#define PHYA_NOC_PHYA_NOC_ERL_ERRLOG3_HIGH___S 0 + +#define PHYA_TXFD_ECO_CONTROL_L (0x00390000) +#define PHYA_TXFD_ECO_CONTROL_L___RWC QCSR_REG_RW +#define PHYA_TXFD_ECO_CONTROL_L___POR 0x00000000 +#define PHYA_TXFD_ECO_CONTROL_L__ECO_CTRL___POR 0x00000000 +#define PHYA_TXFD_ECO_CONTROL_L__ECO_CTRL___M 0xFFFFFFFF +#define PHYA_TXFD_ECO_CONTROL_L__ECO_CTRL___S 0 +#define PHYA_TXFD_ECO_CONTROL_L___M 0xFFFFFFFF +#define PHYA_TXFD_ECO_CONTROL_L___S 0 + +#define PHYA_TXFD_ECO_CONTROL_U (0x00390004) +#define PHYA_TXFD_ECO_CONTROL_U___RWC QCSR_REG_RW +#define PHYA_TXFD_ECO_CONTROL_U___POR 0x00000000 +#define PHYA_TXFD_ECO_CONTROL_U__ECO_CFG___POR 0x00000000 +#define PHYA_TXFD_ECO_CONTROL_U__ECO_CFG___M 0xFFFFFFFF +#define PHYA_TXFD_ECO_CONTROL_U__ECO_CFG___S 0 +#define PHYA_TXFD_ECO_CONTROL_U___M 0xFFFFFFFF +#define PHYA_TXFD_ECO_CONTROL_U___S 0 + +#define PHYA_TXFD_ECO_STATUS_L (0x00390008) +#define PHYA_TXFD_ECO_STATUS_L___RWC QCSR_REG_RO +#define PHYA_TXFD_ECO_STATUS_L___POR 0x00000000 +#define PHYA_TXFD_ECO_STATUS_L__ECO_STAT___POR 0x00000000 +#define PHYA_TXFD_ECO_STATUS_L__ECO_STAT___M 0xFFFFFFFF +#define PHYA_TXFD_ECO_STATUS_L__ECO_STAT___S 0 +#define PHYA_TXFD_ECO_STATUS_L___M 0xFFFFFFFF +#define PHYA_TXFD_ECO_STATUS_L___S 0 + +#define PHYA_TXFD_CONFIG_CONFIG_L (0x00390010) +#define PHYA_TXFD_CONFIG_CONFIG_L___RWC QCSR_REG_RW +#define PHYA_TXFD_CONFIG_CONFIG_L___POR 0x00000000 +#define PHYA_TXFD_CONFIG_CONFIG_L__AXI_TIMEOUT_ENABLE___POR 0x0 +#define PHYA_TXFD_CONFIG_CONFIG_L__AXI_TIMEOUT_ENABLE___M 0x00000001 +#define PHYA_TXFD_CONFIG_CONFIG_L__AXI_TIMEOUT_ENABLE___S 0 +#define PHYA_TXFD_CONFIG_CONFIG_L___M 0x00000001 +#define PHYA_TXFD_CONFIG_CONFIG_L___S 0 + +#define PHYA_TXFD_EVENT_STATUS_L (0x00390018) +#define PHYA_TXFD_EVENT_STATUS_L___RWC QCSR_REG_RW +#define PHYA_TXFD_EVENT_STATUS_L___POR 0x00000000 +#define PHYA_TXFD_EVENT_STATUS_L__PREFETCH_DONE_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_L__PREFETCH_CV_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_L__RU_ALLOC_CORR_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_L__PARTIAL_PREFETCH_DONE_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_L__TXBF_HW_ACC_DONE_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_L__PRECODING_DONE_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_L__CBF_TCCBF_DONE_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_L__LDPC_PARAM_CORR_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_L__USER_PARAM_CORR_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_L__DDR_DMA1_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_L__DDR_DMA0_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_L__ALL_MIMO_DECODE_DONE_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_L__DDR_TRANSFER_DONE_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_L__CVMEM_TRANSFER_DONE_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_L__EXPECT_CBF_PARAMS_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_L__HE_SIGB_PARAMS_READY_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_L__PHY_ABORT_ACK_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_L__TXBF_PARAMS_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_L__PACKET_DONE_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_L__TLV_FIFO_RD_TIMEOUT_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_L__HE_SIGA_SYM_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_L__BF_PORTION_START_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_L__FIRST_DATA_SYM_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_L__MAC_ABORT_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_L__RU_PARAMS_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_L__FW_SYM_START_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_L__ALL_SYM_START_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_L__PKT_START_SLOW_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_L__PKT_START_FAST_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_L__PRE_PKT_START_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_L__ECO_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_L__ERROR_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_L__PREFETCH_DONE_EVENT___M 0x80000000 +#define PHYA_TXFD_EVENT_STATUS_L__PREFETCH_DONE_EVENT___S 31 +#define PHYA_TXFD_EVENT_STATUS_L__PREFETCH_CV_EVENT___M 0x40000000 +#define PHYA_TXFD_EVENT_STATUS_L__PREFETCH_CV_EVENT___S 30 +#define PHYA_TXFD_EVENT_STATUS_L__RU_ALLOC_CORR_EVENT___M 0x20000000 +#define PHYA_TXFD_EVENT_STATUS_L__RU_ALLOC_CORR_EVENT___S 29 +#define PHYA_TXFD_EVENT_STATUS_L__PARTIAL_PREFETCH_DONE_EVENT___M 0x10000000 +#define PHYA_TXFD_EVENT_STATUS_L__PARTIAL_PREFETCH_DONE_EVENT___S 28 +#define PHYA_TXFD_EVENT_STATUS_L__TXBF_HW_ACC_DONE_EVENT___M 0x08000000 +#define PHYA_TXFD_EVENT_STATUS_L__TXBF_HW_ACC_DONE_EVENT___S 27 +#define PHYA_TXFD_EVENT_STATUS_L__PRECODING_DONE_EVENT___M 0x04000000 +#define PHYA_TXFD_EVENT_STATUS_L__PRECODING_DONE_EVENT___S 26 +#define PHYA_TXFD_EVENT_STATUS_L__CBF_TCCBF_DONE_EVENT___M 0x02000000 +#define PHYA_TXFD_EVENT_STATUS_L__CBF_TCCBF_DONE_EVENT___S 25 +#define PHYA_TXFD_EVENT_STATUS_L__LDPC_PARAM_CORR_EVENT___M 0x01000000 +#define PHYA_TXFD_EVENT_STATUS_L__LDPC_PARAM_CORR_EVENT___S 24 +#define PHYA_TXFD_EVENT_STATUS_L__USER_PARAM_CORR_EVENT___M 0x00800000 +#define PHYA_TXFD_EVENT_STATUS_L__USER_PARAM_CORR_EVENT___S 23 +#define PHYA_TXFD_EVENT_STATUS_L__DDR_DMA1_EVENT___M 0x00400000 +#define PHYA_TXFD_EVENT_STATUS_L__DDR_DMA1_EVENT___S 22 +#define PHYA_TXFD_EVENT_STATUS_L__DDR_DMA0_EVENT___M 0x00200000 +#define PHYA_TXFD_EVENT_STATUS_L__DDR_DMA0_EVENT___S 21 +#define PHYA_TXFD_EVENT_STATUS_L__ALL_MIMO_DECODE_DONE_EVENT___M 0x00100000 +#define PHYA_TXFD_EVENT_STATUS_L__ALL_MIMO_DECODE_DONE_EVENT___S 20 +#define PHYA_TXFD_EVENT_STATUS_L__DDR_TRANSFER_DONE_EVENT___M 0x00080000 +#define PHYA_TXFD_EVENT_STATUS_L__DDR_TRANSFER_DONE_EVENT___S 19 +#define PHYA_TXFD_EVENT_STATUS_L__CVMEM_TRANSFER_DONE_EVENT___M 0x00040000 +#define PHYA_TXFD_EVENT_STATUS_L__CVMEM_TRANSFER_DONE_EVENT___S 18 +#define PHYA_TXFD_EVENT_STATUS_L__EXPECT_CBF_PARAMS_EVENT___M 0x00020000 +#define PHYA_TXFD_EVENT_STATUS_L__EXPECT_CBF_PARAMS_EVENT___S 17 +#define PHYA_TXFD_EVENT_STATUS_L__HE_SIGB_PARAMS_READY_EVENT___M 0x00010000 +#define PHYA_TXFD_EVENT_STATUS_L__HE_SIGB_PARAMS_READY_EVENT___S 16 +#define PHYA_TXFD_EVENT_STATUS_L__PHY_ABORT_ACK_EVENT___M 0x00008000 +#define PHYA_TXFD_EVENT_STATUS_L__PHY_ABORT_ACK_EVENT___S 15 +#define PHYA_TXFD_EVENT_STATUS_L__TXBF_PARAMS_EVENT___M 0x00004000 +#define PHYA_TXFD_EVENT_STATUS_L__TXBF_PARAMS_EVENT___S 14 +#define PHYA_TXFD_EVENT_STATUS_L__PACKET_DONE_EVENT___M 0x00002000 +#define PHYA_TXFD_EVENT_STATUS_L__PACKET_DONE_EVENT___S 13 +#define PHYA_TXFD_EVENT_STATUS_L__TLV_FIFO_RD_TIMEOUT_EVENT___M 0x00001000 +#define PHYA_TXFD_EVENT_STATUS_L__TLV_FIFO_RD_TIMEOUT_EVENT___S 12 +#define PHYA_TXFD_EVENT_STATUS_L__HE_SIGA_SYM_EVENT___M 0x00000800 +#define PHYA_TXFD_EVENT_STATUS_L__HE_SIGA_SYM_EVENT___S 11 +#define PHYA_TXFD_EVENT_STATUS_L__BF_PORTION_START_EVENT___M 0x00000400 +#define PHYA_TXFD_EVENT_STATUS_L__BF_PORTION_START_EVENT___S 10 +#define PHYA_TXFD_EVENT_STATUS_L__FIRST_DATA_SYM_EVENT___M 0x00000200 +#define PHYA_TXFD_EVENT_STATUS_L__FIRST_DATA_SYM_EVENT___S 9 +#define PHYA_TXFD_EVENT_STATUS_L__MAC_ABORT_EVENT___M 0x00000100 +#define PHYA_TXFD_EVENT_STATUS_L__MAC_ABORT_EVENT___S 8 +#define PHYA_TXFD_EVENT_STATUS_L__RU_PARAMS_EVENT___M 0x00000080 +#define PHYA_TXFD_EVENT_STATUS_L__RU_PARAMS_EVENT___S 7 +#define PHYA_TXFD_EVENT_STATUS_L__FW_SYM_START_EVENT___M 0x00000040 +#define PHYA_TXFD_EVENT_STATUS_L__FW_SYM_START_EVENT___S 6 +#define PHYA_TXFD_EVENT_STATUS_L__ALL_SYM_START_EVENT___M 0x00000020 +#define PHYA_TXFD_EVENT_STATUS_L__ALL_SYM_START_EVENT___S 5 +#define PHYA_TXFD_EVENT_STATUS_L__PKT_START_SLOW_EVENT___M 0x00000010 +#define PHYA_TXFD_EVENT_STATUS_L__PKT_START_SLOW_EVENT___S 4 +#define PHYA_TXFD_EVENT_STATUS_L__PKT_START_FAST_EVENT___M 0x00000008 +#define PHYA_TXFD_EVENT_STATUS_L__PKT_START_FAST_EVENT___S 3 +#define PHYA_TXFD_EVENT_STATUS_L__PRE_PKT_START_EVENT___M 0x00000004 +#define PHYA_TXFD_EVENT_STATUS_L__PRE_PKT_START_EVENT___S 2 +#define PHYA_TXFD_EVENT_STATUS_L__ECO_EVENT___M 0x00000002 +#define PHYA_TXFD_EVENT_STATUS_L__ECO_EVENT___S 1 +#define PHYA_TXFD_EVENT_STATUS_L__ERROR_EVENT___M 0x00000001 +#define PHYA_TXFD_EVENT_STATUS_L__ERROR_EVENT___S 0 +#define PHYA_TXFD_EVENT_STATUS_L___M 0xFFFFFFFF +#define PHYA_TXFD_EVENT_STATUS_L___S 0 + +#define PHYA_TXFD_EVENT_STATUS_U (0x0039001C) +#define PHYA_TXFD_EVENT_STATUS_U___RWC QCSR_REG_RW +#define PHYA_TXFD_EVENT_STATUS_U___POR 0x00000000 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_15_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_14_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_13_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_12_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_11_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_10_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_9_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_8_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_7_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_6_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_5_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_4_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_3_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_2_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_1_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_0_EVENT___POR 0x0 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_15_EVENT___M 0x00008000 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_15_EVENT___S 15 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_14_EVENT___M 0x00004000 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_14_EVENT___S 14 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_13_EVENT___M 0x00002000 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_13_EVENT___S 13 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_12_EVENT___M 0x00001000 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_12_EVENT___S 12 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_11_EVENT___M 0x00000800 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_11_EVENT___S 11 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_10_EVENT___M 0x00000400 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_10_EVENT___S 10 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_9_EVENT___M 0x00000200 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_9_EVENT___S 9 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_8_EVENT___M 0x00000100 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_8_EVENT___S 8 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_7_EVENT___M 0x00000080 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_7_EVENT___S 7 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_6_EVENT___M 0x00000040 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_6_EVENT___S 6 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_5_EVENT___M 0x00000020 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_5_EVENT___S 5 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_4_EVENT___M 0x00000010 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_4_EVENT___S 4 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_3_EVENT___M 0x00000008 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_3_EVENT___S 3 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_2_EVENT___M 0x00000004 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_2_EVENT___S 2 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_1_EVENT___M 0x00000002 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_1_EVENT___S 1 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_0_EVENT___M 0x00000001 +#define PHYA_TXFD_EVENT_STATUS_U__TLV_0_EVENT___S 0 +#define PHYA_TXFD_EVENT_STATUS_U___M 0x0000FFFF +#define PHYA_TXFD_EVENT_STATUS_U___S 0 + +#define PHYA_TXFD_EVENT_MASK_L (0x00390020) +#define PHYA_TXFD_EVENT_MASK_L___RWC QCSR_REG_RW +#define PHYA_TXFD_EVENT_MASK_L___POR 0xFFFFFFFF +#define PHYA_TXFD_EVENT_MASK_L__PREFETCH_DONE_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_L__PREFETCH_CV_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_L__RU_ALLOC_CORR_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_L__PARTIAL_PREFETCH_DONE_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_L__TXBF_HW_ACC_DONE_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_L__PRECODING_DONE_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_L__CBF_TCCBF_DONE_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_L__LDPC_PARAM_CORR_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_L__USER_PARAM_CORR_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_L__DDR_DMA1_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_L__DDR_DMA0_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_L__ALL_MIMO_DECODE_DONE_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_L__DDR_TRANSFER_DONE_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_L__CVMEM_TRANSFER_DONE_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_L__EXPECT_CBF_PARAMS_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_L__HE_SIGB_PARAMS_READY_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_L__PHY_ABORT_ACK_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_L__TXBF_PARAMS_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_L__PACKET_DONE_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_L__TLV_FIFO_RD_TIMEOUT_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_L__HE_SIGA_SYM_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_L__BF_PORTION_START_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_L__FIRST_DATA_SYM_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_L__MAC_ABORT_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_L__RU_PARAMS_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_L__FW_SYM_START_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_L__ALL_SYM_START_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_L__PKT_START_SLOW_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_L__PKT_START_FAST_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_L__PRE_PKT_START_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_L__ECO_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_L__ERROR_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_L__PREFETCH_DONE_EVENT_MASK___M 0x80000000 +#define PHYA_TXFD_EVENT_MASK_L__PREFETCH_DONE_EVENT_MASK___S 31 +#define PHYA_TXFD_EVENT_MASK_L__PREFETCH_CV_EVENT_MASK___M 0x40000000 +#define PHYA_TXFD_EVENT_MASK_L__PREFETCH_CV_EVENT_MASK___S 30 +#define PHYA_TXFD_EVENT_MASK_L__RU_ALLOC_CORR_EVENT_MASK___M 0x20000000 +#define PHYA_TXFD_EVENT_MASK_L__RU_ALLOC_CORR_EVENT_MASK___S 29 +#define PHYA_TXFD_EVENT_MASK_L__PARTIAL_PREFETCH_DONE_EVENT_MASK___M 0x10000000 +#define PHYA_TXFD_EVENT_MASK_L__PARTIAL_PREFETCH_DONE_EVENT_MASK___S 28 +#define PHYA_TXFD_EVENT_MASK_L__TXBF_HW_ACC_DONE_EVENT_MASK___M 0x08000000 +#define PHYA_TXFD_EVENT_MASK_L__TXBF_HW_ACC_DONE_EVENT_MASK___S 27 +#define PHYA_TXFD_EVENT_MASK_L__PRECODING_DONE_EVENT_MASK___M 0x04000000 +#define PHYA_TXFD_EVENT_MASK_L__PRECODING_DONE_EVENT_MASK___S 26 +#define PHYA_TXFD_EVENT_MASK_L__CBF_TCCBF_DONE_EVENT_MASK___M 0x02000000 +#define PHYA_TXFD_EVENT_MASK_L__CBF_TCCBF_DONE_EVENT_MASK___S 25 +#define PHYA_TXFD_EVENT_MASK_L__LDPC_PARAM_CORR_EVENT_MASK___M 0x01000000 +#define PHYA_TXFD_EVENT_MASK_L__LDPC_PARAM_CORR_EVENT_MASK___S 24 +#define PHYA_TXFD_EVENT_MASK_L__USER_PARAM_CORR_EVENT_MASK___M 0x00800000 +#define PHYA_TXFD_EVENT_MASK_L__USER_PARAM_CORR_EVENT_MASK___S 23 +#define PHYA_TXFD_EVENT_MASK_L__DDR_DMA1_EVENT_MASK___M 0x00400000 +#define PHYA_TXFD_EVENT_MASK_L__DDR_DMA1_EVENT_MASK___S 22 +#define PHYA_TXFD_EVENT_MASK_L__DDR_DMA0_EVENT_MASK___M 0x00200000 +#define PHYA_TXFD_EVENT_MASK_L__DDR_DMA0_EVENT_MASK___S 21 +#define PHYA_TXFD_EVENT_MASK_L__ALL_MIMO_DECODE_DONE_EVENT_MASK___M 0x00100000 +#define PHYA_TXFD_EVENT_MASK_L__ALL_MIMO_DECODE_DONE_EVENT_MASK___S 20 +#define PHYA_TXFD_EVENT_MASK_L__DDR_TRANSFER_DONE_EVENT_MASK___M 0x00080000 +#define PHYA_TXFD_EVENT_MASK_L__DDR_TRANSFER_DONE_EVENT_MASK___S 19 +#define PHYA_TXFD_EVENT_MASK_L__CVMEM_TRANSFER_DONE_EVENT_MASK___M 0x00040000 +#define PHYA_TXFD_EVENT_MASK_L__CVMEM_TRANSFER_DONE_EVENT_MASK___S 18 +#define PHYA_TXFD_EVENT_MASK_L__EXPECT_CBF_PARAMS_EVENT_MASK___M 0x00020000 +#define PHYA_TXFD_EVENT_MASK_L__EXPECT_CBF_PARAMS_EVENT_MASK___S 17 +#define PHYA_TXFD_EVENT_MASK_L__HE_SIGB_PARAMS_READY_EVENT_MASK___M 0x00010000 +#define PHYA_TXFD_EVENT_MASK_L__HE_SIGB_PARAMS_READY_EVENT_MASK___S 16 +#define PHYA_TXFD_EVENT_MASK_L__PHY_ABORT_ACK_EVENT_MASK___M 0x00008000 +#define PHYA_TXFD_EVENT_MASK_L__PHY_ABORT_ACK_EVENT_MASK___S 15 +#define PHYA_TXFD_EVENT_MASK_L__TXBF_PARAMS_EVENT_MASK___M 0x00004000 +#define PHYA_TXFD_EVENT_MASK_L__TXBF_PARAMS_EVENT_MASK___S 14 +#define PHYA_TXFD_EVENT_MASK_L__PACKET_DONE_EVENT_MASK___M 0x00002000 +#define PHYA_TXFD_EVENT_MASK_L__PACKET_DONE_EVENT_MASK___S 13 +#define PHYA_TXFD_EVENT_MASK_L__TLV_FIFO_RD_TIMEOUT_EVENT_MASK___M 0x00001000 +#define PHYA_TXFD_EVENT_MASK_L__TLV_FIFO_RD_TIMEOUT_EVENT_MASK___S 12 +#define PHYA_TXFD_EVENT_MASK_L__HE_SIGA_SYM_EVENT_MASK___M 0x00000800 +#define PHYA_TXFD_EVENT_MASK_L__HE_SIGA_SYM_EVENT_MASK___S 11 +#define PHYA_TXFD_EVENT_MASK_L__BF_PORTION_START_EVENT_MASK___M 0x00000400 +#define PHYA_TXFD_EVENT_MASK_L__BF_PORTION_START_EVENT_MASK___S 10 +#define PHYA_TXFD_EVENT_MASK_L__FIRST_DATA_SYM_EVENT_MASK___M 0x00000200 +#define PHYA_TXFD_EVENT_MASK_L__FIRST_DATA_SYM_EVENT_MASK___S 9 +#define PHYA_TXFD_EVENT_MASK_L__MAC_ABORT_EVENT_MASK___M 0x00000100 +#define PHYA_TXFD_EVENT_MASK_L__MAC_ABORT_EVENT_MASK___S 8 +#define PHYA_TXFD_EVENT_MASK_L__RU_PARAMS_EVENT_MASK___M 0x00000080 +#define PHYA_TXFD_EVENT_MASK_L__RU_PARAMS_EVENT_MASK___S 7 +#define PHYA_TXFD_EVENT_MASK_L__FW_SYM_START_EVENT_MASK___M 0x00000040 +#define PHYA_TXFD_EVENT_MASK_L__FW_SYM_START_EVENT_MASK___S 6 +#define PHYA_TXFD_EVENT_MASK_L__ALL_SYM_START_EVENT_MASK___M 0x00000020 +#define PHYA_TXFD_EVENT_MASK_L__ALL_SYM_START_EVENT_MASK___S 5 +#define PHYA_TXFD_EVENT_MASK_L__PKT_START_SLOW_EVENT_MASK___M 0x00000010 +#define PHYA_TXFD_EVENT_MASK_L__PKT_START_SLOW_EVENT_MASK___S 4 +#define PHYA_TXFD_EVENT_MASK_L__PKT_START_FAST_EVENT_MASK___M 0x00000008 +#define PHYA_TXFD_EVENT_MASK_L__PKT_START_FAST_EVENT_MASK___S 3 +#define PHYA_TXFD_EVENT_MASK_L__PRE_PKT_START_EVENT_MASK___M 0x00000004 +#define PHYA_TXFD_EVENT_MASK_L__PRE_PKT_START_EVENT_MASK___S 2 +#define PHYA_TXFD_EVENT_MASK_L__ECO_EVENT_MASK___M 0x00000002 +#define PHYA_TXFD_EVENT_MASK_L__ECO_EVENT_MASK___S 1 +#define PHYA_TXFD_EVENT_MASK_L__ERROR_EVENT_MASK___M 0x00000001 +#define PHYA_TXFD_EVENT_MASK_L__ERROR_EVENT_MASK___S 0 +#define PHYA_TXFD_EVENT_MASK_L___M 0xFFFFFFFF +#define PHYA_TXFD_EVENT_MASK_L___S 0 + +#define PHYA_TXFD_EVENT_MASK_U (0x00390024) +#define PHYA_TXFD_EVENT_MASK_U___RWC QCSR_REG_RW +#define PHYA_TXFD_EVENT_MASK_U___POR 0x0000FFFF +#define PHYA_TXFD_EVENT_MASK_U__TLV_15_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_U__TLV_14_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_U__TLV_13_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_U__TLV_12_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_U__TLV_11_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_U__TLV_10_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_U__TLV_9_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_U__TLV_8_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_U__TLV_7_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_U__TLV_6_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_U__TLV_5_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_U__TLV_4_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_U__TLV_3_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_U__TLV_2_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_U__TLV_1_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_U__TLV_0_EVENT_MASK___POR 0x1 +#define PHYA_TXFD_EVENT_MASK_U__TLV_15_EVENT_MASK___M 0x00008000 +#define PHYA_TXFD_EVENT_MASK_U__TLV_15_EVENT_MASK___S 15 +#define PHYA_TXFD_EVENT_MASK_U__TLV_14_EVENT_MASK___M 0x00004000 +#define PHYA_TXFD_EVENT_MASK_U__TLV_14_EVENT_MASK___S 14 +#define PHYA_TXFD_EVENT_MASK_U__TLV_13_EVENT_MASK___M 0x00002000 +#define PHYA_TXFD_EVENT_MASK_U__TLV_13_EVENT_MASK___S 13 +#define PHYA_TXFD_EVENT_MASK_U__TLV_12_EVENT_MASK___M 0x00001000 +#define PHYA_TXFD_EVENT_MASK_U__TLV_12_EVENT_MASK___S 12 +#define PHYA_TXFD_EVENT_MASK_U__TLV_11_EVENT_MASK___M 0x00000800 +#define PHYA_TXFD_EVENT_MASK_U__TLV_11_EVENT_MASK___S 11 +#define PHYA_TXFD_EVENT_MASK_U__TLV_10_EVENT_MASK___M 0x00000400 +#define PHYA_TXFD_EVENT_MASK_U__TLV_10_EVENT_MASK___S 10 +#define PHYA_TXFD_EVENT_MASK_U__TLV_9_EVENT_MASK___M 0x00000200 +#define PHYA_TXFD_EVENT_MASK_U__TLV_9_EVENT_MASK___S 9 +#define PHYA_TXFD_EVENT_MASK_U__TLV_8_EVENT_MASK___M 0x00000100 +#define PHYA_TXFD_EVENT_MASK_U__TLV_8_EVENT_MASK___S 8 +#define PHYA_TXFD_EVENT_MASK_U__TLV_7_EVENT_MASK___M 0x00000080 +#define PHYA_TXFD_EVENT_MASK_U__TLV_7_EVENT_MASK___S 7 +#define PHYA_TXFD_EVENT_MASK_U__TLV_6_EVENT_MASK___M 0x00000040 +#define PHYA_TXFD_EVENT_MASK_U__TLV_6_EVENT_MASK___S 6 +#define PHYA_TXFD_EVENT_MASK_U__TLV_5_EVENT_MASK___M 0x00000020 +#define PHYA_TXFD_EVENT_MASK_U__TLV_5_EVENT_MASK___S 5 +#define PHYA_TXFD_EVENT_MASK_U__TLV_4_EVENT_MASK___M 0x00000010 +#define PHYA_TXFD_EVENT_MASK_U__TLV_4_EVENT_MASK___S 4 +#define PHYA_TXFD_EVENT_MASK_U__TLV_3_EVENT_MASK___M 0x00000008 +#define PHYA_TXFD_EVENT_MASK_U__TLV_3_EVENT_MASK___S 3 +#define PHYA_TXFD_EVENT_MASK_U__TLV_2_EVENT_MASK___M 0x00000004 +#define PHYA_TXFD_EVENT_MASK_U__TLV_2_EVENT_MASK___S 2 +#define PHYA_TXFD_EVENT_MASK_U__TLV_1_EVENT_MASK___M 0x00000002 +#define PHYA_TXFD_EVENT_MASK_U__TLV_1_EVENT_MASK___S 1 +#define PHYA_TXFD_EVENT_MASK_U__TLV_0_EVENT_MASK___M 0x00000001 +#define PHYA_TXFD_EVENT_MASK_U__TLV_0_EVENT_MASK___S 0 +#define PHYA_TXFD_EVENT_MASK_U___M 0x0000FFFF +#define PHYA_TXFD_EVENT_MASK_U___S 0 + +#define PHYA_TXFD_EVENT_TLV_STATUS_L (0x00390028) +#define PHYA_TXFD_EVENT_TLV_STATUS_L___RWC QCSR_REG_RO +#define PHYA_TXFD_EVENT_TLV_STATUS_L___POR 0x00000000 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_15___POR 0x0 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_14___POR 0x0 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_13___POR 0x0 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_12___POR 0x0 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_11___POR 0x0 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_10___POR 0x0 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_9___POR 0x0 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_8___POR 0x0 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_7___POR 0x0 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_6___POR 0x0 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_5___POR 0x0 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_4___POR 0x0 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_3___POR 0x0 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_2___POR 0x0 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_1___POR 0x0 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_0___POR 0x0 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_15___M 0x00008000 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_15___S 15 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_14___M 0x00004000 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_14___S 14 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_13___M 0x00002000 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_13___S 13 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_12___M 0x00001000 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_12___S 12 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_11___M 0x00000800 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_11___S 11 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_10___M 0x00000400 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_10___S 10 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_9___M 0x00000200 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_9___S 9 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_8___M 0x00000100 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_8___S 8 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_7___M 0x00000080 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_7___S 7 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_6___M 0x00000040 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_6___S 6 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_5___M 0x00000020 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_5___S 5 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_4___M 0x00000010 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_4___S 4 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_3___M 0x00000008 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_3___S 3 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_2___M 0x00000004 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_2___S 2 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_1___M 0x00000002 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_1___S 1 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_0___M 0x00000001 +#define PHYA_TXFD_EVENT_TLV_STATUS_L__TLV_STATUS_0___S 0 +#define PHYA_TXFD_EVENT_TLV_STATUS_L___M 0x0000FFFF +#define PHYA_TXFD_EVENT_TLV_STATUS_L___S 0 + +#define PHYA_TXFD_EVENT_TLV_MASK_L (0x00390030) +#define PHYA_TXFD_EVENT_TLV_MASK_L___RWC QCSR_REG_RW +#define PHYA_TXFD_EVENT_TLV_MASK_L___POR 0x00000000 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_15___POR 0x0 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_14___POR 0x0 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_13___POR 0x0 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_12___POR 0x0 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_11___POR 0x0 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_10___POR 0x0 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_9___POR 0x0 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_8___POR 0x0 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_7___POR 0x0 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_6___POR 0x0 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_5___POR 0x0 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_4___POR 0x0 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_3___POR 0x0 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_2___POR 0x0 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_1___POR 0x0 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_0___POR 0x0 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_15___M 0x00008000 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_15___S 15 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_14___M 0x00004000 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_14___S 14 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_13___M 0x00002000 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_13___S 13 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_12___M 0x00001000 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_12___S 12 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_11___M 0x00000800 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_11___S 11 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_10___M 0x00000400 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_10___S 10 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_9___M 0x00000200 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_9___S 9 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_8___M 0x00000100 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_8___S 8 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_7___M 0x00000080 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_7___S 7 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_6___M 0x00000040 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_6___S 6 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_5___M 0x00000020 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_5___S 5 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_4___M 0x00000010 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_4___S 4 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_3___M 0x00000008 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_3___S 3 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_2___M 0x00000004 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_2___S 2 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_1___M 0x00000002 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_1___S 1 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_0___M 0x00000001 +#define PHYA_TXFD_EVENT_TLV_MASK_L__TLV_MASK_0___S 0 +#define PHYA_TXFD_EVENT_TLV_MASK_L___M 0x0000FFFF +#define PHYA_TXFD_EVENT_TLV_MASK_L___S 0 + +#define PHYA_TXFD_ERROR_CODE_L (0x00390038) +#define PHYA_TXFD_ERROR_CODE_L___RWC QCSR_REG_RO +#define PHYA_TXFD_ERROR_CODE_L___POR 0x00000000 +#define PHYA_TXFD_ERROR_CODE_L__ERROR_CODE___POR 0x00000000 +#define PHYA_TXFD_ERROR_CODE_L__ERROR_CODE___M 0xFFFFFFFF +#define PHYA_TXFD_ERROR_CODE_L__ERROR_CODE___S 0 +#define PHYA_TXFD_ERROR_CODE_L___M 0xFFFFFFFF +#define PHYA_TXFD_ERROR_CODE_L___S 0 + +#define PHYA_TXFD_ERROR_STATUS_L (0x00390040) +#define PHYA_TXFD_ERROR_STATUS_L___RWC QCSR_REG_RO +#define PHYA_TXFD_ERROR_STATUS_L___POR 0x00000000 +#define PHYA_TXFD_ERROR_STATUS_L__EXTRA_USER_DESC_PER_USER_TLV_ERROR___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_L__UNKNOWN_RU_ALLOC_ERROR___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_L__TXB_REQ_FIFO_UNDERRUN_ERROR___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_L__TXFD_HW_ACC_ERROR___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_L__TXFD_AXI_SLAVE_TIMEOUT_ERROR___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_L__LEG_BF_WEIGHTS_NOT_READY_ERROR___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_L__TXFD_WATCHDOG_TIMEOUT_ERROR___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_L__REQ_TIMER_BREACH_ERROR___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_L__BF_WEIGHTS_NOT_READY_ERROR___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_L__PRE_PKT_ISR_NOT_DONE_BEFORE_PHY_DESC___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_L__PHY_ABORT_ACK_WATCHDOG_TIMEOUT_ERROR___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_L__NUM_PAD_BITS_ERROR___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_L__STREAM_RU_HANG_ERROR___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_L__USER_RU_HANG_ERROR___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_L__ILLEGAL_CF_TLV_ERROR___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_L__ORDERING_FIFO_NO_RD_ERROR___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_L__TLV_FIFO_NO_RD_ERROR___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_L__TLV_FIFO_RD_HANG_ERROR___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_L__UNEXPECTED_MAC_PKT_END_ERROR___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_L__MAC_RESPONSE_ORDERING_ERROR___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_L__UNKNOWN_TLV_ERROR___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_L__HE_SIGA_FIFO_OVERFLOW_ERROR___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_L__SPURIOUS_DATA_FIFO_WRITE_ERROR___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_L__HE_SIGB_FIFO_OVERFLOW_ERROR___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_L__SERVICE_FIFO_OVERFLOW_ERROR___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_L__DATA_FIFO_OVERFLOW_ERROR___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_L__DATA_FIFO_UNDERFLOW_ERROR___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_L__TLV_FIFO_OVERFLOW_ERROR___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_L__CONTROL_TLV_FIFO_OVERFLOW_ERROR___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_L__MPI_REQ_GRANT_ERROR___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_L__TXCCK_UNDERRUN_ERROR___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_L__TXCCK_ILLEGAL_TX_RATE_ERROR___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_L__EXTRA_USER_DESC_PER_USER_TLV_ERROR___M 0x80000000 +#define PHYA_TXFD_ERROR_STATUS_L__EXTRA_USER_DESC_PER_USER_TLV_ERROR___S 31 +#define PHYA_TXFD_ERROR_STATUS_L__UNKNOWN_RU_ALLOC_ERROR___M 0x40000000 +#define PHYA_TXFD_ERROR_STATUS_L__UNKNOWN_RU_ALLOC_ERROR___S 30 +#define PHYA_TXFD_ERROR_STATUS_L__TXB_REQ_FIFO_UNDERRUN_ERROR___M 0x20000000 +#define PHYA_TXFD_ERROR_STATUS_L__TXB_REQ_FIFO_UNDERRUN_ERROR___S 29 +#define PHYA_TXFD_ERROR_STATUS_L__TXFD_HW_ACC_ERROR___M 0x10000000 +#define PHYA_TXFD_ERROR_STATUS_L__TXFD_HW_ACC_ERROR___S 28 +#define PHYA_TXFD_ERROR_STATUS_L__TXFD_AXI_SLAVE_TIMEOUT_ERROR___M 0x08000000 +#define PHYA_TXFD_ERROR_STATUS_L__TXFD_AXI_SLAVE_TIMEOUT_ERROR___S 27 +#define PHYA_TXFD_ERROR_STATUS_L__LEG_BF_WEIGHTS_NOT_READY_ERROR___M 0x04000000 +#define PHYA_TXFD_ERROR_STATUS_L__LEG_BF_WEIGHTS_NOT_READY_ERROR___S 26 +#define PHYA_TXFD_ERROR_STATUS_L__TXFD_WATCHDOG_TIMEOUT_ERROR___M 0x02000000 +#define PHYA_TXFD_ERROR_STATUS_L__TXFD_WATCHDOG_TIMEOUT_ERROR___S 25 +#define PHYA_TXFD_ERROR_STATUS_L__REQ_TIMER_BREACH_ERROR___M 0x01000000 +#define PHYA_TXFD_ERROR_STATUS_L__REQ_TIMER_BREACH_ERROR___S 24 +#define PHYA_TXFD_ERROR_STATUS_L__BF_WEIGHTS_NOT_READY_ERROR___M 0x00800000 +#define PHYA_TXFD_ERROR_STATUS_L__BF_WEIGHTS_NOT_READY_ERROR___S 23 +#define PHYA_TXFD_ERROR_STATUS_L__PRE_PKT_ISR_NOT_DONE_BEFORE_PHY_DESC___M 0x00400000 +#define PHYA_TXFD_ERROR_STATUS_L__PRE_PKT_ISR_NOT_DONE_BEFORE_PHY_DESC___S 22 +#define PHYA_TXFD_ERROR_STATUS_L__PHY_ABORT_ACK_WATCHDOG_TIMEOUT_ERROR___M 0x00200000 +#define PHYA_TXFD_ERROR_STATUS_L__PHY_ABORT_ACK_WATCHDOG_TIMEOUT_ERROR___S 21 +#define PHYA_TXFD_ERROR_STATUS_L__NUM_PAD_BITS_ERROR___M 0x00100000 +#define PHYA_TXFD_ERROR_STATUS_L__NUM_PAD_BITS_ERROR___S 20 +#define PHYA_TXFD_ERROR_STATUS_L__STREAM_RU_HANG_ERROR___M 0x00080000 +#define PHYA_TXFD_ERROR_STATUS_L__STREAM_RU_HANG_ERROR___S 19 +#define PHYA_TXFD_ERROR_STATUS_L__USER_RU_HANG_ERROR___M 0x00040000 +#define PHYA_TXFD_ERROR_STATUS_L__USER_RU_HANG_ERROR___S 18 +#define PHYA_TXFD_ERROR_STATUS_L__ILLEGAL_CF_TLV_ERROR___M 0x00020000 +#define PHYA_TXFD_ERROR_STATUS_L__ILLEGAL_CF_TLV_ERROR___S 17 +#define PHYA_TXFD_ERROR_STATUS_L__ORDERING_FIFO_NO_RD_ERROR___M 0x00010000 +#define PHYA_TXFD_ERROR_STATUS_L__ORDERING_FIFO_NO_RD_ERROR___S 16 +#define PHYA_TXFD_ERROR_STATUS_L__TLV_FIFO_NO_RD_ERROR___M 0x00008000 +#define PHYA_TXFD_ERROR_STATUS_L__TLV_FIFO_NO_RD_ERROR___S 15 +#define PHYA_TXFD_ERROR_STATUS_L__TLV_FIFO_RD_HANG_ERROR___M 0x00004000 +#define PHYA_TXFD_ERROR_STATUS_L__TLV_FIFO_RD_HANG_ERROR___S 14 +#define PHYA_TXFD_ERROR_STATUS_L__UNEXPECTED_MAC_PKT_END_ERROR___M 0x00002000 +#define PHYA_TXFD_ERROR_STATUS_L__UNEXPECTED_MAC_PKT_END_ERROR___S 13 +#define PHYA_TXFD_ERROR_STATUS_L__MAC_RESPONSE_ORDERING_ERROR___M 0x00001000 +#define PHYA_TXFD_ERROR_STATUS_L__MAC_RESPONSE_ORDERING_ERROR___S 12 +#define PHYA_TXFD_ERROR_STATUS_L__UNKNOWN_TLV_ERROR___M 0x00000800 +#define PHYA_TXFD_ERROR_STATUS_L__UNKNOWN_TLV_ERROR___S 11 +#define PHYA_TXFD_ERROR_STATUS_L__HE_SIGA_FIFO_OVERFLOW_ERROR___M 0x00000400 +#define PHYA_TXFD_ERROR_STATUS_L__HE_SIGA_FIFO_OVERFLOW_ERROR___S 10 +#define PHYA_TXFD_ERROR_STATUS_L__SPURIOUS_DATA_FIFO_WRITE_ERROR___M 0x00000200 +#define PHYA_TXFD_ERROR_STATUS_L__SPURIOUS_DATA_FIFO_WRITE_ERROR___S 9 +#define PHYA_TXFD_ERROR_STATUS_L__HE_SIGB_FIFO_OVERFLOW_ERROR___M 0x00000100 +#define PHYA_TXFD_ERROR_STATUS_L__HE_SIGB_FIFO_OVERFLOW_ERROR___S 8 +#define PHYA_TXFD_ERROR_STATUS_L__SERVICE_FIFO_OVERFLOW_ERROR___M 0x00000080 +#define PHYA_TXFD_ERROR_STATUS_L__SERVICE_FIFO_OVERFLOW_ERROR___S 7 +#define PHYA_TXFD_ERROR_STATUS_L__DATA_FIFO_OVERFLOW_ERROR___M 0x00000040 +#define PHYA_TXFD_ERROR_STATUS_L__DATA_FIFO_OVERFLOW_ERROR___S 6 +#define PHYA_TXFD_ERROR_STATUS_L__DATA_FIFO_UNDERFLOW_ERROR___M 0x00000020 +#define PHYA_TXFD_ERROR_STATUS_L__DATA_FIFO_UNDERFLOW_ERROR___S 5 +#define PHYA_TXFD_ERROR_STATUS_L__TLV_FIFO_OVERFLOW_ERROR___M 0x00000010 +#define PHYA_TXFD_ERROR_STATUS_L__TLV_FIFO_OVERFLOW_ERROR___S 4 +#define PHYA_TXFD_ERROR_STATUS_L__CONTROL_TLV_FIFO_OVERFLOW_ERROR___M 0x00000008 +#define PHYA_TXFD_ERROR_STATUS_L__CONTROL_TLV_FIFO_OVERFLOW_ERROR___S 3 +#define PHYA_TXFD_ERROR_STATUS_L__MPI_REQ_GRANT_ERROR___M 0x00000004 +#define PHYA_TXFD_ERROR_STATUS_L__MPI_REQ_GRANT_ERROR___S 2 +#define PHYA_TXFD_ERROR_STATUS_L__TXCCK_UNDERRUN_ERROR___M 0x00000002 +#define PHYA_TXFD_ERROR_STATUS_L__TXCCK_UNDERRUN_ERROR___S 1 +#define PHYA_TXFD_ERROR_STATUS_L__TXCCK_ILLEGAL_TX_RATE_ERROR___M 0x00000001 +#define PHYA_TXFD_ERROR_STATUS_L__TXCCK_ILLEGAL_TX_RATE_ERROR___S 0 +#define PHYA_TXFD_ERROR_STATUS_L___M 0xFFFFFFFF +#define PHYA_TXFD_ERROR_STATUS_L___S 0 + +#define PHYA_TXFD_ERROR_STATUS_U (0x00390044) +#define PHYA_TXFD_ERROR_STATUS_U___RWC QCSR_REG_RO +#define PHYA_TXFD_ERROR_STATUS_U___POR 0x00000000 +#define PHYA_TXFD_ERROR_STATUS_U__TLV_FIFO_PER_USER_NO_RD_ERROR___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_U__TLV_FIFO_PER_USER_RD_HANG_ERROR___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_U__LDPC_PARAM_CALC_TIMEOUT_ERROR___POR 0x0 +#define PHYA_TXFD_ERROR_STATUS_U__TLV_FIFO_PER_USER_NO_RD_ERROR___M 0x00000004 +#define PHYA_TXFD_ERROR_STATUS_U__TLV_FIFO_PER_USER_NO_RD_ERROR___S 2 +#define PHYA_TXFD_ERROR_STATUS_U__TLV_FIFO_PER_USER_RD_HANG_ERROR___M 0x00000002 +#define PHYA_TXFD_ERROR_STATUS_U__TLV_FIFO_PER_USER_RD_HANG_ERROR___S 1 +#define PHYA_TXFD_ERROR_STATUS_U__LDPC_PARAM_CALC_TIMEOUT_ERROR___M 0x00000001 +#define PHYA_TXFD_ERROR_STATUS_U__LDPC_PARAM_CALC_TIMEOUT_ERROR___S 0 +#define PHYA_TXFD_ERROR_STATUS_U___M 0x00000007 +#define PHYA_TXFD_ERROR_STATUS_U___S 0 + +#define PHYA_TXFD_ERROR_MASK_L (0x00390048) +#define PHYA_TXFD_ERROR_MASK_L___RWC QCSR_REG_RW +#define PHYA_TXFD_ERROR_MASK_L___POR 0xFFFFFFFF +#define PHYA_TXFD_ERROR_MASK_L__EXTRA_USER_DESC_PER_USER_TLV_ERROR_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_L__UNKNOWN_RU_ALLOC_ERROR_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_L__TXB_REQ_FIFO_UNDERRUN_ERROR_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_L__TXFD_HW_ACC_ERROR_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_L__TXFD_AXI_SLAVE_TIMEOUT_ERROR_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_L__LEG_BF_WEIGHTS_NOT_READY_ERROR_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_L__TXFD_WATCHDOG_TIMEOUT_ERROR_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_L__REQ_TIMER_BREACH_ERROR_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_L__BF_WEIGHTS_NOT_READY_ERROR_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_L__PRE_PKT_ISR_NOT_DONE_BEFORE_PHY_DESC_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_L__PHY_ABORT_ACK_WATCHDOG_TIMEOUT_ERROR_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_L__NUM_PAD_BITS_ERROR_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_L__STREAM_RU_HANG_ERROR_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_L__USER_RU_HANG_ERROR_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_L__ILLEGAL_CF_TLV_ERROR_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_L__ORDERING_FIFO_NO_RD_ERROR_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_L__TLV_FIFO_NO_RD_ERROR_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_L__TLV_FIFO_RD_HANG_ERROR_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_L__UNEXPECTED_MAC_PKT_END_ERROR_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_L__MAC_RESPONSE_ORDERING_ERROR_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_L__UNKNOWN_TLV_ERROR_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_L__HE_SIGA_FIFO_OVERFLOW_ERROR_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_L__SPURIOUS_DATA_FIFO_WRITE_ERROR_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_L__HE_SIGB_FIFO_OVERFLOW_ERROR_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_L__SERVICE_FIFO_OVERFLOW_ERROR_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_L__DATA_FIFO_OVERFLOW_ERROR_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_L__DATA_FIFO_UNDERFLOW_ERROR_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_L__TLV_FIFO_OVERFLOW_ERROR_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_L__CONTROL_TLV_FIFO_OVERFLOW_ERROR_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_L__MPI_REQ_GRANT_ERROR_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_L__TXCCK_UNDERRUN_ERROR_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_L__TXCCK_ILLEGAL_TX_RATE_ERROR_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_L__EXTRA_USER_DESC_PER_USER_TLV_ERROR_MASK___M 0x80000000 +#define PHYA_TXFD_ERROR_MASK_L__EXTRA_USER_DESC_PER_USER_TLV_ERROR_MASK___S 31 +#define PHYA_TXFD_ERROR_MASK_L__UNKNOWN_RU_ALLOC_ERROR_MASK___M 0x40000000 +#define PHYA_TXFD_ERROR_MASK_L__UNKNOWN_RU_ALLOC_ERROR_MASK___S 30 +#define PHYA_TXFD_ERROR_MASK_L__TXB_REQ_FIFO_UNDERRUN_ERROR_MASK___M 0x20000000 +#define PHYA_TXFD_ERROR_MASK_L__TXB_REQ_FIFO_UNDERRUN_ERROR_MASK___S 29 +#define PHYA_TXFD_ERROR_MASK_L__TXFD_HW_ACC_ERROR_MASK___M 0x10000000 +#define PHYA_TXFD_ERROR_MASK_L__TXFD_HW_ACC_ERROR_MASK___S 28 +#define PHYA_TXFD_ERROR_MASK_L__TXFD_AXI_SLAVE_TIMEOUT_ERROR_MASK___M 0x08000000 +#define PHYA_TXFD_ERROR_MASK_L__TXFD_AXI_SLAVE_TIMEOUT_ERROR_MASK___S 27 +#define PHYA_TXFD_ERROR_MASK_L__LEG_BF_WEIGHTS_NOT_READY_ERROR_MASK___M 0x04000000 +#define PHYA_TXFD_ERROR_MASK_L__LEG_BF_WEIGHTS_NOT_READY_ERROR_MASK___S 26 +#define PHYA_TXFD_ERROR_MASK_L__TXFD_WATCHDOG_TIMEOUT_ERROR_MASK___M 0x02000000 +#define PHYA_TXFD_ERROR_MASK_L__TXFD_WATCHDOG_TIMEOUT_ERROR_MASK___S 25 +#define PHYA_TXFD_ERROR_MASK_L__REQ_TIMER_BREACH_ERROR_MASK___M 0x01000000 +#define PHYA_TXFD_ERROR_MASK_L__REQ_TIMER_BREACH_ERROR_MASK___S 24 +#define PHYA_TXFD_ERROR_MASK_L__BF_WEIGHTS_NOT_READY_ERROR_MASK___M 0x00800000 +#define PHYA_TXFD_ERROR_MASK_L__BF_WEIGHTS_NOT_READY_ERROR_MASK___S 23 +#define PHYA_TXFD_ERROR_MASK_L__PRE_PKT_ISR_NOT_DONE_BEFORE_PHY_DESC_MASK___M 0x00400000 +#define PHYA_TXFD_ERROR_MASK_L__PRE_PKT_ISR_NOT_DONE_BEFORE_PHY_DESC_MASK___S 22 +#define PHYA_TXFD_ERROR_MASK_L__PHY_ABORT_ACK_WATCHDOG_TIMEOUT_ERROR_MASK___M 0x00200000 +#define PHYA_TXFD_ERROR_MASK_L__PHY_ABORT_ACK_WATCHDOG_TIMEOUT_ERROR_MASK___S 21 +#define PHYA_TXFD_ERROR_MASK_L__NUM_PAD_BITS_ERROR_MASK___M 0x00100000 +#define PHYA_TXFD_ERROR_MASK_L__NUM_PAD_BITS_ERROR_MASK___S 20 +#define PHYA_TXFD_ERROR_MASK_L__STREAM_RU_HANG_ERROR_MASK___M 0x00080000 +#define PHYA_TXFD_ERROR_MASK_L__STREAM_RU_HANG_ERROR_MASK___S 19 +#define PHYA_TXFD_ERROR_MASK_L__USER_RU_HANG_ERROR_MASK___M 0x00040000 +#define PHYA_TXFD_ERROR_MASK_L__USER_RU_HANG_ERROR_MASK___S 18 +#define PHYA_TXFD_ERROR_MASK_L__ILLEGAL_CF_TLV_ERROR_MASK___M 0x00020000 +#define PHYA_TXFD_ERROR_MASK_L__ILLEGAL_CF_TLV_ERROR_MASK___S 17 +#define PHYA_TXFD_ERROR_MASK_L__ORDERING_FIFO_NO_RD_ERROR_MASK___M 0x00010000 +#define PHYA_TXFD_ERROR_MASK_L__ORDERING_FIFO_NO_RD_ERROR_MASK___S 16 +#define PHYA_TXFD_ERROR_MASK_L__TLV_FIFO_NO_RD_ERROR_MASK___M 0x00008000 +#define PHYA_TXFD_ERROR_MASK_L__TLV_FIFO_NO_RD_ERROR_MASK___S 15 +#define PHYA_TXFD_ERROR_MASK_L__TLV_FIFO_RD_HANG_ERROR_MASK___M 0x00004000 +#define PHYA_TXFD_ERROR_MASK_L__TLV_FIFO_RD_HANG_ERROR_MASK___S 14 +#define PHYA_TXFD_ERROR_MASK_L__UNEXPECTED_MAC_PKT_END_ERROR_MASK___M 0x00002000 +#define PHYA_TXFD_ERROR_MASK_L__UNEXPECTED_MAC_PKT_END_ERROR_MASK___S 13 +#define PHYA_TXFD_ERROR_MASK_L__MAC_RESPONSE_ORDERING_ERROR_MASK___M 0x00001000 +#define PHYA_TXFD_ERROR_MASK_L__MAC_RESPONSE_ORDERING_ERROR_MASK___S 12 +#define PHYA_TXFD_ERROR_MASK_L__UNKNOWN_TLV_ERROR_MASK___M 0x00000800 +#define PHYA_TXFD_ERROR_MASK_L__UNKNOWN_TLV_ERROR_MASK___S 11 +#define PHYA_TXFD_ERROR_MASK_L__HE_SIGA_FIFO_OVERFLOW_ERROR_MASK___M 0x00000400 +#define PHYA_TXFD_ERROR_MASK_L__HE_SIGA_FIFO_OVERFLOW_ERROR_MASK___S 10 +#define PHYA_TXFD_ERROR_MASK_L__SPURIOUS_DATA_FIFO_WRITE_ERROR_MASK___M 0x00000200 +#define PHYA_TXFD_ERROR_MASK_L__SPURIOUS_DATA_FIFO_WRITE_ERROR_MASK___S 9 +#define PHYA_TXFD_ERROR_MASK_L__HE_SIGB_FIFO_OVERFLOW_ERROR_MASK___M 0x00000100 +#define PHYA_TXFD_ERROR_MASK_L__HE_SIGB_FIFO_OVERFLOW_ERROR_MASK___S 8 +#define PHYA_TXFD_ERROR_MASK_L__SERVICE_FIFO_OVERFLOW_ERROR_MASK___M 0x00000080 +#define PHYA_TXFD_ERROR_MASK_L__SERVICE_FIFO_OVERFLOW_ERROR_MASK___S 7 +#define PHYA_TXFD_ERROR_MASK_L__DATA_FIFO_OVERFLOW_ERROR_MASK___M 0x00000040 +#define PHYA_TXFD_ERROR_MASK_L__DATA_FIFO_OVERFLOW_ERROR_MASK___S 6 +#define PHYA_TXFD_ERROR_MASK_L__DATA_FIFO_UNDERFLOW_ERROR_MASK___M 0x00000020 +#define PHYA_TXFD_ERROR_MASK_L__DATA_FIFO_UNDERFLOW_ERROR_MASK___S 5 +#define PHYA_TXFD_ERROR_MASK_L__TLV_FIFO_OVERFLOW_ERROR_MASK___M 0x00000010 +#define PHYA_TXFD_ERROR_MASK_L__TLV_FIFO_OVERFLOW_ERROR_MASK___S 4 +#define PHYA_TXFD_ERROR_MASK_L__CONTROL_TLV_FIFO_OVERFLOW_ERROR_MASK___M 0x00000008 +#define PHYA_TXFD_ERROR_MASK_L__CONTROL_TLV_FIFO_OVERFLOW_ERROR_MASK___S 3 +#define PHYA_TXFD_ERROR_MASK_L__MPI_REQ_GRANT_ERROR_MASK___M 0x00000004 +#define PHYA_TXFD_ERROR_MASK_L__MPI_REQ_GRANT_ERROR_MASK___S 2 +#define PHYA_TXFD_ERROR_MASK_L__TXCCK_UNDERRUN_ERROR_MASK___M 0x00000002 +#define PHYA_TXFD_ERROR_MASK_L__TXCCK_UNDERRUN_ERROR_MASK___S 1 +#define PHYA_TXFD_ERROR_MASK_L__TXCCK_ILLEGAL_TX_RATE_ERROR_MASK___M 0x00000001 +#define PHYA_TXFD_ERROR_MASK_L__TXCCK_ILLEGAL_TX_RATE_ERROR_MASK___S 0 +#define PHYA_TXFD_ERROR_MASK_L___M 0xFFFFFFFF +#define PHYA_TXFD_ERROR_MASK_L___S 0 + +#define PHYA_TXFD_ERROR_MASK_U (0x0039004C) +#define PHYA_TXFD_ERROR_MASK_U___RWC QCSR_REG_RW +#define PHYA_TXFD_ERROR_MASK_U___POR 0x00000007 +#define PHYA_TXFD_ERROR_MASK_U__TLV_FIFO_PER_USER_NO_RD_ERROR_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_U__TLV_FIFO_PER_USER_RD_HANG_ERROR_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_U__LDPC_PARAM_CALC_TIMEOUT_ERROR_MASK___POR 0x1 +#define PHYA_TXFD_ERROR_MASK_U__TLV_FIFO_PER_USER_NO_RD_ERROR_MASK___M 0x00000004 +#define PHYA_TXFD_ERROR_MASK_U__TLV_FIFO_PER_USER_NO_RD_ERROR_MASK___S 2 +#define PHYA_TXFD_ERROR_MASK_U__TLV_FIFO_PER_USER_RD_HANG_ERROR_MASK___M 0x00000002 +#define PHYA_TXFD_ERROR_MASK_U__TLV_FIFO_PER_USER_RD_HANG_ERROR_MASK___S 1 +#define PHYA_TXFD_ERROR_MASK_U__LDPC_PARAM_CALC_TIMEOUT_ERROR_MASK___M 0x00000001 +#define PHYA_TXFD_ERROR_MASK_U__LDPC_PARAM_CALC_TIMEOUT_ERROR_MASK___S 0 +#define PHYA_TXFD_ERROR_MASK_U___M 0x00000007 +#define PHYA_TXFD_ERROR_MASK_U___S 0 + +#define PHYA_TXFD_PHYDBG_MPI_0_L (0x00390050) +#define PHYA_TXFD_PHYDBG_MPI_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_PHYDBG_MPI_0_L___POR 0x00000000 +#define PHYA_TXFD_PHYDBG_MPI_0_L__MPI_PHYDBG_MUX_SEL___POR 0x0 +#define PHYA_TXFD_PHYDBG_MPI_0_L__MPI_PHYDBG_EVENT_EN___POR 0x00 +#define PHYA_TXFD_PHYDBG_MPI_0_L__MPI_PHYDBG_RAW_MODE___POR 0x0 +#define PHYA_TXFD_PHYDBG_MPI_0_L__MPI_PHYDBG_MUX_SEL___M 0x00030000 +#define PHYA_TXFD_PHYDBG_MPI_0_L__MPI_PHYDBG_MUX_SEL___S 16 +#define PHYA_TXFD_PHYDBG_MPI_0_L__MPI_PHYDBG_EVENT_EN___M 0x0000FF00 +#define PHYA_TXFD_PHYDBG_MPI_0_L__MPI_PHYDBG_EVENT_EN___S 8 +#define PHYA_TXFD_PHYDBG_MPI_0_L__MPI_PHYDBG_RAW_MODE___M 0x00000001 +#define PHYA_TXFD_PHYDBG_MPI_0_L__MPI_PHYDBG_RAW_MODE___S 0 +#define PHYA_TXFD_PHYDBG_MPI_0_L___M 0x0003FF01 +#define PHYA_TXFD_PHYDBG_MPI_0_L___S 0 + +#define PHYA_TXFD_PHYDBG_MPI_1_L (0x00390058) +#define PHYA_TXFD_PHYDBG_MPI_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_PHYDBG_MPI_1_L___POR 0x00000000 +#define PHYA_TXFD_PHYDBG_MPI_1_L__MPI_PHYDBG_TLV_MASK_0___POR 0x00000000 +#define PHYA_TXFD_PHYDBG_MPI_1_L__MPI_PHYDBG_TLV_MASK_0___M 0xFFFFFFFF +#define PHYA_TXFD_PHYDBG_MPI_1_L__MPI_PHYDBG_TLV_MASK_0___S 0 +#define PHYA_TXFD_PHYDBG_MPI_1_L___M 0xFFFFFFFF +#define PHYA_TXFD_PHYDBG_MPI_1_L___S 0 + +#define PHYA_TXFD_PHYDBG_MPI_1_U (0x0039005C) +#define PHYA_TXFD_PHYDBG_MPI_1_U___RWC QCSR_REG_RW +#define PHYA_TXFD_PHYDBG_MPI_1_U___POR 0x00000000 +#define PHYA_TXFD_PHYDBG_MPI_1_U__MPI_PHYDBG_TLV_MASK_1___POR 0x00000000 +#define PHYA_TXFD_PHYDBG_MPI_1_U__MPI_PHYDBG_TLV_MASK_1___M 0xFFFFFFFF +#define PHYA_TXFD_PHYDBG_MPI_1_U__MPI_PHYDBG_TLV_MASK_1___S 0 +#define PHYA_TXFD_PHYDBG_MPI_1_U___M 0xFFFFFFFF +#define PHYA_TXFD_PHYDBG_MPI_1_U___S 0 + +#define PHYA_TXFD_PHYDBG_MPI_20_L (0x00390060) +#define PHYA_TXFD_PHYDBG_MPI_20_L___RWC QCSR_REG_RW +#define PHYA_TXFD_PHYDBG_MPI_20_L___POR 0x00000000 +#define PHYA_TXFD_PHYDBG_MPI_20_L__MPI_PHYDBG_EVENT_MASK_0_0___POR 0x00000000 +#define PHYA_TXFD_PHYDBG_MPI_20_L__MPI_PHYDBG_EVENT_MASK_0_0___M 0xFFFFFFFF +#define PHYA_TXFD_PHYDBG_MPI_20_L__MPI_PHYDBG_EVENT_MASK_0_0___S 0 +#define PHYA_TXFD_PHYDBG_MPI_20_L___M 0xFFFFFFFF +#define PHYA_TXFD_PHYDBG_MPI_20_L___S 0 + +#define PHYA_TXFD_PHYDBG_MPI_20_U (0x00390064) +#define PHYA_TXFD_PHYDBG_MPI_20_U___RWC QCSR_REG_RW +#define PHYA_TXFD_PHYDBG_MPI_20_U___POR 0x00000000 +#define PHYA_TXFD_PHYDBG_MPI_20_U__MPI_PHYDBG_EVENT_MASK_1_0___POR 0x00000000 +#define PHYA_TXFD_PHYDBG_MPI_20_U__MPI_PHYDBG_EVENT_MASK_1_0___M 0xFFFFFFFF +#define PHYA_TXFD_PHYDBG_MPI_20_U__MPI_PHYDBG_EVENT_MASK_1_0___S 0 +#define PHYA_TXFD_PHYDBG_MPI_20_U___M 0xFFFFFFFF +#define PHYA_TXFD_PHYDBG_MPI_20_U___S 0 + +#define PHYA_TXFD_PHYDBG_MPI_21_L (0x00390068) +#define PHYA_TXFD_PHYDBG_MPI_21_L___RWC QCSR_REG_RW +#define PHYA_TXFD_PHYDBG_MPI_21_L___POR 0x00000000 +#define PHYA_TXFD_PHYDBG_MPI_21_L__MPI_PHYDBG_EVENT_MASK_0_1___POR 0x00000000 +#define PHYA_TXFD_PHYDBG_MPI_21_L__MPI_PHYDBG_EVENT_MASK_0_1___M 0xFFFFFFFF +#define PHYA_TXFD_PHYDBG_MPI_21_L__MPI_PHYDBG_EVENT_MASK_0_1___S 0 +#define PHYA_TXFD_PHYDBG_MPI_21_L___M 0xFFFFFFFF +#define PHYA_TXFD_PHYDBG_MPI_21_L___S 0 + +#define PHYA_TXFD_PHYDBG_MPI_21_U (0x0039006C) +#define PHYA_TXFD_PHYDBG_MPI_21_U___RWC QCSR_REG_RW +#define PHYA_TXFD_PHYDBG_MPI_21_U___POR 0x00000000 +#define PHYA_TXFD_PHYDBG_MPI_21_U__MPI_PHYDBG_EVENT_MASK_1_1___POR 0x00000000 +#define PHYA_TXFD_PHYDBG_MPI_21_U__MPI_PHYDBG_EVENT_MASK_1_1___M 0xFFFFFFFF +#define PHYA_TXFD_PHYDBG_MPI_21_U__MPI_PHYDBG_EVENT_MASK_1_1___S 0 +#define PHYA_TXFD_PHYDBG_MPI_21_U___M 0xFFFFFFFF +#define PHYA_TXFD_PHYDBG_MPI_21_U___S 0 + +#define PHYA_TXFD_PHYDBG_TXFD_0_L (0x00390070) +#define PHYA_TXFD_PHYDBG_TXFD_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_PHYDBG_TXFD_0_L___POR 0x00000000 +#define PHYA_TXFD_PHYDBG_TXFD_0_L__USER_PHYDBG_RAW_MUX_SEL___POR 0x00 +#define PHYA_TXFD_PHYDBG_TXFD_0_L__TXFD_PHYDBG_EVENT_EN___POR 0x00 +#define PHYA_TXFD_PHYDBG_TXFD_0_L__TXFD_PHYDBG_RAW_MODE___POR 0x0 +#define PHYA_TXFD_PHYDBG_TXFD_0_L__TXFD_PHYDBG_RAW_STREAM_SEL___POR 0x0 +#define PHYA_TXFD_PHYDBG_TXFD_0_L__USER_PHYDBG_RAW_MUX_SEL___M 0x3F000000 +#define PHYA_TXFD_PHYDBG_TXFD_0_L__USER_PHYDBG_RAW_MUX_SEL___S 24 +#define PHYA_TXFD_PHYDBG_TXFD_0_L__TXFD_PHYDBG_EVENT_EN___M 0x00FF0000 +#define PHYA_TXFD_PHYDBG_TXFD_0_L__TXFD_PHYDBG_EVENT_EN___S 16 +#define PHYA_TXFD_PHYDBG_TXFD_0_L__TXFD_PHYDBG_RAW_MODE___M 0x00000100 +#define PHYA_TXFD_PHYDBG_TXFD_0_L__TXFD_PHYDBG_RAW_MODE___S 8 +#define PHYA_TXFD_PHYDBG_TXFD_0_L__TXFD_PHYDBG_RAW_STREAM_SEL___M 0x00000001 +#define PHYA_TXFD_PHYDBG_TXFD_0_L__TXFD_PHYDBG_RAW_STREAM_SEL___S 0 +#define PHYA_TXFD_PHYDBG_TXFD_0_L___M 0x3FFF0101 +#define PHYA_TXFD_PHYDBG_TXFD_0_L___S 0 + +#define PHYA_TXFD_PHYDBG_TXFD_0_U (0x00390074) +#define PHYA_TXFD_PHYDBG_TXFD_0_U___RWC QCSR_REG_RW +#define PHYA_TXFD_PHYDBG_TXFD_0_U___POR 0x00000000 +#define PHYA_TXFD_PHYDBG_TXFD_0_U__TXCTRL_PHYDBG_EVENT_MUX_SEL___POR 0x0 +#define PHYA_TXFD_PHYDBG_TXFD_0_U__STREAM_PHYDBG_EVENT_MUX_SEL___POR 0x00 +#define PHYA_TXFD_PHYDBG_TXFD_0_U__STREAM_PHYDBG_RAW_MUX_SEL___POR 0x00 +#define PHYA_TXFD_PHYDBG_TXFD_0_U__USER_PHYDBG_EVENT_MUX_SEL___POR 0x0 +#define PHYA_TXFD_PHYDBG_TXFD_0_U__TXCTRL_PHYDBG_EVENT_MUX_SEL___M 0x0F000000 +#define PHYA_TXFD_PHYDBG_TXFD_0_U__TXCTRL_PHYDBG_EVENT_MUX_SEL___S 24 +#define PHYA_TXFD_PHYDBG_TXFD_0_U__STREAM_PHYDBG_EVENT_MUX_SEL___M 0x00FF0000 +#define PHYA_TXFD_PHYDBG_TXFD_0_U__STREAM_PHYDBG_EVENT_MUX_SEL___S 16 +#define PHYA_TXFD_PHYDBG_TXFD_0_U__STREAM_PHYDBG_RAW_MUX_SEL___M 0x00003F00 +#define PHYA_TXFD_PHYDBG_TXFD_0_U__STREAM_PHYDBG_RAW_MUX_SEL___S 8 +#define PHYA_TXFD_PHYDBG_TXFD_0_U__USER_PHYDBG_EVENT_MUX_SEL___M 0x0000000F +#define PHYA_TXFD_PHYDBG_TXFD_0_U__USER_PHYDBG_EVENT_MUX_SEL___S 0 +#define PHYA_TXFD_PHYDBG_TXFD_0_U___M 0x0FFF3F0F +#define PHYA_TXFD_PHYDBG_TXFD_0_U___S 0 + +#define PHYA_TXFD_PHYDBG_TXFD_10_L (0x00390078) +#define PHYA_TXFD_PHYDBG_TXFD_10_L___RWC QCSR_REG_RW +#define PHYA_TXFD_PHYDBG_TXFD_10_L___POR 0x00000000 +#define PHYA_TXFD_PHYDBG_TXFD_10_L__TXFD_PHYDBG_EVENT_MASK_0_0___POR 0x00000000 +#define PHYA_TXFD_PHYDBG_TXFD_10_L__TXFD_PHYDBG_EVENT_MASK_0_0___M 0xFFFFFFFF +#define PHYA_TXFD_PHYDBG_TXFD_10_L__TXFD_PHYDBG_EVENT_MASK_0_0___S 0 +#define PHYA_TXFD_PHYDBG_TXFD_10_L___M 0xFFFFFFFF +#define PHYA_TXFD_PHYDBG_TXFD_10_L___S 0 + +#define PHYA_TXFD_PHYDBG_TXFD_10_U (0x0039007C) +#define PHYA_TXFD_PHYDBG_TXFD_10_U___RWC QCSR_REG_RW +#define PHYA_TXFD_PHYDBG_TXFD_10_U___POR 0x00000000 +#define PHYA_TXFD_PHYDBG_TXFD_10_U__TXFD_PHYDBG_EVENT_MASK_1_0___POR 0x00000000 +#define PHYA_TXFD_PHYDBG_TXFD_10_U__TXFD_PHYDBG_EVENT_MASK_1_0___M 0xFFFFFFFF +#define PHYA_TXFD_PHYDBG_TXFD_10_U__TXFD_PHYDBG_EVENT_MASK_1_0___S 0 +#define PHYA_TXFD_PHYDBG_TXFD_10_U___M 0xFFFFFFFF +#define PHYA_TXFD_PHYDBG_TXFD_10_U___S 0 + +#define PHYA_TXFD_PHYDBG_TXFD_11_L (0x00390080) +#define PHYA_TXFD_PHYDBG_TXFD_11_L___RWC QCSR_REG_RW +#define PHYA_TXFD_PHYDBG_TXFD_11_L___POR 0x00000000 +#define PHYA_TXFD_PHYDBG_TXFD_11_L__TXFD_PHYDBG_EVENT_MASK_0_1___POR 0x00000000 +#define PHYA_TXFD_PHYDBG_TXFD_11_L__TXFD_PHYDBG_EVENT_MASK_0_1___M 0xFFFFFFFF +#define PHYA_TXFD_PHYDBG_TXFD_11_L__TXFD_PHYDBG_EVENT_MASK_0_1___S 0 +#define PHYA_TXFD_PHYDBG_TXFD_11_L___M 0xFFFFFFFF +#define PHYA_TXFD_PHYDBG_TXFD_11_L___S 0 + +#define PHYA_TXFD_PHYDBG_TXFD_11_U (0x00390084) +#define PHYA_TXFD_PHYDBG_TXFD_11_U___RWC QCSR_REG_RW +#define PHYA_TXFD_PHYDBG_TXFD_11_U___POR 0x00000000 +#define PHYA_TXFD_PHYDBG_TXFD_11_U__TXFD_PHYDBG_EVENT_MASK_1_1___POR 0x00000000 +#define PHYA_TXFD_PHYDBG_TXFD_11_U__TXFD_PHYDBG_EVENT_MASK_1_1___M 0xFFFFFFFF +#define PHYA_TXFD_PHYDBG_TXFD_11_U__TXFD_PHYDBG_EVENT_MASK_1_1___S 0 +#define PHYA_TXFD_PHYDBG_TXFD_11_U___M 0xFFFFFFFF +#define PHYA_TXFD_PHYDBG_TXFD_11_U___S 0 + +#define PHYA_TXFD_PHYDBG_TXFD_12_L (0x00390088) +#define PHYA_TXFD_PHYDBG_TXFD_12_L___RWC QCSR_REG_RW +#define PHYA_TXFD_PHYDBG_TXFD_12_L___POR 0x00000000 +#define PHYA_TXFD_PHYDBG_TXFD_12_L__TXFD_PHYDBG_EVENT_MASK_0_2___POR 0x00000000 +#define PHYA_TXFD_PHYDBG_TXFD_12_L__TXFD_PHYDBG_EVENT_MASK_0_2___M 0xFFFFFFFF +#define PHYA_TXFD_PHYDBG_TXFD_12_L__TXFD_PHYDBG_EVENT_MASK_0_2___S 0 +#define PHYA_TXFD_PHYDBG_TXFD_12_L___M 0xFFFFFFFF +#define PHYA_TXFD_PHYDBG_TXFD_12_L___S 0 + +#define PHYA_TXFD_PHYDBG_TXFD_12_U (0x0039008C) +#define PHYA_TXFD_PHYDBG_TXFD_12_U___RWC QCSR_REG_RW +#define PHYA_TXFD_PHYDBG_TXFD_12_U___POR 0x00000000 +#define PHYA_TXFD_PHYDBG_TXFD_12_U__TXFD_PHYDBG_EVENT_MASK_1_2___POR 0x00000000 +#define PHYA_TXFD_PHYDBG_TXFD_12_U__TXFD_PHYDBG_EVENT_MASK_1_2___M 0xFFFFFFFF +#define PHYA_TXFD_PHYDBG_TXFD_12_U__TXFD_PHYDBG_EVENT_MASK_1_2___S 0 +#define PHYA_TXFD_PHYDBG_TXFD_12_U___M 0xFFFFFFFF +#define PHYA_TXFD_PHYDBG_TXFD_12_U___S 0 + +#define PHYA_TXFD_PHYDBG_TXFD_13_L (0x00390090) +#define PHYA_TXFD_PHYDBG_TXFD_13_L___RWC QCSR_REG_RW +#define PHYA_TXFD_PHYDBG_TXFD_13_L___POR 0x00000000 +#define PHYA_TXFD_PHYDBG_TXFD_13_L__TXFD_PHYDBG_EVENT_MASK_0_3___POR 0x00000000 +#define PHYA_TXFD_PHYDBG_TXFD_13_L__TXFD_PHYDBG_EVENT_MASK_0_3___M 0xFFFFFFFF +#define PHYA_TXFD_PHYDBG_TXFD_13_L__TXFD_PHYDBG_EVENT_MASK_0_3___S 0 +#define PHYA_TXFD_PHYDBG_TXFD_13_L___M 0xFFFFFFFF +#define PHYA_TXFD_PHYDBG_TXFD_13_L___S 0 + +#define PHYA_TXFD_PHYDBG_TXFD_13_U (0x00390094) +#define PHYA_TXFD_PHYDBG_TXFD_13_U___RWC QCSR_REG_RW +#define PHYA_TXFD_PHYDBG_TXFD_13_U___POR 0x00000000 +#define PHYA_TXFD_PHYDBG_TXFD_13_U__TXFD_PHYDBG_EVENT_MASK_1_3___POR 0x00000000 +#define PHYA_TXFD_PHYDBG_TXFD_13_U__TXFD_PHYDBG_EVENT_MASK_1_3___M 0xFFFFFFFF +#define PHYA_TXFD_PHYDBG_TXFD_13_U__TXFD_PHYDBG_EVENT_MASK_1_3___S 0 +#define PHYA_TXFD_PHYDBG_TXFD_13_U___M 0xFFFFFFFF +#define PHYA_TXFD_PHYDBG_TXFD_13_U___S 0 + +#define PHYA_TXFD_FTPG_CTRL_0_L (0x00390098) +#define PHYA_TXFD_FTPG_CTRL_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_FTPG_CTRL_0_L___POR 0x00000000 +#define PHYA_TXFD_FTPG_CTRL_0_L__FTPG_RESET___POR 0x0 +#define PHYA_TXFD_FTPG_CTRL_0_L__FTPG_STOP___POR 0x0 +#define PHYA_TXFD_FTPG_CTRL_0_L__FTPG_START___POR 0x0 +#define PHYA_TXFD_FTPG_CTRL_0_L__FTPG_RESET___M 0x00010000 +#define PHYA_TXFD_FTPG_CTRL_0_L__FTPG_RESET___S 16 +#define PHYA_TXFD_FTPG_CTRL_0_L__FTPG_STOP___M 0x00000100 +#define PHYA_TXFD_FTPG_CTRL_0_L__FTPG_STOP___S 8 +#define PHYA_TXFD_FTPG_CTRL_0_L__FTPG_START___M 0x00000001 +#define PHYA_TXFD_FTPG_CTRL_0_L__FTPG_START___S 0 +#define PHYA_TXFD_FTPG_CTRL_0_L___M 0x00010101 +#define PHYA_TXFD_FTPG_CTRL_0_L___S 0 + +#define PHYA_TXFD_FTPG_CTRL_0_U (0x0039009C) +#define PHYA_TXFD_FTPG_CTRL_0_U___RWC QCSR_REG_RW +#define PHYA_TXFD_FTPG_CTRL_0_U___POR 0x00000001 +#define PHYA_TXFD_FTPG_CTRL_0_U__FTPG_PKT_TYPE___POR 0x0 +#define PHYA_TXFD_FTPG_CTRL_0_U__FTPG_AMPDU___POR 0x0 +#define PHYA_TXFD_FTPG_CTRL_0_U__FTPG_REPEAT_COUNT___POR 0x0001 +#define PHYA_TXFD_FTPG_CTRL_0_U__FTPG_PKT_TYPE___M 0x0F000000 +#define PHYA_TXFD_FTPG_CTRL_0_U__FTPG_PKT_TYPE___S 24 +#define PHYA_TXFD_FTPG_CTRL_0_U__FTPG_AMPDU___M 0x00010000 +#define PHYA_TXFD_FTPG_CTRL_0_U__FTPG_AMPDU___S 16 +#define PHYA_TXFD_FTPG_CTRL_0_U__FTPG_REPEAT_COUNT___M 0x0000FFFF +#define PHYA_TXFD_FTPG_CTRL_0_U__FTPG_REPEAT_COUNT___S 0 +#define PHYA_TXFD_FTPG_CTRL_0_U___M 0x0F01FFFF +#define PHYA_TXFD_FTPG_CTRL_0_U___S 0 + +#define PHYA_TXFD_FTPG_CTRL_1_L (0x003900A0) +#define PHYA_TXFD_FTPG_CTRL_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_FTPG_CTRL_1_L___POR 0x64010000 +#define PHYA_TXFD_FTPG_CTRL_1_L__FTPG_MAC_HEADER_LATENCY___POR 0x64 +#define PHYA_TXFD_FTPG_CTRL_1_L__FTPG_NUM_USERS___POR 0x01 +#define PHYA_TXFD_FTPG_CTRL_1_L__FTPG_MODE___POR 0x0 +#define PHYA_TXFD_FTPG_CTRL_1_L__FTPG_PAYLOAD_TYPE___POR 0x0 +#define PHYA_TXFD_FTPG_CTRL_1_L__FTPG_MAC_HEADER_LATENCY___M 0xFF000000 +#define PHYA_TXFD_FTPG_CTRL_1_L__FTPG_MAC_HEADER_LATENCY___S 24 +#define PHYA_TXFD_FTPG_CTRL_1_L__FTPG_NUM_USERS___M 0x007F0000 +#define PHYA_TXFD_FTPG_CTRL_1_L__FTPG_NUM_USERS___S 16 +#define PHYA_TXFD_FTPG_CTRL_1_L__FTPG_MODE___M 0x00000100 +#define PHYA_TXFD_FTPG_CTRL_1_L__FTPG_MODE___S 8 +#define PHYA_TXFD_FTPG_CTRL_1_L__FTPG_PAYLOAD_TYPE___M 0x00000003 +#define PHYA_TXFD_FTPG_CTRL_1_L__FTPG_PAYLOAD_TYPE___S 0 +#define PHYA_TXFD_FTPG_CTRL_1_L___M 0xFF7F0103 +#define PHYA_TXFD_FTPG_CTRL_1_L___S 0 + +#define PHYA_TXFD_FTPG_CTRL_1_U (0x003900A4) +#define PHYA_TXFD_FTPG_CTRL_1_U___RWC QCSR_REG_RW +#define PHYA_TXFD_FTPG_CTRL_1_U___POR 0x0064000A +#define PHYA_TXFD_FTPG_CTRL_1_U__FTPG_DELIMITER_MPDU_LENGTH___POR 0x0064 +#define PHYA_TXFD_FTPG_CTRL_1_U__FTPG_MAC_DATA_LATENCY___POR 0x0A +#define PHYA_TXFD_FTPG_CTRL_1_U__FTPG_DELIMITER_MPDU_LENGTH___M 0xFFFF0000 +#define PHYA_TXFD_FTPG_CTRL_1_U__FTPG_DELIMITER_MPDU_LENGTH___S 16 +#define PHYA_TXFD_FTPG_CTRL_1_U__FTPG_MAC_DATA_LATENCY___M 0x0000003F +#define PHYA_TXFD_FTPG_CTRL_1_U__FTPG_MAC_DATA_LATENCY___S 0 +#define PHYA_TXFD_FTPG_CTRL_1_U___M 0xFFFF003F +#define PHYA_TXFD_FTPG_CTRL_1_U___S 0 + +#define PHYA_TXFD_FTPG_CTRL_2_L (0x003900A8) +#define PHYA_TXFD_FTPG_CTRL_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_FTPG_CTRL_2_L___POR 0x00000001 +#define PHYA_TXFD_FTPG_CTRL_2_L__FTPG_INTER_PACKET_TRIGGER___POR 0x1 +#define PHYA_TXFD_FTPG_CTRL_2_L__FTPG_INTER_PACKET_TRIGGER___M 0x00000001 +#define PHYA_TXFD_FTPG_CTRL_2_L__FTPG_INTER_PACKET_TRIGGER___S 0 +#define PHYA_TXFD_FTPG_CTRL_2_L___M 0x00000001 +#define PHYA_TXFD_FTPG_CTRL_2_L___S 0 + +#define PHYA_TXFD_FTPG_CTRL_2_U (0x003900AC) +#define PHYA_TXFD_FTPG_CTRL_2_U___RWC QCSR_REG_RW +#define PHYA_TXFD_FTPG_CTRL_2_U___POR 0x00000FA0 +#define PHYA_TXFD_FTPG_CTRL_2_U__FTPG_INTER_PACKET_DELAY___POR 0x00000FA0 +#define PHYA_TXFD_FTPG_CTRL_2_U__FTPG_INTER_PACKET_DELAY___M 0xFFFFFFFF +#define PHYA_TXFD_FTPG_CTRL_2_U__FTPG_INTER_PACKET_DELAY___S 0 +#define PHYA_TXFD_FTPG_CTRL_2_U___M 0xFFFFFFFF +#define PHYA_TXFD_FTPG_CTRL_2_U___S 0 + +#define PHYA_TXFD_FTPG_CTRL_3_L (0x003900B0) +#define PHYA_TXFD_FTPG_CTRL_3_L___RWC QCSR_REG_RW +#define PHYA_TXFD_FTPG_CTRL_3_L___POR 0x00000280 +#define PHYA_TXFD_FTPG_CTRL_3_L__FTPG_PRE_PHY_TO_PHY_DESC_DELAY___POR 0x0280 +#define PHYA_TXFD_FTPG_CTRL_3_L__FTPG_PRE_PHY_TO_PHY_DESC_DELAY___M 0x0000FFFF +#define PHYA_TXFD_FTPG_CTRL_3_L__FTPG_PRE_PHY_TO_PHY_DESC_DELAY___S 0 +#define PHYA_TXFD_FTPG_CTRL_3_L___M 0x0000FFFF +#define PHYA_TXFD_FTPG_CTRL_3_L___S 0 + +#define PHYA_TXFD_FTPG_CTRL_3_U (0x003900B4) +#define PHYA_TXFD_FTPG_CTRL_3_U___RWC QCSR_REG_RW +#define PHYA_TXFD_FTPG_CTRL_3_U___POR 0x4E790001 +#define PHYA_TXFD_FTPG_CTRL_3_U__FTPG_EOF_DELIMITER___POR 0x4E790001 +#define PHYA_TXFD_FTPG_CTRL_3_U__FTPG_EOF_DELIMITER___M 0xFFFFFFFF +#define PHYA_TXFD_FTPG_CTRL_3_U__FTPG_EOF_DELIMITER___S 0 +#define PHYA_TXFD_FTPG_CTRL_3_U___M 0xFFFFFFFF +#define PHYA_TXFD_FTPG_CTRL_3_U___S 0 + +#define PHYA_TXFD_FTPG_CTRL_4_L (0x003900B8) +#define PHYA_TXFD_FTPG_CTRL_4_L___RWC QCSR_REG_RW +#define PHYA_TXFD_FTPG_CTRL_4_L___POR 0x00000000 +#define PHYA_TXFD_FTPG_CTRL_4_L__FTPG_EOF_PAD___POR 0x00000000 +#define PHYA_TXFD_FTPG_CTRL_4_L__FTPG_EOF_PAD___M 0xFFFFFFFF +#define PHYA_TXFD_FTPG_CTRL_4_L__FTPG_EOF_PAD___S 0 +#define PHYA_TXFD_FTPG_CTRL_4_L___M 0xFFFFFFFF +#define PHYA_TXFD_FTPG_CTRL_4_L___S 0 + +#define PHYA_TXFD_FTPG_CTRL_4_U (0x003900BC) +#define PHYA_TXFD_FTPG_CTRL_4_U___RWC QCSR_REG_RW +#define PHYA_TXFD_FTPG_CTRL_4_U___POR 0xDEADBEEF +#define PHYA_TXFD_FTPG_CTRL_4_U__FTPG_FIXED_PAYLOAD___POR 0xDEADBEEF +#define PHYA_TXFD_FTPG_CTRL_4_U__FTPG_FIXED_PAYLOAD___M 0xFFFFFFFF +#define PHYA_TXFD_FTPG_CTRL_4_U__FTPG_FIXED_PAYLOAD___S 0 +#define PHYA_TXFD_FTPG_CTRL_4_U___M 0xFFFFFFFF +#define PHYA_TXFD_FTPG_CTRL_4_U___S 0 + +#define PHYA_TXFD_FTPG_CTRL_5_L (0x003900C0) +#define PHYA_TXFD_FTPG_CTRL_5_L___RWC QCSR_REG_RW +#define PHYA_TXFD_FTPG_CTRL_5_L___POR 0x00000000 +#define PHYA_TXFD_FTPG_CTRL_5_L__FTPG_RSVD1___POR 0x00000000 +#define PHYA_TXFD_FTPG_CTRL_5_L__FTPG_RSVD1___M 0xFFFFFFFF +#define PHYA_TXFD_FTPG_CTRL_5_L__FTPG_RSVD1___S 0 +#define PHYA_TXFD_FTPG_CTRL_5_L___M 0xFFFFFFFF +#define PHYA_TXFD_FTPG_CTRL_5_L___S 0 + +#define PHYA_TXFD_FTPG_CTRL_5_U (0x003900C4) +#define PHYA_TXFD_FTPG_CTRL_5_U___RWC QCSR_REG_RW +#define PHYA_TXFD_FTPG_CTRL_5_U___POR 0x00000000 +#define PHYA_TXFD_FTPG_CTRL_5_U__FTPG_RSVD2___POR 0x00000000 +#define PHYA_TXFD_FTPG_CTRL_5_U__FTPG_RSVD2___M 0xFFFFFFFF +#define PHYA_TXFD_FTPG_CTRL_5_U__FTPG_RSVD2___S 0 +#define PHYA_TXFD_FTPG_CTRL_5_U___M 0xFFFFFFFF +#define PHYA_TXFD_FTPG_CTRL_5_U___S 0 + +#define PHYA_TXFD_FTPG_CTRL_6_L (0x003900C8) +#define PHYA_TXFD_FTPG_CTRL_6_L___RWC QCSR_REG_RW +#define PHYA_TXFD_FTPG_CTRL_6_L___POR 0x00000000 +#define PHYA_TXFD_FTPG_CTRL_6_L__FTPG_RSVD3___POR 0x00000000 +#define PHYA_TXFD_FTPG_CTRL_6_L__FTPG_RSVD3___M 0xFFFFFFFF +#define PHYA_TXFD_FTPG_CTRL_6_L__FTPG_RSVD3___S 0 +#define PHYA_TXFD_FTPG_CTRL_6_L___M 0xFFFFFFFF +#define PHYA_TXFD_FTPG_CTRL_6_L___S 0 + +#define PHYA_TXFD_FTPG_CTRL_6_U (0x003900CC) +#define PHYA_TXFD_FTPG_CTRL_6_U___RWC QCSR_REG_RW +#define PHYA_TXFD_FTPG_CTRL_6_U___POR 0x00000000 +#define PHYA_TXFD_FTPG_CTRL_6_U__FTPG_RSVD4___POR 0x00000000 +#define PHYA_TXFD_FTPG_CTRL_6_U__FTPG_RSVD4___M 0xFFFFFFFF +#define PHYA_TXFD_FTPG_CTRL_6_U__FTPG_RSVD4___S 0 +#define PHYA_TXFD_FTPG_CTRL_6_U___M 0xFFFFFFFF +#define PHYA_TXFD_FTPG_CTRL_6_U___S 0 + +#define PHYA_TXFD_FTPG_STATUS_L (0x003900D0) +#define PHYA_TXFD_FTPG_STATUS_L___RWC QCSR_REG_RO +#define PHYA_TXFD_FTPG_STATUS_L___POR 0x00000000 +#define PHYA_TXFD_FTPG_STATUS_L__FTPG_PACKET_INSTANCE___POR 0x0000 +#define PHYA_TXFD_FTPG_STATUS_L__FTPG_PACKET_INSTANCE___M 0x0000FFFF +#define PHYA_TXFD_FTPG_STATUS_L__FTPG_PACKET_INSTANCE___S 0 +#define PHYA_TXFD_FTPG_STATUS_L___M 0x0000FFFF +#define PHYA_TXFD_FTPG_STATUS_L___S 0 + +#define PHYA_TXFD_FTPG_USER_CFG_L (0x003900D8) +#define PHYA_TXFD_FTPG_USER_CFG_L___RWC QCSR_REG_RW +#define PHYA_TXFD_FTPG_USER_CFG_L___POR 0x00000000 +#define PHYA_TXFD_FTPG_USER_CFG_L__USER_ADDR_OFFSET___POR 0x0000 +#define PHYA_TXFD_FTPG_USER_CFG_L__USER_ADDR_OFFSET___M 0x00001FFF +#define PHYA_TXFD_FTPG_USER_CFG_L__USER_ADDR_OFFSET___S 0 +#define PHYA_TXFD_FTPG_USER_CFG_L___M 0x00001FFF +#define PHYA_TXFD_FTPG_USER_CFG_L___S 0 + +#define PHYA_TXFD_FTPG_USER_CFG_U (0x003900DC) +#define PHYA_TXFD_FTPG_USER_CFG_U___RWC QCSR_REG_RW +#define PHYA_TXFD_FTPG_USER_CFG_U___POR 0x00000000 +#define PHYA_TXFD_FTPG_USER_CFG_U__USER_PAYLOAD_LENGTH___POR 0x000000 +#define PHYA_TXFD_FTPG_USER_CFG_U__USER_PAYLOAD_LENGTH___M 0x007FFFFF +#define PHYA_TXFD_FTPG_USER_CFG_U__USER_PAYLOAD_LENGTH___S 0 +#define PHYA_TXFD_FTPG_USER_CFG_U___M 0x007FFFFF +#define PHYA_TXFD_FTPG_USER_CFG_U___S 0 + +#define PHYA_TXFD_PEF_COEFF_BW_OSR_HC_L_n(n) (0x003902D8+0x8*(n)) +#define PHYA_TXFD_PEF_COEFF_BW_OSR_HC_L_n_nMIN 0 +#define PHYA_TXFD_PEF_COEFF_BW_OSR_HC_L_n_nMAX 0 +#define PHYA_TXFD_PEF_COEFF_BW_OSR_HC_L_n_ELEM 1 +#define PHYA_TXFD_PEF_COEFF_BW_OSR_HC_L_n___RWC QCSR_REG_RW +#define PHYA_TXFD_PEF_COEFF_BW_OSR_HC_L_n___POR 0x00000000 +#define PHYA_TXFD_PEF_COEFF_BW_OSR_HC_L_n__PEF_COEFF_BW_OSR_HC_0___POR 0x00000000 +#define PHYA_TXFD_PEF_COEFF_BW_OSR_HC_L_n__PEF_COEFF_BW_OSR_HC_0___M 0xFFFFFFFF +#define PHYA_TXFD_PEF_COEFF_BW_OSR_HC_L_n__PEF_COEFF_BW_OSR_HC_0___S 0 +#define PHYA_TXFD_PEF_COEFF_BW_OSR_HC_L_n___M 0xFFFFFFFF +#define PHYA_TXFD_PEF_COEFF_BW_OSR_HC_L_n___S 0 +#define PHYA_TXFD_PEF_COEFF_BW_OSR_HC_L_0 (0x003902D8) +#define PHYA_TXFD_PEF_COEFF_BW_OSR_HC_L_0___RWC QCSR_REG_RW +#define PHYA_TXFD_PEF_COEFF_BW_OSR_HC_L_0__PEF_COEFF_BW_OSR_HC_0___M 0xFFFFFFFF +#define PHYA_TXFD_PEF_COEFF_BW_OSR_HC_L_0__PEF_COEFF_BW_OSR_HC_0___S 0 + +#define PHYA_TXFD_PEF_COEFF_BW_OSR_HC_U_n(n) (0x003902DC+0x8*(n)) +#define PHYA_TXFD_PEF_COEFF_BW_OSR_HC_U_n_nMIN 0 +#define PHYA_TXFD_PEF_COEFF_BW_OSR_HC_U_n_nMAX 0 +#define PHYA_TXFD_PEF_COEFF_BW_OSR_HC_U_n_ELEM 1 +#define PHYA_TXFD_PEF_COEFF_BW_OSR_HC_U_n___RWC QCSR_REG_RW +#define PHYA_TXFD_PEF_COEFF_BW_OSR_HC_U_n___POR 0x00000000 +#define PHYA_TXFD_PEF_COEFF_BW_OSR_HC_U_n__PEF_COEFF_BW_OSR_HC_1___POR 0x00000000 +#define PHYA_TXFD_PEF_COEFF_BW_OSR_HC_U_n__PEF_COEFF_BW_OSR_HC_1___M 0xFFFFFFFF +#define PHYA_TXFD_PEF_COEFF_BW_OSR_HC_U_n__PEF_COEFF_BW_OSR_HC_1___S 0 +#define PHYA_TXFD_PEF_COEFF_BW_OSR_HC_U_n___M 0xFFFFFFFF +#define PHYA_TXFD_PEF_COEFF_BW_OSR_HC_U_n___S 0 +#define PHYA_TXFD_PEF_COEFF_BW_OSR_HC_U_0 (0x003902DC) +#define PHYA_TXFD_PEF_COEFF_BW_OSR_HC_U_0___RWC QCSR_REG_RW +#define PHYA_TXFD_PEF_COEFF_BW_OSR_HC_U_0__PEF_COEFF_BW_OSR_HC_1___M 0xFFFFFFFF +#define PHYA_TXFD_PEF_COEFF_BW_OSR_HC_U_0__PEF_COEFF_BW_OSR_HC_1___S 0 + +#define PHYA_TXFD_TXB_CFG_0_L (0x003915D8) +#define PHYA_TXFD_TXB_CFG_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_TXB_CFG_0_L___POR 0x00000000 +#define PHYA_TXFD_TXB_CFG_0_L__TXCCK_TXFIR_JAPAN_CCK___POR 0x0 +#define PHYA_TXFD_TXB_CFG_0_L__TXCCK_TX_DAC_SCALE_CCK___POR 0x0 +#define PHYA_TXFD_TXB_CFG_0_L__TXCCK_ALLOW_1MBPS_SHORT___POR 0x0 +#define PHYA_TXFD_TXB_CFG_0_L__TXCCK_TXFIR_JAPAN_CCK___M 0x00010000 +#define PHYA_TXFD_TXB_CFG_0_L__TXCCK_TXFIR_JAPAN_CCK___S 16 +#define PHYA_TXFD_TXB_CFG_0_L__TXCCK_TX_DAC_SCALE_CCK___M 0x00000300 +#define PHYA_TXFD_TXB_CFG_0_L__TXCCK_TX_DAC_SCALE_CCK___S 8 +#define PHYA_TXFD_TXB_CFG_0_L__TXCCK_ALLOW_1MBPS_SHORT___M 0x00000001 +#define PHYA_TXFD_TXB_CFG_0_L__TXCCK_ALLOW_1MBPS_SHORT___S 0 +#define PHYA_TXFD_TXB_CFG_0_L___M 0x00010301 +#define PHYA_TXFD_TXB_CFG_0_L___S 0 + +#define PHYA_TXFD_TXB_CFG_10_L (0x003915E0) +#define PHYA_TXFD_TXB_CFG_10_L___RWC QCSR_REG_RW +#define PHYA_TXFD_TXB_CFG_10_L___POR 0x00000000 +#define PHYA_TXFD_TXB_CFG_10_L__TXCCK_TXFIR_COEFF_3_0___POR 0x00 +#define PHYA_TXFD_TXB_CFG_10_L__TXCCK_TXFIR_COEFF_2_0___POR 0x00 +#define PHYA_TXFD_TXB_CFG_10_L__TXCCK_TXFIR_COEFF_1_0___POR 0x00 +#define PHYA_TXFD_TXB_CFG_10_L__TXCCK_TXFIR_COEFF_0_0___POR 0x00 +#define PHYA_TXFD_TXB_CFG_10_L__TXCCK_TXFIR_COEFF_3_0___M 0xFF000000 +#define PHYA_TXFD_TXB_CFG_10_L__TXCCK_TXFIR_COEFF_3_0___S 24 +#define PHYA_TXFD_TXB_CFG_10_L__TXCCK_TXFIR_COEFF_2_0___M 0x00FF0000 +#define PHYA_TXFD_TXB_CFG_10_L__TXCCK_TXFIR_COEFF_2_0___S 16 +#define PHYA_TXFD_TXB_CFG_10_L__TXCCK_TXFIR_COEFF_1_0___M 0x0000FF00 +#define PHYA_TXFD_TXB_CFG_10_L__TXCCK_TXFIR_COEFF_1_0___S 8 +#define PHYA_TXFD_TXB_CFG_10_L__TXCCK_TXFIR_COEFF_0_0___M 0x000000FF +#define PHYA_TXFD_TXB_CFG_10_L__TXCCK_TXFIR_COEFF_0_0___S 0 +#define PHYA_TXFD_TXB_CFG_10_L___M 0xFFFFFFFF +#define PHYA_TXFD_TXB_CFG_10_L___S 0 + +#define PHYA_TXFD_TXB_CFG_10_U (0x003915E4) +#define PHYA_TXFD_TXB_CFG_10_U___RWC QCSR_REG_RW +#define PHYA_TXFD_TXB_CFG_10_U___POR 0x00000000 +#define PHYA_TXFD_TXB_CFG_10_U__TXCCK_TXFIR_COEFF_7_0___POR 0x00 +#define PHYA_TXFD_TXB_CFG_10_U__TXCCK_TXFIR_COEFF_6_0___POR 0x00 +#define PHYA_TXFD_TXB_CFG_10_U__TXCCK_TXFIR_COEFF_5_0___POR 0x00 +#define PHYA_TXFD_TXB_CFG_10_U__TXCCK_TXFIR_COEFF_4_0___POR 0x00 +#define PHYA_TXFD_TXB_CFG_10_U__TXCCK_TXFIR_COEFF_7_0___M 0xFF000000 +#define PHYA_TXFD_TXB_CFG_10_U__TXCCK_TXFIR_COEFF_7_0___S 24 +#define PHYA_TXFD_TXB_CFG_10_U__TXCCK_TXFIR_COEFF_6_0___M 0x00FF0000 +#define PHYA_TXFD_TXB_CFG_10_U__TXCCK_TXFIR_COEFF_6_0___S 16 +#define PHYA_TXFD_TXB_CFG_10_U__TXCCK_TXFIR_COEFF_5_0___M 0x0000FF00 +#define PHYA_TXFD_TXB_CFG_10_U__TXCCK_TXFIR_COEFF_5_0___S 8 +#define PHYA_TXFD_TXB_CFG_10_U__TXCCK_TXFIR_COEFF_4_0___M 0x000000FF +#define PHYA_TXFD_TXB_CFG_10_U__TXCCK_TXFIR_COEFF_4_0___S 0 +#define PHYA_TXFD_TXB_CFG_10_U___M 0xFFFFFFFF +#define PHYA_TXFD_TXB_CFG_10_U___S 0 + +#define PHYA_TXFD_TXB_CFG_11_L (0x003915E8) +#define PHYA_TXFD_TXB_CFG_11_L___RWC QCSR_REG_RW +#define PHYA_TXFD_TXB_CFG_11_L___POR 0xEEB74ADC +#define PHYA_TXFD_TXB_CFG_11_L__TXCCK_TXFIR_COEFF_3_1___POR 0xEE +#define PHYA_TXFD_TXB_CFG_11_L__TXCCK_TXFIR_COEFF_2_1___POR 0xB7 +#define PHYA_TXFD_TXB_CFG_11_L__TXCCK_TXFIR_COEFF_1_1___POR 0x4A +#define PHYA_TXFD_TXB_CFG_11_L__TXCCK_TXFIR_COEFF_0_1___POR 0xDC +#define PHYA_TXFD_TXB_CFG_11_L__TXCCK_TXFIR_COEFF_3_1___M 0xFF000000 +#define PHYA_TXFD_TXB_CFG_11_L__TXCCK_TXFIR_COEFF_3_1___S 24 +#define PHYA_TXFD_TXB_CFG_11_L__TXCCK_TXFIR_COEFF_2_1___M 0x00FF0000 +#define PHYA_TXFD_TXB_CFG_11_L__TXCCK_TXFIR_COEFF_2_1___S 16 +#define PHYA_TXFD_TXB_CFG_11_L__TXCCK_TXFIR_COEFF_1_1___M 0x0000FF00 +#define PHYA_TXFD_TXB_CFG_11_L__TXCCK_TXFIR_COEFF_1_1___S 8 +#define PHYA_TXFD_TXB_CFG_11_L__TXCCK_TXFIR_COEFF_0_1___M 0x000000FF +#define PHYA_TXFD_TXB_CFG_11_L__TXCCK_TXFIR_COEFF_0_1___S 0 +#define PHYA_TXFD_TXB_CFG_11_L___M 0xFFFFFFFF +#define PHYA_TXFD_TXB_CFG_11_L___S 0 + +#define PHYA_TXFD_TXB_CFG_11_U (0x003915EC) +#define PHYA_TXFD_TXB_CFG_11_U___RWC QCSR_REG_RW +#define PHYA_TXFD_TXB_CFG_11_U___POR 0x00000000 +#define PHYA_TXFD_TXB_CFG_11_U__TXCCK_TXFIR_COEFF_7_1___POR 0x00 +#define PHYA_TXFD_TXB_CFG_11_U__TXCCK_TXFIR_COEFF_6_1___POR 0x00 +#define PHYA_TXFD_TXB_CFG_11_U__TXCCK_TXFIR_COEFF_5_1___POR 0x00 +#define PHYA_TXFD_TXB_CFG_11_U__TXCCK_TXFIR_COEFF_4_1___POR 0x00 +#define PHYA_TXFD_TXB_CFG_11_U__TXCCK_TXFIR_COEFF_7_1___M 0xFF000000 +#define PHYA_TXFD_TXB_CFG_11_U__TXCCK_TXFIR_COEFF_7_1___S 24 +#define PHYA_TXFD_TXB_CFG_11_U__TXCCK_TXFIR_COEFF_6_1___M 0x00FF0000 +#define PHYA_TXFD_TXB_CFG_11_U__TXCCK_TXFIR_COEFF_6_1___S 16 +#define PHYA_TXFD_TXB_CFG_11_U__TXCCK_TXFIR_COEFF_5_1___M 0x0000FF00 +#define PHYA_TXFD_TXB_CFG_11_U__TXCCK_TXFIR_COEFF_5_1___S 8 +#define PHYA_TXFD_TXB_CFG_11_U__TXCCK_TXFIR_COEFF_4_1___M 0x000000FF +#define PHYA_TXFD_TXB_CFG_11_U__TXCCK_TXFIR_COEFF_4_1___S 0 +#define PHYA_TXFD_TXB_CFG_11_U___M 0xFFFFFFFF +#define PHYA_TXFD_TXB_CFG_11_U___S 0 + +#define PHYA_TXFD_TXB_CFG_12_L (0x003915F0) +#define PHYA_TXFD_TXB_CFG_12_L___RWC QCSR_REG_RW +#define PHYA_TXFD_TXB_CFG_12_L___POR 0x00000000 +#define PHYA_TXFD_TXB_CFG_12_L__TXCCK_TXFIR_COEFF_3_2___POR 0x00 +#define PHYA_TXFD_TXB_CFG_12_L__TXCCK_TXFIR_COEFF_2_2___POR 0x00 +#define PHYA_TXFD_TXB_CFG_12_L__TXCCK_TXFIR_COEFF_1_2___POR 0x00 +#define PHYA_TXFD_TXB_CFG_12_L__TXCCK_TXFIR_COEFF_0_2___POR 0x00 +#define PHYA_TXFD_TXB_CFG_12_L__TXCCK_TXFIR_COEFF_3_2___M 0xFF000000 +#define PHYA_TXFD_TXB_CFG_12_L__TXCCK_TXFIR_COEFF_3_2___S 24 +#define PHYA_TXFD_TXB_CFG_12_L__TXCCK_TXFIR_COEFF_2_2___M 0x00FF0000 +#define PHYA_TXFD_TXB_CFG_12_L__TXCCK_TXFIR_COEFF_2_2___S 16 +#define PHYA_TXFD_TXB_CFG_12_L__TXCCK_TXFIR_COEFF_1_2___M 0x0000FF00 +#define PHYA_TXFD_TXB_CFG_12_L__TXCCK_TXFIR_COEFF_1_2___S 8 +#define PHYA_TXFD_TXB_CFG_12_L__TXCCK_TXFIR_COEFF_0_2___M 0x000000FF +#define PHYA_TXFD_TXB_CFG_12_L__TXCCK_TXFIR_COEFF_0_2___S 0 +#define PHYA_TXFD_TXB_CFG_12_L___M 0xFFFFFFFF +#define PHYA_TXFD_TXB_CFG_12_L___S 0 + +#define PHYA_TXFD_TXB_CFG_12_U (0x003915F4) +#define PHYA_TXFD_TXB_CFG_12_U___RWC QCSR_REG_RW +#define PHYA_TXFD_TXB_CFG_12_U___POR 0x00000000 +#define PHYA_TXFD_TXB_CFG_12_U__TXCCK_TXFIR_COEFF_7_2___POR 0x00 +#define PHYA_TXFD_TXB_CFG_12_U__TXCCK_TXFIR_COEFF_6_2___POR 0x00 +#define PHYA_TXFD_TXB_CFG_12_U__TXCCK_TXFIR_COEFF_5_2___POR 0x00 +#define PHYA_TXFD_TXB_CFG_12_U__TXCCK_TXFIR_COEFF_4_2___POR 0x00 +#define PHYA_TXFD_TXB_CFG_12_U__TXCCK_TXFIR_COEFF_7_2___M 0xFF000000 +#define PHYA_TXFD_TXB_CFG_12_U__TXCCK_TXFIR_COEFF_7_2___S 24 +#define PHYA_TXFD_TXB_CFG_12_U__TXCCK_TXFIR_COEFF_6_2___M 0x00FF0000 +#define PHYA_TXFD_TXB_CFG_12_U__TXCCK_TXFIR_COEFF_6_2___S 16 +#define PHYA_TXFD_TXB_CFG_12_U__TXCCK_TXFIR_COEFF_5_2___M 0x0000FF00 +#define PHYA_TXFD_TXB_CFG_12_U__TXCCK_TXFIR_COEFF_5_2___S 8 +#define PHYA_TXFD_TXB_CFG_12_U__TXCCK_TXFIR_COEFF_4_2___M 0x000000FF +#define PHYA_TXFD_TXB_CFG_12_U__TXCCK_TXFIR_COEFF_4_2___S 0 +#define PHYA_TXFD_TXB_CFG_12_U___M 0xFFFFFFFF +#define PHYA_TXFD_TXB_CFG_12_U___S 0 + +#define PHYA_TXFD_TXB_CFG_2_L (0x003915F8) +#define PHYA_TXFD_TXB_CFG_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_TXB_CFG_2_L___POR 0x00015303 +#define PHYA_TXFD_TXB_CFG_2_L__BT_BREAK_CCK_EN___POR 0x0 +#define PHYA_TXFD_TXB_CFG_2_L__ENABLE_POWER_OPTIM_SM___POR 0x1 +#define PHYA_TXFD_TXB_CFG_2_L__TXCCK_PACKET_END_DELAY___POR 0x53 +#define PHYA_TXFD_TXB_CFG_2_L__TXCCK_TXFIR_COEFF_SEL___POR 0x3 +#define PHYA_TXFD_TXB_CFG_2_L__BT_BREAK_CCK_EN___M 0x01000000 +#define PHYA_TXFD_TXB_CFG_2_L__BT_BREAK_CCK_EN___S 24 +#define PHYA_TXFD_TXB_CFG_2_L__ENABLE_POWER_OPTIM_SM___M 0x00010000 +#define PHYA_TXFD_TXB_CFG_2_L__ENABLE_POWER_OPTIM_SM___S 16 +#define PHYA_TXFD_TXB_CFG_2_L__TXCCK_PACKET_END_DELAY___M 0x0000FF00 +#define PHYA_TXFD_TXB_CFG_2_L__TXCCK_PACKET_END_DELAY___S 8 +#define PHYA_TXFD_TXB_CFG_2_L__TXCCK_TXFIR_COEFF_SEL___M 0x0000000F +#define PHYA_TXFD_TXB_CFG_2_L__TXCCK_TXFIR_COEFF_SEL___S 0 +#define PHYA_TXFD_TXB_CFG_2_L___M 0x0101FF0F +#define PHYA_TXFD_TXB_CFG_2_L___S 0 + +#define PHYA_TXFD_TXB_CFG_2_U (0x003915FC) +#define PHYA_TXFD_TXB_CFG_2_U___RWC QCSR_REG_RW +#define PHYA_TXFD_TXB_CFG_2_U___POR 0x00000000 +#define PHYA_TXFD_TXB_CFG_2_U__TXCCK_USE_SCRAMBLER_SEED___POR 0x0 +#define PHYA_TXFD_TXB_CFG_2_U__TXCCK_DISABLE_SCRAMBLER___POR 0x0 +#define PHYA_TXFD_TXB_CFG_2_U__TXCCK_USE_SCRAMBLER_SEED___M 0x00000100 +#define PHYA_TXFD_TXB_CFG_2_U__TXCCK_USE_SCRAMBLER_SEED___S 8 +#define PHYA_TXFD_TXB_CFG_2_U__TXCCK_DISABLE_SCRAMBLER___M 0x00000001 +#define PHYA_TXFD_TXB_CFG_2_U__TXCCK_DISABLE_SCRAMBLER___S 0 +#define PHYA_TXFD_TXB_CFG_2_U___M 0x00000101 +#define PHYA_TXFD_TXB_CFG_2_U___S 0 + +#define PHYA_TXFD_TXB_CFG_3_L (0x00391600) +#define PHYA_TXFD_TXB_CFG_3_L___RWC QCSR_REG_RW +#define PHYA_TXFD_TXB_CFG_3_L___POR 0x00000064 +#define PHYA_TXFD_TXB_CFG_3_L__TXCCK_LSIGB_REQ_COUNTER___POR 0x00000064 +#define PHYA_TXFD_TXB_CFG_3_L__TXCCK_LSIGB_REQ_COUNTER___M 0xFFFFFFFF +#define PHYA_TXFD_TXB_CFG_3_L__TXCCK_LSIGB_REQ_COUNTER___S 0 +#define PHYA_TXFD_TXB_CFG_3_L___M 0xFFFFFFFF +#define PHYA_TXFD_TXB_CFG_3_L___S 0 + +#define PHYA_TXFD_TXB_CFG_3_U (0x00391604) +#define PHYA_TXFD_TXB_CFG_3_U___RWC QCSR_REG_RW +#define PHYA_TXFD_TXB_CFG_3_U___POR 0x000000C8 +#define PHYA_TXFD_TXB_CFG_3_U__TXCCK_SERVICE_REQ_COUNTER___POR 0x000000C8 +#define PHYA_TXFD_TXB_CFG_3_U__TXCCK_SERVICE_REQ_COUNTER___M 0xFFFFFFFF +#define PHYA_TXFD_TXB_CFG_3_U__TXCCK_SERVICE_REQ_COUNTER___S 0 +#define PHYA_TXFD_TXB_CFG_3_U___M 0xFFFFFFFF +#define PHYA_TXFD_TXB_CFG_3_U___S 0 + +#define PHYA_TXFD_TXB_CFG_4_L (0x00391608) +#define PHYA_TXFD_TXB_CFG_4_L___RWC QCSR_REG_RW +#define PHYA_TXFD_TXB_CFG_4_L___POR 0x00000096 +#define PHYA_TXFD_TXB_CFG_4_L__TXCCK_USER_DESC_REQ_COUNTER___POR 0x00000096 +#define PHYA_TXFD_TXB_CFG_4_L__TXCCK_USER_DESC_REQ_COUNTER___M 0xFFFFFFFF +#define PHYA_TXFD_TXB_CFG_4_L__TXCCK_USER_DESC_REQ_COUNTER___S 0 +#define PHYA_TXFD_TXB_CFG_4_L___M 0xFFFFFFFF +#define PHYA_TXFD_TXB_CFG_4_L___S 0 + +#define PHYA_TXFD_WUR_CFG_0_L (0x00391610) +#define PHYA_TXFD_WUR_CFG_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_0_L___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_0_L__WUR_BPSK_0___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_0_L__WUR_BPSK_0___M 0xFFFFFFFF +#define PHYA_TXFD_WUR_CFG_0_L__WUR_BPSK_0___S 0 +#define PHYA_TXFD_WUR_CFG_0_L___M 0xFFFFFFFF +#define PHYA_TXFD_WUR_CFG_0_L___S 0 + +#define PHYA_TXFD_WUR_CFG_0_U (0x00391614) +#define PHYA_TXFD_WUR_CFG_0_U___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_0_U___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_0_U__WUR_BPSK_1___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_0_U__WUR_BPSK_1___M 0xFFFFFFFF +#define PHYA_TXFD_WUR_CFG_0_U__WUR_BPSK_1___S 0 +#define PHYA_TXFD_WUR_CFG_0_U___M 0xFFFFFFFF +#define PHYA_TXFD_WUR_CFG_0_U___S 0 + +#define PHYA_TXFD_WUR_CFG_1_L (0x00391618) +#define PHYA_TXFD_WUR_CFG_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_1_L___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_1_L__WUR_W_PATTERN___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_1_L__WUR_W_PATTERN___M 0xFFFFFFFF +#define PHYA_TXFD_WUR_CFG_1_L__WUR_W_PATTERN___S 0 +#define PHYA_TXFD_WUR_CFG_1_L___M 0xFFFFFFFF +#define PHYA_TXFD_WUR_CFG_1_L___S 0 + +#define PHYA_TXFD_WUR_CFG_20_L (0x00391620) +#define PHYA_TXFD_WUR_CFG_20_L___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_20_L___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_20_L__WUR_ON_I_COEFF_4US_1_0___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_20_L__WUR_ON_I_COEFF_4US_0_0___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_20_L__WUR_ON_I_COEFF_4US_1_0___M 0x3FFF0000 +#define PHYA_TXFD_WUR_CFG_20_L__WUR_ON_I_COEFF_4US_1_0___S 16 +#define PHYA_TXFD_WUR_CFG_20_L__WUR_ON_I_COEFF_4US_0_0___M 0x00003FFF +#define PHYA_TXFD_WUR_CFG_20_L__WUR_ON_I_COEFF_4US_0_0___S 0 +#define PHYA_TXFD_WUR_CFG_20_L___M 0x3FFF3FFF +#define PHYA_TXFD_WUR_CFG_20_L___S 0 + +#define PHYA_TXFD_WUR_CFG_20_U (0x00391624) +#define PHYA_TXFD_WUR_CFG_20_U___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_20_U___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_20_U__WUR_ON_I_COEFF_4US_3_0___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_20_U__WUR_ON_I_COEFF_4US_2_0___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_20_U__WUR_ON_I_COEFF_4US_3_0___M 0x3FFF0000 +#define PHYA_TXFD_WUR_CFG_20_U__WUR_ON_I_COEFF_4US_3_0___S 16 +#define PHYA_TXFD_WUR_CFG_20_U__WUR_ON_I_COEFF_4US_2_0___M 0x00003FFF +#define PHYA_TXFD_WUR_CFG_20_U__WUR_ON_I_COEFF_4US_2_0___S 0 +#define PHYA_TXFD_WUR_CFG_20_U___M 0x3FFF3FFF +#define PHYA_TXFD_WUR_CFG_20_U___S 0 + +#define PHYA_TXFD_WUR_CFG_21_L (0x00391628) +#define PHYA_TXFD_WUR_CFG_21_L___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_21_L___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_21_L__WUR_ON_I_COEFF_4US_1_1___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_21_L__WUR_ON_I_COEFF_4US_0_1___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_21_L__WUR_ON_I_COEFF_4US_1_1___M 0x3FFF0000 +#define PHYA_TXFD_WUR_CFG_21_L__WUR_ON_I_COEFF_4US_1_1___S 16 +#define PHYA_TXFD_WUR_CFG_21_L__WUR_ON_I_COEFF_4US_0_1___M 0x00003FFF +#define PHYA_TXFD_WUR_CFG_21_L__WUR_ON_I_COEFF_4US_0_1___S 0 +#define PHYA_TXFD_WUR_CFG_21_L___M 0x3FFF3FFF +#define PHYA_TXFD_WUR_CFG_21_L___S 0 + +#define PHYA_TXFD_WUR_CFG_21_U (0x0039162C) +#define PHYA_TXFD_WUR_CFG_21_U___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_21_U___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_21_U__WUR_ON_I_COEFF_4US_3_1___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_21_U__WUR_ON_I_COEFF_4US_2_1___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_21_U__WUR_ON_I_COEFF_4US_3_1___M 0x3FFF0000 +#define PHYA_TXFD_WUR_CFG_21_U__WUR_ON_I_COEFF_4US_3_1___S 16 +#define PHYA_TXFD_WUR_CFG_21_U__WUR_ON_I_COEFF_4US_2_1___M 0x00003FFF +#define PHYA_TXFD_WUR_CFG_21_U__WUR_ON_I_COEFF_4US_2_1___S 0 +#define PHYA_TXFD_WUR_CFG_21_U___M 0x3FFF3FFF +#define PHYA_TXFD_WUR_CFG_21_U___S 0 + +#define PHYA_TXFD_WUR_CFG_22_L (0x00391630) +#define PHYA_TXFD_WUR_CFG_22_L___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_22_L___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_22_L__WUR_ON_I_COEFF_4US_1_2___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_22_L__WUR_ON_I_COEFF_4US_0_2___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_22_L__WUR_ON_I_COEFF_4US_1_2___M 0x3FFF0000 +#define PHYA_TXFD_WUR_CFG_22_L__WUR_ON_I_COEFF_4US_1_2___S 16 +#define PHYA_TXFD_WUR_CFG_22_L__WUR_ON_I_COEFF_4US_0_2___M 0x00003FFF +#define PHYA_TXFD_WUR_CFG_22_L__WUR_ON_I_COEFF_4US_0_2___S 0 +#define PHYA_TXFD_WUR_CFG_22_L___M 0x3FFF3FFF +#define PHYA_TXFD_WUR_CFG_22_L___S 0 + +#define PHYA_TXFD_WUR_CFG_22_U (0x00391634) +#define PHYA_TXFD_WUR_CFG_22_U___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_22_U___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_22_U__WUR_ON_I_COEFF_4US_3_2___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_22_U__WUR_ON_I_COEFF_4US_2_2___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_22_U__WUR_ON_I_COEFF_4US_3_2___M 0x3FFF0000 +#define PHYA_TXFD_WUR_CFG_22_U__WUR_ON_I_COEFF_4US_3_2___S 16 +#define PHYA_TXFD_WUR_CFG_22_U__WUR_ON_I_COEFF_4US_2_2___M 0x00003FFF +#define PHYA_TXFD_WUR_CFG_22_U__WUR_ON_I_COEFF_4US_2_2___S 0 +#define PHYA_TXFD_WUR_CFG_22_U___M 0x3FFF3FFF +#define PHYA_TXFD_WUR_CFG_22_U___S 0 + +#define PHYA_TXFD_WUR_CFG_23_L (0x00391638) +#define PHYA_TXFD_WUR_CFG_23_L___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_23_L___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_23_L__WUR_ON_I_COEFF_4US_1_3___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_23_L__WUR_ON_I_COEFF_4US_0_3___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_23_L__WUR_ON_I_COEFF_4US_1_3___M 0x3FFF0000 +#define PHYA_TXFD_WUR_CFG_23_L__WUR_ON_I_COEFF_4US_1_3___S 16 +#define PHYA_TXFD_WUR_CFG_23_L__WUR_ON_I_COEFF_4US_0_3___M 0x00003FFF +#define PHYA_TXFD_WUR_CFG_23_L__WUR_ON_I_COEFF_4US_0_3___S 0 +#define PHYA_TXFD_WUR_CFG_23_L___M 0x3FFF3FFF +#define PHYA_TXFD_WUR_CFG_23_L___S 0 + +#define PHYA_TXFD_WUR_CFG_23_U (0x0039163C) +#define PHYA_TXFD_WUR_CFG_23_U___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_23_U___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_23_U__WUR_ON_I_COEFF_4US_3_3___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_23_U__WUR_ON_I_COEFF_4US_2_3___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_23_U__WUR_ON_I_COEFF_4US_3_3___M 0x3FFF0000 +#define PHYA_TXFD_WUR_CFG_23_U__WUR_ON_I_COEFF_4US_3_3___S 16 +#define PHYA_TXFD_WUR_CFG_23_U__WUR_ON_I_COEFF_4US_2_3___M 0x00003FFF +#define PHYA_TXFD_WUR_CFG_23_U__WUR_ON_I_COEFF_4US_2_3___S 0 +#define PHYA_TXFD_WUR_CFG_23_U___M 0x3FFF3FFF +#define PHYA_TXFD_WUR_CFG_23_U___S 0 + +#define PHYA_TXFD_WUR_CFG_30_L (0x00391640) +#define PHYA_TXFD_WUR_CFG_30_L___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_30_L___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_30_L__WUR_ON_Q_COEFF_4US_1_0___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_30_L__WUR_ON_Q_COEFF_4US_0_0___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_30_L__WUR_ON_Q_COEFF_4US_1_0___M 0x3FFF0000 +#define PHYA_TXFD_WUR_CFG_30_L__WUR_ON_Q_COEFF_4US_1_0___S 16 +#define PHYA_TXFD_WUR_CFG_30_L__WUR_ON_Q_COEFF_4US_0_0___M 0x00003FFF +#define PHYA_TXFD_WUR_CFG_30_L__WUR_ON_Q_COEFF_4US_0_0___S 0 +#define PHYA_TXFD_WUR_CFG_30_L___M 0x3FFF3FFF +#define PHYA_TXFD_WUR_CFG_30_L___S 0 + +#define PHYA_TXFD_WUR_CFG_30_U (0x00391644) +#define PHYA_TXFD_WUR_CFG_30_U___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_30_U___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_30_U__WUR_ON_Q_COEFF_4US_3_0___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_30_U__WUR_ON_Q_COEFF_4US_2_0___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_30_U__WUR_ON_Q_COEFF_4US_3_0___M 0x3FFF0000 +#define PHYA_TXFD_WUR_CFG_30_U__WUR_ON_Q_COEFF_4US_3_0___S 16 +#define PHYA_TXFD_WUR_CFG_30_U__WUR_ON_Q_COEFF_4US_2_0___M 0x00003FFF +#define PHYA_TXFD_WUR_CFG_30_U__WUR_ON_Q_COEFF_4US_2_0___S 0 +#define PHYA_TXFD_WUR_CFG_30_U___M 0x3FFF3FFF +#define PHYA_TXFD_WUR_CFG_30_U___S 0 + +#define PHYA_TXFD_WUR_CFG_31_L (0x00391648) +#define PHYA_TXFD_WUR_CFG_31_L___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_31_L___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_31_L__WUR_ON_Q_COEFF_4US_1_1___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_31_L__WUR_ON_Q_COEFF_4US_0_1___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_31_L__WUR_ON_Q_COEFF_4US_1_1___M 0x3FFF0000 +#define PHYA_TXFD_WUR_CFG_31_L__WUR_ON_Q_COEFF_4US_1_1___S 16 +#define PHYA_TXFD_WUR_CFG_31_L__WUR_ON_Q_COEFF_4US_0_1___M 0x00003FFF +#define PHYA_TXFD_WUR_CFG_31_L__WUR_ON_Q_COEFF_4US_0_1___S 0 +#define PHYA_TXFD_WUR_CFG_31_L___M 0x3FFF3FFF +#define PHYA_TXFD_WUR_CFG_31_L___S 0 + +#define PHYA_TXFD_WUR_CFG_31_U (0x0039164C) +#define PHYA_TXFD_WUR_CFG_31_U___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_31_U___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_31_U__WUR_ON_Q_COEFF_4US_3_1___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_31_U__WUR_ON_Q_COEFF_4US_2_1___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_31_U__WUR_ON_Q_COEFF_4US_3_1___M 0x3FFF0000 +#define PHYA_TXFD_WUR_CFG_31_U__WUR_ON_Q_COEFF_4US_3_1___S 16 +#define PHYA_TXFD_WUR_CFG_31_U__WUR_ON_Q_COEFF_4US_2_1___M 0x00003FFF +#define PHYA_TXFD_WUR_CFG_31_U__WUR_ON_Q_COEFF_4US_2_1___S 0 +#define PHYA_TXFD_WUR_CFG_31_U___M 0x3FFF3FFF +#define PHYA_TXFD_WUR_CFG_31_U___S 0 + +#define PHYA_TXFD_WUR_CFG_32_L (0x00391650) +#define PHYA_TXFD_WUR_CFG_32_L___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_32_L___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_32_L__WUR_ON_Q_COEFF_4US_1_2___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_32_L__WUR_ON_Q_COEFF_4US_0_2___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_32_L__WUR_ON_Q_COEFF_4US_1_2___M 0x3FFF0000 +#define PHYA_TXFD_WUR_CFG_32_L__WUR_ON_Q_COEFF_4US_1_2___S 16 +#define PHYA_TXFD_WUR_CFG_32_L__WUR_ON_Q_COEFF_4US_0_2___M 0x00003FFF +#define PHYA_TXFD_WUR_CFG_32_L__WUR_ON_Q_COEFF_4US_0_2___S 0 +#define PHYA_TXFD_WUR_CFG_32_L___M 0x3FFF3FFF +#define PHYA_TXFD_WUR_CFG_32_L___S 0 + +#define PHYA_TXFD_WUR_CFG_32_U (0x00391654) +#define PHYA_TXFD_WUR_CFG_32_U___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_32_U___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_32_U__WUR_ON_Q_COEFF_4US_3_2___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_32_U__WUR_ON_Q_COEFF_4US_2_2___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_32_U__WUR_ON_Q_COEFF_4US_3_2___M 0x3FFF0000 +#define PHYA_TXFD_WUR_CFG_32_U__WUR_ON_Q_COEFF_4US_3_2___S 16 +#define PHYA_TXFD_WUR_CFG_32_U__WUR_ON_Q_COEFF_4US_2_2___M 0x00003FFF +#define PHYA_TXFD_WUR_CFG_32_U__WUR_ON_Q_COEFF_4US_2_2___S 0 +#define PHYA_TXFD_WUR_CFG_32_U___M 0x3FFF3FFF +#define PHYA_TXFD_WUR_CFG_32_U___S 0 + +#define PHYA_TXFD_WUR_CFG_33_L (0x00391658) +#define PHYA_TXFD_WUR_CFG_33_L___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_33_L___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_33_L__WUR_ON_Q_COEFF_4US_1_3___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_33_L__WUR_ON_Q_COEFF_4US_0_3___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_33_L__WUR_ON_Q_COEFF_4US_1_3___M 0x3FFF0000 +#define PHYA_TXFD_WUR_CFG_33_L__WUR_ON_Q_COEFF_4US_1_3___S 16 +#define PHYA_TXFD_WUR_CFG_33_L__WUR_ON_Q_COEFF_4US_0_3___M 0x00003FFF +#define PHYA_TXFD_WUR_CFG_33_L__WUR_ON_Q_COEFF_4US_0_3___S 0 +#define PHYA_TXFD_WUR_CFG_33_L___M 0x3FFF3FFF +#define PHYA_TXFD_WUR_CFG_33_L___S 0 + +#define PHYA_TXFD_WUR_CFG_33_U (0x0039165C) +#define PHYA_TXFD_WUR_CFG_33_U___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_33_U___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_33_U__WUR_ON_Q_COEFF_4US_3_3___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_33_U__WUR_ON_Q_COEFF_4US_2_3___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_33_U__WUR_ON_Q_COEFF_4US_3_3___M 0x3FFF0000 +#define PHYA_TXFD_WUR_CFG_33_U__WUR_ON_Q_COEFF_4US_3_3___S 16 +#define PHYA_TXFD_WUR_CFG_33_U__WUR_ON_Q_COEFF_4US_2_3___M 0x00003FFF +#define PHYA_TXFD_WUR_CFG_33_U__WUR_ON_Q_COEFF_4US_2_3___S 0 +#define PHYA_TXFD_WUR_CFG_33_U___M 0x3FFF3FFF +#define PHYA_TXFD_WUR_CFG_33_U___S 0 + +#define PHYA_TXFD_WUR_CFG_40_L (0x00391660) +#define PHYA_TXFD_WUR_CFG_40_L___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_40_L___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_40_L__WUR_ON_I_COEFF_2US_1_0___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_40_L__WUR_ON_I_COEFF_2US_0_0___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_40_L__WUR_ON_I_COEFF_2US_1_0___M 0x3FFF0000 +#define PHYA_TXFD_WUR_CFG_40_L__WUR_ON_I_COEFF_2US_1_0___S 16 +#define PHYA_TXFD_WUR_CFG_40_L__WUR_ON_I_COEFF_2US_0_0___M 0x00003FFF +#define PHYA_TXFD_WUR_CFG_40_L__WUR_ON_I_COEFF_2US_0_0___S 0 +#define PHYA_TXFD_WUR_CFG_40_L___M 0x3FFF3FFF +#define PHYA_TXFD_WUR_CFG_40_L___S 0 + +#define PHYA_TXFD_WUR_CFG_40_U (0x00391664) +#define PHYA_TXFD_WUR_CFG_40_U___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_40_U___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_40_U__WUR_ON_I_COEFF_2US_3_0___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_40_U__WUR_ON_I_COEFF_2US_2_0___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_40_U__WUR_ON_I_COEFF_2US_3_0___M 0x3FFF0000 +#define PHYA_TXFD_WUR_CFG_40_U__WUR_ON_I_COEFF_2US_3_0___S 16 +#define PHYA_TXFD_WUR_CFG_40_U__WUR_ON_I_COEFF_2US_2_0___M 0x00003FFF +#define PHYA_TXFD_WUR_CFG_40_U__WUR_ON_I_COEFF_2US_2_0___S 0 +#define PHYA_TXFD_WUR_CFG_40_U___M 0x3FFF3FFF +#define PHYA_TXFD_WUR_CFG_40_U___S 0 + +#define PHYA_TXFD_WUR_CFG_41_L (0x00391668) +#define PHYA_TXFD_WUR_CFG_41_L___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_41_L___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_41_L__WUR_ON_I_COEFF_2US_1_1___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_41_L__WUR_ON_I_COEFF_2US_0_1___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_41_L__WUR_ON_I_COEFF_2US_1_1___M 0x3FFF0000 +#define PHYA_TXFD_WUR_CFG_41_L__WUR_ON_I_COEFF_2US_1_1___S 16 +#define PHYA_TXFD_WUR_CFG_41_L__WUR_ON_I_COEFF_2US_0_1___M 0x00003FFF +#define PHYA_TXFD_WUR_CFG_41_L__WUR_ON_I_COEFF_2US_0_1___S 0 +#define PHYA_TXFD_WUR_CFG_41_L___M 0x3FFF3FFF +#define PHYA_TXFD_WUR_CFG_41_L___S 0 + +#define PHYA_TXFD_WUR_CFG_41_U (0x0039166C) +#define PHYA_TXFD_WUR_CFG_41_U___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_41_U___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_41_U__WUR_ON_I_COEFF_2US_3_1___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_41_U__WUR_ON_I_COEFF_2US_2_1___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_41_U__WUR_ON_I_COEFF_2US_3_1___M 0x3FFF0000 +#define PHYA_TXFD_WUR_CFG_41_U__WUR_ON_I_COEFF_2US_3_1___S 16 +#define PHYA_TXFD_WUR_CFG_41_U__WUR_ON_I_COEFF_2US_2_1___M 0x00003FFF +#define PHYA_TXFD_WUR_CFG_41_U__WUR_ON_I_COEFF_2US_2_1___S 0 +#define PHYA_TXFD_WUR_CFG_41_U___M 0x3FFF3FFF +#define PHYA_TXFD_WUR_CFG_41_U___S 0 + +#define PHYA_TXFD_WUR_CFG_42_L (0x00391670) +#define PHYA_TXFD_WUR_CFG_42_L___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_42_L___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_42_L__WUR_ON_I_COEFF_2US_1_2___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_42_L__WUR_ON_I_COEFF_2US_0_2___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_42_L__WUR_ON_I_COEFF_2US_1_2___M 0x3FFF0000 +#define PHYA_TXFD_WUR_CFG_42_L__WUR_ON_I_COEFF_2US_1_2___S 16 +#define PHYA_TXFD_WUR_CFG_42_L__WUR_ON_I_COEFF_2US_0_2___M 0x00003FFF +#define PHYA_TXFD_WUR_CFG_42_L__WUR_ON_I_COEFF_2US_0_2___S 0 +#define PHYA_TXFD_WUR_CFG_42_L___M 0x3FFF3FFF +#define PHYA_TXFD_WUR_CFG_42_L___S 0 + +#define PHYA_TXFD_WUR_CFG_42_U (0x00391674) +#define PHYA_TXFD_WUR_CFG_42_U___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_42_U___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_42_U__WUR_ON_I_COEFF_2US_3_2___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_42_U__WUR_ON_I_COEFF_2US_2_2___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_42_U__WUR_ON_I_COEFF_2US_3_2___M 0x3FFF0000 +#define PHYA_TXFD_WUR_CFG_42_U__WUR_ON_I_COEFF_2US_3_2___S 16 +#define PHYA_TXFD_WUR_CFG_42_U__WUR_ON_I_COEFF_2US_2_2___M 0x00003FFF +#define PHYA_TXFD_WUR_CFG_42_U__WUR_ON_I_COEFF_2US_2_2___S 0 +#define PHYA_TXFD_WUR_CFG_42_U___M 0x3FFF3FFF +#define PHYA_TXFD_WUR_CFG_42_U___S 0 + +#define PHYA_TXFD_WUR_CFG_43_L (0x00391678) +#define PHYA_TXFD_WUR_CFG_43_L___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_43_L___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_43_L__WUR_ON_I_COEFF_2US_1_3___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_43_L__WUR_ON_I_COEFF_2US_0_3___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_43_L__WUR_ON_I_COEFF_2US_1_3___M 0x3FFF0000 +#define PHYA_TXFD_WUR_CFG_43_L__WUR_ON_I_COEFF_2US_1_3___S 16 +#define PHYA_TXFD_WUR_CFG_43_L__WUR_ON_I_COEFF_2US_0_3___M 0x00003FFF +#define PHYA_TXFD_WUR_CFG_43_L__WUR_ON_I_COEFF_2US_0_3___S 0 +#define PHYA_TXFD_WUR_CFG_43_L___M 0x3FFF3FFF +#define PHYA_TXFD_WUR_CFG_43_L___S 0 + +#define PHYA_TXFD_WUR_CFG_43_U (0x0039167C) +#define PHYA_TXFD_WUR_CFG_43_U___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_43_U___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_43_U__WUR_ON_I_COEFF_2US_3_3___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_43_U__WUR_ON_I_COEFF_2US_2_3___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_43_U__WUR_ON_I_COEFF_2US_3_3___M 0x3FFF0000 +#define PHYA_TXFD_WUR_CFG_43_U__WUR_ON_I_COEFF_2US_3_3___S 16 +#define PHYA_TXFD_WUR_CFG_43_U__WUR_ON_I_COEFF_2US_2_3___M 0x00003FFF +#define PHYA_TXFD_WUR_CFG_43_U__WUR_ON_I_COEFF_2US_2_3___S 0 +#define PHYA_TXFD_WUR_CFG_43_U___M 0x3FFF3FFF +#define PHYA_TXFD_WUR_CFG_43_U___S 0 + +#define PHYA_TXFD_WUR_CFG_50_L (0x00391680) +#define PHYA_TXFD_WUR_CFG_50_L___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_50_L___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_50_L__WUR_ON_Q_COEFF_2US_1_0___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_50_L__WUR_ON_Q_COEFF_2US_0_0___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_50_L__WUR_ON_Q_COEFF_2US_1_0___M 0x3FFF0000 +#define PHYA_TXFD_WUR_CFG_50_L__WUR_ON_Q_COEFF_2US_1_0___S 16 +#define PHYA_TXFD_WUR_CFG_50_L__WUR_ON_Q_COEFF_2US_0_0___M 0x00003FFF +#define PHYA_TXFD_WUR_CFG_50_L__WUR_ON_Q_COEFF_2US_0_0___S 0 +#define PHYA_TXFD_WUR_CFG_50_L___M 0x3FFF3FFF +#define PHYA_TXFD_WUR_CFG_50_L___S 0 + +#define PHYA_TXFD_WUR_CFG_50_U (0x00391684) +#define PHYA_TXFD_WUR_CFG_50_U___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_50_U___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_50_U__WUR_ON_Q_COEFF_2US_3_0___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_50_U__WUR_ON_Q_COEFF_2US_2_0___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_50_U__WUR_ON_Q_COEFF_2US_3_0___M 0x3FFF0000 +#define PHYA_TXFD_WUR_CFG_50_U__WUR_ON_Q_COEFF_2US_3_0___S 16 +#define PHYA_TXFD_WUR_CFG_50_U__WUR_ON_Q_COEFF_2US_2_0___M 0x00003FFF +#define PHYA_TXFD_WUR_CFG_50_U__WUR_ON_Q_COEFF_2US_2_0___S 0 +#define PHYA_TXFD_WUR_CFG_50_U___M 0x3FFF3FFF +#define PHYA_TXFD_WUR_CFG_50_U___S 0 + +#define PHYA_TXFD_WUR_CFG_51_L (0x00391688) +#define PHYA_TXFD_WUR_CFG_51_L___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_51_L___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_51_L__WUR_ON_Q_COEFF_2US_1_1___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_51_L__WUR_ON_Q_COEFF_2US_0_1___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_51_L__WUR_ON_Q_COEFF_2US_1_1___M 0x3FFF0000 +#define PHYA_TXFD_WUR_CFG_51_L__WUR_ON_Q_COEFF_2US_1_1___S 16 +#define PHYA_TXFD_WUR_CFG_51_L__WUR_ON_Q_COEFF_2US_0_1___M 0x00003FFF +#define PHYA_TXFD_WUR_CFG_51_L__WUR_ON_Q_COEFF_2US_0_1___S 0 +#define PHYA_TXFD_WUR_CFG_51_L___M 0x3FFF3FFF +#define PHYA_TXFD_WUR_CFG_51_L___S 0 + +#define PHYA_TXFD_WUR_CFG_51_U (0x0039168C) +#define PHYA_TXFD_WUR_CFG_51_U___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_51_U___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_51_U__WUR_ON_Q_COEFF_2US_3_1___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_51_U__WUR_ON_Q_COEFF_2US_2_1___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_51_U__WUR_ON_Q_COEFF_2US_3_1___M 0x3FFF0000 +#define PHYA_TXFD_WUR_CFG_51_U__WUR_ON_Q_COEFF_2US_3_1___S 16 +#define PHYA_TXFD_WUR_CFG_51_U__WUR_ON_Q_COEFF_2US_2_1___M 0x00003FFF +#define PHYA_TXFD_WUR_CFG_51_U__WUR_ON_Q_COEFF_2US_2_1___S 0 +#define PHYA_TXFD_WUR_CFG_51_U___M 0x3FFF3FFF +#define PHYA_TXFD_WUR_CFG_51_U___S 0 + +#define PHYA_TXFD_WUR_CFG_52_L (0x00391690) +#define PHYA_TXFD_WUR_CFG_52_L___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_52_L___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_52_L__WUR_ON_Q_COEFF_2US_1_2___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_52_L__WUR_ON_Q_COEFF_2US_0_2___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_52_L__WUR_ON_Q_COEFF_2US_1_2___M 0x3FFF0000 +#define PHYA_TXFD_WUR_CFG_52_L__WUR_ON_Q_COEFF_2US_1_2___S 16 +#define PHYA_TXFD_WUR_CFG_52_L__WUR_ON_Q_COEFF_2US_0_2___M 0x00003FFF +#define PHYA_TXFD_WUR_CFG_52_L__WUR_ON_Q_COEFF_2US_0_2___S 0 +#define PHYA_TXFD_WUR_CFG_52_L___M 0x3FFF3FFF +#define PHYA_TXFD_WUR_CFG_52_L___S 0 + +#define PHYA_TXFD_WUR_CFG_52_U (0x00391694) +#define PHYA_TXFD_WUR_CFG_52_U___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_52_U___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_52_U__WUR_ON_Q_COEFF_2US_3_2___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_52_U__WUR_ON_Q_COEFF_2US_2_2___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_52_U__WUR_ON_Q_COEFF_2US_3_2___M 0x3FFF0000 +#define PHYA_TXFD_WUR_CFG_52_U__WUR_ON_Q_COEFF_2US_3_2___S 16 +#define PHYA_TXFD_WUR_CFG_52_U__WUR_ON_Q_COEFF_2US_2_2___M 0x00003FFF +#define PHYA_TXFD_WUR_CFG_52_U__WUR_ON_Q_COEFF_2US_2_2___S 0 +#define PHYA_TXFD_WUR_CFG_52_U___M 0x3FFF3FFF +#define PHYA_TXFD_WUR_CFG_52_U___S 0 + +#define PHYA_TXFD_WUR_CFG_53_L (0x00391698) +#define PHYA_TXFD_WUR_CFG_53_L___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_53_L___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_53_L__WUR_ON_Q_COEFF_2US_1_3___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_53_L__WUR_ON_Q_COEFF_2US_0_3___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_53_L__WUR_ON_Q_COEFF_2US_1_3___M 0x3FFF0000 +#define PHYA_TXFD_WUR_CFG_53_L__WUR_ON_Q_COEFF_2US_1_3___S 16 +#define PHYA_TXFD_WUR_CFG_53_L__WUR_ON_Q_COEFF_2US_0_3___M 0x00003FFF +#define PHYA_TXFD_WUR_CFG_53_L__WUR_ON_Q_COEFF_2US_0_3___S 0 +#define PHYA_TXFD_WUR_CFG_53_L___M 0x3FFF3FFF +#define PHYA_TXFD_WUR_CFG_53_L___S 0 + +#define PHYA_TXFD_WUR_CFG_53_U (0x0039169C) +#define PHYA_TXFD_WUR_CFG_53_U___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_53_U___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_53_U__WUR_ON_Q_COEFF_2US_3_3___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_53_U__WUR_ON_Q_COEFF_2US_2_3___POR 0x0000 +#define PHYA_TXFD_WUR_CFG_53_U__WUR_ON_Q_COEFF_2US_3_3___M 0x3FFF0000 +#define PHYA_TXFD_WUR_CFG_53_U__WUR_ON_Q_COEFF_2US_3_3___S 16 +#define PHYA_TXFD_WUR_CFG_53_U__WUR_ON_Q_COEFF_2US_2_3___M 0x00003FFF +#define PHYA_TXFD_WUR_CFG_53_U__WUR_ON_Q_COEFF_2US_2_3___S 0 +#define PHYA_TXFD_WUR_CFG_53_U___M 0x3FFF3FFF +#define PHYA_TXFD_WUR_CFG_53_U___S 0 + +#define PHYA_TXFD_WUR_CFG_6_L (0x003916A0) +#define PHYA_TXFD_WUR_CFG_6_L___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_6_L___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_6_L__WUR_CSD_LFSR_OVERRIDE___POR 0x0 +#define PHYA_TXFD_WUR_CFG_6_L__WUR_CSD_LFSR_OVERRIDE___M 0x00000001 +#define PHYA_TXFD_WUR_CFG_6_L__WUR_CSD_LFSR_OVERRIDE___S 0 +#define PHYA_TXFD_WUR_CFG_6_L___M 0x00000001 +#define PHYA_TXFD_WUR_CFG_6_L___S 0 + +#define PHYA_TXFD_WUR_CFG_7_L (0x003916A8) +#define PHYA_TXFD_WUR_CFG_7_L___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_7_L___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_7_L__WUR_RSVD_0___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_7_L__WUR_RSVD_0___M 0xFFFFFFFF +#define PHYA_TXFD_WUR_CFG_7_L__WUR_RSVD_0___S 0 +#define PHYA_TXFD_WUR_CFG_7_L___M 0xFFFFFFFF +#define PHYA_TXFD_WUR_CFG_7_L___S 0 + +#define PHYA_TXFD_WUR_CFG_7_U (0x003916AC) +#define PHYA_TXFD_WUR_CFG_7_U___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_CFG_7_U___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_7_U__WUR_RSVD_1___POR 0x00000000 +#define PHYA_TXFD_WUR_CFG_7_U__WUR_RSVD_1___M 0xFFFFFFFF +#define PHYA_TXFD_WUR_CFG_7_U__WUR_RSVD_1___S 0 +#define PHYA_TXFD_WUR_CFG_7_U___M 0xFFFFFFFF +#define PHYA_TXFD_WUR_CFG_7_U___S 0 + +#define PHYA_TXFD_CFG_0_L (0x003916B0) +#define PHYA_TXFD_CFG_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_CFG_0_L___POR 0x00000000 +#define PHYA_TXFD_CFG_0_L__DYN_CGC_DIS_CLK320_PEF_COEFF_MEM___POR 0x0 +#define PHYA_TXFD_CFG_0_L__DYN_CGC_DIS_CLK_TXFD___POR 0x0 +#define PHYA_TXFD_CFG_0_L__DYN_CGC_DIS_CSR_CLK___POR 0x0 +#define PHYA_TXFD_CFG_0_L__DYN_CGC_DIS___POR 0x0 +#define PHYA_TXFD_CFG_0_L__DYN_CGC_DIS_CLK320_PEF_COEFF_MEM___M 0x01000000 +#define PHYA_TXFD_CFG_0_L__DYN_CGC_DIS_CLK320_PEF_COEFF_MEM___S 24 +#define PHYA_TXFD_CFG_0_L__DYN_CGC_DIS_CLK_TXFD___M 0x00010000 +#define PHYA_TXFD_CFG_0_L__DYN_CGC_DIS_CLK_TXFD___S 16 +#define PHYA_TXFD_CFG_0_L__DYN_CGC_DIS_CSR_CLK___M 0x00000100 +#define PHYA_TXFD_CFG_0_L__DYN_CGC_DIS_CSR_CLK___S 8 +#define PHYA_TXFD_CFG_0_L__DYN_CGC_DIS___M 0x00000001 +#define PHYA_TXFD_CFG_0_L__DYN_CGC_DIS___S 0 +#define PHYA_TXFD_CFG_0_L___M 0x01010101 +#define PHYA_TXFD_CFG_0_L___S 0 + +#define PHYA_TXFD_CFG_0_U (0x003916B4) +#define PHYA_TXFD_CFG_0_U___RWC QCSR_REG_RW +#define PHYA_TXFD_CFG_0_U___POR 0x00000100 +#define PHYA_TXFD_CFG_0_U__FTPG_CLK_EN___POR 0x0 +#define PHYA_TXFD_CFG_0_U__PHYDBG_CLK_EN___POR 0x0 +#define PHYA_TXFD_CFG_0_U__CLK_MPI_ENABLE___POR 0x1 +#define PHYA_TXFD_CFG_0_U__DYN_CGC_DIS_CLK80___POR 0x0 +#define PHYA_TXFD_CFG_0_U__FTPG_CLK_EN___M 0x01000000 +#define PHYA_TXFD_CFG_0_U__FTPG_CLK_EN___S 24 +#define PHYA_TXFD_CFG_0_U__PHYDBG_CLK_EN___M 0x00010000 +#define PHYA_TXFD_CFG_0_U__PHYDBG_CLK_EN___S 16 +#define PHYA_TXFD_CFG_0_U__CLK_MPI_ENABLE___M 0x00000100 +#define PHYA_TXFD_CFG_0_U__CLK_MPI_ENABLE___S 8 +#define PHYA_TXFD_CFG_0_U__DYN_CGC_DIS_CLK80___M 0x00000001 +#define PHYA_TXFD_CFG_0_U__DYN_CGC_DIS_CLK80___S 0 +#define PHYA_TXFD_CFG_0_U___M 0x01010101 +#define PHYA_TXFD_CFG_0_U___S 0 + +#define PHYA_TXFD_CFG_1_L (0x003916B8) +#define PHYA_TXFD_CFG_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_CFG_1_L___POR 0x00000001 +#define PHYA_TXFD_CFG_1_L__DATA_REQ_THROTTLE_MODE___POR 0x0 +#define PHYA_TXFD_CFG_1_L__STREAM_CLKGATE_OVERRIDE___POR 0x0 +#define PHYA_TXFD_CFG_1_L__USER_CLKGATE_OVERRIDE___POR 0x0 +#define PHYA_TXFD_CFG_1_L__TLV_DECODER_CLK_EN___POR 0x1 +#define PHYA_TXFD_CFG_1_L__DATA_REQ_THROTTLE_MODE___M 0x03000000 +#define PHYA_TXFD_CFG_1_L__DATA_REQ_THROTTLE_MODE___S 24 +#define PHYA_TXFD_CFG_1_L__STREAM_CLKGATE_OVERRIDE___M 0x00010000 +#define PHYA_TXFD_CFG_1_L__STREAM_CLKGATE_OVERRIDE___S 16 +#define PHYA_TXFD_CFG_1_L__USER_CLKGATE_OVERRIDE___M 0x00000100 +#define PHYA_TXFD_CFG_1_L__USER_CLKGATE_OVERRIDE___S 8 +#define PHYA_TXFD_CFG_1_L__TLV_DECODER_CLK_EN___M 0x00000001 +#define PHYA_TXFD_CFG_1_L__TLV_DECODER_CLK_EN___S 0 +#define PHYA_TXFD_CFG_1_L___M 0x03010101 +#define PHYA_TXFD_CFG_1_L___S 0 + +#define PHYA_TXFD_CFG_1_U (0x003916BC) +#define PHYA_TXFD_CFG_1_U___RWC QCSR_REG_RW +#define PHYA_TXFD_CFG_1_U___POR 0x00000000 +#define PHYA_TXFD_CFG_1_U__WAIT_FOR_PKT_START_FAST___POR 0x0 +#define PHYA_TXFD_CFG_1_U__APPLY_WALSH_ON_LEGACY___POR 0x0 +#define PHYA_TXFD_CFG_1_U__WAIT_FOR_PKT_START_FAST___M 0x00000100 +#define PHYA_TXFD_CFG_1_U__WAIT_FOR_PKT_START_FAST___S 8 +#define PHYA_TXFD_CFG_1_U__APPLY_WALSH_ON_LEGACY___M 0x00000001 +#define PHYA_TXFD_CFG_1_U__APPLY_WALSH_ON_LEGACY___S 0 +#define PHYA_TXFD_CFG_1_U___M 0x00000101 +#define PHYA_TXFD_CFG_1_U___S 0 + +#define PHYA_TXFD_CFG_2_L (0x003916C0) +#define PHYA_TXFD_CFG_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_CFG_2_L___POR 0x0004040A +#define PHYA_TXFD_CFG_2_L__NUM_CTRL_REQ_TLV_CYCLES_OFFSET___POR 0x04 +#define PHYA_TXFD_CFG_2_L__NUM_CTRL_REQ_TLV_CYCLES___POR 0x04 +#define PHYA_TXFD_CFG_2_L__NUM_OUTSTANDING_DATA_REQ___POR 0x0A +#define PHYA_TXFD_CFG_2_L__NUM_CTRL_REQ_TLV_CYCLES_OFFSET___M 0x00FF0000 +#define PHYA_TXFD_CFG_2_L__NUM_CTRL_REQ_TLV_CYCLES_OFFSET___S 16 +#define PHYA_TXFD_CFG_2_L__NUM_CTRL_REQ_TLV_CYCLES___M 0x0000FF00 +#define PHYA_TXFD_CFG_2_L__NUM_CTRL_REQ_TLV_CYCLES___S 8 +#define PHYA_TXFD_CFG_2_L__NUM_OUTSTANDING_DATA_REQ___M 0x0000001F +#define PHYA_TXFD_CFG_2_L__NUM_OUTSTANDING_DATA_REQ___S 0 +#define PHYA_TXFD_CFG_2_L___M 0x00FFFF1F +#define PHYA_TXFD_CFG_2_L___S 0 + +#define PHYA_TXFD_CFG_2_U (0x003916C4) +#define PHYA_TXFD_CFG_2_U___RWC QCSR_REG_RW +#define PHYA_TXFD_CFG_2_U___POR 0x140F03E8 +#define PHYA_TXFD_CFG_2_U__MAC_DATA_LATENCY_MAX___POR 0x14 +#define PHYA_TXFD_CFG_2_U__RU_INIT_DURATION___POR 0x0F +#define PHYA_TXFD_CFG_2_U__INTERVAL_BTWN_CTRL_REQ___POR 0x03E8 +#define PHYA_TXFD_CFG_2_U__MAC_DATA_LATENCY_MAX___M 0xFF000000 +#define PHYA_TXFD_CFG_2_U__MAC_DATA_LATENCY_MAX___S 24 +#define PHYA_TXFD_CFG_2_U__RU_INIT_DURATION___M 0x001F0000 +#define PHYA_TXFD_CFG_2_U__RU_INIT_DURATION___S 16 +#define PHYA_TXFD_CFG_2_U__INTERVAL_BTWN_CTRL_REQ___M 0x0000FFFF +#define PHYA_TXFD_CFG_2_U__INTERVAL_BTWN_CTRL_REQ___S 0 +#define PHYA_TXFD_CFG_2_U___M 0xFF1FFFFF +#define PHYA_TXFD_CFG_2_U___S 0 + +#define PHYA_TXFD_CFG_3_L (0x003916C8) +#define PHYA_TXFD_CFG_3_L___RWC QCSR_REG_RW +#define PHYA_TXFD_CFG_3_L___POR 0x00007C96 +#define PHYA_TXFD_CFG_3_L__NON_M3_MODE___POR 0x0 +#define PHYA_TXFD_CFG_3_L__TLV_FIFO_ALMOST_FULL_DEPTH___POR 0x7C +#define PHYA_TXFD_CFG_3_L__MAC_HEADER_LATENCY_MAX___POR 0x96 +#define PHYA_TXFD_CFG_3_L__NON_M3_MODE___M 0x00010000 +#define PHYA_TXFD_CFG_3_L__NON_M3_MODE___S 16 +#define PHYA_TXFD_CFG_3_L__TLV_FIFO_ALMOST_FULL_DEPTH___M 0x0000FF00 +#define PHYA_TXFD_CFG_3_L__TLV_FIFO_ALMOST_FULL_DEPTH___S 8 +#define PHYA_TXFD_CFG_3_L__MAC_HEADER_LATENCY_MAX___M 0x000000FF +#define PHYA_TXFD_CFG_3_L__MAC_HEADER_LATENCY_MAX___S 0 +#define PHYA_TXFD_CFG_3_L___M 0x0001FFFF +#define PHYA_TXFD_CFG_3_L___S 0 + +#define PHYA_TXFD_CFG_3_U (0x003916CC) +#define PHYA_TXFD_CFG_3_U___RWC QCSR_REG_RW +#define PHYA_TXFD_CFG_3_U___POR 0x00003E80 +#define PHYA_TXFD_CFG_3_U__PHY_ABORT_ACK_WATCHDOG_TIMER___POR 0x00003E80 +#define PHYA_TXFD_CFG_3_U__PHY_ABORT_ACK_WATCHDOG_TIMER___M 0xFFFFFFFF +#define PHYA_TXFD_CFG_3_U__PHY_ABORT_ACK_WATCHDOG_TIMER___S 0 +#define PHYA_TXFD_CFG_3_U___M 0xFFFFFFFF +#define PHYA_TXFD_CFG_3_U___S 0 + +#define PHYA_TXFD_CFG_4_L (0x003916D0) +#define PHYA_TXFD_CFG_4_L___RWC QCSR_REG_RW +#define PHYA_TXFD_CFG_4_L___POR 0x001E00A0 +#define PHYA_TXFD_CFG_4_L__TLV_FIFO_NOT_EMPTY_TIMEOUT___POR 0x001E +#define PHYA_TXFD_CFG_4_L__TLV_FIFO_RD_HANG_TIMEOUT___POR 0x00A0 +#define PHYA_TXFD_CFG_4_L__TLV_FIFO_NOT_EMPTY_TIMEOUT___M 0xFFFF0000 +#define PHYA_TXFD_CFG_4_L__TLV_FIFO_NOT_EMPTY_TIMEOUT___S 16 +#define PHYA_TXFD_CFG_4_L__TLV_FIFO_RD_HANG_TIMEOUT___M 0x0000FFFF +#define PHYA_TXFD_CFG_4_L__TLV_FIFO_RD_HANG_TIMEOUT___S 0 +#define PHYA_TXFD_CFG_4_L___M 0xFFFFFFFF +#define PHYA_TXFD_CFG_4_L___S 0 + +#define PHYA_TXFD_CFG_4_U (0x003916D4) +#define PHYA_TXFD_CFG_4_U___RWC QCSR_REG_RW +#define PHYA_TXFD_CFG_4_U___POR 0x01010096 +#define PHYA_TXFD_CFG_4_U__DROP_TLV_DURING_PHY_ABORT___POR 0x1 +#define PHYA_TXFD_CFG_4_U__DROP_TLV_DURING_MAC_ABORT___POR 0x1 +#define PHYA_TXFD_CFG_4_U__ORDERING_FIFO_NOT_EMPTY_TIMEOUT___POR 0x0096 +#define PHYA_TXFD_CFG_4_U__DROP_TLV_DURING_PHY_ABORT___M 0x01000000 +#define PHYA_TXFD_CFG_4_U__DROP_TLV_DURING_PHY_ABORT___S 24 +#define PHYA_TXFD_CFG_4_U__DROP_TLV_DURING_MAC_ABORT___M 0x00010000 +#define PHYA_TXFD_CFG_4_U__DROP_TLV_DURING_MAC_ABORT___S 16 +#define PHYA_TXFD_CFG_4_U__ORDERING_FIFO_NOT_EMPTY_TIMEOUT___M 0x0000FFFF +#define PHYA_TXFD_CFG_4_U__ORDERING_FIFO_NOT_EMPTY_TIMEOUT___S 0 +#define PHYA_TXFD_CFG_4_U___M 0x0101FFFF +#define PHYA_TXFD_CFG_4_U___S 0 + +#define PHYA_TXFD_CFG_5_L (0x003916D8) +#define PHYA_TXFD_CFG_5_L___RWC QCSR_REG_RW +#define PHYA_TXFD_CFG_5_L___POR 0x00010000 +#define PHYA_TXFD_CFG_5_L__HEAVYCLIP_EN_FOR_MU___POR 0x0 +#define PHYA_TXFD_CFG_5_L__HEAVYCLIP_EN_OVERRIDE_FOR_MU___POR 0x1 +#define PHYA_TXFD_CFG_5_L__HEAVYCLIP_EN_FOR_NDP___POR 0x0 +#define PHYA_TXFD_CFG_5_L__HEAVYCLIP_EN_FOR_11BA___POR 0x0 +#define PHYA_TXFD_CFG_5_L__HEAVYCLIP_EN_FOR_MU___M 0x01000000 +#define PHYA_TXFD_CFG_5_L__HEAVYCLIP_EN_FOR_MU___S 24 +#define PHYA_TXFD_CFG_5_L__HEAVYCLIP_EN_OVERRIDE_FOR_MU___M 0x00010000 +#define PHYA_TXFD_CFG_5_L__HEAVYCLIP_EN_OVERRIDE_FOR_MU___S 16 +#define PHYA_TXFD_CFG_5_L__HEAVYCLIP_EN_FOR_NDP___M 0x00000100 +#define PHYA_TXFD_CFG_5_L__HEAVYCLIP_EN_FOR_NDP___S 8 +#define PHYA_TXFD_CFG_5_L__HEAVYCLIP_EN_FOR_11BA___M 0x00000007 +#define PHYA_TXFD_CFG_5_L__HEAVYCLIP_EN_FOR_11BA___S 0 +#define PHYA_TXFD_CFG_5_L___M 0x01010107 +#define PHYA_TXFD_CFG_5_L___S 0 + +#define PHYA_TXFD_CFG_5_U (0x003916DC) +#define PHYA_TXFD_CFG_5_U___RWC QCSR_REG_RW +#define PHYA_TXFD_CFG_5_U___POR 0x00000001 +#define PHYA_TXFD_CFG_5_U__DCM_EXTRA_BIT_MODE___POR 0x0 +#define PHYA_TXFD_CFG_5_U__HEAVYCLIP_EN_FW_OVERRIDE___POR 0x0 +#define PHYA_TXFD_CFG_5_U__HEAVYCLIP_EN_FOR_OFDMA___POR 0x0 +#define PHYA_TXFD_CFG_5_U__HEAVYCLIP_EN_OVERRIDE_FOR_OFDMA___POR 0x1 +#define PHYA_TXFD_CFG_5_U__DCM_EXTRA_BIT_MODE___M 0x01000000 +#define PHYA_TXFD_CFG_5_U__DCM_EXTRA_BIT_MODE___S 24 +#define PHYA_TXFD_CFG_5_U__HEAVYCLIP_EN_FW_OVERRIDE___M 0x00010000 +#define PHYA_TXFD_CFG_5_U__HEAVYCLIP_EN_FW_OVERRIDE___S 16 +#define PHYA_TXFD_CFG_5_U__HEAVYCLIP_EN_FOR_OFDMA___M 0x00000100 +#define PHYA_TXFD_CFG_5_U__HEAVYCLIP_EN_FOR_OFDMA___S 8 +#define PHYA_TXFD_CFG_5_U__HEAVYCLIP_EN_OVERRIDE_FOR_OFDMA___M 0x00000001 +#define PHYA_TXFD_CFG_5_U__HEAVYCLIP_EN_OVERRIDE_FOR_OFDMA___S 0 +#define PHYA_TXFD_CFG_5_U___M 0x01010101 +#define PHYA_TXFD_CFG_5_U___S 0 + +#define PHYA_TXFD_CFG_6_L (0x003916E0) +#define PHYA_TXFD_CFG_6_L___RWC QCSR_REG_RW +#define PHYA_TXFD_CFG_6_L___POR 0x08000000 +#define PHYA_TXFD_CFG_6_L__HE_SIGB_NUM_BITS_COMMON___POR 0x8 +#define PHYA_TXFD_CFG_6_L__HE_SIGB_FW_CRC_OVERRIDE___POR 0x0 +#define PHYA_TXFD_CFG_6_L__HE_SIGA_FW_CRC_OVERRIDE___POR 0x0 +#define PHYA_TXFD_CFG_6_L__PKT_EXT_ENABLE_PMAT_GRT_4___POR 0x0 +#define PHYA_TXFD_CFG_6_L__HE_SIGB_NUM_BITS_COMMON___M 0x0F000000 +#define PHYA_TXFD_CFG_6_L__HE_SIGB_NUM_BITS_COMMON___S 24 +#define PHYA_TXFD_CFG_6_L__HE_SIGB_FW_CRC_OVERRIDE___M 0x00010000 +#define PHYA_TXFD_CFG_6_L__HE_SIGB_FW_CRC_OVERRIDE___S 16 +#define PHYA_TXFD_CFG_6_L__HE_SIGA_FW_CRC_OVERRIDE___M 0x00000100 +#define PHYA_TXFD_CFG_6_L__HE_SIGA_FW_CRC_OVERRIDE___S 8 +#define PHYA_TXFD_CFG_6_L__PKT_EXT_ENABLE_PMAT_GRT_4___M 0x00000001 +#define PHYA_TXFD_CFG_6_L__PKT_EXT_ENABLE_PMAT_GRT_4___S 0 +#define PHYA_TXFD_CFG_6_L___M 0x0F010101 +#define PHYA_TXFD_CFG_6_L___S 0 + +#define PHYA_TXFD_CFG_6_U (0x003916E4) +#define PHYA_TXFD_CFG_6_U___RWC QCSR_REG_RW +#define PHYA_TXFD_CFG_6_U___POR 0x00000015 +#define PHYA_TXFD_CFG_6_U__HE_SIGB_NUM_BITS_USER___POR 0x15 +#define PHYA_TXFD_CFG_6_U__HE_SIGB_NUM_BITS_USER___M 0x0000003F +#define PHYA_TXFD_CFG_6_U__HE_SIGB_NUM_BITS_USER___S 0 +#define PHYA_TXFD_CFG_6_U___M 0x0000003F +#define PHYA_TXFD_CFG_6_U___S 0 + +#define PHYA_TXFD_CFG_7_L (0x003916E8) +#define PHYA_TXFD_CFG_7_L___RWC QCSR_REG_RW +#define PHYA_TXFD_CFG_7_L___POR 0x00000101 +#define PHYA_TXFD_CFG_7_L__HE_PKT_LSIG_PILOT_VAL_LUT_3___POR 0x0 +#define PHYA_TXFD_CFG_7_L__HE_PKT_LSIG_PILOT_VAL_LUT_2___POR 0x0 +#define PHYA_TXFD_CFG_7_L__HE_PKT_LSIG_PILOT_VAL_LUT_1___POR 0x1 +#define PHYA_TXFD_CFG_7_L__HE_PKT_LSIG_PILOT_VAL_LUT_0___POR 0x1 +#define PHYA_TXFD_CFG_7_L__HE_PKT_LSIG_PILOT_VAL_LUT_3___M 0x03000000 +#define PHYA_TXFD_CFG_7_L__HE_PKT_LSIG_PILOT_VAL_LUT_3___S 24 +#define PHYA_TXFD_CFG_7_L__HE_PKT_LSIG_PILOT_VAL_LUT_2___M 0x00030000 +#define PHYA_TXFD_CFG_7_L__HE_PKT_LSIG_PILOT_VAL_LUT_2___S 16 +#define PHYA_TXFD_CFG_7_L__HE_PKT_LSIG_PILOT_VAL_LUT_1___M 0x00000300 +#define PHYA_TXFD_CFG_7_L__HE_PKT_LSIG_PILOT_VAL_LUT_1___S 8 +#define PHYA_TXFD_CFG_7_L__HE_PKT_LSIG_PILOT_VAL_LUT_0___M 0x00000003 +#define PHYA_TXFD_CFG_7_L__HE_PKT_LSIG_PILOT_VAL_LUT_0___S 0 +#define PHYA_TXFD_CFG_7_L___M 0x03030303 +#define PHYA_TXFD_CFG_7_L___S 0 + +#define PHYA_TXFD_CFG_7_U (0x003916EC) +#define PHYA_TXFD_CFG_7_U___RWC QCSR_REG_RW +#define PHYA_TXFD_CFG_7_U___POR 0x00010100 +#define PHYA_TXFD_CFG_7_U__HE_PKT_LSIG_PILOT_VAL_LUT_7___POR 0x0 +#define PHYA_TXFD_CFG_7_U__HE_PKT_LSIG_PILOT_VAL_LUT_6___POR 0x1 +#define PHYA_TXFD_CFG_7_U__HE_PKT_LSIG_PILOT_VAL_LUT_5___POR 0x1 +#define PHYA_TXFD_CFG_7_U__HE_PKT_LSIG_PILOT_VAL_LUT_4___POR 0x0 +#define PHYA_TXFD_CFG_7_U__HE_PKT_LSIG_PILOT_VAL_LUT_7___M 0x03000000 +#define PHYA_TXFD_CFG_7_U__HE_PKT_LSIG_PILOT_VAL_LUT_7___S 24 +#define PHYA_TXFD_CFG_7_U__HE_PKT_LSIG_PILOT_VAL_LUT_6___M 0x00030000 +#define PHYA_TXFD_CFG_7_U__HE_PKT_LSIG_PILOT_VAL_LUT_6___S 16 +#define PHYA_TXFD_CFG_7_U__HE_PKT_LSIG_PILOT_VAL_LUT_5___M 0x00000300 +#define PHYA_TXFD_CFG_7_U__HE_PKT_LSIG_PILOT_VAL_LUT_5___S 8 +#define PHYA_TXFD_CFG_7_U__HE_PKT_LSIG_PILOT_VAL_LUT_4___M 0x00000003 +#define PHYA_TXFD_CFG_7_U__HE_PKT_LSIG_PILOT_VAL_LUT_4___S 0 +#define PHYA_TXFD_CFG_7_U___M 0x03030303 +#define PHYA_TXFD_CFG_7_U___S 0 + +#define PHYA_TXFD_CFG_8_L (0x003916F0) +#define PHYA_TXFD_CFG_8_L___RWC QCSR_REG_RW +#define PHYA_TXFD_CFG_8_L___POR 0x01000000 +#define PHYA_TXFD_CFG_8_L__HE_PKT_HESIG_PILOT_VAL_LUT_3___POR 0x1 +#define PHYA_TXFD_CFG_8_L__HE_PKT_HESIG_PILOT_VAL_LUT_2___POR 0x0 +#define PHYA_TXFD_CFG_8_L__HE_PKT_HESIG_PILOT_VAL_LUT_1___POR 0x0 +#define PHYA_TXFD_CFG_8_L__HE_PKT_HESIG_PILOT_VAL_LUT_0___POR 0x0 +#define PHYA_TXFD_CFG_8_L__HE_PKT_HESIG_PILOT_VAL_LUT_3___M 0x03000000 +#define PHYA_TXFD_CFG_8_L__HE_PKT_HESIG_PILOT_VAL_LUT_3___S 24 +#define PHYA_TXFD_CFG_8_L__HE_PKT_HESIG_PILOT_VAL_LUT_2___M 0x00030000 +#define PHYA_TXFD_CFG_8_L__HE_PKT_HESIG_PILOT_VAL_LUT_2___S 16 +#define PHYA_TXFD_CFG_8_L__HE_PKT_HESIG_PILOT_VAL_LUT_1___M 0x00000300 +#define PHYA_TXFD_CFG_8_L__HE_PKT_HESIG_PILOT_VAL_LUT_1___S 8 +#define PHYA_TXFD_CFG_8_L__HE_PKT_HESIG_PILOT_VAL_LUT_0___M 0x00000003 +#define PHYA_TXFD_CFG_8_L__HE_PKT_HESIG_PILOT_VAL_LUT_0___S 0 +#define PHYA_TXFD_CFG_8_L___M 0x03030303 +#define PHYA_TXFD_CFG_8_L___S 0 + +#define PHYA_TXFD_CFG_9_L (0x003916F8) +#define PHYA_TXFD_CFG_9_L___RWC QCSR_REG_RW +#define PHYA_TXFD_CFG_9_L___POR 0x000003C0 +#define PHYA_TXFD_CFG_9_L__WAIT_FOR_TXBF_WEIGHTS_READY_TIMEOUT___POR 0x03C0 +#define PHYA_TXFD_CFG_9_L__WAIT_FOR_TXBF_WEIGHTS_READY_TIMEOUT___M 0x0000FFFF +#define PHYA_TXFD_CFG_9_L__WAIT_FOR_TXBF_WEIGHTS_READY_TIMEOUT___S 0 +#define PHYA_TXFD_CFG_9_L___M 0x0000FFFF +#define PHYA_TXFD_CFG_9_L___S 0 + +#define PHYA_TXFD_CFG_9_U (0x003916FC) +#define PHYA_TXFD_CFG_9_U___RWC QCSR_REG_RW +#define PHYA_TXFD_CFG_9_U___POR 0x00001400 +#define PHYA_TXFD_CFG_9_U__TXFD_WATCHDOG_TIMEOUT___POR 0x00001400 +#define PHYA_TXFD_CFG_9_U__TXFD_WATCHDOG_TIMEOUT___M 0xFFFFFFFF +#define PHYA_TXFD_CFG_9_U__TXFD_WATCHDOG_TIMEOUT___S 0 +#define PHYA_TXFD_CFG_9_U___M 0xFFFFFFFF +#define PHYA_TXFD_CFG_9_U___S 0 + +#define PHYA_TXFD_CFG_10_L (0x00391700) +#define PHYA_TXFD_CFG_10_L___RWC QCSR_REG_RW +#define PHYA_TXFD_CFG_10_L___POR 0x00000000 +#define PHYA_TXFD_CFG_10_L__HE_SIGB_CRC_NIBBLE___POR 0x0 +#define PHYA_TXFD_CFG_10_L__HE_SIGA_CRC_NIBBLE___POR 0x0 +#define PHYA_TXFD_CFG_10_L__MPI_REQ_TLV_THROTTLE_MODE___POR 0x0 +#define PHYA_TXFD_CFG_10_L__APPLY_WALSH_FOR_NSTS_EQ_NTX___POR 0x0 +#define PHYA_TXFD_CFG_10_L__HE_SIGB_CRC_NIBBLE___M 0x01000000 +#define PHYA_TXFD_CFG_10_L__HE_SIGB_CRC_NIBBLE___S 24 +#define PHYA_TXFD_CFG_10_L__HE_SIGA_CRC_NIBBLE___M 0x00010000 +#define PHYA_TXFD_CFG_10_L__HE_SIGA_CRC_NIBBLE___S 16 +#define PHYA_TXFD_CFG_10_L__MPI_REQ_TLV_THROTTLE_MODE___M 0x00000300 +#define PHYA_TXFD_CFG_10_L__MPI_REQ_TLV_THROTTLE_MODE___S 8 +#define PHYA_TXFD_CFG_10_L__APPLY_WALSH_FOR_NSTS_EQ_NTX___M 0x00000001 +#define PHYA_TXFD_CFG_10_L__APPLY_WALSH_FOR_NSTS_EQ_NTX___S 0 +#define PHYA_TXFD_CFG_10_L___M 0x01010301 +#define PHYA_TXFD_CFG_10_L___S 0 + +#define PHYA_TXFD_CFG_10_U (0x00391704) +#define PHYA_TXFD_CFG_10_U___RWC QCSR_REG_RW +#define PHYA_TXFD_CFG_10_U___POR 0x00000101 +#define PHYA_TXFD_CFG_10_U__TLV_FIFO_OCCUPANCY___POR 0x01 +#define PHYA_TXFD_CFG_10_U__PRI_IS_LOWER_80___POR 0x1 +#define PHYA_TXFD_CFG_10_U__TLV_FIFO_OCCUPANCY___M 0x0000FF00 +#define PHYA_TXFD_CFG_10_U__TLV_FIFO_OCCUPANCY___S 8 +#define PHYA_TXFD_CFG_10_U__PRI_IS_LOWER_80___M 0x00000001 +#define PHYA_TXFD_CFG_10_U__PRI_IS_LOWER_80___S 0 +#define PHYA_TXFD_CFG_10_U___M 0x0000FF01 +#define PHYA_TXFD_CFG_10_U___S 0 + +#define PHYA_TXFD_CFG_11_L (0x00391708) +#define PHYA_TXFD_CFG_11_L___RWC QCSR_REG_RW +#define PHYA_TXFD_CFG_11_L___POR 0x00000000 +#define PHYA_TXFD_CFG_11_L__TLV_TO_PCSS_MASK_0___POR 0x00000000 +#define PHYA_TXFD_CFG_11_L__TLV_TO_PCSS_MASK_0___M 0xFFFFFFFF +#define PHYA_TXFD_CFG_11_L__TLV_TO_PCSS_MASK_0___S 0 +#define PHYA_TXFD_CFG_11_L___M 0xFFFFFFFF +#define PHYA_TXFD_CFG_11_L___S 0 + +#define PHYA_TXFD_CFG_11_U (0x0039170C) +#define PHYA_TXFD_CFG_11_U___RWC QCSR_REG_RW +#define PHYA_TXFD_CFG_11_U___POR 0x00000000 +#define PHYA_TXFD_CFG_11_U__TLV_TO_PCSS_MASK_1___POR 0x00000000 +#define PHYA_TXFD_CFG_11_U__TLV_TO_PCSS_MASK_1___M 0xFFFFFFFF +#define PHYA_TXFD_CFG_11_U__TLV_TO_PCSS_MASK_1___S 0 +#define PHYA_TXFD_CFG_11_U___M 0xFFFFFFFF +#define PHYA_TXFD_CFG_11_U___S 0 + +#define PHYA_TXFD_CFG_12_L (0x00391710) +#define PHYA_TXFD_CFG_12_L___RWC QCSR_REG_RW +#define PHYA_TXFD_CFG_12_L___POR 0x00000000 +#define PHYA_TXFD_CFG_12_L__MACTX_PHYTX_TLV_MASK___POR 0x00 +#define PHYA_TXFD_CFG_12_L__PHYTX_MACTX_TLV_MASK___POR 0x00 +#define PHYA_TXFD_CFG_12_L__PHY_ABORT_FLAG_RST___POR 0x0 +#define PHYA_TXFD_CFG_12_L__MACTX_PHYTX_TLV_MASK___M 0x00FF0000 +#define PHYA_TXFD_CFG_12_L__MACTX_PHYTX_TLV_MASK___S 16 +#define PHYA_TXFD_CFG_12_L__PHYTX_MACTX_TLV_MASK___M 0x0000FF00 +#define PHYA_TXFD_CFG_12_L__PHYTX_MACTX_TLV_MASK___S 8 +#define PHYA_TXFD_CFG_12_L__PHY_ABORT_FLAG_RST___M 0x00000001 +#define PHYA_TXFD_CFG_12_L__PHY_ABORT_FLAG_RST___S 0 +#define PHYA_TXFD_CFG_12_L___M 0x00FFFF01 +#define PHYA_TXFD_CFG_12_L___S 0 + +#define PHYA_TXFD_CFG_12_U (0x00391714) +#define PHYA_TXFD_CFG_12_U___RWC QCSR_REG_RW +#define PHYA_TXFD_CFG_12_U___POR 0x00040008 +#define PHYA_TXFD_CFG_12_U__POST_FEC_LFSR_TAP_SEL___POR 0x00040008 +#define PHYA_TXFD_CFG_12_U__POST_FEC_LFSR_TAP_SEL___M 0xFFFFFFFF +#define PHYA_TXFD_CFG_12_U__POST_FEC_LFSR_TAP_SEL___S 0 +#define PHYA_TXFD_CFG_12_U___M 0xFFFFFFFF +#define PHYA_TXFD_CFG_12_U___S 0 + +#define PHYA_TXFD_CFG_13_L (0x00391718) +#define PHYA_TXFD_CFG_13_L___RWC QCSR_REG_RW +#define PHYA_TXFD_CFG_13_L___POR 0x00000100 +#define PHYA_TXFD_CFG_13_L__RU0_IN_LOWER_80___POR 0x1 +#define PHYA_TXFD_CFG_13_L__FFT_CTRL_OVERRIDE___POR 0x0 +#define PHYA_TXFD_CFG_13_L__RU0_IN_LOWER_80___M 0x00000100 +#define PHYA_TXFD_CFG_13_L__RU0_IN_LOWER_80___S 8 +#define PHYA_TXFD_CFG_13_L__FFT_CTRL_OVERRIDE___M 0x00000001 +#define PHYA_TXFD_CFG_13_L__FFT_CTRL_OVERRIDE___S 0 +#define PHYA_TXFD_CFG_13_L___M 0x00000101 +#define PHYA_TXFD_CFG_13_L___S 0 + +#define PHYA_TXFD_CFG_14_L (0x00391720) +#define PHYA_TXFD_CFG_14_L___RWC QCSR_REG_RW +#define PHYA_TXFD_CFG_14_L___POR 0x00000200 +#define PHYA_TXFD_CFG_14_L__HT_CHAIN_CSD_DELTA_1___POR 0x02 +#define PHYA_TXFD_CFG_14_L__HT_CHAIN_CSD_DELTA_0___POR 0x00 +#define PHYA_TXFD_CFG_14_L__HT_CHAIN_CSD_DELTA_1___M 0x0000FF00 +#define PHYA_TXFD_CFG_14_L__HT_CHAIN_CSD_DELTA_1___S 8 +#define PHYA_TXFD_CFG_14_L__HT_CHAIN_CSD_DELTA_0___M 0x000000FF +#define PHYA_TXFD_CFG_14_L__HT_CHAIN_CSD_DELTA_0___S 0 +#define PHYA_TXFD_CFG_14_L___M 0x0000FFFF +#define PHYA_TXFD_CFG_14_L___S 0 + +#define PHYA_TXFD_CFG_15_L (0x00391728) +#define PHYA_TXFD_CFG_15_L___RWC QCSR_REG_RW +#define PHYA_TXFD_CFG_15_L___POR 0x00000200 +#define PHYA_TXFD_CFG_15_L__VHT_CHAIN_CSD_DELTA_1___POR 0x02 +#define PHYA_TXFD_CFG_15_L__VHT_CHAIN_CSD_DELTA_0___POR 0x00 +#define PHYA_TXFD_CFG_15_L__VHT_CHAIN_CSD_DELTA_1___M 0x0000FF00 +#define PHYA_TXFD_CFG_15_L__VHT_CHAIN_CSD_DELTA_1___S 8 +#define PHYA_TXFD_CFG_15_L__VHT_CHAIN_CSD_DELTA_0___M 0x000000FF +#define PHYA_TXFD_CFG_15_L__VHT_CHAIN_CSD_DELTA_0___S 0 +#define PHYA_TXFD_CFG_15_L___M 0x0000FFFF +#define PHYA_TXFD_CFG_15_L___S 0 + +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L (0x00391730) +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L___POR 0x00000EEF +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_31_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_30_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_29_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_28_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_27_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_26_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_25_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_24_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_23_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_22_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_21_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_20_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_19_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_18_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_17_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_16_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_15_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_14_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_13_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_12_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_11_0___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_10_0___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_9_0___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_8_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_7_0___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_6_0___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_5_0___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_4_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_3_0___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_2_0___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_1_0___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_0_0___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_31_0___M 0x80000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_31_0___S 31 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_30_0___M 0x40000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_30_0___S 30 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_29_0___M 0x20000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_29_0___S 29 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_28_0___M 0x10000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_28_0___S 28 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_27_0___M 0x08000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_27_0___S 27 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_26_0___M 0x04000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_26_0___S 26 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_25_0___M 0x02000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_25_0___S 25 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_24_0___M 0x01000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_24_0___S 24 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_23_0___M 0x00800000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_23_0___S 23 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_22_0___M 0x00400000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_22_0___S 22 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_21_0___M 0x00200000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_21_0___S 21 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_20_0___M 0x00100000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_20_0___S 20 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_19_0___M 0x00080000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_19_0___S 19 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_18_0___M 0x00040000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_18_0___S 18 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_17_0___M 0x00020000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_17_0___S 17 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_16_0___M 0x00010000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_16_0___S 16 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_15_0___M 0x00008000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_15_0___S 15 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_14_0___M 0x00004000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_14_0___S 14 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_13_0___M 0x00002000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_13_0___S 13 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_12_0___M 0x00001000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_12_0___S 12 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_11_0___M 0x00000800 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_11_0___S 11 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_10_0___M 0x00000400 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_10_0___S 10 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_9_0___M 0x00000200 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_9_0___S 9 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_8_0___M 0x00000100 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_8_0___S 8 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_7_0___M 0x00000080 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_7_0___S 7 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_6_0___M 0x00000040 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_6_0___S 6 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_5_0___M 0x00000020 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_5_0___S 5 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_4_0___M 0x00000010 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_4_0___S 4 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_3_0___M 0x00000008 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_3_0___S 3 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_2_0___M 0x00000004 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_2_0___S 2 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_1_0___M 0x00000002 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_1_0___S 1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_0_0___M 0x00000001 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L__HEAVYCLIP_EN_LUT_0_0___S 0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L___M 0xFFFFFFFF +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_L___S 0 + +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U (0x00391734) +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U___RWC QCSR_REG_RW +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U___POR 0x00000EEF +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_63_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_62_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_61_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_60_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_59_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_58_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_57_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_56_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_55_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_54_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_53_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_52_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_51_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_50_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_49_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_48_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_47_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_46_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_45_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_44_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_43_0___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_42_0___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_41_0___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_40_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_39_0___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_38_0___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_37_0___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_36_0___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_35_0___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_34_0___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_33_0___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_32_0___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_63_0___M 0x80000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_63_0___S 31 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_62_0___M 0x40000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_62_0___S 30 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_61_0___M 0x20000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_61_0___S 29 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_60_0___M 0x10000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_60_0___S 28 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_59_0___M 0x08000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_59_0___S 27 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_58_0___M 0x04000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_58_0___S 26 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_57_0___M 0x02000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_57_0___S 25 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_56_0___M 0x01000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_56_0___S 24 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_55_0___M 0x00800000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_55_0___S 23 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_54_0___M 0x00400000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_54_0___S 22 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_53_0___M 0x00200000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_53_0___S 21 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_52_0___M 0x00100000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_52_0___S 20 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_51_0___M 0x00080000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_51_0___S 19 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_50_0___M 0x00040000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_50_0___S 18 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_49_0___M 0x00020000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_49_0___S 17 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_48_0___M 0x00010000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_48_0___S 16 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_47_0___M 0x00008000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_47_0___S 15 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_46_0___M 0x00004000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_46_0___S 14 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_45_0___M 0x00002000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_45_0___S 13 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_44_0___M 0x00001000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_44_0___S 12 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_43_0___M 0x00000800 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_43_0___S 11 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_42_0___M 0x00000400 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_42_0___S 10 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_41_0___M 0x00000200 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_41_0___S 9 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_40_0___M 0x00000100 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_40_0___S 8 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_39_0___M 0x00000080 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_39_0___S 7 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_38_0___M 0x00000040 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_38_0___S 6 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_37_0___M 0x00000020 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_37_0___S 5 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_36_0___M 0x00000010 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_36_0___S 4 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_35_0___M 0x00000008 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_35_0___S 3 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_34_0___M 0x00000004 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_34_0___S 2 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_33_0___M 0x00000002 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_33_0___S 1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_32_0___M 0x00000001 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U__HEAVYCLIP_EN_LUT_32_0___S 0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U___M 0xFFFFFFFF +#define PHYA_TXFD_HEAVYCLIP_EN_LUT0_U___S 0 + +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L (0x00391738) +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L___POR 0x00000EEF +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_31_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_30_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_29_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_28_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_27_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_26_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_25_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_24_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_23_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_22_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_21_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_20_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_19_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_18_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_17_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_16_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_15_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_14_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_13_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_12_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_11_1___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_10_1___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_9_1___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_8_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_7_1___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_6_1___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_5_1___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_4_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_3_1___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_2_1___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_1_1___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_0_1___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_31_1___M 0x80000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_31_1___S 31 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_30_1___M 0x40000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_30_1___S 30 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_29_1___M 0x20000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_29_1___S 29 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_28_1___M 0x10000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_28_1___S 28 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_27_1___M 0x08000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_27_1___S 27 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_26_1___M 0x04000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_26_1___S 26 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_25_1___M 0x02000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_25_1___S 25 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_24_1___M 0x01000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_24_1___S 24 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_23_1___M 0x00800000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_23_1___S 23 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_22_1___M 0x00400000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_22_1___S 22 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_21_1___M 0x00200000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_21_1___S 21 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_20_1___M 0x00100000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_20_1___S 20 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_19_1___M 0x00080000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_19_1___S 19 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_18_1___M 0x00040000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_18_1___S 18 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_17_1___M 0x00020000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_17_1___S 17 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_16_1___M 0x00010000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_16_1___S 16 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_15_1___M 0x00008000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_15_1___S 15 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_14_1___M 0x00004000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_14_1___S 14 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_13_1___M 0x00002000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_13_1___S 13 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_12_1___M 0x00001000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_12_1___S 12 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_11_1___M 0x00000800 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_11_1___S 11 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_10_1___M 0x00000400 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_10_1___S 10 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_9_1___M 0x00000200 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_9_1___S 9 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_8_1___M 0x00000100 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_8_1___S 8 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_7_1___M 0x00000080 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_7_1___S 7 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_6_1___M 0x00000040 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_6_1___S 6 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_5_1___M 0x00000020 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_5_1___S 5 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_4_1___M 0x00000010 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_4_1___S 4 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_3_1___M 0x00000008 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_3_1___S 3 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_2_1___M 0x00000004 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_2_1___S 2 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_1_1___M 0x00000002 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_1_1___S 1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_0_1___M 0x00000001 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L__HEAVYCLIP_EN_LUT_0_1___S 0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L___M 0xFFFFFFFF +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_L___S 0 + +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U (0x0039173C) +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U___RWC QCSR_REG_RW +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U___POR 0x00000EEF +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_63_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_62_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_61_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_60_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_59_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_58_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_57_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_56_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_55_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_54_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_53_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_52_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_51_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_50_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_49_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_48_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_47_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_46_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_45_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_44_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_43_1___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_42_1___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_41_1___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_40_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_39_1___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_38_1___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_37_1___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_36_1___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_35_1___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_34_1___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_33_1___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_32_1___POR 0x1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_63_1___M 0x80000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_63_1___S 31 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_62_1___M 0x40000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_62_1___S 30 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_61_1___M 0x20000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_61_1___S 29 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_60_1___M 0x10000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_60_1___S 28 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_59_1___M 0x08000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_59_1___S 27 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_58_1___M 0x04000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_58_1___S 26 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_57_1___M 0x02000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_57_1___S 25 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_56_1___M 0x01000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_56_1___S 24 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_55_1___M 0x00800000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_55_1___S 23 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_54_1___M 0x00400000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_54_1___S 22 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_53_1___M 0x00200000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_53_1___S 21 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_52_1___M 0x00100000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_52_1___S 20 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_51_1___M 0x00080000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_51_1___S 19 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_50_1___M 0x00040000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_50_1___S 18 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_49_1___M 0x00020000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_49_1___S 17 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_48_1___M 0x00010000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_48_1___S 16 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_47_1___M 0x00008000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_47_1___S 15 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_46_1___M 0x00004000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_46_1___S 14 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_45_1___M 0x00002000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_45_1___S 13 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_44_1___M 0x00001000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_44_1___S 12 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_43_1___M 0x00000800 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_43_1___S 11 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_42_1___M 0x00000400 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_42_1___S 10 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_41_1___M 0x00000200 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_41_1___S 9 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_40_1___M 0x00000100 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_40_1___S 8 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_39_1___M 0x00000080 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_39_1___S 7 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_38_1___M 0x00000040 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_38_1___S 6 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_37_1___M 0x00000020 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_37_1___S 5 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_36_1___M 0x00000010 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_36_1___S 4 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_35_1___M 0x00000008 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_35_1___S 3 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_34_1___M 0x00000004 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_34_1___S 2 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_33_1___M 0x00000002 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_33_1___S 1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_32_1___M 0x00000001 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U__HEAVYCLIP_EN_LUT_32_1___S 0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U___M 0xFFFFFFFF +#define PHYA_TXFD_HEAVYCLIP_EN_LUT1_U___S 0 + +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L (0x00391740) +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L___POR 0x00000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_31_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_30_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_29_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_28_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_27_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_26_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_25_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_24_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_23_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_22_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_21_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_20_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_19_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_18_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_17_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_16_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_15_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_14_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_13_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_12_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_11_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_10_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_9_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_8_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_7_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_6_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_5_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_4_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_3_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_2_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_1_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_0_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_31_2___M 0x80000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_31_2___S 31 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_30_2___M 0x40000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_30_2___S 30 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_29_2___M 0x20000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_29_2___S 29 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_28_2___M 0x10000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_28_2___S 28 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_27_2___M 0x08000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_27_2___S 27 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_26_2___M 0x04000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_26_2___S 26 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_25_2___M 0x02000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_25_2___S 25 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_24_2___M 0x01000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_24_2___S 24 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_23_2___M 0x00800000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_23_2___S 23 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_22_2___M 0x00400000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_22_2___S 22 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_21_2___M 0x00200000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_21_2___S 21 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_20_2___M 0x00100000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_20_2___S 20 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_19_2___M 0x00080000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_19_2___S 19 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_18_2___M 0x00040000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_18_2___S 18 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_17_2___M 0x00020000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_17_2___S 17 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_16_2___M 0x00010000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_16_2___S 16 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_15_2___M 0x00008000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_15_2___S 15 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_14_2___M 0x00004000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_14_2___S 14 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_13_2___M 0x00002000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_13_2___S 13 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_12_2___M 0x00001000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_12_2___S 12 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_11_2___M 0x00000800 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_11_2___S 11 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_10_2___M 0x00000400 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_10_2___S 10 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_9_2___M 0x00000200 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_9_2___S 9 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_8_2___M 0x00000100 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_8_2___S 8 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_7_2___M 0x00000080 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_7_2___S 7 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_6_2___M 0x00000040 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_6_2___S 6 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_5_2___M 0x00000020 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_5_2___S 5 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_4_2___M 0x00000010 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_4_2___S 4 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_3_2___M 0x00000008 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_3_2___S 3 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_2_2___M 0x00000004 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_2_2___S 2 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_1_2___M 0x00000002 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_1_2___S 1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_0_2___M 0x00000001 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L__HEAVYCLIP_EN_LUT_0_2___S 0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L___M 0xFFFFFFFF +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_L___S 0 + +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U (0x00391744) +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U___RWC QCSR_REG_RW +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U___POR 0x00000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_63_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_62_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_61_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_60_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_59_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_58_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_57_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_56_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_55_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_54_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_53_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_52_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_51_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_50_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_49_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_48_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_47_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_46_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_45_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_44_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_43_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_42_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_41_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_40_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_39_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_38_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_37_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_36_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_35_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_34_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_33_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_32_2___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_63_2___M 0x80000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_63_2___S 31 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_62_2___M 0x40000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_62_2___S 30 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_61_2___M 0x20000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_61_2___S 29 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_60_2___M 0x10000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_60_2___S 28 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_59_2___M 0x08000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_59_2___S 27 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_58_2___M 0x04000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_58_2___S 26 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_57_2___M 0x02000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_57_2___S 25 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_56_2___M 0x01000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_56_2___S 24 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_55_2___M 0x00800000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_55_2___S 23 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_54_2___M 0x00400000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_54_2___S 22 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_53_2___M 0x00200000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_53_2___S 21 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_52_2___M 0x00100000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_52_2___S 20 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_51_2___M 0x00080000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_51_2___S 19 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_50_2___M 0x00040000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_50_2___S 18 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_49_2___M 0x00020000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_49_2___S 17 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_48_2___M 0x00010000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_48_2___S 16 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_47_2___M 0x00008000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_47_2___S 15 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_46_2___M 0x00004000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_46_2___S 14 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_45_2___M 0x00002000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_45_2___S 13 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_44_2___M 0x00001000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_44_2___S 12 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_43_2___M 0x00000800 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_43_2___S 11 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_42_2___M 0x00000400 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_42_2___S 10 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_41_2___M 0x00000200 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_41_2___S 9 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_40_2___M 0x00000100 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_40_2___S 8 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_39_2___M 0x00000080 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_39_2___S 7 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_38_2___M 0x00000040 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_38_2___S 6 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_37_2___M 0x00000020 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_37_2___S 5 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_36_2___M 0x00000010 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_36_2___S 4 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_35_2___M 0x00000008 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_35_2___S 3 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_34_2___M 0x00000004 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_34_2___S 2 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_33_2___M 0x00000002 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_33_2___S 1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_32_2___M 0x00000001 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U__HEAVYCLIP_EN_LUT_32_2___S 0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U___M 0xFFFFFFFF +#define PHYA_TXFD_HEAVYCLIP_EN_LUT2_U___S 0 + +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L (0x00391748) +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L___RWC QCSR_REG_RW +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L___POR 0x00000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_31_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_30_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_29_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_28_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_27_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_26_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_25_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_24_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_23_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_22_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_21_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_20_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_19_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_18_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_17_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_16_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_15_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_14_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_13_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_12_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_11_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_10_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_9_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_8_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_7_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_6_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_5_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_4_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_3_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_2_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_1_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_0_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_31_3___M 0x80000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_31_3___S 31 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_30_3___M 0x40000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_30_3___S 30 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_29_3___M 0x20000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_29_3___S 29 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_28_3___M 0x10000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_28_3___S 28 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_27_3___M 0x08000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_27_3___S 27 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_26_3___M 0x04000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_26_3___S 26 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_25_3___M 0x02000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_25_3___S 25 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_24_3___M 0x01000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_24_3___S 24 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_23_3___M 0x00800000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_23_3___S 23 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_22_3___M 0x00400000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_22_3___S 22 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_21_3___M 0x00200000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_21_3___S 21 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_20_3___M 0x00100000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_20_3___S 20 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_19_3___M 0x00080000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_19_3___S 19 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_18_3___M 0x00040000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_18_3___S 18 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_17_3___M 0x00020000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_17_3___S 17 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_16_3___M 0x00010000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_16_3___S 16 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_15_3___M 0x00008000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_15_3___S 15 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_14_3___M 0x00004000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_14_3___S 14 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_13_3___M 0x00002000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_13_3___S 13 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_12_3___M 0x00001000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_12_3___S 12 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_11_3___M 0x00000800 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_11_3___S 11 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_10_3___M 0x00000400 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_10_3___S 10 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_9_3___M 0x00000200 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_9_3___S 9 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_8_3___M 0x00000100 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_8_3___S 8 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_7_3___M 0x00000080 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_7_3___S 7 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_6_3___M 0x00000040 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_6_3___S 6 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_5_3___M 0x00000020 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_5_3___S 5 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_4_3___M 0x00000010 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_4_3___S 4 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_3_3___M 0x00000008 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_3_3___S 3 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_2_3___M 0x00000004 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_2_3___S 2 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_1_3___M 0x00000002 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_1_3___S 1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_0_3___M 0x00000001 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L__HEAVYCLIP_EN_LUT_0_3___S 0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L___M 0xFFFFFFFF +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_L___S 0 + +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U (0x0039174C) +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U___RWC QCSR_REG_RW +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U___POR 0x00000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_63_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_62_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_61_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_60_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_59_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_58_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_57_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_56_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_55_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_54_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_53_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_52_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_51_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_50_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_49_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_48_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_47_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_46_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_45_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_44_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_43_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_42_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_41_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_40_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_39_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_38_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_37_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_36_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_35_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_34_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_33_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_32_3___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_63_3___M 0x80000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_63_3___S 31 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_62_3___M 0x40000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_62_3___S 30 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_61_3___M 0x20000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_61_3___S 29 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_60_3___M 0x10000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_60_3___S 28 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_59_3___M 0x08000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_59_3___S 27 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_58_3___M 0x04000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_58_3___S 26 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_57_3___M 0x02000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_57_3___S 25 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_56_3___M 0x01000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_56_3___S 24 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_55_3___M 0x00800000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_55_3___S 23 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_54_3___M 0x00400000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_54_3___S 22 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_53_3___M 0x00200000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_53_3___S 21 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_52_3___M 0x00100000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_52_3___S 20 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_51_3___M 0x00080000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_51_3___S 19 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_50_3___M 0x00040000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_50_3___S 18 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_49_3___M 0x00020000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_49_3___S 17 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_48_3___M 0x00010000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_48_3___S 16 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_47_3___M 0x00008000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_47_3___S 15 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_46_3___M 0x00004000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_46_3___S 14 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_45_3___M 0x00002000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_45_3___S 13 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_44_3___M 0x00001000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_44_3___S 12 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_43_3___M 0x00000800 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_43_3___S 11 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_42_3___M 0x00000400 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_42_3___S 10 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_41_3___M 0x00000200 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_41_3___S 9 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_40_3___M 0x00000100 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_40_3___S 8 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_39_3___M 0x00000080 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_39_3___S 7 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_38_3___M 0x00000040 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_38_3___S 6 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_37_3___M 0x00000020 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_37_3___S 5 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_36_3___M 0x00000010 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_36_3___S 4 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_35_3___M 0x00000008 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_35_3___S 3 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_34_3___M 0x00000004 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_34_3___S 2 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_33_3___M 0x00000002 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_33_3___S 1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_32_3___M 0x00000001 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U__HEAVYCLIP_EN_LUT_32_3___S 0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U___M 0xFFFFFFFF +#define PHYA_TXFD_HEAVYCLIP_EN_LUT3_U___S 0 + +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L (0x00391750) +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L___RWC QCSR_REG_RW +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L___POR 0x00000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_31_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_30_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_29_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_28_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_27_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_26_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_25_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_24_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_23_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_22_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_21_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_20_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_19_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_18_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_17_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_16_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_15_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_14_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_13_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_12_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_11_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_10_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_9_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_8_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_7_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_6_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_5_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_4_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_3_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_2_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_1_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_0_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_31_4___M 0x80000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_31_4___S 31 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_30_4___M 0x40000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_30_4___S 30 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_29_4___M 0x20000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_29_4___S 29 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_28_4___M 0x10000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_28_4___S 28 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_27_4___M 0x08000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_27_4___S 27 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_26_4___M 0x04000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_26_4___S 26 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_25_4___M 0x02000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_25_4___S 25 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_24_4___M 0x01000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_24_4___S 24 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_23_4___M 0x00800000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_23_4___S 23 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_22_4___M 0x00400000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_22_4___S 22 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_21_4___M 0x00200000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_21_4___S 21 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_20_4___M 0x00100000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_20_4___S 20 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_19_4___M 0x00080000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_19_4___S 19 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_18_4___M 0x00040000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_18_4___S 18 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_17_4___M 0x00020000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_17_4___S 17 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_16_4___M 0x00010000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_16_4___S 16 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_15_4___M 0x00008000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_15_4___S 15 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_14_4___M 0x00004000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_14_4___S 14 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_13_4___M 0x00002000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_13_4___S 13 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_12_4___M 0x00001000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_12_4___S 12 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_11_4___M 0x00000800 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_11_4___S 11 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_10_4___M 0x00000400 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_10_4___S 10 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_9_4___M 0x00000200 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_9_4___S 9 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_8_4___M 0x00000100 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_8_4___S 8 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_7_4___M 0x00000080 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_7_4___S 7 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_6_4___M 0x00000040 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_6_4___S 6 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_5_4___M 0x00000020 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_5_4___S 5 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_4_4___M 0x00000010 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_4_4___S 4 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_3_4___M 0x00000008 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_3_4___S 3 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_2_4___M 0x00000004 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_2_4___S 2 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_1_4___M 0x00000002 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_1_4___S 1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_0_4___M 0x00000001 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L__HEAVYCLIP_EN_LUT_0_4___S 0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L___M 0xFFFFFFFF +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_L___S 0 + +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U (0x00391754) +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U___RWC QCSR_REG_RW +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U___POR 0x00000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_63_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_62_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_61_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_60_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_59_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_58_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_57_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_56_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_55_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_54_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_53_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_52_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_51_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_50_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_49_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_48_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_47_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_46_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_45_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_44_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_43_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_42_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_41_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_40_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_39_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_38_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_37_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_36_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_35_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_34_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_33_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_32_4___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_63_4___M 0x80000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_63_4___S 31 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_62_4___M 0x40000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_62_4___S 30 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_61_4___M 0x20000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_61_4___S 29 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_60_4___M 0x10000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_60_4___S 28 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_59_4___M 0x08000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_59_4___S 27 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_58_4___M 0x04000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_58_4___S 26 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_57_4___M 0x02000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_57_4___S 25 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_56_4___M 0x01000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_56_4___S 24 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_55_4___M 0x00800000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_55_4___S 23 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_54_4___M 0x00400000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_54_4___S 22 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_53_4___M 0x00200000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_53_4___S 21 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_52_4___M 0x00100000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_52_4___S 20 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_51_4___M 0x00080000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_51_4___S 19 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_50_4___M 0x00040000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_50_4___S 18 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_49_4___M 0x00020000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_49_4___S 17 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_48_4___M 0x00010000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_48_4___S 16 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_47_4___M 0x00008000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_47_4___S 15 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_46_4___M 0x00004000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_46_4___S 14 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_45_4___M 0x00002000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_45_4___S 13 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_44_4___M 0x00001000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_44_4___S 12 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_43_4___M 0x00000800 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_43_4___S 11 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_42_4___M 0x00000400 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_42_4___S 10 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_41_4___M 0x00000200 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_41_4___S 9 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_40_4___M 0x00000100 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_40_4___S 8 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_39_4___M 0x00000080 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_39_4___S 7 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_38_4___M 0x00000040 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_38_4___S 6 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_37_4___M 0x00000020 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_37_4___S 5 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_36_4___M 0x00000010 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_36_4___S 4 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_35_4___M 0x00000008 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_35_4___S 3 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_34_4___M 0x00000004 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_34_4___S 2 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_33_4___M 0x00000002 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_33_4___S 1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_32_4___M 0x00000001 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U__HEAVYCLIP_EN_LUT_32_4___S 0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U___M 0xFFFFFFFF +#define PHYA_TXFD_HEAVYCLIP_EN_LUT4_U___S 0 + +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L (0x00391758) +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L___RWC QCSR_REG_RW +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L___POR 0x00000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_31_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_30_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_29_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_28_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_27_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_26_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_25_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_24_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_23_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_22_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_21_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_20_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_19_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_18_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_17_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_16_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_15_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_14_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_13_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_12_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_11_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_10_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_9_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_8_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_7_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_6_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_5_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_4_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_3_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_2_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_1_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_0_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_31_5___M 0x80000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_31_5___S 31 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_30_5___M 0x40000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_30_5___S 30 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_29_5___M 0x20000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_29_5___S 29 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_28_5___M 0x10000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_28_5___S 28 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_27_5___M 0x08000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_27_5___S 27 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_26_5___M 0x04000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_26_5___S 26 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_25_5___M 0x02000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_25_5___S 25 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_24_5___M 0x01000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_24_5___S 24 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_23_5___M 0x00800000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_23_5___S 23 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_22_5___M 0x00400000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_22_5___S 22 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_21_5___M 0x00200000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_21_5___S 21 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_20_5___M 0x00100000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_20_5___S 20 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_19_5___M 0x00080000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_19_5___S 19 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_18_5___M 0x00040000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_18_5___S 18 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_17_5___M 0x00020000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_17_5___S 17 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_16_5___M 0x00010000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_16_5___S 16 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_15_5___M 0x00008000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_15_5___S 15 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_14_5___M 0x00004000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_14_5___S 14 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_13_5___M 0x00002000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_13_5___S 13 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_12_5___M 0x00001000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_12_5___S 12 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_11_5___M 0x00000800 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_11_5___S 11 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_10_5___M 0x00000400 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_10_5___S 10 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_9_5___M 0x00000200 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_9_5___S 9 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_8_5___M 0x00000100 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_8_5___S 8 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_7_5___M 0x00000080 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_7_5___S 7 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_6_5___M 0x00000040 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_6_5___S 6 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_5_5___M 0x00000020 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_5_5___S 5 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_4_5___M 0x00000010 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_4_5___S 4 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_3_5___M 0x00000008 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_3_5___S 3 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_2_5___M 0x00000004 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_2_5___S 2 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_1_5___M 0x00000002 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_1_5___S 1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_0_5___M 0x00000001 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L__HEAVYCLIP_EN_LUT_0_5___S 0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L___M 0xFFFFFFFF +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_L___S 0 + +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U (0x0039175C) +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U___RWC QCSR_REG_RW +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U___POR 0x00000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_63_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_62_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_61_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_60_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_59_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_58_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_57_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_56_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_55_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_54_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_53_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_52_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_51_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_50_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_49_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_48_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_47_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_46_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_45_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_44_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_43_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_42_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_41_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_40_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_39_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_38_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_37_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_36_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_35_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_34_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_33_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_32_5___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_63_5___M 0x80000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_63_5___S 31 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_62_5___M 0x40000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_62_5___S 30 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_61_5___M 0x20000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_61_5___S 29 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_60_5___M 0x10000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_60_5___S 28 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_59_5___M 0x08000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_59_5___S 27 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_58_5___M 0x04000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_58_5___S 26 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_57_5___M 0x02000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_57_5___S 25 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_56_5___M 0x01000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_56_5___S 24 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_55_5___M 0x00800000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_55_5___S 23 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_54_5___M 0x00400000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_54_5___S 22 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_53_5___M 0x00200000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_53_5___S 21 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_52_5___M 0x00100000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_52_5___S 20 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_51_5___M 0x00080000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_51_5___S 19 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_50_5___M 0x00040000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_50_5___S 18 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_49_5___M 0x00020000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_49_5___S 17 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_48_5___M 0x00010000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_48_5___S 16 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_47_5___M 0x00008000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_47_5___S 15 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_46_5___M 0x00004000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_46_5___S 14 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_45_5___M 0x00002000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_45_5___S 13 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_44_5___M 0x00001000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_44_5___S 12 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_43_5___M 0x00000800 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_43_5___S 11 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_42_5___M 0x00000400 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_42_5___S 10 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_41_5___M 0x00000200 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_41_5___S 9 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_40_5___M 0x00000100 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_40_5___S 8 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_39_5___M 0x00000080 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_39_5___S 7 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_38_5___M 0x00000040 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_38_5___S 6 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_37_5___M 0x00000020 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_37_5___S 5 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_36_5___M 0x00000010 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_36_5___S 4 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_35_5___M 0x00000008 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_35_5___S 3 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_34_5___M 0x00000004 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_34_5___S 2 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_33_5___M 0x00000002 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_33_5___S 1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_32_5___M 0x00000001 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U__HEAVYCLIP_EN_LUT_32_5___S 0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U___M 0xFFFFFFFF +#define PHYA_TXFD_HEAVYCLIP_EN_LUT5_U___S 0 + +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L (0x00391760) +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L___RWC QCSR_REG_RW +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L___POR 0x00000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_31_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_30_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_29_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_28_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_27_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_26_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_25_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_24_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_23_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_22_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_21_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_20_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_19_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_18_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_17_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_16_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_15_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_14_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_13_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_12_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_11_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_10_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_9_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_8_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_7_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_6_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_5_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_4_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_3_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_2_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_1_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_0_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_31_6___M 0x80000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_31_6___S 31 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_30_6___M 0x40000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_30_6___S 30 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_29_6___M 0x20000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_29_6___S 29 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_28_6___M 0x10000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_28_6___S 28 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_27_6___M 0x08000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_27_6___S 27 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_26_6___M 0x04000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_26_6___S 26 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_25_6___M 0x02000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_25_6___S 25 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_24_6___M 0x01000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_24_6___S 24 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_23_6___M 0x00800000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_23_6___S 23 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_22_6___M 0x00400000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_22_6___S 22 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_21_6___M 0x00200000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_21_6___S 21 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_20_6___M 0x00100000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_20_6___S 20 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_19_6___M 0x00080000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_19_6___S 19 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_18_6___M 0x00040000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_18_6___S 18 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_17_6___M 0x00020000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_17_6___S 17 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_16_6___M 0x00010000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_16_6___S 16 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_15_6___M 0x00008000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_15_6___S 15 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_14_6___M 0x00004000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_14_6___S 14 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_13_6___M 0x00002000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_13_6___S 13 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_12_6___M 0x00001000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_12_6___S 12 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_11_6___M 0x00000800 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_11_6___S 11 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_10_6___M 0x00000400 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_10_6___S 10 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_9_6___M 0x00000200 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_9_6___S 9 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_8_6___M 0x00000100 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_8_6___S 8 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_7_6___M 0x00000080 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_7_6___S 7 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_6_6___M 0x00000040 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_6_6___S 6 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_5_6___M 0x00000020 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_5_6___S 5 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_4_6___M 0x00000010 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_4_6___S 4 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_3_6___M 0x00000008 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_3_6___S 3 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_2_6___M 0x00000004 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_2_6___S 2 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_1_6___M 0x00000002 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_1_6___S 1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_0_6___M 0x00000001 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L__HEAVYCLIP_EN_LUT_0_6___S 0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L___M 0xFFFFFFFF +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_L___S 0 + +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U (0x00391764) +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U___RWC QCSR_REG_RW +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U___POR 0x00000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_63_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_62_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_61_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_60_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_59_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_58_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_57_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_56_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_55_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_54_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_53_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_52_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_51_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_50_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_49_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_48_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_47_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_46_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_45_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_44_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_43_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_42_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_41_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_40_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_39_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_38_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_37_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_36_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_35_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_34_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_33_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_32_6___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_63_6___M 0x80000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_63_6___S 31 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_62_6___M 0x40000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_62_6___S 30 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_61_6___M 0x20000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_61_6___S 29 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_60_6___M 0x10000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_60_6___S 28 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_59_6___M 0x08000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_59_6___S 27 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_58_6___M 0x04000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_58_6___S 26 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_57_6___M 0x02000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_57_6___S 25 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_56_6___M 0x01000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_56_6___S 24 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_55_6___M 0x00800000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_55_6___S 23 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_54_6___M 0x00400000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_54_6___S 22 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_53_6___M 0x00200000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_53_6___S 21 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_52_6___M 0x00100000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_52_6___S 20 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_51_6___M 0x00080000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_51_6___S 19 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_50_6___M 0x00040000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_50_6___S 18 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_49_6___M 0x00020000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_49_6___S 17 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_48_6___M 0x00010000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_48_6___S 16 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_47_6___M 0x00008000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_47_6___S 15 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_46_6___M 0x00004000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_46_6___S 14 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_45_6___M 0x00002000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_45_6___S 13 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_44_6___M 0x00001000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_44_6___S 12 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_43_6___M 0x00000800 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_43_6___S 11 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_42_6___M 0x00000400 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_42_6___S 10 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_41_6___M 0x00000200 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_41_6___S 9 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_40_6___M 0x00000100 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_40_6___S 8 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_39_6___M 0x00000080 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_39_6___S 7 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_38_6___M 0x00000040 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_38_6___S 6 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_37_6___M 0x00000020 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_37_6___S 5 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_36_6___M 0x00000010 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_36_6___S 4 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_35_6___M 0x00000008 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_35_6___S 3 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_34_6___M 0x00000004 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_34_6___S 2 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_33_6___M 0x00000002 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_33_6___S 1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_32_6___M 0x00000001 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U__HEAVYCLIP_EN_LUT_32_6___S 0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U___M 0xFFFFFFFF +#define PHYA_TXFD_HEAVYCLIP_EN_LUT6_U___S 0 + +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L (0x00391768) +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L___RWC QCSR_REG_RW +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L___POR 0x00000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_31_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_30_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_29_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_28_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_27_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_26_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_25_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_24_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_23_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_22_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_21_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_20_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_19_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_18_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_17_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_16_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_15_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_14_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_13_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_12_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_11_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_10_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_9_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_8_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_7_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_6_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_5_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_4_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_3_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_2_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_1_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_0_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_31_7___M 0x80000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_31_7___S 31 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_30_7___M 0x40000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_30_7___S 30 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_29_7___M 0x20000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_29_7___S 29 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_28_7___M 0x10000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_28_7___S 28 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_27_7___M 0x08000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_27_7___S 27 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_26_7___M 0x04000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_26_7___S 26 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_25_7___M 0x02000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_25_7___S 25 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_24_7___M 0x01000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_24_7___S 24 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_23_7___M 0x00800000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_23_7___S 23 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_22_7___M 0x00400000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_22_7___S 22 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_21_7___M 0x00200000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_21_7___S 21 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_20_7___M 0x00100000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_20_7___S 20 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_19_7___M 0x00080000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_19_7___S 19 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_18_7___M 0x00040000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_18_7___S 18 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_17_7___M 0x00020000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_17_7___S 17 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_16_7___M 0x00010000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_16_7___S 16 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_15_7___M 0x00008000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_15_7___S 15 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_14_7___M 0x00004000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_14_7___S 14 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_13_7___M 0x00002000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_13_7___S 13 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_12_7___M 0x00001000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_12_7___S 12 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_11_7___M 0x00000800 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_11_7___S 11 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_10_7___M 0x00000400 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_10_7___S 10 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_9_7___M 0x00000200 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_9_7___S 9 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_8_7___M 0x00000100 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_8_7___S 8 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_7_7___M 0x00000080 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_7_7___S 7 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_6_7___M 0x00000040 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_6_7___S 6 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_5_7___M 0x00000020 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_5_7___S 5 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_4_7___M 0x00000010 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_4_7___S 4 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_3_7___M 0x00000008 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_3_7___S 3 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_2_7___M 0x00000004 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_2_7___S 2 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_1_7___M 0x00000002 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_1_7___S 1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_0_7___M 0x00000001 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L__HEAVYCLIP_EN_LUT_0_7___S 0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L___M 0xFFFFFFFF +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_L___S 0 + +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U (0x0039176C) +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U___RWC QCSR_REG_RW +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U___POR 0x00000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_63_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_62_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_61_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_60_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_59_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_58_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_57_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_56_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_55_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_54_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_53_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_52_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_51_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_50_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_49_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_48_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_47_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_46_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_45_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_44_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_43_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_42_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_41_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_40_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_39_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_38_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_37_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_36_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_35_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_34_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_33_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_32_7___POR 0x0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_63_7___M 0x80000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_63_7___S 31 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_62_7___M 0x40000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_62_7___S 30 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_61_7___M 0x20000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_61_7___S 29 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_60_7___M 0x10000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_60_7___S 28 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_59_7___M 0x08000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_59_7___S 27 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_58_7___M 0x04000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_58_7___S 26 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_57_7___M 0x02000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_57_7___S 25 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_56_7___M 0x01000000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_56_7___S 24 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_55_7___M 0x00800000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_55_7___S 23 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_54_7___M 0x00400000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_54_7___S 22 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_53_7___M 0x00200000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_53_7___S 21 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_52_7___M 0x00100000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_52_7___S 20 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_51_7___M 0x00080000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_51_7___S 19 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_50_7___M 0x00040000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_50_7___S 18 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_49_7___M 0x00020000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_49_7___S 17 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_48_7___M 0x00010000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_48_7___S 16 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_47_7___M 0x00008000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_47_7___S 15 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_46_7___M 0x00004000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_46_7___S 14 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_45_7___M 0x00002000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_45_7___S 13 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_44_7___M 0x00001000 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_44_7___S 12 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_43_7___M 0x00000800 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_43_7___S 11 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_42_7___M 0x00000400 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_42_7___S 10 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_41_7___M 0x00000200 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_41_7___S 9 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_40_7___M 0x00000100 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_40_7___S 8 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_39_7___M 0x00000080 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_39_7___S 7 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_38_7___M 0x00000040 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_38_7___S 6 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_37_7___M 0x00000020 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_37_7___S 5 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_36_7___M 0x00000010 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_36_7___S 4 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_35_7___M 0x00000008 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_35_7___S 3 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_34_7___M 0x00000004 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_34_7___S 2 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_33_7___M 0x00000002 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_33_7___S 1 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_32_7___M 0x00000001 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U__HEAVYCLIP_EN_LUT_32_7___S 0 +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U___M 0xFFFFFFFF +#define PHYA_TXFD_HEAVYCLIP_EN_LUT7_U___S 0 + +#define PHYA_TXFD_PUBLIC_SPARE_L (0x00391770) +#define PHYA_TXFD_PUBLIC_SPARE_L___RWC QCSR_REG_RW +#define PHYA_TXFD_PUBLIC_SPARE_L___POR 0x00000000 +#define PHYA_TXFD_PUBLIC_SPARE_L__PUBLIC_SPARE_0___POR 0x00000000 +#define PHYA_TXFD_PUBLIC_SPARE_L__PUBLIC_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXFD_PUBLIC_SPARE_L__PUBLIC_SPARE_0___S 0 +#define PHYA_TXFD_PUBLIC_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXFD_PUBLIC_SPARE_L___S 0 + +#define PHYA_TXFD_PUBLIC_SPARE_U (0x00391774) +#define PHYA_TXFD_PUBLIC_SPARE_U___RWC QCSR_REG_RW +#define PHYA_TXFD_PUBLIC_SPARE_U___POR 0x00000000 +#define PHYA_TXFD_PUBLIC_SPARE_U__PUBLIC_SPARE_1___POR 0x00000000 +#define PHYA_TXFD_PUBLIC_SPARE_U__PUBLIC_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXFD_PUBLIC_SPARE_U__PUBLIC_SPARE_1___S 0 +#define PHYA_TXFD_PUBLIC_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXFD_PUBLIC_SPARE_U___S 0 + +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG0_L (0x00391778) +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG0_L___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG0_L__TLV_INTERRUPT_CFG_0_0___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG0_L__TLV_INTERRUPT_CFG_0_0___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG0_L__TLV_INTERRUPT_CFG_0_0___S 0 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG0_L___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG0_L___S 0 + +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG0_U (0x0039177C) +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG0_U___RWC QCSR_REG_RW +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG0_U___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG0_U__TLV_INTERRUPT_CFG_1_0___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG0_U__TLV_INTERRUPT_CFG_1_0___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG0_U__TLV_INTERRUPT_CFG_1_0___S 0 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG0_U___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG0_U___S 0 + +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG1_L (0x00391780) +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG1_L___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG1_L__TLV_INTERRUPT_CFG_0_1___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG1_L__TLV_INTERRUPT_CFG_0_1___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG1_L__TLV_INTERRUPT_CFG_0_1___S 0 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG1_L___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG1_L___S 0 + +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG1_U (0x00391784) +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG1_U___RWC QCSR_REG_RW +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG1_U___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG1_U__TLV_INTERRUPT_CFG_1_1___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG1_U__TLV_INTERRUPT_CFG_1_1___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG1_U__TLV_INTERRUPT_CFG_1_1___S 0 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG1_U___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG1_U___S 0 + +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG2_L (0x00391788) +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG2_L___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG2_L__TLV_INTERRUPT_CFG_0_2___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG2_L__TLV_INTERRUPT_CFG_0_2___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG2_L__TLV_INTERRUPT_CFG_0_2___S 0 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG2_L___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG2_L___S 0 + +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG2_U (0x0039178C) +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG2_U___RWC QCSR_REG_RW +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG2_U___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG2_U__TLV_INTERRUPT_CFG_1_2___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG2_U__TLV_INTERRUPT_CFG_1_2___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG2_U__TLV_INTERRUPT_CFG_1_2___S 0 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG2_U___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG2_U___S 0 + +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG3_L (0x00391790) +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG3_L___RWC QCSR_REG_RW +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG3_L___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG3_L__TLV_INTERRUPT_CFG_0_3___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG3_L__TLV_INTERRUPT_CFG_0_3___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG3_L__TLV_INTERRUPT_CFG_0_3___S 0 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG3_L___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG3_L___S 0 + +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG3_U (0x00391794) +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG3_U___RWC QCSR_REG_RW +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG3_U___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG3_U__TLV_INTERRUPT_CFG_1_3___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG3_U__TLV_INTERRUPT_CFG_1_3___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG3_U__TLV_INTERRUPT_CFG_1_3___S 0 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG3_U___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG3_U___S 0 + +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG4_L (0x00391798) +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG4_L___RWC QCSR_REG_RW +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG4_L___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG4_L__TLV_INTERRUPT_CFG_0_4___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG4_L__TLV_INTERRUPT_CFG_0_4___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG4_L__TLV_INTERRUPT_CFG_0_4___S 0 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG4_L___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG4_L___S 0 + +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG4_U (0x0039179C) +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG4_U___RWC QCSR_REG_RW +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG4_U___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG4_U__TLV_INTERRUPT_CFG_1_4___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG4_U__TLV_INTERRUPT_CFG_1_4___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG4_U__TLV_INTERRUPT_CFG_1_4___S 0 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG4_U___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG4_U___S 0 + +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG5_L (0x003917A0) +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG5_L___RWC QCSR_REG_RW +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG5_L___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG5_L__TLV_INTERRUPT_CFG_0_5___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG5_L__TLV_INTERRUPT_CFG_0_5___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG5_L__TLV_INTERRUPT_CFG_0_5___S 0 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG5_L___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG5_L___S 0 + +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG5_U (0x003917A4) +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG5_U___RWC QCSR_REG_RW +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG5_U___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG5_U__TLV_INTERRUPT_CFG_1_5___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG5_U__TLV_INTERRUPT_CFG_1_5___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG5_U__TLV_INTERRUPT_CFG_1_5___S 0 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG5_U___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG5_U___S 0 + +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG6_L (0x003917A8) +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG6_L___RWC QCSR_REG_RW +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG6_L___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG6_L__TLV_INTERRUPT_CFG_0_6___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG6_L__TLV_INTERRUPT_CFG_0_6___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG6_L__TLV_INTERRUPT_CFG_0_6___S 0 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG6_L___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG6_L___S 0 + +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG6_U (0x003917AC) +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG6_U___RWC QCSR_REG_RW +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG6_U___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG6_U__TLV_INTERRUPT_CFG_1_6___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG6_U__TLV_INTERRUPT_CFG_1_6___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG6_U__TLV_INTERRUPT_CFG_1_6___S 0 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG6_U___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG6_U___S 0 + +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG7_L (0x003917B0) +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG7_L___RWC QCSR_REG_RW +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG7_L___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG7_L__TLV_INTERRUPT_CFG_0_7___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG7_L__TLV_INTERRUPT_CFG_0_7___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG7_L__TLV_INTERRUPT_CFG_0_7___S 0 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG7_L___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG7_L___S 0 + +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG7_U (0x003917B4) +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG7_U___RWC QCSR_REG_RW +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG7_U___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG7_U__TLV_INTERRUPT_CFG_1_7___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG7_U__TLV_INTERRUPT_CFG_1_7___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG7_U__TLV_INTERRUPT_CFG_1_7___S 0 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG7_U___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG7_U___S 0 + +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG8_L (0x003917B8) +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG8_L___RWC QCSR_REG_RW +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG8_L___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG8_L__TLV_INTERRUPT_CFG_0_8___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG8_L__TLV_INTERRUPT_CFG_0_8___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG8_L__TLV_INTERRUPT_CFG_0_8___S 0 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG8_L___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG8_L___S 0 + +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG8_U (0x003917BC) +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG8_U___RWC QCSR_REG_RW +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG8_U___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG8_U__TLV_INTERRUPT_CFG_1_8___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG8_U__TLV_INTERRUPT_CFG_1_8___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG8_U__TLV_INTERRUPT_CFG_1_8___S 0 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG8_U___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG8_U___S 0 + +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG9_L (0x003917C0) +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG9_L___RWC QCSR_REG_RW +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG9_L___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG9_L__TLV_INTERRUPT_CFG_0_9___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG9_L__TLV_INTERRUPT_CFG_0_9___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG9_L__TLV_INTERRUPT_CFG_0_9___S 0 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG9_L___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG9_L___S 0 + +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG9_U (0x003917C4) +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG9_U___RWC QCSR_REG_RW +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG9_U___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG9_U__TLV_INTERRUPT_CFG_1_9___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG9_U__TLV_INTERRUPT_CFG_1_9___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG9_U__TLV_INTERRUPT_CFG_1_9___S 0 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG9_U___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG9_U___S 0 + +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG10_L (0x003917C8) +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG10_L___RWC QCSR_REG_RW +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG10_L___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG10_L__TLV_INTERRUPT_CFG_0_10___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG10_L__TLV_INTERRUPT_CFG_0_10___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG10_L__TLV_INTERRUPT_CFG_0_10___S 0 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG10_L___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG10_L___S 0 + +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG10_U (0x003917CC) +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG10_U___RWC QCSR_REG_RW +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG10_U___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG10_U__TLV_INTERRUPT_CFG_1_10___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG10_U__TLV_INTERRUPT_CFG_1_10___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG10_U__TLV_INTERRUPT_CFG_1_10___S 0 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG10_U___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG10_U___S 0 + +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG11_L (0x003917D0) +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG11_L___RWC QCSR_REG_RW +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG11_L___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG11_L__TLV_INTERRUPT_CFG_0_11___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG11_L__TLV_INTERRUPT_CFG_0_11___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG11_L__TLV_INTERRUPT_CFG_0_11___S 0 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG11_L___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG11_L___S 0 + +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG11_U (0x003917D4) +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG11_U___RWC QCSR_REG_RW +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG11_U___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG11_U__TLV_INTERRUPT_CFG_1_11___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG11_U__TLV_INTERRUPT_CFG_1_11___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG11_U__TLV_INTERRUPT_CFG_1_11___S 0 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG11_U___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG11_U___S 0 + +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG12_L (0x003917D8) +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG12_L___RWC QCSR_REG_RW +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG12_L___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG12_L__TLV_INTERRUPT_CFG_0_12___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG12_L__TLV_INTERRUPT_CFG_0_12___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG12_L__TLV_INTERRUPT_CFG_0_12___S 0 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG12_L___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG12_L___S 0 + +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG12_U (0x003917DC) +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG12_U___RWC QCSR_REG_RW +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG12_U___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG12_U__TLV_INTERRUPT_CFG_1_12___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG12_U__TLV_INTERRUPT_CFG_1_12___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG12_U__TLV_INTERRUPT_CFG_1_12___S 0 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG12_U___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG12_U___S 0 + +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG13_L (0x003917E0) +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG13_L___RWC QCSR_REG_RW +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG13_L___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG13_L__TLV_INTERRUPT_CFG_0_13___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG13_L__TLV_INTERRUPT_CFG_0_13___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG13_L__TLV_INTERRUPT_CFG_0_13___S 0 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG13_L___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG13_L___S 0 + +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG13_U (0x003917E4) +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG13_U___RWC QCSR_REG_RW +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG13_U___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG13_U__TLV_INTERRUPT_CFG_1_13___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG13_U__TLV_INTERRUPT_CFG_1_13___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG13_U__TLV_INTERRUPT_CFG_1_13___S 0 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG13_U___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG13_U___S 0 + +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG14_L (0x003917E8) +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG14_L___RWC QCSR_REG_RW +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG14_L___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG14_L__TLV_INTERRUPT_CFG_0_14___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG14_L__TLV_INTERRUPT_CFG_0_14___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG14_L__TLV_INTERRUPT_CFG_0_14___S 0 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG14_L___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG14_L___S 0 + +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG14_U (0x003917EC) +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG14_U___RWC QCSR_REG_RW +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG14_U___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG14_U__TLV_INTERRUPT_CFG_1_14___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG14_U__TLV_INTERRUPT_CFG_1_14___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG14_U__TLV_INTERRUPT_CFG_1_14___S 0 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG14_U___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG14_U___S 0 + +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG15_L (0x003917F0) +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG15_L___RWC QCSR_REG_RW +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG15_L___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG15_L__TLV_INTERRUPT_CFG_0_15___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG15_L__TLV_INTERRUPT_CFG_0_15___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG15_L__TLV_INTERRUPT_CFG_0_15___S 0 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG15_L___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG15_L___S 0 + +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG15_U (0x003917F4) +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG15_U___RWC QCSR_REG_RW +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG15_U___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG15_U__TLV_INTERRUPT_CFG_1_15___POR 0x00000000 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG15_U__TLV_INTERRUPT_CFG_1_15___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG15_U__TLV_INTERRUPT_CFG_1_15___S 0 +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG15_U___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_INTERRUPT_CONFIG15_U___S 0 + +#define PHYA_TXFD_PRIVATE_SPARE_L (0x003917F8) +#define PHYA_TXFD_PRIVATE_SPARE_L___RWC QCSR_REG_RW +#define PHYA_TXFD_PRIVATE_SPARE_L___POR 0x00000000 +#define PHYA_TXFD_PRIVATE_SPARE_L__PRIVATE_SPARE_0___POR 0x00000000 +#define PHYA_TXFD_PRIVATE_SPARE_L__PRIVATE_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXFD_PRIVATE_SPARE_L__PRIVATE_SPARE_0___S 0 +#define PHYA_TXFD_PRIVATE_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXFD_PRIVATE_SPARE_L___S 0 + +#define PHYA_TXFD_PRIVATE_SPARE_U (0x003917FC) +#define PHYA_TXFD_PRIVATE_SPARE_U___RWC QCSR_REG_RW +#define PHYA_TXFD_PRIVATE_SPARE_U___POR 0x00000000 +#define PHYA_TXFD_PRIVATE_SPARE_U__PRIVATE_SPARE_1___POR 0x00000000 +#define PHYA_TXFD_PRIVATE_SPARE_U__PRIVATE_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXFD_PRIVATE_SPARE_U__PRIVATE_SPARE_1___S 0 +#define PHYA_TXFD_PRIVATE_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXFD_PRIVATE_SPARE_U___S 0 + +#define PHYA_TXFD_PRE_PKT_START_WR_0_L (0x00391800) +#define PHYA_TXFD_PRE_PKT_START_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_PRE_PKT_START_WR_0_L___POR 0x00000100 +#define PHYA_TXFD_PRE_PKT_START_WR_0_L__PEF_EN___POR 0x1 +#define PHYA_TXFD_PRE_PKT_START_WR_0_L__HEAVYCLIP_EN_PER_PACKET___POR 0x0 +#define PHYA_TXFD_PRE_PKT_START_WR_0_L__PEF_EN___M 0x00000100 +#define PHYA_TXFD_PRE_PKT_START_WR_0_L__PEF_EN___S 8 +#define PHYA_TXFD_PRE_PKT_START_WR_0_L__HEAVYCLIP_EN_PER_PACKET___M 0x00000001 +#define PHYA_TXFD_PRE_PKT_START_WR_0_L__HEAVYCLIP_EN_PER_PACKET___S 0 +#define PHYA_TXFD_PRE_PKT_START_WR_0_L___M 0x00000101 +#define PHYA_TXFD_PRE_PKT_START_WR_0_L___S 0 + +#define PHYA_TXFD_PRE_PKT_START_WR_0_U (0x00391804) +#define PHYA_TXFD_PRE_PKT_START_WR_0_U___RWC QCSR_REG_RW +#define PHYA_TXFD_PRE_PKT_START_WR_0_U___POR 0x00000033 +#define PHYA_TXFD_PRE_PKT_START_WR_0_U__LSTF_FFT_SCALE___POR 0x000033 +#define PHYA_TXFD_PRE_PKT_START_WR_0_U__LSTF_FFT_SCALE___M 0x00FFFFFF +#define PHYA_TXFD_PRE_PKT_START_WR_0_U__LSTF_FFT_SCALE___S 0 +#define PHYA_TXFD_PRE_PKT_START_WR_0_U___M 0x00FFFFFF +#define PHYA_TXFD_PRE_PKT_START_WR_0_U___S 0 + +#define PHYA_TXFD_PRE_PKT_START_WR_1_L (0x00391808) +#define PHYA_TXFD_PRE_PKT_START_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_PRE_PKT_START_WR_1_L___POR 0xFF010100 +#define PHYA_TXFD_PRE_PKT_START_WR_1_L__SUBBAND_CHANNEL_BONDING_MASK___POR 0xFF +#define PHYA_TXFD_PRE_PKT_START_WR_1_L__BEAM_CHANGE___POR 0x1 +#define PHYA_TXFD_PRE_PKT_START_WR_1_L__CHAIN_MASK___POR 0x01 +#define PHYA_TXFD_PRE_PKT_START_WR_1_L__UL_TRIG_STREAM_OFFSET___POR 0x0 +#define PHYA_TXFD_PRE_PKT_START_WR_1_L__SUBBAND_CHANNEL_BONDING_MASK___M 0xFF000000 +#define PHYA_TXFD_PRE_PKT_START_WR_1_L__SUBBAND_CHANNEL_BONDING_MASK___S 24 +#define PHYA_TXFD_PRE_PKT_START_WR_1_L__BEAM_CHANGE___M 0x00010000 +#define PHYA_TXFD_PRE_PKT_START_WR_1_L__BEAM_CHANGE___S 16 +#define PHYA_TXFD_PRE_PKT_START_WR_1_L__CHAIN_MASK___M 0x0000FF00 +#define PHYA_TXFD_PRE_PKT_START_WR_1_L__CHAIN_MASK___S 8 +#define PHYA_TXFD_PRE_PKT_START_WR_1_L__UL_TRIG_STREAM_OFFSET___M 0x0000000F +#define PHYA_TXFD_PRE_PKT_START_WR_1_L__UL_TRIG_STREAM_OFFSET___S 0 +#define PHYA_TXFD_PRE_PKT_START_WR_1_L___M 0xFF01FF0F +#define PHYA_TXFD_PRE_PKT_START_WR_1_L___S 0 + +#define PHYA_TXFD_PRE_PKT_START_WR_1_U (0x0039180C) +#define PHYA_TXFD_PRE_PKT_START_WR_1_U___RWC QCSR_REG_RW +#define PHYA_TXFD_PRE_PKT_START_WR_1_U___POR 0x00000000 +#define PHYA_TXFD_PRE_PKT_START_WR_1_U__HE_LEG_PORTION_CHAIN_CSD_EN___POR 0x0 +#define PHYA_TXFD_PRE_PKT_START_WR_1_U__HE_LEG_PORTION_CHAIN_CSD_EN___M 0x00000001 +#define PHYA_TXFD_PRE_PKT_START_WR_1_U__HE_LEG_PORTION_CHAIN_CSD_EN___S 0 +#define PHYA_TXFD_PRE_PKT_START_WR_1_U___M 0x00000001 +#define PHYA_TXFD_PRE_PKT_START_WR_1_U___S 0 + +#define PHYA_TXFD_PRE_PKT_START_WR_2_L (0x00391810) +#define PHYA_TXFD_PRE_PKT_START_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_PRE_PKT_START_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_PRE_PKT_START_WR_2_L__HE_LEG_PORTION_CHAIN_CSD_DELTA_1___POR 0x00 +#define PHYA_TXFD_PRE_PKT_START_WR_2_L__HE_LEG_PORTION_CHAIN_CSD_DELTA_0___POR 0x00 +#define PHYA_TXFD_PRE_PKT_START_WR_2_L__HE_LEG_PORTION_CHAIN_CSD_DELTA_1___M 0x0000FF00 +#define PHYA_TXFD_PRE_PKT_START_WR_2_L__HE_LEG_PORTION_CHAIN_CSD_DELTA_1___S 8 +#define PHYA_TXFD_PRE_PKT_START_WR_2_L__HE_LEG_PORTION_CHAIN_CSD_DELTA_0___M 0x000000FF +#define PHYA_TXFD_PRE_PKT_START_WR_2_L__HE_LEG_PORTION_CHAIN_CSD_DELTA_0___S 0 +#define PHYA_TXFD_PRE_PKT_START_WR_2_L___M 0x0000FFFF +#define PHYA_TXFD_PRE_PKT_START_WR_2_L___S 0 + +#define PHYA_TXFD_PRE_PKT_START_WR_3_L (0x00391818) +#define PHYA_TXFD_PRE_PKT_START_WR_3_L___RWC QCSR_REG_RW +#define PHYA_TXFD_PRE_PKT_START_WR_3_L___POR 0x00000033 +#define PHYA_TXFD_PRE_PKT_START_WR_3_L__HE_LSTF_POWER_NORM_EN___POR 0x0 +#define PHYA_TXFD_PRE_PKT_START_WR_3_L__LSTF_SUBBAND_PHASE_ROT___POR 0x0033 +#define PHYA_TXFD_PRE_PKT_START_WR_3_L__HE_LSTF_POWER_NORM_EN___M 0x00010000 +#define PHYA_TXFD_PRE_PKT_START_WR_3_L__HE_LSTF_POWER_NORM_EN___S 16 +#define PHYA_TXFD_PRE_PKT_START_WR_3_L__LSTF_SUBBAND_PHASE_ROT___M 0x0000FFFF +#define PHYA_TXFD_PRE_PKT_START_WR_3_L__LSTF_SUBBAND_PHASE_ROT___S 0 +#define PHYA_TXFD_PRE_PKT_START_WR_3_L___M 0x0001FFFF +#define PHYA_TXFD_PRE_PKT_START_WR_3_L___S 0 + +#define PHYA_TXFD_PRE_PKT_START_WR_4_L (0x00391820) +#define PHYA_TXFD_PRE_PKT_START_WR_4_L___RWC QCSR_REG_RW +#define PHYA_TXFD_PRE_PKT_START_WR_4_L___POR 0x00000000 +#define PHYA_TXFD_PRE_PKT_START_WR_4_L__HE_LSTF_POWER_NORM_FACTOR_1___POR 0x0000 +#define PHYA_TXFD_PRE_PKT_START_WR_4_L__HE_LSTF_POWER_NORM_FACTOR_0___POR 0x0000 +#define PHYA_TXFD_PRE_PKT_START_WR_4_L__HE_LSTF_POWER_NORM_FACTOR_1___M 0x3FFF0000 +#define PHYA_TXFD_PRE_PKT_START_WR_4_L__HE_LSTF_POWER_NORM_FACTOR_1___S 16 +#define PHYA_TXFD_PRE_PKT_START_WR_4_L__HE_LSTF_POWER_NORM_FACTOR_0___M 0x00003FFF +#define PHYA_TXFD_PRE_PKT_START_WR_4_L__HE_LSTF_POWER_NORM_FACTOR_0___S 0 +#define PHYA_TXFD_PRE_PKT_START_WR_4_L___M 0x3FFF3FFF +#define PHYA_TXFD_PRE_PKT_START_WR_4_L___S 0 + +#define PHYA_TXFD_PRE_PKT_START_WR_5_L (0x00391830) +#define PHYA_TXFD_PRE_PKT_START_WR_5_L___RWC QCSR_REG_RW +#define PHYA_TXFD_PRE_PKT_START_WR_5_L___POR 0x00000000 +#define PHYA_TXFD_PRE_PKT_START_WR_5_L__NON_HE_LSTF_POWER_NORM_EN___POR 0x0 +#define PHYA_TXFD_PRE_PKT_START_WR_5_L__NON_HE_LSTF_POWER_NORM_EN___M 0x00000001 +#define PHYA_TXFD_PRE_PKT_START_WR_5_L__NON_HE_LSTF_POWER_NORM_EN___S 0 +#define PHYA_TXFD_PRE_PKT_START_WR_5_L___M 0x00000001 +#define PHYA_TXFD_PRE_PKT_START_WR_5_L___S 0 + +#define PHYA_TXFD_PRE_PKT_START_WR_6_L (0x00391838) +#define PHYA_TXFD_PRE_PKT_START_WR_6_L___RWC QCSR_REG_RW +#define PHYA_TXFD_PRE_PKT_START_WR_6_L___POR 0x00000000 +#define PHYA_TXFD_PRE_PKT_START_WR_6_L__NON_HE_LSTF_POWER_NORM_FACTOR_1___POR 0x0000 +#define PHYA_TXFD_PRE_PKT_START_WR_6_L__NON_HE_LSTF_POWER_NORM_FACTOR_0___POR 0x0000 +#define PHYA_TXFD_PRE_PKT_START_WR_6_L__NON_HE_LSTF_POWER_NORM_FACTOR_1___M 0x3FFF0000 +#define PHYA_TXFD_PRE_PKT_START_WR_6_L__NON_HE_LSTF_POWER_NORM_FACTOR_1___S 16 +#define PHYA_TXFD_PRE_PKT_START_WR_6_L__NON_HE_LSTF_POWER_NORM_FACTOR_0___M 0x00003FFF +#define PHYA_TXFD_PRE_PKT_START_WR_6_L__NON_HE_LSTF_POWER_NORM_FACTOR_0___S 0 +#define PHYA_TXFD_PRE_PKT_START_WR_6_L___M 0x3FFF3FFF +#define PHYA_TXFD_PRE_PKT_START_WR_6_L___S 0 + +#define PHYA_TXFD_PRE_PKT_START_WR_7_L (0x00391848) +#define PHYA_TXFD_PRE_PKT_START_WR_7_L___RWC QCSR_REG_RW +#define PHYA_TXFD_PRE_PKT_START_WR_7_L___POR 0x00000000 +#define PHYA_TXFD_PRE_PKT_START_WR_7_L__IMPLICIT_BF___POR 0x0 +#define PHYA_TXFD_PRE_PKT_START_WR_7_L__IMPLICIT_BF___M 0x00000001 +#define PHYA_TXFD_PRE_PKT_START_WR_7_L__IMPLICIT_BF___S 0 +#define PHYA_TXFD_PRE_PKT_START_WR_7_L___M 0x00000001 +#define PHYA_TXFD_PRE_PKT_START_WR_7_L___S 0 + +#define PHYA_TXFD_PRE_PKT_START_WR_SPARE_L (0x00391850) +#define PHYA_TXFD_PRE_PKT_START_WR_SPARE_L___RWC QCSR_REG_RW +#define PHYA_TXFD_PRE_PKT_START_WR_SPARE_L___POR 0x00000000 +#define PHYA_TXFD_PRE_PKT_START_WR_SPARE_L__PRE_PKT_START_WR_SPARE_0___POR 0x00000000 +#define PHYA_TXFD_PRE_PKT_START_WR_SPARE_L__PRE_PKT_START_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXFD_PRE_PKT_START_WR_SPARE_L__PRE_PKT_START_WR_SPARE_0___S 0 +#define PHYA_TXFD_PRE_PKT_START_WR_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXFD_PRE_PKT_START_WR_SPARE_L___S 0 + +#define PHYA_TXFD_PRE_PKT_START_WR_SPARE_U (0x00391854) +#define PHYA_TXFD_PRE_PKT_START_WR_SPARE_U___RWC QCSR_REG_RW +#define PHYA_TXFD_PRE_PKT_START_WR_SPARE_U___POR 0x00000000 +#define PHYA_TXFD_PRE_PKT_START_WR_SPARE_U__PRE_PKT_START_WR_SPARE_1___POR 0x00000000 +#define PHYA_TXFD_PRE_PKT_START_WR_SPARE_U__PRE_PKT_START_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXFD_PRE_PKT_START_WR_SPARE_U__PRE_PKT_START_WR_SPARE_1___S 0 +#define PHYA_TXFD_PRE_PKT_START_WR_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXFD_PRE_PKT_START_WR_SPARE_U___S 0 + +#define PHYA_TXFD_PKT_START_FAST_WR_L (0x00391858) +#define PHYA_TXFD_PKT_START_FAST_WR_L___RWC QCSR_REG_RW +#define PHYA_TXFD_PKT_START_FAST_WR_L___POR 0x00000000 +#define PHYA_TXFD_PKT_START_FAST_WR_L__PKT_START_FAST_RSVD1___POR 0x00000000 +#define PHYA_TXFD_PKT_START_FAST_WR_L__PKT_START_FAST_RSVD1___M 0xFFFFFFFF +#define PHYA_TXFD_PKT_START_FAST_WR_L__PKT_START_FAST_RSVD1___S 0 +#define PHYA_TXFD_PKT_START_FAST_WR_L___M 0xFFFFFFFF +#define PHYA_TXFD_PKT_START_FAST_WR_L___S 0 + +#define PHYA_TXFD_PKT_START_FAST_WR_U (0x0039185C) +#define PHYA_TXFD_PKT_START_FAST_WR_U___RWC QCSR_REG_RW +#define PHYA_TXFD_PKT_START_FAST_WR_U___POR 0x00000000 +#define PHYA_TXFD_PKT_START_FAST_WR_U__PKT_START_FAST_RSVD2___POR 0x00000000 +#define PHYA_TXFD_PKT_START_FAST_WR_U__PKT_START_FAST_RSVD2___M 0xFFFFFFFF +#define PHYA_TXFD_PKT_START_FAST_WR_U__PKT_START_FAST_RSVD2___S 0 +#define PHYA_TXFD_PKT_START_FAST_WR_U___M 0xFFFFFFFF +#define PHYA_TXFD_PKT_START_FAST_WR_U___S 0 + +#define PHYA_TXFD_PKT_START_FAST_WR_SPARE_L (0x00391860) +#define PHYA_TXFD_PKT_START_FAST_WR_SPARE_L___RWC QCSR_REG_RW +#define PHYA_TXFD_PKT_START_FAST_WR_SPARE_L___POR 0x00000000 +#define PHYA_TXFD_PKT_START_FAST_WR_SPARE_L__PKT_START_FAST_WR_SPARE_0___POR 0x00000000 +#define PHYA_TXFD_PKT_START_FAST_WR_SPARE_L__PKT_START_FAST_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXFD_PKT_START_FAST_WR_SPARE_L__PKT_START_FAST_WR_SPARE_0___S 0 +#define PHYA_TXFD_PKT_START_FAST_WR_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXFD_PKT_START_FAST_WR_SPARE_L___S 0 + +#define PHYA_TXFD_PKT_START_FAST_WR_SPARE_U (0x00391864) +#define PHYA_TXFD_PKT_START_FAST_WR_SPARE_U___RWC QCSR_REG_RW +#define PHYA_TXFD_PKT_START_FAST_WR_SPARE_U___POR 0x00000000 +#define PHYA_TXFD_PKT_START_FAST_WR_SPARE_U__PKT_START_FAST_WR_SPARE_1___POR 0x00000000 +#define PHYA_TXFD_PKT_START_FAST_WR_SPARE_U__PKT_START_FAST_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXFD_PKT_START_FAST_WR_SPARE_U__PKT_START_FAST_WR_SPARE_1___S 0 +#define PHYA_TXFD_PKT_START_FAST_WR_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXFD_PKT_START_FAST_WR_SPARE_U___S 0 + +#define PHYA_TXFD_PKT_START_FAST_RD_L (0x00391868) +#define PHYA_TXFD_PKT_START_FAST_RD_L___RWC QCSR_REG_RO +#define PHYA_TXFD_PKT_START_FAST_RD_L___POR 0x00000000 +#define PHYA_TXFD_PKT_START_FAST_RD_L__HEAVYCLIP_EN_DECODED___POR 0x0 +#define PHYA_TXFD_PKT_START_FAST_RD_L__HEAVYCLIP_EN_DECODED___M 0x00000001 +#define PHYA_TXFD_PKT_START_FAST_RD_L__HEAVYCLIP_EN_DECODED___S 0 +#define PHYA_TXFD_PKT_START_FAST_RD_L___M 0x00000001 +#define PHYA_TXFD_PKT_START_FAST_RD_L___S 0 + +#define PHYA_TXFD_PKT_START_FAST_RD_SPARE_L (0x00391870) +#define PHYA_TXFD_PKT_START_FAST_RD_SPARE_L___RWC QCSR_REG_RW +#define PHYA_TXFD_PKT_START_FAST_RD_SPARE_L___POR 0x00000000 +#define PHYA_TXFD_PKT_START_FAST_RD_SPARE_L__PKT_START_FAST_RD_SPARE_0___POR 0x00000000 +#define PHYA_TXFD_PKT_START_FAST_RD_SPARE_L__PKT_START_FAST_RD_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXFD_PKT_START_FAST_RD_SPARE_L__PKT_START_FAST_RD_SPARE_0___S 0 +#define PHYA_TXFD_PKT_START_FAST_RD_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXFD_PKT_START_FAST_RD_SPARE_L___S 0 + +#define PHYA_TXFD_PKT_START_FAST_RD_SPARE_U (0x00391874) +#define PHYA_TXFD_PKT_START_FAST_RD_SPARE_U___RWC QCSR_REG_RW +#define PHYA_TXFD_PKT_START_FAST_RD_SPARE_U___POR 0x00000000 +#define PHYA_TXFD_PKT_START_FAST_RD_SPARE_U__PKT_START_FAST_RD_SPARE_1___POR 0x00000000 +#define PHYA_TXFD_PKT_START_FAST_RD_SPARE_U__PKT_START_FAST_RD_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXFD_PKT_START_FAST_RD_SPARE_U__PKT_START_FAST_RD_SPARE_1___S 0 +#define PHYA_TXFD_PKT_START_FAST_RD_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXFD_PKT_START_FAST_RD_SPARE_U___S 0 + +#define PHYA_TXFD_PKT_START_SLOW_WR_0_L (0x00391878) +#define PHYA_TXFD_PKT_START_SLOW_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_PKT_START_SLOW_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_PKT_START_SLOW_WR_0_L__EN_HE_LSIG_EXTRA_TONE_SCALE___POR 0x0 +#define PHYA_TXFD_PKT_START_SLOW_WR_0_L__QAM1024_ORDER___POR 0x0 +#define PHYA_TXFD_PKT_START_SLOW_WR_0_L__QAM1024_INV___POR 0x0 +#define PHYA_TXFD_PKT_START_SLOW_WR_0_L__EN_HE_LSIG_EXTRA_TONE_SCALE___M 0x00010000 +#define PHYA_TXFD_PKT_START_SLOW_WR_0_L__EN_HE_LSIG_EXTRA_TONE_SCALE___S 16 +#define PHYA_TXFD_PKT_START_SLOW_WR_0_L__QAM1024_ORDER___M 0x00000100 +#define PHYA_TXFD_PKT_START_SLOW_WR_0_L__QAM1024_ORDER___S 8 +#define PHYA_TXFD_PKT_START_SLOW_WR_0_L__QAM1024_INV___M 0x00000001 +#define PHYA_TXFD_PKT_START_SLOW_WR_0_L__QAM1024_INV___S 0 +#define PHYA_TXFD_PKT_START_SLOW_WR_0_L___M 0x00010101 +#define PHYA_TXFD_PKT_START_SLOW_WR_0_L___S 0 + +#define PHYA_TXFD_PKT_START_SLOW_WR_0_U (0x0039187C) +#define PHYA_TXFD_PKT_START_SLOW_WR_0_U___RWC QCSR_REG_RW +#define PHYA_TXFD_PKT_START_SLOW_WR_0_U___POR 0x00000000 +#define PHYA_TXFD_PKT_START_SLOW_WR_0_U__HE_LSIG_EXTRA_TONE_SCALE___POR 0x0000 +#define PHYA_TXFD_PKT_START_SLOW_WR_0_U__HE_LSIG_NORMAL_TONE_SCALE___POR 0x0000 +#define PHYA_TXFD_PKT_START_SLOW_WR_0_U__HE_LSIG_EXTRA_TONE_SCALE___M 0xFFFF0000 +#define PHYA_TXFD_PKT_START_SLOW_WR_0_U__HE_LSIG_EXTRA_TONE_SCALE___S 16 +#define PHYA_TXFD_PKT_START_SLOW_WR_0_U__HE_LSIG_NORMAL_TONE_SCALE___M 0x0000FFFF +#define PHYA_TXFD_PKT_START_SLOW_WR_0_U__HE_LSIG_NORMAL_TONE_SCALE___S 0 +#define PHYA_TXFD_PKT_START_SLOW_WR_0_U___M 0xFFFFFFFF +#define PHYA_TXFD_PKT_START_SLOW_WR_0_U___S 0 + +#define PHYA_TXFD_PKT_START_SLOW_WR_1_L (0x00391880) +#define PHYA_TXFD_PKT_START_SLOW_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_PKT_START_SLOW_WR_1_L___POR 0x00010000 +#define PHYA_TXFD_PKT_START_SLOW_WR_1_L__FULL_BW___POR 0x0 +#define PHYA_TXFD_PKT_START_SLOW_WR_1_L__HE_LTF_PRIMARY_USES_LOWER___POR 0x1 +#define PHYA_TXFD_PKT_START_SLOW_WR_1_L__HE_PILOT_TYPE_11AC___POR 0x0 +#define PHYA_TXFD_PKT_START_SLOW_WR_1_L__EN_HE_LSIG_NORMAL_TONE_SCALE___POR 0x0 +#define PHYA_TXFD_PKT_START_SLOW_WR_1_L__FULL_BW___M 0x01000000 +#define PHYA_TXFD_PKT_START_SLOW_WR_1_L__FULL_BW___S 24 +#define PHYA_TXFD_PKT_START_SLOW_WR_1_L__HE_LTF_PRIMARY_USES_LOWER___M 0x00010000 +#define PHYA_TXFD_PKT_START_SLOW_WR_1_L__HE_LTF_PRIMARY_USES_LOWER___S 16 +#define PHYA_TXFD_PKT_START_SLOW_WR_1_L__HE_PILOT_TYPE_11AC___M 0x00000100 +#define PHYA_TXFD_PKT_START_SLOW_WR_1_L__HE_PILOT_TYPE_11AC___S 8 +#define PHYA_TXFD_PKT_START_SLOW_WR_1_L__EN_HE_LSIG_NORMAL_TONE_SCALE___M 0x00000001 +#define PHYA_TXFD_PKT_START_SLOW_WR_1_L__EN_HE_LSIG_NORMAL_TONE_SCALE___S 0 +#define PHYA_TXFD_PKT_START_SLOW_WR_1_L___M 0x01010101 +#define PHYA_TXFD_PKT_START_SLOW_WR_1_L___S 0 + +#define PHYA_TXFD_PKT_START_SLOW_WR_1_U (0x00391884) +#define PHYA_TXFD_PKT_START_SLOW_WR_1_U___RWC QCSR_REG_RW +#define PHYA_TXFD_PKT_START_SLOW_WR_1_U___POR 0x00000000 +#define PHYA_TXFD_PKT_START_SLOW_WR_1_U__QAM4096_ORDER___POR 0x0 +#define PHYA_TXFD_PKT_START_SLOW_WR_1_U__QAM4096_INV___POR 0x0 +#define PHYA_TXFD_PKT_START_SLOW_WR_1_U__QAM4096_ORDER___M 0x00000100 +#define PHYA_TXFD_PKT_START_SLOW_WR_1_U__QAM4096_ORDER___S 8 +#define PHYA_TXFD_PKT_START_SLOW_WR_1_U__QAM4096_INV___M 0x00000001 +#define PHYA_TXFD_PKT_START_SLOW_WR_1_U__QAM4096_INV___S 0 +#define PHYA_TXFD_PKT_START_SLOW_WR_1_U___M 0x00000101 +#define PHYA_TXFD_PKT_START_SLOW_WR_1_U___S 0 + +#define PHYA_TXFD_SYM_SEQ_TBL0_L (0x00391888) +#define PHYA_TXFD_SYM_SEQ_TBL0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_SYM_SEQ_TBL0_L___POR 0x00040302 +#define PHYA_TXFD_SYM_SEQ_TBL0_L__SYM_SEQ_TBL_3_0___POR 0x00 +#define PHYA_TXFD_SYM_SEQ_TBL0_L__SYM_SEQ_TBL_2_0___POR 0x04 +#define PHYA_TXFD_SYM_SEQ_TBL0_L__SYM_SEQ_TBL_1_0___POR 0x03 +#define PHYA_TXFD_SYM_SEQ_TBL0_L__SYM_SEQ_TBL_0_0___POR 0x02 +#define PHYA_TXFD_SYM_SEQ_TBL0_L__SYM_SEQ_TBL_3_0___M 0x1F000000 +#define PHYA_TXFD_SYM_SEQ_TBL0_L__SYM_SEQ_TBL_3_0___S 24 +#define PHYA_TXFD_SYM_SEQ_TBL0_L__SYM_SEQ_TBL_2_0___M 0x001F0000 +#define PHYA_TXFD_SYM_SEQ_TBL0_L__SYM_SEQ_TBL_2_0___S 16 +#define PHYA_TXFD_SYM_SEQ_TBL0_L__SYM_SEQ_TBL_1_0___M 0x00001F00 +#define PHYA_TXFD_SYM_SEQ_TBL0_L__SYM_SEQ_TBL_1_0___S 8 +#define PHYA_TXFD_SYM_SEQ_TBL0_L__SYM_SEQ_TBL_0_0___M 0x0000001F +#define PHYA_TXFD_SYM_SEQ_TBL0_L__SYM_SEQ_TBL_0_0___S 0 +#define PHYA_TXFD_SYM_SEQ_TBL0_L___M 0x1F1F1F1F +#define PHYA_TXFD_SYM_SEQ_TBL0_L___S 0 + +#define PHYA_TXFD_SYM_SEQ_TBL0_U (0x0039188C) +#define PHYA_TXFD_SYM_SEQ_TBL0_U___RWC QCSR_REG_RW +#define PHYA_TXFD_SYM_SEQ_TBL0_U___POR 0x00000000 +#define PHYA_TXFD_SYM_SEQ_TBL0_U__SYM_SEQ_TBL_7_0___POR 0x00 +#define PHYA_TXFD_SYM_SEQ_TBL0_U__SYM_SEQ_TBL_6_0___POR 0x00 +#define PHYA_TXFD_SYM_SEQ_TBL0_U__SYM_SEQ_TBL_5_0___POR 0x00 +#define PHYA_TXFD_SYM_SEQ_TBL0_U__SYM_SEQ_TBL_4_0___POR 0x00 +#define PHYA_TXFD_SYM_SEQ_TBL0_U__SYM_SEQ_TBL_7_0___M 0x1F000000 +#define PHYA_TXFD_SYM_SEQ_TBL0_U__SYM_SEQ_TBL_7_0___S 24 +#define PHYA_TXFD_SYM_SEQ_TBL0_U__SYM_SEQ_TBL_6_0___M 0x001F0000 +#define PHYA_TXFD_SYM_SEQ_TBL0_U__SYM_SEQ_TBL_6_0___S 16 +#define PHYA_TXFD_SYM_SEQ_TBL0_U__SYM_SEQ_TBL_5_0___M 0x00001F00 +#define PHYA_TXFD_SYM_SEQ_TBL0_U__SYM_SEQ_TBL_5_0___S 8 +#define PHYA_TXFD_SYM_SEQ_TBL0_U__SYM_SEQ_TBL_4_0___M 0x0000001F +#define PHYA_TXFD_SYM_SEQ_TBL0_U__SYM_SEQ_TBL_4_0___S 0 +#define PHYA_TXFD_SYM_SEQ_TBL0_U___M 0x1F1F1F1F +#define PHYA_TXFD_SYM_SEQ_TBL0_U___S 0 + +#define PHYA_TXFD_SYM_SEQ_TBL1_L (0x00391890) +#define PHYA_TXFD_SYM_SEQ_TBL1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_SYM_SEQ_TBL1_L___POR 0x00000000 +#define PHYA_TXFD_SYM_SEQ_TBL1_L__SYM_SEQ_TBL_3_1___POR 0x00 +#define PHYA_TXFD_SYM_SEQ_TBL1_L__SYM_SEQ_TBL_2_1___POR 0x00 +#define PHYA_TXFD_SYM_SEQ_TBL1_L__SYM_SEQ_TBL_1_1___POR 0x00 +#define PHYA_TXFD_SYM_SEQ_TBL1_L__SYM_SEQ_TBL_0_1___POR 0x00 +#define PHYA_TXFD_SYM_SEQ_TBL1_L__SYM_SEQ_TBL_3_1___M 0x1F000000 +#define PHYA_TXFD_SYM_SEQ_TBL1_L__SYM_SEQ_TBL_3_1___S 24 +#define PHYA_TXFD_SYM_SEQ_TBL1_L__SYM_SEQ_TBL_2_1___M 0x001F0000 +#define PHYA_TXFD_SYM_SEQ_TBL1_L__SYM_SEQ_TBL_2_1___S 16 +#define PHYA_TXFD_SYM_SEQ_TBL1_L__SYM_SEQ_TBL_1_1___M 0x00001F00 +#define PHYA_TXFD_SYM_SEQ_TBL1_L__SYM_SEQ_TBL_1_1___S 8 +#define PHYA_TXFD_SYM_SEQ_TBL1_L__SYM_SEQ_TBL_0_1___M 0x0000001F +#define PHYA_TXFD_SYM_SEQ_TBL1_L__SYM_SEQ_TBL_0_1___S 0 +#define PHYA_TXFD_SYM_SEQ_TBL1_L___M 0x1F1F1F1F +#define PHYA_TXFD_SYM_SEQ_TBL1_L___S 0 + +#define PHYA_TXFD_SYM_SEQ_TBL1_U (0x00391894) +#define PHYA_TXFD_SYM_SEQ_TBL1_U___RWC QCSR_REG_RW +#define PHYA_TXFD_SYM_SEQ_TBL1_U___POR 0x00000000 +#define PHYA_TXFD_SYM_SEQ_TBL1_U__SYM_SEQ_TBL_7_1___POR 0x00 +#define PHYA_TXFD_SYM_SEQ_TBL1_U__SYM_SEQ_TBL_6_1___POR 0x00 +#define PHYA_TXFD_SYM_SEQ_TBL1_U__SYM_SEQ_TBL_5_1___POR 0x00 +#define PHYA_TXFD_SYM_SEQ_TBL1_U__SYM_SEQ_TBL_4_1___POR 0x00 +#define PHYA_TXFD_SYM_SEQ_TBL1_U__SYM_SEQ_TBL_7_1___M 0x1F000000 +#define PHYA_TXFD_SYM_SEQ_TBL1_U__SYM_SEQ_TBL_7_1___S 24 +#define PHYA_TXFD_SYM_SEQ_TBL1_U__SYM_SEQ_TBL_6_1___M 0x001F0000 +#define PHYA_TXFD_SYM_SEQ_TBL1_U__SYM_SEQ_TBL_6_1___S 16 +#define PHYA_TXFD_SYM_SEQ_TBL1_U__SYM_SEQ_TBL_5_1___M 0x00001F00 +#define PHYA_TXFD_SYM_SEQ_TBL1_U__SYM_SEQ_TBL_5_1___S 8 +#define PHYA_TXFD_SYM_SEQ_TBL1_U__SYM_SEQ_TBL_4_1___M 0x0000001F +#define PHYA_TXFD_SYM_SEQ_TBL1_U__SYM_SEQ_TBL_4_1___S 0 +#define PHYA_TXFD_SYM_SEQ_TBL1_U___M 0x1F1F1F1F +#define PHYA_TXFD_SYM_SEQ_TBL1_U___S 0 + +#define PHYA_TXFD_REQ_TBL0_L (0x00391898) +#define PHYA_TXFD_REQ_TBL0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_REQ_TBL0_L___POR 0x00000020 +#define PHYA_TXFD_REQ_TBL0_L__REQ_TBL_SYM_TYPE_0___POR 0x20 +#define PHYA_TXFD_REQ_TBL0_L__REQ_TBL_SYM_TYPE_0___M 0x0000003F +#define PHYA_TXFD_REQ_TBL0_L__REQ_TBL_SYM_TYPE_0___S 0 +#define PHYA_TXFD_REQ_TBL0_L___M 0x0000003F +#define PHYA_TXFD_REQ_TBL0_L___S 0 + +#define PHYA_TXFD_REQ_TBL0_U (0x0039189C) +#define PHYA_TXFD_REQ_TBL0_U___RWC QCSR_REG_RW +#define PHYA_TXFD_REQ_TBL0_U___POR 0x000003E8 +#define PHYA_TXFD_REQ_TBL0_U__REQ_TBL_REQ_TIME_0___POR 0x000003E8 +#define PHYA_TXFD_REQ_TBL0_U__REQ_TBL_REQ_TIME_0___M 0xFFFFFFFF +#define PHYA_TXFD_REQ_TBL0_U__REQ_TBL_REQ_TIME_0___S 0 +#define PHYA_TXFD_REQ_TBL0_U___M 0xFFFFFFFF +#define PHYA_TXFD_REQ_TBL0_U___S 0 + +#define PHYA_TXFD_REQ_TBL1_L (0x003918A0) +#define PHYA_TXFD_REQ_TBL1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_REQ_TBL1_L___POR 0x00000000 +#define PHYA_TXFD_REQ_TBL1_L__REQ_TBL_SYM_TYPE_1___POR 0x00 +#define PHYA_TXFD_REQ_TBL1_L__REQ_TBL_SYM_TYPE_1___M 0x0000003F +#define PHYA_TXFD_REQ_TBL1_L__REQ_TBL_SYM_TYPE_1___S 0 +#define PHYA_TXFD_REQ_TBL1_L___M 0x0000003F +#define PHYA_TXFD_REQ_TBL1_L___S 0 + +#define PHYA_TXFD_REQ_TBL1_U (0x003918A4) +#define PHYA_TXFD_REQ_TBL1_U___RWC QCSR_REG_RW +#define PHYA_TXFD_REQ_TBL1_U___POR 0x00000000 +#define PHYA_TXFD_REQ_TBL1_U__REQ_TBL_REQ_TIME_1___POR 0x00000000 +#define PHYA_TXFD_REQ_TBL1_U__REQ_TBL_REQ_TIME_1___M 0xFFFFFFFF +#define PHYA_TXFD_REQ_TBL1_U__REQ_TBL_REQ_TIME_1___S 0 +#define PHYA_TXFD_REQ_TBL1_U___M 0xFFFFFFFF +#define PHYA_TXFD_REQ_TBL1_U___S 0 + +#define PHYA_TXFD_REQ_TBL2_L (0x003918A8) +#define PHYA_TXFD_REQ_TBL2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_REQ_TBL2_L___POR 0x00000000 +#define PHYA_TXFD_REQ_TBL2_L__REQ_TBL_SYM_TYPE_2___POR 0x00 +#define PHYA_TXFD_REQ_TBL2_L__REQ_TBL_SYM_TYPE_2___M 0x0000003F +#define PHYA_TXFD_REQ_TBL2_L__REQ_TBL_SYM_TYPE_2___S 0 +#define PHYA_TXFD_REQ_TBL2_L___M 0x0000003F +#define PHYA_TXFD_REQ_TBL2_L___S 0 + +#define PHYA_TXFD_REQ_TBL2_U (0x003918AC) +#define PHYA_TXFD_REQ_TBL2_U___RWC QCSR_REG_RW +#define PHYA_TXFD_REQ_TBL2_U___POR 0x00000000 +#define PHYA_TXFD_REQ_TBL2_U__REQ_TBL_REQ_TIME_2___POR 0x00000000 +#define PHYA_TXFD_REQ_TBL2_U__REQ_TBL_REQ_TIME_2___M 0xFFFFFFFF +#define PHYA_TXFD_REQ_TBL2_U__REQ_TBL_REQ_TIME_2___S 0 +#define PHYA_TXFD_REQ_TBL2_U___M 0xFFFFFFFF +#define PHYA_TXFD_REQ_TBL2_U___S 0 + +#define PHYA_TXFD_REQ_TBL3_L (0x003918B0) +#define PHYA_TXFD_REQ_TBL3_L___RWC QCSR_REG_RW +#define PHYA_TXFD_REQ_TBL3_L___POR 0x00000000 +#define PHYA_TXFD_REQ_TBL3_L__REQ_TBL_SYM_TYPE_3___POR 0x00 +#define PHYA_TXFD_REQ_TBL3_L__REQ_TBL_SYM_TYPE_3___M 0x0000003F +#define PHYA_TXFD_REQ_TBL3_L__REQ_TBL_SYM_TYPE_3___S 0 +#define PHYA_TXFD_REQ_TBL3_L___M 0x0000003F +#define PHYA_TXFD_REQ_TBL3_L___S 0 + +#define PHYA_TXFD_REQ_TBL3_U (0x003918B4) +#define PHYA_TXFD_REQ_TBL3_U___RWC QCSR_REG_RW +#define PHYA_TXFD_REQ_TBL3_U___POR 0x00000000 +#define PHYA_TXFD_REQ_TBL3_U__REQ_TBL_REQ_TIME_3___POR 0x00000000 +#define PHYA_TXFD_REQ_TBL3_U__REQ_TBL_REQ_TIME_3___M 0xFFFFFFFF +#define PHYA_TXFD_REQ_TBL3_U__REQ_TBL_REQ_TIME_3___S 0 +#define PHYA_TXFD_REQ_TBL3_U___M 0xFFFFFFFF +#define PHYA_TXFD_REQ_TBL3_U___S 0 + +#define PHYA_TXFD_REQ_TBL4_L (0x003918B8) +#define PHYA_TXFD_REQ_TBL4_L___RWC QCSR_REG_RW +#define PHYA_TXFD_REQ_TBL4_L___POR 0x00000000 +#define PHYA_TXFD_REQ_TBL4_L__REQ_TBL_SYM_TYPE_4___POR 0x00 +#define PHYA_TXFD_REQ_TBL4_L__REQ_TBL_SYM_TYPE_4___M 0x0000003F +#define PHYA_TXFD_REQ_TBL4_L__REQ_TBL_SYM_TYPE_4___S 0 +#define PHYA_TXFD_REQ_TBL4_L___M 0x0000003F +#define PHYA_TXFD_REQ_TBL4_L___S 0 + +#define PHYA_TXFD_REQ_TBL4_U (0x003918BC) +#define PHYA_TXFD_REQ_TBL4_U___RWC QCSR_REG_RW +#define PHYA_TXFD_REQ_TBL4_U___POR 0x00000000 +#define PHYA_TXFD_REQ_TBL4_U__REQ_TBL_REQ_TIME_4___POR 0x00000000 +#define PHYA_TXFD_REQ_TBL4_U__REQ_TBL_REQ_TIME_4___M 0xFFFFFFFF +#define PHYA_TXFD_REQ_TBL4_U__REQ_TBL_REQ_TIME_4___S 0 +#define PHYA_TXFD_REQ_TBL4_U___M 0xFFFFFFFF +#define PHYA_TXFD_REQ_TBL4_U___S 0 + +#define PHYA_TXFD_REQ_TBL5_L (0x003918C0) +#define PHYA_TXFD_REQ_TBL5_L___RWC QCSR_REG_RW +#define PHYA_TXFD_REQ_TBL5_L___POR 0x00000000 +#define PHYA_TXFD_REQ_TBL5_L__REQ_TBL_SYM_TYPE_5___POR 0x00 +#define PHYA_TXFD_REQ_TBL5_L__REQ_TBL_SYM_TYPE_5___M 0x0000003F +#define PHYA_TXFD_REQ_TBL5_L__REQ_TBL_SYM_TYPE_5___S 0 +#define PHYA_TXFD_REQ_TBL5_L___M 0x0000003F +#define PHYA_TXFD_REQ_TBL5_L___S 0 + +#define PHYA_TXFD_REQ_TBL5_U (0x003918C4) +#define PHYA_TXFD_REQ_TBL5_U___RWC QCSR_REG_RW +#define PHYA_TXFD_REQ_TBL5_U___POR 0x00000000 +#define PHYA_TXFD_REQ_TBL5_U__REQ_TBL_REQ_TIME_5___POR 0x00000000 +#define PHYA_TXFD_REQ_TBL5_U__REQ_TBL_REQ_TIME_5___M 0xFFFFFFFF +#define PHYA_TXFD_REQ_TBL5_U__REQ_TBL_REQ_TIME_5___S 0 +#define PHYA_TXFD_REQ_TBL5_U___M 0xFFFFFFFF +#define PHYA_TXFD_REQ_TBL5_U___S 0 + +#define PHYA_TXFD_REQ_TBL6_L (0x003918C8) +#define PHYA_TXFD_REQ_TBL6_L___RWC QCSR_REG_RW +#define PHYA_TXFD_REQ_TBL6_L___POR 0x00000000 +#define PHYA_TXFD_REQ_TBL6_L__REQ_TBL_SYM_TYPE_6___POR 0x00 +#define PHYA_TXFD_REQ_TBL6_L__REQ_TBL_SYM_TYPE_6___M 0x0000003F +#define PHYA_TXFD_REQ_TBL6_L__REQ_TBL_SYM_TYPE_6___S 0 +#define PHYA_TXFD_REQ_TBL6_L___M 0x0000003F +#define PHYA_TXFD_REQ_TBL6_L___S 0 + +#define PHYA_TXFD_REQ_TBL6_U (0x003918CC) +#define PHYA_TXFD_REQ_TBL6_U___RWC QCSR_REG_RW +#define PHYA_TXFD_REQ_TBL6_U___POR 0x00000000 +#define PHYA_TXFD_REQ_TBL6_U__REQ_TBL_REQ_TIME_6___POR 0x00000000 +#define PHYA_TXFD_REQ_TBL6_U__REQ_TBL_REQ_TIME_6___M 0xFFFFFFFF +#define PHYA_TXFD_REQ_TBL6_U__REQ_TBL_REQ_TIME_6___S 0 +#define PHYA_TXFD_REQ_TBL6_U___M 0xFFFFFFFF +#define PHYA_TXFD_REQ_TBL6_U___S 0 + +#define PHYA_TXFD_REQ_TBL7_L (0x003918D0) +#define PHYA_TXFD_REQ_TBL7_L___RWC QCSR_REG_RW +#define PHYA_TXFD_REQ_TBL7_L___POR 0x00000000 +#define PHYA_TXFD_REQ_TBL7_L__REQ_TBL_SYM_TYPE_7___POR 0x00 +#define PHYA_TXFD_REQ_TBL7_L__REQ_TBL_SYM_TYPE_7___M 0x0000003F +#define PHYA_TXFD_REQ_TBL7_L__REQ_TBL_SYM_TYPE_7___S 0 +#define PHYA_TXFD_REQ_TBL7_L___M 0x0000003F +#define PHYA_TXFD_REQ_TBL7_L___S 0 + +#define PHYA_TXFD_REQ_TBL7_U (0x003918D4) +#define PHYA_TXFD_REQ_TBL7_U___RWC QCSR_REG_RW +#define PHYA_TXFD_REQ_TBL7_U___POR 0x00000000 +#define PHYA_TXFD_REQ_TBL7_U__REQ_TBL_REQ_TIME_7___POR 0x00000000 +#define PHYA_TXFD_REQ_TBL7_U__REQ_TBL_REQ_TIME_7___M 0xFFFFFFFF +#define PHYA_TXFD_REQ_TBL7_U__REQ_TBL_REQ_TIME_7___S 0 +#define PHYA_TXFD_REQ_TBL7_U___M 0xFFFFFFFF +#define PHYA_TXFD_REQ_TBL7_U___S 0 + +#define PHYA_TXFD_REQ_TBL8_L (0x003918D8) +#define PHYA_TXFD_REQ_TBL8_L___RWC QCSR_REG_RW +#define PHYA_TXFD_REQ_TBL8_L___POR 0x00000000 +#define PHYA_TXFD_REQ_TBL8_L__REQ_TBL_SYM_TYPE_8___POR 0x00 +#define PHYA_TXFD_REQ_TBL8_L__REQ_TBL_SYM_TYPE_8___M 0x0000003F +#define PHYA_TXFD_REQ_TBL8_L__REQ_TBL_SYM_TYPE_8___S 0 +#define PHYA_TXFD_REQ_TBL8_L___M 0x0000003F +#define PHYA_TXFD_REQ_TBL8_L___S 0 + +#define PHYA_TXFD_REQ_TBL8_U (0x003918DC) +#define PHYA_TXFD_REQ_TBL8_U___RWC QCSR_REG_RW +#define PHYA_TXFD_REQ_TBL8_U___POR 0x00000000 +#define PHYA_TXFD_REQ_TBL8_U__REQ_TBL_REQ_TIME_8___POR 0x00000000 +#define PHYA_TXFD_REQ_TBL8_U__REQ_TBL_REQ_TIME_8___M 0xFFFFFFFF +#define PHYA_TXFD_REQ_TBL8_U__REQ_TBL_REQ_TIME_8___S 0 +#define PHYA_TXFD_REQ_TBL8_U___M 0xFFFFFFFF +#define PHYA_TXFD_REQ_TBL8_U___S 0 + +#define PHYA_TXFD_REQ_TBL9_L (0x003918E0) +#define PHYA_TXFD_REQ_TBL9_L___RWC QCSR_REG_RW +#define PHYA_TXFD_REQ_TBL9_L___POR 0x00000000 +#define PHYA_TXFD_REQ_TBL9_L__REQ_TBL_SYM_TYPE_9___POR 0x00 +#define PHYA_TXFD_REQ_TBL9_L__REQ_TBL_SYM_TYPE_9___M 0x0000003F +#define PHYA_TXFD_REQ_TBL9_L__REQ_TBL_SYM_TYPE_9___S 0 +#define PHYA_TXFD_REQ_TBL9_L___M 0x0000003F +#define PHYA_TXFD_REQ_TBL9_L___S 0 + +#define PHYA_TXFD_REQ_TBL9_U (0x003918E4) +#define PHYA_TXFD_REQ_TBL9_U___RWC QCSR_REG_RW +#define PHYA_TXFD_REQ_TBL9_U___POR 0x00000000 +#define PHYA_TXFD_REQ_TBL9_U__REQ_TBL_REQ_TIME_9___POR 0x00000000 +#define PHYA_TXFD_REQ_TBL9_U__REQ_TBL_REQ_TIME_9___M 0xFFFFFFFF +#define PHYA_TXFD_REQ_TBL9_U__REQ_TBL_REQ_TIME_9___S 0 +#define PHYA_TXFD_REQ_TBL9_U___M 0xFFFFFFFF +#define PHYA_TXFD_REQ_TBL9_U___S 0 + +#define PHYA_TXFD_REQ_TBL10_L (0x003918E8) +#define PHYA_TXFD_REQ_TBL10_L___RWC QCSR_REG_RW +#define PHYA_TXFD_REQ_TBL10_L___POR 0x00000000 +#define PHYA_TXFD_REQ_TBL10_L__REQ_TBL_SYM_TYPE_10___POR 0x00 +#define PHYA_TXFD_REQ_TBL10_L__REQ_TBL_SYM_TYPE_10___M 0x0000003F +#define PHYA_TXFD_REQ_TBL10_L__REQ_TBL_SYM_TYPE_10___S 0 +#define PHYA_TXFD_REQ_TBL10_L___M 0x0000003F +#define PHYA_TXFD_REQ_TBL10_L___S 0 + +#define PHYA_TXFD_REQ_TBL10_U (0x003918EC) +#define PHYA_TXFD_REQ_TBL10_U___RWC QCSR_REG_RW +#define PHYA_TXFD_REQ_TBL10_U___POR 0x00000000 +#define PHYA_TXFD_REQ_TBL10_U__REQ_TBL_REQ_TIME_10___POR 0x00000000 +#define PHYA_TXFD_REQ_TBL10_U__REQ_TBL_REQ_TIME_10___M 0xFFFFFFFF +#define PHYA_TXFD_REQ_TBL10_U__REQ_TBL_REQ_TIME_10___S 0 +#define PHYA_TXFD_REQ_TBL10_U___M 0xFFFFFFFF +#define PHYA_TXFD_REQ_TBL10_U___S 0 + +#define PHYA_TXFD_REQ_TBL11_L (0x003918F0) +#define PHYA_TXFD_REQ_TBL11_L___RWC QCSR_REG_RW +#define PHYA_TXFD_REQ_TBL11_L___POR 0x00000000 +#define PHYA_TXFD_REQ_TBL11_L__REQ_TBL_SYM_TYPE_11___POR 0x00 +#define PHYA_TXFD_REQ_TBL11_L__REQ_TBL_SYM_TYPE_11___M 0x0000003F +#define PHYA_TXFD_REQ_TBL11_L__REQ_TBL_SYM_TYPE_11___S 0 +#define PHYA_TXFD_REQ_TBL11_L___M 0x0000003F +#define PHYA_TXFD_REQ_TBL11_L___S 0 + +#define PHYA_TXFD_REQ_TBL11_U (0x003918F4) +#define PHYA_TXFD_REQ_TBL11_U___RWC QCSR_REG_RW +#define PHYA_TXFD_REQ_TBL11_U___POR 0x00000000 +#define PHYA_TXFD_REQ_TBL11_U__REQ_TBL_REQ_TIME_11___POR 0x00000000 +#define PHYA_TXFD_REQ_TBL11_U__REQ_TBL_REQ_TIME_11___M 0xFFFFFFFF +#define PHYA_TXFD_REQ_TBL11_U__REQ_TBL_REQ_TIME_11___S 0 +#define PHYA_TXFD_REQ_TBL11_U___M 0xFFFFFFFF +#define PHYA_TXFD_REQ_TBL11_U___S 0 + +#define PHYA_TXFD_PKT_START_SLOW_WR_SPARE_L (0x003918F8) +#define PHYA_TXFD_PKT_START_SLOW_WR_SPARE_L___RWC QCSR_REG_RW +#define PHYA_TXFD_PKT_START_SLOW_WR_SPARE_L___POR 0x00000000 +#define PHYA_TXFD_PKT_START_SLOW_WR_SPARE_L__PKT_START_SLOW_WR_SPARE_0___POR 0x00000000 +#define PHYA_TXFD_PKT_START_SLOW_WR_SPARE_L__PKT_START_SLOW_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXFD_PKT_START_SLOW_WR_SPARE_L__PKT_START_SLOW_WR_SPARE_0___S 0 +#define PHYA_TXFD_PKT_START_SLOW_WR_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXFD_PKT_START_SLOW_WR_SPARE_L___S 0 + +#define PHYA_TXFD_PKT_START_SLOW_WR_SPARE_U (0x003918FC) +#define PHYA_TXFD_PKT_START_SLOW_WR_SPARE_U___RWC QCSR_REG_RW +#define PHYA_TXFD_PKT_START_SLOW_WR_SPARE_U___POR 0x00000000 +#define PHYA_TXFD_PKT_START_SLOW_WR_SPARE_U__PKT_START_SLOW_WR_SPARE_1___POR 0x00000000 +#define PHYA_TXFD_PKT_START_SLOW_WR_SPARE_U__PKT_START_SLOW_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXFD_PKT_START_SLOW_WR_SPARE_U__PKT_START_SLOW_WR_SPARE_1___S 0 +#define PHYA_TXFD_PKT_START_SLOW_WR_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXFD_PKT_START_SLOW_WR_SPARE_U___S 0 + +#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_L (0x00391900) +#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_L__RU_ALLOCATION_3___POR 0x00 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_L__RU_ALLOCATION_2___POR 0x00 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_L__RU_ALLOCATION_1___POR 0x00 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_L__RU_ALLOCATION_0___POR 0x00 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_L__RU_ALLOCATION_3___M 0xFF000000 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_L__RU_ALLOCATION_3___S 24 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_L__RU_ALLOCATION_2___M 0x00FF0000 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_L__RU_ALLOCATION_2___S 16 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_L__RU_ALLOCATION_1___M 0x0000FF00 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_L__RU_ALLOCATION_1___S 8 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_L__RU_ALLOCATION_0___M 0x000000FF +#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_L__RU_ALLOCATION_0___S 0 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_L___M 0xFFFFFFFF +#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_L___S 0 + +#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_U (0x00391904) +#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_U___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_U___POR 0x00000000 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_U__RU_ALLOCATION_7___POR 0x00 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_U__RU_ALLOCATION_6___POR 0x00 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_U__RU_ALLOCATION_5___POR 0x00 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_U__RU_ALLOCATION_4___POR 0x00 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_U__RU_ALLOCATION_7___M 0xFF000000 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_U__RU_ALLOCATION_7___S 24 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_U__RU_ALLOCATION_6___M 0x00FF0000 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_U__RU_ALLOCATION_6___S 16 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_U__RU_ALLOCATION_5___M 0x0000FF00 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_U__RU_ALLOCATION_5___S 8 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_U__RU_ALLOCATION_4___M 0x000000FF +#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_U__RU_ALLOCATION_4___S 0 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_U___M 0xFFFFFFFF +#define PHYA_TXFD_RU_ALLOC_CORR_WR_0_U___S 0 + +#define PHYA_TXFD_RU_ALLOC_CORR_WR_1_L (0x00391908) +#define PHYA_TXFD_RU_ALLOC_CORR_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_ALLOC_CORR_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_1_L__ALPHA___POR 0x0 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_1_L__ALPHA___M 0x00000003 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_1_L__ALPHA___S 0 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_1_L___M 0x00000003 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_1_L___S 0 + +#define PHYA_TXFD_RU_ALLOC_CORR_WR_SPARE_L (0x00391910) +#define PHYA_TXFD_RU_ALLOC_CORR_WR_SPARE_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_ALLOC_CORR_WR_SPARE_L___POR 0x00000000 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_SPARE_L__RU_ALLOC_CORR_WR_SPARE_0___POR 0x00000000 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_SPARE_L__RU_ALLOC_CORR_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXFD_RU_ALLOC_CORR_WR_SPARE_L__RU_ALLOC_CORR_WR_SPARE_0___S 0 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXFD_RU_ALLOC_CORR_WR_SPARE_L___S 0 + +#define PHYA_TXFD_RU_ALLOC_CORR_WR_SPARE_U (0x00391914) +#define PHYA_TXFD_RU_ALLOC_CORR_WR_SPARE_U___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_ALLOC_CORR_WR_SPARE_U___POR 0x00000000 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_SPARE_U__RU_ALLOC_CORR_WR_SPARE_1___POR 0x00000000 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_SPARE_U__RU_ALLOC_CORR_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXFD_RU_ALLOC_CORR_WR_SPARE_U__RU_ALLOC_CORR_WR_SPARE_1___S 0 +#define PHYA_TXFD_RU_ALLOC_CORR_WR_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXFD_RU_ALLOC_CORR_WR_SPARE_U___S 0 + +#define PHYA_TXFD_ERROR_EVENT_RD_0_L (0x00391918) +#define PHYA_TXFD_ERROR_EVENT_RD_0_L___RWC QCSR_REG_RO +#define PHYA_TXFD_ERROR_EVENT_RD_0_L___POR 0x00000000 +#define PHYA_TXFD_ERROR_EVENT_RD_0_L__ERROR_NUM_PAD_BITS_USER___POR 0x00 +#define PHYA_TXFD_ERROR_EVENT_RD_0_L__ERROR_NUM_PAD_BITS_USER___M 0x000000FF +#define PHYA_TXFD_ERROR_EVENT_RD_0_L__ERROR_NUM_PAD_BITS_USER___S 0 +#define PHYA_TXFD_ERROR_EVENT_RD_0_L___M 0x000000FF +#define PHYA_TXFD_ERROR_EVENT_RD_0_L___S 0 + +#define PHYA_TXFD_ERROR_EVENT_RD_0_U (0x0039191C) +#define PHYA_TXFD_ERROR_EVENT_RD_0_U___RWC QCSR_REG_RO +#define PHYA_TXFD_ERROR_EVENT_RD_0_U___POR 0x00000000 +#define PHYA_TXFD_ERROR_EVENT_RD_0_U__ERROR_LSIG_TIMER_COUNT___POR 0x00000000 +#define PHYA_TXFD_ERROR_EVENT_RD_0_U__ERROR_LSIG_TIMER_COUNT___M 0xFFFFFFFF +#define PHYA_TXFD_ERROR_EVENT_RD_0_U__ERROR_LSIG_TIMER_COUNT___S 0 +#define PHYA_TXFD_ERROR_EVENT_RD_0_U___M 0xFFFFFFFF +#define PHYA_TXFD_ERROR_EVENT_RD_0_U___S 0 + +#define PHYA_TXFD_ERROR_EVENT_RD_1_L (0x00391920) +#define PHYA_TXFD_ERROR_EVENT_RD_1_L___RWC QCSR_REG_RO +#define PHYA_TXFD_ERROR_EVENT_RD_1_L___POR 0x00000000 +#define PHYA_TXFD_ERROR_EVENT_RD_1_L__ERROR_TXB_STATUS___POR 0x00000000 +#define PHYA_TXFD_ERROR_EVENT_RD_1_L__ERROR_TXB_STATUS___M 0xFFFFFFFF +#define PHYA_TXFD_ERROR_EVENT_RD_1_L__ERROR_TXB_STATUS___S 0 +#define PHYA_TXFD_ERROR_EVENT_RD_1_L___M 0xFFFFFFFF +#define PHYA_TXFD_ERROR_EVENT_RD_1_L___S 0 + +#define PHYA_TXFD_ERROR_EVENT_RD_1_U (0x00391924) +#define PHYA_TXFD_ERROR_EVENT_RD_1_U___RWC QCSR_REG_RO +#define PHYA_TXFD_ERROR_EVENT_RD_1_U___POR 0x00000000 +#define PHYA_TXFD_ERROR_EVENT_RD_1_U__HW_ACC_ERROR_STATUS___POR 0x00000000 +#define PHYA_TXFD_ERROR_EVENT_RD_1_U__HW_ACC_ERROR_STATUS___M 0xFFFFFFFF +#define PHYA_TXFD_ERROR_EVENT_RD_1_U__HW_ACC_ERROR_STATUS___S 0 +#define PHYA_TXFD_ERROR_EVENT_RD_1_U___M 0xFFFFFFFF +#define PHYA_TXFD_ERROR_EVENT_RD_1_U___S 0 + +#define PHYA_TXFD_ERROR_EVENT_RD_2_L (0x00391928) +#define PHYA_TXFD_ERROR_EVENT_RD_2_L___RWC QCSR_REG_RO +#define PHYA_TXFD_ERROR_EVENT_RD_2_L___POR 0x00000000 +#define PHYA_TXFD_ERROR_EVENT_RD_2_L__USER_DATA_REQ_CNT___POR 0x00000000 +#define PHYA_TXFD_ERROR_EVENT_RD_2_L__USER_DATA_REQ_CNT___M 0xFFFFFFFF +#define PHYA_TXFD_ERROR_EVENT_RD_2_L__USER_DATA_REQ_CNT___S 0 +#define PHYA_TXFD_ERROR_EVENT_RD_2_L___M 0xFFFFFFFF +#define PHYA_TXFD_ERROR_EVENT_RD_2_L___S 0 + +#define PHYA_TXFD_ERROR_EVENT_RD_2_U (0x0039192C) +#define PHYA_TXFD_ERROR_EVENT_RD_2_U___RWC QCSR_REG_RO +#define PHYA_TXFD_ERROR_EVENT_RD_2_U___POR 0x00000000 +#define PHYA_TXFD_ERROR_EVENT_RD_2_U__USER_DATA_RESP_CNT___POR 0x00000000 +#define PHYA_TXFD_ERROR_EVENT_RD_2_U__USER_DATA_RESP_CNT___M 0xFFFFFFFF +#define PHYA_TXFD_ERROR_EVENT_RD_2_U__USER_DATA_RESP_CNT___S 0 +#define PHYA_TXFD_ERROR_EVENT_RD_2_U___M 0xFFFFFFFF +#define PHYA_TXFD_ERROR_EVENT_RD_2_U___S 0 + +#define PHYA_TXFD_ERROR_RD_SPARE_0_L (0x00391930) +#define PHYA_TXFD_ERROR_RD_SPARE_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_ERROR_RD_SPARE_0_L___POR 0x00000000 +#define PHYA_TXFD_ERROR_RD_SPARE_0_L__ERROR_EVENT_RD_SPARE_0___POR 0x00000000 +#define PHYA_TXFD_ERROR_RD_SPARE_0_L__ERROR_EVENT_RD_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXFD_ERROR_RD_SPARE_0_L__ERROR_EVENT_RD_SPARE_0___S 0 +#define PHYA_TXFD_ERROR_RD_SPARE_0_L___M 0xFFFFFFFF +#define PHYA_TXFD_ERROR_RD_SPARE_0_L___S 0 + +#define PHYA_TXFD_ERROR_RD_SPARE_0_U (0x00391934) +#define PHYA_TXFD_ERROR_RD_SPARE_0_U___RWC QCSR_REG_RW +#define PHYA_TXFD_ERROR_RD_SPARE_0_U___POR 0x00000000 +#define PHYA_TXFD_ERROR_RD_SPARE_0_U__ERROR_EVENT_RD_SPARE_1___POR 0x00000000 +#define PHYA_TXFD_ERROR_RD_SPARE_0_U__ERROR_EVENT_RD_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXFD_ERROR_RD_SPARE_0_U__ERROR_EVENT_RD_SPARE_1___S 0 +#define PHYA_TXFD_ERROR_RD_SPARE_0_U___M 0xFFFFFFFF +#define PHYA_TXFD_ERROR_RD_SPARE_0_U___S 0 + +#define PHYA_TXFD_ERROR_EVENT_WR_L (0x00391938) +#define PHYA_TXFD_ERROR_EVENT_WR_L___RWC QCSR_REG_RW +#define PHYA_TXFD_ERROR_EVENT_WR_L___POR 0x00000000 +#define PHYA_TXFD_ERROR_EVENT_WR_L__DEBUG_PROBE_USER_ID___POR 0x00 +#define PHYA_TXFD_ERROR_EVENT_WR_L__MACTX_PHYTX_ASYNC_FIFO_BACK_PRESSURE___POR 0x0 +#define PHYA_TXFD_ERROR_EVENT_WR_L__TXFD_ABORT___POR 0x0 +#define PHYA_TXFD_ERROR_EVENT_WR_L__DEBUG_PROBE_USER_ID___M 0x003F0000 +#define PHYA_TXFD_ERROR_EVENT_WR_L__DEBUG_PROBE_USER_ID___S 16 +#define PHYA_TXFD_ERROR_EVENT_WR_L__MACTX_PHYTX_ASYNC_FIFO_BACK_PRESSURE___M 0x00000100 +#define PHYA_TXFD_ERROR_EVENT_WR_L__MACTX_PHYTX_ASYNC_FIFO_BACK_PRESSURE___S 8 +#define PHYA_TXFD_ERROR_EVENT_WR_L__TXFD_ABORT___M 0x00000001 +#define PHYA_TXFD_ERROR_EVENT_WR_L__TXFD_ABORT___S 0 +#define PHYA_TXFD_ERROR_EVENT_WR_L___M 0x003F0101 +#define PHYA_TXFD_ERROR_EVENT_WR_L___S 0 + +#define PHYA_TXFD_ERROR_RD_SPARE_1_L (0x00391940) +#define PHYA_TXFD_ERROR_RD_SPARE_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_ERROR_RD_SPARE_1_L___POR 0x00000000 +#define PHYA_TXFD_ERROR_RD_SPARE_1_L__ERROR_EVENT_WR_SPARE_0___POR 0x00000000 +#define PHYA_TXFD_ERROR_RD_SPARE_1_L__ERROR_EVENT_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXFD_ERROR_RD_SPARE_1_L__ERROR_EVENT_WR_SPARE_0___S 0 +#define PHYA_TXFD_ERROR_RD_SPARE_1_L___M 0xFFFFFFFF +#define PHYA_TXFD_ERROR_RD_SPARE_1_L___S 0 + +#define PHYA_TXFD_ERROR_RD_SPARE_1_U (0x00391944) +#define PHYA_TXFD_ERROR_RD_SPARE_1_U___RWC QCSR_REG_RW +#define PHYA_TXFD_ERROR_RD_SPARE_1_U___POR 0x00000000 +#define PHYA_TXFD_ERROR_RD_SPARE_1_U__ERROR_EVENT_WR_SPARE_1___POR 0x00000000 +#define PHYA_TXFD_ERROR_RD_SPARE_1_U__ERROR_EVENT_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXFD_ERROR_RD_SPARE_1_U__ERROR_EVENT_WR_SPARE_1___S 0 +#define PHYA_TXFD_ERROR_RD_SPARE_1_U___M 0xFFFFFFFF +#define PHYA_TXFD_ERROR_RD_SPARE_1_U___S 0 + +#define PHYA_TXFD_FW_SYM_START_WR_L (0x00391948) +#define PHYA_TXFD_FW_SYM_START_WR_L___RWC QCSR_REG_RW +#define PHYA_TXFD_FW_SYM_START_WR_L___POR 0x00000000 +#define PHYA_TXFD_FW_SYM_START_WR_L__PE_PMAT_COL_NUM___POR 0x0 +#define PHYA_TXFD_FW_SYM_START_WR_L__SUBBAND_PHASE_ROT___POR 0x0000 +#define PHYA_TXFD_FW_SYM_START_WR_L__PE_PMAT_COL_NUM___M 0x00070000 +#define PHYA_TXFD_FW_SYM_START_WR_L__PE_PMAT_COL_NUM___S 16 +#define PHYA_TXFD_FW_SYM_START_WR_L__SUBBAND_PHASE_ROT___M 0x0000FFFF +#define PHYA_TXFD_FW_SYM_START_WR_L__SUBBAND_PHASE_ROT___S 0 +#define PHYA_TXFD_FW_SYM_START_WR_L___M 0x0007FFFF +#define PHYA_TXFD_FW_SYM_START_WR_L___S 0 + +#define PHYA_TXFD_NULL_LUT_2_L (0x00391950) +#define PHYA_TXFD_NULL_LUT_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_NULL_LUT_2_L___POR 0x00001222 +#define PHYA_TXFD_NULL_LUT_2_L__PER_SYM_FFT_SCALE___POR 0x001222 +#define PHYA_TXFD_NULL_LUT_2_L__PER_SYM_FFT_SCALE___M 0x00FFFFFF +#define PHYA_TXFD_NULL_LUT_2_L__PER_SYM_FFT_SCALE___S 0 +#define PHYA_TXFD_NULL_LUT_2_L___M 0x00FFFFFF +#define PHYA_TXFD_NULL_LUT_2_L___S 0 + +#define PHYA_TXFD_FW_SYM_START_WR_SPARE_L (0x00391958) +#define PHYA_TXFD_FW_SYM_START_WR_SPARE_L___RWC QCSR_REG_RW +#define PHYA_TXFD_FW_SYM_START_WR_SPARE_L___POR 0x00000000 +#define PHYA_TXFD_FW_SYM_START_WR_SPARE_L__FW_SYM_START_WR_SPARE_0___POR 0x00000000 +#define PHYA_TXFD_FW_SYM_START_WR_SPARE_L__FW_SYM_START_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXFD_FW_SYM_START_WR_SPARE_L__FW_SYM_START_WR_SPARE_0___S 0 +#define PHYA_TXFD_FW_SYM_START_WR_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXFD_FW_SYM_START_WR_SPARE_L___S 0 + +#define PHYA_TXFD_FW_SYM_START_WR_SPARE_U (0x0039195C) +#define PHYA_TXFD_FW_SYM_START_WR_SPARE_U___RWC QCSR_REG_RW +#define PHYA_TXFD_FW_SYM_START_WR_SPARE_U___POR 0x00000000 +#define PHYA_TXFD_FW_SYM_START_WR_SPARE_U__FW_SYM_START_WR_SPARE_1___POR 0x00000000 +#define PHYA_TXFD_FW_SYM_START_WR_SPARE_U__FW_SYM_START_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXFD_FW_SYM_START_WR_SPARE_U__FW_SYM_START_WR_SPARE_1___S 0 +#define PHYA_TXFD_FW_SYM_START_WR_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXFD_FW_SYM_START_WR_SPARE_U___S 0 + +#define PHYA_TXFD_ALL_SYM_START_RD_L (0x00391960) +#define PHYA_TXFD_ALL_SYM_START_RD_L___RWC QCSR_REG_RO +#define PHYA_TXFD_ALL_SYM_START_RD_L___POR 0x00000000 +#define PHYA_TXFD_ALL_SYM_START_RD_L__SYM_START_DONE_COUNT___POR 0x0000 +#define PHYA_TXFD_ALL_SYM_START_RD_L__CURRENT_SYM___POR 0x00 +#define PHYA_TXFD_ALL_SYM_START_RD_L__SYM_START_DONE_COUNT___M 0xFFFF0000 +#define PHYA_TXFD_ALL_SYM_START_RD_L__SYM_START_DONE_COUNT___S 16 +#define PHYA_TXFD_ALL_SYM_START_RD_L__CURRENT_SYM___M 0x0000001F +#define PHYA_TXFD_ALL_SYM_START_RD_L__CURRENT_SYM___S 0 +#define PHYA_TXFD_ALL_SYM_START_RD_L___M 0xFFFF001F +#define PHYA_TXFD_ALL_SYM_START_RD_L___S 0 + +#define PHYA_TXFD_ALL_SYM_START_RD_U (0x00391964) +#define PHYA_TXFD_ALL_SYM_START_RD_U___RWC QCSR_REG_RO +#define PHYA_TXFD_ALL_SYM_START_RD_U___POR 0x00000000 +#define PHYA_TXFD_ALL_SYM_START_RD_U__SYM_DONE_START_COUNT___POR 0x0000 +#define PHYA_TXFD_ALL_SYM_START_RD_U__SYM_DONE_START_COUNT___M 0x0000FFFF +#define PHYA_TXFD_ALL_SYM_START_RD_U__SYM_DONE_START_COUNT___S 0 +#define PHYA_TXFD_ALL_SYM_START_RD_U___M 0x0000FFFF +#define PHYA_TXFD_ALL_SYM_START_RD_U___S 0 + +#define PHYA_TXFD_ALL_SYM_START_RD_SPARE_L (0x00391968) +#define PHYA_TXFD_ALL_SYM_START_RD_SPARE_L___RWC QCSR_REG_RW +#define PHYA_TXFD_ALL_SYM_START_RD_SPARE_L___POR 0x00000000 +#define PHYA_TXFD_ALL_SYM_START_RD_SPARE_L__ALL_SYM_START_RD_SPARE_0___POR 0x00000000 +#define PHYA_TXFD_ALL_SYM_START_RD_SPARE_L__ALL_SYM_START_RD_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXFD_ALL_SYM_START_RD_SPARE_L__ALL_SYM_START_RD_SPARE_0___S 0 +#define PHYA_TXFD_ALL_SYM_START_RD_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXFD_ALL_SYM_START_RD_SPARE_L___S 0 + +#define PHYA_TXFD_ALL_SYM_START_RD_SPARE_U (0x0039196C) +#define PHYA_TXFD_ALL_SYM_START_RD_SPARE_U___RWC QCSR_REG_RW +#define PHYA_TXFD_ALL_SYM_START_RD_SPARE_U___POR 0x00000000 +#define PHYA_TXFD_ALL_SYM_START_RD_SPARE_U__ALL_SYM_START_RD_SPARE_1___POR 0x00000000 +#define PHYA_TXFD_ALL_SYM_START_RD_SPARE_U__ALL_SYM_START_RD_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXFD_ALL_SYM_START_RD_SPARE_U__ALL_SYM_START_RD_SPARE_1___S 0 +#define PHYA_TXFD_ALL_SYM_START_RD_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXFD_ALL_SYM_START_RD_SPARE_U___S 0 + +#define PHYA_TXFD_ALL_SYM_START_WR_L (0x00391970) +#define PHYA_TXFD_ALL_SYM_START_WR_L___RWC QCSR_REG_RW +#define PHYA_TXFD_ALL_SYM_START_WR_L___POR 0x00000000 +#define PHYA_TXFD_ALL_SYM_START_WR_L__FFT_OUT_BUF_OFFSET___POR 0x000 +#define PHYA_TXFD_ALL_SYM_START_WR_L__FFT_MODE___POR 0x0 +#define PHYA_TXFD_ALL_SYM_START_WR_L__FFT_OUT_BUF_OFFSET___M 0x07FF0000 +#define PHYA_TXFD_ALL_SYM_START_WR_L__FFT_OUT_BUF_OFFSET___S 16 +#define PHYA_TXFD_ALL_SYM_START_WR_L__FFT_MODE___M 0x00000003 +#define PHYA_TXFD_ALL_SYM_START_WR_L__FFT_MODE___S 0 +#define PHYA_TXFD_ALL_SYM_START_WR_L___M 0x07FF0003 +#define PHYA_TXFD_ALL_SYM_START_WR_L___S 0 + +#define PHYA_TXFD_ALL_SYM_START_WR_U (0x00391974) +#define PHYA_TXFD_ALL_SYM_START_WR_U___RWC QCSR_REG_RW +#define PHYA_TXFD_ALL_SYM_START_WR_U___POR 0x00000000 +#define PHYA_TXFD_ALL_SYM_START_WR_U__FFT_IN_BUF_OFFSET___POR 0x000 +#define PHYA_TXFD_ALL_SYM_START_WR_U__FFT_IN_BUF_OFFSET___M 0x000007FF +#define PHYA_TXFD_ALL_SYM_START_WR_U__FFT_IN_BUF_OFFSET___S 0 +#define PHYA_TXFD_ALL_SYM_START_WR_U___M 0x000007FF +#define PHYA_TXFD_ALL_SYM_START_WR_U___S 0 + +#define PHYA_TXFD_WUR_ALL_SYM_START_WR_L (0x00391978) +#define PHYA_TXFD_WUR_ALL_SYM_START_WR_L___RWC QCSR_REG_RW +#define PHYA_TXFD_WUR_ALL_SYM_START_WR_L___POR 0x00000000 +#define PHYA_TXFD_WUR_ALL_SYM_START_WR_L__WUR_LFSR_CSD___POR 0x00 +#define PHYA_TXFD_WUR_ALL_SYM_START_WR_L__WUR_LFSR_CSD___M 0x000000FF +#define PHYA_TXFD_WUR_ALL_SYM_START_WR_L__WUR_LFSR_CSD___S 0 +#define PHYA_TXFD_WUR_ALL_SYM_START_WR_L___M 0x000000FF +#define PHYA_TXFD_WUR_ALL_SYM_START_WR_L___S 0 + +#define PHYA_TXFD_ALL_SYM_START_WR_SPARE_L (0x00391980) +#define PHYA_TXFD_ALL_SYM_START_WR_SPARE_L___RWC QCSR_REG_RW +#define PHYA_TXFD_ALL_SYM_START_WR_SPARE_L___POR 0x00000000 +#define PHYA_TXFD_ALL_SYM_START_WR_SPARE_L__ALL_SYM_START_WR_SPARE_0___POR 0x00000000 +#define PHYA_TXFD_ALL_SYM_START_WR_SPARE_L__ALL_SYM_START_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXFD_ALL_SYM_START_WR_SPARE_L__ALL_SYM_START_WR_SPARE_0___S 0 +#define PHYA_TXFD_ALL_SYM_START_WR_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXFD_ALL_SYM_START_WR_SPARE_L___S 0 + +#define PHYA_TXFD_ALL_SYM_START_WR_SPARE_U (0x00391984) +#define PHYA_TXFD_ALL_SYM_START_WR_SPARE_U___RWC QCSR_REG_RW +#define PHYA_TXFD_ALL_SYM_START_WR_SPARE_U___POR 0x00000000 +#define PHYA_TXFD_ALL_SYM_START_WR_SPARE_U__ALL_SYM_START_WR_SPARE_1___POR 0x00000000 +#define PHYA_TXFD_ALL_SYM_START_WR_SPARE_U__ALL_SYM_START_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXFD_ALL_SYM_START_WR_SPARE_U__ALL_SYM_START_WR_SPARE_1___S 0 +#define PHYA_TXFD_ALL_SYM_START_WR_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXFD_ALL_SYM_START_WR_SPARE_U___S 0 + +#define PHYA_TXFD_CONTROL_TLV_FIFO_0_L_n(n) (0x00391988+0x8*(n)) +#define PHYA_TXFD_CONTROL_TLV_FIFO_0_L_n_nMIN 0 +#define PHYA_TXFD_CONTROL_TLV_FIFO_0_L_n_nMAX 0 +#define PHYA_TXFD_CONTROL_TLV_FIFO_0_L_n_ELEM 1 +#define PHYA_TXFD_CONTROL_TLV_FIFO_0_L_n___RWC QCSR_REG_RW +#define PHYA_TXFD_CONTROL_TLV_FIFO_0_L_n___POR 0x00000000 +#define PHYA_TXFD_CONTROL_TLV_FIFO_0_L_n__CONTROL_TLV_LAST___POR 0x0 +#define PHYA_TXFD_CONTROL_TLV_FIFO_0_L_n__CONTROL_TLV_START___POR 0x0 +#define PHYA_TXFD_CONTROL_TLV_FIFO_0_L_n__CONTROL_TLV_DATA___POR 0x0000 +#define PHYA_TXFD_CONTROL_TLV_FIFO_0_L_n__CONTROL_TLV_LAST___M 0x00020000 +#define PHYA_TXFD_CONTROL_TLV_FIFO_0_L_n__CONTROL_TLV_LAST___S 17 +#define PHYA_TXFD_CONTROL_TLV_FIFO_0_L_n__CONTROL_TLV_START___M 0x00010000 +#define PHYA_TXFD_CONTROL_TLV_FIFO_0_L_n__CONTROL_TLV_START___S 16 +#define PHYA_TXFD_CONTROL_TLV_FIFO_0_L_n__CONTROL_TLV_DATA___M 0x0000FFFF +#define PHYA_TXFD_CONTROL_TLV_FIFO_0_L_n__CONTROL_TLV_DATA___S 0 +#define PHYA_TXFD_CONTROL_TLV_FIFO_0_L_n___M 0x0003FFFF +#define PHYA_TXFD_CONTROL_TLV_FIFO_0_L_n___S 0 +#define PHYA_TXFD_CONTROL_TLV_FIFO_0_L_0 (0x00391988) +#define PHYA_TXFD_CONTROL_TLV_FIFO_0_L_0___RWC QCSR_REG_RW +#define PHYA_TXFD_CONTROL_TLV_FIFO_0_L_0__CONTROL_TLV_LAST___M 0x00020000 +#define PHYA_TXFD_CONTROL_TLV_FIFO_0_L_0__CONTROL_TLV_LAST___S 17 +#define PHYA_TXFD_CONTROL_TLV_FIFO_0_L_0__CONTROL_TLV_START___M 0x00010000 +#define PHYA_TXFD_CONTROL_TLV_FIFO_0_L_0__CONTROL_TLV_START___S 16 +#define PHYA_TXFD_CONTROL_TLV_FIFO_0_L_0__CONTROL_TLV_DATA___M 0x0000FFFF +#define PHYA_TXFD_CONTROL_TLV_FIFO_0_L_0__CONTROL_TLV_DATA___S 0 + +#define PHYA_TXFD_HE_SIGA_FIFO_L_n(n) (0x00391A08+0x8*(n)) +#define PHYA_TXFD_HE_SIGA_FIFO_L_n_nMIN 0 +#define PHYA_TXFD_HE_SIGA_FIFO_L_n_nMAX 0 +#define PHYA_TXFD_HE_SIGA_FIFO_L_n_ELEM 1 +#define PHYA_TXFD_HE_SIGA_FIFO_L_n___RWC QCSR_REG_RW +#define PHYA_TXFD_HE_SIGA_FIFO_L_n___POR 0x00000000 +#define PHYA_TXFD_HE_SIGA_FIFO_L_n__HE_SIGA_0___POR 0x00000000 +#define PHYA_TXFD_HE_SIGA_FIFO_L_n__HE_SIGA_0___M 0xFFFFFFFF +#define PHYA_TXFD_HE_SIGA_FIFO_L_n__HE_SIGA_0___S 0 +#define PHYA_TXFD_HE_SIGA_FIFO_L_n___M 0xFFFFFFFF +#define PHYA_TXFD_HE_SIGA_FIFO_L_n___S 0 +#define PHYA_TXFD_HE_SIGA_FIFO_L_0 (0x00391A08) +#define PHYA_TXFD_HE_SIGA_FIFO_L_0___RWC QCSR_REG_RW +#define PHYA_TXFD_HE_SIGA_FIFO_L_0__HE_SIGA_0___M 0xFFFFFFFF +#define PHYA_TXFD_HE_SIGA_FIFO_L_0__HE_SIGA_0___S 0 + +#define PHYA_TXFD_HE_SIGA_FIFO_U_n(n) (0x00391A0C+0x8*(n)) +#define PHYA_TXFD_HE_SIGA_FIFO_U_n_nMIN 0 +#define PHYA_TXFD_HE_SIGA_FIFO_U_n_nMAX 0 +#define PHYA_TXFD_HE_SIGA_FIFO_U_n_ELEM 1 +#define PHYA_TXFD_HE_SIGA_FIFO_U_n___RWC QCSR_REG_RW +#define PHYA_TXFD_HE_SIGA_FIFO_U_n___POR 0x00000000 +#define PHYA_TXFD_HE_SIGA_FIFO_U_n__HE_SIGA_1___POR 0x00000000 +#define PHYA_TXFD_HE_SIGA_FIFO_U_n__HE_SIGA_1___M 0xFFFFFFFF +#define PHYA_TXFD_HE_SIGA_FIFO_U_n__HE_SIGA_1___S 0 +#define PHYA_TXFD_HE_SIGA_FIFO_U_n___M 0xFFFFFFFF +#define PHYA_TXFD_HE_SIGA_FIFO_U_n___S 0 +#define PHYA_TXFD_HE_SIGA_FIFO_U_0 (0x00391A0C) +#define PHYA_TXFD_HE_SIGA_FIFO_U_0___RWC QCSR_REG_RW +#define PHYA_TXFD_HE_SIGA_FIFO_U_0__HE_SIGA_1___M 0xFFFFFFFF +#define PHYA_TXFD_HE_SIGA_FIFO_U_0__HE_SIGA_1___S 0 + +#define PHYA_TXFD_HE_SIGB_PARAMS_STRUCT_L (0x00391A88) +#define PHYA_TXFD_HE_SIGB_PARAMS_STRUCT_L___RWC QCSR_REG_RW +#define PHYA_TXFD_HE_SIGB_PARAMS_STRUCT_L___POR 0x00000000 +#define PHYA_TXFD_HE_SIGB_PARAMS_STRUCT_L__HE_SIGB_NUM_BITS_COMMON_EXTRA___POR 0x0 +#define PHYA_TXFD_HE_SIGB_PARAMS_STRUCT_L__HE_SIGB_NUM_BITS_COMMON_EXTRA___M 0x0000000F +#define PHYA_TXFD_HE_SIGB_PARAMS_STRUCT_L__HE_SIGB_NUM_BITS_COMMON_EXTRA___S 0 +#define PHYA_TXFD_HE_SIGB_PARAMS_STRUCT_L___M 0x0000000F +#define PHYA_TXFD_HE_SIGB_PARAMS_STRUCT_L___S 0 + +#define PHYA_TXFD_HE_SIGB_PARAMS_STRUCT_U (0x00391A8C) +#define PHYA_TXFD_HE_SIGB_PARAMS_STRUCT_U___RWC QCSR_REG_RW +#define PHYA_TXFD_HE_SIGB_PARAMS_STRUCT_U___POR 0x00000000 +#define PHYA_TXFD_HE_SIGB_PARAMS_STRUCT_U__HE_SIGB_PAD___POR 0x00000000 +#define PHYA_TXFD_HE_SIGB_PARAMS_STRUCT_U__HE_SIGB_PAD___M 0xFFFFFFFF +#define PHYA_TXFD_HE_SIGB_PARAMS_STRUCT_U__HE_SIGB_PAD___S 0 +#define PHYA_TXFD_HE_SIGB_PARAMS_STRUCT_U___M 0xFFFFFFFF +#define PHYA_TXFD_HE_SIGB_PARAMS_STRUCT_U___S 0 + +#define PHYA_TXFD_HE_SIGB0_FIFO_L_n(n) (0x00391A90+0x8*(n)) +#define PHYA_TXFD_HE_SIGB0_FIFO_L_n_nMIN 0 +#define PHYA_TXFD_HE_SIGB0_FIFO_L_n_nMAX 0 +#define PHYA_TXFD_HE_SIGB0_FIFO_L_n_ELEM 1 +#define PHYA_TXFD_HE_SIGB0_FIFO_L_n___RWC QCSR_REG_RW +#define PHYA_TXFD_HE_SIGB0_FIFO_L_n___POR 0x00000000 +#define PHYA_TXFD_HE_SIGB0_FIFO_L_n__HE_SIGB0_FIFO_0___POR 0x00000000 +#define PHYA_TXFD_HE_SIGB0_FIFO_L_n__HE_SIGB0_FIFO_0___M 0xFFFFFFFF +#define PHYA_TXFD_HE_SIGB0_FIFO_L_n__HE_SIGB0_FIFO_0___S 0 +#define PHYA_TXFD_HE_SIGB0_FIFO_L_n___M 0xFFFFFFFF +#define PHYA_TXFD_HE_SIGB0_FIFO_L_n___S 0 +#define PHYA_TXFD_HE_SIGB0_FIFO_L_0 (0x00391A90) +#define PHYA_TXFD_HE_SIGB0_FIFO_L_0___RWC QCSR_REG_RW +#define PHYA_TXFD_HE_SIGB0_FIFO_L_0__HE_SIGB0_FIFO_0___M 0xFFFFFFFF +#define PHYA_TXFD_HE_SIGB0_FIFO_L_0__HE_SIGB0_FIFO_0___S 0 + +#define PHYA_TXFD_HE_SIGB0_FIFO_U_n(n) (0x00391A94+0x8*(n)) +#define PHYA_TXFD_HE_SIGB0_FIFO_U_n_nMIN 0 +#define PHYA_TXFD_HE_SIGB0_FIFO_U_n_nMAX 0 +#define PHYA_TXFD_HE_SIGB0_FIFO_U_n_ELEM 1 +#define PHYA_TXFD_HE_SIGB0_FIFO_U_n___RWC QCSR_REG_RW +#define PHYA_TXFD_HE_SIGB0_FIFO_U_n___POR 0x00000000 +#define PHYA_TXFD_HE_SIGB0_FIFO_U_n__HE_SIGB0_FIFO_1___POR 0x00000000 +#define PHYA_TXFD_HE_SIGB0_FIFO_U_n__HE_SIGB0_FIFO_1___M 0xFFFFFFFF +#define PHYA_TXFD_HE_SIGB0_FIFO_U_n__HE_SIGB0_FIFO_1___S 0 +#define PHYA_TXFD_HE_SIGB0_FIFO_U_n___M 0xFFFFFFFF +#define PHYA_TXFD_HE_SIGB0_FIFO_U_n___S 0 +#define PHYA_TXFD_HE_SIGB0_FIFO_U_0 (0x00391A94) +#define PHYA_TXFD_HE_SIGB0_FIFO_U_0___RWC QCSR_REG_RW +#define PHYA_TXFD_HE_SIGB0_FIFO_U_0__HE_SIGB0_FIFO_1___M 0xFFFFFFFF +#define PHYA_TXFD_HE_SIGB0_FIFO_U_0__HE_SIGB0_FIFO_1___S 0 + +#define PHYA_TXFD_HE_SIGB1_FIFO_L_n(n) (0x00391B10+0x8*(n)) +#define PHYA_TXFD_HE_SIGB1_FIFO_L_n_nMIN 0 +#define PHYA_TXFD_HE_SIGB1_FIFO_L_n_nMAX 0 +#define PHYA_TXFD_HE_SIGB1_FIFO_L_n_ELEM 1 +#define PHYA_TXFD_HE_SIGB1_FIFO_L_n___RWC QCSR_REG_RW +#define PHYA_TXFD_HE_SIGB1_FIFO_L_n___POR 0x00000000 +#define PHYA_TXFD_HE_SIGB1_FIFO_L_n__HE_SIGB1_FIFO_0___POR 0x00000000 +#define PHYA_TXFD_HE_SIGB1_FIFO_L_n__HE_SIGB1_FIFO_0___M 0xFFFFFFFF +#define PHYA_TXFD_HE_SIGB1_FIFO_L_n__HE_SIGB1_FIFO_0___S 0 +#define PHYA_TXFD_HE_SIGB1_FIFO_L_n___M 0xFFFFFFFF +#define PHYA_TXFD_HE_SIGB1_FIFO_L_n___S 0 +#define PHYA_TXFD_HE_SIGB1_FIFO_L_0 (0x00391B10) +#define PHYA_TXFD_HE_SIGB1_FIFO_L_0___RWC QCSR_REG_RW +#define PHYA_TXFD_HE_SIGB1_FIFO_L_0__HE_SIGB1_FIFO_0___M 0xFFFFFFFF +#define PHYA_TXFD_HE_SIGB1_FIFO_L_0__HE_SIGB1_FIFO_0___S 0 + +#define PHYA_TXFD_HE_SIGB1_FIFO_U_n(n) (0x00391B14+0x8*(n)) +#define PHYA_TXFD_HE_SIGB1_FIFO_U_n_nMIN 0 +#define PHYA_TXFD_HE_SIGB1_FIFO_U_n_nMAX 0 +#define PHYA_TXFD_HE_SIGB1_FIFO_U_n_ELEM 1 +#define PHYA_TXFD_HE_SIGB1_FIFO_U_n___RWC QCSR_REG_RW +#define PHYA_TXFD_HE_SIGB1_FIFO_U_n___POR 0x00000000 +#define PHYA_TXFD_HE_SIGB1_FIFO_U_n__HE_SIGB1_FIFO_1___POR 0x00000000 +#define PHYA_TXFD_HE_SIGB1_FIFO_U_n__HE_SIGB1_FIFO_1___M 0xFFFFFFFF +#define PHYA_TXFD_HE_SIGB1_FIFO_U_n__HE_SIGB1_FIFO_1___S 0 +#define PHYA_TXFD_HE_SIGB1_FIFO_U_n___M 0xFFFFFFFF +#define PHYA_TXFD_HE_SIGB1_FIFO_U_n___S 0 +#define PHYA_TXFD_HE_SIGB1_FIFO_U_0 (0x00391B14) +#define PHYA_TXFD_HE_SIGB1_FIFO_U_0___RWC QCSR_REG_RW +#define PHYA_TXFD_HE_SIGB1_FIFO_U_0__HE_SIGB1_FIFO_1___M 0xFFFFFFFF +#define PHYA_TXFD_HE_SIGB1_FIFO_U_0__HE_SIGB1_FIFO_1___S 0 + +#define PHYA_TXFD_TLV_FIFO_L_n(n) (0x00391B90+0x8*(n)) +#define PHYA_TXFD_TLV_FIFO_L_n_nMIN 0 +#define PHYA_TXFD_TLV_FIFO_L_n_nMAX 0 +#define PHYA_TXFD_TLV_FIFO_L_n_ELEM 1 +#define PHYA_TXFD_TLV_FIFO_L_n___RWC QCSR_REG_RO +#define PHYA_TXFD_TLV_FIFO_L_n___POR 0x00000000 +#define PHYA_TXFD_TLV_FIFO_L_n__TLV_FIFO_0___POR 0x00000000 +#define PHYA_TXFD_TLV_FIFO_L_n__TLV_FIFO_0___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_FIFO_L_n__TLV_FIFO_0___S 0 +#define PHYA_TXFD_TLV_FIFO_L_n___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_FIFO_L_n___S 0 +#define PHYA_TXFD_TLV_FIFO_L_0 (0x00391B90) +#define PHYA_TXFD_TLV_FIFO_L_0___RWC QCSR_REG_RO +#define PHYA_TXFD_TLV_FIFO_L_0__TLV_FIFO_0___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_FIFO_L_0__TLV_FIFO_0___S 0 + +#define PHYA_TXFD_TLV_FIFO_U_n(n) (0x00391B94+0x8*(n)) +#define PHYA_TXFD_TLV_FIFO_U_n_nMIN 0 +#define PHYA_TXFD_TLV_FIFO_U_n_nMAX 0 +#define PHYA_TXFD_TLV_FIFO_U_n_ELEM 1 +#define PHYA_TXFD_TLV_FIFO_U_n___RWC QCSR_REG_RO +#define PHYA_TXFD_TLV_FIFO_U_n___POR 0x00000000 +#define PHYA_TXFD_TLV_FIFO_U_n__TLV_FIFO_1___POR 0x00000000 +#define PHYA_TXFD_TLV_FIFO_U_n__TLV_FIFO_1___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_FIFO_U_n__TLV_FIFO_1___S 0 +#define PHYA_TXFD_TLV_FIFO_U_n___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_FIFO_U_n___S 0 +#define PHYA_TXFD_TLV_FIFO_U_0 (0x00391B94) +#define PHYA_TXFD_TLV_FIFO_U_0___RWC QCSR_REG_RO +#define PHYA_TXFD_TLV_FIFO_U_0__TLV_FIFO_1___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_FIFO_U_0__TLV_FIFO_1___S 0 + +#define PHYA_TXFD_TLV_FIFO_PER_USER_L_n(n) (0x00391C10+0x8*(n)) +#define PHYA_TXFD_TLV_FIFO_PER_USER_L_n_nMIN 0 +#define PHYA_TXFD_TLV_FIFO_PER_USER_L_n_nMAX 0 +#define PHYA_TXFD_TLV_FIFO_PER_USER_L_n_ELEM 1 +#define PHYA_TXFD_TLV_FIFO_PER_USER_L_n___RWC QCSR_REG_RO +#define PHYA_TXFD_TLV_FIFO_PER_USER_L_n___POR 0x00000000 +#define PHYA_TXFD_TLV_FIFO_PER_USER_L_n__TLV_FIFO_PER_USER_0___POR 0x00000000 +#define PHYA_TXFD_TLV_FIFO_PER_USER_L_n__TLV_FIFO_PER_USER_0___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_FIFO_PER_USER_L_n__TLV_FIFO_PER_USER_0___S 0 +#define PHYA_TXFD_TLV_FIFO_PER_USER_L_n___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_FIFO_PER_USER_L_n___S 0 +#define PHYA_TXFD_TLV_FIFO_PER_USER_L_0 (0x00391C10) +#define PHYA_TXFD_TLV_FIFO_PER_USER_L_0___RWC QCSR_REG_RO +#define PHYA_TXFD_TLV_FIFO_PER_USER_L_0__TLV_FIFO_PER_USER_0___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_FIFO_PER_USER_L_0__TLV_FIFO_PER_USER_0___S 0 + +#define PHYA_TXFD_TLV_FIFO_PER_USER_U_n(n) (0x00391C14+0x8*(n)) +#define PHYA_TXFD_TLV_FIFO_PER_USER_U_n_nMIN 0 +#define PHYA_TXFD_TLV_FIFO_PER_USER_U_n_nMAX 0 +#define PHYA_TXFD_TLV_FIFO_PER_USER_U_n_ELEM 1 +#define PHYA_TXFD_TLV_FIFO_PER_USER_U_n___RWC QCSR_REG_RO +#define PHYA_TXFD_TLV_FIFO_PER_USER_U_n___POR 0x00000000 +#define PHYA_TXFD_TLV_FIFO_PER_USER_U_n__TLV_FIFO_PER_USER_1___POR 0x00000000 +#define PHYA_TXFD_TLV_FIFO_PER_USER_U_n__TLV_FIFO_PER_USER_1___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_FIFO_PER_USER_U_n__TLV_FIFO_PER_USER_1___S 0 +#define PHYA_TXFD_TLV_FIFO_PER_USER_U_n___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_FIFO_PER_USER_U_n___S 0 +#define PHYA_TXFD_TLV_FIFO_PER_USER_U_0 (0x00391C14) +#define PHYA_TXFD_TLV_FIFO_PER_USER_U_0___RWC QCSR_REG_RO +#define PHYA_TXFD_TLV_FIFO_PER_USER_U_0__TLV_FIFO_PER_USER_1___M 0xFFFFFFFF +#define PHYA_TXFD_TLV_FIFO_PER_USER_U_0__TLV_FIFO_PER_USER_1___S 0 + +#define PHYA_TXFD_PKT_END_RD_0_L (0x00391C90) +#define PHYA_TXFD_PKT_END_RD_0_L___RWC QCSR_REG_RO +#define PHYA_TXFD_PKT_END_RD_0_L___POR 0x00000000 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_31___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_30___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_29___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_28___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_27___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_26___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_25___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_24___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_23___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_22___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_21___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_20___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_19___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_18___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_17___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_16___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_15___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_14___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_13___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_12___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_11___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_10___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_9___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_8___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_7___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_6___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_5___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_4___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_3___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_2___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_1___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_0___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_31___M 0x80000000 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_31___S 31 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_30___M 0x40000000 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_30___S 30 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_29___M 0x20000000 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_29___S 29 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_28___M 0x10000000 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_28___S 28 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_27___M 0x08000000 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_27___S 27 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_26___M 0x04000000 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_26___S 26 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_25___M 0x02000000 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_25___S 25 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_24___M 0x01000000 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_24___S 24 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_23___M 0x00800000 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_23___S 23 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_22___M 0x00400000 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_22___S 22 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_21___M 0x00200000 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_21___S 21 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_20___M 0x00100000 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_20___S 20 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_19___M 0x00080000 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_19___S 19 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_18___M 0x00040000 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_18___S 18 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_17___M 0x00020000 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_17___S 17 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_16___M 0x00010000 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_16___S 16 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_15___M 0x00008000 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_15___S 15 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_14___M 0x00004000 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_14___S 14 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_13___M 0x00002000 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_13___S 13 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_12___M 0x00001000 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_12___S 12 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_11___M 0x00000800 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_11___S 11 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_10___M 0x00000400 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_10___S 10 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_9___M 0x00000200 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_9___S 9 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_8___M 0x00000100 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_8___S 8 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_7___M 0x00000080 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_7___S 7 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_6___M 0x00000040 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_6___S 6 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_5___M 0x00000020 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_5___S 5 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_4___M 0x00000010 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_4___S 4 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_3___M 0x00000008 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_3___S 3 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_2___M 0x00000004 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_2___S 2 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_1___M 0x00000002 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_1___S 1 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_0___M 0x00000001 +#define PHYA_TXFD_PKT_END_RD_0_L__STATUS_MAC_PKT_END_0___S 0 +#define PHYA_TXFD_PKT_END_RD_0_L___M 0xFFFFFFFF +#define PHYA_TXFD_PKT_END_RD_0_L___S 0 + +#define PHYA_TXFD_PKT_END_RD_0_U (0x00391C94) +#define PHYA_TXFD_PKT_END_RD_0_U___RWC QCSR_REG_RO +#define PHYA_TXFD_PKT_END_RD_0_U___POR 0x00000000 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_63___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_62___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_61___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_60___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_59___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_58___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_57___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_56___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_55___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_54___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_53___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_52___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_51___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_50___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_49___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_48___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_47___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_46___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_45___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_44___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_43___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_42___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_41___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_40___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_39___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_38___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_37___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_36___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_35___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_34___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_33___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_32___POR 0x0 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_63___M 0x80000000 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_63___S 31 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_62___M 0x40000000 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_62___S 30 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_61___M 0x20000000 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_61___S 29 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_60___M 0x10000000 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_60___S 28 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_59___M 0x08000000 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_59___S 27 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_58___M 0x04000000 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_58___S 26 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_57___M 0x02000000 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_57___S 25 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_56___M 0x01000000 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_56___S 24 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_55___M 0x00800000 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_55___S 23 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_54___M 0x00400000 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_54___S 22 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_53___M 0x00200000 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_53___S 21 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_52___M 0x00100000 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_52___S 20 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_51___M 0x00080000 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_51___S 19 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_50___M 0x00040000 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_50___S 18 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_49___M 0x00020000 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_49___S 17 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_48___M 0x00010000 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_48___S 16 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_47___M 0x00008000 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_47___S 15 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_46___M 0x00004000 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_46___S 14 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_45___M 0x00002000 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_45___S 13 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_44___M 0x00001000 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_44___S 12 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_43___M 0x00000800 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_43___S 11 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_42___M 0x00000400 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_42___S 10 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_41___M 0x00000200 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_41___S 9 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_40___M 0x00000100 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_40___S 8 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_39___M 0x00000080 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_39___S 7 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_38___M 0x00000040 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_38___S 6 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_37___M 0x00000020 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_37___S 5 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_36___M 0x00000010 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_36___S 4 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_35___M 0x00000008 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_35___S 3 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_34___M 0x00000004 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_34___S 2 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_33___M 0x00000002 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_33___S 1 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_32___M 0x00000001 +#define PHYA_TXFD_PKT_END_RD_0_U__STATUS_MAC_PKT_END_32___S 0 +#define PHYA_TXFD_PKT_END_RD_0_U___M 0xFFFFFFFF +#define PHYA_TXFD_PKT_END_RD_0_U___S 0 + +#define PHYA_TXFD_PKT_END_RD_1_L (0x00391C98) +#define PHYA_TXFD_PKT_END_RD_1_L___RWC QCSR_REG_RO +#define PHYA_TXFD_PKT_END_RD_1_L___POR 0x00000000 +#define PHYA_TXFD_PKT_END_RD_1_L__BF_WEIGHTS_WAIT_TIME___POR 0x0000 +#define PHYA_TXFD_PKT_END_RD_1_L__BF_WEIGHTS_WAIT_TIME___M 0x0000FFFF +#define PHYA_TXFD_PKT_END_RD_1_L__BF_WEIGHTS_WAIT_TIME___S 0 +#define PHYA_TXFD_PKT_END_RD_1_L___M 0x0000FFFF +#define PHYA_TXFD_PKT_END_RD_1_L___S 0 + +#define PHYA_TXFD_PKT_END_SPARE_L (0x00391CA0) +#define PHYA_TXFD_PKT_END_SPARE_L___RWC QCSR_REG_RW +#define PHYA_TXFD_PKT_END_SPARE_L___POR 0x00000000 +#define PHYA_TXFD_PKT_END_SPARE_L__PKT_END_SPARE_0___POR 0x00000000 +#define PHYA_TXFD_PKT_END_SPARE_L__PKT_END_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXFD_PKT_END_SPARE_L__PKT_END_SPARE_0___S 0 +#define PHYA_TXFD_PKT_END_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXFD_PKT_END_SPARE_L___S 0 + +#define PHYA_TXFD_PKT_END_SPARE_U (0x00391CA4) +#define PHYA_TXFD_PKT_END_SPARE_U___RWC QCSR_REG_RW +#define PHYA_TXFD_PKT_END_SPARE_U___POR 0x00000000 +#define PHYA_TXFD_PKT_END_SPARE_U__PKT_END_SPARE_1___POR 0x00000000 +#define PHYA_TXFD_PKT_END_SPARE_U__PKT_END_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXFD_PKT_END_SPARE_U__PKT_END_SPARE_1___S 0 +#define PHYA_TXFD_PKT_END_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXFD_PKT_END_SPARE_U___S 0 + +#define PHYA_TXFD_MAC_ABORT_RD_L (0x00391CA8) +#define PHYA_TXFD_MAC_ABORT_RD_L___RWC QCSR_REG_RO +#define PHYA_TXFD_MAC_ABORT_RD_L___POR 0x00000000 +#define PHYA_TXFD_MAC_ABORT_RD_L__MAC_ABORT_SIGNATURE___POR 0x00000000 +#define PHYA_TXFD_MAC_ABORT_RD_L__MAC_ABORT_SIGNATURE___M 0xFFFFFFFF +#define PHYA_TXFD_MAC_ABORT_RD_L__MAC_ABORT_SIGNATURE___S 0 +#define PHYA_TXFD_MAC_ABORT_RD_L___M 0xFFFFFFFF +#define PHYA_TXFD_MAC_ABORT_RD_L___S 0 + +#define PHYA_TXFD_MAC_ABORT_RD_SPARE_L (0x00391CB0) +#define PHYA_TXFD_MAC_ABORT_RD_SPARE_L___RWC QCSR_REG_RW +#define PHYA_TXFD_MAC_ABORT_RD_SPARE_L___POR 0x00000000 +#define PHYA_TXFD_MAC_ABORT_RD_SPARE_L__MAC_ABORT_RD_SPARE_0___POR 0x00000000 +#define PHYA_TXFD_MAC_ABORT_RD_SPARE_L__MAC_ABORT_RD_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXFD_MAC_ABORT_RD_SPARE_L__MAC_ABORT_RD_SPARE_0___S 0 +#define PHYA_TXFD_MAC_ABORT_RD_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXFD_MAC_ABORT_RD_SPARE_L___S 0 + +#define PHYA_TXFD_MAC_ABORT_RD_SPARE_U (0x00391CB4) +#define PHYA_TXFD_MAC_ABORT_RD_SPARE_U___RWC QCSR_REG_RW +#define PHYA_TXFD_MAC_ABORT_RD_SPARE_U___POR 0x00000000 +#define PHYA_TXFD_MAC_ABORT_RD_SPARE_U__MAC_ABORT_RD_SPARE_1___POR 0x00000000 +#define PHYA_TXFD_MAC_ABORT_RD_SPARE_U__MAC_ABORT_RD_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXFD_MAC_ABORT_RD_SPARE_U__MAC_ABORT_RD_SPARE_1___S 0 +#define PHYA_TXFD_MAC_ABORT_RD_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXFD_MAC_ABORT_RD_SPARE_U___S 0 + +#define PHYA_TXFD_HE_SIGA_SYM_WR_0_L (0x00391CB8) +#define PHYA_TXFD_HE_SIGA_SYM_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_HE_SIGA_SYM_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_HE_SIGA_SYM_WR_0_L__NUM_UNIQUE_BANDS___POR 0x0 +#define PHYA_TXFD_HE_SIGA_SYM_WR_0_L__NUM_HE_SIGB_SYM___POR 0x0 +#define PHYA_TXFD_HE_SIGA_SYM_WR_0_L__HESIGA_REP___POR 0x0 +#define PHYA_TXFD_HE_SIGA_SYM_WR_0_L__NUM_UNIQUE_BANDS___M 0x000F0000 +#define PHYA_TXFD_HE_SIGA_SYM_WR_0_L__NUM_UNIQUE_BANDS___S 16 +#define PHYA_TXFD_HE_SIGA_SYM_WR_0_L__NUM_HE_SIGB_SYM___M 0x00000F00 +#define PHYA_TXFD_HE_SIGA_SYM_WR_0_L__NUM_HE_SIGB_SYM___S 8 +#define PHYA_TXFD_HE_SIGA_SYM_WR_0_L__HESIGA_REP___M 0x00000001 +#define PHYA_TXFD_HE_SIGA_SYM_WR_0_L__HESIGA_REP___S 0 +#define PHYA_TXFD_HE_SIGA_SYM_WR_0_L___M 0x000F0F01 +#define PHYA_TXFD_HE_SIGA_SYM_WR_0_L___S 0 + +#define PHYA_TXFD_HE_SIGA_SYM_WR_0_U (0x00391CBC) +#define PHYA_TXFD_HE_SIGA_SYM_WR_0_U___RWC QCSR_REG_RW +#define PHYA_TXFD_HE_SIGA_SYM_WR_0_U___POR 0x00000000 +#define PHYA_TXFD_HE_SIGA_SYM_WR_0_U__HE_SIGB_NDBPS___POR 0x00000 +#define PHYA_TXFD_HE_SIGA_SYM_WR_0_U__HE_SIGB_NDBPS___M 0x0001FFFF +#define PHYA_TXFD_HE_SIGA_SYM_WR_0_U__HE_SIGB_NDBPS___S 0 +#define PHYA_TXFD_HE_SIGA_SYM_WR_0_U___M 0x0001FFFF +#define PHYA_TXFD_HE_SIGA_SYM_WR_0_U___S 0 + +#define PHYA_TXFD_HE_SIGA_SYM_WR_1_L (0x00391CC0) +#define PHYA_TXFD_HE_SIGA_SYM_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_HE_SIGA_SYM_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_HE_SIGA_SYM_WR_1_L__HE_SIGB_COMPRESSION___POR 0x0 +#define PHYA_TXFD_HE_SIGA_SYM_WR_1_L__HE_SIGB_DCM___POR 0x0 +#define PHYA_TXFD_HE_SIGA_SYM_WR_1_L__HE_SIGB_QAM___POR 0x0 +#define PHYA_TXFD_HE_SIGA_SYM_WR_1_L__HE_SIGB_CODE_RATE___POR 0x0 +#define PHYA_TXFD_HE_SIGA_SYM_WR_1_L__HE_SIGB_COMPRESSION___M 0x01000000 +#define PHYA_TXFD_HE_SIGA_SYM_WR_1_L__HE_SIGB_COMPRESSION___S 24 +#define PHYA_TXFD_HE_SIGA_SYM_WR_1_L__HE_SIGB_DCM___M 0x00010000 +#define PHYA_TXFD_HE_SIGA_SYM_WR_1_L__HE_SIGB_DCM___S 16 +#define PHYA_TXFD_HE_SIGA_SYM_WR_1_L__HE_SIGB_QAM___M 0x00000700 +#define PHYA_TXFD_HE_SIGA_SYM_WR_1_L__HE_SIGB_QAM___S 8 +#define PHYA_TXFD_HE_SIGA_SYM_WR_1_L__HE_SIGB_CODE_RATE___M 0x00000007 +#define PHYA_TXFD_HE_SIGA_SYM_WR_1_L__HE_SIGB_CODE_RATE___S 0 +#define PHYA_TXFD_HE_SIGA_SYM_WR_1_L___M 0x01010707 +#define PHYA_TXFD_HE_SIGA_SYM_WR_1_L___S 0 + +#define PHYA_TXFD_HE_SIGA_SYM_WR_1_U (0x00391CC4) +#define PHYA_TXFD_HE_SIGA_SYM_WR_1_U___RWC QCSR_REG_RW +#define PHYA_TXFD_HE_SIGA_SYM_WR_1_U___POR 0x00000000 +#define PHYA_TXFD_HE_SIGA_SYM_WR_1_U__HE_SIGB1_NUM_USERS___POR 0x00 +#define PHYA_TXFD_HE_SIGA_SYM_WR_1_U__HE_SIGB0_NUM_USERS___POR 0x00 +#define PHYA_TXFD_HE_SIGA_SYM_WR_1_U__HE_SIGB_NUM_20MHZ_BANDS___POR 0x0 +#define PHYA_TXFD_HE_SIGA_SYM_WR_1_U__HE_SIGB1_NUM_USERS___M 0x00FF0000 +#define PHYA_TXFD_HE_SIGA_SYM_WR_1_U__HE_SIGB1_NUM_USERS___S 16 +#define PHYA_TXFD_HE_SIGA_SYM_WR_1_U__HE_SIGB0_NUM_USERS___M 0x0000FF00 +#define PHYA_TXFD_HE_SIGA_SYM_WR_1_U__HE_SIGB0_NUM_USERS___S 8 +#define PHYA_TXFD_HE_SIGA_SYM_WR_1_U__HE_SIGB_NUM_20MHZ_BANDS___M 0x00000003 +#define PHYA_TXFD_HE_SIGA_SYM_WR_1_U__HE_SIGB_NUM_20MHZ_BANDS___S 0 +#define PHYA_TXFD_HE_SIGA_SYM_WR_1_U___M 0x00FFFF03 +#define PHYA_TXFD_HE_SIGA_SYM_WR_1_U___S 0 + +#define PHYA_TXFD_HE_SIGA_SYM_WR_SPARE_L (0x00391CC8) +#define PHYA_TXFD_HE_SIGA_SYM_WR_SPARE_L___RWC QCSR_REG_RW +#define PHYA_TXFD_HE_SIGA_SYM_WR_SPARE_L___POR 0x00000000 +#define PHYA_TXFD_HE_SIGA_SYM_WR_SPARE_L__HE_SIGA_SYM_WR_SPARE_0___POR 0x00000000 +#define PHYA_TXFD_HE_SIGA_SYM_WR_SPARE_L__HE_SIGA_SYM_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXFD_HE_SIGA_SYM_WR_SPARE_L__HE_SIGA_SYM_WR_SPARE_0___S 0 +#define PHYA_TXFD_HE_SIGA_SYM_WR_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXFD_HE_SIGA_SYM_WR_SPARE_L___S 0 + +#define PHYA_TXFD_HE_SIGA_SYM_WR_SPARE_U (0x00391CCC) +#define PHYA_TXFD_HE_SIGA_SYM_WR_SPARE_U___RWC QCSR_REG_RW +#define PHYA_TXFD_HE_SIGA_SYM_WR_SPARE_U___POR 0x00000000 +#define PHYA_TXFD_HE_SIGA_SYM_WR_SPARE_U__HE_SIGA_SYM_WR_SPARE_1___POR 0x00000000 +#define PHYA_TXFD_HE_SIGA_SYM_WR_SPARE_U__HE_SIGA_SYM_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXFD_HE_SIGA_SYM_WR_SPARE_U__HE_SIGA_SYM_WR_SPARE_1___S 0 +#define PHYA_TXFD_HE_SIGA_SYM_WR_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXFD_HE_SIGA_SYM_WR_SPARE_U___S 0 + +#define PHYA_TXFD_HE_PARAMS_0_L (0x00391CD0) +#define PHYA_TXFD_HE_PARAMS_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_HE_PARAMS_0_L___POR 0x00000000 +#define PHYA_TXFD_HE_PARAMS_0_L__PACKET_EXTENTION_CONTENT___POR 0x0 +#define PHYA_TXFD_HE_PARAMS_0_L__PACKET_EXTENTION_DURATION___POR 0x0 +#define PHYA_TXFD_HE_PARAMS_0_L__HE_LTF_SIZE___POR 0x0 +#define PHYA_TXFD_HE_PARAMS_0_L__HE_STF_LONG___POR 0x0 +#define PHYA_TXFD_HE_PARAMS_0_L__PACKET_EXTENTION_CONTENT___M 0x01000000 +#define PHYA_TXFD_HE_PARAMS_0_L__PACKET_EXTENTION_CONTENT___S 24 +#define PHYA_TXFD_HE_PARAMS_0_L__PACKET_EXTENTION_DURATION___M 0x00070000 +#define PHYA_TXFD_HE_PARAMS_0_L__PACKET_EXTENTION_DURATION___S 16 +#define PHYA_TXFD_HE_PARAMS_0_L__HE_LTF_SIZE___M 0x00000300 +#define PHYA_TXFD_HE_PARAMS_0_L__HE_LTF_SIZE___S 8 +#define PHYA_TXFD_HE_PARAMS_0_L__HE_STF_LONG___M 0x00000001 +#define PHYA_TXFD_HE_PARAMS_0_L__HE_STF_LONG___S 0 +#define PHYA_TXFD_HE_PARAMS_0_L___M 0x01070301 +#define PHYA_TXFD_HE_PARAMS_0_L___S 0 + +#define PHYA_TXFD_HE_PARAMS_1_L (0x00391CD8) +#define PHYA_TXFD_HE_PARAMS_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_HE_PARAMS_1_L___POR 0x00000000 +#define PHYA_TXFD_HE_PARAMS_1_L__PELTF_SIZE___POR 0x0 +#define PHYA_TXFD_HE_PARAMS_1_L__PE_NSS___POR 0x0 +#define PHYA_TXFD_HE_PARAMS_1_L__FTM_EN___POR 0x0 +#define PHYA_TXFD_HE_PARAMS_1_L__NUM_HE_LTF___POR 0x0 +#define PHYA_TXFD_HE_PARAMS_1_L__PELTF_SIZE___M 0x03000000 +#define PHYA_TXFD_HE_PARAMS_1_L__PELTF_SIZE___S 24 +#define PHYA_TXFD_HE_PARAMS_1_L__PE_NSS___M 0x00070000 +#define PHYA_TXFD_HE_PARAMS_1_L__PE_NSS___S 16 +#define PHYA_TXFD_HE_PARAMS_1_L__FTM_EN___M 0x00000100 +#define PHYA_TXFD_HE_PARAMS_1_L__FTM_EN___S 8 +#define PHYA_TXFD_HE_PARAMS_1_L__NUM_HE_LTF___M 0x0000000F +#define PHYA_TXFD_HE_PARAMS_1_L__NUM_HE_LTF___S 0 +#define PHYA_TXFD_HE_PARAMS_1_L___M 0x0307010F +#define PHYA_TXFD_HE_PARAMS_1_L___S 0 + +#define PHYA_TXFD_HE_PARAMS_1_U (0x00391CDC) +#define PHYA_TXFD_HE_PARAMS_1_U___RWC QCSR_REG_RW +#define PHYA_TXFD_HE_PARAMS_1_U___POR 0x00000000 +#define PHYA_TXFD_HE_PARAMS_1_U__HE_BF_REQUIRED___POR 0x0 +#define PHYA_TXFD_HE_PARAMS_1_U__HE_SEG_PARSE_EN___POR 0x0 +#define PHYA_TXFD_HE_PARAMS_1_U__HE_BF_REQUIRED___M 0x00000100 +#define PHYA_TXFD_HE_PARAMS_1_U__HE_BF_REQUIRED___S 8 +#define PHYA_TXFD_HE_PARAMS_1_U__HE_SEG_PARSE_EN___M 0x00000003 +#define PHYA_TXFD_HE_PARAMS_1_U__HE_SEG_PARSE_EN___S 0 +#define PHYA_TXFD_HE_PARAMS_1_U___M 0x00000103 +#define PHYA_TXFD_HE_PARAMS_1_U___S 0 + +#define PHYA_TXFD_HE_PARAMS_2_L (0x00391CE0) +#define PHYA_TXFD_HE_PARAMS_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_HE_PARAMS_2_L___POR 0x00000000 +#define PHYA_TXFD_HE_PARAMS_2_L__NUM_PE_HE_LTF___POR 0x0 +#define PHYA_TXFD_HE_PARAMS_2_L__NUM_PE_HE_LTF___M 0x0000000F +#define PHYA_TXFD_HE_PARAMS_2_L__NUM_PE_HE_LTF___S 0 +#define PHYA_TXFD_HE_PARAMS_2_L___M 0x0000000F +#define PHYA_TXFD_HE_PARAMS_2_L___S 0 + +#define PHYA_TXFD_POWER_NORM_CFG_L (0x00391CE8) +#define PHYA_TXFD_POWER_NORM_CFG_L___RWC QCSR_REG_RW +#define PHYA_TXFD_POWER_NORM_CFG_L___POR 0x01010001 +#define PHYA_TXFD_POWER_NORM_CFG_L__POWER_NORM_COPY_RU_DATA___POR 0x1 +#define PHYA_TXFD_POWER_NORM_CFG_L__POWER_NORM_COPY_RU_LTF___POR 0x1 +#define PHYA_TXFD_POWER_NORM_CFG_L__POWER_NORM_COPY_RU_STF___POR 0x0 +#define PHYA_TXFD_POWER_NORM_CFG_L__POWER_NORM_COPY_STR___POR 0x1 +#define PHYA_TXFD_POWER_NORM_CFG_L__POWER_NORM_COPY_RU_DATA___M 0x01000000 +#define PHYA_TXFD_POWER_NORM_CFG_L__POWER_NORM_COPY_RU_DATA___S 24 +#define PHYA_TXFD_POWER_NORM_CFG_L__POWER_NORM_COPY_RU_LTF___M 0x00010000 +#define PHYA_TXFD_POWER_NORM_CFG_L__POWER_NORM_COPY_RU_LTF___S 16 +#define PHYA_TXFD_POWER_NORM_CFG_L__POWER_NORM_COPY_RU_STF___M 0x00000100 +#define PHYA_TXFD_POWER_NORM_CFG_L__POWER_NORM_COPY_RU_STF___S 8 +#define PHYA_TXFD_POWER_NORM_CFG_L__POWER_NORM_COPY_STR___M 0x00000001 +#define PHYA_TXFD_POWER_NORM_CFG_L__POWER_NORM_COPY_STR___S 0 +#define PHYA_TXFD_POWER_NORM_CFG_L___M 0x01010101 +#define PHYA_TXFD_POWER_NORM_CFG_L___S 0 + +#define PHYA_TXFD_POWER_NORM_CFG_U (0x00391CEC) +#define PHYA_TXFD_POWER_NORM_CFG_U___RWC QCSR_REG_RW +#define PHYA_TXFD_POWER_NORM_CFG_U___POR 0x00000001 +#define PHYA_TXFD_POWER_NORM_CFG_U__CHAIN_CSD_DELTA_COPY_RU___POR 0x1 +#define PHYA_TXFD_POWER_NORM_CFG_U__CHAIN_CSD_DELTA_COPY_RU___M 0x00000001 +#define PHYA_TXFD_POWER_NORM_CFG_U__CHAIN_CSD_DELTA_COPY_RU___S 0 +#define PHYA_TXFD_POWER_NORM_CFG_U___M 0x00000001 +#define PHYA_TXFD_POWER_NORM_CFG_U___S 0 + +#define PHYA_TXFD_BF_PORTION_START_WR_SPARE_L (0x00391CF0) +#define PHYA_TXFD_BF_PORTION_START_WR_SPARE_L___RWC QCSR_REG_RW +#define PHYA_TXFD_BF_PORTION_START_WR_SPARE_L___POR 0x00000000 +#define PHYA_TXFD_BF_PORTION_START_WR_SPARE_L__BF_PORTION_START_WR_SPARE_0___POR 0x00000000 +#define PHYA_TXFD_BF_PORTION_START_WR_SPARE_L__BF_PORTION_START_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXFD_BF_PORTION_START_WR_SPARE_L__BF_PORTION_START_WR_SPARE_0___S 0 +#define PHYA_TXFD_BF_PORTION_START_WR_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXFD_BF_PORTION_START_WR_SPARE_L___S 0 + +#define PHYA_TXFD_BF_PORTION_START_WR_SPARE_U (0x00391CF4) +#define PHYA_TXFD_BF_PORTION_START_WR_SPARE_U___RWC QCSR_REG_RW +#define PHYA_TXFD_BF_PORTION_START_WR_SPARE_U___POR 0x00000000 +#define PHYA_TXFD_BF_PORTION_START_WR_SPARE_U__BF_PORTION_START_WR_SPARE_1___POR 0x00000000 +#define PHYA_TXFD_BF_PORTION_START_WR_SPARE_U__BF_PORTION_START_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXFD_BF_PORTION_START_WR_SPARE_U__BF_PORTION_START_WR_SPARE_1___S 0 +#define PHYA_TXFD_BF_PORTION_START_WR_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXFD_BF_PORTION_START_WR_SPARE_U___S 0 + +#define PHYA_TXFD_SERVICE_TLV_MEM_L_n(n) (0x00391CF8+0x8*(n)) +#define PHYA_TXFD_SERVICE_TLV_MEM_L_n_nMIN 0 +#define PHYA_TXFD_SERVICE_TLV_MEM_L_n_nMAX 0 +#define PHYA_TXFD_SERVICE_TLV_MEM_L_n_ELEM 1 +#define PHYA_TXFD_SERVICE_TLV_MEM_L_n___RWC QCSR_REG_RW +#define PHYA_TXFD_SERVICE_TLV_MEM_L_n___POR 0x00000000 +#define PHYA_TXFD_SERVICE_TLV_MEM_L_n__SERVICE_TLV_MEM_0___POR 0x00000000 +#define PHYA_TXFD_SERVICE_TLV_MEM_L_n__SERVICE_TLV_MEM_0___M 0xFFFFFFFF +#define PHYA_TXFD_SERVICE_TLV_MEM_L_n__SERVICE_TLV_MEM_0___S 0 +#define PHYA_TXFD_SERVICE_TLV_MEM_L_n___M 0xFFFFFFFF +#define PHYA_TXFD_SERVICE_TLV_MEM_L_n___S 0 +#define PHYA_TXFD_SERVICE_TLV_MEM_L_0 (0x00391CF8) +#define PHYA_TXFD_SERVICE_TLV_MEM_L_0___RWC QCSR_REG_RW +#define PHYA_TXFD_SERVICE_TLV_MEM_L_0__SERVICE_TLV_MEM_0___M 0xFFFFFFFF +#define PHYA_TXFD_SERVICE_TLV_MEM_L_0__SERVICE_TLV_MEM_0___S 0 + +#define PHYA_TXFD_SERVICE_TLV_MEM_U_n(n) (0x00391CFC+0x8*(n)) +#define PHYA_TXFD_SERVICE_TLV_MEM_U_n_nMIN 0 +#define PHYA_TXFD_SERVICE_TLV_MEM_U_n_nMAX 0 +#define PHYA_TXFD_SERVICE_TLV_MEM_U_n_ELEM 1 +#define PHYA_TXFD_SERVICE_TLV_MEM_U_n___RWC QCSR_REG_RW +#define PHYA_TXFD_SERVICE_TLV_MEM_U_n___POR 0x00000000 +#define PHYA_TXFD_SERVICE_TLV_MEM_U_n__SERVICE_TLV_MEM_1___POR 0x00000000 +#define PHYA_TXFD_SERVICE_TLV_MEM_U_n__SERVICE_TLV_MEM_1___M 0xFFFFFFFF +#define PHYA_TXFD_SERVICE_TLV_MEM_U_n__SERVICE_TLV_MEM_1___S 0 +#define PHYA_TXFD_SERVICE_TLV_MEM_U_n___M 0xFFFFFFFF +#define PHYA_TXFD_SERVICE_TLV_MEM_U_n___S 0 +#define PHYA_TXFD_SERVICE_TLV_MEM_U_0 (0x00391CFC) +#define PHYA_TXFD_SERVICE_TLV_MEM_U_0___RWC QCSR_REG_RW +#define PHYA_TXFD_SERVICE_TLV_MEM_U_0__SERVICE_TLV_MEM_1___M 0xFFFFFFFF +#define PHYA_TXFD_SERVICE_TLV_MEM_U_0__SERVICE_TLV_MEM_1___S 0 + +#define PHYA_TXFD_FIRST_DATA_SYM_WR_SPARE_L (0x00391D20) +#define PHYA_TXFD_FIRST_DATA_SYM_WR_SPARE_L___RWC QCSR_REG_RW +#define PHYA_TXFD_FIRST_DATA_SYM_WR_SPARE_L___POR 0x00000000 +#define PHYA_TXFD_FIRST_DATA_SYM_WR_SPARE_L__FIRST_DATA_SYM_WR_SPARE_0___POR 0x00000000 +#define PHYA_TXFD_FIRST_DATA_SYM_WR_SPARE_L__FIRST_DATA_SYM_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXFD_FIRST_DATA_SYM_WR_SPARE_L__FIRST_DATA_SYM_WR_SPARE_0___S 0 +#define PHYA_TXFD_FIRST_DATA_SYM_WR_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXFD_FIRST_DATA_SYM_WR_SPARE_L___S 0 + +#define PHYA_TXFD_FIRST_DATA_SYM_WR_SPARE_U (0x00391D24) +#define PHYA_TXFD_FIRST_DATA_SYM_WR_SPARE_U___RWC QCSR_REG_RW +#define PHYA_TXFD_FIRST_DATA_SYM_WR_SPARE_U___POR 0x00000000 +#define PHYA_TXFD_FIRST_DATA_SYM_WR_SPARE_U__FIRST_DATA_SYM_WR_SPARE_1___POR 0x00000000 +#define PHYA_TXFD_FIRST_DATA_SYM_WR_SPARE_U__FIRST_DATA_SYM_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXFD_FIRST_DATA_SYM_WR_SPARE_U__FIRST_DATA_SYM_WR_SPARE_1___S 0 +#define PHYA_TXFD_FIRST_DATA_SYM_WR_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXFD_FIRST_DATA_SYM_WR_SPARE_U___S 0 + +#define PHYA_TXFD_USER_PARAMS_L_n(n) (0x00391D28+0x8*(n)) +#define PHYA_TXFD_USER_PARAMS_L_n_nMIN 0 +#define PHYA_TXFD_USER_PARAMS_L_n_nMAX 0 +#define PHYA_TXFD_USER_PARAMS_L_n_ELEM 1 +#define PHYA_TXFD_USER_PARAMS_L_n___RWC QCSR_REG_RW +#define PHYA_TXFD_USER_PARAMS_L_n___POR 0x00000000 +#define PHYA_TXFD_USER_PARAMS_L_n__USER_PARAMS_0___POR 0x00000000 +#define PHYA_TXFD_USER_PARAMS_L_n__USER_PARAMS_0___M 0xFFFFFFFF +#define PHYA_TXFD_USER_PARAMS_L_n__USER_PARAMS_0___S 0 +#define PHYA_TXFD_USER_PARAMS_L_n___M 0xFFFFFFFF +#define PHYA_TXFD_USER_PARAMS_L_n___S 0 +#define PHYA_TXFD_USER_PARAMS_L_0 (0x00391D28) +#define PHYA_TXFD_USER_PARAMS_L_0___RWC QCSR_REG_RW +#define PHYA_TXFD_USER_PARAMS_L_0__USER_PARAMS_0___M 0xFFFFFFFF +#define PHYA_TXFD_USER_PARAMS_L_0__USER_PARAMS_0___S 0 + +#define PHYA_TXFD_USER_PARAMS_U_n(n) (0x00391D2C+0x8*(n)) +#define PHYA_TXFD_USER_PARAMS_U_n_nMIN 0 +#define PHYA_TXFD_USER_PARAMS_U_n_nMAX 0 +#define PHYA_TXFD_USER_PARAMS_U_n_ELEM 1 +#define PHYA_TXFD_USER_PARAMS_U_n___RWC QCSR_REG_RW +#define PHYA_TXFD_USER_PARAMS_U_n___POR 0x00000000 +#define PHYA_TXFD_USER_PARAMS_U_n__USER_PARAMS_1___POR 0x00000000 +#define PHYA_TXFD_USER_PARAMS_U_n__USER_PARAMS_1___M 0xFFFFFFFF +#define PHYA_TXFD_USER_PARAMS_U_n__USER_PARAMS_1___S 0 +#define PHYA_TXFD_USER_PARAMS_U_n___M 0xFFFFFFFF +#define PHYA_TXFD_USER_PARAMS_U_n___S 0 +#define PHYA_TXFD_USER_PARAMS_U_0 (0x00391D2C) +#define PHYA_TXFD_USER_PARAMS_U_0___RWC QCSR_REG_RW +#define PHYA_TXFD_USER_PARAMS_U_0__USER_PARAMS_1___M 0xFFFFFFFF +#define PHYA_TXFD_USER_PARAMS_U_0__USER_PARAMS_1___S 0 + +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_L (0x00392128) +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_L__NUM_ACTIVE_LTF_TONES_SEG0___POR 0x000 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_L__NUM_ACTIVE_STF_TONES_SEG0___POR 0x000 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_L__NUM_ACTIVE_LTF_TONES_SEG0___M 0x03FF0000 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_L__NUM_ACTIVE_LTF_TONES_SEG0___S 16 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_L__NUM_ACTIVE_STF_TONES_SEG0___M 0x000003FF +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_L__NUM_ACTIVE_STF_TONES_SEG0___S 0 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_L___M 0x03FF03FF +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_U (0x0039212C) +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_U___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_U___POR 0x00000000 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_U__NUM_ACTIVE_STF_TONES_SEG1___POR 0x000 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_U__NUM_ACTIVE_DATA_TONES_SEG0___POR 0x000 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_U__NUM_ACTIVE_STF_TONES_SEG1___M 0x03FF0000 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_U__NUM_ACTIVE_STF_TONES_SEG1___S 16 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_U__NUM_ACTIVE_DATA_TONES_SEG0___M 0x000003FF +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_U__NUM_ACTIVE_DATA_TONES_SEG0___S 0 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_U___M 0x03FF03FF +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_0_U___S 0 + +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_L (0x00392130) +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_L__NUM_ACTIVE_DATA_TONES_SEG1___POR 0x000 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_L__NUM_ACTIVE_LTF_TONES_SEG1___POR 0x000 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_L__NUM_ACTIVE_DATA_TONES_SEG1___M 0x03FF0000 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_L__NUM_ACTIVE_DATA_TONES_SEG1___S 16 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_L__NUM_ACTIVE_LTF_TONES_SEG1___M 0x000003FF +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_L__NUM_ACTIVE_LTF_TONES_SEG1___S 0 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_L___M 0x03FF03FF +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_U (0x00392134) +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_U___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_U___POR 0x00000000 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_U__NON_DASH_BAND0___POR 0x00 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_U__NUM_RUS_SEG1___POR 0x00 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_U__NUM_RUS_SEG0___POR 0x00 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_U__NUM_RUS___POR 0x00 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_U__NON_DASH_BAND0___M 0xFF000000 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_U__NON_DASH_BAND0___S 24 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_U__NUM_RUS_SEG1___M 0x00FF0000 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_U__NUM_RUS_SEG1___S 16 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_U__NUM_RUS_SEG0___M 0x0000FF00 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_U__NUM_RUS_SEG0___S 8 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_U__NUM_RUS___M 0x000000FF +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_U__NUM_RUS___S 0 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_U___M 0xFFFFFFFF +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_1_U___S 0 + +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_2_L (0x00392138) +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_2_L__CURR_RU_ALLOC_SPARE___POR 0x00 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_2_L__NON_DASH_BAND1___POR 0x00 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_2_L__CURR_RU_ALLOC_SPARE___M 0x0000FF00 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_2_L__CURR_RU_ALLOC_SPARE___S 8 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_2_L__NON_DASH_BAND1___M 0x000000FF +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_2_L__NON_DASH_BAND1___S 0 +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_2_L___M 0x0000FFFF +#define PHYA_TXFD_RU_CURR_RU_ALLOC_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_0_L (0x00392140) +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_0_L__RU0_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_0_L__RU0_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_0_L__RU0_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_0_L__RU0_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_0_L__RU0_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_0_L__RU0_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_0_L__RU0_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_0_L__RU0_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_0_L__RU0_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_1_L (0x00392148) +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_1_L__RU0_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_1_L__RU0_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_1_L__RU0_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_1_L__RU0_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_1_L__RU0_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_1_L__RU0_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_2_L (0x00392150) +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_2_L__RU0_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_2_L__RU0_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_2_L__RU0_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_2_L__RU0_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_2_L__RU0_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_2_L__RU0_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU0_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_0_L (0x00392158) +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_0_L__RU1_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_0_L__RU1_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_0_L__RU1_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_0_L__RU1_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_0_L__RU1_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_0_L__RU1_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_0_L__RU1_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_0_L__RU1_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_0_L__RU1_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_1_L (0x00392160) +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_1_L__RU1_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_1_L__RU1_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_1_L__RU1_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_1_L__RU1_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_1_L__RU1_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_1_L__RU1_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_2_L (0x00392168) +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_2_L__RU1_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_2_L__RU1_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_2_L__RU1_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_2_L__RU1_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_2_L__RU1_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_2_L__RU1_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU1_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_0_L (0x00392170) +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_0_L__RU2_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_0_L__RU2_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_0_L__RU2_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_0_L__RU2_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_0_L__RU2_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_0_L__RU2_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_0_L__RU2_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_0_L__RU2_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_0_L__RU2_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_1_L (0x00392178) +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_1_L__RU2_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_1_L__RU2_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_1_L__RU2_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_1_L__RU2_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_1_L__RU2_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_1_L__RU2_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_2_L (0x00392180) +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_2_L__RU2_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_2_L__RU2_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_2_L__RU2_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_2_L__RU2_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_2_L__RU2_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_2_L__RU2_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU2_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_0_L (0x00392188) +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_0_L__RU3_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_0_L__RU3_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_0_L__RU3_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_0_L__RU3_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_0_L__RU3_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_0_L__RU3_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_0_L__RU3_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_0_L__RU3_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_0_L__RU3_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_1_L (0x00392190) +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_1_L__RU3_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_1_L__RU3_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_1_L__RU3_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_1_L__RU3_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_1_L__RU3_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_1_L__RU3_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_2_L (0x00392198) +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_2_L__RU3_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_2_L__RU3_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_2_L__RU3_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_2_L__RU3_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_2_L__RU3_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_2_L__RU3_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU3_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_0_L (0x003921A0) +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_0_L__RU4_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_0_L__RU4_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_0_L__RU4_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_0_L__RU4_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_0_L__RU4_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_0_L__RU4_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_0_L__RU4_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_0_L__RU4_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_0_L__RU4_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_1_L (0x003921A8) +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_1_L__RU4_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_1_L__RU4_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_1_L__RU4_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_1_L__RU4_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_1_L__RU4_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_1_L__RU4_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_2_L (0x003921B0) +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_2_L__RU4_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_2_L__RU4_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_2_L__RU4_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_2_L__RU4_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_2_L__RU4_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_2_L__RU4_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU4_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_0_L (0x003921B8) +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_0_L__RU5_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_0_L__RU5_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_0_L__RU5_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_0_L__RU5_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_0_L__RU5_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_0_L__RU5_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_0_L__RU5_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_0_L__RU5_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_0_L__RU5_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_1_L (0x003921C0) +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_1_L__RU5_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_1_L__RU5_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_1_L__RU5_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_1_L__RU5_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_1_L__RU5_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_1_L__RU5_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_2_L (0x003921C8) +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_2_L__RU5_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_2_L__RU5_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_2_L__RU5_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_2_L__RU5_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_2_L__RU5_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_2_L__RU5_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU5_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_0_L (0x003921D0) +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_0_L__RU6_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_0_L__RU6_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_0_L__RU6_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_0_L__RU6_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_0_L__RU6_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_0_L__RU6_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_0_L__RU6_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_0_L__RU6_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_0_L__RU6_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_1_L (0x003921D8) +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_1_L__RU6_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_1_L__RU6_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_1_L__RU6_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_1_L__RU6_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_1_L__RU6_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_1_L__RU6_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_2_L (0x003921E0) +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_2_L__RU6_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_2_L__RU6_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_2_L__RU6_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_2_L__RU6_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_2_L__RU6_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_2_L__RU6_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU6_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_0_L (0x003921E8) +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_0_L__RU7_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_0_L__RU7_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_0_L__RU7_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_0_L__RU7_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_0_L__RU7_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_0_L__RU7_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_0_L__RU7_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_0_L__RU7_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_0_L__RU7_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_1_L (0x003921F0) +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_1_L__RU7_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_1_L__RU7_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_1_L__RU7_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_1_L__RU7_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_1_L__RU7_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_1_L__RU7_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_2_L (0x003921F8) +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_2_L__RU7_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_2_L__RU7_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_2_L__RU7_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_2_L__RU7_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_2_L__RU7_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_2_L__RU7_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU7_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_0_L (0x00392200) +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_0_L__RU8_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_0_L__RU8_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_0_L__RU8_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_0_L__RU8_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_0_L__RU8_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_0_L__RU8_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_0_L__RU8_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_0_L__RU8_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_0_L__RU8_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_1_L (0x00392208) +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_1_L__RU8_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_1_L__RU8_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_1_L__RU8_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_1_L__RU8_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_1_L__RU8_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_1_L__RU8_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_2_L (0x00392210) +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_2_L__RU8_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_2_L__RU8_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_2_L__RU8_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_2_L__RU8_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_2_L__RU8_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_2_L__RU8_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU8_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_0_L (0x00392218) +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_0_L__RU9_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_0_L__RU9_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_0_L__RU9_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_0_L__RU9_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_0_L__RU9_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_0_L__RU9_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_0_L__RU9_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_0_L__RU9_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_0_L__RU9_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_1_L (0x00392220) +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_1_L__RU9_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_1_L__RU9_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_1_L__RU9_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_1_L__RU9_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_1_L__RU9_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_1_L__RU9_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_2_L (0x00392228) +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_2_L__RU9_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_2_L__RU9_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_2_L__RU9_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_2_L__RU9_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_2_L__RU9_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_2_L__RU9_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU9_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_0_L (0x00392230) +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_0_L__RU10_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_0_L__RU10_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_0_L__RU10_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_0_L__RU10_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_0_L__RU10_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_0_L__RU10_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_0_L__RU10_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_0_L__RU10_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_0_L__RU10_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_1_L (0x00392238) +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_1_L__RU10_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_1_L__RU10_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_1_L__RU10_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_1_L__RU10_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_1_L__RU10_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_1_L__RU10_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_2_L (0x00392240) +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_2_L__RU10_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_2_L__RU10_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_2_L__RU10_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_2_L__RU10_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_2_L__RU10_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_2_L__RU10_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU10_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_0_L (0x00392248) +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_0_L__RU11_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_0_L__RU11_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_0_L__RU11_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_0_L__RU11_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_0_L__RU11_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_0_L__RU11_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_0_L__RU11_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_0_L__RU11_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_0_L__RU11_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_1_L (0x00392250) +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_1_L__RU11_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_1_L__RU11_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_1_L__RU11_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_1_L__RU11_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_1_L__RU11_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_1_L__RU11_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_2_L (0x00392258) +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_2_L__RU11_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_2_L__RU11_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_2_L__RU11_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_2_L__RU11_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_2_L__RU11_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_2_L__RU11_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU11_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_0_L (0x00392260) +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_0_L__RU12_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_0_L__RU12_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_0_L__RU12_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_0_L__RU12_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_0_L__RU12_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_0_L__RU12_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_0_L__RU12_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_0_L__RU12_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_0_L__RU12_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_1_L (0x00392268) +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_1_L__RU12_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_1_L__RU12_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_1_L__RU12_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_1_L__RU12_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_1_L__RU12_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_1_L__RU12_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_2_L (0x00392270) +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_2_L__RU12_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_2_L__RU12_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_2_L__RU12_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_2_L__RU12_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_2_L__RU12_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_2_L__RU12_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU12_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_0_L (0x00392278) +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_0_L__RU13_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_0_L__RU13_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_0_L__RU13_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_0_L__RU13_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_0_L__RU13_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_0_L__RU13_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_0_L__RU13_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_0_L__RU13_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_0_L__RU13_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_1_L (0x00392280) +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_1_L__RU13_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_1_L__RU13_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_1_L__RU13_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_1_L__RU13_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_1_L__RU13_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_1_L__RU13_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_2_L (0x00392288) +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_2_L__RU13_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_2_L__RU13_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_2_L__RU13_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_2_L__RU13_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_2_L__RU13_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_2_L__RU13_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU13_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_0_L (0x00392290) +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_0_L__RU14_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_0_L__RU14_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_0_L__RU14_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_0_L__RU14_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_0_L__RU14_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_0_L__RU14_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_0_L__RU14_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_0_L__RU14_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_0_L__RU14_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_1_L (0x00392298) +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_1_L__RU14_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_1_L__RU14_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_1_L__RU14_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_1_L__RU14_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_1_L__RU14_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_1_L__RU14_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_2_L (0x003922A0) +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_2_L__RU14_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_2_L__RU14_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_2_L__RU14_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_2_L__RU14_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_2_L__RU14_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_2_L__RU14_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU14_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_0_L (0x003922A8) +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_0_L__RU15_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_0_L__RU15_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_0_L__RU15_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_0_L__RU15_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_0_L__RU15_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_0_L__RU15_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_0_L__RU15_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_0_L__RU15_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_0_L__RU15_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_1_L (0x003922B0) +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_1_L__RU15_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_1_L__RU15_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_1_L__RU15_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_1_L__RU15_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_1_L__RU15_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_1_L__RU15_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_2_L (0x003922B8) +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_2_L__RU15_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_2_L__RU15_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_2_L__RU15_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_2_L__RU15_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_2_L__RU15_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_2_L__RU15_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU15_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_0_L (0x003922C0) +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_0_L__RU16_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_0_L__RU16_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_0_L__RU16_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_0_L__RU16_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_0_L__RU16_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_0_L__RU16_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_0_L__RU16_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_0_L__RU16_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_0_L__RU16_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_1_L (0x003922C8) +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_1_L__RU16_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_1_L__RU16_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_1_L__RU16_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_1_L__RU16_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_1_L__RU16_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_1_L__RU16_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_2_L (0x003922D0) +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_2_L__RU16_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_2_L__RU16_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_2_L__RU16_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_2_L__RU16_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_2_L__RU16_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_2_L__RU16_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU16_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_0_L (0x003922D8) +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_0_L__RU17_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_0_L__RU17_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_0_L__RU17_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_0_L__RU17_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_0_L__RU17_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_0_L__RU17_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_0_L__RU17_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_0_L__RU17_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_0_L__RU17_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_1_L (0x003922E0) +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_1_L__RU17_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_1_L__RU17_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_1_L__RU17_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_1_L__RU17_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_1_L__RU17_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_1_L__RU17_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_2_L (0x003922E8) +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_2_L__RU17_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_2_L__RU17_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_2_L__RU17_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_2_L__RU17_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_2_L__RU17_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_2_L__RU17_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU17_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_0_L (0x003922F0) +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_0_L__RU18_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_0_L__RU18_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_0_L__RU18_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_0_L__RU18_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_0_L__RU18_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_0_L__RU18_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_0_L__RU18_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_0_L__RU18_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_0_L__RU18_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_1_L (0x003922F8) +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_1_L__RU18_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_1_L__RU18_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_1_L__RU18_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_1_L__RU18_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_1_L__RU18_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_1_L__RU18_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_2_L (0x00392300) +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_2_L__RU18_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_2_L__RU18_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_2_L__RU18_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_2_L__RU18_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_2_L__RU18_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_2_L__RU18_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU18_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_0_L (0x00392308) +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_0_L__RU19_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_0_L__RU19_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_0_L__RU19_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_0_L__RU19_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_0_L__RU19_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_0_L__RU19_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_0_L__RU19_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_0_L__RU19_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_0_L__RU19_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_1_L (0x00392310) +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_1_L__RU19_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_1_L__RU19_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_1_L__RU19_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_1_L__RU19_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_1_L__RU19_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_1_L__RU19_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_2_L (0x00392318) +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_2_L__RU19_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_2_L__RU19_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_2_L__RU19_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_2_L__RU19_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_2_L__RU19_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_2_L__RU19_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU19_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_0_L (0x00392320) +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_0_L__RU20_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_0_L__RU20_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_0_L__RU20_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_0_L__RU20_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_0_L__RU20_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_0_L__RU20_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_0_L__RU20_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_0_L__RU20_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_0_L__RU20_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_1_L (0x00392328) +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_1_L__RU20_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_1_L__RU20_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_1_L__RU20_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_1_L__RU20_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_1_L__RU20_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_1_L__RU20_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_2_L (0x00392330) +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_2_L__RU20_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_2_L__RU20_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_2_L__RU20_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_2_L__RU20_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_2_L__RU20_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_2_L__RU20_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU20_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_0_L (0x00392338) +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_0_L__RU21_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_0_L__RU21_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_0_L__RU21_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_0_L__RU21_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_0_L__RU21_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_0_L__RU21_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_0_L__RU21_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_0_L__RU21_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_0_L__RU21_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_1_L (0x00392340) +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_1_L__RU21_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_1_L__RU21_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_1_L__RU21_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_1_L__RU21_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_1_L__RU21_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_1_L__RU21_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_2_L (0x00392348) +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_2_L__RU21_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_2_L__RU21_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_2_L__RU21_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_2_L__RU21_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_2_L__RU21_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_2_L__RU21_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU21_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_0_L (0x00392350) +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_0_L__RU22_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_0_L__RU22_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_0_L__RU22_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_0_L__RU22_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_0_L__RU22_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_0_L__RU22_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_0_L__RU22_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_0_L__RU22_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_0_L__RU22_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_1_L (0x00392358) +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_1_L__RU22_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_1_L__RU22_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_1_L__RU22_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_1_L__RU22_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_1_L__RU22_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_1_L__RU22_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_2_L (0x00392360) +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_2_L__RU22_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_2_L__RU22_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_2_L__RU22_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_2_L__RU22_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_2_L__RU22_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_2_L__RU22_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU22_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_0_L (0x00392368) +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_0_L__RU23_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_0_L__RU23_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_0_L__RU23_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_0_L__RU23_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_0_L__RU23_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_0_L__RU23_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_0_L__RU23_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_0_L__RU23_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_0_L__RU23_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_1_L (0x00392370) +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_1_L__RU23_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_1_L__RU23_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_1_L__RU23_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_1_L__RU23_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_1_L__RU23_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_1_L__RU23_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_2_L (0x00392378) +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_2_L__RU23_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_2_L__RU23_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_2_L__RU23_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_2_L__RU23_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_2_L__RU23_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_2_L__RU23_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU23_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_0_L (0x00392380) +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_0_L__RU24_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_0_L__RU24_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_0_L__RU24_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_0_L__RU24_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_0_L__RU24_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_0_L__RU24_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_0_L__RU24_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_0_L__RU24_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_0_L__RU24_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_1_L (0x00392388) +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_1_L__RU24_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_1_L__RU24_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_1_L__RU24_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_1_L__RU24_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_1_L__RU24_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_1_L__RU24_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_2_L (0x00392390) +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_2_L__RU24_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_2_L__RU24_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_2_L__RU24_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_2_L__RU24_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_2_L__RU24_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_2_L__RU24_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU24_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_0_L (0x00392398) +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_0_L__RU25_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_0_L__RU25_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_0_L__RU25_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_0_L__RU25_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_0_L__RU25_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_0_L__RU25_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_0_L__RU25_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_0_L__RU25_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_0_L__RU25_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_1_L (0x003923A0) +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_1_L__RU25_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_1_L__RU25_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_1_L__RU25_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_1_L__RU25_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_1_L__RU25_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_1_L__RU25_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_2_L (0x003923A8) +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_2_L__RU25_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_2_L__RU25_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_2_L__RU25_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_2_L__RU25_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_2_L__RU25_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_2_L__RU25_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU25_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_0_L (0x003923B0) +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_0_L__RU26_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_0_L__RU26_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_0_L__RU26_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_0_L__RU26_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_0_L__RU26_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_0_L__RU26_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_0_L__RU26_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_0_L__RU26_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_0_L__RU26_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_1_L (0x003923B8) +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_1_L__RU26_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_1_L__RU26_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_1_L__RU26_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_1_L__RU26_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_1_L__RU26_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_1_L__RU26_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_2_L (0x003923C0) +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_2_L__RU26_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_2_L__RU26_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_2_L__RU26_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_2_L__RU26_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_2_L__RU26_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_2_L__RU26_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU26_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_0_L (0x003923C8) +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_0_L__RU27_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_0_L__RU27_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_0_L__RU27_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_0_L__RU27_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_0_L__RU27_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_0_L__RU27_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_0_L__RU27_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_0_L__RU27_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_0_L__RU27_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_1_L (0x003923D0) +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_1_L__RU27_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_1_L__RU27_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_1_L__RU27_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_1_L__RU27_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_1_L__RU27_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_1_L__RU27_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_2_L (0x003923D8) +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_2_L__RU27_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_2_L__RU27_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_2_L__RU27_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_2_L__RU27_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_2_L__RU27_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_2_L__RU27_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU27_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_0_L (0x003923E0) +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_0_L__RU28_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_0_L__RU28_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_0_L__RU28_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_0_L__RU28_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_0_L__RU28_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_0_L__RU28_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_0_L__RU28_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_0_L__RU28_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_0_L__RU28_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_1_L (0x003923E8) +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_1_L__RU28_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_1_L__RU28_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_1_L__RU28_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_1_L__RU28_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_1_L__RU28_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_1_L__RU28_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_2_L (0x003923F0) +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_2_L__RU28_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_2_L__RU28_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_2_L__RU28_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_2_L__RU28_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_2_L__RU28_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_2_L__RU28_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU28_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_0_L (0x003923F8) +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_0_L__RU29_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_0_L__RU29_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_0_L__RU29_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_0_L__RU29_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_0_L__RU29_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_0_L__RU29_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_0_L__RU29_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_0_L__RU29_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_0_L__RU29_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_1_L (0x00392400) +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_1_L__RU29_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_1_L__RU29_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_1_L__RU29_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_1_L__RU29_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_1_L__RU29_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_1_L__RU29_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_2_L (0x00392408) +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_2_L__RU29_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_2_L__RU29_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_2_L__RU29_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_2_L__RU29_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_2_L__RU29_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_2_L__RU29_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU29_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_0_L (0x00392410) +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_0_L__RU30_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_0_L__RU30_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_0_L__RU30_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_0_L__RU30_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_0_L__RU30_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_0_L__RU30_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_0_L__RU30_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_0_L__RU30_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_0_L__RU30_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_1_L (0x00392418) +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_1_L__RU30_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_1_L__RU30_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_1_L__RU30_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_1_L__RU30_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_1_L__RU30_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_1_L__RU30_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_2_L (0x00392420) +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_2_L__RU30_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_2_L__RU30_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_2_L__RU30_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_2_L__RU30_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_2_L__RU30_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_2_L__RU30_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU30_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_0_L (0x00392428) +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_0_L__RU31_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_0_L__RU31_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_0_L__RU31_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_0_L__RU31_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_0_L__RU31_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_0_L__RU31_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_0_L__RU31_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_0_L__RU31_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_0_L__RU31_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_1_L (0x00392430) +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_1_L__RU31_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_1_L__RU31_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_1_L__RU31_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_1_L__RU31_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_1_L__RU31_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_1_L__RU31_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_2_L (0x00392438) +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_2_L__RU31_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_2_L__RU31_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_2_L__RU31_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_2_L__RU31_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_2_L__RU31_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_2_L__RU31_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU31_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_0_L (0x00392440) +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_0_L__RU32_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_0_L__RU32_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_0_L__RU32_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_0_L__RU32_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_0_L__RU32_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_0_L__RU32_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_0_L__RU32_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_0_L__RU32_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_0_L__RU32_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_1_L (0x00392448) +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_1_L__RU32_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_1_L__RU32_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_1_L__RU32_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_1_L__RU32_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_1_L__RU32_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_1_L__RU32_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_2_L (0x00392450) +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_2_L__RU32_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_2_L__RU32_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_2_L__RU32_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_2_L__RU32_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_2_L__RU32_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_2_L__RU32_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU32_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_0_L (0x00392458) +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_0_L__RU33_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_0_L__RU33_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_0_L__RU33_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_0_L__RU33_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_0_L__RU33_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_0_L__RU33_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_0_L__RU33_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_0_L__RU33_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_0_L__RU33_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_1_L (0x00392460) +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_1_L__RU33_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_1_L__RU33_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_1_L__RU33_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_1_L__RU33_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_1_L__RU33_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_1_L__RU33_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_2_L (0x00392468) +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_2_L__RU33_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_2_L__RU33_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_2_L__RU33_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_2_L__RU33_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_2_L__RU33_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_2_L__RU33_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU33_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_0_L (0x00392470) +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_0_L__RU34_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_0_L__RU34_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_0_L__RU34_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_0_L__RU34_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_0_L__RU34_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_0_L__RU34_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_0_L__RU34_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_0_L__RU34_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_0_L__RU34_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_1_L (0x00392478) +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_1_L__RU34_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_1_L__RU34_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_1_L__RU34_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_1_L__RU34_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_1_L__RU34_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_1_L__RU34_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_2_L (0x00392480) +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_2_L__RU34_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_2_L__RU34_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_2_L__RU34_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_2_L__RU34_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_2_L__RU34_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_2_L__RU34_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU34_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_0_L (0x00392488) +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_0_L__RU35_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_0_L__RU35_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_0_L__RU35_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_0_L__RU35_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_0_L__RU35_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_0_L__RU35_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_0_L__RU35_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_0_L__RU35_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_0_L__RU35_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_1_L (0x00392490) +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_1_L__RU35_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_1_L__RU35_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_1_L__RU35_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_1_L__RU35_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_1_L__RU35_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_1_L__RU35_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_2_L (0x00392498) +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_2_L__RU35_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_2_L__RU35_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_2_L__RU35_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_2_L__RU35_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_2_L__RU35_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_2_L__RU35_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU35_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_0_L (0x003924A0) +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_0_L__RU36_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_0_L__RU36_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_0_L__RU36_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_0_L__RU36_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_0_L__RU36_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_0_L__RU36_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_0_L__RU36_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_0_L__RU36_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_0_L__RU36_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_1_L (0x003924A8) +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_1_L__RU36_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_1_L__RU36_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_1_L__RU36_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_1_L__RU36_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_1_L__RU36_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_1_L__RU36_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_2_L (0x003924B0) +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_2_L__RU36_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_2_L__RU36_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_2_L__RU36_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_2_L__RU36_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_2_L__RU36_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_2_L__RU36_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU36_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_0_L (0x003924B8) +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_0_L__RU37_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_0_L__RU37_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_0_L__RU37_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_0_L__RU37_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_0_L__RU37_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_0_L__RU37_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_0_L__RU37_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_0_L__RU37_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_0_L__RU37_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_1_L (0x003924C0) +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_1_L__RU37_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_1_L__RU37_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_1_L__RU37_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_1_L__RU37_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_1_L__RU37_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_1_L__RU37_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_2_L (0x003924C8) +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_2_L__RU37_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_2_L__RU37_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_2_L__RU37_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_2_L__RU37_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_2_L__RU37_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_2_L__RU37_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU37_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_0_L (0x003924D0) +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_0_L__RU38_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_0_L__RU38_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_0_L__RU38_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_0_L__RU38_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_0_L__RU38_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_0_L__RU38_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_0_L__RU38_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_0_L__RU38_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_0_L__RU38_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_1_L (0x003924D8) +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_1_L__RU38_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_1_L__RU38_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_1_L__RU38_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_1_L__RU38_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_1_L__RU38_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_1_L__RU38_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_2_L (0x003924E0) +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_2_L__RU38_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_2_L__RU38_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_2_L__RU38_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_2_L__RU38_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_2_L__RU38_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_2_L__RU38_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU38_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_0_L (0x003924E8) +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_0_L__RU39_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_0_L__RU39_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_0_L__RU39_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_0_L__RU39_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_0_L__RU39_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_0_L__RU39_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_0_L__RU39_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_0_L__RU39_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_0_L__RU39_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_1_L (0x003924F0) +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_1_L__RU39_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_1_L__RU39_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_1_L__RU39_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_1_L__RU39_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_1_L__RU39_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_1_L__RU39_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_2_L (0x003924F8) +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_2_L__RU39_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_2_L__RU39_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_2_L__RU39_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_2_L__RU39_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_2_L__RU39_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_2_L__RU39_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU39_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_0_L (0x00392500) +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_0_L__RU40_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_0_L__RU40_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_0_L__RU40_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_0_L__RU40_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_0_L__RU40_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_0_L__RU40_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_0_L__RU40_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_0_L__RU40_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_0_L__RU40_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_1_L (0x00392508) +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_1_L__RU40_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_1_L__RU40_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_1_L__RU40_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_1_L__RU40_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_1_L__RU40_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_1_L__RU40_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_2_L (0x00392510) +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_2_L__RU40_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_2_L__RU40_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_2_L__RU40_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_2_L__RU40_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_2_L__RU40_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_2_L__RU40_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU40_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_0_L (0x00392518) +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_0_L__RU41_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_0_L__RU41_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_0_L__RU41_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_0_L__RU41_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_0_L__RU41_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_0_L__RU41_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_0_L__RU41_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_0_L__RU41_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_0_L__RU41_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_1_L (0x00392520) +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_1_L__RU41_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_1_L__RU41_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_1_L__RU41_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_1_L__RU41_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_1_L__RU41_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_1_L__RU41_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_2_L (0x00392528) +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_2_L__RU41_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_2_L__RU41_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_2_L__RU41_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_2_L__RU41_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_2_L__RU41_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_2_L__RU41_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU41_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_0_L (0x00392530) +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_0_L__RU42_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_0_L__RU42_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_0_L__RU42_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_0_L__RU42_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_0_L__RU42_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_0_L__RU42_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_0_L__RU42_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_0_L__RU42_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_0_L__RU42_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_1_L (0x00392538) +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_1_L__RU42_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_1_L__RU42_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_1_L__RU42_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_1_L__RU42_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_1_L__RU42_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_1_L__RU42_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_2_L (0x00392540) +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_2_L__RU42_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_2_L__RU42_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_2_L__RU42_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_2_L__RU42_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_2_L__RU42_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_2_L__RU42_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU42_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_0_L (0x00392548) +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_0_L__RU43_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_0_L__RU43_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_0_L__RU43_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_0_L__RU43_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_0_L__RU43_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_0_L__RU43_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_0_L__RU43_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_0_L__RU43_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_0_L__RU43_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_1_L (0x00392550) +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_1_L__RU43_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_1_L__RU43_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_1_L__RU43_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_1_L__RU43_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_1_L__RU43_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_1_L__RU43_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_2_L (0x00392558) +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_2_L__RU43_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_2_L__RU43_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_2_L__RU43_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_2_L__RU43_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_2_L__RU43_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_2_L__RU43_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU43_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_0_L (0x00392560) +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_0_L__RU44_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_0_L__RU44_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_0_L__RU44_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_0_L__RU44_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_0_L__RU44_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_0_L__RU44_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_0_L__RU44_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_0_L__RU44_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_0_L__RU44_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_1_L (0x00392568) +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_1_L__RU44_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_1_L__RU44_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_1_L__RU44_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_1_L__RU44_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_1_L__RU44_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_1_L__RU44_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_2_L (0x00392570) +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_2_L__RU44_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_2_L__RU44_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_2_L__RU44_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_2_L__RU44_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_2_L__RU44_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_2_L__RU44_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU44_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_0_L (0x00392578) +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_0_L__RU45_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_0_L__RU45_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_0_L__RU45_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_0_L__RU45_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_0_L__RU45_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_0_L__RU45_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_0_L__RU45_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_0_L__RU45_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_0_L__RU45_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_1_L (0x00392580) +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_1_L__RU45_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_1_L__RU45_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_1_L__RU45_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_1_L__RU45_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_1_L__RU45_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_1_L__RU45_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_2_L (0x00392588) +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_2_L__RU45_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_2_L__RU45_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_2_L__RU45_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_2_L__RU45_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_2_L__RU45_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_2_L__RU45_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU45_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_0_L (0x00392590) +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_0_L__RU46_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_0_L__RU46_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_0_L__RU46_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_0_L__RU46_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_0_L__RU46_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_0_L__RU46_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_0_L__RU46_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_0_L__RU46_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_0_L__RU46_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_1_L (0x00392598) +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_1_L__RU46_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_1_L__RU46_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_1_L__RU46_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_1_L__RU46_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_1_L__RU46_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_1_L__RU46_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_2_L (0x003925A0) +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_2_L__RU46_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_2_L__RU46_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_2_L__RU46_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_2_L__RU46_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_2_L__RU46_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_2_L__RU46_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU46_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_0_L (0x003925A8) +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_0_L__RU47_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_0_L__RU47_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_0_L__RU47_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_0_L__RU47_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_0_L__RU47_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_0_L__RU47_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_0_L__RU47_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_0_L__RU47_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_0_L__RU47_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_1_L (0x003925B0) +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_1_L__RU47_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_1_L__RU47_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_1_L__RU47_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_1_L__RU47_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_1_L__RU47_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_1_L__RU47_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_2_L (0x003925B8) +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_2_L__RU47_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_2_L__RU47_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_2_L__RU47_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_2_L__RU47_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_2_L__RU47_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_2_L__RU47_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU47_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_0_L (0x003925C0) +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_0_L__RU48_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_0_L__RU48_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_0_L__RU48_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_0_L__RU48_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_0_L__RU48_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_0_L__RU48_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_0_L__RU48_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_0_L__RU48_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_0_L__RU48_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_1_L (0x003925C8) +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_1_L__RU48_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_1_L__RU48_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_1_L__RU48_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_1_L__RU48_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_1_L__RU48_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_1_L__RU48_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_2_L (0x003925D0) +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_2_L__RU48_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_2_L__RU48_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_2_L__RU48_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_2_L__RU48_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_2_L__RU48_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_2_L__RU48_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU48_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_0_L (0x003925D8) +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_0_L__RU49_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_0_L__RU49_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_0_L__RU49_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_0_L__RU49_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_0_L__RU49_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_0_L__RU49_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_0_L__RU49_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_0_L__RU49_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_0_L__RU49_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_1_L (0x003925E0) +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_1_L__RU49_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_1_L__RU49_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_1_L__RU49_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_1_L__RU49_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_1_L__RU49_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_1_L__RU49_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_2_L (0x003925E8) +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_2_L__RU49_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_2_L__RU49_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_2_L__RU49_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_2_L__RU49_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_2_L__RU49_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_2_L__RU49_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU49_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_0_L (0x003925F0) +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_0_L__RU50_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_0_L__RU50_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_0_L__RU50_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_0_L__RU50_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_0_L__RU50_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_0_L__RU50_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_0_L__RU50_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_0_L__RU50_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_0_L__RU50_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_1_L (0x003925F8) +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_1_L__RU50_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_1_L__RU50_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_1_L__RU50_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_1_L__RU50_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_1_L__RU50_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_1_L__RU50_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_2_L (0x00392600) +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_2_L__RU50_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_2_L__RU50_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_2_L__RU50_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_2_L__RU50_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_2_L__RU50_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_2_L__RU50_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU50_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_0_L (0x00392608) +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_0_L__RU51_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_0_L__RU51_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_0_L__RU51_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_0_L__RU51_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_0_L__RU51_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_0_L__RU51_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_0_L__RU51_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_0_L__RU51_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_0_L__RU51_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_1_L (0x00392610) +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_1_L__RU51_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_1_L__RU51_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_1_L__RU51_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_1_L__RU51_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_1_L__RU51_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_1_L__RU51_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_2_L (0x00392618) +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_2_L__RU51_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_2_L__RU51_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_2_L__RU51_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_2_L__RU51_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_2_L__RU51_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_2_L__RU51_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU51_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_0_L (0x00392620) +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_0_L__RU52_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_0_L__RU52_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_0_L__RU52_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_0_L__RU52_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_0_L__RU52_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_0_L__RU52_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_0_L__RU52_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_0_L__RU52_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_0_L__RU52_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_1_L (0x00392628) +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_1_L__RU52_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_1_L__RU52_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_1_L__RU52_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_1_L__RU52_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_1_L__RU52_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_1_L__RU52_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_2_L (0x00392630) +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_2_L__RU52_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_2_L__RU52_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_2_L__RU52_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_2_L__RU52_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_2_L__RU52_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_2_L__RU52_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU52_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_0_L (0x00392638) +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_0_L__RU53_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_0_L__RU53_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_0_L__RU53_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_0_L__RU53_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_0_L__RU53_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_0_L__RU53_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_0_L__RU53_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_0_L__RU53_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_0_L__RU53_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_1_L (0x00392640) +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_1_L__RU53_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_1_L__RU53_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_1_L__RU53_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_1_L__RU53_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_1_L__RU53_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_1_L__RU53_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_2_L (0x00392648) +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_2_L__RU53_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_2_L__RU53_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_2_L__RU53_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_2_L__RU53_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_2_L__RU53_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_2_L__RU53_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU53_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_0_L (0x00392650) +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_0_L__RU54_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_0_L__RU54_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_0_L__RU54_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_0_L__RU54_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_0_L__RU54_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_0_L__RU54_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_0_L__RU54_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_0_L__RU54_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_0_L__RU54_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_1_L (0x00392658) +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_1_L__RU54_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_1_L__RU54_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_1_L__RU54_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_1_L__RU54_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_1_L__RU54_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_1_L__RU54_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_2_L (0x00392660) +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_2_L__RU54_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_2_L__RU54_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_2_L__RU54_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_2_L__RU54_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_2_L__RU54_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_2_L__RU54_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU54_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_0_L (0x00392668) +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_0_L__RU55_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_0_L__RU55_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_0_L__RU55_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_0_L__RU55_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_0_L__RU55_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_0_L__RU55_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_0_L__RU55_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_0_L__RU55_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_0_L__RU55_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_1_L (0x00392670) +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_1_L__RU55_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_1_L__RU55_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_1_L__RU55_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_1_L__RU55_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_1_L__RU55_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_1_L__RU55_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_2_L (0x00392678) +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_2_L__RU55_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_2_L__RU55_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_2_L__RU55_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_2_L__RU55_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_2_L__RU55_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_2_L__RU55_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU55_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_0_L (0x00392680) +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_0_L__RU56_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_0_L__RU56_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_0_L__RU56_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_0_L__RU56_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_0_L__RU56_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_0_L__RU56_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_0_L__RU56_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_0_L__RU56_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_0_L__RU56_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_1_L (0x00392688) +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_1_L__RU56_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_1_L__RU56_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_1_L__RU56_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_1_L__RU56_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_1_L__RU56_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_1_L__RU56_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_2_L (0x00392690) +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_2_L__RU56_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_2_L__RU56_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_2_L__RU56_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_2_L__RU56_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_2_L__RU56_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_2_L__RU56_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU56_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_0_L (0x00392698) +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_0_L__RU57_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_0_L__RU57_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_0_L__RU57_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_0_L__RU57_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_0_L__RU57_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_0_L__RU57_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_0_L__RU57_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_0_L__RU57_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_0_L__RU57_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_1_L (0x003926A0) +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_1_L__RU57_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_1_L__RU57_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_1_L__RU57_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_1_L__RU57_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_1_L__RU57_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_1_L__RU57_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_2_L (0x003926A8) +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_2_L__RU57_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_2_L__RU57_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_2_L__RU57_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_2_L__RU57_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_2_L__RU57_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_2_L__RU57_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU57_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_0_L (0x003926B0) +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_0_L__RU58_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_0_L__RU58_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_0_L__RU58_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_0_L__RU58_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_0_L__RU58_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_0_L__RU58_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_0_L__RU58_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_0_L__RU58_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_0_L__RU58_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_1_L (0x003926B8) +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_1_L__RU58_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_1_L__RU58_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_1_L__RU58_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_1_L__RU58_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_1_L__RU58_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_1_L__RU58_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_2_L (0x003926C0) +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_2_L__RU58_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_2_L__RU58_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_2_L__RU58_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_2_L__RU58_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_2_L__RU58_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_2_L__RU58_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU58_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_0_L (0x003926C8) +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_0_L__RU59_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_0_L__RU59_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_0_L__RU59_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_0_L__RU59_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_0_L__RU59_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_0_L__RU59_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_0_L__RU59_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_0_L__RU59_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_0_L__RU59_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_1_L (0x003926D0) +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_1_L__RU59_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_1_L__RU59_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_1_L__RU59_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_1_L__RU59_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_1_L__RU59_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_1_L__RU59_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_2_L (0x003926D8) +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_2_L__RU59_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_2_L__RU59_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_2_L__RU59_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_2_L__RU59_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_2_L__RU59_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_2_L__RU59_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU59_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_0_L (0x003926E0) +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_0_L__RU60_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_0_L__RU60_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_0_L__RU60_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_0_L__RU60_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_0_L__RU60_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_0_L__RU60_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_0_L__RU60_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_0_L__RU60_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_0_L__RU60_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_1_L (0x003926E8) +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_1_L__RU60_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_1_L__RU60_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_1_L__RU60_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_1_L__RU60_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_1_L__RU60_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_1_L__RU60_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_2_L (0x003926F0) +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_2_L__RU60_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_2_L__RU60_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_2_L__RU60_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_2_L__RU60_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_2_L__RU60_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_2_L__RU60_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU60_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_0_L (0x003926F8) +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_0_L__RU61_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_0_L__RU61_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_0_L__RU61_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_0_L__RU61_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_0_L__RU61_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_0_L__RU61_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_0_L__RU61_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_0_L__RU61_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_0_L__RU61_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_1_L (0x00392700) +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_1_L__RU61_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_1_L__RU61_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_1_L__RU61_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_1_L__RU61_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_1_L__RU61_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_1_L__RU61_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_2_L (0x00392708) +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_2_L__RU61_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_2_L__RU61_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_2_L__RU61_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_2_L__RU61_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_2_L__RU61_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_2_L__RU61_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU61_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_0_L (0x00392710) +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_0_L__RU62_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_0_L__RU62_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_0_L__RU62_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_0_L__RU62_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_0_L__RU62_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_0_L__RU62_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_0_L__RU62_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_0_L__RU62_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_0_L__RU62_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_1_L (0x00392718) +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_1_L__RU62_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_1_L__RU62_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_1_L__RU62_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_1_L__RU62_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_1_L__RU62_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_1_L__RU62_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_2_L (0x00392720) +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_2_L__RU62_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_2_L__RU62_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_2_L__RU62_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_2_L__RU62_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_2_L__RU62_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_2_L__RU62_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU62_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_0_L (0x00392728) +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_0_L__RU63_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_0_L__RU63_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_0_L__RU63_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_0_L__RU63_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_0_L__RU63_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_0_L__RU63_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_0_L__RU63_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_0_L__RU63_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_0_L__RU63_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_1_L (0x00392730) +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_1_L__RU63_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_1_L__RU63_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_1_L__RU63_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_1_L__RU63_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_1_L__RU63_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_1_L__RU63_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_2_L (0x00392738) +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_2_L__RU63_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_2_L__RU63_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_2_L__RU63_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_2_L__RU63_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_2_L__RU63_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_2_L__RU63_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU63_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_0_L (0x00392740) +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_0_L__RU64_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_0_L__RU64_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_0_L__RU64_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_0_L__RU64_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_0_L__RU64_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_0_L__RU64_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_0_L__RU64_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_0_L__RU64_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_0_L__RU64_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_1_L (0x00392748) +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_1_L__RU64_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_1_L__RU64_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_1_L__RU64_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_1_L__RU64_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_1_L__RU64_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_1_L__RU64_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_2_L (0x00392750) +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_2_L__RU64_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_2_L__RU64_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_2_L__RU64_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_2_L__RU64_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_2_L__RU64_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_2_L__RU64_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU64_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_0_L (0x00392758) +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_0_L__RU65_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_0_L__RU65_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_0_L__RU65_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_0_L__RU65_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_0_L__RU65_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_0_L__RU65_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_0_L__RU65_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_0_L__RU65_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_0_L__RU65_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_1_L (0x00392760) +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_1_L__RU65_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_1_L__RU65_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_1_L__RU65_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_1_L__RU65_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_1_L__RU65_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_1_L__RU65_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_2_L (0x00392768) +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_2_L__RU65_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_2_L__RU65_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_2_L__RU65_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_2_L__RU65_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_2_L__RU65_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_2_L__RU65_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU65_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_0_L (0x00392770) +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_0_L__RU66_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_0_L__RU66_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_0_L__RU66_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_0_L__RU66_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_0_L__RU66_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_0_L__RU66_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_0_L__RU66_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_0_L__RU66_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_0_L__RU66_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_1_L (0x00392778) +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_1_L__RU66_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_1_L__RU66_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_1_L__RU66_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_1_L__RU66_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_1_L__RU66_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_1_L__RU66_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_2_L (0x00392780) +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_2_L__RU66_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_2_L__RU66_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_2_L__RU66_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_2_L__RU66_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_2_L__RU66_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_2_L__RU66_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU66_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_0_L (0x00392788) +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_0_L__RU67_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_0_L__RU67_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_0_L__RU67_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_0_L__RU67_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_0_L__RU67_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_0_L__RU67_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_0_L__RU67_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_0_L__RU67_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_0_L__RU67_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_1_L (0x00392790) +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_1_L__RU67_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_1_L__RU67_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_1_L__RU67_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_1_L__RU67_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_1_L__RU67_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_1_L__RU67_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_2_L (0x00392798) +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_2_L__RU67_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_2_L__RU67_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_2_L__RU67_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_2_L__RU67_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_2_L__RU67_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_2_L__RU67_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU67_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_0_L (0x003927A0) +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_0_L__RU68_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_0_L__RU68_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_0_L__RU68_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_0_L__RU68_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_0_L__RU68_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_0_L__RU68_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_0_L__RU68_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_0_L__RU68_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_0_L__RU68_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_1_L (0x003927A8) +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_1_L__RU68_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_1_L__RU68_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_1_L__RU68_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_1_L__RU68_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_1_L__RU68_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_1_L__RU68_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_2_L (0x003927B0) +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_2_L__RU68_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_2_L__RU68_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_2_L__RU68_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_2_L__RU68_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_2_L__RU68_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_2_L__RU68_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU68_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_0_L (0x003927B8) +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_0_L__RU69_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_0_L__RU69_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_0_L__RU69_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_0_L__RU69_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_0_L__RU69_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_0_L__RU69_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_0_L__RU69_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_0_L__RU69_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_0_L__RU69_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_1_L (0x003927C0) +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_1_L__RU69_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_1_L__RU69_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_1_L__RU69_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_1_L__RU69_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_1_L__RU69_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_1_L__RU69_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_2_L (0x003927C8) +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_2_L__RU69_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_2_L__RU69_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_2_L__RU69_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_2_L__RU69_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_2_L__RU69_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_2_L__RU69_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU69_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_0_L (0x003927D0) +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_0_L__RU70_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_0_L__RU70_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_0_L__RU70_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_0_L__RU70_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_0_L__RU70_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_0_L__RU70_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_0_L__RU70_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_0_L__RU70_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_0_L__RU70_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_1_L (0x003927D8) +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_1_L__RU70_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_1_L__RU70_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_1_L__RU70_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_1_L__RU70_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_1_L__RU70_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_1_L__RU70_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_2_L (0x003927E0) +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_2_L__RU70_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_2_L__RU70_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_2_L__RU70_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_2_L__RU70_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_2_L__RU70_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_2_L__RU70_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU70_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_0_L (0x003927E8) +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_0_L__RU71_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_0_L__RU71_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_0_L__RU71_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_0_L__RU71_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_0_L__RU71_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_0_L__RU71_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_0_L__RU71_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_0_L__RU71_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_0_L__RU71_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_1_L (0x003927F0) +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_1_L__RU71_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_1_L__RU71_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_1_L__RU71_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_1_L__RU71_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_1_L__RU71_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_1_L__RU71_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_2_L (0x003927F8) +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_2_L__RU71_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_2_L__RU71_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_2_L__RU71_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_2_L__RU71_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_2_L__RU71_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_2_L__RU71_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU71_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_0_L (0x00392800) +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_0_L__RU72_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_0_L__RU72_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_0_L__RU72_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_0_L__RU72_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_0_L__RU72_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_0_L__RU72_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_0_L__RU72_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_0_L__RU72_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_0_L__RU72_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_1_L (0x00392808) +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_1_L__RU72_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_1_L__RU72_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_1_L__RU72_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_1_L__RU72_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_1_L__RU72_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_1_L__RU72_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_2_L (0x00392810) +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_2_L__RU72_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_2_L__RU72_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_2_L__RU72_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_2_L__RU72_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_2_L__RU72_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_2_L__RU72_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU72_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_0_L (0x00392818) +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_0_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_0_L__RU73_NUM_USERS___POR 0x0 +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_0_L__RU73_RU_VALID___POR 0x0 +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_0_L__RU73_RU_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_0_L__RU73_NUM_USERS___M 0x000F0000 +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_0_L__RU73_NUM_USERS___S 16 +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_0_L__RU73_RU_VALID___M 0x00000300 +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_0_L__RU73_RU_VALID___S 8 +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_0_L__RU73_RU_TYPE___M 0x00000007 +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_0_L__RU73_RU_TYPE___S 0 +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_0_L___M 0x000F0307 +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_0_L___S 0 + +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_1_L (0x00392820) +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_1_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_1_L__RU73_1_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_1_L__RU73_0_BAND_TYPE___POR 0x0 +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_1_L__RU73_1_BAND_TYPE___M 0x00000100 +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_1_L__RU73_1_BAND_TYPE___S 8 +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_1_L__RU73_0_BAND_TYPE___M 0x00000001 +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_1_L__RU73_0_BAND_TYPE___S 0 +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_1_L___M 0x00000101 +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_1_L___S 0 + +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_2_L (0x00392828) +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_2_L___POR 0x00000000 +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_2_L__RU73_1_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_2_L__RU73_0_USER_INDEX___POR 0x00 +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_2_L__RU73_1_USER_INDEX___M 0x00003F00 +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_2_L__RU73_1_USER_INDEX___S 8 +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_2_L__RU73_0_USER_INDEX___M 0x0000003F +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_2_L__RU73_0_USER_INDEX___S 0 +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_2_L___M 0x00003F3F +#define PHYA_TXFD_RU_RU73_RU_INFO_RD_WR_2_L___S 0 + +#define PHYA_TXFD_USER_PARAM_CORR_WR_L (0x00392830) +#define PHYA_TXFD_USER_PARAM_CORR_WR_L___RWC QCSR_REG_RW +#define PHYA_TXFD_USER_PARAM_CORR_WR_L___POR 0x00000000 +#define PHYA_TXFD_USER_PARAM_CORR_WR_L__NUM_DATA_SYM___POR 0x0000 +#define PHYA_TXFD_USER_PARAM_CORR_WR_L__NUM_DATA_SYM___M 0x0000FFFF +#define PHYA_TXFD_USER_PARAM_CORR_WR_L__NUM_DATA_SYM___S 0 +#define PHYA_TXFD_USER_PARAM_CORR_WR_L___M 0x0000FFFF +#define PHYA_TXFD_USER_PARAM_CORR_WR_L___S 0 + +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B0 (0x00392838) +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B0___RWC QCSR_REG_RW +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B0___POR 0x00000000 +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B0__POWER_NORM_EN___POR 0x0 +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B0__CHAIN_CSD_DELTA___POR 0x00 +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B0__CHAIN_CSD_EN___POR 0x0 +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B0__POWER_NORM_EN___M 0x00010000 +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B0__POWER_NORM_EN___S 16 +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B0__CHAIN_CSD_DELTA___M 0x0000FF00 +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B0__CHAIN_CSD_DELTA___S 8 +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B0__CHAIN_CSD_EN___M 0x00000001 +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B0__CHAIN_CSD_EN___S 0 +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B0___M 0x0001FF01 +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B0___S 0 + +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B1 (0x003929B0) +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B1___RWC QCSR_REG_RW +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B1___POR 0x00000000 +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B1__POWER_NORM_EN___POR 0x0 +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B1__CHAIN_CSD_DELTA___POR 0x00 +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B1__CHAIN_CSD_EN___POR 0x0 +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B1__POWER_NORM_EN___M 0x00010000 +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B1__POWER_NORM_EN___S 16 +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B1__CHAIN_CSD_DELTA___M 0x0000FF00 +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B1__CHAIN_CSD_DELTA___S 8 +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B1__CHAIN_CSD_EN___M 0x00000001 +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B1__CHAIN_CSD_EN___S 0 +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B1___M 0x0001FF01 +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_L_B1___S 0 + +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_U_B0 (0x0039283C) +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_U_B0___RWC QCSR_REG_RW +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_U_B0___POR 0x00000000 +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_U_B0__POWER_NORM_FACTOR___POR 0x0000 +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_U_B0__POWER_NORM_FACTOR___M 0x00003FFF +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_U_B0__POWER_NORM_FACTOR___S 0 +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_U_B0___M 0x00003FFF +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_U_B0___S 0 + +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_U_B1 (0x003929B4) +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_U_B1___RWC QCSR_REG_RW +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_U_B1___POR 0x00000000 +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_U_B1__POWER_NORM_FACTOR___POR 0x0000 +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_U_B1__POWER_NORM_FACTOR___M 0x00003FFF +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_U_B1__POWER_NORM_FACTOR___S 0 +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_U_B1___M 0x00003FFF +#define PHYA_TXFD_STR_RU_RU_PARAMS_WR_U_B1___S 0 + +#define PHYA_TXFD_STR_RU_PARAMS_WR_L_B0 (0x00392960) +#define PHYA_TXFD_STR_RU_PARAMS_WR_L_B0___RWC QCSR_REG_RW +#define PHYA_TXFD_STR_RU_PARAMS_WR_L_B0___POR 0x00000000 +#define PHYA_TXFD_STR_RU_PARAMS_WR_L_B0__RU_PARAMS_WR_SPARE_0___POR 0x00000000 +#define PHYA_TXFD_STR_RU_PARAMS_WR_L_B0__RU_PARAMS_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXFD_STR_RU_PARAMS_WR_L_B0__RU_PARAMS_WR_SPARE_0___S 0 +#define PHYA_TXFD_STR_RU_PARAMS_WR_L_B0___M 0xFFFFFFFF +#define PHYA_TXFD_STR_RU_PARAMS_WR_L_B0___S 0 + +#define PHYA_TXFD_STR_RU_PARAMS_WR_L_B1 (0x00392AD8) +#define PHYA_TXFD_STR_RU_PARAMS_WR_L_B1___RWC QCSR_REG_RW +#define PHYA_TXFD_STR_RU_PARAMS_WR_L_B1___POR 0x00000000 +#define PHYA_TXFD_STR_RU_PARAMS_WR_L_B1__RU_PARAMS_WR_SPARE_0___POR 0x00000000 +#define PHYA_TXFD_STR_RU_PARAMS_WR_L_B1__RU_PARAMS_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXFD_STR_RU_PARAMS_WR_L_B1__RU_PARAMS_WR_SPARE_0___S 0 +#define PHYA_TXFD_STR_RU_PARAMS_WR_L_B1___M 0xFFFFFFFF +#define PHYA_TXFD_STR_RU_PARAMS_WR_L_B1___S 0 + +#define PHYA_TXFD_STR_RU_PARAMS_WR_U_B0 (0x00392964) +#define PHYA_TXFD_STR_RU_PARAMS_WR_U_B0___RWC QCSR_REG_RW +#define PHYA_TXFD_STR_RU_PARAMS_WR_U_B0___POR 0x00000000 +#define PHYA_TXFD_STR_RU_PARAMS_WR_U_B0__RU_PARAMS_WR_SPARE_1___POR 0x00000000 +#define PHYA_TXFD_STR_RU_PARAMS_WR_U_B0__RU_PARAMS_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXFD_STR_RU_PARAMS_WR_U_B0__RU_PARAMS_WR_SPARE_1___S 0 +#define PHYA_TXFD_STR_RU_PARAMS_WR_U_B0___M 0xFFFFFFFF +#define PHYA_TXFD_STR_RU_PARAMS_WR_U_B0___S 0 + +#define PHYA_TXFD_STR_RU_PARAMS_WR_U_B1 (0x00392ADC) +#define PHYA_TXFD_STR_RU_PARAMS_WR_U_B1___RWC QCSR_REG_RW +#define PHYA_TXFD_STR_RU_PARAMS_WR_U_B1___POR 0x00000000 +#define PHYA_TXFD_STR_RU_PARAMS_WR_U_B1__RU_PARAMS_WR_SPARE_1___POR 0x00000000 +#define PHYA_TXFD_STR_RU_PARAMS_WR_U_B1__RU_PARAMS_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXFD_STR_RU_PARAMS_WR_U_B1__RU_PARAMS_WR_SPARE_1___S 0 +#define PHYA_TXFD_STR_RU_PARAMS_WR_U_B1___M 0xFFFFFFFF +#define PHYA_TXFD_STR_RU_PARAMS_WR_U_B1___S 0 + +#define PHYA_TXFD_DUMMY_L (0x00397FF8) +#define PHYA_TXFD_DUMMY_L___RWC QCSR_REG_RW +#define PHYA_TXFD_DUMMY_L___POR 0x00000000 +#define PHYA_TXFD_DUMMY_L__DUMMY___POR 0x0 +#define PHYA_TXFD_DUMMY_L__DUMMY___M 0x00000001 +#define PHYA_TXFD_DUMMY_L__DUMMY___S 0 +#define PHYA_TXFD_DUMMY_L___M 0x00000001 +#define PHYA_TXFD_DUMMY_L___S 0 + +#define PHYA_RXTD_ECO_CONTROL_L (0x003A0000) +#define PHYA_RXTD_ECO_CONTROL_L___RWC QCSR_REG_RW +#define PHYA_RXTD_ECO_CONTROL_L___POR 0x00000000 +#define PHYA_RXTD_ECO_CONTROL_L__ECO_CTRL___POR 0x00000000 +#define PHYA_RXTD_ECO_CONTROL_L__ECO_CTRL___M 0xFFFFFFFF +#define PHYA_RXTD_ECO_CONTROL_L__ECO_CTRL___S 0 +#define PHYA_RXTD_ECO_CONTROL_L___M 0xFFFFFFFF +#define PHYA_RXTD_ECO_CONTROL_L___S 0 + +#define PHYA_RXTD_ECO_CONTROL_U (0x003A0004) +#define PHYA_RXTD_ECO_CONTROL_U___RWC QCSR_REG_RW +#define PHYA_RXTD_ECO_CONTROL_U___POR 0x00000000 +#define PHYA_RXTD_ECO_CONTROL_U__ECO_CFG___POR 0x00000000 +#define PHYA_RXTD_ECO_CONTROL_U__ECO_CFG___M 0xFFFFFFFF +#define PHYA_RXTD_ECO_CONTROL_U__ECO_CFG___S 0 +#define PHYA_RXTD_ECO_CONTROL_U___M 0xFFFFFFFF +#define PHYA_RXTD_ECO_CONTROL_U___S 0 + +#define PHYA_RXTD_ECO_STATUS_L (0x003A0008) +#define PHYA_RXTD_ECO_STATUS_L___RWC QCSR_REG_RO +#define PHYA_RXTD_ECO_STATUS_L___POR 0x00000000 +#define PHYA_RXTD_ECO_STATUS_L__ECO_STAT___POR 0x00000000 +#define PHYA_RXTD_ECO_STATUS_L__ECO_STAT___M 0xFFFFFFFF +#define PHYA_RXTD_ECO_STATUS_L__ECO_STAT___S 0 +#define PHYA_RXTD_ECO_STATUS_L___M 0xFFFFFFFF +#define PHYA_RXTD_ECO_STATUS_L___S 0 + +#define PHYA_RXTD_EVENT_STATUS_L (0x003A0010) +#define PHYA_RXTD_EVENT_STATUS_L___RWC QCSR_REG_RW +#define PHYA_RXTD_EVENT_STATUS_L___POR 0x00000000 +#define PHYA_RXTD_EVENT_STATUS_L__SIZING_EVENT_2ND_AGC___POR 0x0 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR1_RADAR_TIMEOUT_EVENT___POR 0x0 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR1_SSCAN_DONE_EVENT___POR 0x0 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR1_SSCAN_RDY_EVENT___POR 0x0 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR1_LONG_FFT_RPT_EVENT___POR 0x0 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR1_SHORT_FFT_RPT_EVENT___POR 0x0 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR1_RADAR_DONE_EVENT___POR 0x0 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR1_RADAR_DET_EVENT___POR 0x0 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR0_RADAR_TIMEOUT_EVENT___POR 0x0 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR0_SSCAN_DONE_EVENT___POR 0x0 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR0_SSCAN_RDY_EVENT___POR 0x0 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR0_LONG_FFT_RPT_EVENT___POR 0x0 +#define PHYA_RXTD_EVENT_STATUS_L__SIZING_EVENT___POR 0x0 +#define PHYA_RXTD_EVENT_STATUS_L__NFCAL_DONE_EVENT___POR 0x0 +#define PHYA_RXTD_EVENT_STATUS_L__RTT_DONE_EVENT___POR 0x0 +#define PHYA_RXTD_EVENT_STATUS_L__CCK_DATA_EVENT___POR 0x0 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR0_SHORT_FFT_RPT_EVENT___POR 0x0 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR0_RADAR_DONE_EVENT___POR 0x0 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR0_RADAR_DET_EVENT___POR 0x0 +#define PHYA_RXTD_EVENT_STATUS_L__SYM_EVENT___POR 0x0 +#define PHYA_RXTD_EVENT_STATUS_L__PKT_EVENT___POR 0x0 +#define PHYA_RXTD_EVENT_STATUS_L__ECO_EVENT___POR 0x0 +#define PHYA_RXTD_EVENT_STATUS_L__RXTD_ERROR_EVENT___POR 0x0 +#define PHYA_RXTD_EVENT_STATUS_L__FATAL_ERROR_EVENT___POR 0x0 +#define PHYA_RXTD_EVENT_STATUS_L__SIZING_EVENT_2ND_AGC___M 0x00800000 +#define PHYA_RXTD_EVENT_STATUS_L__SIZING_EVENT_2ND_AGC___S 23 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR1_RADAR_TIMEOUT_EVENT___M 0x00400000 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR1_RADAR_TIMEOUT_EVENT___S 22 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR1_SSCAN_DONE_EVENT___M 0x00200000 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR1_SSCAN_DONE_EVENT___S 21 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR1_SSCAN_RDY_EVENT___M 0x00100000 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR1_SSCAN_RDY_EVENT___S 20 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR1_LONG_FFT_RPT_EVENT___M 0x00080000 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR1_LONG_FFT_RPT_EVENT___S 19 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR1_SHORT_FFT_RPT_EVENT___M 0x00040000 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR1_SHORT_FFT_RPT_EVENT___S 18 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR1_RADAR_DONE_EVENT___M 0x00020000 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR1_RADAR_DONE_EVENT___S 17 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR1_RADAR_DET_EVENT___M 0x00010000 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR1_RADAR_DET_EVENT___S 16 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR0_RADAR_TIMEOUT_EVENT___M 0x00008000 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR0_RADAR_TIMEOUT_EVENT___S 15 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR0_SSCAN_DONE_EVENT___M 0x00004000 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR0_SSCAN_DONE_EVENT___S 14 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR0_SSCAN_RDY_EVENT___M 0x00002000 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR0_SSCAN_RDY_EVENT___S 13 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR0_LONG_FFT_RPT_EVENT___M 0x00001000 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR0_LONG_FFT_RPT_EVENT___S 12 +#define PHYA_RXTD_EVENT_STATUS_L__SIZING_EVENT___M 0x00000800 +#define PHYA_RXTD_EVENT_STATUS_L__SIZING_EVENT___S 11 +#define PHYA_RXTD_EVENT_STATUS_L__NFCAL_DONE_EVENT___M 0x00000400 +#define PHYA_RXTD_EVENT_STATUS_L__NFCAL_DONE_EVENT___S 10 +#define PHYA_RXTD_EVENT_STATUS_L__RTT_DONE_EVENT___M 0x00000200 +#define PHYA_RXTD_EVENT_STATUS_L__RTT_DONE_EVENT___S 9 +#define PHYA_RXTD_EVENT_STATUS_L__CCK_DATA_EVENT___M 0x00000100 +#define PHYA_RXTD_EVENT_STATUS_L__CCK_DATA_EVENT___S 8 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR0_SHORT_FFT_RPT_EVENT___M 0x00000080 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR0_SHORT_FFT_RPT_EVENT___S 7 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR0_RADAR_DONE_EVENT___M 0x00000040 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR0_RADAR_DONE_EVENT___S 6 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR0_RADAR_DET_EVENT___M 0x00000020 +#define PHYA_RXTD_EVENT_STATUS_L__RADAR0_RADAR_DET_EVENT___S 5 +#define PHYA_RXTD_EVENT_STATUS_L__SYM_EVENT___M 0x00000010 +#define PHYA_RXTD_EVENT_STATUS_L__SYM_EVENT___S 4 +#define PHYA_RXTD_EVENT_STATUS_L__PKT_EVENT___M 0x00000008 +#define PHYA_RXTD_EVENT_STATUS_L__PKT_EVENT___S 3 +#define PHYA_RXTD_EVENT_STATUS_L__ECO_EVENT___M 0x00000004 +#define PHYA_RXTD_EVENT_STATUS_L__ECO_EVENT___S 2 +#define PHYA_RXTD_EVENT_STATUS_L__RXTD_ERROR_EVENT___M 0x00000002 +#define PHYA_RXTD_EVENT_STATUS_L__RXTD_ERROR_EVENT___S 1 +#define PHYA_RXTD_EVENT_STATUS_L__FATAL_ERROR_EVENT___M 0x00000001 +#define PHYA_RXTD_EVENT_STATUS_L__FATAL_ERROR_EVENT___S 0 +#define PHYA_RXTD_EVENT_STATUS_L___M 0x00FFFFFF +#define PHYA_RXTD_EVENT_STATUS_L___S 0 + +#define PHYA_RXTD_EVENT_MASK_L (0x003A0018) +#define PHYA_RXTD_EVENT_MASK_L___RWC QCSR_REG_RW +#define PHYA_RXTD_EVENT_MASK_L___POR 0x00FFFFFF +#define PHYA_RXTD_EVENT_MASK_L__SIZING_EVENT_2ND_AGC_MASK___POR 0x1 +#define PHYA_RXTD_EVENT_MASK_L__RADAR1_RADAR_TIMEOUT_EVENT_MASK___POR 0x1 +#define PHYA_RXTD_EVENT_MASK_L__RADAR1_SSCAN_DONE_EVENT_MASK___POR 0x1 +#define PHYA_RXTD_EVENT_MASK_L__RADAR1_SSCAN_RDY_EVENT_MASK___POR 0x1 +#define PHYA_RXTD_EVENT_MASK_L__RADAR1_LONG_FFT_RPT_EVENT_MASK___POR 0x1 +#define PHYA_RXTD_EVENT_MASK_L__RADAR1_SHORT_FFT_RPT_EVENT_MASK___POR 0x1 +#define PHYA_RXTD_EVENT_MASK_L__RADAR1_RADAR_DONE_EVENT_MASK___POR 0x1 +#define PHYA_RXTD_EVENT_MASK_L__RADAR1_RADAR_DET_EVENT_MASK___POR 0x1 +#define PHYA_RXTD_EVENT_MASK_L__RADAR0_RADAR_TIMEOUT_EVENT_MASK___POR 0x1 +#define PHYA_RXTD_EVENT_MASK_L__RADAR0_SSCAN_DONE_EVENT_MASK___POR 0x1 +#define PHYA_RXTD_EVENT_MASK_L__RADAR0_SSCAN_RDY_EVENT_MASK___POR 0x1 +#define PHYA_RXTD_EVENT_MASK_L__RADAR0_LONG_FFT_RPT_EVENT_MASK___POR 0x1 +#define PHYA_RXTD_EVENT_MASK_L__SIZING_EVENT_MASK___POR 0x1 +#define PHYA_RXTD_EVENT_MASK_L__NFCAL_DONE_EVENT_MASK___POR 0x1 +#define PHYA_RXTD_EVENT_MASK_L__RTT_DONE_EVENT_MASK___POR 0x1 +#define PHYA_RXTD_EVENT_MASK_L__CCK_DATA_EVENT_MASK___POR 0x1 +#define PHYA_RXTD_EVENT_MASK_L__RADAR0_SHORT_FFT_RPT_EVENT_MASK___POR 0x1 +#define PHYA_RXTD_EVENT_MASK_L__RADAR0_RADAR_DONE_EVENT_MASK___POR 0x1 +#define PHYA_RXTD_EVENT_MASK_L__RADAR0_RADAR_DET_EVENT_MASK___POR 0x1 +#define PHYA_RXTD_EVENT_MASK_L__SYM_EVENT_MASK___POR 0x1 +#define PHYA_RXTD_EVENT_MASK_L__PKT_EVENT_MASK___POR 0x1 +#define PHYA_RXTD_EVENT_MASK_L__ECO_EVENT_MASK___POR 0x1 +#define PHYA_RXTD_EVENT_MASK_L__RXTD_ERROR_EVENT_MASK___POR 0x1 +#define PHYA_RXTD_EVENT_MASK_L__FATAL_ERROR_EVENT_MASK___POR 0x1 +#define PHYA_RXTD_EVENT_MASK_L__SIZING_EVENT_2ND_AGC_MASK___M 0x00800000 +#define PHYA_RXTD_EVENT_MASK_L__SIZING_EVENT_2ND_AGC_MASK___S 23 +#define PHYA_RXTD_EVENT_MASK_L__RADAR1_RADAR_TIMEOUT_EVENT_MASK___M 0x00400000 +#define PHYA_RXTD_EVENT_MASK_L__RADAR1_RADAR_TIMEOUT_EVENT_MASK___S 22 +#define PHYA_RXTD_EVENT_MASK_L__RADAR1_SSCAN_DONE_EVENT_MASK___M 0x00200000 +#define PHYA_RXTD_EVENT_MASK_L__RADAR1_SSCAN_DONE_EVENT_MASK___S 21 +#define PHYA_RXTD_EVENT_MASK_L__RADAR1_SSCAN_RDY_EVENT_MASK___M 0x00100000 +#define PHYA_RXTD_EVENT_MASK_L__RADAR1_SSCAN_RDY_EVENT_MASK___S 20 +#define PHYA_RXTD_EVENT_MASK_L__RADAR1_LONG_FFT_RPT_EVENT_MASK___M 0x00080000 +#define PHYA_RXTD_EVENT_MASK_L__RADAR1_LONG_FFT_RPT_EVENT_MASK___S 19 +#define PHYA_RXTD_EVENT_MASK_L__RADAR1_SHORT_FFT_RPT_EVENT_MASK___M 0x00040000 +#define PHYA_RXTD_EVENT_MASK_L__RADAR1_SHORT_FFT_RPT_EVENT_MASK___S 18 +#define PHYA_RXTD_EVENT_MASK_L__RADAR1_RADAR_DONE_EVENT_MASK___M 0x00020000 +#define PHYA_RXTD_EVENT_MASK_L__RADAR1_RADAR_DONE_EVENT_MASK___S 17 +#define PHYA_RXTD_EVENT_MASK_L__RADAR1_RADAR_DET_EVENT_MASK___M 0x00010000 +#define PHYA_RXTD_EVENT_MASK_L__RADAR1_RADAR_DET_EVENT_MASK___S 16 +#define PHYA_RXTD_EVENT_MASK_L__RADAR0_RADAR_TIMEOUT_EVENT_MASK___M 0x00008000 +#define PHYA_RXTD_EVENT_MASK_L__RADAR0_RADAR_TIMEOUT_EVENT_MASK___S 15 +#define PHYA_RXTD_EVENT_MASK_L__RADAR0_SSCAN_DONE_EVENT_MASK___M 0x00004000 +#define PHYA_RXTD_EVENT_MASK_L__RADAR0_SSCAN_DONE_EVENT_MASK___S 14 +#define PHYA_RXTD_EVENT_MASK_L__RADAR0_SSCAN_RDY_EVENT_MASK___M 0x00002000 +#define PHYA_RXTD_EVENT_MASK_L__RADAR0_SSCAN_RDY_EVENT_MASK___S 13 +#define PHYA_RXTD_EVENT_MASK_L__RADAR0_LONG_FFT_RPT_EVENT_MASK___M 0x00001000 +#define PHYA_RXTD_EVENT_MASK_L__RADAR0_LONG_FFT_RPT_EVENT_MASK___S 12 +#define PHYA_RXTD_EVENT_MASK_L__SIZING_EVENT_MASK___M 0x00000800 +#define PHYA_RXTD_EVENT_MASK_L__SIZING_EVENT_MASK___S 11 +#define PHYA_RXTD_EVENT_MASK_L__NFCAL_DONE_EVENT_MASK___M 0x00000400 +#define PHYA_RXTD_EVENT_MASK_L__NFCAL_DONE_EVENT_MASK___S 10 +#define PHYA_RXTD_EVENT_MASK_L__RTT_DONE_EVENT_MASK___M 0x00000200 +#define PHYA_RXTD_EVENT_MASK_L__RTT_DONE_EVENT_MASK___S 9 +#define PHYA_RXTD_EVENT_MASK_L__CCK_DATA_EVENT_MASK___M 0x00000100 +#define PHYA_RXTD_EVENT_MASK_L__CCK_DATA_EVENT_MASK___S 8 +#define PHYA_RXTD_EVENT_MASK_L__RADAR0_SHORT_FFT_RPT_EVENT_MASK___M 0x00000080 +#define PHYA_RXTD_EVENT_MASK_L__RADAR0_SHORT_FFT_RPT_EVENT_MASK___S 7 +#define PHYA_RXTD_EVENT_MASK_L__RADAR0_RADAR_DONE_EVENT_MASK___M 0x00000040 +#define PHYA_RXTD_EVENT_MASK_L__RADAR0_RADAR_DONE_EVENT_MASK___S 6 +#define PHYA_RXTD_EVENT_MASK_L__RADAR0_RADAR_DET_EVENT_MASK___M 0x00000020 +#define PHYA_RXTD_EVENT_MASK_L__RADAR0_RADAR_DET_EVENT_MASK___S 5 +#define PHYA_RXTD_EVENT_MASK_L__SYM_EVENT_MASK___M 0x00000010 +#define PHYA_RXTD_EVENT_MASK_L__SYM_EVENT_MASK___S 4 +#define PHYA_RXTD_EVENT_MASK_L__PKT_EVENT_MASK___M 0x00000008 +#define PHYA_RXTD_EVENT_MASK_L__PKT_EVENT_MASK___S 3 +#define PHYA_RXTD_EVENT_MASK_L__ECO_EVENT_MASK___M 0x00000004 +#define PHYA_RXTD_EVENT_MASK_L__ECO_EVENT_MASK___S 2 +#define PHYA_RXTD_EVENT_MASK_L__RXTD_ERROR_EVENT_MASK___M 0x00000002 +#define PHYA_RXTD_EVENT_MASK_L__RXTD_ERROR_EVENT_MASK___S 1 +#define PHYA_RXTD_EVENT_MASK_L__FATAL_ERROR_EVENT_MASK___M 0x00000001 +#define PHYA_RXTD_EVENT_MASK_L__FATAL_ERROR_EVENT_MASK___S 0 +#define PHYA_RXTD_EVENT_MASK_L___M 0x00FFFFFF +#define PHYA_RXTD_EVENT_MASK_L___S 0 + +#define PHYA_RXTD_ERROR_CODE_L (0x003A0020) +#define PHYA_RXTD_ERROR_CODE_L___RWC QCSR_REG_RO +#define PHYA_RXTD_ERROR_CODE_L___POR 0x00000000 +#define PHYA_RXTD_ERROR_CODE_L__ERROR_CODE___POR 0x00 +#define PHYA_RXTD_ERROR_CODE_L__ERROR_CODE___M 0x000000FF +#define PHYA_RXTD_ERROR_CODE_L__ERROR_CODE___S 0 +#define PHYA_RXTD_ERROR_CODE_L___M 0x000000FF +#define PHYA_RXTD_ERROR_CODE_L___S 0 + +#define PHYA_RXTD_ERROR_STATUS_L (0x003A0028) +#define PHYA_RXTD_ERROR_STATUS_L___RWC QCSR_REG_RO +#define PHYA_RXTD_ERROR_STATUS_L___POR 0x00000000 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR1_RADAR_TIMEOUT_ERROR___POR 0x0 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR1_SSCAN_DONE_ERROR___POR 0x0 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR1_SSCAN_RDY_ERROR___POR 0x0 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR1_LONG_FFT_RPT_ERROR___POR 0x0 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR1_SHORT_FFT_RPT_ERROR___POR 0x0 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR1_RADAR_DONE_ERROR___POR 0x0 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR1_RADAR_DET_ERROR___POR 0x0 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR0_RADAR_TIMEOUT_ERROR___POR 0x0 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR0_SSCAN_DONE_ERROR___POR 0x0 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR0_SSCAN_RDY_ERROR___POR 0x0 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR0_LONG_FFT_RPT_ERROR___POR 0x0 +#define PHYA_RXTD_ERROR_STATUS_L__FFT_DONE_TIMEOUT_ERROR___POR 0x0 +#define PHYA_RXTD_ERROR_STATUS_L__PPM_TS_ERROR___POR 0x0 +#define PHYA_RXTD_ERROR_STATUS_L__VSRC_FIFO_ERROR___POR 0x0 +#define PHYA_RXTD_ERROR_STATUS_L__RXTD_FFT_START_ERROR___POR 0x0 +#define PHYA_RXTD_ERROR_STATUS_L__SIZING_ERROR___POR 0x0 +#define PHYA_RXTD_ERROR_STATUS_L__NFCAL_ERROR___POR 0x0 +#define PHYA_RXTD_ERROR_STATUS_L__RTT_ERROR___POR 0x0 +#define PHYA_RXTD_ERROR_STATUS_L__CCK_DATA_ERROR___POR 0x0 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR0_SHORT_FFT_RPT_ERROR___POR 0x0 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR0_RADAR_DONE_ERROR___POR 0x0 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR0_RADAR_DET_ERROR___POR 0x0 +#define PHYA_RXTD_ERROR_STATUS_L__SYM_ERROR___POR 0x0 +#define PHYA_RXTD_ERROR_STATUS_L__PKT_ERROR___POR 0x0 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR1_RADAR_TIMEOUT_ERROR___M 0x00800000 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR1_RADAR_TIMEOUT_ERROR___S 23 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR1_SSCAN_DONE_ERROR___M 0x00400000 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR1_SSCAN_DONE_ERROR___S 22 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR1_SSCAN_RDY_ERROR___M 0x00200000 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR1_SSCAN_RDY_ERROR___S 21 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR1_LONG_FFT_RPT_ERROR___M 0x00100000 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR1_LONG_FFT_RPT_ERROR___S 20 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR1_SHORT_FFT_RPT_ERROR___M 0x00080000 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR1_SHORT_FFT_RPT_ERROR___S 19 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR1_RADAR_DONE_ERROR___M 0x00040000 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR1_RADAR_DONE_ERROR___S 18 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR1_RADAR_DET_ERROR___M 0x00020000 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR1_RADAR_DET_ERROR___S 17 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR0_RADAR_TIMEOUT_ERROR___M 0x00010000 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR0_RADAR_TIMEOUT_ERROR___S 16 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR0_SSCAN_DONE_ERROR___M 0x00008000 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR0_SSCAN_DONE_ERROR___S 15 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR0_SSCAN_RDY_ERROR___M 0x00004000 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR0_SSCAN_RDY_ERROR___S 14 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR0_LONG_FFT_RPT_ERROR___M 0x00002000 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR0_LONG_FFT_RPT_ERROR___S 13 +#define PHYA_RXTD_ERROR_STATUS_L__FFT_DONE_TIMEOUT_ERROR___M 0x00001000 +#define PHYA_RXTD_ERROR_STATUS_L__FFT_DONE_TIMEOUT_ERROR___S 12 +#define PHYA_RXTD_ERROR_STATUS_L__PPM_TS_ERROR___M 0x00000800 +#define PHYA_RXTD_ERROR_STATUS_L__PPM_TS_ERROR___S 11 +#define PHYA_RXTD_ERROR_STATUS_L__VSRC_FIFO_ERROR___M 0x00000400 +#define PHYA_RXTD_ERROR_STATUS_L__VSRC_FIFO_ERROR___S 10 +#define PHYA_RXTD_ERROR_STATUS_L__RXTD_FFT_START_ERROR___M 0x00000200 +#define PHYA_RXTD_ERROR_STATUS_L__RXTD_FFT_START_ERROR___S 9 +#define PHYA_RXTD_ERROR_STATUS_L__SIZING_ERROR___M 0x00000100 +#define PHYA_RXTD_ERROR_STATUS_L__SIZING_ERROR___S 8 +#define PHYA_RXTD_ERROR_STATUS_L__NFCAL_ERROR___M 0x00000080 +#define PHYA_RXTD_ERROR_STATUS_L__NFCAL_ERROR___S 7 +#define PHYA_RXTD_ERROR_STATUS_L__RTT_ERROR___M 0x00000040 +#define PHYA_RXTD_ERROR_STATUS_L__RTT_ERROR___S 6 +#define PHYA_RXTD_ERROR_STATUS_L__CCK_DATA_ERROR___M 0x00000020 +#define PHYA_RXTD_ERROR_STATUS_L__CCK_DATA_ERROR___S 5 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR0_SHORT_FFT_RPT_ERROR___M 0x00000010 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR0_SHORT_FFT_RPT_ERROR___S 4 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR0_RADAR_DONE_ERROR___M 0x00000008 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR0_RADAR_DONE_ERROR___S 3 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR0_RADAR_DET_ERROR___M 0x00000004 +#define PHYA_RXTD_ERROR_STATUS_L__RADAR0_RADAR_DET_ERROR___S 2 +#define PHYA_RXTD_ERROR_STATUS_L__SYM_ERROR___M 0x00000002 +#define PHYA_RXTD_ERROR_STATUS_L__SYM_ERROR___S 1 +#define PHYA_RXTD_ERROR_STATUS_L__PKT_ERROR___M 0x00000001 +#define PHYA_RXTD_ERROR_STATUS_L__PKT_ERROR___S 0 +#define PHYA_RXTD_ERROR_STATUS_L___M 0x00FFFFFF +#define PHYA_RXTD_ERROR_STATUS_L___S 0 + +#define PHYA_RXTD_ERROR_MASK_L (0x003A0030) +#define PHYA_RXTD_ERROR_MASK_L___RWC QCSR_REG_RW +#define PHYA_RXTD_ERROR_MASK_L___POR 0x00000000 +#define PHYA_RXTD_ERROR_MASK_L__RADAR1_RADAR_TIMEOUT_ERROR_MASK___POR 0x0 +#define PHYA_RXTD_ERROR_MASK_L__RADAR1_SSCAN_DONE_ERROR_MASK___POR 0x0 +#define PHYA_RXTD_ERROR_MASK_L__RADAR1_SSCAN_RDY_ERROR_MASK___POR 0x0 +#define PHYA_RXTD_ERROR_MASK_L__RADAR1_LONG_FFT_RPT_ERROR_MASK___POR 0x0 +#define PHYA_RXTD_ERROR_MASK_L__RADAR1_SHORT_FFT_RPT_ERROR_MASK___POR 0x0 +#define PHYA_RXTD_ERROR_MASK_L__RADAR1_RADAR_DONE_ERROR_MASK___POR 0x0 +#define PHYA_RXTD_ERROR_MASK_L__RADAR1_RADAR_DET_ERROR_MASK___POR 0x0 +#define PHYA_RXTD_ERROR_MASK_L__RADAR0_RADAR_TIMEOUT_ERROR_MASK___POR 0x0 +#define PHYA_RXTD_ERROR_MASK_L__RADAR0_SSCAN_DONE_ERROR_MASK___POR 0x0 +#define PHYA_RXTD_ERROR_MASK_L__RADAR0_SSCAN_RDY_ERROR_MASK___POR 0x0 +#define PHYA_RXTD_ERROR_MASK_L__RADAR0_LONG_FFT_RPT_ERROR_MASK___POR 0x0 +#define PHYA_RXTD_ERROR_MASK_L__FFT_DONE_TIMEOUT_ERROR_MASK___POR 0x0 +#define PHYA_RXTD_ERROR_MASK_L__PPM_TS_ERROR_MASK___POR 0x0 +#define PHYA_RXTD_ERROR_MASK_L__VSRC_FIFO_ERROR_MASK___POR 0x0 +#define PHYA_RXTD_ERROR_MASK_L__RXTD_FFT_START_ERROR_MASK___POR 0x0 +#define PHYA_RXTD_ERROR_MASK_L__SIZING_MASK___POR 0x0 +#define PHYA_RXTD_ERROR_MASK_L__NFCAL_MASK___POR 0x0 +#define PHYA_RXTD_ERROR_MASK_L__RTT_MASK___POR 0x0 +#define PHYA_RXTD_ERROR_MASK_L__CCK_DATA_MASK___POR 0x0 +#define PHYA_RXTD_ERROR_MASK_L__RADAR0_SHORT_FFT_RPT_ERROR_MASK___POR 0x0 +#define PHYA_RXTD_ERROR_MASK_L__RADAR0_RADAR_DONE_ERROR_MASK___POR 0x0 +#define PHYA_RXTD_ERROR_MASK_L__RADAR0_RADAR_DET_ERROR_MASK___POR 0x0 +#define PHYA_RXTD_ERROR_MASK_L__SYM_ERROR_MASK___POR 0x0 +#define PHYA_RXTD_ERROR_MASK_L__PKT_ERROR_MASK___POR 0x0 +#define PHYA_RXTD_ERROR_MASK_L__RADAR1_RADAR_TIMEOUT_ERROR_MASK___M 0x00800000 +#define PHYA_RXTD_ERROR_MASK_L__RADAR1_RADAR_TIMEOUT_ERROR_MASK___S 23 +#define PHYA_RXTD_ERROR_MASK_L__RADAR1_SSCAN_DONE_ERROR_MASK___M 0x00400000 +#define PHYA_RXTD_ERROR_MASK_L__RADAR1_SSCAN_DONE_ERROR_MASK___S 22 +#define PHYA_RXTD_ERROR_MASK_L__RADAR1_SSCAN_RDY_ERROR_MASK___M 0x00200000 +#define PHYA_RXTD_ERROR_MASK_L__RADAR1_SSCAN_RDY_ERROR_MASK___S 21 +#define PHYA_RXTD_ERROR_MASK_L__RADAR1_LONG_FFT_RPT_ERROR_MASK___M 0x00100000 +#define PHYA_RXTD_ERROR_MASK_L__RADAR1_LONG_FFT_RPT_ERROR_MASK___S 20 +#define PHYA_RXTD_ERROR_MASK_L__RADAR1_SHORT_FFT_RPT_ERROR_MASK___M 0x00080000 +#define PHYA_RXTD_ERROR_MASK_L__RADAR1_SHORT_FFT_RPT_ERROR_MASK___S 19 +#define PHYA_RXTD_ERROR_MASK_L__RADAR1_RADAR_DONE_ERROR_MASK___M 0x00040000 +#define PHYA_RXTD_ERROR_MASK_L__RADAR1_RADAR_DONE_ERROR_MASK___S 18 +#define PHYA_RXTD_ERROR_MASK_L__RADAR1_RADAR_DET_ERROR_MASK___M 0x00020000 +#define PHYA_RXTD_ERROR_MASK_L__RADAR1_RADAR_DET_ERROR_MASK___S 17 +#define PHYA_RXTD_ERROR_MASK_L__RADAR0_RADAR_TIMEOUT_ERROR_MASK___M 0x00010000 +#define PHYA_RXTD_ERROR_MASK_L__RADAR0_RADAR_TIMEOUT_ERROR_MASK___S 16 +#define PHYA_RXTD_ERROR_MASK_L__RADAR0_SSCAN_DONE_ERROR_MASK___M 0x00008000 +#define PHYA_RXTD_ERROR_MASK_L__RADAR0_SSCAN_DONE_ERROR_MASK___S 15 +#define PHYA_RXTD_ERROR_MASK_L__RADAR0_SSCAN_RDY_ERROR_MASK___M 0x00004000 +#define PHYA_RXTD_ERROR_MASK_L__RADAR0_SSCAN_RDY_ERROR_MASK___S 14 +#define PHYA_RXTD_ERROR_MASK_L__RADAR0_LONG_FFT_RPT_ERROR_MASK___M 0x00002000 +#define PHYA_RXTD_ERROR_MASK_L__RADAR0_LONG_FFT_RPT_ERROR_MASK___S 13 +#define PHYA_RXTD_ERROR_MASK_L__FFT_DONE_TIMEOUT_ERROR_MASK___M 0x00001000 +#define PHYA_RXTD_ERROR_MASK_L__FFT_DONE_TIMEOUT_ERROR_MASK___S 12 +#define PHYA_RXTD_ERROR_MASK_L__PPM_TS_ERROR_MASK___M 0x00000800 +#define PHYA_RXTD_ERROR_MASK_L__PPM_TS_ERROR_MASK___S 11 +#define PHYA_RXTD_ERROR_MASK_L__VSRC_FIFO_ERROR_MASK___M 0x00000400 +#define PHYA_RXTD_ERROR_MASK_L__VSRC_FIFO_ERROR_MASK___S 10 +#define PHYA_RXTD_ERROR_MASK_L__RXTD_FFT_START_ERROR_MASK___M 0x00000200 +#define PHYA_RXTD_ERROR_MASK_L__RXTD_FFT_START_ERROR_MASK___S 9 +#define PHYA_RXTD_ERROR_MASK_L__SIZING_MASK___M 0x00000100 +#define PHYA_RXTD_ERROR_MASK_L__SIZING_MASK___S 8 +#define PHYA_RXTD_ERROR_MASK_L__NFCAL_MASK___M 0x00000080 +#define PHYA_RXTD_ERROR_MASK_L__NFCAL_MASK___S 7 +#define PHYA_RXTD_ERROR_MASK_L__RTT_MASK___M 0x00000040 +#define PHYA_RXTD_ERROR_MASK_L__RTT_MASK___S 6 +#define PHYA_RXTD_ERROR_MASK_L__CCK_DATA_MASK___M 0x00000020 +#define PHYA_RXTD_ERROR_MASK_L__CCK_DATA_MASK___S 5 +#define PHYA_RXTD_ERROR_MASK_L__RADAR0_SHORT_FFT_RPT_ERROR_MASK___M 0x00000010 +#define PHYA_RXTD_ERROR_MASK_L__RADAR0_SHORT_FFT_RPT_ERROR_MASK___S 4 +#define PHYA_RXTD_ERROR_MASK_L__RADAR0_RADAR_DONE_ERROR_MASK___M 0x00000008 +#define PHYA_RXTD_ERROR_MASK_L__RADAR0_RADAR_DONE_ERROR_MASK___S 3 +#define PHYA_RXTD_ERROR_MASK_L__RADAR0_RADAR_DET_ERROR_MASK___M 0x00000004 +#define PHYA_RXTD_ERROR_MASK_L__RADAR0_RADAR_DET_ERROR_MASK___S 2 +#define PHYA_RXTD_ERROR_MASK_L__SYM_ERROR_MASK___M 0x00000002 +#define PHYA_RXTD_ERROR_MASK_L__SYM_ERROR_MASK___S 1 +#define PHYA_RXTD_ERROR_MASK_L__PKT_ERROR_MASK___M 0x00000001 +#define PHYA_RXTD_ERROR_MASK_L__PKT_ERROR_MASK___S 0 +#define PHYA_RXTD_ERROR_MASK_L___M 0x00FFFFFF +#define PHYA_RXTD_ERROR_MASK_L___S 0 + +#define PHYA_RXTD_GEN_CONFIG_L (0x003A0038) +#define PHYA_RXTD_GEN_CONFIG_L___RWC QCSR_REG_RW +#define PHYA_RXTD_GEN_CONFIG_L___POR 0x00000100 +#define PHYA_RXTD_GEN_CONFIG_L__ENABLE_RESTART___POR 0x0 +#define PHYA_RXTD_GEN_CONFIG_L__DISABLE_AGC_TO_A2___POR 0x0 +#define PHYA_RXTD_GEN_CONFIG_L__DYN_OFDM_CCK_MODE___POR 0x1 +#define PHYA_RXTD_GEN_CONFIG_L__ENABLE_RECEIVER___POR 0x0 +#define PHYA_RXTD_GEN_CONFIG_L__ENABLE_RESTART___M 0x01000000 +#define PHYA_RXTD_GEN_CONFIG_L__ENABLE_RESTART___S 24 +#define PHYA_RXTD_GEN_CONFIG_L__DISABLE_AGC_TO_A2___M 0x00010000 +#define PHYA_RXTD_GEN_CONFIG_L__DISABLE_AGC_TO_A2___S 16 +#define PHYA_RXTD_GEN_CONFIG_L__DYN_OFDM_CCK_MODE___M 0x00000100 +#define PHYA_RXTD_GEN_CONFIG_L__DYN_OFDM_CCK_MODE___S 8 +#define PHYA_RXTD_GEN_CONFIG_L__ENABLE_RECEIVER___M 0x00000001 +#define PHYA_RXTD_GEN_CONFIG_L__ENABLE_RECEIVER___S 0 +#define PHYA_RXTD_GEN_CONFIG_L___M 0x01010101 +#define PHYA_RXTD_GEN_CONFIG_L___S 0 + +#define PHYA_RXTD_GEN_CONTROLS_L (0x003A0040) +#define PHYA_RXTD_GEN_CONTROLS_L___RWC QCSR_REG_RW +#define PHYA_RXTD_GEN_CONTROLS_L___POR 0x00000000 +#define PHYA_RXTD_GEN_CONTROLS_L__SHUTDOWN___POR 0x0 +#define PHYA_RXTD_GEN_CONTROLS_L__DEFER___POR 0x0 +#define PHYA_RXTD_GEN_CONTROLS_L__FINDNXTFRAME___POR 0x0 +#define PHYA_RXTD_GEN_CONTROLS_L__SHUTDOWN___M 0x00000004 +#define PHYA_RXTD_GEN_CONTROLS_L__SHUTDOWN___S 2 +#define PHYA_RXTD_GEN_CONTROLS_L__DEFER___M 0x00000002 +#define PHYA_RXTD_GEN_CONTROLS_L__DEFER___S 1 +#define PHYA_RXTD_GEN_CONTROLS_L__FINDNXTFRAME___M 0x00000001 +#define PHYA_RXTD_GEN_CONTROLS_L__FINDNXTFRAME___S 0 +#define PHYA_RXTD_GEN_CONTROLS_L___M 0x00000007 +#define PHYA_RXTD_GEN_CONTROLS_L___S 0 + +#define PHYA_RXTD_MIXER_CONFIG_L (0x003A0048) +#define PHYA_RXTD_MIXER_CONFIG_L___RWC QCSR_REG_RW +#define PHYA_RXTD_MIXER_CONFIG_L___POR 0x00000004 +#define PHYA_RXTD_MIXER_CONFIG_L__ALT_DIG_MIX_MODE_165___POR 0x1 +#define PHYA_RXTD_MIXER_CONFIG_L__DYN_PRI_CHN_EXT80___POR 0x0 +#define PHYA_RXTD_MIXER_CONFIG_L__ALT_DIG_MIX_MODE_165___M 0x00000004 +#define PHYA_RXTD_MIXER_CONFIG_L__ALT_DIG_MIX_MODE_165___S 2 +#define PHYA_RXTD_MIXER_CONFIG_L__DYN_PRI_CHN_EXT80___M 0x00000003 +#define PHYA_RXTD_MIXER_CONFIG_L__DYN_PRI_CHN_EXT80___S 0 +#define PHYA_RXTD_MIXER_CONFIG_L___M 0x00000007 +#define PHYA_RXTD_MIXER_CONFIG_L___S 0 + +#define PHYA_RXTD_PDBWC_WEAK_LOW_L (0x003A0050) +#define PHYA_RXTD_PDBWC_WEAK_LOW_L___RWC QCSR_REG_RW +#define PHYA_RXTD_PDBWC_WEAK_LOW_L___POR 0x00000254 +#define PHYA_RXTD_PDBWC_WEAK_LOW_L__PD_ACC_THR_LOW___POR 0x01 +#define PHYA_RXTD_PDBWC_WEAK_LOW_L__PD_POW_THR_LOW___POR 0x05 +#define PHYA_RXTD_PDBWC_WEAK_LOW_L__PD_THR_LOW___POR 0x4 +#define PHYA_RXTD_PDBWC_WEAK_LOW_L__PD_ACC_THR_LOW___M 0x00003E00 +#define PHYA_RXTD_PDBWC_WEAK_LOW_L__PD_ACC_THR_LOW___S 9 +#define PHYA_RXTD_PDBWC_WEAK_LOW_L__PD_POW_THR_LOW___M 0x000001F0 +#define PHYA_RXTD_PDBWC_WEAK_LOW_L__PD_POW_THR_LOW___S 4 +#define PHYA_RXTD_PDBWC_WEAK_LOW_L__PD_THR_LOW___M 0x0000000F +#define PHYA_RXTD_PDBWC_WEAK_LOW_L__PD_THR_LOW___S 0 +#define PHYA_RXTD_PDBWC_WEAK_LOW_L___M 0x00003FFF +#define PHYA_RXTD_PDBWC_WEAK_LOW_L___S 0 + +#define PHYA_RXTD_PDBWC_WEAK_L (0x003A0058) +#define PHYA_RXTD_PDBWC_WEAK_L___RWC QCSR_REG_RW +#define PHYA_RXTD_PDBWC_WEAK_L___POR 0x00000258 +#define PHYA_RXTD_PDBWC_WEAK_L__PD_ACC_THR_WEAK___POR 0x01 +#define PHYA_RXTD_PDBWC_WEAK_L__PD_POW_THR_WEAK___POR 0x05 +#define PHYA_RXTD_PDBWC_WEAK_L__PD_THR_WEAK___POR 0x8 +#define PHYA_RXTD_PDBWC_WEAK_L__PD_ACC_THR_WEAK___M 0x00003E00 +#define PHYA_RXTD_PDBWC_WEAK_L__PD_ACC_THR_WEAK___S 9 +#define PHYA_RXTD_PDBWC_WEAK_L__PD_POW_THR_WEAK___M 0x000001F0 +#define PHYA_RXTD_PDBWC_WEAK_L__PD_POW_THR_WEAK___S 4 +#define PHYA_RXTD_PDBWC_WEAK_L__PD_THR_WEAK___M 0x0000000F +#define PHYA_RXTD_PDBWC_WEAK_L__PD_THR_WEAK___S 0 +#define PHYA_RXTD_PDBWC_WEAK_L___M 0x00003FFF +#define PHYA_RXTD_PDBWC_WEAK_L___S 0 + +#define PHYA_RXTD_PDBWC_STRONG_L (0x003A0060) +#define PHYA_RXTD_PDBWC_STRONG_L___RWC QCSR_REG_RW +#define PHYA_RXTD_PDBWC_STRONG_L___POR 0x00000258 +#define PHYA_RXTD_PDBWC_STRONG_L__PD_ACC_THR_STRONG___POR 0x01 +#define PHYA_RXTD_PDBWC_STRONG_L__PD_POW_THR_STRONG___POR 0x05 +#define PHYA_RXTD_PDBWC_STRONG_L__PD_THR_STRONG___POR 0x8 +#define PHYA_RXTD_PDBWC_STRONG_L__PD_ACC_THR_STRONG___M 0x00003E00 +#define PHYA_RXTD_PDBWC_STRONG_L__PD_ACC_THR_STRONG___S 9 +#define PHYA_RXTD_PDBWC_STRONG_L__PD_POW_THR_STRONG___M 0x000001F0 +#define PHYA_RXTD_PDBWC_STRONG_L__PD_POW_THR_STRONG___S 4 +#define PHYA_RXTD_PDBWC_STRONG_L__PD_THR_STRONG___M 0x0000000F +#define PHYA_RXTD_PDBWC_STRONG_L__PD_THR_STRONG___S 0 +#define PHYA_RXTD_PDBWC_STRONG_L___M 0x00003FFF +#define PHYA_RXTD_PDBWC_STRONG_L___S 0 + +#define PHYA_RXTD_PDBWC_L (0x003A0068) +#define PHYA_RXTD_PDBWC_L___RWC QCSR_REG_RW +#define PHYA_RXTD_PDBWC_L___POR 0x00000001 +#define PHYA_RXTD_PDBWC_L__PD_WIN_LEN___POR 0x01 +#define PHYA_RXTD_PDBWC_L__PD_WIN_LEN___M 0x0000001F +#define PHYA_RXTD_PDBWC_L__PD_WIN_LEN___S 0 +#define PHYA_RXTD_PDBWC_L___M 0x0000001F +#define PHYA_RXTD_PDBWC_L___S 0 + +#define PHYA_RXTD_LEAKYB_CTRL_L (0x003A0070) +#define PHYA_RXTD_LEAKYB_CTRL_L___RWC QCSR_REG_RW +#define PHYA_RXTD_LEAKYB_CTRL_L___POR 0x01C3FFFF +#define PHYA_RXTD_LEAKYB_CTRL_L__LB_ALPHA_SHIFT___POR 0x07 +#define PHYA_RXTD_LEAKYB_CTRL_L__LB_DC_CAP___POR 0x01FFFF +#define PHYA_RXTD_LEAKYB_CTRL_L__LB_EN___POR 0x1 +#define PHYA_RXTD_LEAKYB_CTRL_L__LB_ALPHA_SHIFT___M 0x07C00000 +#define PHYA_RXTD_LEAKYB_CTRL_L__LB_ALPHA_SHIFT___S 22 +#define PHYA_RXTD_LEAKYB_CTRL_L__LB_DC_CAP___M 0x003FFFFE +#define PHYA_RXTD_LEAKYB_CTRL_L__LB_DC_CAP___S 1 +#define PHYA_RXTD_LEAKYB_CTRL_L__LB_EN___M 0x00000001 +#define PHYA_RXTD_LEAKYB_CTRL_L__LB_EN___S 0 +#define PHYA_RXTD_LEAKYB_CTRL_L___M 0x07FFFFFF +#define PHYA_RXTD_LEAKYB_CTRL_L___S 0 + +#define PHYA_RXTD_ADCPWR_ADJ_1_L (0x003A0078) +#define PHYA_RXTD_ADCPWR_ADJ_1_L___RWC QCSR_REG_RW +#define PHYA_RXTD_ADCPWR_ADJ_1_L___POR 0x00014014 +#define PHYA_RXTD_ADCPWR_ADJ_1_L__ADC_PWR800NS_ADJ_DB16___POR 0x014 +#define PHYA_RXTD_ADCPWR_ADJ_1_L__ADC_PWR400NS_ADJ_DB16___POR 0x014 +#define PHYA_RXTD_ADCPWR_ADJ_1_L__ADC_PWR800NS_ADJ_DB16___M 0x00FFF000 +#define PHYA_RXTD_ADCPWR_ADJ_1_L__ADC_PWR800NS_ADJ_DB16___S 12 +#define PHYA_RXTD_ADCPWR_ADJ_1_L__ADC_PWR400NS_ADJ_DB16___M 0x00000FFF +#define PHYA_RXTD_ADCPWR_ADJ_1_L__ADC_PWR400NS_ADJ_DB16___S 0 +#define PHYA_RXTD_ADCPWR_ADJ_1_L___M 0x00FFFFFF +#define PHYA_RXTD_ADCPWR_ADJ_1_L___S 0 + +#define PHYA_RXTD_ADCPWR_ADJ_2_L (0x003A0080) +#define PHYA_RXTD_ADCPWR_ADJ_2_L___RWC QCSR_REG_RW +#define PHYA_RXTD_ADCPWR_ADJ_2_L___POR 0x00000014 +#define PHYA_RXTD_ADCPWR_ADJ_2_L__ADC_PWR1600NS_ADJ_DB16___POR 0x014 +#define PHYA_RXTD_ADCPWR_ADJ_2_L__ADC_PWR1600NS_ADJ_DB16___M 0x00000FFF +#define PHYA_RXTD_ADCPWR_ADJ_2_L__ADC_PWR1600NS_ADJ_DB16___S 0 +#define PHYA_RXTD_ADCPWR_ADJ_2_L___M 0x00000FFF +#define PHYA_RXTD_ADCPWR_ADJ_2_L___S 0 + +#define PHYA_RXTD_PRI20PWR_ADJ_0_L (0x003A0088) +#define PHYA_RXTD_PRI20PWR_ADJ_0_L___RWC QCSR_REG_RW +#define PHYA_RXTD_PRI20PWR_ADJ_0_L___POR 0x00000000 +#define PHYA_RXTD_PRI20PWR_ADJ_0_L__PRI20_PWR1600NS_ADJ_DB16___POR 0x000 +#define PHYA_RXTD_PRI20PWR_ADJ_0_L__PRI20_PWR800NS_ADJ_DB16___POR 0x000 +#define PHYA_RXTD_PRI20PWR_ADJ_0_L__PRI20_PWR1600NS_ADJ_DB16___M 0x00FFF000 +#define PHYA_RXTD_PRI20PWR_ADJ_0_L__PRI20_PWR1600NS_ADJ_DB16___S 12 +#define PHYA_RXTD_PRI20PWR_ADJ_0_L__PRI20_PWR800NS_ADJ_DB16___M 0x00000FFF +#define PHYA_RXTD_PRI20PWR_ADJ_0_L__PRI20_PWR800NS_ADJ_DB16___S 0 +#define PHYA_RXTD_PRI20PWR_ADJ_0_L___M 0x00FFFFFF +#define PHYA_RXTD_PRI20PWR_ADJ_0_L___S 0 + +#define PHYA_RXTD_NOISE_FLOOR_PWR_ADJ_L (0x003A0090) +#define PHYA_RXTD_NOISE_FLOOR_PWR_ADJ_L___RWC QCSR_REG_RW +#define PHYA_RXTD_NOISE_FLOOR_PWR_ADJ_L___POR 0x00000000 +#define PHYA_RXTD_NOISE_FLOOR_PWR_ADJ_L__FIR_PWR6400NS_ADJ_DB16___POR 0x000 +#define PHYA_RXTD_NOISE_FLOOR_PWR_ADJ_L__FIR_PWR6400NS_ADJ_DB16___M 0x00000FFF +#define PHYA_RXTD_NOISE_FLOOR_PWR_ADJ_L__FIR_PWR6400NS_ADJ_DB16___S 0 +#define PHYA_RXTD_NOISE_FLOOR_PWR_ADJ_L___M 0x00000FFF +#define PHYA_RXTD_NOISE_FLOOR_PWR_ADJ_L___S 0 + +#define PHYA_RXTD_CCA_PWR_ADJ_L (0x003A0098) +#define PHYA_RXTD_CCA_PWR_ADJ_L___RWC QCSR_REG_RW +#define PHYA_RXTD_CCA_PWR_ADJ_L___POR 0x00000000 +#define PHYA_RXTD_CCA_PWR_ADJ_L__FIR_PWR800NS_ADJ_DB16___POR 0x000 +#define PHYA_RXTD_CCA_PWR_ADJ_L__FIR_PWR800NS_ADJ_DB16___M 0x00000FFF +#define PHYA_RXTD_CCA_PWR_ADJ_L__FIR_PWR800NS_ADJ_DB16___S 0 +#define PHYA_RXTD_CCA_PWR_ADJ_L___M 0x00000FFF +#define PHYA_RXTD_CCA_PWR_ADJ_L___S 0 + +#define PHYA_RXTD_PKDET_KRELPWR_L (0x003A00A0) +#define PHYA_RXTD_PKDET_KRELPWR_L___RWC QCSR_REG_RW +#define PHYA_RXTD_PKDET_KRELPWR_L___POR 0x0763B1EC +#define PHYA_RXTD_PKDET_KRELPWR_L__KRELPOW_LOW_DB2___POR 0x1D8 +#define PHYA_RXTD_PKDET_KRELPWR_L__KRELPOW_DB2___POR 0x1D8 +#define PHYA_RXTD_PKDET_KRELPWR_L__KRELPOW_STR_DB2___POR 0x1EC +#define PHYA_RXTD_PKDET_KRELPWR_L__KRELPOW_LOW_DB2___M 0x07FC0000 +#define PHYA_RXTD_PKDET_KRELPWR_L__KRELPOW_LOW_DB2___S 18 +#define PHYA_RXTD_PKDET_KRELPWR_L__KRELPOW_DB2___M 0x0003FE00 +#define PHYA_RXTD_PKDET_KRELPWR_L__KRELPOW_DB2___S 9 +#define PHYA_RXTD_PKDET_KRELPWR_L__KRELPOW_STR_DB2___M 0x000001FF +#define PHYA_RXTD_PKDET_KRELPWR_L__KRELPOW_STR_DB2___S 0 +#define PHYA_RXTD_PKDET_KRELPWR_L___M 0x07FFFFFF +#define PHYA_RXTD_PKDET_KRELPWR_L___S 0 + +#define PHYA_RXTD_PKDET_KPRIPWR_L (0x003A00A8) +#define PHYA_RXTD_PKDET_KPRIPWR_L___RWC QCSR_REG_RW +#define PHYA_RXTD_PKDET_KPRIPWR_L___POR 0x0673259C +#define PHYA_RXTD_PKDET_KPRIPWR_L__KPRIPOW_LOW_DB2___POR 0x19C +#define PHYA_RXTD_PKDET_KPRIPWR_L__KPRIPOW_DB2___POR 0x192 +#define PHYA_RXTD_PKDET_KPRIPWR_L__KPRIPOW_STR_DB2___POR 0x19C +#define PHYA_RXTD_PKDET_KPRIPWR_L__KPRIPOW_LOW_DB2___M 0x07FC0000 +#define PHYA_RXTD_PKDET_KPRIPWR_L__KPRIPOW_LOW_DB2___S 18 +#define PHYA_RXTD_PKDET_KPRIPWR_L__KPRIPOW_DB2___M 0x0003FE00 +#define PHYA_RXTD_PKDET_KPRIPWR_L__KPRIPOW_DB2___S 9 +#define PHYA_RXTD_PKDET_KPRIPWR_L__KPRIPOW_STR_DB2___M 0x000001FF +#define PHYA_RXTD_PKDET_KPRIPWR_L__KPRIPOW_STR_DB2___S 0 +#define PHYA_RXTD_PKDET_KPRIPWR_L___M 0x07FFFFFF +#define PHYA_RXTD_PKDET_KPRIPWR_L___S 0 + +#define PHYA_RXTD_PKDET_KRELSTEP_L (0x003A00B0) +#define PHYA_RXTD_PKDET_KRELSTEP_L___RWC QCSR_REG_RW +#define PHYA_RXTD_PKDET_KRELSTEP_L___POR 0x0003399C +#define PHYA_RXTD_PKDET_KRELSTEP_L__KRELSTEP_LOW_DB2___POR 0x19C +#define PHYA_RXTD_PKDET_KRELSTEP_L__KRELSTEP_DB2___POR 0x19C +#define PHYA_RXTD_PKDET_KRELSTEP_L__KRELSTEP_LOW_DB2___M 0x0003FE00 +#define PHYA_RXTD_PKDET_KRELSTEP_L__KRELSTEP_LOW_DB2___S 9 +#define PHYA_RXTD_PKDET_KRELSTEP_L__KRELSTEP_DB2___M 0x000001FF +#define PHYA_RXTD_PKDET_KRELSTEP_L__KRELSTEP_DB2___S 0 +#define PHYA_RXTD_PKDET_KRELSTEP_L___M 0x0003FFFF +#define PHYA_RXTD_PKDET_KRELSTEP_L___S 0 + +#define PHYA_RXTD_PKDET_KPRISTEP_L (0x003A00B8) +#define PHYA_RXTD_PKDET_KPRISTEP_L___RWC QCSR_REG_RW +#define PHYA_RXTD_PKDET_KPRISTEP_L___POR 0x00033805 +#define PHYA_RXTD_PKDET_KPRISTEP_L__KPRISTEP_LOW_DB2___POR 0x19C +#define PHYA_RXTD_PKDET_KPRISTEP_L__KPRISTEP_DB2___POR 0x005 +#define PHYA_RXTD_PKDET_KPRISTEP_L__KPRISTEP_LOW_DB2___M 0x0003FE00 +#define PHYA_RXTD_PKDET_KPRISTEP_L__KPRISTEP_LOW_DB2___S 9 +#define PHYA_RXTD_PKDET_KPRISTEP_L__KPRISTEP_DB2___M 0x000001FF +#define PHYA_RXTD_PKDET_KPRISTEP_L__KPRISTEP_DB2___S 0 +#define PHYA_RXTD_PKDET_KPRISTEP_L___M 0x0003FFFF +#define PHYA_RXTD_PKDET_KPRISTEP_L___S 0 + +#define PHYA_RXTD_PKDET_PARAMS_L (0x003A00C0) +#define PHYA_RXTD_PKDET_PARAMS_L___RWC QCSR_REG_RW +#define PHYA_RXTD_PKDET_PARAMS_L___POR 0x12020020 +#define PHYA_RXTD_PKDET_PARAMS_L__YCOKMAX_L___POR 0x2 +#define PHYA_RXTD_PKDET_PARAMS_L__YCOKMAX___POR 0x2 +#define PHYA_RXTD_PKDET_PARAMS_L__GC_SETTLING_THR_L___POR 0x020 +#define PHYA_RXTD_PKDET_PARAMS_L__GC_SETTLING_THR___POR 0x020 +#define PHYA_RXTD_PKDET_PARAMS_L__YCOKMAX_L___M 0x38000000 +#define PHYA_RXTD_PKDET_PARAMS_L__YCOKMAX_L___S 27 +#define PHYA_RXTD_PKDET_PARAMS_L__YCOKMAX___M 0x07000000 +#define PHYA_RXTD_PKDET_PARAMS_L__YCOKMAX___S 24 +#define PHYA_RXTD_PKDET_PARAMS_L__GC_SETTLING_THR_L___M 0x00FFF000 +#define PHYA_RXTD_PKDET_PARAMS_L__GC_SETTLING_THR_L___S 12 +#define PHYA_RXTD_PKDET_PARAMS_L__GC_SETTLING_THR___M 0x00000FFF +#define PHYA_RXTD_PKDET_PARAMS_L__GC_SETTLING_THR___S 0 +#define PHYA_RXTD_PKDET_PARAMS_L___M 0x3FFFFFFF +#define PHYA_RXTD_PKDET_PARAMS_L___S 0 + +#define PHYA_RXTD_RSSI_THR_L (0x003A00C8) +#define PHYA_RXTD_RSSI_THR_L___RWC QCSR_REG_RW +#define PHYA_RXTD_RSSI_THR_L___POR 0x12880AB1 +#define PHYA_RXTD_RSSI_THR_L__RSSI_THR1D_DB___POR 0x12 +#define PHYA_RXTD_RSSI_THR_L__RSSI_THR1C_DB___POR 0x88 +#define PHYA_RXTD_RSSI_THR_L__RSSI_THR1B_DB___POR 0x0A +#define PHYA_RXTD_RSSI_THR_L__RSSI_THR1A_DB___POR 0xB1 +#define PHYA_RXTD_RSSI_THR_L__RSSI_THR1D_DB___M 0xFF000000 +#define PHYA_RXTD_RSSI_THR_L__RSSI_THR1D_DB___S 24 +#define PHYA_RXTD_RSSI_THR_L__RSSI_THR1C_DB___M 0x00FF0000 +#define PHYA_RXTD_RSSI_THR_L__RSSI_THR1C_DB___S 16 +#define PHYA_RXTD_RSSI_THR_L__RSSI_THR1B_DB___M 0x0000FF00 +#define PHYA_RXTD_RSSI_THR_L__RSSI_THR1B_DB___S 8 +#define PHYA_RXTD_RSSI_THR_L__RSSI_THR1A_DB___M 0x000000FF +#define PHYA_RXTD_RSSI_THR_L__RSSI_THR1A_DB___S 0 +#define PHYA_RXTD_RSSI_THR_L___M 0xFFFFFFFF +#define PHYA_RXTD_RSSI_THR_L___S 0 + +#define PHYA_RXTD_RSSI_THR_U (0x003A00CC) +#define PHYA_RXTD_RSSI_THR_U___RWC QCSR_REG_RW +#define PHYA_RXTD_RSSI_THR_U___POR 0x0000000F +#define PHYA_RXTD_RSSI_THR_U__RSSI_LT_THR1D_EN___POR 0x1 +#define PHYA_RXTD_RSSI_THR_U__RSSI_GT_THR1C_EN___POR 0x1 +#define PHYA_RXTD_RSSI_THR_U__RSSI_GT_THR1B_EN___POR 0x1 +#define PHYA_RXTD_RSSI_THR_U__RSSI_GT_THR1A_EN___POR 0x1 +#define PHYA_RXTD_RSSI_THR_U__RSSI_LT_THR1D_EN___M 0x00000008 +#define PHYA_RXTD_RSSI_THR_U__RSSI_LT_THR1D_EN___S 3 +#define PHYA_RXTD_RSSI_THR_U__RSSI_GT_THR1C_EN___M 0x00000004 +#define PHYA_RXTD_RSSI_THR_U__RSSI_GT_THR1C_EN___S 2 +#define PHYA_RXTD_RSSI_THR_U__RSSI_GT_THR1B_EN___M 0x00000002 +#define PHYA_RXTD_RSSI_THR_U__RSSI_GT_THR1B_EN___S 1 +#define PHYA_RXTD_RSSI_THR_U__RSSI_GT_THR1A_EN___M 0x00000001 +#define PHYA_RXTD_RSSI_THR_U__RSSI_GT_THR1A_EN___S 0 +#define PHYA_RXTD_RSSI_THR_U___M 0x0000000F +#define PHYA_RXTD_RSSI_THR_U___S 0 + +#define PHYA_RXTD_TIMESTAMP_L (0x003A00D0) +#define PHYA_RXTD_TIMESTAMP_L___RWC QCSR_REG_RW +#define PHYA_RXTD_TIMESTAMP_L___POR 0x00000000 +#define PHYA_RXTD_TIMESTAMP_L__SPARE_MISC___POR 0x00000000 +#define PHYA_RXTD_TIMESTAMP_L__REGMAP_CLKGATE_N___POR 0x0 +#define PHYA_RXTD_TIMESTAMP_L__DIS_TS_RST_SLV___POR 0x0 +#define PHYA_RXTD_TIMESTAMP_L__SPARE_MISC___M 0xFFFFFFFC +#define PHYA_RXTD_TIMESTAMP_L__SPARE_MISC___S 2 +#define PHYA_RXTD_TIMESTAMP_L__REGMAP_CLKGATE_N___M 0x00000002 +#define PHYA_RXTD_TIMESTAMP_L__REGMAP_CLKGATE_N___S 1 +#define PHYA_RXTD_TIMESTAMP_L__DIS_TS_RST_SLV___M 0x00000001 +#define PHYA_RXTD_TIMESTAMP_L__DIS_TS_RST_SLV___S 0 +#define PHYA_RXTD_TIMESTAMP_L___M 0xFFFFFFFF +#define PHYA_RXTD_TIMESTAMP_L___S 0 + +#define PHYA_RXTD_RADAR_SBS_CTRL_0_L (0x003A00D8) +#define PHYA_RXTD_RADAR_SBS_CTRL_0_L___RWC QCSR_REG_RW +#define PHYA_RXTD_RADAR_SBS_CTRL_0_L___POR 0x00000000 +#define PHYA_RXTD_RADAR_SBS_CTRL_0_L__DIS_FFT_UNLOAD_GATE___POR 0x0 +#define PHYA_RXTD_RADAR_SBS_CTRL_0_L__RXTD_DP_CLKGATE_N___POR 0x0 +#define PHYA_RXTD_RADAR_SBS_CTRL_0_L__RXTD_PWR_CLKGATE_N___POR 0x0 +#define PHYA_RXTD_RADAR_SBS_CTRL_0_L__AGILE_RADAR_SELECTED___POR 0x0 +#define PHYA_RXTD_RADAR_SBS_CTRL_0_L__DIS_FFT_UNLOAD_GATE___M 0x00000008 +#define PHYA_RXTD_RADAR_SBS_CTRL_0_L__DIS_FFT_UNLOAD_GATE___S 3 +#define PHYA_RXTD_RADAR_SBS_CTRL_0_L__RXTD_DP_CLKGATE_N___M 0x00000004 +#define PHYA_RXTD_RADAR_SBS_CTRL_0_L__RXTD_DP_CLKGATE_N___S 2 +#define PHYA_RXTD_RADAR_SBS_CTRL_0_L__RXTD_PWR_CLKGATE_N___M 0x00000002 +#define PHYA_RXTD_RADAR_SBS_CTRL_0_L__RXTD_PWR_CLKGATE_N___S 1 +#define PHYA_RXTD_RADAR_SBS_CTRL_0_L__AGILE_RADAR_SELECTED___M 0x00000001 +#define PHYA_RXTD_RADAR_SBS_CTRL_0_L__AGILE_RADAR_SELECTED___S 0 +#define PHYA_RXTD_RADAR_SBS_CTRL_0_L___M 0x0000000F +#define PHYA_RXTD_RADAR_SBS_CTRL_0_L___S 0 + +#define PHYA_RXTD_RADAR_SBS_CTRL_1_L (0x003A00E0) +#define PHYA_RXTD_RADAR_SBS_CTRL_1_L___RWC QCSR_REG_RW +#define PHYA_RXTD_RADAR_SBS_CTRL_1_L___POR 0x0007E013 +#define PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_LOW_RF_GAIN_TABLE_MIN___POR 0x00 +#define PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_DEFAULT_GAIN_TABLE_MAX___POR 0x3F +#define PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_DEFAULT_GAIN_TABLE_MIN___POR 0x00 +#define PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_MAIN_ANALOG_SAT___POR 0x1 +#define PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_GAIN_TABLE_HOLD_MODE___POR 0x0 +#define PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_SWITCH_TABLE_PWR_LOW___POR 0x1 +#define PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_SWITCH_TABLE_NO_CLIP___POR 0x1 +#define PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_LOW_RF_GAIN_TABLE_MIN___M 0x1FE00000 +#define PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_LOW_RF_GAIN_TABLE_MIN___S 21 +#define PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_DEFAULT_GAIN_TABLE_MAX___M 0x001FE000 +#define PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_DEFAULT_GAIN_TABLE_MAX___S 13 +#define PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_DEFAULT_GAIN_TABLE_MIN___M 0x00001FE0 +#define PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_DEFAULT_GAIN_TABLE_MIN___S 5 +#define PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_MAIN_ANALOG_SAT___M 0x00000010 +#define PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_MAIN_ANALOG_SAT___S 4 +#define PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_GAIN_TABLE_HOLD_MODE___M 0x0000000C +#define PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_GAIN_TABLE_HOLD_MODE___S 2 +#define PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_SWITCH_TABLE_PWR_LOW___M 0x00000002 +#define PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_SWITCH_TABLE_PWR_LOW___S 1 +#define PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_SWITCH_TABLE_NO_CLIP___M 0x00000001 +#define PHYA_RXTD_RADAR_SBS_CTRL_1_L__GTC_SWITCH_TABLE_NO_CLIP___S 0 +#define PHYA_RXTD_RADAR_SBS_CTRL_1_L___M 0x1FFFFFFF +#define PHYA_RXTD_RADAR_SBS_CTRL_1_L___S 0 + +#define PHYA_RXTD_RADAR_SBS_CTRL_1_U (0x003A00E4) +#define PHYA_RXTD_RADAR_SBS_CTRL_1_U___RWC QCSR_REG_RW +#define PHYA_RXTD_RADAR_SBS_CTRL_1_U___POR 0x003F003F +#define PHYA_RXTD_RADAR_SBS_CTRL_1_U__GTC_BT_GAIN_TABLE_MIN___POR 0x00 +#define PHYA_RXTD_RADAR_SBS_CTRL_1_U__GTC_VERY_LOW_RF_GAIN_TABLE_MAX___POR 0x3F +#define PHYA_RXTD_RADAR_SBS_CTRL_1_U__GTC_VERY_LOW_RF_GAIN_TABLE_MIN___POR 0x00 +#define PHYA_RXTD_RADAR_SBS_CTRL_1_U__GTC_LOW_RF_GAIN_TABLE_MAX___POR 0x3F +#define PHYA_RXTD_RADAR_SBS_CTRL_1_U__GTC_BT_GAIN_TABLE_MIN___M 0xFF000000 +#define PHYA_RXTD_RADAR_SBS_CTRL_1_U__GTC_BT_GAIN_TABLE_MIN___S 24 +#define PHYA_RXTD_RADAR_SBS_CTRL_1_U__GTC_VERY_LOW_RF_GAIN_TABLE_MAX___M 0x00FF0000 +#define PHYA_RXTD_RADAR_SBS_CTRL_1_U__GTC_VERY_LOW_RF_GAIN_TABLE_MAX___S 16 +#define PHYA_RXTD_RADAR_SBS_CTRL_1_U__GTC_VERY_LOW_RF_GAIN_TABLE_MIN___M 0x0000FF00 +#define PHYA_RXTD_RADAR_SBS_CTRL_1_U__GTC_VERY_LOW_RF_GAIN_TABLE_MIN___S 8 +#define PHYA_RXTD_RADAR_SBS_CTRL_1_U__GTC_LOW_RF_GAIN_TABLE_MAX___M 0x000000FF +#define PHYA_RXTD_RADAR_SBS_CTRL_1_U__GTC_LOW_RF_GAIN_TABLE_MAX___S 0 +#define PHYA_RXTD_RADAR_SBS_CTRL_1_U___M 0xFFFFFFFF +#define PHYA_RXTD_RADAR_SBS_CTRL_1_U___S 0 + +#define PHYA_RXTD_RADAR_SBS_CTRL_2_L (0x003A00E8) +#define PHYA_RXTD_RADAR_SBS_CTRL_2_L___RWC QCSR_REG_RW +#define PHYA_RXTD_RADAR_SBS_CTRL_2_L___POR 0x009C402A +#define PHYA_RXTD_RADAR_SBS_CTRL_2_L__GTC_GAIN_TABLE_FORCE_VALUE___POR 0x0 +#define PHYA_RXTD_RADAR_SBS_CTRL_2_L__GTC_GAIN_TABLE_FORCE_MODE___POR 0x0 +#define PHYA_RXTD_RADAR_SBS_CTRL_2_L__GTC_GAIN_TABLE_HOLD_COUNT___POR 0x09C40 +#define PHYA_RXTD_RADAR_SBS_CTRL_2_L__GTC_BT_GAIN_TABLE_MAX___POR 0x2A +#define PHYA_RXTD_RADAR_SBS_CTRL_2_L__GTC_GAIN_TABLE_FORCE_VALUE___M 0xC0000000 +#define PHYA_RXTD_RADAR_SBS_CTRL_2_L__GTC_GAIN_TABLE_FORCE_VALUE___S 30 +#define PHYA_RXTD_RADAR_SBS_CTRL_2_L__GTC_GAIN_TABLE_FORCE_MODE___M 0x30000000 +#define PHYA_RXTD_RADAR_SBS_CTRL_2_L__GTC_GAIN_TABLE_FORCE_MODE___S 28 +#define PHYA_RXTD_RADAR_SBS_CTRL_2_L__GTC_GAIN_TABLE_HOLD_COUNT___M 0x0FFFFF00 +#define PHYA_RXTD_RADAR_SBS_CTRL_2_L__GTC_GAIN_TABLE_HOLD_COUNT___S 8 +#define PHYA_RXTD_RADAR_SBS_CTRL_2_L__GTC_BT_GAIN_TABLE_MAX___M 0x000000FF +#define PHYA_RXTD_RADAR_SBS_CTRL_2_L__GTC_BT_GAIN_TABLE_MAX___S 0 +#define PHYA_RXTD_RADAR_SBS_CTRL_2_L___M 0xFFFFFFFF +#define PHYA_RXTD_RADAR_SBS_CTRL_2_L___S 0 + +#define PHYA_RXTD_HT_STF_AGC_CTRL_1_L (0x003A00F0) +#define PHYA_RXTD_HT_STF_AGC_CTRL_1_L___RWC QCSR_REG_RW +#define PHYA_RXTD_HT_STF_AGC_CTRL_1_L___POR 0x01800800 +#define PHYA_RXTD_HT_STF_AGC_CTRL_1_L__AGC_HT_STF_ENA___POR 0x1 +#define PHYA_RXTD_HT_STF_AGC_CTRL_1_L__AGC_HT_STF_MIN_LSTF_PWR_DB2___POR 0x800 +#define PHYA_RXTD_HT_STF_AGC_CTRL_1_L__AGC_HT_STF_MIN_ADC_PWR_DB2___POR 0x800 +#define PHYA_RXTD_HT_STF_AGC_CTRL_1_L__AGC_HT_STF_ENA___M 0x01000000 +#define PHYA_RXTD_HT_STF_AGC_CTRL_1_L__AGC_HT_STF_ENA___S 24 +#define PHYA_RXTD_HT_STF_AGC_CTRL_1_L__AGC_HT_STF_MIN_LSTF_PWR_DB2___M 0x00FFF000 +#define PHYA_RXTD_HT_STF_AGC_CTRL_1_L__AGC_HT_STF_MIN_LSTF_PWR_DB2___S 12 +#define PHYA_RXTD_HT_STF_AGC_CTRL_1_L__AGC_HT_STF_MIN_ADC_PWR_DB2___M 0x00000FFF +#define PHYA_RXTD_HT_STF_AGC_CTRL_1_L__AGC_HT_STF_MIN_ADC_PWR_DB2___S 0 +#define PHYA_RXTD_HT_STF_AGC_CTRL_1_L___M 0x01FFFFFF +#define PHYA_RXTD_HT_STF_AGC_CTRL_1_L___S 0 + +#define PHYA_RXTD_HT_STF_AGC_CTRL_2_L (0x003A00F8) +#define PHYA_RXTD_HT_STF_AGC_CTRL_2_L___RWC QCSR_REG_RW +#define PHYA_RXTD_HT_STF_AGC_CTRL_2_L___POR 0x01000000 +#define PHYA_RXTD_HT_STF_AGC_CTRL_2_L__AGC_HT_STF_ALLOW_GAIN_INCR___POR 0x1 +#define PHYA_RXTD_HT_STF_AGC_CTRL_2_L__AGC_HT_STF_PWR_LOW_GC_THR___POR 0x000 +#define PHYA_RXTD_HT_STF_AGC_CTRL_2_L__AGC_HT_STF_PWR_HIGH_GC_THR___POR 0x000 +#define PHYA_RXTD_HT_STF_AGC_CTRL_2_L__AGC_HT_STF_ALLOW_GAIN_INCR___M 0x01000000 +#define PHYA_RXTD_HT_STF_AGC_CTRL_2_L__AGC_HT_STF_ALLOW_GAIN_INCR___S 24 +#define PHYA_RXTD_HT_STF_AGC_CTRL_2_L__AGC_HT_STF_PWR_LOW_GC_THR___M 0x00FFF000 +#define PHYA_RXTD_HT_STF_AGC_CTRL_2_L__AGC_HT_STF_PWR_LOW_GC_THR___S 12 +#define PHYA_RXTD_HT_STF_AGC_CTRL_2_L__AGC_HT_STF_PWR_HIGH_GC_THR___M 0x00000FFF +#define PHYA_RXTD_HT_STF_AGC_CTRL_2_L__AGC_HT_STF_PWR_HIGH_GC_THR___S 0 +#define PHYA_RXTD_HT_STF_AGC_CTRL_2_L___M 0x01FFFFFF +#define PHYA_RXTD_HT_STF_AGC_CTRL_2_L___S 0 + +#define PHYA_RXTD_HT_STF_AGC_CTRL_3_L (0x003A0100) +#define PHYA_RXTD_HT_STF_AGC_CTRL_3_L___RWC QCSR_REG_RW +#define PHYA_RXTD_HT_STF_AGC_CTRL_3_L___POR 0xDA0005E4 +#define PHYA_RXTD_HT_STF_AGC_CTRL_3_L__AGC_HT_STF_ADC_SIZE_DESIRED_MAX_DB2___POR 0xDA +#define PHYA_RXTD_HT_STF_AGC_CTRL_3_L__AGC_HT_STF_SETTLING_100NS___POR 0x0005 +#define PHYA_RXTD_HT_STF_AGC_CTRL_3_L__AGC_HT_STF_WEAK_SIZE_DESIRED_DB2___POR 0xE4 +#define PHYA_RXTD_HT_STF_AGC_CTRL_3_L__AGC_HT_STF_ADC_SIZE_DESIRED_MAX_DB2___M 0xFF000000 +#define PHYA_RXTD_HT_STF_AGC_CTRL_3_L__AGC_HT_STF_ADC_SIZE_DESIRED_MAX_DB2___S 24 +#define PHYA_RXTD_HT_STF_AGC_CTRL_3_L__AGC_HT_STF_SETTLING_100NS___M 0x00FFFF00 +#define PHYA_RXTD_HT_STF_AGC_CTRL_3_L__AGC_HT_STF_SETTLING_100NS___S 8 +#define PHYA_RXTD_HT_STF_AGC_CTRL_3_L__AGC_HT_STF_WEAK_SIZE_DESIRED_DB2___M 0x000000FF +#define PHYA_RXTD_HT_STF_AGC_CTRL_3_L__AGC_HT_STF_WEAK_SIZE_DESIRED_DB2___S 0 +#define PHYA_RXTD_HT_STF_AGC_CTRL_3_L___M 0xFFFFFFFF +#define PHYA_RXTD_HT_STF_AGC_CTRL_3_L___S 0 + +#define PHYA_RXTD_HT_STF_AGC_CTRL_3_U (0x003A0104) +#define PHYA_RXTD_HT_STF_AGC_CTRL_3_U___RWC QCSR_REG_RW +#define PHYA_RXTD_HT_STF_AGC_CTRL_3_U___POR 0x000000DA +#define PHYA_RXTD_HT_STF_AGC_CTRL_3_U__AGC_HT_STF_ADC_SIZE_DESIRED_MIN_DB2___POR 0xDA +#define PHYA_RXTD_HT_STF_AGC_CTRL_3_U__AGC_HT_STF_ADC_SIZE_DESIRED_MIN_DB2___M 0x000000FF +#define PHYA_RXTD_HT_STF_AGC_CTRL_3_U__AGC_HT_STF_ADC_SIZE_DESIRED_MIN_DB2___S 0 +#define PHYA_RXTD_HT_STF_AGC_CTRL_3_U___M 0x000000FF +#define PHYA_RXTD_HT_STF_AGC_CTRL_3_U___S 0 + +#define PHYA_RXTD_AGC_GAIN_COPY_CTRL_L (0x003A0108) +#define PHYA_RXTD_AGC_GAIN_COPY_CTRL_L___RWC QCSR_REG_RW +#define PHYA_RXTD_AGC_GAIN_COPY_CTRL_L___POR 0x00000000 +#define PHYA_RXTD_AGC_GAIN_COPY_CTRL_L__ENABLE_IS_HT_STF_FOR_2ND_AGC___POR 0x0 +#define PHYA_RXTD_AGC_GAIN_COPY_CTRL_L__PPS_FINE_400___POR 0x0 +#define PHYA_RXTD_AGC_GAIN_COPY_CTRL_L__AGC_GAIN_COPY_REDUCE_DB2___POR 0x00 +#define PHYA_RXTD_AGC_GAIN_COPY_CTRL_L__AGC_GAIN_COPY_MODE___POR 0x0 +#define PHYA_RXTD_AGC_GAIN_COPY_CTRL_L__ENABLE_IS_HT_STF_FOR_2ND_AGC___M 0x00000200 +#define PHYA_RXTD_AGC_GAIN_COPY_CTRL_L__ENABLE_IS_HT_STF_FOR_2ND_AGC___S 9 +#define PHYA_RXTD_AGC_GAIN_COPY_CTRL_L__PPS_FINE_400___M 0x00000100 +#define PHYA_RXTD_AGC_GAIN_COPY_CTRL_L__PPS_FINE_400___S 8 +#define PHYA_RXTD_AGC_GAIN_COPY_CTRL_L__AGC_GAIN_COPY_REDUCE_DB2___M 0x000000FE +#define PHYA_RXTD_AGC_GAIN_COPY_CTRL_L__AGC_GAIN_COPY_REDUCE_DB2___S 1 +#define PHYA_RXTD_AGC_GAIN_COPY_CTRL_L__AGC_GAIN_COPY_MODE___M 0x00000001 +#define PHYA_RXTD_AGC_GAIN_COPY_CTRL_L__AGC_GAIN_COPY_MODE___S 0 +#define PHYA_RXTD_AGC_GAIN_COPY_CTRL_L___M 0x000003FF +#define PHYA_RXTD_AGC_GAIN_COPY_CTRL_L___S 0 + +#define PHYA_RXTD_AGC_CCA_DUP_L (0x003A0110) +#define PHYA_RXTD_AGC_CCA_DUP_L___RWC QCSR_REG_RW +#define PHYA_RXTD_AGC_CCA_DUP_L___POR 0x05208208 +#define PHYA_RXTD_AGC_CCA_DUP_L__DUPBW_EXT20_MIN_RSSI_DB___POR 0x05 +#define PHYA_RXTD_AGC_CCA_DUP_L__DUPBW_PRI20_MIN_RSSI_DB___POR 0x08 +#define PHYA_RXTD_AGC_CCA_DUP_L__DUPBW_EXT80_MAX_DELTA_DB___POR 0x08 +#define PHYA_RXTD_AGC_CCA_DUP_L__DUPBW_EXT40_MAX_DELTA_DB___POR 0x08 +#define PHYA_RXTD_AGC_CCA_DUP_L__DUPBW_EXT20_MAX_DELTA_DB___POR 0x08 +#define PHYA_RXTD_AGC_CCA_DUP_L__DUPBW_EXT20_MIN_RSSI_DB___M 0x3F000000 +#define PHYA_RXTD_AGC_CCA_DUP_L__DUPBW_EXT20_MIN_RSSI_DB___S 24 +#define PHYA_RXTD_AGC_CCA_DUP_L__DUPBW_PRI20_MIN_RSSI_DB___M 0x00FC0000 +#define PHYA_RXTD_AGC_CCA_DUP_L__DUPBW_PRI20_MIN_RSSI_DB___S 18 +#define PHYA_RXTD_AGC_CCA_DUP_L__DUPBW_EXT80_MAX_DELTA_DB___M 0x0003F000 +#define PHYA_RXTD_AGC_CCA_DUP_L__DUPBW_EXT80_MAX_DELTA_DB___S 12 +#define PHYA_RXTD_AGC_CCA_DUP_L__DUPBW_EXT40_MAX_DELTA_DB___M 0x00000FC0 +#define PHYA_RXTD_AGC_CCA_DUP_L__DUPBW_EXT40_MAX_DELTA_DB___S 6 +#define PHYA_RXTD_AGC_CCA_DUP_L__DUPBW_EXT20_MAX_DELTA_DB___M 0x0000003F +#define PHYA_RXTD_AGC_CCA_DUP_L__DUPBW_EXT20_MAX_DELTA_DB___S 0 +#define PHYA_RXTD_AGC_CCA_DUP_L___M 0x3FFFFFFF +#define PHYA_RXTD_AGC_CCA_DUP_L___S 0 + +#define PHYA_RXTD_AGC_CCA_DUP_U (0x003A0114) +#define PHYA_RXTD_AGC_CCA_DUP_U___RWC QCSR_REG_RW +#define PHYA_RXTD_AGC_CCA_DUP_U___POR 0x00000208 +#define PHYA_RXTD_AGC_CCA_DUP_U__DUPBW_EXT80_MIN_RSSI_DB___POR 0x08 +#define PHYA_RXTD_AGC_CCA_DUP_U__DUPBW_EXT40_MIN_RSSI_DB___POR 0x08 +#define PHYA_RXTD_AGC_CCA_DUP_U__DUPBW_EXT80_MIN_RSSI_DB___M 0x00000FC0 +#define PHYA_RXTD_AGC_CCA_DUP_U__DUPBW_EXT80_MIN_RSSI_DB___S 6 +#define PHYA_RXTD_AGC_CCA_DUP_U__DUPBW_EXT40_MIN_RSSI_DB___M 0x0000003F +#define PHYA_RXTD_AGC_CCA_DUP_U__DUPBW_EXT40_MIN_RSSI_DB___S 0 +#define PHYA_RXTD_AGC_CCA_DUP_U___M 0x00000FFF +#define PHYA_RXTD_AGC_CCA_DUP_U___S 0 + +#define PHYA_RXTD_AGC_CCA_THRA_L (0x003A0118) +#define PHYA_RXTD_AGC_CCA_THRA_L___RWC QCSR_REG_RW +#define PHYA_RXTD_AGC_CCA_THRA_L___POR 0x0C0C0C0C +#define PHYA_RXTD_AGC_CCA_THRA_L__THRA_CCA_EXT80_DB___POR 0x0C +#define PHYA_RXTD_AGC_CCA_THRA_L__THRA_CCA_EXT40_DB___POR 0x0C +#define PHYA_RXTD_AGC_CCA_THRA_L__THRA_CCA_EXT20_DB___POR 0x0C +#define PHYA_RXTD_AGC_CCA_THRA_L__THRA_CCA_PRI20_DB___POR 0x0C +#define PHYA_RXTD_AGC_CCA_THRA_L__THRA_CCA_EXT80_DB___M 0xFF000000 +#define PHYA_RXTD_AGC_CCA_THRA_L__THRA_CCA_EXT80_DB___S 24 +#define PHYA_RXTD_AGC_CCA_THRA_L__THRA_CCA_EXT40_DB___M 0x00FF0000 +#define PHYA_RXTD_AGC_CCA_THRA_L__THRA_CCA_EXT40_DB___S 16 +#define PHYA_RXTD_AGC_CCA_THRA_L__THRA_CCA_EXT20_DB___M 0x0000FF00 +#define PHYA_RXTD_AGC_CCA_THRA_L__THRA_CCA_EXT20_DB___S 8 +#define PHYA_RXTD_AGC_CCA_THRA_L__THRA_CCA_PRI20_DB___M 0x000000FF +#define PHYA_RXTD_AGC_CCA_THRA_L__THRA_CCA_PRI20_DB___S 0 +#define PHYA_RXTD_AGC_CCA_THRA_L___M 0xFFFFFFFF +#define PHYA_RXTD_AGC_CCA_THRA_L___S 0 + +#define PHYA_RXTD_AGC_CCA_THRB_L (0x003A0120) +#define PHYA_RXTD_AGC_CCA_THRB_L___RWC QCSR_REG_RW +#define PHYA_RXTD_AGC_CCA_THRB_L___POR 0x0C0C0C0C +#define PHYA_RXTD_AGC_CCA_THRB_L__THRB_CCA_EXT80_DB___POR 0x0C +#define PHYA_RXTD_AGC_CCA_THRB_L__THRB_CCA_EXT40_DB___POR 0x0C +#define PHYA_RXTD_AGC_CCA_THRB_L__THRB_CCA_EXT20_DB___POR 0x0C +#define PHYA_RXTD_AGC_CCA_THRB_L__THRB_CCA_PRI20_DB___POR 0x0C +#define PHYA_RXTD_AGC_CCA_THRB_L__THRB_CCA_EXT80_DB___M 0xFF000000 +#define PHYA_RXTD_AGC_CCA_THRB_L__THRB_CCA_EXT80_DB___S 24 +#define PHYA_RXTD_AGC_CCA_THRB_L__THRB_CCA_EXT40_DB___M 0x00FF0000 +#define PHYA_RXTD_AGC_CCA_THRB_L__THRB_CCA_EXT40_DB___S 16 +#define PHYA_RXTD_AGC_CCA_THRB_L__THRB_CCA_EXT20_DB___M 0x0000FF00 +#define PHYA_RXTD_AGC_CCA_THRB_L__THRB_CCA_EXT20_DB___S 8 +#define PHYA_RXTD_AGC_CCA_THRB_L__THRB_CCA_PRI20_DB___M 0x000000FF +#define PHYA_RXTD_AGC_CCA_THRB_L__THRB_CCA_PRI20_DB___S 0 +#define PHYA_RXTD_AGC_CCA_THRB_L___M 0xFFFFFFFF +#define PHYA_RXTD_AGC_CCA_THRB_L___S 0 + +#define PHYA_RXTD_AGC_CCA_THRC_L (0x003A0128) +#define PHYA_RXTD_AGC_CCA_THRC_L___RWC QCSR_REG_RW +#define PHYA_RXTD_AGC_CCA_THRC_L___POR 0x0C0C0C0C +#define PHYA_RXTD_AGC_CCA_THRC_L__THRC_CCA_EXT80_DB___POR 0x0C +#define PHYA_RXTD_AGC_CCA_THRC_L__THRC_CCA_EXT40_DB___POR 0x0C +#define PHYA_RXTD_AGC_CCA_THRC_L__THRC_CCA_EXT20_DB___POR 0x0C +#define PHYA_RXTD_AGC_CCA_THRC_L__THRC_CCA_PRI20_DB___POR 0x0C +#define PHYA_RXTD_AGC_CCA_THRC_L__THRC_CCA_EXT80_DB___M 0xFF000000 +#define PHYA_RXTD_AGC_CCA_THRC_L__THRC_CCA_EXT80_DB___S 24 +#define PHYA_RXTD_AGC_CCA_THRC_L__THRC_CCA_EXT40_DB___M 0x00FF0000 +#define PHYA_RXTD_AGC_CCA_THRC_L__THRC_CCA_EXT40_DB___S 16 +#define PHYA_RXTD_AGC_CCA_THRC_L__THRC_CCA_EXT20_DB___M 0x0000FF00 +#define PHYA_RXTD_AGC_CCA_THRC_L__THRC_CCA_EXT20_DB___S 8 +#define PHYA_RXTD_AGC_CCA_THRC_L__THRC_CCA_PRI20_DB___M 0x000000FF +#define PHYA_RXTD_AGC_CCA_THRC_L__THRC_CCA_PRI20_DB___S 0 +#define PHYA_RXTD_AGC_CCA_THRC_L___M 0xFFFFFFFF +#define PHYA_RXTD_AGC_CCA_THRC_L___S 0 + +#define PHYA_RXTD_AGC_CCA_CONFIG_L (0x003A0130) +#define PHYA_RXTD_AGC_CCA_CONFIG_L___RWC QCSR_REG_RW +#define PHYA_RXTD_AGC_CCA_CONFIG_L___POR 0x0BFFF802 +#define PHYA_RXTD_AGC_CCA_CONFIG_L__CCA_AVG_ENA___POR 0x1 +#define PHYA_RXTD_AGC_CCA_CONFIG_L__CCA_NO_HTBW_UPDATE___POR 0x0 +#define PHYA_RXTD_AGC_CCA_CONFIG_L__CCA_NO_AGCBW_UPDATE___POR 0x1 +#define PHYA_RXTD_AGC_CCA_CONFIG_L__DYN_BW_CCA___POR 0x3 +#define PHYA_RXTD_AGC_CCA_CONFIG_L__GI_MODE_HIGH_MASK___POR 0x3F +#define PHYA_RXTD_AGC_CCA_CONFIG_L__GI_MODE_LOW_MASK___POR 0x3F +#define PHYA_RXTD_AGC_CCA_CONFIG_L__MINCCAPWR_THR___POR 0x000 +#define PHYA_RXTD_AGC_CCA_CONFIG_L__MINCCAPWR_THR_EN___POR 0x1 +#define PHYA_RXTD_AGC_CCA_CONFIG_L__THR_CCA_MODE___POR 0x0 +#define PHYA_RXTD_AGC_CCA_CONFIG_L__CCA_AVG_ENA___M 0x08000000 +#define PHYA_RXTD_AGC_CCA_CONFIG_L__CCA_AVG_ENA___S 27 +#define PHYA_RXTD_AGC_CCA_CONFIG_L__CCA_NO_HTBW_UPDATE___M 0x04000000 +#define PHYA_RXTD_AGC_CCA_CONFIG_L__CCA_NO_HTBW_UPDATE___S 26 +#define PHYA_RXTD_AGC_CCA_CONFIG_L__CCA_NO_AGCBW_UPDATE___M 0x02000000 +#define PHYA_RXTD_AGC_CCA_CONFIG_L__CCA_NO_AGCBW_UPDATE___S 25 +#define PHYA_RXTD_AGC_CCA_CONFIG_L__DYN_BW_CCA___M 0x01800000 +#define PHYA_RXTD_AGC_CCA_CONFIG_L__DYN_BW_CCA___S 23 +#define PHYA_RXTD_AGC_CCA_CONFIG_L__GI_MODE_HIGH_MASK___M 0x007E0000 +#define PHYA_RXTD_AGC_CCA_CONFIG_L__GI_MODE_HIGH_MASK___S 17 +#define PHYA_RXTD_AGC_CCA_CONFIG_L__GI_MODE_LOW_MASK___M 0x0001F800 +#define PHYA_RXTD_AGC_CCA_CONFIG_L__GI_MODE_LOW_MASK___S 11 +#define PHYA_RXTD_AGC_CCA_CONFIG_L__MINCCAPWR_THR___M 0x000007FC +#define PHYA_RXTD_AGC_CCA_CONFIG_L__MINCCAPWR_THR___S 2 +#define PHYA_RXTD_AGC_CCA_CONFIG_L__MINCCAPWR_THR_EN___M 0x00000002 +#define PHYA_RXTD_AGC_CCA_CONFIG_L__MINCCAPWR_THR_EN___S 1 +#define PHYA_RXTD_AGC_CCA_CONFIG_L__THR_CCA_MODE___M 0x00000001 +#define PHYA_RXTD_AGC_CCA_CONFIG_L__THR_CCA_MODE___S 0 +#define PHYA_RXTD_AGC_CCA_CONFIG_L___M 0x0FFFFFFF +#define PHYA_RXTD_AGC_CCA_CONFIG_L___S 0 + +#define PHYA_RXTD_CCA_RXFRAME_FORCE_L (0x003A0138) +#define PHYA_RXTD_CCA_RXFRAME_FORCE_L___RWC QCSR_REG_RW +#define PHYA_RXTD_CCA_RXFRAME_FORCE_L___POR 0x000000FF +#define PHYA_RXTD_CCA_RXFRAME_FORCE_L__CCA_FORCE_ON_RX_FRAME___POR 0x00 +#define PHYA_RXTD_CCA_RXFRAME_FORCE_L__CCA_FORCE_ON_RX_VALUE___POR 0xFF +#define PHYA_RXTD_CCA_RXFRAME_FORCE_L__CCA_FORCE_ON_RX_FRAME___M 0x0000FF00 +#define PHYA_RXTD_CCA_RXFRAME_FORCE_L__CCA_FORCE_ON_RX_FRAME___S 8 +#define PHYA_RXTD_CCA_RXFRAME_FORCE_L__CCA_FORCE_ON_RX_VALUE___M 0x000000FF +#define PHYA_RXTD_CCA_RXFRAME_FORCE_L__CCA_FORCE_ON_RX_VALUE___S 0 +#define PHYA_RXTD_CCA_RXFRAME_FORCE_L___M 0x0000FFFF +#define PHYA_RXTD_CCA_RXFRAME_FORCE_L___S 0 + +#define PHYA_RXTD_AGC_CCA_GI_CONFIG_0_L (0x003A0140) +#define PHYA_RXTD_AGC_CCA_GI_CONFIG_0_L___RWC QCSR_REG_RW +#define PHYA_RXTD_AGC_CCA_GI_CONFIG_0_L___POR 0x000000FF +#define PHYA_RXTD_AGC_CCA_GI_CONFIG_0_L__EDGI_MASK_LOW_B___POR 0xFF +#define PHYA_RXTD_AGC_CCA_GI_CONFIG_0_L__EDGI_MASK_LOW_B___M 0x000000FF +#define PHYA_RXTD_AGC_CCA_GI_CONFIG_0_L__EDGI_MASK_LOW_B___S 0 +#define PHYA_RXTD_AGC_CCA_GI_CONFIG_0_L___M 0x000000FF +#define PHYA_RXTD_AGC_CCA_GI_CONFIG_0_L___S 0 + +#define PHYA_RXTD_AGC_CCA_GI_CONFIG_1_L (0x003A0148) +#define PHYA_RXTD_AGC_CCA_GI_CONFIG_1_L___RWC QCSR_REG_RW +#define PHYA_RXTD_AGC_CCA_GI_CONFIG_1_L___POR 0x00000000 +#define PHYA_RXTD_AGC_CCA_GI_CONFIG_1_L__EDGI_MASK_LOW_C___POR 0x00 +#define PHYA_RXTD_AGC_CCA_GI_CONFIG_1_L__EDGI_MASK_LOW_C___M 0x000000FF +#define PHYA_RXTD_AGC_CCA_GI_CONFIG_1_L__EDGI_MASK_LOW_C___S 0 +#define PHYA_RXTD_AGC_CCA_GI_CONFIG_1_L___M 0x000000FF +#define PHYA_RXTD_AGC_CCA_GI_CONFIG_1_L___S 0 + +#define PHYA_RXTD_AGC_CCA_GI_CONFIG_2_L (0x003A0150) +#define PHYA_RXTD_AGC_CCA_GI_CONFIG_2_L___RWC QCSR_REG_RW +#define PHYA_RXTD_AGC_CCA_GI_CONFIG_2_L___POR 0x00000000 +#define PHYA_RXTD_AGC_CCA_GI_CONFIG_2_L__EDGI_MASK_HIGH_B___POR 0x00 +#define PHYA_RXTD_AGC_CCA_GI_CONFIG_2_L__EDGI_MASK_HIGH_B___M 0x000000FF +#define PHYA_RXTD_AGC_CCA_GI_CONFIG_2_L__EDGI_MASK_HIGH_B___S 0 +#define PHYA_RXTD_AGC_CCA_GI_CONFIG_2_L___M 0x000000FF +#define PHYA_RXTD_AGC_CCA_GI_CONFIG_2_L___S 0 + +#define PHYA_RXTD_AGC_CCA_GI_CONFIG_3_L (0x003A0158) +#define PHYA_RXTD_AGC_CCA_GI_CONFIG_3_L___RWC QCSR_REG_RW +#define PHYA_RXTD_AGC_CCA_GI_CONFIG_3_L___POR 0x000000FF +#define PHYA_RXTD_AGC_CCA_GI_CONFIG_3_L__EDGI_MASK_HIGH_C___POR 0xFF +#define PHYA_RXTD_AGC_CCA_GI_CONFIG_3_L__EDGI_MASK_HIGH_C___M 0x000000FF +#define PHYA_RXTD_AGC_CCA_GI_CONFIG_3_L__EDGI_MASK_HIGH_C___S 0 +#define PHYA_RXTD_AGC_CCA_GI_CONFIG_3_L___M 0x000000FF +#define PHYA_RXTD_AGC_CCA_GI_CONFIG_3_L___S 0 + +#define PHYA_RXTD_RSSI_CONFIG_L (0x003A0160) +#define PHYA_RXTD_RSSI_CONFIG_L___RWC QCSR_REG_RW +#define PHYA_RXTD_RSSI_CONFIG_L___POR 0x00000000 +#define PHYA_RXTD_RSSI_CONFIG_L__POST_RSSI_DELAY___POR 0x000 +#define PHYA_RXTD_RSSI_CONFIG_L__RSSI_OUT_SELECT___POR 0x0 +#define PHYA_RXTD_RSSI_CONFIG_L__POST_RSSI_DELAY___M 0x01FF0000 +#define PHYA_RXTD_RSSI_CONFIG_L__POST_RSSI_DELAY___S 16 +#define PHYA_RXTD_RSSI_CONFIG_L__RSSI_OUT_SELECT___M 0x00000003 +#define PHYA_RXTD_RSSI_CONFIG_L__RSSI_OUT_SELECT___S 0 +#define PHYA_RXTD_RSSI_CONFIG_L___M 0x01FF0003 +#define PHYA_RXTD_RSSI_CONFIG_L___S 0 + +#define PHYA_RXTD_RSSI_CONFIG_U (0x003A0164) +#define PHYA_RXTD_RSSI_CONFIG_U___RWC QCSR_REG_RW +#define PHYA_RXTD_RSSI_CONFIG_U___POR 0x00000000 +#define PHYA_RXTD_RSSI_CONFIG_U__RSSI_DB_TO_DBM_OFFSET___POR 0x00 +#define PHYA_RXTD_RSSI_CONFIG_U__RSSI_DB_TO_DBM_OFFSET___M 0x000000FF +#define PHYA_RXTD_RSSI_CONFIG_U__RSSI_DB_TO_DBM_OFFSET___S 0 +#define PHYA_RXTD_RSSI_CONFIG_U___M 0x000000FF +#define PHYA_RXTD_RSSI_CONFIG_U___S 0 + +#define PHYA_RXTD_CCA_FORCE_L (0x003A0168) +#define PHYA_RXTD_CCA_FORCE_L___RWC QCSR_REG_RW +#define PHYA_RXTD_CCA_FORCE_L___POR 0xFFFF0000 +#define PHYA_RXTD_CCA_FORCE_L__CCA_FORCE_VALUE_THRB___POR 0xFF +#define PHYA_RXTD_CCA_FORCE_L__CCA_FORCE_VALUE___POR 0xFF +#define PHYA_RXTD_CCA_FORCE_L__CCA_FORCE_STROBE___POR 0x0 +#define PHYA_RXTD_CCA_FORCE_L__CCA_FORCE_EN___POR 0x0 +#define PHYA_RXTD_CCA_FORCE_L__CCA_FORCE_VALUE_THRB___M 0xFF000000 +#define PHYA_RXTD_CCA_FORCE_L__CCA_FORCE_VALUE_THRB___S 24 +#define PHYA_RXTD_CCA_FORCE_L__CCA_FORCE_VALUE___M 0x00FF0000 +#define PHYA_RXTD_CCA_FORCE_L__CCA_FORCE_VALUE___S 16 +#define PHYA_RXTD_CCA_FORCE_L__CCA_FORCE_STROBE___M 0x00000100 +#define PHYA_RXTD_CCA_FORCE_L__CCA_FORCE_STROBE___S 8 +#define PHYA_RXTD_CCA_FORCE_L__CCA_FORCE_EN___M 0x00000001 +#define PHYA_RXTD_CCA_FORCE_L__CCA_FORCE_EN___S 0 +#define PHYA_RXTD_CCA_FORCE_L___M 0xFFFF0101 +#define PHYA_RXTD_CCA_FORCE_L___S 0 + +#define PHYA_RXTD_CCA_FORCE_U (0x003A016C) +#define PHYA_RXTD_CCA_FORCE_U___RWC QCSR_REG_RW +#define PHYA_RXTD_CCA_FORCE_U___POR 0x00FFFFFF +#define PHYA_RXTD_CCA_FORCE_U__CCA_FORCE_VALUE_GI_HIGH___POR 0xFF +#define PHYA_RXTD_CCA_FORCE_U__CCA_FORCE_VALUE_GI_LOW___POR 0xFF +#define PHYA_RXTD_CCA_FORCE_U__CCA_FORCE_VALUE_THRC___POR 0xFF +#define PHYA_RXTD_CCA_FORCE_U__CCA_FORCE_VALUE_GI_HIGH___M 0x00FF0000 +#define PHYA_RXTD_CCA_FORCE_U__CCA_FORCE_VALUE_GI_HIGH___S 16 +#define PHYA_RXTD_CCA_FORCE_U__CCA_FORCE_VALUE_GI_LOW___M 0x0000FF00 +#define PHYA_RXTD_CCA_FORCE_U__CCA_FORCE_VALUE_GI_LOW___S 8 +#define PHYA_RXTD_CCA_FORCE_U__CCA_FORCE_VALUE_THRC___M 0x000000FF +#define PHYA_RXTD_CCA_FORCE_U__CCA_FORCE_VALUE_THRC___S 0 +#define PHYA_RXTD_CCA_FORCE_U___M 0x00FFFFFF +#define PHYA_RXTD_CCA_FORCE_U___S 0 + +#define PHYA_RXTD_GAIN_RATIO_CONFIG_L (0x003A0170) +#define PHYA_RXTD_GAIN_RATIO_CONFIG_L___RWC QCSR_REG_RW +#define PHYA_RXTD_GAIN_RATIO_CONFIG_L___POR 0x000001BB +#define PHYA_RXTD_GAIN_RATIO_CONFIG_L__FIXED_GAIN_RATIO_EN___POR 0x0 +#define PHYA_RXTD_GAIN_RATIO_CONFIG_L__QUANT_NOISE_FLOOR_EN___POR 0x1 +#define PHYA_RXTD_GAIN_RATIO_CONFIG_L__QUANT_NOISE_FLOOR_DB___POR 0xBB +#define PHYA_RXTD_GAIN_RATIO_CONFIG_L__FIXED_GAIN_RATIO_EN___M 0x00000200 +#define PHYA_RXTD_GAIN_RATIO_CONFIG_L__FIXED_GAIN_RATIO_EN___S 9 +#define PHYA_RXTD_GAIN_RATIO_CONFIG_L__QUANT_NOISE_FLOOR_EN___M 0x00000100 +#define PHYA_RXTD_GAIN_RATIO_CONFIG_L__QUANT_NOISE_FLOOR_EN___S 8 +#define PHYA_RXTD_GAIN_RATIO_CONFIG_L__QUANT_NOISE_FLOOR_DB___M 0x000000FF +#define PHYA_RXTD_GAIN_RATIO_CONFIG_L__QUANT_NOISE_FLOOR_DB___S 0 +#define PHYA_RXTD_GAIN_RATIO_CONFIG_L___M 0x000003FF +#define PHYA_RXTD_GAIN_RATIO_CONFIG_L___S 0 + +#define PHYA_RXTD_AGC_NFCAL_PHY0_L (0x003A0178) +#define PHYA_RXTD_AGC_NFCAL_PHY0_L___RWC QCSR_REG_RW +#define PHYA_RXTD_AGC_NFCAL_PHY0_L___POR 0xE0A60003 +#define PHYA_RXTD_AGC_NFCAL_PHY0_L__MINCCA_RELPWR_THR_DB2___POR 0xE0 +#define PHYA_RXTD_AGC_NFCAL_PHY0_L__MINCCA_FIRPWR_THR_DB2___POR 0xA6 +#define PHYA_RXTD_AGC_NFCAL_PHY0_L__ENABLE_NOISEFLOOR___POR 0x0 +#define PHYA_RXTD_AGC_NFCAL_PHY0_L__CF_CCA_COUNT_MAXC___POR 0x3 +#define PHYA_RXTD_AGC_NFCAL_PHY0_L__MINCCA_RELPWR_THR_DB2___M 0xFF000000 +#define PHYA_RXTD_AGC_NFCAL_PHY0_L__MINCCA_RELPWR_THR_DB2___S 24 +#define PHYA_RXTD_AGC_NFCAL_PHY0_L__MINCCA_FIRPWR_THR_DB2___M 0x00FF0000 +#define PHYA_RXTD_AGC_NFCAL_PHY0_L__MINCCA_FIRPWR_THR_DB2___S 16 +#define PHYA_RXTD_AGC_NFCAL_PHY0_L__ENABLE_NOISEFLOOR___M 0x00000100 +#define PHYA_RXTD_AGC_NFCAL_PHY0_L__ENABLE_NOISEFLOOR___S 8 +#define PHYA_RXTD_AGC_NFCAL_PHY0_L__CF_CCA_COUNT_MAXC___M 0x0000000F +#define PHYA_RXTD_AGC_NFCAL_PHY0_L__CF_CCA_COUNT_MAXC___S 0 +#define PHYA_RXTD_AGC_NFCAL_PHY0_L___M 0xFFFF010F +#define PHYA_RXTD_AGC_NFCAL_PHY0_L___S 0 + +#define PHYA_RXTD_VSRC_CONFIG_L (0x003A0180) +#define PHYA_RXTD_VSRC_CONFIG_L___RWC QCSR_REG_RW +#define PHYA_RXTD_VSRC_CONFIG_L___POR 0x00000002 +#define PHYA_RXTD_VSRC_CONFIG_L__VSRC_HB_BYPASS___POR 0x0 +#define PHYA_RXTD_VSRC_CONFIG_L__VSRC_FIFO_INIT_DEPTH___POR 0x02 +#define PHYA_RXTD_VSRC_CONFIG_L__VSRC_HB_BYPASS___M 0x00000020 +#define PHYA_RXTD_VSRC_CONFIG_L__VSRC_HB_BYPASS___S 5 +#define PHYA_RXTD_VSRC_CONFIG_L__VSRC_FIFO_INIT_DEPTH___M 0x0000001F +#define PHYA_RXTD_VSRC_CONFIG_L__VSRC_FIFO_INIT_DEPTH___S 0 +#define PHYA_RXTD_VSRC_CONFIG_L___M 0x0000003F +#define PHYA_RXTD_VSRC_CONFIG_L___S 0 + +#define PHYA_RXTD_VSRC_CONFIG_U (0x003A0184) +#define PHYA_RXTD_VSRC_CONFIG_U___RWC QCSR_REG_RW +#define PHYA_RXTD_VSRC_CONFIG_U___POR 0x00000000 +#define PHYA_RXTD_VSRC_CONFIG_U__VSRC_PPM_FC_FACTOR___POR 0x00000000 +#define PHYA_RXTD_VSRC_CONFIG_U__VSRC_PPM_FC_FACTOR___M 0xFFFFFFFF +#define PHYA_RXTD_VSRC_CONFIG_U__VSRC_PPM_FC_FACTOR___S 0 +#define PHYA_RXTD_VSRC_CONFIG_U___M 0xFFFFFFFF +#define PHYA_RXTD_VSRC_CONFIG_U___S 0 + +#define PHYA_RXTD_NOTCH_CNTL_1_L (0x003A0188) +#define PHYA_RXTD_NOTCH_CNTL_1_L___RWC QCSR_REG_RW +#define PHYA_RXTD_NOTCH_CNTL_1_L___POR 0x12200C91 +#define PHYA_RXTD_NOTCH_CNTL_1_L__ALPHA_SPUR4___POR 0x4 +#define PHYA_RXTD_NOTCH_CNTL_1_L__ALPHA_SPUR3___POR 0x4 +#define PHYA_RXTD_NOTCH_CNTL_1_L__SPUR_GAIN_THR_ENA___POR 0x0 +#define PHYA_RXTD_NOTCH_CNTL_1_L__SPUR_GAIN_THR_DB2___POR 0x200 +#define PHYA_RXTD_NOTCH_CNTL_1_L__RX11B_DC_EST_ACCUM_INTERVAL___POR 0x1 +#define PHYA_RXTD_NOTCH_CNTL_1_L__ALPHA_DC___POR 0x4 +#define PHYA_RXTD_NOTCH_CNTL_1_L__ALPHA_SPUR2___POR 0x4 +#define PHYA_RXTD_NOTCH_CNTL_1_L__ALPHA_SPUR1___POR 0x4 +#define PHYA_RXTD_NOTCH_CNTL_1_L__ENA_DC_NOTCH_FILTER_11B___POR 0x0 +#define PHYA_RXTD_NOTCH_CNTL_1_L__ENA_DC_NOTCH_FILTER___POR 0x1 +#define PHYA_RXTD_NOTCH_CNTL_1_L__ALPHA_SPUR4___M 0x1C000000 +#define PHYA_RXTD_NOTCH_CNTL_1_L__ALPHA_SPUR4___S 26 +#define PHYA_RXTD_NOTCH_CNTL_1_L__ALPHA_SPUR3___M 0x03800000 +#define PHYA_RXTD_NOTCH_CNTL_1_L__ALPHA_SPUR3___S 23 +#define PHYA_RXTD_NOTCH_CNTL_1_L__SPUR_GAIN_THR_ENA___M 0x00400000 +#define PHYA_RXTD_NOTCH_CNTL_1_L__SPUR_GAIN_THR_ENA___S 22 +#define PHYA_RXTD_NOTCH_CNTL_1_L__SPUR_GAIN_THR_DB2___M 0x003FF000 +#define PHYA_RXTD_NOTCH_CNTL_1_L__SPUR_GAIN_THR_DB2___S 12 +#define PHYA_RXTD_NOTCH_CNTL_1_L__RX11B_DC_EST_ACCUM_INTERVAL___M 0x00000800 +#define PHYA_RXTD_NOTCH_CNTL_1_L__RX11B_DC_EST_ACCUM_INTERVAL___S 11 +#define PHYA_RXTD_NOTCH_CNTL_1_L__ALPHA_DC___M 0x00000700 +#define PHYA_RXTD_NOTCH_CNTL_1_L__ALPHA_DC___S 8 +#define PHYA_RXTD_NOTCH_CNTL_1_L__ALPHA_SPUR2___M 0x000000E0 +#define PHYA_RXTD_NOTCH_CNTL_1_L__ALPHA_SPUR2___S 5 +#define PHYA_RXTD_NOTCH_CNTL_1_L__ALPHA_SPUR1___M 0x0000001C +#define PHYA_RXTD_NOTCH_CNTL_1_L__ALPHA_SPUR1___S 2 +#define PHYA_RXTD_NOTCH_CNTL_1_L__ENA_DC_NOTCH_FILTER_11B___M 0x00000002 +#define PHYA_RXTD_NOTCH_CNTL_1_L__ENA_DC_NOTCH_FILTER_11B___S 1 +#define PHYA_RXTD_NOTCH_CNTL_1_L__ENA_DC_NOTCH_FILTER___M 0x00000001 +#define PHYA_RXTD_NOTCH_CNTL_1_L__ENA_DC_NOTCH_FILTER___S 0 +#define PHYA_RXTD_NOTCH_CNTL_1_L___M 0x1FFFFFFF +#define PHYA_RXTD_NOTCH_CNTL_1_L___S 0 + +#define PHYA_RXTD_CTE_CONFIG_1_0_L (0x003A0190) +#define PHYA_RXTD_CTE_CONFIG_1_0_L___RWC QCSR_REG_RW +#define PHYA_RXTD_CTE_CONFIG_1_0_L___POR 0x00499BE1 +#define PHYA_RXTD_CTE_CONFIG_1_0_L__WEAKLOW_CFO_BACKOFF___POR 0x4 +#define PHYA_RXTD_CTE_CONFIG_1_0_L__CTE_DETECT_THRESH___POR 0x266 +#define PHYA_RXTD_CTE_CONFIG_1_0_L__CTE_LPF_BETA___POR 0x3E1 +#define PHYA_RXTD_CTE_CONFIG_1_0_L__WEAKLOW_CFO_BACKOFF___M 0x00700000 +#define PHYA_RXTD_CTE_CONFIG_1_0_L__WEAKLOW_CFO_BACKOFF___S 20 +#define PHYA_RXTD_CTE_CONFIG_1_0_L__CTE_DETECT_THRESH___M 0x000FFC00 +#define PHYA_RXTD_CTE_CONFIG_1_0_L__CTE_DETECT_THRESH___S 10 +#define PHYA_RXTD_CTE_CONFIG_1_0_L__CTE_LPF_BETA___M 0x000003FF +#define PHYA_RXTD_CTE_CONFIG_1_0_L__CTE_LPF_BETA___S 0 +#define PHYA_RXTD_CTE_CONFIG_1_0_L___M 0x007FFFFF +#define PHYA_RXTD_CTE_CONFIG_1_0_L___S 0 + +#define PHYA_RXTD_CTE_CONFIG_1_0_U (0x003A0194) +#define PHYA_RXTD_CTE_CONFIG_1_0_U___RWC QCSR_REG_RW +#define PHYA_RXTD_CTE_CONFIG_1_0_U___POR 0x7C299BE1 +#define PHYA_RXTD_CTE_CONFIG_1_0_U__CTE_LPF_BETA_WEAK___POR 0x3E1 +#define PHYA_RXTD_CTE_CONFIG_1_0_U__CTE_ENA_STR___POR 0x0 +#define PHYA_RXTD_CTE_CONFIG_1_0_U__CTE_DETECT_THRESH_STR___POR 0x266 +#define PHYA_RXTD_CTE_CONFIG_1_0_U__CTE_LPF_BETA_STR___POR 0x3E1 +#define PHYA_RXTD_CTE_CONFIG_1_0_U__CTE_LPF_BETA_WEAK___M 0x7FE00000 +#define PHYA_RXTD_CTE_CONFIG_1_0_U__CTE_LPF_BETA_WEAK___S 21 +#define PHYA_RXTD_CTE_CONFIG_1_0_U__CTE_ENA_STR___M 0x00100000 +#define PHYA_RXTD_CTE_CONFIG_1_0_U__CTE_ENA_STR___S 20 +#define PHYA_RXTD_CTE_CONFIG_1_0_U__CTE_DETECT_THRESH_STR___M 0x000FFC00 +#define PHYA_RXTD_CTE_CONFIG_1_0_U__CTE_DETECT_THRESH_STR___S 10 +#define PHYA_RXTD_CTE_CONFIG_1_0_U__CTE_LPF_BETA_STR___M 0x000003FF +#define PHYA_RXTD_CTE_CONFIG_1_0_U__CTE_LPF_BETA_STR___S 0 +#define PHYA_RXTD_CTE_CONFIG_1_0_U___M 0x7FFFFFFF +#define PHYA_RXTD_CTE_CONFIG_1_0_U___S 0 + +#define PHYA_RXTD_CTE_CONFIG_1_1_L (0x003A0198) +#define PHYA_RXTD_CTE_CONFIG_1_1_L___RWC QCSR_REG_RW +#define PHYA_RXTD_CTE_CONFIG_1_1_L___POR 0x00000266 +#define PHYA_RXTD_CTE_CONFIG_1_1_L__CTE_ENA_WEAK___POR 0x0 +#define PHYA_RXTD_CTE_CONFIG_1_1_L__CTE_DETECT_THRESH_WEAK___POR 0x266 +#define PHYA_RXTD_CTE_CONFIG_1_1_L__CTE_ENA_WEAK___M 0x00000400 +#define PHYA_RXTD_CTE_CONFIG_1_1_L__CTE_ENA_WEAK___S 10 +#define PHYA_RXTD_CTE_CONFIG_1_1_L__CTE_DETECT_THRESH_WEAK___M 0x000003FF +#define PHYA_RXTD_CTE_CONFIG_1_1_L__CTE_DETECT_THRESH_WEAK___S 0 +#define PHYA_RXTD_CTE_CONFIG_1_1_L___M 0x000007FF +#define PHYA_RXTD_CTE_CONFIG_1_1_L___S 0 + +#define PHYA_RXTD_BTCF_CONFIG_1_L (0x003A01A0) +#define PHYA_RXTD_BTCF_CONFIG_1_L___RWC QCSR_REG_RW +#define PHYA_RXTD_BTCF_CONFIG_1_L___POR 0x03C29FA3 +#define PHYA_RXTD_BTCF_CONFIG_1_L__BTCF_RSSI_THR_HIGH_DB___POR 0x1E +#define PHYA_RXTD_BTCF_CONFIG_1_L__BTCF_RSSI_THR_LOW_DB___POR 0x14 +#define PHYA_RXTD_BTCF_CONFIG_1_L__BTCF_LGFIRPWR_IDEAL___POR 0xFD1 +#define PHYA_RXTD_BTCF_CONFIG_1_L__BTCF_ENABLE_FINE_TIMING___POR 0x1 +#define PHYA_RXTD_BTCF_CONFIG_1_L__BTCF_RSSI_THR_HIGH_DB___M 0x1FE00000 +#define PHYA_RXTD_BTCF_CONFIG_1_L__BTCF_RSSI_THR_HIGH_DB___S 21 +#define PHYA_RXTD_BTCF_CONFIG_1_L__BTCF_RSSI_THR_LOW_DB___M 0x001FE000 +#define PHYA_RXTD_BTCF_CONFIG_1_L__BTCF_RSSI_THR_LOW_DB___S 13 +#define PHYA_RXTD_BTCF_CONFIG_1_L__BTCF_LGFIRPWR_IDEAL___M 0x00001FFE +#define PHYA_RXTD_BTCF_CONFIG_1_L__BTCF_LGFIRPWR_IDEAL___S 1 +#define PHYA_RXTD_BTCF_CONFIG_1_L__BTCF_ENABLE_FINE_TIMING___M 0x00000001 +#define PHYA_RXTD_BTCF_CONFIG_1_L__BTCF_ENABLE_FINE_TIMING___S 0 +#define PHYA_RXTD_BTCF_CONFIG_1_L___M 0x1FFFFFFF +#define PHYA_RXTD_BTCF_CONFIG_1_L___S 0 + +#define PHYA_RXTD_BTCF_CONFIG_1_U (0x003A01A4) +#define PHYA_RXTD_BTCF_CONFIG_1_U___RWC QCSR_REG_RW +#define PHYA_RXTD_BTCF_CONFIG_1_U___POR 0x00060708 +#define PHYA_RXTD_BTCF_CONFIG_1_U__BTCF_BACKOFF_HIGH___POR 0x06 +#define PHYA_RXTD_BTCF_CONFIG_1_U__BTCF_BACKOFF_MID___POR 0x07 +#define PHYA_RXTD_BTCF_CONFIG_1_U__BTCF_BACKOFF_LOW___POR 0x08 +#define PHYA_RXTD_BTCF_CONFIG_1_U__BTCF_BACKOFF_HIGH___M 0x00FF0000 +#define PHYA_RXTD_BTCF_CONFIG_1_U__BTCF_BACKOFF_HIGH___S 16 +#define PHYA_RXTD_BTCF_CONFIG_1_U__BTCF_BACKOFF_MID___M 0x0000FF00 +#define PHYA_RXTD_BTCF_CONFIG_1_U__BTCF_BACKOFF_MID___S 8 +#define PHYA_RXTD_BTCF_CONFIG_1_U__BTCF_BACKOFF_LOW___M 0x000000FF +#define PHYA_RXTD_BTCF_CONFIG_1_U__BTCF_BACKOFF_LOW___S 0 +#define PHYA_RXTD_BTCF_CONFIG_1_U___M 0x00FFFFFF +#define PHYA_RXTD_BTCF_CONFIG_1_U___S 0 + +#define PHYA_RXTD_BTCF_CONFIG_3_L (0x003A01A8) +#define PHYA_RXTD_BTCF_CONFIG_3_L___RWC QCSR_REG_RW +#define PHYA_RXTD_BTCF_CONFIG_3_L___POR 0x0160B05F +#define PHYA_RXTD_BTCF_CONFIG_3_L__BTCF_AVG_INTERVAL_HIGH___POR 0x058 +#define PHYA_RXTD_BTCF_CONFIG_3_L__BTCF_AVG_INTERVAL_MID___POR 0x058 +#define PHYA_RXTD_BTCF_CONFIG_3_L__BTCF_AVG_INTERVAL_LOW___POR 0x05F +#define PHYA_RXTD_BTCF_CONFIG_3_L__BTCF_AVG_INTERVAL_HIGH___M 0x07FC0000 +#define PHYA_RXTD_BTCF_CONFIG_3_L__BTCF_AVG_INTERVAL_HIGH___S 18 +#define PHYA_RXTD_BTCF_CONFIG_3_L__BTCF_AVG_INTERVAL_MID___M 0x0003FE00 +#define PHYA_RXTD_BTCF_CONFIG_3_L__BTCF_AVG_INTERVAL_MID___S 9 +#define PHYA_RXTD_BTCF_CONFIG_3_L__BTCF_AVG_INTERVAL_LOW___M 0x000001FF +#define PHYA_RXTD_BTCF_CONFIG_3_L__BTCF_AVG_INTERVAL_LOW___S 0 +#define PHYA_RXTD_BTCF_CONFIG_3_L___M 0x07FFFFFF +#define PHYA_RXTD_BTCF_CONFIG_3_L___S 0 + +#define PHYA_RXTD_BTCF_CONFIG_3_U (0x003A01AC) +#define PHYA_RXTD_BTCF_CONFIG_3_U___RWC QCSR_REG_RW +#define PHYA_RXTD_BTCF_CONFIG_3_U___POR 0x00000000 +#define PHYA_RXTD_BTCF_CONFIG_3_U__UL_MU_BTCF_EST___POR 0x0000 +#define PHYA_RXTD_BTCF_CONFIG_3_U__UL_MU_BTCF_DONE___POR 0x0000 +#define PHYA_RXTD_BTCF_CONFIG_3_U__UL_MU_BTCF_EST___M 0xFFFF0000 +#define PHYA_RXTD_BTCF_CONFIG_3_U__UL_MU_BTCF_EST___S 16 +#define PHYA_RXTD_BTCF_CONFIG_3_U__UL_MU_BTCF_DONE___M 0x0000FFFF +#define PHYA_RXTD_BTCF_CONFIG_3_U__UL_MU_BTCF_DONE___S 0 +#define PHYA_RXTD_BTCF_CONFIG_3_U___M 0xFFFFFFFF +#define PHYA_RXTD_BTCF_CONFIG_3_U___S 0 + +#define PHYA_RXTD_BTCF_CONFIG_2_L (0x003A01B0) +#define PHYA_RXTD_BTCF_CONFIG_2_L___RWC QCSR_REG_RW +#define PHYA_RXTD_BTCF_CONFIG_2_L___POR 0x04CE3503 +#define PHYA_RXTD_BTCF_CONFIG_2_L__BTCF_RISING_EDGE_THR_HIGH___POR 0x133 +#define PHYA_RXTD_BTCF_CONFIG_2_L__BTCF_RISING_EDGE_THR_MID___POR 0x11A +#define PHYA_RXTD_BTCF_CONFIG_2_L__BTCF_RISING_EDGE_THR_LOW___POR 0x103 +#define PHYA_RXTD_BTCF_CONFIG_2_L__BTCF_RISING_EDGE_THR_HIGH___M 0x07FC0000 +#define PHYA_RXTD_BTCF_CONFIG_2_L__BTCF_RISING_EDGE_THR_HIGH___S 18 +#define PHYA_RXTD_BTCF_CONFIG_2_L__BTCF_RISING_EDGE_THR_MID___M 0x0003FE00 +#define PHYA_RXTD_BTCF_CONFIG_2_L__BTCF_RISING_EDGE_THR_MID___S 9 +#define PHYA_RXTD_BTCF_CONFIG_2_L__BTCF_RISING_EDGE_THR_LOW___M 0x000001FF +#define PHYA_RXTD_BTCF_CONFIG_2_L__BTCF_RISING_EDGE_THR_LOW___S 0 +#define PHYA_RXTD_BTCF_CONFIG_2_L___M 0x07FFFFFF +#define PHYA_RXTD_BTCF_CONFIG_2_L___S 0 + +#define PHYA_RXTD_BTCF_CONFIG_2_U (0x003A01B4) +#define PHYA_RXTD_BTCF_CONFIG_2_U___RWC QCSR_REG_RW +#define PHYA_RXTD_BTCF_CONFIG_2_U___POR 0x8399004D +#define PHYA_RXTD_BTCF_CONFIG_2_U__BTCF_SEARCH_ABORT_TIME___POR 0x10 +#define PHYA_RXTD_BTCF_CONFIG_2_U__BTCF_PACKET_DET_THR_HIGH___POR 0x0E6 +#define PHYA_RXTD_BTCF_CONFIG_2_U__BTCF_PACKET_DET_THR_MID___POR 0x080 +#define PHYA_RXTD_BTCF_CONFIG_2_U__BTCF_PACKET_DET_THR_LOW___POR 0x04D +#define PHYA_RXTD_BTCF_CONFIG_2_U__BTCF_SEARCH_ABORT_TIME___M 0xF8000000 +#define PHYA_RXTD_BTCF_CONFIG_2_U__BTCF_SEARCH_ABORT_TIME___S 27 +#define PHYA_RXTD_BTCF_CONFIG_2_U__BTCF_PACKET_DET_THR_HIGH___M 0x07FC0000 +#define PHYA_RXTD_BTCF_CONFIG_2_U__BTCF_PACKET_DET_THR_HIGH___S 18 +#define PHYA_RXTD_BTCF_CONFIG_2_U__BTCF_PACKET_DET_THR_MID___M 0x0003FE00 +#define PHYA_RXTD_BTCF_CONFIG_2_U__BTCF_PACKET_DET_THR_MID___S 9 +#define PHYA_RXTD_BTCF_CONFIG_2_U__BTCF_PACKET_DET_THR_LOW___M 0x000001FF +#define PHYA_RXTD_BTCF_CONFIG_2_U__BTCF_PACKET_DET_THR_LOW___S 0 +#define PHYA_RXTD_BTCF_CONFIG_2_U___M 0xFFFFFFFF +#define PHYA_RXTD_BTCF_CONFIG_2_U___S 0 + +#define PHYA_RXTD_GIC_CTRL_0_L (0x003A01B8) +#define PHYA_RXTD_GIC_CTRL_0_L___RWC QCSR_REG_RW +#define PHYA_RXTD_GIC_CTRL_0_L___POR 0xB3000000 +#define PHYA_RXTD_GIC_CTRL_0_L__GIC_SHIFT___POR 0x2 +#define PHYA_RXTD_GIC_CTRL_0_L__GIC_BETA_4X___POR 0xC +#define PHYA_RXTD_GIC_CTRL_0_L__GIC_BETA_1X___POR 0xC +#define PHYA_RXTD_GIC_CTRL_0_L__GIC1_CHN_B___POR 0x0 +#define PHYA_RXTD_GIC_CTRL_0_L__GIC1_CHN_A___POR 0x0 +#define PHYA_RXTD_GIC_CTRL_0_L__GIC1_NUM_CHN___POR 0x0 +#define PHYA_RXTD_GIC_CTRL_0_L__GIC1_SB_ENA___POR 0x0 +#define PHYA_RXTD_GIC_CTRL_0_L__GIC0_CHN_B___POR 0x0 +#define PHYA_RXTD_GIC_CTRL_0_L__GIC0_CHN_A___POR 0x0 +#define PHYA_RXTD_GIC_CTRL_0_L__GIC0_NUM_CHN___POR 0x0 +#define PHYA_RXTD_GIC_CTRL_0_L__GIC0_SB_ENA___POR 0x0 +#define PHYA_RXTD_GIC_CTRL_0_L__GIC_SHIFT___M 0xC0000000 +#define PHYA_RXTD_GIC_CTRL_0_L__GIC_SHIFT___S 30 +#define PHYA_RXTD_GIC_CTRL_0_L__GIC_BETA_4X___M 0x3C000000 +#define PHYA_RXTD_GIC_CTRL_0_L__GIC_BETA_4X___S 26 +#define PHYA_RXTD_GIC_CTRL_0_L__GIC_BETA_1X___M 0x03C00000 +#define PHYA_RXTD_GIC_CTRL_0_L__GIC_BETA_1X___S 22 +#define PHYA_RXTD_GIC_CTRL_0_L__GIC1_CHN_B___M 0x00380000 +#define PHYA_RXTD_GIC_CTRL_0_L__GIC1_CHN_B___S 19 +#define PHYA_RXTD_GIC_CTRL_0_L__GIC1_CHN_A___M 0x00070000 +#define PHYA_RXTD_GIC_CTRL_0_L__GIC1_CHN_A___S 16 +#define PHYA_RXTD_GIC_CTRL_0_L__GIC1_NUM_CHN___M 0x00008000 +#define PHYA_RXTD_GIC_CTRL_0_L__GIC1_NUM_CHN___S 15 +#define PHYA_RXTD_GIC_CTRL_0_L__GIC1_SB_ENA___M 0x00007800 +#define PHYA_RXTD_GIC_CTRL_0_L__GIC1_SB_ENA___S 11 +#define PHYA_RXTD_GIC_CTRL_0_L__GIC0_CHN_B___M 0x00000700 +#define PHYA_RXTD_GIC_CTRL_0_L__GIC0_CHN_B___S 8 +#define PHYA_RXTD_GIC_CTRL_0_L__GIC0_CHN_A___M 0x000000E0 +#define PHYA_RXTD_GIC_CTRL_0_L__GIC0_CHN_A___S 5 +#define PHYA_RXTD_GIC_CTRL_0_L__GIC0_NUM_CHN___M 0x00000010 +#define PHYA_RXTD_GIC_CTRL_0_L__GIC0_NUM_CHN___S 4 +#define PHYA_RXTD_GIC_CTRL_0_L__GIC0_SB_ENA___M 0x0000000F +#define PHYA_RXTD_GIC_CTRL_0_L__GIC0_SB_ENA___S 0 +#define PHYA_RXTD_GIC_CTRL_0_L___M 0xFFFFFFFF +#define PHYA_RXTD_GIC_CTRL_0_L___S 0 + +#define PHYA_RXTD_GIC_CTRL_1_L (0x003A01C0) +#define PHYA_RXTD_GIC_CTRL_1_L___RWC QCSR_REG_RW +#define PHYA_RXTD_GIC_CTRL_1_L___POR 0x000168B4 +#define PHYA_RXTD_GIC_CTRL_1_L__GIC_THRESHOLD_4X_LOW___POR 0x0B4 +#define PHYA_RXTD_GIC_CTRL_1_L__GIC_THRESHOLD_1X_LOW___POR 0x0B4 +#define PHYA_RXTD_GIC_CTRL_1_L__GIC_THRESHOLD_4X_LOW___M 0x0003FE00 +#define PHYA_RXTD_GIC_CTRL_1_L__GIC_THRESHOLD_4X_LOW___S 9 +#define PHYA_RXTD_GIC_CTRL_1_L__GIC_THRESHOLD_1X_LOW___M 0x000001FF +#define PHYA_RXTD_GIC_CTRL_1_L__GIC_THRESHOLD_1X_LOW___S 0 +#define PHYA_RXTD_GIC_CTRL_1_L___M 0x0003FFFF +#define PHYA_RXTD_GIC_CTRL_1_L___S 0 + +#define PHYA_RXTD_GIC_CTRL_2_L (0x003A01C8) +#define PHYA_RXTD_GIC_CTRL_2_L___RWC QCSR_REG_RW +#define PHYA_RXTD_GIC_CTRL_2_L___POR 0x057968B4 +#define PHYA_RXTD_GIC_CTRL_2_L__GIC_THRESHOLD_4X_CROSS___POR 0x15E +#define PHYA_RXTD_GIC_CTRL_2_L__GIC_THRESHOLD_4X_HIGH___POR 0x0B4 +#define PHYA_RXTD_GIC_CTRL_2_L__GIC_THRESHOLD_1X_HIGH___POR 0x0B4 +#define PHYA_RXTD_GIC_CTRL_2_L__GIC_THRESHOLD_4X_CROSS___M 0x07FC0000 +#define PHYA_RXTD_GIC_CTRL_2_L__GIC_THRESHOLD_4X_CROSS___S 18 +#define PHYA_RXTD_GIC_CTRL_2_L__GIC_THRESHOLD_4X_HIGH___M 0x0003FE00 +#define PHYA_RXTD_GIC_CTRL_2_L__GIC_THRESHOLD_4X_HIGH___S 9 +#define PHYA_RXTD_GIC_CTRL_2_L__GIC_THRESHOLD_1X_HIGH___M 0x000001FF +#define PHYA_RXTD_GIC_CTRL_2_L__GIC_THRESHOLD_1X_HIGH___S 0 +#define PHYA_RXTD_GIC_CTRL_2_L___M 0x07FFFFFF +#define PHYA_RXTD_GIC_CTRL_2_L___S 0 + +#define PHYA_RXTD_GIC_CTRL_3_L (0x003A01D0) +#define PHYA_RXTD_GIC_CTRL_3_L___RWC QCSR_REG_RW +#define PHYA_RXTD_GIC_CTRL_3_L___POR 0x00320190 +#define PHYA_RXTD_GIC_CTRL_3_L__GIC_WAIT_4X___POR 0x640 +#define PHYA_RXTD_GIC_CTRL_3_L__GIC_WAIT_1X___POR 0x190 +#define PHYA_RXTD_GIC_CTRL_3_L__GIC_WAIT_4X___M 0x003FF800 +#define PHYA_RXTD_GIC_CTRL_3_L__GIC_WAIT_4X___S 11 +#define PHYA_RXTD_GIC_CTRL_3_L__GIC_WAIT_1X___M 0x000007FF +#define PHYA_RXTD_GIC_CTRL_3_L__GIC_WAIT_1X___S 0 +#define PHYA_RXTD_GIC_CTRL_3_L___M 0x003FFFFF +#define PHYA_RXTD_GIC_CTRL_3_L___S 0 + +#define PHYA_RXTD_GIC_CTRL_4_L (0x003A01D8) +#define PHYA_RXTD_GIC_CTRL_4_L___RWC QCSR_REG_RW +#define PHYA_RXTD_GIC_CTRL_4_L___POR 0x00028050 +#define PHYA_RXTD_GIC_CTRL_4_L__GIC_HOLD_1___POR 0x050 +#define PHYA_RXTD_GIC_CTRL_4_L__GIC_HOLD_0___POR 0x050 +#define PHYA_RXTD_GIC_CTRL_4_L__GIC_HOLD_1___M 0x003FF800 +#define PHYA_RXTD_GIC_CTRL_4_L__GIC_HOLD_1___S 11 +#define PHYA_RXTD_GIC_CTRL_4_L__GIC_HOLD_0___M 0x000007FF +#define PHYA_RXTD_GIC_CTRL_4_L__GIC_HOLD_0___S 0 +#define PHYA_RXTD_GIC_CTRL_4_L___M 0x003FFFFF +#define PHYA_RXTD_GIC_CTRL_4_L___S 0 + +#define PHYA_RXTD_GIC_CTRL_5_L (0x003A01E0) +#define PHYA_RXTD_GIC_CTRL_5_L___RWC QCSR_REG_RW +#define PHYA_RXTD_GIC_CTRL_5_L___POR 0x000A0140 +#define PHYA_RXTD_GIC_CTRL_5_L__GIC_HOLD_3___POR 0x140 +#define PHYA_RXTD_GIC_CTRL_5_L__GIC_HOLD_2___POR 0x140 +#define PHYA_RXTD_GIC_CTRL_5_L__GIC_HOLD_3___M 0x003FF800 +#define PHYA_RXTD_GIC_CTRL_5_L__GIC_HOLD_3___S 11 +#define PHYA_RXTD_GIC_CTRL_5_L__GIC_HOLD_2___M 0x000007FF +#define PHYA_RXTD_GIC_CTRL_5_L__GIC_HOLD_2___S 0 +#define PHYA_RXTD_GIC_CTRL_5_L___M 0x003FFFFF +#define PHYA_RXTD_GIC_CTRL_5_L___S 0 + +#define PHYA_RXTD_GIC_CTRL_6_L (0x003A01E8) +#define PHYA_RXTD_GIC_CTRL_6_L___RWC QCSR_REG_RW +#define PHYA_RXTD_GIC_CTRL_6_L___POR 0x000A0140 +#define PHYA_RXTD_GIC_CTRL_6_L__GIC_HOLD_5___POR 0x140 +#define PHYA_RXTD_GIC_CTRL_6_L__GIC_HOLD_4___POR 0x140 +#define PHYA_RXTD_GIC_CTRL_6_L__GIC_HOLD_5___M 0x003FF800 +#define PHYA_RXTD_GIC_CTRL_6_L__GIC_HOLD_5___S 11 +#define PHYA_RXTD_GIC_CTRL_6_L__GIC_HOLD_4___M 0x000007FF +#define PHYA_RXTD_GIC_CTRL_6_L__GIC_HOLD_4___S 0 +#define PHYA_RXTD_GIC_CTRL_6_L___M 0x003FFFFF +#define PHYA_RXTD_GIC_CTRL_6_L___S 0 + +#define PHYA_RXTD_AGC_GAIN_SETTLING_1_L (0x003A01F0) +#define PHYA_RXTD_AGC_GAIN_SETTLING_1_L___RWC QCSR_REG_RW +#define PHYA_RXTD_AGC_GAIN_SETTLING_1_L___POR 0x0007000A +#define PHYA_RXTD_AGC_GAIN_SETTLING_1_L__RADIO_SETTLING_100NS___POR 0x0007 +#define PHYA_RXTD_AGC_GAIN_SETTLING_1_L__AGC_SIG_CHK_TIME_100NS___POR 0x000A +#define PHYA_RXTD_AGC_GAIN_SETTLING_1_L__RADIO_SETTLING_100NS___M 0xFFFF0000 +#define PHYA_RXTD_AGC_GAIN_SETTLING_1_L__RADIO_SETTLING_100NS___S 16 +#define PHYA_RXTD_AGC_GAIN_SETTLING_1_L__AGC_SIG_CHK_TIME_100NS___M 0x0000FFFF +#define PHYA_RXTD_AGC_GAIN_SETTLING_1_L__AGC_SIG_CHK_TIME_100NS___S 0 +#define PHYA_RXTD_AGC_GAIN_SETTLING_1_L___M 0xFFFFFFFF +#define PHYA_RXTD_AGC_GAIN_SETTLING_1_L___S 0 + +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_0_L (0x003A01F8) +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_0_L___RWC QCSR_REG_RW +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_0_L___POR 0x00000000 +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_0_L__XLNA_SETTLING1_100NS___POR 0x0000 +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_0_L__XLNA_SETTLING0_100NS___POR 0x0000 +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_0_L__XLNA_SETTLING1_100NS___M 0xFFFF0000 +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_0_L__XLNA_SETTLING1_100NS___S 16 +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_0_L__XLNA_SETTLING0_100NS___M 0x0000FFFF +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_0_L__XLNA_SETTLING0_100NS___S 0 +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_0_L___M 0xFFFFFFFF +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_0_L___S 0 + +#define PHYA_RXTD_AGC_GAIN_SETTLING_3_L (0x003A0200) +#define PHYA_RXTD_AGC_GAIN_SETTLING_3_L___RWC QCSR_REG_RW +#define PHYA_RXTD_AGC_GAIN_SETTLING_3_L___POR 0x00050000 +#define PHYA_RXTD_AGC_GAIN_SETTLING_3_L__AGC_SIG_CHK2_TIME_100NS___POR 0x0005 +#define PHYA_RXTD_AGC_GAIN_SETTLING_3_L__XLNA_SETTLING2_100NS___POR 0x0000 +#define PHYA_RXTD_AGC_GAIN_SETTLING_3_L__AGC_SIG_CHK2_TIME_100NS___M 0xFFFF0000 +#define PHYA_RXTD_AGC_GAIN_SETTLING_3_L__AGC_SIG_CHK2_TIME_100NS___S 16 +#define PHYA_RXTD_AGC_GAIN_SETTLING_3_L__XLNA_SETTLING2_100NS___M 0x0000FFFF +#define PHYA_RXTD_AGC_GAIN_SETTLING_3_L__XLNA_SETTLING2_100NS___S 0 +#define PHYA_RXTD_AGC_GAIN_SETTLING_3_L___M 0xFFFFFFFF +#define PHYA_RXTD_AGC_GAIN_SETTLING_3_L___S 0 + +#define PHYA_RXTD_AGC_GC_DELAY_L (0x003A0208) +#define PHYA_RXTD_AGC_GC_DELAY_L___RWC QCSR_REG_RW +#define PHYA_RXTD_AGC_GC_DELAY_L___POR 0x00000001 +#define PHYA_RXTD_AGC_GC_DELAY_L__MAX_CONSEC_GC___POR 0x1 +#define PHYA_RXTD_AGC_GC_DELAY_L__MAX_CONSEC_GC___M 0x0000000F +#define PHYA_RXTD_AGC_GC_DELAY_L__MAX_CONSEC_GC___S 0 +#define PHYA_RXTD_AGC_GC_DELAY_L___M 0x0000000F +#define PHYA_RXTD_AGC_GC_DELAY_L___S 0 + +#define PHYA_RXTD_PEAK_DET_CTRL_1_L (0x003A0210) +#define PHYA_RXTD_PEAK_DET_CTRL_1_L___RWC QCSR_REG_RW +#define PHYA_RXTD_PEAK_DET_CTRL_1_L___POR 0x00000001 +#define PHYA_RXTD_PEAK_DET_CTRL_1_L__XRF_GAIN_DROP_ENA___POR 0x0 +#define PHYA_RXTD_PEAK_DET_CTRL_1_L__USE_COMMON_RF_GAIN_DROP___POR 0x0 +#define PHYA_RXTD_PEAK_DET_CTRL_1_L__ENABLE_RFSAT_STRONG___POR 0x1 +#define PHYA_RXTD_PEAK_DET_CTRL_1_L__XRF_GAIN_DROP_ENA___M 0x00000004 +#define PHYA_RXTD_PEAK_DET_CTRL_1_L__XRF_GAIN_DROP_ENA___S 2 +#define PHYA_RXTD_PEAK_DET_CTRL_1_L__USE_COMMON_RF_GAIN_DROP___M 0x00000002 +#define PHYA_RXTD_PEAK_DET_CTRL_1_L__USE_COMMON_RF_GAIN_DROP___S 1 +#define PHYA_RXTD_PEAK_DET_CTRL_1_L__ENABLE_RFSAT_STRONG___M 0x00000001 +#define PHYA_RXTD_PEAK_DET_CTRL_1_L__ENABLE_RFSAT_STRONG___S 0 +#define PHYA_RXTD_PEAK_DET_CTRL_1_L___M 0x00000007 +#define PHYA_RXTD_PEAK_DET_CTRL_1_L___S 0 + +#define PHYA_RXTD_AGC_GAIN_FORCE_CTRL_L (0x003A0218) +#define PHYA_RXTD_AGC_GAIN_FORCE_CTRL_L___RWC QCSR_REG_RW +#define PHYA_RXTD_AGC_GAIN_FORCE_CTRL_L___POR 0x00000000 +#define PHYA_RXTD_AGC_GAIN_FORCE_CTRL_L__WAIT_ON_PWR_HIGH___POR 0x0 +#define PHYA_RXTD_AGC_GAIN_FORCE_CTRL_L__USE_FIXED_GAIN___POR 0x0 +#define PHYA_RXTD_AGC_GAIN_FORCE_CTRL_L__WAIT_ON_PWR_HIGH___M 0x00000002 +#define PHYA_RXTD_AGC_GAIN_FORCE_CTRL_L__WAIT_ON_PWR_HIGH___S 1 +#define PHYA_RXTD_AGC_GAIN_FORCE_CTRL_L__USE_FIXED_GAIN___M 0x00000001 +#define PHYA_RXTD_AGC_GAIN_FORCE_CTRL_L__USE_FIXED_GAIN___S 0 +#define PHYA_RXTD_AGC_GAIN_FORCE_CTRL_L___M 0x00000003 +#define PHYA_RXTD_AGC_GAIN_FORCE_CTRL_L___S 0 + +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_1_L (0x003A0220) +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_1_L___RWC QCSR_REG_RW +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_1_L___POR 0x00A01E3C +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_1_L__BTCF_TIMEOUT___POR 0x0A0 +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_1_L__BTCF_START_DELAY_100NS___POR 0x1E +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_1_L__VOTING_INTERVAL_100NS___POR 0x3C +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_1_L__BTCF_TIMEOUT___M 0x03FF0000 +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_1_L__BTCF_TIMEOUT___S 16 +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_1_L__BTCF_START_DELAY_100NS___M 0x0000FF00 +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_1_L__BTCF_START_DELAY_100NS___S 8 +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_1_L__VOTING_INTERVAL_100NS___M 0x000000FF +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_1_L__VOTING_INTERVAL_100NS___S 0 +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_1_L___M 0x03FFFFFF +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_1_L___S 0 + +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_1_U (0x003A0224) +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_1_U___RWC QCSR_REG_RW +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_1_U___POR 0x00005050 +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_1_U__WEAK_CTE_TIMEOUT_100NS___POR 0x50 +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_1_U__STR_CTE_TIMEOUT_100NS___POR 0x50 +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_1_U__WEAK_CTE_TIMEOUT_100NS___M 0x0000FF00 +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_1_U__WEAK_CTE_TIMEOUT_100NS___S 8 +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_1_U__STR_CTE_TIMEOUT_100NS___M 0x000000FF +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_1_U__STR_CTE_TIMEOUT_100NS___S 0 +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_1_U___M 0x0000FFFF +#define PHYA_RXTD_AGC_GAIN_SETTLING_2_1_U___S 0 + +#define PHYA_RXTD_AGC_UL_MU_CTRL_1_L (0x003A0228) +#define PHYA_RXTD_AGC_UL_MU_CTRL_1_L___RWC QCSR_REG_RW +#define PHYA_RXTD_AGC_UL_MU_CTRL_1_L___POR 0x00000000 +#define PHYA_RXTD_AGC_UL_MU_CTRL_1_L__UL_MU_AGC___POR 0x0 +#define PHYA_RXTD_AGC_UL_MU_CTRL_1_L__UL_MU_AGC___M 0x00000001 +#define PHYA_RXTD_AGC_UL_MU_CTRL_1_L__UL_MU_AGC___S 0 +#define PHYA_RXTD_AGC_UL_MU_CTRL_1_L___M 0x00000001 +#define PHYA_RXTD_AGC_UL_MU_CTRL_1_L___S 0 + +#define PHYA_RXTD_AGC_UL_MU_CTRL_1_U (0x003A022C) +#define PHYA_RXTD_AGC_UL_MU_CTRL_1_U___RWC QCSR_REG_RW +#define PHYA_RXTD_AGC_UL_MU_CTRL_1_U___POR 0x00000000 +#define PHYA_RXTD_AGC_UL_MU_CTRL_1_U__UL_MU_RX_FRAME_ASSERT___POR 0x0000 +#define PHYA_RXTD_AGC_UL_MU_CTRL_1_U__UL_MU_RX_FRAME_ASSERT___M 0x0000FFFF +#define PHYA_RXTD_AGC_UL_MU_CTRL_1_U__UL_MU_RX_FRAME_ASSERT___S 0 +#define PHYA_RXTD_AGC_UL_MU_CTRL_1_U___M 0x0000FFFF +#define PHYA_RXTD_AGC_UL_MU_CTRL_1_U___S 0 + +#define PHYA_RXTD_AGC_UL_MU_CTRL_2_L (0x003A0230) +#define PHYA_RXTD_AGC_UL_MU_CTRL_2_L___RWC QCSR_REG_RW +#define PHYA_RXTD_AGC_UL_MU_CTRL_2_L___POR 0x00000000 +#define PHYA_RXTD_AGC_UL_MU_CTRL_2_L__UL_MU_11A_DET___POR 0x0000 +#define PHYA_RXTD_AGC_UL_MU_CTRL_2_L__UL_MU_SEARCH_START___POR 0x0000 +#define PHYA_RXTD_AGC_UL_MU_CTRL_2_L__UL_MU_11A_DET___M 0xFFFF0000 +#define PHYA_RXTD_AGC_UL_MU_CTRL_2_L__UL_MU_11A_DET___S 16 +#define PHYA_RXTD_AGC_UL_MU_CTRL_2_L__UL_MU_SEARCH_START___M 0x0000FFFF +#define PHYA_RXTD_AGC_UL_MU_CTRL_2_L__UL_MU_SEARCH_START___S 0 +#define PHYA_RXTD_AGC_UL_MU_CTRL_2_L___M 0xFFFFFFFF +#define PHYA_RXTD_AGC_UL_MU_CTRL_2_L___S 0 + +#define PHYA_RXTD_AGC_SRCH_CTRL_1_L (0x003A0238) +#define PHYA_RXTD_AGC_SRCH_CTRL_1_L___RWC QCSR_REG_RW +#define PHYA_RXTD_AGC_SRCH_CTRL_1_L___POR 0x00000009 +#define PHYA_RXTD_AGC_SRCH_CTRL_1_L__BYPASS_XLNA_IN_LISTEN___POR 0x0 +#define PHYA_RXTD_AGC_SRCH_CTRL_1_L__USE_XLNA___POR 0x1 +#define PHYA_RXTD_AGC_SRCH_CTRL_1_L__PRI_PWR_INIT_MODE___POR 0x0 +#define PHYA_RXTD_AGC_SRCH_CTRL_1_L__GAIN_FORCE_ENA___POR 0x0 +#define PHYA_RXTD_AGC_SRCH_CTRL_1_L__ENABLE_SRCH_START_GAIN___POR 0x1 +#define PHYA_RXTD_AGC_SRCH_CTRL_1_L__BYPASS_XLNA_IN_LISTEN___M 0x00000010 +#define PHYA_RXTD_AGC_SRCH_CTRL_1_L__BYPASS_XLNA_IN_LISTEN___S 4 +#define PHYA_RXTD_AGC_SRCH_CTRL_1_L__USE_XLNA___M 0x00000008 +#define PHYA_RXTD_AGC_SRCH_CTRL_1_L__USE_XLNA___S 3 +#define PHYA_RXTD_AGC_SRCH_CTRL_1_L__PRI_PWR_INIT_MODE___M 0x00000004 +#define PHYA_RXTD_AGC_SRCH_CTRL_1_L__PRI_PWR_INIT_MODE___S 2 +#define PHYA_RXTD_AGC_SRCH_CTRL_1_L__GAIN_FORCE_ENA___M 0x00000002 +#define PHYA_RXTD_AGC_SRCH_CTRL_1_L__GAIN_FORCE_ENA___S 1 +#define PHYA_RXTD_AGC_SRCH_CTRL_1_L__ENABLE_SRCH_START_GAIN___M 0x00000001 +#define PHYA_RXTD_AGC_SRCH_CTRL_1_L__ENABLE_SRCH_START_GAIN___S 0 +#define PHYA_RXTD_AGC_SRCH_CTRL_1_L___M 0x0000001F +#define PHYA_RXTD_AGC_SRCH_CTRL_1_L___S 0 + +#define PHYA_RXTD_PEAK_DET_CTRL_2_L (0x003A0240) +#define PHYA_RXTD_PEAK_DET_CTRL_2_L___RWC QCSR_REG_RW +#define PHYA_RXTD_PEAK_DET_CTRL_2_L___POR 0x07823A28 +#define PHYA_RXTD_PEAK_DET_CTRL_2_L__RF_GAIN_DROP_DB_NO_ADCSAT___POR 0x0F +#define PHYA_RXTD_PEAK_DET_CTRL_2_L__XRF_GAIN_DROP_DB___POR 0x00 +#define PHYA_RXTD_PEAK_DET_CTRL_2_L__RF_GAIN_DROP_DB_NON___POR 0x23 +#define PHYA_RXTD_PEAK_DET_CTRL_2_L__RF_GAIN_DROP_DB_LOW___POR 0x28 +#define PHYA_RXTD_PEAK_DET_CTRL_2_L__RF_GAIN_DROP_DB_HIGH___POR 0x28 +#define PHYA_RXTD_PEAK_DET_CTRL_2_L__RF_GAIN_DROP_DB_NO_ADCSAT___M 0x1F800000 +#define PHYA_RXTD_PEAK_DET_CTRL_2_L__RF_GAIN_DROP_DB_NO_ADCSAT___S 23 +#define PHYA_RXTD_PEAK_DET_CTRL_2_L__XRF_GAIN_DROP_DB___M 0x007C0000 +#define PHYA_RXTD_PEAK_DET_CTRL_2_L__XRF_GAIN_DROP_DB___S 18 +#define PHYA_RXTD_PEAK_DET_CTRL_2_L__RF_GAIN_DROP_DB_NON___M 0x0003F000 +#define PHYA_RXTD_PEAK_DET_CTRL_2_L__RF_GAIN_DROP_DB_NON___S 12 +#define PHYA_RXTD_PEAK_DET_CTRL_2_L__RF_GAIN_DROP_DB_LOW___M 0x00000FC0 +#define PHYA_RXTD_PEAK_DET_CTRL_2_L__RF_GAIN_DROP_DB_LOW___S 6 +#define PHYA_RXTD_PEAK_DET_CTRL_2_L__RF_GAIN_DROP_DB_HIGH___M 0x0000003F +#define PHYA_RXTD_PEAK_DET_CTRL_2_L__RF_GAIN_DROP_DB_HIGH___S 0 +#define PHYA_RXTD_PEAK_DET_CTRL_2_L___M 0x1FFFFFFF +#define PHYA_RXTD_PEAK_DET_CTRL_2_L___S 0 + +#define PHYA_RXTD_PEAK_DET_CTRL_3_L (0x003A0248) +#define PHYA_RXTD_PEAK_DET_CTRL_3_L___RWC QCSR_REG_RW +#define PHYA_RXTD_PEAK_DET_CTRL_3_L___POR 0x003DE8E3 +#define PHYA_RXTD_PEAK_DET_CTRL_3_L__BB_GAIN_DROP_DB_NO_ADCSAT___POR 0x0F +#define PHYA_RXTD_PEAK_DET_CTRL_3_L__BB_GAIN_DROP_DB_NON___POR 0x1E +#define PHYA_RXTD_PEAK_DET_CTRL_3_L__BB_GAIN_DROP_DB_LOW___POR 0x23 +#define PHYA_RXTD_PEAK_DET_CTRL_3_L__BB_GAIN_DROP_DB_HIGH___POR 0x23 +#define PHYA_RXTD_PEAK_DET_CTRL_3_L__BB_GAIN_DROP_DB_NO_ADCSAT___M 0x00FC0000 +#define PHYA_RXTD_PEAK_DET_CTRL_3_L__BB_GAIN_DROP_DB_NO_ADCSAT___S 18 +#define PHYA_RXTD_PEAK_DET_CTRL_3_L__BB_GAIN_DROP_DB_NON___M 0x0003F000 +#define PHYA_RXTD_PEAK_DET_CTRL_3_L__BB_GAIN_DROP_DB_NON___S 12 +#define PHYA_RXTD_PEAK_DET_CTRL_3_L__BB_GAIN_DROP_DB_LOW___M 0x00000FC0 +#define PHYA_RXTD_PEAK_DET_CTRL_3_L__BB_GAIN_DROP_DB_LOW___S 6 +#define PHYA_RXTD_PEAK_DET_CTRL_3_L__BB_GAIN_DROP_DB_HIGH___M 0x0000003F +#define PHYA_RXTD_PEAK_DET_CTRL_3_L__BB_GAIN_DROP_DB_HIGH___S 0 +#define PHYA_RXTD_PEAK_DET_CTRL_3_L___M 0x00FFFFFF +#define PHYA_RXTD_PEAK_DET_CTRL_3_L___S 0 + +#define PHYA_RXTD_AGC_PWR_THR_L (0x003A0250) +#define PHYA_RXTD_AGC_PWR_THR_L___RWC QCSR_REG_RW +#define PHYA_RXTD_AGC_PWR_THR_L___POR 0x28FD9C9C +#define PHYA_RXTD_AGC_PWR_THR_L__PWRLOW_GAIN_THR_DB___POR 0x28 +#define PHYA_RXTD_AGC_PWR_THR_L__COARSE_HIGH_DB2___POR 0xFD +#define PHYA_RXTD_AGC_PWR_THR_L__FOUND_LOW_DB2___POR 0x9C +#define PHYA_RXTD_AGC_PWR_THR_L__COARSE_LOW_DB2___POR 0x9C +#define PHYA_RXTD_AGC_PWR_THR_L__PWRLOW_GAIN_THR_DB___M 0xFF000000 +#define PHYA_RXTD_AGC_PWR_THR_L__PWRLOW_GAIN_THR_DB___S 24 +#define PHYA_RXTD_AGC_PWR_THR_L__COARSE_HIGH_DB2___M 0x00FF0000 +#define PHYA_RXTD_AGC_PWR_THR_L__COARSE_HIGH_DB2___S 16 +#define PHYA_RXTD_AGC_PWR_THR_L__FOUND_LOW_DB2___M 0x0000FF00 +#define PHYA_RXTD_AGC_PWR_THR_L__FOUND_LOW_DB2___S 8 +#define PHYA_RXTD_AGC_PWR_THR_L__COARSE_LOW_DB2___M 0x000000FF +#define PHYA_RXTD_AGC_PWR_THR_L__COARSE_LOW_DB2___S 0 +#define PHYA_RXTD_AGC_PWR_THR_L___M 0xFFFFFFFF +#define PHYA_RXTD_AGC_PWR_THR_L___S 0 + +#define PHYA_RXTD_AGC_PWR_TARGET_1_L (0x003A0258) +#define PHYA_RXTD_AGC_PWR_TARGET_1_L___RWC QCSR_REG_RW +#define PHYA_RXTD_AGC_PWR_TARGET_1_L___POR 0x017ECEDA +#define PHYA_RXTD_AGC_PWR_TARGET_1_L__FOUND_LOW_ENA___POR 0x1 +#define PHYA_RXTD_AGC_PWR_TARGET_1_L__START_GAIN_OFFSET_DB2___POR 0x7E +#define PHYA_RXTD_AGC_PWR_TARGET_1_L__TOTAL_DESIRED_DB2___POR 0xCE +#define PHYA_RXTD_AGC_PWR_TARGET_1_L__COARSEPWR_CONST_DB2___POR 0xDA +#define PHYA_RXTD_AGC_PWR_TARGET_1_L__FOUND_LOW_ENA___M 0x01000000 +#define PHYA_RXTD_AGC_PWR_TARGET_1_L__FOUND_LOW_ENA___S 24 +#define PHYA_RXTD_AGC_PWR_TARGET_1_L__START_GAIN_OFFSET_DB2___M 0x00FF0000 +#define PHYA_RXTD_AGC_PWR_TARGET_1_L__START_GAIN_OFFSET_DB2___S 16 +#define PHYA_RXTD_AGC_PWR_TARGET_1_L__TOTAL_DESIRED_DB2___M 0x0000FF00 +#define PHYA_RXTD_AGC_PWR_TARGET_1_L__TOTAL_DESIRED_DB2___S 8 +#define PHYA_RXTD_AGC_PWR_TARGET_1_L__COARSEPWR_CONST_DB2___M 0x000000FF +#define PHYA_RXTD_AGC_PWR_TARGET_1_L__COARSEPWR_CONST_DB2___S 0 +#define PHYA_RXTD_AGC_PWR_TARGET_1_L___M 0x01FFFFFF +#define PHYA_RXTD_AGC_PWR_TARGET_1_L___S 0 + +#define PHYA_RXTD_AGC_PWR_TARGET_2_L (0x003A0260) +#define PHYA_RXTD_AGC_PWR_TARGET_2_L___RWC QCSR_REG_RW +#define PHYA_RXTD_AGC_PWR_TARGET_2_L___POR 0x06D6D001 +#define PHYA_RXTD_AGC_PWR_TARGET_2_L__ADC_SIZE_DESIRED_MIN_DB2___POR 0xDA +#define PHYA_RXTD_AGC_PWR_TARGET_2_L__ADC_SIZE_DESIRED_MAX_DB2___POR 0xDA +#define PHYA_RXTD_AGC_PWR_TARGET_2_L__RSSI_PRI_HIGH_THR_DB___POR 0x00 +#define PHYA_RXTD_AGC_PWR_TARGET_2_L__ALPHA_ADC_SIZE_RELPWR___POR 0x0 +#define PHYA_RXTD_AGC_PWR_TARGET_2_L__ALPHA_ADC_SIZE_RSSI___POR 0x1 +#define PHYA_RXTD_AGC_PWR_TARGET_2_L__ADC_SIZE_DESIRED_MIN_DB2___M 0x07F80000 +#define PHYA_RXTD_AGC_PWR_TARGET_2_L__ADC_SIZE_DESIRED_MIN_DB2___S 19 +#define PHYA_RXTD_AGC_PWR_TARGET_2_L__ADC_SIZE_DESIRED_MAX_DB2___M 0x0007F800 +#define PHYA_RXTD_AGC_PWR_TARGET_2_L__ADC_SIZE_DESIRED_MAX_DB2___S 11 +#define PHYA_RXTD_AGC_PWR_TARGET_2_L__RSSI_PRI_HIGH_THR_DB___M 0x000007F0 +#define PHYA_RXTD_AGC_PWR_TARGET_2_L__RSSI_PRI_HIGH_THR_DB___S 4 +#define PHYA_RXTD_AGC_PWR_TARGET_2_L__ALPHA_ADC_SIZE_RELPWR___M 0x0000000C +#define PHYA_RXTD_AGC_PWR_TARGET_2_L__ALPHA_ADC_SIZE_RELPWR___S 2 +#define PHYA_RXTD_AGC_PWR_TARGET_2_L__ALPHA_ADC_SIZE_RSSI___M 0x00000003 +#define PHYA_RXTD_AGC_PWR_TARGET_2_L__ALPHA_ADC_SIZE_RSSI___S 0 +#define PHYA_RXTD_AGC_PWR_TARGET_2_L___M 0x07FFFFFF +#define PHYA_RXTD_AGC_PWR_TARGET_2_L___S 0 + +#define PHYA_RXTD_AGC_PWR_TARGET_3_L (0x003A0268) +#define PHYA_RXTD_AGC_PWR_TARGET_3_L___RWC QCSR_REG_RW +#define PHYA_RXTD_AGC_PWR_TARGET_3_L___POR 0x0000DADA +#define PHYA_RXTD_AGC_PWR_TARGET_3_L__ADC_SIZE_DESIRED_CCK_MIN_DB2___POR 0xDA +#define PHYA_RXTD_AGC_PWR_TARGET_3_L__ADC_SIZE_DESIRED_CCK_MAX_DB2___POR 0xDA +#define PHYA_RXTD_AGC_PWR_TARGET_3_L__ADC_SIZE_DESIRED_CCK_MIN_DB2___M 0x0000FF00 +#define PHYA_RXTD_AGC_PWR_TARGET_3_L__ADC_SIZE_DESIRED_CCK_MIN_DB2___S 8 +#define PHYA_RXTD_AGC_PWR_TARGET_3_L__ADC_SIZE_DESIRED_CCK_MAX_DB2___M 0x000000FF +#define PHYA_RXTD_AGC_PWR_TARGET_3_L__ADC_SIZE_DESIRED_CCK_MAX_DB2___S 0 +#define PHYA_RXTD_AGC_PWR_TARGET_3_L___M 0x0000FFFF +#define PHYA_RXTD_AGC_PWR_TARGET_3_L___S 0 + +#define PHYA_RXTD_AGC_QUICKDROP_L (0x003A0270) +#define PHYA_RXTD_AGC_QUICKDROP_L___RWC QCSR_REG_RW +#define PHYA_RXTD_AGC_QUICKDROP_L___POR 0x00D8CECE +#define PHYA_RXTD_AGC_QUICKDROP_L__QUICKDROP_NON_DB2___POR 0xD8 +#define PHYA_RXTD_AGC_QUICKDROP_L__QUICKDROP_LOW_DB2___POR 0xCE +#define PHYA_RXTD_AGC_QUICKDROP_L__QUICKDROP_HIGH_DB2___POR 0xCE +#define PHYA_RXTD_AGC_QUICKDROP_L__QUICKDROP_NON_DB2___M 0x00FF0000 +#define PHYA_RXTD_AGC_QUICKDROP_L__QUICKDROP_NON_DB2___S 16 +#define PHYA_RXTD_AGC_QUICKDROP_L__QUICKDROP_LOW_DB2___M 0x0000FF00 +#define PHYA_RXTD_AGC_QUICKDROP_L__QUICKDROP_LOW_DB2___S 8 +#define PHYA_RXTD_AGC_QUICKDROP_L__QUICKDROP_HIGH_DB2___M 0x000000FF +#define PHYA_RXTD_AGC_QUICKDROP_L__QUICKDROP_HIGH_DB2___S 0 +#define PHYA_RXTD_AGC_QUICKDROP_L___M 0x00FFFFFF +#define PHYA_RXTD_AGC_QUICKDROP_L___S 0 + +#define PHYA_RXTD_AGC_PWR_HIGH_L (0x003A0278) +#define PHYA_RXTD_AGC_PWR_HIGH_L___RWC QCSR_REG_RW +#define PHYA_RXTD_AGC_PWR_HIGH_L___POR 0x0013E80A +#define PHYA_RXTD_AGC_PWR_HIGH_L__ENABLE_ADC_CHECK_WITH_PWRHIGH___POR 0x0 +#define PHYA_RXTD_AGC_PWR_HIGH_L__ENABLE_ADC_CHECK_WITH_ADCSAT___POR 0x0 +#define PHYA_RXTD_AGC_PWR_HIGH_L__ENABLE_ADC_CHECK_IN_BBSAT___POR 0x0 +#define PHYA_RXTD_AGC_PWR_HIGH_L__ENABLE_ADC_CHECK_IN_RFSAT___POR 0x0 +#define PHYA_RXTD_AGC_PWR_HIGH_L__PWR_HIGH_LEN___POR 0x4 +#define PHYA_RXTD_AGC_PWR_HIGH_L__SHIFT_THR_M___POR 0x1F4 +#define PHYA_RXTD_AGC_PWR_HIGH_L__SHIFT_THR_P___POR 0x00A +#define PHYA_RXTD_AGC_PWR_HIGH_L__ENABLE_ADC_CHECK_WITH_PWRHIGH___M 0x02000000 +#define PHYA_RXTD_AGC_PWR_HIGH_L__ENABLE_ADC_CHECK_WITH_PWRHIGH___S 25 +#define PHYA_RXTD_AGC_PWR_HIGH_L__ENABLE_ADC_CHECK_WITH_ADCSAT___M 0x01000000 +#define PHYA_RXTD_AGC_PWR_HIGH_L__ENABLE_ADC_CHECK_WITH_ADCSAT___S 24 +#define PHYA_RXTD_AGC_PWR_HIGH_L__ENABLE_ADC_CHECK_IN_BBSAT___M 0x00800000 +#define PHYA_RXTD_AGC_PWR_HIGH_L__ENABLE_ADC_CHECK_IN_BBSAT___S 23 +#define PHYA_RXTD_AGC_PWR_HIGH_L__ENABLE_ADC_CHECK_IN_RFSAT___M 0x00400000 +#define PHYA_RXTD_AGC_PWR_HIGH_L__ENABLE_ADC_CHECK_IN_RFSAT___S 22 +#define PHYA_RXTD_AGC_PWR_HIGH_L__PWR_HIGH_LEN___M 0x003C0000 +#define PHYA_RXTD_AGC_PWR_HIGH_L__PWR_HIGH_LEN___S 18 +#define PHYA_RXTD_AGC_PWR_HIGH_L__SHIFT_THR_M___M 0x0003FE00 +#define PHYA_RXTD_AGC_PWR_HIGH_L__SHIFT_THR_M___S 9 +#define PHYA_RXTD_AGC_PWR_HIGH_L__SHIFT_THR_P___M 0x000001FF +#define PHYA_RXTD_AGC_PWR_HIGH_L__SHIFT_THR_P___S 0 +#define PHYA_RXTD_AGC_PWR_HIGH_L___M 0x03FFFFFF +#define PHYA_RXTD_AGC_PWR_HIGH_L___S 0 + +#define PHYA_RXTD_BTCF_METRICS_1_0_L (0x003A0280) +#define PHYA_RXTD_BTCF_METRICS_1_0_L___RWC QCSR_REG_RW +#define PHYA_RXTD_BTCF_METRICS_1_0_L___POR 0x00000000 +#define PHYA_RXTD_BTCF_METRICS_1_0_L__BTCF_BR_POSTMIN_INDX___POR 0x00 +#define PHYA_RXTD_BTCF_METRICS_1_0_L__BTCF_BR_POSTMIN_INDX___M 0x0000001F +#define PHYA_RXTD_BTCF_METRICS_1_0_L__BTCF_BR_POSTMIN_INDX___S 0 +#define PHYA_RXTD_BTCF_METRICS_1_0_L___M 0x0000001F +#define PHYA_RXTD_BTCF_METRICS_1_0_L___S 0 + +#define PHYA_RXTD_BTCF_METRICS_1_0_U (0x003A0284) +#define PHYA_RXTD_BTCF_METRICS_1_0_U___RWC QCSR_REG_RO +#define PHYA_RXTD_BTCF_METRICS_1_0_U___POR 0x00000000 +#define PHYA_RXTD_BTCF_METRICS_1_0_U__BTCF_BR_VALUE___POR 0x00000000 +#define PHYA_RXTD_BTCF_METRICS_1_0_U__BTCF_BR_VALUE___M 0xFFFFFFFF +#define PHYA_RXTD_BTCF_METRICS_1_0_U__BTCF_BR_VALUE___S 0 +#define PHYA_RXTD_BTCF_METRICS_1_0_U___M 0xFFFFFFFF +#define PHYA_RXTD_BTCF_METRICS_1_0_U___S 0 + +#define PHYA_RXTD_BTCF_METRICS_1_1_L (0x003A0288) +#define PHYA_RXTD_BTCF_METRICS_1_1_L___RWC QCSR_REG_RW +#define PHYA_RXTD_BTCF_METRICS_1_1_L___POR 0x00000000 +#define PHYA_RXTD_BTCF_METRICS_1_1_L__BTCF_FREEZE___POR 0x0 +#define PHYA_RXTD_BTCF_METRICS_1_1_L__BTCF_BR_FFTSTART___POR 0x000 +#define PHYA_RXTD_BTCF_METRICS_1_1_L__BTCF_FREEZE___M 0x00010000 +#define PHYA_RXTD_BTCF_METRICS_1_1_L__BTCF_FREEZE___S 16 +#define PHYA_RXTD_BTCF_METRICS_1_1_L__BTCF_BR_FFTSTART___M 0x000003FF +#define PHYA_RXTD_BTCF_METRICS_1_1_L__BTCF_BR_FFTSTART___S 0 +#define PHYA_RXTD_BTCF_METRICS_1_1_L___M 0x000103FF +#define PHYA_RXTD_BTCF_METRICS_1_1_L___S 0 + +#define PHYA_RXTD_BTCF_METRICS_1_1_U (0x003A028C) +#define PHYA_RXTD_BTCF_METRICS_1_1_U___RWC QCSR_REG_RW +#define PHYA_RXTD_BTCF_METRICS_1_1_U___POR 0x00000FFF +#define PHYA_RXTD_BTCF_METRICS_1_1_U__FFT_DONE_TIMEOUT___POR 0x0FFF +#define PHYA_RXTD_BTCF_METRICS_1_1_U__FFT_DONE_TIMEOUT___M 0x0000FFFF +#define PHYA_RXTD_BTCF_METRICS_1_1_U__FFT_DONE_TIMEOUT___S 0 +#define PHYA_RXTD_BTCF_METRICS_1_1_U___M 0x0000FFFF +#define PHYA_RXTD_BTCF_METRICS_1_1_U___S 0 + +#define PHYA_RXTD_BTCF_CONFIG_4_L (0x003A0290) +#define PHYA_RXTD_BTCF_CONFIG_4_L___RWC QCSR_REG_RW +#define PHYA_RXTD_BTCF_CONFIG_4_L___POR 0x00000005 +#define PHYA_RXTD_BTCF_CONFIG_4_L__BTCF_FLOOR___POR 0x00000005 +#define PHYA_RXTD_BTCF_CONFIG_4_L__BTCF_FLOOR___M 0xFFFFFFFF +#define PHYA_RXTD_BTCF_CONFIG_4_L__BTCF_FLOOR___S 0 +#define PHYA_RXTD_BTCF_CONFIG_4_L___M 0xFFFFFFFF +#define PHYA_RXTD_BTCF_CONFIG_4_L___S 0 + +#define PHYA_RXTD_BTCF_CONFIG_4_U (0x003A0294) +#define PHYA_RXTD_BTCF_CONFIG_4_U___RWC QCSR_REG_RW +#define PHYA_RXTD_BTCF_CONFIG_4_U___POR 0x001F0000 +#define PHYA_RXTD_BTCF_CONFIG_4_U__BTCF_EARLY_FFT_START_COUNT___POR 0x1F +#define PHYA_RXTD_BTCF_CONFIG_4_U__BTCF_DELAY_SPREAD___POR 0x0000 +#define PHYA_RXTD_BTCF_CONFIG_4_U__BTCF_EARLY_FFT_START_COUNT___M 0x00FF0000 +#define PHYA_RXTD_BTCF_CONFIG_4_U__BTCF_EARLY_FFT_START_COUNT___S 16 +#define PHYA_RXTD_BTCF_CONFIG_4_U__BTCF_DELAY_SPREAD___M 0x0000FFFF +#define PHYA_RXTD_BTCF_CONFIG_4_U__BTCF_DELAY_SPREAD___S 0 +#define PHYA_RXTD_BTCF_CONFIG_4_U___M 0x00FFFFFF +#define PHYA_RXTD_BTCF_CONFIG_4_U___S 0 + +#define PHYA_RXTD_BTCF_CONFIG_5_L (0x003A0298) +#define PHYA_RXTD_BTCF_CONFIG_5_L___RWC QCSR_REG_RW +#define PHYA_RXTD_BTCF_CONFIG_5_L___POR 0x00000064 +#define PHYA_RXTD_BTCF_CONFIG_5_L__EN_BTCF_TIMER_AFTER_CTE___POR 0x0 +#define PHYA_RXTD_BTCF_CONFIG_5_L__BTCF_TIMER_AFTER_CTE_50NS___POR 0x64 +#define PHYA_RXTD_BTCF_CONFIG_5_L__EN_BTCF_TIMER_AFTER_CTE___M 0x00000100 +#define PHYA_RXTD_BTCF_CONFIG_5_L__EN_BTCF_TIMER_AFTER_CTE___S 8 +#define PHYA_RXTD_BTCF_CONFIG_5_L__BTCF_TIMER_AFTER_CTE_50NS___M 0x000000FF +#define PHYA_RXTD_BTCF_CONFIG_5_L__BTCF_TIMER_AFTER_CTE_50NS___S 0 +#define PHYA_RXTD_BTCF_CONFIG_5_L___M 0x000001FF +#define PHYA_RXTD_BTCF_CONFIG_5_L___S 0 + +#define PHYA_RXTD_CFO_EST_FORCE_CONFIG_L (0x003A02A0) +#define PHYA_RXTD_CFO_EST_FORCE_CONFIG_L___RWC QCSR_REG_RW +#define PHYA_RXTD_CFO_EST_FORCE_CONFIG_L___POR 0x00000000 +#define PHYA_RXTD_CFO_EST_FORCE_CONFIG_L__BTCF_FORCED_FINE_CFO_EST___POR 0x0000 +#define PHYA_RXTD_CFO_EST_FORCE_CONFIG_L__BTCF_FORCE_FINE_CFO_EST___POR 0x0 +#define PHYA_RXTD_CFO_EST_FORCE_CONFIG_L__BTCF_FORCED_FINE_CFO_EST___M 0x3FFF0000 +#define PHYA_RXTD_CFO_EST_FORCE_CONFIG_L__BTCF_FORCED_FINE_CFO_EST___S 16 +#define PHYA_RXTD_CFO_EST_FORCE_CONFIG_L__BTCF_FORCE_FINE_CFO_EST___M 0x00000001 +#define PHYA_RXTD_CFO_EST_FORCE_CONFIG_L__BTCF_FORCE_FINE_CFO_EST___S 0 +#define PHYA_RXTD_CFO_EST_FORCE_CONFIG_L___M 0x3FFF0001 +#define PHYA_RXTD_CFO_EST_FORCE_CONFIG_L___S 0 + +#define PHYA_RXTD_CFO_EST_FORCE_CONFIG_U (0x003A02A4) +#define PHYA_RXTD_CFO_EST_FORCE_CONFIG_U___RWC QCSR_REG_RW +#define PHYA_RXTD_CFO_EST_FORCE_CONFIG_U___POR 0x00000000 +#define PHYA_RXTD_CFO_EST_FORCE_CONFIG_U__FORCED_COARSE_CFO_EST___POR 0x0000 +#define PHYA_RXTD_CFO_EST_FORCE_CONFIG_U__FORCE_COARSE_CFO_EST___POR 0x0 +#define PHYA_RXTD_CFO_EST_FORCE_CONFIG_U__FORCED_COARSE_CFO_EST___M 0x3FFF0000 +#define PHYA_RXTD_CFO_EST_FORCE_CONFIG_U__FORCED_COARSE_CFO_EST___S 16 +#define PHYA_RXTD_CFO_EST_FORCE_CONFIG_U__FORCE_COARSE_CFO_EST___M 0x00000001 +#define PHYA_RXTD_CFO_EST_FORCE_CONFIG_U__FORCE_COARSE_CFO_EST___S 0 +#define PHYA_RXTD_CFO_EST_FORCE_CONFIG_U___M 0x3FFF0001 +#define PHYA_RXTD_CFO_EST_FORCE_CONFIG_U___S 0 + +#define PHYA_RXTD_CFO_CORR_FRAC_CONFIG_L (0x003A02A8) +#define PHYA_RXTD_CFO_CORR_FRAC_CONFIG_L___RWC QCSR_REG_RW +#define PHYA_RXTD_CFO_CORR_FRAC_CONFIG_L___POR 0x00000000 +#define PHYA_RXTD_CFO_CORR_FRAC_CONFIG_L__CFO_CORR_FRAC_PRI80___POR 0x000 +#define PHYA_RXTD_CFO_CORR_FRAC_CONFIG_L__CFO_CORR_FRAC_PRI40___POR 0x000 +#define PHYA_RXTD_CFO_CORR_FRAC_CONFIG_L__CFO_CORR_FRAC_EN___POR 0x0 +#define PHYA_RXTD_CFO_CORR_FRAC_CONFIG_L__CFO_CORR_FRAC_PRI80___M 0x01FFE000 +#define PHYA_RXTD_CFO_CORR_FRAC_CONFIG_L__CFO_CORR_FRAC_PRI80___S 13 +#define PHYA_RXTD_CFO_CORR_FRAC_CONFIG_L__CFO_CORR_FRAC_PRI40___M 0x00001FFE +#define PHYA_RXTD_CFO_CORR_FRAC_CONFIG_L__CFO_CORR_FRAC_PRI40___S 1 +#define PHYA_RXTD_CFO_CORR_FRAC_CONFIG_L__CFO_CORR_FRAC_EN___M 0x00000001 +#define PHYA_RXTD_CFO_CORR_FRAC_CONFIG_L__CFO_CORR_FRAC_EN___S 0 +#define PHYA_RXTD_CFO_CORR_FRAC_CONFIG_L___M 0x01FFFFFF +#define PHYA_RXTD_CFO_CORR_FRAC_CONFIG_L___S 0 + +#define PHYA_RXTD_CFO_CORR_FRAC_CONFIG_U (0x003A02AC) +#define PHYA_RXTD_CFO_CORR_FRAC_CONFIG_U___RWC QCSR_REG_RW +#define PHYA_RXTD_CFO_CORR_FRAC_CONFIG_U___POR 0x00000000 +#define PHYA_RXTD_CFO_CORR_FRAC_CONFIG_U__CFO_CORR_FRAC_PRI80_IN_160___POR 0x000 +#define PHYA_RXTD_CFO_CORR_FRAC_CONFIG_U__CFO_CORR_FRAC_SEC80___POR 0x000 +#define PHYA_RXTD_CFO_CORR_FRAC_CONFIG_U__CFO_CORR_FRAC_PRI80_IN_160___M 0x00FFF000 +#define PHYA_RXTD_CFO_CORR_FRAC_CONFIG_U__CFO_CORR_FRAC_PRI80_IN_160___S 12 +#define PHYA_RXTD_CFO_CORR_FRAC_CONFIG_U__CFO_CORR_FRAC_SEC80___M 0x00000FFF +#define PHYA_RXTD_CFO_CORR_FRAC_CONFIG_U__CFO_CORR_FRAC_SEC80___S 0 +#define PHYA_RXTD_CFO_CORR_FRAC_CONFIG_U___M 0x00FFFFFF +#define PHYA_RXTD_CFO_CORR_FRAC_CONFIG_U___S 0 + +#define PHYA_RXTD_TFEST_CONTROL_L (0x003A02B0) +#define PHYA_RXTD_TFEST_CONTROL_L___RWC QCSR_REG_RW +#define PHYA_RXTD_TFEST_CONTROL_L___POR 0x0000005F +#define PHYA_RXTD_TFEST_CONTROL_L__RX11B_TFEST_START_TIME___POR 0x5F +#define PHYA_RXTD_TFEST_CONTROL_L__RX11B_TFEST_START_TIME___M 0x0000007F +#define PHYA_RXTD_TFEST_CONTROL_L__RX11B_TFEST_START_TIME___S 0 +#define PHYA_RXTD_TFEST_CONTROL_L___M 0x0000007F +#define PHYA_RXTD_TFEST_CONTROL_L___S 0 + +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_1_L (0x003A02B8) +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_1_L___RWC QCSR_REG_RW +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_1_L___POR 0x01903000 +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_1_L__ILNA2_DB2___POR 0x019 +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_1_L__ILNA1_DB2___POR 0x00C +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_1_L__ILNA0_DB2___POR 0x000 +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_1_L__ILNA2_DB2___M 0x3FF00000 +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_1_L__ILNA2_DB2___S 20 +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_1_L__ILNA1_DB2___M 0x000FFC00 +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_1_L__ILNA1_DB2___S 10 +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_1_L__ILNA0_DB2___M 0x000003FF +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_1_L__ILNA0_DB2___S 0 +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_1_L___M 0x3FFFFFFF +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_1_L___S 0 + +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_2_L (0x003A02C0) +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_2_L___RWC QCSR_REG_RW +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_2_L___POR 0x0440CC27 +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_2_L__ILNA5_DB2___POR 0x044 +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_2_L__ILNA4_DB2___POR 0x033 +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_2_L__ILNA3_DB2___POR 0x027 +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_2_L__ILNA5_DB2___M 0x3FF00000 +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_2_L__ILNA5_DB2___S 20 +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_2_L__ILNA4_DB2___M 0x000FFC00 +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_2_L__ILNA4_DB2___S 10 +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_2_L__ILNA3_DB2___M 0x000003FF +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_2_L__ILNA3_DB2___S 0 +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_2_L___M 0x3FFFFFFF +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_2_L___S 0 + +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_3_L (0x003A02C8) +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_3_L___RWC QCSR_REG_RW +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_3_L___POR 0x00014451 +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_3_L__ILNA7_DB2___POR 0x051 +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_3_L__ILNA6_DB2___POR 0x051 +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_3_L__ILNA7_DB2___M 0x000FFC00 +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_3_L__ILNA7_DB2___S 10 +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_3_L__ILNA6_DB2___M 0x000003FF +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_3_L__ILNA6_DB2___S 0 +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_3_L___M 0x000FFFFF +#define PHYA_RXTD_BT_COEX_ILNA_GAIN_3_L___S 0 + +#define PHYA_RXTD_BT_COEX_XLNA_GAIN_L (0x003A02D0) +#define PHYA_RXTD_BT_COEX_XLNA_GAIN_L___RWC QCSR_REG_RW +#define PHYA_RXTD_BT_COEX_XLNA_GAIN_L___POR 0x0000483E +#define PHYA_RXTD_BT_COEX_XLNA_GAIN_L__XLNA2_DB2___POR 0x000 +#define PHYA_RXTD_BT_COEX_XLNA_GAIN_L__XLNA1_DB2___POR 0x012 +#define PHYA_RXTD_BT_COEX_XLNA_GAIN_L__XLNA0_DB2___POR 0x03E +#define PHYA_RXTD_BT_COEX_XLNA_GAIN_L__XLNA2_DB2___M 0x3FF00000 +#define PHYA_RXTD_BT_COEX_XLNA_GAIN_L__XLNA2_DB2___S 20 +#define PHYA_RXTD_BT_COEX_XLNA_GAIN_L__XLNA1_DB2___M 0x000FFC00 +#define PHYA_RXTD_BT_COEX_XLNA_GAIN_L__XLNA1_DB2___S 10 +#define PHYA_RXTD_BT_COEX_XLNA_GAIN_L__XLNA0_DB2___M 0x000003FF +#define PHYA_RXTD_BT_COEX_XLNA_GAIN_L__XLNA0_DB2___S 0 +#define PHYA_RXTD_BT_COEX_XLNA_GAIN_L___M 0x3FFFFFFF +#define PHYA_RXTD_BT_COEX_XLNA_GAIN_L___S 0 + +#define PHYA_RXTD_BT_COEX_CTRL_L (0x003A02D8) +#define PHYA_RXTD_BT_COEX_CTRL_L___RWC QCSR_REG_RW +#define PHYA_RXTD_BT_COEX_CTRL_L___POR 0x00000000 +#define PHYA_RXTD_BT_COEX_CTRL_L__BT_SHARED_ANT_MODE___POR 0x0 +#define PHYA_RXTD_BT_COEX_CTRL_L__WLAN_BT_PRIORITY_ENA___POR 0x0 +#define PHYA_RXTD_BT_COEX_CTRL_L__BT_RX_DISABLE_NF_CAL___POR 0x0 +#define PHYA_RXTD_BT_COEX_CTRL_L__BT_TX_DISABLE_NF_CAL___POR 0x0 +#define PHYA_RXTD_BT_COEX_CTRL_L__ENABLE_DYN_DEWEIGHT___POR 0x0 +#define PHYA_RXTD_BT_COEX_CTRL_L__ENABLE_STATIC_DEWEIGHT___POR 0x0 +#define PHYA_RXTD_BT_COEX_CTRL_L__ENABLE_BT_COEX___POR 0x0 +#define PHYA_RXTD_BT_COEX_CTRL_L__BT_SHARED_ANT_MODE___M 0x00000040 +#define PHYA_RXTD_BT_COEX_CTRL_L__BT_SHARED_ANT_MODE___S 6 +#define PHYA_RXTD_BT_COEX_CTRL_L__WLAN_BT_PRIORITY_ENA___M 0x00000020 +#define PHYA_RXTD_BT_COEX_CTRL_L__WLAN_BT_PRIORITY_ENA___S 5 +#define PHYA_RXTD_BT_COEX_CTRL_L__BT_RX_DISABLE_NF_CAL___M 0x00000010 +#define PHYA_RXTD_BT_COEX_CTRL_L__BT_RX_DISABLE_NF_CAL___S 4 +#define PHYA_RXTD_BT_COEX_CTRL_L__BT_TX_DISABLE_NF_CAL___M 0x00000008 +#define PHYA_RXTD_BT_COEX_CTRL_L__BT_TX_DISABLE_NF_CAL___S 3 +#define PHYA_RXTD_BT_COEX_CTRL_L__ENABLE_DYN_DEWEIGHT___M 0x00000004 +#define PHYA_RXTD_BT_COEX_CTRL_L__ENABLE_DYN_DEWEIGHT___S 2 +#define PHYA_RXTD_BT_COEX_CTRL_L__ENABLE_STATIC_DEWEIGHT___M 0x00000002 +#define PHYA_RXTD_BT_COEX_CTRL_L__ENABLE_STATIC_DEWEIGHT___S 1 +#define PHYA_RXTD_BT_COEX_CTRL_L__ENABLE_BT_COEX___M 0x00000001 +#define PHYA_RXTD_BT_COEX_CTRL_L__ENABLE_BT_COEX___S 0 +#define PHYA_RXTD_BT_COEX_CTRL_L___M 0x0000007F +#define PHYA_RXTD_BT_COEX_CTRL_L___S 0 + +#define PHYA_RXTD_BT_COEX_DET_FLAGS_L (0x003A02E0) +#define PHYA_RXTD_BT_COEX_DET_FLAGS_L___RWC QCSR_REG_RW +#define PHYA_RXTD_BT_COEX_DET_FLAGS_L___POR 0x00000000 +#define PHYA_RXTD_BT_COEX_DET_FLAGS_L__BT_RX_FIRPWR_INCR_DB2___POR 0x000 +#define PHYA_RXTD_BT_COEX_DET_FLAGS_L__BT_RX_FIRPWR_INCR_DB2___M 0x000003FF +#define PHYA_RXTD_BT_COEX_DET_FLAGS_L__BT_RX_FIRPWR_INCR_DB2___S 0 +#define PHYA_RXTD_BT_COEX_DET_FLAGS_L___M 0x000003FF +#define PHYA_RXTD_BT_COEX_DET_FLAGS_L___S 0 + +#define PHYA_RXTD_LISTEN_MASK_L (0x003A02E8) +#define PHYA_RXTD_LISTEN_MASK_L___RWC QCSR_REG_RW +#define PHYA_RXTD_LISTEN_MASK_L___POR 0x00000001 +#define PHYA_RXTD_LISTEN_MASK_L__LISTEN_VHT160_MODE___POR 0x0 +#define PHYA_RXTD_LISTEN_MASK_L__LISTEN_ADFS_MASK___POR 0x00 +#define PHYA_RXTD_LISTEN_MASK_L__LISTEN_SEC80_MASK___POR 0x00 +#define PHYA_RXTD_LISTEN_MASK_L__LISTEN_PRI80_MASK___POR 0x01 +#define PHYA_RXTD_LISTEN_MASK_L__LISTEN_VHT160_MODE___M 0x0F000000 +#define PHYA_RXTD_LISTEN_MASK_L__LISTEN_VHT160_MODE___S 24 +#define PHYA_RXTD_LISTEN_MASK_L__LISTEN_ADFS_MASK___M 0x00FF0000 +#define PHYA_RXTD_LISTEN_MASK_L__LISTEN_ADFS_MASK___S 16 +#define PHYA_RXTD_LISTEN_MASK_L__LISTEN_SEC80_MASK___M 0x0000FF00 +#define PHYA_RXTD_LISTEN_MASK_L__LISTEN_SEC80_MASK___S 8 +#define PHYA_RXTD_LISTEN_MASK_L__LISTEN_PRI80_MASK___M 0x000000FF +#define PHYA_RXTD_LISTEN_MASK_L__LISTEN_PRI80_MASK___S 0 +#define PHYA_RXTD_LISTEN_MASK_L___M 0x0FFFFFFF +#define PHYA_RXTD_LISTEN_MASK_L___S 0 + +#define PHYA_RXTD_RCV_MASK_0_L (0x003A02F0) +#define PHYA_RXTD_RCV_MASK_0_L___RWC QCSR_REG_RW +#define PHYA_RXTD_RCV_MASK_0_L___POR 0x00000001 +#define PHYA_RXTD_RCV_MASK_0_L__RCV80_VHT160_MODE___POR 0x0 +#define PHYA_RXTD_RCV_MASK_0_L__RCV80_ADFS_MASK___POR 0x00 +#define PHYA_RXTD_RCV_MASK_0_L__RCV80_SEC80_MASK___POR 0x00 +#define PHYA_RXTD_RCV_MASK_0_L__RCV80_PRI80_MASK___POR 0x01 +#define PHYA_RXTD_RCV_MASK_0_L__RCV80_VHT160_MODE___M 0x0F000000 +#define PHYA_RXTD_RCV_MASK_0_L__RCV80_VHT160_MODE___S 24 +#define PHYA_RXTD_RCV_MASK_0_L__RCV80_ADFS_MASK___M 0x00FF0000 +#define PHYA_RXTD_RCV_MASK_0_L__RCV80_ADFS_MASK___S 16 +#define PHYA_RXTD_RCV_MASK_0_L__RCV80_SEC80_MASK___M 0x0000FF00 +#define PHYA_RXTD_RCV_MASK_0_L__RCV80_SEC80_MASK___S 8 +#define PHYA_RXTD_RCV_MASK_0_L__RCV80_PRI80_MASK___M 0x000000FF +#define PHYA_RXTD_RCV_MASK_0_L__RCV80_PRI80_MASK___S 0 +#define PHYA_RXTD_RCV_MASK_0_L___M 0x0FFFFFFF +#define PHYA_RXTD_RCV_MASK_0_L___S 0 + +#define PHYA_RXTD_RCV_MASK_1_L (0x003A02F8) +#define PHYA_RXTD_RCV_MASK_1_L___RWC QCSR_REG_RW +#define PHYA_RXTD_RCV_MASK_1_L___POR 0x00000000 +#define PHYA_RXTD_RCV_MASK_1_L__RCV160_VHT160_MODE___POR 0x0 +#define PHYA_RXTD_RCV_MASK_1_L__RCV160_ADFS_MASK___POR 0x00 +#define PHYA_RXTD_RCV_MASK_1_L__RCV160_SEC80_MASK___POR 0x00 +#define PHYA_RXTD_RCV_MASK_1_L__RCV160_PRI80_MASK___POR 0x00 +#define PHYA_RXTD_RCV_MASK_1_L__RCV160_VHT160_MODE___M 0x0F000000 +#define PHYA_RXTD_RCV_MASK_1_L__RCV160_VHT160_MODE___S 24 +#define PHYA_RXTD_RCV_MASK_1_L__RCV160_ADFS_MASK___M 0x00FF0000 +#define PHYA_RXTD_RCV_MASK_1_L__RCV160_ADFS_MASK___S 16 +#define PHYA_RXTD_RCV_MASK_1_L__RCV160_SEC80_MASK___M 0x0000FF00 +#define PHYA_RXTD_RCV_MASK_1_L__RCV160_SEC80_MASK___S 8 +#define PHYA_RXTD_RCV_MASK_1_L__RCV160_PRI80_MASK___M 0x000000FF +#define PHYA_RXTD_RCV_MASK_1_L__RCV160_PRI80_MASK___S 0 +#define PHYA_RXTD_RCV_MASK_1_L___M 0x0FFFFFFF +#define PHYA_RXTD_RCV_MASK_1_L___S 0 + +#define PHYA_RXTD_ACK_RESPONSE_L (0x003A0300) +#define PHYA_RXTD_ACK_RESPONSE_L___RWC QCSR_REG_RW +#define PHYA_RXTD_ACK_RESPONSE_L___POR 0x00000000 +#define PHYA_RXTD_ACK_RESPONSE_L__ACK_RESPONSE_EN___POR 0x0 +#define PHYA_RXTD_ACK_RESPONSE_L__ACK_RESPONSE_FROM_MAC___POR 0x0 +#define PHYA_RXTD_ACK_RESPONSE_L__ACK_RESPONSE_EN___M 0x00000100 +#define PHYA_RXTD_ACK_RESPONSE_L__ACK_RESPONSE_EN___S 8 +#define PHYA_RXTD_ACK_RESPONSE_L__ACK_RESPONSE_FROM_MAC___M 0x00000003 +#define PHYA_RXTD_ACK_RESPONSE_L__ACK_RESPONSE_FROM_MAC___S 0 +#define PHYA_RXTD_ACK_RESPONSE_L___M 0x00000103 +#define PHYA_RXTD_ACK_RESPONSE_L___S 0 + +#define PHYA_RXTD_RXTD_CONTROL_CFG_L (0x003A0308) +#define PHYA_RXTD_RXTD_CONTROL_CFG_L___RWC QCSR_REG_RW +#define PHYA_RXTD_RXTD_CONTROL_CFG_L___POR 0x00000100 +#define PHYA_RXTD_RXTD_CONTROL_CFG_L__ACK_RESPONSE_TIMEOUT___POR 0x000 +#define PHYA_RXTD_RXTD_CONTROL_CFG_L__DIS_RADAR_DURING_RECEIVE___POR 0x1 +#define PHYA_RXTD_RXTD_CONTROL_CFG_L__RX_FRAME_ENABLE___POR 0x0 +#define PHYA_RXTD_RXTD_CONTROL_CFG_L__ACK_RESPONSE_TIMEOUT___M 0x0FFF0000 +#define PHYA_RXTD_RXTD_CONTROL_CFG_L__ACK_RESPONSE_TIMEOUT___S 16 +#define PHYA_RXTD_RXTD_CONTROL_CFG_L__DIS_RADAR_DURING_RECEIVE___M 0x00000100 +#define PHYA_RXTD_RXTD_CONTROL_CFG_L__DIS_RADAR_DURING_RECEIVE___S 8 +#define PHYA_RXTD_RXTD_CONTROL_CFG_L__RX_FRAME_ENABLE___M 0x00000001 +#define PHYA_RXTD_RXTD_CONTROL_CFG_L__RX_FRAME_ENABLE___S 0 +#define PHYA_RXTD_RXTD_CONTROL_CFG_L___M 0x0FFF0101 +#define PHYA_RXTD_RXTD_CONTROL_CFG_L___S 0 + +#define PHYA_RXTD_XBAR_L (0x003A0310) +#define PHYA_RXTD_XBAR_L___RWC QCSR_REG_RW +#define PHYA_RXTD_XBAR_L___POR 0x00FAC688 +#define PHYA_RXTD_XBAR_L__RX_XBAR_CTRL___POR 0xFAC688 +#define PHYA_RXTD_XBAR_L__RX_XBAR_CTRL___M 0x00FFFFFF +#define PHYA_RXTD_XBAR_L__RX_XBAR_CTRL___S 0 +#define PHYA_RXTD_XBAR_L___M 0x00FFFFFF +#define PHYA_RXTD_XBAR_L___S 0 + +#define PHYA_RXTD_XBAR_U (0x003A0314) +#define PHYA_RXTD_XBAR_U___RWC QCSR_REG_RW +#define PHYA_RXTD_XBAR_U___POR 0x000000FF +#define PHYA_RXTD_XBAR_U__RXTD_RX_CHAIN_ENABLE___POR 0xFF +#define PHYA_RXTD_XBAR_U__RXTD_RX_CHAIN_ENABLE___M 0x000000FF +#define PHYA_RXTD_XBAR_U__RXTD_RX_CHAIN_ENABLE___S 0 +#define PHYA_RXTD_XBAR_U___M 0x000000FF +#define PHYA_RXTD_XBAR_U___S 0 + +#define PHYA_RXTD_RX11B_DET_CTRL0_L (0x003A0318) +#define PHYA_RXTD_RX11B_DET_CTRL0_L___RWC QCSR_REG_RW +#define PHYA_RXTD_RX11B_DET_CTRL0_L___POR 0x7C0000DA +#define PHYA_RXTD_RX11B_DET_CTRL0_L__RX11B_DET_CORR_AVG___POR 0xF8 +#define PHYA_RXTD_RX11B_DET_CTRL0_L__RX11B_DET_SHIFT_S___POR 0x0 +#define PHYA_RXTD_RX11B_DET_CTRL0_L__RX11B_DET_SHIFT___POR 0x0 +#define PHYA_RXTD_RX11B_DET_CTRL0_L__RX11B_DAGC_INIT_GAIN___POR 0x00 +#define PHYA_RXTD_RX11B_DET_CTRL0_L__RX11B_DAGC_TARGET_PWR___POR 0xDA +#define PHYA_RXTD_RX11B_DET_CTRL0_L__RX11B_DET_CORR_AVG___M 0x7F800000 +#define PHYA_RXTD_RX11B_DET_CTRL0_L__RX11B_DET_CORR_AVG___S 23 +#define PHYA_RXTD_RX11B_DET_CTRL0_L__RX11B_DET_SHIFT_S___M 0x00780000 +#define PHYA_RXTD_RX11B_DET_CTRL0_L__RX11B_DET_SHIFT_S___S 19 +#define PHYA_RXTD_RX11B_DET_CTRL0_L__RX11B_DET_SHIFT___M 0x00078000 +#define PHYA_RXTD_RX11B_DET_CTRL0_L__RX11B_DET_SHIFT___S 15 +#define PHYA_RXTD_RX11B_DET_CTRL0_L__RX11B_DAGC_INIT_GAIN___M 0x00007F00 +#define PHYA_RXTD_RX11B_DET_CTRL0_L__RX11B_DAGC_INIT_GAIN___S 8 +#define PHYA_RXTD_RX11B_DET_CTRL0_L__RX11B_DAGC_TARGET_PWR___M 0x000000FF +#define PHYA_RXTD_RX11B_DET_CTRL0_L__RX11B_DAGC_TARGET_PWR___S 0 +#define PHYA_RXTD_RX11B_DET_CTRL0_L___M 0x7FFFFFFF +#define PHYA_RXTD_RX11B_DET_CTRL0_L___S 0 + +#define PHYA_RXTD_RX11B_DET_CTRL0_U (0x003A031C) +#define PHYA_RXTD_RX11B_DET_CTRL0_U___RWC QCSR_REG_RW +#define PHYA_RXTD_RX11B_DET_CTRL0_U___POR 0x00E8FF55 +#define PHYA_RXTD_RX11B_DET_CTRL0_U__RX11B_DET_PWR_AVG_S___POR 0xE8 +#define PHYA_RXTD_RX11B_DET_CTRL0_U__RX11B_DET_PWR_AVG___POR 0xFF +#define PHYA_RXTD_RX11B_DET_CTRL0_U__RX11B_DET_CORR_AVG_S___POR 0x55 +#define PHYA_RXTD_RX11B_DET_CTRL0_U__RX11B_DET_PWR_AVG_S___M 0x00FF0000 +#define PHYA_RXTD_RX11B_DET_CTRL0_U__RX11B_DET_PWR_AVG_S___S 16 +#define PHYA_RXTD_RX11B_DET_CTRL0_U__RX11B_DET_PWR_AVG___M 0x0000FF00 +#define PHYA_RXTD_RX11B_DET_CTRL0_U__RX11B_DET_PWR_AVG___S 8 +#define PHYA_RXTD_RX11B_DET_CTRL0_U__RX11B_DET_CORR_AVG_S___M 0x000000FF +#define PHYA_RXTD_RX11B_DET_CTRL0_U__RX11B_DET_CORR_AVG_S___S 0 +#define PHYA_RXTD_RX11B_DET_CTRL0_U___M 0x00FFFFFF +#define PHYA_RXTD_RX11B_DET_CTRL0_U___S 0 + +#define PHYA_RXTD_RX11B_DET_CTRL1_L (0x003A0320) +#define PHYA_RXTD_RX11B_DET_CTRL1_L___RWC QCSR_REG_RW +#define PHYA_RXTD_RX11B_DET_CTRL1_L___POR 0x00645A26 +#define PHYA_RXTD_RX11B_DET_CTRL1_L__RX11B_DET_CORR_THR_S___POR 0x32 +#define PHYA_RXTD_RX11B_DET_CTRL1_L__RX11B_DET_CORR_THR___POR 0x2D +#define PHYA_RXTD_RX11B_DET_CTRL1_L__RX11B_BLK_MAXCORB_THR___POR 0x026 +#define PHYA_RXTD_RX11B_DET_CTRL1_L__RX11B_DET_CORR_THR_S___M 0x01FE0000 +#define PHYA_RXTD_RX11B_DET_CTRL1_L__RX11B_DET_CORR_THR_S___S 17 +#define PHYA_RXTD_RX11B_DET_CTRL1_L__RX11B_DET_CORR_THR___M 0x0001FE00 +#define PHYA_RXTD_RX11B_DET_CTRL1_L__RX11B_DET_CORR_THR___S 9 +#define PHYA_RXTD_RX11B_DET_CTRL1_L__RX11B_BLK_MAXCORB_THR___M 0x000001FF +#define PHYA_RXTD_RX11B_DET_CTRL1_L__RX11B_BLK_MAXCORB_THR___S 0 +#define PHYA_RXTD_RX11B_DET_CTRL1_L___M 0x01FFFFFF +#define PHYA_RXTD_RX11B_DET_CTRL1_L___S 0 + +#define PHYA_RXTD_RX11B_DET_CTRL1_U (0x003A0324) +#define PHYA_RXTD_RX11B_DET_CTRL1_U___RWC QCSR_REG_RW +#define PHYA_RXTD_RX11B_DET_CTRL1_U___POR 0x025B2214 +#define PHYA_RXTD_RX11B_DET_CTRL1_U__RX11B_CHANNEL_FREQ___POR 0x096C +#define PHYA_RXTD_RX11B_DET_CTRL1_U__RX11B_INBAND_PWR_BLK_THR___POR 0x4 +#define PHYA_RXTD_RX11B_DET_CTRL1_U__RX11B_VOTE_SUP_TIME___POR 0x2 +#define PHYA_RXTD_RX11B_DET_CTRL1_U__RX11B_DET_CORR_TFEST_THR___POR 0x14 +#define PHYA_RXTD_RX11B_DET_CTRL1_U__RX11B_CHANNEL_FREQ___M 0x07FFC000 +#define PHYA_RXTD_RX11B_DET_CTRL1_U__RX11B_CHANNEL_FREQ___S 14 +#define PHYA_RXTD_RX11B_DET_CTRL1_U__RX11B_INBAND_PWR_BLK_THR___M 0x00003800 +#define PHYA_RXTD_RX11B_DET_CTRL1_U__RX11B_INBAND_PWR_BLK_THR___S 11 +#define PHYA_RXTD_RX11B_DET_CTRL1_U__RX11B_VOTE_SUP_TIME___M 0x00000700 +#define PHYA_RXTD_RX11B_DET_CTRL1_U__RX11B_VOTE_SUP_TIME___S 8 +#define PHYA_RXTD_RX11B_DET_CTRL1_U__RX11B_DET_CORR_TFEST_THR___M 0x000000FF +#define PHYA_RXTD_RX11B_DET_CTRL1_U__RX11B_DET_CORR_TFEST_THR___S 0 +#define PHYA_RXTD_RX11B_DET_CTRL1_U___M 0x07FFFFFF +#define PHYA_RXTD_RX11B_DET_CTRL1_U___S 0 + +#define PHYA_RXTD_RX11B_PLL_FREQ_OFFSET_L (0x003A0328) +#define PHYA_RXTD_RX11B_PLL_FREQ_OFFSET_L___RWC QCSR_REG_RW +#define PHYA_RXTD_RX11B_PLL_FREQ_OFFSET_L___POR 0x00000000 +#define PHYA_RXTD_RX11B_PLL_FREQ_OFFSET_L__RX11B_PLL_FREQ_OFFSET___POR 0x000 +#define PHYA_RXTD_RX11B_PLL_FREQ_OFFSET_L__RX11B_PLL_FREQ_OFFSET___M 0x000001FF +#define PHYA_RXTD_RX11B_PLL_FREQ_OFFSET_L__RX11B_PLL_FREQ_OFFSET___S 0 +#define PHYA_RXTD_RX11B_PLL_FREQ_OFFSET_L___M 0x000001FF +#define PHYA_RXTD_RX11B_PLL_FREQ_OFFSET_L___S 0 + +#define PHYA_RXTD_RXB_RX_RESET_L (0x003A0330) +#define PHYA_RXTD_RXB_RX_RESET_L___RWC QCSR_REG_RW +#define PHYA_RXTD_RXB_RX_RESET_L___POR 0x00000000 +#define PHYA_RXTD_RXB_RX_RESET_L__RBAPB_RBCTL_RESET___POR 0x0 +#define PHYA_RXTD_RXB_RX_RESET_L__RBAPB_RBCTL_RESET___M 0x00000001 +#define PHYA_RXTD_RXB_RX_RESET_L__RBAPB_RBCTL_RESET___S 0 +#define PHYA_RXTD_RXB_RX_RESET_L___M 0x00000001 +#define PHYA_RXTD_RXB_RX_RESET_L___S 0 + +#define PHYA_RXTD_RXB_RX_CONFIG_1_L (0x003A0338) +#define PHYA_RXTD_RXB_RX_CONFIG_1_L___RWC QCSR_REG_RW +#define PHYA_RXTD_RXB_RX_CONFIG_1_L___POR 0x02B49EDE +#define PHYA_RXTD_RXB_RX_CONFIG_1_L__RBAPB_RBBRK_TE_TH___POR 0x2 +#define PHYA_RXTD_RXB_RX_CONFIG_1_L__RBAPB_RBRSM_USE_FEEDBACK___POR 0x1 +#define PHYA_RXTD_RXB_RX_CONFIG_1_L__RBAPB_RBLMS_MU_SH___POR 0x3 +#define PHYA_RXTD_RXB_RX_CONFIG_1_L__RBAPB_RBCMF_PLL_COEFF_B___POR 0x127 +#define PHYA_RXTD_RXB_RX_CONFIG_1_L__RBAPB_RBCMF_PLL_COEFF_A___POR 0x2DE +#define PHYA_RXTD_RXB_RX_CONFIG_1_L__RBAPB_RBBRK_TE_TH___M 0x03000000 +#define PHYA_RXTD_RXB_RX_CONFIG_1_L__RBAPB_RBBRK_TE_TH___S 24 +#define PHYA_RXTD_RXB_RX_CONFIG_1_L__RBAPB_RBRSM_USE_FEEDBACK___M 0x00800000 +#define PHYA_RXTD_RXB_RX_CONFIG_1_L__RBAPB_RBRSM_USE_FEEDBACK___S 23 +#define PHYA_RXTD_RXB_RX_CONFIG_1_L__RBAPB_RBLMS_MU_SH___M 0x00700000 +#define PHYA_RXTD_RXB_RX_CONFIG_1_L__RBAPB_RBLMS_MU_SH___S 20 +#define PHYA_RXTD_RXB_RX_CONFIG_1_L__RBAPB_RBCMF_PLL_COEFF_B___M 0x000FFC00 +#define PHYA_RXTD_RXB_RX_CONFIG_1_L__RBAPB_RBCMF_PLL_COEFF_B___S 10 +#define PHYA_RXTD_RXB_RX_CONFIG_1_L__RBAPB_RBCMF_PLL_COEFF_A___M 0x000003FF +#define PHYA_RXTD_RXB_RX_CONFIG_1_L__RBAPB_RBCMF_PLL_COEFF_A___S 0 +#define PHYA_RXTD_RXB_RX_CONFIG_1_L___M 0x03FFFFFF +#define PHYA_RXTD_RXB_RX_CONFIG_1_L___S 0 + +#define PHYA_RXTD_RXB_RX_CONFIG_2_L (0x003A0340) +#define PHYA_RXTD_RXB_RX_CONFIG_2_L___RWC QCSR_REG_RW +#define PHYA_RXTD_RXB_RX_CONFIG_2_L___POR 0x0000107D +#define PHYA_RXTD_RXB_RX_CONFIG_2_L__AGC_RBCTL_D_AGC_B___POR 0x10 +#define PHYA_RXTD_RXB_RX_CONFIG_2_L__RBAPB_RBCTL_SFD_DET_TMO___POR 0x7D +#define PHYA_RXTD_RXB_RX_CONFIG_2_L__AGC_RBCTL_D_AGC_B___M 0x00003F00 +#define PHYA_RXTD_RXB_RX_CONFIG_2_L__AGC_RBCTL_D_AGC_B___S 8 +#define PHYA_RXTD_RXB_RX_CONFIG_2_L__RBAPB_RBCTL_SFD_DET_TMO___M 0x000000FF +#define PHYA_RXTD_RXB_RX_CONFIG_2_L__RBAPB_RBCTL_SFD_DET_TMO___S 0 +#define PHYA_RXTD_RXB_RX_CONFIG_2_L___M 0x00003FFF +#define PHYA_RXTD_RXB_RX_CONFIG_2_L___S 0 + +#define PHYA_RXTD_RXB_RX_DISABLES_L (0x003A0348) +#define PHYA_RXTD_RXB_RX_DISABLES_L___RWC QCSR_REG_RW +#define PHYA_RXTD_RXB_RX_DISABLES_L___POR 0x000000FB +#define PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBDSCR_DISABLE_SSFD_DETECT___POR 0x0 +#define PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBDSCR_BYPASS_DSC___POR 0x0 +#define PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBHPC_IGN_SIG___POR 0x0 +#define PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBHPC_IGN_SVC___POR 0x0 +#define PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBHPC_IGN_CRC___POR 0x0 +#define PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBHPC_SVC_MASK___POR 0xFB +#define PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBDSCR_DISABLE_SSFD_DETECT___M 0x00001000 +#define PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBDSCR_DISABLE_SSFD_DETECT___S 12 +#define PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBDSCR_BYPASS_DSC___M 0x00000800 +#define PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBDSCR_BYPASS_DSC___S 11 +#define PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBHPC_IGN_SIG___M 0x00000400 +#define PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBHPC_IGN_SIG___S 10 +#define PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBHPC_IGN_SVC___M 0x00000200 +#define PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBHPC_IGN_SVC___S 9 +#define PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBHPC_IGN_CRC___M 0x00000100 +#define PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBHPC_IGN_CRC___S 8 +#define PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBHPC_SVC_MASK___M 0x000000FF +#define PHYA_RXTD_RXB_RX_DISABLES_L__RBAPB_RBHPC_SVC_MASK___S 0 +#define PHYA_RXTD_RXB_RX_DISABLES_L___M 0x00001FFF +#define PHYA_RXTD_RXB_RX_DISABLES_L___S 0 + +#define PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L (0x003A0350) +#define PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L___RWC QCSR_REG_RW +#define PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L___POR 0x00002819 +#define PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L__RBAPB_RBCCK_HANDOFF_AVERAGER_GAIN___POR 0x2 +#define PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L__RBAPB_RBBRK_HANDOFF_AVERAGER_GAIN___POR 0x2 +#define PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L__RBAPB_RBBRK_ANTSEL_AVERAGER_GAIN___POR 0x0 +#define PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L__RBAPB_RBCTL_ANT_SEL_MODE___POR 0x0 +#define PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L__RBAPB_RBCTL_SNR_THRESHOLD___POR 0x19 +#define PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L__RBAPB_RBCCK_HANDOFF_AVERAGER_GAIN___M 0x00003000 +#define PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L__RBAPB_RBCCK_HANDOFF_AVERAGER_GAIN___S 12 +#define PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L__RBAPB_RBBRK_HANDOFF_AVERAGER_GAIN___M 0x00000C00 +#define PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L__RBAPB_RBBRK_HANDOFF_AVERAGER_GAIN___S 10 +#define PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L__RBAPB_RBBRK_ANTSEL_AVERAGER_GAIN___M 0x00000300 +#define PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L__RBAPB_RBBRK_ANTSEL_AVERAGER_GAIN___S 8 +#define PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L__RBAPB_RBCTL_ANT_SEL_MODE___M 0x000000C0 +#define PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L__RBAPB_RBCTL_ANT_SEL_MODE___S 6 +#define PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L__RBAPB_RBCTL_SNR_THRESHOLD___M 0x0000003F +#define PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L__RBAPB_RBCTL_SNR_THRESHOLD___S 0 +#define PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L___M 0x00003FFF +#define PHYA_RXTD_RXB_RX_DIVERSITY_MODE_L___S 0 + +#define PHYA_RXTD_RXB_RX_SSFD_LSFD_L (0x003A0358) +#define PHYA_RXTD_RXB_RX_SSFD_LSFD_L___RWC QCSR_REG_RO +#define PHYA_RXTD_RXB_RX_SSFD_LSFD_L___POR 0x00000000 +#define PHYA_RXTD_RXB_RX_SSFD_LSFD_L__RBDSCR_RBAPB_SSFD_COUNT___POR 0x0000 +#define PHYA_RXTD_RXB_RX_SSFD_LSFD_L__RBDSCR_RBAPB_LSFD_COUNT___POR 0x0000 +#define PHYA_RXTD_RXB_RX_SSFD_LSFD_L__RBDSCR_RBAPB_SSFD_COUNT___M 0xFFFF0000 +#define PHYA_RXTD_RXB_RX_SSFD_LSFD_L__RBDSCR_RBAPB_SSFD_COUNT___S 16 +#define PHYA_RXTD_RXB_RX_SSFD_LSFD_L__RBDSCR_RBAPB_LSFD_COUNT___M 0x0000FFFF +#define PHYA_RXTD_RXB_RX_SSFD_LSFD_L__RBDSCR_RBAPB_LSFD_COUNT___S 0 +#define PHYA_RXTD_RXB_RX_SSFD_LSFD_L___M 0xFFFFFFFF +#define PHYA_RXTD_RXB_RX_SSFD_LSFD_L___S 0 + +#define PHYA_RXTD_RXB_RX_SIG_SVC_ERRORS_L (0x003A0360) +#define PHYA_RXTD_RXB_RX_SIG_SVC_ERRORS_L___RWC QCSR_REG_RO +#define PHYA_RXTD_RXB_RX_SIG_SVC_ERRORS_L___POR 0x00000000 +#define PHYA_RXTD_RXB_RX_SIG_SVC_ERRORS_L__RBHPC_RBAPB_SVC_ERRORS_COUNT___POR 0x0000 +#define PHYA_RXTD_RXB_RX_SIG_SVC_ERRORS_L__RBHPC_RBAPB_SIG_ERRORS_COUNT___POR 0x0000 +#define PHYA_RXTD_RXB_RX_SIG_SVC_ERRORS_L__RBHPC_RBAPB_SVC_ERRORS_COUNT___M 0xFFFF0000 +#define PHYA_RXTD_RXB_RX_SIG_SVC_ERRORS_L__RBHPC_RBAPB_SVC_ERRORS_COUNT___S 16 +#define PHYA_RXTD_RXB_RX_SIG_SVC_ERRORS_L__RBHPC_RBAPB_SIG_ERRORS_COUNT___M 0x0000FFFF +#define PHYA_RXTD_RXB_RX_SIG_SVC_ERRORS_L__RBHPC_RBAPB_SIG_ERRORS_COUNT___S 0 +#define PHYA_RXTD_RXB_RX_SIG_SVC_ERRORS_L___M 0xFFFFFFFF +#define PHYA_RXTD_RXB_RX_SIG_SVC_ERRORS_L___S 0 + +#define PHYA_RXTD_RXB_RX_CRC_ERRORS_L (0x003A0368) +#define PHYA_RXTD_RXB_RX_CRC_ERRORS_L___RWC QCSR_REG_RO +#define PHYA_RXTD_RXB_RX_CRC_ERRORS_L___POR 0x00000000 +#define PHYA_RXTD_RXB_RX_CRC_ERRORS_L__RBHPC_RBAPB_CRC_ERRORS_COUNT___POR 0x0000 +#define PHYA_RXTD_RXB_RX_CRC_ERRORS_L__RBHPC_RBAPB_CRC_ERRORS_COUNT___M 0x0000FFFF +#define PHYA_RXTD_RXB_RX_CRC_ERRORS_L__RBHPC_RBAPB_CRC_ERRORS_COUNT___S 0 +#define PHYA_RXTD_RXB_RX_CRC_ERRORS_L___M 0x0000FFFF +#define PHYA_RXTD_RXB_RX_CRC_ERRORS_L___S 0 + +#define PHYA_RXTD_RXB_RX_BYTES_L (0x003A0370) +#define PHYA_RXTD_RXB_RX_BYTES_L___RWC QCSR_REG_RO +#define PHYA_RXTD_RXB_RX_BYTES_L___POR 0x00000000 +#define PHYA_RXTD_RXB_RX_BYTES_L__RBHPC_RBAPB_RX_RATE_1M___POR 0x0 +#define PHYA_RXTD_RXB_RX_BYTES_L__RBHPC_RBAPB_RX_RATE_2M___POR 0x0 +#define PHYA_RXTD_RXB_RX_BYTES_L__RBHPC_RBAPB_RX_RATE_5P5M___POR 0x0 +#define PHYA_RXTD_RXB_RX_BYTES_L__RBHPC_RBAPB_RX_RATE_11M___POR 0x0 +#define PHYA_RXTD_RXB_RX_BYTES_L__RBHPC_RBAPB_RX_BYTES_COUNT___POR 0x0000 +#define PHYA_RXTD_RXB_RX_BYTES_L__RBHPC_RBAPB_RX_RATE_1M___M 0xF0000000 +#define PHYA_RXTD_RXB_RX_BYTES_L__RBHPC_RBAPB_RX_RATE_1M___S 28 +#define PHYA_RXTD_RXB_RX_BYTES_L__RBHPC_RBAPB_RX_RATE_2M___M 0x0F000000 +#define PHYA_RXTD_RXB_RX_BYTES_L__RBHPC_RBAPB_RX_RATE_2M___S 24 +#define PHYA_RXTD_RXB_RX_BYTES_L__RBHPC_RBAPB_RX_RATE_5P5M___M 0x00F00000 +#define PHYA_RXTD_RXB_RX_BYTES_L__RBHPC_RBAPB_RX_RATE_5P5M___S 20 +#define PHYA_RXTD_RXB_RX_BYTES_L__RBHPC_RBAPB_RX_RATE_11M___M 0x000F0000 +#define PHYA_RXTD_RXB_RX_BYTES_L__RBHPC_RBAPB_RX_RATE_11M___S 16 +#define PHYA_RXTD_RXB_RX_BYTES_L__RBHPC_RBAPB_RX_BYTES_COUNT___M 0x0000FFFF +#define PHYA_RXTD_RXB_RX_BYTES_L__RBHPC_RBAPB_RX_BYTES_COUNT___S 0 +#define PHYA_RXTD_RXB_RX_BYTES_L___M 0xFFFFFFFF +#define PHYA_RXTD_RXB_RX_BYTES_L___S 0 + +#define PHYA_RXTD_RXB_MPI_SOF_EOF_L (0x003A0378) +#define PHYA_RXTD_RXB_MPI_SOF_EOF_L___RWC QCSR_REG_RO +#define PHYA_RXTD_RXB_MPI_SOF_EOF_L___POR 0x00000000 +#define PHYA_RXTD_RXB_MPI_SOF_EOF_L__RBHPC_RBAPB_PMI_EOF_COUNT___POR 0x0000 +#define PHYA_RXTD_RXB_MPI_SOF_EOF_L__RBHPC_RBAPB_PMI_SOF_COUNT___POR 0x0000 +#define PHYA_RXTD_RXB_MPI_SOF_EOF_L__RBHPC_RBAPB_PMI_EOF_COUNT___M 0xFFFF0000 +#define PHYA_RXTD_RXB_MPI_SOF_EOF_L__RBHPC_RBAPB_PMI_EOF_COUNT___S 16 +#define PHYA_RXTD_RXB_MPI_SOF_EOF_L__RBHPC_RBAPB_PMI_SOF_COUNT___M 0x0000FFFF +#define PHYA_RXTD_RXB_MPI_SOF_EOF_L__RBHPC_RBAPB_PMI_SOF_COUNT___S 0 +#define PHYA_RXTD_RXB_MPI_SOF_EOF_L___M 0xFFFFFFFF +#define PHYA_RXTD_RXB_MPI_SOF_EOF_L___S 0 + +#define PHYA_RXTD_RXB_START_ABORT_L (0x003A0380) +#define PHYA_RXTD_RXB_START_ABORT_L___RWC QCSR_REG_RO +#define PHYA_RXTD_RXB_START_ABORT_L___POR 0x00000000 +#define PHYA_RXTD_RXB_START_ABORT_L__RBCTL_RBAPB_RXB_ABORT_COUNT___POR 0x0000 +#define PHYA_RXTD_RXB_START_ABORT_L__RBCTL_RBAPB_RXB_START_COUNT___POR 0x0000 +#define PHYA_RXTD_RXB_START_ABORT_L__RBCTL_RBAPB_RXB_ABORT_COUNT___M 0xFFFF0000 +#define PHYA_RXTD_RXB_START_ABORT_L__RBCTL_RBAPB_RXB_ABORT_COUNT___S 16 +#define PHYA_RXTD_RXB_START_ABORT_L__RBCTL_RBAPB_RXB_START_COUNT___M 0x0000FFFF +#define PHYA_RXTD_RXB_START_ABORT_L__RBCTL_RBAPB_RXB_START_COUNT___S 0 +#define PHYA_RXTD_RXB_START_ABORT_L___M 0xFFFFFFFF +#define PHYA_RXTD_RXB_START_ABORT_L___S 0 + +#define PHYA_RXTD_RXB_DYNSEL_ANT0_ANT1_L (0x003A0388) +#define PHYA_RXTD_RXB_DYNSEL_ANT0_ANT1_L___RWC QCSR_REG_RO +#define PHYA_RXTD_RXB_DYNSEL_ANT0_ANT1_L___POR 0x00000000 +#define PHYA_RXTD_RXB_DYNSEL_ANT0_ANT1_L__RBCTL_RBAPB_ANT1_CNT___POR 0x0000 +#define PHYA_RXTD_RXB_DYNSEL_ANT0_ANT1_L__RBCTL_RBAPB_ANT0_CNT___POR 0x0000 +#define PHYA_RXTD_RXB_DYNSEL_ANT0_ANT1_L__RBCTL_RBAPB_ANT1_CNT___M 0xFFFF0000 +#define PHYA_RXTD_RXB_DYNSEL_ANT0_ANT1_L__RBCTL_RBAPB_ANT1_CNT___S 16 +#define PHYA_RXTD_RXB_DYNSEL_ANT0_ANT1_L__RBCTL_RBAPB_ANT0_CNT___M 0x0000FFFF +#define PHYA_RXTD_RXB_DYNSEL_ANT0_ANT1_L__RBCTL_RBAPB_ANT0_CNT___S 0 +#define PHYA_RXTD_RXB_DYNSEL_ANT0_ANT1_L___M 0xFFFFFFFF +#define PHYA_RXTD_RXB_DYNSEL_ANT0_ANT1_L___S 0 + +#define PHYA_RXTD_RXB_DYNSEL_ANT2_ANT3_L (0x003A0390) +#define PHYA_RXTD_RXB_DYNSEL_ANT2_ANT3_L___RWC QCSR_REG_RO +#define PHYA_RXTD_RXB_DYNSEL_ANT2_ANT3_L___POR 0x00000000 +#define PHYA_RXTD_RXB_DYNSEL_ANT2_ANT3_L__RBCTL_RBAPB_ANT3_CNT___POR 0x0000 +#define PHYA_RXTD_RXB_DYNSEL_ANT2_ANT3_L__RBCTL_RBAPB_ANT2_CNT___POR 0x0000 +#define PHYA_RXTD_RXB_DYNSEL_ANT2_ANT3_L__RBCTL_RBAPB_ANT3_CNT___M 0xFFFF0000 +#define PHYA_RXTD_RXB_DYNSEL_ANT2_ANT3_L__RBCTL_RBAPB_ANT3_CNT___S 16 +#define PHYA_RXTD_RXB_DYNSEL_ANT2_ANT3_L__RBCTL_RBAPB_ANT2_CNT___M 0x0000FFFF +#define PHYA_RXTD_RXB_DYNSEL_ANT2_ANT3_L__RBCTL_RBAPB_ANT2_CNT___S 0 +#define PHYA_RXTD_RXB_DYNSEL_ANT2_ANT3_L___M 0xFFFFFFFF +#define PHYA_RXTD_RXB_DYNSEL_ANT2_ANT3_L___S 0 + +#define PHYA_RXTD_RXB_DYNSEL_ALL_ANT_L (0x003A0398) +#define PHYA_RXTD_RXB_DYNSEL_ALL_ANT_L___RWC QCSR_REG_RO +#define PHYA_RXTD_RXB_DYNSEL_ALL_ANT_L___POR 0x00000000 +#define PHYA_RXTD_RXB_DYNSEL_ALL_ANT_L__RBCTL_RBAPB_ALLANT_CNT___POR 0x0000 +#define PHYA_RXTD_RXB_DYNSEL_ALL_ANT_L__RBCTL_RBAPB_ALLANT_CNT___M 0x0000FFFF +#define PHYA_RXTD_RXB_DYNSEL_ALL_ANT_L__RBCTL_RBAPB_ALLANT_CNT___S 0 +#define PHYA_RXTD_RXB_DYNSEL_ALL_ANT_L___M 0x0000FFFF +#define PHYA_RXTD_RXB_DYNSEL_ALL_ANT_L___S 0 + +#define PHYA_RXTD_FORCE_CLKEN_CCK_L (0x003A03A0) +#define PHYA_RXTD_FORCE_CLKEN_CCK_L___RWC QCSR_REG_RW +#define PHYA_RXTD_FORCE_CLKEN_CCK_L___POR 0x00000000 +#define PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_TXSM_CLKEN___POR 0x0 +#define PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_RX_ALWAYS___POR 0x0 +#define PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_RX_ENABLE3___POR 0x0 +#define PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_RX_ENABLE2___POR 0x0 +#define PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_RX_ENABLE1___POR 0x0 +#define PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_RX_ENABLE0___POR 0x0 +#define PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_TXSM_CLKEN___M 0x00000020 +#define PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_TXSM_CLKEN___S 5 +#define PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_RX_ALWAYS___M 0x00000010 +#define PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_RX_ALWAYS___S 4 +#define PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_RX_ENABLE3___M 0x00000008 +#define PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_RX_ENABLE3___S 3 +#define PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_RX_ENABLE2___M 0x00000004 +#define PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_RX_ENABLE2___S 2 +#define PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_RX_ENABLE1___M 0x00000002 +#define PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_RX_ENABLE1___S 1 +#define PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_RX_ENABLE0___M 0x00000001 +#define PHYA_RXTD_FORCE_CLKEN_CCK_L__FORCE_RX_ENABLE0___S 0 +#define PHYA_RXTD_FORCE_CLKEN_CCK_L___M 0x0000003F +#define PHYA_RXTD_FORCE_CLKEN_CCK_L___S 0 + +#define PHYA_RXTD_RXB_SPARE_01_L (0x003A03A8) +#define PHYA_RXTD_RXB_SPARE_01_L___RWC QCSR_REG_RW +#define PHYA_RXTD_RXB_SPARE_01_L___POR 0x00000000 +#define PHYA_RXTD_RXB_SPARE_01_L__RXB_ECO_CTRL___POR 0x0000000 +#define PHYA_RXTD_RXB_SPARE_01_L__RXB_ECO_CTRL___M 0x03FFFFFF +#define PHYA_RXTD_RXB_SPARE_01_L__RXB_ECO_CTRL___S 0 +#define PHYA_RXTD_RXB_SPARE_01_L___M 0x03FFFFFF +#define PHYA_RXTD_RXB_SPARE_01_L___S 0 + +#define PHYA_RXTD_PMI_OUTPUT_L (0x003A03B0) +#define PHYA_RXTD_PMI_OUTPUT_L___RWC QCSR_REG_RO +#define PHYA_RXTD_PMI_OUTPUT_L___POR 0x00000000 +#define PHYA_RXTD_PMI_OUTPUT_L__RXB_SM_RXB_BUSY___POR 0x0 +#define PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_SHORT_PREAMBLE___POR 0x0 +#define PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_RATE___POR 0x0 +#define PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_PKTSTART___POR 0x0 +#define PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_LENGTH___POR 0x00000 +#define PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_ERROR_CODE___POR 0x0 +#define PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_ABORT___POR 0x0 +#define PHYA_RXTD_PMI_OUTPUT_L__RXB_SM_RXB_BUSY___M 0x02000000 +#define PHYA_RXTD_PMI_OUTPUT_L__RXB_SM_RXB_BUSY___S 25 +#define PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_SHORT_PREAMBLE___M 0x01000000 +#define PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_SHORT_PREAMBLE___S 24 +#define PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_RATE___M 0x00C00000 +#define PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_RATE___S 22 +#define PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_PKTSTART___M 0x00200000 +#define PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_PKTSTART___S 21 +#define PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_LENGTH___M 0x001FFFF0 +#define PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_LENGTH___S 4 +#define PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_ERROR_CODE___M 0x0000000E +#define PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_ERROR_CODE___S 1 +#define PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_ABORT___M 0x00000001 +#define PHYA_RXTD_PMI_OUTPUT_L__RBHPC_PMI_ABORT___S 0 +#define PHYA_RXTD_PMI_OUTPUT_L___M 0x03FFFFFF +#define PHYA_RXTD_PMI_OUTPUT_L___S 0 + +#define PHYA_RXTD_RBCTL_AGC_INFO_L (0x003A03B8) +#define PHYA_RXTD_RBCTL_AGC_INFO_L___RWC QCSR_REG_RO +#define PHYA_RXTD_RBCTL_AGC_INFO_L___POR 0x00000000 +#define PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_NO_B_PKT_DET___POR 0x0 +#define PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_EOP_RXB___POR 0x0 +#define PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_END_OPPKT___POR 0x0 +#define PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_B_VLD_HDR_P___POR 0x0 +#define PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_B_PKT_DET___POR 0x0 +#define PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_B_INV_HDR___POR 0x0 +#define PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_NO_B_PKT_DET___M 0x00000020 +#define PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_NO_B_PKT_DET___S 5 +#define PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_EOP_RXB___M 0x00000010 +#define PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_EOP_RXB___S 4 +#define PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_END_OPPKT___M 0x00000008 +#define PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_END_OPPKT___S 3 +#define PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_B_VLD_HDR_P___M 0x00000004 +#define PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_B_VLD_HDR_P___S 2 +#define PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_B_PKT_DET___M 0x00000002 +#define PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_B_PKT_DET___S 1 +#define PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_B_INV_HDR___M 0x00000001 +#define PHYA_RXTD_RBCTL_AGC_INFO_L__RBCTL_AGC_B_INV_HDR___S 0 +#define PHYA_RXTD_RBCTL_AGC_INFO_L___M 0x0000003F +#define PHYA_RXTD_RBCTL_AGC_INFO_L___S 0 + +#define PHYA_RXTD_RXTD_PHYDBG_CTRL_L (0x003A03C0) +#define PHYA_RXTD_RXTD_PHYDBG_CTRL_L___RWC QCSR_REG_RW +#define PHYA_RXTD_RXTD_PHYDBG_CTRL_L___POR 0x00000000 +#define PHYA_RXTD_RXTD_PHYDBG_CTRL_L__RXTD_PHYDBG_SEL___POR 0x00 +#define PHYA_RXTD_RXTD_PHYDBG_CTRL_L__RXTD_PHYDBG_EN___POR 0x0 +#define PHYA_RXTD_RXTD_PHYDBG_CTRL_L__RXTD_PHYDBG_SEL___M 0x0000FF00 +#define PHYA_RXTD_RXTD_PHYDBG_CTRL_L__RXTD_PHYDBG_SEL___S 8 +#define PHYA_RXTD_RXTD_PHYDBG_CTRL_L__RXTD_PHYDBG_EN___M 0x00000001 +#define PHYA_RXTD_RXTD_PHYDBG_CTRL_L__RXTD_PHYDBG_EN___S 0 +#define PHYA_RXTD_RXTD_PHYDBG_CTRL_L___M 0x0000FF01 +#define PHYA_RXTD_RXTD_PHYDBG_CTRL_L___S 0 + +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CTRL_L (0x003A03C8) +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CTRL_L___RWC QCSR_REG_RW +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CTRL_L___POR 0x00000000 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CTRL_L__RXDCO_CAPTURE_TIMER___POR 0x000 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CTRL_L__RXDCO_CAPTURE_MODE___POR 0x0 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CTRL_L__RXDCO_CAPTURE_ENABLE___POR 0x0 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CTRL_L__RXDCO_CAPTURE_TIMER___M 0x03FF0000 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CTRL_L__RXDCO_CAPTURE_TIMER___S 16 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CTRL_L__RXDCO_CAPTURE_MODE___M 0x00000100 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CTRL_L__RXDCO_CAPTURE_MODE___S 8 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CTRL_L__RXDCO_CAPTURE_ENABLE___M 0x00000001 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CTRL_L__RXDCO_CAPTURE_ENABLE___S 0 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CTRL_L___M 0x03FF0101 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CTRL_L___S 0 + +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_L (0x003A03D0) +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_L___RWC QCSR_REG_RO +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_L___POR 0x00000000 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_L__DCO_ESTIMATE_Q_CHN0___POR 0x000 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_L__DCO_ESTIMATE_I_CHN0___POR 0x000 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_L__DCO_ESTIMATE_Q_CHN0___M 0x07FF0000 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_L__DCO_ESTIMATE_Q_CHN0___S 16 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_L__DCO_ESTIMATE_I_CHN0___M 0x000007FF +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_L__DCO_ESTIMATE_I_CHN0___S 0 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_L___M 0x07FF07FF +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_L___S 0 + +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_U (0x003A03D4) +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_U___RWC QCSR_REG_RO +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_U___POR 0x00000000 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_U__GAIN_TABLE_SEL_CHN0___POR 0x0 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_U__TOTAL_GAIN_CHN0___POR 0x000 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_U__GAIN_TABLE_SEL_CHN0___M 0x00030000 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_U__GAIN_TABLE_SEL_CHN0___S 16 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_U__TOTAL_GAIN_CHN0___M 0x000003FF +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_U__TOTAL_GAIN_CHN0___S 0 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_U___M 0x000303FF +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN0_U___S 0 + +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_L (0x003A03D8) +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_L___RWC QCSR_REG_RO +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_L___POR 0x00000000 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_L__DCO_ESTIMATE_Q_CHN1___POR 0x000 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_L__DCO_ESTIMATE_I_CHN1___POR 0x000 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_L__DCO_ESTIMATE_Q_CHN1___M 0x07FF0000 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_L__DCO_ESTIMATE_Q_CHN1___S 16 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_L__DCO_ESTIMATE_I_CHN1___M 0x000007FF +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_L__DCO_ESTIMATE_I_CHN1___S 0 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_L___M 0x07FF07FF +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_L___S 0 + +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_U (0x003A03DC) +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_U___RWC QCSR_REG_RO +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_U___POR 0x00000000 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_U__GAIN_TABLE_SEL_CHN1___POR 0x0 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_U__TOTAL_GAIN_CHN1___POR 0x000 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_U__GAIN_TABLE_SEL_CHN1___M 0x00030000 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_U__GAIN_TABLE_SEL_CHN1___S 16 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_U__TOTAL_GAIN_CHN1___M 0x000003FF +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_U__TOTAL_GAIN_CHN1___S 0 +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_U___M 0x000303FF +#define PHYA_RXTD_DBG_RXDCO_CAPTURE_CHN1_U___S 0 + +#define PHYA_RXTD_RXTD_MMSE_IS_CTRL_L (0x003A03E0) +#define PHYA_RXTD_RXTD_MMSE_IS_CTRL_L___RWC QCSR_REG_RW +#define PHYA_RXTD_RXTD_MMSE_IS_CTRL_L___POR 0x03020000 +#define PHYA_RXTD_RXTD_MMSE_IS_CTRL_L__MMSE_IS_MIN_SNR_LEVEL___POR 0x3 +#define PHYA_RXTD_RXTD_MMSE_IS_CTRL_L__MMSE_IS_MAX_SNR_LEVEL___POR 0x2 +#define PHYA_RXTD_RXTD_MMSE_IS_CTRL_L__MMSE_IS_SNR_CORR_FACTOR___POR 0x0 +#define PHYA_RXTD_RXTD_MMSE_IS_CTRL_L__MMSE_IS_FORCED_SNR___POR 0x00 +#define PHYA_RXTD_RXTD_MMSE_IS_CTRL_L__MMSE_IS_MIN_SNR_LEVEL___M 0x03000000 +#define PHYA_RXTD_RXTD_MMSE_IS_CTRL_L__MMSE_IS_MIN_SNR_LEVEL___S 24 +#define PHYA_RXTD_RXTD_MMSE_IS_CTRL_L__MMSE_IS_MAX_SNR_LEVEL___M 0x00070000 +#define PHYA_RXTD_RXTD_MMSE_IS_CTRL_L__MMSE_IS_MAX_SNR_LEVEL___S 16 +#define PHYA_RXTD_RXTD_MMSE_IS_CTRL_L__MMSE_IS_SNR_CORR_FACTOR___M 0x00000F00 +#define PHYA_RXTD_RXTD_MMSE_IS_CTRL_L__MMSE_IS_SNR_CORR_FACTOR___S 8 +#define PHYA_RXTD_RXTD_MMSE_IS_CTRL_L__MMSE_IS_FORCED_SNR___M 0x0000003F +#define PHYA_RXTD_RXTD_MMSE_IS_CTRL_L__MMSE_IS_FORCED_SNR___S 0 +#define PHYA_RXTD_RXTD_MMSE_IS_CTRL_L___M 0x03070F3F +#define PHYA_RXTD_RXTD_MMSE_IS_CTRL_L___S 0 + +#define PHYA_RXTD_RXTD_MMSE_IS_CTRL_U (0x003A03E4) +#define PHYA_RXTD_RXTD_MMSE_IS_CTRL_U___RWC QCSR_REG_RW +#define PHYA_RXTD_RXTD_MMSE_IS_CTRL_U___POR 0x00000000 +#define PHYA_RXTD_RXTD_MMSE_IS_CTRL_U__MMSE_CHAIN_MASK___POR 0x00 +#define PHYA_RXTD_RXTD_MMSE_IS_CTRL_U__MMSE_CHAIN_MASK___M 0x000000FF +#define PHYA_RXTD_RXTD_MMSE_IS_CTRL_U__MMSE_CHAIN_MASK___S 0 +#define PHYA_RXTD_RXTD_MMSE_IS_CTRL_U___M 0x000000FF +#define PHYA_RXTD_RXTD_MMSE_IS_CTRL_U___S 0 + +#define PHYA_RXTD_FFT_BUF_CONFIG_0_L (0x003A03E8) +#define PHYA_RXTD_FFT_BUF_CONFIG_0_L___RWC QCSR_REG_RW +#define PHYA_RXTD_FFT_BUF_CONFIG_0_L___POR 0x00030000 +#define PHYA_RXTD_FFT_BUF_CONFIG_0_L__N_AUTO_LAUNCH___POR 0x3 +#define PHYA_RXTD_FFT_BUF_CONFIG_0_L__CATCHUP_CTRL___POR 0x0 +#define PHYA_RXTD_FFT_BUF_CONFIG_0_L__START_TRIG___POR 0x0 +#define PHYA_RXTD_FFT_BUF_CONFIG_0_L__N_AUTO_LAUNCH___M 0x00030000 +#define PHYA_RXTD_FFT_BUF_CONFIG_0_L__N_AUTO_LAUNCH___S 16 +#define PHYA_RXTD_FFT_BUF_CONFIG_0_L__CATCHUP_CTRL___M 0x00000100 +#define PHYA_RXTD_FFT_BUF_CONFIG_0_L__CATCHUP_CTRL___S 8 +#define PHYA_RXTD_FFT_BUF_CONFIG_0_L__START_TRIG___M 0x00000007 +#define PHYA_RXTD_FFT_BUF_CONFIG_0_L__START_TRIG___S 0 +#define PHYA_RXTD_FFT_BUF_CONFIG_0_L___M 0x00030107 +#define PHYA_RXTD_FFT_BUF_CONFIG_0_L___S 0 + +#define PHYA_RXTD_FFT_BUF_CONFIG_0_U (0x003A03EC) +#define PHYA_RXTD_FFT_BUF_CONFIG_0_U___RWC QCSR_REG_RW +#define PHYA_RXTD_FFT_BUF_CONFIG_0_U___POR 0x00000000 +#define PHYA_RXTD_FFT_BUF_CONFIG_0_U__FFT_CTRL_SPARE___POR 0x00000000 +#define PHYA_RXTD_FFT_BUF_CONFIG_0_U__FFT_CTRL_SPARE___M 0xFFFFFFFF +#define PHYA_RXTD_FFT_BUF_CONFIG_0_U__FFT_CTRL_SPARE___S 0 +#define PHYA_RXTD_FFT_BUF_CONFIG_0_U___M 0xFFFFFFFF +#define PHYA_RXTD_FFT_BUF_CONFIG_0_U___S 0 + +#define PHYA_RXTD_FFT_BUF_CONFIG_1_L (0x003A03F0) +#define PHYA_RXTD_FFT_BUF_CONFIG_1_L___RWC QCSR_REG_RW +#define PHYA_RXTD_FFT_BUF_CONFIG_1_L___POR 0x00000001 +#define PHYA_RXTD_FFT_BUF_CONFIG_1_L__ALWAYS_USE_FFT_CFO_CORR___POR 0x1 +#define PHYA_RXTD_FFT_BUF_CONFIG_1_L__ALWAYS_USE_FFT_CFO_CORR___M 0x00000001 +#define PHYA_RXTD_FFT_BUF_CONFIG_1_L__ALWAYS_USE_FFT_CFO_CORR___S 0 +#define PHYA_RXTD_FFT_BUF_CONFIG_1_L___M 0x00000001 +#define PHYA_RXTD_FFT_BUF_CONFIG_1_L___S 0 + +#define PHYA_RXTD_OCL_CONFIG_0_L (0x003A03F8) +#define PHYA_RXTD_OCL_CONFIG_0_L___RWC QCSR_REG_RW +#define PHYA_RXTD_OCL_CONFIG_0_L___POR 0x00000000 +#define PHYA_RXTD_OCL_CONFIG_0_L__LEGACY_RSSI_EXTRA_SETTLING_TIME_100NS___POR 0x00 +#define PHYA_RXTD_OCL_CONFIG_0_L__GAIN_BACKOFF_SLEEP_CHAIN_DB___POR 0x00 +#define PHYA_RXTD_OCL_CONFIG_0_L__LISTEN_CHAIN___POR 0x0 +#define PHYA_RXTD_OCL_CONFIG_0_L__ENABLE_ONE_CHAIN_SEARCH___POR 0x0 +#define PHYA_RXTD_OCL_CONFIG_0_L__LEGACY_RSSI_EXTRA_SETTLING_TIME_100NS___M 0x00000F80 +#define PHYA_RXTD_OCL_CONFIG_0_L__LEGACY_RSSI_EXTRA_SETTLING_TIME_100NS___S 7 +#define PHYA_RXTD_OCL_CONFIG_0_L__GAIN_BACKOFF_SLEEP_CHAIN_DB___M 0x0000007C +#define PHYA_RXTD_OCL_CONFIG_0_L__GAIN_BACKOFF_SLEEP_CHAIN_DB___S 2 +#define PHYA_RXTD_OCL_CONFIG_0_L__LISTEN_CHAIN___M 0x00000002 +#define PHYA_RXTD_OCL_CONFIG_0_L__LISTEN_CHAIN___S 1 +#define PHYA_RXTD_OCL_CONFIG_0_L__ENABLE_ONE_CHAIN_SEARCH___M 0x00000001 +#define PHYA_RXTD_OCL_CONFIG_0_L__ENABLE_ONE_CHAIN_SEARCH___S 0 +#define PHYA_RXTD_OCL_CONFIG_0_L___M 0x00000FFF +#define PHYA_RXTD_OCL_CONFIG_0_L___S 0 + +#define PHYA_RXTD_OCL_CONFIG_1_L (0x003A0400) +#define PHYA_RXTD_OCL_CONFIG_1_L___RWC QCSR_REG_RW +#define PHYA_RXTD_OCL_CONFIG_1_L___POR 0x00000000 +#define PHYA_RXTD_OCL_CONFIG_1_L__RX_PHASE_JUMP___POR 0x00 +#define PHYA_RXTD_OCL_CONFIG_1_L__RX_PHASE_JUMP___M 0x0000007F +#define PHYA_RXTD_OCL_CONFIG_1_L__RX_PHASE_JUMP___S 0 +#define PHYA_RXTD_OCL_CONFIG_1_L___M 0x0000007F +#define PHYA_RXTD_OCL_CONFIG_1_L___S 0 + +#define PHYA_RXTD_OCL_CONFIG_2_L (0x003A0408) +#define PHYA_RXTD_OCL_CONFIG_2_L___RWC QCSR_REG_RW +#define PHYA_RXTD_OCL_CONFIG_2_L___POR 0x01452300 +#define PHYA_RXTD_OCL_CONFIG_2_L__DC_SUB_CFO_THR___POR 0x0145 +#define PHYA_RXTD_OCL_CONFIG_2_L__DC_SUB_RSSI_THR___POR 0x23 +#define PHYA_RXTD_OCL_CONFIG_2_L__DC_SUB_ENABLE___POR 0x0 +#define PHYA_RXTD_OCL_CONFIG_2_L__DC_SUB_CFO_THR___M 0x3FFF0000 +#define PHYA_RXTD_OCL_CONFIG_2_L__DC_SUB_CFO_THR___S 16 +#define PHYA_RXTD_OCL_CONFIG_2_L__DC_SUB_RSSI_THR___M 0x0000FF00 +#define PHYA_RXTD_OCL_CONFIG_2_L__DC_SUB_RSSI_THR___S 8 +#define PHYA_RXTD_OCL_CONFIG_2_L__DC_SUB_ENABLE___M 0x00000001 +#define PHYA_RXTD_OCL_CONFIG_2_L__DC_SUB_ENABLE___S 0 +#define PHYA_RXTD_OCL_CONFIG_2_L___M 0x3FFFFF01 +#define PHYA_RXTD_OCL_CONFIG_2_L___S 0 + +#define PHYA_RXTD_OCL_CONFIG_2_U (0x003A040C) +#define PHYA_RXTD_OCL_CONFIG_2_U___RWC QCSR_REG_RW +#define PHYA_RXTD_OCL_CONFIG_2_U___POR 0x00000001 +#define PHYA_RXTD_OCL_CONFIG_2_U__DC_SUB_LONG_MODE___POR 0x1 +#define PHYA_RXTD_OCL_CONFIG_2_U__DC_SUB_LONG_MODE___M 0x00000001 +#define PHYA_RXTD_OCL_CONFIG_2_U__DC_SUB_LONG_MODE___S 0 +#define PHYA_RXTD_OCL_CONFIG_2_U___M 0x00000001 +#define PHYA_RXTD_OCL_CONFIG_2_U___S 0 + +#define PHYA_RXTD_EVENT_CONFIG_L (0x003A0410) +#define PHYA_RXTD_EVENT_CONFIG_L___RWC QCSR_REG_RW +#define PHYA_RXTD_EVENT_CONFIG_L___POR 0x00010000 +#define PHYA_RXTD_EVENT_CONFIG_L__MASK_SIZING_EVENT_2ND_AGC___POR 0x1 +#define PHYA_RXTD_EVENT_CONFIG_L__MASK_11B_DET_FOR_PKT_EVT___POR 0x0 +#define PHYA_RXTD_EVENT_CONFIG_L__MASK_BTCF_FOR_PKT_EVT___POR 0x0 +#define PHYA_RXTD_EVENT_CONFIG_L__MASK_SIZING_EVENT_2ND_AGC___M 0x00010000 +#define PHYA_RXTD_EVENT_CONFIG_L__MASK_SIZING_EVENT_2ND_AGC___S 16 +#define PHYA_RXTD_EVENT_CONFIG_L__MASK_11B_DET_FOR_PKT_EVT___M 0x00000100 +#define PHYA_RXTD_EVENT_CONFIG_L__MASK_11B_DET_FOR_PKT_EVT___S 8 +#define PHYA_RXTD_EVENT_CONFIG_L__MASK_BTCF_FOR_PKT_EVT___M 0x00000001 +#define PHYA_RXTD_EVENT_CONFIG_L__MASK_BTCF_FOR_PKT_EVT___S 0 +#define PHYA_RXTD_EVENT_CONFIG_L___M 0x00010101 +#define PHYA_RXTD_EVENT_CONFIG_L___S 0 + +#define PHYA_RXTD_FFT_CTRL_DBG_L (0x003A0418) +#define PHYA_RXTD_FFT_CTRL_DBG_L___RWC QCSR_REG_RO +#define PHYA_RXTD_FFT_CTRL_DBG_L___POR 0x00000000 +#define PHYA_RXTD_FFT_CTRL_DBG_L__TS_SYMBOL_START_DIFF_CAPTURE___POR 0x0000 +#define PHYA_RXTD_FFT_CTRL_DBG_L__TS_SYMBOL_START_DIFF_CAPTURE___M 0x0000FFFF +#define PHYA_RXTD_FFT_CTRL_DBG_L__TS_SYMBOL_START_DIFF_CAPTURE___S 0 +#define PHYA_RXTD_FFT_CTRL_DBG_L___M 0x0000FFFF +#define PHYA_RXTD_FFT_CTRL_DBG_L___S 0 + +#define PHYA_RXTD_FFT_CTRL_L (0x003A0420) +#define PHYA_RXTD_FFT_CTRL_L___RWC QCSR_REG_RW +#define PHYA_RXTD_FFT_CTRL_L___POR 0x00000000 +#define PHYA_RXTD_FFT_CTRL_L__OFDM_FFT_SIZE___POR 0x0 +#define PHYA_RXTD_FFT_CTRL_L__OFDM_FIR_MUX_SEL___POR 0x0 +#define PHYA_RXTD_FFT_CTRL_L__OFDM_FFT_START___POR 0x0000 +#define PHYA_RXTD_FFT_CTRL_L__OFDM_FFT_SIZE___M 0x07000000 +#define PHYA_RXTD_FFT_CTRL_L__OFDM_FFT_SIZE___S 24 +#define PHYA_RXTD_FFT_CTRL_L__OFDM_FIR_MUX_SEL___M 0x00030000 +#define PHYA_RXTD_FFT_CTRL_L__OFDM_FIR_MUX_SEL___S 16 +#define PHYA_RXTD_FFT_CTRL_L__OFDM_FFT_START___M 0x0000FFFF +#define PHYA_RXTD_FFT_CTRL_L__OFDM_FFT_START___S 0 +#define PHYA_RXTD_FFT_CTRL_L___M 0x0703FFFF +#define PHYA_RXTD_FFT_CTRL_L___S 0 + +#define PHYA_RXTD_FFT_CTRL_U (0x003A0424) +#define PHYA_RXTD_FFT_CTRL_U___RWC QCSR_REG_RW +#define PHYA_RXTD_FFT_CTRL_U___POR 0x00000000 +#define PHYA_RXTD_FFT_CTRL_U__OFDM_FFT_SYM_ABORT___POR 0x0 +#define PHYA_RXTD_FFT_CTRL_U__OFDM_FFT_SYM_ABORT___M 0x00000001 +#define PHYA_RXTD_FFT_CTRL_U__OFDM_FFT_SYM_ABORT___S 0 +#define PHYA_RXTD_FFT_CTRL_U___M 0x00000001 +#define PHYA_RXTD_FFT_CTRL_U___S 0 + +#define PHYA_RXTD_FFT_CTRL_SCALE_L (0x003A0428) +#define PHYA_RXTD_FFT_CTRL_SCALE_L___RWC QCSR_REG_RW +#define PHYA_RXTD_FFT_CTRL_SCALE_L___POR 0x00000000 +#define PHYA_RXTD_FFT_CTRL_SCALE_L__OFDM_FFT_SCALING_CTL___POR 0x000000 +#define PHYA_RXTD_FFT_CTRL_SCALE_L__OFDM_FFT_SCALING_CTL___M 0x00FFFFFF +#define PHYA_RXTD_FFT_CTRL_SCALE_L__OFDM_FFT_SCALING_CTL___S 0 +#define PHYA_RXTD_FFT_CTRL_SCALE_L___M 0x00FFFFFF +#define PHYA_RXTD_FFT_CTRL_SCALE_L___S 0 + +#define PHYA_RXTD_FFT_CTRL_CFO_0_L (0x003A0430) +#define PHYA_RXTD_FFT_CTRL_CFO_0_L___RWC QCSR_REG_RW +#define PHYA_RXTD_FFT_CTRL_CFO_0_L___POR 0x00000000 +#define PHYA_RXTD_FFT_CTRL_CFO_0_L__FFT_IN_CFO_SLOPE_VALUE_PRI___POR 0x000000 +#define PHYA_RXTD_FFT_CTRL_CFO_0_L__FFT_IN_CFO_SLOPE_VALUE_PRI___M 0x001FFFFF +#define PHYA_RXTD_FFT_CTRL_CFO_0_L__FFT_IN_CFO_SLOPE_VALUE_PRI___S 0 +#define PHYA_RXTD_FFT_CTRL_CFO_0_L___M 0x001FFFFF +#define PHYA_RXTD_FFT_CTRL_CFO_0_L___S 0 + +#define PHYA_RXTD_FFT_CTRL_CFO_0_U (0x003A0434) +#define PHYA_RXTD_FFT_CTRL_CFO_0_U___RWC QCSR_REG_RW +#define PHYA_RXTD_FFT_CTRL_CFO_0_U___POR 0x00000000 +#define PHYA_RXTD_FFT_CTRL_CFO_0_U__FFT_IN_CFO_SLOPE_VALUE_SEC___POR 0x000000 +#define PHYA_RXTD_FFT_CTRL_CFO_0_U__FFT_IN_CFO_SLOPE_VALUE_SEC___M 0x001FFFFF +#define PHYA_RXTD_FFT_CTRL_CFO_0_U__FFT_IN_CFO_SLOPE_VALUE_SEC___S 0 +#define PHYA_RXTD_FFT_CTRL_CFO_0_U___M 0x001FFFFF +#define PHYA_RXTD_FFT_CTRL_CFO_0_U___S 0 + +#define PHYA_RXTD_FFT_CTRL_CFO_1_L (0x003A0438) +#define PHYA_RXTD_FFT_CTRL_CFO_1_L___RWC QCSR_REG_RW +#define PHYA_RXTD_FFT_CTRL_CFO_1_L___POR 0x00000000 +#define PHYA_RXTD_FFT_CTRL_CFO_1_L__FFT_IN_CFO_INIT_VALUE_PRI___POR 0x000000 +#define PHYA_RXTD_FFT_CTRL_CFO_1_L__FFT_IN_CFO_INIT_VALUE_PRI___M 0x001FFFFF +#define PHYA_RXTD_FFT_CTRL_CFO_1_L__FFT_IN_CFO_INIT_VALUE_PRI___S 0 +#define PHYA_RXTD_FFT_CTRL_CFO_1_L___M 0x001FFFFF +#define PHYA_RXTD_FFT_CTRL_CFO_1_L___S 0 + +#define PHYA_RXTD_FFT_CTRL_CFO_1_U (0x003A043C) +#define PHYA_RXTD_FFT_CTRL_CFO_1_U___RWC QCSR_REG_RW +#define PHYA_RXTD_FFT_CTRL_CFO_1_U___POR 0x00000000 +#define PHYA_RXTD_FFT_CTRL_CFO_1_U__FFT_IN_CFO_INIT_VALUE_SEC___POR 0x000000 +#define PHYA_RXTD_FFT_CTRL_CFO_1_U__FFT_IN_CFO_INIT_VALUE_SEC___M 0x001FFFFF +#define PHYA_RXTD_FFT_CTRL_CFO_1_U__FFT_IN_CFO_INIT_VALUE_SEC___S 0 +#define PHYA_RXTD_FFT_CTRL_CFO_1_U___M 0x001FFFFF +#define PHYA_RXTD_FFT_CTRL_CFO_1_U___S 0 + +#define PHYA_RXTD_TD_CFO_CTRL_0_L (0x003A0440) +#define PHYA_RXTD_TD_CFO_CTRL_0_L___RWC QCSR_REG_RW +#define PHYA_RXTD_TD_CFO_CTRL_0_L___POR 0x00000000 +#define PHYA_RXTD_TD_CFO_CTRL_0_L__TD_CFO_SLOPE_VALUE_PRI___POR 0x000000 +#define PHYA_RXTD_TD_CFO_CTRL_0_L__TD_CFO_SLOPE_VALUE_PRI___M 0x001FFFFF +#define PHYA_RXTD_TD_CFO_CTRL_0_L__TD_CFO_SLOPE_VALUE_PRI___S 0 +#define PHYA_RXTD_TD_CFO_CTRL_0_L___M 0x001FFFFF +#define PHYA_RXTD_TD_CFO_CTRL_0_L___S 0 + +#define PHYA_RXTD_TD_CFO_CTRL_0_U (0x003A0444) +#define PHYA_RXTD_TD_CFO_CTRL_0_U___RWC QCSR_REG_RW +#define PHYA_RXTD_TD_CFO_CTRL_0_U___POR 0x00000000 +#define PHYA_RXTD_TD_CFO_CTRL_0_U__TD_CFO_SLOPE_VALUE_SEC___POR 0x000000 +#define PHYA_RXTD_TD_CFO_CTRL_0_U__TD_CFO_SLOPE_VALUE_SEC___M 0x001FFFFF +#define PHYA_RXTD_TD_CFO_CTRL_0_U__TD_CFO_SLOPE_VALUE_SEC___S 0 +#define PHYA_RXTD_TD_CFO_CTRL_0_U___M 0x001FFFFF +#define PHYA_RXTD_TD_CFO_CTRL_0_U___S 0 + +#define PHYA_RXTD_TD_CFO_CTRL_1_L (0x003A0448) +#define PHYA_RXTD_TD_CFO_CTRL_1_L___RWC QCSR_REG_RW +#define PHYA_RXTD_TD_CFO_CTRL_1_L___POR 0x00000000 +#define PHYA_RXTD_TD_CFO_CTRL_1_L__TD_CFO_INIT_VALUE_PRI___POR 0x000000 +#define PHYA_RXTD_TD_CFO_CTRL_1_L__TD_CFO_INIT_VALUE_PRI___M 0x001FFFFF +#define PHYA_RXTD_TD_CFO_CTRL_1_L__TD_CFO_INIT_VALUE_PRI___S 0 +#define PHYA_RXTD_TD_CFO_CTRL_1_L___M 0x001FFFFF +#define PHYA_RXTD_TD_CFO_CTRL_1_L___S 0 + +#define PHYA_RXTD_TD_CFO_CTRL_1_U (0x003A044C) +#define PHYA_RXTD_TD_CFO_CTRL_1_U___RWC QCSR_REG_RW +#define PHYA_RXTD_TD_CFO_CTRL_1_U___POR 0x00000000 +#define PHYA_RXTD_TD_CFO_CTRL_1_U__TD_CFO_INIT_VALUE_SEC___POR 0x000000 +#define PHYA_RXTD_TD_CFO_CTRL_1_U__TD_CFO_INIT_VALUE_SEC___M 0x001FFFFF +#define PHYA_RXTD_TD_CFO_CTRL_1_U__TD_CFO_INIT_VALUE_SEC___S 0 +#define PHYA_RXTD_TD_CFO_CTRL_1_U___M 0x001FFFFF +#define PHYA_RXTD_TD_CFO_CTRL_1_U___S 0 + +#define PHYA_RXTD_TD_CFO_CTRL_2_L (0x003A0450) +#define PHYA_RXTD_TD_CFO_CTRL_2_L___RWC QCSR_REG_RW +#define PHYA_RXTD_TD_CFO_CTRL_2_L___POR 0x00000000 +#define PHYA_RXTD_TD_CFO_CTRL_2_L__TD_CFO_NUM_SAMPLES___POR 0x0 +#define PHYA_RXTD_TD_CFO_CTRL_2_L__TD_CFO_CMD_MODE___POR 0x0 +#define PHYA_RXTD_TD_CFO_CTRL_2_L__TD_CFO_UPDATE_TS___POR 0x0000 +#define PHYA_RXTD_TD_CFO_CTRL_2_L__TD_CFO_NUM_SAMPLES___M 0x03000000 +#define PHYA_RXTD_TD_CFO_CTRL_2_L__TD_CFO_NUM_SAMPLES___S 24 +#define PHYA_RXTD_TD_CFO_CTRL_2_L__TD_CFO_CMD_MODE___M 0x00070000 +#define PHYA_RXTD_TD_CFO_CTRL_2_L__TD_CFO_CMD_MODE___S 16 +#define PHYA_RXTD_TD_CFO_CTRL_2_L__TD_CFO_UPDATE_TS___M 0x0000FFFF +#define PHYA_RXTD_TD_CFO_CTRL_2_L__TD_CFO_UPDATE_TS___S 0 +#define PHYA_RXTD_TD_CFO_CTRL_2_L___M 0x0307FFFF +#define PHYA_RXTD_TD_CFO_CTRL_2_L___S 0 + +#define PHYA_RXTD_TD_MIXERFIR_CTRL_L (0x003A0458) +#define PHYA_RXTD_TD_MIXERFIR_CTRL_L___RWC QCSR_REG_RW +#define PHYA_RXTD_TD_MIXERFIR_CTRL_L___POR 0x00000000 +#define PHYA_RXTD_TD_MIXERFIR_CTRL_L__MIXER_PHASE_UPDATE_TS___POR 0x0000 +#define PHYA_RXTD_TD_MIXERFIR_CTRL_L__MIXER_STAGE1_NUM_SAMPLES___POR 0x0 +#define PHYA_RXTD_TD_MIXERFIR_CTRL_L__MIXER_PHASE_UPDATE_TS___M 0xFFFF0000 +#define PHYA_RXTD_TD_MIXERFIR_CTRL_L__MIXER_PHASE_UPDATE_TS___S 16 +#define PHYA_RXTD_TD_MIXERFIR_CTRL_L__MIXER_STAGE1_NUM_SAMPLES___M 0x00000003 +#define PHYA_RXTD_TD_MIXERFIR_CTRL_L__MIXER_STAGE1_NUM_SAMPLES___S 0 +#define PHYA_RXTD_TD_MIXERFIR_CTRL_L___M 0xFFFF0003 +#define PHYA_RXTD_TD_MIXERFIR_CTRL_L___S 0 + +#define PHYA_RXTD_RXTD_CONTROL_DYN_L (0x003A0460) +#define PHYA_RXTD_RXTD_CONTROL_DYN_L___RWC QCSR_REG_WO +#define PHYA_RXTD_RXTD_CONTROL_DYN_L___POR 0x00000000 +#define PHYA_RXTD_RXTD_CONTROL_DYN_L__IS_11A_PKT___POR 0x0 +#define PHYA_RXTD_RXTD_CONTROL_DYN_L__RX_FRAME_ASSERT___POR 0x0 +#define PHYA_RXTD_RXTD_CONTROL_DYN_L__IS_11A_PKT___M 0x00000100 +#define PHYA_RXTD_RXTD_CONTROL_DYN_L__IS_11A_PKT___S 8 +#define PHYA_RXTD_RXTD_CONTROL_DYN_L__RX_FRAME_ASSERT___M 0x00000001 +#define PHYA_RXTD_RXTD_CONTROL_DYN_L__RX_FRAME_ASSERT___S 0 +#define PHYA_RXTD_RXTD_CONTROL_DYN_L___M 0x00000101 +#define PHYA_RXTD_RXTD_CONTROL_DYN_L___S 0 + +#define PHYA_RXTD_VSRC_DYN_CONFIG_L (0x003A0468) +#define PHYA_RXTD_VSRC_DYN_CONFIG_L___RWC QCSR_REG_RW +#define PHYA_RXTD_VSRC_DYN_CONFIG_L___POR 0x00000000 +#define PHYA_RXTD_VSRC_DYN_CONFIG_L__GI_START_TS___POR 0x0000 +#define PHYA_RXTD_VSRC_DYN_CONFIG_L__VSRC_FIFO_UPDATE_DELTA___POR 0x00 +#define PHYA_RXTD_VSRC_DYN_CONFIG_L__GI_START_TS___M 0xFFFF0000 +#define PHYA_RXTD_VSRC_DYN_CONFIG_L__GI_START_TS___S 16 +#define PHYA_RXTD_VSRC_DYN_CONFIG_L__VSRC_FIFO_UPDATE_DELTA___M 0x0000001F +#define PHYA_RXTD_VSRC_DYN_CONFIG_L__VSRC_FIFO_UPDATE_DELTA___S 0 +#define PHYA_RXTD_VSRC_DYN_CONFIG_L___M 0xFFFF001F +#define PHYA_RXTD_VSRC_DYN_CONFIG_L___S 0 + +#define PHYA_RXTD_VSRC_PPM_L (0x003A0470) +#define PHYA_RXTD_VSRC_PPM_L___RWC QCSR_REG_RW +#define PHYA_RXTD_VSRC_PPM_L___POR 0x00000000 +#define PHYA_RXTD_VSRC_PPM_L__VSRC_PPM___POR 0x00000 +#define PHYA_RXTD_VSRC_PPM_L__VSRC_PPM___M 0x0003FFFF +#define PHYA_RXTD_VSRC_PPM_L__VSRC_PPM___S 0 +#define PHYA_RXTD_VSRC_PPM_L___M 0x0003FFFF +#define PHYA_RXTD_VSRC_PPM_L___S 0 + +#define PHYA_RXTD_MMSE_DYN_CONFIG_L (0x003A0478) +#define PHYA_RXTD_MMSE_DYN_CONFIG_L___RWC QCSR_REG_RW +#define PHYA_RXTD_MMSE_DYN_CONFIG_L___POR 0x00000000 +#define PHYA_RXTD_MMSE_DYN_CONFIG_L__MMSE_PWR_EXP_SHIFT___POR 0x0 +#define PHYA_RXTD_MMSE_DYN_CONFIG_L__MMSE_PWR_EXP_SHIFT___M 0x0000000F +#define PHYA_RXTD_MMSE_DYN_CONFIG_L__MMSE_PWR_EXP_SHIFT___S 0 +#define PHYA_RXTD_MMSE_DYN_CONFIG_L___M 0x0000000F +#define PHYA_RXTD_MMSE_DYN_CONFIG_L___S 0 + +#define PHYA_RXTD_RESTART_DISABLE_CTRL_L (0x003A0480) +#define PHYA_RXTD_RESTART_DISABLE_CTRL_L___RWC QCSR_REG_RW +#define PHYA_RXTD_RESTART_DISABLE_CTRL_L___POR 0x00000000 +#define PHYA_RXTD_RESTART_DISABLE_CTRL_L__TSCMD_RESTART_DISABLE_IN_ACQUIRE___POR 0x0 +#define PHYA_RXTD_RESTART_DISABLE_CTRL_L__TS_RESTART_DISABLE_IN_ACQUIRE___POR 0x0000 +#define PHYA_RXTD_RESTART_DISABLE_CTRL_L__TSCMD_RESTART_DISABLE_IN_ACQUIRE___M 0x00010000 +#define PHYA_RXTD_RESTART_DISABLE_CTRL_L__TSCMD_RESTART_DISABLE_IN_ACQUIRE___S 16 +#define PHYA_RXTD_RESTART_DISABLE_CTRL_L__TS_RESTART_DISABLE_IN_ACQUIRE___M 0x0000FFFF +#define PHYA_RXTD_RESTART_DISABLE_CTRL_L__TS_RESTART_DISABLE_IN_ACQUIRE___S 0 +#define PHYA_RXTD_RESTART_DISABLE_CTRL_L___M 0x0001FFFF +#define PHYA_RXTD_RESTART_DISABLE_CTRL_L___S 0 + +#define PHYA_RXTD_RXTD_CONTROL_CMD_L (0x003A0488) +#define PHYA_RXTD_RXTD_CONTROL_CMD_L___RWC QCSR_REG_RW +#define PHYA_RXTD_RXTD_CONTROL_CMD_L___POR 0x00000000 +#define PHYA_RXTD_RXTD_CONTROL_CMD_L__VSRC_UPDATE___POR 0x0 +#define PHYA_RXTD_RXTD_CONTROL_CMD_L__MIXER_PHASE_UPDATE_CMD___POR 0x0 +#define PHYA_RXTD_RXTD_CONTROL_CMD_L__TD_CFO_UPDATE_CMD___POR 0x0 +#define PHYA_RXTD_RXTD_CONTROL_CMD_L__VSRC_UPDATE___M 0x00010000 +#define PHYA_RXTD_RXTD_CONTROL_CMD_L__VSRC_UPDATE___S 16 +#define PHYA_RXTD_RXTD_CONTROL_CMD_L__MIXER_PHASE_UPDATE_CMD___M 0x00000100 +#define PHYA_RXTD_RXTD_CONTROL_CMD_L__MIXER_PHASE_UPDATE_CMD___S 8 +#define PHYA_RXTD_RXTD_CONTROL_CMD_L__TD_CFO_UPDATE_CMD___M 0x00000001 +#define PHYA_RXTD_RXTD_CONTROL_CMD_L__TD_CFO_UPDATE_CMD___S 0 +#define PHYA_RXTD_RXTD_CONTROL_CMD_L___M 0x00010101 +#define PHYA_RXTD_RXTD_CONTROL_CMD_L___S 0 + +#define PHYA_RXTD_DYN_CONTROL_PKT_L (0x003A0490) +#define PHYA_RXTD_DYN_CONTROL_PKT_L___RWC QCSR_REG_RW +#define PHYA_RXTD_DYN_CONTROL_PKT_L___POR 0x00000000 +#define PHYA_RXTD_DYN_CONTROL_PKT_L__IS_BW80___POR 0x0 +#define PHYA_RXTD_DYN_CONTROL_PKT_L__DO_2ND_AGC___POR 0x0 +#define PHYA_RXTD_DYN_CONTROL_PKT_L__SEARCH_START_DELAY___POR 0x000 +#define PHYA_RXTD_DYN_CONTROL_PKT_L__IS_BW80___M 0x01000000 +#define PHYA_RXTD_DYN_CONTROL_PKT_L__IS_BW80___S 24 +#define PHYA_RXTD_DYN_CONTROL_PKT_L__DO_2ND_AGC___M 0x00010000 +#define PHYA_RXTD_DYN_CONTROL_PKT_L__DO_2ND_AGC___S 16 +#define PHYA_RXTD_DYN_CONTROL_PKT_L__SEARCH_START_DELAY___M 0x00000FFF +#define PHYA_RXTD_DYN_CONTROL_PKT_L__SEARCH_START_DELAY___S 0 +#define PHYA_RXTD_DYN_CONTROL_PKT_L___M 0x01010FFF +#define PHYA_RXTD_DYN_CONTROL_PKT_L___S 0 + +#define PHYA_RXTD_DYN_CONTROL_PKT_U (0x003A0494) +#define PHYA_RXTD_DYN_CONTROL_PKT_U___RWC QCSR_REG_RW +#define PHYA_RXTD_DYN_CONTROL_PKT_U___POR 0x00000000 +#define PHYA_RXTD_DYN_CONTROL_PKT_U__HE_STF_8US___POR 0x0 +#define PHYA_RXTD_DYN_CONTROL_PKT_U__DIS_RADAR_DURING_IFS___POR 0x0 +#define PHYA_RXTD_DYN_CONTROL_PKT_U__IS_BW160___POR 0x0 +#define PHYA_RXTD_DYN_CONTROL_PKT_U__HE_STF_8US___M 0x00010000 +#define PHYA_RXTD_DYN_CONTROL_PKT_U__HE_STF_8US___S 16 +#define PHYA_RXTD_DYN_CONTROL_PKT_U__DIS_RADAR_DURING_IFS___M 0x00000100 +#define PHYA_RXTD_DYN_CONTROL_PKT_U__DIS_RADAR_DURING_IFS___S 8 +#define PHYA_RXTD_DYN_CONTROL_PKT_U__IS_BW160___M 0x00000001 +#define PHYA_RXTD_DYN_CONTROL_PKT_U__IS_BW160___S 0 +#define PHYA_RXTD_DYN_CONTROL_PKT_U___M 0x00010101 +#define PHYA_RXTD_DYN_CONTROL_PKT_U___S 0 + +#define PHYA_RXTD_DYN_E2E_HW_STATUS_L (0x003A0498) +#define PHYA_RXTD_DYN_E2E_HW_STATUS_L___RWC QCSR_REG_RW +#define PHYA_RXTD_DYN_E2E_HW_STATUS_L___POR 0x00000000 +#define PHYA_RXTD_DYN_E2E_HW_STATUS_L__RADAR_PULSE_DETECT___POR 0x0 +#define PHYA_RXTD_DYN_E2E_HW_STATUS_L__FRAME_END___POR 0x0 +#define PHYA_RXTD_DYN_E2E_HW_STATUS_L__RESTART___POR 0x0 +#define PHYA_RXTD_DYN_E2E_HW_STATUS_L__FRAME_DETECT___POR 0x0 +#define PHYA_RXTD_DYN_E2E_HW_STATUS_L__RADAR_PULSE_DETECT___M 0x01000000 +#define PHYA_RXTD_DYN_E2E_HW_STATUS_L__RADAR_PULSE_DETECT___S 24 +#define PHYA_RXTD_DYN_E2E_HW_STATUS_L__FRAME_END___M 0x00010000 +#define PHYA_RXTD_DYN_E2E_HW_STATUS_L__FRAME_END___S 16 +#define PHYA_RXTD_DYN_E2E_HW_STATUS_L__RESTART___M 0x00000100 +#define PHYA_RXTD_DYN_E2E_HW_STATUS_L__RESTART___S 8 +#define PHYA_RXTD_DYN_E2E_HW_STATUS_L__FRAME_DETECT___M 0x00000001 +#define PHYA_RXTD_DYN_E2E_HW_STATUS_L__FRAME_DETECT___S 0 +#define PHYA_RXTD_DYN_E2E_HW_STATUS_L___M 0x01010101 +#define PHYA_RXTD_DYN_E2E_HW_STATUS_L___S 0 + +#define PHYA_RXTD_DYN_E2E_HW_STATUS_U (0x003A049C) +#define PHYA_RXTD_DYN_E2E_HW_STATUS_U___RWC QCSR_REG_RO +#define PHYA_RXTD_DYN_E2E_HW_STATUS_U___POR 0x00000000 +#define PHYA_RXTD_DYN_E2E_HW_STATUS_U__RADAR_ALLOW_RESTART___POR 0x0 +#define PHYA_RXTD_DYN_E2E_HW_STATUS_U__RADAR_ALLOW_RESTART___M 0x00000001 +#define PHYA_RXTD_DYN_E2E_HW_STATUS_U__RADAR_ALLOW_RESTART___S 0 +#define PHYA_RXTD_DYN_E2E_HW_STATUS_U___M 0x00000001 +#define PHYA_RXTD_DYN_E2E_HW_STATUS_U___S 0 + +#define PHYA_RXTD_FSM_STATE_L (0x003A04A0) +#define PHYA_RXTD_FSM_STATE_L___RWC QCSR_REG_RO +#define PHYA_RXTD_FSM_STATE_L___POR 0x00000000 +#define PHYA_RXTD_FSM_STATE_L__PHYDBG_FSM_STATE___POR 0x00000000 +#define PHYA_RXTD_FSM_STATE_L__PHYDBG_FSM_STATE___M 0xFFFFFFFF +#define PHYA_RXTD_FSM_STATE_L__PHYDBG_FSM_STATE___S 0 +#define PHYA_RXTD_FSM_STATE_L___M 0xFFFFFFFF +#define PHYA_RXTD_FSM_STATE_L___S 0 + +#define PHYA_RXTD_FSM_STATE_U (0x003A04A4) +#define PHYA_RXTD_FSM_STATE_U___RWC QCSR_REG_RO +#define PHYA_RXTD_FSM_STATE_U___POR 0x00000000 +#define PHYA_RXTD_FSM_STATE_U__PHY_MAC_CCA_WORD0___POR 0x00000000 +#define PHYA_RXTD_FSM_STATE_U__PHY_MAC_CCA_WORD0___M 0xFFFFFFFF +#define PHYA_RXTD_FSM_STATE_U__PHY_MAC_CCA_WORD0___S 0 +#define PHYA_RXTD_FSM_STATE_U___M 0xFFFFFFFF +#define PHYA_RXTD_FSM_STATE_U___S 0 + +#define PHYA_RXTD_DYN_HW_STATUS_0_L (0x003A04A8) +#define PHYA_RXTD_DYN_HW_STATUS_0_L___RWC QCSR_REG_RO +#define PHYA_RXTD_DYN_HW_STATUS_0_L___POR 0x00000000 +#define PHYA_RXTD_DYN_HW_STATUS_0_L__BTCF_TIMING_EST_RESULT___POR 0x0000 +#define PHYA_RXTD_DYN_HW_STATUS_0_L__SYM_COUNT___POR 0x000 +#define PHYA_RXTD_DYN_HW_STATUS_0_L__BTCF_TIMING_EST_RESULT___M 0xFFFF0000 +#define PHYA_RXTD_DYN_HW_STATUS_0_L__BTCF_TIMING_EST_RESULT___S 16 +#define PHYA_RXTD_DYN_HW_STATUS_0_L__SYM_COUNT___M 0x000003FF +#define PHYA_RXTD_DYN_HW_STATUS_0_L__SYM_COUNT___S 0 +#define PHYA_RXTD_DYN_HW_STATUS_0_L___M 0xFFFF03FF +#define PHYA_RXTD_DYN_HW_STATUS_0_L___S 0 + +#define PHYA_RXTD_DYN_HW_STATUS_0_U (0x003A04AC) +#define PHYA_RXTD_DYN_HW_STATUS_0_U___RWC QCSR_REG_RO +#define PHYA_RXTD_DYN_HW_STATUS_0_U___POR 0x00000000 +#define PHYA_RXTD_DYN_HW_STATUS_0_U__COARSE_CFO_EST_RESULT___POR 0x0000 +#define PHYA_RXTD_DYN_HW_STATUS_0_U__BTCF_FINE_CFO_EST_RESULT___POR 0x0000 +#define PHYA_RXTD_DYN_HW_STATUS_0_U__COARSE_CFO_EST_RESULT___M 0xFFFF0000 +#define PHYA_RXTD_DYN_HW_STATUS_0_U__COARSE_CFO_EST_RESULT___S 16 +#define PHYA_RXTD_DYN_HW_STATUS_0_U__BTCF_FINE_CFO_EST_RESULT___M 0x0000FFFF +#define PHYA_RXTD_DYN_HW_STATUS_0_U__BTCF_FINE_CFO_EST_RESULT___S 0 +#define PHYA_RXTD_DYN_HW_STATUS_0_U___M 0xFFFFFFFF +#define PHYA_RXTD_DYN_HW_STATUS_0_U___S 0 + +#define PHYA_RXTD_DYN_HW_STATUS_1_L (0x003A04B0) +#define PHYA_RXTD_DYN_HW_STATUS_1_L___RWC QCSR_REG_RO +#define PHYA_RXTD_DYN_HW_STATUS_1_L___POR 0x00000000 +#define PHYA_RXTD_DYN_HW_STATUS_1_L__NOISE_PWR_SQRT_EXP___POR 0x0 +#define PHYA_RXTD_DYN_HW_STATUS_1_L__NOISE_PWR_SQRT_MAN___POR 0x00 +#define PHYA_RXTD_DYN_HW_STATUS_1_L__SNR_EST_MMSE_IS___POR 0x00 +#define PHYA_RXTD_DYN_HW_STATUS_1_L__VSRC_DEPTH___POR 0x00 +#define PHYA_RXTD_DYN_HW_STATUS_1_L__NOISE_PWR_SQRT_EXP___M 0x0F000000 +#define PHYA_RXTD_DYN_HW_STATUS_1_L__NOISE_PWR_SQRT_EXP___S 24 +#define PHYA_RXTD_DYN_HW_STATUS_1_L__NOISE_PWR_SQRT_MAN___M 0x003F0000 +#define PHYA_RXTD_DYN_HW_STATUS_1_L__NOISE_PWR_SQRT_MAN___S 16 +#define PHYA_RXTD_DYN_HW_STATUS_1_L__SNR_EST_MMSE_IS___M 0x00003F00 +#define PHYA_RXTD_DYN_HW_STATUS_1_L__SNR_EST_MMSE_IS___S 8 +#define PHYA_RXTD_DYN_HW_STATUS_1_L__VSRC_DEPTH___M 0x000000FF +#define PHYA_RXTD_DYN_HW_STATUS_1_L__VSRC_DEPTH___S 0 +#define PHYA_RXTD_DYN_HW_STATUS_1_L___M 0x0F3F3FFF +#define PHYA_RXTD_DYN_HW_STATUS_1_L___S 0 + +#define PHYA_RXTD_DYN_HW_STATUS_1_U (0x003A04B4) +#define PHYA_RXTD_DYN_HW_STATUS_1_U___RWC QCSR_REG_RO +#define PHYA_RXTD_DYN_HW_STATUS_1_U___POR 0x00000000 +#define PHYA_RXTD_DYN_HW_STATUS_1_U__NOISE_PWR_SQRT_EXP_SEC80___POR 0x0 +#define PHYA_RXTD_DYN_HW_STATUS_1_U__NOISE_PWR_SQRT_MAN_SEC80___POR 0x00 +#define PHYA_RXTD_DYN_HW_STATUS_1_U__SNR_EST_MMSE_IS_SEC80___POR 0x00 +#define PHYA_RXTD_DYN_HW_STATUS_1_U__NOISE_PWR_SQRT_EXP_SEC80___M 0x000F0000 +#define PHYA_RXTD_DYN_HW_STATUS_1_U__NOISE_PWR_SQRT_EXP_SEC80___S 16 +#define PHYA_RXTD_DYN_HW_STATUS_1_U__NOISE_PWR_SQRT_MAN_SEC80___M 0x00003F00 +#define PHYA_RXTD_DYN_HW_STATUS_1_U__NOISE_PWR_SQRT_MAN_SEC80___S 8 +#define PHYA_RXTD_DYN_HW_STATUS_1_U__SNR_EST_MMSE_IS_SEC80___M 0x0000003F +#define PHYA_RXTD_DYN_HW_STATUS_1_U__SNR_EST_MMSE_IS_SEC80___S 0 +#define PHYA_RXTD_DYN_HW_STATUS_1_U___M 0x000F3F3F +#define PHYA_RXTD_DYN_HW_STATUS_1_U___S 0 + +#define PHYA_RXTD_RSSI_COMB_0_L (0x003A04B8) +#define PHYA_RXTD_RSSI_COMB_0_L___RWC QCSR_REG_RO +#define PHYA_RXTD_RSSI_COMB_0_L___POR 0x00000000 +#define PHYA_RXTD_RSSI_COMB_0_L__AGC_DUP_BW___POR 0x0 +#define PHYA_RXTD_RSSI_COMB_0_L__AGC_DUP_BW___M 0x00000003 +#define PHYA_RXTD_RSSI_COMB_0_L__AGC_DUP_BW___S 0 +#define PHYA_RXTD_RSSI_COMB_0_L___M 0x00000003 +#define PHYA_RXTD_RSSI_COMB_0_L___S 0 + +#define PHYA_RXTD_RSSI_COMB_1_L (0x003A04C0) +#define PHYA_RXTD_RSSI_COMB_1_L___RWC QCSR_REG_RO +#define PHYA_RXTD_RSSI_COMB_1_L___POR 0x00000080 +#define PHYA_RXTD_RSSI_COMB_1_L__RSSI_COMB___POR 0x80 +#define PHYA_RXTD_RSSI_COMB_1_L__RSSI_COMB___M 0x000000FF +#define PHYA_RXTD_RSSI_COMB_1_L__RSSI_COMB___S 0 +#define PHYA_RXTD_RSSI_COMB_1_L___M 0x000000FF +#define PHYA_RXTD_RSSI_COMB_1_L___S 0 + +#define PHYA_RXTD_RSSI_COMB_2_L (0x003A04C8) +#define PHYA_RXTD_RSSI_COMB_2_L___RWC QCSR_REG_RO +#define PHYA_RXTD_RSSI_COMB_2_L___POR 0x00000080 +#define PHYA_RXTD_RSSI_COMB_2_L__PRE_RSSI_COMB___POR 0x80 +#define PHYA_RXTD_RSSI_COMB_2_L__PRE_RSSI_COMB___M 0x000000FF +#define PHYA_RXTD_RSSI_COMB_2_L__PRE_RSSI_COMB___S 0 +#define PHYA_RXTD_RSSI_COMB_2_L___M 0x000000FF +#define PHYA_RXTD_RSSI_COMB_2_L___S 0 + +#define PHYA_RXTD_RSSI_COMB_3_L (0x003A04D0) +#define PHYA_RXTD_RSSI_COMB_3_L___RWC QCSR_REG_RO +#define PHYA_RXTD_RSSI_COMB_3_L___POR 0x00000080 +#define PHYA_RXTD_RSSI_COMB_3_L__POST_RSSI_COMB___POR 0x80 +#define PHYA_RXTD_RSSI_COMB_3_L__POST_RSSI_COMB___M 0x000000FF +#define PHYA_RXTD_RSSI_COMB_3_L__POST_RSSI_COMB___S 0 +#define PHYA_RXTD_RSSI_COMB_3_L___M 0x000000FF +#define PHYA_RXTD_RSSI_COMB_3_L___S 0 + +#define PHYA_RXTD_RSSI_COMB_4_L (0x003A04D8) +#define PHYA_RXTD_RSSI_COMB_4_L___RWC QCSR_REG_RO +#define PHYA_RXTD_RSSI_COMB_4_L___POR 0x00000080 +#define PHYA_RXTD_RSSI_COMB_4_L__RSSI_PKT_BW_MAC___POR 0x80 +#define PHYA_RXTD_RSSI_COMB_4_L__RSSI_PKT_BW_MAC___M 0x000000FF +#define PHYA_RXTD_RSSI_COMB_4_L__RSSI_PKT_BW_MAC___S 0 +#define PHYA_RXTD_RSSI_COMB_4_L___M 0x000000FF +#define PHYA_RXTD_RSSI_COMB_4_L___S 0 + +#define PHYA_RXTD_RSSI_COMB_5_L (0x003A04E0) +#define PHYA_RXTD_RSSI_COMB_5_L___RWC QCSR_REG_RO +#define PHYA_RXTD_RSSI_COMB_5_L___POR 0x00000080 +#define PHYA_RXTD_RSSI_COMB_5_L__RSSI_PRI20_COMB_MAC___POR 0x80 +#define PHYA_RXTD_RSSI_COMB_5_L__RSSI_PRI20_COMB_MAC___M 0x000000FF +#define PHYA_RXTD_RSSI_COMB_5_L__RSSI_PRI20_COMB_MAC___S 0 +#define PHYA_RXTD_RSSI_COMB_5_L___M 0x000000FF +#define PHYA_RXTD_RSSI_COMB_5_L___S 0 + +#define PHYA_RXTD_RSSI_COMB_6_L (0x003A04E8) +#define PHYA_RXTD_RSSI_COMB_6_L___RWC QCSR_REG_RO +#define PHYA_RXTD_RSSI_COMB_6_L___POR 0x00000000 +#define PHYA_RXTD_RSSI_COMB_6_L__RSSI_OUT_RESERVED___POR 0x00 +#define PHYA_RXTD_RSSI_COMB_6_L__RSSI_OUT_RESERVED___M 0x000000FF +#define PHYA_RXTD_RSSI_COMB_6_L__RSSI_OUT_RESERVED___S 0 +#define PHYA_RXTD_RSSI_COMB_6_L___M 0x000000FF +#define PHYA_RXTD_RSSI_COMB_6_L___S 0 + +#define PHYA_RXTD_PKT_PARAM_0_L (0x003A04F0) +#define PHYA_RXTD_PKT_PARAM_0_L___RWC QCSR_REG_RO +#define PHYA_RXTD_PKT_PARAM_0_L___POR 0x00000000 +#define PHYA_RXTD_PKT_PARAM_0_L__DET_11B___POR 0x0 +#define PHYA_RXTD_PKT_PARAM_0_L__BTCF_TIMING_BACKOFF___POR 0x00 +#define PHYA_RXTD_PKT_PARAM_0_L__VSRC_PHASE___POR 0x000 +#define PHYA_RXTD_PKT_PARAM_0_L__DET_11B___M 0x01000000 +#define PHYA_RXTD_PKT_PARAM_0_L__DET_11B___S 24 +#define PHYA_RXTD_PKT_PARAM_0_L__BTCF_TIMING_BACKOFF___M 0x00FF0000 +#define PHYA_RXTD_PKT_PARAM_0_L__BTCF_TIMING_BACKOFF___S 16 +#define PHYA_RXTD_PKT_PARAM_0_L__VSRC_PHASE___M 0x00000FFF +#define PHYA_RXTD_PKT_PARAM_0_L__VSRC_PHASE___S 0 +#define PHYA_RXTD_PKT_PARAM_0_L___M 0x01FF0FFF +#define PHYA_RXTD_PKT_PARAM_0_L___S 0 + +#define PHYA_RXTD_PKT_PARAM_0_U (0x003A04F4) +#define PHYA_RXTD_PKT_PARAM_0_U___RWC QCSR_REG_RO +#define PHYA_RXTD_PKT_PARAM_0_U___POR 0x00000000 +#define PHYA_RXTD_PKT_PARAM_0_U__WEAK_LOW_DETECT___POR 0x0 +#define PHYA_RXTD_PKT_PARAM_0_U__WEAK_LOW_DETECT___M 0x00000001 +#define PHYA_RXTD_PKT_PARAM_0_U__WEAK_LOW_DETECT___S 0 +#define PHYA_RXTD_PKT_PARAM_0_U___M 0x00000001 +#define PHYA_RXTD_PKT_PARAM_0_U___S 0 + +#define PHYA_RXTD_PKT_PARAM_1_L (0x003A04F8) +#define PHYA_RXTD_PKT_PARAM_1_L___RWC QCSR_REG_RO +#define PHYA_RXTD_PKT_PARAM_1_L___POR 0x00000000 +#define PHYA_RXTD_PKT_PARAM_1_L__RBHPC_PMI_DATA___POR 0x00000000 +#define PHYA_RXTD_PKT_PARAM_1_L__RBHPC_PMI_DATA___M 0xFFFFFFFF +#define PHYA_RXTD_PKT_PARAM_1_L__RBHPC_PMI_DATA___S 0 +#define PHYA_RXTD_PKT_PARAM_1_L___M 0xFFFFFFFF +#define PHYA_RXTD_PKT_PARAM_1_L___S 0 + +#define PHYA_RXTD_PKT_PARAM_1_U (0x003A04FC) +#define PHYA_RXTD_PKT_PARAM_1_U___RWC QCSR_REG_RO +#define PHYA_RXTD_PKT_PARAM_1_U___POR 0x00000000 +#define PHYA_RXTD_PKT_PARAM_1_U__RBHPC_PMI_DVALID___POR 0x0 +#define PHYA_RXTD_PKT_PARAM_1_U__RBHPC_PMI_DVALID___M 0x0000000F +#define PHYA_RXTD_PKT_PARAM_1_U__RBHPC_PMI_DVALID___S 0 +#define PHYA_RXTD_PKT_PARAM_1_U___M 0x0000000F +#define PHYA_RXTD_PKT_PARAM_1_U___S 0 + +#define PHYA_RXTD_AGC_NFCAL_PHY_L (0x003A0500) +#define PHYA_RXTD_AGC_NFCAL_PHY_L___RWC QCSR_REG_RW +#define PHYA_RXTD_AGC_NFCAL_PHY_L___POR 0x00000000 +#define PHYA_RXTD_AGC_NFCAL_PHY_L__DO_NOISEFLOOR___POR 0x0 +#define PHYA_RXTD_AGC_NFCAL_PHY_L__DO_NOISEFLOOR___M 0x00000001 +#define PHYA_RXTD_AGC_NFCAL_PHY_L__DO_NOISEFLOOR___S 0 +#define PHYA_RXTD_AGC_NFCAL_PHY_L___M 0x00000001 +#define PHYA_RXTD_AGC_NFCAL_PHY_L___S 0 + +#define PHYA_RXTD_BT_COEX_TLV_1_L (0x003A0508) +#define PHYA_RXTD_BT_COEX_TLV_1_L___RWC QCSR_REG_RW +#define PHYA_RXTD_BT_COEX_TLV_1_L___POR 0x00000000 +#define PHYA_RXTD_BT_COEX_TLV_1_L__WLAN_BT_PRIORITY___POR 0x0 +#define PHYA_RXTD_BT_COEX_TLV_1_L__SHARED_ANT_DEWEIGHT_VALID___POR 0x0 +#define PHYA_RXTD_BT_COEX_TLV_1_L__BT_XLNA_SETTING___POR 0x0 +#define PHYA_RXTD_BT_COEX_TLV_1_L__BT_ILNA_SETTING___POR 0x0 +#define PHYA_RXTD_BT_COEX_TLV_1_L__LNA_LOCKED_BY_BT___POR 0x0 +#define PHYA_RXTD_BT_COEX_TLV_1_L__LNA_IN_USE_BY_BT___POR 0x0 +#define PHYA_RXTD_BT_COEX_TLV_1_L__BT_IN_TX___POR 0x0 +#define PHYA_RXTD_BT_COEX_TLV_1_L__WLAN_BT_PRIORITY___M 0x00000600 +#define PHYA_RXTD_BT_COEX_TLV_1_L__WLAN_BT_PRIORITY___S 9 +#define PHYA_RXTD_BT_COEX_TLV_1_L__SHARED_ANT_DEWEIGHT_VALID___M 0x00000100 +#define PHYA_RXTD_BT_COEX_TLV_1_L__SHARED_ANT_DEWEIGHT_VALID___S 8 +#define PHYA_RXTD_BT_COEX_TLV_1_L__BT_XLNA_SETTING___M 0x000000C0 +#define PHYA_RXTD_BT_COEX_TLV_1_L__BT_XLNA_SETTING___S 6 +#define PHYA_RXTD_BT_COEX_TLV_1_L__BT_ILNA_SETTING___M 0x00000038 +#define PHYA_RXTD_BT_COEX_TLV_1_L__BT_ILNA_SETTING___S 3 +#define PHYA_RXTD_BT_COEX_TLV_1_L__LNA_LOCKED_BY_BT___M 0x00000004 +#define PHYA_RXTD_BT_COEX_TLV_1_L__LNA_LOCKED_BY_BT___S 2 +#define PHYA_RXTD_BT_COEX_TLV_1_L__LNA_IN_USE_BY_BT___M 0x00000002 +#define PHYA_RXTD_BT_COEX_TLV_1_L__LNA_IN_USE_BY_BT___S 1 +#define PHYA_RXTD_BT_COEX_TLV_1_L__BT_IN_TX___M 0x00000001 +#define PHYA_RXTD_BT_COEX_TLV_1_L__BT_IN_TX___S 0 +#define PHYA_RXTD_BT_COEX_TLV_1_L___M 0x000007FF +#define PHYA_RXTD_BT_COEX_TLV_1_L___S 0 + +#define PHYA_RXTD_BT_COEX_TLV_2_L (0x003A0510) +#define PHYA_RXTD_BT_COEX_TLV_2_L___RWC QCSR_REG_RW +#define PHYA_RXTD_BT_COEX_TLV_2_L___POR 0x00000000 +#define PHYA_RXTD_BT_COEX_TLV_2_L__BT_CCA_THRESHOLD_VALUE_160___POR 0x00 +#define PHYA_RXTD_BT_COEX_TLV_2_L__BT_CCA_THRESHOLD_VALUE_80___POR 0x00 +#define PHYA_RXTD_BT_COEX_TLV_2_L__BT_CCA_THRESHOLD_VALUE_40___POR 0x00 +#define PHYA_RXTD_BT_COEX_TLV_2_L__BT_CCA_THRESHOLD_VALUE_20___POR 0x00 +#define PHYA_RXTD_BT_COEX_TLV_2_L__BT_CCA_THRESHOLD_VALUE_160___M 0xFF000000 +#define PHYA_RXTD_BT_COEX_TLV_2_L__BT_CCA_THRESHOLD_VALUE_160___S 24 +#define PHYA_RXTD_BT_COEX_TLV_2_L__BT_CCA_THRESHOLD_VALUE_80___M 0x00FF0000 +#define PHYA_RXTD_BT_COEX_TLV_2_L__BT_CCA_THRESHOLD_VALUE_80___S 16 +#define PHYA_RXTD_BT_COEX_TLV_2_L__BT_CCA_THRESHOLD_VALUE_40___M 0x0000FF00 +#define PHYA_RXTD_BT_COEX_TLV_2_L__BT_CCA_THRESHOLD_VALUE_40___S 8 +#define PHYA_RXTD_BT_COEX_TLV_2_L__BT_CCA_THRESHOLD_VALUE_20___M 0x000000FF +#define PHYA_RXTD_BT_COEX_TLV_2_L__BT_CCA_THRESHOLD_VALUE_20___S 0 +#define PHYA_RXTD_BT_COEX_TLV_2_L___M 0xFFFFFFFF +#define PHYA_RXTD_BT_COEX_TLV_2_L___S 0 + +#define PHYA_RXTD_DETECT_PWR_ERR_L (0x003A0518) +#define PHYA_RXTD_DETECT_PWR_ERR_L___RWC QCSR_REG_RW +#define PHYA_RXTD_DETECT_PWR_ERR_L___POR 0x0101140C +#define PHYA_RXTD_DETECT_PWR_ERR_L__DET_DROP_ENABLE___POR 0x1 +#define PHYA_RXTD_DETECT_PWR_ERR_L__DET_SURGE_ENABLE___POR 0x1 +#define PHYA_RXTD_DETECT_PWR_ERR_L__PWRDROP_DELTA_THR_DB___POR 0x14 +#define PHYA_RXTD_DETECT_PWR_ERR_L__PWRSURGE_DELTA_THR_DB___POR 0x0C +#define PHYA_RXTD_DETECT_PWR_ERR_L__DET_DROP_ENABLE___M 0x01000000 +#define PHYA_RXTD_DETECT_PWR_ERR_L__DET_DROP_ENABLE___S 24 +#define PHYA_RXTD_DETECT_PWR_ERR_L__DET_SURGE_ENABLE___M 0x00010000 +#define PHYA_RXTD_DETECT_PWR_ERR_L__DET_SURGE_ENABLE___S 16 +#define PHYA_RXTD_DETECT_PWR_ERR_L__PWRDROP_DELTA_THR_DB___M 0x00001F00 +#define PHYA_RXTD_DETECT_PWR_ERR_L__PWRDROP_DELTA_THR_DB___S 8 +#define PHYA_RXTD_DETECT_PWR_ERR_L__PWRSURGE_DELTA_THR_DB___M 0x0000001F +#define PHYA_RXTD_DETECT_PWR_ERR_L__PWRSURGE_DELTA_THR_DB___S 0 +#define PHYA_RXTD_DETECT_PWR_ERR_L___M 0x01011F1F +#define PHYA_RXTD_DETECT_PWR_ERR_L___S 0 + +#define PHYA_RXTD_DETECT_PWR_ERR_U (0x003A051C) +#define PHYA_RXTD_DETECT_PWR_ERR_U___RWC QCSR_REG_RW +#define PHYA_RXTD_DETECT_PWR_ERR_U___POR 0x00000000 +#define PHYA_RXTD_DETECT_PWR_ERR_U__PWR_ERR_FAST___POR 0x0 +#define PHYA_RXTD_DETECT_PWR_ERR_U__DIS_SEC80_DROP___POR 0x0 +#define PHYA_RXTD_DETECT_PWR_ERR_U__DIS_SEC80_SURGE___POR 0x0 +#define PHYA_RXTD_DETECT_PWR_ERR_U__PWR_ERR_FAST___M 0x00010000 +#define PHYA_RXTD_DETECT_PWR_ERR_U__PWR_ERR_FAST___S 16 +#define PHYA_RXTD_DETECT_PWR_ERR_U__DIS_SEC80_DROP___M 0x00000100 +#define PHYA_RXTD_DETECT_PWR_ERR_U__DIS_SEC80_DROP___S 8 +#define PHYA_RXTD_DETECT_PWR_ERR_U__DIS_SEC80_SURGE___M 0x00000001 +#define PHYA_RXTD_DETECT_PWR_ERR_U__DIS_SEC80_SURGE___S 0 +#define PHYA_RXTD_DETECT_PWR_ERR_U___M 0x00010101 +#define PHYA_RXTD_DETECT_PWR_ERR_U___S 0 + +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L (0x003A0520) +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L___RWC QCSR_REG_RW +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L___POR 0x00000000 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L__CTE_FAIL_STR_WEAK___POR 0x0 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L__COARSE_TIMING_TIMEOUT_ERROR___POR 0x0 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L__BTCF_PACKET_DETECT_ERROR___POR 0x0 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L__BTCF_TIMING_TIMEOUT_ERROR___POR 0x0 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L__POWER_DROP___POR 0x0 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L__POWER_SURGE___POR 0x0 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L__CCK_FAIL___POR 0x0 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L__STRONG_SIG_FAIL___POR 0x0 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L__WEAK_DET_FAIL___POR 0x0 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L__VOTING_FAIL___POR 0x0 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L__CTE_FAIL_STR_WEAK___M 0x00000200 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L__CTE_FAIL_STR_WEAK___S 9 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L__COARSE_TIMING_TIMEOUT_ERROR___M 0x00000100 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L__COARSE_TIMING_TIMEOUT_ERROR___S 8 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L__BTCF_PACKET_DETECT_ERROR___M 0x00000080 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L__BTCF_PACKET_DETECT_ERROR___S 7 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L__BTCF_TIMING_TIMEOUT_ERROR___M 0x00000040 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L__BTCF_TIMING_TIMEOUT_ERROR___S 6 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L__POWER_DROP___M 0x00000020 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L__POWER_DROP___S 5 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L__POWER_SURGE___M 0x00000010 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L__POWER_SURGE___S 4 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L__CCK_FAIL___M 0x00000008 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L__CCK_FAIL___S 3 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L__STRONG_SIG_FAIL___M 0x00000004 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L__STRONG_SIG_FAIL___S 2 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L__WEAK_DET_FAIL___M 0x00000002 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L__WEAK_DET_FAIL___S 1 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L__VOTING_FAIL___M 0x00000001 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L__VOTING_FAIL___S 0 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L___M 0x000003FF +#define PHYA_RXTD_RXTD_RESTART_CAUSE_L___S 0 + +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L (0x003A0528) +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L___RWC QCSR_REG_RW +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L___POR 0x00000000 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__CTE_FAIL_STR_WEAK_MASK___POR 0x0 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__COARSE_TIMING_TIMEOUT_ERROR_MASK___POR 0x0 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__BTCF_PACKET_DETECT_ERROR_MASK___POR 0x0 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__BTCF_TIMING_TIMEOUT_ERROR_MASK___POR 0x0 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__POWER_DROP_MASK___POR 0x0 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__POWER_SURGE_MASK___POR 0x0 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__CCK_FAIL_MASK___POR 0x0 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__STRONG_SIG_FAIL_MASK___POR 0x0 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__WEAK_DET_FAIL_MASK___POR 0x0 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__VOTING_FAIL_MASK___POR 0x0 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__CTE_FAIL_STR_WEAK_MASK___M 0x00000200 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__CTE_FAIL_STR_WEAK_MASK___S 9 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__COARSE_TIMING_TIMEOUT_ERROR_MASK___M 0x00000100 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__COARSE_TIMING_TIMEOUT_ERROR_MASK___S 8 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__BTCF_PACKET_DETECT_ERROR_MASK___M 0x00000080 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__BTCF_PACKET_DETECT_ERROR_MASK___S 7 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__BTCF_TIMING_TIMEOUT_ERROR_MASK___M 0x00000040 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__BTCF_TIMING_TIMEOUT_ERROR_MASK___S 6 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__POWER_DROP_MASK___M 0x00000020 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__POWER_DROP_MASK___S 5 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__POWER_SURGE_MASK___M 0x00000010 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__POWER_SURGE_MASK___S 4 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__CCK_FAIL_MASK___M 0x00000008 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__CCK_FAIL_MASK___S 3 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__STRONG_SIG_FAIL_MASK___M 0x00000004 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__STRONG_SIG_FAIL_MASK___S 2 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__WEAK_DET_FAIL_MASK___M 0x00000002 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__WEAK_DET_FAIL_MASK___S 1 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__VOTING_FAIL_MASK___M 0x00000001 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L__VOTING_FAIL_MASK___S 0 +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L___M 0x000003FF +#define PHYA_RXTD_RXTD_RESTART_CAUSE_MASK_L___S 0 + +#define PHYA_RXTD_CCK_ERROR_CAUSE_L (0x003A0530) +#define PHYA_RXTD_CCK_ERROR_CAUSE_L___RWC QCSR_REG_RO +#define PHYA_RXTD_CCK_ERROR_CAUSE_L___POR 0x00000000 +#define PHYA_RXTD_CCK_ERROR_CAUSE_L__CCK_ERROR_CAUSE___POR 0x00 +#define PHYA_RXTD_CCK_ERROR_CAUSE_L__CCK_ERROR_CAUSE___M 0x000000FF +#define PHYA_RXTD_CCK_ERROR_CAUSE_L__CCK_ERROR_CAUSE___S 0 +#define PHYA_RXTD_CCK_ERROR_CAUSE_L___M 0x000000FF +#define PHYA_RXTD_CCK_ERROR_CAUSE_L___S 0 + +#define PHYA_RXTD_DET0_RADAR_DETECTION_L (0x003A0538) +#define PHYA_RXTD_DET0_RADAR_DETECTION_L___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_RADAR_DETECTION_L___POR 0x007FFC07 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_FFT_CHN_SEL___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_MAX_WIDTH_CHK_ENA___POR 0x1 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_NONLIN_VEL_CHK_ENA___POR 0x1 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_DELTA_PEAK_CHK_ENA___POR 0x1 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_TIME_PHASE_CHK_ENA___POR 0x1 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_TIME_AMP_CHK_ENA___POR 0x1 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_TIME_FREQ_CHK_ENA___POR 0x1 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_ADCSAT_PEAKMAG_CHK_ENA___POR 0x1 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_BBSAT_PEAKMAG_CHK_ENA___POR 0x1 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_RFSAT_PEAKMAG_CHK_ENA___POR 0x1 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_IBPWR_CHK_ENA___POR 0x1 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_IB_CHK_ENA___POR 0x1 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_NB_CHK_ENA___POR 0x1 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_TRIGGER_MASK___POR 0x80 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_END_OB_RADAR_ENA___POR 0x1 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_START_OB_RADAR_ENA___POR 0x1 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_ENABLE___POR 0x1 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_FFT_CHN_SEL___M 0x03800000 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_FFT_CHN_SEL___S 23 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_MAX_WIDTH_CHK_ENA___M 0x00400000 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_MAX_WIDTH_CHK_ENA___S 22 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_NONLIN_VEL_CHK_ENA___M 0x00200000 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_NONLIN_VEL_CHK_ENA___S 21 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_DELTA_PEAK_CHK_ENA___M 0x00100000 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_DELTA_PEAK_CHK_ENA___S 20 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_TIME_PHASE_CHK_ENA___M 0x00080000 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_TIME_PHASE_CHK_ENA___S 19 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_TIME_AMP_CHK_ENA___M 0x00040000 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_TIME_AMP_CHK_ENA___S 18 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_TIME_FREQ_CHK_ENA___M 0x00020000 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_TIME_FREQ_CHK_ENA___S 17 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_ADCSAT_PEAKMAG_CHK_ENA___M 0x00010000 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_ADCSAT_PEAKMAG_CHK_ENA___S 16 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_BBSAT_PEAKMAG_CHK_ENA___M 0x00008000 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_BBSAT_PEAKMAG_CHK_ENA___S 15 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_RFSAT_PEAKMAG_CHK_ENA___M 0x00004000 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_RFSAT_PEAKMAG_CHK_ENA___S 14 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_IBPWR_CHK_ENA___M 0x00002000 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_IBPWR_CHK_ENA___S 13 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_IB_CHK_ENA___M 0x00001000 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_IB_CHK_ENA___S 12 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_NB_CHK_ENA___M 0x00000800 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_NB_CHK_ENA___S 11 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_TRIGGER_MASK___M 0x000007F8 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_TRIGGER_MASK___S 3 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_END_OB_RADAR_ENA___M 0x00000004 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_END_OB_RADAR_ENA___S 2 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_START_OB_RADAR_ENA___M 0x00000002 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_START_OB_RADAR_ENA___S 1 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_ENABLE___M 0x00000001 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L__DET0_RADAR_ENABLE___S 0 +#define PHYA_RXTD_DET0_RADAR_DETECTION_L___M 0x03FFFFFF +#define PHYA_RXTD_DET0_RADAR_DETECTION_L___S 0 + +#define PHYA_RXTD_DET0_RADAR_DETECTION_U (0x003A053C) +#define PHYA_RXTD_DET0_RADAR_DETECTION_U___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_RADAR_DETECTION_U___POR 0x01A78478 +#define PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_BUFFER_MODE___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_VERBOSE_MODE___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_RADAR_AGC_DONE_TIME___POR 0x6 +#define PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_RADAR_TIMER_INIT___POR 0x9 +#define PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_RADAR_FIRST_FFT_DELAY___POR 0xE1 +#define PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_PULSE_WIDTH_MAX___POR 0x078 +#define PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_BUFFER_MODE___M 0x08000000 +#define PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_BUFFER_MODE___S 27 +#define PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_VERBOSE_MODE___M 0x04000000 +#define PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_VERBOSE_MODE___S 26 +#define PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_RADAR_AGC_DONE_TIME___M 0x03C00000 +#define PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_RADAR_AGC_DONE_TIME___S 22 +#define PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_RADAR_TIMER_INIT___M 0x003C0000 +#define PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_RADAR_TIMER_INIT___S 18 +#define PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_RADAR_FIRST_FFT_DELAY___M 0x0003FC00 +#define PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_RADAR_FIRST_FFT_DELAY___S 10 +#define PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_PULSE_WIDTH_MAX___M 0x000003FF +#define PHYA_RXTD_DET0_RADAR_DETECTION_U__DET0_PULSE_WIDTH_MAX___S 0 +#define PHYA_RXTD_DET0_RADAR_DETECTION_U___M 0x0FFFFFFF +#define PHYA_RXTD_DET0_RADAR_DETECTION_U___S 0 + +#define PHYA_RXTD_DET0_RADAR_TIMEOUT_L (0x003A0540) +#define PHYA_RXTD_DET0_RADAR_TIMEOUT_L___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_RADAR_TIMEOUT_L___POR 0x00000000 +#define PHYA_RXTD_DET0_RADAR_TIMEOUT_L__DET0_RADAR_SM_TIMEOUT___POR 0x000 +#define PHYA_RXTD_DET0_RADAR_TIMEOUT_L__DET0_RADAR_SM_TIMEOUT___M 0x000003FF +#define PHYA_RXTD_DET0_RADAR_TIMEOUT_L__DET0_RADAR_SM_TIMEOUT___S 0 +#define PHYA_RXTD_DET0_RADAR_TIMEOUT_L___M 0x000003FF +#define PHYA_RXTD_DET0_RADAR_TIMEOUT_L___S 0 + +#define PHYA_RXTD_DET0_RADAR_POW_DET_L (0x003A0548) +#define PHYA_RXTD_DET0_RADAR_POW_DET_L___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_RADAR_POW_DET_L___POR 0x13832064 +#define PHYA_RXTD_DET0_RADAR_POW_DET_L__DET0_RADAR_PD_DC_NOTCH_ALPHA___POR 0x4 +#define PHYA_RXTD_DET0_RADAR_POW_DET_L__DET0_RADAR_PD_DC_CHECK_ENA___POR 0x1 +#define PHYA_RXTD_DET0_RADAR_POW_DET_L__DET0_RADAR_PD_NUM_LOW___POR 0x18 +#define PHYA_RXTD_DET0_RADAR_POW_DET_L__DET0_RADAR_PD_MA_TH_HIGH___POR 0x0C8 +#define PHYA_RXTD_DET0_RADAR_POW_DET_L__DET0_RADAR_PD_MA_TH_LOW___POR 0x064 +#define PHYA_RXTD_DET0_RADAR_POW_DET_L__DET0_RADAR_PD_DC_NOTCH_ALPHA___M 0x1C000000 +#define PHYA_RXTD_DET0_RADAR_POW_DET_L__DET0_RADAR_PD_DC_NOTCH_ALPHA___S 26 +#define PHYA_RXTD_DET0_RADAR_POW_DET_L__DET0_RADAR_PD_DC_CHECK_ENA___M 0x02000000 +#define PHYA_RXTD_DET0_RADAR_POW_DET_L__DET0_RADAR_PD_DC_CHECK_ENA___S 25 +#define PHYA_RXTD_DET0_RADAR_POW_DET_L__DET0_RADAR_PD_NUM_LOW___M 0x01F00000 +#define PHYA_RXTD_DET0_RADAR_POW_DET_L__DET0_RADAR_PD_NUM_LOW___S 20 +#define PHYA_RXTD_DET0_RADAR_POW_DET_L__DET0_RADAR_PD_MA_TH_HIGH___M 0x000FFC00 +#define PHYA_RXTD_DET0_RADAR_POW_DET_L__DET0_RADAR_PD_MA_TH_HIGH___S 10 +#define PHYA_RXTD_DET0_RADAR_POW_DET_L__DET0_RADAR_PD_MA_TH_LOW___M 0x000003FF +#define PHYA_RXTD_DET0_RADAR_POW_DET_L__DET0_RADAR_PD_MA_TH_LOW___S 0 +#define PHYA_RXTD_DET0_RADAR_POW_DET_L___M 0x1FFFFFFF +#define PHYA_RXTD_DET0_RADAR_POW_DET_L___S 0 + +#define PHYA_RXTD_DET0_RADAR_POW_DET_U (0x003A054C) +#define PHYA_RXTD_DET0_RADAR_POW_DET_U___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_RADAR_POW_DET_U___POR 0x0C8053CD +#define PHYA_RXTD_DET0_RADAR_POW_DET_U__DET0_RADAR_PD_JUMP_TH___POR 0x32 +#define PHYA_RXTD_DET0_RADAR_POW_DET_U__DET0_RADAR_POWER_ADJ___POR 0x014 +#define PHYA_RXTD_DET0_RADAR_POW_DET_U__DET0_RADAR_PD_MA_LENGTH___POR 0x3 +#define PHYA_RXTD_DET0_RADAR_POW_DET_U__DET0_RADAR_PD_DC_CHECK_TH___POR 0xCD +#define PHYA_RXTD_DET0_RADAR_POW_DET_U__DET0_RADAR_PD_JUMP_TH___M 0x1FC00000 +#define PHYA_RXTD_DET0_RADAR_POW_DET_U__DET0_RADAR_PD_JUMP_TH___S 22 +#define PHYA_RXTD_DET0_RADAR_POW_DET_U__DET0_RADAR_POWER_ADJ___M 0x003FFC00 +#define PHYA_RXTD_DET0_RADAR_POW_DET_U__DET0_RADAR_POWER_ADJ___S 10 +#define PHYA_RXTD_DET0_RADAR_POW_DET_U__DET0_RADAR_PD_MA_LENGTH___M 0x00000300 +#define PHYA_RXTD_DET0_RADAR_POW_DET_U__DET0_RADAR_PD_MA_LENGTH___S 8 +#define PHYA_RXTD_DET0_RADAR_POW_DET_U__DET0_RADAR_PD_DC_CHECK_TH___M 0x000000FF +#define PHYA_RXTD_DET0_RADAR_POW_DET_U__DET0_RADAR_PD_DC_CHECK_TH___S 0 +#define PHYA_RXTD_DET0_RADAR_POW_DET_U___M 0x1FFFFFFF +#define PHYA_RXTD_DET0_RADAR_POW_DET_U___S 0 + +#define PHYA_RXTD_DET0_RADAR_FFT_THR_L (0x003A0550) +#define PHYA_RXTD_DET0_RADAR_FFT_THR_L___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_RADAR_FFT_THR_L___POR 0x841905D4 +#define PHYA_RXTD_DET0_RADAR_FFT_THR_L__DET0_CHIRP_END_OB_BIN_NUM___POR 0x8 +#define PHYA_RXTD_DET0_RADAR_FFT_THR_L__DET0_CHIRP_START_OB_BIN_NUM___POR 0x4 +#define PHYA_RXTD_DET0_RADAR_FFT_THR_L__DET0_SRCH_FFT_ADCSAT_PEAKMAG_THR___POR 0x064 +#define PHYA_RXTD_DET0_RADAR_FFT_THR_L__DET0_NB_TONE_THRES_RADAR_CHIRP___POR 0x17 +#define PHYA_RXTD_DET0_RADAR_FFT_THR_L__DET0_STR_BIN_THR_RADAR_CHIRP___POR 0x14 +#define PHYA_RXTD_DET0_RADAR_FFT_THR_L__DET0_CHIRP_END_OB_BIN_NUM___M 0xF0000000 +#define PHYA_RXTD_DET0_RADAR_FFT_THR_L__DET0_CHIRP_END_OB_BIN_NUM___S 28 +#define PHYA_RXTD_DET0_RADAR_FFT_THR_L__DET0_CHIRP_START_OB_BIN_NUM___M 0x0F000000 +#define PHYA_RXTD_DET0_RADAR_FFT_THR_L__DET0_CHIRP_START_OB_BIN_NUM___S 24 +#define PHYA_RXTD_DET0_RADAR_FFT_THR_L__DET0_SRCH_FFT_ADCSAT_PEAKMAG_THR___M 0x00FFC000 +#define PHYA_RXTD_DET0_RADAR_FFT_THR_L__DET0_SRCH_FFT_ADCSAT_PEAKMAG_THR___S 14 +#define PHYA_RXTD_DET0_RADAR_FFT_THR_L__DET0_NB_TONE_THRES_RADAR_CHIRP___M 0x00003FC0 +#define PHYA_RXTD_DET0_RADAR_FFT_THR_L__DET0_NB_TONE_THRES_RADAR_CHIRP___S 6 +#define PHYA_RXTD_DET0_RADAR_FFT_THR_L__DET0_STR_BIN_THR_RADAR_CHIRP___M 0x0000003F +#define PHYA_RXTD_DET0_RADAR_FFT_THR_L__DET0_STR_BIN_THR_RADAR_CHIRP___S 0 +#define PHYA_RXTD_DET0_RADAR_FFT_THR_L___M 0xFFFFFFFF +#define PHYA_RXTD_DET0_RADAR_FFT_THR_L___S 0 + +#define PHYA_RXTD_DET0_RADAR_FFT_THR_U (0x003A0554) +#define PHYA_RXTD_DET0_RADAR_FFT_THR_U___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_RADAR_FFT_THR_U___POR 0x00000005 +#define PHYA_RXTD_DET0_RADAR_FFT_THR_U__DET0_ALLOW_OB_CHIRP_RESTART___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_FFT_THR_U__DET0_CHIRP_FFT_STR_BIN_MAG_THR___POR 0x5 +#define PHYA_RXTD_DET0_RADAR_FFT_THR_U__DET0_ALLOW_OB_CHIRP_RESTART___M 0x00000010 +#define PHYA_RXTD_DET0_RADAR_FFT_THR_U__DET0_ALLOW_OB_CHIRP_RESTART___S 4 +#define PHYA_RXTD_DET0_RADAR_FFT_THR_U__DET0_CHIRP_FFT_STR_BIN_MAG_THR___M 0x0000000F +#define PHYA_RXTD_DET0_RADAR_FFT_THR_U__DET0_CHIRP_FFT_STR_BIN_MAG_THR___S 0 +#define PHYA_RXTD_DET0_RADAR_FFT_THR_U___M 0x0000001F +#define PHYA_RXTD_DET0_RADAR_FFT_THR_U___S 0 + +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L (0x003A0558) +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L___POR 0x400FFFC1 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_SRCH_FFT_SB_FREQ___POR 0x400 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_SPECTRAL_SCAN_DBM_ADJ___POR 0x1 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_RADAR_FFT_DBM_ADJ___POR 0x1 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_SRCH_FFT_SCALE_VEC___POR 0xFFF +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_SPECTRAL_SCAN_BIN_SCALE___POR 0x0 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_RADAR_FFT_BIN_SCALE___POR 0x0 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_SPECTRAL_SCAN_PWR_FORMAT___POR 0x0 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_RADAR_FFT_PWR_FORMAT___POR 0x1 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_SRCH_FFT_SB_FREQ___M 0xFFF00000 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_SRCH_FFT_SB_FREQ___S 20 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_SPECTRAL_SCAN_DBM_ADJ___M 0x00080000 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_SPECTRAL_SCAN_DBM_ADJ___S 19 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_RADAR_FFT_DBM_ADJ___M 0x00040000 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_RADAR_FFT_DBM_ADJ___S 18 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_SRCH_FFT_SCALE_VEC___M 0x0003FFC0 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_SRCH_FFT_SCALE_VEC___S 6 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_SPECTRAL_SCAN_BIN_SCALE___M 0x00000030 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_SPECTRAL_SCAN_BIN_SCALE___S 4 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_RADAR_FFT_BIN_SCALE___M 0x0000000C +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_RADAR_FFT_BIN_SCALE___S 2 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_SPECTRAL_SCAN_PWR_FORMAT___M 0x00000002 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_SPECTRAL_SCAN_PWR_FORMAT___S 1 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_RADAR_FFT_PWR_FORMAT___M 0x00000001 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L__DET0_RADAR_FFT_PWR_FORMAT___S 0 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L___M 0xFFFFFFFF +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_L___S 0 + +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_U (0x003A055C) +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_U___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_U___POR 0x00500802 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_U__DET0_STR_BIN_THR_RADAR___POR 0x05 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_U__DET0_SRCH_FFT_IB_THR_SHORT___POR 0x002 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_U__DET0_SRCH_FFT_IB_THR___POR 0x002 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_U__DET0_STR_BIN_THR_RADAR___M 0x03F00000 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_U__DET0_STR_BIN_THR_RADAR___S 20 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_U__DET0_SRCH_FFT_IB_THR_SHORT___M 0x000FFC00 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_U__DET0_SRCH_FFT_IB_THR_SHORT___S 10 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_U__DET0_SRCH_FFT_IB_THR___M 0x000003FF +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_U__DET0_SRCH_FFT_IB_THR___S 0 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_U___M 0x03FFFFFF +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL1_U___S 0 + +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_L (0x003A0560) +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_L___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_L___POR 0x009B170B +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_L__DET0_SRCH_FFT_RFSAT_PEAKMAG_THR___POR 0x09B +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_L__DET0_NB_TONE_THR_RADAR_BLK___POR 0x17 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_L__DET0_NB_TONE_THR_RADAR_COARSE___POR 0x0B +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_L__DET0_SRCH_FFT_RFSAT_PEAKMAG_THR___M 0x03FF0000 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_L__DET0_SRCH_FFT_RFSAT_PEAKMAG_THR___S 16 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_L__DET0_NB_TONE_THR_RADAR_BLK___M 0x0000FF00 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_L__DET0_NB_TONE_THR_RADAR_BLK___S 8 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_L__DET0_NB_TONE_THR_RADAR_COARSE___M 0x000000FF +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_L__DET0_NB_TONE_THR_RADAR_COARSE___S 0 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_L___M 0x03FFFFFF +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_L___S 0 + +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U (0x003A0564) +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U___POR 0x0023FCC8 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U__DET0_SRCH_FFT_PACK_MODE___POR 0x0 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U__DET0_SRCH_FFT_DC_SCALE_INBAND___POR 0x2 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U__DET0_SRCH_FFT_PWR_DROP_RATIO___POR 0x3 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U__DET0_SRCH_FFT_PWR_LOW_CAP___POR 0x3F +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U__DET0_SRCH_FFT_BBSAT_PEAKMAG_THR___POR 0x0C8 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U__DET0_SRCH_FFT_PACK_MODE___M 0x00800000 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U__DET0_SRCH_FFT_PACK_MODE___S 23 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U__DET0_SRCH_FFT_DC_SCALE_INBAND___M 0x00700000 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U__DET0_SRCH_FFT_DC_SCALE_INBAND___S 20 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U__DET0_SRCH_FFT_PWR_DROP_RATIO___M 0x000F0000 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U__DET0_SRCH_FFT_PWR_DROP_RATIO___S 16 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U__DET0_SRCH_FFT_PWR_LOW_CAP___M 0x0000FC00 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U__DET0_SRCH_FFT_PWR_LOW_CAP___S 10 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U__DET0_SRCH_FFT_BBSAT_PEAKMAG_THR___M 0x000003FF +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U__DET0_SRCH_FFT_BBSAT_PEAKMAG_THR___S 0 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U___M 0x00FFFFFF +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_0_U___S 0 + +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_1_L (0x003A0568) +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_1_L___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_1_L___POR 0x00000000 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_1_L__DET0_MASK_SIDX_DELTA___POR 0x00 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_1_L__DET0_RADAR_SUBBAND_MASK___POR 0x0000 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_1_L__DET0_MASK_SIDX_DELTA___M 0x001F0000 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_1_L__DET0_MASK_SIDX_DELTA___S 16 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_1_L__DET0_RADAR_SUBBAND_MASK___M 0x0000FFFF +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_1_L__DET0_RADAR_SUBBAND_MASK___S 0 +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_1_L___M 0x001FFFFF +#define PHYA_RXTD_DET0_SRCH_FFT_CTRL2_1_L___S 0 + +#define PHYA_RXTD_DET0_RADAR_TIME_THR_L (0x003A0570) +#define PHYA_RXTD_DET0_RADAR_TIME_THR_L___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_RADAR_TIME_THR_L___POR 0x20141928 +#define PHYA_RXTD_DET0_RADAR_TIME_THR_L__DET0_RADAR_TIME_SAMP___POR 0x20 +#define PHYA_RXTD_DET0_RADAR_TIME_THR_L__DET0_RADAR_TIME_PHASE_THR___POR 0x14 +#define PHYA_RXTD_DET0_RADAR_TIME_THR_L__DET0_RADAR_TIME_FREQ_THR___POR 0x19 +#define PHYA_RXTD_DET0_RADAR_TIME_THR_L__DET0_RADAR_TIME_AMP_THR___POR 0x28 +#define PHYA_RXTD_DET0_RADAR_TIME_THR_L__DET0_RADAR_TIME_SAMP___M 0x3F000000 +#define PHYA_RXTD_DET0_RADAR_TIME_THR_L__DET0_RADAR_TIME_SAMP___S 24 +#define PHYA_RXTD_DET0_RADAR_TIME_THR_L__DET0_RADAR_TIME_PHASE_THR___M 0x00FF0000 +#define PHYA_RXTD_DET0_RADAR_TIME_THR_L__DET0_RADAR_TIME_PHASE_THR___S 16 +#define PHYA_RXTD_DET0_RADAR_TIME_THR_L__DET0_RADAR_TIME_FREQ_THR___M 0x0000FF00 +#define PHYA_RXTD_DET0_RADAR_TIME_THR_L__DET0_RADAR_TIME_FREQ_THR___S 8 +#define PHYA_RXTD_DET0_RADAR_TIME_THR_L__DET0_RADAR_TIME_AMP_THR___M 0x000000FF +#define PHYA_RXTD_DET0_RADAR_TIME_THR_L__DET0_RADAR_TIME_AMP_THR___S 0 +#define PHYA_RXTD_DET0_RADAR_TIME_THR_L___M 0x3FFFFFFF +#define PHYA_RXTD_DET0_RADAR_TIME_THR_L___S 0 + +#define PHYA_RXTD_DET0_RADAR_TIME_THR_U (0x003A0574) +#define PHYA_RXTD_DET0_RADAR_TIME_THR_U___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_RADAR_TIME_THR_U___POR 0x05031405 +#define PHYA_RXTD_DET0_RADAR_TIME_THR_U__DET0_RADAR_TIME_PROC_DELAY___POR 0x14 +#define PHYA_RXTD_DET0_RADAR_TIME_THR_U__DET0_RADAR_MAX_IQ_ZERO_CROSS_DIFF___POR 0x03 +#define PHYA_RXTD_DET0_RADAR_TIME_THR_U__DET0_RADAR_MIN_NUM_ZERO_CROSS___POR 0x05 +#define PHYA_RXTD_DET0_RADAR_TIME_THR_U__DET0_RADAR_ZERO_CROSS_NOISE_THR___POR 0x005 +#define PHYA_RXTD_DET0_RADAR_TIME_THR_U__DET0_RADAR_TIME_PROC_DELAY___M 0x0FC00000 +#define PHYA_RXTD_DET0_RADAR_TIME_THR_U__DET0_RADAR_TIME_PROC_DELAY___S 22 +#define PHYA_RXTD_DET0_RADAR_TIME_THR_U__DET0_RADAR_MAX_IQ_ZERO_CROSS_DIFF___M 0x003F0000 +#define PHYA_RXTD_DET0_RADAR_TIME_THR_U__DET0_RADAR_MAX_IQ_ZERO_CROSS_DIFF___S 16 +#define PHYA_RXTD_DET0_RADAR_TIME_THR_U__DET0_RADAR_MIN_NUM_ZERO_CROSS___M 0x0000FC00 +#define PHYA_RXTD_DET0_RADAR_TIME_THR_U__DET0_RADAR_MIN_NUM_ZERO_CROSS___S 10 +#define PHYA_RXTD_DET0_RADAR_TIME_THR_U__DET0_RADAR_ZERO_CROSS_NOISE_THR___M 0x000003FF +#define PHYA_RXTD_DET0_RADAR_TIME_THR_U__DET0_RADAR_ZERO_CROSS_NOISE_THR___S 0 +#define PHYA_RXTD_DET0_RADAR_TIME_THR_U___M 0x0FFFFFFF +#define PHYA_RXTD_DET0_RADAR_TIME_THR_U___S 0 + +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_L (0x003A0578) +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_L___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_L___POR 0x3B11A815 +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_PULSE_AT_DC_RSSI_THRESH___POR 0x0E +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_RADAR_FIRPWR_THRESH___POR 0x62 +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_PULSE_DROP_THRESH___POR 0x0D +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_PULSE_RSSI_THRESH___POR 0x10 +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_PULSE_HEIGHT_THRESH___POR 0x0A +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_ENABLE_PULSE_DROP_CHECK___POR 0x1 +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_PULSE_AT_DC_RSSI_THRESH___M 0xFC000000 +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_PULSE_AT_DC_RSSI_THRESH___S 26 +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_RADAR_FIRPWR_THRESH___M 0x03F80000 +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_RADAR_FIRPWR_THRESH___S 19 +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_PULSE_DROP_THRESH___M 0x0007E000 +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_PULSE_DROP_THRESH___S 13 +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_PULSE_RSSI_THRESH___M 0x00001F80 +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_PULSE_RSSI_THRESH___S 7 +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_PULSE_HEIGHT_THRESH___M 0x0000007E +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_PULSE_HEIGHT_THRESH___S 1 +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_ENABLE_PULSE_DROP_CHECK___M 0x00000001 +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_L__DET0_ENABLE_PULSE_DROP_CHECK___S 0 +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_L___M 0xFFFFFFFF +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_L___S 0 + +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_U (0x003A057C) +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_U___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_U___POR 0x000AB38E +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_ENA_DELAY_COUNTER_THR___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_FLAGS_DELAY_COUNTER_THR___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_RADAR_SHORT_PWR___POR 0x55 +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_LONG_PULSE_RSSI_CHECK_ENA___POR 0x1 +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_LONG_PULSE_AT_DC_RSSI_THRESH___POR 0x0E +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_LONG_PULSE_RSSI_THRESH___POR 0x0E +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_ENA_DELAY_COUNTER_THR___M 0x01000000 +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_ENA_DELAY_COUNTER_THR___S 24 +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_FLAGS_DELAY_COUNTER_THR___M 0x00F00000 +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_FLAGS_DELAY_COUNTER_THR___S 20 +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_RADAR_SHORT_PWR___M 0x000FE000 +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_RADAR_SHORT_PWR___S 13 +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_LONG_PULSE_RSSI_CHECK_ENA___M 0x00001000 +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_LONG_PULSE_RSSI_CHECK_ENA___S 12 +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_LONG_PULSE_AT_DC_RSSI_THRESH___M 0x00000FC0 +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_LONG_PULSE_AT_DC_RSSI_THRESH___S 6 +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_LONG_PULSE_RSSI_THRESH___M 0x0000003F +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_U__DET0_LONG_PULSE_RSSI_THRESH___S 0 +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_U___M 0x01FFFFFF +#define PHYA_RXTD_DET0_RADAR_PULSE_THR_U___S 0 + +#define PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L (0x003A0580) +#define PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L___POR 0x02D06C0A +#define PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_FFT_BW_CHECK_ENA___POR 0x1 +#define PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_MAX_NUM_FFT___POR 0x6 +#define PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_RADAR_FFT_LONG_PERIOD___POR 0x8 +#define PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_MAX_DELTA_DIFF___POR 0x3 +#define PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_MAX_DELTA_BIN___POR 0x0C +#define PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_MIN_DELTA_BIN___POR 0x01 +#define PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_MAX_NUM_DIFF___POR 0x2 +#define PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_FFT_BW_CHECK_ENA___M 0x02000000 +#define PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_FFT_BW_CHECK_ENA___S 25 +#define PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_MAX_NUM_FFT___M 0x01E00000 +#define PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_MAX_NUM_FFT___S 21 +#define PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_RADAR_FFT_LONG_PERIOD___M 0x001E0000 +#define PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_RADAR_FFT_LONG_PERIOD___S 17 +#define PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_MAX_DELTA_DIFF___M 0x0001E000 +#define PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_MAX_DELTA_DIFF___S 13 +#define PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_MAX_DELTA_BIN___M 0x00001F00 +#define PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_MAX_DELTA_BIN___S 8 +#define PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_MIN_DELTA_BIN___M 0x000000F8 +#define PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_MIN_DELTA_BIN___S 3 +#define PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_MAX_NUM_DIFF___M 0x00000007 +#define PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L__DET0_CHIRP_MAX_NUM_DIFF___S 0 +#define PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L___M 0x03FFFFFF +#define PHYA_RXTD_DET0_RADAR_CHIP_DETECT_L___S 0 + +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_L (0x003A0588) +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_L___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_L___POR 0x0081C850 +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_L__DET0_RADAR_LB_DC_CAP_AT_DC___POR 0x20 +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_L__DET0_FORCE_LB_BYPASS___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_L__DET0_RADAR_LB_MODE___POR 0x1 +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_L__DET0_RADAR_LB_DC_CAP_FINE___POR 0xC8 +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_L__DET0_RADAR_LB_DC_CAP___POR 0x50 +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_L__DET0_RADAR_LB_DC_CAP_AT_DC___M 0x03FC0000 +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_L__DET0_RADAR_LB_DC_CAP_AT_DC___S 18 +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_L__DET0_FORCE_LB_BYPASS___M 0x00020000 +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_L__DET0_FORCE_LB_BYPASS___S 17 +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_L__DET0_RADAR_LB_MODE___M 0x00010000 +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_L__DET0_RADAR_LB_MODE___S 16 +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_L__DET0_RADAR_LB_DC_CAP_FINE___M 0x0000FF00 +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_L__DET0_RADAR_LB_DC_CAP_FINE___S 8 +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_L__DET0_RADAR_LB_DC_CAP___M 0x000000FF +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_L__DET0_RADAR_LB_DC_CAP___S 0 +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_L___M 0x03FFFFFF +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_L___S 0 + +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_U (0x003A058C) +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_U___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_U___POR 0x00066A05 +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_U__DET0_CHIRP_OVER_DC_INTERVAL___POR 0x19 +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_U__DET0_CHIRP_OVER_DC_SKIP_ENA___POR 0x1 +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_U__DET0_RADAR_LB_ADAPT_CMP_THR___POR 0x0A +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_U__DET0_RADAR_LB_CONV_FACTOR___POR 0x05 +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_U__DET0_CHIRP_OVER_DC_INTERVAL___M 0x000FC000 +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_U__DET0_CHIRP_OVER_DC_INTERVAL___S 14 +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_U__DET0_CHIRP_OVER_DC_SKIP_ENA___M 0x00002000 +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_U__DET0_CHIRP_OVER_DC_SKIP_ENA___S 13 +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_U__DET0_RADAR_LB_ADAPT_CMP_THR___M 0x00001F00 +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_U__DET0_RADAR_LB_ADAPT_CMP_THR___S 8 +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_U__DET0_RADAR_LB_CONV_FACTOR___M 0x000000FF +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_U__DET0_RADAR_LB_CONV_FACTOR___S 0 +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_U___M 0x000FFFFF +#define PHYA_RXTD_DET0_RADAR_LB_CTRL_U___S 0 + +#define PHYA_RXTD_DET0_SPECTRAL_SCAN1_L (0x003A0590) +#define PHYA_RXTD_DET0_SPECTRAL_SCAN1_L___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_SPECTRAL_SCAN1_L___POR 0x001BA050 +#define PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_RSSI_RPT_MODE___POR 0x0 +#define PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_WB_RPT_MODE___POR 0x0 +#define PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_PERIOD___POR 0x01B +#define PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_NOISE_FLOOR_REF___POR 0xA0 +#define PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_FFT_SIZE___POR 0x5 +#define PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_FFT_CHN_SEL___POR 0x0 +#define PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_ENA___POR 0x0 +#define PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_RSSI_RPT_MODE___M 0x20000000 +#define PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_RSSI_RPT_MODE___S 29 +#define PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_WB_RPT_MODE___M 0x10000000 +#define PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_WB_RPT_MODE___S 28 +#define PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_PERIOD___M 0x0FFF0000 +#define PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_PERIOD___S 16 +#define PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_NOISE_FLOOR_REF___M 0x0000FF00 +#define PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_NOISE_FLOOR_REF___S 8 +#define PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_FFT_SIZE___M 0x000000F0 +#define PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_FFT_SIZE___S 4 +#define PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_FFT_CHN_SEL___M 0x0000000E +#define PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_FFT_CHN_SEL___S 1 +#define PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_ENA___M 0x00000001 +#define PHYA_RXTD_DET0_SPECTRAL_SCAN1_L__DET0_SPECTRAL_SCAN_ENA___S 0 +#define PHYA_RXTD_DET0_SPECTRAL_SCAN1_L___M 0x3FFFFFFF +#define PHYA_RXTD_DET0_SPECTRAL_SCAN1_L___S 0 + +#define PHYA_RXTD_DET0_SPECTRAL_SCAN2_L (0x003A0598) +#define PHYA_RXTD_DET0_SPECTRAL_SCAN2_L___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_SPECTRAL_SCAN2_L___POR 0x00080C00 +#define PHYA_RXTD_DET0_SPECTRAL_SCAN2_L__DET0_SPECTRAL_SCAN_RFSAT_DELAY___POR 0x0 +#define PHYA_RXTD_DET0_SPECTRAL_SCAN2_L__DET0_SPECTRAL_SCAN_STR_BIN_THR___POR 0x08 +#define PHYA_RXTD_DET0_SPECTRAL_SCAN2_L__DET0_SPECTRAL_SCAN_NB_TONE_THR___POR 0x0C +#define PHYA_RXTD_DET0_SPECTRAL_SCAN2_L__DET0_SPECTRAL_SCAN_RSSI_THR___POR 0x00 +#define PHYA_RXTD_DET0_SPECTRAL_SCAN2_L__DET0_SPECTRAL_SCAN_RFSAT_DELAY___M 0x03C00000 +#define PHYA_RXTD_DET0_SPECTRAL_SCAN2_L__DET0_SPECTRAL_SCAN_RFSAT_DELAY___S 22 +#define PHYA_RXTD_DET0_SPECTRAL_SCAN2_L__DET0_SPECTRAL_SCAN_STR_BIN_THR___M 0x003F0000 +#define PHYA_RXTD_DET0_SPECTRAL_SCAN2_L__DET0_SPECTRAL_SCAN_STR_BIN_THR___S 16 +#define PHYA_RXTD_DET0_SPECTRAL_SCAN2_L__DET0_SPECTRAL_SCAN_NB_TONE_THR___M 0x0000FF00 +#define PHYA_RXTD_DET0_SPECTRAL_SCAN2_L__DET0_SPECTRAL_SCAN_NB_TONE_THR___S 8 +#define PHYA_RXTD_DET0_SPECTRAL_SCAN2_L__DET0_SPECTRAL_SCAN_RSSI_THR___M 0x000000FF +#define PHYA_RXTD_DET0_SPECTRAL_SCAN2_L__DET0_SPECTRAL_SCAN_RSSI_THR___S 0 +#define PHYA_RXTD_DET0_SPECTRAL_SCAN2_L___M 0x03FFFFFF +#define PHYA_RXTD_DET0_SPECTRAL_SCAN2_L___S 0 + +#define PHYA_RXTD_DET0_SPECTRAL_SCAN2_U (0x003A059C) +#define PHYA_RXTD_DET0_SPECTRAL_SCAN2_U___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_SPECTRAL_SCAN2_U___POR 0x0000000A +#define PHYA_RXTD_DET0_SPECTRAL_SCAN2_U__DET0_SPECTRAL_SCAN_RPT_DELAY___POR 0x00A +#define PHYA_RXTD_DET0_SPECTRAL_SCAN2_U__DET0_SPECTRAL_SCAN_RPT_DELAY___M 0x000003FF +#define PHYA_RXTD_DET0_SPECTRAL_SCAN2_U__DET0_SPECTRAL_SCAN_RPT_DELAY___S 0 +#define PHYA_RXTD_DET0_SPECTRAL_SCAN2_U___M 0x000003FF +#define PHYA_RXTD_DET0_SPECTRAL_SCAN2_U___S 0 + +#define PHYA_RXTD_DET0_RADAR_START_0_L (0x003A05A0) +#define PHYA_RXTD_DET0_RADAR_START_0_L___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_RADAR_START_0_L___POR 0x00000000 +#define PHYA_RXTD_DET0_RADAR_START_0_L__DET0_RTT_START___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_START_0_L__DET0_SPECTRAL_SCAN_ABORT___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_START_0_L__DET0_SPECTRAL_SCAN_START___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_START_0_L__DET0_RADAR_ABORT___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_START_0_L__DET0_RTT_START___M 0x01000000 +#define PHYA_RXTD_DET0_RADAR_START_0_L__DET0_RTT_START___S 24 +#define PHYA_RXTD_DET0_RADAR_START_0_L__DET0_SPECTRAL_SCAN_ABORT___M 0x00010000 +#define PHYA_RXTD_DET0_RADAR_START_0_L__DET0_SPECTRAL_SCAN_ABORT___S 16 +#define PHYA_RXTD_DET0_RADAR_START_0_L__DET0_SPECTRAL_SCAN_START___M 0x00000100 +#define PHYA_RXTD_DET0_RADAR_START_0_L__DET0_SPECTRAL_SCAN_START___S 8 +#define PHYA_RXTD_DET0_RADAR_START_0_L__DET0_RADAR_ABORT___M 0x00000001 +#define PHYA_RXTD_DET0_RADAR_START_0_L__DET0_RADAR_ABORT___S 0 +#define PHYA_RXTD_DET0_RADAR_START_0_L___M 0x01010101 +#define PHYA_RXTD_DET0_RADAR_START_0_L___S 0 + +#define PHYA_RXTD_DET0_RADAR_START_0_U (0x003A05A4) +#define PHYA_RXTD_DET0_RADAR_START_0_U___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_RADAR_START_0_U___POR 0x00000000 +#define PHYA_RXTD_DET0_RADAR_START_0_U__DET0_FFT_ABORT___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_START_0_U__DET0_FFT_START___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_START_0_U__DET0_FFT_BUF_START___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_START_0_U__DET0_RTT_ABORT___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_START_0_U__DET0_FFT_ABORT___M 0x01000000 +#define PHYA_RXTD_DET0_RADAR_START_0_U__DET0_FFT_ABORT___S 24 +#define PHYA_RXTD_DET0_RADAR_START_0_U__DET0_FFT_START___M 0x00010000 +#define PHYA_RXTD_DET0_RADAR_START_0_U__DET0_FFT_START___S 16 +#define PHYA_RXTD_DET0_RADAR_START_0_U__DET0_FFT_BUF_START___M 0x00000100 +#define PHYA_RXTD_DET0_RADAR_START_0_U__DET0_FFT_BUF_START___S 8 +#define PHYA_RXTD_DET0_RADAR_START_0_U__DET0_RTT_ABORT___M 0x00000001 +#define PHYA_RXTD_DET0_RADAR_START_0_U__DET0_RTT_ABORT___S 0 +#define PHYA_RXTD_DET0_RADAR_START_0_U___M 0x01010101 +#define PHYA_RXTD_DET0_RADAR_START_0_U___S 0 + +#define PHYA_RXTD_DET0_RADAR_START_1_L (0x003A05A8) +#define PHYA_RXTD_DET0_RADAR_START_1_L___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_RADAR_START_1_L___POR 0x00000000 +#define PHYA_RXTD_DET0_RADAR_START_1_L__DET0_RTT_ENGINE_START___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_START_1_L__DET0_RTT_ENGINE_START___M 0x00000001 +#define PHYA_RXTD_DET0_RADAR_START_1_L__DET0_RTT_ENGINE_START___S 0 +#define PHYA_RXTD_DET0_RADAR_START_1_L___M 0x00000001 +#define PHYA_RXTD_DET0_RADAR_START_1_L___S 0 + +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_L (0x003A05B0) +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_L___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_L___POR 0x00000000 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_L__DET0_RADAR_DETECT_MASK___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_L__DET0_RADAR_DETECT_MASK___M 0x00000001 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_L__DET0_RADAR_DETECT_MASK___S 0 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_L___M 0x00000001 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_L___S 0 + +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_U (0x003A05B4) +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_U___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_U___POR 0x00000000 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_U__DET0_RADAR_TIMEOUT_MASK___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_U__DET0_LONG_FFT_RPT_MASK___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_U__DET0_SHORT_FFT_RPT_MASK___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_U__DET0_RADAR_DONE_MASK___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_U__DET0_RADAR_TIMEOUT_MASK___M 0x01000000 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_U__DET0_RADAR_TIMEOUT_MASK___S 24 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_U__DET0_LONG_FFT_RPT_MASK___M 0x00010000 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_U__DET0_LONG_FFT_RPT_MASK___S 16 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_U__DET0_SHORT_FFT_RPT_MASK___M 0x00000100 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_U__DET0_SHORT_FFT_RPT_MASK___S 8 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_U__DET0_RADAR_DONE_MASK___M 0x00000001 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_U__DET0_RADAR_DONE_MASK___S 0 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_U___M 0x01010101 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_0_U___S 0 + +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_1_L (0x003A05B8) +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_1_L___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_1_L___POR 0x00010000 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_1_L__DET0_FFT_DONE_MASK___POR 0x1 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_1_L__DET0_SSCAN_DONE_MASK___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_1_L__DET0_SSCAN_READY_MASK___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_1_L__DET0_FFT_DONE_MASK___M 0x00010000 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_1_L__DET0_FFT_DONE_MASK___S 16 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_1_L__DET0_SSCAN_DONE_MASK___M 0x00000100 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_1_L__DET0_SSCAN_DONE_MASK___S 8 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_1_L__DET0_SSCAN_READY_MASK___M 0x00000001 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_1_L__DET0_SSCAN_READY_MASK___S 0 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_1_L___M 0x00010101 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK_1_L___S 0 + +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_L (0x003A05C0) +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_L___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_L___POR 0x00000000 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_L__DET0_RADAR_DETECT_MASK2___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_L__DET0_RADAR_DETECT_MASK2___M 0x00000001 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_L__DET0_RADAR_DETECT_MASK2___S 0 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_L___M 0x00000001 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_L___S 0 + +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_U (0x003A05C4) +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_U___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_U___POR 0x00000000 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_U__DET0_RADAR_TIMEOUT_MASK2___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_U__DET0_LONG_FFT_RPT_MASK2___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_U__DET0_SHORT_FFT_RPT_MASK2___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_U__DET0_RADAR_DONE_MASK2___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_U__DET0_RADAR_TIMEOUT_MASK2___M 0x01000000 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_U__DET0_RADAR_TIMEOUT_MASK2___S 24 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_U__DET0_LONG_FFT_RPT_MASK2___M 0x00010000 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_U__DET0_LONG_FFT_RPT_MASK2___S 16 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_U__DET0_SHORT_FFT_RPT_MASK2___M 0x00000100 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_U__DET0_SHORT_FFT_RPT_MASK2___S 8 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_U__DET0_RADAR_DONE_MASK2___M 0x00000001 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_U__DET0_RADAR_DONE_MASK2___S 0 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_U___M 0x01010101 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_0_U___S 0 + +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_1_L (0x003A05C8) +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_1_L___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_1_L___POR 0x00010000 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_1_L__DET0_FFT_DONE_MASK2___POR 0x1 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_1_L__DET0_SSCAN_DONE_MASK2___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_1_L__DET0_SSCAN_READY_MASK2___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_1_L__DET0_FFT_DONE_MASK2___M 0x00010000 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_1_L__DET0_FFT_DONE_MASK2___S 16 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_1_L__DET0_SSCAN_DONE_MASK2___M 0x00000100 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_1_L__DET0_SSCAN_DONE_MASK2___S 8 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_1_L__DET0_SSCAN_READY_MASK2___M 0x00000001 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_1_L__DET0_SSCAN_READY_MASK2___S 0 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_1_L___M 0x00010101 +#define PHYA_RXTD_DET0_RADAR_EVENT_MASK2_1_L___S 0 + +#define PHYA_RXTD_DET0_RTT_CONFIG_0_L (0x003A05D0) +#define PHYA_RXTD_DET0_RTT_CONFIG_0_L___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_RTT_CONFIG_0_L___POR 0x09140001 +#define PHYA_RXTD_DET0_RTT_CONFIG_0_L__DET0_RTT_DET_THR___POR 0x09 +#define PHYA_RXTD_DET0_RTT_CONFIG_0_L__DET0_RTT_SRCH_WINDOW___POR 0x14 +#define PHYA_RXTD_DET0_RTT_CONFIG_0_L__DET0_RTT_LTF_DEROT___POR 0x00 +#define PHYA_RXTD_DET0_RTT_CONFIG_0_L__DET0_RTT_DO_ADAPT_SCALING___POR 0x1 +#define PHYA_RXTD_DET0_RTT_CONFIG_0_L__DET0_RTT_DET_THR___M 0x1F000000 +#define PHYA_RXTD_DET0_RTT_CONFIG_0_L__DET0_RTT_DET_THR___S 24 +#define PHYA_RXTD_DET0_RTT_CONFIG_0_L__DET0_RTT_SRCH_WINDOW___M 0x00FF0000 +#define PHYA_RXTD_DET0_RTT_CONFIG_0_L__DET0_RTT_SRCH_WINDOW___S 16 +#define PHYA_RXTD_DET0_RTT_CONFIG_0_L__DET0_RTT_LTF_DEROT___M 0x0000FF00 +#define PHYA_RXTD_DET0_RTT_CONFIG_0_L__DET0_RTT_LTF_DEROT___S 8 +#define PHYA_RXTD_DET0_RTT_CONFIG_0_L__DET0_RTT_DO_ADAPT_SCALING___M 0x00000001 +#define PHYA_RXTD_DET0_RTT_CONFIG_0_L__DET0_RTT_DO_ADAPT_SCALING___S 0 +#define PHYA_RXTD_DET0_RTT_CONFIG_0_L___M 0x1FFFFF01 +#define PHYA_RXTD_DET0_RTT_CONFIG_0_L___S 0 + +#define PHYA_RXTD_DET0_RTT_CONFIG_0_U (0x003A05D4) +#define PHYA_RXTD_DET0_RTT_CONFIG_0_U___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_RTT_CONFIG_0_U___POR 0x00000000 +#define PHYA_RXTD_DET0_RTT_CONFIG_0_U__DET0_RTT_DO_ADAPT_THR___POR 0x0 +#define PHYA_RXTD_DET0_RTT_CONFIG_0_U__DET0_RTT_DO_FAC_INTERP___POR 0x0 +#define PHYA_RXTD_DET0_RTT_CONFIG_0_U__DET0_RTT_DET_THR_RSSI_THR___POR 0x00 +#define PHYA_RXTD_DET0_RTT_CONFIG_0_U__DET0_RTT_DET_THR_LOW___POR 0x00 +#define PHYA_RXTD_DET0_RTT_CONFIG_0_U__DET0_RTT_DO_ADAPT_THR___M 0x01000000 +#define PHYA_RXTD_DET0_RTT_CONFIG_0_U__DET0_RTT_DO_ADAPT_THR___S 24 +#define PHYA_RXTD_DET0_RTT_CONFIG_0_U__DET0_RTT_DO_FAC_INTERP___M 0x00010000 +#define PHYA_RXTD_DET0_RTT_CONFIG_0_U__DET0_RTT_DO_FAC_INTERP___S 16 +#define PHYA_RXTD_DET0_RTT_CONFIG_0_U__DET0_RTT_DET_THR_RSSI_THR___M 0x0000FF00 +#define PHYA_RXTD_DET0_RTT_CONFIG_0_U__DET0_RTT_DET_THR_RSSI_THR___S 8 +#define PHYA_RXTD_DET0_RTT_CONFIG_0_U__DET0_RTT_DET_THR_LOW___M 0x0000001F +#define PHYA_RXTD_DET0_RTT_CONFIG_0_U__DET0_RTT_DET_THR_LOW___S 0 +#define PHYA_RXTD_DET0_RTT_CONFIG_0_U___M 0x0101FF1F +#define PHYA_RXTD_DET0_RTT_CONFIG_0_U___S 0 + +#define PHYA_RXTD_DET0_RTT_CONFIG_1_L (0x003A05D8) +#define PHYA_RXTD_DET0_RTT_CONFIG_1_L___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_RTT_CONFIG_1_L___POR 0x00000019 +#define PHYA_RXTD_DET0_RTT_CONFIG_1_L__DET0_RTT_SPARES___POR 0x00 +#define PHYA_RXTD_DET0_RTT_CONFIG_1_L__DET0_RTT_USE_LSIG_4TONES___POR 0x0 +#define PHYA_RXTD_DET0_RTT_CONFIG_1_L__DET0_RTT_DO_CHAN_SPREAD_EST___POR 0x0 +#define PHYA_RXTD_DET0_RTT_CONFIG_1_L__DET0_RTT_ADAPT_THR_SCALING___POR 0x19 +#define PHYA_RXTD_DET0_RTT_CONFIG_1_L__DET0_RTT_SPARES___M 0xFF000000 +#define PHYA_RXTD_DET0_RTT_CONFIG_1_L__DET0_RTT_SPARES___S 24 +#define PHYA_RXTD_DET0_RTT_CONFIG_1_L__DET0_RTT_USE_LSIG_4TONES___M 0x00010000 +#define PHYA_RXTD_DET0_RTT_CONFIG_1_L__DET0_RTT_USE_LSIG_4TONES___S 16 +#define PHYA_RXTD_DET0_RTT_CONFIG_1_L__DET0_RTT_DO_CHAN_SPREAD_EST___M 0x00000100 +#define PHYA_RXTD_DET0_RTT_CONFIG_1_L__DET0_RTT_DO_CHAN_SPREAD_EST___S 8 +#define PHYA_RXTD_DET0_RTT_CONFIG_1_L__DET0_RTT_ADAPT_THR_SCALING___M 0x0000003F +#define PHYA_RXTD_DET0_RTT_CONFIG_1_L__DET0_RTT_ADAPT_THR_SCALING___S 0 +#define PHYA_RXTD_DET0_RTT_CONFIG_1_L___M 0xFF01013F +#define PHYA_RXTD_DET0_RTT_CONFIG_1_L___S 0 + +#define PHYA_RXTD_DET0_RXTD_SPARE_L (0x003A05E0) +#define PHYA_RXTD_DET0_RXTD_SPARE_L___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_RXTD_SPARE_L___POR 0x00000000 +#define PHYA_RXTD_DET0_RXTD_SPARE_L__DET0_RXTD_SPARE___POR 0x00000000 +#define PHYA_RXTD_DET0_RXTD_SPARE_L__DET0_RXTD_SPARE___M 0xFFFFFFFF +#define PHYA_RXTD_DET0_RXTD_SPARE_L__DET0_RXTD_SPARE___S 0 +#define PHYA_RXTD_DET0_RXTD_SPARE_L___M 0xFFFFFFFF +#define PHYA_RXTD_DET0_RXTD_SPARE_L___S 0 + +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_L (0x003A05E8) +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_L___RWC QCSR_REG_RO +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_L___POR 0x00000000 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_L__DET0_RADAR_TIMESTAMP___POR 0x00000000 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_L__DET0_RADAR_TIMESTAMP___M 0xFFFFFFFF +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_L__DET0_RADAR_TIMESTAMP___S 0 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_L___M 0xFFFFFFFF +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_L___S 0 + +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_U (0x003A05EC) +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_U___RWC QCSR_REG_RO +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_U___POR 0x00000000 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_U__DET0_RADAR_HDR_SIG___POR 0x00 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_U__DET0_RADAR_HDR_TAG___POR 0x00 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_U__DET0_RADAR_HDR_LENGTH___POR 0x0000 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_U__DET0_RADAR_HDR_SIG___M 0xFF000000 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_U__DET0_RADAR_HDR_SIG___S 24 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_U__DET0_RADAR_HDR_TAG___M 0x00FF0000 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_U__DET0_RADAR_HDR_TAG___S 16 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_U__DET0_RADAR_HDR_LENGTH___M 0x0000FFFF +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_U__DET0_RADAR_HDR_LENGTH___S 0 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_U___M 0xFFFFFFFF +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS1_U___S 0 + +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L (0x003A05F0) +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L___RWC QCSR_REG_RO +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L___POR 0x00000000 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L__DET0_PULSE_RSSI___POR 0x00 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L__DET0_FALSE_RADAR___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L__DET0_RADAR_CHECK___POR 0x0000 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L__DET0_RADAR_FFT_NUM___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L__DET0_RADAR_DETECTOR_ID___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L__DET0_PULSE_RSSI___M 0x3FC00000 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L__DET0_PULSE_RSSI___S 22 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L__DET0_FALSE_RADAR___M 0x00200000 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L__DET0_FALSE_RADAR___S 21 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L__DET0_RADAR_CHECK___M 0x001FFFE0 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L__DET0_RADAR_CHECK___S 5 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L__DET0_RADAR_FFT_NUM___M 0x0000001C +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L__DET0_RADAR_FFT_NUM___S 2 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L__DET0_RADAR_DETECTOR_ID___M 0x00000003 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L__DET0_RADAR_DETECTOR_ID___S 0 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L___M 0x3FFFFFFF +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_L___S 0 + +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_U (0x003A05F4) +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_U___RWC QCSR_REG_RO +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_U___POR 0x00000000 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_U__DET0_AGC_EVENT___POR 0x00 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_U__DET0_AGC_EVENT___M 0x0000003F +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_U__DET0_AGC_EVENT___S 0 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_U___M 0x0000003F +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS2_U___S 0 + +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L (0x003A05F8) +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L___RWC QCSR_REG_RO +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L___POR 0x00000000 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_PULSE_IS_CHIRP___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_IS_MAX_PULSE_WIDTH___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_AGC_TOTAL_GAIN___POR 0x000 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_PULSE_DELTA_DIFF___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_PULSE_DELTA_PEAK___POR 0x00 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_PULSE_SIDX___POR 0x000 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_PULSE_IS_CHIRP___M 0x80000000 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_PULSE_IS_CHIRP___S 31 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_IS_MAX_PULSE_WIDTH___M 0x40000000 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_IS_MAX_PULSE_WIDTH___S 30 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_AGC_TOTAL_GAIN___M 0x3FF00000 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_AGC_TOTAL_GAIN___S 20 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_PULSE_DELTA_DIFF___M 0x000F0000 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_PULSE_DELTA_DIFF___S 16 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_PULSE_DELTA_PEAK___M 0x0000FC00 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_PULSE_DELTA_PEAK___S 10 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_PULSE_SIDX___M 0x000003FF +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L__DET0_PULSE_SIDX___S 0 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L___M 0xFFFFFFFF +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_L___S 0 + +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_U (0x003A05FC) +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_U___RWC QCSR_REG_RO +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_U___POR 0x00000000 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_U__DET0_RADAR_SUBCHAN_MASK___POR 0x0000 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_U__DET0_PULSE_DURATION___POR 0x000 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_U__DET0_RADAR_SUBCHAN_MASK___M 0x03FFFC00 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_U__DET0_RADAR_SUBCHAN_MASK___S 10 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_U__DET0_PULSE_DURATION___M 0x000003FF +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_U__DET0_PULSE_DURATION___S 0 +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_U___M 0x03FFFFFF +#define PHYA_RXTD_DET0_RADAR_PULSE_RESULTS3_U___S 0 + +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_L (0x003A0600) +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_L___RWC QCSR_REG_RO +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_L___POR 0x00000000 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_L__DET0_SSCAN_TIMESTAMP___POR 0x00000000 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_L__DET0_SSCAN_TIMESTAMP___M 0xFFFFFFFF +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_L__DET0_SSCAN_TIMESTAMP___S 0 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_L___M 0xFFFFFFFF +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_L___S 0 + +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_U (0x003A0604) +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_U___RWC QCSR_REG_RO +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_U___POR 0x00000000 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_U__DET0_SSCAN_HDR_SIG___POR 0x00 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_U__DET0_SSCAN_HDR_TAG___POR 0x00 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_U__DET0_SSCAN_HDR_LENGTH___POR 0x0000 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_U__DET0_SSCAN_HDR_SIG___M 0xFF000000 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_U__DET0_SSCAN_HDR_SIG___S 24 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_U__DET0_SSCAN_HDR_TAG___M 0x00FF0000 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_U__DET0_SSCAN_HDR_TAG___S 16 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_U__DET0_SSCAN_HDR_LENGTH___M 0x0000FFFF +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_U__DET0_SSCAN_HDR_LENGTH___S 0 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_U___M 0xFFFFFFFF +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS1_U___S 0 + +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L (0x003A0608) +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L___RWC QCSR_REG_RO +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L___POR 0x00000000 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_SSCAN_PRI80___POR 0x0 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_SSCAN_DETECTOR_ID___POR 0x0 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_FALSE_SSCAN___POR 0x0 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_INBAND_PWR_DB___POR 0x000 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_RECENT_RFSAT___POR 0x0 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_SSCAN_GIDX___POR 0x00 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_SSCAN_OB_FLAG___POR 0x0 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_SSCAN_AGC_TOTAL_GAIN___POR 0x00 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_SSCAN_PRI80___M 0x80000000 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_SSCAN_PRI80___S 31 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_SSCAN_DETECTOR_ID___M 0x60000000 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_SSCAN_DETECTOR_ID___S 29 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_FALSE_SSCAN___M 0x10000000 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_FALSE_SSCAN___S 28 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_INBAND_PWR_DB___M 0x0FFC0000 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_INBAND_PWR_DB___S 18 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_RECENT_RFSAT___M 0x00020000 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_RECENT_RFSAT___S 17 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_SSCAN_GIDX___M 0x0001FE00 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_SSCAN_GIDX___S 9 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_SSCAN_OB_FLAG___M 0x00000100 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_SSCAN_OB_FLAG___S 8 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_SSCAN_AGC_TOTAL_GAIN___M 0x000000FF +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L__DET0_SSCAN_AGC_TOTAL_GAIN___S 0 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L___M 0xFFFFFFFF +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS2_L___S 0 + +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_L (0x003A0610) +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_L___RWC QCSR_REG_RO +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_L___POR 0x00000000 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_L__DET0_SSCAN_PEAK_MAG___POR 0x000 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_L__DET0_SSCAN_PEAK_SIDX___POR 0x000 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_L__DET0_SSCAN_PEAK_MAG___M 0x003FF000 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_L__DET0_SSCAN_PEAK_MAG___S 12 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_L__DET0_SSCAN_PEAK_SIDX___M 0x00000FFF +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_L__DET0_SSCAN_PEAK_SIDX___S 0 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_L___M 0x003FFFFF +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_L___S 0 + +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_U (0x003A0614) +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_U___RWC QCSR_REG_RO +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_U___POR 0x00000000 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_U__DET0_SSCAN_GAINCHANGE___POR 0x0 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_U__DET0_SSCAN_NB_MASK___POR 0x0000 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_U__DET0_SSCAN_GAINCHANGE___M 0x00010000 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_U__DET0_SSCAN_GAINCHANGE___S 16 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_U__DET0_SSCAN_NB_MASK___M 0x0000FFFF +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_U__DET0_SSCAN_NB_MASK___S 0 +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_U___M 0x0001FFFF +#define PHYA_RXTD_DET0_SSCAN_PULSE_RESULTS3_U___S 0 + +#define PHYA_RXTD_DET0_RADAR_EVENT_L (0x003A0618) +#define PHYA_RXTD_DET0_RADAR_EVENT_L___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_RADAR_EVENT_L___POR 0x00000000 +#define PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_FFT_DONE___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_SSCAN_DONE___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_SSCAN_READY___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_RADAR_TIMEOUT___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_LONG_FFT_RPT___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_SHORT_FFT_RPT___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_RADAR_DONE___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_RADAR_DETECT___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_FFT_DONE___M 0x00000080 +#define PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_FFT_DONE___S 7 +#define PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_SSCAN_DONE___M 0x00000040 +#define PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_SSCAN_DONE___S 6 +#define PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_SSCAN_READY___M 0x00000020 +#define PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_SSCAN_READY___S 5 +#define PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_RADAR_TIMEOUT___M 0x00000010 +#define PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_RADAR_TIMEOUT___S 4 +#define PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_LONG_FFT_RPT___M 0x00000008 +#define PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_LONG_FFT_RPT___S 3 +#define PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_SHORT_FFT_RPT___M 0x00000004 +#define PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_SHORT_FFT_RPT___S 2 +#define PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_RADAR_DONE___M 0x00000002 +#define PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_RADAR_DONE___S 1 +#define PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_RADAR_DETECT___M 0x00000001 +#define PHYA_RXTD_DET0_RADAR_EVENT_L__DET0_RADAR_DETECT___S 0 +#define PHYA_RXTD_DET0_RADAR_EVENT_L___M 0x000000FF +#define PHYA_RXTD_DET0_RADAR_EVENT_L___S 0 + +#define PHYA_RXTD_DET0_RADAR_EVENT2_L (0x003A0620) +#define PHYA_RXTD_DET0_RADAR_EVENT2_L___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_RADAR_EVENT2_L___POR 0x00000000 +#define PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_FFT_DONE2___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_SSCAN_DONE2___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_SSCAN_READY2___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_RADAR_TIMEOUT2___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_LONG_FFT_RPT2___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_SHORT_FFT_RPT2___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_RADAR_DONE2___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_RADAR_DETECT2___POR 0x0 +#define PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_FFT_DONE2___M 0x00000080 +#define PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_FFT_DONE2___S 7 +#define PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_SSCAN_DONE2___M 0x00000040 +#define PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_SSCAN_DONE2___S 6 +#define PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_SSCAN_READY2___M 0x00000020 +#define PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_SSCAN_READY2___S 5 +#define PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_RADAR_TIMEOUT2___M 0x00000010 +#define PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_RADAR_TIMEOUT2___S 4 +#define PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_LONG_FFT_RPT2___M 0x00000008 +#define PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_LONG_FFT_RPT2___S 3 +#define PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_SHORT_FFT_RPT2___M 0x00000004 +#define PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_SHORT_FFT_RPT2___S 2 +#define PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_RADAR_DONE2___M 0x00000002 +#define PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_RADAR_DONE2___S 1 +#define PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_RADAR_DETECT2___M 0x00000001 +#define PHYA_RXTD_DET0_RADAR_EVENT2_L__DET0_RADAR_DETECT2___S 0 +#define PHYA_RXTD_DET0_RADAR_EVENT2_L___M 0x000000FF +#define PHYA_RXTD_DET0_RADAR_EVENT2_L___S 0 + +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_L (0x003A0628) +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_L___RWC QCSR_REG_RO +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_L___POR 0x00000000 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_L__DET0_FFT_TIMESTAMP___POR 0x00000000 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_L__DET0_FFT_TIMESTAMP___M 0xFFFFFFFF +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_L__DET0_FFT_TIMESTAMP___S 0 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_L___M 0xFFFFFFFF +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_L___S 0 + +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_U (0x003A062C) +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_U___RWC QCSR_REG_RO +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_U___POR 0x00000000 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_U__DET0_FFT_HDR_SIG___POR 0x00 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_U__DET0_FFT_HDR_TAG___POR 0x00 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_U__DET0_FFT_HDR_LENGTH___POR 0x0000 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_U__DET0_FFT_HDR_SIG___M 0xFF000000 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_U__DET0_FFT_HDR_SIG___S 24 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_U__DET0_FFT_HDR_TAG___M 0x00FF0000 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_U__DET0_FFT_HDR_TAG___S 16 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_U__DET0_FFT_HDR_LENGTH___M 0x0000FFFF +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_U__DET0_FFT_HDR_LENGTH___S 0 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_U___M 0xFFFFFFFF +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS1_U___S 0 + +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_L (0x003A0630) +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_L___RWC QCSR_REG_RO +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_L___POR 0x00000000 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_L__DET0_FFT_PEAK_SIDX___POR 0x000 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_L__DET0_FFT_RADAR_CHECK___POR 0x0000 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_L__DET0_FFT_NUM___POR 0x0 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_L__DET0_FFT_DETECTOR_ID___POR 0x0 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_L__DET0_FFT_PEAK_SIDX___M 0x3FF80000 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_L__DET0_FFT_PEAK_SIDX___S 19 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_L__DET0_FFT_RADAR_CHECK___M 0x0007FFE0 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_L__DET0_FFT_RADAR_CHECK___S 5 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_L__DET0_FFT_NUM___M 0x0000001C +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_L__DET0_FFT_NUM___S 2 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_L__DET0_FFT_DETECTOR_ID___M 0x00000003 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_L__DET0_FFT_DETECTOR_ID___S 0 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_L___M 0x3FFFFFFF +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_L___S 0 + +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_U (0x003A0634) +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_U___RWC QCSR_REG_RO +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_U___POR 0x00000000 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_U__DET0_FFT_TOTAL_GAIN_DB___POR 0x00 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_U__DET0_FFT_BASE_PWR_DB___POR 0x000 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_U__DET0_FFT_CHN_IDX___POR 0x0 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_U__DET0_FFT_TOTAL_GAIN_DB___M 0x000FF000 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_U__DET0_FFT_TOTAL_GAIN_DB___S 12 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_U__DET0_FFT_BASE_PWR_DB___M 0x00000FF8 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_U__DET0_FFT_BASE_PWR_DB___S 3 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_U__DET0_FFT_CHN_IDX___M 0x00000007 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_U__DET0_FFT_CHN_IDX___S 0 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_U___M 0x000FFFFF +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS2_U___S 0 + +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS3_L (0x003A0638) +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS3_L___RWC QCSR_REG_RO +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS3_L___POR 0x00000000 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS3_L__DET0_FFT_RELPWR_DB___POR 0x00 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS3_L__DET0_FFT_AVGPWR_DB___POR 0x00 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS3_L__DET0_FFT_PEAK_MAG___POR 0x000 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS3_L__DET0_FFT_NUM_STR_BINS_IB___POR 0x00 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS3_L__DET0_FFT_RELPWR_DB___M 0xFE000000 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS3_L__DET0_FFT_RELPWR_DB___S 25 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS3_L__DET0_FFT_AVGPWR_DB___M 0x01FC0000 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS3_L__DET0_FFT_AVGPWR_DB___S 18 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS3_L__DET0_FFT_PEAK_MAG___M 0x0003FF00 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS3_L__DET0_FFT_PEAK_MAG___S 8 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS3_L__DET0_FFT_NUM_STR_BINS_IB___M 0x000000FF +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS3_L__DET0_FFT_NUM_STR_BINS_IB___S 0 +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS3_L___M 0xFFFFFFFF +#define PHYA_RXTD_DET0_SRCH_FFT_RESULTS3_L___S 0 + +#define PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_L_n(n) (0x003A0640+0x8*(n)) +#define PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_L_n_nMIN 0 +#define PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_L_n_nMAX 0 +#define PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_L_n_ELEM 1 +#define PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_L_n___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_L_n___POR 0x00000000 +#define PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_L_n__DET0_0_FFT_OUT_MEM___POR 0x00000000 +#define PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_L_n__DET0_0_FFT_OUT_MEM___M 0xFFFFFFFF +#define PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_L_n__DET0_0_FFT_OUT_MEM___S 0 +#define PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_L_n___M 0xFFFFFFFF +#define PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_L_n___S 0 +#define PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_L_0 (0x003A0640) +#define PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_L_0___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_L_0__DET0_0_FFT_OUT_MEM___M 0xFFFFFFFF +#define PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_L_0__DET0_0_FFT_OUT_MEM___S 0 + +#define PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_U_n(n) (0x003A0644+0x8*(n)) +#define PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_U_n_nMIN 0 +#define PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_U_n_nMAX 0 +#define PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_U_n_ELEM 1 +#define PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_U_n___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_U_n___POR 0x00000000 +#define PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_U_n__DET0_1_FFT_OUT_MEM___POR 0x00000000 +#define PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_U_n__DET0_1_FFT_OUT_MEM___M 0xFFFFFFFF +#define PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_U_n__DET0_1_FFT_OUT_MEM___S 0 +#define PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_U_n___M 0xFFFFFFFF +#define PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_U_n___S 0 +#define PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_U_0 (0x003A0644) +#define PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_U_0___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_U_0__DET0_1_FFT_OUT_MEM___M 0xFFFFFFFF +#define PHYA_RXTD_DET0_SRCH_FFT_OUT_MEM_U_0__DET0_1_FFT_OUT_MEM___S 0 + +#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_L (0x003A1640) +#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_L___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_L___POR 0x00000000 +#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_L__DET0_RADAR_DETECT_COUNT___POR 0x0000 +#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_L__DET0_RADAR_DONE_COUNT___POR 0x0000 +#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_L__DET0_RADAR_DETECT_COUNT___M 0xFFFF0000 +#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_L__DET0_RADAR_DETECT_COUNT___S 16 +#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_L__DET0_RADAR_DONE_COUNT___M 0x0000FFFF +#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_L__DET0_RADAR_DONE_COUNT___S 0 +#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_L___M 0xFFFFFFFF +#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_L___S 0 + +#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_U (0x003A1644) +#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_U___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_U___POR 0x00000000 +#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_U__DET0_LONG_FFT_RPT_COUNT___POR 0x0000 +#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_U__DET0_SHORT_FFT_RPT_COUNT___POR 0x0000 +#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_U__DET0_LONG_FFT_RPT_COUNT___M 0xFFFF0000 +#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_U__DET0_LONG_FFT_RPT_COUNT___S 16 +#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_U__DET0_SHORT_FFT_RPT_COUNT___M 0x0000FFFF +#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_U__DET0_SHORT_FFT_RPT_COUNT___S 0 +#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_U___M 0xFFFFFFFF +#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_0_U___S 0 + +#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_1_L (0x003A1648) +#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_1_L___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_1_L___POR 0x00000000 +#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_1_L__DET0_SSCAN_DONE_COUNT___POR 0x0000 +#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_1_L__DET0_SSCAN_READY_COUNT___POR 0x0000 +#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_1_L__DET0_SSCAN_DONE_COUNT___M 0xFFFF0000 +#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_1_L__DET0_SSCAN_DONE_COUNT___S 16 +#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_1_L__DET0_SSCAN_READY_COUNT___M 0x0000FFFF +#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_1_L__DET0_SSCAN_READY_COUNT___S 0 +#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_1_L___M 0xFFFFFFFF +#define PHYA_RXTD_DET0_EVENT_STAT_COUNT_1_L___S 0 + +#define PHYA_RXTD_DET0_SRCH_FFT_MEM_L_n(n) (0x003A1650+0x8*(n)) +#define PHYA_RXTD_DET0_SRCH_FFT_MEM_L_n_nMIN 0 +#define PHYA_RXTD_DET0_SRCH_FFT_MEM_L_n_nMAX 0 +#define PHYA_RXTD_DET0_SRCH_FFT_MEM_L_n_ELEM 1 +#define PHYA_RXTD_DET0_SRCH_FFT_MEM_L_n___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_SRCH_FFT_MEM_L_n___POR 0x00000000 +#define PHYA_RXTD_DET0_SRCH_FFT_MEM_L_n__DET0_0_FFT_MEM___POR 0x00000000 +#define PHYA_RXTD_DET0_SRCH_FFT_MEM_L_n__DET0_0_FFT_MEM___M 0xFFFFFFFF +#define PHYA_RXTD_DET0_SRCH_FFT_MEM_L_n__DET0_0_FFT_MEM___S 0 +#define PHYA_RXTD_DET0_SRCH_FFT_MEM_L_n___M 0xFFFFFFFF +#define PHYA_RXTD_DET0_SRCH_FFT_MEM_L_n___S 0 +#define PHYA_RXTD_DET0_SRCH_FFT_MEM_L_0 (0x003A1650) +#define PHYA_RXTD_DET0_SRCH_FFT_MEM_L_0___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_SRCH_FFT_MEM_L_0__DET0_0_FFT_MEM___M 0xFFFFFFFF +#define PHYA_RXTD_DET0_SRCH_FFT_MEM_L_0__DET0_0_FFT_MEM___S 0 + +#define PHYA_RXTD_DET0_SRCH_FFT_MEM_U_n(n) (0x003A1654+0x8*(n)) +#define PHYA_RXTD_DET0_SRCH_FFT_MEM_U_n_nMIN 0 +#define PHYA_RXTD_DET0_SRCH_FFT_MEM_U_n_nMAX 0 +#define PHYA_RXTD_DET0_SRCH_FFT_MEM_U_n_ELEM 1 +#define PHYA_RXTD_DET0_SRCH_FFT_MEM_U_n___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_SRCH_FFT_MEM_U_n___POR 0x00000000 +#define PHYA_RXTD_DET0_SRCH_FFT_MEM_U_n__DET0_1_FFT_MEM___POR 0x00000000 +#define PHYA_RXTD_DET0_SRCH_FFT_MEM_U_n__DET0_1_FFT_MEM___M 0xFFFFFFFF +#define PHYA_RXTD_DET0_SRCH_FFT_MEM_U_n__DET0_1_FFT_MEM___S 0 +#define PHYA_RXTD_DET0_SRCH_FFT_MEM_U_n___M 0xFFFFFFFF +#define PHYA_RXTD_DET0_SRCH_FFT_MEM_U_n___S 0 +#define PHYA_RXTD_DET0_SRCH_FFT_MEM_U_0 (0x003A1654) +#define PHYA_RXTD_DET0_SRCH_FFT_MEM_U_0___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_SRCH_FFT_MEM_U_0__DET0_1_FFT_MEM___M 0xFFFFFFFF +#define PHYA_RXTD_DET0_SRCH_FFT_MEM_U_0__DET0_1_FFT_MEM___S 0 + +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_L (0x003A2650) +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_L___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_L___POR 0x00000000 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_L__DET0_RTT_IS_AX___POR 0x0 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_L__DET0_RTT_PREAMBLE_TYPE___POR 0x0 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_L__DET0_RTT_SYM_TYPE___POR 0x0 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_L__DET0_RTT_INPUT_SHIFT___POR 0x0 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_L__DET0_RTT_IS_AX___M 0x01000000 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_L__DET0_RTT_IS_AX___S 24 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_L__DET0_RTT_PREAMBLE_TYPE___M 0x000F0000 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_L__DET0_RTT_PREAMBLE_TYPE___S 16 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_L__DET0_RTT_SYM_TYPE___M 0x00000100 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_L__DET0_RTT_SYM_TYPE___S 8 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_L__DET0_RTT_INPUT_SHIFT___M 0x00000007 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_L__DET0_RTT_INPUT_SHIFT___S 0 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_L___M 0x010F0107 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_L___S 0 + +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_U (0x003A2654) +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_U___RWC QCSR_REG_RW +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_U___POR 0x00000000 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_U__DET0_RTT_EN_165___POR 0x0 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_U__DET0_RTT_RSSI___POR 0x00 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_U__DET0_RTT_PKT_BW_VHT___POR 0x0 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_U__DET0_RTT_PKT_BW_LEG___POR 0x0 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_U__DET0_RTT_EN_165___M 0x01000000 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_U__DET0_RTT_EN_165___S 24 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_U__DET0_RTT_RSSI___M 0x00FF0000 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_U__DET0_RTT_RSSI___S 16 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_U__DET0_RTT_PKT_BW_VHT___M 0x00000300 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_U__DET0_RTT_PKT_BW_VHT___S 8 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_U__DET0_RTT_PKT_BW_LEG___M 0x00000003 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_U__DET0_RTT_PKT_BW_LEG___S 0 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_U___M 0x01FF0303 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_0_U___S 0 + +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_1_L (0x003A2658) +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_1_L___RWC QCSR_REG_RO +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_1_L___POR 0x00000000 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_1_L__DET0_RTT_FAC_VALID___POR 0x0 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_1_L__DET0_RTT_CHAN_DELAY_SPREAD___POR 0x00 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_1_L__DET0_RTT_FAC_VALUE___POR 0x0000 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_1_L__DET0_RTT_FAC_VALID___M 0x01000000 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_1_L__DET0_RTT_FAC_VALID___S 24 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_1_L__DET0_RTT_CHAN_DELAY_SPREAD___M 0x00FF0000 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_1_L__DET0_RTT_CHAN_DELAY_SPREAD___S 16 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_1_L__DET0_RTT_FAC_VALUE___M 0x0000FFFF +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_1_L__DET0_RTT_FAC_VALUE___S 0 +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_1_L___M 0x01FFFFFF +#define PHYA_RXTD_DET0_RTT_DYN_CONFIG_1_L___S 0 + +#define PHYA_RXTD_ASTF_CONFIG_L (0x003A2660) +#define PHYA_RXTD_ASTF_CONFIG_L___RWC QCSR_REG_RW +#define PHYA_RXTD_ASTF_CONFIG_L___POR 0x000084A8 +#define PHYA_RXTD_ASTF_CONFIG_L__ASTF_PD_WIN_LEN___POR 0x01 +#define PHYA_RXTD_ASTF_CONFIG_L__ASTF_PD_ACC_THR_LOW___POR 0x01 +#define PHYA_RXTD_ASTF_CONFIG_L__ASTF_PD_POW_THR_LOW___POR 0x05 +#define PHYA_RXTD_ASTF_CONFIG_L__ASTF_PD_THR_LOW___POR 0x4 +#define PHYA_RXTD_ASTF_CONFIG_L__ASTF_ENABLE___POR 0x0 +#define PHYA_RXTD_ASTF_CONFIG_L__ASTF_PD_WIN_LEN___M 0x000F8000 +#define PHYA_RXTD_ASTF_CONFIG_L__ASTF_PD_WIN_LEN___S 15 +#define PHYA_RXTD_ASTF_CONFIG_L__ASTF_PD_ACC_THR_LOW___M 0x00007C00 +#define PHYA_RXTD_ASTF_CONFIG_L__ASTF_PD_ACC_THR_LOW___S 10 +#define PHYA_RXTD_ASTF_CONFIG_L__ASTF_PD_POW_THR_LOW___M 0x000003E0 +#define PHYA_RXTD_ASTF_CONFIG_L__ASTF_PD_POW_THR_LOW___S 5 +#define PHYA_RXTD_ASTF_CONFIG_L__ASTF_PD_THR_LOW___M 0x0000001E +#define PHYA_RXTD_ASTF_CONFIG_L__ASTF_PD_THR_LOW___S 1 +#define PHYA_RXTD_ASTF_CONFIG_L__ASTF_ENABLE___M 0x00000001 +#define PHYA_RXTD_ASTF_CONFIG_L__ASTF_ENABLE___S 0 +#define PHYA_RXTD_ASTF_CONFIG_L___M 0x000FFFFF +#define PHYA_RXTD_ASTF_CONFIG_L___S 0 + +#define PHYA_RXTD_ABTCF_CONFIG_L (0x003A2668) +#define PHYA_RXTD_ABTCF_CONFIG_L___RWC QCSR_REG_RW +#define PHYA_RXTD_ABTCF_CONFIG_L___POR 0x00000078 +#define PHYA_RXTD_ABTCF_CONFIG_L__ABTCF_PACKET_DET_THR_LOW___POR 0x03C +#define PHYA_RXTD_ABTCF_CONFIG_L__ABTCF_ENABLE___POR 0x0 +#define PHYA_RXTD_ABTCF_CONFIG_L__ABTCF_PACKET_DET_THR_LOW___M 0x000003FE +#define PHYA_RXTD_ABTCF_CONFIG_L__ABTCF_PACKET_DET_THR_LOW___S 1 +#define PHYA_RXTD_ABTCF_CONFIG_L__ABTCF_ENABLE___M 0x00000001 +#define PHYA_RXTD_ABTCF_CONFIG_L__ABTCF_ENABLE___S 0 +#define PHYA_RXTD_ABTCF_CONFIG_L___M 0x000003FF +#define PHYA_RXTD_ABTCF_CONFIG_L___S 0 + +#define PHYA_RXTD_ABTCF_CONFIG_2_L (0x003A2670) +#define PHYA_RXTD_ABTCF_CONFIG_2_L___RWC QCSR_REG_RW +#define PHYA_RXTD_ABTCF_CONFIG_2_L___POR 0x00001103 +#define PHYA_RXTD_ABTCF_CONFIG_2_L__ABTCF_BACKOFF_LOW___POR 0x08 +#define PHYA_RXTD_ABTCF_CONFIG_2_L__ABTCF_RISING_EDGE_THR_LOW___POR 0x103 +#define PHYA_RXTD_ABTCF_CONFIG_2_L__ABTCF_BACKOFF_LOW___M 0x0001FE00 +#define PHYA_RXTD_ABTCF_CONFIG_2_L__ABTCF_BACKOFF_LOW___S 9 +#define PHYA_RXTD_ABTCF_CONFIG_2_L__ABTCF_RISING_EDGE_THR_LOW___M 0x000001FF +#define PHYA_RXTD_ABTCF_CONFIG_2_L__ABTCF_RISING_EDGE_THR_LOW___S 0 +#define PHYA_RXTD_ABTCF_CONFIG_2_L___M 0x0001FFFF +#define PHYA_RXTD_ABTCF_CONFIG_2_L___S 0 + +#define PHYA_RXTD_ECTE_CONFIG_L (0x003A2678) +#define PHYA_RXTD_ECTE_CONFIG_L___RWC QCSR_REG_RW +#define PHYA_RXTD_ECTE_CONFIG_L___POR 0x001EF780 +#define PHYA_RXTD_ECTE_CONFIG_L__ECTE_DETECT_THRESH___POR 0x3DE +#define PHYA_RXTD_ECTE_CONFIG_L__ECTE_LPF_BETA___POR 0x3C0 +#define PHYA_RXTD_ECTE_CONFIG_L__ECTE_ENABLE___POR 0x0 +#define PHYA_RXTD_ECTE_CONFIG_L__ECTE_DETECT_THRESH___M 0x001FF800 +#define PHYA_RXTD_ECTE_CONFIG_L__ECTE_DETECT_THRESH___S 11 +#define PHYA_RXTD_ECTE_CONFIG_L__ECTE_LPF_BETA___M 0x000007FE +#define PHYA_RXTD_ECTE_CONFIG_L__ECTE_LPF_BETA___S 1 +#define PHYA_RXTD_ECTE_CONFIG_L__ECTE_ENABLE___M 0x00000001 +#define PHYA_RXTD_ECTE_CONFIG_L__ECTE_ENABLE___S 0 +#define PHYA_RXTD_ECTE_CONFIG_L___M 0x001FFFFF +#define PHYA_RXTD_ECTE_CONFIG_L___S 0 + +#define PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B0 (0x003A4000) +#define PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B0___RWC QCSR_REG_RW +#define PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B0___POR 0x00000000 +#define PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B0__AGC_GAIN_COPY_FORCE_DB2___POR 0x000 +#define PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B0__AGC_GAIN_COPY_SOURCE_S___POR 0x0 +#define PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B0__AGC_GAIN_COPY_SOURCE_P___POR 0x0 +#define PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B0__AGC_GAIN_COPY_FORCE_DB2___M 0x0000FFC0 +#define PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B0__AGC_GAIN_COPY_FORCE_DB2___S 6 +#define PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B0__AGC_GAIN_COPY_SOURCE_S___M 0x00000038 +#define PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B0__AGC_GAIN_COPY_SOURCE_S___S 3 +#define PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B0__AGC_GAIN_COPY_SOURCE_P___M 0x00000007 +#define PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B0__AGC_GAIN_COPY_SOURCE_P___S 0 +#define PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B0___M 0x0000FFFF +#define PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B0___S 0 + +#define PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B1 (0x003A5000) +#define PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B1___RWC QCSR_REG_RW +#define PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B1___POR 0x00000000 +#define PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B1__AGC_GAIN_COPY_FORCE_DB2___POR 0x000 +#define PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B1__AGC_GAIN_COPY_SOURCE_S___POR 0x0 +#define PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B1__AGC_GAIN_COPY_SOURCE_P___POR 0x0 +#define PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B1__AGC_GAIN_COPY_FORCE_DB2___M 0x0000FFC0 +#define PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B1__AGC_GAIN_COPY_FORCE_DB2___S 6 +#define PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B1__AGC_GAIN_COPY_SOURCE_S___M 0x00000038 +#define PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B1__AGC_GAIN_COPY_SOURCE_S___S 3 +#define PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B1__AGC_GAIN_COPY_SOURCE_P___M 0x00000007 +#define PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B1__AGC_GAIN_COPY_SOURCE_P___S 0 +#define PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B1___M 0x0000FFFF +#define PHYA_RXTD_CHN_AGC_GAIN_COPY_SOURCE_L_B1___S 0 + +#define PHYA_RXTD_CHN_AGC_INIT_GAIN_L_B0 (0x003A4008) +#define PHYA_RXTD_CHN_AGC_INIT_GAIN_L_B0___RWC QCSR_REG_RW +#define PHYA_RXTD_CHN_AGC_INIT_GAIN_L_B0___POR 0x0000004E +#define PHYA_RXTD_CHN_AGC_INIT_GAIN_L_B0__TOTAL_GAIN_F_DB2___POR 0x04E +#define PHYA_RXTD_CHN_AGC_INIT_GAIN_L_B0__TOTAL_GAIN_F_DB2___M 0x000003FF +#define PHYA_RXTD_CHN_AGC_INIT_GAIN_L_B0__TOTAL_GAIN_F_DB2___S 0 +#define PHYA_RXTD_CHN_AGC_INIT_GAIN_L_B0___M 0x000003FF +#define PHYA_RXTD_CHN_AGC_INIT_GAIN_L_B0___S 0 + +#define PHYA_RXTD_CHN_AGC_INIT_GAIN_L_B1 (0x003A5008) +#define PHYA_RXTD_CHN_AGC_INIT_GAIN_L_B1___RWC QCSR_REG_RW +#define PHYA_RXTD_CHN_AGC_INIT_GAIN_L_B1___POR 0x0000004E +#define PHYA_RXTD_CHN_AGC_INIT_GAIN_L_B1__TOTAL_GAIN_F_DB2___POR 0x04E +#define PHYA_RXTD_CHN_AGC_INIT_GAIN_L_B1__TOTAL_GAIN_F_DB2___M 0x000003FF +#define PHYA_RXTD_CHN_AGC_INIT_GAIN_L_B1__TOTAL_GAIN_F_DB2___S 0 +#define PHYA_RXTD_CHN_AGC_INIT_GAIN_L_B1___M 0x000003FF +#define PHYA_RXTD_CHN_AGC_INIT_GAIN_L_B1___S 0 + +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_L_B0 (0x003A4010) +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_L_B0___RWC QCSR_REG_RW +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_L_B0___POR 0x00000000 +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_L_B0__SPUR1_DELTA_PHASE_PRI___POR 0x00000 +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_L_B0__SPUR1_DELTA_PHASE_PRI___M 0x000FFFFF +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_L_B0__SPUR1_DELTA_PHASE_PRI___S 0 +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_L_B0___M 0x000FFFFF +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_L_B0___S 0 + +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_L_B1 (0x003A5010) +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_L_B1___RWC QCSR_REG_RW +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_L_B1___POR 0x00000000 +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_L_B1__SPUR1_DELTA_PHASE_PRI___POR 0x00000 +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_L_B1__SPUR1_DELTA_PHASE_PRI___M 0x000FFFFF +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_L_B1__SPUR1_DELTA_PHASE_PRI___S 0 +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_L_B1___M 0x000FFFFF +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_L_B1___S 0 + +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_U_B0 (0x003A4014) +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_U_B0___RWC QCSR_REG_RW +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_U_B0___POR 0x00000000 +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_U_B0__ENABLE_SPUR_FILTER_PRI___POR 0x0 +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_U_B0__ENABLE_SPUR_FILTER_PRI___M 0x00000003 +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_U_B0__ENABLE_SPUR_FILTER_PRI___S 0 +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_U_B0___M 0x00000003 +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_U_B0___S 0 + +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_U_B1 (0x003A5014) +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_U_B1___RWC QCSR_REG_RW +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_U_B1___POR 0x00000000 +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_U_B1__ENABLE_SPUR_FILTER_PRI___POR 0x0 +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_U_B1__ENABLE_SPUR_FILTER_PRI___M 0x00000003 +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_U_B1__ENABLE_SPUR_FILTER_PRI___S 0 +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_U_B1___M 0x00000003 +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_0_U_B1___S 0 + +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_1_L_B0 (0x003A4018) +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_1_L_B0___RWC QCSR_REG_RW +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_1_L_B0___POR 0x00000000 +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_1_L_B0__SPUR2_DELTA_PHASE_PRI___POR 0x00000 +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_1_L_B0__SPUR2_DELTA_PHASE_PRI___M 0x000FFFFF +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_1_L_B0__SPUR2_DELTA_PHASE_PRI___S 0 +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_1_L_B0___M 0x000FFFFF +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_1_L_B0___S 0 + +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_1_L_B1 (0x003A5018) +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_1_L_B1___RWC QCSR_REG_RW +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_1_L_B1___POR 0x00000000 +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_1_L_B1__SPUR2_DELTA_PHASE_PRI___POR 0x00000 +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_1_L_B1__SPUR2_DELTA_PHASE_PRI___M 0x000FFFFF +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_1_L_B1__SPUR2_DELTA_PHASE_PRI___S 0 +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_1_L_B1___M 0x000FFFFF +#define PHYA_RXTD_CHN_SPUR_NOTCH_PRI_CTRL1_1_L_B1___S 0 + +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_L_B0 (0x003A4020) +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_L_B0___RWC QCSR_REG_RW +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_L_B0___POR 0x00000000 +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_L_B0__SPUR1_DELTA_PHASE_EXT___POR 0x00000 +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_L_B0__SPUR1_DELTA_PHASE_EXT___M 0x000FFFFF +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_L_B0__SPUR1_DELTA_PHASE_EXT___S 0 +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_L_B0___M 0x000FFFFF +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_L_B0___S 0 + +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_L_B1 (0x003A5020) +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_L_B1___RWC QCSR_REG_RW +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_L_B1___POR 0x00000000 +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_L_B1__SPUR1_DELTA_PHASE_EXT___POR 0x00000 +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_L_B1__SPUR1_DELTA_PHASE_EXT___M 0x000FFFFF +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_L_B1__SPUR1_DELTA_PHASE_EXT___S 0 +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_L_B1___M 0x000FFFFF +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_L_B1___S 0 + +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_U_B0 (0x003A4024) +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_U_B0___RWC QCSR_REG_RW +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_U_B0___POR 0x00000000 +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_U_B0__ENABLE_SPUR_FILTER_EXT___POR 0x0 +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_U_B0__ENABLE_SPUR_FILTER_EXT___M 0x00000003 +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_U_B0__ENABLE_SPUR_FILTER_EXT___S 0 +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_U_B0___M 0x00000003 +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_U_B0___S 0 + +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_U_B1 (0x003A5024) +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_U_B1___RWC QCSR_REG_RW +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_U_B1___POR 0x00000000 +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_U_B1__ENABLE_SPUR_FILTER_EXT___POR 0x0 +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_U_B1__ENABLE_SPUR_FILTER_EXT___M 0x00000003 +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_U_B1__ENABLE_SPUR_FILTER_EXT___S 0 +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_U_B1___M 0x00000003 +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_0_U_B1___S 0 + +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_1_L_B0 (0x003A4028) +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_1_L_B0___RWC QCSR_REG_RW +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_1_L_B0___POR 0x00000000 +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_1_L_B0__SPUR2_DELTA_PHASE_EXT___POR 0x00000 +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_1_L_B0__SPUR2_DELTA_PHASE_EXT___M 0x000FFFFF +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_1_L_B0__SPUR2_DELTA_PHASE_EXT___S 0 +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_1_L_B0___M 0x000FFFFF +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_1_L_B0___S 0 + +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_1_L_B1 (0x003A5028) +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_1_L_B1___RWC QCSR_REG_RW +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_1_L_B1___POR 0x00000000 +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_1_L_B1__SPUR2_DELTA_PHASE_EXT___POR 0x00000 +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_1_L_B1__SPUR2_DELTA_PHASE_EXT___M 0x000FFFFF +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_1_L_B1__SPUR2_DELTA_PHASE_EXT___S 0 +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_1_L_B1___M 0x000FFFFF +#define PHYA_RXTD_CHN_SPUR_NOTCH_EXT_CTRL1_1_L_B1___S 0 + +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B0 (0x003A4030) +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B0___RWC QCSR_REG_RW +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B0___POR 0x00000400 +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_SPUR1_PRI_Q___POR 0x000 +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_SPUR1_PRI_I___POR 0x400 +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_SPUR1_PRI_Q___M 0x0FFF0000 +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_SPUR1_PRI_Q___S 16 +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_SPUR1_PRI_I___M 0x00000FFF +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_SPUR1_PRI_I___S 0 +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B0___M 0x0FFF0FFF +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B0___S 0 + +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B1 (0x003A5030) +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B1___RWC QCSR_REG_RW +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B1___POR 0x00000400 +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_SPUR1_PRI_Q___POR 0x000 +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_SPUR1_PRI_I___POR 0x400 +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_SPUR1_PRI_Q___M 0x0FFF0000 +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_SPUR1_PRI_Q___S 16 +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_SPUR1_PRI_I___M 0x00000FFF +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_SPUR1_PRI_I___S 0 +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B1___M 0x0FFF0FFF +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_L_B1___S 0 + +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B0 (0x003A4034) +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B0___RWC QCSR_REG_RW +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B0___POR 0x00000400 +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_SPUR1_EXT_Q___POR 0x000 +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_SPUR1_EXT_I___POR 0x400 +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_SPUR1_EXT_Q___M 0x0FFF0000 +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_SPUR1_EXT_Q___S 16 +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_SPUR1_EXT_I___M 0x00000FFF +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_SPUR1_EXT_I___S 0 +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B0___M 0x0FFF0FFF +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B0___S 0 + +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B1 (0x003A5034) +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B1___RWC QCSR_REG_RW +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B1___POR 0x00000400 +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_SPUR1_EXT_Q___POR 0x000 +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_SPUR1_EXT_I___POR 0x400 +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_SPUR1_EXT_Q___M 0x0FFF0000 +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_SPUR1_EXT_Q___S 16 +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_SPUR1_EXT_I___M 0x00000FFF +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_SPUR1_EXT_I___S 0 +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B1___M 0x0FFF0FFF +#define PHYA_RXTD_CHN_SPUR1_NOTCH_CORR_COEFF_U_B1___S 0 + +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B0 (0x003A4038) +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B0___RWC QCSR_REG_RW +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B0___POR 0x00000400 +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_SPUR2_PRI_Q___POR 0x000 +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_SPUR2_PRI_I___POR 0x400 +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_SPUR2_PRI_Q___M 0x0FFF0000 +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_SPUR2_PRI_Q___S 16 +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_SPUR2_PRI_I___M 0x00000FFF +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_SPUR2_PRI_I___S 0 +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B0___M 0x0FFF0FFF +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B0___S 0 + +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B1 (0x003A5038) +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B1___RWC QCSR_REG_RW +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B1___POR 0x00000400 +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_SPUR2_PRI_Q___POR 0x000 +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_SPUR2_PRI_I___POR 0x400 +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_SPUR2_PRI_Q___M 0x0FFF0000 +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_SPUR2_PRI_Q___S 16 +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_SPUR2_PRI_I___M 0x00000FFF +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_SPUR2_PRI_I___S 0 +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B1___M 0x0FFF0FFF +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_L_B1___S 0 + +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B0 (0x003A403C) +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B0___RWC QCSR_REG_RW +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B0___POR 0x00000400 +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_SPUR2_EXT_Q___POR 0x000 +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_SPUR2_EXT_I___POR 0x400 +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_SPUR2_EXT_Q___M 0x0FFF0000 +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_SPUR2_EXT_Q___S 16 +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_SPUR2_EXT_I___M 0x00000FFF +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_SPUR2_EXT_I___S 0 +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B0___M 0x0FFF0FFF +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B0___S 0 + +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B1 (0x003A503C) +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B1___RWC QCSR_REG_RW +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B1___POR 0x00000400 +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_SPUR2_EXT_Q___POR 0x000 +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_SPUR2_EXT_I___POR 0x400 +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_SPUR2_EXT_Q___M 0x0FFF0000 +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_SPUR2_EXT_Q___S 16 +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_SPUR2_EXT_I___M 0x00000FFF +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_SPUR2_EXT_I___S 0 +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B1___M 0x0FFF0FFF +#define PHYA_RXTD_CHN_SPUR2_NOTCH_CORR_COEFF_U_B1___S 0 + +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B0 (0x003A4040) +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B0___RWC QCSR_REG_RW +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B0___POR 0x00000400 +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_DC_PRI_Q___POR 0x000 +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_DC_PRI_I___POR 0x400 +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_DC_PRI_Q___M 0x0FFF0000 +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_DC_PRI_Q___S 16 +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_DC_PRI_I___M 0x00000FFF +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B0__NOTCH_CORR_DC_PRI_I___S 0 +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B0___M 0x0FFF0FFF +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B0___S 0 + +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B1 (0x003A5040) +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B1___RWC QCSR_REG_RW +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B1___POR 0x00000400 +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_DC_PRI_Q___POR 0x000 +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_DC_PRI_I___POR 0x400 +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_DC_PRI_Q___M 0x0FFF0000 +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_DC_PRI_Q___S 16 +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_DC_PRI_I___M 0x00000FFF +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B1__NOTCH_CORR_DC_PRI_I___S 0 +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B1___M 0x0FFF0FFF +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_L_B1___S 0 + +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B0 (0x003A4044) +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B0___RWC QCSR_REG_RW +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B0___POR 0x00000400 +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_DC_EXT_Q___POR 0x000 +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_DC_EXT_I___POR 0x400 +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_DC_EXT_Q___M 0x0FFF0000 +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_DC_EXT_Q___S 16 +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_DC_EXT_I___M 0x00000FFF +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B0__NOTCH_CORR_DC_EXT_I___S 0 +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B0___M 0x0FFF0FFF +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B0___S 0 + +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B1 (0x003A5044) +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B1___RWC QCSR_REG_RW +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B1___POR 0x00000400 +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_DC_EXT_Q___POR 0x000 +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_DC_EXT_I___POR 0x400 +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_DC_EXT_Q___M 0x0FFF0000 +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_DC_EXT_Q___S 16 +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_DC_EXT_I___M 0x00000FFF +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B1__NOTCH_CORR_DC_EXT_I___S 0 +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B1___M 0x0FFF0FFF +#define PHYA_RXTD_CHN_DC_NOTCH_CORR_COEFF_U_B1___S 0 + +#define PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B0 (0x003A4048) +#define PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B0___RWC QCSR_REG_RW +#define PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B0___POR 0x04000400 +#define PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B0__NOTCH_CORR_AGG_EXT_I___POR 0x400 +#define PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B0__NOTCH_CORR_AGG_PRI_I___POR 0x400 +#define PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B0__NOTCH_CORR_AGG_EXT_I___M 0x0FFF0000 +#define PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B0__NOTCH_CORR_AGG_EXT_I___S 16 +#define PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B0__NOTCH_CORR_AGG_PRI_I___M 0x00000FFF +#define PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B0__NOTCH_CORR_AGG_PRI_I___S 0 +#define PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B0___M 0x0FFF0FFF +#define PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B0___S 0 + +#define PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B1 (0x003A5048) +#define PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B1___RWC QCSR_REG_RW +#define PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B1___POR 0x04000400 +#define PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B1__NOTCH_CORR_AGG_EXT_I___POR 0x400 +#define PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B1__NOTCH_CORR_AGG_PRI_I___POR 0x400 +#define PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B1__NOTCH_CORR_AGG_EXT_I___M 0x0FFF0000 +#define PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B1__NOTCH_CORR_AGG_EXT_I___S 16 +#define PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B1__NOTCH_CORR_AGG_PRI_I___M 0x00000FFF +#define PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B1__NOTCH_CORR_AGG_PRI_I___S 0 +#define PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B1___M 0x0FFF0FFF +#define PHYA_RXTD_CHN_NOTCH_AGG_CORR_COEFF_L_B1___S 0 + +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B0 (0x003A4050) +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B0___RWC QCSR_REG_RW +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B0___POR 0x032C032C +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B0__MINCCAPWR_SEC80_DB2___POR 0x32C +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B0__MINCCAPWR_PRI80_DB2___POR 0x32C +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B0__MINCCAPWR_SEC80_DB2___M 0x03FF0000 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B0__MINCCAPWR_SEC80_DB2___S 16 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B0__MINCCAPWR_PRI80_DB2___M 0x000003FF +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B0__MINCCAPWR_PRI80_DB2___S 0 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B0___M 0x03FF03FF +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B0___S 0 + +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B1 (0x003A5050) +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B1___RWC QCSR_REG_RW +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B1___POR 0x032C032C +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B1__MINCCAPWR_SEC80_DB2___POR 0x32C +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B1__MINCCAPWR_PRI80_DB2___POR 0x32C +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B1__MINCCAPWR_SEC80_DB2___M 0x03FF0000 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B1__MINCCAPWR_SEC80_DB2___S 16 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B1__MINCCAPWR_PRI80_DB2___M 0x000003FF +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B1__MINCCAPWR_PRI80_DB2___S 0 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B1___M 0x03FF03FF +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_L_B1___S 0 + +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B0 (0x003A4054) +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B0___RWC QCSR_REG_RW +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B0___POR 0x000F019C +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B0__R_BT_IN_TX_HOLD_NF___POR 0x0 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B0__NF_CAL_GTC_MASK___POR 0xF +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B0__CF_MAXCCAPWR_DB2___POR 0x19C +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B0__R_BT_IN_TX_HOLD_NF___M 0x01000000 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B0__R_BT_IN_TX_HOLD_NF___S 24 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B0__NF_CAL_GTC_MASK___M 0x000F0000 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B0__NF_CAL_GTC_MASK___S 16 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B0__CF_MAXCCAPWR_DB2___M 0x000001FF +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B0__CF_MAXCCAPWR_DB2___S 0 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B0___M 0x010F01FF +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B0___S 0 + +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B1 (0x003A5054) +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B1___RWC QCSR_REG_RW +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B1___POR 0x000F019C +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B1__R_BT_IN_TX_HOLD_NF___POR 0x0 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B1__NF_CAL_GTC_MASK___POR 0xF +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B1__CF_MAXCCAPWR_DB2___POR 0x19C +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B1__R_BT_IN_TX_HOLD_NF___M 0x01000000 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B1__R_BT_IN_TX_HOLD_NF___S 24 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B1__NF_CAL_GTC_MASK___M 0x000F0000 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B1__NF_CAL_GTC_MASK___S 16 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B1__CF_MAXCCAPWR_DB2___M 0x000001FF +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B1__CF_MAXCCAPWR_DB2___S 0 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B1___M 0x010F01FF +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG1_U_B1___S 0 + +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B0 (0x003A4058) +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B0___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B0___POR 0x00008080 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B0__GAIN_TABLE_IDX___POR 0x0 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B0__TOTAL_GAIN_DB___POR 0x00 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B0__GAIN_RATIO_SQ___POR 0x80 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B0__GAIN_RATIO___POR 0x80 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B0__GAIN_TABLE_IDX___M 0x03000000 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B0__GAIN_TABLE_IDX___S 24 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B0__TOTAL_GAIN_DB___M 0x00FF0000 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B0__TOTAL_GAIN_DB___S 16 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B0__GAIN_RATIO_SQ___M 0x0000FF00 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B0__GAIN_RATIO_SQ___S 8 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B0__GAIN_RATIO___M 0x000000FF +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B0__GAIN_RATIO___S 0 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B0___M 0x03FFFFFF +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B0___S 0 + +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B1 (0x003A5058) +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B1___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B1___POR 0x00008080 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B1__GAIN_TABLE_IDX___POR 0x0 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B1__TOTAL_GAIN_DB___POR 0x00 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B1__GAIN_RATIO_SQ___POR 0x80 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B1__GAIN_RATIO___POR 0x80 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B1__GAIN_TABLE_IDX___M 0x03000000 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B1__GAIN_TABLE_IDX___S 24 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B1__TOTAL_GAIN_DB___M 0x00FF0000 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B1__TOTAL_GAIN_DB___S 16 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B1__GAIN_RATIO_SQ___M 0x0000FF00 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B1__GAIN_RATIO_SQ___S 8 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B1__GAIN_RATIO___M 0x000000FF +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B1__GAIN_RATIO___S 0 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B1___M 0x03FFFFFF +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_L_B1___S 0 + +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B0 (0x003A405C) +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B0___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B0___POR 0x00000000 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B0__LOCAL_RESERVED_WORD___POR 0x0000 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B0__DC_SUB_ACTIVE_VLD___POR 0x0 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B0__DC_SUB_ACTIVE___POR 0x0 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B0__LOCAL_RESERVED_WORD___M 0xFFFF0000 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B0__LOCAL_RESERVED_WORD___S 16 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B0__DC_SUB_ACTIVE_VLD___M 0x00000100 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B0__DC_SUB_ACTIVE_VLD___S 8 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B0__DC_SUB_ACTIVE___M 0x00000001 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B0__DC_SUB_ACTIVE___S 0 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B0___M 0xFFFF0101 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B0___S 0 + +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B1 (0x003A505C) +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B1___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B1___POR 0x00000000 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B1__LOCAL_RESERVED_WORD___POR 0x0000 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B1__DC_SUB_ACTIVE_VLD___POR 0x0 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B1__DC_SUB_ACTIVE___POR 0x0 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B1__LOCAL_RESERVED_WORD___M 0xFFFF0000 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B1__LOCAL_RESERVED_WORD___S 16 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B1__DC_SUB_ACTIVE_VLD___M 0x00000100 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B1__DC_SUB_ACTIVE_VLD___S 8 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B1__DC_SUB_ACTIVE___M 0x00000001 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B1__DC_SUB_ACTIVE___S 0 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B1___M 0xFFFF0101 +#define PHYA_RXTD_CHN_GAIN_RATIO_INFO_U_B1___S 0 + +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B0 (0x003A4060) +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B0___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B0___POR 0x00000000 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B0__CCA_2ND_CHECK_FIRPWR_COUNT___POR 0x000 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B0__CURR_CCA_COUNT___POR 0x000 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B0__CCA_2ND_CHECK_FIRPWR_COUNT___M 0x0FFF0000 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B0__CCA_2ND_CHECK_FIRPWR_COUNT___S 16 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B0__CURR_CCA_COUNT___M 0x00000FFF +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B0__CURR_CCA_COUNT___S 0 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B0___M 0x0FFF0FFF +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B0___S 0 + +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B1 (0x003A5060) +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B1___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B1___POR 0x00000000 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B1__CCA_2ND_CHECK_FIRPWR_COUNT___POR 0x000 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B1__CURR_CCA_COUNT___POR 0x000 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B1__CCA_2ND_CHECK_FIRPWR_COUNT___M 0x0FFF0000 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B1__CCA_2ND_CHECK_FIRPWR_COUNT___S 16 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B1__CURR_CCA_COUNT___M 0x00000FFF +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B1__CURR_CCA_COUNT___S 0 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B1___M 0x0FFF0FFF +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_L_B1___S 0 + +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_U_B0 (0x003A4064) +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_U_B0___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_U_B0___POR 0x00000000 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_U_B0__CCA_2ND_CHECK_RELPWR_COUNT___POR 0x000 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_U_B0__CCA_2ND_CHECK_RELPWR_COUNT___M 0x00000FFF +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_U_B0__CCA_2ND_CHECK_RELPWR_COUNT___S 0 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_U_B0___M 0x00000FFF +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_U_B0___S 0 + +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_U_B1 (0x003A5064) +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_U_B1___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_U_B1___POR 0x00000000 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_U_B1__CCA_2ND_CHECK_RELPWR_COUNT___POR 0x000 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_U_B1__CCA_2ND_CHECK_RELPWR_COUNT___M 0x00000FFF +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_U_B1__CCA_2ND_CHECK_RELPWR_COUNT___S 0 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_U_B1___M 0x00000FFF +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG2_U_B1___S 0 + +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B0 (0x003A4068) +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B0___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B0___POR 0x02000200 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B0__MINCCAPWR_EXT20_OUT_DB2___POR 0x200 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B0__MINCCAPWR_OUT_DB2___POR 0x200 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B0__MINCCAPWR_EXT20_OUT_DB2___M 0x03FF0000 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B0__MINCCAPWR_EXT20_OUT_DB2___S 16 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B0__MINCCAPWR_OUT_DB2___M 0x000003FF +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B0__MINCCAPWR_OUT_DB2___S 0 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B0___M 0x03FF03FF +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B0___S 0 + +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B1 (0x003A5068) +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B1___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B1___POR 0x02000200 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B1__MINCCAPWR_EXT20_OUT_DB2___POR 0x200 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B1__MINCCAPWR_OUT_DB2___POR 0x200 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B1__MINCCAPWR_EXT20_OUT_DB2___M 0x03FF0000 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B1__MINCCAPWR_EXT20_OUT_DB2___S 16 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B1__MINCCAPWR_OUT_DB2___M 0x000003FF +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B1__MINCCAPWR_OUT_DB2___S 0 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B1___M 0x03FF03FF +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_L_B1___S 0 + +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B0 (0x003A406C) +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B0___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B0___POR 0x02000200 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B0__MINCCAPWR_EXT40_HI20_OUT_DB2___POR 0x200 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B0__MINCCAPWR_EXT40_LOW20_OUT_DB2___POR 0x200 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B0__MINCCAPWR_EXT40_HI20_OUT_DB2___M 0x03FF0000 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B0__MINCCAPWR_EXT40_HI20_OUT_DB2___S 16 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B0__MINCCAPWR_EXT40_LOW20_OUT_DB2___M 0x000003FF +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B0__MINCCAPWR_EXT40_LOW20_OUT_DB2___S 0 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B0___M 0x03FF03FF +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B0___S 0 + +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B1 (0x003A506C) +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B1___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B1___POR 0x02000200 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B1__MINCCAPWR_EXT40_HI20_OUT_DB2___POR 0x200 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B1__MINCCAPWR_EXT40_LOW20_OUT_DB2___POR 0x200 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B1__MINCCAPWR_EXT40_HI20_OUT_DB2___M 0x03FF0000 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B1__MINCCAPWR_EXT40_HI20_OUT_DB2___S 16 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B1__MINCCAPWR_EXT40_LOW20_OUT_DB2___M 0x000003FF +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B1__MINCCAPWR_EXT40_LOW20_OUT_DB2___S 0 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B1___M 0x03FF03FF +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_0_U_B1___S 0 + +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B0 (0x003A4070) +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B0___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B0___POR 0x02000200 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B0__MINCCAPWR_EXT80_LOW40_HI20_OUT_DB2___POR 0x200 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B0__MINCCAPWR_EXT80_LOW40_LOW20_OUT_DB2___POR 0x200 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B0__MINCCAPWR_EXT80_LOW40_HI20_OUT_DB2___M 0x03FF0000 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B0__MINCCAPWR_EXT80_LOW40_HI20_OUT_DB2___S 16 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B0__MINCCAPWR_EXT80_LOW40_LOW20_OUT_DB2___M 0x000003FF +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B0__MINCCAPWR_EXT80_LOW40_LOW20_OUT_DB2___S 0 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B0___M 0x03FF03FF +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B0___S 0 + +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B1 (0x003A5070) +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B1___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B1___POR 0x02000200 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B1__MINCCAPWR_EXT80_LOW40_HI20_OUT_DB2___POR 0x200 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B1__MINCCAPWR_EXT80_LOW40_LOW20_OUT_DB2___POR 0x200 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B1__MINCCAPWR_EXT80_LOW40_HI20_OUT_DB2___M 0x03FF0000 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B1__MINCCAPWR_EXT80_LOW40_HI20_OUT_DB2___S 16 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B1__MINCCAPWR_EXT80_LOW40_LOW20_OUT_DB2___M 0x000003FF +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B1__MINCCAPWR_EXT80_LOW40_LOW20_OUT_DB2___S 0 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B1___M 0x03FF03FF +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_L_B1___S 0 + +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B0 (0x003A4074) +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B0___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B0___POR 0x02000200 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B0__MINCCAPWR_EXT80_HI40_HI20_OUT_DB2___POR 0x200 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B0__MINCCAPWR_EXT80_HI40_LOW20_OUT_DB2___POR 0x200 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B0__MINCCAPWR_EXT80_HI40_HI20_OUT_DB2___M 0x03FF0000 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B0__MINCCAPWR_EXT80_HI40_HI20_OUT_DB2___S 16 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B0__MINCCAPWR_EXT80_HI40_LOW20_OUT_DB2___M 0x000003FF +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B0__MINCCAPWR_EXT80_HI40_LOW20_OUT_DB2___S 0 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B0___M 0x03FF03FF +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B0___S 0 + +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B1 (0x003A5074) +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B1___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B1___POR 0x02000200 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B1__MINCCAPWR_EXT80_HI40_HI20_OUT_DB2___POR 0x200 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B1__MINCCAPWR_EXT80_HI40_LOW20_OUT_DB2___POR 0x200 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B1__MINCCAPWR_EXT80_HI40_HI20_OUT_DB2___M 0x03FF0000 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B1__MINCCAPWR_EXT80_HI40_HI20_OUT_DB2___S 16 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B1__MINCCAPWR_EXT80_HI40_LOW20_OUT_DB2___M 0x000003FF +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B1__MINCCAPWR_EXT80_HI40_LOW20_OUT_DB2___S 0 +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B1___M 0x03FF03FF +#define PHYA_RXTD_CHN_AGC_NFCAL_CHN_CONFIG3_1_U_B1___S 0 + +#define PHYA_RXTD_CHN_LB_DC_OFF_L_B0 (0x003A4078) +#define PHYA_RXTD_CHN_LB_DC_OFF_L_B0___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_LB_DC_OFF_L_B0___POR 0x00000000 +#define PHYA_RXTD_CHN_LB_DC_OFF_L_B0__DC_OFF_Q___POR 0x0000 +#define PHYA_RXTD_CHN_LB_DC_OFF_L_B0__DC_OFF_I___POR 0x0000 +#define PHYA_RXTD_CHN_LB_DC_OFF_L_B0__DC_OFF_Q___M 0xFFFF0000 +#define PHYA_RXTD_CHN_LB_DC_OFF_L_B0__DC_OFF_Q___S 16 +#define PHYA_RXTD_CHN_LB_DC_OFF_L_B0__DC_OFF_I___M 0x0000FFFF +#define PHYA_RXTD_CHN_LB_DC_OFF_L_B0__DC_OFF_I___S 0 +#define PHYA_RXTD_CHN_LB_DC_OFF_L_B0___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_LB_DC_OFF_L_B0___S 0 + +#define PHYA_RXTD_CHN_LB_DC_OFF_L_B1 (0x003A5078) +#define PHYA_RXTD_CHN_LB_DC_OFF_L_B1___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_LB_DC_OFF_L_B1___POR 0x00000000 +#define PHYA_RXTD_CHN_LB_DC_OFF_L_B1__DC_OFF_Q___POR 0x0000 +#define PHYA_RXTD_CHN_LB_DC_OFF_L_B1__DC_OFF_I___POR 0x0000 +#define PHYA_RXTD_CHN_LB_DC_OFF_L_B1__DC_OFF_Q___M 0xFFFF0000 +#define PHYA_RXTD_CHN_LB_DC_OFF_L_B1__DC_OFF_Q___S 16 +#define PHYA_RXTD_CHN_LB_DC_OFF_L_B1__DC_OFF_I___M 0x0000FFFF +#define PHYA_RXTD_CHN_LB_DC_OFF_L_B1__DC_OFF_I___S 0 +#define PHYA_RXTD_CHN_LB_DC_OFF_L_B1___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_LB_DC_OFF_L_B1___S 0 + +#define PHYA_RXTD_CHN_RSSI_CAPTURE_L_B0 (0x003A4080) +#define PHYA_RXTD_CHN_RSSI_CAPTURE_L_B0___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_RSSI_CAPTURE_L_B0___POR 0x80808080 +#define PHYA_RXTD_CHN_RSSI_CAPTURE_L_B0__RSSI_CAPTURE___POR 0x80808080 +#define PHYA_RXTD_CHN_RSSI_CAPTURE_L_B0__RSSI_CAPTURE___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_RSSI_CAPTURE_L_B0__RSSI_CAPTURE___S 0 +#define PHYA_RXTD_CHN_RSSI_CAPTURE_L_B0___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_RSSI_CAPTURE_L_B0___S 0 + +#define PHYA_RXTD_CHN_RSSI_CAPTURE_L_B1 (0x003A5080) +#define PHYA_RXTD_CHN_RSSI_CAPTURE_L_B1___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_RSSI_CAPTURE_L_B1___POR 0x80808080 +#define PHYA_RXTD_CHN_RSSI_CAPTURE_L_B1__RSSI_CAPTURE___POR 0x80808080 +#define PHYA_RXTD_CHN_RSSI_CAPTURE_L_B1__RSSI_CAPTURE___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_RSSI_CAPTURE_L_B1__RSSI_CAPTURE___S 0 +#define PHYA_RXTD_CHN_RSSI_CAPTURE_L_B1___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_RSSI_CAPTURE_L_B1___S 0 + +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_L_B0 (0x003A4088) +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_L_B0___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_L_B0___POR 0x80808080 +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_L_B0__POST_RSSI_CAPTURE___POR 0x80808080 +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_L_B0__POST_RSSI_CAPTURE___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_L_B0__POST_RSSI_CAPTURE___S 0 +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_L_B0___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_L_B0___S 0 + +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_L_B1 (0x003A5088) +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_L_B1___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_L_B1___POR 0x80808080 +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_L_B1__POST_RSSI_CAPTURE___POR 0x80808080 +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_L_B1__POST_RSSI_CAPTURE___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_L_B1__POST_RSSI_CAPTURE___S 0 +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_L_B1___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_L_B1___S 0 + +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_L_B0 (0x003A4090) +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_L_B0___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_L_B0___POR 0x80808080 +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_L_B0__PRE_RSSI_CAPTURE___POR 0x80808080 +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_L_B0__PRE_RSSI_CAPTURE___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_L_B0__PRE_RSSI_CAPTURE___S 0 +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_L_B0___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_L_B0___S 0 + +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_L_B1 (0x003A5090) +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_L_B1___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_L_B1___POR 0x80808080 +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_L_B1__PRE_RSSI_CAPTURE___POR 0x80808080 +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_L_B1__PRE_RSSI_CAPTURE___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_L_B1__PRE_RSSI_CAPTURE___S 0 +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_L_B1___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_L_B1___S 0 + +#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_L_B0 (0x003A4098) +#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_L_B0___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_L_B0___POR 0x80808080 +#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_L_B0__RSSI_CAPTURE_EXT80___POR 0x80808080 +#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_L_B0__RSSI_CAPTURE_EXT80___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_L_B0__RSSI_CAPTURE_EXT80___S 0 +#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_L_B0___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_L_B0___S 0 + +#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_L_B1 (0x003A5098) +#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_L_B1___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_L_B1___POR 0x80808080 +#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_L_B1__RSSI_CAPTURE_EXT80___POR 0x80808080 +#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_L_B1__RSSI_CAPTURE_EXT80___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_L_B1__RSSI_CAPTURE_EXT80___S 0 +#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_L_B1___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_L_B1___S 0 + +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_L_B0 (0x003A40A0) +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_L_B0___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_L_B0___POR 0x80808080 +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_L_B0__POST_RSSI_CAPTURE_EXT80___POR 0x80808080 +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_L_B0__POST_RSSI_CAPTURE_EXT80___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_L_B0__POST_RSSI_CAPTURE_EXT80___S 0 +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_L_B0___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_L_B0___S 0 + +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_L_B1 (0x003A50A0) +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_L_B1___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_L_B1___POR 0x80808080 +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_L_B1__POST_RSSI_CAPTURE_EXT80___POR 0x80808080 +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_L_B1__POST_RSSI_CAPTURE_EXT80___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_L_B1__POST_RSSI_CAPTURE_EXT80___S 0 +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_L_B1___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_L_B1___S 0 + +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_L_B0 (0x003A40A8) +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_L_B0___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_L_B0___POR 0x80808080 +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_L_B0__PRE_RSSI_CAPTURE_EXT80___POR 0x80808080 +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_L_B0__PRE_RSSI_CAPTURE_EXT80___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_L_B0__PRE_RSSI_CAPTURE_EXT80___S 0 +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_L_B0___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_L_B0___S 0 + +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_L_B1 (0x003A50A8) +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_L_B1___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_L_B1___POR 0x80808080 +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_L_B1__PRE_RSSI_CAPTURE_EXT80___POR 0x80808080 +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_L_B1__PRE_RSSI_CAPTURE_EXT80___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_L_B1__PRE_RSSI_CAPTURE_EXT80___S 0 +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_L_B1___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_L_B1___S 0 + +#define PHYA_RXTD_CHN_RSSI_CAPTURE_DBM_L_B0 (0x003A40B0) +#define PHYA_RXTD_CHN_RSSI_CAPTURE_DBM_L_B0___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_RSSI_CAPTURE_DBM_L_B0___POR 0x80808080 +#define PHYA_RXTD_CHN_RSSI_CAPTURE_DBM_L_B0__RSSI_CAPTURE_DBM___POR 0x80808080 +#define PHYA_RXTD_CHN_RSSI_CAPTURE_DBM_L_B0__RSSI_CAPTURE_DBM___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_RSSI_CAPTURE_DBM_L_B0__RSSI_CAPTURE_DBM___S 0 +#define PHYA_RXTD_CHN_RSSI_CAPTURE_DBM_L_B0___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_RSSI_CAPTURE_DBM_L_B0___S 0 + +#define PHYA_RXTD_CHN_RSSI_CAPTURE_DBM_L_B1 (0x003A50B0) +#define PHYA_RXTD_CHN_RSSI_CAPTURE_DBM_L_B1___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_RSSI_CAPTURE_DBM_L_B1___POR 0x80808080 +#define PHYA_RXTD_CHN_RSSI_CAPTURE_DBM_L_B1__RSSI_CAPTURE_DBM___POR 0x80808080 +#define PHYA_RXTD_CHN_RSSI_CAPTURE_DBM_L_B1__RSSI_CAPTURE_DBM___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_RSSI_CAPTURE_DBM_L_B1__RSSI_CAPTURE_DBM___S 0 +#define PHYA_RXTD_CHN_RSSI_CAPTURE_DBM_L_B1___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_RSSI_CAPTURE_DBM_L_B1___S 0 + +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_DBM_L_B0 (0x003A40B8) +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_DBM_L_B0___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_DBM_L_B0___POR 0x80808080 +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_DBM_L_B0__POST_RSSI_CAPTURE_DBM___POR 0x80808080 +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_DBM_L_B0__POST_RSSI_CAPTURE_DBM___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_DBM_L_B0__POST_RSSI_CAPTURE_DBM___S 0 +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_DBM_L_B0___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_DBM_L_B0___S 0 + +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_DBM_L_B1 (0x003A50B8) +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_DBM_L_B1___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_DBM_L_B1___POR 0x80808080 +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_DBM_L_B1__POST_RSSI_CAPTURE_DBM___POR 0x80808080 +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_DBM_L_B1__POST_RSSI_CAPTURE_DBM___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_DBM_L_B1__POST_RSSI_CAPTURE_DBM___S 0 +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_DBM_L_B1___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_DBM_L_B1___S 0 + +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_DBM_L_B0 (0x003A40C0) +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_DBM_L_B0___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_DBM_L_B0___POR 0x80808080 +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_DBM_L_B0__PRE_RSSI_CAPTURE_DBM___POR 0x80808080 +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_DBM_L_B0__PRE_RSSI_CAPTURE_DBM___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_DBM_L_B0__PRE_RSSI_CAPTURE_DBM___S 0 +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_DBM_L_B0___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_DBM_L_B0___S 0 + +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_DBM_L_B1 (0x003A50C0) +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_DBM_L_B1___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_DBM_L_B1___POR 0x80808080 +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_DBM_L_B1__PRE_RSSI_CAPTURE_DBM___POR 0x80808080 +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_DBM_L_B1__PRE_RSSI_CAPTURE_DBM___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_DBM_L_B1__PRE_RSSI_CAPTURE_DBM___S 0 +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_DBM_L_B1___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_DBM_L_B1___S 0 + +#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_DBM_L_B0 (0x003A40C8) +#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_DBM_L_B0___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_DBM_L_B0___POR 0x80808080 +#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_DBM_L_B0__RSSI_CAPTURE_EXT80_DBM___POR 0x80808080 +#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_DBM_L_B0__RSSI_CAPTURE_EXT80_DBM___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_DBM_L_B0__RSSI_CAPTURE_EXT80_DBM___S 0 +#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_DBM_L_B0___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_DBM_L_B0___S 0 + +#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_DBM_L_B1 (0x003A50C8) +#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_DBM_L_B1___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_DBM_L_B1___POR 0x80808080 +#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_DBM_L_B1__RSSI_CAPTURE_EXT80_DBM___POR 0x80808080 +#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_DBM_L_B1__RSSI_CAPTURE_EXT80_DBM___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_DBM_L_B1__RSSI_CAPTURE_EXT80_DBM___S 0 +#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_DBM_L_B1___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_RSSI_CAPTURE_EXT80_DBM_L_B1___S 0 + +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_DBM_L_B0 (0x003A40D0) +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_DBM_L_B0___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_DBM_L_B0___POR 0x80808080 +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_DBM_L_B0__POST_RSSI_CAPTURE_EXT80_DBM___POR 0x80808080 +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_DBM_L_B0__POST_RSSI_CAPTURE_EXT80_DBM___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_DBM_L_B0__POST_RSSI_CAPTURE_EXT80_DBM___S 0 +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_DBM_L_B0___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_DBM_L_B0___S 0 + +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_DBM_L_B1 (0x003A50D0) +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_DBM_L_B1___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_DBM_L_B1___POR 0x80808080 +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_DBM_L_B1__POST_RSSI_CAPTURE_EXT80_DBM___POR 0x80808080 +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_DBM_L_B1__POST_RSSI_CAPTURE_EXT80_DBM___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_DBM_L_B1__POST_RSSI_CAPTURE_EXT80_DBM___S 0 +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_DBM_L_B1___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_POST_RSSI_CAPTURE_EXT80_DBM_L_B1___S 0 + +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_DBM_0_L_B0 (0x003A40D8) +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_DBM_0_L_B0___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_DBM_0_L_B0___POR 0x80808080 +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_DBM_0_L_B0__PRE_RSSI_CAPTURE_EXT80_DBM___POR 0x80808080 +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_DBM_0_L_B0__PRE_RSSI_CAPTURE_EXT80_DBM___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_DBM_0_L_B0__PRE_RSSI_CAPTURE_EXT80_DBM___S 0 +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_DBM_0_L_B0___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_DBM_0_L_B0___S 0 + +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_DBM_0_L_B1 (0x003A50D8) +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_DBM_0_L_B1___RWC QCSR_REG_RO +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_DBM_0_L_B1___POR 0x80808080 +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_DBM_0_L_B1__PRE_RSSI_CAPTURE_EXT80_DBM___POR 0x80808080 +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_DBM_0_L_B1__PRE_RSSI_CAPTURE_EXT80_DBM___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_DBM_0_L_B1__PRE_RSSI_CAPTURE_EXT80_DBM___S 0 +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_DBM_0_L_B1___M 0xFFFFFFFF +#define PHYA_RXTD_CHN_PRE_RSSI_CAPTURE_EXT80_DBM_0_L_B1___S 0 + +#define PHYA_TXTD_RESET_CTRL_L (0x003B0000) +#define PHYA_TXTD_RESET_CTRL_L___RWC QCSR_REG_RW +#define PHYA_TXTD_RESET_CTRL_L___POR 0x00000000 +#define PHYA_TXTD_RESET_CTRL_L__TXTD_ACC_RESET___POR 0x0 +#define PHYA_TXTD_RESET_CTRL_L__TXTD_ACC_RESET___M 0x00000001 +#define PHYA_TXTD_RESET_CTRL_L__TXTD_ACC_RESET___S 0 +#define PHYA_TXTD_RESET_CTRL_L___M 0x00000001 +#define PHYA_TXTD_RESET_CTRL_L___S 0 + +#define PHYA_TXTD_TX_CTRL_L (0x003B0008) +#define PHYA_TXTD_TX_CTRL_L___RWC QCSR_REG_RW +#define PHYA_TXTD_TX_CTRL_L___POR 0x00000000 +#define PHYA_TXTD_TX_CTRL_L__TX_ABORT___POR 0x0 +#define PHYA_TXTD_TX_CTRL_L__TX_ABORT___M 0x00000001 +#define PHYA_TXTD_TX_CTRL_L__TX_ABORT___S 0 +#define PHYA_TXTD_TX_CTRL_L___M 0x00000001 +#define PHYA_TXTD_TX_CTRL_L___S 0 + +#define PHYA_TXTD_ECO_CONTROL_L (0x003B0010) +#define PHYA_TXTD_ECO_CONTROL_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ECO_CONTROL_L___POR 0x00000000 +#define PHYA_TXTD_ECO_CONTROL_L__ECO_CTRL___POR 0x00000000 +#define PHYA_TXTD_ECO_CONTROL_L__ECO_CTRL___M 0xFFFFFFFF +#define PHYA_TXTD_ECO_CONTROL_L__ECO_CTRL___S 0 +#define PHYA_TXTD_ECO_CONTROL_L___M 0xFFFFFFFF +#define PHYA_TXTD_ECO_CONTROL_L___S 0 + +#define PHYA_TXTD_ECO_CONTROL_U (0x003B0014) +#define PHYA_TXTD_ECO_CONTROL_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ECO_CONTROL_U___POR 0x00000000 +#define PHYA_TXTD_ECO_CONTROL_U__ECO_CFG___POR 0x00000000 +#define PHYA_TXTD_ECO_CONTROL_U__ECO_CFG___M 0xFFFFFFFF +#define PHYA_TXTD_ECO_CONTROL_U__ECO_CFG___S 0 +#define PHYA_TXTD_ECO_CONTROL_U___M 0xFFFFFFFF +#define PHYA_TXTD_ECO_CONTROL_U___S 0 + +#define PHYA_TXTD_ECO_STATUS_L (0x003B0018) +#define PHYA_TXTD_ECO_STATUS_L___RWC QCSR_REG_RO +#define PHYA_TXTD_ECO_STATUS_L___POR 0x00000000 +#define PHYA_TXTD_ECO_STATUS_L__ECO_STAT___POR 0x00000000 +#define PHYA_TXTD_ECO_STATUS_L__ECO_STAT___M 0xFFFFFFFF +#define PHYA_TXTD_ECO_STATUS_L__ECO_STAT___S 0 +#define PHYA_TXTD_ECO_STATUS_L___M 0xFFFFFFFF +#define PHYA_TXTD_ECO_STATUS_L___S 0 + +#define PHYA_TXTD_EVENT_STATUS_L (0x003B0020) +#define PHYA_TXTD_EVENT_STATUS_L___RWC QCSR_REG_RW +#define PHYA_TXTD_EVENT_STATUS_L___POR 0x00000000 +#define PHYA_TXTD_EVENT_STATUS_L__FFT_LAST_SAMPLE_OUT_EVENT___POR 0x0 +#define PHYA_TXTD_EVENT_STATUS_L__SPARE_EVENT_4___POR 0x0 +#define PHYA_TXTD_EVENT_STATUS_L__FFT_STAGES_DONE_EVENT___POR 0x0 +#define PHYA_TXTD_EVENT_STATUS_L__FFT_STAGE0_DONE_EVENT___POR 0x0 +#define PHYA_TXTD_EVENT_STATUS_L__SPARE_EVENT_1___POR 0x0 +#define PHYA_TXTD_EVENT_STATUS_L__PKT_END_EVENT___POR 0x0 +#define PHYA_TXTD_EVENT_STATUS_L__PKT_DATA_EVENT___POR 0x0 +#define PHYA_TXTD_EVENT_STATUS_L__PRE_DATA_EVENT___POR 0x0 +#define PHYA_TXTD_EVENT_STATUS_L__MULTI_SYM_EVENT___POR 0x0 +#define PHYA_TXTD_EVENT_STATUS_L__SYM_EVENT___POR 0x0 +#define PHYA_TXTD_EVENT_STATUS_L__TXTD_START_EVENT___POR 0x0 +#define PHYA_TXTD_EVENT_STATUS_L__PKT_START_EVENT___POR 0x0 +#define PHYA_TXTD_EVENT_STATUS_L__TX_DESC_EVENT___POR 0x0 +#define PHYA_TXTD_EVENT_STATUS_L__TX_PRE_DESC_EVENT___POR 0x0 +#define PHYA_TXTD_EVENT_STATUS_L__ECO_EVENT___POR 0x0 +#define PHYA_TXTD_EVENT_STATUS_L__ERROR_EVENT___POR 0x0 +#define PHYA_TXTD_EVENT_STATUS_L__FFT_LAST_SAMPLE_OUT_EVENT___M 0x00008000 +#define PHYA_TXTD_EVENT_STATUS_L__FFT_LAST_SAMPLE_OUT_EVENT___S 15 +#define PHYA_TXTD_EVENT_STATUS_L__SPARE_EVENT_4___M 0x00004000 +#define PHYA_TXTD_EVENT_STATUS_L__SPARE_EVENT_4___S 14 +#define PHYA_TXTD_EVENT_STATUS_L__FFT_STAGES_DONE_EVENT___M 0x00002000 +#define PHYA_TXTD_EVENT_STATUS_L__FFT_STAGES_DONE_EVENT___S 13 +#define PHYA_TXTD_EVENT_STATUS_L__FFT_STAGE0_DONE_EVENT___M 0x00001000 +#define PHYA_TXTD_EVENT_STATUS_L__FFT_STAGE0_DONE_EVENT___S 12 +#define PHYA_TXTD_EVENT_STATUS_L__SPARE_EVENT_1___M 0x00000800 +#define PHYA_TXTD_EVENT_STATUS_L__SPARE_EVENT_1___S 11 +#define PHYA_TXTD_EVENT_STATUS_L__PKT_END_EVENT___M 0x00000400 +#define PHYA_TXTD_EVENT_STATUS_L__PKT_END_EVENT___S 10 +#define PHYA_TXTD_EVENT_STATUS_L__PKT_DATA_EVENT___M 0x00000200 +#define PHYA_TXTD_EVENT_STATUS_L__PKT_DATA_EVENT___S 9 +#define PHYA_TXTD_EVENT_STATUS_L__PRE_DATA_EVENT___M 0x00000100 +#define PHYA_TXTD_EVENT_STATUS_L__PRE_DATA_EVENT___S 8 +#define PHYA_TXTD_EVENT_STATUS_L__MULTI_SYM_EVENT___M 0x00000080 +#define PHYA_TXTD_EVENT_STATUS_L__MULTI_SYM_EVENT___S 7 +#define PHYA_TXTD_EVENT_STATUS_L__SYM_EVENT___M 0x00000040 +#define PHYA_TXTD_EVENT_STATUS_L__SYM_EVENT___S 6 +#define PHYA_TXTD_EVENT_STATUS_L__TXTD_START_EVENT___M 0x00000020 +#define PHYA_TXTD_EVENT_STATUS_L__TXTD_START_EVENT___S 5 +#define PHYA_TXTD_EVENT_STATUS_L__PKT_START_EVENT___M 0x00000010 +#define PHYA_TXTD_EVENT_STATUS_L__PKT_START_EVENT___S 4 +#define PHYA_TXTD_EVENT_STATUS_L__TX_DESC_EVENT___M 0x00000008 +#define PHYA_TXTD_EVENT_STATUS_L__TX_DESC_EVENT___S 3 +#define PHYA_TXTD_EVENT_STATUS_L__TX_PRE_DESC_EVENT___M 0x00000004 +#define PHYA_TXTD_EVENT_STATUS_L__TX_PRE_DESC_EVENT___S 2 +#define PHYA_TXTD_EVENT_STATUS_L__ECO_EVENT___M 0x00000002 +#define PHYA_TXTD_EVENT_STATUS_L__ECO_EVENT___S 1 +#define PHYA_TXTD_EVENT_STATUS_L__ERROR_EVENT___M 0x00000001 +#define PHYA_TXTD_EVENT_STATUS_L__ERROR_EVENT___S 0 +#define PHYA_TXTD_EVENT_STATUS_L___M 0x0000FFFF +#define PHYA_TXTD_EVENT_STATUS_L___S 0 + +#define PHYA_TXTD_EVENT_MASK_L (0x003B0028) +#define PHYA_TXTD_EVENT_MASK_L___RWC QCSR_REG_RW +#define PHYA_TXTD_EVENT_MASK_L___POR 0x0000FFFF +#define PHYA_TXTD_EVENT_MASK_L__FFT_LAST_SAMPLE_OUT_EVENT_MASK___POR 0x1 +#define PHYA_TXTD_EVENT_MASK_L__SPARE_EVENT_MASK_4___POR 0x1 +#define PHYA_TXTD_EVENT_MASK_L__FFT_STAGES_DONE_EVENT_MASK___POR 0x1 +#define PHYA_TXTD_EVENT_MASK_L__FFT_STAGE0_DONE_EVENT_MASK___POR 0x1 +#define PHYA_TXTD_EVENT_MASK_L__SPARE_EVENT_MASK_1___POR 0x1 +#define PHYA_TXTD_EVENT_MASK_L__PKT_END_EVENT_MASK___POR 0x1 +#define PHYA_TXTD_EVENT_MASK_L__PKT_DATA_EVENT_MASK___POR 0x1 +#define PHYA_TXTD_EVENT_MASK_L__PRE_DATA_EVENT_MASK___POR 0x1 +#define PHYA_TXTD_EVENT_MASK_L__MULTI_SYM_EVENT_MASK___POR 0x1 +#define PHYA_TXTD_EVENT_MASK_L__SYM_EVENT_MASK___POR 0x1 +#define PHYA_TXTD_EVENT_MASK_L__TXTD_START_EVENT_MASK___POR 0x1 +#define PHYA_TXTD_EVENT_MASK_L__PKT_START_EVENT_MASK___POR 0x1 +#define PHYA_TXTD_EVENT_MASK_L__TX_DESC_EVENT_MASK___POR 0x1 +#define PHYA_TXTD_EVENT_MASK_L__TX_PRE_DESC_EVENT_MASK___POR 0x1 +#define PHYA_TXTD_EVENT_MASK_L__ECO_EVENT_MASK___POR 0x1 +#define PHYA_TXTD_EVENT_MASK_L__ERROR_EVENT_MASK___POR 0x1 +#define PHYA_TXTD_EVENT_MASK_L__FFT_LAST_SAMPLE_OUT_EVENT_MASK___M 0x00008000 +#define PHYA_TXTD_EVENT_MASK_L__FFT_LAST_SAMPLE_OUT_EVENT_MASK___S 15 +#define PHYA_TXTD_EVENT_MASK_L__SPARE_EVENT_MASK_4___M 0x00004000 +#define PHYA_TXTD_EVENT_MASK_L__SPARE_EVENT_MASK_4___S 14 +#define PHYA_TXTD_EVENT_MASK_L__FFT_STAGES_DONE_EVENT_MASK___M 0x00002000 +#define PHYA_TXTD_EVENT_MASK_L__FFT_STAGES_DONE_EVENT_MASK___S 13 +#define PHYA_TXTD_EVENT_MASK_L__FFT_STAGE0_DONE_EVENT_MASK___M 0x00001000 +#define PHYA_TXTD_EVENT_MASK_L__FFT_STAGE0_DONE_EVENT_MASK___S 12 +#define PHYA_TXTD_EVENT_MASK_L__SPARE_EVENT_MASK_1___M 0x00000800 +#define PHYA_TXTD_EVENT_MASK_L__SPARE_EVENT_MASK_1___S 11 +#define PHYA_TXTD_EVENT_MASK_L__PKT_END_EVENT_MASK___M 0x00000400 +#define PHYA_TXTD_EVENT_MASK_L__PKT_END_EVENT_MASK___S 10 +#define PHYA_TXTD_EVENT_MASK_L__PKT_DATA_EVENT_MASK___M 0x00000200 +#define PHYA_TXTD_EVENT_MASK_L__PKT_DATA_EVENT_MASK___S 9 +#define PHYA_TXTD_EVENT_MASK_L__PRE_DATA_EVENT_MASK___M 0x00000100 +#define PHYA_TXTD_EVENT_MASK_L__PRE_DATA_EVENT_MASK___S 8 +#define PHYA_TXTD_EVENT_MASK_L__MULTI_SYM_EVENT_MASK___M 0x00000080 +#define PHYA_TXTD_EVENT_MASK_L__MULTI_SYM_EVENT_MASK___S 7 +#define PHYA_TXTD_EVENT_MASK_L__SYM_EVENT_MASK___M 0x00000040 +#define PHYA_TXTD_EVENT_MASK_L__SYM_EVENT_MASK___S 6 +#define PHYA_TXTD_EVENT_MASK_L__TXTD_START_EVENT_MASK___M 0x00000020 +#define PHYA_TXTD_EVENT_MASK_L__TXTD_START_EVENT_MASK___S 5 +#define PHYA_TXTD_EVENT_MASK_L__PKT_START_EVENT_MASK___M 0x00000010 +#define PHYA_TXTD_EVENT_MASK_L__PKT_START_EVENT_MASK___S 4 +#define PHYA_TXTD_EVENT_MASK_L__TX_DESC_EVENT_MASK___M 0x00000008 +#define PHYA_TXTD_EVENT_MASK_L__TX_DESC_EVENT_MASK___S 3 +#define PHYA_TXTD_EVENT_MASK_L__TX_PRE_DESC_EVENT_MASK___M 0x00000004 +#define PHYA_TXTD_EVENT_MASK_L__TX_PRE_DESC_EVENT_MASK___S 2 +#define PHYA_TXTD_EVENT_MASK_L__ECO_EVENT_MASK___M 0x00000002 +#define PHYA_TXTD_EVENT_MASK_L__ECO_EVENT_MASK___S 1 +#define PHYA_TXTD_EVENT_MASK_L__ERROR_EVENT_MASK___M 0x00000001 +#define PHYA_TXTD_EVENT_MASK_L__ERROR_EVENT_MASK___S 0 +#define PHYA_TXTD_EVENT_MASK_L___M 0x0000FFFF +#define PHYA_TXTD_EVENT_MASK_L___S 0 + +#define PHYA_TXTD_ERROR_CODE_L (0x003B0030) +#define PHYA_TXTD_ERROR_CODE_L___RWC QCSR_REG_RO +#define PHYA_TXTD_ERROR_CODE_L___POR 0x00000000 +#define PHYA_TXTD_ERROR_CODE_L__ERROR_CODE___POR 0x00000000 +#define PHYA_TXTD_ERROR_CODE_L__ERROR_CODE___M 0xFFFFFFFF +#define PHYA_TXTD_ERROR_CODE_L__ERROR_CODE___S 0 +#define PHYA_TXTD_ERROR_CODE_L___M 0xFFFFFFFF +#define PHYA_TXTD_ERROR_CODE_L___S 0 + +#define PHYA_TXTD_ERROR_STATUS_L (0x003B0038) +#define PHYA_TXTD_ERROR_STATUS_L___RWC QCSR_REG_RO +#define PHYA_TXTD_ERROR_STATUS_L___POR 0x00000000 +#define PHYA_TXTD_ERROR_STATUS_L__FFT_ERROR_2___POR 0x0 +#define PHYA_TXTD_ERROR_STATUS_L__FFT_ERROR_1___POR 0x0 +#define PHYA_TXTD_ERROR_STATUS_L__FFT_ERROR_0___POR 0x0 +#define PHYA_TXTD_ERROR_STATUS_L__CCK_TIMEOUT___POR 0x0 +#define PHYA_TXTD_ERROR_STATUS_L__CCK_SAMPLE_OVERFLOW___POR 0x0 +#define PHYA_TXTD_ERROR_STATUS_L__OFDM_SYM_MISMATCH___POR 0x0 +#define PHYA_TXTD_ERROR_STATUS_L__ULD_SYM_CP_LEN_ZERO___POR 0x0 +#define PHYA_TXTD_ERROR_STATUS_L__TXTD_START_DONE___POR 0x0 +#define PHYA_TXTD_ERROR_STATUS_L__TXTD_START_NONIDLE___POR 0x0 +#define PHYA_TXTD_ERROR_STATUS_L__TX_ABORT_NONIDLE___POR 0x0 +#define PHYA_TXTD_ERROR_STATUS_L__TX_ABORT_DONE___POR 0x0 +#define PHYA_TXTD_ERROR_STATUS_L__TX_ABORT_IDLE___POR 0x0 +#define PHYA_TXTD_ERROR_STATUS_L__TXTD_START_UNEXPECTED___POR 0x0 +#define PHYA_TXTD_ERROR_STATUS_L__TX_FRAME_UNEXPECTED___POR 0x0 +#define PHYA_TXTD_ERROR_STATUS_L__TX_VLD_UNALIGN_ERROR___POR 0x0 +#define PHYA_TXTD_ERROR_STATUS_L__PKT_END_ERROR___POR 0x0 +#define PHYA_TXTD_ERROR_STATUS_L__PKT_DATA_ERROR___POR 0x0 +#define PHYA_TXTD_ERROR_STATUS_L__PRE_DATA_ERROR___POR 0x0 +#define PHYA_TXTD_ERROR_STATUS_L__MULTI_SYM_ERROR___POR 0x0 +#define PHYA_TXTD_ERROR_STATUS_L__SYM_ERROR___POR 0x0 +#define PHYA_TXTD_ERROR_STATUS_L__TXTD_START_ERROR___POR 0x0 +#define PHYA_TXTD_ERROR_STATUS_L__PKT_START_ERROR___POR 0x0 +#define PHYA_TXTD_ERROR_STATUS_L__TX_DESC_ERROR___POR 0x0 +#define PHYA_TXTD_ERROR_STATUS_L__TX_PRE_DESC_ERROR___POR 0x0 +#define PHYA_TXTD_ERROR_STATUS_L__FFT_ERROR_2___M 0x00800000 +#define PHYA_TXTD_ERROR_STATUS_L__FFT_ERROR_2___S 23 +#define PHYA_TXTD_ERROR_STATUS_L__FFT_ERROR_1___M 0x00400000 +#define PHYA_TXTD_ERROR_STATUS_L__FFT_ERROR_1___S 22 +#define PHYA_TXTD_ERROR_STATUS_L__FFT_ERROR_0___M 0x00200000 +#define PHYA_TXTD_ERROR_STATUS_L__FFT_ERROR_0___S 21 +#define PHYA_TXTD_ERROR_STATUS_L__CCK_TIMEOUT___M 0x00100000 +#define PHYA_TXTD_ERROR_STATUS_L__CCK_TIMEOUT___S 20 +#define PHYA_TXTD_ERROR_STATUS_L__CCK_SAMPLE_OVERFLOW___M 0x00080000 +#define PHYA_TXTD_ERROR_STATUS_L__CCK_SAMPLE_OVERFLOW___S 19 +#define PHYA_TXTD_ERROR_STATUS_L__OFDM_SYM_MISMATCH___M 0x00040000 +#define PHYA_TXTD_ERROR_STATUS_L__OFDM_SYM_MISMATCH___S 18 +#define PHYA_TXTD_ERROR_STATUS_L__ULD_SYM_CP_LEN_ZERO___M 0x00020000 +#define PHYA_TXTD_ERROR_STATUS_L__ULD_SYM_CP_LEN_ZERO___S 17 +#define PHYA_TXTD_ERROR_STATUS_L__TXTD_START_DONE___M 0x00010000 +#define PHYA_TXTD_ERROR_STATUS_L__TXTD_START_DONE___S 16 +#define PHYA_TXTD_ERROR_STATUS_L__TXTD_START_NONIDLE___M 0x00008000 +#define PHYA_TXTD_ERROR_STATUS_L__TXTD_START_NONIDLE___S 15 +#define PHYA_TXTD_ERROR_STATUS_L__TX_ABORT_NONIDLE___M 0x00004000 +#define PHYA_TXTD_ERROR_STATUS_L__TX_ABORT_NONIDLE___S 14 +#define PHYA_TXTD_ERROR_STATUS_L__TX_ABORT_DONE___M 0x00002000 +#define PHYA_TXTD_ERROR_STATUS_L__TX_ABORT_DONE___S 13 +#define PHYA_TXTD_ERROR_STATUS_L__TX_ABORT_IDLE___M 0x00001000 +#define PHYA_TXTD_ERROR_STATUS_L__TX_ABORT_IDLE___S 12 +#define PHYA_TXTD_ERROR_STATUS_L__TXTD_START_UNEXPECTED___M 0x00000800 +#define PHYA_TXTD_ERROR_STATUS_L__TXTD_START_UNEXPECTED___S 11 +#define PHYA_TXTD_ERROR_STATUS_L__TX_FRAME_UNEXPECTED___M 0x00000400 +#define PHYA_TXTD_ERROR_STATUS_L__TX_FRAME_UNEXPECTED___S 10 +#define PHYA_TXTD_ERROR_STATUS_L__TX_VLD_UNALIGN_ERROR___M 0x00000200 +#define PHYA_TXTD_ERROR_STATUS_L__TX_VLD_UNALIGN_ERROR___S 9 +#define PHYA_TXTD_ERROR_STATUS_L__PKT_END_ERROR___M 0x00000100 +#define PHYA_TXTD_ERROR_STATUS_L__PKT_END_ERROR___S 8 +#define PHYA_TXTD_ERROR_STATUS_L__PKT_DATA_ERROR___M 0x00000080 +#define PHYA_TXTD_ERROR_STATUS_L__PKT_DATA_ERROR___S 7 +#define PHYA_TXTD_ERROR_STATUS_L__PRE_DATA_ERROR___M 0x00000040 +#define PHYA_TXTD_ERROR_STATUS_L__PRE_DATA_ERROR___S 6 +#define PHYA_TXTD_ERROR_STATUS_L__MULTI_SYM_ERROR___M 0x00000020 +#define PHYA_TXTD_ERROR_STATUS_L__MULTI_SYM_ERROR___S 5 +#define PHYA_TXTD_ERROR_STATUS_L__SYM_ERROR___M 0x00000010 +#define PHYA_TXTD_ERROR_STATUS_L__SYM_ERROR___S 4 +#define PHYA_TXTD_ERROR_STATUS_L__TXTD_START_ERROR___M 0x00000008 +#define PHYA_TXTD_ERROR_STATUS_L__TXTD_START_ERROR___S 3 +#define PHYA_TXTD_ERROR_STATUS_L__PKT_START_ERROR___M 0x00000004 +#define PHYA_TXTD_ERROR_STATUS_L__PKT_START_ERROR___S 2 +#define PHYA_TXTD_ERROR_STATUS_L__TX_DESC_ERROR___M 0x00000002 +#define PHYA_TXTD_ERROR_STATUS_L__TX_DESC_ERROR___S 1 +#define PHYA_TXTD_ERROR_STATUS_L__TX_PRE_DESC_ERROR___M 0x00000001 +#define PHYA_TXTD_ERROR_STATUS_L__TX_PRE_DESC_ERROR___S 0 +#define PHYA_TXTD_ERROR_STATUS_L___M 0x00FFFFFF +#define PHYA_TXTD_ERROR_STATUS_L___S 0 + +#define PHYA_TXTD_ERROR_STATUS_U (0x003B003C) +#define PHYA_TXTD_ERROR_STATUS_U___RWC QCSR_REG_RO +#define PHYA_TXTD_ERROR_STATUS_U___POR 0x00000000 +#define PHYA_TXTD_ERROR_STATUS_U__ERROR_SPARE___POR 0x0000 +#define PHYA_TXTD_ERROR_STATUS_U__ERROR_SPARE___M 0x0000FFFF +#define PHYA_TXTD_ERROR_STATUS_U__ERROR_SPARE___S 0 +#define PHYA_TXTD_ERROR_STATUS_U___M 0x0000FFFF +#define PHYA_TXTD_ERROR_STATUS_U___S 0 + +#define PHYA_TXTD_ERROR_MASK_L (0x003B0040) +#define PHYA_TXTD_ERROR_MASK_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ERROR_MASK_L___POR 0x00FFFFFF +#define PHYA_TXTD_ERROR_MASK_L__FFT_ERROR_2_MASK___POR 0x1 +#define PHYA_TXTD_ERROR_MASK_L__FFT_ERROR_1_MASK___POR 0x1 +#define PHYA_TXTD_ERROR_MASK_L__FFT_ERROR_0_MASK___POR 0x1 +#define PHYA_TXTD_ERROR_MASK_L__CCK_TIMEOUT_MASK___POR 0x1 +#define PHYA_TXTD_ERROR_MASK_L__CCK_SAMPLE_OVERFLOW_MASK___POR 0x1 +#define PHYA_TXTD_ERROR_MASK_L__OFDM_SYM_MISMATCH_MASK___POR 0x1 +#define PHYA_TXTD_ERROR_MASK_L__ULD_SYM_CP_LEN_ZERO_MASK___POR 0x1 +#define PHYA_TXTD_ERROR_MASK_L__TXTD_START_DONE_MASK___POR 0x1 +#define PHYA_TXTD_ERROR_MASK_L__TXTD_START_NONIDLE_MASK___POR 0x1 +#define PHYA_TXTD_ERROR_MASK_L__TX_ABORT_NONIDLE_MASK___POR 0x1 +#define PHYA_TXTD_ERROR_MASK_L__TX_ABORT_DONE_MASK___POR 0x1 +#define PHYA_TXTD_ERROR_MASK_L__TX_ABORT_IDLE_MASK___POR 0x1 +#define PHYA_TXTD_ERROR_MASK_L__TXTD_START_UNEXPECTED_MASK___POR 0x1 +#define PHYA_TXTD_ERROR_MASK_L__TX_FRAME_UNEXPECTED_MASK___POR 0x1 +#define PHYA_TXTD_ERROR_MASK_L__TX_VLD_UNALIGN_ERROR_MASK___POR 0x1 +#define PHYA_TXTD_ERROR_MASK_L__PKT_END_ERROR_MASK___POR 0x1 +#define PHYA_TXTD_ERROR_MASK_L__PKT_DATA_ERROR_MASK___POR 0x1 +#define PHYA_TXTD_ERROR_MASK_L__PRE_DATA_ERROR_MASK___POR 0x1 +#define PHYA_TXTD_ERROR_MASK_L__MULTI_SYM_ERROR_MASK___POR 0x1 +#define PHYA_TXTD_ERROR_MASK_L__SYM_ERROR_MASK___POR 0x1 +#define PHYA_TXTD_ERROR_MASK_L__TXTD_START_ERROR_MASK___POR 0x1 +#define PHYA_TXTD_ERROR_MASK_L__PKT_START_ERROR_MASK___POR 0x1 +#define PHYA_TXTD_ERROR_MASK_L__TX_DESC_ERROR_MASK___POR 0x1 +#define PHYA_TXTD_ERROR_MASK_L__TX_PRE_DESC_ERROR_MASK___POR 0x1 +#define PHYA_TXTD_ERROR_MASK_L__FFT_ERROR_2_MASK___M 0x00800000 +#define PHYA_TXTD_ERROR_MASK_L__FFT_ERROR_2_MASK___S 23 +#define PHYA_TXTD_ERROR_MASK_L__FFT_ERROR_1_MASK___M 0x00400000 +#define PHYA_TXTD_ERROR_MASK_L__FFT_ERROR_1_MASK___S 22 +#define PHYA_TXTD_ERROR_MASK_L__FFT_ERROR_0_MASK___M 0x00200000 +#define PHYA_TXTD_ERROR_MASK_L__FFT_ERROR_0_MASK___S 21 +#define PHYA_TXTD_ERROR_MASK_L__CCK_TIMEOUT_MASK___M 0x00100000 +#define PHYA_TXTD_ERROR_MASK_L__CCK_TIMEOUT_MASK___S 20 +#define PHYA_TXTD_ERROR_MASK_L__CCK_SAMPLE_OVERFLOW_MASK___M 0x00080000 +#define PHYA_TXTD_ERROR_MASK_L__CCK_SAMPLE_OVERFLOW_MASK___S 19 +#define PHYA_TXTD_ERROR_MASK_L__OFDM_SYM_MISMATCH_MASK___M 0x00040000 +#define PHYA_TXTD_ERROR_MASK_L__OFDM_SYM_MISMATCH_MASK___S 18 +#define PHYA_TXTD_ERROR_MASK_L__ULD_SYM_CP_LEN_ZERO_MASK___M 0x00020000 +#define PHYA_TXTD_ERROR_MASK_L__ULD_SYM_CP_LEN_ZERO_MASK___S 17 +#define PHYA_TXTD_ERROR_MASK_L__TXTD_START_DONE_MASK___M 0x00010000 +#define PHYA_TXTD_ERROR_MASK_L__TXTD_START_DONE_MASK___S 16 +#define PHYA_TXTD_ERROR_MASK_L__TXTD_START_NONIDLE_MASK___M 0x00008000 +#define PHYA_TXTD_ERROR_MASK_L__TXTD_START_NONIDLE_MASK___S 15 +#define PHYA_TXTD_ERROR_MASK_L__TX_ABORT_NONIDLE_MASK___M 0x00004000 +#define PHYA_TXTD_ERROR_MASK_L__TX_ABORT_NONIDLE_MASK___S 14 +#define PHYA_TXTD_ERROR_MASK_L__TX_ABORT_DONE_MASK___M 0x00002000 +#define PHYA_TXTD_ERROR_MASK_L__TX_ABORT_DONE_MASK___S 13 +#define PHYA_TXTD_ERROR_MASK_L__TX_ABORT_IDLE_MASK___M 0x00001000 +#define PHYA_TXTD_ERROR_MASK_L__TX_ABORT_IDLE_MASK___S 12 +#define PHYA_TXTD_ERROR_MASK_L__TXTD_START_UNEXPECTED_MASK___M 0x00000800 +#define PHYA_TXTD_ERROR_MASK_L__TXTD_START_UNEXPECTED_MASK___S 11 +#define PHYA_TXTD_ERROR_MASK_L__TX_FRAME_UNEXPECTED_MASK___M 0x00000400 +#define PHYA_TXTD_ERROR_MASK_L__TX_FRAME_UNEXPECTED_MASK___S 10 +#define PHYA_TXTD_ERROR_MASK_L__TX_VLD_UNALIGN_ERROR_MASK___M 0x00000200 +#define PHYA_TXTD_ERROR_MASK_L__TX_VLD_UNALIGN_ERROR_MASK___S 9 +#define PHYA_TXTD_ERROR_MASK_L__PKT_END_ERROR_MASK___M 0x00000100 +#define PHYA_TXTD_ERROR_MASK_L__PKT_END_ERROR_MASK___S 8 +#define PHYA_TXTD_ERROR_MASK_L__PKT_DATA_ERROR_MASK___M 0x00000080 +#define PHYA_TXTD_ERROR_MASK_L__PKT_DATA_ERROR_MASK___S 7 +#define PHYA_TXTD_ERROR_MASK_L__PRE_DATA_ERROR_MASK___M 0x00000040 +#define PHYA_TXTD_ERROR_MASK_L__PRE_DATA_ERROR_MASK___S 6 +#define PHYA_TXTD_ERROR_MASK_L__MULTI_SYM_ERROR_MASK___M 0x00000020 +#define PHYA_TXTD_ERROR_MASK_L__MULTI_SYM_ERROR_MASK___S 5 +#define PHYA_TXTD_ERROR_MASK_L__SYM_ERROR_MASK___M 0x00000010 +#define PHYA_TXTD_ERROR_MASK_L__SYM_ERROR_MASK___S 4 +#define PHYA_TXTD_ERROR_MASK_L__TXTD_START_ERROR_MASK___M 0x00000008 +#define PHYA_TXTD_ERROR_MASK_L__TXTD_START_ERROR_MASK___S 3 +#define PHYA_TXTD_ERROR_MASK_L__PKT_START_ERROR_MASK___M 0x00000004 +#define PHYA_TXTD_ERROR_MASK_L__PKT_START_ERROR_MASK___S 2 +#define PHYA_TXTD_ERROR_MASK_L__TX_DESC_ERROR_MASK___M 0x00000002 +#define PHYA_TXTD_ERROR_MASK_L__TX_DESC_ERROR_MASK___S 1 +#define PHYA_TXTD_ERROR_MASK_L__TX_PRE_DESC_ERROR_MASK___M 0x00000001 +#define PHYA_TXTD_ERROR_MASK_L__TX_PRE_DESC_ERROR_MASK___S 0 +#define PHYA_TXTD_ERROR_MASK_L___M 0x00FFFFFF +#define PHYA_TXTD_ERROR_MASK_L___S 0 + +#define PHYA_TXTD_ERROR_MASK_U (0x003B0044) +#define PHYA_TXTD_ERROR_MASK_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ERROR_MASK_U___POR 0x0000FFFF +#define PHYA_TXTD_ERROR_MASK_U__ERROR_SPARE_MASK___POR 0xFFFF +#define PHYA_TXTD_ERROR_MASK_U__ERROR_SPARE_MASK___M 0x0000FFFF +#define PHYA_TXTD_ERROR_MASK_U__ERROR_SPARE_MASK___S 0 +#define PHYA_TXTD_ERROR_MASK_U___M 0x0000FFFF +#define PHYA_TXTD_ERROR_MASK_U___S 0 + +#define PHYA_TXTD_CORE_STATUS_L (0x003B0048) +#define PHYA_TXTD_CORE_STATUS_L___RWC QCSR_REG_RO +#define PHYA_TXTD_CORE_STATUS_L___POR 0x00000000 +#define PHYA_TXTD_CORE_STATUS_L__CSR_TXTD_CORE_STATUS_0___POR 0x00000000 +#define PHYA_TXTD_CORE_STATUS_L__CSR_TXTD_CORE_STATUS_0___M 0xFFFFFFFF +#define PHYA_TXTD_CORE_STATUS_L__CSR_TXTD_CORE_STATUS_0___S 0 +#define PHYA_TXTD_CORE_STATUS_L___M 0xFFFFFFFF +#define PHYA_TXTD_CORE_STATUS_L___S 0 + +#define PHYA_TXTD_CORE_STATUS_U (0x003B004C) +#define PHYA_TXTD_CORE_STATUS_U___RWC QCSR_REG_RO +#define PHYA_TXTD_CORE_STATUS_U___POR 0x00000000 +#define PHYA_TXTD_CORE_STATUS_U__CSR_TXTD_CORE_STATUS_1___POR 0x00000000 +#define PHYA_TXTD_CORE_STATUS_U__CSR_TXTD_CORE_STATUS_1___M 0xFFFFFFFF +#define PHYA_TXTD_CORE_STATUS_U__CSR_TXTD_CORE_STATUS_1___S 0 +#define PHYA_TXTD_CORE_STATUS_U___M 0xFFFFFFFF +#define PHYA_TXTD_CORE_STATUS_U___S 0 + +#define PHYA_TXTD_DATA_DUMP_CTRL_L (0x003B0050) +#define PHYA_TXTD_DATA_DUMP_CTRL_L___RWC QCSR_REG_RW +#define PHYA_TXTD_DATA_DUMP_CTRL_L___POR 0x0000000F +#define PHYA_TXTD_DATA_DUMP_CTRL_L__CSR_TXTD_DUMP_CHN0_SEL___POR 0x0 +#define PHYA_TXTD_DATA_DUMP_CTRL_L__CSR_TXTD_DUMP_PREC___POR 0x0 +#define PHYA_TXTD_DATA_DUMP_CTRL_L__CSR_TXTD_DUMP_MODE___POR 0x0 +#define PHYA_TXTD_DATA_DUMP_CTRL_L__CSR_TXTDP_DUMP_POINT___POR 0xF +#define PHYA_TXTD_DATA_DUMP_CTRL_L__CSR_TXTD_DUMP_CHN0_SEL___M 0x03000000 +#define PHYA_TXTD_DATA_DUMP_CTRL_L__CSR_TXTD_DUMP_CHN0_SEL___S 24 +#define PHYA_TXTD_DATA_DUMP_CTRL_L__CSR_TXTD_DUMP_PREC___M 0x00030000 +#define PHYA_TXTD_DATA_DUMP_CTRL_L__CSR_TXTD_DUMP_PREC___S 16 +#define PHYA_TXTD_DATA_DUMP_CTRL_L__CSR_TXTD_DUMP_MODE___M 0x00000700 +#define PHYA_TXTD_DATA_DUMP_CTRL_L__CSR_TXTD_DUMP_MODE___S 8 +#define PHYA_TXTD_DATA_DUMP_CTRL_L__CSR_TXTDP_DUMP_POINT___M 0x0000000F +#define PHYA_TXTD_DATA_DUMP_CTRL_L__CSR_TXTDP_DUMP_POINT___S 0 +#define PHYA_TXTD_DATA_DUMP_CTRL_L___M 0x0303070F +#define PHYA_TXTD_DATA_DUMP_CTRL_L___S 0 + +#define PHYA_TXTD_DATA_DUMP_CTRL_U (0x003B0054) +#define PHYA_TXTD_DATA_DUMP_CTRL_U___RWC QCSR_REG_RW +#define PHYA_TXTD_DATA_DUMP_CTRL_U___POR 0x00000000 +#define PHYA_TXTD_DATA_DUMP_CTRL_U__CSR_TXTD_DUMP_CHN1_SEL___POR 0x0 +#define PHYA_TXTD_DATA_DUMP_CTRL_U__CSR_TXTD_DUMP_CHN1_SEL___M 0x00000003 +#define PHYA_TXTD_DATA_DUMP_CTRL_U__CSR_TXTD_DUMP_CHN1_SEL___S 0 +#define PHYA_TXTD_DATA_DUMP_CTRL_U___M 0x00000003 +#define PHYA_TXTD_DATA_DUMP_CTRL_U___S 0 + +#define PHYA_TXTD_PUBLIC_SPARE_L (0x003B0058) +#define PHYA_TXTD_PUBLIC_SPARE_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PUBLIC_SPARE_L___POR 0x00000000 +#define PHYA_TXTD_PUBLIC_SPARE_L__PUBLIC_SPARE_0___POR 0x00000000 +#define PHYA_TXTD_PUBLIC_SPARE_L__PUBLIC_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXTD_PUBLIC_SPARE_L__PUBLIC_SPARE_0___S 0 +#define PHYA_TXTD_PUBLIC_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXTD_PUBLIC_SPARE_L___S 0 + +#define PHYA_TXTD_PUBLIC_SPARE_U (0x003B005C) +#define PHYA_TXTD_PUBLIC_SPARE_U___RWC QCSR_REG_RW +#define PHYA_TXTD_PUBLIC_SPARE_U___POR 0x00CC0000 +#define PHYA_TXTD_PUBLIC_SPARE_U__PUBLIC_SPARE_1___POR 0x00CC0000 +#define PHYA_TXTD_PUBLIC_SPARE_U__PUBLIC_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXTD_PUBLIC_SPARE_U__PUBLIC_SPARE_1___S 0 +#define PHYA_TXTD_PUBLIC_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXTD_PUBLIC_SPARE_U___S 0 + +#define PHYA_TXTD_TX_FIR_COEFF_MEM_L_n(n) (0x003B0060+0x8*(n)) +#define PHYA_TXTD_TX_FIR_COEFF_MEM_L_n_nMIN 0 +#define PHYA_TXTD_TX_FIR_COEFF_MEM_L_n_nMAX 0 +#define PHYA_TXTD_TX_FIR_COEFF_MEM_L_n_ELEM 1 +#define PHYA_TXTD_TX_FIR_COEFF_MEM_L_n___RWC QCSR_REG_RW +#define PHYA_TXTD_TX_FIR_COEFF_MEM_L_n___POR 0x00000000 +#define PHYA_TXTD_TX_FIR_COEFF_MEM_L_n__TX_FIR_COEFF_0___POR 0x0000000 +#define PHYA_TXTD_TX_FIR_COEFF_MEM_L_n__TX_FIR_COEFF_0___M 0x0FFFFFFF +#define PHYA_TXTD_TX_FIR_COEFF_MEM_L_n__TX_FIR_COEFF_0___S 0 +#define PHYA_TXTD_TX_FIR_COEFF_MEM_L_n___M 0x0FFFFFFF +#define PHYA_TXTD_TX_FIR_COEFF_MEM_L_n___S 0 +#define PHYA_TXTD_TX_FIR_COEFF_MEM_L_0 (0x003B0060) +#define PHYA_TXTD_TX_FIR_COEFF_MEM_L_0___RWC QCSR_REG_RW +#define PHYA_TXTD_TX_FIR_COEFF_MEM_L_0__TX_FIR_COEFF_0___M 0x0FFFFFFF +#define PHYA_TXTD_TX_FIR_COEFF_MEM_L_0__TX_FIR_COEFF_0___S 0 + +#define PHYA_TXTD_TX_FIR_COEFF_MEM_U_n(n) (0x003B0064+0x8*(n)) +#define PHYA_TXTD_TX_FIR_COEFF_MEM_U_n_nMIN 0 +#define PHYA_TXTD_TX_FIR_COEFF_MEM_U_n_nMAX 0 +#define PHYA_TXTD_TX_FIR_COEFF_MEM_U_n_ELEM 1 +#define PHYA_TXTD_TX_FIR_COEFF_MEM_U_n___RWC QCSR_REG_RW +#define PHYA_TXTD_TX_FIR_COEFF_MEM_U_n___POR 0x00000000 +#define PHYA_TXTD_TX_FIR_COEFF_MEM_U_n__TX_FIR_COEFF_1___POR 0x0000000 +#define PHYA_TXTD_TX_FIR_COEFF_MEM_U_n__TX_FIR_COEFF_1___M 0x0FFFFFFF +#define PHYA_TXTD_TX_FIR_COEFF_MEM_U_n__TX_FIR_COEFF_1___S 0 +#define PHYA_TXTD_TX_FIR_COEFF_MEM_U_n___M 0x0FFFFFFF +#define PHYA_TXTD_TX_FIR_COEFF_MEM_U_n___S 0 +#define PHYA_TXTD_TX_FIR_COEFF_MEM_U_0 (0x003B0064) +#define PHYA_TXTD_TX_FIR_COEFF_MEM_U_0___RWC QCSR_REG_RW +#define PHYA_TXTD_TX_FIR_COEFF_MEM_U_0__TX_FIR_COEFF_1___M 0x0FFFFFFF +#define PHYA_TXTD_TX_FIR_COEFF_MEM_U_0__TX_FIR_COEFF_1___S 0 + +#define PHYA_TXTD_CLOCK_GATING_0_L (0x003B0360) +#define PHYA_TXTD_CLOCK_GATING_0_L___RWC QCSR_REG_RW +#define PHYA_TXTD_CLOCK_GATING_0_L___POR 0x00000000 +#define PHYA_TXTD_CLOCK_GATING_0_L__CSR_DISABLE_CG_TXTD_CLKBWX4___POR 0x0 +#define PHYA_TXTD_CLOCK_GATING_0_L__CSR_DISABLE_CG_TXTD_CLKBWX4___M 0x00000001 +#define PHYA_TXTD_CLOCK_GATING_0_L__CSR_DISABLE_CG_TXTD_CLKBWX4___S 0 +#define PHYA_TXTD_CLOCK_GATING_0_L___M 0x00000001 +#define PHYA_TXTD_CLOCK_GATING_0_L___S 0 + +#define PHYA_TXTD_CLOCK_GATING_1_L (0x003B0368) +#define PHYA_TXTD_CLOCK_GATING_1_L___RWC QCSR_REG_RW +#define PHYA_TXTD_CLOCK_GATING_1_L___POR 0x00000000 +#define PHYA_TXTD_CLOCK_GATING_1_L__CSR_DISABLE_CG_TXTDP_CLKTDAC___POR 0x0 +#define PHYA_TXTD_CLOCK_GATING_1_L__CSR_DISABLE_CG_TXTDP_CLKBWX3___POR 0x0 +#define PHYA_TXTD_CLOCK_GATING_1_L__CSR_DISABLE_CG_TXTDP_CLKBWX4___POR 0x0 +#define PHYA_TXTD_CLOCK_GATING_1_L__CSR_DISABLE_CG_TXTD_CLKBWX3___POR 0x0 +#define PHYA_TXTD_CLOCK_GATING_1_L__CSR_DISABLE_CG_TXTDP_CLKTDAC___M 0x01000000 +#define PHYA_TXTD_CLOCK_GATING_1_L__CSR_DISABLE_CG_TXTDP_CLKTDAC___S 24 +#define PHYA_TXTD_CLOCK_GATING_1_L__CSR_DISABLE_CG_TXTDP_CLKBWX3___M 0x00010000 +#define PHYA_TXTD_CLOCK_GATING_1_L__CSR_DISABLE_CG_TXTDP_CLKBWX3___S 16 +#define PHYA_TXTD_CLOCK_GATING_1_L__CSR_DISABLE_CG_TXTDP_CLKBWX4___M 0x00000100 +#define PHYA_TXTD_CLOCK_GATING_1_L__CSR_DISABLE_CG_TXTDP_CLKBWX4___S 8 +#define PHYA_TXTD_CLOCK_GATING_1_L__CSR_DISABLE_CG_TXTD_CLKBWX3___M 0x00000001 +#define PHYA_TXTD_CLOCK_GATING_1_L__CSR_DISABLE_CG_TXTD_CLKBWX3___S 0 +#define PHYA_TXTD_CLOCK_GATING_1_L___M 0x01010101 +#define PHYA_TXTD_CLOCK_GATING_1_L___S 0 + +#define PHYA_TXTD_CLOCK_GATING_1_U (0x003B036C) +#define PHYA_TXTD_CLOCK_GATING_1_U___RWC QCSR_REG_RW +#define PHYA_TXTD_CLOCK_GATING_1_U___POR 0x00000000 +#define PHYA_TXTD_CLOCK_GATING_1_U__CSR_DISABLE_CG_FFT_CLK___POR 0x0 +#define PHYA_TXTD_CLOCK_GATING_1_U__CSR_ENA_DBG_CG___POR 0x0 +#define PHYA_TXTD_CLOCK_GATING_1_U__CSR_DISABLE_CG_FFT_CLK___M 0x00000300 +#define PHYA_TXTD_CLOCK_GATING_1_U__CSR_DISABLE_CG_FFT_CLK___S 8 +#define PHYA_TXTD_CLOCK_GATING_1_U__CSR_ENA_DBG_CG___M 0x00000001 +#define PHYA_TXTD_CLOCK_GATING_1_U__CSR_ENA_DBG_CG___S 0 +#define PHYA_TXTD_CLOCK_GATING_1_U___M 0x00000301 +#define PHYA_TXTD_CLOCK_GATING_1_U___S 0 + +#define PHYA_TXTD_GEN_CONTROLS_0_L (0x003B0370) +#define PHYA_TXTD_GEN_CONTROLS_0_L___RWC QCSR_REG_RW +#define PHYA_TXTD_GEN_CONTROLS_0_L___POR 0x00010300 +#define PHYA_TXTD_GEN_CONTROLS_0_L__ALT_DIG_MIX_MODE_165___POR 0x1 +#define PHYA_TXTD_GEN_CONTROLS_0_L__FFT_ERROR_MASK___POR 0x3 +#define PHYA_TXTD_GEN_CONTROLS_0_L__SPARE0___POR 0x0 +#define PHYA_TXTD_GEN_CONTROLS_0_L__ALT_DIG_MIX_MODE_165___M 0x00010000 +#define PHYA_TXTD_GEN_CONTROLS_0_L__ALT_DIG_MIX_MODE_165___S 16 +#define PHYA_TXTD_GEN_CONTROLS_0_L__FFT_ERROR_MASK___M 0x00000300 +#define PHYA_TXTD_GEN_CONTROLS_0_L__FFT_ERROR_MASK___S 8 +#define PHYA_TXTD_GEN_CONTROLS_0_L__SPARE0___M 0x00000007 +#define PHYA_TXTD_GEN_CONTROLS_0_L__SPARE0___S 0 +#define PHYA_TXTD_GEN_CONTROLS_0_L___M 0x00010307 +#define PHYA_TXTD_GEN_CONTROLS_0_L___S 0 + +#define PHYA_TXTD_GEN_CONTROLS_1_L (0x003B0378) +#define PHYA_TXTD_GEN_CONTROLS_1_L___RWC QCSR_REG_RW +#define PHYA_TXTD_GEN_CONTROLS_1_L___POR 0x00000100 +#define PHYA_TXTD_GEN_CONTROLS_1_L__EN_CSR_COPY___POR 0x1 +#define PHYA_TXTD_GEN_CONTROLS_1_L__TX_PHASE_JUMP_160___POR 0x00 +#define PHYA_TXTD_GEN_CONTROLS_1_L__EN_CSR_COPY___M 0x00000100 +#define PHYA_TXTD_GEN_CONTROLS_1_L__EN_CSR_COPY___S 8 +#define PHYA_TXTD_GEN_CONTROLS_1_L__TX_PHASE_JUMP_160___M 0x0000007F +#define PHYA_TXTD_GEN_CONTROLS_1_L__TX_PHASE_JUMP_160___S 0 +#define PHYA_TXTD_GEN_CONTROLS_1_L___M 0x0000017F +#define PHYA_TXTD_GEN_CONTROLS_1_L___S 0 + +#define PHYA_TXTD_GEN_CONTROLS_1_U (0x003B037C) +#define PHYA_TXTD_GEN_CONTROLS_1_U___RWC QCSR_REG_RW +#define PHYA_TXTD_GEN_CONTROLS_1_U___POR 0x0223001F +#define PHYA_TXTD_GEN_CONTROLS_1_U__USE_FW_PWR_COMP_FACTOR___POR 0x0 +#define PHYA_TXTD_GEN_CONTROLS_1_U__USE_FW_HEAVY_CLIP_FACTOR___POR 0x0 +#define PHYA_TXTD_GEN_CONTROLS_1_U__USE_FW_HEAVY_CLIP_EN___POR 0x0 +#define PHYA_TXTD_GEN_CONTROLS_1_U__USE_TXFD_HEAVY_CLIP_EN___POR 0x1 +#define PHYA_TXTD_GEN_CONTROLS_1_U__HEAVY_CLIP_EN_OFDMA___POR 0x0 +#define PHYA_TXTD_GEN_CONTROLS_1_U__HEAVY_CLIP_EN_MU___POR 0x0 +#define PHYA_TXTD_GEN_CONTROLS_1_U__HEAVY_CLIP_TXFIR_COEF_NSSTHRH___POR 0x2 +#define PHYA_TXTD_GEN_CONTROLS_1_U__HEAVY_CLIP_LITE_MCS_THR___POR 0x3 +#define PHYA_TXTD_GEN_CONTROLS_1_U__HEAVY_CLIP_VECTOR___POR 0x001F +#define PHYA_TXTD_GEN_CONTROLS_1_U__USE_FW_PWR_COMP_FACTOR___M 0x10000000 +#define PHYA_TXTD_GEN_CONTROLS_1_U__USE_FW_PWR_COMP_FACTOR___S 28 +#define PHYA_TXTD_GEN_CONTROLS_1_U__USE_FW_HEAVY_CLIP_FACTOR___M 0x08000000 +#define PHYA_TXTD_GEN_CONTROLS_1_U__USE_FW_HEAVY_CLIP_FACTOR___S 27 +#define PHYA_TXTD_GEN_CONTROLS_1_U__USE_FW_HEAVY_CLIP_EN___M 0x04000000 +#define PHYA_TXTD_GEN_CONTROLS_1_U__USE_FW_HEAVY_CLIP_EN___S 26 +#define PHYA_TXTD_GEN_CONTROLS_1_U__USE_TXFD_HEAVY_CLIP_EN___M 0x02000000 +#define PHYA_TXTD_GEN_CONTROLS_1_U__USE_TXFD_HEAVY_CLIP_EN___S 25 +#define PHYA_TXTD_GEN_CONTROLS_1_U__HEAVY_CLIP_EN_OFDMA___M 0x01000000 +#define PHYA_TXTD_GEN_CONTROLS_1_U__HEAVY_CLIP_EN_OFDMA___S 24 +#define PHYA_TXTD_GEN_CONTROLS_1_U__HEAVY_CLIP_EN_MU___M 0x00800000 +#define PHYA_TXTD_GEN_CONTROLS_1_U__HEAVY_CLIP_EN_MU___S 23 +#define PHYA_TXTD_GEN_CONTROLS_1_U__HEAVY_CLIP_TXFIR_COEF_NSSTHRH___M 0x00700000 +#define PHYA_TXTD_GEN_CONTROLS_1_U__HEAVY_CLIP_TXFIR_COEF_NSSTHRH___S 20 +#define PHYA_TXTD_GEN_CONTROLS_1_U__HEAVY_CLIP_LITE_MCS_THR___M 0x000F0000 +#define PHYA_TXTD_GEN_CONTROLS_1_U__HEAVY_CLIP_LITE_MCS_THR___S 16 +#define PHYA_TXTD_GEN_CONTROLS_1_U__HEAVY_CLIP_VECTOR___M 0x0000FFFF +#define PHYA_TXTD_GEN_CONTROLS_1_U__HEAVY_CLIP_VECTOR___S 0 +#define PHYA_TXTD_GEN_CONTROLS_1_U___M 0x1FFFFFFF +#define PHYA_TXTD_GEN_CONTROLS_1_U___S 0 + +#define PHYA_TXTD_TX_VSRC_GAIN_L (0x003B0380) +#define PHYA_TXTD_TX_VSRC_GAIN_L___RWC QCSR_REG_RW +#define PHYA_TXTD_TX_VSRC_GAIN_L___POR 0x00000030 +#define PHYA_TXTD_TX_VSRC_GAIN_L__CSR_TX_VSRC_GAIN___POR 0x30 +#define PHYA_TXTD_TX_VSRC_GAIN_L__CSR_TX_VSRC_GAIN___M 0x000000FF +#define PHYA_TXTD_TX_VSRC_GAIN_L__CSR_TX_VSRC_GAIN___S 0 +#define PHYA_TXTD_TX_VSRC_GAIN_L___M 0x000000FF +#define PHYA_TXTD_TX_VSRC_GAIN_L___S 0 + +#define PHYA_TXTD_PHYDBG_L (0x003B0388) +#define PHYA_TXTD_PHYDBG_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PHYDBG_L___POR 0x0000000F +#define PHYA_TXTD_PHYDBG_L__PHYDBG_MODE___POR 0xF +#define PHYA_TXTD_PHYDBG_L__PHYDBG_MODE___M 0x0000000F +#define PHYA_TXTD_PHYDBG_L__PHYDBG_MODE___S 0 +#define PHYA_TXTD_PHYDBG_L___M 0x0000000F +#define PHYA_TXTD_PHYDBG_L___S 0 + +#define PHYA_TXTD_PRETXFIR0_COEFF0_L (0x003B0390) +#define PHYA_TXTD_PRETXFIR0_COEFF0_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PRETXFIR0_COEFF0_L___POR 0x00000000 +#define PHYA_TXTD_PRETXFIR0_COEFF0_L__PRETXFIR0_COEFF_1_0___POR 0x000 +#define PHYA_TXTD_PRETXFIR0_COEFF0_L__PRETXFIR0_COEFF_0_0___POR 0x000 +#define PHYA_TXTD_PRETXFIR0_COEFF0_L__PRETXFIR0_COEFF_1_0___M 0x03FF0000 +#define PHYA_TXTD_PRETXFIR0_COEFF0_L__PRETXFIR0_COEFF_1_0___S 16 +#define PHYA_TXTD_PRETXFIR0_COEFF0_L__PRETXFIR0_COEFF_0_0___M 0x000003FF +#define PHYA_TXTD_PRETXFIR0_COEFF0_L__PRETXFIR0_COEFF_0_0___S 0 +#define PHYA_TXTD_PRETXFIR0_COEFF0_L___M 0x03FF03FF +#define PHYA_TXTD_PRETXFIR0_COEFF0_L___S 0 + +#define PHYA_TXTD_PRETXFIR0_COEFF0_U (0x003B0394) +#define PHYA_TXTD_PRETXFIR0_COEFF0_U___RWC QCSR_REG_RW +#define PHYA_TXTD_PRETXFIR0_COEFF0_U___POR 0x03FA0000 +#define PHYA_TXTD_PRETXFIR0_COEFF0_U__PRETXFIR0_COEFF_3_0___POR 0x3FA +#define PHYA_TXTD_PRETXFIR0_COEFF0_U__PRETXFIR0_COEFF_2_0___POR 0x000 +#define PHYA_TXTD_PRETXFIR0_COEFF0_U__PRETXFIR0_COEFF_3_0___M 0x03FF0000 +#define PHYA_TXTD_PRETXFIR0_COEFF0_U__PRETXFIR0_COEFF_3_0___S 16 +#define PHYA_TXTD_PRETXFIR0_COEFF0_U__PRETXFIR0_COEFF_2_0___M 0x000003FF +#define PHYA_TXTD_PRETXFIR0_COEFF0_U__PRETXFIR0_COEFF_2_0___S 0 +#define PHYA_TXTD_PRETXFIR0_COEFF0_U___M 0x03FF03FF +#define PHYA_TXTD_PRETXFIR0_COEFF0_U___S 0 + +#define PHYA_TXTD_PRETXFIR0_COEFF1_L (0x003B0398) +#define PHYA_TXTD_PRETXFIR0_COEFF1_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PRETXFIR0_COEFF1_L___POR 0x0041001C +#define PHYA_TXTD_PRETXFIR0_COEFF1_L__PRETXFIR0_COEFF_1_1___POR 0x041 +#define PHYA_TXTD_PRETXFIR0_COEFF1_L__PRETXFIR0_COEFF_0_1___POR 0x01C +#define PHYA_TXTD_PRETXFIR0_COEFF1_L__PRETXFIR0_COEFF_1_1___M 0x03FF0000 +#define PHYA_TXTD_PRETXFIR0_COEFF1_L__PRETXFIR0_COEFF_1_1___S 16 +#define PHYA_TXTD_PRETXFIR0_COEFF1_L__PRETXFIR0_COEFF_0_1___M 0x000003FF +#define PHYA_TXTD_PRETXFIR0_COEFF1_L__PRETXFIR0_COEFF_0_1___S 0 +#define PHYA_TXTD_PRETXFIR0_COEFF1_L___M 0x03FF03FF +#define PHYA_TXTD_PRETXFIR0_COEFF1_L___S 0 + +#define PHYA_TXTD_PRETXFIR0_COEFF1_U (0x003B039C) +#define PHYA_TXTD_PRETXFIR0_COEFF1_U___RWC QCSR_REG_RW +#define PHYA_TXTD_PRETXFIR0_COEFF1_U___POR 0x00410052 +#define PHYA_TXTD_PRETXFIR0_COEFF1_U__PRETXFIR0_COEFF_3_1___POR 0x041 +#define PHYA_TXTD_PRETXFIR0_COEFF1_U__PRETXFIR0_COEFF_2_1___POR 0x052 +#define PHYA_TXTD_PRETXFIR0_COEFF1_U__PRETXFIR0_COEFF_3_1___M 0x03FF0000 +#define PHYA_TXTD_PRETXFIR0_COEFF1_U__PRETXFIR0_COEFF_3_1___S 16 +#define PHYA_TXTD_PRETXFIR0_COEFF1_U__PRETXFIR0_COEFF_2_1___M 0x000003FF +#define PHYA_TXTD_PRETXFIR0_COEFF1_U__PRETXFIR0_COEFF_2_1___S 0 +#define PHYA_TXTD_PRETXFIR0_COEFF1_U___M 0x03FF03FF +#define PHYA_TXTD_PRETXFIR0_COEFF1_U___S 0 + +#define PHYA_TXTD_PRETXFIR0_COEFF2_L (0x003B03A0) +#define PHYA_TXTD_PRETXFIR0_COEFF2_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PRETXFIR0_COEFF2_L___POR 0x03FA001C +#define PHYA_TXTD_PRETXFIR0_COEFF2_L__PRETXFIR0_COEFF_1_2___POR 0x3FA +#define PHYA_TXTD_PRETXFIR0_COEFF2_L__PRETXFIR0_COEFF_0_2___POR 0x01C +#define PHYA_TXTD_PRETXFIR0_COEFF2_L__PRETXFIR0_COEFF_1_2___M 0x03FF0000 +#define PHYA_TXTD_PRETXFIR0_COEFF2_L__PRETXFIR0_COEFF_1_2___S 16 +#define PHYA_TXTD_PRETXFIR0_COEFF2_L__PRETXFIR0_COEFF_0_2___M 0x000003FF +#define PHYA_TXTD_PRETXFIR0_COEFF2_L__PRETXFIR0_COEFF_0_2___S 0 +#define PHYA_TXTD_PRETXFIR0_COEFF2_L___M 0x03FF03FF +#define PHYA_TXTD_PRETXFIR0_COEFF2_L___S 0 + +#define PHYA_TXTD_PRETXFIR0_COEFF2_U (0x003B03A4) +#define PHYA_TXTD_PRETXFIR0_COEFF2_U___RWC QCSR_REG_RW +#define PHYA_TXTD_PRETXFIR0_COEFF2_U___POR 0x00000000 +#define PHYA_TXTD_PRETXFIR0_COEFF2_U__PRETXFIR0_COEFF_3_2___POR 0x000 +#define PHYA_TXTD_PRETXFIR0_COEFF2_U__PRETXFIR0_COEFF_2_2___POR 0x000 +#define PHYA_TXTD_PRETXFIR0_COEFF2_U__PRETXFIR0_COEFF_3_2___M 0x03FF0000 +#define PHYA_TXTD_PRETXFIR0_COEFF2_U__PRETXFIR0_COEFF_3_2___S 16 +#define PHYA_TXTD_PRETXFIR0_COEFF2_U__PRETXFIR0_COEFF_2_2___M 0x000003FF +#define PHYA_TXTD_PRETXFIR0_COEFF2_U__PRETXFIR0_COEFF_2_2___S 0 +#define PHYA_TXTD_PRETXFIR0_COEFF2_U___M 0x03FF03FF +#define PHYA_TXTD_PRETXFIR0_COEFF2_U___S 0 + +#define PHYA_TXTD_PRETXFIR0_COEFF3_L (0x003B03A8) +#define PHYA_TXTD_PRETXFIR0_COEFF3_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PRETXFIR0_COEFF3_L___POR 0x00000000 +#define PHYA_TXTD_PRETXFIR0_COEFF3_L__PRETXFIR0_COEFF_1_3___POR 0x000 +#define PHYA_TXTD_PRETXFIR0_COEFF3_L__PRETXFIR0_COEFF_0_3___POR 0x000 +#define PHYA_TXTD_PRETXFIR0_COEFF3_L__PRETXFIR0_COEFF_1_3___M 0x03FF0000 +#define PHYA_TXTD_PRETXFIR0_COEFF3_L__PRETXFIR0_COEFF_1_3___S 16 +#define PHYA_TXTD_PRETXFIR0_COEFF3_L__PRETXFIR0_COEFF_0_3___M 0x000003FF +#define PHYA_TXTD_PRETXFIR0_COEFF3_L__PRETXFIR0_COEFF_0_3___S 0 +#define PHYA_TXTD_PRETXFIR0_COEFF3_L___M 0x03FF03FF +#define PHYA_TXTD_PRETXFIR0_COEFF3_L___S 0 + +#define PHYA_TXTD_PRETXFIR0_COEFF3_U (0x003B03AC) +#define PHYA_TXTD_PRETXFIR0_COEFF3_U___RWC QCSR_REG_RW +#define PHYA_TXTD_PRETXFIR0_COEFF3_U___POR 0x00000000 +#define PHYA_TXTD_PRETXFIR0_COEFF3_U__PRETXFIR0_COEFF_3_3___POR 0x000 +#define PHYA_TXTD_PRETXFIR0_COEFF3_U__PRETXFIR0_COEFF_2_3___POR 0x000 +#define PHYA_TXTD_PRETXFIR0_COEFF3_U__PRETXFIR0_COEFF_3_3___M 0x03FF0000 +#define PHYA_TXTD_PRETXFIR0_COEFF3_U__PRETXFIR0_COEFF_3_3___S 16 +#define PHYA_TXTD_PRETXFIR0_COEFF3_U__PRETXFIR0_COEFF_2_3___M 0x000003FF +#define PHYA_TXTD_PRETXFIR0_COEFF3_U__PRETXFIR0_COEFF_2_3___S 0 +#define PHYA_TXTD_PRETXFIR0_COEFF3_U___M 0x03FF03FF +#define PHYA_TXTD_PRETXFIR0_COEFF3_U___S 0 + +#define PHYA_TXTD_PRETXFIR1_COEFF0_L (0x003B03B0) +#define PHYA_TXTD_PRETXFIR1_COEFF0_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PRETXFIR1_COEFF0_L___POR 0x03F303FC +#define PHYA_TXTD_PRETXFIR1_COEFF0_L__PRETXFIR1_COEFF_1_0___POR 0x3F3 +#define PHYA_TXTD_PRETXFIR1_COEFF0_L__PRETXFIR1_COEFF_0_0___POR 0x3FC +#define PHYA_TXTD_PRETXFIR1_COEFF0_L__PRETXFIR1_COEFF_1_0___M 0x03FF0000 +#define PHYA_TXTD_PRETXFIR1_COEFF0_L__PRETXFIR1_COEFF_1_0___S 16 +#define PHYA_TXTD_PRETXFIR1_COEFF0_L__PRETXFIR1_COEFF_0_0___M 0x000003FF +#define PHYA_TXTD_PRETXFIR1_COEFF0_L__PRETXFIR1_COEFF_0_0___S 0 +#define PHYA_TXTD_PRETXFIR1_COEFF0_L___M 0x03FF03FF +#define PHYA_TXTD_PRETXFIR1_COEFF0_L___S 0 + +#define PHYA_TXTD_PRETXFIR1_COEFF0_U (0x003B03B4) +#define PHYA_TXTD_PRETXFIR1_COEFF0_U___RWC QCSR_REG_RW +#define PHYA_TXTD_PRETXFIR1_COEFF0_U___POR 0x000103EF +#define PHYA_TXTD_PRETXFIR1_COEFF0_U__PRETXFIR1_COEFF_3_0___POR 0x001 +#define PHYA_TXTD_PRETXFIR1_COEFF0_U__PRETXFIR1_COEFF_2_0___POR 0x3EF +#define PHYA_TXTD_PRETXFIR1_COEFF0_U__PRETXFIR1_COEFF_3_0___M 0x03FF0000 +#define PHYA_TXTD_PRETXFIR1_COEFF0_U__PRETXFIR1_COEFF_3_0___S 16 +#define PHYA_TXTD_PRETXFIR1_COEFF0_U__PRETXFIR1_COEFF_2_0___M 0x000003FF +#define PHYA_TXTD_PRETXFIR1_COEFF0_U__PRETXFIR1_COEFF_2_0___S 0 +#define PHYA_TXTD_PRETXFIR1_COEFF0_U___M 0x03FF03FF +#define PHYA_TXTD_PRETXFIR1_COEFF0_U___S 0 + +#define PHYA_TXTD_PRETXFIR1_COEFF1_L (0x003B03B8) +#define PHYA_TXTD_PRETXFIR1_COEFF1_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PRETXFIR1_COEFF1_L___POR 0x004C0026 +#define PHYA_TXTD_PRETXFIR1_COEFF1_L__PRETXFIR1_COEFF_1_1___POR 0x04C +#define PHYA_TXTD_PRETXFIR1_COEFF1_L__PRETXFIR1_COEFF_0_1___POR 0x026 +#define PHYA_TXTD_PRETXFIR1_COEFF1_L__PRETXFIR1_COEFF_1_1___M 0x03FF0000 +#define PHYA_TXTD_PRETXFIR1_COEFF1_L__PRETXFIR1_COEFF_1_1___S 16 +#define PHYA_TXTD_PRETXFIR1_COEFF1_L__PRETXFIR1_COEFF_0_1___M 0x000003FF +#define PHYA_TXTD_PRETXFIR1_COEFF1_L__PRETXFIR1_COEFF_0_1___S 0 +#define PHYA_TXTD_PRETXFIR1_COEFF1_L___M 0x03FF03FF +#define PHYA_TXTD_PRETXFIR1_COEFF1_L___S 0 + +#define PHYA_TXTD_PRETXFIR1_COEFF1_U (0x003B03BC) +#define PHYA_TXTD_PRETXFIR1_COEFF1_U___RWC QCSR_REG_RW +#define PHYA_TXTD_PRETXFIR1_COEFF1_U___POR 0x004C005D +#define PHYA_TXTD_PRETXFIR1_COEFF1_U__PRETXFIR1_COEFF_3_1___POR 0x04C +#define PHYA_TXTD_PRETXFIR1_COEFF1_U__PRETXFIR1_COEFF_2_1___POR 0x05D +#define PHYA_TXTD_PRETXFIR1_COEFF1_U__PRETXFIR1_COEFF_3_1___M 0x03FF0000 +#define PHYA_TXTD_PRETXFIR1_COEFF1_U__PRETXFIR1_COEFF_3_1___S 16 +#define PHYA_TXTD_PRETXFIR1_COEFF1_U__PRETXFIR1_COEFF_2_1___M 0x000003FF +#define PHYA_TXTD_PRETXFIR1_COEFF1_U__PRETXFIR1_COEFF_2_1___S 0 +#define PHYA_TXTD_PRETXFIR1_COEFF1_U___M 0x03FF03FF +#define PHYA_TXTD_PRETXFIR1_COEFF1_U___S 0 + +#define PHYA_TXTD_PRETXFIR1_COEFF2_L (0x003B03C0) +#define PHYA_TXTD_PRETXFIR1_COEFF2_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PRETXFIR1_COEFF2_L___POR 0x00010026 +#define PHYA_TXTD_PRETXFIR1_COEFF2_L__PRETXFIR1_COEFF_1_2___POR 0x001 +#define PHYA_TXTD_PRETXFIR1_COEFF2_L__PRETXFIR1_COEFF_0_2___POR 0x026 +#define PHYA_TXTD_PRETXFIR1_COEFF2_L__PRETXFIR1_COEFF_1_2___M 0x03FF0000 +#define PHYA_TXTD_PRETXFIR1_COEFF2_L__PRETXFIR1_COEFF_1_2___S 16 +#define PHYA_TXTD_PRETXFIR1_COEFF2_L__PRETXFIR1_COEFF_0_2___M 0x000003FF +#define PHYA_TXTD_PRETXFIR1_COEFF2_L__PRETXFIR1_COEFF_0_2___S 0 +#define PHYA_TXTD_PRETXFIR1_COEFF2_L___M 0x03FF03FF +#define PHYA_TXTD_PRETXFIR1_COEFF2_L___S 0 + +#define PHYA_TXTD_PRETXFIR1_COEFF2_U (0x003B03C4) +#define PHYA_TXTD_PRETXFIR1_COEFF2_U___RWC QCSR_REG_RW +#define PHYA_TXTD_PRETXFIR1_COEFF2_U___POR 0x03F303EF +#define PHYA_TXTD_PRETXFIR1_COEFF2_U__PRETXFIR1_COEFF_3_2___POR 0x3F3 +#define PHYA_TXTD_PRETXFIR1_COEFF2_U__PRETXFIR1_COEFF_2_2___POR 0x3EF +#define PHYA_TXTD_PRETXFIR1_COEFF2_U__PRETXFIR1_COEFF_3_2___M 0x03FF0000 +#define PHYA_TXTD_PRETXFIR1_COEFF2_U__PRETXFIR1_COEFF_3_2___S 16 +#define PHYA_TXTD_PRETXFIR1_COEFF2_U__PRETXFIR1_COEFF_2_2___M 0x000003FF +#define PHYA_TXTD_PRETXFIR1_COEFF2_U__PRETXFIR1_COEFF_2_2___S 0 +#define PHYA_TXTD_PRETXFIR1_COEFF2_U___M 0x03FF03FF +#define PHYA_TXTD_PRETXFIR1_COEFF2_U___S 0 + +#define PHYA_TXTD_PRETXFIR1_COEFF3_L (0x003B03C8) +#define PHYA_TXTD_PRETXFIR1_COEFF3_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PRETXFIR1_COEFF3_L___POR 0x000003FC +#define PHYA_TXTD_PRETXFIR1_COEFF3_L__PRETXFIR1_COEFF_1_3___POR 0x000 +#define PHYA_TXTD_PRETXFIR1_COEFF3_L__PRETXFIR1_COEFF_0_3___POR 0x3FC +#define PHYA_TXTD_PRETXFIR1_COEFF3_L__PRETXFIR1_COEFF_1_3___M 0x03FF0000 +#define PHYA_TXTD_PRETXFIR1_COEFF3_L__PRETXFIR1_COEFF_1_3___S 16 +#define PHYA_TXTD_PRETXFIR1_COEFF3_L__PRETXFIR1_COEFF_0_3___M 0x000003FF +#define PHYA_TXTD_PRETXFIR1_COEFF3_L__PRETXFIR1_COEFF_0_3___S 0 +#define PHYA_TXTD_PRETXFIR1_COEFF3_L___M 0x03FF03FF +#define PHYA_TXTD_PRETXFIR1_COEFF3_L___S 0 + +#define PHYA_TXTD_PRETXFIR1_COEFF3_U (0x003B03CC) +#define PHYA_TXTD_PRETXFIR1_COEFF3_U___RWC QCSR_REG_RW +#define PHYA_TXTD_PRETXFIR1_COEFF3_U___POR 0x00000000 +#define PHYA_TXTD_PRETXFIR1_COEFF3_U__PRETXFIR1_COEFF_3_3___POR 0x000 +#define PHYA_TXTD_PRETXFIR1_COEFF3_U__PRETXFIR1_COEFF_2_3___POR 0x000 +#define PHYA_TXTD_PRETXFIR1_COEFF3_U__PRETXFIR1_COEFF_3_3___M 0x03FF0000 +#define PHYA_TXTD_PRETXFIR1_COEFF3_U__PRETXFIR1_COEFF_3_3___S 16 +#define PHYA_TXTD_PRETXFIR1_COEFF3_U__PRETXFIR1_COEFF_2_3___M 0x000003FF +#define PHYA_TXTD_PRETXFIR1_COEFF3_U__PRETXFIR1_COEFF_2_3___S 0 +#define PHYA_TXTD_PRETXFIR1_COEFF3_U___M 0x03FF03FF +#define PHYA_TXTD_PRETXFIR1_COEFF3_U___S 0 + +#define PHYA_TXTD_PRETXFIR2_COEFF0_L (0x003B03D0) +#define PHYA_TXTD_PRETXFIR2_COEFF0_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PRETXFIR2_COEFF0_L___POR 0x03EE03F9 +#define PHYA_TXTD_PRETXFIR2_COEFF0_L__PRETXFIR2_COEFF_1_0___POR 0x3EE +#define PHYA_TXTD_PRETXFIR2_COEFF0_L__PRETXFIR2_COEFF_0_0___POR 0x3F9 +#define PHYA_TXTD_PRETXFIR2_COEFF0_L__PRETXFIR2_COEFF_1_0___M 0x03FF0000 +#define PHYA_TXTD_PRETXFIR2_COEFF0_L__PRETXFIR2_COEFF_1_0___S 16 +#define PHYA_TXTD_PRETXFIR2_COEFF0_L__PRETXFIR2_COEFF_0_0___M 0x000003FF +#define PHYA_TXTD_PRETXFIR2_COEFF0_L__PRETXFIR2_COEFF_0_0___S 0 +#define PHYA_TXTD_PRETXFIR2_COEFF0_L___M 0x03FF03FF +#define PHYA_TXTD_PRETXFIR2_COEFF0_L___S 0 + +#define PHYA_TXTD_PRETXFIR2_COEFF0_U (0x003B03D4) +#define PHYA_TXTD_PRETXFIR2_COEFF0_U___RWC QCSR_REG_RW +#define PHYA_TXTD_PRETXFIR2_COEFF0_U___POR 0x000403F2 +#define PHYA_TXTD_PRETXFIR2_COEFF0_U__PRETXFIR2_COEFF_3_0___POR 0x004 +#define PHYA_TXTD_PRETXFIR2_COEFF0_U__PRETXFIR2_COEFF_2_0___POR 0x3F2 +#define PHYA_TXTD_PRETXFIR2_COEFF0_U__PRETXFIR2_COEFF_3_0___M 0x03FF0000 +#define PHYA_TXTD_PRETXFIR2_COEFF0_U__PRETXFIR2_COEFF_3_0___S 16 +#define PHYA_TXTD_PRETXFIR2_COEFF0_U__PRETXFIR2_COEFF_2_0___M 0x000003FF +#define PHYA_TXTD_PRETXFIR2_COEFF0_U__PRETXFIR2_COEFF_2_0___S 0 +#define PHYA_TXTD_PRETXFIR2_COEFF0_U___M 0x03FF03FF +#define PHYA_TXTD_PRETXFIR2_COEFF0_U___S 0 + +#define PHYA_TXTD_PRETXFIR2_COEFF1_L (0x003B03D8) +#define PHYA_TXTD_PRETXFIR2_COEFF1_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PRETXFIR2_COEFF1_L___POR 0x004C0029 +#define PHYA_TXTD_PRETXFIR2_COEFF1_L__PRETXFIR2_COEFF_1_1___POR 0x04C +#define PHYA_TXTD_PRETXFIR2_COEFF1_L__PRETXFIR2_COEFF_0_1___POR 0x029 +#define PHYA_TXTD_PRETXFIR2_COEFF1_L__PRETXFIR2_COEFF_1_1___M 0x03FF0000 +#define PHYA_TXTD_PRETXFIR2_COEFF1_L__PRETXFIR2_COEFF_1_1___S 16 +#define PHYA_TXTD_PRETXFIR2_COEFF1_L__PRETXFIR2_COEFF_0_1___M 0x000003FF +#define PHYA_TXTD_PRETXFIR2_COEFF1_L__PRETXFIR2_COEFF_0_1___S 0 +#define PHYA_TXTD_PRETXFIR2_COEFF1_L___M 0x03FF03FF +#define PHYA_TXTD_PRETXFIR2_COEFF1_L___S 0 + +#define PHYA_TXTD_PRETXFIR2_COEFF1_U (0x003B03DC) +#define PHYA_TXTD_PRETXFIR2_COEFF1_U___RWC QCSR_REG_RW +#define PHYA_TXTD_PRETXFIR2_COEFF1_U___POR 0x004C005C +#define PHYA_TXTD_PRETXFIR2_COEFF1_U__PRETXFIR2_COEFF_3_1___POR 0x04C +#define PHYA_TXTD_PRETXFIR2_COEFF1_U__PRETXFIR2_COEFF_2_1___POR 0x05C +#define PHYA_TXTD_PRETXFIR2_COEFF1_U__PRETXFIR2_COEFF_3_1___M 0x03FF0000 +#define PHYA_TXTD_PRETXFIR2_COEFF1_U__PRETXFIR2_COEFF_3_1___S 16 +#define PHYA_TXTD_PRETXFIR2_COEFF1_U__PRETXFIR2_COEFF_2_1___M 0x000003FF +#define PHYA_TXTD_PRETXFIR2_COEFF1_U__PRETXFIR2_COEFF_2_1___S 0 +#define PHYA_TXTD_PRETXFIR2_COEFF1_U___M 0x03FF03FF +#define PHYA_TXTD_PRETXFIR2_COEFF1_U___S 0 + +#define PHYA_TXTD_PRETXFIR2_COEFF2_L (0x003B03E0) +#define PHYA_TXTD_PRETXFIR2_COEFF2_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PRETXFIR2_COEFF2_L___POR 0x00040029 +#define PHYA_TXTD_PRETXFIR2_COEFF2_L__PRETXFIR2_COEFF_1_2___POR 0x004 +#define PHYA_TXTD_PRETXFIR2_COEFF2_L__PRETXFIR2_COEFF_0_2___POR 0x029 +#define PHYA_TXTD_PRETXFIR2_COEFF2_L__PRETXFIR2_COEFF_1_2___M 0x03FF0000 +#define PHYA_TXTD_PRETXFIR2_COEFF2_L__PRETXFIR2_COEFF_1_2___S 16 +#define PHYA_TXTD_PRETXFIR2_COEFF2_L__PRETXFIR2_COEFF_0_2___M 0x000003FF +#define PHYA_TXTD_PRETXFIR2_COEFF2_L__PRETXFIR2_COEFF_0_2___S 0 +#define PHYA_TXTD_PRETXFIR2_COEFF2_L___M 0x03FF03FF +#define PHYA_TXTD_PRETXFIR2_COEFF2_L___S 0 + +#define PHYA_TXTD_PRETXFIR2_COEFF2_U (0x003B03E4) +#define PHYA_TXTD_PRETXFIR2_COEFF2_U___RWC QCSR_REG_RW +#define PHYA_TXTD_PRETXFIR2_COEFF2_U___POR 0x03EE03F2 +#define PHYA_TXTD_PRETXFIR2_COEFF2_U__PRETXFIR2_COEFF_3_2___POR 0x3EE +#define PHYA_TXTD_PRETXFIR2_COEFF2_U__PRETXFIR2_COEFF_2_2___POR 0x3F2 +#define PHYA_TXTD_PRETXFIR2_COEFF2_U__PRETXFIR2_COEFF_3_2___M 0x03FF0000 +#define PHYA_TXTD_PRETXFIR2_COEFF2_U__PRETXFIR2_COEFF_3_2___S 16 +#define PHYA_TXTD_PRETXFIR2_COEFF2_U__PRETXFIR2_COEFF_2_2___M 0x000003FF +#define PHYA_TXTD_PRETXFIR2_COEFF2_U__PRETXFIR2_COEFF_2_2___S 0 +#define PHYA_TXTD_PRETXFIR2_COEFF2_U___M 0x03FF03FF +#define PHYA_TXTD_PRETXFIR2_COEFF2_U___S 0 + +#define PHYA_TXTD_PRETXFIR2_COEFF3_L (0x003B03E8) +#define PHYA_TXTD_PRETXFIR2_COEFF3_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PRETXFIR2_COEFF3_L___POR 0x000003F9 +#define PHYA_TXTD_PRETXFIR2_COEFF3_L__PRETXFIR2_COEFF_1_3___POR 0x000 +#define PHYA_TXTD_PRETXFIR2_COEFF3_L__PRETXFIR2_COEFF_0_3___POR 0x3F9 +#define PHYA_TXTD_PRETXFIR2_COEFF3_L__PRETXFIR2_COEFF_1_3___M 0x03FF0000 +#define PHYA_TXTD_PRETXFIR2_COEFF3_L__PRETXFIR2_COEFF_1_3___S 16 +#define PHYA_TXTD_PRETXFIR2_COEFF3_L__PRETXFIR2_COEFF_0_3___M 0x000003FF +#define PHYA_TXTD_PRETXFIR2_COEFF3_L__PRETXFIR2_COEFF_0_3___S 0 +#define PHYA_TXTD_PRETXFIR2_COEFF3_L___M 0x03FF03FF +#define PHYA_TXTD_PRETXFIR2_COEFF3_L___S 0 + +#define PHYA_TXTD_PRETXFIR2_COEFF3_U (0x003B03EC) +#define PHYA_TXTD_PRETXFIR2_COEFF3_U___RWC QCSR_REG_RW +#define PHYA_TXTD_PRETXFIR2_COEFF3_U___POR 0x00000000 +#define PHYA_TXTD_PRETXFIR2_COEFF3_U__PRETXFIR2_COEFF_3_3___POR 0x000 +#define PHYA_TXTD_PRETXFIR2_COEFF3_U__PRETXFIR2_COEFF_2_3___POR 0x000 +#define PHYA_TXTD_PRETXFIR2_COEFF3_U__PRETXFIR2_COEFF_3_3___M 0x03FF0000 +#define PHYA_TXTD_PRETXFIR2_COEFF3_U__PRETXFIR2_COEFF_3_3___S 16 +#define PHYA_TXTD_PRETXFIR2_COEFF3_U__PRETXFIR2_COEFF_2_3___M 0x000003FF +#define PHYA_TXTD_PRETXFIR2_COEFF3_U__PRETXFIR2_COEFF_2_3___S 0 +#define PHYA_TXTD_PRETXFIR2_COEFF3_U___M 0x03FF03FF +#define PHYA_TXTD_PRETXFIR2_COEFF3_U___S 0 + +#define PHYA_TXTD_TX_FIR_CNTL_L (0x003B03F0) +#define PHYA_TXTD_TX_FIR_CNTL_L___RWC QCSR_REG_RW +#define PHYA_TXTD_TX_FIR_CNTL_L___POR 0x00000000 +#define PHYA_TXTD_TX_FIR_CNTL_L__TX_FIR_COEFF_SET_FORCE_EN___POR 0x0 +#define PHYA_TXTD_TX_FIR_CNTL_L__TX_FIR_COEFF_SET_FORCE_VAL___POR 0x0 +#define PHYA_TXTD_TX_FIR_CNTL_L__TX_FIR_COEFF_SET_FORCE_EN___M 0x00000100 +#define PHYA_TXTD_TX_FIR_CNTL_L__TX_FIR_COEFF_SET_FORCE_EN___S 8 +#define PHYA_TXTD_TX_FIR_CNTL_L__TX_FIR_COEFF_SET_FORCE_VAL___M 0x0000000F +#define PHYA_TXTD_TX_FIR_CNTL_L__TX_FIR_COEFF_SET_FORCE_VAL___S 0 +#define PHYA_TXTD_TX_FIR_CNTL_L___M 0x0000010F +#define PHYA_TXTD_TX_FIR_CNTL_L___S 0 + +#define PHYA_TXTD_PAPRD_TRAINER_CTRL_L (0x003B03F8) +#define PHYA_TXTD_PAPRD_TRAINER_CTRL_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PAPRD_TRAINER_CTRL_L___POR 0x00000001 +#define PHYA_TXTD_PAPRD_TRAINER_CTRL_L__CF_PAPRD_BBTXMIX_DISABLE___POR 0x1 +#define PHYA_TXTD_PAPRD_TRAINER_CTRL_L__CF_PAPRD_BBTXMIX_DISABLE___M 0x00000001 +#define PHYA_TXTD_PAPRD_TRAINER_CTRL_L__CF_PAPRD_BBTXMIX_DISABLE___S 0 +#define PHYA_TXTD_PAPRD_TRAINER_CTRL_L___M 0x00000001 +#define PHYA_TXTD_PAPRD_TRAINER_CTRL_L___S 0 + +#define PHYA_TXTD_PRIVATE_SPARE_L (0x003B0400) +#define PHYA_TXTD_PRIVATE_SPARE_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PRIVATE_SPARE_L___POR 0x00000000 +#define PHYA_TXTD_PRIVATE_SPARE_L__PRIVATE_SPARE_0___POR 0x00000000 +#define PHYA_TXTD_PRIVATE_SPARE_L__PRIVATE_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXTD_PRIVATE_SPARE_L__PRIVATE_SPARE_0___S 0 +#define PHYA_TXTD_PRIVATE_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXTD_PRIVATE_SPARE_L___S 0 + +#define PHYA_TXTD_PRIVATE_SPARE_U (0x003B0404) +#define PHYA_TXTD_PRIVATE_SPARE_U___RWC QCSR_REG_RW +#define PHYA_TXTD_PRIVATE_SPARE_U___POR 0x00000000 +#define PHYA_TXTD_PRIVATE_SPARE_U__PRIVATE_SPARE_1___POR 0x00000000 +#define PHYA_TXTD_PRIVATE_SPARE_U__PRIVATE_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXTD_PRIVATE_SPARE_U__PRIVATE_SPARE_1___S 0 +#define PHYA_TXTD_PRIVATE_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXTD_PRIVATE_SPARE_U___S 0 + +#define PHYA_TXTD_TX_PRE_DESC_WR_0_L (0x003B0408) +#define PHYA_TXTD_TX_PRE_DESC_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXTD_TX_PRE_DESC_WR_0_L___POR 0x00000000 +#define PHYA_TXTD_TX_PRE_DESC_WR_0_L__TX_PRE_DESC_TLV_HEADER___POR 0x00000000 +#define PHYA_TXTD_TX_PRE_DESC_WR_0_L__TX_PRE_DESC_TLV_HEADER___M 0xFFFFFFFF +#define PHYA_TXTD_TX_PRE_DESC_WR_0_L__TX_PRE_DESC_TLV_HEADER___S 0 +#define PHYA_TXTD_TX_PRE_DESC_WR_0_L___M 0xFFFFFFFF +#define PHYA_TXTD_TX_PRE_DESC_WR_0_L___S 0 + +#define PHYA_TXTD_TX_PRE_DESC_WR_0_U (0x003B040C) +#define PHYA_TXTD_TX_PRE_DESC_WR_0_U___RWC QCSR_REG_RW +#define PHYA_TXTD_TX_PRE_DESC_WR_0_U___POR 0x00000000 +#define PHYA_TXTD_TX_PRE_DESC_WR_0_U__TX_PRE_DESC_DWORD_0___POR 0x00000000 +#define PHYA_TXTD_TX_PRE_DESC_WR_0_U__TX_PRE_DESC_DWORD_0___M 0xFFFFFFFF +#define PHYA_TXTD_TX_PRE_DESC_WR_0_U__TX_PRE_DESC_DWORD_0___S 0 +#define PHYA_TXTD_TX_PRE_DESC_WR_0_U___M 0xFFFFFFFF +#define PHYA_TXTD_TX_PRE_DESC_WR_0_U___S 0 + +#define PHYA_TXTD_TX_PRE_DESC_WR_1_L (0x003B0410) +#define PHYA_TXTD_TX_PRE_DESC_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXTD_TX_PRE_DESC_WR_1_L___POR 0x00000000 +#define PHYA_TXTD_TX_PRE_DESC_WR_1_L__TX_PRE_DESC_DWORD_1___POR 0x00000000 +#define PHYA_TXTD_TX_PRE_DESC_WR_1_L__TX_PRE_DESC_DWORD_1___M 0xFFFFFFFF +#define PHYA_TXTD_TX_PRE_DESC_WR_1_L__TX_PRE_DESC_DWORD_1___S 0 +#define PHYA_TXTD_TX_PRE_DESC_WR_1_L___M 0xFFFFFFFF +#define PHYA_TXTD_TX_PRE_DESC_WR_1_L___S 0 + +#define PHYA_TXTD_TX_PRE_DESC_WR_1_U (0x003B0414) +#define PHYA_TXTD_TX_PRE_DESC_WR_1_U___RWC QCSR_REG_RW +#define PHYA_TXTD_TX_PRE_DESC_WR_1_U___POR 0x00000000 +#define PHYA_TXTD_TX_PRE_DESC_WR_1_U__TX_PRE_DESC_DWORD_2___POR 0x00000000 +#define PHYA_TXTD_TX_PRE_DESC_WR_1_U__TX_PRE_DESC_DWORD_2___M 0xFFFFFFFF +#define PHYA_TXTD_TX_PRE_DESC_WR_1_U__TX_PRE_DESC_DWORD_2___S 0 +#define PHYA_TXTD_TX_PRE_DESC_WR_1_U___M 0xFFFFFFFF +#define PHYA_TXTD_TX_PRE_DESC_WR_1_U___S 0 + +#define PHYA_TXTD_TX_PRE_DESC_WR_2_L (0x003B0418) +#define PHYA_TXTD_TX_PRE_DESC_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXTD_TX_PRE_DESC_WR_2_L___POR 0x00000000 +#define PHYA_TXTD_TX_PRE_DESC_WR_2_L__TX_PRE_DESC_DWORD_3___POR 0x00000000 +#define PHYA_TXTD_TX_PRE_DESC_WR_2_L__TX_PRE_DESC_DWORD_3___M 0xFFFFFFFF +#define PHYA_TXTD_TX_PRE_DESC_WR_2_L__TX_PRE_DESC_DWORD_3___S 0 +#define PHYA_TXTD_TX_PRE_DESC_WR_2_L___M 0xFFFFFFFF +#define PHYA_TXTD_TX_PRE_DESC_WR_2_L___S 0 + +#define PHYA_TXTD_TX_PRE_DESC_WR_2_U (0x003B041C) +#define PHYA_TXTD_TX_PRE_DESC_WR_2_U___RWC QCSR_REG_RW +#define PHYA_TXTD_TX_PRE_DESC_WR_2_U___POR 0x00000000 +#define PHYA_TXTD_TX_PRE_DESC_WR_2_U__TX_PRE_DESC_DWORD_4___POR 0x00000000 +#define PHYA_TXTD_TX_PRE_DESC_WR_2_U__TX_PRE_DESC_DWORD_4___M 0xFFFFFFFF +#define PHYA_TXTD_TX_PRE_DESC_WR_2_U__TX_PRE_DESC_DWORD_4___S 0 +#define PHYA_TXTD_TX_PRE_DESC_WR_2_U___M 0xFFFFFFFF +#define PHYA_TXTD_TX_PRE_DESC_WR_2_U___S 0 + +#define PHYA_TXTD_TX_PRE_DESC_WR_3_L (0x003B0420) +#define PHYA_TXTD_TX_PRE_DESC_WR_3_L___RWC QCSR_REG_RW +#define PHYA_TXTD_TX_PRE_DESC_WR_3_L___POR 0x00000000 +#define PHYA_TXTD_TX_PRE_DESC_WR_3_L__TX_PRE_DESC_DWORD_5___POR 0x00000000 +#define PHYA_TXTD_TX_PRE_DESC_WR_3_L__TX_PRE_DESC_DWORD_5___M 0xFFFFFFFF +#define PHYA_TXTD_TX_PRE_DESC_WR_3_L__TX_PRE_DESC_DWORD_5___S 0 +#define PHYA_TXTD_TX_PRE_DESC_WR_3_L___M 0xFFFFFFFF +#define PHYA_TXTD_TX_PRE_DESC_WR_3_L___S 0 + +#define PHYA_TXTD_TX_PRE_DESC_WR_SPARE_L (0x003B0428) +#define PHYA_TXTD_TX_PRE_DESC_WR_SPARE_L___RWC QCSR_REG_RW +#define PHYA_TXTD_TX_PRE_DESC_WR_SPARE_L___POR 0x00000000 +#define PHYA_TXTD_TX_PRE_DESC_WR_SPARE_L__TX_PRE_DESC_WR_SPARE_0___POR 0x00000000 +#define PHYA_TXTD_TX_PRE_DESC_WR_SPARE_L__TX_PRE_DESC_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXTD_TX_PRE_DESC_WR_SPARE_L__TX_PRE_DESC_WR_SPARE_0___S 0 +#define PHYA_TXTD_TX_PRE_DESC_WR_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXTD_TX_PRE_DESC_WR_SPARE_L___S 0 + +#define PHYA_TXTD_TX_PRE_DESC_WR_SPARE_U (0x003B042C) +#define PHYA_TXTD_TX_PRE_DESC_WR_SPARE_U___RWC QCSR_REG_RW +#define PHYA_TXTD_TX_PRE_DESC_WR_SPARE_U___POR 0x00000000 +#define PHYA_TXTD_TX_PRE_DESC_WR_SPARE_U__TX_PRE_DESC_WR_SPARE_1___POR 0x00000000 +#define PHYA_TXTD_TX_PRE_DESC_WR_SPARE_U__TX_PRE_DESC_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXTD_TX_PRE_DESC_WR_SPARE_U__TX_PRE_DESC_WR_SPARE_1___S 0 +#define PHYA_TXTD_TX_PRE_DESC_WR_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXTD_TX_PRE_DESC_WR_SPARE_U___S 0 + +#define PHYA_TXTD_TX_DESC_WR_0_L (0x003B0430) +#define PHYA_TXTD_TX_DESC_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXTD_TX_DESC_WR_0_L___POR 0x00000000 +#define PHYA_TXTD_TX_DESC_WR_0_L__TX_DESC_TLV_HEADER___POR 0x00000000 +#define PHYA_TXTD_TX_DESC_WR_0_L__TX_DESC_TLV_HEADER___M 0xFFFFFFFF +#define PHYA_TXTD_TX_DESC_WR_0_L__TX_DESC_TLV_HEADER___S 0 +#define PHYA_TXTD_TX_DESC_WR_0_L___M 0xFFFFFFFF +#define PHYA_TXTD_TX_DESC_WR_0_L___S 0 + +#define PHYA_TXTD_TX_DESC_WR_0_U (0x003B0434) +#define PHYA_TXTD_TX_DESC_WR_0_U___RWC QCSR_REG_RW +#define PHYA_TXTD_TX_DESC_WR_0_U___POR 0x00000000 +#define PHYA_TXTD_TX_DESC_WR_0_U__TX_DESC_DWORD_0___POR 0x00000000 +#define PHYA_TXTD_TX_DESC_WR_0_U__TX_DESC_DWORD_0___M 0xFFFFFFFF +#define PHYA_TXTD_TX_DESC_WR_0_U__TX_DESC_DWORD_0___S 0 +#define PHYA_TXTD_TX_DESC_WR_0_U___M 0xFFFFFFFF +#define PHYA_TXTD_TX_DESC_WR_0_U___S 0 + +#define PHYA_TXTD_TX_DESC_WR_1_L (0x003B0438) +#define PHYA_TXTD_TX_DESC_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXTD_TX_DESC_WR_1_L___POR 0x00000000 +#define PHYA_TXTD_TX_DESC_WR_1_L__TX_DESC_DWORD_1___POR 0x00000000 +#define PHYA_TXTD_TX_DESC_WR_1_L__TX_DESC_DWORD_1___M 0xFFFFFFFF +#define PHYA_TXTD_TX_DESC_WR_1_L__TX_DESC_DWORD_1___S 0 +#define PHYA_TXTD_TX_DESC_WR_1_L___M 0xFFFFFFFF +#define PHYA_TXTD_TX_DESC_WR_1_L___S 0 + +#define PHYA_TXTD_TX_DESC_WR_1_U (0x003B043C) +#define PHYA_TXTD_TX_DESC_WR_1_U___RWC QCSR_REG_RW +#define PHYA_TXTD_TX_DESC_WR_1_U___POR 0x00000000 +#define PHYA_TXTD_TX_DESC_WR_1_U__TX_DESC_DWORD_2___POR 0x00000000 +#define PHYA_TXTD_TX_DESC_WR_1_U__TX_DESC_DWORD_2___M 0xFFFFFFFF +#define PHYA_TXTD_TX_DESC_WR_1_U__TX_DESC_DWORD_2___S 0 +#define PHYA_TXTD_TX_DESC_WR_1_U___M 0xFFFFFFFF +#define PHYA_TXTD_TX_DESC_WR_1_U___S 0 + +#define PHYA_TXTD_TX_DESC_WR_2_L (0x003B0440) +#define PHYA_TXTD_TX_DESC_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXTD_TX_DESC_WR_2_L___POR 0x00000000 +#define PHYA_TXTD_TX_DESC_WR_2_L__TX_DESC_DWORD_3___POR 0x00000000 +#define PHYA_TXTD_TX_DESC_WR_2_L__TX_DESC_DWORD_3___M 0xFFFFFFFF +#define PHYA_TXTD_TX_DESC_WR_2_L__TX_DESC_DWORD_3___S 0 +#define PHYA_TXTD_TX_DESC_WR_2_L___M 0xFFFFFFFF +#define PHYA_TXTD_TX_DESC_WR_2_L___S 0 + +#define PHYA_TXTD_TX_DESC_WR_SPARE_L (0x003B0448) +#define PHYA_TXTD_TX_DESC_WR_SPARE_L___RWC QCSR_REG_RW +#define PHYA_TXTD_TX_DESC_WR_SPARE_L___POR 0x00000000 +#define PHYA_TXTD_TX_DESC_WR_SPARE_L__TX_DESC_WR_SPARE_0___POR 0x00000000 +#define PHYA_TXTD_TX_DESC_WR_SPARE_L__TX_DESC_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXTD_TX_DESC_WR_SPARE_L__TX_DESC_WR_SPARE_0___S 0 +#define PHYA_TXTD_TX_DESC_WR_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXTD_TX_DESC_WR_SPARE_L___S 0 + +#define PHYA_TXTD_TX_DESC_WR_SPARE_U (0x003B044C) +#define PHYA_TXTD_TX_DESC_WR_SPARE_U___RWC QCSR_REG_RW +#define PHYA_TXTD_TX_DESC_WR_SPARE_U___POR 0x00000000 +#define PHYA_TXTD_TX_DESC_WR_SPARE_U__TX_DESC_WR_SPARE_1___POR 0x00000000 +#define PHYA_TXTD_TX_DESC_WR_SPARE_U__TX_DESC_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXTD_TX_DESC_WR_SPARE_U__TX_DESC_WR_SPARE_1___S 0 +#define PHYA_TXTD_TX_DESC_WR_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXTD_TX_DESC_WR_SPARE_U___S 0 + +#define PHYA_TXTD_ULD0_DESC_0_L (0x003B0450) +#define PHYA_TXTD_ULD0_DESC_0_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD0_DESC_0_L___POR 0x01400000 +#define PHYA_TXTD_ULD0_DESC_0_L__ULD0_CSR_ULD_SYM_CP_LEN___POR 0x140 +#define PHYA_TXTD_ULD0_DESC_0_L__ULD0_CSR_ULD_START_ADDR___POR 0x000 +#define PHYA_TXTD_ULD0_DESC_0_L__ULD0_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000 +#define PHYA_TXTD_ULD0_DESC_0_L__ULD0_CSR_ULD_SYM_CP_LEN___S 16 +#define PHYA_TXTD_ULD0_DESC_0_L__ULD0_CSR_ULD_START_ADDR___M 0x00000FFF +#define PHYA_TXTD_ULD0_DESC_0_L__ULD0_CSR_ULD_START_ADDR___S 0 +#define PHYA_TXTD_ULD0_DESC_0_L___M 0x0FFF0FFF +#define PHYA_TXTD_ULD0_DESC_0_L___S 0 + +#define PHYA_TXTD_ULD0_DESC_0_U (0x003B0454) +#define PHYA_TXTD_ULD0_DESC_0_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD0_DESC_0_U___POR 0x01010100 +#define PHYA_TXTD_ULD0_DESC_0_U__ULD0_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x1 +#define PHYA_TXTD_ULD0_DESC_0_U__ULD0_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1 +#define PHYA_TXTD_ULD0_DESC_0_U__ULD0_CSR_ULD_DESC_DURATION___POR 0x1 +#define PHYA_TXTD_ULD0_DESC_0_U__ULD0_CSR_ULD_FFT_SIZE___POR 0x0 +#define PHYA_TXTD_ULD0_DESC_0_U__ULD0_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000 +#define PHYA_TXTD_ULD0_DESC_0_U__ULD0_CSR_ULD_APPLY_PER_CHN_CSD___S 24 +#define PHYA_TXTD_ULD0_DESC_0_U__ULD0_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000 +#define PHYA_TXTD_ULD0_DESC_0_U__ULD0_CSR_ULD_IFFT_BUF_REPEAT___S 16 +#define PHYA_TXTD_ULD0_DESC_0_U__ULD0_CSR_ULD_DESC_DURATION___M 0x00000F00 +#define PHYA_TXTD_ULD0_DESC_0_U__ULD0_CSR_ULD_DESC_DURATION___S 8 +#define PHYA_TXTD_ULD0_DESC_0_U__ULD0_CSR_ULD_FFT_SIZE___M 0x0000000F +#define PHYA_TXTD_ULD0_DESC_0_U__ULD0_CSR_ULD_FFT_SIZE___S 0 +#define PHYA_TXTD_ULD0_DESC_0_U___M 0x0F0F0F0F +#define PHYA_TXTD_ULD0_DESC_0_U___S 0 + +#define PHYA_TXTD_ULD0_DESC_1_L (0x003B0458) +#define PHYA_TXTD_ULD0_DESC_1_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD0_DESC_1_L___POR 0x01000100 +#define PHYA_TXTD_ULD0_DESC_1_L__ULD0_CSR_WIN_SHAPE_RIGHT___POR 0x1 +#define PHYA_TXTD_ULD0_DESC_1_L__ULD0_CSR_WIN_SHAPE_LEFT___POR 0x0 +#define PHYA_TXTD_ULD0_DESC_1_L__ULD0_CSR_WIN_LENGTH_RIGHT___POR 0x01 +#define PHYA_TXTD_ULD0_DESC_1_L__ULD0_CSR_WIN_LENGTH_LEFT___POR 0x00 +#define PHYA_TXTD_ULD0_DESC_1_L__ULD0_CSR_WIN_SHAPE_RIGHT___M 0x01000000 +#define PHYA_TXTD_ULD0_DESC_1_L__ULD0_CSR_WIN_SHAPE_RIGHT___S 24 +#define PHYA_TXTD_ULD0_DESC_1_L__ULD0_CSR_WIN_SHAPE_LEFT___M 0x00010000 +#define PHYA_TXTD_ULD0_DESC_1_L__ULD0_CSR_WIN_SHAPE_LEFT___S 16 +#define PHYA_TXTD_ULD0_DESC_1_L__ULD0_CSR_WIN_LENGTH_RIGHT___M 0x00001F00 +#define PHYA_TXTD_ULD0_DESC_1_L__ULD0_CSR_WIN_LENGTH_RIGHT___S 8 +#define PHYA_TXTD_ULD0_DESC_1_L__ULD0_CSR_WIN_LENGTH_LEFT___M 0x0000001F +#define PHYA_TXTD_ULD0_DESC_1_L__ULD0_CSR_WIN_LENGTH_LEFT___S 0 +#define PHYA_TXTD_ULD0_DESC_1_L___M 0x01011F1F +#define PHYA_TXTD_ULD0_DESC_1_L___S 0 + +#define PHYA_TXTD_ULD0_DESC_1_U (0x003B045C) +#define PHYA_TXTD_ULD0_DESC_1_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD0_DESC_1_U___POR 0x00000000 +#define PHYA_TXTD_ULD0_DESC_1_U__ULD0_CSR_POWER_SCALING_SEL___POR 0x0 +#define PHYA_TXTD_ULD0_DESC_1_U__ULD0_CSR_POWER_SCALING_SEL___M 0x00000007 +#define PHYA_TXTD_ULD0_DESC_1_U__ULD0_CSR_POWER_SCALING_SEL___S 0 +#define PHYA_TXTD_ULD0_DESC_1_U___M 0x00000007 +#define PHYA_TXTD_ULD0_DESC_1_U___S 0 + +#define PHYA_TXTD_ULD1_DESC_0_L (0x003B0460) +#define PHYA_TXTD_ULD1_DESC_0_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD1_DESC_0_L___POR 0x01400040 +#define PHYA_TXTD_ULD1_DESC_0_L__ULD1_CSR_ULD_SYM_CP_LEN___POR 0x140 +#define PHYA_TXTD_ULD1_DESC_0_L__ULD1_CSR_ULD_START_ADDR___POR 0x040 +#define PHYA_TXTD_ULD1_DESC_0_L__ULD1_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000 +#define PHYA_TXTD_ULD1_DESC_0_L__ULD1_CSR_ULD_SYM_CP_LEN___S 16 +#define PHYA_TXTD_ULD1_DESC_0_L__ULD1_CSR_ULD_START_ADDR___M 0x00000FFF +#define PHYA_TXTD_ULD1_DESC_0_L__ULD1_CSR_ULD_START_ADDR___S 0 +#define PHYA_TXTD_ULD1_DESC_0_L___M 0x0FFF0FFF +#define PHYA_TXTD_ULD1_DESC_0_L___S 0 + +#define PHYA_TXTD_ULD1_DESC_0_U (0x003B0464) +#define PHYA_TXTD_ULD1_DESC_0_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD1_DESC_0_U___POR 0x01010102 +#define PHYA_TXTD_ULD1_DESC_0_U__ULD1_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x1 +#define PHYA_TXTD_ULD1_DESC_0_U__ULD1_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1 +#define PHYA_TXTD_ULD1_DESC_0_U__ULD1_CSR_ULD_DESC_DURATION___POR 0x1 +#define PHYA_TXTD_ULD1_DESC_0_U__ULD1_CSR_ULD_FFT_SIZE___POR 0x2 +#define PHYA_TXTD_ULD1_DESC_0_U__ULD1_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000 +#define PHYA_TXTD_ULD1_DESC_0_U__ULD1_CSR_ULD_APPLY_PER_CHN_CSD___S 24 +#define PHYA_TXTD_ULD1_DESC_0_U__ULD1_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000 +#define PHYA_TXTD_ULD1_DESC_0_U__ULD1_CSR_ULD_IFFT_BUF_REPEAT___S 16 +#define PHYA_TXTD_ULD1_DESC_0_U__ULD1_CSR_ULD_DESC_DURATION___M 0x00000F00 +#define PHYA_TXTD_ULD1_DESC_0_U__ULD1_CSR_ULD_DESC_DURATION___S 8 +#define PHYA_TXTD_ULD1_DESC_0_U__ULD1_CSR_ULD_FFT_SIZE___M 0x0000000F +#define PHYA_TXTD_ULD1_DESC_0_U__ULD1_CSR_ULD_FFT_SIZE___S 0 +#define PHYA_TXTD_ULD1_DESC_0_U___M 0x0F0F0F0F +#define PHYA_TXTD_ULD1_DESC_0_U___S 0 + +#define PHYA_TXTD_ULD1_DESC_1_L (0x003B0468) +#define PHYA_TXTD_ULD1_DESC_1_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD1_DESC_1_L___POR 0x00010300 +#define PHYA_TXTD_ULD1_DESC_1_L__ULD1_CSR_WIN_SHAPE_RIGHT___POR 0x0 +#define PHYA_TXTD_ULD1_DESC_1_L__ULD1_CSR_WIN_SHAPE_LEFT___POR 0x1 +#define PHYA_TXTD_ULD1_DESC_1_L__ULD1_CSR_WIN_LENGTH_RIGHT___POR 0x03 +#define PHYA_TXTD_ULD1_DESC_1_L__ULD1_CSR_WIN_LENGTH_LEFT___POR 0x00 +#define PHYA_TXTD_ULD1_DESC_1_L__ULD1_CSR_WIN_SHAPE_RIGHT___M 0x01000000 +#define PHYA_TXTD_ULD1_DESC_1_L__ULD1_CSR_WIN_SHAPE_RIGHT___S 24 +#define PHYA_TXTD_ULD1_DESC_1_L__ULD1_CSR_WIN_SHAPE_LEFT___M 0x00010000 +#define PHYA_TXTD_ULD1_DESC_1_L__ULD1_CSR_WIN_SHAPE_LEFT___S 16 +#define PHYA_TXTD_ULD1_DESC_1_L__ULD1_CSR_WIN_LENGTH_RIGHT___M 0x00001F00 +#define PHYA_TXTD_ULD1_DESC_1_L__ULD1_CSR_WIN_LENGTH_RIGHT___S 8 +#define PHYA_TXTD_ULD1_DESC_1_L__ULD1_CSR_WIN_LENGTH_LEFT___M 0x0000001F +#define PHYA_TXTD_ULD1_DESC_1_L__ULD1_CSR_WIN_LENGTH_LEFT___S 0 +#define PHYA_TXTD_ULD1_DESC_1_L___M 0x01011F1F +#define PHYA_TXTD_ULD1_DESC_1_L___S 0 + +#define PHYA_TXTD_ULD1_DESC_1_U (0x003B046C) +#define PHYA_TXTD_ULD1_DESC_1_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD1_DESC_1_U___POR 0x00000000 +#define PHYA_TXTD_ULD1_DESC_1_U__ULD1_CSR_POWER_SCALING_SEL___POR 0x0 +#define PHYA_TXTD_ULD1_DESC_1_U__ULD1_CSR_POWER_SCALING_SEL___M 0x00000007 +#define PHYA_TXTD_ULD1_DESC_1_U__ULD1_CSR_POWER_SCALING_SEL___S 0 +#define PHYA_TXTD_ULD1_DESC_1_U___M 0x00000007 +#define PHYA_TXTD_ULD1_DESC_1_U___S 0 + +#define PHYA_TXTD_ULD2_DESC_0_L (0x003B0470) +#define PHYA_TXTD_ULD2_DESC_0_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD2_DESC_0_L___POR 0x00A00060 +#define PHYA_TXTD_ULD2_DESC_0_L__ULD2_CSR_ULD_SYM_CP_LEN___POR 0x0A0 +#define PHYA_TXTD_ULD2_DESC_0_L__ULD2_CSR_ULD_START_ADDR___POR 0x060 +#define PHYA_TXTD_ULD2_DESC_0_L__ULD2_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000 +#define PHYA_TXTD_ULD2_DESC_0_L__ULD2_CSR_ULD_SYM_CP_LEN___S 16 +#define PHYA_TXTD_ULD2_DESC_0_L__ULD2_CSR_ULD_START_ADDR___M 0x00000FFF +#define PHYA_TXTD_ULD2_DESC_0_L__ULD2_CSR_ULD_START_ADDR___S 0 +#define PHYA_TXTD_ULD2_DESC_0_L___M 0x0FFF0FFF +#define PHYA_TXTD_ULD2_DESC_0_L___S 0 + +#define PHYA_TXTD_ULD2_DESC_0_U (0x003B0474) +#define PHYA_TXTD_ULD2_DESC_0_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD2_DESC_0_U___POR 0x01010102 +#define PHYA_TXTD_ULD2_DESC_0_U__ULD2_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x1 +#define PHYA_TXTD_ULD2_DESC_0_U__ULD2_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1 +#define PHYA_TXTD_ULD2_DESC_0_U__ULD2_CSR_ULD_DESC_DURATION___POR 0x1 +#define PHYA_TXTD_ULD2_DESC_0_U__ULD2_CSR_ULD_FFT_SIZE___POR 0x2 +#define PHYA_TXTD_ULD2_DESC_0_U__ULD2_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000 +#define PHYA_TXTD_ULD2_DESC_0_U__ULD2_CSR_ULD_APPLY_PER_CHN_CSD___S 24 +#define PHYA_TXTD_ULD2_DESC_0_U__ULD2_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000 +#define PHYA_TXTD_ULD2_DESC_0_U__ULD2_CSR_ULD_IFFT_BUF_REPEAT___S 16 +#define PHYA_TXTD_ULD2_DESC_0_U__ULD2_CSR_ULD_DESC_DURATION___M 0x00000F00 +#define PHYA_TXTD_ULD2_DESC_0_U__ULD2_CSR_ULD_DESC_DURATION___S 8 +#define PHYA_TXTD_ULD2_DESC_0_U__ULD2_CSR_ULD_FFT_SIZE___M 0x0000000F +#define PHYA_TXTD_ULD2_DESC_0_U__ULD2_CSR_ULD_FFT_SIZE___S 0 +#define PHYA_TXTD_ULD2_DESC_0_U___M 0x0F0F0F0F +#define PHYA_TXTD_ULD2_DESC_0_U___S 0 + +#define PHYA_TXTD_ULD2_DESC_1_L (0x003B0478) +#define PHYA_TXTD_ULD2_DESC_1_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD2_DESC_1_L___POR 0x00000300 +#define PHYA_TXTD_ULD2_DESC_1_L__ULD2_CSR_WIN_SHAPE_RIGHT___POR 0x0 +#define PHYA_TXTD_ULD2_DESC_1_L__ULD2_CSR_WIN_SHAPE_LEFT___POR 0x0 +#define PHYA_TXTD_ULD2_DESC_1_L__ULD2_CSR_WIN_LENGTH_RIGHT___POR 0x03 +#define PHYA_TXTD_ULD2_DESC_1_L__ULD2_CSR_WIN_LENGTH_LEFT___POR 0x00 +#define PHYA_TXTD_ULD2_DESC_1_L__ULD2_CSR_WIN_SHAPE_RIGHT___M 0x01000000 +#define PHYA_TXTD_ULD2_DESC_1_L__ULD2_CSR_WIN_SHAPE_RIGHT___S 24 +#define PHYA_TXTD_ULD2_DESC_1_L__ULD2_CSR_WIN_SHAPE_LEFT___M 0x00010000 +#define PHYA_TXTD_ULD2_DESC_1_L__ULD2_CSR_WIN_SHAPE_LEFT___S 16 +#define PHYA_TXTD_ULD2_DESC_1_L__ULD2_CSR_WIN_LENGTH_RIGHT___M 0x00001F00 +#define PHYA_TXTD_ULD2_DESC_1_L__ULD2_CSR_WIN_LENGTH_RIGHT___S 8 +#define PHYA_TXTD_ULD2_DESC_1_L__ULD2_CSR_WIN_LENGTH_LEFT___M 0x0000001F +#define PHYA_TXTD_ULD2_DESC_1_L__ULD2_CSR_WIN_LENGTH_LEFT___S 0 +#define PHYA_TXTD_ULD2_DESC_1_L___M 0x01011F1F +#define PHYA_TXTD_ULD2_DESC_1_L___S 0 + +#define PHYA_TXTD_ULD2_DESC_1_U (0x003B047C) +#define PHYA_TXTD_ULD2_DESC_1_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD2_DESC_1_U___POR 0x00000000 +#define PHYA_TXTD_ULD2_DESC_1_U__ULD2_CSR_POWER_SCALING_SEL___POR 0x0 +#define PHYA_TXTD_ULD2_DESC_1_U__ULD2_CSR_POWER_SCALING_SEL___M 0x00000007 +#define PHYA_TXTD_ULD2_DESC_1_U__ULD2_CSR_POWER_SCALING_SEL___S 0 +#define PHYA_TXTD_ULD2_DESC_1_U___M 0x00000007 +#define PHYA_TXTD_ULD2_DESC_1_U___S 0 + +#define PHYA_TXTD_ULD3_DESC_0_L (0x003B0480) +#define PHYA_TXTD_ULD3_DESC_0_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD3_DESC_0_L___POR 0x00A00060 +#define PHYA_TXTD_ULD3_DESC_0_L__ULD3_CSR_ULD_SYM_CP_LEN___POR 0x0A0 +#define PHYA_TXTD_ULD3_DESC_0_L__ULD3_CSR_ULD_START_ADDR___POR 0x060 +#define PHYA_TXTD_ULD3_DESC_0_L__ULD3_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000 +#define PHYA_TXTD_ULD3_DESC_0_L__ULD3_CSR_ULD_SYM_CP_LEN___S 16 +#define PHYA_TXTD_ULD3_DESC_0_L__ULD3_CSR_ULD_START_ADDR___M 0x00000FFF +#define PHYA_TXTD_ULD3_DESC_0_L__ULD3_CSR_ULD_START_ADDR___S 0 +#define PHYA_TXTD_ULD3_DESC_0_L___M 0x0FFF0FFF +#define PHYA_TXTD_ULD3_DESC_0_L___S 0 + +#define PHYA_TXTD_ULD3_DESC_0_U (0x003B0484) +#define PHYA_TXTD_ULD3_DESC_0_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD3_DESC_0_U___POR 0x01010002 +#define PHYA_TXTD_ULD3_DESC_0_U__ULD3_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x1 +#define PHYA_TXTD_ULD3_DESC_0_U__ULD3_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1 +#define PHYA_TXTD_ULD3_DESC_0_U__ULD3_CSR_ULD_DESC_DURATION___POR 0x0 +#define PHYA_TXTD_ULD3_DESC_0_U__ULD3_CSR_ULD_FFT_SIZE___POR 0x2 +#define PHYA_TXTD_ULD3_DESC_0_U__ULD3_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000 +#define PHYA_TXTD_ULD3_DESC_0_U__ULD3_CSR_ULD_APPLY_PER_CHN_CSD___S 24 +#define PHYA_TXTD_ULD3_DESC_0_U__ULD3_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000 +#define PHYA_TXTD_ULD3_DESC_0_U__ULD3_CSR_ULD_IFFT_BUF_REPEAT___S 16 +#define PHYA_TXTD_ULD3_DESC_0_U__ULD3_CSR_ULD_DESC_DURATION___M 0x00000F00 +#define PHYA_TXTD_ULD3_DESC_0_U__ULD3_CSR_ULD_DESC_DURATION___S 8 +#define PHYA_TXTD_ULD3_DESC_0_U__ULD3_CSR_ULD_FFT_SIZE___M 0x0000000F +#define PHYA_TXTD_ULD3_DESC_0_U__ULD3_CSR_ULD_FFT_SIZE___S 0 +#define PHYA_TXTD_ULD3_DESC_0_U___M 0x0F0F0F0F +#define PHYA_TXTD_ULD3_DESC_0_U___S 0 + +#define PHYA_TXTD_ULD3_DESC_1_L (0x003B0488) +#define PHYA_TXTD_ULD3_DESC_1_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD3_DESC_1_L___POR 0x00000300 +#define PHYA_TXTD_ULD3_DESC_1_L__ULD3_CSR_WIN_SHAPE_RIGHT___POR 0x0 +#define PHYA_TXTD_ULD3_DESC_1_L__ULD3_CSR_WIN_SHAPE_LEFT___POR 0x0 +#define PHYA_TXTD_ULD3_DESC_1_L__ULD3_CSR_WIN_LENGTH_RIGHT___POR 0x03 +#define PHYA_TXTD_ULD3_DESC_1_L__ULD3_CSR_WIN_LENGTH_LEFT___POR 0x00 +#define PHYA_TXTD_ULD3_DESC_1_L__ULD3_CSR_WIN_SHAPE_RIGHT___M 0x01000000 +#define PHYA_TXTD_ULD3_DESC_1_L__ULD3_CSR_WIN_SHAPE_RIGHT___S 24 +#define PHYA_TXTD_ULD3_DESC_1_L__ULD3_CSR_WIN_SHAPE_LEFT___M 0x00010000 +#define PHYA_TXTD_ULD3_DESC_1_L__ULD3_CSR_WIN_SHAPE_LEFT___S 16 +#define PHYA_TXTD_ULD3_DESC_1_L__ULD3_CSR_WIN_LENGTH_RIGHT___M 0x00001F00 +#define PHYA_TXTD_ULD3_DESC_1_L__ULD3_CSR_WIN_LENGTH_RIGHT___S 8 +#define PHYA_TXTD_ULD3_DESC_1_L__ULD3_CSR_WIN_LENGTH_LEFT___M 0x0000001F +#define PHYA_TXTD_ULD3_DESC_1_L__ULD3_CSR_WIN_LENGTH_LEFT___S 0 +#define PHYA_TXTD_ULD3_DESC_1_L___M 0x01011F1F +#define PHYA_TXTD_ULD3_DESC_1_L___S 0 + +#define PHYA_TXTD_ULD3_DESC_1_U (0x003B048C) +#define PHYA_TXTD_ULD3_DESC_1_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD3_DESC_1_U___POR 0x00000000 +#define PHYA_TXTD_ULD3_DESC_1_U__ULD3_CSR_POWER_SCALING_SEL___POR 0x0 +#define PHYA_TXTD_ULD3_DESC_1_U__ULD3_CSR_POWER_SCALING_SEL___M 0x00000007 +#define PHYA_TXTD_ULD3_DESC_1_U__ULD3_CSR_POWER_SCALING_SEL___S 0 +#define PHYA_TXTD_ULD3_DESC_1_U___M 0x00000007 +#define PHYA_TXTD_ULD3_DESC_1_U___S 0 + +#define PHYA_TXTD_ULD4_DESC_0_L (0x003B0490) +#define PHYA_TXTD_ULD4_DESC_0_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD4_DESC_0_L___POR 0x00A00060 +#define PHYA_TXTD_ULD4_DESC_0_L__ULD4_CSR_ULD_SYM_CP_LEN___POR 0x0A0 +#define PHYA_TXTD_ULD4_DESC_0_L__ULD4_CSR_ULD_START_ADDR___POR 0x060 +#define PHYA_TXTD_ULD4_DESC_0_L__ULD4_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000 +#define PHYA_TXTD_ULD4_DESC_0_L__ULD4_CSR_ULD_SYM_CP_LEN___S 16 +#define PHYA_TXTD_ULD4_DESC_0_L__ULD4_CSR_ULD_START_ADDR___M 0x00000FFF +#define PHYA_TXTD_ULD4_DESC_0_L__ULD4_CSR_ULD_START_ADDR___S 0 +#define PHYA_TXTD_ULD4_DESC_0_L___M 0x0FFF0FFF +#define PHYA_TXTD_ULD4_DESC_0_L___S 0 + +#define PHYA_TXTD_ULD4_DESC_0_U (0x003B0494) +#define PHYA_TXTD_ULD4_DESC_0_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD4_DESC_0_U___POR 0x02010102 +#define PHYA_TXTD_ULD4_DESC_0_U__ULD4_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x2 +#define PHYA_TXTD_ULD4_DESC_0_U__ULD4_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1 +#define PHYA_TXTD_ULD4_DESC_0_U__ULD4_CSR_ULD_DESC_DURATION___POR 0x1 +#define PHYA_TXTD_ULD4_DESC_0_U__ULD4_CSR_ULD_FFT_SIZE___POR 0x2 +#define PHYA_TXTD_ULD4_DESC_0_U__ULD4_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000 +#define PHYA_TXTD_ULD4_DESC_0_U__ULD4_CSR_ULD_APPLY_PER_CHN_CSD___S 24 +#define PHYA_TXTD_ULD4_DESC_0_U__ULD4_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000 +#define PHYA_TXTD_ULD4_DESC_0_U__ULD4_CSR_ULD_IFFT_BUF_REPEAT___S 16 +#define PHYA_TXTD_ULD4_DESC_0_U__ULD4_CSR_ULD_DESC_DURATION___M 0x00000F00 +#define PHYA_TXTD_ULD4_DESC_0_U__ULD4_CSR_ULD_DESC_DURATION___S 8 +#define PHYA_TXTD_ULD4_DESC_0_U__ULD4_CSR_ULD_FFT_SIZE___M 0x0000000F +#define PHYA_TXTD_ULD4_DESC_0_U__ULD4_CSR_ULD_FFT_SIZE___S 0 +#define PHYA_TXTD_ULD4_DESC_0_U___M 0x0F0F0F0F +#define PHYA_TXTD_ULD4_DESC_0_U___S 0 + +#define PHYA_TXTD_ULD4_DESC_1_L (0x003B0498) +#define PHYA_TXTD_ULD4_DESC_1_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD4_DESC_1_L___POR 0x00000000 +#define PHYA_TXTD_ULD4_DESC_1_L__ULD4_CSR_WIN_SHAPE_RIGHT___POR 0x0 +#define PHYA_TXTD_ULD4_DESC_1_L__ULD4_CSR_WIN_SHAPE_LEFT___POR 0x0 +#define PHYA_TXTD_ULD4_DESC_1_L__ULD4_CSR_WIN_LENGTH_RIGHT___POR 0x00 +#define PHYA_TXTD_ULD4_DESC_1_L__ULD4_CSR_WIN_LENGTH_LEFT___POR 0x00 +#define PHYA_TXTD_ULD4_DESC_1_L__ULD4_CSR_WIN_SHAPE_RIGHT___M 0x01000000 +#define PHYA_TXTD_ULD4_DESC_1_L__ULD4_CSR_WIN_SHAPE_RIGHT___S 24 +#define PHYA_TXTD_ULD4_DESC_1_L__ULD4_CSR_WIN_SHAPE_LEFT___M 0x00010000 +#define PHYA_TXTD_ULD4_DESC_1_L__ULD4_CSR_WIN_SHAPE_LEFT___S 16 +#define PHYA_TXTD_ULD4_DESC_1_L__ULD4_CSR_WIN_LENGTH_RIGHT___M 0x00001F00 +#define PHYA_TXTD_ULD4_DESC_1_L__ULD4_CSR_WIN_LENGTH_RIGHT___S 8 +#define PHYA_TXTD_ULD4_DESC_1_L__ULD4_CSR_WIN_LENGTH_LEFT___M 0x0000001F +#define PHYA_TXTD_ULD4_DESC_1_L__ULD4_CSR_WIN_LENGTH_LEFT___S 0 +#define PHYA_TXTD_ULD4_DESC_1_L___M 0x01011F1F +#define PHYA_TXTD_ULD4_DESC_1_L___S 0 + +#define PHYA_TXTD_ULD4_DESC_1_U (0x003B049C) +#define PHYA_TXTD_ULD4_DESC_1_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD4_DESC_1_U___POR 0x00000000 +#define PHYA_TXTD_ULD4_DESC_1_U__ULD4_CSR_POWER_SCALING_SEL___POR 0x0 +#define PHYA_TXTD_ULD4_DESC_1_U__ULD4_CSR_POWER_SCALING_SEL___M 0x00000007 +#define PHYA_TXTD_ULD4_DESC_1_U__ULD4_CSR_POWER_SCALING_SEL___S 0 +#define PHYA_TXTD_ULD4_DESC_1_U___M 0x00000007 +#define PHYA_TXTD_ULD4_DESC_1_U___S 0 + +#define PHYA_TXTD_ULD5_DESC_0_L (0x003B04A0) +#define PHYA_TXTD_ULD5_DESC_0_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD5_DESC_0_L___POR 0x00A00000 +#define PHYA_TXTD_ULD5_DESC_0_L__ULD5_CSR_ULD_SYM_CP_LEN___POR 0x0A0 +#define PHYA_TXTD_ULD5_DESC_0_L__ULD5_CSR_ULD_START_ADDR___POR 0x000 +#define PHYA_TXTD_ULD5_DESC_0_L__ULD5_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000 +#define PHYA_TXTD_ULD5_DESC_0_L__ULD5_CSR_ULD_SYM_CP_LEN___S 16 +#define PHYA_TXTD_ULD5_DESC_0_L__ULD5_CSR_ULD_START_ADDR___M 0x00000FFF +#define PHYA_TXTD_ULD5_DESC_0_L__ULD5_CSR_ULD_START_ADDR___S 0 +#define PHYA_TXTD_ULD5_DESC_0_L___M 0x0FFF0FFF +#define PHYA_TXTD_ULD5_DESC_0_L___S 0 + +#define PHYA_TXTD_ULD5_DESC_0_U (0x003B04A4) +#define PHYA_TXTD_ULD5_DESC_0_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD5_DESC_0_U___POR 0x02010100 +#define PHYA_TXTD_ULD5_DESC_0_U__ULD5_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x2 +#define PHYA_TXTD_ULD5_DESC_0_U__ULD5_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1 +#define PHYA_TXTD_ULD5_DESC_0_U__ULD5_CSR_ULD_DESC_DURATION___POR 0x1 +#define PHYA_TXTD_ULD5_DESC_0_U__ULD5_CSR_ULD_FFT_SIZE___POR 0x0 +#define PHYA_TXTD_ULD5_DESC_0_U__ULD5_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000 +#define PHYA_TXTD_ULD5_DESC_0_U__ULD5_CSR_ULD_APPLY_PER_CHN_CSD___S 24 +#define PHYA_TXTD_ULD5_DESC_0_U__ULD5_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000 +#define PHYA_TXTD_ULD5_DESC_0_U__ULD5_CSR_ULD_IFFT_BUF_REPEAT___S 16 +#define PHYA_TXTD_ULD5_DESC_0_U__ULD5_CSR_ULD_DESC_DURATION___M 0x00000F00 +#define PHYA_TXTD_ULD5_DESC_0_U__ULD5_CSR_ULD_DESC_DURATION___S 8 +#define PHYA_TXTD_ULD5_DESC_0_U__ULD5_CSR_ULD_FFT_SIZE___M 0x0000000F +#define PHYA_TXTD_ULD5_DESC_0_U__ULD5_CSR_ULD_FFT_SIZE___S 0 +#define PHYA_TXTD_ULD5_DESC_0_U___M 0x0F0F0F0F +#define PHYA_TXTD_ULD5_DESC_0_U___S 0 + +#define PHYA_TXTD_ULD5_DESC_1_L (0x003B04A8) +#define PHYA_TXTD_ULD5_DESC_1_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD5_DESC_1_L___POR 0x00000000 +#define PHYA_TXTD_ULD5_DESC_1_L__ULD5_CSR_WIN_SHAPE_RIGHT___POR 0x0 +#define PHYA_TXTD_ULD5_DESC_1_L__ULD5_CSR_WIN_SHAPE_LEFT___POR 0x0 +#define PHYA_TXTD_ULD5_DESC_1_L__ULD5_CSR_WIN_LENGTH_RIGHT___POR 0x00 +#define PHYA_TXTD_ULD5_DESC_1_L__ULD5_CSR_WIN_LENGTH_LEFT___POR 0x00 +#define PHYA_TXTD_ULD5_DESC_1_L__ULD5_CSR_WIN_SHAPE_RIGHT___M 0x01000000 +#define PHYA_TXTD_ULD5_DESC_1_L__ULD5_CSR_WIN_SHAPE_RIGHT___S 24 +#define PHYA_TXTD_ULD5_DESC_1_L__ULD5_CSR_WIN_SHAPE_LEFT___M 0x00010000 +#define PHYA_TXTD_ULD5_DESC_1_L__ULD5_CSR_WIN_SHAPE_LEFT___S 16 +#define PHYA_TXTD_ULD5_DESC_1_L__ULD5_CSR_WIN_LENGTH_RIGHT___M 0x00001F00 +#define PHYA_TXTD_ULD5_DESC_1_L__ULD5_CSR_WIN_LENGTH_RIGHT___S 8 +#define PHYA_TXTD_ULD5_DESC_1_L__ULD5_CSR_WIN_LENGTH_LEFT___M 0x0000001F +#define PHYA_TXTD_ULD5_DESC_1_L__ULD5_CSR_WIN_LENGTH_LEFT___S 0 +#define PHYA_TXTD_ULD5_DESC_1_L___M 0x01011F1F +#define PHYA_TXTD_ULD5_DESC_1_L___S 0 + +#define PHYA_TXTD_ULD5_DESC_1_U (0x003B04AC) +#define PHYA_TXTD_ULD5_DESC_1_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD5_DESC_1_U___POR 0x00000000 +#define PHYA_TXTD_ULD5_DESC_1_U__ULD5_CSR_POWER_SCALING_SEL___POR 0x0 +#define PHYA_TXTD_ULD5_DESC_1_U__ULD5_CSR_POWER_SCALING_SEL___M 0x00000007 +#define PHYA_TXTD_ULD5_DESC_1_U__ULD5_CSR_POWER_SCALING_SEL___S 0 +#define PHYA_TXTD_ULD5_DESC_1_U___M 0x00000007 +#define PHYA_TXTD_ULD5_DESC_1_U___S 0 + +#define PHYA_TXTD_ULD6_DESC_0_L (0x003B04B0) +#define PHYA_TXTD_ULD6_DESC_0_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD6_DESC_0_L___POR 0x00A00060 +#define PHYA_TXTD_ULD6_DESC_0_L__ULD6_CSR_ULD_SYM_CP_LEN___POR 0x0A0 +#define PHYA_TXTD_ULD6_DESC_0_L__ULD6_CSR_ULD_START_ADDR___POR 0x060 +#define PHYA_TXTD_ULD6_DESC_0_L__ULD6_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000 +#define PHYA_TXTD_ULD6_DESC_0_L__ULD6_CSR_ULD_SYM_CP_LEN___S 16 +#define PHYA_TXTD_ULD6_DESC_0_L__ULD6_CSR_ULD_START_ADDR___M 0x00000FFF +#define PHYA_TXTD_ULD6_DESC_0_L__ULD6_CSR_ULD_START_ADDR___S 0 +#define PHYA_TXTD_ULD6_DESC_0_L___M 0x0FFF0FFF +#define PHYA_TXTD_ULD6_DESC_0_L___S 0 + +#define PHYA_TXTD_ULD6_DESC_0_U (0x003B04B4) +#define PHYA_TXTD_ULD6_DESC_0_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD6_DESC_0_U___POR 0x02010102 +#define PHYA_TXTD_ULD6_DESC_0_U__ULD6_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x2 +#define PHYA_TXTD_ULD6_DESC_0_U__ULD6_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1 +#define PHYA_TXTD_ULD6_DESC_0_U__ULD6_CSR_ULD_DESC_DURATION___POR 0x1 +#define PHYA_TXTD_ULD6_DESC_0_U__ULD6_CSR_ULD_FFT_SIZE___POR 0x2 +#define PHYA_TXTD_ULD6_DESC_0_U__ULD6_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000 +#define PHYA_TXTD_ULD6_DESC_0_U__ULD6_CSR_ULD_APPLY_PER_CHN_CSD___S 24 +#define PHYA_TXTD_ULD6_DESC_0_U__ULD6_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000 +#define PHYA_TXTD_ULD6_DESC_0_U__ULD6_CSR_ULD_IFFT_BUF_REPEAT___S 16 +#define PHYA_TXTD_ULD6_DESC_0_U__ULD6_CSR_ULD_DESC_DURATION___M 0x00000F00 +#define PHYA_TXTD_ULD6_DESC_0_U__ULD6_CSR_ULD_DESC_DURATION___S 8 +#define PHYA_TXTD_ULD6_DESC_0_U__ULD6_CSR_ULD_FFT_SIZE___M 0x0000000F +#define PHYA_TXTD_ULD6_DESC_0_U__ULD6_CSR_ULD_FFT_SIZE___S 0 +#define PHYA_TXTD_ULD6_DESC_0_U___M 0x0F0F0F0F +#define PHYA_TXTD_ULD6_DESC_0_U___S 0 + +#define PHYA_TXTD_ULD6_DESC_1_L (0x003B04B8) +#define PHYA_TXTD_ULD6_DESC_1_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD6_DESC_1_L___POR 0x00000000 +#define PHYA_TXTD_ULD6_DESC_1_L__ULD6_CSR_WIN_SHAPE_RIGHT___POR 0x0 +#define PHYA_TXTD_ULD6_DESC_1_L__ULD6_CSR_WIN_SHAPE_LEFT___POR 0x0 +#define PHYA_TXTD_ULD6_DESC_1_L__ULD6_CSR_WIN_LENGTH_RIGHT___POR 0x00 +#define PHYA_TXTD_ULD6_DESC_1_L__ULD6_CSR_WIN_LENGTH_LEFT___POR 0x00 +#define PHYA_TXTD_ULD6_DESC_1_L__ULD6_CSR_WIN_SHAPE_RIGHT___M 0x01000000 +#define PHYA_TXTD_ULD6_DESC_1_L__ULD6_CSR_WIN_SHAPE_RIGHT___S 24 +#define PHYA_TXTD_ULD6_DESC_1_L__ULD6_CSR_WIN_SHAPE_LEFT___M 0x00010000 +#define PHYA_TXTD_ULD6_DESC_1_L__ULD6_CSR_WIN_SHAPE_LEFT___S 16 +#define PHYA_TXTD_ULD6_DESC_1_L__ULD6_CSR_WIN_LENGTH_RIGHT___M 0x00001F00 +#define PHYA_TXTD_ULD6_DESC_1_L__ULD6_CSR_WIN_LENGTH_RIGHT___S 8 +#define PHYA_TXTD_ULD6_DESC_1_L__ULD6_CSR_WIN_LENGTH_LEFT___M 0x0000001F +#define PHYA_TXTD_ULD6_DESC_1_L__ULD6_CSR_WIN_LENGTH_LEFT___S 0 +#define PHYA_TXTD_ULD6_DESC_1_L___M 0x01011F1F +#define PHYA_TXTD_ULD6_DESC_1_L___S 0 + +#define PHYA_TXTD_ULD6_DESC_1_U (0x003B04BC) +#define PHYA_TXTD_ULD6_DESC_1_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD6_DESC_1_U___POR 0x00000000 +#define PHYA_TXTD_ULD6_DESC_1_U__ULD6_CSR_POWER_SCALING_SEL___POR 0x0 +#define PHYA_TXTD_ULD6_DESC_1_U__ULD6_CSR_POWER_SCALING_SEL___M 0x00000007 +#define PHYA_TXTD_ULD6_DESC_1_U__ULD6_CSR_POWER_SCALING_SEL___S 0 +#define PHYA_TXTD_ULD6_DESC_1_U___M 0x00000007 +#define PHYA_TXTD_ULD6_DESC_1_U___S 0 + +#define PHYA_TXTD_ULD7_DESC_0_L (0x003B04C0) +#define PHYA_TXTD_ULD7_DESC_0_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD7_DESC_0_L___POR 0x00A00060 +#define PHYA_TXTD_ULD7_DESC_0_L__ULD7_CSR_ULD_SYM_CP_LEN___POR 0x0A0 +#define PHYA_TXTD_ULD7_DESC_0_L__ULD7_CSR_ULD_START_ADDR___POR 0x060 +#define PHYA_TXTD_ULD7_DESC_0_L__ULD7_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000 +#define PHYA_TXTD_ULD7_DESC_0_L__ULD7_CSR_ULD_SYM_CP_LEN___S 16 +#define PHYA_TXTD_ULD7_DESC_0_L__ULD7_CSR_ULD_START_ADDR___M 0x00000FFF +#define PHYA_TXTD_ULD7_DESC_0_L__ULD7_CSR_ULD_START_ADDR___S 0 +#define PHYA_TXTD_ULD7_DESC_0_L___M 0x0FFF0FFF +#define PHYA_TXTD_ULD7_DESC_0_L___S 0 + +#define PHYA_TXTD_ULD7_DESC_0_U (0x003B04C4) +#define PHYA_TXTD_ULD7_DESC_0_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD7_DESC_0_U___POR 0x02010102 +#define PHYA_TXTD_ULD7_DESC_0_U__ULD7_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x2 +#define PHYA_TXTD_ULD7_DESC_0_U__ULD7_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1 +#define PHYA_TXTD_ULD7_DESC_0_U__ULD7_CSR_ULD_DESC_DURATION___POR 0x1 +#define PHYA_TXTD_ULD7_DESC_0_U__ULD7_CSR_ULD_FFT_SIZE___POR 0x2 +#define PHYA_TXTD_ULD7_DESC_0_U__ULD7_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000 +#define PHYA_TXTD_ULD7_DESC_0_U__ULD7_CSR_ULD_APPLY_PER_CHN_CSD___S 24 +#define PHYA_TXTD_ULD7_DESC_0_U__ULD7_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000 +#define PHYA_TXTD_ULD7_DESC_0_U__ULD7_CSR_ULD_IFFT_BUF_REPEAT___S 16 +#define PHYA_TXTD_ULD7_DESC_0_U__ULD7_CSR_ULD_DESC_DURATION___M 0x00000F00 +#define PHYA_TXTD_ULD7_DESC_0_U__ULD7_CSR_ULD_DESC_DURATION___S 8 +#define PHYA_TXTD_ULD7_DESC_0_U__ULD7_CSR_ULD_FFT_SIZE___M 0x0000000F +#define PHYA_TXTD_ULD7_DESC_0_U__ULD7_CSR_ULD_FFT_SIZE___S 0 +#define PHYA_TXTD_ULD7_DESC_0_U___M 0x0F0F0F0F +#define PHYA_TXTD_ULD7_DESC_0_U___S 0 + +#define PHYA_TXTD_ULD7_DESC_1_L (0x003B04C8) +#define PHYA_TXTD_ULD7_DESC_1_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD7_DESC_1_L___POR 0x00000000 +#define PHYA_TXTD_ULD7_DESC_1_L__ULD7_CSR_WIN_SHAPE_RIGHT___POR 0x0 +#define PHYA_TXTD_ULD7_DESC_1_L__ULD7_CSR_WIN_SHAPE_LEFT___POR 0x0 +#define PHYA_TXTD_ULD7_DESC_1_L__ULD7_CSR_WIN_LENGTH_RIGHT___POR 0x00 +#define PHYA_TXTD_ULD7_DESC_1_L__ULD7_CSR_WIN_LENGTH_LEFT___POR 0x00 +#define PHYA_TXTD_ULD7_DESC_1_L__ULD7_CSR_WIN_SHAPE_RIGHT___M 0x01000000 +#define PHYA_TXTD_ULD7_DESC_1_L__ULD7_CSR_WIN_SHAPE_RIGHT___S 24 +#define PHYA_TXTD_ULD7_DESC_1_L__ULD7_CSR_WIN_SHAPE_LEFT___M 0x00010000 +#define PHYA_TXTD_ULD7_DESC_1_L__ULD7_CSR_WIN_SHAPE_LEFT___S 16 +#define PHYA_TXTD_ULD7_DESC_1_L__ULD7_CSR_WIN_LENGTH_RIGHT___M 0x00001F00 +#define PHYA_TXTD_ULD7_DESC_1_L__ULD7_CSR_WIN_LENGTH_RIGHT___S 8 +#define PHYA_TXTD_ULD7_DESC_1_L__ULD7_CSR_WIN_LENGTH_LEFT___M 0x0000001F +#define PHYA_TXTD_ULD7_DESC_1_L__ULD7_CSR_WIN_LENGTH_LEFT___S 0 +#define PHYA_TXTD_ULD7_DESC_1_L___M 0x01011F1F +#define PHYA_TXTD_ULD7_DESC_1_L___S 0 + +#define PHYA_TXTD_ULD7_DESC_1_U (0x003B04CC) +#define PHYA_TXTD_ULD7_DESC_1_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD7_DESC_1_U___POR 0x00000000 +#define PHYA_TXTD_ULD7_DESC_1_U__ULD7_CSR_POWER_SCALING_SEL___POR 0x0 +#define PHYA_TXTD_ULD7_DESC_1_U__ULD7_CSR_POWER_SCALING_SEL___M 0x00000007 +#define PHYA_TXTD_ULD7_DESC_1_U__ULD7_CSR_POWER_SCALING_SEL___S 0 +#define PHYA_TXTD_ULD7_DESC_1_U___M 0x00000007 +#define PHYA_TXTD_ULD7_DESC_1_U___S 0 + +#define PHYA_TXTD_ULD8_DESC_0_L (0x003B04D0) +#define PHYA_TXTD_ULD8_DESC_0_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD8_DESC_0_L___POR 0x00A00060 +#define PHYA_TXTD_ULD8_DESC_0_L__ULD8_CSR_ULD_SYM_CP_LEN___POR 0x0A0 +#define PHYA_TXTD_ULD8_DESC_0_L__ULD8_CSR_ULD_START_ADDR___POR 0x060 +#define PHYA_TXTD_ULD8_DESC_0_L__ULD8_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000 +#define PHYA_TXTD_ULD8_DESC_0_L__ULD8_CSR_ULD_SYM_CP_LEN___S 16 +#define PHYA_TXTD_ULD8_DESC_0_L__ULD8_CSR_ULD_START_ADDR___M 0x00000FFF +#define PHYA_TXTD_ULD8_DESC_0_L__ULD8_CSR_ULD_START_ADDR___S 0 +#define PHYA_TXTD_ULD8_DESC_0_L___M 0x0FFF0FFF +#define PHYA_TXTD_ULD8_DESC_0_L___S 0 + +#define PHYA_TXTD_ULD8_DESC_0_U (0x003B04D4) +#define PHYA_TXTD_ULD8_DESC_0_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD8_DESC_0_U___POR 0x02010102 +#define PHYA_TXTD_ULD8_DESC_0_U__ULD8_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x2 +#define PHYA_TXTD_ULD8_DESC_0_U__ULD8_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1 +#define PHYA_TXTD_ULD8_DESC_0_U__ULD8_CSR_ULD_DESC_DURATION___POR 0x1 +#define PHYA_TXTD_ULD8_DESC_0_U__ULD8_CSR_ULD_FFT_SIZE___POR 0x2 +#define PHYA_TXTD_ULD8_DESC_0_U__ULD8_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000 +#define PHYA_TXTD_ULD8_DESC_0_U__ULD8_CSR_ULD_APPLY_PER_CHN_CSD___S 24 +#define PHYA_TXTD_ULD8_DESC_0_U__ULD8_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000 +#define PHYA_TXTD_ULD8_DESC_0_U__ULD8_CSR_ULD_IFFT_BUF_REPEAT___S 16 +#define PHYA_TXTD_ULD8_DESC_0_U__ULD8_CSR_ULD_DESC_DURATION___M 0x00000F00 +#define PHYA_TXTD_ULD8_DESC_0_U__ULD8_CSR_ULD_DESC_DURATION___S 8 +#define PHYA_TXTD_ULD8_DESC_0_U__ULD8_CSR_ULD_FFT_SIZE___M 0x0000000F +#define PHYA_TXTD_ULD8_DESC_0_U__ULD8_CSR_ULD_FFT_SIZE___S 0 +#define PHYA_TXTD_ULD8_DESC_0_U___M 0x0F0F0F0F +#define PHYA_TXTD_ULD8_DESC_0_U___S 0 + +#define PHYA_TXTD_ULD8_DESC_1_L (0x003B04D8) +#define PHYA_TXTD_ULD8_DESC_1_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD8_DESC_1_L___POR 0x00000000 +#define PHYA_TXTD_ULD8_DESC_1_L__ULD8_CSR_WIN_SHAPE_RIGHT___POR 0x0 +#define PHYA_TXTD_ULD8_DESC_1_L__ULD8_CSR_WIN_SHAPE_LEFT___POR 0x0 +#define PHYA_TXTD_ULD8_DESC_1_L__ULD8_CSR_WIN_LENGTH_RIGHT___POR 0x00 +#define PHYA_TXTD_ULD8_DESC_1_L__ULD8_CSR_WIN_LENGTH_LEFT___POR 0x00 +#define PHYA_TXTD_ULD8_DESC_1_L__ULD8_CSR_WIN_SHAPE_RIGHT___M 0x01000000 +#define PHYA_TXTD_ULD8_DESC_1_L__ULD8_CSR_WIN_SHAPE_RIGHT___S 24 +#define PHYA_TXTD_ULD8_DESC_1_L__ULD8_CSR_WIN_SHAPE_LEFT___M 0x00010000 +#define PHYA_TXTD_ULD8_DESC_1_L__ULD8_CSR_WIN_SHAPE_LEFT___S 16 +#define PHYA_TXTD_ULD8_DESC_1_L__ULD8_CSR_WIN_LENGTH_RIGHT___M 0x00001F00 +#define PHYA_TXTD_ULD8_DESC_1_L__ULD8_CSR_WIN_LENGTH_RIGHT___S 8 +#define PHYA_TXTD_ULD8_DESC_1_L__ULD8_CSR_WIN_LENGTH_LEFT___M 0x0000001F +#define PHYA_TXTD_ULD8_DESC_1_L__ULD8_CSR_WIN_LENGTH_LEFT___S 0 +#define PHYA_TXTD_ULD8_DESC_1_L___M 0x01011F1F +#define PHYA_TXTD_ULD8_DESC_1_L___S 0 + +#define PHYA_TXTD_ULD8_DESC_1_U (0x003B04DC) +#define PHYA_TXTD_ULD8_DESC_1_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD8_DESC_1_U___POR 0x00000000 +#define PHYA_TXTD_ULD8_DESC_1_U__ULD8_CSR_POWER_SCALING_SEL___POR 0x0 +#define PHYA_TXTD_ULD8_DESC_1_U__ULD8_CSR_POWER_SCALING_SEL___M 0x00000007 +#define PHYA_TXTD_ULD8_DESC_1_U__ULD8_CSR_POWER_SCALING_SEL___S 0 +#define PHYA_TXTD_ULD8_DESC_1_U___M 0x00000007 +#define PHYA_TXTD_ULD8_DESC_1_U___S 0 + +#define PHYA_TXTD_ULD9_DESC_0_L (0x003B04E0) +#define PHYA_TXTD_ULD9_DESC_0_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD9_DESC_0_L___POR 0x00A00060 +#define PHYA_TXTD_ULD9_DESC_0_L__ULD9_CSR_ULD_SYM_CP_LEN___POR 0x0A0 +#define PHYA_TXTD_ULD9_DESC_0_L__ULD9_CSR_ULD_START_ADDR___POR 0x060 +#define PHYA_TXTD_ULD9_DESC_0_L__ULD9_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000 +#define PHYA_TXTD_ULD9_DESC_0_L__ULD9_CSR_ULD_SYM_CP_LEN___S 16 +#define PHYA_TXTD_ULD9_DESC_0_L__ULD9_CSR_ULD_START_ADDR___M 0x00000FFF +#define PHYA_TXTD_ULD9_DESC_0_L__ULD9_CSR_ULD_START_ADDR___S 0 +#define PHYA_TXTD_ULD9_DESC_0_L___M 0x0FFF0FFF +#define PHYA_TXTD_ULD9_DESC_0_L___S 0 + +#define PHYA_TXTD_ULD9_DESC_0_U (0x003B04E4) +#define PHYA_TXTD_ULD9_DESC_0_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD9_DESC_0_U___POR 0x02010002 +#define PHYA_TXTD_ULD9_DESC_0_U__ULD9_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x2 +#define PHYA_TXTD_ULD9_DESC_0_U__ULD9_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1 +#define PHYA_TXTD_ULD9_DESC_0_U__ULD9_CSR_ULD_DESC_DURATION___POR 0x0 +#define PHYA_TXTD_ULD9_DESC_0_U__ULD9_CSR_ULD_FFT_SIZE___POR 0x2 +#define PHYA_TXTD_ULD9_DESC_0_U__ULD9_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000 +#define PHYA_TXTD_ULD9_DESC_0_U__ULD9_CSR_ULD_APPLY_PER_CHN_CSD___S 24 +#define PHYA_TXTD_ULD9_DESC_0_U__ULD9_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000 +#define PHYA_TXTD_ULD9_DESC_0_U__ULD9_CSR_ULD_IFFT_BUF_REPEAT___S 16 +#define PHYA_TXTD_ULD9_DESC_0_U__ULD9_CSR_ULD_DESC_DURATION___M 0x00000F00 +#define PHYA_TXTD_ULD9_DESC_0_U__ULD9_CSR_ULD_DESC_DURATION___S 8 +#define PHYA_TXTD_ULD9_DESC_0_U__ULD9_CSR_ULD_FFT_SIZE___M 0x0000000F +#define PHYA_TXTD_ULD9_DESC_0_U__ULD9_CSR_ULD_FFT_SIZE___S 0 +#define PHYA_TXTD_ULD9_DESC_0_U___M 0x0F0F0F0F +#define PHYA_TXTD_ULD9_DESC_0_U___S 0 + +#define PHYA_TXTD_ULD9_DESC_1_L (0x003B04E8) +#define PHYA_TXTD_ULD9_DESC_1_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD9_DESC_1_L___POR 0x00000000 +#define PHYA_TXTD_ULD9_DESC_1_L__ULD9_CSR_WIN_SHAPE_RIGHT___POR 0x0 +#define PHYA_TXTD_ULD9_DESC_1_L__ULD9_CSR_WIN_SHAPE_LEFT___POR 0x0 +#define PHYA_TXTD_ULD9_DESC_1_L__ULD9_CSR_WIN_LENGTH_RIGHT___POR 0x00 +#define PHYA_TXTD_ULD9_DESC_1_L__ULD9_CSR_WIN_LENGTH_LEFT___POR 0x00 +#define PHYA_TXTD_ULD9_DESC_1_L__ULD9_CSR_WIN_SHAPE_RIGHT___M 0x01000000 +#define PHYA_TXTD_ULD9_DESC_1_L__ULD9_CSR_WIN_SHAPE_RIGHT___S 24 +#define PHYA_TXTD_ULD9_DESC_1_L__ULD9_CSR_WIN_SHAPE_LEFT___M 0x00010000 +#define PHYA_TXTD_ULD9_DESC_1_L__ULD9_CSR_WIN_SHAPE_LEFT___S 16 +#define PHYA_TXTD_ULD9_DESC_1_L__ULD9_CSR_WIN_LENGTH_RIGHT___M 0x00001F00 +#define PHYA_TXTD_ULD9_DESC_1_L__ULD9_CSR_WIN_LENGTH_RIGHT___S 8 +#define PHYA_TXTD_ULD9_DESC_1_L__ULD9_CSR_WIN_LENGTH_LEFT___M 0x0000001F +#define PHYA_TXTD_ULD9_DESC_1_L__ULD9_CSR_WIN_LENGTH_LEFT___S 0 +#define PHYA_TXTD_ULD9_DESC_1_L___M 0x01011F1F +#define PHYA_TXTD_ULD9_DESC_1_L___S 0 + +#define PHYA_TXTD_ULD9_DESC_1_U (0x003B04EC) +#define PHYA_TXTD_ULD9_DESC_1_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD9_DESC_1_U___POR 0x00000000 +#define PHYA_TXTD_ULD9_DESC_1_U__ULD9_CSR_POWER_SCALING_SEL___POR 0x0 +#define PHYA_TXTD_ULD9_DESC_1_U__ULD9_CSR_POWER_SCALING_SEL___M 0x00000007 +#define PHYA_TXTD_ULD9_DESC_1_U__ULD9_CSR_POWER_SCALING_SEL___S 0 +#define PHYA_TXTD_ULD9_DESC_1_U___M 0x00000007 +#define PHYA_TXTD_ULD9_DESC_1_U___S 0 + +#define PHYA_TXTD_ULD10_DESC_0_L (0x003B04F0) +#define PHYA_TXTD_ULD10_DESC_0_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD10_DESC_0_L___POR 0x00000000 +#define PHYA_TXTD_ULD10_DESC_0_L__ULD10_CSR_ULD_SYM_CP_LEN___POR 0x000 +#define PHYA_TXTD_ULD10_DESC_0_L__ULD10_CSR_ULD_START_ADDR___POR 0x000 +#define PHYA_TXTD_ULD10_DESC_0_L__ULD10_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000 +#define PHYA_TXTD_ULD10_DESC_0_L__ULD10_CSR_ULD_SYM_CP_LEN___S 16 +#define PHYA_TXTD_ULD10_DESC_0_L__ULD10_CSR_ULD_START_ADDR___M 0x00000FFF +#define PHYA_TXTD_ULD10_DESC_0_L__ULD10_CSR_ULD_START_ADDR___S 0 +#define PHYA_TXTD_ULD10_DESC_0_L___M 0x0FFF0FFF +#define PHYA_TXTD_ULD10_DESC_0_L___S 0 + +#define PHYA_TXTD_ULD10_DESC_0_U (0x003B04F4) +#define PHYA_TXTD_ULD10_DESC_0_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD10_DESC_0_U___POR 0x00010000 +#define PHYA_TXTD_ULD10_DESC_0_U__ULD10_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x0 +#define PHYA_TXTD_ULD10_DESC_0_U__ULD10_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1 +#define PHYA_TXTD_ULD10_DESC_0_U__ULD10_CSR_ULD_DESC_DURATION___POR 0x0 +#define PHYA_TXTD_ULD10_DESC_0_U__ULD10_CSR_ULD_FFT_SIZE___POR 0x0 +#define PHYA_TXTD_ULD10_DESC_0_U__ULD10_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000 +#define PHYA_TXTD_ULD10_DESC_0_U__ULD10_CSR_ULD_APPLY_PER_CHN_CSD___S 24 +#define PHYA_TXTD_ULD10_DESC_0_U__ULD10_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000 +#define PHYA_TXTD_ULD10_DESC_0_U__ULD10_CSR_ULD_IFFT_BUF_REPEAT___S 16 +#define PHYA_TXTD_ULD10_DESC_0_U__ULD10_CSR_ULD_DESC_DURATION___M 0x00000F00 +#define PHYA_TXTD_ULD10_DESC_0_U__ULD10_CSR_ULD_DESC_DURATION___S 8 +#define PHYA_TXTD_ULD10_DESC_0_U__ULD10_CSR_ULD_FFT_SIZE___M 0x0000000F +#define PHYA_TXTD_ULD10_DESC_0_U__ULD10_CSR_ULD_FFT_SIZE___S 0 +#define PHYA_TXTD_ULD10_DESC_0_U___M 0x0F0F0F0F +#define PHYA_TXTD_ULD10_DESC_0_U___S 0 + +#define PHYA_TXTD_ULD10_DESC_1_L (0x003B04F8) +#define PHYA_TXTD_ULD10_DESC_1_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD10_DESC_1_L___POR 0x00000000 +#define PHYA_TXTD_ULD10_DESC_1_L__ULD10_CSR_WIN_SHAPE_RIGHT___POR 0x0 +#define PHYA_TXTD_ULD10_DESC_1_L__ULD10_CSR_WIN_SHAPE_LEFT___POR 0x0 +#define PHYA_TXTD_ULD10_DESC_1_L__ULD10_CSR_WIN_LENGTH_RIGHT___POR 0x00 +#define PHYA_TXTD_ULD10_DESC_1_L__ULD10_CSR_WIN_LENGTH_LEFT___POR 0x00 +#define PHYA_TXTD_ULD10_DESC_1_L__ULD10_CSR_WIN_SHAPE_RIGHT___M 0x01000000 +#define PHYA_TXTD_ULD10_DESC_1_L__ULD10_CSR_WIN_SHAPE_RIGHT___S 24 +#define PHYA_TXTD_ULD10_DESC_1_L__ULD10_CSR_WIN_SHAPE_LEFT___M 0x00010000 +#define PHYA_TXTD_ULD10_DESC_1_L__ULD10_CSR_WIN_SHAPE_LEFT___S 16 +#define PHYA_TXTD_ULD10_DESC_1_L__ULD10_CSR_WIN_LENGTH_RIGHT___M 0x00001F00 +#define PHYA_TXTD_ULD10_DESC_1_L__ULD10_CSR_WIN_LENGTH_RIGHT___S 8 +#define PHYA_TXTD_ULD10_DESC_1_L__ULD10_CSR_WIN_LENGTH_LEFT___M 0x0000001F +#define PHYA_TXTD_ULD10_DESC_1_L__ULD10_CSR_WIN_LENGTH_LEFT___S 0 +#define PHYA_TXTD_ULD10_DESC_1_L___M 0x01011F1F +#define PHYA_TXTD_ULD10_DESC_1_L___S 0 + +#define PHYA_TXTD_ULD10_DESC_1_U (0x003B04FC) +#define PHYA_TXTD_ULD10_DESC_1_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD10_DESC_1_U___POR 0x00000000 +#define PHYA_TXTD_ULD10_DESC_1_U__ULD10_CSR_POWER_SCALING_SEL___POR 0x0 +#define PHYA_TXTD_ULD10_DESC_1_U__ULD10_CSR_POWER_SCALING_SEL___M 0x00000007 +#define PHYA_TXTD_ULD10_DESC_1_U__ULD10_CSR_POWER_SCALING_SEL___S 0 +#define PHYA_TXTD_ULD10_DESC_1_U___M 0x00000007 +#define PHYA_TXTD_ULD10_DESC_1_U___S 0 + +#define PHYA_TXTD_ULD11_DESC_0_L (0x003B0500) +#define PHYA_TXTD_ULD11_DESC_0_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD11_DESC_0_L___POR 0x00000000 +#define PHYA_TXTD_ULD11_DESC_0_L__ULD11_CSR_ULD_SYM_CP_LEN___POR 0x000 +#define PHYA_TXTD_ULD11_DESC_0_L__ULD11_CSR_ULD_START_ADDR___POR 0x000 +#define PHYA_TXTD_ULD11_DESC_0_L__ULD11_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000 +#define PHYA_TXTD_ULD11_DESC_0_L__ULD11_CSR_ULD_SYM_CP_LEN___S 16 +#define PHYA_TXTD_ULD11_DESC_0_L__ULD11_CSR_ULD_START_ADDR___M 0x00000FFF +#define PHYA_TXTD_ULD11_DESC_0_L__ULD11_CSR_ULD_START_ADDR___S 0 +#define PHYA_TXTD_ULD11_DESC_0_L___M 0x0FFF0FFF +#define PHYA_TXTD_ULD11_DESC_0_L___S 0 + +#define PHYA_TXTD_ULD11_DESC_0_U (0x003B0504) +#define PHYA_TXTD_ULD11_DESC_0_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD11_DESC_0_U___POR 0x00010000 +#define PHYA_TXTD_ULD11_DESC_0_U__ULD11_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x0 +#define PHYA_TXTD_ULD11_DESC_0_U__ULD11_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1 +#define PHYA_TXTD_ULD11_DESC_0_U__ULD11_CSR_ULD_DESC_DURATION___POR 0x0 +#define PHYA_TXTD_ULD11_DESC_0_U__ULD11_CSR_ULD_FFT_SIZE___POR 0x0 +#define PHYA_TXTD_ULD11_DESC_0_U__ULD11_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000 +#define PHYA_TXTD_ULD11_DESC_0_U__ULD11_CSR_ULD_APPLY_PER_CHN_CSD___S 24 +#define PHYA_TXTD_ULD11_DESC_0_U__ULD11_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000 +#define PHYA_TXTD_ULD11_DESC_0_U__ULD11_CSR_ULD_IFFT_BUF_REPEAT___S 16 +#define PHYA_TXTD_ULD11_DESC_0_U__ULD11_CSR_ULD_DESC_DURATION___M 0x00000F00 +#define PHYA_TXTD_ULD11_DESC_0_U__ULD11_CSR_ULD_DESC_DURATION___S 8 +#define PHYA_TXTD_ULD11_DESC_0_U__ULD11_CSR_ULD_FFT_SIZE___M 0x0000000F +#define PHYA_TXTD_ULD11_DESC_0_U__ULD11_CSR_ULD_FFT_SIZE___S 0 +#define PHYA_TXTD_ULD11_DESC_0_U___M 0x0F0F0F0F +#define PHYA_TXTD_ULD11_DESC_0_U___S 0 + +#define PHYA_TXTD_ULD11_DESC_1_L (0x003B0508) +#define PHYA_TXTD_ULD11_DESC_1_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD11_DESC_1_L___POR 0x00000000 +#define PHYA_TXTD_ULD11_DESC_1_L__ULD11_CSR_WIN_SHAPE_RIGHT___POR 0x0 +#define PHYA_TXTD_ULD11_DESC_1_L__ULD11_CSR_WIN_SHAPE_LEFT___POR 0x0 +#define PHYA_TXTD_ULD11_DESC_1_L__ULD11_CSR_WIN_LENGTH_RIGHT___POR 0x00 +#define PHYA_TXTD_ULD11_DESC_1_L__ULD11_CSR_WIN_LENGTH_LEFT___POR 0x00 +#define PHYA_TXTD_ULD11_DESC_1_L__ULD11_CSR_WIN_SHAPE_RIGHT___M 0x01000000 +#define PHYA_TXTD_ULD11_DESC_1_L__ULD11_CSR_WIN_SHAPE_RIGHT___S 24 +#define PHYA_TXTD_ULD11_DESC_1_L__ULD11_CSR_WIN_SHAPE_LEFT___M 0x00010000 +#define PHYA_TXTD_ULD11_DESC_1_L__ULD11_CSR_WIN_SHAPE_LEFT___S 16 +#define PHYA_TXTD_ULD11_DESC_1_L__ULD11_CSR_WIN_LENGTH_RIGHT___M 0x00001F00 +#define PHYA_TXTD_ULD11_DESC_1_L__ULD11_CSR_WIN_LENGTH_RIGHT___S 8 +#define PHYA_TXTD_ULD11_DESC_1_L__ULD11_CSR_WIN_LENGTH_LEFT___M 0x0000001F +#define PHYA_TXTD_ULD11_DESC_1_L__ULD11_CSR_WIN_LENGTH_LEFT___S 0 +#define PHYA_TXTD_ULD11_DESC_1_L___M 0x01011F1F +#define PHYA_TXTD_ULD11_DESC_1_L___S 0 + +#define PHYA_TXTD_ULD11_DESC_1_U (0x003B050C) +#define PHYA_TXTD_ULD11_DESC_1_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD11_DESC_1_U___POR 0x00000000 +#define PHYA_TXTD_ULD11_DESC_1_U__ULD11_CSR_POWER_SCALING_SEL___POR 0x0 +#define PHYA_TXTD_ULD11_DESC_1_U__ULD11_CSR_POWER_SCALING_SEL___M 0x00000007 +#define PHYA_TXTD_ULD11_DESC_1_U__ULD11_CSR_POWER_SCALING_SEL___S 0 +#define PHYA_TXTD_ULD11_DESC_1_U___M 0x00000007 +#define PHYA_TXTD_ULD11_DESC_1_U___S 0 + +#define PHYA_TXTD_ULD12_DESC_0_L (0x003B0510) +#define PHYA_TXTD_ULD12_DESC_0_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD12_DESC_0_L___POR 0x00000000 +#define PHYA_TXTD_ULD12_DESC_0_L__ULD12_CSR_ULD_SYM_CP_LEN___POR 0x000 +#define PHYA_TXTD_ULD12_DESC_0_L__ULD12_CSR_ULD_START_ADDR___POR 0x000 +#define PHYA_TXTD_ULD12_DESC_0_L__ULD12_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000 +#define PHYA_TXTD_ULD12_DESC_0_L__ULD12_CSR_ULD_SYM_CP_LEN___S 16 +#define PHYA_TXTD_ULD12_DESC_0_L__ULD12_CSR_ULD_START_ADDR___M 0x00000FFF +#define PHYA_TXTD_ULD12_DESC_0_L__ULD12_CSR_ULD_START_ADDR___S 0 +#define PHYA_TXTD_ULD12_DESC_0_L___M 0x0FFF0FFF +#define PHYA_TXTD_ULD12_DESC_0_L___S 0 + +#define PHYA_TXTD_ULD12_DESC_0_U (0x003B0514) +#define PHYA_TXTD_ULD12_DESC_0_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD12_DESC_0_U___POR 0x00010000 +#define PHYA_TXTD_ULD12_DESC_0_U__ULD12_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x0 +#define PHYA_TXTD_ULD12_DESC_0_U__ULD12_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1 +#define PHYA_TXTD_ULD12_DESC_0_U__ULD12_CSR_ULD_DESC_DURATION___POR 0x0 +#define PHYA_TXTD_ULD12_DESC_0_U__ULD12_CSR_ULD_FFT_SIZE___POR 0x0 +#define PHYA_TXTD_ULD12_DESC_0_U__ULD12_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000 +#define PHYA_TXTD_ULD12_DESC_0_U__ULD12_CSR_ULD_APPLY_PER_CHN_CSD___S 24 +#define PHYA_TXTD_ULD12_DESC_0_U__ULD12_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000 +#define PHYA_TXTD_ULD12_DESC_0_U__ULD12_CSR_ULD_IFFT_BUF_REPEAT___S 16 +#define PHYA_TXTD_ULD12_DESC_0_U__ULD12_CSR_ULD_DESC_DURATION___M 0x00000F00 +#define PHYA_TXTD_ULD12_DESC_0_U__ULD12_CSR_ULD_DESC_DURATION___S 8 +#define PHYA_TXTD_ULD12_DESC_0_U__ULD12_CSR_ULD_FFT_SIZE___M 0x0000000F +#define PHYA_TXTD_ULD12_DESC_0_U__ULD12_CSR_ULD_FFT_SIZE___S 0 +#define PHYA_TXTD_ULD12_DESC_0_U___M 0x0F0F0F0F +#define PHYA_TXTD_ULD12_DESC_0_U___S 0 + +#define PHYA_TXTD_ULD12_DESC_1_L (0x003B0518) +#define PHYA_TXTD_ULD12_DESC_1_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD12_DESC_1_L___POR 0x00000000 +#define PHYA_TXTD_ULD12_DESC_1_L__ULD12_CSR_WIN_SHAPE_RIGHT___POR 0x0 +#define PHYA_TXTD_ULD12_DESC_1_L__ULD12_CSR_WIN_SHAPE_LEFT___POR 0x0 +#define PHYA_TXTD_ULD12_DESC_1_L__ULD12_CSR_WIN_LENGTH_RIGHT___POR 0x00 +#define PHYA_TXTD_ULD12_DESC_1_L__ULD12_CSR_WIN_LENGTH_LEFT___POR 0x00 +#define PHYA_TXTD_ULD12_DESC_1_L__ULD12_CSR_WIN_SHAPE_RIGHT___M 0x01000000 +#define PHYA_TXTD_ULD12_DESC_1_L__ULD12_CSR_WIN_SHAPE_RIGHT___S 24 +#define PHYA_TXTD_ULD12_DESC_1_L__ULD12_CSR_WIN_SHAPE_LEFT___M 0x00010000 +#define PHYA_TXTD_ULD12_DESC_1_L__ULD12_CSR_WIN_SHAPE_LEFT___S 16 +#define PHYA_TXTD_ULD12_DESC_1_L__ULD12_CSR_WIN_LENGTH_RIGHT___M 0x00001F00 +#define PHYA_TXTD_ULD12_DESC_1_L__ULD12_CSR_WIN_LENGTH_RIGHT___S 8 +#define PHYA_TXTD_ULD12_DESC_1_L__ULD12_CSR_WIN_LENGTH_LEFT___M 0x0000001F +#define PHYA_TXTD_ULD12_DESC_1_L__ULD12_CSR_WIN_LENGTH_LEFT___S 0 +#define PHYA_TXTD_ULD12_DESC_1_L___M 0x01011F1F +#define PHYA_TXTD_ULD12_DESC_1_L___S 0 + +#define PHYA_TXTD_ULD12_DESC_1_U (0x003B051C) +#define PHYA_TXTD_ULD12_DESC_1_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD12_DESC_1_U___POR 0x00000000 +#define PHYA_TXTD_ULD12_DESC_1_U__ULD12_CSR_POWER_SCALING_SEL___POR 0x0 +#define PHYA_TXTD_ULD12_DESC_1_U__ULD12_CSR_POWER_SCALING_SEL___M 0x00000007 +#define PHYA_TXTD_ULD12_DESC_1_U__ULD12_CSR_POWER_SCALING_SEL___S 0 +#define PHYA_TXTD_ULD12_DESC_1_U___M 0x00000007 +#define PHYA_TXTD_ULD12_DESC_1_U___S 0 + +#define PHYA_TXTD_ULD13_DESC_0_L (0x003B0520) +#define PHYA_TXTD_ULD13_DESC_0_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD13_DESC_0_L___POR 0x00000000 +#define PHYA_TXTD_ULD13_DESC_0_L__ULD13_CSR_ULD_SYM_CP_LEN___POR 0x000 +#define PHYA_TXTD_ULD13_DESC_0_L__ULD13_CSR_ULD_START_ADDR___POR 0x000 +#define PHYA_TXTD_ULD13_DESC_0_L__ULD13_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000 +#define PHYA_TXTD_ULD13_DESC_0_L__ULD13_CSR_ULD_SYM_CP_LEN___S 16 +#define PHYA_TXTD_ULD13_DESC_0_L__ULD13_CSR_ULD_START_ADDR___M 0x00000FFF +#define PHYA_TXTD_ULD13_DESC_0_L__ULD13_CSR_ULD_START_ADDR___S 0 +#define PHYA_TXTD_ULD13_DESC_0_L___M 0x0FFF0FFF +#define PHYA_TXTD_ULD13_DESC_0_L___S 0 + +#define PHYA_TXTD_ULD13_DESC_0_U (0x003B0524) +#define PHYA_TXTD_ULD13_DESC_0_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD13_DESC_0_U___POR 0x00010000 +#define PHYA_TXTD_ULD13_DESC_0_U__ULD13_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x0 +#define PHYA_TXTD_ULD13_DESC_0_U__ULD13_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1 +#define PHYA_TXTD_ULD13_DESC_0_U__ULD13_CSR_ULD_DESC_DURATION___POR 0x0 +#define PHYA_TXTD_ULD13_DESC_0_U__ULD13_CSR_ULD_FFT_SIZE___POR 0x0 +#define PHYA_TXTD_ULD13_DESC_0_U__ULD13_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000 +#define PHYA_TXTD_ULD13_DESC_0_U__ULD13_CSR_ULD_APPLY_PER_CHN_CSD___S 24 +#define PHYA_TXTD_ULD13_DESC_0_U__ULD13_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000 +#define PHYA_TXTD_ULD13_DESC_0_U__ULD13_CSR_ULD_IFFT_BUF_REPEAT___S 16 +#define PHYA_TXTD_ULD13_DESC_0_U__ULD13_CSR_ULD_DESC_DURATION___M 0x00000F00 +#define PHYA_TXTD_ULD13_DESC_0_U__ULD13_CSR_ULD_DESC_DURATION___S 8 +#define PHYA_TXTD_ULD13_DESC_0_U__ULD13_CSR_ULD_FFT_SIZE___M 0x0000000F +#define PHYA_TXTD_ULD13_DESC_0_U__ULD13_CSR_ULD_FFT_SIZE___S 0 +#define PHYA_TXTD_ULD13_DESC_0_U___M 0x0F0F0F0F +#define PHYA_TXTD_ULD13_DESC_0_U___S 0 + +#define PHYA_TXTD_ULD13_DESC_1_L (0x003B0528) +#define PHYA_TXTD_ULD13_DESC_1_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD13_DESC_1_L___POR 0x00000000 +#define PHYA_TXTD_ULD13_DESC_1_L__ULD13_CSR_WIN_SHAPE_RIGHT___POR 0x0 +#define PHYA_TXTD_ULD13_DESC_1_L__ULD13_CSR_WIN_SHAPE_LEFT___POR 0x0 +#define PHYA_TXTD_ULD13_DESC_1_L__ULD13_CSR_WIN_LENGTH_RIGHT___POR 0x00 +#define PHYA_TXTD_ULD13_DESC_1_L__ULD13_CSR_WIN_LENGTH_LEFT___POR 0x00 +#define PHYA_TXTD_ULD13_DESC_1_L__ULD13_CSR_WIN_SHAPE_RIGHT___M 0x01000000 +#define PHYA_TXTD_ULD13_DESC_1_L__ULD13_CSR_WIN_SHAPE_RIGHT___S 24 +#define PHYA_TXTD_ULD13_DESC_1_L__ULD13_CSR_WIN_SHAPE_LEFT___M 0x00010000 +#define PHYA_TXTD_ULD13_DESC_1_L__ULD13_CSR_WIN_SHAPE_LEFT___S 16 +#define PHYA_TXTD_ULD13_DESC_1_L__ULD13_CSR_WIN_LENGTH_RIGHT___M 0x00001F00 +#define PHYA_TXTD_ULD13_DESC_1_L__ULD13_CSR_WIN_LENGTH_RIGHT___S 8 +#define PHYA_TXTD_ULD13_DESC_1_L__ULD13_CSR_WIN_LENGTH_LEFT___M 0x0000001F +#define PHYA_TXTD_ULD13_DESC_1_L__ULD13_CSR_WIN_LENGTH_LEFT___S 0 +#define PHYA_TXTD_ULD13_DESC_1_L___M 0x01011F1F +#define PHYA_TXTD_ULD13_DESC_1_L___S 0 + +#define PHYA_TXTD_ULD13_DESC_1_U (0x003B052C) +#define PHYA_TXTD_ULD13_DESC_1_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD13_DESC_1_U___POR 0x00000000 +#define PHYA_TXTD_ULD13_DESC_1_U__ULD13_CSR_POWER_SCALING_SEL___POR 0x0 +#define PHYA_TXTD_ULD13_DESC_1_U__ULD13_CSR_POWER_SCALING_SEL___M 0x00000007 +#define PHYA_TXTD_ULD13_DESC_1_U__ULD13_CSR_POWER_SCALING_SEL___S 0 +#define PHYA_TXTD_ULD13_DESC_1_U___M 0x00000007 +#define PHYA_TXTD_ULD13_DESC_1_U___S 0 + +#define PHYA_TXTD_ULD14_DESC_0_L (0x003B0530) +#define PHYA_TXTD_ULD14_DESC_0_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD14_DESC_0_L___POR 0x00000000 +#define PHYA_TXTD_ULD14_DESC_0_L__ULD14_CSR_ULD_SYM_CP_LEN___POR 0x000 +#define PHYA_TXTD_ULD14_DESC_0_L__ULD14_CSR_ULD_START_ADDR___POR 0x000 +#define PHYA_TXTD_ULD14_DESC_0_L__ULD14_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000 +#define PHYA_TXTD_ULD14_DESC_0_L__ULD14_CSR_ULD_SYM_CP_LEN___S 16 +#define PHYA_TXTD_ULD14_DESC_0_L__ULD14_CSR_ULD_START_ADDR___M 0x00000FFF +#define PHYA_TXTD_ULD14_DESC_0_L__ULD14_CSR_ULD_START_ADDR___S 0 +#define PHYA_TXTD_ULD14_DESC_0_L___M 0x0FFF0FFF +#define PHYA_TXTD_ULD14_DESC_0_L___S 0 + +#define PHYA_TXTD_ULD14_DESC_0_U (0x003B0534) +#define PHYA_TXTD_ULD14_DESC_0_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD14_DESC_0_U___POR 0x00010000 +#define PHYA_TXTD_ULD14_DESC_0_U__ULD14_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x0 +#define PHYA_TXTD_ULD14_DESC_0_U__ULD14_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1 +#define PHYA_TXTD_ULD14_DESC_0_U__ULD14_CSR_ULD_DESC_DURATION___POR 0x0 +#define PHYA_TXTD_ULD14_DESC_0_U__ULD14_CSR_ULD_FFT_SIZE___POR 0x0 +#define PHYA_TXTD_ULD14_DESC_0_U__ULD14_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000 +#define PHYA_TXTD_ULD14_DESC_0_U__ULD14_CSR_ULD_APPLY_PER_CHN_CSD___S 24 +#define PHYA_TXTD_ULD14_DESC_0_U__ULD14_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000 +#define PHYA_TXTD_ULD14_DESC_0_U__ULD14_CSR_ULD_IFFT_BUF_REPEAT___S 16 +#define PHYA_TXTD_ULD14_DESC_0_U__ULD14_CSR_ULD_DESC_DURATION___M 0x00000F00 +#define PHYA_TXTD_ULD14_DESC_0_U__ULD14_CSR_ULD_DESC_DURATION___S 8 +#define PHYA_TXTD_ULD14_DESC_0_U__ULD14_CSR_ULD_FFT_SIZE___M 0x0000000F +#define PHYA_TXTD_ULD14_DESC_0_U__ULD14_CSR_ULD_FFT_SIZE___S 0 +#define PHYA_TXTD_ULD14_DESC_0_U___M 0x0F0F0F0F +#define PHYA_TXTD_ULD14_DESC_0_U___S 0 + +#define PHYA_TXTD_ULD14_DESC_1_L (0x003B0538) +#define PHYA_TXTD_ULD14_DESC_1_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD14_DESC_1_L___POR 0x00000000 +#define PHYA_TXTD_ULD14_DESC_1_L__ULD14_CSR_WIN_SHAPE_RIGHT___POR 0x0 +#define PHYA_TXTD_ULD14_DESC_1_L__ULD14_CSR_WIN_SHAPE_LEFT___POR 0x0 +#define PHYA_TXTD_ULD14_DESC_1_L__ULD14_CSR_WIN_LENGTH_RIGHT___POR 0x00 +#define PHYA_TXTD_ULD14_DESC_1_L__ULD14_CSR_WIN_LENGTH_LEFT___POR 0x00 +#define PHYA_TXTD_ULD14_DESC_1_L__ULD14_CSR_WIN_SHAPE_RIGHT___M 0x01000000 +#define PHYA_TXTD_ULD14_DESC_1_L__ULD14_CSR_WIN_SHAPE_RIGHT___S 24 +#define PHYA_TXTD_ULD14_DESC_1_L__ULD14_CSR_WIN_SHAPE_LEFT___M 0x00010000 +#define PHYA_TXTD_ULD14_DESC_1_L__ULD14_CSR_WIN_SHAPE_LEFT___S 16 +#define PHYA_TXTD_ULD14_DESC_1_L__ULD14_CSR_WIN_LENGTH_RIGHT___M 0x00001F00 +#define PHYA_TXTD_ULD14_DESC_1_L__ULD14_CSR_WIN_LENGTH_RIGHT___S 8 +#define PHYA_TXTD_ULD14_DESC_1_L__ULD14_CSR_WIN_LENGTH_LEFT___M 0x0000001F +#define PHYA_TXTD_ULD14_DESC_1_L__ULD14_CSR_WIN_LENGTH_LEFT___S 0 +#define PHYA_TXTD_ULD14_DESC_1_L___M 0x01011F1F +#define PHYA_TXTD_ULD14_DESC_1_L___S 0 + +#define PHYA_TXTD_ULD14_DESC_1_U (0x003B053C) +#define PHYA_TXTD_ULD14_DESC_1_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD14_DESC_1_U___POR 0x00000000 +#define PHYA_TXTD_ULD14_DESC_1_U__ULD14_CSR_POWER_SCALING_SEL___POR 0x0 +#define PHYA_TXTD_ULD14_DESC_1_U__ULD14_CSR_POWER_SCALING_SEL___M 0x00000007 +#define PHYA_TXTD_ULD14_DESC_1_U__ULD14_CSR_POWER_SCALING_SEL___S 0 +#define PHYA_TXTD_ULD14_DESC_1_U___M 0x00000007 +#define PHYA_TXTD_ULD14_DESC_1_U___S 0 + +#define PHYA_TXTD_ULD15_DESC_0_L (0x003B0540) +#define PHYA_TXTD_ULD15_DESC_0_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD15_DESC_0_L___POR 0x00000000 +#define PHYA_TXTD_ULD15_DESC_0_L__ULD15_CSR_ULD_SYM_CP_LEN___POR 0x000 +#define PHYA_TXTD_ULD15_DESC_0_L__ULD15_CSR_ULD_START_ADDR___POR 0x000 +#define PHYA_TXTD_ULD15_DESC_0_L__ULD15_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000 +#define PHYA_TXTD_ULD15_DESC_0_L__ULD15_CSR_ULD_SYM_CP_LEN___S 16 +#define PHYA_TXTD_ULD15_DESC_0_L__ULD15_CSR_ULD_START_ADDR___M 0x00000FFF +#define PHYA_TXTD_ULD15_DESC_0_L__ULD15_CSR_ULD_START_ADDR___S 0 +#define PHYA_TXTD_ULD15_DESC_0_L___M 0x0FFF0FFF +#define PHYA_TXTD_ULD15_DESC_0_L___S 0 + +#define PHYA_TXTD_ULD15_DESC_0_U (0x003B0544) +#define PHYA_TXTD_ULD15_DESC_0_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD15_DESC_0_U___POR 0x00010000 +#define PHYA_TXTD_ULD15_DESC_0_U__ULD15_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x0 +#define PHYA_TXTD_ULD15_DESC_0_U__ULD15_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1 +#define PHYA_TXTD_ULD15_DESC_0_U__ULD15_CSR_ULD_DESC_DURATION___POR 0x0 +#define PHYA_TXTD_ULD15_DESC_0_U__ULD15_CSR_ULD_FFT_SIZE___POR 0x0 +#define PHYA_TXTD_ULD15_DESC_0_U__ULD15_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000 +#define PHYA_TXTD_ULD15_DESC_0_U__ULD15_CSR_ULD_APPLY_PER_CHN_CSD___S 24 +#define PHYA_TXTD_ULD15_DESC_0_U__ULD15_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000 +#define PHYA_TXTD_ULD15_DESC_0_U__ULD15_CSR_ULD_IFFT_BUF_REPEAT___S 16 +#define PHYA_TXTD_ULD15_DESC_0_U__ULD15_CSR_ULD_DESC_DURATION___M 0x00000F00 +#define PHYA_TXTD_ULD15_DESC_0_U__ULD15_CSR_ULD_DESC_DURATION___S 8 +#define PHYA_TXTD_ULD15_DESC_0_U__ULD15_CSR_ULD_FFT_SIZE___M 0x0000000F +#define PHYA_TXTD_ULD15_DESC_0_U__ULD15_CSR_ULD_FFT_SIZE___S 0 +#define PHYA_TXTD_ULD15_DESC_0_U___M 0x0F0F0F0F +#define PHYA_TXTD_ULD15_DESC_0_U___S 0 + +#define PHYA_TXTD_ULD15_DESC_1_L (0x003B0548) +#define PHYA_TXTD_ULD15_DESC_1_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD15_DESC_1_L___POR 0x00000000 +#define PHYA_TXTD_ULD15_DESC_1_L__ULD15_CSR_WIN_SHAPE_RIGHT___POR 0x0 +#define PHYA_TXTD_ULD15_DESC_1_L__ULD15_CSR_WIN_SHAPE_LEFT___POR 0x0 +#define PHYA_TXTD_ULD15_DESC_1_L__ULD15_CSR_WIN_LENGTH_RIGHT___POR 0x00 +#define PHYA_TXTD_ULD15_DESC_1_L__ULD15_CSR_WIN_LENGTH_LEFT___POR 0x00 +#define PHYA_TXTD_ULD15_DESC_1_L__ULD15_CSR_WIN_SHAPE_RIGHT___M 0x01000000 +#define PHYA_TXTD_ULD15_DESC_1_L__ULD15_CSR_WIN_SHAPE_RIGHT___S 24 +#define PHYA_TXTD_ULD15_DESC_1_L__ULD15_CSR_WIN_SHAPE_LEFT___M 0x00010000 +#define PHYA_TXTD_ULD15_DESC_1_L__ULD15_CSR_WIN_SHAPE_LEFT___S 16 +#define PHYA_TXTD_ULD15_DESC_1_L__ULD15_CSR_WIN_LENGTH_RIGHT___M 0x00001F00 +#define PHYA_TXTD_ULD15_DESC_1_L__ULD15_CSR_WIN_LENGTH_RIGHT___S 8 +#define PHYA_TXTD_ULD15_DESC_1_L__ULD15_CSR_WIN_LENGTH_LEFT___M 0x0000001F +#define PHYA_TXTD_ULD15_DESC_1_L__ULD15_CSR_WIN_LENGTH_LEFT___S 0 +#define PHYA_TXTD_ULD15_DESC_1_L___M 0x01011F1F +#define PHYA_TXTD_ULD15_DESC_1_L___S 0 + +#define PHYA_TXTD_ULD15_DESC_1_U (0x003B054C) +#define PHYA_TXTD_ULD15_DESC_1_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD15_DESC_1_U___POR 0x00000000 +#define PHYA_TXTD_ULD15_DESC_1_U__ULD15_CSR_POWER_SCALING_SEL___POR 0x0 +#define PHYA_TXTD_ULD15_DESC_1_U__ULD15_CSR_POWER_SCALING_SEL___M 0x00000007 +#define PHYA_TXTD_ULD15_DESC_1_U__ULD15_CSR_POWER_SCALING_SEL___S 0 +#define PHYA_TXTD_ULD15_DESC_1_U___M 0x00000007 +#define PHYA_TXTD_ULD15_DESC_1_U___S 0 + +#define PHYA_TXTD_ULD16_DESC_0_L (0x003B0550) +#define PHYA_TXTD_ULD16_DESC_0_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD16_DESC_0_L___POR 0x00000000 +#define PHYA_TXTD_ULD16_DESC_0_L__ULD16_CSR_ULD_SYM_CP_LEN___POR 0x000 +#define PHYA_TXTD_ULD16_DESC_0_L__ULD16_CSR_ULD_START_ADDR___POR 0x000 +#define PHYA_TXTD_ULD16_DESC_0_L__ULD16_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000 +#define PHYA_TXTD_ULD16_DESC_0_L__ULD16_CSR_ULD_SYM_CP_LEN___S 16 +#define PHYA_TXTD_ULD16_DESC_0_L__ULD16_CSR_ULD_START_ADDR___M 0x00000FFF +#define PHYA_TXTD_ULD16_DESC_0_L__ULD16_CSR_ULD_START_ADDR___S 0 +#define PHYA_TXTD_ULD16_DESC_0_L___M 0x0FFF0FFF +#define PHYA_TXTD_ULD16_DESC_0_L___S 0 + +#define PHYA_TXTD_ULD16_DESC_0_U (0x003B0554) +#define PHYA_TXTD_ULD16_DESC_0_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD16_DESC_0_U___POR 0x00010000 +#define PHYA_TXTD_ULD16_DESC_0_U__ULD16_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x0 +#define PHYA_TXTD_ULD16_DESC_0_U__ULD16_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1 +#define PHYA_TXTD_ULD16_DESC_0_U__ULD16_CSR_ULD_DESC_DURATION___POR 0x0 +#define PHYA_TXTD_ULD16_DESC_0_U__ULD16_CSR_ULD_FFT_SIZE___POR 0x0 +#define PHYA_TXTD_ULD16_DESC_0_U__ULD16_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000 +#define PHYA_TXTD_ULD16_DESC_0_U__ULD16_CSR_ULD_APPLY_PER_CHN_CSD___S 24 +#define PHYA_TXTD_ULD16_DESC_0_U__ULD16_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000 +#define PHYA_TXTD_ULD16_DESC_0_U__ULD16_CSR_ULD_IFFT_BUF_REPEAT___S 16 +#define PHYA_TXTD_ULD16_DESC_0_U__ULD16_CSR_ULD_DESC_DURATION___M 0x00000F00 +#define PHYA_TXTD_ULD16_DESC_0_U__ULD16_CSR_ULD_DESC_DURATION___S 8 +#define PHYA_TXTD_ULD16_DESC_0_U__ULD16_CSR_ULD_FFT_SIZE___M 0x0000000F +#define PHYA_TXTD_ULD16_DESC_0_U__ULD16_CSR_ULD_FFT_SIZE___S 0 +#define PHYA_TXTD_ULD16_DESC_0_U___M 0x0F0F0F0F +#define PHYA_TXTD_ULD16_DESC_0_U___S 0 + +#define PHYA_TXTD_ULD16_DESC_1_L (0x003B0558) +#define PHYA_TXTD_ULD16_DESC_1_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD16_DESC_1_L___POR 0x00000000 +#define PHYA_TXTD_ULD16_DESC_1_L__ULD16_CSR_WIN_SHAPE_RIGHT___POR 0x0 +#define PHYA_TXTD_ULD16_DESC_1_L__ULD16_CSR_WIN_SHAPE_LEFT___POR 0x0 +#define PHYA_TXTD_ULD16_DESC_1_L__ULD16_CSR_WIN_LENGTH_RIGHT___POR 0x00 +#define PHYA_TXTD_ULD16_DESC_1_L__ULD16_CSR_WIN_LENGTH_LEFT___POR 0x00 +#define PHYA_TXTD_ULD16_DESC_1_L__ULD16_CSR_WIN_SHAPE_RIGHT___M 0x01000000 +#define PHYA_TXTD_ULD16_DESC_1_L__ULD16_CSR_WIN_SHAPE_RIGHT___S 24 +#define PHYA_TXTD_ULD16_DESC_1_L__ULD16_CSR_WIN_SHAPE_LEFT___M 0x00010000 +#define PHYA_TXTD_ULD16_DESC_1_L__ULD16_CSR_WIN_SHAPE_LEFT___S 16 +#define PHYA_TXTD_ULD16_DESC_1_L__ULD16_CSR_WIN_LENGTH_RIGHT___M 0x00001F00 +#define PHYA_TXTD_ULD16_DESC_1_L__ULD16_CSR_WIN_LENGTH_RIGHT___S 8 +#define PHYA_TXTD_ULD16_DESC_1_L__ULD16_CSR_WIN_LENGTH_LEFT___M 0x0000001F +#define PHYA_TXTD_ULD16_DESC_1_L__ULD16_CSR_WIN_LENGTH_LEFT___S 0 +#define PHYA_TXTD_ULD16_DESC_1_L___M 0x01011F1F +#define PHYA_TXTD_ULD16_DESC_1_L___S 0 + +#define PHYA_TXTD_ULD16_DESC_1_U (0x003B055C) +#define PHYA_TXTD_ULD16_DESC_1_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD16_DESC_1_U___POR 0x00000000 +#define PHYA_TXTD_ULD16_DESC_1_U__ULD16_CSR_POWER_SCALING_SEL___POR 0x0 +#define PHYA_TXTD_ULD16_DESC_1_U__ULD16_CSR_POWER_SCALING_SEL___M 0x00000007 +#define PHYA_TXTD_ULD16_DESC_1_U__ULD16_CSR_POWER_SCALING_SEL___S 0 +#define PHYA_TXTD_ULD16_DESC_1_U___M 0x00000007 +#define PHYA_TXTD_ULD16_DESC_1_U___S 0 + +#define PHYA_TXTD_ULD17_DESC_0_L (0x003B0560) +#define PHYA_TXTD_ULD17_DESC_0_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD17_DESC_0_L___POR 0x00000000 +#define PHYA_TXTD_ULD17_DESC_0_L__ULD17_CSR_ULD_SYM_CP_LEN___POR 0x000 +#define PHYA_TXTD_ULD17_DESC_0_L__ULD17_CSR_ULD_START_ADDR___POR 0x000 +#define PHYA_TXTD_ULD17_DESC_0_L__ULD17_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000 +#define PHYA_TXTD_ULD17_DESC_0_L__ULD17_CSR_ULD_SYM_CP_LEN___S 16 +#define PHYA_TXTD_ULD17_DESC_0_L__ULD17_CSR_ULD_START_ADDR___M 0x00000FFF +#define PHYA_TXTD_ULD17_DESC_0_L__ULD17_CSR_ULD_START_ADDR___S 0 +#define PHYA_TXTD_ULD17_DESC_0_L___M 0x0FFF0FFF +#define PHYA_TXTD_ULD17_DESC_0_L___S 0 + +#define PHYA_TXTD_ULD17_DESC_0_U (0x003B0564) +#define PHYA_TXTD_ULD17_DESC_0_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD17_DESC_0_U___POR 0x00010000 +#define PHYA_TXTD_ULD17_DESC_0_U__ULD17_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x0 +#define PHYA_TXTD_ULD17_DESC_0_U__ULD17_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1 +#define PHYA_TXTD_ULD17_DESC_0_U__ULD17_CSR_ULD_DESC_DURATION___POR 0x0 +#define PHYA_TXTD_ULD17_DESC_0_U__ULD17_CSR_ULD_FFT_SIZE___POR 0x0 +#define PHYA_TXTD_ULD17_DESC_0_U__ULD17_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000 +#define PHYA_TXTD_ULD17_DESC_0_U__ULD17_CSR_ULD_APPLY_PER_CHN_CSD___S 24 +#define PHYA_TXTD_ULD17_DESC_0_U__ULD17_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000 +#define PHYA_TXTD_ULD17_DESC_0_U__ULD17_CSR_ULD_IFFT_BUF_REPEAT___S 16 +#define PHYA_TXTD_ULD17_DESC_0_U__ULD17_CSR_ULD_DESC_DURATION___M 0x00000F00 +#define PHYA_TXTD_ULD17_DESC_0_U__ULD17_CSR_ULD_DESC_DURATION___S 8 +#define PHYA_TXTD_ULD17_DESC_0_U__ULD17_CSR_ULD_FFT_SIZE___M 0x0000000F +#define PHYA_TXTD_ULD17_DESC_0_U__ULD17_CSR_ULD_FFT_SIZE___S 0 +#define PHYA_TXTD_ULD17_DESC_0_U___M 0x0F0F0F0F +#define PHYA_TXTD_ULD17_DESC_0_U___S 0 + +#define PHYA_TXTD_ULD17_DESC_1_L (0x003B0568) +#define PHYA_TXTD_ULD17_DESC_1_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD17_DESC_1_L___POR 0x00000000 +#define PHYA_TXTD_ULD17_DESC_1_L__ULD17_CSR_WIN_SHAPE_RIGHT___POR 0x0 +#define PHYA_TXTD_ULD17_DESC_1_L__ULD17_CSR_WIN_SHAPE_LEFT___POR 0x0 +#define PHYA_TXTD_ULD17_DESC_1_L__ULD17_CSR_WIN_LENGTH_RIGHT___POR 0x00 +#define PHYA_TXTD_ULD17_DESC_1_L__ULD17_CSR_WIN_LENGTH_LEFT___POR 0x00 +#define PHYA_TXTD_ULD17_DESC_1_L__ULD17_CSR_WIN_SHAPE_RIGHT___M 0x01000000 +#define PHYA_TXTD_ULD17_DESC_1_L__ULD17_CSR_WIN_SHAPE_RIGHT___S 24 +#define PHYA_TXTD_ULD17_DESC_1_L__ULD17_CSR_WIN_SHAPE_LEFT___M 0x00010000 +#define PHYA_TXTD_ULD17_DESC_1_L__ULD17_CSR_WIN_SHAPE_LEFT___S 16 +#define PHYA_TXTD_ULD17_DESC_1_L__ULD17_CSR_WIN_LENGTH_RIGHT___M 0x00001F00 +#define PHYA_TXTD_ULD17_DESC_1_L__ULD17_CSR_WIN_LENGTH_RIGHT___S 8 +#define PHYA_TXTD_ULD17_DESC_1_L__ULD17_CSR_WIN_LENGTH_LEFT___M 0x0000001F +#define PHYA_TXTD_ULD17_DESC_1_L__ULD17_CSR_WIN_LENGTH_LEFT___S 0 +#define PHYA_TXTD_ULD17_DESC_1_L___M 0x01011F1F +#define PHYA_TXTD_ULD17_DESC_1_L___S 0 + +#define PHYA_TXTD_ULD17_DESC_1_U (0x003B056C) +#define PHYA_TXTD_ULD17_DESC_1_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD17_DESC_1_U___POR 0x00000000 +#define PHYA_TXTD_ULD17_DESC_1_U__ULD17_CSR_POWER_SCALING_SEL___POR 0x0 +#define PHYA_TXTD_ULD17_DESC_1_U__ULD17_CSR_POWER_SCALING_SEL___M 0x00000007 +#define PHYA_TXTD_ULD17_DESC_1_U__ULD17_CSR_POWER_SCALING_SEL___S 0 +#define PHYA_TXTD_ULD17_DESC_1_U___M 0x00000007 +#define PHYA_TXTD_ULD17_DESC_1_U___S 0 + +#define PHYA_TXTD_ULD18_DESC_0_L (0x003B0570) +#define PHYA_TXTD_ULD18_DESC_0_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD18_DESC_0_L___POR 0x00000000 +#define PHYA_TXTD_ULD18_DESC_0_L__ULD18_CSR_ULD_SYM_CP_LEN___POR 0x000 +#define PHYA_TXTD_ULD18_DESC_0_L__ULD18_CSR_ULD_START_ADDR___POR 0x000 +#define PHYA_TXTD_ULD18_DESC_0_L__ULD18_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000 +#define PHYA_TXTD_ULD18_DESC_0_L__ULD18_CSR_ULD_SYM_CP_LEN___S 16 +#define PHYA_TXTD_ULD18_DESC_0_L__ULD18_CSR_ULD_START_ADDR___M 0x00000FFF +#define PHYA_TXTD_ULD18_DESC_0_L__ULD18_CSR_ULD_START_ADDR___S 0 +#define PHYA_TXTD_ULD18_DESC_0_L___M 0x0FFF0FFF +#define PHYA_TXTD_ULD18_DESC_0_L___S 0 + +#define PHYA_TXTD_ULD18_DESC_0_U (0x003B0574) +#define PHYA_TXTD_ULD18_DESC_0_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD18_DESC_0_U___POR 0x00010000 +#define PHYA_TXTD_ULD18_DESC_0_U__ULD18_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x0 +#define PHYA_TXTD_ULD18_DESC_0_U__ULD18_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1 +#define PHYA_TXTD_ULD18_DESC_0_U__ULD18_CSR_ULD_DESC_DURATION___POR 0x0 +#define PHYA_TXTD_ULD18_DESC_0_U__ULD18_CSR_ULD_FFT_SIZE___POR 0x0 +#define PHYA_TXTD_ULD18_DESC_0_U__ULD18_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000 +#define PHYA_TXTD_ULD18_DESC_0_U__ULD18_CSR_ULD_APPLY_PER_CHN_CSD___S 24 +#define PHYA_TXTD_ULD18_DESC_0_U__ULD18_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000 +#define PHYA_TXTD_ULD18_DESC_0_U__ULD18_CSR_ULD_IFFT_BUF_REPEAT___S 16 +#define PHYA_TXTD_ULD18_DESC_0_U__ULD18_CSR_ULD_DESC_DURATION___M 0x00000F00 +#define PHYA_TXTD_ULD18_DESC_0_U__ULD18_CSR_ULD_DESC_DURATION___S 8 +#define PHYA_TXTD_ULD18_DESC_0_U__ULD18_CSR_ULD_FFT_SIZE___M 0x0000000F +#define PHYA_TXTD_ULD18_DESC_0_U__ULD18_CSR_ULD_FFT_SIZE___S 0 +#define PHYA_TXTD_ULD18_DESC_0_U___M 0x0F0F0F0F +#define PHYA_TXTD_ULD18_DESC_0_U___S 0 + +#define PHYA_TXTD_ULD18_DESC_1_L (0x003B0578) +#define PHYA_TXTD_ULD18_DESC_1_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD18_DESC_1_L___POR 0x00000000 +#define PHYA_TXTD_ULD18_DESC_1_L__ULD18_CSR_WIN_SHAPE_RIGHT___POR 0x0 +#define PHYA_TXTD_ULD18_DESC_1_L__ULD18_CSR_WIN_SHAPE_LEFT___POR 0x0 +#define PHYA_TXTD_ULD18_DESC_1_L__ULD18_CSR_WIN_LENGTH_RIGHT___POR 0x00 +#define PHYA_TXTD_ULD18_DESC_1_L__ULD18_CSR_WIN_LENGTH_LEFT___POR 0x00 +#define PHYA_TXTD_ULD18_DESC_1_L__ULD18_CSR_WIN_SHAPE_RIGHT___M 0x01000000 +#define PHYA_TXTD_ULD18_DESC_1_L__ULD18_CSR_WIN_SHAPE_RIGHT___S 24 +#define PHYA_TXTD_ULD18_DESC_1_L__ULD18_CSR_WIN_SHAPE_LEFT___M 0x00010000 +#define PHYA_TXTD_ULD18_DESC_1_L__ULD18_CSR_WIN_SHAPE_LEFT___S 16 +#define PHYA_TXTD_ULD18_DESC_1_L__ULD18_CSR_WIN_LENGTH_RIGHT___M 0x00001F00 +#define PHYA_TXTD_ULD18_DESC_1_L__ULD18_CSR_WIN_LENGTH_RIGHT___S 8 +#define PHYA_TXTD_ULD18_DESC_1_L__ULD18_CSR_WIN_LENGTH_LEFT___M 0x0000001F +#define PHYA_TXTD_ULD18_DESC_1_L__ULD18_CSR_WIN_LENGTH_LEFT___S 0 +#define PHYA_TXTD_ULD18_DESC_1_L___M 0x01011F1F +#define PHYA_TXTD_ULD18_DESC_1_L___S 0 + +#define PHYA_TXTD_ULD18_DESC_1_U (0x003B057C) +#define PHYA_TXTD_ULD18_DESC_1_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD18_DESC_1_U___POR 0x00000000 +#define PHYA_TXTD_ULD18_DESC_1_U__ULD18_CSR_POWER_SCALING_SEL___POR 0x0 +#define PHYA_TXTD_ULD18_DESC_1_U__ULD18_CSR_POWER_SCALING_SEL___M 0x00000007 +#define PHYA_TXTD_ULD18_DESC_1_U__ULD18_CSR_POWER_SCALING_SEL___S 0 +#define PHYA_TXTD_ULD18_DESC_1_U___M 0x00000007 +#define PHYA_TXTD_ULD18_DESC_1_U___S 0 + +#define PHYA_TXTD_ULD19_DESC_0_L (0x003B0580) +#define PHYA_TXTD_ULD19_DESC_0_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD19_DESC_0_L___POR 0x00000000 +#define PHYA_TXTD_ULD19_DESC_0_L__ULD19_CSR_ULD_SYM_CP_LEN___POR 0x000 +#define PHYA_TXTD_ULD19_DESC_0_L__ULD19_CSR_ULD_START_ADDR___POR 0x000 +#define PHYA_TXTD_ULD19_DESC_0_L__ULD19_CSR_ULD_SYM_CP_LEN___M 0x0FFF0000 +#define PHYA_TXTD_ULD19_DESC_0_L__ULD19_CSR_ULD_SYM_CP_LEN___S 16 +#define PHYA_TXTD_ULD19_DESC_0_L__ULD19_CSR_ULD_START_ADDR___M 0x00000FFF +#define PHYA_TXTD_ULD19_DESC_0_L__ULD19_CSR_ULD_START_ADDR___S 0 +#define PHYA_TXTD_ULD19_DESC_0_L___M 0x0FFF0FFF +#define PHYA_TXTD_ULD19_DESC_0_L___S 0 + +#define PHYA_TXTD_ULD19_DESC_0_U (0x003B0584) +#define PHYA_TXTD_ULD19_DESC_0_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD19_DESC_0_U___POR 0x00010000 +#define PHYA_TXTD_ULD19_DESC_0_U__ULD19_CSR_ULD_APPLY_PER_CHN_CSD___POR 0x0 +#define PHYA_TXTD_ULD19_DESC_0_U__ULD19_CSR_ULD_IFFT_BUF_REPEAT___POR 0x1 +#define PHYA_TXTD_ULD19_DESC_0_U__ULD19_CSR_ULD_DESC_DURATION___POR 0x0 +#define PHYA_TXTD_ULD19_DESC_0_U__ULD19_CSR_ULD_FFT_SIZE___POR 0x0 +#define PHYA_TXTD_ULD19_DESC_0_U__ULD19_CSR_ULD_APPLY_PER_CHN_CSD___M 0x0F000000 +#define PHYA_TXTD_ULD19_DESC_0_U__ULD19_CSR_ULD_APPLY_PER_CHN_CSD___S 24 +#define PHYA_TXTD_ULD19_DESC_0_U__ULD19_CSR_ULD_IFFT_BUF_REPEAT___M 0x000F0000 +#define PHYA_TXTD_ULD19_DESC_0_U__ULD19_CSR_ULD_IFFT_BUF_REPEAT___S 16 +#define PHYA_TXTD_ULD19_DESC_0_U__ULD19_CSR_ULD_DESC_DURATION___M 0x00000F00 +#define PHYA_TXTD_ULD19_DESC_0_U__ULD19_CSR_ULD_DESC_DURATION___S 8 +#define PHYA_TXTD_ULD19_DESC_0_U__ULD19_CSR_ULD_FFT_SIZE___M 0x0000000F +#define PHYA_TXTD_ULD19_DESC_0_U__ULD19_CSR_ULD_FFT_SIZE___S 0 +#define PHYA_TXTD_ULD19_DESC_0_U___M 0x0F0F0F0F +#define PHYA_TXTD_ULD19_DESC_0_U___S 0 + +#define PHYA_TXTD_ULD19_DESC_1_L (0x003B0588) +#define PHYA_TXTD_ULD19_DESC_1_L___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD19_DESC_1_L___POR 0x00000000 +#define PHYA_TXTD_ULD19_DESC_1_L__ULD19_CSR_WIN_SHAPE_RIGHT___POR 0x0 +#define PHYA_TXTD_ULD19_DESC_1_L__ULD19_CSR_WIN_SHAPE_LEFT___POR 0x0 +#define PHYA_TXTD_ULD19_DESC_1_L__ULD19_CSR_WIN_LENGTH_RIGHT___POR 0x00 +#define PHYA_TXTD_ULD19_DESC_1_L__ULD19_CSR_WIN_LENGTH_LEFT___POR 0x00 +#define PHYA_TXTD_ULD19_DESC_1_L__ULD19_CSR_WIN_SHAPE_RIGHT___M 0x01000000 +#define PHYA_TXTD_ULD19_DESC_1_L__ULD19_CSR_WIN_SHAPE_RIGHT___S 24 +#define PHYA_TXTD_ULD19_DESC_1_L__ULD19_CSR_WIN_SHAPE_LEFT___M 0x00010000 +#define PHYA_TXTD_ULD19_DESC_1_L__ULD19_CSR_WIN_SHAPE_LEFT___S 16 +#define PHYA_TXTD_ULD19_DESC_1_L__ULD19_CSR_WIN_LENGTH_RIGHT___M 0x00001F00 +#define PHYA_TXTD_ULD19_DESC_1_L__ULD19_CSR_WIN_LENGTH_RIGHT___S 8 +#define PHYA_TXTD_ULD19_DESC_1_L__ULD19_CSR_WIN_LENGTH_LEFT___M 0x0000001F +#define PHYA_TXTD_ULD19_DESC_1_L__ULD19_CSR_WIN_LENGTH_LEFT___S 0 +#define PHYA_TXTD_ULD19_DESC_1_L___M 0x01011F1F +#define PHYA_TXTD_ULD19_DESC_1_L___S 0 + +#define PHYA_TXTD_ULD19_DESC_1_U (0x003B058C) +#define PHYA_TXTD_ULD19_DESC_1_U___RWC QCSR_REG_RW +#define PHYA_TXTD_ULD19_DESC_1_U___POR 0x00000000 +#define PHYA_TXTD_ULD19_DESC_1_U__ULD19_CSR_POWER_SCALING_SEL___POR 0x0 +#define PHYA_TXTD_ULD19_DESC_1_U__ULD19_CSR_POWER_SCALING_SEL___M 0x00000007 +#define PHYA_TXTD_ULD19_DESC_1_U__ULD19_CSR_POWER_SCALING_SEL___S 0 +#define PHYA_TXTD_ULD19_DESC_1_U___M 0x00000007 +#define PHYA_TXTD_ULD19_DESC_1_U___S 0 + +#define PHYA_TXTD_FW_DYN_CTRL_0_L (0x003B0590) +#define PHYA_TXTD_FW_DYN_CTRL_0_L___RWC QCSR_REG_RW +#define PHYA_TXTD_FW_DYN_CTRL_0_L___POR 0x00000000 +#define PHYA_TXTD_FW_DYN_CTRL_0_L__SCALE_SWITCH___POR 0x0 +#define PHYA_TXTD_FW_DYN_CTRL_0_L__SM_HEAVY_CLIP_ENABLE___POR 0x0 +#define PHYA_TXTD_FW_DYN_CTRL_0_L__SCALE_SWITCH___M 0x00000100 +#define PHYA_TXTD_FW_DYN_CTRL_0_L__SCALE_SWITCH___S 8 +#define PHYA_TXTD_FW_DYN_CTRL_0_L__SM_HEAVY_CLIP_ENABLE___M 0x00000001 +#define PHYA_TXTD_FW_DYN_CTRL_0_L__SM_HEAVY_CLIP_ENABLE___S 0 +#define PHYA_TXTD_FW_DYN_CTRL_0_L___M 0x00000101 +#define PHYA_TXTD_FW_DYN_CTRL_0_L___S 0 + +#define PHYA_TXTD_FW_DYN_CTRL_1_L (0x003B0598) +#define PHYA_TXTD_FW_DYN_CTRL_1_L___RWC QCSR_REG_RW +#define PHYA_TXTD_FW_DYN_CTRL_1_L___POR 0x00000003 +#define PHYA_TXTD_FW_DYN_CTRL_1_L__DAC_OSR_SCALE___POR 0x3 +#define PHYA_TXTD_FW_DYN_CTRL_1_L__DAC_OSR_SCALE___M 0x00000003 +#define PHYA_TXTD_FW_DYN_CTRL_1_L__DAC_OSR_SCALE___S 0 +#define PHYA_TXTD_FW_DYN_CTRL_1_L___M 0x00000003 +#define PHYA_TXTD_FW_DYN_CTRL_1_L___S 0 + +#define PHYA_TXTD_TX_VSRC_L (0x003B05A0) +#define PHYA_TXTD_TX_VSRC_L___RWC QCSR_REG_RW +#define PHYA_TXTD_TX_VSRC_L___POR 0xAAAAAAAB +#define PHYA_TXTD_TX_VSRC_L__CSR_TX_VSRC_PPM___POR 0xAAAAAAAB +#define PHYA_TXTD_TX_VSRC_L__CSR_TX_VSRC_PPM___M 0xFFFFFFFF +#define PHYA_TXTD_TX_VSRC_L__CSR_TX_VSRC_PPM___S 0 +#define PHYA_TXTD_TX_VSRC_L___M 0xFFFFFFFF +#define PHYA_TXTD_TX_VSRC_L___S 0 + +#define PHYA_TXTD_CFO_CTRL_L (0x003B05A8) +#define PHYA_TXTD_CFO_CTRL_L___RWC QCSR_REG_RW +#define PHYA_TXTD_CFO_CTRL_L___POR 0x00000000 +#define PHYA_TXTD_CFO_CTRL_L__CFO_COMPENSATION_ENA___POR 0x0 +#define PHYA_TXTD_CFO_CTRL_L__CFO_COMPENSATION_ENA___M 0x00000001 +#define PHYA_TXTD_CFO_CTRL_L__CFO_COMPENSATION_ENA___S 0 +#define PHYA_TXTD_CFO_CTRL_L___M 0x00000001 +#define PHYA_TXTD_CFO_CTRL_L___S 0 + +#define PHYA_TXTD_CFO_CTRL_U (0x003B05AC) +#define PHYA_TXTD_CFO_CTRL_U___RWC QCSR_REG_RW +#define PHYA_TXTD_CFO_CTRL_U___POR 0x00000000 +#define PHYA_TXTD_CFO_CTRL_U__CFO_COMPENSATION_HZ___POR 0x00000 +#define PHYA_TXTD_CFO_CTRL_U__CFO_COMPENSATION_HZ___M 0x000FFFFF +#define PHYA_TXTD_CFO_CTRL_U__CFO_COMPENSATION_HZ___S 0 +#define PHYA_TXTD_CFO_CTRL_U___M 0x000FFFFF +#define PHYA_TXTD_CFO_CTRL_U___S 0 + +#define PHYA_TXTD_POWER_SCALING0_L (0x003B05B0) +#define PHYA_TXTD_POWER_SCALING0_L___RWC QCSR_REG_RW +#define PHYA_TXTD_POWER_SCALING0_L___POR 0x00400040 +#define PHYA_TXTD_POWER_SCALING0_L__POWER_SCALING_1_0___POR 0x0040 +#define PHYA_TXTD_POWER_SCALING0_L__POWER_SCALING_0_0___POR 0x0040 +#define PHYA_TXTD_POWER_SCALING0_L__POWER_SCALING_1_0___M 0x3FFF0000 +#define PHYA_TXTD_POWER_SCALING0_L__POWER_SCALING_1_0___S 16 +#define PHYA_TXTD_POWER_SCALING0_L__POWER_SCALING_0_0___M 0x00003FFF +#define PHYA_TXTD_POWER_SCALING0_L__POWER_SCALING_0_0___S 0 +#define PHYA_TXTD_POWER_SCALING0_L___M 0x3FFF3FFF +#define PHYA_TXTD_POWER_SCALING0_L___S 0 + +#define PHYA_TXTD_POWER_SCALING0_U (0x003B05B4) +#define PHYA_TXTD_POWER_SCALING0_U___RWC QCSR_REG_RW +#define PHYA_TXTD_POWER_SCALING0_U___POR 0x00400040 +#define PHYA_TXTD_POWER_SCALING0_U__POWER_SCALING_3_0___POR 0x0040 +#define PHYA_TXTD_POWER_SCALING0_U__POWER_SCALING_2_0___POR 0x0040 +#define PHYA_TXTD_POWER_SCALING0_U__POWER_SCALING_3_0___M 0x3FFF0000 +#define PHYA_TXTD_POWER_SCALING0_U__POWER_SCALING_3_0___S 16 +#define PHYA_TXTD_POWER_SCALING0_U__POWER_SCALING_2_0___M 0x00003FFF +#define PHYA_TXTD_POWER_SCALING0_U__POWER_SCALING_2_0___S 0 +#define PHYA_TXTD_POWER_SCALING0_U___M 0x3FFF3FFF +#define PHYA_TXTD_POWER_SCALING0_U___S 0 + +#define PHYA_TXTD_POWER_SCALING1_L (0x003B05B8) +#define PHYA_TXTD_POWER_SCALING1_L___RWC QCSR_REG_RW +#define PHYA_TXTD_POWER_SCALING1_L___POR 0x00400040 +#define PHYA_TXTD_POWER_SCALING1_L__POWER_SCALING_1_1___POR 0x0040 +#define PHYA_TXTD_POWER_SCALING1_L__POWER_SCALING_0_1___POR 0x0040 +#define PHYA_TXTD_POWER_SCALING1_L__POWER_SCALING_1_1___M 0x3FFF0000 +#define PHYA_TXTD_POWER_SCALING1_L__POWER_SCALING_1_1___S 16 +#define PHYA_TXTD_POWER_SCALING1_L__POWER_SCALING_0_1___M 0x00003FFF +#define PHYA_TXTD_POWER_SCALING1_L__POWER_SCALING_0_1___S 0 +#define PHYA_TXTD_POWER_SCALING1_L___M 0x3FFF3FFF +#define PHYA_TXTD_POWER_SCALING1_L___S 0 + +#define PHYA_TXTD_POWER_SCALING1_U (0x003B05BC) +#define PHYA_TXTD_POWER_SCALING1_U___RWC QCSR_REG_RW +#define PHYA_TXTD_POWER_SCALING1_U___POR 0x00400040 +#define PHYA_TXTD_POWER_SCALING1_U__POWER_SCALING_3_1___POR 0x0040 +#define PHYA_TXTD_POWER_SCALING1_U__POWER_SCALING_2_1___POR 0x0040 +#define PHYA_TXTD_POWER_SCALING1_U__POWER_SCALING_3_1___M 0x3FFF0000 +#define PHYA_TXTD_POWER_SCALING1_U__POWER_SCALING_3_1___S 16 +#define PHYA_TXTD_POWER_SCALING1_U__POWER_SCALING_2_1___M 0x00003FFF +#define PHYA_TXTD_POWER_SCALING1_U__POWER_SCALING_2_1___S 0 +#define PHYA_TXTD_POWER_SCALING1_U___M 0x3FFF3FFF +#define PHYA_TXTD_POWER_SCALING1_U___S 0 + +#define PHYA_TXTD_PRETXFIR_CTRL_L (0x003B05C0) +#define PHYA_TXTD_PRETXFIR_CTRL_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PRETXFIR_CTRL_L___POR 0x00000000 +#define PHYA_TXTD_PRETXFIR_CTRL_L__PRETXFIR_MODE___POR 0x0 +#define PHYA_TXTD_PRETXFIR_CTRL_L__PRETXFIR_MODE___M 0x00000003 +#define PHYA_TXTD_PRETXFIR_CTRL_L__PRETXFIR_MODE___S 0 +#define PHYA_TXTD_PRETXFIR_CTRL_L___M 0x00000003 +#define PHYA_TXTD_PRETXFIR_CTRL_L___S 0 + +#define PHYA_TXTD_HEAVY_CLIP_FACTOR_L (0x003B05C8) +#define PHYA_TXTD_HEAVY_CLIP_FACTOR_L___RWC QCSR_REG_RW +#define PHYA_TXTD_HEAVY_CLIP_FACTOR_L___POR 0x00000048 +#define PHYA_TXTD_HEAVY_CLIP_FACTOR_L__CSR_HEAVY_CLIP_FACTOR___POR 0x48 +#define PHYA_TXTD_HEAVY_CLIP_FACTOR_L__CSR_HEAVY_CLIP_FACTOR___M 0x0000007F +#define PHYA_TXTD_HEAVY_CLIP_FACTOR_L__CSR_HEAVY_CLIP_FACTOR___S 0 +#define PHYA_TXTD_HEAVY_CLIP_FACTOR_L___M 0x0000007F +#define PHYA_TXTD_HEAVY_CLIP_FACTOR_L___S 0 + +#define PHYA_TXTD_PWR_COMP_L (0x003B05D0) +#define PHYA_TXTD_PWR_COMP_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PWR_COMP_L___POR 0x00000084 +#define PHYA_TXTD_PWR_COMP_L__CSR_TXTDP_PWR_COMP___POR 0x84 +#define PHYA_TXTD_PWR_COMP_L__CSR_TXTDP_PWR_COMP___M 0x000000FF +#define PHYA_TXTD_PWR_COMP_L__CSR_TXTDP_PWR_COMP___S 0 +#define PHYA_TXTD_PWR_COMP_L___M 0x000000FF +#define PHYA_TXTD_PWR_COMP_L___S 0 + +#define PHYA_TXTD_PKT_START_WR_SPARE_L (0x003B05D8) +#define PHYA_TXTD_PKT_START_WR_SPARE_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PKT_START_WR_SPARE_L___POR 0x00000000 +#define PHYA_TXTD_PKT_START_WR_SPARE_L__PKT_START_WR_SPARE_0___POR 0x00000000 +#define PHYA_TXTD_PKT_START_WR_SPARE_L__PKT_START_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXTD_PKT_START_WR_SPARE_L__PKT_START_WR_SPARE_0___S 0 +#define PHYA_TXTD_PKT_START_WR_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXTD_PKT_START_WR_SPARE_L___S 0 + +#define PHYA_TXTD_PKT_START_WR_SPARE_U (0x003B05DC) +#define PHYA_TXTD_PKT_START_WR_SPARE_U___RWC QCSR_REG_RW +#define PHYA_TXTD_PKT_START_WR_SPARE_U___POR 0x00000000 +#define PHYA_TXTD_PKT_START_WR_SPARE_U__PKT_START_WR_SPARE_1___POR 0x00000000 +#define PHYA_TXTD_PKT_START_WR_SPARE_U__PKT_START_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXTD_PKT_START_WR_SPARE_U__PKT_START_WR_SPARE_1___S 0 +#define PHYA_TXTD_PKT_START_WR_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXTD_PKT_START_WR_SPARE_U___S 0 + +#define PHYA_TXTD_PKT_END_CTRL_0_L (0x003B05E0) +#define PHYA_TXTD_PKT_END_CTRL_0_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PKT_END_CTRL_0_L___POR 0x0000000A +#define PHYA_TXTD_PKT_END_CTRL_0_L__CSR_NUM_DESC_REPEAT___POR 0x0000000A +#define PHYA_TXTD_PKT_END_CTRL_0_L__CSR_NUM_DESC_REPEAT___M 0xFFFFFFFF +#define PHYA_TXTD_PKT_END_CTRL_0_L__CSR_NUM_DESC_REPEAT___S 0 +#define PHYA_TXTD_PKT_END_CTRL_0_L___M 0xFFFFFFFF +#define PHYA_TXTD_PKT_END_CTRL_0_L___S 0 + +#define PHYA_TXTD_PKT_END_CTRL_0_U (0x003B05E4) +#define PHYA_TXTD_PKT_END_CTRL_0_U___RWC QCSR_REG_RW +#define PHYA_TXTD_PKT_END_CTRL_0_U___POR 0x0000000A +#define PHYA_TXTD_PKT_END_CTRL_0_U__CSR_TOTAL_OFDM_SYMBOLS___POR 0x0000000A +#define PHYA_TXTD_PKT_END_CTRL_0_U__CSR_TOTAL_OFDM_SYMBOLS___M 0xFFFFFFFF +#define PHYA_TXTD_PKT_END_CTRL_0_U__CSR_TOTAL_OFDM_SYMBOLS___S 0 +#define PHYA_TXTD_PKT_END_CTRL_0_U___M 0xFFFFFFFF +#define PHYA_TXTD_PKT_END_CTRL_0_U___S 0 + +#define PHYA_TXTD_PKT_END_CTRL_1_L (0x003B05E8) +#define PHYA_TXTD_PKT_END_CTRL_1_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PKT_END_CTRL_1_L___POR 0x00000040 +#define PHYA_TXTD_PKT_END_CTRL_1_L__CSR_TOTAL_11B_SAMPLES___POR 0x00000040 +#define PHYA_TXTD_PKT_END_CTRL_1_L__CSR_TOTAL_11B_SAMPLES___M 0xFFFFFFFF +#define PHYA_TXTD_PKT_END_CTRL_1_L__CSR_TOTAL_11B_SAMPLES___S 0 +#define PHYA_TXTD_PKT_END_CTRL_1_L___M 0xFFFFFFFF +#define PHYA_TXTD_PKT_END_CTRL_1_L___S 0 + +#define PHYA_TXTD_PKT_END_CTRL_1_U (0x003B05EC) +#define PHYA_TXTD_PKT_END_CTRL_1_U___RWC QCSR_REG_RW +#define PHYA_TXTD_PKT_END_CTRL_1_U___POR 0x00001900 +#define PHYA_TXTD_PKT_END_CTRL_1_U__CSR_TXTD_TAIL_LENGTH___POR 0x19 +#define PHYA_TXTD_PKT_END_CTRL_1_U__USE_TXB_EOP___POR 0x0 +#define PHYA_TXTD_PKT_END_CTRL_1_U__CSR_TXTD_TAIL_LENGTH___M 0x00007F00 +#define PHYA_TXTD_PKT_END_CTRL_1_U__CSR_TXTD_TAIL_LENGTH___S 8 +#define PHYA_TXTD_PKT_END_CTRL_1_U__USE_TXB_EOP___M 0x00000001 +#define PHYA_TXTD_PKT_END_CTRL_1_U__USE_TXB_EOP___S 0 +#define PHYA_TXTD_PKT_END_CTRL_1_U___M 0x00007F01 +#define PHYA_TXTD_PKT_END_CTRL_1_U___S 0 + +#define PHYA_TXTD_MULTI_SYM_EVENT_CTRL_L (0x003B05F0) +#define PHYA_TXTD_MULTI_SYM_EVENT_CTRL_L___RWC QCSR_REG_RW +#define PHYA_TXTD_MULTI_SYM_EVENT_CTRL_L___POR 0x00000002 +#define PHYA_TXTD_MULTI_SYM_EVENT_CTRL_L__CSR_MULTI_SYM_CNT___POR 0x2 +#define PHYA_TXTD_MULTI_SYM_EVENT_CTRL_L__CSR_MULTI_SYM_CNT___M 0x0000000F +#define PHYA_TXTD_MULTI_SYM_EVENT_CTRL_L__CSR_MULTI_SYM_CNT___S 0 +#define PHYA_TXTD_MULTI_SYM_EVENT_CTRL_L___M 0x0000000F +#define PHYA_TXTD_MULTI_SYM_EVENT_CTRL_L___S 0 + +#define PHYA_TXTD_MULTI_SYM_EVENT_CTRL_U (0x003B05F4) +#define PHYA_TXTD_MULTI_SYM_EVENT_CTRL_U___RWC QCSR_REG_RW +#define PHYA_TXTD_MULTI_SYM_EVENT_CTRL_U___POR 0x00000003 +#define PHYA_TXTD_MULTI_SYM_EVENT_CTRL_U__CSR_PRE_DATA_EVENT_CNT___POR 0x3 +#define PHYA_TXTD_MULTI_SYM_EVENT_CTRL_U__CSR_PRE_DATA_EVENT_CNT___M 0x0000000F +#define PHYA_TXTD_MULTI_SYM_EVENT_CTRL_U__CSR_PRE_DATA_EVENT_CNT___S 0 +#define PHYA_TXTD_MULTI_SYM_EVENT_CTRL_U___M 0x0000000F +#define PHYA_TXTD_MULTI_SYM_EVENT_CTRL_U___S 0 + +#define PHYA_TXTD_TXTD_START_WR_SPARE_L (0x003B05F8) +#define PHYA_TXTD_TXTD_START_WR_SPARE_L___RWC QCSR_REG_RW +#define PHYA_TXTD_TXTD_START_WR_SPARE_L___POR 0x00000000 +#define PHYA_TXTD_TXTD_START_WR_SPARE_L__TXTD_START_WR_SPARE_0___POR 0x00000000 +#define PHYA_TXTD_TXTD_START_WR_SPARE_L__TXTD_START_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXTD_TXTD_START_WR_SPARE_L__TXTD_START_WR_SPARE_0___S 0 +#define PHYA_TXTD_TXTD_START_WR_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXTD_TXTD_START_WR_SPARE_L___S 0 + +#define PHYA_TXTD_TXTD_START_WR_SPARE_U (0x003B05FC) +#define PHYA_TXTD_TXTD_START_WR_SPARE_U___RWC QCSR_REG_RW +#define PHYA_TXTD_TXTD_START_WR_SPARE_U___POR 0x00000000 +#define PHYA_TXTD_TXTD_START_WR_SPARE_U__TXTD_START_WR_SPARE_1___POR 0x00000000 +#define PHYA_TXTD_TXTD_START_WR_SPARE_U__TXTD_START_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXTD_TXTD_START_WR_SPARE_U__TXTD_START_WR_SPARE_1___S 0 +#define PHYA_TXTD_TXTD_START_WR_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXTD_TXTD_START_WR_SPARE_U___S 0 + +#define PHYA_TXTD_TXTD_START_RD_SPARE_L (0x003B0600) +#define PHYA_TXTD_TXTD_START_RD_SPARE_L___RWC QCSR_REG_RO +#define PHYA_TXTD_TXTD_START_RD_SPARE_L___POR 0x00000000 +#define PHYA_TXTD_TXTD_START_RD_SPARE_L__TXTD_START_RD_SPARE_0___POR 0x00000000 +#define PHYA_TXTD_TXTD_START_RD_SPARE_L__TXTD_START_RD_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXTD_TXTD_START_RD_SPARE_L__TXTD_START_RD_SPARE_0___S 0 +#define PHYA_TXTD_TXTD_START_RD_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXTD_TXTD_START_RD_SPARE_L___S 0 + +#define PHYA_TXTD_TXTD_START_RD_SPARE_U (0x003B0604) +#define PHYA_TXTD_TXTD_START_RD_SPARE_U___RWC QCSR_REG_RO +#define PHYA_TXTD_TXTD_START_RD_SPARE_U___POR 0x00000000 +#define PHYA_TXTD_TXTD_START_RD_SPARE_U__TXTD_START_RD_SPARE_1___POR 0x00000000 +#define PHYA_TXTD_TXTD_START_RD_SPARE_U__TXTD_START_RD_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXTD_TXTD_START_RD_SPARE_U__TXTD_START_RD_SPARE_1___S 0 +#define PHYA_TXTD_TXTD_START_RD_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXTD_TXTD_START_RD_SPARE_U___S 0 + +#define PHYA_TXTD_SYM_WR_SPARE_L (0x003B0608) +#define PHYA_TXTD_SYM_WR_SPARE_L___RWC QCSR_REG_RW +#define PHYA_TXTD_SYM_WR_SPARE_L___POR 0x00000000 +#define PHYA_TXTD_SYM_WR_SPARE_L__SYM_WR_SPARE_0___POR 0x00000000 +#define PHYA_TXTD_SYM_WR_SPARE_L__SYM_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXTD_SYM_WR_SPARE_L__SYM_WR_SPARE_0___S 0 +#define PHYA_TXTD_SYM_WR_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXTD_SYM_WR_SPARE_L___S 0 + +#define PHYA_TXTD_SYM_WR_SPARE_U (0x003B060C) +#define PHYA_TXTD_SYM_WR_SPARE_U___RWC QCSR_REG_RW +#define PHYA_TXTD_SYM_WR_SPARE_U___POR 0x00000000 +#define PHYA_TXTD_SYM_WR_SPARE_U__SYM_WR_SPARE_1___POR 0x00000000 +#define PHYA_TXTD_SYM_WR_SPARE_U__SYM_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXTD_SYM_WR_SPARE_U__SYM_WR_SPARE_1___S 0 +#define PHYA_TXTD_SYM_WR_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXTD_SYM_WR_SPARE_U___S 0 + +#define PHYA_TXTD_SYM_RD_L (0x003B0610) +#define PHYA_TXTD_SYM_RD_L___RWC QCSR_REG_RO +#define PHYA_TXTD_SYM_RD_L___POR 0x00000000 +#define PHYA_TXTD_SYM_RD_L__CURR_DESC___POR 0x00 +#define PHYA_TXTD_SYM_RD_L__CURR_DESC___M 0x0000001F +#define PHYA_TXTD_SYM_RD_L__CURR_DESC___S 0 +#define PHYA_TXTD_SYM_RD_L___M 0x0000001F +#define PHYA_TXTD_SYM_RD_L___S 0 + +#define PHYA_TXTD_SYM_RD_SPARE_L (0x003B0618) +#define PHYA_TXTD_SYM_RD_SPARE_L___RWC QCSR_REG_RO +#define PHYA_TXTD_SYM_RD_SPARE_L___POR 0x00000000 +#define PHYA_TXTD_SYM_RD_SPARE_L__SYM_RD_SPARE_0___POR 0x00000000 +#define PHYA_TXTD_SYM_RD_SPARE_L__SYM_RD_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXTD_SYM_RD_SPARE_L__SYM_RD_SPARE_0___S 0 +#define PHYA_TXTD_SYM_RD_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXTD_SYM_RD_SPARE_L___S 0 + +#define PHYA_TXTD_SYM_RD_SPARE_U (0x003B061C) +#define PHYA_TXTD_SYM_RD_SPARE_U___RWC QCSR_REG_RO +#define PHYA_TXTD_SYM_RD_SPARE_U___POR 0x00000000 +#define PHYA_TXTD_SYM_RD_SPARE_U__SYM_RD_SPARE_1___POR 0x00000000 +#define PHYA_TXTD_SYM_RD_SPARE_U__SYM_RD_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXTD_SYM_RD_SPARE_U__SYM_RD_SPARE_1___S 0 +#define PHYA_TXTD_SYM_RD_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXTD_SYM_RD_SPARE_U___S 0 + +#define PHYA_TXTD_MULTI_SYM_WR_SPARE_L (0x003B0620) +#define PHYA_TXTD_MULTI_SYM_WR_SPARE_L___RWC QCSR_REG_RW +#define PHYA_TXTD_MULTI_SYM_WR_SPARE_L___POR 0x00000000 +#define PHYA_TXTD_MULTI_SYM_WR_SPARE_L__MULTI_SYM_WR_SPARE_0___POR 0x00000000 +#define PHYA_TXTD_MULTI_SYM_WR_SPARE_L__MULTI_SYM_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXTD_MULTI_SYM_WR_SPARE_L__MULTI_SYM_WR_SPARE_0___S 0 +#define PHYA_TXTD_MULTI_SYM_WR_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXTD_MULTI_SYM_WR_SPARE_L___S 0 + +#define PHYA_TXTD_MULTI_SYM_WR_SPARE_U (0x003B0624) +#define PHYA_TXTD_MULTI_SYM_WR_SPARE_U___RWC QCSR_REG_RW +#define PHYA_TXTD_MULTI_SYM_WR_SPARE_U___POR 0x00000000 +#define PHYA_TXTD_MULTI_SYM_WR_SPARE_U__MULTI_SYM_WR_SPARE_1___POR 0x00000000 +#define PHYA_TXTD_MULTI_SYM_WR_SPARE_U__MULTI_SYM_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXTD_MULTI_SYM_WR_SPARE_U__MULTI_SYM_WR_SPARE_1___S 0 +#define PHYA_TXTD_MULTI_SYM_WR_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXTD_MULTI_SYM_WR_SPARE_U___S 0 + +#define PHYA_TXTD_MULTI_SYM_RD_L (0x003B0628) +#define PHYA_TXTD_MULTI_SYM_RD_L___RWC QCSR_REG_RO +#define PHYA_TXTD_MULTI_SYM_RD_L___POR 0x00000000 +#define PHYA_TXTD_MULTI_SYM_RD_L__MULTI_SYM_CURR_DESC___POR 0x00 +#define PHYA_TXTD_MULTI_SYM_RD_L__MULTI_SYM_CURR_DESC___M 0x0000001F +#define PHYA_TXTD_MULTI_SYM_RD_L__MULTI_SYM_CURR_DESC___S 0 +#define PHYA_TXTD_MULTI_SYM_RD_L___M 0x0000001F +#define PHYA_TXTD_MULTI_SYM_RD_L___S 0 + +#define PHYA_TXTD_MULTI_SYM_RD_SPARE_L (0x003B0630) +#define PHYA_TXTD_MULTI_SYM_RD_SPARE_L___RWC QCSR_REG_RO +#define PHYA_TXTD_MULTI_SYM_RD_SPARE_L___POR 0x00000000 +#define PHYA_TXTD_MULTI_SYM_RD_SPARE_L__MULTI_SYM_RD_SPARE_0___POR 0x00000000 +#define PHYA_TXTD_MULTI_SYM_RD_SPARE_L__MULTI_SYM_RD_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXTD_MULTI_SYM_RD_SPARE_L__MULTI_SYM_RD_SPARE_0___S 0 +#define PHYA_TXTD_MULTI_SYM_RD_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXTD_MULTI_SYM_RD_SPARE_L___S 0 + +#define PHYA_TXTD_MULTI_SYM_RD_SPARE_U (0x003B0634) +#define PHYA_TXTD_MULTI_SYM_RD_SPARE_U___RWC QCSR_REG_RO +#define PHYA_TXTD_MULTI_SYM_RD_SPARE_U___POR 0x00000000 +#define PHYA_TXTD_MULTI_SYM_RD_SPARE_U__MULTI_SYM_RD_SPARE_1___POR 0x00000000 +#define PHYA_TXTD_MULTI_SYM_RD_SPARE_U__MULTI_SYM_RD_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXTD_MULTI_SYM_RD_SPARE_U__MULTI_SYM_RD_SPARE_1___S 0 +#define PHYA_TXTD_MULTI_SYM_RD_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXTD_MULTI_SYM_RD_SPARE_U___S 0 + +#define PHYA_TXTD_PRE_DATA_WR_SPARE_L (0x003B0638) +#define PHYA_TXTD_PRE_DATA_WR_SPARE_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PRE_DATA_WR_SPARE_L___POR 0x00000000 +#define PHYA_TXTD_PRE_DATA_WR_SPARE_L__PRE_DATA_WR_SPARE_0___POR 0x00000000 +#define PHYA_TXTD_PRE_DATA_WR_SPARE_L__PRE_DATA_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXTD_PRE_DATA_WR_SPARE_L__PRE_DATA_WR_SPARE_0___S 0 +#define PHYA_TXTD_PRE_DATA_WR_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXTD_PRE_DATA_WR_SPARE_L___S 0 + +#define PHYA_TXTD_PRE_DATA_WR_SPARE_U (0x003B063C) +#define PHYA_TXTD_PRE_DATA_WR_SPARE_U___RWC QCSR_REG_RW +#define PHYA_TXTD_PRE_DATA_WR_SPARE_U___POR 0x00000000 +#define PHYA_TXTD_PRE_DATA_WR_SPARE_U__PRE_DATA_WR_SPARE_1___POR 0x00000000 +#define PHYA_TXTD_PRE_DATA_WR_SPARE_U__PRE_DATA_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXTD_PRE_DATA_WR_SPARE_U__PRE_DATA_WR_SPARE_1___S 0 +#define PHYA_TXTD_PRE_DATA_WR_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXTD_PRE_DATA_WR_SPARE_U___S 0 + +#define PHYA_TXTD_PRE_DATA_RD_L (0x003B0640) +#define PHYA_TXTD_PRE_DATA_RD_L___RWC QCSR_REG_RO +#define PHYA_TXTD_PRE_DATA_RD_L___POR 0x00000000 +#define PHYA_TXTD_PRE_DATA_RD_L__PRE_DATA_CURR_DESC___POR 0x00 +#define PHYA_TXTD_PRE_DATA_RD_L__PRE_DATA_CURR_DESC___M 0x0000001F +#define PHYA_TXTD_PRE_DATA_RD_L__PRE_DATA_CURR_DESC___S 0 +#define PHYA_TXTD_PRE_DATA_RD_L___M 0x0000001F +#define PHYA_TXTD_PRE_DATA_RD_L___S 0 + +#define PHYA_TXTD_PRE_DATA_RD_SPARE_L (0x003B0648) +#define PHYA_TXTD_PRE_DATA_RD_SPARE_L___RWC QCSR_REG_RO +#define PHYA_TXTD_PRE_DATA_RD_SPARE_L___POR 0x00000000 +#define PHYA_TXTD_PRE_DATA_RD_SPARE_L__PRE_DATA_RD_SPARE_0___POR 0x00000000 +#define PHYA_TXTD_PRE_DATA_RD_SPARE_L__PRE_DATA_RD_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXTD_PRE_DATA_RD_SPARE_L__PRE_DATA_RD_SPARE_0___S 0 +#define PHYA_TXTD_PRE_DATA_RD_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXTD_PRE_DATA_RD_SPARE_L___S 0 + +#define PHYA_TXTD_PRE_DATA_RD_SPARE_U (0x003B064C) +#define PHYA_TXTD_PRE_DATA_RD_SPARE_U___RWC QCSR_REG_RO +#define PHYA_TXTD_PRE_DATA_RD_SPARE_U___POR 0x00000000 +#define PHYA_TXTD_PRE_DATA_RD_SPARE_U__PRE_DATA_RD_SPARE_1___POR 0x00000000 +#define PHYA_TXTD_PRE_DATA_RD_SPARE_U__PRE_DATA_RD_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXTD_PRE_DATA_RD_SPARE_U__PRE_DATA_RD_SPARE_1___S 0 +#define PHYA_TXTD_PRE_DATA_RD_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXTD_PRE_DATA_RD_SPARE_U___S 0 + +#define PHYA_TXTD_PKT_DATA_WR_SPARE_L (0x003B0650) +#define PHYA_TXTD_PKT_DATA_WR_SPARE_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PKT_DATA_WR_SPARE_L___POR 0x00000000 +#define PHYA_TXTD_PKT_DATA_WR_SPARE_L__PKT_DATA_WR_SPARE_0___POR 0x00000000 +#define PHYA_TXTD_PKT_DATA_WR_SPARE_L__PKT_DATA_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXTD_PKT_DATA_WR_SPARE_L__PKT_DATA_WR_SPARE_0___S 0 +#define PHYA_TXTD_PKT_DATA_WR_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXTD_PKT_DATA_WR_SPARE_L___S 0 + +#define PHYA_TXTD_PKT_DATA_WR_SPARE_U (0x003B0654) +#define PHYA_TXTD_PKT_DATA_WR_SPARE_U___RWC QCSR_REG_RW +#define PHYA_TXTD_PKT_DATA_WR_SPARE_U___POR 0x00000000 +#define PHYA_TXTD_PKT_DATA_WR_SPARE_U__PKT_DATA_WR_SPARE_1___POR 0x00000000 +#define PHYA_TXTD_PKT_DATA_WR_SPARE_U__PKT_DATA_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXTD_PKT_DATA_WR_SPARE_U__PKT_DATA_WR_SPARE_1___S 0 +#define PHYA_TXTD_PKT_DATA_WR_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXTD_PKT_DATA_WR_SPARE_U___S 0 + +#define PHYA_TXTD_PKT_DATA_RD_SPARE_L (0x003B0658) +#define PHYA_TXTD_PKT_DATA_RD_SPARE_L___RWC QCSR_REG_RO +#define PHYA_TXTD_PKT_DATA_RD_SPARE_L___POR 0x00000000 +#define PHYA_TXTD_PKT_DATA_RD_SPARE_L__PKT_DATA_RD_SPARE_0___POR 0x00000000 +#define PHYA_TXTD_PKT_DATA_RD_SPARE_L__PKT_DATA_RD_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXTD_PKT_DATA_RD_SPARE_L__PKT_DATA_RD_SPARE_0___S 0 +#define PHYA_TXTD_PKT_DATA_RD_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXTD_PKT_DATA_RD_SPARE_L___S 0 + +#define PHYA_TXTD_PKT_DATA_RD_SPARE_U (0x003B065C) +#define PHYA_TXTD_PKT_DATA_RD_SPARE_U___RWC QCSR_REG_RO +#define PHYA_TXTD_PKT_DATA_RD_SPARE_U___POR 0x00000000 +#define PHYA_TXTD_PKT_DATA_RD_SPARE_U__PKT_DATA_RD_SPARE_1___POR 0x00000000 +#define PHYA_TXTD_PKT_DATA_RD_SPARE_U__PKT_DATA_RD_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXTD_PKT_DATA_RD_SPARE_U__PKT_DATA_RD_SPARE_1___S 0 +#define PHYA_TXTD_PKT_DATA_RD_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXTD_PKT_DATA_RD_SPARE_U___S 0 + +#define PHYA_TXTD_PKT_END_WR_SPARE_L (0x003B0660) +#define PHYA_TXTD_PKT_END_WR_SPARE_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PKT_END_WR_SPARE_L___POR 0x00000000 +#define PHYA_TXTD_PKT_END_WR_SPARE_L__PKT_END_WR_SPARE_0___POR 0x00000000 +#define PHYA_TXTD_PKT_END_WR_SPARE_L__PKT_END_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXTD_PKT_END_WR_SPARE_L__PKT_END_WR_SPARE_0___S 0 +#define PHYA_TXTD_PKT_END_WR_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXTD_PKT_END_WR_SPARE_L___S 0 + +#define PHYA_TXTD_PKT_END_WR_SPARE_U (0x003B0664) +#define PHYA_TXTD_PKT_END_WR_SPARE_U___RWC QCSR_REG_RW +#define PHYA_TXTD_PKT_END_WR_SPARE_U___POR 0x00000000 +#define PHYA_TXTD_PKT_END_WR_SPARE_U__PKT_END_WR_SPARE_1___POR 0x00000000 +#define PHYA_TXTD_PKT_END_WR_SPARE_U__PKT_END_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXTD_PKT_END_WR_SPARE_U__PKT_END_WR_SPARE_1___S 0 +#define PHYA_TXTD_PKT_END_WR_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXTD_PKT_END_WR_SPARE_U___S 0 + +#define PHYA_TXTD_PKT_END_RD_0_L (0x003B0668) +#define PHYA_TXTD_PKT_END_RD_0_L___RWC QCSR_REG_RO +#define PHYA_TXTD_PKT_END_RD_0_L___POR 0x00000000 +#define PHYA_TXTD_PKT_END_RD_0_L__TOTAL_OFDM_SYMBOL_CNT___POR 0x00000000 +#define PHYA_TXTD_PKT_END_RD_0_L__TOTAL_OFDM_SYMBOL_CNT___M 0xFFFFFFFF +#define PHYA_TXTD_PKT_END_RD_0_L__TOTAL_OFDM_SYMBOL_CNT___S 0 +#define PHYA_TXTD_PKT_END_RD_0_L___M 0xFFFFFFFF +#define PHYA_TXTD_PKT_END_RD_0_L___S 0 + +#define PHYA_TXTD_PKT_END_RD_0_U (0x003B066C) +#define PHYA_TXTD_PKT_END_RD_0_U___RWC QCSR_REG_RO +#define PHYA_TXTD_PKT_END_RD_0_U___POR 0x00000000 +#define PHYA_TXTD_PKT_END_RD_0_U__TOTAL_11B_SAMPLE_CNT___POR 0x00000000 +#define PHYA_TXTD_PKT_END_RD_0_U__TOTAL_11B_SAMPLE_CNT___M 0xFFFFFFFF +#define PHYA_TXTD_PKT_END_RD_0_U__TOTAL_11B_SAMPLE_CNT___S 0 +#define PHYA_TXTD_PKT_END_RD_0_U___M 0xFFFFFFFF +#define PHYA_TXTD_PKT_END_RD_0_U___S 0 + +#define PHYA_TXTD_PKT_END_RD_1_L (0x003B0670) +#define PHYA_TXTD_PKT_END_RD_1_L___RWC QCSR_REG_RO +#define PHYA_TXTD_PKT_END_RD_1_L___POR 0x00000000 +#define PHYA_TXTD_PKT_END_RD_1_L__TOTAL_OFDM_PKT_CNT___POR 0x00000000 +#define PHYA_TXTD_PKT_END_RD_1_L__TOTAL_OFDM_PKT_CNT___M 0xFFFFFFFF +#define PHYA_TXTD_PKT_END_RD_1_L__TOTAL_OFDM_PKT_CNT___S 0 +#define PHYA_TXTD_PKT_END_RD_1_L___M 0xFFFFFFFF +#define PHYA_TXTD_PKT_END_RD_1_L___S 0 + +#define PHYA_TXTD_PKT_END_RD_1_U (0x003B0674) +#define PHYA_TXTD_PKT_END_RD_1_U___RWC QCSR_REG_RO +#define PHYA_TXTD_PKT_END_RD_1_U___POR 0x00000000 +#define PHYA_TXTD_PKT_END_RD_1_U__TOTAL_11B_PKT_CNT___POR 0x00000000 +#define PHYA_TXTD_PKT_END_RD_1_U__TOTAL_11B_PKT_CNT___M 0xFFFFFFFF +#define PHYA_TXTD_PKT_END_RD_1_U__TOTAL_11B_PKT_CNT___S 0 +#define PHYA_TXTD_PKT_END_RD_1_U___M 0xFFFFFFFF +#define PHYA_TXTD_PKT_END_RD_1_U___S 0 + +#define PHYA_TXTD_PKT_END_RD_2_L (0x003B0678) +#define PHYA_TXTD_PKT_END_RD_2_L___RWC QCSR_REG_RO +#define PHYA_TXTD_PKT_END_RD_2_L___POR 0x00000000 +#define PHYA_TXTD_PKT_END_RD_2_L__TOTAL_PER_PKT_DESC_CNT___POR 0x00 +#define PHYA_TXTD_PKT_END_RD_2_L__TOTAL_PER_PKT_DESC_CNT___M 0x0000001F +#define PHYA_TXTD_PKT_END_RD_2_L__TOTAL_PER_PKT_DESC_CNT___S 0 +#define PHYA_TXTD_PKT_END_RD_2_L___M 0x0000001F +#define PHYA_TXTD_PKT_END_RD_2_L___S 0 + +#define PHYA_TXTD_PKT_END_RD_SPARE_L (0x003B0680) +#define PHYA_TXTD_PKT_END_RD_SPARE_L___RWC QCSR_REG_RO +#define PHYA_TXTD_PKT_END_RD_SPARE_L___POR 0x00000000 +#define PHYA_TXTD_PKT_END_RD_SPARE_L__PKT_END_RD_SPARE_0___POR 0x00000000 +#define PHYA_TXTD_PKT_END_RD_SPARE_L__PKT_END_RD_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXTD_PKT_END_RD_SPARE_L__PKT_END_RD_SPARE_0___S 0 +#define PHYA_TXTD_PKT_END_RD_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXTD_PKT_END_RD_SPARE_L___S 0 + +#define PHYA_TXTD_PKT_END_RD_SPARE_U (0x003B0684) +#define PHYA_TXTD_PKT_END_RD_SPARE_U___RWC QCSR_REG_RO +#define PHYA_TXTD_PKT_END_RD_SPARE_U___POR 0x00000000 +#define PHYA_TXTD_PKT_END_RD_SPARE_U__PKT_END_RD_SPARE_1___POR 0x00000000 +#define PHYA_TXTD_PKT_END_RD_SPARE_U__PKT_END_RD_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXTD_PKT_END_RD_SPARE_U__PKT_END_RD_SPARE_1___S 0 +#define PHYA_TXTD_PKT_END_RD_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXTD_PKT_END_RD_SPARE_U___S 0 + +#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B0 (0x003B0800) +#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B0___RWC QCSR_REG_RW +#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B0___POR 0x00000000 +#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B0__PER_CHAIN_HE_CSD___POR 0x00 +#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B0__PER_CHAIN_HT_CSD___POR 0x00 +#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B0__PER_CHAIN_LEG_CSD___POR 0x00 +#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B0__ENABLE_PHASE_DITHERING___POR 0x0 +#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B0__PER_CHAIN_HE_CSD___M 0x1F000000 +#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B0__PER_CHAIN_HE_CSD___S 24 +#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B0__PER_CHAIN_HT_CSD___M 0x001F0000 +#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B0__PER_CHAIN_HT_CSD___S 16 +#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B0__PER_CHAIN_LEG_CSD___M 0x00001F00 +#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B0__PER_CHAIN_LEG_CSD___S 8 +#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B0__ENABLE_PHASE_DITHERING___M 0x00000001 +#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B0__ENABLE_PHASE_DITHERING___S 0 +#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B0___M 0x1F1F1F01 +#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B0___S 0 + +#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B1 (0x003B0C00) +#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B1___RWC QCSR_REG_RW +#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B1___POR 0x00000000 +#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B1__PER_CHAIN_HE_CSD___POR 0x00 +#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B1__PER_CHAIN_HT_CSD___POR 0x00 +#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B1__PER_CHAIN_LEG_CSD___POR 0x00 +#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B1__ENABLE_PHASE_DITHERING___POR 0x0 +#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B1__PER_CHAIN_HE_CSD___M 0x1F000000 +#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B1__PER_CHAIN_HE_CSD___S 24 +#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B1__PER_CHAIN_HT_CSD___M 0x001F0000 +#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B1__PER_CHAIN_HT_CSD___S 16 +#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B1__PER_CHAIN_LEG_CSD___M 0x00001F00 +#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B1__PER_CHAIN_LEG_CSD___S 8 +#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B1__ENABLE_PHASE_DITHERING___M 0x00000001 +#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B1__ENABLE_PHASE_DITHERING___S 0 +#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B1___M 0x1F1F1F01 +#define PHYA_TXTD_CHN_FW_CHN_DYN_CTRL_L_B1___S 0 + +#define PHYA_TXTD_CHN_TX_CCK_DELAY_L_B0 (0x003B0808) +#define PHYA_TXTD_CHN_TX_CCK_DELAY_L_B0___RWC QCSR_REG_RW +#define PHYA_TXTD_CHN_TX_CCK_DELAY_L_B0___POR 0x00000000 +#define PHYA_TXTD_CHN_TX_CCK_DELAY_L_B0__TX_CCK_DELAY___POR 0x0 +#define PHYA_TXTD_CHN_TX_CCK_DELAY_L_B0__TX_CCK_DELAY___M 0x00000007 +#define PHYA_TXTD_CHN_TX_CCK_DELAY_L_B0__TX_CCK_DELAY___S 0 +#define PHYA_TXTD_CHN_TX_CCK_DELAY_L_B0___M 0x00000007 +#define PHYA_TXTD_CHN_TX_CCK_DELAY_L_B0___S 0 + +#define PHYA_TXTD_CHN_TX_CCK_DELAY_L_B1 (0x003B0C08) +#define PHYA_TXTD_CHN_TX_CCK_DELAY_L_B1___RWC QCSR_REG_RW +#define PHYA_TXTD_CHN_TX_CCK_DELAY_L_B1___POR 0x00000000 +#define PHYA_TXTD_CHN_TX_CCK_DELAY_L_B1__TX_CCK_DELAY___POR 0x0 +#define PHYA_TXTD_CHN_TX_CCK_DELAY_L_B1__TX_CCK_DELAY___M 0x00000007 +#define PHYA_TXTD_CHN_TX_CCK_DELAY_L_B1__TX_CCK_DELAY___S 0 +#define PHYA_TXTD_CHN_TX_CCK_DELAY_L_B1___M 0x00000007 +#define PHYA_TXTD_CHN_TX_CCK_DELAY_L_B1___S 0 + +#define PHYA_TXTD_CHN_TX_PLAYBACK_CHN_CTRL_L_B0 (0x003B0810) +#define PHYA_TXTD_CHN_TX_PLAYBACK_CHN_CTRL_L_B0___RWC QCSR_REG_RW +#define PHYA_TXTD_CHN_TX_PLAYBACK_CHN_CTRL_L_B0___POR 0x00000000 +#define PHYA_TXTD_CHN_TX_PLAYBACK_CHN_CTRL_L_B0__TX_PLYBCK_MIX_DISABLE___POR 0x0 +#define PHYA_TXTD_CHN_TX_PLAYBACK_CHN_CTRL_L_B0__TX_PLYBCK_MIX_DISABLE___M 0x00000001 +#define PHYA_TXTD_CHN_TX_PLAYBACK_CHN_CTRL_L_B0__TX_PLYBCK_MIX_DISABLE___S 0 +#define PHYA_TXTD_CHN_TX_PLAYBACK_CHN_CTRL_L_B0___M 0x00000001 +#define PHYA_TXTD_CHN_TX_PLAYBACK_CHN_CTRL_L_B0___S 0 + +#define PHYA_TXTD_CHN_TX_PLAYBACK_CHN_CTRL_L_B1 (0x003B0C10) +#define PHYA_TXTD_CHN_TX_PLAYBACK_CHN_CTRL_L_B1___RWC QCSR_REG_RW +#define PHYA_TXTD_CHN_TX_PLAYBACK_CHN_CTRL_L_B1___POR 0x00000000 +#define PHYA_TXTD_CHN_TX_PLAYBACK_CHN_CTRL_L_B1__TX_PLYBCK_MIX_DISABLE___POR 0x0 +#define PHYA_TXTD_CHN_TX_PLAYBACK_CHN_CTRL_L_B1__TX_PLYBCK_MIX_DISABLE___M 0x00000001 +#define PHYA_TXTD_CHN_TX_PLAYBACK_CHN_CTRL_L_B1__TX_PLYBCK_MIX_DISABLE___S 0 +#define PHYA_TXTD_CHN_TX_PLAYBACK_CHN_CTRL_L_B1___M 0x00000001 +#define PHYA_TXTD_CHN_TX_PLAYBACK_CHN_CTRL_L_B1___S 0 + +#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_L_B0 (0x003B0818) +#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_L_B0___RWC QCSR_REG_RW +#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_L_B0___POR 0x00000000 +#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_L_B0__CHN_PKT_START_WR_SPARE_0___POR 0x00000000 +#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_L_B0__CHN_PKT_START_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_L_B0__CHN_PKT_START_WR_SPARE_0___S 0 +#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_L_B0___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_L_B0___S 0 + +#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_L_B1 (0x003B0C18) +#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_L_B1___RWC QCSR_REG_RW +#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_L_B1___POR 0x00000000 +#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_L_B1__CHN_PKT_START_WR_SPARE_0___POR 0x00000000 +#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_L_B1__CHN_PKT_START_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_L_B1__CHN_PKT_START_WR_SPARE_0___S 0 +#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_L_B1___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_L_B1___S 0 + +#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_U_B0 (0x003B081C) +#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_U_B0___RWC QCSR_REG_RW +#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_U_B0___POR 0x00000000 +#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_U_B0__CHN_PKT_START_WR_SPARE_1___POR 0x00000000 +#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_U_B0__CHN_PKT_START_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_U_B0__CHN_PKT_START_WR_SPARE_1___S 0 +#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_U_B0___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_U_B0___S 0 + +#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_U_B1 (0x003B0C1C) +#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_U_B1___RWC QCSR_REG_RW +#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_U_B1___POR 0x00000000 +#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_U_B1__CHN_PKT_START_WR_SPARE_1___POR 0x00000000 +#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_U_B1__CHN_PKT_START_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_U_B1__CHN_PKT_START_WR_SPARE_1___S 0 +#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_U_B1___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_CHN_PKT_START_WR_SPARE_U_B1___S 0 + +#define PHYA_TXTD_CHN_ERROR_CODE_CHN_L_B0 (0x003B0820) +#define PHYA_TXTD_CHN_ERROR_CODE_CHN_L_B0___RWC QCSR_REG_RO +#define PHYA_TXTD_CHN_ERROR_CODE_CHN_L_B0___POR 0x00000000 +#define PHYA_TXTD_CHN_ERROR_CODE_CHN_L_B0__ERROR_CODE_CHN___POR 0x00000000 +#define PHYA_TXTD_CHN_ERROR_CODE_CHN_L_B0__ERROR_CODE_CHN___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_ERROR_CODE_CHN_L_B0__ERROR_CODE_CHN___S 0 +#define PHYA_TXTD_CHN_ERROR_CODE_CHN_L_B0___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_ERROR_CODE_CHN_L_B0___S 0 + +#define PHYA_TXTD_CHN_ERROR_CODE_CHN_L_B1 (0x003B0C20) +#define PHYA_TXTD_CHN_ERROR_CODE_CHN_L_B1___RWC QCSR_REG_RO +#define PHYA_TXTD_CHN_ERROR_CODE_CHN_L_B1___POR 0x00000000 +#define PHYA_TXTD_CHN_ERROR_CODE_CHN_L_B1__ERROR_CODE_CHN___POR 0x00000000 +#define PHYA_TXTD_CHN_ERROR_CODE_CHN_L_B1__ERROR_CODE_CHN___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_ERROR_CODE_CHN_L_B1__ERROR_CODE_CHN___S 0 +#define PHYA_TXTD_CHN_ERROR_CODE_CHN_L_B1___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_ERROR_CODE_CHN_L_B1___S 0 + +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B0 (0x003B0828) +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B0___RWC QCSR_REG_RO +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B0___POR 0x00000000 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B0__ERROR_SPARE_CHN___POR 0x0000 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B0__VSRC160_OVERFLOW_ERROR___POR 0x0 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B0__TXFIR_OVERFLOW_ERROR___POR 0x0 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B0__VSRC_OVERFLOW_ERROR___POR 0x0 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B0__FIRX2_OVERFLOW_ERROR___POR 0x0 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B0__TX_IFFT_UNDERRUN_ERROR___POR 0x0 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B0__ERROR_SPARE_CHN___M 0x001FFFE0 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B0__ERROR_SPARE_CHN___S 5 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B0__VSRC160_OVERFLOW_ERROR___M 0x00000010 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B0__VSRC160_OVERFLOW_ERROR___S 4 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B0__TXFIR_OVERFLOW_ERROR___M 0x00000008 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B0__TXFIR_OVERFLOW_ERROR___S 3 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B0__VSRC_OVERFLOW_ERROR___M 0x00000004 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B0__VSRC_OVERFLOW_ERROR___S 2 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B0__FIRX2_OVERFLOW_ERROR___M 0x00000002 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B0__FIRX2_OVERFLOW_ERROR___S 1 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B0__TX_IFFT_UNDERRUN_ERROR___M 0x00000001 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B0__TX_IFFT_UNDERRUN_ERROR___S 0 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B0___M 0x001FFFFF +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B0___S 0 + +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B1 (0x003B0C28) +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B1___RWC QCSR_REG_RO +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B1___POR 0x00000000 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B1__ERROR_SPARE_CHN___POR 0x0000 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B1__VSRC160_OVERFLOW_ERROR___POR 0x0 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B1__TXFIR_OVERFLOW_ERROR___POR 0x0 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B1__VSRC_OVERFLOW_ERROR___POR 0x0 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B1__FIRX2_OVERFLOW_ERROR___POR 0x0 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B1__TX_IFFT_UNDERRUN_ERROR___POR 0x0 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B1__ERROR_SPARE_CHN___M 0x001FFFE0 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B1__ERROR_SPARE_CHN___S 5 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B1__VSRC160_OVERFLOW_ERROR___M 0x00000010 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B1__VSRC160_OVERFLOW_ERROR___S 4 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B1__TXFIR_OVERFLOW_ERROR___M 0x00000008 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B1__TXFIR_OVERFLOW_ERROR___S 3 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B1__VSRC_OVERFLOW_ERROR___M 0x00000004 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B1__VSRC_OVERFLOW_ERROR___S 2 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B1__FIRX2_OVERFLOW_ERROR___M 0x00000002 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B1__FIRX2_OVERFLOW_ERROR___S 1 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B1__TX_IFFT_UNDERRUN_ERROR___M 0x00000001 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B1__TX_IFFT_UNDERRUN_ERROR___S 0 +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B1___M 0x001FFFFF +#define PHYA_TXTD_CHN_ERROR_STATUS_L_B1___S 0 + +#define PHYA_TXTD_CHN_ERROR_MASK_L_B0 (0x003B0830) +#define PHYA_TXTD_CHN_ERROR_MASK_L_B0___RWC QCSR_REG_RW +#define PHYA_TXTD_CHN_ERROR_MASK_L_B0___POR 0x001FFFFF +#define PHYA_TXTD_CHN_ERROR_MASK_L_B0__ERROR_SPARE_CHN_MASK___POR 0xFFFF +#define PHYA_TXTD_CHN_ERROR_MASK_L_B0__VSRC160_OVERFLOW_ERROR_MASK___POR 0x1 +#define PHYA_TXTD_CHN_ERROR_MASK_L_B0__TXFIR_OVERFLOW_ERROR_MASK___POR 0x1 +#define PHYA_TXTD_CHN_ERROR_MASK_L_B0__VSRC_OVERFLOW_ERROR_MASK___POR 0x1 +#define PHYA_TXTD_CHN_ERROR_MASK_L_B0__FIRX2_OVERFLOW_ERROR_MASK___POR 0x1 +#define PHYA_TXTD_CHN_ERROR_MASK_L_B0__TX_IFFT_UNDERRUN_ERROR_MASK___POR 0x1 +#define PHYA_TXTD_CHN_ERROR_MASK_L_B0__ERROR_SPARE_CHN_MASK___M 0x001FFFE0 +#define PHYA_TXTD_CHN_ERROR_MASK_L_B0__ERROR_SPARE_CHN_MASK___S 5 +#define PHYA_TXTD_CHN_ERROR_MASK_L_B0__VSRC160_OVERFLOW_ERROR_MASK___M 0x00000010 +#define PHYA_TXTD_CHN_ERROR_MASK_L_B0__VSRC160_OVERFLOW_ERROR_MASK___S 4 +#define PHYA_TXTD_CHN_ERROR_MASK_L_B0__TXFIR_OVERFLOW_ERROR_MASK___M 0x00000008 +#define PHYA_TXTD_CHN_ERROR_MASK_L_B0__TXFIR_OVERFLOW_ERROR_MASK___S 3 +#define PHYA_TXTD_CHN_ERROR_MASK_L_B0__VSRC_OVERFLOW_ERROR_MASK___M 0x00000004 +#define PHYA_TXTD_CHN_ERROR_MASK_L_B0__VSRC_OVERFLOW_ERROR_MASK___S 2 +#define PHYA_TXTD_CHN_ERROR_MASK_L_B0__FIRX2_OVERFLOW_ERROR_MASK___M 0x00000002 +#define PHYA_TXTD_CHN_ERROR_MASK_L_B0__FIRX2_OVERFLOW_ERROR_MASK___S 1 +#define PHYA_TXTD_CHN_ERROR_MASK_L_B0__TX_IFFT_UNDERRUN_ERROR_MASK___M 0x00000001 +#define PHYA_TXTD_CHN_ERROR_MASK_L_B0__TX_IFFT_UNDERRUN_ERROR_MASK___S 0 +#define PHYA_TXTD_CHN_ERROR_MASK_L_B0___M 0x001FFFFF +#define PHYA_TXTD_CHN_ERROR_MASK_L_B0___S 0 + +#define PHYA_TXTD_CHN_ERROR_MASK_L_B1 (0x003B0C30) +#define PHYA_TXTD_CHN_ERROR_MASK_L_B1___RWC QCSR_REG_RW +#define PHYA_TXTD_CHN_ERROR_MASK_L_B1___POR 0x001FFFFF +#define PHYA_TXTD_CHN_ERROR_MASK_L_B1__ERROR_SPARE_CHN_MASK___POR 0xFFFF +#define PHYA_TXTD_CHN_ERROR_MASK_L_B1__VSRC160_OVERFLOW_ERROR_MASK___POR 0x1 +#define PHYA_TXTD_CHN_ERROR_MASK_L_B1__TXFIR_OVERFLOW_ERROR_MASK___POR 0x1 +#define PHYA_TXTD_CHN_ERROR_MASK_L_B1__VSRC_OVERFLOW_ERROR_MASK___POR 0x1 +#define PHYA_TXTD_CHN_ERROR_MASK_L_B1__FIRX2_OVERFLOW_ERROR_MASK___POR 0x1 +#define PHYA_TXTD_CHN_ERROR_MASK_L_B1__TX_IFFT_UNDERRUN_ERROR_MASK___POR 0x1 +#define PHYA_TXTD_CHN_ERROR_MASK_L_B1__ERROR_SPARE_CHN_MASK___M 0x001FFFE0 +#define PHYA_TXTD_CHN_ERROR_MASK_L_B1__ERROR_SPARE_CHN_MASK___S 5 +#define PHYA_TXTD_CHN_ERROR_MASK_L_B1__VSRC160_OVERFLOW_ERROR_MASK___M 0x00000010 +#define PHYA_TXTD_CHN_ERROR_MASK_L_B1__VSRC160_OVERFLOW_ERROR_MASK___S 4 +#define PHYA_TXTD_CHN_ERROR_MASK_L_B1__TXFIR_OVERFLOW_ERROR_MASK___M 0x00000008 +#define PHYA_TXTD_CHN_ERROR_MASK_L_B1__TXFIR_OVERFLOW_ERROR_MASK___S 3 +#define PHYA_TXTD_CHN_ERROR_MASK_L_B1__VSRC_OVERFLOW_ERROR_MASK___M 0x00000004 +#define PHYA_TXTD_CHN_ERROR_MASK_L_B1__VSRC_OVERFLOW_ERROR_MASK___S 2 +#define PHYA_TXTD_CHN_ERROR_MASK_L_B1__FIRX2_OVERFLOW_ERROR_MASK___M 0x00000002 +#define PHYA_TXTD_CHN_ERROR_MASK_L_B1__FIRX2_OVERFLOW_ERROR_MASK___S 1 +#define PHYA_TXTD_CHN_ERROR_MASK_L_B1__TX_IFFT_UNDERRUN_ERROR_MASK___M 0x00000001 +#define PHYA_TXTD_CHN_ERROR_MASK_L_B1__TX_IFFT_UNDERRUN_ERROR_MASK___S 0 +#define PHYA_TXTD_CHN_ERROR_MASK_L_B1___M 0x001FFFFF +#define PHYA_TXTD_CHN_ERROR_MASK_L_B1___S 0 + +#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_L_B0 (0x003B0838) +#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_L_B0___RWC QCSR_REG_RW +#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_L_B0___POR 0x00000000 +#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_L_B0__PRIVATE_SPARE_CHN_0___POR 0x00000000 +#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_L_B0__PRIVATE_SPARE_CHN_0___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_L_B0__PRIVATE_SPARE_CHN_0___S 0 +#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_L_B0___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_L_B0___S 0 + +#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_L_B1 (0x003B0C38) +#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_L_B1___RWC QCSR_REG_RW +#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_L_B1___POR 0x00000000 +#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_L_B1__PRIVATE_SPARE_CHN_0___POR 0x00000000 +#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_L_B1__PRIVATE_SPARE_CHN_0___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_L_B1__PRIVATE_SPARE_CHN_0___S 0 +#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_L_B1___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_L_B1___S 0 + +#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_U_B0 (0x003B083C) +#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_U_B0___RWC QCSR_REG_RW +#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_U_B0___POR 0x00000000 +#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_U_B0__PRIVATE_SPARE_CHN_1___POR 0x00000000 +#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_U_B0__PRIVATE_SPARE_CHN_1___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_U_B0__PRIVATE_SPARE_CHN_1___S 0 +#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_U_B0___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_U_B0___S 0 + +#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_U_B1 (0x003B0C3C) +#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_U_B1___RWC QCSR_REG_RW +#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_U_B1___POR 0x00000000 +#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_U_B1__PRIVATE_SPARE_CHN_1___POR 0x00000000 +#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_U_B1__PRIVATE_SPARE_CHN_1___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_U_B1__PRIVATE_SPARE_CHN_1___S 0 +#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_U_B1___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_PRIVATE_SPARE_CHN_U_B1___S 0 + +#define PHYA_TXTD_CHN_STATUS_CHN_L_B0 (0x003B0840) +#define PHYA_TXTD_CHN_STATUS_CHN_L_B0___RWC QCSR_REG_RO +#define PHYA_TXTD_CHN_STATUS_CHN_L_B0___POR 0x00000000 +#define PHYA_TXTD_CHN_STATUS_CHN_L_B0__CSR_TXTD_STATUS_CHN_0___POR 0x00000000 +#define PHYA_TXTD_CHN_STATUS_CHN_L_B0__CSR_TXTD_STATUS_CHN_0___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_STATUS_CHN_L_B0__CSR_TXTD_STATUS_CHN_0___S 0 +#define PHYA_TXTD_CHN_STATUS_CHN_L_B0___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_STATUS_CHN_L_B0___S 0 + +#define PHYA_TXTD_CHN_STATUS_CHN_L_B1 (0x003B0C40) +#define PHYA_TXTD_CHN_STATUS_CHN_L_B1___RWC QCSR_REG_RO +#define PHYA_TXTD_CHN_STATUS_CHN_L_B1___POR 0x00000000 +#define PHYA_TXTD_CHN_STATUS_CHN_L_B1__CSR_TXTD_STATUS_CHN_0___POR 0x00000000 +#define PHYA_TXTD_CHN_STATUS_CHN_L_B1__CSR_TXTD_STATUS_CHN_0___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_STATUS_CHN_L_B1__CSR_TXTD_STATUS_CHN_0___S 0 +#define PHYA_TXTD_CHN_STATUS_CHN_L_B1___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_STATUS_CHN_L_B1___S 0 + +#define PHYA_TXTD_CHN_STATUS_CHN_U_B0 (0x003B0844) +#define PHYA_TXTD_CHN_STATUS_CHN_U_B0___RWC QCSR_REG_RO +#define PHYA_TXTD_CHN_STATUS_CHN_U_B0___POR 0x00000000 +#define PHYA_TXTD_CHN_STATUS_CHN_U_B0__CSR_TXTD_STATUS_CHN_1___POR 0x00000000 +#define PHYA_TXTD_CHN_STATUS_CHN_U_B0__CSR_TXTD_STATUS_CHN_1___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_STATUS_CHN_U_B0__CSR_TXTD_STATUS_CHN_1___S 0 +#define PHYA_TXTD_CHN_STATUS_CHN_U_B0___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_STATUS_CHN_U_B0___S 0 + +#define PHYA_TXTD_CHN_STATUS_CHN_U_B1 (0x003B0C44) +#define PHYA_TXTD_CHN_STATUS_CHN_U_B1___RWC QCSR_REG_RO +#define PHYA_TXTD_CHN_STATUS_CHN_U_B1___POR 0x00000000 +#define PHYA_TXTD_CHN_STATUS_CHN_U_B1__CSR_TXTD_STATUS_CHN_1___POR 0x00000000 +#define PHYA_TXTD_CHN_STATUS_CHN_U_B1__CSR_TXTD_STATUS_CHN_1___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_STATUS_CHN_U_B1__CSR_TXTD_STATUS_CHN_1___S 0 +#define PHYA_TXTD_CHN_STATUS_CHN_U_B1___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_STATUS_CHN_U_B1___S 0 + +#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_L_B0 (0x003B0848) +#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_L_B0___RWC QCSR_REG_RW +#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_L_B0___POR 0x00000000 +#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_L_B0__PUBLIC_SPARE_CHN_0___POR 0x00000000 +#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_L_B0__PUBLIC_SPARE_CHN_0___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_L_B0__PUBLIC_SPARE_CHN_0___S 0 +#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_L_B0___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_L_B0___S 0 + +#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_L_B1 (0x003B0C48) +#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_L_B1___RWC QCSR_REG_RW +#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_L_B1___POR 0x00000000 +#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_L_B1__PUBLIC_SPARE_CHN_0___POR 0x00000000 +#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_L_B1__PUBLIC_SPARE_CHN_0___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_L_B1__PUBLIC_SPARE_CHN_0___S 0 +#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_L_B1___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_L_B1___S 0 + +#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_U_B0 (0x003B084C) +#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_U_B0___RWC QCSR_REG_RW +#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_U_B0___POR 0x00000000 +#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_U_B0__PUBLIC_SPARE_CHN_1___POR 0x00000000 +#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_U_B0__PUBLIC_SPARE_CHN_1___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_U_B0__PUBLIC_SPARE_CHN_1___S 0 +#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_U_B0___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_U_B0___S 0 + +#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_U_B1 (0x003B0C4C) +#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_U_B1___RWC QCSR_REG_RW +#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_U_B1___POR 0x00000000 +#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_U_B1__PUBLIC_SPARE_CHN_1___POR 0x00000000 +#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_U_B1__PUBLIC_SPARE_CHN_1___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_U_B1__PUBLIC_SPARE_CHN_1___S 0 +#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_U_B1___M 0xFFFFFFFF +#define PHYA_TXTD_CHN_PUBLIC_SPARE_CHN_U_B1___S 0 + +#define PHYA_TXTD_HCF_SETS_0_L (0x003B5000) +#define PHYA_TXTD_HCF_SETS_0_L___RWC QCSR_REG_RW +#define PHYA_TXTD_HCF_SETS_0_L___POR 0x4949494B +#define PHYA_TXTD_HCF_SETS_0_L__HCF_SETS_HEAVY_03___POR 0x49 +#define PHYA_TXTD_HCF_SETS_0_L__HCF_SETS_HEAVY_02___POR 0x49 +#define PHYA_TXTD_HCF_SETS_0_L__HCF_SETS_HEAVY_01___POR 0x49 +#define PHYA_TXTD_HCF_SETS_0_L__HCF_SETS_HEAVY_00___POR 0x4B +#define PHYA_TXTD_HCF_SETS_0_L__HCF_SETS_HEAVY_03___M 0x7F000000 +#define PHYA_TXTD_HCF_SETS_0_L__HCF_SETS_HEAVY_03___S 24 +#define PHYA_TXTD_HCF_SETS_0_L__HCF_SETS_HEAVY_02___M 0x007F0000 +#define PHYA_TXTD_HCF_SETS_0_L__HCF_SETS_HEAVY_02___S 16 +#define PHYA_TXTD_HCF_SETS_0_L__HCF_SETS_HEAVY_01___M 0x00007F00 +#define PHYA_TXTD_HCF_SETS_0_L__HCF_SETS_HEAVY_01___S 8 +#define PHYA_TXTD_HCF_SETS_0_L__HCF_SETS_HEAVY_00___M 0x0000007F +#define PHYA_TXTD_HCF_SETS_0_L__HCF_SETS_HEAVY_00___S 0 +#define PHYA_TXTD_HCF_SETS_0_L___M 0x7F7F7F7F +#define PHYA_TXTD_HCF_SETS_0_L___S 0 + +#define PHYA_TXTD_HCF_SETS_0_U (0x003B5004) +#define PHYA_TXTD_HCF_SETS_0_U___RWC QCSR_REG_RW +#define PHYA_TXTD_HCF_SETS_0_U___POR 0x49494948 +#define PHYA_TXTD_HCF_SETS_0_U__HCF_SETS_HEAVY_07___POR 0x49 +#define PHYA_TXTD_HCF_SETS_0_U__HCF_SETS_HEAVY_06___POR 0x49 +#define PHYA_TXTD_HCF_SETS_0_U__HCF_SETS_HEAVY_05___POR 0x49 +#define PHYA_TXTD_HCF_SETS_0_U__HCF_SETS_HEAVY_04___POR 0x48 +#define PHYA_TXTD_HCF_SETS_0_U__HCF_SETS_HEAVY_07___M 0x7F000000 +#define PHYA_TXTD_HCF_SETS_0_U__HCF_SETS_HEAVY_07___S 24 +#define PHYA_TXTD_HCF_SETS_0_U__HCF_SETS_HEAVY_06___M 0x007F0000 +#define PHYA_TXTD_HCF_SETS_0_U__HCF_SETS_HEAVY_06___S 16 +#define PHYA_TXTD_HCF_SETS_0_U__HCF_SETS_HEAVY_05___M 0x00007F00 +#define PHYA_TXTD_HCF_SETS_0_U__HCF_SETS_HEAVY_05___S 8 +#define PHYA_TXTD_HCF_SETS_0_U__HCF_SETS_HEAVY_04___M 0x0000007F +#define PHYA_TXTD_HCF_SETS_0_U__HCF_SETS_HEAVY_04___S 0 +#define PHYA_TXTD_HCF_SETS_0_U___M 0x7F7F7F7F +#define PHYA_TXTD_HCF_SETS_0_U___S 0 + +#define PHYA_TXTD_HCF_SETS_1_L (0x003B5008) +#define PHYA_TXTD_HCF_SETS_1_L___RWC QCSR_REG_RW +#define PHYA_TXTD_HCF_SETS_1_L___POR 0x49494946 +#define PHYA_TXTD_HCF_SETS_1_L__HCF_SETS_HEAVY_11___POR 0x49 +#define PHYA_TXTD_HCF_SETS_1_L__HCF_SETS_HEAVY_10___POR 0x49 +#define PHYA_TXTD_HCF_SETS_1_L__HCF_SETS_HEAVY_09___POR 0x49 +#define PHYA_TXTD_HCF_SETS_1_L__HCF_SETS_HEAVY_08___POR 0x46 +#define PHYA_TXTD_HCF_SETS_1_L__HCF_SETS_HEAVY_11___M 0x7F000000 +#define PHYA_TXTD_HCF_SETS_1_L__HCF_SETS_HEAVY_11___S 24 +#define PHYA_TXTD_HCF_SETS_1_L__HCF_SETS_HEAVY_10___M 0x007F0000 +#define PHYA_TXTD_HCF_SETS_1_L__HCF_SETS_HEAVY_10___S 16 +#define PHYA_TXTD_HCF_SETS_1_L__HCF_SETS_HEAVY_09___M 0x00007F00 +#define PHYA_TXTD_HCF_SETS_1_L__HCF_SETS_HEAVY_09___S 8 +#define PHYA_TXTD_HCF_SETS_1_L__HCF_SETS_HEAVY_08___M 0x0000007F +#define PHYA_TXTD_HCF_SETS_1_L__HCF_SETS_HEAVY_08___S 0 +#define PHYA_TXTD_HCF_SETS_1_L___M 0x7F7F7F7F +#define PHYA_TXTD_HCF_SETS_1_L___S 0 + +#define PHYA_TXTD_HCF_SETS_1_U (0x003B500C) +#define PHYA_TXTD_HCF_SETS_1_U___RWC QCSR_REG_RW +#define PHYA_TXTD_HCF_SETS_1_U___POR 0x49494946 +#define PHYA_TXTD_HCF_SETS_1_U__HCF_SETS_HEAVY_15___POR 0x49 +#define PHYA_TXTD_HCF_SETS_1_U__HCF_SETS_HEAVY_14___POR 0x49 +#define PHYA_TXTD_HCF_SETS_1_U__HCF_SETS_HEAVY_13___POR 0x49 +#define PHYA_TXTD_HCF_SETS_1_U__HCF_SETS_HEAVY_12___POR 0x46 +#define PHYA_TXTD_HCF_SETS_1_U__HCF_SETS_HEAVY_15___M 0x7F000000 +#define PHYA_TXTD_HCF_SETS_1_U__HCF_SETS_HEAVY_15___S 24 +#define PHYA_TXTD_HCF_SETS_1_U__HCF_SETS_HEAVY_14___M 0x007F0000 +#define PHYA_TXTD_HCF_SETS_1_U__HCF_SETS_HEAVY_14___S 16 +#define PHYA_TXTD_HCF_SETS_1_U__HCF_SETS_HEAVY_13___M 0x00007F00 +#define PHYA_TXTD_HCF_SETS_1_U__HCF_SETS_HEAVY_13___S 8 +#define PHYA_TXTD_HCF_SETS_1_U__HCF_SETS_HEAVY_12___M 0x0000007F +#define PHYA_TXTD_HCF_SETS_1_U__HCF_SETS_HEAVY_12___S 0 +#define PHYA_TXTD_HCF_SETS_1_U___M 0x7F7F7F7F +#define PHYA_TXTD_HCF_SETS_1_U___S 0 + +#define PHYA_TXTD_HCF_SETS_2_L (0x003B5010) +#define PHYA_TXTD_HCF_SETS_2_L___RWC QCSR_REG_RW +#define PHYA_TXTD_HCF_SETS_2_L___POR 0x36333431 +#define PHYA_TXTD_HCF_SETS_2_L__HCF_SETS_LITE_03___POR 0x36 +#define PHYA_TXTD_HCF_SETS_2_L__HCF_SETS_LITE_02___POR 0x33 +#define PHYA_TXTD_HCF_SETS_2_L__HCF_SETS_LITE_01___POR 0x34 +#define PHYA_TXTD_HCF_SETS_2_L__HCF_SETS_LITE_00___POR 0x31 +#define PHYA_TXTD_HCF_SETS_2_L__HCF_SETS_LITE_03___M 0x7F000000 +#define PHYA_TXTD_HCF_SETS_2_L__HCF_SETS_LITE_03___S 24 +#define PHYA_TXTD_HCF_SETS_2_L__HCF_SETS_LITE_02___M 0x007F0000 +#define PHYA_TXTD_HCF_SETS_2_L__HCF_SETS_LITE_02___S 16 +#define PHYA_TXTD_HCF_SETS_2_L__HCF_SETS_LITE_01___M 0x00007F00 +#define PHYA_TXTD_HCF_SETS_2_L__HCF_SETS_LITE_01___S 8 +#define PHYA_TXTD_HCF_SETS_2_L__HCF_SETS_LITE_00___M 0x0000007F +#define PHYA_TXTD_HCF_SETS_2_L__HCF_SETS_LITE_00___S 0 +#define PHYA_TXTD_HCF_SETS_2_L___M 0x7F7F7F7F +#define PHYA_TXTD_HCF_SETS_2_L___S 0 + +#define PHYA_TXTD_HCF_SETS_2_U (0x003B5014) +#define PHYA_TXTD_HCF_SETS_2_U___RWC QCSR_REG_RW +#define PHYA_TXTD_HCF_SETS_2_U___POR 0x36333231 +#define PHYA_TXTD_HCF_SETS_2_U__HCF_SETS_LITE_07___POR 0x36 +#define PHYA_TXTD_HCF_SETS_2_U__HCF_SETS_LITE_06___POR 0x33 +#define PHYA_TXTD_HCF_SETS_2_U__HCF_SETS_LITE_05___POR 0x32 +#define PHYA_TXTD_HCF_SETS_2_U__HCF_SETS_LITE_04___POR 0x31 +#define PHYA_TXTD_HCF_SETS_2_U__HCF_SETS_LITE_07___M 0x7F000000 +#define PHYA_TXTD_HCF_SETS_2_U__HCF_SETS_LITE_07___S 24 +#define PHYA_TXTD_HCF_SETS_2_U__HCF_SETS_LITE_06___M 0x007F0000 +#define PHYA_TXTD_HCF_SETS_2_U__HCF_SETS_LITE_06___S 16 +#define PHYA_TXTD_HCF_SETS_2_U__HCF_SETS_LITE_05___M 0x00007F00 +#define PHYA_TXTD_HCF_SETS_2_U__HCF_SETS_LITE_05___S 8 +#define PHYA_TXTD_HCF_SETS_2_U__HCF_SETS_LITE_04___M 0x0000007F +#define PHYA_TXTD_HCF_SETS_2_U__HCF_SETS_LITE_04___S 0 +#define PHYA_TXTD_HCF_SETS_2_U___M 0x7F7F7F7F +#define PHYA_TXTD_HCF_SETS_2_U___S 0 + +#define PHYA_TXTD_HCF_SETS_3_L (0x003B5018) +#define PHYA_TXTD_HCF_SETS_3_L___RWC QCSR_REG_RW +#define PHYA_TXTD_HCF_SETS_3_L___POR 0x36333230 +#define PHYA_TXTD_HCF_SETS_3_L__HCF_SETS_LITE_11___POR 0x36 +#define PHYA_TXTD_HCF_SETS_3_L__HCF_SETS_LITE_10___POR 0x33 +#define PHYA_TXTD_HCF_SETS_3_L__HCF_SETS_LITE_09___POR 0x32 +#define PHYA_TXTD_HCF_SETS_3_L__HCF_SETS_LITE_08___POR 0x30 +#define PHYA_TXTD_HCF_SETS_3_L__HCF_SETS_LITE_11___M 0x7F000000 +#define PHYA_TXTD_HCF_SETS_3_L__HCF_SETS_LITE_11___S 24 +#define PHYA_TXTD_HCF_SETS_3_L__HCF_SETS_LITE_10___M 0x007F0000 +#define PHYA_TXTD_HCF_SETS_3_L__HCF_SETS_LITE_10___S 16 +#define PHYA_TXTD_HCF_SETS_3_L__HCF_SETS_LITE_09___M 0x00007F00 +#define PHYA_TXTD_HCF_SETS_3_L__HCF_SETS_LITE_09___S 8 +#define PHYA_TXTD_HCF_SETS_3_L__HCF_SETS_LITE_08___M 0x0000007F +#define PHYA_TXTD_HCF_SETS_3_L__HCF_SETS_LITE_08___S 0 +#define PHYA_TXTD_HCF_SETS_3_L___M 0x7F7F7F7F +#define PHYA_TXTD_HCF_SETS_3_L___S 0 + +#define PHYA_TXTD_HCF_SETS_3_U (0x003B501C) +#define PHYA_TXTD_HCF_SETS_3_U___RWC QCSR_REG_RW +#define PHYA_TXTD_HCF_SETS_3_U___POR 0x36333230 +#define PHYA_TXTD_HCF_SETS_3_U__HCF_SETS_LITE_15___POR 0x36 +#define PHYA_TXTD_HCF_SETS_3_U__HCF_SETS_LITE_14___POR 0x33 +#define PHYA_TXTD_HCF_SETS_3_U__HCF_SETS_LITE_13___POR 0x32 +#define PHYA_TXTD_HCF_SETS_3_U__HCF_SETS_LITE_12___POR 0x30 +#define PHYA_TXTD_HCF_SETS_3_U__HCF_SETS_LITE_15___M 0x7F000000 +#define PHYA_TXTD_HCF_SETS_3_U__HCF_SETS_LITE_15___S 24 +#define PHYA_TXTD_HCF_SETS_3_U__HCF_SETS_LITE_14___M 0x007F0000 +#define PHYA_TXTD_HCF_SETS_3_U__HCF_SETS_LITE_14___S 16 +#define PHYA_TXTD_HCF_SETS_3_U__HCF_SETS_LITE_13___M 0x00007F00 +#define PHYA_TXTD_HCF_SETS_3_U__HCF_SETS_LITE_13___S 8 +#define PHYA_TXTD_HCF_SETS_3_U__HCF_SETS_LITE_12___M 0x0000007F +#define PHYA_TXTD_HCF_SETS_3_U__HCF_SETS_LITE_12___S 0 +#define PHYA_TXTD_HCF_SETS_3_U___M 0x7F7F7F7F +#define PHYA_TXTD_HCF_SETS_3_U___S 0 + +#define PHYA_TXTD_HCF_SETS_4_L (0x003B5020) +#define PHYA_TXTD_HCF_SETS_4_L___RWC QCSR_REG_RW +#define PHYA_TXTD_HCF_SETS_4_L___POR 0x3E3A4B3E +#define PHYA_TXTD_HCF_SETS_4_L__HCF_NONHTDUP_SETS_HEAVY_3___POR 0x3E +#define PHYA_TXTD_HCF_SETS_4_L__HCF_NONHTDUP_SETS_HEAVY_2___POR 0x3A +#define PHYA_TXTD_HCF_SETS_4_L__HCF_NONHTDUP_SETS_HEAVY_1___POR 0x4B +#define PHYA_TXTD_HCF_SETS_4_L__HCF_NONHTDUP_SETS_HEAVY_0___POR 0x3E +#define PHYA_TXTD_HCF_SETS_4_L__HCF_NONHTDUP_SETS_HEAVY_3___M 0x7F000000 +#define PHYA_TXTD_HCF_SETS_4_L__HCF_NONHTDUP_SETS_HEAVY_3___S 24 +#define PHYA_TXTD_HCF_SETS_4_L__HCF_NONHTDUP_SETS_HEAVY_2___M 0x007F0000 +#define PHYA_TXTD_HCF_SETS_4_L__HCF_NONHTDUP_SETS_HEAVY_2___S 16 +#define PHYA_TXTD_HCF_SETS_4_L__HCF_NONHTDUP_SETS_HEAVY_1___M 0x00007F00 +#define PHYA_TXTD_HCF_SETS_4_L__HCF_NONHTDUP_SETS_HEAVY_1___S 8 +#define PHYA_TXTD_HCF_SETS_4_L__HCF_NONHTDUP_SETS_HEAVY_0___M 0x0000007F +#define PHYA_TXTD_HCF_SETS_4_L__HCF_NONHTDUP_SETS_HEAVY_0___S 0 +#define PHYA_TXTD_HCF_SETS_4_L___M 0x7F7F7F7F +#define PHYA_TXTD_HCF_SETS_4_L___S 0 + +#define PHYA_TXTD_HCF_SETS_4_U (0x003B5024) +#define PHYA_TXTD_HCF_SETS_4_U___RWC QCSR_REG_RW +#define PHYA_TXTD_HCF_SETS_4_U___POR 0x4B3E3A4B +#define PHYA_TXTD_HCF_SETS_4_U__HCF_NONHTDUP_SETS_HEAVY_7___POR 0x4B +#define PHYA_TXTD_HCF_SETS_4_U__HCF_NONHTDUP_SETS_HEAVY_6___POR 0x3E +#define PHYA_TXTD_HCF_SETS_4_U__HCF_NONHTDUP_SETS_HEAVY_5___POR 0x3A +#define PHYA_TXTD_HCF_SETS_4_U__HCF_NONHTDUP_SETS_HEAVY_4___POR 0x4B +#define PHYA_TXTD_HCF_SETS_4_U__HCF_NONHTDUP_SETS_HEAVY_7___M 0x7F000000 +#define PHYA_TXTD_HCF_SETS_4_U__HCF_NONHTDUP_SETS_HEAVY_7___S 24 +#define PHYA_TXTD_HCF_SETS_4_U__HCF_NONHTDUP_SETS_HEAVY_6___M 0x007F0000 +#define PHYA_TXTD_HCF_SETS_4_U__HCF_NONHTDUP_SETS_HEAVY_6___S 16 +#define PHYA_TXTD_HCF_SETS_4_U__HCF_NONHTDUP_SETS_HEAVY_5___M 0x00007F00 +#define PHYA_TXTD_HCF_SETS_4_U__HCF_NONHTDUP_SETS_HEAVY_5___S 8 +#define PHYA_TXTD_HCF_SETS_4_U__HCF_NONHTDUP_SETS_HEAVY_4___M 0x0000007F +#define PHYA_TXTD_HCF_SETS_4_U__HCF_NONHTDUP_SETS_HEAVY_4___S 0 +#define PHYA_TXTD_HCF_SETS_4_U___M 0x7F7F7F7F +#define PHYA_TXTD_HCF_SETS_4_U___S 0 + +#define PHYA_TXTD_HCF_SETS_5_L (0x003B5028) +#define PHYA_TXTD_HCF_SETS_5_L___RWC QCSR_REG_RW +#define PHYA_TXTD_HCF_SETS_5_L___POR 0x3A4B3E3A +#define PHYA_TXTD_HCF_SETS_5_L__HCF_NONHTDUP_SETS_HEAVY_11___POR 0x3A +#define PHYA_TXTD_HCF_SETS_5_L__HCF_NONHTDUP_SETS_HEAVY_10___POR 0x4B +#define PHYA_TXTD_HCF_SETS_5_L__HCF_NONHTDUP_SETS_HEAVY_9___POR 0x3E +#define PHYA_TXTD_HCF_SETS_5_L__HCF_NONHTDUP_SETS_HEAVY_8___POR 0x3A +#define PHYA_TXTD_HCF_SETS_5_L__HCF_NONHTDUP_SETS_HEAVY_11___M 0x7F000000 +#define PHYA_TXTD_HCF_SETS_5_L__HCF_NONHTDUP_SETS_HEAVY_11___S 24 +#define PHYA_TXTD_HCF_SETS_5_L__HCF_NONHTDUP_SETS_HEAVY_10___M 0x007F0000 +#define PHYA_TXTD_HCF_SETS_5_L__HCF_NONHTDUP_SETS_HEAVY_10___S 16 +#define PHYA_TXTD_HCF_SETS_5_L__HCF_NONHTDUP_SETS_HEAVY_9___M 0x00007F00 +#define PHYA_TXTD_HCF_SETS_5_L__HCF_NONHTDUP_SETS_HEAVY_9___S 8 +#define PHYA_TXTD_HCF_SETS_5_L__HCF_NONHTDUP_SETS_HEAVY_8___M 0x0000007F +#define PHYA_TXTD_HCF_SETS_5_L__HCF_NONHTDUP_SETS_HEAVY_8___S 0 +#define PHYA_TXTD_HCF_SETS_5_L___M 0x7F7F7F7F +#define PHYA_TXTD_HCF_SETS_5_L___S 0 + +#define PHYA_TXTD_HCF_SETS_5_U (0x003B502C) +#define PHYA_TXTD_HCF_SETS_5_U___RWC QCSR_REG_RW +#define PHYA_TXTD_HCF_SETS_5_U___POR 0x282A3128 +#define PHYA_TXTD_HCF_SETS_5_U__HCF_NONHTDUP_SETS_LITE_3___POR 0x28 +#define PHYA_TXTD_HCF_SETS_5_U__HCF_NONHTDUP_SETS_LITE_2___POR 0x2A +#define PHYA_TXTD_HCF_SETS_5_U__HCF_NONHTDUP_SETS_LITE_1___POR 0x31 +#define PHYA_TXTD_HCF_SETS_5_U__HCF_NONHTDUP_SETS_LITE_0___POR 0x28 +#define PHYA_TXTD_HCF_SETS_5_U__HCF_NONHTDUP_SETS_LITE_3___M 0x7F000000 +#define PHYA_TXTD_HCF_SETS_5_U__HCF_NONHTDUP_SETS_LITE_3___S 24 +#define PHYA_TXTD_HCF_SETS_5_U__HCF_NONHTDUP_SETS_LITE_2___M 0x007F0000 +#define PHYA_TXTD_HCF_SETS_5_U__HCF_NONHTDUP_SETS_LITE_2___S 16 +#define PHYA_TXTD_HCF_SETS_5_U__HCF_NONHTDUP_SETS_LITE_1___M 0x00007F00 +#define PHYA_TXTD_HCF_SETS_5_U__HCF_NONHTDUP_SETS_LITE_1___S 8 +#define PHYA_TXTD_HCF_SETS_5_U__HCF_NONHTDUP_SETS_LITE_0___M 0x0000007F +#define PHYA_TXTD_HCF_SETS_5_U__HCF_NONHTDUP_SETS_LITE_0___S 0 +#define PHYA_TXTD_HCF_SETS_5_U___M 0x7F7F7F7F +#define PHYA_TXTD_HCF_SETS_5_U___S 0 + +#define PHYA_TXTD_HCF_SETS_6_L (0x003B5030) +#define PHYA_TXTD_HCF_SETS_6_L___RWC QCSR_REG_RW +#define PHYA_TXTD_HCF_SETS_6_L___POR 0x31282A31 +#define PHYA_TXTD_HCF_SETS_6_L__HCF_NONHTDUP_SETS_LITE_7___POR 0x31 +#define PHYA_TXTD_HCF_SETS_6_L__HCF_NONHTDUP_SETS_LITE_6___POR 0x28 +#define PHYA_TXTD_HCF_SETS_6_L__HCF_NONHTDUP_SETS_LITE_5___POR 0x2A +#define PHYA_TXTD_HCF_SETS_6_L__HCF_NONHTDUP_SETS_LITE_4___POR 0x31 +#define PHYA_TXTD_HCF_SETS_6_L__HCF_NONHTDUP_SETS_LITE_7___M 0x7F000000 +#define PHYA_TXTD_HCF_SETS_6_L__HCF_NONHTDUP_SETS_LITE_7___S 24 +#define PHYA_TXTD_HCF_SETS_6_L__HCF_NONHTDUP_SETS_LITE_6___M 0x007F0000 +#define PHYA_TXTD_HCF_SETS_6_L__HCF_NONHTDUP_SETS_LITE_6___S 16 +#define PHYA_TXTD_HCF_SETS_6_L__HCF_NONHTDUP_SETS_LITE_5___M 0x00007F00 +#define PHYA_TXTD_HCF_SETS_6_L__HCF_NONHTDUP_SETS_LITE_5___S 8 +#define PHYA_TXTD_HCF_SETS_6_L__HCF_NONHTDUP_SETS_LITE_4___M 0x0000007F +#define PHYA_TXTD_HCF_SETS_6_L__HCF_NONHTDUP_SETS_LITE_4___S 0 +#define PHYA_TXTD_HCF_SETS_6_L___M 0x7F7F7F7F +#define PHYA_TXTD_HCF_SETS_6_L___S 0 + +#define PHYA_TXTD_HCF_SETS_6_U (0x003B5034) +#define PHYA_TXTD_HCF_SETS_6_U___RWC QCSR_REG_RW +#define PHYA_TXTD_HCF_SETS_6_U___POR 0x2A31282A +#define PHYA_TXTD_HCF_SETS_6_U__HCF_NONHTDUP_SETS_LITE_11___POR 0x2A +#define PHYA_TXTD_HCF_SETS_6_U__HCF_NONHTDUP_SETS_LITE_10___POR 0x31 +#define PHYA_TXTD_HCF_SETS_6_U__HCF_NONHTDUP_SETS_LITE_9___POR 0x28 +#define PHYA_TXTD_HCF_SETS_6_U__HCF_NONHTDUP_SETS_LITE_8___POR 0x2A +#define PHYA_TXTD_HCF_SETS_6_U__HCF_NONHTDUP_SETS_LITE_11___M 0x7F000000 +#define PHYA_TXTD_HCF_SETS_6_U__HCF_NONHTDUP_SETS_LITE_11___S 24 +#define PHYA_TXTD_HCF_SETS_6_U__HCF_NONHTDUP_SETS_LITE_10___M 0x007F0000 +#define PHYA_TXTD_HCF_SETS_6_U__HCF_NONHTDUP_SETS_LITE_10___S 16 +#define PHYA_TXTD_HCF_SETS_6_U__HCF_NONHTDUP_SETS_LITE_9___M 0x00007F00 +#define PHYA_TXTD_HCF_SETS_6_U__HCF_NONHTDUP_SETS_LITE_9___S 8 +#define PHYA_TXTD_HCF_SETS_6_U__HCF_NONHTDUP_SETS_LITE_8___M 0x0000007F +#define PHYA_TXTD_HCF_SETS_6_U__HCF_NONHTDUP_SETS_LITE_8___S 0 +#define PHYA_TXTD_HCF_SETS_6_U___M 0x7F7F7F7F +#define PHYA_TXTD_HCF_SETS_6_U___S 0 + +#define PHYA_TXTD_HCF_SETS_7_L (0x003B5038) +#define PHYA_TXTD_HCF_SETS_7_L___RWC QCSR_REG_RW +#define PHYA_TXTD_HCF_SETS_7_L___POR 0x49554969 +#define PHYA_TXTD_HCF_SETS_7_L__HCF_80P80_HEAVY_3___POR 0x49 +#define PHYA_TXTD_HCF_SETS_7_L__HCF_80P80_HEAVY_2___POR 0x55 +#define PHYA_TXTD_HCF_SETS_7_L__HCF_80P80_HEAVY_1___POR 0x49 +#define PHYA_TXTD_HCF_SETS_7_L__HCF_80P80_HEAVY_0___POR 0x69 +#define PHYA_TXTD_HCF_SETS_7_L__HCF_80P80_HEAVY_3___M 0x7F000000 +#define PHYA_TXTD_HCF_SETS_7_L__HCF_80P80_HEAVY_3___S 24 +#define PHYA_TXTD_HCF_SETS_7_L__HCF_80P80_HEAVY_2___M 0x007F0000 +#define PHYA_TXTD_HCF_SETS_7_L__HCF_80P80_HEAVY_2___S 16 +#define PHYA_TXTD_HCF_SETS_7_L__HCF_80P80_HEAVY_1___M 0x00007F00 +#define PHYA_TXTD_HCF_SETS_7_L__HCF_80P80_HEAVY_1___S 8 +#define PHYA_TXTD_HCF_SETS_7_L__HCF_80P80_HEAVY_0___M 0x0000007F +#define PHYA_TXTD_HCF_SETS_7_L__HCF_80P80_HEAVY_0___S 0 +#define PHYA_TXTD_HCF_SETS_7_L___M 0x7F7F7F7F +#define PHYA_TXTD_HCF_SETS_7_L___S 0 + +#define PHYA_TXTD_HCF_SETS_7_U (0x003B503C) +#define PHYA_TXTD_HCF_SETS_7_U___RWC QCSR_REG_RW +#define PHYA_TXTD_HCF_SETS_7_U___POR 0x49554969 +#define PHYA_TXTD_HCF_SETS_7_U__HCF_80P80_HEAVY_7___POR 0x49 +#define PHYA_TXTD_HCF_SETS_7_U__HCF_80P80_HEAVY_6___POR 0x55 +#define PHYA_TXTD_HCF_SETS_7_U__HCF_80P80_HEAVY_5___POR 0x49 +#define PHYA_TXTD_HCF_SETS_7_U__HCF_80P80_HEAVY_4___POR 0x69 +#define PHYA_TXTD_HCF_SETS_7_U__HCF_80P80_HEAVY_7___M 0x7F000000 +#define PHYA_TXTD_HCF_SETS_7_U__HCF_80P80_HEAVY_7___S 24 +#define PHYA_TXTD_HCF_SETS_7_U__HCF_80P80_HEAVY_6___M 0x007F0000 +#define PHYA_TXTD_HCF_SETS_7_U__HCF_80P80_HEAVY_6___S 16 +#define PHYA_TXTD_HCF_SETS_7_U__HCF_80P80_HEAVY_5___M 0x00007F00 +#define PHYA_TXTD_HCF_SETS_7_U__HCF_80P80_HEAVY_5___S 8 +#define PHYA_TXTD_HCF_SETS_7_U__HCF_80P80_HEAVY_4___M 0x0000007F +#define PHYA_TXTD_HCF_SETS_7_U__HCF_80P80_HEAVY_4___S 0 +#define PHYA_TXTD_HCF_SETS_7_U___M 0x7F7F7F7F +#define PHYA_TXTD_HCF_SETS_7_U___S 0 + +#define PHYA_TXTD_HCF_SETS_8_L (0x003B5040) +#define PHYA_TXTD_HCF_SETS_8_L___RWC QCSR_REG_RW +#define PHYA_TXTD_HCF_SETS_8_L___POR 0x33493349 +#define PHYA_TXTD_HCF_SETS_8_L__HCF_80P80_LITE_3___POR 0x33 +#define PHYA_TXTD_HCF_SETS_8_L__HCF_80P80_LITE_2___POR 0x49 +#define PHYA_TXTD_HCF_SETS_8_L__HCF_80P80_LITE_1___POR 0x33 +#define PHYA_TXTD_HCF_SETS_8_L__HCF_80P80_LITE_0___POR 0x49 +#define PHYA_TXTD_HCF_SETS_8_L__HCF_80P80_LITE_3___M 0x7F000000 +#define PHYA_TXTD_HCF_SETS_8_L__HCF_80P80_LITE_3___S 24 +#define PHYA_TXTD_HCF_SETS_8_L__HCF_80P80_LITE_2___M 0x007F0000 +#define PHYA_TXTD_HCF_SETS_8_L__HCF_80P80_LITE_2___S 16 +#define PHYA_TXTD_HCF_SETS_8_L__HCF_80P80_LITE_1___M 0x00007F00 +#define PHYA_TXTD_HCF_SETS_8_L__HCF_80P80_LITE_1___S 8 +#define PHYA_TXTD_HCF_SETS_8_L__HCF_80P80_LITE_0___M 0x0000007F +#define PHYA_TXTD_HCF_SETS_8_L__HCF_80P80_LITE_0___S 0 +#define PHYA_TXTD_HCF_SETS_8_L___M 0x7F7F7F7F +#define PHYA_TXTD_HCF_SETS_8_L___S 0 + +#define PHYA_TXTD_HCF_SETS_8_U (0x003B5044) +#define PHYA_TXTD_HCF_SETS_8_U___RWC QCSR_REG_RW +#define PHYA_TXTD_HCF_SETS_8_U___POR 0x33493349 +#define PHYA_TXTD_HCF_SETS_8_U__HCF_80P80_LITE_7___POR 0x33 +#define PHYA_TXTD_HCF_SETS_8_U__HCF_80P80_LITE_6___POR 0x49 +#define PHYA_TXTD_HCF_SETS_8_U__HCF_80P80_LITE_5___POR 0x33 +#define PHYA_TXTD_HCF_SETS_8_U__HCF_80P80_LITE_4___POR 0x49 +#define PHYA_TXTD_HCF_SETS_8_U__HCF_80P80_LITE_7___M 0x7F000000 +#define PHYA_TXTD_HCF_SETS_8_U__HCF_80P80_LITE_7___S 24 +#define PHYA_TXTD_HCF_SETS_8_U__HCF_80P80_LITE_6___M 0x007F0000 +#define PHYA_TXTD_HCF_SETS_8_U__HCF_80P80_LITE_6___S 16 +#define PHYA_TXTD_HCF_SETS_8_U__HCF_80P80_LITE_5___M 0x00007F00 +#define PHYA_TXTD_HCF_SETS_8_U__HCF_80P80_LITE_5___S 8 +#define PHYA_TXTD_HCF_SETS_8_U__HCF_80P80_LITE_4___M 0x0000007F +#define PHYA_TXTD_HCF_SETS_8_U__HCF_80P80_LITE_4___S 0 +#define PHYA_TXTD_HCF_SETS_8_U___M 0x7F7F7F7F +#define PHYA_TXTD_HCF_SETS_8_U___S 0 + +#define PHYA_TXTD_PWR_COMP_SETS_0_L (0x003B5048) +#define PHYA_TXTD_PWR_COMP_SETS_0_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PWR_COMP_SETS_0_L___POR 0x79506B96 +#define PHYA_TXTD_PWR_COMP_SETS_0_L__PWR_COMP_DUP80_0___POR 0x79 +#define PHYA_TXTD_PWR_COMP_SETS_0_L__PWR_COMP_DUP40_2___POR 0x50 +#define PHYA_TXTD_PWR_COMP_SETS_0_L__PWR_COMP_DUP40_1___POR 0x6B +#define PHYA_TXTD_PWR_COMP_SETS_0_L__PWR_COMP_DUP40_0___POR 0x96 +#define PHYA_TXTD_PWR_COMP_SETS_0_L__PWR_COMP_DUP80_0___M 0xFF000000 +#define PHYA_TXTD_PWR_COMP_SETS_0_L__PWR_COMP_DUP80_0___S 24 +#define PHYA_TXTD_PWR_COMP_SETS_0_L__PWR_COMP_DUP40_2___M 0x00FF0000 +#define PHYA_TXTD_PWR_COMP_SETS_0_L__PWR_COMP_DUP40_2___S 16 +#define PHYA_TXTD_PWR_COMP_SETS_0_L__PWR_COMP_DUP40_1___M 0x0000FF00 +#define PHYA_TXTD_PWR_COMP_SETS_0_L__PWR_COMP_DUP40_1___S 8 +#define PHYA_TXTD_PWR_COMP_SETS_0_L__PWR_COMP_DUP40_0___M 0x000000FF +#define PHYA_TXTD_PWR_COMP_SETS_0_L__PWR_COMP_DUP40_0___S 0 +#define PHYA_TXTD_PWR_COMP_SETS_0_L___M 0xFFFFFFFF +#define PHYA_TXTD_PWR_COMP_SETS_0_L___S 0 + +#define PHYA_TXTD_PWR_COMP_SETS_0_U (0x003B504C) +#define PHYA_TXTD_PWR_COMP_SETS_0_U___RWC QCSR_REG_RW +#define PHYA_TXTD_PWR_COMP_SETS_0_U___POR 0x5D863F51 +#define PHYA_TXTD_PWR_COMP_SETS_0_U__PWR_COMP_DUP160_1___POR 0x5D +#define PHYA_TXTD_PWR_COMP_SETS_0_U__PWR_COMP_DUP160_0___POR 0x86 +#define PHYA_TXTD_PWR_COMP_SETS_0_U__PWR_COMP_DUP80_2___POR 0x3F +#define PHYA_TXTD_PWR_COMP_SETS_0_U__PWR_COMP_DUP80_1___POR 0x51 +#define PHYA_TXTD_PWR_COMP_SETS_0_U__PWR_COMP_DUP160_1___M 0xFF000000 +#define PHYA_TXTD_PWR_COMP_SETS_0_U__PWR_COMP_DUP160_1___S 24 +#define PHYA_TXTD_PWR_COMP_SETS_0_U__PWR_COMP_DUP160_0___M 0x00FF0000 +#define PHYA_TXTD_PWR_COMP_SETS_0_U__PWR_COMP_DUP160_0___S 16 +#define PHYA_TXTD_PWR_COMP_SETS_0_U__PWR_COMP_DUP80_2___M 0x0000FF00 +#define PHYA_TXTD_PWR_COMP_SETS_0_U__PWR_COMP_DUP80_2___S 8 +#define PHYA_TXTD_PWR_COMP_SETS_0_U__PWR_COMP_DUP80_1___M 0x000000FF +#define PHYA_TXTD_PWR_COMP_SETS_0_U__PWR_COMP_DUP80_1___S 0 +#define PHYA_TXTD_PWR_COMP_SETS_0_U___M 0xFFFFFFFF +#define PHYA_TXTD_PWR_COMP_SETS_0_U___S 0 + +#define PHYA_TXTD_PWR_COMP_SETS_1_L (0x003B5050) +#define PHYA_TXTD_PWR_COMP_SETS_1_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PWR_COMP_SETS_1_L___POR 0x4E5D864E +#define PHYA_TXTD_PWR_COMP_SETS_1_L__PWR_COMP_DUP160_5___POR 0x4E +#define PHYA_TXTD_PWR_COMP_SETS_1_L__PWR_COMP_DUP160_4___POR 0x5D +#define PHYA_TXTD_PWR_COMP_SETS_1_L__PWR_COMP_DUP160_3___POR 0x86 +#define PHYA_TXTD_PWR_COMP_SETS_1_L__PWR_COMP_DUP160_2___POR 0x4E +#define PHYA_TXTD_PWR_COMP_SETS_1_L__PWR_COMP_DUP160_5___M 0xFF000000 +#define PHYA_TXTD_PWR_COMP_SETS_1_L__PWR_COMP_DUP160_5___S 24 +#define PHYA_TXTD_PWR_COMP_SETS_1_L__PWR_COMP_DUP160_4___M 0x00FF0000 +#define PHYA_TXTD_PWR_COMP_SETS_1_L__PWR_COMP_DUP160_4___S 16 +#define PHYA_TXTD_PWR_COMP_SETS_1_L__PWR_COMP_DUP160_3___M 0x0000FF00 +#define PHYA_TXTD_PWR_COMP_SETS_1_L__PWR_COMP_DUP160_3___S 8 +#define PHYA_TXTD_PWR_COMP_SETS_1_L__PWR_COMP_DUP160_2___M 0x000000FF +#define PHYA_TXTD_PWR_COMP_SETS_1_L__PWR_COMP_DUP160_2___S 0 +#define PHYA_TXTD_PWR_COMP_SETS_1_L___M 0xFFFFFFFF +#define PHYA_TXTD_PWR_COMP_SETS_1_L___S 0 + +#define PHYA_TXTD_PWR_COMP_SETS_1_U (0x003B5054) +#define PHYA_TXTD_PWR_COMP_SETS_1_U___RWC QCSR_REG_RW +#define PHYA_TXTD_PWR_COMP_SETS_1_U___POR 0x864E5D86 +#define PHYA_TXTD_PWR_COMP_SETS_1_U__PWR_COMP_DUP160_9___POR 0x86 +#define PHYA_TXTD_PWR_COMP_SETS_1_U__PWR_COMP_DUP160_8___POR 0x4E +#define PHYA_TXTD_PWR_COMP_SETS_1_U__PWR_COMP_DUP160_7___POR 0x5D +#define PHYA_TXTD_PWR_COMP_SETS_1_U__PWR_COMP_DUP160_6___POR 0x86 +#define PHYA_TXTD_PWR_COMP_SETS_1_U__PWR_COMP_DUP160_9___M 0xFF000000 +#define PHYA_TXTD_PWR_COMP_SETS_1_U__PWR_COMP_DUP160_9___S 24 +#define PHYA_TXTD_PWR_COMP_SETS_1_U__PWR_COMP_DUP160_8___M 0x00FF0000 +#define PHYA_TXTD_PWR_COMP_SETS_1_U__PWR_COMP_DUP160_8___S 16 +#define PHYA_TXTD_PWR_COMP_SETS_1_U__PWR_COMP_DUP160_7___M 0x0000FF00 +#define PHYA_TXTD_PWR_COMP_SETS_1_U__PWR_COMP_DUP160_7___S 8 +#define PHYA_TXTD_PWR_COMP_SETS_1_U__PWR_COMP_DUP160_6___M 0x000000FF +#define PHYA_TXTD_PWR_COMP_SETS_1_U__PWR_COMP_DUP160_6___S 0 +#define PHYA_TXTD_PWR_COMP_SETS_1_U___M 0xFFFFFFFF +#define PHYA_TXTD_PWR_COMP_SETS_1_U___S 0 + +#define PHYA_TXTD_PWR_COMP_SETS_2_L (0x003B5058) +#define PHYA_TXTD_PWR_COMP_SETS_2_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PWR_COMP_SETS_2_L___POR 0x55894E5D +#define PHYA_TXTD_PWR_COMP_SETS_2_L__PWR_COMP_20IN20_1___POR 0x55 +#define PHYA_TXTD_PWR_COMP_SETS_2_L__PWR_COMP_20IN20_0___POR 0x89 +#define PHYA_TXTD_PWR_COMP_SETS_2_L__PWR_COMP_DUP160_11___POR 0x4E +#define PHYA_TXTD_PWR_COMP_SETS_2_L__PWR_COMP_DUP160_10___POR 0x5D +#define PHYA_TXTD_PWR_COMP_SETS_2_L__PWR_COMP_20IN20_1___M 0xFF000000 +#define PHYA_TXTD_PWR_COMP_SETS_2_L__PWR_COMP_20IN20_1___S 24 +#define PHYA_TXTD_PWR_COMP_SETS_2_L__PWR_COMP_20IN20_0___M 0x00FF0000 +#define PHYA_TXTD_PWR_COMP_SETS_2_L__PWR_COMP_20IN20_0___S 16 +#define PHYA_TXTD_PWR_COMP_SETS_2_L__PWR_COMP_DUP160_11___M 0x0000FF00 +#define PHYA_TXTD_PWR_COMP_SETS_2_L__PWR_COMP_DUP160_11___S 8 +#define PHYA_TXTD_PWR_COMP_SETS_2_L__PWR_COMP_DUP160_10___M 0x000000FF +#define PHYA_TXTD_PWR_COMP_SETS_2_L__PWR_COMP_DUP160_10___S 0 +#define PHYA_TXTD_PWR_COMP_SETS_2_L___M 0xFFFFFFFF +#define PHYA_TXTD_PWR_COMP_SETS_2_L___S 0 + +#define PHYA_TXTD_PWR_COMP_SETS_2_U (0x003B505C) +#define PHYA_TXTD_PWR_COMP_SETS_2_U___RWC QCSR_REG_RW +#define PHYA_TXTD_PWR_COMP_SETS_2_U___POR 0x495B8941 +#define PHYA_TXTD_PWR_COMP_SETS_2_U__PWR_COMP_20IN20_5___POR 0x49 +#define PHYA_TXTD_PWR_COMP_SETS_2_U__PWR_COMP_20IN20_4___POR 0x5B +#define PHYA_TXTD_PWR_COMP_SETS_2_U__PWR_COMP_20IN20_3___POR 0x89 +#define PHYA_TXTD_PWR_COMP_SETS_2_U__PWR_COMP_20IN20_2___POR 0x41 +#define PHYA_TXTD_PWR_COMP_SETS_2_U__PWR_COMP_20IN20_5___M 0xFF000000 +#define PHYA_TXTD_PWR_COMP_SETS_2_U__PWR_COMP_20IN20_5___S 24 +#define PHYA_TXTD_PWR_COMP_SETS_2_U__PWR_COMP_20IN20_4___M 0x00FF0000 +#define PHYA_TXTD_PWR_COMP_SETS_2_U__PWR_COMP_20IN20_4___S 16 +#define PHYA_TXTD_PWR_COMP_SETS_2_U__PWR_COMP_20IN20_3___M 0x0000FF00 +#define PHYA_TXTD_PWR_COMP_SETS_2_U__PWR_COMP_20IN20_3___S 8 +#define PHYA_TXTD_PWR_COMP_SETS_2_U__PWR_COMP_20IN20_2___M 0x000000FF +#define PHYA_TXTD_PWR_COMP_SETS_2_U__PWR_COMP_20IN20_2___S 0 +#define PHYA_TXTD_PWR_COMP_SETS_2_U___M 0xFFFFFFFF +#define PHYA_TXTD_PWR_COMP_SETS_2_U___S 0 + +#define PHYA_TXTD_PWR_COMP_SETS_3_L (0x003B5060) +#define PHYA_TXTD_PWR_COMP_SETS_3_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PWR_COMP_SETS_3_L___POR 0x874D6387 +#define PHYA_TXTD_PWR_COMP_SETS_3_L__PWR_COMP_20IN40_3___POR 0x87 +#define PHYA_TXTD_PWR_COMP_SETS_3_L__PWR_COMP_20IN40_2___POR 0x4D +#define PHYA_TXTD_PWR_COMP_SETS_3_L__PWR_COMP_20IN40_1___POR 0x63 +#define PHYA_TXTD_PWR_COMP_SETS_3_L__PWR_COMP_20IN40_0___POR 0x87 +#define PHYA_TXTD_PWR_COMP_SETS_3_L__PWR_COMP_20IN40_3___M 0xFF000000 +#define PHYA_TXTD_PWR_COMP_SETS_3_L__PWR_COMP_20IN40_3___S 24 +#define PHYA_TXTD_PWR_COMP_SETS_3_L__PWR_COMP_20IN40_2___M 0x00FF0000 +#define PHYA_TXTD_PWR_COMP_SETS_3_L__PWR_COMP_20IN40_2___S 16 +#define PHYA_TXTD_PWR_COMP_SETS_3_L__PWR_COMP_20IN40_1___M 0x0000FF00 +#define PHYA_TXTD_PWR_COMP_SETS_3_L__PWR_COMP_20IN40_1___S 8 +#define PHYA_TXTD_PWR_COMP_SETS_3_L__PWR_COMP_20IN40_0___M 0x000000FF +#define PHYA_TXTD_PWR_COMP_SETS_3_L__PWR_COMP_20IN40_0___S 0 +#define PHYA_TXTD_PWR_COMP_SETS_3_L___M 0xFFFFFFFF +#define PHYA_TXTD_PWR_COMP_SETS_3_L___S 0 + +#define PHYA_TXTD_PWR_COMP_SETS_3_U (0x003B5064) +#define PHYA_TXTD_PWR_COMP_SETS_3_U___RWC QCSR_REG_RW +#define PHYA_TXTD_PWR_COMP_SETS_3_U___POR 0x58875771 +#define PHYA_TXTD_PWR_COMP_SETS_3_U__PWR_COMP_20IN80_1___POR 0x58 +#define PHYA_TXTD_PWR_COMP_SETS_3_U__PWR_COMP_20IN80_0___POR 0x87 +#define PHYA_TXTD_PWR_COMP_SETS_3_U__PWR_COMP_20IN40_5___POR 0x57 +#define PHYA_TXTD_PWR_COMP_SETS_3_U__PWR_COMP_20IN40_4___POR 0x71 +#define PHYA_TXTD_PWR_COMP_SETS_3_U__PWR_COMP_20IN80_1___M 0xFF000000 +#define PHYA_TXTD_PWR_COMP_SETS_3_U__PWR_COMP_20IN80_1___S 24 +#define PHYA_TXTD_PWR_COMP_SETS_3_U__PWR_COMP_20IN80_0___M 0x00FF0000 +#define PHYA_TXTD_PWR_COMP_SETS_3_U__PWR_COMP_20IN80_0___S 16 +#define PHYA_TXTD_PWR_COMP_SETS_3_U__PWR_COMP_20IN40_5___M 0x0000FF00 +#define PHYA_TXTD_PWR_COMP_SETS_3_U__PWR_COMP_20IN40_5___S 8 +#define PHYA_TXTD_PWR_COMP_SETS_3_U__PWR_COMP_20IN40_4___M 0x000000FF +#define PHYA_TXTD_PWR_COMP_SETS_3_U__PWR_COMP_20IN40_4___S 0 +#define PHYA_TXTD_PWR_COMP_SETS_3_U___M 0xFFFFFFFF +#define PHYA_TXTD_PWR_COMP_SETS_3_U___S 0 + +#define PHYA_TXTD_PWR_COMP_SETS_4_L (0x003B5068) +#define PHYA_TXTD_PWR_COMP_SETS_4_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PWR_COMP_SETS_4_L___POR 0x4A638C41 +#define PHYA_TXTD_PWR_COMP_SETS_4_L__PWR_COMP_20IN80_5___POR 0x4A +#define PHYA_TXTD_PWR_COMP_SETS_4_L__PWR_COMP_20IN80_4___POR 0x63 +#define PHYA_TXTD_PWR_COMP_SETS_4_L__PWR_COMP_20IN80_3___POR 0x8C +#define PHYA_TXTD_PWR_COMP_SETS_4_L__PWR_COMP_20IN80_2___POR 0x41 +#define PHYA_TXTD_PWR_COMP_SETS_4_L__PWR_COMP_20IN80_5___M 0xFF000000 +#define PHYA_TXTD_PWR_COMP_SETS_4_L__PWR_COMP_20IN80_5___S 24 +#define PHYA_TXTD_PWR_COMP_SETS_4_L__PWR_COMP_20IN80_4___M 0x00FF0000 +#define PHYA_TXTD_PWR_COMP_SETS_4_L__PWR_COMP_20IN80_4___S 16 +#define PHYA_TXTD_PWR_COMP_SETS_4_L__PWR_COMP_20IN80_3___M 0x0000FF00 +#define PHYA_TXTD_PWR_COMP_SETS_4_L__PWR_COMP_20IN80_3___S 8 +#define PHYA_TXTD_PWR_COMP_SETS_4_L__PWR_COMP_20IN80_2___M 0x000000FF +#define PHYA_TXTD_PWR_COMP_SETS_4_L__PWR_COMP_20IN80_2___S 0 +#define PHYA_TXTD_PWR_COMP_SETS_4_L___M 0xFFFFFFFF +#define PHYA_TXTD_PWR_COMP_SETS_4_L___S 0 + +#define PHYA_TXTD_PWR_COMP_SETS_4_U (0x003B506C) +#define PHYA_TXTD_PWR_COMP_SETS_4_U___RWC QCSR_REG_RW +#define PHYA_TXTD_PWR_COMP_SETS_4_U___POR 0x8C415887 +#define PHYA_TXTD_PWR_COMP_SETS_4_U__PWR_COMP_20IN160_3___POR 0x8C +#define PHYA_TXTD_PWR_COMP_SETS_4_U__PWR_COMP_20IN160_2___POR 0x41 +#define PHYA_TXTD_PWR_COMP_SETS_4_U__PWR_COMP_20IN160_1___POR 0x58 +#define PHYA_TXTD_PWR_COMP_SETS_4_U__PWR_COMP_20IN160_0___POR 0x87 +#define PHYA_TXTD_PWR_COMP_SETS_4_U__PWR_COMP_20IN160_3___M 0xFF000000 +#define PHYA_TXTD_PWR_COMP_SETS_4_U__PWR_COMP_20IN160_3___S 24 +#define PHYA_TXTD_PWR_COMP_SETS_4_U__PWR_COMP_20IN160_2___M 0x00FF0000 +#define PHYA_TXTD_PWR_COMP_SETS_4_U__PWR_COMP_20IN160_2___S 16 +#define PHYA_TXTD_PWR_COMP_SETS_4_U__PWR_COMP_20IN160_1___M 0x0000FF00 +#define PHYA_TXTD_PWR_COMP_SETS_4_U__PWR_COMP_20IN160_1___S 8 +#define PHYA_TXTD_PWR_COMP_SETS_4_U__PWR_COMP_20IN160_0___M 0x000000FF +#define PHYA_TXTD_PWR_COMP_SETS_4_U__PWR_COMP_20IN160_0___S 0 +#define PHYA_TXTD_PWR_COMP_SETS_4_U___M 0xFFFFFFFF +#define PHYA_TXTD_PWR_COMP_SETS_4_U___S 0 + +#define PHYA_TXTD_PWR_COMP_SETS_5_L (0x003B5070) +#define PHYA_TXTD_PWR_COMP_SETS_5_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PWR_COMP_SETS_5_L___POR 0x559A4A63 +#define PHYA_TXTD_PWR_COMP_SETS_5_L__PWR_COMP_40IN40_1___POR 0x55 +#define PHYA_TXTD_PWR_COMP_SETS_5_L__PWR_COMP_40IN40_0___POR 0x9A +#define PHYA_TXTD_PWR_COMP_SETS_5_L__PWR_COMP_20IN160_5___POR 0x4A +#define PHYA_TXTD_PWR_COMP_SETS_5_L__PWR_COMP_20IN160_4___POR 0x63 +#define PHYA_TXTD_PWR_COMP_SETS_5_L__PWR_COMP_40IN40_1___M 0xFF000000 +#define PHYA_TXTD_PWR_COMP_SETS_5_L__PWR_COMP_40IN40_1___S 24 +#define PHYA_TXTD_PWR_COMP_SETS_5_L__PWR_COMP_40IN40_0___M 0x00FF0000 +#define PHYA_TXTD_PWR_COMP_SETS_5_L__PWR_COMP_40IN40_0___S 16 +#define PHYA_TXTD_PWR_COMP_SETS_5_L__PWR_COMP_20IN160_5___M 0x0000FF00 +#define PHYA_TXTD_PWR_COMP_SETS_5_L__PWR_COMP_20IN160_5___S 8 +#define PHYA_TXTD_PWR_COMP_SETS_5_L__PWR_COMP_20IN160_4___M 0x000000FF +#define PHYA_TXTD_PWR_COMP_SETS_5_L__PWR_COMP_20IN160_4___S 0 +#define PHYA_TXTD_PWR_COMP_SETS_5_L___M 0xFFFFFFFF +#define PHYA_TXTD_PWR_COMP_SETS_5_L___S 0 + +#define PHYA_TXTD_PWR_COMP_SETS_5_U (0x003B5074) +#define PHYA_TXTD_PWR_COMP_SETS_5_U___RWC QCSR_REG_RW +#define PHYA_TXTD_PWR_COMP_SETS_5_U___POR 0x495D9742 +#define PHYA_TXTD_PWR_COMP_SETS_5_U__PWR_COMP_40IN40_5___POR 0x49 +#define PHYA_TXTD_PWR_COMP_SETS_5_U__PWR_COMP_40IN40_4___POR 0x5D +#define PHYA_TXTD_PWR_COMP_SETS_5_U__PWR_COMP_40IN40_3___POR 0x97 +#define PHYA_TXTD_PWR_COMP_SETS_5_U__PWR_COMP_40IN40_2___POR 0x42 +#define PHYA_TXTD_PWR_COMP_SETS_5_U__PWR_COMP_40IN40_5___M 0xFF000000 +#define PHYA_TXTD_PWR_COMP_SETS_5_U__PWR_COMP_40IN40_5___S 24 +#define PHYA_TXTD_PWR_COMP_SETS_5_U__PWR_COMP_40IN40_4___M 0x00FF0000 +#define PHYA_TXTD_PWR_COMP_SETS_5_U__PWR_COMP_40IN40_4___S 16 +#define PHYA_TXTD_PWR_COMP_SETS_5_U__PWR_COMP_40IN40_3___M 0x0000FF00 +#define PHYA_TXTD_PWR_COMP_SETS_5_U__PWR_COMP_40IN40_3___S 8 +#define PHYA_TXTD_PWR_COMP_SETS_5_U__PWR_COMP_40IN40_2___M 0x000000FF +#define PHYA_TXTD_PWR_COMP_SETS_5_U__PWR_COMP_40IN40_2___S 0 +#define PHYA_TXTD_PWR_COMP_SETS_5_U___M 0xFFFFFFFF +#define PHYA_TXTD_PWR_COMP_SETS_5_U___S 0 + +#define PHYA_TXTD_PWR_COMP_SETS_6_L (0x003B5078) +#define PHYA_TXTD_PWR_COMP_SETS_6_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PWR_COMP_SETS_6_L___POR 0x9738469A +#define PHYA_TXTD_PWR_COMP_SETS_6_L__PWR_COMP_40IN80_3___POR 0x97 +#define PHYA_TXTD_PWR_COMP_SETS_6_L__PWR_COMP_40IN80_2___POR 0x38 +#define PHYA_TXTD_PWR_COMP_SETS_6_L__PWR_COMP_40IN80_1___POR 0x46 +#define PHYA_TXTD_PWR_COMP_SETS_6_L__PWR_COMP_40IN80_0___POR 0x9A +#define PHYA_TXTD_PWR_COMP_SETS_6_L__PWR_COMP_40IN80_3___M 0xFF000000 +#define PHYA_TXTD_PWR_COMP_SETS_6_L__PWR_COMP_40IN80_3___S 24 +#define PHYA_TXTD_PWR_COMP_SETS_6_L__PWR_COMP_40IN80_2___M 0x00FF0000 +#define PHYA_TXTD_PWR_COMP_SETS_6_L__PWR_COMP_40IN80_2___S 16 +#define PHYA_TXTD_PWR_COMP_SETS_6_L__PWR_COMP_40IN80_1___M 0x0000FF00 +#define PHYA_TXTD_PWR_COMP_SETS_6_L__PWR_COMP_40IN80_1___S 8 +#define PHYA_TXTD_PWR_COMP_SETS_6_L__PWR_COMP_40IN80_0___M 0x000000FF +#define PHYA_TXTD_PWR_COMP_SETS_6_L__PWR_COMP_40IN80_0___S 0 +#define PHYA_TXTD_PWR_COMP_SETS_6_L___M 0xFFFFFFFF +#define PHYA_TXTD_PWR_COMP_SETS_6_L___S 0 + +#define PHYA_TXTD_PWR_COMP_SETS_6_U (0x003B507C) +#define PHYA_TXTD_PWR_COMP_SETS_6_U___RWC QCSR_REG_RW +#define PHYA_TXTD_PWR_COMP_SETS_6_U___POR 0x469A3D4D +#define PHYA_TXTD_PWR_COMP_SETS_6_U__PWR_COMP_40IN160_1___POR 0x46 +#define PHYA_TXTD_PWR_COMP_SETS_6_U__PWR_COMP_40IN160_0___POR 0x9A +#define PHYA_TXTD_PWR_COMP_SETS_6_U__PWR_COMP_40IN80_5___POR 0x3D +#define PHYA_TXTD_PWR_COMP_SETS_6_U__PWR_COMP_40IN80_4___POR 0x4D +#define PHYA_TXTD_PWR_COMP_SETS_6_U__PWR_COMP_40IN160_1___M 0xFF000000 +#define PHYA_TXTD_PWR_COMP_SETS_6_U__PWR_COMP_40IN160_1___S 24 +#define PHYA_TXTD_PWR_COMP_SETS_6_U__PWR_COMP_40IN160_0___M 0x00FF0000 +#define PHYA_TXTD_PWR_COMP_SETS_6_U__PWR_COMP_40IN160_0___S 16 +#define PHYA_TXTD_PWR_COMP_SETS_6_U__PWR_COMP_40IN80_5___M 0x0000FF00 +#define PHYA_TXTD_PWR_COMP_SETS_6_U__PWR_COMP_40IN80_5___S 8 +#define PHYA_TXTD_PWR_COMP_SETS_6_U__PWR_COMP_40IN80_4___M 0x000000FF +#define PHYA_TXTD_PWR_COMP_SETS_6_U__PWR_COMP_40IN80_4___S 0 +#define PHYA_TXTD_PWR_COMP_SETS_6_U___M 0xFFFFFFFF +#define PHYA_TXTD_PWR_COMP_SETS_6_U___S 0 + +#define PHYA_TXTD_PWR_COMP_SETS_7_L (0x003B5080) +#define PHYA_TXTD_PWR_COMP_SETS_7_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PWR_COMP_SETS_7_L___POR 0x3D4D9738 +#define PHYA_TXTD_PWR_COMP_SETS_7_L__PWR_COMP_40IN160_5___POR 0x3D +#define PHYA_TXTD_PWR_COMP_SETS_7_L__PWR_COMP_40IN160_4___POR 0x4D +#define PHYA_TXTD_PWR_COMP_SETS_7_L__PWR_COMP_40IN160_3___POR 0x97 +#define PHYA_TXTD_PWR_COMP_SETS_7_L__PWR_COMP_40IN160_2___POR 0x38 +#define PHYA_TXTD_PWR_COMP_SETS_7_L__PWR_COMP_40IN160_5___M 0xFF000000 +#define PHYA_TXTD_PWR_COMP_SETS_7_L__PWR_COMP_40IN160_5___S 24 +#define PHYA_TXTD_PWR_COMP_SETS_7_L__PWR_COMP_40IN160_4___M 0x00FF0000 +#define PHYA_TXTD_PWR_COMP_SETS_7_L__PWR_COMP_40IN160_4___S 16 +#define PHYA_TXTD_PWR_COMP_SETS_7_L__PWR_COMP_40IN160_3___M 0x0000FF00 +#define PHYA_TXTD_PWR_COMP_SETS_7_L__PWR_COMP_40IN160_3___S 8 +#define PHYA_TXTD_PWR_COMP_SETS_7_L__PWR_COMP_40IN160_2___M 0x000000FF +#define PHYA_TXTD_PWR_COMP_SETS_7_L__PWR_COMP_40IN160_2___S 0 +#define PHYA_TXTD_PWR_COMP_SETS_7_L___M 0xFFFFFFFF +#define PHYA_TXTD_PWR_COMP_SETS_7_L___S 0 + +#define PHYA_TXTD_PWR_COMP_SETS_7_U (0x003B5084) +#define PHYA_TXTD_PWR_COMP_SETS_7_U___RWC QCSR_REG_RW +#define PHYA_TXTD_PWR_COMP_SETS_7_U___POR 0x883C4C7B +#define PHYA_TXTD_PWR_COMP_SETS_7_U__PWR_COMP_80IN80_3___POR 0x88 +#define PHYA_TXTD_PWR_COMP_SETS_7_U__PWR_COMP_80IN80_2___POR 0x3C +#define PHYA_TXTD_PWR_COMP_SETS_7_U__PWR_COMP_80IN80_1___POR 0x4C +#define PHYA_TXTD_PWR_COMP_SETS_7_U__PWR_COMP_80IN80_0___POR 0x7B +#define PHYA_TXTD_PWR_COMP_SETS_7_U__PWR_COMP_80IN80_3___M 0xFF000000 +#define PHYA_TXTD_PWR_COMP_SETS_7_U__PWR_COMP_80IN80_3___S 24 +#define PHYA_TXTD_PWR_COMP_SETS_7_U__PWR_COMP_80IN80_2___M 0x00FF0000 +#define PHYA_TXTD_PWR_COMP_SETS_7_U__PWR_COMP_80IN80_2___S 16 +#define PHYA_TXTD_PWR_COMP_SETS_7_U__PWR_COMP_80IN80_1___M 0x0000FF00 +#define PHYA_TXTD_PWR_COMP_SETS_7_U__PWR_COMP_80IN80_1___S 8 +#define PHYA_TXTD_PWR_COMP_SETS_7_U__PWR_COMP_80IN80_0___M 0x000000FF +#define PHYA_TXTD_PWR_COMP_SETS_7_U__PWR_COMP_80IN80_0___S 0 +#define PHYA_TXTD_PWR_COMP_SETS_7_U___M 0xFFFFFFFF +#define PHYA_TXTD_PWR_COMP_SETS_7_U___S 0 + +#define PHYA_TXTD_PWR_COMP_SETS_8_L (0x003B5088) +#define PHYA_TXTD_PWR_COMP_SETS_8_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PWR_COMP_SETS_8_L___POR 0x4C9A4152 +#define PHYA_TXTD_PWR_COMP_SETS_8_L__PWR_COMP_80IN160_1___POR 0x4C +#define PHYA_TXTD_PWR_COMP_SETS_8_L__PWR_COMP_80IN160_0___POR 0x9A +#define PHYA_TXTD_PWR_COMP_SETS_8_L__PWR_COMP_80IN80_5___POR 0x41 +#define PHYA_TXTD_PWR_COMP_SETS_8_L__PWR_COMP_80IN80_4___POR 0x52 +#define PHYA_TXTD_PWR_COMP_SETS_8_L__PWR_COMP_80IN160_1___M 0xFF000000 +#define PHYA_TXTD_PWR_COMP_SETS_8_L__PWR_COMP_80IN160_1___S 24 +#define PHYA_TXTD_PWR_COMP_SETS_8_L__PWR_COMP_80IN160_0___M 0x00FF0000 +#define PHYA_TXTD_PWR_COMP_SETS_8_L__PWR_COMP_80IN160_0___S 16 +#define PHYA_TXTD_PWR_COMP_SETS_8_L__PWR_COMP_80IN80_5___M 0x0000FF00 +#define PHYA_TXTD_PWR_COMP_SETS_8_L__PWR_COMP_80IN80_5___S 8 +#define PHYA_TXTD_PWR_COMP_SETS_8_L__PWR_COMP_80IN80_4___M 0x000000FF +#define PHYA_TXTD_PWR_COMP_SETS_8_L__PWR_COMP_80IN80_4___S 0 +#define PHYA_TXTD_PWR_COMP_SETS_8_L___M 0xFFFFFFFF +#define PHYA_TXTD_PWR_COMP_SETS_8_L___S 0 + +#define PHYA_TXTD_PWR_COMP_SETS_8_U (0x003B508C) +#define PHYA_TXTD_PWR_COMP_SETS_8_U___RWC QCSR_REG_RW +#define PHYA_TXTD_PWR_COMP_SETS_8_U___POR 0x4152AD3C +#define PHYA_TXTD_PWR_COMP_SETS_8_U__PWR_COMP_80IN160_5___POR 0x41 +#define PHYA_TXTD_PWR_COMP_SETS_8_U__PWR_COMP_80IN160_4___POR 0x52 +#define PHYA_TXTD_PWR_COMP_SETS_8_U__PWR_COMP_80IN160_3___POR 0xAD +#define PHYA_TXTD_PWR_COMP_SETS_8_U__PWR_COMP_80IN160_2___POR 0x3C +#define PHYA_TXTD_PWR_COMP_SETS_8_U__PWR_COMP_80IN160_5___M 0xFF000000 +#define PHYA_TXTD_PWR_COMP_SETS_8_U__PWR_COMP_80IN160_5___S 24 +#define PHYA_TXTD_PWR_COMP_SETS_8_U__PWR_COMP_80IN160_4___M 0x00FF0000 +#define PHYA_TXTD_PWR_COMP_SETS_8_U__PWR_COMP_80IN160_4___S 16 +#define PHYA_TXTD_PWR_COMP_SETS_8_U__PWR_COMP_80IN160_3___M 0x0000FF00 +#define PHYA_TXTD_PWR_COMP_SETS_8_U__PWR_COMP_80IN160_3___S 8 +#define PHYA_TXTD_PWR_COMP_SETS_8_U__PWR_COMP_80IN160_2___M 0x000000FF +#define PHYA_TXTD_PWR_COMP_SETS_8_U__PWR_COMP_80IN160_2___S 0 +#define PHYA_TXTD_PWR_COMP_SETS_8_U___M 0xFFFFFFFF +#define PHYA_TXTD_PWR_COMP_SETS_8_U___S 0 + +#define PHYA_TXTD_PWR_COMP_SETS_9_L (0x003B5090) +#define PHYA_TXTD_PWR_COMP_SETS_9_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PWR_COMP_SETS_9_L___POR 0x8F41538F +#define PHYA_TXTD_PWR_COMP_SETS_9_L__PWR_COMP_160IN160_3___POR 0x8F +#define PHYA_TXTD_PWR_COMP_SETS_9_L__PWR_COMP_160IN160_2___POR 0x41 +#define PHYA_TXTD_PWR_COMP_SETS_9_L__PWR_COMP_160IN160_1___POR 0x53 +#define PHYA_TXTD_PWR_COMP_SETS_9_L__PWR_COMP_160IN160_0___POR 0x8F +#define PHYA_TXTD_PWR_COMP_SETS_9_L__PWR_COMP_160IN160_3___M 0xFF000000 +#define PHYA_TXTD_PWR_COMP_SETS_9_L__PWR_COMP_160IN160_3___S 24 +#define PHYA_TXTD_PWR_COMP_SETS_9_L__PWR_COMP_160IN160_2___M 0x00FF0000 +#define PHYA_TXTD_PWR_COMP_SETS_9_L__PWR_COMP_160IN160_2___S 16 +#define PHYA_TXTD_PWR_COMP_SETS_9_L__PWR_COMP_160IN160_1___M 0x0000FF00 +#define PHYA_TXTD_PWR_COMP_SETS_9_L__PWR_COMP_160IN160_1___S 8 +#define PHYA_TXTD_PWR_COMP_SETS_9_L__PWR_COMP_160IN160_0___M 0x000000FF +#define PHYA_TXTD_PWR_COMP_SETS_9_L__PWR_COMP_160IN160_0___S 0 +#define PHYA_TXTD_PWR_COMP_SETS_9_L___M 0xFFFFFFFF +#define PHYA_TXTD_PWR_COMP_SETS_9_L___S 0 + +#define PHYA_TXTD_PWR_COMP_SETS_9_U (0x003B5094) +#define PHYA_TXTD_PWR_COMP_SETS_9_U___RWC QCSR_REG_RW +#define PHYA_TXTD_PWR_COMP_SETS_9_U___POR 0x538F5F6C +#define PHYA_TXTD_PWR_COMP_SETS_9_U__PWR_COMP_160IN160_7___POR 0x53 +#define PHYA_TXTD_PWR_COMP_SETS_9_U__PWR_COMP_160IN160_6___POR 0x8F +#define PHYA_TXTD_PWR_COMP_SETS_9_U__PWR_COMP_160IN160_5___POR 0x5F +#define PHYA_TXTD_PWR_COMP_SETS_9_U__PWR_COMP_160IN160_4___POR 0x6C +#define PHYA_TXTD_PWR_COMP_SETS_9_U__PWR_COMP_160IN160_7___M 0xFF000000 +#define PHYA_TXTD_PWR_COMP_SETS_9_U__PWR_COMP_160IN160_7___S 24 +#define PHYA_TXTD_PWR_COMP_SETS_9_U__PWR_COMP_160IN160_6___M 0x00FF0000 +#define PHYA_TXTD_PWR_COMP_SETS_9_U__PWR_COMP_160IN160_6___S 16 +#define PHYA_TXTD_PWR_COMP_SETS_9_U__PWR_COMP_160IN160_5___M 0x0000FF00 +#define PHYA_TXTD_PWR_COMP_SETS_9_U__PWR_COMP_160IN160_5___S 8 +#define PHYA_TXTD_PWR_COMP_SETS_9_U__PWR_COMP_160IN160_4___M 0x000000FF +#define PHYA_TXTD_PWR_COMP_SETS_9_U__PWR_COMP_160IN160_4___S 0 +#define PHYA_TXTD_PWR_COMP_SETS_9_U___M 0xFFFFFFFF +#define PHYA_TXTD_PWR_COMP_SETS_9_U___S 0 + +#define PHYA_TXTD_PWR_COMP_SETS_10_L (0x003B5098) +#define PHYA_TXTD_PWR_COMP_SETS_10_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PWR_COMP_SETS_10_L___POR 0x5F6C8F41 +#define PHYA_TXTD_PWR_COMP_SETS_10_L__PWR_COMP_160IN160_11___POR 0x5F +#define PHYA_TXTD_PWR_COMP_SETS_10_L__PWR_COMP_160IN160_10___POR 0x6C +#define PHYA_TXTD_PWR_COMP_SETS_10_L__PWR_COMP_160IN160_9___POR 0x8F +#define PHYA_TXTD_PWR_COMP_SETS_10_L__PWR_COMP_160IN160_8___POR 0x41 +#define PHYA_TXTD_PWR_COMP_SETS_10_L__PWR_COMP_160IN160_11___M 0xFF000000 +#define PHYA_TXTD_PWR_COMP_SETS_10_L__PWR_COMP_160IN160_11___S 24 +#define PHYA_TXTD_PWR_COMP_SETS_10_L__PWR_COMP_160IN160_10___M 0x00FF0000 +#define PHYA_TXTD_PWR_COMP_SETS_10_L__PWR_COMP_160IN160_10___S 16 +#define PHYA_TXTD_PWR_COMP_SETS_10_L__PWR_COMP_160IN160_9___M 0x0000FF00 +#define PHYA_TXTD_PWR_COMP_SETS_10_L__PWR_COMP_160IN160_9___S 8 +#define PHYA_TXTD_PWR_COMP_SETS_10_L__PWR_COMP_160IN160_8___M 0x000000FF +#define PHYA_TXTD_PWR_COMP_SETS_10_L__PWR_COMP_160IN160_8___S 0 +#define PHYA_TXTD_PWR_COMP_SETS_10_L___M 0xFFFFFFFF +#define PHYA_TXTD_PWR_COMP_SETS_10_L___S 0 + +#define PHYA_TXTD_PWR_COMP_SETS_10_U (0x003B509C) +#define PHYA_TXTD_PWR_COMP_SETS_10_U___RWC QCSR_REG_RW +#define PHYA_TXTD_PWR_COMP_SETS_10_U___POR 0x8B3D4C86 +#define PHYA_TXTD_PWR_COMP_SETS_10_U__PWR_COMP_80P80_03___POR 0x8B +#define PHYA_TXTD_PWR_COMP_SETS_10_U__PWR_COMP_80P80_02___POR 0x3D +#define PHYA_TXTD_PWR_COMP_SETS_10_U__PWR_COMP_80P80_01___POR 0x4C +#define PHYA_TXTD_PWR_COMP_SETS_10_U__PWR_COMP_80P80_00___POR 0x86 +#define PHYA_TXTD_PWR_COMP_SETS_10_U__PWR_COMP_80P80_03___M 0xFF000000 +#define PHYA_TXTD_PWR_COMP_SETS_10_U__PWR_COMP_80P80_03___S 24 +#define PHYA_TXTD_PWR_COMP_SETS_10_U__PWR_COMP_80P80_02___M 0x00FF0000 +#define PHYA_TXTD_PWR_COMP_SETS_10_U__PWR_COMP_80P80_02___S 16 +#define PHYA_TXTD_PWR_COMP_SETS_10_U__PWR_COMP_80P80_01___M 0x0000FF00 +#define PHYA_TXTD_PWR_COMP_SETS_10_U__PWR_COMP_80P80_01___S 8 +#define PHYA_TXTD_PWR_COMP_SETS_10_U__PWR_COMP_80P80_00___M 0x000000FF +#define PHYA_TXTD_PWR_COMP_SETS_10_U__PWR_COMP_80P80_00___S 0 +#define PHYA_TXTD_PWR_COMP_SETS_10_U___M 0xFFFFFFFF +#define PHYA_TXTD_PWR_COMP_SETS_10_U___S 0 + +#define PHYA_TXTD_PWR_COMP_SETS_11_L (0x003B50A0) +#define PHYA_TXTD_PWR_COMP_SETS_11_L___RWC QCSR_REG_RW +#define PHYA_TXTD_PWR_COMP_SETS_11_L___POR 0x00004153 +#define PHYA_TXTD_PWR_COMP_SETS_11_L__PWR_COMP_80P80_05___POR 0x41 +#define PHYA_TXTD_PWR_COMP_SETS_11_L__PWR_COMP_80P80_04___POR 0x53 +#define PHYA_TXTD_PWR_COMP_SETS_11_L__PWR_COMP_80P80_05___M 0x0000FF00 +#define PHYA_TXTD_PWR_COMP_SETS_11_L__PWR_COMP_80P80_05___S 8 +#define PHYA_TXTD_PWR_COMP_SETS_11_L__PWR_COMP_80P80_04___M 0x000000FF +#define PHYA_TXTD_PWR_COMP_SETS_11_L__PWR_COMP_80P80_04___S 0 +#define PHYA_TXTD_PWR_COMP_SETS_11_L___M 0x0000FFFF +#define PHYA_TXTD_PWR_COMP_SETS_11_L___S 0 + +#define PHYA_TXTD_DUMMY_L (0x003B7FF8) +#define PHYA_TXTD_DUMMY_L___RWC QCSR_REG_RW +#define PHYA_TXTD_DUMMY_L___POR 0x00000000 +#define PHYA_TXTD_DUMMY_L__DUMMY___POR 0x0 +#define PHYA_TXTD_DUMMY_L__DUMMY___M 0x00000001 +#define PHYA_TXTD_DUMMY_L__DUMMY___S 0 +#define PHYA_TXTD_DUMMY_L___M 0x00000001 +#define PHYA_TXTD_DUMMY_L___S 0 + +#define PHYA_TXBF_ECO_CONTROL_L (0x003C0000) +#define PHYA_TXBF_ECO_CONTROL_L___RWC QCSR_REG_RW +#define PHYA_TXBF_ECO_CONTROL_L___POR 0x00000000 +#define PHYA_TXBF_ECO_CONTROL_L__ECO_CTRL___POR 0x00000000 +#define PHYA_TXBF_ECO_CONTROL_L__ECO_CTRL___M 0xFFFFFFFF +#define PHYA_TXBF_ECO_CONTROL_L__ECO_CTRL___S 0 +#define PHYA_TXBF_ECO_CONTROL_L___M 0xFFFFFFFF +#define PHYA_TXBF_ECO_CONTROL_L___S 0 + +#define PHYA_TXBF_ECO_CONTROL_U (0x003C0004) +#define PHYA_TXBF_ECO_CONTROL_U___RWC QCSR_REG_RW +#define PHYA_TXBF_ECO_CONTROL_U___POR 0x00000000 +#define PHYA_TXBF_ECO_CONTROL_U__ECO_CFG___POR 0x00000000 +#define PHYA_TXBF_ECO_CONTROL_U__ECO_CFG___M 0xFFFFFFFF +#define PHYA_TXBF_ECO_CONTROL_U__ECO_CFG___S 0 +#define PHYA_TXBF_ECO_CONTROL_U___M 0xFFFFFFFF +#define PHYA_TXBF_ECO_CONTROL_U___S 0 + +#define PHYA_TXBF_ECO_STATUS_L (0x003C0008) +#define PHYA_TXBF_ECO_STATUS_L___RWC QCSR_REG_RO +#define PHYA_TXBF_ECO_STATUS_L___POR 0x00000000 +#define PHYA_TXBF_ECO_STATUS_L__ECO_STAT___POR 0x00000000 +#define PHYA_TXBF_ECO_STATUS_L__ECO_STAT___M 0xFFFFFFFF +#define PHYA_TXBF_ECO_STATUS_L__ECO_STAT___S 0 +#define PHYA_TXBF_ECO_STATUS_L___M 0xFFFFFFFF +#define PHYA_TXBF_ECO_STATUS_L___S 0 + +#define PHYA_TXBF_CONFIG_CONFIG_L (0x003C0010) +#define PHYA_TXBF_CONFIG_CONFIG_L___RWC QCSR_REG_RW +#define PHYA_TXBF_CONFIG_CONFIG_L___POR 0x00000000 +#define PHYA_TXBF_CONFIG_CONFIG_L__AXI_TIMEOUT_ENABLE___POR 0x0 +#define PHYA_TXBF_CONFIG_CONFIG_L__AXI_TIMEOUT_ENABLE___M 0x00000001 +#define PHYA_TXBF_CONFIG_CONFIG_L__AXI_TIMEOUT_ENABLE___S 0 +#define PHYA_TXBF_CONFIG_CONFIG_L___M 0x00000001 +#define PHYA_TXBF_CONFIG_CONFIG_L___S 0 + +#define PHYA_TXBF_ERROR_CODE_L (0x003C0018) +#define PHYA_TXBF_ERROR_CODE_L___RWC QCSR_REG_RO +#define PHYA_TXBF_ERROR_CODE_L___POR 0x00000000 +#define PHYA_TXBF_ERROR_CODE_L__ERROR_CODE___POR 0x00000000 +#define PHYA_TXBF_ERROR_CODE_L__ERROR_CODE___M 0xFFFFFFFF +#define PHYA_TXBF_ERROR_CODE_L__ERROR_CODE___S 0 +#define PHYA_TXBF_ERROR_CODE_L___M 0xFFFFFFFF +#define PHYA_TXBF_ERROR_CODE_L___S 0 + +#define PHYA_TXBF_ERROR_STATUS_L (0x003C0020) +#define PHYA_TXBF_ERROR_STATUS_L___RWC QCSR_REG_RO +#define PHYA_TXBF_ERROR_STATUS_L___POR 0x00000000 +#define PHYA_TXBF_ERROR_STATUS_L__BF_PARAMS_PER_USER_LESS_TLVS_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_L__TXBFP_QRE_TONE_UNDERRUN_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_L__CVCTRL_STATE_TIMEOUT_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_L__PRECODING_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_L__PREFETCH_FIFO_UNDERFLOW_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_L__PREFETCH_FIFO_OVERFLOW_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_L__MORE_PREFETCH_TLVS_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_L__LESS_PREFETCH_TLVS_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_L__TXBF_AXI_SLAVE_TIMEOUT_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_L__PRECODING_FIFO_UNDERFLOW_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_L__PRECODING_FIFO_OVERFLOW_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_L__TONE_MAP_LUT_RD_CONFLICT_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_L__PRECODING_START_BEFORE_BF_PARAMS_CLEAR_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_L__QRE_RX_STOMP_TXBF_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_L__QRE_TXBF_STOMP_RX_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_L__QRE_INTERFACE_TIMEOUT_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_L__WT_MEM_RD_CONFLICT_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_L__WT_MEM_WR_CONFLICT_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_L__UNSAVED_CV_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_L__B2B_CBF_DONE_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_L__B2B_CBF_START_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_L__DMA1_HANG_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_L__DMA0_HANG_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_L__CBF_BUFFER_OVERFLOW___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_L__MIMO_CTRL_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_L__CBF_START_MISING_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_L__MPI_CBF_VALID_TIMEOUT_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_L__CBF_DONE_NOT_RECEIVED_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_L__MORE_CBF_DATA_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_L__LESS_CBF_DATA_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_L__OUT_OF_RANGE_CBF_USER_ID_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_L__CBF_START_BEFORE_EXPECT_CBF_CLEAR_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_L__BF_PARAMS_PER_USER_LESS_TLVS_ERROR___M 0x80000000 +#define PHYA_TXBF_ERROR_STATUS_L__BF_PARAMS_PER_USER_LESS_TLVS_ERROR___S 31 +#define PHYA_TXBF_ERROR_STATUS_L__TXBFP_QRE_TONE_UNDERRUN_ERROR___M 0x40000000 +#define PHYA_TXBF_ERROR_STATUS_L__TXBFP_QRE_TONE_UNDERRUN_ERROR___S 30 +#define PHYA_TXBF_ERROR_STATUS_L__CVCTRL_STATE_TIMEOUT_ERROR___M 0x20000000 +#define PHYA_TXBF_ERROR_STATUS_L__CVCTRL_STATE_TIMEOUT_ERROR___S 29 +#define PHYA_TXBF_ERROR_STATUS_L__PRECODING_ERROR___M 0x10000000 +#define PHYA_TXBF_ERROR_STATUS_L__PRECODING_ERROR___S 28 +#define PHYA_TXBF_ERROR_STATUS_L__PREFETCH_FIFO_UNDERFLOW_ERROR___M 0x08000000 +#define PHYA_TXBF_ERROR_STATUS_L__PREFETCH_FIFO_UNDERFLOW_ERROR___S 27 +#define PHYA_TXBF_ERROR_STATUS_L__PREFETCH_FIFO_OVERFLOW_ERROR___M 0x04000000 +#define PHYA_TXBF_ERROR_STATUS_L__PREFETCH_FIFO_OVERFLOW_ERROR___S 26 +#define PHYA_TXBF_ERROR_STATUS_L__MORE_PREFETCH_TLVS_ERROR___M 0x02000000 +#define PHYA_TXBF_ERROR_STATUS_L__MORE_PREFETCH_TLVS_ERROR___S 25 +#define PHYA_TXBF_ERROR_STATUS_L__LESS_PREFETCH_TLVS_ERROR___M 0x01000000 +#define PHYA_TXBF_ERROR_STATUS_L__LESS_PREFETCH_TLVS_ERROR___S 24 +#define PHYA_TXBF_ERROR_STATUS_L__TXBF_AXI_SLAVE_TIMEOUT_ERROR___M 0x00800000 +#define PHYA_TXBF_ERROR_STATUS_L__TXBF_AXI_SLAVE_TIMEOUT_ERROR___S 23 +#define PHYA_TXBF_ERROR_STATUS_L__PRECODING_FIFO_UNDERFLOW_ERROR___M 0x00400000 +#define PHYA_TXBF_ERROR_STATUS_L__PRECODING_FIFO_UNDERFLOW_ERROR___S 22 +#define PHYA_TXBF_ERROR_STATUS_L__PRECODING_FIFO_OVERFLOW_ERROR___M 0x00200000 +#define PHYA_TXBF_ERROR_STATUS_L__PRECODING_FIFO_OVERFLOW_ERROR___S 21 +#define PHYA_TXBF_ERROR_STATUS_L__TONE_MAP_LUT_RD_CONFLICT_ERROR___M 0x00100000 +#define PHYA_TXBF_ERROR_STATUS_L__TONE_MAP_LUT_RD_CONFLICT_ERROR___S 20 +#define PHYA_TXBF_ERROR_STATUS_L__PRECODING_START_BEFORE_BF_PARAMS_CLEAR_ERROR___M 0x00080000 +#define PHYA_TXBF_ERROR_STATUS_L__PRECODING_START_BEFORE_BF_PARAMS_CLEAR_ERROR___S 19 +#define PHYA_TXBF_ERROR_STATUS_L__QRE_RX_STOMP_TXBF_ERROR___M 0x00040000 +#define PHYA_TXBF_ERROR_STATUS_L__QRE_RX_STOMP_TXBF_ERROR___S 18 +#define PHYA_TXBF_ERROR_STATUS_L__QRE_TXBF_STOMP_RX_ERROR___M 0x00020000 +#define PHYA_TXBF_ERROR_STATUS_L__QRE_TXBF_STOMP_RX_ERROR___S 17 +#define PHYA_TXBF_ERROR_STATUS_L__QRE_INTERFACE_TIMEOUT_ERROR___M 0x00010000 +#define PHYA_TXBF_ERROR_STATUS_L__QRE_INTERFACE_TIMEOUT_ERROR___S 16 +#define PHYA_TXBF_ERROR_STATUS_L__WT_MEM_RD_CONFLICT_ERROR___M 0x00008000 +#define PHYA_TXBF_ERROR_STATUS_L__WT_MEM_RD_CONFLICT_ERROR___S 15 +#define PHYA_TXBF_ERROR_STATUS_L__WT_MEM_WR_CONFLICT_ERROR___M 0x00004000 +#define PHYA_TXBF_ERROR_STATUS_L__WT_MEM_WR_CONFLICT_ERROR___S 14 +#define PHYA_TXBF_ERROR_STATUS_L__UNSAVED_CV_ERROR___M 0x00002000 +#define PHYA_TXBF_ERROR_STATUS_L__UNSAVED_CV_ERROR___S 13 +#define PHYA_TXBF_ERROR_STATUS_L__B2B_CBF_DONE_ERROR___M 0x00001000 +#define PHYA_TXBF_ERROR_STATUS_L__B2B_CBF_DONE_ERROR___S 12 +#define PHYA_TXBF_ERROR_STATUS_L__B2B_CBF_START_ERROR___M 0x00000800 +#define PHYA_TXBF_ERROR_STATUS_L__B2B_CBF_START_ERROR___S 11 +#define PHYA_TXBF_ERROR_STATUS_L__DMA1_HANG_ERROR___M 0x00000400 +#define PHYA_TXBF_ERROR_STATUS_L__DMA1_HANG_ERROR___S 10 +#define PHYA_TXBF_ERROR_STATUS_L__DMA0_HANG_ERROR___M 0x00000200 +#define PHYA_TXBF_ERROR_STATUS_L__DMA0_HANG_ERROR___S 9 +#define PHYA_TXBF_ERROR_STATUS_L__CBF_BUFFER_OVERFLOW___M 0x00000100 +#define PHYA_TXBF_ERROR_STATUS_L__CBF_BUFFER_OVERFLOW___S 8 +#define PHYA_TXBF_ERROR_STATUS_L__MIMO_CTRL_ERROR___M 0x00000080 +#define PHYA_TXBF_ERROR_STATUS_L__MIMO_CTRL_ERROR___S 7 +#define PHYA_TXBF_ERROR_STATUS_L__CBF_START_MISING_ERROR___M 0x00000040 +#define PHYA_TXBF_ERROR_STATUS_L__CBF_START_MISING_ERROR___S 6 +#define PHYA_TXBF_ERROR_STATUS_L__MPI_CBF_VALID_TIMEOUT_ERROR___M 0x00000020 +#define PHYA_TXBF_ERROR_STATUS_L__MPI_CBF_VALID_TIMEOUT_ERROR___S 5 +#define PHYA_TXBF_ERROR_STATUS_L__CBF_DONE_NOT_RECEIVED_ERROR___M 0x00000010 +#define PHYA_TXBF_ERROR_STATUS_L__CBF_DONE_NOT_RECEIVED_ERROR___S 4 +#define PHYA_TXBF_ERROR_STATUS_L__MORE_CBF_DATA_ERROR___M 0x00000008 +#define PHYA_TXBF_ERROR_STATUS_L__MORE_CBF_DATA_ERROR___S 3 +#define PHYA_TXBF_ERROR_STATUS_L__LESS_CBF_DATA_ERROR___M 0x00000004 +#define PHYA_TXBF_ERROR_STATUS_L__LESS_CBF_DATA_ERROR___S 2 +#define PHYA_TXBF_ERROR_STATUS_L__OUT_OF_RANGE_CBF_USER_ID_ERROR___M 0x00000002 +#define PHYA_TXBF_ERROR_STATUS_L__OUT_OF_RANGE_CBF_USER_ID_ERROR___S 1 +#define PHYA_TXBF_ERROR_STATUS_L__CBF_START_BEFORE_EXPECT_CBF_CLEAR_ERROR___M 0x00000001 +#define PHYA_TXBF_ERROR_STATUS_L__CBF_START_BEFORE_EXPECT_CBF_CLEAR_ERROR___S 0 +#define PHYA_TXBF_ERROR_STATUS_L___M 0xFFFFFFFF +#define PHYA_TXBF_ERROR_STATUS_L___S 0 + +#define PHYA_TXBF_ERROR_STATUS_U (0x003C0024) +#define PHYA_TXBF_ERROR_STATUS_U___RWC QCSR_REG_RO +#define PHYA_TXBF_ERROR_STATUS_U___POR 0x00000000 +#define PHYA_TXBF_ERROR_STATUS_U__EXPECT_CBF_BUF_TIMEOUT_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_U__BF_PARAMS_PER_USER_BEFORE_COMMON_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_U__PREFETCH_PER_USER_BEFORE_COMMON_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_U__EXPECT_CBF_PER_USER_BEFORE_COMMON_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_U__PRECODING_STG1_STG2_WAIT_TIMEOUT_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_U__EXPECT_CBF_PER_USER_MORE_TLVS_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_U__EXPECT_CBF_PER_USER_LESS_TLVS_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_U__BF_PARAMS_COMMON_UNEXPECTED_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_U__BF_PARAMS_PER_USER_MORE_TLVS_ERROR___POR 0x0 +#define PHYA_TXBF_ERROR_STATUS_U__EXPECT_CBF_BUF_TIMEOUT_ERROR___M 0x00000100 +#define PHYA_TXBF_ERROR_STATUS_U__EXPECT_CBF_BUF_TIMEOUT_ERROR___S 8 +#define PHYA_TXBF_ERROR_STATUS_U__BF_PARAMS_PER_USER_BEFORE_COMMON_ERROR___M 0x00000080 +#define PHYA_TXBF_ERROR_STATUS_U__BF_PARAMS_PER_USER_BEFORE_COMMON_ERROR___S 7 +#define PHYA_TXBF_ERROR_STATUS_U__PREFETCH_PER_USER_BEFORE_COMMON_ERROR___M 0x00000040 +#define PHYA_TXBF_ERROR_STATUS_U__PREFETCH_PER_USER_BEFORE_COMMON_ERROR___S 6 +#define PHYA_TXBF_ERROR_STATUS_U__EXPECT_CBF_PER_USER_BEFORE_COMMON_ERROR___M 0x00000020 +#define PHYA_TXBF_ERROR_STATUS_U__EXPECT_CBF_PER_USER_BEFORE_COMMON_ERROR___S 5 +#define PHYA_TXBF_ERROR_STATUS_U__PRECODING_STG1_STG2_WAIT_TIMEOUT_ERROR___M 0x00000010 +#define PHYA_TXBF_ERROR_STATUS_U__PRECODING_STG1_STG2_WAIT_TIMEOUT_ERROR___S 4 +#define PHYA_TXBF_ERROR_STATUS_U__EXPECT_CBF_PER_USER_MORE_TLVS_ERROR___M 0x00000008 +#define PHYA_TXBF_ERROR_STATUS_U__EXPECT_CBF_PER_USER_MORE_TLVS_ERROR___S 3 +#define PHYA_TXBF_ERROR_STATUS_U__EXPECT_CBF_PER_USER_LESS_TLVS_ERROR___M 0x00000004 +#define PHYA_TXBF_ERROR_STATUS_U__EXPECT_CBF_PER_USER_LESS_TLVS_ERROR___S 2 +#define PHYA_TXBF_ERROR_STATUS_U__BF_PARAMS_COMMON_UNEXPECTED_ERROR___M 0x00000002 +#define PHYA_TXBF_ERROR_STATUS_U__BF_PARAMS_COMMON_UNEXPECTED_ERROR___S 1 +#define PHYA_TXBF_ERROR_STATUS_U__BF_PARAMS_PER_USER_MORE_TLVS_ERROR___M 0x00000001 +#define PHYA_TXBF_ERROR_STATUS_U__BF_PARAMS_PER_USER_MORE_TLVS_ERROR___S 0 +#define PHYA_TXBF_ERROR_STATUS_U___M 0x000001FF +#define PHYA_TXBF_ERROR_STATUS_U___S 0 + +#define PHYA_TXBF_ERROR_MASK_L (0x003C0028) +#define PHYA_TXBF_ERROR_MASK_L___RWC QCSR_REG_RW +#define PHYA_TXBF_ERROR_MASK_L___POR 0xFFFFFFFF +#define PHYA_TXBF_ERROR_MASK_L__BF_PARAMS_PER_USER_LESS_TLVS_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_L__TXBFP_QRE_TONE_UNDERRUN_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_L__CVCTRL_STATE_TIMEOUT_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_L__PRECODING_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_L__PREFETCH_FIFO_UNDERFLOW_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_L__PREFETCH_FIFO_OVERFLOW_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_L__MORE_PREFETCH_TLVS_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_L__LESS_PREFETCH_TLVS_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_L__TXBF_AXI_SLAVE_TIMEOUT_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_L__PRECODING_FIFO_UNDERFLOW_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_L__PRECODING_FIFO_OVERFLOW_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_L__TONE_MAP_LUT_RD_CONFLICT_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_L__PRECODING_START_BEFORE_BF_PARAMS_CLEAR_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_L__QRE_RX_STOMP_TXBF_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_L__QRE_TXBF_STOMP_RX_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_L__QRE_INTERFACE_TIMEOUT_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_L__WT_MEM_RD_CONFLICT_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_L__WT_MEM_WR_CONFLICT_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_L__UNSAVED_CV_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_L__B2B_CBF_DONE_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_L__B2B_CBF_START_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_L__DMA1_HANG_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_L__DMA0_HANG_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_L__CBF_BUFFER_OVERFLOW_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_L__MIMO_CTRL_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_L__CBF_START_MISING_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_L__MPI_CBF_VALID_TIMEOUT_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_L__CBF_DONE_NOT_RECEIVED_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_L__MORE_CBF_DATA_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_L__LESS_CBF_DATA_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_L__OUT_OF_RANGE_CBF_USER_ID_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_L__CBF_START_BEFORE_EXPECT_CBF_CLEAR_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_L__BF_PARAMS_PER_USER_LESS_TLVS_ERROR_MASK___M 0x80000000 +#define PHYA_TXBF_ERROR_MASK_L__BF_PARAMS_PER_USER_LESS_TLVS_ERROR_MASK___S 31 +#define PHYA_TXBF_ERROR_MASK_L__TXBFP_QRE_TONE_UNDERRUN_ERROR_MASK___M 0x40000000 +#define PHYA_TXBF_ERROR_MASK_L__TXBFP_QRE_TONE_UNDERRUN_ERROR_MASK___S 30 +#define PHYA_TXBF_ERROR_MASK_L__CVCTRL_STATE_TIMEOUT_ERROR_MASK___M 0x20000000 +#define PHYA_TXBF_ERROR_MASK_L__CVCTRL_STATE_TIMEOUT_ERROR_MASK___S 29 +#define PHYA_TXBF_ERROR_MASK_L__PRECODING_ERROR_MASK___M 0x10000000 +#define PHYA_TXBF_ERROR_MASK_L__PRECODING_ERROR_MASK___S 28 +#define PHYA_TXBF_ERROR_MASK_L__PREFETCH_FIFO_UNDERFLOW_ERROR_MASK___M 0x08000000 +#define PHYA_TXBF_ERROR_MASK_L__PREFETCH_FIFO_UNDERFLOW_ERROR_MASK___S 27 +#define PHYA_TXBF_ERROR_MASK_L__PREFETCH_FIFO_OVERFLOW_ERROR_MASK___M 0x04000000 +#define PHYA_TXBF_ERROR_MASK_L__PREFETCH_FIFO_OVERFLOW_ERROR_MASK___S 26 +#define PHYA_TXBF_ERROR_MASK_L__MORE_PREFETCH_TLVS_ERROR_MASK___M 0x02000000 +#define PHYA_TXBF_ERROR_MASK_L__MORE_PREFETCH_TLVS_ERROR_MASK___S 25 +#define PHYA_TXBF_ERROR_MASK_L__LESS_PREFETCH_TLVS_ERROR_MASK___M 0x01000000 +#define PHYA_TXBF_ERROR_MASK_L__LESS_PREFETCH_TLVS_ERROR_MASK___S 24 +#define PHYA_TXBF_ERROR_MASK_L__TXBF_AXI_SLAVE_TIMEOUT_ERROR_MASK___M 0x00800000 +#define PHYA_TXBF_ERROR_MASK_L__TXBF_AXI_SLAVE_TIMEOUT_ERROR_MASK___S 23 +#define PHYA_TXBF_ERROR_MASK_L__PRECODING_FIFO_UNDERFLOW_ERROR_MASK___M 0x00400000 +#define PHYA_TXBF_ERROR_MASK_L__PRECODING_FIFO_UNDERFLOW_ERROR_MASK___S 22 +#define PHYA_TXBF_ERROR_MASK_L__PRECODING_FIFO_OVERFLOW_ERROR_MASK___M 0x00200000 +#define PHYA_TXBF_ERROR_MASK_L__PRECODING_FIFO_OVERFLOW_ERROR_MASK___S 21 +#define PHYA_TXBF_ERROR_MASK_L__TONE_MAP_LUT_RD_CONFLICT_ERROR_MASK___M 0x00100000 +#define PHYA_TXBF_ERROR_MASK_L__TONE_MAP_LUT_RD_CONFLICT_ERROR_MASK___S 20 +#define PHYA_TXBF_ERROR_MASK_L__PRECODING_START_BEFORE_BF_PARAMS_CLEAR_ERROR_MASK___M 0x00080000 +#define PHYA_TXBF_ERROR_MASK_L__PRECODING_START_BEFORE_BF_PARAMS_CLEAR_ERROR_MASK___S 19 +#define PHYA_TXBF_ERROR_MASK_L__QRE_RX_STOMP_TXBF_ERROR_MASK___M 0x00040000 +#define PHYA_TXBF_ERROR_MASK_L__QRE_RX_STOMP_TXBF_ERROR_MASK___S 18 +#define PHYA_TXBF_ERROR_MASK_L__QRE_TXBF_STOMP_RX_ERROR_MASK___M 0x00020000 +#define PHYA_TXBF_ERROR_MASK_L__QRE_TXBF_STOMP_RX_ERROR_MASK___S 17 +#define PHYA_TXBF_ERROR_MASK_L__QRE_INTERFACE_TIMEOUT_ERROR_MASK___M 0x00010000 +#define PHYA_TXBF_ERROR_MASK_L__QRE_INTERFACE_TIMEOUT_ERROR_MASK___S 16 +#define PHYA_TXBF_ERROR_MASK_L__WT_MEM_RD_CONFLICT_ERROR_MASK___M 0x00008000 +#define PHYA_TXBF_ERROR_MASK_L__WT_MEM_RD_CONFLICT_ERROR_MASK___S 15 +#define PHYA_TXBF_ERROR_MASK_L__WT_MEM_WR_CONFLICT_ERROR_MASK___M 0x00004000 +#define PHYA_TXBF_ERROR_MASK_L__WT_MEM_WR_CONFLICT_ERROR_MASK___S 14 +#define PHYA_TXBF_ERROR_MASK_L__UNSAVED_CV_ERROR_MASK___M 0x00002000 +#define PHYA_TXBF_ERROR_MASK_L__UNSAVED_CV_ERROR_MASK___S 13 +#define PHYA_TXBF_ERROR_MASK_L__B2B_CBF_DONE_ERROR_MASK___M 0x00001000 +#define PHYA_TXBF_ERROR_MASK_L__B2B_CBF_DONE_ERROR_MASK___S 12 +#define PHYA_TXBF_ERROR_MASK_L__B2B_CBF_START_ERROR_MASK___M 0x00000800 +#define PHYA_TXBF_ERROR_MASK_L__B2B_CBF_START_ERROR_MASK___S 11 +#define PHYA_TXBF_ERROR_MASK_L__DMA1_HANG_ERROR_MASK___M 0x00000400 +#define PHYA_TXBF_ERROR_MASK_L__DMA1_HANG_ERROR_MASK___S 10 +#define PHYA_TXBF_ERROR_MASK_L__DMA0_HANG_ERROR_MASK___M 0x00000200 +#define PHYA_TXBF_ERROR_MASK_L__DMA0_HANG_ERROR_MASK___S 9 +#define PHYA_TXBF_ERROR_MASK_L__CBF_BUFFER_OVERFLOW_MASK___M 0x00000100 +#define PHYA_TXBF_ERROR_MASK_L__CBF_BUFFER_OVERFLOW_MASK___S 8 +#define PHYA_TXBF_ERROR_MASK_L__MIMO_CTRL_ERROR_MASK___M 0x00000080 +#define PHYA_TXBF_ERROR_MASK_L__MIMO_CTRL_ERROR_MASK___S 7 +#define PHYA_TXBF_ERROR_MASK_L__CBF_START_MISING_ERROR_MASK___M 0x00000040 +#define PHYA_TXBF_ERROR_MASK_L__CBF_START_MISING_ERROR_MASK___S 6 +#define PHYA_TXBF_ERROR_MASK_L__MPI_CBF_VALID_TIMEOUT_ERROR_MASK___M 0x00000020 +#define PHYA_TXBF_ERROR_MASK_L__MPI_CBF_VALID_TIMEOUT_ERROR_MASK___S 5 +#define PHYA_TXBF_ERROR_MASK_L__CBF_DONE_NOT_RECEIVED_ERROR_MASK___M 0x00000010 +#define PHYA_TXBF_ERROR_MASK_L__CBF_DONE_NOT_RECEIVED_ERROR_MASK___S 4 +#define PHYA_TXBF_ERROR_MASK_L__MORE_CBF_DATA_ERROR_MASK___M 0x00000008 +#define PHYA_TXBF_ERROR_MASK_L__MORE_CBF_DATA_ERROR_MASK___S 3 +#define PHYA_TXBF_ERROR_MASK_L__LESS_CBF_DATA_ERROR_MASK___M 0x00000004 +#define PHYA_TXBF_ERROR_MASK_L__LESS_CBF_DATA_ERROR_MASK___S 2 +#define PHYA_TXBF_ERROR_MASK_L__OUT_OF_RANGE_CBF_USER_ID_ERROR_MASK___M 0x00000002 +#define PHYA_TXBF_ERROR_MASK_L__OUT_OF_RANGE_CBF_USER_ID_ERROR_MASK___S 1 +#define PHYA_TXBF_ERROR_MASK_L__CBF_START_BEFORE_EXPECT_CBF_CLEAR_ERROR_MASK___M 0x00000001 +#define PHYA_TXBF_ERROR_MASK_L__CBF_START_BEFORE_EXPECT_CBF_CLEAR_ERROR_MASK___S 0 +#define PHYA_TXBF_ERROR_MASK_L___M 0xFFFFFFFF +#define PHYA_TXBF_ERROR_MASK_L___S 0 + +#define PHYA_TXBF_ERROR_MASK_U (0x003C002C) +#define PHYA_TXBF_ERROR_MASK_U___RWC QCSR_REG_RW +#define PHYA_TXBF_ERROR_MASK_U___POR 0x000001FF +#define PHYA_TXBF_ERROR_MASK_U__EXPECT_CBF_BUF_TIMEOUT_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_U__BF_PARAMS_PER_USER_BEFORE_COMMON_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_U__PREFETCH_PER_USER_BEFORE_COMMON_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_U__EXPECT_CBF_PER_USER_BEFORE_COMMON_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_U__PRECODING_STG1_STG2_WAIT_TIMEOUT_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_U__EXPECT_CBF_PER_USER_MORE_TLVS_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_U__EXPECT_CBF_PER_USER_LESS_TLVS_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_U__BF_PARAMS_COMMON_UNEXPECTED_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_U__BF_PARAMS_PER_USER_MORE_TLVS_ERROR_MASK___POR 0x1 +#define PHYA_TXBF_ERROR_MASK_U__EXPECT_CBF_BUF_TIMEOUT_ERROR_MASK___M 0x00000100 +#define PHYA_TXBF_ERROR_MASK_U__EXPECT_CBF_BUF_TIMEOUT_ERROR_MASK___S 8 +#define PHYA_TXBF_ERROR_MASK_U__BF_PARAMS_PER_USER_BEFORE_COMMON_ERROR_MASK___M 0x00000080 +#define PHYA_TXBF_ERROR_MASK_U__BF_PARAMS_PER_USER_BEFORE_COMMON_ERROR_MASK___S 7 +#define PHYA_TXBF_ERROR_MASK_U__PREFETCH_PER_USER_BEFORE_COMMON_ERROR_MASK___M 0x00000040 +#define PHYA_TXBF_ERROR_MASK_U__PREFETCH_PER_USER_BEFORE_COMMON_ERROR_MASK___S 6 +#define PHYA_TXBF_ERROR_MASK_U__EXPECT_CBF_PER_USER_BEFORE_COMMON_ERROR_MASK___M 0x00000020 +#define PHYA_TXBF_ERROR_MASK_U__EXPECT_CBF_PER_USER_BEFORE_COMMON_ERROR_MASK___S 5 +#define PHYA_TXBF_ERROR_MASK_U__PRECODING_STG1_STG2_WAIT_TIMEOUT_ERROR_MASK___M 0x00000010 +#define PHYA_TXBF_ERROR_MASK_U__PRECODING_STG1_STG2_WAIT_TIMEOUT_ERROR_MASK___S 4 +#define PHYA_TXBF_ERROR_MASK_U__EXPECT_CBF_PER_USER_MORE_TLVS_ERROR_MASK___M 0x00000008 +#define PHYA_TXBF_ERROR_MASK_U__EXPECT_CBF_PER_USER_MORE_TLVS_ERROR_MASK___S 3 +#define PHYA_TXBF_ERROR_MASK_U__EXPECT_CBF_PER_USER_LESS_TLVS_ERROR_MASK___M 0x00000004 +#define PHYA_TXBF_ERROR_MASK_U__EXPECT_CBF_PER_USER_LESS_TLVS_ERROR_MASK___S 2 +#define PHYA_TXBF_ERROR_MASK_U__BF_PARAMS_COMMON_UNEXPECTED_ERROR_MASK___M 0x00000002 +#define PHYA_TXBF_ERROR_MASK_U__BF_PARAMS_COMMON_UNEXPECTED_ERROR_MASK___S 1 +#define PHYA_TXBF_ERROR_MASK_U__BF_PARAMS_PER_USER_MORE_TLVS_ERROR_MASK___M 0x00000001 +#define PHYA_TXBF_ERROR_MASK_U__BF_PARAMS_PER_USER_MORE_TLVS_ERROR_MASK___S 0 +#define PHYA_TXBF_ERROR_MASK_U___M 0x000001FF +#define PHYA_TXBF_ERROR_MASK_U___S 0 + +#define PHYA_TXBF_PHYDBG_TXBF_0_L (0x003C0030) +#define PHYA_TXBF_PHYDBG_TXBF_0_L___RWC QCSR_REG_RW +#define PHYA_TXBF_PHYDBG_TXBF_0_L___POR 0x00000000 +#define PHYA_TXBF_PHYDBG_TXBF_0_L__TXBF_PHYDBG_EVENT_EN___POR 0x00 +#define PHYA_TXBF_PHYDBG_TXBF_0_L__TXBF_PHYDBG_RAW_MODE___POR 0x0 +#define PHYA_TXBF_PHYDBG_TXBF_0_L__TXBF_PHYDBG_EVENT_EN___M 0x0000FF00 +#define PHYA_TXBF_PHYDBG_TXBF_0_L__TXBF_PHYDBG_EVENT_EN___S 8 +#define PHYA_TXBF_PHYDBG_TXBF_0_L__TXBF_PHYDBG_RAW_MODE___M 0x00000001 +#define PHYA_TXBF_PHYDBG_TXBF_0_L__TXBF_PHYDBG_RAW_MODE___S 0 +#define PHYA_TXBF_PHYDBG_TXBF_0_L___M 0x0000FF01 +#define PHYA_TXBF_PHYDBG_TXBF_0_L___S 0 + +#define PHYA_TXBF_PHYDBG_TXBF_10_L (0x003C0038) +#define PHYA_TXBF_PHYDBG_TXBF_10_L___RWC QCSR_REG_RW +#define PHYA_TXBF_PHYDBG_TXBF_10_L___POR 0x00000000 +#define PHYA_TXBF_PHYDBG_TXBF_10_L__TXBF_PHYDBG_EVENT_MASK_0_0___POR 0x00000000 +#define PHYA_TXBF_PHYDBG_TXBF_10_L__TXBF_PHYDBG_EVENT_MASK_0_0___M 0xFFFFFFFF +#define PHYA_TXBF_PHYDBG_TXBF_10_L__TXBF_PHYDBG_EVENT_MASK_0_0___S 0 +#define PHYA_TXBF_PHYDBG_TXBF_10_L___M 0xFFFFFFFF +#define PHYA_TXBF_PHYDBG_TXBF_10_L___S 0 + +#define PHYA_TXBF_PHYDBG_TXBF_10_U (0x003C003C) +#define PHYA_TXBF_PHYDBG_TXBF_10_U___RWC QCSR_REG_RW +#define PHYA_TXBF_PHYDBG_TXBF_10_U___POR 0x00000000 +#define PHYA_TXBF_PHYDBG_TXBF_10_U__TXBF_PHYDBG_EVENT_MASK_1_0___POR 0x00000000 +#define PHYA_TXBF_PHYDBG_TXBF_10_U__TXBF_PHYDBG_EVENT_MASK_1_0___M 0xFFFFFFFF +#define PHYA_TXBF_PHYDBG_TXBF_10_U__TXBF_PHYDBG_EVENT_MASK_1_0___S 0 +#define PHYA_TXBF_PHYDBG_TXBF_10_U___M 0xFFFFFFFF +#define PHYA_TXBF_PHYDBG_TXBF_10_U___S 0 + +#define PHYA_TXBF_PHYDBG_TXBF_11_L (0x003C0040) +#define PHYA_TXBF_PHYDBG_TXBF_11_L___RWC QCSR_REG_RW +#define PHYA_TXBF_PHYDBG_TXBF_11_L___POR 0x00000000 +#define PHYA_TXBF_PHYDBG_TXBF_11_L__TXBF_PHYDBG_EVENT_MASK_0_1___POR 0x00000000 +#define PHYA_TXBF_PHYDBG_TXBF_11_L__TXBF_PHYDBG_EVENT_MASK_0_1___M 0xFFFFFFFF +#define PHYA_TXBF_PHYDBG_TXBF_11_L__TXBF_PHYDBG_EVENT_MASK_0_1___S 0 +#define PHYA_TXBF_PHYDBG_TXBF_11_L___M 0xFFFFFFFF +#define PHYA_TXBF_PHYDBG_TXBF_11_L___S 0 + +#define PHYA_TXBF_PHYDBG_TXBF_11_U (0x003C0044) +#define PHYA_TXBF_PHYDBG_TXBF_11_U___RWC QCSR_REG_RW +#define PHYA_TXBF_PHYDBG_TXBF_11_U___POR 0x00000000 +#define PHYA_TXBF_PHYDBG_TXBF_11_U__TXBF_PHYDBG_EVENT_MASK_1_1___POR 0x00000000 +#define PHYA_TXBF_PHYDBG_TXBF_11_U__TXBF_PHYDBG_EVENT_MASK_1_1___M 0xFFFFFFFF +#define PHYA_TXBF_PHYDBG_TXBF_11_U__TXBF_PHYDBG_EVENT_MASK_1_1___S 0 +#define PHYA_TXBF_PHYDBG_TXBF_11_U___M 0xFFFFFFFF +#define PHYA_TXBF_PHYDBG_TXBF_11_U___S 0 + +#define PHYA_TXBF_PHYDBG_TXBF_12_L (0x003C0048) +#define PHYA_TXBF_PHYDBG_TXBF_12_L___RWC QCSR_REG_RW +#define PHYA_TXBF_PHYDBG_TXBF_12_L___POR 0x00000000 +#define PHYA_TXBF_PHYDBG_TXBF_12_L__TXBF_PHYDBG_EVENT_MASK_0_2___POR 0x00000000 +#define PHYA_TXBF_PHYDBG_TXBF_12_L__TXBF_PHYDBG_EVENT_MASK_0_2___M 0xFFFFFFFF +#define PHYA_TXBF_PHYDBG_TXBF_12_L__TXBF_PHYDBG_EVENT_MASK_0_2___S 0 +#define PHYA_TXBF_PHYDBG_TXBF_12_L___M 0xFFFFFFFF +#define PHYA_TXBF_PHYDBG_TXBF_12_L___S 0 + +#define PHYA_TXBF_PHYDBG_TXBF_12_U (0x003C004C) +#define PHYA_TXBF_PHYDBG_TXBF_12_U___RWC QCSR_REG_RW +#define PHYA_TXBF_PHYDBG_TXBF_12_U___POR 0x00000000 +#define PHYA_TXBF_PHYDBG_TXBF_12_U__TXBF_PHYDBG_EVENT_MASK_1_2___POR 0x00000000 +#define PHYA_TXBF_PHYDBG_TXBF_12_U__TXBF_PHYDBG_EVENT_MASK_1_2___M 0xFFFFFFFF +#define PHYA_TXBF_PHYDBG_TXBF_12_U__TXBF_PHYDBG_EVENT_MASK_1_2___S 0 +#define PHYA_TXBF_PHYDBG_TXBF_12_U___M 0xFFFFFFFF +#define PHYA_TXBF_PHYDBG_TXBF_12_U___S 0 + +#define PHYA_TXBF_PHYDBG_TXBF_13_L (0x003C0050) +#define PHYA_TXBF_PHYDBG_TXBF_13_L___RWC QCSR_REG_RW +#define PHYA_TXBF_PHYDBG_TXBF_13_L___POR 0x00000000 +#define PHYA_TXBF_PHYDBG_TXBF_13_L__TXBF_PHYDBG_EVENT_MASK_0_3___POR 0x00000000 +#define PHYA_TXBF_PHYDBG_TXBF_13_L__TXBF_PHYDBG_EVENT_MASK_0_3___M 0xFFFFFFFF +#define PHYA_TXBF_PHYDBG_TXBF_13_L__TXBF_PHYDBG_EVENT_MASK_0_3___S 0 +#define PHYA_TXBF_PHYDBG_TXBF_13_L___M 0xFFFFFFFF +#define PHYA_TXBF_PHYDBG_TXBF_13_L___S 0 + +#define PHYA_TXBF_PHYDBG_TXBF_13_U (0x003C0054) +#define PHYA_TXBF_PHYDBG_TXBF_13_U___RWC QCSR_REG_RW +#define PHYA_TXBF_PHYDBG_TXBF_13_U___POR 0x00000000 +#define PHYA_TXBF_PHYDBG_TXBF_13_U__TXBF_PHYDBG_EVENT_MASK_1_3___POR 0x00000000 +#define PHYA_TXBF_PHYDBG_TXBF_13_U__TXBF_PHYDBG_EVENT_MASK_1_3___M 0xFFFFFFFF +#define PHYA_TXBF_PHYDBG_TXBF_13_U__TXBF_PHYDBG_EVENT_MASK_1_3___S 0 +#define PHYA_TXBF_PHYDBG_TXBF_13_U___M 0xFFFFFFFF +#define PHYA_TXBF_PHYDBG_TXBF_13_U___S 0 + +#define PHYA_TXBF_PHYDBG_TXBF_2_L (0x003C0058) +#define PHYA_TXBF_PHYDBG_TXBF_2_L___RWC QCSR_REG_RW +#define PHYA_TXBF_PHYDBG_TXBF_2_L___POR 0x00000000 +#define PHYA_TXBF_PHYDBG_TXBF_2_L__TXBF_PHYDBG_RAW_MUX_SEL___POR 0x0000 +#define PHYA_TXBF_PHYDBG_TXBF_2_L__TXBF_PHYDBG_EVENT_MUX_SEL___POR 0x00 +#define PHYA_TXBF_PHYDBG_TXBF_2_L__TXBF_PHYDBG_RAW_MUX_SEL___M 0xFFFF0000 +#define PHYA_TXBF_PHYDBG_TXBF_2_L__TXBF_PHYDBG_RAW_MUX_SEL___S 16 +#define PHYA_TXBF_PHYDBG_TXBF_2_L__TXBF_PHYDBG_EVENT_MUX_SEL___M 0x000000FF +#define PHYA_TXBF_PHYDBG_TXBF_2_L__TXBF_PHYDBG_EVENT_MUX_SEL___S 0 +#define PHYA_TXBF_PHYDBG_TXBF_2_L___M 0xFFFF00FF +#define PHYA_TXBF_PHYDBG_TXBF_2_L___S 0 + +#define PHYA_TXBF_CFG_0_L (0x003C0060) +#define PHYA_TXBF_CFG_0_L___RWC QCSR_REG_RW +#define PHYA_TXBF_CFG_0_L___POR 0x00000000 +#define PHYA_TXBF_CFG_0_L__DYN_CGC_DIS_CBF_TCCBF_LOGIC___POR 0x0 +#define PHYA_TXBF_CFG_0_L__DYN_CGC_DIS_TXBFP_LOGIC___POR 0x0 +#define PHYA_TXBF_CFG_0_L__DYN_CGC_CSR_DIS___POR 0x0 +#define PHYA_TXBF_CFG_0_L__DYN_CGC_DIS___POR 0x0 +#define PHYA_TXBF_CFG_0_L__DYN_CGC_DIS_CBF_TCCBF_LOGIC___M 0x01000000 +#define PHYA_TXBF_CFG_0_L__DYN_CGC_DIS_CBF_TCCBF_LOGIC___S 24 +#define PHYA_TXBF_CFG_0_L__DYN_CGC_DIS_TXBFP_LOGIC___M 0x00010000 +#define PHYA_TXBF_CFG_0_L__DYN_CGC_DIS_TXBFP_LOGIC___S 16 +#define PHYA_TXBF_CFG_0_L__DYN_CGC_CSR_DIS___M 0x00000100 +#define PHYA_TXBF_CFG_0_L__DYN_CGC_CSR_DIS___S 8 +#define PHYA_TXBF_CFG_0_L__DYN_CGC_DIS___M 0x00000001 +#define PHYA_TXBF_CFG_0_L__DYN_CGC_DIS___S 0 +#define PHYA_TXBF_CFG_0_L___M 0x01010101 +#define PHYA_TXBF_CFG_0_L___S 0 + +#define PHYA_TXBF_CFG_0_U (0x003C0064) +#define PHYA_TXBF_CFG_0_U___RWC QCSR_REG_RW +#define PHYA_TXBF_CFG_0_U___POR 0x01000000 +#define PHYA_TXBF_CFG_0_U__EXPECT_CBF_BUF_EN___POR 0x1 +#define PHYA_TXBF_CFG_0_U__DYN_CGC_DIS_TXBFP_HW_ACC___POR 0x0 +#define PHYA_TXBF_CFG_0_U__DYN_CGC_DIS_TXBF_WT_MEM___POR 0x0 +#define PHYA_TXBF_CFG_0_U__DYN_CGC_DIS_TXBF_CV_MEM___POR 0x0 +#define PHYA_TXBF_CFG_0_U__EXPECT_CBF_BUF_EN___M 0x01000000 +#define PHYA_TXBF_CFG_0_U__EXPECT_CBF_BUF_EN___S 24 +#define PHYA_TXBF_CFG_0_U__DYN_CGC_DIS_TXBFP_HW_ACC___M 0x00010000 +#define PHYA_TXBF_CFG_0_U__DYN_CGC_DIS_TXBFP_HW_ACC___S 16 +#define PHYA_TXBF_CFG_0_U__DYN_CGC_DIS_TXBF_WT_MEM___M 0x00000100 +#define PHYA_TXBF_CFG_0_U__DYN_CGC_DIS_TXBF_WT_MEM___S 8 +#define PHYA_TXBF_CFG_0_U__DYN_CGC_DIS_TXBF_CV_MEM___M 0x00000001 +#define PHYA_TXBF_CFG_0_U__DYN_CGC_DIS_TXBF_CV_MEM___S 0 +#define PHYA_TXBF_CFG_0_U___M 0x01010101 +#define PHYA_TXBF_CFG_0_U___S 0 + +#define PHYA_TXBF_CFG_1_L (0x003C0068) +#define PHYA_TXBF_CFG_1_L___RWC QCSR_REG_RW +#define PHYA_TXBF_CFG_1_L___POR 0x00001400 +#define PHYA_TXBF_CFG_1_L__MPI_CBF_VALID_TIMEOUT___POR 0x00001400 +#define PHYA_TXBF_CFG_1_L__MPI_CBF_VALID_TIMEOUT___M 0xFFFFFFFF +#define PHYA_TXBF_CFG_1_L__MPI_CBF_VALID_TIMEOUT___S 0 +#define PHYA_TXBF_CFG_1_L___M 0xFFFFFFFF +#define PHYA_TXBF_CFG_1_L___S 0 + +#define PHYA_TXBF_CFG_1_U (0x003C006C) +#define PHYA_TXBF_CFG_1_U___RWC QCSR_REG_RW +#define PHYA_TXBF_CFG_1_U___POR 0x00001400 +#define PHYA_TXBF_CFG_1_U__CBF_DONE_NOT_RECEIVED_TIMEOUT___POR 0x00001400 +#define PHYA_TXBF_CFG_1_U__CBF_DONE_NOT_RECEIVED_TIMEOUT___M 0xFFFFFFFF +#define PHYA_TXBF_CFG_1_U__CBF_DONE_NOT_RECEIVED_TIMEOUT___S 0 +#define PHYA_TXBF_CFG_1_U___M 0xFFFFFFFF +#define PHYA_TXBF_CFG_1_U___S 0 + +#define PHYA_TXBF_CFG_2_L (0x003C0070) +#define PHYA_TXBF_CFG_2_L___RWC QCSR_REG_RW +#define PHYA_TXBF_CFG_2_L___POR 0x00001400 +#define PHYA_TXBF_CFG_2_L__CBF_START_MISSING_TIMEOUT___POR 0x00001400 +#define PHYA_TXBF_CFG_2_L__CBF_START_MISSING_TIMEOUT___M 0xFFFFFFFF +#define PHYA_TXBF_CFG_2_L__CBF_START_MISSING_TIMEOUT___S 0 +#define PHYA_TXBF_CFG_2_L___M 0xFFFFFFFF +#define PHYA_TXBF_CFG_2_L___S 0 + +#define PHYA_TXBF_CFG_2_U (0x003C0074) +#define PHYA_TXBF_CFG_2_U___RWC QCSR_REG_RW +#define PHYA_TXBF_CFG_2_U___POR 0x00001400 +#define PHYA_TXBF_CFG_2_U__DMA_HANG_TIMEOUT___POR 0x00001400 +#define PHYA_TXBF_CFG_2_U__DMA_HANG_TIMEOUT___M 0xFFFFFFFF +#define PHYA_TXBF_CFG_2_U__DMA_HANG_TIMEOUT___S 0 +#define PHYA_TXBF_CFG_2_U___M 0xFFFFFFFF +#define PHYA_TXBF_CFG_2_U___S 0 + +#define PHYA_TXBF_CFG_3_L (0x003C0078) +#define PHYA_TXBF_CFG_3_L___RWC QCSR_REG_RW +#define PHYA_TXBF_CFG_3_L___POR 0x00000200 +#define PHYA_TXBF_CFG_3_L__QRE_INTERFACE_TIMEOUT___POR 0x00000200 +#define PHYA_TXBF_CFG_3_L__QRE_INTERFACE_TIMEOUT___M 0xFFFFFFFF +#define PHYA_TXBF_CFG_3_L__QRE_INTERFACE_TIMEOUT___S 0 +#define PHYA_TXBF_CFG_3_L___M 0xFFFFFFFF +#define PHYA_TXBF_CFG_3_L___S 0 + +#define PHYA_TXBF_CFG_3_U (0x003C007C) +#define PHYA_TXBF_CFG_3_U___RWC QCSR_REG_RW +#define PHYA_TXBF_CFG_3_U___POR 0x00001400 +#define PHYA_TXBF_CFG_3_U__EXPECT_CBF_BUF_TIMEOUT___POR 0x00001400 +#define PHYA_TXBF_CFG_3_U__EXPECT_CBF_BUF_TIMEOUT___M 0xFFFFFFFF +#define PHYA_TXBF_CFG_3_U__EXPECT_CBF_BUF_TIMEOUT___S 0 +#define PHYA_TXBF_CFG_3_U___M 0xFFFFFFFF +#define PHYA_TXBF_CFG_3_U___S 0 + +#define PHYA_TXBF_TXBF_0_L (0x003C0080) +#define PHYA_TXBF_TXBF_0_L___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_0_L___POR 0x00010100 +#define PHYA_TXBF_TXBF_0_L__TXBF_PTONE_WTG_RU___POR 0x0 +#define PHYA_TXBF_TXBF_0_L__TXBF_PCHN_WTG_EN___POR 0x1 +#define PHYA_TXBF_TXBF_0_L__TXBF_MU_PTONE_WTG_EN___POR 0x1 +#define PHYA_TXBF_TXBF_0_L__TXBF_SU_PTONE_WTG_EN___POR 0x0 +#define PHYA_TXBF_TXBF_0_L__TXBF_PTONE_WTG_RU___M 0x01000000 +#define PHYA_TXBF_TXBF_0_L__TXBF_PTONE_WTG_RU___S 24 +#define PHYA_TXBF_TXBF_0_L__TXBF_PCHN_WTG_EN___M 0x00010000 +#define PHYA_TXBF_TXBF_0_L__TXBF_PCHN_WTG_EN___S 16 +#define PHYA_TXBF_TXBF_0_L__TXBF_MU_PTONE_WTG_EN___M 0x00000100 +#define PHYA_TXBF_TXBF_0_L__TXBF_MU_PTONE_WTG_EN___S 8 +#define PHYA_TXBF_TXBF_0_L__TXBF_SU_PTONE_WTG_EN___M 0x00000001 +#define PHYA_TXBF_TXBF_0_L__TXBF_SU_PTONE_WTG_EN___S 0 +#define PHYA_TXBF_TXBF_0_L___M 0x01010101 +#define PHYA_TXBF_TXBF_0_L___S 0 + +#define PHYA_TXBF_TXBF_0_U (0x003C0084) +#define PHYA_TXBF_TXBF_0_U___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_0_U___POR 0x00040100 +#define PHYA_TXBF_TXBF_0_U__TXBF_MU_SNR_MODE___POR 0x0 +#define PHYA_TXBF_TXBF_0_U__TXBF_BETA___POR 0x04 +#define PHYA_TXBF_TXBF_0_U__TXBF_SU_STREAM_WTG_EN___POR 0x1 +#define PHYA_TXBF_TXBF_0_U__TXBF_PCHN_WTG_RU___POR 0x0 +#define PHYA_TXBF_TXBF_0_U__TXBF_MU_SNR_MODE___M 0x03000000 +#define PHYA_TXBF_TXBF_0_U__TXBF_MU_SNR_MODE___S 24 +#define PHYA_TXBF_TXBF_0_U__TXBF_BETA___M 0x001F0000 +#define PHYA_TXBF_TXBF_0_U__TXBF_BETA___S 16 +#define PHYA_TXBF_TXBF_0_U__TXBF_SU_STREAM_WTG_EN___M 0x00000100 +#define PHYA_TXBF_TXBF_0_U__TXBF_SU_STREAM_WTG_EN___S 8 +#define PHYA_TXBF_TXBF_0_U__TXBF_PCHN_WTG_RU___M 0x00000001 +#define PHYA_TXBF_TXBF_0_U__TXBF_PCHN_WTG_RU___S 0 +#define PHYA_TXBF_TXBF_0_U___M 0x031F0101 +#define PHYA_TXBF_TXBF_0_U___S 0 + +#define PHYA_TXBF_TXBF_1_L (0x003C0088) +#define PHYA_TXBF_TXBF_1_L___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_1_L___POR 0x00000000 +#define PHYA_TXBF_TXBF_1_L__WT_MEM_BASE_ADDR_0___POR 0x00000000 +#define PHYA_TXBF_TXBF_1_L__WT_MEM_BASE_ADDR_0___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_1_L__WT_MEM_BASE_ADDR_0___S 0 +#define PHYA_TXBF_TXBF_1_L___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_1_L___S 0 + +#define PHYA_TXBF_TXBF_1_U (0x003C008C) +#define PHYA_TXBF_TXBF_1_U___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_1_U___POR 0x00000000 +#define PHYA_TXBF_TXBF_1_U__WT_MEM_BASE_ADDR_1___POR 0x00000000 +#define PHYA_TXBF_TXBF_1_U__WT_MEM_BASE_ADDR_1___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_1_U__WT_MEM_BASE_ADDR_1___S 0 +#define PHYA_TXBF_TXBF_1_U___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_1_U___S 0 + +#define PHYA_TXBF_TXBF_2_L (0x003C0090) +#define PHYA_TXBF_TXBF_2_L___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_2_L___POR 0x00010001 +#define PHYA_TXBF_TXBF_2_L__DDR_DMA_DONE_DETECT_MODE___POR 0x0 +#define PHYA_TXBF_TXBF_2_L__PRECODING_STG2_WAIT_FOR_DDR_TRANSFER_DONE___POR 0x1 +#define PHYA_TXBF_TXBF_2_L__CBF_DDR_DMA_1_EN___POR 0x0 +#define PHYA_TXBF_TXBF_2_L__CBF_DDR_DMA_0_EN___POR 0x1 +#define PHYA_TXBF_TXBF_2_L__DDR_DMA_DONE_DETECT_MODE___M 0x01000000 +#define PHYA_TXBF_TXBF_2_L__DDR_DMA_DONE_DETECT_MODE___S 24 +#define PHYA_TXBF_TXBF_2_L__PRECODING_STG2_WAIT_FOR_DDR_TRANSFER_DONE___M 0x00010000 +#define PHYA_TXBF_TXBF_2_L__PRECODING_STG2_WAIT_FOR_DDR_TRANSFER_DONE___S 16 +#define PHYA_TXBF_TXBF_2_L__CBF_DDR_DMA_1_EN___M 0x00000100 +#define PHYA_TXBF_TXBF_2_L__CBF_DDR_DMA_1_EN___S 8 +#define PHYA_TXBF_TXBF_2_L__CBF_DDR_DMA_0_EN___M 0x00000001 +#define PHYA_TXBF_TXBF_2_L__CBF_DDR_DMA_0_EN___S 0 +#define PHYA_TXBF_TXBF_2_L___M 0x01010101 +#define PHYA_TXBF_TXBF_2_L___S 0 + +#define PHYA_TXBF_TXBF_2_U (0x003C0094) +#define PHYA_TXBF_TXBF_2_U___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_2_U___POR 0x00000000 +#define PHYA_TXBF_TXBF_2_U__PRIMARY_CHANNEL___POR 0x0 +#define PHYA_TXBF_TXBF_2_U__PRIMARY_CHANNEL___M 0x00000007 +#define PHYA_TXBF_TXBF_2_U__PRIMARY_CHANNEL___S 0 +#define PHYA_TXBF_TXBF_2_U___M 0x00000007 +#define PHYA_TXBF_TXBF_2_U___S 0 + +#define PHYA_TXBF_TXBF_30_L (0x003C0098) +#define PHYA_TXBF_TXBF_30_L___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_30_L___POR 0x00000000 +#define PHYA_TXBF_TXBF_30_L__DMA_DESC_TEMPLATE_0_0_0___POR 0x00000000 +#define PHYA_TXBF_TXBF_30_L__DMA_DESC_TEMPLATE_0_0_0___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_30_L__DMA_DESC_TEMPLATE_0_0_0___S 0 +#define PHYA_TXBF_TXBF_30_L___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_30_L___S 0 + +#define PHYA_TXBF_TXBF_30_U (0x003C009C) +#define PHYA_TXBF_TXBF_30_U___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_30_U___POR 0x00000000 +#define PHYA_TXBF_TXBF_30_U__DMA_DESC_TEMPLATE_0_1_0___POR 0x00000000 +#define PHYA_TXBF_TXBF_30_U__DMA_DESC_TEMPLATE_0_1_0___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_30_U__DMA_DESC_TEMPLATE_0_1_0___S 0 +#define PHYA_TXBF_TXBF_30_U___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_30_U___S 0 + +#define PHYA_TXBF_TXBF_31_L (0x003C00A0) +#define PHYA_TXBF_TXBF_31_L___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_31_L___POR 0x00000000 +#define PHYA_TXBF_TXBF_31_L__DMA_DESC_TEMPLATE_0_0_1___POR 0x00000000 +#define PHYA_TXBF_TXBF_31_L__DMA_DESC_TEMPLATE_0_0_1___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_31_L__DMA_DESC_TEMPLATE_0_0_1___S 0 +#define PHYA_TXBF_TXBF_31_L___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_31_L___S 0 + +#define PHYA_TXBF_TXBF_31_U (0x003C00A4) +#define PHYA_TXBF_TXBF_31_U___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_31_U___POR 0x00000000 +#define PHYA_TXBF_TXBF_31_U__DMA_DESC_TEMPLATE_0_1_1___POR 0x00000000 +#define PHYA_TXBF_TXBF_31_U__DMA_DESC_TEMPLATE_0_1_1___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_31_U__DMA_DESC_TEMPLATE_0_1_1___S 0 +#define PHYA_TXBF_TXBF_31_U___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_31_U___S 0 + +#define PHYA_TXBF_TXBF_32_L (0x003C00A8) +#define PHYA_TXBF_TXBF_32_L___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_32_L___POR 0x00000000 +#define PHYA_TXBF_TXBF_32_L__DMA_DESC_TEMPLATE_0_0_2___POR 0x00000000 +#define PHYA_TXBF_TXBF_32_L__DMA_DESC_TEMPLATE_0_0_2___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_32_L__DMA_DESC_TEMPLATE_0_0_2___S 0 +#define PHYA_TXBF_TXBF_32_L___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_32_L___S 0 + +#define PHYA_TXBF_TXBF_32_U (0x003C00AC) +#define PHYA_TXBF_TXBF_32_U___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_32_U___POR 0x00000000 +#define PHYA_TXBF_TXBF_32_U__DMA_DESC_TEMPLATE_0_1_2___POR 0x00000000 +#define PHYA_TXBF_TXBF_32_U__DMA_DESC_TEMPLATE_0_1_2___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_32_U__DMA_DESC_TEMPLATE_0_1_2___S 0 +#define PHYA_TXBF_TXBF_32_U___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_32_U___S 0 + +#define PHYA_TXBF_TXBF_40_L (0x003C00B0) +#define PHYA_TXBF_TXBF_40_L___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_40_L___POR 0x00000000 +#define PHYA_TXBF_TXBF_40_L__DMA_DESC_TEMPLATE_1_0_0___POR 0x00000000 +#define PHYA_TXBF_TXBF_40_L__DMA_DESC_TEMPLATE_1_0_0___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_40_L__DMA_DESC_TEMPLATE_1_0_0___S 0 +#define PHYA_TXBF_TXBF_40_L___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_40_L___S 0 + +#define PHYA_TXBF_TXBF_40_U (0x003C00B4) +#define PHYA_TXBF_TXBF_40_U___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_40_U___POR 0x00000000 +#define PHYA_TXBF_TXBF_40_U__DMA_DESC_TEMPLATE_1_1_0___POR 0x00000000 +#define PHYA_TXBF_TXBF_40_U__DMA_DESC_TEMPLATE_1_1_0___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_40_U__DMA_DESC_TEMPLATE_1_1_0___S 0 +#define PHYA_TXBF_TXBF_40_U___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_40_U___S 0 + +#define PHYA_TXBF_TXBF_41_L (0x003C00B8) +#define PHYA_TXBF_TXBF_41_L___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_41_L___POR 0x00000000 +#define PHYA_TXBF_TXBF_41_L__DMA_DESC_TEMPLATE_1_0_1___POR 0x00000000 +#define PHYA_TXBF_TXBF_41_L__DMA_DESC_TEMPLATE_1_0_1___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_41_L__DMA_DESC_TEMPLATE_1_0_1___S 0 +#define PHYA_TXBF_TXBF_41_L___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_41_L___S 0 + +#define PHYA_TXBF_TXBF_41_U (0x003C00BC) +#define PHYA_TXBF_TXBF_41_U___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_41_U___POR 0x00000000 +#define PHYA_TXBF_TXBF_41_U__DMA_DESC_TEMPLATE_1_1_1___POR 0x00000000 +#define PHYA_TXBF_TXBF_41_U__DMA_DESC_TEMPLATE_1_1_1___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_41_U__DMA_DESC_TEMPLATE_1_1_1___S 0 +#define PHYA_TXBF_TXBF_41_U___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_41_U___S 0 + +#define PHYA_TXBF_TXBF_42_L (0x003C00C0) +#define PHYA_TXBF_TXBF_42_L___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_42_L___POR 0x00000000 +#define PHYA_TXBF_TXBF_42_L__DMA_DESC_TEMPLATE_1_0_2___POR 0x00000000 +#define PHYA_TXBF_TXBF_42_L__DMA_DESC_TEMPLATE_1_0_2___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_42_L__DMA_DESC_TEMPLATE_1_0_2___S 0 +#define PHYA_TXBF_TXBF_42_L___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_42_L___S 0 + +#define PHYA_TXBF_TXBF_42_U (0x003C00C4) +#define PHYA_TXBF_TXBF_42_U___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_42_U___POR 0x00000000 +#define PHYA_TXBF_TXBF_42_U__DMA_DESC_TEMPLATE_1_1_2___POR 0x00000000 +#define PHYA_TXBF_TXBF_42_U__DMA_DESC_TEMPLATE_1_1_2___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_42_U__DMA_DESC_TEMPLATE_1_1_2___S 0 +#define PHYA_TXBF_TXBF_42_U___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_42_U___S 0 + +#define PHYA_TXBF_TXBF_50_L (0x003C00C8) +#define PHYA_TXBF_TXBF_50_L___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_50_L___POR 0x00000000 +#define PHYA_TXBF_TXBF_50_L__PREFETCH_CV_DESC_TEMPLATE_0_0___POR 0x00000000 +#define PHYA_TXBF_TXBF_50_L__PREFETCH_CV_DESC_TEMPLATE_0_0___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_50_L__PREFETCH_CV_DESC_TEMPLATE_0_0___S 0 +#define PHYA_TXBF_TXBF_50_L___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_50_L___S 0 + +#define PHYA_TXBF_TXBF_50_U (0x003C00CC) +#define PHYA_TXBF_TXBF_50_U___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_50_U___POR 0x00000000 +#define PHYA_TXBF_TXBF_50_U__PREFETCH_CV_DESC_TEMPLATE_1_0___POR 0x00000000 +#define PHYA_TXBF_TXBF_50_U__PREFETCH_CV_DESC_TEMPLATE_1_0___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_50_U__PREFETCH_CV_DESC_TEMPLATE_1_0___S 0 +#define PHYA_TXBF_TXBF_50_U___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_50_U___S 0 + +#define PHYA_TXBF_TXBF_51_L (0x003C00D0) +#define PHYA_TXBF_TXBF_51_L___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_51_L___POR 0x00000000 +#define PHYA_TXBF_TXBF_51_L__PREFETCH_CV_DESC_TEMPLATE_0_1___POR 0x00000000 +#define PHYA_TXBF_TXBF_51_L__PREFETCH_CV_DESC_TEMPLATE_0_1___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_51_L__PREFETCH_CV_DESC_TEMPLATE_0_1___S 0 +#define PHYA_TXBF_TXBF_51_L___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_51_L___S 0 + +#define PHYA_TXBF_TXBF_51_U (0x003C00D4) +#define PHYA_TXBF_TXBF_51_U___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_51_U___POR 0x00000000 +#define PHYA_TXBF_TXBF_51_U__PREFETCH_CV_DESC_TEMPLATE_1_1___POR 0x00000000 +#define PHYA_TXBF_TXBF_51_U__PREFETCH_CV_DESC_TEMPLATE_1_1___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_51_U__PREFETCH_CV_DESC_TEMPLATE_1_1___S 0 +#define PHYA_TXBF_TXBF_51_U___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_51_U___S 0 + +#define PHYA_TXBF_TXBF_52_L (0x003C00D8) +#define PHYA_TXBF_TXBF_52_L___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_52_L___POR 0x00000000 +#define PHYA_TXBF_TXBF_52_L__PREFETCH_CV_DESC_TEMPLATE_0_2___POR 0x00000000 +#define PHYA_TXBF_TXBF_52_L__PREFETCH_CV_DESC_TEMPLATE_0_2___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_52_L__PREFETCH_CV_DESC_TEMPLATE_0_2___S 0 +#define PHYA_TXBF_TXBF_52_L___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_52_L___S 0 + +#define PHYA_TXBF_TXBF_52_U (0x003C00DC) +#define PHYA_TXBF_TXBF_52_U___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_52_U___POR 0x00000000 +#define PHYA_TXBF_TXBF_52_U__PREFETCH_CV_DESC_TEMPLATE_1_2___POR 0x00000000 +#define PHYA_TXBF_TXBF_52_U__PREFETCH_CV_DESC_TEMPLATE_1_2___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_52_U__PREFETCH_CV_DESC_TEMPLATE_1_2___S 0 +#define PHYA_TXBF_TXBF_52_U___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_52_U___S 0 + +#define PHYA_TXBF_TXBF_60_L (0x003C00E0) +#define PHYA_TXBF_TXBF_60_L___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_60_L___POR 0x00000000 +#define PHYA_TXBF_TXBF_60_L__PREFETCH_CV_DESC_TEMPLATE_LAST_0_0___POR 0x00000000 +#define PHYA_TXBF_TXBF_60_L__PREFETCH_CV_DESC_TEMPLATE_LAST_0_0___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_60_L__PREFETCH_CV_DESC_TEMPLATE_LAST_0_0___S 0 +#define PHYA_TXBF_TXBF_60_L___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_60_L___S 0 + +#define PHYA_TXBF_TXBF_60_U (0x003C00E4) +#define PHYA_TXBF_TXBF_60_U___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_60_U___POR 0x00000000 +#define PHYA_TXBF_TXBF_60_U__PREFETCH_CV_DESC_TEMPLATE_LAST_1_0___POR 0x00000000 +#define PHYA_TXBF_TXBF_60_U__PREFETCH_CV_DESC_TEMPLATE_LAST_1_0___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_60_U__PREFETCH_CV_DESC_TEMPLATE_LAST_1_0___S 0 +#define PHYA_TXBF_TXBF_60_U___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_60_U___S 0 + +#define PHYA_TXBF_TXBF_61_L (0x003C00E8) +#define PHYA_TXBF_TXBF_61_L___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_61_L___POR 0x00000000 +#define PHYA_TXBF_TXBF_61_L__PREFETCH_CV_DESC_TEMPLATE_LAST_0_1___POR 0x00000000 +#define PHYA_TXBF_TXBF_61_L__PREFETCH_CV_DESC_TEMPLATE_LAST_0_1___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_61_L__PREFETCH_CV_DESC_TEMPLATE_LAST_0_1___S 0 +#define PHYA_TXBF_TXBF_61_L___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_61_L___S 0 + +#define PHYA_TXBF_TXBF_61_U (0x003C00EC) +#define PHYA_TXBF_TXBF_61_U___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_61_U___POR 0x00000000 +#define PHYA_TXBF_TXBF_61_U__PREFETCH_CV_DESC_TEMPLATE_LAST_1_1___POR 0x00000000 +#define PHYA_TXBF_TXBF_61_U__PREFETCH_CV_DESC_TEMPLATE_LAST_1_1___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_61_U__PREFETCH_CV_DESC_TEMPLATE_LAST_1_1___S 0 +#define PHYA_TXBF_TXBF_61_U___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_61_U___S 0 + +#define PHYA_TXBF_TXBF_62_L (0x003C00F0) +#define PHYA_TXBF_TXBF_62_L___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_62_L___POR 0x00000000 +#define PHYA_TXBF_TXBF_62_L__PREFETCH_CV_DESC_TEMPLATE_LAST_0_2___POR 0x00000000 +#define PHYA_TXBF_TXBF_62_L__PREFETCH_CV_DESC_TEMPLATE_LAST_0_2___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_62_L__PREFETCH_CV_DESC_TEMPLATE_LAST_0_2___S 0 +#define PHYA_TXBF_TXBF_62_L___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_62_L___S 0 + +#define PHYA_TXBF_TXBF_62_U (0x003C00F4) +#define PHYA_TXBF_TXBF_62_U___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_62_U___POR 0x00000000 +#define PHYA_TXBF_TXBF_62_U__PREFETCH_CV_DESC_TEMPLATE_LAST_1_2___POR 0x00000000 +#define PHYA_TXBF_TXBF_62_U__PREFETCH_CV_DESC_TEMPLATE_LAST_1_2___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_62_U__PREFETCH_CV_DESC_TEMPLATE_LAST_1_2___S 0 +#define PHYA_TXBF_TXBF_62_U___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_62_U___S 0 + +#define PHYA_TXBF_TXBF_7_L (0x003C00F8) +#define PHYA_TXBF_TXBF_7_L___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_7_L___POR 0x00000100 +#define PHYA_TXBF_TXBF_7_L__PREFETCH_HW_ACC_EN___POR 0x1 +#define PHYA_TXBF_TXBF_7_L__PREFETCH_CV_TRIGGER_THRESHOLD___POR 0x0 +#define PHYA_TXBF_TXBF_7_L__PREFETCH_HW_ACC_EN___M 0x00000100 +#define PHYA_TXBF_TXBF_7_L__PREFETCH_HW_ACC_EN___S 8 +#define PHYA_TXBF_TXBF_7_L__PREFETCH_CV_TRIGGER_THRESHOLD___M 0x0000000F +#define PHYA_TXBF_TXBF_7_L__PREFETCH_CV_TRIGGER_THRESHOLD___S 0 +#define PHYA_TXBF_TXBF_7_L___M 0x0000010F +#define PHYA_TXBF_TXBF_7_L___S 0 + +#define PHYA_TXBF_TXBF_7_U (0x003C00FC) +#define PHYA_TXBF_TXBF_7_U___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_7_U___POR 0x00000014 +#define PHYA_TXBF_TXBF_7_U__TXBF_QRE_ALPHA___POR 0x00014 +#define PHYA_TXBF_TXBF_7_U__TXBF_QRE_ALPHA___M 0x000FFFFF +#define PHYA_TXBF_TXBF_7_U__TXBF_QRE_ALPHA___S 0 +#define PHYA_TXBF_TXBF_7_U___M 0x000FFFFF +#define PHYA_TXBF_TXBF_7_U___S 0 + +#define PHYA_TXBF_TXBF_8_L (0x003C0100) +#define PHYA_TXBF_TXBF_8_L___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_8_L___POR 0x00000000 +#define PHYA_TXBF_TXBF_8_L__SW_SCRATCH_OVERRIDE_MODE___POR 0x0 +#define PHYA_TXBF_TXBF_8_L__SW_WT_OVERRIDE_MODE___POR 0x0 +#define PHYA_TXBF_TXBF_8_L__SW_SCRATCH_OVERRIDE_MODE___M 0x00000100 +#define PHYA_TXBF_TXBF_8_L__SW_SCRATCH_OVERRIDE_MODE___S 8 +#define PHYA_TXBF_TXBF_8_L__SW_WT_OVERRIDE_MODE___M 0x00000001 +#define PHYA_TXBF_TXBF_8_L__SW_WT_OVERRIDE_MODE___S 0 +#define PHYA_TXBF_TXBF_8_L___M 0x00000101 +#define PHYA_TXBF_TXBF_8_L___S 0 + +#define PHYA_TXBF_TXBF_TONE_MAP_LUT_L_n(n) (0x003C0108+0x8*(n)) +#define PHYA_TXBF_TXBF_TONE_MAP_LUT_L_n_nMIN 0 +#define PHYA_TXBF_TXBF_TONE_MAP_LUT_L_n_nMAX 0 +#define PHYA_TXBF_TXBF_TONE_MAP_LUT_L_n_ELEM 1 +#define PHYA_TXBF_TXBF_TONE_MAP_LUT_L_n___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_TONE_MAP_LUT_L_n___POR 0x00000000 +#define PHYA_TXBF_TXBF_TONE_MAP_LUT_L_n__TXBF_TONE_MAP_LUT_0___POR 0x00000000 +#define PHYA_TXBF_TXBF_TONE_MAP_LUT_L_n__TXBF_TONE_MAP_LUT_0___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_TONE_MAP_LUT_L_n__TXBF_TONE_MAP_LUT_0___S 0 +#define PHYA_TXBF_TXBF_TONE_MAP_LUT_L_n___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_TONE_MAP_LUT_L_n___S 0 +#define PHYA_TXBF_TXBF_TONE_MAP_LUT_L_0 (0x003C0108) +#define PHYA_TXBF_TXBF_TONE_MAP_LUT_L_0___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_TONE_MAP_LUT_L_0__TXBF_TONE_MAP_LUT_0___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_TONE_MAP_LUT_L_0__TXBF_TONE_MAP_LUT_0___S 0 + +#define PHYA_TXBF_TXBF_TONE_MAP_LUT_U_n(n) (0x003C010C+0x8*(n)) +#define PHYA_TXBF_TXBF_TONE_MAP_LUT_U_n_nMIN 0 +#define PHYA_TXBF_TXBF_TONE_MAP_LUT_U_n_nMAX 0 +#define PHYA_TXBF_TXBF_TONE_MAP_LUT_U_n_ELEM 1 +#define PHYA_TXBF_TXBF_TONE_MAP_LUT_U_n___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_TONE_MAP_LUT_U_n___POR 0x00000000 +#define PHYA_TXBF_TXBF_TONE_MAP_LUT_U_n__TXBF_TONE_MAP_LUT_1___POR 0x00000000 +#define PHYA_TXBF_TXBF_TONE_MAP_LUT_U_n__TXBF_TONE_MAP_LUT_1___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_TONE_MAP_LUT_U_n__TXBF_TONE_MAP_LUT_1___S 0 +#define PHYA_TXBF_TXBF_TONE_MAP_LUT_U_n___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_TONE_MAP_LUT_U_n___S 0 +#define PHYA_TXBF_TXBF_TONE_MAP_LUT_U_0 (0x003C010C) +#define PHYA_TXBF_TXBF_TONE_MAP_LUT_U_0___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_TONE_MAP_LUT_U_0__TXBF_TONE_MAP_LUT_1___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_TONE_MAP_LUT_U_0__TXBF_TONE_MAP_LUT_1___S 0 + +#define PHYA_TXBF_VSMOOTH_COEFF_0_L (0x003C1108) +#define PHYA_TXBF_VSMOOTH_COEFF_0_L___RWC QCSR_REG_RW +#define PHYA_TXBF_VSMOOTH_COEFF_0_L___POR 0x110C1704 +#define PHYA_TXBF_VSMOOTH_COEFF_0_L__VSMOOTH_11AX_COEFF_3___POR 0x11 +#define PHYA_TXBF_VSMOOTH_COEFF_0_L__VSMOOTH_11AX_COEFF_2___POR 0x0C +#define PHYA_TXBF_VSMOOTH_COEFF_0_L__VSMOOTH_11AX_COEFF_1___POR 0x17 +#define PHYA_TXBF_VSMOOTH_COEFF_0_L__VSMOOTH_11AX_COEFF_0___POR 0x04 +#define PHYA_TXBF_VSMOOTH_COEFF_0_L__VSMOOTH_11AX_COEFF_3___M 0xFF000000 +#define PHYA_TXBF_VSMOOTH_COEFF_0_L__VSMOOTH_11AX_COEFF_3___S 24 +#define PHYA_TXBF_VSMOOTH_COEFF_0_L__VSMOOTH_11AX_COEFF_2___M 0x00FF0000 +#define PHYA_TXBF_VSMOOTH_COEFF_0_L__VSMOOTH_11AX_COEFF_2___S 16 +#define PHYA_TXBF_VSMOOTH_COEFF_0_L__VSMOOTH_11AX_COEFF_1___M 0x0000FF00 +#define PHYA_TXBF_VSMOOTH_COEFF_0_L__VSMOOTH_11AX_COEFF_1___S 8 +#define PHYA_TXBF_VSMOOTH_COEFF_0_L__VSMOOTH_11AX_COEFF_0___M 0x000000FF +#define PHYA_TXBF_VSMOOTH_COEFF_0_L__VSMOOTH_11AX_COEFF_0___S 0 +#define PHYA_TXBF_VSMOOTH_COEFF_0_L___M 0xFFFFFFFF +#define PHYA_TXBF_VSMOOTH_COEFF_0_L___S 0 + +#define PHYA_TXBF_VSMOOTH_COEFF_0_U (0x003C110C) +#define PHYA_TXBF_VSMOOTH_COEFF_0_U___RWC QCSR_REG_RW +#define PHYA_TXBF_VSMOOTH_COEFF_0_U___POR 0x00000011 +#define PHYA_TXBF_VSMOOTH_COEFF_0_U__VSMOOTH_11AX_COEFF_4___POR 0x11 +#define PHYA_TXBF_VSMOOTH_COEFF_0_U__VSMOOTH_11AX_COEFF_4___M 0x000000FF +#define PHYA_TXBF_VSMOOTH_COEFF_0_U__VSMOOTH_11AX_COEFF_4___S 0 +#define PHYA_TXBF_VSMOOTH_COEFF_0_U___M 0x000000FF +#define PHYA_TXBF_VSMOOTH_COEFF_0_U___S 0 + +#define PHYA_TXBF_VSMOOTH_COEFF_1_L (0x003C1110) +#define PHYA_TXBF_VSMOOTH_COEFF_1_L___RWC QCSR_REG_RW +#define PHYA_TXBF_VSMOOTH_COEFF_1_L___POR 0x271301EF +#define PHYA_TXBF_VSMOOTH_COEFF_1_L__VSMOOTH_11AC_COEFF_3___POR 0x27 +#define PHYA_TXBF_VSMOOTH_COEFF_1_L__VSMOOTH_11AC_COEFF_2___POR 0x13 +#define PHYA_TXBF_VSMOOTH_COEFF_1_L__VSMOOTH_11AC_COEFF_1___POR 0x01 +#define PHYA_TXBF_VSMOOTH_COEFF_1_L__VSMOOTH_11AC_COEFF_0___POR 0xEF +#define PHYA_TXBF_VSMOOTH_COEFF_1_L__VSMOOTH_11AC_COEFF_3___M 0xFF000000 +#define PHYA_TXBF_VSMOOTH_COEFF_1_L__VSMOOTH_11AC_COEFF_3___S 24 +#define PHYA_TXBF_VSMOOTH_COEFF_1_L__VSMOOTH_11AC_COEFF_2___M 0x00FF0000 +#define PHYA_TXBF_VSMOOTH_COEFF_1_L__VSMOOTH_11AC_COEFF_2___S 16 +#define PHYA_TXBF_VSMOOTH_COEFF_1_L__VSMOOTH_11AC_COEFF_1___M 0x0000FF00 +#define PHYA_TXBF_VSMOOTH_COEFF_1_L__VSMOOTH_11AC_COEFF_1___S 8 +#define PHYA_TXBF_VSMOOTH_COEFF_1_L__VSMOOTH_11AC_COEFF_0___M 0x000000FF +#define PHYA_TXBF_VSMOOTH_COEFF_1_L__VSMOOTH_11AC_COEFF_0___S 0 +#define PHYA_TXBF_VSMOOTH_COEFF_1_L___M 0xFFFFFFFF +#define PHYA_TXBF_VSMOOTH_COEFF_1_L___S 0 + +#define PHYA_TXBF_VSMOOTH_COEFF_1_U (0x003C1114) +#define PHYA_TXBF_VSMOOTH_COEFF_1_U___RWC QCSR_REG_RW +#define PHYA_TXBF_VSMOOTH_COEFF_1_U___POR 0x0000002F +#define PHYA_TXBF_VSMOOTH_COEFF_1_U__VSMOOTH_11AC_COEFF_4___POR 0x2F +#define PHYA_TXBF_VSMOOTH_COEFF_1_U__VSMOOTH_11AC_COEFF_4___M 0x000000FF +#define PHYA_TXBF_VSMOOTH_COEFF_1_U__VSMOOTH_11AC_COEFF_4___S 0 +#define PHYA_TXBF_VSMOOTH_COEFF_1_U___M 0x000000FF +#define PHYA_TXBF_VSMOOTH_COEFF_1_U___S 0 + +#define PHYA_TXBF_VSMOOTH_COEFF_2_L (0x003C1118) +#define PHYA_TXBF_VSMOOTH_COEFF_2_L___RWC QCSR_REG_RW +#define PHYA_TXBF_VSMOOTH_COEFF_2_L___POR 0x02710000 +#define PHYA_TXBF_VSMOOTH_COEFF_2_L__PARTIAL_PREFETCH_DONE_INTR_NUM_DWS_REMAINING_THRESHOLD___POR 0x0271 +#define PHYA_TXBF_VSMOOTH_COEFF_2_L__DISABLE_CV_PREFETCH_OPT___POR 0x0 +#define PHYA_TXBF_VSMOOTH_COEFF_2_L__PARTIAL_PREFETCH_DONE_INTR_NUM_DWS_REMAINING_THRESHOLD___M 0xFFFF0000 +#define PHYA_TXBF_VSMOOTH_COEFF_2_L__PARTIAL_PREFETCH_DONE_INTR_NUM_DWS_REMAINING_THRESHOLD___S 16 +#define PHYA_TXBF_VSMOOTH_COEFF_2_L__DISABLE_CV_PREFETCH_OPT___M 0x00000001 +#define PHYA_TXBF_VSMOOTH_COEFF_2_L__DISABLE_CV_PREFETCH_OPT___S 0 +#define PHYA_TXBF_VSMOOTH_COEFF_2_L___M 0xFFFF0001 +#define PHYA_TXBF_VSMOOTH_COEFF_2_L___S 0 + +#define PHYA_TXBF_VSMOOTH_COEFF_2_U (0x003C111C) +#define PHYA_TXBF_VSMOOTH_COEFF_2_U___RWC QCSR_REG_RW +#define PHYA_TXBF_VSMOOTH_COEFF_2_U___POR 0x00000280 +#define PHYA_TXBF_VSMOOTH_COEFF_2_U__PRECODING_STG1_STG2_WAIT_TIMEOUT___POR 0x00000280 +#define PHYA_TXBF_VSMOOTH_COEFF_2_U__PRECODING_STG1_STG2_WAIT_TIMEOUT___M 0xFFFFFFFF +#define PHYA_TXBF_VSMOOTH_COEFF_2_U__PRECODING_STG1_STG2_WAIT_TIMEOUT___S 0 +#define PHYA_TXBF_VSMOOTH_COEFF_2_U___M 0xFFFFFFFF +#define PHYA_TXBF_VSMOOTH_COEFF_2_U___S 0 + +#define PHYA_TXBF_FW_DMA_L (0x003C1120) +#define PHYA_TXBF_FW_DMA_L___RWC QCSR_REG_RW +#define PHYA_TXBF_FW_DMA_L___POR 0x00000000 +#define PHYA_TXBF_FW_DMA_L__FW_DDR_TRANSFER_ONGOING___POR 0x0 +#define PHYA_TXBF_FW_DMA_L__FW_INIT_DMA___POR 0x0 +#define PHYA_TXBF_FW_DMA_L__FW_DDR_TRANSFER_ONGOING___M 0x00000100 +#define PHYA_TXBF_FW_DMA_L__FW_DDR_TRANSFER_ONGOING___S 8 +#define PHYA_TXBF_FW_DMA_L__FW_INIT_DMA___M 0x00000001 +#define PHYA_TXBF_FW_DMA_L__FW_INIT_DMA___S 0 +#define PHYA_TXBF_FW_DMA_L___M 0x00000101 +#define PHYA_TXBF_FW_DMA_L___S 0 + +#define PHYA_TXBF_HW_ACC_RST_L (0x003C1128) +#define PHYA_TXBF_HW_ACC_RST_L___RWC QCSR_REG_WO +#define PHYA_TXBF_HW_ACC_RST_L___POR 0x00000000 +#define PHYA_TXBF_HW_ACC_RST_L__PREFETCH_HW_ACC_RST___POR 0x0 +#define PHYA_TXBF_HW_ACC_RST_L__CBF_HW_ACC_RST___POR 0x0 +#define PHYA_TXBF_HW_ACC_RST_L__TXBFP_HW_ACC_RST___POR 0x0 +#define PHYA_TXBF_HW_ACC_RST_L__PREFETCH_HW_ACC_RST___M 0x00010000 +#define PHYA_TXBF_HW_ACC_RST_L__PREFETCH_HW_ACC_RST___S 16 +#define PHYA_TXBF_HW_ACC_RST_L__CBF_HW_ACC_RST___M 0x00000100 +#define PHYA_TXBF_HW_ACC_RST_L__CBF_HW_ACC_RST___S 8 +#define PHYA_TXBF_HW_ACC_RST_L__TXBFP_HW_ACC_RST___M 0x00000001 +#define PHYA_TXBF_HW_ACC_RST_L__TXBFP_HW_ACC_RST___S 0 +#define PHYA_TXBF_HW_ACC_RST_L___M 0x00010101 +#define PHYA_TXBF_HW_ACC_RST_L___S 0 + +#define PHYA_TXBF_TXBF_WEIGHTS_MEMORY_L_n(n) (0x003C1130+0x8*(n)) +#define PHYA_TXBF_TXBF_WEIGHTS_MEMORY_L_n_nMIN 0 +#define PHYA_TXBF_TXBF_WEIGHTS_MEMORY_L_n_nMAX 0 +#define PHYA_TXBF_TXBF_WEIGHTS_MEMORY_L_n_ELEM 1 +#define PHYA_TXBF_TXBF_WEIGHTS_MEMORY_L_n___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_WEIGHTS_MEMORY_L_n___POR 0x00000000 +#define PHYA_TXBF_TXBF_WEIGHTS_MEMORY_L_n__TXBF_WEIGHTS_MEMORY_0___POR 0x00000000 +#define PHYA_TXBF_TXBF_WEIGHTS_MEMORY_L_n__TXBF_WEIGHTS_MEMORY_0___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_WEIGHTS_MEMORY_L_n__TXBF_WEIGHTS_MEMORY_0___S 0 +#define PHYA_TXBF_TXBF_WEIGHTS_MEMORY_L_n___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_WEIGHTS_MEMORY_L_n___S 0 +#define PHYA_TXBF_TXBF_WEIGHTS_MEMORY_L_0 (0x003C1130) +#define PHYA_TXBF_TXBF_WEIGHTS_MEMORY_L_0___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_WEIGHTS_MEMORY_L_0__TXBF_WEIGHTS_MEMORY_0___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_WEIGHTS_MEMORY_L_0__TXBF_WEIGHTS_MEMORY_0___S 0 + +#define PHYA_TXBF_TXBF_WEIGHTS_MEMORY_U_n(n) (0x003C1134+0x8*(n)) +#define PHYA_TXBF_TXBF_WEIGHTS_MEMORY_U_n_nMIN 0 +#define PHYA_TXBF_TXBF_WEIGHTS_MEMORY_U_n_nMAX 0 +#define PHYA_TXBF_TXBF_WEIGHTS_MEMORY_U_n_ELEM 1 +#define PHYA_TXBF_TXBF_WEIGHTS_MEMORY_U_n___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_WEIGHTS_MEMORY_U_n___POR 0x00000000 +#define PHYA_TXBF_TXBF_WEIGHTS_MEMORY_U_n__TXBF_WEIGHTS_MEMORY_1___POR 0x00000000 +#define PHYA_TXBF_TXBF_WEIGHTS_MEMORY_U_n__TXBF_WEIGHTS_MEMORY_1___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_WEIGHTS_MEMORY_U_n__TXBF_WEIGHTS_MEMORY_1___S 0 +#define PHYA_TXBF_TXBF_WEIGHTS_MEMORY_U_n___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_WEIGHTS_MEMORY_U_n___S 0 +#define PHYA_TXBF_TXBF_WEIGHTS_MEMORY_U_0 (0x003C1134) +#define PHYA_TXBF_TXBF_WEIGHTS_MEMORY_U_0___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_WEIGHTS_MEMORY_U_0__TXBF_WEIGHTS_MEMORY_1___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_WEIGHTS_MEMORY_U_0__TXBF_WEIGHTS_MEMORY_1___S 0 + +#define PHYA_TXBF_TXBF_CV_MEMORY_L_n(n) (0x003D9130+0x8*(n)) +#define PHYA_TXBF_TXBF_CV_MEMORY_L_n_nMIN 0 +#define PHYA_TXBF_TXBF_CV_MEMORY_L_n_nMAX 0 +#define PHYA_TXBF_TXBF_CV_MEMORY_L_n_ELEM 1 +#define PHYA_TXBF_TXBF_CV_MEMORY_L_n___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_CV_MEMORY_L_n___POR 0x00000000 +#define PHYA_TXBF_TXBF_CV_MEMORY_L_n__TXBF_CV_MEMORY_0___POR 0x00000000 +#define PHYA_TXBF_TXBF_CV_MEMORY_L_n__TXBF_CV_MEMORY_0___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_CV_MEMORY_L_n__TXBF_CV_MEMORY_0___S 0 +#define PHYA_TXBF_TXBF_CV_MEMORY_L_n___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_CV_MEMORY_L_n___S 0 +#define PHYA_TXBF_TXBF_CV_MEMORY_L_0 (0x003D9130) +#define PHYA_TXBF_TXBF_CV_MEMORY_L_0___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_CV_MEMORY_L_0__TXBF_CV_MEMORY_0___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_CV_MEMORY_L_0__TXBF_CV_MEMORY_0___S 0 + +#define PHYA_TXBF_TXBF_CV_MEMORY_U_n(n) (0x003D9134+0x8*(n)) +#define PHYA_TXBF_TXBF_CV_MEMORY_U_n_nMIN 0 +#define PHYA_TXBF_TXBF_CV_MEMORY_U_n_nMAX 0 +#define PHYA_TXBF_TXBF_CV_MEMORY_U_n_ELEM 1 +#define PHYA_TXBF_TXBF_CV_MEMORY_U_n___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_CV_MEMORY_U_n___POR 0x00000000 +#define PHYA_TXBF_TXBF_CV_MEMORY_U_n__TXBF_CV_MEMORY_1___POR 0x00000000 +#define PHYA_TXBF_TXBF_CV_MEMORY_U_n__TXBF_CV_MEMORY_1___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_CV_MEMORY_U_n__TXBF_CV_MEMORY_1___S 0 +#define PHYA_TXBF_TXBF_CV_MEMORY_U_n___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_CV_MEMORY_U_n___S 0 +#define PHYA_TXBF_TXBF_CV_MEMORY_U_0 (0x003D9134) +#define PHYA_TXBF_TXBF_CV_MEMORY_U_0___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_CV_MEMORY_U_0__TXBF_CV_MEMORY_1___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_CV_MEMORY_U_0__TXBF_CV_MEMORY_1___S 0 + +#define PHYA_TXBF_TXBF_SCRATCH_MEMORY_L_n(n) (0x003E5050+0x8*(n)) +#define PHYA_TXBF_TXBF_SCRATCH_MEMORY_L_n_nMIN 0 +#define PHYA_TXBF_TXBF_SCRATCH_MEMORY_L_n_nMAX 0 +#define PHYA_TXBF_TXBF_SCRATCH_MEMORY_L_n_ELEM 1 +#define PHYA_TXBF_TXBF_SCRATCH_MEMORY_L_n___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_SCRATCH_MEMORY_L_n___POR 0x00000000 +#define PHYA_TXBF_TXBF_SCRATCH_MEMORY_L_n__TXBF_SCRATCH_MEMORY_0___POR 0x00000000 +#define PHYA_TXBF_TXBF_SCRATCH_MEMORY_L_n__TXBF_SCRATCH_MEMORY_0___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_SCRATCH_MEMORY_L_n__TXBF_SCRATCH_MEMORY_0___S 0 +#define PHYA_TXBF_TXBF_SCRATCH_MEMORY_L_n___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_SCRATCH_MEMORY_L_n___S 0 +#define PHYA_TXBF_TXBF_SCRATCH_MEMORY_L_0 (0x003E5050) +#define PHYA_TXBF_TXBF_SCRATCH_MEMORY_L_0___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_SCRATCH_MEMORY_L_0__TXBF_SCRATCH_MEMORY_0___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_SCRATCH_MEMORY_L_0__TXBF_SCRATCH_MEMORY_0___S 0 + +#define PHYA_TXBF_TXBF_SCRATCH_MEMORY_U_n(n) (0x003E5054+0x8*(n)) +#define PHYA_TXBF_TXBF_SCRATCH_MEMORY_U_n_nMIN 0 +#define PHYA_TXBF_TXBF_SCRATCH_MEMORY_U_n_nMAX 0 +#define PHYA_TXBF_TXBF_SCRATCH_MEMORY_U_n_ELEM 1 +#define PHYA_TXBF_TXBF_SCRATCH_MEMORY_U_n___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_SCRATCH_MEMORY_U_n___POR 0x00000000 +#define PHYA_TXBF_TXBF_SCRATCH_MEMORY_U_n__TXBF_SCRATCH_MEMORY_1___POR 0x00000000 +#define PHYA_TXBF_TXBF_SCRATCH_MEMORY_U_n__TXBF_SCRATCH_MEMORY_1___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_SCRATCH_MEMORY_U_n__TXBF_SCRATCH_MEMORY_1___S 0 +#define PHYA_TXBF_TXBF_SCRATCH_MEMORY_U_n___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_SCRATCH_MEMORY_U_n___S 0 +#define PHYA_TXBF_TXBF_SCRATCH_MEMORY_U_0 (0x003E5054) +#define PHYA_TXBF_TXBF_SCRATCH_MEMORY_U_0___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_SCRATCH_MEMORY_U_0__TXBF_SCRATCH_MEMORY_1___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_SCRATCH_MEMORY_U_0__TXBF_SCRATCH_MEMORY_1___S 0 + +#define PHYA_TXBF_PUBLIC_SPARE_L (0x003FB050) +#define PHYA_TXBF_PUBLIC_SPARE_L___RWC QCSR_REG_RW +#define PHYA_TXBF_PUBLIC_SPARE_L___POR 0x00000000 +#define PHYA_TXBF_PUBLIC_SPARE_L__PUBLIC_SPARE_0___POR 0x00000000 +#define PHYA_TXBF_PUBLIC_SPARE_L__PUBLIC_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXBF_PUBLIC_SPARE_L__PUBLIC_SPARE_0___S 0 +#define PHYA_TXBF_PUBLIC_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXBF_PUBLIC_SPARE_L___S 0 + +#define PHYA_TXBF_PUBLIC_SPARE_U (0x003FB054) +#define PHYA_TXBF_PUBLIC_SPARE_U___RWC QCSR_REG_RW +#define PHYA_TXBF_PUBLIC_SPARE_U___POR 0x00000000 +#define PHYA_TXBF_PUBLIC_SPARE_U__PUBLIC_SPARE_1___POR 0x00000000 +#define PHYA_TXBF_PUBLIC_SPARE_U__PUBLIC_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXBF_PUBLIC_SPARE_U__PUBLIC_SPARE_1___S 0 +#define PHYA_TXBF_PUBLIC_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXBF_PUBLIC_SPARE_U___S 0 + +#define PHYA_TXBF_PRIVATE_SPARE_L (0x003FB058) +#define PHYA_TXBF_PRIVATE_SPARE_L___RWC QCSR_REG_RW +#define PHYA_TXBF_PRIVATE_SPARE_L___POR 0x00000000 +#define PHYA_TXBF_PRIVATE_SPARE_L__PRIVATE_SPARE_0___POR 0x00000000 +#define PHYA_TXBF_PRIVATE_SPARE_L__PRIVATE_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXBF_PRIVATE_SPARE_L__PRIVATE_SPARE_0___S 0 +#define PHYA_TXBF_PRIVATE_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXBF_PRIVATE_SPARE_L___S 0 + +#define PHYA_TXBF_PRIVATE_SPARE_U (0x003FB05C) +#define PHYA_TXBF_PRIVATE_SPARE_U___RWC QCSR_REG_RW +#define PHYA_TXBF_PRIVATE_SPARE_U___POR 0x00000000 +#define PHYA_TXBF_PRIVATE_SPARE_U__PRIVATE_SPARE_1___POR 0x00000000 +#define PHYA_TXBF_PRIVATE_SPARE_U__PRIVATE_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXBF_PRIVATE_SPARE_U__PRIVATE_SPARE_1___S 0 +#define PHYA_TXBF_PRIVATE_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXBF_PRIVATE_SPARE_U___S 0 + +#define PHYA_TXBF_PREFETCH_CV_DESC_FIFO_L_n(n) (0x003FB060+0x8*(n)) +#define PHYA_TXBF_PREFETCH_CV_DESC_FIFO_L_n_nMIN 0 +#define PHYA_TXBF_PREFETCH_CV_DESC_FIFO_L_n_nMAX 0 +#define PHYA_TXBF_PREFETCH_CV_DESC_FIFO_L_n_ELEM 1 +#define PHYA_TXBF_PREFETCH_CV_DESC_FIFO_L_n___RWC QCSR_REG_RO +#define PHYA_TXBF_PREFETCH_CV_DESC_FIFO_L_n___POR 0x00000000 +#define PHYA_TXBF_PREFETCH_CV_DESC_FIFO_L_n__PREFETCH_CV_DESC_FIFO_0___POR 0x00000000 +#define PHYA_TXBF_PREFETCH_CV_DESC_FIFO_L_n__PREFETCH_CV_DESC_FIFO_0___M 0xFFFFFFFF +#define PHYA_TXBF_PREFETCH_CV_DESC_FIFO_L_n__PREFETCH_CV_DESC_FIFO_0___S 0 +#define PHYA_TXBF_PREFETCH_CV_DESC_FIFO_L_n___M 0xFFFFFFFF +#define PHYA_TXBF_PREFETCH_CV_DESC_FIFO_L_n___S 0 +#define PHYA_TXBF_PREFETCH_CV_DESC_FIFO_L_0 (0x003FB060) +#define PHYA_TXBF_PREFETCH_CV_DESC_FIFO_L_0___RWC QCSR_REG_RO +#define PHYA_TXBF_PREFETCH_CV_DESC_FIFO_L_0__PREFETCH_CV_DESC_FIFO_0___M 0xFFFFFFFF +#define PHYA_TXBF_PREFETCH_CV_DESC_FIFO_L_0__PREFETCH_CV_DESC_FIFO_0___S 0 + +#define PHYA_TXBF_PREFETCH_CV_DESC_FIFO_U_n(n) (0x003FB064+0x8*(n)) +#define PHYA_TXBF_PREFETCH_CV_DESC_FIFO_U_n_nMIN 0 +#define PHYA_TXBF_PREFETCH_CV_DESC_FIFO_U_n_nMAX 0 +#define PHYA_TXBF_PREFETCH_CV_DESC_FIFO_U_n_ELEM 1 +#define PHYA_TXBF_PREFETCH_CV_DESC_FIFO_U_n___RWC QCSR_REG_RO +#define PHYA_TXBF_PREFETCH_CV_DESC_FIFO_U_n___POR 0x00000000 +#define PHYA_TXBF_PREFETCH_CV_DESC_FIFO_U_n__PREFETCH_CV_DESC_FIFO_1___POR 0x00000000 +#define PHYA_TXBF_PREFETCH_CV_DESC_FIFO_U_n__PREFETCH_CV_DESC_FIFO_1___M 0xFFFFFFFF +#define PHYA_TXBF_PREFETCH_CV_DESC_FIFO_U_n__PREFETCH_CV_DESC_FIFO_1___S 0 +#define PHYA_TXBF_PREFETCH_CV_DESC_FIFO_U_n___M 0xFFFFFFFF +#define PHYA_TXBF_PREFETCH_CV_DESC_FIFO_U_n___S 0 +#define PHYA_TXBF_PREFETCH_CV_DESC_FIFO_U_0 (0x003FB064) +#define PHYA_TXBF_PREFETCH_CV_DESC_FIFO_U_0___RWC QCSR_REG_RO +#define PHYA_TXBF_PREFETCH_CV_DESC_FIFO_U_0__PREFETCH_CV_DESC_FIFO_1___M 0xFFFFFFFF +#define PHYA_TXBF_PREFETCH_CV_DESC_FIFO_U_0__PREFETCH_CV_DESC_FIFO_1___S 0 + +#define PHYA_TXBF_ERROR_EVENT_RD_0_L (0x003FB160) +#define PHYA_TXBF_ERROR_EVENT_RD_0_L___RWC QCSR_REG_RO +#define PHYA_TXBF_ERROR_EVENT_RD_0_L___POR 0x00000000 +#define PHYA_TXBF_ERROR_EVENT_RD_0_L__ALL_CBF_DATA_RCVD___POR 0x00000000 +#define PHYA_TXBF_ERROR_EVENT_RD_0_L__ALL_CBF_DATA_RCVD___M 0xFFFFFFFF +#define PHYA_TXBF_ERROR_EVENT_RD_0_L__ALL_CBF_DATA_RCVD___S 0 +#define PHYA_TXBF_ERROR_EVENT_RD_0_L___M 0xFFFFFFFF +#define PHYA_TXBF_ERROR_EVENT_RD_0_L___S 0 + +#define PHYA_TXBF_ERROR_EVENT_RD_0_U (0x003FB164) +#define PHYA_TXBF_ERROR_EVENT_RD_0_U___RWC QCSR_REG_RO +#define PHYA_TXBF_ERROR_EVENT_RD_0_U___POR 0x00000000 +#define PHYA_TXBF_ERROR_EVENT_RD_0_U__CBF_START_RCVD___POR 0x00000000 +#define PHYA_TXBF_ERROR_EVENT_RD_0_U__CBF_START_RCVD___M 0xFFFFFFFF +#define PHYA_TXBF_ERROR_EVENT_RD_0_U__CBF_START_RCVD___S 0 +#define PHYA_TXBF_ERROR_EVENT_RD_0_U___M 0xFFFFFFFF +#define PHYA_TXBF_ERROR_EVENT_RD_0_U___S 0 + +#define PHYA_TXBF_ERROR_EVENT_RD_1_L (0x003FB168) +#define PHYA_TXBF_ERROR_EVENT_RD_1_L___RWC QCSR_REG_RO +#define PHYA_TXBF_ERROR_EVENT_RD_1_L___POR 0x00000000 +#define PHYA_TXBF_ERROR_EVENT_RD_1_L__CBF_DONE_RCVD___POR 0x00000000 +#define PHYA_TXBF_ERROR_EVENT_RD_1_L__CBF_DONE_RCVD___M 0xFFFFFFFF +#define PHYA_TXBF_ERROR_EVENT_RD_1_L__CBF_DONE_RCVD___S 0 +#define PHYA_TXBF_ERROR_EVENT_RD_1_L___M 0xFFFFFFFF +#define PHYA_TXBF_ERROR_EVENT_RD_1_L___S 0 + +#define PHYA_TXBF_ERROR_EVENT_RD_1_U (0x003FB16C) +#define PHYA_TXBF_ERROR_EVENT_RD_1_U___RWC QCSR_REG_RO +#define PHYA_TXBF_ERROR_EVENT_RD_1_U___POR 0x00000000 +#define PHYA_TXBF_ERROR_EVENT_RD_1_U__CBF_FCS_ERROR___POR 0x00000000 +#define PHYA_TXBF_ERROR_EVENT_RD_1_U__CBF_FCS_ERROR___M 0xFFFFFFFF +#define PHYA_TXBF_ERROR_EVENT_RD_1_U__CBF_FCS_ERROR___S 0 +#define PHYA_TXBF_ERROR_EVENT_RD_1_U___M 0xFFFFFFFF +#define PHYA_TXBF_ERROR_EVENT_RD_1_U___S 0 + +#define PHYA_TXBF_ERROR_EVENT_RD_20_L (0x003FB170) +#define PHYA_TXBF_ERROR_EVENT_RD_20_L___RWC QCSR_REG_RO +#define PHYA_TXBF_ERROR_EVENT_RD_20_L___POR 0x00000000 +#define PHYA_TXBF_ERROR_EVENT_RD_20_L__PRECODING_ERROR_INFO_0_0___POR 0x00000000 +#define PHYA_TXBF_ERROR_EVENT_RD_20_L__PRECODING_ERROR_INFO_0_0___M 0xFFFFFFFF +#define PHYA_TXBF_ERROR_EVENT_RD_20_L__PRECODING_ERROR_INFO_0_0___S 0 +#define PHYA_TXBF_ERROR_EVENT_RD_20_L___M 0xFFFFFFFF +#define PHYA_TXBF_ERROR_EVENT_RD_20_L___S 0 + +#define PHYA_TXBF_ERROR_EVENT_RD_20_U (0x003FB174) +#define PHYA_TXBF_ERROR_EVENT_RD_20_U___RWC QCSR_REG_RO +#define PHYA_TXBF_ERROR_EVENT_RD_20_U___POR 0x00000000 +#define PHYA_TXBF_ERROR_EVENT_RD_20_U__PRECODING_ERROR_INFO_1_0___POR 0x00000000 +#define PHYA_TXBF_ERROR_EVENT_RD_20_U__PRECODING_ERROR_INFO_1_0___M 0xFFFFFFFF +#define PHYA_TXBF_ERROR_EVENT_RD_20_U__PRECODING_ERROR_INFO_1_0___S 0 +#define PHYA_TXBF_ERROR_EVENT_RD_20_U___M 0xFFFFFFFF +#define PHYA_TXBF_ERROR_EVENT_RD_20_U___S 0 + +#define PHYA_TXBF_ERROR_EVENT_RD_21_L (0x003FB178) +#define PHYA_TXBF_ERROR_EVENT_RD_21_L___RWC QCSR_REG_RO +#define PHYA_TXBF_ERROR_EVENT_RD_21_L___POR 0x00000000 +#define PHYA_TXBF_ERROR_EVENT_RD_21_L__PRECODING_ERROR_INFO_0_1___POR 0x00000000 +#define PHYA_TXBF_ERROR_EVENT_RD_21_L__PRECODING_ERROR_INFO_0_1___M 0xFFFFFFFF +#define PHYA_TXBF_ERROR_EVENT_RD_21_L__PRECODING_ERROR_INFO_0_1___S 0 +#define PHYA_TXBF_ERROR_EVENT_RD_21_L___M 0xFFFFFFFF +#define PHYA_TXBF_ERROR_EVENT_RD_21_L___S 0 + +#define PHYA_TXBF_ERROR_EVENT_RD_21_U (0x003FB17C) +#define PHYA_TXBF_ERROR_EVENT_RD_21_U___RWC QCSR_REG_RO +#define PHYA_TXBF_ERROR_EVENT_RD_21_U___POR 0x00000000 +#define PHYA_TXBF_ERROR_EVENT_RD_21_U__PRECODING_ERROR_INFO_1_1___POR 0x00000000 +#define PHYA_TXBF_ERROR_EVENT_RD_21_U__PRECODING_ERROR_INFO_1_1___M 0xFFFFFFFF +#define PHYA_TXBF_ERROR_EVENT_RD_21_U__PRECODING_ERROR_INFO_1_1___S 0 +#define PHYA_TXBF_ERROR_EVENT_RD_21_U___M 0xFFFFFFFF +#define PHYA_TXBF_ERROR_EVENT_RD_21_U___S 0 + +#define PHYA_TXBF_ERROR_EVENT_RD_3_L (0x003FB180) +#define PHYA_TXBF_ERROR_EVENT_RD_3_L___RWC QCSR_REG_RO +#define PHYA_TXBF_ERROR_EVENT_RD_3_L___POR 0x00000000 +#define PHYA_TXBF_ERROR_EVENT_RD_3_L__CBF_RECEIVE_STATUS___POR 0x0 +#define PHYA_TXBF_ERROR_EVENT_RD_3_L__CBF_RECEIVE_STATUS___M 0x0000000F +#define PHYA_TXBF_ERROR_EVENT_RD_3_L__CBF_RECEIVE_STATUS___S 0 +#define PHYA_TXBF_ERROR_EVENT_RD_3_L___M 0x0000000F +#define PHYA_TXBF_ERROR_EVENT_RD_3_L___S 0 + +#define PHYA_TXBF_ERROR_EVENT_RD_4_L (0x003FB1A8) +#define PHYA_TXBF_ERROR_EVENT_RD_4_L___RWC QCSR_REG_RO +#define PHYA_TXBF_ERROR_EVENT_RD_4_L___POR 0x00000000 +#define PHYA_TXBF_ERROR_EVENT_RD_4_L__DDR_TRANSFER_DONE___POR 0x00000000 +#define PHYA_TXBF_ERROR_EVENT_RD_4_L__DDR_TRANSFER_DONE___M 0xFFFFFFFF +#define PHYA_TXBF_ERROR_EVENT_RD_4_L__DDR_TRANSFER_DONE___S 0 +#define PHYA_TXBF_ERROR_EVENT_RD_4_L___M 0xFFFFFFFF +#define PHYA_TXBF_ERROR_EVENT_RD_4_L___S 0 + +#define PHYA_TXBF_ERROR_EVENT_RD_4_U (0x003FB1AC) +#define PHYA_TXBF_ERROR_EVENT_RD_4_U___RWC QCSR_REG_RO +#define PHYA_TXBF_ERROR_EVENT_RD_4_U___POR 0x00000000 +#define PHYA_TXBF_ERROR_EVENT_RD_4_U__B2B_CBF_START_ERROR_USER___POR 0x00 +#define PHYA_TXBF_ERROR_EVENT_RD_4_U__MIMO_CTRL_ERROR_USER___POR 0x00 +#define PHYA_TXBF_ERROR_EVENT_RD_4_U__MORE_CBF_DATA_ERROR_USER___POR 0x00 +#define PHYA_TXBF_ERROR_EVENT_RD_4_U__LESS_CBF_DATA_ERROR_USER___POR 0x00 +#define PHYA_TXBF_ERROR_EVENT_RD_4_U__B2B_CBF_START_ERROR_USER___M 0x3F000000 +#define PHYA_TXBF_ERROR_EVENT_RD_4_U__B2B_CBF_START_ERROR_USER___S 24 +#define PHYA_TXBF_ERROR_EVENT_RD_4_U__MIMO_CTRL_ERROR_USER___M 0x003F0000 +#define PHYA_TXBF_ERROR_EVENT_RD_4_U__MIMO_CTRL_ERROR_USER___S 16 +#define PHYA_TXBF_ERROR_EVENT_RD_4_U__MORE_CBF_DATA_ERROR_USER___M 0x00003F00 +#define PHYA_TXBF_ERROR_EVENT_RD_4_U__MORE_CBF_DATA_ERROR_USER___S 8 +#define PHYA_TXBF_ERROR_EVENT_RD_4_U__LESS_CBF_DATA_ERROR_USER___M 0x0000003F +#define PHYA_TXBF_ERROR_EVENT_RD_4_U__LESS_CBF_DATA_ERROR_USER___S 0 +#define PHYA_TXBF_ERROR_EVENT_RD_4_U___M 0x3F3F3F3F +#define PHYA_TXBF_ERROR_EVENT_RD_4_U___S 0 + +#define PHYA_TXBF_ERROR_EVENT_RD_5_L (0x003FB1B0) +#define PHYA_TXBF_ERROR_EVENT_RD_5_L___RWC QCSR_REG_RO +#define PHYA_TXBF_ERROR_EVENT_RD_5_L___POR 0x00000000 +#define PHYA_TXBF_ERROR_EVENT_RD_5_L__CBF_DONE_NOT_RECEIVED_ERROR_USER___POR 0x00 +#define PHYA_TXBF_ERROR_EVENT_RD_5_L__WT_MEM_WR_CONFLICT_ERROR_USER___POR 0x00 +#define PHYA_TXBF_ERROR_EVENT_RD_5_L__UNSAVED_CV_ERROR_USER___POR 0x00 +#define PHYA_TXBF_ERROR_EVENT_RD_5_L__B2B_CBF_DONE_ERROR_USER___POR 0x00 +#define PHYA_TXBF_ERROR_EVENT_RD_5_L__CBF_DONE_NOT_RECEIVED_ERROR_USER___M 0x3F000000 +#define PHYA_TXBF_ERROR_EVENT_RD_5_L__CBF_DONE_NOT_RECEIVED_ERROR_USER___S 24 +#define PHYA_TXBF_ERROR_EVENT_RD_5_L__WT_MEM_WR_CONFLICT_ERROR_USER___M 0x003F0000 +#define PHYA_TXBF_ERROR_EVENT_RD_5_L__WT_MEM_WR_CONFLICT_ERROR_USER___S 16 +#define PHYA_TXBF_ERROR_EVENT_RD_5_L__UNSAVED_CV_ERROR_USER___M 0x00003F00 +#define PHYA_TXBF_ERROR_EVENT_RD_5_L__UNSAVED_CV_ERROR_USER___S 8 +#define PHYA_TXBF_ERROR_EVENT_RD_5_L__B2B_CBF_DONE_ERROR_USER___M 0x0000003F +#define PHYA_TXBF_ERROR_EVENT_RD_5_L__B2B_CBF_DONE_ERROR_USER___S 0 +#define PHYA_TXBF_ERROR_EVENT_RD_5_L___M 0x3F3F3F3F +#define PHYA_TXBF_ERROR_EVENT_RD_5_L___S 0 + +#define PHYA_TXBF_ERROR_EVENT_RD_6_L (0x003FB1B8) +#define PHYA_TXBF_ERROR_EVENT_RD_6_L___RWC QCSR_REG_RO +#define PHYA_TXBF_ERROR_EVENT_RD_6_L___POR 0x00000000 +#define PHYA_TXBF_ERROR_EVENT_RD_6_L__FIFO_OVERFLOW_INFO_0___POR 0x00000000 +#define PHYA_TXBF_ERROR_EVENT_RD_6_L__FIFO_OVERFLOW_INFO_0___M 0xFFFFFFFF +#define PHYA_TXBF_ERROR_EVENT_RD_6_L__FIFO_OVERFLOW_INFO_0___S 0 +#define PHYA_TXBF_ERROR_EVENT_RD_6_L___M 0xFFFFFFFF +#define PHYA_TXBF_ERROR_EVENT_RD_6_L___S 0 + +#define PHYA_TXBF_ERROR_EVENT_RD_6_U (0x003FB1BC) +#define PHYA_TXBF_ERROR_EVENT_RD_6_U___RWC QCSR_REG_RO +#define PHYA_TXBF_ERROR_EVENT_RD_6_U___POR 0x00000000 +#define PHYA_TXBF_ERROR_EVENT_RD_6_U__FIFO_OVERFLOW_INFO_1___POR 0x00000000 +#define PHYA_TXBF_ERROR_EVENT_RD_6_U__FIFO_OVERFLOW_INFO_1___M 0xFFFFFFFF +#define PHYA_TXBF_ERROR_EVENT_RD_6_U__FIFO_OVERFLOW_INFO_1___S 0 +#define PHYA_TXBF_ERROR_EVENT_RD_6_U___M 0xFFFFFFFF +#define PHYA_TXBF_ERROR_EVENT_RD_6_U___S 0 + +#define PHYA_TXBF_ERROR_EVENT_RD_7_L (0x003FB1C0) +#define PHYA_TXBF_ERROR_EVENT_RD_7_L___RWC QCSR_REG_RO +#define PHYA_TXBF_ERROR_EVENT_RD_7_L___POR 0x00000000 +#define PHYA_TXBF_ERROR_EVENT_RD_7_L__FIFO_UNDERFLOW_INFO_0___POR 0x00000000 +#define PHYA_TXBF_ERROR_EVENT_RD_7_L__FIFO_UNDERFLOW_INFO_0___M 0xFFFFFFFF +#define PHYA_TXBF_ERROR_EVENT_RD_7_L__FIFO_UNDERFLOW_INFO_0___S 0 +#define PHYA_TXBF_ERROR_EVENT_RD_7_L___M 0xFFFFFFFF +#define PHYA_TXBF_ERROR_EVENT_RD_7_L___S 0 + +#define PHYA_TXBF_ERROR_EVENT_RD_7_U (0x003FB1C4) +#define PHYA_TXBF_ERROR_EVENT_RD_7_U___RWC QCSR_REG_RO +#define PHYA_TXBF_ERROR_EVENT_RD_7_U___POR 0x00000000 +#define PHYA_TXBF_ERROR_EVENT_RD_7_U__FIFO_UNDERFLOW_INFO_1___POR 0x00000000 +#define PHYA_TXBF_ERROR_EVENT_RD_7_U__FIFO_UNDERFLOW_INFO_1___M 0xFFFFFFFF +#define PHYA_TXBF_ERROR_EVENT_RD_7_U__FIFO_UNDERFLOW_INFO_1___S 0 +#define PHYA_TXBF_ERROR_EVENT_RD_7_U___M 0xFFFFFFFF +#define PHYA_TXBF_ERROR_EVENT_RD_7_U___S 0 + +#define PHYA_TXBF_ERROR_EVENT_RD_8_L (0x003FB1C8) +#define PHYA_TXBF_ERROR_EVENT_RD_8_L___RWC QCSR_REG_RO +#define PHYA_TXBF_ERROR_EVENT_RD_8_L___POR 0x00000000 +#define PHYA_TXBF_ERROR_EVENT_RD_8_L__CVCTRL_STATE___POR 0x0 +#define PHYA_TXBF_ERROR_EVENT_RD_8_L__CVCTRL_STATE___M 0x00000003 +#define PHYA_TXBF_ERROR_EVENT_RD_8_L__CVCTRL_STATE___S 0 +#define PHYA_TXBF_ERROR_EVENT_RD_8_L___M 0x00000003 +#define PHYA_TXBF_ERROR_EVENT_RD_8_L___S 0 + +#define PHYA_TXBF_ERROR_EVENT_RD_9_L (0x003FB1D0) +#define PHYA_TXBF_ERROR_EVENT_RD_9_L___RWC QCSR_REG_RO +#define PHYA_TXBF_ERROR_EVENT_RD_9_L___POR 0x00000000 +#define PHYA_TXBF_ERROR_EVENT_RD_9_L__PREFETCH_REMAINING_DW___POR 0x0000 +#define PHYA_TXBF_ERROR_EVENT_RD_9_L__PREFETCH_TOTAL_DW___POR 0x0000 +#define PHYA_TXBF_ERROR_EVENT_RD_9_L__PREFETCH_REMAINING_DW___M 0xFFFF0000 +#define PHYA_TXBF_ERROR_EVENT_RD_9_L__PREFETCH_REMAINING_DW___S 16 +#define PHYA_TXBF_ERROR_EVENT_RD_9_L__PREFETCH_TOTAL_DW___M 0x0000FFFF +#define PHYA_TXBF_ERROR_EVENT_RD_9_L__PREFETCH_TOTAL_DW___S 0 +#define PHYA_TXBF_ERROR_EVENT_RD_9_L___M 0xFFFFFFFF +#define PHYA_TXBF_ERROR_EVENT_RD_9_L___S 0 + +#define PHYA_TXBF_USER_ERROR_EVENT_RD_L (0x003FB1D8) +#define PHYA_TXBF_USER_ERROR_EVENT_RD_L___RWC QCSR_REG_RO +#define PHYA_TXBF_USER_ERROR_EVENT_RD_L___POR 0x00000000 +#define PHYA_TXBF_USER_ERROR_EVENT_RD_L__WT_MEM_BUFF_FULL_COUNTER___POR 0x00000000 +#define PHYA_TXBF_USER_ERROR_EVENT_RD_L__WT_MEM_BUFF_FULL_COUNTER___M 0xFFFFFFFF +#define PHYA_TXBF_USER_ERROR_EVENT_RD_L__WT_MEM_BUFF_FULL_COUNTER___S 0 +#define PHYA_TXBF_USER_ERROR_EVENT_RD_L___M 0xFFFFFFFF +#define PHYA_TXBF_USER_ERROR_EVENT_RD_L___S 0 + +#define PHYA_TXBF_DEBUG_RD_00_L (0x003FB270) +#define PHYA_TXBF_DEBUG_RD_00_L___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_00_L___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_00_L__TONE_MASK_0_0___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_00_L__TONE_MASK_0_0___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_00_L__TONE_MASK_0_0___S 0 +#define PHYA_TXBF_DEBUG_RD_00_L___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_00_L___S 0 + +#define PHYA_TXBF_DEBUG_RD_00_U (0x003FB274) +#define PHYA_TXBF_DEBUG_RD_00_U___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_00_U___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_00_U__TONE_MASK_1_0___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_00_U__TONE_MASK_1_0___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_00_U__TONE_MASK_1_0___S 0 +#define PHYA_TXBF_DEBUG_RD_00_U___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_00_U___S 0 + +#define PHYA_TXBF_DEBUG_RD_01_L (0x003FB278) +#define PHYA_TXBF_DEBUG_RD_01_L___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_01_L___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_01_L__TONE_MASK_0_1___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_01_L__TONE_MASK_0_1___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_01_L__TONE_MASK_0_1___S 0 +#define PHYA_TXBF_DEBUG_RD_01_L___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_01_L___S 0 + +#define PHYA_TXBF_DEBUG_RD_01_U (0x003FB27C) +#define PHYA_TXBF_DEBUG_RD_01_U___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_01_U___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_01_U__TONE_MASK_1_1___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_01_U__TONE_MASK_1_1___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_01_U__TONE_MASK_1_1___S 0 +#define PHYA_TXBF_DEBUG_RD_01_U___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_01_U___S 0 + +#define PHYA_TXBF_DEBUG_RD_02_L (0x003FB280) +#define PHYA_TXBF_DEBUG_RD_02_L___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_02_L___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_02_L__TONE_MASK_0_2___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_02_L__TONE_MASK_0_2___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_02_L__TONE_MASK_0_2___S 0 +#define PHYA_TXBF_DEBUG_RD_02_L___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_02_L___S 0 + +#define PHYA_TXBF_DEBUG_RD_02_U (0x003FB284) +#define PHYA_TXBF_DEBUG_RD_02_U___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_02_U___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_02_U__TONE_MASK_1_2___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_02_U__TONE_MASK_1_2___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_02_U__TONE_MASK_1_2___S 0 +#define PHYA_TXBF_DEBUG_RD_02_U___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_02_U___S 0 + +#define PHYA_TXBF_DEBUG_RD_03_L (0x003FB288) +#define PHYA_TXBF_DEBUG_RD_03_L___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_03_L___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_03_L__TONE_MASK_0_3___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_03_L__TONE_MASK_0_3___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_03_L__TONE_MASK_0_3___S 0 +#define PHYA_TXBF_DEBUG_RD_03_L___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_03_L___S 0 + +#define PHYA_TXBF_DEBUG_RD_03_U (0x003FB28C) +#define PHYA_TXBF_DEBUG_RD_03_U___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_03_U___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_03_U__TONE_MASK_1_3___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_03_U__TONE_MASK_1_3___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_03_U__TONE_MASK_1_3___S 0 +#define PHYA_TXBF_DEBUG_RD_03_U___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_03_U___S 0 + +#define PHYA_TXBF_DEBUG_RD_04_L (0x003FB290) +#define PHYA_TXBF_DEBUG_RD_04_L___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_04_L___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_04_L__TONE_MASK_0_4___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_04_L__TONE_MASK_0_4___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_04_L__TONE_MASK_0_4___S 0 +#define PHYA_TXBF_DEBUG_RD_04_L___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_04_L___S 0 + +#define PHYA_TXBF_DEBUG_RD_04_U (0x003FB294) +#define PHYA_TXBF_DEBUG_RD_04_U___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_04_U___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_04_U__TONE_MASK_1_4___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_04_U__TONE_MASK_1_4___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_04_U__TONE_MASK_1_4___S 0 +#define PHYA_TXBF_DEBUG_RD_04_U___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_04_U___S 0 + +#define PHYA_TXBF_DEBUG_RD_05_L (0x003FB298) +#define PHYA_TXBF_DEBUG_RD_05_L___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_05_L___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_05_L__TONE_MASK_0_5___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_05_L__TONE_MASK_0_5___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_05_L__TONE_MASK_0_5___S 0 +#define PHYA_TXBF_DEBUG_RD_05_L___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_05_L___S 0 + +#define PHYA_TXBF_DEBUG_RD_05_U (0x003FB29C) +#define PHYA_TXBF_DEBUG_RD_05_U___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_05_U___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_05_U__TONE_MASK_1_5___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_05_U__TONE_MASK_1_5___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_05_U__TONE_MASK_1_5___S 0 +#define PHYA_TXBF_DEBUG_RD_05_U___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_05_U___S 0 + +#define PHYA_TXBF_DEBUG_RD_06_L (0x003FB2A0) +#define PHYA_TXBF_DEBUG_RD_06_L___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_06_L___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_06_L__TONE_MASK_0_6___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_06_L__TONE_MASK_0_6___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_06_L__TONE_MASK_0_6___S 0 +#define PHYA_TXBF_DEBUG_RD_06_L___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_06_L___S 0 + +#define PHYA_TXBF_DEBUG_RD_06_U (0x003FB2A4) +#define PHYA_TXBF_DEBUG_RD_06_U___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_06_U___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_06_U__TONE_MASK_1_6___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_06_U__TONE_MASK_1_6___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_06_U__TONE_MASK_1_6___S 0 +#define PHYA_TXBF_DEBUG_RD_06_U___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_06_U___S 0 + +#define PHYA_TXBF_DEBUG_RD_07_L (0x003FB2A8) +#define PHYA_TXBF_DEBUG_RD_07_L___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_07_L___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_07_L__TONE_MASK_0_7___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_07_L__TONE_MASK_0_7___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_07_L__TONE_MASK_0_7___S 0 +#define PHYA_TXBF_DEBUG_RD_07_L___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_07_L___S 0 + +#define PHYA_TXBF_DEBUG_RD_07_U (0x003FB2AC) +#define PHYA_TXBF_DEBUG_RD_07_U___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_07_U___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_07_U__TONE_MASK_1_7___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_07_U__TONE_MASK_1_7___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_07_U__TONE_MASK_1_7___S 0 +#define PHYA_TXBF_DEBUG_RD_07_U___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_07_U___S 0 + +#define PHYA_TXBF_DEBUG_RD_08_L (0x003FB2B0) +#define PHYA_TXBF_DEBUG_RD_08_L___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_08_L___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_08_L__TONE_MASK_0_8___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_08_L__TONE_MASK_0_8___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_08_L__TONE_MASK_0_8___S 0 +#define PHYA_TXBF_DEBUG_RD_08_L___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_08_L___S 0 + +#define PHYA_TXBF_DEBUG_RD_08_U (0x003FB2B4) +#define PHYA_TXBF_DEBUG_RD_08_U___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_08_U___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_08_U__TONE_MASK_1_8___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_08_U__TONE_MASK_1_8___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_08_U__TONE_MASK_1_8___S 0 +#define PHYA_TXBF_DEBUG_RD_08_U___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_08_U___S 0 + +#define PHYA_TXBF_DEBUG_RD_09_L (0x003FB2B8) +#define PHYA_TXBF_DEBUG_RD_09_L___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_09_L___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_09_L__TONE_MASK_0_9___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_09_L__TONE_MASK_0_9___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_09_L__TONE_MASK_0_9___S 0 +#define PHYA_TXBF_DEBUG_RD_09_L___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_09_L___S 0 + +#define PHYA_TXBF_DEBUG_RD_09_U (0x003FB2BC) +#define PHYA_TXBF_DEBUG_RD_09_U___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_09_U___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_09_U__TONE_MASK_1_9___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_09_U__TONE_MASK_1_9___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_09_U__TONE_MASK_1_9___S 0 +#define PHYA_TXBF_DEBUG_RD_09_U___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_09_U___S 0 + +#define PHYA_TXBF_DEBUG_RD_010_L (0x003FB2C0) +#define PHYA_TXBF_DEBUG_RD_010_L___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_010_L___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_010_L__TONE_MASK_0_10___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_010_L__TONE_MASK_0_10___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_010_L__TONE_MASK_0_10___S 0 +#define PHYA_TXBF_DEBUG_RD_010_L___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_010_L___S 0 + +#define PHYA_TXBF_DEBUG_RD_010_U (0x003FB2C4) +#define PHYA_TXBF_DEBUG_RD_010_U___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_010_U___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_010_U__TONE_MASK_1_10___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_010_U__TONE_MASK_1_10___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_010_U__TONE_MASK_1_10___S 0 +#define PHYA_TXBF_DEBUG_RD_010_U___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_010_U___S 0 + +#define PHYA_TXBF_DEBUG_RD_011_L (0x003FB2C8) +#define PHYA_TXBF_DEBUG_RD_011_L___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_011_L___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_011_L__TONE_MASK_0_11___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_011_L__TONE_MASK_0_11___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_011_L__TONE_MASK_0_11___S 0 +#define PHYA_TXBF_DEBUG_RD_011_L___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_011_L___S 0 + +#define PHYA_TXBF_DEBUG_RD_011_U (0x003FB2CC) +#define PHYA_TXBF_DEBUG_RD_011_U___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_011_U___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_011_U__TONE_MASK_1_11___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_011_U__TONE_MASK_1_11___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_011_U__TONE_MASK_1_11___S 0 +#define PHYA_TXBF_DEBUG_RD_011_U___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_011_U___S 0 + +#define PHYA_TXBF_DEBUG_RD_012_L (0x003FB2D0) +#define PHYA_TXBF_DEBUG_RD_012_L___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_012_L___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_012_L__TONE_MASK_0_12___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_012_L__TONE_MASK_0_12___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_012_L__TONE_MASK_0_12___S 0 +#define PHYA_TXBF_DEBUG_RD_012_L___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_012_L___S 0 + +#define PHYA_TXBF_DEBUG_RD_012_U (0x003FB2D4) +#define PHYA_TXBF_DEBUG_RD_012_U___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_012_U___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_012_U__TONE_MASK_1_12___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_012_U__TONE_MASK_1_12___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_012_U__TONE_MASK_1_12___S 0 +#define PHYA_TXBF_DEBUG_RD_012_U___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_012_U___S 0 + +#define PHYA_TXBF_DEBUG_RD_013_L (0x003FB2D8) +#define PHYA_TXBF_DEBUG_RD_013_L___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_013_L___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_013_L__TONE_MASK_0_13___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_013_L__TONE_MASK_0_13___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_013_L__TONE_MASK_0_13___S 0 +#define PHYA_TXBF_DEBUG_RD_013_L___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_013_L___S 0 + +#define PHYA_TXBF_DEBUG_RD_013_U (0x003FB2DC) +#define PHYA_TXBF_DEBUG_RD_013_U___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_013_U___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_013_U__TONE_MASK_1_13___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_013_U__TONE_MASK_1_13___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_013_U__TONE_MASK_1_13___S 0 +#define PHYA_TXBF_DEBUG_RD_013_U___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_013_U___S 0 + +#define PHYA_TXBF_DEBUG_RD_014_L (0x003FB2E0) +#define PHYA_TXBF_DEBUG_RD_014_L___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_014_L___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_014_L__TONE_MASK_0_14___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_014_L__TONE_MASK_0_14___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_014_L__TONE_MASK_0_14___S 0 +#define PHYA_TXBF_DEBUG_RD_014_L___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_014_L___S 0 + +#define PHYA_TXBF_DEBUG_RD_014_U (0x003FB2E4) +#define PHYA_TXBF_DEBUG_RD_014_U___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_014_U___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_014_U__TONE_MASK_1_14___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_014_U__TONE_MASK_1_14___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_014_U__TONE_MASK_1_14___S 0 +#define PHYA_TXBF_DEBUG_RD_014_U___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_014_U___S 0 + +#define PHYA_TXBF_DEBUG_RD_015_L (0x003FB2E8) +#define PHYA_TXBF_DEBUG_RD_015_L___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_015_L___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_015_L__TONE_MASK_0_15___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_015_L__TONE_MASK_0_15___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_015_L__TONE_MASK_0_15___S 0 +#define PHYA_TXBF_DEBUG_RD_015_L___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_015_L___S 0 + +#define PHYA_TXBF_DEBUG_RD_015_U (0x003FB2EC) +#define PHYA_TXBF_DEBUG_RD_015_U___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_015_U___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_015_U__TONE_MASK_1_15___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_015_U__TONE_MASK_1_15___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_015_U__TONE_MASK_1_15___S 0 +#define PHYA_TXBF_DEBUG_RD_015_U___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_015_U___S 0 + +#define PHYA_TXBF_DEBUG_RD_1_L (0x003FB2F0) +#define PHYA_TXBF_DEBUG_RD_1_L___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_1_L___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_1_L__CLKON_TMAP_LUT_MEM___POR 0x0 +#define PHYA_TXBF_DEBUG_RD_1_L__CLKON_CV_MEM___POR 0x0 +#define PHYA_TXBF_DEBUG_RD_1_L__HW_DMA_TRANSFER_ONGOING___POR 0x0 +#define PHYA_TXBF_DEBUG_RD_1_L__CLKON_TMAP_LUT_MEM___M 0x00010000 +#define PHYA_TXBF_DEBUG_RD_1_L__CLKON_TMAP_LUT_MEM___S 16 +#define PHYA_TXBF_DEBUG_RD_1_L__CLKON_CV_MEM___M 0x00000100 +#define PHYA_TXBF_DEBUG_RD_1_L__CLKON_CV_MEM___S 8 +#define PHYA_TXBF_DEBUG_RD_1_L__HW_DMA_TRANSFER_ONGOING___M 0x00000001 +#define PHYA_TXBF_DEBUG_RD_1_L__HW_DMA_TRANSFER_ONGOING___S 0 +#define PHYA_TXBF_DEBUG_RD_1_L___M 0x00010101 +#define PHYA_TXBF_DEBUG_RD_1_L___S 0 + +#define PHYA_TXBF_DEBUG_RD_1_U (0x003FB2F4) +#define PHYA_TXBF_DEBUG_RD_1_U___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_1_U___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_1_U__POWER_WTG_TOTAL_TONE_CNT___POR 0x000 +#define PHYA_TXBF_DEBUG_RD_1_U__QRE_TX_TONE_CNT___POR 0x000 +#define PHYA_TXBF_DEBUG_RD_1_U__POWER_WTG_TOTAL_TONE_CNT___M 0x03FF0000 +#define PHYA_TXBF_DEBUG_RD_1_U__POWER_WTG_TOTAL_TONE_CNT___S 16 +#define PHYA_TXBF_DEBUG_RD_1_U__QRE_TX_TONE_CNT___M 0x000003FF +#define PHYA_TXBF_DEBUG_RD_1_U__QRE_TX_TONE_CNT___S 0 +#define PHYA_TXBF_DEBUG_RD_1_U___M 0x03FF03FF +#define PHYA_TXBF_DEBUG_RD_1_U___S 0 + +#define PHYA_TXBF_DEBUG_RD_2_L (0x003FB2F8) +#define PHYA_TXBF_DEBUG_RD_2_L___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_2_L___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_2_L__POWER_WTG_CURR_RU_IDX___POR 0x00 +#define PHYA_TXBF_DEBUG_RD_2_L__POWER_WTG_RU_TONE_CNT___POR 0x000 +#define PHYA_TXBF_DEBUG_RD_2_L__POWER_WTG_CURR_RU_IDX___M 0x007F0000 +#define PHYA_TXBF_DEBUG_RD_2_L__POWER_WTG_CURR_RU_IDX___S 16 +#define PHYA_TXBF_DEBUG_RD_2_L__POWER_WTG_RU_TONE_CNT___M 0x000003FF +#define PHYA_TXBF_DEBUG_RD_2_L__POWER_WTG_RU_TONE_CNT___S 0 +#define PHYA_TXBF_DEBUG_RD_2_L___M 0x007F03FF +#define PHYA_TXBF_DEBUG_RD_2_L___S 0 + +#define PHYA_TXBF_DEBUG_RD_2_U (0x003FB2FC) +#define PHYA_TXBF_DEBUG_RD_2_U___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_2_U___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_2_U__POST_FINAL_INTERP_TONE_CNT___POR 0x000 +#define PHYA_TXBF_DEBUG_RD_2_U__PRE_FIRST_INTERP_COL_TONE_CNT___POR 0x000 +#define PHYA_TXBF_DEBUG_RD_2_U__POST_FINAL_INTERP_TONE_CNT___M 0x03FF0000 +#define PHYA_TXBF_DEBUG_RD_2_U__POST_FINAL_INTERP_TONE_CNT___S 16 +#define PHYA_TXBF_DEBUG_RD_2_U__PRE_FIRST_INTERP_COL_TONE_CNT___M 0x000003FF +#define PHYA_TXBF_DEBUG_RD_2_U__PRE_FIRST_INTERP_COL_TONE_CNT___S 0 +#define PHYA_TXBF_DEBUG_RD_2_U___M 0x03FF03FF +#define PHYA_TXBF_DEBUG_RD_2_U___S 0 + +#define PHYA_TXBF_DEBUG_RD_3_L (0x003FB300) +#define PHYA_TXBF_DEBUG_RD_3_L___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_3_L___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_3_L__WEIGHTS_MEM_USER_OCCUPANCY___POR 0x0000 +#define PHYA_TXBF_DEBUG_RD_3_L__MAX_CBF_INPUT_FIFO_OCCUPANCY___POR 0x0000 +#define PHYA_TXBF_DEBUG_RD_3_L__WEIGHTS_MEM_USER_OCCUPANCY___M 0xFFFF0000 +#define PHYA_TXBF_DEBUG_RD_3_L__WEIGHTS_MEM_USER_OCCUPANCY___S 16 +#define PHYA_TXBF_DEBUG_RD_3_L__MAX_CBF_INPUT_FIFO_OCCUPANCY___M 0x0000FFFF +#define PHYA_TXBF_DEBUG_RD_3_L__MAX_CBF_INPUT_FIFO_OCCUPANCY___S 0 +#define PHYA_TXBF_DEBUG_RD_3_L___M 0xFFFFFFFF +#define PHYA_TXBF_DEBUG_RD_3_L___S 0 + +#define PHYA_TXBF_DEBUG_RD_3_U (0x003FB304) +#define PHYA_TXBF_DEBUG_RD_3_U___RWC QCSR_REG_RO +#define PHYA_TXBF_DEBUG_RD_3_U___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_3_U__WEIGHTS_MEM_OFFSET___POR 0x000 +#define PHYA_TXBF_DEBUG_RD_3_U__WEIGHTS_MEM_OFFSET___M 0x000003FF +#define PHYA_TXBF_DEBUG_RD_3_U__WEIGHTS_MEM_OFFSET___S 0 +#define PHYA_TXBF_DEBUG_RD_3_U___M 0x000003FF +#define PHYA_TXBF_DEBUG_RD_3_U___S 0 + +#define PHYA_TXBF_FSM_L (0x003FB308) +#define PHYA_TXBF_FSM_L___RWC QCSR_REG_RO +#define PHYA_TXBF_FSM_L___POR 0x00000000 +#define PHYA_TXBF_FSM_L__AC_INTERPS_STATE___POR 0x0 +#define PHYA_TXBF_FSM_L__STORE_WT_RD_CTRL_STATE___POR 0x0 +#define PHYA_TXBF_FSM_L__POWER_WTG_STATE___POR 0x0 +#define PHYA_TXBF_FSM_L__INTERPV_STATE___POR 0x0 +#define PHYA_TXBF_FSM_L__AC_INTERPS_STATE___M 0x03000000 +#define PHYA_TXBF_FSM_L__AC_INTERPS_STATE___S 24 +#define PHYA_TXBF_FSM_L__STORE_WT_RD_CTRL_STATE___M 0x00030000 +#define PHYA_TXBF_FSM_L__STORE_WT_RD_CTRL_STATE___S 16 +#define PHYA_TXBF_FSM_L__POWER_WTG_STATE___M 0x00000700 +#define PHYA_TXBF_FSM_L__POWER_WTG_STATE___S 8 +#define PHYA_TXBF_FSM_L__INTERPV_STATE___M 0x00000003 +#define PHYA_TXBF_FSM_L__INTERPV_STATE___S 0 +#define PHYA_TXBF_FSM_L___M 0x03030703 +#define PHYA_TXBF_FSM_L___S 0 + +#define PHYA_TXBF_FSM_U (0x003FB30C) +#define PHYA_TXBF_FSM_U___RWC QCSR_REG_RO +#define PHYA_TXBF_FSM_U___POR 0x00000000 +#define PHYA_TXBF_FSM_U__BF_PARAMS_STATE___POR 0x0 +#define PHYA_TXBF_FSM_U__BF_PARAMS_STATE___M 0x0000000F +#define PHYA_TXBF_FSM_U__BF_PARAMS_STATE___S 0 +#define PHYA_TXBF_FSM_U___M 0x0000000F +#define PHYA_TXBF_FSM_U___S 0 + +#define PHYA_TXBF_ERROR_EVENT_WR_0_L (0x003FB310) +#define PHYA_TXBF_ERROR_EVENT_WR_0_L___RWC QCSR_REG_WO +#define PHYA_TXBF_ERROR_EVENT_WR_0_L___POR 0x00000000 +#define PHYA_TXBF_ERROR_EVENT_WR_0_L__MASK_WT_MEM_DMA_RD___POR 0x0 +#define PHYA_TXBF_ERROR_EVENT_WR_0_L__MASK_WT_MEM_DMA_RD___M 0x00000001 +#define PHYA_TXBF_ERROR_EVENT_WR_0_L__MASK_WT_MEM_DMA_RD___S 0 +#define PHYA_TXBF_ERROR_EVENT_WR_0_L___M 0x00000001 +#define PHYA_TXBF_ERROR_EVENT_WR_0_L___S 0 + +#define PHYA_TXBF_DEBUG_RD_4_L (0x003FB318) +#define PHYA_TXBF_DEBUG_RD_4_L___RWC QCSR_REG_WO +#define PHYA_TXBF_DEBUG_RD_4_L___POR 0x00000000 +#define PHYA_TXBF_DEBUG_RD_4_L__USER_SELECTION_INDEX___POR 0x00 +#define PHYA_TXBF_DEBUG_RD_4_L__COL_SELECTION_INDEX___POR 0x0 +#define PHYA_TXBF_DEBUG_RD_4_L__USER_SELECTION_INDEX___M 0x0000FF00 +#define PHYA_TXBF_DEBUG_RD_4_L__USER_SELECTION_INDEX___S 8 +#define PHYA_TXBF_DEBUG_RD_4_L__COL_SELECTION_INDEX___M 0x0000000F +#define PHYA_TXBF_DEBUG_RD_4_L__COL_SELECTION_INDEX___S 0 +#define PHYA_TXBF_DEBUG_RD_4_L___M 0x0000FF0F +#define PHYA_TXBF_DEBUG_RD_4_L___S 0 + +#define PHYA_TXBF_ERROR_EVENT_WR_1_L (0x003FB320) +#define PHYA_TXBF_ERROR_EVENT_WR_1_L___RWC QCSR_REG_WO +#define PHYA_TXBF_ERROR_EVENT_WR_1_L___POR 0x00000000 +#define PHYA_TXBF_ERROR_EVENT_WR_1_L__FW_FORCE_PRECODING_STG2_START___POR 0x0 +#define PHYA_TXBF_ERROR_EVENT_WR_1_L__FW_FORCE_PRECODING_STG2_START___M 0x00000001 +#define PHYA_TXBF_ERROR_EVENT_WR_1_L__FW_FORCE_PRECODING_STG2_START___S 0 +#define PHYA_TXBF_ERROR_EVENT_WR_1_L___M 0x00000001 +#define PHYA_TXBF_ERROR_EVENT_WR_1_L___S 0 + +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_L (0x003FB328) +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_L___RWC QCSR_REG_RW +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_L___POR 0x00000000 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_L__TXBF_VSMOOTH_EN___POR 0x0 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_L__TXBF_PCHN_MODE___POR 0x0 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_L__TXBF_VSMOOTH_EN___M 0x00000100 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_L__TXBF_VSMOOTH_EN___S 8 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_L__TXBF_PCHN_MODE___M 0x00000001 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_L__TXBF_PCHN_MODE___S 0 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_L___M 0x00000101 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_L___S 0 + +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_0_L (0x003FB378) +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_0_L___POR 0x00000000 +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_0_L__TXBF_USER_CV_IS_AX___POR 0x0 +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_0_L__TXBF_USER_CV_IS_AX___M 0x00000001 +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_0_L__TXBF_USER_CV_IS_AX___S 0 +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_0_L___M 0x00000001 +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_0_L___S 0 + +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_0_U (0x003FB37C) +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_0_U___RWC QCSR_REG_RW +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_0_U___POR 0x00000000 +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_0_U__MIMO_CTRL_0_CFG___POR 0x00000000 +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_0_U__MIMO_CTRL_0_CFG___M 0xFFFFFFFF +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_0_U__MIMO_CTRL_0_CFG___S 0 +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_0_U___M 0xFFFFFFFF +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_0_U___S 0 + +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_1_L (0x003FB380) +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_1_L___POR 0x00000000 +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_1_L__MIMO_CTRL_1_CFG___POR 0x00000000 +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_1_L__MIMO_CTRL_1_CFG___M 0xFFFFFFFF +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_1_L__MIMO_CTRL_1_CFG___S 0 +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_1_L___M 0xFFFFFFFF +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_1_L___S 0 + +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_1_U (0x003FB384) +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_1_U___RWC QCSR_REG_RW +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_1_U___POR 0x00000000 +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_1_U__ASNR_CFG___POR 0x00000000 +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_1_U__ASNR_CFG___M 0xFFFFFFFF +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_1_U__ASNR_CFG___S 0 +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_1_U___M 0xFFFFFFFF +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_1_U___S 0 + +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_2_L (0x003FB388) +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_2_L___POR 0x00000000 +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_2_L__TXBF_USER_CV_IS_IMPLICIT___POR 0x00000000 +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_2_L__TXBF_USER_CV_IS_IMPLICIT___M 0xFFFFFFFF +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_2_L__TXBF_USER_CV_IS_IMPLICIT___S 0 +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_2_L___M 0xFFFFFFFF +#define PHYA_TXBF_USER_A_TXBF_PARAMS_WR_2_L___S 0 + +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_0_L (0x003FB6F0) +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_0_L___RWC QCSR_REG_RW +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_0_L___POR 0x00000000 +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_0_L__TXBF_USER_CV_MEM_BIT_OFFSET_1___POR 0x00 +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_0_L__TXBF_USER_CV_MEM_BIT_OFFSET_0___POR 0x00 +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_0_L__TXBF_USER_CV_MEM_BIT_OFFSET_1___M 0x00003F00 +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_0_L__TXBF_USER_CV_MEM_BIT_OFFSET_1___S 8 +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_0_L__TXBF_USER_CV_MEM_BIT_OFFSET_0___M 0x0000003F +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_0_L__TXBF_USER_CV_MEM_BIT_OFFSET_0___S 0 +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_0_L___M 0x00003F3F +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_0_L___S 0 + +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_L (0x003FB6F8) +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_L___POR 0x00000000 +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_L__TXBF_USER_SNR_NIBBLE_OFFSET_1___POR 0x0 +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_L__TXBF_USER_SNR_NIBBLE_OFFSET_0___POR 0x0 +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_L__TXBF_USER_SNR_NIBBLE_OFFSET_1___M 0x00000F00 +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_L__TXBF_USER_SNR_NIBBLE_OFFSET_1___S 8 +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_L__TXBF_USER_SNR_NIBBLE_OFFSET_0___M 0x0000000F +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_L__TXBF_USER_SNR_NIBBLE_OFFSET_0___S 0 +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_L___M 0x00000F0F +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_L___S 0 + +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_2_L (0x003FB700) +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_2_L___RWC QCSR_REG_RW +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_2_L___POR 0x00000000 +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_2_L__TXBF_USER_BANK_OFFSET_1___POR 0x0 +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_2_L__TXBF_USER_BANK_OFFSET_0___POR 0x0 +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_2_L__TXBF_USER_BANK_OFFSET_1___M 0x00000700 +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_2_L__TXBF_USER_BANK_OFFSET_1___S 8 +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_2_L__TXBF_USER_BANK_OFFSET_0___M 0x00000007 +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_2_L__TXBF_USER_BANK_OFFSET_0___S 0 +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_2_L___M 0x00000707 +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_2_L___S 0 + +#define PHYA_TXBF_CTRL_TXBF_PARAMS_WR_L (0x003FBA68) +#define PHYA_TXBF_CTRL_TXBF_PARAMS_WR_L___RWC QCSR_REG_WO +#define PHYA_TXBF_CTRL_TXBF_PARAMS_WR_L___POR 0x00000000 +#define PHYA_TXBF_CTRL_TXBF_PARAMS_WR_L__TXBF_START_PRECODING___POR 0x0 +#define PHYA_TXBF_CTRL_TXBF_PARAMS_WR_L__TXBF_REUSE_WTS___POR 0x0 +#define PHYA_TXBF_CTRL_TXBF_PARAMS_WR_L__TXBF_START_PRECODING___M 0x00000100 +#define PHYA_TXBF_CTRL_TXBF_PARAMS_WR_L__TXBF_START_PRECODING___S 8 +#define PHYA_TXBF_CTRL_TXBF_PARAMS_WR_L__TXBF_REUSE_WTS___M 0x00000001 +#define PHYA_TXBF_CTRL_TXBF_PARAMS_WR_L__TXBF_REUSE_WTS___S 0 +#define PHYA_TXBF_CTRL_TXBF_PARAMS_WR_L___M 0x00000101 +#define PHYA_TXBF_CTRL_TXBF_PARAMS_WR_L___S 0 + +#define PHYA_TXBF_TXBF_PARAMS_WR_SPARE_L (0x003FBA70) +#define PHYA_TXBF_TXBF_PARAMS_WR_SPARE_L___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_PARAMS_WR_SPARE_L___POR 0x00000000 +#define PHYA_TXBF_TXBF_PARAMS_WR_SPARE_L__TXBF_PARAMS_WR_SPARE_0___POR 0x00000000 +#define PHYA_TXBF_TXBF_PARAMS_WR_SPARE_L__TXBF_PARAMS_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_PARAMS_WR_SPARE_L__TXBF_PARAMS_WR_SPARE_0___S 0 +#define PHYA_TXBF_TXBF_PARAMS_WR_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_PARAMS_WR_SPARE_L___S 0 + +#define PHYA_TXBF_TXBF_PARAMS_WR_SPARE_U (0x003FBA74) +#define PHYA_TXBF_TXBF_PARAMS_WR_SPARE_U___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_PARAMS_WR_SPARE_U___POR 0x00000000 +#define PHYA_TXBF_TXBF_PARAMS_WR_SPARE_U__TXBF_PARAMS_WR_SPARE_1___POR 0x00000000 +#define PHYA_TXBF_TXBF_PARAMS_WR_SPARE_U__TXBF_PARAMS_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_PARAMS_WR_SPARE_U__TXBF_PARAMS_WR_SPARE_1___S 0 +#define PHYA_TXBF_TXBF_PARAMS_WR_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_PARAMS_WR_SPARE_U___S 0 + +#define PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_L (0x003FBA78) +#define PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_L___POR 0x00000000 +#define PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_L__TXBF_NUM_RU___POR 0x00 +#define PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_L__TXBF_CHAIN_MASK___POR 0x00 +#define PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_L__TXBF_PKT_BW___POR 0x0 +#define PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_L__TXBF_BF_IS_AX___POR 0x0 +#define PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_L__TXBF_NUM_RU___M 0x7F000000 +#define PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_L__TXBF_NUM_RU___S 24 +#define PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_L__TXBF_CHAIN_MASK___M 0x00FF0000 +#define PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_L__TXBF_CHAIN_MASK___S 16 +#define PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_L__TXBF_PKT_BW___M 0x00000300 +#define PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_L__TXBF_PKT_BW___S 8 +#define PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_L__TXBF_BF_IS_AX___M 0x00000001 +#define PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_L__TXBF_BF_IS_AX___S 0 +#define PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_L___M 0x7FFF0301 +#define PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_L___S 0 + +#define PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_U (0x003FBA7C) +#define PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_U___RWC QCSR_REG_RW +#define PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_U___POR 0x00000000 +#define PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_U__TXBF_RU_STRUCT_IDX_SEG1___POR 0x00 +#define PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_U__TXBF_PKT_IS_OFDMA___POR 0x0 +#define PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_U__TXBF_RU_STRUCT_IDX_SEG1___M 0x0000FF00 +#define PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_U__TXBF_RU_STRUCT_IDX_SEG1___S 8 +#define PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_U__TXBF_PKT_IS_OFDMA___M 0x00000001 +#define PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_U__TXBF_PKT_IS_OFDMA___S 0 +#define PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_U___M 0x0000FF01 +#define PHYA_TXBF_COMMON_TXBF_PARAMS_WR_1_U___S 0 + +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_L (0x003FBA80) +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_L___RWC QCSR_REG_RW +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_L___POR 0x00000000 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_L__TXBF_NR___POR 0x0 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_L__TXBF_RU_SIZE___POR 0x0 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_L__TXBF_RU_START_IDX___POR 0x00 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_L__TXBF_RU_VALID___POR 0x0 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_L__TXBF_NR___M 0x07000000 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_L__TXBF_NR___S 24 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_L__TXBF_RU_SIZE___M 0x00070000 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_L__TXBF_RU_SIZE___S 16 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_L__TXBF_RU_START_IDX___M 0x00007F00 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_L__TXBF_RU_START_IDX___S 8 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_L__TXBF_RU_VALID___M 0x00000001 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_L__TXBF_RU_VALID___S 0 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_L___M 0x07077F01 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_L___S 0 + +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_U (0x003FBA84) +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_U___RWC QCSR_REG_RW +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_U___POR 0x00000000 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_U__TXBF_VLD_USERS___POR 0x00 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_U__TXBF_VLD_USERS___M 0x000000FF +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_U__TXBF_VLD_USERS___S 0 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_U___M 0x000000FF +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_0_U___S 0 + +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_1_L (0x003FBA88) +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_1_L___RWC QCSR_REG_RW +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_1_L___POR 0x00000000 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_1_L__USER1_TXBF_USER_ID___POR 0x00 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_1_L__USER0_TXBF_USER_ID___POR 0x00 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_1_L__USER1_TXBF_USER_ID___M 0x00003F00 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_1_L__USER1_TXBF_USER_ID___S 8 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_1_L__USER0_TXBF_USER_ID___M 0x0000003F +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_1_L__USER0_TXBF_USER_ID___S 0 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_1_L___M 0x00003F3F +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_1_L___S 0 + +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_2_L (0x003FBA90) +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_2_L___RWC QCSR_REG_RW +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_2_L___POR 0x00000000 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_2_L__USER1_TXBF_USER_SW_PEER_ID___POR 0x0000 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_2_L__USER0_TXBF_USER_SW_PEER_ID___POR 0x0000 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_2_L__USER1_TXBF_USER_SW_PEER_ID___M 0xFFFF0000 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_2_L__USER1_TXBF_USER_SW_PEER_ID___S 16 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_2_L__USER0_TXBF_USER_SW_PEER_ID___M 0x0000FFFF +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_2_L__USER0_TXBF_USER_SW_PEER_ID___S 0 +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_2_L___M 0xFFFFFFFF +#define PHYA_TXBF_RU_TXBF_PARAMS_WR_1_2_L___S 0 + +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_0_L (0x003FBF20) +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_0_L___RWC QCSR_REG_RW +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_0_L___POR 0x00000000 +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_0_L__TXBF_USER_CSD_EN___POR 0x0 +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_0_L__TXBF_USER_NSS___POR 0x0 +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_0_L__TXBF_USER_CSD_EN___M 0x00000100 +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_0_L__TXBF_USER_CSD_EN___S 8 +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_0_L__TXBF_USER_NSS___M 0x00000007 +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_0_L__TXBF_USER_NSS___S 0 +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_0_L___M 0x00000107 +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_0_L___S 0 + +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_1_L (0x003FBF28) +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_1_L___RWC QCSR_REG_RW +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_1_L___POR 0x00000000 +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_1_L__TXBF_USER_CSD_OFFSET_1___POR 0x00 +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_1_L__TXBF_USER_CSD_OFFSET_0___POR 0x00 +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_1_L__TXBF_USER_CSD_OFFSET_1___M 0x0000FF00 +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_1_L__TXBF_USER_CSD_OFFSET_1___S 8 +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_1_L__TXBF_USER_CSD_OFFSET_0___M 0x000000FF +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_1_L__TXBF_USER_CSD_OFFSET_0___S 0 +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_1_L___M 0x0000FFFF +#define PHYA_TXBF_USER_TXBF_PARAMS_WR_1_1_L___S 0 + +#define PHYA_TXBF_TXBF_PARAMS_WR_1_SPARE_L (0x003FC170) +#define PHYA_TXBF_TXBF_PARAMS_WR_1_SPARE_L___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_PARAMS_WR_1_SPARE_L___POR 0x00000000 +#define PHYA_TXBF_TXBF_PARAMS_WR_1_SPARE_L__TXBF_PARAMS_WR_1_SPARE_0___POR 0x00000000 +#define PHYA_TXBF_TXBF_PARAMS_WR_1_SPARE_L__TXBF_PARAMS_WR_1_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_PARAMS_WR_1_SPARE_L__TXBF_PARAMS_WR_1_SPARE_0___S 0 +#define PHYA_TXBF_TXBF_PARAMS_WR_1_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_PARAMS_WR_1_SPARE_L___S 0 + +#define PHYA_TXBF_TXBF_PARAMS_WR_1_SPARE_U (0x003FC174) +#define PHYA_TXBF_TXBF_PARAMS_WR_1_SPARE_U___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_PARAMS_WR_1_SPARE_U___POR 0x00000000 +#define PHYA_TXBF_TXBF_PARAMS_WR_1_SPARE_U__TXBF_PARAMS_WR_1_SPARE_1___POR 0x00000000 +#define PHYA_TXBF_TXBF_PARAMS_WR_1_SPARE_U__TXBF_PARAMS_WR_1_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_PARAMS_WR_1_SPARE_U__TXBF_PARAMS_WR_1_SPARE_1___S 0 +#define PHYA_TXBF_TXBF_PARAMS_WR_1_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_PARAMS_WR_1_SPARE_U___S 0 + +#define PHYA_TXBF_TXBF_PARAMS__RD_0_L (0x003FC178) +#define PHYA_TXBF_TXBF_PARAMS__RD_0_L___RWC QCSR_REG_RO +#define PHYA_TXBF_TXBF_PARAMS__RD_0_L___POR 0x00000000 +#define PHYA_TXBF_TXBF_PARAMS__RD_0_L__TXBF_WEIGHTS_RDY___POR 0x0 +#define PHYA_TXBF_TXBF_PARAMS__RD_0_L__TXBF_WEIGHTS_RDY___M 0x00000001 +#define PHYA_TXBF_TXBF_PARAMS__RD_0_L__TXBF_WEIGHTS_RDY___S 0 +#define PHYA_TXBF_TXBF_PARAMS__RD_0_L___M 0x00000001 +#define PHYA_TXBF_TXBF_PARAMS__RD_0_L___S 0 + +#define PHYA_TXBF_TXBF_PARAMS__RD_0_U (0x003FC17C) +#define PHYA_TXBF_TXBF_PARAMS__RD_0_U___RWC QCSR_REG_RO +#define PHYA_TXBF_TXBF_PARAMS__RD_0_U___POR 0x00000000 +#define PHYA_TXBF_TXBF_PARAMS__RD_0_U__PRECODING_STG1_STG2_WAIT_CTR___POR 0x00000000 +#define PHYA_TXBF_TXBF_PARAMS__RD_0_U__PRECODING_STG1_STG2_WAIT_CTR___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_PARAMS__RD_0_U__PRECODING_STG1_STG2_WAIT_CTR___S 0 +#define PHYA_TXBF_TXBF_PARAMS__RD_0_U___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_PARAMS__RD_0_U___S 0 + +#define PHYA_TXBF_TXBF_PARAMS__RD_1_L (0x003FC180) +#define PHYA_TXBF_TXBF_PARAMS__RD_1_L___RWC QCSR_REG_RO +#define PHYA_TXBF_TXBF_PARAMS__RD_1_L___POR 0x00000000 +#define PHYA_TXBF_TXBF_PARAMS__RD_1_L__TXBF_RU_WALSH_0___POR 0x00000000 +#define PHYA_TXBF_TXBF_PARAMS__RD_1_L__TXBF_RU_WALSH_0___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_PARAMS__RD_1_L__TXBF_RU_WALSH_0___S 0 +#define PHYA_TXBF_TXBF_PARAMS__RD_1_L___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_PARAMS__RD_1_L___S 0 + +#define PHYA_TXBF_TXBF_PARAMS__RD_1_U (0x003FC184) +#define PHYA_TXBF_TXBF_PARAMS__RD_1_U___RWC QCSR_REG_RO +#define PHYA_TXBF_TXBF_PARAMS__RD_1_U___POR 0x00000000 +#define PHYA_TXBF_TXBF_PARAMS__RD_1_U__TXBF_RU_WALSH_1___POR 0x00000000 +#define PHYA_TXBF_TXBF_PARAMS__RD_1_U__TXBF_RU_WALSH_1___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_PARAMS__RD_1_U__TXBF_RU_WALSH_1___S 0 +#define PHYA_TXBF_TXBF_PARAMS__RD_1_U___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_PARAMS__RD_1_U___S 0 + +#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_0_L (0x003FC188) +#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_0_L___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_0_L___POR 0x00000000 +#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_0_L__TXBF_PARAMS_RD_SPARE_0___POR 0x00000000 +#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_0_L__TXBF_PARAMS_RD_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_0_L__TXBF_PARAMS_RD_SPARE_0___S 0 +#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_0_L___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_0_L___S 0 + +#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_0_U (0x003FC18C) +#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_0_U___RWC QCSR_REG_RW +#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_0_U___POR 0x00000000 +#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_0_U__TXBF_PARAMS_RD_SPARE_1___POR 0x00000000 +#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_0_U__TXBF_PARAMS_RD_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_0_U__TXBF_PARAMS_RD_SPARE_1___S 0 +#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_0_U___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_0_U___S 0 + +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_L (0x003FC190) +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_L___RWC QCSR_REG_RW +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_L___POR 0x00400000 +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_L__WT_MEM_DEPTH_0___POR 0x0040 +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_L__WT_MEM_START_ADR_0___POR 0x0000 +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_L__WT_MEM_DEPTH_0___M 0xFFFF0000 +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_L__WT_MEM_DEPTH_0___S 16 +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_L__WT_MEM_START_ADR_0___M 0x0000FFFF +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_L__WT_MEM_START_ADR_0___S 0 +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_L___M 0xFFFFFFFF +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_L___S 0 + +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_U (0x003FC194) +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_U___RWC QCSR_REG_RW +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_U___POR 0x00200010 +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_U__FILL_THRESHOLD_HIGH_0___POR 0x0020 +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_U__FILL_THRESHOLD_LOW_0___POR 0x0010 +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_U__FILL_THRESHOLD_HIGH_0___M 0xFFFF0000 +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_U__FILL_THRESHOLD_HIGH_0___S 16 +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_U__FILL_THRESHOLD_LOW_0___M 0x0000FFFF +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_U__FILL_THRESHOLD_LOW_0___S 0 +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_U___M 0xFFFFFFFF +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR0_U___S 0 + +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_L (0x003FC198) +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_L___RWC QCSR_REG_RW +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_L___POR 0x00400000 +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_L__WT_MEM_DEPTH_1___POR 0x0040 +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_L__WT_MEM_START_ADR_1___POR 0x0000 +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_L__WT_MEM_DEPTH_1___M 0xFFFF0000 +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_L__WT_MEM_DEPTH_1___S 16 +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_L__WT_MEM_START_ADR_1___M 0x0000FFFF +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_L__WT_MEM_START_ADR_1___S 0 +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_L___M 0xFFFFFFFF +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_L___S 0 + +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_U (0x003FC19C) +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_U___RWC QCSR_REG_RW +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_U___POR 0x00200010 +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_U__FILL_THRESHOLD_HIGH_1___POR 0x0020 +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_U__FILL_THRESHOLD_LOW_1___POR 0x0010 +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_U__FILL_THRESHOLD_HIGH_1___M 0xFFFF0000 +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_U__FILL_THRESHOLD_HIGH_1___S 16 +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_U__FILL_THRESHOLD_LOW_1___M 0x0000FFFF +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_U__FILL_THRESHOLD_LOW_1___S 0 +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_U___M 0xFFFFFFFF +#define PHYA_TXBF_USER_COL_EXPECT_CBF_PARAMS_WR1_U___S 0 + +#define PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_L_n(n) (0x003FC630+0x8*(n)) +#define PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_L_n_nMIN 0 +#define PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_L_n_nMAX 0 +#define PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_L_n_ELEM 1 +#define PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_L_n___RWC QCSR_REG_RW +#define PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_L_n___POR 0x00000000 +#define PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_L_n__DDR_DEST_ADDR_0___POR 0x00000000 +#define PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_L_n__DDR_DEST_ADDR_0___M 0xFFFFFFFF +#define PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_L_n__DDR_DEST_ADDR_0___S 0 +#define PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_L_n___M 0xFFFFFFFF +#define PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_L_n___S 0 +#define PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_L_0 (0x003FC630) +#define PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_L_0___RWC QCSR_REG_RW +#define PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_L_0__DDR_DEST_ADDR_0___M 0xFFFFFFFF +#define PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_L_0__DDR_DEST_ADDR_0___S 0 + +#define PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_U_n(n) (0x003FC634+0x8*(n)) +#define PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_U_n_nMIN 0 +#define PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_U_n_nMAX 0 +#define PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_U_n_ELEM 1 +#define PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_U_n___RWC QCSR_REG_RW +#define PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_U_n___POR 0x00000000 +#define PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_U_n__DDR_DEST_ADDR_1___POR 0x00000000 +#define PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_U_n__DDR_DEST_ADDR_1___M 0xFFFFFFFF +#define PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_U_n__DDR_DEST_ADDR_1___S 0 +#define PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_U_n___M 0xFFFFFFFF +#define PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_U_n___S 0 +#define PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_U_0 (0x003FC634) +#define PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_U_0___RWC QCSR_REG_RW +#define PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_U_0__DDR_DEST_ADDR_1___M 0xFFFFFFFF +#define PHYA_TXBF_DDR_DEST_ADDR_EXPECT_CBF_PARAMS_WR_U_0__DDR_DEST_ADDR_1___S 0 + +#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_SPARE_L (0x003FD030) +#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_SPARE_L___RWC QCSR_REG_RW +#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_SPARE_L___POR 0x00000000 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_SPARE_L__EXPECT_CBF_PARAMS_WR_SPARE_0___POR 0x00000000 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_SPARE_L__EXPECT_CBF_PARAMS_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_SPARE_L__EXPECT_CBF_PARAMS_WR_SPARE_0___S 0 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_SPARE_L___S 0 + +#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_SPARE_U (0x003FD034) +#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_SPARE_U___RWC QCSR_REG_RW +#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_SPARE_U___POR 0x00000000 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_SPARE_U__EXPECT_CBF_PARAMS_WR_SPARE_1___POR 0x00000000 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_SPARE_U__EXPECT_CBF_PARAMS_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_SPARE_U__EXPECT_CBF_PARAMS_WR_SPARE_1___S 0 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_SPARE_U___S 0 + +#define PHYA_TXBF_COMMON_EXPECT_CBF_PARAMS_WR_1_L (0x003FD038) +#define PHYA_TXBF_COMMON_EXPECT_CBF_PARAMS_WR_1_L___RWC QCSR_REG_RW +#define PHYA_TXBF_COMMON_EXPECT_CBF_PARAMS_WR_1_L___POR 0x00000000 +#define PHYA_TXBF_COMMON_EXPECT_CBF_PARAMS_WR_1_L__CBF_NUM_USERS___POR 0x00 +#define PHYA_TXBF_COMMON_EXPECT_CBF_PARAMS_WR_1_L__CBF_TYPE_IS_AX___POR 0x0 +#define PHYA_TXBF_COMMON_EXPECT_CBF_PARAMS_WR_1_L__CBF_NUM_USERS___M 0x00003F00 +#define PHYA_TXBF_COMMON_EXPECT_CBF_PARAMS_WR_1_L__CBF_NUM_USERS___S 8 +#define PHYA_TXBF_COMMON_EXPECT_CBF_PARAMS_WR_1_L__CBF_TYPE_IS_AX___M 0x00000001 +#define PHYA_TXBF_COMMON_EXPECT_CBF_PARAMS_WR_1_L__CBF_TYPE_IS_AX___S 0 +#define PHYA_TXBF_COMMON_EXPECT_CBF_PARAMS_WR_1_L___M 0x00003F01 +#define PHYA_TXBF_COMMON_EXPECT_CBF_PARAMS_WR_1_L___S 0 + +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_L (0x003FD040) +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_L___RWC QCSR_REG_RW +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_L___POR 0x00000000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_L__CBF_CV_MEM_BW20_START_TONE_IDX___POR 0x000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_L__CBF_CV_MEM_BW20_SAVE_EN___POR 0x0 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_L__CBF_CV_MEM_BW20_START_TONE_IDX___M 0x07FF0000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_L__CBF_CV_MEM_BW20_START_TONE_IDX___S 16 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_L__CBF_CV_MEM_BW20_SAVE_EN___M 0x00000001 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_L__CBF_CV_MEM_BW20_SAVE_EN___S 0 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_L___M 0x07FF0001 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_L___S 0 + +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_U (0x003FD044) +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_U___RWC QCSR_REG_RW +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_U___POR 0x00000000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_U__CBF_CV_MEM_BW20_RU_START_IDX___POR 0x00 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_U__CBF_CV_MEM_BW20_NSS___POR 0x0 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_U__CBF_CV_MEM_BW20_END_TONE_IDX___POR 0x000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_U__CBF_CV_MEM_BW20_RU_START_IDX___M 0x7F000000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_U__CBF_CV_MEM_BW20_RU_START_IDX___S 24 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_U__CBF_CV_MEM_BW20_NSS___M 0x00070000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_U__CBF_CV_MEM_BW20_NSS___S 16 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_U__CBF_CV_MEM_BW20_END_TONE_IDX___M 0x000007FF +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_U__CBF_CV_MEM_BW20_END_TONE_IDX___S 0 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_U___M 0x7F0707FF +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_0_U___S 0 + +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_1_L (0x003FD048) +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_1_L___RWC QCSR_REG_RW +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_1_L___POR 0x00000000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_1_L__CBF_CV_MEM_BW20_DEST_BANK_IDX_1___POR 0x0 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_1_L__CBF_CV_MEM_BW20_DEST_BANK_IDX_0___POR 0x0 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_1_L__CBF_CV_MEM_BW20_DEST_BANK_IDX_1___M 0x00000700 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_1_L__CBF_CV_MEM_BW20_DEST_BANK_IDX_1___S 8 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_1_L__CBF_CV_MEM_BW20_DEST_BANK_IDX_0___M 0x00000007 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_1_L__CBF_CV_MEM_BW20_DEST_BANK_IDX_0___S 0 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_1_L___M 0x00000707 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_1_L___S 0 + +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_L (0x003FD050) +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_L___RWC QCSR_REG_RW +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_L___POR 0x00000000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_L__CBF_CV_MEM_BW40_START_TONE_IDX___POR 0x000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_L__CBF_CV_MEM_BW40_SAVE_EN___POR 0x0 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_L__CBF_CV_MEM_BW40_START_TONE_IDX___M 0x07FF0000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_L__CBF_CV_MEM_BW40_START_TONE_IDX___S 16 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_L__CBF_CV_MEM_BW40_SAVE_EN___M 0x00000001 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_L__CBF_CV_MEM_BW40_SAVE_EN___S 0 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_L___M 0x07FF0001 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_L___S 0 + +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_U (0x003FD054) +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_U___RWC QCSR_REG_RW +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_U___POR 0x00000000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_U__CBF_CV_MEM_BW40_RU_START_IDX___POR 0x00 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_U__CBF_CV_MEM_BW40_NSS___POR 0x0 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_U__CBF_CV_MEM_BW40_END_TONE_IDX___POR 0x000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_U__CBF_CV_MEM_BW40_RU_START_IDX___M 0x7F000000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_U__CBF_CV_MEM_BW40_RU_START_IDX___S 24 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_U__CBF_CV_MEM_BW40_NSS___M 0x00070000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_U__CBF_CV_MEM_BW40_NSS___S 16 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_U__CBF_CV_MEM_BW40_END_TONE_IDX___M 0x000007FF +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_U__CBF_CV_MEM_BW40_END_TONE_IDX___S 0 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_U___M 0x7F0707FF +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_2_U___S 0 + +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_3_L (0x003FD058) +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_3_L___RWC QCSR_REG_RW +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_3_L___POR 0x00000000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_3_L__CBF_CV_MEM_BW40_DEST_BANK_IDX_1___POR 0x0 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_3_L__CBF_CV_MEM_BW40_DEST_BANK_IDX_0___POR 0x0 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_3_L__CBF_CV_MEM_BW40_DEST_BANK_IDX_1___M 0x00000700 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_3_L__CBF_CV_MEM_BW40_DEST_BANK_IDX_1___S 8 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_3_L__CBF_CV_MEM_BW40_DEST_BANK_IDX_0___M 0x00000007 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_3_L__CBF_CV_MEM_BW40_DEST_BANK_IDX_0___S 0 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_3_L___M 0x00000707 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_3_L___S 0 + +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_L (0x003FD060) +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_L___RWC QCSR_REG_RW +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_L___POR 0x00000000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_L__CBF_CV_MEM_BW80_START_TONE_IDX___POR 0x000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_L__CBF_CV_MEM_BW80_SAVE_EN___POR 0x0 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_L__CBF_CV_MEM_BW80_START_TONE_IDX___M 0x07FF0000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_L__CBF_CV_MEM_BW80_START_TONE_IDX___S 16 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_L__CBF_CV_MEM_BW80_SAVE_EN___M 0x00000001 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_L__CBF_CV_MEM_BW80_SAVE_EN___S 0 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_L___M 0x07FF0001 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_L___S 0 + +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_U (0x003FD064) +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_U___RWC QCSR_REG_RW +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_U___POR 0x00000000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_U__CBF_CV_MEM_BW80_RU_START_IDX___POR 0x00 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_U__CBF_CV_MEM_BW80_NSS___POR 0x0 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_U__CBF_CV_MEM_BW80_END_TONE_IDX___POR 0x000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_U__CBF_CV_MEM_BW80_RU_START_IDX___M 0x7F000000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_U__CBF_CV_MEM_BW80_RU_START_IDX___S 24 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_U__CBF_CV_MEM_BW80_NSS___M 0x00070000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_U__CBF_CV_MEM_BW80_NSS___S 16 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_U__CBF_CV_MEM_BW80_END_TONE_IDX___M 0x000007FF +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_U__CBF_CV_MEM_BW80_END_TONE_IDX___S 0 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_U___M 0x7F0707FF +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_4_U___S 0 + +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_5_L (0x003FD068) +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_5_L___RWC QCSR_REG_RW +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_5_L___POR 0x00000000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_5_L__CBF_CV_MEM_BW80_DEST_BANK_IDX_1___POR 0x0 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_5_L__CBF_CV_MEM_BW80_DEST_BANK_IDX_0___POR 0x0 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_5_L__CBF_CV_MEM_BW80_DEST_BANK_IDX_1___M 0x00000700 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_5_L__CBF_CV_MEM_BW80_DEST_BANK_IDX_1___S 8 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_5_L__CBF_CV_MEM_BW80_DEST_BANK_IDX_0___M 0x00000007 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_5_L__CBF_CV_MEM_BW80_DEST_BANK_IDX_0___S 0 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_5_L___M 0x00000707 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_5_L___S 0 + +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_L (0x003FD070) +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_L___RWC QCSR_REG_RW +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_L___POR 0x00000000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_L__CBF_CV_MEM_BW160_START_TONE_IDX___POR 0x000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_L__CBF_CV_MEM_BW160_SAVE_EN___POR 0x0 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_L__CBF_CV_MEM_BW160_START_TONE_IDX___M 0x07FF0000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_L__CBF_CV_MEM_BW160_START_TONE_IDX___S 16 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_L__CBF_CV_MEM_BW160_SAVE_EN___M 0x00000001 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_L__CBF_CV_MEM_BW160_SAVE_EN___S 0 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_L___M 0x07FF0001 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_L___S 0 + +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_U (0x003FD074) +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_U___RWC QCSR_REG_RW +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_U___POR 0x00000000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_U__CBF_CV_MEM_BW160_RU_START_IDX___POR 0x00 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_U__CBF_CV_MEM_BW160_NSS___POR 0x0 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_U__CBF_CV_MEM_BW160_END_TONE_IDX___POR 0x000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_U__CBF_CV_MEM_BW160_RU_START_IDX___M 0x7F000000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_U__CBF_CV_MEM_BW160_RU_START_IDX___S 24 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_U__CBF_CV_MEM_BW160_NSS___M 0x00070000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_U__CBF_CV_MEM_BW160_NSS___S 16 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_U__CBF_CV_MEM_BW160_END_TONE_IDX___M 0x000007FF +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_U__CBF_CV_MEM_BW160_END_TONE_IDX___S 0 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_U___M 0x7F0707FF +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_6_U___S 0 + +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_7_L (0x003FD078) +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_7_L___RWC QCSR_REG_RW +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_7_L___POR 0x00000000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_7_L__CBF_CV_MEM_BW160_DEST_BANK_IDX_1___POR 0x0 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_7_L__CBF_CV_MEM_BW160_DEST_BANK_IDX_0___POR 0x0 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_7_L__CBF_CV_MEM_BW160_DEST_BANK_IDX_1___M 0x00000700 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_7_L__CBF_CV_MEM_BW160_DEST_BANK_IDX_1___S 8 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_7_L__CBF_CV_MEM_BW160_DEST_BANK_IDX_0___M 0x00000007 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_7_L__CBF_CV_MEM_BW160_DEST_BANK_IDX_0___S 0 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_7_L___M 0x00000707 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_7_L___S 0 + +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_L (0x003FD080) +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_L___RWC QCSR_REG_RW +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_L___POR 0x00000000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_L__CBF_DDR_START_TONE_IDX___POR 0x000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_L__CBF_DDR_SAVE_EN___POR 0x0 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_L__CBF_DDR_START_TONE_IDX___M 0x07FF0000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_L__CBF_DDR_START_TONE_IDX___S 16 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_L__CBF_DDR_SAVE_EN___M 0x00000001 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_L__CBF_DDR_SAVE_EN___S 0 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_L___M 0x07FF0001 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_L___S 0 + +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_U (0x003FD084) +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_U___RWC QCSR_REG_RW +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_U___POR 0x00000000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_U__CBF_DDR_NSS___POR 0x0 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_U__CBF_DDR_END_TONE_IDX___POR 0x000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_U__CBF_DDR_NSS___M 0x00070000 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_U__CBF_DDR_NSS___S 16 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_U__CBF_DDR_END_TONE_IDX___M 0x000007FF +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_U__CBF_DDR_END_TONE_IDX___S 0 +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_U___M 0x000707FF +#define PHYA_TXBF_USER_EXPECT_CBF_PARAMS_WR_1_8_U___S 0 + +#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_1_SPARE_L (0x003FDAA8) +#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_1_SPARE_L___RWC QCSR_REG_RW +#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_1_SPARE_L___POR 0x00000000 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_1_SPARE_L__EXPECT_CBF_PARAMS_WR_1_SPARE_0___POR 0x00000000 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_1_SPARE_L__EXPECT_CBF_PARAMS_WR_1_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_1_SPARE_L__EXPECT_CBF_PARAMS_WR_1_SPARE_0___S 0 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_1_SPARE_L___M 0xFFFFFFFF +#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_1_SPARE_L___S 0 + +#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_1_SPARE_U (0x003FDAAC) +#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_1_SPARE_U___RWC QCSR_REG_RW +#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_1_SPARE_U___POR 0x00000000 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_1_SPARE_U__EXPECT_CBF_PARAMS_WR_1_SPARE_1___POR 0x00000000 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_1_SPARE_U__EXPECT_CBF_PARAMS_WR_1_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_1_SPARE_U__EXPECT_CBF_PARAMS_WR_1_SPARE_1___S 0 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_1_SPARE_U___M 0xFFFFFFFF +#define PHYA_TXBF_EXPECT_CBF_PARAMS_WR_1_SPARE_U___S 0 + +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_00_L (0x003FDAB0) +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_00_L___RWC QCSR_REG_RO +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_00_L___POR 0x00000000 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_00_L__DMA_DESC_0_0_0___POR 0x00000000 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_00_L__DMA_DESC_0_0_0___M 0xFFFFFFFF +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_00_L__DMA_DESC_0_0_0___S 0 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_00_L___M 0xFFFFFFFF +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_00_L___S 0 + +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_00_U (0x003FDAB4) +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_00_U___RWC QCSR_REG_RO +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_00_U___POR 0x00000000 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_00_U__DMA_DESC_0_1_0___POR 0x00000000 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_00_U__DMA_DESC_0_1_0___M 0xFFFFFFFF +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_00_U__DMA_DESC_0_1_0___S 0 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_00_U___M 0xFFFFFFFF +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_00_U___S 0 + +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_01_L (0x003FDAB8) +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_01_L___RWC QCSR_REG_RO +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_01_L___POR 0x00000000 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_01_L__DMA_DESC_0_0_1___POR 0x00000000 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_01_L__DMA_DESC_0_0_1___M 0xFFFFFFFF +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_01_L__DMA_DESC_0_0_1___S 0 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_01_L___M 0xFFFFFFFF +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_01_L___S 0 + +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_01_U (0x003FDABC) +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_01_U___RWC QCSR_REG_RO +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_01_U___POR 0x00000000 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_01_U__DMA_DESC_0_1_1___POR 0x00000000 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_01_U__DMA_DESC_0_1_1___M 0xFFFFFFFF +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_01_U__DMA_DESC_0_1_1___S 0 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_01_U___M 0xFFFFFFFF +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_01_U___S 0 + +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_02_L (0x003FDAC0) +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_02_L___RWC QCSR_REG_RO +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_02_L___POR 0x00000000 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_02_L__DMA_DESC_0_0_2___POR 0x00000000 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_02_L__DMA_DESC_0_0_2___M 0xFFFFFFFF +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_02_L__DMA_DESC_0_0_2___S 0 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_02_L___M 0xFFFFFFFF +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_02_L___S 0 + +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_02_U (0x003FDAC4) +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_02_U___RWC QCSR_REG_RO +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_02_U___POR 0x00000000 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_02_U__DMA_DESC_0_1_2___POR 0x00000000 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_02_U__DMA_DESC_0_1_2___M 0xFFFFFFFF +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_02_U__DMA_DESC_0_1_2___S 0 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_02_U___M 0xFFFFFFFF +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_02_U___S 0 + +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_10_L (0x003FDAC8) +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_10_L___RWC QCSR_REG_RO +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_10_L___POR 0x00000000 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_10_L__DMA_DESC_1_0_0___POR 0x00000000 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_10_L__DMA_DESC_1_0_0___M 0xFFFFFFFF +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_10_L__DMA_DESC_1_0_0___S 0 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_10_L___M 0xFFFFFFFF +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_10_L___S 0 + +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_10_U (0x003FDACC) +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_10_U___RWC QCSR_REG_RO +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_10_U___POR 0x00000000 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_10_U__DMA_DESC_1_1_0___POR 0x00000000 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_10_U__DMA_DESC_1_1_0___M 0xFFFFFFFF +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_10_U__DMA_DESC_1_1_0___S 0 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_10_U___M 0xFFFFFFFF +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_10_U___S 0 + +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_11_L (0x003FDAD0) +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_11_L___RWC QCSR_REG_RO +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_11_L___POR 0x00000000 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_11_L__DMA_DESC_1_0_1___POR 0x00000000 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_11_L__DMA_DESC_1_0_1___M 0xFFFFFFFF +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_11_L__DMA_DESC_1_0_1___S 0 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_11_L___M 0xFFFFFFFF +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_11_L___S 0 + +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_11_U (0x003FDAD4) +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_11_U___RWC QCSR_REG_RO +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_11_U___POR 0x00000000 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_11_U__DMA_DESC_1_1_1___POR 0x00000000 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_11_U__DMA_DESC_1_1_1___M 0xFFFFFFFF +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_11_U__DMA_DESC_1_1_1___S 0 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_11_U___M 0xFFFFFFFF +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_11_U___S 0 + +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_12_L (0x003FDAD8) +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_12_L___RWC QCSR_REG_RO +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_12_L___POR 0x00000000 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_12_L__DMA_DESC_1_0_2___POR 0x00000000 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_12_L__DMA_DESC_1_0_2___M 0xFFFFFFFF +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_12_L__DMA_DESC_1_0_2___S 0 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_12_L___M 0xFFFFFFFF +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_12_L___S 0 + +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_12_U (0x003FDADC) +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_12_U___RWC QCSR_REG_RO +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_12_U___POR 0x00000000 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_12_U__DMA_DESC_1_1_2___POR 0x00000000 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_12_U__DMA_DESC_1_1_2___M 0xFFFFFFFF +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_12_U__DMA_DESC_1_1_2___S 0 +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_12_U___M 0xFFFFFFFF +#define PHYA_TXBF_EXPECT_CBF_PARAMS_RD_12_U___S 0 + +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_L (0x003FDAE0) +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_L___RWC QCSR_REG_RO +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_L___POR 0x00000000 +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_L__MU___POR 0x0 +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_L__NG___POR 0x0 +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_L__NC___POR 0x0 +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_L__NR___POR 0x0 +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_L__MU___M 0x01000000 +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_L__MU___S 24 +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_L__NG___M 0x00030000 +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_L__NG___S 16 +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_L__NC___M 0x00000700 +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_L__NC___S 8 +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_L__NR___M 0x00000007 +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_L__NR___S 0 +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_L___M 0x01030707 +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_L___S 0 + +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_U (0x003FDAE4) +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_U___RWC QCSR_REG_RO +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_U___POR 0x00000000 +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_U__BW___POR 0x0 +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_U__CB___POR 0x0 +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_U__BW___M 0x00000300 +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_U__BW___S 8 +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_U__CB___M 0x00000001 +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_U__CB___S 0 +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_U___M 0x00000301 +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_0_U___S 0 + +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_1_L (0x003FDAE8) +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_1_L___RWC QCSR_REG_RO +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_1_L___POR 0x00000000 +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_1_L__MIMO_CTRL_0___POR 0x00000000 +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_1_L__MIMO_CTRL_0___M 0xFFFFFFFF +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_1_L__MIMO_CTRL_0___S 0 +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_1_L___M 0xFFFFFFFF +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_1_L___S 0 + +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_1_U (0x003FDAEC) +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_1_U___RWC QCSR_REG_RO +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_1_U___POR 0x00000000 +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_1_U__MIMO_CTRL_1___POR 0x00000000 +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_1_U__MIMO_CTRL_1___M 0xFFFFFFFF +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_1_U__MIMO_CTRL_1___S 0 +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_1_U___M 0xFFFFFFFF +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_1_U___S 0 + +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_2_L (0x003FDAF0) +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_2_L___RWC QCSR_REG_RO +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_2_L___POR 0x00000000 +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_2_L__ASNR___POR 0x00000000 +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_2_L__ASNR___M 0xFFFFFFFF +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_2_L__ASNR___S 0 +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_2_L___M 0xFFFFFFFF +#define PHYA_TXBF_CBF_INFO_USER_CBF_USER_INFO_STATUS_2_L___S 0 + +#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_1_L (0x003FDE58) +#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_1_L___RWC QCSR_REG_RO +#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_1_L___POR 0x00000000 +#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_1_L__EXPECT_CBF_PARAMS_RD_SPARE_0___POR 0x00000000 +#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_1_L__EXPECT_CBF_PARAMS_RD_SPARE_0___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_1_L__EXPECT_CBF_PARAMS_RD_SPARE_0___S 0 +#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_1_L___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_1_L___S 0 + +#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_1_U (0x003FDE5C) +#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_1_U___RWC QCSR_REG_RO +#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_1_U___POR 0x00000000 +#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_1_U__EXPECT_CBF_PARAMS_RD_SPARE_1___POR 0x00000000 +#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_1_U__EXPECT_CBF_PARAMS_RD_SPARE_1___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_1_U__EXPECT_CBF_PARAMS_RD_SPARE_1___S 0 +#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_1_U___M 0xFFFFFFFF +#define PHYA_TXBF_TXBF_PARAMS_RD_SPARE_1_U___S 0 + +#define PHYA_DEMFRONT_0_RESET_CTRL_L (0x00400000) +#define PHYA_DEMFRONT_0_RESET_CTRL_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RESET_CTRL_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RESET_CTRL_L__DYNAMIC_REGS_RESET___POR 0x0 +#define PHYA_DEMFRONT_0_RESET_CTRL_L__DYNAMIC_REGS_RESET___M 0x00000001 +#define PHYA_DEMFRONT_0_RESET_CTRL_L__DYNAMIC_REGS_RESET___S 0 +#define PHYA_DEMFRONT_0_RESET_CTRL_L___M 0x00000001 +#define PHYA_DEMFRONT_0_RESET_CTRL_L___S 0 + +#define PHYA_DEMFRONT_0_ECO_RESET_CTRL_L (0x00400008) +#define PHYA_DEMFRONT_0_ECO_RESET_CTRL_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_ECO_RESET_CTRL_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_ECO_RESET_CTRL_L__ECO_CTRL___POR 0x00000000 +#define PHYA_DEMFRONT_0_ECO_RESET_CTRL_L__ECO_CTRL___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_ECO_RESET_CTRL_L__ECO_CTRL___S 0 +#define PHYA_DEMFRONT_0_ECO_RESET_CTRL_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_ECO_RESET_CTRL_L___S 0 + +#define PHYA_DEMFRONT_0_ECO_RESET_CTRL_U (0x0040000C) +#define PHYA_DEMFRONT_0_ECO_RESET_CTRL_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_ECO_RESET_CTRL_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_ECO_RESET_CTRL_U__ECO_DATA___POR 0x00000000 +#define PHYA_DEMFRONT_0_ECO_RESET_CTRL_U__ECO_DATA___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_ECO_RESET_CTRL_U__ECO_DATA___S 0 +#define PHYA_DEMFRONT_0_ECO_RESET_CTRL_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_ECO_RESET_CTRL_U___S 0 + +#define PHYA_DEMFRONT_0_EVENT_STATUS_L (0x00400010) +#define PHYA_DEMFRONT_0_EVENT_STATUS_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_EVENT_STATUS_L___POR 0x000000C4 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__SPARE15_EVENT___POR 0x0 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__SPARE14_EVENT___POR 0x0 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__SPARE13_EVENT___POR 0x0 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__SPARE12_EVENT___POR 0x0 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__PER_PKT_PROGRAM_EVENT___POR 0x0 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__RU_BD_PTC_HW_UPDATE_EVENT___POR 0x0 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__PROC_COMPLETE_EVENT___POR 0x0 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__RXTD_NOISEPWR_BTCF_EVENT___POR 0x1 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__RXTD_GAIN_RATIO_EVENT___POR 0x1 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__RLSIG_DET_EVENT___POR 0x0 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__QBPSK_DET_EVENT___POR 0x0 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__NEXT_RU_DESC_EVENT___POR 0x0 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__NEXT_DESC_EVENT___POR 0x1 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__ECO_EVENT___POR 0x0 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__ERROR_EVENT___POR 0x0 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__SPARE15_EVENT___M 0x00008000 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__SPARE15_EVENT___S 15 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__SPARE14_EVENT___M 0x00004000 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__SPARE14_EVENT___S 14 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__SPARE13_EVENT___M 0x00002000 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__SPARE13_EVENT___S 13 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__SPARE12_EVENT___M 0x00001000 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__SPARE12_EVENT___S 12 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__PER_PKT_PROGRAM_EVENT___M 0x00000800 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__PER_PKT_PROGRAM_EVENT___S 11 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__RU_BD_PTC_HW_UPDATE_EVENT___M 0x00000400 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__RU_BD_PTC_HW_UPDATE_EVENT___S 10 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__PROC_COMPLETE_EVENT___M 0x00000100 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__PROC_COMPLETE_EVENT___S 8 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__RXTD_NOISEPWR_BTCF_EVENT___M 0x00000080 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__RXTD_NOISEPWR_BTCF_EVENT___S 7 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__RXTD_GAIN_RATIO_EVENT___M 0x00000040 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__RXTD_GAIN_RATIO_EVENT___S 6 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__RLSIG_DET_EVENT___M 0x00000020 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__RLSIG_DET_EVENT___S 5 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__QBPSK_DET_EVENT___M 0x00000010 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__QBPSK_DET_EVENT___S 4 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__NEXT_RU_DESC_EVENT___M 0x00000008 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__NEXT_RU_DESC_EVENT___S 3 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__NEXT_DESC_EVENT___M 0x00000004 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__NEXT_DESC_EVENT___S 2 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__ECO_EVENT___M 0x00000002 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__ECO_EVENT___S 1 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__ERROR_EVENT___M 0x00000001 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L__ERROR_EVENT___S 0 +#define PHYA_DEMFRONT_0_EVENT_STATUS_L___M 0x0000FDFF +#define PHYA_DEMFRONT_0_EVENT_STATUS_L___S 0 + +#define PHYA_DEMFRONT_0_EVENT_MASK_L (0x00400018) +#define PHYA_DEMFRONT_0_EVENT_MASK_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_EVENT_MASK_L___POR 0x0000FDFF +#define PHYA_DEMFRONT_0_EVENT_MASK_L__SPARE15_EVENT_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__SPARE14_EVENT_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__SPARE13_EVENT_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__SPARE12_EVENT_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__PER_PKT_PROGRAM_EVENT_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__RU_BD_PTC_HW_UPDATE_EVENT_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__PROC_COMPLETE_EVENT_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__RXTD_NOISEPWR_BTCF_EVENT_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__RXTD_GAIN_RATIO_EVENT_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__RLSIG_DET_EVENT_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__QBPSK_DET_EVENT_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__NEXT_RU_DESC_EVENT_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__NEXT_DESC_EVENT_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__ECO_EVENT_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__ERROR_EVENT_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__SPARE15_EVENT_MASK___M 0x00008000 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__SPARE15_EVENT_MASK___S 15 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__SPARE14_EVENT_MASK___M 0x00004000 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__SPARE14_EVENT_MASK___S 14 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__SPARE13_EVENT_MASK___M 0x00002000 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__SPARE13_EVENT_MASK___S 13 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__SPARE12_EVENT_MASK___M 0x00001000 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__SPARE12_EVENT_MASK___S 12 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__PER_PKT_PROGRAM_EVENT_MASK___M 0x00000800 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__PER_PKT_PROGRAM_EVENT_MASK___S 11 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__RU_BD_PTC_HW_UPDATE_EVENT_MASK___M 0x00000400 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__RU_BD_PTC_HW_UPDATE_EVENT_MASK___S 10 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__PROC_COMPLETE_EVENT_MASK___M 0x00000100 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__PROC_COMPLETE_EVENT_MASK___S 8 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__RXTD_NOISEPWR_BTCF_EVENT_MASK___M 0x00000080 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__RXTD_NOISEPWR_BTCF_EVENT_MASK___S 7 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__RXTD_GAIN_RATIO_EVENT_MASK___M 0x00000040 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__RXTD_GAIN_RATIO_EVENT_MASK___S 6 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__RLSIG_DET_EVENT_MASK___M 0x00000020 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__RLSIG_DET_EVENT_MASK___S 5 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__QBPSK_DET_EVENT_MASK___M 0x00000010 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__QBPSK_DET_EVENT_MASK___S 4 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__NEXT_RU_DESC_EVENT_MASK___M 0x00000008 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__NEXT_RU_DESC_EVENT_MASK___S 3 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__NEXT_DESC_EVENT_MASK___M 0x00000004 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__NEXT_DESC_EVENT_MASK___S 2 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__ECO_EVENT_MASK___M 0x00000002 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__ECO_EVENT_MASK___S 1 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__ERROR_EVENT_MASK___M 0x00000001 +#define PHYA_DEMFRONT_0_EVENT_MASK_L__ERROR_EVENT_MASK___S 0 +#define PHYA_DEMFRONT_0_EVENT_MASK_L___M 0x0000FDFF +#define PHYA_DEMFRONT_0_EVENT_MASK_L___S 0 + +#define PHYA_DEMFRONT_0_ERROR_MASK_L (0x00400020) +#define PHYA_DEMFRONT_0_ERROR_MASK_L___RWC QCSR_REG_RO +#define PHYA_DEMFRONT_0_ERROR_MASK_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_ERROR_MASK_L__ERROR_CODE___POR 0x00 +#define PHYA_DEMFRONT_0_ERROR_MASK_L__ERROR_CODE___M 0x0000003F +#define PHYA_DEMFRONT_0_ERROR_MASK_L__ERROR_CODE___S 0 +#define PHYA_DEMFRONT_0_ERROR_MASK_L___M 0x0000003F +#define PHYA_DEMFRONT_0_ERROR_MASK_L___S 0 + +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L (0x00400028) +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__QRE_RU_STOMP_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__CBFG_RU_STOMP_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__CHE_RU_STOMP_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__PTC_RU_STOMP_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__MRC_RU_STOMP_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SYM_PROC_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__PCNT_STUCK_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__PTC_MISALIGNMENT_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__CV2V_MISALIGNMENT_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__MRC_TONE_MISALIGNMENT_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__LLR_MISALIGNMENT_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__ILLEGAL_QRE_REQUEST_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__ILLEGAL_RATE_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SDF_REQUEST_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SPARE13_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SPARE12_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SPARE11_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SPARE10_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__PER_PKT_PROGRAM_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__RU_BD_PTC_HW_UPDATE_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__PROC_COMPLETE_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__RXTD_NOISEPWR_BTCF_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__RXTD_GAIN_RATIO_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__RLSIG_DET_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__QBPSK_DET_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__NEXT_RU_DESC_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__NEXT_DESC_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__QRE_RU_STOMP_ERROR___M 0x80000000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__QRE_RU_STOMP_ERROR___S 31 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__CBFG_RU_STOMP_ERROR___M 0x40000000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__CBFG_RU_STOMP_ERROR___S 30 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__CHE_RU_STOMP_ERROR___M 0x10000000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__CHE_RU_STOMP_ERROR___S 28 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__PTC_RU_STOMP_ERROR___M 0x08000000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__PTC_RU_STOMP_ERROR___S 27 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__MRC_RU_STOMP_ERROR___M 0x04000000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__MRC_RU_STOMP_ERROR___S 26 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SYM_PROC_ERROR___M 0x01000000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SYM_PROC_ERROR___S 24 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__PCNT_STUCK_ERROR___M 0x00800000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__PCNT_STUCK_ERROR___S 23 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__PTC_MISALIGNMENT_ERROR___M 0x00400000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__PTC_MISALIGNMENT_ERROR___S 22 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__CV2V_MISALIGNMENT_ERROR___M 0x00200000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__CV2V_MISALIGNMENT_ERROR___S 21 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__MRC_TONE_MISALIGNMENT_ERROR___M 0x00100000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__MRC_TONE_MISALIGNMENT_ERROR___S 20 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__LLR_MISALIGNMENT_ERROR___M 0x00080000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__LLR_MISALIGNMENT_ERROR___S 19 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__ILLEGAL_QRE_REQUEST_ERROR___M 0x00010000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__ILLEGAL_QRE_REQUEST_ERROR___S 16 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__ILLEGAL_RATE_ERROR___M 0x00008000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__ILLEGAL_RATE_ERROR___S 15 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SDF_REQUEST_ERROR___M 0x00004000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SDF_REQUEST_ERROR___S 14 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SPARE13_ERROR___M 0x00002000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SPARE13_ERROR___S 13 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SPARE12_ERROR___M 0x00001000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SPARE12_ERROR___S 12 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SPARE11_ERROR___M 0x00000800 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SPARE11_ERROR___S 11 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SPARE10_ERROR___M 0x00000400 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__SPARE10_ERROR___S 10 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__PER_PKT_PROGRAM_ERROR___M 0x00000200 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__PER_PKT_PROGRAM_ERROR___S 9 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__RU_BD_PTC_HW_UPDATE_ERROR___M 0x00000100 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__RU_BD_PTC_HW_UPDATE_ERROR___S 8 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__PROC_COMPLETE_ERROR___M 0x00000040 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__PROC_COMPLETE_ERROR___S 6 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__RXTD_NOISEPWR_BTCF_ERROR___M 0x00000020 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__RXTD_NOISEPWR_BTCF_ERROR___S 5 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__RXTD_GAIN_RATIO_ERROR___M 0x00000010 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__RXTD_GAIN_RATIO_ERROR___S 4 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__RLSIG_DET_ERROR___M 0x00000008 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__RLSIG_DET_ERROR___S 3 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__QBPSK_DET_ERROR___M 0x00000004 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__QBPSK_DET_ERROR___S 2 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__NEXT_RU_DESC_ERROR___M 0x00000002 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__NEXT_RU_DESC_ERROR___S 1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__NEXT_DESC_ERROR___M 0x00000001 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L__NEXT_DESC_ERROR___S 0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L___M 0xDDF9FF7F +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_L___S 0 + +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U (0x0040002C) +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE63_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE62_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE61_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE60_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE59_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE58_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE57_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE56_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE55_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE54_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE53_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE52_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE51_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE50_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE49_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE48_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE47_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE46_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE45_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE44_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE43_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__LLR_STREAM_MISALIGNMENT_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__MRC_STREAM_MISALIGNMENT_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__QRE_STREAM_MISALIGNMENT_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__NP_STREAM_MISALIGNMENT_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__ROBE_RU_STOMP_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__FDPP_RU_STOMP_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__FTE_RU_STOMP_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__NP_RU_STOMP_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__LLR_RU_STOMP_ERROR___POR 0x0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE63_ERROR___M 0x80000000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE63_ERROR___S 31 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE62_ERROR___M 0x40000000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE62_ERROR___S 30 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE61_ERROR___M 0x20000000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE61_ERROR___S 29 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE60_ERROR___M 0x10000000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE60_ERROR___S 28 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE59_ERROR___M 0x08000000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE59_ERROR___S 27 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE58_ERROR___M 0x04000000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE58_ERROR___S 26 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE57_ERROR___M 0x02000000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE57_ERROR___S 25 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE56_ERROR___M 0x01000000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE56_ERROR___S 24 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE55_ERROR___M 0x00800000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE55_ERROR___S 23 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE54_ERROR___M 0x00400000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE54_ERROR___S 22 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE53_ERROR___M 0x00200000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE53_ERROR___S 21 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE52_ERROR___M 0x00100000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE52_ERROR___S 20 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE51_ERROR___M 0x00080000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE51_ERROR___S 19 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE50_ERROR___M 0x00040000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE50_ERROR___S 18 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE49_ERROR___M 0x00020000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE49_ERROR___S 17 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE48_ERROR___M 0x00010000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE48_ERROR___S 16 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE47_ERROR___M 0x00008000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE47_ERROR___S 15 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE46_ERROR___M 0x00004000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE46_ERROR___S 14 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE45_ERROR___M 0x00002000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE45_ERROR___S 13 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE44_ERROR___M 0x00001000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE44_ERROR___S 12 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE43_ERROR___M 0x00000800 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__SPARE43_ERROR___S 11 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__LLR_STREAM_MISALIGNMENT_ERROR___M 0x00000400 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__LLR_STREAM_MISALIGNMENT_ERROR___S 10 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__MRC_STREAM_MISALIGNMENT_ERROR___M 0x00000200 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__MRC_STREAM_MISALIGNMENT_ERROR___S 9 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__QRE_STREAM_MISALIGNMENT_ERROR___M 0x00000100 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__QRE_STREAM_MISALIGNMENT_ERROR___S 8 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__NP_STREAM_MISALIGNMENT_ERROR___M 0x00000080 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__NP_STREAM_MISALIGNMENT_ERROR___S 7 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__ROBE_RU_STOMP_ERROR___M 0x00000010 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__ROBE_RU_STOMP_ERROR___S 4 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__FDPP_RU_STOMP_ERROR___M 0x00000008 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__FDPP_RU_STOMP_ERROR___S 3 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__FTE_RU_STOMP_ERROR___M 0x00000004 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__FTE_RU_STOMP_ERROR___S 2 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__NP_RU_STOMP_ERROR___M 0x00000002 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__NP_RU_STOMP_ERROR___S 1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__LLR_RU_STOMP_ERROR___M 0x00000001 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U__LLR_RU_STOMP_ERROR___S 0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U___M 0xFFFFFF9F +#define PHYA_DEMFRONT_0_ERROR_ERROR_STATUS_U___S 0 + +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L (0x00400030) +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L___POR 0xDDF9FF7F +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__QRE_RU_STOMP_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__CBFG_RU_STOMP_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__CHE_RU_STOMP_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__PTC_RU_STOMP_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__MRC_RU_STOMP_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SYM_PROC_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__PCNT_STUCK_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__PTC_MISALIGNMENT_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__CV2V_MISALIGNMENT_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__MRC_TONE_MISALIGNMENT_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__LLR_MISALIGNMENT_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__ILLEGAL_QRE_REQUEST_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__ILLEGAL_RATE_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SDF_REQUEST_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SPARE13_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SPARE12_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SPARE11_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SPARE10_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__PER_PKT_PROGRAM_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__RU_BD_PTC_HW_UPDATE_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__PROC_COMPLETE_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__RXTD_NOISEPWR_BTCF_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__RXTD_GAIN_RATIO_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__RLSIG_DET_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__QBPSK_DET_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__NEXT_RU_DESC_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__NEXT_DESC_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__QRE_RU_STOMP_ERROR_MASK___M 0x80000000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__QRE_RU_STOMP_ERROR_MASK___S 31 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__CBFG_RU_STOMP_ERROR_MASK___M 0x40000000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__CBFG_RU_STOMP_ERROR_MASK___S 30 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__CHE_RU_STOMP_ERROR_MASK___M 0x10000000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__CHE_RU_STOMP_ERROR_MASK___S 28 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__PTC_RU_STOMP_ERROR_MASK___M 0x08000000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__PTC_RU_STOMP_ERROR_MASK___S 27 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__MRC_RU_STOMP_ERROR_MASK___M 0x04000000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__MRC_RU_STOMP_ERROR_MASK___S 26 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SYM_PROC_ERROR_MASK___M 0x01000000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SYM_PROC_ERROR_MASK___S 24 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__PCNT_STUCK_ERROR_MASK___M 0x00800000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__PCNT_STUCK_ERROR_MASK___S 23 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__PTC_MISALIGNMENT_ERROR_MASK___M 0x00400000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__PTC_MISALIGNMENT_ERROR_MASK___S 22 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__CV2V_MISALIGNMENT_ERROR_MASK___M 0x00200000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__CV2V_MISALIGNMENT_ERROR_MASK___S 21 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__MRC_TONE_MISALIGNMENT_ERROR_MASK___M 0x00100000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__MRC_TONE_MISALIGNMENT_ERROR_MASK___S 20 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__LLR_MISALIGNMENT_ERROR_MASK___M 0x00080000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__LLR_MISALIGNMENT_ERROR_MASK___S 19 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__ILLEGAL_QRE_REQUEST_ERROR_MASK___M 0x00010000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__ILLEGAL_QRE_REQUEST_ERROR_MASK___S 16 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__ILLEGAL_RATE_ERROR_MASK___M 0x00008000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__ILLEGAL_RATE_ERROR_MASK___S 15 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SDF_REQUEST_ERROR_MASK___M 0x00004000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SDF_REQUEST_ERROR_MASK___S 14 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SPARE13_ERROR_MASK___M 0x00002000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SPARE13_ERROR_MASK___S 13 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SPARE12_ERROR_MASK___M 0x00001000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SPARE12_ERROR_MASK___S 12 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SPARE11_ERROR_MASK___M 0x00000800 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SPARE11_ERROR_MASK___S 11 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SPARE10_ERROR_MASK___M 0x00000400 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__SPARE10_ERROR_MASK___S 10 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__PER_PKT_PROGRAM_ERROR_MASK___M 0x00000200 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__PER_PKT_PROGRAM_ERROR_MASK___S 9 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__RU_BD_PTC_HW_UPDATE_ERROR_MASK___M 0x00000100 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__RU_BD_PTC_HW_UPDATE_ERROR_MASK___S 8 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__PROC_COMPLETE_ERROR_MASK___M 0x00000040 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__PROC_COMPLETE_ERROR_MASK___S 6 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__RXTD_NOISEPWR_BTCF_ERROR_MASK___M 0x00000020 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__RXTD_NOISEPWR_BTCF_ERROR_MASK___S 5 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__RXTD_GAIN_RATIO_ERROR_MASK___M 0x00000010 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__RXTD_GAIN_RATIO_ERROR_MASK___S 4 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__RLSIG_DET_ERROR_MASK___M 0x00000008 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__RLSIG_DET_ERROR_MASK___S 3 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__QBPSK_DET_ERROR_MASK___M 0x00000004 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__QBPSK_DET_ERROR_MASK___S 2 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__NEXT_RU_DESC_ERROR_MASK___M 0x00000002 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__NEXT_RU_DESC_ERROR_MASK___S 1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__NEXT_DESC_ERROR_MASK___M 0x00000001 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L__NEXT_DESC_ERROR_MASK___S 0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L___M 0xDDF9FF7F +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_L___S 0 + +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U (0x00400034) +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U___POR 0xFFFFFF9F +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE63_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE62_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE61_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE60_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE59_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE58_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE57_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE56_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE55_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE54_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE53_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE52_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE51_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE50_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE49_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE48_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE47_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE46_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE45_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE44_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE43_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__LLR_STREAM_MISALIGNMENT_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__MRC_STREAM_MISALIGNMENT_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__QRE_STREAM_MISALIGNMENT_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__NP_STREAM_MISALIGNMENT_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__ROBE_RU_STOMP_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__FDPP_RU_STOMP_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__FTE_RU_STOMP_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__NP_RU_STOMP_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__LLR_RU_STOMP_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE63_ERROR_MASK___M 0x80000000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE63_ERROR_MASK___S 31 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE62_ERROR_MASK___M 0x40000000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE62_ERROR_MASK___S 30 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE61_ERROR_MASK___M 0x20000000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE61_ERROR_MASK___S 29 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE60_ERROR_MASK___M 0x10000000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE60_ERROR_MASK___S 28 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE59_ERROR_MASK___M 0x08000000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE59_ERROR_MASK___S 27 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE58_ERROR_MASK___M 0x04000000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE58_ERROR_MASK___S 26 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE57_ERROR_MASK___M 0x02000000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE57_ERROR_MASK___S 25 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE56_ERROR_MASK___M 0x01000000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE56_ERROR_MASK___S 24 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE55_ERROR_MASK___M 0x00800000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE55_ERROR_MASK___S 23 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE54_ERROR_MASK___M 0x00400000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE54_ERROR_MASK___S 22 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE53_ERROR_MASK___M 0x00200000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE53_ERROR_MASK___S 21 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE52_ERROR_MASK___M 0x00100000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE52_ERROR_MASK___S 20 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE51_ERROR_MASK___M 0x00080000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE51_ERROR_MASK___S 19 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE50_ERROR_MASK___M 0x00040000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE50_ERROR_MASK___S 18 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE49_ERROR_MASK___M 0x00020000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE49_ERROR_MASK___S 17 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE48_ERROR_MASK___M 0x00010000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE48_ERROR_MASK___S 16 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE47_ERROR_MASK___M 0x00008000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE47_ERROR_MASK___S 15 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE46_ERROR_MASK___M 0x00004000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE46_ERROR_MASK___S 14 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE45_ERROR_MASK___M 0x00002000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE45_ERROR_MASK___S 13 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE44_ERROR_MASK___M 0x00001000 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE44_ERROR_MASK___S 12 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE43_ERROR_MASK___M 0x00000800 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__SPARE43_ERROR_MASK___S 11 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__LLR_STREAM_MISALIGNMENT_ERROR_MASK___M 0x00000400 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__LLR_STREAM_MISALIGNMENT_ERROR_MASK___S 10 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__MRC_STREAM_MISALIGNMENT_ERROR_MASK___M 0x00000200 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__MRC_STREAM_MISALIGNMENT_ERROR_MASK___S 9 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__QRE_STREAM_MISALIGNMENT_ERROR_MASK___M 0x00000100 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__QRE_STREAM_MISALIGNMENT_ERROR_MASK___S 8 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__NP_STREAM_MISALIGNMENT_ERROR_MASK___M 0x00000080 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__NP_STREAM_MISALIGNMENT_ERROR_MASK___S 7 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__ROBE_RU_STOMP_ERROR_MASK___M 0x00000010 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__ROBE_RU_STOMP_ERROR_MASK___S 4 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__FDPP_RU_STOMP_ERROR_MASK___M 0x00000008 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__FDPP_RU_STOMP_ERROR_MASK___S 3 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__FTE_RU_STOMP_ERROR_MASK___M 0x00000004 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__FTE_RU_STOMP_ERROR_MASK___S 2 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__NP_RU_STOMP_ERROR_MASK___M 0x00000002 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__NP_RU_STOMP_ERROR_MASK___S 1 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__LLR_RU_STOMP_ERROR_MASK___M 0x00000001 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U__LLR_RU_STOMP_ERROR_MASK___S 0 +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U___M 0xFFFFFF9F +#define PHYA_DEMFRONT_0_ERROR_ERROR_MASK_U___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_L (0x00400038) +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_L___POR 0x01000034 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_L__N_DC_TONE___POR 0x1 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_L__N_PILOT_TONE___POR 0x00 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_L__N_DATA_TONE___POR 0x034 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_L__N_DC_TONE___M 0x07000000 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_L__N_DC_TONE___S 24 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_L__N_PILOT_TONE___M 0x001F0000 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_L__N_PILOT_TONE___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_L__N_DATA_TONE___M 0x000003FF +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_L__N_DATA_TONE___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_L___M 0x071F03FF +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_U (0x0040003C) +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_U___POR 0x00640000 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_U__WAIT_CYCLES___POR 0x064 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_U__EQUALIZER_TYPE___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_U__WAIT_CYCLES___M 0x01FF0000 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_U__WAIT_CYCLES___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_U__EQUALIZER_TYPE___M 0x00000007 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_U__EQUALIZER_TYPE___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_U___M 0x01FF0007 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_0_U___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_1_L (0x00400040) +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_1_L___POR 0xFFE6FFE6 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_1_L__START_TONE_1___POR 0xFFE6 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_1_L__START_TONE_0___POR 0xFFE6 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_1_L__START_TONE_1___M 0xFFFF0000 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_1_L__START_TONE_1___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_1_L__START_TONE_0___M 0x0000FFFF +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_1_L__START_TONE_0___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_1_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_1_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_L (0x00400048) +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_L___POR 0x00010100 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_L__N_USER___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_L__LAST_RU___POR 0x1 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_L__FIRST_RU___POR 0x1 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_L__IS_STBC___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_L__N_USER___M 0x0F000000 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_L__N_USER___S 24 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_L__LAST_RU___M 0x00010000 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_L__LAST_RU___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_L__FIRST_RU___M 0x00000100 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_L__FIRST_RU___S 8 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_L__IS_STBC___M 0x00000001 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_L__IS_STBC___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_L___M 0x0F010101 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_U (0x0040004C) +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_U___POR 0x00001003 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_U__NOTCH_FREQ_SHIFT___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_U__THROTTLE_RATE___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_U__N_COL___POR 0x10 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_U__N_ROW___POR 0x03 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_U__NOTCH_FREQ_SHIFT___M 0x0F000000 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_U__NOTCH_FREQ_SHIFT___S 24 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_U__THROTTLE_RATE___M 0x00070000 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_U__THROTTLE_RATE___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_U__N_COL___M 0x00003F00 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_U__N_COL___S 8 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_U__N_ROW___M 0x0000001F +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_U__N_ROW___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_U___M 0x0F073F1F +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_2_U___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_L (0x00400050) +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_L__DCM_POLARITY___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_L__ENA_DCM___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_L__N_SD_SHORT___POR 0x000 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_L__DCM_POLARITY___M 0x01000000 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_L__DCM_POLARITY___S 24 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_L__ENA_DCM___M 0x00010000 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_L__ENA_DCM___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_L__N_SD_SHORT___M 0x000003FF +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_L__N_SD_SHORT___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_L___M 0x010103FF +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_U (0x00400054) +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_U__ENA_UPBAND_FLIP___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_U__RESET_EVM___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_U__COMPUTE_EVM___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_U__RUBD_FW_LOAD___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_U__ENA_UPBAND_FLIP___M 0x01000000 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_U__ENA_UPBAND_FLIP___S 24 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_U__RESET_EVM___M 0x00010000 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_U__RESET_EVM___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_U__COMPUTE_EVM___M 0x00000100 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_U__COMPUTE_EVM___S 8 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_U__RUBD_FW_LOAD___M 0x00000001 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_U__RUBD_FW_LOAD___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_U___M 0x01010101 +#define PHYA_DEMFRONT_0_RUUD_RU_UD_CONTROL_3_U___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_CMD_L (0x00400058) +#define PHYA_DEMFRONT_0_RUUD_RU_CMD_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_CMD_L___POR 0x00000001 +#define PHYA_DEMFRONT_0_RUUD_RU_CMD_L__CMD_3___POR 0x00 +#define PHYA_DEMFRONT_0_RUUD_RU_CMD_L__CMD_2___POR 0x00 +#define PHYA_DEMFRONT_0_RUUD_RU_CMD_L__CMD_1___POR 0x00 +#define PHYA_DEMFRONT_0_RUUD_RU_CMD_L__CMD_0___POR 0x01 +#define PHYA_DEMFRONT_0_RUUD_RU_CMD_L__CMD_3___M 0xFF000000 +#define PHYA_DEMFRONT_0_RUUD_RU_CMD_L__CMD_3___S 24 +#define PHYA_DEMFRONT_0_RUUD_RU_CMD_L__CMD_2___M 0x00FF0000 +#define PHYA_DEMFRONT_0_RUUD_RU_CMD_L__CMD_2___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_CMD_L__CMD_1___M 0x0000FF00 +#define PHYA_DEMFRONT_0_RUUD_RU_CMD_L__CMD_1___S 8 +#define PHYA_DEMFRONT_0_RUUD_RU_CMD_L__CMD_0___M 0x000000FF +#define PHYA_DEMFRONT_0_RUUD_RU_CMD_L__CMD_0___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_CMD_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_RU_CMD_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_CMD_U (0x0040005C) +#define PHYA_DEMFRONT_0_RUUD_RU_CMD_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_CMD_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_CMD_U__CMD_7___POR 0x00 +#define PHYA_DEMFRONT_0_RUUD_RU_CMD_U__CMD_6___POR 0x00 +#define PHYA_DEMFRONT_0_RUUD_RU_CMD_U__CMD_5___POR 0x00 +#define PHYA_DEMFRONT_0_RUUD_RU_CMD_U__CMD_4___POR 0x00 +#define PHYA_DEMFRONT_0_RUUD_RU_CMD_U__CMD_7___M 0xFF000000 +#define PHYA_DEMFRONT_0_RUUD_RU_CMD_U__CMD_7___S 24 +#define PHYA_DEMFRONT_0_RUUD_RU_CMD_U__CMD_6___M 0x00FF0000 +#define PHYA_DEMFRONT_0_RUUD_RU_CMD_U__CMD_6___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_CMD_U__CMD_5___M 0x0000FF00 +#define PHYA_DEMFRONT_0_RUUD_RU_CMD_U__CMD_5___S 8 +#define PHYA_DEMFRONT_0_RUUD_RU_CMD_U__CMD_4___M 0x000000FF +#define PHYA_DEMFRONT_0_RUUD_RU_CMD_U__CMD_4___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_CMD_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_RU_CMD_U___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT0_L (0x00400060) +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT0_L___POR 0xFFF9FFEB +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT0_L__PILOT_INDEX_1_0___POR 0xFFF9 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT0_L__PILOT_INDEX_0_0___POR 0xFFEB +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT0_L__PILOT_INDEX_1_0___M 0xFFFF0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT0_L__PILOT_INDEX_1_0___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT0_L__PILOT_INDEX_0_0___M 0x0000FFFF +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT0_L__PILOT_INDEX_0_0___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT0_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT0_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT0_U (0x00400064) +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT0_U___POR 0x00150007 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT0_U__PILOT_INDEX_3_0___POR 0x0015 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT0_U__PILOT_INDEX_2_0___POR 0x0007 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT0_U__PILOT_INDEX_3_0___M 0xFFFF0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT0_U__PILOT_INDEX_3_0___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT0_U__PILOT_INDEX_2_0___M 0x0000FFFF +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT0_U__PILOT_INDEX_2_0___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT0_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT0_U___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT1_L (0x00400068) +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT1_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT1_L__PILOT_INDEX_1_1___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT1_L__PILOT_INDEX_0_1___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT1_L__PILOT_INDEX_1_1___M 0xFFFF0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT1_L__PILOT_INDEX_1_1___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT1_L__PILOT_INDEX_0_1___M 0x0000FFFF +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT1_L__PILOT_INDEX_0_1___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT1_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT1_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT1_U (0x0040006C) +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT1_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT1_U__PILOT_INDEX_3_1___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT1_U__PILOT_INDEX_2_1___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT1_U__PILOT_INDEX_3_1___M 0xFFFF0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT1_U__PILOT_INDEX_3_1___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT1_U__PILOT_INDEX_2_1___M 0x0000FFFF +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT1_U__PILOT_INDEX_2_1___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT1_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT1_U___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT2_L (0x00400070) +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT2_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT2_L__PILOT_INDEX_1_2___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT2_L__PILOT_INDEX_0_2___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT2_L__PILOT_INDEX_1_2___M 0xFFFF0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT2_L__PILOT_INDEX_1_2___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT2_L__PILOT_INDEX_0_2___M 0x0000FFFF +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT2_L__PILOT_INDEX_0_2___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT2_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT2_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT2_U (0x00400074) +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT2_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT2_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT2_U__PILOT_INDEX_3_2___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT2_U__PILOT_INDEX_2_2___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT2_U__PILOT_INDEX_3_2___M 0xFFFF0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT2_U__PILOT_INDEX_3_2___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT2_U__PILOT_INDEX_2_2___M 0x0000FFFF +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT2_U__PILOT_INDEX_2_2___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT2_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT2_U___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT3_L (0x00400078) +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT3_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT3_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT3_L__PILOT_INDEX_1_3___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT3_L__PILOT_INDEX_0_3___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT3_L__PILOT_INDEX_1_3___M 0xFFFF0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT3_L__PILOT_INDEX_1_3___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT3_L__PILOT_INDEX_0_3___M 0x0000FFFF +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT3_L__PILOT_INDEX_0_3___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT3_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT3_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT3_U (0x0040007C) +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT3_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT3_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT3_U__PILOT_INDEX_3_3___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT3_U__PILOT_INDEX_2_3___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT3_U__PILOT_INDEX_3_3___M 0xFFFF0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT3_U__PILOT_INDEX_3_3___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT3_U__PILOT_INDEX_2_3___M 0x0000FFFF +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT3_U__PILOT_INDEX_2_3___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT3_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_RU_PILOT3_U___S 0 + +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_L (0x00400080) +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_L__QAM_0___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_L__IS_LDPC_0___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_L__N_SS_0___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_L__USER_ID_0___POR 0x00 +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_L__QAM_0___M 0x07000000 +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_L__QAM_0___S 24 +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_L__IS_LDPC_0___M 0x00010000 +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_L__IS_LDPC_0___S 16 +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_L__N_SS_0___M 0x00000F00 +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_L__N_SS_0___S 8 +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_L__USER_ID_0___M 0x0000003F +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_L__USER_ID_0___S 0 +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_L___M 0x07010F3F +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_U (0x00400084) +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_U__LDPC_LLR_SCALE_0___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_U__LDPC_LLR_SCALE_0___M 0x00000007 +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_U__LDPC_LLR_SCALE_0___S 0 +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_U___M 0x00000007 +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL0_U___S 0 + +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_L (0x00400088) +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_L__QAM_1___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_L__IS_LDPC_1___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_L__N_SS_1___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_L__USER_ID_1___POR 0x00 +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_L__QAM_1___M 0x07000000 +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_L__QAM_1___S 24 +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_L__IS_LDPC_1___M 0x00010000 +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_L__IS_LDPC_1___S 16 +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_L__N_SS_1___M 0x00000F00 +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_L__N_SS_1___S 8 +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_L__USER_ID_1___M 0x0000003F +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_L__USER_ID_1___S 0 +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_L___M 0x07010F3F +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_U (0x0040008C) +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_U__LDPC_LLR_SCALE_1___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_U__LDPC_LLR_SCALE_1___M 0x00000007 +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_U__LDPC_LLR_SCALE_1___S 0 +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_U___M 0x00000007 +#define PHYA_DEMFRONT_0_RUUD_UREC_USER_CONTROL1_U___S 0 + +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_0_L (0x004000A0) +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_0_L__NEXT_RU_DESC_UREC_WR_SPARE_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_0_L__NEXT_RU_DESC_UREC_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_0_L__NEXT_RU_DESC_UREC_WR_SPARE_0___S 0 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_0_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_0_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_0_U (0x004000A4) +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_0_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_0_U__NEXT_RU_DESC_UREC_WR_SPARE_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_0_U__NEXT_RU_DESC_UREC_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_0_U__NEXT_RU_DESC_UREC_WR_SPARE_1___S 0 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_0_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_0_U___S 0 + +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_1_L (0x004000D0) +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_1_L__NEXT_RU_DESC_NP_WR_SPARE_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_1_L__NEXT_RU_DESC_NP_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_1_L__NEXT_RU_DESC_NP_WR_SPARE_0___S 0 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_1_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_1_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_1_U (0x004000D4) +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_1_U__NEXT_RU_DESC_NP_WR_SPARE_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_1_U__NEXT_RU_DESC_NP_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_1_U__NEXT_RU_DESC_NP_WR_SPARE_1___S 0 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_1_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_1_U___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_FDPP_CONTROL_L (0x004000D8) +#define PHYA_DEMFRONT_0_RUUD_RU_FDPP_CONTROL_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_FDPP_CONTROL_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_FDPP_CONTROL_L__ENABLE_PHASE_CORR___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_FDPP_CONTROL_L__ENABLE_PHASE_CORR___M 0x00000001 +#define PHYA_DEMFRONT_0_RUUD_RU_FDPP_CONTROL_L__ENABLE_PHASE_CORR___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_FDPP_CONTROL_L___M 0x00000001 +#define PHYA_DEMFRONT_0_RUUD_RU_FDPP_CONTROL_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_2_L (0x004000E0) +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_2_L__NEXT_RU_DESC_FDPP_WR_SPARE_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_2_L__NEXT_RU_DESC_FDPP_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_2_L__NEXT_RU_DESC_FDPP_WR_SPARE_0___S 0 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_2_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_2_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_2_U (0x004000E4) +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_2_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_2_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_2_U__NEXT_RU_DESC_FDPP_WR_SPARE_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_2_U__NEXT_RU_DESC_FDPP_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_2_U__NEXT_RU_DESC_FDPP_WR_SPARE_1___S 0 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_2_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_2_U___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_ML_CONTROL_L (0x004000E8) +#define PHYA_DEMFRONT_0_RUUD_RU_ML_CONTROL_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_ML_CONTROL_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_ML_CONTROL_L__ML_LLR_EMU_ENABLE_1___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_ML_CONTROL_L__ML_LLR_EMU_ENABLE_0___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_ML_CONTROL_L__ML_LLR_EMU_ENABLE_1___M 0x00000100 +#define PHYA_DEMFRONT_0_RUUD_RU_ML_CONTROL_L__ML_LLR_EMU_ENABLE_1___S 8 +#define PHYA_DEMFRONT_0_RUUD_RU_ML_CONTROL_L__ML_LLR_EMU_ENABLE_0___M 0x00000001 +#define PHYA_DEMFRONT_0_RUUD_RU_ML_CONTROL_L__ML_LLR_EMU_ENABLE_0___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_ML_CONTROL_L___M 0x00000101 +#define PHYA_DEMFRONT_0_RUUD_RU_ML_CONTROL_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_ML_SWEIGHT_TABLE_0_L (0x004000F0) +#define PHYA_DEMFRONT_0_RUUD_ML_SWEIGHT_TABLE_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_ML_SWEIGHT_TABLE_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_ML_SWEIGHT_TABLE_0_L__SWEIGHT_SS_1___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_ML_SWEIGHT_TABLE_0_L__SWEIGHT_SS_0___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_ML_SWEIGHT_TABLE_0_L__SWEIGHT_SS_1___M 0x00000700 +#define PHYA_DEMFRONT_0_RUUD_ML_SWEIGHT_TABLE_0_L__SWEIGHT_SS_1___S 8 +#define PHYA_DEMFRONT_0_RUUD_ML_SWEIGHT_TABLE_0_L__SWEIGHT_SS_0___M 0x00000007 +#define PHYA_DEMFRONT_0_RUUD_ML_SWEIGHT_TABLE_0_L__SWEIGHT_SS_0___S 0 +#define PHYA_DEMFRONT_0_RUUD_ML_SWEIGHT_TABLE_0_L___M 0x00000707 +#define PHYA_DEMFRONT_0_RUUD_ML_SWEIGHT_TABLE_0_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_L (0x00400100) +#define PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_3___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_2___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_1___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_0___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_3___M 0x07000000 +#define PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_3___S 24 +#define PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_2___M 0x00070000 +#define PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_2___S 16 +#define PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_1___M 0x00000700 +#define PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_1___S 8 +#define PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_0___M 0x00000007 +#define PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_0___S 0 +#define PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_L___M 0x07070707 +#define PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_U (0x00400104) +#define PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_U__MIMO_LLR_SCALE_TABLE_5___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_U__MIMO_LLR_SCALE_TABLE_4___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_U__MIMO_LLR_SCALE_TABLE_5___M 0x00000700 +#define PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_U__MIMO_LLR_SCALE_TABLE_5___S 8 +#define PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_U__MIMO_LLR_SCALE_TABLE_4___M 0x00000007 +#define PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_U__MIMO_LLR_SCALE_TABLE_4___S 0 +#define PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_U___M 0x00000707 +#define PHYA_DEMFRONT_0_RUUD_ML_LLR_SCALE_TABLE_U___S 0 + +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_3_L (0x00400108) +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_3_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_3_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_3_L__NEXT_RU_DESC_ML_WR_SPARE_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_3_L__NEXT_RU_DESC_ML_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_3_L__NEXT_RU_DESC_ML_WR_SPARE_0___S 0 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_3_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_3_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_3_U (0x0040010C) +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_3_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_3_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_3_U__NEXT_RU_DESC_ML_WR_SPARE_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_3_U__NEXT_RU_DESC_ML_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_3_U__NEXT_RU_DESC_ML_WR_SPARE_1___S 0 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_3_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_3_U___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_L (0x00400110) +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_L__PILOT_PATTERN_1_0___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_L__PILOT_PATTERN_0_0___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_L__PILOT_PATTERN_1_0___M 0xFFFF0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_L__PILOT_PATTERN_1_0___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_L__PILOT_PATTERN_0_0___M 0x0000FFFF +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_L__PILOT_PATTERN_0_0___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_U (0x00400114) +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_U__PILOT_PATTERN_3_0___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_U__PILOT_PATTERN_2_0___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_U__PILOT_PATTERN_3_0___M 0xFFFF0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_U__PILOT_PATTERN_3_0___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_U__PILOT_PATTERN_2_0___M 0x0000FFFF +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_U__PILOT_PATTERN_2_0___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_00_U___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_L (0x00400118) +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_L__PILOT_PATTERN_1_1___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_L__PILOT_PATTERN_0_1___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_L__PILOT_PATTERN_1_1___M 0xFFFF0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_L__PILOT_PATTERN_1_1___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_L__PILOT_PATTERN_0_1___M 0x0000FFFF +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_L__PILOT_PATTERN_0_1___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_U (0x0040011C) +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_U__PILOT_PATTERN_3_1___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_U__PILOT_PATTERN_2_1___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_U__PILOT_PATTERN_3_1___M 0xFFFF0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_U__PILOT_PATTERN_3_1___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_U__PILOT_PATTERN_2_1___M 0x0000FFFF +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_U__PILOT_PATTERN_2_1___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_01_U___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_L (0x00400128) +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_L___POR 0x00040000 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_L__ENABLE_DF_PILOT___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_L__MAX_DF_TONES___POR 0x4 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_L__ENABLE_DF_PILOT___M 0x01000000 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_L__ENABLE_DF_PILOT___S 24 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_L__MAX_DF_TONES___M 0x00070000 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_L__MAX_DF_TONES___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_L___M 0x01070000 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_L___S 16 + +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_U (0x0040012C) +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_U__SPUR_NOTCH_OFF___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_U__FREEZE_PTC___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_U__PHASE32___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_U__SPUR_NOTCH_OFF___M 0x01000000 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_U__SPUR_NOTCH_OFF___S 24 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_U__FREEZE_PTC___M 0x00010000 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_U__FREEZE_PTC___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_U__PHASE32___M 0x0000FFFF +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_U__PHASE32___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_U___M 0x0101FFFF +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_2_U___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_L (0x00400130) +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_L__PREV_RESIDUAL_PHASE___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_L__PREV_RESIDUAL_PHASE___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_L__PREV_RESIDUAL_PHASE___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_U (0x00400134) +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_U__PHASE_OFFSET_REF___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_U__CURR_RESIDUAL_PHASE_RSHIFT___POR 0x00 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_U__CURR_PPM_STRIDE___POR 0x00 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_U__PHASE_OFFSET_REF___M 0xFFFF0000 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_U__PHASE_OFFSET_REF___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_U__CURR_RESIDUAL_PHASE_RSHIFT___M 0x0000FF00 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_U__CURR_RESIDUAL_PHASE_RSHIFT___S 8 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_U__CURR_PPM_STRIDE___M 0x000000FF +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_U__CURR_PPM_STRIDE___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_3_U___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_4_L (0x00400138) +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_4_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_4_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_4_L__EN_RU_BD_PTC_HW_UPDATE___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_4_L__EN_RU_BD_PTC_HW_UPDATE___M 0x00000001 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_4_L__EN_RU_BD_PTC_HW_UPDATE___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_4_L___M 0x00000001 +#define PHYA_DEMFRONT_0_RUUD_RU_PTC_CONTROL_4_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_L (0x00400140) +#define PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_L__UPDATE_FLAT_CHANNEL___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_L__ENA_MAX_BIN_PWR___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_L__ENA_PMAG_CORR___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_L__ENA_PHASE_CORR___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_L__UPDATE_FLAT_CHANNEL___M 0x01000000 +#define PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_L__UPDATE_FLAT_CHANNEL___S 24 +#define PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_L__ENA_MAX_BIN_PWR___M 0x00010000 +#define PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_L__ENA_MAX_BIN_PWR___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_L__ENA_PMAG_CORR___M 0x00000100 +#define PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_L__ENA_PMAG_CORR___S 8 +#define PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_L__ENA_PHASE_CORR___M 0x00000001 +#define PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_L__ENA_PHASE_CORR___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_L___M 0x01010101 +#define PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_U (0x00400144) +#define PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_U__UPDATE_FD_RSSI___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_U__UPDATE_FD_RSSI___M 0x00000001 +#define PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_U__UPDATE_FD_RSSI___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_U___M 0x00000001 +#define PHYA_DEMFRONT_0_RUUD_RU_MRC_CONTROL_U___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_L (0x00400148) +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_L__SM_FILTER_SHORT_SEL___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_L__SM_FILTER_HIGHSNR_SEL___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_L__EN_SMOOTHING___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_L__LTF_PATTERN___POR 0x00 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_L__SM_FILTER_SHORT_SEL___M 0x01000000 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_L__SM_FILTER_SHORT_SEL___S 24 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_L__SM_FILTER_HIGHSNR_SEL___M 0x00010000 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_L__SM_FILTER_HIGHSNR_SEL___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_L__EN_SMOOTHING___M 0x00000100 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_L__EN_SMOOTHING___S 8 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_L__LTF_PATTERN___M 0x0000001F +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_L__LTF_PATTERN___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_L___M 0x0101011F +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_U (0x0040014C) +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_U___POR 0x00000100 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_U__PILOT_H_STORE_INDEX___POR 0x000 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_U__PILOT_H_RAW_SEL___POR 0x1 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_U__SM_FILTER_DUR_MODE_SEL___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_U__PILOT_H_STORE_INDEX___M 0x03FF0000 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_U__PILOT_H_STORE_INDEX___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_U__PILOT_H_RAW_SEL___M 0x00000100 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_U__PILOT_H_RAW_SEL___S 8 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_U__SM_FILTER_DUR_MODE_SEL___M 0x00000003 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_U__SM_FILTER_DUR_MODE_SEL___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_U___M 0x03FF0103 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_0_U___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_L (0x00400150) +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_L__PBD_M___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_L__PILOT_H_COMB_SEL___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_L__H_BW_DET_EXP___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_L__PBD_M___M 0xFFFF0000 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_L__PBD_M___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_L__PILOT_H_COMB_SEL___M 0x00000100 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_L__PILOT_H_COMB_SEL___S 8 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_L__H_BW_DET_EXP___M 0x0000000F +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_L__H_BW_DET_EXP___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_L___M 0xFFFF010F +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_U (0x00400154) +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_U__PBD_P___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_U__PBD_P___M 0x0000FFFF +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_U__PBD_P___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_U___M 0x0000FFFF +#define PHYA_DEMFRONT_0_RUUD_RU_CHE_CONTROL_1_U___S 0 + +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_4_L (0x00400158) +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_4_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_4_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_4_L__NEXT_RU_DESC_CHE_WR_SPARE_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_4_L__NEXT_RU_DESC_CHE_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_4_L__NEXT_RU_DESC_CHE_WR_SPARE_0___S 0 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_4_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_4_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_4_U (0x0040015C) +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_4_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_4_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_4_U__NEXT_RU_DESC_CHE_WR_SPARE_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_4_U__NEXT_RU_DESC_CHE_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_4_U__NEXT_RU_DESC_CHE_WR_SPARE_1___S 0 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_4_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_4_U___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_0_L (0x00400160) +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_0_L__MRC_MAX_BIN_PWR_EXP___POR 0x00 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_0_L__MRC_MAX_BIN_PWR_MAN___POR 0x00 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_0_L__MRC_MAX_BIN_PWR_EXP___M 0x0000FF00 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_0_L__MRC_MAX_BIN_PWR_EXP___S 8 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_0_L__MRC_MAX_BIN_PWR_MAN___M 0x000000FF +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_0_L__MRC_MAX_BIN_PWR_MAN___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_0_L___M 0x0000FFFF +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_0_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_1_L (0x00400168) +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_1_L__FD_RSSI_1___POR 0x00 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_1_L__FD_RSSI_0___POR 0x00 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_1_L__FD_RSSI_1___M 0x0000FF00 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_1_L__FD_RSSI_1___S 8 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_1_L__FD_RSSI_0___M 0x000000FF +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_1_L__FD_RSSI_0___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_1_L___M 0x0000FFFF +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_1_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_2_L (0x00400170) +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_2_L__MRC_IS_FLAT_CHAN_SMOOTH___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_2_L__MRC_IS_FLAT_CHAN___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_2_L__MRC_IS_FLAT_CHAN_SMOOTH___M 0x00000100 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_2_L__MRC_IS_FLAT_CHAN_SMOOTH___S 8 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_2_L__MRC_IS_FLAT_CHAN___M 0x00000001 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_2_L__MRC_IS_FLAT_CHAN___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_2_L___M 0x00000101 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_2_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_3_L (0x00400178) +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_3_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_3_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_3_L__LLR_MAX_ED_SS_1___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_3_L__LLR_MAX_ED_SS_0___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_3_L__LLR_MAX_ED_SS_1___M 0x3FFF0000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_3_L__LLR_MAX_ED_SS_1___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_3_L__LLR_MAX_ED_SS_0___M 0x00003FFF +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_3_L__LLR_MAX_ED_SS_0___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_3_L___M 0x3FFF3FFF +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_3_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_4_L (0x00400180) +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_4_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_4_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_4_L__LLR_MIN_ED_SS_1___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_4_L__LLR_MIN_ED_SS_0___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_4_L__LLR_MIN_ED_SS_1___M 0x3FFF0000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_4_L__LLR_MIN_ED_SS_1___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_4_L__LLR_MIN_ED_SS_0___M 0x00003FFF +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_4_L__LLR_MIN_ED_SS_0___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_4_L___M 0x3FFF3FFF +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_4_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_5_L (0x00400188) +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_5_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_5_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_5_L__CH_DIAG_SS_1___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_5_L__CH_DIAG_SS_0___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_5_L__CH_DIAG_SS_1___M 0x00000300 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_5_L__CH_DIAG_SS_1___S 8 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_5_L__CH_DIAG_SS_0___M 0x00000003 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_5_L__CH_DIAG_SS_0___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_5_L___M 0x00000303 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_5_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_7_L (0x00400198) +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_7_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_7_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_7_L__COMPUTED_EMU_ENABLE_1___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_7_L__COMPUTED_EMU_ENABLE_0___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_7_L__COMPUTED_EMU_ENABLE_1___M 0x00000100 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_7_L__COMPUTED_EMU_ENABLE_1___S 8 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_7_L__COMPUTED_EMU_ENABLE_0___M 0x00000001 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_7_L__COMPUTED_EMU_ENABLE_0___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_7_L___M 0x00000101 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_DATA_7_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_0_U (0x004001A4) +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_0_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_0_U__CURR_PREDICTED_SLOPE___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_0_U__CURR_PREDICTED_SLOPE___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_0_U__CURR_PREDICTED_SLOPE___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_0_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_0_U___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_1_L (0x004001A8) +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_1_L__CURR_PREDICTED_SLOPE_FRAC___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_1_L__CURR_PREDICTED_SLOPE_FRAC___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_1_L__CURR_PREDICTED_SLOPE_FRAC___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_1_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_1_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_1_U (0x004001AC) +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_1_U__CURR_OFFSET___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_1_U__CURR_OFFSET___M 0x0000FFFF +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_1_U__CURR_OFFSET___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_1_U___M 0x0000FFFF +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_1_U___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_L (0x004001B0) +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_L__PILOT_POWER_IIR___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_L__PILOT_POWER_IIR___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_L__PILOT_POWER_IIR___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_U (0x004001B4) +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_U__CURR_OFFSET_M1___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_U__CURR_TIMING_ADJUST___POR 0x00 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_U__CURR_OFFSET_M1___M 0xFFFF0000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_U__CURR_OFFSET_M1___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_U__CURR_TIMING_ADJUST___M 0x000000FF +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_U__CURR_TIMING_ADJUST___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_U___M 0xFFFF00FF +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_2_U___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_3_L (0x004001B8) +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_3_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_3_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_3_L__PILOT_ROTATE_CURR_SYM___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_3_L__CURR_OFFSET_M2___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_3_L__PILOT_ROTATE_CURR_SYM___M 0x000F0000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_3_L__PILOT_ROTATE_CURR_SYM___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_3_L__CURR_OFFSET_M2___M 0x0000FFFF +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_3_L__CURR_OFFSET_M2___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_3_L___M 0x000FFFFF +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_3_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_L (0x004001C0) +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_L__DF_PILOT_1___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_L__DF_PILOT_0___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_L__DF_PILOT_1___M 0xFFFF0000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_L__DF_PILOT_1___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_L__DF_PILOT_0___M 0x0000FFFF +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_L__DF_PILOT_0___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_U (0x004001C4) +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_U__DF_PILOT_3___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_U__DF_PILOT_2___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_U__DF_PILOT_3___M 0xFFFF0000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_U__DF_PILOT_3___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_U__DF_PILOT_2___M 0x0000FFFF +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_U__DF_PILOT_2___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_4_U___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_L (0x004001C8) +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_L__PILOT_MAG_EXP___POR 0x00 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_L__PILOT_MAG_MAN___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_L__PILOT_MAG_EXP___M 0x00FF0000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_L__PILOT_MAG_EXP___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_L__PILOT_MAG_MAN___M 0x0000FFFF +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_L__PILOT_MAG_MAN___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_L___M 0x00FFFFFF +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_U (0x004001CC) +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_U__PILOT_POWER_REF___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_U__PHASE_FINE___POR 0x0000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_U__PILOT_POWER_REF___M 0xFFFF0000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_U__PILOT_POWER_REF___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_U__PHASE_FINE___M 0x0000FFFF +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_U__PHASE_FINE___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_RU_BD_PTC_5_U___S 0 + +#define PHYA_DEMFRONT_0_RUUD_RU_BD_CHE_L (0x004001D0) +#define PHYA_DEMFRONT_0_RUUD_RU_BD_CHE_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_RU_BD_CHE_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_CHE_L__H_BW_DET_EXP_CHN_1___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_CHE_L__RESCALE_AMT_SHIFT_1___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_CHE_L__H_BW_DET_EXP_CHN_0___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_CHE_L__RESCALE_AMT_SHIFT_0___POR 0x0 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_CHE_L__H_BW_DET_EXP_CHN_1___M 0x0F000000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_CHE_L__H_BW_DET_EXP_CHN_1___S 24 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_CHE_L__RESCALE_AMT_SHIFT_1___M 0x00030000 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_CHE_L__RESCALE_AMT_SHIFT_1___S 16 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_CHE_L__H_BW_DET_EXP_CHN_0___M 0x00000F00 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_CHE_L__H_BW_DET_EXP_CHN_0___S 8 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_CHE_L__RESCALE_AMT_SHIFT_0___M 0x00000003 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_CHE_L__RESCALE_AMT_SHIFT_0___S 0 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_CHE_L___M 0x0F030F03 +#define PHYA_DEMFRONT_0_RUUD_RU_BD_CHE_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_5_L (0x004001D8) +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_5_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_5_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_5_L__NEXT_RU_DESC_DATA_RD_SPARE_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_5_L__NEXT_RU_DESC_DATA_RD_SPARE_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_5_L__NEXT_RU_DESC_DATA_RD_SPARE_0___S 0 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_5_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_5_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_5_U (0x004001DC) +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_5_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_5_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_5_U__NEXT_RU_DESC_DATA_RD_SPARE_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_5_U__NEXT_RU_DESC_DATA_RD_SPARE_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_5_U__NEXT_RU_DESC_DATA_RD_SPARE_1___S 0 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_5_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_5_U___S 0 + +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_6_L (0x004001E0) +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_6_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_6_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_6_L__NEXT_RU_DESC_RD_SPARE_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_6_L__NEXT_RU_DESC_RD_SPARE_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_6_L__NEXT_RU_DESC_RD_SPARE_0___S 0 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_6_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_6_L___S 0 + +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_6_U (0x004001E4) +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_6_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_6_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_6_U__NEXT_RU_DESC_RD_SPARE_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_6_U__NEXT_RU_DESC_RD_SPARE_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_6_U__NEXT_RU_DESC_RD_SPARE_1___S 0 +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_6_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RUUD_USER_SPARE_6_U___S 0 + +#define PHYA_DEMFRONT_0_USER_SPARE_0_L (0x004001E8) +#define PHYA_DEMFRONT_0_USER_SPARE_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_USER_SPARE_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_USER_SPARE_0_L__NEXT_RU_DESC_WR_SPARE_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_USER_SPARE_0_L__NEXT_RU_DESC_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_USER_SPARE_0_L__NEXT_RU_DESC_WR_SPARE_0___S 0 +#define PHYA_DEMFRONT_0_USER_SPARE_0_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_USER_SPARE_0_L___S 0 + +#define PHYA_DEMFRONT_0_USER_SPARE_0_U (0x004001EC) +#define PHYA_DEMFRONT_0_USER_SPARE_0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_USER_SPARE_0_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_USER_SPARE_0_U__NEXT_RU_DESC_WR_SPARE_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_USER_SPARE_0_U__NEXT_RU_DESC_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_USER_SPARE_0_U__NEXT_RU_DESC_WR_SPARE_1___S 0 +#define PHYA_DEMFRONT_0_USER_SPARE_0_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_USER_SPARE_0_U___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_EVM0_L (0x004001F0) +#define PHYA_DEMFRONT_0_RU_BD_EVM0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RU_BD_EVM0_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM0_L__ACC_LINEAR_EVM_0_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM0_L__ACC_LINEAR_EVM_0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM0_L__ACC_LINEAR_EVM_0_0___S 0 +#define PHYA_DEMFRONT_0_RU_BD_EVM0_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM0_L___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_EVM0_U (0x004001F4) +#define PHYA_DEMFRONT_0_RU_BD_EVM0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RU_BD_EVM0_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM0_U__ACC_LINEAR_EVM_1_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM0_U__ACC_LINEAR_EVM_1_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM0_U__ACC_LINEAR_EVM_1_0___S 0 +#define PHYA_DEMFRONT_0_RU_BD_EVM0_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM0_U___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_EVM1_L (0x004001F8) +#define PHYA_DEMFRONT_0_RU_BD_EVM1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RU_BD_EVM1_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM1_L__ACC_LINEAR_EVM_0_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM1_L__ACC_LINEAR_EVM_0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM1_L__ACC_LINEAR_EVM_0_1___S 0 +#define PHYA_DEMFRONT_0_RU_BD_EVM1_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM1_L___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_EVM1_U (0x004001FC) +#define PHYA_DEMFRONT_0_RU_BD_EVM1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RU_BD_EVM1_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM1_U__ACC_LINEAR_EVM_1_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM1_U__ACC_LINEAR_EVM_1_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM1_U__ACC_LINEAR_EVM_1_1___S 0 +#define PHYA_DEMFRONT_0_RU_BD_EVM1_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM1_U___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_EVM2_L (0x00400200) +#define PHYA_DEMFRONT_0_RU_BD_EVM2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RU_BD_EVM2_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM2_L__ACC_LINEAR_EVM_0_2___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM2_L__ACC_LINEAR_EVM_0_2___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM2_L__ACC_LINEAR_EVM_0_2___S 0 +#define PHYA_DEMFRONT_0_RU_BD_EVM2_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM2_L___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_EVM2_U (0x00400204) +#define PHYA_DEMFRONT_0_RU_BD_EVM2_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RU_BD_EVM2_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM2_U__ACC_LINEAR_EVM_1_2___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM2_U__ACC_LINEAR_EVM_1_2___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM2_U__ACC_LINEAR_EVM_1_2___S 0 +#define PHYA_DEMFRONT_0_RU_BD_EVM2_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM2_U___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_EVM3_L (0x00400208) +#define PHYA_DEMFRONT_0_RU_BD_EVM3_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RU_BD_EVM3_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM3_L__ACC_LINEAR_EVM_0_3___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM3_L__ACC_LINEAR_EVM_0_3___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM3_L__ACC_LINEAR_EVM_0_3___S 0 +#define PHYA_DEMFRONT_0_RU_BD_EVM3_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM3_L___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_EVM3_U (0x0040020C) +#define PHYA_DEMFRONT_0_RU_BD_EVM3_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RU_BD_EVM3_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM3_U__ACC_LINEAR_EVM_1_3___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM3_U__ACC_LINEAR_EVM_1_3___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM3_U__ACC_LINEAR_EVM_1_3___S 0 +#define PHYA_DEMFRONT_0_RU_BD_EVM3_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM3_U___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_EVM4_L (0x00400210) +#define PHYA_DEMFRONT_0_RU_BD_EVM4_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RU_BD_EVM4_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM4_L__ACC_LINEAR_EVM_0_4___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM4_L__ACC_LINEAR_EVM_0_4___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM4_L__ACC_LINEAR_EVM_0_4___S 0 +#define PHYA_DEMFRONT_0_RU_BD_EVM4_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM4_L___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_EVM4_U (0x00400214) +#define PHYA_DEMFRONT_0_RU_BD_EVM4_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RU_BD_EVM4_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM4_U__ACC_LINEAR_EVM_1_4___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM4_U__ACC_LINEAR_EVM_1_4___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM4_U__ACC_LINEAR_EVM_1_4___S 0 +#define PHYA_DEMFRONT_0_RU_BD_EVM4_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM4_U___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_EVM5_L (0x00400218) +#define PHYA_DEMFRONT_0_RU_BD_EVM5_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RU_BD_EVM5_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM5_L__ACC_LINEAR_EVM_0_5___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM5_L__ACC_LINEAR_EVM_0_5___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM5_L__ACC_LINEAR_EVM_0_5___S 0 +#define PHYA_DEMFRONT_0_RU_BD_EVM5_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM5_L___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_EVM5_U (0x0040021C) +#define PHYA_DEMFRONT_0_RU_BD_EVM5_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RU_BD_EVM5_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM5_U__ACC_LINEAR_EVM_1_5___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM5_U__ACC_LINEAR_EVM_1_5___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM5_U__ACC_LINEAR_EVM_1_5___S 0 +#define PHYA_DEMFRONT_0_RU_BD_EVM5_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM5_U___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_EVM6_L (0x00400220) +#define PHYA_DEMFRONT_0_RU_BD_EVM6_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RU_BD_EVM6_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM6_L__ACC_LINEAR_EVM_0_6___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM6_L__ACC_LINEAR_EVM_0_6___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM6_L__ACC_LINEAR_EVM_0_6___S 0 +#define PHYA_DEMFRONT_0_RU_BD_EVM6_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM6_L___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_EVM6_U (0x00400224) +#define PHYA_DEMFRONT_0_RU_BD_EVM6_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RU_BD_EVM6_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM6_U__ACC_LINEAR_EVM_1_6___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM6_U__ACC_LINEAR_EVM_1_6___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM6_U__ACC_LINEAR_EVM_1_6___S 0 +#define PHYA_DEMFRONT_0_RU_BD_EVM6_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM6_U___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_EVM7_L (0x00400228) +#define PHYA_DEMFRONT_0_RU_BD_EVM7_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RU_BD_EVM7_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM7_L__ACC_LINEAR_EVM_0_7___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM7_L__ACC_LINEAR_EVM_0_7___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM7_L__ACC_LINEAR_EVM_0_7___S 0 +#define PHYA_DEMFRONT_0_RU_BD_EVM7_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM7_L___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_EVM7_U (0x0040022C) +#define PHYA_DEMFRONT_0_RU_BD_EVM7_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RU_BD_EVM7_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM7_U__ACC_LINEAR_EVM_1_7___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM7_U__ACC_LINEAR_EVM_1_7___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM7_U__ACC_LINEAR_EVM_1_7___S 0 +#define PHYA_DEMFRONT_0_RU_BD_EVM7_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM7_U___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_EVM8_L (0x00400230) +#define PHYA_DEMFRONT_0_RU_BD_EVM8_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RU_BD_EVM8_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM8_L__ACC_LINEAR_EVM_0_8___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM8_L__ACC_LINEAR_EVM_0_8___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM8_L__ACC_LINEAR_EVM_0_8___S 0 +#define PHYA_DEMFRONT_0_RU_BD_EVM8_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM8_L___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_EVM8_U (0x00400234) +#define PHYA_DEMFRONT_0_RU_BD_EVM8_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RU_BD_EVM8_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM8_U__ACC_LINEAR_EVM_1_8___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM8_U__ACC_LINEAR_EVM_1_8___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM8_U__ACC_LINEAR_EVM_1_8___S 0 +#define PHYA_DEMFRONT_0_RU_BD_EVM8_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM8_U___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_EVM9_L (0x00400238) +#define PHYA_DEMFRONT_0_RU_BD_EVM9_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RU_BD_EVM9_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM9_L__ACC_LINEAR_EVM_0_9___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM9_L__ACC_LINEAR_EVM_0_9___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM9_L__ACC_LINEAR_EVM_0_9___S 0 +#define PHYA_DEMFRONT_0_RU_BD_EVM9_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM9_L___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_EVM9_U (0x0040023C) +#define PHYA_DEMFRONT_0_RU_BD_EVM9_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RU_BD_EVM9_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM9_U__ACC_LINEAR_EVM_1_9___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM9_U__ACC_LINEAR_EVM_1_9___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM9_U__ACC_LINEAR_EVM_1_9___S 0 +#define PHYA_DEMFRONT_0_RU_BD_EVM9_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM9_U___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_EVM10_L (0x00400240) +#define PHYA_DEMFRONT_0_RU_BD_EVM10_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RU_BD_EVM10_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM10_L__ACC_LINEAR_EVM_0_10___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM10_L__ACC_LINEAR_EVM_0_10___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM10_L__ACC_LINEAR_EVM_0_10___S 0 +#define PHYA_DEMFRONT_0_RU_BD_EVM10_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM10_L___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_EVM10_U (0x00400244) +#define PHYA_DEMFRONT_0_RU_BD_EVM10_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RU_BD_EVM10_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM10_U__ACC_LINEAR_EVM_1_10___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM10_U__ACC_LINEAR_EVM_1_10___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM10_U__ACC_LINEAR_EVM_1_10___S 0 +#define PHYA_DEMFRONT_0_RU_BD_EVM10_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM10_U___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_EVM11_L (0x00400248) +#define PHYA_DEMFRONT_0_RU_BD_EVM11_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RU_BD_EVM11_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM11_L__ACC_LINEAR_EVM_0_11___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM11_L__ACC_LINEAR_EVM_0_11___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM11_L__ACC_LINEAR_EVM_0_11___S 0 +#define PHYA_DEMFRONT_0_RU_BD_EVM11_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM11_L___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_EVM11_U (0x0040024C) +#define PHYA_DEMFRONT_0_RU_BD_EVM11_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RU_BD_EVM11_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM11_U__ACC_LINEAR_EVM_1_11___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM11_U__ACC_LINEAR_EVM_1_11___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM11_U__ACC_LINEAR_EVM_1_11___S 0 +#define PHYA_DEMFRONT_0_RU_BD_EVM11_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM11_U___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_EVM12_L (0x00400250) +#define PHYA_DEMFRONT_0_RU_BD_EVM12_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RU_BD_EVM12_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM12_L__ACC_LINEAR_EVM_0_12___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM12_L__ACC_LINEAR_EVM_0_12___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM12_L__ACC_LINEAR_EVM_0_12___S 0 +#define PHYA_DEMFRONT_0_RU_BD_EVM12_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM12_L___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_EVM12_U (0x00400254) +#define PHYA_DEMFRONT_0_RU_BD_EVM12_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RU_BD_EVM12_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM12_U__ACC_LINEAR_EVM_1_12___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM12_U__ACC_LINEAR_EVM_1_12___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM12_U__ACC_LINEAR_EVM_1_12___S 0 +#define PHYA_DEMFRONT_0_RU_BD_EVM12_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM12_U___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_EVM13_L (0x00400258) +#define PHYA_DEMFRONT_0_RU_BD_EVM13_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RU_BD_EVM13_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM13_L__ACC_LINEAR_EVM_0_13___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM13_L__ACC_LINEAR_EVM_0_13___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM13_L__ACC_LINEAR_EVM_0_13___S 0 +#define PHYA_DEMFRONT_0_RU_BD_EVM13_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM13_L___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_EVM13_U (0x0040025C) +#define PHYA_DEMFRONT_0_RU_BD_EVM13_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RU_BD_EVM13_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM13_U__ACC_LINEAR_EVM_1_13___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM13_U__ACC_LINEAR_EVM_1_13___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM13_U__ACC_LINEAR_EVM_1_13___S 0 +#define PHYA_DEMFRONT_0_RU_BD_EVM13_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM13_U___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_EVM14_L (0x00400260) +#define PHYA_DEMFRONT_0_RU_BD_EVM14_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RU_BD_EVM14_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM14_L__ACC_LINEAR_EVM_0_14___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM14_L__ACC_LINEAR_EVM_0_14___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM14_L__ACC_LINEAR_EVM_0_14___S 0 +#define PHYA_DEMFRONT_0_RU_BD_EVM14_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM14_L___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_EVM14_U (0x00400264) +#define PHYA_DEMFRONT_0_RU_BD_EVM14_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RU_BD_EVM14_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM14_U__ACC_LINEAR_EVM_1_14___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM14_U__ACC_LINEAR_EVM_1_14___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM14_U__ACC_LINEAR_EVM_1_14___S 0 +#define PHYA_DEMFRONT_0_RU_BD_EVM14_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM14_U___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_EVM15_L (0x00400268) +#define PHYA_DEMFRONT_0_RU_BD_EVM15_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RU_BD_EVM15_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM15_L__ACC_LINEAR_EVM_0_15___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM15_L__ACC_LINEAR_EVM_0_15___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM15_L__ACC_LINEAR_EVM_0_15___S 0 +#define PHYA_DEMFRONT_0_RU_BD_EVM15_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM15_L___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_EVM15_U (0x0040026C) +#define PHYA_DEMFRONT_0_RU_BD_EVM15_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RU_BD_EVM15_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM15_U__ACC_LINEAR_EVM_1_15___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_EVM15_U__ACC_LINEAR_EVM_1_15___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM15_U__ACC_LINEAR_EVM_1_15___S 0 +#define PHYA_DEMFRONT_0_RU_BD_EVM15_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_RU_BD_EVM15_U___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_QRE_0_L (0x00400270) +#define PHYA_DEMFRONT_0_RU_BD_QRE_0_L___RWC QCSR_REG_RO +#define PHYA_DEMFRONT_0_RU_BD_QRE_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_QRE_0_L__ML_SUBSET_SEARCH_2X2_USAGE_1___POR 0x000 +#define PHYA_DEMFRONT_0_RU_BD_QRE_0_L__ML_SUBSET_SEARCH_2X2_USAGE_0___POR 0x000 +#define PHYA_DEMFRONT_0_RU_BD_QRE_0_L__ML_SUBSET_SEARCH_2X2_USAGE_1___M 0x0FFF0000 +#define PHYA_DEMFRONT_0_RU_BD_QRE_0_L__ML_SUBSET_SEARCH_2X2_USAGE_1___S 16 +#define PHYA_DEMFRONT_0_RU_BD_QRE_0_L__ML_SUBSET_SEARCH_2X2_USAGE_0___M 0x00000FFF +#define PHYA_DEMFRONT_0_RU_BD_QRE_0_L__ML_SUBSET_SEARCH_2X2_USAGE_0___S 0 +#define PHYA_DEMFRONT_0_RU_BD_QRE_0_L___M 0x0FFF0FFF +#define PHYA_DEMFRONT_0_RU_BD_QRE_0_L___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_QRE_1_L (0x00400278) +#define PHYA_DEMFRONT_0_RU_BD_QRE_1_L___RWC QCSR_REG_RO +#define PHYA_DEMFRONT_0_RU_BD_QRE_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_QRE_1_L__ML_SUBSET_SEARCH_4X4_USAGE_1___POR 0x000 +#define PHYA_DEMFRONT_0_RU_BD_QRE_1_L__ML_SUBSET_SEARCH_4X4_USAGE_0___POR 0x000 +#define PHYA_DEMFRONT_0_RU_BD_QRE_1_L__ML_SUBSET_SEARCH_4X4_USAGE_1___M 0x0FFF0000 +#define PHYA_DEMFRONT_0_RU_BD_QRE_1_L__ML_SUBSET_SEARCH_4X4_USAGE_1___S 16 +#define PHYA_DEMFRONT_0_RU_BD_QRE_1_L__ML_SUBSET_SEARCH_4X4_USAGE_0___M 0x00000FFF +#define PHYA_DEMFRONT_0_RU_BD_QRE_1_L__ML_SUBSET_SEARCH_4X4_USAGE_0___S 0 +#define PHYA_DEMFRONT_0_RU_BD_QRE_1_L___M 0x0FFF0FFF +#define PHYA_DEMFRONT_0_RU_BD_QRE_1_L___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_0_L (0x004003F0) +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_0_L___RWC QCSR_REG_RO +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_0_L__IS_FLAT_CHANNEL___POR 0x0 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_0_L__IS_FLAT_CHANNEL___M 0x00000001 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_0_L__IS_FLAT_CHANNEL___S 0 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_0_L___M 0x00000001 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_0_L___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_1_L (0x004003F8) +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_1_L___RWC QCSR_REG_RO +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_1_L__IS_HIGH_FREQ_SELECT_1___POR 0x00 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_1_L__IS_HIGH_FREQ_SELECT_0___POR 0x00 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_1_L__IS_HIGH_FREQ_SELECT_1___M 0x0000FF00 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_1_L__IS_HIGH_FREQ_SELECT_1___S 8 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_1_L__IS_HIGH_FREQ_SELECT_0___M 0x000000FF +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_1_L__IS_HIGH_FREQ_SELECT_0___S 0 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_1_L___M 0x0000FFFF +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_1_L___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_2_L (0x00400400) +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_2_L___RWC QCSR_REG_RO +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_2_L__IS_VALID_HIGH_FREQ_SELECT_1___POR 0x00 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_2_L__IS_VALID_HIGH_FREQ_SELECT_0___POR 0x00 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_2_L__IS_VALID_HIGH_FREQ_SELECT_1___M 0x0000FF00 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_2_L__IS_VALID_HIGH_FREQ_SELECT_1___S 8 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_2_L__IS_VALID_HIGH_FREQ_SELECT_0___M 0x000000FF +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_2_L__IS_VALID_HIGH_FREQ_SELECT_0___S 0 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_2_L___M 0x0000FFFF +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_2_L___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_3_L (0x00400408) +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_3_L___RWC QCSR_REG_RO +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_3_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_3_L__SHIFTSAMPLENO_VLD_1___POR 0x00 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_3_L__SHIFTSAMPLENO_VLD_0___POR 0x00 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_3_L__SHIFTSAMPLENO_VLD_1___M 0x0000FF00 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_3_L__SHIFTSAMPLENO_VLD_1___S 8 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_3_L__SHIFTSAMPLENO_VLD_0___M 0x000000FF +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_3_L__SHIFTSAMPLENO_VLD_0___S 0 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_3_L___M 0x0000FFFF +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_3_L___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_4_L (0x00400410) +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_4_L___RWC QCSR_REG_RO +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_4_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_4_L__SHIFTSAMPLENO_S0_1___POR 0x000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_4_L__SHIFTSAMPLENO_S0_0___POR 0x000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_4_L__SHIFTSAMPLENO_S0_1___M 0x07FF0000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_4_L__SHIFTSAMPLENO_S0_1___S 16 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_4_L__SHIFTSAMPLENO_S0_0___M 0x000007FF +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_4_L__SHIFTSAMPLENO_S0_0___S 0 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_4_L___M 0x07FF07FF +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_4_L___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_5_L (0x00400418) +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_5_L___RWC QCSR_REG_RO +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_5_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_5_L__SHIFTSAMPLENO_S1_1___POR 0x000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_5_L__SHIFTSAMPLENO_S1_0___POR 0x000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_5_L__SHIFTSAMPLENO_S1_1___M 0x07FF0000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_5_L__SHIFTSAMPLENO_S1_1___S 16 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_5_L__SHIFTSAMPLENO_S1_0___M 0x000007FF +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_5_L__SHIFTSAMPLENO_S1_0___S 0 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_5_L___M 0x07FF07FF +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_5_L___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_6_L (0x00400420) +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_6_L___RWC QCSR_REG_RO +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_6_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_6_L__SHIFTSAMPLENO_S2_1___POR 0x000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_6_L__SHIFTSAMPLENO_S2_0___POR 0x000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_6_L__SHIFTSAMPLENO_S2_1___M 0x07FF0000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_6_L__SHIFTSAMPLENO_S2_1___S 16 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_6_L__SHIFTSAMPLENO_S2_0___M 0x000007FF +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_6_L__SHIFTSAMPLENO_S2_0___S 0 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_6_L___M 0x07FF07FF +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_6_L___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_7_L (0x00400428) +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_7_L___RWC QCSR_REG_RO +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_7_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_7_L__SHIFTSAMPLENO_S3_1___POR 0x000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_7_L__SHIFTSAMPLENO_S3_0___POR 0x000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_7_L__SHIFTSAMPLENO_S3_1___M 0x07FF0000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_7_L__SHIFTSAMPLENO_S3_1___S 16 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_7_L__SHIFTSAMPLENO_S3_0___M 0x000007FF +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_7_L__SHIFTSAMPLENO_S3_0___S 0 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_7_L___M 0x07FF07FF +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_7_L___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_8_L (0x00400430) +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_8_L___RWC QCSR_REG_RO +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_8_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_8_L__SHIFTSAMPLENO_S4_1___POR 0x000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_8_L__SHIFTSAMPLENO_S4_0___POR 0x000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_8_L__SHIFTSAMPLENO_S4_1___M 0x07FF0000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_8_L__SHIFTSAMPLENO_S4_1___S 16 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_8_L__SHIFTSAMPLENO_S4_0___M 0x000007FF +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_8_L__SHIFTSAMPLENO_S4_0___S 0 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_8_L___M 0x07FF07FF +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_8_L___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_9_L (0x00400438) +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_9_L___RWC QCSR_REG_RO +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_9_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_9_L__SHIFTSAMPLENO_S5_1___POR 0x000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_9_L__SHIFTSAMPLENO_S5_0___POR 0x000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_9_L__SHIFTSAMPLENO_S5_1___M 0x07FF0000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_9_L__SHIFTSAMPLENO_S5_1___S 16 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_9_L__SHIFTSAMPLENO_S5_0___M 0x000007FF +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_9_L__SHIFTSAMPLENO_S5_0___S 0 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_9_L___M 0x07FF07FF +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_9_L___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_10_L (0x00400440) +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_10_L___RWC QCSR_REG_RO +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_10_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_10_L__SHIFTSAMPLENO_S6_1___POR 0x000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_10_L__SHIFTSAMPLENO_S6_0___POR 0x000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_10_L__SHIFTSAMPLENO_S6_1___M 0x07FF0000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_10_L__SHIFTSAMPLENO_S6_1___S 16 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_10_L__SHIFTSAMPLENO_S6_0___M 0x000007FF +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_10_L__SHIFTSAMPLENO_S6_0___S 0 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_10_L___M 0x07FF07FF +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_10_L___S 0 + +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_11_L (0x00400448) +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_11_L___RWC QCSR_REG_RO +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_11_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_11_L__SHIFTSAMPLENO_S7_1___POR 0x000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_11_L__SHIFTSAMPLENO_S7_0___POR 0x000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_11_L__SHIFTSAMPLENO_S7_1___M 0x07FF0000 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_11_L__SHIFTSAMPLENO_S7_1___S 16 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_11_L__SHIFTSAMPLENO_S7_0___M 0x000007FF +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_11_L__SHIFTSAMPLENO_S7_0___S 0 +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_11_L___M 0x07FF07FF +#define PHYA_DEMFRONT_0_RU_BD_DEBUG_11_L___S 0 + +#define PHYA_DEMFRONT_0_SDF_BUFFER_L_n(n) (0x004004B8+0x8*(n)) +#define PHYA_DEMFRONT_0_SDF_BUFFER_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_SDF_BUFFER_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_SDF_BUFFER_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_SDF_BUFFER_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SDF_BUFFER_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_SDF_BUFFER_L_n__SDF_BUFFER_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_SDF_BUFFER_L_n__SDF_BUFFER_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_SDF_BUFFER_L_n__SDF_BUFFER_0___S 0 +#define PHYA_DEMFRONT_0_SDF_BUFFER_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_SDF_BUFFER_L_n___S 0 +#define PHYA_DEMFRONT_0_SDF_BUFFER_L_0 (0x004004B8) +#define PHYA_DEMFRONT_0_SDF_BUFFER_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SDF_BUFFER_L_0__SDF_BUFFER_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_SDF_BUFFER_L_0__SDF_BUFFER_0___S 0 + +#define PHYA_DEMFRONT_0_SDF_BUFFER_U_n(n) (0x004004BC+0x8*(n)) +#define PHYA_DEMFRONT_0_SDF_BUFFER_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_SDF_BUFFER_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_SDF_BUFFER_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_SDF_BUFFER_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SDF_BUFFER_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_SDF_BUFFER_U_n__SDF_BUFFER_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_SDF_BUFFER_U_n__SDF_BUFFER_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_SDF_BUFFER_U_n__SDF_BUFFER_1___S 0 +#define PHYA_DEMFRONT_0_SDF_BUFFER_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_SDF_BUFFER_U_n___S 0 +#define PHYA_DEMFRONT_0_SDF_BUFFER_U_0 (0x004004BC) +#define PHYA_DEMFRONT_0_SDF_BUFFER_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SDF_BUFFER_U_0__SDF_BUFFER_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_SDF_BUFFER_U_0__SDF_BUFFER_1___S 0 + +#define PHYA_DEMFRONT_0_SYM_CONTROL_0_L (0x004004C0) +#define PHYA_DEMFRONT_0_SYM_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SYM_CONTROL_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SYM_CONTROL_0_L__LAST_FILL___POR 0x0 +#define PHYA_DEMFRONT_0_SYM_CONTROL_0_L__IS_160___POR 0x0 +#define PHYA_DEMFRONT_0_SYM_CONTROL_0_L__FLUSH_IF_QBPSK___POR 0x0 +#define PHYA_DEMFRONT_0_SYM_CONTROL_0_L__FLUSH___POR 0x0 +#define PHYA_DEMFRONT_0_SYM_CONTROL_0_L__LAST_FILL___M 0x03000000 +#define PHYA_DEMFRONT_0_SYM_CONTROL_0_L__LAST_FILL___S 24 +#define PHYA_DEMFRONT_0_SYM_CONTROL_0_L__IS_160___M 0x00010000 +#define PHYA_DEMFRONT_0_SYM_CONTROL_0_L__IS_160___S 16 +#define PHYA_DEMFRONT_0_SYM_CONTROL_0_L__FLUSH_IF_QBPSK___M 0x00000100 +#define PHYA_DEMFRONT_0_SYM_CONTROL_0_L__FLUSH_IF_QBPSK___S 8 +#define PHYA_DEMFRONT_0_SYM_CONTROL_0_L__FLUSH___M 0x00000001 +#define PHYA_DEMFRONT_0_SYM_CONTROL_0_L__FLUSH___S 0 +#define PHYA_DEMFRONT_0_SYM_CONTROL_0_L___M 0x03010101 +#define PHYA_DEMFRONT_0_SYM_CONTROL_0_L___S 0 + +#define PHYA_DEMFRONT_0_SYM_CONTROL_0_U (0x004004C4) +#define PHYA_DEMFRONT_0_SYM_CONTROL_0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SYM_CONTROL_0_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_SYM_CONTROL_0_U__MAX_LLR_TO_ROBE___POR 0x00 +#define PHYA_DEMFRONT_0_SYM_CONTROL_0_U__MRC_RSHIFT___POR 0x00 +#define PHYA_DEMFRONT_0_SYM_CONTROL_0_U__SYM_TYPE_QBPSK___POR 0x00 +#define PHYA_DEMFRONT_0_SYM_CONTROL_0_U__SYM_TYPE___POR 0x00 +#define PHYA_DEMFRONT_0_SYM_CONTROL_0_U__MAX_LLR_TO_ROBE___M 0x3F000000 +#define PHYA_DEMFRONT_0_SYM_CONTROL_0_U__MAX_LLR_TO_ROBE___S 24 +#define PHYA_DEMFRONT_0_SYM_CONTROL_0_U__MRC_RSHIFT___M 0x003F0000 +#define PHYA_DEMFRONT_0_SYM_CONTROL_0_U__MRC_RSHIFT___S 16 +#define PHYA_DEMFRONT_0_SYM_CONTROL_0_U__SYM_TYPE_QBPSK___M 0x0000FF00 +#define PHYA_DEMFRONT_0_SYM_CONTROL_0_U__SYM_TYPE_QBPSK___S 8 +#define PHYA_DEMFRONT_0_SYM_CONTROL_0_U__SYM_TYPE___M 0x000000FF +#define PHYA_DEMFRONT_0_SYM_CONTROL_0_U__SYM_TYPE___S 0 +#define PHYA_DEMFRONT_0_SYM_CONTROL_0_U___M 0x3F3FFFFF +#define PHYA_DEMFRONT_0_SYM_CONTROL_0_U___S 0 + +#define PHYA_DEMFRONT_0_SYM_CONTROL_1_L (0x004004C8) +#define PHYA_DEMFRONT_0_SYM_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SYM_CONTROL_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SYM_CONTROL_1_L__ENA_LLR_AVG___POR 0x0 +#define PHYA_DEMFRONT_0_SYM_CONTROL_1_L__ENA_MAX_LLR_TO_ROBE___POR 0x0 +#define PHYA_DEMFRONT_0_SYM_CONTROL_1_L__ENA_LLR_STORE___POR 0x0 +#define PHYA_DEMFRONT_0_SYM_CONTROL_1_L__USE_COMBINE_CHAN___POR 0x0 +#define PHYA_DEMFRONT_0_SYM_CONTROL_1_L__ENA_LLR_AVG___M 0x01000000 +#define PHYA_DEMFRONT_0_SYM_CONTROL_1_L__ENA_LLR_AVG___S 24 +#define PHYA_DEMFRONT_0_SYM_CONTROL_1_L__ENA_MAX_LLR_TO_ROBE___M 0x00010000 +#define PHYA_DEMFRONT_0_SYM_CONTROL_1_L__ENA_MAX_LLR_TO_ROBE___S 16 +#define PHYA_DEMFRONT_0_SYM_CONTROL_1_L__ENA_LLR_STORE___M 0x00000100 +#define PHYA_DEMFRONT_0_SYM_CONTROL_1_L__ENA_LLR_STORE___S 8 +#define PHYA_DEMFRONT_0_SYM_CONTROL_1_L__USE_COMBINE_CHAN___M 0x00000001 +#define PHYA_DEMFRONT_0_SYM_CONTROL_1_L__USE_COMBINE_CHAN___S 0 +#define PHYA_DEMFRONT_0_SYM_CONTROL_1_L___M 0x01010101 +#define PHYA_DEMFRONT_0_SYM_CONTROL_1_L___S 0 + +#define PHYA_DEMFRONT_0_SYM_CONTROL_1_U (0x004004CC) +#define PHYA_DEMFRONT_0_SYM_CONTROL_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SYM_CONTROL_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_SYM_CONTROL_1_U__LTF_IDX___POR 0x0 +#define PHYA_DEMFRONT_0_SYM_CONTROL_1_U__ENA_CORR_Y_STORE___POR 0x0 +#define PHYA_DEMFRONT_0_SYM_CONTROL_1_U__ENA_LLR_AVG_QBPSK___POR 0x0 +#define PHYA_DEMFRONT_0_SYM_CONTROL_1_U__ENA_LLR_AVG_RLSIG___POR 0x0 +#define PHYA_DEMFRONT_0_SYM_CONTROL_1_U__LTF_IDX___M 0x07000000 +#define PHYA_DEMFRONT_0_SYM_CONTROL_1_U__LTF_IDX___S 24 +#define PHYA_DEMFRONT_0_SYM_CONTROL_1_U__ENA_CORR_Y_STORE___M 0x00010000 +#define PHYA_DEMFRONT_0_SYM_CONTROL_1_U__ENA_CORR_Y_STORE___S 16 +#define PHYA_DEMFRONT_0_SYM_CONTROL_1_U__ENA_LLR_AVG_QBPSK___M 0x00000100 +#define PHYA_DEMFRONT_0_SYM_CONTROL_1_U__ENA_LLR_AVG_QBPSK___S 8 +#define PHYA_DEMFRONT_0_SYM_CONTROL_1_U__ENA_LLR_AVG_RLSIG___M 0x00000001 +#define PHYA_DEMFRONT_0_SYM_CONTROL_1_U__ENA_LLR_AVG_RLSIG___S 0 +#define PHYA_DEMFRONT_0_SYM_CONTROL_1_U___M 0x07010101 +#define PHYA_DEMFRONT_0_SYM_CONTROL_1_U___S 0 + +#define PHYA_DEMFRONT_0_SYM_CONTROL_2_L (0x004004D0) +#define PHYA_DEMFRONT_0_SYM_CONTROL_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SYM_CONTROL_2_L___POR 0x01000002 +#define PHYA_DEMFRONT_0_SYM_CONTROL_2_L__ASSERT_RXTD_GAIN_RATIO_EVENT___POR 0x1 +#define PHYA_DEMFRONT_0_SYM_CONTROL_2_L__ASSERT_PROC_COMPLETE_EVENT___POR 0x0 +#define PHYA_DEMFRONT_0_SYM_CONTROL_2_L__DISABLE_DEINT_QBPSK___POR 0x0 +#define PHYA_DEMFRONT_0_SYM_CONTROL_2_L__N_LTF___POR 0x2 +#define PHYA_DEMFRONT_0_SYM_CONTROL_2_L__ASSERT_RXTD_GAIN_RATIO_EVENT___M 0x01000000 +#define PHYA_DEMFRONT_0_SYM_CONTROL_2_L__ASSERT_RXTD_GAIN_RATIO_EVENT___S 24 +#define PHYA_DEMFRONT_0_SYM_CONTROL_2_L__ASSERT_PROC_COMPLETE_EVENT___M 0x00010000 +#define PHYA_DEMFRONT_0_SYM_CONTROL_2_L__ASSERT_PROC_COMPLETE_EVENT___S 16 +#define PHYA_DEMFRONT_0_SYM_CONTROL_2_L__DISABLE_DEINT_QBPSK___M 0x00000100 +#define PHYA_DEMFRONT_0_SYM_CONTROL_2_L__DISABLE_DEINT_QBPSK___S 8 +#define PHYA_DEMFRONT_0_SYM_CONTROL_2_L__N_LTF___M 0x0000000F +#define PHYA_DEMFRONT_0_SYM_CONTROL_2_L__N_LTF___S 0 +#define PHYA_DEMFRONT_0_SYM_CONTROL_2_L___M 0x0101010F +#define PHYA_DEMFRONT_0_SYM_CONTROL_2_L___S 0 + +#define PHYA_DEMFRONT_0_SYM_CONTROL_2_U (0x004004D4) +#define PHYA_DEMFRONT_0_SYM_CONTROL_2_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SYM_CONTROL_2_U___POR 0x04010101 +#define PHYA_DEMFRONT_0_SYM_CONTROL_2_U__ACTIVE_RX_CHAIN_COMB___POR 0x4 +#define PHYA_DEMFRONT_0_SYM_CONTROL_2_U__ASSERT_PER_PKT_PROGRAM_EVENT___POR 0x1 +#define PHYA_DEMFRONT_0_SYM_CONTROL_2_U__ASSERT_RXTD_INIT_PHASE_EVENT___POR 0x1 +#define PHYA_DEMFRONT_0_SYM_CONTROL_2_U__ASSERT_RXTD_NOISEPWR_BTCF_EVENT___POR 0x1 +#define PHYA_DEMFRONT_0_SYM_CONTROL_2_U__ACTIVE_RX_CHAIN_COMB___M 0x0F000000 +#define PHYA_DEMFRONT_0_SYM_CONTROL_2_U__ACTIVE_RX_CHAIN_COMB___S 24 +#define PHYA_DEMFRONT_0_SYM_CONTROL_2_U__ASSERT_PER_PKT_PROGRAM_EVENT___M 0x00010000 +#define PHYA_DEMFRONT_0_SYM_CONTROL_2_U__ASSERT_PER_PKT_PROGRAM_EVENT___S 16 +#define PHYA_DEMFRONT_0_SYM_CONTROL_2_U__ASSERT_RXTD_INIT_PHASE_EVENT___M 0x00000100 +#define PHYA_DEMFRONT_0_SYM_CONTROL_2_U__ASSERT_RXTD_INIT_PHASE_EVENT___S 8 +#define PHYA_DEMFRONT_0_SYM_CONTROL_2_U__ASSERT_RXTD_NOISEPWR_BTCF_EVENT___M 0x00000001 +#define PHYA_DEMFRONT_0_SYM_CONTROL_2_U__ASSERT_RXTD_NOISEPWR_BTCF_EVENT___S 0 +#define PHYA_DEMFRONT_0_SYM_CONTROL_2_U___M 0x0F010101 +#define PHYA_DEMFRONT_0_SYM_CONTROL_2_U___S 0 + +#define PHYA_DEMFRONT_0_MRC_CONTROL_0_L (0x004004D8) +#define PHYA_DEMFRONT_0_MRC_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_MRC_CONTROL_0_L___POR 0x30000000 +#define PHYA_DEMFRONT_0_MRC_CONTROL_0_L__QBPSK_DET_NUM_TONES___POR 0x30 +#define PHYA_DEMFRONT_0_MRC_CONTROL_0_L__QBPSK_DET_ENA___POR 0x0 +#define PHYA_DEMFRONT_0_MRC_CONTROL_0_L__MRC_TONE_INVERT___POR 0x0 +#define PHYA_DEMFRONT_0_MRC_CONTROL_0_L__QBPSK_DET_NUM_TONES___M 0x3F000000 +#define PHYA_DEMFRONT_0_MRC_CONTROL_0_L__QBPSK_DET_NUM_TONES___S 24 +#define PHYA_DEMFRONT_0_MRC_CONTROL_0_L__QBPSK_DET_ENA___M 0x00010000 +#define PHYA_DEMFRONT_0_MRC_CONTROL_0_L__QBPSK_DET_ENA___S 16 +#define PHYA_DEMFRONT_0_MRC_CONTROL_0_L__MRC_TONE_INVERT___M 0x00000001 +#define PHYA_DEMFRONT_0_MRC_CONTROL_0_L__MRC_TONE_INVERT___S 0 +#define PHYA_DEMFRONT_0_MRC_CONTROL_0_L___M 0x3F010001 +#define PHYA_DEMFRONT_0_MRC_CONTROL_0_L___S 0 + +#define PHYA_DEMFRONT_0_MRC_CONTROL_0_U (0x004004DC) +#define PHYA_DEMFRONT_0_MRC_CONTROL_0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_MRC_CONTROL_0_U___POR 0x00003000 +#define PHYA_DEMFRONT_0_MRC_CONTROL_0_U__FORCE_IS_RLSIG___POR 0x0 +#define PHYA_DEMFRONT_0_MRC_CONTROL_0_U__FORCE_IS_QBPSK___POR 0x0 +#define PHYA_DEMFRONT_0_MRC_CONTROL_0_U__RLSIG_DET_NUM_TONES___POR 0x30 +#define PHYA_DEMFRONT_0_MRC_CONTROL_0_U__RLSIG_DET_ENA___POR 0x0 +#define PHYA_DEMFRONT_0_MRC_CONTROL_0_U__FORCE_IS_RLSIG___M 0x01000000 +#define PHYA_DEMFRONT_0_MRC_CONTROL_0_U__FORCE_IS_RLSIG___S 24 +#define PHYA_DEMFRONT_0_MRC_CONTROL_0_U__FORCE_IS_QBPSK___M 0x00010000 +#define PHYA_DEMFRONT_0_MRC_CONTROL_0_U__FORCE_IS_QBPSK___S 16 +#define PHYA_DEMFRONT_0_MRC_CONTROL_0_U__RLSIG_DET_NUM_TONES___M 0x00003F00 +#define PHYA_DEMFRONT_0_MRC_CONTROL_0_U__RLSIG_DET_NUM_TONES___S 8 +#define PHYA_DEMFRONT_0_MRC_CONTROL_0_U__RLSIG_DET_ENA___M 0x00000001 +#define PHYA_DEMFRONT_0_MRC_CONTROL_0_U__RLSIG_DET_ENA___S 0 +#define PHYA_DEMFRONT_0_MRC_CONTROL_0_U___M 0x01013F01 +#define PHYA_DEMFRONT_0_MRC_CONTROL_0_U___S 0 + +#define PHYA_DEMFRONT_0_MRC_CONTROL_1_L (0x004004E0) +#define PHYA_DEMFRONT_0_MRC_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_MRC_CONTROL_1_L___POR 0x08000000 +#define PHYA_DEMFRONT_0_MRC_CONTROL_1_L__ULMU_MIMO_N_LTF_IN_TRACKING___POR 0x8 +#define PHYA_DEMFRONT_0_MRC_CONTROL_1_L__ULMU_MIMO_LTF_TRACK_ENABLE___POR 0x0 +#define PHYA_DEMFRONT_0_MRC_CONTROL_1_L__BIN_RSHIFT_SCALE___POR 0x0 +#define PHYA_DEMFRONT_0_MRC_CONTROL_1_L__ENA_EQ_INV_SAT___POR 0x0 +#define PHYA_DEMFRONT_0_MRC_CONTROL_1_L__ULMU_MIMO_N_LTF_IN_TRACKING___M 0x0F000000 +#define PHYA_DEMFRONT_0_MRC_CONTROL_1_L__ULMU_MIMO_N_LTF_IN_TRACKING___S 24 +#define PHYA_DEMFRONT_0_MRC_CONTROL_1_L__ULMU_MIMO_LTF_TRACK_ENABLE___M 0x00010000 +#define PHYA_DEMFRONT_0_MRC_CONTROL_1_L__ULMU_MIMO_LTF_TRACK_ENABLE___S 16 +#define PHYA_DEMFRONT_0_MRC_CONTROL_1_L__BIN_RSHIFT_SCALE___M 0x00000300 +#define PHYA_DEMFRONT_0_MRC_CONTROL_1_L__BIN_RSHIFT_SCALE___S 8 +#define PHYA_DEMFRONT_0_MRC_CONTROL_1_L__ENA_EQ_INV_SAT___M 0x00000001 +#define PHYA_DEMFRONT_0_MRC_CONTROL_1_L__ENA_EQ_INV_SAT___S 0 +#define PHYA_DEMFRONT_0_MRC_CONTROL_1_L___M 0x0F010301 +#define PHYA_DEMFRONT_0_MRC_CONTROL_1_L___S 0 + +#define PHYA_DEMFRONT_0_USER_SPARE_1_L (0x004004E8) +#define PHYA_DEMFRONT_0_USER_SPARE_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_USER_SPARE_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_USER_SPARE_1_L__NEXT_DESC_WR_MRC_SPARE_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_USER_SPARE_1_L__NEXT_DESC_WR_MRC_SPARE_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_USER_SPARE_1_L__NEXT_DESC_WR_MRC_SPARE_0___S 0 +#define PHYA_DEMFRONT_0_USER_SPARE_1_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_USER_SPARE_1_L___S 0 + +#define PHYA_DEMFRONT_0_USER_SPARE_1_U (0x004004EC) +#define PHYA_DEMFRONT_0_USER_SPARE_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_USER_SPARE_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_USER_SPARE_1_U__NEXT_DESC_WR_MRC_SPARE_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_USER_SPARE_1_U__NEXT_DESC_WR_MRC_SPARE_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_USER_SPARE_1_U__NEXT_DESC_WR_MRC_SPARE_1___S 0 +#define PHYA_DEMFRONT_0_USER_SPARE_1_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_USER_SPARE_1_U___S 0 + +#define PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_L (0x004004F0) +#define PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_L__ENABLE_SM_CHE_COPY___POR 0x0 +#define PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_L__ENABLE_SM_BW___POR 0x0 +#define PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_L__ENABLE_SM_PTC___POR 0x0 +#define PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_L__ENABLE_SM_CHE___POR 0x0 +#define PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_L__ENABLE_SM_CHE_COPY___M 0x01000000 +#define PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_L__ENABLE_SM_CHE_COPY___S 24 +#define PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_L__ENABLE_SM_BW___M 0x00010000 +#define PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_L__ENABLE_SM_BW___S 16 +#define PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_L__ENABLE_SM_PTC___M 0x00000100 +#define PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_L__ENABLE_SM_PTC___S 8 +#define PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_L__ENABLE_SM_CHE___M 0x00000001 +#define PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_L__ENABLE_SM_CHE___S 0 +#define PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_L___M 0x01010101 +#define PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_L___S 0 + +#define PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_U (0x004004F4) +#define PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_U__DL_OFDMA_IS_EXT80___POR 0x0 +#define PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_U__DL_OFDMA_IS_EXT80___M 0x00000001 +#define PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_U__DL_OFDMA_IS_EXT80___S 0 +#define PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_U___M 0x00000001 +#define PHYA_DEMFRONT_0_SPUR_MAIN_CONTROL_U___S 0 + +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_0_L (0x004004F8) +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_0_L___POR 0x000001FF +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_0_L__SM0_SPUR_IDX___POR 0x01FF +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_0_L__SM0_SPUR_IDX___M 0x0000FFFF +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_0_L__SM0_SPUR_IDX___S 0 +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_0_L___M 0x0000FFFF +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_0_L___S 0 + +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_L (0x00400500) +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_L__SM0_3_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_L__SM0_2_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_L__SM0_1_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_L__SM0_0_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_L__SM0_3_SPUR_MASK___M 0x07000000 +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_L__SM0_3_SPUR_MASK___S 24 +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_L__SM0_2_SPUR_MASK___M 0x00070000 +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_L__SM0_2_SPUR_MASK___S 16 +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_L__SM0_1_SPUR_MASK___M 0x00000700 +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_L__SM0_1_SPUR_MASK___S 8 +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_L__SM0_0_SPUR_MASK___M 0x00000007 +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_L__SM0_0_SPUR_MASK___S 0 +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_L___M 0x07070707 +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_L___S 0 + +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_U (0x00400504) +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_U__SM0_4_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_U__SM0_4_SPUR_MASK___M 0x00000007 +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_U__SM0_4_SPUR_MASK___S 0 +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_U___M 0x00000007 +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_1_U___S 0 + +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_2_L (0x00400508) +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_2_L__SM0_SPUR_CP_OFFSET_R___POR 0x00 +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_2_L__SM0_SPUR_CP_OFFSET_L___POR 0x00 +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_2_L__SM0_SPUR_CP_OFFSET_R___M 0x0000FF00 +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_2_L__SM0_SPUR_CP_OFFSET_R___S 8 +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_2_L__SM0_SPUR_CP_OFFSET_L___M 0x000000FF +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_2_L__SM0_SPUR_CP_OFFSET_L___S 0 +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_2_L___M 0x0000FFFF +#define PHYA_DEMFRONT_0_SM0_SPUR_CONTROL_2_L___S 0 + +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_0_L (0x00400510) +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_0_L___POR 0x000001FF +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_0_L__SM1_SPUR_IDX___POR 0x01FF +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_0_L__SM1_SPUR_IDX___M 0x0000FFFF +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_0_L__SM1_SPUR_IDX___S 0 +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_0_L___M 0x0000FFFF +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_0_L___S 0 + +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_L (0x00400518) +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_L__SM1_3_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_L__SM1_2_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_L__SM1_1_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_L__SM1_0_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_L__SM1_3_SPUR_MASK___M 0x07000000 +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_L__SM1_3_SPUR_MASK___S 24 +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_L__SM1_2_SPUR_MASK___M 0x00070000 +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_L__SM1_2_SPUR_MASK___S 16 +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_L__SM1_1_SPUR_MASK___M 0x00000700 +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_L__SM1_1_SPUR_MASK___S 8 +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_L__SM1_0_SPUR_MASK___M 0x00000007 +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_L__SM1_0_SPUR_MASK___S 0 +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_L___M 0x07070707 +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_L___S 0 + +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_U (0x0040051C) +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_U__SM1_4_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_U__SM1_4_SPUR_MASK___M 0x00000007 +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_U__SM1_4_SPUR_MASK___S 0 +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_U___M 0x00000007 +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_1_U___S 0 + +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_2_L (0x00400520) +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_2_L__SM1_SPUR_CP_OFFSET_R___POR 0x00 +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_2_L__SM1_SPUR_CP_OFFSET_L___POR 0x00 +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_2_L__SM1_SPUR_CP_OFFSET_R___M 0x0000FF00 +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_2_L__SM1_SPUR_CP_OFFSET_R___S 8 +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_2_L__SM1_SPUR_CP_OFFSET_L___M 0x000000FF +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_2_L__SM1_SPUR_CP_OFFSET_L___S 0 +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_2_L___M 0x0000FFFF +#define PHYA_DEMFRONT_0_SM1_SPUR_CONTROL_2_L___S 0 + +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_0_L (0x00400528) +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_0_L___POR 0x000001FF +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_0_L__SM2_SPUR_IDX___POR 0x01FF +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_0_L__SM2_SPUR_IDX___M 0x0000FFFF +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_0_L__SM2_SPUR_IDX___S 0 +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_0_L___M 0x0000FFFF +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_0_L___S 0 + +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_L (0x00400530) +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_L__SM2_3_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_L__SM2_2_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_L__SM2_1_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_L__SM2_0_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_L__SM2_3_SPUR_MASK___M 0x07000000 +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_L__SM2_3_SPUR_MASK___S 24 +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_L__SM2_2_SPUR_MASK___M 0x00070000 +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_L__SM2_2_SPUR_MASK___S 16 +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_L__SM2_1_SPUR_MASK___M 0x00000700 +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_L__SM2_1_SPUR_MASK___S 8 +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_L__SM2_0_SPUR_MASK___M 0x00000007 +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_L__SM2_0_SPUR_MASK___S 0 +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_L___M 0x07070707 +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_L___S 0 + +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_U (0x00400534) +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_U__SM2_4_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_U__SM2_4_SPUR_MASK___M 0x00000007 +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_U__SM2_4_SPUR_MASK___S 0 +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_U___M 0x00000007 +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_1_U___S 0 + +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_2_L (0x00400538) +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_2_L__SM2_SPUR_CP_OFFSET_R___POR 0x00 +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_2_L__SM2_SPUR_CP_OFFSET_L___POR 0x00 +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_2_L__SM2_SPUR_CP_OFFSET_R___M 0x0000FF00 +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_2_L__SM2_SPUR_CP_OFFSET_R___S 8 +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_2_L__SM2_SPUR_CP_OFFSET_L___M 0x000000FF +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_2_L__SM2_SPUR_CP_OFFSET_L___S 0 +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_2_L___M 0x0000FFFF +#define PHYA_DEMFRONT_0_SM2_SPUR_CONTROL_2_L___S 0 + +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_0_L (0x00400540) +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_0_L___POR 0x000001FF +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_0_L__SM3_SPUR_IDX___POR 0x01FF +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_0_L__SM3_SPUR_IDX___M 0x0000FFFF +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_0_L__SM3_SPUR_IDX___S 0 +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_0_L___M 0x0000FFFF +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_0_L___S 0 + +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_L (0x00400548) +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_L__SM3_3_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_L__SM3_2_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_L__SM3_1_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_L__SM3_0_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_L__SM3_3_SPUR_MASK___M 0x07000000 +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_L__SM3_3_SPUR_MASK___S 24 +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_L__SM3_2_SPUR_MASK___M 0x00070000 +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_L__SM3_2_SPUR_MASK___S 16 +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_L__SM3_1_SPUR_MASK___M 0x00000700 +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_L__SM3_1_SPUR_MASK___S 8 +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_L__SM3_0_SPUR_MASK___M 0x00000007 +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_L__SM3_0_SPUR_MASK___S 0 +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_L___M 0x07070707 +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_L___S 0 + +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_U (0x0040054C) +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_U__SM3_4_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_U__SM3_4_SPUR_MASK___M 0x00000007 +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_U__SM3_4_SPUR_MASK___S 0 +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_U___M 0x00000007 +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_1_U___S 0 + +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_2_L (0x00400550) +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_2_L__SM3_SPUR_CP_OFFSET_R___POR 0x00 +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_2_L__SM3_SPUR_CP_OFFSET_L___POR 0x00 +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_2_L__SM3_SPUR_CP_OFFSET_R___M 0x0000FF00 +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_2_L__SM3_SPUR_CP_OFFSET_R___S 8 +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_2_L__SM3_SPUR_CP_OFFSET_L___M 0x000000FF +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_2_L__SM3_SPUR_CP_OFFSET_L___S 0 +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_2_L___M 0x0000FFFF +#define PHYA_DEMFRONT_0_SM3_SPUR_CONTROL_2_L___S 0 + +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_0_L (0x00400558) +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_0_L___POR 0x000001FF +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_0_L__SM4_SPUR_IDX___POR 0x01FF +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_0_L__SM4_SPUR_IDX___M 0x0000FFFF +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_0_L__SM4_SPUR_IDX___S 0 +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_0_L___M 0x0000FFFF +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_0_L___S 0 + +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_L (0x00400560) +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_L__SM4_3_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_L__SM4_2_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_L__SM4_1_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_L__SM4_0_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_L__SM4_3_SPUR_MASK___M 0x07000000 +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_L__SM4_3_SPUR_MASK___S 24 +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_L__SM4_2_SPUR_MASK___M 0x00070000 +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_L__SM4_2_SPUR_MASK___S 16 +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_L__SM4_1_SPUR_MASK___M 0x00000700 +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_L__SM4_1_SPUR_MASK___S 8 +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_L__SM4_0_SPUR_MASK___M 0x00000007 +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_L__SM4_0_SPUR_MASK___S 0 +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_L___M 0x07070707 +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_L___S 0 + +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_U (0x00400564) +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_U__SM4_4_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_U__SM4_4_SPUR_MASK___M 0x00000007 +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_U__SM4_4_SPUR_MASK___S 0 +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_U___M 0x00000007 +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_1_U___S 0 + +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_2_L (0x00400568) +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_2_L__SM4_SPUR_CP_OFFSET_R___POR 0x00 +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_2_L__SM4_SPUR_CP_OFFSET_L___POR 0x00 +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_2_L__SM4_SPUR_CP_OFFSET_R___M 0x0000FF00 +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_2_L__SM4_SPUR_CP_OFFSET_R___S 8 +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_2_L__SM4_SPUR_CP_OFFSET_L___M 0x000000FF +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_2_L__SM4_SPUR_CP_OFFSET_L___S 0 +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_2_L___M 0x0000FFFF +#define PHYA_DEMFRONT_0_SM4_SPUR_CONTROL_2_L___S 0 + +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_0_L (0x00400570) +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_0_L___POR 0x000001FF +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_0_L__SM5_SPUR_IDX___POR 0x01FF +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_0_L__SM5_SPUR_IDX___M 0x0000FFFF +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_0_L__SM5_SPUR_IDX___S 0 +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_0_L___M 0x0000FFFF +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_0_L___S 0 + +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_L (0x00400578) +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_L__SM5_3_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_L__SM5_2_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_L__SM5_1_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_L__SM5_0_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_L__SM5_3_SPUR_MASK___M 0x07000000 +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_L__SM5_3_SPUR_MASK___S 24 +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_L__SM5_2_SPUR_MASK___M 0x00070000 +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_L__SM5_2_SPUR_MASK___S 16 +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_L__SM5_1_SPUR_MASK___M 0x00000700 +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_L__SM5_1_SPUR_MASK___S 8 +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_L__SM5_0_SPUR_MASK___M 0x00000007 +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_L__SM5_0_SPUR_MASK___S 0 +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_L___M 0x07070707 +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_L___S 0 + +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_U (0x0040057C) +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_U__SM5_4_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_U__SM5_4_SPUR_MASK___M 0x00000007 +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_U__SM5_4_SPUR_MASK___S 0 +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_U___M 0x00000007 +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_1_U___S 0 + +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_2_L (0x00400580) +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_2_L__SM5_SPUR_CP_OFFSET_R___POR 0x00 +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_2_L__SM5_SPUR_CP_OFFSET_L___POR 0x00 +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_2_L__SM5_SPUR_CP_OFFSET_R___M 0x0000FF00 +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_2_L__SM5_SPUR_CP_OFFSET_R___S 8 +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_2_L__SM5_SPUR_CP_OFFSET_L___M 0x000000FF +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_2_L__SM5_SPUR_CP_OFFSET_L___S 0 +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_2_L___M 0x0000FFFF +#define PHYA_DEMFRONT_0_SM5_SPUR_CONTROL_2_L___S 0 + +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_0_L (0x00400588) +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_0_L___POR 0x000001FF +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_0_L__SM6_SPUR_IDX___POR 0x01FF +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_0_L__SM6_SPUR_IDX___M 0x0000FFFF +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_0_L__SM6_SPUR_IDX___S 0 +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_0_L___M 0x0000FFFF +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_0_L___S 0 + +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_L (0x00400590) +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_L__SM6_3_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_L__SM6_2_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_L__SM6_1_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_L__SM6_0_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_L__SM6_3_SPUR_MASK___M 0x07000000 +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_L__SM6_3_SPUR_MASK___S 24 +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_L__SM6_2_SPUR_MASK___M 0x00070000 +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_L__SM6_2_SPUR_MASK___S 16 +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_L__SM6_1_SPUR_MASK___M 0x00000700 +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_L__SM6_1_SPUR_MASK___S 8 +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_L__SM6_0_SPUR_MASK___M 0x00000007 +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_L__SM6_0_SPUR_MASK___S 0 +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_L___M 0x07070707 +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_L___S 0 + +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_U (0x00400594) +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_U__SM6_4_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_U__SM6_4_SPUR_MASK___M 0x00000007 +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_U__SM6_4_SPUR_MASK___S 0 +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_U___M 0x00000007 +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_1_U___S 0 + +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_2_L (0x00400598) +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_2_L__SM6_SPUR_CP_OFFSET_R___POR 0x00 +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_2_L__SM6_SPUR_CP_OFFSET_L___POR 0x00 +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_2_L__SM6_SPUR_CP_OFFSET_R___M 0x0000FF00 +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_2_L__SM6_SPUR_CP_OFFSET_R___S 8 +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_2_L__SM6_SPUR_CP_OFFSET_L___M 0x000000FF +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_2_L__SM6_SPUR_CP_OFFSET_L___S 0 +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_2_L___M 0x0000FFFF +#define PHYA_DEMFRONT_0_SM6_SPUR_CONTROL_2_L___S 0 + +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_0_L (0x004005A0) +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_0_L___POR 0x000001FF +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_0_L__SM7_SPUR_IDX___POR 0x01FF +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_0_L__SM7_SPUR_IDX___M 0x0000FFFF +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_0_L__SM7_SPUR_IDX___S 0 +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_0_L___M 0x0000FFFF +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_0_L___S 0 + +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_L (0x004005A8) +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_L__SM7_3_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_L__SM7_2_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_L__SM7_1_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_L__SM7_0_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_L__SM7_3_SPUR_MASK___M 0x07000000 +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_L__SM7_3_SPUR_MASK___S 24 +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_L__SM7_2_SPUR_MASK___M 0x00070000 +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_L__SM7_2_SPUR_MASK___S 16 +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_L__SM7_1_SPUR_MASK___M 0x00000700 +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_L__SM7_1_SPUR_MASK___S 8 +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_L__SM7_0_SPUR_MASK___M 0x00000007 +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_L__SM7_0_SPUR_MASK___S 0 +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_L___M 0x07070707 +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_L___S 0 + +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_U (0x004005AC) +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_U__SM7_4_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_U__SM7_4_SPUR_MASK___M 0x00000007 +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_U__SM7_4_SPUR_MASK___S 0 +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_U___M 0x00000007 +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_1_U___S 0 + +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_2_L (0x004005B0) +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_2_L__SM7_SPUR_CP_OFFSET_R___POR 0x00 +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_2_L__SM7_SPUR_CP_OFFSET_L___POR 0x00 +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_2_L__SM7_SPUR_CP_OFFSET_R___M 0x0000FF00 +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_2_L__SM7_SPUR_CP_OFFSET_R___S 8 +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_2_L__SM7_SPUR_CP_OFFSET_L___M 0x000000FF +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_2_L__SM7_SPUR_CP_OFFSET_L___S 0 +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_2_L___M 0x0000FFFF +#define PHYA_DEMFRONT_0_SM7_SPUR_CONTROL_2_L___S 0 + +#define PHYA_DEMFRONT_0_CHE_CONTROL_0_L (0x004005B8) +#define PHYA_DEMFRONT_0_CHE_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CHE_CONTROL_0_L___POR 0x02000000 +#define PHYA_DEMFRONT_0_CHE_CONTROL_0_L__FREQ_SEL_ID_LAG_SEL___POR 0x2 +#define PHYA_DEMFRONT_0_CHE_CONTROL_0_L__SLOPE_SCALE___POR 0x0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_0_L__LOG2_FFT_SIZE___POR 0x0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_0_L__HE_INTERPOLATION___POR 0x0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_0_L__FREQ_SEL_ID_LAG_SEL___M 0x03000000 +#define PHYA_DEMFRONT_0_CHE_CONTROL_0_L__FREQ_SEL_ID_LAG_SEL___S 24 +#define PHYA_DEMFRONT_0_CHE_CONTROL_0_L__SLOPE_SCALE___M 0x00070000 +#define PHYA_DEMFRONT_0_CHE_CONTROL_0_L__SLOPE_SCALE___S 16 +#define PHYA_DEMFRONT_0_CHE_CONTROL_0_L__LOG2_FFT_SIZE___M 0x00000F00 +#define PHYA_DEMFRONT_0_CHE_CONTROL_0_L__LOG2_FFT_SIZE___S 8 +#define PHYA_DEMFRONT_0_CHE_CONTROL_0_L__HE_INTERPOLATION___M 0x00000003 +#define PHYA_DEMFRONT_0_CHE_CONTROL_0_L__HE_INTERPOLATION___S 0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_0_L___M 0x03070F03 +#define PHYA_DEMFRONT_0_CHE_CONTROL_0_L___S 0 + +#define PHYA_DEMFRONT_0_CHE_CONTROL_0_U (0x004005BC) +#define PHYA_DEMFRONT_0_CHE_CONTROL_0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CHE_CONTROL_0_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_CHE_CONTROL_0_U__SUBBAND_ROT_DIS___POR 0x0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_0_U__EN_CSD_REMOVAL___POR 0x0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_0_U__EN_SLOPE_ADDITION___POR 0x0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_0_U__EN_SLOPE_REMOVAL___POR 0x0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_0_U__SUBBAND_ROT_DIS___M 0x01000000 +#define PHYA_DEMFRONT_0_CHE_CONTROL_0_U__SUBBAND_ROT_DIS___S 24 +#define PHYA_DEMFRONT_0_CHE_CONTROL_0_U__EN_CSD_REMOVAL___M 0x00010000 +#define PHYA_DEMFRONT_0_CHE_CONTROL_0_U__EN_CSD_REMOVAL___S 16 +#define PHYA_DEMFRONT_0_CHE_CONTROL_0_U__EN_SLOPE_ADDITION___M 0x00000100 +#define PHYA_DEMFRONT_0_CHE_CONTROL_0_U__EN_SLOPE_ADDITION___S 8 +#define PHYA_DEMFRONT_0_CHE_CONTROL_0_U__EN_SLOPE_REMOVAL___M 0x00000001 +#define PHYA_DEMFRONT_0_CHE_CONTROL_0_U__EN_SLOPE_REMOVAL___S 0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_0_U___M 0x01010101 +#define PHYA_DEMFRONT_0_CHE_CONTROL_0_U___S 0 + +#define PHYA_DEMFRONT_0_CHE_CONTROL_1_L (0x004005C0) +#define PHYA_DEMFRONT_0_CHE_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CHE_CONTROL_1_L___POR 0x02000000 +#define PHYA_DEMFRONT_0_CHE_CONTROL_1_L__CC_START_TONE___POR 0x200 +#define PHYA_DEMFRONT_0_CHE_CONTROL_1_L__FE_FILTER_ROT_TABLE_SEL___POR 0x0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_1_L__EN_QRMEM_SPLIT___POR 0x0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_1_L__CC_START_TONE___M 0x03FF0000 +#define PHYA_DEMFRONT_0_CHE_CONTROL_1_L__CC_START_TONE___S 16 +#define PHYA_DEMFRONT_0_CHE_CONTROL_1_L__FE_FILTER_ROT_TABLE_SEL___M 0x00000300 +#define PHYA_DEMFRONT_0_CHE_CONTROL_1_L__FE_FILTER_ROT_TABLE_SEL___S 8 +#define PHYA_DEMFRONT_0_CHE_CONTROL_1_L__EN_QRMEM_SPLIT___M 0x00000001 +#define PHYA_DEMFRONT_0_CHE_CONTROL_1_L__EN_QRMEM_SPLIT___S 0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_1_L___M 0x03FF0301 +#define PHYA_DEMFRONT_0_CHE_CONTROL_1_L___S 0 + +#define PHYA_DEMFRONT_0_CHE_CONTROL_1_U (0x004005C4) +#define PHYA_DEMFRONT_0_CHE_CONTROL_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CHE_CONTROL_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_CHE_CONTROL_1_U__DFCHE_EN___POR 0x0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_1_U__DSRC_EN___POR 0x0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_1_U__LSIG_DF_EN___POR 0x0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_1_U__DSRC_ADAPTIVE_ADD_EN___POR 0x0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_1_U__DFCHE_EN___M 0x01000000 +#define PHYA_DEMFRONT_0_CHE_CONTROL_1_U__DFCHE_EN___S 24 +#define PHYA_DEMFRONT_0_CHE_CONTROL_1_U__DSRC_EN___M 0x00010000 +#define PHYA_DEMFRONT_0_CHE_CONTROL_1_U__DSRC_EN___S 16 +#define PHYA_DEMFRONT_0_CHE_CONTROL_1_U__LSIG_DF_EN___M 0x00000100 +#define PHYA_DEMFRONT_0_CHE_CONTROL_1_U__LSIG_DF_EN___S 8 +#define PHYA_DEMFRONT_0_CHE_CONTROL_1_U__DSRC_ADAPTIVE_ADD_EN___M 0x00000001 +#define PHYA_DEMFRONT_0_CHE_CONTROL_1_U__DSRC_ADAPTIVE_ADD_EN___S 0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_1_U___M 0x01010101 +#define PHYA_DEMFRONT_0_CHE_CONTROL_1_U___S 0 + +#define PHYA_DEMFRONT_0_CHE_CONTROL_2_L (0x004005C8) +#define PHYA_DEMFRONT_0_CHE_CONTROL_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CHE_CONTROL_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_CHE_CONTROL_2_L__ENA_CHE_AVERAGE___POR 0x0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_2_L__EN_RESCALE_AMT_SHIFT___POR 0x0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_2_L__COMPUTE_AMT_SHIFT___POR 0x0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_2_L__PBD_EN___POR 0x0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_2_L__ENA_CHE_AVERAGE___M 0x01000000 +#define PHYA_DEMFRONT_0_CHE_CONTROL_2_L__ENA_CHE_AVERAGE___S 24 +#define PHYA_DEMFRONT_0_CHE_CONTROL_2_L__EN_RESCALE_AMT_SHIFT___M 0x00010000 +#define PHYA_DEMFRONT_0_CHE_CONTROL_2_L__EN_RESCALE_AMT_SHIFT___S 16 +#define PHYA_DEMFRONT_0_CHE_CONTROL_2_L__COMPUTE_AMT_SHIFT___M 0x00000100 +#define PHYA_DEMFRONT_0_CHE_CONTROL_2_L__COMPUTE_AMT_SHIFT___S 8 +#define PHYA_DEMFRONT_0_CHE_CONTROL_2_L__PBD_EN___M 0x00000001 +#define PHYA_DEMFRONT_0_CHE_CONTROL_2_L__PBD_EN___S 0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_2_L___M 0x01010101 +#define PHYA_DEMFRONT_0_CHE_CONTROL_2_L___S 0 + +#define PHYA_DEMFRONT_0_CHE_CONTROL_2_U (0x004005CC) +#define PHYA_DEMFRONT_0_CHE_CONTROL_2_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CHE_CONTROL_2_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_CHE_CONTROL_2_U__DFHD_CMBN_ALPHA___POR 0x0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_2_U__EN_DFHD_CHAN_TRACK_ON_PILOT___POR 0x0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_2_U__EN_DFHD_CHAN_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_2_U__EN_DFHD_CHAN_FILTER___POR 0x0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_2_U__DFHD_CMBN_ALPHA___M 0x07000000 +#define PHYA_DEMFRONT_0_CHE_CONTROL_2_U__DFHD_CMBN_ALPHA___S 24 +#define PHYA_DEMFRONT_0_CHE_CONTROL_2_U__EN_DFHD_CHAN_TRACK_ON_PILOT___M 0x00010000 +#define PHYA_DEMFRONT_0_CHE_CONTROL_2_U__EN_DFHD_CHAN_TRACK_ON_PILOT___S 16 +#define PHYA_DEMFRONT_0_CHE_CONTROL_2_U__EN_DFHD_CHAN_MASK___M 0x00000100 +#define PHYA_DEMFRONT_0_CHE_CONTROL_2_U__EN_DFHD_CHAN_MASK___S 8 +#define PHYA_DEMFRONT_0_CHE_CONTROL_2_U__EN_DFHD_CHAN_FILTER___M 0x00000001 +#define PHYA_DEMFRONT_0_CHE_CONTROL_2_U__EN_DFHD_CHAN_FILTER___S 0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_2_U___M 0x07010101 +#define PHYA_DEMFRONT_0_CHE_CONTROL_2_U___S 0 + +#define PHYA_DEMFRONT_0_CHE_CONTROL_3_L (0x004005D0) +#define PHYA_DEMFRONT_0_CHE_CONTROL_3_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CHE_CONTROL_3_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_CHE_CONTROL_3_L__SDF_CODE_RATE___POR 0x0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_3_L__SDF_BUFFER_MODE___POR 0x0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_3_L__SDF_DTONE_BUFFER_IDX___POR 0x0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_3_L__SDF_DTONE_BUFFER_EN___POR 0x0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_3_L__SDF_CODE_RATE___M 0x03000000 +#define PHYA_DEMFRONT_0_CHE_CONTROL_3_L__SDF_CODE_RATE___S 24 +#define PHYA_DEMFRONT_0_CHE_CONTROL_3_L__SDF_BUFFER_MODE___M 0x00010000 +#define PHYA_DEMFRONT_0_CHE_CONTROL_3_L__SDF_BUFFER_MODE___S 16 +#define PHYA_DEMFRONT_0_CHE_CONTROL_3_L__SDF_DTONE_BUFFER_IDX___M 0x00000700 +#define PHYA_DEMFRONT_0_CHE_CONTROL_3_L__SDF_DTONE_BUFFER_IDX___S 8 +#define PHYA_DEMFRONT_0_CHE_CONTROL_3_L__SDF_DTONE_BUFFER_EN___M 0x00000001 +#define PHYA_DEMFRONT_0_CHE_CONTROL_3_L__SDF_DTONE_BUFFER_EN___S 0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_3_L___M 0x03010701 +#define PHYA_DEMFRONT_0_CHE_CONTROL_3_L___S 0 + +#define PHYA_DEMFRONT_0_CHE_CONTROL_3_U (0x004005D4) +#define PHYA_DEMFRONT_0_CHE_CONTROL_3_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CHE_CONTROL_3_U___POR 0x00010000 +#define PHYA_DEMFRONT_0_CHE_CONTROL_3_U__DSBL_SM_DC_EDGE_TONE_NUM___POR 0x0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_3_U__EN_TONE_REPLACEMENT___POR 0x1 +#define PHYA_DEMFRONT_0_CHE_CONTROL_3_U__CHE_CA_TONE_NUM___POR 0x000 +#define PHYA_DEMFRONT_0_CHE_CONTROL_3_U__DSBL_SM_DC_EDGE_TONE_NUM___M 0x0F000000 +#define PHYA_DEMFRONT_0_CHE_CONTROL_3_U__DSBL_SM_DC_EDGE_TONE_NUM___S 24 +#define PHYA_DEMFRONT_0_CHE_CONTROL_3_U__EN_TONE_REPLACEMENT___M 0x00010000 +#define PHYA_DEMFRONT_0_CHE_CONTROL_3_U__EN_TONE_REPLACEMENT___S 16 +#define PHYA_DEMFRONT_0_CHE_CONTROL_3_U__CHE_CA_TONE_NUM___M 0x000003FF +#define PHYA_DEMFRONT_0_CHE_CONTROL_3_U__CHE_CA_TONE_NUM___S 0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_3_U___M 0x0F0103FF +#define PHYA_DEMFRONT_0_CHE_CONTROL_3_U___S 0 + +#define PHYA_DEMFRONT_0_CHE_CONTROL_4_L (0x004005D8) +#define PHYA_DEMFRONT_0_CHE_CONTROL_4_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CHE_CONTROL_4_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_CHE_CONTROL_4_L__CC_TONE_DECIMATION___POR 0x0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_4_L__RTT_PACK_MODE___POR 0x0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_4_L__SM_FILTER_NOT_FLAT_OVERRIDE___POR 0x0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_4_L__CC_TONE_DECIMATION___M 0x00030000 +#define PHYA_DEMFRONT_0_CHE_CONTROL_4_L__CC_TONE_DECIMATION___S 16 +#define PHYA_DEMFRONT_0_CHE_CONTROL_4_L__RTT_PACK_MODE___M 0x00000300 +#define PHYA_DEMFRONT_0_CHE_CONTROL_4_L__RTT_PACK_MODE___S 8 +#define PHYA_DEMFRONT_0_CHE_CONTROL_4_L__SM_FILTER_NOT_FLAT_OVERRIDE___M 0x00000001 +#define PHYA_DEMFRONT_0_CHE_CONTROL_4_L__SM_FILTER_NOT_FLAT_OVERRIDE___S 0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_4_L___M 0x00030301 +#define PHYA_DEMFRONT_0_CHE_CONTROL_4_L___S 0 + +#define PHYA_DEMFRONT_0_CHE_CONTROL_4_U (0x004005DC) +#define PHYA_DEMFRONT_0_CHE_CONTROL_4_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CHE_CONTROL_4_U___POR 0x01010000 +#define PHYA_DEMFRONT_0_CHE_CONTROL_4_U__EN_HIGH_FREQ_SELECT_CHECK___POR 0x1 +#define PHYA_DEMFRONT_0_CHE_CONTROL_4_U__CHAN_SM_FILT_BACKOFF___POR 0x1 +#define PHYA_DEMFRONT_0_CHE_CONTROL_4_U__LTF_PATTERN_SHIFT___POR 0x000 +#define PHYA_DEMFRONT_0_CHE_CONTROL_4_U__EN_HIGH_FREQ_SELECT_CHECK___M 0x01000000 +#define PHYA_DEMFRONT_0_CHE_CONTROL_4_U__EN_HIGH_FREQ_SELECT_CHECK___S 24 +#define PHYA_DEMFRONT_0_CHE_CONTROL_4_U__CHAN_SM_FILT_BACKOFF___M 0x00010000 +#define PHYA_DEMFRONT_0_CHE_CONTROL_4_U__CHAN_SM_FILT_BACKOFF___S 16 +#define PHYA_DEMFRONT_0_CHE_CONTROL_4_U__LTF_PATTERN_SHIFT___M 0x000003FF +#define PHYA_DEMFRONT_0_CHE_CONTROL_4_U__LTF_PATTERN_SHIFT___S 0 +#define PHYA_DEMFRONT_0_CHE_CONTROL_4_U___M 0x010103FF +#define PHYA_DEMFRONT_0_CHE_CONTROL_4_U___S 0 + +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_L (0x004005E0) +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_L__DELTA_SLOPE_COEF_EXP_BW___POR 0x000 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_L__DELTA_SLOPE_COEF_MAN_BW___POR 0x0000 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_L__DELTA_SLOPE_COEF_EXP_BW___M 0x03FF0000 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_L__DELTA_SLOPE_COEF_EXP_BW___S 16 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_L__DELTA_SLOPE_COEF_MAN_BW___M 0x00007FFF +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_L__DELTA_SLOPE_COEF_MAN_BW___S 0 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_L___M 0x03FF7FFF +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_L___S 0 + +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_U (0x004005E4) +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_U__PTC_PHASE_OFFSET_BIAS___POR 0x0000 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_U__DELTAF_SIGN___POR 0x0 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_U__PTC_PHASE_OFFSET_BIAS___M 0xFFFF0000 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_U__PTC_PHASE_OFFSET_BIAS___S 16 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_U__DELTAF_SIGN___M 0x00000001 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_U__DELTAF_SIGN___S 0 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_U___M 0xFFFF0001 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_0_U___S 0 + +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_L (0x004005E8) +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_L__TARGET_SLOPE___POR 0x00000000 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_L__TARGET_SLOPE___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_L__TARGET_SLOPE___S 0 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_L___S 0 + +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_U (0x004005EC) +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_U__ENABLE_PPM_RESCUE___POR 0x0 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_U__ENABLE_OFFSET_FILTER___POR 0x0 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_U__SLOPE_MODE___POR 0x0 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_U__RESET_SLOPE___POR 0x0 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_U__ENABLE_PPM_RESCUE___M 0x01000000 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_U__ENABLE_PPM_RESCUE___S 24 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_U__ENABLE_OFFSET_FILTER___M 0x00010000 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_U__ENABLE_OFFSET_FILTER___S 16 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_U__SLOPE_MODE___M 0x00000300 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_U__SLOPE_MODE___S 8 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_U__RESET_SLOPE___M 0x00000001 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_U__RESET_SLOPE___S 0 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_U___M 0x01010301 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_1_U___S 0 + +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_L (0x004005F0) +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_L___POR 0x00000300 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_L__RESET_DATA_COUNT___POR 0x0 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_L__USE_CORDIC_HT___POR 0x0 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_L__PMAG_CORR_FILTER_SHIFT___POR 0x3 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_L__EN_SCALEUP_3DB___POR 0x0 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_L__RESET_DATA_COUNT___M 0x01000000 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_L__RESET_DATA_COUNT___S 24 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_L__USE_CORDIC_HT___M 0x00010000 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_L__USE_CORDIC_HT___S 16 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_L__PMAG_CORR_FILTER_SHIFT___M 0x00000300 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_L__PMAG_CORR_FILTER_SHIFT___S 8 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_L__EN_SCALEUP_3DB___M 0x00000001 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_L__EN_SCALEUP_3DB___S 0 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_L___M 0x01010301 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_L___S 0 + +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_U (0x004005F4) +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_U__PILOT_ROTATE_EN___POR 0x0 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_U__DLTF_SYMBOL___POR 0x0 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_U__PILOT_1SS___POR 0x0 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_U__PILOT_ROTATE_EN___M 0x00010000 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_U__PILOT_ROTATE_EN___S 16 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_U__DLTF_SYMBOL___M 0x00000100 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_U__DLTF_SYMBOL___S 8 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_U__PILOT_1SS___M 0x00000001 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_U__PILOT_1SS___S 0 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_U___M 0x00010101 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_2_U___S 0 + +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_L (0x004005F8) +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_L__CFO_CORR_SCALE_FRAC_SEL___POR 0x0 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_L__RESET_MAG_TRACK___POR 0x0 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_L__MRC_OFFSET_VHTDLTF_CORR___POR 0x000 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_L__CFO_CORR_SCALE_FRAC_SEL___M 0x01000000 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_L__CFO_CORR_SCALE_FRAC_SEL___S 24 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_L__RESET_MAG_TRACK___M 0x00010000 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_L__RESET_MAG_TRACK___S 16 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_L__MRC_OFFSET_VHTDLTF_CORR___M 0x000003FF +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_L__MRC_OFFSET_VHTDLTF_CORR___S 0 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_L___M 0x010103FF +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_L___S 0 + +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_U (0x004005FC) +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_U__ENABLE_MAGNITUDE_TRACK___POR 0x0 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_U__SEC_SEGMENT___POR 0x0 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_U__CFO_CORR_SCALE_FRAC_BW___POR 0x000 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_U__ENABLE_MAGNITUDE_TRACK___M 0x01000000 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_U__ENABLE_MAGNITUDE_TRACK___S 24 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_U__SEC_SEGMENT___M 0x00010000 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_U__SEC_SEGMENT___S 16 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_U__CFO_CORR_SCALE_FRAC_BW___M 0x000003FF +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_U__CFO_CORR_SCALE_FRAC_BW___S 0 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_U___M 0x010103FF +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_3_U___S 0 + +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_L (0x00400600) +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_L__COMPARE_REF___POR 0x0 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_L__COMPUTE_REF___POR 0x0 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_L__TIMING_BACKOFF___POR 0x00 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_L__ENABLE_LIN_EVM___POR 0x0 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_L__COMPARE_REF___M 0x01000000 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_L__COMPARE_REF___S 24 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_L__COMPUTE_REF___M 0x00010000 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_L__COMPUTE_REF___S 16 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_L__TIMING_BACKOFF___M 0x00001F00 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_L__TIMING_BACKOFF___S 8 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_L__ENABLE_LIN_EVM___M 0x00000001 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_L__ENABLE_LIN_EVM___S 0 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_L___M 0x01011F01 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_L___S 0 + +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_U (0x00400604) +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_U__DEMF_SYMBOL_CNT___POR 0x00000000 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_U__DEMF_SYMBOL_CNT___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_U__DEMF_SYMBOL_CNT___S 0 +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_PTC_PTC_CONTROL_4_U___S 0 + +#define PHYA_DEMFRONT_0_USER_SPARE_2_L (0x00400608) +#define PHYA_DEMFRONT_0_USER_SPARE_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_USER_SPARE_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_USER_SPARE_2_L__NEXT_DESC_WR_PTC_SPARE_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_USER_SPARE_2_L__NEXT_DESC_WR_PTC_SPARE_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_USER_SPARE_2_L__NEXT_DESC_WR_PTC_SPARE_0___S 0 +#define PHYA_DEMFRONT_0_USER_SPARE_2_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_USER_SPARE_2_L___S 0 + +#define PHYA_DEMFRONT_0_USER_SPARE_2_U (0x0040060C) +#define PHYA_DEMFRONT_0_USER_SPARE_2_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_USER_SPARE_2_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_USER_SPARE_2_U__NEXT_DESC_WR_PTC_SPARE_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_USER_SPARE_2_U__NEXT_DESC_WR_PTC_SPARE_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_USER_SPARE_2_U__NEXT_DESC_WR_PTC_SPARE_1___S 0 +#define PHYA_DEMFRONT_0_USER_SPARE_2_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_USER_SPARE_2_U___S 0 + +#define PHYA_DEMFRONT_0_DCN_CONTROL_L (0x00400610) +#define PHYA_DEMFRONT_0_DCN_CONTROL_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_DCN_CONTROL_L___POR 0x00000100 +#define PHYA_DEMFRONT_0_DCN_CONTROL_L__DCN_STRIDE_MODE___POR 0x0 +#define PHYA_DEMFRONT_0_DCN_CONTROL_L__DCN_MIRROR_EN_SEG1___POR 0x1 +#define PHYA_DEMFRONT_0_DCN_CONTROL_L__DCN_MIRROR_EN_SEG0___POR 0x0 +#define PHYA_DEMFRONT_0_DCN_CONTROL_L__DCN_STRIDE_MODE___M 0x00030000 +#define PHYA_DEMFRONT_0_DCN_CONTROL_L__DCN_STRIDE_MODE___S 16 +#define PHYA_DEMFRONT_0_DCN_CONTROL_L__DCN_MIRROR_EN_SEG1___M 0x00000100 +#define PHYA_DEMFRONT_0_DCN_CONTROL_L__DCN_MIRROR_EN_SEG1___S 8 +#define PHYA_DEMFRONT_0_DCN_CONTROL_L__DCN_MIRROR_EN_SEG0___M 0x00000001 +#define PHYA_DEMFRONT_0_DCN_CONTROL_L__DCN_MIRROR_EN_SEG0___S 0 +#define PHYA_DEMFRONT_0_DCN_CONTROL_L___M 0x00030101 +#define PHYA_DEMFRONT_0_DCN_CONTROL_L___S 0 + +#define PHYA_DEMFRONT_0_SYM_FDPP_CONTROL_L (0x00400618) +#define PHYA_DEMFRONT_0_SYM_FDPP_CONTROL_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SYM_FDPP_CONTROL_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SYM_FDPP_CONTROL_L__ENABLE_DC_NOTCH_COMP___POR 0x0 +#define PHYA_DEMFRONT_0_SYM_FDPP_CONTROL_L__ENABLE_GAIN_RATIO___POR 0x0 +#define PHYA_DEMFRONT_0_SYM_FDPP_CONTROL_L__ENABLE_DC_NOTCH_COMP___M 0x00000100 +#define PHYA_DEMFRONT_0_SYM_FDPP_CONTROL_L__ENABLE_DC_NOTCH_COMP___S 8 +#define PHYA_DEMFRONT_0_SYM_FDPP_CONTROL_L__ENABLE_GAIN_RATIO___M 0x00000001 +#define PHYA_DEMFRONT_0_SYM_FDPP_CONTROL_L__ENABLE_GAIN_RATIO___S 0 +#define PHYA_DEMFRONT_0_SYM_FDPP_CONTROL_L___M 0x00000101 +#define PHYA_DEMFRONT_0_SYM_FDPP_CONTROL_L___S 0 + +#define PHYA_DEMFRONT_0_SYM_QRE_CONTROL_L (0x00400620) +#define PHYA_DEMFRONT_0_SYM_QRE_CONTROL_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SYM_QRE_CONTROL_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SYM_QRE_CONTROL_L__QRE_CHAIN_MASK___POR 0x00 +#define PHYA_DEMFRONT_0_SYM_QRE_CONTROL_L__QRE_CHAIN_MASK___M 0x000000FF +#define PHYA_DEMFRONT_0_SYM_QRE_CONTROL_L__QRE_CHAIN_MASK___S 0 +#define PHYA_DEMFRONT_0_SYM_QRE_CONTROL_L___M 0x000000FF +#define PHYA_DEMFRONT_0_SYM_QRE_CONTROL_L___S 0 + +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_0_L (0x00400628) +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_0_L___POR 0x0FFFFFFF +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_0_L__NEXT_DESC_PROG_THR___POR 0xFFF +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_0_L__SYM_PROC_THR___POR 0xFFFF +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_0_L__NEXT_DESC_PROG_THR___M 0x0FFF0000 +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_0_L__NEXT_DESC_PROG_THR___S 16 +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_0_L__SYM_PROC_THR___M 0x0000FFFF +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_0_L__SYM_PROC_THR___S 0 +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_0_L___M 0x0FFFFFFF +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_0_L___S 0 + +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_1_L (0x00400630) +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_1_L__ERROR_STATE_MASK_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_1_L__ERROR_STATE_MASK_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_1_L__ERROR_STATE_MASK_0___S 0 +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_1_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_1_L___S 0 + +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_1_U (0x00400634) +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_1_U__ERROR_STATE_MASK_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_1_U__ERROR_STATE_MASK_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_1_U__ERROR_STATE_MASK_1___S 0 +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_1_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_1_U___S 0 + +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_L (0x00400638) +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_L__EN_RAW_CV_DUMP___POR 0x0 +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_L__RAW_FFT_DUMP_MEM_SEL___POR 0x0 +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_L__RAW_FFT_DUMP_ADR_OFFSET___POR 0x0000 +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_L__EN_RAW_CV_DUMP___M 0x01000000 +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_L__EN_RAW_CV_DUMP___S 24 +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_L__RAW_FFT_DUMP_MEM_SEL___M 0x00010000 +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_L__RAW_FFT_DUMP_MEM_SEL___S 16 +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_L__RAW_FFT_DUMP_ADR_OFFSET___M 0x0000FFFF +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_L__RAW_FFT_DUMP_ADR_OFFSET___S 0 +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_L___M 0x0101FFFF +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_L___S 0 + +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_U (0x0040063C) +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE2___POR 0x00 +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE1___POR 0x00 +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE0___POR 0x00 +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_U__EN_PHYDBG___POR 0x0 +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE2___M 0xFF000000 +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE2___S 24 +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE1___M 0x00FF0000 +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE1___S 16 +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE0___M 0x0000FF00 +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE0___S 8 +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_U__EN_PHYDBG___M 0x00000001 +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_U__EN_PHYDBG___S 0 +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_U___M 0xFFFFFF01 +#define PHYA_DEMFRONT_0_SYM_DEBUG_CONTROL_2_U___S 0 + +#define PHYA_DEMFRONT_0_RXTD_GAIN_RATIO0_L (0x00400640) +#define PHYA_DEMFRONT_0_RXTD_GAIN_RATIO0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RXTD_GAIN_RATIO0_L___POR 0x00000080 +#define PHYA_DEMFRONT_0_RXTD_GAIN_RATIO0_L__TOTAL_GAIN_0___POR 0x000 +#define PHYA_DEMFRONT_0_RXTD_GAIN_RATIO0_L__GAIN_RATIO_SQ_0___POR 0x00 +#define PHYA_DEMFRONT_0_RXTD_GAIN_RATIO0_L__FDPP_GAIN_RATIO_0___POR 0x80 +#define PHYA_DEMFRONT_0_RXTD_GAIN_RATIO0_L__TOTAL_GAIN_0___M 0x03FF0000 +#define PHYA_DEMFRONT_0_RXTD_GAIN_RATIO0_L__TOTAL_GAIN_0___S 16 +#define PHYA_DEMFRONT_0_RXTD_GAIN_RATIO0_L__GAIN_RATIO_SQ_0___M 0x0000FF00 +#define PHYA_DEMFRONT_0_RXTD_GAIN_RATIO0_L__GAIN_RATIO_SQ_0___S 8 +#define PHYA_DEMFRONT_0_RXTD_GAIN_RATIO0_L__FDPP_GAIN_RATIO_0___M 0x000000FF +#define PHYA_DEMFRONT_0_RXTD_GAIN_RATIO0_L__FDPP_GAIN_RATIO_0___S 0 +#define PHYA_DEMFRONT_0_RXTD_GAIN_RATIO0_L___M 0x03FFFFFF +#define PHYA_DEMFRONT_0_RXTD_GAIN_RATIO0_L___S 0 + +#define PHYA_DEMFRONT_0_RXTD_GAIN_RATIO1_L (0x00400648) +#define PHYA_DEMFRONT_0_RXTD_GAIN_RATIO1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_RXTD_GAIN_RATIO1_L___POR 0x00000080 +#define PHYA_DEMFRONT_0_RXTD_GAIN_RATIO1_L__TOTAL_GAIN_1___POR 0x000 +#define PHYA_DEMFRONT_0_RXTD_GAIN_RATIO1_L__GAIN_RATIO_SQ_1___POR 0x00 +#define PHYA_DEMFRONT_0_RXTD_GAIN_RATIO1_L__FDPP_GAIN_RATIO_1___POR 0x80 +#define PHYA_DEMFRONT_0_RXTD_GAIN_RATIO1_L__TOTAL_GAIN_1___M 0x03FF0000 +#define PHYA_DEMFRONT_0_RXTD_GAIN_RATIO1_L__TOTAL_GAIN_1___S 16 +#define PHYA_DEMFRONT_0_RXTD_GAIN_RATIO1_L__GAIN_RATIO_SQ_1___M 0x0000FF00 +#define PHYA_DEMFRONT_0_RXTD_GAIN_RATIO1_L__GAIN_RATIO_SQ_1___S 8 +#define PHYA_DEMFRONT_0_RXTD_GAIN_RATIO1_L__FDPP_GAIN_RATIO_1___M 0x000000FF +#define PHYA_DEMFRONT_0_RXTD_GAIN_RATIO1_L__FDPP_GAIN_RATIO_1___S 0 +#define PHYA_DEMFRONT_0_RXTD_GAIN_RATIO1_L___M 0x03FFFFFF +#define PHYA_DEMFRONT_0_RXTD_GAIN_RATIO1_L___S 0 + +#define PHYA_DEMFRONT_0_NOISE_PWR_0_L (0x00400660) +#define PHYA_DEMFRONT_0_NOISE_PWR_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_NOISE_PWR_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_NOISE_PWR_0_L__FRAME_END___POR 0x0 +#define PHYA_DEMFRONT_0_NOISE_PWR_0_L__RESTART___POR 0x0 +#define PHYA_DEMFRONT_0_NOISE_PWR_0_L__FRAME_DETECT___POR 0x0 +#define PHYA_DEMFRONT_0_NOISE_PWR_0_L__FRAME_END___M 0x00010000 +#define PHYA_DEMFRONT_0_NOISE_PWR_0_L__FRAME_END___S 16 +#define PHYA_DEMFRONT_0_NOISE_PWR_0_L__RESTART___M 0x00000100 +#define PHYA_DEMFRONT_0_NOISE_PWR_0_L__RESTART___S 8 +#define PHYA_DEMFRONT_0_NOISE_PWR_0_L__FRAME_DETECT___M 0x00000001 +#define PHYA_DEMFRONT_0_NOISE_PWR_0_L__FRAME_DETECT___S 0 +#define PHYA_DEMFRONT_0_NOISE_PWR_0_L___M 0x00010101 +#define PHYA_DEMFRONT_0_NOISE_PWR_0_L___S 0 + +#define PHYA_DEMFRONT_0_NOISE_PWR_0_U (0x00400664) +#define PHYA_DEMFRONT_0_NOISE_PWR_0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_NOISE_PWR_0_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_NOISE_PWR_0_U__BTCF_TIMING_EST_RESULT___POR 0x0000 +#define PHYA_DEMFRONT_0_NOISE_PWR_0_U__SYM_COUNT___POR 0x000 +#define PHYA_DEMFRONT_0_NOISE_PWR_0_U__BTCF_TIMING_EST_RESULT___M 0xFFFF0000 +#define PHYA_DEMFRONT_0_NOISE_PWR_0_U__BTCF_TIMING_EST_RESULT___S 16 +#define PHYA_DEMFRONT_0_NOISE_PWR_0_U__SYM_COUNT___M 0x000003FF +#define PHYA_DEMFRONT_0_NOISE_PWR_0_U__SYM_COUNT___S 0 +#define PHYA_DEMFRONT_0_NOISE_PWR_0_U___M 0xFFFF03FF +#define PHYA_DEMFRONT_0_NOISE_PWR_0_U___S 0 + +#define PHYA_DEMFRONT_0_NOISE_PWR_1_L (0x00400668) +#define PHYA_DEMFRONT_0_NOISE_PWR_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_NOISE_PWR_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_NOISE_PWR_1_L__COARSE_CFO_EST_RESULT___POR 0x0000 +#define PHYA_DEMFRONT_0_NOISE_PWR_1_L__BTCF_FINE_CFO_EST_RESULT___POR 0x0000 +#define PHYA_DEMFRONT_0_NOISE_PWR_1_L__COARSE_CFO_EST_RESULT___M 0xFFFF0000 +#define PHYA_DEMFRONT_0_NOISE_PWR_1_L__COARSE_CFO_EST_RESULT___S 16 +#define PHYA_DEMFRONT_0_NOISE_PWR_1_L__BTCF_FINE_CFO_EST_RESULT___M 0x0000FFFF +#define PHYA_DEMFRONT_0_NOISE_PWR_1_L__BTCF_FINE_CFO_EST_RESULT___S 0 +#define PHYA_DEMFRONT_0_NOISE_PWR_1_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_NOISE_PWR_1_L___S 0 + +#define PHYA_DEMFRONT_0_NOISE_PWR_1_U (0x0040066C) +#define PHYA_DEMFRONT_0_NOISE_PWR_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_NOISE_PWR_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_NOISE_PWR_1_U__NOISE_PWR_SQRT_EXP___POR 0x0 +#define PHYA_DEMFRONT_0_NOISE_PWR_1_U__NOISE_PWR_SQRT_MAN___POR 0x00 +#define PHYA_DEMFRONT_0_NOISE_PWR_1_U__SNR_EST_MMSE_IS___POR 0x00 +#define PHYA_DEMFRONT_0_NOISE_PWR_1_U__VSRC_DEPTH___POR 0x00 +#define PHYA_DEMFRONT_0_NOISE_PWR_1_U__NOISE_PWR_SQRT_EXP___M 0x0F000000 +#define PHYA_DEMFRONT_0_NOISE_PWR_1_U__NOISE_PWR_SQRT_EXP___S 24 +#define PHYA_DEMFRONT_0_NOISE_PWR_1_U__NOISE_PWR_SQRT_MAN___M 0x003F0000 +#define PHYA_DEMFRONT_0_NOISE_PWR_1_U__NOISE_PWR_SQRT_MAN___S 16 +#define PHYA_DEMFRONT_0_NOISE_PWR_1_U__SNR_EST_MMSE_IS___M 0x00003F00 +#define PHYA_DEMFRONT_0_NOISE_PWR_1_U__SNR_EST_MMSE_IS___S 8 +#define PHYA_DEMFRONT_0_NOISE_PWR_1_U__VSRC_DEPTH___M 0x000000FF +#define PHYA_DEMFRONT_0_NOISE_PWR_1_U__VSRC_DEPTH___S 0 +#define PHYA_DEMFRONT_0_NOISE_PWR_1_U___M 0x0F3F3FFF +#define PHYA_DEMFRONT_0_NOISE_PWR_1_U___S 0 + +#define PHYA_DEMFRONT_0_USER_SPARE_3_L (0x00400670) +#define PHYA_DEMFRONT_0_USER_SPARE_3_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_USER_SPARE_3_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_USER_SPARE_3_L__RXTD_NOISEPWR_BTCF_WR_SPARE_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_USER_SPARE_3_L__RXTD_NOISEPWR_BTCF_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_USER_SPARE_3_L__RXTD_NOISEPWR_BTCF_WR_SPARE_0___S 0 +#define PHYA_DEMFRONT_0_USER_SPARE_3_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_USER_SPARE_3_L___S 0 + +#define PHYA_DEMFRONT_0_USER_SPARE_3_U (0x00400674) +#define PHYA_DEMFRONT_0_USER_SPARE_3_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_USER_SPARE_3_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_USER_SPARE_3_U__RXTD_NOISEPWR_BTCF_WR_SPARE_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_USER_SPARE_3_U__RXTD_NOISEPWR_BTCF_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_USER_SPARE_3_U__RXTD_NOISEPWR_BTCF_WR_SPARE_1___S 0 +#define PHYA_DEMFRONT_0_USER_SPARE_3_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_USER_SPARE_3_U___S 0 + +#define PHYA_DEMFRONT_0_SCSR_CHE0_L (0x00400678) +#define PHYA_DEMFRONT_0_SCSR_CHE0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_CHE0_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SCSR_CHE0_L__CSD_VALUE_0___POR 0x000 +#define PHYA_DEMFRONT_0_SCSR_CHE0_L__CSD_VALUE_0___M 0x000001FF +#define PHYA_DEMFRONT_0_SCSR_CHE0_L__CSD_VALUE_0___S 0 +#define PHYA_DEMFRONT_0_SCSR_CHE0_L___M 0x000001FF +#define PHYA_DEMFRONT_0_SCSR_CHE0_L___S 0 + +#define PHYA_DEMFRONT_0_SCSR_CHE1_L (0x00400680) +#define PHYA_DEMFRONT_0_SCSR_CHE1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_CHE1_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SCSR_CHE1_L__CSD_VALUE_1___POR 0x000 +#define PHYA_DEMFRONT_0_SCSR_CHE1_L__CSD_VALUE_1___M 0x000001FF +#define PHYA_DEMFRONT_0_SCSR_CHE1_L__CSD_VALUE_1___S 0 +#define PHYA_DEMFRONT_0_SCSR_CHE1_L___M 0x000001FF +#define PHYA_DEMFRONT_0_SCSR_CHE1_L___S 0 + +#define PHYA_DEMFRONT_0_SCSR_CHE2_L (0x00400688) +#define PHYA_DEMFRONT_0_SCSR_CHE2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_CHE2_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SCSR_CHE2_L__CSD_VALUE_2___POR 0x000 +#define PHYA_DEMFRONT_0_SCSR_CHE2_L__CSD_VALUE_2___M 0x000001FF +#define PHYA_DEMFRONT_0_SCSR_CHE2_L__CSD_VALUE_2___S 0 +#define PHYA_DEMFRONT_0_SCSR_CHE2_L___M 0x000001FF +#define PHYA_DEMFRONT_0_SCSR_CHE2_L___S 0 + +#define PHYA_DEMFRONT_0_SCSR_CHE3_L (0x00400690) +#define PHYA_DEMFRONT_0_SCSR_CHE3_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_CHE3_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SCSR_CHE3_L__CSD_VALUE_3___POR 0x000 +#define PHYA_DEMFRONT_0_SCSR_CHE3_L__CSD_VALUE_3___M 0x000001FF +#define PHYA_DEMFRONT_0_SCSR_CHE3_L__CSD_VALUE_3___S 0 +#define PHYA_DEMFRONT_0_SCSR_CHE3_L___M 0x000001FF +#define PHYA_DEMFRONT_0_SCSR_CHE3_L___S 0 + +#define PHYA_DEMFRONT_0_SCSR_CHE4_L (0x00400698) +#define PHYA_DEMFRONT_0_SCSR_CHE4_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_CHE4_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SCSR_CHE4_L__CSD_VALUE_4___POR 0x000 +#define PHYA_DEMFRONT_0_SCSR_CHE4_L__CSD_VALUE_4___M 0x000001FF +#define PHYA_DEMFRONT_0_SCSR_CHE4_L__CSD_VALUE_4___S 0 +#define PHYA_DEMFRONT_0_SCSR_CHE4_L___M 0x000001FF +#define PHYA_DEMFRONT_0_SCSR_CHE4_L___S 0 + +#define PHYA_DEMFRONT_0_SCSR_CHE5_L (0x004006A0) +#define PHYA_DEMFRONT_0_SCSR_CHE5_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_CHE5_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SCSR_CHE5_L__CSD_VALUE_5___POR 0x000 +#define PHYA_DEMFRONT_0_SCSR_CHE5_L__CSD_VALUE_5___M 0x000001FF +#define PHYA_DEMFRONT_0_SCSR_CHE5_L__CSD_VALUE_5___S 0 +#define PHYA_DEMFRONT_0_SCSR_CHE5_L___M 0x000001FF +#define PHYA_DEMFRONT_0_SCSR_CHE5_L___S 0 + +#define PHYA_DEMFRONT_0_SCSR_CHE6_L (0x004006A8) +#define PHYA_DEMFRONT_0_SCSR_CHE6_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_CHE6_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SCSR_CHE6_L__CSD_VALUE_6___POR 0x000 +#define PHYA_DEMFRONT_0_SCSR_CHE6_L__CSD_VALUE_6___M 0x000001FF +#define PHYA_DEMFRONT_0_SCSR_CHE6_L__CSD_VALUE_6___S 0 +#define PHYA_DEMFRONT_0_SCSR_CHE6_L___M 0x000001FF +#define PHYA_DEMFRONT_0_SCSR_CHE6_L___S 0 + +#define PHYA_DEMFRONT_0_SCSR_CHE7_L (0x004006B0) +#define PHYA_DEMFRONT_0_SCSR_CHE7_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_CHE7_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SCSR_CHE7_L__CSD_VALUE_7___POR 0x000 +#define PHYA_DEMFRONT_0_SCSR_CHE7_L__CSD_VALUE_7___M 0x000001FF +#define PHYA_DEMFRONT_0_SCSR_CHE7_L__CSD_VALUE_7___S 0 +#define PHYA_DEMFRONT_0_SCSR_CHE7_L___M 0x000001FF +#define PHYA_DEMFRONT_0_SCSR_CHE7_L___S 0 + +#define PHYA_DEMFRONT_0_SCSR_LLR_0_L (0x004006B8) +#define PHYA_DEMFRONT_0_SCSR_LLR_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_LLR_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SCSR_LLR_0_L__QAM4096_LLR_INV___POR 0x0 +#define PHYA_DEMFRONT_0_SCSR_LLR_0_L__QAM4096_LLR_INV___M 0x00000001 +#define PHYA_DEMFRONT_0_SCSR_LLR_0_L__QAM4096_LLR_INV___S 0 +#define PHYA_DEMFRONT_0_SCSR_LLR_0_L___M 0x00000001 +#define PHYA_DEMFRONT_0_SCSR_LLR_0_L___S 0 + +#define PHYA_DEMFRONT_0_SCSR_LLR_1_L (0x004006C0) +#define PHYA_DEMFRONT_0_SCSR_LLR_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_LLR_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SCSR_LLR_1_L__QAM4096_LLR_ORDER___POR 0x0 +#define PHYA_DEMFRONT_0_SCSR_LLR_1_L__QAM4096_LLR_ORDER___M 0x00000001 +#define PHYA_DEMFRONT_0_SCSR_LLR_1_L__QAM4096_LLR_ORDER___S 0 +#define PHYA_DEMFRONT_0_SCSR_LLR_1_L___M 0x00000001 +#define PHYA_DEMFRONT_0_SCSR_LLR_1_L___S 0 + +#define PHYA_DEMFRONT_0_SCSR_LLR_2_L (0x004006C8) +#define PHYA_DEMFRONT_0_SCSR_LLR_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_LLR_2_L___POR 0x00007F01 +#define PHYA_DEMFRONT_0_SCSR_LLR_2_L__PILOT_POLARITY_SEQ___POR 0x7F +#define PHYA_DEMFRONT_0_SCSR_LLR_2_L__EN_SEG_DUPLICATE_WR___POR 0x1 +#define PHYA_DEMFRONT_0_SCSR_LLR_2_L__PILOT_POLARITY_SEQ___M 0x0000FF00 +#define PHYA_DEMFRONT_0_SCSR_LLR_2_L__PILOT_POLARITY_SEQ___S 8 +#define PHYA_DEMFRONT_0_SCSR_LLR_2_L__EN_SEG_DUPLICATE_WR___M 0x00000001 +#define PHYA_DEMFRONT_0_SCSR_LLR_2_L__EN_SEG_DUPLICATE_WR___S 0 +#define PHYA_DEMFRONT_0_SCSR_LLR_2_L___M 0x0000FF01 +#define PHYA_DEMFRONT_0_SCSR_LLR_2_L___S 0 + +#define PHYA_DEMFRONT_0_SCSR_DLMU_L (0x004006D0) +#define PHYA_DEMFRONT_0_SCSR_DLMU_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_DLMU_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SCSR_DLMU_L__DLMU_SS_OFFSET___POR 0x0 +#define PHYA_DEMFRONT_0_SCSR_DLMU_L__DLMU_NSS_TOTAL___POR 0x0 +#define PHYA_DEMFRONT_0_SCSR_DLMU_L__DLMU_NSS_USER___POR 0x0 +#define PHYA_DEMFRONT_0_SCSR_DLMU_L__DLMU_USER_ID___POR 0x00 +#define PHYA_DEMFRONT_0_SCSR_DLMU_L__DLMU_SS_OFFSET___M 0x07000000 +#define PHYA_DEMFRONT_0_SCSR_DLMU_L__DLMU_SS_OFFSET___S 24 +#define PHYA_DEMFRONT_0_SCSR_DLMU_L__DLMU_NSS_TOTAL___M 0x000F0000 +#define PHYA_DEMFRONT_0_SCSR_DLMU_L__DLMU_NSS_TOTAL___S 16 +#define PHYA_DEMFRONT_0_SCSR_DLMU_L__DLMU_NSS_USER___M 0x00000F00 +#define PHYA_DEMFRONT_0_SCSR_DLMU_L__DLMU_NSS_USER___S 8 +#define PHYA_DEMFRONT_0_SCSR_DLMU_L__DLMU_USER_ID___M 0x0000003F +#define PHYA_DEMFRONT_0_SCSR_DLMU_L__DLMU_USER_ID___S 0 +#define PHYA_DEMFRONT_0_SCSR_DLMU_L___M 0x070F0F3F +#define PHYA_DEMFRONT_0_SCSR_DLMU_L___S 0 + +#define PHYA_DEMFRONT_0_SCSR_DLMU_U (0x004006D4) +#define PHYA_DEMFRONT_0_SCSR_DLMU_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_DLMU_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_SCSR_DLMU_U__CBF_DISABLE_TXBF___POR 0x0 +#define PHYA_DEMFRONT_0_SCSR_DLMU_U__DLMU_LDPC_LLR_SCALE___POR 0x0 +#define PHYA_DEMFRONT_0_SCSR_DLMU_U__DLMU_IS_QAM___POR 0x0 +#define PHYA_DEMFRONT_0_SCSR_DLMU_U__DLMU_IS_LDPC___POR 0x0 +#define PHYA_DEMFRONT_0_SCSR_DLMU_U__CBF_DISABLE_TXBF___M 0x03000000 +#define PHYA_DEMFRONT_0_SCSR_DLMU_U__CBF_DISABLE_TXBF___S 24 +#define PHYA_DEMFRONT_0_SCSR_DLMU_U__DLMU_LDPC_LLR_SCALE___M 0x00070000 +#define PHYA_DEMFRONT_0_SCSR_DLMU_U__DLMU_LDPC_LLR_SCALE___S 16 +#define PHYA_DEMFRONT_0_SCSR_DLMU_U__DLMU_IS_QAM___M 0x00000700 +#define PHYA_DEMFRONT_0_SCSR_DLMU_U__DLMU_IS_QAM___S 8 +#define PHYA_DEMFRONT_0_SCSR_DLMU_U__DLMU_IS_LDPC___M 0x00000001 +#define PHYA_DEMFRONT_0_SCSR_DLMU_U__DLMU_IS_LDPC___S 0 +#define PHYA_DEMFRONT_0_SCSR_DLMU_U___M 0x03070701 +#define PHYA_DEMFRONT_0_SCSR_DLMU_U___S 0 + +#define PHYA_DEMFRONT_0_CBFG_CFG_0_L (0x004006D8) +#define PHYA_DEMFRONT_0_CBFG_CFG_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CBFG_CFG_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_CBFG_CFG_0_L__CBF_NG___POR 0x0 +#define PHYA_DEMFRONT_0_CBFG_CFG_0_L__CBF_PKB___POR 0x0 +#define PHYA_DEMFRONT_0_CBFG_CFG_0_L__CBF_PKT___POR 0x0 +#define PHYA_DEMFRONT_0_CBFG_CFG_0_L__CBF_CVMEM_SEL___POR 0x0 +#define PHYA_DEMFRONT_0_CBFG_CFG_0_L__CBF_NG___M 0x07000000 +#define PHYA_DEMFRONT_0_CBFG_CFG_0_L__CBF_NG___S 24 +#define PHYA_DEMFRONT_0_CBFG_CFG_0_L__CBF_PKB___M 0x00030000 +#define PHYA_DEMFRONT_0_CBFG_CFG_0_L__CBF_PKB___S 16 +#define PHYA_DEMFRONT_0_CBFG_CFG_0_L__CBF_PKT___M 0x00000300 +#define PHYA_DEMFRONT_0_CBFG_CFG_0_L__CBF_PKT___S 8 +#define PHYA_DEMFRONT_0_CBFG_CFG_0_L__CBF_CVMEM_SEL___M 0x00000001 +#define PHYA_DEMFRONT_0_CBFG_CFG_0_L__CBF_CVMEM_SEL___S 0 +#define PHYA_DEMFRONT_0_CBFG_CFG_0_L___M 0x07030301 +#define PHYA_DEMFRONT_0_CBFG_CFG_0_L___S 0 + +#define PHYA_DEMFRONT_0_CBFG_CFG_0_U (0x004006DC) +#define PHYA_DEMFRONT_0_CBFG_CFG_0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CBFG_CFG_0_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_CBFG_CFG_0_U__CBF_NC___POR 0x0 +#define PHYA_DEMFRONT_0_CBFG_CFG_0_U__CBF_NR___POR 0x0 +#define PHYA_DEMFRONT_0_CBFG_CFG_0_U__CBF_MU___POR 0x0 +#define PHYA_DEMFRONT_0_CBFG_CFG_0_U__CBF_CB___POR 0x0 +#define PHYA_DEMFRONT_0_CBFG_CFG_0_U__CBF_NC___M 0x07000000 +#define PHYA_DEMFRONT_0_CBFG_CFG_0_U__CBF_NC___S 24 +#define PHYA_DEMFRONT_0_CBFG_CFG_0_U__CBF_NR___M 0x00070000 +#define PHYA_DEMFRONT_0_CBFG_CFG_0_U__CBF_NR___S 16 +#define PHYA_DEMFRONT_0_CBFG_CFG_0_U__CBF_MU___M 0x00000100 +#define PHYA_DEMFRONT_0_CBFG_CFG_0_U__CBF_MU___S 8 +#define PHYA_DEMFRONT_0_CBFG_CFG_0_U__CBF_CB___M 0x00000001 +#define PHYA_DEMFRONT_0_CBFG_CFG_0_U__CBF_CB___S 0 +#define PHYA_DEMFRONT_0_CBFG_CFG_0_U___M 0x07070101 +#define PHYA_DEMFRONT_0_CBFG_CFG_0_U___S 0 + +#define PHYA_DEMFRONT_0_CBFG_CFG_1_L (0x004006E0) +#define PHYA_DEMFRONT_0_CBFG_CFG_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CBFG_CFG_1_L___POR 0x000A0000 +#define PHYA_DEMFRONT_0_CBFG_CFG_1_L__CBF_MAX_STREAM_SNR_CAP___POR 0x00 +#define PHYA_DEMFRONT_0_CBFG_CFG_1_L__CBF_SNR_RX1_BIAS___POR 0xA +#define PHYA_DEMFRONT_0_CBFG_CFG_1_L__CBF_RU_NUM___POR 0x00 +#define PHYA_DEMFRONT_0_CBFG_CFG_1_L__CBF_START_RU_IDX___POR 0x00 +#define PHYA_DEMFRONT_0_CBFG_CFG_1_L__CBF_MAX_STREAM_SNR_CAP___M 0x3F000000 +#define PHYA_DEMFRONT_0_CBFG_CFG_1_L__CBF_MAX_STREAM_SNR_CAP___S 24 +#define PHYA_DEMFRONT_0_CBFG_CFG_1_L__CBF_SNR_RX1_BIAS___M 0x000F0000 +#define PHYA_DEMFRONT_0_CBFG_CFG_1_L__CBF_SNR_RX1_BIAS___S 16 +#define PHYA_DEMFRONT_0_CBFG_CFG_1_L__CBF_RU_NUM___M 0x00003F00 +#define PHYA_DEMFRONT_0_CBFG_CFG_1_L__CBF_RU_NUM___S 8 +#define PHYA_DEMFRONT_0_CBFG_CFG_1_L__CBF_START_RU_IDX___M 0x0000003F +#define PHYA_DEMFRONT_0_CBFG_CFG_1_L__CBF_START_RU_IDX___S 0 +#define PHYA_DEMFRONT_0_CBFG_CFG_1_L___M 0x3F0F3F3F +#define PHYA_DEMFRONT_0_CBFG_CFG_1_L___S 0 + +#define PHYA_DEMFRONT_0_CBFG_CFG_1_U (0x004006E4) +#define PHYA_DEMFRONT_0_CBFG_CFG_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CBFG_CFG_1_U___POR 0x000C0000 +#define PHYA_DEMFRONT_0_CBFG_CFG_1_U__CBF_CNP_CTRL___POR 0x0C +#define PHYA_DEMFRONT_0_CBFG_CFG_1_U__CBF_INTER_CV_DSNR___POR 0x00 +#define PHYA_DEMFRONT_0_CBFG_CFG_1_U__CBF_INTER_ASNR_CV___POR 0x00 +#define PHYA_DEMFRONT_0_CBFG_CFG_1_U__CBF_CNP_CTRL___M 0x00FF0000 +#define PHYA_DEMFRONT_0_CBFG_CFG_1_U__CBF_CNP_CTRL___S 16 +#define PHYA_DEMFRONT_0_CBFG_CFG_1_U__CBF_INTER_CV_DSNR___M 0x0000FF00 +#define PHYA_DEMFRONT_0_CBFG_CFG_1_U__CBF_INTER_CV_DSNR___S 8 +#define PHYA_DEMFRONT_0_CBFG_CFG_1_U__CBF_INTER_ASNR_CV___M 0x000000FF +#define PHYA_DEMFRONT_0_CBFG_CFG_1_U__CBF_INTER_ASNR_CV___S 0 +#define PHYA_DEMFRONT_0_CBFG_CFG_1_U___M 0x00FFFFFF +#define PHYA_DEMFRONT_0_CBFG_CFG_1_U___S 0 + +#define PHYA_DEMFRONT_0_CBFG_CFG_2_L (0x004006E8) +#define PHYA_DEMFRONT_0_CBFG_CFG_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CBFG_CFG_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_CBFG_CFG_2_L__CBF_SNR_BIAS_1___POR 0x000 +#define PHYA_DEMFRONT_0_CBFG_CFG_2_L__CBF_SNR_BIAS_0___POR 0x000 +#define PHYA_DEMFRONT_0_CBFG_CFG_2_L__CBF_SNR_BIAS_1___M 0x03FF0000 +#define PHYA_DEMFRONT_0_CBFG_CFG_2_L__CBF_SNR_BIAS_1___S 16 +#define PHYA_DEMFRONT_0_CBFG_CFG_2_L__CBF_SNR_BIAS_0___M 0x000003FF +#define PHYA_DEMFRONT_0_CBFG_CFG_2_L__CBF_SNR_BIAS_0___S 0 +#define PHYA_DEMFRONT_0_CBFG_CFG_2_L___M 0x03FF03FF +#define PHYA_DEMFRONT_0_CBFG_CFG_2_L___S 0 + +#define PHYA_DEMFRONT_0_CBFG_CFG_3_L (0x004006F0) +#define PHYA_DEMFRONT_0_CBFG_CFG_3_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CBFG_CFG_3_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_CBFG_CFG_3_L__CBF_SEGMENT_SIZE___POR 0x0000 +#define PHYA_DEMFRONT_0_CBFG_CFG_3_L__SOUNDING_DIALOG_TOKEN___POR 0x00 +#define PHYA_DEMFRONT_0_CBFG_CFG_3_L__CBF_DISABLE_TXBF_THR___POR 0x00 +#define PHYA_DEMFRONT_0_CBFG_CFG_3_L__CBF_SEGMENT_SIZE___M 0xFFFF0000 +#define PHYA_DEMFRONT_0_CBFG_CFG_3_L__CBF_SEGMENT_SIZE___S 16 +#define PHYA_DEMFRONT_0_CBFG_CFG_3_L__SOUNDING_DIALOG_TOKEN___M 0x0000FF00 +#define PHYA_DEMFRONT_0_CBFG_CFG_3_L__SOUNDING_DIALOG_TOKEN___S 8 +#define PHYA_DEMFRONT_0_CBFG_CFG_3_L__CBF_DISABLE_TXBF_THR___M 0x000000FF +#define PHYA_DEMFRONT_0_CBFG_CFG_3_L__CBF_DISABLE_TXBF_THR___S 0 +#define PHYA_DEMFRONT_0_CBFG_CFG_3_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CBFG_CFG_3_L___S 0 + +#define PHYA_DEMFRONT_0_CBFG_CFG_3_U (0x004006F4) +#define PHYA_DEMFRONT_0_CBFG_CFG_3_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CBFG_CFG_3_U___POR 0x00000E00 +#define PHYA_DEMFRONT_0_CBFG_CFG_3_U__CBF_TOTAL_GAIN___POR 0x000 +#define PHYA_DEMFRONT_0_CBFG_CFG_3_U__CBF_SNR_ADC_SCALE___POR 0x0E +#define PHYA_DEMFRONT_0_CBFG_CFG_3_U__CBF_SEGMENT_NUM___POR 0x0 +#define PHYA_DEMFRONT_0_CBFG_CFG_3_U__CBF_TOTAL_GAIN___M 0x0FFF0000 +#define PHYA_DEMFRONT_0_CBFG_CFG_3_U__CBF_TOTAL_GAIN___S 16 +#define PHYA_DEMFRONT_0_CBFG_CFG_3_U__CBF_SNR_ADC_SCALE___M 0x00001F00 +#define PHYA_DEMFRONT_0_CBFG_CFG_3_U__CBF_SNR_ADC_SCALE___S 8 +#define PHYA_DEMFRONT_0_CBFG_CFG_3_U__CBF_SEGMENT_NUM___M 0x0000000F +#define PHYA_DEMFRONT_0_CBFG_CFG_3_U__CBF_SEGMENT_NUM___S 0 +#define PHYA_DEMFRONT_0_CBFG_CFG_3_U___M 0x0FFF1F0F +#define PHYA_DEMFRONT_0_CBFG_CFG_3_U___S 0 + +#define PHYA_DEMFRONT_0_CBFG_CFG_4_L (0x004006F8) +#define PHYA_DEMFRONT_0_CBFG_CFG_4_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CBFG_CFG_4_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_CBFG_CFG_4_L__CBF_CV_SEG0_END___POR 0x0000 +#define PHYA_DEMFRONT_0_CBFG_CFG_4_L__CBF_NOISE_PWR___POR 0x000 +#define PHYA_DEMFRONT_0_CBFG_CFG_4_L__CBF_CV_SEG0_END___M 0x1FFF0000 +#define PHYA_DEMFRONT_0_CBFG_CFG_4_L__CBF_CV_SEG0_END___S 16 +#define PHYA_DEMFRONT_0_CBFG_CFG_4_L__CBF_NOISE_PWR___M 0x00000FFF +#define PHYA_DEMFRONT_0_CBFG_CFG_4_L__CBF_NOISE_PWR___S 0 +#define PHYA_DEMFRONT_0_CBFG_CFG_4_L___M 0x1FFF0FFF +#define PHYA_DEMFRONT_0_CBFG_CFG_4_L___S 0 + +#define PHYA_DEMFRONT_0_CBFG_CFG_4_U (0x004006FC) +#define PHYA_DEMFRONT_0_CBFG_CFG_4_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CBFG_CFG_4_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_CBFG_CFG_4_U__CBF_CV_SEG1_START___POR 0x0000 +#define PHYA_DEMFRONT_0_CBFG_CFG_4_U__CBF_DSNR_SEG0_END___POR 0x0000 +#define PHYA_DEMFRONT_0_CBFG_CFG_4_U__CBF_CV_SEG1_START___M 0x1FFF0000 +#define PHYA_DEMFRONT_0_CBFG_CFG_4_U__CBF_CV_SEG1_START___S 16 +#define PHYA_DEMFRONT_0_CBFG_CFG_4_U__CBF_DSNR_SEG0_END___M 0x00001FFF +#define PHYA_DEMFRONT_0_CBFG_CFG_4_U__CBF_DSNR_SEG0_END___S 0 +#define PHYA_DEMFRONT_0_CBFG_CFG_4_U___M 0x1FFF1FFF +#define PHYA_DEMFRONT_0_CBFG_CFG_4_U___S 0 + +#define PHYA_DEMFRONT_0_CBFG_CFG_5_L (0x00400700) +#define PHYA_DEMFRONT_0_CBFG_CFG_5_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CBFG_CFG_5_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_CBFG_CFG_5_L__CBF_CV_SEG1_END___POR 0x0000 +#define PHYA_DEMFRONT_0_CBFG_CFG_5_L__CBF_DSNR_SEG1_START___POR 0x0000 +#define PHYA_DEMFRONT_0_CBFG_CFG_5_L__CBF_CV_SEG1_END___M 0x1FFF0000 +#define PHYA_DEMFRONT_0_CBFG_CFG_5_L__CBF_CV_SEG1_END___S 16 +#define PHYA_DEMFRONT_0_CBFG_CFG_5_L__CBF_DSNR_SEG1_START___M 0x00001FFF +#define PHYA_DEMFRONT_0_CBFG_CFG_5_L__CBF_DSNR_SEG1_START___S 0 +#define PHYA_DEMFRONT_0_CBFG_CFG_5_L___M 0x1FFF1FFF +#define PHYA_DEMFRONT_0_CBFG_CFG_5_L___S 0 + +#define PHYA_DEMFRONT_0_CBFG_CFG_5_U (0x00400704) +#define PHYA_DEMFRONT_0_CBFG_CFG_5_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CBFG_CFG_5_U___POR 0x00150000 +#define PHYA_DEMFRONT_0_CBFG_CFG_5_U__CBF_SPARE1___POR 0x00 +#define PHYA_DEMFRONT_0_CBFG_CFG_5_U__CBF_CATEGORY___POR 0x15 +#define PHYA_DEMFRONT_0_CBFG_CFG_5_U__CBF_DSNR_SEG0_START___POR 0x0000 +#define PHYA_DEMFRONT_0_CBFG_CFG_5_U__CBF_SPARE1___M 0xFF000000 +#define PHYA_DEMFRONT_0_CBFG_CFG_5_U__CBF_SPARE1___S 24 +#define PHYA_DEMFRONT_0_CBFG_CFG_5_U__CBF_CATEGORY___M 0x00FF0000 +#define PHYA_DEMFRONT_0_CBFG_CFG_5_U__CBF_CATEGORY___S 16 +#define PHYA_DEMFRONT_0_CBFG_CFG_5_U__CBF_DSNR_SEG0_START___M 0x00001FFF +#define PHYA_DEMFRONT_0_CBFG_CFG_5_U__CBF_DSNR_SEG0_START___S 0 +#define PHYA_DEMFRONT_0_CBFG_CFG_5_U___M 0xFFFF1FFF +#define PHYA_DEMFRONT_0_CBFG_CFG_5_U___S 0 + +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_L (0x00400708) +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_L___POR 0x00010000 +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_L__ENABLE_QRNP_MEM_WRITE___POR 0x0 +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_L__SINGLE_PHY___POR 0x1 +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_L__RX_CHAIN_MASK___POR 0x0 +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_L__CLKAXI_RATIO___POR 0x0 +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_L__ENABLE_QRNP_MEM_WRITE___M 0x01000000 +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_L__ENABLE_QRNP_MEM_WRITE___S 24 +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_L__SINGLE_PHY___M 0x00010000 +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_L__SINGLE_PHY___S 16 +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_L__RX_CHAIN_MASK___M 0x00000F00 +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_L__RX_CHAIN_MASK___S 8 +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_L__CLKAXI_RATIO___M 0x00000007 +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_L__CLKAXI_RATIO___S 0 +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_L___M 0x01010F07 +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_L___S 0 + +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_U (0x0040070C) +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_U___POR 0xFFFF0000 +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_U__ENABLE_CLKGATE___POR 0xFFFF +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_U__ENABLE_RXCVMEM_IDM_MODE___POR 0x0 +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_U__ENABLE_CLKGATE___M 0xFFFF0000 +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_U__ENABLE_CLKGATE___S 16 +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_U__ENABLE_RXCVMEM_IDM_MODE___M 0x00000100 +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_U__ENABLE_RXCVMEM_IDM_MODE___S 8 +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_U___M 0xFFFF0100 +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_0_U___S 8 + +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_1_L (0x00400710) +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_1_L___POR 0x00050100 +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_1_L__ML_QAM_THR___POR 0x5 +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_1_L__PILOT_MEM_EN___POR 0x1 +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_1_L__MSS_PHASE_CORR_MODE___POR 0x0 +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_1_L__ML_QAM_THR___M 0x00070000 +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_1_L__ML_QAM_THR___S 16 +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_1_L__PILOT_MEM_EN___M 0x00000100 +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_1_L__PILOT_MEM_EN___S 8 +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_1_L__MSS_PHASE_CORR_MODE___M 0x00000001 +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_1_L__MSS_PHASE_CORR_MODE___S 0 +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_1_L___M 0x00070101 +#define PHYA_DEMFRONT_0_DEMF_GEN_CONTROL_1_L___S 0 + +#define PHYA_DEMFRONT_0_SCSR_MRC_0_L (0x00400718) +#define PHYA_DEMFRONT_0_SCSR_MRC_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_MRC_0_L___POR 0x01070100 +#define PHYA_DEMFRONT_0_SCSR_MRC_0_L__QBPSK_BINW_SCALE_ENA___POR 0x1 +#define PHYA_DEMFRONT_0_SCSR_MRC_0_L__QBPSK_BINW_DISCARD_THR___POR 0x7 +#define PHYA_DEMFRONT_0_SCSR_MRC_0_L__FLAT_CH_THR_SMOOTH_MRC___POR 0x1 +#define PHYA_DEMFRONT_0_SCSR_MRC_0_L__FLAT_CH_THR_MRC___POR 0x0 +#define PHYA_DEMFRONT_0_SCSR_MRC_0_L__QBPSK_BINW_SCALE_ENA___M 0x01000000 +#define PHYA_DEMFRONT_0_SCSR_MRC_0_L__QBPSK_BINW_SCALE_ENA___S 24 +#define PHYA_DEMFRONT_0_SCSR_MRC_0_L__QBPSK_BINW_DISCARD_THR___M 0x00070000 +#define PHYA_DEMFRONT_0_SCSR_MRC_0_L__QBPSK_BINW_DISCARD_THR___S 16 +#define PHYA_DEMFRONT_0_SCSR_MRC_0_L__FLAT_CH_THR_SMOOTH_MRC___M 0x00000300 +#define PHYA_DEMFRONT_0_SCSR_MRC_0_L__FLAT_CH_THR_SMOOTH_MRC___S 8 +#define PHYA_DEMFRONT_0_SCSR_MRC_0_L__FLAT_CH_THR_MRC___M 0x00000003 +#define PHYA_DEMFRONT_0_SCSR_MRC_0_L__FLAT_CH_THR_MRC___S 0 +#define PHYA_DEMFRONT_0_SCSR_MRC_0_L___M 0x01070303 +#define PHYA_DEMFRONT_0_SCSR_MRC_0_L___S 0 + +#define PHYA_DEMFRONT_0_SCSR_MRC_0_U (0x0040071C) +#define PHYA_DEMFRONT_0_SCSR_MRC_0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_MRC_0_U___POR 0x02580107 +#define PHYA_DEMFRONT_0_SCSR_MRC_0_U__RLSIG_THR___POR 0x0258 +#define PHYA_DEMFRONT_0_SCSR_MRC_0_U__RLSIG_BINW_SCALE_ENA___POR 0x1 +#define PHYA_DEMFRONT_0_SCSR_MRC_0_U__RLSIG_BINW_DISCARD_THR___POR 0x7 +#define PHYA_DEMFRONT_0_SCSR_MRC_0_U__RLSIG_THR___M 0xFFFF0000 +#define PHYA_DEMFRONT_0_SCSR_MRC_0_U__RLSIG_THR___S 16 +#define PHYA_DEMFRONT_0_SCSR_MRC_0_U__RLSIG_BINW_SCALE_ENA___M 0x00000100 +#define PHYA_DEMFRONT_0_SCSR_MRC_0_U__RLSIG_BINW_SCALE_ENA___S 8 +#define PHYA_DEMFRONT_0_SCSR_MRC_0_U__RLSIG_BINW_DISCARD_THR___M 0x00000007 +#define PHYA_DEMFRONT_0_SCSR_MRC_0_U__RLSIG_BINW_DISCARD_THR___S 0 +#define PHYA_DEMFRONT_0_SCSR_MRC_0_U___M 0xFFFF0107 +#define PHYA_DEMFRONT_0_SCSR_MRC_0_U___S 0 + +#define PHYA_DEMFRONT_0_SCSR_MRC_1_L (0x00400720) +#define PHYA_DEMFRONT_0_SCSR_MRC_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_MRC_1_L___POR 0x00000001 +#define PHYA_DEMFRONT_0_SCSR_MRC_1_L__EN_BIN_WEIGHTING___POR 0x1 +#define PHYA_DEMFRONT_0_SCSR_MRC_1_L__EN_BIN_WEIGHTING___M 0x00000001 +#define PHYA_DEMFRONT_0_SCSR_MRC_1_L__EN_BIN_WEIGHTING___S 0 +#define PHYA_DEMFRONT_0_SCSR_MRC_1_L___M 0x00000001 +#define PHYA_DEMFRONT_0_SCSR_MRC_1_L___S 0 + +#define PHYA_DEMFRONT_0_SCSR_MRC_2_L (0x00400728) +#define PHYA_DEMFRONT_0_SCSR_MRC_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_MRC_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SCSR_MRC_2_L__MAX_BIN_IQ_EXP_1___POR 0x00 +#define PHYA_DEMFRONT_0_SCSR_MRC_2_L__MAX_BIN_IQ_EXP_0___POR 0x00 +#define PHYA_DEMFRONT_0_SCSR_MRC_2_L__MAX_BIN_IQ_EXP_1___M 0x00001F00 +#define PHYA_DEMFRONT_0_SCSR_MRC_2_L__MAX_BIN_IQ_EXP_1___S 8 +#define PHYA_DEMFRONT_0_SCSR_MRC_2_L__MAX_BIN_IQ_EXP_0___M 0x0000001F +#define PHYA_DEMFRONT_0_SCSR_MRC_2_L__MAX_BIN_IQ_EXP_0___S 0 +#define PHYA_DEMFRONT_0_SCSR_MRC_2_L___M 0x00001F1F +#define PHYA_DEMFRONT_0_SCSR_MRC_2_L___S 0 + +#define PHYA_DEMFRONT_0_SCSR_PTC_0_L (0x00400730) +#define PHYA_DEMFRONT_0_SCSR_PTC_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_PTC_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SCSR_PTC_0_L__ML_FLAT_CHAN_RATIO___POR 0x0 +#define PHYA_DEMFRONT_0_SCSR_PTC_0_L__MRC_SCALE_TABLE___POR 0x0 +#define PHYA_DEMFRONT_0_SCSR_PTC_0_L__LLR_SCALE_NONFLAT_MCS_THR___POR 0x0 +#define PHYA_DEMFRONT_0_SCSR_PTC_0_L__BYPASS_HW_SLOPE___POR 0x0 +#define PHYA_DEMFRONT_0_SCSR_PTC_0_L__ML_FLAT_CHAN_RATIO___M 0x07000000 +#define PHYA_DEMFRONT_0_SCSR_PTC_0_L__ML_FLAT_CHAN_RATIO___S 24 +#define PHYA_DEMFRONT_0_SCSR_PTC_0_L__MRC_SCALE_TABLE___M 0x00070000 +#define PHYA_DEMFRONT_0_SCSR_PTC_0_L__MRC_SCALE_TABLE___S 16 +#define PHYA_DEMFRONT_0_SCSR_PTC_0_L__LLR_SCALE_NONFLAT_MCS_THR___M 0x00000700 +#define PHYA_DEMFRONT_0_SCSR_PTC_0_L__LLR_SCALE_NONFLAT_MCS_THR___S 8 +#define PHYA_DEMFRONT_0_SCSR_PTC_0_L__BYPASS_HW_SLOPE___M 0x00000001 +#define PHYA_DEMFRONT_0_SCSR_PTC_0_L__BYPASS_HW_SLOPE___S 0 +#define PHYA_DEMFRONT_0_SCSR_PTC_0_L___M 0x07070701 +#define PHYA_DEMFRONT_0_SCSR_PTC_0_L___S 0 + +#define PHYA_DEMFRONT_0_SCSR_PTC_0_U (0x00400734) +#define PHYA_DEMFRONT_0_SCSR_PTC_0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_PTC_0_U___POR 0x000001FF +#define PHYA_DEMFRONT_0_SCSR_PTC_0_U__EN_SEGMENT_PTC___POR 0x0 +#define PHYA_DEMFRONT_0_SCSR_PTC_0_U__EN_MODE1P5___POR 0x0 +#define PHYA_DEMFRONT_0_SCSR_PTC_0_U__PCNT_STUCK_THR___POR 0x1FF +#define PHYA_DEMFRONT_0_SCSR_PTC_0_U__EN_SEGMENT_PTC___M 0x01000000 +#define PHYA_DEMFRONT_0_SCSR_PTC_0_U__EN_SEGMENT_PTC___S 24 +#define PHYA_DEMFRONT_0_SCSR_PTC_0_U__EN_MODE1P5___M 0x00010000 +#define PHYA_DEMFRONT_0_SCSR_PTC_0_U__EN_MODE1P5___S 16 +#define PHYA_DEMFRONT_0_SCSR_PTC_0_U__PCNT_STUCK_THR___M 0x000001FF +#define PHYA_DEMFRONT_0_SCSR_PTC_0_U__PCNT_STUCK_THR___S 0 +#define PHYA_DEMFRONT_0_SCSR_PTC_0_U___M 0x010101FF +#define PHYA_DEMFRONT_0_SCSR_PTC_0_U___S 0 + +#define PHYA_DEMFRONT_0_SCSR_PTC_1_L (0x00400738) +#define PHYA_DEMFRONT_0_SCSR_PTC_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_PTC_1_L___POR 0x03000001 +#define PHYA_DEMFRONT_0_SCSR_PTC_1_L__PTC_NON_HE_BETA___POR 0x3 +#define PHYA_DEMFRONT_0_SCSR_PTC_1_L__ENABLE_PTC_JQBPSK___POR 0x0 +#define PHYA_DEMFRONT_0_SCSR_PTC_1_L__DISABLE_CLK_AXI_GATING___POR 0x0 +#define PHYA_DEMFRONT_0_SCSR_PTC_1_L__EN_CHANNEL_CAPTURE___POR 0x1 +#define PHYA_DEMFRONT_0_SCSR_PTC_1_L__PTC_NON_HE_BETA___M 0x07000000 +#define PHYA_DEMFRONT_0_SCSR_PTC_1_L__PTC_NON_HE_BETA___S 24 +#define PHYA_DEMFRONT_0_SCSR_PTC_1_L__ENABLE_PTC_JQBPSK___M 0x00010000 +#define PHYA_DEMFRONT_0_SCSR_PTC_1_L__ENABLE_PTC_JQBPSK___S 16 +#define PHYA_DEMFRONT_0_SCSR_PTC_1_L__DISABLE_CLK_AXI_GATING___M 0x00000100 +#define PHYA_DEMFRONT_0_SCSR_PTC_1_L__DISABLE_CLK_AXI_GATING___S 8 +#define PHYA_DEMFRONT_0_SCSR_PTC_1_L__EN_CHANNEL_CAPTURE___M 0x00000001 +#define PHYA_DEMFRONT_0_SCSR_PTC_1_L__EN_CHANNEL_CAPTURE___S 0 +#define PHYA_DEMFRONT_0_SCSR_PTC_1_L___M 0x07010101 +#define PHYA_DEMFRONT_0_SCSR_PTC_1_L___S 0 + +#define PHYA_DEMFRONT_0_SCSR_PTC_1_U (0x0040073C) +#define PHYA_DEMFRONT_0_SCSR_PTC_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_PTC_1_U___POR 0x00070302 +#define PHYA_DEMFRONT_0_SCSR_PTC_1_U__ML_OFF_DIAG_THR_LLR___POR 0x007 +#define PHYA_DEMFRONT_0_SCSR_PTC_1_U__ML_DIAG_THR_LLR___POR 0x03 +#define PHYA_DEMFRONT_0_SCSR_PTC_1_U__PTC_HE_BETA___POR 0x2 +#define PHYA_DEMFRONT_0_SCSR_PTC_1_U__ML_OFF_DIAG_THR_LLR___M 0x03FF0000 +#define PHYA_DEMFRONT_0_SCSR_PTC_1_U__ML_OFF_DIAG_THR_LLR___S 16 +#define PHYA_DEMFRONT_0_SCSR_PTC_1_U__ML_DIAG_THR_LLR___M 0x00001F00 +#define PHYA_DEMFRONT_0_SCSR_PTC_1_U__ML_DIAG_THR_LLR___S 8 +#define PHYA_DEMFRONT_0_SCSR_PTC_1_U__PTC_HE_BETA___M 0x00000007 +#define PHYA_DEMFRONT_0_SCSR_PTC_1_U__PTC_HE_BETA___S 0 +#define PHYA_DEMFRONT_0_SCSR_PTC_1_U___M 0x03FF1F07 +#define PHYA_DEMFRONT_0_SCSR_PTC_1_U___S 0 + +#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_0_L (0x00400740) +#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_0_L__PM0_PILOT_MASK_IDX___POR 0x0000 +#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_0_L__PM0_PILOT_MASK_IDX___M 0x0000FFFF +#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_0_L__PM0_PILOT_MASK_IDX___S 0 +#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_0_L___M 0x0000FFFF +#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_0_L___S 0 + +#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_L (0x00400748) +#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_L__PM0_3_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_L__PM0_2_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_L__PM0_1_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_L__PM0_0_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_L__PM0_3_PMASK___M 0x1F000000 +#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_L__PM0_3_PMASK___S 24 +#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_L__PM0_2_PMASK___M 0x001F0000 +#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_L__PM0_2_PMASK___S 16 +#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_L__PM0_1_PMASK___M 0x00001F00 +#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_L__PM0_1_PMASK___S 8 +#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_L__PM0_0_PMASK___M 0x0000001F +#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_L__PM0_0_PMASK___S 0 +#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_L___M 0x1F1F1F1F +#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_L___S 0 + +#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_U (0x0040074C) +#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_U__PM0_4_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_U__PM0_4_PMASK___M 0x0000001F +#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_U__PM0_4_PMASK___S 0 +#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_U___M 0x0000001F +#define PHYA_DEMFRONT_0_PM0_PILOT_MASK_1_U___S 0 + +#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_0_L (0x00400750) +#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_0_L__PM1_PILOT_MASK_IDX___POR 0x0000 +#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_0_L__PM1_PILOT_MASK_IDX___M 0x0000FFFF +#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_0_L__PM1_PILOT_MASK_IDX___S 0 +#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_0_L___M 0x0000FFFF +#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_0_L___S 0 + +#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_L (0x00400758) +#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_L__PM1_3_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_L__PM1_2_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_L__PM1_1_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_L__PM1_0_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_L__PM1_3_PMASK___M 0x1F000000 +#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_L__PM1_3_PMASK___S 24 +#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_L__PM1_2_PMASK___M 0x001F0000 +#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_L__PM1_2_PMASK___S 16 +#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_L__PM1_1_PMASK___M 0x00001F00 +#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_L__PM1_1_PMASK___S 8 +#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_L__PM1_0_PMASK___M 0x0000001F +#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_L__PM1_0_PMASK___S 0 +#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_L___M 0x1F1F1F1F +#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_L___S 0 + +#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_U (0x0040075C) +#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_U__PM1_4_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_U__PM1_4_PMASK___M 0x0000001F +#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_U__PM1_4_PMASK___S 0 +#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_U___M 0x0000001F +#define PHYA_DEMFRONT_0_PM1_PILOT_MASK_1_U___S 0 + +#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_0_L (0x00400760) +#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_0_L__PM2_PILOT_MASK_IDX___POR 0x0000 +#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_0_L__PM2_PILOT_MASK_IDX___M 0x0000FFFF +#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_0_L__PM2_PILOT_MASK_IDX___S 0 +#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_0_L___M 0x0000FFFF +#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_0_L___S 0 + +#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_L (0x00400768) +#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_L__PM2_3_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_L__PM2_2_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_L__PM2_1_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_L__PM2_0_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_L__PM2_3_PMASK___M 0x1F000000 +#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_L__PM2_3_PMASK___S 24 +#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_L__PM2_2_PMASK___M 0x001F0000 +#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_L__PM2_2_PMASK___S 16 +#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_L__PM2_1_PMASK___M 0x00001F00 +#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_L__PM2_1_PMASK___S 8 +#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_L__PM2_0_PMASK___M 0x0000001F +#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_L__PM2_0_PMASK___S 0 +#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_L___M 0x1F1F1F1F +#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_L___S 0 + +#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_U (0x0040076C) +#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_U__PM2_4_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_U__PM2_4_PMASK___M 0x0000001F +#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_U__PM2_4_PMASK___S 0 +#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_U___M 0x0000001F +#define PHYA_DEMFRONT_0_PM2_PILOT_MASK_1_U___S 0 + +#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_0_L (0x00400770) +#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_0_L__PM3_PILOT_MASK_IDX___POR 0x0000 +#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_0_L__PM3_PILOT_MASK_IDX___M 0x0000FFFF +#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_0_L__PM3_PILOT_MASK_IDX___S 0 +#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_0_L___M 0x0000FFFF +#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_0_L___S 0 + +#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_L (0x00400778) +#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_L__PM3_3_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_L__PM3_2_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_L__PM3_1_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_L__PM3_0_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_L__PM3_3_PMASK___M 0x1F000000 +#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_L__PM3_3_PMASK___S 24 +#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_L__PM3_2_PMASK___M 0x001F0000 +#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_L__PM3_2_PMASK___S 16 +#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_L__PM3_1_PMASK___M 0x00001F00 +#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_L__PM3_1_PMASK___S 8 +#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_L__PM3_0_PMASK___M 0x0000001F +#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_L__PM3_0_PMASK___S 0 +#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_L___M 0x1F1F1F1F +#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_L___S 0 + +#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_U (0x0040077C) +#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_U__PM3_4_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_U__PM3_4_PMASK___M 0x0000001F +#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_U__PM3_4_PMASK___S 0 +#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_U___M 0x0000001F +#define PHYA_DEMFRONT_0_PM3_PILOT_MASK_1_U___S 0 + +#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_0_L (0x00400780) +#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_0_L__PM4_PILOT_MASK_IDX___POR 0x0000 +#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_0_L__PM4_PILOT_MASK_IDX___M 0x0000FFFF +#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_0_L__PM4_PILOT_MASK_IDX___S 0 +#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_0_L___M 0x0000FFFF +#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_0_L___S 0 + +#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_L (0x00400788) +#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_L__PM4_3_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_L__PM4_2_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_L__PM4_1_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_L__PM4_0_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_L__PM4_3_PMASK___M 0x1F000000 +#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_L__PM4_3_PMASK___S 24 +#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_L__PM4_2_PMASK___M 0x001F0000 +#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_L__PM4_2_PMASK___S 16 +#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_L__PM4_1_PMASK___M 0x00001F00 +#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_L__PM4_1_PMASK___S 8 +#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_L__PM4_0_PMASK___M 0x0000001F +#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_L__PM4_0_PMASK___S 0 +#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_L___M 0x1F1F1F1F +#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_L___S 0 + +#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_U (0x0040078C) +#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_U__PM4_4_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_U__PM4_4_PMASK___M 0x0000001F +#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_U__PM4_4_PMASK___S 0 +#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_U___M 0x0000001F +#define PHYA_DEMFRONT_0_PM4_PILOT_MASK_1_U___S 0 + +#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_0_L (0x00400790) +#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_0_L__PM5_PILOT_MASK_IDX___POR 0x0000 +#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_0_L__PM5_PILOT_MASK_IDX___M 0x0000FFFF +#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_0_L__PM5_PILOT_MASK_IDX___S 0 +#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_0_L___M 0x0000FFFF +#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_0_L___S 0 + +#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_L (0x00400798) +#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_L__PM5_3_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_L__PM5_2_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_L__PM5_1_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_L__PM5_0_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_L__PM5_3_PMASK___M 0x1F000000 +#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_L__PM5_3_PMASK___S 24 +#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_L__PM5_2_PMASK___M 0x001F0000 +#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_L__PM5_2_PMASK___S 16 +#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_L__PM5_1_PMASK___M 0x00001F00 +#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_L__PM5_1_PMASK___S 8 +#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_L__PM5_0_PMASK___M 0x0000001F +#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_L__PM5_0_PMASK___S 0 +#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_L___M 0x1F1F1F1F +#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_L___S 0 + +#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_U (0x0040079C) +#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_U__PM5_4_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_U__PM5_4_PMASK___M 0x0000001F +#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_U__PM5_4_PMASK___S 0 +#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_U___M 0x0000001F +#define PHYA_DEMFRONT_0_PM5_PILOT_MASK_1_U___S 0 + +#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_0_L (0x004007A0) +#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_0_L__PM6_PILOT_MASK_IDX___POR 0x0000 +#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_0_L__PM6_PILOT_MASK_IDX___M 0x0000FFFF +#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_0_L__PM6_PILOT_MASK_IDX___S 0 +#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_0_L___M 0x0000FFFF +#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_0_L___S 0 + +#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_L (0x004007A8) +#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_L__PM6_3_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_L__PM6_2_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_L__PM6_1_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_L__PM6_0_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_L__PM6_3_PMASK___M 0x1F000000 +#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_L__PM6_3_PMASK___S 24 +#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_L__PM6_2_PMASK___M 0x001F0000 +#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_L__PM6_2_PMASK___S 16 +#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_L__PM6_1_PMASK___M 0x00001F00 +#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_L__PM6_1_PMASK___S 8 +#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_L__PM6_0_PMASK___M 0x0000001F +#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_L__PM6_0_PMASK___S 0 +#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_L___M 0x1F1F1F1F +#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_L___S 0 + +#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_U (0x004007AC) +#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_U__PM6_4_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_U__PM6_4_PMASK___M 0x0000001F +#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_U__PM6_4_PMASK___S 0 +#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_U___M 0x0000001F +#define PHYA_DEMFRONT_0_PM6_PILOT_MASK_1_U___S 0 + +#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_0_L (0x004007B0) +#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_0_L__PM7_PILOT_MASK_IDX___POR 0x0000 +#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_0_L__PM7_PILOT_MASK_IDX___M 0x0000FFFF +#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_0_L__PM7_PILOT_MASK_IDX___S 0 +#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_0_L___M 0x0000FFFF +#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_0_L___S 0 + +#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_L (0x004007B8) +#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_L__PM7_3_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_L__PM7_2_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_L__PM7_1_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_L__PM7_0_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_L__PM7_3_PMASK___M 0x1F000000 +#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_L__PM7_3_PMASK___S 24 +#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_L__PM7_2_PMASK___M 0x001F0000 +#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_L__PM7_2_PMASK___S 16 +#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_L__PM7_1_PMASK___M 0x00001F00 +#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_L__PM7_1_PMASK___S 8 +#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_L__PM7_0_PMASK___M 0x0000001F +#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_L__PM7_0_PMASK___S 0 +#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_L___M 0x1F1F1F1F +#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_L___S 0 + +#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_U (0x004007BC) +#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_U__PM7_4_PMASK___POR 0x00 +#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_U__PM7_4_PMASK___M 0x0000001F +#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_U__PM7_4_PMASK___S 0 +#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_U___M 0x0000001F +#define PHYA_DEMFRONT_0_PM7_PILOT_MASK_1_U___S 0 + +#define PHYA_DEMFRONT_0_PTC_CONTROL_L (0x004007C0) +#define PHYA_DEMFRONT_0_PTC_CONTROL_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PTC_CONTROL_L___POR 0x00044E05 +#define PHYA_DEMFRONT_0_PTC_CONTROL_L__DELTA_SLOPE_COEF_EXP___POR 0x004 +#define PHYA_DEMFRONT_0_PTC_CONTROL_L__DELTA_SLOPE_COEF_MAN___POR 0x4E05 +#define PHYA_DEMFRONT_0_PTC_CONTROL_L__DELTA_SLOPE_COEF_EXP___M 0x03FF0000 +#define PHYA_DEMFRONT_0_PTC_CONTROL_L__DELTA_SLOPE_COEF_EXP___S 16 +#define PHYA_DEMFRONT_0_PTC_CONTROL_L__DELTA_SLOPE_COEF_MAN___M 0x00007FFF +#define PHYA_DEMFRONT_0_PTC_CONTROL_L__DELTA_SLOPE_COEF_MAN___S 0 +#define PHYA_DEMFRONT_0_PTC_CONTROL_L___M 0x03FF7FFF +#define PHYA_DEMFRONT_0_PTC_CONTROL_L___S 0 + +#define PHYA_DEMFRONT_0_SCSR_QRE_0_L (0x004007C8) +#define PHYA_DEMFRONT_0_SCSR_QRE_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_QRE_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SCSR_QRE_0_L__ML_DIAG_THR1___POR 0x0 +#define PHYA_DEMFRONT_0_SCSR_QRE_0_L__ML_DIAG_THR1___M 0x0000000F +#define PHYA_DEMFRONT_0_SCSR_QRE_0_L__ML_DIAG_THR1___S 0 +#define PHYA_DEMFRONT_0_SCSR_QRE_0_L___M 0x0000000F +#define PHYA_DEMFRONT_0_SCSR_QRE_0_L___S 0 + +#define PHYA_DEMFRONT_0_SCSR_QRE_1_L (0x004007D0) +#define PHYA_DEMFRONT_0_SCSR_QRE_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_QRE_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SCSR_QRE_1_L__ML_DIAG_THR2___POR 0x0 +#define PHYA_DEMFRONT_0_SCSR_QRE_1_L__ML_DIAG_THR2___M 0x0000000F +#define PHYA_DEMFRONT_0_SCSR_QRE_1_L__ML_DIAG_THR2___S 0 +#define PHYA_DEMFRONT_0_SCSR_QRE_1_L___M 0x0000000F +#define PHYA_DEMFRONT_0_SCSR_QRE_1_L___S 0 + +#define PHYA_DEMFRONT_0_SCSR_QRE_2_L (0x004007D8) +#define PHYA_DEMFRONT_0_SCSR_QRE_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_QRE_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SCSR_QRE_2_L__SIR_NORM_FACT___POR 0x000 +#define PHYA_DEMFRONT_0_SCSR_QRE_2_L__SIR_NORM_FACT___M 0x000001FF +#define PHYA_DEMFRONT_0_SCSR_QRE_2_L__SIR_NORM_FACT___S 0 +#define PHYA_DEMFRONT_0_SCSR_QRE_2_L___M 0x000001FF +#define PHYA_DEMFRONT_0_SCSR_QRE_2_L___S 0 + +#define PHYA_DEMFRONT_0_SCSR_QRE_3_L (0x004007E0) +#define PHYA_DEMFRONT_0_SCSR_QRE_3_L___RWC QCSR_REG_RO +#define PHYA_DEMFRONT_0_SCSR_QRE_3_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SCSR_QRE_3_L__SIR_DB_1___POR 0x00 +#define PHYA_DEMFRONT_0_SCSR_QRE_3_L__SIR_DB_0___POR 0x00 +#define PHYA_DEMFRONT_0_SCSR_QRE_3_L__SIR_DB_1___M 0x00003F00 +#define PHYA_DEMFRONT_0_SCSR_QRE_3_L__SIR_DB_1___S 8 +#define PHYA_DEMFRONT_0_SCSR_QRE_3_L__SIR_DB_0___M 0x0000003F +#define PHYA_DEMFRONT_0_SCSR_QRE_3_L__SIR_DB_0___S 0 +#define PHYA_DEMFRONT_0_SCSR_QRE_3_L___M 0x00003F3F +#define PHYA_DEMFRONT_0_SCSR_QRE_3_L___S 0 + +#define PHYA_DEMFRONT_0_CBFG_CFG1_L (0x00400830) +#define PHYA_DEMFRONT_0_CBFG_CFG1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CBFG_CFG1_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_CBFG_CFG1_L__CBFG_SYNC_RST___POR 0x0 +#define PHYA_DEMFRONT_0_CBFG_CFG1_L__USE_BFEE_SYNC_RST___POR 0x0 +#define PHYA_DEMFRONT_0_CBFG_CFG1_L__BFEE_SYNC_RST___POR 0x0 +#define PHYA_DEMFRONT_0_CBFG_CFG1_L__CBFG_SYNC_RST___M 0x00010000 +#define PHYA_DEMFRONT_0_CBFG_CFG1_L__CBFG_SYNC_RST___S 16 +#define PHYA_DEMFRONT_0_CBFG_CFG1_L__USE_BFEE_SYNC_RST___M 0x00000100 +#define PHYA_DEMFRONT_0_CBFG_CFG1_L__USE_BFEE_SYNC_RST___S 8 +#define PHYA_DEMFRONT_0_CBFG_CFG1_L__BFEE_SYNC_RST___M 0x00000001 +#define PHYA_DEMFRONT_0_CBFG_CFG1_L__BFEE_SYNC_RST___S 0 +#define PHYA_DEMFRONT_0_CBFG_CFG1_L___M 0x00010101 +#define PHYA_DEMFRONT_0_CBFG_CFG1_L___S 0 + +#define PHYA_DEMFRONT_0_DYNAMIC_ROOT_CLK_EN_L (0x00400840) +#define PHYA_DEMFRONT_0_DYNAMIC_ROOT_CLK_EN_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_DYNAMIC_ROOT_CLK_EN_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_DYNAMIC_ROOT_CLK_EN_L__ROOT_CLK_EN___POR 0x0 +#define PHYA_DEMFRONT_0_DYNAMIC_ROOT_CLK_EN_L__ROOT_CLK_EN___M 0x00000001 +#define PHYA_DEMFRONT_0_DYNAMIC_ROOT_CLK_EN_L__ROOT_CLK_EN___S 0 +#define PHYA_DEMFRONT_0_DYNAMIC_ROOT_CLK_EN_L___M 0x00000001 +#define PHYA_DEMFRONT_0_DYNAMIC_ROOT_CLK_EN_L___S 0 + +#define PHYA_DEMFRONT_0_ENA_DEMF_ASYNC_RST_L (0x00400848) +#define PHYA_DEMFRONT_0_ENA_DEMF_ASYNC_RST_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_ENA_DEMF_ASYNC_RST_L___POR 0x00000001 +#define PHYA_DEMFRONT_0_ENA_DEMF_ASYNC_RST_L__ENA_DEMF_ASYNC_RST___POR 0x1 +#define PHYA_DEMFRONT_0_ENA_DEMF_ASYNC_RST_L__ENA_DEMF_ASYNC_RST___M 0x00000001 +#define PHYA_DEMFRONT_0_ENA_DEMF_ASYNC_RST_L__ENA_DEMF_ASYNC_RST___S 0 +#define PHYA_DEMFRONT_0_ENA_DEMF_ASYNC_RST_L___M 0x00000001 +#define PHYA_DEMFRONT_0_ENA_DEMF_ASYNC_RST_L___S 0 + +#define PHYA_DEMFRONT_0_SCSR_CTRL_0_L (0x00400850) +#define PHYA_DEMFRONT_0_SCSR_CTRL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_CTRL_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SCSR_CTRL_0_L__AVG_1SS_OFDMA___POR 0x0 +#define PHYA_DEMFRONT_0_SCSR_CTRL_0_L__LISTEN_CHAIN___POR 0x0 +#define PHYA_DEMFRONT_0_SCSR_CTRL_0_L__SKIP_LLTF1_CHE___POR 0x0 +#define PHYA_DEMFRONT_0_SCSR_CTRL_0_L__ENABLE_ONE_CHAIN_SEARCH___POR 0x0 +#define PHYA_DEMFRONT_0_SCSR_CTRL_0_L__AVG_1SS_OFDMA___M 0x01000000 +#define PHYA_DEMFRONT_0_SCSR_CTRL_0_L__AVG_1SS_OFDMA___S 24 +#define PHYA_DEMFRONT_0_SCSR_CTRL_0_L__LISTEN_CHAIN___M 0x00010000 +#define PHYA_DEMFRONT_0_SCSR_CTRL_0_L__LISTEN_CHAIN___S 16 +#define PHYA_DEMFRONT_0_SCSR_CTRL_0_L__SKIP_LLTF1_CHE___M 0x00000100 +#define PHYA_DEMFRONT_0_SCSR_CTRL_0_L__SKIP_LLTF1_CHE___S 8 +#define PHYA_DEMFRONT_0_SCSR_CTRL_0_L__ENABLE_ONE_CHAIN_SEARCH___M 0x00000001 +#define PHYA_DEMFRONT_0_SCSR_CTRL_0_L__ENABLE_ONE_CHAIN_SEARCH___S 0 +#define PHYA_DEMFRONT_0_SCSR_CTRL_0_L___M 0x01010101 +#define PHYA_DEMFRONT_0_SCSR_CTRL_0_L___S 0 + +#define PHYA_DEMFRONT_0_SCSR_CTRL_0_U (0x00400854) +#define PHYA_DEMFRONT_0_SCSR_CTRL_0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_CTRL_0_U___POR 0x00010100 +#define PHYA_DEMFRONT_0_SCSR_CTRL_0_U__PTC_SYM_IDX_TO_SWITCH_BETA___POR 0x0 +#define PHYA_DEMFRONT_0_SCSR_CTRL_0_U__DISABLE_DF_PTC_MCS1_QPSK_LDPC___POR 0x1 +#define PHYA_DEMFRONT_0_SCSR_CTRL_0_U__DISABLE_DF_PTC_QPSK___POR 0x1 +#define PHYA_DEMFRONT_0_SCSR_CTRL_0_U__PTC_SYM_IDX_TO_SWITCH_BETA___M 0x03000000 +#define PHYA_DEMFRONT_0_SCSR_CTRL_0_U__PTC_SYM_IDX_TO_SWITCH_BETA___S 24 +#define PHYA_DEMFRONT_0_SCSR_CTRL_0_U__DISABLE_DF_PTC_MCS1_QPSK_LDPC___M 0x00010000 +#define PHYA_DEMFRONT_0_SCSR_CTRL_0_U__DISABLE_DF_PTC_MCS1_QPSK_LDPC___S 16 +#define PHYA_DEMFRONT_0_SCSR_CTRL_0_U__DISABLE_DF_PTC_QPSK___M 0x00000100 +#define PHYA_DEMFRONT_0_SCSR_CTRL_0_U__DISABLE_DF_PTC_QPSK___S 8 +#define PHYA_DEMFRONT_0_SCSR_CTRL_0_U___M 0x03010100 +#define PHYA_DEMFRONT_0_SCSR_CTRL_0_U___S 8 + +#define PHYA_DEMFRONT_0_SCSR_CTRL_1_L (0x00400858) +#define PHYA_DEMFRONT_0_SCSR_CTRL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_CTRL_1_L___POR 0x01010202 +#define PHYA_DEMFRONT_0_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_3___POR 0x1 +#define PHYA_DEMFRONT_0_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_2___POR 0x1 +#define PHYA_DEMFRONT_0_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_1___POR 0x2 +#define PHYA_DEMFRONT_0_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_0___POR 0x2 +#define PHYA_DEMFRONT_0_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_3___M 0x07000000 +#define PHYA_DEMFRONT_0_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_3___S 24 +#define PHYA_DEMFRONT_0_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_2___M 0x00070000 +#define PHYA_DEMFRONT_0_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_2___S 16 +#define PHYA_DEMFRONT_0_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_1___M 0x00000700 +#define PHYA_DEMFRONT_0_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_1___S 8 +#define PHYA_DEMFRONT_0_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_0___M 0x00000007 +#define PHYA_DEMFRONT_0_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_0___S 0 +#define PHYA_DEMFRONT_0_SCSR_CTRL_1_L___M 0x07070707 +#define PHYA_DEMFRONT_0_SCSR_CTRL_1_L___S 0 + +#define PHYA_DEMFRONT_0_SCSR_CTRL_1_U (0x0040085C) +#define PHYA_DEMFRONT_0_SCSR_CTRL_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_CTRL_1_U___POR 0x02010101 +#define PHYA_DEMFRONT_0_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_7___POR 0x2 +#define PHYA_DEMFRONT_0_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_6___POR 0x1 +#define PHYA_DEMFRONT_0_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_5___POR 0x1 +#define PHYA_DEMFRONT_0_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_4___POR 0x1 +#define PHYA_DEMFRONT_0_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_7___M 0x07000000 +#define PHYA_DEMFRONT_0_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_7___S 24 +#define PHYA_DEMFRONT_0_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_6___M 0x00070000 +#define PHYA_DEMFRONT_0_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_6___S 16 +#define PHYA_DEMFRONT_0_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_5___M 0x00000700 +#define PHYA_DEMFRONT_0_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_5___S 8 +#define PHYA_DEMFRONT_0_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_4___M 0x00000007 +#define PHYA_DEMFRONT_0_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_4___S 0 +#define PHYA_DEMFRONT_0_SCSR_CTRL_1_U___M 0x07070707 +#define PHYA_DEMFRONT_0_SCSR_CTRL_1_U___S 0 + +#define PHYA_DEMFRONT_0_SCSR_CTRL_2_L (0x00400860) +#define PHYA_DEMFRONT_0_SCSR_CTRL_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_CTRL_2_L___POR 0x02020303 +#define PHYA_DEMFRONT_0_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_3___POR 0x2 +#define PHYA_DEMFRONT_0_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_2___POR 0x2 +#define PHYA_DEMFRONT_0_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_1___POR 0x3 +#define PHYA_DEMFRONT_0_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_0___POR 0x3 +#define PHYA_DEMFRONT_0_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_3___M 0x07000000 +#define PHYA_DEMFRONT_0_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_3___S 24 +#define PHYA_DEMFRONT_0_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_2___M 0x00070000 +#define PHYA_DEMFRONT_0_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_2___S 16 +#define PHYA_DEMFRONT_0_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_1___M 0x00000700 +#define PHYA_DEMFRONT_0_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_1___S 8 +#define PHYA_DEMFRONT_0_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_0___M 0x00000007 +#define PHYA_DEMFRONT_0_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_0___S 0 +#define PHYA_DEMFRONT_0_SCSR_CTRL_2_L___M 0x07070707 +#define PHYA_DEMFRONT_0_SCSR_CTRL_2_L___S 0 + +#define PHYA_DEMFRONT_0_SCSR_CTRL_2_U (0x00400864) +#define PHYA_DEMFRONT_0_SCSR_CTRL_2_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_CTRL_2_U___POR 0x03010102 +#define PHYA_DEMFRONT_0_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_7___POR 0x3 +#define PHYA_DEMFRONT_0_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_6___POR 0x1 +#define PHYA_DEMFRONT_0_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_5___POR 0x1 +#define PHYA_DEMFRONT_0_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_4___POR 0x2 +#define PHYA_DEMFRONT_0_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_7___M 0x07000000 +#define PHYA_DEMFRONT_0_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_7___S 24 +#define PHYA_DEMFRONT_0_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_6___M 0x00070000 +#define PHYA_DEMFRONT_0_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_6___S 16 +#define PHYA_DEMFRONT_0_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_5___M 0x00000700 +#define PHYA_DEMFRONT_0_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_5___S 8 +#define PHYA_DEMFRONT_0_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_4___M 0x00000007 +#define PHYA_DEMFRONT_0_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_4___S 0 +#define PHYA_DEMFRONT_0_SCSR_CTRL_2_U___M 0x07070707 +#define PHYA_DEMFRONT_0_SCSR_CTRL_2_U___S 0 + +#define PHYA_DEMFRONT_0_SCSR_CTRL_3_L (0x00400868) +#define PHYA_DEMFRONT_0_SCSR_CTRL_3_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_CTRL_3_L___POR 0x02020202 +#define PHYA_DEMFRONT_0_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_3___POR 0x2 +#define PHYA_DEMFRONT_0_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_2___POR 0x2 +#define PHYA_DEMFRONT_0_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_1___POR 0x2 +#define PHYA_DEMFRONT_0_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_0___POR 0x2 +#define PHYA_DEMFRONT_0_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_3___M 0x07000000 +#define PHYA_DEMFRONT_0_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_3___S 24 +#define PHYA_DEMFRONT_0_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_2___M 0x00070000 +#define PHYA_DEMFRONT_0_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_2___S 16 +#define PHYA_DEMFRONT_0_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_1___M 0x00000700 +#define PHYA_DEMFRONT_0_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_1___S 8 +#define PHYA_DEMFRONT_0_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_0___M 0x00000007 +#define PHYA_DEMFRONT_0_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_0___S 0 +#define PHYA_DEMFRONT_0_SCSR_CTRL_3_L___M 0x07070707 +#define PHYA_DEMFRONT_0_SCSR_CTRL_3_L___S 0 + +#define PHYA_DEMFRONT_0_SCSR_CTRL_3_U (0x0040086C) +#define PHYA_DEMFRONT_0_SCSR_CTRL_3_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_CTRL_3_U___POR 0x02010102 +#define PHYA_DEMFRONT_0_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_7___POR 0x2 +#define PHYA_DEMFRONT_0_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_6___POR 0x1 +#define PHYA_DEMFRONT_0_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_5___POR 0x1 +#define PHYA_DEMFRONT_0_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_4___POR 0x2 +#define PHYA_DEMFRONT_0_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_7___M 0x07000000 +#define PHYA_DEMFRONT_0_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_7___S 24 +#define PHYA_DEMFRONT_0_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_6___M 0x00070000 +#define PHYA_DEMFRONT_0_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_6___S 16 +#define PHYA_DEMFRONT_0_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_5___M 0x00000700 +#define PHYA_DEMFRONT_0_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_5___S 8 +#define PHYA_DEMFRONT_0_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_4___M 0x00000007 +#define PHYA_DEMFRONT_0_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_4___S 0 +#define PHYA_DEMFRONT_0_SCSR_CTRL_3_U___M 0x07070707 +#define PHYA_DEMFRONT_0_SCSR_CTRL_3_U___S 0 + +#define PHYA_DEMFRONT_0_SCSR_CTRL_4_L (0x00400870) +#define PHYA_DEMFRONT_0_SCSR_CTRL_4_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_CTRL_4_L___POR 0x03030303 +#define PHYA_DEMFRONT_0_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_3___POR 0x3 +#define PHYA_DEMFRONT_0_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_2___POR 0x3 +#define PHYA_DEMFRONT_0_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_1___POR 0x3 +#define PHYA_DEMFRONT_0_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_0___POR 0x3 +#define PHYA_DEMFRONT_0_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_3___M 0x07000000 +#define PHYA_DEMFRONT_0_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_3___S 24 +#define PHYA_DEMFRONT_0_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_2___M 0x00070000 +#define PHYA_DEMFRONT_0_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_2___S 16 +#define PHYA_DEMFRONT_0_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_1___M 0x00000700 +#define PHYA_DEMFRONT_0_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_1___S 8 +#define PHYA_DEMFRONT_0_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_0___M 0x00000007 +#define PHYA_DEMFRONT_0_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_0___S 0 +#define PHYA_DEMFRONT_0_SCSR_CTRL_4_L___M 0x07070707 +#define PHYA_DEMFRONT_0_SCSR_CTRL_4_L___S 0 + +#define PHYA_DEMFRONT_0_SCSR_CTRL_4_U (0x00400874) +#define PHYA_DEMFRONT_0_SCSR_CTRL_4_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_CTRL_4_U___POR 0x03020203 +#define PHYA_DEMFRONT_0_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_7___POR 0x3 +#define PHYA_DEMFRONT_0_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_6___POR 0x2 +#define PHYA_DEMFRONT_0_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_5___POR 0x2 +#define PHYA_DEMFRONT_0_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_4___POR 0x3 +#define PHYA_DEMFRONT_0_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_7___M 0x07000000 +#define PHYA_DEMFRONT_0_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_7___S 24 +#define PHYA_DEMFRONT_0_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_6___M 0x00070000 +#define PHYA_DEMFRONT_0_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_6___S 16 +#define PHYA_DEMFRONT_0_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_5___M 0x00000700 +#define PHYA_DEMFRONT_0_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_5___S 8 +#define PHYA_DEMFRONT_0_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_4___M 0x00000007 +#define PHYA_DEMFRONT_0_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_4___S 0 +#define PHYA_DEMFRONT_0_SCSR_CTRL_4_U___M 0x07070707 +#define PHYA_DEMFRONT_0_SCSR_CTRL_4_U___S 0 + +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_L (0x00400DA0) +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_L___POR 0x0020000C +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_L__FREQ_SEL_ID_MIN_NUM_TONES___POR 0x020 +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_L__FREQ_SEL_ID_THRES___POR 0x0C +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_L__FREQ_SEL_ID_MIN_NUM_TONES___M 0x03FF0000 +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_L__FREQ_SEL_ID_MIN_NUM_TONES___S 16 +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_L__FREQ_SEL_ID_THRES___M 0x0000001F +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_L__FREQ_SEL_ID_THRES___S 0 +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_L___M 0x03FF001F +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_L___S 0 + +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_U (0x00400DA4) +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_U___POR 0x00070100 +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_U__SLOPE_EST_MIN_NUM_TONES___POR 0x007 +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_U__EN_SLOPE_ESTIMATION___POR 0x1 +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_U__SLOPE_EST_MIN_NUM_TONES___M 0x03FF0000 +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_U__SLOPE_EST_MIN_NUM_TONES___S 16 +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_U__EN_SLOPE_ESTIMATION___M 0x00000100 +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_U__EN_SLOPE_ESTIMATION___S 8 +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_U___M 0x03FF0100 +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_0_U___S 8 + +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_1_L (0x00400DA8) +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_1_L___POR 0x00000106 +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_1_L__SM_FILTER_SEL_OVERRIDE___POR 0x0 +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_1_L__EN_FLAT_CHANNEL_CHECK___POR 0x1 +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_1_L__IS_FLAT_CHANNEL_THR___POR 0x06 +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_1_L__SM_FILTER_SEL_OVERRIDE___M 0x00030000 +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_1_L__SM_FILTER_SEL_OVERRIDE___S 16 +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_1_L__EN_FLAT_CHANNEL_CHECK___M 0x00000100 +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_1_L__EN_FLAT_CHANNEL_CHECK___S 8 +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_1_L__IS_FLAT_CHANNEL_THR___M 0x0000007F +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_1_L__IS_FLAT_CHANNEL_THR___S 0 +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_1_L___M 0x0003017F +#define PHYA_DEMFRONT_0_SCSR_CHE_CONTROL_1_L___S 0 + +#define PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_L (0x00400DB0) +#define PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_L__PRI80_IS_UPPER80___POR 0x0 +#define PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_L__PHYDBG_SYM_CNT___POR 0x00 +#define PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_L__DEBUGMUX_CTRL_1___POR 0x00 +#define PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_L__DEBUGMUX_CTRL_0___POR 0x00 +#define PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_L__PRI80_IS_UPPER80___M 0x01000000 +#define PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_L__PRI80_IS_UPPER80___S 24 +#define PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_L__PHYDBG_SYM_CNT___M 0x00FF0000 +#define PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_L__PHYDBG_SYM_CNT___S 16 +#define PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_L__DEBUGMUX_CTRL_1___M 0x0000FF00 +#define PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_L__DEBUGMUX_CTRL_1___S 8 +#define PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_L__DEBUGMUX_CTRL_0___M 0x000000FF +#define PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_L__DEBUGMUX_CTRL_0___S 0 +#define PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_L___M 0x01FFFFFF +#define PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_L___S 0 + +#define PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_U (0x00400DB4) +#define PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_U___RWC QCSR_REG_RO +#define PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_U___POR 0x00000000 +#define PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_U__DEMF_HW_STATUS___POR 0x00000000 +#define PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_U__DEMF_HW_STATUS___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_U__DEMF_HW_STATUS___S 0 +#define PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_SCSR_CDEBUGCONTROL_U___S 0 + +#define PHYA_DEMFRONT_0_DC_MEM_L_n(n) (0x00400DB8+0x8*(n)) +#define PHYA_DEMFRONT_0_DC_MEM_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_DC_MEM_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_DC_MEM_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_DC_MEM_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_DC_MEM_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_DC_MEM_L_n__DC_MEM_1___POR 0x0000 +#define PHYA_DEMFRONT_0_DC_MEM_L_n__DC_MEM_0___POR 0x0000 +#define PHYA_DEMFRONT_0_DC_MEM_L_n__DC_MEM_1___M 0xFFFF0000 +#define PHYA_DEMFRONT_0_DC_MEM_L_n__DC_MEM_1___S 16 +#define PHYA_DEMFRONT_0_DC_MEM_L_n__DC_MEM_0___M 0x0000FFFF +#define PHYA_DEMFRONT_0_DC_MEM_L_n__DC_MEM_0___S 0 +#define PHYA_DEMFRONT_0_DC_MEM_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_DC_MEM_L_n___S 0 +#define PHYA_DEMFRONT_0_DC_MEM_L_0 (0x00400DB8) +#define PHYA_DEMFRONT_0_DC_MEM_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_DC_MEM_L_0__DC_MEM_1___M 0xFFFF0000 +#define PHYA_DEMFRONT_0_DC_MEM_L_0__DC_MEM_1___S 16 +#define PHYA_DEMFRONT_0_DC_MEM_L_0__DC_MEM_0___M 0x0000FFFF +#define PHYA_DEMFRONT_0_DC_MEM_L_0__DC_MEM_0___S 0 + +#define PHYA_DEMFRONT_0_DC_MEM_U_n(n) (0x00400DBC+0x8*(n)) +#define PHYA_DEMFRONT_0_DC_MEM_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_DC_MEM_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_DC_MEM_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_DC_MEM_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_DC_MEM_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_DC_MEM_U_n__DC_MEM_3___POR 0x0000 +#define PHYA_DEMFRONT_0_DC_MEM_U_n__DC_MEM_2___POR 0x0000 +#define PHYA_DEMFRONT_0_DC_MEM_U_n__DC_MEM_3___M 0xFFFF0000 +#define PHYA_DEMFRONT_0_DC_MEM_U_n__DC_MEM_3___S 16 +#define PHYA_DEMFRONT_0_DC_MEM_U_n__DC_MEM_2___M 0x0000FFFF +#define PHYA_DEMFRONT_0_DC_MEM_U_n__DC_MEM_2___S 0 +#define PHYA_DEMFRONT_0_DC_MEM_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_DC_MEM_U_n___S 0 +#define PHYA_DEMFRONT_0_DC_MEM_U_0 (0x00400DBC) +#define PHYA_DEMFRONT_0_DC_MEM_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_DC_MEM_U_0__DC_MEM_3___M 0xFFFF0000 +#define PHYA_DEMFRONT_0_DC_MEM_U_0__DC_MEM_3___S 16 +#define PHYA_DEMFRONT_0_DC_MEM_U_0__DC_MEM_2___M 0x0000FFFF +#define PHYA_DEMFRONT_0_DC_MEM_U_0__DC_MEM_2___S 0 + +#define PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_L_n(n) (0x004015B8+0x8*(n)) +#define PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_L_n__R_MEM_CHN0_63_0_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_L_n__R_MEM_CHN0_63_0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_L_n__R_MEM_CHN0_63_0_0___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_L_n___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_L_0 (0x004015B8) +#define PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_L_0__R_MEM_CHN0_63_0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_L_0__R_MEM_CHN0_63_0_0___S 0 + +#define PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_U_n(n) (0x004015BC+0x8*(n)) +#define PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_U_n__R_MEM_CHN0_63_0_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_U_n__R_MEM_CHN0_63_0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_U_n__R_MEM_CHN0_63_0_1___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_U_n___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_U_0 (0x004015BC) +#define PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_U_0__R_MEM_CHN0_63_0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN0_63_0_U_0__R_MEM_CHN0_63_0_1___S 0 + +#define PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_L_n(n) (0x004035B8+0x8*(n)) +#define PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_L_n__R_MEM_CHN0_127_64_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_L_n__R_MEM_CHN0_127_64_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_L_n__R_MEM_CHN0_127_64_0___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_L_n___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_L_0 (0x004035B8) +#define PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_L_0__R_MEM_CHN0_127_64_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_L_0__R_MEM_CHN0_127_64_0___S 0 + +#define PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_U_n(n) (0x004035BC+0x8*(n)) +#define PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_U_n__R_MEM_CHN0_127_64_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_U_n__R_MEM_CHN0_127_64_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_U_n__R_MEM_CHN0_127_64_1___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_U_n___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_U_0 (0x004035BC) +#define PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_U_0__R_MEM_CHN0_127_64_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN0_127_64_U_0__R_MEM_CHN0_127_64_1___S 0 + +#define PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_L_n(n) (0x004055B8+0x8*(n)) +#define PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_L_n__R_MEM_CHN0_191_128_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_L_n__R_MEM_CHN0_191_128_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_L_n__R_MEM_CHN0_191_128_0___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_L_n___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_L_0 (0x004055B8) +#define PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_L_0__R_MEM_CHN0_191_128_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_L_0__R_MEM_CHN0_191_128_0___S 0 + +#define PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_U_n(n) (0x004055BC+0x8*(n)) +#define PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_U_n__R_MEM_CHN0_191_128_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_U_n__R_MEM_CHN0_191_128_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_U_n__R_MEM_CHN0_191_128_1___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_U_n___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_U_0 (0x004055BC) +#define PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_U_0__R_MEM_CHN0_191_128_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN0_191_128_U_0__R_MEM_CHN0_191_128_1___S 0 + +#define PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_L_n(n) (0x004075B8+0x8*(n)) +#define PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_L_n__R_MEM_CHN0_255_192_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_L_n__R_MEM_CHN0_255_192_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_L_n__R_MEM_CHN0_255_192_0___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_L_n___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_L_0 (0x004075B8) +#define PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_L_0__R_MEM_CHN0_255_192_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_L_0__R_MEM_CHN0_255_192_0___S 0 + +#define PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_U_n(n) (0x004075BC+0x8*(n)) +#define PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_U_n__R_MEM_CHN0_255_192_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_U_n__R_MEM_CHN0_255_192_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_U_n__R_MEM_CHN0_255_192_1___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_U_n___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_U_0 (0x004075BC) +#define PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_U_0__R_MEM_CHN0_255_192_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN0_255_192_U_0__R_MEM_CHN0_255_192_1___S 0 + +#define PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_L_n(n) (0x004095B8+0x8*(n)) +#define PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_L_n__R_MEM_CHN1_63_0_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_L_n__R_MEM_CHN1_63_0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_L_n__R_MEM_CHN1_63_0_0___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_L_n___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_L_0 (0x004095B8) +#define PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_L_0__R_MEM_CHN1_63_0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_L_0__R_MEM_CHN1_63_0_0___S 0 + +#define PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_U_n(n) (0x004095BC+0x8*(n)) +#define PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_U_n__R_MEM_CHN1_63_0_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_U_n__R_MEM_CHN1_63_0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_U_n__R_MEM_CHN1_63_0_1___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_U_n___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_U_0 (0x004095BC) +#define PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_U_0__R_MEM_CHN1_63_0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN1_63_0_U_0__R_MEM_CHN1_63_0_1___S 0 + +#define PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_L_n(n) (0x0040B5B8+0x8*(n)) +#define PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_L_n__R_MEM_CHN1_127_64_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_L_n__R_MEM_CHN1_127_64_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_L_n__R_MEM_CHN1_127_64_0___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_L_n___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_L_0 (0x0040B5B8) +#define PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_L_0__R_MEM_CHN1_127_64_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_L_0__R_MEM_CHN1_127_64_0___S 0 + +#define PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_U_n(n) (0x0040B5BC+0x8*(n)) +#define PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_U_n__R_MEM_CHN1_127_64_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_U_n__R_MEM_CHN1_127_64_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_U_n__R_MEM_CHN1_127_64_1___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_U_n___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_U_0 (0x0040B5BC) +#define PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_U_0__R_MEM_CHN1_127_64_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN1_127_64_U_0__R_MEM_CHN1_127_64_1___S 0 + +#define PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_L_n(n) (0x0040D5B8+0x8*(n)) +#define PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_L_n__R_MEM_CHN1_191_128_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_L_n__R_MEM_CHN1_191_128_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_L_n__R_MEM_CHN1_191_128_0___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_L_n___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_L_0 (0x0040D5B8) +#define PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_L_0__R_MEM_CHN1_191_128_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_L_0__R_MEM_CHN1_191_128_0___S 0 + +#define PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_U_n(n) (0x0040D5BC+0x8*(n)) +#define PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_U_n__R_MEM_CHN1_191_128_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_U_n__R_MEM_CHN1_191_128_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_U_n__R_MEM_CHN1_191_128_1___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_U_n___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_U_0 (0x0040D5BC) +#define PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_U_0__R_MEM_CHN1_191_128_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN1_191_128_U_0__R_MEM_CHN1_191_128_1___S 0 + +#define PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_L_n(n) (0x0040F5B8+0x8*(n)) +#define PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_L_n__R_MEM_CHN1_255_192_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_L_n__R_MEM_CHN1_255_192_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_L_n__R_MEM_CHN1_255_192_0___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_L_n___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_L_0 (0x0040F5B8) +#define PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_L_0__R_MEM_CHN1_255_192_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_L_0__R_MEM_CHN1_255_192_0___S 0 + +#define PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_U_n(n) (0x0040F5BC+0x8*(n)) +#define PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_U_n__R_MEM_CHN1_255_192_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_U_n__R_MEM_CHN1_255_192_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_U_n__R_MEM_CHN1_255_192_1___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_U_n___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_U_0 (0x0040F5BC) +#define PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_U_0__R_MEM_CHN1_255_192_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN1_255_192_U_0__R_MEM_CHN1_255_192_1___S 0 + +#define PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_L_n(n) (0x004115B8+0x8*(n)) +#define PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_L_n__R_MEM_CHN2_63_0_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_L_n__R_MEM_CHN2_63_0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_L_n__R_MEM_CHN2_63_0_0___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_L_n___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_L_0 (0x004115B8) +#define PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_L_0__R_MEM_CHN2_63_0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_L_0__R_MEM_CHN2_63_0_0___S 0 + +#define PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_U_n(n) (0x004115BC+0x8*(n)) +#define PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_U_n__R_MEM_CHN2_63_0_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_U_n__R_MEM_CHN2_63_0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_U_n__R_MEM_CHN2_63_0_1___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_U_n___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_U_0 (0x004115BC) +#define PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_U_0__R_MEM_CHN2_63_0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN2_63_0_U_0__R_MEM_CHN2_63_0_1___S 0 + +#define PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_L_n(n) (0x004135B8+0x8*(n)) +#define PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_L_n__R_MEM_CHN2_127_64_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_L_n__R_MEM_CHN2_127_64_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_L_n__R_MEM_CHN2_127_64_0___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_L_n___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_L_0 (0x004135B8) +#define PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_L_0__R_MEM_CHN2_127_64_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_L_0__R_MEM_CHN2_127_64_0___S 0 + +#define PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_U_n(n) (0x004135BC+0x8*(n)) +#define PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_U_n__R_MEM_CHN2_127_64_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_U_n__R_MEM_CHN2_127_64_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_U_n__R_MEM_CHN2_127_64_1___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_U_n___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_U_0 (0x004135BC) +#define PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_U_0__R_MEM_CHN2_127_64_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN2_127_64_U_0__R_MEM_CHN2_127_64_1___S 0 + +#define PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_L_n(n) (0x004155B8+0x8*(n)) +#define PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_L_n__R_MEM_CHN2_191_128_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_L_n__R_MEM_CHN2_191_128_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_L_n__R_MEM_CHN2_191_128_0___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_L_n___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_L_0 (0x004155B8) +#define PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_L_0__R_MEM_CHN2_191_128_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_L_0__R_MEM_CHN2_191_128_0___S 0 + +#define PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_U_n(n) (0x004155BC+0x8*(n)) +#define PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_U_n__R_MEM_CHN2_191_128_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_U_n__R_MEM_CHN2_191_128_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_U_n__R_MEM_CHN2_191_128_1___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_U_n___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_U_0 (0x004155BC) +#define PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_U_0__R_MEM_CHN2_191_128_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN2_191_128_U_0__R_MEM_CHN2_191_128_1___S 0 + +#define PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_L_n(n) (0x004175B8+0x8*(n)) +#define PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_L_n__R_MEM_CHN2_255_192_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_L_n__R_MEM_CHN2_255_192_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_L_n__R_MEM_CHN2_255_192_0___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_L_n___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_L_0 (0x004175B8) +#define PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_L_0__R_MEM_CHN2_255_192_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_L_0__R_MEM_CHN2_255_192_0___S 0 + +#define PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_U_n(n) (0x004175BC+0x8*(n)) +#define PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_U_n__R_MEM_CHN2_255_192_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_U_n__R_MEM_CHN2_255_192_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_U_n__R_MEM_CHN2_255_192_1___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_U_n___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_U_0 (0x004175BC) +#define PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_U_0__R_MEM_CHN2_255_192_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN2_255_192_U_0__R_MEM_CHN2_255_192_1___S 0 + +#define PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_L_n(n) (0x004195B8+0x8*(n)) +#define PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_L_n__R_MEM_CHN3_63_0_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_L_n__R_MEM_CHN3_63_0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_L_n__R_MEM_CHN3_63_0_0___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_L_n___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_L_0 (0x004195B8) +#define PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_L_0__R_MEM_CHN3_63_0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_L_0__R_MEM_CHN3_63_0_0___S 0 + +#define PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_U_n(n) (0x004195BC+0x8*(n)) +#define PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_U_n__R_MEM_CHN3_63_0_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_U_n__R_MEM_CHN3_63_0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_U_n__R_MEM_CHN3_63_0_1___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_U_n___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_U_0 (0x004195BC) +#define PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_U_0__R_MEM_CHN3_63_0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN3_63_0_U_0__R_MEM_CHN3_63_0_1___S 0 + +#define PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_L_n(n) (0x0041B5B8+0x8*(n)) +#define PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_L_n__R_MEM_CHN3_127_64_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_L_n__R_MEM_CHN3_127_64_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_L_n__R_MEM_CHN3_127_64_0___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_L_n___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_L_0 (0x0041B5B8) +#define PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_L_0__R_MEM_CHN3_127_64_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_L_0__R_MEM_CHN3_127_64_0___S 0 + +#define PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_U_n(n) (0x0041B5BC+0x8*(n)) +#define PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_U_n__R_MEM_CHN3_127_64_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_U_n__R_MEM_CHN3_127_64_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_U_n__R_MEM_CHN3_127_64_1___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_U_n___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_U_0 (0x0041B5BC) +#define PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_U_0__R_MEM_CHN3_127_64_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN3_127_64_U_0__R_MEM_CHN3_127_64_1___S 0 + +#define PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_L_n(n) (0x0041D5B8+0x8*(n)) +#define PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_L_n__R_MEM_CHN3_191_128_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_L_n__R_MEM_CHN3_191_128_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_L_n__R_MEM_CHN3_191_128_0___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_L_n___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_L_0 (0x0041D5B8) +#define PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_L_0__R_MEM_CHN3_191_128_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_L_0__R_MEM_CHN3_191_128_0___S 0 + +#define PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_U_n(n) (0x0041D5BC+0x8*(n)) +#define PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_U_n__R_MEM_CHN3_191_128_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_U_n__R_MEM_CHN3_191_128_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_U_n__R_MEM_CHN3_191_128_1___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_U_n___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_U_0 (0x0041D5BC) +#define PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_U_0__R_MEM_CHN3_191_128_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN3_191_128_U_0__R_MEM_CHN3_191_128_1___S 0 + +#define PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_L_n(n) (0x0041F5B8+0x8*(n)) +#define PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_L_n__R_MEM_CHN3_255_192_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_L_n__R_MEM_CHN3_255_192_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_L_n__R_MEM_CHN3_255_192_0___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_L_n___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_L_0 (0x0041F5B8) +#define PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_L_0__R_MEM_CHN3_255_192_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_L_0__R_MEM_CHN3_255_192_0___S 0 + +#define PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_U_n(n) (0x0041F5BC+0x8*(n)) +#define PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_U_n__R_MEM_CHN3_255_192_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_U_n__R_MEM_CHN3_255_192_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_U_n__R_MEM_CHN3_255_192_1___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_U_n___S 0 +#define PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_U_0 (0x0041F5BC) +#define PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_U_0__R_MEM_CHN3_255_192_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_R_MEM_CHN3_255_192_U_0__R_MEM_CHN3_255_192_1___S 0 + +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_L_n(n) (0x004215B8+0x8*(n)) +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_L_n__Q_MEM_CHN0_63_0_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_L_n__Q_MEM_CHN0_63_0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_L_n__Q_MEM_CHN0_63_0_0___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_L_n___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_L_0 (0x004215B8) +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_L_0__Q_MEM_CHN0_63_0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_L_0__Q_MEM_CHN0_63_0_0___S 0 + +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_U_n(n) (0x004215BC+0x8*(n)) +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_U_n__Q_MEM_CHN0_63_0_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_U_n__Q_MEM_CHN0_63_0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_U_n__Q_MEM_CHN0_63_0_1___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_U_n___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_U_0 (0x004215BC) +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_U_0__Q_MEM_CHN0_63_0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_63_0_U_0__Q_MEM_CHN0_63_0_1___S 0 + +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_L_n(n) (0x004235B8+0x8*(n)) +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_L_n__Q_MEM_CHN0_127_64_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_L_n__Q_MEM_CHN0_127_64_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_L_n__Q_MEM_CHN0_127_64_0___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_L_n___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_L_0 (0x004235B8) +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_L_0__Q_MEM_CHN0_127_64_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_L_0__Q_MEM_CHN0_127_64_0___S 0 + +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_U_n(n) (0x004235BC+0x8*(n)) +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_U_n__Q_MEM_CHN0_127_64_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_U_n__Q_MEM_CHN0_127_64_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_U_n__Q_MEM_CHN0_127_64_1___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_U_n___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_U_0 (0x004235BC) +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_U_0__Q_MEM_CHN0_127_64_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_127_64_U_0__Q_MEM_CHN0_127_64_1___S 0 + +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_L_n(n) (0x004255B8+0x8*(n)) +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_L_n__Q_MEM_CHN0_191_128_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_L_n__Q_MEM_CHN0_191_128_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_L_n__Q_MEM_CHN0_191_128_0___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_L_n___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_L_0 (0x004255B8) +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_L_0__Q_MEM_CHN0_191_128_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_L_0__Q_MEM_CHN0_191_128_0___S 0 + +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_U_n(n) (0x004255BC+0x8*(n)) +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_U_n__Q_MEM_CHN0_191_128_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_U_n__Q_MEM_CHN0_191_128_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_U_n__Q_MEM_CHN0_191_128_1___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_U_n___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_U_0 (0x004255BC) +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_U_0__Q_MEM_CHN0_191_128_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN0_191_128_U_0__Q_MEM_CHN0_191_128_1___S 0 + +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_L_n(n) (0x004275B8+0x8*(n)) +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_L_n__Q_MEM_CHN1_63_0_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_L_n__Q_MEM_CHN1_63_0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_L_n__Q_MEM_CHN1_63_0_0___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_L_n___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_L_0 (0x004275B8) +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_L_0__Q_MEM_CHN1_63_0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_L_0__Q_MEM_CHN1_63_0_0___S 0 + +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_U_n(n) (0x004275BC+0x8*(n)) +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_U_n__Q_MEM_CHN1_63_0_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_U_n__Q_MEM_CHN1_63_0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_U_n__Q_MEM_CHN1_63_0_1___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_U_n___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_U_0 (0x004275BC) +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_U_0__Q_MEM_CHN1_63_0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_63_0_U_0__Q_MEM_CHN1_63_0_1___S 0 + +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_L_n(n) (0x004295B8+0x8*(n)) +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_L_n__Q_MEM_CHN1_127_64_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_L_n__Q_MEM_CHN1_127_64_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_L_n__Q_MEM_CHN1_127_64_0___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_L_n___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_L_0 (0x004295B8) +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_L_0__Q_MEM_CHN1_127_64_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_L_0__Q_MEM_CHN1_127_64_0___S 0 + +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_U_n(n) (0x004295BC+0x8*(n)) +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_U_n__Q_MEM_CHN1_127_64_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_U_n__Q_MEM_CHN1_127_64_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_U_n__Q_MEM_CHN1_127_64_1___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_U_n___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_U_0 (0x004295BC) +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_U_0__Q_MEM_CHN1_127_64_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_127_64_U_0__Q_MEM_CHN1_127_64_1___S 0 + +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_L_n(n) (0x0042B5B8+0x8*(n)) +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_L_n__Q_MEM_CHN1_191_128_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_L_n__Q_MEM_CHN1_191_128_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_L_n__Q_MEM_CHN1_191_128_0___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_L_n___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_L_0 (0x0042B5B8) +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_L_0__Q_MEM_CHN1_191_128_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_L_0__Q_MEM_CHN1_191_128_0___S 0 + +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_U_n(n) (0x0042B5BC+0x8*(n)) +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_U_n__Q_MEM_CHN1_191_128_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_U_n__Q_MEM_CHN1_191_128_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_U_n__Q_MEM_CHN1_191_128_1___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_U_n___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_U_0 (0x0042B5BC) +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_U_0__Q_MEM_CHN1_191_128_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN1_191_128_U_0__Q_MEM_CHN1_191_128_1___S 0 + +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_L_n(n) (0x0042D5B8+0x8*(n)) +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_L_n__Q_MEM_CHN2_63_0_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_L_n__Q_MEM_CHN2_63_0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_L_n__Q_MEM_CHN2_63_0_0___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_L_n___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_L_0 (0x0042D5B8) +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_L_0__Q_MEM_CHN2_63_0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_L_0__Q_MEM_CHN2_63_0_0___S 0 + +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_U_n(n) (0x0042D5BC+0x8*(n)) +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_U_n__Q_MEM_CHN2_63_0_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_U_n__Q_MEM_CHN2_63_0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_U_n__Q_MEM_CHN2_63_0_1___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_U_n___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_U_0 (0x0042D5BC) +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_U_0__Q_MEM_CHN2_63_0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_63_0_U_0__Q_MEM_CHN2_63_0_1___S 0 + +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_L_n(n) (0x0042F5B8+0x8*(n)) +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_L_n__Q_MEM_CHN2_127_64_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_L_n__Q_MEM_CHN2_127_64_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_L_n__Q_MEM_CHN2_127_64_0___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_L_n___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_L_0 (0x0042F5B8) +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_L_0__Q_MEM_CHN2_127_64_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_L_0__Q_MEM_CHN2_127_64_0___S 0 + +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_U_n(n) (0x0042F5BC+0x8*(n)) +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_U_n__Q_MEM_CHN2_127_64_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_U_n__Q_MEM_CHN2_127_64_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_U_n__Q_MEM_CHN2_127_64_1___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_U_n___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_U_0 (0x0042F5BC) +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_U_0__Q_MEM_CHN2_127_64_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_127_64_U_0__Q_MEM_CHN2_127_64_1___S 0 + +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_L_n(n) (0x004315B8+0x8*(n)) +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_L_n__Q_MEM_CHN2_191_128_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_L_n__Q_MEM_CHN2_191_128_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_L_n__Q_MEM_CHN2_191_128_0___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_L_n___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_L_0 (0x004315B8) +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_L_0__Q_MEM_CHN2_191_128_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_L_0__Q_MEM_CHN2_191_128_0___S 0 + +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_U_n(n) (0x004315BC+0x8*(n)) +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_U_n__Q_MEM_CHN2_191_128_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_U_n__Q_MEM_CHN2_191_128_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_U_n__Q_MEM_CHN2_191_128_1___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_U_n___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_U_0 (0x004315BC) +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_U_0__Q_MEM_CHN2_191_128_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN2_191_128_U_0__Q_MEM_CHN2_191_128_1___S 0 + +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_L_n(n) (0x004335B8+0x8*(n)) +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_L_n__Q_MEM_CHN3_63_0_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_L_n__Q_MEM_CHN3_63_0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_L_n__Q_MEM_CHN3_63_0_0___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_L_n___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_L_0 (0x004335B8) +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_L_0__Q_MEM_CHN3_63_0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_L_0__Q_MEM_CHN3_63_0_0___S 0 + +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_U_n(n) (0x004335BC+0x8*(n)) +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_U_n__Q_MEM_CHN3_63_0_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_U_n__Q_MEM_CHN3_63_0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_U_n__Q_MEM_CHN3_63_0_1___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_U_n___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_U_0 (0x004335BC) +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_U_0__Q_MEM_CHN3_63_0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_63_0_U_0__Q_MEM_CHN3_63_0_1___S 0 + +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_L_n(n) (0x004355B8+0x8*(n)) +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_L_n__Q_MEM_CHN3_127_64_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_L_n__Q_MEM_CHN3_127_64_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_L_n__Q_MEM_CHN3_127_64_0___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_L_n___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_L_0 (0x004355B8) +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_L_0__Q_MEM_CHN3_127_64_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_L_0__Q_MEM_CHN3_127_64_0___S 0 + +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_U_n(n) (0x004355BC+0x8*(n)) +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_U_n__Q_MEM_CHN3_127_64_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_U_n__Q_MEM_CHN3_127_64_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_U_n__Q_MEM_CHN3_127_64_1___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_U_n___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_U_0 (0x004355BC) +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_U_0__Q_MEM_CHN3_127_64_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_127_64_U_0__Q_MEM_CHN3_127_64_1___S 0 + +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_L_n(n) (0x004375B8+0x8*(n)) +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_L_n__Q_MEM_CHN3_191_128_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_L_n__Q_MEM_CHN3_191_128_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_L_n__Q_MEM_CHN3_191_128_0___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_L_n___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_L_0 (0x004375B8) +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_L_0__Q_MEM_CHN3_191_128_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_L_0__Q_MEM_CHN3_191_128_0___S 0 + +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_U_n(n) (0x004375BC+0x8*(n)) +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_U_n__Q_MEM_CHN3_191_128_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_U_n__Q_MEM_CHN3_191_128_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_U_n__Q_MEM_CHN3_191_128_1___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_U_n___S 0 +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_U_0 (0x004375BC) +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_U_0__Q_MEM_CHN3_191_128_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_Q_MEM_CHN3_191_128_U_0__Q_MEM_CHN3_191_128_1___S 0 + +#define PHYA_DEMFRONT_0_CV_IDM_RXMEM0_ADDR_L (0x004395D0) +#define PHYA_DEMFRONT_0_CV_IDM_RXMEM0_ADDR_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CV_IDM_RXMEM0_ADDR_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_IDM_RXMEM0_ADDR_L__CV_IDM_RXMEM0_ADDR___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_IDM_RXMEM0_ADDR_L__CV_IDM_RXMEM0_ADDR___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_IDM_RXMEM0_ADDR_L__CV_IDM_RXMEM0_ADDR___S 0 +#define PHYA_DEMFRONT_0_CV_IDM_RXMEM0_ADDR_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_IDM_RXMEM0_ADDR_L___S 0 + +#define PHYA_DEMFRONT_0_CV_IDM_RXMEM1_ADDR_L (0x004395D8) +#define PHYA_DEMFRONT_0_CV_IDM_RXMEM1_ADDR_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CV_IDM_RXMEM1_ADDR_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_IDM_RXMEM1_ADDR_L__CV_IDM_RXMEM1_ADDR___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_IDM_RXMEM1_ADDR_L__CV_IDM_RXMEM1_ADDR___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_IDM_RXMEM1_ADDR_L__CV_IDM_RXMEM1_ADDR___S 0 +#define PHYA_DEMFRONT_0_CV_IDM_RXMEM1_ADDR_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_IDM_RXMEM1_ADDR_L___S 0 + +#define PHYA_DEMFRONT_0_CV_RXMEM0_S0_L_n(n) (0x004415E0+0x8*(n)) +#define PHYA_DEMFRONT_0_CV_RXMEM0_S0_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S0_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S0_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S0_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CV_RXMEM0_S0_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S0_L_n__CV_RXMEM0_S0_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S0_L_n__CV_RXMEM0_S0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM0_S0_L_n__CV_RXMEM0_S0_0___S 0 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S0_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM0_S0_L_n___S 0 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S0_L_0 (0x004415E0) +#define PHYA_DEMFRONT_0_CV_RXMEM0_S0_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CV_RXMEM0_S0_L_0__CV_RXMEM0_S0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM0_S0_L_0__CV_RXMEM0_S0_0___S 0 + +#define PHYA_DEMFRONT_0_CV_RXMEM0_S0_U_n(n) (0x004415E4+0x8*(n)) +#define PHYA_DEMFRONT_0_CV_RXMEM0_S0_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S0_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S0_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S0_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CV_RXMEM0_S0_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S0_U_n__CV_RXMEM0_S0_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S0_U_n__CV_RXMEM0_S0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM0_S0_U_n__CV_RXMEM0_S0_1___S 0 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S0_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM0_S0_U_n___S 0 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S0_U_0 (0x004415E4) +#define PHYA_DEMFRONT_0_CV_RXMEM0_S0_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CV_RXMEM0_S0_U_0__CV_RXMEM0_S0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM0_S0_U_0__CV_RXMEM0_S0_1___S 0 + +#define PHYA_DEMFRONT_0_CV_RXMEM0_S1_L_n(n) (0x004435E0+0x8*(n)) +#define PHYA_DEMFRONT_0_CV_RXMEM0_S1_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S1_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S1_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S1_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CV_RXMEM0_S1_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S1_L_n__CV_RXMEM0_S1_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S1_L_n__CV_RXMEM0_S1_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM0_S1_L_n__CV_RXMEM0_S1_0___S 0 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S1_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM0_S1_L_n___S 0 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S1_L_0 (0x004435E0) +#define PHYA_DEMFRONT_0_CV_RXMEM0_S1_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CV_RXMEM0_S1_L_0__CV_RXMEM0_S1_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM0_S1_L_0__CV_RXMEM0_S1_0___S 0 + +#define PHYA_DEMFRONT_0_CV_RXMEM0_S1_U_n(n) (0x004435E4+0x8*(n)) +#define PHYA_DEMFRONT_0_CV_RXMEM0_S1_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S1_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S1_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S1_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CV_RXMEM0_S1_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S1_U_n__CV_RXMEM0_S1_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S1_U_n__CV_RXMEM0_S1_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM0_S1_U_n__CV_RXMEM0_S1_1___S 0 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S1_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM0_S1_U_n___S 0 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S1_U_0 (0x004435E4) +#define PHYA_DEMFRONT_0_CV_RXMEM0_S1_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CV_RXMEM0_S1_U_0__CV_RXMEM0_S1_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM0_S1_U_0__CV_RXMEM0_S1_1___S 0 + +#define PHYA_DEMFRONT_0_CV_RXMEM0_S2_L_n(n) (0x004455E0+0x8*(n)) +#define PHYA_DEMFRONT_0_CV_RXMEM0_S2_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S2_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S2_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S2_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CV_RXMEM0_S2_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S2_L_n__CV_RXMEM0_S2_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S2_L_n__CV_RXMEM0_S2_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM0_S2_L_n__CV_RXMEM0_S2_0___S 0 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S2_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM0_S2_L_n___S 0 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S2_L_0 (0x004455E0) +#define PHYA_DEMFRONT_0_CV_RXMEM0_S2_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CV_RXMEM0_S2_L_0__CV_RXMEM0_S2_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM0_S2_L_0__CV_RXMEM0_S2_0___S 0 + +#define PHYA_DEMFRONT_0_CV_RXMEM0_S2_U_n(n) (0x004455E4+0x8*(n)) +#define PHYA_DEMFRONT_0_CV_RXMEM0_S2_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S2_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S2_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S2_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CV_RXMEM0_S2_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S2_U_n__CV_RXMEM0_S2_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S2_U_n__CV_RXMEM0_S2_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM0_S2_U_n__CV_RXMEM0_S2_1___S 0 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S2_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM0_S2_U_n___S 0 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S2_U_0 (0x004455E4) +#define PHYA_DEMFRONT_0_CV_RXMEM0_S2_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CV_RXMEM0_S2_U_0__CV_RXMEM0_S2_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM0_S2_U_0__CV_RXMEM0_S2_1___S 0 + +#define PHYA_DEMFRONT_0_CV_RXMEM0_S3_L_n(n) (0x004475E0+0x8*(n)) +#define PHYA_DEMFRONT_0_CV_RXMEM0_S3_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S3_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S3_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S3_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CV_RXMEM0_S3_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S3_L_n__CV_RXMEM0_S3_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S3_L_n__CV_RXMEM0_S3_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM0_S3_L_n__CV_RXMEM0_S3_0___S 0 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S3_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM0_S3_L_n___S 0 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S3_L_0 (0x004475E0) +#define PHYA_DEMFRONT_0_CV_RXMEM0_S3_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CV_RXMEM0_S3_L_0__CV_RXMEM0_S3_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM0_S3_L_0__CV_RXMEM0_S3_0___S 0 + +#define PHYA_DEMFRONT_0_CV_RXMEM0_S3_U_n(n) (0x004475E4+0x8*(n)) +#define PHYA_DEMFRONT_0_CV_RXMEM0_S3_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S3_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S3_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S3_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CV_RXMEM0_S3_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S3_U_n__CV_RXMEM0_S3_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S3_U_n__CV_RXMEM0_S3_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM0_S3_U_n__CV_RXMEM0_S3_1___S 0 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S3_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM0_S3_U_n___S 0 +#define PHYA_DEMFRONT_0_CV_RXMEM0_S3_U_0 (0x004475E4) +#define PHYA_DEMFRONT_0_CV_RXMEM0_S3_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CV_RXMEM0_S3_U_0__CV_RXMEM0_S3_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM0_S3_U_0__CV_RXMEM0_S3_1___S 0 + +#define PHYA_DEMFRONT_0_CV_RXMEM1_S0_L_n(n) (0x004495E0+0x8*(n)) +#define PHYA_DEMFRONT_0_CV_RXMEM1_S0_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S0_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S0_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S0_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CV_RXMEM1_S0_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S0_L_n__CV_RXMEM1_S0_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S0_L_n__CV_RXMEM1_S0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM1_S0_L_n__CV_RXMEM1_S0_0___S 0 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S0_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM1_S0_L_n___S 0 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S0_L_0 (0x004495E0) +#define PHYA_DEMFRONT_0_CV_RXMEM1_S0_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CV_RXMEM1_S0_L_0__CV_RXMEM1_S0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM1_S0_L_0__CV_RXMEM1_S0_0___S 0 + +#define PHYA_DEMFRONT_0_CV_RXMEM1_S0_U_n(n) (0x004495E4+0x8*(n)) +#define PHYA_DEMFRONT_0_CV_RXMEM1_S0_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S0_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S0_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S0_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CV_RXMEM1_S0_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S0_U_n__CV_RXMEM1_S0_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S0_U_n__CV_RXMEM1_S0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM1_S0_U_n__CV_RXMEM1_S0_1___S 0 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S0_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM1_S0_U_n___S 0 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S0_U_0 (0x004495E4) +#define PHYA_DEMFRONT_0_CV_RXMEM1_S0_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CV_RXMEM1_S0_U_0__CV_RXMEM1_S0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM1_S0_U_0__CV_RXMEM1_S0_1___S 0 + +#define PHYA_DEMFRONT_0_CV_RXMEM1_S1_L_n(n) (0x0044B5E0+0x8*(n)) +#define PHYA_DEMFRONT_0_CV_RXMEM1_S1_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S1_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S1_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S1_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CV_RXMEM1_S1_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S1_L_n__CV_RXMEM1_S1_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S1_L_n__CV_RXMEM1_S1_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM1_S1_L_n__CV_RXMEM1_S1_0___S 0 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S1_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM1_S1_L_n___S 0 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S1_L_0 (0x0044B5E0) +#define PHYA_DEMFRONT_0_CV_RXMEM1_S1_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CV_RXMEM1_S1_L_0__CV_RXMEM1_S1_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM1_S1_L_0__CV_RXMEM1_S1_0___S 0 + +#define PHYA_DEMFRONT_0_CV_RXMEM1_S1_U_n(n) (0x0044B5E4+0x8*(n)) +#define PHYA_DEMFRONT_0_CV_RXMEM1_S1_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S1_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S1_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S1_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CV_RXMEM1_S1_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S1_U_n__CV_RXMEM1_S1_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S1_U_n__CV_RXMEM1_S1_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM1_S1_U_n__CV_RXMEM1_S1_1___S 0 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S1_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM1_S1_U_n___S 0 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S1_U_0 (0x0044B5E4) +#define PHYA_DEMFRONT_0_CV_RXMEM1_S1_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CV_RXMEM1_S1_U_0__CV_RXMEM1_S1_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM1_S1_U_0__CV_RXMEM1_S1_1___S 0 + +#define PHYA_DEMFRONT_0_CV_RXMEM1_S2_L_n(n) (0x0044D5E0+0x8*(n)) +#define PHYA_DEMFRONT_0_CV_RXMEM1_S2_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S2_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S2_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S2_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CV_RXMEM1_S2_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S2_L_n__CV_RXMEM1_S2_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S2_L_n__CV_RXMEM1_S2_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM1_S2_L_n__CV_RXMEM1_S2_0___S 0 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S2_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM1_S2_L_n___S 0 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S2_L_0 (0x0044D5E0) +#define PHYA_DEMFRONT_0_CV_RXMEM1_S2_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CV_RXMEM1_S2_L_0__CV_RXMEM1_S2_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM1_S2_L_0__CV_RXMEM1_S2_0___S 0 + +#define PHYA_DEMFRONT_0_CV_RXMEM1_S2_U_n(n) (0x0044D5E4+0x8*(n)) +#define PHYA_DEMFRONT_0_CV_RXMEM1_S2_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S2_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S2_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S2_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CV_RXMEM1_S2_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S2_U_n__CV_RXMEM1_S2_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S2_U_n__CV_RXMEM1_S2_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM1_S2_U_n__CV_RXMEM1_S2_1___S 0 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S2_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM1_S2_U_n___S 0 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S2_U_0 (0x0044D5E4) +#define PHYA_DEMFRONT_0_CV_RXMEM1_S2_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CV_RXMEM1_S2_U_0__CV_RXMEM1_S2_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM1_S2_U_0__CV_RXMEM1_S2_1___S 0 + +#define PHYA_DEMFRONT_0_CV_RXMEM1_S3_L_n(n) (0x0044F5E0+0x8*(n)) +#define PHYA_DEMFRONT_0_CV_RXMEM1_S3_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S3_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S3_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S3_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CV_RXMEM1_S3_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S3_L_n__CV_RXMEM1_S3_0___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S3_L_n__CV_RXMEM1_S3_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM1_S3_L_n__CV_RXMEM1_S3_0___S 0 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S3_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM1_S3_L_n___S 0 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S3_L_0 (0x0044F5E0) +#define PHYA_DEMFRONT_0_CV_RXMEM1_S3_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CV_RXMEM1_S3_L_0__CV_RXMEM1_S3_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM1_S3_L_0__CV_RXMEM1_S3_0___S 0 + +#define PHYA_DEMFRONT_0_CV_RXMEM1_S3_U_n(n) (0x0044F5E4+0x8*(n)) +#define PHYA_DEMFRONT_0_CV_RXMEM1_S3_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S3_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S3_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S3_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CV_RXMEM1_S3_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S3_U_n__CV_RXMEM1_S3_1___POR 0x00000000 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S3_U_n__CV_RXMEM1_S3_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM1_S3_U_n__CV_RXMEM1_S3_1___S 0 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S3_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM1_S3_U_n___S 0 +#define PHYA_DEMFRONT_0_CV_RXMEM1_S3_U_0 (0x0044F5E4) +#define PHYA_DEMFRONT_0_CV_RXMEM1_S3_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_CV_RXMEM1_S3_U_0__CV_RXMEM1_S3_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_0_CV_RXMEM1_S3_U_0__CV_RXMEM1_S3_1___S 0 + +#define PHYA_DEMFRONT_0_NPR_PHYB_CFG_L (0x004615E0) +#define PHYA_DEMFRONT_0_NPR_PHYB_CFG_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_NPR_PHYB_CFG_L___POR 0x00000000 +#define PHYA_DEMFRONT_0_NPR_PHYB_CFG_L__WFAX_DEMF_CSR_11AX_1X1_80___POR 0x0 +#define PHYA_DEMFRONT_0_NPR_PHYB_CFG_L__WFAX_DEMF_CSR_11AX_1X1_80___M 0x00000001 +#define PHYA_DEMFRONT_0_NPR_PHYB_CFG_L__WFAX_DEMF_CSR_11AX_1X1_80___S 0 +#define PHYA_DEMFRONT_0_NPR_PHYB_CFG_L___M 0x00000001 +#define PHYA_DEMFRONT_0_NPR_PHYB_CFG_L___S 0 + +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN0_L_n(n) (0x004615E8+0x8*(n)) +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN0_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN0_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN0_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN0_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN0_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN0_L_n__PILOT_MEM_CHN0_0___POR 0x0000000 +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN0_L_n__PILOT_MEM_CHN0_0___M 0x0FFFFFFF +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN0_L_n__PILOT_MEM_CHN0_0___S 0 +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN0_L_n___M 0x0FFFFFFF +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN0_L_n___S 0 +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN0_L_0 (0x004615E8) +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN0_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN0_L_0__PILOT_MEM_CHN0_0___M 0x0FFFFFFF +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN0_L_0__PILOT_MEM_CHN0_0___S 0 + +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN0_U_n(n) (0x004615EC+0x8*(n)) +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN0_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN0_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN0_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN0_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN0_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN0_U_n__PILOT_MEM_CHN0_1___POR 0x0000000 +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN0_U_n__PILOT_MEM_CHN0_1___M 0x0FFFFFFF +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN0_U_n__PILOT_MEM_CHN0_1___S 0 +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN0_U_n___M 0x0FFFFFFF +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN0_U_n___S 0 +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN0_U_0 (0x004615EC) +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN0_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN0_U_0__PILOT_MEM_CHN0_1___M 0x0FFFFFFF +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN0_U_0__PILOT_MEM_CHN0_1___S 0 + +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN1_L_n(n) (0x00461868+0x8*(n)) +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN1_L_n_nMIN 0 +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN1_L_n_nMAX 0 +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN1_L_n_ELEM 1 +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN1_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN1_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN1_L_n__PILOT_MEM_CHN1_0___POR 0x0000000 +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN1_L_n__PILOT_MEM_CHN1_0___M 0x0FFFFFFF +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN1_L_n__PILOT_MEM_CHN1_0___S 0 +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN1_L_n___M 0x0FFFFFFF +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN1_L_n___S 0 +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN1_L_0 (0x00461868) +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN1_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN1_L_0__PILOT_MEM_CHN1_0___M 0x0FFFFFFF +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN1_L_0__PILOT_MEM_CHN1_0___S 0 + +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN1_U_n(n) (0x0046186C+0x8*(n)) +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN1_U_n_nMIN 0 +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN1_U_n_nMAX 0 +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN1_U_n_ELEM 1 +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN1_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN1_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN1_U_n__PILOT_MEM_CHN1_1___POR 0x0000000 +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN1_U_n__PILOT_MEM_CHN1_1___M 0x0FFFFFFF +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN1_U_n__PILOT_MEM_CHN1_1___S 0 +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN1_U_n___M 0x0FFFFFFF +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN1_U_n___S 0 +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN1_U_0 (0x0046186C) +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN1_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN1_U_0__PILOT_MEM_CHN1_1___M 0x0FFFFFFF +#define PHYA_DEMFRONT_0_PILOT_MEM_CHN1_U_0__PILOT_MEM_CHN1_1___S 0 + +#define PHYA_PHYRF_ECO_CONTROL_L (0x00480000) +#define PHYA_PHYRF_ECO_CONTROL_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_ECO_CONTROL_L___POR 0x00000000 +#define PHYA_PHYRF_ECO_CONTROL_L__ECO_CTRL___POR 0x00000000 +#define PHYA_PHYRF_ECO_CONTROL_L__ECO_CTRL___M 0xFFFFFFFF +#define PHYA_PHYRF_ECO_CONTROL_L__ECO_CTRL___S 0 +#define PHYA_PHYRF_ECO_CONTROL_L___M 0xFFFFFFFF +#define PHYA_PHYRF_ECO_CONTROL_L___S 0 + +#define PHYA_PHYRF_ECO_CONTROL_U (0x00480004) +#define PHYA_PHYRF_ECO_CONTROL_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_ECO_CONTROL_U___POR 0x00000000 +#define PHYA_PHYRF_ECO_CONTROL_U__ECO_CFG___POR 0x00000000 +#define PHYA_PHYRF_ECO_CONTROL_U__ECO_CFG___M 0xFFFFFFFF +#define PHYA_PHYRF_ECO_CONTROL_U__ECO_CFG___S 0 +#define PHYA_PHYRF_ECO_CONTROL_U___M 0xFFFFFFFF +#define PHYA_PHYRF_ECO_CONTROL_U___S 0 + +#define PHYA_PHYRF_ECO_STATUS_L (0x00480008) +#define PHYA_PHYRF_ECO_STATUS_L___RWC QCSR_REG_RO +#define PHYA_PHYRF_ECO_STATUS_L___POR 0x00000000 +#define PHYA_PHYRF_ECO_STATUS_L__ECO_STAT___POR 0x00000000 +#define PHYA_PHYRF_ECO_STATUS_L__ECO_STAT___M 0xFFFFFFFF +#define PHYA_PHYRF_ECO_STATUS_L__ECO_STAT___S 0 +#define PHYA_PHYRF_ECO_STATUS_L___M 0xFFFFFFFF +#define PHYA_PHYRF_ECO_STATUS_L___S 0 + +#define PHYA_PHYRF_EVENT_STATUS_L (0x00480010) +#define PHYA_PHYRF_EVENT_STATUS_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_EVENT_STATUS_L___POR 0x00040000 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TS_TIMER0_EVENT___POR 0x0 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYDBG_BANK3_EVENT___POR 0x0 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYDBG_BANK2_EVENT___POR 0x0 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYDBG_BANK1_EVENT___POR 0x0 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYDBG_BANK0_EVENT___POR 0x0 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TX_PRE_DESC_EVENT___POR 0x1 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_MASTER_SYNTH_RELOCK_EVENT___POR 0x0 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_IMPCORR_EVENT___POR 0x0 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_CAL_RESULTS_RDY_EVENT___POR 0x0 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_CAL_CMD_SEQ_PAUSE_EVENT___POR 0x0 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TPC_CLPC_EVENT___POR 0x0 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_RFACTRL_EVENT___POR 0x0 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TX_FLAG_NOTIFY_EVENT___POR 0x0 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TX_DESC_EVENT___POR 0x0 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_PHYDBG_EVENT___POR 0x0 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_DPDTRAIN_DONE_EVENT___POR 0x0 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_CAL_CMD_SEQ_DONE_EVENT___POR 0x0 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TS_TIMER1_EVENT___POR 0x0 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_RX_PACKET_SYM_EVENT___POR 0x0 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TX_PACKET_END_EVENT___POR 0x0 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_READY_TO_RECEIVE_EVENT___POR 0x0 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_SYNTH_ON_EVENT___POR 0x0 +#define PHYA_PHYRF_EVENT_STATUS_L__ECO_EVENT___POR 0x0 +#define PHYA_PHYRF_EVENT_STATUS_L__ERROR_EVENT___POR 0x0 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TS_TIMER0_EVENT___M 0x00800000 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TS_TIMER0_EVENT___S 23 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYDBG_BANK3_EVENT___M 0x00400000 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYDBG_BANK3_EVENT___S 22 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYDBG_BANK2_EVENT___M 0x00200000 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYDBG_BANK2_EVENT___S 21 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYDBG_BANK1_EVENT___M 0x00100000 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYDBG_BANK1_EVENT___S 20 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYDBG_BANK0_EVENT___M 0x00080000 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYDBG_BANK0_EVENT___S 19 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TX_PRE_DESC_EVENT___M 0x00040000 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TX_PRE_DESC_EVENT___S 18 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_MASTER_SYNTH_RELOCK_EVENT___M 0x00020000 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_MASTER_SYNTH_RELOCK_EVENT___S 17 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_IMPCORR_EVENT___M 0x00010000 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_IMPCORR_EVENT___S 16 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_CAL_RESULTS_RDY_EVENT___M 0x00008000 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_CAL_RESULTS_RDY_EVENT___S 15 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_CAL_CMD_SEQ_PAUSE_EVENT___M 0x00004000 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_CAL_CMD_SEQ_PAUSE_EVENT___S 14 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TPC_CLPC_EVENT___M 0x00002000 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TPC_CLPC_EVENT___S 13 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_RFACTRL_EVENT___M 0x00001000 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_RFACTRL_EVENT___S 12 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TX_FLAG_NOTIFY_EVENT___M 0x00000800 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TX_FLAG_NOTIFY_EVENT___S 11 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TX_DESC_EVENT___M 0x00000400 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TX_DESC_EVENT___S 10 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_PHYDBG_EVENT___M 0x00000200 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_PHYDBG_EVENT___S 9 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_DPDTRAIN_DONE_EVENT___M 0x00000100 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_DPDTRAIN_DONE_EVENT___S 8 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_CAL_CMD_SEQ_DONE_EVENT___M 0x00000080 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_CAL_CMD_SEQ_DONE_EVENT___S 7 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TS_TIMER1_EVENT___M 0x00000040 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TS_TIMER1_EVENT___S 6 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_RX_PACKET_SYM_EVENT___M 0x00000020 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_RX_PACKET_SYM_EVENT___S 5 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TX_PACKET_END_EVENT___M 0x00000010 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_TX_PACKET_END_EVENT___S 4 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_READY_TO_RECEIVE_EVENT___M 0x00000008 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_READY_TO_RECEIVE_EVENT___S 3 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_SYNTH_ON_EVENT___M 0x00000004 +#define PHYA_PHYRF_EVENT_STATUS_L__PHYRF_SYNTH_ON_EVENT___S 2 +#define PHYA_PHYRF_EVENT_STATUS_L__ECO_EVENT___M 0x00000002 +#define PHYA_PHYRF_EVENT_STATUS_L__ECO_EVENT___S 1 +#define PHYA_PHYRF_EVENT_STATUS_L__ERROR_EVENT___M 0x00000001 +#define PHYA_PHYRF_EVENT_STATUS_L__ERROR_EVENT___S 0 +#define PHYA_PHYRF_EVENT_STATUS_L___M 0x00FFFFFF +#define PHYA_PHYRF_EVENT_STATUS_L___S 0 + +#define PHYA_PHYRF_EVENT_MASK_L (0x00480018) +#define PHYA_PHYRF_EVENT_MASK_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_EVENT_MASK_L___POR 0x00FFFFFF +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_TS_TIMER0_EVENT_MASK___POR 0x1 +#define PHYA_PHYRF_EVENT_MASK_L__PHYDBG_BANK3_EVENT_MASK___POR 0x1 +#define PHYA_PHYRF_EVENT_MASK_L__PHYDBG_BANK2_EVENT_MASK___POR 0x1 +#define PHYA_PHYRF_EVENT_MASK_L__PHYDBG_BANK1_EVENT_MASK___POR 0x1 +#define PHYA_PHYRF_EVENT_MASK_L__PHYDBG_BANK0_EVENT_MASK___POR 0x1 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_TX_PRE_DESC_EVENT_MASK___POR 0x1 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_MASTER_SYNTH_RELOCK_EVENT_MASK___POR 0x1 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_IMPCORR_EVENT_MASK___POR 0x1 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_CAL_RESULTS_RDY_EVENT_MASK___POR 0x1 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_CAL_CMD_SEQ_PAUSE_EVENT_MASK___POR 0x1 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_TPC_CLPC_EVENT_MASK___POR 0x1 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_RFACTRL_EVENT_MASK___POR 0x1 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_TX_FLAG_NOTIFY_EVENT_MASK___POR 0x1 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_TX_DESC_EVENT_MASK___POR 0x1 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_PHYDBG_EVENT_MASK___POR 0x1 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_DPDTRAIN_DONE_EVENT_MASK___POR 0x1 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_CAL_CMD_SEQ_DONE_EVENT_MASK___POR 0x1 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_TS_TIMER1_EVENT_MASK___POR 0x1 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_RX_PACKET_SYM_EVENT_MASK___POR 0x1 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_TX_PACKET_END_EVENT_MASK___POR 0x1 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_READY_TO_RECEIVE_EVENT_MASK___POR 0x1 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_SYNTH_ON_EVENT_MASK___POR 0x1 +#define PHYA_PHYRF_EVENT_MASK_L__ECO_EVENT_MASK___POR 0x1 +#define PHYA_PHYRF_EVENT_MASK_L__ERROR_EVENT_MASK___POR 0x1 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_TS_TIMER0_EVENT_MASK___M 0x00800000 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_TS_TIMER0_EVENT_MASK___S 23 +#define PHYA_PHYRF_EVENT_MASK_L__PHYDBG_BANK3_EVENT_MASK___M 0x00400000 +#define PHYA_PHYRF_EVENT_MASK_L__PHYDBG_BANK3_EVENT_MASK___S 22 +#define PHYA_PHYRF_EVENT_MASK_L__PHYDBG_BANK2_EVENT_MASK___M 0x00200000 +#define PHYA_PHYRF_EVENT_MASK_L__PHYDBG_BANK2_EVENT_MASK___S 21 +#define PHYA_PHYRF_EVENT_MASK_L__PHYDBG_BANK1_EVENT_MASK___M 0x00100000 +#define PHYA_PHYRF_EVENT_MASK_L__PHYDBG_BANK1_EVENT_MASK___S 20 +#define PHYA_PHYRF_EVENT_MASK_L__PHYDBG_BANK0_EVENT_MASK___M 0x00080000 +#define PHYA_PHYRF_EVENT_MASK_L__PHYDBG_BANK0_EVENT_MASK___S 19 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_TX_PRE_DESC_EVENT_MASK___M 0x00040000 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_TX_PRE_DESC_EVENT_MASK___S 18 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_MASTER_SYNTH_RELOCK_EVENT_MASK___M 0x00020000 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_MASTER_SYNTH_RELOCK_EVENT_MASK___S 17 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_IMPCORR_EVENT_MASK___M 0x00010000 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_IMPCORR_EVENT_MASK___S 16 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_CAL_RESULTS_RDY_EVENT_MASK___M 0x00008000 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_CAL_RESULTS_RDY_EVENT_MASK___S 15 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_CAL_CMD_SEQ_PAUSE_EVENT_MASK___M 0x00004000 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_CAL_CMD_SEQ_PAUSE_EVENT_MASK___S 14 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_TPC_CLPC_EVENT_MASK___M 0x00002000 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_TPC_CLPC_EVENT_MASK___S 13 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_RFACTRL_EVENT_MASK___M 0x00001000 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_RFACTRL_EVENT_MASK___S 12 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_TX_FLAG_NOTIFY_EVENT_MASK___M 0x00000800 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_TX_FLAG_NOTIFY_EVENT_MASK___S 11 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_TX_DESC_EVENT_MASK___M 0x00000400 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_TX_DESC_EVENT_MASK___S 10 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_PHYDBG_EVENT_MASK___M 0x00000200 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_PHYDBG_EVENT_MASK___S 9 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_DPDTRAIN_DONE_EVENT_MASK___M 0x00000100 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_DPDTRAIN_DONE_EVENT_MASK___S 8 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_CAL_CMD_SEQ_DONE_EVENT_MASK___M 0x00000080 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_CAL_CMD_SEQ_DONE_EVENT_MASK___S 7 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_TS_TIMER1_EVENT_MASK___M 0x00000040 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_TS_TIMER1_EVENT_MASK___S 6 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_RX_PACKET_SYM_EVENT_MASK___M 0x00000020 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_RX_PACKET_SYM_EVENT_MASK___S 5 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_TX_PACKET_END_EVENT_MASK___M 0x00000010 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_TX_PACKET_END_EVENT_MASK___S 4 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_READY_TO_RECEIVE_EVENT_MASK___M 0x00000008 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_READY_TO_RECEIVE_EVENT_MASK___S 3 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_SYNTH_ON_EVENT_MASK___M 0x00000004 +#define PHYA_PHYRF_EVENT_MASK_L__PHYRF_SYNTH_ON_EVENT_MASK___S 2 +#define PHYA_PHYRF_EVENT_MASK_L__ECO_EVENT_MASK___M 0x00000002 +#define PHYA_PHYRF_EVENT_MASK_L__ECO_EVENT_MASK___S 1 +#define PHYA_PHYRF_EVENT_MASK_L__ERROR_EVENT_MASK___M 0x00000001 +#define PHYA_PHYRF_EVENT_MASK_L__ERROR_EVENT_MASK___S 0 +#define PHYA_PHYRF_EVENT_MASK_L___M 0x00FFFFFF +#define PHYA_PHYRF_EVENT_MASK_L___S 0 + +#define PHYA_PHYRF_ERROR_CODE_L (0x00480020) +#define PHYA_PHYRF_ERROR_CODE_L___RWC QCSR_REG_RO +#define PHYA_PHYRF_ERROR_CODE_L___POR 0x00000000 +#define PHYA_PHYRF_ERROR_CODE_L__ERROR_CODE___POR 0x0 +#define PHYA_PHYRF_ERROR_CODE_L__ERROR_CODE___M 0x0000000F +#define PHYA_PHYRF_ERROR_CODE_L__ERROR_CODE___S 0 +#define PHYA_PHYRF_ERROR_CODE_L___M 0x0000000F +#define PHYA_PHYRF_ERROR_CODE_L___S 0 + +#define PHYA_PHYRF_ERROR_STATUS_L (0x00480028) +#define PHYA_PHYRF_ERROR_STATUS_L___RWC QCSR_REG_RO +#define PHYA_PHYRF_ERROR_STATUS_L___POR 0x00000000 +#define PHYA_PHYRF_ERROR_STATUS_L__RXIMPCORR_ERROR___POR 0x0 +#define PHYA_PHYRF_ERROR_STATUS_L__TXIMPCORR_ERROR___POR 0x0 +#define PHYA_PHYRF_ERROR_STATUS_L__TPC_GAIN_NOT_RDY_ERROR___POR 0x0 +#define PHYA_PHYRF_ERROR_STATUS_L__PHYRF_TX_FLAG_NOTIFY_ERROR___POR 0x0 +#define PHYA_PHYRF_ERROR_STATUS_L__PHYRF_TPC_CLPC_ERROR___POR 0x0 +#define PHYA_PHYRF_ERROR_STATUS_L__TPC_MISS_ERROR___POR 0x0 +#define PHYA_PHYRF_ERROR_STATUS_L__PHYRF_TX_PRE_DESC_ERROR___POR 0x0 +#define PHYA_PHYRF_ERROR_STATUS_L__PHYRF_TX_DESC_ERROR___POR 0x0 +#define PHYA_PHYRF_ERROR_STATUS_L__PHYRF_CONFIG_ERROR___POR 0x0 +#define PHYA_PHYRF_ERROR_STATUS_L__ADAC_CTRL_ERROR___POR 0x0 +#define PHYA_PHYRF_ERROR_STATUS_L__RFCMD_DROP_ERROR___POR 0x0 +#define PHYA_PHYRF_ERROR_STATUS_L__WSI_ERROR___POR 0x0 +#define PHYA_PHYRF_ERROR_STATUS_L__RFACTRL_ERROR___POR 0x0 +#define PHYA_PHYRF_ERROR_STATUS_L__CAL_ERROR___POR 0x0 +#define PHYA_PHYRF_ERROR_STATUS_L__RXIMPCORR_ERROR___M 0x00002000 +#define PHYA_PHYRF_ERROR_STATUS_L__RXIMPCORR_ERROR___S 13 +#define PHYA_PHYRF_ERROR_STATUS_L__TXIMPCORR_ERROR___M 0x00001000 +#define PHYA_PHYRF_ERROR_STATUS_L__TXIMPCORR_ERROR___S 12 +#define PHYA_PHYRF_ERROR_STATUS_L__TPC_GAIN_NOT_RDY_ERROR___M 0x00000800 +#define PHYA_PHYRF_ERROR_STATUS_L__TPC_GAIN_NOT_RDY_ERROR___S 11 +#define PHYA_PHYRF_ERROR_STATUS_L__PHYRF_TX_FLAG_NOTIFY_ERROR___M 0x00000400 +#define PHYA_PHYRF_ERROR_STATUS_L__PHYRF_TX_FLAG_NOTIFY_ERROR___S 10 +#define PHYA_PHYRF_ERROR_STATUS_L__PHYRF_TPC_CLPC_ERROR___M 0x00000200 +#define PHYA_PHYRF_ERROR_STATUS_L__PHYRF_TPC_CLPC_ERROR___S 9 +#define PHYA_PHYRF_ERROR_STATUS_L__TPC_MISS_ERROR___M 0x00000100 +#define PHYA_PHYRF_ERROR_STATUS_L__TPC_MISS_ERROR___S 8 +#define PHYA_PHYRF_ERROR_STATUS_L__PHYRF_TX_PRE_DESC_ERROR___M 0x00000080 +#define PHYA_PHYRF_ERROR_STATUS_L__PHYRF_TX_PRE_DESC_ERROR___S 7 +#define PHYA_PHYRF_ERROR_STATUS_L__PHYRF_TX_DESC_ERROR___M 0x00000040 +#define PHYA_PHYRF_ERROR_STATUS_L__PHYRF_TX_DESC_ERROR___S 6 +#define PHYA_PHYRF_ERROR_STATUS_L__PHYRF_CONFIG_ERROR___M 0x00000020 +#define PHYA_PHYRF_ERROR_STATUS_L__PHYRF_CONFIG_ERROR___S 5 +#define PHYA_PHYRF_ERROR_STATUS_L__ADAC_CTRL_ERROR___M 0x00000010 +#define PHYA_PHYRF_ERROR_STATUS_L__ADAC_CTRL_ERROR___S 4 +#define PHYA_PHYRF_ERROR_STATUS_L__RFCMD_DROP_ERROR___M 0x00000008 +#define PHYA_PHYRF_ERROR_STATUS_L__RFCMD_DROP_ERROR___S 3 +#define PHYA_PHYRF_ERROR_STATUS_L__WSI_ERROR___M 0x00000004 +#define PHYA_PHYRF_ERROR_STATUS_L__WSI_ERROR___S 2 +#define PHYA_PHYRF_ERROR_STATUS_L__RFACTRL_ERROR___M 0x00000002 +#define PHYA_PHYRF_ERROR_STATUS_L__RFACTRL_ERROR___S 1 +#define PHYA_PHYRF_ERROR_STATUS_L__CAL_ERROR___M 0x00000001 +#define PHYA_PHYRF_ERROR_STATUS_L__CAL_ERROR___S 0 +#define PHYA_PHYRF_ERROR_STATUS_L___M 0x00003FFF +#define PHYA_PHYRF_ERROR_STATUS_L___S 0 + +#define PHYA_PHYRF_ERROR_MASK_L (0x00480030) +#define PHYA_PHYRF_ERROR_MASK_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_ERROR_MASK_L___POR 0x00003FFF +#define PHYA_PHYRF_ERROR_MASK_L__RXIMPCORR_ERROR_MASK___POR 0x1 +#define PHYA_PHYRF_ERROR_MASK_L__TXIMPCORR_ERROR_MASK___POR 0x1 +#define PHYA_PHYRF_ERROR_MASK_L__TPC_GAIN_NOT_RDY_ERROR_MASK___POR 0x1 +#define PHYA_PHYRF_ERROR_MASK_L__PHYRF_TX_FLAG_NOTIFY_ERROR_MASK___POR 0x1 +#define PHYA_PHYRF_ERROR_MASK_L__PHYRF_TPC_CLPC_ERROR_MASK___POR 0x1 +#define PHYA_PHYRF_ERROR_MASK_L__TPC_MISS_ERROR_MASK___POR 0x1 +#define PHYA_PHYRF_ERROR_MASK_L__PHYRF_TX_PRE_DESC_ERROR_MASK___POR 0x1 +#define PHYA_PHYRF_ERROR_MASK_L__PHYRF_TX_DESC_ERROR_MASK___POR 0x1 +#define PHYA_PHYRF_ERROR_MASK_L__PHYRF_CONFIG_ERROR_MASK___POR 0x1 +#define PHYA_PHYRF_ERROR_MASK_L__ADAC_CTRL_ERROR_MASK___POR 0x1 +#define PHYA_PHYRF_ERROR_MASK_L__RFCMD_DROP_ERROR_MASK___POR 0x1 +#define PHYA_PHYRF_ERROR_MASK_L__WSI_ERROR_MASK___POR 0x1 +#define PHYA_PHYRF_ERROR_MASK_L__RFACTRL_ERROR_MASK___POR 0x1 +#define PHYA_PHYRF_ERROR_MASK_L__CAL_ERROR_MASK___POR 0x1 +#define PHYA_PHYRF_ERROR_MASK_L__RXIMPCORR_ERROR_MASK___M 0x00002000 +#define PHYA_PHYRF_ERROR_MASK_L__RXIMPCORR_ERROR_MASK___S 13 +#define PHYA_PHYRF_ERROR_MASK_L__TXIMPCORR_ERROR_MASK___M 0x00001000 +#define PHYA_PHYRF_ERROR_MASK_L__TXIMPCORR_ERROR_MASK___S 12 +#define PHYA_PHYRF_ERROR_MASK_L__TPC_GAIN_NOT_RDY_ERROR_MASK___M 0x00000800 +#define PHYA_PHYRF_ERROR_MASK_L__TPC_GAIN_NOT_RDY_ERROR_MASK___S 11 +#define PHYA_PHYRF_ERROR_MASK_L__PHYRF_TX_FLAG_NOTIFY_ERROR_MASK___M 0x00000400 +#define PHYA_PHYRF_ERROR_MASK_L__PHYRF_TX_FLAG_NOTIFY_ERROR_MASK___S 10 +#define PHYA_PHYRF_ERROR_MASK_L__PHYRF_TPC_CLPC_ERROR_MASK___M 0x00000200 +#define PHYA_PHYRF_ERROR_MASK_L__PHYRF_TPC_CLPC_ERROR_MASK___S 9 +#define PHYA_PHYRF_ERROR_MASK_L__TPC_MISS_ERROR_MASK___M 0x00000100 +#define PHYA_PHYRF_ERROR_MASK_L__TPC_MISS_ERROR_MASK___S 8 +#define PHYA_PHYRF_ERROR_MASK_L__PHYRF_TX_PRE_DESC_ERROR_MASK___M 0x00000080 +#define PHYA_PHYRF_ERROR_MASK_L__PHYRF_TX_PRE_DESC_ERROR_MASK___S 7 +#define PHYA_PHYRF_ERROR_MASK_L__PHYRF_TX_DESC_ERROR_MASK___M 0x00000040 +#define PHYA_PHYRF_ERROR_MASK_L__PHYRF_TX_DESC_ERROR_MASK___S 6 +#define PHYA_PHYRF_ERROR_MASK_L__PHYRF_CONFIG_ERROR_MASK___M 0x00000020 +#define PHYA_PHYRF_ERROR_MASK_L__PHYRF_CONFIG_ERROR_MASK___S 5 +#define PHYA_PHYRF_ERROR_MASK_L__ADAC_CTRL_ERROR_MASK___M 0x00000010 +#define PHYA_PHYRF_ERROR_MASK_L__ADAC_CTRL_ERROR_MASK___S 4 +#define PHYA_PHYRF_ERROR_MASK_L__RFCMD_DROP_ERROR_MASK___M 0x00000008 +#define PHYA_PHYRF_ERROR_MASK_L__RFCMD_DROP_ERROR_MASK___S 3 +#define PHYA_PHYRF_ERROR_MASK_L__WSI_ERROR_MASK___M 0x00000004 +#define PHYA_PHYRF_ERROR_MASK_L__WSI_ERROR_MASK___S 2 +#define PHYA_PHYRF_ERROR_MASK_L__RFACTRL_ERROR_MASK___M 0x00000002 +#define PHYA_PHYRF_ERROR_MASK_L__RFACTRL_ERROR_MASK___S 1 +#define PHYA_PHYRF_ERROR_MASK_L__CAL_ERROR_MASK___M 0x00000001 +#define PHYA_PHYRF_ERROR_MASK_L__CAL_ERROR_MASK___S 0 +#define PHYA_PHYRF_ERROR_MASK_L___M 0x00003FFF +#define PHYA_PHYRF_ERROR_MASK_L___S 0 + +#define PHYA_PHYRF_TIMESTAMP_0_L (0x00480038) +#define PHYA_PHYRF_TIMESTAMP_0_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TIMESTAMP_0_L___POR 0x00000000 +#define PHYA_PHYRF_TIMESTAMP_0_L__PRELOAD_TIMESTAMP_DATA___POR 0x00000000 +#define PHYA_PHYRF_TIMESTAMP_0_L__PRELOAD_TIMESTAMP_DATA___M 0xFFFFFFFF +#define PHYA_PHYRF_TIMESTAMP_0_L__PRELOAD_TIMESTAMP_DATA___S 0 +#define PHYA_PHYRF_TIMESTAMP_0_L___M 0xFFFFFFFF +#define PHYA_PHYRF_TIMESTAMP_0_L___S 0 + +#define PHYA_PHYRF_TIMESTAMP_0_U (0x0048003C) +#define PHYA_PHYRF_TIMESTAMP_0_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_TIMESTAMP_0_U___POR 0x00010100 +#define PHYA_PHYRF_TIMESTAMP_0_U__TIMESTAMP_INC_VALUE___POR 0x1 +#define PHYA_PHYRF_TIMESTAMP_0_U__RUN_TIMESTAMP___POR 0x1 +#define PHYA_PHYRF_TIMESTAMP_0_U__PRELOAD_TIMESTAMP___POR 0x0 +#define PHYA_PHYRF_TIMESTAMP_0_U__TIMESTAMP_INC_VALUE___M 0x000F0000 +#define PHYA_PHYRF_TIMESTAMP_0_U__TIMESTAMP_INC_VALUE___S 16 +#define PHYA_PHYRF_TIMESTAMP_0_U__RUN_TIMESTAMP___M 0x00000100 +#define PHYA_PHYRF_TIMESTAMP_0_U__RUN_TIMESTAMP___S 8 +#define PHYA_PHYRF_TIMESTAMP_0_U__PRELOAD_TIMESTAMP___M 0x00000001 +#define PHYA_PHYRF_TIMESTAMP_0_U__PRELOAD_TIMESTAMP___S 0 +#define PHYA_PHYRF_TIMESTAMP_0_U___M 0x000F0101 +#define PHYA_PHYRF_TIMESTAMP_0_U___S 0 + +#define PHYA_PHYRF_TIMESTAMP_1_L (0x00480040) +#define PHYA_PHYRF_TIMESTAMP_1_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TIMESTAMP_1_L___POR 0x0000FFFF +#define PHYA_PHYRF_TIMESTAMP_1_L__TIMESTAMP_SOURCE_MASK___POR 0x0000FFFF +#define PHYA_PHYRF_TIMESTAMP_1_L__TIMESTAMP_SOURCE_MASK___M 0xFFFFFFFF +#define PHYA_PHYRF_TIMESTAMP_1_L__TIMESTAMP_SOURCE_MASK___S 0 +#define PHYA_PHYRF_TIMESTAMP_1_L___M 0xFFFFFFFF +#define PHYA_PHYRF_TIMESTAMP_1_L___S 0 + +#define PHYA_PHYRF_ASF_CTRL_L (0x00480048) +#define PHYA_PHYRF_ASF_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_ASF_CTRL_L___POR 0x00000700 +#define PHYA_PHYRF_ASF_CTRL_L__ASF_INVERT_MSB___POR 0x1 +#define PHYA_PHYRF_ASF_CTRL_L__ASF_MSB_PAD_MODE___POR 0x1 +#define PHYA_PHYRF_ASF_CTRL_L__ASF_MSB_ALIGN___POR 0x1 +#define PHYA_PHYRF_ASF_CTRL_L__ASF_INVERT_ANALOG_RX___POR 0x0 +#define PHYA_PHYRF_ASF_CTRL_L__ASF_SWAP_ANALOG_RX___POR 0x0 +#define PHYA_PHYRF_ASF_CTRL_L__ASF_INVERT_MSB___M 0x00000400 +#define PHYA_PHYRF_ASF_CTRL_L__ASF_INVERT_MSB___S 10 +#define PHYA_PHYRF_ASF_CTRL_L__ASF_MSB_PAD_MODE___M 0x00000200 +#define PHYA_PHYRF_ASF_CTRL_L__ASF_MSB_PAD_MODE___S 9 +#define PHYA_PHYRF_ASF_CTRL_L__ASF_MSB_ALIGN___M 0x00000100 +#define PHYA_PHYRF_ASF_CTRL_L__ASF_MSB_ALIGN___S 8 +#define PHYA_PHYRF_ASF_CTRL_L__ASF_INVERT_ANALOG_RX___M 0x000000F0 +#define PHYA_PHYRF_ASF_CTRL_L__ASF_INVERT_ANALOG_RX___S 4 +#define PHYA_PHYRF_ASF_CTRL_L__ASF_SWAP_ANALOG_RX___M 0x0000000F +#define PHYA_PHYRF_ASF_CTRL_L__ASF_SWAP_ANALOG_RX___S 0 +#define PHYA_PHYRF_ASF_CTRL_L___M 0x000007FF +#define PHYA_PHYRF_ASF_CTRL_L___S 0 + +#define PHYA_PHYRF_ADCFIFO_CTRL_L (0x00480050) +#define PHYA_PHYRF_ADCFIFO_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_ADCFIFO_CTRL_L___POR 0x00E40100 +#define PHYA_PHYRF_ADCFIFO_CTRL_L__ADC_MAP_SEL___POR 0xE4 +#define PHYA_PHYRF_ADCFIFO_CTRL_L__ADC_ASYNC_FIFO_EN___POR 0x1 +#define PHYA_PHYRF_ADCFIFO_CTRL_L__PHYRF_NPRB_SBS_ADC_MUX_SEL___POR 0x0 +#define PHYA_PHYRF_ADCFIFO_CTRL_L__ADC_MAP_SEL___M 0x00FF0000 +#define PHYA_PHYRF_ADCFIFO_CTRL_L__ADC_MAP_SEL___S 16 +#define PHYA_PHYRF_ADCFIFO_CTRL_L__ADC_ASYNC_FIFO_EN___M 0x00000100 +#define PHYA_PHYRF_ADCFIFO_CTRL_L__ADC_ASYNC_FIFO_EN___S 8 +#define PHYA_PHYRF_ADCFIFO_CTRL_L__PHYRF_NPRB_SBS_ADC_MUX_SEL___M 0x00000001 +#define PHYA_PHYRF_ADCFIFO_CTRL_L__PHYRF_NPRB_SBS_ADC_MUX_SEL___S 0 +#define PHYA_PHYRF_ADCFIFO_CTRL_L___M 0x00FF0101 +#define PHYA_PHYRF_ADCFIFO_CTRL_L___S 0 + +#define PHYA_PHYRF_TX_VHT160_MODE_L (0x00480058) +#define PHYA_PHYRF_TX_VHT160_MODE_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TX_VHT160_MODE_L___POR 0x00000000 +#define PHYA_PHYRF_TX_VHT160_MODE_L__TX_SEC80_CHAIN_MASK___POR 0x0 +#define PHYA_PHYRF_TX_VHT160_MODE_L__TX_VHT160_MODE_IS_80___POR 0x0 +#define PHYA_PHYRF_TX_VHT160_MODE_L__TX_VHT160_MODE_IS_80P80___POR 0x0 +#define PHYA_PHYRF_TX_VHT160_MODE_L__TX_SEC80_CHAIN_MASK___M 0x000F0000 +#define PHYA_PHYRF_TX_VHT160_MODE_L__TX_SEC80_CHAIN_MASK___S 16 +#define PHYA_PHYRF_TX_VHT160_MODE_L__TX_VHT160_MODE_IS_80___M 0x00000300 +#define PHYA_PHYRF_TX_VHT160_MODE_L__TX_VHT160_MODE_IS_80___S 8 +#define PHYA_PHYRF_TX_VHT160_MODE_L__TX_VHT160_MODE_IS_80P80___M 0x00000003 +#define PHYA_PHYRF_TX_VHT160_MODE_L__TX_VHT160_MODE_IS_80P80___S 0 +#define PHYA_PHYRF_TX_VHT160_MODE_L___M 0x000F0303 +#define PHYA_PHYRF_TX_VHT160_MODE_L___S 0 + +#define PHYA_PHYRF_ADCSAT_L (0x00480060) +#define PHYA_PHYRF_ADCSAT_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_ADCSAT_L___POR 0x00320001 +#define PHYA_PHYRF_ADCSAT_L__ADCSAT_CNT_HIGH___POR 0x032 +#define PHYA_PHYRF_ADCSAT_L__ADCSAT_CNT_LOW___POR 0x001 +#define PHYA_PHYRF_ADCSAT_L__ADCSAT_CNT_HIGH___M 0x07FF0000 +#define PHYA_PHYRF_ADCSAT_L__ADCSAT_CNT_HIGH___S 16 +#define PHYA_PHYRF_ADCSAT_L__ADCSAT_CNT_LOW___M 0x000007FF +#define PHYA_PHYRF_ADCSAT_L__ADCSAT_CNT_LOW___S 0 +#define PHYA_PHYRF_ADCSAT_L___M 0x07FF07FF +#define PHYA_PHYRF_ADCSAT_L___S 0 + +#define PHYA_PHYRF_ADCSAT_U (0x00480064) +#define PHYA_PHYRF_ADCSAT_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_ADCSAT_U___POR 0x07F00002 +#define PHYA_PHYRF_ADCSAT_U__ADCSAT_THR___POR 0x7F0 +#define PHYA_PHYRF_ADCSAT_U__ADCSAT_DELAY___POR 0x00 +#define PHYA_PHYRF_ADCSAT_U__ADCSAT_MA_LEN___POR 0x2 +#define PHYA_PHYRF_ADCSAT_U__ADCSAT_THR___M 0x07FF0000 +#define PHYA_PHYRF_ADCSAT_U__ADCSAT_THR___S 16 +#define PHYA_PHYRF_ADCSAT_U__ADCSAT_DELAY___M 0x00007F00 +#define PHYA_PHYRF_ADCSAT_U__ADCSAT_DELAY___S 8 +#define PHYA_PHYRF_ADCSAT_U__ADCSAT_MA_LEN___M 0x00000003 +#define PHYA_PHYRF_ADCSAT_U__ADCSAT_MA_LEN___S 0 +#define PHYA_PHYRF_ADCSAT_U___M 0x07FF7F03 +#define PHYA_PHYRF_ADCSAT_U___S 0 + +#define PHYA_PHYRF_RFCTRL_0_L (0x00480068) +#define PHYA_PHYRF_RFCTRL_0_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_RFCTRL_0_L___POR 0x00000000 +#define PHYA_PHYRF_RFCTRL_0_L__ACTIVE_TO_ADC_ON_CM___POR 0x0 +#define PHYA_PHYRF_RFCTRL_0_L__ACTIVE_TO_RX_ON_CM___POR 0x0 +#define PHYA_PHYRF_RFCTRL_0_L__USE_MAC_CHAIN_MASK___POR 0x0 +#define PHYA_PHYRF_RFCTRL_0_L__ANT_SEL___POR 0x0 +#define PHYA_PHYRF_RFCTRL_0_L__ACTIVE_TO_ADC_ON_CM___M 0x0F000000 +#define PHYA_PHYRF_RFCTRL_0_L__ACTIVE_TO_ADC_ON_CM___S 24 +#define PHYA_PHYRF_RFCTRL_0_L__ACTIVE_TO_RX_ON_CM___M 0x000F0000 +#define PHYA_PHYRF_RFCTRL_0_L__ACTIVE_TO_RX_ON_CM___S 16 +#define PHYA_PHYRF_RFCTRL_0_L__USE_MAC_CHAIN_MASK___M 0x00000100 +#define PHYA_PHYRF_RFCTRL_0_L__USE_MAC_CHAIN_MASK___S 8 +#define PHYA_PHYRF_RFCTRL_0_L__ANT_SEL___M 0x00000001 +#define PHYA_PHYRF_RFCTRL_0_L__ANT_SEL___S 0 +#define PHYA_PHYRF_RFCTRL_0_L___M 0x0F0F0101 +#define PHYA_PHYRF_RFCTRL_0_L___S 0 + +#define PHYA_PHYRF_RFCTRL_0_U (0x0048006C) +#define PHYA_PHYRF_RFCTRL_0_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_RFCTRL_0_U___POR 0x00000000 +#define PHYA_PHYRF_RFCTRL_0_U__ACTIVE_TO_RECEIVE___POR 0x0000 +#define PHYA_PHYRF_RFCTRL_0_U__ENABLE_SKIP_SYNTH_SETTLE___POR 0x0 +#define PHYA_PHYRF_RFCTRL_0_U__RX_ON_TO_RECEIVE_CM___POR 0x00 +#define PHYA_PHYRF_RFCTRL_0_U__ACTIVE_TO_RECEIVE___M 0x3FFF0000 +#define PHYA_PHYRF_RFCTRL_0_U__ACTIVE_TO_RECEIVE___S 16 +#define PHYA_PHYRF_RFCTRL_0_U__ENABLE_SKIP_SYNTH_SETTLE___M 0x00000100 +#define PHYA_PHYRF_RFCTRL_0_U__ENABLE_SKIP_SYNTH_SETTLE___S 8 +#define PHYA_PHYRF_RFCTRL_0_U__RX_ON_TO_RECEIVE_CM___M 0x000000FF +#define PHYA_PHYRF_RFCTRL_0_U__RX_ON_TO_RECEIVE_CM___S 0 +#define PHYA_PHYRF_RFCTRL_0_U___M 0x3FFF01FF +#define PHYA_PHYRF_RFCTRL_0_U___S 0 + +#define PHYA_PHYRF_RFCTRL_1_L (0x00480070) +#define PHYA_PHYRF_RFCTRL_1_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_RFCTRL_1_L___POR 0x00140100 +#define PHYA_PHYRF_RFCTRL_1_L__PHYRF_REG_CLOCK_GATE_DISABLE___POR 0x0 +#define PHYA_PHYRF_RFCTRL_1_L__ADC_ON_TO_ADC_STABLE___POR 0x14 +#define PHYA_PHYRF_RFCTRL_1_L__ACTIVE_TO_ADC_ON___POR 0x01 +#define PHYA_PHYRF_RFCTRL_1_L__ACTIVE_TO_RX_ON___POR 0x00 +#define PHYA_PHYRF_RFCTRL_1_L__PHYRF_REG_CLOCK_GATE_DISABLE___M 0x01000000 +#define PHYA_PHYRF_RFCTRL_1_L__PHYRF_REG_CLOCK_GATE_DISABLE___S 24 +#define PHYA_PHYRF_RFCTRL_1_L__ADC_ON_TO_ADC_STABLE___M 0x00FF0000 +#define PHYA_PHYRF_RFCTRL_1_L__ADC_ON_TO_ADC_STABLE___S 16 +#define PHYA_PHYRF_RFCTRL_1_L__ACTIVE_TO_ADC_ON___M 0x0000FF00 +#define PHYA_PHYRF_RFCTRL_1_L__ACTIVE_TO_ADC_ON___S 8 +#define PHYA_PHYRF_RFCTRL_1_L__ACTIVE_TO_RX_ON___M 0x000000FF +#define PHYA_PHYRF_RFCTRL_1_L__ACTIVE_TO_RX_ON___S 0 +#define PHYA_PHYRF_RFCTRL_1_L___M 0x01FFFFFF +#define PHYA_PHYRF_RFCTRL_1_L___S 0 + +#define PHYA_PHYRF_RFCTRL_1_U (0x00480074) +#define PHYA_PHYRF_RFCTRL_1_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_RFCTRL_1_U___POR 0xFFFF0000 +#define PHYA_PHYRF_RFCTRL_1_U__PHYRF_TX_CHAIN_ENABLE___POR 0xFF +#define PHYA_PHYRF_RFCTRL_1_U__RX_CHAIN_MASK___POR 0xFF +#define PHYA_PHYRF_RFCTRL_1_U__RX_CH_BW___POR 0x0 +#define PHYA_PHYRF_RFCTRL_1_U__TX_CH_BW___POR 0x0 +#define PHYA_PHYRF_RFCTRL_1_U__PHYRF_TX_CHAIN_ENABLE___M 0xFF000000 +#define PHYA_PHYRF_RFCTRL_1_U__PHYRF_TX_CHAIN_ENABLE___S 24 +#define PHYA_PHYRF_RFCTRL_1_U__RX_CHAIN_MASK___M 0x00FF0000 +#define PHYA_PHYRF_RFCTRL_1_U__RX_CHAIN_MASK___S 16 +#define PHYA_PHYRF_RFCTRL_1_U__RX_CH_BW___M 0x00000700 +#define PHYA_PHYRF_RFCTRL_1_U__RX_CH_BW___S 8 +#define PHYA_PHYRF_RFCTRL_1_U__TX_CH_BW___M 0x00000007 +#define PHYA_PHYRF_RFCTRL_1_U__TX_CH_BW___S 0 +#define PHYA_PHYRF_RFCTRL_1_U___M 0xFFFF0707 +#define PHYA_PHYRF_RFCTRL_1_U___S 0 + +#define PHYA_PHYRF_RFCTRL_2_L (0x00480078) +#define PHYA_PHYRF_RFCTRL_2_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_RFCTRL_2_L___POR 0x00000A00 +#define PHYA_PHYRF_RFCTRL_2_L__MASTER_SYNTH_RELOCK_DBG_STATUS___POR 0x0 +#define PHYA_PHYRF_RFCTRL_2_L__MASTER_SYNTH_RELOCK_RFBBSAT_MASK___POR 0xA +#define PHYA_PHYRF_RFCTRL_2_L__PHYRF_TX_CHAIN_ENABLE_OVRD___POR 0x0 +#define PHYA_PHYRF_RFCTRL_2_L__MASTER_SYNTH_RELOCK_DBG_STATUS___M 0x00030000 +#define PHYA_PHYRF_RFCTRL_2_L__MASTER_SYNTH_RELOCK_DBG_STATUS___S 16 +#define PHYA_PHYRF_RFCTRL_2_L__MASTER_SYNTH_RELOCK_RFBBSAT_MASK___M 0x00000F00 +#define PHYA_PHYRF_RFCTRL_2_L__MASTER_SYNTH_RELOCK_RFBBSAT_MASK___S 8 +#define PHYA_PHYRF_RFCTRL_2_L__PHYRF_TX_CHAIN_ENABLE_OVRD___M 0x00000001 +#define PHYA_PHYRF_RFCTRL_2_L__PHYRF_TX_CHAIN_ENABLE_OVRD___S 0 +#define PHYA_PHYRF_RFCTRL_2_L___M 0x00030F01 +#define PHYA_PHYRF_RFCTRL_2_L___S 0 + +#define PHYA_PHYRF_RFCTRL_2_U (0x0048007C) +#define PHYA_PHYRF_RFCTRL_2_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_RFCTRL_2_U___POR 0xFFFF1E00 +#define PHYA_PHYRF_RFCTRL_2_U__PHYRF_PHYDBG_EVENTS_MASK___POR 0xFFFF +#define PHYA_PHYRF_RFCTRL_2_U__SIFS_DELAY_TUNED___POR 0x1E00 +#define PHYA_PHYRF_RFCTRL_2_U__PHYRF_PHYDBG_EVENTS_MASK___M 0xFFFF0000 +#define PHYA_PHYRF_RFCTRL_2_U__PHYRF_PHYDBG_EVENTS_MASK___S 16 +#define PHYA_PHYRF_RFCTRL_2_U__SIFS_DELAY_TUNED___M 0x0000FFFF +#define PHYA_PHYRF_RFCTRL_2_U__SIFS_DELAY_TUNED___S 0 +#define PHYA_PHYRF_RFCTRL_2_U___M 0xFFFFFFFF +#define PHYA_PHYRF_RFCTRL_2_U___S 0 + +#define PHYA_PHYRF_RFCTRL_3_L (0x00480080) +#define PHYA_PHYRF_RFCTRL_3_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_RFCTRL_3_L___POR 0x00000000 +#define PHYA_PHYRF_RFCTRL_3_L__RFCNTL_GEN_CONTROLS___POR 0x00000000 +#define PHYA_PHYRF_RFCTRL_3_L__RFCNTL_GEN_CONTROLS___M 0xFFFFFFFF +#define PHYA_PHYRF_RFCTRL_3_L__RFCNTL_GEN_CONTROLS___S 0 +#define PHYA_PHYRF_RFCTRL_3_L___M 0xFFFFFFFF +#define PHYA_PHYRF_RFCTRL_3_L___S 0 + +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L (0x00480088) +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__PHY_IN_CALIBRATION_STAGE___POR 0x0 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__IS_PHYRF_RDY_TO_RCV___POR 0x0 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__IS_RADIO_ON___POR 0x0 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__IS_SYNTH_ON___POR 0x0 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__IS_PHYRF_ON___POR 0x0 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_OFF_ADC___POR 0x0 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_ON_ADC___POR 0x0 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_OFF_DAC___POR 0x0 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_ON_DAC___POR 0x0 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_OFF_RADIO___POR 0x0 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_ON_RADIO___POR 0x0 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_OFF_SYNTH___POR 0x0 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_ON_SYNTH___POR 0x0 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_OFF_PHYRF___POR 0x0 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_ON_PHYRF___POR 0x0 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__PHY_IN_CALIBRATION_STAGE___M 0x00004000 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__PHY_IN_CALIBRATION_STAGE___S 14 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__IS_PHYRF_RDY_TO_RCV___M 0x00002000 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__IS_PHYRF_RDY_TO_RCV___S 13 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__IS_RADIO_ON___M 0x00001000 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__IS_RADIO_ON___S 12 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__IS_SYNTH_ON___M 0x00000800 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__IS_SYNTH_ON___S 11 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__IS_PHYRF_ON___M 0x00000400 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__IS_PHYRF_ON___S 10 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_OFF_ADC___M 0x00000200 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_OFF_ADC___S 9 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_ON_ADC___M 0x00000100 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_ON_ADC___S 8 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_OFF_DAC___M 0x00000080 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_OFF_DAC___S 7 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_ON_DAC___M 0x00000040 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_ON_DAC___S 6 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_OFF_RADIO___M 0x00000020 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_OFF_RADIO___S 5 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_ON_RADIO___M 0x00000010 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_ON_RADIO___S 4 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_OFF_SYNTH___M 0x00000008 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_OFF_SYNTH___S 3 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_ON_SYNTH___M 0x00000004 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_ON_SYNTH___S 2 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_OFF_PHYRF___M 0x00000002 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_OFF_PHYRF___S 1 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_ON_PHYRF___M 0x00000001 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L__TURN_ON_PHYRF___S 0 +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L___M 0x00007FFF +#define PHYA_PHYRF_PHYRF_ACTIVATION_CTRL_L___S 0 + +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_L (0x00480090) +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_L___POR 0x01000100 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_L__OFF_PWDADC___POR 0x1 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_L__ON_PWDADC___POR 0x0 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_L__OFF_PWDDAC___POR 0x1 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_L__ON_PWDDAC___POR 0x0 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_L__OFF_PWDADC___M 0x01000000 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_L__OFF_PWDADC___S 24 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_L__ON_PWDADC___M 0x00010000 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_L__ON_PWDADC___S 16 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_L__OFF_PWDDAC___M 0x00000100 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_L__OFF_PWDDAC___S 8 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_L__ON_PWDDAC___M 0x00000001 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_L__ON_PWDDAC___S 0 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_L___M 0x01010101 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_L___S 0 + +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_U (0x00480094) +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_U___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_U__RFA_DAC_RATE_OVRD_EN___POR 0x0 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_U__RFA_ADC_RATE_OVRD_EN___POR 0x0 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_U__RFA_DAC_RATE_OVRD_VAL___POR 0x0 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_U__RFA_ADC_RATE_OVRD_VAL___POR 0x0 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_U__RFA_DAC_RATE_OVRD_EN___M 0x01000000 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_U__RFA_DAC_RATE_OVRD_EN___S 24 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_U__RFA_ADC_RATE_OVRD_EN___M 0x00010000 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_U__RFA_ADC_RATE_OVRD_EN___S 16 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_U__RFA_DAC_RATE_OVRD_VAL___M 0x00000300 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_U__RFA_DAC_RATE_OVRD_VAL___S 8 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_U__RFA_ADC_RATE_OVRD_VAL___M 0x00000007 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_U__RFA_ADC_RATE_OVRD_VAL___S 0 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_U___M 0x01010307 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_0_U___S 0 + +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_1_L (0x00480098) +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_1_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_1_L___POR 0x00200000 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_1_L__RFCNTL_GEN_CONTROLS_2___POR 0x0020 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_1_L__USE_TI_ADC_CLK_RATE___POR 0x0 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_1_L__RFCNTL_GEN_CONTROLS_2___M 0xFFFF0000 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_1_L__RFCNTL_GEN_CONTROLS_2___S 16 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_1_L__USE_TI_ADC_CLK_RATE___M 0x00000001 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_1_L__USE_TI_ADC_CLK_RATE___S 0 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_1_L___M 0xFFFF0001 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_1_L___S 0 + +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_1_U (0x0048009C) +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_1_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_1_U___POR 0x00000BB8 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_1_U__DAC_BIAS_EN_TIMEOUT___POR 0xBB8 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_1_U__DAC_BIAS_EN_TIMEOUT___M 0x00000FFF +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_1_U__DAC_BIAS_EN_TIMEOUT___S 0 +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_1_U___M 0x00000FFF +#define PHYA_PHYRF_PHYRF_ADAC_CTRL_1_U___S 0 + +#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_0_L (0x004800A0) +#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_0_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_0_L___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_0_L__PHYRF_SPARES_0___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_0_L__PHYRF_SPARES_0___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_0_L__PHYRF_SPARES_0___S 0 +#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_0_L___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_0_L___S 0 + +#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_0_U (0x004800A4) +#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_0_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_0_U___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_0_U__PHYRF_SPARES_1___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_0_U__PHYRF_SPARES_1___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_0_U__PHYRF_SPARES_1___S 0 +#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_0_U___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_0_U___S 0 + +#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_1_L (0x004800A8) +#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_1_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_1_L___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_1_L__PHYRF_SPARES_2___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_1_L__PHYRF_SPARES_2___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_1_L__PHYRF_SPARES_2___S 0 +#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_1_L___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_1_L___S 0 + +#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_1_U (0x004800AC) +#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_1_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_1_U___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_1_U__PHYRF_SPARES_3___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_1_U__PHYRF_SPARES_3___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_1_U__PHYRF_SPARES_3___S 0 +#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_1_U___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_SPARE_CONTROLS_1_U___S 0 + +#define PHYA_PHYRF_TX_TIMING_1_L (0x004800B0) +#define PHYA_PHYRF_TX_TIMING_1_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TX_TIMING_1_L___POR 0x14080000 +#define PHYA_PHYRF_TX_TIMING_1_L__TX_FRAME_TO_TX_ON___POR 0x14 +#define PHYA_PHYRF_TX_TIMING_1_L__TX_FRAME_TO_DAC_ON___POR 0x08 +#define PHYA_PHYRF_TX_TIMING_1_L__TX_FRAME_TO_RX_OFF___POR 0x00 +#define PHYA_PHYRF_TX_TIMING_1_L__TX_FRAME_TO_ADC_OFF___POR 0x00 +#define PHYA_PHYRF_TX_TIMING_1_L__TX_FRAME_TO_TX_ON___M 0xFF000000 +#define PHYA_PHYRF_TX_TIMING_1_L__TX_FRAME_TO_TX_ON___S 24 +#define PHYA_PHYRF_TX_TIMING_1_L__TX_FRAME_TO_DAC_ON___M 0x00FF0000 +#define PHYA_PHYRF_TX_TIMING_1_L__TX_FRAME_TO_DAC_ON___S 16 +#define PHYA_PHYRF_TX_TIMING_1_L__TX_FRAME_TO_RX_OFF___M 0x0000FF00 +#define PHYA_PHYRF_TX_TIMING_1_L__TX_FRAME_TO_RX_OFF___S 8 +#define PHYA_PHYRF_TX_TIMING_1_L__TX_FRAME_TO_ADC_OFF___M 0x000000FF +#define PHYA_PHYRF_TX_TIMING_1_L__TX_FRAME_TO_ADC_OFF___S 0 +#define PHYA_PHYRF_TX_TIMING_1_L___M 0xFFFFFFFF +#define PHYA_PHYRF_TX_TIMING_1_L___S 0 + +#define PHYA_PHYRF_TX_TIMING_1_U (0x004800B4) +#define PHYA_PHYRF_TX_TIMING_1_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_TX_TIMING_1_U___POR 0x0C402800 +#define PHYA_PHYRF_TX_TIMING_1_U__TX_FRAME_TO_TPC_START___POR 0x0C +#define PHYA_PHYRF_TX_TIMING_1_U__TX_FRAME_TO_TXTD_START___POR 0x40 +#define PHYA_PHYRF_TX_TIMING_1_U__TX_FRAME_TO_TXGAIN___POR 0x28 +#define PHYA_PHYRF_TX_TIMING_1_U__TX_ON_STAGGER___POR 0x00 +#define PHYA_PHYRF_TX_TIMING_1_U__TX_FRAME_TO_TPC_START___M 0xFF000000 +#define PHYA_PHYRF_TX_TIMING_1_U__TX_FRAME_TO_TPC_START___S 24 +#define PHYA_PHYRF_TX_TIMING_1_U__TX_FRAME_TO_TXTD_START___M 0x00FF0000 +#define PHYA_PHYRF_TX_TIMING_1_U__TX_FRAME_TO_TXTD_START___S 16 +#define PHYA_PHYRF_TX_TIMING_1_U__TX_FRAME_TO_TXGAIN___M 0x0000FF00 +#define PHYA_PHYRF_TX_TIMING_1_U__TX_FRAME_TO_TXGAIN___S 8 +#define PHYA_PHYRF_TX_TIMING_1_U__TX_ON_STAGGER___M 0x000000FF +#define PHYA_PHYRF_TX_TIMING_1_U__TX_ON_STAGGER___S 0 +#define PHYA_PHYRF_TX_TIMING_1_U___M 0xFFFFFFFF +#define PHYA_PHYRF_TX_TIMING_1_U___S 0 + +#define PHYA_PHYRF_TX_TIMING_2_L (0x004800B8) +#define PHYA_PHYRF_TX_TIMING_2_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TX_TIMING_2_L___POR 0x28002820 +#define PHYA_PHYRF_TX_TIMING_2_L__TX_END_TO_RX_ON___POR 0x28 +#define PHYA_PHYRF_TX_TIMING_2_L__TX_END_TO_TX_OFF___POR 0x00 +#define PHYA_PHYRF_TX_TIMING_2_L__TX_END_TO_ADC_ON___POR 0x28 +#define PHYA_PHYRF_TX_TIMING_2_L__TX_END_TO_DAC_OFF___POR 0x20 +#define PHYA_PHYRF_TX_TIMING_2_L__TX_END_TO_RX_ON___M 0xFF000000 +#define PHYA_PHYRF_TX_TIMING_2_L__TX_END_TO_RX_ON___S 24 +#define PHYA_PHYRF_TX_TIMING_2_L__TX_END_TO_TX_OFF___M 0x00FF0000 +#define PHYA_PHYRF_TX_TIMING_2_L__TX_END_TO_TX_OFF___S 16 +#define PHYA_PHYRF_TX_TIMING_2_L__TX_END_TO_ADC_ON___M 0x0000FF00 +#define PHYA_PHYRF_TX_TIMING_2_L__TX_END_TO_ADC_ON___S 8 +#define PHYA_PHYRF_TX_TIMING_2_L__TX_END_TO_DAC_OFF___M 0x000000FF +#define PHYA_PHYRF_TX_TIMING_2_L__TX_END_TO_DAC_OFF___S 0 +#define PHYA_PHYRF_TX_TIMING_2_L___M 0xFFFFFFFF +#define PHYA_PHYRF_TX_TIMING_2_L___S 0 + +#define PHYA_PHYRF_TX_TIMING_2_U (0x004800BC) +#define PHYA_PHYRF_TX_TIMING_2_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_TX_TIMING_2_U___POR 0x00000004 +#define PHYA_PHYRF_TX_TIMING_2_U__PHYRF_TIMING_SPARES_3___POR 0x00 +#define PHYA_PHYRF_TX_TIMING_2_U__PHYRF_TIMING_SPARES_2___POR 0x00 +#define PHYA_PHYRF_TX_TIMING_2_U__PHYRF_TIMING_SPARES_1___POR 0x00 +#define PHYA_PHYRF_TX_TIMING_2_U__TX_END_TO_TPC_READ___POR 0x04 +#define PHYA_PHYRF_TX_TIMING_2_U__PHYRF_TIMING_SPARES_3___M 0xFF000000 +#define PHYA_PHYRF_TX_TIMING_2_U__PHYRF_TIMING_SPARES_3___S 24 +#define PHYA_PHYRF_TX_TIMING_2_U__PHYRF_TIMING_SPARES_2___M 0x00FF0000 +#define PHYA_PHYRF_TX_TIMING_2_U__PHYRF_TIMING_SPARES_2___S 16 +#define PHYA_PHYRF_TX_TIMING_2_U__PHYRF_TIMING_SPARES_1___M 0x0000FF00 +#define PHYA_PHYRF_TX_TIMING_2_U__PHYRF_TIMING_SPARES_1___S 8 +#define PHYA_PHYRF_TX_TIMING_2_U__TX_END_TO_TPC_READ___M 0x000000FF +#define PHYA_PHYRF_TX_TIMING_2_U__TX_END_TO_TPC_READ___S 0 +#define PHYA_PHYRF_TX_TIMING_2_U___M 0xFFFFFFFF +#define PHYA_PHYRF_TX_TIMING_2_U___S 0 + +#define PHYA_PHYRF_TX_TS_CTRL_L (0x004800C0) +#define PHYA_PHYRF_TX_TS_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TX_TS_CTRL_L___POR 0x7FFFFFFF +#define PHYA_PHYRF_TX_TS_CTRL_L__TXTD_START_TIMESTAMP___POR 0x7FFFFFFF +#define PHYA_PHYRF_TX_TS_CTRL_L__TXTD_START_TIMESTAMP___M 0xFFFFFFFF +#define PHYA_PHYRF_TX_TS_CTRL_L__TXTD_START_TIMESTAMP___S 0 +#define PHYA_PHYRF_TX_TS_CTRL_L___M 0xFFFFFFFF +#define PHYA_PHYRF_TX_TS_CTRL_L___S 0 + +#define PHYA_PHYRF_TXCORR_CTRL_L (0x004800C8) +#define PHYA_PHYRF_TXCORR_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TXCORR_CTRL_L___POR 0x00000000 +#define PHYA_PHYRF_TXCORR_CTRL_L__ANALOG_TX_SWAP_CNTL___POR 0x0 +#define PHYA_PHYRF_TXCORR_CTRL_L__DISABLE_CG_TXTDC_TXIQC_MEMCLK___POR 0x0 +#define PHYA_PHYRF_TXCORR_CTRL_L__DISABLE_CG_TXTDC_DPD_MEMCLK___POR 0x0 +#define PHYA_PHYRF_TXCORR_CTRL_L__DISABLE_CG_TXTDC_CLKTDAC___POR 0x0 +#define PHYA_PHYRF_TXCORR_CTRL_L__TXIQCORR_CAL_USE_SINGLE_TAP___POR 0x0 +#define PHYA_PHYRF_TXCORR_CTRL_L__TXTDC_SOFT_RESET___POR 0x0 +#define PHYA_PHYRF_TXCORR_CTRL_L__TX_CCK___POR 0x0 +#define PHYA_PHYRF_TXCORR_CTRL_L__MPI_TXTD_MU_BF___POR 0x0 +#define PHYA_PHYRF_TXCORR_CTRL_L__BW_ST___POR 0x0 +#define PHYA_PHYRF_TXCORR_CTRL_L__TX_PREEMP_FIR_EN___POR 0x0 +#define PHYA_PHYRF_TXCORR_CTRL_L__ANALOG_TX_SWAP_CNTL___M 0x00003800 +#define PHYA_PHYRF_TXCORR_CTRL_L__ANALOG_TX_SWAP_CNTL___S 11 +#define PHYA_PHYRF_TXCORR_CTRL_L__DISABLE_CG_TXTDC_TXIQC_MEMCLK___M 0x00000400 +#define PHYA_PHYRF_TXCORR_CTRL_L__DISABLE_CG_TXTDC_TXIQC_MEMCLK___S 10 +#define PHYA_PHYRF_TXCORR_CTRL_L__DISABLE_CG_TXTDC_DPD_MEMCLK___M 0x00000200 +#define PHYA_PHYRF_TXCORR_CTRL_L__DISABLE_CG_TXTDC_DPD_MEMCLK___S 9 +#define PHYA_PHYRF_TXCORR_CTRL_L__DISABLE_CG_TXTDC_CLKTDAC___M 0x00000100 +#define PHYA_PHYRF_TXCORR_CTRL_L__DISABLE_CG_TXTDC_CLKTDAC___S 8 +#define PHYA_PHYRF_TXCORR_CTRL_L__TXIQCORR_CAL_USE_SINGLE_TAP___M 0x00000080 +#define PHYA_PHYRF_TXCORR_CTRL_L__TXIQCORR_CAL_USE_SINGLE_TAP___S 7 +#define PHYA_PHYRF_TXCORR_CTRL_L__TXTDC_SOFT_RESET___M 0x00000040 +#define PHYA_PHYRF_TXCORR_CTRL_L__TXTDC_SOFT_RESET___S 6 +#define PHYA_PHYRF_TXCORR_CTRL_L__TX_CCK___M 0x00000020 +#define PHYA_PHYRF_TXCORR_CTRL_L__TX_CCK___S 5 +#define PHYA_PHYRF_TXCORR_CTRL_L__MPI_TXTD_MU_BF___M 0x00000010 +#define PHYA_PHYRF_TXCORR_CTRL_L__MPI_TXTD_MU_BF___S 4 +#define PHYA_PHYRF_TXCORR_CTRL_L__BW_ST___M 0x0000000E +#define PHYA_PHYRF_TXCORR_CTRL_L__BW_ST___S 1 +#define PHYA_PHYRF_TXCORR_CTRL_L__TX_PREEMP_FIR_EN___M 0x00000001 +#define PHYA_PHYRF_TXCORR_CTRL_L__TX_PREEMP_FIR_EN___S 0 +#define PHYA_PHYRF_TXCORR_CTRL_L___M 0x00003FFF +#define PHYA_PHYRF_TXCORR_CTRL_L___S 0 + +#define PHYA_PHYRF_TXCORR_CTRL_U (0x004800CC) +#define PHYA_PHYRF_TXCORR_CTRL_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_TXCORR_CTRL_U___POR 0x00000000 +#define PHYA_PHYRF_TXCORR_CTRL_U__TXTDC_SPARE_CTRL___POR 0x00000000 +#define PHYA_PHYRF_TXCORR_CTRL_U__TXTDC_SPARE_CTRL___M 0xFFFFFFFF +#define PHYA_PHYRF_TXCORR_CTRL_U__TXTDC_SPARE_CTRL___S 0 +#define PHYA_PHYRF_TXCORR_CTRL_U___M 0xFFFFFFFF +#define PHYA_PHYRF_TXCORR_CTRL_U___S 0 + +#define PHYA_PHYRF_TXCORR_OVRD_CTRL_L (0x004800D0) +#define PHYA_PHYRF_TXCORR_OVRD_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TXCORR_OVRD_CTRL_L___POR 0x00000000 +#define PHYA_PHYRF_TXCORR_OVRD_CTRL_L__SEL_EXT80_TABLES_OVRD_VAL___POR 0x0 +#define PHYA_PHYRF_TXCORR_OVRD_CTRL_L__SEL_EXT80_TABLES_OVRD_EN___POR 0x0 +#define PHYA_PHYRF_TXCORR_OVRD_CTRL_L__TX_MCS_OVRD_VAL___POR 0x000 +#define PHYA_PHYRF_TXCORR_OVRD_CTRL_L__TX_MCS_OVRD_EN___POR 0x0 +#define PHYA_PHYRF_TXCORR_OVRD_CTRL_L__TX_NSS_OVRD_VAL___POR 0x0 +#define PHYA_PHYRF_TXCORR_OVRD_CTRL_L__TX_NSS_OVRD_EN___POR 0x0 +#define PHYA_PHYRF_TXCORR_OVRD_CTRL_L__DPD_ENABLE_OVRD_VAL___POR 0x0 +#define PHYA_PHYRF_TXCORR_OVRD_CTRL_L__DPD_ENABLE_OVRD_EN___POR 0x0 +#define PHYA_PHYRF_TXCORR_OVRD_CTRL_L__SEL_EXT80_TABLES_OVRD_VAL___M 0x00020000 +#define PHYA_PHYRF_TXCORR_OVRD_CTRL_L__SEL_EXT80_TABLES_OVRD_VAL___S 17 +#define PHYA_PHYRF_TXCORR_OVRD_CTRL_L__SEL_EXT80_TABLES_OVRD_EN___M 0x00010000 +#define PHYA_PHYRF_TXCORR_OVRD_CTRL_L__SEL_EXT80_TABLES_OVRD_EN___S 16 +#define PHYA_PHYRF_TXCORR_OVRD_CTRL_L__TX_MCS_OVRD_VAL___M 0x0000FFC0 +#define PHYA_PHYRF_TXCORR_OVRD_CTRL_L__TX_MCS_OVRD_VAL___S 6 +#define PHYA_PHYRF_TXCORR_OVRD_CTRL_L__TX_MCS_OVRD_EN___M 0x00000020 +#define PHYA_PHYRF_TXCORR_OVRD_CTRL_L__TX_MCS_OVRD_EN___S 5 +#define PHYA_PHYRF_TXCORR_OVRD_CTRL_L__TX_NSS_OVRD_VAL___M 0x00000018 +#define PHYA_PHYRF_TXCORR_OVRD_CTRL_L__TX_NSS_OVRD_VAL___S 3 +#define PHYA_PHYRF_TXCORR_OVRD_CTRL_L__TX_NSS_OVRD_EN___M 0x00000004 +#define PHYA_PHYRF_TXCORR_OVRD_CTRL_L__TX_NSS_OVRD_EN___S 2 +#define PHYA_PHYRF_TXCORR_OVRD_CTRL_L__DPD_ENABLE_OVRD_VAL___M 0x00000002 +#define PHYA_PHYRF_TXCORR_OVRD_CTRL_L__DPD_ENABLE_OVRD_VAL___S 1 +#define PHYA_PHYRF_TXCORR_OVRD_CTRL_L__DPD_ENABLE_OVRD_EN___M 0x00000001 +#define PHYA_PHYRF_TXCORR_OVRD_CTRL_L__DPD_ENABLE_OVRD_EN___S 0 +#define PHYA_PHYRF_TXCORR_OVRD_CTRL_L___M 0x0003FFFF +#define PHYA_PHYRF_TXCORR_OVRD_CTRL_L___S 0 + +#define PHYA_PHYRF_PAPRD_RATE_MASK_L (0x004800D8) +#define PHYA_PHYRF_PAPRD_RATE_MASK_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_PAPRD_RATE_MASK_L___POR 0x7FFFFFFF +#define PHYA_PHYRF_PAPRD_RATE_MASK_L__PAPRD_RATE_MASK___POR 0x7FFFFFFF +#define PHYA_PHYRF_PAPRD_RATE_MASK_L__PAPRD_RATE_MASK___M 0x7FFFFFFF +#define PHYA_PHYRF_PAPRD_RATE_MASK_L__PAPRD_RATE_MASK___S 0 +#define PHYA_PHYRF_PAPRD_RATE_MASK_L___M 0x7FFFFFFF +#define PHYA_PHYRF_PAPRD_RATE_MASK_L___S 0 + +#define PHYA_PHYRF_PREEMP_MASK_L (0x004800E0) +#define PHYA_PHYRF_PREEMP_MASK_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_PREEMP_MASK_L___POR 0x00000000 +#define PHYA_PHYRF_PREEMP_MASK_L__PREEMP_MASK___POR 0x00000000 +#define PHYA_PHYRF_PREEMP_MASK_L__PREEMP_MASK___M 0x7FFFFFFF +#define PHYA_PHYRF_PREEMP_MASK_L__PREEMP_MASK___S 0 +#define PHYA_PHYRF_PREEMP_MASK_L___M 0x7FFFFFFF +#define PHYA_PHYRF_PREEMP_MASK_L___S 0 + +#define PHYA_PHYRF_PDC_CTRL_L (0x004800E8) +#define PHYA_PHYRF_PDC_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_PDC_CTRL_L___POR 0x00020001 +#define PHYA_PHYRF_PDC_CTRL_L__PDC_GAP_IDX_OVRD_VAL___POR 0x2 +#define PHYA_PHYRF_PDC_CTRL_L__PDC_GAP_IDX_OVRD_EN___POR 0x0 +#define PHYA_PHYRF_PDC_CTRL_L__PDC_DISABLE___POR 0x1 +#define PHYA_PHYRF_PDC_CTRL_L__PDC_GAP_IDX_OVRD_VAL___M 0x00030000 +#define PHYA_PHYRF_PDC_CTRL_L__PDC_GAP_IDX_OVRD_VAL___S 16 +#define PHYA_PHYRF_PDC_CTRL_L__PDC_GAP_IDX_OVRD_EN___M 0x00000100 +#define PHYA_PHYRF_PDC_CTRL_L__PDC_GAP_IDX_OVRD_EN___S 8 +#define PHYA_PHYRF_PDC_CTRL_L__PDC_DISABLE___M 0x00000001 +#define PHYA_PHYRF_PDC_CTRL_L__PDC_DISABLE___S 0 +#define PHYA_PHYRF_PDC_CTRL_L___M 0x00030101 +#define PHYA_PHYRF_PDC_CTRL_L___S 0 + +#define PHYA_PHYRF_PDC_CTRL_U (0x004800EC) +#define PHYA_PHYRF_PDC_CTRL_U___RWC QCSR_REG_RO +#define PHYA_PHYRF_PDC_CTRL_U___POR 0x00000000 +#define PHYA_PHYRF_PDC_CTRL_U__PDC_GAP_TIMER___POR 0x00000000 +#define PHYA_PHYRF_PDC_CTRL_U__PDC_GAP_TIMER___M 0xFFFFFFFF +#define PHYA_PHYRF_PDC_CTRL_U__PDC_GAP_TIMER___S 0 +#define PHYA_PHYRF_PDC_CTRL_U___M 0xFFFFFFFF +#define PHYA_PHYRF_PDC_CTRL_U___S 0 + +#define PHYA_PHYRF_PDC_GAP_THR_L (0x004800F0) +#define PHYA_PHYRF_PDC_GAP_THR_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_PDC_GAP_THR_L___POR 0x00000000 +#define PHYA_PHYRF_PDC_GAP_THR_L__PDC_GAP_TH1___POR 0x00000000 +#define PHYA_PHYRF_PDC_GAP_THR_L__PDC_GAP_TH1___M 0xFFFFFFFF +#define PHYA_PHYRF_PDC_GAP_THR_L__PDC_GAP_TH1___S 0 +#define PHYA_PHYRF_PDC_GAP_THR_L___M 0xFFFFFFFF +#define PHYA_PHYRF_PDC_GAP_THR_L___S 0 + +#define PHYA_PHYRF_PDC_GAP_THR_U (0x004800F4) +#define PHYA_PHYRF_PDC_GAP_THR_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_PDC_GAP_THR_U___POR 0x00000000 +#define PHYA_PHYRF_PDC_GAP_THR_U__PDC_GAP_TH2___POR 0x00000000 +#define PHYA_PHYRF_PDC_GAP_THR_U__PDC_GAP_TH2___M 0xFFFFFFFF +#define PHYA_PHYRF_PDC_GAP_THR_U__PDC_GAP_TH2___S 0 +#define PHYA_PHYRF_PDC_GAP_THR_U___M 0xFFFFFFFF +#define PHYA_PHYRF_PDC_GAP_THR_U___S 0 + +#define PHYA_PHYRF_PDC_GAP_THR_MAX_L (0x004800F8) +#define PHYA_PHYRF_PDC_GAP_THR_MAX_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_PDC_GAP_THR_MAX_L___POR 0x00000000 +#define PHYA_PHYRF_PDC_GAP_THR_MAX_L__PDC_GAP_MAX_THR___POR 0x00000000 +#define PHYA_PHYRF_PDC_GAP_THR_MAX_L__PDC_GAP_MAX_THR___M 0xFFFFFFFF +#define PHYA_PHYRF_PDC_GAP_THR_MAX_L__PDC_GAP_MAX_THR___S 0 +#define PHYA_PHYRF_PDC_GAP_THR_MAX_L___M 0xFFFFFFFF +#define PHYA_PHYRF_PDC_GAP_THR_MAX_L___S 0 + +#define PHYA_PHYRF_PDC_COMP_START_L (0x00480100) +#define PHYA_PHYRF_PDC_COMP_START_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_PDC_COMP_START_L___POR 0x00000000 +#define PHYA_PHYRF_PDC_COMP_START_L__PDC_DROOP_COMP_START___POR 0x00000000 +#define PHYA_PHYRF_PDC_COMP_START_L__PDC_DROOP_COMP_START___M 0xFFFFFFFF +#define PHYA_PHYRF_PDC_COMP_START_L__PDC_DROOP_COMP_START___S 0 +#define PHYA_PHYRF_PDC_COMP_START_L___M 0xFFFFFFFF +#define PHYA_PHYRF_PDC_COMP_START_L___S 0 + +#define PHYA_PHYRF_IMP_CTRL_L (0x00480108) +#define PHYA_PHYRF_IMP_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_IMP_CTRL_L___POR 0x00000088 +#define PHYA_PHYRF_IMP_CTRL_L__LPC_FILTER_CPS_SHIFT___POR 0x2 +#define PHYA_PHYRF_IMP_CTRL_L__LPC_FILTER_EN___POR 0x0 +#define PHYA_PHYRF_IMP_CTRL_L__USE_DAC_CL_CORRECTION___POR 0x0 +#define PHYA_PHYRF_IMP_CTRL_L__TX_IQCORR_COEF_SHIFT___POR 0x2 +#define PHYA_PHYRF_IMP_CTRL_L__SEL_ALT_TABLES___POR 0x0 +#define PHYA_PHYRF_IMP_CTRL_L__TX_IQCORR_EN___POR 0x0 +#define PHYA_PHYRF_IMP_CTRL_L__LPC_FILTER_CPS_SHIFT___M 0x000000C0 +#define PHYA_PHYRF_IMP_CTRL_L__LPC_FILTER_CPS_SHIFT___S 6 +#define PHYA_PHYRF_IMP_CTRL_L__LPC_FILTER_EN___M 0x00000020 +#define PHYA_PHYRF_IMP_CTRL_L__LPC_FILTER_EN___S 5 +#define PHYA_PHYRF_IMP_CTRL_L__USE_DAC_CL_CORRECTION___M 0x00000010 +#define PHYA_PHYRF_IMP_CTRL_L__USE_DAC_CL_CORRECTION___S 4 +#define PHYA_PHYRF_IMP_CTRL_L__TX_IQCORR_COEF_SHIFT___M 0x0000000C +#define PHYA_PHYRF_IMP_CTRL_L__TX_IQCORR_COEF_SHIFT___S 2 +#define PHYA_PHYRF_IMP_CTRL_L__SEL_ALT_TABLES___M 0x00000002 +#define PHYA_PHYRF_IMP_CTRL_L__SEL_ALT_TABLES___S 1 +#define PHYA_PHYRF_IMP_CTRL_L__TX_IQCORR_EN___M 0x00000001 +#define PHYA_PHYRF_IMP_CTRL_L__TX_IQCORR_EN___S 0 +#define PHYA_PHYRF_IMP_CTRL_L___M 0x000000FF +#define PHYA_PHYRF_IMP_CTRL_L___S 0 + +#define PHYA_PHYRF_TXTDC_DEBUG_L (0x00480110) +#define PHYA_PHYRF_TXTDC_DEBUG_L___RWC QCSR_REG_RO +#define PHYA_PHYRF_TXTDC_DEBUG_L___POR 0x00000000 +#define PHYA_PHYRF_TXTDC_DEBUG_L__TXTDC_CMN_STATUS___POR 0x00000000 +#define PHYA_PHYRF_TXTDC_DEBUG_L__TXTDC_CMN_STATUS___M 0xFFFFFFFF +#define PHYA_PHYRF_TXTDC_DEBUG_L__TXTDC_CMN_STATUS___S 0 +#define PHYA_PHYRF_TXTDC_DEBUG_L___M 0xFFFFFFFF +#define PHYA_PHYRF_TXTDC_DEBUG_L___S 0 + +#define PHYA_PHYRF_TXTDC_DEBUG_U (0x00480114) +#define PHYA_PHYRF_TXTDC_DEBUG_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_TXTDC_DEBUG_U___POR 0x0000000F +#define PHYA_PHYRF_TXTDC_DEBUG_U__TXTDC_DUMP_CHN1_SEL___POR 0x0 +#define PHYA_PHYRF_TXTDC_DEBUG_U__TXTDC_DUMP_CHN0_SEL___POR 0x0 +#define PHYA_PHYRF_TXTDC_DEBUG_U__TXTDC_DUMP_PREC___POR 0x0 +#define PHYA_PHYRF_TXTDC_DEBUG_U__TXTDC_DUMP_MODE___POR 0x0 +#define PHYA_PHYRF_TXTDC_DEBUG_U__TXTDC_DUMP_POINT___POR 0xF +#define PHYA_PHYRF_TXTDC_DEBUG_U__TXTDC_DUMP_CHN1_SEL___M 0x00001800 +#define PHYA_PHYRF_TXTDC_DEBUG_U__TXTDC_DUMP_CHN1_SEL___S 11 +#define PHYA_PHYRF_TXTDC_DEBUG_U__TXTDC_DUMP_CHN0_SEL___M 0x00000600 +#define PHYA_PHYRF_TXTDC_DEBUG_U__TXTDC_DUMP_CHN0_SEL___S 9 +#define PHYA_PHYRF_TXTDC_DEBUG_U__TXTDC_DUMP_PREC___M 0x00000180 +#define PHYA_PHYRF_TXTDC_DEBUG_U__TXTDC_DUMP_PREC___S 7 +#define PHYA_PHYRF_TXTDC_DEBUG_U__TXTDC_DUMP_MODE___M 0x00000070 +#define PHYA_PHYRF_TXTDC_DEBUG_U__TXTDC_DUMP_MODE___S 4 +#define PHYA_PHYRF_TXTDC_DEBUG_U__TXTDC_DUMP_POINT___M 0x0000000F +#define PHYA_PHYRF_TXTDC_DEBUG_U__TXTDC_DUMP_POINT___S 0 +#define PHYA_PHYRF_TXTDC_DEBUG_U___M 0x00001FFF +#define PHYA_PHYRF_TXTDC_DEBUG_U___S 0 + +#define PHYA_PHYRF_RXCORR_CTRL_0_L (0x00480118) +#define PHYA_PHYRF_RXCORR_CTRL_0_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXCORR_CTRL_0_L___POR 0x00000000 +#define PHYA_PHYRF_RXCORR_CTRL_0_L__RXCORR_ADC_GAIN_ENA___POR 0x0 +#define PHYA_PHYRF_RXCORR_CTRL_0_L__RXCORR_RES_DC_ENABLE___POR 0x0 +#define PHYA_PHYRF_RXCORR_CTRL_0_L__RXCORR_PHASE_COMP_ENA___POR 0x0 +#define PHYA_PHYRF_RXCORR_CTRL_0_L__RXCORR_IQCORR_ENABLE___POR 0x0 +#define PHYA_PHYRF_RXCORR_CTRL_0_L__RXCORR_ADC_GAIN_ENA___M 0x01000000 +#define PHYA_PHYRF_RXCORR_CTRL_0_L__RXCORR_ADC_GAIN_ENA___S 24 +#define PHYA_PHYRF_RXCORR_CTRL_0_L__RXCORR_RES_DC_ENABLE___M 0x00010000 +#define PHYA_PHYRF_RXCORR_CTRL_0_L__RXCORR_RES_DC_ENABLE___S 16 +#define PHYA_PHYRF_RXCORR_CTRL_0_L__RXCORR_PHASE_COMP_ENA___M 0x00000100 +#define PHYA_PHYRF_RXCORR_CTRL_0_L__RXCORR_PHASE_COMP_ENA___S 8 +#define PHYA_PHYRF_RXCORR_CTRL_0_L__RXCORR_IQCORR_ENABLE___M 0x00000001 +#define PHYA_PHYRF_RXCORR_CTRL_0_L__RXCORR_IQCORR_ENABLE___S 0 +#define PHYA_PHYRF_RXCORR_CTRL_0_L___M 0x01010101 +#define PHYA_PHYRF_RXCORR_CTRL_0_L___S 0 + +#define PHYA_PHYRF_RXCORR_CTRL_0_U (0x0048011C) +#define PHYA_PHYRF_RXCORR_CTRL_0_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXCORR_CTRL_0_U___POR 0x02020000 +#define PHYA_PHYRF_RXCORR_CTRL_0_U__RXCORR_IQCORR_SHIFT___POR 0x2 +#define PHYA_PHYRF_RXCORR_CTRL_0_U__RXCORR_PHASE_COMP_SHIFT___POR 0x2 +#define PHYA_PHYRF_RXCORR_CTRL_0_U__RXCORR_ENA_BW_MODE_SEL___POR 0x0 +#define PHYA_PHYRF_RXCORR_CTRL_0_U__RXCORR_ADC_DC_ENA___POR 0x0 +#define PHYA_PHYRF_RXCORR_CTRL_0_U__RXCORR_IQCORR_SHIFT___M 0x03000000 +#define PHYA_PHYRF_RXCORR_CTRL_0_U__RXCORR_IQCORR_SHIFT___S 24 +#define PHYA_PHYRF_RXCORR_CTRL_0_U__RXCORR_PHASE_COMP_SHIFT___M 0x00030000 +#define PHYA_PHYRF_RXCORR_CTRL_0_U__RXCORR_PHASE_COMP_SHIFT___S 16 +#define PHYA_PHYRF_RXCORR_CTRL_0_U__RXCORR_ENA_BW_MODE_SEL___M 0x00000100 +#define PHYA_PHYRF_RXCORR_CTRL_0_U__RXCORR_ENA_BW_MODE_SEL___S 8 +#define PHYA_PHYRF_RXCORR_CTRL_0_U__RXCORR_ADC_DC_ENA___M 0x00000001 +#define PHYA_PHYRF_RXCORR_CTRL_0_U__RXCORR_ADC_DC_ENA___S 0 +#define PHYA_PHYRF_RXCORR_CTRL_0_U___M 0x03030101 +#define PHYA_PHYRF_RXCORR_CTRL_0_U___S 0 + +#define PHYA_PHYRF_RXCORR_CTRL_1_L (0x00480120) +#define PHYA_PHYRF_RXCORR_CTRL_1_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXCORR_CTRL_1_L___POR 0x00000400 +#define PHYA_PHYRF_RXCORR_CTRL_1_L__ENABLE_ONETAP_IN_SRCH___POR 0x0 +#define PHYA_PHYRF_RXCORR_CTRL_1_L__RXCORR_DTIM_USE_SINGLETAP___POR 0x0 +#define PHYA_PHYRF_RXCORR_CTRL_1_L__RXCORR_IQCORR_CENTER_TAP___POR 0x4 +#define PHYA_PHYRF_RXCORR_CTRL_1_L__RXCORR_IQCORR_USE_ONETAP___POR 0x0 +#define PHYA_PHYRF_RXCORR_CTRL_1_L__ENABLE_ONETAP_IN_SRCH___M 0x01000000 +#define PHYA_PHYRF_RXCORR_CTRL_1_L__ENABLE_ONETAP_IN_SRCH___S 24 +#define PHYA_PHYRF_RXCORR_CTRL_1_L__RXCORR_DTIM_USE_SINGLETAP___M 0x00010000 +#define PHYA_PHYRF_RXCORR_CTRL_1_L__RXCORR_DTIM_USE_SINGLETAP___S 16 +#define PHYA_PHYRF_RXCORR_CTRL_1_L__RXCORR_IQCORR_CENTER_TAP___M 0x00000F00 +#define PHYA_PHYRF_RXCORR_CTRL_1_L__RXCORR_IQCORR_CENTER_TAP___S 8 +#define PHYA_PHYRF_RXCORR_CTRL_1_L__RXCORR_IQCORR_USE_ONETAP___M 0x00000001 +#define PHYA_PHYRF_RXCORR_CTRL_1_L__RXCORR_IQCORR_USE_ONETAP___S 0 +#define PHYA_PHYRF_RXCORR_CTRL_1_L___M 0x01010F01 +#define PHYA_PHYRF_RXCORR_CTRL_1_L___S 0 + +#define PHYA_PHYRF_RXCORR_CTRL_1_U (0x00480124) +#define PHYA_PHYRF_RXCORR_CTRL_1_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXCORR_CTRL_1_U___POR 0x00000000 +#define PHYA_PHYRF_RXCORR_CTRL_1_U__RXCORR_SPARE2___POR 0x0 +#define PHYA_PHYRF_RXCORR_CTRL_1_U__RXCORR_SPARE2___M 0x00000001 +#define PHYA_PHYRF_RXCORR_CTRL_1_U__RXCORR_SPARE2___S 0 +#define PHYA_PHYRF_RXCORR_CTRL_1_U___M 0x00000001 +#define PHYA_PHYRF_RXCORR_CTRL_1_U___S 0 + +#define PHYA_PHYRF_RXXBAR_L (0x00480128) +#define PHYA_PHYRF_RXXBAR_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXXBAR_L___POR 0x00FAC688 +#define PHYA_PHYRF_RXXBAR_L__RX_XBAR_CTRL___POR 0xFAC688 +#define PHYA_PHYRF_RXXBAR_L__RX_XBAR_CTRL___M 0x00FFFFFF +#define PHYA_PHYRF_RXXBAR_L__RX_XBAR_CTRL___S 0 +#define PHYA_PHYRF_RXXBAR_L___M 0x00FFFFFF +#define PHYA_PHYRF_RXXBAR_L___S 0 + +#define PHYA_PHYRF_TXXBAR_L (0x00480130) +#define PHYA_PHYRF_TXXBAR_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TXXBAR_L___POR 0x01F58D10 +#define PHYA_PHYRF_TXXBAR_L__TX_XBAR_CTRL_OVRD_VAL___POR 0xFAC688 +#define PHYA_PHYRF_TXXBAR_L__TX_XBAR_CTRL_OVRD_EN___POR 0x0 +#define PHYA_PHYRF_TXXBAR_L__TX_XBAR_CTRL_OVRD_VAL___M 0x01FFFFFE +#define PHYA_PHYRF_TXXBAR_L__TX_XBAR_CTRL_OVRD_VAL___S 1 +#define PHYA_PHYRF_TXXBAR_L__TX_XBAR_CTRL_OVRD_EN___M 0x00000001 +#define PHYA_PHYRF_TXXBAR_L__TX_XBAR_CTRL_OVRD_EN___S 0 +#define PHYA_PHYRF_TXXBAR_L___M 0x01FFFFFF +#define PHYA_PHYRF_TXXBAR_L___S 0 + +#define PHYA_PHYRF_TPC_GEN_CTRL_L (0x00480138) +#define PHYA_PHYRF_TPC_GEN_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_GEN_CTRL_L___POR 0x05439E00 +#define PHYA_PHYRF_TPC_GEN_CTRL_L__TARGET_PWR_CLPC_THR_CORR___POR 0x0A +#define PHYA_PHYRF_TPC_GEN_CTRL_L__TPC_CL_PKT_THR___POR 0x10 +#define PHYA_PHYRF_TPC_GEN_CTRL_L__MIN_MAX_METHOD___POR 0x1 +#define PHYA_PHYRF_TPC_GEN_CTRL_L__TPC_CLK_GATE_ENABLE___POR 0x1 +#define PHYA_PHYRF_TPC_GEN_CTRL_L__TPC_TXGAIN_TBL_FCS_CONTROL___POR 0x1 +#define PHYA_PHYRF_TPC_GEN_CTRL_L__TX_GAIN_TABLE_MAX___POR 0x0F +#define PHYA_PHYRF_TPC_GEN_CTRL_L__TPC_MU_ENABLE___POR 0x0 +#define PHYA_PHYRF_TPC_GEN_CTRL_L__DISABLE_TPC_RFA_CTRL___POR 0x0 +#define PHYA_PHYRF_TPC_GEN_CTRL_L__TPC_DBG_BUS_SEL___POR 0x0 +#define PHYA_PHYRF_TPC_GEN_CTRL_L__MEAS_PWR_SW___POR 0x0 +#define PHYA_PHYRF_TPC_GEN_CTRL_L__CALC_GAIN_TRIG_SW___POR 0x0 +#define PHYA_PHYRF_TPC_GEN_CTRL_L__OLPC_MODE___POR 0x0 +#define PHYA_PHYRF_TPC_GEN_CTRL_L__TARGET_PWR_CLPC_THR_CORR___M 0x7F800000 +#define PHYA_PHYRF_TPC_GEN_CTRL_L__TARGET_PWR_CLPC_THR_CORR___S 23 +#define PHYA_PHYRF_TPC_GEN_CTRL_L__TPC_CL_PKT_THR___M 0x007C0000 +#define PHYA_PHYRF_TPC_GEN_CTRL_L__TPC_CL_PKT_THR___S 18 +#define PHYA_PHYRF_TPC_GEN_CTRL_L__MIN_MAX_METHOD___M 0x00020000 +#define PHYA_PHYRF_TPC_GEN_CTRL_L__MIN_MAX_METHOD___S 17 +#define PHYA_PHYRF_TPC_GEN_CTRL_L__TPC_CLK_GATE_ENABLE___M 0x00010000 +#define PHYA_PHYRF_TPC_GEN_CTRL_L__TPC_CLK_GATE_ENABLE___S 16 +#define PHYA_PHYRF_TPC_GEN_CTRL_L__TPC_TXGAIN_TBL_FCS_CONTROL___M 0x00008000 +#define PHYA_PHYRF_TPC_GEN_CTRL_L__TPC_TXGAIN_TBL_FCS_CONTROL___S 15 +#define PHYA_PHYRF_TPC_GEN_CTRL_L__TX_GAIN_TABLE_MAX___M 0x00007E00 +#define PHYA_PHYRF_TPC_GEN_CTRL_L__TX_GAIN_TABLE_MAX___S 9 +#define PHYA_PHYRF_TPC_GEN_CTRL_L__TPC_MU_ENABLE___M 0x00000100 +#define PHYA_PHYRF_TPC_GEN_CTRL_L__TPC_MU_ENABLE___S 8 +#define PHYA_PHYRF_TPC_GEN_CTRL_L__DISABLE_TPC_RFA_CTRL___M 0x00000080 +#define PHYA_PHYRF_TPC_GEN_CTRL_L__DISABLE_TPC_RFA_CTRL___S 7 +#define PHYA_PHYRF_TPC_GEN_CTRL_L__TPC_DBG_BUS_SEL___M 0x00000078 +#define PHYA_PHYRF_TPC_GEN_CTRL_L__TPC_DBG_BUS_SEL___S 3 +#define PHYA_PHYRF_TPC_GEN_CTRL_L__MEAS_PWR_SW___M 0x00000004 +#define PHYA_PHYRF_TPC_GEN_CTRL_L__MEAS_PWR_SW___S 2 +#define PHYA_PHYRF_TPC_GEN_CTRL_L__CALC_GAIN_TRIG_SW___M 0x00000002 +#define PHYA_PHYRF_TPC_GEN_CTRL_L__CALC_GAIN_TRIG_SW___S 1 +#define PHYA_PHYRF_TPC_GEN_CTRL_L__OLPC_MODE___M 0x00000001 +#define PHYA_PHYRF_TPC_GEN_CTRL_L__OLPC_MODE___S 0 +#define PHYA_PHYRF_TPC_GEN_CTRL_L___M 0x7FFFFFFF +#define PHYA_PHYRF_TPC_GEN_CTRL_L___S 0 + +#define PHYA_PHYRF_TPC_GEN_CTRL_U (0x0048013C) +#define PHYA_PHYRF_TPC_GEN_CTRL_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_GEN_CTRL_U___POR 0x0000020A +#define PHYA_PHYRF_TPC_GEN_CTRL_U__WSI_TIMEOUT___POR 0x00 +#define PHYA_PHYRF_TPC_GEN_CTRL_U__CF_TX_DAC_SCALE_CCK___POR 0x0 +#define PHYA_PHYRF_TPC_GEN_CTRL_U__CF_RFBMODE___POR 0x0 +#define PHYA_PHYRF_TPC_GEN_CTRL_U__CF_TX_CLIP___POR 0x0 +#define PHYA_PHYRF_TPC_GEN_CTRL_U__USE_DCSR_FOR_TPC_END___POR 0x0 +#define PHYA_PHYRF_TPC_GEN_CTRL_U__USE_DCSR_FOR_TPC_GAIN_SEND___POR 0x0 +#define PHYA_PHYRF_TPC_GEN_CTRL_U__USE_DCSR_FOR_TPC_START___POR 0x0 +#define PHYA_PHYRF_TPC_GEN_CTRL_U__TPC_PWR_SHARED_CHAIN_MASK___POR 0x1 +#define PHYA_PHYRF_TPC_GEN_CTRL_U__TPC_IGNORE_BT_IN_TX___POR 0x0 +#define PHYA_PHYRF_TPC_GEN_CTRL_U__TARGET_PWR_CLPC_THR_UPDATE___POR 0x0A +#define PHYA_PHYRF_TPC_GEN_CTRL_U__WSI_TIMEOUT___M 0x0FC00000 +#define PHYA_PHYRF_TPC_GEN_CTRL_U__WSI_TIMEOUT___S 22 +#define PHYA_PHYRF_TPC_GEN_CTRL_U__CF_TX_DAC_SCALE_CCK___M 0x00300000 +#define PHYA_PHYRF_TPC_GEN_CTRL_U__CF_TX_DAC_SCALE_CCK___S 20 +#define PHYA_PHYRF_TPC_GEN_CTRL_U__CF_RFBMODE___M 0x00080000 +#define PHYA_PHYRF_TPC_GEN_CTRL_U__CF_RFBMODE___S 19 +#define PHYA_PHYRF_TPC_GEN_CTRL_U__CF_TX_CLIP___M 0x00070000 +#define PHYA_PHYRF_TPC_GEN_CTRL_U__CF_TX_CLIP___S 16 +#define PHYA_PHYRF_TPC_GEN_CTRL_U__USE_DCSR_FOR_TPC_END___M 0x00008000 +#define PHYA_PHYRF_TPC_GEN_CTRL_U__USE_DCSR_FOR_TPC_END___S 15 +#define PHYA_PHYRF_TPC_GEN_CTRL_U__USE_DCSR_FOR_TPC_GAIN_SEND___M 0x00004000 +#define PHYA_PHYRF_TPC_GEN_CTRL_U__USE_DCSR_FOR_TPC_GAIN_SEND___S 14 +#define PHYA_PHYRF_TPC_GEN_CTRL_U__USE_DCSR_FOR_TPC_START___M 0x00002000 +#define PHYA_PHYRF_TPC_GEN_CTRL_U__USE_DCSR_FOR_TPC_START___S 13 +#define PHYA_PHYRF_TPC_GEN_CTRL_U__TPC_PWR_SHARED_CHAIN_MASK___M 0x00001E00 +#define PHYA_PHYRF_TPC_GEN_CTRL_U__TPC_PWR_SHARED_CHAIN_MASK___S 9 +#define PHYA_PHYRF_TPC_GEN_CTRL_U__TPC_IGNORE_BT_IN_TX___M 0x00000100 +#define PHYA_PHYRF_TPC_GEN_CTRL_U__TPC_IGNORE_BT_IN_TX___S 8 +#define PHYA_PHYRF_TPC_GEN_CTRL_U__TARGET_PWR_CLPC_THR_UPDATE___M 0x000000FF +#define PHYA_PHYRF_TPC_GEN_CTRL_U__TARGET_PWR_CLPC_THR_UPDATE___S 0 +#define PHYA_PHYRF_TPC_GEN_CTRL_U___M 0x0FFFFFFF +#define PHYA_PHYRF_TPC_GEN_CTRL_U___S 0 + +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_L (0x00480140) +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_L___POR 0x00800190 +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_L__TPC_ALUT_BASE___POR 0x80 +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_L__CLPC_PKT_DUR_THR___POR 0x0064 +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_L__MASK_OUT_CLPC_ERR_UPDATE___POR 0x0 +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_L__CLPC_ERR_UPDATE_DIS___POR 0x0 +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_L__TPC_ALUT_BASE___M 0x00FF0000 +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_L__TPC_ALUT_BASE___S 16 +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_L__CLPC_PKT_DUR_THR___M 0x0000FFFC +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_L__CLPC_PKT_DUR_THR___S 2 +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_L__MASK_OUT_CLPC_ERR_UPDATE___M 0x00000002 +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_L__MASK_OUT_CLPC_ERR_UPDATE___S 1 +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_L__CLPC_ERR_UPDATE_DIS___M 0x00000001 +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_L__CLPC_ERR_UPDATE_DIS___S 0 +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_L___M 0x00FFFFFF +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_L___S 0 + +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_U (0x00480144) +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_U___POR 0x01210000 +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_U__TPC_CL_ERR_SCALE_STG0___POR 0x04 +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLPC_ERR_CMN_IGNORE_AFTER_DUP___POR 0x1 +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLPC_ERR_CMN_PKT_THR___POR 0x08 +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLPC_ERR_CMN_DUP_EN___POR 0x0 +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLEAR_ALL_CLPC_ERROR_DONE___POR 0x0 +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLEAR_ALL_CLPC_ERROR___POR 0x0 +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLPC_ERROR_INIT_VALUE___POR 0x000 +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_U__TPC_CL_ERR_SCALE_STG0___M 0x0FC00000 +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_U__TPC_CL_ERR_SCALE_STG0___S 22 +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLPC_ERR_CMN_IGNORE_AFTER_DUP___M 0x00200000 +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLPC_ERR_CMN_IGNORE_AFTER_DUP___S 21 +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLPC_ERR_CMN_PKT_THR___M 0x001FE000 +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLPC_ERR_CMN_PKT_THR___S 13 +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLPC_ERR_CMN_DUP_EN___M 0x00001000 +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLPC_ERR_CMN_DUP_EN___S 12 +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLEAR_ALL_CLPC_ERROR_DONE___M 0x00000800 +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLEAR_ALL_CLPC_ERROR_DONE___S 11 +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLEAR_ALL_CLPC_ERROR___M 0x00000400 +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLEAR_ALL_CLPC_ERROR___S 10 +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLPC_ERROR_INIT_VALUE___M 0x000003FF +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_U__CLPC_ERROR_INIT_VALUE___S 0 +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_U___M 0x0FFFFFFF +#define PHYA_PHYRF_TPC_CLPC_CTRL_0_U___S 0 + +#define PHYA_PHYRF_TPC_CLPC_CTRL_1_L (0x00480148) +#define PHYA_PHYRF_TPC_CLPC_CTRL_1_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_CLPC_CTRL_1_L___POR 0x41044088 +#define PHYA_PHYRF_TPC_CLPC_CTRL_1_L__MU_TPC_CL_ERR_CLIP_EN___POR 0x0 +#define PHYA_PHYRF_TPC_CLPC_CTRL_1_L__MU_TPC_CL_ERR_CLIP___POR 0x20 +#define PHYA_PHYRF_TPC_CLPC_CTRL_1_L__MU_TPC_CL_ERR_SCALE___POR 0x20 +#define PHYA_PHYRF_TPC_CLPC_CTRL_1_L__TPC_CL_ERR_CLIP_EN___POR 0x1 +#define PHYA_PHYRF_TPC_CLPC_CTRL_1_L__TPC_CL_ERR_CLIP_STG1___POR 0x04 +#define PHYA_PHYRF_TPC_CLPC_CTRL_1_L__TPC_CL_ERR_SCALE_STG1___POR 0x02 +#define PHYA_PHYRF_TPC_CLPC_CTRL_1_L__TPC_CL_ERR_CLIP_STG0___POR 0x08 +#define PHYA_PHYRF_TPC_CLPC_CTRL_1_L__MU_TPC_CL_ERR_CLIP_EN___M 0x80000000 +#define PHYA_PHYRF_TPC_CLPC_CTRL_1_L__MU_TPC_CL_ERR_CLIP_EN___S 31 +#define PHYA_PHYRF_TPC_CLPC_CTRL_1_L__MU_TPC_CL_ERR_CLIP___M 0x7E000000 +#define PHYA_PHYRF_TPC_CLPC_CTRL_1_L__MU_TPC_CL_ERR_CLIP___S 25 +#define PHYA_PHYRF_TPC_CLPC_CTRL_1_L__MU_TPC_CL_ERR_SCALE___M 0x01F80000 +#define PHYA_PHYRF_TPC_CLPC_CTRL_1_L__MU_TPC_CL_ERR_SCALE___S 19 +#define PHYA_PHYRF_TPC_CLPC_CTRL_1_L__TPC_CL_ERR_CLIP_EN___M 0x00040000 +#define PHYA_PHYRF_TPC_CLPC_CTRL_1_L__TPC_CL_ERR_CLIP_EN___S 18 +#define PHYA_PHYRF_TPC_CLPC_CTRL_1_L__TPC_CL_ERR_CLIP_STG1___M 0x0003F000 +#define PHYA_PHYRF_TPC_CLPC_CTRL_1_L__TPC_CL_ERR_CLIP_STG1___S 12 +#define PHYA_PHYRF_TPC_CLPC_CTRL_1_L__TPC_CL_ERR_SCALE_STG1___M 0x00000FC0 +#define PHYA_PHYRF_TPC_CLPC_CTRL_1_L__TPC_CL_ERR_SCALE_STG1___S 6 +#define PHYA_PHYRF_TPC_CLPC_CTRL_1_L__TPC_CL_ERR_CLIP_STG0___M 0x0000003F +#define PHYA_PHYRF_TPC_CLPC_CTRL_1_L__TPC_CL_ERR_CLIP_STG0___S 0 +#define PHYA_PHYRF_TPC_CLPC_CTRL_1_L___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_CLPC_CTRL_1_L___S 0 + +#define PHYA_PHYRF_TPC_OLPC_CTRL_L (0x00480150) +#define PHYA_PHYRF_TPC_OLPC_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_OLPC_CTRL_L___POR 0x00000000 +#define PHYA_PHYRF_TPC_OLPC_CTRL_L__TPC_SPARE___POR 0x0000 +#define PHYA_PHYRF_TPC_OLPC_CTRL_L__TPC_USE_INIT_THERM_VOLT_AFTER_WARM_RESET___POR 0x0 +#define PHYA_PHYRF_TPC_OLPC_CTRL_L__MIN_POWER_THERM_VOLT_GAIN_CORR___POR 0x00 +#define PHYA_PHYRF_TPC_OLPC_CTRL_L__THERM_GAIN_ERR_DB_MAX___POR 0x00 +#define PHYA_PHYRF_TPC_OLPC_CTRL_L__TPC_SPARE___M 0x0FFFF000 +#define PHYA_PHYRF_TPC_OLPC_CTRL_L__TPC_SPARE___S 12 +#define PHYA_PHYRF_TPC_OLPC_CTRL_L__TPC_USE_INIT_THERM_VOLT_AFTER_WARM_RESET___M 0x00000800 +#define PHYA_PHYRF_TPC_OLPC_CTRL_L__TPC_USE_INIT_THERM_VOLT_AFTER_WARM_RESET___S 11 +#define PHYA_PHYRF_TPC_OLPC_CTRL_L__MIN_POWER_THERM_VOLT_GAIN_CORR___M 0x000007E0 +#define PHYA_PHYRF_TPC_OLPC_CTRL_L__MIN_POWER_THERM_VOLT_GAIN_CORR___S 5 +#define PHYA_PHYRF_TPC_OLPC_CTRL_L__THERM_GAIN_ERR_DB_MAX___M 0x0000001F +#define PHYA_PHYRF_TPC_OLPC_CTRL_L__THERM_GAIN_ERR_DB_MAX___S 0 +#define PHYA_PHYRF_TPC_OLPC_CTRL_L___M 0x0FFFFFFF +#define PHYA_PHYRF_TPC_OLPC_CTRL_L___S 0 + +#define PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L (0x00480158) +#define PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L___POR 0x00000C00 +#define PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__POWER_OFFSET_EXTENDED_RANGE_SU___POR 0x00 +#define PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__POWER_OFFSET_CCK___POR 0x00 +#define PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__EN_CLPC_RATE_PWR_OFST_STF___POR 0x1 +#define PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__EN_CLPC_BW_PWR_OFST_STF___POR 0x1 +#define PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__EN_CLPC_RATE_PWR_OFST_FPKT___POR 0x0 +#define PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__EN_CLPC_BW_PWR_OFST_FPKT___POR 0x0 +#define PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__PWR_OFST_MCS_THR_HIGH___POR 0x0 +#define PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__PWR_OFST_MCS_THR_MID___POR 0x0 +#define PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__POWER_OFFSET_EXTENDED_RANGE_SU___M 0x0FF00000 +#define PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__POWER_OFFSET_EXTENDED_RANGE_SU___S 20 +#define PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__POWER_OFFSET_CCK___M 0x000FF000 +#define PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__POWER_OFFSET_CCK___S 12 +#define PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__EN_CLPC_RATE_PWR_OFST_STF___M 0x00000800 +#define PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__EN_CLPC_RATE_PWR_OFST_STF___S 11 +#define PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__EN_CLPC_BW_PWR_OFST_STF___M 0x00000400 +#define PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__EN_CLPC_BW_PWR_OFST_STF___S 10 +#define PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__EN_CLPC_RATE_PWR_OFST_FPKT___M 0x00000200 +#define PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__EN_CLPC_RATE_PWR_OFST_FPKT___S 9 +#define PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__EN_CLPC_BW_PWR_OFST_FPKT___M 0x00000100 +#define PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__EN_CLPC_BW_PWR_OFST_FPKT___S 8 +#define PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__PWR_OFST_MCS_THR_HIGH___M 0x000000F0 +#define PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__PWR_OFST_MCS_THR_HIGH___S 4 +#define PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__PWR_OFST_MCS_THR_MID___M 0x0000000F +#define PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L__PWR_OFST_MCS_THR_MID___S 0 +#define PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L___M 0x0FFFFFFF +#define PHYA_PHYRF_TPC_POWER_OFFSET_CTRL_L___S 0 + +#define PHYA_PHYRF_TPC_FORCE_CTRL_L (0x00480160) +#define PHYA_PHYRF_TPC_FORCE_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_FORCE_CTRL_L___POR 0x00000000 +#define PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_GLUT_IDX___POR 0x0 +#define PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_GLUT_IDX_ENA___POR 0x0 +#define PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_USE_PREAMBLE_PWR___POR 0x0 +#define PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_TPC_TXCAL_TABLE_OUTPUT___POR 0x0 +#define PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_CLPC_DISABLE___POR 0x0 +#define PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_CLPC_ENABLE___POR 0x0 +#define PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_TXGAIN_IDX___POR 0x0 +#define PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_DAC_GAIN___POR 0x0 +#define PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCED_TARGET_POWER_SHARED___POR 0x00 +#define PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCED_TARGET_POWER_UNSHARED___POR 0x00 +#define PHYA_PHYRF_TPC_FORCE_CTRL_L__USE_FORCED_TARGET_POWER___POR 0x0 +#define PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_GLUT_IDX___M 0x0F000000 +#define PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_GLUT_IDX___S 24 +#define PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_GLUT_IDX_ENA___M 0x00800000 +#define PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_GLUT_IDX_ENA___S 23 +#define PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_USE_PREAMBLE_PWR___M 0x00400000 +#define PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_USE_PREAMBLE_PWR___S 22 +#define PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_TPC_TXCAL_TABLE_OUTPUT___M 0x00200000 +#define PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_TPC_TXCAL_TABLE_OUTPUT___S 21 +#define PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_CLPC_DISABLE___M 0x00100000 +#define PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_CLPC_DISABLE___S 20 +#define PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_CLPC_ENABLE___M 0x00080000 +#define PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_CLPC_ENABLE___S 19 +#define PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_TXGAIN_IDX___M 0x00040000 +#define PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_TXGAIN_IDX___S 18 +#define PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_DAC_GAIN___M 0x00020000 +#define PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCE_DAC_GAIN___S 17 +#define PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCED_TARGET_POWER_SHARED___M 0x0001FE00 +#define PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCED_TARGET_POWER_SHARED___S 9 +#define PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCED_TARGET_POWER_UNSHARED___M 0x000001FE +#define PHYA_PHYRF_TPC_FORCE_CTRL_L__FORCED_TARGET_POWER_UNSHARED___S 1 +#define PHYA_PHYRF_TPC_FORCE_CTRL_L__USE_FORCED_TARGET_POWER___M 0x00000001 +#define PHYA_PHYRF_TPC_FORCE_CTRL_L__USE_FORCED_TARGET_POWER___S 0 +#define PHYA_PHYRF_TPC_FORCE_CTRL_L___M 0x0FFFFFFF +#define PHYA_PHYRF_TPC_FORCE_CTRL_L___S 0 + +#define PHYA_PHYRF_TPC_FORCE_CTRL_U (0x00480164) +#define PHYA_PHYRF_TPC_FORCE_CTRL_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_FORCE_CTRL_U___POR 0x00000000 +#define PHYA_PHYRF_TPC_FORCE_CTRL_U__MIN_DAC_GAIN_FORCE_GLUT_IDX_ENA___POR 0x00 +#define PHYA_PHYRF_TPC_FORCE_CTRL_U__MAX_DAC_GAIN_FORCE_GLUT_IDX_ENA___POR 0x00 +#define PHYA_PHYRF_TPC_FORCE_CTRL_U__MIN_DAC_GAIN_FORCE_GLUT_IDX_ENA___M 0x0000FF00 +#define PHYA_PHYRF_TPC_FORCE_CTRL_U__MIN_DAC_GAIN_FORCE_GLUT_IDX_ENA___S 8 +#define PHYA_PHYRF_TPC_FORCE_CTRL_U__MAX_DAC_GAIN_FORCE_GLUT_IDX_ENA___M 0x000000FF +#define PHYA_PHYRF_TPC_FORCE_CTRL_U__MAX_DAC_GAIN_FORCE_GLUT_IDX_ENA___S 0 +#define PHYA_PHYRF_TPC_FORCE_CTRL_U___M 0x0000FFFF +#define PHYA_PHYRF_TPC_FORCE_CTRL_U___S 0 + +#define PHYA_PHYRF_TPC_DAC_BO_0_L (0x00480168) +#define PHYA_PHYRF_TPC_DAC_BO_0_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_DAC_BO_0_L___POR 0x0000022C +#define PHYA_PHYRF_TPC_DAC_BO_0_L__MIN_DAC_BO_CCK___POR 0x08 +#define PHYA_PHYRF_TPC_DAC_BO_0_L__MAX_DAC_BO_CCK___POR 0x2C +#define PHYA_PHYRF_TPC_DAC_BO_0_L__MIN_DAC_BO_CCK___M 0x00000FC0 +#define PHYA_PHYRF_TPC_DAC_BO_0_L__MIN_DAC_BO_CCK___S 6 +#define PHYA_PHYRF_TPC_DAC_BO_0_L__MAX_DAC_BO_CCK___M 0x0000003F +#define PHYA_PHYRF_TPC_DAC_BO_0_L__MAX_DAC_BO_CCK___S 0 +#define PHYA_PHYRF_TPC_DAC_BO_0_L___M 0x00000FFF +#define PHYA_PHYRF_TPC_DAC_BO_0_L___S 0 + +#define PHYA_PHYRF_TPC_DAC_BO_1_L (0x00480170) +#define PHYA_PHYRF_TPC_DAC_BO_1_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_DAC_BO_1_L___POR 0x00000000 +#define PHYA_PHYRF_TPC_DAC_BO_1_L__MAX_DAC_BO_QAM_3___POR 0x00 +#define PHYA_PHYRF_TPC_DAC_BO_1_L__MAX_DAC_BO_QAM_2___POR 0x00 +#define PHYA_PHYRF_TPC_DAC_BO_1_L__MAX_DAC_BO_QAM_1___POR 0x00 +#define PHYA_PHYRF_TPC_DAC_BO_1_L__MAX_DAC_BO_QAM_0___POR 0x00 +#define PHYA_PHYRF_TPC_DAC_BO_1_L__MAX_DAC_BO_QAM_3___M 0x3F000000 +#define PHYA_PHYRF_TPC_DAC_BO_1_L__MAX_DAC_BO_QAM_3___S 24 +#define PHYA_PHYRF_TPC_DAC_BO_1_L__MAX_DAC_BO_QAM_2___M 0x003F0000 +#define PHYA_PHYRF_TPC_DAC_BO_1_L__MAX_DAC_BO_QAM_2___S 16 +#define PHYA_PHYRF_TPC_DAC_BO_1_L__MAX_DAC_BO_QAM_1___M 0x00003F00 +#define PHYA_PHYRF_TPC_DAC_BO_1_L__MAX_DAC_BO_QAM_1___S 8 +#define PHYA_PHYRF_TPC_DAC_BO_1_L__MAX_DAC_BO_QAM_0___M 0x0000003F +#define PHYA_PHYRF_TPC_DAC_BO_1_L__MAX_DAC_BO_QAM_0___S 0 +#define PHYA_PHYRF_TPC_DAC_BO_1_L___M 0x3F3F3F3F +#define PHYA_PHYRF_TPC_DAC_BO_1_L___S 0 + +#define PHYA_PHYRF_TPC_DAC_BO_1_U (0x00480174) +#define PHYA_PHYRF_TPC_DAC_BO_1_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_DAC_BO_1_U___POR 0x00000000 +#define PHYA_PHYRF_TPC_DAC_BO_1_U__MAX_DAC_BO_QAM_6___POR 0x00 +#define PHYA_PHYRF_TPC_DAC_BO_1_U__MAX_DAC_BO_QAM_5___POR 0x00 +#define PHYA_PHYRF_TPC_DAC_BO_1_U__MAX_DAC_BO_QAM_4___POR 0x00 +#define PHYA_PHYRF_TPC_DAC_BO_1_U__MAX_DAC_BO_QAM_6___M 0x003F0000 +#define PHYA_PHYRF_TPC_DAC_BO_1_U__MAX_DAC_BO_QAM_6___S 16 +#define PHYA_PHYRF_TPC_DAC_BO_1_U__MAX_DAC_BO_QAM_5___M 0x00003F00 +#define PHYA_PHYRF_TPC_DAC_BO_1_U__MAX_DAC_BO_QAM_5___S 8 +#define PHYA_PHYRF_TPC_DAC_BO_1_U__MAX_DAC_BO_QAM_4___M 0x0000003F +#define PHYA_PHYRF_TPC_DAC_BO_1_U__MAX_DAC_BO_QAM_4___S 0 +#define PHYA_PHYRF_TPC_DAC_BO_1_U___M 0x003F3F3F +#define PHYA_PHYRF_TPC_DAC_BO_1_U___S 0 + +#define PHYA_PHYRF_TPC_DAC_BO_2_L (0x00480178) +#define PHYA_PHYRF_TPC_DAC_BO_2_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_DAC_BO_2_L___POR 0x00000000 +#define PHYA_PHYRF_TPC_DAC_BO_2_L__MIN_DAC_BO_QAM_3___POR 0x00 +#define PHYA_PHYRF_TPC_DAC_BO_2_L__MIN_DAC_BO_QAM_2___POR 0x00 +#define PHYA_PHYRF_TPC_DAC_BO_2_L__MIN_DAC_BO_QAM_1___POR 0x00 +#define PHYA_PHYRF_TPC_DAC_BO_2_L__MIN_DAC_BO_QAM_0___POR 0x00 +#define PHYA_PHYRF_TPC_DAC_BO_2_L__MIN_DAC_BO_QAM_3___M 0x3F000000 +#define PHYA_PHYRF_TPC_DAC_BO_2_L__MIN_DAC_BO_QAM_3___S 24 +#define PHYA_PHYRF_TPC_DAC_BO_2_L__MIN_DAC_BO_QAM_2___M 0x003F0000 +#define PHYA_PHYRF_TPC_DAC_BO_2_L__MIN_DAC_BO_QAM_2___S 16 +#define PHYA_PHYRF_TPC_DAC_BO_2_L__MIN_DAC_BO_QAM_1___M 0x00003F00 +#define PHYA_PHYRF_TPC_DAC_BO_2_L__MIN_DAC_BO_QAM_1___S 8 +#define PHYA_PHYRF_TPC_DAC_BO_2_L__MIN_DAC_BO_QAM_0___M 0x0000003F +#define PHYA_PHYRF_TPC_DAC_BO_2_L__MIN_DAC_BO_QAM_0___S 0 +#define PHYA_PHYRF_TPC_DAC_BO_2_L___M 0x3F3F3F3F +#define PHYA_PHYRF_TPC_DAC_BO_2_L___S 0 + +#define PHYA_PHYRF_TPC_DAC_BO_2_U (0x0048017C) +#define PHYA_PHYRF_TPC_DAC_BO_2_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_DAC_BO_2_U___POR 0x00000000 +#define PHYA_PHYRF_TPC_DAC_BO_2_U__MIN_DAC_BO_QAM_6___POR 0x00 +#define PHYA_PHYRF_TPC_DAC_BO_2_U__MIN_DAC_BO_QAM_5___POR 0x00 +#define PHYA_PHYRF_TPC_DAC_BO_2_U__MIN_DAC_BO_QAM_4___POR 0x00 +#define PHYA_PHYRF_TPC_DAC_BO_2_U__MIN_DAC_BO_QAM_6___M 0x003F0000 +#define PHYA_PHYRF_TPC_DAC_BO_2_U__MIN_DAC_BO_QAM_6___S 16 +#define PHYA_PHYRF_TPC_DAC_BO_2_U__MIN_DAC_BO_QAM_5___M 0x00003F00 +#define PHYA_PHYRF_TPC_DAC_BO_2_U__MIN_DAC_BO_QAM_5___S 8 +#define PHYA_PHYRF_TPC_DAC_BO_2_U__MIN_DAC_BO_QAM_4___M 0x0000003F +#define PHYA_PHYRF_TPC_DAC_BO_2_U__MIN_DAC_BO_QAM_4___S 0 +#define PHYA_PHYRF_TPC_DAC_BO_2_U___M 0x003F3F3F +#define PHYA_PHYRF_TPC_DAC_BO_2_U___S 0 + +#define PHYA_PHYRF_TPC_DAC_BO_3_L (0x00480180) +#define PHYA_PHYRF_TPC_DAC_BO_3_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_DAC_BO_3_L___POR 0x00000000 +#define PHYA_PHYRF_TPC_DAC_BO_3_L__MAX_MU_DAC_BO_QAM_3___POR 0x00 +#define PHYA_PHYRF_TPC_DAC_BO_3_L__MAX_MU_DAC_BO_QAM_2___POR 0x00 +#define PHYA_PHYRF_TPC_DAC_BO_3_L__MAX_MU_DAC_BO_QAM_1___POR 0x00 +#define PHYA_PHYRF_TPC_DAC_BO_3_L__MAX_MU_DAC_BO_QAM_0___POR 0x00 +#define PHYA_PHYRF_TPC_DAC_BO_3_L__MAX_MU_DAC_BO_QAM_3___M 0x3F000000 +#define PHYA_PHYRF_TPC_DAC_BO_3_L__MAX_MU_DAC_BO_QAM_3___S 24 +#define PHYA_PHYRF_TPC_DAC_BO_3_L__MAX_MU_DAC_BO_QAM_2___M 0x003F0000 +#define PHYA_PHYRF_TPC_DAC_BO_3_L__MAX_MU_DAC_BO_QAM_2___S 16 +#define PHYA_PHYRF_TPC_DAC_BO_3_L__MAX_MU_DAC_BO_QAM_1___M 0x00003F00 +#define PHYA_PHYRF_TPC_DAC_BO_3_L__MAX_MU_DAC_BO_QAM_1___S 8 +#define PHYA_PHYRF_TPC_DAC_BO_3_L__MAX_MU_DAC_BO_QAM_0___M 0x0000003F +#define PHYA_PHYRF_TPC_DAC_BO_3_L__MAX_MU_DAC_BO_QAM_0___S 0 +#define PHYA_PHYRF_TPC_DAC_BO_3_L___M 0x3F3F3F3F +#define PHYA_PHYRF_TPC_DAC_BO_3_L___S 0 + +#define PHYA_PHYRF_TPC_DAC_BO_3_U (0x00480184) +#define PHYA_PHYRF_TPC_DAC_BO_3_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_DAC_BO_3_U___POR 0x00000000 +#define PHYA_PHYRF_TPC_DAC_BO_3_U__MAX_MU_DAC_BO_QAM_6___POR 0x00 +#define PHYA_PHYRF_TPC_DAC_BO_3_U__MAX_MU_DAC_BO_QAM_5___POR 0x00 +#define PHYA_PHYRF_TPC_DAC_BO_3_U__MAX_MU_DAC_BO_QAM_4___POR 0x00 +#define PHYA_PHYRF_TPC_DAC_BO_3_U__MAX_MU_DAC_BO_QAM_6___M 0x003F0000 +#define PHYA_PHYRF_TPC_DAC_BO_3_U__MAX_MU_DAC_BO_QAM_6___S 16 +#define PHYA_PHYRF_TPC_DAC_BO_3_U__MAX_MU_DAC_BO_QAM_5___M 0x00003F00 +#define PHYA_PHYRF_TPC_DAC_BO_3_U__MAX_MU_DAC_BO_QAM_5___S 8 +#define PHYA_PHYRF_TPC_DAC_BO_3_U__MAX_MU_DAC_BO_QAM_4___M 0x0000003F +#define PHYA_PHYRF_TPC_DAC_BO_3_U__MAX_MU_DAC_BO_QAM_4___S 0 +#define PHYA_PHYRF_TPC_DAC_BO_3_U___M 0x003F3F3F +#define PHYA_PHYRF_TPC_DAC_BO_3_U___S 0 + +#define PHYA_PHYRF_TPC_DAC_BO_4_L (0x00480188) +#define PHYA_PHYRF_TPC_DAC_BO_4_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_DAC_BO_4_L___POR 0x00000000 +#define PHYA_PHYRF_TPC_DAC_BO_4_L__MIN_MU_DAC_BO_QAM_3___POR 0x00 +#define PHYA_PHYRF_TPC_DAC_BO_4_L__MIN_MU_DAC_BO_QAM_2___POR 0x00 +#define PHYA_PHYRF_TPC_DAC_BO_4_L__MIN_MU_DAC_BO_QAM_1___POR 0x00 +#define PHYA_PHYRF_TPC_DAC_BO_4_L__MIN_MU_DAC_BO_QAM_0___POR 0x00 +#define PHYA_PHYRF_TPC_DAC_BO_4_L__MIN_MU_DAC_BO_QAM_3___M 0x3F000000 +#define PHYA_PHYRF_TPC_DAC_BO_4_L__MIN_MU_DAC_BO_QAM_3___S 24 +#define PHYA_PHYRF_TPC_DAC_BO_4_L__MIN_MU_DAC_BO_QAM_2___M 0x003F0000 +#define PHYA_PHYRF_TPC_DAC_BO_4_L__MIN_MU_DAC_BO_QAM_2___S 16 +#define PHYA_PHYRF_TPC_DAC_BO_4_L__MIN_MU_DAC_BO_QAM_1___M 0x00003F00 +#define PHYA_PHYRF_TPC_DAC_BO_4_L__MIN_MU_DAC_BO_QAM_1___S 8 +#define PHYA_PHYRF_TPC_DAC_BO_4_L__MIN_MU_DAC_BO_QAM_0___M 0x0000003F +#define PHYA_PHYRF_TPC_DAC_BO_4_L__MIN_MU_DAC_BO_QAM_0___S 0 +#define PHYA_PHYRF_TPC_DAC_BO_4_L___M 0x3F3F3F3F +#define PHYA_PHYRF_TPC_DAC_BO_4_L___S 0 + +#define PHYA_PHYRF_TPC_DAC_BO_4_U (0x0048018C) +#define PHYA_PHYRF_TPC_DAC_BO_4_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_DAC_BO_4_U___POR 0x00000000 +#define PHYA_PHYRF_TPC_DAC_BO_4_U__MIN_MU_DAC_BO_QAM_6___POR 0x00 +#define PHYA_PHYRF_TPC_DAC_BO_4_U__MIN_MU_DAC_BO_QAM_5___POR 0x00 +#define PHYA_PHYRF_TPC_DAC_BO_4_U__MIN_MU_DAC_BO_QAM_4___POR 0x00 +#define PHYA_PHYRF_TPC_DAC_BO_4_U__MIN_MU_DAC_BO_QAM_6___M 0x003F0000 +#define PHYA_PHYRF_TPC_DAC_BO_4_U__MIN_MU_DAC_BO_QAM_6___S 16 +#define PHYA_PHYRF_TPC_DAC_BO_4_U__MIN_MU_DAC_BO_QAM_5___M 0x00003F00 +#define PHYA_PHYRF_TPC_DAC_BO_4_U__MIN_MU_DAC_BO_QAM_5___S 8 +#define PHYA_PHYRF_TPC_DAC_BO_4_U__MIN_MU_DAC_BO_QAM_4___M 0x0000003F +#define PHYA_PHYRF_TPC_DAC_BO_4_U__MIN_MU_DAC_BO_QAM_4___S 0 +#define PHYA_PHYRF_TPC_DAC_BO_4_U___M 0x003F3F3F +#define PHYA_PHYRF_TPC_DAC_BO_4_U___S 0 + +#define PHYA_PHYRF_TPC_DAC_BO_5_L (0x00480190) +#define PHYA_PHYRF_TPC_DAC_BO_5_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_DAC_BO_5_L___POR 0x00000000 +#define PHYA_PHYRF_TPC_DAC_BO_5_L__MIN_DAC_BO_SINGLERU___POR 0x00 +#define PHYA_PHYRF_TPC_DAC_BO_5_L__MAX_DAC_BO_SINGLERU___POR 0x00 +#define PHYA_PHYRF_TPC_DAC_BO_5_L__MIN_DAC_BO_SINGLERU___M 0x00000FC0 +#define PHYA_PHYRF_TPC_DAC_BO_5_L__MIN_DAC_BO_SINGLERU___S 6 +#define PHYA_PHYRF_TPC_DAC_BO_5_L__MAX_DAC_BO_SINGLERU___M 0x0000003F +#define PHYA_PHYRF_TPC_DAC_BO_5_L__MAX_DAC_BO_SINGLERU___S 0 +#define PHYA_PHYRF_TPC_DAC_BO_5_L___M 0x00000FFF +#define PHYA_PHYRF_TPC_DAC_BO_5_L___S 0 + +#define PHYA_PHYRF_TPC_GLUT_IDX_0_L (0x00480198) +#define PHYA_PHYRF_TPC_GLUT_IDX_0_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_GLUT_IDX_0_L___POR 0x00000000 +#define PHYA_PHYRF_TPC_GLUT_IDX_0_L__TPC_GLUT_INIT_IDX_CCK_RANGE_3___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_0_L__TPC_GLUT_INIT_IDX_CCK_RANGE_2___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_0_L__TPC_GLUT_INIT_IDX_CCK_RANGE_1___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_0_L__TPC_GLUT_INIT_IDX_CCK_RANGE_0___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_0_L__TPC_GLUT_INIT_IDX_CCK_RANGE_3___M 0x0F000000 +#define PHYA_PHYRF_TPC_GLUT_IDX_0_L__TPC_GLUT_INIT_IDX_CCK_RANGE_3___S 24 +#define PHYA_PHYRF_TPC_GLUT_IDX_0_L__TPC_GLUT_INIT_IDX_CCK_RANGE_2___M 0x000F0000 +#define PHYA_PHYRF_TPC_GLUT_IDX_0_L__TPC_GLUT_INIT_IDX_CCK_RANGE_2___S 16 +#define PHYA_PHYRF_TPC_GLUT_IDX_0_L__TPC_GLUT_INIT_IDX_CCK_RANGE_1___M 0x00000F00 +#define PHYA_PHYRF_TPC_GLUT_IDX_0_L__TPC_GLUT_INIT_IDX_CCK_RANGE_1___S 8 +#define PHYA_PHYRF_TPC_GLUT_IDX_0_L__TPC_GLUT_INIT_IDX_CCK_RANGE_0___M 0x0000000F +#define PHYA_PHYRF_TPC_GLUT_IDX_0_L__TPC_GLUT_INIT_IDX_CCK_RANGE_0___S 0 +#define PHYA_PHYRF_TPC_GLUT_IDX_0_L___M 0x0F0F0F0F +#define PHYA_PHYRF_TPC_GLUT_IDX_0_L___S 0 + +#define PHYA_PHYRF_TPC_GLUT_IDX_1_L (0x004801A0) +#define PHYA_PHYRF_TPC_GLUT_IDX_1_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_GLUT_IDX_1_L___POR 0x00000000 +#define PHYA_PHYRF_TPC_GLUT_IDX_1_L__TPC_GLUT_LAST_IDX_CCK_RANGE_3___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_1_L__TPC_GLUT_LAST_IDX_CCK_RANGE_2___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_1_L__TPC_GLUT_LAST_IDX_CCK_RANGE_1___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_1_L__TPC_GLUT_LAST_IDX_CCK_RANGE_0___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_1_L__TPC_GLUT_LAST_IDX_CCK_RANGE_3___M 0x0F000000 +#define PHYA_PHYRF_TPC_GLUT_IDX_1_L__TPC_GLUT_LAST_IDX_CCK_RANGE_3___S 24 +#define PHYA_PHYRF_TPC_GLUT_IDX_1_L__TPC_GLUT_LAST_IDX_CCK_RANGE_2___M 0x000F0000 +#define PHYA_PHYRF_TPC_GLUT_IDX_1_L__TPC_GLUT_LAST_IDX_CCK_RANGE_2___S 16 +#define PHYA_PHYRF_TPC_GLUT_IDX_1_L__TPC_GLUT_LAST_IDX_CCK_RANGE_1___M 0x00000F00 +#define PHYA_PHYRF_TPC_GLUT_IDX_1_L__TPC_GLUT_LAST_IDX_CCK_RANGE_1___S 8 +#define PHYA_PHYRF_TPC_GLUT_IDX_1_L__TPC_GLUT_LAST_IDX_CCK_RANGE_0___M 0x0000000F +#define PHYA_PHYRF_TPC_GLUT_IDX_1_L__TPC_GLUT_LAST_IDX_CCK_RANGE_0___S 0 +#define PHYA_PHYRF_TPC_GLUT_IDX_1_L___M 0x0F0F0F0F +#define PHYA_PHYRF_TPC_GLUT_IDX_1_L___S 0 + +#define PHYA_PHYRF_TPC_GLUT_IDX_2_L (0x004801A8) +#define PHYA_PHYRF_TPC_GLUT_IDX_2_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_GLUT_IDX_2_L___POR 0x00000000 +#define PHYA_PHYRF_TPC_GLUT_IDX_2_L__TPC_GLUT_INIT_IDX_OFDM_LOWMCS_RANGE_3___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_2_L__TPC_GLUT_INIT_IDX_OFDM_LOWMCS_RANGE_2___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_2_L__TPC_GLUT_INIT_IDX_OFDM_LOWMCS_RANGE_1___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_2_L__TPC_GLUT_INIT_IDX_OFDM_LOWMCS_RANGE_0___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_2_L__TPC_GLUT_INIT_IDX_OFDM_LOWMCS_RANGE_3___M 0x0F000000 +#define PHYA_PHYRF_TPC_GLUT_IDX_2_L__TPC_GLUT_INIT_IDX_OFDM_LOWMCS_RANGE_3___S 24 +#define PHYA_PHYRF_TPC_GLUT_IDX_2_L__TPC_GLUT_INIT_IDX_OFDM_LOWMCS_RANGE_2___M 0x000F0000 +#define PHYA_PHYRF_TPC_GLUT_IDX_2_L__TPC_GLUT_INIT_IDX_OFDM_LOWMCS_RANGE_2___S 16 +#define PHYA_PHYRF_TPC_GLUT_IDX_2_L__TPC_GLUT_INIT_IDX_OFDM_LOWMCS_RANGE_1___M 0x00000F00 +#define PHYA_PHYRF_TPC_GLUT_IDX_2_L__TPC_GLUT_INIT_IDX_OFDM_LOWMCS_RANGE_1___S 8 +#define PHYA_PHYRF_TPC_GLUT_IDX_2_L__TPC_GLUT_INIT_IDX_OFDM_LOWMCS_RANGE_0___M 0x0000000F +#define PHYA_PHYRF_TPC_GLUT_IDX_2_L__TPC_GLUT_INIT_IDX_OFDM_LOWMCS_RANGE_0___S 0 +#define PHYA_PHYRF_TPC_GLUT_IDX_2_L___M 0x0F0F0F0F +#define PHYA_PHYRF_TPC_GLUT_IDX_2_L___S 0 + +#define PHYA_PHYRF_TPC_GLUT_IDX_3_L (0x004801B0) +#define PHYA_PHYRF_TPC_GLUT_IDX_3_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_GLUT_IDX_3_L___POR 0x00000000 +#define PHYA_PHYRF_TPC_GLUT_IDX_3_L__TPC_GLUT_LAST_IDX_OFDM_LOWMCS_RANGE_3___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_3_L__TPC_GLUT_LAST_IDX_OFDM_LOWMCS_RANGE_2___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_3_L__TPC_GLUT_LAST_IDX_OFDM_LOWMCS_RANGE_1___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_3_L__TPC_GLUT_LAST_IDX_OFDM_LOWMCS_RANGE_0___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_3_L__TPC_GLUT_LAST_IDX_OFDM_LOWMCS_RANGE_3___M 0x0F000000 +#define PHYA_PHYRF_TPC_GLUT_IDX_3_L__TPC_GLUT_LAST_IDX_OFDM_LOWMCS_RANGE_3___S 24 +#define PHYA_PHYRF_TPC_GLUT_IDX_3_L__TPC_GLUT_LAST_IDX_OFDM_LOWMCS_RANGE_2___M 0x000F0000 +#define PHYA_PHYRF_TPC_GLUT_IDX_3_L__TPC_GLUT_LAST_IDX_OFDM_LOWMCS_RANGE_2___S 16 +#define PHYA_PHYRF_TPC_GLUT_IDX_3_L__TPC_GLUT_LAST_IDX_OFDM_LOWMCS_RANGE_1___M 0x00000F00 +#define PHYA_PHYRF_TPC_GLUT_IDX_3_L__TPC_GLUT_LAST_IDX_OFDM_LOWMCS_RANGE_1___S 8 +#define PHYA_PHYRF_TPC_GLUT_IDX_3_L__TPC_GLUT_LAST_IDX_OFDM_LOWMCS_RANGE_0___M 0x0000000F +#define PHYA_PHYRF_TPC_GLUT_IDX_3_L__TPC_GLUT_LAST_IDX_OFDM_LOWMCS_RANGE_0___S 0 +#define PHYA_PHYRF_TPC_GLUT_IDX_3_L___M 0x0F0F0F0F +#define PHYA_PHYRF_TPC_GLUT_IDX_3_L___S 0 + +#define PHYA_PHYRF_TPC_GLUT_IDX_4_L (0x004801B8) +#define PHYA_PHYRF_TPC_GLUT_IDX_4_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_GLUT_IDX_4_L___POR 0x00000000 +#define PHYA_PHYRF_TPC_GLUT_IDX_4_L__TPC_GLUT_INIT_IDX_OFDM_HIGHMCS_RANGE_3___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_4_L__TPC_GLUT_INIT_IDX_OFDM_HIGHMCS_RANGE_2___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_4_L__TPC_GLUT_INIT_IDX_OFDM_HIGHMCS_RANGE_1___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_4_L__TPC_GLUT_INIT_IDX_OFDM_HIGHMCS_RANGE_0___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_4_L__TPC_GLUT_INIT_IDX_OFDM_HIGHMCS_RANGE_3___M 0x0F000000 +#define PHYA_PHYRF_TPC_GLUT_IDX_4_L__TPC_GLUT_INIT_IDX_OFDM_HIGHMCS_RANGE_3___S 24 +#define PHYA_PHYRF_TPC_GLUT_IDX_4_L__TPC_GLUT_INIT_IDX_OFDM_HIGHMCS_RANGE_2___M 0x000F0000 +#define PHYA_PHYRF_TPC_GLUT_IDX_4_L__TPC_GLUT_INIT_IDX_OFDM_HIGHMCS_RANGE_2___S 16 +#define PHYA_PHYRF_TPC_GLUT_IDX_4_L__TPC_GLUT_INIT_IDX_OFDM_HIGHMCS_RANGE_1___M 0x00000F00 +#define PHYA_PHYRF_TPC_GLUT_IDX_4_L__TPC_GLUT_INIT_IDX_OFDM_HIGHMCS_RANGE_1___S 8 +#define PHYA_PHYRF_TPC_GLUT_IDX_4_L__TPC_GLUT_INIT_IDX_OFDM_HIGHMCS_RANGE_0___M 0x0000000F +#define PHYA_PHYRF_TPC_GLUT_IDX_4_L__TPC_GLUT_INIT_IDX_OFDM_HIGHMCS_RANGE_0___S 0 +#define PHYA_PHYRF_TPC_GLUT_IDX_4_L___M 0x0F0F0F0F +#define PHYA_PHYRF_TPC_GLUT_IDX_4_L___S 0 + +#define PHYA_PHYRF_TPC_GLUT_IDX_5_L (0x004801C0) +#define PHYA_PHYRF_TPC_GLUT_IDX_5_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_GLUT_IDX_5_L___POR 0x00000000 +#define PHYA_PHYRF_TPC_GLUT_IDX_5_L__TPC_GLUT_LAST_IDX_OFDM_HIGHMCS_RANGE_3___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_5_L__TPC_GLUT_LAST_IDX_OFDM_HIGHMCS_RANGE_2___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_5_L__TPC_GLUT_LAST_IDX_OFDM_HIGHMCS_RANGE_1___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_5_L__TPC_GLUT_LAST_IDX_OFDM_HIGHMCS_RANGE_0___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_5_L__TPC_GLUT_LAST_IDX_OFDM_HIGHMCS_RANGE_3___M 0x0F000000 +#define PHYA_PHYRF_TPC_GLUT_IDX_5_L__TPC_GLUT_LAST_IDX_OFDM_HIGHMCS_RANGE_3___S 24 +#define PHYA_PHYRF_TPC_GLUT_IDX_5_L__TPC_GLUT_LAST_IDX_OFDM_HIGHMCS_RANGE_2___M 0x000F0000 +#define PHYA_PHYRF_TPC_GLUT_IDX_5_L__TPC_GLUT_LAST_IDX_OFDM_HIGHMCS_RANGE_2___S 16 +#define PHYA_PHYRF_TPC_GLUT_IDX_5_L__TPC_GLUT_LAST_IDX_OFDM_HIGHMCS_RANGE_1___M 0x00000F00 +#define PHYA_PHYRF_TPC_GLUT_IDX_5_L__TPC_GLUT_LAST_IDX_OFDM_HIGHMCS_RANGE_1___S 8 +#define PHYA_PHYRF_TPC_GLUT_IDX_5_L__TPC_GLUT_LAST_IDX_OFDM_HIGHMCS_RANGE_0___M 0x0000000F +#define PHYA_PHYRF_TPC_GLUT_IDX_5_L__TPC_GLUT_LAST_IDX_OFDM_HIGHMCS_RANGE_0___S 0 +#define PHYA_PHYRF_TPC_GLUT_IDX_5_L___M 0x0F0F0F0F +#define PHYA_PHYRF_TPC_GLUT_IDX_5_L___S 0 + +#define PHYA_PHYRF_TPC_GLUT_IDX_6_L (0x004801C8) +#define PHYA_PHYRF_TPC_GLUT_IDX_6_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_GLUT_IDX_6_L___POR 0x00000000 +#define PHYA_PHYRF_TPC_GLUT_IDX_6_L__TPC_GLUT_INIT_IDX_SINGLE_RU_RANGE_3___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_6_L__TPC_GLUT_INIT_IDX_SINGLE_RU_RANGE_2___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_6_L__TPC_GLUT_INIT_IDX_SINGLE_RU_RANGE_1___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_6_L__TPC_GLUT_INIT_IDX_SINGLE_RU_RANGE_0___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_6_L__TPC_GLUT_INIT_IDX_SINGLE_RU_RANGE_3___M 0x0F000000 +#define PHYA_PHYRF_TPC_GLUT_IDX_6_L__TPC_GLUT_INIT_IDX_SINGLE_RU_RANGE_3___S 24 +#define PHYA_PHYRF_TPC_GLUT_IDX_6_L__TPC_GLUT_INIT_IDX_SINGLE_RU_RANGE_2___M 0x000F0000 +#define PHYA_PHYRF_TPC_GLUT_IDX_6_L__TPC_GLUT_INIT_IDX_SINGLE_RU_RANGE_2___S 16 +#define PHYA_PHYRF_TPC_GLUT_IDX_6_L__TPC_GLUT_INIT_IDX_SINGLE_RU_RANGE_1___M 0x00000F00 +#define PHYA_PHYRF_TPC_GLUT_IDX_6_L__TPC_GLUT_INIT_IDX_SINGLE_RU_RANGE_1___S 8 +#define PHYA_PHYRF_TPC_GLUT_IDX_6_L__TPC_GLUT_INIT_IDX_SINGLE_RU_RANGE_0___M 0x0000000F +#define PHYA_PHYRF_TPC_GLUT_IDX_6_L__TPC_GLUT_INIT_IDX_SINGLE_RU_RANGE_0___S 0 +#define PHYA_PHYRF_TPC_GLUT_IDX_6_L___M 0x0F0F0F0F +#define PHYA_PHYRF_TPC_GLUT_IDX_6_L___S 0 + +#define PHYA_PHYRF_TPC_GLUT_IDX_7_L (0x004801D0) +#define PHYA_PHYRF_TPC_GLUT_IDX_7_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_GLUT_IDX_7_L___POR 0x00000000 +#define PHYA_PHYRF_TPC_GLUT_IDX_7_L__TPC_GLUT_LAST_IDX_SINGLE_RU_RANGE_3___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_7_L__TPC_GLUT_LAST_IDX_SINGLE_RU_RANGE_2___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_7_L__TPC_GLUT_LAST_IDX_SINGLE_RU_RANGE_1___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_7_L__TPC_GLUT_LAST_IDX_SINGLE_RU_RANGE_0___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_7_L__TPC_GLUT_LAST_IDX_SINGLE_RU_RANGE_3___M 0x0F000000 +#define PHYA_PHYRF_TPC_GLUT_IDX_7_L__TPC_GLUT_LAST_IDX_SINGLE_RU_RANGE_3___S 24 +#define PHYA_PHYRF_TPC_GLUT_IDX_7_L__TPC_GLUT_LAST_IDX_SINGLE_RU_RANGE_2___M 0x000F0000 +#define PHYA_PHYRF_TPC_GLUT_IDX_7_L__TPC_GLUT_LAST_IDX_SINGLE_RU_RANGE_2___S 16 +#define PHYA_PHYRF_TPC_GLUT_IDX_7_L__TPC_GLUT_LAST_IDX_SINGLE_RU_RANGE_1___M 0x00000F00 +#define PHYA_PHYRF_TPC_GLUT_IDX_7_L__TPC_GLUT_LAST_IDX_SINGLE_RU_RANGE_1___S 8 +#define PHYA_PHYRF_TPC_GLUT_IDX_7_L__TPC_GLUT_LAST_IDX_SINGLE_RU_RANGE_0___M 0x0000000F +#define PHYA_PHYRF_TPC_GLUT_IDX_7_L__TPC_GLUT_LAST_IDX_SINGLE_RU_RANGE_0___S 0 +#define PHYA_PHYRF_TPC_GLUT_IDX_7_L___M 0x0F0F0F0F +#define PHYA_PHYRF_TPC_GLUT_IDX_7_L___S 0 + +#define PHYA_PHYRF_TPC_GLUT_IDX_8_L (0x004801D8) +#define PHYA_PHYRF_TPC_GLUT_IDX_8_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_GLUT_IDX_8_L___POR 0x00000000 +#define PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_LAST_IDX_DPDTRAIN___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_INIT_IDX_DPDTRAIN___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_LAST_IDX_BTCOEX___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_INIT_IDX_BTCOEX___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_DPDTRAIN_EN___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_BTCOEX_EN___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_INIT_IDX_MCS_THR___POR 0x0 +#define PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_LAST_IDX_DPDTRAIN___M 0x003C0000 +#define PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_LAST_IDX_DPDTRAIN___S 18 +#define PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_INIT_IDX_DPDTRAIN___M 0x0003C000 +#define PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_INIT_IDX_DPDTRAIN___S 14 +#define PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_LAST_IDX_BTCOEX___M 0x00003C00 +#define PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_LAST_IDX_BTCOEX___S 10 +#define PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_INIT_IDX_BTCOEX___M 0x000003C0 +#define PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_INIT_IDX_BTCOEX___S 6 +#define PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_DPDTRAIN_EN___M 0x00000020 +#define PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_DPDTRAIN_EN___S 5 +#define PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_BTCOEX_EN___M 0x00000010 +#define PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_BTCOEX_EN___S 4 +#define PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_INIT_IDX_MCS_THR___M 0x0000000F +#define PHYA_PHYRF_TPC_GLUT_IDX_8_L__TPC_GLUT_INIT_IDX_MCS_THR___S 0 +#define PHYA_PHYRF_TPC_GLUT_IDX_8_L___M 0x003FFFFF +#define PHYA_PHYRF_TPC_GLUT_IDX_8_L___S 0 + +#define PHYA_PHYRF_TPC_GLUT_SETTINGS_L (0x004801E0) +#define PHYA_PHYRF_TPC_GLUT_SETTINGS_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_GLUT_SETTINGS_L___POR 0x00000000 +#define PHYA_PHYRF_TPC_GLUT_SETTINGS_L__DPD_TXGAIN_IDX_CAL___POR 0x00 +#define PHYA_PHYRF_TPC_GLUT_SETTINGS_L__DPD_DAC_GAIN_CAL___POR 0x00 +#define PHYA_PHYRF_TPC_GLUT_SETTINGS_L__GLUT_MAX_DAC_GAIN_CAL___POR 0x00 +#define PHYA_PHYRF_TPC_GLUT_SETTINGS_L__GLUT_DAC_GAIN_CAL___POR 0x00 +#define PHYA_PHYRF_TPC_GLUT_SETTINGS_L__DPD_TXGAIN_IDX_CAL___M 0x3F000000 +#define PHYA_PHYRF_TPC_GLUT_SETTINGS_L__DPD_TXGAIN_IDX_CAL___S 24 +#define PHYA_PHYRF_TPC_GLUT_SETTINGS_L__DPD_DAC_GAIN_CAL___M 0x00FF0000 +#define PHYA_PHYRF_TPC_GLUT_SETTINGS_L__DPD_DAC_GAIN_CAL___S 16 +#define PHYA_PHYRF_TPC_GLUT_SETTINGS_L__GLUT_MAX_DAC_GAIN_CAL___M 0x0000FF00 +#define PHYA_PHYRF_TPC_GLUT_SETTINGS_L__GLUT_MAX_DAC_GAIN_CAL___S 8 +#define PHYA_PHYRF_TPC_GLUT_SETTINGS_L__GLUT_DAC_GAIN_CAL___M 0x000000FF +#define PHYA_PHYRF_TPC_GLUT_SETTINGS_L__GLUT_DAC_GAIN_CAL___S 0 +#define PHYA_PHYRF_TPC_GLUT_SETTINGS_L___M 0x3FFFFFFF +#define PHYA_PHYRF_TPC_GLUT_SETTINGS_L___S 0 + +#define PHYA_PHYRF_TPC_GLUT_TARGET_PWR_LEVEL_L (0x004801E8) +#define PHYA_PHYRF_TPC_GLUT_TARGET_PWR_LEVEL_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_GLUT_TARGET_PWR_LEVEL_L___POR 0x00EC143C +#define PHYA_PHYRF_TPC_GLUT_TARGET_PWR_LEVEL_L__GLUT_TARGET_PWR_LEVEL_LOW___POR 0xEC +#define PHYA_PHYRF_TPC_GLUT_TARGET_PWR_LEVEL_L__GLUT_TARGET_PWR_LEVEL_MID___POR 0x14 +#define PHYA_PHYRF_TPC_GLUT_TARGET_PWR_LEVEL_L__GLUT_TARGET_PWR_LEVEL_HIGH___POR 0x3C +#define PHYA_PHYRF_TPC_GLUT_TARGET_PWR_LEVEL_L__GLUT_TARGET_PWR_LEVEL_LOW___M 0x00FF0000 +#define PHYA_PHYRF_TPC_GLUT_TARGET_PWR_LEVEL_L__GLUT_TARGET_PWR_LEVEL_LOW___S 16 +#define PHYA_PHYRF_TPC_GLUT_TARGET_PWR_LEVEL_L__GLUT_TARGET_PWR_LEVEL_MID___M 0x0000FF00 +#define PHYA_PHYRF_TPC_GLUT_TARGET_PWR_LEVEL_L__GLUT_TARGET_PWR_LEVEL_MID___S 8 +#define PHYA_PHYRF_TPC_GLUT_TARGET_PWR_LEVEL_L__GLUT_TARGET_PWR_LEVEL_HIGH___M 0x000000FF +#define PHYA_PHYRF_TPC_GLUT_TARGET_PWR_LEVEL_L__GLUT_TARGET_PWR_LEVEL_HIGH___S 0 +#define PHYA_PHYRF_TPC_GLUT_TARGET_PWR_LEVEL_L___M 0x00FFFFFF +#define PHYA_PHYRF_TPC_GLUT_TARGET_PWR_LEVEL_L___S 0 + +#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_L (0x004801F0) +#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_L___POR 0x00000000 +#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_L__PLUT_PWR_OFFSET_TABLE_3___POR 0x00 +#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_L__PLUT_PWR_OFFSET_TABLE_2___POR 0x00 +#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_L__PLUT_PWR_OFFSET_TABLE_1___POR 0x00 +#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_L__PLUT_PWR_OFFSET_TABLE_0___POR 0x00 +#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_L__PLUT_PWR_OFFSET_TABLE_3___M 0xFF000000 +#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_L__PLUT_PWR_OFFSET_TABLE_3___S 24 +#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_L__PLUT_PWR_OFFSET_TABLE_2___M 0x00FF0000 +#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_L__PLUT_PWR_OFFSET_TABLE_2___S 16 +#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_L__PLUT_PWR_OFFSET_TABLE_1___M 0x0000FF00 +#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_L__PLUT_PWR_OFFSET_TABLE_1___S 8 +#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_L__PLUT_PWR_OFFSET_TABLE_0___M 0x000000FF +#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_L__PLUT_PWR_OFFSET_TABLE_0___S 0 +#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_L___M 0xFFFFFFFF +#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_L___S 0 + +#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_U (0x004801F4) +#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_U___POR 0x00000000 +#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_U__PLUT_PWR_OFFSET_TABLE_7___POR 0x00 +#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_U__PLUT_PWR_OFFSET_TABLE_6___POR 0x00 +#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_U__PLUT_PWR_OFFSET_TABLE_5___POR 0x00 +#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_U__PLUT_PWR_OFFSET_TABLE_4___POR 0x00 +#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_U__PLUT_PWR_OFFSET_TABLE_7___M 0xFF000000 +#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_U__PLUT_PWR_OFFSET_TABLE_7___S 24 +#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_U__PLUT_PWR_OFFSET_TABLE_6___M 0x00FF0000 +#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_U__PLUT_PWR_OFFSET_TABLE_6___S 16 +#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_U__PLUT_PWR_OFFSET_TABLE_5___M 0x0000FF00 +#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_U__PLUT_PWR_OFFSET_TABLE_5___S 8 +#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_U__PLUT_PWR_OFFSET_TABLE_4___M 0x000000FF +#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_U__PLUT_PWR_OFFSET_TABLE_4___S 0 +#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_U___M 0xFFFFFFFF +#define PHYA_PHYRF_PLUT_PWR_OFFSET_TABLE_U___S 0 + +#define PHYA_PHYRF_TPC_STAT_L (0x004801F8) +#define PHYA_PHYRF_TPC_STAT_L___RWC QCSR_REG_RO +#define PHYA_PHYRF_TPC_STAT_L___POR 0x00000000 +#define PHYA_PHYRF_TPC_STAT_L__LATEST_PAPRD_CHAIN_MASK___POR 0x0 +#define PHYA_PHYRF_TPC_STAT_L__LATEST_TX_CHAIN_MASK___POR 0x0 +#define PHYA_PHYRF_TPC_STAT_L__OLPC_GAIN_CORR___POR 0x0000 +#define PHYA_PHYRF_TPC_STAT_L__TPC_DPDTRAIN_COUNTER___POR 0x00 +#define PHYA_PHYRF_TPC_STAT_L__INIT_PWR_CFG_DPDTRAIN_LATEST_OUT___POR 0x0 +#define PHYA_PHYRF_TPC_STAT_L__LATEST_PAPRD_CHAIN_MASK___M 0xF0000000 +#define PHYA_PHYRF_TPC_STAT_L__LATEST_PAPRD_CHAIN_MASK___S 28 +#define PHYA_PHYRF_TPC_STAT_L__LATEST_TX_CHAIN_MASK___M 0x0F000000 +#define PHYA_PHYRF_TPC_STAT_L__LATEST_TX_CHAIN_MASK___S 24 +#define PHYA_PHYRF_TPC_STAT_L__OLPC_GAIN_CORR___M 0x00FFF800 +#define PHYA_PHYRF_TPC_STAT_L__OLPC_GAIN_CORR___S 11 +#define PHYA_PHYRF_TPC_STAT_L__TPC_DPDTRAIN_COUNTER___M 0x000007F0 +#define PHYA_PHYRF_TPC_STAT_L__TPC_DPDTRAIN_COUNTER___S 4 +#define PHYA_PHYRF_TPC_STAT_L__INIT_PWR_CFG_DPDTRAIN_LATEST_OUT___M 0x0000000F +#define PHYA_PHYRF_TPC_STAT_L__INIT_PWR_CFG_DPDTRAIN_LATEST_OUT___S 0 +#define PHYA_PHYRF_TPC_STAT_L___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_STAT_L___S 0 + +#define PHYA_PHYRF_TPC_STAT_SELF_CAL_L (0x00480200) +#define PHYA_PHYRF_TPC_STAT_SELF_CAL_L___RWC QCSR_REG_RO +#define PHYA_PHYRF_TPC_STAT_SELF_CAL_L___POR 0x00000000 +#define PHYA_PHYRF_TPC_STAT_SELF_CAL_L__TPC_SELF_CAL_STATUS___POR 0x0 +#define PHYA_PHYRF_TPC_STAT_SELF_CAL_L__TPC_SELF_CAL_STATUS___M 0x00000003 +#define PHYA_PHYRF_TPC_STAT_SELF_CAL_L__TPC_SELF_CAL_STATUS___S 0 +#define PHYA_PHYRF_TPC_STAT_SELF_CAL_L___M 0x00000003 +#define PHYA_PHYRF_TPC_STAT_SELF_CAL_L___S 0 + +#define PHYA_PHYRF_TPC_TWO_WAY_CONTROLS_L (0x00480208) +#define PHYA_PHYRF_TPC_TWO_WAY_CONTROLS_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_TWO_WAY_CONTROLS_L___POR 0x00000000 +#define PHYA_PHYRF_TPC_TWO_WAY_CONTROLS_L__CLPC_ERR_CMN_DUP_STATUS___POR 0x00 +#define PHYA_PHYRF_TPC_TWO_WAY_CONTROLS_L__CLPC_ERR_CMN_DUP_STATUS___M 0x000000FF +#define PHYA_PHYRF_TPC_TWO_WAY_CONTROLS_L__CLPC_ERR_CMN_DUP_STATUS___S 0 +#define PHYA_PHYRF_TPC_TWO_WAY_CONTROLS_L___M 0x000000FF +#define PHYA_PHYRF_TPC_TWO_WAY_CONTROLS_L___S 0 + +#define PHYA_PHYRF_TPC_MU_L (0x00480210) +#define PHYA_PHYRF_TPC_MU_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_MU_L___POR 0x00000000 +#define PHYA_PHYRF_TPC_MU_L__OLPC_MODE_NDP___POR 0x0 +#define PHYA_PHYRF_TPC_MU_L__OLPC_MODE_NDP___M 0x00000001 +#define PHYA_PHYRF_TPC_MU_L__OLPC_MODE_NDP___S 0 +#define PHYA_PHYRF_TPC_MU_L___M 0x00000001 +#define PHYA_PHYRF_TPC_MU_L___S 0 + +#define PHYA_PHYRF_TPC_RST_CTRL_L (0x00480218) +#define PHYA_PHYRF_TPC_RST_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_RST_CTRL_L___POR 0x00000000 +#define PHYA_PHYRF_TPC_RST_CTRL_L__TPC_SOFT_RESET___POR 0x0 +#define PHYA_PHYRF_TPC_RST_CTRL_L__TPC_SOFT_RESET___M 0x00000001 +#define PHYA_PHYRF_TPC_RST_CTRL_L__TPC_SOFT_RESET___S 0 +#define PHYA_PHYRF_TPC_RST_CTRL_L___M 0x00000001 +#define PHYA_PHYRF_TPC_RST_CTRL_L___S 0 + +#define PHYA_PHYRF_TPC_RECORDER_CTRL_L (0x00480220) +#define PHYA_PHYRF_TPC_RECORDER_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_RECORDER_CTRL_L___POR 0x00000000 +#define PHYA_PHYRF_TPC_RECORDER_CTRL_L__TPC_RECORD_COUNT___POR 0x00 +#define PHYA_PHYRF_TPC_RECORDER_CTRL_L__TPC_RECORD_MAX_TX_PKTS___POR 0x00 +#define PHYA_PHYRF_TPC_RECORDER_CTRL_L__TPC_RECORD_DONE___POR 0x0 +#define PHYA_PHYRF_TPC_RECORDER_CTRL_L__TPC_RECORD_ENABLE___POR 0x0 +#define PHYA_PHYRF_TPC_RECORDER_CTRL_L__TPC_RECORD_COUNT___M 0x0003FC00 +#define PHYA_PHYRF_TPC_RECORDER_CTRL_L__TPC_RECORD_COUNT___S 10 +#define PHYA_PHYRF_TPC_RECORDER_CTRL_L__TPC_RECORD_MAX_TX_PKTS___M 0x000003FC +#define PHYA_PHYRF_TPC_RECORDER_CTRL_L__TPC_RECORD_MAX_TX_PKTS___S 2 +#define PHYA_PHYRF_TPC_RECORDER_CTRL_L__TPC_RECORD_DONE___M 0x00000002 +#define PHYA_PHYRF_TPC_RECORDER_CTRL_L__TPC_RECORD_DONE___S 1 +#define PHYA_PHYRF_TPC_RECORDER_CTRL_L__TPC_RECORD_ENABLE___M 0x00000001 +#define PHYA_PHYRF_TPC_RECORDER_CTRL_L__TPC_RECORD_ENABLE___S 0 +#define PHYA_PHYRF_TPC_RECORDER_CTRL_L___M 0x0003FFFF +#define PHYA_PHYRF_TPC_RECORDER_CTRL_L___S 0 + +#define PHYA_PHYRF_TPC_DBG_BUS0_L (0x00480228) +#define PHYA_PHYRF_TPC_DBG_BUS0_L___RWC QCSR_REG_RO +#define PHYA_PHYRF_TPC_DBG_BUS0_L___POR 0x00000000 +#define PHYA_PHYRF_TPC_DBG_BUS0_L__TPC_DBG_BUS_0_0___POR 0x00000000 +#define PHYA_PHYRF_TPC_DBG_BUS0_L__TPC_DBG_BUS_0_0___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_DBG_BUS0_L__TPC_DBG_BUS_0_0___S 0 +#define PHYA_PHYRF_TPC_DBG_BUS0_L___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_DBG_BUS0_L___S 0 + +#define PHYA_PHYRF_TPC_DBG_BUS0_U (0x0048022C) +#define PHYA_PHYRF_TPC_DBG_BUS0_U___RWC QCSR_REG_RO +#define PHYA_PHYRF_TPC_DBG_BUS0_U___POR 0x00000000 +#define PHYA_PHYRF_TPC_DBG_BUS0_U__TPC_DBG_BUS_1_0___POR 0x00000000 +#define PHYA_PHYRF_TPC_DBG_BUS0_U__TPC_DBG_BUS_1_0___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_DBG_BUS0_U__TPC_DBG_BUS_1_0___S 0 +#define PHYA_PHYRF_TPC_DBG_BUS0_U___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_DBG_BUS0_U___S 0 + +#define PHYA_PHYRF_TPC_DBG_BUS1_L (0x00480230) +#define PHYA_PHYRF_TPC_DBG_BUS1_L___RWC QCSR_REG_RO +#define PHYA_PHYRF_TPC_DBG_BUS1_L___POR 0x00000000 +#define PHYA_PHYRF_TPC_DBG_BUS1_L__TPC_DBG_BUS_0_1___POR 0x00000000 +#define PHYA_PHYRF_TPC_DBG_BUS1_L__TPC_DBG_BUS_0_1___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_DBG_BUS1_L__TPC_DBG_BUS_0_1___S 0 +#define PHYA_PHYRF_TPC_DBG_BUS1_L___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_DBG_BUS1_L___S 0 + +#define PHYA_PHYRF_TPC_DBG_BUS1_U (0x00480234) +#define PHYA_PHYRF_TPC_DBG_BUS1_U___RWC QCSR_REG_RO +#define PHYA_PHYRF_TPC_DBG_BUS1_U___POR 0x00000000 +#define PHYA_PHYRF_TPC_DBG_BUS1_U__TPC_DBG_BUS_1_1___POR 0x00000000 +#define PHYA_PHYRF_TPC_DBG_BUS1_U__TPC_DBG_BUS_1_1___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_DBG_BUS1_U__TPC_DBG_BUS_1_1___S 0 +#define PHYA_PHYRF_TPC_DBG_BUS1_U___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_DBG_BUS1_U___S 0 + +#define PHYA_PHYRF_TPC_TRIG_SW_CTRL_L (0x00480238) +#define PHYA_PHYRF_TPC_TRIG_SW_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_TRIG_SW_CTRL_L___POR 0x00000000 +#define PHYA_PHYRF_TPC_TRIG_SW_CTRL_L__TX_END___POR 0x0 +#define PHYA_PHYRF_TPC_TRIG_SW_CTRL_L__TPC_GAIN_SEND___POR 0x0 +#define PHYA_PHYRF_TPC_TRIG_SW_CTRL_L__TPC_START___POR 0x0 +#define PHYA_PHYRF_TPC_TRIG_SW_CTRL_L__TX_END___M 0x00000004 +#define PHYA_PHYRF_TPC_TRIG_SW_CTRL_L__TX_END___S 2 +#define PHYA_PHYRF_TPC_TRIG_SW_CTRL_L__TPC_GAIN_SEND___M 0x00000002 +#define PHYA_PHYRF_TPC_TRIG_SW_CTRL_L__TPC_GAIN_SEND___S 1 +#define PHYA_PHYRF_TPC_TRIG_SW_CTRL_L__TPC_START___M 0x00000001 +#define PHYA_PHYRF_TPC_TRIG_SW_CTRL_L__TPC_START___S 0 +#define PHYA_PHYRF_TPC_TRIG_SW_CTRL_L___M 0x00000007 +#define PHYA_PHYRF_TPC_TRIG_SW_CTRL_L___S 0 + +#define PHYA_PHYRF_TPC_DCSR_ERROR_L (0x00480240) +#define PHYA_PHYRF_TPC_DCSR_ERROR_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_DCSR_ERROR_L___POR 0x00000000 +#define PHYA_PHYRF_TPC_DCSR_ERROR_L__TX_ERROR___POR 0x0 +#define PHYA_PHYRF_TPC_DCSR_ERROR_L__TX_ERROR___M 0x00000001 +#define PHYA_PHYRF_TPC_DCSR_ERROR_L__TX_ERROR___S 0 +#define PHYA_PHYRF_TPC_DCSR_ERROR_L___M 0x00000001 +#define PHYA_PHYRF_TPC_DCSR_ERROR_L___S 0 + +#define PHYA_PHYRF_TPC_DCSR_BT_L (0x00480248) +#define PHYA_PHYRF_TPC_DCSR_BT_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_DCSR_BT_L___POR 0x00000000 +#define PHYA_PHYRF_TPC_DCSR_BT_L__BT_IN_TX___POR 0x0 +#define PHYA_PHYRF_TPC_DCSR_BT_L__BT_IN_TX___M 0x00000001 +#define PHYA_PHYRF_TPC_DCSR_BT_L__BT_IN_TX___S 0 +#define PHYA_PHYRF_TPC_DCSR_BT_L___M 0x00000001 +#define PHYA_PHYRF_TPC_DCSR_BT_L___S 0 + +#define PHYA_PHYRF_TPC_ALUT_SRAM_L_n(n) (0x00480250+0x8*(n)) +#define PHYA_PHYRF_TPC_ALUT_SRAM_L_n_nMIN 0 +#define PHYA_PHYRF_TPC_ALUT_SRAM_L_n_nMAX 0 +#define PHYA_PHYRF_TPC_ALUT_SRAM_L_n_ELEM 1 +#define PHYA_PHYRF_TPC_ALUT_SRAM_L_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_ALUT_SRAM_L_n___POR 0x00000000 +#define PHYA_PHYRF_TPC_ALUT_SRAM_L_n__TPC_ALUT_0___POR 0x00000000 +#define PHYA_PHYRF_TPC_ALUT_SRAM_L_n__TPC_ALUT_0___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_ALUT_SRAM_L_n__TPC_ALUT_0___S 0 +#define PHYA_PHYRF_TPC_ALUT_SRAM_L_n___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_ALUT_SRAM_L_n___S 0 +#define PHYA_PHYRF_TPC_ALUT_SRAM_L_0 (0x00480250) +#define PHYA_PHYRF_TPC_ALUT_SRAM_L_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_ALUT_SRAM_L_0__TPC_ALUT_0___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_ALUT_SRAM_L_0__TPC_ALUT_0___S 0 + +#define PHYA_PHYRF_TPC_ALUT_SRAM_U_n(n) (0x00480254+0x8*(n)) +#define PHYA_PHYRF_TPC_ALUT_SRAM_U_n_nMIN 0 +#define PHYA_PHYRF_TPC_ALUT_SRAM_U_n_nMAX 0 +#define PHYA_PHYRF_TPC_ALUT_SRAM_U_n_ELEM 1 +#define PHYA_PHYRF_TPC_ALUT_SRAM_U_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_ALUT_SRAM_U_n___POR 0x00000000 +#define PHYA_PHYRF_TPC_ALUT_SRAM_U_n__TPC_ALUT_1___POR 0x00000000 +#define PHYA_PHYRF_TPC_ALUT_SRAM_U_n__TPC_ALUT_1___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_ALUT_SRAM_U_n__TPC_ALUT_1___S 0 +#define PHYA_PHYRF_TPC_ALUT_SRAM_U_n___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_ALUT_SRAM_U_n___S 0 +#define PHYA_PHYRF_TPC_ALUT_SRAM_U_0 (0x00480254) +#define PHYA_PHYRF_TPC_ALUT_SRAM_U_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_ALUT_SRAM_U_0__TPC_ALUT_1___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_ALUT_SRAM_U_0__TPC_ALUT_1___S 0 + +#define PHYA_PHYRF_TPC_GLUT_SRAM_L_n(n) (0x00480550+0x8*(n)) +#define PHYA_PHYRF_TPC_GLUT_SRAM_L_n_nMIN 0 +#define PHYA_PHYRF_TPC_GLUT_SRAM_L_n_nMAX 0 +#define PHYA_PHYRF_TPC_GLUT_SRAM_L_n_ELEM 1 +#define PHYA_PHYRF_TPC_GLUT_SRAM_L_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_GLUT_SRAM_L_n___POR 0x00000000 +#define PHYA_PHYRF_TPC_GLUT_SRAM_L_n__TPC_GLUT_0___POR 0x00000000 +#define PHYA_PHYRF_TPC_GLUT_SRAM_L_n__TPC_GLUT_0___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_GLUT_SRAM_L_n__TPC_GLUT_0___S 0 +#define PHYA_PHYRF_TPC_GLUT_SRAM_L_n___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_GLUT_SRAM_L_n___S 0 +#define PHYA_PHYRF_TPC_GLUT_SRAM_L_0 (0x00480550) +#define PHYA_PHYRF_TPC_GLUT_SRAM_L_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_GLUT_SRAM_L_0__TPC_GLUT_0___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_GLUT_SRAM_L_0__TPC_GLUT_0___S 0 + +#define PHYA_PHYRF_TPC_GLUT_SRAM_U_n(n) (0x00480554+0x8*(n)) +#define PHYA_PHYRF_TPC_GLUT_SRAM_U_n_nMIN 0 +#define PHYA_PHYRF_TPC_GLUT_SRAM_U_n_nMAX 0 +#define PHYA_PHYRF_TPC_GLUT_SRAM_U_n_ELEM 1 +#define PHYA_PHYRF_TPC_GLUT_SRAM_U_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_GLUT_SRAM_U_n___POR 0x00000000 +#define PHYA_PHYRF_TPC_GLUT_SRAM_U_n__TPC_GLUT_1___POR 0x00000000 +#define PHYA_PHYRF_TPC_GLUT_SRAM_U_n__TPC_GLUT_1___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_GLUT_SRAM_U_n__TPC_GLUT_1___S 0 +#define PHYA_PHYRF_TPC_GLUT_SRAM_U_n___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_GLUT_SRAM_U_n___S 0 +#define PHYA_PHYRF_TPC_GLUT_SRAM_U_0 (0x00480554) +#define PHYA_PHYRF_TPC_GLUT_SRAM_U_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_GLUT_SRAM_U_0__TPC_GLUT_1___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_GLUT_SRAM_U_0__TPC_GLUT_1___S 0 + +#define PHYA_PHYRF_TPC_PLUT_SRAM_L_n(n) (0x00480B50+0x8*(n)) +#define PHYA_PHYRF_TPC_PLUT_SRAM_L_n_nMIN 0 +#define PHYA_PHYRF_TPC_PLUT_SRAM_L_n_nMAX 0 +#define PHYA_PHYRF_TPC_PLUT_SRAM_L_n_ELEM 1 +#define PHYA_PHYRF_TPC_PLUT_SRAM_L_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_PLUT_SRAM_L_n___POR 0x00000000 +#define PHYA_PHYRF_TPC_PLUT_SRAM_L_n__TPC_PLUT_0___POR 0x00000000 +#define PHYA_PHYRF_TPC_PLUT_SRAM_L_n__TPC_PLUT_0___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_PLUT_SRAM_L_n__TPC_PLUT_0___S 0 +#define PHYA_PHYRF_TPC_PLUT_SRAM_L_n___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_PLUT_SRAM_L_n___S 0 +#define PHYA_PHYRF_TPC_PLUT_SRAM_L_0 (0x00480B50) +#define PHYA_PHYRF_TPC_PLUT_SRAM_L_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_PLUT_SRAM_L_0__TPC_PLUT_0___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_PLUT_SRAM_L_0__TPC_PLUT_0___S 0 + +#define PHYA_PHYRF_TPC_PLUT_SRAM_U_n(n) (0x00480B54+0x8*(n)) +#define PHYA_PHYRF_TPC_PLUT_SRAM_U_n_nMIN 0 +#define PHYA_PHYRF_TPC_PLUT_SRAM_U_n_nMAX 0 +#define PHYA_PHYRF_TPC_PLUT_SRAM_U_n_ELEM 1 +#define PHYA_PHYRF_TPC_PLUT_SRAM_U_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_PLUT_SRAM_U_n___POR 0x00000000 +#define PHYA_PHYRF_TPC_PLUT_SRAM_U_n__TPC_PLUT_1___POR 0x00000000 +#define PHYA_PHYRF_TPC_PLUT_SRAM_U_n__TPC_PLUT_1___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_PLUT_SRAM_U_n__TPC_PLUT_1___S 0 +#define PHYA_PHYRF_TPC_PLUT_SRAM_U_n___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_PLUT_SRAM_U_n___S 0 +#define PHYA_PHYRF_TPC_PLUT_SRAM_U_0 (0x00480B54) +#define PHYA_PHYRF_TPC_PLUT_SRAM_U_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_PLUT_SRAM_U_0__TPC_PLUT_1___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_PLUT_SRAM_U_0__TPC_PLUT_1___S 0 + +#define PHYA_PHYRF_TPC_TXGAIN_SRAM_L_n(n) (0x00481750+0x8*(n)) +#define PHYA_PHYRF_TPC_TXGAIN_SRAM_L_n_nMIN 0 +#define PHYA_PHYRF_TPC_TXGAIN_SRAM_L_n_nMAX 0 +#define PHYA_PHYRF_TPC_TXGAIN_SRAM_L_n_ELEM 1 +#define PHYA_PHYRF_TPC_TXGAIN_SRAM_L_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_TXGAIN_SRAM_L_n___POR 0x00000000 +#define PHYA_PHYRF_TPC_TXGAIN_SRAM_L_n__TPC_TXCAL_TABLE_0___POR 0x00000000 +#define PHYA_PHYRF_TPC_TXGAIN_SRAM_L_n__TPC_TXCAL_TABLE_0___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_TXGAIN_SRAM_L_n__TPC_TXCAL_TABLE_0___S 0 +#define PHYA_PHYRF_TPC_TXGAIN_SRAM_L_n___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_TXGAIN_SRAM_L_n___S 0 +#define PHYA_PHYRF_TPC_TXGAIN_SRAM_L_0 (0x00481750) +#define PHYA_PHYRF_TPC_TXGAIN_SRAM_L_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_TXGAIN_SRAM_L_0__TPC_TXCAL_TABLE_0___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_TXGAIN_SRAM_L_0__TPC_TXCAL_TABLE_0___S 0 + +#define PHYA_PHYRF_TPC_TXGAIN_SRAM_U_n(n) (0x00481754+0x8*(n)) +#define PHYA_PHYRF_TPC_TXGAIN_SRAM_U_n_nMIN 0 +#define PHYA_PHYRF_TPC_TXGAIN_SRAM_U_n_nMAX 0 +#define PHYA_PHYRF_TPC_TXGAIN_SRAM_U_n_ELEM 1 +#define PHYA_PHYRF_TPC_TXGAIN_SRAM_U_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_TXGAIN_SRAM_U_n___POR 0x00000000 +#define PHYA_PHYRF_TPC_TXGAIN_SRAM_U_n__TPC_TXCAL_TABLE_1___POR 0x00000000 +#define PHYA_PHYRF_TPC_TXGAIN_SRAM_U_n__TPC_TXCAL_TABLE_1___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_TXGAIN_SRAM_U_n__TPC_TXCAL_TABLE_1___S 0 +#define PHYA_PHYRF_TPC_TXGAIN_SRAM_U_n___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_TXGAIN_SRAM_U_n___S 0 +#define PHYA_PHYRF_TPC_TXGAIN_SRAM_U_0 (0x00481754) +#define PHYA_PHYRF_TPC_TXGAIN_SRAM_U_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_TXGAIN_SRAM_U_0__TPC_TXCAL_TABLE_1___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_TXGAIN_SRAM_U_0__TPC_TXCAL_TABLE_1___S 0 + +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_L (0x00481890) +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_L___POR 0x0000D3C0 +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_L__PDCCAL_BLOCK_NUM1___POR 0x00 +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_L__PDCCAL_STEP_SIZE1___POR 0x00 +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_L__BLOCK_ACCUM_AVG_ENABLE___POR 0x1 +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_L__BLOCK_ACCUM_NUM_BLOCKS___POR 0xA +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_L__BLOCK_ACCUM_BLOCK_SIZE___POR 0x3C0 +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_L__PDCCAL_BLOCK_NUM1___M 0x0FC00000 +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_L__PDCCAL_BLOCK_NUM1___S 22 +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_L__PDCCAL_STEP_SIZE1___M 0x003F0000 +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_L__PDCCAL_STEP_SIZE1___S 16 +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_L__BLOCK_ACCUM_AVG_ENABLE___M 0x00008000 +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_L__BLOCK_ACCUM_AVG_ENABLE___S 15 +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_L__BLOCK_ACCUM_NUM_BLOCKS___M 0x00007800 +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_L__BLOCK_ACCUM_NUM_BLOCKS___S 11 +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_L__BLOCK_ACCUM_BLOCK_SIZE___M 0x000007FF +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_L__BLOCK_ACCUM_BLOCK_SIZE___S 0 +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_L___M 0x0FFFFFFF +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_L___S 0 + +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_U (0x00481894) +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_U___POR 0xE6B9A000 +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_U__INTDET_DCO_VAR2_FG_FCTR___POR 0x39A +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_U__INTDET_PWR_FG_FCTR___POR 0x39A +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_U__PDCCAL_BLOCK_NUM2___POR 0x00 +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_U__PDCCAL_STEP_SIZE2___POR 0x00 +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_U__INTDET_DCO_VAR2_FG_FCTR___M 0xFFC00000 +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_U__INTDET_DCO_VAR2_FG_FCTR___S 22 +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_U__INTDET_PWR_FG_FCTR___M 0x003FF000 +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_U__INTDET_PWR_FG_FCTR___S 12 +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_U__PDCCAL_BLOCK_NUM2___M 0x00000FC0 +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_U__PDCCAL_BLOCK_NUM2___S 6 +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_U__PDCCAL_STEP_SIZE2___M 0x0000003F +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_U__PDCCAL_STEP_SIZE2___S 0 +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_MEAS_CTRL_0_U___S 0 + +#define PHYA_PHYRF_CAL_MEAS_CTRL_1_L (0x00481898) +#define PHYA_PHYRF_CAL_MEAS_CTRL_1_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_MEAS_CTRL_1_L___POR 0x01E07B9A +#define PHYA_PHYRF_CAL_MEAS_CTRL_1_L__INTDET_DCO_VAR2_DET_M___POR 0x01E +#define PHYA_PHYRF_CAL_MEAS_CTRL_1_L__INTDET_PWR_DET_M___POR 0x01E +#define PHYA_PHYRF_CAL_MEAS_CTRL_1_L__INTDET_DCO_FG_FCTR___POR 0x39A +#define PHYA_PHYRF_CAL_MEAS_CTRL_1_L__INTDET_DCO_VAR2_DET_M___M 0x3FF00000 +#define PHYA_PHYRF_CAL_MEAS_CTRL_1_L__INTDET_DCO_VAR2_DET_M___S 20 +#define PHYA_PHYRF_CAL_MEAS_CTRL_1_L__INTDET_PWR_DET_M___M 0x000FFC00 +#define PHYA_PHYRF_CAL_MEAS_CTRL_1_L__INTDET_PWR_DET_M___S 10 +#define PHYA_PHYRF_CAL_MEAS_CTRL_1_L__INTDET_DCO_FG_FCTR___M 0x000003FF +#define PHYA_PHYRF_CAL_MEAS_CTRL_1_L__INTDET_DCO_FG_FCTR___S 0 +#define PHYA_PHYRF_CAL_MEAS_CTRL_1_L___M 0x3FFFFFFF +#define PHYA_PHYRF_CAL_MEAS_CTRL_1_L___S 0 + +#define PHYA_PHYRF_CAL_MEAS_CTRL_1_U (0x0048189C) +#define PHYA_PHYRF_CAL_MEAS_CTRL_1_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_MEAS_CTRL_1_U___POR 0x00068DB9 +#define PHYA_PHYRF_CAL_MEAS_CTRL_1_U__INTDET_PWR_DET_THR___POR 0x00068DB9 +#define PHYA_PHYRF_CAL_MEAS_CTRL_1_U__INTDET_PWR_DET_THR___M 0x3FFFFFFF +#define PHYA_PHYRF_CAL_MEAS_CTRL_1_U__INTDET_PWR_DET_THR___S 0 +#define PHYA_PHYRF_CAL_MEAS_CTRL_1_U___M 0x3FFFFFFF +#define PHYA_PHYRF_CAL_MEAS_CTRL_1_U___S 0 + +#define PHYA_PHYRF_CAL_MEAS_CTRL_2_L (0x004818A0) +#define PHYA_PHYRF_CAL_MEAS_CTRL_2_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_MEAS_CTRL_2_L___POR 0x00800096 +#define PHYA_PHYRF_CAL_MEAS_CTRL_2_L__INTDET_DCO_DIG_ABS_MIN___POR 0x008 +#define PHYA_PHYRF_CAL_MEAS_CTRL_2_L__INTDET_DCO_VAR2_DET_THR___POR 0x00096 +#define PHYA_PHYRF_CAL_MEAS_CTRL_2_L__INTDET_DCO_DIG_ABS_MIN___M 0xFFF00000 +#define PHYA_PHYRF_CAL_MEAS_CTRL_2_L__INTDET_DCO_DIG_ABS_MIN___S 20 +#define PHYA_PHYRF_CAL_MEAS_CTRL_2_L__INTDET_DCO_VAR2_DET_THR___M 0x000FFFFF +#define PHYA_PHYRF_CAL_MEAS_CTRL_2_L__INTDET_DCO_VAR2_DET_THR___S 0 +#define PHYA_PHYRF_CAL_MEAS_CTRL_2_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_MEAS_CTRL_2_L___S 0 + +#define PHYA_PHYRF_CAL_MEAS_CTRL_2_U (0x004818A4) +#define PHYA_PHYRF_CAL_MEAS_CTRL_2_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_MEAS_CTRL_2_U___POR 0x03E8001E +#define PHYA_PHYRF_CAL_MEAS_CTRL_2_U__INTDET_WATCHDOG_1_MAX___POR 0x3E8 +#define PHYA_PHYRF_CAL_MEAS_CTRL_2_U__INTDET_DCO_AVG_INTERVAL_LEN___POR 0x001E +#define PHYA_PHYRF_CAL_MEAS_CTRL_2_U__INTDET_WATCHDOG_1_MAX___M 0x0FFF0000 +#define PHYA_PHYRF_CAL_MEAS_CTRL_2_U__INTDET_WATCHDOG_1_MAX___S 16 +#define PHYA_PHYRF_CAL_MEAS_CTRL_2_U__INTDET_DCO_AVG_INTERVAL_LEN___M 0x0000FFFF +#define PHYA_PHYRF_CAL_MEAS_CTRL_2_U__INTDET_DCO_AVG_INTERVAL_LEN___S 0 +#define PHYA_PHYRF_CAL_MEAS_CTRL_2_U___M 0x0FFFFFFF +#define PHYA_PHYRF_CAL_MEAS_CTRL_2_U___S 0 + +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_L (0x004818A8) +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_L___POR 0x983E83E8 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_L__CAL_IQ_MEAS_LEN___POR 0x4 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_L__CAL_DC_REMOVE_EN___POR 0x1 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_L__CAL_DC_EST_LEN___POR 0x4 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_L__CAL_MEAS_FIXED_DC___POR 0x0 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_L__CAL_MEM_CLEAR_SIZE___POR 0x0 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_L__INTDET_WATCHDOG_3_MAX___POR 0x3E8 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_L__INTDET_WATCHDOG_2_MAX___POR 0x3E8 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_L__CAL_IQ_MEAS_LEN___M 0xE0000000 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_L__CAL_IQ_MEAS_LEN___S 29 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_L__CAL_DC_REMOVE_EN___M 0x10000000 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_L__CAL_DC_REMOVE_EN___S 28 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_L__CAL_DC_EST_LEN___M 0x0E000000 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_L__CAL_DC_EST_LEN___S 25 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_L__CAL_MEAS_FIXED_DC___M 0x01000000 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_L__CAL_MEAS_FIXED_DC___S 24 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_L__CAL_MEM_CLEAR_SIZE___M 0x00C00000 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_L__CAL_MEM_CLEAR_SIZE___S 22 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_L__INTDET_WATCHDOG_3_MAX___M 0x003FF000 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_L__INTDET_WATCHDOG_3_MAX___S 12 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_L__INTDET_WATCHDOG_2_MAX___M 0x00000FFF +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_L__INTDET_WATCHDOG_2_MAX___S 0 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_L___S 0 + +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U (0x004818AC) +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U___POR 0x02144440 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_FORCED_SQ_IDX___POR 0x00 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_FORCE___POR 0x0 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_NUM_CANDIDATES___POR 0x8 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_MAX_RATIO___POR 0x0A +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_MIN_RATIO___POR 0x04 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_STAGE2_LEN___POR 0x1 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_STAGE1_LEN___POR 0x0 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_TIMING_ONLY___POR 0x0 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_DC_CORR_ENABLE___POR 0x1 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_ADC_SHIFT___POR 0x0 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__CAL_ADC_SHIFT___POR 0x0 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__CAL_TX_PHASE_SEL___POR 0x0 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__TIADCCAL_ADC_PHASE_FLIP___POR 0x0 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_FORCED_SQ_IDX___M 0xF8000000 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_FORCED_SQ_IDX___S 27 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_FORCE___M 0x04000000 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_FORCE___S 26 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_NUM_CANDIDATES___M 0x03C00000 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_NUM_CANDIDATES___S 22 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_MAX_RATIO___M 0x003E0000 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_MAX_RATIO___S 17 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_MIN_RATIO___M 0x0001F000 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_MIN_RATIO___S 12 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_STAGE2_LEN___M 0x00000C00 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_STAGE2_LEN___S 10 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_STAGE1_LEN___M 0x00000300 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_SQ_STAGE1_LEN___S 8 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_TIMING_ONLY___M 0x00000080 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_TIMING_ONLY___S 7 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_DC_CORR_ENABLE___M 0x00000040 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_DC_CORR_ENABLE___S 6 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_ADC_SHIFT___M 0x00000030 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__DPDTRAIN_ADC_SHIFT___S 4 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__CAL_ADC_SHIFT___M 0x0000000C +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__CAL_ADC_SHIFT___S 2 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__CAL_TX_PHASE_SEL___M 0x00000002 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__CAL_TX_PHASE_SEL___S 1 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__TIADCCAL_ADC_PHASE_FLIP___M 0x00000001 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U__TIADCCAL_ADC_PHASE_FLIP___S 0 +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_MEAS_CTRL_3_U___S 0 + +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_L (0x004818B0) +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_L___POR 0x09608000 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_L__DPDTRAIN_NUM_TRAIN_SAMPLES___POR 0x096 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_L__DPDTRAIN_MEM_DDR_HALF_RATE_PHASE___POR 0x0 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_L__DPDTRAIN_MEM_NUM_TRAIN_SAMPLES___POR 0x10 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_L__DPDTRAIN_MEM_CAP_LOG_START_DLY___POR 0x00 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_L__DPDTRAIN_MEM_CAP_LOGMODE___POR 0x0 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_L__DPDTRAIN_NUM_TRAIN_SAMPLES___M 0x3FF00000 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_L__DPDTRAIN_NUM_TRAIN_SAMPLES___S 20 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_L__DPDTRAIN_MEM_DDR_HALF_RATE_PHASE___M 0x00080000 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_L__DPDTRAIN_MEM_DDR_HALF_RATE_PHASE___S 19 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_L__DPDTRAIN_MEM_NUM_TRAIN_SAMPLES___M 0x0007F800 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_L__DPDTRAIN_MEM_NUM_TRAIN_SAMPLES___S 11 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_L__DPDTRAIN_MEM_CAP_LOG_START_DLY___M 0x000007F8 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_L__DPDTRAIN_MEM_CAP_LOG_START_DLY___S 3 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_L__DPDTRAIN_MEM_CAP_LOGMODE___M 0x00000007 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_L__DPDTRAIN_MEM_CAP_LOGMODE___S 0 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_L___M 0x3FFFFFFF +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_L___S 0 + +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_U (0x004818B4) +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_U___POR 0x00000FD5 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_U__DPDTRAIN_RX_DOWNRT_SEL___POR 0x0 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_U__DPDTRAIN_CPT_480___POR 0x0 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_U__CAL_RX_PHASE_SEL___POR 0x0 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_U__CAL_MEAS_CONTROLS_SPARE___POR 0x0000 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_U__DPDTRAIN_CORRELATION_LEN___POR 0x7 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_U__CAL_CORRELATION_LEN___POR 0x7 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_U__DPDTRAIN_MIN_LOOPBACK_DEL___POR 0x15 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_U__DPDTRAIN_RX_DOWNRT_SEL___M 0x40000000 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_U__DPDTRAIN_RX_DOWNRT_SEL___S 30 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_U__DPDTRAIN_CPT_480___M 0x20000000 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_U__DPDTRAIN_CPT_480___S 29 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_U__CAL_RX_PHASE_SEL___M 0x10000000 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_U__CAL_RX_PHASE_SEL___S 28 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_U__CAL_MEAS_CONTROLS_SPARE___M 0x0FFFF000 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_U__CAL_MEAS_CONTROLS_SPARE___S 12 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_U__DPDTRAIN_CORRELATION_LEN___M 0x00000E00 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_U__DPDTRAIN_CORRELATION_LEN___S 9 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_U__CAL_CORRELATION_LEN___M 0x000001C0 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_U__CAL_CORRELATION_LEN___S 6 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_U__DPDTRAIN_MIN_LOOPBACK_DEL___M 0x0000003F +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_U__DPDTRAIN_MIN_LOOPBACK_DEL___S 0 +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_U___M 0x7FFFFFFF +#define PHYA_PHYRF_CAL_MEAS_CTRL_4_U___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_0_L (0x004818B8) +#define PHYA_PHYRF_CAL_SEQ_CTRL_0_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_0_L___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_0_L__CAL_SEQ_CMDS_0___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_0_L__CAL_SEQ_CMDS_0___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_0_L__CAL_SEQ_CMDS_0___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_0_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_0_L___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_0_U (0x004818BC) +#define PHYA_PHYRF_CAL_SEQ_CTRL_0_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_0_U___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_0_U__CAL_SEQ_CMDS_1___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_0_U__CAL_SEQ_CMDS_1___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_0_U__CAL_SEQ_CMDS_1___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_0_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_0_U___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_1_L (0x004818C0) +#define PHYA_PHYRF_CAL_SEQ_CTRL_1_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_1_L___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_1_L__CAL_SEQ_CMDS_2___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_1_L__CAL_SEQ_CMDS_2___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_1_L__CAL_SEQ_CMDS_2___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_1_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_1_L___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_1_U (0x004818C4) +#define PHYA_PHYRF_CAL_SEQ_CTRL_1_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_1_U___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_1_U__CAL_SEQ_CMDS_3___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_1_U__CAL_SEQ_CMDS_3___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_1_U__CAL_SEQ_CMDS_3___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_1_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_1_U___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_2_L (0x004818C8) +#define PHYA_PHYRF_CAL_SEQ_CTRL_2_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_2_L___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_2_L__CAL_SEQ_CMDS_4___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_2_L__CAL_SEQ_CMDS_4___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_2_L__CAL_SEQ_CMDS_4___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_2_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_2_L___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_2_U (0x004818CC) +#define PHYA_PHYRF_CAL_SEQ_CTRL_2_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_2_U___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_2_U__CAL_SEQ_CMDS_5___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_2_U__CAL_SEQ_CMDS_5___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_2_U__CAL_SEQ_CMDS_5___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_2_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_2_U___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_3_L (0x004818D0) +#define PHYA_PHYRF_CAL_SEQ_CTRL_3_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_3_L___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_3_L__CAL_SEQ_CMDS_6___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_3_L__CAL_SEQ_CMDS_6___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_3_L__CAL_SEQ_CMDS_6___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_3_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_3_L___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_3_U (0x004818D4) +#define PHYA_PHYRF_CAL_SEQ_CTRL_3_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_3_U___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_3_U__CAL_SEQ_CMDS_7___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_3_U__CAL_SEQ_CMDS_7___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_3_U__CAL_SEQ_CMDS_7___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_3_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_3_U___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_4_L (0x004818D8) +#define PHYA_PHYRF_CAL_SEQ_CTRL_4_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_4_L___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_4_L__CAL_SEQ_CMDS_8___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_4_L__CAL_SEQ_CMDS_8___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_4_L__CAL_SEQ_CMDS_8___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_4_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_4_L___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_4_U (0x004818DC) +#define PHYA_PHYRF_CAL_SEQ_CTRL_4_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_4_U___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_4_U__CAL_SEQ_CMDS_9___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_4_U__CAL_SEQ_CMDS_9___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_4_U__CAL_SEQ_CMDS_9___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_4_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_4_U___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_5_L (0x004818E0) +#define PHYA_PHYRF_CAL_SEQ_CTRL_5_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_5_L___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_5_L__CAL_SEQ_CMDS_10___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_5_L__CAL_SEQ_CMDS_10___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_5_L__CAL_SEQ_CMDS_10___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_5_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_5_L___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_5_U (0x004818E4) +#define PHYA_PHYRF_CAL_SEQ_CTRL_5_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_5_U___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_5_U__CAL_SEQ_CMDS_11___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_5_U__CAL_SEQ_CMDS_11___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_5_U__CAL_SEQ_CMDS_11___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_5_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_5_U___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_6_L (0x004818E8) +#define PHYA_PHYRF_CAL_SEQ_CTRL_6_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_6_L___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_6_L__CAL_SEQ_CMDS_12___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_6_L__CAL_SEQ_CMDS_12___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_6_L__CAL_SEQ_CMDS_12___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_6_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_6_L___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_6_U (0x004818EC) +#define PHYA_PHYRF_CAL_SEQ_CTRL_6_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_6_U___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_6_U__CAL_SEQ_CMDS_13___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_6_U__CAL_SEQ_CMDS_13___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_6_U__CAL_SEQ_CMDS_13___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_6_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_6_U___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_7_L (0x004818F0) +#define PHYA_PHYRF_CAL_SEQ_CTRL_7_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_7_L___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_7_L__CAL_SEQ_CMDS_14___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_7_L__CAL_SEQ_CMDS_14___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_7_L__CAL_SEQ_CMDS_14___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_7_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_7_L___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_7_U (0x004818F4) +#define PHYA_PHYRF_CAL_SEQ_CTRL_7_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_7_U___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_7_U__CAL_SEQ_CMDS_15___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_7_U__CAL_SEQ_CMDS_15___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_7_U__CAL_SEQ_CMDS_15___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_7_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_7_U___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_8_L (0x004818F8) +#define PHYA_PHYRF_CAL_SEQ_CTRL_8_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_8_L___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_8_L__CAL_SEQ_CMDS_16___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_8_L__CAL_SEQ_CMDS_16___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_8_L__CAL_SEQ_CMDS_16___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_8_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_8_L___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_8_U (0x004818FC) +#define PHYA_PHYRF_CAL_SEQ_CTRL_8_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_8_U___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_8_U__CAL_SEQ_CMDS_17___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_8_U__CAL_SEQ_CMDS_17___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_8_U__CAL_SEQ_CMDS_17___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_8_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_8_U___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_9_L (0x00481900) +#define PHYA_PHYRF_CAL_SEQ_CTRL_9_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_9_L___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_9_L__CAL_SEQ_CMDS_18___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_9_L__CAL_SEQ_CMDS_18___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_9_L__CAL_SEQ_CMDS_18___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_9_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_9_L___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_9_U (0x00481904) +#define PHYA_PHYRF_CAL_SEQ_CTRL_9_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_9_U___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_9_U__CAL_SEQ_CMDS_19___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_9_U__CAL_SEQ_CMDS_19___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_9_U__CAL_SEQ_CMDS_19___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_9_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_9_U___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_10_L (0x00481908) +#define PHYA_PHYRF_CAL_SEQ_CTRL_10_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_10_L___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_10_L__CAL_SEQ_CMDS_20___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_10_L__CAL_SEQ_CMDS_20___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_10_L__CAL_SEQ_CMDS_20___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_10_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_10_L___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_10_U (0x0048190C) +#define PHYA_PHYRF_CAL_SEQ_CTRL_10_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_10_U___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_10_U__CAL_SEQ_CMDS_21___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_10_U__CAL_SEQ_CMDS_21___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_10_U__CAL_SEQ_CMDS_21___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_10_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_10_U___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_11_L (0x00481910) +#define PHYA_PHYRF_CAL_SEQ_CTRL_11_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_11_L___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_11_L__CAL_SEQ_CMDS_22___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_11_L__CAL_SEQ_CMDS_22___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_11_L__CAL_SEQ_CMDS_22___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_11_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_11_L___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_11_U (0x00481914) +#define PHYA_PHYRF_CAL_SEQ_CTRL_11_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_11_U___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_11_U__CAL_SEQ_CMDS_23___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_11_U__CAL_SEQ_CMDS_23___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_11_U__CAL_SEQ_CMDS_23___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_11_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_11_U___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_12_L (0x00481918) +#define PHYA_PHYRF_CAL_SEQ_CTRL_12_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_12_L___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_12_L__CAL_SEQ_CMDS_24___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_12_L__CAL_SEQ_CMDS_24___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_12_L__CAL_SEQ_CMDS_24___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_12_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_12_L___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_12_U (0x0048191C) +#define PHYA_PHYRF_CAL_SEQ_CTRL_12_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_12_U___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_12_U__CAL_SEQ_CMDS_25___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_12_U__CAL_SEQ_CMDS_25___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_12_U__CAL_SEQ_CMDS_25___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_12_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_12_U___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_13_L (0x00481920) +#define PHYA_PHYRF_CAL_SEQ_CTRL_13_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_13_L___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_13_L__CAL_SEQ_CMDS_26___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_13_L__CAL_SEQ_CMDS_26___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_13_L__CAL_SEQ_CMDS_26___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_13_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_13_L___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_13_U (0x00481924) +#define PHYA_PHYRF_CAL_SEQ_CTRL_13_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_13_U___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_13_U__CAL_SEQ_CMDS_27___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_13_U__CAL_SEQ_CMDS_27___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_13_U__CAL_SEQ_CMDS_27___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_13_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_13_U___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_14_L (0x00481928) +#define PHYA_PHYRF_CAL_SEQ_CTRL_14_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_14_L___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_14_L__CAL_SEQ_CMDS_28___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_14_L__CAL_SEQ_CMDS_28___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_14_L__CAL_SEQ_CMDS_28___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_14_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_14_L___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_14_U (0x0048192C) +#define PHYA_PHYRF_CAL_SEQ_CTRL_14_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_14_U___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_14_U__CAL_SEQ_CMDS_29___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_14_U__CAL_SEQ_CMDS_29___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_14_U__CAL_SEQ_CMDS_29___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_14_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_14_U___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_15_L (0x00481930) +#define PHYA_PHYRF_CAL_SEQ_CTRL_15_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_15_L___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_15_L__CAL_SEQ_CMDS_30___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_15_L__CAL_SEQ_CMDS_30___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_15_L__CAL_SEQ_CMDS_30___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_15_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_15_L___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_15_U (0x00481934) +#define PHYA_PHYRF_CAL_SEQ_CTRL_15_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_15_U___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_15_U__CAL_SEQ_CMDS_31___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_15_U__CAL_SEQ_CMDS_31___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_15_U__CAL_SEQ_CMDS_31___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_15_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_15_U___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_L (0x00481938) +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_L___POR 0x80408000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_L__DPDTRAIN_ALLOW___POR 0x1 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_L__CAL_ADC_ON_TO_ADC_STABLE___POR 0x00 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_L__CAL_NUM_TONES___POR 0x40 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_L__CAL_NUM_GAINS___POR 0x10 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_L__CAL_TYPE___POR 0x0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_L__DO_CALIBRATE___POR 0x0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_L__CAL_SEQ_CMDS_NUM___POR 0x00 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_L__DPDTRAIN_ALLOW___M 0x80000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_L__DPDTRAIN_ALLOW___S 31 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_L__CAL_ADC_ON_TO_ADC_STABLE___M 0x7F800000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_L__CAL_ADC_ON_TO_ADC_STABLE___S 23 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_L__CAL_NUM_TONES___M 0x007F0000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_L__CAL_NUM_TONES___S 16 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_L__CAL_NUM_GAINS___M 0x0000F800 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_L__CAL_NUM_GAINS___S 11 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_L__CAL_TYPE___M 0x00000780 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_L__CAL_TYPE___S 7 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_L__DO_CALIBRATE___M 0x00000040 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_L__DO_CALIBRATE___S 6 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_L__CAL_SEQ_CMDS_NUM___M 0x0000003F +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_L__CAL_SEQ_CMDS_NUM___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_L___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_U (0x0048193C) +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_U___POR 0x00000006 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_RX_PHASE_COMP_EN___POR 0x0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_RXIQCORR_SINGLETAP_EN___POR 0x0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_UNFORCE_ADC_BW_DELAY___POR 0x00 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_FORCE_ADC_BW_DELAY___POR 0x00 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_CAL_MODE_ISSUE_DELAY___POR 0x00 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_AGC_START_DELAY___POR 0x06 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_RX_PHASE_COMP_EN___M 0x80000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_RX_PHASE_COMP_EN___S 31 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_RXIQCORR_SINGLETAP_EN___M 0x40000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_RXIQCORR_SINGLETAP_EN___S 30 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_UNFORCE_ADC_BW_DELAY___M 0x3FC00000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_UNFORCE_ADC_BW_DELAY___S 22 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_FORCE_ADC_BW_DELAY___M 0x003FC000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_FORCE_ADC_BW_DELAY___S 14 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_CAL_MODE_ISSUE_DELAY___M 0x00003FC0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_CAL_MODE_ISSUE_DELAY___S 6 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_AGC_START_DELAY___M 0x0000003F +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_U__DPDTRAIN_AGC_START_DELAY___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_16_U___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_L (0x00481940) +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_L___POR 0x00009200 +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_L__CAL_TX_DIG_CL_OFFSET___POR 0x000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_L__IQCAL_INJECT_DIGITAL_OFFSET___POR 0x0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_L__IQCAL_DIG_PHS_MISMATCH___POR 0x012 +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_L__IQCAL_TIMEOUT_DISABLE___POR 0x0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_L__RXDCCAL_2ND_STAGE_ALLOW___POR 0x1 +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_L__DPDTRAIN_RX_PHASE_COMP_VALUE___POR 0x000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_L__CAL_TX_DIG_CL_OFFSET___M 0xFFE00000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_L__CAL_TX_DIG_CL_OFFSET___S 21 +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_L__IQCAL_INJECT_DIGITAL_OFFSET___M 0x00100000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_L__IQCAL_INJECT_DIGITAL_OFFSET___S 20 +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_L__IQCAL_DIG_PHS_MISMATCH___M 0x000FF800 +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_L__IQCAL_DIG_PHS_MISMATCH___S 11 +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_L__IQCAL_TIMEOUT_DISABLE___M 0x00000400 +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_L__IQCAL_TIMEOUT_DISABLE___S 10 +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_L__RXDCCAL_2ND_STAGE_ALLOW___M 0x00000200 +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_L__RXDCCAL_2ND_STAGE_ALLOW___S 9 +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_L__DPDTRAIN_RX_PHASE_COMP_VALUE___M 0x000001FF +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_L__DPDTRAIN_RX_PHASE_COMP_VALUE___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_L___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_U (0x00481944) +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_U___POR 0x10101020 +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_U__CAL_WAIT_TX_SHIFT_SETTLE___POR 0x10 +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_U__CAL_WAIT_TX_GAIN_SETTLE___POR 0x10 +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_U__CAL_WAIT_CAL_MODE_SETTLE___POR 0x10 +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_U__CAL_WAIT_LOOPBACK_SETTLE___POR 0x20 +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_U__CAL_WAIT_TX_SHIFT_SETTLE___M 0xFF000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_U__CAL_WAIT_TX_SHIFT_SETTLE___S 24 +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_U__CAL_WAIT_TX_GAIN_SETTLE___M 0x00FF0000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_U__CAL_WAIT_TX_GAIN_SETTLE___S 16 +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_U__CAL_WAIT_CAL_MODE_SETTLE___M 0x0000FF00 +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_U__CAL_WAIT_CAL_MODE_SETTLE___S 8 +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_U__CAL_WAIT_LOOPBACK_SETTLE___M 0x000000FF +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_U__CAL_WAIT_LOOPBACK_SETTLE___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_17_U___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_18_L (0x00481948) +#define PHYA_PHYRF_CAL_SEQ_CTRL_18_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_18_L___POR 0x10101010 +#define PHYA_PHYRF_CAL_SEQ_CTRL_18_L__CAL_WAIT_TXODAC_SETTLE___POR 0x10 +#define PHYA_PHYRF_CAL_SEQ_CTRL_18_L__CAL_WAIT_RXODAC_SETTLE___POR 0x10 +#define PHYA_PHYRF_CAL_SEQ_CTRL_18_L__CAL_WAIT_PA_SETTLE___POR 0x10 +#define PHYA_PHYRF_CAL_SEQ_CTRL_18_L__CAL_WAIT_TX_RESIDUE_SETTLE___POR 0x10 +#define PHYA_PHYRF_CAL_SEQ_CTRL_18_L__CAL_WAIT_TXODAC_SETTLE___M 0xFF000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_18_L__CAL_WAIT_TXODAC_SETTLE___S 24 +#define PHYA_PHYRF_CAL_SEQ_CTRL_18_L__CAL_WAIT_RXODAC_SETTLE___M 0x00FF0000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_18_L__CAL_WAIT_RXODAC_SETTLE___S 16 +#define PHYA_PHYRF_CAL_SEQ_CTRL_18_L__CAL_WAIT_PA_SETTLE___M 0x0000FF00 +#define PHYA_PHYRF_CAL_SEQ_CTRL_18_L__CAL_WAIT_PA_SETTLE___S 8 +#define PHYA_PHYRF_CAL_SEQ_CTRL_18_L__CAL_WAIT_TX_RESIDUE_SETTLE___M 0x000000FF +#define PHYA_PHYRF_CAL_SEQ_CTRL_18_L__CAL_WAIT_TX_RESIDUE_SETTLE___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_18_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_18_L___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_18_U (0x0048194C) +#define PHYA_PHYRF_CAL_SEQ_CTRL_18_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_18_U___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_18_U__PDCCAL_DELAY3___POR 0x000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_18_U__PDCCAL_DELAY2___POR 0x000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_18_U__PDCCAL_DELAY1___POR 0x000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_18_U__PDCCAL_DELAY3___M 0x3FF00000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_18_U__PDCCAL_DELAY3___S 20 +#define PHYA_PHYRF_CAL_SEQ_CTRL_18_U__PDCCAL_DELAY2___M 0x000FFC00 +#define PHYA_PHYRF_CAL_SEQ_CTRL_18_U__PDCCAL_DELAY2___S 10 +#define PHYA_PHYRF_CAL_SEQ_CTRL_18_U__PDCCAL_DELAY1___M 0x000003FF +#define PHYA_PHYRF_CAL_SEQ_CTRL_18_U__PDCCAL_DELAY1___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_18_U___M 0x3FFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_18_U___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L (0x00481950) +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L___POR 0x661043C0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L__DPDTRAIN_DAC_RATE_OVRD_VAL___POR 0x3 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L__DPDTRAIN_DAC_RATE_OVRD___POR 0x0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L__DPDTRAIN_ADC_RATE_OVRD_VAL___POR 0x3 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L__DPDTRAIN_ADC_RATE_OVRD___POR 0x0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L__DPDTRAIN_ADC_STABLE_WAIT___POR 0x0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L__CAL_DBG_CHAIN_SEL___POR 0x0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L__CAL_DRIVE_TX_GLUT_IDX___POR 0x1 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L__CAL_CLOCK_GATE_DISABLE___POR 0x0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L__CAL_SW_RESET___POR 0x0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L__RXDCCAL_WAIT_AFTER_TIMEOUT___POR 0x10 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L__PDCCAL_WIN_SIZE___POR 0x3C0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L__DPDTRAIN_DAC_RATE_OVRD_VAL___M 0x60000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L__DPDTRAIN_DAC_RATE_OVRD_VAL___S 29 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L__DPDTRAIN_DAC_RATE_OVRD___M 0x10000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L__DPDTRAIN_DAC_RATE_OVRD___S 28 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L__DPDTRAIN_ADC_RATE_OVRD_VAL___M 0x0E000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L__DPDTRAIN_ADC_RATE_OVRD_VAL___S 25 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L__DPDTRAIN_ADC_RATE_OVRD___M 0x01000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L__DPDTRAIN_ADC_RATE_OVRD___S 24 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L__DPDTRAIN_ADC_STABLE_WAIT___M 0x00800000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L__DPDTRAIN_ADC_STABLE_WAIT___S 23 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L__CAL_DBG_CHAIN_SEL___M 0x00600000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L__CAL_DBG_CHAIN_SEL___S 21 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L__CAL_DRIVE_TX_GLUT_IDX___M 0x00100000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L__CAL_DRIVE_TX_GLUT_IDX___S 20 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L__CAL_CLOCK_GATE_DISABLE___M 0x00080000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L__CAL_CLOCK_GATE_DISABLE___S 19 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L__CAL_SW_RESET___M 0x00040000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L__CAL_SW_RESET___S 18 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L__RXDCCAL_WAIT_AFTER_TIMEOUT___M 0x0003FC00 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L__RXDCCAL_WAIT_AFTER_TIMEOUT___S 10 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L__PDCCAL_WIN_SIZE___M 0x000003FF +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L__PDCCAL_WIN_SIZE___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L___M 0x7FFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_L___S 0 + +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_U (0x00481954) +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_U___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_U__CAL_GEN_CONTROLS___POR 0x00000000 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_U__CAL_GEN_CONTROLS___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_U__CAL_GEN_CONTROLS___S 0 +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_SEQ_CTRL_19_U___S 0 + +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_L (0x00481958) +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_L___POR 0x043177DC +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_L__IQCAL_INIT_RX_GAIN_DB___POR 0x21 +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_L__IQCAL_MIN_TX_TONE_DB___POR 0x22 +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_L__IQCAL_MAX_TX_TONE_DB___POR 0x3B +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_L__IQCAL_INIT_TX_TONE_DB___POR 0x3B +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_L__IQCAL_PEAK_EST_LEN___POR 0x4 +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_L__IQCAL_INIT_RX_GAIN_DB___M 0x07E00000 +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_L__IQCAL_INIT_RX_GAIN_DB___S 21 +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_L__IQCAL_MIN_TX_TONE_DB___M 0x001F8000 +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_L__IQCAL_MIN_TX_TONE_DB___S 15 +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_L__IQCAL_MAX_TX_TONE_DB___M 0x00007E00 +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_L__IQCAL_MAX_TX_TONE_DB___S 9 +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_L__IQCAL_INIT_TX_TONE_DB___M 0x000001F8 +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_L__IQCAL_INIT_TX_TONE_DB___S 3 +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_L__IQCAL_PEAK_EST_LEN___M 0x00000007 +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_L__IQCAL_PEAK_EST_LEN___S 0 +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_L___M 0x07FFFFFF +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_L___S 0 + +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_U (0x0048195C) +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_U___POR 0x0DBEF2A1 +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_U__IQCAL_PWR_LOW_DB___POR 0x36 +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_U__IQCAL_PWR_HIGH_DB___POR 0x3E +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_U__IQCAL_MAX_GC_CNT___POR 0xF +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_U__IQCAL_MIN_RX_GAIN_DB___POR 0x0A +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_U__IQCAL_MAX_RX_GAIN_DB___POR 0x21 +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_U__IQCAL_PWR_LOW_DB___M 0x0FC00000 +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_U__IQCAL_PWR_LOW_DB___S 22 +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_U__IQCAL_PWR_HIGH_DB___M 0x003F0000 +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_U__IQCAL_PWR_HIGH_DB___S 16 +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_U__IQCAL_MAX_GC_CNT___M 0x0000F000 +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_U__IQCAL_MAX_GC_CNT___S 12 +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_U__IQCAL_MIN_RX_GAIN_DB___M 0x00000FC0 +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_U__IQCAL_MIN_RX_GAIN_DB___S 6 +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_U__IQCAL_MAX_RX_GAIN_DB___M 0x0000003F +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_U__IQCAL_MAX_RX_GAIN_DB___S 0 +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_U___M 0x0FFFFFFF +#define PHYA_PHYRF_CAL_GAIN_CTRL_0_U___S 0 + +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_L (0x00481960) +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_L___POR 0x0330201A +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_L__DPDTRAIN_ADCSAT_NUM_THR___POR 0x06 +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_ADC_SAT_SEL___POR 0x1 +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_ADC_SAT_LEN___POR 0x4 +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_SCALE_INCLUDED_DC_POWER___POR 0x0 +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_INCLUDE_DC_POWER___POR 0x0 +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_PEAK_EST_CORR_FACTOR___POR 0x4 +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_DC_BACKOFF___POR 0x0 +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_ADCSAT_GAIN_MOD___POR 0x0 +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_DESIRED_SIZE_DB___POR 0x1A +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_L__DPDTRAIN_ADCSAT_NUM_THR___M 0x1F800000 +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_L__DPDTRAIN_ADCSAT_NUM_THR___S 23 +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_ADC_SAT_SEL___M 0x00600000 +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_ADC_SAT_SEL___S 21 +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_ADC_SAT_LEN___M 0x001C0000 +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_ADC_SAT_LEN___S 18 +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_SCALE_INCLUDED_DC_POWER___M 0x00030000 +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_SCALE_INCLUDED_DC_POWER___S 16 +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_INCLUDE_DC_POWER___M 0x00008000 +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_INCLUDE_DC_POWER___S 15 +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_PEAK_EST_CORR_FACTOR___M 0x00007800 +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_PEAK_EST_CORR_FACTOR___S 11 +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_DC_BACKOFF___M 0x00000600 +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_DC_BACKOFF___S 9 +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_ADCSAT_GAIN_MOD___M 0x000001E0 +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_ADCSAT_GAIN_MOD___S 5 +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_DESIRED_SIZE_DB___M 0x0000001F +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_L__IQCAL_DESIRED_SIZE_DB___S 0 +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_L___M 0x1FFFFFFF +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_L___S 0 + +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_U (0x00481964) +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_U___POR 0x0080BF90 +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_U__DPDTRAIN_ADCSAT_THRL___POR 0x101 +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_U__DPDTRAIN_ADCSAT_THRH___POR 0x0FE +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_U__DPDTRAIN_ADCSAT_ICOUNT___POR 0x10 +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_U__DPDTRAIN_ADCSAT_THRL___M 0x00FF8000 +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_U__DPDTRAIN_ADCSAT_THRL___S 15 +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_U__DPDTRAIN_ADCSAT_THRH___M 0x00007FC0 +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_U__DPDTRAIN_ADCSAT_THRH___S 6 +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_U__DPDTRAIN_ADCSAT_ICOUNT___M 0x0000003F +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_U__DPDTRAIN_ADCSAT_ICOUNT___S 0 +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_U___M 0x00FFFFFF +#define PHYA_PHYRF_CAL_GAIN_CTRL_1_U___S 0 + +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_L (0x00481968) +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_L___POR 0x1F88A01E +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_MAX_RXGAIN___POR 0x0F +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_QUICK_DROP___POR 0x31 +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_INIT_RXGAIN___POR 0x0A +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_RXGAIN_FORCE___POR 0x0 +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_RXIQCORR_ENABLE___POR 0x0 +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_WAIT_RXGAIN_SETTLE___POR 0x01E +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_MAX_RXGAIN___M 0xFE000000 +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_MAX_RXGAIN___S 25 +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_QUICK_DROP___M 0x01F80000 +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_QUICK_DROP___S 19 +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_INIT_RXGAIN___M 0x0007F000 +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_INIT_RXGAIN___S 12 +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_RXGAIN_FORCE___M 0x00000800 +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_RXGAIN_FORCE___S 11 +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_RXIQCORR_ENABLE___M 0x00000400 +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_RXIQCORR_ENABLE___S 10 +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_WAIT_RXGAIN_SETTLE___M 0x000003FF +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_L__DPDTRAIN_WAIT_RXGAIN_SETTLE___S 0 +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_L___S 0 + +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_U (0x0048196C) +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_U___POR 0x1AF1F7F7 +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_U__DPDTRAIN_CONSEC_GAIN_CHANGE___POR 0x6 +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_U__DPDTRAIN_CONSEC_PWR_LOW_CNT___POR 0x2 +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_U__DPDTRAIN_PWR_WEAK_DB___POR 0xF1 +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_U__DPDTRAIN_PWR_LOW_DB___POR 0xF7 +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_U__DPDTRAIN_PWR_HIGH_DB___POR 0xF7 +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_U__DPDTRAIN_CONSEC_GAIN_CHANGE___M 0x3C000000 +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_U__DPDTRAIN_CONSEC_GAIN_CHANGE___S 26 +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_U__DPDTRAIN_CONSEC_PWR_LOW_CNT___M 0x03000000 +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_U__DPDTRAIN_CONSEC_PWR_LOW_CNT___S 24 +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_U__DPDTRAIN_PWR_WEAK_DB___M 0x00FF0000 +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_U__DPDTRAIN_PWR_WEAK_DB___S 16 +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_U__DPDTRAIN_PWR_LOW_DB___M 0x0000FF00 +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_U__DPDTRAIN_PWR_LOW_DB___S 8 +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_U__DPDTRAIN_PWR_HIGH_DB___M 0x000000FF +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_U__DPDTRAIN_PWR_HIGH_DB___S 0 +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_U___M 0x3FFFFFFF +#define PHYA_PHYRF_CAL_GAIN_CTRL_2_U___S 0 + +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_L (0x00481970) +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_L___POR 0x20334D34 +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_L__CAL_ADCSAT_ICOUNT___POR 0x10 +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_L__CAL_ADCSAT_NUM_THR___POR 0x06 +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_L__CAL_AGC_FIXED_GAIN___POR 0x0 +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_L__DPDTRAIN_TARGET_LVL_WEAK_DB___POR 0x34 +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_L__DPDTRAIN_TARGET_LVL_LOW_DB___POR 0x34 +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_L__DPDTRAIN_TARGET_LVL_HI_DB___POR 0x34 +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_L__CAL_ADCSAT_ICOUNT___M 0x7E000000 +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_L__CAL_ADCSAT_ICOUNT___S 25 +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_L__CAL_ADCSAT_NUM_THR___M 0x01F80000 +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_L__CAL_ADCSAT_NUM_THR___S 19 +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_L__CAL_AGC_FIXED_GAIN___M 0x00040000 +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_L__CAL_AGC_FIXED_GAIN___S 18 +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_L__DPDTRAIN_TARGET_LVL_WEAK_DB___M 0x0003F000 +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_L__DPDTRAIN_TARGET_LVL_WEAK_DB___S 12 +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_L__DPDTRAIN_TARGET_LVL_LOW_DB___M 0x00000FC0 +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_L__DPDTRAIN_TARGET_LVL_LOW_DB___S 6 +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_L__DPDTRAIN_TARGET_LVL_HI_DB___M 0x0000003F +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_L__DPDTRAIN_TARGET_LVL_HI_DB___S 0 +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_L___M 0x7FFFFFFF +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_L___S 0 + +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_U (0x00481974) +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_U___POR 0x009E02FE +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_U__CAL_WAIT_RXGAIN_SETTLE___POR 0x027 +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_U__CAL_ADCSAT_THRL___POR 0x101 +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_U__CAL_ADCSAT_THRH___POR 0x0FE +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_U__CAL_WAIT_RXGAIN_SETTLE___M 0x0FFC0000 +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_U__CAL_WAIT_RXGAIN_SETTLE___S 18 +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_U__CAL_ADCSAT_THRL___M 0x0003FE00 +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_U__CAL_ADCSAT_THRL___S 9 +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_U__CAL_ADCSAT_THRH___M 0x000001FF +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_U__CAL_ADCSAT_THRH___S 0 +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_U___M 0x0FFFFFFF +#define PHYA_PHYRF_CAL_GAIN_CTRL_3_U___S 0 + +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_L (0x00481978) +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_L___POR 0x1EFEE531 +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_L__CAL_PWR_LOW_DB___POR 0xF7 +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_L__CAL_PWR_HIGH_DB___POR 0xF7 +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_L__CAL_MAX_RXGAIN___POR 0x14 +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_L__CAL_QUICK_DROP___POR 0x31 +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_L__CAL_PWR_LOW_DB___M 0x1FE00000 +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_L__CAL_PWR_LOW_DB___S 21 +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_L__CAL_PWR_HIGH_DB___M 0x001FE000 +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_L__CAL_PWR_HIGH_DB___S 13 +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_L__CAL_MAX_RXGAIN___M 0x00001FC0 +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_L__CAL_MAX_RXGAIN___S 6 +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_L__CAL_QUICK_DROP___M 0x0000003F +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_L__CAL_QUICK_DROP___S 0 +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_L___M 0x1FFFFFFF +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_L___S 0 + +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_U (0x0048197C) +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_U___POR 0x1A68D0F1 +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_TARGET_LVL_LOW_DB___POR 0x34 +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_TARGET_LVL_HI_DB___POR 0x34 +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_CONSEC_GAIN_CHANGE___POR 0x6 +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_CONSEC_PWR_LOW_CNT___POR 0x2 +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_PWR_MEAS_LEN___POR 0x0 +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_PWR_WEAK_DB___POR 0xF1 +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_TARGET_LVL_LOW_DB___M 0x1F800000 +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_TARGET_LVL_LOW_DB___S 23 +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_TARGET_LVL_HI_DB___M 0x007E0000 +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_TARGET_LVL_HI_DB___S 17 +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_CONSEC_GAIN_CHANGE___M 0x0001E000 +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_CONSEC_GAIN_CHANGE___S 13 +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_CONSEC_PWR_LOW_CNT___M 0x00001800 +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_CONSEC_PWR_LOW_CNT___S 11 +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_PWR_MEAS_LEN___M 0x00000700 +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_PWR_MEAS_LEN___S 8 +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_PWR_WEAK_DB___M 0x000000FF +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_U__CAL_PWR_WEAK_DB___S 0 +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_U___M 0x1FFFFFFF +#define PHYA_PHYRF_CAL_GAIN_CTRL_4_U___S 0 + +#define PHYA_PHYRF_CAL_GAIN_CTRL_5_L (0x00481980) +#define PHYA_PHYRF_CAL_GAIN_CTRL_5_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_GAIN_CTRL_5_L___POR 0x00000034 +#define PHYA_PHYRF_CAL_GAIN_CTRL_5_L__CAL_GAIN_CONTROLS_SPARE___POR 0x0000000 +#define PHYA_PHYRF_CAL_GAIN_CTRL_5_L__CAL_TARGET_LVL_WEAK_DB___POR 0x34 +#define PHYA_PHYRF_CAL_GAIN_CTRL_5_L__CAL_GAIN_CONTROLS_SPARE___M 0xFFFFFFC0 +#define PHYA_PHYRF_CAL_GAIN_CTRL_5_L__CAL_GAIN_CONTROLS_SPARE___S 6 +#define PHYA_PHYRF_CAL_GAIN_CTRL_5_L__CAL_TARGET_LVL_WEAK_DB___M 0x0000003F +#define PHYA_PHYRF_CAL_GAIN_CTRL_5_L__CAL_TARGET_LVL_WEAK_DB___S 0 +#define PHYA_PHYRF_CAL_GAIN_CTRL_5_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_GAIN_CTRL_5_L___S 0 + +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_0_L (0x00481988) +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_0_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_0_L___POR 0x00000000 +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_0_L__DPDTRAIN_RXIQCORR_IDX_0___POR 0x00000000 +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_0_L__DPDTRAIN_RXIQCORR_IDX_0___M 0xFFFFFFFF +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_0_L__DPDTRAIN_RXIQCORR_IDX_0___S 0 +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_0_L___M 0xFFFFFFFF +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_0_L___S 0 + +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_0_U (0x0048198C) +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_0_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_0_U___POR 0x00000000 +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_0_U__DPDTRAIN_RXIQCORR_IDX_1___POR 0x00000000 +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_0_U__DPDTRAIN_RXIQCORR_IDX_1___M 0xFFFFFFFF +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_0_U__DPDTRAIN_RXIQCORR_IDX_1___S 0 +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_0_U___M 0xFFFFFFFF +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_0_U___S 0 + +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_1_L (0x00481990) +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_1_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_1_L___POR 0x00000000 +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_1_L__DPDTRAIN_RXIQCORR_IDX_2___POR 0x00000000 +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_1_L__DPDTRAIN_RXIQCORR_IDX_2___M 0xFFFFFFFF +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_1_L__DPDTRAIN_RXIQCORR_IDX_2___S 0 +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_1_L___M 0xFFFFFFFF +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_1_L___S 0 + +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_1_U (0x00481994) +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_1_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_1_U___POR 0x00000000 +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_1_U__DPDTRAIN_RXIQCORR_IDX_3___POR 0x00000000 +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_1_U__DPDTRAIN_RXIQCORR_IDX_3___M 0xFFFFFFFF +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_1_U__DPDTRAIN_RXIQCORR_IDX_3___S 0 +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_1_U___M 0xFFFFFFFF +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_1_U___S 0 + +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_2_L (0x00481998) +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_2_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_2_L___POR 0x00000000 +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_2_L__DPDTRAIN_RXIQCORR_IDX_4___POR 0x00000000 +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_2_L__DPDTRAIN_RXIQCORR_IDX_4___M 0xFFFFFFFF +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_2_L__DPDTRAIN_RXIQCORR_IDX_4___S 0 +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_2_L___M 0xFFFFFFFF +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_2_L___S 0 + +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_2_U (0x0048199C) +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_2_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_2_U___POR 0x00000000 +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_2_U__DPDTRAIN_RXIQCORR_IDX_5___POR 0x00000000 +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_2_U__DPDTRAIN_RXIQCORR_IDX_5___M 0xFFFFFFFF +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_2_U__DPDTRAIN_RXIQCORR_IDX_5___S 0 +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_2_U___M 0xFFFFFFFF +#define PHYA_PHYRF_DPDTRAIN_RXIQCORR_IDX_SET_2_U___S 0 + +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_0_L (0x004819A0) +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_0_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_0_L___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_0_L__CALENGINE0_0_SAVED_GAINS___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_0_L__CALENGINE0_0_SAVED_GAINS___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_0_L__CALENGINE0_0_SAVED_GAINS___S 0 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_0_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_0_L___S 0 + +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_0_U (0x004819A4) +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_0_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_0_U___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_0_U__CALENGINE0_1_SAVED_GAINS___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_0_U__CALENGINE0_1_SAVED_GAINS___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_0_U__CALENGINE0_1_SAVED_GAINS___S 0 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_0_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_0_U___S 0 + +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_1_L (0x004819A8) +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_1_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_1_L___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_1_L__CALENGINE0_2_SAVED_GAINS___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_1_L__CALENGINE0_2_SAVED_GAINS___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_1_L__CALENGINE0_2_SAVED_GAINS___S 0 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_1_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_1_L___S 0 + +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_1_U (0x004819AC) +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_1_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_1_U___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_1_U__CALENGINE0_3_SAVED_GAINS___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_1_U__CALENGINE0_3_SAVED_GAINS___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_1_U__CALENGINE0_3_SAVED_GAINS___S 0 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_1_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_1_U___S 0 + +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_2_L (0x004819B0) +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_2_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_2_L___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_2_L__CALENGINE0_4_SAVED_GAINS___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_2_L__CALENGINE0_4_SAVED_GAINS___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_2_L__CALENGINE0_4_SAVED_GAINS___S 0 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_2_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_2_L___S 0 + +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_2_U (0x004819B4) +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_2_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_2_U___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_2_U__CALENGINE0_5_SAVED_GAINS___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_2_U__CALENGINE0_5_SAVED_GAINS___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_2_U__CALENGINE0_5_SAVED_GAINS___S 0 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_2_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_2_U___S 0 + +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_3_L (0x004819B8) +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_3_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_3_L___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_3_L__CALENGINE0_6_SAVED_GAINS___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_3_L__CALENGINE0_6_SAVED_GAINS___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_3_L__CALENGINE0_6_SAVED_GAINS___S 0 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_3_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_3_L___S 0 + +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_3_U (0x004819BC) +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_3_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_3_U___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_3_U__CALENGINE0_7_SAVED_GAINS___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_3_U__CALENGINE0_7_SAVED_GAINS___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_3_U__CALENGINE0_7_SAVED_GAINS___S 0 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_3_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_3_U___S 0 + +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_4_L (0x004819C0) +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_4_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_4_L___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_4_L__CALENGINE0_8_SAVED_GAINS___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_4_L__CALENGINE0_8_SAVED_GAINS___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_4_L__CALENGINE0_8_SAVED_GAINS___S 0 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_4_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_4_L___S 0 + +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_4_U (0x004819C4) +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_4_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_4_U___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_4_U__CALENGINE0_9_SAVED_GAINS___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_4_U__CALENGINE0_9_SAVED_GAINS___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_4_U__CALENGINE0_9_SAVED_GAINS___S 0 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_4_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_4_U___S 0 + +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_5_L (0x004819C8) +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_5_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_5_L___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_5_L__CALENGINE0_10_SAVED_GAINS___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_5_L__CALENGINE0_10_SAVED_GAINS___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_5_L__CALENGINE0_10_SAVED_GAINS___S 0 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_5_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_5_L___S 0 + +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_5_U (0x004819CC) +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_5_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_5_U___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_5_U__CALENGINE0_11_SAVED_GAINS___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_5_U__CALENGINE0_11_SAVED_GAINS___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_5_U__CALENGINE0_11_SAVED_GAINS___S 0 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_5_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_5_U___S 0 + +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_6_L (0x004819D0) +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_6_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_6_L___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_6_L__CALENGINE0_12_SAVED_GAINS___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_6_L__CALENGINE0_12_SAVED_GAINS___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_6_L__CALENGINE0_12_SAVED_GAINS___S 0 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_6_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_6_L___S 0 + +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_6_U (0x004819D4) +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_6_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_6_U___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_6_U__CALENGINE0_13_SAVED_GAINS___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_6_U__CALENGINE0_13_SAVED_GAINS___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_6_U__CALENGINE0_13_SAVED_GAINS___S 0 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_6_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_6_U___S 0 + +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_7_L (0x004819D8) +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_7_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_7_L___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_7_L__CALENGINE0_14_SAVED_GAINS___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_7_L__CALENGINE0_14_SAVED_GAINS___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_7_L__CALENGINE0_14_SAVED_GAINS___S 0 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_7_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_7_L___S 0 + +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_7_U (0x004819DC) +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_7_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_7_U___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_7_U__CALENGINE0_15_SAVED_GAINS___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_7_U__CALENGINE0_15_SAVED_GAINS___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_7_U__CALENGINE0_15_SAVED_GAINS___S 0 +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_7_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_SAVED_GAINS_7_U___S 0 + +#define PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_0_L (0x004819E0) +#define PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_0_L___RWC QCSR_REG_RO +#define PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_0_L___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_0_L__CALENGINE0_IQCAL_FAILED___POR 0x0 +#define PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_0_L__CALENGINE0_IQCAL_FAILED___M 0x00000001 +#define PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_0_L__CALENGINE0_IQCAL_FAILED___S 0 +#define PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_0_L___M 0x00000001 +#define PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_0_L___S 0 + +#define PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_0_U (0x004819E4) +#define PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_0_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_0_U___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_0_U__CALENGINE0_IQCAL_FAILED_ERROR_CODE___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_0_U__CALENGINE0_IQCAL_FAILED_ERROR_CODE___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_0_U__CALENGINE0_IQCAL_FAILED_ERROR_CODE___S 0 +#define PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_0_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_0_U___S 0 + +#define PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_1_L (0x004819E8) +#define PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_1_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_1_L___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_1_L__CALENGINE0_SAVED_DC_EST_Q___POR 0x000 +#define PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_1_L__CALENGINE0_SAVED_DC_EST_I___POR 0x000 +#define PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_1_L__CALENGINE0_SAVED_DC_EST_Q___M 0x03FF0000 +#define PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_1_L__CALENGINE0_SAVED_DC_EST_Q___S 16 +#define PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_1_L__CALENGINE0_SAVED_DC_EST_I___M 0x000003FF +#define PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_1_L__CALENGINE0_SAVED_DC_EST_I___S 0 +#define PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_1_L___M 0x03FF03FF +#define PHYA_PHYRF_CALENGINE0_ENGINE_CTRL_DBG_1_L___S 0 + +#define PHYA_PHYRF_CALENGINE0_CAL_DEBUG_L (0x004819F0) +#define PHYA_PHYRF_CALENGINE0_CAL_DEBUG_L___RWC QCSR_REG_RO +#define PHYA_PHYRF_CALENGINE0_CAL_DEBUG_L___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_CAL_DEBUG_L__CALENGINE0_CAL_DEBUG_1___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_CAL_DEBUG_L__CALENGINE0_CAL_DEBUG_1___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_CAL_DEBUG_L__CALENGINE0_CAL_DEBUG_1___S 0 +#define PHYA_PHYRF_CALENGINE0_CAL_DEBUG_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_CAL_DEBUG_L___S 0 + +#define PHYA_PHYRF_CALENGINE0_CAL_DEBUG_U (0x004819F4) +#define PHYA_PHYRF_CALENGINE0_CAL_DEBUG_U___RWC QCSR_REG_RO +#define PHYA_PHYRF_CALENGINE0_CAL_DEBUG_U___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_CAL_DEBUG_U__CALENGINE0_CAL_DEBUG_2___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE0_CAL_DEBUG_U__CALENGINE0_CAL_DEBUG_2___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_CAL_DEBUG_U__CALENGINE0_CAL_DEBUG_2___S 0 +#define PHYA_PHYRF_CALENGINE0_CAL_DEBUG_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE0_CAL_DEBUG_U___S 0 + +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_0_L (0x004819F8) +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_0_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_0_L___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_0_L__CALENGINE1_0_SAVED_GAINS___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_0_L__CALENGINE1_0_SAVED_GAINS___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_0_L__CALENGINE1_0_SAVED_GAINS___S 0 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_0_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_0_L___S 0 + +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_0_U (0x004819FC) +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_0_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_0_U___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_0_U__CALENGINE1_1_SAVED_GAINS___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_0_U__CALENGINE1_1_SAVED_GAINS___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_0_U__CALENGINE1_1_SAVED_GAINS___S 0 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_0_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_0_U___S 0 + +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_1_L (0x00481A00) +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_1_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_1_L___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_1_L__CALENGINE1_2_SAVED_GAINS___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_1_L__CALENGINE1_2_SAVED_GAINS___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_1_L__CALENGINE1_2_SAVED_GAINS___S 0 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_1_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_1_L___S 0 + +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_1_U (0x00481A04) +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_1_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_1_U___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_1_U__CALENGINE1_3_SAVED_GAINS___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_1_U__CALENGINE1_3_SAVED_GAINS___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_1_U__CALENGINE1_3_SAVED_GAINS___S 0 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_1_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_1_U___S 0 + +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_2_L (0x00481A08) +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_2_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_2_L___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_2_L__CALENGINE1_4_SAVED_GAINS___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_2_L__CALENGINE1_4_SAVED_GAINS___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_2_L__CALENGINE1_4_SAVED_GAINS___S 0 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_2_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_2_L___S 0 + +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_2_U (0x00481A0C) +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_2_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_2_U___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_2_U__CALENGINE1_5_SAVED_GAINS___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_2_U__CALENGINE1_5_SAVED_GAINS___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_2_U__CALENGINE1_5_SAVED_GAINS___S 0 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_2_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_2_U___S 0 + +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_3_L (0x00481A10) +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_3_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_3_L___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_3_L__CALENGINE1_6_SAVED_GAINS___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_3_L__CALENGINE1_6_SAVED_GAINS___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_3_L__CALENGINE1_6_SAVED_GAINS___S 0 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_3_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_3_L___S 0 + +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_3_U (0x00481A14) +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_3_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_3_U___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_3_U__CALENGINE1_7_SAVED_GAINS___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_3_U__CALENGINE1_7_SAVED_GAINS___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_3_U__CALENGINE1_7_SAVED_GAINS___S 0 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_3_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_3_U___S 0 + +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_4_L (0x00481A18) +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_4_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_4_L___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_4_L__CALENGINE1_8_SAVED_GAINS___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_4_L__CALENGINE1_8_SAVED_GAINS___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_4_L__CALENGINE1_8_SAVED_GAINS___S 0 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_4_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_4_L___S 0 + +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_4_U (0x00481A1C) +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_4_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_4_U___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_4_U__CALENGINE1_9_SAVED_GAINS___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_4_U__CALENGINE1_9_SAVED_GAINS___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_4_U__CALENGINE1_9_SAVED_GAINS___S 0 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_4_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_4_U___S 0 + +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_5_L (0x00481A20) +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_5_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_5_L___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_5_L__CALENGINE1_10_SAVED_GAINS___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_5_L__CALENGINE1_10_SAVED_GAINS___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_5_L__CALENGINE1_10_SAVED_GAINS___S 0 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_5_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_5_L___S 0 + +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_5_U (0x00481A24) +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_5_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_5_U___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_5_U__CALENGINE1_11_SAVED_GAINS___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_5_U__CALENGINE1_11_SAVED_GAINS___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_5_U__CALENGINE1_11_SAVED_GAINS___S 0 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_5_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_5_U___S 0 + +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_6_L (0x00481A28) +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_6_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_6_L___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_6_L__CALENGINE1_12_SAVED_GAINS___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_6_L__CALENGINE1_12_SAVED_GAINS___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_6_L__CALENGINE1_12_SAVED_GAINS___S 0 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_6_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_6_L___S 0 + +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_6_U (0x00481A2C) +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_6_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_6_U___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_6_U__CALENGINE1_13_SAVED_GAINS___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_6_U__CALENGINE1_13_SAVED_GAINS___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_6_U__CALENGINE1_13_SAVED_GAINS___S 0 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_6_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_6_U___S 0 + +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_7_L (0x00481A30) +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_7_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_7_L___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_7_L__CALENGINE1_14_SAVED_GAINS___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_7_L__CALENGINE1_14_SAVED_GAINS___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_7_L__CALENGINE1_14_SAVED_GAINS___S 0 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_7_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_7_L___S 0 + +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_7_U (0x00481A34) +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_7_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_7_U___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_7_U__CALENGINE1_15_SAVED_GAINS___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_7_U__CALENGINE1_15_SAVED_GAINS___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_7_U__CALENGINE1_15_SAVED_GAINS___S 0 +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_7_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_SAVED_GAINS_7_U___S 0 + +#define PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_0_L (0x00481A38) +#define PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_0_L___RWC QCSR_REG_RO +#define PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_0_L___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_0_L__CALENGINE1_IQCAL_FAILED___POR 0x0 +#define PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_0_L__CALENGINE1_IQCAL_FAILED___M 0x00000001 +#define PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_0_L__CALENGINE1_IQCAL_FAILED___S 0 +#define PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_0_L___M 0x00000001 +#define PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_0_L___S 0 + +#define PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_0_U (0x00481A3C) +#define PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_0_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_0_U___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_0_U__CALENGINE1_IQCAL_FAILED_ERROR_CODE___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_0_U__CALENGINE1_IQCAL_FAILED_ERROR_CODE___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_0_U__CALENGINE1_IQCAL_FAILED_ERROR_CODE___S 0 +#define PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_0_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_0_U___S 0 + +#define PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_1_L (0x00481A40) +#define PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_1_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_1_L___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_1_L__CALENGINE1_SAVED_DC_EST_Q___POR 0x000 +#define PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_1_L__CALENGINE1_SAVED_DC_EST_I___POR 0x000 +#define PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_1_L__CALENGINE1_SAVED_DC_EST_Q___M 0x03FF0000 +#define PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_1_L__CALENGINE1_SAVED_DC_EST_Q___S 16 +#define PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_1_L__CALENGINE1_SAVED_DC_EST_I___M 0x000003FF +#define PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_1_L__CALENGINE1_SAVED_DC_EST_I___S 0 +#define PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_1_L___M 0x03FF03FF +#define PHYA_PHYRF_CALENGINE1_ENGINE_CTRL_DBG_1_L___S 0 + +#define PHYA_PHYRF_CALENGINE1_CAL_DEBUG_L (0x00481A48) +#define PHYA_PHYRF_CALENGINE1_CAL_DEBUG_L___RWC QCSR_REG_RO +#define PHYA_PHYRF_CALENGINE1_CAL_DEBUG_L___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_CAL_DEBUG_L__CALENGINE1_CAL_DEBUG_1___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_CAL_DEBUG_L__CALENGINE1_CAL_DEBUG_1___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_CAL_DEBUG_L__CALENGINE1_CAL_DEBUG_1___S 0 +#define PHYA_PHYRF_CALENGINE1_CAL_DEBUG_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_CAL_DEBUG_L___S 0 + +#define PHYA_PHYRF_CALENGINE1_CAL_DEBUG_U (0x00481A4C) +#define PHYA_PHYRF_CALENGINE1_CAL_DEBUG_U___RWC QCSR_REG_RO +#define PHYA_PHYRF_CALENGINE1_CAL_DEBUG_U___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_CAL_DEBUG_U__CALENGINE1_CAL_DEBUG_2___POR 0x00000000 +#define PHYA_PHYRF_CALENGINE1_CAL_DEBUG_U__CALENGINE1_CAL_DEBUG_2___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_CAL_DEBUG_U__CALENGINE1_CAL_DEBUG_2___S 0 +#define PHYA_PHYRF_CALENGINE1_CAL_DEBUG_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CALENGINE1_CAL_DEBUG_U___S 0 + +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_L (0x00481A50) +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_L___POR 0x00000008 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_L__CAL_TONEGEN_FREQ_SECOND___POR 0x000 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_L__CAL_TONEGEN_EN_SECOND___POR 0x0 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_L__CAL_TONEGEN_INIT_PHASE___POR 0x00 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_L__CAL_TONEGEN_FREQ___POR 0x008 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_L__CAL_TONEGEN_FREQ_SECOND___M 0x1FF80000 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_L__CAL_TONEGEN_FREQ_SECOND___S 19 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_L__CAL_TONEGEN_EN_SECOND___M 0x00040000 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_L__CAL_TONEGEN_EN_SECOND___S 18 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_L__CAL_TONEGEN_INIT_PHASE___M 0x0003FC00 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_L__CAL_TONEGEN_INIT_PHASE___S 10 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_L__CAL_TONEGEN_FREQ___M 0x000003FF +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_L__CAL_TONEGEN_FREQ___S 0 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_L___M 0x1FFFFFFF +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_L___S 0 + +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U (0x00481A54) +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U___POR 0x00000000 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U__CAL_TONEGEN_EN_FOURTH___POR 0x0 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U__CAL_TONEGEN_INIT_PHASE_THIRD___POR 0x00 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U__CAL_TONEGEN_FREQ_THIRD___POR 0x000 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U__CAL_TONEGEN_EN_THIRD___POR 0x0 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U__CAL_TONEGEN_INIT_PHASE_SECOND___POR 0x00 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U__CAL_TONEGEN_EN_FOURTH___M 0x08000000 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U__CAL_TONEGEN_EN_FOURTH___S 27 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U__CAL_TONEGEN_INIT_PHASE_THIRD___M 0x07F80000 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U__CAL_TONEGEN_INIT_PHASE_THIRD___S 19 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U__CAL_TONEGEN_FREQ_THIRD___M 0x0007FE00 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U__CAL_TONEGEN_FREQ_THIRD___S 9 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U__CAL_TONEGEN_EN_THIRD___M 0x00000100 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U__CAL_TONEGEN_EN_THIRD___S 8 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U__CAL_TONEGEN_INIT_PHASE_SECOND___M 0x000000FF +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U__CAL_TONEGEN_INIT_PHASE_SECOND___S 0 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U___M 0x0FFFFFFF +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_0_U___S 0 + +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L (0x00481A58) +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L___POR 0x00800000 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_FREQ_INC___POR 0x002 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_DBG_CONT_EN___POR 0x0 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_MAG_SHIFT___POR 0x0 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_NULL_Q_DATA___POR 0x0 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_INIT_PHASE_FOURTH___POR 0x00 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_FREQ_FOURTH___POR 0x000 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_FREQ_INC___M 0xFFC00000 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_FREQ_INC___S 22 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_DBG_CONT_EN___M 0x00200000 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_DBG_CONT_EN___S 21 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_MAG_SHIFT___M 0x00180000 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_MAG_SHIFT___S 19 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_NULL_Q_DATA___M 0x00040000 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_NULL_Q_DATA___S 18 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_INIT_PHASE_FOURTH___M 0x0003FC00 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_INIT_PHASE_FOURTH___S 10 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_FREQ_FOURTH___M 0x000003FF +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L__CAL_TONEGEN_FREQ_FOURTH___S 0 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_1_L___S 0 + +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_1_U (0x00481A5C) +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_1_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_1_U___POR 0x00000002 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_1_U__CAL_TONEGEN_FPREAMBLE___POR 0x002 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_1_U__CAL_TONEGEN_FPREAMBLE___M 0x000003FF +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_1_U__CAL_TONEGEN_FPREAMBLE___S 0 +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_1_U___M 0x000003FF +#define PHYA_PHYRF_CAL_TXSTIM_CTRL_1_U___S 0 + +#define PHYA_PHYRF_CAL_RADIO_CTRL_L (0x00481A60) +#define PHYA_PHYRF_CAL_RADIO_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RADIO_CTRL_L___POR 0x01C3C00F +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__DPDTRAIN_RX_GAIN_TYPE_SEL___POR 0x0 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__DPDTRAIN_RX_VHT160_MODE_SEL___POR 0x0 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__DPDTRAIN_TX_VHT160_MODE_SEL___POR 0x0 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__DPDTRAIN_CAL_MODE_SEL___POR 0x7 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_LPBK_TX_CHAIN_INDICATOR___POR 0x0 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_RF_LPBK_PHASE_SHIFT___POR 0x0 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_TXLO_I_OFFSET_VAL_SEL___POR 0x0 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_PA_EN_OVRD_MASK___POR 0xF +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_RX_GAIN_TYPE_SEL___POR 0x0 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_RX_VHT160_MODE_SEL___POR 0x0 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_TX_VHT160_MODE_SEL___POR 0x0 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_MODE_SEL___POR 0x0 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__RXDCCAL_ODAC_OVRD_MASK___POR 0xF +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__DPDTRAIN_RX_GAIN_TYPE_SEL___M 0xC0000000 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__DPDTRAIN_RX_GAIN_TYPE_SEL___S 30 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__DPDTRAIN_RX_VHT160_MODE_SEL___M 0x30000000 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__DPDTRAIN_RX_VHT160_MODE_SEL___S 28 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__DPDTRAIN_TX_VHT160_MODE_SEL___M 0x0C000000 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__DPDTRAIN_TX_VHT160_MODE_SEL___S 26 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__DPDTRAIN_CAL_MODE_SEL___M 0x03C00000 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__DPDTRAIN_CAL_MODE_SEL___S 22 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_LPBK_TX_CHAIN_INDICATOR___M 0x00200000 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_LPBK_TX_CHAIN_INDICATOR___S 21 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_RF_LPBK_PHASE_SHIFT___M 0x00100000 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_RF_LPBK_PHASE_SHIFT___S 20 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_TXLO_I_OFFSET_VAL_SEL___M 0x000C0000 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_TXLO_I_OFFSET_VAL_SEL___S 18 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_PA_EN_OVRD_MASK___M 0x0003C000 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_PA_EN_OVRD_MASK___S 14 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_RX_GAIN_TYPE_SEL___M 0x00003000 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_RX_GAIN_TYPE_SEL___S 12 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_RX_VHT160_MODE_SEL___M 0x00000C00 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_RX_VHT160_MODE_SEL___S 10 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_TX_VHT160_MODE_SEL___M 0x00000300 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_TX_VHT160_MODE_SEL___S 8 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_MODE_SEL___M 0x000000F0 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__CAL_MODE_SEL___S 4 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__RXDCCAL_ODAC_OVRD_MASK___M 0x0000000F +#define PHYA_PHYRF_CAL_RADIO_CTRL_L__RXDCCAL_ODAC_OVRD_MASK___S 0 +#define PHYA_PHYRF_CAL_RADIO_CTRL_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_RADIO_CTRL_L___S 0 + +#define PHYA_PHYRF_CAL_RADIO_CTRL_U (0x00481A64) +#define PHYA_PHYRF_CAL_RADIO_CTRL_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RADIO_CTRL_U___POR 0x00000A00 +#define PHYA_PHYRF_CAL_RADIO_CTRL_U__CAL_WSI_ISSUE_DISABLE___POR 0x0 +#define PHYA_PHYRF_CAL_RADIO_CTRL_U__RXDCCAL_ODAC_FORMAT_SYMSAT___POR 0x1 +#define PHYA_PHYRF_CAL_RADIO_CTRL_U__RXDCCAL_ODAC_FORMAT_SHIFT___POR 0x100 +#define PHYA_PHYRF_CAL_RADIO_CTRL_U__DPDTRAIN_LPBK_TX_CHAIN_INDICATOR___POR 0x0 +#define PHYA_PHYRF_CAL_RADIO_CTRL_U__CAL_WSI_ISSUE_DISABLE___M 0x00001000 +#define PHYA_PHYRF_CAL_RADIO_CTRL_U__CAL_WSI_ISSUE_DISABLE___S 12 +#define PHYA_PHYRF_CAL_RADIO_CTRL_U__RXDCCAL_ODAC_FORMAT_SYMSAT___M 0x00000800 +#define PHYA_PHYRF_CAL_RADIO_CTRL_U__RXDCCAL_ODAC_FORMAT_SYMSAT___S 11 +#define PHYA_PHYRF_CAL_RADIO_CTRL_U__RXDCCAL_ODAC_FORMAT_SHIFT___M 0x000007FE +#define PHYA_PHYRF_CAL_RADIO_CTRL_U__RXDCCAL_ODAC_FORMAT_SHIFT___S 1 +#define PHYA_PHYRF_CAL_RADIO_CTRL_U__DPDTRAIN_LPBK_TX_CHAIN_INDICATOR___M 0x00000001 +#define PHYA_PHYRF_CAL_RADIO_CTRL_U__DPDTRAIN_LPBK_TX_CHAIN_INDICATOR___S 0 +#define PHYA_PHYRF_CAL_RADIO_CTRL_U___M 0x00001FFF +#define PHYA_PHYRF_CAL_RADIO_CTRL_U___S 0 + +#define PHYA_PHYRF_CAL_CHAIN_SELECT_L (0x00481A68) +#define PHYA_PHYRF_CAL_CHAIN_SELECT_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_CHAIN_SELECT_L___POR 0x0093B13F +#define PHYA_PHYRF_CAL_CHAIN_SELECT_L__DPDTRAIN_ADC_MAP_SEL___POR 0x93 +#define PHYA_PHYRF_CAL_CHAIN_SELECT_L__CAL_ADC_MAP_SEL___POR 0xB1 +#define PHYA_PHYRF_CAL_CHAIN_SELECT_L__CAL_ENGINE_SHARING_CFG___POR 0x0 +#define PHYA_PHYRF_CAL_CHAIN_SELECT_L__DPDTRAIN_WSI_PAIRWISE_BROADCAST_EN___POR 0x1 +#define PHYA_PHYRF_CAL_CHAIN_SELECT_L__CAL_WSI_PAIRWISE_BROADCAST_EN___POR 0x1 +#define PHYA_PHYRF_CAL_CHAIN_SELECT_L__CAL_CHAIN_MASK___POR 0xF +#define PHYA_PHYRF_CAL_CHAIN_SELECT_L__DPDTRAIN_ADC_MAP_SEL___M 0x00FF0000 +#define PHYA_PHYRF_CAL_CHAIN_SELECT_L__DPDTRAIN_ADC_MAP_SEL___S 16 +#define PHYA_PHYRF_CAL_CHAIN_SELECT_L__CAL_ADC_MAP_SEL___M 0x0000FF00 +#define PHYA_PHYRF_CAL_CHAIN_SELECT_L__CAL_ADC_MAP_SEL___S 8 +#define PHYA_PHYRF_CAL_CHAIN_SELECT_L__CAL_ENGINE_SHARING_CFG___M 0x000000C0 +#define PHYA_PHYRF_CAL_CHAIN_SELECT_L__CAL_ENGINE_SHARING_CFG___S 6 +#define PHYA_PHYRF_CAL_CHAIN_SELECT_L__DPDTRAIN_WSI_PAIRWISE_BROADCAST_EN___M 0x00000020 +#define PHYA_PHYRF_CAL_CHAIN_SELECT_L__DPDTRAIN_WSI_PAIRWISE_BROADCAST_EN___S 5 +#define PHYA_PHYRF_CAL_CHAIN_SELECT_L__CAL_WSI_PAIRWISE_BROADCAST_EN___M 0x00000010 +#define PHYA_PHYRF_CAL_CHAIN_SELECT_L__CAL_WSI_PAIRWISE_BROADCAST_EN___S 4 +#define PHYA_PHYRF_CAL_CHAIN_SELECT_L__CAL_CHAIN_MASK___M 0x0000000F +#define PHYA_PHYRF_CAL_CHAIN_SELECT_L__CAL_CHAIN_MASK___S 0 +#define PHYA_PHYRF_CAL_CHAIN_SELECT_L___M 0x00FFFFFF +#define PHYA_PHYRF_CAL_CHAIN_SELECT_L___S 0 + +#define PHYA_PHYRF_CAL_STATUS_DBG_0_L (0x00481A70) +#define PHYA_PHYRF_CAL_STATUS_DBG_0_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_STATUS_DBG_0_L___POR 0x00000000 +#define PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_SM___POR 0x0 +#define PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_TIMING_SM___POR 0x0 +#define PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_AGC_SIZED___POR 0x0 +#define PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_AGC_PWR___POR 0x00 +#define PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_RXGAIN_IDX___POR 0x00 +#define PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_ACTIVE___POR 0x0 +#define PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_INCOMPLETE___POR 0x0 +#define PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_DONE___POR 0x0 +#define PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_SM___M 0x07800000 +#define PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_SM___S 23 +#define PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_TIMING_SM___M 0x00780000 +#define PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_TIMING_SM___S 19 +#define PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_AGC_SIZED___M 0x00040000 +#define PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_AGC_SIZED___S 18 +#define PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_AGC_PWR___M 0x0003FC00 +#define PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_AGC_PWR___S 10 +#define PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_RXGAIN_IDX___M 0x000003F8 +#define PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_RXGAIN_IDX___S 3 +#define PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_ACTIVE___M 0x00000004 +#define PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_ACTIVE___S 2 +#define PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_INCOMPLETE___M 0x00000002 +#define PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_INCOMPLETE___S 1 +#define PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_DONE___M 0x00000001 +#define PHYA_PHYRF_CAL_STATUS_DBG_0_L__DPDTRAIN_DONE___S 0 +#define PHYA_PHYRF_CAL_STATUS_DBG_0_L___M 0x07FFFFFF +#define PHYA_PHYRF_CAL_STATUS_DBG_0_L___S 0 + +#define PHYA_PHYRF_CAL_STATUS_DBG_0_U (0x00481A74) +#define PHYA_PHYRF_CAL_STATUS_DBG_0_U___RWC QCSR_REG_RO +#define PHYA_PHYRF_CAL_STATUS_DBG_0_U___POR 0x00000000 +#define PHYA_PHYRF_CAL_STATUS_DBG_0_U__DPDTRAIN_SQ_IDX___POR 0x00 +#define PHYA_PHYRF_CAL_STATUS_DBG_0_U__DPDTRAIN_SAMPLES_CNT___POR 0x00000 +#define PHYA_PHYRF_CAL_STATUS_DBG_0_U__DPDTRAIN_SQ_IDX___M 0x01F00000 +#define PHYA_PHYRF_CAL_STATUS_DBG_0_U__DPDTRAIN_SQ_IDX___S 20 +#define PHYA_PHYRF_CAL_STATUS_DBG_0_U__DPDTRAIN_SAMPLES_CNT___M 0x000FFFFF +#define PHYA_PHYRF_CAL_STATUS_DBG_0_U__DPDTRAIN_SAMPLES_CNT___S 0 +#define PHYA_PHYRF_CAL_STATUS_DBG_0_U___M 0x01FFFFFF +#define PHYA_PHYRF_CAL_STATUS_DBG_0_U___S 0 + +#define PHYA_PHYRF_CAL_STATUS_DBG_1_L (0x00481A78) +#define PHYA_PHYRF_CAL_STATUS_DBG_1_L___RWC QCSR_REG_RO +#define PHYA_PHYRF_CAL_STATUS_DBG_1_L___POR 0x00000000 +#define PHYA_PHYRF_CAL_STATUS_DBG_1_L__DPDTRAIN_STAGE1_TX_MAX___POR 0x000 +#define PHYA_PHYRF_CAL_STATUS_DBG_1_L__DPDTRAIN_STAGE1_TX_MIN___POR 0x000 +#define PHYA_PHYRF_CAL_STATUS_DBG_1_L__DPDTRAIN_STAGE1_TX_MAX___M 0x00FFF000 +#define PHYA_PHYRF_CAL_STATUS_DBG_1_L__DPDTRAIN_STAGE1_TX_MAX___S 12 +#define PHYA_PHYRF_CAL_STATUS_DBG_1_L__DPDTRAIN_STAGE1_TX_MIN___M 0x00000FFF +#define PHYA_PHYRF_CAL_STATUS_DBG_1_L__DPDTRAIN_STAGE1_TX_MIN___S 0 +#define PHYA_PHYRF_CAL_STATUS_DBG_1_L___M 0x00FFFFFF +#define PHYA_PHYRF_CAL_STATUS_DBG_1_L___S 0 + +#define PHYA_PHYRF_CAL_STATUS_DBG_1_U (0x00481A7C) +#define PHYA_PHYRF_CAL_STATUS_DBG_1_U___RWC QCSR_REG_RO +#define PHYA_PHYRF_CAL_STATUS_DBG_1_U___POR 0x0007FFFF +#define PHYA_PHYRF_CAL_STATUS_DBG_1_U__DPDTRAIN_SQ_VAL___POR 0x07FFFF +#define PHYA_PHYRF_CAL_STATUS_DBG_1_U__DPDTRAIN_SQ_VAL___M 0x007FFFFF +#define PHYA_PHYRF_CAL_STATUS_DBG_1_U__DPDTRAIN_SQ_VAL___S 0 +#define PHYA_PHYRF_CAL_STATUS_DBG_1_U___M 0x007FFFFF +#define PHYA_PHYRF_CAL_STATUS_DBG_1_U___S 0 + +#define PHYA_PHYRF_CAL_STATUS_DBG_2_L (0x00481A80) +#define PHYA_PHYRF_CAL_STATUS_DBG_2_L___RWC QCSR_REG_RO +#define PHYA_PHYRF_CAL_STATUS_DBG_2_L___POR 0x0007FFFF +#define PHYA_PHYRF_CAL_STATUS_DBG_2_L__DPDTRAIN_SQ_VAL_M1___POR 0x07FFFF +#define PHYA_PHYRF_CAL_STATUS_DBG_2_L__DPDTRAIN_SQ_VAL_M1___M 0x007FFFFF +#define PHYA_PHYRF_CAL_STATUS_DBG_2_L__DPDTRAIN_SQ_VAL_M1___S 0 +#define PHYA_PHYRF_CAL_STATUS_DBG_2_L___M 0x007FFFFF +#define PHYA_PHYRF_CAL_STATUS_DBG_2_L___S 0 + +#define PHYA_PHYRF_CAL_STATUS_DBG_2_U (0x00481A84) +#define PHYA_PHYRF_CAL_STATUS_DBG_2_U___RWC QCSR_REG_RO +#define PHYA_PHYRF_CAL_STATUS_DBG_2_U___POR 0x0007FFFF +#define PHYA_PHYRF_CAL_STATUS_DBG_2_U__DPDTRAIN_SQ_VAL_P1___POR 0x07FFFF +#define PHYA_PHYRF_CAL_STATUS_DBG_2_U__DPDTRAIN_SQ_VAL_P1___M 0x007FFFFF +#define PHYA_PHYRF_CAL_STATUS_DBG_2_U__DPDTRAIN_SQ_VAL_P1___S 0 +#define PHYA_PHYRF_CAL_STATUS_DBG_2_U___M 0x007FFFFF +#define PHYA_PHYRF_CAL_STATUS_DBG_2_U___S 0 + +#define PHYA_PHYRF_CAL_STATUS_DBG_3_L (0x00481A88) +#define PHYA_PHYRF_CAL_STATUS_DBG_3_L___RWC QCSR_REG_RO +#define PHYA_PHYRF_CAL_STATUS_DBG_3_L___POR 0x00000000 +#define PHYA_PHYRF_CAL_STATUS_DBG_3_L__DPDTRAIN_LOOPBACK_PHASE_EST___POR 0x000 +#define PHYA_PHYRF_CAL_STATUS_DBG_3_L__DPDTRAIN_LOOPBACK_PHASE_EST___M 0x00000FFF +#define PHYA_PHYRF_CAL_STATUS_DBG_3_L__DPDTRAIN_LOOPBACK_PHASE_EST___S 0 +#define PHYA_PHYRF_CAL_STATUS_DBG_3_L___M 0x00000FFF +#define PHYA_PHYRF_CAL_STATUS_DBG_3_L___S 0 + +#define PHYA_PHYRF_CAL_STATUS_DBG_3_U (0x00481A8C) +#define PHYA_PHYRF_CAL_STATUS_DBG_3_U___RWC QCSR_REG_RO +#define PHYA_PHYRF_CAL_STATUS_DBG_3_U___POR 0x00000000 +#define PHYA_PHYRF_CAL_STATUS_DBG_3_U__DPDTRAIN_DEBUG_1___POR 0x00000000 +#define PHYA_PHYRF_CAL_STATUS_DBG_3_U__DPDTRAIN_DEBUG_1___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_STATUS_DBG_3_U__DPDTRAIN_DEBUG_1___S 0 +#define PHYA_PHYRF_CAL_STATUS_DBG_3_U___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_STATUS_DBG_3_U___S 0 + +#define PHYA_PHYRF_CAL_STATUS_DBG_4_L (0x00481A90) +#define PHYA_PHYRF_CAL_STATUS_DBG_4_L___RWC QCSR_REG_RO +#define PHYA_PHYRF_CAL_STATUS_DBG_4_L___POR 0x00000000 +#define PHYA_PHYRF_CAL_STATUS_DBG_4_L__DPDTRAIN_DEBUG_2___POR 0x00000000 +#define PHYA_PHYRF_CAL_STATUS_DBG_4_L__DPDTRAIN_DEBUG_2___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_STATUS_DBG_4_L__DPDTRAIN_DEBUG_2___S 0 +#define PHYA_PHYRF_CAL_STATUS_DBG_4_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_STATUS_DBG_4_L___S 0 + +#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L (0x00481A98) +#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L___POR 0x0000A198 +#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__DFT_SYMBOL_START_OFFSET___POR 0x000 +#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__DFT_NUM_TONES___POR 0x14 +#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__DFT_SCALING_FACTOR___POR 0x3 +#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__DFT_SKIP_SIZE___POR 0x3 +#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__DFT_SIZE___POR 0x0 +#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__FDMT_IQCAL_DFT_ENABLE___POR 0x0 +#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__DFT_SYMBOL_START_OFFSET___M 0x0FFE0000 +#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__DFT_SYMBOL_START_OFFSET___S 17 +#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__DFT_NUM_TONES___M 0x0001F800 +#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__DFT_NUM_TONES___S 11 +#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__DFT_SCALING_FACTOR___M 0x00000780 +#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__DFT_SCALING_FACTOR___S 7 +#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__DFT_SKIP_SIZE___M 0x00000078 +#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__DFT_SKIP_SIZE___S 3 +#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__DFT_SIZE___M 0x00000006 +#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__DFT_SIZE___S 1 +#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__FDMT_IQCAL_DFT_ENABLE___M 0x00000001 +#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L__FDMT_IQCAL_DFT_ENABLE___S 0 +#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L___M 0x0FFFFFFF +#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_L___S 0 + +#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_U (0x00481A9C) +#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_U___POR 0x00000000 +#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_U__DFT_RESULT_START_ADDR___POR 0x000 +#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_U__TONE_INDEX_START_ADDR___POR 0x000 +#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_U__DFT_RESULT_START_ADDR___M 0x003FF800 +#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_U__DFT_RESULT_START_ADDR___S 11 +#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_U__TONE_INDEX_START_ADDR___M 0x000007FF +#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_U__TONE_INDEX_START_ADDR___S 0 +#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_U___M 0x003FFFFF +#define PHYA_PHYRF_CAL_FDMT_DFT_CTRL_U___S 0 + +#define PHYA_PHYRF_CAL_FDMT_DFT_DBG_L (0x00481AA0) +#define PHYA_PHYRF_CAL_FDMT_DFT_DBG_L___RWC QCSR_REG_RO +#define PHYA_PHYRF_CAL_FDMT_DFT_DBG_L___POR 0x00000000 +#define PHYA_PHYRF_CAL_FDMT_DFT_DBG_L__CAL_FDMT_DFT_DBG_BUS___POR 0x00000000 +#define PHYA_PHYRF_CAL_FDMT_DFT_DBG_L__CAL_FDMT_DFT_DBG_BUS___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_FDMT_DFT_DBG_L__CAL_FDMT_DFT_DBG_BUS___S 0 +#define PHYA_PHYRF_CAL_FDMT_DFT_DBG_L___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_FDMT_DFT_DBG_L___S 0 + +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n(n) (0x00481AA8+0x8*(n)) +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n_nMIN 0 +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n_nMAX 0 +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n_ELEM 1 +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n___POR 0x00000000 +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n__MEM_ADDR___POR 0x0000 +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n__MEM_ADDR___M 0x00003FFF +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n__MEM_ADDR___S 0 +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n___M 0x00003FFF +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_n___S 0 +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_0 (0x00481AA8) +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_0__MEM_ADDR___M 0x00003FFF +#define PHYA_PHYRF_PHYDBG_MEM_ADDR_L_0__MEM_ADDR___S 0 + +#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_n(n) (0x00481AB0+0x8*(n)) +#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_n_nMIN 0 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_n_nMAX 0 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_n_ELEM 1 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_n___POR 0x00000000 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_n__MEM_DATA_L32___POR 0x00000000 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_n__MEM_DATA_L32___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_n__MEM_DATA_L32___S 0 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_n___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_n___S 0 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_0 (0x00481AB0) +#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_0__MEM_DATA_L32___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYDBG_MEM_DATA_L_0__MEM_DATA_L32___S 0 + +#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_n(n) (0x00481AB4+0x8*(n)) +#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_n_nMIN 0 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_n_nMAX 0 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_n_ELEM 1 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_n___POR 0x00000000 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_n__MEM_DATA_U32___POR 0x00000000 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_n__MEM_DATA_U32___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_n__MEM_DATA_U32___S 0 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_n___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_n___S 0 +#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_0 (0x00481AB4) +#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_0__MEM_DATA_U32___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYDBG_MEM_DATA_U_0__MEM_DATA_U32___S 0 + +#define PHYA_PHYRF_PHYDBG_MODE_L (0x00481AD0) +#define PHYA_PHYRF_PHYDBG_MODE_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYDBG_MODE_L___POR 0x00000000 +#define PHYA_PHYRF_PHYDBG_MODE_L__CSR_BANK_ERROR___POR 0x0 +#define PHYA_PHYRF_PHYDBG_MODE_L__CSR_PHYDBG_CLOCKON___POR 0x0 +#define PHYA_PHYRF_PHYDBG_MODE_L__CSR_TRACER_CAPTURE___POR 0x0 +#define PHYA_PHYRF_PHYDBG_MODE_L__CSR_CAPTURE_EVENTS_2BANKS___POR 0x0 +#define PHYA_PHYRF_PHYDBG_MODE_L__CSR_CAPTURE_MODE___POR 0x0 +#define PHYA_PHYRF_PHYDBG_MODE_L__CSR_FTPG_BANK___POR 0x0 +#define PHYA_PHYRF_PHYDBG_MODE_L__CSR_PLAYBACK_BANK___POR 0x0 +#define PHYA_PHYRF_PHYDBG_MODE_L__CSR_CAPTURE_BANK___POR 0x0 +#define PHYA_PHYRF_PHYDBG_MODE_L__CSR_BANK_ERROR___M 0x0003C000 +#define PHYA_PHYRF_PHYDBG_MODE_L__CSR_BANK_ERROR___S 14 +#define PHYA_PHYRF_PHYDBG_MODE_L__CSR_PHYDBG_CLOCKON___M 0x00002000 +#define PHYA_PHYRF_PHYDBG_MODE_L__CSR_PHYDBG_CLOCKON___S 13 +#define PHYA_PHYRF_PHYDBG_MODE_L__CSR_TRACER_CAPTURE___M 0x00001000 +#define PHYA_PHYRF_PHYDBG_MODE_L__CSR_TRACER_CAPTURE___S 12 +#define PHYA_PHYRF_PHYDBG_MODE_L__CSR_CAPTURE_EVENTS_2BANKS___M 0x00000800 +#define PHYA_PHYRF_PHYDBG_MODE_L__CSR_CAPTURE_EVENTS_2BANKS___S 11 +#define PHYA_PHYRF_PHYDBG_MODE_L__CSR_CAPTURE_MODE___M 0x00000600 +#define PHYA_PHYRF_PHYDBG_MODE_L__CSR_CAPTURE_MODE___S 9 +#define PHYA_PHYRF_PHYDBG_MODE_L__CSR_FTPG_BANK___M 0x00000100 +#define PHYA_PHYRF_PHYDBG_MODE_L__CSR_FTPG_BANK___S 8 +#define PHYA_PHYRF_PHYDBG_MODE_L__CSR_PLAYBACK_BANK___M 0x000000F0 +#define PHYA_PHYRF_PHYDBG_MODE_L__CSR_PLAYBACK_BANK___S 4 +#define PHYA_PHYRF_PHYDBG_MODE_L__CSR_CAPTURE_BANK___M 0x0000000F +#define PHYA_PHYRF_PHYDBG_MODE_L__CSR_CAPTURE_BANK___S 0 +#define PHYA_PHYRF_PHYDBG_MODE_L___M 0x0003FFFF +#define PHYA_PHYRF_PHYDBG_MODE_L___S 0 + +#define PHYA_PHYRF_PHYDBG_TRIGGER_0_L (0x00481AD8) +#define PHYA_PHYRF_PHYDBG_TRIGGER_0_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYDBG_TRIGGER_0_L___POR 0x00000000 +#define PHYA_PHYRF_PHYDBG_TRIGGER_0_L__CSR_CAPTURE_TRIG_PATTERN_LO___POR 0x00000000 +#define PHYA_PHYRF_PHYDBG_TRIGGER_0_L__CSR_CAPTURE_TRIG_PATTERN_LO___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYDBG_TRIGGER_0_L__CSR_CAPTURE_TRIG_PATTERN_LO___S 0 +#define PHYA_PHYRF_PHYDBG_TRIGGER_0_L___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYDBG_TRIGGER_0_L___S 0 + +#define PHYA_PHYRF_PHYDBG_TRIGGER_0_U (0x00481ADC) +#define PHYA_PHYRF_PHYDBG_TRIGGER_0_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYDBG_TRIGGER_0_U___POR 0x00000000 +#define PHYA_PHYRF_PHYDBG_TRIGGER_0_U__CSR_CAPTURE_TRIG_MASK_LO___POR 0x00000000 +#define PHYA_PHYRF_PHYDBG_TRIGGER_0_U__CSR_CAPTURE_TRIG_MASK_LO___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYDBG_TRIGGER_0_U__CSR_CAPTURE_TRIG_MASK_LO___S 0 +#define PHYA_PHYRF_PHYDBG_TRIGGER_0_U___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYDBG_TRIGGER_0_U___S 0 + +#define PHYA_PHYRF_PHYDBG_TRIGGER_1_L (0x00481AE0) +#define PHYA_PHYRF_PHYDBG_TRIGGER_1_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYDBG_TRIGGER_1_L___POR 0x00000000 +#define PHYA_PHYRF_PHYDBG_TRIGGER_1_L__CSR_CAPTURE_TRIG_COND___POR 0x00 +#define PHYA_PHYRF_PHYDBG_TRIGGER_1_L__CSR_CAPTURE_TRIG_MASK_HI___POR 0x00 +#define PHYA_PHYRF_PHYDBG_TRIGGER_1_L__CSR_CAPTURE_TRIG_PATTERN_HI___POR 0x00 +#define PHYA_PHYRF_PHYDBG_TRIGGER_1_L__CSR_CAPTURE_TRIG_COND___M 0x00FF0000 +#define PHYA_PHYRF_PHYDBG_TRIGGER_1_L__CSR_CAPTURE_TRIG_COND___S 16 +#define PHYA_PHYRF_PHYDBG_TRIGGER_1_L__CSR_CAPTURE_TRIG_MASK_HI___M 0x0000FF00 +#define PHYA_PHYRF_PHYDBG_TRIGGER_1_L__CSR_CAPTURE_TRIG_MASK_HI___S 8 +#define PHYA_PHYRF_PHYDBG_TRIGGER_1_L__CSR_CAPTURE_TRIG_PATTERN_HI___M 0x000000FF +#define PHYA_PHYRF_PHYDBG_TRIGGER_1_L__CSR_CAPTURE_TRIG_PATTERN_HI___S 0 +#define PHYA_PHYRF_PHYDBG_TRIGGER_1_L___M 0x00FFFFFF +#define PHYA_PHYRF_PHYDBG_TRIGGER_1_L___S 0 + +#define PHYA_PHYRF_PHYDBG_PLAYBACK_L (0x00481AE8) +#define PHYA_PHYRF_PHYDBG_PLAYBACK_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYDBG_PLAYBACK_L___POR 0x00000000 +#define PHYA_PHYRF_PHYDBG_PLAYBACK_L__CSR_PLAYBACK_COUNT_B___POR 0x0000 +#define PHYA_PHYRF_PHYDBG_PLAYBACK_L__CSR_PLAYBACK_COUNT_A___POR 0x0000 +#define PHYA_PHYRF_PHYDBG_PLAYBACK_L__CSR_PLAYBACK_COUNT_B___M 0xFFFF0000 +#define PHYA_PHYRF_PHYDBG_PLAYBACK_L__CSR_PLAYBACK_COUNT_B___S 16 +#define PHYA_PHYRF_PHYDBG_PLAYBACK_L__CSR_PLAYBACK_COUNT_A___M 0x0000FFFF +#define PHYA_PHYRF_PHYDBG_PLAYBACK_L__CSR_PLAYBACK_COUNT_A___S 0 +#define PHYA_PHYRF_PHYDBG_PLAYBACK_L___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYDBG_PLAYBACK_L___S 0 + +#define PHYA_PHYRF_PHYDBG_PLAYBACK_U (0x00481AEC) +#define PHYA_PHYRF_PHYDBG_PLAYBACK_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYDBG_PLAYBACK_U___POR 0x10000000 +#define PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_EN___POR 0x0 +#define PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_ON_BOTH_SPLIT_PHYS___POR 0x0 +#define PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_FIFO_TH___POR 0x8 +#define PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_TRIGGER___POR 0x0 +#define PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_LOOP_COUNT___POR 0x00 +#define PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_MEM_DEPTH___POR 0x0000 +#define PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_EN___M 0x40000000 +#define PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_EN___S 30 +#define PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_ON_BOTH_SPLIT_PHYS___M 0x20000000 +#define PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_ON_BOTH_SPLIT_PHYS___S 29 +#define PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_FIFO_TH___M 0x1E000000 +#define PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_FIFO_TH___S 25 +#define PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_TRIGGER___M 0x01000000 +#define PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_TRIGGER___S 24 +#define PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_LOOP_COUNT___M 0x00FF0000 +#define PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_LOOP_COUNT___S 16 +#define PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_MEM_DEPTH___M 0x0000FFFF +#define PHYA_PHYRF_PHYDBG_PLAYBACK_U__CSR_PLAYBACK_MEM_DEPTH___S 0 +#define PHYA_PHYRF_PHYDBG_PLAYBACK_U___M 0x7FFFFFFF +#define PHYA_PHYRF_PHYDBG_PLAYBACK_U___S 0 + +#define PHYA_PHYRF_PHYDBG_CAPTURE_L (0x00481AF0) +#define PHYA_PHYRF_PHYDBG_CAPTURE_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYDBG_CAPTURE_L___POR 0x00000000 +#define PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_CAPTURE_EVENT_MASK___POR 0x0000 +#define PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_CAPTURE_BYPASS_TS_REORDERING___POR 0x0 +#define PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_CAPTURE_STOPONTRIG___POR 0x0 +#define PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_ADC_IQ_SELECTIVE___POR 0x0 +#define PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_ADC_SIDEBAND___POR 0x0 +#define PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_ADC_CHAIN_MASK___POR 0x0 +#define PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_CAPTURE_EVENT_MASK___M 0x07FFF800 +#define PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_CAPTURE_EVENT_MASK___S 11 +#define PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_CAPTURE_BYPASS_TS_REORDERING___M 0x00000400 +#define PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_CAPTURE_BYPASS_TS_REORDERING___S 10 +#define PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_CAPTURE_STOPONTRIG___M 0x00000200 +#define PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_CAPTURE_STOPONTRIG___S 9 +#define PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_ADC_IQ_SELECTIVE___M 0x00000180 +#define PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_ADC_IQ_SELECTIVE___S 7 +#define PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_ADC_SIDEBAND___M 0x00000070 +#define PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_ADC_SIDEBAND___S 4 +#define PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_ADC_CHAIN_MASK___M 0x0000000F +#define PHYA_PHYRF_PHYDBG_CAPTURE_L__CSR_ADC_CHAIN_MASK___S 0 +#define PHYA_PHYRF_PHYDBG_CAPTURE_L___M 0x07FFFFFF +#define PHYA_PHYRF_PHYDBG_CAPTURE_L___S 0 + +#define PHYA_PHYRF_PHYDBG_CAPTURE_U (0x00481AF4) +#define PHYA_PHYRF_PHYDBG_CAPTURE_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYDBG_CAPTURE_U___POR 0x00000000 +#define PHYA_PHYRF_PHYDBG_CAPTURE_U__CSR_CAPTURE_EN___POR 0x0 +#define PHYA_PHYRF_PHYDBG_CAPTURE_U__CSR_CAPTURE_PRETRIG___POR 0x0000 +#define PHYA_PHYRF_PHYDBG_CAPTURE_U__CSR_CAPTURE_EN___M 0x00004000 +#define PHYA_PHYRF_PHYDBG_CAPTURE_U__CSR_CAPTURE_EN___S 14 +#define PHYA_PHYRF_PHYDBG_CAPTURE_U__CSR_CAPTURE_PRETRIG___M 0x00003FFF +#define PHYA_PHYRF_PHYDBG_CAPTURE_U__CSR_CAPTURE_PRETRIG___S 0 +#define PHYA_PHYRF_PHYDBG_CAPTURE_U___M 0x00007FFF +#define PHYA_PHYRF_PHYDBG_CAPTURE_U___S 0 + +#define PHYA_PHYRF_PHYRF_WDOG_L (0x00481AF8) +#define PHYA_PHYRF_PHYRF_WDOG_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_WDOG_L___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_WDOG_L__CSR_PHYRF_WDOG_CONFIG___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_WDOG_L__CSR_PHYRF_WDOG_CONFIG___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_WDOG_L__CSR_PHYRF_WDOG_CONFIG___S 0 +#define PHYA_PHYRF_PHYRF_WDOG_L___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_WDOG_L___S 0 + +#define PHYA_PHYRF_PHYRF_WDOG_U (0x00481AFC) +#define PHYA_PHYRF_PHYRF_WDOG_U___RWC QCSR_REG_RO +#define PHYA_PHYRF_PHYRF_WDOG_U___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_WDOG_U__CSR_PHYRF_WDOG_STATUS___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_WDOG_U__CSR_PHYRF_WDOG_STATUS___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_WDOG_U__CSR_PHYRF_WDOG_STATUS___S 0 +#define PHYA_PHYRF_PHYRF_WDOG_U___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_WDOG_U___S 0 + +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L (0x00481B00) +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L___POR 0x30C08030 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__TIMER_THR3___POR 0x18 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__TIMER_THR2___POR 0x18 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__TIMER_THR1___POR 0x04 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__FORCED_WSI_SYN_VAL___POR 0x0 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__USE_FORCED_WSI_SYN_VAL___POR 0x0 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__SATURATE_CYCLE_CNT___POR 0x0 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__STAT_FREEZE___POR 0x0 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__STAT_CLEAR___POR 0x0 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__FILTER_OUT_NON_INBOUND_HT_PKT___POR 0x1 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__ALLOW_WSI_CMD_DURING_TXRX___POR 0x1 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__MODE_PRIORITY___POR 0x0 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__DTIM_MODE___POR 0x0 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__SYNTH_SWITCH_SOFT_RESET___POR 0x0 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__SYNTH_SWITCH_ENABLE___POR 0x0 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__TIMER_THR3___M 0x7E000000 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__TIMER_THR3___S 25 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__TIMER_THR2___M 0x01F80000 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__TIMER_THR2___S 19 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__TIMER_THR1___M 0x0007E000 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__TIMER_THR1___S 13 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__FORCED_WSI_SYN_VAL___M 0x00001C00 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__FORCED_WSI_SYN_VAL___S 10 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__USE_FORCED_WSI_SYN_VAL___M 0x00000200 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__USE_FORCED_WSI_SYN_VAL___S 9 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__SATURATE_CYCLE_CNT___M 0x00000100 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__SATURATE_CYCLE_CNT___S 8 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__STAT_FREEZE___M 0x00000080 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__STAT_FREEZE___S 7 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__STAT_CLEAR___M 0x00000040 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__STAT_CLEAR___S 6 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__FILTER_OUT_NON_INBOUND_HT_PKT___M 0x00000020 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__FILTER_OUT_NON_INBOUND_HT_PKT___S 5 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__ALLOW_WSI_CMD_DURING_TXRX___M 0x00000010 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__ALLOW_WSI_CMD_DURING_TXRX___S 4 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__MODE_PRIORITY___M 0x00000008 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__MODE_PRIORITY___S 3 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__DTIM_MODE___M 0x00000004 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__DTIM_MODE___S 2 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__SYNTH_SWITCH_SOFT_RESET___M 0x00000002 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__SYNTH_SWITCH_SOFT_RESET___S 1 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__SYNTH_SWITCH_ENABLE___M 0x00000001 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L__SYNTH_SWITCH_ENABLE___S 0 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L___M 0x7FFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_L___S 0 + +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_U (0x00481B04) +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_U___POR 0x4FDFC298 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_U__STAT_UNIT_DUR___POR 0x13F +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_U__USEC_DUR___POR 0x7F +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_U__RSSI_DB_THR___POR 0x0A +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_U__TIMER_THR4___POR 0x18 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_U__STAT_UNIT_DUR___M 0x7FC00000 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_U__STAT_UNIT_DUR___S 22 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_U__USEC_DUR___M 0x003FC000 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_U__USEC_DUR___S 14 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_U__RSSI_DB_THR___M 0x00003FC0 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_U__RSSI_DB_THR___S 6 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_U__TIMER_THR4___M 0x0000003F +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_U__TIMER_THR4___S 0 +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_U___M 0x7FFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_CTRL_U___S 0 + +#define PHYA_PHYRF_SYNTH_SWITCH_SLEEP_L (0x00481B08) +#define PHYA_PHYRF_SYNTH_SWITCH_SLEEP_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_SYNTH_SWITCH_SLEEP_L___POR 0x00000000 +#define PHYA_PHYRF_SYNTH_SWITCH_SLEEP_L__PHY_SLEEP___POR 0x0 +#define PHYA_PHYRF_SYNTH_SWITCH_SLEEP_L__PHY_SLEEP___M 0x00000001 +#define PHYA_PHYRF_SYNTH_SWITCH_SLEEP_L__PHY_SLEEP___S 0 +#define PHYA_PHYRF_SYNTH_SWITCH_SLEEP_L___M 0x00000001 +#define PHYA_PHYRF_SYNTH_SWITCH_SLEEP_L___S 0 + +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_0_L (0x00481B10) +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_0_L___RWC QCSR_REG_RO +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_0_L___POR 0x00000000 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_0_L__CYCLE_CNT___POR 0x00000000 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_0_L__CYCLE_CNT___M 0xFFFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_0_L__CYCLE_CNT___S 0 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_0_L___M 0xFFFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_0_L___S 0 + +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_10_L (0x00481B18) +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_10_L___RWC QCSR_REG_RO +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_10_L___POR 0x00000000 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_10_L__STATE_CNT_0_0___POR 0x00000000 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_10_L__STATE_CNT_0_0___M 0xFFFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_10_L__STATE_CNT_0_0___S 0 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_10_L___M 0xFFFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_10_L___S 0 + +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_10_U (0x00481B1C) +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_10_U___RWC QCSR_REG_RO +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_10_U___POR 0x00000000 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_10_U__STATE_CNT_1_0___POR 0x00000000 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_10_U__STATE_CNT_1_0___M 0xFFFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_10_U__STATE_CNT_1_0___S 0 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_10_U___M 0xFFFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_10_U___S 0 + +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_11_L (0x00481B20) +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_11_L___RWC QCSR_REG_RO +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_11_L___POR 0x00000000 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_11_L__STATE_CNT_0_1___POR 0x00000000 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_11_L__STATE_CNT_0_1___M 0xFFFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_11_L__STATE_CNT_0_1___S 0 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_11_L___M 0xFFFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_11_L___S 0 + +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_11_U (0x00481B24) +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_11_U___RWC QCSR_REG_RO +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_11_U___POR 0x00000000 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_11_U__STATE_CNT_1_1___POR 0x00000000 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_11_U__STATE_CNT_1_1___M 0xFFFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_11_U__STATE_CNT_1_1___S 0 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_11_U___M 0xFFFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_11_U___S 0 + +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_12_L (0x00481B28) +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_12_L___RWC QCSR_REG_RO +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_12_L___POR 0x00000000 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_12_L__STATE_CNT_0_2___POR 0x00000000 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_12_L__STATE_CNT_0_2___M 0xFFFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_12_L__STATE_CNT_0_2___S 0 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_12_L___M 0xFFFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_12_L___S 0 + +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_12_U (0x00481B2C) +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_12_U___RWC QCSR_REG_RO +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_12_U___POR 0x00000000 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_12_U__STATE_CNT_1_2___POR 0x00000000 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_12_U__STATE_CNT_1_2___M 0xFFFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_12_U__STATE_CNT_1_2___S 0 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_12_U___M 0xFFFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_12_U___S 0 + +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_13_L (0x00481B30) +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_13_L___RWC QCSR_REG_RO +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_13_L___POR 0x00000000 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_13_L__STATE_CNT_0_3___POR 0x00000000 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_13_L__STATE_CNT_0_3___M 0xFFFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_13_L__STATE_CNT_0_3___S 0 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_13_L___M 0xFFFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_13_L___S 0 + +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_13_U (0x00481B34) +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_13_U___RWC QCSR_REG_RO +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_13_U___POR 0x00000000 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_13_U__STATE_CNT_1_3___POR 0x00000000 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_13_U__STATE_CNT_1_3___M 0xFFFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_13_U__STATE_CNT_1_3___S 0 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_13_U___M 0xFFFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_13_U___S 0 + +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_2_L (0x00481B38) +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_2_L___RWC QCSR_REG_RO +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_2_L___POR 0x00000000 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_2_L__RX_FRAME_MOD_CNT___POR 0x00000000 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_2_L__RX_FRAME_MOD_CNT___M 0xFFFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_2_L__RX_FRAME_MOD_CNT___S 0 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_2_L___M 0xFFFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_2_L___S 0 + +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_2_U (0x00481B3C) +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_2_U___RWC QCSR_REG_RO +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_2_U___POR 0x00000000 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_2_U__TX_EN_CNT___POR 0x00000000 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_2_U__TX_EN_CNT___M 0xFFFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_2_U__TX_EN_CNT___S 0 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_2_U___M 0xFFFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_2_U___S 0 + +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_3_L (0x00481B40) +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_3_L___RWC QCSR_REG_RO +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_3_L___POR 0x00000000 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_3_L__TX_EN_AFTER_WARMUP_CNT___POR 0x00000000 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_3_L__TX_EN_AFTER_WARMUP_CNT___M 0xFFFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_3_L__TX_EN_AFTER_WARMUP_CNT___S 0 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_3_L___M 0xFFFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_3_L___S 0 + +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_3_U (0x00481B44) +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_3_U___RWC QCSR_REG_RO +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_3_U___POR 0x00000000 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_3_U__TX_ABORT_AFTER_WARMUP_CNT___POR 0x00000000 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_3_U__TX_ABORT_AFTER_WARMUP_CNT___M 0xFFFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_3_U__TX_ABORT_AFTER_WARMUP_CNT___S 0 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_3_U___M 0xFFFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_3_U___S 0 + +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_4_L (0x00481B48) +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_4_L___RWC QCSR_REG_RO +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_4_L___POR 0x00000000 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_4_L__LP_RX_AFTER_WARMUP_CNT___POR 0x00000000 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_4_L__LP_RX_AFTER_WARMUP_CNT___M 0xFFFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_4_L__LP_RX_AFTER_WARMUP_CNT___S 0 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_4_L___M 0xFFFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_4_L___S 0 + +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_4_U (0x00481B4C) +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_4_U___RWC QCSR_REG_RO +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_4_U___POR 0x00000000 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_4_U__RX_ABORT_AFTER_WARMUP_CNT___POR 0x00000000 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_4_U__RX_ABORT_AFTER_WARMUP_CNT___M 0xFFFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_4_U__RX_ABORT_AFTER_WARMUP_CNT___S 0 +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_4_U___M 0xFFFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_STAT_4_U___S 0 + +#define PHYA_PHYRF_SYNTH_SWITCH_DBG_L (0x00481B50) +#define PHYA_PHYRF_SYNTH_SWITCH_DBG_L___RWC QCSR_REG_RO +#define PHYA_PHYRF_SYNTH_SWITCH_DBG_L___POR 0x00000801 +#define PHYA_PHYRF_SYNTH_SWITCH_DBG_L__SYNTH_DBG_BUS_0___POR 0x00000801 +#define PHYA_PHYRF_SYNTH_SWITCH_DBG_L__SYNTH_DBG_BUS_0___M 0xFFFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_DBG_L__SYNTH_DBG_BUS_0___S 0 +#define PHYA_PHYRF_SYNTH_SWITCH_DBG_L___M 0xFFFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_DBG_L___S 0 + +#define PHYA_PHYRF_SYNTH_SWITCH_DBG_U (0x00481B54) +#define PHYA_PHYRF_SYNTH_SWITCH_DBG_U___RWC QCSR_REG_RO +#define PHYA_PHYRF_SYNTH_SWITCH_DBG_U___POR 0x00000000 +#define PHYA_PHYRF_SYNTH_SWITCH_DBG_U__SYNTH_DBG_BUS_1___POR 0x00000000 +#define PHYA_PHYRF_SYNTH_SWITCH_DBG_U__SYNTH_DBG_BUS_1___M 0xFFFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_DBG_U__SYNTH_DBG_BUS_1___S 0 +#define PHYA_PHYRF_SYNTH_SWITCH_DBG_U___M 0xFFFFFFFF +#define PHYA_PHYRF_SYNTH_SWITCH_DBG_U___S 0 + +#define PHYA_PHYRF_OCL_CONFIG_L (0x00481B58) +#define PHYA_PHYRF_OCL_CONFIG_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_OCL_CONFIG_L___POR 0x0000000A +#define PHYA_PHYRF_OCL_CONFIG_L__OCL_RX_ON_TO_ADC_ON___POR 0x0A +#define PHYA_PHYRF_OCL_CONFIG_L__OCL_RX_ON_TO_ADC_ON___M 0x0000003F +#define PHYA_PHYRF_OCL_CONFIG_L__OCL_RX_ON_TO_ADC_ON___S 0 +#define PHYA_PHYRF_OCL_CONFIG_L___M 0x0000003F +#define PHYA_PHYRF_OCL_CONFIG_L___S 0 + +#define PHYA_PHYRF_PHYRF_PUBLIC_SPARE_L (0x00481B60) +#define PHYA_PHYRF_PHYRF_PUBLIC_SPARE_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_PUBLIC_SPARE_L___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_PUBLIC_SPARE_L__PHYRF_PUBLIC_SPARE_0___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_PUBLIC_SPARE_L__PHYRF_PUBLIC_SPARE_0___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_PUBLIC_SPARE_L__PHYRF_PUBLIC_SPARE_0___S 0 +#define PHYA_PHYRF_PHYRF_PUBLIC_SPARE_L___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_PUBLIC_SPARE_L___S 0 + +#define PHYA_PHYRF_PHYRF_PUBLIC_SPARE_U (0x00481B64) +#define PHYA_PHYRF_PHYRF_PUBLIC_SPARE_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_PUBLIC_SPARE_U___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_PUBLIC_SPARE_U__PHYRF_PUBLIC_SPARE_1___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_PUBLIC_SPARE_U__PHYRF_PUBLIC_SPARE_1___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_PUBLIC_SPARE_U__PHYRF_PUBLIC_SPARE_1___S 0 +#define PHYA_PHYRF_PHYRF_PUBLIC_SPARE_U___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_PUBLIC_SPARE_U___S 0 + +#define PHYA_PHYRF_PHYRF_DUMMY_STATIC_PRIVATE_CSR_L (0x00481B68) +#define PHYA_PHYRF_PHYRF_DUMMY_STATIC_PRIVATE_CSR_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_DUMMY_STATIC_PRIVATE_CSR_L___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_DUMMY_STATIC_PRIVATE_CSR_L__PHYRF_DUMMY_STATIC_PRIVATE_CSR___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_DUMMY_STATIC_PRIVATE_CSR_L__PHYRF_DUMMY_STATIC_PRIVATE_CSR___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_DUMMY_STATIC_PRIVATE_CSR_L__PHYRF_DUMMY_STATIC_PRIVATE_CSR___S 0 +#define PHYA_PHYRF_PHYRF_DUMMY_STATIC_PRIVATE_CSR_L___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_DUMMY_STATIC_PRIVATE_CSR_L___S 0 + +#define PHYA_PHYRF_PHYRF_PRIVATE_SPARE_L (0x00481B70) +#define PHYA_PHYRF_PHYRF_PRIVATE_SPARE_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_PRIVATE_SPARE_L___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_PRIVATE_SPARE_L__PHYRF_PRIVATE_SPARE_0___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_PRIVATE_SPARE_L__PHYRF_PRIVATE_SPARE_0___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_PRIVATE_SPARE_L__PHYRF_PRIVATE_SPARE_0___S 0 +#define PHYA_PHYRF_PHYRF_PRIVATE_SPARE_L___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_PRIVATE_SPARE_L___S 0 + +#define PHYA_PHYRF_PHYRF_PRIVATE_SPARE_U (0x00481B74) +#define PHYA_PHYRF_PHYRF_PRIVATE_SPARE_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_PRIVATE_SPARE_U___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_PRIVATE_SPARE_U__PHYRF_PRIVATE_SPARE_1___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_PRIVATE_SPARE_U__PHYRF_PRIVATE_SPARE_1___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_PRIVATE_SPARE_U__PHYRF_PRIVATE_SPARE_1___S 0 +#define PHYA_PHYRF_PHYRF_PRIVATE_SPARE_U___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_PRIVATE_SPARE_U___S 0 + +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_0_L (0x00481B78) +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_0_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_0_L___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_0_L__TX_DESC_TLV_HEADER___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_0_L__TX_DESC_TLV_HEADER___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_0_L__TX_DESC_TLV_HEADER___S 0 +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_0_L___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_0_L___S 0 + +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_0_U (0x00481B7C) +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_0_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_0_U___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_0_U__TX_DESC_DWORD_0___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_0_U__TX_DESC_DWORD_0___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_0_U__TX_DESC_DWORD_0___S 0 +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_0_U___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_0_U___S 0 + +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_1_L (0x00481B80) +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_1_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_1_L___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_1_L__TX_DESC_DWORD_1___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_1_L__TX_DESC_DWORD_1___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_1_L__TX_DESC_DWORD_1___S 0 +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_1_L___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_1_L___S 0 + +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_1_U (0x00481B84) +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_1_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_1_U___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_1_U__TX_DESC_DWORD_2___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_1_U__TX_DESC_DWORD_2___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_1_U__TX_DESC_DWORD_2___S 0 +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_1_U___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_1_U___S 0 + +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_2_L (0x00481B88) +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_2_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_2_L___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_2_L__TX_DESC_DWORD_3___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_2_L__TX_DESC_DWORD_3___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_2_L__TX_DESC_DWORD_3___S 0 +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_2_L___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_2_L___S 0 + +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_SPARE_L (0x00481B90) +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_SPARE_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_SPARE_L___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_SPARE_L__PHYRF_TX_DESC_WR_SPARE_0___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_SPARE_L__PHYRF_TX_DESC_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_SPARE_L__PHYRF_TX_DESC_WR_SPARE_0___S 0 +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_SPARE_L___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_SPARE_L___S 0 + +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_SPARE_U (0x00481B94) +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_SPARE_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_SPARE_U___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_SPARE_U__PHYRF_TX_DESC_WR_SPARE_1___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_SPARE_U__PHYRF_TX_DESC_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_SPARE_U__PHYRF_TX_DESC_WR_SPARE_1___S 0 +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_SPARE_U___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_TX_DESC_WR_SPARE_U___S 0 + +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_0_L (0x00481B98) +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_0_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_0_L___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_0_L__TX_PRE_DESC_TLV_HEADER___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_0_L__TX_PRE_DESC_TLV_HEADER___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_0_L__TX_PRE_DESC_TLV_HEADER___S 0 +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_0_L___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_0_L___S 0 + +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_0_U (0x00481B9C) +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_0_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_0_U___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_0_U__TX_PRE_DESC_DWORD_0___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_0_U__TX_PRE_DESC_DWORD_0___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_0_U__TX_PRE_DESC_DWORD_0___S 0 +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_0_U___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_0_U___S 0 + +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_1_L (0x00481BA0) +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_1_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_1_L___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_1_L__TX_PRE_DESC_DWORD_1___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_1_L__TX_PRE_DESC_DWORD_1___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_1_L__TX_PRE_DESC_DWORD_1___S 0 +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_1_L___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_1_L___S 0 + +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_1_U (0x00481BA4) +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_1_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_1_U___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_1_U__TX_PRE_DESC_DWORD_2___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_1_U__TX_PRE_DESC_DWORD_2___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_1_U__TX_PRE_DESC_DWORD_2___S 0 +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_1_U___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_1_U___S 0 + +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_2_L (0x00481BA8) +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_2_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_2_L___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_2_L__TX_PRE_DESC_DWORD_3___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_2_L__TX_PRE_DESC_DWORD_3___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_2_L__TX_PRE_DESC_DWORD_3___S 0 +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_2_L___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_2_L___S 0 + +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_2_U (0x00481BAC) +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_2_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_2_U___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_2_U__TX_PRE_DESC_DWORD_4___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_2_U__TX_PRE_DESC_DWORD_4___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_2_U__TX_PRE_DESC_DWORD_4___S 0 +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_2_U___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_2_U___S 0 + +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_3_L (0x00481BB0) +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_3_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_3_L___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_3_L__TX_PRE_DESC_DWORD_5___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_3_L__TX_PRE_DESC_DWORD_5___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_3_L__TX_PRE_DESC_DWORD_5___S 0 +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_3_L___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_3_L___S 0 + +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_3_U (0x00481BB4) +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_3_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_3_U___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_3_U__TX_PRE_DESC_DWORD_6___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_3_U__TX_PRE_DESC_DWORD_6___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_3_U__TX_PRE_DESC_DWORD_6___S 0 +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_3_U___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_3_U___S 0 + +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_4_L (0x00481BB8) +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_4_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_4_L___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_4_L__TX_PRE_DESC_DWORD_7___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_4_L__TX_PRE_DESC_DWORD_7___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_4_L__TX_PRE_DESC_DWORD_7___S 0 +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_4_L___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_TX_PRE_DESC_WR_4_L___S 0 + +#define PHYA_PHYRF_PHYRF_TX_FLAG_NOTIFY_WR_L (0x00481BC0) +#define PHYA_PHYRF_PHYRF_TX_FLAG_NOTIFY_WR_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_TX_FLAG_NOTIFY_WR_L___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_TX_FLAG_NOTIFY_WR_L__TX_FRAME_FLAGS___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_TX_FLAG_NOTIFY_WR_L__TX_FRAME_FLAGS___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_TX_FLAG_NOTIFY_WR_L__TX_FRAME_FLAGS___S 0 +#define PHYA_PHYRF_PHYRF_TX_FLAG_NOTIFY_WR_L___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_TX_FLAG_NOTIFY_WR_L___S 0 + +#define PHYA_PHYRF_CAL_INFO_MEM_0_L_n(n) (0x00481C00+0x8*(n)) +#define PHYA_PHYRF_CAL_INFO_MEM_0_L_n_nMIN 0 +#define PHYA_PHYRF_CAL_INFO_MEM_0_L_n_nMAX 0 +#define PHYA_PHYRF_CAL_INFO_MEM_0_L_n_ELEM 1 +#define PHYA_PHYRF_CAL_INFO_MEM_0_L_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_INFO_MEM_0_L_n___POR 0x00000000 +#define PHYA_PHYRF_CAL_INFO_MEM_0_L_n__CAL_INFO_MEM_0_0___POR 0x00000000 +#define PHYA_PHYRF_CAL_INFO_MEM_0_L_n__CAL_INFO_MEM_0_0___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_INFO_MEM_0_L_n__CAL_INFO_MEM_0_0___S 0 +#define PHYA_PHYRF_CAL_INFO_MEM_0_L_n___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_INFO_MEM_0_L_n___S 0 +#define PHYA_PHYRF_CAL_INFO_MEM_0_L_0 (0x00481C00) +#define PHYA_PHYRF_CAL_INFO_MEM_0_L_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_INFO_MEM_0_L_0__CAL_INFO_MEM_0_0___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_INFO_MEM_0_L_0__CAL_INFO_MEM_0_0___S 0 + +#define PHYA_PHYRF_CAL_INFO_MEM_0_U_n(n) (0x00481C04+0x8*(n)) +#define PHYA_PHYRF_CAL_INFO_MEM_0_U_n_nMIN 0 +#define PHYA_PHYRF_CAL_INFO_MEM_0_U_n_nMAX 0 +#define PHYA_PHYRF_CAL_INFO_MEM_0_U_n_ELEM 1 +#define PHYA_PHYRF_CAL_INFO_MEM_0_U_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_INFO_MEM_0_U_n___POR 0x00000000 +#define PHYA_PHYRF_CAL_INFO_MEM_0_U_n__CAL_INFO_MEM_0_1___POR 0x00000000 +#define PHYA_PHYRF_CAL_INFO_MEM_0_U_n__CAL_INFO_MEM_0_1___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_INFO_MEM_0_U_n__CAL_INFO_MEM_0_1___S 0 +#define PHYA_PHYRF_CAL_INFO_MEM_0_U_n___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_INFO_MEM_0_U_n___S 0 +#define PHYA_PHYRF_CAL_INFO_MEM_0_U_0 (0x00481C04) +#define PHYA_PHYRF_CAL_INFO_MEM_0_U_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_INFO_MEM_0_U_0__CAL_INFO_MEM_0_1___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_INFO_MEM_0_U_0__CAL_INFO_MEM_0_1___S 0 + +#define PHYA_PHYRF_CAL_INFO_MEM_1_L_n(n) (0x00485C00+0x8*(n)) +#define PHYA_PHYRF_CAL_INFO_MEM_1_L_n_nMIN 0 +#define PHYA_PHYRF_CAL_INFO_MEM_1_L_n_nMAX 0 +#define PHYA_PHYRF_CAL_INFO_MEM_1_L_n_ELEM 1 +#define PHYA_PHYRF_CAL_INFO_MEM_1_L_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_INFO_MEM_1_L_n___POR 0x00000000 +#define PHYA_PHYRF_CAL_INFO_MEM_1_L_n__CAL_INFO_MEM_1_0___POR 0x00000000 +#define PHYA_PHYRF_CAL_INFO_MEM_1_L_n__CAL_INFO_MEM_1_0___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_INFO_MEM_1_L_n__CAL_INFO_MEM_1_0___S 0 +#define PHYA_PHYRF_CAL_INFO_MEM_1_L_n___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_INFO_MEM_1_L_n___S 0 +#define PHYA_PHYRF_CAL_INFO_MEM_1_L_0 (0x00485C00) +#define PHYA_PHYRF_CAL_INFO_MEM_1_L_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_INFO_MEM_1_L_0__CAL_INFO_MEM_1_0___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_INFO_MEM_1_L_0__CAL_INFO_MEM_1_0___S 0 + +#define PHYA_PHYRF_CAL_INFO_MEM_1_U_n(n) (0x00485C04+0x8*(n)) +#define PHYA_PHYRF_CAL_INFO_MEM_1_U_n_nMIN 0 +#define PHYA_PHYRF_CAL_INFO_MEM_1_U_n_nMAX 0 +#define PHYA_PHYRF_CAL_INFO_MEM_1_U_n_ELEM 1 +#define PHYA_PHYRF_CAL_INFO_MEM_1_U_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_INFO_MEM_1_U_n___POR 0x00000000 +#define PHYA_PHYRF_CAL_INFO_MEM_1_U_n__CAL_INFO_MEM_1_1___POR 0x00000000 +#define PHYA_PHYRF_CAL_INFO_MEM_1_U_n__CAL_INFO_MEM_1_1___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_INFO_MEM_1_U_n__CAL_INFO_MEM_1_1___S 0 +#define PHYA_PHYRF_CAL_INFO_MEM_1_U_n___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_INFO_MEM_1_U_n___S 0 +#define PHYA_PHYRF_CAL_INFO_MEM_1_U_0 (0x00485C04) +#define PHYA_PHYRF_CAL_INFO_MEM_1_U_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_INFO_MEM_1_U_0__CAL_INFO_MEM_1_1___M 0xFFFFFFFF +#define PHYA_PHYRF_CAL_INFO_MEM_1_U_0__CAL_INFO_MEM_1_1___S 0 + +#define PHYA_PHYRF_RX_FRAME_CTRL_0_L (0x00489C00) +#define PHYA_PHYRF_RX_FRAME_CTRL_0_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_RX_FRAME_CTRL_0_L___POR 0x00000000 +#define PHYA_PHYRF_RX_FRAME_CTRL_0_L__TS_OF_LAST_RX_SAMPLE___POR 0x00000000 +#define PHYA_PHYRF_RX_FRAME_CTRL_0_L__TS_OF_LAST_RX_SAMPLE___M 0xFFFFFFFF +#define PHYA_PHYRF_RX_FRAME_CTRL_0_L__TS_OF_LAST_RX_SAMPLE___S 0 +#define PHYA_PHYRF_RX_FRAME_CTRL_0_L___M 0xFFFFFFFF +#define PHYA_PHYRF_RX_FRAME_CTRL_0_L___S 0 + +#define PHYA_PHYRF_RX_FRAME_CTRL_1_L (0x00489C08) +#define PHYA_PHYRF_RX_FRAME_CTRL_1_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_RX_FRAME_CTRL_1_L___POR 0x00000000 +#define PHYA_PHYRF_RX_FRAME_CTRL_1_L__TS_OF_LAST_RX_SAMPLE_VLD___POR 0x0 +#define PHYA_PHYRF_RX_FRAME_CTRL_1_L__TS_OF_LAST_RX_SAMPLE_VLD___M 0x00000001 +#define PHYA_PHYRF_RX_FRAME_CTRL_1_L__TS_OF_LAST_RX_SAMPLE_VLD___S 0 +#define PHYA_PHYRF_RX_FRAME_CTRL_1_L___M 0x00000001 +#define PHYA_PHYRF_RX_FRAME_CTRL_1_L___S 0 + +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_0_L (0x00489C10) +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_0_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_0_L___POR 0x00000000 +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_0_L__RUN_RXDCCAL_2ND_STAGE___POR 0x0 +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_0_L__RUN_RXDCCAL_2ND_STAGE___M 0x00000001 +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_0_L__RUN_RXDCCAL_2ND_STAGE___S 0 +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_0_L___M 0x00000001 +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_0_L___S 0 + +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_1_L (0x00489C18) +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_1_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_1_L___POR 0x00000000 +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_1_L__RXDCCAL_2ND_STAGE_RESULT_POINTER___POR 0x00 +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_1_L__RXDCCAL_2ND_STAGE_RESULT_POINTER___M 0x000000FF +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_1_L__RXDCCAL_2ND_STAGE_RESULT_POINTER___S 0 +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_1_L___M 0x000000FF +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_1_L___S 0 + +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_2_L (0x00489C20) +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_2_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_2_L___POR 0x00000000 +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_2_L__RXDCCAL_2ND_STAGE_SET_RX_GAIN_TYPE___POR 0x00 +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_2_L__RXDCCAL_2ND_STAGE_SET_RX_GAIN_TYPE___M 0x0000007F +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_2_L__RXDCCAL_2ND_STAGE_SET_RX_GAIN_TYPE___S 0 +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_2_L___M 0x0000007F +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_2_L___S 0 + +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_3_L (0x00489C28) +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_3_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_3_L___POR 0x00000000 +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_3_L__RXDCCAL_2ND_STAGE_SET_RX_GAIN_INDEX___POR 0x0 +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_3_L__RXDCCAL_2ND_STAGE_SET_RX_GAIN_INDEX___M 0x00000003 +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_3_L__RXDCCAL_2ND_STAGE_SET_RX_GAIN_INDEX___S 0 +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_3_L___M 0x00000003 +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_3_L___S 0 + +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_4_L (0x00489C30) +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_4_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_4_L___POR 0x00000000 +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_4_L__RXDCCAL_2ND_STAGE_RESTORE_RX_GAIN_TYPE___POR 0x00 +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_4_L__RXDCCAL_2ND_STAGE_RESTORE_RX_GAIN_TYPE___M 0x0000007F +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_4_L__RXDCCAL_2ND_STAGE_RESTORE_RX_GAIN_TYPE___S 0 +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_4_L___M 0x0000007F +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_4_L___S 0 + +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_5_L (0x00489C38) +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_5_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_5_L___POR 0x00000000 +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_5_L__RXDCCAL_2ND_STAGE_RESTORE_RX_GAIN_INDEX___POR 0x0 +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_5_L__RXDCCAL_2ND_STAGE_RESTORE_RX_GAIN_INDEX___M 0x00000003 +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_5_L__RXDCCAL_2ND_STAGE_RESTORE_RX_GAIN_INDEX___S 0 +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_5_L___M 0x00000003 +#define PHYA_PHYRF_RXDCCAL_2ND_STAGE_5_L___S 0 + +#define PHYA_PHYRF_RTT_FAC_CORRECTION_L (0x00489C40) +#define PHYA_PHYRF_RTT_FAC_CORRECTION_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_RTT_FAC_CORRECTION_L___POR 0x00000000 +#define PHYA_PHYRF_RTT_FAC_CORRECTION_L__PHYRF_RTT_FAC_CORRECTION_VALUE___POR 0x000000 +#define PHYA_PHYRF_RTT_FAC_CORRECTION_L__PHYRF_RTT_FAC_CORRECTION_VALUE___M 0x00FFFFFF +#define PHYA_PHYRF_RTT_FAC_CORRECTION_L__PHYRF_RTT_FAC_CORRECTION_VALUE___S 0 +#define PHYA_PHYRF_RTT_FAC_CORRECTION_L___M 0x00FFFFFF +#define PHYA_PHYRF_RTT_FAC_CORRECTION_L___S 0 + +#define PHYA_PHYRF_RTT_FAC_CORRECTION_U (0x00489C44) +#define PHYA_PHYRF_RTT_FAC_CORRECTION_U___RWC QCSR_REG_RW +#define PHYA_PHYRF_RTT_FAC_CORRECTION_U___POR 0x00000000 +#define PHYA_PHYRF_RTT_FAC_CORRECTION_U__PHYRF_RTT_FAC_CORRECTION_VALID___POR 0x0 +#define PHYA_PHYRF_RTT_FAC_CORRECTION_U__PHYRF_RTT_FAC_CORRECTION_VALID___M 0x00000001 +#define PHYA_PHYRF_RTT_FAC_CORRECTION_U__PHYRF_RTT_FAC_CORRECTION_VALID___S 0 +#define PHYA_PHYRF_RTT_FAC_CORRECTION_U___M 0x00000001 +#define PHYA_PHYRF_RTT_FAC_CORRECTION_U___S 0 + +#define PHYA_PHYRF_FREERUNNING_TIMESTAMP_L (0x00489C48) +#define PHYA_PHYRF_FREERUNNING_TIMESTAMP_L___RWC QCSR_REG_RO +#define PHYA_PHYRF_FREERUNNING_TIMESTAMP_L___POR 0x00000000 +#define PHYA_PHYRF_FREERUNNING_TIMESTAMP_L__FREERUNNING_TIMESTAMP___POR 0x00000000 +#define PHYA_PHYRF_FREERUNNING_TIMESTAMP_L__FREERUNNING_TIMESTAMP___M 0xFFFFFFFF +#define PHYA_PHYRF_FREERUNNING_TIMESTAMP_L__FREERUNNING_TIMESTAMP___S 0 +#define PHYA_PHYRF_FREERUNNING_TIMESTAMP_L___M 0xFFFFFFFF +#define PHYA_PHYRF_FREERUNNING_TIMESTAMP_L___S 0 + +#define PHYA_PHYRF_TX_FRAME_CTRL_0_L (0x00489C50) +#define PHYA_PHYRF_TX_FRAME_CTRL_0_L___RWC QCSR_REG_RO +#define PHYA_PHYRF_TX_FRAME_CTRL_0_L___POR 0x00000000 +#define PHYA_PHYRF_TX_FRAME_CTRL_0_L__TS_OF_FIRST_TX_SAMPLE_15_0___POR 0x0000 +#define PHYA_PHYRF_TX_FRAME_CTRL_0_L__TS_OF_FIRST_TX_SAMPLE_15_0___M 0x0000FFFF +#define PHYA_PHYRF_TX_FRAME_CTRL_0_L__TS_OF_FIRST_TX_SAMPLE_15_0___S 0 +#define PHYA_PHYRF_TX_FRAME_CTRL_0_L___M 0x0000FFFF +#define PHYA_PHYRF_TX_FRAME_CTRL_0_L___S 0 + +#define PHYA_PHYRF_TX_FRAME_CTRL_0_U (0x00489C54) +#define PHYA_PHYRF_TX_FRAME_CTRL_0_U___RWC QCSR_REG_RO +#define PHYA_PHYRF_TX_FRAME_CTRL_0_U___POR 0x00000000 +#define PHYA_PHYRF_TX_FRAME_CTRL_0_U__TS_OF_FIRST_TX_SAMPLE_31_16___POR 0x0000 +#define PHYA_PHYRF_TX_FRAME_CTRL_0_U__TS_OF_FIRST_TX_SAMPLE_31_16___M 0x0000FFFF +#define PHYA_PHYRF_TX_FRAME_CTRL_0_U__TS_OF_FIRST_TX_SAMPLE_31_16___S 0 +#define PHYA_PHYRF_TX_FRAME_CTRL_0_U___M 0x0000FFFF +#define PHYA_PHYRF_TX_FRAME_CTRL_0_U___S 0 + +#define PHYA_PHYRF_TX_FRAME_CTRL_1_L (0x00489C58) +#define PHYA_PHYRF_TX_FRAME_CTRL_1_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TX_FRAME_CTRL_1_L___POR 0x00000000 +#define PHYA_PHYRF_TX_FRAME_CTRL_1_L__TS_OF_FIRST_TX_DUMMY___POR 0x0 +#define PHYA_PHYRF_TX_FRAME_CTRL_1_L__TS_OF_FIRST_TX_DUMMY___M 0x00000001 +#define PHYA_PHYRF_TX_FRAME_CTRL_1_L__TS_OF_FIRST_TX_DUMMY___S 0 +#define PHYA_PHYRF_TX_FRAME_CTRL_1_L___M 0x00000001 +#define PHYA_PHYRF_TX_FRAME_CTRL_1_L___S 0 + +#define PHYA_PHYRF_TX_FRAME_CTRL_2_L (0x00489C60) +#define PHYA_PHYRF_TX_FRAME_CTRL_2_L___RWC QCSR_REG_RO +#define PHYA_PHYRF_TX_FRAME_CTRL_2_L___POR 0x00000000 +#define PHYA_PHYRF_TX_FRAME_CTRL_2_L__TS_OF_LAST_TX_SAMPLE_15_0___POR 0x0000 +#define PHYA_PHYRF_TX_FRAME_CTRL_2_L__TS_OF_LAST_TX_SAMPLE_15_0___M 0x0000FFFF +#define PHYA_PHYRF_TX_FRAME_CTRL_2_L__TS_OF_LAST_TX_SAMPLE_15_0___S 0 +#define PHYA_PHYRF_TX_FRAME_CTRL_2_L___M 0x0000FFFF +#define PHYA_PHYRF_TX_FRAME_CTRL_2_L___S 0 + +#define PHYA_PHYRF_TX_FRAME_CTRL_2_U (0x00489C64) +#define PHYA_PHYRF_TX_FRAME_CTRL_2_U___RWC QCSR_REG_RO +#define PHYA_PHYRF_TX_FRAME_CTRL_2_U___POR 0x00000000 +#define PHYA_PHYRF_TX_FRAME_CTRL_2_U__TS_OF_LAST_TX_SAMPLE_31_16___POR 0x0000 +#define PHYA_PHYRF_TX_FRAME_CTRL_2_U__TS_OF_LAST_TX_SAMPLE_31_16___M 0x0000FFFF +#define PHYA_PHYRF_TX_FRAME_CTRL_2_U__TS_OF_LAST_TX_SAMPLE_31_16___S 0 +#define PHYA_PHYRF_TX_FRAME_CTRL_2_U___M 0x0000FFFF +#define PHYA_PHYRF_TX_FRAME_CTRL_2_U___S 0 + +#define PHYA_PHYRF_TX_FRAME_CTRL_3_L (0x00489C68) +#define PHYA_PHYRF_TX_FRAME_CTRL_3_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TX_FRAME_CTRL_3_L___POR 0x00000000 +#define PHYA_PHYRF_TX_FRAME_CTRL_3_L__TS_OF_LAST_TX_DUMMY___POR 0x0 +#define PHYA_PHYRF_TX_FRAME_CTRL_3_L__TS_OF_LAST_TX_DUMMY___M 0x00000001 +#define PHYA_PHYRF_TX_FRAME_CTRL_3_L__TS_OF_LAST_TX_DUMMY___S 0 +#define PHYA_PHYRF_TX_FRAME_CTRL_3_L___M 0x00000001 +#define PHYA_PHYRF_TX_FRAME_CTRL_3_L___S 0 + +#define PHYA_PHYRF_PHYR_TPC_CLPC_WR_L (0x00489C70) +#define PHYA_PHYRF_PHYR_TPC_CLPC_WR_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYR_TPC_CLPC_WR_L___POR 0x00000000 +#define PHYA_PHYRF_PHYR_TPC_CLPC_WR_L__USE_PREAMBLE_PWR_FOR_SHORT_PKT___POR 0x0 +#define PHYA_PHYRF_PHYR_TPC_CLPC_WR_L__HEAVY_CLIP_ENABLE___POR 0x0 +#define PHYA_PHYRF_PHYR_TPC_CLPC_WR_L__USE_PREAMBLE_PWR_FOR_SHORT_PKT___M 0x00000002 +#define PHYA_PHYRF_PHYR_TPC_CLPC_WR_L__USE_PREAMBLE_PWR_FOR_SHORT_PKT___S 1 +#define PHYA_PHYRF_PHYR_TPC_CLPC_WR_L__HEAVY_CLIP_ENABLE___M 0x00000001 +#define PHYA_PHYRF_PHYR_TPC_CLPC_WR_L__HEAVY_CLIP_ENABLE___S 0 +#define PHYA_PHYRF_PHYR_TPC_CLPC_WR_L___M 0x00000003 +#define PHYA_PHYRF_PHYR_TPC_CLPC_WR_L___S 0 + +#define PHYA_PHYRF_TS_TIMER0_CTRL_0_L (0x00489C78) +#define PHYA_PHYRF_TS_TIMER0_CTRL_0_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TS_TIMER0_CTRL_0_L___POR 0x00000000 +#define PHYA_PHYRF_TS_TIMER0_CTRL_0_L__TS_TARGET_OF_TIMER0___POR 0x00000000 +#define PHYA_PHYRF_TS_TIMER0_CTRL_0_L__TS_TARGET_OF_TIMER0___M 0xFFFFFFFF +#define PHYA_PHYRF_TS_TIMER0_CTRL_0_L__TS_TARGET_OF_TIMER0___S 0 +#define PHYA_PHYRF_TS_TIMER0_CTRL_0_L___M 0xFFFFFFFF +#define PHYA_PHYRF_TS_TIMER0_CTRL_0_L___S 0 + +#define PHYA_PHYRF_TS_TIMER0_CTRL_1_L (0x00489C80) +#define PHYA_PHYRF_TS_TIMER0_CTRL_1_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TS_TIMER0_CTRL_1_L___POR 0x00000000 +#define PHYA_PHYRF_TS_TIMER0_CTRL_1_L__TS_TARGET_OF_TIMER0_VLD___POR 0x0 +#define PHYA_PHYRF_TS_TIMER0_CTRL_1_L__TS_TARGET_OF_TIMER0_VLD___M 0x00000001 +#define PHYA_PHYRF_TS_TIMER0_CTRL_1_L__TS_TARGET_OF_TIMER0_VLD___S 0 +#define PHYA_PHYRF_TS_TIMER0_CTRL_1_L___M 0x00000001 +#define PHYA_PHYRF_TS_TIMER0_CTRL_1_L___S 0 + +#define PHYA_PHYRF_TS_TIMER1_CTRL_0_L (0x00489C88) +#define PHYA_PHYRF_TS_TIMER1_CTRL_0_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TS_TIMER1_CTRL_0_L___POR 0x00000000 +#define PHYA_PHYRF_TS_TIMER1_CTRL_0_L__TS_TARGET_OF_TIMER1___POR 0x00000000 +#define PHYA_PHYRF_TS_TIMER1_CTRL_0_L__TS_TARGET_OF_TIMER1___M 0xFFFFFFFF +#define PHYA_PHYRF_TS_TIMER1_CTRL_0_L__TS_TARGET_OF_TIMER1___S 0 +#define PHYA_PHYRF_TS_TIMER1_CTRL_0_L___M 0xFFFFFFFF +#define PHYA_PHYRF_TS_TIMER1_CTRL_0_L___S 0 + +#define PHYA_PHYRF_TS_TIMER1_CTRL_1_L (0x00489C90) +#define PHYA_PHYRF_TS_TIMER1_CTRL_1_L___RWC QCSR_REG_RW +#define PHYA_PHYRF_TS_TIMER1_CTRL_1_L___POR 0x00000000 +#define PHYA_PHYRF_TS_TIMER1_CTRL_1_L__TS_TARGET_OF_TIMER1_VLD___POR 0x0 +#define PHYA_PHYRF_TS_TIMER1_CTRL_1_L__TS_TARGET_OF_TIMER1_VLD___M 0x00000001 +#define PHYA_PHYRF_TS_TIMER1_CTRL_1_L__TS_TARGET_OF_TIMER1_VLD___S 0 +#define PHYA_PHYRF_TS_TIMER1_CTRL_1_L___M 0x00000001 +#define PHYA_PHYRF_TS_TIMER1_CTRL_1_L___S 0 + +#define PHYA_PHYRF_PAPRD_CTRL_L_B0 (0x00490000) +#define PHYA_PHYRF_PAPRD_CTRL_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PAPRD_CTRL_L_B0___POR 0x001F8000 +#define PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_TARGET_PWR_MIN___POR 0x00 +#define PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_TARGET_PWR_MAX___POR 0x3F +#define PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_ENABLE_TRAIN___POR 0x0 +#define PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_ADAPTIVE_TABLE_VALID___POR 0x00 +#define PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_MAG_THRSH___POR 0x00 +#define PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_ENABLE___POR 0x0 +#define PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_TARGET_PWR_MIN___M 0x7F800000 +#define PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_TARGET_PWR_MIN___S 23 +#define PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_TARGET_PWR_MAX___M 0x007F8000 +#define PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_TARGET_PWR_MAX___S 15 +#define PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_ENABLE_TRAIN___M 0x00004000 +#define PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_ENABLE_TRAIN___S 14 +#define PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_ADAPTIVE_TABLE_VALID___M 0x00003FC0 +#define PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_ADAPTIVE_TABLE_VALID___S 6 +#define PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_MAG_THRSH___M 0x0000003E +#define PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_MAG_THRSH___S 1 +#define PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_ENABLE___M 0x00000001 +#define PHYA_PHYRF_PAPRD_CTRL_L_B0__PAPRD_ENABLE___S 0 +#define PHYA_PHYRF_PAPRD_CTRL_L_B0___M 0x7FFFFFFF +#define PHYA_PHYRF_PAPRD_CTRL_L_B0___S 0 + +#define PHYA_PHYRF_PAPRD_CTRL_L_B1 (0x00498000) +#define PHYA_PHYRF_PAPRD_CTRL_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_PAPRD_CTRL_L_B1___POR 0x001F8000 +#define PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_TARGET_PWR_MIN___POR 0x00 +#define PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_TARGET_PWR_MAX___POR 0x3F +#define PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_ENABLE_TRAIN___POR 0x0 +#define PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_ADAPTIVE_TABLE_VALID___POR 0x00 +#define PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_MAG_THRSH___POR 0x00 +#define PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_ENABLE___POR 0x0 +#define PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_TARGET_PWR_MIN___M 0x7F800000 +#define PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_TARGET_PWR_MIN___S 23 +#define PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_TARGET_PWR_MAX___M 0x007F8000 +#define PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_TARGET_PWR_MAX___S 15 +#define PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_ENABLE_TRAIN___M 0x00004000 +#define PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_ENABLE_TRAIN___S 14 +#define PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_ADAPTIVE_TABLE_VALID___M 0x00003FC0 +#define PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_ADAPTIVE_TABLE_VALID___S 6 +#define PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_MAG_THRSH___M 0x0000003E +#define PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_MAG_THRSH___S 1 +#define PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_ENABLE___M 0x00000001 +#define PHYA_PHYRF_PAPRD_CTRL_L_B1__PAPRD_ENABLE___S 0 +#define PHYA_PHYRF_PAPRD_CTRL_L_B1___M 0x7FFFFFFF +#define PHYA_PHYRF_PAPRD_CTRL_L_B1___S 0 + +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0 (0x00490008) +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0___POR 0x00000000 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__PEF_ENABLE_OVRD_VAL___POR 0x0 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__PEF_ENABLE_OVRD_EN___POR 0x0 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__GAIN_INDEX_VALID_OVRD_VAL___POR 0x00 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__PAPRD_ENABLE_OVRD_VAL___POR 0x0 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__PAPRD_ENABLE_OVRD_EN___POR 0x0 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__TXCORR_CHAIN_ENABLE_OVRD_VAL___POR 0x0 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__TXCORR_CHAIN_ENABLE_OVRD_EN___POR 0x0 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__PEF_ENABLE_OVRD_VAL___M 0x00002000 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__PEF_ENABLE_OVRD_VAL___S 13 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__PEF_ENABLE_OVRD_EN___M 0x00001000 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__PEF_ENABLE_OVRD_EN___S 12 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__GAIN_INDEX_VALID_OVRD_VAL___M 0x00000FF0 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__GAIN_INDEX_VALID_OVRD_VAL___S 4 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__PAPRD_ENABLE_OVRD_VAL___M 0x00000008 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__PAPRD_ENABLE_OVRD_VAL___S 3 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__PAPRD_ENABLE_OVRD_EN___M 0x00000004 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__PAPRD_ENABLE_OVRD_EN___S 2 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__TXCORR_CHAIN_ENABLE_OVRD_VAL___M 0x00000002 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__TXCORR_CHAIN_ENABLE_OVRD_VAL___S 1 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__TXCORR_CHAIN_ENABLE_OVRD_EN___M 0x00000001 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0__TXCORR_CHAIN_ENABLE_OVRD_EN___S 0 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0___M 0x00003FFF +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B0___S 0 + +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1 (0x00498008) +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1___POR 0x00000000 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__PEF_ENABLE_OVRD_VAL___POR 0x0 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__PEF_ENABLE_OVRD_EN___POR 0x0 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__GAIN_INDEX_VALID_OVRD_VAL___POR 0x00 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__PAPRD_ENABLE_OVRD_VAL___POR 0x0 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__PAPRD_ENABLE_OVRD_EN___POR 0x0 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__TXCORR_CHAIN_ENABLE_OVRD_VAL___POR 0x0 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__TXCORR_CHAIN_ENABLE_OVRD_EN___POR 0x0 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__PEF_ENABLE_OVRD_VAL___M 0x00002000 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__PEF_ENABLE_OVRD_VAL___S 13 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__PEF_ENABLE_OVRD_EN___M 0x00001000 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__PEF_ENABLE_OVRD_EN___S 12 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__GAIN_INDEX_VALID_OVRD_VAL___M 0x00000FF0 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__GAIN_INDEX_VALID_OVRD_VAL___S 4 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__PAPRD_ENABLE_OVRD_VAL___M 0x00000008 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__PAPRD_ENABLE_OVRD_VAL___S 3 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__PAPRD_ENABLE_OVRD_EN___M 0x00000004 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__PAPRD_ENABLE_OVRD_EN___S 2 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__TXCORR_CHAIN_ENABLE_OVRD_VAL___M 0x00000002 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__TXCORR_CHAIN_ENABLE_OVRD_VAL___S 1 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__TXCORR_CHAIN_ENABLE_OVRD_EN___M 0x00000001 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1__TXCORR_CHAIN_ENABLE_OVRD_EN___S 0 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1___M 0x00003FFF +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_L_B1___S 0 + +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_U_B0 (0x0049000C) +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_U_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_U_B0___POR 0x00000000 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_U_B0__TXCORR_CHAIN_SPARE___POR 0x00000000 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_U_B0__TXCORR_CHAIN_SPARE___M 0xFFFFFFFF +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_U_B0__TXCORR_CHAIN_SPARE___S 0 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_U_B0___M 0xFFFFFFFF +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_U_B0___S 0 + +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_U_B1 (0x0049800C) +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_U_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_U_B1___POR 0x00000000 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_U_B1__TXCORR_CHAIN_SPARE___POR 0x00000000 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_U_B1__TXCORR_CHAIN_SPARE___M 0xFFFFFFFF +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_U_B1__TXCORR_CHAIN_SPARE___S 0 +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_U_B1___M 0xFFFFFFFF +#define PHYA_PHYRF_PAPRD_CTRL_OVRD_U_B1___S 0 + +#define PHYA_PHYRF_EDPD_CTRL_0_L_B0 (0x00490010) +#define PHYA_PHYRF_EDPD_CTRL_0_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_CTRL_0_L_B0___POR 0x04030000 +#define PHYA_PHYRF_EDPD_CTRL_0_L_B0__Q6_FOR_LUT_XQ6_ABS_XQ7___POR 0x4 +#define PHYA_PHYRF_EDPD_CTRL_0_L_B0__Q4_FOR_LUT_XQ4_ABS_XQ5___POR 0x3 +#define PHYA_PHYRF_EDPD_CTRL_0_L_B0__Q2_FOR_LUT_XQ2_ABS_XQ3___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_0_L_B0__Q0_FOR_LUT_XQ0_ABS_XQ1___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_0_L_B0__Q6_FOR_LUT_XQ6_ABS_XQ7___M 0x0F000000 +#define PHYA_PHYRF_EDPD_CTRL_0_L_B0__Q6_FOR_LUT_XQ6_ABS_XQ7___S 24 +#define PHYA_PHYRF_EDPD_CTRL_0_L_B0__Q4_FOR_LUT_XQ4_ABS_XQ5___M 0x000F0000 +#define PHYA_PHYRF_EDPD_CTRL_0_L_B0__Q4_FOR_LUT_XQ4_ABS_XQ5___S 16 +#define PHYA_PHYRF_EDPD_CTRL_0_L_B0__Q2_FOR_LUT_XQ2_ABS_XQ3___M 0x00000F00 +#define PHYA_PHYRF_EDPD_CTRL_0_L_B0__Q2_FOR_LUT_XQ2_ABS_XQ3___S 8 +#define PHYA_PHYRF_EDPD_CTRL_0_L_B0__Q0_FOR_LUT_XQ0_ABS_XQ1___M 0x0000000F +#define PHYA_PHYRF_EDPD_CTRL_0_L_B0__Q0_FOR_LUT_XQ0_ABS_XQ1___S 0 +#define PHYA_PHYRF_EDPD_CTRL_0_L_B0___M 0x0F0F0F0F +#define PHYA_PHYRF_EDPD_CTRL_0_L_B0___S 0 + +#define PHYA_PHYRF_EDPD_CTRL_0_L_B1 (0x00498010) +#define PHYA_PHYRF_EDPD_CTRL_0_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_CTRL_0_L_B1___POR 0x04030000 +#define PHYA_PHYRF_EDPD_CTRL_0_L_B1__Q6_FOR_LUT_XQ6_ABS_XQ7___POR 0x4 +#define PHYA_PHYRF_EDPD_CTRL_0_L_B1__Q4_FOR_LUT_XQ4_ABS_XQ5___POR 0x3 +#define PHYA_PHYRF_EDPD_CTRL_0_L_B1__Q2_FOR_LUT_XQ2_ABS_XQ3___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_0_L_B1__Q0_FOR_LUT_XQ0_ABS_XQ1___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_0_L_B1__Q6_FOR_LUT_XQ6_ABS_XQ7___M 0x0F000000 +#define PHYA_PHYRF_EDPD_CTRL_0_L_B1__Q6_FOR_LUT_XQ6_ABS_XQ7___S 24 +#define PHYA_PHYRF_EDPD_CTRL_0_L_B1__Q4_FOR_LUT_XQ4_ABS_XQ5___M 0x000F0000 +#define PHYA_PHYRF_EDPD_CTRL_0_L_B1__Q4_FOR_LUT_XQ4_ABS_XQ5___S 16 +#define PHYA_PHYRF_EDPD_CTRL_0_L_B1__Q2_FOR_LUT_XQ2_ABS_XQ3___M 0x00000F00 +#define PHYA_PHYRF_EDPD_CTRL_0_L_B1__Q2_FOR_LUT_XQ2_ABS_XQ3___S 8 +#define PHYA_PHYRF_EDPD_CTRL_0_L_B1__Q0_FOR_LUT_XQ0_ABS_XQ1___M 0x0000000F +#define PHYA_PHYRF_EDPD_CTRL_0_L_B1__Q0_FOR_LUT_XQ0_ABS_XQ1___S 0 +#define PHYA_PHYRF_EDPD_CTRL_0_L_B1___M 0x0F0F0F0F +#define PHYA_PHYRF_EDPD_CTRL_0_L_B1___S 0 + +#define PHYA_PHYRF_EDPD_CTRL_0_U_B0 (0x00490014) +#define PHYA_PHYRF_EDPD_CTRL_0_U_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_CTRL_0_U_B0___POR 0x04030605 +#define PHYA_PHYRF_EDPD_CTRL_0_U_B0__Q7_FOR_LUT_XQ6_ABS_XQ7___POR 0x4 +#define PHYA_PHYRF_EDPD_CTRL_0_U_B0__Q5_FOR_LUT_XQ4_ABS_XQ5___POR 0x3 +#define PHYA_PHYRF_EDPD_CTRL_0_U_B0__Q3_FOR_LUT_XQ2_ABS_XQ3___POR 0x6 +#define PHYA_PHYRF_EDPD_CTRL_0_U_B0__Q1_FOR_LUT_XQ0_ABS_XQ1___POR 0x5 +#define PHYA_PHYRF_EDPD_CTRL_0_U_B0__Q7_FOR_LUT_XQ6_ABS_XQ7___M 0x07000000 +#define PHYA_PHYRF_EDPD_CTRL_0_U_B0__Q7_FOR_LUT_XQ6_ABS_XQ7___S 24 +#define PHYA_PHYRF_EDPD_CTRL_0_U_B0__Q5_FOR_LUT_XQ4_ABS_XQ5___M 0x00070000 +#define PHYA_PHYRF_EDPD_CTRL_0_U_B0__Q5_FOR_LUT_XQ4_ABS_XQ5___S 16 +#define PHYA_PHYRF_EDPD_CTRL_0_U_B0__Q3_FOR_LUT_XQ2_ABS_XQ3___M 0x00000700 +#define PHYA_PHYRF_EDPD_CTRL_0_U_B0__Q3_FOR_LUT_XQ2_ABS_XQ3___S 8 +#define PHYA_PHYRF_EDPD_CTRL_0_U_B0__Q1_FOR_LUT_XQ0_ABS_XQ1___M 0x00000007 +#define PHYA_PHYRF_EDPD_CTRL_0_U_B0__Q1_FOR_LUT_XQ0_ABS_XQ1___S 0 +#define PHYA_PHYRF_EDPD_CTRL_0_U_B0___M 0x07070707 +#define PHYA_PHYRF_EDPD_CTRL_0_U_B0___S 0 + +#define PHYA_PHYRF_EDPD_CTRL_0_U_B1 (0x00498014) +#define PHYA_PHYRF_EDPD_CTRL_0_U_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_CTRL_0_U_B1___POR 0x04030605 +#define PHYA_PHYRF_EDPD_CTRL_0_U_B1__Q7_FOR_LUT_XQ6_ABS_XQ7___POR 0x4 +#define PHYA_PHYRF_EDPD_CTRL_0_U_B1__Q5_FOR_LUT_XQ4_ABS_XQ5___POR 0x3 +#define PHYA_PHYRF_EDPD_CTRL_0_U_B1__Q3_FOR_LUT_XQ2_ABS_XQ3___POR 0x6 +#define PHYA_PHYRF_EDPD_CTRL_0_U_B1__Q1_FOR_LUT_XQ0_ABS_XQ1___POR 0x5 +#define PHYA_PHYRF_EDPD_CTRL_0_U_B1__Q7_FOR_LUT_XQ6_ABS_XQ7___M 0x07000000 +#define PHYA_PHYRF_EDPD_CTRL_0_U_B1__Q7_FOR_LUT_XQ6_ABS_XQ7___S 24 +#define PHYA_PHYRF_EDPD_CTRL_0_U_B1__Q5_FOR_LUT_XQ4_ABS_XQ5___M 0x00070000 +#define PHYA_PHYRF_EDPD_CTRL_0_U_B1__Q5_FOR_LUT_XQ4_ABS_XQ5___S 16 +#define PHYA_PHYRF_EDPD_CTRL_0_U_B1__Q3_FOR_LUT_XQ2_ABS_XQ3___M 0x00000700 +#define PHYA_PHYRF_EDPD_CTRL_0_U_B1__Q3_FOR_LUT_XQ2_ABS_XQ3___S 8 +#define PHYA_PHYRF_EDPD_CTRL_0_U_B1__Q1_FOR_LUT_XQ0_ABS_XQ1___M 0x00000007 +#define PHYA_PHYRF_EDPD_CTRL_0_U_B1__Q1_FOR_LUT_XQ0_ABS_XQ1___S 0 +#define PHYA_PHYRF_EDPD_CTRL_0_U_B1___M 0x07070707 +#define PHYA_PHYRF_EDPD_CTRL_0_U_B1___S 0 + +#define PHYA_PHYRF_EDPD_CTRL_1_L_B0 (0x00490018) +#define PHYA_PHYRF_EDPD_CTRL_1_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_CTRL_1_L_B0___POR 0x08000008 +#define PHYA_PHYRF_EDPD_CTRL_1_L_B0__Q3_FOR_XQ3XQ4___POR 0x8 +#define PHYA_PHYRF_EDPD_CTRL_1_L_B0__Q2_FOR_XQ1XQ2___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_1_L_B0__Q1_FOR_XQ1XQ2___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_1_L_B0__Q_FOR_XQ___POR 0x8 +#define PHYA_PHYRF_EDPD_CTRL_1_L_B0__Q3_FOR_XQ3XQ4___M 0x0F000000 +#define PHYA_PHYRF_EDPD_CTRL_1_L_B0__Q3_FOR_XQ3XQ4___S 24 +#define PHYA_PHYRF_EDPD_CTRL_1_L_B0__Q2_FOR_XQ1XQ2___M 0x000F0000 +#define PHYA_PHYRF_EDPD_CTRL_1_L_B0__Q2_FOR_XQ1XQ2___S 16 +#define PHYA_PHYRF_EDPD_CTRL_1_L_B0__Q1_FOR_XQ1XQ2___M 0x00000F00 +#define PHYA_PHYRF_EDPD_CTRL_1_L_B0__Q1_FOR_XQ1XQ2___S 8 +#define PHYA_PHYRF_EDPD_CTRL_1_L_B0__Q_FOR_XQ___M 0x0000000F +#define PHYA_PHYRF_EDPD_CTRL_1_L_B0__Q_FOR_XQ___S 0 +#define PHYA_PHYRF_EDPD_CTRL_1_L_B0___M 0x0F0F0F0F +#define PHYA_PHYRF_EDPD_CTRL_1_L_B0___S 0 + +#define PHYA_PHYRF_EDPD_CTRL_1_L_B1 (0x00498018) +#define PHYA_PHYRF_EDPD_CTRL_1_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_CTRL_1_L_B1___POR 0x08000008 +#define PHYA_PHYRF_EDPD_CTRL_1_L_B1__Q3_FOR_XQ3XQ4___POR 0x8 +#define PHYA_PHYRF_EDPD_CTRL_1_L_B1__Q2_FOR_XQ1XQ2___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_1_L_B1__Q1_FOR_XQ1XQ2___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_1_L_B1__Q_FOR_XQ___POR 0x8 +#define PHYA_PHYRF_EDPD_CTRL_1_L_B1__Q3_FOR_XQ3XQ4___M 0x0F000000 +#define PHYA_PHYRF_EDPD_CTRL_1_L_B1__Q3_FOR_XQ3XQ4___S 24 +#define PHYA_PHYRF_EDPD_CTRL_1_L_B1__Q2_FOR_XQ1XQ2___M 0x000F0000 +#define PHYA_PHYRF_EDPD_CTRL_1_L_B1__Q2_FOR_XQ1XQ2___S 16 +#define PHYA_PHYRF_EDPD_CTRL_1_L_B1__Q1_FOR_XQ1XQ2___M 0x00000F00 +#define PHYA_PHYRF_EDPD_CTRL_1_L_B1__Q1_FOR_XQ1XQ2___S 8 +#define PHYA_PHYRF_EDPD_CTRL_1_L_B1__Q_FOR_XQ___M 0x0000000F +#define PHYA_PHYRF_EDPD_CTRL_1_L_B1__Q_FOR_XQ___S 0 +#define PHYA_PHYRF_EDPD_CTRL_1_L_B1___M 0x0F0F0F0F +#define PHYA_PHYRF_EDPD_CTRL_1_L_B1___S 0 + +#define PHYA_PHYRF_EDPD_CTRL_1_U_B0 (0x0049001C) +#define PHYA_PHYRF_EDPD_CTRL_1_U_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_CTRL_1_U_B0___POR 0x00020108 +#define PHYA_PHYRF_EDPD_CTRL_1_U_B0__Q1_FOR_XQ1ABSXQ2ABSXQ3___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_1_U_B0__Q2_FOR_X0X0CONJXQ2___POR 0x2 +#define PHYA_PHYRF_EDPD_CTRL_1_U_B0__Q1_FOR_X0X0CONJXQ1___POR 0x1 +#define PHYA_PHYRF_EDPD_CTRL_1_U_B0__Q4_FOR_XQ3XQ4___POR 0x8 +#define PHYA_PHYRF_EDPD_CTRL_1_U_B0__Q1_FOR_XQ1ABSXQ2ABSXQ3___M 0x0F000000 +#define PHYA_PHYRF_EDPD_CTRL_1_U_B0__Q1_FOR_XQ1ABSXQ2ABSXQ3___S 24 +#define PHYA_PHYRF_EDPD_CTRL_1_U_B0__Q2_FOR_X0X0CONJXQ2___M 0x00070000 +#define PHYA_PHYRF_EDPD_CTRL_1_U_B0__Q2_FOR_X0X0CONJXQ2___S 16 +#define PHYA_PHYRF_EDPD_CTRL_1_U_B0__Q1_FOR_X0X0CONJXQ1___M 0x00000700 +#define PHYA_PHYRF_EDPD_CTRL_1_U_B0__Q1_FOR_X0X0CONJXQ1___S 8 +#define PHYA_PHYRF_EDPD_CTRL_1_U_B0__Q4_FOR_XQ3XQ4___M 0x0000000F +#define PHYA_PHYRF_EDPD_CTRL_1_U_B0__Q4_FOR_XQ3XQ4___S 0 +#define PHYA_PHYRF_EDPD_CTRL_1_U_B0___M 0x0F07070F +#define PHYA_PHYRF_EDPD_CTRL_1_U_B0___S 0 + +#define PHYA_PHYRF_EDPD_CTRL_1_U_B1 (0x0049801C) +#define PHYA_PHYRF_EDPD_CTRL_1_U_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_CTRL_1_U_B1___POR 0x00020108 +#define PHYA_PHYRF_EDPD_CTRL_1_U_B1__Q1_FOR_XQ1ABSXQ2ABSXQ3___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_1_U_B1__Q2_FOR_X0X0CONJXQ2___POR 0x2 +#define PHYA_PHYRF_EDPD_CTRL_1_U_B1__Q1_FOR_X0X0CONJXQ1___POR 0x1 +#define PHYA_PHYRF_EDPD_CTRL_1_U_B1__Q4_FOR_XQ3XQ4___POR 0x8 +#define PHYA_PHYRF_EDPD_CTRL_1_U_B1__Q1_FOR_XQ1ABSXQ2ABSXQ3___M 0x0F000000 +#define PHYA_PHYRF_EDPD_CTRL_1_U_B1__Q1_FOR_XQ1ABSXQ2ABSXQ3___S 24 +#define PHYA_PHYRF_EDPD_CTRL_1_U_B1__Q2_FOR_X0X0CONJXQ2___M 0x00070000 +#define PHYA_PHYRF_EDPD_CTRL_1_U_B1__Q2_FOR_X0X0CONJXQ2___S 16 +#define PHYA_PHYRF_EDPD_CTRL_1_U_B1__Q1_FOR_X0X0CONJXQ1___M 0x00000700 +#define PHYA_PHYRF_EDPD_CTRL_1_U_B1__Q1_FOR_X0X0CONJXQ1___S 8 +#define PHYA_PHYRF_EDPD_CTRL_1_U_B1__Q4_FOR_XQ3XQ4___M 0x0000000F +#define PHYA_PHYRF_EDPD_CTRL_1_U_B1__Q4_FOR_XQ3XQ4___S 0 +#define PHYA_PHYRF_EDPD_CTRL_1_U_B1___M 0x0F07070F +#define PHYA_PHYRF_EDPD_CTRL_1_U_B1___S 0 + +#define PHYA_PHYRF_EDPD_CTRL_2_L_B0 (0x00490020) +#define PHYA_PHYRF_EDPD_CTRL_2_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_CTRL_2_L_B0___POR 0x00000201 +#define PHYA_PHYRF_EDPD_CTRL_2_L_B0__Q3_FOR_XQ1ABSXQ2ABSXQ3___POR 0x2 +#define PHYA_PHYRF_EDPD_CTRL_2_L_B0__Q2_FOR_XQ1ABSXQ2ABSXQ3___POR 0x1 +#define PHYA_PHYRF_EDPD_CTRL_2_L_B0__Q3_FOR_XQ1ABSXQ2ABSXQ3___M 0x00000700 +#define PHYA_PHYRF_EDPD_CTRL_2_L_B0__Q3_FOR_XQ1ABSXQ2ABSXQ3___S 8 +#define PHYA_PHYRF_EDPD_CTRL_2_L_B0__Q2_FOR_XQ1ABSXQ2ABSXQ3___M 0x00000007 +#define PHYA_PHYRF_EDPD_CTRL_2_L_B0__Q2_FOR_XQ1ABSXQ2ABSXQ3___S 0 +#define PHYA_PHYRF_EDPD_CTRL_2_L_B0___M 0x00000707 +#define PHYA_PHYRF_EDPD_CTRL_2_L_B0___S 0 + +#define PHYA_PHYRF_EDPD_CTRL_2_L_B1 (0x00498020) +#define PHYA_PHYRF_EDPD_CTRL_2_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_CTRL_2_L_B1___POR 0x00000201 +#define PHYA_PHYRF_EDPD_CTRL_2_L_B1__Q3_FOR_XQ1ABSXQ2ABSXQ3___POR 0x2 +#define PHYA_PHYRF_EDPD_CTRL_2_L_B1__Q2_FOR_XQ1ABSXQ2ABSXQ3___POR 0x1 +#define PHYA_PHYRF_EDPD_CTRL_2_L_B1__Q3_FOR_XQ1ABSXQ2ABSXQ3___M 0x00000700 +#define PHYA_PHYRF_EDPD_CTRL_2_L_B1__Q3_FOR_XQ1ABSXQ2ABSXQ3___S 8 +#define PHYA_PHYRF_EDPD_CTRL_2_L_B1__Q2_FOR_XQ1ABSXQ2ABSXQ3___M 0x00000007 +#define PHYA_PHYRF_EDPD_CTRL_2_L_B1__Q2_FOR_XQ1ABSXQ2ABSXQ3___S 0 +#define PHYA_PHYRF_EDPD_CTRL_2_L_B1___M 0x00000707 +#define PHYA_PHYRF_EDPD_CTRL_2_L_B1___S 0 + +#define PHYA_PHYRF_EDPD_CTRL_2_U_B0 (0x00490024) +#define PHYA_PHYRF_EDPD_CTRL_2_U_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_CTRL_2_U_B0___POR 0x000080BE +#define PHYA_PHYRF_EDPD_CTRL_2_U_B0__DELAY_DDR_1___POR 0x080BE +#define PHYA_PHYRF_EDPD_CTRL_2_U_B0__DELAY_DDR_1___M 0x0003FFFF +#define PHYA_PHYRF_EDPD_CTRL_2_U_B0__DELAY_DDR_1___S 0 +#define PHYA_PHYRF_EDPD_CTRL_2_U_B0___M 0x0003FFFF +#define PHYA_PHYRF_EDPD_CTRL_2_U_B0___S 0 + +#define PHYA_PHYRF_EDPD_CTRL_2_U_B1 (0x00498024) +#define PHYA_PHYRF_EDPD_CTRL_2_U_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_CTRL_2_U_B1___POR 0x000080BE +#define PHYA_PHYRF_EDPD_CTRL_2_U_B1__DELAY_DDR_1___POR 0x080BE +#define PHYA_PHYRF_EDPD_CTRL_2_U_B1__DELAY_DDR_1___M 0x0003FFFF +#define PHYA_PHYRF_EDPD_CTRL_2_U_B1__DELAY_DDR_1___S 0 +#define PHYA_PHYRF_EDPD_CTRL_2_U_B1___M 0x0003FFFF +#define PHYA_PHYRF_EDPD_CTRL_2_U_B1___S 0 + +#define PHYA_PHYRF_EDPD_CTRL_3_L_B0 (0x00490028) +#define PHYA_PHYRF_EDPD_CTRL_3_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_CTRL_3_L_B0___POR 0x00012416 +#define PHYA_PHYRF_EDPD_CTRL_3_L_B0__DELAY_DDR_2___POR 0x12416 +#define PHYA_PHYRF_EDPD_CTRL_3_L_B0__DELAY_DDR_2___M 0x0003FFFF +#define PHYA_PHYRF_EDPD_CTRL_3_L_B0__DELAY_DDR_2___S 0 +#define PHYA_PHYRF_EDPD_CTRL_3_L_B0___M 0x0003FFFF +#define PHYA_PHYRF_EDPD_CTRL_3_L_B0___S 0 + +#define PHYA_PHYRF_EDPD_CTRL_3_L_B1 (0x00498028) +#define PHYA_PHYRF_EDPD_CTRL_3_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_CTRL_3_L_B1___POR 0x00012416 +#define PHYA_PHYRF_EDPD_CTRL_3_L_B1__DELAY_DDR_2___POR 0x12416 +#define PHYA_PHYRF_EDPD_CTRL_3_L_B1__DELAY_DDR_2___M 0x0003FFFF +#define PHYA_PHYRF_EDPD_CTRL_3_L_B1__DELAY_DDR_2___S 0 +#define PHYA_PHYRF_EDPD_CTRL_3_L_B1___M 0x0003FFFF +#define PHYA_PHYRF_EDPD_CTRL_3_L_B1___S 0 + +#define PHYA_PHYRF_EDPD_CTRL_4_L_B0 (0x00490030) +#define PHYA_PHYRF_EDPD_CTRL_4_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_CTRL_4_L_B0___POR 0x06060606 +#define PHYA_PHYRF_EDPD_CTRL_4_L_B0__MEMDPD_STANDALONE_COEFSHIFT_3___POR 0x6 +#define PHYA_PHYRF_EDPD_CTRL_4_L_B0__MEMDPD_STANDALONE_COEFSHIFT_2___POR 0x6 +#define PHYA_PHYRF_EDPD_CTRL_4_L_B0__MEMDPD_STANDALONE_COEFSHIFT_1___POR 0x6 +#define PHYA_PHYRF_EDPD_CTRL_4_L_B0__MEMDPD_STANDALONE_COEFSHIFT_0___POR 0x6 +#define PHYA_PHYRF_EDPD_CTRL_4_L_B0__MEMDPD_STANDALONE_COEFSHIFT_3___M 0x0F000000 +#define PHYA_PHYRF_EDPD_CTRL_4_L_B0__MEMDPD_STANDALONE_COEFSHIFT_3___S 24 +#define PHYA_PHYRF_EDPD_CTRL_4_L_B0__MEMDPD_STANDALONE_COEFSHIFT_2___M 0x000F0000 +#define PHYA_PHYRF_EDPD_CTRL_4_L_B0__MEMDPD_STANDALONE_COEFSHIFT_2___S 16 +#define PHYA_PHYRF_EDPD_CTRL_4_L_B0__MEMDPD_STANDALONE_COEFSHIFT_1___M 0x00000F00 +#define PHYA_PHYRF_EDPD_CTRL_4_L_B0__MEMDPD_STANDALONE_COEFSHIFT_1___S 8 +#define PHYA_PHYRF_EDPD_CTRL_4_L_B0__MEMDPD_STANDALONE_COEFSHIFT_0___M 0x0000000F +#define PHYA_PHYRF_EDPD_CTRL_4_L_B0__MEMDPD_STANDALONE_COEFSHIFT_0___S 0 +#define PHYA_PHYRF_EDPD_CTRL_4_L_B0___M 0x0F0F0F0F +#define PHYA_PHYRF_EDPD_CTRL_4_L_B0___S 0 + +#define PHYA_PHYRF_EDPD_CTRL_4_L_B1 (0x00498030) +#define PHYA_PHYRF_EDPD_CTRL_4_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_CTRL_4_L_B1___POR 0x06060606 +#define PHYA_PHYRF_EDPD_CTRL_4_L_B1__MEMDPD_STANDALONE_COEFSHIFT_3___POR 0x6 +#define PHYA_PHYRF_EDPD_CTRL_4_L_B1__MEMDPD_STANDALONE_COEFSHIFT_2___POR 0x6 +#define PHYA_PHYRF_EDPD_CTRL_4_L_B1__MEMDPD_STANDALONE_COEFSHIFT_1___POR 0x6 +#define PHYA_PHYRF_EDPD_CTRL_4_L_B1__MEMDPD_STANDALONE_COEFSHIFT_0___POR 0x6 +#define PHYA_PHYRF_EDPD_CTRL_4_L_B1__MEMDPD_STANDALONE_COEFSHIFT_3___M 0x0F000000 +#define PHYA_PHYRF_EDPD_CTRL_4_L_B1__MEMDPD_STANDALONE_COEFSHIFT_3___S 24 +#define PHYA_PHYRF_EDPD_CTRL_4_L_B1__MEMDPD_STANDALONE_COEFSHIFT_2___M 0x000F0000 +#define PHYA_PHYRF_EDPD_CTRL_4_L_B1__MEMDPD_STANDALONE_COEFSHIFT_2___S 16 +#define PHYA_PHYRF_EDPD_CTRL_4_L_B1__MEMDPD_STANDALONE_COEFSHIFT_1___M 0x00000F00 +#define PHYA_PHYRF_EDPD_CTRL_4_L_B1__MEMDPD_STANDALONE_COEFSHIFT_1___S 8 +#define PHYA_PHYRF_EDPD_CTRL_4_L_B1__MEMDPD_STANDALONE_COEFSHIFT_0___M 0x0000000F +#define PHYA_PHYRF_EDPD_CTRL_4_L_B1__MEMDPD_STANDALONE_COEFSHIFT_0___S 0 +#define PHYA_PHYRF_EDPD_CTRL_4_L_B1___M 0x0F0F0F0F +#define PHYA_PHYRF_EDPD_CTRL_4_L_B1___S 0 + +#define PHYA_PHYRF_EDPD_CTRL_4_U_B0 (0x00490034) +#define PHYA_PHYRF_EDPD_CTRL_4_U_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_CTRL_4_U_B0___POR 0x06060606 +#define PHYA_PHYRF_EDPD_CTRL_4_U_B0__MEMDPD_STANDALONE_COEFSHIFT_7___POR 0x6 +#define PHYA_PHYRF_EDPD_CTRL_4_U_B0__MEMDPD_STANDALONE_COEFSHIFT_6___POR 0x6 +#define PHYA_PHYRF_EDPD_CTRL_4_U_B0__MEMDPD_STANDALONE_COEFSHIFT_5___POR 0x6 +#define PHYA_PHYRF_EDPD_CTRL_4_U_B0__MEMDPD_STANDALONE_COEFSHIFT_4___POR 0x6 +#define PHYA_PHYRF_EDPD_CTRL_4_U_B0__MEMDPD_STANDALONE_COEFSHIFT_7___M 0x0F000000 +#define PHYA_PHYRF_EDPD_CTRL_4_U_B0__MEMDPD_STANDALONE_COEFSHIFT_7___S 24 +#define PHYA_PHYRF_EDPD_CTRL_4_U_B0__MEMDPD_STANDALONE_COEFSHIFT_6___M 0x000F0000 +#define PHYA_PHYRF_EDPD_CTRL_4_U_B0__MEMDPD_STANDALONE_COEFSHIFT_6___S 16 +#define PHYA_PHYRF_EDPD_CTRL_4_U_B0__MEMDPD_STANDALONE_COEFSHIFT_5___M 0x00000F00 +#define PHYA_PHYRF_EDPD_CTRL_4_U_B0__MEMDPD_STANDALONE_COEFSHIFT_5___S 8 +#define PHYA_PHYRF_EDPD_CTRL_4_U_B0__MEMDPD_STANDALONE_COEFSHIFT_4___M 0x0000000F +#define PHYA_PHYRF_EDPD_CTRL_4_U_B0__MEMDPD_STANDALONE_COEFSHIFT_4___S 0 +#define PHYA_PHYRF_EDPD_CTRL_4_U_B0___M 0x0F0F0F0F +#define PHYA_PHYRF_EDPD_CTRL_4_U_B0___S 0 + +#define PHYA_PHYRF_EDPD_CTRL_4_U_B1 (0x00498034) +#define PHYA_PHYRF_EDPD_CTRL_4_U_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_CTRL_4_U_B1___POR 0x06060606 +#define PHYA_PHYRF_EDPD_CTRL_4_U_B1__MEMDPD_STANDALONE_COEFSHIFT_7___POR 0x6 +#define PHYA_PHYRF_EDPD_CTRL_4_U_B1__MEMDPD_STANDALONE_COEFSHIFT_6___POR 0x6 +#define PHYA_PHYRF_EDPD_CTRL_4_U_B1__MEMDPD_STANDALONE_COEFSHIFT_5___POR 0x6 +#define PHYA_PHYRF_EDPD_CTRL_4_U_B1__MEMDPD_STANDALONE_COEFSHIFT_4___POR 0x6 +#define PHYA_PHYRF_EDPD_CTRL_4_U_B1__MEMDPD_STANDALONE_COEFSHIFT_7___M 0x0F000000 +#define PHYA_PHYRF_EDPD_CTRL_4_U_B1__MEMDPD_STANDALONE_COEFSHIFT_7___S 24 +#define PHYA_PHYRF_EDPD_CTRL_4_U_B1__MEMDPD_STANDALONE_COEFSHIFT_6___M 0x000F0000 +#define PHYA_PHYRF_EDPD_CTRL_4_U_B1__MEMDPD_STANDALONE_COEFSHIFT_6___S 16 +#define PHYA_PHYRF_EDPD_CTRL_4_U_B1__MEMDPD_STANDALONE_COEFSHIFT_5___M 0x00000F00 +#define PHYA_PHYRF_EDPD_CTRL_4_U_B1__MEMDPD_STANDALONE_COEFSHIFT_5___S 8 +#define PHYA_PHYRF_EDPD_CTRL_4_U_B1__MEMDPD_STANDALONE_COEFSHIFT_4___M 0x0000000F +#define PHYA_PHYRF_EDPD_CTRL_4_U_B1__MEMDPD_STANDALONE_COEFSHIFT_4___S 0 +#define PHYA_PHYRF_EDPD_CTRL_4_U_B1___M 0x0F0F0F0F +#define PHYA_PHYRF_EDPD_CTRL_4_U_B1___S 0 + +#define PHYA_PHYRF_EDPD_CTRL_5_L_B0 (0x00490038) +#define PHYA_PHYRF_EDPD_CTRL_5_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_CTRL_5_L_B0___POR 0x00000000 +#define PHYA_PHYRF_EDPD_CTRL_5_L_B0__MEMDPD_BIN_SIZE_SEL_3___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_5_L_B0__MEMDPD_BIN_SIZE_SEL_2___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_5_L_B0__MEMDPD_BIN_SIZE_SEL_1___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_5_L_B0__MEMDPD_BIN_SIZE_SEL_0___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_5_L_B0__MEMDPD_BIN_SIZE_SEL_3___M 0x01000000 +#define PHYA_PHYRF_EDPD_CTRL_5_L_B0__MEMDPD_BIN_SIZE_SEL_3___S 24 +#define PHYA_PHYRF_EDPD_CTRL_5_L_B0__MEMDPD_BIN_SIZE_SEL_2___M 0x00010000 +#define PHYA_PHYRF_EDPD_CTRL_5_L_B0__MEMDPD_BIN_SIZE_SEL_2___S 16 +#define PHYA_PHYRF_EDPD_CTRL_5_L_B0__MEMDPD_BIN_SIZE_SEL_1___M 0x00000100 +#define PHYA_PHYRF_EDPD_CTRL_5_L_B0__MEMDPD_BIN_SIZE_SEL_1___S 8 +#define PHYA_PHYRF_EDPD_CTRL_5_L_B0__MEMDPD_BIN_SIZE_SEL_0___M 0x00000001 +#define PHYA_PHYRF_EDPD_CTRL_5_L_B0__MEMDPD_BIN_SIZE_SEL_0___S 0 +#define PHYA_PHYRF_EDPD_CTRL_5_L_B0___M 0x01010101 +#define PHYA_PHYRF_EDPD_CTRL_5_L_B0___S 0 + +#define PHYA_PHYRF_EDPD_CTRL_5_L_B1 (0x00498038) +#define PHYA_PHYRF_EDPD_CTRL_5_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_CTRL_5_L_B1___POR 0x00000000 +#define PHYA_PHYRF_EDPD_CTRL_5_L_B1__MEMDPD_BIN_SIZE_SEL_3___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_5_L_B1__MEMDPD_BIN_SIZE_SEL_2___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_5_L_B1__MEMDPD_BIN_SIZE_SEL_1___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_5_L_B1__MEMDPD_BIN_SIZE_SEL_0___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_5_L_B1__MEMDPD_BIN_SIZE_SEL_3___M 0x01000000 +#define PHYA_PHYRF_EDPD_CTRL_5_L_B1__MEMDPD_BIN_SIZE_SEL_3___S 24 +#define PHYA_PHYRF_EDPD_CTRL_5_L_B1__MEMDPD_BIN_SIZE_SEL_2___M 0x00010000 +#define PHYA_PHYRF_EDPD_CTRL_5_L_B1__MEMDPD_BIN_SIZE_SEL_2___S 16 +#define PHYA_PHYRF_EDPD_CTRL_5_L_B1__MEMDPD_BIN_SIZE_SEL_1___M 0x00000100 +#define PHYA_PHYRF_EDPD_CTRL_5_L_B1__MEMDPD_BIN_SIZE_SEL_1___S 8 +#define PHYA_PHYRF_EDPD_CTRL_5_L_B1__MEMDPD_BIN_SIZE_SEL_0___M 0x00000001 +#define PHYA_PHYRF_EDPD_CTRL_5_L_B1__MEMDPD_BIN_SIZE_SEL_0___S 0 +#define PHYA_PHYRF_EDPD_CTRL_5_L_B1___M 0x01010101 +#define PHYA_PHYRF_EDPD_CTRL_5_L_B1___S 0 + +#define PHYA_PHYRF_EDPD_CTRL_5_U_B0 (0x0049003C) +#define PHYA_PHYRF_EDPD_CTRL_5_U_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_CTRL_5_U_B0___POR 0x00000000 +#define PHYA_PHYRF_EDPD_CTRL_5_U_B0__MEMDPD_BIN_SIZE_SEL_7___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_5_U_B0__MEMDPD_BIN_SIZE_SEL_6___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_5_U_B0__MEMDPD_BIN_SIZE_SEL_5___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_5_U_B0__MEMDPD_BIN_SIZE_SEL_4___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_5_U_B0__MEMDPD_BIN_SIZE_SEL_7___M 0x01000000 +#define PHYA_PHYRF_EDPD_CTRL_5_U_B0__MEMDPD_BIN_SIZE_SEL_7___S 24 +#define PHYA_PHYRF_EDPD_CTRL_5_U_B0__MEMDPD_BIN_SIZE_SEL_6___M 0x00010000 +#define PHYA_PHYRF_EDPD_CTRL_5_U_B0__MEMDPD_BIN_SIZE_SEL_6___S 16 +#define PHYA_PHYRF_EDPD_CTRL_5_U_B0__MEMDPD_BIN_SIZE_SEL_5___M 0x00000100 +#define PHYA_PHYRF_EDPD_CTRL_5_U_B0__MEMDPD_BIN_SIZE_SEL_5___S 8 +#define PHYA_PHYRF_EDPD_CTRL_5_U_B0__MEMDPD_BIN_SIZE_SEL_4___M 0x00000001 +#define PHYA_PHYRF_EDPD_CTRL_5_U_B0__MEMDPD_BIN_SIZE_SEL_4___S 0 +#define PHYA_PHYRF_EDPD_CTRL_5_U_B0___M 0x01010101 +#define PHYA_PHYRF_EDPD_CTRL_5_U_B0___S 0 + +#define PHYA_PHYRF_EDPD_CTRL_5_U_B1 (0x0049803C) +#define PHYA_PHYRF_EDPD_CTRL_5_U_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_CTRL_5_U_B1___POR 0x00000000 +#define PHYA_PHYRF_EDPD_CTRL_5_U_B1__MEMDPD_BIN_SIZE_SEL_7___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_5_U_B1__MEMDPD_BIN_SIZE_SEL_6___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_5_U_B1__MEMDPD_BIN_SIZE_SEL_5___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_5_U_B1__MEMDPD_BIN_SIZE_SEL_4___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_5_U_B1__MEMDPD_BIN_SIZE_SEL_7___M 0x01000000 +#define PHYA_PHYRF_EDPD_CTRL_5_U_B1__MEMDPD_BIN_SIZE_SEL_7___S 24 +#define PHYA_PHYRF_EDPD_CTRL_5_U_B1__MEMDPD_BIN_SIZE_SEL_6___M 0x00010000 +#define PHYA_PHYRF_EDPD_CTRL_5_U_B1__MEMDPD_BIN_SIZE_SEL_6___S 16 +#define PHYA_PHYRF_EDPD_CTRL_5_U_B1__MEMDPD_BIN_SIZE_SEL_5___M 0x00000100 +#define PHYA_PHYRF_EDPD_CTRL_5_U_B1__MEMDPD_BIN_SIZE_SEL_5___S 8 +#define PHYA_PHYRF_EDPD_CTRL_5_U_B1__MEMDPD_BIN_SIZE_SEL_4___M 0x00000001 +#define PHYA_PHYRF_EDPD_CTRL_5_U_B1__MEMDPD_BIN_SIZE_SEL_4___S 0 +#define PHYA_PHYRF_EDPD_CTRL_5_U_B1___M 0x01010101 +#define PHYA_PHYRF_EDPD_CTRL_5_U_B1___S 0 + +#define PHYA_PHYRF_EDPD_CTRL_6_L_B0 (0x00490040) +#define PHYA_PHYRF_EDPD_CTRL_6_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_CTRL_6_L_B0___POR 0x00000000 +#define PHYA_PHYRF_EDPD_CTRL_6_L_B0__POST_DPD_SCALING_ENABLE_3___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_6_L_B0__POST_DPD_SCALING_ENABLE_2___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_6_L_B0__POST_DPD_SCALING_ENABLE_1___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_6_L_B0__POST_DPD_SCALING_ENABLE_0___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_6_L_B0__POST_DPD_SCALING_ENABLE_3___M 0x01000000 +#define PHYA_PHYRF_EDPD_CTRL_6_L_B0__POST_DPD_SCALING_ENABLE_3___S 24 +#define PHYA_PHYRF_EDPD_CTRL_6_L_B0__POST_DPD_SCALING_ENABLE_2___M 0x00010000 +#define PHYA_PHYRF_EDPD_CTRL_6_L_B0__POST_DPD_SCALING_ENABLE_2___S 16 +#define PHYA_PHYRF_EDPD_CTRL_6_L_B0__POST_DPD_SCALING_ENABLE_1___M 0x00000100 +#define PHYA_PHYRF_EDPD_CTRL_6_L_B0__POST_DPD_SCALING_ENABLE_1___S 8 +#define PHYA_PHYRF_EDPD_CTRL_6_L_B0__POST_DPD_SCALING_ENABLE_0___M 0x00000001 +#define PHYA_PHYRF_EDPD_CTRL_6_L_B0__POST_DPD_SCALING_ENABLE_0___S 0 +#define PHYA_PHYRF_EDPD_CTRL_6_L_B0___M 0x01010101 +#define PHYA_PHYRF_EDPD_CTRL_6_L_B0___S 0 + +#define PHYA_PHYRF_EDPD_CTRL_6_L_B1 (0x00498040) +#define PHYA_PHYRF_EDPD_CTRL_6_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_CTRL_6_L_B1___POR 0x00000000 +#define PHYA_PHYRF_EDPD_CTRL_6_L_B1__POST_DPD_SCALING_ENABLE_3___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_6_L_B1__POST_DPD_SCALING_ENABLE_2___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_6_L_B1__POST_DPD_SCALING_ENABLE_1___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_6_L_B1__POST_DPD_SCALING_ENABLE_0___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_6_L_B1__POST_DPD_SCALING_ENABLE_3___M 0x01000000 +#define PHYA_PHYRF_EDPD_CTRL_6_L_B1__POST_DPD_SCALING_ENABLE_3___S 24 +#define PHYA_PHYRF_EDPD_CTRL_6_L_B1__POST_DPD_SCALING_ENABLE_2___M 0x00010000 +#define PHYA_PHYRF_EDPD_CTRL_6_L_B1__POST_DPD_SCALING_ENABLE_2___S 16 +#define PHYA_PHYRF_EDPD_CTRL_6_L_B1__POST_DPD_SCALING_ENABLE_1___M 0x00000100 +#define PHYA_PHYRF_EDPD_CTRL_6_L_B1__POST_DPD_SCALING_ENABLE_1___S 8 +#define PHYA_PHYRF_EDPD_CTRL_6_L_B1__POST_DPD_SCALING_ENABLE_0___M 0x00000001 +#define PHYA_PHYRF_EDPD_CTRL_6_L_B1__POST_DPD_SCALING_ENABLE_0___S 0 +#define PHYA_PHYRF_EDPD_CTRL_6_L_B1___M 0x01010101 +#define PHYA_PHYRF_EDPD_CTRL_6_L_B1___S 0 + +#define PHYA_PHYRF_EDPD_CTRL_6_U_B0 (0x00490044) +#define PHYA_PHYRF_EDPD_CTRL_6_U_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_CTRL_6_U_B0___POR 0x00000000 +#define PHYA_PHYRF_EDPD_CTRL_6_U_B0__POST_DPD_SCALING_ENABLE_7___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_6_U_B0__POST_DPD_SCALING_ENABLE_6___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_6_U_B0__POST_DPD_SCALING_ENABLE_5___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_6_U_B0__POST_DPD_SCALING_ENABLE_4___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_6_U_B0__POST_DPD_SCALING_ENABLE_7___M 0x01000000 +#define PHYA_PHYRF_EDPD_CTRL_6_U_B0__POST_DPD_SCALING_ENABLE_7___S 24 +#define PHYA_PHYRF_EDPD_CTRL_6_U_B0__POST_DPD_SCALING_ENABLE_6___M 0x00010000 +#define PHYA_PHYRF_EDPD_CTRL_6_U_B0__POST_DPD_SCALING_ENABLE_6___S 16 +#define PHYA_PHYRF_EDPD_CTRL_6_U_B0__POST_DPD_SCALING_ENABLE_5___M 0x00000100 +#define PHYA_PHYRF_EDPD_CTRL_6_U_B0__POST_DPD_SCALING_ENABLE_5___S 8 +#define PHYA_PHYRF_EDPD_CTRL_6_U_B0__POST_DPD_SCALING_ENABLE_4___M 0x00000001 +#define PHYA_PHYRF_EDPD_CTRL_6_U_B0__POST_DPD_SCALING_ENABLE_4___S 0 +#define PHYA_PHYRF_EDPD_CTRL_6_U_B0___M 0x01010101 +#define PHYA_PHYRF_EDPD_CTRL_6_U_B0___S 0 + +#define PHYA_PHYRF_EDPD_CTRL_6_U_B1 (0x00498044) +#define PHYA_PHYRF_EDPD_CTRL_6_U_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_CTRL_6_U_B1___POR 0x00000000 +#define PHYA_PHYRF_EDPD_CTRL_6_U_B1__POST_DPD_SCALING_ENABLE_7___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_6_U_B1__POST_DPD_SCALING_ENABLE_6___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_6_U_B1__POST_DPD_SCALING_ENABLE_5___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_6_U_B1__POST_DPD_SCALING_ENABLE_4___POR 0x0 +#define PHYA_PHYRF_EDPD_CTRL_6_U_B1__POST_DPD_SCALING_ENABLE_7___M 0x01000000 +#define PHYA_PHYRF_EDPD_CTRL_6_U_B1__POST_DPD_SCALING_ENABLE_7___S 24 +#define PHYA_PHYRF_EDPD_CTRL_6_U_B1__POST_DPD_SCALING_ENABLE_6___M 0x00010000 +#define PHYA_PHYRF_EDPD_CTRL_6_U_B1__POST_DPD_SCALING_ENABLE_6___S 16 +#define PHYA_PHYRF_EDPD_CTRL_6_U_B1__POST_DPD_SCALING_ENABLE_5___M 0x00000100 +#define PHYA_PHYRF_EDPD_CTRL_6_U_B1__POST_DPD_SCALING_ENABLE_5___S 8 +#define PHYA_PHYRF_EDPD_CTRL_6_U_B1__POST_DPD_SCALING_ENABLE_4___M 0x00000001 +#define PHYA_PHYRF_EDPD_CTRL_6_U_B1__POST_DPD_SCALING_ENABLE_4___S 0 +#define PHYA_PHYRF_EDPD_CTRL_6_U_B1___M 0x01010101 +#define PHYA_PHYRF_EDPD_CTRL_6_U_B1___S 0 + +#define PHYA_PHYRF_EDPD_CTRL_7_L_B0 (0x00490048) +#define PHYA_PHYRF_EDPD_CTRL_7_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_CTRL_7_L_B0___POR 0x80808080 +#define PHYA_PHYRF_EDPD_CTRL_7_L_B0__POST_DPD_SCALING_3___POR 0x80 +#define PHYA_PHYRF_EDPD_CTRL_7_L_B0__POST_DPD_SCALING_2___POR 0x80 +#define PHYA_PHYRF_EDPD_CTRL_7_L_B0__POST_DPD_SCALING_1___POR 0x80 +#define PHYA_PHYRF_EDPD_CTRL_7_L_B0__POST_DPD_SCALING_0___POR 0x80 +#define PHYA_PHYRF_EDPD_CTRL_7_L_B0__POST_DPD_SCALING_3___M 0xFF000000 +#define PHYA_PHYRF_EDPD_CTRL_7_L_B0__POST_DPD_SCALING_3___S 24 +#define PHYA_PHYRF_EDPD_CTRL_7_L_B0__POST_DPD_SCALING_2___M 0x00FF0000 +#define PHYA_PHYRF_EDPD_CTRL_7_L_B0__POST_DPD_SCALING_2___S 16 +#define PHYA_PHYRF_EDPD_CTRL_7_L_B0__POST_DPD_SCALING_1___M 0x0000FF00 +#define PHYA_PHYRF_EDPD_CTRL_7_L_B0__POST_DPD_SCALING_1___S 8 +#define PHYA_PHYRF_EDPD_CTRL_7_L_B0__POST_DPD_SCALING_0___M 0x000000FF +#define PHYA_PHYRF_EDPD_CTRL_7_L_B0__POST_DPD_SCALING_0___S 0 +#define PHYA_PHYRF_EDPD_CTRL_7_L_B0___M 0xFFFFFFFF +#define PHYA_PHYRF_EDPD_CTRL_7_L_B0___S 0 + +#define PHYA_PHYRF_EDPD_CTRL_7_L_B1 (0x00498048) +#define PHYA_PHYRF_EDPD_CTRL_7_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_CTRL_7_L_B1___POR 0x80808080 +#define PHYA_PHYRF_EDPD_CTRL_7_L_B1__POST_DPD_SCALING_3___POR 0x80 +#define PHYA_PHYRF_EDPD_CTRL_7_L_B1__POST_DPD_SCALING_2___POR 0x80 +#define PHYA_PHYRF_EDPD_CTRL_7_L_B1__POST_DPD_SCALING_1___POR 0x80 +#define PHYA_PHYRF_EDPD_CTRL_7_L_B1__POST_DPD_SCALING_0___POR 0x80 +#define PHYA_PHYRF_EDPD_CTRL_7_L_B1__POST_DPD_SCALING_3___M 0xFF000000 +#define PHYA_PHYRF_EDPD_CTRL_7_L_B1__POST_DPD_SCALING_3___S 24 +#define PHYA_PHYRF_EDPD_CTRL_7_L_B1__POST_DPD_SCALING_2___M 0x00FF0000 +#define PHYA_PHYRF_EDPD_CTRL_7_L_B1__POST_DPD_SCALING_2___S 16 +#define PHYA_PHYRF_EDPD_CTRL_7_L_B1__POST_DPD_SCALING_1___M 0x0000FF00 +#define PHYA_PHYRF_EDPD_CTRL_7_L_B1__POST_DPD_SCALING_1___S 8 +#define PHYA_PHYRF_EDPD_CTRL_7_L_B1__POST_DPD_SCALING_0___M 0x000000FF +#define PHYA_PHYRF_EDPD_CTRL_7_L_B1__POST_DPD_SCALING_0___S 0 +#define PHYA_PHYRF_EDPD_CTRL_7_L_B1___M 0xFFFFFFFF +#define PHYA_PHYRF_EDPD_CTRL_7_L_B1___S 0 + +#define PHYA_PHYRF_EDPD_CTRL_7_U_B0 (0x0049004C) +#define PHYA_PHYRF_EDPD_CTRL_7_U_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_CTRL_7_U_B0___POR 0x80808080 +#define PHYA_PHYRF_EDPD_CTRL_7_U_B0__POST_DPD_SCALING_7___POR 0x80 +#define PHYA_PHYRF_EDPD_CTRL_7_U_B0__POST_DPD_SCALING_6___POR 0x80 +#define PHYA_PHYRF_EDPD_CTRL_7_U_B0__POST_DPD_SCALING_5___POR 0x80 +#define PHYA_PHYRF_EDPD_CTRL_7_U_B0__POST_DPD_SCALING_4___POR 0x80 +#define PHYA_PHYRF_EDPD_CTRL_7_U_B0__POST_DPD_SCALING_7___M 0xFF000000 +#define PHYA_PHYRF_EDPD_CTRL_7_U_B0__POST_DPD_SCALING_7___S 24 +#define PHYA_PHYRF_EDPD_CTRL_7_U_B0__POST_DPD_SCALING_6___M 0x00FF0000 +#define PHYA_PHYRF_EDPD_CTRL_7_U_B0__POST_DPD_SCALING_6___S 16 +#define PHYA_PHYRF_EDPD_CTRL_7_U_B0__POST_DPD_SCALING_5___M 0x0000FF00 +#define PHYA_PHYRF_EDPD_CTRL_7_U_B0__POST_DPD_SCALING_5___S 8 +#define PHYA_PHYRF_EDPD_CTRL_7_U_B0__POST_DPD_SCALING_4___M 0x000000FF +#define PHYA_PHYRF_EDPD_CTRL_7_U_B0__POST_DPD_SCALING_4___S 0 +#define PHYA_PHYRF_EDPD_CTRL_7_U_B0___M 0xFFFFFFFF +#define PHYA_PHYRF_EDPD_CTRL_7_U_B0___S 0 + +#define PHYA_PHYRF_EDPD_CTRL_7_U_B1 (0x0049804C) +#define PHYA_PHYRF_EDPD_CTRL_7_U_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_CTRL_7_U_B1___POR 0x80808080 +#define PHYA_PHYRF_EDPD_CTRL_7_U_B1__POST_DPD_SCALING_7___POR 0x80 +#define PHYA_PHYRF_EDPD_CTRL_7_U_B1__POST_DPD_SCALING_6___POR 0x80 +#define PHYA_PHYRF_EDPD_CTRL_7_U_B1__POST_DPD_SCALING_5___POR 0x80 +#define PHYA_PHYRF_EDPD_CTRL_7_U_B1__POST_DPD_SCALING_4___POR 0x80 +#define PHYA_PHYRF_EDPD_CTRL_7_U_B1__POST_DPD_SCALING_7___M 0xFF000000 +#define PHYA_PHYRF_EDPD_CTRL_7_U_B1__POST_DPD_SCALING_7___S 24 +#define PHYA_PHYRF_EDPD_CTRL_7_U_B1__POST_DPD_SCALING_6___M 0x00FF0000 +#define PHYA_PHYRF_EDPD_CTRL_7_U_B1__POST_DPD_SCALING_6___S 16 +#define PHYA_PHYRF_EDPD_CTRL_7_U_B1__POST_DPD_SCALING_5___M 0x0000FF00 +#define PHYA_PHYRF_EDPD_CTRL_7_U_B1__POST_DPD_SCALING_5___S 8 +#define PHYA_PHYRF_EDPD_CTRL_7_U_B1__POST_DPD_SCALING_4___M 0x000000FF +#define PHYA_PHYRF_EDPD_CTRL_7_U_B1__POST_DPD_SCALING_4___S 0 +#define PHYA_PHYRF_EDPD_CTRL_7_U_B1___M 0xFFFFFFFF +#define PHYA_PHYRF_EDPD_CTRL_7_U_B1___S 0 + +#define PHYA_PHYRF_EDPD_CTRL_8_L_B0 (0x00490050) +#define PHYA_PHYRF_EDPD_CTRL_8_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_CTRL_8_L_B0___POR 0xFFFF0101 +#define PHYA_PHYRF_EDPD_CTRL_8_L_B0__EDPD_KERNEL_EN___POR 0xFFFF +#define PHYA_PHYRF_EDPD_CTRL_8_L_B0__XQ3XQ4XQ4_EN___POR 0x1 +#define PHYA_PHYRF_EDPD_CTRL_8_L_B0__XQ1XQ2XQ2_EN___POR 0x1 +#define PHYA_PHYRF_EDPD_CTRL_8_L_B0__EDPD_KERNEL_EN___M 0xFFFF0000 +#define PHYA_PHYRF_EDPD_CTRL_8_L_B0__EDPD_KERNEL_EN___S 16 +#define PHYA_PHYRF_EDPD_CTRL_8_L_B0__XQ3XQ4XQ4_EN___M 0x00000100 +#define PHYA_PHYRF_EDPD_CTRL_8_L_B0__XQ3XQ4XQ4_EN___S 8 +#define PHYA_PHYRF_EDPD_CTRL_8_L_B0__XQ1XQ2XQ2_EN___M 0x00000001 +#define PHYA_PHYRF_EDPD_CTRL_8_L_B0__XQ1XQ2XQ2_EN___S 0 +#define PHYA_PHYRF_EDPD_CTRL_8_L_B0___M 0xFFFF0101 +#define PHYA_PHYRF_EDPD_CTRL_8_L_B0___S 0 + +#define PHYA_PHYRF_EDPD_CTRL_8_L_B1 (0x00498050) +#define PHYA_PHYRF_EDPD_CTRL_8_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_CTRL_8_L_B1___POR 0xFFFF0101 +#define PHYA_PHYRF_EDPD_CTRL_8_L_B1__EDPD_KERNEL_EN___POR 0xFFFF +#define PHYA_PHYRF_EDPD_CTRL_8_L_B1__XQ3XQ4XQ4_EN___POR 0x1 +#define PHYA_PHYRF_EDPD_CTRL_8_L_B1__XQ1XQ2XQ2_EN___POR 0x1 +#define PHYA_PHYRF_EDPD_CTRL_8_L_B1__EDPD_KERNEL_EN___M 0xFFFF0000 +#define PHYA_PHYRF_EDPD_CTRL_8_L_B1__EDPD_KERNEL_EN___S 16 +#define PHYA_PHYRF_EDPD_CTRL_8_L_B1__XQ3XQ4XQ4_EN___M 0x00000100 +#define PHYA_PHYRF_EDPD_CTRL_8_L_B1__XQ3XQ4XQ4_EN___S 8 +#define PHYA_PHYRF_EDPD_CTRL_8_L_B1__XQ1XQ2XQ2_EN___M 0x00000001 +#define PHYA_PHYRF_EDPD_CTRL_8_L_B1__XQ1XQ2XQ2_EN___S 0 +#define PHYA_PHYRF_EDPD_CTRL_8_L_B1___M 0xFFFF0101 +#define PHYA_PHYRF_EDPD_CTRL_8_L_B1___S 0 + +#define PHYA_PHYRF_PAPRD_TABLE_TYPE_L_B0 (0x00490058) +#define PHYA_PHYRF_PAPRD_TABLE_TYPE_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PAPRD_TABLE_TYPE_L_B0___POR 0x00000000 +#define PHYA_PHYRF_PAPRD_TABLE_TYPE_L_B0__PAPRD_TABLE_TYPE___POR 0x00 +#define PHYA_PHYRF_PAPRD_TABLE_TYPE_L_B0__PAPRD_TABLE_TYPE___M 0x000000FF +#define PHYA_PHYRF_PAPRD_TABLE_TYPE_L_B0__PAPRD_TABLE_TYPE___S 0 +#define PHYA_PHYRF_PAPRD_TABLE_TYPE_L_B0___M 0x000000FF +#define PHYA_PHYRF_PAPRD_TABLE_TYPE_L_B0___S 0 + +#define PHYA_PHYRF_PAPRD_TABLE_TYPE_L_B1 (0x00498058) +#define PHYA_PHYRF_PAPRD_TABLE_TYPE_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_PAPRD_TABLE_TYPE_L_B1___POR 0x00000000 +#define PHYA_PHYRF_PAPRD_TABLE_TYPE_L_B1__PAPRD_TABLE_TYPE___POR 0x00 +#define PHYA_PHYRF_PAPRD_TABLE_TYPE_L_B1__PAPRD_TABLE_TYPE___M 0x000000FF +#define PHYA_PHYRF_PAPRD_TABLE_TYPE_L_B1__PAPRD_TABLE_TYPE___S 0 +#define PHYA_PHYRF_PAPRD_TABLE_TYPE_L_B1___M 0x000000FF +#define PHYA_PHYRF_PAPRD_TABLE_TYPE_L_B1___S 0 + +#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B0 (0x00490060) +#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B0___POR 0x00000000 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B0__PAPRD_VALID_GAIN_3___POR 0x00 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B0__PAPRD_VALID_GAIN_2___POR 0x00 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B0__PAPRD_VALID_GAIN_1___POR 0x00 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B0__PAPRD_VALID_GAIN_0___POR 0x00 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B0__PAPRD_VALID_GAIN_3___M 0x3F000000 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B0__PAPRD_VALID_GAIN_3___S 24 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B0__PAPRD_VALID_GAIN_2___M 0x003F0000 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B0__PAPRD_VALID_GAIN_2___S 16 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B0__PAPRD_VALID_GAIN_1___M 0x00003F00 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B0__PAPRD_VALID_GAIN_1___S 8 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B0__PAPRD_VALID_GAIN_0___M 0x0000003F +#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B0__PAPRD_VALID_GAIN_0___S 0 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B0___M 0x3F3F3F3F +#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B0___S 0 + +#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B1 (0x00498060) +#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B1___POR 0x00000000 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B1__PAPRD_VALID_GAIN_3___POR 0x00 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B1__PAPRD_VALID_GAIN_2___POR 0x00 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B1__PAPRD_VALID_GAIN_1___POR 0x00 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B1__PAPRD_VALID_GAIN_0___POR 0x00 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B1__PAPRD_VALID_GAIN_3___M 0x3F000000 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B1__PAPRD_VALID_GAIN_3___S 24 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B1__PAPRD_VALID_GAIN_2___M 0x003F0000 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B1__PAPRD_VALID_GAIN_2___S 16 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B1__PAPRD_VALID_GAIN_1___M 0x00003F00 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B1__PAPRD_VALID_GAIN_1___S 8 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B1__PAPRD_VALID_GAIN_0___M 0x0000003F +#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B1__PAPRD_VALID_GAIN_0___S 0 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B1___M 0x3F3F3F3F +#define PHYA_PHYRF_PAPRD_VALID_GAIN_L_B1___S 0 + +#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B0 (0x00490064) +#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B0___POR 0x00000000 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B0__PAPRD_VALID_GAIN_7___POR 0x00 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B0__PAPRD_VALID_GAIN_6___POR 0x00 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B0__PAPRD_VALID_GAIN_5___POR 0x00 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B0__PAPRD_VALID_GAIN_4___POR 0x00 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B0__PAPRD_VALID_GAIN_7___M 0x3F000000 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B0__PAPRD_VALID_GAIN_7___S 24 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B0__PAPRD_VALID_GAIN_6___M 0x003F0000 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B0__PAPRD_VALID_GAIN_6___S 16 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B0__PAPRD_VALID_GAIN_5___M 0x00003F00 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B0__PAPRD_VALID_GAIN_5___S 8 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B0__PAPRD_VALID_GAIN_4___M 0x0000003F +#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B0__PAPRD_VALID_GAIN_4___S 0 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B0___M 0x3F3F3F3F +#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B0___S 0 + +#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B1 (0x00498064) +#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B1___POR 0x00000000 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B1__PAPRD_VALID_GAIN_7___POR 0x00 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B1__PAPRD_VALID_GAIN_6___POR 0x00 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B1__PAPRD_VALID_GAIN_5___POR 0x00 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B1__PAPRD_VALID_GAIN_4___POR 0x00 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B1__PAPRD_VALID_GAIN_7___M 0x3F000000 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B1__PAPRD_VALID_GAIN_7___S 24 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B1__PAPRD_VALID_GAIN_6___M 0x003F0000 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B1__PAPRD_VALID_GAIN_6___S 16 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B1__PAPRD_VALID_GAIN_5___M 0x00003F00 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B1__PAPRD_VALID_GAIN_5___S 8 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B1__PAPRD_VALID_GAIN_4___M 0x0000003F +#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B1__PAPRD_VALID_GAIN_4___S 0 +#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B1___M 0x3F3F3F3F +#define PHYA_PHYRF_PAPRD_VALID_GAIN_U_B1___S 0 + +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B0 (0x00490068) +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B0___POR 0x00000000 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B0__PAPRD_SM_SIG_GAIN_1___POR 0x000 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B0__PAPRD_SM_SIG_GAIN_0___POR 0x000 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B0__PAPRD_SM_SIG_GAIN_1___M 0x03FF0000 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B0__PAPRD_SM_SIG_GAIN_1___S 16 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B0__PAPRD_SM_SIG_GAIN_0___M 0x000003FF +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B0__PAPRD_SM_SIG_GAIN_0___S 0 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B0___M 0x03FF03FF +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B0___S 0 + +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B1 (0x00498068) +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B1___POR 0x00000000 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B1__PAPRD_SM_SIG_GAIN_1___POR 0x000 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B1__PAPRD_SM_SIG_GAIN_0___POR 0x000 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B1__PAPRD_SM_SIG_GAIN_1___M 0x03FF0000 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B1__PAPRD_SM_SIG_GAIN_1___S 16 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B1__PAPRD_SM_SIG_GAIN_0___M 0x000003FF +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B1__PAPRD_SM_SIG_GAIN_0___S 0 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B1___M 0x03FF03FF +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_L_B1___S 0 + +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B0 (0x0049006C) +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B0___POR 0x00000000 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B0__PAPRD_SM_SIG_GAIN_3___POR 0x000 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B0__PAPRD_SM_SIG_GAIN_2___POR 0x000 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B0__PAPRD_SM_SIG_GAIN_3___M 0x03FF0000 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B0__PAPRD_SM_SIG_GAIN_3___S 16 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B0__PAPRD_SM_SIG_GAIN_2___M 0x000003FF +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B0__PAPRD_SM_SIG_GAIN_2___S 0 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B0___M 0x03FF03FF +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B0___S 0 + +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B1 (0x0049806C) +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B1___POR 0x00000000 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B1__PAPRD_SM_SIG_GAIN_3___POR 0x000 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B1__PAPRD_SM_SIG_GAIN_2___POR 0x000 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B1__PAPRD_SM_SIG_GAIN_3___M 0x03FF0000 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B1__PAPRD_SM_SIG_GAIN_3___S 16 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B1__PAPRD_SM_SIG_GAIN_2___M 0x000003FF +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B1__PAPRD_SM_SIG_GAIN_2___S 0 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B1___M 0x03FF03FF +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_0_U_B1___S 0 + +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B0 (0x00490070) +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B0___POR 0x00000000 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B0__PAPRD_SM_SIG_GAIN_5___POR 0x000 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B0__PAPRD_SM_SIG_GAIN_4___POR 0x000 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B0__PAPRD_SM_SIG_GAIN_5___M 0x03FF0000 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B0__PAPRD_SM_SIG_GAIN_5___S 16 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B0__PAPRD_SM_SIG_GAIN_4___M 0x000003FF +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B0__PAPRD_SM_SIG_GAIN_4___S 0 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B0___M 0x03FF03FF +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B0___S 0 + +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B1 (0x00498070) +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B1___POR 0x00000000 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B1__PAPRD_SM_SIG_GAIN_5___POR 0x000 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B1__PAPRD_SM_SIG_GAIN_4___POR 0x000 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B1__PAPRD_SM_SIG_GAIN_5___M 0x03FF0000 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B1__PAPRD_SM_SIG_GAIN_5___S 16 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B1__PAPRD_SM_SIG_GAIN_4___M 0x000003FF +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B1__PAPRD_SM_SIG_GAIN_4___S 0 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B1___M 0x03FF03FF +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_L_B1___S 0 + +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B0 (0x00490074) +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B0___POR 0x00000000 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B0__PAPRD_SM_SIG_GAIN_7___POR 0x000 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B0__PAPRD_SM_SIG_GAIN_6___POR 0x000 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B0__PAPRD_SM_SIG_GAIN_7___M 0x03FF0000 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B0__PAPRD_SM_SIG_GAIN_7___S 16 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B0__PAPRD_SM_SIG_GAIN_6___M 0x000003FF +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B0__PAPRD_SM_SIG_GAIN_6___S 0 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B0___M 0x03FF03FF +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B0___S 0 + +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B1 (0x00498074) +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B1___POR 0x00000000 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B1__PAPRD_SM_SIG_GAIN_7___POR 0x000 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B1__PAPRD_SM_SIG_GAIN_6___POR 0x000 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B1__PAPRD_SM_SIG_GAIN_7___M 0x03FF0000 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B1__PAPRD_SM_SIG_GAIN_7___S 16 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B1__PAPRD_SM_SIG_GAIN_6___M 0x000003FF +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B1__PAPRD_SM_SIG_GAIN_6___S 0 +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B1___M 0x03FF03FF +#define PHYA_PHYRF_PAPRD_SM_SIG_GAIN_TBL_1_U_B1___S 0 + +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B0 (0x00490078) +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B0___POR 0x00000000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B0__TX_PREEMP_COEF_TBL_1___POR 0x000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B0__TX_PREEMP_COEF_TBL_0___POR 0x000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B0__TX_PREEMP_COEF_TBL_1___M 0x0FFF0000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B0__TX_PREEMP_COEF_TBL_1___S 16 +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B0__TX_PREEMP_COEF_TBL_0___M 0x00000FFF +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B0__TX_PREEMP_COEF_TBL_0___S 0 +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B0___M 0x0FFF0FFF +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B0___S 0 + +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B1 (0x00498078) +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B1___POR 0x00000000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B1__TX_PREEMP_COEF_TBL_1___POR 0x000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B1__TX_PREEMP_COEF_TBL_0___POR 0x000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B1__TX_PREEMP_COEF_TBL_1___M 0x0FFF0000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B1__TX_PREEMP_COEF_TBL_1___S 16 +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B1__TX_PREEMP_COEF_TBL_0___M 0x00000FFF +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B1__TX_PREEMP_COEF_TBL_0___S 0 +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B1___M 0x0FFF0FFF +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_L_B1___S 0 + +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B0 (0x0049007C) +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B0___POR 0x00000000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B0__TX_PREEMP_COEF_TBL_3___POR 0x000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B0__TX_PREEMP_COEF_TBL_2___POR 0x000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B0__TX_PREEMP_COEF_TBL_3___M 0x0FFF0000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B0__TX_PREEMP_COEF_TBL_3___S 16 +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B0__TX_PREEMP_COEF_TBL_2___M 0x00000FFF +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B0__TX_PREEMP_COEF_TBL_2___S 0 +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B0___M 0x0FFF0FFF +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B0___S 0 + +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B1 (0x0049807C) +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B1___POR 0x00000000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B1__TX_PREEMP_COEF_TBL_3___POR 0x000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B1__TX_PREEMP_COEF_TBL_2___POR 0x000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B1__TX_PREEMP_COEF_TBL_3___M 0x0FFF0000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B1__TX_PREEMP_COEF_TBL_3___S 16 +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B1__TX_PREEMP_COEF_TBL_2___M 0x00000FFF +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B1__TX_PREEMP_COEF_TBL_2___S 0 +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B1___M 0x0FFF0FFF +#define PHYA_PHYRF_PREEMP_COEF_TBL_0_U_B1___S 0 + +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B0 (0x00490080) +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B0___POR 0x00000000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B0__TX_PREEMP_COEF_TBL_5___POR 0x000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B0__TX_PREEMP_COEF_TBL_4___POR 0x000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B0__TX_PREEMP_COEF_TBL_5___M 0x0FFF0000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B0__TX_PREEMP_COEF_TBL_5___S 16 +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B0__TX_PREEMP_COEF_TBL_4___M 0x00000FFF +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B0__TX_PREEMP_COEF_TBL_4___S 0 +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B0___M 0x0FFF0FFF +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B0___S 0 + +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B1 (0x00498080) +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B1___POR 0x00000000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B1__TX_PREEMP_COEF_TBL_5___POR 0x000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B1__TX_PREEMP_COEF_TBL_4___POR 0x000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B1__TX_PREEMP_COEF_TBL_5___M 0x0FFF0000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B1__TX_PREEMP_COEF_TBL_5___S 16 +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B1__TX_PREEMP_COEF_TBL_4___M 0x00000FFF +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B1__TX_PREEMP_COEF_TBL_4___S 0 +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B1___M 0x0FFF0FFF +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_L_B1___S 0 + +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B0 (0x00490084) +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B0___POR 0x00000000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B0__TX_PREEMP_COEF_TBL_7___POR 0x000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B0__TX_PREEMP_COEF_TBL_6___POR 0x000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B0__TX_PREEMP_COEF_TBL_7___M 0x0FFF0000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B0__TX_PREEMP_COEF_TBL_7___S 16 +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B0__TX_PREEMP_COEF_TBL_6___M 0x00000FFF +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B0__TX_PREEMP_COEF_TBL_6___S 0 +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B0___M 0x0FFF0FFF +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B0___S 0 + +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B1 (0x00498084) +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B1___POR 0x00000000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B1__TX_PREEMP_COEF_TBL_7___POR 0x000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B1__TX_PREEMP_COEF_TBL_6___POR 0x000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B1__TX_PREEMP_COEF_TBL_7___M 0x0FFF0000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B1__TX_PREEMP_COEF_TBL_7___S 16 +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B1__TX_PREEMP_COEF_TBL_6___M 0x00000FFF +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B1__TX_PREEMP_COEF_TBL_6___S 0 +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B1___M 0x0FFF0FFF +#define PHYA_PHYRF_PREEMP_COEF_TBL_1_U_B1___S 0 + +#define PHYA_PHYRF_PREEMP_COEF_TBL_2_L_B0 (0x00490088) +#define PHYA_PHYRF_PREEMP_COEF_TBL_2_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PREEMP_COEF_TBL_2_L_B0___POR 0x00000000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_2_L_B0__TX_PREEMP_COEF_TBL_8___POR 0x000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_2_L_B0__TX_PREEMP_COEF_TBL_8___M 0x00000FFF +#define PHYA_PHYRF_PREEMP_COEF_TBL_2_L_B0__TX_PREEMP_COEF_TBL_8___S 0 +#define PHYA_PHYRF_PREEMP_COEF_TBL_2_L_B0___M 0x00000FFF +#define PHYA_PHYRF_PREEMP_COEF_TBL_2_L_B0___S 0 + +#define PHYA_PHYRF_PREEMP_COEF_TBL_2_L_B1 (0x00498088) +#define PHYA_PHYRF_PREEMP_COEF_TBL_2_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_PREEMP_COEF_TBL_2_L_B1___POR 0x00000000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_2_L_B1__TX_PREEMP_COEF_TBL_8___POR 0x000 +#define PHYA_PHYRF_PREEMP_COEF_TBL_2_L_B1__TX_PREEMP_COEF_TBL_8___M 0x00000FFF +#define PHYA_PHYRF_PREEMP_COEF_TBL_2_L_B1__TX_PREEMP_COEF_TBL_8___S 0 +#define PHYA_PHYRF_PREEMP_COEF_TBL_2_L_B1___M 0x00000FFF +#define PHYA_PHYRF_PREEMP_COEF_TBL_2_L_B1___S 0 + +#define PHYA_PHYRF_PDC_NCHAIN_0_L_B0 (0x00490090) +#define PHYA_PHYRF_PDC_NCHAIN_0_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PDC_NCHAIN_0_L_B0___POR 0x0000ABCD +#define PHYA_PHYRF_PDC_NCHAIN_0_L_B0__PDC_COEFA1_S0___POR 0x0ABCD +#define PHYA_PHYRF_PDC_NCHAIN_0_L_B0__PDC_COEFA1_S0___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_0_L_B0__PDC_COEFA1_S0___S 0 +#define PHYA_PHYRF_PDC_NCHAIN_0_L_B0___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_0_L_B0___S 0 + +#define PHYA_PHYRF_PDC_NCHAIN_0_L_B1 (0x00498090) +#define PHYA_PHYRF_PDC_NCHAIN_0_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_PDC_NCHAIN_0_L_B1___POR 0x0000ABCD +#define PHYA_PHYRF_PDC_NCHAIN_0_L_B1__PDC_COEFA1_S0___POR 0x0ABCD +#define PHYA_PHYRF_PDC_NCHAIN_0_L_B1__PDC_COEFA1_S0___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_0_L_B1__PDC_COEFA1_S0___S 0 +#define PHYA_PHYRF_PDC_NCHAIN_0_L_B1___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_0_L_B1___S 0 + +#define PHYA_PHYRF_PDC_NCHAIN_0_U_B0 (0x00490094) +#define PHYA_PHYRF_PDC_NCHAIN_0_U_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PDC_NCHAIN_0_U_B0___POR 0x00000000 +#define PHYA_PHYRF_PDC_NCHAIN_0_U_B0__PDC_COEFA1_S1___POR 0x00000 +#define PHYA_PHYRF_PDC_NCHAIN_0_U_B0__PDC_COEFA1_S1___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_0_U_B0__PDC_COEFA1_S1___S 0 +#define PHYA_PHYRF_PDC_NCHAIN_0_U_B0___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_0_U_B0___S 0 + +#define PHYA_PHYRF_PDC_NCHAIN_0_U_B1 (0x00498094) +#define PHYA_PHYRF_PDC_NCHAIN_0_U_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_PDC_NCHAIN_0_U_B1___POR 0x00000000 +#define PHYA_PHYRF_PDC_NCHAIN_0_U_B1__PDC_COEFA1_S1___POR 0x00000 +#define PHYA_PHYRF_PDC_NCHAIN_0_U_B1__PDC_COEFA1_S1___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_0_U_B1__PDC_COEFA1_S1___S 0 +#define PHYA_PHYRF_PDC_NCHAIN_0_U_B1___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_0_U_B1___S 0 + +#define PHYA_PHYRF_PDC_NCHAIN_1_L_B0 (0x00490098) +#define PHYA_PHYRF_PDC_NCHAIN_1_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PDC_NCHAIN_1_L_B0___POR 0x00000000 +#define PHYA_PHYRF_PDC_NCHAIN_1_L_B0__PDC_COEFA1_S2___POR 0x00000 +#define PHYA_PHYRF_PDC_NCHAIN_1_L_B0__PDC_COEFA1_S2___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_1_L_B0__PDC_COEFA1_S2___S 0 +#define PHYA_PHYRF_PDC_NCHAIN_1_L_B0___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_1_L_B0___S 0 + +#define PHYA_PHYRF_PDC_NCHAIN_1_L_B1 (0x00498098) +#define PHYA_PHYRF_PDC_NCHAIN_1_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_PDC_NCHAIN_1_L_B1___POR 0x00000000 +#define PHYA_PHYRF_PDC_NCHAIN_1_L_B1__PDC_COEFA1_S2___POR 0x00000 +#define PHYA_PHYRF_PDC_NCHAIN_1_L_B1__PDC_COEFA1_S2___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_1_L_B1__PDC_COEFA1_S2___S 0 +#define PHYA_PHYRF_PDC_NCHAIN_1_L_B1___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_1_L_B1___S 0 + +#define PHYA_PHYRF_PDC_NCHAIN_1_U_B0 (0x0049009C) +#define PHYA_PHYRF_PDC_NCHAIN_1_U_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PDC_NCHAIN_1_U_B0___POR 0x0000AB73 +#define PHYA_PHYRF_PDC_NCHAIN_1_U_B0__PDC_COEFB1_S0___POR 0x0AB73 +#define PHYA_PHYRF_PDC_NCHAIN_1_U_B0__PDC_COEFB1_S0___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_1_U_B0__PDC_COEFB1_S0___S 0 +#define PHYA_PHYRF_PDC_NCHAIN_1_U_B0___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_1_U_B0___S 0 + +#define PHYA_PHYRF_PDC_NCHAIN_1_U_B1 (0x0049809C) +#define PHYA_PHYRF_PDC_NCHAIN_1_U_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_PDC_NCHAIN_1_U_B1___POR 0x0000AB73 +#define PHYA_PHYRF_PDC_NCHAIN_1_U_B1__PDC_COEFB1_S0___POR 0x0AB73 +#define PHYA_PHYRF_PDC_NCHAIN_1_U_B1__PDC_COEFB1_S0___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_1_U_B1__PDC_COEFB1_S0___S 0 +#define PHYA_PHYRF_PDC_NCHAIN_1_U_B1___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_1_U_B1___S 0 + +#define PHYA_PHYRF_PDC_NCHAIN_2_L_B0 (0x004900A0) +#define PHYA_PHYRF_PDC_NCHAIN_2_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PDC_NCHAIN_2_L_B0___POR 0x00000000 +#define PHYA_PHYRF_PDC_NCHAIN_2_L_B0__PDC_COEFB1_S1___POR 0x00000 +#define PHYA_PHYRF_PDC_NCHAIN_2_L_B0__PDC_COEFB1_S1___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_2_L_B0__PDC_COEFB1_S1___S 0 +#define PHYA_PHYRF_PDC_NCHAIN_2_L_B0___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_2_L_B0___S 0 + +#define PHYA_PHYRF_PDC_NCHAIN_2_L_B1 (0x004980A0) +#define PHYA_PHYRF_PDC_NCHAIN_2_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_PDC_NCHAIN_2_L_B1___POR 0x00000000 +#define PHYA_PHYRF_PDC_NCHAIN_2_L_B1__PDC_COEFB1_S1___POR 0x00000 +#define PHYA_PHYRF_PDC_NCHAIN_2_L_B1__PDC_COEFB1_S1___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_2_L_B1__PDC_COEFB1_S1___S 0 +#define PHYA_PHYRF_PDC_NCHAIN_2_L_B1___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_2_L_B1___S 0 + +#define PHYA_PHYRF_PDC_NCHAIN_2_U_B0 (0x004900A4) +#define PHYA_PHYRF_PDC_NCHAIN_2_U_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PDC_NCHAIN_2_U_B0___POR 0x00000000 +#define PHYA_PHYRF_PDC_NCHAIN_2_U_B0__PDC_COEFB1_S2___POR 0x00000 +#define PHYA_PHYRF_PDC_NCHAIN_2_U_B0__PDC_COEFB1_S2___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_2_U_B0__PDC_COEFB1_S2___S 0 +#define PHYA_PHYRF_PDC_NCHAIN_2_U_B0___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_2_U_B0___S 0 + +#define PHYA_PHYRF_PDC_NCHAIN_2_U_B1 (0x004980A4) +#define PHYA_PHYRF_PDC_NCHAIN_2_U_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_PDC_NCHAIN_2_U_B1___POR 0x00000000 +#define PHYA_PHYRF_PDC_NCHAIN_2_U_B1__PDC_COEFB1_S2___POR 0x00000 +#define PHYA_PHYRF_PDC_NCHAIN_2_U_B1__PDC_COEFB1_S2___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_2_U_B1__PDC_COEFB1_S2___S 0 +#define PHYA_PHYRF_PDC_NCHAIN_2_U_B1___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_2_U_B1___S 0 + +#define PHYA_PHYRF_PDC_NCHAIN_3_L_B0 (0x004900A8) +#define PHYA_PHYRF_PDC_NCHAIN_3_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PDC_NCHAIN_3_L_B0___POR 0x0000AB73 +#define PHYA_PHYRF_PDC_NCHAIN_3_L_B0__PDC_COEFB2_S0___POR 0x0AB73 +#define PHYA_PHYRF_PDC_NCHAIN_3_L_B0__PDC_COEFB2_S0___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_3_L_B0__PDC_COEFB2_S0___S 0 +#define PHYA_PHYRF_PDC_NCHAIN_3_L_B0___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_3_L_B0___S 0 + +#define PHYA_PHYRF_PDC_NCHAIN_3_L_B1 (0x004980A8) +#define PHYA_PHYRF_PDC_NCHAIN_3_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_PDC_NCHAIN_3_L_B1___POR 0x0000AB73 +#define PHYA_PHYRF_PDC_NCHAIN_3_L_B1__PDC_COEFB2_S0___POR 0x0AB73 +#define PHYA_PHYRF_PDC_NCHAIN_3_L_B1__PDC_COEFB2_S0___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_3_L_B1__PDC_COEFB2_S0___S 0 +#define PHYA_PHYRF_PDC_NCHAIN_3_L_B1___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_3_L_B1___S 0 + +#define PHYA_PHYRF_PDC_NCHAIN_3_U_B0 (0x004900AC) +#define PHYA_PHYRF_PDC_NCHAIN_3_U_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PDC_NCHAIN_3_U_B0___POR 0x00000000 +#define PHYA_PHYRF_PDC_NCHAIN_3_U_B0__PDC_COEFB2_S1___POR 0x00000 +#define PHYA_PHYRF_PDC_NCHAIN_3_U_B0__PDC_COEFB2_S1___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_3_U_B0__PDC_COEFB2_S1___S 0 +#define PHYA_PHYRF_PDC_NCHAIN_3_U_B0___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_3_U_B0___S 0 + +#define PHYA_PHYRF_PDC_NCHAIN_3_U_B1 (0x004980AC) +#define PHYA_PHYRF_PDC_NCHAIN_3_U_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_PDC_NCHAIN_3_U_B1___POR 0x00000000 +#define PHYA_PHYRF_PDC_NCHAIN_3_U_B1__PDC_COEFB2_S1___POR 0x00000 +#define PHYA_PHYRF_PDC_NCHAIN_3_U_B1__PDC_COEFB2_S1___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_3_U_B1__PDC_COEFB2_S1___S 0 +#define PHYA_PHYRF_PDC_NCHAIN_3_U_B1___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_3_U_B1___S 0 + +#define PHYA_PHYRF_PDC_NCHAIN_4_L_B0 (0x004900B0) +#define PHYA_PHYRF_PDC_NCHAIN_4_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PDC_NCHAIN_4_L_B0___POR 0x00000000 +#define PHYA_PHYRF_PDC_NCHAIN_4_L_B0__PDC_COEFB2_S2___POR 0x00000 +#define PHYA_PHYRF_PDC_NCHAIN_4_L_B0__PDC_COEFB2_S2___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_4_L_B0__PDC_COEFB2_S2___S 0 +#define PHYA_PHYRF_PDC_NCHAIN_4_L_B0___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_4_L_B0___S 0 + +#define PHYA_PHYRF_PDC_NCHAIN_4_L_B1 (0x004980B0) +#define PHYA_PHYRF_PDC_NCHAIN_4_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_PDC_NCHAIN_4_L_B1___POR 0x00000000 +#define PHYA_PHYRF_PDC_NCHAIN_4_L_B1__PDC_COEFB2_S2___POR 0x00000 +#define PHYA_PHYRF_PDC_NCHAIN_4_L_B1__PDC_COEFB2_S2___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_4_L_B1__PDC_COEFB2_S2___S 0 +#define PHYA_PHYRF_PDC_NCHAIN_4_L_B1___M 0x0003FFFF +#define PHYA_PHYRF_PDC_NCHAIN_4_L_B1___S 0 + +#define PHYA_PHYRF_PDC_NCHAIN_4_U_B0 (0x004900B4) +#define PHYA_PHYRF_PDC_NCHAIN_4_U_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PDC_NCHAIN_4_U_B0___POR 0x00000000 +#define PHYA_PHYRF_PDC_NCHAIN_4_U_B0__PDC_STEP_P1___POR 0x00000000 +#define PHYA_PHYRF_PDC_NCHAIN_4_U_B0__PDC_STEP_P1___M 0xFFFFFFFF +#define PHYA_PHYRF_PDC_NCHAIN_4_U_B0__PDC_STEP_P1___S 0 +#define PHYA_PHYRF_PDC_NCHAIN_4_U_B0___M 0xFFFFFFFF +#define PHYA_PHYRF_PDC_NCHAIN_4_U_B0___S 0 + +#define PHYA_PHYRF_PDC_NCHAIN_4_U_B1 (0x004980B4) +#define PHYA_PHYRF_PDC_NCHAIN_4_U_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_PDC_NCHAIN_4_U_B1___POR 0x00000000 +#define PHYA_PHYRF_PDC_NCHAIN_4_U_B1__PDC_STEP_P1___POR 0x00000000 +#define PHYA_PHYRF_PDC_NCHAIN_4_U_B1__PDC_STEP_P1___M 0xFFFFFFFF +#define PHYA_PHYRF_PDC_NCHAIN_4_U_B1__PDC_STEP_P1___S 0 +#define PHYA_PHYRF_PDC_NCHAIN_4_U_B1___M 0xFFFFFFFF +#define PHYA_PHYRF_PDC_NCHAIN_4_U_B1___S 0 + +#define PHYA_PHYRF_PDC_NCHAIN_5_L_B0 (0x004900B8) +#define PHYA_PHYRF_PDC_NCHAIN_5_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PDC_NCHAIN_5_L_B0___POR 0x00000000 +#define PHYA_PHYRF_PDC_NCHAIN_5_L_B0__PDC_STEP_P2___POR 0x00000000 +#define PHYA_PHYRF_PDC_NCHAIN_5_L_B0__PDC_STEP_P2___M 0xFFFFFFFF +#define PHYA_PHYRF_PDC_NCHAIN_5_L_B0__PDC_STEP_P2___S 0 +#define PHYA_PHYRF_PDC_NCHAIN_5_L_B0___M 0xFFFFFFFF +#define PHYA_PHYRF_PDC_NCHAIN_5_L_B0___S 0 + +#define PHYA_PHYRF_PDC_NCHAIN_5_L_B1 (0x004980B8) +#define PHYA_PHYRF_PDC_NCHAIN_5_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_PDC_NCHAIN_5_L_B1___POR 0x00000000 +#define PHYA_PHYRF_PDC_NCHAIN_5_L_B1__PDC_STEP_P2___POR 0x00000000 +#define PHYA_PHYRF_PDC_NCHAIN_5_L_B1__PDC_STEP_P2___M 0xFFFFFFFF +#define PHYA_PHYRF_PDC_NCHAIN_5_L_B1__PDC_STEP_P2___S 0 +#define PHYA_PHYRF_PDC_NCHAIN_5_L_B1___M 0xFFFFFFFF +#define PHYA_PHYRF_PDC_NCHAIN_5_L_B1___S 0 + +#define PHYA_PHYRF_PDC_NCHAIN_5_U_B0 (0x004900BC) +#define PHYA_PHYRF_PDC_NCHAIN_5_U_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PDC_NCHAIN_5_U_B0___POR 0x00100000 +#define PHYA_PHYRF_PDC_NCHAIN_5_U_B0__PDC_N_STEP_P1___POR 0x10 +#define PHYA_PHYRF_PDC_NCHAIN_5_U_B0__PDC_N_P2_MAX___POR 0x00 +#define PHYA_PHYRF_PDC_NCHAIN_5_U_B0__PDC_N_P1_MAX___POR 0x00 +#define PHYA_PHYRF_PDC_NCHAIN_5_U_B0__PDC_N_STEP_P1___M 0x00FF0000 +#define PHYA_PHYRF_PDC_NCHAIN_5_U_B0__PDC_N_STEP_P1___S 16 +#define PHYA_PHYRF_PDC_NCHAIN_5_U_B0__PDC_N_P2_MAX___M 0x0000FF00 +#define PHYA_PHYRF_PDC_NCHAIN_5_U_B0__PDC_N_P2_MAX___S 8 +#define PHYA_PHYRF_PDC_NCHAIN_5_U_B0__PDC_N_P1_MAX___M 0x000000FF +#define PHYA_PHYRF_PDC_NCHAIN_5_U_B0__PDC_N_P1_MAX___S 0 +#define PHYA_PHYRF_PDC_NCHAIN_5_U_B0___M 0x00FFFFFF +#define PHYA_PHYRF_PDC_NCHAIN_5_U_B0___S 0 + +#define PHYA_PHYRF_PDC_NCHAIN_5_U_B1 (0x004980BC) +#define PHYA_PHYRF_PDC_NCHAIN_5_U_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_PDC_NCHAIN_5_U_B1___POR 0x00100000 +#define PHYA_PHYRF_PDC_NCHAIN_5_U_B1__PDC_N_STEP_P1___POR 0x10 +#define PHYA_PHYRF_PDC_NCHAIN_5_U_B1__PDC_N_P2_MAX___POR 0x00 +#define PHYA_PHYRF_PDC_NCHAIN_5_U_B1__PDC_N_P1_MAX___POR 0x00 +#define PHYA_PHYRF_PDC_NCHAIN_5_U_B1__PDC_N_STEP_P1___M 0x00FF0000 +#define PHYA_PHYRF_PDC_NCHAIN_5_U_B1__PDC_N_STEP_P1___S 16 +#define PHYA_PHYRF_PDC_NCHAIN_5_U_B1__PDC_N_P2_MAX___M 0x0000FF00 +#define PHYA_PHYRF_PDC_NCHAIN_5_U_B1__PDC_N_P2_MAX___S 8 +#define PHYA_PHYRF_PDC_NCHAIN_5_U_B1__PDC_N_P1_MAX___M 0x000000FF +#define PHYA_PHYRF_PDC_NCHAIN_5_U_B1__PDC_N_P1_MAX___S 0 +#define PHYA_PHYRF_PDC_NCHAIN_5_U_B1___M 0x00FFFFFF +#define PHYA_PHYRF_PDC_NCHAIN_5_U_B1___S 0 + +#define PHYA_PHYRF_RXCORR_COEFF_L_B0 (0x004900C0) +#define PHYA_PHYRF_RXCORR_COEFF_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXCORR_COEFF_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RXCORR_COEFF_L_B0__RXCORR_ADC_GAIN_CEOFF_Q___POR 0x000 +#define PHYA_PHYRF_RXCORR_COEFF_L_B0__RXCORR_ADC_GAIN_CEOFF_I___POR 0x000 +#define PHYA_PHYRF_RXCORR_COEFF_L_B0__RXCORR_ADC_GAIN_CEOFF_Q___M 0x01FF0000 +#define PHYA_PHYRF_RXCORR_COEFF_L_B0__RXCORR_ADC_GAIN_CEOFF_Q___S 16 +#define PHYA_PHYRF_RXCORR_COEFF_L_B0__RXCORR_ADC_GAIN_CEOFF_I___M 0x000001FF +#define PHYA_PHYRF_RXCORR_COEFF_L_B0__RXCORR_ADC_GAIN_CEOFF_I___S 0 +#define PHYA_PHYRF_RXCORR_COEFF_L_B0___M 0x01FF01FF +#define PHYA_PHYRF_RXCORR_COEFF_L_B0___S 0 + +#define PHYA_PHYRF_RXCORR_COEFF_L_B1 (0x004980C0) +#define PHYA_PHYRF_RXCORR_COEFF_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXCORR_COEFF_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RXCORR_COEFF_L_B1__RXCORR_ADC_GAIN_CEOFF_Q___POR 0x000 +#define PHYA_PHYRF_RXCORR_COEFF_L_B1__RXCORR_ADC_GAIN_CEOFF_I___POR 0x000 +#define PHYA_PHYRF_RXCORR_COEFF_L_B1__RXCORR_ADC_GAIN_CEOFF_Q___M 0x01FF0000 +#define PHYA_PHYRF_RXCORR_COEFF_L_B1__RXCORR_ADC_GAIN_CEOFF_Q___S 16 +#define PHYA_PHYRF_RXCORR_COEFF_L_B1__RXCORR_ADC_GAIN_CEOFF_I___M 0x000001FF +#define PHYA_PHYRF_RXCORR_COEFF_L_B1__RXCORR_ADC_GAIN_CEOFF_I___S 0 +#define PHYA_PHYRF_RXCORR_COEFF_L_B1___M 0x01FF01FF +#define PHYA_PHYRF_RXCORR_COEFF_L_B1___S 0 + +#define PHYA_PHYRF_RXCORR_COEFF_U_B0 (0x004900C4) +#define PHYA_PHYRF_RXCORR_COEFF_U_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXCORR_COEFF_U_B0___POR 0x00000000 +#define PHYA_PHYRF_RXCORR_COEFF_U_B0__RXCORR_ADC_DC_CEOFF_Q___POR 0x000 +#define PHYA_PHYRF_RXCORR_COEFF_U_B0__RXCORR_ADC_DC_CEOFF_I___POR 0x000 +#define PHYA_PHYRF_RXCORR_COEFF_U_B0__RXCORR_ADC_DC_CEOFF_Q___M 0x01FF0000 +#define PHYA_PHYRF_RXCORR_COEFF_U_B0__RXCORR_ADC_DC_CEOFF_Q___S 16 +#define PHYA_PHYRF_RXCORR_COEFF_U_B0__RXCORR_ADC_DC_CEOFF_I___M 0x000001FF +#define PHYA_PHYRF_RXCORR_COEFF_U_B0__RXCORR_ADC_DC_CEOFF_I___S 0 +#define PHYA_PHYRF_RXCORR_COEFF_U_B0___M 0x01FF01FF +#define PHYA_PHYRF_RXCORR_COEFF_U_B0___S 0 + +#define PHYA_PHYRF_RXCORR_COEFF_U_B1 (0x004980C4) +#define PHYA_PHYRF_RXCORR_COEFF_U_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXCORR_COEFF_U_B1___POR 0x00000000 +#define PHYA_PHYRF_RXCORR_COEFF_U_B1__RXCORR_ADC_DC_CEOFF_Q___POR 0x000 +#define PHYA_PHYRF_RXCORR_COEFF_U_B1__RXCORR_ADC_DC_CEOFF_I___POR 0x000 +#define PHYA_PHYRF_RXCORR_COEFF_U_B1__RXCORR_ADC_DC_CEOFF_Q___M 0x01FF0000 +#define PHYA_PHYRF_RXCORR_COEFF_U_B1__RXCORR_ADC_DC_CEOFF_Q___S 16 +#define PHYA_PHYRF_RXCORR_COEFF_U_B1__RXCORR_ADC_DC_CEOFF_I___M 0x000001FF +#define PHYA_PHYRF_RXCORR_COEFF_U_B1__RXCORR_ADC_DC_CEOFF_I___S 0 +#define PHYA_PHYRF_RXCORR_COEFF_U_B1___M 0x01FF01FF +#define PHYA_PHYRF_RXCORR_COEFF_U_B1___S 0 + +#define PHYA_PHYRF_RXCORR_FCS_COEFF_L_B0 (0x004900C8) +#define PHYA_PHYRF_RXCORR_FCS_COEFF_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXCORR_FCS_COEFF_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RXCORR_FCS_COEFF_L_B0__RXCORR_FCS_ADC_GAIN_CEOFF_Q___POR 0x000 +#define PHYA_PHYRF_RXCORR_FCS_COEFF_L_B0__RXCORR_FCS_ADC_GAIN_CEOFF_I___POR 0x000 +#define PHYA_PHYRF_RXCORR_FCS_COEFF_L_B0__RXCORR_FCS_ADC_GAIN_CEOFF_Q___M 0x01FF0000 +#define PHYA_PHYRF_RXCORR_FCS_COEFF_L_B0__RXCORR_FCS_ADC_GAIN_CEOFF_Q___S 16 +#define PHYA_PHYRF_RXCORR_FCS_COEFF_L_B0__RXCORR_FCS_ADC_GAIN_CEOFF_I___M 0x000001FF +#define PHYA_PHYRF_RXCORR_FCS_COEFF_L_B0__RXCORR_FCS_ADC_GAIN_CEOFF_I___S 0 +#define PHYA_PHYRF_RXCORR_FCS_COEFF_L_B0___M 0x01FF01FF +#define PHYA_PHYRF_RXCORR_FCS_COEFF_L_B0___S 0 + +#define PHYA_PHYRF_RXCORR_FCS_COEFF_L_B1 (0x004980C8) +#define PHYA_PHYRF_RXCORR_FCS_COEFF_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXCORR_FCS_COEFF_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RXCORR_FCS_COEFF_L_B1__RXCORR_FCS_ADC_GAIN_CEOFF_Q___POR 0x000 +#define PHYA_PHYRF_RXCORR_FCS_COEFF_L_B1__RXCORR_FCS_ADC_GAIN_CEOFF_I___POR 0x000 +#define PHYA_PHYRF_RXCORR_FCS_COEFF_L_B1__RXCORR_FCS_ADC_GAIN_CEOFF_Q___M 0x01FF0000 +#define PHYA_PHYRF_RXCORR_FCS_COEFF_L_B1__RXCORR_FCS_ADC_GAIN_CEOFF_Q___S 16 +#define PHYA_PHYRF_RXCORR_FCS_COEFF_L_B1__RXCORR_FCS_ADC_GAIN_CEOFF_I___M 0x000001FF +#define PHYA_PHYRF_RXCORR_FCS_COEFF_L_B1__RXCORR_FCS_ADC_GAIN_CEOFF_I___S 0 +#define PHYA_PHYRF_RXCORR_FCS_COEFF_L_B1___M 0x01FF01FF +#define PHYA_PHYRF_RXCORR_FCS_COEFF_L_B1___S 0 + +#define PHYA_PHYRF_RXCORR_FCS_COEFF_U_B0 (0x004900CC) +#define PHYA_PHYRF_RXCORR_FCS_COEFF_U_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXCORR_FCS_COEFF_U_B0___POR 0x00000000 +#define PHYA_PHYRF_RXCORR_FCS_COEFF_U_B0__RXCORR_FCS_ADC_DC_CEOFF_Q___POR 0x000 +#define PHYA_PHYRF_RXCORR_FCS_COEFF_U_B0__RXCORR_FCS_ADC_DC_CEOFF_I___POR 0x000 +#define PHYA_PHYRF_RXCORR_FCS_COEFF_U_B0__RXCORR_FCS_ADC_DC_CEOFF_Q___M 0x01FF0000 +#define PHYA_PHYRF_RXCORR_FCS_COEFF_U_B0__RXCORR_FCS_ADC_DC_CEOFF_Q___S 16 +#define PHYA_PHYRF_RXCORR_FCS_COEFF_U_B0__RXCORR_FCS_ADC_DC_CEOFF_I___M 0x000001FF +#define PHYA_PHYRF_RXCORR_FCS_COEFF_U_B0__RXCORR_FCS_ADC_DC_CEOFF_I___S 0 +#define PHYA_PHYRF_RXCORR_FCS_COEFF_U_B0___M 0x01FF01FF +#define PHYA_PHYRF_RXCORR_FCS_COEFF_U_B0___S 0 + +#define PHYA_PHYRF_RXCORR_FCS_COEFF_U_B1 (0x004980CC) +#define PHYA_PHYRF_RXCORR_FCS_COEFF_U_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXCORR_FCS_COEFF_U_B1___POR 0x00000000 +#define PHYA_PHYRF_RXCORR_FCS_COEFF_U_B1__RXCORR_FCS_ADC_DC_CEOFF_Q___POR 0x000 +#define PHYA_PHYRF_RXCORR_FCS_COEFF_U_B1__RXCORR_FCS_ADC_DC_CEOFF_I___POR 0x000 +#define PHYA_PHYRF_RXCORR_FCS_COEFF_U_B1__RXCORR_FCS_ADC_DC_CEOFF_Q___M 0x01FF0000 +#define PHYA_PHYRF_RXCORR_FCS_COEFF_U_B1__RXCORR_FCS_ADC_DC_CEOFF_Q___S 16 +#define PHYA_PHYRF_RXCORR_FCS_COEFF_U_B1__RXCORR_FCS_ADC_DC_CEOFF_I___M 0x000001FF +#define PHYA_PHYRF_RXCORR_FCS_COEFF_U_B1__RXCORR_FCS_ADC_DC_CEOFF_I___S 0 +#define PHYA_PHYRF_RXCORR_FCS_COEFF_U_B1___M 0x01FF01FF +#define PHYA_PHYRF_RXCORR_FCS_COEFF_U_B1___S 0 + +#define PHYA_PHYRF_RXCORR_FORCE_0_L_B0 (0x004900D0) +#define PHYA_PHYRF_RXCORR_FORCE_0_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXCORR_FORCE_0_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RXCORR_FORCE_0_L_B0__RXCORR_RXIQ_FORCE_MODE_SEL___POR 0x0 +#define PHYA_PHYRF_RXCORR_FORCE_0_L_B0__RXCORR_RXIQ_FORCE_INDEX___POR 0x0 +#define PHYA_PHYRF_RXCORR_FORCE_0_L_B0__RXCORR_RXIQ_FORCE_MODE___POR 0x0 +#define PHYA_PHYRF_RXCORR_FORCE_0_L_B0__RXCORR_RXIQ_FORCE_BYPASS___POR 0x0 +#define PHYA_PHYRF_RXCORR_FORCE_0_L_B0__RXCORR_RXIQ_FORCE_MODE_SEL___M 0x03000000 +#define PHYA_PHYRF_RXCORR_FORCE_0_L_B0__RXCORR_RXIQ_FORCE_MODE_SEL___S 24 +#define PHYA_PHYRF_RXCORR_FORCE_0_L_B0__RXCORR_RXIQ_FORCE_INDEX___M 0x000F0000 +#define PHYA_PHYRF_RXCORR_FORCE_0_L_B0__RXCORR_RXIQ_FORCE_INDEX___S 16 +#define PHYA_PHYRF_RXCORR_FORCE_0_L_B0__RXCORR_RXIQ_FORCE_MODE___M 0x00000100 +#define PHYA_PHYRF_RXCORR_FORCE_0_L_B0__RXCORR_RXIQ_FORCE_MODE___S 8 +#define PHYA_PHYRF_RXCORR_FORCE_0_L_B0__RXCORR_RXIQ_FORCE_BYPASS___M 0x00000001 +#define PHYA_PHYRF_RXCORR_FORCE_0_L_B0__RXCORR_RXIQ_FORCE_BYPASS___S 0 +#define PHYA_PHYRF_RXCORR_FORCE_0_L_B0___M 0x030F0101 +#define PHYA_PHYRF_RXCORR_FORCE_0_L_B0___S 0 + +#define PHYA_PHYRF_RXCORR_FORCE_0_L_B1 (0x004980D0) +#define PHYA_PHYRF_RXCORR_FORCE_0_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXCORR_FORCE_0_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RXCORR_FORCE_0_L_B1__RXCORR_RXIQ_FORCE_MODE_SEL___POR 0x0 +#define PHYA_PHYRF_RXCORR_FORCE_0_L_B1__RXCORR_RXIQ_FORCE_INDEX___POR 0x0 +#define PHYA_PHYRF_RXCORR_FORCE_0_L_B1__RXCORR_RXIQ_FORCE_MODE___POR 0x0 +#define PHYA_PHYRF_RXCORR_FORCE_0_L_B1__RXCORR_RXIQ_FORCE_BYPASS___POR 0x0 +#define PHYA_PHYRF_RXCORR_FORCE_0_L_B1__RXCORR_RXIQ_FORCE_MODE_SEL___M 0x03000000 +#define PHYA_PHYRF_RXCORR_FORCE_0_L_B1__RXCORR_RXIQ_FORCE_MODE_SEL___S 24 +#define PHYA_PHYRF_RXCORR_FORCE_0_L_B1__RXCORR_RXIQ_FORCE_INDEX___M 0x000F0000 +#define PHYA_PHYRF_RXCORR_FORCE_0_L_B1__RXCORR_RXIQ_FORCE_INDEX___S 16 +#define PHYA_PHYRF_RXCORR_FORCE_0_L_B1__RXCORR_RXIQ_FORCE_MODE___M 0x00000100 +#define PHYA_PHYRF_RXCORR_FORCE_0_L_B1__RXCORR_RXIQ_FORCE_MODE___S 8 +#define PHYA_PHYRF_RXCORR_FORCE_0_L_B1__RXCORR_RXIQ_FORCE_BYPASS___M 0x00000001 +#define PHYA_PHYRF_RXCORR_FORCE_0_L_B1__RXCORR_RXIQ_FORCE_BYPASS___S 0 +#define PHYA_PHYRF_RXCORR_FORCE_0_L_B1___M 0x030F0101 +#define PHYA_PHYRF_RXCORR_FORCE_0_L_B1___S 0 + +#define PHYA_PHYRF_RXCORR_FORCE_0_U_B0 (0x004900D4) +#define PHYA_PHYRF_RXCORR_FORCE_0_U_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXCORR_FORCE_0_U_B0___POR 0x00000000 +#define PHYA_PHYRF_RXCORR_FORCE_0_U_B0__RXCORR_RXDC_FORCE_MODE_DC_I___POR 0x00 +#define PHYA_PHYRF_RXCORR_FORCE_0_U_B0__RXCORR_RXDC_FORCE_MODE___POR 0x0 +#define PHYA_PHYRF_RXCORR_FORCE_0_U_B0__RXCORR_RXDC_FORCE_BYPASS___POR 0x0 +#define PHYA_PHYRF_RXCORR_FORCE_0_U_B0__RXCORR_RXIQ_FORCE_LOAD___POR 0x0 +#define PHYA_PHYRF_RXCORR_FORCE_0_U_B0__RXCORR_RXDC_FORCE_MODE_DC_I___M 0xFF000000 +#define PHYA_PHYRF_RXCORR_FORCE_0_U_B0__RXCORR_RXDC_FORCE_MODE_DC_I___S 24 +#define PHYA_PHYRF_RXCORR_FORCE_0_U_B0__RXCORR_RXDC_FORCE_MODE___M 0x00010000 +#define PHYA_PHYRF_RXCORR_FORCE_0_U_B0__RXCORR_RXDC_FORCE_MODE___S 16 +#define PHYA_PHYRF_RXCORR_FORCE_0_U_B0__RXCORR_RXDC_FORCE_BYPASS___M 0x00000100 +#define PHYA_PHYRF_RXCORR_FORCE_0_U_B0__RXCORR_RXDC_FORCE_BYPASS___S 8 +#define PHYA_PHYRF_RXCORR_FORCE_0_U_B0__RXCORR_RXIQ_FORCE_LOAD___M 0x00000001 +#define PHYA_PHYRF_RXCORR_FORCE_0_U_B0__RXCORR_RXIQ_FORCE_LOAD___S 0 +#define PHYA_PHYRF_RXCORR_FORCE_0_U_B0___M 0xFF010101 +#define PHYA_PHYRF_RXCORR_FORCE_0_U_B0___S 0 + +#define PHYA_PHYRF_RXCORR_FORCE_0_U_B1 (0x004980D4) +#define PHYA_PHYRF_RXCORR_FORCE_0_U_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXCORR_FORCE_0_U_B1___POR 0x00000000 +#define PHYA_PHYRF_RXCORR_FORCE_0_U_B1__RXCORR_RXDC_FORCE_MODE_DC_I___POR 0x00 +#define PHYA_PHYRF_RXCORR_FORCE_0_U_B1__RXCORR_RXDC_FORCE_MODE___POR 0x0 +#define PHYA_PHYRF_RXCORR_FORCE_0_U_B1__RXCORR_RXDC_FORCE_BYPASS___POR 0x0 +#define PHYA_PHYRF_RXCORR_FORCE_0_U_B1__RXCORR_RXIQ_FORCE_LOAD___POR 0x0 +#define PHYA_PHYRF_RXCORR_FORCE_0_U_B1__RXCORR_RXDC_FORCE_MODE_DC_I___M 0xFF000000 +#define PHYA_PHYRF_RXCORR_FORCE_0_U_B1__RXCORR_RXDC_FORCE_MODE_DC_I___S 24 +#define PHYA_PHYRF_RXCORR_FORCE_0_U_B1__RXCORR_RXDC_FORCE_MODE___M 0x00010000 +#define PHYA_PHYRF_RXCORR_FORCE_0_U_B1__RXCORR_RXDC_FORCE_MODE___S 16 +#define PHYA_PHYRF_RXCORR_FORCE_0_U_B1__RXCORR_RXDC_FORCE_BYPASS___M 0x00000100 +#define PHYA_PHYRF_RXCORR_FORCE_0_U_B1__RXCORR_RXDC_FORCE_BYPASS___S 8 +#define PHYA_PHYRF_RXCORR_FORCE_0_U_B1__RXCORR_RXIQ_FORCE_LOAD___M 0x00000001 +#define PHYA_PHYRF_RXCORR_FORCE_0_U_B1__RXCORR_RXIQ_FORCE_LOAD___S 0 +#define PHYA_PHYRF_RXCORR_FORCE_0_U_B1___M 0xFF010101 +#define PHYA_PHYRF_RXCORR_FORCE_0_U_B1___S 0 + +#define PHYA_PHYRF_RXCORR_FORCE_1_L_B0 (0x004900D8) +#define PHYA_PHYRF_RXCORR_FORCE_1_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXCORR_FORCE_1_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RXCORR_FORCE_1_L_B0__RXCORR_RXDC_FORCE_MODE_DC_Q___POR 0x00 +#define PHYA_PHYRF_RXCORR_FORCE_1_L_B0__RXCORR_RXDC_FORCE_MODE_DC_Q___M 0x000000FF +#define PHYA_PHYRF_RXCORR_FORCE_1_L_B0__RXCORR_RXDC_FORCE_MODE_DC_Q___S 0 +#define PHYA_PHYRF_RXCORR_FORCE_1_L_B0___M 0x000000FF +#define PHYA_PHYRF_RXCORR_FORCE_1_L_B0___S 0 + +#define PHYA_PHYRF_RXCORR_FORCE_1_L_B1 (0x004980D8) +#define PHYA_PHYRF_RXCORR_FORCE_1_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXCORR_FORCE_1_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RXCORR_FORCE_1_L_B1__RXCORR_RXDC_FORCE_MODE_DC_Q___POR 0x00 +#define PHYA_PHYRF_RXCORR_FORCE_1_L_B1__RXCORR_RXDC_FORCE_MODE_DC_Q___M 0x000000FF +#define PHYA_PHYRF_RXCORR_FORCE_1_L_B1__RXCORR_RXDC_FORCE_MODE_DC_Q___S 0 +#define PHYA_PHYRF_RXCORR_FORCE_1_L_B1___M 0x000000FF +#define PHYA_PHYRF_RXCORR_FORCE_1_L_B1___S 0 + +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_n(n) (0x004900E0+0x8*(n)) +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_n_nMIN 0 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_n_nMAX 0 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_n_ELEM 1 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_n___POR 0x00000000 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_n__PAPRD_COEF_Q_EVEN___POR 0x0000 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_n__PAPRD_COEF_I_EVEN___POR 0x0000 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_n__PAPRD_COEF_Q_EVEN___M 0x3FFF0000 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_n__PAPRD_COEF_Q_EVEN___S 16 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_n__PAPRD_COEF_I_EVEN___M 0x00003FFF +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_n__PAPRD_COEF_I_EVEN___S 0 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_n___M 0x3FFF3FFF +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_n___S 0 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_0 (0x004900E0) +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_0__PAPRD_COEF_Q_EVEN___M 0x3FFF0000 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_0__PAPRD_COEF_Q_EVEN___S 16 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_0__PAPRD_COEF_I_EVEN___M 0x00003FFF +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B0_0__PAPRD_COEF_I_EVEN___S 0 + +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_n(n) (0x004980E0+0x8*(n)) +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_n_nMIN 0 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_n_nMAX 0 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_n_ELEM 1 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_n___POR 0x00000000 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_n__PAPRD_COEF_Q_EVEN___POR 0x0000 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_n__PAPRD_COEF_I_EVEN___POR 0x0000 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_n__PAPRD_COEF_Q_EVEN___M 0x3FFF0000 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_n__PAPRD_COEF_Q_EVEN___S 16 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_n__PAPRD_COEF_I_EVEN___M 0x00003FFF +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_n__PAPRD_COEF_I_EVEN___S 0 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_n___M 0x3FFF3FFF +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_n___S 0 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_0 (0x004980E0) +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_0__PAPRD_COEF_Q_EVEN___M 0x3FFF0000 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_0__PAPRD_COEF_Q_EVEN___S 16 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_0__PAPRD_COEF_I_EVEN___M 0x00003FFF +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_L_B1_0__PAPRD_COEF_I_EVEN___S 0 + +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_n(n) (0x004900E4+0x8*(n)) +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_n_nMIN 0 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_n_nMAX 0 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_n_ELEM 1 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_n___POR 0x00000000 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_n__PAPRD_COEF_Q_ODD___POR 0x0000 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_n__PAPRD_COEF_I_ODD___POR 0x0000 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_n__PAPRD_COEF_Q_ODD___M 0x3FFF0000 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_n__PAPRD_COEF_Q_ODD___S 16 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_n__PAPRD_COEF_I_ODD___M 0x00003FFF +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_n__PAPRD_COEF_I_ODD___S 0 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_n___M 0x3FFF3FFF +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_n___S 0 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_0 (0x004900E4) +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_0__PAPRD_COEF_Q_ODD___M 0x3FFF0000 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_0__PAPRD_COEF_Q_ODD___S 16 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_0__PAPRD_COEF_I_ODD___M 0x00003FFF +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B0_0__PAPRD_COEF_I_ODD___S 0 + +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_n(n) (0x004980E4+0x8*(n)) +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_n_nMIN 0 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_n_nMAX 0 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_n_ELEM 1 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_n___POR 0x00000000 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_n__PAPRD_COEF_Q_ODD___POR 0x0000 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_n__PAPRD_COEF_I_ODD___POR 0x0000 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_n__PAPRD_COEF_Q_ODD___M 0x3FFF0000 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_n__PAPRD_COEF_Q_ODD___S 16 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_n__PAPRD_COEF_I_ODD___M 0x00003FFF +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_n__PAPRD_COEF_I_ODD___S 0 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_n___M 0x3FFF3FFF +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_n___S 0 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_0 (0x004980E4) +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_0__PAPRD_COEF_Q_ODD___M 0x3FFF0000 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_0__PAPRD_COEF_Q_ODD___S 16 +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_0__PAPRD_COEF_I_ODD___M 0x00003FFF +#define PHYA_PHYRF_PAPRD_MEMLESS_TAB_U_B1_0__PAPRD_COEF_I_ODD___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_n(n) (0x004908E0+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_n__BASE_Q_OR_I_ABSX1_0___POR 0x0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_n__LOWER_Q_OR_I_ABSX1_0___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_n__BASE_Q_OR_I_ABSX1_0___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_n__BASE_Q_OR_I_ABSX1_0___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_n__LOWER_Q_OR_I_ABSX1_0___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_n__LOWER_Q_OR_I_ABSX1_0___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_n___M 0x3FFF03FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_0 (0x004908E0) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_0__BASE_Q_OR_I_ABSX1_0___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_0__BASE_Q_OR_I_ABSX1_0___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_0__LOWER_Q_OR_I_ABSX1_0___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B0_0__LOWER_Q_OR_I_ABSX1_0___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_n(n) (0x004988E0+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_n__BASE_Q_OR_I_ABSX1_0___POR 0x0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_n__LOWER_Q_OR_I_ABSX1_0___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_n__BASE_Q_OR_I_ABSX1_0___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_n__BASE_Q_OR_I_ABSX1_0___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_n__LOWER_Q_OR_I_ABSX1_0___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_n__LOWER_Q_OR_I_ABSX1_0___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_n___M 0x3FFF03FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_0 (0x004988E0) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_0__BASE_Q_OR_I_ABSX1_0___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_0__BASE_Q_OR_I_ABSX1_0___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_0__LOWER_Q_OR_I_ABSX1_0___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_L_B1_0__LOWER_Q_OR_I_ABSX1_0___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B0_n(n) (0x004908E4+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B0_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B0_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B0_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B0_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX1_0___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX1_0___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX1_0___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B0_n___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B0_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B0_0 (0x004908E4) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B0_0__HIGHER_Q_OR_I_ABSX1_0___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B0_0__HIGHER_Q_OR_I_ABSX1_0___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B1_n(n) (0x004988E4+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B1_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B1_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B1_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B1_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX1_0___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX1_0___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX1_0___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B1_n___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B1_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B1_0 (0x004988E4) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B1_0__HIGHER_Q_OR_I_ABSX1_0___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_0_TAB_U_B1_0__HIGHER_Q_OR_I_ABSX1_0___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_n(n) (0x00490CE0+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_n__BASE_Q_OR_I_ABSX1_1___POR 0x0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_n__LOWER_Q_OR_I_ABSX1_1___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_n__BASE_Q_OR_I_ABSX1_1___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_n__BASE_Q_OR_I_ABSX1_1___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_n__LOWER_Q_OR_I_ABSX1_1___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_n__LOWER_Q_OR_I_ABSX1_1___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_n___M 0x3FFF03FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_0 (0x00490CE0) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_0__BASE_Q_OR_I_ABSX1_1___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_0__BASE_Q_OR_I_ABSX1_1___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_0__LOWER_Q_OR_I_ABSX1_1___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B0_0__LOWER_Q_OR_I_ABSX1_1___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_n(n) (0x00498CE0+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_n__BASE_Q_OR_I_ABSX1_1___POR 0x0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_n__LOWER_Q_OR_I_ABSX1_1___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_n__BASE_Q_OR_I_ABSX1_1___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_n__BASE_Q_OR_I_ABSX1_1___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_n__LOWER_Q_OR_I_ABSX1_1___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_n__LOWER_Q_OR_I_ABSX1_1___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_n___M 0x3FFF03FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_0 (0x00498CE0) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_0__BASE_Q_OR_I_ABSX1_1___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_0__BASE_Q_OR_I_ABSX1_1___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_0__LOWER_Q_OR_I_ABSX1_1___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_L_B1_0__LOWER_Q_OR_I_ABSX1_1___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B0_n(n) (0x00490CE4+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B0_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B0_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B0_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B0_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX1_1___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX1_1___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX1_1___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B0_n___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B0_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B0_0 (0x00490CE4) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B0_0__HIGHER_Q_OR_I_ABSX1_1___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B0_0__HIGHER_Q_OR_I_ABSX1_1___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B1_n(n) (0x00498CE4+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B1_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B1_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B1_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B1_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX1_1___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX1_1___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX1_1___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B1_n___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B1_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B1_0 (0x00498CE4) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B1_0__HIGHER_Q_OR_I_ABSX1_1___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX1_1_TAB_U_B1_0__HIGHER_Q_OR_I_ABSX1_1___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_n(n) (0x004910E0+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_n__BASE_Q_OR_I_ABSX2_0___POR 0x0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_n__LOWER_Q_OR_I_ABSX2_0___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_n__BASE_Q_OR_I_ABSX2_0___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_n__BASE_Q_OR_I_ABSX2_0___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_n__LOWER_Q_OR_I_ABSX2_0___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_n__LOWER_Q_OR_I_ABSX2_0___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_n___M 0x3FFF03FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_0 (0x004910E0) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_0__BASE_Q_OR_I_ABSX2_0___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_0__BASE_Q_OR_I_ABSX2_0___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_0__LOWER_Q_OR_I_ABSX2_0___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B0_0__LOWER_Q_OR_I_ABSX2_0___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_n(n) (0x004990E0+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_n__BASE_Q_OR_I_ABSX2_0___POR 0x0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_n__LOWER_Q_OR_I_ABSX2_0___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_n__BASE_Q_OR_I_ABSX2_0___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_n__BASE_Q_OR_I_ABSX2_0___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_n__LOWER_Q_OR_I_ABSX2_0___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_n__LOWER_Q_OR_I_ABSX2_0___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_n___M 0x3FFF03FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_0 (0x004990E0) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_0__BASE_Q_OR_I_ABSX2_0___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_0__BASE_Q_OR_I_ABSX2_0___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_0__LOWER_Q_OR_I_ABSX2_0___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_L_B1_0__LOWER_Q_OR_I_ABSX2_0___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B0_n(n) (0x004910E4+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B0_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B0_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B0_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B0_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX2_0___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX2_0___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX2_0___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B0_n___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B0_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B0_0 (0x004910E4) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B0_0__HIGHER_Q_OR_I_ABSX2_0___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B0_0__HIGHER_Q_OR_I_ABSX2_0___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B1_n(n) (0x004990E4+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B1_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B1_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B1_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B1_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX2_0___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX2_0___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX2_0___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B1_n___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B1_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B1_0 (0x004990E4) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B1_0__HIGHER_Q_OR_I_ABSX2_0___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_0_TAB_U_B1_0__HIGHER_Q_OR_I_ABSX2_0___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_n(n) (0x004914E0+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_n__BASE_Q_OR_I_ABSX2_1___POR 0x0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_n__LOWER_Q_OR_I_ABSX2_1___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_n__BASE_Q_OR_I_ABSX2_1___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_n__BASE_Q_OR_I_ABSX2_1___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_n__LOWER_Q_OR_I_ABSX2_1___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_n__LOWER_Q_OR_I_ABSX2_1___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_n___M 0x3FFF03FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_0 (0x004914E0) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_0__BASE_Q_OR_I_ABSX2_1___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_0__BASE_Q_OR_I_ABSX2_1___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_0__LOWER_Q_OR_I_ABSX2_1___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B0_0__LOWER_Q_OR_I_ABSX2_1___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_n(n) (0x004994E0+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_n__BASE_Q_OR_I_ABSX2_1___POR 0x0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_n__LOWER_Q_OR_I_ABSX2_1___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_n__BASE_Q_OR_I_ABSX2_1___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_n__BASE_Q_OR_I_ABSX2_1___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_n__LOWER_Q_OR_I_ABSX2_1___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_n__LOWER_Q_OR_I_ABSX2_1___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_n___M 0x3FFF03FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_0 (0x004994E0) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_0__BASE_Q_OR_I_ABSX2_1___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_0__BASE_Q_OR_I_ABSX2_1___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_0__LOWER_Q_OR_I_ABSX2_1___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_L_B1_0__LOWER_Q_OR_I_ABSX2_1___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B0_n(n) (0x004914E4+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B0_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B0_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B0_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B0_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX2_1___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX2_1___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX2_1___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B0_n___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B0_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B0_0 (0x004914E4) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B0_0__HIGHER_Q_OR_I_ABSX2_1___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B0_0__HIGHER_Q_OR_I_ABSX2_1___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B1_n(n) (0x004994E4+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B1_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B1_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B1_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B1_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX2_1___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX2_1___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX2_1___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B1_n___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B1_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B1_0 (0x004994E4) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B1_0__HIGHER_Q_OR_I_ABSX2_1___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX2_1_TAB_U_B1_0__HIGHER_Q_OR_I_ABSX2_1___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_n(n) (0x004918E0+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_n__BASE_Q_OR_I_ABSX3___POR 0x0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_n__LOWER_Q_OR_I_ABSX3___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_n__BASE_Q_OR_I_ABSX3___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_n__BASE_Q_OR_I_ABSX3___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_n__LOWER_Q_OR_I_ABSX3___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_n__LOWER_Q_OR_I_ABSX3___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_n___M 0x3FFF03FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_0 (0x004918E0) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_0__BASE_Q_OR_I_ABSX3___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_0__BASE_Q_OR_I_ABSX3___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_0__LOWER_Q_OR_I_ABSX3___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B0_0__LOWER_Q_OR_I_ABSX3___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_n(n) (0x004998E0+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_n__BASE_Q_OR_I_ABSX3___POR 0x0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_n__LOWER_Q_OR_I_ABSX3___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_n__BASE_Q_OR_I_ABSX3___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_n__BASE_Q_OR_I_ABSX3___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_n__LOWER_Q_OR_I_ABSX3___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_n__LOWER_Q_OR_I_ABSX3___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_n___M 0x3FFF03FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_0 (0x004998E0) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_0__BASE_Q_OR_I_ABSX3___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_0__BASE_Q_OR_I_ABSX3___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_0__LOWER_Q_OR_I_ABSX3___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_L_B1_0__LOWER_Q_OR_I_ABSX3___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B0_n(n) (0x004918E4+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B0_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B0_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B0_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B0_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX3___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX3___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX3___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B0_n___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B0_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B0_0 (0x004918E4) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B0_0__HIGHER_Q_OR_I_ABSX3___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B0_0__HIGHER_Q_OR_I_ABSX3___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B1_n(n) (0x004998E4+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B1_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B1_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B1_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B1_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX3___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX3___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX3___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B1_n___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B1_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B1_0 (0x004998E4) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B1_0__HIGHER_Q_OR_I_ABSX3___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX3_TAB_U_B1_0__HIGHER_Q_OR_I_ABSX3___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_n(n) (0x00491CE0+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_n__BASE_Q_OR_I_ABSX4___POR 0x0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_n__LOWER_Q_OR_I_ABSX4___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_n__BASE_Q_OR_I_ABSX4___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_n__BASE_Q_OR_I_ABSX4___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_n__LOWER_Q_OR_I_ABSX4___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_n__LOWER_Q_OR_I_ABSX4___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_n___M 0x3FFF03FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_0 (0x00491CE0) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_0__BASE_Q_OR_I_ABSX4___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_0__BASE_Q_OR_I_ABSX4___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_0__LOWER_Q_OR_I_ABSX4___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B0_0__LOWER_Q_OR_I_ABSX4___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_n(n) (0x00499CE0+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_n__BASE_Q_OR_I_ABSX4___POR 0x0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_n__LOWER_Q_OR_I_ABSX4___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_n__BASE_Q_OR_I_ABSX4___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_n__BASE_Q_OR_I_ABSX4___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_n__LOWER_Q_OR_I_ABSX4___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_n__LOWER_Q_OR_I_ABSX4___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_n___M 0x3FFF03FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_0 (0x00499CE0) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_0__BASE_Q_OR_I_ABSX4___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_0__BASE_Q_OR_I_ABSX4___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_0__LOWER_Q_OR_I_ABSX4___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_L_B1_0__LOWER_Q_OR_I_ABSX4___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B0_n(n) (0x00491CE4+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B0_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B0_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B0_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B0_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX4___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX4___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B0_n__HIGHER_Q_OR_I_ABSX4___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B0_n___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B0_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B0_0 (0x00491CE4) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B0_0__HIGHER_Q_OR_I_ABSX4___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B0_0__HIGHER_Q_OR_I_ABSX4___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B1_n(n) (0x00499CE4+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B1_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B1_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B1_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B1_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX4___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX4___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B1_n__HIGHER_Q_OR_I_ABSX4___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B1_n___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B1_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B1_0 (0x00499CE4) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B1_0__HIGHER_Q_OR_I_ABSX4___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSX4_TAB_U_B1_0__HIGHER_Q_OR_I_ABSX4___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_n(n) (0x004920E0+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_n__BASE_Q_OR_I_ABSXQ5___POR 0x0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_n__LOWER_Q_OR_I_ABSXQ5___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_n__BASE_Q_OR_I_ABSXQ5___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_n__BASE_Q_OR_I_ABSXQ5___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_n__LOWER_Q_OR_I_ABSXQ5___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_n__LOWER_Q_OR_I_ABSXQ5___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_n___M 0x3FFF03FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_0 (0x004920E0) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_0__BASE_Q_OR_I_ABSXQ5___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_0__BASE_Q_OR_I_ABSXQ5___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_0__LOWER_Q_OR_I_ABSXQ5___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B0_0__LOWER_Q_OR_I_ABSXQ5___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_n(n) (0x0049A0E0+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_n__BASE_Q_OR_I_ABSXQ5___POR 0x0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_n__LOWER_Q_OR_I_ABSXQ5___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_n__BASE_Q_OR_I_ABSXQ5___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_n__BASE_Q_OR_I_ABSXQ5___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_n__LOWER_Q_OR_I_ABSXQ5___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_n__LOWER_Q_OR_I_ABSXQ5___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_n___M 0x3FFF03FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_0 (0x0049A0E0) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_0__BASE_Q_OR_I_ABSXQ5___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_0__BASE_Q_OR_I_ABSXQ5___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_0__LOWER_Q_OR_I_ABSXQ5___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_L_B1_0__LOWER_Q_OR_I_ABSXQ5___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B0_n(n) (0x004920E4+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B0_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B0_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B0_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B0_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B0_n__HIGHER_Q_OR_I_ABSXQ5___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B0_n__HIGHER_Q_OR_I_ABSXQ5___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B0_n__HIGHER_Q_OR_I_ABSXQ5___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B0_n___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B0_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B0_0 (0x004920E4) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B0_0__HIGHER_Q_OR_I_ABSXQ5___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B0_0__HIGHER_Q_OR_I_ABSXQ5___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B1_n(n) (0x0049A0E4+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B1_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B1_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B1_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B1_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B1_n__HIGHER_Q_OR_I_ABSXQ5___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B1_n__HIGHER_Q_OR_I_ABSXQ5___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B1_n__HIGHER_Q_OR_I_ABSXQ5___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B1_n___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B1_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B1_0 (0x0049A0E4) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B1_0__HIGHER_Q_OR_I_ABSXQ5___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ5_TAB_U_B1_0__HIGHER_Q_OR_I_ABSXQ5___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_n(n) (0x004924E0+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_n__BASE_Q_OR_I_ABSXQ6___POR 0x0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_n__LOWER_Q_OR_I_ABSXQ6___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_n__BASE_Q_OR_I_ABSXQ6___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_n__BASE_Q_OR_I_ABSXQ6___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_n__LOWER_Q_OR_I_ABSXQ6___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_n__LOWER_Q_OR_I_ABSXQ6___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_n___M 0x3FFF03FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_0 (0x004924E0) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_0__BASE_Q_OR_I_ABSXQ6___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_0__BASE_Q_OR_I_ABSXQ6___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_0__LOWER_Q_OR_I_ABSXQ6___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B0_0__LOWER_Q_OR_I_ABSXQ6___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_n(n) (0x0049A4E0+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_n__BASE_Q_OR_I_ABSXQ6___POR 0x0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_n__LOWER_Q_OR_I_ABSXQ6___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_n__BASE_Q_OR_I_ABSXQ6___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_n__BASE_Q_OR_I_ABSXQ6___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_n__LOWER_Q_OR_I_ABSXQ6___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_n__LOWER_Q_OR_I_ABSXQ6___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_n___M 0x3FFF03FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_0 (0x0049A4E0) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_0__BASE_Q_OR_I_ABSXQ6___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_0__BASE_Q_OR_I_ABSXQ6___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_0__LOWER_Q_OR_I_ABSXQ6___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_L_B1_0__LOWER_Q_OR_I_ABSXQ6___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B0_n(n) (0x004924E4+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B0_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B0_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B0_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B0_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B0_n__HIGHER_Q_OR_I_ABSXQ6___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B0_n__HIGHER_Q_OR_I_ABSXQ6___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B0_n__HIGHER_Q_OR_I_ABSXQ6___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B0_n___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B0_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B0_0 (0x004924E4) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B0_0__HIGHER_Q_OR_I_ABSXQ6___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B0_0__HIGHER_Q_OR_I_ABSXQ6___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B1_n(n) (0x0049A4E4+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B1_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B1_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B1_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B1_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B1_n__HIGHER_Q_OR_I_ABSXQ6___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B1_n__HIGHER_Q_OR_I_ABSXQ6___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B1_n__HIGHER_Q_OR_I_ABSXQ6___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B1_n___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B1_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B1_0 (0x0049A4E4) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B1_0__HIGHER_Q_OR_I_ABSXQ6___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ6_TAB_U_B1_0__HIGHER_Q_OR_I_ABSXQ6___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_n(n) (0x004928E0+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_n__BASE_Q_OR_I_ABSXQ7___POR 0x0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_n__LOWER_Q_OR_I_ABSXQ7___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_n__BASE_Q_OR_I_ABSXQ7___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_n__BASE_Q_OR_I_ABSXQ7___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_n__LOWER_Q_OR_I_ABSXQ7___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_n__LOWER_Q_OR_I_ABSXQ7___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_n___M 0x3FFF03FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_0 (0x004928E0) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_0__BASE_Q_OR_I_ABSXQ7___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_0__BASE_Q_OR_I_ABSXQ7___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_0__LOWER_Q_OR_I_ABSXQ7___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B0_0__LOWER_Q_OR_I_ABSXQ7___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_n(n) (0x0049A8E0+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_n__BASE_Q_OR_I_ABSXQ7___POR 0x0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_n__LOWER_Q_OR_I_ABSXQ7___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_n__BASE_Q_OR_I_ABSXQ7___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_n__BASE_Q_OR_I_ABSXQ7___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_n__LOWER_Q_OR_I_ABSXQ7___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_n__LOWER_Q_OR_I_ABSXQ7___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_n___M 0x3FFF03FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_0 (0x0049A8E0) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_0__BASE_Q_OR_I_ABSXQ7___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_0__BASE_Q_OR_I_ABSXQ7___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_0__LOWER_Q_OR_I_ABSXQ7___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_L_B1_0__LOWER_Q_OR_I_ABSXQ7___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B0_n(n) (0x004928E4+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B0_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B0_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B0_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B0_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B0_n__HIGHER_Q_OR_I_ABSXQ7___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B0_n__HIGHER_Q_OR_I_ABSXQ7___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B0_n__HIGHER_Q_OR_I_ABSXQ7___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B0_n___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B0_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B0_0 (0x004928E4) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B0_0__HIGHER_Q_OR_I_ABSXQ7___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B0_0__HIGHER_Q_OR_I_ABSXQ7___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B1_n(n) (0x0049A8E4+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B1_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B1_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B1_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B1_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B1_n__HIGHER_Q_OR_I_ABSXQ7___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B1_n__HIGHER_Q_OR_I_ABSXQ7___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B1_n__HIGHER_Q_OR_I_ABSXQ7___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B1_n___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B1_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B1_0 (0x0049A8E4) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B1_0__HIGHER_Q_OR_I_ABSXQ7___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ7_TAB_U_B1_0__HIGHER_Q_OR_I_ABSXQ7___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_n(n) (0x00492CE0+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_n__BASE_Q_OR_I_ABSXQ8___POR 0x0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_n__LOWER_Q_OR_I_ABSXQ8___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_n__BASE_Q_OR_I_ABSXQ8___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_n__BASE_Q_OR_I_ABSXQ8___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_n__LOWER_Q_OR_I_ABSXQ8___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_n__LOWER_Q_OR_I_ABSXQ8___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_n___M 0x3FFF03FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_0 (0x00492CE0) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_0__BASE_Q_OR_I_ABSXQ8___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_0__BASE_Q_OR_I_ABSXQ8___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_0__LOWER_Q_OR_I_ABSXQ8___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B0_0__LOWER_Q_OR_I_ABSXQ8___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_n(n) (0x0049ACE0+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_n__BASE_Q_OR_I_ABSXQ8___POR 0x0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_n__LOWER_Q_OR_I_ABSXQ8___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_n__BASE_Q_OR_I_ABSXQ8___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_n__BASE_Q_OR_I_ABSXQ8___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_n__LOWER_Q_OR_I_ABSXQ8___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_n__LOWER_Q_OR_I_ABSXQ8___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_n___M 0x3FFF03FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_0 (0x0049ACE0) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_0__BASE_Q_OR_I_ABSXQ8___M 0x3FFF0000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_0__BASE_Q_OR_I_ABSXQ8___S 16 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_0__LOWER_Q_OR_I_ABSXQ8___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_L_B1_0__LOWER_Q_OR_I_ABSXQ8___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B0_n(n) (0x00492CE4+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B0_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B0_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B0_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B0_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B0_n__HIGHER_Q_OR_I_ABSXQ8___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B0_n__HIGHER_Q_OR_I_ABSXQ8___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B0_n__HIGHER_Q_OR_I_ABSXQ8___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B0_n___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B0_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B0_0 (0x00492CE4) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B0_0__HIGHER_Q_OR_I_ABSXQ8___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B0_0__HIGHER_Q_OR_I_ABSXQ8___S 0 + +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B1_n(n) (0x0049ACE4+0x8*(n)) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B1_n_nMIN 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B1_n_nMAX 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B1_n_ELEM 1 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B1_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B1_n__HIGHER_Q_OR_I_ABSXQ8___POR 0x000 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B1_n__HIGHER_Q_OR_I_ABSXQ8___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B1_n__HIGHER_Q_OR_I_ABSXQ8___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B1_n___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B1_n___S 0 +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B1_0 (0x0049ACE4) +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B1_0__HIGHER_Q_OR_I_ABSXQ8___M 0x000003FF +#define PHYA_PHYRF_EDPD_LUT_MEM_ABSXQ8_TAB_U_B1_0__HIGHER_Q_OR_I_ABSXQ8___S 0 + +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_n(n) (0x004930E0+0x8*(n)) +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_n_nMIN 0 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_n_nMAX 0 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_n_ELEM 1 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_n__COEF_A_Q_EVEN___POR 0x000 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_n__COEF_A_I_EVEN___POR 0x000 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_n__COEF_A_Q_EVEN___M 0x0FFF0000 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_n__COEF_A_Q_EVEN___S 16 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_n__COEF_A_I_EVEN___M 0x00000FFF +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_n__COEF_A_I_EVEN___S 0 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_n___M 0x0FFF0FFF +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_n___S 0 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_0 (0x004930E0) +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_0__COEF_A_Q_EVEN___M 0x0FFF0000 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_0__COEF_A_Q_EVEN___S 16 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_0__COEF_A_I_EVEN___M 0x00000FFF +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B0_0__COEF_A_I_EVEN___S 0 + +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_n(n) (0x0049B0E0+0x8*(n)) +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_n_nMIN 0 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_n_nMAX 0 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_n_ELEM 1 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_n__COEF_A_Q_EVEN___POR 0x000 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_n__COEF_A_I_EVEN___POR 0x000 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_n__COEF_A_Q_EVEN___M 0x0FFF0000 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_n__COEF_A_Q_EVEN___S 16 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_n__COEF_A_I_EVEN___M 0x00000FFF +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_n__COEF_A_I_EVEN___S 0 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_n___M 0x0FFF0FFF +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_n___S 0 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_0 (0x0049B0E0) +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_0__COEF_A_Q_EVEN___M 0x0FFF0000 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_0__COEF_A_Q_EVEN___S 16 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_0__COEF_A_I_EVEN___M 0x00000FFF +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_L_B1_0__COEF_A_I_EVEN___S 0 + +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_n(n) (0x004930E4+0x8*(n)) +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_n_nMIN 0 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_n_nMAX 0 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_n_ELEM 1 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_n__COEF_A_Q_ODD___POR 0x000 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_n__COEF_A_I_ODD___POR 0x000 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_n__COEF_A_Q_ODD___M 0x0FFF0000 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_n__COEF_A_Q_ODD___S 16 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_n__COEF_A_I_ODD___M 0x00000FFF +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_n__COEF_A_I_ODD___S 0 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_n___M 0x0FFF0FFF +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_n___S 0 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_0 (0x004930E4) +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_0__COEF_A_Q_ODD___M 0x0FFF0000 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_0__COEF_A_Q_ODD___S 16 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_0__COEF_A_I_ODD___M 0x00000FFF +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B0_0__COEF_A_I_ODD___S 0 + +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_n(n) (0x0049B0E4+0x8*(n)) +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_n_nMIN 0 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_n_nMAX 0 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_n_ELEM 1 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_n___POR 0x00000000 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_n__COEF_A_Q_ODD___POR 0x000 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_n__COEF_A_I_ODD___POR 0x000 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_n__COEF_A_Q_ODD___M 0x0FFF0000 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_n__COEF_A_Q_ODD___S 16 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_n__COEF_A_I_ODD___M 0x00000FFF +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_n__COEF_A_I_ODD___S 0 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_n___M 0x0FFF0FFF +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_n___S 0 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_0 (0x0049B0E4) +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_0__COEF_A_Q_ODD___M 0x0FFF0000 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_0__COEF_A_Q_ODD___S 16 +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_0__COEF_A_I_ODD___M 0x00000FFF +#define PHYA_PHYRF_EDPD_COEF_MEM_TAB_U_B1_0__COEF_A_I_ODD___S 0 + +#define PHYA_PHYRF_CL_TAB_L_B0_n(n) (0x004931A0+0x8*(n)) +#define PHYA_PHYRF_CL_TAB_L_B0_n_nMIN 0 +#define PHYA_PHYRF_CL_TAB_L_B0_n_nMAX 0 +#define PHYA_PHYRF_CL_TAB_L_B0_n_ELEM 1 +#define PHYA_PHYRF_CL_TAB_L_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_CL_TAB_L_B0_n___POR 0x00000000 +#define PHYA_PHYRF_CL_TAB_L_B0_n__CL_CARR_Q_EVEN___POR 0x000 +#define PHYA_PHYRF_CL_TAB_L_B0_n__CL_CARR_I_EVEN___POR 0x000 +#define PHYA_PHYRF_CL_TAB_L_B0_n__CL_CARR_Q_EVEN___M 0x07FF0000 +#define PHYA_PHYRF_CL_TAB_L_B0_n__CL_CARR_Q_EVEN___S 16 +#define PHYA_PHYRF_CL_TAB_L_B0_n__CL_CARR_I_EVEN___M 0x000007FF +#define PHYA_PHYRF_CL_TAB_L_B0_n__CL_CARR_I_EVEN___S 0 +#define PHYA_PHYRF_CL_TAB_L_B0_n___M 0x07FF07FF +#define PHYA_PHYRF_CL_TAB_L_B0_n___S 0 +#define PHYA_PHYRF_CL_TAB_L_B0_0 (0x004931A0) +#define PHYA_PHYRF_CL_TAB_L_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_CL_TAB_L_B0_0__CL_CARR_Q_EVEN___M 0x07FF0000 +#define PHYA_PHYRF_CL_TAB_L_B0_0__CL_CARR_Q_EVEN___S 16 +#define PHYA_PHYRF_CL_TAB_L_B0_0__CL_CARR_I_EVEN___M 0x000007FF +#define PHYA_PHYRF_CL_TAB_L_B0_0__CL_CARR_I_EVEN___S 0 + +#define PHYA_PHYRF_CL_TAB_L_B1_n(n) (0x0049B1A0+0x8*(n)) +#define PHYA_PHYRF_CL_TAB_L_B1_n_nMIN 0 +#define PHYA_PHYRF_CL_TAB_L_B1_n_nMAX 0 +#define PHYA_PHYRF_CL_TAB_L_B1_n_ELEM 1 +#define PHYA_PHYRF_CL_TAB_L_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_CL_TAB_L_B1_n___POR 0x00000000 +#define PHYA_PHYRF_CL_TAB_L_B1_n__CL_CARR_Q_EVEN___POR 0x000 +#define PHYA_PHYRF_CL_TAB_L_B1_n__CL_CARR_I_EVEN___POR 0x000 +#define PHYA_PHYRF_CL_TAB_L_B1_n__CL_CARR_Q_EVEN___M 0x07FF0000 +#define PHYA_PHYRF_CL_TAB_L_B1_n__CL_CARR_Q_EVEN___S 16 +#define PHYA_PHYRF_CL_TAB_L_B1_n__CL_CARR_I_EVEN___M 0x000007FF +#define PHYA_PHYRF_CL_TAB_L_B1_n__CL_CARR_I_EVEN___S 0 +#define PHYA_PHYRF_CL_TAB_L_B1_n___M 0x07FF07FF +#define PHYA_PHYRF_CL_TAB_L_B1_n___S 0 +#define PHYA_PHYRF_CL_TAB_L_B1_0 (0x0049B1A0) +#define PHYA_PHYRF_CL_TAB_L_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_CL_TAB_L_B1_0__CL_CARR_Q_EVEN___M 0x07FF0000 +#define PHYA_PHYRF_CL_TAB_L_B1_0__CL_CARR_Q_EVEN___S 16 +#define PHYA_PHYRF_CL_TAB_L_B1_0__CL_CARR_I_EVEN___M 0x000007FF +#define PHYA_PHYRF_CL_TAB_L_B1_0__CL_CARR_I_EVEN___S 0 + +#define PHYA_PHYRF_CL_TAB_U_B0_n(n) (0x004931A4+0x8*(n)) +#define PHYA_PHYRF_CL_TAB_U_B0_n_nMIN 0 +#define PHYA_PHYRF_CL_TAB_U_B0_n_nMAX 0 +#define PHYA_PHYRF_CL_TAB_U_B0_n_ELEM 1 +#define PHYA_PHYRF_CL_TAB_U_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_CL_TAB_U_B0_n___POR 0x00000000 +#define PHYA_PHYRF_CL_TAB_U_B0_n__CL_CARR_Q_ODD___POR 0x000 +#define PHYA_PHYRF_CL_TAB_U_B0_n__CL_CARR_I_ODD___POR 0x000 +#define PHYA_PHYRF_CL_TAB_U_B0_n__CL_CARR_Q_ODD___M 0x07FF0000 +#define PHYA_PHYRF_CL_TAB_U_B0_n__CL_CARR_Q_ODD___S 16 +#define PHYA_PHYRF_CL_TAB_U_B0_n__CL_CARR_I_ODD___M 0x000007FF +#define PHYA_PHYRF_CL_TAB_U_B0_n__CL_CARR_I_ODD___S 0 +#define PHYA_PHYRF_CL_TAB_U_B0_n___M 0x07FF07FF +#define PHYA_PHYRF_CL_TAB_U_B0_n___S 0 +#define PHYA_PHYRF_CL_TAB_U_B0_0 (0x004931A4) +#define PHYA_PHYRF_CL_TAB_U_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_CL_TAB_U_B0_0__CL_CARR_Q_ODD___M 0x07FF0000 +#define PHYA_PHYRF_CL_TAB_U_B0_0__CL_CARR_Q_ODD___S 16 +#define PHYA_PHYRF_CL_TAB_U_B0_0__CL_CARR_I_ODD___M 0x000007FF +#define PHYA_PHYRF_CL_TAB_U_B0_0__CL_CARR_I_ODD___S 0 + +#define PHYA_PHYRF_CL_TAB_U_B1_n(n) (0x0049B1A4+0x8*(n)) +#define PHYA_PHYRF_CL_TAB_U_B1_n_nMIN 0 +#define PHYA_PHYRF_CL_TAB_U_B1_n_nMAX 0 +#define PHYA_PHYRF_CL_TAB_U_B1_n_ELEM 1 +#define PHYA_PHYRF_CL_TAB_U_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_CL_TAB_U_B1_n___POR 0x00000000 +#define PHYA_PHYRF_CL_TAB_U_B1_n__CL_CARR_Q_ODD___POR 0x000 +#define PHYA_PHYRF_CL_TAB_U_B1_n__CL_CARR_I_ODD___POR 0x000 +#define PHYA_PHYRF_CL_TAB_U_B1_n__CL_CARR_Q_ODD___M 0x07FF0000 +#define PHYA_PHYRF_CL_TAB_U_B1_n__CL_CARR_Q_ODD___S 16 +#define PHYA_PHYRF_CL_TAB_U_B1_n__CL_CARR_I_ODD___M 0x000007FF +#define PHYA_PHYRF_CL_TAB_U_B1_n__CL_CARR_I_ODD___S 0 +#define PHYA_PHYRF_CL_TAB_U_B1_n___M 0x07FF07FF +#define PHYA_PHYRF_CL_TAB_U_B1_n___S 0 +#define PHYA_PHYRF_CL_TAB_U_B1_0 (0x0049B1A4) +#define PHYA_PHYRF_CL_TAB_U_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_CL_TAB_U_B1_0__CL_CARR_Q_ODD___M 0x07FF0000 +#define PHYA_PHYRF_CL_TAB_U_B1_0__CL_CARR_Q_ODD___S 16 +#define PHYA_PHYRF_CL_TAB_U_B1_0__CL_CARR_I_ODD___M 0x000007FF +#define PHYA_PHYRF_CL_TAB_U_B1_0__CL_CARR_I_ODD___S 0 + +#define PHYA_PHYRF_TXIQCORR_MEM_L_B0_n(n) (0x004932A0+0x8*(n)) +#define PHYA_PHYRF_TXIQCORR_MEM_L_B0_n_nMIN 0 +#define PHYA_PHYRF_TXIQCORR_MEM_L_B0_n_nMAX 0 +#define PHYA_PHYRF_TXIQCORR_MEM_L_B0_n_ELEM 1 +#define PHYA_PHYRF_TXIQCORR_MEM_L_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_TXIQCORR_MEM_L_B0_n___POR 0x00000000 +#define PHYA_PHYRF_TXIQCORR_MEM_L_B0_n__TX_IQCOEFF_0_31BIT___POR 0x00000000 +#define PHYA_PHYRF_TXIQCORR_MEM_L_B0_n__TX_IQCOEFF_0_31BIT___M 0xFFFFFFFF +#define PHYA_PHYRF_TXIQCORR_MEM_L_B0_n__TX_IQCOEFF_0_31BIT___S 0 +#define PHYA_PHYRF_TXIQCORR_MEM_L_B0_n___M 0xFFFFFFFF +#define PHYA_PHYRF_TXIQCORR_MEM_L_B0_n___S 0 +#define PHYA_PHYRF_TXIQCORR_MEM_L_B0_0 (0x004932A0) +#define PHYA_PHYRF_TXIQCORR_MEM_L_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_TXIQCORR_MEM_L_B0_0__TX_IQCOEFF_0_31BIT___M 0xFFFFFFFF +#define PHYA_PHYRF_TXIQCORR_MEM_L_B0_0__TX_IQCOEFF_0_31BIT___S 0 + +#define PHYA_PHYRF_TXIQCORR_MEM_L_B1_n(n) (0x0049B2A0+0x8*(n)) +#define PHYA_PHYRF_TXIQCORR_MEM_L_B1_n_nMIN 0 +#define PHYA_PHYRF_TXIQCORR_MEM_L_B1_n_nMAX 0 +#define PHYA_PHYRF_TXIQCORR_MEM_L_B1_n_ELEM 1 +#define PHYA_PHYRF_TXIQCORR_MEM_L_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_TXIQCORR_MEM_L_B1_n___POR 0x00000000 +#define PHYA_PHYRF_TXIQCORR_MEM_L_B1_n__TX_IQCOEFF_0_31BIT___POR 0x00000000 +#define PHYA_PHYRF_TXIQCORR_MEM_L_B1_n__TX_IQCOEFF_0_31BIT___M 0xFFFFFFFF +#define PHYA_PHYRF_TXIQCORR_MEM_L_B1_n__TX_IQCOEFF_0_31BIT___S 0 +#define PHYA_PHYRF_TXIQCORR_MEM_L_B1_n___M 0xFFFFFFFF +#define PHYA_PHYRF_TXIQCORR_MEM_L_B1_n___S 0 +#define PHYA_PHYRF_TXIQCORR_MEM_L_B1_0 (0x0049B2A0) +#define PHYA_PHYRF_TXIQCORR_MEM_L_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_TXIQCORR_MEM_L_B1_0__TX_IQCOEFF_0_31BIT___M 0xFFFFFFFF +#define PHYA_PHYRF_TXIQCORR_MEM_L_B1_0__TX_IQCOEFF_0_31BIT___S 0 + +#define PHYA_PHYRF_TXIQCORR_MEM_U_B0_n(n) (0x004932A4+0x8*(n)) +#define PHYA_PHYRF_TXIQCORR_MEM_U_B0_n_nMIN 0 +#define PHYA_PHYRF_TXIQCORR_MEM_U_B0_n_nMAX 0 +#define PHYA_PHYRF_TXIQCORR_MEM_U_B0_n_ELEM 1 +#define PHYA_PHYRF_TXIQCORR_MEM_U_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_TXIQCORR_MEM_U_B0_n___POR 0x00000000 +#define PHYA_PHYRF_TXIQCORR_MEM_U_B0_n__TX_IQCOEFF_32_62BIT___POR 0x00000000 +#define PHYA_PHYRF_TXIQCORR_MEM_U_B0_n__TX_IQCOEFF_32_62BIT___M 0x7FFFFFFF +#define PHYA_PHYRF_TXIQCORR_MEM_U_B0_n__TX_IQCOEFF_32_62BIT___S 0 +#define PHYA_PHYRF_TXIQCORR_MEM_U_B0_n___M 0x7FFFFFFF +#define PHYA_PHYRF_TXIQCORR_MEM_U_B0_n___S 0 +#define PHYA_PHYRF_TXIQCORR_MEM_U_B0_0 (0x004932A4) +#define PHYA_PHYRF_TXIQCORR_MEM_U_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_TXIQCORR_MEM_U_B0_0__TX_IQCOEFF_32_62BIT___M 0x7FFFFFFF +#define PHYA_PHYRF_TXIQCORR_MEM_U_B0_0__TX_IQCOEFF_32_62BIT___S 0 + +#define PHYA_PHYRF_TXIQCORR_MEM_U_B1_n(n) (0x0049B2A4+0x8*(n)) +#define PHYA_PHYRF_TXIQCORR_MEM_U_B1_n_nMIN 0 +#define PHYA_PHYRF_TXIQCORR_MEM_U_B1_n_nMAX 0 +#define PHYA_PHYRF_TXIQCORR_MEM_U_B1_n_ELEM 1 +#define PHYA_PHYRF_TXIQCORR_MEM_U_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_TXIQCORR_MEM_U_B1_n___POR 0x00000000 +#define PHYA_PHYRF_TXIQCORR_MEM_U_B1_n__TX_IQCOEFF_32_62BIT___POR 0x00000000 +#define PHYA_PHYRF_TXIQCORR_MEM_U_B1_n__TX_IQCOEFF_32_62BIT___M 0x7FFFFFFF +#define PHYA_PHYRF_TXIQCORR_MEM_U_B1_n__TX_IQCOEFF_32_62BIT___S 0 +#define PHYA_PHYRF_TXIQCORR_MEM_U_B1_n___M 0x7FFFFFFF +#define PHYA_PHYRF_TXIQCORR_MEM_U_B1_n___S 0 +#define PHYA_PHYRF_TXIQCORR_MEM_U_B1_0 (0x0049B2A4) +#define PHYA_PHYRF_TXIQCORR_MEM_U_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_TXIQCORR_MEM_U_B1_0__TX_IQCOEFF_32_62BIT___M 0x7FFFFFFF +#define PHYA_PHYRF_TXIQCORR_MEM_U_B1_0__TX_IQCOEFF_32_62BIT___S 0 + +#define PHYA_PHYRF_TXTDC_CHN_STATUS_L_B0 (0x004938A0) +#define PHYA_PHYRF_TXTDC_CHN_STATUS_L_B0___RWC QCSR_REG_RO +#define PHYA_PHYRF_TXTDC_CHN_STATUS_L_B0___POR 0x00000000 +#define PHYA_PHYRF_TXTDC_CHN_STATUS_L_B0__TXTDC_CHN_STATUS___POR 0x00000000 +#define PHYA_PHYRF_TXTDC_CHN_STATUS_L_B0__TXTDC_CHN_STATUS___M 0xFFFFFFFF +#define PHYA_PHYRF_TXTDC_CHN_STATUS_L_B0__TXTDC_CHN_STATUS___S 0 +#define PHYA_PHYRF_TXTDC_CHN_STATUS_L_B0___M 0xFFFFFFFF +#define PHYA_PHYRF_TXTDC_CHN_STATUS_L_B0___S 0 + +#define PHYA_PHYRF_TXTDC_CHN_STATUS_L_B1 (0x0049B8A0) +#define PHYA_PHYRF_TXTDC_CHN_STATUS_L_B1___RWC QCSR_REG_RO +#define PHYA_PHYRF_TXTDC_CHN_STATUS_L_B1___POR 0x00000000 +#define PHYA_PHYRF_TXTDC_CHN_STATUS_L_B1__TXTDC_CHN_STATUS___POR 0x00000000 +#define PHYA_PHYRF_TXTDC_CHN_STATUS_L_B1__TXTDC_CHN_STATUS___M 0xFFFFFFFF +#define PHYA_PHYRF_TXTDC_CHN_STATUS_L_B1__TXTDC_CHN_STATUS___S 0 +#define PHYA_PHYRF_TXTDC_CHN_STATUS_L_B1___M 0xFFFFFFFF +#define PHYA_PHYRF_TXTDC_CHN_STATUS_L_B1___S 0 + +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_n(n) (0x004938A8+0x8*(n)) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_n_nMIN 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_n_nMAX 7 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_n_ELEM 8 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_n___POR 0x00000000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___POR 0x000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___POR 0x000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_n___M 0x01FF01FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_n___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_0 (0x004938A8) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_0__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_0__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_0__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_0__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_1 (0x004938B0) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_1___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_1__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_1__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_1__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_1__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_2 (0x004938B8) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_2___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_2__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_2__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_2__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_2__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_3 (0x004938C0) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_3___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_3__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_3__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_3__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_3__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_4 (0x004938C8) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_4___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_4__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_4__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_4__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_4__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_5 (0x004938D0) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_5___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_5__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_5__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_5__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_5__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_6 (0x004938D8) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_6___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_6__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_6__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_6__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_6__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_7 (0x004938E0) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_7___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_7__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_7__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_7__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B0_7__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 + +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_n(n) (0x0049B8A8+0x8*(n)) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_n_nMIN 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_n_nMAX 7 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_n_ELEM 8 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_n___POR 0x00000000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___POR 0x000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___POR 0x000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_n___M 0x01FF01FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_n___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_0 (0x0049B8A8) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_0__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_0__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_0__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_0__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_1 (0x0049B8B0) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_1___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_1__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_1__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_1__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_1__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_2 (0x0049B8B8) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_2___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_2__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_2__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_2__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_2__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_3 (0x0049B8C0) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_3___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_3__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_3__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_3__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_3__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_4 (0x0049B8C8) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_4___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_4__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_4__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_4__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_4__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_5 (0x0049B8D0) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_5___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_5__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_5__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_5__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_5__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_6 (0x0049B8D8) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_6___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_6__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_6__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_6__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_6__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_7 (0x0049B8E0) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_7___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_7__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_7__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_7__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_L_B1_7__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 + +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_n(n) (0x004938AC+0x8*(n)) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_n_nMIN 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_n_nMAX 7 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_n_ELEM 8 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_n___POR 0x00000000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___POR 0x000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___POR 0x000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_n___M 0x01FF01FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_n___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_0 (0x004938AC) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_0__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_0__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_0__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_0__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_1 (0x004938B4) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_1___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_1__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_1__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_1__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_1__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_2 (0x004938BC) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_2___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_2__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_2__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_2__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_2__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_3 (0x004938C4) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_3___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_3__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_3__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_3__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_3__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_4 (0x004938CC) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_4___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_4__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_4__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_4__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_4__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_5 (0x004938D4) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_5___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_5__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_5__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_5__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_5__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_6 (0x004938DC) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_6___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_6__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_6__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_6__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_6__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_7 (0x004938E4) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_7___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_7__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_7__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_7__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B0_7__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 + +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_n(n) (0x0049B8AC+0x8*(n)) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_n_nMIN 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_n_nMAX 7 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_n_ELEM 8 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_n___POR 0x00000000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___POR 0x000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___POR 0x000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_n__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_n___M 0x01FF01FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_n___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_0 (0x0049B8AC) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_0__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_0__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_0__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_0__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_1 (0x0049B8B4) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_1___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_1__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_1__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_1__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_1__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_2 (0x0049B8BC) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_2___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_2__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_2__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_2__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_2__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_3 (0x0049B8C4) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_3___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_3__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_3__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_3__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_3__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_4 (0x0049B8CC) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_4___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_4__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_4__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_4__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_4__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_5 (0x0049B8D4) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_5___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_5__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_5__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_5__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_5__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_6 (0x0049B8DC) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_6___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_6__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_6__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_6__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_6__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_7 (0x0049B8E4) +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_7___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_7__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_7__CAL_TXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_7__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_TXIQ_CORR_SINGLETAP_COEFF_U_B1_7__CAL_TXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 + +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n(n) (0x004938E8+0x8*(n)) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n_nMIN 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n_nMAX 7 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n_ELEM 8 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n___POR 0x00000000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___POR 0x000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___POR 0x000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n___M 0x01FF01FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_0 (0x004938E8) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_0__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_0__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_0__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_0__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_1 (0x004938F0) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_1___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_1__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_1__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_1__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_1__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_2 (0x004938F8) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_2___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_2__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_2__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_2__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_2__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_3 (0x00493900) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_3___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_3__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_3__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_3__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_3__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_4 (0x00493908) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_4___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_4__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_4__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_4__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_4__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_5 (0x00493910) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_5___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_5__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_5__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_5__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_5__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_6 (0x00493918) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_6___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_6__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_6__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_6__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_6__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_7 (0x00493920) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_7___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_7__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_7__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_7__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B0_7__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 + +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n(n) (0x0049B8E8+0x8*(n)) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n_nMIN 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n_nMAX 7 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n_ELEM 8 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n___POR 0x00000000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___POR 0x000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___POR 0x000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n___M 0x01FF01FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_0 (0x0049B8E8) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_0__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_0__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_0__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_0__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_1 (0x0049B8F0) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_1___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_1__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_1__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_1__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_1__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_2 (0x0049B8F8) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_2___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_2__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_2__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_2__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_2__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_3 (0x0049B900) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_3___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_3__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_3__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_3__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_3__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_4 (0x0049B908) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_4___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_4__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_4__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_4__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_4__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_5 (0x0049B910) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_5___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_5__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_5__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_5__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_5__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_6 (0x0049B918) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_6___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_6__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_6__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_6__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_6__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_7 (0x0049B920) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_7___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_7__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_7__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_7__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_L_B1_7__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 + +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n(n) (0x004938EC+0x8*(n)) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n_nMIN 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n_nMAX 7 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n_ELEM 8 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n___POR 0x00000000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___POR 0x000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___POR 0x000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n___M 0x01FF01FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_0 (0x004938EC) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_0__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_0__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_0__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_0__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_1 (0x004938F4) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_1___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_1__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_1__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_1__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_1__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_2 (0x004938FC) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_2___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_2__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_2__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_2__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_2__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_3 (0x00493904) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_3___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_3__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_3__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_3__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_3__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_4 (0x0049390C) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_4___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_4__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_4__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_4__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_4__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_5 (0x00493914) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_5___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_5__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_5__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_5__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_5__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_6 (0x0049391C) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_6___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_6__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_6__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_6__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_6__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_7 (0x00493924) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_7___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_7__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_7__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_7__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B0_7__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 + +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n(n) (0x0049B8EC+0x8*(n)) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n_nMIN 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n_nMAX 7 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n_ELEM 8 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n___POR 0x00000000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___POR 0x000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___POR 0x000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n___M 0x01FF01FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_0 (0x0049B8EC) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_0__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_0__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_0__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_0__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_1 (0x0049B8F4) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_1___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_1__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_1__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_1__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_1__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_2 (0x0049B8FC) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_2___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_2__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_2__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_2__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_2__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_3 (0x0049B904) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_3___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_3__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_3__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_3__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_3__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_4 (0x0049B90C) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_4___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_4__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_4__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_4__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_4__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_5 (0x0049B914) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_5___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_5__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_5__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_5__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_5__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_6 (0x0049B91C) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_6___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_6__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_6__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_6__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_6__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_7 (0x0049B924) +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_7___RWC QCSR_REG_RW +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_7__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_7__DTIM_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_7__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_DTIM_RXIQ_CORR_SINGLETAP_COEFF_U_B1_7__DTIM_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 + +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B0_n(n) (0x00493928+0x8*(n)) +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B0_n_nMIN 0 +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B0_n_nMAX 0 +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B0_n_ELEM 1 +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B0_n___POR 0x00000000 +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B0_n__RXIQ_CORR_COEFF_MEM_0___POR 0x00000000 +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B0_n__RXIQ_CORR_COEFF_MEM_0___M 0xFFFFFFFF +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B0_n__RXIQ_CORR_COEFF_MEM_0___S 0 +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B0_n___M 0xFFFFFFFF +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B0_n___S 0 +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B0_0 (0x00493928) +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B0_0__RXIQ_CORR_COEFF_MEM_0___M 0xFFFFFFFF +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B0_0__RXIQ_CORR_COEFF_MEM_0___S 0 + +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B1_n(n) (0x0049B928+0x8*(n)) +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B1_n_nMIN 0 +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B1_n_nMAX 0 +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B1_n_ELEM 1 +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B1_n___POR 0x00000000 +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B1_n__RXIQ_CORR_COEFF_MEM_0___POR 0x00000000 +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B1_n__RXIQ_CORR_COEFF_MEM_0___M 0xFFFFFFFF +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B1_n__RXIQ_CORR_COEFF_MEM_0___S 0 +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B1_n___M 0xFFFFFFFF +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B1_n___S 0 +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B1_0 (0x0049B928) +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B1_0__RXIQ_CORR_COEFF_MEM_0___M 0xFFFFFFFF +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_L_B1_0__RXIQ_CORR_COEFF_MEM_0___S 0 + +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B0_n(n) (0x0049392C+0x8*(n)) +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B0_n_nMIN 0 +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B0_n_nMAX 0 +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B0_n_ELEM 1 +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B0_n___POR 0x00000000 +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B0_n__RXIQ_CORR_COEFF_MEM_1___POR 0x00000000 +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B0_n__RXIQ_CORR_COEFF_MEM_1___M 0xFFFFFFFF +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B0_n__RXIQ_CORR_COEFF_MEM_1___S 0 +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B0_n___M 0xFFFFFFFF +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B0_n___S 0 +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B0_0 (0x0049392C) +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B0_0__RXIQ_CORR_COEFF_MEM_1___M 0xFFFFFFFF +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B0_0__RXIQ_CORR_COEFF_MEM_1___S 0 + +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B1_n(n) (0x0049B92C+0x8*(n)) +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B1_n_nMIN 0 +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B1_n_nMAX 0 +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B1_n_ELEM 1 +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B1_n___POR 0x00000000 +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B1_n__RXIQ_CORR_COEFF_MEM_1___POR 0x00000000 +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B1_n__RXIQ_CORR_COEFF_MEM_1___M 0xFFFFFFFF +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B1_n__RXIQ_CORR_COEFF_MEM_1___S 0 +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B1_n___M 0xFFFFFFFF +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B1_n___S 0 +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B1_0 (0x0049B92C) +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B1_0__RXIQ_CORR_COEFF_MEM_1___M 0xFFFFFFFF +#define PHYA_PHYRF_RXIQ_CORR_COEFF_MEM_U_B1_0__RXIQ_CORR_COEFF_MEM_1___S 0 + +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n(n) (0x00494328+0x8*(n)) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n_nMIN 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n_nMAX 7 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n_ELEM 8 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n___POR 0x00000000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___POR 0x000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___POR 0x000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n___M 0x01FF01FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_n___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_0 (0x00494328) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_0__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_0__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_0__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_0__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_1 (0x00494330) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_1___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_1__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_1__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_1__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_1__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_2 (0x00494338) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_2___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_2__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_2__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_2__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_2__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_3 (0x00494340) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_3___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_3__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_3__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_3__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_3__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_4 (0x00494348) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_4___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_4__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_4__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_4__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_4__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_5 (0x00494350) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_5___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_5__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_5__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_5__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_5__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_6 (0x00494358) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_6___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_6__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_6__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_6__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_6__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_7 (0x00494360) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_7___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_7__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_7__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_7__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B0_7__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 + +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n(n) (0x0049C328+0x8*(n)) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n_nMIN 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n_nMAX 7 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n_ELEM 8 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n___POR 0x00000000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___POR 0x000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___POR 0x000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n___M 0x01FF01FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_n___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_0 (0x0049C328) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_0__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_0__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_0__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_0__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_1 (0x0049C330) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_1___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_1__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_1__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_1__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_1__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_2 (0x0049C338) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_2___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_2__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_2__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_2__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_2__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_3 (0x0049C340) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_3___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_3__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_3__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_3__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_3__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_4 (0x0049C348) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_4___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_4__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_4__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_4__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_4__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_5 (0x0049C350) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_5___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_5__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_5__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_5__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_5__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_6 (0x0049C358) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_6___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_6__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_6__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_6__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_6__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_7 (0x0049C360) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_7___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_7__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_7__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_EVEN___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_7__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_L_B1_7__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_EVEN___S 0 + +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n(n) (0x0049432C+0x8*(n)) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n_nMIN 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n_nMAX 7 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n_ELEM 8 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n___POR 0x00000000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___POR 0x000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___POR 0x000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n___M 0x01FF01FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_n___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_0 (0x0049432C) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_0__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_0__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_0__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_0__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_1 (0x00494334) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_1___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_1__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_1__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_1__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_1__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_2 (0x0049433C) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_2___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_2__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_2__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_2__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_2__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_3 (0x00494344) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_3___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_3__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_3__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_3__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_3__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_4 (0x0049434C) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_4___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_4__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_4__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_4__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_4__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_5 (0x00494354) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_5___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_5__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_5__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_5__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_5__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_6 (0x0049435C) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_6___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_6__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_6__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_6__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_6__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_7 (0x00494364) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_7___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_7__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_7__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_7__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B0_7__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 + +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n(n) (0x0049C32C+0x8*(n)) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n_nMIN 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n_nMAX 7 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n_ELEM 8 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n___POR 0x00000000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___POR 0x000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___POR 0x000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n___M 0x01FF01FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_n___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_0 (0x0049C32C) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_0__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_0__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_0__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_0__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_1 (0x0049C334) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_1___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_1__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_1__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_1__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_1__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_2 (0x0049C33C) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_2___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_2__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_2__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_2__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_2__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_3 (0x0049C344) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_3___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_3__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_3__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_3__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_3__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_4 (0x0049C34C) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_4___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_4__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_4__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_4__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_4__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_5 (0x0049C354) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_5___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_5__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_5__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_5__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_5__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_6 (0x0049C35C) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_6___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_6__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_6__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_6__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_6__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_7 (0x0049C364) +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_7___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_7__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___M 0x01FF0000 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_7__CAL_RXIQ_CORR_SINGLETAP_COEFF_Q_ODD___S 16 +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_7__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___M 0x000001FF +#define PHYA_PHYRF_CAL_RXIQ_CORR_SINGLETAP_COEFF_U_B1_7__CAL_RXIQ_CORR_SINGLETAP_COEFF_I_ODD___S 0 + +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B0 (0x00494368) +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B0___POR 0x00000000 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B0__POWER_OFFSET_OFDM160___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B0__POWER_OFFSET_OFDM80___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B0__POWER_OFFSET_OFDM40___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B0__POWER_OFFSET_OFDM20___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B0__POWER_OFFSET_OFDM160___M 0xFF000000 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B0__POWER_OFFSET_OFDM160___S 24 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B0__POWER_OFFSET_OFDM80___M 0x00FF0000 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B0__POWER_OFFSET_OFDM80___S 16 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B0__POWER_OFFSET_OFDM40___M 0x0000FF00 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B0__POWER_OFFSET_OFDM40___S 8 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B0__POWER_OFFSET_OFDM20___M 0x000000FF +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B0__POWER_OFFSET_OFDM20___S 0 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B0___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B0___S 0 + +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B1 (0x0049C368) +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B1___POR 0x00000000 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B1__POWER_OFFSET_OFDM160___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B1__POWER_OFFSET_OFDM80___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B1__POWER_OFFSET_OFDM40___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B1__POWER_OFFSET_OFDM20___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B1__POWER_OFFSET_OFDM160___M 0xFF000000 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B1__POWER_OFFSET_OFDM160___S 24 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B1__POWER_OFFSET_OFDM80___M 0x00FF0000 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B1__POWER_OFFSET_OFDM80___S 16 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B1__POWER_OFFSET_OFDM40___M 0x0000FF00 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B1__POWER_OFFSET_OFDM40___S 8 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B1__POWER_OFFSET_OFDM20___M 0x000000FF +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B1__POWER_OFFSET_OFDM20___S 0 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B1___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_L_B1___S 0 + +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B0 (0x0049436C) +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B0___POR 0x00000000 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B0__POWER_OFFSET_OFDM160_HC___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B0__POWER_OFFSET_OFDM80_HC___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B0__POWER_OFFSET_OFDM40_HC___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B0__POWER_OFFSET_OFDM20_HC___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B0__POWER_OFFSET_OFDM160_HC___M 0xFF000000 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B0__POWER_OFFSET_OFDM160_HC___S 24 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B0__POWER_OFFSET_OFDM80_HC___M 0x00FF0000 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B0__POWER_OFFSET_OFDM80_HC___S 16 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B0__POWER_OFFSET_OFDM40_HC___M 0x0000FF00 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B0__POWER_OFFSET_OFDM40_HC___S 8 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B0__POWER_OFFSET_OFDM20_HC___M 0x000000FF +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B0__POWER_OFFSET_OFDM20_HC___S 0 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B0___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B0___S 0 + +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B1 (0x0049C36C) +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B1___POR 0x00000000 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B1__POWER_OFFSET_OFDM160_HC___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B1__POWER_OFFSET_OFDM80_HC___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B1__POWER_OFFSET_OFDM40_HC___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B1__POWER_OFFSET_OFDM20_HC___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B1__POWER_OFFSET_OFDM160_HC___M 0xFF000000 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B1__POWER_OFFSET_OFDM160_HC___S 24 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B1__POWER_OFFSET_OFDM80_HC___M 0x00FF0000 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B1__POWER_OFFSET_OFDM80_HC___S 16 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B1__POWER_OFFSET_OFDM40_HC___M 0x0000FF00 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B1__POWER_OFFSET_OFDM40_HC___S 8 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B1__POWER_OFFSET_OFDM20_HC___M 0x000000FF +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B1__POWER_OFFSET_OFDM20_HC___S 0 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B1___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_BANDWIDTH_U_B1___S 0 + +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B0 (0x00494370) +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B0___POR 0x00000000 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B0__PWR_OFST_OFDM_HIGHMCS___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B0__PWR_OFST_OFDM_MIDMCS___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B0__PWR_OFST_OFDM_LOWMCS___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B0__PWR_OFST_CCK___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B0__PWR_OFST_OFDM_HIGHMCS___M 0xFF000000 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B0__PWR_OFST_OFDM_HIGHMCS___S 24 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B0__PWR_OFST_OFDM_MIDMCS___M 0x00FF0000 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B0__PWR_OFST_OFDM_MIDMCS___S 16 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B0__PWR_OFST_OFDM_LOWMCS___M 0x0000FF00 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B0__PWR_OFST_OFDM_LOWMCS___S 8 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B0__PWR_OFST_CCK___M 0x000000FF +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B0__PWR_OFST_CCK___S 0 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B0___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B0___S 0 + +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B1 (0x0049C370) +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B1___POR 0x00000000 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B1__PWR_OFST_OFDM_HIGHMCS___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B1__PWR_OFST_OFDM_MIDMCS___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B1__PWR_OFST_OFDM_LOWMCS___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B1__PWR_OFST_CCK___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B1__PWR_OFST_OFDM_HIGHMCS___M 0xFF000000 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B1__PWR_OFST_OFDM_HIGHMCS___S 24 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B1__PWR_OFST_OFDM_MIDMCS___M 0x00FF0000 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B1__PWR_OFST_OFDM_MIDMCS___S 16 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B1__PWR_OFST_OFDM_LOWMCS___M 0x0000FF00 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B1__PWR_OFST_OFDM_LOWMCS___S 8 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B1__PWR_OFST_CCK___M 0x000000FF +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B1__PWR_OFST_CCK___S 0 +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B1___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_CHN_POWER_OFFSET_RATE_L_B1___S 0 + +#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B0 (0x00494378) +#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B0___POR 0x00000000 +#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B0__ALPHA_VOLT___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B0__ALPHA_THERM___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B0__VOLT_CAL_VALUE___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B0__THERM_CAL_VALUE___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B0__ALPHA_VOLT___M 0x7F000000 +#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B0__ALPHA_VOLT___S 24 +#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B0__ALPHA_THERM___M 0x00FF0000 +#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B0__ALPHA_THERM___S 16 +#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B0__VOLT_CAL_VALUE___M 0x0000FF00 +#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B0__VOLT_CAL_VALUE___S 8 +#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B0__THERM_CAL_VALUE___M 0x000000FF +#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B0__THERM_CAL_VALUE___S 0 +#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B0___M 0x7FFFFFFF +#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B0___S 0 + +#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B1 (0x0049C378) +#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B1___POR 0x00000000 +#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B1__ALPHA_VOLT___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B1__ALPHA_THERM___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B1__VOLT_CAL_VALUE___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B1__THERM_CAL_VALUE___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B1__ALPHA_VOLT___M 0x7F000000 +#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B1__ALPHA_VOLT___S 24 +#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B1__ALPHA_THERM___M 0x00FF0000 +#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B1__ALPHA_THERM___S 16 +#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B1__VOLT_CAL_VALUE___M 0x0000FF00 +#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B1__VOLT_CAL_VALUE___S 8 +#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B1__THERM_CAL_VALUE___M 0x000000FF +#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B1__THERM_CAL_VALUE___S 0 +#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B1___M 0x7FFFFFFF +#define PHYA_PHYRF_TPC_CHN_OLPC_CAL_SETTING_L_B1___S 0 + +#define PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B0 (0x00494380) +#define PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B0___POR 0x00000000 +#define PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B0__TPC_INIT_VOLT_SETTING___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B0__TPC_INIT_THERM_SETTING___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B0__TPC_INIT_VOLT_SETTING___M 0x0000FF00 +#define PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B0__TPC_INIT_VOLT_SETTING___S 8 +#define PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B0__TPC_INIT_THERM_SETTING___M 0x000000FF +#define PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B0__TPC_INIT_THERM_SETTING___S 0 +#define PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B0___M 0x0000FFFF +#define PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B0___S 0 + +#define PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B1 (0x0049C380) +#define PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B1___POR 0x00000000 +#define PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B1__TPC_INIT_VOLT_SETTING___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B1__TPC_INIT_THERM_SETTING___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B1__TPC_INIT_VOLT_SETTING___M 0x0000FF00 +#define PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B1__TPC_INIT_VOLT_SETTING___S 8 +#define PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B1__TPC_INIT_THERM_SETTING___M 0x000000FF +#define PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B1__TPC_INIT_THERM_SETTING___S 0 +#define PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B1___M 0x0000FFFF +#define PHYA_PHYRF_TPC_CHN_OLPC_INIT_SETTING_L_B1___S 0 + +#define PHYA_PHYRF_TPC_CHN_BTCOEX_CTRL_L_B0 (0x00494388) +#define PHYA_PHYRF_TPC_CHN_BTCOEX_CTRL_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_CHN_BTCOEX_CTRL_L_B0___POR 0x00000000 +#define PHYA_PHYRF_TPC_CHN_BTCOEX_CTRL_L_B0__BT_CLPC_ERR_UPDT___POR 0x0 +#define PHYA_PHYRF_TPC_CHN_BTCOEX_CTRL_L_B0__BT_CLPC_ERR_UPDT___M 0x00000001 +#define PHYA_PHYRF_TPC_CHN_BTCOEX_CTRL_L_B0__BT_CLPC_ERR_UPDT___S 0 +#define PHYA_PHYRF_TPC_CHN_BTCOEX_CTRL_L_B0___M 0x00000001 +#define PHYA_PHYRF_TPC_CHN_BTCOEX_CTRL_L_B0___S 0 + +#define PHYA_PHYRF_TPC_CHN_BTCOEX_CTRL_L_B1 (0x0049C388) +#define PHYA_PHYRF_TPC_CHN_BTCOEX_CTRL_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_CHN_BTCOEX_CTRL_L_B1___POR 0x00000000 +#define PHYA_PHYRF_TPC_CHN_BTCOEX_CTRL_L_B1__BT_CLPC_ERR_UPDT___POR 0x0 +#define PHYA_PHYRF_TPC_CHN_BTCOEX_CTRL_L_B1__BT_CLPC_ERR_UPDT___M 0x00000001 +#define PHYA_PHYRF_TPC_CHN_BTCOEX_CTRL_L_B1__BT_CLPC_ERR_UPDT___S 0 +#define PHYA_PHYRF_TPC_CHN_BTCOEX_CTRL_L_B1___M 0x00000001 +#define PHYA_PHYRF_TPC_CHN_BTCOEX_CTRL_L_B1___S 0 + +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0 (0x00494390) +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0___POR 0x00000000 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCED_DAC_GAIN___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCED_TXGAIN_IDX___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCED_OLPC_VOLT_INPUT___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCE_OLPC_VOLT_INPUT___POR 0x0 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCED_OLPC_THERM_INPUT___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCE_OLPC_THERM_INPUT___POR 0x0 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCED_DAC_GAIN___M 0xFF000000 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCED_DAC_GAIN___S 24 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCED_TXGAIN_IDX___M 0x00FC0000 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCED_TXGAIN_IDX___S 18 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCED_OLPC_VOLT_INPUT___M 0x0003FC00 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCED_OLPC_VOLT_INPUT___S 10 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCE_OLPC_VOLT_INPUT___M 0x00000200 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCE_OLPC_VOLT_INPUT___S 9 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCED_OLPC_THERM_INPUT___M 0x000001FE +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCED_OLPC_THERM_INPUT___S 1 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCE_OLPC_THERM_INPUT___M 0x00000001 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0__FORCE_OLPC_THERM_INPUT___S 0 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B0___S 0 + +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1 (0x0049C390) +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1___POR 0x00000000 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCED_DAC_GAIN___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCED_TXGAIN_IDX___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCED_OLPC_VOLT_INPUT___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCE_OLPC_VOLT_INPUT___POR 0x0 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCED_OLPC_THERM_INPUT___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCE_OLPC_THERM_INPUT___POR 0x0 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCED_DAC_GAIN___M 0xFF000000 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCED_DAC_GAIN___S 24 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCED_TXGAIN_IDX___M 0x00FC0000 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCED_TXGAIN_IDX___S 18 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCED_OLPC_VOLT_INPUT___M 0x0003FC00 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCED_OLPC_VOLT_INPUT___S 10 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCE_OLPC_VOLT_INPUT___M 0x00000200 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCE_OLPC_VOLT_INPUT___S 9 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCED_OLPC_THERM_INPUT___M 0x000001FE +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCED_OLPC_THERM_INPUT___S 1 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCE_OLPC_THERM_INPUT___M 0x00000001 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1__FORCE_OLPC_THERM_INPUT___S 0 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1___M 0xFFFFFFFF +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_L_B1___S 0 + +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B0 (0x00494394) +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B0___POR 0x00000000 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B0__FORCED_TXCAL_LO_INDEX___POR 0x0 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B0__FORCED_TXCAL_GAIN_INDEX___POR 0x0 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B0__FORCED_TXCAL_LO_INDEX___M 0x000000F0 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B0__FORCED_TXCAL_LO_INDEX___S 4 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B0__FORCED_TXCAL_GAIN_INDEX___M 0x0000000F +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B0__FORCED_TXCAL_GAIN_INDEX___S 0 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B0___M 0x000000FF +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B0___S 0 + +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B1 (0x0049C394) +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B1___POR 0x00000000 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B1__FORCED_TXCAL_LO_INDEX___POR 0x0 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B1__FORCED_TXCAL_GAIN_INDEX___POR 0x0 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B1__FORCED_TXCAL_LO_INDEX___M 0x000000F0 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B1__FORCED_TXCAL_LO_INDEX___S 4 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B1__FORCED_TXCAL_GAIN_INDEX___M 0x0000000F +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B1__FORCED_TXCAL_GAIN_INDEX___S 0 +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B1___M 0x000000FF +#define PHYA_PHYRF_TPC_CHN_FORCE_CTRL_U_B1___S 0 + +#define PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B0 (0x00494398) +#define PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B0___POR 0x00000000 +#define PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B0__GAIN_MISS_MID___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B0__GAIN_MISS_HIGH___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B0__GAIN_MISS_LOW___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B0__GAIN_MISS_MID___M 0x00FF0000 +#define PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B0__GAIN_MISS_MID___S 16 +#define PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B0__GAIN_MISS_HIGH___M 0x0000FF00 +#define PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B0__GAIN_MISS_HIGH___S 8 +#define PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B0__GAIN_MISS_LOW___M 0x000000FF +#define PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B0__GAIN_MISS_LOW___S 0 +#define PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B0___M 0x00FFFFFF +#define PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B0___S 0 + +#define PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B1 (0x0049C398) +#define PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B1___POR 0x00000000 +#define PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B1__GAIN_MISS_MID___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B1__GAIN_MISS_HIGH___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B1__GAIN_MISS_LOW___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B1__GAIN_MISS_MID___M 0x00FF0000 +#define PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B1__GAIN_MISS_MID___S 16 +#define PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B1__GAIN_MISS_HIGH___M 0x0000FF00 +#define PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B1__GAIN_MISS_HIGH___S 8 +#define PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B1__GAIN_MISS_LOW___M 0x000000FF +#define PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B1__GAIN_MISS_LOW___S 0 +#define PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B1___M 0x00FFFFFF +#define PHYA_PHYRF_TPC_CHN_STAT_GAIN_MISS_COUNT_L_B1___S 0 + +#define PHYA_PHYRF_TPC_CHN_MU_L_B0 (0x004943A0) +#define PHYA_PHYRF_TPC_CHN_MU_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_CHN_MU_L_B0___POR 0x00000000 +#define PHYA_PHYRF_TPC_CHN_MU_L_B0__TPC_ERR_MU___POR 0x000 +#define PHYA_PHYRF_TPC_CHN_MU_L_B0__DAC_GAIN_NDP___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_MU_L_B0__GLUT_IDX_NDP___POR 0x0 +#define PHYA_PHYRF_TPC_CHN_MU_L_B0__TPC_ERR_MU___M 0x003FF000 +#define PHYA_PHYRF_TPC_CHN_MU_L_B0__TPC_ERR_MU___S 12 +#define PHYA_PHYRF_TPC_CHN_MU_L_B0__DAC_GAIN_NDP___M 0x00000FF0 +#define PHYA_PHYRF_TPC_CHN_MU_L_B0__DAC_GAIN_NDP___S 4 +#define PHYA_PHYRF_TPC_CHN_MU_L_B0__GLUT_IDX_NDP___M 0x0000000F +#define PHYA_PHYRF_TPC_CHN_MU_L_B0__GLUT_IDX_NDP___S 0 +#define PHYA_PHYRF_TPC_CHN_MU_L_B0___M 0x003FFFFF +#define PHYA_PHYRF_TPC_CHN_MU_L_B0___S 0 + +#define PHYA_PHYRF_TPC_CHN_MU_L_B1 (0x0049C3A0) +#define PHYA_PHYRF_TPC_CHN_MU_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_CHN_MU_L_B1___POR 0x00000000 +#define PHYA_PHYRF_TPC_CHN_MU_L_B1__TPC_ERR_MU___POR 0x000 +#define PHYA_PHYRF_TPC_CHN_MU_L_B1__DAC_GAIN_NDP___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_MU_L_B1__GLUT_IDX_NDP___POR 0x0 +#define PHYA_PHYRF_TPC_CHN_MU_L_B1__TPC_ERR_MU___M 0x003FF000 +#define PHYA_PHYRF_TPC_CHN_MU_L_B1__TPC_ERR_MU___S 12 +#define PHYA_PHYRF_TPC_CHN_MU_L_B1__DAC_GAIN_NDP___M 0x00000FF0 +#define PHYA_PHYRF_TPC_CHN_MU_L_B1__DAC_GAIN_NDP___S 4 +#define PHYA_PHYRF_TPC_CHN_MU_L_B1__GLUT_IDX_NDP___M 0x0000000F +#define PHYA_PHYRF_TPC_CHN_MU_L_B1__GLUT_IDX_NDP___S 0 +#define PHYA_PHYRF_TPC_CHN_MU_L_B1___M 0x003FFFFF +#define PHYA_PHYRF_TPC_CHN_MU_L_B1___S 0 + +#define PHYA_PHYRF_TPC_CHN_MAX_TARGET_PWR_L_B0 (0x004943A8) +#define PHYA_PHYRF_TPC_CHN_MAX_TARGET_PWR_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_CHN_MAX_TARGET_PWR_L_B0___POR 0x0000007F +#define PHYA_PHYRF_TPC_CHN_MAX_TARGET_PWR_L_B0__PER_CHAIN_MAX_TARGET_PWR___POR 0x7F +#define PHYA_PHYRF_TPC_CHN_MAX_TARGET_PWR_L_B0__PER_CHAIN_MAX_TARGET_PWR___M 0x000000FF +#define PHYA_PHYRF_TPC_CHN_MAX_TARGET_PWR_L_B0__PER_CHAIN_MAX_TARGET_PWR___S 0 +#define PHYA_PHYRF_TPC_CHN_MAX_TARGET_PWR_L_B0___M 0x000000FF +#define PHYA_PHYRF_TPC_CHN_MAX_TARGET_PWR_L_B0___S 0 + +#define PHYA_PHYRF_TPC_CHN_MAX_TARGET_PWR_L_B1 (0x0049C3A8) +#define PHYA_PHYRF_TPC_CHN_MAX_TARGET_PWR_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPC_CHN_MAX_TARGET_PWR_L_B1___POR 0x0000007F +#define PHYA_PHYRF_TPC_CHN_MAX_TARGET_PWR_L_B1__PER_CHAIN_MAX_TARGET_PWR___POR 0x7F +#define PHYA_PHYRF_TPC_CHN_MAX_TARGET_PWR_L_B1__PER_CHAIN_MAX_TARGET_PWR___M 0x000000FF +#define PHYA_PHYRF_TPC_CHN_MAX_TARGET_PWR_L_B1__PER_CHAIN_MAX_TARGET_PWR___S 0 +#define PHYA_PHYRF_TPC_CHN_MAX_TARGET_PWR_L_B1___M 0x000000FF +#define PHYA_PHYRF_TPC_CHN_MAX_TARGET_PWR_L_B1___S 0 + +#define PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B0 (0x004943B0) +#define PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B0___RWC QCSR_REG_RO +#define PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B0___POR 0x00000000 +#define PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B0__TPC_SELF_CAL_TARGET_PWR___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B0__TPC_SELF_CAL_CLPC_ERR___POR 0x000 +#define PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B0__TPC_SELF_CAL_MEAS_PWR___POR 0x000 +#define PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B0__TPC_SELF_CAL_TARGET_PWR___M 0x07F80000 +#define PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B0__TPC_SELF_CAL_TARGET_PWR___S 19 +#define PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B0__TPC_SELF_CAL_CLPC_ERR___M 0x0007FE00 +#define PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B0__TPC_SELF_CAL_CLPC_ERR___S 9 +#define PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B0__TPC_SELF_CAL_MEAS_PWR___M 0x000001FF +#define PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B0__TPC_SELF_CAL_MEAS_PWR___S 0 +#define PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B0___M 0x07FFFFFF +#define PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B0___S 0 + +#define PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B1 (0x0049C3B0) +#define PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B1___RWC QCSR_REG_RO +#define PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B1___POR 0x00000000 +#define PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B1__TPC_SELF_CAL_TARGET_PWR___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B1__TPC_SELF_CAL_CLPC_ERR___POR 0x000 +#define PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B1__TPC_SELF_CAL_MEAS_PWR___POR 0x000 +#define PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B1__TPC_SELF_CAL_TARGET_PWR___M 0x07F80000 +#define PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B1__TPC_SELF_CAL_TARGET_PWR___S 19 +#define PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B1__TPC_SELF_CAL_CLPC_ERR___M 0x0007FE00 +#define PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B1__TPC_SELF_CAL_CLPC_ERR___S 9 +#define PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B1__TPC_SELF_CAL_MEAS_PWR___M 0x000001FF +#define PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B1__TPC_SELF_CAL_MEAS_PWR___S 0 +#define PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B1___M 0x07FFFFFF +#define PHYA_PHYRF_TPC_CHN_STAT_SELF_CAL_L_B1___S 0 + +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0 (0x004943B8) +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0___RWC QCSR_REG_RO +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0___POR 0x00000000 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0__LATEST_TX_IQ_IDX___POR 0x0 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0__LATEST_GLUT_IDX___POR 0x0 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0__LATEST_TXGAIN_IDX___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0__LATEST_DAC_GAIN___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0__LATEST_TARGET_PWR___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0__LATEST_TX_IQ_IDX___M 0x3C000000 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0__LATEST_TX_IQ_IDX___S 26 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0__LATEST_GLUT_IDX___M 0x03C00000 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0__LATEST_GLUT_IDX___S 22 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0__LATEST_TXGAIN_IDX___M 0x003F0000 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0__LATEST_TXGAIN_IDX___S 16 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0__LATEST_DAC_GAIN___M 0x0000FF00 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0__LATEST_DAC_GAIN___S 8 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0__LATEST_TARGET_PWR___M 0x000000FF +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0__LATEST_TARGET_PWR___S 0 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0___M 0x3FFFFFFF +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B0___S 0 + +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1 (0x0049C3B8) +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1___RWC QCSR_REG_RO +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1___POR 0x00000000 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1__LATEST_TX_IQ_IDX___POR 0x0 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1__LATEST_GLUT_IDX___POR 0x0 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1__LATEST_TXGAIN_IDX___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1__LATEST_DAC_GAIN___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1__LATEST_TARGET_PWR___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1__LATEST_TX_IQ_IDX___M 0x3C000000 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1__LATEST_TX_IQ_IDX___S 26 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1__LATEST_GLUT_IDX___M 0x03C00000 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1__LATEST_GLUT_IDX___S 22 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1__LATEST_TXGAIN_IDX___M 0x003F0000 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1__LATEST_TXGAIN_IDX___S 16 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1__LATEST_DAC_GAIN___M 0x0000FF00 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1__LATEST_DAC_GAIN___S 8 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1__LATEST_TARGET_PWR___M 0x000000FF +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1__LATEST_TARGET_PWR___S 0 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1___M 0x3FFFFFFF +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_L_B1___S 0 + +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B0 (0x004943BC) +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B0___RWC QCSR_REG_RO +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B0___POR 0x00000000 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B0__LATEST_TXCAL_GAIN_DELTA___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B0__LATEST_TX_LO_IDX___POR 0x0 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B0__LATEST_TXCAL_GAIN_DELTA___M 0x000003F0 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B0__LATEST_TXCAL_GAIN_DELTA___S 4 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B0__LATEST_TX_LO_IDX___M 0x0000000F +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B0__LATEST_TX_LO_IDX___S 0 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B0___M 0x000003FF +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B0___S 0 + +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B1 (0x0049C3BC) +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B1___RWC QCSR_REG_RO +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B1___POR 0x00000000 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B1__LATEST_TXCAL_GAIN_DELTA___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B1__LATEST_TX_LO_IDX___POR 0x0 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B1__LATEST_TXCAL_GAIN_DELTA___M 0x000003F0 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B1__LATEST_TXCAL_GAIN_DELTA___S 4 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B1__LATEST_TX_LO_IDX___M 0x0000000F +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B1__LATEST_TX_LO_IDX___S 0 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B1___M 0x000003FF +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_FWD_U_B1___S 0 + +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B0 (0x004943C0) +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B0___RWC QCSR_REG_RO +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B0___POR 0x00000000 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B0__LATEST_ACCUMULATED_CLPC_ERR___POR 0x000 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B0__LATEST_CLPC_ERR___POR 0x000 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B0__LATEST_MEAS_PWR_OUT___POR 0x000 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B0__LATEST_ACCUMULATED_CLPC_ERR___M 0x1FF80000 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B0__LATEST_ACCUMULATED_CLPC_ERR___S 19 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B0__LATEST_CLPC_ERR___M 0x0007FE00 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B0__LATEST_CLPC_ERR___S 9 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B0__LATEST_MEAS_PWR_OUT___M 0x000001FF +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B0__LATEST_MEAS_PWR_OUT___S 0 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B0___M 0x1FFFFFFF +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B0___S 0 + +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B1 (0x0049C3C0) +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B1___RWC QCSR_REG_RO +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B1___POR 0x00000000 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B1__LATEST_ACCUMULATED_CLPC_ERR___POR 0x000 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B1__LATEST_CLPC_ERR___POR 0x000 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B1__LATEST_MEAS_PWR_OUT___POR 0x000 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B1__LATEST_ACCUMULATED_CLPC_ERR___M 0x1FF80000 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B1__LATEST_ACCUMULATED_CLPC_ERR___S 19 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B1__LATEST_CLPC_ERR___M 0x0007FE00 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B1__LATEST_CLPC_ERR___S 9 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B1__LATEST_MEAS_PWR_OUT___M 0x000001FF +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B1__LATEST_MEAS_PWR_OUT___S 0 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B1___M 0x1FFFFFFF +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_LB_L_B1___S 0 + +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0 (0x004943C8) +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0___RWC QCSR_REG_RO +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0___POR 0x00000000 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0__LATEST_WSI_VHT160_MODE___POR 0x0 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0__LATEST_WSI_TX_GAIN_IDX___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0__LATEST_WSI_CLPC_PKT_TYPE___POR 0x0 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0__LATEST_WSI_TPC_PDET_GAIN_IDX___POR 0x0 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0__LATEST_WSI_TPC_ATTEN___POR 0x0 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0__LATEST_WSI_VHT160_MODE___M 0x00003000 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0__LATEST_WSI_VHT160_MODE___S 12 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0__LATEST_WSI_TX_GAIN_IDX___M 0x00000FC0 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0__LATEST_WSI_TX_GAIN_IDX___S 6 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0__LATEST_WSI_CLPC_PKT_TYPE___M 0x00000020 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0__LATEST_WSI_CLPC_PKT_TYPE___S 5 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0__LATEST_WSI_TPC_PDET_GAIN_IDX___M 0x00000010 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0__LATEST_WSI_TPC_PDET_GAIN_IDX___S 4 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0__LATEST_WSI_TPC_ATTEN___M 0x0000000F +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0__LATEST_WSI_TPC_ATTEN___S 0 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0___M 0x00003FFF +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B0___S 0 + +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1 (0x0049C3C8) +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1___RWC QCSR_REG_RO +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1___POR 0x00000000 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1__LATEST_WSI_VHT160_MODE___POR 0x0 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1__LATEST_WSI_TX_GAIN_IDX___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1__LATEST_WSI_CLPC_PKT_TYPE___POR 0x0 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1__LATEST_WSI_TPC_PDET_GAIN_IDX___POR 0x0 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1__LATEST_WSI_TPC_ATTEN___POR 0x0 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1__LATEST_WSI_VHT160_MODE___M 0x00003000 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1__LATEST_WSI_VHT160_MODE___S 12 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1__LATEST_WSI_TX_GAIN_IDX___M 0x00000FC0 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1__LATEST_WSI_TX_GAIN_IDX___S 6 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1__LATEST_WSI_CLPC_PKT_TYPE___M 0x00000020 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1__LATEST_WSI_CLPC_PKT_TYPE___S 5 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1__LATEST_WSI_TPC_PDET_GAIN_IDX___M 0x00000010 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1__LATEST_WSI_TPC_PDET_GAIN_IDX___S 4 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1__LATEST_WSI_TPC_ATTEN___M 0x0000000F +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1__LATEST_WSI_TPC_ATTEN___S 0 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1___M 0x00003FFF +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_TXGAIN_L_B1___S 0 + +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0 (0x004943D0) +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0___RWC QCSR_REG_RO +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0___POR 0x00000000 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_TEMP_VALID___POR 0x0 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_FULLPKT_PWR_VALID___POR 0x0 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_PREAMBLE_PWR_VALID___POR 0x0 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_TEMP___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_FULLPKT_PWR___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_PREAMBLE_PWR___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_TEMP_VALID___M 0x04000000 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_TEMP_VALID___S 26 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_FULLPKT_PWR_VALID___M 0x02000000 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_FULLPKT_PWR_VALID___S 25 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_PREAMBLE_PWR_VALID___M 0x01000000 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_PREAMBLE_PWR_VALID___S 24 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_TEMP___M 0x00FF0000 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_TEMP___S 16 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_FULLPKT_PWR___M 0x0000FF00 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_FULLPKT_PWR___S 8 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_PREAMBLE_PWR___M 0x000000FF +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0__LATEST_WSI_PREAMBLE_PWR___S 0 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0___M 0x07FFFFFF +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B0___S 0 + +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1 (0x0049C3D0) +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1___RWC QCSR_REG_RO +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1___POR 0x00000000 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_TEMP_VALID___POR 0x0 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_FULLPKT_PWR_VALID___POR 0x0 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_PREAMBLE_PWR_VALID___POR 0x0 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_TEMP___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_FULLPKT_PWR___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_PREAMBLE_PWR___POR 0x00 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_TEMP_VALID___M 0x04000000 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_TEMP_VALID___S 26 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_FULLPKT_PWR_VALID___M 0x02000000 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_FULLPKT_PWR_VALID___S 25 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_PREAMBLE_PWR_VALID___M 0x01000000 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_PREAMBLE_PWR_VALID___S 24 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_TEMP___M 0x00FF0000 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_TEMP___S 16 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_FULLPKT_PWR___M 0x0000FF00 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_FULLPKT_PWR___S 8 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_PREAMBLE_PWR___M 0x000000FF +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1__LATEST_WSI_PREAMBLE_PWR___S 0 +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1___M 0x07FFFFFF +#define PHYA_PHYRF_TPC_CHN_STAT_LATEST_READBACK_L_B1___S 0 + +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B0_n(n) (0x004943D8+0x8*(n)) +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B0_n_nMIN 0 +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B0_n_nMAX 0 +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B0_n_ELEM 1 +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B0_n___POR 0x00000000 +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B0_n__RESDC_0___POR 0x00000000 +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B0_n__RESDC_0___M 0xFFFFFFFF +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B0_n__RESDC_0___S 0 +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B0_n___M 0xFFFFFFFF +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B0_n___S 0 +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B0_0 (0x004943D8) +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B0_0__RESDC_0___M 0xFFFFFFFF +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B0_0__RESDC_0___S 0 + +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B1_n(n) (0x0049C3D8+0x8*(n)) +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B1_n_nMIN 0 +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B1_n_nMAX 0 +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B1_n_ELEM 1 +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B1_n___POR 0x00000000 +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B1_n__RESDC_0___POR 0x00000000 +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B1_n__RESDC_0___M 0xFFFFFFFF +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B1_n__RESDC_0___S 0 +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B1_n___M 0xFFFFFFFF +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B1_n___S 0 +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B1_0 (0x0049C3D8) +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B1_0__RESDC_0___M 0xFFFFFFFF +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_L_B1_0__RESDC_0___S 0 + +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B0_n(n) (0x004943DC+0x8*(n)) +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B0_n_nMIN 0 +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B0_n_nMAX 0 +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B0_n_ELEM 1 +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B0_n___POR 0x00000000 +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B0_n__RESDC_1___POR 0x00000000 +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B0_n__RESDC_1___M 0xFFFFFFFF +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B0_n__RESDC_1___S 0 +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B0_n___M 0xFFFFFFFF +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B0_n___S 0 +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B0_0 (0x004943DC) +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B0_0__RESDC_1___M 0xFFFFFFFF +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B0_0__RESDC_1___S 0 + +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B1_n(n) (0x0049C3DC+0x8*(n)) +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B1_n_nMIN 0 +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B1_n_nMAX 0 +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B1_n_ELEM 1 +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B1_n___POR 0x00000000 +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B1_n__RESDC_1___POR 0x00000000 +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B1_n__RESDC_1___M 0xFFFFFFFF +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B1_n__RESDC_1___S 0 +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B1_n___M 0xFFFFFFFF +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B1_n___S 0 +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B1_0 (0x0049C3DC) +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B1_0__RESDC_1___M 0xFFFFFFFF +#define PHYA_PHYRF_RXGAIN_IND_TAB_0_U_B1_0__RESDC_1___S 0 + +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B0_n(n) (0x00494BD8+0x8*(n)) +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B0_n_nMIN 0 +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B0_n_nMAX 0 +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B0_n_ELEM 1 +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B0_n___POR 0x00000000 +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B0_n__XLNA_RXIQCORR_0___POR 0x000000 +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B0_n__XLNA_RXIQCORR_0___M 0x00FFFFFF +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B0_n__XLNA_RXIQCORR_0___S 0 +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B0_n___M 0x00FFFFFF +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B0_n___S 0 +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B0_0 (0x00494BD8) +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B0_0__XLNA_RXIQCORR_0___M 0x00FFFFFF +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B0_0__XLNA_RXIQCORR_0___S 0 + +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B1_n(n) (0x0049CBD8+0x8*(n)) +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B1_n_nMIN 0 +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B1_n_nMAX 0 +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B1_n_ELEM 1 +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B1_n___POR 0x00000000 +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B1_n__XLNA_RXIQCORR_0___POR 0x000000 +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B1_n__XLNA_RXIQCORR_0___M 0x00FFFFFF +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B1_n__XLNA_RXIQCORR_0___S 0 +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B1_n___M 0x00FFFFFF +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B1_n___S 0 +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B1_0 (0x0049CBD8) +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B1_0__XLNA_RXIQCORR_0___M 0x00FFFFFF +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_L_B1_0__XLNA_RXIQCORR_0___S 0 + +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B0_n(n) (0x00494BDC+0x8*(n)) +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B0_n_nMIN 0 +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B0_n_nMAX 0 +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B0_n_ELEM 1 +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B0_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B0_n___POR 0x00000000 +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B0_n__XLNA_RXIQCORR_1___POR 0x000000 +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B0_n__XLNA_RXIQCORR_1___M 0x00FFFFFF +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B0_n__XLNA_RXIQCORR_1___S 0 +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B0_n___M 0x00FFFFFF +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B0_n___S 0 +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B0_0 (0x00494BDC) +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B0_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B0_0__XLNA_RXIQCORR_1___M 0x00FFFFFF +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B0_0__XLNA_RXIQCORR_1___S 0 + +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B1_n(n) (0x0049CBDC+0x8*(n)) +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B1_n_nMIN 0 +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B1_n_nMAX 0 +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B1_n_ELEM 1 +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B1_n___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B1_n___POR 0x00000000 +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B1_n__XLNA_RXIQCORR_1___POR 0x000000 +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B1_n__XLNA_RXIQCORR_1___M 0x00FFFFFF +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B1_n__XLNA_RXIQCORR_1___S 0 +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B1_n___M 0x00FFFFFF +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B1_n___S 0 +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B1_0 (0x0049CBDC) +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B1_0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B1_0__XLNA_RXIQCORR_1___M 0x00FFFFFF +#define PHYA_PHYRF_RXGAIN_IND_TAB_1_U_B1_0__XLNA_RXIQCORR_1___S 0 + +#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B0 (0x00494FD8) +#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B0__RXGAIN_INDEX_TAB_FORCE_TOTAL_GAIN_DB___POR 0x00 +#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B0__RXGAIN_INDEX_TAB_FORCE_TABLE_SEL___POR 0x0 +#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B0__RXGAIN_INDEX_TAB_FORCE_MODE_SEL___POR 0x0 +#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B0__RXGAIN_INDEX_TAB_FORCE___POR 0x0 +#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B0__RXGAIN_INDEX_TAB_FORCE_TOTAL_GAIN_DB___M 0xFF000000 +#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B0__RXGAIN_INDEX_TAB_FORCE_TOTAL_GAIN_DB___S 24 +#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B0__RXGAIN_INDEX_TAB_FORCE_TABLE_SEL___M 0x00030000 +#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B0__RXGAIN_INDEX_TAB_FORCE_TABLE_SEL___S 16 +#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B0__RXGAIN_INDEX_TAB_FORCE_MODE_SEL___M 0x00000300 +#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B0__RXGAIN_INDEX_TAB_FORCE_MODE_SEL___S 8 +#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B0__RXGAIN_INDEX_TAB_FORCE___M 0x00000001 +#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B0__RXGAIN_INDEX_TAB_FORCE___S 0 +#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B0___M 0xFF030301 +#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B0___S 0 + +#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B1 (0x0049CFD8) +#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B1__RXGAIN_INDEX_TAB_FORCE_TOTAL_GAIN_DB___POR 0x00 +#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B1__RXGAIN_INDEX_TAB_FORCE_TABLE_SEL___POR 0x0 +#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B1__RXGAIN_INDEX_TAB_FORCE_MODE_SEL___POR 0x0 +#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B1__RXGAIN_INDEX_TAB_FORCE___POR 0x0 +#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B1__RXGAIN_INDEX_TAB_FORCE_TOTAL_GAIN_DB___M 0xFF000000 +#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B1__RXGAIN_INDEX_TAB_FORCE_TOTAL_GAIN_DB___S 24 +#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B1__RXGAIN_INDEX_TAB_FORCE_TABLE_SEL___M 0x00030000 +#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B1__RXGAIN_INDEX_TAB_FORCE_TABLE_SEL___S 16 +#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B1__RXGAIN_INDEX_TAB_FORCE_MODE_SEL___M 0x00000300 +#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B1__RXGAIN_INDEX_TAB_FORCE_MODE_SEL___S 8 +#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B1__RXGAIN_INDEX_TAB_FORCE___M 0x00000001 +#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B1__RXGAIN_INDEX_TAB_FORCE___S 0 +#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B1___M 0xFF030301 +#define PHYA_PHYRF_RXGAIN_INDEX_TAB_FORCE_CTRL_L_B1___S 0 + +#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B0 (0x00494FE0) +#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B0__BASE_ADDR_TBL3___POR 0x00 +#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B0__BASE_ADDR_TBL2___POR 0x00 +#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B0__BASE_ADDR_TBL1___POR 0x00 +#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B0__BASE_ADDR_TBL0___POR 0x00 +#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B0__BASE_ADDR_TBL3___M 0xFF000000 +#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B0__BASE_ADDR_TBL3___S 24 +#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B0__BASE_ADDR_TBL2___M 0x00FF0000 +#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B0__BASE_ADDR_TBL2___S 16 +#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B0__BASE_ADDR_TBL1___M 0x0000FF00 +#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B0__BASE_ADDR_TBL1___S 8 +#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B0__BASE_ADDR_TBL0___M 0x000000FF +#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B0__BASE_ADDR_TBL0___S 0 +#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B0___M 0xFFFFFFFF +#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B0___S 0 + +#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B1 (0x0049CFE0) +#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B1__BASE_ADDR_TBL3___POR 0x00 +#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B1__BASE_ADDR_TBL2___POR 0x00 +#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B1__BASE_ADDR_TBL1___POR 0x00 +#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B1__BASE_ADDR_TBL0___POR 0x00 +#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B1__BASE_ADDR_TBL3___M 0xFF000000 +#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B1__BASE_ADDR_TBL3___S 24 +#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B1__BASE_ADDR_TBL2___M 0x00FF0000 +#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B1__BASE_ADDR_TBL2___S 16 +#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B1__BASE_ADDR_TBL1___M 0x0000FF00 +#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B1__BASE_ADDR_TBL1___S 8 +#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B1__BASE_ADDR_TBL0___M 0x000000FF +#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B1__BASE_ADDR_TBL0___S 0 +#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B1___M 0xFFFFFFFF +#define PHYA_PHYRF_RXGAIN_BASE_ADDR_L_B1___S 0 + +#define PHYA_PHYRF_RFCTRL_PERCHAIN_L_B0 (0x00494FE8) +#define PHYA_PHYRF_RFCTRL_PERCHAIN_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RFCTRL_PERCHAIN_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RFCTRL_PERCHAIN_L_B0__GAIN_UPDATE_RST_SOURCE_SELECT___POR 0x0 +#define PHYA_PHYRF_RFCTRL_PERCHAIN_L_B0__GAIN_UPDATE_RST_SOURCE_SELECT___M 0x00000001 +#define PHYA_PHYRF_RFCTRL_PERCHAIN_L_B0__GAIN_UPDATE_RST_SOURCE_SELECT___S 0 +#define PHYA_PHYRF_RFCTRL_PERCHAIN_L_B0___M 0x00000001 +#define PHYA_PHYRF_RFCTRL_PERCHAIN_L_B0___S 0 + +#define PHYA_PHYRF_RFCTRL_PERCHAIN_L_B1 (0x0049CFE8) +#define PHYA_PHYRF_RFCTRL_PERCHAIN_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RFCTRL_PERCHAIN_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RFCTRL_PERCHAIN_L_B1__GAIN_UPDATE_RST_SOURCE_SELECT___POR 0x0 +#define PHYA_PHYRF_RFCTRL_PERCHAIN_L_B1__GAIN_UPDATE_RST_SOURCE_SELECT___M 0x00000001 +#define PHYA_PHYRF_RFCTRL_PERCHAIN_L_B1__GAIN_UPDATE_RST_SOURCE_SELECT___S 0 +#define PHYA_PHYRF_RFCTRL_PERCHAIN_L_B1___M 0x00000001 +#define PHYA_PHYRF_RFCTRL_PERCHAIN_L_B1___S 0 + +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0 (0x00494FF0) +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0___POR 0x00001000 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__CAL_LOOPBACK_RFARXCHAIN_SEL___POR 0x0 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__DPDTRAIN_LOOPBACK_RFARXCHAIN_SEL___POR 0x0 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__RXDCCAL_ODAC_SETTING_INIT___POR 0x100 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__RXDCCAL_ODAC_RANGE_INIT___POR 0x0 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__RXDCCAL_ODAC_POLARITY_Q___POR 0x0 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__RXDCCAL_ODAC_POLARITY_I___POR 0x0 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__CAL_LOOPBACK_RFARXCHAIN_SEL___M 0x00030000 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__CAL_LOOPBACK_RFARXCHAIN_SEL___S 16 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__DPDTRAIN_LOOPBACK_RFARXCHAIN_SEL___M 0x0000C000 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__DPDTRAIN_LOOPBACK_RFARXCHAIN_SEL___S 14 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__RXDCCAL_ODAC_SETTING_INIT___M 0x00003FF0 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__RXDCCAL_ODAC_SETTING_INIT___S 4 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__RXDCCAL_ODAC_RANGE_INIT___M 0x0000000C +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__RXDCCAL_ODAC_RANGE_INIT___S 2 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__RXDCCAL_ODAC_POLARITY_Q___M 0x00000002 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__RXDCCAL_ODAC_POLARITY_Q___S 1 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__RXDCCAL_ODAC_POLARITY_I___M 0x00000001 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0__RXDCCAL_ODAC_POLARITY_I___S 0 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0___M 0x0003FFFF +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B0___S 0 + +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1 (0x0049CFF0) +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1___POR 0x00001000 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__CAL_LOOPBACK_RFARXCHAIN_SEL___POR 0x0 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__DPDTRAIN_LOOPBACK_RFARXCHAIN_SEL___POR 0x0 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__RXDCCAL_ODAC_SETTING_INIT___POR 0x100 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__RXDCCAL_ODAC_RANGE_INIT___POR 0x0 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__RXDCCAL_ODAC_POLARITY_Q___POR 0x0 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__RXDCCAL_ODAC_POLARITY_I___POR 0x0 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__CAL_LOOPBACK_RFARXCHAIN_SEL___M 0x00030000 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__CAL_LOOPBACK_RFARXCHAIN_SEL___S 16 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__DPDTRAIN_LOOPBACK_RFARXCHAIN_SEL___M 0x0000C000 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__DPDTRAIN_LOOPBACK_RFARXCHAIN_SEL___S 14 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__RXDCCAL_ODAC_SETTING_INIT___M 0x00003FF0 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__RXDCCAL_ODAC_SETTING_INIT___S 4 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__RXDCCAL_ODAC_RANGE_INIT___M 0x0000000C +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__RXDCCAL_ODAC_RANGE_INIT___S 2 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__RXDCCAL_ODAC_POLARITY_Q___M 0x00000002 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__RXDCCAL_ODAC_POLARITY_Q___S 1 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__RXDCCAL_ODAC_POLARITY_I___M 0x00000001 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1__RXDCCAL_ODAC_POLARITY_I___S 0 +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1___M 0x0003FFFF +#define PHYA_PHYRF_CAL_PER_CHAIN_CTRL_L_B1___S 0 + +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0 (0x00494FF8) +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0___POR 0x09000627 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_POST_WRITE_ENABLE___POR 0x1 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_RFAREG_WRITE_EN___POR 0x0 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_DISABLE_WSI___POR 0x0 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_BP_LIMIT___POR 0x8 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_PREAMBLE_DLY___POR 0x0 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_SL_ASSERT_CAP_DLY___POR 0x00 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_AUTOSYNCH_MODE___POR 0x3 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_SC_BEFORE_ALL_CMDS___POR 0x0 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_SC_BEFORE_OTHER_CMDS___POR 0x0 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_RD_ACT___POR 0x1 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_RD_DLY___POR 0x3 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_ENBL___POR 0x1 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_POST_WRITE_ENABLE___M 0x08000000 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_POST_WRITE_ENABLE___S 27 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_RFAREG_WRITE_EN___M 0x04000000 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_RFAREG_WRITE_EN___S 26 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_DISABLE_WSI___M 0x02000000 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_DISABLE_WSI___S 25 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_BP_LIMIT___M 0x01E00000 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_BP_LIMIT___S 21 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_PREAMBLE_DLY___M 0x00180000 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_PREAMBLE_DLY___S 19 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_SL_ASSERT_CAP_DLY___M 0x0007F800 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_SL_ASSERT_CAP_DLY___S 11 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_AUTOSYNCH_MODE___M 0x00000600 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_AUTOSYNCH_MODE___S 9 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_SC_BEFORE_ALL_CMDS___M 0x00000100 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_SC_BEFORE_ALL_CMDS___S 8 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_SC_BEFORE_OTHER_CMDS___M 0x00000080 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_SC_BEFORE_OTHER_CMDS___S 7 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_RD_ACT___M 0x00000060 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_RD_ACT___S 5 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_RD_DLY___M 0x0000001E +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_RD_DLY___S 1 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_ENBL___M 0x00000001 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0__RF_BUS_CONFIG_ENBL___S 0 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0___M 0x0FFFFFFF +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B0___S 0 + +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1 (0x0049CFF8) +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1___POR 0x09000627 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_POST_WRITE_ENABLE___POR 0x1 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_RFAREG_WRITE_EN___POR 0x0 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_DISABLE_WSI___POR 0x0 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_BP_LIMIT___POR 0x8 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_PREAMBLE_DLY___POR 0x0 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_SL_ASSERT_CAP_DLY___POR 0x00 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_AUTOSYNCH_MODE___POR 0x3 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_SC_BEFORE_ALL_CMDS___POR 0x0 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_SC_BEFORE_OTHER_CMDS___POR 0x0 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_RD_ACT___POR 0x1 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_RD_DLY___POR 0x3 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_ENBL___POR 0x1 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_POST_WRITE_ENABLE___M 0x08000000 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_POST_WRITE_ENABLE___S 27 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_RFAREG_WRITE_EN___M 0x04000000 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_RFAREG_WRITE_EN___S 26 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_DISABLE_WSI___M 0x02000000 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_DISABLE_WSI___S 25 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_BP_LIMIT___M 0x01E00000 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_BP_LIMIT___S 21 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_PREAMBLE_DLY___M 0x00180000 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_PREAMBLE_DLY___S 19 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_SL_ASSERT_CAP_DLY___M 0x0007F800 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_SL_ASSERT_CAP_DLY___S 11 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_AUTOSYNCH_MODE___M 0x00000600 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_AUTOSYNCH_MODE___S 9 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_SC_BEFORE_ALL_CMDS___M 0x00000100 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_SC_BEFORE_ALL_CMDS___S 8 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_SC_BEFORE_OTHER_CMDS___M 0x00000080 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_SC_BEFORE_OTHER_CMDS___S 7 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_RD_ACT___M 0x00000060 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_RD_ACT___S 5 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_RD_DLY___M 0x0000001E +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_RD_DLY___S 1 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_ENBL___M 0x00000001 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1__RF_BUS_CONFIG_ENBL___S 0 +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1___M 0x0FFFFFFF +#define PHYA_PHYRF_RF_BUS_CONFIG_L_B1___S 0 + +#define PHYA_PHYRF_RF_BUS_STATUS_L_B0 (0x00495000) +#define PHYA_PHYRF_RF_BUS_STATUS_L_B0___RWC QCSR_REG_RO +#define PHYA_PHYRF_RF_BUS_STATUS_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_STATUS_L_B0__RF_BUS_STATUS_RF_BUS_SYNCH_STATE___POR 0x0 +#define PHYA_PHYRF_RF_BUS_STATUS_L_B0__RF_BUS_STATUS_WSI_SM_STATE___POR 0x00 +#define PHYA_PHYRF_RF_BUS_STATUS_L_B0__RF_BUS_STATUS_RF_BUS_SM_STATE___POR 0x0 +#define PHYA_PHYRF_RF_BUS_STATUS_L_B0__RF_BUS_STATUS_RF_BUS_SYNCH_STATE___M 0x00000200 +#define PHYA_PHYRF_RF_BUS_STATUS_L_B0__RF_BUS_STATUS_RF_BUS_SYNCH_STATE___S 9 +#define PHYA_PHYRF_RF_BUS_STATUS_L_B0__RF_BUS_STATUS_WSI_SM_STATE___M 0x000001F0 +#define PHYA_PHYRF_RF_BUS_STATUS_L_B0__RF_BUS_STATUS_WSI_SM_STATE___S 4 +#define PHYA_PHYRF_RF_BUS_STATUS_L_B0__RF_BUS_STATUS_RF_BUS_SM_STATE___M 0x0000000F +#define PHYA_PHYRF_RF_BUS_STATUS_L_B0__RF_BUS_STATUS_RF_BUS_SM_STATE___S 0 +#define PHYA_PHYRF_RF_BUS_STATUS_L_B0___M 0x000003FF +#define PHYA_PHYRF_RF_BUS_STATUS_L_B0___S 0 + +#define PHYA_PHYRF_RF_BUS_STATUS_L_B1 (0x0049D000) +#define PHYA_PHYRF_RF_BUS_STATUS_L_B1___RWC QCSR_REG_RO +#define PHYA_PHYRF_RF_BUS_STATUS_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_STATUS_L_B1__RF_BUS_STATUS_RF_BUS_SYNCH_STATE___POR 0x0 +#define PHYA_PHYRF_RF_BUS_STATUS_L_B1__RF_BUS_STATUS_WSI_SM_STATE___POR 0x00 +#define PHYA_PHYRF_RF_BUS_STATUS_L_B1__RF_BUS_STATUS_RF_BUS_SM_STATE___POR 0x0 +#define PHYA_PHYRF_RF_BUS_STATUS_L_B1__RF_BUS_STATUS_RF_BUS_SYNCH_STATE___M 0x00000200 +#define PHYA_PHYRF_RF_BUS_STATUS_L_B1__RF_BUS_STATUS_RF_BUS_SYNCH_STATE___S 9 +#define PHYA_PHYRF_RF_BUS_STATUS_L_B1__RF_BUS_STATUS_WSI_SM_STATE___M 0x000001F0 +#define PHYA_PHYRF_RF_BUS_STATUS_L_B1__RF_BUS_STATUS_WSI_SM_STATE___S 4 +#define PHYA_PHYRF_RF_BUS_STATUS_L_B1__RF_BUS_STATUS_RF_BUS_SM_STATE___M 0x0000000F +#define PHYA_PHYRF_RF_BUS_STATUS_L_B1__RF_BUS_STATUS_RF_BUS_SM_STATE___S 0 +#define PHYA_PHYRF_RF_BUS_STATUS_L_B1___M 0x000003FF +#define PHYA_PHYRF_RF_BUS_STATUS_L_B1___S 0 + +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0 (0x00495008) +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_TPCRB_OVERLAPPING_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RXDCOC_OVERLAPPING_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RFCAL_OVERLAPPING_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_SYNEN_OVERLAPPING_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_DEBUG_OVERLAPPING_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_MODE_OVERLAPPING_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_TXGAIN_OVERLAPPING_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RXGAIN_OVERLAPPING_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_TPCRB_TIMEOUT_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RXDCOC_TIMEOUT_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RFCAL_TIMEOUT_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_SYNEN_TIMEOUT_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_DEBUG_TIMEOUT_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_MODE_TIMEOUT_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_TXGAIN_TIMEOUT_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RXGAIN_TIMEOUT_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_PARALLEL_READ_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_PHYCMDS_DROPPED_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RFBUS_RESYNCH_REQ___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RFAPB_TIMEOUT_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_BP_TIMEOUT_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_NAK_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_PARITY_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_TPCRB_OVERLAPPING_ERR___M 0x00400000 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_TPCRB_OVERLAPPING_ERR___S 22 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RXDCOC_OVERLAPPING_ERR___M 0x00200000 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RXDCOC_OVERLAPPING_ERR___S 21 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RFCAL_OVERLAPPING_ERR___M 0x00100000 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RFCAL_OVERLAPPING_ERR___S 20 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_SYNEN_OVERLAPPING_ERR___M 0x00080000 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_SYNEN_OVERLAPPING_ERR___S 19 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_DEBUG_OVERLAPPING_ERR___M 0x00040000 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_DEBUG_OVERLAPPING_ERR___S 18 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_MODE_OVERLAPPING_ERR___M 0x00020000 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_MODE_OVERLAPPING_ERR___S 17 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_TXGAIN_OVERLAPPING_ERR___M 0x00010000 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_TXGAIN_OVERLAPPING_ERR___S 16 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RXGAIN_OVERLAPPING_ERR___M 0x00008000 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RXGAIN_OVERLAPPING_ERR___S 15 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_TPCRB_TIMEOUT_ERR___M 0x00004000 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_TPCRB_TIMEOUT_ERR___S 14 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RXDCOC_TIMEOUT_ERR___M 0x00002000 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RXDCOC_TIMEOUT_ERR___S 13 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RFCAL_TIMEOUT_ERR___M 0x00001000 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RFCAL_TIMEOUT_ERR___S 12 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_SYNEN_TIMEOUT_ERR___M 0x00000800 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_SYNEN_TIMEOUT_ERR___S 11 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_DEBUG_TIMEOUT_ERR___M 0x00000400 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_DEBUG_TIMEOUT_ERR___S 10 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_MODE_TIMEOUT_ERR___M 0x00000200 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_MODE_TIMEOUT_ERR___S 9 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_TXGAIN_TIMEOUT_ERR___M 0x00000100 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_TXGAIN_TIMEOUT_ERR___S 8 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RXGAIN_TIMEOUT_ERR___M 0x00000080 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RXGAIN_TIMEOUT_ERR___S 7 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_PARALLEL_READ_ERR___M 0x00000040 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_PARALLEL_READ_ERR___S 6 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_PHYCMDS_DROPPED_ERR___M 0x00000020 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_PHYCMDS_DROPPED_ERR___S 5 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RFBUS_RESYNCH_REQ___M 0x00000010 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RFBUS_RESYNCH_REQ___S 4 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RFAPB_TIMEOUT_ERR___M 0x00000008 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_RFAPB_TIMEOUT_ERR___S 3 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_BP_TIMEOUT_ERR___M 0x00000004 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_BP_TIMEOUT_ERR___S 2 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_NAK_ERR___M 0x00000002 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_NAK_ERR___S 1 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_PARITY_ERR___M 0x00000001 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0__RF_BUS_ERR_STATUS_PARITY_ERR___S 0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0___M 0x007FFFFF +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B0___S 0 + +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1 (0x0049D008) +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_TPCRB_OVERLAPPING_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RXDCOC_OVERLAPPING_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RFCAL_OVERLAPPING_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_SYNEN_OVERLAPPING_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_DEBUG_OVERLAPPING_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_MODE_OVERLAPPING_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_TXGAIN_OVERLAPPING_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RXGAIN_OVERLAPPING_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_TPCRB_TIMEOUT_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RXDCOC_TIMEOUT_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RFCAL_TIMEOUT_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_SYNEN_TIMEOUT_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_DEBUG_TIMEOUT_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_MODE_TIMEOUT_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_TXGAIN_TIMEOUT_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RXGAIN_TIMEOUT_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_PARALLEL_READ_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_PHYCMDS_DROPPED_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RFBUS_RESYNCH_REQ___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RFAPB_TIMEOUT_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_BP_TIMEOUT_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_NAK_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_PARITY_ERR___POR 0x0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_TPCRB_OVERLAPPING_ERR___M 0x00400000 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_TPCRB_OVERLAPPING_ERR___S 22 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RXDCOC_OVERLAPPING_ERR___M 0x00200000 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RXDCOC_OVERLAPPING_ERR___S 21 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RFCAL_OVERLAPPING_ERR___M 0x00100000 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RFCAL_OVERLAPPING_ERR___S 20 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_SYNEN_OVERLAPPING_ERR___M 0x00080000 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_SYNEN_OVERLAPPING_ERR___S 19 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_DEBUG_OVERLAPPING_ERR___M 0x00040000 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_DEBUG_OVERLAPPING_ERR___S 18 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_MODE_OVERLAPPING_ERR___M 0x00020000 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_MODE_OVERLAPPING_ERR___S 17 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_TXGAIN_OVERLAPPING_ERR___M 0x00010000 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_TXGAIN_OVERLAPPING_ERR___S 16 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RXGAIN_OVERLAPPING_ERR___M 0x00008000 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RXGAIN_OVERLAPPING_ERR___S 15 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_TPCRB_TIMEOUT_ERR___M 0x00004000 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_TPCRB_TIMEOUT_ERR___S 14 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RXDCOC_TIMEOUT_ERR___M 0x00002000 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RXDCOC_TIMEOUT_ERR___S 13 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RFCAL_TIMEOUT_ERR___M 0x00001000 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RFCAL_TIMEOUT_ERR___S 12 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_SYNEN_TIMEOUT_ERR___M 0x00000800 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_SYNEN_TIMEOUT_ERR___S 11 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_DEBUG_TIMEOUT_ERR___M 0x00000400 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_DEBUG_TIMEOUT_ERR___S 10 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_MODE_TIMEOUT_ERR___M 0x00000200 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_MODE_TIMEOUT_ERR___S 9 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_TXGAIN_TIMEOUT_ERR___M 0x00000100 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_TXGAIN_TIMEOUT_ERR___S 8 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RXGAIN_TIMEOUT_ERR___M 0x00000080 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RXGAIN_TIMEOUT_ERR___S 7 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_PARALLEL_READ_ERR___M 0x00000040 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_PARALLEL_READ_ERR___S 6 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_PHYCMDS_DROPPED_ERR___M 0x00000020 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_PHYCMDS_DROPPED_ERR___S 5 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RFBUS_RESYNCH_REQ___M 0x00000010 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RFBUS_RESYNCH_REQ___S 4 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RFAPB_TIMEOUT_ERR___M 0x00000008 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_RFAPB_TIMEOUT_ERR___S 3 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_BP_TIMEOUT_ERR___M 0x00000004 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_BP_TIMEOUT_ERR___S 2 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_NAK_ERR___M 0x00000002 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_NAK_ERR___S 1 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_PARITY_ERR___M 0x00000001 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1__RF_BUS_ERR_STATUS_PARITY_ERR___S 0 +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1___M 0x007FFFFF +#define PHYA_PHYRF_RF_BUS_ERR_STATUS_L_B1___S 0 + +#define PHYA_PHYRF_RF_BUS_PERROR_COUNT_L_B0 (0x00495010) +#define PHYA_PHYRF_RF_BUS_PERROR_COUNT_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_BUS_PERROR_COUNT_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_PERROR_COUNT_L_B0__RF_BUS_PERROR_COUNT_PERRORS___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_PERROR_COUNT_L_B0__RF_BUS_PERROR_COUNT_PERRORS___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_PERROR_COUNT_L_B0__RF_BUS_PERROR_COUNT_PERRORS___S 0 +#define PHYA_PHYRF_RF_BUS_PERROR_COUNT_L_B0___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_PERROR_COUNT_L_B0___S 0 + +#define PHYA_PHYRF_RF_BUS_PERROR_COUNT_L_B1 (0x0049D010) +#define PHYA_PHYRF_RF_BUS_PERROR_COUNT_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_BUS_PERROR_COUNT_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_PERROR_COUNT_L_B1__RF_BUS_PERROR_COUNT_PERRORS___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_PERROR_COUNT_L_B1__RF_BUS_PERROR_COUNT_PERRORS___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_PERROR_COUNT_L_B1__RF_BUS_PERROR_COUNT_PERRORS___S 0 +#define PHYA_PHYRF_RF_BUS_PERROR_COUNT_L_B1___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_PERROR_COUNT_L_B1___S 0 + +#define PHYA_PHYRF_RF_BUS_NAK_COUNT_L_B0 (0x00495018) +#define PHYA_PHYRF_RF_BUS_NAK_COUNT_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_BUS_NAK_COUNT_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_NAK_COUNT_L_B0__RF_BUS_NAK_COUNT_NAKS___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_NAK_COUNT_L_B0__RF_BUS_NAK_COUNT_NAKS___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_NAK_COUNT_L_B0__RF_BUS_NAK_COUNT_NAKS___S 0 +#define PHYA_PHYRF_RF_BUS_NAK_COUNT_L_B0___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_NAK_COUNT_L_B0___S 0 + +#define PHYA_PHYRF_RF_BUS_NAK_COUNT_L_B1 (0x0049D018) +#define PHYA_PHYRF_RF_BUS_NAK_COUNT_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_BUS_NAK_COUNT_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_NAK_COUNT_L_B1__RF_BUS_NAK_COUNT_NAKS___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_NAK_COUNT_L_B1__RF_BUS_NAK_COUNT_NAKS___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_NAK_COUNT_L_B1__RF_BUS_NAK_COUNT_NAKS___S 0 +#define PHYA_PHYRF_RF_BUS_NAK_COUNT_L_B1___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_NAK_COUNT_L_B1___S 0 + +#define PHYA_PHYRF_RF_BUS_BP_TIMEOUT_COUNT_L_B0 (0x00495020) +#define PHYA_PHYRF_RF_BUS_BP_TIMEOUT_COUNT_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_BUS_BP_TIMEOUT_COUNT_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_BP_TIMEOUT_COUNT_L_B0__RF_BUS_BP_TIMEOUT_COUNT_VAL___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_BP_TIMEOUT_COUNT_L_B0__RF_BUS_BP_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_BP_TIMEOUT_COUNT_L_B0__RF_BUS_BP_TIMEOUT_COUNT_VAL___S 0 +#define PHYA_PHYRF_RF_BUS_BP_TIMEOUT_COUNT_L_B0___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_BP_TIMEOUT_COUNT_L_B0___S 0 + +#define PHYA_PHYRF_RF_BUS_BP_TIMEOUT_COUNT_L_B1 (0x0049D020) +#define PHYA_PHYRF_RF_BUS_BP_TIMEOUT_COUNT_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_BUS_BP_TIMEOUT_COUNT_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_BP_TIMEOUT_COUNT_L_B1__RF_BUS_BP_TIMEOUT_COUNT_VAL___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_BP_TIMEOUT_COUNT_L_B1__RF_BUS_BP_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_BP_TIMEOUT_COUNT_L_B1__RF_BUS_BP_TIMEOUT_COUNT_VAL___S 0 +#define PHYA_PHYRF_RF_BUS_BP_TIMEOUT_COUNT_L_B1___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_BP_TIMEOUT_COUNT_L_B1___S 0 + +#define PHYA_PHYRF_RF_BUS_RFAPB_TIMEOUT_COUNT_L_B0 (0x00495028) +#define PHYA_PHYRF_RF_BUS_RFAPB_TIMEOUT_COUNT_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_BUS_RFAPB_TIMEOUT_COUNT_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_RFAPB_TIMEOUT_COUNT_L_B0__RF_BUS_RFAPB_TIMEOUT_COUNT_VAL___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_RFAPB_TIMEOUT_COUNT_L_B0__RF_BUS_RFAPB_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_RFAPB_TIMEOUT_COUNT_L_B0__RF_BUS_RFAPB_TIMEOUT_COUNT_VAL___S 0 +#define PHYA_PHYRF_RF_BUS_RFAPB_TIMEOUT_COUNT_L_B0___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_RFAPB_TIMEOUT_COUNT_L_B0___S 0 + +#define PHYA_PHYRF_RF_BUS_RFAPB_TIMEOUT_COUNT_L_B1 (0x0049D028) +#define PHYA_PHYRF_RF_BUS_RFAPB_TIMEOUT_COUNT_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_BUS_RFAPB_TIMEOUT_COUNT_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_RFAPB_TIMEOUT_COUNT_L_B1__RF_BUS_RFAPB_TIMEOUT_COUNT_VAL___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_RFAPB_TIMEOUT_COUNT_L_B1__RF_BUS_RFAPB_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_RFAPB_TIMEOUT_COUNT_L_B1__RF_BUS_RFAPB_TIMEOUT_COUNT_VAL___S 0 +#define PHYA_PHYRF_RF_BUS_RFAPB_TIMEOUT_COUNT_L_B1___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_RFAPB_TIMEOUT_COUNT_L_B1___S 0 + +#define PHYA_PHYRF_RF_BUS_RESYNCH_REQ_COUNT_L_B0 (0x00495030) +#define PHYA_PHYRF_RF_BUS_RESYNCH_REQ_COUNT_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_BUS_RESYNCH_REQ_COUNT_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_RESYNCH_REQ_COUNT_L_B0__RF_BUS_RESYNCH_REQ_COUNT_RESYNCH_REQS___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_RESYNCH_REQ_COUNT_L_B0__RF_BUS_RESYNCH_REQ_COUNT_RESYNCH_REQS___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_RESYNCH_REQ_COUNT_L_B0__RF_BUS_RESYNCH_REQ_COUNT_RESYNCH_REQS___S 0 +#define PHYA_PHYRF_RF_BUS_RESYNCH_REQ_COUNT_L_B0___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_RESYNCH_REQ_COUNT_L_B0___S 0 + +#define PHYA_PHYRF_RF_BUS_RESYNCH_REQ_COUNT_L_B1 (0x0049D030) +#define PHYA_PHYRF_RF_BUS_RESYNCH_REQ_COUNT_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_BUS_RESYNCH_REQ_COUNT_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_RESYNCH_REQ_COUNT_L_B1__RF_BUS_RESYNCH_REQ_COUNT_RESYNCH_REQS___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_RESYNCH_REQ_COUNT_L_B1__RF_BUS_RESYNCH_REQ_COUNT_RESYNCH_REQS___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_RESYNCH_REQ_COUNT_L_B1__RF_BUS_RESYNCH_REQ_COUNT_RESYNCH_REQS___S 0 +#define PHYA_PHYRF_RF_BUS_RESYNCH_REQ_COUNT_L_B1___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_RESYNCH_REQ_COUNT_L_B1___S 0 + +#define PHYA_PHYRF_RF_BUS_DROPPED_PHYCMDS_COUNT_L_B0 (0x00495038) +#define PHYA_PHYRF_RF_BUS_DROPPED_PHYCMDS_COUNT_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_BUS_DROPPED_PHYCMDS_COUNT_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_DROPPED_PHYCMDS_COUNT_L_B0__RF_BUS_DROPPED_PHYCMDS_COUNT_DROPPED_PHYCMDS___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_DROPPED_PHYCMDS_COUNT_L_B0__RF_BUS_DROPPED_PHYCMDS_COUNT_DROPPED_PHYCMDS___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_DROPPED_PHYCMDS_COUNT_L_B0__RF_BUS_DROPPED_PHYCMDS_COUNT_DROPPED_PHYCMDS___S 0 +#define PHYA_PHYRF_RF_BUS_DROPPED_PHYCMDS_COUNT_L_B0___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_DROPPED_PHYCMDS_COUNT_L_B0___S 0 + +#define PHYA_PHYRF_RF_BUS_DROPPED_PHYCMDS_COUNT_L_B1 (0x0049D038) +#define PHYA_PHYRF_RF_BUS_DROPPED_PHYCMDS_COUNT_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_BUS_DROPPED_PHYCMDS_COUNT_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_DROPPED_PHYCMDS_COUNT_L_B1__RF_BUS_DROPPED_PHYCMDS_COUNT_DROPPED_PHYCMDS___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_DROPPED_PHYCMDS_COUNT_L_B1__RF_BUS_DROPPED_PHYCMDS_COUNT_DROPPED_PHYCMDS___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_DROPPED_PHYCMDS_COUNT_L_B1__RF_BUS_DROPPED_PHYCMDS_COUNT_DROPPED_PHYCMDS___S 0 +#define PHYA_PHYRF_RF_BUS_DROPPED_PHYCMDS_COUNT_L_B1___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_DROPPED_PHYCMDS_COUNT_L_B1___S 0 + +#define PHYA_PHYRF_RF_BUS_RXGAIN_TIMEOUT_COUNT_L_B0 (0x00495040) +#define PHYA_PHYRF_RF_BUS_RXGAIN_TIMEOUT_COUNT_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_BUS_RXGAIN_TIMEOUT_COUNT_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_RXGAIN_TIMEOUT_COUNT_L_B0__RF_BUS_RXGAIN_TIMEOUT_COUNT_VAL___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_RXGAIN_TIMEOUT_COUNT_L_B0__RF_BUS_RXGAIN_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_RXGAIN_TIMEOUT_COUNT_L_B0__RF_BUS_RXGAIN_TIMEOUT_COUNT_VAL___S 0 +#define PHYA_PHYRF_RF_BUS_RXGAIN_TIMEOUT_COUNT_L_B0___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_RXGAIN_TIMEOUT_COUNT_L_B0___S 0 + +#define PHYA_PHYRF_RF_BUS_RXGAIN_TIMEOUT_COUNT_L_B1 (0x0049D040) +#define PHYA_PHYRF_RF_BUS_RXGAIN_TIMEOUT_COUNT_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_BUS_RXGAIN_TIMEOUT_COUNT_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_RXGAIN_TIMEOUT_COUNT_L_B1__RF_BUS_RXGAIN_TIMEOUT_COUNT_VAL___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_RXGAIN_TIMEOUT_COUNT_L_B1__RF_BUS_RXGAIN_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_RXGAIN_TIMEOUT_COUNT_L_B1__RF_BUS_RXGAIN_TIMEOUT_COUNT_VAL___S 0 +#define PHYA_PHYRF_RF_BUS_RXGAIN_TIMEOUT_COUNT_L_B1___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_RXGAIN_TIMEOUT_COUNT_L_B1___S 0 + +#define PHYA_PHYRF_RF_BUS_TXGAIN_TIMEOUT_COUNT_L_B0 (0x00495048) +#define PHYA_PHYRF_RF_BUS_TXGAIN_TIMEOUT_COUNT_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_BUS_TXGAIN_TIMEOUT_COUNT_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_TXGAIN_TIMEOUT_COUNT_L_B0__RF_BUS_TXGAIN_TIMEOUT_COUNT_VAL___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_TXGAIN_TIMEOUT_COUNT_L_B0__RF_BUS_TXGAIN_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_TXGAIN_TIMEOUT_COUNT_L_B0__RF_BUS_TXGAIN_TIMEOUT_COUNT_VAL___S 0 +#define PHYA_PHYRF_RF_BUS_TXGAIN_TIMEOUT_COUNT_L_B0___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_TXGAIN_TIMEOUT_COUNT_L_B0___S 0 + +#define PHYA_PHYRF_RF_BUS_TXGAIN_TIMEOUT_COUNT_L_B1 (0x0049D048) +#define PHYA_PHYRF_RF_BUS_TXGAIN_TIMEOUT_COUNT_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_BUS_TXGAIN_TIMEOUT_COUNT_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_TXGAIN_TIMEOUT_COUNT_L_B1__RF_BUS_TXGAIN_TIMEOUT_COUNT_VAL___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_TXGAIN_TIMEOUT_COUNT_L_B1__RF_BUS_TXGAIN_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_TXGAIN_TIMEOUT_COUNT_L_B1__RF_BUS_TXGAIN_TIMEOUT_COUNT_VAL___S 0 +#define PHYA_PHYRF_RF_BUS_TXGAIN_TIMEOUT_COUNT_L_B1___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_TXGAIN_TIMEOUT_COUNT_L_B1___S 0 + +#define PHYA_PHYRF_RF_BUS_MODE_TIMEOUT_COUNT_L_B0 (0x00495050) +#define PHYA_PHYRF_RF_BUS_MODE_TIMEOUT_COUNT_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_BUS_MODE_TIMEOUT_COUNT_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_MODE_TIMEOUT_COUNT_L_B0__RF_BUS_MODE_TIMEOUT_COUNT_VAL___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_MODE_TIMEOUT_COUNT_L_B0__RF_BUS_MODE_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_MODE_TIMEOUT_COUNT_L_B0__RF_BUS_MODE_TIMEOUT_COUNT_VAL___S 0 +#define PHYA_PHYRF_RF_BUS_MODE_TIMEOUT_COUNT_L_B0___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_MODE_TIMEOUT_COUNT_L_B0___S 0 + +#define PHYA_PHYRF_RF_BUS_MODE_TIMEOUT_COUNT_L_B1 (0x0049D050) +#define PHYA_PHYRF_RF_BUS_MODE_TIMEOUT_COUNT_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_BUS_MODE_TIMEOUT_COUNT_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_MODE_TIMEOUT_COUNT_L_B1__RF_BUS_MODE_TIMEOUT_COUNT_VAL___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_MODE_TIMEOUT_COUNT_L_B1__RF_BUS_MODE_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_MODE_TIMEOUT_COUNT_L_B1__RF_BUS_MODE_TIMEOUT_COUNT_VAL___S 0 +#define PHYA_PHYRF_RF_BUS_MODE_TIMEOUT_COUNT_L_B1___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_MODE_TIMEOUT_COUNT_L_B1___S 0 + +#define PHYA_PHYRF_RF_BUS_DEBUG_TIMEOUT_COUNT_L_B0 (0x00495058) +#define PHYA_PHYRF_RF_BUS_DEBUG_TIMEOUT_COUNT_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_BUS_DEBUG_TIMEOUT_COUNT_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_DEBUG_TIMEOUT_COUNT_L_B0__RF_BUS_DEBUG_TIMEOUT_COUNT_VAL___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_DEBUG_TIMEOUT_COUNT_L_B0__RF_BUS_DEBUG_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_DEBUG_TIMEOUT_COUNT_L_B0__RF_BUS_DEBUG_TIMEOUT_COUNT_VAL___S 0 +#define PHYA_PHYRF_RF_BUS_DEBUG_TIMEOUT_COUNT_L_B0___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_DEBUG_TIMEOUT_COUNT_L_B0___S 0 + +#define PHYA_PHYRF_RF_BUS_DEBUG_TIMEOUT_COUNT_L_B1 (0x0049D058) +#define PHYA_PHYRF_RF_BUS_DEBUG_TIMEOUT_COUNT_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_BUS_DEBUG_TIMEOUT_COUNT_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_DEBUG_TIMEOUT_COUNT_L_B1__RF_BUS_DEBUG_TIMEOUT_COUNT_VAL___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_DEBUG_TIMEOUT_COUNT_L_B1__RF_BUS_DEBUG_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_DEBUG_TIMEOUT_COUNT_L_B1__RF_BUS_DEBUG_TIMEOUT_COUNT_VAL___S 0 +#define PHYA_PHYRF_RF_BUS_DEBUG_TIMEOUT_COUNT_L_B1___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_DEBUG_TIMEOUT_COUNT_L_B1___S 0 + +#define PHYA_PHYRF_RF_BUS_SYNEN_TIMEOUT_COUNT_L_B0 (0x00495060) +#define PHYA_PHYRF_RF_BUS_SYNEN_TIMEOUT_COUNT_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_BUS_SYNEN_TIMEOUT_COUNT_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_SYNEN_TIMEOUT_COUNT_L_B0__RF_BUS_SYNEN_TIMEOUT_COUNT_VAL___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_SYNEN_TIMEOUT_COUNT_L_B0__RF_BUS_SYNEN_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_SYNEN_TIMEOUT_COUNT_L_B0__RF_BUS_SYNEN_TIMEOUT_COUNT_VAL___S 0 +#define PHYA_PHYRF_RF_BUS_SYNEN_TIMEOUT_COUNT_L_B0___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_SYNEN_TIMEOUT_COUNT_L_B0___S 0 + +#define PHYA_PHYRF_RF_BUS_SYNEN_TIMEOUT_COUNT_L_B1 (0x0049D060) +#define PHYA_PHYRF_RF_BUS_SYNEN_TIMEOUT_COUNT_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_BUS_SYNEN_TIMEOUT_COUNT_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_SYNEN_TIMEOUT_COUNT_L_B1__RF_BUS_SYNEN_TIMEOUT_COUNT_VAL___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_SYNEN_TIMEOUT_COUNT_L_B1__RF_BUS_SYNEN_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_SYNEN_TIMEOUT_COUNT_L_B1__RF_BUS_SYNEN_TIMEOUT_COUNT_VAL___S 0 +#define PHYA_PHYRF_RF_BUS_SYNEN_TIMEOUT_COUNT_L_B1___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_SYNEN_TIMEOUT_COUNT_L_B1___S 0 + +#define PHYA_PHYRF_RF_BUS_RFCAL_TIMEOUT_COUNT_L_B0 (0x00495068) +#define PHYA_PHYRF_RF_BUS_RFCAL_TIMEOUT_COUNT_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_BUS_RFCAL_TIMEOUT_COUNT_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_RFCAL_TIMEOUT_COUNT_L_B0__RF_BUS_RFCAL_TIMEOUT_COUNT_VAL___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_RFCAL_TIMEOUT_COUNT_L_B0__RF_BUS_RFCAL_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_RFCAL_TIMEOUT_COUNT_L_B0__RF_BUS_RFCAL_TIMEOUT_COUNT_VAL___S 0 +#define PHYA_PHYRF_RF_BUS_RFCAL_TIMEOUT_COUNT_L_B0___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_RFCAL_TIMEOUT_COUNT_L_B0___S 0 + +#define PHYA_PHYRF_RF_BUS_RFCAL_TIMEOUT_COUNT_L_B1 (0x0049D068) +#define PHYA_PHYRF_RF_BUS_RFCAL_TIMEOUT_COUNT_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_BUS_RFCAL_TIMEOUT_COUNT_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_RFCAL_TIMEOUT_COUNT_L_B1__RF_BUS_RFCAL_TIMEOUT_COUNT_VAL___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_RFCAL_TIMEOUT_COUNT_L_B1__RF_BUS_RFCAL_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_RFCAL_TIMEOUT_COUNT_L_B1__RF_BUS_RFCAL_TIMEOUT_COUNT_VAL___S 0 +#define PHYA_PHYRF_RF_BUS_RFCAL_TIMEOUT_COUNT_L_B1___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_RFCAL_TIMEOUT_COUNT_L_B1___S 0 + +#define PHYA_PHYRF_RF_BUS_RXDCOC_TIMEOUT_COUNT_L_B0 (0x00495070) +#define PHYA_PHYRF_RF_BUS_RXDCOC_TIMEOUT_COUNT_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_BUS_RXDCOC_TIMEOUT_COUNT_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_RXDCOC_TIMEOUT_COUNT_L_B0__RF_BUS_RXDCOC_TIMEOUT_COUNT_VAL___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_RXDCOC_TIMEOUT_COUNT_L_B0__RF_BUS_RXDCOC_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_RXDCOC_TIMEOUT_COUNT_L_B0__RF_BUS_RXDCOC_TIMEOUT_COUNT_VAL___S 0 +#define PHYA_PHYRF_RF_BUS_RXDCOC_TIMEOUT_COUNT_L_B0___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_RXDCOC_TIMEOUT_COUNT_L_B0___S 0 + +#define PHYA_PHYRF_RF_BUS_RXDCOC_TIMEOUT_COUNT_L_B1 (0x0049D070) +#define PHYA_PHYRF_RF_BUS_RXDCOC_TIMEOUT_COUNT_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_BUS_RXDCOC_TIMEOUT_COUNT_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_RXDCOC_TIMEOUT_COUNT_L_B1__RF_BUS_RXDCOC_TIMEOUT_COUNT_VAL___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_RXDCOC_TIMEOUT_COUNT_L_B1__RF_BUS_RXDCOC_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_RXDCOC_TIMEOUT_COUNT_L_B1__RF_BUS_RXDCOC_TIMEOUT_COUNT_VAL___S 0 +#define PHYA_PHYRF_RF_BUS_RXDCOC_TIMEOUT_COUNT_L_B1___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_RXDCOC_TIMEOUT_COUNT_L_B1___S 0 + +#define PHYA_PHYRF_RF_BUS_TPCRB_TIMEOUT_COUNT_L_B0 (0x00495078) +#define PHYA_PHYRF_RF_BUS_TPCRB_TIMEOUT_COUNT_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_BUS_TPCRB_TIMEOUT_COUNT_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_TPCRB_TIMEOUT_COUNT_L_B0__RF_BUS_TPCRB_TIMEOUT_COUNT_VAL___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_TPCRB_TIMEOUT_COUNT_L_B0__RF_BUS_TPCRB_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_TPCRB_TIMEOUT_COUNT_L_B0__RF_BUS_TPCRB_TIMEOUT_COUNT_VAL___S 0 +#define PHYA_PHYRF_RF_BUS_TPCRB_TIMEOUT_COUNT_L_B0___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_TPCRB_TIMEOUT_COUNT_L_B0___S 0 + +#define PHYA_PHYRF_RF_BUS_TPCRB_TIMEOUT_COUNT_L_B1 (0x0049D078) +#define PHYA_PHYRF_RF_BUS_TPCRB_TIMEOUT_COUNT_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_BUS_TPCRB_TIMEOUT_COUNT_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_TPCRB_TIMEOUT_COUNT_L_B1__RF_BUS_TPCRB_TIMEOUT_COUNT_VAL___POR 0x00000000 +#define PHYA_PHYRF_RF_BUS_TPCRB_TIMEOUT_COUNT_L_B1__RF_BUS_TPCRB_TIMEOUT_COUNT_VAL___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_TPCRB_TIMEOUT_COUNT_L_B1__RF_BUS_TPCRB_TIMEOUT_COUNT_VAL___S 0 +#define PHYA_PHYRF_RF_BUS_TPCRB_TIMEOUT_COUNT_L_B1___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_BUS_TPCRB_TIMEOUT_COUNT_L_B1___S 0 + +#define PHYA_PHYRF_ARB_CTRL_L_B0 (0x00495080) +#define PHYA_PHYRF_ARB_CTRL_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_ARB_CTRL_L_B0___POR 0x00000000 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_LOW_PRIORITY___POR 0x0 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_WR_TIMEOUT___POR 0x0 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_RD_TIMEOUT___POR 0x0 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_BURST_WR___POR 0x0 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_BURST_RD___POR 0x0 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_CMDS___POR 0x0 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_ARB_CMDS___POR 0x0 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFSAT_RD_CMDS___POR 0x0 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_TPCRB_CMDS___POR 0x0 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RXDCOC_CMDS___POR 0x0 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFCAL_CMDS___POR 0x0 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_SYNEN_CMDS___POR 0x0 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_DEBUG_CMDS___POR 0x0 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_MODE_CMDS___POR 0x0 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_TXGAIN_CMDS___POR 0x0 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RXGAIN_CMDS___POR 0x0 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_LOW_PRIORITY___M 0x00008000 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_LOW_PRIORITY___S 15 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_WR_TIMEOUT___M 0x00004000 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_WR_TIMEOUT___S 14 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_RD_TIMEOUT___M 0x00002000 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_RD_TIMEOUT___S 13 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_BURST_WR___M 0x00001000 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_BURST_WR___S 12 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_BURST_RD___M 0x00000800 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_BURST_RD___S 11 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_CMDS___M 0x00000400 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFAPB_CMDS___S 10 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_ARB_CMDS___M 0x00000200 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_ARB_CMDS___S 9 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFSAT_RD_CMDS___M 0x00000100 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFSAT_RD_CMDS___S 8 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_TPCRB_CMDS___M 0x00000080 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_TPCRB_CMDS___S 7 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RXDCOC_CMDS___M 0x00000040 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RXDCOC_CMDS___S 6 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFCAL_CMDS___M 0x00000020 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RFCAL_CMDS___S 5 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_SYNEN_CMDS___M 0x00000010 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_SYNEN_CMDS___S 4 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_DEBUG_CMDS___M 0x00000008 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_DEBUG_CMDS___S 3 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_MODE_CMDS___M 0x00000004 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_MODE_CMDS___S 2 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_TXGAIN_CMDS___M 0x00000002 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_TXGAIN_CMDS___S 1 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RXGAIN_CMDS___M 0x00000001 +#define PHYA_PHYRF_ARB_CTRL_L_B0__ARB_CTRL_ENBL_RXGAIN_CMDS___S 0 +#define PHYA_PHYRF_ARB_CTRL_L_B0___M 0x0000FFFF +#define PHYA_PHYRF_ARB_CTRL_L_B0___S 0 + +#define PHYA_PHYRF_ARB_CTRL_L_B1 (0x0049D080) +#define PHYA_PHYRF_ARB_CTRL_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_ARB_CTRL_L_B1___POR 0x00000000 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_LOW_PRIORITY___POR 0x0 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_WR_TIMEOUT___POR 0x0 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_RD_TIMEOUT___POR 0x0 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_BURST_WR___POR 0x0 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_BURST_RD___POR 0x0 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_CMDS___POR 0x0 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_ARB_CMDS___POR 0x0 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFSAT_RD_CMDS___POR 0x0 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_TPCRB_CMDS___POR 0x0 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RXDCOC_CMDS___POR 0x0 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFCAL_CMDS___POR 0x0 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_SYNEN_CMDS___POR 0x0 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_DEBUG_CMDS___POR 0x0 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_MODE_CMDS___POR 0x0 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_TXGAIN_CMDS___POR 0x0 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RXGAIN_CMDS___POR 0x0 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_LOW_PRIORITY___M 0x00008000 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_LOW_PRIORITY___S 15 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_WR_TIMEOUT___M 0x00004000 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_WR_TIMEOUT___S 14 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_RD_TIMEOUT___M 0x00002000 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_RD_TIMEOUT___S 13 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_BURST_WR___M 0x00001000 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_BURST_WR___S 12 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_BURST_RD___M 0x00000800 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_BURST_RD___S 11 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_CMDS___M 0x00000400 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFAPB_CMDS___S 10 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_ARB_CMDS___M 0x00000200 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_ARB_CMDS___S 9 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFSAT_RD_CMDS___M 0x00000100 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFSAT_RD_CMDS___S 8 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_TPCRB_CMDS___M 0x00000080 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_TPCRB_CMDS___S 7 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RXDCOC_CMDS___M 0x00000040 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RXDCOC_CMDS___S 6 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFCAL_CMDS___M 0x00000020 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RFCAL_CMDS___S 5 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_SYNEN_CMDS___M 0x00000010 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_SYNEN_CMDS___S 4 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_DEBUG_CMDS___M 0x00000008 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_DEBUG_CMDS___S 3 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_MODE_CMDS___M 0x00000004 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_MODE_CMDS___S 2 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_TXGAIN_CMDS___M 0x00000002 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_TXGAIN_CMDS___S 1 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RXGAIN_CMDS___M 0x00000001 +#define PHYA_PHYRF_ARB_CTRL_L_B1__ARB_CTRL_ENBL_RXGAIN_CMDS___S 0 +#define PHYA_PHYRF_ARB_CTRL_L_B1___M 0x0000FFFF +#define PHYA_PHYRF_ARB_CTRL_L_B1___S 0 + +#define PHYA_PHYRF_ARB_STATUS_L_B0 (0x00495088) +#define PHYA_PHYRF_ARB_STATUS_L_B0___RWC QCSR_REG_RO +#define PHYA_PHYRF_ARB_STATUS_L_B0___POR 0x00000000 +#define PHYA_PHYRF_ARB_STATUS_L_B0__ARB_STATUS_RF_CMD_BUSY___POR 0x0 +#define PHYA_PHYRF_ARB_STATUS_L_B0__ARB_STATUS_RFAPB_OVERLAPPING_PHY_CMDS___POR 0x0 +#define PHYA_PHYRF_ARB_STATUS_L_B0__ARB_STATUS_RFAPB_DROPPED_CMDS___POR 0x0 +#define PHYA_PHYRF_ARB_STATUS_L_B0__ARB_STATUS_BLOCKED_CMDS___POR 0x0 +#define PHYA_PHYRF_ARB_STATUS_L_B0__ARB_STATUS_ARB_SM_STATE___POR 0x0 +#define PHYA_PHYRF_ARB_STATUS_L_B0__ARB_STATUS_RF_CMD_BUSY___M 0x00010000 +#define PHYA_PHYRF_ARB_STATUS_L_B0__ARB_STATUS_RF_CMD_BUSY___S 16 +#define PHYA_PHYRF_ARB_STATUS_L_B0__ARB_STATUS_RFAPB_OVERLAPPING_PHY_CMDS___M 0x0000F000 +#define PHYA_PHYRF_ARB_STATUS_L_B0__ARB_STATUS_RFAPB_OVERLAPPING_PHY_CMDS___S 12 +#define PHYA_PHYRF_ARB_STATUS_L_B0__ARB_STATUS_RFAPB_DROPPED_CMDS___M 0x00000F00 +#define PHYA_PHYRF_ARB_STATUS_L_B0__ARB_STATUS_RFAPB_DROPPED_CMDS___S 8 +#define PHYA_PHYRF_ARB_STATUS_L_B0__ARB_STATUS_BLOCKED_CMDS___M 0x000000F0 +#define PHYA_PHYRF_ARB_STATUS_L_B0__ARB_STATUS_BLOCKED_CMDS___S 4 +#define PHYA_PHYRF_ARB_STATUS_L_B0__ARB_STATUS_ARB_SM_STATE___M 0x0000000F +#define PHYA_PHYRF_ARB_STATUS_L_B0__ARB_STATUS_ARB_SM_STATE___S 0 +#define PHYA_PHYRF_ARB_STATUS_L_B0___M 0x0001FFFF +#define PHYA_PHYRF_ARB_STATUS_L_B0___S 0 + +#define PHYA_PHYRF_ARB_STATUS_L_B1 (0x0049D088) +#define PHYA_PHYRF_ARB_STATUS_L_B1___RWC QCSR_REG_RO +#define PHYA_PHYRF_ARB_STATUS_L_B1___POR 0x00000000 +#define PHYA_PHYRF_ARB_STATUS_L_B1__ARB_STATUS_RF_CMD_BUSY___POR 0x0 +#define PHYA_PHYRF_ARB_STATUS_L_B1__ARB_STATUS_RFAPB_OVERLAPPING_PHY_CMDS___POR 0x0 +#define PHYA_PHYRF_ARB_STATUS_L_B1__ARB_STATUS_RFAPB_DROPPED_CMDS___POR 0x0 +#define PHYA_PHYRF_ARB_STATUS_L_B1__ARB_STATUS_BLOCKED_CMDS___POR 0x0 +#define PHYA_PHYRF_ARB_STATUS_L_B1__ARB_STATUS_ARB_SM_STATE___POR 0x0 +#define PHYA_PHYRF_ARB_STATUS_L_B1__ARB_STATUS_RF_CMD_BUSY___M 0x00010000 +#define PHYA_PHYRF_ARB_STATUS_L_B1__ARB_STATUS_RF_CMD_BUSY___S 16 +#define PHYA_PHYRF_ARB_STATUS_L_B1__ARB_STATUS_RFAPB_OVERLAPPING_PHY_CMDS___M 0x0000F000 +#define PHYA_PHYRF_ARB_STATUS_L_B1__ARB_STATUS_RFAPB_OVERLAPPING_PHY_CMDS___S 12 +#define PHYA_PHYRF_ARB_STATUS_L_B1__ARB_STATUS_RFAPB_DROPPED_CMDS___M 0x00000F00 +#define PHYA_PHYRF_ARB_STATUS_L_B1__ARB_STATUS_RFAPB_DROPPED_CMDS___S 8 +#define PHYA_PHYRF_ARB_STATUS_L_B1__ARB_STATUS_BLOCKED_CMDS___M 0x000000F0 +#define PHYA_PHYRF_ARB_STATUS_L_B1__ARB_STATUS_BLOCKED_CMDS___S 4 +#define PHYA_PHYRF_ARB_STATUS_L_B1__ARB_STATUS_ARB_SM_STATE___M 0x0000000F +#define PHYA_PHYRF_ARB_STATUS_L_B1__ARB_STATUS_ARB_SM_STATE___S 0 +#define PHYA_PHYRF_ARB_STATUS_L_B1___M 0x0001FFFF +#define PHYA_PHYRF_ARB_STATUS_L_B1___S 0 + +#define PHYA_PHYRF_ARB_CMD_CTRL_L_B0 (0x00495090) +#define PHYA_PHYRF_ARB_CMD_CTRL_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_ARB_CMD_CTRL_L_B0___POR 0x00000000 +#define PHYA_PHYRF_ARB_CMD_CTRL_L_B0__ARB_CMD_CTRL_RF_CMD___POR 0x00 +#define PHYA_PHYRF_ARB_CMD_CTRL_L_B0__ARB_CMD_CTRL_RF_CMD___M 0x000000FF +#define PHYA_PHYRF_ARB_CMD_CTRL_L_B0__ARB_CMD_CTRL_RF_CMD___S 0 +#define PHYA_PHYRF_ARB_CMD_CTRL_L_B0___M 0x000000FF +#define PHYA_PHYRF_ARB_CMD_CTRL_L_B0___S 0 + +#define PHYA_PHYRF_ARB_CMD_CTRL_L_B1 (0x0049D090) +#define PHYA_PHYRF_ARB_CMD_CTRL_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_ARB_CMD_CTRL_L_B1___POR 0x00000000 +#define PHYA_PHYRF_ARB_CMD_CTRL_L_B1__ARB_CMD_CTRL_RF_CMD___POR 0x00 +#define PHYA_PHYRF_ARB_CMD_CTRL_L_B1__ARB_CMD_CTRL_RF_CMD___M 0x000000FF +#define PHYA_PHYRF_ARB_CMD_CTRL_L_B1__ARB_CMD_CTRL_RF_CMD___S 0 +#define PHYA_PHYRF_ARB_CMD_CTRL_L_B1___M 0x000000FF +#define PHYA_PHYRF_ARB_CMD_CTRL_L_B1___S 0 + +#define PHYA_PHYRF_ARB_DATA_L_B0 (0x00495098) +#define PHYA_PHYRF_ARB_DATA_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_ARB_DATA_L_B0___POR 0x00000000 +#define PHYA_PHYRF_ARB_DATA_L_B0__ARB_DATA_ARB_CMD_WRDATA___POR 0x00000 +#define PHYA_PHYRF_ARB_DATA_L_B0__ARB_DATA_ARB_CMD_WRDATA___M 0x0003FFFF +#define PHYA_PHYRF_ARB_DATA_L_B0__ARB_DATA_ARB_CMD_WRDATA___S 0 +#define PHYA_PHYRF_ARB_DATA_L_B0___M 0x0003FFFF +#define PHYA_PHYRF_ARB_DATA_L_B0___S 0 + +#define PHYA_PHYRF_ARB_DATA_L_B1 (0x0049D098) +#define PHYA_PHYRF_ARB_DATA_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_ARB_DATA_L_B1___POR 0x00000000 +#define PHYA_PHYRF_ARB_DATA_L_B1__ARB_DATA_ARB_CMD_WRDATA___POR 0x00000 +#define PHYA_PHYRF_ARB_DATA_L_B1__ARB_DATA_ARB_CMD_WRDATA___M 0x0003FFFF +#define PHYA_PHYRF_ARB_DATA_L_B1__ARB_DATA_ARB_CMD_WRDATA___S 0 +#define PHYA_PHYRF_ARB_DATA_L_B1___M 0x0003FFFF +#define PHYA_PHYRF_ARB_DATA_L_B1___S 0 + +#define PHYA_PHYRF_ARB_CMD_ISSUE_L_B0 (0x004950A0) +#define PHYA_PHYRF_ARB_CMD_ISSUE_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_ARB_CMD_ISSUE_L_B0___POR 0x00000000 +#define PHYA_PHYRF_ARB_CMD_ISSUE_L_B0__ARB_CMD_ISSUE_ISSUE_CMD___POR 0x0 +#define PHYA_PHYRF_ARB_CMD_ISSUE_L_B0__ARB_CMD_ISSUE_ISSUE_CMD___M 0x00000001 +#define PHYA_PHYRF_ARB_CMD_ISSUE_L_B0__ARB_CMD_ISSUE_ISSUE_CMD___S 0 +#define PHYA_PHYRF_ARB_CMD_ISSUE_L_B0___M 0x00000001 +#define PHYA_PHYRF_ARB_CMD_ISSUE_L_B0___S 0 + +#define PHYA_PHYRF_ARB_CMD_ISSUE_L_B1 (0x0049D0A0) +#define PHYA_PHYRF_ARB_CMD_ISSUE_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_ARB_CMD_ISSUE_L_B1___POR 0x00000000 +#define PHYA_PHYRF_ARB_CMD_ISSUE_L_B1__ARB_CMD_ISSUE_ISSUE_CMD___POR 0x0 +#define PHYA_PHYRF_ARB_CMD_ISSUE_L_B1__ARB_CMD_ISSUE_ISSUE_CMD___M 0x00000001 +#define PHYA_PHYRF_ARB_CMD_ISSUE_L_B1__ARB_CMD_ISSUE_ISSUE_CMD___S 0 +#define PHYA_PHYRF_ARB_CMD_ISSUE_L_B1___M 0x00000001 +#define PHYA_PHYRF_ARB_CMD_ISSUE_L_B1___S 0 + +#define PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B0 (0x004950A8) +#define PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B0__RFACTRL_CLOCK_CTRL_CLKGATE_DISABLE___POR 0x0 +#define PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B0__RFACTRL_CLOCK_CTRL_FORCE_CLK_DISABLE___POR 0x0 +#define PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B0__RFACTRL_CLOCK_CTRL_CLKGATE_DISABLE___M 0x00000100 +#define PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B0__RFACTRL_CLOCK_CTRL_CLKGATE_DISABLE___S 8 +#define PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B0__RFACTRL_CLOCK_CTRL_FORCE_CLK_DISABLE___M 0x00000001 +#define PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B0__RFACTRL_CLOCK_CTRL_FORCE_CLK_DISABLE___S 0 +#define PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B0___M 0x00000101 +#define PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B0___S 0 + +#define PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B1 (0x0049D0A8) +#define PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B1__RFACTRL_CLOCK_CTRL_CLKGATE_DISABLE___POR 0x0 +#define PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B1__RFACTRL_CLOCK_CTRL_FORCE_CLK_DISABLE___POR 0x0 +#define PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B1__RFACTRL_CLOCK_CTRL_CLKGATE_DISABLE___M 0x00000100 +#define PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B1__RFACTRL_CLOCK_CTRL_CLKGATE_DISABLE___S 8 +#define PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B1__RFACTRL_CLOCK_CTRL_FORCE_CLK_DISABLE___M 0x00000001 +#define PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B1__RFACTRL_CLOCK_CTRL_FORCE_CLK_DISABLE___S 0 +#define PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B1___M 0x00000101 +#define PHYA_PHYRF_RFACTRL_CLOCK_CTRL_L_B1___S 0 + +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0 (0x004950B0) +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0__RFACTRL_RESET_CTRL_STATS_RESET___POR 0x0 +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0__RFACTRL_RESET_CTRL_PHYHW_SM_RESET___POR 0x0 +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0__RFACTRL_RESET_CTRL_RF_BUS_IF_SM_RESET___POR 0x0 +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0__RFACTRL_RESET_CTRL_ARB_SM_RESET___POR 0x0 +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0__RFACTRL_RESET_CTRL_RFAPB_SM_RESET___POR 0x0 +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0__RFACTRL_RESET_CTRL_STATS_RESET___M 0x00000010 +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0__RFACTRL_RESET_CTRL_STATS_RESET___S 4 +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0__RFACTRL_RESET_CTRL_PHYHW_SM_RESET___M 0x00000008 +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0__RFACTRL_RESET_CTRL_PHYHW_SM_RESET___S 3 +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0__RFACTRL_RESET_CTRL_RF_BUS_IF_SM_RESET___M 0x00000004 +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0__RFACTRL_RESET_CTRL_RF_BUS_IF_SM_RESET___S 2 +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0__RFACTRL_RESET_CTRL_ARB_SM_RESET___M 0x00000002 +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0__RFACTRL_RESET_CTRL_ARB_SM_RESET___S 1 +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0__RFACTRL_RESET_CTRL_RFAPB_SM_RESET___M 0x00000001 +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0__RFACTRL_RESET_CTRL_RFAPB_SM_RESET___S 0 +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0___M 0x0000001F +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B0___S 0 + +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1 (0x0049D0B0) +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1__RFACTRL_RESET_CTRL_STATS_RESET___POR 0x0 +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1__RFACTRL_RESET_CTRL_PHYHW_SM_RESET___POR 0x0 +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1__RFACTRL_RESET_CTRL_RF_BUS_IF_SM_RESET___POR 0x0 +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1__RFACTRL_RESET_CTRL_ARB_SM_RESET___POR 0x0 +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1__RFACTRL_RESET_CTRL_RFAPB_SM_RESET___POR 0x0 +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1__RFACTRL_RESET_CTRL_STATS_RESET___M 0x00000010 +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1__RFACTRL_RESET_CTRL_STATS_RESET___S 4 +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1__RFACTRL_RESET_CTRL_PHYHW_SM_RESET___M 0x00000008 +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1__RFACTRL_RESET_CTRL_PHYHW_SM_RESET___S 3 +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1__RFACTRL_RESET_CTRL_RF_BUS_IF_SM_RESET___M 0x00000004 +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1__RFACTRL_RESET_CTRL_RF_BUS_IF_SM_RESET___S 2 +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1__RFACTRL_RESET_CTRL_ARB_SM_RESET___M 0x00000002 +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1__RFACTRL_RESET_CTRL_ARB_SM_RESET___S 1 +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1__RFACTRL_RESET_CTRL_RFAPB_SM_RESET___M 0x00000001 +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1__RFACTRL_RESET_CTRL_RFAPB_SM_RESET___S 0 +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1___M 0x0000001F +#define PHYA_PHYRF_RFACTRL_RESET_CTRL_L_B1___S 0 + +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0 (0x004950B8) +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0___RWC QCSR_REG_RO +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0___POR 0x00000000 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_TPCRB_STATE___POR 0x0 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_RXDCOC_STATE___POR 0x0 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_RFCAL_STATE___POR 0x0 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_SYNEN_STATE___POR 0x0 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_DEBUG_STATE___POR 0x0 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_MODE_STATE___POR 0x0 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_TXGAIN_STATE___POR 0x0 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_RXGAIN_STATE___POR 0x0 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_TPCRB_STATE___M 0x00E00000 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_TPCRB_STATE___S 21 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_RXDCOC_STATE___M 0x001C0000 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_RXDCOC_STATE___S 18 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_RFCAL_STATE___M 0x00038000 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_RFCAL_STATE___S 15 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_SYNEN_STATE___M 0x00007000 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_SYNEN_STATE___S 12 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_DEBUG_STATE___M 0x00000E00 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_DEBUG_STATE___S 9 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_MODE_STATE___M 0x000001C0 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_MODE_STATE___S 6 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_TXGAIN_STATE___M 0x00000038 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_TXGAIN_STATE___S 3 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_RXGAIN_STATE___M 0x00000007 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0__PHY_HW_SM_STATUS_RXGAIN_STATE___S 0 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0___M 0x00FFFFFF +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B0___S 0 + +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1 (0x0049D0B8) +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1___RWC QCSR_REG_RO +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1___POR 0x00000000 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_TPCRB_STATE___POR 0x0 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_RXDCOC_STATE___POR 0x0 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_RFCAL_STATE___POR 0x0 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_SYNEN_STATE___POR 0x0 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_DEBUG_STATE___POR 0x0 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_MODE_STATE___POR 0x0 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_TXGAIN_STATE___POR 0x0 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_RXGAIN_STATE___POR 0x0 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_TPCRB_STATE___M 0x00E00000 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_TPCRB_STATE___S 21 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_RXDCOC_STATE___M 0x001C0000 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_RXDCOC_STATE___S 18 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_RFCAL_STATE___M 0x00038000 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_RFCAL_STATE___S 15 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_SYNEN_STATE___M 0x00007000 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_SYNEN_STATE___S 12 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_DEBUG_STATE___M 0x00000E00 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_DEBUG_STATE___S 9 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_MODE_STATE___M 0x000001C0 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_MODE_STATE___S 6 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_TXGAIN_STATE___M 0x00000038 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_TXGAIN_STATE___S 3 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_RXGAIN_STATE___M 0x00000007 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1__PHY_HW_SM_STATUS_RXGAIN_STATE___S 0 +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1___M 0x00FFFFFF +#define PHYA_PHYRF_PHY_HW_SM_STATUS_L_B1___S 0 + +#define PHYA_PHYRF_PHY_HW_DROPPED_CMDS_L_B0 (0x004950C0) +#define PHYA_PHYRF_PHY_HW_DROPPED_CMDS_L_B0___RWC QCSR_REG_RO +#define PHYA_PHYRF_PHY_HW_DROPPED_CMDS_L_B0___POR 0x00000000 +#define PHYA_PHYRF_PHY_HW_DROPPED_CMDS_L_B0__PHY_HW_DROPPED_CMDS_PHYHW_DROPPED_CMDS___POR 0x00 +#define PHYA_PHYRF_PHY_HW_DROPPED_CMDS_L_B0__PHY_HW_DROPPED_CMDS_PHYHW_DROPPED_CMDS___M 0x0000003F +#define PHYA_PHYRF_PHY_HW_DROPPED_CMDS_L_B0__PHY_HW_DROPPED_CMDS_PHYHW_DROPPED_CMDS___S 0 +#define PHYA_PHYRF_PHY_HW_DROPPED_CMDS_L_B0___M 0x0000003F +#define PHYA_PHYRF_PHY_HW_DROPPED_CMDS_L_B0___S 0 + +#define PHYA_PHYRF_PHY_HW_DROPPED_CMDS_L_B1 (0x0049D0C0) +#define PHYA_PHYRF_PHY_HW_DROPPED_CMDS_L_B1___RWC QCSR_REG_RO +#define PHYA_PHYRF_PHY_HW_DROPPED_CMDS_L_B1___POR 0x00000000 +#define PHYA_PHYRF_PHY_HW_DROPPED_CMDS_L_B1__PHY_HW_DROPPED_CMDS_PHYHW_DROPPED_CMDS___POR 0x00 +#define PHYA_PHYRF_PHY_HW_DROPPED_CMDS_L_B1__PHY_HW_DROPPED_CMDS_PHYHW_DROPPED_CMDS___M 0x0000003F +#define PHYA_PHYRF_PHY_HW_DROPPED_CMDS_L_B1__PHY_HW_DROPPED_CMDS_PHYHW_DROPPED_CMDS___S 0 +#define PHYA_PHYRF_PHY_HW_DROPPED_CMDS_L_B1___M 0x0000003F +#define PHYA_PHYRF_PHY_HW_DROPPED_CMDS_L_B1___S 0 + +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0 (0x004950C8) +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0___POR 0x00000000 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_TPCRB_TIMEOUT___POR 0x0 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_RXDCOC_TIMEOUT___POR 0x0 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_RFCAL_TIMEOUT___POR 0x0 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_SYNEN_TIMEOUT___POR 0x0 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_DEBUG_TIMEOUT___POR 0x0 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_MODE_TIMEOUT___POR 0x0 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_TXGAIN_TIMEOUT___POR 0x0 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_RXGAIN_TIMEOUT___POR 0x0 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_TPCRB_TIMEOUT___M 0x00000080 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_TPCRB_TIMEOUT___S 7 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_RXDCOC_TIMEOUT___M 0x00000040 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_RXDCOC_TIMEOUT___S 6 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_RFCAL_TIMEOUT___M 0x00000020 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_RFCAL_TIMEOUT___S 5 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_SYNEN_TIMEOUT___M 0x00000010 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_SYNEN_TIMEOUT___S 4 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_DEBUG_TIMEOUT___M 0x00000008 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_DEBUG_TIMEOUT___S 3 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_MODE_TIMEOUT___M 0x00000004 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_MODE_TIMEOUT___S 2 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_TXGAIN_TIMEOUT___M 0x00000002 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_TXGAIN_TIMEOUT___S 1 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_RXGAIN_TIMEOUT___M 0x00000001 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0__PHY_HW_TIMEOUT_CTRL_ENBL_RXGAIN_TIMEOUT___S 0 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0___M 0x000000FF +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B0___S 0 + +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1 (0x0049D0C8) +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1___POR 0x00000000 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_TPCRB_TIMEOUT___POR 0x0 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_RXDCOC_TIMEOUT___POR 0x0 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_RFCAL_TIMEOUT___POR 0x0 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_SYNEN_TIMEOUT___POR 0x0 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_DEBUG_TIMEOUT___POR 0x0 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_MODE_TIMEOUT___POR 0x0 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_TXGAIN_TIMEOUT___POR 0x0 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_RXGAIN_TIMEOUT___POR 0x0 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_TPCRB_TIMEOUT___M 0x00000080 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_TPCRB_TIMEOUT___S 7 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_RXDCOC_TIMEOUT___M 0x00000040 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_RXDCOC_TIMEOUT___S 6 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_RFCAL_TIMEOUT___M 0x00000020 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_RFCAL_TIMEOUT___S 5 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_SYNEN_TIMEOUT___M 0x00000010 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_SYNEN_TIMEOUT___S 4 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_DEBUG_TIMEOUT___M 0x00000008 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_DEBUG_TIMEOUT___S 3 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_MODE_TIMEOUT___M 0x00000004 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_MODE_TIMEOUT___S 2 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_TXGAIN_TIMEOUT___M 0x00000002 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_TXGAIN_TIMEOUT___S 1 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_RXGAIN_TIMEOUT___M 0x00000001 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1__PHY_HW_TIMEOUT_CTRL_ENBL_RXGAIN_TIMEOUT___S 0 +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1___M 0x000000FF +#define PHYA_PHYRF_PHY_HW_TIMEOUT_CTRL_L_B1___S 0 + +#define PHYA_PHYRF_PHYHW_TIMEOUT_L_B0 (0x004950D0) +#define PHYA_PHYRF_PHYHW_TIMEOUT_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYHW_TIMEOUT_L_B0___POR 0x00000000 +#define PHYA_PHYRF_PHYHW_TIMEOUT_L_B0__PHYHW_TIMEOUT_SET_PHYCMDS_TIMEOUT___POR 0x000 +#define PHYA_PHYRF_PHYHW_TIMEOUT_L_B0__PHYHW_TIMEOUT_SET_PHYCMDS_TIMEOUT___M 0x000007FF +#define PHYA_PHYRF_PHYHW_TIMEOUT_L_B0__PHYHW_TIMEOUT_SET_PHYCMDS_TIMEOUT___S 0 +#define PHYA_PHYRF_PHYHW_TIMEOUT_L_B0___M 0x000007FF +#define PHYA_PHYRF_PHYHW_TIMEOUT_L_B0___S 0 + +#define PHYA_PHYRF_PHYHW_TIMEOUT_L_B1 (0x0049D0D0) +#define PHYA_PHYRF_PHYHW_TIMEOUT_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYHW_TIMEOUT_L_B1___POR 0x00000000 +#define PHYA_PHYRF_PHYHW_TIMEOUT_L_B1__PHYHW_TIMEOUT_SET_PHYCMDS_TIMEOUT___POR 0x000 +#define PHYA_PHYRF_PHYHW_TIMEOUT_L_B1__PHYHW_TIMEOUT_SET_PHYCMDS_TIMEOUT___M 0x000007FF +#define PHYA_PHYRF_PHYHW_TIMEOUT_L_B1__PHYHW_TIMEOUT_SET_PHYCMDS_TIMEOUT___S 0 +#define PHYA_PHYRF_PHYHW_TIMEOUT_L_B1___M 0x000007FF +#define PHYA_PHYRF_PHYHW_TIMEOUT_L_B1___S 0 + +#define PHYA_PHYRF_RFAPB_TIMEOUT_L_B0 (0x004950D8) +#define PHYA_PHYRF_RFAPB_TIMEOUT_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RFAPB_TIMEOUT_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RFAPB_TIMEOUT_L_B0__RFAPB_TIMEOUT_SET_RFAPB_TIMEOUT___POR 0x000 +#define PHYA_PHYRF_RFAPB_TIMEOUT_L_B0__RFAPB_TIMEOUT_SET_RFAPB_TIMEOUT___M 0x000007FF +#define PHYA_PHYRF_RFAPB_TIMEOUT_L_B0__RFAPB_TIMEOUT_SET_RFAPB_TIMEOUT___S 0 +#define PHYA_PHYRF_RFAPB_TIMEOUT_L_B0___M 0x000007FF +#define PHYA_PHYRF_RFAPB_TIMEOUT_L_B0___S 0 + +#define PHYA_PHYRF_RFAPB_TIMEOUT_L_B1 (0x0049D0D8) +#define PHYA_PHYRF_RFAPB_TIMEOUT_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RFAPB_TIMEOUT_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RFAPB_TIMEOUT_L_B1__RFAPB_TIMEOUT_SET_RFAPB_TIMEOUT___POR 0x000 +#define PHYA_PHYRF_RFAPB_TIMEOUT_L_B1__RFAPB_TIMEOUT_SET_RFAPB_TIMEOUT___M 0x000007FF +#define PHYA_PHYRF_RFAPB_TIMEOUT_L_B1__RFAPB_TIMEOUT_SET_RFAPB_TIMEOUT___S 0 +#define PHYA_PHYRF_RFAPB_TIMEOUT_L_B1___M 0x000007FF +#define PHYA_PHYRF_RFAPB_TIMEOUT_L_B1___S 0 + +#define PHYA_PHYRF_RFAPB_STATUS_L_B0 (0x004950E0) +#define PHYA_PHYRF_RFAPB_STATUS_L_B0___RWC QCSR_REG_RO +#define PHYA_PHYRF_RFAPB_STATUS_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RFAPB_STATUS_L_B0__RFAPB_STATUS_RFAPB_SM_STATE___POR 0x0 +#define PHYA_PHYRF_RFAPB_STATUS_L_B0__RFAPB_STATUS_RFAPB_SM_STATE___M 0x00000007 +#define PHYA_PHYRF_RFAPB_STATUS_L_B0__RFAPB_STATUS_RFAPB_SM_STATE___S 0 +#define PHYA_PHYRF_RFAPB_STATUS_L_B0___M 0x00000007 +#define PHYA_PHYRF_RFAPB_STATUS_L_B0___S 0 + +#define PHYA_PHYRF_RFAPB_STATUS_L_B1 (0x0049D0E0) +#define PHYA_PHYRF_RFAPB_STATUS_L_B1___RWC QCSR_REG_RO +#define PHYA_PHYRF_RFAPB_STATUS_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RFAPB_STATUS_L_B1__RFAPB_STATUS_RFAPB_SM_STATE___POR 0x0 +#define PHYA_PHYRF_RFAPB_STATUS_L_B1__RFAPB_STATUS_RFAPB_SM_STATE___M 0x00000007 +#define PHYA_PHYRF_RFAPB_STATUS_L_B1__RFAPB_STATUS_RFAPB_SM_STATE___S 0 +#define PHYA_PHYRF_RFAPB_STATUS_L_B1___M 0x00000007 +#define PHYA_PHYRF_RFAPB_STATUS_L_B1___S 0 + +#define PHYA_PHYRF_ERR_CONDS_L_B0 (0x004950E8) +#define PHYA_PHYRF_ERR_CONDS_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_ERR_CONDS_L_B0___POR 0x00000000 +#define PHYA_PHYRF_ERR_CONDS_L_B0__ERR_CONDS_WR_FIFO_RD_EMPTY_ERR___POR 0x0 +#define PHYA_PHYRF_ERR_CONDS_L_B0__ERR_CONDS_WR_FIFO_RD_EMPTY_ERR___M 0x00000001 +#define PHYA_PHYRF_ERR_CONDS_L_B0__ERR_CONDS_WR_FIFO_RD_EMPTY_ERR___S 0 +#define PHYA_PHYRF_ERR_CONDS_L_B0___M 0x00000001 +#define PHYA_PHYRF_ERR_CONDS_L_B0___S 0 + +#define PHYA_PHYRF_ERR_CONDS_L_B1 (0x0049D0E8) +#define PHYA_PHYRF_ERR_CONDS_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_ERR_CONDS_L_B1___POR 0x00000000 +#define PHYA_PHYRF_ERR_CONDS_L_B1__ERR_CONDS_WR_FIFO_RD_EMPTY_ERR___POR 0x0 +#define PHYA_PHYRF_ERR_CONDS_L_B1__ERR_CONDS_WR_FIFO_RD_EMPTY_ERR___M 0x00000001 +#define PHYA_PHYRF_ERR_CONDS_L_B1__ERR_CONDS_WR_FIFO_RD_EMPTY_ERR___S 0 +#define PHYA_PHYRF_ERR_CONDS_L_B1___M 0x00000001 +#define PHYA_PHYRF_ERR_CONDS_L_B1___S 0 + +#define PHYA_PHYRF_RFSAT_RD_DELAY_L_B0 (0x004950F0) +#define PHYA_PHYRF_RFSAT_RD_DELAY_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RFSAT_RD_DELAY_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RFSAT_RD_DELAY_L_B0__RFSAT_RD_DELAY_VAL___POR 0x000 +#define PHYA_PHYRF_RFSAT_RD_DELAY_L_B0__RFSAT_RD_DELAY_VAL___M 0x000007FF +#define PHYA_PHYRF_RFSAT_RD_DELAY_L_B0__RFSAT_RD_DELAY_VAL___S 0 +#define PHYA_PHYRF_RFSAT_RD_DELAY_L_B0___M 0x000007FF +#define PHYA_PHYRF_RFSAT_RD_DELAY_L_B0___S 0 + +#define PHYA_PHYRF_RFSAT_RD_DELAY_L_B1 (0x0049D0F0) +#define PHYA_PHYRF_RFSAT_RD_DELAY_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RFSAT_RD_DELAY_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RFSAT_RD_DELAY_L_B1__RFSAT_RD_DELAY_VAL___POR 0x000 +#define PHYA_PHYRF_RFSAT_RD_DELAY_L_B1__RFSAT_RD_DELAY_VAL___M 0x000007FF +#define PHYA_PHYRF_RFSAT_RD_DELAY_L_B1__RFSAT_RD_DELAY_VAL___S 0 +#define PHYA_PHYRF_RFSAT_RD_DELAY_L_B1___M 0x000007FF +#define PHYA_PHYRF_RFSAT_RD_DELAY_L_B1___S 0 + +#define PHYA_PHYRF_SYNEN_WR_ADDR_L_B0 (0x004950F8) +#define PHYA_PHYRF_SYNEN_WR_ADDR_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_SYNEN_WR_ADDR_L_B0___POR 0x00000000 +#define PHYA_PHYRF_SYNEN_WR_ADDR_L_B0__SYNEN_WR_ADDR_VAL___POR 0x0000 +#define PHYA_PHYRF_SYNEN_WR_ADDR_L_B0__SYNEN_WR_ADDR_VAL___M 0x0000FFFF +#define PHYA_PHYRF_SYNEN_WR_ADDR_L_B0__SYNEN_WR_ADDR_VAL___S 0 +#define PHYA_PHYRF_SYNEN_WR_ADDR_L_B0___M 0x0000FFFF +#define PHYA_PHYRF_SYNEN_WR_ADDR_L_B0___S 0 + +#define PHYA_PHYRF_SYNEN_WR_ADDR_L_B1 (0x0049D0F8) +#define PHYA_PHYRF_SYNEN_WR_ADDR_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_SYNEN_WR_ADDR_L_B1___POR 0x00000000 +#define PHYA_PHYRF_SYNEN_WR_ADDR_L_B1__SYNEN_WR_ADDR_VAL___POR 0x0000 +#define PHYA_PHYRF_SYNEN_WR_ADDR_L_B1__SYNEN_WR_ADDR_VAL___M 0x0000FFFF +#define PHYA_PHYRF_SYNEN_WR_ADDR_L_B1__SYNEN_WR_ADDR_VAL___S 0 +#define PHYA_PHYRF_SYNEN_WR_ADDR_L_B1___M 0x0000FFFF +#define PHYA_PHYRF_SYNEN_WR_ADDR_L_B1___S 0 + +#define PHYA_PHYRF_RFCAL_WR_ADDR_L_B0 (0x00495100) +#define PHYA_PHYRF_RFCAL_WR_ADDR_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RFCAL_WR_ADDR_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RFCAL_WR_ADDR_L_B0__RFCAL_WR_ADDR_VAL___POR 0x0000 +#define PHYA_PHYRF_RFCAL_WR_ADDR_L_B0__RFCAL_WR_ADDR_VAL___M 0x0000FFFF +#define PHYA_PHYRF_RFCAL_WR_ADDR_L_B0__RFCAL_WR_ADDR_VAL___S 0 +#define PHYA_PHYRF_RFCAL_WR_ADDR_L_B0___M 0x0000FFFF +#define PHYA_PHYRF_RFCAL_WR_ADDR_L_B0___S 0 + +#define PHYA_PHYRF_RFCAL_WR_ADDR_L_B1 (0x0049D100) +#define PHYA_PHYRF_RFCAL_WR_ADDR_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RFCAL_WR_ADDR_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RFCAL_WR_ADDR_L_B1__RFCAL_WR_ADDR_VAL___POR 0x0000 +#define PHYA_PHYRF_RFCAL_WR_ADDR_L_B1__RFCAL_WR_ADDR_VAL___M 0x0000FFFF +#define PHYA_PHYRF_RFCAL_WR_ADDR_L_B1__RFCAL_WR_ADDR_VAL___S 0 +#define PHYA_PHYRF_RFCAL_WR_ADDR_L_B1___M 0x0000FFFF +#define PHYA_PHYRF_RFCAL_WR_ADDR_L_B1___S 0 + +#define PHYA_PHYRF_RXDCOC_WR_ADDR_L_B0 (0x00495108) +#define PHYA_PHYRF_RXDCOC_WR_ADDR_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXDCOC_WR_ADDR_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RXDCOC_WR_ADDR_L_B0__RXDCOC_WR_ADDR_VAL___POR 0x0000 +#define PHYA_PHYRF_RXDCOC_WR_ADDR_L_B0__RXDCOC_WR_ADDR_VAL___M 0x0000FFFF +#define PHYA_PHYRF_RXDCOC_WR_ADDR_L_B0__RXDCOC_WR_ADDR_VAL___S 0 +#define PHYA_PHYRF_RXDCOC_WR_ADDR_L_B0___M 0x0000FFFF +#define PHYA_PHYRF_RXDCOC_WR_ADDR_L_B0___S 0 + +#define PHYA_PHYRF_RXDCOC_WR_ADDR_L_B1 (0x0049D108) +#define PHYA_PHYRF_RXDCOC_WR_ADDR_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RXDCOC_WR_ADDR_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RXDCOC_WR_ADDR_L_B1__RXDCOC_WR_ADDR_VAL___POR 0x0000 +#define PHYA_PHYRF_RXDCOC_WR_ADDR_L_B1__RXDCOC_WR_ADDR_VAL___M 0x0000FFFF +#define PHYA_PHYRF_RXDCOC_WR_ADDR_L_B1__RXDCOC_WR_ADDR_VAL___S 0 +#define PHYA_PHYRF_RXDCOC_WR_ADDR_L_B1___M 0x0000FFFF +#define PHYA_PHYRF_RXDCOC_WR_ADDR_L_B1___S 0 + +#define PHYA_PHYRF_TPCRB_RD_ADDR_L_B0 (0x00495110) +#define PHYA_PHYRF_TPCRB_RD_ADDR_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPCRB_RD_ADDR_L_B0___POR 0x00000000 +#define PHYA_PHYRF_TPCRB_RD_ADDR_L_B0__TPCRB_RD_ADDR_VAL___POR 0x0000 +#define PHYA_PHYRF_TPCRB_RD_ADDR_L_B0__TPCRB_RD_ADDR_VAL___M 0x0000FFFF +#define PHYA_PHYRF_TPCRB_RD_ADDR_L_B0__TPCRB_RD_ADDR_VAL___S 0 +#define PHYA_PHYRF_TPCRB_RD_ADDR_L_B0___M 0x0000FFFF +#define PHYA_PHYRF_TPCRB_RD_ADDR_L_B0___S 0 + +#define PHYA_PHYRF_TPCRB_RD_ADDR_L_B1 (0x0049D110) +#define PHYA_PHYRF_TPCRB_RD_ADDR_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_TPCRB_RD_ADDR_L_B1___POR 0x00000000 +#define PHYA_PHYRF_TPCRB_RD_ADDR_L_B1__TPCRB_RD_ADDR_VAL___POR 0x0000 +#define PHYA_PHYRF_TPCRB_RD_ADDR_L_B1__TPCRB_RD_ADDR_VAL___M 0x0000FFFF +#define PHYA_PHYRF_TPCRB_RD_ADDR_L_B1__TPCRB_RD_ADDR_VAL___S 0 +#define PHYA_PHYRF_TPCRB_RD_ADDR_L_B1___M 0x0000FFFF +#define PHYA_PHYRF_TPCRB_RD_ADDR_L_B1___S 0 + +#define PHYA_PHYRF_WSI_DEBUG_CTRL_L_B0 (0x00495118) +#define PHYA_PHYRF_WSI_DEBUG_CTRL_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_WSI_DEBUG_CTRL_L_B0___POR 0x00000000 +#define PHYA_PHYRF_WSI_DEBUG_CTRL_L_B0__WSI_DEBUG_CTRL_SEL_WSI_TESTBUS___POR 0x0 +#define PHYA_PHYRF_WSI_DEBUG_CTRL_L_B0__WSI_DEBUG_CTRL_IGNORE_ACK___POR 0x0 +#define PHYA_PHYRF_WSI_DEBUG_CTRL_L_B0__WSI_DEBUG_CTRL_FORCE_ERROR___POR 0x0 +#define PHYA_PHYRF_WSI_DEBUG_CTRL_L_B0__WSI_DEBUG_CTRL_SEL_WSI_TESTBUS___M 0x00010000 +#define PHYA_PHYRF_WSI_DEBUG_CTRL_L_B0__WSI_DEBUG_CTRL_SEL_WSI_TESTBUS___S 16 +#define PHYA_PHYRF_WSI_DEBUG_CTRL_L_B0__WSI_DEBUG_CTRL_IGNORE_ACK___M 0x00000100 +#define PHYA_PHYRF_WSI_DEBUG_CTRL_L_B0__WSI_DEBUG_CTRL_IGNORE_ACK___S 8 +#define PHYA_PHYRF_WSI_DEBUG_CTRL_L_B0__WSI_DEBUG_CTRL_FORCE_ERROR___M 0x00000001 +#define PHYA_PHYRF_WSI_DEBUG_CTRL_L_B0__WSI_DEBUG_CTRL_FORCE_ERROR___S 0 +#define PHYA_PHYRF_WSI_DEBUG_CTRL_L_B0___M 0x00010101 +#define PHYA_PHYRF_WSI_DEBUG_CTRL_L_B0___S 0 + +#define PHYA_PHYRF_WSI_DEBUG_CTRL_L_B1 (0x0049D118) +#define PHYA_PHYRF_WSI_DEBUG_CTRL_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_WSI_DEBUG_CTRL_L_B1___POR 0x00000000 +#define PHYA_PHYRF_WSI_DEBUG_CTRL_L_B1__WSI_DEBUG_CTRL_SEL_WSI_TESTBUS___POR 0x0 +#define PHYA_PHYRF_WSI_DEBUG_CTRL_L_B1__WSI_DEBUG_CTRL_IGNORE_ACK___POR 0x0 +#define PHYA_PHYRF_WSI_DEBUG_CTRL_L_B1__WSI_DEBUG_CTRL_FORCE_ERROR___POR 0x0 +#define PHYA_PHYRF_WSI_DEBUG_CTRL_L_B1__WSI_DEBUG_CTRL_SEL_WSI_TESTBUS___M 0x00010000 +#define PHYA_PHYRF_WSI_DEBUG_CTRL_L_B1__WSI_DEBUG_CTRL_SEL_WSI_TESTBUS___S 16 +#define PHYA_PHYRF_WSI_DEBUG_CTRL_L_B1__WSI_DEBUG_CTRL_IGNORE_ACK___M 0x00000100 +#define PHYA_PHYRF_WSI_DEBUG_CTRL_L_B1__WSI_DEBUG_CTRL_IGNORE_ACK___S 8 +#define PHYA_PHYRF_WSI_DEBUG_CTRL_L_B1__WSI_DEBUG_CTRL_FORCE_ERROR___M 0x00000001 +#define PHYA_PHYRF_WSI_DEBUG_CTRL_L_B1__WSI_DEBUG_CTRL_FORCE_ERROR___S 0 +#define PHYA_PHYRF_WSI_DEBUG_CTRL_L_B1___M 0x00010101 +#define PHYA_PHYRF_WSI_DEBUG_CTRL_L_B1___S 0 + +#define PHYA_PHYRF_RF_REG_CMD_L_B0 (0x00495120) +#define PHYA_PHYRF_RF_REG_CMD_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_REG_CMD_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RF_REG_CMD_L_B0__RF_REG_CMD_RWN___POR 0x0 +#define PHYA_PHYRF_RF_REG_CMD_L_B0__RF_REG_CMD_BUSY___POR 0x0 +#define PHYA_PHYRF_RF_REG_CMD_L_B0__RF_REG_CMD_RWN___M 0x00000100 +#define PHYA_PHYRF_RF_REG_CMD_L_B0__RF_REG_CMD_RWN___S 8 +#define PHYA_PHYRF_RF_REG_CMD_L_B0__RF_REG_CMD_BUSY___M 0x00000001 +#define PHYA_PHYRF_RF_REG_CMD_L_B0__RF_REG_CMD_BUSY___S 0 +#define PHYA_PHYRF_RF_REG_CMD_L_B0___M 0x00000101 +#define PHYA_PHYRF_RF_REG_CMD_L_B0___S 0 + +#define PHYA_PHYRF_RF_REG_CMD_L_B1 (0x0049D120) +#define PHYA_PHYRF_RF_REG_CMD_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_REG_CMD_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RF_REG_CMD_L_B1__RF_REG_CMD_RWN___POR 0x0 +#define PHYA_PHYRF_RF_REG_CMD_L_B1__RF_REG_CMD_BUSY___POR 0x0 +#define PHYA_PHYRF_RF_REG_CMD_L_B1__RF_REG_CMD_RWN___M 0x00000100 +#define PHYA_PHYRF_RF_REG_CMD_L_B1__RF_REG_CMD_RWN___S 8 +#define PHYA_PHYRF_RF_REG_CMD_L_B1__RF_REG_CMD_BUSY___M 0x00000001 +#define PHYA_PHYRF_RF_REG_CMD_L_B1__RF_REG_CMD_BUSY___S 0 +#define PHYA_PHYRF_RF_REG_CMD_L_B1___M 0x00000101 +#define PHYA_PHYRF_RF_REG_CMD_L_B1___S 0 + +#define PHYA_PHYRF_RF_REG_ADDR_L_B0 (0x00495128) +#define PHYA_PHYRF_RF_REG_ADDR_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_REG_ADDR_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RF_REG_ADDR_L_B0__RF_REG_ADDR_CMD_ADDR___POR 0x0000 +#define PHYA_PHYRF_RF_REG_ADDR_L_B0__RF_REG_ADDR_CMD_ADDR___M 0x0000FFFF +#define PHYA_PHYRF_RF_REG_ADDR_L_B0__RF_REG_ADDR_CMD_ADDR___S 0 +#define PHYA_PHYRF_RF_REG_ADDR_L_B0___M 0x0000FFFF +#define PHYA_PHYRF_RF_REG_ADDR_L_B0___S 0 + +#define PHYA_PHYRF_RF_REG_ADDR_L_B1 (0x0049D128) +#define PHYA_PHYRF_RF_REG_ADDR_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_REG_ADDR_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RF_REG_ADDR_L_B1__RF_REG_ADDR_CMD_ADDR___POR 0x0000 +#define PHYA_PHYRF_RF_REG_ADDR_L_B1__RF_REG_ADDR_CMD_ADDR___M 0x0000FFFF +#define PHYA_PHYRF_RF_REG_ADDR_L_B1__RF_REG_ADDR_CMD_ADDR___S 0 +#define PHYA_PHYRF_RF_REG_ADDR_L_B1___M 0x0000FFFF +#define PHYA_PHYRF_RF_REG_ADDR_L_B1___S 0 + +#define PHYA_PHYRF_RF_REG_WDATA_L_B0 (0x00495130) +#define PHYA_PHYRF_RF_REG_WDATA_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_REG_WDATA_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RF_REG_WDATA_L_B0__RF_REG_WDATA_CMD_WDATA___POR 0x00000000 +#define PHYA_PHYRF_RF_REG_WDATA_L_B0__RF_REG_WDATA_CMD_WDATA___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_REG_WDATA_L_B0__RF_REG_WDATA_CMD_WDATA___S 0 +#define PHYA_PHYRF_RF_REG_WDATA_L_B0___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_REG_WDATA_L_B0___S 0 + +#define PHYA_PHYRF_RF_REG_WDATA_L_B1 (0x0049D130) +#define PHYA_PHYRF_RF_REG_WDATA_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_REG_WDATA_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RF_REG_WDATA_L_B1__RF_REG_WDATA_CMD_WDATA___POR 0x00000000 +#define PHYA_PHYRF_RF_REG_WDATA_L_B1__RF_REG_WDATA_CMD_WDATA___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_REG_WDATA_L_B1__RF_REG_WDATA_CMD_WDATA___S 0 +#define PHYA_PHYRF_RF_REG_WDATA_L_B1___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_REG_WDATA_L_B1___S 0 + +#define PHYA_PHYRF_RF_REG_RDATA_L_B0 (0x00495138) +#define PHYA_PHYRF_RF_REG_RDATA_L_B0___RWC QCSR_REG_RO +#define PHYA_PHYRF_RF_REG_RDATA_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RF_REG_RDATA_L_B0__RF_REG_RDATA_CMD_RDATA___POR 0x00000000 +#define PHYA_PHYRF_RF_REG_RDATA_L_B0__RF_REG_RDATA_CMD_RDATA___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_REG_RDATA_L_B0__RF_REG_RDATA_CMD_RDATA___S 0 +#define PHYA_PHYRF_RF_REG_RDATA_L_B0___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_REG_RDATA_L_B0___S 0 + +#define PHYA_PHYRF_RF_REG_RDATA_L_B1 (0x0049D138) +#define PHYA_PHYRF_RF_REG_RDATA_L_B1___RWC QCSR_REG_RO +#define PHYA_PHYRF_RF_REG_RDATA_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RF_REG_RDATA_L_B1__RF_REG_RDATA_CMD_RDATA___POR 0x00000000 +#define PHYA_PHYRF_RF_REG_RDATA_L_B1__RF_REG_RDATA_CMD_RDATA___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_REG_RDATA_L_B1__RF_REG_RDATA_CMD_RDATA___S 0 +#define PHYA_PHYRF_RF_REG_RDATA_L_B1___M 0xFFFFFFFF +#define PHYA_PHYRF_RF_REG_RDATA_L_B1___S 0 + +#define PHYA_PHYRF_RF_REG_CMD_ISSUE_L_B0 (0x00495140) +#define PHYA_PHYRF_RF_REG_CMD_ISSUE_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_REG_CMD_ISSUE_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RF_REG_CMD_ISSUE_L_B0__RF_REG_CMD_ISSUE_START___POR 0x0 +#define PHYA_PHYRF_RF_REG_CMD_ISSUE_L_B0__RF_REG_CMD_ISSUE_START___M 0x00000001 +#define PHYA_PHYRF_RF_REG_CMD_ISSUE_L_B0__RF_REG_CMD_ISSUE_START___S 0 +#define PHYA_PHYRF_RF_REG_CMD_ISSUE_L_B0___M 0x00000001 +#define PHYA_PHYRF_RF_REG_CMD_ISSUE_L_B0___S 0 + +#define PHYA_PHYRF_RF_REG_CMD_ISSUE_L_B1 (0x0049D140) +#define PHYA_PHYRF_RF_REG_CMD_ISSUE_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RF_REG_CMD_ISSUE_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RF_REG_CMD_ISSUE_L_B1__RF_REG_CMD_ISSUE_START___POR 0x0 +#define PHYA_PHYRF_RF_REG_CMD_ISSUE_L_B1__RF_REG_CMD_ISSUE_START___M 0x00000001 +#define PHYA_PHYRF_RF_REG_CMD_ISSUE_L_B1__RF_REG_CMD_ISSUE_START___S 0 +#define PHYA_PHYRF_RF_REG_CMD_ISSUE_L_B1___M 0x00000001 +#define PHYA_PHYRF_RF_REG_CMD_ISSUE_L_B1___S 0 + +#define PHYA_PHYRF_CMD_COUNT_RFAPB_WR_L_B0 (0x00495148) +#define PHYA_PHYRF_CMD_COUNT_RFAPB_WR_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_CMD_COUNT_RFAPB_WR_L_B0___POR 0x00000000 +#define PHYA_PHYRF_CMD_COUNT_RFAPB_WR_L_B0__CMD_COUNT_RFAPB_WR_COUNT___POR 0x0000 +#define PHYA_PHYRF_CMD_COUNT_RFAPB_WR_L_B0__CMD_COUNT_RFAPB_WR_COUNT___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_RFAPB_WR_L_B0__CMD_COUNT_RFAPB_WR_COUNT___S 0 +#define PHYA_PHYRF_CMD_COUNT_RFAPB_WR_L_B0___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_RFAPB_WR_L_B0___S 0 + +#define PHYA_PHYRF_CMD_COUNT_RFAPB_WR_L_B1 (0x0049D148) +#define PHYA_PHYRF_CMD_COUNT_RFAPB_WR_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_CMD_COUNT_RFAPB_WR_L_B1___POR 0x00000000 +#define PHYA_PHYRF_CMD_COUNT_RFAPB_WR_L_B1__CMD_COUNT_RFAPB_WR_COUNT___POR 0x0000 +#define PHYA_PHYRF_CMD_COUNT_RFAPB_WR_L_B1__CMD_COUNT_RFAPB_WR_COUNT___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_RFAPB_WR_L_B1__CMD_COUNT_RFAPB_WR_COUNT___S 0 +#define PHYA_PHYRF_CMD_COUNT_RFAPB_WR_L_B1___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_RFAPB_WR_L_B1___S 0 + +#define PHYA_PHYRF_CMD_COUNT_RFAPB_RD_L_B0 (0x00495150) +#define PHYA_PHYRF_CMD_COUNT_RFAPB_RD_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_CMD_COUNT_RFAPB_RD_L_B0___POR 0x00000000 +#define PHYA_PHYRF_CMD_COUNT_RFAPB_RD_L_B0__CMD_COUNT_RFAPB_RD_COUNT___POR 0x0000 +#define PHYA_PHYRF_CMD_COUNT_RFAPB_RD_L_B0__CMD_COUNT_RFAPB_RD_COUNT___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_RFAPB_RD_L_B0__CMD_COUNT_RFAPB_RD_COUNT___S 0 +#define PHYA_PHYRF_CMD_COUNT_RFAPB_RD_L_B0___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_RFAPB_RD_L_B0___S 0 + +#define PHYA_PHYRF_CMD_COUNT_RFAPB_RD_L_B1 (0x0049D150) +#define PHYA_PHYRF_CMD_COUNT_RFAPB_RD_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_CMD_COUNT_RFAPB_RD_L_B1___POR 0x00000000 +#define PHYA_PHYRF_CMD_COUNT_RFAPB_RD_L_B1__CMD_COUNT_RFAPB_RD_COUNT___POR 0x0000 +#define PHYA_PHYRF_CMD_COUNT_RFAPB_RD_L_B1__CMD_COUNT_RFAPB_RD_COUNT___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_RFAPB_RD_L_B1__CMD_COUNT_RFAPB_RD_COUNT___S 0 +#define PHYA_PHYRF_CMD_COUNT_RFAPB_RD_L_B1___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_RFAPB_RD_L_B1___S 0 + +#define PHYA_PHYRF_CMD_COUNT_SWCMD_L_B0 (0x00495158) +#define PHYA_PHYRF_CMD_COUNT_SWCMD_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_CMD_COUNT_SWCMD_L_B0___POR 0x00000000 +#define PHYA_PHYRF_CMD_COUNT_SWCMD_L_B0__CMD_COUNT_SWCMD_COUNT___POR 0x0000 +#define PHYA_PHYRF_CMD_COUNT_SWCMD_L_B0__CMD_COUNT_SWCMD_COUNT___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_SWCMD_L_B0__CMD_COUNT_SWCMD_COUNT___S 0 +#define PHYA_PHYRF_CMD_COUNT_SWCMD_L_B0___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_SWCMD_L_B0___S 0 + +#define PHYA_PHYRF_CMD_COUNT_SWCMD_L_B1 (0x0049D158) +#define PHYA_PHYRF_CMD_COUNT_SWCMD_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_CMD_COUNT_SWCMD_L_B1___POR 0x00000000 +#define PHYA_PHYRF_CMD_COUNT_SWCMD_L_B1__CMD_COUNT_SWCMD_COUNT___POR 0x0000 +#define PHYA_PHYRF_CMD_COUNT_SWCMD_L_B1__CMD_COUNT_SWCMD_COUNT___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_SWCMD_L_B1__CMD_COUNT_SWCMD_COUNT___S 0 +#define PHYA_PHYRF_CMD_COUNT_SWCMD_L_B1___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_SWCMD_L_B1___S 0 + +#define PHYA_PHYRF_CMD_COUNT_RFSAT_RD_L_B0 (0x00495160) +#define PHYA_PHYRF_CMD_COUNT_RFSAT_RD_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_CMD_COUNT_RFSAT_RD_L_B0___POR 0x00000000 +#define PHYA_PHYRF_CMD_COUNT_RFSAT_RD_L_B0__CMD_COUNT_RFSAT_RD_COUNT___POR 0x0000 +#define PHYA_PHYRF_CMD_COUNT_RFSAT_RD_L_B0__CMD_COUNT_RFSAT_RD_COUNT___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_RFSAT_RD_L_B0__CMD_COUNT_RFSAT_RD_COUNT___S 0 +#define PHYA_PHYRF_CMD_COUNT_RFSAT_RD_L_B0___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_RFSAT_RD_L_B0___S 0 + +#define PHYA_PHYRF_CMD_COUNT_RFSAT_RD_L_B1 (0x0049D160) +#define PHYA_PHYRF_CMD_COUNT_RFSAT_RD_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_CMD_COUNT_RFSAT_RD_L_B1___POR 0x00000000 +#define PHYA_PHYRF_CMD_COUNT_RFSAT_RD_L_B1__CMD_COUNT_RFSAT_RD_COUNT___POR 0x0000 +#define PHYA_PHYRF_CMD_COUNT_RFSAT_RD_L_B1__CMD_COUNT_RFSAT_RD_COUNT___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_RFSAT_RD_L_B1__CMD_COUNT_RFSAT_RD_COUNT___S 0 +#define PHYA_PHYRF_CMD_COUNT_RFSAT_RD_L_B1___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_RFSAT_RD_L_B1___S 0 + +#define PHYA_PHYRF_CMD_COUNT_RXGAIN_L_B0 (0x00495168) +#define PHYA_PHYRF_CMD_COUNT_RXGAIN_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_CMD_COUNT_RXGAIN_L_B0___POR 0x00000000 +#define PHYA_PHYRF_CMD_COUNT_RXGAIN_L_B0__CMD_COUNT_RXGAIN_COUNT___POR 0x0000 +#define PHYA_PHYRF_CMD_COUNT_RXGAIN_L_B0__CMD_COUNT_RXGAIN_COUNT___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_RXGAIN_L_B0__CMD_COUNT_RXGAIN_COUNT___S 0 +#define PHYA_PHYRF_CMD_COUNT_RXGAIN_L_B0___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_RXGAIN_L_B0___S 0 + +#define PHYA_PHYRF_CMD_COUNT_RXGAIN_L_B1 (0x0049D168) +#define PHYA_PHYRF_CMD_COUNT_RXGAIN_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_CMD_COUNT_RXGAIN_L_B1___POR 0x00000000 +#define PHYA_PHYRF_CMD_COUNT_RXGAIN_L_B1__CMD_COUNT_RXGAIN_COUNT___POR 0x0000 +#define PHYA_PHYRF_CMD_COUNT_RXGAIN_L_B1__CMD_COUNT_RXGAIN_COUNT___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_RXGAIN_L_B1__CMD_COUNT_RXGAIN_COUNT___S 0 +#define PHYA_PHYRF_CMD_COUNT_RXGAIN_L_B1___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_RXGAIN_L_B1___S 0 + +#define PHYA_PHYRF_CMD_COUNT_TXGAIN_L_B0 (0x00495170) +#define PHYA_PHYRF_CMD_COUNT_TXGAIN_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_CMD_COUNT_TXGAIN_L_B0___POR 0x00000000 +#define PHYA_PHYRF_CMD_COUNT_TXGAIN_L_B0__CMD_COUNT_TXGAIN_COUNT___POR 0x0000 +#define PHYA_PHYRF_CMD_COUNT_TXGAIN_L_B0__CMD_COUNT_TXGAIN_COUNT___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_TXGAIN_L_B0__CMD_COUNT_TXGAIN_COUNT___S 0 +#define PHYA_PHYRF_CMD_COUNT_TXGAIN_L_B0___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_TXGAIN_L_B0___S 0 + +#define PHYA_PHYRF_CMD_COUNT_TXGAIN_L_B1 (0x0049D170) +#define PHYA_PHYRF_CMD_COUNT_TXGAIN_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_CMD_COUNT_TXGAIN_L_B1___POR 0x00000000 +#define PHYA_PHYRF_CMD_COUNT_TXGAIN_L_B1__CMD_COUNT_TXGAIN_COUNT___POR 0x0000 +#define PHYA_PHYRF_CMD_COUNT_TXGAIN_L_B1__CMD_COUNT_TXGAIN_COUNT___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_TXGAIN_L_B1__CMD_COUNT_TXGAIN_COUNT___S 0 +#define PHYA_PHYRF_CMD_COUNT_TXGAIN_L_B1___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_TXGAIN_L_B1___S 0 + +#define PHYA_PHYRF_CMD_COUNT_MODE_L_B0 (0x00495178) +#define PHYA_PHYRF_CMD_COUNT_MODE_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_CMD_COUNT_MODE_L_B0___POR 0x00000000 +#define PHYA_PHYRF_CMD_COUNT_MODE_L_B0__CMD_COUNT_MODE_COUNT___POR 0x0000 +#define PHYA_PHYRF_CMD_COUNT_MODE_L_B0__CMD_COUNT_MODE_COUNT___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_MODE_L_B0__CMD_COUNT_MODE_COUNT___S 0 +#define PHYA_PHYRF_CMD_COUNT_MODE_L_B0___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_MODE_L_B0___S 0 + +#define PHYA_PHYRF_CMD_COUNT_MODE_L_B1 (0x0049D178) +#define PHYA_PHYRF_CMD_COUNT_MODE_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_CMD_COUNT_MODE_L_B1___POR 0x00000000 +#define PHYA_PHYRF_CMD_COUNT_MODE_L_B1__CMD_COUNT_MODE_COUNT___POR 0x0000 +#define PHYA_PHYRF_CMD_COUNT_MODE_L_B1__CMD_COUNT_MODE_COUNT___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_MODE_L_B1__CMD_COUNT_MODE_COUNT___S 0 +#define PHYA_PHYRF_CMD_COUNT_MODE_L_B1___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_MODE_L_B1___S 0 + +#define PHYA_PHYRF_CMD_COUNT_DEBUG_L_B0 (0x00495180) +#define PHYA_PHYRF_CMD_COUNT_DEBUG_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_CMD_COUNT_DEBUG_L_B0___POR 0x00000000 +#define PHYA_PHYRF_CMD_COUNT_DEBUG_L_B0__CMD_COUNT_DEBUG_COUNT___POR 0x0000 +#define PHYA_PHYRF_CMD_COUNT_DEBUG_L_B0__CMD_COUNT_DEBUG_COUNT___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_DEBUG_L_B0__CMD_COUNT_DEBUG_COUNT___S 0 +#define PHYA_PHYRF_CMD_COUNT_DEBUG_L_B0___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_DEBUG_L_B0___S 0 + +#define PHYA_PHYRF_CMD_COUNT_DEBUG_L_B1 (0x0049D180) +#define PHYA_PHYRF_CMD_COUNT_DEBUG_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_CMD_COUNT_DEBUG_L_B1___POR 0x00000000 +#define PHYA_PHYRF_CMD_COUNT_DEBUG_L_B1__CMD_COUNT_DEBUG_COUNT___POR 0x0000 +#define PHYA_PHYRF_CMD_COUNT_DEBUG_L_B1__CMD_COUNT_DEBUG_COUNT___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_DEBUG_L_B1__CMD_COUNT_DEBUG_COUNT___S 0 +#define PHYA_PHYRF_CMD_COUNT_DEBUG_L_B1___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_DEBUG_L_B1___S 0 + +#define PHYA_PHYRF_CMD_COUNT_SYNEN_L_B0 (0x00495188) +#define PHYA_PHYRF_CMD_COUNT_SYNEN_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_CMD_COUNT_SYNEN_L_B0___POR 0x00000000 +#define PHYA_PHYRF_CMD_COUNT_SYNEN_L_B0__CMD_COUNT_SYNEN_COUNT___POR 0x0000 +#define PHYA_PHYRF_CMD_COUNT_SYNEN_L_B0__CMD_COUNT_SYNEN_COUNT___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_SYNEN_L_B0__CMD_COUNT_SYNEN_COUNT___S 0 +#define PHYA_PHYRF_CMD_COUNT_SYNEN_L_B0___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_SYNEN_L_B0___S 0 + +#define PHYA_PHYRF_CMD_COUNT_SYNEN_L_B1 (0x0049D188) +#define PHYA_PHYRF_CMD_COUNT_SYNEN_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_CMD_COUNT_SYNEN_L_B1___POR 0x00000000 +#define PHYA_PHYRF_CMD_COUNT_SYNEN_L_B1__CMD_COUNT_SYNEN_COUNT___POR 0x0000 +#define PHYA_PHYRF_CMD_COUNT_SYNEN_L_B1__CMD_COUNT_SYNEN_COUNT___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_SYNEN_L_B1__CMD_COUNT_SYNEN_COUNT___S 0 +#define PHYA_PHYRF_CMD_COUNT_SYNEN_L_B1___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_SYNEN_L_B1___S 0 + +#define PHYA_PHYRF_CMD_COUNT_RFCAL_L_B0 (0x00495190) +#define PHYA_PHYRF_CMD_COUNT_RFCAL_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_CMD_COUNT_RFCAL_L_B0___POR 0x00000000 +#define PHYA_PHYRF_CMD_COUNT_RFCAL_L_B0__CMD_COUNT_RFCAL_COUNT___POR 0x0000 +#define PHYA_PHYRF_CMD_COUNT_RFCAL_L_B0__CMD_COUNT_RFCAL_COUNT___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_RFCAL_L_B0__CMD_COUNT_RFCAL_COUNT___S 0 +#define PHYA_PHYRF_CMD_COUNT_RFCAL_L_B0___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_RFCAL_L_B0___S 0 + +#define PHYA_PHYRF_CMD_COUNT_RFCAL_L_B1 (0x0049D190) +#define PHYA_PHYRF_CMD_COUNT_RFCAL_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_CMD_COUNT_RFCAL_L_B1___POR 0x00000000 +#define PHYA_PHYRF_CMD_COUNT_RFCAL_L_B1__CMD_COUNT_RFCAL_COUNT___POR 0x0000 +#define PHYA_PHYRF_CMD_COUNT_RFCAL_L_B1__CMD_COUNT_RFCAL_COUNT___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_RFCAL_L_B1__CMD_COUNT_RFCAL_COUNT___S 0 +#define PHYA_PHYRF_CMD_COUNT_RFCAL_L_B1___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_RFCAL_L_B1___S 0 + +#define PHYA_PHYRF_CMD_COUNT_RXDCOC_L_B0 (0x00495198) +#define PHYA_PHYRF_CMD_COUNT_RXDCOC_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_CMD_COUNT_RXDCOC_L_B0___POR 0x00000000 +#define PHYA_PHYRF_CMD_COUNT_RXDCOC_L_B0__CMD_COUNT_RXDCOC_COUNT___POR 0x0000 +#define PHYA_PHYRF_CMD_COUNT_RXDCOC_L_B0__CMD_COUNT_RXDCOC_COUNT___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_RXDCOC_L_B0__CMD_COUNT_RXDCOC_COUNT___S 0 +#define PHYA_PHYRF_CMD_COUNT_RXDCOC_L_B0___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_RXDCOC_L_B0___S 0 + +#define PHYA_PHYRF_CMD_COUNT_RXDCOC_L_B1 (0x0049D198) +#define PHYA_PHYRF_CMD_COUNT_RXDCOC_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_CMD_COUNT_RXDCOC_L_B1___POR 0x00000000 +#define PHYA_PHYRF_CMD_COUNT_RXDCOC_L_B1__CMD_COUNT_RXDCOC_COUNT___POR 0x0000 +#define PHYA_PHYRF_CMD_COUNT_RXDCOC_L_B1__CMD_COUNT_RXDCOC_COUNT___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_RXDCOC_L_B1__CMD_COUNT_RXDCOC_COUNT___S 0 +#define PHYA_PHYRF_CMD_COUNT_RXDCOC_L_B1___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_RXDCOC_L_B1___S 0 + +#define PHYA_PHYRF_CMD_COUNT_TPCRB_L_B0 (0x004951A0) +#define PHYA_PHYRF_CMD_COUNT_TPCRB_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_CMD_COUNT_TPCRB_L_B0___POR 0x00000000 +#define PHYA_PHYRF_CMD_COUNT_TPCRB_L_B0__CMD_COUNT_TPCRB_COUNT___POR 0x0000 +#define PHYA_PHYRF_CMD_COUNT_TPCRB_L_B0__CMD_COUNT_TPCRB_COUNT___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_TPCRB_L_B0__CMD_COUNT_TPCRB_COUNT___S 0 +#define PHYA_PHYRF_CMD_COUNT_TPCRB_L_B0___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_TPCRB_L_B0___S 0 + +#define PHYA_PHYRF_CMD_COUNT_TPCRB_L_B1 (0x0049D1A0) +#define PHYA_PHYRF_CMD_COUNT_TPCRB_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_CMD_COUNT_TPCRB_L_B1___POR 0x00000000 +#define PHYA_PHYRF_CMD_COUNT_TPCRB_L_B1__CMD_COUNT_TPCRB_COUNT___POR 0x0000 +#define PHYA_PHYRF_CMD_COUNT_TPCRB_L_B1__CMD_COUNT_TPCRB_COUNT___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_TPCRB_L_B1__CMD_COUNT_TPCRB_COUNT___S 0 +#define PHYA_PHYRF_CMD_COUNT_TPCRB_L_B1___M 0x0000FFFF +#define PHYA_PHYRF_CMD_COUNT_TPCRB_L_B1___S 0 + +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0 (0x004951A8) +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0___POR 0x000003FF +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_TPCRB___POR 0x1 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_RXDCOC___POR 0x1 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_RFCAL___POR 0x1 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_SYNEN___POR 0x1 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_DEBUG___POR 0x1 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_MODE___POR 0x1 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_TXGAIN___POR 0x1 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_RXGAIN___POR 0x1 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_RFSAT_RD___POR 0x1 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_SWCMD___POR 0x1 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_TPCRB___M 0x00000200 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_TPCRB___S 9 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_RXDCOC___M 0x00000100 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_RXDCOC___S 8 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_RFCAL___M 0x00000080 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_RFCAL___S 7 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_SYNEN___M 0x00000040 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_SYNEN___S 6 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_DEBUG___M 0x00000020 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_DEBUG___S 5 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_MODE___M 0x00000010 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_MODE___S 4 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_TXGAIN___M 0x00000008 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_TXGAIN___S 3 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_RXGAIN___M 0x00000004 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_RXGAIN___S 2 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_RFSAT_RD___M 0x00000002 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_RFSAT_RD___S 1 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_SWCMD___M 0x00000001 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0__OVERLAPPING_CMD_CNT_CTRL_ENBL_SWCMD___S 0 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0___M 0x000003FF +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B0___S 0 + +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1 (0x0049D1A8) +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1___POR 0x000003FF +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_TPCRB___POR 0x1 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_RXDCOC___POR 0x1 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_RFCAL___POR 0x1 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_SYNEN___POR 0x1 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_DEBUG___POR 0x1 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_MODE___POR 0x1 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_TXGAIN___POR 0x1 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_RXGAIN___POR 0x1 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_RFSAT_RD___POR 0x1 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_SWCMD___POR 0x1 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_TPCRB___M 0x00000200 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_TPCRB___S 9 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_RXDCOC___M 0x00000100 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_RXDCOC___S 8 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_RFCAL___M 0x00000080 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_RFCAL___S 7 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_SYNEN___M 0x00000040 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_SYNEN___S 6 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_DEBUG___M 0x00000020 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_DEBUG___S 5 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_MODE___M 0x00000010 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_MODE___S 4 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_TXGAIN___M 0x00000008 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_TXGAIN___S 3 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_RXGAIN___M 0x00000004 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_RXGAIN___S 2 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_RFSAT_RD___M 0x00000002 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_RFSAT_RD___S 1 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_SWCMD___M 0x00000001 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1__OVERLAPPING_CMD_CNT_CTRL_ENBL_SWCMD___S 0 +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1___M 0x000003FF +#define PHYA_PHYRF_OVERLAPPING_CMD_CNT_CTRL_L_B1___S 0 + +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SWCMD_L_B0 (0x004951B0) +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SWCMD_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SWCMD_L_B0___POR 0x00000000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SWCMD_L_B0__OVERLAPPING_CMD_COUNT_SWCMD_VAL___POR 0x0000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SWCMD_L_B0__OVERLAPPING_CMD_COUNT_SWCMD_VAL___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SWCMD_L_B0__OVERLAPPING_CMD_COUNT_SWCMD_VAL___S 0 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SWCMD_L_B0___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SWCMD_L_B0___S 0 + +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SWCMD_L_B1 (0x0049D1B0) +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SWCMD_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SWCMD_L_B1___POR 0x00000000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SWCMD_L_B1__OVERLAPPING_CMD_COUNT_SWCMD_VAL___POR 0x0000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SWCMD_L_B1__OVERLAPPING_CMD_COUNT_SWCMD_VAL___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SWCMD_L_B1__OVERLAPPING_CMD_COUNT_SWCMD_VAL___S 0 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SWCMD_L_B1___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SWCMD_L_B1___S 0 + +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFSAT_RD_L_B0 (0x004951B8) +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFSAT_RD_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFSAT_RD_L_B0___POR 0x00000000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFSAT_RD_L_B0__OVERLAPPING_CMD_COUNT_RFSAT_RD_VAL___POR 0x0000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFSAT_RD_L_B0__OVERLAPPING_CMD_COUNT_RFSAT_RD_VAL___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFSAT_RD_L_B0__OVERLAPPING_CMD_COUNT_RFSAT_RD_VAL___S 0 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFSAT_RD_L_B0___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFSAT_RD_L_B0___S 0 + +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFSAT_RD_L_B1 (0x0049D1B8) +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFSAT_RD_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFSAT_RD_L_B1___POR 0x00000000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFSAT_RD_L_B1__OVERLAPPING_CMD_COUNT_RFSAT_RD_VAL___POR 0x0000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFSAT_RD_L_B1__OVERLAPPING_CMD_COUNT_RFSAT_RD_VAL___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFSAT_RD_L_B1__OVERLAPPING_CMD_COUNT_RFSAT_RD_VAL___S 0 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFSAT_RD_L_B1___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFSAT_RD_L_B1___S 0 + +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXGAIN_L_B0 (0x004951C0) +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXGAIN_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXGAIN_L_B0___POR 0x00000000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXGAIN_L_B0__OVERLAPPING_CMD_COUNT_RXGAIN_VAL___POR 0x0000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXGAIN_L_B0__OVERLAPPING_CMD_COUNT_RXGAIN_VAL___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXGAIN_L_B0__OVERLAPPING_CMD_COUNT_RXGAIN_VAL___S 0 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXGAIN_L_B0___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXGAIN_L_B0___S 0 + +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXGAIN_L_B1 (0x0049D1C0) +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXGAIN_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXGAIN_L_B1___POR 0x00000000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXGAIN_L_B1__OVERLAPPING_CMD_COUNT_RXGAIN_VAL___POR 0x0000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXGAIN_L_B1__OVERLAPPING_CMD_COUNT_RXGAIN_VAL___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXGAIN_L_B1__OVERLAPPING_CMD_COUNT_RXGAIN_VAL___S 0 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXGAIN_L_B1___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXGAIN_L_B1___S 0 + +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TXGAIN_L_B0 (0x004951C8) +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TXGAIN_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TXGAIN_L_B0___POR 0x00000000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TXGAIN_L_B0__OVERLAPPING_CMD_COUNT_TXGAIN_VAL___POR 0x0000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TXGAIN_L_B0__OVERLAPPING_CMD_COUNT_TXGAIN_VAL___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TXGAIN_L_B0__OVERLAPPING_CMD_COUNT_TXGAIN_VAL___S 0 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TXGAIN_L_B0___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TXGAIN_L_B0___S 0 + +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TXGAIN_L_B1 (0x0049D1C8) +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TXGAIN_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TXGAIN_L_B1___POR 0x00000000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TXGAIN_L_B1__OVERLAPPING_CMD_COUNT_TXGAIN_VAL___POR 0x0000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TXGAIN_L_B1__OVERLAPPING_CMD_COUNT_TXGAIN_VAL___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TXGAIN_L_B1__OVERLAPPING_CMD_COUNT_TXGAIN_VAL___S 0 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TXGAIN_L_B1___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TXGAIN_L_B1___S 0 + +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_MODE_L_B0 (0x004951D0) +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_MODE_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_MODE_L_B0___POR 0x00000000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_MODE_L_B0__OVERLAPPING_CMD_COUNT_MODE_VAL___POR 0x0000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_MODE_L_B0__OVERLAPPING_CMD_COUNT_MODE_VAL___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_MODE_L_B0__OVERLAPPING_CMD_COUNT_MODE_VAL___S 0 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_MODE_L_B0___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_MODE_L_B0___S 0 + +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_MODE_L_B1 (0x0049D1D0) +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_MODE_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_MODE_L_B1___POR 0x00000000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_MODE_L_B1__OVERLAPPING_CMD_COUNT_MODE_VAL___POR 0x0000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_MODE_L_B1__OVERLAPPING_CMD_COUNT_MODE_VAL___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_MODE_L_B1__OVERLAPPING_CMD_COUNT_MODE_VAL___S 0 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_MODE_L_B1___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_MODE_L_B1___S 0 + +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_DEBUG_L_B0 (0x004951D8) +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_DEBUG_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_DEBUG_L_B0___POR 0x00000000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_DEBUG_L_B0__OVERLAPPING_CMD_COUNT_DEBUG_VAL___POR 0x0000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_DEBUG_L_B0__OVERLAPPING_CMD_COUNT_DEBUG_VAL___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_DEBUG_L_B0__OVERLAPPING_CMD_COUNT_DEBUG_VAL___S 0 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_DEBUG_L_B0___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_DEBUG_L_B0___S 0 + +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_DEBUG_L_B1 (0x0049D1D8) +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_DEBUG_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_DEBUG_L_B1___POR 0x00000000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_DEBUG_L_B1__OVERLAPPING_CMD_COUNT_DEBUG_VAL___POR 0x0000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_DEBUG_L_B1__OVERLAPPING_CMD_COUNT_DEBUG_VAL___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_DEBUG_L_B1__OVERLAPPING_CMD_COUNT_DEBUG_VAL___S 0 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_DEBUG_L_B1___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_DEBUG_L_B1___S 0 + +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SYNEN_L_B0 (0x004951E0) +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SYNEN_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SYNEN_L_B0___POR 0x00000000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SYNEN_L_B0__OVERLAPPING_CMD_COUNT_SYNEN_VAL___POR 0x0000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SYNEN_L_B0__OVERLAPPING_CMD_COUNT_SYNEN_VAL___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SYNEN_L_B0__OVERLAPPING_CMD_COUNT_SYNEN_VAL___S 0 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SYNEN_L_B0___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SYNEN_L_B0___S 0 + +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SYNEN_L_B1 (0x0049D1E0) +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SYNEN_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SYNEN_L_B1___POR 0x00000000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SYNEN_L_B1__OVERLAPPING_CMD_COUNT_SYNEN_VAL___POR 0x0000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SYNEN_L_B1__OVERLAPPING_CMD_COUNT_SYNEN_VAL___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SYNEN_L_B1__OVERLAPPING_CMD_COUNT_SYNEN_VAL___S 0 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SYNEN_L_B1___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_SYNEN_L_B1___S 0 + +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFCAL_L_B0 (0x004951E8) +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFCAL_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFCAL_L_B0___POR 0x00000000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFCAL_L_B0__OVERLAPPING_CMD_COUNT_RFCAL_VAL___POR 0x0000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFCAL_L_B0__OVERLAPPING_CMD_COUNT_RFCAL_VAL___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFCAL_L_B0__OVERLAPPING_CMD_COUNT_RFCAL_VAL___S 0 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFCAL_L_B0___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFCAL_L_B0___S 0 + +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFCAL_L_B1 (0x0049D1E8) +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFCAL_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFCAL_L_B1___POR 0x00000000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFCAL_L_B1__OVERLAPPING_CMD_COUNT_RFCAL_VAL___POR 0x0000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFCAL_L_B1__OVERLAPPING_CMD_COUNT_RFCAL_VAL___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFCAL_L_B1__OVERLAPPING_CMD_COUNT_RFCAL_VAL___S 0 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFCAL_L_B1___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RFCAL_L_B1___S 0 + +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXDCOC_L_B0 (0x004951F0) +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXDCOC_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXDCOC_L_B0___POR 0x00000000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXDCOC_L_B0__OVERLAPPING_CMD_COUNT_RXDCOC_VAL___POR 0x0000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXDCOC_L_B0__OVERLAPPING_CMD_COUNT_RXDCOC_VAL___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXDCOC_L_B0__OVERLAPPING_CMD_COUNT_RXDCOC_VAL___S 0 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXDCOC_L_B0___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXDCOC_L_B0___S 0 + +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXDCOC_L_B1 (0x0049D1F0) +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXDCOC_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXDCOC_L_B1___POR 0x00000000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXDCOC_L_B1__OVERLAPPING_CMD_COUNT_RXDCOC_VAL___POR 0x0000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXDCOC_L_B1__OVERLAPPING_CMD_COUNT_RXDCOC_VAL___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXDCOC_L_B1__OVERLAPPING_CMD_COUNT_RXDCOC_VAL___S 0 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXDCOC_L_B1___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_RXDCOC_L_B1___S 0 + +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TPCRB_L_B0 (0x004951F8) +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TPCRB_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TPCRB_L_B0___POR 0x00000000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TPCRB_L_B0__OVERLAPPING_CMD_COUNT_TPCRB_VAL___POR 0x0000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TPCRB_L_B0__OVERLAPPING_CMD_COUNT_TPCRB_VAL___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TPCRB_L_B0__OVERLAPPING_CMD_COUNT_TPCRB_VAL___S 0 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TPCRB_L_B0___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TPCRB_L_B0___S 0 + +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TPCRB_L_B1 (0x0049D1F8) +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TPCRB_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TPCRB_L_B1___POR 0x00000000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TPCRB_L_B1__OVERLAPPING_CMD_COUNT_TPCRB_VAL___POR 0x0000 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TPCRB_L_B1__OVERLAPPING_CMD_COUNT_TPCRB_VAL___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TPCRB_L_B1__OVERLAPPING_CMD_COUNT_TPCRB_VAL___S 0 +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TPCRB_L_B1___M 0x0000FFFF +#define PHYA_PHYRF_OVERLAPPING_CMD_COUNT_TPCRB_L_B1___S 0 + +#define PHYA_PHYRF_CMD_CAPTURE_L_B0 (0x00495200) +#define PHYA_PHYRF_CMD_CAPTURE_L_B0___RWC QCSR_REG_RO +#define PHYA_PHYRF_CMD_CAPTURE_L_B0___POR 0x00000F0F +#define PHYA_PHYRF_CMD_CAPTURE_L_B0__CMD_CAPTURE_PREV___POR 0x0F +#define PHYA_PHYRF_CMD_CAPTURE_L_B0__CMD_CAPTURE_CURR___POR 0x0F +#define PHYA_PHYRF_CMD_CAPTURE_L_B0__CMD_CAPTURE_PREV___M 0x00001F00 +#define PHYA_PHYRF_CMD_CAPTURE_L_B0__CMD_CAPTURE_PREV___S 8 +#define PHYA_PHYRF_CMD_CAPTURE_L_B0__CMD_CAPTURE_CURR___M 0x0000001F +#define PHYA_PHYRF_CMD_CAPTURE_L_B0__CMD_CAPTURE_CURR___S 0 +#define PHYA_PHYRF_CMD_CAPTURE_L_B0___M 0x00001F1F +#define PHYA_PHYRF_CMD_CAPTURE_L_B0___S 0 + +#define PHYA_PHYRF_CMD_CAPTURE_L_B1 (0x0049D200) +#define PHYA_PHYRF_CMD_CAPTURE_L_B1___RWC QCSR_REG_RO +#define PHYA_PHYRF_CMD_CAPTURE_L_B1___POR 0x00000F0F +#define PHYA_PHYRF_CMD_CAPTURE_L_B1__CMD_CAPTURE_PREV___POR 0x0F +#define PHYA_PHYRF_CMD_CAPTURE_L_B1__CMD_CAPTURE_CURR___POR 0x0F +#define PHYA_PHYRF_CMD_CAPTURE_L_B1__CMD_CAPTURE_PREV___M 0x00001F00 +#define PHYA_PHYRF_CMD_CAPTURE_L_B1__CMD_CAPTURE_PREV___S 8 +#define PHYA_PHYRF_CMD_CAPTURE_L_B1__CMD_CAPTURE_CURR___M 0x0000001F +#define PHYA_PHYRF_CMD_CAPTURE_L_B1__CMD_CAPTURE_CURR___S 0 +#define PHYA_PHYRF_CMD_CAPTURE_L_B1___M 0x00001F1F +#define PHYA_PHYRF_CMD_CAPTURE_L_B1___S 0 + +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B0 (0x00495208) +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B0___POR 0x00000001 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B0__RFACTRL_TRACE_BUF_CONFIG_CAPTURE_ALL___POR 0x0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B0__RFACTRL_TRACE_BUF_CONFIG_KEEP_FIRST___POR 0x0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B0__RFACTRL_TRACE_BUF_CONFIG_TRACE_ON___POR 0x0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B0__RFACTRL_TRACE_BUF_CONFIG_TRACE_RST___POR 0x1 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B0__RFACTRL_TRACE_BUF_CONFIG_CAPTURE_ALL___M 0x01000000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B0__RFACTRL_TRACE_BUF_CONFIG_CAPTURE_ALL___S 24 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B0__RFACTRL_TRACE_BUF_CONFIG_KEEP_FIRST___M 0x00010000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B0__RFACTRL_TRACE_BUF_CONFIG_KEEP_FIRST___S 16 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B0__RFACTRL_TRACE_BUF_CONFIG_TRACE_ON___M 0x00000100 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B0__RFACTRL_TRACE_BUF_CONFIG_TRACE_ON___S 8 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B0__RFACTRL_TRACE_BUF_CONFIG_TRACE_RST___M 0x00000001 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B0__RFACTRL_TRACE_BUF_CONFIG_TRACE_RST___S 0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B0___M 0x01010101 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B0___S 0 + +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B1 (0x0049D208) +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B1___POR 0x00000001 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B1__RFACTRL_TRACE_BUF_CONFIG_CAPTURE_ALL___POR 0x0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B1__RFACTRL_TRACE_BUF_CONFIG_KEEP_FIRST___POR 0x0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B1__RFACTRL_TRACE_BUF_CONFIG_TRACE_ON___POR 0x0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B1__RFACTRL_TRACE_BUF_CONFIG_TRACE_RST___POR 0x1 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B1__RFACTRL_TRACE_BUF_CONFIG_CAPTURE_ALL___M 0x01000000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B1__RFACTRL_TRACE_BUF_CONFIG_CAPTURE_ALL___S 24 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B1__RFACTRL_TRACE_BUF_CONFIG_KEEP_FIRST___M 0x00010000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B1__RFACTRL_TRACE_BUF_CONFIG_KEEP_FIRST___S 16 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B1__RFACTRL_TRACE_BUF_CONFIG_TRACE_ON___M 0x00000100 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B1__RFACTRL_TRACE_BUF_CONFIG_TRACE_ON___S 8 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B1__RFACTRL_TRACE_BUF_CONFIG_TRACE_RST___M 0x00000001 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B1__RFACTRL_TRACE_BUF_CONFIG_TRACE_RST___S 0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B1___M 0x01010101 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_CONFIG_L_B1___S 0 + +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0 (0x00495210) +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0___RWC QCSR_REG_RO +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0___POR 0x00000000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_LGWR_REQ_TRACE_OV___POR 0x0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_SHWR_REQ_TRACE_OV___POR 0x0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_ARB_TRACE_OV___POR 0x0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_LGWR_REQ_TRACE_COUNT___POR 0x00 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_SHWR_REQ_TRACE_COUNT___POR 0x00 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_ARB_TRACE_COUNT___POR 0x00 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_LGWR_REQ_TRACE_OV___M 0x00100000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_LGWR_REQ_TRACE_OV___S 20 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_SHWR_REQ_TRACE_OV___M 0x00080000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_SHWR_REQ_TRACE_OV___S 19 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_ARB_TRACE_OV___M 0x00040000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_ARB_TRACE_OV___S 18 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_LGWR_REQ_TRACE_COUNT___M 0x0003F000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_LGWR_REQ_TRACE_COUNT___S 12 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_SHWR_REQ_TRACE_COUNT___M 0x00000FC0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_SHWR_REQ_TRACE_COUNT___S 6 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_ARB_TRACE_COUNT___M 0x0000003F +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0__RFACTRL_TRACE_BUF_STATUS_ARB_TRACE_COUNT___S 0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0___M 0x001FFFFF +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B0___S 0 + +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1 (0x0049D210) +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1___RWC QCSR_REG_RO +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1___POR 0x00000000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_LGWR_REQ_TRACE_OV___POR 0x0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_SHWR_REQ_TRACE_OV___POR 0x0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_ARB_TRACE_OV___POR 0x0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_LGWR_REQ_TRACE_COUNT___POR 0x00 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_SHWR_REQ_TRACE_COUNT___POR 0x00 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_ARB_TRACE_COUNT___POR 0x00 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_LGWR_REQ_TRACE_OV___M 0x00100000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_LGWR_REQ_TRACE_OV___S 20 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_SHWR_REQ_TRACE_OV___M 0x00080000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_SHWR_REQ_TRACE_OV___S 19 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_ARB_TRACE_OV___M 0x00040000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_ARB_TRACE_OV___S 18 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_LGWR_REQ_TRACE_COUNT___M 0x0003F000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_LGWR_REQ_TRACE_COUNT___S 12 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_SHWR_REQ_TRACE_COUNT___M 0x00000FC0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_SHWR_REQ_TRACE_COUNT___S 6 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_ARB_TRACE_COUNT___M 0x0000003F +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1__RFACTRL_TRACE_BUF_STATUS_ARB_TRACE_COUNT___S 0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1___M 0x001FFFFF +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_STATUS_L_B1___S 0 + +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_n(n) (0x00495218+0x8*(n)) +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_n_nMIN 0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_n_nMAX 0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_n_ELEM 1 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_n___RWC QCSR_REG_RO +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_n___POR 0x00000000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_n__RFACTRL_TRACE_BUF_ARB_SM_RESERVED_ARB___POR 0x0000000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_n__RFACTRL_TRACE_BUF_ARB_SM_ARB_STATE_TRACE___POR 0x0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_n__RFACTRL_TRACE_BUF_ARB_SM_RESERVED_ARB___M 0xFFFFFFF0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_n__RFACTRL_TRACE_BUF_ARB_SM_RESERVED_ARB___S 4 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_n__RFACTRL_TRACE_BUF_ARB_SM_ARB_STATE_TRACE___M 0x0000000F +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_n__RFACTRL_TRACE_BUF_ARB_SM_ARB_STATE_TRACE___S 0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_n___M 0xFFFFFFFF +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_n___S 0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_0 (0x00495218) +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_0___RWC QCSR_REG_RO +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_0__RFACTRL_TRACE_BUF_ARB_SM_RESERVED_ARB___M 0xFFFFFFF0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_0__RFACTRL_TRACE_BUF_ARB_SM_RESERVED_ARB___S 4 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_0__RFACTRL_TRACE_BUF_ARB_SM_ARB_STATE_TRACE___M 0x0000000F +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B0_0__RFACTRL_TRACE_BUF_ARB_SM_ARB_STATE_TRACE___S 0 + +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_n(n) (0x0049D218+0x8*(n)) +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_n_nMIN 0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_n_nMAX 0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_n_ELEM 1 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_n___RWC QCSR_REG_RO +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_n___POR 0x00000000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_n__RFACTRL_TRACE_BUF_ARB_SM_RESERVED_ARB___POR 0x0000000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_n__RFACTRL_TRACE_BUF_ARB_SM_ARB_STATE_TRACE___POR 0x0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_n__RFACTRL_TRACE_BUF_ARB_SM_RESERVED_ARB___M 0xFFFFFFF0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_n__RFACTRL_TRACE_BUF_ARB_SM_RESERVED_ARB___S 4 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_n__RFACTRL_TRACE_BUF_ARB_SM_ARB_STATE_TRACE___M 0x0000000F +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_n__RFACTRL_TRACE_BUF_ARB_SM_ARB_STATE_TRACE___S 0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_n___M 0xFFFFFFFF +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_n___S 0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_0 (0x0049D218) +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_0___RWC QCSR_REG_RO +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_0__RFACTRL_TRACE_BUF_ARB_SM_RESERVED_ARB___M 0xFFFFFFF0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_0__RFACTRL_TRACE_BUF_ARB_SM_RESERVED_ARB___S 4 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_0__RFACTRL_TRACE_BUF_ARB_SM_ARB_STATE_TRACE___M 0x0000000F +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_ARB_SM_L_B1_0__RFACTRL_TRACE_BUF_ARB_SM_ARB_STATE_TRACE___S 0 + +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n(n) (0x00495220+0x8*(n)) +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n_nMIN 0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n_nMAX 0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n_ELEM 1 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n___RWC QCSR_REG_RO +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n___POR 0x00000000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RESERVED_SHWR___POR 0x00000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RXGAIN_STATE_TRACE___POR 0x0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_TXGAIN_STATE_TRACE___POR 0x0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_MODE_STATE_TRACE___POR 0x0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_DEBUG_STATE_TRACE___POR 0x0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RESERVED_SHWR___M 0xFFFFF000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RESERVED_SHWR___S 12 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RXGAIN_STATE_TRACE___M 0x00000E00 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RXGAIN_STATE_TRACE___S 9 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_TXGAIN_STATE_TRACE___M 0x000001C0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_TXGAIN_STATE_TRACE___S 6 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_MODE_STATE_TRACE___M 0x00000038 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_MODE_STATE_TRACE___S 3 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_DEBUG_STATE_TRACE___M 0x00000007 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_DEBUG_STATE_TRACE___S 0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n___M 0xFFFFFFFF +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_n___S 0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_0 (0x00495220) +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_0___RWC QCSR_REG_RO +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RESERVED_SHWR___M 0xFFFFF000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RESERVED_SHWR___S 12 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RXGAIN_STATE_TRACE___M 0x00000E00 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RXGAIN_STATE_TRACE___S 9 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_TXGAIN_STATE_TRACE___M 0x000001C0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_TXGAIN_STATE_TRACE___S 6 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_MODE_STATE_TRACE___M 0x00000038 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_MODE_STATE_TRACE___S 3 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_DEBUG_STATE_TRACE___M 0x00000007 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_DEBUG_STATE_TRACE___S 0 + +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n(n) (0x0049D220+0x8*(n)) +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n_nMIN 0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n_nMAX 0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n_ELEM 1 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n___RWC QCSR_REG_RO +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n___POR 0x00000000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RESERVED_SHWR___POR 0x00000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RXGAIN_STATE_TRACE___POR 0x0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_TXGAIN_STATE_TRACE___POR 0x0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_MODE_STATE_TRACE___POR 0x0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_DEBUG_STATE_TRACE___POR 0x0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RESERVED_SHWR___M 0xFFFFF000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RESERVED_SHWR___S 12 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RXGAIN_STATE_TRACE___M 0x00000E00 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RXGAIN_STATE_TRACE___S 9 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_TXGAIN_STATE_TRACE___M 0x000001C0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_TXGAIN_STATE_TRACE___S 6 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_MODE_STATE_TRACE___M 0x00000038 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_MODE_STATE_TRACE___S 3 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_DEBUG_STATE_TRACE___M 0x00000007 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_SHWR_REQ_SM_DEBUG_STATE_TRACE___S 0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n___M 0xFFFFFFFF +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_n___S 0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_0 (0x0049D220) +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_0___RWC QCSR_REG_RO +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RESERVED_SHWR___M 0xFFFFF000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RESERVED_SHWR___S 12 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RXGAIN_STATE_TRACE___M 0x00000E00 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_RXGAIN_STATE_TRACE___S 9 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_TXGAIN_STATE_TRACE___M 0x000001C0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_TXGAIN_STATE_TRACE___S 6 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_MODE_STATE_TRACE___M 0x00000038 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_MODE_STATE_TRACE___S 3 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_DEBUG_STATE_TRACE___M 0x00000007 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_SHWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_SHWR_REQ_SM_DEBUG_STATE_TRACE___S 0 + +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n(n) (0x00495228+0x8*(n)) +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n_nMIN 0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n_nMAX 0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n_ELEM 1 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n___RWC QCSR_REG_RO +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n___POR 0x00000000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RESERVED_LGWR___POR 0x00000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_SYNEN_STATE_TRACE___POR 0x0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFCAL_STATE_TRACE___POR 0x0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RXDCOC_STATE_TRACE___POR 0x0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_TPCRB_STATE_TRACE___POR 0x0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFAPB_STATE_TRACE___POR 0x0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RESERVED_LGWR___M 0xFFFF8000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RESERVED_LGWR___S 15 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_SYNEN_STATE_TRACE___M 0x00007000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_SYNEN_STATE_TRACE___S 12 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFCAL_STATE_TRACE___M 0x00000E00 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFCAL_STATE_TRACE___S 9 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RXDCOC_STATE_TRACE___M 0x000001C0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RXDCOC_STATE_TRACE___S 6 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_TPCRB_STATE_TRACE___M 0x00000038 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_TPCRB_STATE_TRACE___S 3 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFAPB_STATE_TRACE___M 0x00000007 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFAPB_STATE_TRACE___S 0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n___M 0xFFFFFFFF +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_n___S 0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_0 (0x00495228) +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_0___RWC QCSR_REG_RO +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RESERVED_LGWR___M 0xFFFF8000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RESERVED_LGWR___S 15 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_SYNEN_STATE_TRACE___M 0x00007000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_SYNEN_STATE_TRACE___S 12 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFCAL_STATE_TRACE___M 0x00000E00 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFCAL_STATE_TRACE___S 9 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RXDCOC_STATE_TRACE___M 0x000001C0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RXDCOC_STATE_TRACE___S 6 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_TPCRB_STATE_TRACE___M 0x00000038 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_TPCRB_STATE_TRACE___S 3 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFAPB_STATE_TRACE___M 0x00000007 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B0_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFAPB_STATE_TRACE___S 0 + +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n(n) (0x0049D228+0x8*(n)) +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n_nMIN 0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n_nMAX 0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n_ELEM 1 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n___RWC QCSR_REG_RO +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n___POR 0x00000000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RESERVED_LGWR___POR 0x00000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_SYNEN_STATE_TRACE___POR 0x0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFCAL_STATE_TRACE___POR 0x0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RXDCOC_STATE_TRACE___POR 0x0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_TPCRB_STATE_TRACE___POR 0x0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFAPB_STATE_TRACE___POR 0x0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RESERVED_LGWR___M 0xFFFF8000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RESERVED_LGWR___S 15 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_SYNEN_STATE_TRACE___M 0x00007000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_SYNEN_STATE_TRACE___S 12 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFCAL_STATE_TRACE___M 0x00000E00 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFCAL_STATE_TRACE___S 9 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RXDCOC_STATE_TRACE___M 0x000001C0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RXDCOC_STATE_TRACE___S 6 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_TPCRB_STATE_TRACE___M 0x00000038 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_TPCRB_STATE_TRACE___S 3 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFAPB_STATE_TRACE___M 0x00000007 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFAPB_STATE_TRACE___S 0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n___M 0xFFFFFFFF +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_n___S 0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_0 (0x0049D228) +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_0___RWC QCSR_REG_RO +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RESERVED_LGWR___M 0xFFFF8000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RESERVED_LGWR___S 15 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_SYNEN_STATE_TRACE___M 0x00007000 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_SYNEN_STATE_TRACE___S 12 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFCAL_STATE_TRACE___M 0x00000E00 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFCAL_STATE_TRACE___S 9 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RXDCOC_STATE_TRACE___M 0x000001C0 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RXDCOC_STATE_TRACE___S 6 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_TPCRB_STATE_TRACE___M 0x00000038 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_TPCRB_STATE_TRACE___S 3 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFAPB_STATE_TRACE___M 0x00000007 +#define PHYA_PHYRF_RFACTRL_TRACE_BUF_LGWR_REQ_SM_L_B1_0__RFACTRL_TRACE_BUF_LGWR_REQ_SM_RFAPB_STATE_TRACE___S 0 + +#define PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B0_n(n) (0x00495230+0x8*(n)) +#define PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B0_n_nMIN 0 +#define PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B0_n_nMAX 0 +#define PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B0_n_ELEM 1 +#define PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B0_n___RWC QCSR_REG_RO +#define PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B0_n___POR 0x00000000 +#define PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B0_n__POST_WSI_WRITE_DEBUG_BUS___POR 0x00000000 +#define PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B0_n__POST_WSI_WRITE_DEBUG_BUS___M 0xFFFFFFFF +#define PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B0_n__POST_WSI_WRITE_DEBUG_BUS___S 0 +#define PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B0_n___M 0xFFFFFFFF +#define PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B0_n___S 0 +#define PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B0_0 (0x00495230) +#define PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B0_0___RWC QCSR_REG_RO +#define PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B0_0__POST_WSI_WRITE_DEBUG_BUS___M 0xFFFFFFFF +#define PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B0_0__POST_WSI_WRITE_DEBUG_BUS___S 0 + +#define PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B1_n(n) (0x0049D230+0x8*(n)) +#define PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B1_n_nMIN 0 +#define PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B1_n_nMAX 0 +#define PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B1_n_ELEM 1 +#define PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B1_n___RWC QCSR_REG_RO +#define PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B1_n___POR 0x00000000 +#define PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B1_n__POST_WSI_WRITE_DEBUG_BUS___POR 0x00000000 +#define PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B1_n__POST_WSI_WRITE_DEBUG_BUS___M 0xFFFFFFFF +#define PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B1_n__POST_WSI_WRITE_DEBUG_BUS___S 0 +#define PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B1_n___M 0xFFFFFFFF +#define PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B1_n___S 0 +#define PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B1_0 (0x0049D230) +#define PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B1_0___RWC QCSR_REG_RO +#define PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B1_0__POST_WSI_WRITE_DEBUG_BUS___M 0xFFFFFFFF +#define PHYA_PHYRF_POST_WSI_WRITE_DEBUG_BUS_L_B1_0__POST_WSI_WRITE_DEBUG_BUS___S 0 + +#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_L_B0 (0x00495238) +#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_L_B0___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_L_B0__PHYRF_N_PUBLIC_SPARE_0___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_L_B0__PHYRF_N_PUBLIC_SPARE_0___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_L_B0__PHYRF_N_PUBLIC_SPARE_0___S 0 +#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_L_B0___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_L_B0___S 0 + +#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_L_B1 (0x0049D238) +#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_L_B1___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_L_B1__PHYRF_N_PUBLIC_SPARE_0___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_L_B1__PHYRF_N_PUBLIC_SPARE_0___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_L_B1__PHYRF_N_PUBLIC_SPARE_0___S 0 +#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_L_B1___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_L_B1___S 0 + +#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_U_B0 (0x0049523C) +#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_U_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_U_B0___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_U_B0__PHYRF_N_PUBLIC_SPARE_1___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_U_B0__PHYRF_N_PUBLIC_SPARE_1___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_U_B0__PHYRF_N_PUBLIC_SPARE_1___S 0 +#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_U_B0___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_U_B0___S 0 + +#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_U_B1 (0x0049D23C) +#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_U_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_U_B1___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_U_B1__PHYRF_N_PUBLIC_SPARE_1___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_U_B1__PHYRF_N_PUBLIC_SPARE_1___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_U_B1__PHYRF_N_PUBLIC_SPARE_1___S 0 +#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_U_B1___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_N_PUBLIC_SPARE_U_B1___S 0 + +#define PHYA_PHYRF_PHYRF_N_DUMMY_STATIC_PRIVATE_CSR_L_B0 (0x00495240) +#define PHYA_PHYRF_PHYRF_N_DUMMY_STATIC_PRIVATE_CSR_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_N_DUMMY_STATIC_PRIVATE_CSR_L_B0___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_N_DUMMY_STATIC_PRIVATE_CSR_L_B0__PHYRF_N_DUMMY_STATIC_PRIVATE_CSR___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_N_DUMMY_STATIC_PRIVATE_CSR_L_B0__PHYRF_N_DUMMY_STATIC_PRIVATE_CSR___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_N_DUMMY_STATIC_PRIVATE_CSR_L_B0__PHYRF_N_DUMMY_STATIC_PRIVATE_CSR___S 0 +#define PHYA_PHYRF_PHYRF_N_DUMMY_STATIC_PRIVATE_CSR_L_B0___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_N_DUMMY_STATIC_PRIVATE_CSR_L_B0___S 0 + +#define PHYA_PHYRF_PHYRF_N_DUMMY_STATIC_PRIVATE_CSR_L_B1 (0x0049D240) +#define PHYA_PHYRF_PHYRF_N_DUMMY_STATIC_PRIVATE_CSR_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_N_DUMMY_STATIC_PRIVATE_CSR_L_B1___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_N_DUMMY_STATIC_PRIVATE_CSR_L_B1__PHYRF_N_DUMMY_STATIC_PRIVATE_CSR___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_N_DUMMY_STATIC_PRIVATE_CSR_L_B1__PHYRF_N_DUMMY_STATIC_PRIVATE_CSR___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_N_DUMMY_STATIC_PRIVATE_CSR_L_B1__PHYRF_N_DUMMY_STATIC_PRIVATE_CSR___S 0 +#define PHYA_PHYRF_PHYRF_N_DUMMY_STATIC_PRIVATE_CSR_L_B1___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_N_DUMMY_STATIC_PRIVATE_CSR_L_B1___S 0 + +#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_L_B0 (0x00495248) +#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_L_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_L_B0___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_L_B0__PHYRF_N_PRIVATE_SPARE_0___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_L_B0__PHYRF_N_PRIVATE_SPARE_0___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_L_B0__PHYRF_N_PRIVATE_SPARE_0___S 0 +#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_L_B0___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_L_B0___S 0 + +#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_L_B1 (0x0049D248) +#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_L_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_L_B1___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_L_B1__PHYRF_N_PRIVATE_SPARE_0___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_L_B1__PHYRF_N_PRIVATE_SPARE_0___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_L_B1__PHYRF_N_PRIVATE_SPARE_0___S 0 +#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_L_B1___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_L_B1___S 0 + +#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_U_B0 (0x0049524C) +#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_U_B0___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_U_B0___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_U_B0__PHYRF_N_PRIVATE_SPARE_1___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_U_B0__PHYRF_N_PRIVATE_SPARE_1___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_U_B0__PHYRF_N_PRIVATE_SPARE_1___S 0 +#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_U_B0___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_U_B0___S 0 + +#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_U_B1 (0x0049D24C) +#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_U_B1___RWC QCSR_REG_RW +#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_U_B1___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_U_B1__PHYRF_N_PRIVATE_SPARE_1___POR 0x00000000 +#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_U_B1__PHYRF_N_PRIVATE_SPARE_1___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_U_B1__PHYRF_N_PRIVATE_SPARE_1___S 0 +#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_U_B1___M 0xFFFFFFFF +#define PHYA_PHYRF_PHYRF_N_PRIVATE_SPARE_U_B1___S 0 + +#define PHYA_ROBE_PMI_RESET_CTRL_L (0x004B0000) +#define PHYA_ROBE_PMI_RESET_CTRL_L___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_RESET_CTRL_L___POR 0x00000000 +#define PHYA_ROBE_PMI_RESET_CTRL_L__CBF_DMA_FIFO_RESET___POR 0x0 +#define PHYA_ROBE_PMI_RESET_CTRL_L__OP_TLV_FIFO_RESET___POR 0x0 +#define PHYA_ROBE_PMI_RESET_CTRL_L__IP_TLV_FIFO_RESET___POR 0x0 +#define PHYA_ROBE_PMI_RESET_CTRL_L__CBF_DMA_FIFO_RESET___M 0x00000004 +#define PHYA_ROBE_PMI_RESET_CTRL_L__CBF_DMA_FIFO_RESET___S 2 +#define PHYA_ROBE_PMI_RESET_CTRL_L__OP_TLV_FIFO_RESET___M 0x00000002 +#define PHYA_ROBE_PMI_RESET_CTRL_L__OP_TLV_FIFO_RESET___S 1 +#define PHYA_ROBE_PMI_RESET_CTRL_L__IP_TLV_FIFO_RESET___M 0x00000001 +#define PHYA_ROBE_PMI_RESET_CTRL_L__IP_TLV_FIFO_RESET___S 0 +#define PHYA_ROBE_PMI_RESET_CTRL_L___M 0x00000007 +#define PHYA_ROBE_PMI_RESET_CTRL_L___S 0 + +#define PHYA_ROBE_PMI_CTRL_L (0x004B0008) +#define PHYA_ROBE_PMI_CTRL_L___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_CTRL_L___POR 0x00000000 +#define PHYA_ROBE_PMI_CTRL_L__PMI_ECO_CTRL___POR 0x00000000 +#define PHYA_ROBE_PMI_CTRL_L__PMI_ECO_CTRL___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_CTRL_L__PMI_ECO_CTRL___S 0 +#define PHYA_ROBE_PMI_CTRL_L___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_CTRL_L___S 0 + +#define PHYA_ROBE_PMI_CFG_L (0x004B0010) +#define PHYA_ROBE_PMI_CFG_L___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_CFG_L___POR 0x00000000 +#define PHYA_ROBE_PMI_CFG_L__PMI_ECO_CFG___POR 0x00000000 +#define PHYA_ROBE_PMI_CFG_L__PMI_ECO_CFG___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_CFG_L__PMI_ECO_CFG___S 0 +#define PHYA_ROBE_PMI_CFG_L___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_CFG_L___S 0 + +#define PHYA_ROBE_PMI_STAT_L (0x004B0018) +#define PHYA_ROBE_PMI_STAT_L___RWC QCSR_REG_RO +#define PHYA_ROBE_PMI_STAT_L___POR 0x00000000 +#define PHYA_ROBE_PMI_STAT_L__PMI_ECO_STAT___POR 0x00000000 +#define PHYA_ROBE_PMI_STAT_L__PMI_ECO_STAT___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_STAT_L__PMI_ECO_STAT___S 0 +#define PHYA_ROBE_PMI_STAT_L___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_STAT_L___S 0 + +#define PHYA_ROBE_PMI_EVENT_STATUS_L (0x004B0020) +#define PHYA_ROBE_PMI_EVENT_STATUS_L___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_EVENT_STATUS_L___POR 0x00000000 +#define PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_IP_TLV_ABORT_EVENT___POR 0x0 +#define PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_IP_TLV_EVENT___POR 0x0 +#define PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_CBF_DMA_LAST_REQ_EVENT___POR 0x0 +#define PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_CBF_DMA_REQ_EVENT___POR 0x0 +#define PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_ECO_EVENT___POR 0x0 +#define PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_ERROR_EVENT___POR 0x0 +#define PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_IP_TLV_ABORT_EVENT___M 0x00000020 +#define PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_IP_TLV_ABORT_EVENT___S 5 +#define PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_IP_TLV_EVENT___M 0x00000010 +#define PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_IP_TLV_EVENT___S 4 +#define PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_CBF_DMA_LAST_REQ_EVENT___M 0x00000008 +#define PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_CBF_DMA_LAST_REQ_EVENT___S 3 +#define PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_CBF_DMA_REQ_EVENT___M 0x00000004 +#define PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_CBF_DMA_REQ_EVENT___S 2 +#define PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_ECO_EVENT___M 0x00000002 +#define PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_ECO_EVENT___S 1 +#define PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_ERROR_EVENT___M 0x00000001 +#define PHYA_ROBE_PMI_EVENT_STATUS_L__PMI_ERROR_EVENT___S 0 +#define PHYA_ROBE_PMI_EVENT_STATUS_L___M 0x0000003F +#define PHYA_ROBE_PMI_EVENT_STATUS_L___S 0 + +#define PHYA_ROBE_PMI_EVENT_MASK_L (0x004B0028) +#define PHYA_ROBE_PMI_EVENT_MASK_L___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_EVENT_MASK_L___POR 0x0000003F +#define PHYA_ROBE_PMI_EVENT_MASK_L__PMI_IP_TLV_ABORT_EVENT_MASK___POR 0x1 +#define PHYA_ROBE_PMI_EVENT_MASK_L__PMI_IP_TLV_EVENT_MASK___POR 0x1 +#define PHYA_ROBE_PMI_EVENT_MASK_L__PMI_CBF_DMA_LAST_REQ_MASK___POR 0x1 +#define PHYA_ROBE_PMI_EVENT_MASK_L__PMI_CBF_DMA_REQ_MASK___POR 0x1 +#define PHYA_ROBE_PMI_EVENT_MASK_L__PMI_ECO_EVENT_MASK___POR 0x1 +#define PHYA_ROBE_PMI_EVENT_MASK_L__PMI_ERROR_EVENT_MASK___POR 0x1 +#define PHYA_ROBE_PMI_EVENT_MASK_L__PMI_IP_TLV_ABORT_EVENT_MASK___M 0x00000020 +#define PHYA_ROBE_PMI_EVENT_MASK_L__PMI_IP_TLV_ABORT_EVENT_MASK___S 5 +#define PHYA_ROBE_PMI_EVENT_MASK_L__PMI_IP_TLV_EVENT_MASK___M 0x00000010 +#define PHYA_ROBE_PMI_EVENT_MASK_L__PMI_IP_TLV_EVENT_MASK___S 4 +#define PHYA_ROBE_PMI_EVENT_MASK_L__PMI_CBF_DMA_LAST_REQ_MASK___M 0x00000008 +#define PHYA_ROBE_PMI_EVENT_MASK_L__PMI_CBF_DMA_LAST_REQ_MASK___S 3 +#define PHYA_ROBE_PMI_EVENT_MASK_L__PMI_CBF_DMA_REQ_MASK___M 0x00000004 +#define PHYA_ROBE_PMI_EVENT_MASK_L__PMI_CBF_DMA_REQ_MASK___S 2 +#define PHYA_ROBE_PMI_EVENT_MASK_L__PMI_ECO_EVENT_MASK___M 0x00000002 +#define PHYA_ROBE_PMI_EVENT_MASK_L__PMI_ECO_EVENT_MASK___S 1 +#define PHYA_ROBE_PMI_EVENT_MASK_L__PMI_ERROR_EVENT_MASK___M 0x00000001 +#define PHYA_ROBE_PMI_EVENT_MASK_L__PMI_ERROR_EVENT_MASK___S 0 +#define PHYA_ROBE_PMI_EVENT_MASK_L___M 0x0000003F +#define PHYA_ROBE_PMI_EVENT_MASK_L___S 0 + +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L (0x004B0030) +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L___RWC QCSR_REG_RO +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L___POR 0x00000000 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_11___POR 0x0 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_10___POR 0x0 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_9___POR 0x0 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_8___POR 0x0 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_7___POR 0x0 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_6___POR 0x0 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_5___POR 0x0 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_4___POR 0x0 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_3___POR 0x0 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_2___POR 0x0 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_1___POR 0x0 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_0___POR 0x0 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_11___M 0x00000800 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_11___S 11 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_10___M 0x00000400 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_10___S 10 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_9___M 0x00000200 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_9___S 9 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_8___M 0x00000100 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_8___S 8 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_7___M 0x00000080 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_7___S 7 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_6___M 0x00000040 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_6___S 6 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_5___M 0x00000020 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_5___S 5 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_4___M 0x00000010 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_4___S 4 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_3___M 0x00000008 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_3___S 3 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_2___M 0x00000004 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_2___S 2 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_1___M 0x00000002 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_1___S 1 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_0___M 0x00000001 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L__IP_TLV_STATUS_0___S 0 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L___M 0x00000FFF +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_0_L___S 0 + +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L (0x004B0038) +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L___POR 0x00000FFF +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_11___POR 0x1 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_10___POR 0x1 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_9___POR 0x1 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_8___POR 0x1 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_7___POR 0x1 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_6___POR 0x1 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_5___POR 0x1 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_4___POR 0x1 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_3___POR 0x1 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_2___POR 0x1 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_1___POR 0x1 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_0___POR 0x1 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_11___M 0x00000800 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_11___S 11 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_10___M 0x00000400 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_10___S 10 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_9___M 0x00000200 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_9___S 9 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_8___M 0x00000100 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_8___S 8 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_7___M 0x00000080 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_7___S 7 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_6___M 0x00000040 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_6___S 6 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_5___M 0x00000020 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_5___S 5 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_4___M 0x00000010 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_4___S 4 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_3___M 0x00000008 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_3___S 3 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_2___M 0x00000004 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_2___S 2 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_1___M 0x00000002 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_1___S 1 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_0___M 0x00000001 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L__IP_TLV_MASK_0___S 0 +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L___M 0x00000FFF +#define PHYA_ROBE_PMI_EVENT_IP_TLV_IP_TLV_1_L___S 0 + +#define PHYA_ROBE_PMI_CODE_L (0x004B0040) +#define PHYA_ROBE_PMI_CODE_L___RWC QCSR_REG_RO +#define PHYA_ROBE_PMI_CODE_L___POR 0x00000100 +#define PHYA_ROBE_PMI_CODE_L__IP_TLV_FIFO_EMPTY___POR 0x1 +#define PHYA_ROBE_PMI_CODE_L__PMI_ERROR_CODE___POR 0x00 +#define PHYA_ROBE_PMI_CODE_L__IP_TLV_FIFO_EMPTY___M 0x00000100 +#define PHYA_ROBE_PMI_CODE_L__IP_TLV_FIFO_EMPTY___S 8 +#define PHYA_ROBE_PMI_CODE_L__PMI_ERROR_CODE___M 0x0000001F +#define PHYA_ROBE_PMI_CODE_L__PMI_ERROR_CODE___S 0 +#define PHYA_ROBE_PMI_CODE_L___M 0x0000011F +#define PHYA_ROBE_PMI_CODE_L___S 0 + +#define PHYA_ROBE_PMI_INFO_L (0x004B0048) +#define PHYA_ROBE_PMI_INFO_L___RWC QCSR_REG_RO +#define PHYA_ROBE_PMI_INFO_L___POR 0x00000000 +#define PHYA_ROBE_PMI_INFO_L__PMI_ERROR_INFO___POR 0x00000000 +#define PHYA_ROBE_PMI_INFO_L__PMI_ERROR_INFO___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_INFO_L__PMI_ERROR_INFO___S 0 +#define PHYA_ROBE_PMI_INFO_L___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_INFO_L___S 0 + +#define PHYA_ROBE_PMI_STATUS_L (0x004B0050) +#define PHYA_ROBE_PMI_STATUS_L___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_STATUS_L___POR 0x00000000 +#define PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_7___POR 0x0 +#define PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_6___POR 0x0 +#define PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_5___POR 0x0 +#define PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_4___POR 0x0 +#define PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_3___POR 0x0 +#define PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_2___POR 0x0 +#define PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_1___POR 0x0 +#define PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_0___POR 0x0 +#define PHYA_ROBE_PMI_STATUS_L__PMI_RSSI_PKT_END_MISMATCH___POR 0x0 +#define PHYA_ROBE_PMI_STATUS_L__PMI_WATCHDOG_TIMEOUT___POR 0x0 +#define PHYA_ROBE_PMI_STATUS_L__PMI_CBF_DMA_FIFO_OVERFLOW___POR 0x0 +#define PHYA_ROBE_PMI_STATUS_L__PMI_FIFO_READ_ERROR___POR 0x0 +#define PHYA_ROBE_PMI_STATUS_L__PMI_OP_TLV_FORMAT_ERROR___POR 0x0 +#define PHYA_ROBE_PMI_STATUS_L__PMI_OP_CF_FIFO_OVERFLOW___POR 0x0 +#define PHYA_ROBE_PMI_STATUS_L__PMI_OP_NCF_FIFO_OVERFLOW___POR 0x0 +#define PHYA_ROBE_PMI_STATUS_L__PMI_IP_TLV_FORMAT_ERROR___POR 0x0 +#define PHYA_ROBE_PMI_STATUS_L__PMI_IP_FIFO_OVERFLOW___POR 0x0 +#define PHYA_ROBE_PMI_STATUS_L__PMI_CBF_DMA_REQ_ERROR___POR 0x0 +#define PHYA_ROBE_PMI_STATUS_L__PMI_ECO_ERROR___POR 0x0 +#define PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_7___M 0x00040000 +#define PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_7___S 18 +#define PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_6___M 0x00020000 +#define PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_6___S 17 +#define PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_5___M 0x00010000 +#define PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_5___S 16 +#define PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_4___M 0x00008000 +#define PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_4___S 15 +#define PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_3___M 0x00004000 +#define PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_3___S 14 +#define PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_2___M 0x00002000 +#define PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_2___S 13 +#define PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_1___M 0x00001000 +#define PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_1___S 12 +#define PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_0___M 0x00000800 +#define PHYA_ROBE_PMI_STATUS_L__PMI_SPARE_ERROR_0___S 11 +#define PHYA_ROBE_PMI_STATUS_L__PMI_RSSI_PKT_END_MISMATCH___M 0x00000400 +#define PHYA_ROBE_PMI_STATUS_L__PMI_RSSI_PKT_END_MISMATCH___S 10 +#define PHYA_ROBE_PMI_STATUS_L__PMI_WATCHDOG_TIMEOUT___M 0x00000200 +#define PHYA_ROBE_PMI_STATUS_L__PMI_WATCHDOG_TIMEOUT___S 9 +#define PHYA_ROBE_PMI_STATUS_L__PMI_CBF_DMA_FIFO_OVERFLOW___M 0x00000100 +#define PHYA_ROBE_PMI_STATUS_L__PMI_CBF_DMA_FIFO_OVERFLOW___S 8 +#define PHYA_ROBE_PMI_STATUS_L__PMI_FIFO_READ_ERROR___M 0x00000080 +#define PHYA_ROBE_PMI_STATUS_L__PMI_FIFO_READ_ERROR___S 7 +#define PHYA_ROBE_PMI_STATUS_L__PMI_OP_TLV_FORMAT_ERROR___M 0x00000040 +#define PHYA_ROBE_PMI_STATUS_L__PMI_OP_TLV_FORMAT_ERROR___S 6 +#define PHYA_ROBE_PMI_STATUS_L__PMI_OP_CF_FIFO_OVERFLOW___M 0x00000020 +#define PHYA_ROBE_PMI_STATUS_L__PMI_OP_CF_FIFO_OVERFLOW___S 5 +#define PHYA_ROBE_PMI_STATUS_L__PMI_OP_NCF_FIFO_OVERFLOW___M 0x00000010 +#define PHYA_ROBE_PMI_STATUS_L__PMI_OP_NCF_FIFO_OVERFLOW___S 4 +#define PHYA_ROBE_PMI_STATUS_L__PMI_IP_TLV_FORMAT_ERROR___M 0x00000008 +#define PHYA_ROBE_PMI_STATUS_L__PMI_IP_TLV_FORMAT_ERROR___S 3 +#define PHYA_ROBE_PMI_STATUS_L__PMI_IP_FIFO_OVERFLOW___M 0x00000004 +#define PHYA_ROBE_PMI_STATUS_L__PMI_IP_FIFO_OVERFLOW___S 2 +#define PHYA_ROBE_PMI_STATUS_L__PMI_CBF_DMA_REQ_ERROR___M 0x00000002 +#define PHYA_ROBE_PMI_STATUS_L__PMI_CBF_DMA_REQ_ERROR___S 1 +#define PHYA_ROBE_PMI_STATUS_L__PMI_ECO_ERROR___M 0x00000001 +#define PHYA_ROBE_PMI_STATUS_L__PMI_ECO_ERROR___S 0 +#define PHYA_ROBE_PMI_STATUS_L___M 0x0007FFFF +#define PHYA_ROBE_PMI_STATUS_L___S 0 + +#define PHYA_ROBE_PMI_MASK_L (0x004B0058) +#define PHYA_ROBE_PMI_MASK_L___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_MASK_L___POR 0x0007FFFF +#define PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_7_MASK___POR 0x1 +#define PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_6_MASK___POR 0x1 +#define PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_5_MASK___POR 0x1 +#define PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_4_MASK___POR 0x1 +#define PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_3_MASK___POR 0x1 +#define PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_2_MASK___POR 0x1 +#define PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_1_MASK___POR 0x1 +#define PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_0_MASK___POR 0x1 +#define PHYA_ROBE_PMI_MASK_L__PMI_RSSI_PKT_END_MISMATCH_MASK___POR 0x1 +#define PHYA_ROBE_PMI_MASK_L__PMI_WATCHDOG_TIMEOUT_MASK___POR 0x1 +#define PHYA_ROBE_PMI_MASK_L__PMI_CBF_DMA_FIFO_OVERFLOW_MASK___POR 0x1 +#define PHYA_ROBE_PMI_MASK_L__PMI_FIFO_READ_ERROR_MASK___POR 0x1 +#define PHYA_ROBE_PMI_MASK_L__PMI_OP_TLV_FORMAT_ERROR_MASK___POR 0x1 +#define PHYA_ROBE_PMI_MASK_L__PMI_OP_CF_FIFO_OVERFLOW_MASK___POR 0x1 +#define PHYA_ROBE_PMI_MASK_L__PMI_OP_NCF_FIFO_OVERFLOW_MASK___POR 0x1 +#define PHYA_ROBE_PMI_MASK_L__PMI_IP_TLV_FORMAT_ERROR_MASK___POR 0x1 +#define PHYA_ROBE_PMI_MASK_L__PMI_IP_FIFO_OVERFLOW_MASK___POR 0x1 +#define PHYA_ROBE_PMI_MASK_L__PMI_CBF_DMA_REQ_ERROR_MASK___POR 0x1 +#define PHYA_ROBE_PMI_MASK_L__PMI_ECO_ERROR_MASK___POR 0x1 +#define PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_7_MASK___M 0x00040000 +#define PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_7_MASK___S 18 +#define PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_6_MASK___M 0x00020000 +#define PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_6_MASK___S 17 +#define PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_5_MASK___M 0x00010000 +#define PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_5_MASK___S 16 +#define PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_4_MASK___M 0x00008000 +#define PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_4_MASK___S 15 +#define PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_3_MASK___M 0x00004000 +#define PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_3_MASK___S 14 +#define PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_2_MASK___M 0x00002000 +#define PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_2_MASK___S 13 +#define PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_1_MASK___M 0x00001000 +#define PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_1_MASK___S 12 +#define PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_0_MASK___M 0x00000800 +#define PHYA_ROBE_PMI_MASK_L__PMI_SPARE_ERROR_0_MASK___S 11 +#define PHYA_ROBE_PMI_MASK_L__PMI_RSSI_PKT_END_MISMATCH_MASK___M 0x00000400 +#define PHYA_ROBE_PMI_MASK_L__PMI_RSSI_PKT_END_MISMATCH_MASK___S 10 +#define PHYA_ROBE_PMI_MASK_L__PMI_WATCHDOG_TIMEOUT_MASK___M 0x00000200 +#define PHYA_ROBE_PMI_MASK_L__PMI_WATCHDOG_TIMEOUT_MASK___S 9 +#define PHYA_ROBE_PMI_MASK_L__PMI_CBF_DMA_FIFO_OVERFLOW_MASK___M 0x00000100 +#define PHYA_ROBE_PMI_MASK_L__PMI_CBF_DMA_FIFO_OVERFLOW_MASK___S 8 +#define PHYA_ROBE_PMI_MASK_L__PMI_FIFO_READ_ERROR_MASK___M 0x00000080 +#define PHYA_ROBE_PMI_MASK_L__PMI_FIFO_READ_ERROR_MASK___S 7 +#define PHYA_ROBE_PMI_MASK_L__PMI_OP_TLV_FORMAT_ERROR_MASK___M 0x00000040 +#define PHYA_ROBE_PMI_MASK_L__PMI_OP_TLV_FORMAT_ERROR_MASK___S 6 +#define PHYA_ROBE_PMI_MASK_L__PMI_OP_CF_FIFO_OVERFLOW_MASK___M 0x00000020 +#define PHYA_ROBE_PMI_MASK_L__PMI_OP_CF_FIFO_OVERFLOW_MASK___S 5 +#define PHYA_ROBE_PMI_MASK_L__PMI_OP_NCF_FIFO_OVERFLOW_MASK___M 0x00000010 +#define PHYA_ROBE_PMI_MASK_L__PMI_OP_NCF_FIFO_OVERFLOW_MASK___S 4 +#define PHYA_ROBE_PMI_MASK_L__PMI_IP_TLV_FORMAT_ERROR_MASK___M 0x00000008 +#define PHYA_ROBE_PMI_MASK_L__PMI_IP_TLV_FORMAT_ERROR_MASK___S 3 +#define PHYA_ROBE_PMI_MASK_L__PMI_IP_FIFO_OVERFLOW_MASK___M 0x00000004 +#define PHYA_ROBE_PMI_MASK_L__PMI_IP_FIFO_OVERFLOW_MASK___S 2 +#define PHYA_ROBE_PMI_MASK_L__PMI_CBF_DMA_REQ_ERROR_MASK___M 0x00000002 +#define PHYA_ROBE_PMI_MASK_L__PMI_CBF_DMA_REQ_ERROR_MASK___S 1 +#define PHYA_ROBE_PMI_MASK_L__PMI_ECO_ERROR_MASK___M 0x00000001 +#define PHYA_ROBE_PMI_MASK_L__PMI_ECO_ERROR_MASK___S 0 +#define PHYA_ROBE_PMI_MASK_L___M 0x0007FFFF +#define PHYA_ROBE_PMI_MASK_L___S 0 + +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_n(n) (0x004B0060+0x8*(n)) +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_n_nMIN 0 +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_n_nMAX 0 +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_n_ELEM 1 +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_n___RWC QCSR_REG_RO +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_n___POR 0x00000000 +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_n__IP_DWORDS_RECEIVED___POR 0x0000 +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_n__IP_TLV_END_FLAG___POR 0x0 +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_n__IP_TLV_TAG_FLAG___POR 0x0 +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_n__IP_DWORDS_RECEIVED___M 0xFFFF0000 +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_n__IP_DWORDS_RECEIVED___S 16 +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_n__IP_TLV_END_FLAG___M 0x00000300 +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_n__IP_TLV_END_FLAG___S 8 +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_n__IP_TLV_TAG_FLAG___M 0x00000003 +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_n__IP_TLV_TAG_FLAG___S 0 +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_n___M 0xFFFF0303 +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_n___S 0 +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_0 (0x004B0060) +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_0___RWC QCSR_REG_RO +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_0__IP_DWORDS_RECEIVED___M 0xFFFF0000 +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_0__IP_DWORDS_RECEIVED___S 16 +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_0__IP_TLV_END_FLAG___M 0x00000300 +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_0__IP_TLV_END_FLAG___S 8 +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_0__IP_TLV_TAG_FLAG___M 0x00000003 +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_L_0__IP_TLV_TAG_FLAG___S 0 + +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_U (0x004B0064) +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_U___RWC QCSR_REG_RO +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_U___POR 0x00000000 +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_U__IP_ACTIVE___POR 0x0 +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_U__IP_TLV_LEN___POR 0x0000 +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_U__IP_ACTIVE___M 0x00010000 +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_U__IP_ACTIVE___S 16 +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_U__IP_TLV_LEN___M 0x0000FFFF +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_U__IP_TLV_LEN___S 0 +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_U___M 0x0001FFFF +#define PHYA_ROBE_PMI_IP_TLV_BUS_STATUS_U___S 0 + +#define PHYA_ROBE_PMI_IP_LAST_TAG_L (0x004B0068) +#define PHYA_ROBE_PMI_IP_LAST_TAG_L___RWC QCSR_REG_RO +#define PHYA_ROBE_PMI_IP_LAST_TAG_L___POR 0x00000000 +#define PHYA_ROBE_PMI_IP_LAST_TAG_L__IP_LAST_TAG1___POR 0x000 +#define PHYA_ROBE_PMI_IP_LAST_TAG_L__IP_LAST_TAG0___POR 0x000 +#define PHYA_ROBE_PMI_IP_LAST_TAG_L__IP_LAST_TAG1___M 0x01FF0000 +#define PHYA_ROBE_PMI_IP_LAST_TAG_L__IP_LAST_TAG1___S 16 +#define PHYA_ROBE_PMI_IP_LAST_TAG_L__IP_LAST_TAG0___M 0x000001FF +#define PHYA_ROBE_PMI_IP_LAST_TAG_L__IP_LAST_TAG0___S 0 +#define PHYA_ROBE_PMI_IP_LAST_TAG_L___M 0x01FF01FF +#define PHYA_ROBE_PMI_IP_LAST_TAG_L___S 0 + +#define PHYA_ROBE_PMI_IP_LAST_TAG_U (0x004B006C) +#define PHYA_ROBE_PMI_IP_LAST_TAG_U___RWC QCSR_REG_RO +#define PHYA_ROBE_PMI_IP_LAST_TAG_U___POR 0x00000000 +#define PHYA_ROBE_PMI_IP_LAST_TAG_U__IP_LAST_TAG3___POR 0x000 +#define PHYA_ROBE_PMI_IP_LAST_TAG_U__IP_LAST_TAG2___POR 0x000 +#define PHYA_ROBE_PMI_IP_LAST_TAG_U__IP_LAST_TAG3___M 0x01FF0000 +#define PHYA_ROBE_PMI_IP_LAST_TAG_U__IP_LAST_TAG3___S 16 +#define PHYA_ROBE_PMI_IP_LAST_TAG_U__IP_LAST_TAG2___M 0x000001FF +#define PHYA_ROBE_PMI_IP_LAST_TAG_U__IP_LAST_TAG2___S 0 +#define PHYA_ROBE_PMI_IP_LAST_TAG_U___M 0x01FF01FF +#define PHYA_ROBE_PMI_IP_LAST_TAG_U___S 0 + +#define PHYA_ROBE_PMI_OP_TLV_STATUS_L (0x004B0070) +#define PHYA_ROBE_PMI_OP_TLV_STATUS_L___RWC QCSR_REG_RO +#define PHYA_ROBE_PMI_OP_TLV_STATUS_L___POR 0x00000000 +#define PHYA_ROBE_PMI_OP_TLV_STATUS_L__OP_TLV_LEN___POR 0x0000 +#define PHYA_ROBE_PMI_OP_TLV_STATUS_L__OP_BYTES_SENT___POR 0x0000 +#define PHYA_ROBE_PMI_OP_TLV_STATUS_L__OP_TLV_LEN___M 0xFFFF0000 +#define PHYA_ROBE_PMI_OP_TLV_STATUS_L__OP_TLV_LEN___S 16 +#define PHYA_ROBE_PMI_OP_TLV_STATUS_L__OP_BYTES_SENT___M 0x0000FFFF +#define PHYA_ROBE_PMI_OP_TLV_STATUS_L__OP_BYTES_SENT___S 0 +#define PHYA_ROBE_PMI_OP_TLV_STATUS_L___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_OP_TLV_STATUS_L___S 0 + +#define PHYA_ROBE_PMI_OP_TLV_STATUS_U (0x004B0074) +#define PHYA_ROBE_PMI_OP_TLV_STATUS_U___RWC QCSR_REG_RO +#define PHYA_ROBE_PMI_OP_TLV_STATUS_U___POR 0x00000000 +#define PHYA_ROBE_PMI_OP_TLV_STATUS_U__OP_ACTIVE___POR 0x0 +#define PHYA_ROBE_PMI_OP_TLV_STATUS_U__OP_ACTIVE___M 0x00000001 +#define PHYA_ROBE_PMI_OP_TLV_STATUS_U__OP_ACTIVE___S 0 +#define PHYA_ROBE_PMI_OP_TLV_STATUS_U___M 0x00000001 +#define PHYA_ROBE_PMI_OP_TLV_STATUS_U___S 0 + +#define PHYA_ROBE_PMI_OP_TLV_HISTORY_L (0x004B0078) +#define PHYA_ROBE_PMI_OP_TLV_HISTORY_L___RWC QCSR_REG_RO +#define PHYA_ROBE_PMI_OP_TLV_HISTORY_L___POR 0x00000000 +#define PHYA_ROBE_PMI_OP_TLV_HISTORY_L__OP_LAST_TAG1___POR 0x000 +#define PHYA_ROBE_PMI_OP_TLV_HISTORY_L__OP_LAST_TAG0___POR 0x000 +#define PHYA_ROBE_PMI_OP_TLV_HISTORY_L__OP_LAST_TAG1___M 0x01FF0000 +#define PHYA_ROBE_PMI_OP_TLV_HISTORY_L__OP_LAST_TAG1___S 16 +#define PHYA_ROBE_PMI_OP_TLV_HISTORY_L__OP_LAST_TAG0___M 0x000001FF +#define PHYA_ROBE_PMI_OP_TLV_HISTORY_L__OP_LAST_TAG0___S 0 +#define PHYA_ROBE_PMI_OP_TLV_HISTORY_L___M 0x01FF01FF +#define PHYA_ROBE_PMI_OP_TLV_HISTORY_L___S 0 + +#define PHYA_ROBE_PMI_OP_TLV_HISTORY_U (0x004B007C) +#define PHYA_ROBE_PMI_OP_TLV_HISTORY_U___RWC QCSR_REG_RO +#define PHYA_ROBE_PMI_OP_TLV_HISTORY_U___POR 0x00000000 +#define PHYA_ROBE_PMI_OP_TLV_HISTORY_U__OP_LAST_TAG3___POR 0x000 +#define PHYA_ROBE_PMI_OP_TLV_HISTORY_U__OP_LAST_TAG2___POR 0x000 +#define PHYA_ROBE_PMI_OP_TLV_HISTORY_U__OP_LAST_TAG3___M 0x01FF0000 +#define PHYA_ROBE_PMI_OP_TLV_HISTORY_U__OP_LAST_TAG3___S 16 +#define PHYA_ROBE_PMI_OP_TLV_HISTORY_U__OP_LAST_TAG2___M 0x000001FF +#define PHYA_ROBE_PMI_OP_TLV_HISTORY_U__OP_LAST_TAG2___S 0 +#define PHYA_ROBE_PMI_OP_TLV_HISTORY_U___M 0x01FF01FF +#define PHYA_ROBE_PMI_OP_TLV_HISTORY_U___S 0 + +#define PHYA_ROBE_PMI_PMI_DEBUG_CONFIG_L (0x004B0080) +#define PHYA_ROBE_PMI_PMI_DEBUG_CONFIG_L___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_PMI_DEBUG_CONFIG_L___POR 0x00000000 +#define PHYA_ROBE_PMI_PMI_DEBUG_CONFIG_L__PHYDBG_SELECT___POR 0x0 +#define PHYA_ROBE_PMI_PMI_DEBUG_CONFIG_L__PHYDBG_SELECT___M 0x00000003 +#define PHYA_ROBE_PMI_PMI_DEBUG_CONFIG_L__PHYDBG_SELECT___S 0 +#define PHYA_ROBE_PMI_PMI_DEBUG_CONFIG_L___M 0x00000003 +#define PHYA_ROBE_PMI_PMI_DEBUG_CONFIG_L___S 0 + +#define PHYA_ROBE_PMI_DEBUG_STATE_L (0x004B0088) +#define PHYA_ROBE_PMI_DEBUG_STATE_L___RWC QCSR_REG_RO +#define PHYA_ROBE_PMI_DEBUG_STATE_L___POR 0x00000000 +#define PHYA_ROBE_PMI_DEBUG_STATE_L__DEBUG_STATE___POR 0x00000000 +#define PHYA_ROBE_PMI_DEBUG_STATE_L__DEBUG_STATE___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_DEBUG_STATE_L__DEBUG_STATE___S 0 +#define PHYA_ROBE_PMI_DEBUG_STATE_L___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_DEBUG_STATE_L___S 0 + +#define PHYA_ROBE_PMI_PMI_WATCHDOG_CONFIG_L (0x004B0090) +#define PHYA_ROBE_PMI_PMI_WATCHDOG_CONFIG_L___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_PMI_WATCHDOG_CONFIG_L___POR 0x000001FF +#define PHYA_ROBE_PMI_PMI_WATCHDOG_CONFIG_L__WATCHDOG_TIMER_DURATION___POR 0x0000 +#define PHYA_ROBE_PMI_PMI_WATCHDOG_CONFIG_L__WATCHDOG_MASK___POR 0x1FF +#define PHYA_ROBE_PMI_PMI_WATCHDOG_CONFIG_L__WATCHDOG_TIMER_DURATION___M 0xFFFF0000 +#define PHYA_ROBE_PMI_PMI_WATCHDOG_CONFIG_L__WATCHDOG_TIMER_DURATION___S 16 +#define PHYA_ROBE_PMI_PMI_WATCHDOG_CONFIG_L__WATCHDOG_MASK___M 0x000001FF +#define PHYA_ROBE_PMI_PMI_WATCHDOG_CONFIG_L__WATCHDOG_MASK___S 0 +#define PHYA_ROBE_PMI_PMI_WATCHDOG_CONFIG_L___M 0xFFFF01FF +#define PHYA_ROBE_PMI_PMI_WATCHDOG_CONFIG_L___S 0 + +#define PHYA_ROBE_PMI_PMI_WATCHDOG_STATUS_L (0x004B0098) +#define PHYA_ROBE_PMI_PMI_WATCHDOG_STATUS_L___RWC QCSR_REG_RO +#define PHYA_ROBE_PMI_PMI_WATCHDOG_STATUS_L___POR 0x00000000 +#define PHYA_ROBE_PMI_PMI_WATCHDOG_STATUS_L__WATCHDOG_TIMEOUT_SIGNATURE___POR 0x000 +#define PHYA_ROBE_PMI_PMI_WATCHDOG_STATUS_L__WATCHDOG_TIMEOUT_SIGNATURE___M 0x00000FFF +#define PHYA_ROBE_PMI_PMI_WATCHDOG_STATUS_L__WATCHDOG_TIMEOUT_SIGNATURE___S 0 +#define PHYA_ROBE_PMI_PMI_WATCHDOG_STATUS_L___M 0x00000FFF +#define PHYA_ROBE_PMI_PMI_WATCHDOG_STATUS_L___S 0 + +#define PHYA_ROBE_PMI_PMI_PHYDBG_CONFIG_L (0x004B00A0) +#define PHYA_ROBE_PMI_PMI_PHYDBG_CONFIG_L___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_PMI_PHYDBG_CONFIG_L___POR 0x00000000 +#define PHYA_ROBE_PMI_PMI_PHYDBG_CONFIG_L__DEBUGMUX_RAW_MODE___POR 0x0 +#define PHYA_ROBE_PMI_PMI_PHYDBG_CONFIG_L__DEBUGMUX_EVENT_EN___POR 0x00 +#define PHYA_ROBE_PMI_PMI_PHYDBG_CONFIG_L__DEBUGMUX_RAW_MODE___M 0x00000100 +#define PHYA_ROBE_PMI_PMI_PHYDBG_CONFIG_L__DEBUGMUX_RAW_MODE___S 8 +#define PHYA_ROBE_PMI_PMI_PHYDBG_CONFIG_L__DEBUGMUX_EVENT_EN___M 0x000000FF +#define PHYA_ROBE_PMI_PMI_PHYDBG_CONFIG_L__DEBUGMUX_EVENT_EN___S 0 +#define PHYA_ROBE_PMI_PMI_PHYDBG_CONFIG_L___M 0x000001FF +#define PHYA_ROBE_PMI_PMI_PHYDBG_CONFIG_L___S 0 + +#define PHYA_ROBE_PMI_PUBLIC_IN_SPARE_L (0x004B00A8) +#define PHYA_ROBE_PMI_PUBLIC_IN_SPARE_L___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_PUBLIC_IN_SPARE_L___POR 0x00000000 +#define PHYA_ROBE_PMI_PUBLIC_IN_SPARE_L__PMI_PUBLIC_IN_SPARE_0___POR 0x00000000 +#define PHYA_ROBE_PMI_PUBLIC_IN_SPARE_L__PMI_PUBLIC_IN_SPARE_0___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_PUBLIC_IN_SPARE_L__PMI_PUBLIC_IN_SPARE_0___S 0 +#define PHYA_ROBE_PMI_PUBLIC_IN_SPARE_L___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_PUBLIC_IN_SPARE_L___S 0 + +#define PHYA_ROBE_PMI_PUBLIC_IN_SPARE_U (0x004B00AC) +#define PHYA_ROBE_PMI_PUBLIC_IN_SPARE_U___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_PUBLIC_IN_SPARE_U___POR 0x00000000 +#define PHYA_ROBE_PMI_PUBLIC_IN_SPARE_U__PMI_PUBLIC_IN_SPARE_1___POR 0x00000000 +#define PHYA_ROBE_PMI_PUBLIC_IN_SPARE_U__PMI_PUBLIC_IN_SPARE_1___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_PUBLIC_IN_SPARE_U__PMI_PUBLIC_IN_SPARE_1___S 0 +#define PHYA_ROBE_PMI_PUBLIC_IN_SPARE_U___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_PUBLIC_IN_SPARE_U___S 0 + +#define PHYA_ROBE_PMI_PUBLIC_OUT_SPARE_L (0x004B00B0) +#define PHYA_ROBE_PMI_PUBLIC_OUT_SPARE_L___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_PUBLIC_OUT_SPARE_L___POR 0x00000000 +#define PHYA_ROBE_PMI_PUBLIC_OUT_SPARE_L__PMI_PUBLIC_OUT_SPARE_0___POR 0x00000000 +#define PHYA_ROBE_PMI_PUBLIC_OUT_SPARE_L__PMI_PUBLIC_OUT_SPARE_0___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_PUBLIC_OUT_SPARE_L__PMI_PUBLIC_OUT_SPARE_0___S 0 +#define PHYA_ROBE_PMI_PUBLIC_OUT_SPARE_L___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_PUBLIC_OUT_SPARE_L___S 0 + +#define PHYA_ROBE_PMI_PUBLIC_OUT_SPARE_U (0x004B00B4) +#define PHYA_ROBE_PMI_PUBLIC_OUT_SPARE_U___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_PUBLIC_OUT_SPARE_U___POR 0x00000000 +#define PHYA_ROBE_PMI_PUBLIC_OUT_SPARE_U__PMI_PUBLIC_OUT_SPARE_1___POR 0x00000000 +#define PHYA_ROBE_PMI_PUBLIC_OUT_SPARE_U__PMI_PUBLIC_OUT_SPARE_1___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_PUBLIC_OUT_SPARE_U__PMI_PUBLIC_OUT_SPARE_1___S 0 +#define PHYA_ROBE_PMI_PUBLIC_OUT_SPARE_U___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_PUBLIC_OUT_SPARE_U___S 0 + +#define PHYA_ROBE_PMI_CRC_CHK_CFG_L (0x004B00B8) +#define PHYA_ROBE_PMI_CRC_CHK_CFG_L___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_CRC_CHK_CFG_L___POR 0x00000000 +#define PHYA_ROBE_PMI_CRC_CHK_CFG_L__CRC_PKT_FILTER_USER___POR 0x00 +#define PHYA_ROBE_PMI_CRC_CHK_CFG_L__CRC_PKT_FILTER_ENABLE___POR 0x0 +#define PHYA_ROBE_PMI_CRC_CHK_CFG_L__CHECKER_RESET___POR 0x0 +#define PHYA_ROBE_PMI_CRC_CHK_CFG_L__CHECKER_ENABLE___POR 0x0 +#define PHYA_ROBE_PMI_CRC_CHK_CFG_L__CRC_PKT_FILTER_USER___M 0x3F000000 +#define PHYA_ROBE_PMI_CRC_CHK_CFG_L__CRC_PKT_FILTER_USER___S 24 +#define PHYA_ROBE_PMI_CRC_CHK_CFG_L__CRC_PKT_FILTER_ENABLE___M 0x00030000 +#define PHYA_ROBE_PMI_CRC_CHK_CFG_L__CRC_PKT_FILTER_ENABLE___S 16 +#define PHYA_ROBE_PMI_CRC_CHK_CFG_L__CHECKER_RESET___M 0x00000100 +#define PHYA_ROBE_PMI_CRC_CHK_CFG_L__CHECKER_RESET___S 8 +#define PHYA_ROBE_PMI_CRC_CHK_CFG_L__CHECKER_ENABLE___M 0x00000001 +#define PHYA_ROBE_PMI_CRC_CHK_CFG_L__CHECKER_ENABLE___S 0 +#define PHYA_ROBE_PMI_CRC_CHK_CFG_L___M 0x3F030101 +#define PHYA_ROBE_PMI_CRC_CHK_CFG_L___S 0 + +#define PHYA_ROBE_PMI_CRC_CHK_CFG_U (0x004B00BC) +#define PHYA_ROBE_PMI_CRC_CHK_CFG_U___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_CRC_CHK_CFG_U___POR 0x00000000 +#define PHYA_ROBE_PMI_CRC_CHK_CFG_U__CRC_PKT_FILTER_VALUE___POR 0x00000000 +#define PHYA_ROBE_PMI_CRC_CHK_CFG_U__CRC_PKT_FILTER_VALUE___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_CRC_CHK_CFG_U__CRC_PKT_FILTER_VALUE___S 0 +#define PHYA_ROBE_PMI_CRC_CHK_CFG_U___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_CRC_CHK_CFG_U___S 0 + +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_L (0x004B00C0) +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_L___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_L___POR 0x00000000 +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_L__MPDU_PASS_COUNT___POR 0x0000 +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_L__CRC_MPDU_ACTIVE___POR 0x0 +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_L__MPDU_PASS_COUNT___M 0xFFFF0000 +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_L__MPDU_PASS_COUNT___S 16 +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_L__CRC_MPDU_ACTIVE___M 0x00000001 +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_L__CRC_MPDU_ACTIVE___S 0 +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_L___M 0xFFFF0001 +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_L___S 0 + +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_U (0x004B00C4) +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_U___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_U___POR 0x00000000 +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_U__MPDU_CHK_COUNT___POR 0x0000 +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_U__AMPDU_PASS_COUNT___POR 0x0000 +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_U__MPDU_CHK_COUNT___M 0xFFFF0000 +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_U__MPDU_CHK_COUNT___S 16 +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_U__AMPDU_PASS_COUNT___M 0x0000FFFF +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_U__AMPDU_PASS_COUNT___S 0 +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_U___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_0_U___S 0 + +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_L (0x004B00C8) +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_L___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_L___POR 0x00000000 +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_L__AMPDU_ABORT_COUNT___POR 0x0000 +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_L__AMPDU_CHK_COUNT___POR 0x0000 +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_L__AMPDU_ABORT_COUNT___M 0xFFFF0000 +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_L__AMPDU_ABORT_COUNT___S 16 +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_L__AMPDU_CHK_COUNT___M 0x0000FFFF +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_L__AMPDU_CHK_COUNT___S 0 +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_L___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_L___S 0 + +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_U (0x004B00CC) +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_U___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_U___POR 0x00000000 +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_U__DBG_ADC_CAPTURE_FCS_RESULT___POR 0x0 +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_U__DBG_ADC_CAPTURE_FCS_RESULT___M 0x00000003 +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_U__DBG_ADC_CAPTURE_FCS_RESULT___S 0 +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_U___M 0x00000003 +#define PHYA_ROBE_PMI_CRC_CHK_MONITOR_1_U___S 0 + +#define PHYA_ROBE_PMI_PRIVATE_IN_SPARE_L (0x004B00D0) +#define PHYA_ROBE_PMI_PRIVATE_IN_SPARE_L___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_PRIVATE_IN_SPARE_L___POR 0x00000000 +#define PHYA_ROBE_PMI_PRIVATE_IN_SPARE_L__PMI_PRIVATE_IN_SPARE_0___POR 0x00000000 +#define PHYA_ROBE_PMI_PRIVATE_IN_SPARE_L__PMI_PRIVATE_IN_SPARE_0___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_PRIVATE_IN_SPARE_L__PMI_PRIVATE_IN_SPARE_0___S 0 +#define PHYA_ROBE_PMI_PRIVATE_IN_SPARE_L___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_PRIVATE_IN_SPARE_L___S 0 + +#define PHYA_ROBE_PMI_PRIVATE_IN_SPARE_U (0x004B00D4) +#define PHYA_ROBE_PMI_PRIVATE_IN_SPARE_U___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_PRIVATE_IN_SPARE_U___POR 0x00000000 +#define PHYA_ROBE_PMI_PRIVATE_IN_SPARE_U__PMI_PRIVATE_IN_SPARE_1___POR 0x00000000 +#define PHYA_ROBE_PMI_PRIVATE_IN_SPARE_U__PMI_PRIVATE_IN_SPARE_1___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_PRIVATE_IN_SPARE_U__PMI_PRIVATE_IN_SPARE_1___S 0 +#define PHYA_ROBE_PMI_PRIVATE_IN_SPARE_U___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_PRIVATE_IN_SPARE_U___S 0 + +#define PHYA_ROBE_PMI_PRIVATE_OUT_SPARE_L (0x004B00D8) +#define PHYA_ROBE_PMI_PRIVATE_OUT_SPARE_L___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_PRIVATE_OUT_SPARE_L___POR 0x00000000 +#define PHYA_ROBE_PMI_PRIVATE_OUT_SPARE_L__PMI_PRIVATE_OUT_SPARE_0___POR 0x00000000 +#define PHYA_ROBE_PMI_PRIVATE_OUT_SPARE_L__PMI_PRIVATE_OUT_SPARE_0___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_PRIVATE_OUT_SPARE_L__PMI_PRIVATE_OUT_SPARE_0___S 0 +#define PHYA_ROBE_PMI_PRIVATE_OUT_SPARE_L___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_PRIVATE_OUT_SPARE_L___S 0 + +#define PHYA_ROBE_PMI_PRIVATE_OUT_SPARE_U (0x004B00DC) +#define PHYA_ROBE_PMI_PRIVATE_OUT_SPARE_U___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_PRIVATE_OUT_SPARE_U___POR 0x00000000 +#define PHYA_ROBE_PMI_PRIVATE_OUT_SPARE_U__PMI_PRIVATE_OUT_SPARE_1___POR 0x00000000 +#define PHYA_ROBE_PMI_PRIVATE_OUT_SPARE_U__PMI_PRIVATE_OUT_SPARE_1___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_PRIVATE_OUT_SPARE_U__PMI_PRIVATE_OUT_SPARE_1___S 0 +#define PHYA_ROBE_PMI_PRIVATE_OUT_SPARE_U___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_PRIVATE_OUT_SPARE_U___S 0 + +#define PHYA_ROBE_PMI_IP_TLV_LENGTH_L (0x004B00E0) +#define PHYA_ROBE_PMI_IP_TLV_LENGTH_L___RWC QCSR_REG_RO +#define PHYA_ROBE_PMI_IP_TLV_LENGTH_L___POR 0x00000000 +#define PHYA_ROBE_PMI_IP_TLV_LENGTH_L__IP_TLV_LENGTH___POR 0x0000 +#define PHYA_ROBE_PMI_IP_TLV_LENGTH_L__IP_TLV_LENGTH___M 0x0000FFFF +#define PHYA_ROBE_PMI_IP_TLV_LENGTH_L__IP_TLV_LENGTH___S 0 +#define PHYA_ROBE_PMI_IP_TLV_LENGTH_L___M 0x0000FFFF +#define PHYA_ROBE_PMI_IP_TLV_LENGTH_L___S 0 + +#define PHYA_ROBE_PMI_IP_TLV_DATA_L_n(n) (0x004B00E8+0x8*(n)) +#define PHYA_ROBE_PMI_IP_TLV_DATA_L_n_nMIN 0 +#define PHYA_ROBE_PMI_IP_TLV_DATA_L_n_nMAX 0 +#define PHYA_ROBE_PMI_IP_TLV_DATA_L_n_ELEM 1 +#define PHYA_ROBE_PMI_IP_TLV_DATA_L_n___RWC QCSR_REG_RO +#define PHYA_ROBE_PMI_IP_TLV_DATA_L_n___POR 0x00000000 +#define PHYA_ROBE_PMI_IP_TLV_DATA_L_n__IP_TLV_DATA_1___POR 0x0000 +#define PHYA_ROBE_PMI_IP_TLV_DATA_L_n__IP_TLV_DATA_0___POR 0x0000 +#define PHYA_ROBE_PMI_IP_TLV_DATA_L_n__IP_TLV_DATA_1___M 0xFFFF0000 +#define PHYA_ROBE_PMI_IP_TLV_DATA_L_n__IP_TLV_DATA_1___S 16 +#define PHYA_ROBE_PMI_IP_TLV_DATA_L_n__IP_TLV_DATA_0___M 0x0000FFFF +#define PHYA_ROBE_PMI_IP_TLV_DATA_L_n__IP_TLV_DATA_0___S 0 +#define PHYA_ROBE_PMI_IP_TLV_DATA_L_n___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_IP_TLV_DATA_L_n___S 0 +#define PHYA_ROBE_PMI_IP_TLV_DATA_L_0 (0x004B00E8) +#define PHYA_ROBE_PMI_IP_TLV_DATA_L_0___RWC QCSR_REG_RO +#define PHYA_ROBE_PMI_IP_TLV_DATA_L_0__IP_TLV_DATA_1___M 0xFFFF0000 +#define PHYA_ROBE_PMI_IP_TLV_DATA_L_0__IP_TLV_DATA_1___S 16 +#define PHYA_ROBE_PMI_IP_TLV_DATA_L_0__IP_TLV_DATA_0___M 0x0000FFFF +#define PHYA_ROBE_PMI_IP_TLV_DATA_L_0__IP_TLV_DATA_0___S 0 + +#define PHYA_ROBE_PMI_IP_TLV_RD_SPARE_L (0x004B00F0) +#define PHYA_ROBE_PMI_IP_TLV_RD_SPARE_L___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_IP_TLV_RD_SPARE_L___POR 0x00000000 +#define PHYA_ROBE_PMI_IP_TLV_RD_SPARE_L__PMI_IP_TLV_RD_SPARE_0___POR 0x00000000 +#define PHYA_ROBE_PMI_IP_TLV_RD_SPARE_L__PMI_IP_TLV_RD_SPARE_0___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_IP_TLV_RD_SPARE_L__PMI_IP_TLV_RD_SPARE_0___S 0 +#define PHYA_ROBE_PMI_IP_TLV_RD_SPARE_L___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_IP_TLV_RD_SPARE_L___S 0 + +#define PHYA_ROBE_PMI_IP_TLV_RD_SPARE_U (0x004B00F4) +#define PHYA_ROBE_PMI_IP_TLV_RD_SPARE_U___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_IP_TLV_RD_SPARE_U___POR 0x00000000 +#define PHYA_ROBE_PMI_IP_TLV_RD_SPARE_U__PMI_IP_TLV_RD_SPARE_1___POR 0x00000000 +#define PHYA_ROBE_PMI_IP_TLV_RD_SPARE_U__PMI_IP_TLV_RD_SPARE_1___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_IP_TLV_RD_SPARE_U__PMI_IP_TLV_RD_SPARE_1___S 0 +#define PHYA_ROBE_PMI_IP_TLV_RD_SPARE_U___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_IP_TLV_RD_SPARE_U___S 0 + +#define PHYA_ROBE_PMI_OP_TLV_DATA_NCF_L_n(n) (0x004B00F8+0x8*(n)) +#define PHYA_ROBE_PMI_OP_TLV_DATA_NCF_L_n_nMIN 0 +#define PHYA_ROBE_PMI_OP_TLV_DATA_NCF_L_n_nMAX 0 +#define PHYA_ROBE_PMI_OP_TLV_DATA_NCF_L_n_ELEM 1 +#define PHYA_ROBE_PMI_OP_TLV_DATA_NCF_L_n___RWC QCSR_REG_WO +#define PHYA_ROBE_PMI_OP_TLV_DATA_NCF_L_n___POR 0x00000000 +#define PHYA_ROBE_PMI_OP_TLV_DATA_NCF_L_n__OP_TLV_DATA_NCF_0___POR 0x00000000 +#define PHYA_ROBE_PMI_OP_TLV_DATA_NCF_L_n__OP_TLV_DATA_NCF_0___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_OP_TLV_DATA_NCF_L_n__OP_TLV_DATA_NCF_0___S 0 +#define PHYA_ROBE_PMI_OP_TLV_DATA_NCF_L_n___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_OP_TLV_DATA_NCF_L_n___S 0 +#define PHYA_ROBE_PMI_OP_TLV_DATA_NCF_L_0 (0x004B00F8) +#define PHYA_ROBE_PMI_OP_TLV_DATA_NCF_L_0___RWC QCSR_REG_WO +#define PHYA_ROBE_PMI_OP_TLV_DATA_NCF_L_0__OP_TLV_DATA_NCF_0___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_OP_TLV_DATA_NCF_L_0__OP_TLV_DATA_NCF_0___S 0 + +#define PHYA_ROBE_PMI_OP_TLV_DATA_NCF_U_n(n) (0x004B00FC+0x8*(n)) +#define PHYA_ROBE_PMI_OP_TLV_DATA_NCF_U_n_nMIN 0 +#define PHYA_ROBE_PMI_OP_TLV_DATA_NCF_U_n_nMAX 0 +#define PHYA_ROBE_PMI_OP_TLV_DATA_NCF_U_n_ELEM 1 +#define PHYA_ROBE_PMI_OP_TLV_DATA_NCF_U_n___RWC QCSR_REG_WO +#define PHYA_ROBE_PMI_OP_TLV_DATA_NCF_U_n___POR 0x00000000 +#define PHYA_ROBE_PMI_OP_TLV_DATA_NCF_U_n__OP_TLV_DATA_NCF_1___POR 0x00000000 +#define PHYA_ROBE_PMI_OP_TLV_DATA_NCF_U_n__OP_TLV_DATA_NCF_1___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_OP_TLV_DATA_NCF_U_n__OP_TLV_DATA_NCF_1___S 0 +#define PHYA_ROBE_PMI_OP_TLV_DATA_NCF_U_n___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_OP_TLV_DATA_NCF_U_n___S 0 +#define PHYA_ROBE_PMI_OP_TLV_DATA_NCF_U_0 (0x004B00FC) +#define PHYA_ROBE_PMI_OP_TLV_DATA_NCF_U_0___RWC QCSR_REG_WO +#define PHYA_ROBE_PMI_OP_TLV_DATA_NCF_U_0__OP_TLV_DATA_NCF_1___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_OP_TLV_DATA_NCF_U_0__OP_TLV_DATA_NCF_1___S 0 + +#define PHYA_ROBE_PMI_OP_TLV_CF_DATA_L_n(n) (0x004B0118+0x8*(n)) +#define PHYA_ROBE_PMI_OP_TLV_CF_DATA_L_n_nMIN 0 +#define PHYA_ROBE_PMI_OP_TLV_CF_DATA_L_n_nMAX 0 +#define PHYA_ROBE_PMI_OP_TLV_CF_DATA_L_n_ELEM 1 +#define PHYA_ROBE_PMI_OP_TLV_CF_DATA_L_n___RWC QCSR_REG_WO +#define PHYA_ROBE_PMI_OP_TLV_CF_DATA_L_n___POR 0x00000000 +#define PHYA_ROBE_PMI_OP_TLV_CF_DATA_L_n__OP_TLV_DATA_CF_0___POR 0x00000000 +#define PHYA_ROBE_PMI_OP_TLV_CF_DATA_L_n__OP_TLV_DATA_CF_0___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_OP_TLV_CF_DATA_L_n__OP_TLV_DATA_CF_0___S 0 +#define PHYA_ROBE_PMI_OP_TLV_CF_DATA_L_n___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_OP_TLV_CF_DATA_L_n___S 0 +#define PHYA_ROBE_PMI_OP_TLV_CF_DATA_L_0 (0x004B0118) +#define PHYA_ROBE_PMI_OP_TLV_CF_DATA_L_0___RWC QCSR_REG_WO +#define PHYA_ROBE_PMI_OP_TLV_CF_DATA_L_0__OP_TLV_DATA_CF_0___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_OP_TLV_CF_DATA_L_0__OP_TLV_DATA_CF_0___S 0 + +#define PHYA_ROBE_PMI_OP_TLV_CF_DATA_U_n(n) (0x004B011C+0x8*(n)) +#define PHYA_ROBE_PMI_OP_TLV_CF_DATA_U_n_nMIN 0 +#define PHYA_ROBE_PMI_OP_TLV_CF_DATA_U_n_nMAX 0 +#define PHYA_ROBE_PMI_OP_TLV_CF_DATA_U_n_ELEM 1 +#define PHYA_ROBE_PMI_OP_TLV_CF_DATA_U_n___RWC QCSR_REG_WO +#define PHYA_ROBE_PMI_OP_TLV_CF_DATA_U_n___POR 0x00000000 +#define PHYA_ROBE_PMI_OP_TLV_CF_DATA_U_n__OP_TLV_DATA_CF_1___POR 0x00000000 +#define PHYA_ROBE_PMI_OP_TLV_CF_DATA_U_n__OP_TLV_DATA_CF_1___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_OP_TLV_CF_DATA_U_n__OP_TLV_DATA_CF_1___S 0 +#define PHYA_ROBE_PMI_OP_TLV_CF_DATA_U_n___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_OP_TLV_CF_DATA_U_n___S 0 +#define PHYA_ROBE_PMI_OP_TLV_CF_DATA_U_0 (0x004B011C) +#define PHYA_ROBE_PMI_OP_TLV_CF_DATA_U_0___RWC QCSR_REG_WO +#define PHYA_ROBE_PMI_OP_TLV_CF_DATA_U_0__OP_TLV_DATA_CF_1___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_OP_TLV_CF_DATA_U_0__OP_TLV_DATA_CF_1___S 0 + +#define PHYA_ROBE_PMI_OP_TLV_CFG_L (0x004B0138) +#define PHYA_ROBE_PMI_OP_TLV_CFG_L___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_OP_TLV_CFG_L___POR 0x00000000 +#define PHYA_ROBE_PMI_OP_TLV_CFG_L__OP_TLV_DISABLE_ROBE_TLVS___POR 0x0 +#define PHYA_ROBE_PMI_OP_TLV_CFG_L__CBF_ZERO_CV_DATA_BYTE___POR 0x0 +#define PHYA_ROBE_PMI_OP_TLV_CFG_L__CBF_ZERO_CV_DATA_ENABLE___POR 0x0 +#define PHYA_ROBE_PMI_OP_TLV_CFG_L__CBF_FILTER_BYTES_PER_DATA_REQ___POR 0x0 +#define PHYA_ROBE_PMI_OP_TLV_CFG_L__OP_TLV_DISABLE_ROBE_TLVS___M 0x01000000 +#define PHYA_ROBE_PMI_OP_TLV_CFG_L__OP_TLV_DISABLE_ROBE_TLVS___S 24 +#define PHYA_ROBE_PMI_OP_TLV_CFG_L__CBF_ZERO_CV_DATA_BYTE___M 0x000F0000 +#define PHYA_ROBE_PMI_OP_TLV_CFG_L__CBF_ZERO_CV_DATA_BYTE___S 16 +#define PHYA_ROBE_PMI_OP_TLV_CFG_L__CBF_ZERO_CV_DATA_ENABLE___M 0x00000100 +#define PHYA_ROBE_PMI_OP_TLV_CFG_L__CBF_ZERO_CV_DATA_ENABLE___S 8 +#define PHYA_ROBE_PMI_OP_TLV_CFG_L__CBF_FILTER_BYTES_PER_DATA_REQ___M 0x00000001 +#define PHYA_ROBE_PMI_OP_TLV_CFG_L__CBF_FILTER_BYTES_PER_DATA_REQ___S 0 +#define PHYA_ROBE_PMI_OP_TLV_CFG_L___M 0x010F0101 +#define PHYA_ROBE_PMI_OP_TLV_CFG_L___S 0 + +#define PHYA_ROBE_PMI_OP_TLV_CFG_U (0x004B013C) +#define PHYA_ROBE_PMI_OP_TLV_CFG_U___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_OP_TLV_CFG_U___POR 0x00000003 +#define PHYA_ROBE_PMI_OP_TLV_CFG_U__CBF_BYTE_OFFSET___POR 0x0 +#define PHYA_ROBE_PMI_OP_TLV_CFG_U__CBF_BYTE_OFFSET_ENABLE___POR 0x0 +#define PHYA_ROBE_PMI_OP_TLV_CFG_U__OP_RESET_RSSI_PKTEND_MISMATCH___POR 0x0 +#define PHYA_ROBE_PMI_OP_TLV_CFG_U__ABORT_RESET_RSSI_PKTEND_MISMATCH___POR 0x3 +#define PHYA_ROBE_PMI_OP_TLV_CFG_U__CBF_BYTE_OFFSET___M 0x07000000 +#define PHYA_ROBE_PMI_OP_TLV_CFG_U__CBF_BYTE_OFFSET___S 24 +#define PHYA_ROBE_PMI_OP_TLV_CFG_U__CBF_BYTE_OFFSET_ENABLE___M 0x00010000 +#define PHYA_ROBE_PMI_OP_TLV_CFG_U__CBF_BYTE_OFFSET_ENABLE___S 16 +#define PHYA_ROBE_PMI_OP_TLV_CFG_U__OP_RESET_RSSI_PKTEND_MISMATCH___M 0x00000100 +#define PHYA_ROBE_PMI_OP_TLV_CFG_U__OP_RESET_RSSI_PKTEND_MISMATCH___S 8 +#define PHYA_ROBE_PMI_OP_TLV_CFG_U__ABORT_RESET_RSSI_PKTEND_MISMATCH___M 0x00000003 +#define PHYA_ROBE_PMI_OP_TLV_CFG_U__ABORT_RESET_RSSI_PKTEND_MISMATCH___S 0 +#define PHYA_ROBE_PMI_OP_TLV_CFG_U___M 0x07010103 +#define PHYA_ROBE_PMI_OP_TLV_CFG_U___S 0 + +#define PHYA_ROBE_PMI_OP_TLV_PARAMS_L (0x004B0140) +#define PHYA_ROBE_PMI_OP_TLV_PARAMS_L___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_OP_TLV_PARAMS_L___POR 0x00000000 +#define PHYA_ROBE_PMI_OP_TLV_PARAMS_L__OP_TLV_USER___POR 0x00 +#define PHYA_ROBE_PMI_OP_TLV_PARAMS_L__OP_TLV_TAG___POR 0x0 +#define PHYA_ROBE_PMI_OP_TLV_PARAMS_L__OP_TLV_USER___M 0x00003F00 +#define PHYA_ROBE_PMI_OP_TLV_PARAMS_L__OP_TLV_USER___S 8 +#define PHYA_ROBE_PMI_OP_TLV_PARAMS_L__OP_TLV_TAG___M 0x00000007 +#define PHYA_ROBE_PMI_OP_TLV_PARAMS_L__OP_TLV_TAG___S 0 +#define PHYA_ROBE_PMI_OP_TLV_PARAMS_L___M 0x00003F07 +#define PHYA_ROBE_PMI_OP_TLV_PARAMS_L___S 0 + +#define PHYA_ROBE_PMI_CBF_DMA_DATA_L_n(n) (0x004B0148+0x8*(n)) +#define PHYA_ROBE_PMI_CBF_DMA_DATA_L_n_nMIN 0 +#define PHYA_ROBE_PMI_CBF_DMA_DATA_L_n_nMAX 0 +#define PHYA_ROBE_PMI_CBF_DMA_DATA_L_n_ELEM 1 +#define PHYA_ROBE_PMI_CBF_DMA_DATA_L_n___RWC QCSR_REG_WO +#define PHYA_ROBE_PMI_CBF_DMA_DATA_L_n___POR 0x00000000 +#define PHYA_ROBE_PMI_CBF_DMA_DATA_L_n__CBF_DMA_DATA_0___POR 0x00000000 +#define PHYA_ROBE_PMI_CBF_DMA_DATA_L_n__CBF_DMA_DATA_0___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_CBF_DMA_DATA_L_n__CBF_DMA_DATA_0___S 0 +#define PHYA_ROBE_PMI_CBF_DMA_DATA_L_n___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_CBF_DMA_DATA_L_n___S 0 +#define PHYA_ROBE_PMI_CBF_DMA_DATA_L_0 (0x004B0148) +#define PHYA_ROBE_PMI_CBF_DMA_DATA_L_0___RWC QCSR_REG_WO +#define PHYA_ROBE_PMI_CBF_DMA_DATA_L_0__CBF_DMA_DATA_0___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_CBF_DMA_DATA_L_0__CBF_DMA_DATA_0___S 0 + +#define PHYA_ROBE_PMI_CBF_DMA_DATA_U_n(n) (0x004B014C+0x8*(n)) +#define PHYA_ROBE_PMI_CBF_DMA_DATA_U_n_nMIN 0 +#define PHYA_ROBE_PMI_CBF_DMA_DATA_U_n_nMAX 0 +#define PHYA_ROBE_PMI_CBF_DMA_DATA_U_n_ELEM 1 +#define PHYA_ROBE_PMI_CBF_DMA_DATA_U_n___RWC QCSR_REG_WO +#define PHYA_ROBE_PMI_CBF_DMA_DATA_U_n___POR 0x00000000 +#define PHYA_ROBE_PMI_CBF_DMA_DATA_U_n__CBF_DMA_DATA_1___POR 0x00000000 +#define PHYA_ROBE_PMI_CBF_DMA_DATA_U_n__CBF_DMA_DATA_1___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_CBF_DMA_DATA_U_n__CBF_DMA_DATA_1___S 0 +#define PHYA_ROBE_PMI_CBF_DMA_DATA_U_n___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_CBF_DMA_DATA_U_n___S 0 +#define PHYA_ROBE_PMI_CBF_DMA_DATA_U_0 (0x004B014C) +#define PHYA_ROBE_PMI_CBF_DMA_DATA_U_0___RWC QCSR_REG_WO +#define PHYA_ROBE_PMI_CBF_DMA_DATA_U_0__CBF_DMA_DATA_1___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_CBF_DMA_DATA_U_0__CBF_DMA_DATA_1___S 0 + +#define PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_L (0x004B0168) +#define PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_L___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_L___POR 0x00080400 +#define PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_L__CBF_DWORDS_PER_DMA___POR 0x08 +#define PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_L__CBF_BYTES_PER_CHUNK___POR 0x0400 +#define PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_L__CBF_DWORDS_PER_DMA___M 0x00FF0000 +#define PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_L__CBF_DWORDS_PER_DMA___S 16 +#define PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_L__CBF_BYTES_PER_CHUNK___M 0x00003FFF +#define PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_L__CBF_BYTES_PER_CHUNK___S 0 +#define PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_L___M 0x00FF3FFF +#define PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_L___S 0 + +#define PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_U (0x004B016C) +#define PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_U___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_U___POR 0x00000000 +#define PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_U__CBF_TRANSFER_ACTIVE___POR 0x0 +#define PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_U__CBF_USER___POR 0x00 +#define PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_U__CBF_BYTE_LENGTH___POR 0x0000 +#define PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_U__CBF_TRANSFER_ACTIVE___M 0x01000000 +#define PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_U__CBF_TRANSFER_ACTIVE___S 24 +#define PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_U__CBF_USER___M 0x003F0000 +#define PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_U__CBF_USER___S 16 +#define PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_U__CBF_BYTE_LENGTH___M 0x00003FFF +#define PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_U__CBF_BYTE_LENGTH___S 0 +#define PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_U___M 0x013F3FFF +#define PHYA_ROBE_PMI_CBF_TRANSFER_PARAMS_U___S 0 + +#define PHYA_ROBE_PMI_CBF_CONTROLS_L (0x004B0170) +#define PHYA_ROBE_PMI_CBF_CONTROLS_L___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_CBF_CONTROLS_L___POR 0x00000000 +#define PHYA_ROBE_PMI_CBF_CONTROLS_L__CBF_DATA_REQ___POR 0x0 +#define PHYA_ROBE_PMI_CBF_CONTROLS_L__CBF_FLUSH___POR 0x0 +#define PHYA_ROBE_PMI_CBF_CONTROLS_L__CBF_DATA_REQ___M 0x00000002 +#define PHYA_ROBE_PMI_CBF_CONTROLS_L__CBF_DATA_REQ___S 1 +#define PHYA_ROBE_PMI_CBF_CONTROLS_L__CBF_FLUSH___M 0x00000001 +#define PHYA_ROBE_PMI_CBF_CONTROLS_L__CBF_FLUSH___S 0 +#define PHYA_ROBE_PMI_CBF_CONTROLS_L___M 0x00000003 +#define PHYA_ROBE_PMI_CBF_CONTROLS_L___S 0 + +#define PHYA_ROBE_PMI_CBF_CHUNK_INFO_L (0x004B0178) +#define PHYA_ROBE_PMI_CBF_CHUNK_INFO_L___RWC QCSR_REG_RO +#define PHYA_ROBE_PMI_CBF_CHUNK_INFO_L___POR 0x00000000 +#define PHYA_ROBE_PMI_CBF_CHUNK_INFO_L__CBF_MAC_BYTES_PER_CHUNK___POR 0x0000 +#define PHYA_ROBE_PMI_CBF_CHUNK_INFO_L__CBF_MAC_BYTES_PER_CHUNK___M 0x00003FFF +#define PHYA_ROBE_PMI_CBF_CHUNK_INFO_L__CBF_MAC_BYTES_PER_CHUNK___S 0 +#define PHYA_ROBE_PMI_CBF_CHUNK_INFO_L___M 0x00003FFF +#define PHYA_ROBE_PMI_CBF_CHUNK_INFO_L___S 0 + +#define PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_L (0x004B0180) +#define PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_L___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_L___POR 0x00000000 +#define PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_L__CRC_PKT_LENGTH___POR 0x00000000 +#define PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_L__CRC_PKT_LENGTH___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_L__CRC_PKT_LENGTH___S 0 +#define PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_L___M 0xFFFFFFFF +#define PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_L___S 0 + +#define PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_U (0x004B0184) +#define PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_U___RWC QCSR_REG_RW +#define PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_U___POR 0x00000000 +#define PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_U__CRC_PKT_ACTIVE___POR 0x0 +#define PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_U__CRC_AMPDU_ACTIVE___POR 0x0 +#define PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_U__CRC_PKT_TYPE_11AC_11AX___POR 0x0 +#define PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_U__CRC_PKT_ACTIVE___M 0x00010000 +#define PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_U__CRC_PKT_ACTIVE___S 16 +#define PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_U__CRC_AMPDU_ACTIVE___M 0x00000100 +#define PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_U__CRC_AMPDU_ACTIVE___S 8 +#define PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_U__CRC_PKT_TYPE_11AC_11AX___M 0x00000001 +#define PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_U__CRC_PKT_TYPE_11AC_11AX___S 0 +#define PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_U___M 0x00010101 +#define PHYA_ROBE_PMI_CRC_CHK_PKT_PARAMS_U___S 0 + +#define PHYA_ROBE_ECO_CTRL_L (0x004B0188) +#define PHYA_ROBE_ECO_CTRL_L___RWC QCSR_REG_RW +#define PHYA_ROBE_ECO_CTRL_L___POR 0x00000000 +#define PHYA_ROBE_ECO_CTRL_L__ECO_CTRL___POR 0x00000000 +#define PHYA_ROBE_ECO_CTRL_L__ECO_CTRL___M 0xFFFFFFFF +#define PHYA_ROBE_ECO_CTRL_L__ECO_CTRL___S 0 +#define PHYA_ROBE_ECO_CTRL_L___M 0xFFFFFFFF +#define PHYA_ROBE_ECO_CTRL_L___S 0 + +#define PHYA_ROBE_ECO_CTRL_U (0x004B018C) +#define PHYA_ROBE_ECO_CTRL_U___RWC QCSR_REG_RW +#define PHYA_ROBE_ECO_CTRL_U___POR 0x00000000 +#define PHYA_ROBE_ECO_CTRL_U__ECO_CFG___POR 0x00000000 +#define PHYA_ROBE_ECO_CTRL_U__ECO_CFG___M 0xFFFFFFFF +#define PHYA_ROBE_ECO_CTRL_U__ECO_CFG___S 0 +#define PHYA_ROBE_ECO_CTRL_U___M 0xFFFFFFFF +#define PHYA_ROBE_ECO_CTRL_U___S 0 + +#define PHYA_ROBE_ECO_STAT_L (0x004B0190) +#define PHYA_ROBE_ECO_STAT_L___RWC QCSR_REG_RO +#define PHYA_ROBE_ECO_STAT_L___POR 0x00000000 +#define PHYA_ROBE_ECO_STAT_L__ECO_STAT___POR 0x00000000 +#define PHYA_ROBE_ECO_STAT_L__ECO_STAT___M 0xFFFFFFFF +#define PHYA_ROBE_ECO_STAT_L__ECO_STAT___S 0 +#define PHYA_ROBE_ECO_STAT_L___M 0xFFFFFFFF +#define PHYA_ROBE_ECO_STAT_L___S 0 + +#define PHYA_ROBE_EVENT_STATUS_L (0x004B0198) +#define PHYA_ROBE_EVENT_STATUS_L___RWC QCSR_REG_RW +#define PHYA_ROBE_EVENT_STATUS_L___POR 0x00000004 +#define PHYA_ROBE_EVENT_STATUS_L__EOP_EVENT___POR 0x0 +#define PHYA_ROBE_EVENT_STATUS_L__DCSR_LATCH_EVENT___POR 0x0 +#define PHYA_ROBE_EVENT_STATUS_L__SIG_EXT_DEC_EVENT___POR 0x0 +#define PHYA_ROBE_EVENT_STATUS_L__SIG_DEC_EVENT___POR 0x0 +#define PHYA_ROBE_EVENT_STATUS_L__PKT_START_EVENT___POR 0x1 +#define PHYA_ROBE_EVENT_STATUS_L__ECO_EVENT___POR 0x0 +#define PHYA_ROBE_EVENT_STATUS_L__ERROR_EVENT___POR 0x0 +#define PHYA_ROBE_EVENT_STATUS_L__EOP_EVENT___M 0x00000040 +#define PHYA_ROBE_EVENT_STATUS_L__EOP_EVENT___S 6 +#define PHYA_ROBE_EVENT_STATUS_L__DCSR_LATCH_EVENT___M 0x00000020 +#define PHYA_ROBE_EVENT_STATUS_L__DCSR_LATCH_EVENT___S 5 +#define PHYA_ROBE_EVENT_STATUS_L__SIG_EXT_DEC_EVENT___M 0x00000010 +#define PHYA_ROBE_EVENT_STATUS_L__SIG_EXT_DEC_EVENT___S 4 +#define PHYA_ROBE_EVENT_STATUS_L__SIG_DEC_EVENT___M 0x00000008 +#define PHYA_ROBE_EVENT_STATUS_L__SIG_DEC_EVENT___S 3 +#define PHYA_ROBE_EVENT_STATUS_L__PKT_START_EVENT___M 0x00000004 +#define PHYA_ROBE_EVENT_STATUS_L__PKT_START_EVENT___S 2 +#define PHYA_ROBE_EVENT_STATUS_L__ECO_EVENT___M 0x00000002 +#define PHYA_ROBE_EVENT_STATUS_L__ECO_EVENT___S 1 +#define PHYA_ROBE_EVENT_STATUS_L__ERROR_EVENT___M 0x00000001 +#define PHYA_ROBE_EVENT_STATUS_L__ERROR_EVENT___S 0 +#define PHYA_ROBE_EVENT_STATUS_L___M 0x0000007F +#define PHYA_ROBE_EVENT_STATUS_L___S 0 + +#define PHYA_ROBE_EVENT_MASK_L (0x004B01A0) +#define PHYA_ROBE_EVENT_MASK_L___RWC QCSR_REG_RW +#define PHYA_ROBE_EVENT_MASK_L___POR 0x0000007F +#define PHYA_ROBE_EVENT_MASK_L__EOP_EVENT_MASK___POR 0x1 +#define PHYA_ROBE_EVENT_MASK_L__DCSR_LATCH_EVENT_MASK___POR 0x1 +#define PHYA_ROBE_EVENT_MASK_L__SIG_EXT_DEC_EVENT_MASK___POR 0x1 +#define PHYA_ROBE_EVENT_MASK_L__SIG_DEC_EVENT_MASK___POR 0x1 +#define PHYA_ROBE_EVENT_MASK_L__PKT_START_EVENT_MASK___POR 0x1 +#define PHYA_ROBE_EVENT_MASK_L__ECO_EVENT_MASK___POR 0x1 +#define PHYA_ROBE_EVENT_MASK_L__ERROR_EVENT_MASK___POR 0x1 +#define PHYA_ROBE_EVENT_MASK_L__EOP_EVENT_MASK___M 0x00000040 +#define PHYA_ROBE_EVENT_MASK_L__EOP_EVENT_MASK___S 6 +#define PHYA_ROBE_EVENT_MASK_L__DCSR_LATCH_EVENT_MASK___M 0x00000020 +#define PHYA_ROBE_EVENT_MASK_L__DCSR_LATCH_EVENT_MASK___S 5 +#define PHYA_ROBE_EVENT_MASK_L__SIG_EXT_DEC_EVENT_MASK___M 0x00000010 +#define PHYA_ROBE_EVENT_MASK_L__SIG_EXT_DEC_EVENT_MASK___S 4 +#define PHYA_ROBE_EVENT_MASK_L__SIG_DEC_EVENT_MASK___M 0x00000008 +#define PHYA_ROBE_EVENT_MASK_L__SIG_DEC_EVENT_MASK___S 3 +#define PHYA_ROBE_EVENT_MASK_L__PKT_START_EVENT_MASK___M 0x00000004 +#define PHYA_ROBE_EVENT_MASK_L__PKT_START_EVENT_MASK___S 2 +#define PHYA_ROBE_EVENT_MASK_L__ECO_EVENT_MASK___M 0x00000002 +#define PHYA_ROBE_EVENT_MASK_L__ECO_EVENT_MASK___S 1 +#define PHYA_ROBE_EVENT_MASK_L__ERROR_EVENT_MASK___M 0x00000001 +#define PHYA_ROBE_EVENT_MASK_L__ERROR_EVENT_MASK___S 0 +#define PHYA_ROBE_EVENT_MASK_L___M 0x0000007F +#define PHYA_ROBE_EVENT_MASK_L___S 0 + +#define PHYA_ROBE_ERROR_CODE_L (0x004B01A8) +#define PHYA_ROBE_ERROR_CODE_L___RWC QCSR_REG_RO +#define PHYA_ROBE_ERROR_CODE_L___POR 0x00000000 +#define PHYA_ROBE_ERROR_CODE_L__ERROR_CODE___POR 0x00 +#define PHYA_ROBE_ERROR_CODE_L__ERROR_CODE___M 0x0000003F +#define PHYA_ROBE_ERROR_CODE_L__ERROR_CODE___S 0 +#define PHYA_ROBE_ERROR_CODE_L___M 0x0000003F +#define PHYA_ROBE_ERROR_CODE_L___S 0 + +#define PHYA_ROBE_ERROR_INFO_L (0x004B01B0) +#define PHYA_ROBE_ERROR_INFO_L___RWC QCSR_REG_RO +#define PHYA_ROBE_ERROR_INFO_L___POR 0x00000000 +#define PHYA_ROBE_ERROR_INFO_L__ERROR_INFO___POR 0x00000000 +#define PHYA_ROBE_ERROR_INFO_L__ERROR_INFO___M 0xFFFFFFFF +#define PHYA_ROBE_ERROR_INFO_L__ERROR_INFO___S 0 +#define PHYA_ROBE_ERROR_INFO_L___M 0xFFFFFFFF +#define PHYA_ROBE_ERROR_INFO_L___S 0 + +#define PHYA_ROBE_ERROR_STATUS_L (0x004B01B8) +#define PHYA_ROBE_ERROR_STATUS_L___RWC QCSR_REG_RO +#define PHYA_ROBE_ERROR_STATUS_L___POR 0x00000000 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_26___POR 0x0 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_25___POR 0x0 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_24___POR 0x0 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_23___POR 0x0 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_22___POR 0x0 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_21___POR 0x0 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_20___POR 0x0 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_19___POR 0x0 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_18___POR 0x0 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_17___POR 0x0 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_16___POR 0x0 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_15___POR 0x0 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_14___POR 0x0 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_13___POR 0x0 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_12___POR 0x0 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_11___POR 0x0 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_10___POR 0x0 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_9___POR 0x0 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_8___POR 0x0 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_7___POR 0x0 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_6___POR 0x0 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_5___POR 0x0 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_4___POR 0x0 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_3___POR 0x0 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_2___POR 0x0 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_1___POR 0x0 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_0___POR 0x0 +#define PHYA_ROBE_ERROR_STATUS_L__EOP_ERROR___POR 0x0 +#define PHYA_ROBE_ERROR_STATUS_L__DCSR_LATCH_ERROR___POR 0x0 +#define PHYA_ROBE_ERROR_STATUS_L__SIG_EXT_DEC_ERROR___POR 0x0 +#define PHYA_ROBE_ERROR_STATUS_L__SIG_DEC_ERROR___POR 0x0 +#define PHYA_ROBE_ERROR_STATUS_L__PKT_START_ERROR___POR 0x0 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_26___M 0x80000000 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_26___S 31 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_25___M 0x40000000 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_25___S 30 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_24___M 0x20000000 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_24___S 29 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_23___M 0x10000000 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_23___S 28 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_22___M 0x08000000 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_22___S 27 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_21___M 0x04000000 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_21___S 26 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_20___M 0x02000000 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_20___S 25 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_19___M 0x01000000 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_19___S 24 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_18___M 0x00800000 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_18___S 23 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_17___M 0x00400000 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_17___S 22 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_16___M 0x00200000 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_16___S 21 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_15___M 0x00100000 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_15___S 20 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_14___M 0x00080000 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_14___S 19 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_13___M 0x00040000 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_13___S 18 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_12___M 0x00020000 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_12___S 17 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_11___M 0x00010000 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_11___S 16 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_10___M 0x00008000 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_10___S 15 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_9___M 0x00004000 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_9___S 14 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_8___M 0x00002000 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_8___S 13 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_7___M 0x00001000 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_7___S 12 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_6___M 0x00000800 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_6___S 11 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_5___M 0x00000400 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_5___S 10 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_4___M 0x00000200 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_4___S 9 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_3___M 0x00000100 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_3___S 8 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_2___M 0x00000080 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_2___S 7 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_1___M 0x00000040 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_1___S 6 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_0___M 0x00000020 +#define PHYA_ROBE_ERROR_STATUS_L__ROBE_SPARE_ERROR_0___S 5 +#define PHYA_ROBE_ERROR_STATUS_L__EOP_ERROR___M 0x00000010 +#define PHYA_ROBE_ERROR_STATUS_L__EOP_ERROR___S 4 +#define PHYA_ROBE_ERROR_STATUS_L__DCSR_LATCH_ERROR___M 0x00000008 +#define PHYA_ROBE_ERROR_STATUS_L__DCSR_LATCH_ERROR___S 3 +#define PHYA_ROBE_ERROR_STATUS_L__SIG_EXT_DEC_ERROR___M 0x00000004 +#define PHYA_ROBE_ERROR_STATUS_L__SIG_EXT_DEC_ERROR___S 2 +#define PHYA_ROBE_ERROR_STATUS_L__SIG_DEC_ERROR___M 0x00000002 +#define PHYA_ROBE_ERROR_STATUS_L__SIG_DEC_ERROR___S 1 +#define PHYA_ROBE_ERROR_STATUS_L__PKT_START_ERROR___M 0x00000001 +#define PHYA_ROBE_ERROR_STATUS_L__PKT_START_ERROR___S 0 +#define PHYA_ROBE_ERROR_STATUS_L___M 0xFFFFFFFF +#define PHYA_ROBE_ERROR_STATUS_L___S 0 + +#define PHYA_ROBE_ERROR_MASK_L (0x004B01C0) +#define PHYA_ROBE_ERROR_MASK_L___RWC QCSR_REG_RW +#define PHYA_ROBE_ERROR_MASK_L___POR 0xFFFFFFFF +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_26_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_25_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_24_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_23_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_22_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_21_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_20_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_19_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_18_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_17_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_16_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_15_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_14_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_13_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_12_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_11_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_10_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_9_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_8_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_7_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_6_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_5_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_4_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_3_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_2_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_1_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_0_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_MASK_L__EOP_ERROR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_MASK_L__DCSR_LATCH_ERROR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_MASK_L__SIG_EXT_DEC_ERROR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_MASK_L__SIG_DEC_ERROR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_MASK_L__PKT_START_ERROR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_26_MASK___M 0x80000000 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_26_MASK___S 31 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_25_MASK___M 0x40000000 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_25_MASK___S 30 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_24_MASK___M 0x20000000 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_24_MASK___S 29 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_23_MASK___M 0x10000000 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_23_MASK___S 28 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_22_MASK___M 0x08000000 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_22_MASK___S 27 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_21_MASK___M 0x04000000 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_21_MASK___S 26 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_20_MASK___M 0x02000000 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_20_MASK___S 25 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_19_MASK___M 0x01000000 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_19_MASK___S 24 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_18_MASK___M 0x00800000 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_18_MASK___S 23 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_17_MASK___M 0x00400000 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_17_MASK___S 22 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_16_MASK___M 0x00200000 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_16_MASK___S 21 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_15_MASK___M 0x00100000 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_15_MASK___S 20 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_14_MASK___M 0x00080000 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_14_MASK___S 19 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_13_MASK___M 0x00040000 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_13_MASK___S 18 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_12_MASK___M 0x00020000 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_12_MASK___S 17 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_11_MASK___M 0x00010000 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_11_MASK___S 16 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_10_MASK___M 0x00008000 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_10_MASK___S 15 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_9_MASK___M 0x00004000 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_9_MASK___S 14 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_8_MASK___M 0x00002000 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_8_MASK___S 13 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_7_MASK___M 0x00001000 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_7_MASK___S 12 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_6_MASK___M 0x00000800 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_6_MASK___S 11 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_5_MASK___M 0x00000400 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_5_MASK___S 10 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_4_MASK___M 0x00000200 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_4_MASK___S 9 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_3_MASK___M 0x00000100 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_3_MASK___S 8 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_2_MASK___M 0x00000080 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_2_MASK___S 7 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_1_MASK___M 0x00000040 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_1_MASK___S 6 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_0_MASK___M 0x00000020 +#define PHYA_ROBE_ERROR_MASK_L__ROBE_SPARE_ERROR_0_MASK___S 5 +#define PHYA_ROBE_ERROR_MASK_L__EOP_ERROR_MASK___M 0x00000010 +#define PHYA_ROBE_ERROR_MASK_L__EOP_ERROR_MASK___S 4 +#define PHYA_ROBE_ERROR_MASK_L__DCSR_LATCH_ERROR_MASK___M 0x00000008 +#define PHYA_ROBE_ERROR_MASK_L__DCSR_LATCH_ERROR_MASK___S 3 +#define PHYA_ROBE_ERROR_MASK_L__SIG_EXT_DEC_ERROR_MASK___M 0x00000004 +#define PHYA_ROBE_ERROR_MASK_L__SIG_EXT_DEC_ERROR_MASK___S 2 +#define PHYA_ROBE_ERROR_MASK_L__SIG_DEC_ERROR_MASK___M 0x00000002 +#define PHYA_ROBE_ERROR_MASK_L__SIG_DEC_ERROR_MASK___S 1 +#define PHYA_ROBE_ERROR_MASK_L__PKT_START_ERROR_MASK___M 0x00000001 +#define PHYA_ROBE_ERROR_MASK_L__PKT_START_ERROR_MASK___S 0 +#define PHYA_ROBE_ERROR_MASK_L___M 0xFFFFFFFF +#define PHYA_ROBE_ERROR_MASK_L___S 0 + +#define PHYA_ROBE_DEBUG_STATUS_0_L (0x004B01C8) +#define PHYA_ROBE_DEBUG_STATUS_0_L___RWC QCSR_REG_RO +#define PHYA_ROBE_DEBUG_STATUS_0_L___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_0_L__LATEST_LSIG___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_0_L__LATEST_LSIG___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_0_L__LATEST_LSIG___S 0 +#define PHYA_ROBE_DEBUG_STATUS_0_L___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_0_L___S 0 + +#define PHYA_ROBE_DEBUG_STATUS_0_U (0x004B01CC) +#define PHYA_ROBE_DEBUG_STATUS_0_U___RWC QCSR_REG_RO +#define PHYA_ROBE_DEBUG_STATUS_0_U___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_0_U__LATEST_RLSIG___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_0_U__LATEST_RLSIG___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_0_U__LATEST_RLSIG___S 0 +#define PHYA_ROBE_DEBUG_STATUS_0_U___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_0_U___S 0 + +#define PHYA_ROBE_DEBUG_STATUS_1_L (0x004B01D0) +#define PHYA_ROBE_DEBUG_STATUS_1_L___RWC QCSR_REG_RO +#define PHYA_ROBE_DEBUG_STATUS_1_L___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_1_L__LATEST_HTVHTHESIGA_0___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_1_L__LATEST_HTVHTHESIGA_0___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_1_L__LATEST_HTVHTHESIGA_0___S 0 +#define PHYA_ROBE_DEBUG_STATUS_1_L___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_1_L___S 0 + +#define PHYA_ROBE_DEBUG_STATUS_1_U (0x004B01D4) +#define PHYA_ROBE_DEBUG_STATUS_1_U___RWC QCSR_REG_RO +#define PHYA_ROBE_DEBUG_STATUS_1_U___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_1_U__LATEST_HTVHTHESIGA_1___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_1_U__LATEST_HTVHTHESIGA_1___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_1_U__LATEST_HTVHTHESIGA_1___S 0 +#define PHYA_ROBE_DEBUG_STATUS_1_U___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_1_U___S 0 + +#define PHYA_ROBE_DEBUG_STATUS_2_L (0x004B01D8) +#define PHYA_ROBE_DEBUG_STATUS_2_L___RWC QCSR_REG_RO +#define PHYA_ROBE_DEBUG_STATUS_2_L___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_2_L__LATEST_VHTSIGB___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_2_L__LATEST_VHTSIGB___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_2_L__LATEST_VHTSIGB___S 0 +#define PHYA_ROBE_DEBUG_STATUS_2_L___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_2_L___S 0 + +#define PHYA_ROBE_DEBUG_STATUS_30_L (0x004B01E0) +#define PHYA_ROBE_DEBUG_STATUS_30_L___RWC QCSR_REG_RO +#define PHYA_ROBE_DEBUG_STATUS_30_L___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_30_L__LATEST_HESIGB_COM_0_0___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_30_L__LATEST_HESIGB_COM_0_0___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_30_L__LATEST_HESIGB_COM_0_0___S 0 +#define PHYA_ROBE_DEBUG_STATUS_30_L___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_30_L___S 0 + +#define PHYA_ROBE_DEBUG_STATUS_30_U (0x004B01E4) +#define PHYA_ROBE_DEBUG_STATUS_30_U___RWC QCSR_REG_RO +#define PHYA_ROBE_DEBUG_STATUS_30_U___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_30_U__LATEST_HESIGB_COM_1_0___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_30_U__LATEST_HESIGB_COM_1_0___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_30_U__LATEST_HESIGB_COM_1_0___S 0 +#define PHYA_ROBE_DEBUG_STATUS_30_U___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_30_U___S 0 + +#define PHYA_ROBE_DEBUG_STATUS_31_L (0x004B01E8) +#define PHYA_ROBE_DEBUG_STATUS_31_L___RWC QCSR_REG_RO +#define PHYA_ROBE_DEBUG_STATUS_31_L___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_31_L__LATEST_HESIGB_COM_0_1___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_31_L__LATEST_HESIGB_COM_0_1___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_31_L__LATEST_HESIGB_COM_0_1___S 0 +#define PHYA_ROBE_DEBUG_STATUS_31_L___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_31_L___S 0 + +#define PHYA_ROBE_DEBUG_STATUS_31_U (0x004B01EC) +#define PHYA_ROBE_DEBUG_STATUS_31_U___RWC QCSR_REG_RO +#define PHYA_ROBE_DEBUG_STATUS_31_U___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_31_U__LATEST_HESIGB_COM_1_1___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_31_U__LATEST_HESIGB_COM_1_1___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_31_U__LATEST_HESIGB_COM_1_1___S 0 +#define PHYA_ROBE_DEBUG_STATUS_31_U___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_31_U___S 0 + +#define PHYA_ROBE_DEBUG_STATUS_40_L (0x004B01F0) +#define PHYA_ROBE_DEBUG_STATUS_40_L___RWC QCSR_REG_RO +#define PHYA_ROBE_DEBUG_STATUS_40_L___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_40_L__LATEST_HESIGB_USR_0_0___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_40_L__LATEST_HESIGB_USR_0_0___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_40_L__LATEST_HESIGB_USR_0_0___S 0 +#define PHYA_ROBE_DEBUG_STATUS_40_L___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_40_L___S 0 + +#define PHYA_ROBE_DEBUG_STATUS_40_U (0x004B01F4) +#define PHYA_ROBE_DEBUG_STATUS_40_U___RWC QCSR_REG_RO +#define PHYA_ROBE_DEBUG_STATUS_40_U___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_40_U__LATEST_HESIGB_USR_1_0___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_40_U__LATEST_HESIGB_USR_1_0___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_40_U__LATEST_HESIGB_USR_1_0___S 0 +#define PHYA_ROBE_DEBUG_STATUS_40_U___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_40_U___S 0 + +#define PHYA_ROBE_DEBUG_STATUS_41_L (0x004B01F8) +#define PHYA_ROBE_DEBUG_STATUS_41_L___RWC QCSR_REG_RO +#define PHYA_ROBE_DEBUG_STATUS_41_L___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_41_L__LATEST_HESIGB_USR_0_1___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_41_L__LATEST_HESIGB_USR_0_1___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_41_L__LATEST_HESIGB_USR_0_1___S 0 +#define PHYA_ROBE_DEBUG_STATUS_41_L___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_41_L___S 0 + +#define PHYA_ROBE_DEBUG_STATUS_41_U (0x004B01FC) +#define PHYA_ROBE_DEBUG_STATUS_41_U___RWC QCSR_REG_RO +#define PHYA_ROBE_DEBUG_STATUS_41_U___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_41_U__LATEST_HESIGB_USR_1_1___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_41_U__LATEST_HESIGB_USR_1_1___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_41_U__LATEST_HESIGB_USR_1_1___S 0 +#define PHYA_ROBE_DEBUG_STATUS_41_U___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_41_U___S 0 + +#define PHYA_ROBE_DEBUG_STATUS_50_L (0x004B0200) +#define PHYA_ROBE_DEBUG_STATUS_50_L___RWC QCSR_REG_RO +#define PHYA_ROBE_DEBUG_STATUS_50_L___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_50_L__LATCHED_HESIGB_USR_0_0___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_50_L__LATCHED_HESIGB_USR_0_0___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_50_L__LATCHED_HESIGB_USR_0_0___S 0 +#define PHYA_ROBE_DEBUG_STATUS_50_L___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_50_L___S 0 + +#define PHYA_ROBE_DEBUG_STATUS_50_U (0x004B0204) +#define PHYA_ROBE_DEBUG_STATUS_50_U___RWC QCSR_REG_RO +#define PHYA_ROBE_DEBUG_STATUS_50_U___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_50_U__LATCHED_HESIGB_USR_1_0___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_50_U__LATCHED_HESIGB_USR_1_0___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_50_U__LATCHED_HESIGB_USR_1_0___S 0 +#define PHYA_ROBE_DEBUG_STATUS_50_U___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_50_U___S 0 + +#define PHYA_ROBE_DEBUG_STATUS_51_L (0x004B0208) +#define PHYA_ROBE_DEBUG_STATUS_51_L___RWC QCSR_REG_RO +#define PHYA_ROBE_DEBUG_STATUS_51_L___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_51_L__LATCHED_HESIGB_USR_0_1___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_51_L__LATCHED_HESIGB_USR_0_1___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_51_L__LATCHED_HESIGB_USR_0_1___S 0 +#define PHYA_ROBE_DEBUG_STATUS_51_L___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_51_L___S 0 + +#define PHYA_ROBE_DEBUG_STATUS_51_U (0x004B020C) +#define PHYA_ROBE_DEBUG_STATUS_51_U___RWC QCSR_REG_RO +#define PHYA_ROBE_DEBUG_STATUS_51_U___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_51_U__LATCHED_HESIGB_USR_1_1___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_51_U__LATCHED_HESIGB_USR_1_1___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_51_U__LATCHED_HESIGB_USR_1_1___S 0 +#define PHYA_ROBE_DEBUG_STATUS_51_U___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_51_U___S 0 + +#define PHYA_ROBE_DEBUG_STATUS_6_L (0x004B0210) +#define PHYA_ROBE_DEBUG_STATUS_6_L___RWC QCSR_REG_RO +#define PHYA_ROBE_DEBUG_STATUS_6_L___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_6_L__TRFC_STATUS_0___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_6_L__TRFC_STATUS_0___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_6_L__TRFC_STATUS_0___S 0 +#define PHYA_ROBE_DEBUG_STATUS_6_L___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_6_L___S 0 + +#define PHYA_ROBE_DEBUG_STATUS_6_U (0x004B0214) +#define PHYA_ROBE_DEBUG_STATUS_6_U___RWC QCSR_REG_RO +#define PHYA_ROBE_DEBUG_STATUS_6_U___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_6_U__TRFC_STATUS_1___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_6_U__TRFC_STATUS_1___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_6_U__TRFC_STATUS_1___S 0 +#define PHYA_ROBE_DEBUG_STATUS_6_U___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_6_U___S 0 + +#define PHYA_ROBE_DEBUG_STATUS_7_L (0x004B0218) +#define PHYA_ROBE_DEBUG_STATUS_7_L___RWC QCSR_REG_RO +#define PHYA_ROBE_DEBUG_STATUS_7_L___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_7_L__TRFC_COUNT_DONE_USER_L32___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_7_L__TRFC_COUNT_DONE_USER_L32___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_7_L__TRFC_COUNT_DONE_USER_L32___S 0 +#define PHYA_ROBE_DEBUG_STATUS_7_L___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_7_L___S 0 + +#define PHYA_ROBE_DEBUG_STATUS_7_U (0x004B021C) +#define PHYA_ROBE_DEBUG_STATUS_7_U___RWC QCSR_REG_RO +#define PHYA_ROBE_DEBUG_STATUS_7_U___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_7_U__TRFC_COUNT_DONE_USER_U32___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_7_U__TRFC_COUNT_DONE_USER_U32___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_7_U__TRFC_COUNT_DONE_USER_U32___S 0 +#define PHYA_ROBE_DEBUG_STATUS_7_U___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_7_U___S 0 + +#define PHYA_ROBE_DEBUG_STATUS_8_L (0x004B0220) +#define PHYA_ROBE_DEBUG_STATUS_8_L___RWC QCSR_REG_RO +#define PHYA_ROBE_DEBUG_STATUS_8_L___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_8_L__LDPC_TIMEOUT_USER_L32___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_8_L__LDPC_TIMEOUT_USER_L32___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_8_L__LDPC_TIMEOUT_USER_L32___S 0 +#define PHYA_ROBE_DEBUG_STATUS_8_L___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_8_L___S 0 + +#define PHYA_ROBE_DEBUG_STATUS_8_U (0x004B0224) +#define PHYA_ROBE_DEBUG_STATUS_8_U___RWC QCSR_REG_RO +#define PHYA_ROBE_DEBUG_STATUS_8_U___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_8_U__LDPC_TIMEOUT_USER_U32___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_8_U__LDPC_TIMEOUT_USER_U32___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_8_U__LDPC_TIMEOUT_USER_U32___S 0 +#define PHYA_ROBE_DEBUG_STATUS_8_U___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_8_U___S 0 + +#define PHYA_ROBE_DEBUG_STATUS_9_L (0x004B0228) +#define PHYA_ROBE_DEBUG_STATUS_9_L___RWC QCSR_REG_RO +#define PHYA_ROBE_DEBUG_STATUS_9_L___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_9_L__OFDMA_DETECTED___POR 0x0 +#define PHYA_ROBE_DEBUG_STATUS_9_L__OFDMA_DETECTED___M 0x00000001 +#define PHYA_ROBE_DEBUG_STATUS_9_L__OFDMA_DETECTED___S 0 +#define PHYA_ROBE_DEBUG_STATUS_9_L___M 0x00000001 +#define PHYA_ROBE_DEBUG_STATUS_9_L___S 0 + +#define PHYA_ROBE_DEBUG_STATUS_9_U (0x004B022C) +#define PHYA_ROBE_DEBUG_STATUS_9_U___RWC QCSR_REG_RO +#define PHYA_ROBE_DEBUG_STATUS_9_U___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_9_U__ERROR_STATUS_UNMASKED___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_9_U__ERROR_STATUS_UNMASKED___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_9_U__ERROR_STATUS_UNMASKED___S 0 +#define PHYA_ROBE_DEBUG_STATUS_9_U___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_9_U___S 0 + +#define PHYA_ROBE_DEBUG_STATUS_10_L (0x004B0230) +#define PHYA_ROBE_DEBUG_STATUS_10_L___RWC QCSR_REG_RO +#define PHYA_ROBE_DEBUG_STATUS_10_L___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_10_L__BMMU1_LLM_AVAIL_BLK___POR 0x000 +#define PHYA_ROBE_DEBUG_STATUS_10_L__BMMU0_LLM_AVAIL_BLK___POR 0x000 +#define PHYA_ROBE_DEBUG_STATUS_10_L__BMMU1_LLM_AVAIL_BLK___M 0x03FF0000 +#define PHYA_ROBE_DEBUG_STATUS_10_L__BMMU1_LLM_AVAIL_BLK___S 16 +#define PHYA_ROBE_DEBUG_STATUS_10_L__BMMU0_LLM_AVAIL_BLK___M 0x000003FF +#define PHYA_ROBE_DEBUG_STATUS_10_L__BMMU0_LLM_AVAIL_BLK___S 0 +#define PHYA_ROBE_DEBUG_STATUS_10_L___M 0x03FF03FF +#define PHYA_ROBE_DEBUG_STATUS_10_L___S 0 + +#define PHYA_ROBE_DEBUG_STATUS_10_U (0x004B0234) +#define PHYA_ROBE_DEBUG_STATUS_10_U___RWC QCSR_REG_RO +#define PHYA_ROBE_DEBUG_STATUS_10_U___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_10_U__BMMU1_MIN_AVAIL_BLK___POR 0x000 +#define PHYA_ROBE_DEBUG_STATUS_10_U__BMMU0_MIN_AVAIL_BLK___POR 0x000 +#define PHYA_ROBE_DEBUG_STATUS_10_U__BMMU1_MIN_AVAIL_BLK___M 0x03FF0000 +#define PHYA_ROBE_DEBUG_STATUS_10_U__BMMU1_MIN_AVAIL_BLK___S 16 +#define PHYA_ROBE_DEBUG_STATUS_10_U__BMMU0_MIN_AVAIL_BLK___M 0x000003FF +#define PHYA_ROBE_DEBUG_STATUS_10_U__BMMU0_MIN_AVAIL_BLK___S 0 +#define PHYA_ROBE_DEBUG_STATUS_10_U___M 0x03FF03FF +#define PHYA_ROBE_DEBUG_STATUS_10_U___S 0 + +#define PHYA_ROBE_DEBUG_STATUS_11_L (0x004B0238) +#define PHYA_ROBE_DEBUG_STATUS_11_L___RWC QCSR_REG_RO +#define PHYA_ROBE_DEBUG_STATUS_11_L___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_11_L__PKT_DATA_START_COUNT_11N___POR 0x0000 +#define PHYA_ROBE_DEBUG_STATUS_11_L__PKT_START_COUNT___POR 0x0000 +#define PHYA_ROBE_DEBUG_STATUS_11_L__PKT_DATA_START_COUNT_11N___M 0xFFFF0000 +#define PHYA_ROBE_DEBUG_STATUS_11_L__PKT_DATA_START_COUNT_11N___S 16 +#define PHYA_ROBE_DEBUG_STATUS_11_L__PKT_START_COUNT___M 0x0000FFFF +#define PHYA_ROBE_DEBUG_STATUS_11_L__PKT_START_COUNT___S 0 +#define PHYA_ROBE_DEBUG_STATUS_11_L___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_11_L___S 0 + +#define PHYA_ROBE_DEBUG_STATUS_11_U (0x004B023C) +#define PHYA_ROBE_DEBUG_STATUS_11_U___RWC QCSR_REG_RO +#define PHYA_ROBE_DEBUG_STATUS_11_U___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_11_U__PKT_DATA_START_COUNT_11AX___POR 0x0000 +#define PHYA_ROBE_DEBUG_STATUS_11_U__PKT_DATA_START_COUNT_11AC___POR 0x0000 +#define PHYA_ROBE_DEBUG_STATUS_11_U__PKT_DATA_START_COUNT_11AX___M 0xFFFF0000 +#define PHYA_ROBE_DEBUG_STATUS_11_U__PKT_DATA_START_COUNT_11AX___S 16 +#define PHYA_ROBE_DEBUG_STATUS_11_U__PKT_DATA_START_COUNT_11AC___M 0x0000FFFF +#define PHYA_ROBE_DEBUG_STATUS_11_U__PKT_DATA_START_COUNT_11AC___S 0 +#define PHYA_ROBE_DEBUG_STATUS_11_U___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_11_U___S 0 + +#define PHYA_ROBE_DEBUG_STATUS_12_L (0x004B0240) +#define PHYA_ROBE_DEBUG_STATUS_12_L___RWC QCSR_REG_RO +#define PHYA_ROBE_DEBUG_STATUS_12_L___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_12_L__SU_DECODED_CW_COUNT___POR 0x0000 +#define PHYA_ROBE_DEBUG_STATUS_12_L__RU_START_COUNT___POR 0x0000 +#define PHYA_ROBE_DEBUG_STATUS_12_L__SU_DECODED_CW_COUNT___M 0xFFFF0000 +#define PHYA_ROBE_DEBUG_STATUS_12_L__SU_DECODED_CW_COUNT___S 16 +#define PHYA_ROBE_DEBUG_STATUS_12_L__RU_START_COUNT___M 0x0000FFFF +#define PHYA_ROBE_DEBUG_STATUS_12_L__RU_START_COUNT___S 0 +#define PHYA_ROBE_DEBUG_STATUS_12_L___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_12_L___S 0 + +#define PHYA_ROBE_DEBUG_STATUS_13_L (0x004B0248) +#define PHYA_ROBE_DEBUG_STATUS_13_L___RWC QCSR_REG_RO +#define PHYA_ROBE_DEBUG_STATUS_13_L___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_13_L__STATUS_SPARE_0___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_13_L__STATUS_SPARE_0___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_13_L__STATUS_SPARE_0___S 0 +#define PHYA_ROBE_DEBUG_STATUS_13_L___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_13_L___S 0 + +#define PHYA_ROBE_DEBUG_STATUS_13_U (0x004B024C) +#define PHYA_ROBE_DEBUG_STATUS_13_U___RWC QCSR_REG_RO +#define PHYA_ROBE_DEBUG_STATUS_13_U___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_13_U__STATUS_SPARE_1___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_13_U__STATUS_SPARE_1___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_13_U__STATUS_SPARE_1___S 0 +#define PHYA_ROBE_DEBUG_STATUS_13_U___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_13_U___S 0 + +#define PHYA_ROBE_PUBLIC_SPARE_L (0x004B0250) +#define PHYA_ROBE_PUBLIC_SPARE_L___RWC QCSR_REG_RW +#define PHYA_ROBE_PUBLIC_SPARE_L___POR 0x00000000 +#define PHYA_ROBE_PUBLIC_SPARE_L__ROBE_PUBLIC_SPARE_0___POR 0x00000000 +#define PHYA_ROBE_PUBLIC_SPARE_L__ROBE_PUBLIC_SPARE_0___M 0xFFFFFFFF +#define PHYA_ROBE_PUBLIC_SPARE_L__ROBE_PUBLIC_SPARE_0___S 0 +#define PHYA_ROBE_PUBLIC_SPARE_L___M 0xFFFFFFFF +#define PHYA_ROBE_PUBLIC_SPARE_L___S 0 + +#define PHYA_ROBE_PUBLIC_SPARE_U (0x004B0254) +#define PHYA_ROBE_PUBLIC_SPARE_U___RWC QCSR_REG_RW +#define PHYA_ROBE_PUBLIC_SPARE_U___POR 0x00000000 +#define PHYA_ROBE_PUBLIC_SPARE_U__ROBE_PUBLIC_SPARE_1___POR 0x00000000 +#define PHYA_ROBE_PUBLIC_SPARE_U__ROBE_PUBLIC_SPARE_1___M 0xFFFFFFFF +#define PHYA_ROBE_PUBLIC_SPARE_U__ROBE_PUBLIC_SPARE_1___S 0 +#define PHYA_ROBE_PUBLIC_SPARE_U___M 0xFFFFFFFF +#define PHYA_ROBE_PUBLIC_SPARE_U___S 0 + +#define PHYA_ROBE_GEN_CONTROL_0_L (0x004B0258) +#define PHYA_ROBE_GEN_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_ROBE_GEN_CONTROL_0_L___POR 0x00000004 +#define PHYA_ROBE_GEN_CONTROL_0_L__DISABLE_LDPC___POR 0x0 +#define PHYA_ROBE_GEN_CONTROL_0_L__DISABLE_UCS___POR 0x0 +#define PHYA_ROBE_GEN_CONTROL_0_L__DISABLE_11AX___POR 0x0 +#define PHYA_ROBE_GEN_CONTROL_0_L__DYN_PRI_CHN___POR 0x4 +#define PHYA_ROBE_GEN_CONTROL_0_L__DISABLE_LDPC___M 0x01000000 +#define PHYA_ROBE_GEN_CONTROL_0_L__DISABLE_LDPC___S 24 +#define PHYA_ROBE_GEN_CONTROL_0_L__DISABLE_UCS___M 0x00010000 +#define PHYA_ROBE_GEN_CONTROL_0_L__DISABLE_UCS___S 16 +#define PHYA_ROBE_GEN_CONTROL_0_L__DISABLE_11AX___M 0x00000100 +#define PHYA_ROBE_GEN_CONTROL_0_L__DISABLE_11AX___S 8 +#define PHYA_ROBE_GEN_CONTROL_0_L__DYN_PRI_CHN___M 0x00000007 +#define PHYA_ROBE_GEN_CONTROL_0_L__DYN_PRI_CHN___S 0 +#define PHYA_ROBE_GEN_CONTROL_0_L___M 0x01010107 +#define PHYA_ROBE_GEN_CONTROL_0_L___S 0 + +#define PHYA_ROBE_GEN_CONTROL_0_U (0x004B025C) +#define PHYA_ROBE_GEN_CONTROL_0_U___RWC QCSR_REG_RW +#define PHYA_ROBE_GEN_CONTROL_0_U___POR 0x00000000 +#define PHYA_ROBE_GEN_CONTROL_0_U__EN_VHTSIGB_CRC_CHK_SU___POR 0x0 +#define PHYA_ROBE_GEN_CONTROL_0_U__EN_VHTSIGB_CRC_CHK_MU___POR 0x0 +#define PHYA_ROBE_GEN_CONTROL_0_U__EN_RLSIG_REL_CHK___POR 0x0 +#define PHYA_ROBE_GEN_CONTROL_0_U__EN_LSIG_REL_CHK___POR 0x0 +#define PHYA_ROBE_GEN_CONTROL_0_U__EN_VHTSIGB_CRC_CHK_SU___M 0x01000000 +#define PHYA_ROBE_GEN_CONTROL_0_U__EN_VHTSIGB_CRC_CHK_SU___S 24 +#define PHYA_ROBE_GEN_CONTROL_0_U__EN_VHTSIGB_CRC_CHK_MU___M 0x00010000 +#define PHYA_ROBE_GEN_CONTROL_0_U__EN_VHTSIGB_CRC_CHK_MU___S 16 +#define PHYA_ROBE_GEN_CONTROL_0_U__EN_RLSIG_REL_CHK___M 0x00000100 +#define PHYA_ROBE_GEN_CONTROL_0_U__EN_RLSIG_REL_CHK___S 8 +#define PHYA_ROBE_GEN_CONTROL_0_U__EN_LSIG_REL_CHK___M 0x00000001 +#define PHYA_ROBE_GEN_CONTROL_0_U__EN_LSIG_REL_CHK___S 0 +#define PHYA_ROBE_GEN_CONTROL_0_U___M 0x01010101 +#define PHYA_ROBE_GEN_CONTROL_0_U___S 0 + +#define PHYA_ROBE_GEN_CONTROL_1_L (0x004B0260) +#define PHYA_ROBE_GEN_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_ROBE_GEN_CONTROL_1_L___POR 0x01020100 +#define PHYA_ROBE_GEN_CONTROL_1_L__LDPC_SU_POWER_OPT_EN___POR 0x1 +#define PHYA_ROBE_GEN_CONTROL_1_L__LDPC_PKT_END_ITR_CTRL___POR 0x2 +#define PHYA_ROBE_GEN_CONTROL_1_L__SRVC_FLD_CTRL___POR 0x1 +#define PHYA_ROBE_GEN_CONTROL_1_L__EN_NON_HE_FLUSH_INPUT___POR 0x0 +#define PHYA_ROBE_GEN_CONTROL_1_L__LDPC_SU_POWER_OPT_EN___M 0x01000000 +#define PHYA_ROBE_GEN_CONTROL_1_L__LDPC_SU_POWER_OPT_EN___S 24 +#define PHYA_ROBE_GEN_CONTROL_1_L__LDPC_PKT_END_ITR_CTRL___M 0x00030000 +#define PHYA_ROBE_GEN_CONTROL_1_L__LDPC_PKT_END_ITR_CTRL___S 16 +#define PHYA_ROBE_GEN_CONTROL_1_L__SRVC_FLD_CTRL___M 0x00000300 +#define PHYA_ROBE_GEN_CONTROL_1_L__SRVC_FLD_CTRL___S 8 +#define PHYA_ROBE_GEN_CONTROL_1_L__EN_NON_HE_FLUSH_INPUT___M 0x00000001 +#define PHYA_ROBE_GEN_CONTROL_1_L__EN_NON_HE_FLUSH_INPUT___S 0 +#define PHYA_ROBE_GEN_CONTROL_1_L___M 0x01030301 +#define PHYA_ROBE_GEN_CONTROL_1_L___S 0 + +#define PHYA_ROBE_ROBE_HW_CONTROL_0_L (0x004B0268) +#define PHYA_ROBE_ROBE_HW_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_ROBE_ROBE_HW_CONTROL_0_L___POR 0x01010101 +#define PHYA_ROBE_ROBE_HW_CONTROL_0_L__EN_SCHD_PU_CALC___POR 0x1 +#define PHYA_ROBE_ROBE_HW_CONTROL_0_L__ENABLE_LDPC_FIXED_LATENCY___POR 0x1 +#define PHYA_ROBE_ROBE_HW_CONTROL_0_L__ENABLE_LDPC_DEC_OVERLAP___POR 0x1 +#define PHYA_ROBE_ROBE_HW_CONTROL_0_L__EN_ROBE_USER_COUNTERS___POR 0x1 +#define PHYA_ROBE_ROBE_HW_CONTROL_0_L__EN_SCHD_PU_CALC___M 0x01000000 +#define PHYA_ROBE_ROBE_HW_CONTROL_0_L__EN_SCHD_PU_CALC___S 24 +#define PHYA_ROBE_ROBE_HW_CONTROL_0_L__ENABLE_LDPC_FIXED_LATENCY___M 0x00010000 +#define PHYA_ROBE_ROBE_HW_CONTROL_0_L__ENABLE_LDPC_FIXED_LATENCY___S 16 +#define PHYA_ROBE_ROBE_HW_CONTROL_0_L__ENABLE_LDPC_DEC_OVERLAP___M 0x00000100 +#define PHYA_ROBE_ROBE_HW_CONTROL_0_L__ENABLE_LDPC_DEC_OVERLAP___S 8 +#define PHYA_ROBE_ROBE_HW_CONTROL_0_L__EN_ROBE_USER_COUNTERS___M 0x00000001 +#define PHYA_ROBE_ROBE_HW_CONTROL_0_L__EN_ROBE_USER_COUNTERS___S 0 +#define PHYA_ROBE_ROBE_HW_CONTROL_0_L___M 0x01010101 +#define PHYA_ROBE_ROBE_HW_CONTROL_0_L___S 0 + +#define PHYA_ROBE_ROBE_HW_CONTROL_0_U (0x004B026C) +#define PHYA_ROBE_ROBE_HW_CONTROL_0_U___RWC QCSR_REG_RW +#define PHYA_ROBE_ROBE_HW_CONTROL_0_U___POR 0x010100FA +#define PHYA_ROBE_ROBE_HW_CONTROL_0_U__SCHD_COST_STORAGE_WEIGHT___POR 0x1 +#define PHYA_ROBE_ROBE_HW_CONTROL_0_U__SCHD_COST_RATE_WEIGHT___POR 0x1 +#define PHYA_ROBE_ROBE_HW_CONTROL_0_U__SCHD_PU_COST_THRESHOLD___POR 0x00FA +#define PHYA_ROBE_ROBE_HW_CONTROL_0_U__SCHD_COST_STORAGE_WEIGHT___M 0x0F000000 +#define PHYA_ROBE_ROBE_HW_CONTROL_0_U__SCHD_COST_STORAGE_WEIGHT___S 24 +#define PHYA_ROBE_ROBE_HW_CONTROL_0_U__SCHD_COST_RATE_WEIGHT___M 0x000F0000 +#define PHYA_ROBE_ROBE_HW_CONTROL_0_U__SCHD_COST_RATE_WEIGHT___S 16 +#define PHYA_ROBE_ROBE_HW_CONTROL_0_U__SCHD_PU_COST_THRESHOLD___M 0x0000FFFF +#define PHYA_ROBE_ROBE_HW_CONTROL_0_U__SCHD_PU_COST_THRESHOLD___S 0 +#define PHYA_ROBE_ROBE_HW_CONTROL_0_U___M 0x0F0FFFFF +#define PHYA_ROBE_ROBE_HW_CONTROL_0_U___S 0 + +#define PHYA_ROBE_ROBE_HW_CONTROL_1_L (0x004B0270) +#define PHYA_ROBE_ROBE_HW_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_ROBE_ROBE_HW_CONTROL_1_L___POR 0x02000100 +#define PHYA_ROBE_ROBE_HW_CONTROL_1_L__TRFC_FIFO_ALMOST_FULL_THRESHOLD___POR 0x2 +#define PHYA_ROBE_ROBE_HW_CONTROL_1_L__EN_BMMU_SELF_DROP___POR 0x0 +#define PHYA_ROBE_ROBE_HW_CONTROL_1_L__DISABLE_DEINT_BACKPRESSURE___POR 0x1 +#define PHYA_ROBE_ROBE_HW_CONTROL_1_L__DEINT_OVERFLOW_THR___POR 0x00 +#define PHYA_ROBE_ROBE_HW_CONTROL_1_L__TRFC_FIFO_ALMOST_FULL_THRESHOLD___M 0x03000000 +#define PHYA_ROBE_ROBE_HW_CONTROL_1_L__TRFC_FIFO_ALMOST_FULL_THRESHOLD___S 24 +#define PHYA_ROBE_ROBE_HW_CONTROL_1_L__EN_BMMU_SELF_DROP___M 0x00010000 +#define PHYA_ROBE_ROBE_HW_CONTROL_1_L__EN_BMMU_SELF_DROP___S 16 +#define PHYA_ROBE_ROBE_HW_CONTROL_1_L__DISABLE_DEINT_BACKPRESSURE___M 0x00000100 +#define PHYA_ROBE_ROBE_HW_CONTROL_1_L__DISABLE_DEINT_BACKPRESSURE___S 8 +#define PHYA_ROBE_ROBE_HW_CONTROL_1_L__DEINT_OVERFLOW_THR___M 0x0000003F +#define PHYA_ROBE_ROBE_HW_CONTROL_1_L__DEINT_OVERFLOW_THR___S 0 +#define PHYA_ROBE_ROBE_HW_CONTROL_1_L___M 0x0301013F +#define PHYA_ROBE_ROBE_HW_CONTROL_1_L___S 0 + +#define PHYA_ROBE_ROBE_HW_CONTROL_1_U (0x004B0274) +#define PHYA_ROBE_ROBE_HW_CONTROL_1_U___RWC QCSR_REG_RW +#define PHYA_ROBE_ROBE_HW_CONTROL_1_U___POR 0x00000000 +#define PHYA_ROBE_ROBE_HW_CONTROL_1_U__DISABLE_1SYM_PKT_PARAM___POR 0x0 +#define PHYA_ROBE_ROBE_HW_CONTROL_1_U__DISABLE_BW160_PKT_PARAM___POR 0x0 +#define PHYA_ROBE_ROBE_HW_CONTROL_1_U__EN_BMMU_DLT_FULL_COUNT___POR 0x0 +#define PHYA_ROBE_ROBE_HW_CONTROL_1_U__EN_ROBE_SELF_EOP___POR 0x0 +#define PHYA_ROBE_ROBE_HW_CONTROL_1_U__DISABLE_1SYM_PKT_PARAM___M 0x01000000 +#define PHYA_ROBE_ROBE_HW_CONTROL_1_U__DISABLE_1SYM_PKT_PARAM___S 24 +#define PHYA_ROBE_ROBE_HW_CONTROL_1_U__DISABLE_BW160_PKT_PARAM___M 0x00010000 +#define PHYA_ROBE_ROBE_HW_CONTROL_1_U__DISABLE_BW160_PKT_PARAM___S 16 +#define PHYA_ROBE_ROBE_HW_CONTROL_1_U__EN_BMMU_DLT_FULL_COUNT___M 0x00000100 +#define PHYA_ROBE_ROBE_HW_CONTROL_1_U__EN_BMMU_DLT_FULL_COUNT___S 8 +#define PHYA_ROBE_ROBE_HW_CONTROL_1_U__EN_ROBE_SELF_EOP___M 0x00000001 +#define PHYA_ROBE_ROBE_HW_CONTROL_1_U__EN_ROBE_SELF_EOP___S 0 +#define PHYA_ROBE_ROBE_HW_CONTROL_1_U___M 0x01010101 +#define PHYA_ROBE_ROBE_HW_CONTROL_1_U___S 0 + +#define PHYA_ROBE_ROBE_HW_CONTROL_2_L (0x004B0278) +#define PHYA_ROBE_ROBE_HW_CONTROL_2_L___RWC QCSR_REG_RW +#define PHYA_ROBE_ROBE_HW_CONTROL_2_L___POR 0x00000000 +#define PHYA_ROBE_ROBE_HW_CONTROL_2_L__DEINT_GEN_CTRL___POR 0x00000000 +#define PHYA_ROBE_ROBE_HW_CONTROL_2_L__DEINT_GEN_CTRL___M 0xFFFFFFFF +#define PHYA_ROBE_ROBE_HW_CONTROL_2_L__DEINT_GEN_CTRL___S 0 +#define PHYA_ROBE_ROBE_HW_CONTROL_2_L___M 0xFFFFFFFF +#define PHYA_ROBE_ROBE_HW_CONTROL_2_L___S 0 + +#define PHYA_ROBE_ROBE_HW_CONTROL_2_U (0x004B027C) +#define PHYA_ROBE_ROBE_HW_CONTROL_2_U___RWC QCSR_REG_RW +#define PHYA_ROBE_ROBE_HW_CONTROL_2_U___POR 0x00000000 +#define PHYA_ROBE_ROBE_HW_CONTROL_2_U__BMMU_GEN_CTRL___POR 0x00000000 +#define PHYA_ROBE_ROBE_HW_CONTROL_2_U__BMMU_GEN_CTRL___M 0xFFFFFFFF +#define PHYA_ROBE_ROBE_HW_CONTROL_2_U__BMMU_GEN_CTRL___S 0 +#define PHYA_ROBE_ROBE_HW_CONTROL_2_U___M 0xFFFFFFFF +#define PHYA_ROBE_ROBE_HW_CONTROL_2_U___S 0 + +#define PHYA_ROBE_ROBE_HW_CONTROL_3_L (0x004B0280) +#define PHYA_ROBE_ROBE_HW_CONTROL_3_L___RWC QCSR_REG_RW +#define PHYA_ROBE_ROBE_HW_CONTROL_3_L___POR 0x00000000 +#define PHYA_ROBE_ROBE_HW_CONTROL_3_L__SCHD_GEN_CTRL___POR 0x00000000 +#define PHYA_ROBE_ROBE_HW_CONTROL_3_L__SCHD_GEN_CTRL___M 0xFFFFFFFF +#define PHYA_ROBE_ROBE_HW_CONTROL_3_L__SCHD_GEN_CTRL___S 0 +#define PHYA_ROBE_ROBE_HW_CONTROL_3_L___M 0xFFFFFFFF +#define PHYA_ROBE_ROBE_HW_CONTROL_3_L___S 0 + +#define PHYA_ROBE_ROBE_HW_CONTROL_3_U (0x004B0284) +#define PHYA_ROBE_ROBE_HW_CONTROL_3_U___RWC QCSR_REG_RW +#define PHYA_ROBE_ROBE_HW_CONTROL_3_U___POR 0x00000000 +#define PHYA_ROBE_ROBE_HW_CONTROL_3_U__VIT_GEN_CTRL___POR 0x00000000 +#define PHYA_ROBE_ROBE_HW_CONTROL_3_U__VIT_GEN_CTRL___M 0xFFFFFFFF +#define PHYA_ROBE_ROBE_HW_CONTROL_3_U__VIT_GEN_CTRL___S 0 +#define PHYA_ROBE_ROBE_HW_CONTROL_3_U___M 0xFFFFFFFF +#define PHYA_ROBE_ROBE_HW_CONTROL_3_U___S 0 + +#define PHYA_ROBE_ROBE_HW_CONTROL_4_L (0x004B0288) +#define PHYA_ROBE_ROBE_HW_CONTROL_4_L___RWC QCSR_REG_RW +#define PHYA_ROBE_ROBE_HW_CONTROL_4_L___POR 0x00000000 +#define PHYA_ROBE_ROBE_HW_CONTROL_4_L__LDPC_GEN_CTRL___POR 0x00000000 +#define PHYA_ROBE_ROBE_HW_CONTROL_4_L__LDPC_GEN_CTRL___M 0xFFFFFFFF +#define PHYA_ROBE_ROBE_HW_CONTROL_4_L__LDPC_GEN_CTRL___S 0 +#define PHYA_ROBE_ROBE_HW_CONTROL_4_L___M 0xFFFFFFFF +#define PHYA_ROBE_ROBE_HW_CONTROL_4_L___S 0 + +#define PHYA_ROBE_ROBE_HW_CONTROL_4_U (0x004B028C) +#define PHYA_ROBE_ROBE_HW_CONTROL_4_U___RWC QCSR_REG_RW +#define PHYA_ROBE_ROBE_HW_CONTROL_4_U___POR 0x00000000 +#define PHYA_ROBE_ROBE_HW_CONTROL_4_U__TRFC_GEN_CTRL___POR 0x00000000 +#define PHYA_ROBE_ROBE_HW_CONTROL_4_U__TRFC_GEN_CTRL___M 0xFFFFFFFF +#define PHYA_ROBE_ROBE_HW_CONTROL_4_U__TRFC_GEN_CTRL___S 0 +#define PHYA_ROBE_ROBE_HW_CONTROL_4_U___M 0xFFFFFFFF +#define PHYA_ROBE_ROBE_HW_CONTROL_4_U___S 0 + +#define PHYA_ROBE_HE_STNDRD_0_L (0x004B0290) +#define PHYA_ROBE_HE_STNDRD_0_L___RWC QCSR_REG_RW +#define PHYA_ROBE_HE_STNDRD_0_L___POR 0x00180000 +#define PHYA_ROBE_HE_STNDRD_0_L__HESIGA_SU_BW_MASK_L32___POR 0x00180000 +#define PHYA_ROBE_HE_STNDRD_0_L__HESIGA_SU_BW_MASK_L32___M 0xFFFFFFFF +#define PHYA_ROBE_HE_STNDRD_0_L__HESIGA_SU_BW_MASK_L32___S 0 +#define PHYA_ROBE_HE_STNDRD_0_L___M 0xFFFFFFFF +#define PHYA_ROBE_HE_STNDRD_0_L___S 0 + +#define PHYA_ROBE_HE_STNDRD_0_U (0x004B0294) +#define PHYA_ROBE_HE_STNDRD_0_U___RWC QCSR_REG_RW +#define PHYA_ROBE_HE_STNDRD_0_U___POR 0x00000000 +#define PHYA_ROBE_HE_STNDRD_0_U__HESIGA_SU_BW_MASK_U32___POR 0x00000000 +#define PHYA_ROBE_HE_STNDRD_0_U__HESIGA_SU_BW_MASK_U32___M 0xFFFFFFFF +#define PHYA_ROBE_HE_STNDRD_0_U__HESIGA_SU_BW_MASK_U32___S 0 +#define PHYA_ROBE_HE_STNDRD_0_U___M 0xFFFFFFFF +#define PHYA_ROBE_HE_STNDRD_0_U___S 0 + +#define PHYA_ROBE_HE_STNDRD_1_L (0x004B0298) +#define PHYA_ROBE_HE_STNDRD_1_L___RWC QCSR_REG_RW +#define PHYA_ROBE_HE_STNDRD_1_L___POR 0x00180000 +#define PHYA_ROBE_HE_STNDRD_1_L__HESIGA_EXT_BW_MASK_L32___POR 0x00180000 +#define PHYA_ROBE_HE_STNDRD_1_L__HESIGA_EXT_BW_MASK_L32___M 0xFFFFFFFF +#define PHYA_ROBE_HE_STNDRD_1_L__HESIGA_EXT_BW_MASK_L32___S 0 +#define PHYA_ROBE_HE_STNDRD_1_L___M 0xFFFFFFFF +#define PHYA_ROBE_HE_STNDRD_1_L___S 0 + +#define PHYA_ROBE_HE_STNDRD_1_U (0x004B029C) +#define PHYA_ROBE_HE_STNDRD_1_U___RWC QCSR_REG_RW +#define PHYA_ROBE_HE_STNDRD_1_U___POR 0x00000000 +#define PHYA_ROBE_HE_STNDRD_1_U__HESIGA_EXT_BW_MASK_U32___POR 0x00000000 +#define PHYA_ROBE_HE_STNDRD_1_U__HESIGA_EXT_BW_MASK_U32___M 0xFFFFFFFF +#define PHYA_ROBE_HE_STNDRD_1_U__HESIGA_EXT_BW_MASK_U32___S 0 +#define PHYA_ROBE_HE_STNDRD_1_U___M 0xFFFFFFFF +#define PHYA_ROBE_HE_STNDRD_1_U___S 0 + +#define PHYA_ROBE_HE_STNDRD_2_L (0x004B02A0) +#define PHYA_ROBE_HE_STNDRD_2_L___RWC QCSR_REG_RW +#define PHYA_ROBE_HE_STNDRD_2_L___POR 0x00038000 +#define PHYA_ROBE_HE_STNDRD_2_L__HESIGA_MU_BW_MASK_L32___POR 0x00038000 +#define PHYA_ROBE_HE_STNDRD_2_L__HESIGA_MU_BW_MASK_L32___M 0xFFFFFFFF +#define PHYA_ROBE_HE_STNDRD_2_L__HESIGA_MU_BW_MASK_L32___S 0 +#define PHYA_ROBE_HE_STNDRD_2_L___M 0xFFFFFFFF +#define PHYA_ROBE_HE_STNDRD_2_L___S 0 + +#define PHYA_ROBE_HE_STNDRD_2_U (0x004B02A4) +#define PHYA_ROBE_HE_STNDRD_2_U___RWC QCSR_REG_RW +#define PHYA_ROBE_HE_STNDRD_2_U___POR 0x00000000 +#define PHYA_ROBE_HE_STNDRD_2_U__HESIGA_MU_BW_MASK_U32___POR 0x00000000 +#define PHYA_ROBE_HE_STNDRD_2_U__HESIGA_MU_BW_MASK_U32___M 0xFFFFFFFF +#define PHYA_ROBE_HE_STNDRD_2_U__HESIGA_MU_BW_MASK_U32___S 0 +#define PHYA_ROBE_HE_STNDRD_2_U___M 0xFFFFFFFF +#define PHYA_ROBE_HE_STNDRD_2_U___S 0 + +#define PHYA_ROBE_HE_STNDRD_3_L (0x004B02A8) +#define PHYA_ROBE_HE_STNDRD_3_L___RWC QCSR_REG_RW +#define PHYA_ROBE_HE_STNDRD_3_L___POR 0x00180000 +#define PHYA_ROBE_HE_STNDRD_3_L__HESIGA_SU_BW_160_VAL_L32___POR 0x00180000 +#define PHYA_ROBE_HE_STNDRD_3_L__HESIGA_SU_BW_160_VAL_L32___M 0xFFFFFFFF +#define PHYA_ROBE_HE_STNDRD_3_L__HESIGA_SU_BW_160_VAL_L32___S 0 +#define PHYA_ROBE_HE_STNDRD_3_L___M 0xFFFFFFFF +#define PHYA_ROBE_HE_STNDRD_3_L___S 0 + +#define PHYA_ROBE_HE_STNDRD_3_U (0x004B02AC) +#define PHYA_ROBE_HE_STNDRD_3_U___RWC QCSR_REG_RW +#define PHYA_ROBE_HE_STNDRD_3_U___POR 0x00000000 +#define PHYA_ROBE_HE_STNDRD_3_U__HESIGA_SU_BW_160_VAL_U32___POR 0x00000000 +#define PHYA_ROBE_HE_STNDRD_3_U__HESIGA_SU_BW_160_VAL_U32___M 0xFFFFFFFF +#define PHYA_ROBE_HE_STNDRD_3_U__HESIGA_SU_BW_160_VAL_U32___S 0 +#define PHYA_ROBE_HE_STNDRD_3_U___M 0xFFFFFFFF +#define PHYA_ROBE_HE_STNDRD_3_U___S 0 + +#define PHYA_ROBE_HE_STNDRD_4_L (0x004B02B0) +#define PHYA_ROBE_HE_STNDRD_4_L___RWC QCSR_REG_RW +#define PHYA_ROBE_HE_STNDRD_4_L___POR 0x00180000 +#define PHYA_ROBE_HE_STNDRD_4_L__HESIGA_EXT_BW_160_VAL_L32___POR 0x00180000 +#define PHYA_ROBE_HE_STNDRD_4_L__HESIGA_EXT_BW_160_VAL_L32___M 0xFFFFFFFF +#define PHYA_ROBE_HE_STNDRD_4_L__HESIGA_EXT_BW_160_VAL_L32___S 0 +#define PHYA_ROBE_HE_STNDRD_4_L___M 0xFFFFFFFF +#define PHYA_ROBE_HE_STNDRD_4_L___S 0 + +#define PHYA_ROBE_HE_STNDRD_4_U (0x004B02B4) +#define PHYA_ROBE_HE_STNDRD_4_U___RWC QCSR_REG_RW +#define PHYA_ROBE_HE_STNDRD_4_U___POR 0x00000000 +#define PHYA_ROBE_HE_STNDRD_4_U__HESIGA_EXT_BW_160_VAL_U32___POR 0x00000000 +#define PHYA_ROBE_HE_STNDRD_4_U__HESIGA_EXT_BW_160_VAL_U32___M 0xFFFFFFFF +#define PHYA_ROBE_HE_STNDRD_4_U__HESIGA_EXT_BW_160_VAL_U32___S 0 +#define PHYA_ROBE_HE_STNDRD_4_U___M 0xFFFFFFFF +#define PHYA_ROBE_HE_STNDRD_4_U___S 0 + +#define PHYA_ROBE_HE_STNDRD_5_L (0x004B02B8) +#define PHYA_ROBE_HE_STNDRD_5_L___RWC QCSR_REG_RW +#define PHYA_ROBE_HE_STNDRD_5_L___POR 0x00018000 +#define PHYA_ROBE_HE_STNDRD_5_L__HESIGA_MU_BW_160_VAL_L32___POR 0x00018000 +#define PHYA_ROBE_HE_STNDRD_5_L__HESIGA_MU_BW_160_VAL_L32___M 0xFFFFFFFF +#define PHYA_ROBE_HE_STNDRD_5_L__HESIGA_MU_BW_160_VAL_L32___S 0 +#define PHYA_ROBE_HE_STNDRD_5_L___M 0xFFFFFFFF +#define PHYA_ROBE_HE_STNDRD_5_L___S 0 + +#define PHYA_ROBE_HE_STNDRD_5_U (0x004B02BC) +#define PHYA_ROBE_HE_STNDRD_5_U___RWC QCSR_REG_RW +#define PHYA_ROBE_HE_STNDRD_5_U___POR 0x00000000 +#define PHYA_ROBE_HE_STNDRD_5_U__HESIGA_MU_BW_160_VAL_U32___POR 0x00000000 +#define PHYA_ROBE_HE_STNDRD_5_U__HESIGA_MU_BW_160_VAL_U32___M 0xFFFFFFFF +#define PHYA_ROBE_HE_STNDRD_5_U__HESIGA_MU_BW_160_VAL_U32___S 0 +#define PHYA_ROBE_HE_STNDRD_5_U___M 0xFFFFFFFF +#define PHYA_ROBE_HE_STNDRD_5_U___S 0 + +#define PHYA_ROBE_NUM_HESIGB_THR_0_L (0x004B02C0) +#define PHYA_ROBE_NUM_HESIGB_THR_0_L___RWC QCSR_REG_RW +#define PHYA_ROBE_NUM_HESIGB_THR_0_L___POR 0x04020200 +#define PHYA_ROBE_NUM_HESIGB_THR_0_L__NUM_HESIGB_THR_MCS3_20M___POR 0x04 +#define PHYA_ROBE_NUM_HESIGB_THR_0_L__NUM_HESIGB_THR_MCS2_20M___POR 0x02 +#define PHYA_ROBE_NUM_HESIGB_THR_0_L__NUM_HESIGB_THR_MCS1_20M___POR 0x02 +#define PHYA_ROBE_NUM_HESIGB_THR_0_L__NUM_HESIGB_THR_MCS0_20M___POR 0x00 +#define PHYA_ROBE_NUM_HESIGB_THR_0_L__NUM_HESIGB_THR_MCS3_20M___M 0xFF000000 +#define PHYA_ROBE_NUM_HESIGB_THR_0_L__NUM_HESIGB_THR_MCS3_20M___S 24 +#define PHYA_ROBE_NUM_HESIGB_THR_0_L__NUM_HESIGB_THR_MCS2_20M___M 0x00FF0000 +#define PHYA_ROBE_NUM_HESIGB_THR_0_L__NUM_HESIGB_THR_MCS2_20M___S 16 +#define PHYA_ROBE_NUM_HESIGB_THR_0_L__NUM_HESIGB_THR_MCS1_20M___M 0x0000FF00 +#define PHYA_ROBE_NUM_HESIGB_THR_0_L__NUM_HESIGB_THR_MCS1_20M___S 8 +#define PHYA_ROBE_NUM_HESIGB_THR_0_L__NUM_HESIGB_THR_MCS0_20M___M 0x000000FF +#define PHYA_ROBE_NUM_HESIGB_THR_0_L__NUM_HESIGB_THR_MCS0_20M___S 0 +#define PHYA_ROBE_NUM_HESIGB_THR_0_L___M 0xFFFFFFFF +#define PHYA_ROBE_NUM_HESIGB_THR_0_L___S 0 + +#define PHYA_ROBE_NUM_HESIGB_THR_0_U (0x004B02C4) +#define PHYA_ROBE_NUM_HESIGB_THR_0_U___RWC QCSR_REG_RW +#define PHYA_ROBE_NUM_HESIGB_THR_0_U___POR 0x01000F06 +#define PHYA_ROBE_NUM_HESIGB_THR_0_U__NUM_HESIGB_THR_ENA_DLMUMIMO___POR 0x1 +#define PHYA_ROBE_NUM_HESIGB_THR_0_U__NUM_HESIGB_THR_DCM_MCS0_20M___POR 0x00 +#define PHYA_ROBE_NUM_HESIGB_THR_0_U__NUM_HESIGB_THR_MCS5_20M___POR 0x0F +#define PHYA_ROBE_NUM_HESIGB_THR_0_U__NUM_HESIGB_THR_MCS4_20M___POR 0x06 +#define PHYA_ROBE_NUM_HESIGB_THR_0_U__NUM_HESIGB_THR_ENA_DLMUMIMO___M 0x01000000 +#define PHYA_ROBE_NUM_HESIGB_THR_0_U__NUM_HESIGB_THR_ENA_DLMUMIMO___S 24 +#define PHYA_ROBE_NUM_HESIGB_THR_0_U__NUM_HESIGB_THR_DCM_MCS0_20M___M 0x00FF0000 +#define PHYA_ROBE_NUM_HESIGB_THR_0_U__NUM_HESIGB_THR_DCM_MCS0_20M___S 16 +#define PHYA_ROBE_NUM_HESIGB_THR_0_U__NUM_HESIGB_THR_MCS5_20M___M 0x0000FF00 +#define PHYA_ROBE_NUM_HESIGB_THR_0_U__NUM_HESIGB_THR_MCS5_20M___S 8 +#define PHYA_ROBE_NUM_HESIGB_THR_0_U__NUM_HESIGB_THR_MCS4_20M___M 0x000000FF +#define PHYA_ROBE_NUM_HESIGB_THR_0_U__NUM_HESIGB_THR_MCS4_20M___S 0 +#define PHYA_ROBE_NUM_HESIGB_THR_0_U___M 0x01FFFFFF +#define PHYA_ROBE_NUM_HESIGB_THR_0_U___S 0 + +#define PHYA_ROBE_NUM_HESIGB_THR_1_L (0x004B02C8) +#define PHYA_ROBE_NUM_HESIGB_THR_1_L___RWC QCSR_REG_RW +#define PHYA_ROBE_NUM_HESIGB_THR_1_L___POR 0x0F040400 +#define PHYA_ROBE_NUM_HESIGB_THR_1_L__NUM_HESIGB_THR_MCS3_40_80M___POR 0x0F +#define PHYA_ROBE_NUM_HESIGB_THR_1_L__NUM_HESIGB_THR_MCS2_40_80M___POR 0x04 +#define PHYA_ROBE_NUM_HESIGB_THR_1_L__NUM_HESIGB_THR_MCS1_40_80M___POR 0x04 +#define PHYA_ROBE_NUM_HESIGB_THR_1_L__NUM_HESIGB_THR_MCS0_40_80M___POR 0x00 +#define PHYA_ROBE_NUM_HESIGB_THR_1_L__NUM_HESIGB_THR_MCS3_40_80M___M 0xFF000000 +#define PHYA_ROBE_NUM_HESIGB_THR_1_L__NUM_HESIGB_THR_MCS3_40_80M___S 24 +#define PHYA_ROBE_NUM_HESIGB_THR_1_L__NUM_HESIGB_THR_MCS2_40_80M___M 0x00FF0000 +#define PHYA_ROBE_NUM_HESIGB_THR_1_L__NUM_HESIGB_THR_MCS2_40_80M___S 16 +#define PHYA_ROBE_NUM_HESIGB_THR_1_L__NUM_HESIGB_THR_MCS1_40_80M___M 0x0000FF00 +#define PHYA_ROBE_NUM_HESIGB_THR_1_L__NUM_HESIGB_THR_MCS1_40_80M___S 8 +#define PHYA_ROBE_NUM_HESIGB_THR_1_L__NUM_HESIGB_THR_MCS0_40_80M___M 0x000000FF +#define PHYA_ROBE_NUM_HESIGB_THR_1_L__NUM_HESIGB_THR_MCS0_40_80M___S 0 +#define PHYA_ROBE_NUM_HESIGB_THR_1_L___M 0xFFFFFFFF +#define PHYA_ROBE_NUM_HESIGB_THR_1_L___S 0 + +#define PHYA_ROBE_NUM_HESIGB_THR_1_U (0x004B02CC) +#define PHYA_ROBE_NUM_HESIGB_THR_1_U___RWC QCSR_REG_RW +#define PHYA_ROBE_NUM_HESIGB_THR_1_U___POR 0x01000F0F +#define PHYA_ROBE_NUM_HESIGB_THR_1_U__NUM_HESIGB_THR_ENA_DLOFDMA___POR 0x1 +#define PHYA_ROBE_NUM_HESIGB_THR_1_U__NUM_HESIGB_THR_DCM_MCS0_40_80M___POR 0x00 +#define PHYA_ROBE_NUM_HESIGB_THR_1_U__NUM_HESIGB_THR_MCS5_40_80M___POR 0x0F +#define PHYA_ROBE_NUM_HESIGB_THR_1_U__NUM_HESIGB_THR_MCS4_40_80M___POR 0x0F +#define PHYA_ROBE_NUM_HESIGB_THR_1_U__NUM_HESIGB_THR_ENA_DLOFDMA___M 0x01000000 +#define PHYA_ROBE_NUM_HESIGB_THR_1_U__NUM_HESIGB_THR_ENA_DLOFDMA___S 24 +#define PHYA_ROBE_NUM_HESIGB_THR_1_U__NUM_HESIGB_THR_DCM_MCS0_40_80M___M 0x00FF0000 +#define PHYA_ROBE_NUM_HESIGB_THR_1_U__NUM_HESIGB_THR_DCM_MCS0_40_80M___S 16 +#define PHYA_ROBE_NUM_HESIGB_THR_1_U__NUM_HESIGB_THR_MCS5_40_80M___M 0x0000FF00 +#define PHYA_ROBE_NUM_HESIGB_THR_1_U__NUM_HESIGB_THR_MCS5_40_80M___S 8 +#define PHYA_ROBE_NUM_HESIGB_THR_1_U__NUM_HESIGB_THR_MCS4_40_80M___M 0x000000FF +#define PHYA_ROBE_NUM_HESIGB_THR_1_U__NUM_HESIGB_THR_MCS4_40_80M___S 0 +#define PHYA_ROBE_NUM_HESIGB_THR_1_U___M 0x01FFFFFF +#define PHYA_ROBE_NUM_HESIGB_THR_1_U___S 0 + +#define PHYA_ROBE_CG_CONTROL_0_L (0x004B02D0) +#define PHYA_ROBE_CG_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_ROBE_CG_CONTROL_0_L___POR 0x00000000 +#define PHYA_ROBE_CG_CONTROL_0_L__DYN_CGC_DISABLE_LDPC___POR 0x0 +#define PHYA_ROBE_CG_CONTROL_0_L__DYN_CGC_DISABLE_VIT___POR 0x0 +#define PHYA_ROBE_CG_CONTROL_0_L__DYN_CGC_DISABLE_DEINT___POR 0x0 +#define PHYA_ROBE_CG_CONTROL_0_L__STATIC_CGC_EN___POR 0x0 +#define PHYA_ROBE_CG_CONTROL_0_L__DYN_CGC_DISABLE_LDPC___M 0x01000000 +#define PHYA_ROBE_CG_CONTROL_0_L__DYN_CGC_DISABLE_LDPC___S 24 +#define PHYA_ROBE_CG_CONTROL_0_L__DYN_CGC_DISABLE_VIT___M 0x00010000 +#define PHYA_ROBE_CG_CONTROL_0_L__DYN_CGC_DISABLE_VIT___S 16 +#define PHYA_ROBE_CG_CONTROL_0_L__DYN_CGC_DISABLE_DEINT___M 0x00000100 +#define PHYA_ROBE_CG_CONTROL_0_L__DYN_CGC_DISABLE_DEINT___S 8 +#define PHYA_ROBE_CG_CONTROL_0_L__STATIC_CGC_EN___M 0x00000001 +#define PHYA_ROBE_CG_CONTROL_0_L__STATIC_CGC_EN___S 0 +#define PHYA_ROBE_CG_CONTROL_0_L___M 0x01010101 +#define PHYA_ROBE_CG_CONTROL_0_L___S 0 + +#define PHYA_ROBE_CG_CONTROL_0_U (0x004B02D4) +#define PHYA_ROBE_CG_CONTROL_0_U___RWC QCSR_REG_RW +#define PHYA_ROBE_CG_CONTROL_0_U___POR 0x00000000 +#define PHYA_ROBE_CG_CONTROL_0_U__DYN_CGC_DISABLE_SCHD___POR 0x0 +#define PHYA_ROBE_CG_CONTROL_0_U__DYN_CGC_DISABLE_CTRL___POR 0x0 +#define PHYA_ROBE_CG_CONTROL_0_U__DYN_CGC_DISABLE_TRFC___POR 0x0 +#define PHYA_ROBE_CG_CONTROL_0_U__DYN_CGC_DISABLE_BMMU___POR 0x0 +#define PHYA_ROBE_CG_CONTROL_0_U__DYN_CGC_DISABLE_SCHD___M 0x01000000 +#define PHYA_ROBE_CG_CONTROL_0_U__DYN_CGC_DISABLE_SCHD___S 24 +#define PHYA_ROBE_CG_CONTROL_0_U__DYN_CGC_DISABLE_CTRL___M 0x00010000 +#define PHYA_ROBE_CG_CONTROL_0_U__DYN_CGC_DISABLE_CTRL___S 16 +#define PHYA_ROBE_CG_CONTROL_0_U__DYN_CGC_DISABLE_TRFC___M 0x00000100 +#define PHYA_ROBE_CG_CONTROL_0_U__DYN_CGC_DISABLE_TRFC___S 8 +#define PHYA_ROBE_CG_CONTROL_0_U__DYN_CGC_DISABLE_BMMU___M 0x00000001 +#define PHYA_ROBE_CG_CONTROL_0_U__DYN_CGC_DISABLE_BMMU___S 0 +#define PHYA_ROBE_CG_CONTROL_0_U___M 0x01010101 +#define PHYA_ROBE_CG_CONTROL_0_U___S 0 + +#define PHYA_ROBE_CG_CONTROL_1_L (0x004B02D8) +#define PHYA_ROBE_CG_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_ROBE_CG_CONTROL_1_L___POR 0x00000000 +#define PHYA_ROBE_CG_CONTROL_1_L__DYN_CGC_DISABLE_ALL___POR 0x0 +#define PHYA_ROBE_CG_CONTROL_1_L__DYN_CGC_DISABLE_CSR___POR 0x0 +#define PHYA_ROBE_CG_CONTROL_1_L__DYN_CGC_DISABLE_DBG___POR 0x0 +#define PHYA_ROBE_CG_CONTROL_1_L__DYN_CGC_DISABLE_ALL___M 0x00010000 +#define PHYA_ROBE_CG_CONTROL_1_L__DYN_CGC_DISABLE_ALL___S 16 +#define PHYA_ROBE_CG_CONTROL_1_L__DYN_CGC_DISABLE_CSR___M 0x00000100 +#define PHYA_ROBE_CG_CONTROL_1_L__DYN_CGC_DISABLE_CSR___S 8 +#define PHYA_ROBE_CG_CONTROL_1_L__DYN_CGC_DISABLE_DBG___M 0x00000001 +#define PHYA_ROBE_CG_CONTROL_1_L__DYN_CGC_DISABLE_DBG___S 0 +#define PHYA_ROBE_CG_CONTROL_1_L___M 0x00010101 +#define PHYA_ROBE_CG_CONTROL_1_L___S 0 + +#define PHYA_ROBE_SVS_CONTROL_L (0x004B02E0) +#define PHYA_ROBE_SVS_CONTROL_L___RWC QCSR_REG_RW +#define PHYA_ROBE_SVS_CONTROL_L___POR 0x00000000 +#define PHYA_ROBE_SVS_CONTROL_L__ROBE_SVS_CLK240_EN___POR 0x0 +#define PHYA_ROBE_SVS_CONTROL_L__ROBE_SVS_CLK240_EN___M 0x00000001 +#define PHYA_ROBE_SVS_CONTROL_L__ROBE_SVS_CLK240_EN___S 0 +#define PHYA_ROBE_SVS_CONTROL_L___M 0x00000001 +#define PHYA_ROBE_SVS_CONTROL_L___S 0 + +#define PHYA_ROBE_LDP_PASS_ITER_L (0x004B02E8) +#define PHYA_ROBE_LDP_PASS_ITER_L___RWC QCSR_REG_RW +#define PHYA_ROBE_LDP_PASS_ITER_L___POR 0x01010101 +#define PHYA_ROBE_LDP_PASS_ITER_L__ITER_LIMIT_RATE56___POR 0x1 +#define PHYA_ROBE_LDP_PASS_ITER_L__ITER_LIMIT_RATE34___POR 0x1 +#define PHYA_ROBE_LDP_PASS_ITER_L__ITER_LIMIT_RATE23___POR 0x1 +#define PHYA_ROBE_LDP_PASS_ITER_L__ITER_LIMIT_RATE12___POR 0x1 +#define PHYA_ROBE_LDP_PASS_ITER_L__ITER_LIMIT_RATE56___M 0x07000000 +#define PHYA_ROBE_LDP_PASS_ITER_L__ITER_LIMIT_RATE56___S 24 +#define PHYA_ROBE_LDP_PASS_ITER_L__ITER_LIMIT_RATE34___M 0x00070000 +#define PHYA_ROBE_LDP_PASS_ITER_L__ITER_LIMIT_RATE34___S 16 +#define PHYA_ROBE_LDP_PASS_ITER_L__ITER_LIMIT_RATE23___M 0x00000700 +#define PHYA_ROBE_LDP_PASS_ITER_L__ITER_LIMIT_RATE23___S 8 +#define PHYA_ROBE_LDP_PASS_ITER_L__ITER_LIMIT_RATE12___M 0x00000007 +#define PHYA_ROBE_LDP_PASS_ITER_L__ITER_LIMIT_RATE12___S 0 +#define PHYA_ROBE_LDP_PASS_ITER_L___M 0x07070707 +#define PHYA_ROBE_LDP_PASS_ITER_L___S 0 + +#define PHYA_ROBE_WDOG_CONTROL_0_L (0x004B02F0) +#define PHYA_ROBE_WDOG_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_ROBE_WDOG_CONTROL_0_L___POR 0x177000C8 +#define PHYA_ROBE_WDOG_CONTROL_0_L__WDOG_PAYLD_USEC___POR 0x1770 +#define PHYA_ROBE_WDOG_CONTROL_0_L__WDOG_HDR_USEC___POR 0xC8 +#define PHYA_ROBE_WDOG_CONTROL_0_L__WDOG_PAYLD_USEC___M 0xFFFF0000 +#define PHYA_ROBE_WDOG_CONTROL_0_L__WDOG_PAYLD_USEC___S 16 +#define PHYA_ROBE_WDOG_CONTROL_0_L__WDOG_HDR_USEC___M 0x000000FF +#define PHYA_ROBE_WDOG_CONTROL_0_L__WDOG_HDR_USEC___S 0 +#define PHYA_ROBE_WDOG_CONTROL_0_L___M 0xFFFF00FF +#define PHYA_ROBE_WDOG_CONTROL_0_L___S 0 + +#define PHYA_ROBE_WDOG_CONTROL_0_U (0x004B02F4) +#define PHYA_ROBE_WDOG_CONTROL_0_U___RWC QCSR_REG_RW +#define PHYA_ROBE_WDOG_CONTROL_0_U___POR 0xFA042010 +#define PHYA_ROBE_WDOG_CONTROL_0_U__WDOG_VIT_USEC___POR 0xFA +#define PHYA_ROBE_WDOG_CONTROL_0_U__WDOG_LDPC_USEC___POR 0x04 +#define PHYA_ROBE_WDOG_CONTROL_0_U__WDOG_SCHD_USEC___POR 0x20 +#define PHYA_ROBE_WDOG_CONTROL_0_U__WDOG_CTRL_USEC___POR 0x10 +#define PHYA_ROBE_WDOG_CONTROL_0_U__WDOG_VIT_USEC___M 0xFF000000 +#define PHYA_ROBE_WDOG_CONTROL_0_U__WDOG_VIT_USEC___S 24 +#define PHYA_ROBE_WDOG_CONTROL_0_U__WDOG_LDPC_USEC___M 0x00FF0000 +#define PHYA_ROBE_WDOG_CONTROL_0_U__WDOG_LDPC_USEC___S 16 +#define PHYA_ROBE_WDOG_CONTROL_0_U__WDOG_SCHD_USEC___M 0x0000FF00 +#define PHYA_ROBE_WDOG_CONTROL_0_U__WDOG_SCHD_USEC___S 8 +#define PHYA_ROBE_WDOG_CONTROL_0_U__WDOG_CTRL_USEC___M 0x000000FF +#define PHYA_ROBE_WDOG_CONTROL_0_U__WDOG_CTRL_USEC___S 0 +#define PHYA_ROBE_WDOG_CONTROL_0_U___M 0xFFFFFFFF +#define PHYA_ROBE_WDOG_CONTROL_0_U___S 0 + +#define PHYA_ROBE_WDOG_CONTROL_1_L (0x004B02F8) +#define PHYA_ROBE_WDOG_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_ROBE_WDOG_CONTROL_1_L___POR 0x004F0404 +#define PHYA_ROBE_WDOG_CONTROL_1_L__WDOG_BMMU_USEC___POR 0x4F +#define PHYA_ROBE_WDOG_CONTROL_1_L__WDOG_TRFC_USEC___POR 0x04 +#define PHYA_ROBE_WDOG_CONTROL_1_L__WDOG_DEINT_USEC___POR 0x04 +#define PHYA_ROBE_WDOG_CONTROL_1_L__WDOG_BMMU_USEC___M 0x00FF0000 +#define PHYA_ROBE_WDOG_CONTROL_1_L__WDOG_BMMU_USEC___S 16 +#define PHYA_ROBE_WDOG_CONTROL_1_L__WDOG_TRFC_USEC___M 0x0000FF00 +#define PHYA_ROBE_WDOG_CONTROL_1_L__WDOG_TRFC_USEC___S 8 +#define PHYA_ROBE_WDOG_CONTROL_1_L__WDOG_DEINT_USEC___M 0x000000FF +#define PHYA_ROBE_WDOG_CONTROL_1_L__WDOG_DEINT_USEC___S 0 +#define PHYA_ROBE_WDOG_CONTROL_1_L___M 0x00FFFFFF +#define PHYA_ROBE_WDOG_CONTROL_1_L___S 0 + +#define PHYA_ROBE_DEBUG_CONTROL_0_L (0x004B0300) +#define PHYA_ROBE_DEBUG_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_ROBE_DEBUG_CONTROL_0_L___POR 0x01FC0000 +#define PHYA_ROBE_DEBUG_CONTROL_0_L__WD_LIMIT_HDR___POR 0x7F +#define PHYA_ROBE_DEBUG_CONTROL_0_L__WD_START_EVENT_SELECT_ARRY___POR 0x0000 +#define PHYA_ROBE_DEBUG_CONTROL_0_L__LOCK_MEM_FOR_DBGCAP___POR 0x0 +#define PHYA_ROBE_DEBUG_CONTROL_0_L__ROBE_DBG_EN___POR 0x0 +#define PHYA_ROBE_DEBUG_CONTROL_0_L__WD_LIMIT_HDR___M 0x01FC0000 +#define PHYA_ROBE_DEBUG_CONTROL_0_L__WD_LIMIT_HDR___S 18 +#define PHYA_ROBE_DEBUG_CONTROL_0_L__WD_START_EVENT_SELECT_ARRY___M 0x0003FFFC +#define PHYA_ROBE_DEBUG_CONTROL_0_L__WD_START_EVENT_SELECT_ARRY___S 2 +#define PHYA_ROBE_DEBUG_CONTROL_0_L__LOCK_MEM_FOR_DBGCAP___M 0x00000002 +#define PHYA_ROBE_DEBUG_CONTROL_0_L__LOCK_MEM_FOR_DBGCAP___S 1 +#define PHYA_ROBE_DEBUG_CONTROL_0_L__ROBE_DBG_EN___M 0x00000001 +#define PHYA_ROBE_DEBUG_CONTROL_0_L__ROBE_DBG_EN___S 0 +#define PHYA_ROBE_DEBUG_CONTROL_0_L___M 0x01FFFFFF +#define PHYA_ROBE_DEBUG_CONTROL_0_L___S 0 + +#define PHYA_ROBE_DEBUG_CONTROL_0_U (0x004B0304) +#define PHYA_ROBE_DEBUG_CONTROL_0_U___RWC QCSR_REG_RW +#define PHYA_ROBE_DEBUG_CONTROL_0_U___POR 0x00011770 +#define PHYA_ROBE_DEBUG_CONTROL_0_U__SINGLE_SHOT_CAPTURE___POR 0x0 +#define PHYA_ROBE_DEBUG_CONTROL_0_U__PICK_LS_LLR___POR 0x0 +#define PHYA_ROBE_DEBUG_CONTROL_0_U__DBG_MODE3_SEL___POR 0x0 +#define PHYA_ROBE_DEBUG_CONTROL_0_U__DBG_MODE___POR 0x0 +#define PHYA_ROBE_DEBUG_CONTROL_0_U__ROBE_TIMER_ONTIME___POR 0x1 +#define PHYA_ROBE_DEBUG_CONTROL_0_U__ROBE_TIMER_WD_RESET___POR 0x0 +#define PHYA_ROBE_DEBUG_CONTROL_0_U__WD_LIMIT_NONHDR___POR 0x1770 +#define PHYA_ROBE_DEBUG_CONTROL_0_U__SINGLE_SHOT_CAPTURE___M 0x04000000 +#define PHYA_ROBE_DEBUG_CONTROL_0_U__SINGLE_SHOT_CAPTURE___S 26 +#define PHYA_ROBE_DEBUG_CONTROL_0_U__PICK_LS_LLR___M 0x02000000 +#define PHYA_ROBE_DEBUG_CONTROL_0_U__PICK_LS_LLR___S 25 +#define PHYA_ROBE_DEBUG_CONTROL_0_U__DBG_MODE3_SEL___M 0x01E00000 +#define PHYA_ROBE_DEBUG_CONTROL_0_U__DBG_MODE3_SEL___S 21 +#define PHYA_ROBE_DEBUG_CONTROL_0_U__DBG_MODE___M 0x001E0000 +#define PHYA_ROBE_DEBUG_CONTROL_0_U__DBG_MODE___S 17 +#define PHYA_ROBE_DEBUG_CONTROL_0_U__ROBE_TIMER_ONTIME___M 0x00010000 +#define PHYA_ROBE_DEBUG_CONTROL_0_U__ROBE_TIMER_ONTIME___S 16 +#define PHYA_ROBE_DEBUG_CONTROL_0_U__ROBE_TIMER_WD_RESET___M 0x00008000 +#define PHYA_ROBE_DEBUG_CONTROL_0_U__ROBE_TIMER_WD_RESET___S 15 +#define PHYA_ROBE_DEBUG_CONTROL_0_U__WD_LIMIT_NONHDR___M 0x00007FFF +#define PHYA_ROBE_DEBUG_CONTROL_0_U__WD_LIMIT_NONHDR___S 0 +#define PHYA_ROBE_DEBUG_CONTROL_0_U___M 0x07FFFFFF +#define PHYA_ROBE_DEBUG_CONTROL_0_U___S 0 + +#define PHYA_ROBE_DEBUG_CONTROL_1_L (0x004B0308) +#define PHYA_ROBE_DEBUG_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_ROBE_DEBUG_CONTROL_1_L___POR 0x00000000 +#define PHYA_ROBE_DEBUG_CONTROL_1_L__BIMM_MEM_DBG___POR 0x0 +#define PHYA_ROBE_DEBUG_CONTROL_1_L__DBG_USR_DATA_REP___POR 0x0 +#define PHYA_ROBE_DEBUG_CONTROL_1_L__HESIGB_LATCH_IDX___POR 0x00 +#define PHYA_ROBE_DEBUG_CONTROL_1_L__USR_IDX_FOR_DBG___POR 0x00 +#define PHYA_ROBE_DEBUG_CONTROL_1_L__BIMM_MEM_DBG___M 0x000C0000 +#define PHYA_ROBE_DEBUG_CONTROL_1_L__BIMM_MEM_DBG___S 18 +#define PHYA_ROBE_DEBUG_CONTROL_1_L__DBG_USR_DATA_REP___M 0x00038000 +#define PHYA_ROBE_DEBUG_CONTROL_1_L__DBG_USR_DATA_REP___S 15 +#define PHYA_ROBE_DEBUG_CONTROL_1_L__HESIGB_LATCH_IDX___M 0x00007F80 +#define PHYA_ROBE_DEBUG_CONTROL_1_L__HESIGB_LATCH_IDX___S 7 +#define PHYA_ROBE_DEBUG_CONTROL_1_L__USR_IDX_FOR_DBG___M 0x0000007F +#define PHYA_ROBE_DEBUG_CONTROL_1_L__USR_IDX_FOR_DBG___S 0 +#define PHYA_ROBE_DEBUG_CONTROL_1_L___M 0x000FFFFF +#define PHYA_ROBE_DEBUG_CONTROL_1_L___S 0 + +#define PHYA_ROBE_DEBUG_CONTROL_1_U (0x004B030C) +#define PHYA_ROBE_DEBUG_CONTROL_1_U___RWC QCSR_REG_RW +#define PHYA_ROBE_DEBUG_CONTROL_1_U___POR 0x00000000 +#define PHYA_ROBE_DEBUG_CONTROL_1_U__VIT_MEM_DBG___POR 0x0000 +#define PHYA_ROBE_DEBUG_CONTROL_1_U__LDPC_MEM_DBG___POR 0x0000 +#define PHYA_ROBE_DEBUG_CONTROL_1_U__VIT_MEM_DBG___M 0xFFFF0000 +#define PHYA_ROBE_DEBUG_CONTROL_1_U__VIT_MEM_DBG___S 16 +#define PHYA_ROBE_DEBUG_CONTROL_1_U__LDPC_MEM_DBG___M 0x0000FFFF +#define PHYA_ROBE_DEBUG_CONTROL_1_U__LDPC_MEM_DBG___S 0 +#define PHYA_ROBE_DEBUG_CONTROL_1_U___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_CONTROL_1_U___S 0 + +#define PHYA_ROBE_DEBUG_CONTROL_2_L (0x004B0310) +#define PHYA_ROBE_DEBUG_CONTROL_2_L___RWC QCSR_REG_RW +#define PHYA_ROBE_DEBUG_CONTROL_2_L___POR 0x00000000 +#define PHYA_ROBE_DEBUG_CONTROL_2_L__BMMU_DBG_PORT0___POR 0x0 +#define PHYA_ROBE_DEBUG_CONTROL_2_L__BMMU_DBG_SET___POR 0x0 +#define PHYA_ROBE_DEBUG_CONTROL_2_L__BMMU_DBG_SEL___POR 0x0 +#define PHYA_ROBE_DEBUG_CONTROL_2_L__TRFC_DBG_SEL___POR 0x0 +#define PHYA_ROBE_DEBUG_CONTROL_2_L__SCHD_DBG_SEL___POR 0x0 +#define PHYA_ROBE_DEBUG_CONTROL_2_L__CTRL_DBG_SEL___POR 0x0 +#define PHYA_ROBE_DEBUG_CONTROL_2_L__LDPC_DBG_SEL___POR 0x0 +#define PHYA_ROBE_DEBUG_CONTROL_2_L__VIT_DBG_SEL___POR 0x0 +#define PHYA_ROBE_DEBUG_CONTROL_2_L__DEINT_DBG_SEL___POR 0x0 +#define PHYA_ROBE_DEBUG_CONTROL_2_L__BMMU_DBG_PORT0___M 0x60000000 +#define PHYA_ROBE_DEBUG_CONTROL_2_L__BMMU_DBG_PORT0___S 29 +#define PHYA_ROBE_DEBUG_CONTROL_2_L__BMMU_DBG_SET___M 0x10000000 +#define PHYA_ROBE_DEBUG_CONTROL_2_L__BMMU_DBG_SET___S 28 +#define PHYA_ROBE_DEBUG_CONTROL_2_L__BMMU_DBG_SEL___M 0x0F000000 +#define PHYA_ROBE_DEBUG_CONTROL_2_L__BMMU_DBG_SEL___S 24 +#define PHYA_ROBE_DEBUG_CONTROL_2_L__TRFC_DBG_SEL___M 0x00F00000 +#define PHYA_ROBE_DEBUG_CONTROL_2_L__TRFC_DBG_SEL___S 20 +#define PHYA_ROBE_DEBUG_CONTROL_2_L__SCHD_DBG_SEL___M 0x000F0000 +#define PHYA_ROBE_DEBUG_CONTROL_2_L__SCHD_DBG_SEL___S 16 +#define PHYA_ROBE_DEBUG_CONTROL_2_L__CTRL_DBG_SEL___M 0x0000F000 +#define PHYA_ROBE_DEBUG_CONTROL_2_L__CTRL_DBG_SEL___S 12 +#define PHYA_ROBE_DEBUG_CONTROL_2_L__LDPC_DBG_SEL___M 0x00000F00 +#define PHYA_ROBE_DEBUG_CONTROL_2_L__LDPC_DBG_SEL___S 8 +#define PHYA_ROBE_DEBUG_CONTROL_2_L__VIT_DBG_SEL___M 0x000000F0 +#define PHYA_ROBE_DEBUG_CONTROL_2_L__VIT_DBG_SEL___S 4 +#define PHYA_ROBE_DEBUG_CONTROL_2_L__DEINT_DBG_SEL___M 0x0000000F +#define PHYA_ROBE_DEBUG_CONTROL_2_L__DEINT_DBG_SEL___S 0 +#define PHYA_ROBE_DEBUG_CONTROL_2_L___M 0x7FFFFFFF +#define PHYA_ROBE_DEBUG_CONTROL_2_L___S 0 + +#define PHYA_ROBE_DEBUG_CONTROL_2_U (0x004B0314) +#define PHYA_ROBE_DEBUG_CONTROL_2_U___RWC QCSR_REG_RW +#define PHYA_ROBE_DEBUG_CONTROL_2_U___POR 0x00FF8000 +#define PHYA_ROBE_DEBUG_CONTROL_2_U__CLEAR_PKT_START_COUNT___POR 0x0 +#define PHYA_ROBE_DEBUG_CONTROL_2_U__BMMU_MIN_AVAIL_CLR___POR 0x0 +#define PHYA_ROBE_DEBUG_CONTROL_2_U__DBG_MODE1B_STRM_NO___POR 0x0 +#define PHYA_ROBE_DEBUG_CONTROL_2_U__DBG_MODE1B_SEG_CFG___POR 0x0 +#define PHYA_ROBE_DEBUG_CONTROL_2_U__DBG_MODE1_LATCH_ON_RU_END___POR 0x0 +#define PHYA_ROBE_DEBUG_CONTROL_2_U__SHORT_LLM_BLK___POR 0x1FF +#define PHYA_ROBE_DEBUG_CONTROL_2_U__SHORT_LLM_EN___POR 0x0 +#define PHYA_ROBE_DEBUG_CONTROL_2_U__BMMU_DBG_USR1___POR 0x00 +#define PHYA_ROBE_DEBUG_CONTROL_2_U__BMMU_DBG_USR0___POR 0x00 +#define PHYA_ROBE_DEBUG_CONTROL_2_U__BMMU_DBG_PORT1___POR 0x0 +#define PHYA_ROBE_DEBUG_CONTROL_2_U__CLEAR_PKT_START_COUNT___M 0x40000000 +#define PHYA_ROBE_DEBUG_CONTROL_2_U__CLEAR_PKT_START_COUNT___S 30 +#define PHYA_ROBE_DEBUG_CONTROL_2_U__BMMU_MIN_AVAIL_CLR___M 0x20000000 +#define PHYA_ROBE_DEBUG_CONTROL_2_U__BMMU_MIN_AVAIL_CLR___S 29 +#define PHYA_ROBE_DEBUG_CONTROL_2_U__DBG_MODE1B_STRM_NO___M 0x18000000 +#define PHYA_ROBE_DEBUG_CONTROL_2_U__DBG_MODE1B_STRM_NO___S 27 +#define PHYA_ROBE_DEBUG_CONTROL_2_U__DBG_MODE1B_SEG_CFG___M 0x06000000 +#define PHYA_ROBE_DEBUG_CONTROL_2_U__DBG_MODE1B_SEG_CFG___S 25 +#define PHYA_ROBE_DEBUG_CONTROL_2_U__DBG_MODE1_LATCH_ON_RU_END___M 0x01000000 +#define PHYA_ROBE_DEBUG_CONTROL_2_U__DBG_MODE1_LATCH_ON_RU_END___S 24 +#define PHYA_ROBE_DEBUG_CONTROL_2_U__SHORT_LLM_BLK___M 0x00FF8000 +#define PHYA_ROBE_DEBUG_CONTROL_2_U__SHORT_LLM_BLK___S 15 +#define PHYA_ROBE_DEBUG_CONTROL_2_U__SHORT_LLM_EN___M 0x00004000 +#define PHYA_ROBE_DEBUG_CONTROL_2_U__SHORT_LLM_EN___S 14 +#define PHYA_ROBE_DEBUG_CONTROL_2_U__BMMU_DBG_USR1___M 0x00003F00 +#define PHYA_ROBE_DEBUG_CONTROL_2_U__BMMU_DBG_USR1___S 8 +#define PHYA_ROBE_DEBUG_CONTROL_2_U__BMMU_DBG_USR0___M 0x000000FC +#define PHYA_ROBE_DEBUG_CONTROL_2_U__BMMU_DBG_USR0___S 2 +#define PHYA_ROBE_DEBUG_CONTROL_2_U__BMMU_DBG_PORT1___M 0x00000003 +#define PHYA_ROBE_DEBUG_CONTROL_2_U__BMMU_DBG_PORT1___S 0 +#define PHYA_ROBE_DEBUG_CONTROL_2_U___M 0x7FFFFFFF +#define PHYA_ROBE_DEBUG_CONTROL_2_U___S 0 + +#define PHYA_ROBE_DEBUG_CONTROL_3_L (0x004B0318) +#define PHYA_ROBE_DEBUG_CONTROL_3_L___RWC QCSR_REG_RW +#define PHYA_ROBE_DEBUG_CONTROL_3_L___POR 0x00000000 +#define PHYA_ROBE_DEBUG_CONTROL_3_L__DBG_SPARE_0___POR 0x00000000 +#define PHYA_ROBE_DEBUG_CONTROL_3_L__DBG_SPARE_0___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_CONTROL_3_L__DBG_SPARE_0___S 0 +#define PHYA_ROBE_DEBUG_CONTROL_3_L___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_CONTROL_3_L___S 0 + +#define PHYA_ROBE_DEBUG_CONTROL_3_U (0x004B031C) +#define PHYA_ROBE_DEBUG_CONTROL_3_U___RWC QCSR_REG_RW +#define PHYA_ROBE_DEBUG_CONTROL_3_U___POR 0x00000000 +#define PHYA_ROBE_DEBUG_CONTROL_3_U__DBG_SPARE_1___POR 0x00000000 +#define PHYA_ROBE_DEBUG_CONTROL_3_U__DBG_SPARE_1___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_CONTROL_3_U__DBG_SPARE_1___S 0 +#define PHYA_ROBE_DEBUG_CONTROL_3_U___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_CONTROL_3_U___S 0 + +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_ADDR_L_n(n) (0x004B0320+0x8*(n)) +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_ADDR_L_n_nMIN 0 +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_ADDR_L_n_nMAX 0 +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_ADDR_L_n_ELEM 1 +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_ADDR_L_n___RWC QCSR_REG_RW +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_ADDR_L_n___POR 0x00000000 +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_ADDR_L_n__BMMU_MEM_ADDR___POR 0x00000000 +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_ADDR_L_n__BMMU_MEM_ADDR___M 0xFFFFFFFF +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_ADDR_L_n__BMMU_MEM_ADDR___S 0 +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_ADDR_L_n___M 0xFFFFFFFF +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_ADDR_L_n___S 0 +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_ADDR_L_0 (0x004B0320) +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_ADDR_L_0___RWC QCSR_REG_RW +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_ADDR_L_0__BMMU_MEM_ADDR___M 0xFFFFFFFF +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_ADDR_L_0__BMMU_MEM_ADDR___S 0 + +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_L_n(n) (0x004B0328+0x8*(n)) +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_L_n_nMIN 0 +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_L_n_nMAX 0 +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_L_n_ELEM 1 +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_L_n___RWC QCSR_REG_RW +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_L_n___POR 0x00000000 +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_L_n__BMMU_MEM_DATA_L32___POR 0x00000000 +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_L_n__BMMU_MEM_DATA_L32___M 0xFFFFFFFF +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_L_n__BMMU_MEM_DATA_L32___S 0 +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_L_n___M 0xFFFFFFFF +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_L_n___S 0 +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_L_0 (0x004B0328) +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_L_0___RWC QCSR_REG_RW +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_L_0__BMMU_MEM_DATA_L32___M 0xFFFFFFFF +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_L_0__BMMU_MEM_DATA_L32___S 0 + +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_U_n(n) (0x004B032C+0x8*(n)) +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_U_n_nMIN 0 +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_U_n_nMAX 0 +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_U_n_ELEM 1 +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_U_n___RWC QCSR_REG_RW +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_U_n___POR 0x00000000 +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_U_n__BMMU_MEM_DATA_U32___POR 0x00000000 +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_U_n__BMMU_MEM_DATA_U32___M 0xFFFFFFFF +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_U_n__BMMU_MEM_DATA_U32___S 0 +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_U_n___M 0xFFFFFFFF +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_U_n___S 0 +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_U_0 (0x004B032C) +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_U_0___RWC QCSR_REG_RW +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_U_0__BMMU_MEM_DATA_U32___M 0xFFFFFFFF +#define PHYA_ROBE_ROBEDBG_BMMU_MEM_DATA_U_0__BMMU_MEM_DATA_U32___S 0 + +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_ADDR_L_n(n) (0x004B0330+0x8*(n)) +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_ADDR_L_n_nMIN 0 +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_ADDR_L_n_nMAX 0 +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_ADDR_L_n_ELEM 1 +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_ADDR_L_n___RWC QCSR_REG_RW +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_ADDR_L_n___POR 0x00000000 +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_ADDR_L_n__LDPC_MEM_ADDR___POR 0x00000000 +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_ADDR_L_n__LDPC_MEM_ADDR___M 0xFFFFFFFF +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_ADDR_L_n__LDPC_MEM_ADDR___S 0 +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_ADDR_L_n___M 0xFFFFFFFF +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_ADDR_L_n___S 0 +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_ADDR_L_0 (0x004B0330) +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_ADDR_L_0___RWC QCSR_REG_RW +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_ADDR_L_0__LDPC_MEM_ADDR___M 0xFFFFFFFF +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_ADDR_L_0__LDPC_MEM_ADDR___S 0 + +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_L_n(n) (0x004B0338+0x8*(n)) +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_L_n_nMIN 0 +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_L_n_nMAX 0 +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_L_n_ELEM 1 +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_L_n___RWC QCSR_REG_RW +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_L_n___POR 0x00000000 +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_L_n__LDPC_MEM_DATA_L32___POR 0x00000000 +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_L_n__LDPC_MEM_DATA_L32___M 0xFFFFFFFF +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_L_n__LDPC_MEM_DATA_L32___S 0 +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_L_n___M 0xFFFFFFFF +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_L_n___S 0 +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_L_0 (0x004B0338) +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_L_0___RWC QCSR_REG_RW +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_L_0__LDPC_MEM_DATA_L32___M 0xFFFFFFFF +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_L_0__LDPC_MEM_DATA_L32___S 0 + +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_U_n(n) (0x004B033C+0x8*(n)) +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_U_n_nMIN 0 +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_U_n_nMAX 0 +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_U_n_ELEM 1 +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_U_n___RWC QCSR_REG_RW +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_U_n___POR 0x00000000 +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_U_n__LDPC_MEM_DATA_U32___POR 0x00000000 +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_U_n__LDPC_MEM_DATA_U32___M 0xFFFFFFFF +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_U_n__LDPC_MEM_DATA_U32___S 0 +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_U_n___M 0xFFFFFFFF +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_U_n___S 0 +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_U_0 (0x004B033C) +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_U_0___RWC QCSR_REG_RW +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_U_0__LDPC_MEM_DATA_U32___M 0xFFFFFFFF +#define PHYA_ROBE_ROBEDBG_LDPC_MEM_DATA_U_0__LDPC_MEM_DATA_U32___S 0 + +#define PHYA_ROBE_ROBEDBG_VIT_MEM_ADDR_L_n(n) (0x004B0340+0x8*(n)) +#define PHYA_ROBE_ROBEDBG_VIT_MEM_ADDR_L_n_nMIN 0 +#define PHYA_ROBE_ROBEDBG_VIT_MEM_ADDR_L_n_nMAX 0 +#define PHYA_ROBE_ROBEDBG_VIT_MEM_ADDR_L_n_ELEM 1 +#define PHYA_ROBE_ROBEDBG_VIT_MEM_ADDR_L_n___RWC QCSR_REG_RW +#define PHYA_ROBE_ROBEDBG_VIT_MEM_ADDR_L_n___POR 0x00000000 +#define PHYA_ROBE_ROBEDBG_VIT_MEM_ADDR_L_n__VIT_MEM_ADDR___POR 0x00000000 +#define PHYA_ROBE_ROBEDBG_VIT_MEM_ADDR_L_n__VIT_MEM_ADDR___M 0xFFFFFFFF +#define PHYA_ROBE_ROBEDBG_VIT_MEM_ADDR_L_n__VIT_MEM_ADDR___S 0 +#define PHYA_ROBE_ROBEDBG_VIT_MEM_ADDR_L_n___M 0xFFFFFFFF +#define PHYA_ROBE_ROBEDBG_VIT_MEM_ADDR_L_n___S 0 +#define PHYA_ROBE_ROBEDBG_VIT_MEM_ADDR_L_0 (0x004B0340) +#define PHYA_ROBE_ROBEDBG_VIT_MEM_ADDR_L_0___RWC QCSR_REG_RW +#define PHYA_ROBE_ROBEDBG_VIT_MEM_ADDR_L_0__VIT_MEM_ADDR___M 0xFFFFFFFF +#define PHYA_ROBE_ROBEDBG_VIT_MEM_ADDR_L_0__VIT_MEM_ADDR___S 0 + +#define PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_L_n(n) (0x004B0348+0x8*(n)) +#define PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_L_n_nMIN 0 +#define PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_L_n_nMAX 0 +#define PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_L_n_ELEM 1 +#define PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_L_n___RWC QCSR_REG_RW +#define PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_L_n___POR 0x00000000 +#define PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_L_n__VIT_MEM_DATA_L32___POR 0x00000000 +#define PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_L_n__VIT_MEM_DATA_L32___M 0xFFFFFFFF +#define PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_L_n__VIT_MEM_DATA_L32___S 0 +#define PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_L_n___M 0xFFFFFFFF +#define PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_L_n___S 0 +#define PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_L_0 (0x004B0348) +#define PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_L_0___RWC QCSR_REG_RW +#define PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_L_0__VIT_MEM_DATA_L32___M 0xFFFFFFFF +#define PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_L_0__VIT_MEM_DATA_L32___S 0 + +#define PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_U_n(n) (0x004B034C+0x8*(n)) +#define PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_U_n_nMIN 0 +#define PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_U_n_nMAX 0 +#define PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_U_n_ELEM 1 +#define PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_U_n___RWC QCSR_REG_RW +#define PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_U_n___POR 0x00000000 +#define PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_U_n__VIT_MEM_DATA_U32___POR 0x00000000 +#define PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_U_n__VIT_MEM_DATA_U32___M 0xFFFFFFFF +#define PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_U_n__VIT_MEM_DATA_U32___S 0 +#define PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_U_n___M 0xFFFFFFFF +#define PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_U_n___S 0 +#define PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_U_0 (0x004B034C) +#define PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_U_0___RWC QCSR_REG_RW +#define PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_U_0__VIT_MEM_DATA_U32___M 0xFFFFFFFF +#define PHYA_ROBE_ROBEDBG_VIT_MEM_DATA_U_0__VIT_MEM_DATA_U32___S 0 + +#define PHYA_ROBE_MAX_ITER_SU_0_L (0x004B0350) +#define PHYA_ROBE_MAX_ITER_SU_0_L___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_ITER_SU_0_L___POR 0x0E0B0D10 +#define PHYA_ROBE_MAX_ITER_SU_0_L__MAX_ITR_SU_MCS_3___POR 0x0E +#define PHYA_ROBE_MAX_ITER_SU_0_L__MAX_ITR_SU_MCS_2___POR 0x0B +#define PHYA_ROBE_MAX_ITER_SU_0_L__MAX_ITR_SU_MCS_1___POR 0x0D +#define PHYA_ROBE_MAX_ITER_SU_0_L__MAX_ITR_SU_MCS_0___POR 0x10 +#define PHYA_ROBE_MAX_ITER_SU_0_L__MAX_ITR_SU_MCS_3___M 0xFF000000 +#define PHYA_ROBE_MAX_ITER_SU_0_L__MAX_ITR_SU_MCS_3___S 24 +#define PHYA_ROBE_MAX_ITER_SU_0_L__MAX_ITR_SU_MCS_2___M 0x00FF0000 +#define PHYA_ROBE_MAX_ITER_SU_0_L__MAX_ITR_SU_MCS_2___S 16 +#define PHYA_ROBE_MAX_ITER_SU_0_L__MAX_ITR_SU_MCS_1___M 0x0000FF00 +#define PHYA_ROBE_MAX_ITER_SU_0_L__MAX_ITR_SU_MCS_1___S 8 +#define PHYA_ROBE_MAX_ITER_SU_0_L__MAX_ITR_SU_MCS_0___M 0x000000FF +#define PHYA_ROBE_MAX_ITER_SU_0_L__MAX_ITR_SU_MCS_0___S 0 +#define PHYA_ROBE_MAX_ITER_SU_0_L___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_ITER_SU_0_L___S 0 + +#define PHYA_ROBE_MAX_ITER_SU_0_U (0x004B0354) +#define PHYA_ROBE_MAX_ITER_SU_0_U___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_ITER_SU_0_U___POR 0x0B0C0E0E +#define PHYA_ROBE_MAX_ITER_SU_0_U__MAX_ITR_SU_MCS_7___POR 0x0B +#define PHYA_ROBE_MAX_ITER_SU_0_U__MAX_ITR_SU_MCS_6___POR 0x0C +#define PHYA_ROBE_MAX_ITER_SU_0_U__MAX_ITR_SU_MCS_5___POR 0x0E +#define PHYA_ROBE_MAX_ITER_SU_0_U__MAX_ITR_SU_MCS_4___POR 0x0E +#define PHYA_ROBE_MAX_ITER_SU_0_U__MAX_ITR_SU_MCS_7___M 0xFF000000 +#define PHYA_ROBE_MAX_ITER_SU_0_U__MAX_ITR_SU_MCS_7___S 24 +#define PHYA_ROBE_MAX_ITER_SU_0_U__MAX_ITR_SU_MCS_6___M 0x00FF0000 +#define PHYA_ROBE_MAX_ITER_SU_0_U__MAX_ITR_SU_MCS_6___S 16 +#define PHYA_ROBE_MAX_ITER_SU_0_U__MAX_ITR_SU_MCS_5___M 0x0000FF00 +#define PHYA_ROBE_MAX_ITER_SU_0_U__MAX_ITR_SU_MCS_5___S 8 +#define PHYA_ROBE_MAX_ITER_SU_0_U__MAX_ITR_SU_MCS_4___M 0x000000FF +#define PHYA_ROBE_MAX_ITER_SU_0_U__MAX_ITR_SU_MCS_4___S 0 +#define PHYA_ROBE_MAX_ITER_SU_0_U___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_ITER_SU_0_U___S 0 + +#define PHYA_ROBE_MAX_ITER_SU_1_L (0x004B0358) +#define PHYA_ROBE_MAX_ITER_SU_1_L___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_ITER_SU_1_L___POR 0x0F0D0D0C +#define PHYA_ROBE_MAX_ITER_SU_1_L__MAX_ITR_SU_MCS_11___POR 0x0F +#define PHYA_ROBE_MAX_ITER_SU_1_L__MAX_ITR_SU_MCS_10___POR 0x0D +#define PHYA_ROBE_MAX_ITER_SU_1_L__MAX_ITR_SU_MCS_9___POR 0x0D +#define PHYA_ROBE_MAX_ITER_SU_1_L__MAX_ITR_SU_MCS_8___POR 0x0C +#define PHYA_ROBE_MAX_ITER_SU_1_L__MAX_ITR_SU_MCS_11___M 0xFF000000 +#define PHYA_ROBE_MAX_ITER_SU_1_L__MAX_ITR_SU_MCS_11___S 24 +#define PHYA_ROBE_MAX_ITER_SU_1_L__MAX_ITR_SU_MCS_10___M 0x00FF0000 +#define PHYA_ROBE_MAX_ITER_SU_1_L__MAX_ITR_SU_MCS_10___S 16 +#define PHYA_ROBE_MAX_ITER_SU_1_L__MAX_ITR_SU_MCS_9___M 0x0000FF00 +#define PHYA_ROBE_MAX_ITER_SU_1_L__MAX_ITR_SU_MCS_9___S 8 +#define PHYA_ROBE_MAX_ITER_SU_1_L__MAX_ITR_SU_MCS_8___M 0x000000FF +#define PHYA_ROBE_MAX_ITER_SU_1_L__MAX_ITR_SU_MCS_8___S 0 +#define PHYA_ROBE_MAX_ITER_SU_1_L___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_ITER_SU_1_L___S 0 + +#define PHYA_ROBE_MAX_ITER_SU_1_U (0x004B035C) +#define PHYA_ROBE_MAX_ITER_SU_1_U___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_ITER_SU_1_U___POR 0x0F0F0F0F +#define PHYA_ROBE_MAX_ITER_SU_1_U__MAX_ITR_SU_MCS_15___POR 0x0F +#define PHYA_ROBE_MAX_ITER_SU_1_U__MAX_ITR_SU_MCS_14___POR 0x0F +#define PHYA_ROBE_MAX_ITER_SU_1_U__MAX_ITR_SU_MCS_13___POR 0x0F +#define PHYA_ROBE_MAX_ITER_SU_1_U__MAX_ITR_SU_MCS_12___POR 0x0F +#define PHYA_ROBE_MAX_ITER_SU_1_U__MAX_ITR_SU_MCS_15___M 0xFF000000 +#define PHYA_ROBE_MAX_ITER_SU_1_U__MAX_ITR_SU_MCS_15___S 24 +#define PHYA_ROBE_MAX_ITER_SU_1_U__MAX_ITR_SU_MCS_14___M 0x00FF0000 +#define PHYA_ROBE_MAX_ITER_SU_1_U__MAX_ITR_SU_MCS_14___S 16 +#define PHYA_ROBE_MAX_ITER_SU_1_U__MAX_ITR_SU_MCS_13___M 0x0000FF00 +#define PHYA_ROBE_MAX_ITER_SU_1_U__MAX_ITR_SU_MCS_13___S 8 +#define PHYA_ROBE_MAX_ITER_SU_1_U__MAX_ITR_SU_MCS_12___M 0x000000FF +#define PHYA_ROBE_MAX_ITER_SU_1_U__MAX_ITR_SU_MCS_12___S 0 +#define PHYA_ROBE_MAX_ITER_SU_1_U___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_ITER_SU_1_U___S 0 + +#define PHYA_ROBE_MAX_ITER_MUM_0_L (0x004B0360) +#define PHYA_ROBE_MAX_ITER_MUM_0_L___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_ITER_MUM_0_L___POR 0x0E0B0D10 +#define PHYA_ROBE_MAX_ITER_MUM_0_L__MAX_ITR_MUM_MCS_3___POR 0x0E +#define PHYA_ROBE_MAX_ITER_MUM_0_L__MAX_ITR_MUM_MCS_2___POR 0x0B +#define PHYA_ROBE_MAX_ITER_MUM_0_L__MAX_ITR_MUM_MCS_1___POR 0x0D +#define PHYA_ROBE_MAX_ITER_MUM_0_L__MAX_ITR_MUM_MCS_0___POR 0x10 +#define PHYA_ROBE_MAX_ITER_MUM_0_L__MAX_ITR_MUM_MCS_3___M 0xFF000000 +#define PHYA_ROBE_MAX_ITER_MUM_0_L__MAX_ITR_MUM_MCS_3___S 24 +#define PHYA_ROBE_MAX_ITER_MUM_0_L__MAX_ITR_MUM_MCS_2___M 0x00FF0000 +#define PHYA_ROBE_MAX_ITER_MUM_0_L__MAX_ITR_MUM_MCS_2___S 16 +#define PHYA_ROBE_MAX_ITER_MUM_0_L__MAX_ITR_MUM_MCS_1___M 0x0000FF00 +#define PHYA_ROBE_MAX_ITER_MUM_0_L__MAX_ITR_MUM_MCS_1___S 8 +#define PHYA_ROBE_MAX_ITER_MUM_0_L__MAX_ITR_MUM_MCS_0___M 0x000000FF +#define PHYA_ROBE_MAX_ITER_MUM_0_L__MAX_ITR_MUM_MCS_0___S 0 +#define PHYA_ROBE_MAX_ITER_MUM_0_L___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_ITER_MUM_0_L___S 0 + +#define PHYA_ROBE_MAX_ITER_MUM_0_U (0x004B0364) +#define PHYA_ROBE_MAX_ITER_MUM_0_U___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_ITER_MUM_0_U___POR 0x0B0C0E0E +#define PHYA_ROBE_MAX_ITER_MUM_0_U__MAX_ITR_MUM_MCS_7___POR 0x0B +#define PHYA_ROBE_MAX_ITER_MUM_0_U__MAX_ITR_MUM_MCS_6___POR 0x0C +#define PHYA_ROBE_MAX_ITER_MUM_0_U__MAX_ITR_MUM_MCS_5___POR 0x0E +#define PHYA_ROBE_MAX_ITER_MUM_0_U__MAX_ITR_MUM_MCS_4___POR 0x0E +#define PHYA_ROBE_MAX_ITER_MUM_0_U__MAX_ITR_MUM_MCS_7___M 0xFF000000 +#define PHYA_ROBE_MAX_ITER_MUM_0_U__MAX_ITR_MUM_MCS_7___S 24 +#define PHYA_ROBE_MAX_ITER_MUM_0_U__MAX_ITR_MUM_MCS_6___M 0x00FF0000 +#define PHYA_ROBE_MAX_ITER_MUM_0_U__MAX_ITR_MUM_MCS_6___S 16 +#define PHYA_ROBE_MAX_ITER_MUM_0_U__MAX_ITR_MUM_MCS_5___M 0x0000FF00 +#define PHYA_ROBE_MAX_ITER_MUM_0_U__MAX_ITR_MUM_MCS_5___S 8 +#define PHYA_ROBE_MAX_ITER_MUM_0_U__MAX_ITR_MUM_MCS_4___M 0x000000FF +#define PHYA_ROBE_MAX_ITER_MUM_0_U__MAX_ITR_MUM_MCS_4___S 0 +#define PHYA_ROBE_MAX_ITER_MUM_0_U___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_ITER_MUM_0_U___S 0 + +#define PHYA_ROBE_MAX_ITER_MUM_1_L (0x004B0368) +#define PHYA_ROBE_MAX_ITER_MUM_1_L___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_ITER_MUM_1_L___POR 0x0F0D0D0C +#define PHYA_ROBE_MAX_ITER_MUM_1_L__MAX_ITR_MUM_MCS_11___POR 0x0F +#define PHYA_ROBE_MAX_ITER_MUM_1_L__MAX_ITR_MUM_MCS_10___POR 0x0D +#define PHYA_ROBE_MAX_ITER_MUM_1_L__MAX_ITR_MUM_MCS_9___POR 0x0D +#define PHYA_ROBE_MAX_ITER_MUM_1_L__MAX_ITR_MUM_MCS_8___POR 0x0C +#define PHYA_ROBE_MAX_ITER_MUM_1_L__MAX_ITR_MUM_MCS_11___M 0xFF000000 +#define PHYA_ROBE_MAX_ITER_MUM_1_L__MAX_ITR_MUM_MCS_11___S 24 +#define PHYA_ROBE_MAX_ITER_MUM_1_L__MAX_ITR_MUM_MCS_10___M 0x00FF0000 +#define PHYA_ROBE_MAX_ITER_MUM_1_L__MAX_ITR_MUM_MCS_10___S 16 +#define PHYA_ROBE_MAX_ITER_MUM_1_L__MAX_ITR_MUM_MCS_9___M 0x0000FF00 +#define PHYA_ROBE_MAX_ITER_MUM_1_L__MAX_ITR_MUM_MCS_9___S 8 +#define PHYA_ROBE_MAX_ITER_MUM_1_L__MAX_ITR_MUM_MCS_8___M 0x000000FF +#define PHYA_ROBE_MAX_ITER_MUM_1_L__MAX_ITR_MUM_MCS_8___S 0 +#define PHYA_ROBE_MAX_ITER_MUM_1_L___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_ITER_MUM_1_L___S 0 + +#define PHYA_ROBE_MAX_ITER_MUM_1_U (0x004B036C) +#define PHYA_ROBE_MAX_ITER_MUM_1_U___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_ITER_MUM_1_U___POR 0x0F0F0F0F +#define PHYA_ROBE_MAX_ITER_MUM_1_U__MAX_ITR_MUM_MCS_15___POR 0x0F +#define PHYA_ROBE_MAX_ITER_MUM_1_U__MAX_ITR_MUM_MCS_14___POR 0x0F +#define PHYA_ROBE_MAX_ITER_MUM_1_U__MAX_ITR_MUM_MCS_13___POR 0x0F +#define PHYA_ROBE_MAX_ITER_MUM_1_U__MAX_ITR_MUM_MCS_12___POR 0x0F +#define PHYA_ROBE_MAX_ITER_MUM_1_U__MAX_ITR_MUM_MCS_15___M 0xFF000000 +#define PHYA_ROBE_MAX_ITER_MUM_1_U__MAX_ITR_MUM_MCS_15___S 24 +#define PHYA_ROBE_MAX_ITER_MUM_1_U__MAX_ITR_MUM_MCS_14___M 0x00FF0000 +#define PHYA_ROBE_MAX_ITER_MUM_1_U__MAX_ITR_MUM_MCS_14___S 16 +#define PHYA_ROBE_MAX_ITER_MUM_1_U__MAX_ITR_MUM_MCS_13___M 0x0000FF00 +#define PHYA_ROBE_MAX_ITER_MUM_1_U__MAX_ITR_MUM_MCS_13___S 8 +#define PHYA_ROBE_MAX_ITER_MUM_1_U__MAX_ITR_MUM_MCS_12___M 0x000000FF +#define PHYA_ROBE_MAX_ITER_MUM_1_U__MAX_ITR_MUM_MCS_12___S 0 +#define PHYA_ROBE_MAX_ITER_MUM_1_U___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_ITER_MUM_1_U___S 0 + +#define PHYA_ROBE_MAX_ITER_MUO_0_L (0x004B0370) +#define PHYA_ROBE_MAX_ITER_MUO_0_L___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_ITER_MUO_0_L___POR 0x0E0B0D10 +#define PHYA_ROBE_MAX_ITER_MUO_0_L__MAX_ITR_MUO_MCS_3___POR 0x0E +#define PHYA_ROBE_MAX_ITER_MUO_0_L__MAX_ITR_MUO_MCS_2___POR 0x0B +#define PHYA_ROBE_MAX_ITER_MUO_0_L__MAX_ITR_MUO_MCS_1___POR 0x0D +#define PHYA_ROBE_MAX_ITER_MUO_0_L__MAX_ITR_MUO_MCS_0___POR 0x10 +#define PHYA_ROBE_MAX_ITER_MUO_0_L__MAX_ITR_MUO_MCS_3___M 0xFF000000 +#define PHYA_ROBE_MAX_ITER_MUO_0_L__MAX_ITR_MUO_MCS_3___S 24 +#define PHYA_ROBE_MAX_ITER_MUO_0_L__MAX_ITR_MUO_MCS_2___M 0x00FF0000 +#define PHYA_ROBE_MAX_ITER_MUO_0_L__MAX_ITR_MUO_MCS_2___S 16 +#define PHYA_ROBE_MAX_ITER_MUO_0_L__MAX_ITR_MUO_MCS_1___M 0x0000FF00 +#define PHYA_ROBE_MAX_ITER_MUO_0_L__MAX_ITR_MUO_MCS_1___S 8 +#define PHYA_ROBE_MAX_ITER_MUO_0_L__MAX_ITR_MUO_MCS_0___M 0x000000FF +#define PHYA_ROBE_MAX_ITER_MUO_0_L__MAX_ITR_MUO_MCS_0___S 0 +#define PHYA_ROBE_MAX_ITER_MUO_0_L___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_ITER_MUO_0_L___S 0 + +#define PHYA_ROBE_MAX_ITER_MUO_0_U (0x004B0374) +#define PHYA_ROBE_MAX_ITER_MUO_0_U___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_ITER_MUO_0_U___POR 0x0B0C0E0E +#define PHYA_ROBE_MAX_ITER_MUO_0_U__MAX_ITR_MUO_MCS_7___POR 0x0B +#define PHYA_ROBE_MAX_ITER_MUO_0_U__MAX_ITR_MUO_MCS_6___POR 0x0C +#define PHYA_ROBE_MAX_ITER_MUO_0_U__MAX_ITR_MUO_MCS_5___POR 0x0E +#define PHYA_ROBE_MAX_ITER_MUO_0_U__MAX_ITR_MUO_MCS_4___POR 0x0E +#define PHYA_ROBE_MAX_ITER_MUO_0_U__MAX_ITR_MUO_MCS_7___M 0xFF000000 +#define PHYA_ROBE_MAX_ITER_MUO_0_U__MAX_ITR_MUO_MCS_7___S 24 +#define PHYA_ROBE_MAX_ITER_MUO_0_U__MAX_ITR_MUO_MCS_6___M 0x00FF0000 +#define PHYA_ROBE_MAX_ITER_MUO_0_U__MAX_ITR_MUO_MCS_6___S 16 +#define PHYA_ROBE_MAX_ITER_MUO_0_U__MAX_ITR_MUO_MCS_5___M 0x0000FF00 +#define PHYA_ROBE_MAX_ITER_MUO_0_U__MAX_ITR_MUO_MCS_5___S 8 +#define PHYA_ROBE_MAX_ITER_MUO_0_U__MAX_ITR_MUO_MCS_4___M 0x000000FF +#define PHYA_ROBE_MAX_ITER_MUO_0_U__MAX_ITR_MUO_MCS_4___S 0 +#define PHYA_ROBE_MAX_ITER_MUO_0_U___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_ITER_MUO_0_U___S 0 + +#define PHYA_ROBE_MAX_ITER_MUO_1_L (0x004B0378) +#define PHYA_ROBE_MAX_ITER_MUO_1_L___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_ITER_MUO_1_L___POR 0x0F0D0D0C +#define PHYA_ROBE_MAX_ITER_MUO_1_L__MAX_ITR_MUO_MCS_11___POR 0x0F +#define PHYA_ROBE_MAX_ITER_MUO_1_L__MAX_ITR_MUO_MCS_10___POR 0x0D +#define PHYA_ROBE_MAX_ITER_MUO_1_L__MAX_ITR_MUO_MCS_9___POR 0x0D +#define PHYA_ROBE_MAX_ITER_MUO_1_L__MAX_ITR_MUO_MCS_8___POR 0x0C +#define PHYA_ROBE_MAX_ITER_MUO_1_L__MAX_ITR_MUO_MCS_11___M 0xFF000000 +#define PHYA_ROBE_MAX_ITER_MUO_1_L__MAX_ITR_MUO_MCS_11___S 24 +#define PHYA_ROBE_MAX_ITER_MUO_1_L__MAX_ITR_MUO_MCS_10___M 0x00FF0000 +#define PHYA_ROBE_MAX_ITER_MUO_1_L__MAX_ITR_MUO_MCS_10___S 16 +#define PHYA_ROBE_MAX_ITER_MUO_1_L__MAX_ITR_MUO_MCS_9___M 0x0000FF00 +#define PHYA_ROBE_MAX_ITER_MUO_1_L__MAX_ITR_MUO_MCS_9___S 8 +#define PHYA_ROBE_MAX_ITER_MUO_1_L__MAX_ITR_MUO_MCS_8___M 0x000000FF +#define PHYA_ROBE_MAX_ITER_MUO_1_L__MAX_ITR_MUO_MCS_8___S 0 +#define PHYA_ROBE_MAX_ITER_MUO_1_L___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_ITER_MUO_1_L___S 0 + +#define PHYA_ROBE_MAX_ITER_MUO_1_U (0x004B037C) +#define PHYA_ROBE_MAX_ITER_MUO_1_U___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_ITER_MUO_1_U___POR 0x0F0F0F0F +#define PHYA_ROBE_MAX_ITER_MUO_1_U__MAX_ITR_MUO_MCS_15___POR 0x0F +#define PHYA_ROBE_MAX_ITER_MUO_1_U__MAX_ITR_MUO_MCS_14___POR 0x0F +#define PHYA_ROBE_MAX_ITER_MUO_1_U__MAX_ITR_MUO_MCS_13___POR 0x0F +#define PHYA_ROBE_MAX_ITER_MUO_1_U__MAX_ITR_MUO_MCS_12___POR 0x0F +#define PHYA_ROBE_MAX_ITER_MUO_1_U__MAX_ITR_MUO_MCS_15___M 0xFF000000 +#define PHYA_ROBE_MAX_ITER_MUO_1_U__MAX_ITR_MUO_MCS_15___S 24 +#define PHYA_ROBE_MAX_ITER_MUO_1_U__MAX_ITR_MUO_MCS_14___M 0x00FF0000 +#define PHYA_ROBE_MAX_ITER_MUO_1_U__MAX_ITR_MUO_MCS_14___S 16 +#define PHYA_ROBE_MAX_ITER_MUO_1_U__MAX_ITR_MUO_MCS_13___M 0x0000FF00 +#define PHYA_ROBE_MAX_ITER_MUO_1_U__MAX_ITR_MUO_MCS_13___S 8 +#define PHYA_ROBE_MAX_ITER_MUO_1_U__MAX_ITR_MUO_MCS_12___M 0x000000FF +#define PHYA_ROBE_MAX_ITER_MUO_1_U__MAX_ITR_MUO_MCS_12___S 0 +#define PHYA_ROBE_MAX_ITER_MUO_1_U___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_ITER_MUO_1_U___S 0 + +#define PHYA_ROBE_MAX_ITER_LST_0_L (0x004B0380) +#define PHYA_ROBE_MAX_ITER_LST_0_L___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_ITER_LST_0_L___POR 0x0A08090C +#define PHYA_ROBE_MAX_ITER_LST_0_L__MAX_ITR_LAST_MCS_3___POR 0x0A +#define PHYA_ROBE_MAX_ITER_LST_0_L__MAX_ITR_LAST_MCS_2___POR 0x08 +#define PHYA_ROBE_MAX_ITER_LST_0_L__MAX_ITR_LAST_MCS_1___POR 0x09 +#define PHYA_ROBE_MAX_ITER_LST_0_L__MAX_ITR_LAST_MCS_0___POR 0x0C +#define PHYA_ROBE_MAX_ITER_LST_0_L__MAX_ITR_LAST_MCS_3___M 0xFF000000 +#define PHYA_ROBE_MAX_ITER_LST_0_L__MAX_ITR_LAST_MCS_3___S 24 +#define PHYA_ROBE_MAX_ITER_LST_0_L__MAX_ITR_LAST_MCS_2___M 0x00FF0000 +#define PHYA_ROBE_MAX_ITER_LST_0_L__MAX_ITR_LAST_MCS_2___S 16 +#define PHYA_ROBE_MAX_ITER_LST_0_L__MAX_ITR_LAST_MCS_1___M 0x0000FF00 +#define PHYA_ROBE_MAX_ITER_LST_0_L__MAX_ITR_LAST_MCS_1___S 8 +#define PHYA_ROBE_MAX_ITER_LST_0_L__MAX_ITR_LAST_MCS_0___M 0x000000FF +#define PHYA_ROBE_MAX_ITER_LST_0_L__MAX_ITR_LAST_MCS_0___S 0 +#define PHYA_ROBE_MAX_ITER_LST_0_L___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_ITER_LST_0_L___S 0 + +#define PHYA_ROBE_MAX_ITER_LST_0_U (0x004B0384) +#define PHYA_ROBE_MAX_ITER_LST_0_U___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_ITER_LST_0_U___POR 0x0A0A0A0A +#define PHYA_ROBE_MAX_ITER_LST_0_U__MAX_ITR_LAST_MCS_7___POR 0x0A +#define PHYA_ROBE_MAX_ITER_LST_0_U__MAX_ITR_LAST_MCS_6___POR 0x0A +#define PHYA_ROBE_MAX_ITER_LST_0_U__MAX_ITR_LAST_MCS_5___POR 0x0A +#define PHYA_ROBE_MAX_ITER_LST_0_U__MAX_ITR_LAST_MCS_4___POR 0x0A +#define PHYA_ROBE_MAX_ITER_LST_0_U__MAX_ITR_LAST_MCS_7___M 0xFF000000 +#define PHYA_ROBE_MAX_ITER_LST_0_U__MAX_ITR_LAST_MCS_7___S 24 +#define PHYA_ROBE_MAX_ITER_LST_0_U__MAX_ITR_LAST_MCS_6___M 0x00FF0000 +#define PHYA_ROBE_MAX_ITER_LST_0_U__MAX_ITR_LAST_MCS_6___S 16 +#define PHYA_ROBE_MAX_ITER_LST_0_U__MAX_ITR_LAST_MCS_5___M 0x0000FF00 +#define PHYA_ROBE_MAX_ITER_LST_0_U__MAX_ITR_LAST_MCS_5___S 8 +#define PHYA_ROBE_MAX_ITER_LST_0_U__MAX_ITR_LAST_MCS_4___M 0x000000FF +#define PHYA_ROBE_MAX_ITER_LST_0_U__MAX_ITR_LAST_MCS_4___S 0 +#define PHYA_ROBE_MAX_ITER_LST_0_U___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_ITER_LST_0_U___S 0 + +#define PHYA_ROBE_MAX_ITER_LST_1_L (0x004B0388) +#define PHYA_ROBE_MAX_ITER_LST_1_L___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_ITER_LST_1_L___POR 0x0A0A0A0A +#define PHYA_ROBE_MAX_ITER_LST_1_L__MAX_ITR_LAST_MCS_11___POR 0x0A +#define PHYA_ROBE_MAX_ITER_LST_1_L__MAX_ITR_LAST_MCS_10___POR 0x0A +#define PHYA_ROBE_MAX_ITER_LST_1_L__MAX_ITR_LAST_MCS_9___POR 0x0A +#define PHYA_ROBE_MAX_ITER_LST_1_L__MAX_ITR_LAST_MCS_8___POR 0x0A +#define PHYA_ROBE_MAX_ITER_LST_1_L__MAX_ITR_LAST_MCS_11___M 0xFF000000 +#define PHYA_ROBE_MAX_ITER_LST_1_L__MAX_ITR_LAST_MCS_11___S 24 +#define PHYA_ROBE_MAX_ITER_LST_1_L__MAX_ITR_LAST_MCS_10___M 0x00FF0000 +#define PHYA_ROBE_MAX_ITER_LST_1_L__MAX_ITR_LAST_MCS_10___S 16 +#define PHYA_ROBE_MAX_ITER_LST_1_L__MAX_ITR_LAST_MCS_9___M 0x0000FF00 +#define PHYA_ROBE_MAX_ITER_LST_1_L__MAX_ITR_LAST_MCS_9___S 8 +#define PHYA_ROBE_MAX_ITER_LST_1_L__MAX_ITR_LAST_MCS_8___M 0x000000FF +#define PHYA_ROBE_MAX_ITER_LST_1_L__MAX_ITR_LAST_MCS_8___S 0 +#define PHYA_ROBE_MAX_ITER_LST_1_L___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_ITER_LST_1_L___S 0 + +#define PHYA_ROBE_MAX_ITER_LST_1_U (0x004B038C) +#define PHYA_ROBE_MAX_ITER_LST_1_U___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_ITER_LST_1_U___POR 0x0A0A0A0A +#define PHYA_ROBE_MAX_ITER_LST_1_U__MAX_ITR_LAST_MCS_15___POR 0x0A +#define PHYA_ROBE_MAX_ITER_LST_1_U__MAX_ITR_LAST_MCS_14___POR 0x0A +#define PHYA_ROBE_MAX_ITER_LST_1_U__MAX_ITR_LAST_MCS_13___POR 0x0A +#define PHYA_ROBE_MAX_ITER_LST_1_U__MAX_ITR_LAST_MCS_12___POR 0x0A +#define PHYA_ROBE_MAX_ITER_LST_1_U__MAX_ITR_LAST_MCS_15___M 0xFF000000 +#define PHYA_ROBE_MAX_ITER_LST_1_U__MAX_ITR_LAST_MCS_15___S 24 +#define PHYA_ROBE_MAX_ITER_LST_1_U__MAX_ITR_LAST_MCS_14___M 0x00FF0000 +#define PHYA_ROBE_MAX_ITER_LST_1_U__MAX_ITR_LAST_MCS_14___S 16 +#define PHYA_ROBE_MAX_ITER_LST_1_U__MAX_ITR_LAST_MCS_13___M 0x0000FF00 +#define PHYA_ROBE_MAX_ITER_LST_1_U__MAX_ITR_LAST_MCS_13___S 8 +#define PHYA_ROBE_MAX_ITER_LST_1_U__MAX_ITR_LAST_MCS_12___M 0x000000FF +#define PHYA_ROBE_MAX_ITER_LST_1_U__MAX_ITR_LAST_MCS_12___S 0 +#define PHYA_ROBE_MAX_ITER_LST_1_U___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_ITER_LST_1_U___S 0 + +#define PHYA_ROBE_MAX_ITER_LST_2_L (0x004B0390) +#define PHYA_ROBE_MAX_ITER_LST_2_L___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_ITER_LST_2_L___POR 0x01030302 +#define PHYA_ROBE_MAX_ITER_LST_2_L__EARLY_TERM_THR___POR 0x01 +#define PHYA_ROBE_MAX_ITER_LST_2_L__EARLY_TERM_THR_HI___POR 0x03 +#define PHYA_ROBE_MAX_ITER_LST_2_L__THRESH_LO_TPUT_MAX_PKT_BW___POR 0x3 +#define PHYA_ROBE_MAX_ITER_LST_2_L__THRESH_LO_TPUT_MAX_NSS___POR 0x2 +#define PHYA_ROBE_MAX_ITER_LST_2_L__EARLY_TERM_THR___M 0x1F000000 +#define PHYA_ROBE_MAX_ITER_LST_2_L__EARLY_TERM_THR___S 24 +#define PHYA_ROBE_MAX_ITER_LST_2_L__EARLY_TERM_THR_HI___M 0x001F0000 +#define PHYA_ROBE_MAX_ITER_LST_2_L__EARLY_TERM_THR_HI___S 16 +#define PHYA_ROBE_MAX_ITER_LST_2_L__THRESH_LO_TPUT_MAX_PKT_BW___M 0x00000300 +#define PHYA_ROBE_MAX_ITER_LST_2_L__THRESH_LO_TPUT_MAX_PKT_BW___S 8 +#define PHYA_ROBE_MAX_ITER_LST_2_L__THRESH_LO_TPUT_MAX_NSS___M 0x0000000F +#define PHYA_ROBE_MAX_ITER_LST_2_L__THRESH_LO_TPUT_MAX_NSS___S 0 +#define PHYA_ROBE_MAX_ITER_LST_2_L___M 0x1F1F030F +#define PHYA_ROBE_MAX_ITER_LST_2_L___S 0 + +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_L (0x004B0398) +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_L___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_L___POR 0x90489090 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_L__MAX_LAYER_MCS_LO_TPUT_3___POR 0x90 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_L__MAX_LAYER_MCS_LO_TPUT_2___POR 0x48 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_L__MAX_LAYER_MCS_LO_TPUT_1___POR 0x90 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_L__MAX_LAYER_MCS_LO_TPUT_0___POR 0x90 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_L__MAX_LAYER_MCS_LO_TPUT_3___M 0xFF000000 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_L__MAX_LAYER_MCS_LO_TPUT_3___S 24 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_L__MAX_LAYER_MCS_LO_TPUT_2___M 0x00FF0000 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_L__MAX_LAYER_MCS_LO_TPUT_2___S 16 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_L__MAX_LAYER_MCS_LO_TPUT_1___M 0x0000FF00 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_L__MAX_LAYER_MCS_LO_TPUT_1___S 8 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_L__MAX_LAYER_MCS_LO_TPUT_0___M 0x000000FF +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_L__MAX_LAYER_MCS_LO_TPUT_0___S 0 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_L___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_L___S 0 + +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_U (0x004B039C) +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_U___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_U___POR 0x30486048 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_U__MAX_LAYER_MCS_LO_TPUT_7___POR 0x30 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_U__MAX_LAYER_MCS_LO_TPUT_6___POR 0x48 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_U__MAX_LAYER_MCS_LO_TPUT_5___POR 0x60 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_U__MAX_LAYER_MCS_LO_TPUT_4___POR 0x48 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_U__MAX_LAYER_MCS_LO_TPUT_7___M 0xFF000000 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_U__MAX_LAYER_MCS_LO_TPUT_7___S 24 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_U__MAX_LAYER_MCS_LO_TPUT_6___M 0x00FF0000 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_U__MAX_LAYER_MCS_LO_TPUT_6___S 16 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_U__MAX_LAYER_MCS_LO_TPUT_5___M 0x0000FF00 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_U__MAX_LAYER_MCS_LO_TPUT_5___S 8 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_U__MAX_LAYER_MCS_LO_TPUT_4___M 0x000000FF +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_U__MAX_LAYER_MCS_LO_TPUT_4___S 0 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_U___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_0_U___S 0 + +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_L (0x004B03A0) +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_L___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_L___POR 0x30483048 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_L__MAX_LAYER_MCS_LO_TPUT_11___POR 0x30 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_L__MAX_LAYER_MCS_LO_TPUT_10___POR 0x48 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_L__MAX_LAYER_MCS_LO_TPUT_9___POR 0x30 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_L__MAX_LAYER_MCS_LO_TPUT_8___POR 0x48 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_L__MAX_LAYER_MCS_LO_TPUT_11___M 0xFF000000 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_L__MAX_LAYER_MCS_LO_TPUT_11___S 24 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_L__MAX_LAYER_MCS_LO_TPUT_10___M 0x00FF0000 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_L__MAX_LAYER_MCS_LO_TPUT_10___S 16 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_L__MAX_LAYER_MCS_LO_TPUT_9___M 0x0000FF00 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_L__MAX_LAYER_MCS_LO_TPUT_9___S 8 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_L__MAX_LAYER_MCS_LO_TPUT_8___M 0x000000FF +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_L__MAX_LAYER_MCS_LO_TPUT_8___S 0 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_L___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_L___S 0 + +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_U (0x004B03A4) +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_U___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_U___POR 0xFFFF3044 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_U__MAX_LAYER_MCS_LO_TPUT_15___POR 0xFF +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_U__MAX_LAYER_MCS_LO_TPUT_14___POR 0xFF +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_U__MAX_LAYER_MCS_LO_TPUT_13___POR 0x30 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_U__MAX_LAYER_MCS_LO_TPUT_12___POR 0x44 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_U__MAX_LAYER_MCS_LO_TPUT_15___M 0xFF000000 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_U__MAX_LAYER_MCS_LO_TPUT_15___S 24 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_U__MAX_LAYER_MCS_LO_TPUT_14___M 0x00FF0000 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_U__MAX_LAYER_MCS_LO_TPUT_14___S 16 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_U__MAX_LAYER_MCS_LO_TPUT_13___M 0x0000FF00 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_U__MAX_LAYER_MCS_LO_TPUT_13___S 8 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_U__MAX_LAYER_MCS_LO_TPUT_12___M 0x000000FF +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_U__MAX_LAYER_MCS_LO_TPUT_12___S 0 +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_U___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_LAYER_MCS_LO_TPUT_1_U___S 0 + +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_L (0x004B03A8) +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_L___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_L___POR 0x90489090 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_L__MAX_LAYER_MCS_HI_TPUT_3___POR 0x90 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_L__MAX_LAYER_MCS_HI_TPUT_2___POR 0x48 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_L__MAX_LAYER_MCS_HI_TPUT_1___POR 0x90 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_L__MAX_LAYER_MCS_HI_TPUT_0___POR 0x90 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_L__MAX_LAYER_MCS_HI_TPUT_3___M 0xFF000000 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_L__MAX_LAYER_MCS_HI_TPUT_3___S 24 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_L__MAX_LAYER_MCS_HI_TPUT_2___M 0x00FF0000 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_L__MAX_LAYER_MCS_HI_TPUT_2___S 16 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_L__MAX_LAYER_MCS_HI_TPUT_1___M 0x0000FF00 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_L__MAX_LAYER_MCS_HI_TPUT_1___S 8 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_L__MAX_LAYER_MCS_HI_TPUT_0___M 0x000000FF +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_L__MAX_LAYER_MCS_HI_TPUT_0___S 0 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_L___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_L___S 0 + +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_U (0x004B03AC) +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_U___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_U___POR 0x2C425842 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_U__MAX_LAYER_MCS_HI_TPUT_7___POR 0x2C +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_U__MAX_LAYER_MCS_HI_TPUT_6___POR 0x42 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_U__MAX_LAYER_MCS_HI_TPUT_5___POR 0x58 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_U__MAX_LAYER_MCS_HI_TPUT_4___POR 0x42 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_U__MAX_LAYER_MCS_HI_TPUT_7___M 0xFF000000 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_U__MAX_LAYER_MCS_HI_TPUT_7___S 24 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_U__MAX_LAYER_MCS_HI_TPUT_6___M 0x00FF0000 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_U__MAX_LAYER_MCS_HI_TPUT_6___S 16 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_U__MAX_LAYER_MCS_HI_TPUT_5___M 0x0000FF00 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_U__MAX_LAYER_MCS_HI_TPUT_5___S 8 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_U__MAX_LAYER_MCS_HI_TPUT_4___M 0x000000FF +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_U__MAX_LAYER_MCS_HI_TPUT_4___S 0 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_U___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_0_U___S 0 + +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_L (0x004B03B0) +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_L___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_L___POR 0x2B392C42 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_L__MAX_LAYER_MCS_HI_TPUT_11___POR 0x2B +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_L__MAX_LAYER_MCS_HI_TPUT_10___POR 0x39 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_L__MAX_LAYER_MCS_HI_TPUT_9___POR 0x2C +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_L__MAX_LAYER_MCS_HI_TPUT_8___POR 0x42 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_L__MAX_LAYER_MCS_HI_TPUT_11___M 0xFF000000 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_L__MAX_LAYER_MCS_HI_TPUT_11___S 24 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_L__MAX_LAYER_MCS_HI_TPUT_10___M 0x00FF0000 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_L__MAX_LAYER_MCS_HI_TPUT_10___S 16 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_L__MAX_LAYER_MCS_HI_TPUT_9___M 0x0000FF00 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_L__MAX_LAYER_MCS_HI_TPUT_9___S 8 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_L__MAX_LAYER_MCS_HI_TPUT_8___M 0x000000FF +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_L__MAX_LAYER_MCS_HI_TPUT_8___S 0 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_L___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_L___S 0 + +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_U (0x004B03B4) +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_U___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_U___POR 0xFFFF222F +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_U__MAX_LAYER_MCS_HI_TPUT_15___POR 0xFF +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_U__MAX_LAYER_MCS_HI_TPUT_14___POR 0xFF +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_U__MAX_LAYER_MCS_HI_TPUT_13___POR 0x22 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_U__MAX_LAYER_MCS_HI_TPUT_12___POR 0x2F +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_U__MAX_LAYER_MCS_HI_TPUT_15___M 0xFF000000 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_U__MAX_LAYER_MCS_HI_TPUT_15___S 24 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_U__MAX_LAYER_MCS_HI_TPUT_14___M 0x00FF0000 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_U__MAX_LAYER_MCS_HI_TPUT_14___S 16 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_U__MAX_LAYER_MCS_HI_TPUT_13___M 0x0000FF00 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_U__MAX_LAYER_MCS_HI_TPUT_13___S 8 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_U__MAX_LAYER_MCS_HI_TPUT_12___M 0x000000FF +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_U__MAX_LAYER_MCS_HI_TPUT_12___S 0 +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_U___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_LAYER_MCS_HI_TPUT_1_U___S 0 + +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_L (0x004B03B8) +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_L___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_L___POR 0x783C7878 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_L__MAX_LAYER_MCS_LAST_3___POR 0x78 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_L__MAX_LAYER_MCS_LAST_2___POR 0x3C +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_L__MAX_LAYER_MCS_LAST_1___POR 0x78 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_L__MAX_LAYER_MCS_LAST_0___POR 0x78 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_L__MAX_LAYER_MCS_LAST_3___M 0xFF000000 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_L__MAX_LAYER_MCS_LAST_3___S 24 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_L__MAX_LAYER_MCS_LAST_2___M 0x00FF0000 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_L__MAX_LAYER_MCS_LAST_2___S 16 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_L__MAX_LAYER_MCS_LAST_1___M 0x0000FF00 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_L__MAX_LAYER_MCS_LAST_1___S 8 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_L__MAX_LAYER_MCS_LAST_0___M 0x000000FF +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_L__MAX_LAYER_MCS_LAST_0___S 0 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_L___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_L___S 0 + +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_U (0x004B03BC) +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_U___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_U___POR 0x283C503C +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_U__MAX_LAYER_MCS_LAST_7___POR 0x28 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_U__MAX_LAYER_MCS_LAST_6___POR 0x3C +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_U__MAX_LAYER_MCS_LAST_5___POR 0x50 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_U__MAX_LAYER_MCS_LAST_4___POR 0x3C +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_U__MAX_LAYER_MCS_LAST_7___M 0xFF000000 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_U__MAX_LAYER_MCS_LAST_7___S 24 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_U__MAX_LAYER_MCS_LAST_6___M 0x00FF0000 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_U__MAX_LAYER_MCS_LAST_6___S 16 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_U__MAX_LAYER_MCS_LAST_5___M 0x0000FF00 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_U__MAX_LAYER_MCS_LAST_5___S 8 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_U__MAX_LAYER_MCS_LAST_4___M 0x000000FF +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_U__MAX_LAYER_MCS_LAST_4___S 0 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_U___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_0_U___S 0 + +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_L (0x004B03C0) +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_L___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_L___POR 0x283C283C +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_L__MAX_LAYER_MCS_LAST_11___POR 0x28 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_L__MAX_LAYER_MCS_LAST_10___POR 0x3C +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_L__MAX_LAYER_MCS_LAST_9___POR 0x28 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_L__MAX_LAYER_MCS_LAST_8___POR 0x3C +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_L__MAX_LAYER_MCS_LAST_11___M 0xFF000000 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_L__MAX_LAYER_MCS_LAST_11___S 24 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_L__MAX_LAYER_MCS_LAST_10___M 0x00FF0000 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_L__MAX_LAYER_MCS_LAST_10___S 16 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_L__MAX_LAYER_MCS_LAST_9___M 0x0000FF00 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_L__MAX_LAYER_MCS_LAST_9___S 8 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_L__MAX_LAYER_MCS_LAST_8___M 0x000000FF +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_L__MAX_LAYER_MCS_LAST_8___S 0 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_L___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_L___S 0 + +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_U (0x004B03C4) +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_U___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_U___POR 0xFFFF283C +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_U__MAX_LAYER_MCS_LAST_15___POR 0xFF +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_U__MAX_LAYER_MCS_LAST_14___POR 0xFF +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_U__MAX_LAYER_MCS_LAST_13___POR 0x28 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_U__MAX_LAYER_MCS_LAST_12___POR 0x3C +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_U__MAX_LAYER_MCS_LAST_15___M 0xFF000000 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_U__MAX_LAYER_MCS_LAST_15___S 24 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_U__MAX_LAYER_MCS_LAST_14___M 0x00FF0000 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_U__MAX_LAYER_MCS_LAST_14___S 16 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_U__MAX_LAYER_MCS_LAST_13___M 0x0000FF00 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_U__MAX_LAYER_MCS_LAST_13___S 8 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_U__MAX_LAYER_MCS_LAST_12___M 0x000000FF +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_U__MAX_LAYER_MCS_LAST_12___S 0 +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_U___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_LAYER_MCS_LAST_1_U___S 0 + +#define PHYA_ROBE_PRIVATE_SPARE_L (0x004B03C8) +#define PHYA_ROBE_PRIVATE_SPARE_L___RWC QCSR_REG_RW +#define PHYA_ROBE_PRIVATE_SPARE_L___POR 0x00000000 +#define PHYA_ROBE_PRIVATE_SPARE_L__ROBE_PRIVATE_SPARE_0___POR 0x00000000 +#define PHYA_ROBE_PRIVATE_SPARE_L__ROBE_PRIVATE_SPARE_0___M 0xFFFFFFFF +#define PHYA_ROBE_PRIVATE_SPARE_L__ROBE_PRIVATE_SPARE_0___S 0 +#define PHYA_ROBE_PRIVATE_SPARE_L___M 0xFFFFFFFF +#define PHYA_ROBE_PRIVATE_SPARE_L___S 0 + +#define PHYA_ROBE_PRIVATE_SPARE_U (0x004B03CC) +#define PHYA_ROBE_PRIVATE_SPARE_U___RWC QCSR_REG_RW +#define PHYA_ROBE_PRIVATE_SPARE_U___POR 0x00000000 +#define PHYA_ROBE_PRIVATE_SPARE_U__ROBE_PRIVATE_SPARE_1___POR 0x00000000 +#define PHYA_ROBE_PRIVATE_SPARE_U__ROBE_PRIVATE_SPARE_1___M 0xFFFFFFFF +#define PHYA_ROBE_PRIVATE_SPARE_U__ROBE_PRIVATE_SPARE_1___S 0 +#define PHYA_ROBE_PRIVATE_SPARE_U___M 0xFFFFFFFF +#define PHYA_ROBE_PRIVATE_SPARE_U___S 0 + +#define PHYA_ROBE_EARLY_TERMINATE_L (0x004B03D0) +#define PHYA_ROBE_EARLY_TERMINATE_L___RWC QCSR_REG_RW +#define PHYA_ROBE_EARLY_TERMINATE_L___POR 0x00000000 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_31___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_30___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_29___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_28___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_27___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_26___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_25___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_24___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_23___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_22___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_21___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_20___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_19___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_18___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_17___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_16___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_15___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_14___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_13___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_12___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_11___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_10___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_9___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_8___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_7___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_6___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_5___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_4___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_3___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_2___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_1___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_0___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_31___M 0x80000000 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_31___S 31 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_30___M 0x40000000 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_30___S 30 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_29___M 0x20000000 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_29___S 29 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_28___M 0x10000000 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_28___S 28 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_27___M 0x08000000 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_27___S 27 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_26___M 0x04000000 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_26___S 26 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_25___M 0x02000000 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_25___S 25 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_24___M 0x01000000 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_24___S 24 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_23___M 0x00800000 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_23___S 23 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_22___M 0x00400000 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_22___S 22 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_21___M 0x00200000 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_21___S 21 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_20___M 0x00100000 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_20___S 20 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_19___M 0x00080000 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_19___S 19 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_18___M 0x00040000 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_18___S 18 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_17___M 0x00020000 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_17___S 17 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_16___M 0x00010000 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_16___S 16 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_15___M 0x00008000 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_15___S 15 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_14___M 0x00004000 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_14___S 14 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_13___M 0x00002000 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_13___S 13 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_12___M 0x00001000 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_12___S 12 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_11___M 0x00000800 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_11___S 11 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_10___M 0x00000400 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_10___S 10 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_9___M 0x00000200 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_9___S 9 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_8___M 0x00000100 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_8___S 8 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_7___M 0x00000080 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_7___S 7 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_6___M 0x00000040 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_6___S 6 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_5___M 0x00000020 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_5___S 5 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_4___M 0x00000010 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_4___S 4 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_3___M 0x00000008 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_3___S 3 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_2___M 0x00000004 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_2___S 2 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_1___M 0x00000002 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_1___S 1 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_0___M 0x00000001 +#define PHYA_ROBE_EARLY_TERMINATE_L__USER_EARLY_TERMINATION_0___S 0 +#define PHYA_ROBE_EARLY_TERMINATE_L___M 0xFFFFFFFF +#define PHYA_ROBE_EARLY_TERMINATE_L___S 0 + +#define PHYA_ROBE_EARLY_TERMINATE_U (0x004B03D4) +#define PHYA_ROBE_EARLY_TERMINATE_U___RWC QCSR_REG_RW +#define PHYA_ROBE_EARLY_TERMINATE_U___POR 0x00000000 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_63___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_62___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_61___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_60___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_59___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_58___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_57___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_56___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_55___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_54___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_53___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_52___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_51___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_50___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_49___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_48___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_47___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_46___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_45___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_44___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_43___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_42___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_41___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_40___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_39___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_38___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_37___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_36___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_35___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_34___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_33___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_32___POR 0x0 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_63___M 0x80000000 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_63___S 31 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_62___M 0x40000000 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_62___S 30 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_61___M 0x20000000 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_61___S 29 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_60___M 0x10000000 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_60___S 28 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_59___M 0x08000000 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_59___S 27 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_58___M 0x04000000 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_58___S 26 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_57___M 0x02000000 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_57___S 25 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_56___M 0x01000000 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_56___S 24 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_55___M 0x00800000 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_55___S 23 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_54___M 0x00400000 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_54___S 22 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_53___M 0x00200000 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_53___S 21 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_52___M 0x00100000 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_52___S 20 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_51___M 0x00080000 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_51___S 19 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_50___M 0x00040000 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_50___S 18 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_49___M 0x00020000 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_49___S 17 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_48___M 0x00010000 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_48___S 16 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_47___M 0x00008000 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_47___S 15 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_46___M 0x00004000 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_46___S 14 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_45___M 0x00002000 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_45___S 13 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_44___M 0x00001000 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_44___S 12 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_43___M 0x00000800 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_43___S 11 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_42___M 0x00000400 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_42___S 10 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_41___M 0x00000200 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_41___S 9 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_40___M 0x00000100 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_40___S 8 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_39___M 0x00000080 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_39___S 7 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_38___M 0x00000040 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_38___S 6 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_37___M 0x00000020 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_37___S 5 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_36___M 0x00000010 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_36___S 4 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_35___M 0x00000008 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_35___S 3 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_34___M 0x00000004 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_34___S 2 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_33___M 0x00000002 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_33___S 1 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_32___M 0x00000001 +#define PHYA_ROBE_EARLY_TERMINATE_U__USER_EARLY_TERMINATION_32___S 0 +#define PHYA_ROBE_EARLY_TERMINATE_U___M 0xFFFFFFFF +#define PHYA_ROBE_EARLY_TERMINATE_U___S 0 + +#define PHYA_ROBE_NUM_USRS_L (0x004B03D8) +#define PHYA_ROBE_NUM_USRS_L___RWC QCSR_REG_RW +#define PHYA_ROBE_NUM_USRS_L___POR 0x00000000 +#define PHYA_ROBE_NUM_USRS_L__DEPRECATED_DCSR_D___POR 0x00 +#define PHYA_ROBE_NUM_USRS_L__DEPRECATED_DCSR_C___POR 0x00 +#define PHYA_ROBE_NUM_USRS_L__DEPRECATED_DCSR_B___POR 0x00 +#define PHYA_ROBE_NUM_USRS_L__DEPRECATED_DCSR_A___POR 0x00 +#define PHYA_ROBE_NUM_USRS_L__DEPRECATED_DCSR_D___M 0xFF000000 +#define PHYA_ROBE_NUM_USRS_L__DEPRECATED_DCSR_D___S 24 +#define PHYA_ROBE_NUM_USRS_L__DEPRECATED_DCSR_C___M 0x00FF0000 +#define PHYA_ROBE_NUM_USRS_L__DEPRECATED_DCSR_C___S 16 +#define PHYA_ROBE_NUM_USRS_L__DEPRECATED_DCSR_B___M 0x0000FF00 +#define PHYA_ROBE_NUM_USRS_L__DEPRECATED_DCSR_B___S 8 +#define PHYA_ROBE_NUM_USRS_L__DEPRECATED_DCSR_A___M 0x000000FF +#define PHYA_ROBE_NUM_USRS_L__DEPRECATED_DCSR_A___S 0 +#define PHYA_ROBE_NUM_USRS_L___M 0xFFFFFFFF +#define PHYA_ROBE_NUM_USRS_L___S 0 + +#define PHYA_ROBE_NUM_USRS_U (0x004B03DC) +#define PHYA_ROBE_NUM_USRS_U___RWC QCSR_REG_RW +#define PHYA_ROBE_NUM_USRS_U___POR 0x00000000 +#define PHYA_ROBE_NUM_USRS_U__DEPRECATED_DCSR_E___POR 0x00 +#define PHYA_ROBE_NUM_USRS_U__DEPRECATED_DCSR_E___M 0x000000FF +#define PHYA_ROBE_NUM_USRS_U__DEPRECATED_DCSR_E___S 0 +#define PHYA_ROBE_NUM_USRS_U___M 0x000000FF +#define PHYA_ROBE_NUM_USRS_U___S 0 + +#define PHYA_ROBE_DISABLE_DECODERS_L (0x004B03E0) +#define PHYA_ROBE_DISABLE_DECODERS_L___RWC QCSR_REG_RW +#define PHYA_ROBE_DISABLE_DECODERS_L___POR 0x00000000 +#define PHYA_ROBE_DISABLE_DECODERS_L__NUM_DISABLED_LDPC_DEC___POR 0x0 +#define PHYA_ROBE_DISABLE_DECODERS_L__NUM_DISABLED_VIT_DEC___POR 0x0 +#define PHYA_ROBE_DISABLE_DECODERS_L__NUM_DISABLED_LDPC_DEC___M 0x00000F00 +#define PHYA_ROBE_DISABLE_DECODERS_L__NUM_DISABLED_LDPC_DEC___S 8 +#define PHYA_ROBE_DISABLE_DECODERS_L__NUM_DISABLED_VIT_DEC___M 0x0000000F +#define PHYA_ROBE_DISABLE_DECODERS_L__NUM_DISABLED_VIT_DEC___S 0 +#define PHYA_ROBE_DISABLE_DECODERS_L___M 0x00000F0F +#define PHYA_ROBE_DISABLE_DECODERS_L___S 0 + +#define PHYA_ROBE_USR_TAB_RDY_L (0x004B03E8) +#define PHYA_ROBE_USR_TAB_RDY_L___RWC QCSR_REG_RW +#define PHYA_ROBE_USR_TAB_RDY_L___POR 0x00000000 +#define PHYA_ROBE_USR_TAB_RDY_L__USR_TAB_RDY___POR 0x0 +#define PHYA_ROBE_USR_TAB_RDY_L__USR_TAB_RDY___M 0x00000001 +#define PHYA_ROBE_USR_TAB_RDY_L__USR_TAB_RDY___S 0 +#define PHYA_ROBE_USR_TAB_RDY_L___M 0x00000001 +#define PHYA_ROBE_USR_TAB_RDY_L___S 0 + +#define PHYA_ROBE_ROBE_EN_L (0x004B03F0) +#define PHYA_ROBE_ROBE_EN_L___RWC QCSR_REG_RW +#define PHYA_ROBE_ROBE_EN_L___POR 0x00000000 +#define PHYA_ROBE_ROBE_EN_L__ROBE_EN___POR 0x0 +#define PHYA_ROBE_ROBE_EN_L__ROBE_EN___M 0x00000001 +#define PHYA_ROBE_ROBE_EN_L__ROBE_EN___S 0 +#define PHYA_ROBE_ROBE_EN_L___M 0x00000001 +#define PHYA_ROBE_ROBE_EN_L___S 0 + +#define PHYA_ROBE_FW_INITIATED_SPARE_L (0x004B03F8) +#define PHYA_ROBE_FW_INITIATED_SPARE_L___RWC QCSR_REG_RW +#define PHYA_ROBE_FW_INITIATED_SPARE_L___POR 0x00000000 +#define PHYA_ROBE_FW_INITIATED_SPARE_L__PKT_START_SPARE_0___POR 0x00000000 +#define PHYA_ROBE_FW_INITIATED_SPARE_L__PKT_START_SPARE_0___M 0xFFFFFFFF +#define PHYA_ROBE_FW_INITIATED_SPARE_L__PKT_START_SPARE_0___S 0 +#define PHYA_ROBE_FW_INITIATED_SPARE_L___M 0xFFFFFFFF +#define PHYA_ROBE_FW_INITIATED_SPARE_L___S 0 + +#define PHYA_ROBE_FW_INITIATED_SPARE_U (0x004B03FC) +#define PHYA_ROBE_FW_INITIATED_SPARE_U___RWC QCSR_REG_RW +#define PHYA_ROBE_FW_INITIATED_SPARE_U___POR 0x00000000 +#define PHYA_ROBE_FW_INITIATED_SPARE_U__PKT_START_SPARE_1___POR 0x00000000 +#define PHYA_ROBE_FW_INITIATED_SPARE_U__PKT_START_SPARE_1___M 0xFFFFFFFF +#define PHYA_ROBE_FW_INITIATED_SPARE_U__PKT_START_SPARE_1___S 0 +#define PHYA_ROBE_FW_INITIATED_SPARE_U___M 0xFFFFFFFF +#define PHYA_ROBE_FW_INITIATED_SPARE_U___S 0 + +#define PHYA_ROBE_SIG_DEC_RD_L (0x004B0400) +#define PHYA_ROBE_SIG_DEC_RD_L___RWC QCSR_REG_RO +#define PHYA_ROBE_SIG_DEC_RD_L___POR 0x00000000 +#define PHYA_ROBE_SIG_DEC_RD_L__SIG_FIELD_0___POR 0x00000000 +#define PHYA_ROBE_SIG_DEC_RD_L__SIG_FIELD_0___M 0xFFFFFFFF +#define PHYA_ROBE_SIG_DEC_RD_L__SIG_FIELD_0___S 0 +#define PHYA_ROBE_SIG_DEC_RD_L___M 0xFFFFFFFF +#define PHYA_ROBE_SIG_DEC_RD_L___S 0 + +#define PHYA_ROBE_SIG_DEC_RD_U (0x004B0404) +#define PHYA_ROBE_SIG_DEC_RD_U___RWC QCSR_REG_RO +#define PHYA_ROBE_SIG_DEC_RD_U___POR 0x00000000 +#define PHYA_ROBE_SIG_DEC_RD_U__SIG_FIELD_1___POR 0x00000000 +#define PHYA_ROBE_SIG_DEC_RD_U__SIG_FIELD_1___M 0xFFFFFFFF +#define PHYA_ROBE_SIG_DEC_RD_U__SIG_FIELD_1___S 0 +#define PHYA_ROBE_SIG_DEC_RD_U___M 0xFFFFFFFF +#define PHYA_ROBE_SIG_DEC_RD_U___S 0 + +#define PHYA_ROBE_SIG_DEC_SPARE_L (0x004B0408) +#define PHYA_ROBE_SIG_DEC_SPARE_L___RWC QCSR_REG_RW +#define PHYA_ROBE_SIG_DEC_SPARE_L___POR 0x00000000 +#define PHYA_ROBE_SIG_DEC_SPARE_L__SIG_DEC_SPARE_0___POR 0x00000000 +#define PHYA_ROBE_SIG_DEC_SPARE_L__SIG_DEC_SPARE_0___M 0xFFFFFFFF +#define PHYA_ROBE_SIG_DEC_SPARE_L__SIG_DEC_SPARE_0___S 0 +#define PHYA_ROBE_SIG_DEC_SPARE_L___M 0xFFFFFFFF +#define PHYA_ROBE_SIG_DEC_SPARE_L___S 0 + +#define PHYA_ROBE_SIG_DEC_SPARE_U (0x004B040C) +#define PHYA_ROBE_SIG_DEC_SPARE_U___RWC QCSR_REG_RW +#define PHYA_ROBE_SIG_DEC_SPARE_U___POR 0x00000000 +#define PHYA_ROBE_SIG_DEC_SPARE_U__SIG_DEC_SPARE_1___POR 0x00000000 +#define PHYA_ROBE_SIG_DEC_SPARE_U__SIG_DEC_SPARE_1___M 0xFFFFFFFF +#define PHYA_ROBE_SIG_DEC_SPARE_U__SIG_DEC_SPARE_1___S 0 +#define PHYA_ROBE_SIG_DEC_SPARE_U___M 0xFFFFFFFF +#define PHYA_ROBE_SIG_DEC_SPARE_U___S 0 + +#define PHYA_ROBE_SIG_EXT_DEC_RD_L (0x004B0410) +#define PHYA_ROBE_SIG_EXT_DEC_RD_L___RWC QCSR_REG_RO +#define PHYA_ROBE_SIG_EXT_DEC_RD_L___POR 0x00000000 +#define PHYA_ROBE_SIG_EXT_DEC_RD_L__SIG_FIELD_EXT_0___POR 0x00000000 +#define PHYA_ROBE_SIG_EXT_DEC_RD_L__SIG_FIELD_EXT_0___M 0xFFFFFFFF +#define PHYA_ROBE_SIG_EXT_DEC_RD_L__SIG_FIELD_EXT_0___S 0 +#define PHYA_ROBE_SIG_EXT_DEC_RD_L___M 0xFFFFFFFF +#define PHYA_ROBE_SIG_EXT_DEC_RD_L___S 0 + +#define PHYA_ROBE_SIG_EXT_DEC_RD_U (0x004B0414) +#define PHYA_ROBE_SIG_EXT_DEC_RD_U___RWC QCSR_REG_RO +#define PHYA_ROBE_SIG_EXT_DEC_RD_U___POR 0x00000000 +#define PHYA_ROBE_SIG_EXT_DEC_RD_U__SIG_FIELD_EXT_1___POR 0x00000000 +#define PHYA_ROBE_SIG_EXT_DEC_RD_U__SIG_FIELD_EXT_1___M 0xFFFFFFFF +#define PHYA_ROBE_SIG_EXT_DEC_RD_U__SIG_FIELD_EXT_1___S 0 +#define PHYA_ROBE_SIG_EXT_DEC_RD_U___M 0xFFFFFFFF +#define PHYA_ROBE_SIG_EXT_DEC_RD_U___S 0 + +#define PHYA_ROBE_SIG_EXT_DEC_SPARE_L (0x004B0418) +#define PHYA_ROBE_SIG_EXT_DEC_SPARE_L___RWC QCSR_REG_RW +#define PHYA_ROBE_SIG_EXT_DEC_SPARE_L___POR 0x00000000 +#define PHYA_ROBE_SIG_EXT_DEC_SPARE_L__SIG_EXT_DEC_SPARE_0___POR 0x00000000 +#define PHYA_ROBE_SIG_EXT_DEC_SPARE_L__SIG_EXT_DEC_SPARE_0___M 0xFFFFFFFF +#define PHYA_ROBE_SIG_EXT_DEC_SPARE_L__SIG_EXT_DEC_SPARE_0___S 0 +#define PHYA_ROBE_SIG_EXT_DEC_SPARE_L___M 0xFFFFFFFF +#define PHYA_ROBE_SIG_EXT_DEC_SPARE_L___S 0 + +#define PHYA_ROBE_SIG_EXT_DEC_SPARE_U (0x004B041C) +#define PHYA_ROBE_SIG_EXT_DEC_SPARE_U___RWC QCSR_REG_RW +#define PHYA_ROBE_SIG_EXT_DEC_SPARE_U___POR 0x00000000 +#define PHYA_ROBE_SIG_EXT_DEC_SPARE_U__SIG_EXT_DEC_SPARE_1___POR 0x00000000 +#define PHYA_ROBE_SIG_EXT_DEC_SPARE_U__SIG_EXT_DEC_SPARE_1___M 0xFFFFFFFF +#define PHYA_ROBE_SIG_EXT_DEC_SPARE_U__SIG_EXT_DEC_SPARE_1___S 0 +#define PHYA_ROBE_SIG_EXT_DEC_SPARE_U___M 0xFFFFFFFF +#define PHYA_ROBE_SIG_EXT_DEC_SPARE_U___S 0 + +#define PHYA_ROBE_PKT_CONTROL_L (0x004B0420) +#define PHYA_ROBE_PKT_CONTROL_L___RWC QCSR_REG_RW +#define PHYA_ROBE_PKT_CONTROL_L___POR 0x00000001 +#define PHYA_ROBE_PKT_CONTROL_L__DSRC_ON___POR 0x0 +#define PHYA_ROBE_PKT_CONTROL_L__IS_11AC_DLMU___POR 0x0 +#define PHYA_ROBE_PKT_CONTROL_L__PKT_BW___POR 0x0 +#define PHYA_ROBE_PKT_CONTROL_L__IS_SU___POR 0x1 +#define PHYA_ROBE_PKT_CONTROL_L__DSRC_ON___M 0x01000000 +#define PHYA_ROBE_PKT_CONTROL_L__DSRC_ON___S 24 +#define PHYA_ROBE_PKT_CONTROL_L__IS_11AC_DLMU___M 0x00010000 +#define PHYA_ROBE_PKT_CONTROL_L__IS_11AC_DLMU___S 16 +#define PHYA_ROBE_PKT_CONTROL_L__PKT_BW___M 0x00000300 +#define PHYA_ROBE_PKT_CONTROL_L__PKT_BW___S 8 +#define PHYA_ROBE_PKT_CONTROL_L__IS_SU___M 0x00000001 +#define PHYA_ROBE_PKT_CONTROL_L__IS_SU___S 0 +#define PHYA_ROBE_PKT_CONTROL_L___M 0x01010301 +#define PHYA_ROBE_PKT_CONTROL_L___S 0 + +#define PHYA_ROBE_PKT_CONTROL_U (0x004B0424) +#define PHYA_ROBE_PKT_CONTROL_U___RWC QCSR_REG_RW +#define PHYA_ROBE_PKT_CONTROL_U___POR 0x00000000 +#define PHYA_ROBE_PKT_CONTROL_U__REDUCED_ITER_N_CW___POR 0x0 +#define PHYA_ROBE_PKT_CONTROL_U__MU_LAST_SYM_PAD_ALPHA___POR 0x0 +#define PHYA_ROBE_PKT_CONTROL_U__USE_SPECIAL_PKT_ITER_TBL___POR 0x0 +#define PHYA_ROBE_PKT_CONTROL_U__DISABLE_BW160_PKT_PARAM_DCSR___POR 0x0 +#define PHYA_ROBE_PKT_CONTROL_U__REDUCED_ITER_N_CW___M 0x0F000000 +#define PHYA_ROBE_PKT_CONTROL_U__REDUCED_ITER_N_CW___S 24 +#define PHYA_ROBE_PKT_CONTROL_U__MU_LAST_SYM_PAD_ALPHA___M 0x00030000 +#define PHYA_ROBE_PKT_CONTROL_U__MU_LAST_SYM_PAD_ALPHA___S 16 +#define PHYA_ROBE_PKT_CONTROL_U__USE_SPECIAL_PKT_ITER_TBL___M 0x00000100 +#define PHYA_ROBE_PKT_CONTROL_U__USE_SPECIAL_PKT_ITER_TBL___S 8 +#define PHYA_ROBE_PKT_CONTROL_U__DISABLE_BW160_PKT_PARAM_DCSR___M 0x00000001 +#define PHYA_ROBE_PKT_CONTROL_U__DISABLE_BW160_PKT_PARAM_DCSR___S 0 +#define PHYA_ROBE_PKT_CONTROL_U___M 0x0F030101 +#define PHYA_ROBE_PKT_CONTROL_U___S 0 + +#define PHYA_ROBE_PKT_CONTROL_LEGACY_L (0x004B0428) +#define PHYA_ROBE_PKT_CONTROL_LEGACY_L___RWC QCSR_REG_RW +#define PHYA_ROBE_PKT_CONTROL_LEGACY_L___POR 0x00000000 +#define PHYA_ROBE_PKT_CONTROL_LEGACY_L__DEPRECATED_DCSR_H___POR 0x0 +#define PHYA_ROBE_PKT_CONTROL_LEGACY_L__DEPRECATED_DCSR_G___POR 0x0 +#define PHYA_ROBE_PKT_CONTROL_LEGACY_L__DEPRECATED_DCSR_F___POR 0x0 +#define PHYA_ROBE_PKT_CONTROL_LEGACY_L__DEPRECATED_DCSR_H___M 0x00070000 +#define PHYA_ROBE_PKT_CONTROL_LEGACY_L__DEPRECATED_DCSR_H___S 16 +#define PHYA_ROBE_PKT_CONTROL_LEGACY_L__DEPRECATED_DCSR_G___M 0x00000100 +#define PHYA_ROBE_PKT_CONTROL_LEGACY_L__DEPRECATED_DCSR_G___S 8 +#define PHYA_ROBE_PKT_CONTROL_LEGACY_L__DEPRECATED_DCSR_F___M 0x00000007 +#define PHYA_ROBE_PKT_CONTROL_LEGACY_L__DEPRECATED_DCSR_F___S 0 +#define PHYA_ROBE_PKT_CONTROL_LEGACY_L___M 0x00070107 +#define PHYA_ROBE_PKT_CONTROL_LEGACY_L___S 0 + +#define PHYA_ROBE_LSIG_REL_L (0x004B0430) +#define PHYA_ROBE_LSIG_REL_L___RWC QCSR_REG_RW +#define PHYA_ROBE_LSIG_REL_L___POR 0x00060005 +#define PHYA_ROBE_LSIG_REL_L__LSIG_MIN_S0_63_DIFF_THR___POR 0x006 +#define PHYA_ROBE_LSIG_REL_L__LSIG_MAX_S0_THR___POR 0x05 +#define PHYA_ROBE_LSIG_REL_L__LSIG_MIN_S0_63_DIFF_THR___M 0x07FF0000 +#define PHYA_ROBE_LSIG_REL_L__LSIG_MIN_S0_63_DIFF_THR___S 16 +#define PHYA_ROBE_LSIG_REL_L__LSIG_MAX_S0_THR___M 0x000000FF +#define PHYA_ROBE_LSIG_REL_L__LSIG_MAX_S0_THR___S 0 +#define PHYA_ROBE_LSIG_REL_L___M 0x07FF00FF +#define PHYA_ROBE_LSIG_REL_L___S 0 + +#define PHYA_ROBE_LSIG_REL_U (0x004B0434) +#define PHYA_ROBE_LSIG_REL_U___RWC QCSR_REG_RW +#define PHYA_ROBE_LSIG_REL_U___POR 0x00000006 +#define PHYA_ROBE_LSIG_REL_U__LSIG_LLR_ABS_SUM_THR___POR 0x06 +#define PHYA_ROBE_LSIG_REL_U__LSIG_LLR_ABS_SUM_THR___M 0x000000FF +#define PHYA_ROBE_LSIG_REL_U__LSIG_LLR_ABS_SUM_THR___S 0 +#define PHYA_ROBE_LSIG_REL_U___M 0x000000FF +#define PHYA_ROBE_LSIG_REL_U___S 0 + +#define PHYA_ROBE_SU_CONTROL_0_L (0x004B0438) +#define PHYA_ROBE_SU_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_ROBE_SU_CONTROL_0_L___POR 0x00000030 +#define PHYA_ROBE_SU_CONTROL_0_L__SU_MCS___POR 0x0 +#define PHYA_ROBE_SU_CONTROL_0_L__SU_ADV_CODING___POR 0x0 +#define PHYA_ROBE_SU_CONTROL_0_L__SU_N_SC___POR 0x030 +#define PHYA_ROBE_SU_CONTROL_0_L__SU_MCS___M 0x0F000000 +#define PHYA_ROBE_SU_CONTROL_0_L__SU_MCS___S 24 +#define PHYA_ROBE_SU_CONTROL_0_L__SU_ADV_CODING___M 0x00010000 +#define PHYA_ROBE_SU_CONTROL_0_L__SU_ADV_CODING___S 16 +#define PHYA_ROBE_SU_CONTROL_0_L__SU_N_SC___M 0x000007FF +#define PHYA_ROBE_SU_CONTROL_0_L__SU_N_SC___S 0 +#define PHYA_ROBE_SU_CONTROL_0_L___M 0x0F0107FF +#define PHYA_ROBE_SU_CONTROL_0_L___S 0 + +#define PHYA_ROBE_SU_CONTROL_0_U (0x004B043C) +#define PHYA_ROBE_SU_CONTROL_0_U___RWC QCSR_REG_RW +#define PHYA_ROBE_SU_CONTROL_0_U___POR 0x1001010B +#define PHYA_ROBE_SU_CONTROL_0_U__SU_NCOL___POR 0x10 +#define PHYA_ROBE_SU_CONTROL_0_U__SU_NES___POR 0x1 +#define PHYA_ROBE_SU_CONTROL_0_U__SU_NSS___POR 0x1 +#define PHYA_ROBE_SU_CONTROL_0_U__SU_RATE_11A___POR 0xB +#define PHYA_ROBE_SU_CONTROL_0_U__SU_NCOL___M 0x3F000000 +#define PHYA_ROBE_SU_CONTROL_0_U__SU_NCOL___S 24 +#define PHYA_ROBE_SU_CONTROL_0_U__SU_NES___M 0x000F0000 +#define PHYA_ROBE_SU_CONTROL_0_U__SU_NES___S 16 +#define PHYA_ROBE_SU_CONTROL_0_U__SU_NSS___M 0x00000F00 +#define PHYA_ROBE_SU_CONTROL_0_U__SU_NSS___S 8 +#define PHYA_ROBE_SU_CONTROL_0_U__SU_RATE_11A___M 0x0000000F +#define PHYA_ROBE_SU_CONTROL_0_U__SU_RATE_11A___S 0 +#define PHYA_ROBE_SU_CONTROL_0_U___M 0x3F0F0F0F +#define PHYA_ROBE_SU_CONTROL_0_U___S 0 + +#define PHYA_ROBE_SU_CONTROL_1_L (0x004B0440) +#define PHYA_ROBE_SU_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_ROBE_SU_CONTROL_1_L___POR 0x00010003 +#define PHYA_ROBE_SU_CONTROL_1_L__SU_IS_DCM___POR 0x0 +#define PHYA_ROBE_SU_CONTROL_1_L__SU_NCBPSC___POR 0x1 +#define PHYA_ROBE_SU_CONTROL_1_L__SU_CODE_RATE___POR 0x0 +#define PHYA_ROBE_SU_CONTROL_1_L__SU_NROW___POR 0x03 +#define PHYA_ROBE_SU_CONTROL_1_L__SU_IS_DCM___M 0x01000000 +#define PHYA_ROBE_SU_CONTROL_1_L__SU_IS_DCM___S 24 +#define PHYA_ROBE_SU_CONTROL_1_L__SU_NCBPSC___M 0x000F0000 +#define PHYA_ROBE_SU_CONTROL_1_L__SU_NCBPSC___S 16 +#define PHYA_ROBE_SU_CONTROL_1_L__SU_CODE_RATE___M 0x00000700 +#define PHYA_ROBE_SU_CONTROL_1_L__SU_CODE_RATE___S 8 +#define PHYA_ROBE_SU_CONTROL_1_L__SU_NROW___M 0x0000001F +#define PHYA_ROBE_SU_CONTROL_1_L__SU_NROW___S 0 +#define PHYA_ROBE_SU_CONTROL_1_L___M 0x010F071F +#define PHYA_ROBE_SU_CONTROL_1_L___S 0 + +#define PHYA_ROBE_SU_CONTROL_1_U (0x004B0444) +#define PHYA_ROBE_SU_CONTROL_1_U___RWC QCSR_REG_RW +#define PHYA_ROBE_SU_CONTROL_1_U___POR 0x00000000 +#define PHYA_ROBE_SU_CONTROL_1_U__SU_DROP_LAST_LLR___POR 0x0 +#define PHYA_ROBE_SU_CONTROL_1_U__SU_DROP_LAST_LLR___M 0x00000001 +#define PHYA_ROBE_SU_CONTROL_1_U__SU_DROP_LAST_LLR___S 0 +#define PHYA_ROBE_SU_CONTROL_1_U___M 0x00000001 +#define PHYA_ROBE_SU_CONTROL_1_U___S 0 + +#define PHYA_ROBE_SU_CONTROL_2_L (0x004B0448) +#define PHYA_ROBE_SU_CONTROL_2_L___RWC QCSR_REG_RW +#define PHYA_ROBE_SU_CONTROL_2_L___POR 0x00000000 +#define PHYA_ROBE_SU_CONTROL_2_L__SU_NUM_DECODED_BITS___POR 0x0000000 +#define PHYA_ROBE_SU_CONTROL_2_L__SU_NUM_DECODED_BITS___M 0x03FFFFFF +#define PHYA_ROBE_SU_CONTROL_2_L__SU_NUM_DECODED_BITS___S 0 +#define PHYA_ROBE_SU_CONTROL_2_L___M 0x03FFFFFF +#define PHYA_ROBE_SU_CONTROL_2_L___S 0 + +#define PHYA_ROBE_SU_CONTROL_2_U (0x004B044C) +#define PHYA_ROBE_SU_CONTROL_2_U___RWC QCSR_REG_RW +#define PHYA_ROBE_SU_CONTROL_2_U___POR 0x00800000 +#define PHYA_ROBE_SU_CONTROL_2_U__HDR_FLUSH_SIZE___POR 0x80 +#define PHYA_ROBE_SU_CONTROL_2_U__SU_LAST_SYM_NUM_CODED_BITS___POR 0x0000 +#define PHYA_ROBE_SU_CONTROL_2_U__HDR_FLUSH_SIZE___M 0x00FF0000 +#define PHYA_ROBE_SU_CONTROL_2_U__HDR_FLUSH_SIZE___S 16 +#define PHYA_ROBE_SU_CONTROL_2_U__SU_LAST_SYM_NUM_CODED_BITS___M 0x00007FFF +#define PHYA_ROBE_SU_CONTROL_2_U__SU_LAST_SYM_NUM_CODED_BITS___S 0 +#define PHYA_ROBE_SU_CONTROL_2_U___M 0x00FF7FFF +#define PHYA_ROBE_SU_CONTROL_2_U___S 0 + +#define PHYA_ROBE_SU_LDPC_CONTROL_0_L (0x004B0450) +#define PHYA_ROBE_SU_LDPC_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_ROBE_SU_LDPC_CONTROL_0_L___POR 0x00000000 +#define PHYA_ROBE_SU_LDPC_CONTROL_0_L__SU_LDPC_N_SHT_PLUS1___POR 0x0000 +#define PHYA_ROBE_SU_LDPC_CONTROL_0_L__SU_LDPC_CODE_LEN___POR 0x0 +#define PHYA_ROBE_SU_LDPC_CONTROL_0_L__SU_LDPC_PUNC___POR 0x0 +#define PHYA_ROBE_SU_LDPC_CONTROL_0_L__SU_LDPC_N_SHT_PLUS1___M 0xFFFF0000 +#define PHYA_ROBE_SU_LDPC_CONTROL_0_L__SU_LDPC_N_SHT_PLUS1___S 16 +#define PHYA_ROBE_SU_LDPC_CONTROL_0_L__SU_LDPC_CODE_LEN___M 0x00000300 +#define PHYA_ROBE_SU_LDPC_CONTROL_0_L__SU_LDPC_CODE_LEN___S 8 +#define PHYA_ROBE_SU_LDPC_CONTROL_0_L__SU_LDPC_PUNC___M 0x00000001 +#define PHYA_ROBE_SU_LDPC_CONTROL_0_L__SU_LDPC_PUNC___S 0 +#define PHYA_ROBE_SU_LDPC_CONTROL_0_L___M 0xFFFF0301 +#define PHYA_ROBE_SU_LDPC_CONTROL_0_L___S 0 + +#define PHYA_ROBE_SU_LDPC_CONTROL_0_U (0x004B0454) +#define PHYA_ROBE_SU_LDPC_CONTROL_0_U___RWC QCSR_REG_RW +#define PHYA_ROBE_SU_LDPC_CONTROL_0_U___POR 0x00000000 +#define PHYA_ROBE_SU_LDPC_CONTROL_0_U__SU_LDPC_N_PRP_PLUS1___POR 0x0000 +#define PHYA_ROBE_SU_LDPC_CONTROL_0_U__SU_LDPC_N_CW___POR 0x0000 +#define PHYA_ROBE_SU_LDPC_CONTROL_0_U__SU_LDPC_N_PRP_PLUS1___M 0xFFFF0000 +#define PHYA_ROBE_SU_LDPC_CONTROL_0_U__SU_LDPC_N_PRP_PLUS1___S 16 +#define PHYA_ROBE_SU_LDPC_CONTROL_0_U__SU_LDPC_N_CW___M 0x0000FFFF +#define PHYA_ROBE_SU_LDPC_CONTROL_0_U__SU_LDPC_N_CW___S 0 +#define PHYA_ROBE_SU_LDPC_CONTROL_0_U___M 0xFFFFFFFF +#define PHYA_ROBE_SU_LDPC_CONTROL_0_U___S 0 + +#define PHYA_ROBE_SU_LDPC_CONTROL_1_L (0x004B0458) +#define PHYA_ROBE_SU_LDPC_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_ROBE_SU_LDPC_CONTROL_1_L___POR 0x00000000 +#define PHYA_ROBE_SU_LDPC_CONTROL_1_L__SU_LDPC_N_PRPCW___POR 0x0000 +#define PHYA_ROBE_SU_LDPC_CONTROL_1_L__SU_LDPC_N_SPCW___POR 0x000 +#define PHYA_ROBE_SU_LDPC_CONTROL_1_L__SU_LDPC_N_PRPCW___M 0xFFFF0000 +#define PHYA_ROBE_SU_LDPC_CONTROL_1_L__SU_LDPC_N_PRPCW___S 16 +#define PHYA_ROBE_SU_LDPC_CONTROL_1_L__SU_LDPC_N_SPCW___M 0x000007FF +#define PHYA_ROBE_SU_LDPC_CONTROL_1_L__SU_LDPC_N_SPCW___S 0 +#define PHYA_ROBE_SU_LDPC_CONTROL_1_L___M 0xFFFF07FF +#define PHYA_ROBE_SU_LDPC_CONTROL_1_L___S 0 + +#define PHYA_ROBE_HESIGB_CONTROL_0_L (0x004B0460) +#define PHYA_ROBE_HESIGB_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_ROBE_HESIGB_CONTROL_0_L___POR 0x001F3412 +#define PHYA_ROBE_HESIGB_CONTROL_0_L__DEPRECATED_DCSR_I___POR 0x00 +#define PHYA_ROBE_HESIGB_CONTROL_0_L__HESIGB_1USR_FLUSH_SZ___POR 0x1F +#define PHYA_ROBE_HESIGB_CONTROL_0_L__HESIGB_2USR_FLUSH_SZ___POR 0x34 +#define PHYA_ROBE_HESIGB_CONTROL_0_L__HESIGB_CMN_FLUSH_SZ___POR 0x12 +#define PHYA_ROBE_HESIGB_CONTROL_0_L__DEPRECATED_DCSR_I___M 0x1F000000 +#define PHYA_ROBE_HESIGB_CONTROL_0_L__DEPRECATED_DCSR_I___S 24 +#define PHYA_ROBE_HESIGB_CONTROL_0_L__HESIGB_1USR_FLUSH_SZ___M 0x00FF0000 +#define PHYA_ROBE_HESIGB_CONTROL_0_L__HESIGB_1USR_FLUSH_SZ___S 16 +#define PHYA_ROBE_HESIGB_CONTROL_0_L__HESIGB_2USR_FLUSH_SZ___M 0x0000FF00 +#define PHYA_ROBE_HESIGB_CONTROL_0_L__HESIGB_2USR_FLUSH_SZ___S 8 +#define PHYA_ROBE_HESIGB_CONTROL_0_L__HESIGB_CMN_FLUSH_SZ___M 0x000000FF +#define PHYA_ROBE_HESIGB_CONTROL_0_L__HESIGB_CMN_FLUSH_SZ___S 0 +#define PHYA_ROBE_HESIGB_CONTROL_0_L___M 0x1FFFFFFF +#define PHYA_ROBE_HESIGB_CONTROL_0_L___S 0 + +#define PHYA_ROBE_HESIGB_CONTROL_0_U (0x004B0464) +#define PHYA_ROBE_HESIGB_CONTROL_0_U___RWC QCSR_REG_RW +#define PHYA_ROBE_HESIGB_CONTROL_0_U___POR 0x00010101 +#define PHYA_ROBE_HESIGB_CONTROL_0_U__HESIGB_NUM_CMN_BAND1___POR 0x00 +#define PHYA_ROBE_HESIGB_CONTROL_0_U__HESIGB_NUM_1USR_BAND0___POR 0x01 +#define PHYA_ROBE_HESIGB_CONTROL_0_U__HESIGB_NUM_2USR_BAND0___POR 0x01 +#define PHYA_ROBE_HESIGB_CONTROL_0_U__HESIGB_NUM_CMN_BAND0___POR 0x01 +#define PHYA_ROBE_HESIGB_CONTROL_0_U__HESIGB_NUM_CMN_BAND1___M 0xFF000000 +#define PHYA_ROBE_HESIGB_CONTROL_0_U__HESIGB_NUM_CMN_BAND1___S 24 +#define PHYA_ROBE_HESIGB_CONTROL_0_U__HESIGB_NUM_1USR_BAND0___M 0x00FF0000 +#define PHYA_ROBE_HESIGB_CONTROL_0_U__HESIGB_NUM_1USR_BAND0___S 16 +#define PHYA_ROBE_HESIGB_CONTROL_0_U__HESIGB_NUM_2USR_BAND0___M 0x0000FF00 +#define PHYA_ROBE_HESIGB_CONTROL_0_U__HESIGB_NUM_2USR_BAND0___S 8 +#define PHYA_ROBE_HESIGB_CONTROL_0_U__HESIGB_NUM_CMN_BAND0___M 0x000000FF +#define PHYA_ROBE_HESIGB_CONTROL_0_U__HESIGB_NUM_CMN_BAND0___S 0 +#define PHYA_ROBE_HESIGB_CONTROL_0_U___M 0xFFFFFFFF +#define PHYA_ROBE_HESIGB_CONTROL_0_U___S 0 + +#define PHYA_ROBE_HESIGB_CONTROL_1_L (0x004B0468) +#define PHYA_ROBE_HESIGB_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_ROBE_HESIGB_CONTROL_1_L___POR 0x00000000 +#define PHYA_ROBE_HESIGB_CONTROL_1_L__HESIGB_IS_DCM___POR 0x0 +#define PHYA_ROBE_HESIGB_CONTROL_1_L__HESIGB_NUM_1USR_BAND1___POR 0x00 +#define PHYA_ROBE_HESIGB_CONTROL_1_L__HESIGB_NUM_2USR_BAND1___POR 0x00 +#define PHYA_ROBE_HESIGB_CONTROL_1_L__HESIGB_IS_DCM___M 0x00010000 +#define PHYA_ROBE_HESIGB_CONTROL_1_L__HESIGB_IS_DCM___S 16 +#define PHYA_ROBE_HESIGB_CONTROL_1_L__HESIGB_NUM_1USR_BAND1___M 0x0000FF00 +#define PHYA_ROBE_HESIGB_CONTROL_1_L__HESIGB_NUM_1USR_BAND1___S 8 +#define PHYA_ROBE_HESIGB_CONTROL_1_L__HESIGB_NUM_2USR_BAND1___M 0x000000FF +#define PHYA_ROBE_HESIGB_CONTROL_1_L__HESIGB_NUM_2USR_BAND1___S 0 +#define PHYA_ROBE_HESIGB_CONTROL_1_L___M 0x0001FFFF +#define PHYA_ROBE_HESIGB_CONTROL_1_L___S 0 + +#define PHYA_ROBE_DCSR_LATCH_SPARE_L (0x004B0470) +#define PHYA_ROBE_DCSR_LATCH_SPARE_L___RWC QCSR_REG_RW +#define PHYA_ROBE_DCSR_LATCH_SPARE_L___POR 0x00000000 +#define PHYA_ROBE_DCSR_LATCH_SPARE_L__DCSR_LATCH_SPARE_0___POR 0x00000000 +#define PHYA_ROBE_DCSR_LATCH_SPARE_L__DCSR_LATCH_SPARE_0___M 0xFFFFFFFF +#define PHYA_ROBE_DCSR_LATCH_SPARE_L__DCSR_LATCH_SPARE_0___S 0 +#define PHYA_ROBE_DCSR_LATCH_SPARE_L___M 0xFFFFFFFF +#define PHYA_ROBE_DCSR_LATCH_SPARE_L___S 0 + +#define PHYA_ROBE_DCSR_LATCH_SPARE_U (0x004B0474) +#define PHYA_ROBE_DCSR_LATCH_SPARE_U___RWC QCSR_REG_RW +#define PHYA_ROBE_DCSR_LATCH_SPARE_U___POR 0x00000000 +#define PHYA_ROBE_DCSR_LATCH_SPARE_U__DCSR_LATCH_SPARE_1___POR 0x00000000 +#define PHYA_ROBE_DCSR_LATCH_SPARE_U__DCSR_LATCH_SPARE_1___M 0xFFFFFFFF +#define PHYA_ROBE_DCSR_LATCH_SPARE_U__DCSR_LATCH_SPARE_1___S 0 +#define PHYA_ROBE_DCSR_LATCH_SPARE_U___M 0xFFFFFFFF +#define PHYA_ROBE_DCSR_LATCH_SPARE_U___S 0 + +#define PHYA_ROBE_USR_TAB_0_L (0x004B0478) +#define PHYA_ROBE_USR_TAB_0_L___RWC QCSR_REG_RW +#define PHYA_ROBE_USR_TAB_0_L___POR 0x00000400 +#define PHYA_ROBE_USR_TAB_0_L__USR_CODE_RATE___POR 0x0 +#define PHYA_ROBE_USR_TAB_0_L__USR_NCBPSC___POR 0x0 +#define PHYA_ROBE_USR_TAB_0_L__USR_BCC_LOAD_THR___POR 0x04 +#define PHYA_ROBE_USR_TAB_0_L__USR_RU_INDEX___POR 0x00 +#define PHYA_ROBE_USR_TAB_0_L__USR_CODE_RATE___M 0x07000000 +#define PHYA_ROBE_USR_TAB_0_L__USR_CODE_RATE___S 24 +#define PHYA_ROBE_USR_TAB_0_L__USR_NCBPSC___M 0x000F0000 +#define PHYA_ROBE_USR_TAB_0_L__USR_NCBPSC___S 16 +#define PHYA_ROBE_USR_TAB_0_L__USR_BCC_LOAD_THR___M 0x00001F00 +#define PHYA_ROBE_USR_TAB_0_L__USR_BCC_LOAD_THR___S 8 +#define PHYA_ROBE_USR_TAB_0_L__USR_RU_INDEX___M 0x0000003F +#define PHYA_ROBE_USR_TAB_0_L__USR_RU_INDEX___S 0 +#define PHYA_ROBE_USR_TAB_0_L___M 0x070F1F3F +#define PHYA_ROBE_USR_TAB_0_L___S 0 + +#define PHYA_ROBE_USR_TAB_0_U (0x004B047C) +#define PHYA_ROBE_USR_TAB_0_U___RWC QCSR_REG_RW +#define PHYA_ROBE_USR_TAB_0_U___POR 0x00000000 +#define PHYA_ROBE_USR_TAB_0_U__USR_SS_OFFSET___POR 0x0 +#define PHYA_ROBE_USR_TAB_0_U__USR_NCOL___POR 0x00 +#define PHYA_ROBE_USR_TAB_0_U__USR_NROW___POR 0x00 +#define PHYA_ROBE_USR_TAB_0_U__USR_MCS___POR 0x0 +#define PHYA_ROBE_USR_TAB_0_U__USR_SS_OFFSET___M 0x0F000000 +#define PHYA_ROBE_USR_TAB_0_U__USR_SS_OFFSET___S 24 +#define PHYA_ROBE_USR_TAB_0_U__USR_NCOL___M 0x003F0000 +#define PHYA_ROBE_USR_TAB_0_U__USR_NCOL___S 16 +#define PHYA_ROBE_USR_TAB_0_U__USR_NROW___M 0x00001F00 +#define PHYA_ROBE_USR_TAB_0_U__USR_NROW___S 8 +#define PHYA_ROBE_USR_TAB_0_U__USR_MCS___M 0x0000000F +#define PHYA_ROBE_USR_TAB_0_U__USR_MCS___S 0 +#define PHYA_ROBE_USR_TAB_0_U___M 0x0F3F1F0F +#define PHYA_ROBE_USR_TAB_0_U___S 0 + +#define PHYA_ROBE_USR_TAB_1_L (0x004B0480) +#define PHYA_ROBE_USR_TAB_1_L___RWC QCSR_REG_RW +#define PHYA_ROBE_USR_TAB_1_L___POR 0x00000000 +#define PHYA_ROBE_USR_TAB_1_L__USR_N_SC___POR 0x000 +#define PHYA_ROBE_USR_TAB_1_L__USR_ADV_CODING___POR 0x0 +#define PHYA_ROBE_USR_TAB_1_L__USR_NSS___POR 0x0 +#define PHYA_ROBE_USR_TAB_1_L__USR_N_SC___M 0x07FF0000 +#define PHYA_ROBE_USR_TAB_1_L__USR_N_SC___S 16 +#define PHYA_ROBE_USR_TAB_1_L__USR_ADV_CODING___M 0x00000100 +#define PHYA_ROBE_USR_TAB_1_L__USR_ADV_CODING___S 8 +#define PHYA_ROBE_USR_TAB_1_L__USR_NSS___M 0x0000000F +#define PHYA_ROBE_USR_TAB_1_L__USR_NSS___S 0 +#define PHYA_ROBE_USR_TAB_1_L___M 0x07FF010F +#define PHYA_ROBE_USR_TAB_1_L___S 0 + +#define PHYA_ROBE_USR_TAB_1_U (0x004B0484) +#define PHYA_ROBE_USR_TAB_1_U___RWC QCSR_REG_RW +#define PHYA_ROBE_USR_TAB_1_U___POR 0x00000000 +#define PHYA_ROBE_USR_TAB_1_U__USR_BCC_PU___POR 0x0 +#define PHYA_ROBE_USR_TAB_1_U__USR_VALID___POR 0x0 +#define PHYA_ROBE_USR_TAB_1_U__USR_DROP_LAST_LLR___POR 0x0 +#define PHYA_ROBE_USR_TAB_1_U__USR_IS_DCM___POR 0x0 +#define PHYA_ROBE_USR_TAB_1_U__USR_BCC_PU___M 0x01000000 +#define PHYA_ROBE_USR_TAB_1_U__USR_BCC_PU___S 24 +#define PHYA_ROBE_USR_TAB_1_U__USR_VALID___M 0x00010000 +#define PHYA_ROBE_USR_TAB_1_U__USR_VALID___S 16 +#define PHYA_ROBE_USR_TAB_1_U__USR_DROP_LAST_LLR___M 0x00000100 +#define PHYA_ROBE_USR_TAB_1_U__USR_DROP_LAST_LLR___S 8 +#define PHYA_ROBE_USR_TAB_1_U__USR_IS_DCM___M 0x00000001 +#define PHYA_ROBE_USR_TAB_1_U__USR_IS_DCM___S 0 +#define PHYA_ROBE_USR_TAB_1_U___M 0x01010101 +#define PHYA_ROBE_USR_TAB_1_U___S 0 + +#define PHYA_ROBE_USR_TAB_2_L (0x004B0488) +#define PHYA_ROBE_USR_TAB_2_L___RWC QCSR_REG_RW +#define PHYA_ROBE_USR_TAB_2_L___POR 0x00000000 +#define PHYA_ROBE_USR_TAB_2_L__USR_SEGMENT___POR 0x0 +#define PHYA_ROBE_USR_TAB_2_L__USR_SEGMENT___M 0x00000001 +#define PHYA_ROBE_USR_TAB_2_L__USR_SEGMENT___S 0 +#define PHYA_ROBE_USR_TAB_2_L___M 0x00000001 +#define PHYA_ROBE_USR_TAB_2_L___S 0 + +#define PHYA_ROBE_USR_TAB_2_U (0x004B048C) +#define PHYA_ROBE_USR_TAB_2_U___RWC QCSR_REG_RW +#define PHYA_ROBE_USR_TAB_2_U___POR 0x00000000 +#define PHYA_ROBE_USR_TAB_2_U__USR_NUM_DECODED_BITS___POR 0x0000000 +#define PHYA_ROBE_USR_TAB_2_U__USR_NUM_DECODED_BITS___M 0x03FFFFFF +#define PHYA_ROBE_USR_TAB_2_U__USR_NUM_DECODED_BITS___S 0 +#define PHYA_ROBE_USR_TAB_2_U___M 0x03FFFFFF +#define PHYA_ROBE_USR_TAB_2_U___S 0 + +#define PHYA_ROBE_USR_TAB_3_L (0x004B0490) +#define PHYA_ROBE_USR_TAB_3_L___RWC QCSR_REG_RW +#define PHYA_ROBE_USR_TAB_3_L___POR 0x00000000 +#define PHYA_ROBE_USR_TAB_3_L__USR_LDPC_N_SHT_PLUS1___POR 0x0000 +#define PHYA_ROBE_USR_TAB_3_L__USR_LDPC_CODE_LEN___POR 0x0 +#define PHYA_ROBE_USR_TAB_3_L__USR_LDPC_PUNC___POR 0x0 +#define PHYA_ROBE_USR_TAB_3_L__USR_LDPC_N_SHT_PLUS1___M 0xFFFF0000 +#define PHYA_ROBE_USR_TAB_3_L__USR_LDPC_N_SHT_PLUS1___S 16 +#define PHYA_ROBE_USR_TAB_3_L__USR_LDPC_CODE_LEN___M 0x00000300 +#define PHYA_ROBE_USR_TAB_3_L__USR_LDPC_CODE_LEN___S 8 +#define PHYA_ROBE_USR_TAB_3_L__USR_LDPC_PUNC___M 0x00000001 +#define PHYA_ROBE_USR_TAB_3_L__USR_LDPC_PUNC___S 0 +#define PHYA_ROBE_USR_TAB_3_L___M 0xFFFF0301 +#define PHYA_ROBE_USR_TAB_3_L___S 0 + +#define PHYA_ROBE_USR_TAB_3_U (0x004B0494) +#define PHYA_ROBE_USR_TAB_3_U___RWC QCSR_REG_RW +#define PHYA_ROBE_USR_TAB_3_U___POR 0x00000000 +#define PHYA_ROBE_USR_TAB_3_U__USR_LDPC_N_PRP_PLUS1___POR 0x0000 +#define PHYA_ROBE_USR_TAB_3_U__USR_LDPC_N_CW___POR 0x0000 +#define PHYA_ROBE_USR_TAB_3_U__USR_LDPC_N_PRP_PLUS1___M 0xFFFF0000 +#define PHYA_ROBE_USR_TAB_3_U__USR_LDPC_N_PRP_PLUS1___S 16 +#define PHYA_ROBE_USR_TAB_3_U__USR_LDPC_N_CW___M 0x0000FFFF +#define PHYA_ROBE_USR_TAB_3_U__USR_LDPC_N_CW___S 0 +#define PHYA_ROBE_USR_TAB_3_U___M 0xFFFFFFFF +#define PHYA_ROBE_USR_TAB_3_U___S 0 + +#define PHYA_ROBE_USR_TAB_4_L (0x004B0498) +#define PHYA_ROBE_USR_TAB_4_L___RWC QCSR_REG_RW +#define PHYA_ROBE_USR_TAB_4_L___POR 0x00000000 +#define PHYA_ROBE_USR_TAB_4_L__USR_LDPC_N_PRPCW___POR 0x0000 +#define PHYA_ROBE_USR_TAB_4_L__USR_LDPC_N_SPCW___POR 0x000 +#define PHYA_ROBE_USR_TAB_4_L__USR_LDPC_N_PRPCW___M 0xFFFF0000 +#define PHYA_ROBE_USR_TAB_4_L__USR_LDPC_N_PRPCW___S 16 +#define PHYA_ROBE_USR_TAB_4_L__USR_LDPC_N_SPCW___M 0x000007FF +#define PHYA_ROBE_USR_TAB_4_L__USR_LDPC_N_SPCW___S 0 +#define PHYA_ROBE_USR_TAB_4_L___M 0xFFFF07FF +#define PHYA_ROBE_USR_TAB_4_L___S 0 + +#define PHYA_ROBE_USR_TAB_4_U (0x004B049C) +#define PHYA_ROBE_USR_TAB_4_U___RWC QCSR_REG_RW +#define PHYA_ROBE_USR_TAB_4_U___POR 0x00000000 +#define PHYA_ROBE_USR_TAB_4_U__PKT_START_WR_USR_SPARE___POR 0x0 +#define PHYA_ROBE_USR_TAB_4_U__PKT_START_WR_USR_SPARE___M 0x0000000F +#define PHYA_ROBE_USR_TAB_4_U__PKT_START_WR_USR_SPARE___S 0 +#define PHYA_ROBE_USR_TAB_4_U___M 0x0000000F +#define PHYA_ROBE_USR_TAB_4_U___S 0 + +#define PHYA_ROBE_ERROR_V2_CODE_L (0x004B5000) +#define PHYA_ROBE_ERROR_V2_CODE_L___RWC QCSR_REG_RO +#define PHYA_ROBE_ERROR_V2_CODE_L___POR 0x00000000 +#define PHYA_ROBE_ERROR_V2_CODE_L__ERROR_CODE_V2___POR 0x00 +#define PHYA_ROBE_ERROR_V2_CODE_L__ERROR_CODE_V2___M 0x0000007F +#define PHYA_ROBE_ERROR_V2_CODE_L__ERROR_CODE_V2___S 0 +#define PHYA_ROBE_ERROR_V2_CODE_L___M 0x0000007F +#define PHYA_ROBE_ERROR_V2_CODE_L___S 0 + +#define PHYA_ROBE_ERROR_V2_INFO_L (0x004B5008) +#define PHYA_ROBE_ERROR_V2_INFO_L___RWC QCSR_REG_RO +#define PHYA_ROBE_ERROR_V2_INFO_L___POR 0x00000000 +#define PHYA_ROBE_ERROR_V2_INFO_L__ERROR_INFO_V2___POR 0x00000000 +#define PHYA_ROBE_ERROR_V2_INFO_L__ERROR_INFO_V2___M 0xFFFFFFFF +#define PHYA_ROBE_ERROR_V2_INFO_L__ERROR_INFO_V2___S 0 +#define PHYA_ROBE_ERROR_V2_INFO_L___M 0xFFFFFFFF +#define PHYA_ROBE_ERROR_V2_INFO_L___S 0 + +#define PHYA_ROBE_ERROR_V2_STATUS_L (0x004B5010) +#define PHYA_ROBE_ERROR_V2_STATUS_L___RWC QCSR_REG_RO +#define PHYA_ROBE_ERROR_V2_STATUS_L___POR 0x00000000 +#define PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ILLEGAL_SU_CODE_RATE_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ZERO_SU_NROW_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ZERO_SU_NCOL_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ZERO_SU_LDPC_N_CW_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ILLEGAL_PKT_BW_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ILLEGAL_SU_NES_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ILLEGAL_SU_NSS_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_L__HESIGB_BUF_OVERFLOW___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_L__DEINT_RU_START_NO_RU_END_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_L__TRFC_LDPC_LRCM_WR_STATE_WD_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_L__TRFC_LDPC_WR_CTRL_STATE_WD_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_L__TRFC_LDPC_ALIGN_STATE_WD_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_L__TRFC_LDPC_RD_CTRL_WD_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_L__SCHD_SEQ_WDOG_TO_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_L__SCHD_LDPCST_WDOG_TO_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_L__SCHD_BCCST_WDOG_TO_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_L__SCHD_LDPCLD_WDOG_TO_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_L__SCHD_POPF_WDOG_TO_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_L__BMMU_WDOG_TO_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_L__LDPC_TIMEOUT___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_L__DEINT_DATA_VALID_WDOG___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_L__DEINT_RU_START_WDOG___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_L__VIT_SU_WDOG_DATA___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_L__VIT_SU_WDOG_PREAMBLE___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_HESIGB_WDOG_TO_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_EOP_WDOG_TO_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_PKT_WDOG_TO_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_L__EOP_ERROR_V2___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_L__DCSR_LATCH_ERROR_V2___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_L__SIG_EXT_DEC_ERROR_V2___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_L__SIG_DEC_ERROR_V2___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_L__PKT_START_ERROR_V2___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ILLEGAL_SU_CODE_RATE_ERR___M 0x80000000 +#define PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ILLEGAL_SU_CODE_RATE_ERR___S 31 +#define PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ZERO_SU_NROW_ERR___M 0x40000000 +#define PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ZERO_SU_NROW_ERR___S 30 +#define PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ZERO_SU_NCOL_ERR___M 0x20000000 +#define PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ZERO_SU_NCOL_ERR___S 29 +#define PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ZERO_SU_LDPC_N_CW_ERR___M 0x10000000 +#define PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ZERO_SU_LDPC_N_CW_ERR___S 28 +#define PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ILLEGAL_PKT_BW_ERR___M 0x08000000 +#define PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ILLEGAL_PKT_BW_ERR___S 27 +#define PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ILLEGAL_SU_NES_ERR___M 0x04000000 +#define PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ILLEGAL_SU_NES_ERR___S 26 +#define PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ILLEGAL_SU_NSS_ERR___M 0x02000000 +#define PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_ILLEGAL_SU_NSS_ERR___S 25 +#define PHYA_ROBE_ERROR_V2_STATUS_L__HESIGB_BUF_OVERFLOW___M 0x01000000 +#define PHYA_ROBE_ERROR_V2_STATUS_L__HESIGB_BUF_OVERFLOW___S 24 +#define PHYA_ROBE_ERROR_V2_STATUS_L__DEINT_RU_START_NO_RU_END_ERR___M 0x00800000 +#define PHYA_ROBE_ERROR_V2_STATUS_L__DEINT_RU_START_NO_RU_END_ERR___S 23 +#define PHYA_ROBE_ERROR_V2_STATUS_L__TRFC_LDPC_LRCM_WR_STATE_WD_ERR___M 0x00400000 +#define PHYA_ROBE_ERROR_V2_STATUS_L__TRFC_LDPC_LRCM_WR_STATE_WD_ERR___S 22 +#define PHYA_ROBE_ERROR_V2_STATUS_L__TRFC_LDPC_WR_CTRL_STATE_WD_ERR___M 0x00200000 +#define PHYA_ROBE_ERROR_V2_STATUS_L__TRFC_LDPC_WR_CTRL_STATE_WD_ERR___S 21 +#define PHYA_ROBE_ERROR_V2_STATUS_L__TRFC_LDPC_ALIGN_STATE_WD_ERR___M 0x00100000 +#define PHYA_ROBE_ERROR_V2_STATUS_L__TRFC_LDPC_ALIGN_STATE_WD_ERR___S 20 +#define PHYA_ROBE_ERROR_V2_STATUS_L__TRFC_LDPC_RD_CTRL_WD_ERR___M 0x00080000 +#define PHYA_ROBE_ERROR_V2_STATUS_L__TRFC_LDPC_RD_CTRL_WD_ERR___S 19 +#define PHYA_ROBE_ERROR_V2_STATUS_L__SCHD_SEQ_WDOG_TO_ERR___M 0x00040000 +#define PHYA_ROBE_ERROR_V2_STATUS_L__SCHD_SEQ_WDOG_TO_ERR___S 18 +#define PHYA_ROBE_ERROR_V2_STATUS_L__SCHD_LDPCST_WDOG_TO_ERR___M 0x00020000 +#define PHYA_ROBE_ERROR_V2_STATUS_L__SCHD_LDPCST_WDOG_TO_ERR___S 17 +#define PHYA_ROBE_ERROR_V2_STATUS_L__SCHD_BCCST_WDOG_TO_ERR___M 0x00010000 +#define PHYA_ROBE_ERROR_V2_STATUS_L__SCHD_BCCST_WDOG_TO_ERR___S 16 +#define PHYA_ROBE_ERROR_V2_STATUS_L__SCHD_LDPCLD_WDOG_TO_ERR___M 0x00008000 +#define PHYA_ROBE_ERROR_V2_STATUS_L__SCHD_LDPCLD_WDOG_TO_ERR___S 15 +#define PHYA_ROBE_ERROR_V2_STATUS_L__SCHD_POPF_WDOG_TO_ERR___M 0x00004000 +#define PHYA_ROBE_ERROR_V2_STATUS_L__SCHD_POPF_WDOG_TO_ERR___S 14 +#define PHYA_ROBE_ERROR_V2_STATUS_L__BMMU_WDOG_TO_ERR___M 0x00002000 +#define PHYA_ROBE_ERROR_V2_STATUS_L__BMMU_WDOG_TO_ERR___S 13 +#define PHYA_ROBE_ERROR_V2_STATUS_L__LDPC_TIMEOUT___M 0x00001000 +#define PHYA_ROBE_ERROR_V2_STATUS_L__LDPC_TIMEOUT___S 12 +#define PHYA_ROBE_ERROR_V2_STATUS_L__DEINT_DATA_VALID_WDOG___M 0x00000800 +#define PHYA_ROBE_ERROR_V2_STATUS_L__DEINT_DATA_VALID_WDOG___S 11 +#define PHYA_ROBE_ERROR_V2_STATUS_L__DEINT_RU_START_WDOG___M 0x00000400 +#define PHYA_ROBE_ERROR_V2_STATUS_L__DEINT_RU_START_WDOG___S 10 +#define PHYA_ROBE_ERROR_V2_STATUS_L__VIT_SU_WDOG_DATA___M 0x00000200 +#define PHYA_ROBE_ERROR_V2_STATUS_L__VIT_SU_WDOG_DATA___S 9 +#define PHYA_ROBE_ERROR_V2_STATUS_L__VIT_SU_WDOG_PREAMBLE___M 0x00000100 +#define PHYA_ROBE_ERROR_V2_STATUS_L__VIT_SU_WDOG_PREAMBLE___S 8 +#define PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_HESIGB_WDOG_TO_ERR___M 0x00000080 +#define PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_HESIGB_WDOG_TO_ERR___S 7 +#define PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_EOP_WDOG_TO_ERR___M 0x00000040 +#define PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_EOP_WDOG_TO_ERR___S 6 +#define PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_PKT_WDOG_TO_ERR___M 0x00000020 +#define PHYA_ROBE_ERROR_V2_STATUS_L__CTRL_PKT_WDOG_TO_ERR___S 5 +#define PHYA_ROBE_ERROR_V2_STATUS_L__EOP_ERROR_V2___M 0x00000010 +#define PHYA_ROBE_ERROR_V2_STATUS_L__EOP_ERROR_V2___S 4 +#define PHYA_ROBE_ERROR_V2_STATUS_L__DCSR_LATCH_ERROR_V2___M 0x00000008 +#define PHYA_ROBE_ERROR_V2_STATUS_L__DCSR_LATCH_ERROR_V2___S 3 +#define PHYA_ROBE_ERROR_V2_STATUS_L__SIG_EXT_DEC_ERROR_V2___M 0x00000004 +#define PHYA_ROBE_ERROR_V2_STATUS_L__SIG_EXT_DEC_ERROR_V2___S 2 +#define PHYA_ROBE_ERROR_V2_STATUS_L__SIG_DEC_ERROR_V2___M 0x00000002 +#define PHYA_ROBE_ERROR_V2_STATUS_L__SIG_DEC_ERROR_V2___S 1 +#define PHYA_ROBE_ERROR_V2_STATUS_L__PKT_START_ERROR_V2___M 0x00000001 +#define PHYA_ROBE_ERROR_V2_STATUS_L__PKT_START_ERROR_V2___S 0 +#define PHYA_ROBE_ERROR_V2_STATUS_L___M 0xFFFFFFFF +#define PHYA_ROBE_ERROR_V2_STATUS_L___S 0 + +#define PHYA_ROBE_ERROR_V2_STATUS_U (0x004B5014) +#define PHYA_ROBE_ERROR_V2_STATUS_U___RWC QCSR_REG_RO +#define PHYA_ROBE_ERROR_V2_STATUS_U___POR 0x00000000 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_63___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_62___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_61___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_60___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_59___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_58___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_57___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_56___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_55___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_54___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_53___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_52___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_51___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_U__CTRL_ILLEGAL_SYM_TYPE_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_U__CTRL_ZERO_SU_NUM_DECODED_BITS_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_U__DEINT_DATA_VALID_BEFORE_RU_START_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_SRV_FLD_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_VHT_SIGB_CRC_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_OOO_CW_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_LDPC_CW_WORD_CNT_MISMATCH_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_LDPC_CW_LAST_DWORD_VALID_BITS_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_TB_BUF_OVFL_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_SU_SYNC_TB_FIRST_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_SU_SYNC_TB_RDY_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_IN_OVERF___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_IN_UNDERF___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_LLM_INT_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_SELF_DROP_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_GNT_ERROR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_U__SCHD_USR_TAB_LATE_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_UID_IN_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_U__CTRL_ILLEGAL_SU_NCBPSC_ERR___POR 0x0 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_63___M 0x80000000 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_63___S 31 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_62___M 0x40000000 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_62___S 30 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_61___M 0x20000000 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_61___S 29 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_60___M 0x10000000 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_60___S 28 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_59___M 0x08000000 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_59___S 27 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_58___M 0x04000000 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_58___S 26 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_57___M 0x02000000 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_57___S 25 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_56___M 0x01000000 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_56___S 24 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_55___M 0x00800000 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_55___S 23 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_54___M 0x00400000 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_54___S 22 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_53___M 0x00200000 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_53___S 21 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_52___M 0x00100000 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_52___S 20 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_51___M 0x00080000 +#define PHYA_ROBE_ERROR_V2_STATUS_U__ROBE_SPARE_ERROR_V2_51___S 19 +#define PHYA_ROBE_ERROR_V2_STATUS_U__CTRL_ILLEGAL_SYM_TYPE_ERR___M 0x00040000 +#define PHYA_ROBE_ERROR_V2_STATUS_U__CTRL_ILLEGAL_SYM_TYPE_ERR___S 18 +#define PHYA_ROBE_ERROR_V2_STATUS_U__CTRL_ZERO_SU_NUM_DECODED_BITS_ERR___M 0x00020000 +#define PHYA_ROBE_ERROR_V2_STATUS_U__CTRL_ZERO_SU_NUM_DECODED_BITS_ERR___S 17 +#define PHYA_ROBE_ERROR_V2_STATUS_U__DEINT_DATA_VALID_BEFORE_RU_START_ERR___M 0x00010000 +#define PHYA_ROBE_ERROR_V2_STATUS_U__DEINT_DATA_VALID_BEFORE_RU_START_ERR___S 16 +#define PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_SRV_FLD_ERR___M 0x00008000 +#define PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_SRV_FLD_ERR___S 15 +#define PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_VHT_SIGB_CRC_ERR___M 0x00004000 +#define PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_VHT_SIGB_CRC_ERR___S 14 +#define PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_OOO_CW_ERR___M 0x00002000 +#define PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_OOO_CW_ERR___S 13 +#define PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_LDPC_CW_WORD_CNT_MISMATCH_ERR___M 0x00001000 +#define PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_LDPC_CW_WORD_CNT_MISMATCH_ERR___S 12 +#define PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_LDPC_CW_LAST_DWORD_VALID_BITS_ERR___M 0x00000800 +#define PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_LDPC_CW_LAST_DWORD_VALID_BITS_ERR___S 11 +#define PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_TB_BUF_OVFL_ERR___M 0x00000400 +#define PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_TB_BUF_OVFL_ERR___S 10 +#define PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_SU_SYNC_TB_FIRST_ERR___M 0x00000200 +#define PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_SU_SYNC_TB_FIRST_ERR___S 9 +#define PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_SU_SYNC_TB_RDY_ERR___M 0x00000100 +#define PHYA_ROBE_ERROR_V2_STATUS_U__TRFC_SU_SYNC_TB_RDY_ERR___S 8 +#define PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_IN_OVERF___M 0x00000080 +#define PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_IN_OVERF___S 7 +#define PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_IN_UNDERF___M 0x00000040 +#define PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_IN_UNDERF___S 6 +#define PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_LLM_INT_ERR___M 0x00000020 +#define PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_LLM_INT_ERR___S 5 +#define PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_SELF_DROP_ERR___M 0x00000010 +#define PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_SELF_DROP_ERR___S 4 +#define PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_GNT_ERROR___M 0x00000008 +#define PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_GNT_ERROR___S 3 +#define PHYA_ROBE_ERROR_V2_STATUS_U__SCHD_USR_TAB_LATE_ERR___M 0x00000004 +#define PHYA_ROBE_ERROR_V2_STATUS_U__SCHD_USR_TAB_LATE_ERR___S 2 +#define PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_UID_IN_ERR___M 0x00000002 +#define PHYA_ROBE_ERROR_V2_STATUS_U__BMMU_UID_IN_ERR___S 1 +#define PHYA_ROBE_ERROR_V2_STATUS_U__CTRL_ILLEGAL_SU_NCBPSC_ERR___M 0x00000001 +#define PHYA_ROBE_ERROR_V2_STATUS_U__CTRL_ILLEGAL_SU_NCBPSC_ERR___S 0 +#define PHYA_ROBE_ERROR_V2_STATUS_U___M 0xFFFFFFFF +#define PHYA_ROBE_ERROR_V2_STATUS_U___S 0 + +#define PHYA_ROBE_ERROR_V2_MASK_L (0x004B5018) +#define PHYA_ROBE_ERROR_V2_MASK_L___RWC QCSR_REG_RW +#define PHYA_ROBE_ERROR_V2_MASK_L___POR 0xFFFFFFFF +#define PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ILLEGAL_SU_CODE_RATE_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ZERO_SU_NROW_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ZERO_SU_NCOL_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ZERO_SU_LDPC_N_CW_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ILLEGAL_PKT_BW_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ILLEGAL_SU_NES_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ILLEGAL_SU_NSS_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_L__HESIGB_BUF_OVERFLOW_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_L__DEINT_RU_START_NO_RU_END_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_L__TRFC_LDPC_LRCM_WR_STATE_WD_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_L__TRFC_LDPC_WR_CTRL_STATE_WD_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_L__TRFC_LDPC_ALIGN_STATE_WD_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_L__TRFC_LDPC_RD_CTRL_WD_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_L__SCHD_SEQ_WDOG_TO_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_L__SCHD_LDPCST_WDOG_TO_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_L__SCHD_BCCST_WDOG_TO_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_L__SCHD_LDPCLD_WDOG_TO_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_L__SCHD_POPF_WDOG_TO_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_L__BMMU_WDOG_TO_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_L__LDPC_TIMEOUT_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_L__DEINT_DATA_VALID_WDOG_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_L__DEINT_RU_START_WDOG_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_L__VIT_SU_WDOG_DATA_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_L__VIT_SU_WDOG_PREAMBLE_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_L__CTRL_HESIGB_WDOG_TO_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_L__CTRL_EOP_WDOG_TO_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_L__CTRL_PKT_WDOG_TO_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_L__EOP_ERROR_V2_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_L__DCSR_LATCH_ERROR_V2_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_L__SIG_EXT_DEC_ERROR_V2_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_L__SIG_DEC_ERROR_V2_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_L__PKT_START_ERROR_V2_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ILLEGAL_SU_CODE_RATE_ERR_MASK___M 0x80000000 +#define PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ILLEGAL_SU_CODE_RATE_ERR_MASK___S 31 +#define PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ZERO_SU_NROW_ERR_MASK___M 0x40000000 +#define PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ZERO_SU_NROW_ERR_MASK___S 30 +#define PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ZERO_SU_NCOL_ERR_MASK___M 0x20000000 +#define PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ZERO_SU_NCOL_ERR_MASK___S 29 +#define PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ZERO_SU_LDPC_N_CW_ERR_MASK___M 0x10000000 +#define PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ZERO_SU_LDPC_N_CW_ERR_MASK___S 28 +#define PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ILLEGAL_PKT_BW_ERR_MASK___M 0x08000000 +#define PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ILLEGAL_PKT_BW_ERR_MASK___S 27 +#define PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ILLEGAL_SU_NES_ERR_MASK___M 0x04000000 +#define PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ILLEGAL_SU_NES_ERR_MASK___S 26 +#define PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ILLEGAL_SU_NSS_ERR_MASK___M 0x02000000 +#define PHYA_ROBE_ERROR_V2_MASK_L__CTRL_ILLEGAL_SU_NSS_ERR_MASK___S 25 +#define PHYA_ROBE_ERROR_V2_MASK_L__HESIGB_BUF_OVERFLOW_MASK___M 0x01000000 +#define PHYA_ROBE_ERROR_V2_MASK_L__HESIGB_BUF_OVERFLOW_MASK___S 24 +#define PHYA_ROBE_ERROR_V2_MASK_L__DEINT_RU_START_NO_RU_END_ERR_MASK___M 0x00800000 +#define PHYA_ROBE_ERROR_V2_MASK_L__DEINT_RU_START_NO_RU_END_ERR_MASK___S 23 +#define PHYA_ROBE_ERROR_V2_MASK_L__TRFC_LDPC_LRCM_WR_STATE_WD_ERR_MASK___M 0x00400000 +#define PHYA_ROBE_ERROR_V2_MASK_L__TRFC_LDPC_LRCM_WR_STATE_WD_ERR_MASK___S 22 +#define PHYA_ROBE_ERROR_V2_MASK_L__TRFC_LDPC_WR_CTRL_STATE_WD_ERR_MASK___M 0x00200000 +#define PHYA_ROBE_ERROR_V2_MASK_L__TRFC_LDPC_WR_CTRL_STATE_WD_ERR_MASK___S 21 +#define PHYA_ROBE_ERROR_V2_MASK_L__TRFC_LDPC_ALIGN_STATE_WD_ERR_MASK___M 0x00100000 +#define PHYA_ROBE_ERROR_V2_MASK_L__TRFC_LDPC_ALIGN_STATE_WD_ERR_MASK___S 20 +#define PHYA_ROBE_ERROR_V2_MASK_L__TRFC_LDPC_RD_CTRL_WD_ERR_MASK___M 0x00080000 +#define PHYA_ROBE_ERROR_V2_MASK_L__TRFC_LDPC_RD_CTRL_WD_ERR_MASK___S 19 +#define PHYA_ROBE_ERROR_V2_MASK_L__SCHD_SEQ_WDOG_TO_ERR_MASK___M 0x00040000 +#define PHYA_ROBE_ERROR_V2_MASK_L__SCHD_SEQ_WDOG_TO_ERR_MASK___S 18 +#define PHYA_ROBE_ERROR_V2_MASK_L__SCHD_LDPCST_WDOG_TO_ERR_MASK___M 0x00020000 +#define PHYA_ROBE_ERROR_V2_MASK_L__SCHD_LDPCST_WDOG_TO_ERR_MASK___S 17 +#define PHYA_ROBE_ERROR_V2_MASK_L__SCHD_BCCST_WDOG_TO_ERR_MASK___M 0x00010000 +#define PHYA_ROBE_ERROR_V2_MASK_L__SCHD_BCCST_WDOG_TO_ERR_MASK___S 16 +#define PHYA_ROBE_ERROR_V2_MASK_L__SCHD_LDPCLD_WDOG_TO_ERR_MASK___M 0x00008000 +#define PHYA_ROBE_ERROR_V2_MASK_L__SCHD_LDPCLD_WDOG_TO_ERR_MASK___S 15 +#define PHYA_ROBE_ERROR_V2_MASK_L__SCHD_POPF_WDOG_TO_ERR_MASK___M 0x00004000 +#define PHYA_ROBE_ERROR_V2_MASK_L__SCHD_POPF_WDOG_TO_ERR_MASK___S 14 +#define PHYA_ROBE_ERROR_V2_MASK_L__BMMU_WDOG_TO_ERR_MASK___M 0x00002000 +#define PHYA_ROBE_ERROR_V2_MASK_L__BMMU_WDOG_TO_ERR_MASK___S 13 +#define PHYA_ROBE_ERROR_V2_MASK_L__LDPC_TIMEOUT_MASK___M 0x00001000 +#define PHYA_ROBE_ERROR_V2_MASK_L__LDPC_TIMEOUT_MASK___S 12 +#define PHYA_ROBE_ERROR_V2_MASK_L__DEINT_DATA_VALID_WDOG_MASK___M 0x00000800 +#define PHYA_ROBE_ERROR_V2_MASK_L__DEINT_DATA_VALID_WDOG_MASK___S 11 +#define PHYA_ROBE_ERROR_V2_MASK_L__DEINT_RU_START_WDOG_MASK___M 0x00000400 +#define PHYA_ROBE_ERROR_V2_MASK_L__DEINT_RU_START_WDOG_MASK___S 10 +#define PHYA_ROBE_ERROR_V2_MASK_L__VIT_SU_WDOG_DATA_MASK___M 0x00000200 +#define PHYA_ROBE_ERROR_V2_MASK_L__VIT_SU_WDOG_DATA_MASK___S 9 +#define PHYA_ROBE_ERROR_V2_MASK_L__VIT_SU_WDOG_PREAMBLE_MASK___M 0x00000100 +#define PHYA_ROBE_ERROR_V2_MASK_L__VIT_SU_WDOG_PREAMBLE_MASK___S 8 +#define PHYA_ROBE_ERROR_V2_MASK_L__CTRL_HESIGB_WDOG_TO_ERR_MASK___M 0x00000080 +#define PHYA_ROBE_ERROR_V2_MASK_L__CTRL_HESIGB_WDOG_TO_ERR_MASK___S 7 +#define PHYA_ROBE_ERROR_V2_MASK_L__CTRL_EOP_WDOG_TO_ERR_MASK___M 0x00000040 +#define PHYA_ROBE_ERROR_V2_MASK_L__CTRL_EOP_WDOG_TO_ERR_MASK___S 6 +#define PHYA_ROBE_ERROR_V2_MASK_L__CTRL_PKT_WDOG_TO_ERR_MASK___M 0x00000020 +#define PHYA_ROBE_ERROR_V2_MASK_L__CTRL_PKT_WDOG_TO_ERR_MASK___S 5 +#define PHYA_ROBE_ERROR_V2_MASK_L__EOP_ERROR_V2_MASK___M 0x00000010 +#define PHYA_ROBE_ERROR_V2_MASK_L__EOP_ERROR_V2_MASK___S 4 +#define PHYA_ROBE_ERROR_V2_MASK_L__DCSR_LATCH_ERROR_V2_MASK___M 0x00000008 +#define PHYA_ROBE_ERROR_V2_MASK_L__DCSR_LATCH_ERROR_V2_MASK___S 3 +#define PHYA_ROBE_ERROR_V2_MASK_L__SIG_EXT_DEC_ERROR_V2_MASK___M 0x00000004 +#define PHYA_ROBE_ERROR_V2_MASK_L__SIG_EXT_DEC_ERROR_V2_MASK___S 2 +#define PHYA_ROBE_ERROR_V2_MASK_L__SIG_DEC_ERROR_V2_MASK___M 0x00000002 +#define PHYA_ROBE_ERROR_V2_MASK_L__SIG_DEC_ERROR_V2_MASK___S 1 +#define PHYA_ROBE_ERROR_V2_MASK_L__PKT_START_ERROR_V2_MASK___M 0x00000001 +#define PHYA_ROBE_ERROR_V2_MASK_L__PKT_START_ERROR_V2_MASK___S 0 +#define PHYA_ROBE_ERROR_V2_MASK_L___M 0xFFFFFFFF +#define PHYA_ROBE_ERROR_V2_MASK_L___S 0 + +#define PHYA_ROBE_ERROR_V2_MASK_U (0x004B501C) +#define PHYA_ROBE_ERROR_V2_MASK_U___RWC QCSR_REG_RW +#define PHYA_ROBE_ERROR_V2_MASK_U___POR 0xFFFFFFFF +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_63_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_62_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_61_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_60_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_59_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_58_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_57_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_56_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_55_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_54_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_53_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_52_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_51_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_U__CTRL_ILLEGAL_SYM_TYPE_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_U__CTRL_ZERO_SU_NUM_DECODED_BITS_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_U__DEINT_DATA_VALID_BEFORE_RU_START_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_U__TRFC_SRV_FLD_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_U__TRFC_VHT_SIGB_CRC_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_U__TRFC_OOO_CW_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_U__TRFC_LDPC_CW_WORD_CNT_MISMATCH_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_U__TRFC_LDPC_CW_LAST_DWORD_VALID_BITS_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_U__TRFC_TB_BUF_OVFL_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_U__TRFC_SU_SYNC_TB_FIRST_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_U__TRFC_SU_SYNC_TB_RDY_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_U__BMMU_IN_OVERF_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_U__BMMU_IN_UNDERF_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_U__BMMU_LLM_INT_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_U__BMMU_SELF_DROP_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_U__BMMU_GNT_ERROR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_U__SCHD_USR_TAB_LATE_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_U__BMMU_UID_IN_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_U__CTRL_ILLEGAL_SU_NCBPSC_ERR_MASK___POR 0x1 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_63_MASK___M 0x80000000 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_63_MASK___S 31 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_62_MASK___M 0x40000000 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_62_MASK___S 30 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_61_MASK___M 0x20000000 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_61_MASK___S 29 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_60_MASK___M 0x10000000 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_60_MASK___S 28 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_59_MASK___M 0x08000000 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_59_MASK___S 27 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_58_MASK___M 0x04000000 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_58_MASK___S 26 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_57_MASK___M 0x02000000 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_57_MASK___S 25 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_56_MASK___M 0x01000000 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_56_MASK___S 24 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_55_MASK___M 0x00800000 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_55_MASK___S 23 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_54_MASK___M 0x00400000 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_54_MASK___S 22 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_53_MASK___M 0x00200000 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_53_MASK___S 21 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_52_MASK___M 0x00100000 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_52_MASK___S 20 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_51_MASK___M 0x00080000 +#define PHYA_ROBE_ERROR_V2_MASK_U__ROBE_SPARE_ERROR_V2_51_MASK___S 19 +#define PHYA_ROBE_ERROR_V2_MASK_U__CTRL_ILLEGAL_SYM_TYPE_ERR_MASK___M 0x00040000 +#define PHYA_ROBE_ERROR_V2_MASK_U__CTRL_ILLEGAL_SYM_TYPE_ERR_MASK___S 18 +#define PHYA_ROBE_ERROR_V2_MASK_U__CTRL_ZERO_SU_NUM_DECODED_BITS_ERR_MASK___M 0x00020000 +#define PHYA_ROBE_ERROR_V2_MASK_U__CTRL_ZERO_SU_NUM_DECODED_BITS_ERR_MASK___S 17 +#define PHYA_ROBE_ERROR_V2_MASK_U__DEINT_DATA_VALID_BEFORE_RU_START_ERR_MASK___M 0x00010000 +#define PHYA_ROBE_ERROR_V2_MASK_U__DEINT_DATA_VALID_BEFORE_RU_START_ERR_MASK___S 16 +#define PHYA_ROBE_ERROR_V2_MASK_U__TRFC_SRV_FLD_ERR_MASK___M 0x00008000 +#define PHYA_ROBE_ERROR_V2_MASK_U__TRFC_SRV_FLD_ERR_MASK___S 15 +#define PHYA_ROBE_ERROR_V2_MASK_U__TRFC_VHT_SIGB_CRC_ERR_MASK___M 0x00004000 +#define PHYA_ROBE_ERROR_V2_MASK_U__TRFC_VHT_SIGB_CRC_ERR_MASK___S 14 +#define PHYA_ROBE_ERROR_V2_MASK_U__TRFC_OOO_CW_ERR_MASK___M 0x00002000 +#define PHYA_ROBE_ERROR_V2_MASK_U__TRFC_OOO_CW_ERR_MASK___S 13 +#define PHYA_ROBE_ERROR_V2_MASK_U__TRFC_LDPC_CW_WORD_CNT_MISMATCH_ERR_MASK___M 0x00001000 +#define PHYA_ROBE_ERROR_V2_MASK_U__TRFC_LDPC_CW_WORD_CNT_MISMATCH_ERR_MASK___S 12 +#define PHYA_ROBE_ERROR_V2_MASK_U__TRFC_LDPC_CW_LAST_DWORD_VALID_BITS_ERR_MASK___M 0x00000800 +#define PHYA_ROBE_ERROR_V2_MASK_U__TRFC_LDPC_CW_LAST_DWORD_VALID_BITS_ERR_MASK___S 11 +#define PHYA_ROBE_ERROR_V2_MASK_U__TRFC_TB_BUF_OVFL_ERR_MASK___M 0x00000400 +#define PHYA_ROBE_ERROR_V2_MASK_U__TRFC_TB_BUF_OVFL_ERR_MASK___S 10 +#define PHYA_ROBE_ERROR_V2_MASK_U__TRFC_SU_SYNC_TB_FIRST_ERR_MASK___M 0x00000200 +#define PHYA_ROBE_ERROR_V2_MASK_U__TRFC_SU_SYNC_TB_FIRST_ERR_MASK___S 9 +#define PHYA_ROBE_ERROR_V2_MASK_U__TRFC_SU_SYNC_TB_RDY_ERR_MASK___M 0x00000100 +#define PHYA_ROBE_ERROR_V2_MASK_U__TRFC_SU_SYNC_TB_RDY_ERR_MASK___S 8 +#define PHYA_ROBE_ERROR_V2_MASK_U__BMMU_IN_OVERF_MASK___M 0x00000080 +#define PHYA_ROBE_ERROR_V2_MASK_U__BMMU_IN_OVERF_MASK___S 7 +#define PHYA_ROBE_ERROR_V2_MASK_U__BMMU_IN_UNDERF_MASK___M 0x00000040 +#define PHYA_ROBE_ERROR_V2_MASK_U__BMMU_IN_UNDERF_MASK___S 6 +#define PHYA_ROBE_ERROR_V2_MASK_U__BMMU_LLM_INT_ERR_MASK___M 0x00000020 +#define PHYA_ROBE_ERROR_V2_MASK_U__BMMU_LLM_INT_ERR_MASK___S 5 +#define PHYA_ROBE_ERROR_V2_MASK_U__BMMU_SELF_DROP_ERR_MASK___M 0x00000010 +#define PHYA_ROBE_ERROR_V2_MASK_U__BMMU_SELF_DROP_ERR_MASK___S 4 +#define PHYA_ROBE_ERROR_V2_MASK_U__BMMU_GNT_ERROR_MASK___M 0x00000008 +#define PHYA_ROBE_ERROR_V2_MASK_U__BMMU_GNT_ERROR_MASK___S 3 +#define PHYA_ROBE_ERROR_V2_MASK_U__SCHD_USR_TAB_LATE_ERR_MASK___M 0x00000004 +#define PHYA_ROBE_ERROR_V2_MASK_U__SCHD_USR_TAB_LATE_ERR_MASK___S 2 +#define PHYA_ROBE_ERROR_V2_MASK_U__BMMU_UID_IN_ERR_MASK___M 0x00000002 +#define PHYA_ROBE_ERROR_V2_MASK_U__BMMU_UID_IN_ERR_MASK___S 1 +#define PHYA_ROBE_ERROR_V2_MASK_U__CTRL_ILLEGAL_SU_NCBPSC_ERR_MASK___M 0x00000001 +#define PHYA_ROBE_ERROR_V2_MASK_U__CTRL_ILLEGAL_SU_NCBPSC_ERR_MASK___S 0 +#define PHYA_ROBE_ERROR_V2_MASK_U___M 0xFFFFFFFF +#define PHYA_ROBE_ERROR_V2_MASK_U___S 0 + +#define PHYA_ROBE_DEBUG_STATUS_14_L (0x004B5020) +#define PHYA_ROBE_DEBUG_STATUS_14_L___RWC QCSR_REG_RO +#define PHYA_ROBE_DEBUG_STATUS_14_L___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_14_L__ERROR_STATUS_V2_UNMASKED_L___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_14_L__ERROR_STATUS_V2_UNMASKED_L___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_14_L__ERROR_STATUS_V2_UNMASKED_L___S 0 +#define PHYA_ROBE_DEBUG_STATUS_14_L___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_14_L___S 0 + +#define PHYA_ROBE_DEBUG_STATUS_14_U (0x004B5024) +#define PHYA_ROBE_DEBUG_STATUS_14_U___RWC QCSR_REG_RO +#define PHYA_ROBE_DEBUG_STATUS_14_U___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_14_U__ERROR_STATUS_V2_UNMASKED_U___POR 0x00000000 +#define PHYA_ROBE_DEBUG_STATUS_14_U__ERROR_STATUS_V2_UNMASKED_U___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_14_U__ERROR_STATUS_V2_UNMASKED_U___S 0 +#define PHYA_ROBE_DEBUG_STATUS_14_U___M 0xFFFFFFFF +#define PHYA_ROBE_DEBUG_STATUS_14_U___S 0 + +#define PHYA_ROBE_ROBE_HW_CONTROL_5_L (0x004B5028) +#define PHYA_ROBE_ROBE_HW_CONTROL_5_L___RWC QCSR_REG_RW +#define PHYA_ROBE_ROBE_HW_CONTROL_5_L___POR 0x00000100 +#define PHYA_ROBE_ROBE_HW_CONTROL_5_L__DISABLE_HT_STF_PKT_PARAM___POR 0x0 +#define PHYA_ROBE_ROBE_HW_CONTROL_5_L__DISABLE_NUM_HESIGB_PKT_PARAM___POR 0x0 +#define PHYA_ROBE_ROBE_HW_CONTROL_5_L__DISABLE_LSIG_6MBPS_PKT_PARAM___POR 0x1 +#define PHYA_ROBE_ROBE_HW_CONTROL_5_L__DISABLE_2SYM_PKT_PARAM___POR 0x0 +#define PHYA_ROBE_ROBE_HW_CONTROL_5_L__DISABLE_HT_STF_PKT_PARAM___M 0x01000000 +#define PHYA_ROBE_ROBE_HW_CONTROL_5_L__DISABLE_HT_STF_PKT_PARAM___S 24 +#define PHYA_ROBE_ROBE_HW_CONTROL_5_L__DISABLE_NUM_HESIGB_PKT_PARAM___M 0x00010000 +#define PHYA_ROBE_ROBE_HW_CONTROL_5_L__DISABLE_NUM_HESIGB_PKT_PARAM___S 16 +#define PHYA_ROBE_ROBE_HW_CONTROL_5_L__DISABLE_LSIG_6MBPS_PKT_PARAM___M 0x00000100 +#define PHYA_ROBE_ROBE_HW_CONTROL_5_L__DISABLE_LSIG_6MBPS_PKT_PARAM___S 8 +#define PHYA_ROBE_ROBE_HW_CONTROL_5_L__DISABLE_2SYM_PKT_PARAM___M 0x00000001 +#define PHYA_ROBE_ROBE_HW_CONTROL_5_L__DISABLE_2SYM_PKT_PARAM___S 0 +#define PHYA_ROBE_ROBE_HW_CONTROL_5_L___M 0x01010101 +#define PHYA_ROBE_ROBE_HW_CONTROL_5_L___S 0 + +#define PHYA_ROBE_ROBE_HW_CONTROL_5_U (0x004B502C) +#define PHYA_ROBE_ROBE_HW_CONTROL_5_U___RWC QCSR_REG_RW +#define PHYA_ROBE_ROBE_HW_CONTROL_5_U___POR 0x02051400 +#define PHYA_ROBE_ROBE_HW_CONTROL_5_U__BMMU_LLM_INT_ERR_THR_MAX___POR 0x02 +#define PHYA_ROBE_ROBE_HW_CONTROL_5_U__BMMU_LLM_INT_ERR_THR_MIN___POR 0x05 +#define PHYA_ROBE_ROBE_HW_CONTROL_5_U__BMMU_LLM_INT_ERR_THR_TIME___POR 0x14 +#define PHYA_ROBE_ROBE_HW_CONTROL_5_U__DISABLE_SHORT_GI_PKT_PARAM___POR 0x0 +#define PHYA_ROBE_ROBE_HW_CONTROL_5_U__BMMU_LLM_INT_ERR_THR_MAX___M 0x3F000000 +#define PHYA_ROBE_ROBE_HW_CONTROL_5_U__BMMU_LLM_INT_ERR_THR_MAX___S 24 +#define PHYA_ROBE_ROBE_HW_CONTROL_5_U__BMMU_LLM_INT_ERR_THR_MIN___M 0x003F0000 +#define PHYA_ROBE_ROBE_HW_CONTROL_5_U__BMMU_LLM_INT_ERR_THR_MIN___S 16 +#define PHYA_ROBE_ROBE_HW_CONTROL_5_U__BMMU_LLM_INT_ERR_THR_TIME___M 0x00003F00 +#define PHYA_ROBE_ROBE_HW_CONTROL_5_U__BMMU_LLM_INT_ERR_THR_TIME___S 8 +#define PHYA_ROBE_ROBE_HW_CONTROL_5_U__DISABLE_SHORT_GI_PKT_PARAM___M 0x00000001 +#define PHYA_ROBE_ROBE_HW_CONTROL_5_U__DISABLE_SHORT_GI_PKT_PARAM___S 0 +#define PHYA_ROBE_ROBE_HW_CONTROL_5_U___M 0x3F3F3F01 +#define PHYA_ROBE_ROBE_HW_CONTROL_5_U___S 0 + +#define PHYA_ROBE_ROBE_HW_CONTROL_6_L (0x004B5030) +#define PHYA_ROBE_ROBE_HW_CONTROL_6_L___RWC QCSR_REG_RW +#define PHYA_ROBE_ROBE_HW_CONTROL_6_L___POR 0x0F000000 +#define PHYA_ROBE_ROBE_HW_CONTROL_6_L__LSIG_6MBPS_QUAL_CHKS_EN___POR 0x0F +#define PHYA_ROBE_ROBE_HW_CONTROL_6_L__USE_ERROR_MASK_V2___POR 0x0 +#define PHYA_ROBE_ROBE_HW_CONTROL_6_L__STATIC_NUM_DISABLED_LDPC_DEC___POR 0x0 +#define PHYA_ROBE_ROBE_HW_CONTROL_6_L__STATIC_NUM_DISABLED_VIT_DEC___POR 0x0 +#define PHYA_ROBE_ROBE_HW_CONTROL_6_L__LSIG_6MBPS_QUAL_CHKS_EN___M 0xFF000000 +#define PHYA_ROBE_ROBE_HW_CONTROL_6_L__LSIG_6MBPS_QUAL_CHKS_EN___S 24 +#define PHYA_ROBE_ROBE_HW_CONTROL_6_L__USE_ERROR_MASK_V2___M 0x00010000 +#define PHYA_ROBE_ROBE_HW_CONTROL_6_L__USE_ERROR_MASK_V2___S 16 +#define PHYA_ROBE_ROBE_HW_CONTROL_6_L__STATIC_NUM_DISABLED_LDPC_DEC___M 0x00000F00 +#define PHYA_ROBE_ROBE_HW_CONTROL_6_L__STATIC_NUM_DISABLED_LDPC_DEC___S 8 +#define PHYA_ROBE_ROBE_HW_CONTROL_6_L__STATIC_NUM_DISABLED_VIT_DEC___M 0x0000000F +#define PHYA_ROBE_ROBE_HW_CONTROL_6_L__STATIC_NUM_DISABLED_VIT_DEC___S 0 +#define PHYA_ROBE_ROBE_HW_CONTROL_6_L___M 0xFF010F0F +#define PHYA_ROBE_ROBE_HW_CONTROL_6_L___S 0 + +#define PHYA_ROBE_CG_CONTROL_2_L (0x004B5038) +#define PHYA_ROBE_CG_CONTROL_2_L___RWC QCSR_REG_RW +#define PHYA_ROBE_CG_CONTROL_2_L___POR 0x00000000 +#define PHYA_ROBE_CG_CONTROL_2_L__DYN_MICRO_CGC_DISABLE_P2S___POR 0x0 +#define PHYA_ROBE_CG_CONTROL_2_L__DYN_MICRO_CGC_DISABLE_S2P___POR 0x0 +#define PHYA_ROBE_CG_CONTROL_2_L__DYN_CGC_DISABLE_P2S___POR 0x0 +#define PHYA_ROBE_CG_CONTROL_2_L__DYN_CGC_DISABLE_S2P___POR 0x0 +#define PHYA_ROBE_CG_CONTROL_2_L__DYN_MICRO_CGC_DISABLE_P2S___M 0x01000000 +#define PHYA_ROBE_CG_CONTROL_2_L__DYN_MICRO_CGC_DISABLE_P2S___S 24 +#define PHYA_ROBE_CG_CONTROL_2_L__DYN_MICRO_CGC_DISABLE_S2P___M 0x00010000 +#define PHYA_ROBE_CG_CONTROL_2_L__DYN_MICRO_CGC_DISABLE_S2P___S 16 +#define PHYA_ROBE_CG_CONTROL_2_L__DYN_CGC_DISABLE_P2S___M 0x00000100 +#define PHYA_ROBE_CG_CONTROL_2_L__DYN_CGC_DISABLE_P2S___S 8 +#define PHYA_ROBE_CG_CONTROL_2_L__DYN_CGC_DISABLE_S2P___M 0x00000001 +#define PHYA_ROBE_CG_CONTROL_2_L__DYN_CGC_DISABLE_S2P___S 0 +#define PHYA_ROBE_CG_CONTROL_2_L___M 0x01010101 +#define PHYA_ROBE_CG_CONTROL_2_L___S 0 + +#define PHYA_ROBE_CG_CONTROL_2_U (0x004B503C) +#define PHYA_ROBE_CG_CONTROL_2_U___RWC QCSR_REG_RW +#define PHYA_ROBE_CG_CONTROL_2_U___POR 0x00000000 +#define PHYA_ROBE_CG_CONTROL_2_U__DYN_MICRO_CGC_DISABLE_BMMU___POR 0x0 +#define PHYA_ROBE_CG_CONTROL_2_U__DYN_MICRO_CGC_DISABLE_LDPC___POR 0x0 +#define PHYA_ROBE_CG_CONTROL_2_U__DYN_MICRO_CGC_DISABLE_VIT___POR 0x0 +#define PHYA_ROBE_CG_CONTROL_2_U__DYN_MICRO_CGC_DISABLE_DEINT___POR 0x0 +#define PHYA_ROBE_CG_CONTROL_2_U__DYN_MICRO_CGC_DISABLE_BMMU___M 0x01000000 +#define PHYA_ROBE_CG_CONTROL_2_U__DYN_MICRO_CGC_DISABLE_BMMU___S 24 +#define PHYA_ROBE_CG_CONTROL_2_U__DYN_MICRO_CGC_DISABLE_LDPC___M 0x00010000 +#define PHYA_ROBE_CG_CONTROL_2_U__DYN_MICRO_CGC_DISABLE_LDPC___S 16 +#define PHYA_ROBE_CG_CONTROL_2_U__DYN_MICRO_CGC_DISABLE_VIT___M 0x00000100 +#define PHYA_ROBE_CG_CONTROL_2_U__DYN_MICRO_CGC_DISABLE_VIT___S 8 +#define PHYA_ROBE_CG_CONTROL_2_U__DYN_MICRO_CGC_DISABLE_DEINT___M 0x00000001 +#define PHYA_ROBE_CG_CONTROL_2_U__DYN_MICRO_CGC_DISABLE_DEINT___S 0 +#define PHYA_ROBE_CG_CONTROL_2_U___M 0x01010101 +#define PHYA_ROBE_CG_CONTROL_2_U___S 0 + +#define PHYA_ROBE_CG_CONTROL_3_L (0x004B5040) +#define PHYA_ROBE_CG_CONTROL_3_L___RWC QCSR_REG_RW +#define PHYA_ROBE_CG_CONTROL_3_L___POR 0x00000000 +#define PHYA_ROBE_CG_CONTROL_3_L__DYN_MICRO_CGC_DISABLE_DBG___POR 0x0 +#define PHYA_ROBE_CG_CONTROL_3_L__DYN_MICRO_CGC_DISABLE_SCHD___POR 0x0 +#define PHYA_ROBE_CG_CONTROL_3_L__DYN_MICRO_CGC_DISABLE_CTRL___POR 0x0 +#define PHYA_ROBE_CG_CONTROL_3_L__DYN_MICRO_CGC_DISABLE_TRFC___POR 0x0 +#define PHYA_ROBE_CG_CONTROL_3_L__DYN_MICRO_CGC_DISABLE_DBG___M 0x01000000 +#define PHYA_ROBE_CG_CONTROL_3_L__DYN_MICRO_CGC_DISABLE_DBG___S 24 +#define PHYA_ROBE_CG_CONTROL_3_L__DYN_MICRO_CGC_DISABLE_SCHD___M 0x00010000 +#define PHYA_ROBE_CG_CONTROL_3_L__DYN_MICRO_CGC_DISABLE_SCHD___S 16 +#define PHYA_ROBE_CG_CONTROL_3_L__DYN_MICRO_CGC_DISABLE_CTRL___M 0x00000100 +#define PHYA_ROBE_CG_CONTROL_3_L__DYN_MICRO_CGC_DISABLE_CTRL___S 8 +#define PHYA_ROBE_CG_CONTROL_3_L__DYN_MICRO_CGC_DISABLE_TRFC___M 0x00000001 +#define PHYA_ROBE_CG_CONTROL_3_L__DYN_MICRO_CGC_DISABLE_TRFC___S 0 +#define PHYA_ROBE_CG_CONTROL_3_L___M 0x01010101 +#define PHYA_ROBE_CG_CONTROL_3_L___S 0 + +#define PHYA_ROBE_CG_CONTROL_3_U (0x004B5044) +#define PHYA_ROBE_CG_CONTROL_3_U___RWC QCSR_REG_RW +#define PHYA_ROBE_CG_CONTROL_3_U___POR 0x00000000 +#define PHYA_ROBE_CG_CONTROL_3_U__DYN_MICRO_CGC_DISABLE_ALL___POR 0x0 +#define PHYA_ROBE_CG_CONTROL_3_U__DYN_MICRO_CGC_DISABLE_CSR___POR 0x0 +#define PHYA_ROBE_CG_CONTROL_3_U__DYN_MICRO_CGC_DISABLE_ALL___M 0x00000100 +#define PHYA_ROBE_CG_CONTROL_3_U__DYN_MICRO_CGC_DISABLE_ALL___S 8 +#define PHYA_ROBE_CG_CONTROL_3_U__DYN_MICRO_CGC_DISABLE_CSR___M 0x00000001 +#define PHYA_ROBE_CG_CONTROL_3_U__DYN_MICRO_CGC_DISABLE_CSR___S 0 +#define PHYA_ROBE_CG_CONTROL_3_U___M 0x00000101 +#define PHYA_ROBE_CG_CONTROL_3_U___S 0 + +#define PHYA_ROBE_DEBUG_CONTROL_4_L (0x004B5048) +#define PHYA_ROBE_DEBUG_CONTROL_4_L___RWC QCSR_REG_RW +#define PHYA_ROBE_DEBUG_CONTROL_4_L___POR 0x00000000 +#define PHYA_ROBE_DEBUG_CONTROL_4_L__DBG_MUX_EVENT_EN___POR 0x00 +#define PHYA_ROBE_DEBUG_CONTROL_4_L__DBG_RAW_MODE_BEFORE_ROBE_ACTIVE___POR 0x0 +#define PHYA_ROBE_DEBUG_CONTROL_4_L__DBG_MUX_RAW_MODE___POR 0x0 +#define PHYA_ROBE_DEBUG_CONTROL_4_L__DBG_MUX_SEL___POR 0x0 +#define PHYA_ROBE_DEBUG_CONTROL_4_L__BCC_IDX_FOR_DBG___POR 0x0 +#define PHYA_ROBE_DEBUG_CONTROL_4_L__LDPC_IDX_FOR_DBG___POR 0x0 +#define PHYA_ROBE_DEBUG_CONTROL_4_L__DBG_MUX_EVENT_EN___M 0x003FC000 +#define PHYA_ROBE_DEBUG_CONTROL_4_L__DBG_MUX_EVENT_EN___S 14 +#define PHYA_ROBE_DEBUG_CONTROL_4_L__DBG_RAW_MODE_BEFORE_ROBE_ACTIVE___M 0x00002000 +#define PHYA_ROBE_DEBUG_CONTROL_4_L__DBG_RAW_MODE_BEFORE_ROBE_ACTIVE___S 13 +#define PHYA_ROBE_DEBUG_CONTROL_4_L__DBG_MUX_RAW_MODE___M 0x00001000 +#define PHYA_ROBE_DEBUG_CONTROL_4_L__DBG_MUX_RAW_MODE___S 12 +#define PHYA_ROBE_DEBUG_CONTROL_4_L__DBG_MUX_SEL___M 0x00000F00 +#define PHYA_ROBE_DEBUG_CONTROL_4_L__DBG_MUX_SEL___S 8 +#define PHYA_ROBE_DEBUG_CONTROL_4_L__BCC_IDX_FOR_DBG___M 0x000000F0 +#define PHYA_ROBE_DEBUG_CONTROL_4_L__BCC_IDX_FOR_DBG___S 4 +#define PHYA_ROBE_DEBUG_CONTROL_4_L__LDPC_IDX_FOR_DBG___M 0x0000000F +#define PHYA_ROBE_DEBUG_CONTROL_4_L__LDPC_IDX_FOR_DBG___S 0 +#define PHYA_ROBE_DEBUG_CONTROL_4_L___M 0x003FFFFF +#define PHYA_ROBE_DEBUG_CONTROL_4_L___S 0 + +#define PHYA_ROBE_MAX_ITER_MUM_LST_0_L (0x004B5050) +#define PHYA_ROBE_MAX_ITER_MUM_LST_0_L___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_ITER_MUM_LST_0_L___POR 0x0A08090C +#define PHYA_ROBE_MAX_ITER_MUM_LST_0_L__MAX_ITR_MUM_LAST_MCS_3___POR 0x0A +#define PHYA_ROBE_MAX_ITER_MUM_LST_0_L__MAX_ITR_MUM_LAST_MCS_2___POR 0x08 +#define PHYA_ROBE_MAX_ITER_MUM_LST_0_L__MAX_ITR_MUM_LAST_MCS_1___POR 0x09 +#define PHYA_ROBE_MAX_ITER_MUM_LST_0_L__MAX_ITR_MUM_LAST_MCS_0___POR 0x0C +#define PHYA_ROBE_MAX_ITER_MUM_LST_0_L__MAX_ITR_MUM_LAST_MCS_3___M 0xFF000000 +#define PHYA_ROBE_MAX_ITER_MUM_LST_0_L__MAX_ITR_MUM_LAST_MCS_3___S 24 +#define PHYA_ROBE_MAX_ITER_MUM_LST_0_L__MAX_ITR_MUM_LAST_MCS_2___M 0x00FF0000 +#define PHYA_ROBE_MAX_ITER_MUM_LST_0_L__MAX_ITR_MUM_LAST_MCS_2___S 16 +#define PHYA_ROBE_MAX_ITER_MUM_LST_0_L__MAX_ITR_MUM_LAST_MCS_1___M 0x0000FF00 +#define PHYA_ROBE_MAX_ITER_MUM_LST_0_L__MAX_ITR_MUM_LAST_MCS_1___S 8 +#define PHYA_ROBE_MAX_ITER_MUM_LST_0_L__MAX_ITR_MUM_LAST_MCS_0___M 0x000000FF +#define PHYA_ROBE_MAX_ITER_MUM_LST_0_L__MAX_ITR_MUM_LAST_MCS_0___S 0 +#define PHYA_ROBE_MAX_ITER_MUM_LST_0_L___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_ITER_MUM_LST_0_L___S 0 + +#define PHYA_ROBE_MAX_ITER_MUM_LST_0_U (0x004B5054) +#define PHYA_ROBE_MAX_ITER_MUM_LST_0_U___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_ITER_MUM_LST_0_U___POR 0x0A0A0A0A +#define PHYA_ROBE_MAX_ITER_MUM_LST_0_U__MAX_ITR_MUM_LAST_MCS_7___POR 0x0A +#define PHYA_ROBE_MAX_ITER_MUM_LST_0_U__MAX_ITR_MUM_LAST_MCS_6___POR 0x0A +#define PHYA_ROBE_MAX_ITER_MUM_LST_0_U__MAX_ITR_MUM_LAST_MCS_5___POR 0x0A +#define PHYA_ROBE_MAX_ITER_MUM_LST_0_U__MAX_ITR_MUM_LAST_MCS_4___POR 0x0A +#define PHYA_ROBE_MAX_ITER_MUM_LST_0_U__MAX_ITR_MUM_LAST_MCS_7___M 0xFF000000 +#define PHYA_ROBE_MAX_ITER_MUM_LST_0_U__MAX_ITR_MUM_LAST_MCS_7___S 24 +#define PHYA_ROBE_MAX_ITER_MUM_LST_0_U__MAX_ITR_MUM_LAST_MCS_6___M 0x00FF0000 +#define PHYA_ROBE_MAX_ITER_MUM_LST_0_U__MAX_ITR_MUM_LAST_MCS_6___S 16 +#define PHYA_ROBE_MAX_ITER_MUM_LST_0_U__MAX_ITR_MUM_LAST_MCS_5___M 0x0000FF00 +#define PHYA_ROBE_MAX_ITER_MUM_LST_0_U__MAX_ITR_MUM_LAST_MCS_5___S 8 +#define PHYA_ROBE_MAX_ITER_MUM_LST_0_U__MAX_ITR_MUM_LAST_MCS_4___M 0x000000FF +#define PHYA_ROBE_MAX_ITER_MUM_LST_0_U__MAX_ITR_MUM_LAST_MCS_4___S 0 +#define PHYA_ROBE_MAX_ITER_MUM_LST_0_U___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_ITER_MUM_LST_0_U___S 0 + +#define PHYA_ROBE_MAX_ITER_MUM_LST_1_L (0x004B5058) +#define PHYA_ROBE_MAX_ITER_MUM_LST_1_L___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_ITER_MUM_LST_1_L___POR 0x0A0A0A0A +#define PHYA_ROBE_MAX_ITER_MUM_LST_1_L__MAX_ITR_MUM_LAST_MCS_11___POR 0x0A +#define PHYA_ROBE_MAX_ITER_MUM_LST_1_L__MAX_ITR_MUM_LAST_MCS_10___POR 0x0A +#define PHYA_ROBE_MAX_ITER_MUM_LST_1_L__MAX_ITR_MUM_LAST_MCS_9___POR 0x0A +#define PHYA_ROBE_MAX_ITER_MUM_LST_1_L__MAX_ITR_MUM_LAST_MCS_8___POR 0x0A +#define PHYA_ROBE_MAX_ITER_MUM_LST_1_L__MAX_ITR_MUM_LAST_MCS_11___M 0xFF000000 +#define PHYA_ROBE_MAX_ITER_MUM_LST_1_L__MAX_ITR_MUM_LAST_MCS_11___S 24 +#define PHYA_ROBE_MAX_ITER_MUM_LST_1_L__MAX_ITR_MUM_LAST_MCS_10___M 0x00FF0000 +#define PHYA_ROBE_MAX_ITER_MUM_LST_1_L__MAX_ITR_MUM_LAST_MCS_10___S 16 +#define PHYA_ROBE_MAX_ITER_MUM_LST_1_L__MAX_ITR_MUM_LAST_MCS_9___M 0x0000FF00 +#define PHYA_ROBE_MAX_ITER_MUM_LST_1_L__MAX_ITR_MUM_LAST_MCS_9___S 8 +#define PHYA_ROBE_MAX_ITER_MUM_LST_1_L__MAX_ITR_MUM_LAST_MCS_8___M 0x000000FF +#define PHYA_ROBE_MAX_ITER_MUM_LST_1_L__MAX_ITR_MUM_LAST_MCS_8___S 0 +#define PHYA_ROBE_MAX_ITER_MUM_LST_1_L___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_ITER_MUM_LST_1_L___S 0 + +#define PHYA_ROBE_MAX_ITER_MUM_LST_1_U (0x004B505C) +#define PHYA_ROBE_MAX_ITER_MUM_LST_1_U___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_ITER_MUM_LST_1_U___POR 0x0A0A0A0A +#define PHYA_ROBE_MAX_ITER_MUM_LST_1_U__MAX_ITR_MUM_LAST_MCS_15___POR 0x0A +#define PHYA_ROBE_MAX_ITER_MUM_LST_1_U__MAX_ITR_MUM_LAST_MCS_14___POR 0x0A +#define PHYA_ROBE_MAX_ITER_MUM_LST_1_U__MAX_ITR_MUM_LAST_MCS_13___POR 0x0A +#define PHYA_ROBE_MAX_ITER_MUM_LST_1_U__MAX_ITR_MUM_LAST_MCS_12___POR 0x0A +#define PHYA_ROBE_MAX_ITER_MUM_LST_1_U__MAX_ITR_MUM_LAST_MCS_15___M 0xFF000000 +#define PHYA_ROBE_MAX_ITER_MUM_LST_1_U__MAX_ITR_MUM_LAST_MCS_15___S 24 +#define PHYA_ROBE_MAX_ITER_MUM_LST_1_U__MAX_ITR_MUM_LAST_MCS_14___M 0x00FF0000 +#define PHYA_ROBE_MAX_ITER_MUM_LST_1_U__MAX_ITR_MUM_LAST_MCS_14___S 16 +#define PHYA_ROBE_MAX_ITER_MUM_LST_1_U__MAX_ITR_MUM_LAST_MCS_13___M 0x0000FF00 +#define PHYA_ROBE_MAX_ITER_MUM_LST_1_U__MAX_ITR_MUM_LAST_MCS_13___S 8 +#define PHYA_ROBE_MAX_ITER_MUM_LST_1_U__MAX_ITR_MUM_LAST_MCS_12___M 0x000000FF +#define PHYA_ROBE_MAX_ITER_MUM_LST_1_U__MAX_ITR_MUM_LAST_MCS_12___S 0 +#define PHYA_ROBE_MAX_ITER_MUM_LST_1_U___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_ITER_MUM_LST_1_U___S 0 + +#define PHYA_ROBE_MAX_ITER_MUO_LST_0_L (0x004B5060) +#define PHYA_ROBE_MAX_ITER_MUO_LST_0_L___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_ITER_MUO_LST_0_L___POR 0x0A08090C +#define PHYA_ROBE_MAX_ITER_MUO_LST_0_L__MAX_ITR_MUO_LAST_MCS_3___POR 0x0A +#define PHYA_ROBE_MAX_ITER_MUO_LST_0_L__MAX_ITR_MUO_LAST_MCS_2___POR 0x08 +#define PHYA_ROBE_MAX_ITER_MUO_LST_0_L__MAX_ITR_MUO_LAST_MCS_1___POR 0x09 +#define PHYA_ROBE_MAX_ITER_MUO_LST_0_L__MAX_ITR_MUO_LAST_MCS_0___POR 0x0C +#define PHYA_ROBE_MAX_ITER_MUO_LST_0_L__MAX_ITR_MUO_LAST_MCS_3___M 0xFF000000 +#define PHYA_ROBE_MAX_ITER_MUO_LST_0_L__MAX_ITR_MUO_LAST_MCS_3___S 24 +#define PHYA_ROBE_MAX_ITER_MUO_LST_0_L__MAX_ITR_MUO_LAST_MCS_2___M 0x00FF0000 +#define PHYA_ROBE_MAX_ITER_MUO_LST_0_L__MAX_ITR_MUO_LAST_MCS_2___S 16 +#define PHYA_ROBE_MAX_ITER_MUO_LST_0_L__MAX_ITR_MUO_LAST_MCS_1___M 0x0000FF00 +#define PHYA_ROBE_MAX_ITER_MUO_LST_0_L__MAX_ITR_MUO_LAST_MCS_1___S 8 +#define PHYA_ROBE_MAX_ITER_MUO_LST_0_L__MAX_ITR_MUO_LAST_MCS_0___M 0x000000FF +#define PHYA_ROBE_MAX_ITER_MUO_LST_0_L__MAX_ITR_MUO_LAST_MCS_0___S 0 +#define PHYA_ROBE_MAX_ITER_MUO_LST_0_L___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_ITER_MUO_LST_0_L___S 0 + +#define PHYA_ROBE_MAX_ITER_MUO_LST_0_U (0x004B5064) +#define PHYA_ROBE_MAX_ITER_MUO_LST_0_U___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_ITER_MUO_LST_0_U___POR 0x0A0A0A0A +#define PHYA_ROBE_MAX_ITER_MUO_LST_0_U__MAX_ITR_MUO_LAST_MCS_7___POR 0x0A +#define PHYA_ROBE_MAX_ITER_MUO_LST_0_U__MAX_ITR_MUO_LAST_MCS_6___POR 0x0A +#define PHYA_ROBE_MAX_ITER_MUO_LST_0_U__MAX_ITR_MUO_LAST_MCS_5___POR 0x0A +#define PHYA_ROBE_MAX_ITER_MUO_LST_0_U__MAX_ITR_MUO_LAST_MCS_4___POR 0x0A +#define PHYA_ROBE_MAX_ITER_MUO_LST_0_U__MAX_ITR_MUO_LAST_MCS_7___M 0xFF000000 +#define PHYA_ROBE_MAX_ITER_MUO_LST_0_U__MAX_ITR_MUO_LAST_MCS_7___S 24 +#define PHYA_ROBE_MAX_ITER_MUO_LST_0_U__MAX_ITR_MUO_LAST_MCS_6___M 0x00FF0000 +#define PHYA_ROBE_MAX_ITER_MUO_LST_0_U__MAX_ITR_MUO_LAST_MCS_6___S 16 +#define PHYA_ROBE_MAX_ITER_MUO_LST_0_U__MAX_ITR_MUO_LAST_MCS_5___M 0x0000FF00 +#define PHYA_ROBE_MAX_ITER_MUO_LST_0_U__MAX_ITR_MUO_LAST_MCS_5___S 8 +#define PHYA_ROBE_MAX_ITER_MUO_LST_0_U__MAX_ITR_MUO_LAST_MCS_4___M 0x000000FF +#define PHYA_ROBE_MAX_ITER_MUO_LST_0_U__MAX_ITR_MUO_LAST_MCS_4___S 0 +#define PHYA_ROBE_MAX_ITER_MUO_LST_0_U___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_ITER_MUO_LST_0_U___S 0 + +#define PHYA_ROBE_MAX_ITER_MUO_LST_1_L (0x004B5068) +#define PHYA_ROBE_MAX_ITER_MUO_LST_1_L___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_ITER_MUO_LST_1_L___POR 0x0A0A0A0A +#define PHYA_ROBE_MAX_ITER_MUO_LST_1_L__MAX_ITR_MUO_LAST_MCS_11___POR 0x0A +#define PHYA_ROBE_MAX_ITER_MUO_LST_1_L__MAX_ITR_MUO_LAST_MCS_10___POR 0x0A +#define PHYA_ROBE_MAX_ITER_MUO_LST_1_L__MAX_ITR_MUO_LAST_MCS_9___POR 0x0A +#define PHYA_ROBE_MAX_ITER_MUO_LST_1_L__MAX_ITR_MUO_LAST_MCS_8___POR 0x0A +#define PHYA_ROBE_MAX_ITER_MUO_LST_1_L__MAX_ITR_MUO_LAST_MCS_11___M 0xFF000000 +#define PHYA_ROBE_MAX_ITER_MUO_LST_1_L__MAX_ITR_MUO_LAST_MCS_11___S 24 +#define PHYA_ROBE_MAX_ITER_MUO_LST_1_L__MAX_ITR_MUO_LAST_MCS_10___M 0x00FF0000 +#define PHYA_ROBE_MAX_ITER_MUO_LST_1_L__MAX_ITR_MUO_LAST_MCS_10___S 16 +#define PHYA_ROBE_MAX_ITER_MUO_LST_1_L__MAX_ITR_MUO_LAST_MCS_9___M 0x0000FF00 +#define PHYA_ROBE_MAX_ITER_MUO_LST_1_L__MAX_ITR_MUO_LAST_MCS_9___S 8 +#define PHYA_ROBE_MAX_ITER_MUO_LST_1_L__MAX_ITR_MUO_LAST_MCS_8___M 0x000000FF +#define PHYA_ROBE_MAX_ITER_MUO_LST_1_L__MAX_ITR_MUO_LAST_MCS_8___S 0 +#define PHYA_ROBE_MAX_ITER_MUO_LST_1_L___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_ITER_MUO_LST_1_L___S 0 + +#define PHYA_ROBE_MAX_ITER_MUO_LST_1_U (0x004B506C) +#define PHYA_ROBE_MAX_ITER_MUO_LST_1_U___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_ITER_MUO_LST_1_U___POR 0x0A0A0A0A +#define PHYA_ROBE_MAX_ITER_MUO_LST_1_U__MAX_ITR_MUO_LAST_MCS_15___POR 0x0A +#define PHYA_ROBE_MAX_ITER_MUO_LST_1_U__MAX_ITR_MUO_LAST_MCS_14___POR 0x0A +#define PHYA_ROBE_MAX_ITER_MUO_LST_1_U__MAX_ITR_MUO_LAST_MCS_13___POR 0x0A +#define PHYA_ROBE_MAX_ITER_MUO_LST_1_U__MAX_ITR_MUO_LAST_MCS_12___POR 0x0A +#define PHYA_ROBE_MAX_ITER_MUO_LST_1_U__MAX_ITR_MUO_LAST_MCS_15___M 0xFF000000 +#define PHYA_ROBE_MAX_ITER_MUO_LST_1_U__MAX_ITR_MUO_LAST_MCS_15___S 24 +#define PHYA_ROBE_MAX_ITER_MUO_LST_1_U__MAX_ITR_MUO_LAST_MCS_14___M 0x00FF0000 +#define PHYA_ROBE_MAX_ITER_MUO_LST_1_U__MAX_ITR_MUO_LAST_MCS_14___S 16 +#define PHYA_ROBE_MAX_ITER_MUO_LST_1_U__MAX_ITR_MUO_LAST_MCS_13___M 0x0000FF00 +#define PHYA_ROBE_MAX_ITER_MUO_LST_1_U__MAX_ITR_MUO_LAST_MCS_13___S 8 +#define PHYA_ROBE_MAX_ITER_MUO_LST_1_U__MAX_ITR_MUO_LAST_MCS_12___M 0x000000FF +#define PHYA_ROBE_MAX_ITER_MUO_LST_1_U__MAX_ITR_MUO_LAST_MCS_12___S 0 +#define PHYA_ROBE_MAX_ITER_MUO_LST_1_U___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_ITER_MUO_LST_1_U___S 0 + +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_L (0x004B5070) +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_L___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_L___POR 0x0A08090C +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_L__MAX_ITR_SPECIAL_PKT_MCS_3___POR 0x0A +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_L__MAX_ITR_SPECIAL_PKT_MCS_2___POR 0x08 +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_L__MAX_ITR_SPECIAL_PKT_MCS_1___POR 0x09 +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_L__MAX_ITR_SPECIAL_PKT_MCS_0___POR 0x0C +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_L__MAX_ITR_SPECIAL_PKT_MCS_3___M 0xFF000000 +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_L__MAX_ITR_SPECIAL_PKT_MCS_3___S 24 +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_L__MAX_ITR_SPECIAL_PKT_MCS_2___M 0x00FF0000 +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_L__MAX_ITR_SPECIAL_PKT_MCS_2___S 16 +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_L__MAX_ITR_SPECIAL_PKT_MCS_1___M 0x0000FF00 +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_L__MAX_ITR_SPECIAL_PKT_MCS_1___S 8 +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_L__MAX_ITR_SPECIAL_PKT_MCS_0___M 0x000000FF +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_L__MAX_ITR_SPECIAL_PKT_MCS_0___S 0 +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_L___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_L___S 0 + +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_U (0x004B5074) +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_U___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_U___POR 0x0A0A0A0A +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_U__MAX_ITR_SPECIAL_PKT_MCS_7___POR 0x0A +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_U__MAX_ITR_SPECIAL_PKT_MCS_6___POR 0x0A +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_U__MAX_ITR_SPECIAL_PKT_MCS_5___POR 0x0A +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_U__MAX_ITR_SPECIAL_PKT_MCS_4___POR 0x0A +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_U__MAX_ITR_SPECIAL_PKT_MCS_7___M 0xFF000000 +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_U__MAX_ITR_SPECIAL_PKT_MCS_7___S 24 +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_U__MAX_ITR_SPECIAL_PKT_MCS_6___M 0x00FF0000 +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_U__MAX_ITR_SPECIAL_PKT_MCS_6___S 16 +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_U__MAX_ITR_SPECIAL_PKT_MCS_5___M 0x0000FF00 +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_U__MAX_ITR_SPECIAL_PKT_MCS_5___S 8 +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_U__MAX_ITR_SPECIAL_PKT_MCS_4___M 0x000000FF +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_U__MAX_ITR_SPECIAL_PKT_MCS_4___S 0 +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_U___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_0_U___S 0 + +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_L (0x004B5078) +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_L___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_L___POR 0x0A0A0A0A +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_L__MAX_ITR_SPECIAL_PKT_MCS_11___POR 0x0A +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_L__MAX_ITR_SPECIAL_PKT_MCS_10___POR 0x0A +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_L__MAX_ITR_SPECIAL_PKT_MCS_9___POR 0x0A +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_L__MAX_ITR_SPECIAL_PKT_MCS_8___POR 0x0A +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_L__MAX_ITR_SPECIAL_PKT_MCS_11___M 0xFF000000 +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_L__MAX_ITR_SPECIAL_PKT_MCS_11___S 24 +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_L__MAX_ITR_SPECIAL_PKT_MCS_10___M 0x00FF0000 +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_L__MAX_ITR_SPECIAL_PKT_MCS_10___S 16 +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_L__MAX_ITR_SPECIAL_PKT_MCS_9___M 0x0000FF00 +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_L__MAX_ITR_SPECIAL_PKT_MCS_9___S 8 +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_L__MAX_ITR_SPECIAL_PKT_MCS_8___M 0x000000FF +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_L__MAX_ITR_SPECIAL_PKT_MCS_8___S 0 +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_L___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_L___S 0 + +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_U (0x004B507C) +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_U___RWC QCSR_REG_RW +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_U___POR 0x0A0A0A0A +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_U__MAX_ITR_SPECIAL_PKT_MCS_15___POR 0x0A +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_U__MAX_ITR_SPECIAL_PKT_MCS_14___POR 0x0A +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_U__MAX_ITR_SPECIAL_PKT_MCS_13___POR 0x0A +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_U__MAX_ITR_SPECIAL_PKT_MCS_12___POR 0x0A +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_U__MAX_ITR_SPECIAL_PKT_MCS_15___M 0xFF000000 +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_U__MAX_ITR_SPECIAL_PKT_MCS_15___S 24 +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_U__MAX_ITR_SPECIAL_PKT_MCS_14___M 0x00FF0000 +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_U__MAX_ITR_SPECIAL_PKT_MCS_14___S 16 +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_U__MAX_ITR_SPECIAL_PKT_MCS_13___M 0x0000FF00 +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_U__MAX_ITR_SPECIAL_PKT_MCS_13___S 8 +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_U__MAX_ITR_SPECIAL_PKT_MCS_12___M 0x000000FF +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_U__MAX_ITR_SPECIAL_PKT_MCS_12___S 0 +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_U___M 0xFFFFFFFF +#define PHYA_ROBE_MAX_ITER_SPECIAL_PKT_1_U___S 0 + +#define PHYA_ROBE_SIG_INTG_CHK_EN_0_L (0x004B5080) +#define PHYA_ROBE_SIG_INTG_CHK_EN_0_L___RWC QCSR_REG_RW +#define PHYA_ROBE_SIG_INTG_CHK_EN_0_L___POR 0x01010101 +#define PHYA_ROBE_SIG_INTG_CHK_EN_0_L__EN_RLSIG_RATE_CHK___POR 0x1 +#define PHYA_ROBE_SIG_INTG_CHK_EN_0_L__EN_RLSIG_LENGTH_CHK___POR 0x1 +#define PHYA_ROBE_SIG_INTG_CHK_EN_0_L__EN_LSIG_RATE_CHK___POR 0x1 +#define PHYA_ROBE_SIG_INTG_CHK_EN_0_L__EN_LSIG_LENGTH_CHK___POR 0x1 +#define PHYA_ROBE_SIG_INTG_CHK_EN_0_L__EN_RLSIG_RATE_CHK___M 0x01000000 +#define PHYA_ROBE_SIG_INTG_CHK_EN_0_L__EN_RLSIG_RATE_CHK___S 24 +#define PHYA_ROBE_SIG_INTG_CHK_EN_0_L__EN_RLSIG_LENGTH_CHK___M 0x00010000 +#define PHYA_ROBE_SIG_INTG_CHK_EN_0_L__EN_RLSIG_LENGTH_CHK___S 16 +#define PHYA_ROBE_SIG_INTG_CHK_EN_0_L__EN_LSIG_RATE_CHK___M 0x00000100 +#define PHYA_ROBE_SIG_INTG_CHK_EN_0_L__EN_LSIG_RATE_CHK___S 8 +#define PHYA_ROBE_SIG_INTG_CHK_EN_0_L__EN_LSIG_LENGTH_CHK___M 0x00000001 +#define PHYA_ROBE_SIG_INTG_CHK_EN_0_L__EN_LSIG_LENGTH_CHK___S 0 +#define PHYA_ROBE_SIG_INTG_CHK_EN_0_L___M 0x01010101 +#define PHYA_ROBE_SIG_INTG_CHK_EN_0_L___S 0 + +#define PHYA_ROBE_SIG_INTG_CHK_EN_0_U (0x004B5084) +#define PHYA_ROBE_SIG_INTG_CHK_EN_0_U___RWC QCSR_REG_RW +#define PHYA_ROBE_SIG_INTG_CHK_EN_0_U___POR 0x01010101 +#define PHYA_ROBE_SIG_INTG_CHK_EN_0_U__EN_HTSIG_STBC_MCS_CHK___POR 0x1 +#define PHYA_ROBE_SIG_INTG_CHK_EN_0_U__EN_HTSIG_STBC_VAL_CHK___POR 0x1 +#define PHYA_ROBE_SIG_INTG_CHK_EN_0_U__EN_HTSIG_RESERVED_CHK___POR 0x1 +#define PHYA_ROBE_SIG_INTG_CHK_EN_0_U__EN_HTSIG_MCS_CHK___POR 0x1 +#define PHYA_ROBE_SIG_INTG_CHK_EN_0_U__EN_HTSIG_STBC_MCS_CHK___M 0x01000000 +#define PHYA_ROBE_SIG_INTG_CHK_EN_0_U__EN_HTSIG_STBC_MCS_CHK___S 24 +#define PHYA_ROBE_SIG_INTG_CHK_EN_0_U__EN_HTSIG_STBC_VAL_CHK___M 0x00010000 +#define PHYA_ROBE_SIG_INTG_CHK_EN_0_U__EN_HTSIG_STBC_VAL_CHK___S 16 +#define PHYA_ROBE_SIG_INTG_CHK_EN_0_U__EN_HTSIG_RESERVED_CHK___M 0x00000100 +#define PHYA_ROBE_SIG_INTG_CHK_EN_0_U__EN_HTSIG_RESERVED_CHK___S 8 +#define PHYA_ROBE_SIG_INTG_CHK_EN_0_U__EN_HTSIG_MCS_CHK___M 0x00000001 +#define PHYA_ROBE_SIG_INTG_CHK_EN_0_U__EN_HTSIG_MCS_CHK___S 0 +#define PHYA_ROBE_SIG_INTG_CHK_EN_0_U___M 0x01010101 +#define PHYA_ROBE_SIG_INTG_CHK_EN_0_U___S 0 + +#define PHYA_ROBE_SIG_INTG_CHK_EN_1_L (0x004B5088) +#define PHYA_ROBE_SIG_INTG_CHK_EN_1_L___RWC QCSR_REG_RW +#define PHYA_ROBE_SIG_INTG_CHK_EN_1_L___POR 0x01010101 +#define PHYA_ROBE_SIG_INTG_CHK_EN_1_L__EN_VHTSIGA_RESERVED_CHK___POR 0x1 +#define PHYA_ROBE_SIG_INTG_CHK_EN_1_L__EN_VHTSIGA_MCS_CHK___POR 0x1 +#define PHYA_ROBE_SIG_INTG_CHK_EN_1_L__EN_HTSIG_NESS_CHK___POR 0x1 +#define PHYA_ROBE_SIG_INTG_CHK_EN_1_L__EN_HTSIG_NOT_SOUNDING_CHK___POR 0x1 +#define PHYA_ROBE_SIG_INTG_CHK_EN_1_L__EN_VHTSIGA_RESERVED_CHK___M 0x01000000 +#define PHYA_ROBE_SIG_INTG_CHK_EN_1_L__EN_VHTSIGA_RESERVED_CHK___S 24 +#define PHYA_ROBE_SIG_INTG_CHK_EN_1_L__EN_VHTSIGA_MCS_CHK___M 0x00010000 +#define PHYA_ROBE_SIG_INTG_CHK_EN_1_L__EN_VHTSIGA_MCS_CHK___S 16 +#define PHYA_ROBE_SIG_INTG_CHK_EN_1_L__EN_HTSIG_NESS_CHK___M 0x00000100 +#define PHYA_ROBE_SIG_INTG_CHK_EN_1_L__EN_HTSIG_NESS_CHK___S 8 +#define PHYA_ROBE_SIG_INTG_CHK_EN_1_L__EN_HTSIG_NOT_SOUNDING_CHK___M 0x00000001 +#define PHYA_ROBE_SIG_INTG_CHK_EN_1_L__EN_HTSIG_NOT_SOUNDING_CHK___S 0 +#define PHYA_ROBE_SIG_INTG_CHK_EN_1_L___M 0x01010101 +#define PHYA_ROBE_SIG_INTG_CHK_EN_1_L___S 0 + +#define PHYA_ROBE_SIG_INTG_CHK_EN_1_U (0x004B508C) +#define PHYA_ROBE_SIG_INTG_CHK_EN_1_U___RWC QCSR_REG_RW +#define PHYA_ROBE_SIG_INTG_CHK_EN_1_U___POR 0x01010101 +#define PHYA_ROBE_SIG_INTG_CHK_EN_1_U__EN_VHTSIGA_MU_NSTS_CHK___POR 0x1 +#define PHYA_ROBE_SIG_INTG_CHK_EN_1_U__EN_VHTSIGA_SU_EXTRASYM_CHK___POR 0x1 +#define PHYA_ROBE_SIG_INTG_CHK_EN_1_U__EN_VHTSIGA_SGI_DISAMBG_CHK___POR 0x1 +#define PHYA_ROBE_SIG_INTG_CHK_EN_1_U__EN_VHTSIGA_SBC_MU_CHK___POR 0x1 +#define PHYA_ROBE_SIG_INTG_CHK_EN_1_U__EN_VHTSIGA_MU_NSTS_CHK___M 0x01000000 +#define PHYA_ROBE_SIG_INTG_CHK_EN_1_U__EN_VHTSIGA_MU_NSTS_CHK___S 24 +#define PHYA_ROBE_SIG_INTG_CHK_EN_1_U__EN_VHTSIGA_SU_EXTRASYM_CHK___M 0x00010000 +#define PHYA_ROBE_SIG_INTG_CHK_EN_1_U__EN_VHTSIGA_SU_EXTRASYM_CHK___S 16 +#define PHYA_ROBE_SIG_INTG_CHK_EN_1_U__EN_VHTSIGA_SGI_DISAMBG_CHK___M 0x00000100 +#define PHYA_ROBE_SIG_INTG_CHK_EN_1_U__EN_VHTSIGA_SGI_DISAMBG_CHK___S 8 +#define PHYA_ROBE_SIG_INTG_CHK_EN_1_U__EN_VHTSIGA_SBC_MU_CHK___M 0x00000001 +#define PHYA_ROBE_SIG_INTG_CHK_EN_1_U__EN_VHTSIGA_SBC_MU_CHK___S 0 +#define PHYA_ROBE_SIG_INTG_CHK_EN_1_U___M 0x01010101 +#define PHYA_ROBE_SIG_INTG_CHK_EN_1_U___S 0 + +#define PHYA_ROBE_SIG_INTG_CHK_EN_2_L (0x004B5090) +#define PHYA_ROBE_SIG_INTG_CHK_EN_2_L___RWC QCSR_REG_RW +#define PHYA_ROBE_SIG_INTG_CHK_EN_2_L___POR 0x01010101 +#define PHYA_ROBE_SIG_INTG_CHK_EN_2_L__EN_VHTSIGA_STBC_NSTS_CHK___POR 0x1 +#define PHYA_ROBE_SIG_INTG_CHK_EN_2_L__EN_VHTSIGA_MU_BEAMFORMED_CHK___POR 0x1 +#define PHYA_ROBE_SIG_INTG_CHK_EN_2_L__EN_VHTSIGA_MU_EXTRASYM_CHK___POR 0x1 +#define PHYA_ROBE_SIG_INTG_CHK_EN_2_L__EN_VHTSIGA_MU_CODING_CHK___POR 0x1 +#define PHYA_ROBE_SIG_INTG_CHK_EN_2_L__EN_VHTSIGA_STBC_NSTS_CHK___M 0x01000000 +#define PHYA_ROBE_SIG_INTG_CHK_EN_2_L__EN_VHTSIGA_STBC_NSTS_CHK___S 24 +#define PHYA_ROBE_SIG_INTG_CHK_EN_2_L__EN_VHTSIGA_MU_BEAMFORMED_CHK___M 0x00010000 +#define PHYA_ROBE_SIG_INTG_CHK_EN_2_L__EN_VHTSIGA_MU_BEAMFORMED_CHK___S 16 +#define PHYA_ROBE_SIG_INTG_CHK_EN_2_L__EN_VHTSIGA_MU_EXTRASYM_CHK___M 0x00000100 +#define PHYA_ROBE_SIG_INTG_CHK_EN_2_L__EN_VHTSIGA_MU_EXTRASYM_CHK___S 8 +#define PHYA_ROBE_SIG_INTG_CHK_EN_2_L__EN_VHTSIGA_MU_CODING_CHK___M 0x00000001 +#define PHYA_ROBE_SIG_INTG_CHK_EN_2_L__EN_VHTSIGA_MU_CODING_CHK___S 0 +#define PHYA_ROBE_SIG_INTG_CHK_EN_2_L___M 0x01010101 +#define PHYA_ROBE_SIG_INTG_CHK_EN_2_L___S 0 + +#define PHYA_ROBE_SIG_INTG_CHK_THR_L (0x004B5098) +#define PHYA_ROBE_SIG_INTG_CHK_THR_L___RWC QCSR_REG_RW +#define PHYA_ROBE_SIG_INTG_CHK_THR_L___POR 0x0FFF0000 +#define PHYA_ROBE_SIG_INTG_CHK_THR_L__LSIG_MAX_LENGTH___POR 0xFFF +#define PHYA_ROBE_SIG_INTG_CHK_THR_L__LSIG_MIN_LENGTH___POR 0x000 +#define PHYA_ROBE_SIG_INTG_CHK_THR_L__LSIG_MAX_LENGTH___M 0x0FFF0000 +#define PHYA_ROBE_SIG_INTG_CHK_THR_L__LSIG_MAX_LENGTH___S 16 +#define PHYA_ROBE_SIG_INTG_CHK_THR_L__LSIG_MIN_LENGTH___M 0x00000FFF +#define PHYA_ROBE_SIG_INTG_CHK_THR_L__LSIG_MIN_LENGTH___S 0 +#define PHYA_ROBE_SIG_INTG_CHK_THR_L___M 0x0FFF0FFF +#define PHYA_ROBE_SIG_INTG_CHK_THR_L___S 0 + +#define PHYA_ROBE_SIG_INTG_CHK_THR_U (0x004B509C) +#define PHYA_ROBE_SIG_INTG_CHK_THR_U___RWC QCSR_REG_RW +#define PHYA_ROBE_SIG_INTG_CHK_THR_U___POR 0x0000001F +#define PHYA_ROBE_SIG_INTG_CHK_THR_U__HTSIG_MAX_MCS___POR 0x1F +#define PHYA_ROBE_SIG_INTG_CHK_THR_U__HTSIG_MAX_MCS___M 0x0000007F +#define PHYA_ROBE_SIG_INTG_CHK_THR_U__HTSIG_MAX_MCS___S 0 +#define PHYA_ROBE_SIG_INTG_CHK_THR_U___M 0x0000007F +#define PHYA_ROBE_SIG_INTG_CHK_THR_U___S 0 + +#define PHYA_ROBE_ADV_HW_CONTROL_L (0x004B50A0) +#define PHYA_ROBE_ADV_HW_CONTROL_L___RWC QCSR_REG_RW +#define PHYA_ROBE_ADV_HW_CONTROL_L___POR 0x00000000 +#define PHYA_ROBE_ADV_HW_CONTROL_L__DEC_PWR_DOWN_COST_THR___POR 0x0000 +#define PHYA_ROBE_ADV_HW_CONTROL_L__EN_DYN_DEC_PWR_DOWN___POR 0x0 +#define PHYA_ROBE_ADV_HW_CONTROL_L__ROBE_LATENCY_LIMIT_100NS___POR 0x00 +#define PHYA_ROBE_ADV_HW_CONTROL_L__DEC_PWR_DOWN_COST_THR___M 0xFFFF0000 +#define PHYA_ROBE_ADV_HW_CONTROL_L__DEC_PWR_DOWN_COST_THR___S 16 +#define PHYA_ROBE_ADV_HW_CONTROL_L__EN_DYN_DEC_PWR_DOWN___M 0x00000100 +#define PHYA_ROBE_ADV_HW_CONTROL_L__EN_DYN_DEC_PWR_DOWN___S 8 +#define PHYA_ROBE_ADV_HW_CONTROL_L__ROBE_LATENCY_LIMIT_100NS___M 0x000000FF +#define PHYA_ROBE_ADV_HW_CONTROL_L__ROBE_LATENCY_LIMIT_100NS___S 0 +#define PHYA_ROBE_ADV_HW_CONTROL_L___M 0xFFFF01FF +#define PHYA_ROBE_ADV_HW_CONTROL_L___S 0 + +#define PHYA_ROBE_ADV_HW_CONTROL_U (0x004B50A4) +#define PHYA_ROBE_ADV_HW_CONTROL_U___RWC QCSR_REG_RW +#define PHYA_ROBE_ADV_HW_CONTROL_U___POR 0x00000000 +#define PHYA_ROBE_ADV_HW_CONTROL_U__BMMU_USER_FILL_THR___POR 0x0000 +#define PHYA_ROBE_ADV_HW_CONTROL_U__EN_DYN_LDPC_TERMINATION___POR 0x0 +#define PHYA_ROBE_ADV_HW_CONTROL_U__BMMU_USER_FILL_THR___M 0x3FFF0000 +#define PHYA_ROBE_ADV_HW_CONTROL_U__BMMU_USER_FILL_THR___S 16 +#define PHYA_ROBE_ADV_HW_CONTROL_U__EN_DYN_LDPC_TERMINATION___M 0x00000001 +#define PHYA_ROBE_ADV_HW_CONTROL_U__EN_DYN_LDPC_TERMINATION___S 0 +#define PHYA_ROBE_ADV_HW_CONTROL_U___M 0x3FFF0001 +#define PHYA_ROBE_ADV_HW_CONTROL_U___S 0 + +#define PHYA_ROBE_ALIAS_DUMMY_L (0x004B7FF0) +#define PHYA_ROBE_ALIAS_DUMMY_L___RWC QCSR_REG_RW +#define PHYA_ROBE_ALIAS_DUMMY_L___POR 0x00000000 +#define PHYA_ROBE_ALIAS_DUMMY_L__ROBE_PMI_ALIAS_DUMMY___POR 0x0 +#define PHYA_ROBE_ALIAS_DUMMY_L__ROBE_PMI_ALIAS_DUMMY___M 0x00000001 +#define PHYA_ROBE_ALIAS_DUMMY_L__ROBE_PMI_ALIAS_DUMMY___S 0 +#define PHYA_ROBE_ALIAS_DUMMY_L___M 0x00000001 +#define PHYA_ROBE_ALIAS_DUMMY_L___S 0 + +#define PHYA_DEMFRONT_1_RESET_CTRL_L (0x00500000) +#define PHYA_DEMFRONT_1_RESET_CTRL_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RESET_CTRL_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RESET_CTRL_L__DYNAMIC_REGS_RESET___POR 0x0 +#define PHYA_DEMFRONT_1_RESET_CTRL_L__DYNAMIC_REGS_RESET___M 0x00000001 +#define PHYA_DEMFRONT_1_RESET_CTRL_L__DYNAMIC_REGS_RESET___S 0 +#define PHYA_DEMFRONT_1_RESET_CTRL_L___M 0x00000001 +#define PHYA_DEMFRONT_1_RESET_CTRL_L___S 0 + +#define PHYA_DEMFRONT_1_ECO_RESET_CTRL_L (0x00500008) +#define PHYA_DEMFRONT_1_ECO_RESET_CTRL_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_ECO_RESET_CTRL_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_ECO_RESET_CTRL_L__ECO_CTRL___POR 0x00000000 +#define PHYA_DEMFRONT_1_ECO_RESET_CTRL_L__ECO_CTRL___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_ECO_RESET_CTRL_L__ECO_CTRL___S 0 +#define PHYA_DEMFRONT_1_ECO_RESET_CTRL_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_ECO_RESET_CTRL_L___S 0 + +#define PHYA_DEMFRONT_1_ECO_RESET_CTRL_U (0x0050000C) +#define PHYA_DEMFRONT_1_ECO_RESET_CTRL_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_ECO_RESET_CTRL_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_ECO_RESET_CTRL_U__ECO_DATA___POR 0x00000000 +#define PHYA_DEMFRONT_1_ECO_RESET_CTRL_U__ECO_DATA___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_ECO_RESET_CTRL_U__ECO_DATA___S 0 +#define PHYA_DEMFRONT_1_ECO_RESET_CTRL_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_ECO_RESET_CTRL_U___S 0 + +#define PHYA_DEMFRONT_1_EVENT_STATUS_L (0x00500010) +#define PHYA_DEMFRONT_1_EVENT_STATUS_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_EVENT_STATUS_L___POR 0x000000C4 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__SPARE15_EVENT___POR 0x0 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__SPARE14_EVENT___POR 0x0 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__SPARE13_EVENT___POR 0x0 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__SPARE12_EVENT___POR 0x0 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__PER_PKT_PROGRAM_EVENT___POR 0x0 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__RU_BD_PTC_HW_UPDATE_EVENT___POR 0x0 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__PROC_COMPLETE_EVENT___POR 0x0 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__RXTD_NOISEPWR_BTCF_EVENT___POR 0x1 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__RXTD_GAIN_RATIO_EVENT___POR 0x1 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__RLSIG_DET_EVENT___POR 0x0 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__QBPSK_DET_EVENT___POR 0x0 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__NEXT_RU_DESC_EVENT___POR 0x0 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__NEXT_DESC_EVENT___POR 0x1 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__ECO_EVENT___POR 0x0 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__ERROR_EVENT___POR 0x0 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__SPARE15_EVENT___M 0x00008000 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__SPARE15_EVENT___S 15 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__SPARE14_EVENT___M 0x00004000 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__SPARE14_EVENT___S 14 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__SPARE13_EVENT___M 0x00002000 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__SPARE13_EVENT___S 13 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__SPARE12_EVENT___M 0x00001000 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__SPARE12_EVENT___S 12 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__PER_PKT_PROGRAM_EVENT___M 0x00000800 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__PER_PKT_PROGRAM_EVENT___S 11 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__RU_BD_PTC_HW_UPDATE_EVENT___M 0x00000400 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__RU_BD_PTC_HW_UPDATE_EVENT___S 10 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__PROC_COMPLETE_EVENT___M 0x00000100 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__PROC_COMPLETE_EVENT___S 8 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__RXTD_NOISEPWR_BTCF_EVENT___M 0x00000080 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__RXTD_NOISEPWR_BTCF_EVENT___S 7 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__RXTD_GAIN_RATIO_EVENT___M 0x00000040 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__RXTD_GAIN_RATIO_EVENT___S 6 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__RLSIG_DET_EVENT___M 0x00000020 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__RLSIG_DET_EVENT___S 5 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__QBPSK_DET_EVENT___M 0x00000010 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__QBPSK_DET_EVENT___S 4 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__NEXT_RU_DESC_EVENT___M 0x00000008 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__NEXT_RU_DESC_EVENT___S 3 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__NEXT_DESC_EVENT___M 0x00000004 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__NEXT_DESC_EVENT___S 2 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__ECO_EVENT___M 0x00000002 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__ECO_EVENT___S 1 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__ERROR_EVENT___M 0x00000001 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L__ERROR_EVENT___S 0 +#define PHYA_DEMFRONT_1_EVENT_STATUS_L___M 0x0000FDFF +#define PHYA_DEMFRONT_1_EVENT_STATUS_L___S 0 + +#define PHYA_DEMFRONT_1_EVENT_MASK_L (0x00500018) +#define PHYA_DEMFRONT_1_EVENT_MASK_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_EVENT_MASK_L___POR 0x0000FDFF +#define PHYA_DEMFRONT_1_EVENT_MASK_L__SPARE15_EVENT_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__SPARE14_EVENT_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__SPARE13_EVENT_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__SPARE12_EVENT_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__PER_PKT_PROGRAM_EVENT_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__RU_BD_PTC_HW_UPDATE_EVENT_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__PROC_COMPLETE_EVENT_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__RXTD_NOISEPWR_BTCF_EVENT_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__RXTD_GAIN_RATIO_EVENT_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__RLSIG_DET_EVENT_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__QBPSK_DET_EVENT_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__NEXT_RU_DESC_EVENT_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__NEXT_DESC_EVENT_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__ECO_EVENT_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__ERROR_EVENT_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__SPARE15_EVENT_MASK___M 0x00008000 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__SPARE15_EVENT_MASK___S 15 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__SPARE14_EVENT_MASK___M 0x00004000 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__SPARE14_EVENT_MASK___S 14 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__SPARE13_EVENT_MASK___M 0x00002000 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__SPARE13_EVENT_MASK___S 13 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__SPARE12_EVENT_MASK___M 0x00001000 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__SPARE12_EVENT_MASK___S 12 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__PER_PKT_PROGRAM_EVENT_MASK___M 0x00000800 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__PER_PKT_PROGRAM_EVENT_MASK___S 11 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__RU_BD_PTC_HW_UPDATE_EVENT_MASK___M 0x00000400 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__RU_BD_PTC_HW_UPDATE_EVENT_MASK___S 10 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__PROC_COMPLETE_EVENT_MASK___M 0x00000100 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__PROC_COMPLETE_EVENT_MASK___S 8 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__RXTD_NOISEPWR_BTCF_EVENT_MASK___M 0x00000080 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__RXTD_NOISEPWR_BTCF_EVENT_MASK___S 7 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__RXTD_GAIN_RATIO_EVENT_MASK___M 0x00000040 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__RXTD_GAIN_RATIO_EVENT_MASK___S 6 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__RLSIG_DET_EVENT_MASK___M 0x00000020 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__RLSIG_DET_EVENT_MASK___S 5 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__QBPSK_DET_EVENT_MASK___M 0x00000010 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__QBPSK_DET_EVENT_MASK___S 4 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__NEXT_RU_DESC_EVENT_MASK___M 0x00000008 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__NEXT_RU_DESC_EVENT_MASK___S 3 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__NEXT_DESC_EVENT_MASK___M 0x00000004 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__NEXT_DESC_EVENT_MASK___S 2 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__ECO_EVENT_MASK___M 0x00000002 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__ECO_EVENT_MASK___S 1 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__ERROR_EVENT_MASK___M 0x00000001 +#define PHYA_DEMFRONT_1_EVENT_MASK_L__ERROR_EVENT_MASK___S 0 +#define PHYA_DEMFRONT_1_EVENT_MASK_L___M 0x0000FDFF +#define PHYA_DEMFRONT_1_EVENT_MASK_L___S 0 + +#define PHYA_DEMFRONT_1_ERROR_MASK_L (0x00500020) +#define PHYA_DEMFRONT_1_ERROR_MASK_L___RWC QCSR_REG_RO +#define PHYA_DEMFRONT_1_ERROR_MASK_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_ERROR_MASK_L__ERROR_CODE___POR 0x00 +#define PHYA_DEMFRONT_1_ERROR_MASK_L__ERROR_CODE___M 0x0000003F +#define PHYA_DEMFRONT_1_ERROR_MASK_L__ERROR_CODE___S 0 +#define PHYA_DEMFRONT_1_ERROR_MASK_L___M 0x0000003F +#define PHYA_DEMFRONT_1_ERROR_MASK_L___S 0 + +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L (0x00500028) +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__QRE_RU_STOMP_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__CBFG_RU_STOMP_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__CHE_RU_STOMP_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__PTC_RU_STOMP_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__MRC_RU_STOMP_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SYM_PROC_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__PCNT_STUCK_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__PTC_MISALIGNMENT_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__CV2V_MISALIGNMENT_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__MRC_TONE_MISALIGNMENT_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__LLR_MISALIGNMENT_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__ILLEGAL_QRE_REQUEST_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__ILLEGAL_RATE_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SDF_REQUEST_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SPARE13_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SPARE12_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SPARE11_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SPARE10_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__PER_PKT_PROGRAM_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__RU_BD_PTC_HW_UPDATE_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__PROC_COMPLETE_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__RXTD_NOISEPWR_BTCF_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__RXTD_GAIN_RATIO_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__RLSIG_DET_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__QBPSK_DET_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__NEXT_RU_DESC_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__NEXT_DESC_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__QRE_RU_STOMP_ERROR___M 0x80000000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__QRE_RU_STOMP_ERROR___S 31 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__CBFG_RU_STOMP_ERROR___M 0x40000000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__CBFG_RU_STOMP_ERROR___S 30 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__CHE_RU_STOMP_ERROR___M 0x10000000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__CHE_RU_STOMP_ERROR___S 28 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__PTC_RU_STOMP_ERROR___M 0x08000000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__PTC_RU_STOMP_ERROR___S 27 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__MRC_RU_STOMP_ERROR___M 0x04000000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__MRC_RU_STOMP_ERROR___S 26 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SYM_PROC_ERROR___M 0x01000000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SYM_PROC_ERROR___S 24 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__PCNT_STUCK_ERROR___M 0x00800000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__PCNT_STUCK_ERROR___S 23 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__PTC_MISALIGNMENT_ERROR___M 0x00400000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__PTC_MISALIGNMENT_ERROR___S 22 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__CV2V_MISALIGNMENT_ERROR___M 0x00200000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__CV2V_MISALIGNMENT_ERROR___S 21 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__MRC_TONE_MISALIGNMENT_ERROR___M 0x00100000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__MRC_TONE_MISALIGNMENT_ERROR___S 20 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__LLR_MISALIGNMENT_ERROR___M 0x00080000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__LLR_MISALIGNMENT_ERROR___S 19 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__ILLEGAL_QRE_REQUEST_ERROR___M 0x00010000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__ILLEGAL_QRE_REQUEST_ERROR___S 16 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__ILLEGAL_RATE_ERROR___M 0x00008000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__ILLEGAL_RATE_ERROR___S 15 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SDF_REQUEST_ERROR___M 0x00004000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SDF_REQUEST_ERROR___S 14 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SPARE13_ERROR___M 0x00002000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SPARE13_ERROR___S 13 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SPARE12_ERROR___M 0x00001000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SPARE12_ERROR___S 12 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SPARE11_ERROR___M 0x00000800 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SPARE11_ERROR___S 11 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SPARE10_ERROR___M 0x00000400 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__SPARE10_ERROR___S 10 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__PER_PKT_PROGRAM_ERROR___M 0x00000200 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__PER_PKT_PROGRAM_ERROR___S 9 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__RU_BD_PTC_HW_UPDATE_ERROR___M 0x00000100 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__RU_BD_PTC_HW_UPDATE_ERROR___S 8 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__PROC_COMPLETE_ERROR___M 0x00000040 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__PROC_COMPLETE_ERROR___S 6 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__RXTD_NOISEPWR_BTCF_ERROR___M 0x00000020 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__RXTD_NOISEPWR_BTCF_ERROR___S 5 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__RXTD_GAIN_RATIO_ERROR___M 0x00000010 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__RXTD_GAIN_RATIO_ERROR___S 4 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__RLSIG_DET_ERROR___M 0x00000008 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__RLSIG_DET_ERROR___S 3 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__QBPSK_DET_ERROR___M 0x00000004 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__QBPSK_DET_ERROR___S 2 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__NEXT_RU_DESC_ERROR___M 0x00000002 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__NEXT_RU_DESC_ERROR___S 1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__NEXT_DESC_ERROR___M 0x00000001 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L__NEXT_DESC_ERROR___S 0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L___M 0xDDF9FF7F +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_L___S 0 + +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U (0x0050002C) +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE63_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE62_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE61_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE60_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE59_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE58_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE57_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE56_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE55_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE54_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE53_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE52_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE51_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE50_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE49_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE48_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE47_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE46_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE45_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE44_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE43_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__LLR_STREAM_MISALIGNMENT_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__MRC_STREAM_MISALIGNMENT_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__QRE_STREAM_MISALIGNMENT_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__NP_STREAM_MISALIGNMENT_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__ROBE_RU_STOMP_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__FDPP_RU_STOMP_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__FTE_RU_STOMP_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__NP_RU_STOMP_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__LLR_RU_STOMP_ERROR___POR 0x0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE63_ERROR___M 0x80000000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE63_ERROR___S 31 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE62_ERROR___M 0x40000000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE62_ERROR___S 30 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE61_ERROR___M 0x20000000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE61_ERROR___S 29 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE60_ERROR___M 0x10000000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE60_ERROR___S 28 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE59_ERROR___M 0x08000000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE59_ERROR___S 27 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE58_ERROR___M 0x04000000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE58_ERROR___S 26 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE57_ERROR___M 0x02000000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE57_ERROR___S 25 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE56_ERROR___M 0x01000000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE56_ERROR___S 24 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE55_ERROR___M 0x00800000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE55_ERROR___S 23 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE54_ERROR___M 0x00400000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE54_ERROR___S 22 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE53_ERROR___M 0x00200000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE53_ERROR___S 21 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE52_ERROR___M 0x00100000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE52_ERROR___S 20 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE51_ERROR___M 0x00080000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE51_ERROR___S 19 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE50_ERROR___M 0x00040000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE50_ERROR___S 18 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE49_ERROR___M 0x00020000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE49_ERROR___S 17 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE48_ERROR___M 0x00010000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE48_ERROR___S 16 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE47_ERROR___M 0x00008000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE47_ERROR___S 15 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE46_ERROR___M 0x00004000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE46_ERROR___S 14 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE45_ERROR___M 0x00002000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE45_ERROR___S 13 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE44_ERROR___M 0x00001000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE44_ERROR___S 12 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE43_ERROR___M 0x00000800 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__SPARE43_ERROR___S 11 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__LLR_STREAM_MISALIGNMENT_ERROR___M 0x00000400 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__LLR_STREAM_MISALIGNMENT_ERROR___S 10 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__MRC_STREAM_MISALIGNMENT_ERROR___M 0x00000200 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__MRC_STREAM_MISALIGNMENT_ERROR___S 9 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__QRE_STREAM_MISALIGNMENT_ERROR___M 0x00000100 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__QRE_STREAM_MISALIGNMENT_ERROR___S 8 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__NP_STREAM_MISALIGNMENT_ERROR___M 0x00000080 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__NP_STREAM_MISALIGNMENT_ERROR___S 7 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__ROBE_RU_STOMP_ERROR___M 0x00000010 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__ROBE_RU_STOMP_ERROR___S 4 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__FDPP_RU_STOMP_ERROR___M 0x00000008 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__FDPP_RU_STOMP_ERROR___S 3 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__FTE_RU_STOMP_ERROR___M 0x00000004 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__FTE_RU_STOMP_ERROR___S 2 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__NP_RU_STOMP_ERROR___M 0x00000002 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__NP_RU_STOMP_ERROR___S 1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__LLR_RU_STOMP_ERROR___M 0x00000001 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U__LLR_RU_STOMP_ERROR___S 0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U___M 0xFFFFFF9F +#define PHYA_DEMFRONT_1_ERROR_ERROR_STATUS_U___S 0 + +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L (0x00500030) +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L___POR 0xDDF9FF7F +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__QRE_RU_STOMP_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__CBFG_RU_STOMP_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__CHE_RU_STOMP_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__PTC_RU_STOMP_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__MRC_RU_STOMP_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SYM_PROC_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__PCNT_STUCK_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__PTC_MISALIGNMENT_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__CV2V_MISALIGNMENT_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__MRC_TONE_MISALIGNMENT_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__LLR_MISALIGNMENT_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__ILLEGAL_QRE_REQUEST_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__ILLEGAL_RATE_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SDF_REQUEST_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SPARE13_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SPARE12_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SPARE11_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SPARE10_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__PER_PKT_PROGRAM_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__RU_BD_PTC_HW_UPDATE_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__PROC_COMPLETE_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__RXTD_NOISEPWR_BTCF_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__RXTD_GAIN_RATIO_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__RLSIG_DET_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__QBPSK_DET_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__NEXT_RU_DESC_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__NEXT_DESC_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__QRE_RU_STOMP_ERROR_MASK___M 0x80000000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__QRE_RU_STOMP_ERROR_MASK___S 31 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__CBFG_RU_STOMP_ERROR_MASK___M 0x40000000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__CBFG_RU_STOMP_ERROR_MASK___S 30 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__CHE_RU_STOMP_ERROR_MASK___M 0x10000000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__CHE_RU_STOMP_ERROR_MASK___S 28 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__PTC_RU_STOMP_ERROR_MASK___M 0x08000000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__PTC_RU_STOMP_ERROR_MASK___S 27 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__MRC_RU_STOMP_ERROR_MASK___M 0x04000000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__MRC_RU_STOMP_ERROR_MASK___S 26 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SYM_PROC_ERROR_MASK___M 0x01000000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SYM_PROC_ERROR_MASK___S 24 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__PCNT_STUCK_ERROR_MASK___M 0x00800000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__PCNT_STUCK_ERROR_MASK___S 23 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__PTC_MISALIGNMENT_ERROR_MASK___M 0x00400000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__PTC_MISALIGNMENT_ERROR_MASK___S 22 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__CV2V_MISALIGNMENT_ERROR_MASK___M 0x00200000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__CV2V_MISALIGNMENT_ERROR_MASK___S 21 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__MRC_TONE_MISALIGNMENT_ERROR_MASK___M 0x00100000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__MRC_TONE_MISALIGNMENT_ERROR_MASK___S 20 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__LLR_MISALIGNMENT_ERROR_MASK___M 0x00080000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__LLR_MISALIGNMENT_ERROR_MASK___S 19 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__ILLEGAL_QRE_REQUEST_ERROR_MASK___M 0x00010000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__ILLEGAL_QRE_REQUEST_ERROR_MASK___S 16 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__ILLEGAL_RATE_ERROR_MASK___M 0x00008000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__ILLEGAL_RATE_ERROR_MASK___S 15 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SDF_REQUEST_ERROR_MASK___M 0x00004000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SDF_REQUEST_ERROR_MASK___S 14 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SPARE13_ERROR_MASK___M 0x00002000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SPARE13_ERROR_MASK___S 13 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SPARE12_ERROR_MASK___M 0x00001000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SPARE12_ERROR_MASK___S 12 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SPARE11_ERROR_MASK___M 0x00000800 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SPARE11_ERROR_MASK___S 11 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SPARE10_ERROR_MASK___M 0x00000400 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__SPARE10_ERROR_MASK___S 10 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__PER_PKT_PROGRAM_ERROR_MASK___M 0x00000200 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__PER_PKT_PROGRAM_ERROR_MASK___S 9 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__RU_BD_PTC_HW_UPDATE_ERROR_MASK___M 0x00000100 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__RU_BD_PTC_HW_UPDATE_ERROR_MASK___S 8 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__PROC_COMPLETE_ERROR_MASK___M 0x00000040 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__PROC_COMPLETE_ERROR_MASK___S 6 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__RXTD_NOISEPWR_BTCF_ERROR_MASK___M 0x00000020 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__RXTD_NOISEPWR_BTCF_ERROR_MASK___S 5 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__RXTD_GAIN_RATIO_ERROR_MASK___M 0x00000010 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__RXTD_GAIN_RATIO_ERROR_MASK___S 4 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__RLSIG_DET_ERROR_MASK___M 0x00000008 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__RLSIG_DET_ERROR_MASK___S 3 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__QBPSK_DET_ERROR_MASK___M 0x00000004 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__QBPSK_DET_ERROR_MASK___S 2 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__NEXT_RU_DESC_ERROR_MASK___M 0x00000002 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__NEXT_RU_DESC_ERROR_MASK___S 1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__NEXT_DESC_ERROR_MASK___M 0x00000001 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L__NEXT_DESC_ERROR_MASK___S 0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L___M 0xDDF9FF7F +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_L___S 0 + +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U (0x00500034) +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U___POR 0xFFFFFF9F +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE63_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE62_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE61_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE60_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE59_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE58_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE57_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE56_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE55_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE54_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE53_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE52_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE51_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE50_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE49_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE48_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE47_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE46_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE45_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE44_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE43_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__LLR_STREAM_MISALIGNMENT_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__MRC_STREAM_MISALIGNMENT_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__QRE_STREAM_MISALIGNMENT_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__NP_STREAM_MISALIGNMENT_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__ROBE_RU_STOMP_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__FDPP_RU_STOMP_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__FTE_RU_STOMP_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__NP_RU_STOMP_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__LLR_RU_STOMP_ERROR_MASK___POR 0x1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE63_ERROR_MASK___M 0x80000000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE63_ERROR_MASK___S 31 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE62_ERROR_MASK___M 0x40000000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE62_ERROR_MASK___S 30 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE61_ERROR_MASK___M 0x20000000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE61_ERROR_MASK___S 29 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE60_ERROR_MASK___M 0x10000000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE60_ERROR_MASK___S 28 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE59_ERROR_MASK___M 0x08000000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE59_ERROR_MASK___S 27 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE58_ERROR_MASK___M 0x04000000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE58_ERROR_MASK___S 26 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE57_ERROR_MASK___M 0x02000000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE57_ERROR_MASK___S 25 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE56_ERROR_MASK___M 0x01000000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE56_ERROR_MASK___S 24 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE55_ERROR_MASK___M 0x00800000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE55_ERROR_MASK___S 23 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE54_ERROR_MASK___M 0x00400000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE54_ERROR_MASK___S 22 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE53_ERROR_MASK___M 0x00200000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE53_ERROR_MASK___S 21 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE52_ERROR_MASK___M 0x00100000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE52_ERROR_MASK___S 20 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE51_ERROR_MASK___M 0x00080000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE51_ERROR_MASK___S 19 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE50_ERROR_MASK___M 0x00040000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE50_ERROR_MASK___S 18 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE49_ERROR_MASK___M 0x00020000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE49_ERROR_MASK___S 17 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE48_ERROR_MASK___M 0x00010000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE48_ERROR_MASK___S 16 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE47_ERROR_MASK___M 0x00008000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE47_ERROR_MASK___S 15 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE46_ERROR_MASK___M 0x00004000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE46_ERROR_MASK___S 14 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE45_ERROR_MASK___M 0x00002000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE45_ERROR_MASK___S 13 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE44_ERROR_MASK___M 0x00001000 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE44_ERROR_MASK___S 12 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE43_ERROR_MASK___M 0x00000800 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__SPARE43_ERROR_MASK___S 11 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__LLR_STREAM_MISALIGNMENT_ERROR_MASK___M 0x00000400 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__LLR_STREAM_MISALIGNMENT_ERROR_MASK___S 10 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__MRC_STREAM_MISALIGNMENT_ERROR_MASK___M 0x00000200 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__MRC_STREAM_MISALIGNMENT_ERROR_MASK___S 9 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__QRE_STREAM_MISALIGNMENT_ERROR_MASK___M 0x00000100 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__QRE_STREAM_MISALIGNMENT_ERROR_MASK___S 8 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__NP_STREAM_MISALIGNMENT_ERROR_MASK___M 0x00000080 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__NP_STREAM_MISALIGNMENT_ERROR_MASK___S 7 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__ROBE_RU_STOMP_ERROR_MASK___M 0x00000010 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__ROBE_RU_STOMP_ERROR_MASK___S 4 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__FDPP_RU_STOMP_ERROR_MASK___M 0x00000008 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__FDPP_RU_STOMP_ERROR_MASK___S 3 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__FTE_RU_STOMP_ERROR_MASK___M 0x00000004 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__FTE_RU_STOMP_ERROR_MASK___S 2 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__NP_RU_STOMP_ERROR_MASK___M 0x00000002 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__NP_RU_STOMP_ERROR_MASK___S 1 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__LLR_RU_STOMP_ERROR_MASK___M 0x00000001 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U__LLR_RU_STOMP_ERROR_MASK___S 0 +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U___M 0xFFFFFF9F +#define PHYA_DEMFRONT_1_ERROR_ERROR_MASK_U___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_L (0x00500038) +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_L___POR 0x01000034 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_L__N_DC_TONE___POR 0x1 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_L__N_PILOT_TONE___POR 0x00 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_L__N_DATA_TONE___POR 0x034 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_L__N_DC_TONE___M 0x07000000 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_L__N_DC_TONE___S 24 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_L__N_PILOT_TONE___M 0x001F0000 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_L__N_PILOT_TONE___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_L__N_DATA_TONE___M 0x000003FF +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_L__N_DATA_TONE___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_L___M 0x071F03FF +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_U (0x0050003C) +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_U___POR 0x00640000 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_U__WAIT_CYCLES___POR 0x064 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_U__EQUALIZER_TYPE___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_U__WAIT_CYCLES___M 0x01FF0000 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_U__WAIT_CYCLES___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_U__EQUALIZER_TYPE___M 0x00000007 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_U__EQUALIZER_TYPE___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_U___M 0x01FF0007 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_0_U___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_1_L (0x00500040) +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_1_L___POR 0xFFE6FFE6 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_1_L__START_TONE_1___POR 0xFFE6 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_1_L__START_TONE_0___POR 0xFFE6 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_1_L__START_TONE_1___M 0xFFFF0000 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_1_L__START_TONE_1___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_1_L__START_TONE_0___M 0x0000FFFF +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_1_L__START_TONE_0___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_1_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_1_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_L (0x00500048) +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_L___POR 0x00010100 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_L__N_USER___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_L__LAST_RU___POR 0x1 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_L__FIRST_RU___POR 0x1 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_L__IS_STBC___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_L__N_USER___M 0x0F000000 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_L__N_USER___S 24 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_L__LAST_RU___M 0x00010000 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_L__LAST_RU___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_L__FIRST_RU___M 0x00000100 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_L__FIRST_RU___S 8 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_L__IS_STBC___M 0x00000001 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_L__IS_STBC___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_L___M 0x0F010101 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_U (0x0050004C) +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_U___POR 0x00001003 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_U__NOTCH_FREQ_SHIFT___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_U__THROTTLE_RATE___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_U__N_COL___POR 0x10 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_U__N_ROW___POR 0x03 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_U__NOTCH_FREQ_SHIFT___M 0x0F000000 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_U__NOTCH_FREQ_SHIFT___S 24 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_U__THROTTLE_RATE___M 0x00070000 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_U__THROTTLE_RATE___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_U__N_COL___M 0x00003F00 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_U__N_COL___S 8 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_U__N_ROW___M 0x0000001F +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_U__N_ROW___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_U___M 0x0F073F1F +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_2_U___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_L (0x00500050) +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_L__DCM_POLARITY___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_L__ENA_DCM___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_L__N_SD_SHORT___POR 0x000 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_L__DCM_POLARITY___M 0x01000000 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_L__DCM_POLARITY___S 24 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_L__ENA_DCM___M 0x00010000 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_L__ENA_DCM___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_L__N_SD_SHORT___M 0x000003FF +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_L__N_SD_SHORT___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_L___M 0x010103FF +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_U (0x00500054) +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_U__ENA_UPBAND_FLIP___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_U__RESET_EVM___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_U__COMPUTE_EVM___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_U__RUBD_FW_LOAD___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_U__ENA_UPBAND_FLIP___M 0x01000000 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_U__ENA_UPBAND_FLIP___S 24 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_U__RESET_EVM___M 0x00010000 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_U__RESET_EVM___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_U__COMPUTE_EVM___M 0x00000100 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_U__COMPUTE_EVM___S 8 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_U__RUBD_FW_LOAD___M 0x00000001 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_U__RUBD_FW_LOAD___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_U___M 0x01010101 +#define PHYA_DEMFRONT_1_RUUD_RU_UD_CONTROL_3_U___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_CMD_L (0x00500058) +#define PHYA_DEMFRONT_1_RUUD_RU_CMD_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_CMD_L___POR 0x00000001 +#define PHYA_DEMFRONT_1_RUUD_RU_CMD_L__CMD_3___POR 0x00 +#define PHYA_DEMFRONT_1_RUUD_RU_CMD_L__CMD_2___POR 0x00 +#define PHYA_DEMFRONT_1_RUUD_RU_CMD_L__CMD_1___POR 0x00 +#define PHYA_DEMFRONT_1_RUUD_RU_CMD_L__CMD_0___POR 0x01 +#define PHYA_DEMFRONT_1_RUUD_RU_CMD_L__CMD_3___M 0xFF000000 +#define PHYA_DEMFRONT_1_RUUD_RU_CMD_L__CMD_3___S 24 +#define PHYA_DEMFRONT_1_RUUD_RU_CMD_L__CMD_2___M 0x00FF0000 +#define PHYA_DEMFRONT_1_RUUD_RU_CMD_L__CMD_2___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_CMD_L__CMD_1___M 0x0000FF00 +#define PHYA_DEMFRONT_1_RUUD_RU_CMD_L__CMD_1___S 8 +#define PHYA_DEMFRONT_1_RUUD_RU_CMD_L__CMD_0___M 0x000000FF +#define PHYA_DEMFRONT_1_RUUD_RU_CMD_L__CMD_0___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_CMD_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_RU_CMD_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_CMD_U (0x0050005C) +#define PHYA_DEMFRONT_1_RUUD_RU_CMD_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_CMD_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_CMD_U__CMD_7___POR 0x00 +#define PHYA_DEMFRONT_1_RUUD_RU_CMD_U__CMD_6___POR 0x00 +#define PHYA_DEMFRONT_1_RUUD_RU_CMD_U__CMD_5___POR 0x00 +#define PHYA_DEMFRONT_1_RUUD_RU_CMD_U__CMD_4___POR 0x00 +#define PHYA_DEMFRONT_1_RUUD_RU_CMD_U__CMD_7___M 0xFF000000 +#define PHYA_DEMFRONT_1_RUUD_RU_CMD_U__CMD_7___S 24 +#define PHYA_DEMFRONT_1_RUUD_RU_CMD_U__CMD_6___M 0x00FF0000 +#define PHYA_DEMFRONT_1_RUUD_RU_CMD_U__CMD_6___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_CMD_U__CMD_5___M 0x0000FF00 +#define PHYA_DEMFRONT_1_RUUD_RU_CMD_U__CMD_5___S 8 +#define PHYA_DEMFRONT_1_RUUD_RU_CMD_U__CMD_4___M 0x000000FF +#define PHYA_DEMFRONT_1_RUUD_RU_CMD_U__CMD_4___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_CMD_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_RU_CMD_U___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT0_L (0x00500060) +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT0_L___POR 0xFFF9FFEB +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT0_L__PILOT_INDEX_1_0___POR 0xFFF9 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT0_L__PILOT_INDEX_0_0___POR 0xFFEB +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT0_L__PILOT_INDEX_1_0___M 0xFFFF0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT0_L__PILOT_INDEX_1_0___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT0_L__PILOT_INDEX_0_0___M 0x0000FFFF +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT0_L__PILOT_INDEX_0_0___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT0_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT0_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT0_U (0x00500064) +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT0_U___POR 0x00150007 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT0_U__PILOT_INDEX_3_0___POR 0x0015 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT0_U__PILOT_INDEX_2_0___POR 0x0007 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT0_U__PILOT_INDEX_3_0___M 0xFFFF0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT0_U__PILOT_INDEX_3_0___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT0_U__PILOT_INDEX_2_0___M 0x0000FFFF +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT0_U__PILOT_INDEX_2_0___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT0_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT0_U___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT1_L (0x00500068) +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT1_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT1_L__PILOT_INDEX_1_1___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT1_L__PILOT_INDEX_0_1___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT1_L__PILOT_INDEX_1_1___M 0xFFFF0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT1_L__PILOT_INDEX_1_1___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT1_L__PILOT_INDEX_0_1___M 0x0000FFFF +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT1_L__PILOT_INDEX_0_1___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT1_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT1_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT1_U (0x0050006C) +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT1_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT1_U__PILOT_INDEX_3_1___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT1_U__PILOT_INDEX_2_1___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT1_U__PILOT_INDEX_3_1___M 0xFFFF0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT1_U__PILOT_INDEX_3_1___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT1_U__PILOT_INDEX_2_1___M 0x0000FFFF +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT1_U__PILOT_INDEX_2_1___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT1_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT1_U___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT2_L (0x00500070) +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT2_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT2_L__PILOT_INDEX_1_2___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT2_L__PILOT_INDEX_0_2___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT2_L__PILOT_INDEX_1_2___M 0xFFFF0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT2_L__PILOT_INDEX_1_2___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT2_L__PILOT_INDEX_0_2___M 0x0000FFFF +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT2_L__PILOT_INDEX_0_2___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT2_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT2_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT2_U (0x00500074) +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT2_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT2_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT2_U__PILOT_INDEX_3_2___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT2_U__PILOT_INDEX_2_2___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT2_U__PILOT_INDEX_3_2___M 0xFFFF0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT2_U__PILOT_INDEX_3_2___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT2_U__PILOT_INDEX_2_2___M 0x0000FFFF +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT2_U__PILOT_INDEX_2_2___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT2_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT2_U___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT3_L (0x00500078) +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT3_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT3_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT3_L__PILOT_INDEX_1_3___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT3_L__PILOT_INDEX_0_3___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT3_L__PILOT_INDEX_1_3___M 0xFFFF0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT3_L__PILOT_INDEX_1_3___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT3_L__PILOT_INDEX_0_3___M 0x0000FFFF +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT3_L__PILOT_INDEX_0_3___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT3_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT3_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT3_U (0x0050007C) +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT3_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT3_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT3_U__PILOT_INDEX_3_3___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT3_U__PILOT_INDEX_2_3___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT3_U__PILOT_INDEX_3_3___M 0xFFFF0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT3_U__PILOT_INDEX_3_3___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT3_U__PILOT_INDEX_2_3___M 0x0000FFFF +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT3_U__PILOT_INDEX_2_3___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT3_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_RU_PILOT3_U___S 0 + +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_L (0x00500080) +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_L__QAM_0___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_L__IS_LDPC_0___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_L__N_SS_0___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_L__USER_ID_0___POR 0x00 +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_L__QAM_0___M 0x07000000 +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_L__QAM_0___S 24 +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_L__IS_LDPC_0___M 0x00010000 +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_L__IS_LDPC_0___S 16 +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_L__N_SS_0___M 0x00000F00 +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_L__N_SS_0___S 8 +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_L__USER_ID_0___M 0x0000003F +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_L__USER_ID_0___S 0 +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_L___M 0x07010F3F +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_U (0x00500084) +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_U__LDPC_LLR_SCALE_0___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_U__LDPC_LLR_SCALE_0___M 0x00000007 +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_U__LDPC_LLR_SCALE_0___S 0 +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_U___M 0x00000007 +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL0_U___S 0 + +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_L (0x00500088) +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_L__QAM_1___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_L__IS_LDPC_1___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_L__N_SS_1___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_L__USER_ID_1___POR 0x00 +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_L__QAM_1___M 0x07000000 +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_L__QAM_1___S 24 +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_L__IS_LDPC_1___M 0x00010000 +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_L__IS_LDPC_1___S 16 +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_L__N_SS_1___M 0x00000F00 +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_L__N_SS_1___S 8 +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_L__USER_ID_1___M 0x0000003F +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_L__USER_ID_1___S 0 +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_L___M 0x07010F3F +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_U (0x0050008C) +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_U__LDPC_LLR_SCALE_1___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_U__LDPC_LLR_SCALE_1___M 0x00000007 +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_U__LDPC_LLR_SCALE_1___S 0 +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_U___M 0x00000007 +#define PHYA_DEMFRONT_1_RUUD_UREC_USER_CONTROL1_U___S 0 + +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_0_L (0x005000A0) +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_0_L__NEXT_RU_DESC_UREC_WR_SPARE_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_0_L__NEXT_RU_DESC_UREC_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_0_L__NEXT_RU_DESC_UREC_WR_SPARE_0___S 0 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_0_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_0_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_0_U (0x005000A4) +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_0_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_0_U__NEXT_RU_DESC_UREC_WR_SPARE_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_0_U__NEXT_RU_DESC_UREC_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_0_U__NEXT_RU_DESC_UREC_WR_SPARE_1___S 0 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_0_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_0_U___S 0 + +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_1_L (0x005000D0) +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_1_L__NEXT_RU_DESC_NP_WR_SPARE_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_1_L__NEXT_RU_DESC_NP_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_1_L__NEXT_RU_DESC_NP_WR_SPARE_0___S 0 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_1_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_1_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_1_U (0x005000D4) +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_1_U__NEXT_RU_DESC_NP_WR_SPARE_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_1_U__NEXT_RU_DESC_NP_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_1_U__NEXT_RU_DESC_NP_WR_SPARE_1___S 0 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_1_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_1_U___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_FDPP_CONTROL_L (0x005000D8) +#define PHYA_DEMFRONT_1_RUUD_RU_FDPP_CONTROL_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_FDPP_CONTROL_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_FDPP_CONTROL_L__ENABLE_PHASE_CORR___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_FDPP_CONTROL_L__ENABLE_PHASE_CORR___M 0x00000001 +#define PHYA_DEMFRONT_1_RUUD_RU_FDPP_CONTROL_L__ENABLE_PHASE_CORR___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_FDPP_CONTROL_L___M 0x00000001 +#define PHYA_DEMFRONT_1_RUUD_RU_FDPP_CONTROL_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_2_L (0x005000E0) +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_2_L__NEXT_RU_DESC_FDPP_WR_SPARE_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_2_L__NEXT_RU_DESC_FDPP_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_2_L__NEXT_RU_DESC_FDPP_WR_SPARE_0___S 0 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_2_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_2_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_2_U (0x005000E4) +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_2_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_2_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_2_U__NEXT_RU_DESC_FDPP_WR_SPARE_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_2_U__NEXT_RU_DESC_FDPP_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_2_U__NEXT_RU_DESC_FDPP_WR_SPARE_1___S 0 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_2_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_2_U___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_ML_CONTROL_L (0x005000E8) +#define PHYA_DEMFRONT_1_RUUD_RU_ML_CONTROL_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_ML_CONTROL_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_ML_CONTROL_L__ML_LLR_EMU_ENABLE_1___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_ML_CONTROL_L__ML_LLR_EMU_ENABLE_0___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_ML_CONTROL_L__ML_LLR_EMU_ENABLE_1___M 0x00000100 +#define PHYA_DEMFRONT_1_RUUD_RU_ML_CONTROL_L__ML_LLR_EMU_ENABLE_1___S 8 +#define PHYA_DEMFRONT_1_RUUD_RU_ML_CONTROL_L__ML_LLR_EMU_ENABLE_0___M 0x00000001 +#define PHYA_DEMFRONT_1_RUUD_RU_ML_CONTROL_L__ML_LLR_EMU_ENABLE_0___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_ML_CONTROL_L___M 0x00000101 +#define PHYA_DEMFRONT_1_RUUD_RU_ML_CONTROL_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_ML_SWEIGHT_TABLE_0_L (0x005000F0) +#define PHYA_DEMFRONT_1_RUUD_ML_SWEIGHT_TABLE_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_ML_SWEIGHT_TABLE_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_ML_SWEIGHT_TABLE_0_L__SWEIGHT_SS_1___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_ML_SWEIGHT_TABLE_0_L__SWEIGHT_SS_0___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_ML_SWEIGHT_TABLE_0_L__SWEIGHT_SS_1___M 0x00000700 +#define PHYA_DEMFRONT_1_RUUD_ML_SWEIGHT_TABLE_0_L__SWEIGHT_SS_1___S 8 +#define PHYA_DEMFRONT_1_RUUD_ML_SWEIGHT_TABLE_0_L__SWEIGHT_SS_0___M 0x00000007 +#define PHYA_DEMFRONT_1_RUUD_ML_SWEIGHT_TABLE_0_L__SWEIGHT_SS_0___S 0 +#define PHYA_DEMFRONT_1_RUUD_ML_SWEIGHT_TABLE_0_L___M 0x00000707 +#define PHYA_DEMFRONT_1_RUUD_ML_SWEIGHT_TABLE_0_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_L (0x00500100) +#define PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_3___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_2___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_1___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_0___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_3___M 0x07000000 +#define PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_3___S 24 +#define PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_2___M 0x00070000 +#define PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_2___S 16 +#define PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_1___M 0x00000700 +#define PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_1___S 8 +#define PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_0___M 0x00000007 +#define PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_L__MIMO_LLR_SCALE_TABLE_0___S 0 +#define PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_L___M 0x07070707 +#define PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_U (0x00500104) +#define PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_U__MIMO_LLR_SCALE_TABLE_5___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_U__MIMO_LLR_SCALE_TABLE_4___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_U__MIMO_LLR_SCALE_TABLE_5___M 0x00000700 +#define PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_U__MIMO_LLR_SCALE_TABLE_5___S 8 +#define PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_U__MIMO_LLR_SCALE_TABLE_4___M 0x00000007 +#define PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_U__MIMO_LLR_SCALE_TABLE_4___S 0 +#define PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_U___M 0x00000707 +#define PHYA_DEMFRONT_1_RUUD_ML_LLR_SCALE_TABLE_U___S 0 + +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_3_L (0x00500108) +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_3_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_3_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_3_L__NEXT_RU_DESC_ML_WR_SPARE_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_3_L__NEXT_RU_DESC_ML_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_3_L__NEXT_RU_DESC_ML_WR_SPARE_0___S 0 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_3_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_3_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_3_U (0x0050010C) +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_3_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_3_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_3_U__NEXT_RU_DESC_ML_WR_SPARE_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_3_U__NEXT_RU_DESC_ML_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_3_U__NEXT_RU_DESC_ML_WR_SPARE_1___S 0 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_3_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_3_U___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_L (0x00500110) +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_L__PILOT_PATTERN_1_0___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_L__PILOT_PATTERN_0_0___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_L__PILOT_PATTERN_1_0___M 0xFFFF0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_L__PILOT_PATTERN_1_0___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_L__PILOT_PATTERN_0_0___M 0x0000FFFF +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_L__PILOT_PATTERN_0_0___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_U (0x00500114) +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_U__PILOT_PATTERN_3_0___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_U__PILOT_PATTERN_2_0___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_U__PILOT_PATTERN_3_0___M 0xFFFF0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_U__PILOT_PATTERN_3_0___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_U__PILOT_PATTERN_2_0___M 0x0000FFFF +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_U__PILOT_PATTERN_2_0___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_00_U___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_L (0x00500118) +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_L__PILOT_PATTERN_1_1___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_L__PILOT_PATTERN_0_1___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_L__PILOT_PATTERN_1_1___M 0xFFFF0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_L__PILOT_PATTERN_1_1___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_L__PILOT_PATTERN_0_1___M 0x0000FFFF +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_L__PILOT_PATTERN_0_1___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_U (0x0050011C) +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_U__PILOT_PATTERN_3_1___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_U__PILOT_PATTERN_2_1___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_U__PILOT_PATTERN_3_1___M 0xFFFF0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_U__PILOT_PATTERN_3_1___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_U__PILOT_PATTERN_2_1___M 0x0000FFFF +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_U__PILOT_PATTERN_2_1___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_01_U___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_L (0x00500128) +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_L___POR 0x00040000 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_L__ENABLE_DF_PILOT___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_L__MAX_DF_TONES___POR 0x4 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_L__ENABLE_DF_PILOT___M 0x01000000 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_L__ENABLE_DF_PILOT___S 24 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_L__MAX_DF_TONES___M 0x00070000 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_L__MAX_DF_TONES___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_L___M 0x01070000 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_L___S 16 + +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_U (0x0050012C) +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_U__SPUR_NOTCH_OFF___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_U__FREEZE_PTC___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_U__PHASE32___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_U__SPUR_NOTCH_OFF___M 0x01000000 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_U__SPUR_NOTCH_OFF___S 24 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_U__FREEZE_PTC___M 0x00010000 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_U__FREEZE_PTC___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_U__PHASE32___M 0x0000FFFF +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_U__PHASE32___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_U___M 0x0101FFFF +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_2_U___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_L (0x00500130) +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_L__PREV_RESIDUAL_PHASE___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_L__PREV_RESIDUAL_PHASE___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_L__PREV_RESIDUAL_PHASE___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_U (0x00500134) +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_U__PHASE_OFFSET_REF___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_U__CURR_RESIDUAL_PHASE_RSHIFT___POR 0x00 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_U__CURR_PPM_STRIDE___POR 0x00 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_U__PHASE_OFFSET_REF___M 0xFFFF0000 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_U__PHASE_OFFSET_REF___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_U__CURR_RESIDUAL_PHASE_RSHIFT___M 0x0000FF00 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_U__CURR_RESIDUAL_PHASE_RSHIFT___S 8 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_U__CURR_PPM_STRIDE___M 0x000000FF +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_U__CURR_PPM_STRIDE___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_3_U___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_4_L (0x00500138) +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_4_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_4_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_4_L__EN_RU_BD_PTC_HW_UPDATE___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_4_L__EN_RU_BD_PTC_HW_UPDATE___M 0x00000001 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_4_L__EN_RU_BD_PTC_HW_UPDATE___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_4_L___M 0x00000001 +#define PHYA_DEMFRONT_1_RUUD_RU_PTC_CONTROL_4_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_L (0x00500140) +#define PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_L__UPDATE_FLAT_CHANNEL___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_L__ENA_MAX_BIN_PWR___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_L__ENA_PMAG_CORR___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_L__ENA_PHASE_CORR___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_L__UPDATE_FLAT_CHANNEL___M 0x01000000 +#define PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_L__UPDATE_FLAT_CHANNEL___S 24 +#define PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_L__ENA_MAX_BIN_PWR___M 0x00010000 +#define PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_L__ENA_MAX_BIN_PWR___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_L__ENA_PMAG_CORR___M 0x00000100 +#define PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_L__ENA_PMAG_CORR___S 8 +#define PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_L__ENA_PHASE_CORR___M 0x00000001 +#define PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_L__ENA_PHASE_CORR___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_L___M 0x01010101 +#define PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_U (0x00500144) +#define PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_U__UPDATE_FD_RSSI___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_U__UPDATE_FD_RSSI___M 0x00000001 +#define PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_U__UPDATE_FD_RSSI___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_U___M 0x00000001 +#define PHYA_DEMFRONT_1_RUUD_RU_MRC_CONTROL_U___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_L (0x00500148) +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_L__SM_FILTER_SHORT_SEL___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_L__SM_FILTER_HIGHSNR_SEL___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_L__EN_SMOOTHING___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_L__LTF_PATTERN___POR 0x00 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_L__SM_FILTER_SHORT_SEL___M 0x01000000 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_L__SM_FILTER_SHORT_SEL___S 24 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_L__SM_FILTER_HIGHSNR_SEL___M 0x00010000 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_L__SM_FILTER_HIGHSNR_SEL___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_L__EN_SMOOTHING___M 0x00000100 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_L__EN_SMOOTHING___S 8 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_L__LTF_PATTERN___M 0x0000001F +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_L__LTF_PATTERN___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_L___M 0x0101011F +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_U (0x0050014C) +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_U___POR 0x00000100 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_U__PILOT_H_STORE_INDEX___POR 0x000 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_U__PILOT_H_RAW_SEL___POR 0x1 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_U__SM_FILTER_DUR_MODE_SEL___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_U__PILOT_H_STORE_INDEX___M 0x03FF0000 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_U__PILOT_H_STORE_INDEX___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_U__PILOT_H_RAW_SEL___M 0x00000100 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_U__PILOT_H_RAW_SEL___S 8 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_U__SM_FILTER_DUR_MODE_SEL___M 0x00000003 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_U__SM_FILTER_DUR_MODE_SEL___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_U___M 0x03FF0103 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_0_U___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_L (0x00500150) +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_L__PBD_M___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_L__PILOT_H_COMB_SEL___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_L__H_BW_DET_EXP___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_L__PBD_M___M 0xFFFF0000 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_L__PBD_M___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_L__PILOT_H_COMB_SEL___M 0x00000100 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_L__PILOT_H_COMB_SEL___S 8 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_L__H_BW_DET_EXP___M 0x0000000F +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_L__H_BW_DET_EXP___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_L___M 0xFFFF010F +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_U (0x00500154) +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_U__PBD_P___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_U__PBD_P___M 0x0000FFFF +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_U__PBD_P___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_U___M 0x0000FFFF +#define PHYA_DEMFRONT_1_RUUD_RU_CHE_CONTROL_1_U___S 0 + +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_4_L (0x00500158) +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_4_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_4_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_4_L__NEXT_RU_DESC_CHE_WR_SPARE_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_4_L__NEXT_RU_DESC_CHE_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_4_L__NEXT_RU_DESC_CHE_WR_SPARE_0___S 0 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_4_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_4_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_4_U (0x0050015C) +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_4_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_4_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_4_U__NEXT_RU_DESC_CHE_WR_SPARE_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_4_U__NEXT_RU_DESC_CHE_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_4_U__NEXT_RU_DESC_CHE_WR_SPARE_1___S 0 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_4_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_4_U___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_0_L (0x00500160) +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_0_L__MRC_MAX_BIN_PWR_EXP___POR 0x00 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_0_L__MRC_MAX_BIN_PWR_MAN___POR 0x00 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_0_L__MRC_MAX_BIN_PWR_EXP___M 0x0000FF00 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_0_L__MRC_MAX_BIN_PWR_EXP___S 8 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_0_L__MRC_MAX_BIN_PWR_MAN___M 0x000000FF +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_0_L__MRC_MAX_BIN_PWR_MAN___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_0_L___M 0x0000FFFF +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_0_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_1_L (0x00500168) +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_1_L__FD_RSSI_1___POR 0x00 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_1_L__FD_RSSI_0___POR 0x00 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_1_L__FD_RSSI_1___M 0x0000FF00 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_1_L__FD_RSSI_1___S 8 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_1_L__FD_RSSI_0___M 0x000000FF +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_1_L__FD_RSSI_0___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_1_L___M 0x0000FFFF +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_1_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_2_L (0x00500170) +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_2_L__MRC_IS_FLAT_CHAN_SMOOTH___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_2_L__MRC_IS_FLAT_CHAN___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_2_L__MRC_IS_FLAT_CHAN_SMOOTH___M 0x00000100 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_2_L__MRC_IS_FLAT_CHAN_SMOOTH___S 8 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_2_L__MRC_IS_FLAT_CHAN___M 0x00000001 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_2_L__MRC_IS_FLAT_CHAN___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_2_L___M 0x00000101 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_2_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_3_L (0x00500178) +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_3_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_3_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_3_L__LLR_MAX_ED_SS_1___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_3_L__LLR_MAX_ED_SS_0___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_3_L__LLR_MAX_ED_SS_1___M 0x3FFF0000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_3_L__LLR_MAX_ED_SS_1___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_3_L__LLR_MAX_ED_SS_0___M 0x00003FFF +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_3_L__LLR_MAX_ED_SS_0___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_3_L___M 0x3FFF3FFF +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_3_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_4_L (0x00500180) +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_4_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_4_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_4_L__LLR_MIN_ED_SS_1___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_4_L__LLR_MIN_ED_SS_0___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_4_L__LLR_MIN_ED_SS_1___M 0x3FFF0000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_4_L__LLR_MIN_ED_SS_1___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_4_L__LLR_MIN_ED_SS_0___M 0x00003FFF +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_4_L__LLR_MIN_ED_SS_0___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_4_L___M 0x3FFF3FFF +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_4_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_5_L (0x00500188) +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_5_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_5_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_5_L__CH_DIAG_SS_1___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_5_L__CH_DIAG_SS_0___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_5_L__CH_DIAG_SS_1___M 0x00000300 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_5_L__CH_DIAG_SS_1___S 8 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_5_L__CH_DIAG_SS_0___M 0x00000003 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_5_L__CH_DIAG_SS_0___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_5_L___M 0x00000303 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_5_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_7_L (0x00500198) +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_7_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_7_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_7_L__COMPUTED_EMU_ENABLE_1___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_7_L__COMPUTED_EMU_ENABLE_0___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_7_L__COMPUTED_EMU_ENABLE_1___M 0x00000100 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_7_L__COMPUTED_EMU_ENABLE_1___S 8 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_7_L__COMPUTED_EMU_ENABLE_0___M 0x00000001 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_7_L__COMPUTED_EMU_ENABLE_0___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_7_L___M 0x00000101 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_DATA_7_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_0_U (0x005001A4) +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_0_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_0_U__CURR_PREDICTED_SLOPE___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_0_U__CURR_PREDICTED_SLOPE___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_0_U__CURR_PREDICTED_SLOPE___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_0_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_0_U___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_1_L (0x005001A8) +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_1_L__CURR_PREDICTED_SLOPE_FRAC___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_1_L__CURR_PREDICTED_SLOPE_FRAC___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_1_L__CURR_PREDICTED_SLOPE_FRAC___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_1_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_1_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_1_U (0x005001AC) +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_1_U__CURR_OFFSET___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_1_U__CURR_OFFSET___M 0x0000FFFF +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_1_U__CURR_OFFSET___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_1_U___M 0x0000FFFF +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_1_U___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_L (0x005001B0) +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_L__PILOT_POWER_IIR___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_L__PILOT_POWER_IIR___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_L__PILOT_POWER_IIR___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_U (0x005001B4) +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_U__CURR_OFFSET_M1___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_U__CURR_TIMING_ADJUST___POR 0x00 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_U__CURR_OFFSET_M1___M 0xFFFF0000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_U__CURR_OFFSET_M1___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_U__CURR_TIMING_ADJUST___M 0x000000FF +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_U__CURR_TIMING_ADJUST___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_U___M 0xFFFF00FF +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_2_U___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_3_L (0x005001B8) +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_3_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_3_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_3_L__PILOT_ROTATE_CURR_SYM___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_3_L__CURR_OFFSET_M2___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_3_L__PILOT_ROTATE_CURR_SYM___M 0x000F0000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_3_L__PILOT_ROTATE_CURR_SYM___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_3_L__CURR_OFFSET_M2___M 0x0000FFFF +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_3_L__CURR_OFFSET_M2___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_3_L___M 0x000FFFFF +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_3_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_L (0x005001C0) +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_L__DF_PILOT_1___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_L__DF_PILOT_0___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_L__DF_PILOT_1___M 0xFFFF0000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_L__DF_PILOT_1___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_L__DF_PILOT_0___M 0x0000FFFF +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_L__DF_PILOT_0___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_U (0x005001C4) +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_U__DF_PILOT_3___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_U__DF_PILOT_2___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_U__DF_PILOT_3___M 0xFFFF0000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_U__DF_PILOT_3___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_U__DF_PILOT_2___M 0x0000FFFF +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_U__DF_PILOT_2___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_4_U___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_L (0x005001C8) +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_L__PILOT_MAG_EXP___POR 0x00 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_L__PILOT_MAG_MAN___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_L__PILOT_MAG_EXP___M 0x00FF0000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_L__PILOT_MAG_EXP___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_L__PILOT_MAG_MAN___M 0x0000FFFF +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_L__PILOT_MAG_MAN___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_L___M 0x00FFFFFF +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_U (0x005001CC) +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_U__PILOT_POWER_REF___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_U__PHASE_FINE___POR 0x0000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_U__PILOT_POWER_REF___M 0xFFFF0000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_U__PILOT_POWER_REF___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_U__PHASE_FINE___M 0x0000FFFF +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_U__PHASE_FINE___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_RU_BD_PTC_5_U___S 0 + +#define PHYA_DEMFRONT_1_RUUD_RU_BD_CHE_L (0x005001D0) +#define PHYA_DEMFRONT_1_RUUD_RU_BD_CHE_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_RU_BD_CHE_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_CHE_L__H_BW_DET_EXP_CHN_1___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_CHE_L__RESCALE_AMT_SHIFT_1___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_CHE_L__H_BW_DET_EXP_CHN_0___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_CHE_L__RESCALE_AMT_SHIFT_0___POR 0x0 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_CHE_L__H_BW_DET_EXP_CHN_1___M 0x0F000000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_CHE_L__H_BW_DET_EXP_CHN_1___S 24 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_CHE_L__RESCALE_AMT_SHIFT_1___M 0x00030000 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_CHE_L__RESCALE_AMT_SHIFT_1___S 16 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_CHE_L__H_BW_DET_EXP_CHN_0___M 0x00000F00 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_CHE_L__H_BW_DET_EXP_CHN_0___S 8 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_CHE_L__RESCALE_AMT_SHIFT_0___M 0x00000003 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_CHE_L__RESCALE_AMT_SHIFT_0___S 0 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_CHE_L___M 0x0F030F03 +#define PHYA_DEMFRONT_1_RUUD_RU_BD_CHE_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_5_L (0x005001D8) +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_5_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_5_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_5_L__NEXT_RU_DESC_DATA_RD_SPARE_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_5_L__NEXT_RU_DESC_DATA_RD_SPARE_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_5_L__NEXT_RU_DESC_DATA_RD_SPARE_0___S 0 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_5_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_5_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_5_U (0x005001DC) +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_5_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_5_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_5_U__NEXT_RU_DESC_DATA_RD_SPARE_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_5_U__NEXT_RU_DESC_DATA_RD_SPARE_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_5_U__NEXT_RU_DESC_DATA_RD_SPARE_1___S 0 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_5_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_5_U___S 0 + +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_6_L (0x005001E0) +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_6_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_6_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_6_L__NEXT_RU_DESC_RD_SPARE_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_6_L__NEXT_RU_DESC_RD_SPARE_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_6_L__NEXT_RU_DESC_RD_SPARE_0___S 0 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_6_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_6_L___S 0 + +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_6_U (0x005001E4) +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_6_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_6_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_6_U__NEXT_RU_DESC_RD_SPARE_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_6_U__NEXT_RU_DESC_RD_SPARE_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_6_U__NEXT_RU_DESC_RD_SPARE_1___S 0 +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_6_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RUUD_USER_SPARE_6_U___S 0 + +#define PHYA_DEMFRONT_1_USER_SPARE_0_L (0x005001E8) +#define PHYA_DEMFRONT_1_USER_SPARE_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_USER_SPARE_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_USER_SPARE_0_L__NEXT_RU_DESC_WR_SPARE_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_USER_SPARE_0_L__NEXT_RU_DESC_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_USER_SPARE_0_L__NEXT_RU_DESC_WR_SPARE_0___S 0 +#define PHYA_DEMFRONT_1_USER_SPARE_0_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_USER_SPARE_0_L___S 0 + +#define PHYA_DEMFRONT_1_USER_SPARE_0_U (0x005001EC) +#define PHYA_DEMFRONT_1_USER_SPARE_0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_USER_SPARE_0_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_USER_SPARE_0_U__NEXT_RU_DESC_WR_SPARE_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_USER_SPARE_0_U__NEXT_RU_DESC_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_USER_SPARE_0_U__NEXT_RU_DESC_WR_SPARE_1___S 0 +#define PHYA_DEMFRONT_1_USER_SPARE_0_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_USER_SPARE_0_U___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_EVM0_L (0x005001F0) +#define PHYA_DEMFRONT_1_RU_BD_EVM0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RU_BD_EVM0_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM0_L__ACC_LINEAR_EVM_0_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM0_L__ACC_LINEAR_EVM_0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM0_L__ACC_LINEAR_EVM_0_0___S 0 +#define PHYA_DEMFRONT_1_RU_BD_EVM0_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM0_L___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_EVM0_U (0x005001F4) +#define PHYA_DEMFRONT_1_RU_BD_EVM0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RU_BD_EVM0_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM0_U__ACC_LINEAR_EVM_1_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM0_U__ACC_LINEAR_EVM_1_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM0_U__ACC_LINEAR_EVM_1_0___S 0 +#define PHYA_DEMFRONT_1_RU_BD_EVM0_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM0_U___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_EVM1_L (0x005001F8) +#define PHYA_DEMFRONT_1_RU_BD_EVM1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RU_BD_EVM1_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM1_L__ACC_LINEAR_EVM_0_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM1_L__ACC_LINEAR_EVM_0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM1_L__ACC_LINEAR_EVM_0_1___S 0 +#define PHYA_DEMFRONT_1_RU_BD_EVM1_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM1_L___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_EVM1_U (0x005001FC) +#define PHYA_DEMFRONT_1_RU_BD_EVM1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RU_BD_EVM1_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM1_U__ACC_LINEAR_EVM_1_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM1_U__ACC_LINEAR_EVM_1_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM1_U__ACC_LINEAR_EVM_1_1___S 0 +#define PHYA_DEMFRONT_1_RU_BD_EVM1_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM1_U___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_EVM2_L (0x00500200) +#define PHYA_DEMFRONT_1_RU_BD_EVM2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RU_BD_EVM2_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM2_L__ACC_LINEAR_EVM_0_2___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM2_L__ACC_LINEAR_EVM_0_2___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM2_L__ACC_LINEAR_EVM_0_2___S 0 +#define PHYA_DEMFRONT_1_RU_BD_EVM2_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM2_L___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_EVM2_U (0x00500204) +#define PHYA_DEMFRONT_1_RU_BD_EVM2_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RU_BD_EVM2_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM2_U__ACC_LINEAR_EVM_1_2___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM2_U__ACC_LINEAR_EVM_1_2___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM2_U__ACC_LINEAR_EVM_1_2___S 0 +#define PHYA_DEMFRONT_1_RU_BD_EVM2_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM2_U___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_EVM3_L (0x00500208) +#define PHYA_DEMFRONT_1_RU_BD_EVM3_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RU_BD_EVM3_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM3_L__ACC_LINEAR_EVM_0_3___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM3_L__ACC_LINEAR_EVM_0_3___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM3_L__ACC_LINEAR_EVM_0_3___S 0 +#define PHYA_DEMFRONT_1_RU_BD_EVM3_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM3_L___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_EVM3_U (0x0050020C) +#define PHYA_DEMFRONT_1_RU_BD_EVM3_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RU_BD_EVM3_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM3_U__ACC_LINEAR_EVM_1_3___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM3_U__ACC_LINEAR_EVM_1_3___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM3_U__ACC_LINEAR_EVM_1_3___S 0 +#define PHYA_DEMFRONT_1_RU_BD_EVM3_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM3_U___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_EVM4_L (0x00500210) +#define PHYA_DEMFRONT_1_RU_BD_EVM4_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RU_BD_EVM4_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM4_L__ACC_LINEAR_EVM_0_4___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM4_L__ACC_LINEAR_EVM_0_4___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM4_L__ACC_LINEAR_EVM_0_4___S 0 +#define PHYA_DEMFRONT_1_RU_BD_EVM4_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM4_L___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_EVM4_U (0x00500214) +#define PHYA_DEMFRONT_1_RU_BD_EVM4_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RU_BD_EVM4_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM4_U__ACC_LINEAR_EVM_1_4___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM4_U__ACC_LINEAR_EVM_1_4___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM4_U__ACC_LINEAR_EVM_1_4___S 0 +#define PHYA_DEMFRONT_1_RU_BD_EVM4_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM4_U___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_EVM5_L (0x00500218) +#define PHYA_DEMFRONT_1_RU_BD_EVM5_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RU_BD_EVM5_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM5_L__ACC_LINEAR_EVM_0_5___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM5_L__ACC_LINEAR_EVM_0_5___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM5_L__ACC_LINEAR_EVM_0_5___S 0 +#define PHYA_DEMFRONT_1_RU_BD_EVM5_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM5_L___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_EVM5_U (0x0050021C) +#define PHYA_DEMFRONT_1_RU_BD_EVM5_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RU_BD_EVM5_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM5_U__ACC_LINEAR_EVM_1_5___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM5_U__ACC_LINEAR_EVM_1_5___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM5_U__ACC_LINEAR_EVM_1_5___S 0 +#define PHYA_DEMFRONT_1_RU_BD_EVM5_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM5_U___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_EVM6_L (0x00500220) +#define PHYA_DEMFRONT_1_RU_BD_EVM6_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RU_BD_EVM6_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM6_L__ACC_LINEAR_EVM_0_6___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM6_L__ACC_LINEAR_EVM_0_6___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM6_L__ACC_LINEAR_EVM_0_6___S 0 +#define PHYA_DEMFRONT_1_RU_BD_EVM6_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM6_L___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_EVM6_U (0x00500224) +#define PHYA_DEMFRONT_1_RU_BD_EVM6_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RU_BD_EVM6_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM6_U__ACC_LINEAR_EVM_1_6___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM6_U__ACC_LINEAR_EVM_1_6___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM6_U__ACC_LINEAR_EVM_1_6___S 0 +#define PHYA_DEMFRONT_1_RU_BD_EVM6_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM6_U___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_EVM7_L (0x00500228) +#define PHYA_DEMFRONT_1_RU_BD_EVM7_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RU_BD_EVM7_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM7_L__ACC_LINEAR_EVM_0_7___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM7_L__ACC_LINEAR_EVM_0_7___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM7_L__ACC_LINEAR_EVM_0_7___S 0 +#define PHYA_DEMFRONT_1_RU_BD_EVM7_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM7_L___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_EVM7_U (0x0050022C) +#define PHYA_DEMFRONT_1_RU_BD_EVM7_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RU_BD_EVM7_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM7_U__ACC_LINEAR_EVM_1_7___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM7_U__ACC_LINEAR_EVM_1_7___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM7_U__ACC_LINEAR_EVM_1_7___S 0 +#define PHYA_DEMFRONT_1_RU_BD_EVM7_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM7_U___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_EVM8_L (0x00500230) +#define PHYA_DEMFRONT_1_RU_BD_EVM8_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RU_BD_EVM8_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM8_L__ACC_LINEAR_EVM_0_8___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM8_L__ACC_LINEAR_EVM_0_8___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM8_L__ACC_LINEAR_EVM_0_8___S 0 +#define PHYA_DEMFRONT_1_RU_BD_EVM8_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM8_L___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_EVM8_U (0x00500234) +#define PHYA_DEMFRONT_1_RU_BD_EVM8_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RU_BD_EVM8_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM8_U__ACC_LINEAR_EVM_1_8___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM8_U__ACC_LINEAR_EVM_1_8___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM8_U__ACC_LINEAR_EVM_1_8___S 0 +#define PHYA_DEMFRONT_1_RU_BD_EVM8_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM8_U___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_EVM9_L (0x00500238) +#define PHYA_DEMFRONT_1_RU_BD_EVM9_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RU_BD_EVM9_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM9_L__ACC_LINEAR_EVM_0_9___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM9_L__ACC_LINEAR_EVM_0_9___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM9_L__ACC_LINEAR_EVM_0_9___S 0 +#define PHYA_DEMFRONT_1_RU_BD_EVM9_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM9_L___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_EVM9_U (0x0050023C) +#define PHYA_DEMFRONT_1_RU_BD_EVM9_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RU_BD_EVM9_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM9_U__ACC_LINEAR_EVM_1_9___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM9_U__ACC_LINEAR_EVM_1_9___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM9_U__ACC_LINEAR_EVM_1_9___S 0 +#define PHYA_DEMFRONT_1_RU_BD_EVM9_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM9_U___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_EVM10_L (0x00500240) +#define PHYA_DEMFRONT_1_RU_BD_EVM10_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RU_BD_EVM10_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM10_L__ACC_LINEAR_EVM_0_10___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM10_L__ACC_LINEAR_EVM_0_10___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM10_L__ACC_LINEAR_EVM_0_10___S 0 +#define PHYA_DEMFRONT_1_RU_BD_EVM10_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM10_L___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_EVM10_U (0x00500244) +#define PHYA_DEMFRONT_1_RU_BD_EVM10_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RU_BD_EVM10_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM10_U__ACC_LINEAR_EVM_1_10___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM10_U__ACC_LINEAR_EVM_1_10___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM10_U__ACC_LINEAR_EVM_1_10___S 0 +#define PHYA_DEMFRONT_1_RU_BD_EVM10_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM10_U___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_EVM11_L (0x00500248) +#define PHYA_DEMFRONT_1_RU_BD_EVM11_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RU_BD_EVM11_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM11_L__ACC_LINEAR_EVM_0_11___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM11_L__ACC_LINEAR_EVM_0_11___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM11_L__ACC_LINEAR_EVM_0_11___S 0 +#define PHYA_DEMFRONT_1_RU_BD_EVM11_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM11_L___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_EVM11_U (0x0050024C) +#define PHYA_DEMFRONT_1_RU_BD_EVM11_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RU_BD_EVM11_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM11_U__ACC_LINEAR_EVM_1_11___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM11_U__ACC_LINEAR_EVM_1_11___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM11_U__ACC_LINEAR_EVM_1_11___S 0 +#define PHYA_DEMFRONT_1_RU_BD_EVM11_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM11_U___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_EVM12_L (0x00500250) +#define PHYA_DEMFRONT_1_RU_BD_EVM12_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RU_BD_EVM12_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM12_L__ACC_LINEAR_EVM_0_12___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM12_L__ACC_LINEAR_EVM_0_12___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM12_L__ACC_LINEAR_EVM_0_12___S 0 +#define PHYA_DEMFRONT_1_RU_BD_EVM12_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM12_L___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_EVM12_U (0x00500254) +#define PHYA_DEMFRONT_1_RU_BD_EVM12_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RU_BD_EVM12_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM12_U__ACC_LINEAR_EVM_1_12___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM12_U__ACC_LINEAR_EVM_1_12___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM12_U__ACC_LINEAR_EVM_1_12___S 0 +#define PHYA_DEMFRONT_1_RU_BD_EVM12_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM12_U___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_EVM13_L (0x00500258) +#define PHYA_DEMFRONT_1_RU_BD_EVM13_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RU_BD_EVM13_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM13_L__ACC_LINEAR_EVM_0_13___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM13_L__ACC_LINEAR_EVM_0_13___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM13_L__ACC_LINEAR_EVM_0_13___S 0 +#define PHYA_DEMFRONT_1_RU_BD_EVM13_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM13_L___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_EVM13_U (0x0050025C) +#define PHYA_DEMFRONT_1_RU_BD_EVM13_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RU_BD_EVM13_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM13_U__ACC_LINEAR_EVM_1_13___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM13_U__ACC_LINEAR_EVM_1_13___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM13_U__ACC_LINEAR_EVM_1_13___S 0 +#define PHYA_DEMFRONT_1_RU_BD_EVM13_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM13_U___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_EVM14_L (0x00500260) +#define PHYA_DEMFRONT_1_RU_BD_EVM14_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RU_BD_EVM14_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM14_L__ACC_LINEAR_EVM_0_14___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM14_L__ACC_LINEAR_EVM_0_14___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM14_L__ACC_LINEAR_EVM_0_14___S 0 +#define PHYA_DEMFRONT_1_RU_BD_EVM14_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM14_L___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_EVM14_U (0x00500264) +#define PHYA_DEMFRONT_1_RU_BD_EVM14_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RU_BD_EVM14_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM14_U__ACC_LINEAR_EVM_1_14___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM14_U__ACC_LINEAR_EVM_1_14___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM14_U__ACC_LINEAR_EVM_1_14___S 0 +#define PHYA_DEMFRONT_1_RU_BD_EVM14_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM14_U___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_EVM15_L (0x00500268) +#define PHYA_DEMFRONT_1_RU_BD_EVM15_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RU_BD_EVM15_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM15_L__ACC_LINEAR_EVM_0_15___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM15_L__ACC_LINEAR_EVM_0_15___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM15_L__ACC_LINEAR_EVM_0_15___S 0 +#define PHYA_DEMFRONT_1_RU_BD_EVM15_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM15_L___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_EVM15_U (0x0050026C) +#define PHYA_DEMFRONT_1_RU_BD_EVM15_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RU_BD_EVM15_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM15_U__ACC_LINEAR_EVM_1_15___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_EVM15_U__ACC_LINEAR_EVM_1_15___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM15_U__ACC_LINEAR_EVM_1_15___S 0 +#define PHYA_DEMFRONT_1_RU_BD_EVM15_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_RU_BD_EVM15_U___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_QRE_0_L (0x00500270) +#define PHYA_DEMFRONT_1_RU_BD_QRE_0_L___RWC QCSR_REG_RO +#define PHYA_DEMFRONT_1_RU_BD_QRE_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_QRE_0_L__ML_SUBSET_SEARCH_2X2_USAGE_1___POR 0x000 +#define PHYA_DEMFRONT_1_RU_BD_QRE_0_L__ML_SUBSET_SEARCH_2X2_USAGE_0___POR 0x000 +#define PHYA_DEMFRONT_1_RU_BD_QRE_0_L__ML_SUBSET_SEARCH_2X2_USAGE_1___M 0x0FFF0000 +#define PHYA_DEMFRONT_1_RU_BD_QRE_0_L__ML_SUBSET_SEARCH_2X2_USAGE_1___S 16 +#define PHYA_DEMFRONT_1_RU_BD_QRE_0_L__ML_SUBSET_SEARCH_2X2_USAGE_0___M 0x00000FFF +#define PHYA_DEMFRONT_1_RU_BD_QRE_0_L__ML_SUBSET_SEARCH_2X2_USAGE_0___S 0 +#define PHYA_DEMFRONT_1_RU_BD_QRE_0_L___M 0x0FFF0FFF +#define PHYA_DEMFRONT_1_RU_BD_QRE_0_L___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_QRE_1_L (0x00500278) +#define PHYA_DEMFRONT_1_RU_BD_QRE_1_L___RWC QCSR_REG_RO +#define PHYA_DEMFRONT_1_RU_BD_QRE_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_QRE_1_L__ML_SUBSET_SEARCH_4X4_USAGE_1___POR 0x000 +#define PHYA_DEMFRONT_1_RU_BD_QRE_1_L__ML_SUBSET_SEARCH_4X4_USAGE_0___POR 0x000 +#define PHYA_DEMFRONT_1_RU_BD_QRE_1_L__ML_SUBSET_SEARCH_4X4_USAGE_1___M 0x0FFF0000 +#define PHYA_DEMFRONT_1_RU_BD_QRE_1_L__ML_SUBSET_SEARCH_4X4_USAGE_1___S 16 +#define PHYA_DEMFRONT_1_RU_BD_QRE_1_L__ML_SUBSET_SEARCH_4X4_USAGE_0___M 0x00000FFF +#define PHYA_DEMFRONT_1_RU_BD_QRE_1_L__ML_SUBSET_SEARCH_4X4_USAGE_0___S 0 +#define PHYA_DEMFRONT_1_RU_BD_QRE_1_L___M 0x0FFF0FFF +#define PHYA_DEMFRONT_1_RU_BD_QRE_1_L___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_0_L (0x005003F0) +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_0_L___RWC QCSR_REG_RO +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_0_L__IS_FLAT_CHANNEL___POR 0x0 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_0_L__IS_FLAT_CHANNEL___M 0x00000001 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_0_L__IS_FLAT_CHANNEL___S 0 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_0_L___M 0x00000001 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_0_L___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_1_L (0x005003F8) +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_1_L___RWC QCSR_REG_RO +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_1_L__IS_HIGH_FREQ_SELECT_1___POR 0x00 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_1_L__IS_HIGH_FREQ_SELECT_0___POR 0x00 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_1_L__IS_HIGH_FREQ_SELECT_1___M 0x0000FF00 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_1_L__IS_HIGH_FREQ_SELECT_1___S 8 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_1_L__IS_HIGH_FREQ_SELECT_0___M 0x000000FF +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_1_L__IS_HIGH_FREQ_SELECT_0___S 0 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_1_L___M 0x0000FFFF +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_1_L___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_2_L (0x00500400) +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_2_L___RWC QCSR_REG_RO +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_2_L__IS_VALID_HIGH_FREQ_SELECT_1___POR 0x00 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_2_L__IS_VALID_HIGH_FREQ_SELECT_0___POR 0x00 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_2_L__IS_VALID_HIGH_FREQ_SELECT_1___M 0x0000FF00 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_2_L__IS_VALID_HIGH_FREQ_SELECT_1___S 8 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_2_L__IS_VALID_HIGH_FREQ_SELECT_0___M 0x000000FF +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_2_L__IS_VALID_HIGH_FREQ_SELECT_0___S 0 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_2_L___M 0x0000FFFF +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_2_L___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_3_L (0x00500408) +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_3_L___RWC QCSR_REG_RO +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_3_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_3_L__SHIFTSAMPLENO_VLD_1___POR 0x00 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_3_L__SHIFTSAMPLENO_VLD_0___POR 0x00 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_3_L__SHIFTSAMPLENO_VLD_1___M 0x0000FF00 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_3_L__SHIFTSAMPLENO_VLD_1___S 8 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_3_L__SHIFTSAMPLENO_VLD_0___M 0x000000FF +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_3_L__SHIFTSAMPLENO_VLD_0___S 0 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_3_L___M 0x0000FFFF +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_3_L___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_4_L (0x00500410) +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_4_L___RWC QCSR_REG_RO +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_4_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_4_L__SHIFTSAMPLENO_S0_1___POR 0x000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_4_L__SHIFTSAMPLENO_S0_0___POR 0x000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_4_L__SHIFTSAMPLENO_S0_1___M 0x07FF0000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_4_L__SHIFTSAMPLENO_S0_1___S 16 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_4_L__SHIFTSAMPLENO_S0_0___M 0x000007FF +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_4_L__SHIFTSAMPLENO_S0_0___S 0 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_4_L___M 0x07FF07FF +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_4_L___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_5_L (0x00500418) +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_5_L___RWC QCSR_REG_RO +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_5_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_5_L__SHIFTSAMPLENO_S1_1___POR 0x000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_5_L__SHIFTSAMPLENO_S1_0___POR 0x000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_5_L__SHIFTSAMPLENO_S1_1___M 0x07FF0000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_5_L__SHIFTSAMPLENO_S1_1___S 16 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_5_L__SHIFTSAMPLENO_S1_0___M 0x000007FF +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_5_L__SHIFTSAMPLENO_S1_0___S 0 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_5_L___M 0x07FF07FF +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_5_L___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_6_L (0x00500420) +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_6_L___RWC QCSR_REG_RO +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_6_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_6_L__SHIFTSAMPLENO_S2_1___POR 0x000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_6_L__SHIFTSAMPLENO_S2_0___POR 0x000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_6_L__SHIFTSAMPLENO_S2_1___M 0x07FF0000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_6_L__SHIFTSAMPLENO_S2_1___S 16 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_6_L__SHIFTSAMPLENO_S2_0___M 0x000007FF +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_6_L__SHIFTSAMPLENO_S2_0___S 0 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_6_L___M 0x07FF07FF +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_6_L___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_7_L (0x00500428) +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_7_L___RWC QCSR_REG_RO +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_7_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_7_L__SHIFTSAMPLENO_S3_1___POR 0x000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_7_L__SHIFTSAMPLENO_S3_0___POR 0x000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_7_L__SHIFTSAMPLENO_S3_1___M 0x07FF0000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_7_L__SHIFTSAMPLENO_S3_1___S 16 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_7_L__SHIFTSAMPLENO_S3_0___M 0x000007FF +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_7_L__SHIFTSAMPLENO_S3_0___S 0 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_7_L___M 0x07FF07FF +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_7_L___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_8_L (0x00500430) +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_8_L___RWC QCSR_REG_RO +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_8_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_8_L__SHIFTSAMPLENO_S4_1___POR 0x000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_8_L__SHIFTSAMPLENO_S4_0___POR 0x000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_8_L__SHIFTSAMPLENO_S4_1___M 0x07FF0000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_8_L__SHIFTSAMPLENO_S4_1___S 16 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_8_L__SHIFTSAMPLENO_S4_0___M 0x000007FF +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_8_L__SHIFTSAMPLENO_S4_0___S 0 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_8_L___M 0x07FF07FF +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_8_L___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_9_L (0x00500438) +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_9_L___RWC QCSR_REG_RO +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_9_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_9_L__SHIFTSAMPLENO_S5_1___POR 0x000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_9_L__SHIFTSAMPLENO_S5_0___POR 0x000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_9_L__SHIFTSAMPLENO_S5_1___M 0x07FF0000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_9_L__SHIFTSAMPLENO_S5_1___S 16 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_9_L__SHIFTSAMPLENO_S5_0___M 0x000007FF +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_9_L__SHIFTSAMPLENO_S5_0___S 0 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_9_L___M 0x07FF07FF +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_9_L___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_10_L (0x00500440) +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_10_L___RWC QCSR_REG_RO +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_10_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_10_L__SHIFTSAMPLENO_S6_1___POR 0x000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_10_L__SHIFTSAMPLENO_S6_0___POR 0x000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_10_L__SHIFTSAMPLENO_S6_1___M 0x07FF0000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_10_L__SHIFTSAMPLENO_S6_1___S 16 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_10_L__SHIFTSAMPLENO_S6_0___M 0x000007FF +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_10_L__SHIFTSAMPLENO_S6_0___S 0 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_10_L___M 0x07FF07FF +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_10_L___S 0 + +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_11_L (0x00500448) +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_11_L___RWC QCSR_REG_RO +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_11_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_11_L__SHIFTSAMPLENO_S7_1___POR 0x000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_11_L__SHIFTSAMPLENO_S7_0___POR 0x000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_11_L__SHIFTSAMPLENO_S7_1___M 0x07FF0000 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_11_L__SHIFTSAMPLENO_S7_1___S 16 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_11_L__SHIFTSAMPLENO_S7_0___M 0x000007FF +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_11_L__SHIFTSAMPLENO_S7_0___S 0 +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_11_L___M 0x07FF07FF +#define PHYA_DEMFRONT_1_RU_BD_DEBUG_11_L___S 0 + +#define PHYA_DEMFRONT_1_SDF_BUFFER_L_n(n) (0x005004B8+0x8*(n)) +#define PHYA_DEMFRONT_1_SDF_BUFFER_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_SDF_BUFFER_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_SDF_BUFFER_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_SDF_BUFFER_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SDF_BUFFER_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_SDF_BUFFER_L_n__SDF_BUFFER_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_SDF_BUFFER_L_n__SDF_BUFFER_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_SDF_BUFFER_L_n__SDF_BUFFER_0___S 0 +#define PHYA_DEMFRONT_1_SDF_BUFFER_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_SDF_BUFFER_L_n___S 0 +#define PHYA_DEMFRONT_1_SDF_BUFFER_L_0 (0x005004B8) +#define PHYA_DEMFRONT_1_SDF_BUFFER_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SDF_BUFFER_L_0__SDF_BUFFER_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_SDF_BUFFER_L_0__SDF_BUFFER_0___S 0 + +#define PHYA_DEMFRONT_1_SDF_BUFFER_U_n(n) (0x005004BC+0x8*(n)) +#define PHYA_DEMFRONT_1_SDF_BUFFER_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_SDF_BUFFER_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_SDF_BUFFER_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_SDF_BUFFER_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SDF_BUFFER_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_SDF_BUFFER_U_n__SDF_BUFFER_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_SDF_BUFFER_U_n__SDF_BUFFER_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_SDF_BUFFER_U_n__SDF_BUFFER_1___S 0 +#define PHYA_DEMFRONT_1_SDF_BUFFER_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_SDF_BUFFER_U_n___S 0 +#define PHYA_DEMFRONT_1_SDF_BUFFER_U_0 (0x005004BC) +#define PHYA_DEMFRONT_1_SDF_BUFFER_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SDF_BUFFER_U_0__SDF_BUFFER_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_SDF_BUFFER_U_0__SDF_BUFFER_1___S 0 + +#define PHYA_DEMFRONT_1_SYM_CONTROL_0_L (0x005004C0) +#define PHYA_DEMFRONT_1_SYM_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SYM_CONTROL_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SYM_CONTROL_0_L__LAST_FILL___POR 0x0 +#define PHYA_DEMFRONT_1_SYM_CONTROL_0_L__IS_160___POR 0x0 +#define PHYA_DEMFRONT_1_SYM_CONTROL_0_L__FLUSH_IF_QBPSK___POR 0x0 +#define PHYA_DEMFRONT_1_SYM_CONTROL_0_L__FLUSH___POR 0x0 +#define PHYA_DEMFRONT_1_SYM_CONTROL_0_L__LAST_FILL___M 0x03000000 +#define PHYA_DEMFRONT_1_SYM_CONTROL_0_L__LAST_FILL___S 24 +#define PHYA_DEMFRONT_1_SYM_CONTROL_0_L__IS_160___M 0x00010000 +#define PHYA_DEMFRONT_1_SYM_CONTROL_0_L__IS_160___S 16 +#define PHYA_DEMFRONT_1_SYM_CONTROL_0_L__FLUSH_IF_QBPSK___M 0x00000100 +#define PHYA_DEMFRONT_1_SYM_CONTROL_0_L__FLUSH_IF_QBPSK___S 8 +#define PHYA_DEMFRONT_1_SYM_CONTROL_0_L__FLUSH___M 0x00000001 +#define PHYA_DEMFRONT_1_SYM_CONTROL_0_L__FLUSH___S 0 +#define PHYA_DEMFRONT_1_SYM_CONTROL_0_L___M 0x03010101 +#define PHYA_DEMFRONT_1_SYM_CONTROL_0_L___S 0 + +#define PHYA_DEMFRONT_1_SYM_CONTROL_0_U (0x005004C4) +#define PHYA_DEMFRONT_1_SYM_CONTROL_0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SYM_CONTROL_0_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_SYM_CONTROL_0_U__MAX_LLR_TO_ROBE___POR 0x00 +#define PHYA_DEMFRONT_1_SYM_CONTROL_0_U__MRC_RSHIFT___POR 0x00 +#define PHYA_DEMFRONT_1_SYM_CONTROL_0_U__SYM_TYPE_QBPSK___POR 0x00 +#define PHYA_DEMFRONT_1_SYM_CONTROL_0_U__SYM_TYPE___POR 0x00 +#define PHYA_DEMFRONT_1_SYM_CONTROL_0_U__MAX_LLR_TO_ROBE___M 0x3F000000 +#define PHYA_DEMFRONT_1_SYM_CONTROL_0_U__MAX_LLR_TO_ROBE___S 24 +#define PHYA_DEMFRONT_1_SYM_CONTROL_0_U__MRC_RSHIFT___M 0x003F0000 +#define PHYA_DEMFRONT_1_SYM_CONTROL_0_U__MRC_RSHIFT___S 16 +#define PHYA_DEMFRONT_1_SYM_CONTROL_0_U__SYM_TYPE_QBPSK___M 0x0000FF00 +#define PHYA_DEMFRONT_1_SYM_CONTROL_0_U__SYM_TYPE_QBPSK___S 8 +#define PHYA_DEMFRONT_1_SYM_CONTROL_0_U__SYM_TYPE___M 0x000000FF +#define PHYA_DEMFRONT_1_SYM_CONTROL_0_U__SYM_TYPE___S 0 +#define PHYA_DEMFRONT_1_SYM_CONTROL_0_U___M 0x3F3FFFFF +#define PHYA_DEMFRONT_1_SYM_CONTROL_0_U___S 0 + +#define PHYA_DEMFRONT_1_SYM_CONTROL_1_L (0x005004C8) +#define PHYA_DEMFRONT_1_SYM_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SYM_CONTROL_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SYM_CONTROL_1_L__ENA_LLR_AVG___POR 0x0 +#define PHYA_DEMFRONT_1_SYM_CONTROL_1_L__ENA_MAX_LLR_TO_ROBE___POR 0x0 +#define PHYA_DEMFRONT_1_SYM_CONTROL_1_L__ENA_LLR_STORE___POR 0x0 +#define PHYA_DEMFRONT_1_SYM_CONTROL_1_L__USE_COMBINE_CHAN___POR 0x0 +#define PHYA_DEMFRONT_1_SYM_CONTROL_1_L__ENA_LLR_AVG___M 0x01000000 +#define PHYA_DEMFRONT_1_SYM_CONTROL_1_L__ENA_LLR_AVG___S 24 +#define PHYA_DEMFRONT_1_SYM_CONTROL_1_L__ENA_MAX_LLR_TO_ROBE___M 0x00010000 +#define PHYA_DEMFRONT_1_SYM_CONTROL_1_L__ENA_MAX_LLR_TO_ROBE___S 16 +#define PHYA_DEMFRONT_1_SYM_CONTROL_1_L__ENA_LLR_STORE___M 0x00000100 +#define PHYA_DEMFRONT_1_SYM_CONTROL_1_L__ENA_LLR_STORE___S 8 +#define PHYA_DEMFRONT_1_SYM_CONTROL_1_L__USE_COMBINE_CHAN___M 0x00000001 +#define PHYA_DEMFRONT_1_SYM_CONTROL_1_L__USE_COMBINE_CHAN___S 0 +#define PHYA_DEMFRONT_1_SYM_CONTROL_1_L___M 0x01010101 +#define PHYA_DEMFRONT_1_SYM_CONTROL_1_L___S 0 + +#define PHYA_DEMFRONT_1_SYM_CONTROL_1_U (0x005004CC) +#define PHYA_DEMFRONT_1_SYM_CONTROL_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SYM_CONTROL_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_SYM_CONTROL_1_U__LTF_IDX___POR 0x0 +#define PHYA_DEMFRONT_1_SYM_CONTROL_1_U__ENA_CORR_Y_STORE___POR 0x0 +#define PHYA_DEMFRONT_1_SYM_CONTROL_1_U__ENA_LLR_AVG_QBPSK___POR 0x0 +#define PHYA_DEMFRONT_1_SYM_CONTROL_1_U__ENA_LLR_AVG_RLSIG___POR 0x0 +#define PHYA_DEMFRONT_1_SYM_CONTROL_1_U__LTF_IDX___M 0x07000000 +#define PHYA_DEMFRONT_1_SYM_CONTROL_1_U__LTF_IDX___S 24 +#define PHYA_DEMFRONT_1_SYM_CONTROL_1_U__ENA_CORR_Y_STORE___M 0x00010000 +#define PHYA_DEMFRONT_1_SYM_CONTROL_1_U__ENA_CORR_Y_STORE___S 16 +#define PHYA_DEMFRONT_1_SYM_CONTROL_1_U__ENA_LLR_AVG_QBPSK___M 0x00000100 +#define PHYA_DEMFRONT_1_SYM_CONTROL_1_U__ENA_LLR_AVG_QBPSK___S 8 +#define PHYA_DEMFRONT_1_SYM_CONTROL_1_U__ENA_LLR_AVG_RLSIG___M 0x00000001 +#define PHYA_DEMFRONT_1_SYM_CONTROL_1_U__ENA_LLR_AVG_RLSIG___S 0 +#define PHYA_DEMFRONT_1_SYM_CONTROL_1_U___M 0x07010101 +#define PHYA_DEMFRONT_1_SYM_CONTROL_1_U___S 0 + +#define PHYA_DEMFRONT_1_SYM_CONTROL_2_L (0x005004D0) +#define PHYA_DEMFRONT_1_SYM_CONTROL_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SYM_CONTROL_2_L___POR 0x01000002 +#define PHYA_DEMFRONT_1_SYM_CONTROL_2_L__ASSERT_RXTD_GAIN_RATIO_EVENT___POR 0x1 +#define PHYA_DEMFRONT_1_SYM_CONTROL_2_L__ASSERT_PROC_COMPLETE_EVENT___POR 0x0 +#define PHYA_DEMFRONT_1_SYM_CONTROL_2_L__DISABLE_DEINT_QBPSK___POR 0x0 +#define PHYA_DEMFRONT_1_SYM_CONTROL_2_L__N_LTF___POR 0x2 +#define PHYA_DEMFRONT_1_SYM_CONTROL_2_L__ASSERT_RXTD_GAIN_RATIO_EVENT___M 0x01000000 +#define PHYA_DEMFRONT_1_SYM_CONTROL_2_L__ASSERT_RXTD_GAIN_RATIO_EVENT___S 24 +#define PHYA_DEMFRONT_1_SYM_CONTROL_2_L__ASSERT_PROC_COMPLETE_EVENT___M 0x00010000 +#define PHYA_DEMFRONT_1_SYM_CONTROL_2_L__ASSERT_PROC_COMPLETE_EVENT___S 16 +#define PHYA_DEMFRONT_1_SYM_CONTROL_2_L__DISABLE_DEINT_QBPSK___M 0x00000100 +#define PHYA_DEMFRONT_1_SYM_CONTROL_2_L__DISABLE_DEINT_QBPSK___S 8 +#define PHYA_DEMFRONT_1_SYM_CONTROL_2_L__N_LTF___M 0x0000000F +#define PHYA_DEMFRONT_1_SYM_CONTROL_2_L__N_LTF___S 0 +#define PHYA_DEMFRONT_1_SYM_CONTROL_2_L___M 0x0101010F +#define PHYA_DEMFRONT_1_SYM_CONTROL_2_L___S 0 + +#define PHYA_DEMFRONT_1_SYM_CONTROL_2_U (0x005004D4) +#define PHYA_DEMFRONT_1_SYM_CONTROL_2_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SYM_CONTROL_2_U___POR 0x04010101 +#define PHYA_DEMFRONT_1_SYM_CONTROL_2_U__ACTIVE_RX_CHAIN_COMB___POR 0x4 +#define PHYA_DEMFRONT_1_SYM_CONTROL_2_U__ASSERT_PER_PKT_PROGRAM_EVENT___POR 0x1 +#define PHYA_DEMFRONT_1_SYM_CONTROL_2_U__ASSERT_RXTD_INIT_PHASE_EVENT___POR 0x1 +#define PHYA_DEMFRONT_1_SYM_CONTROL_2_U__ASSERT_RXTD_NOISEPWR_BTCF_EVENT___POR 0x1 +#define PHYA_DEMFRONT_1_SYM_CONTROL_2_U__ACTIVE_RX_CHAIN_COMB___M 0x0F000000 +#define PHYA_DEMFRONT_1_SYM_CONTROL_2_U__ACTIVE_RX_CHAIN_COMB___S 24 +#define PHYA_DEMFRONT_1_SYM_CONTROL_2_U__ASSERT_PER_PKT_PROGRAM_EVENT___M 0x00010000 +#define PHYA_DEMFRONT_1_SYM_CONTROL_2_U__ASSERT_PER_PKT_PROGRAM_EVENT___S 16 +#define PHYA_DEMFRONT_1_SYM_CONTROL_2_U__ASSERT_RXTD_INIT_PHASE_EVENT___M 0x00000100 +#define PHYA_DEMFRONT_1_SYM_CONTROL_2_U__ASSERT_RXTD_INIT_PHASE_EVENT___S 8 +#define PHYA_DEMFRONT_1_SYM_CONTROL_2_U__ASSERT_RXTD_NOISEPWR_BTCF_EVENT___M 0x00000001 +#define PHYA_DEMFRONT_1_SYM_CONTROL_2_U__ASSERT_RXTD_NOISEPWR_BTCF_EVENT___S 0 +#define PHYA_DEMFRONT_1_SYM_CONTROL_2_U___M 0x0F010101 +#define PHYA_DEMFRONT_1_SYM_CONTROL_2_U___S 0 + +#define PHYA_DEMFRONT_1_MRC_CONTROL_0_L (0x005004D8) +#define PHYA_DEMFRONT_1_MRC_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_MRC_CONTROL_0_L___POR 0x30000000 +#define PHYA_DEMFRONT_1_MRC_CONTROL_0_L__QBPSK_DET_NUM_TONES___POR 0x30 +#define PHYA_DEMFRONT_1_MRC_CONTROL_0_L__QBPSK_DET_ENA___POR 0x0 +#define PHYA_DEMFRONT_1_MRC_CONTROL_0_L__MRC_TONE_INVERT___POR 0x0 +#define PHYA_DEMFRONT_1_MRC_CONTROL_0_L__QBPSK_DET_NUM_TONES___M 0x3F000000 +#define PHYA_DEMFRONT_1_MRC_CONTROL_0_L__QBPSK_DET_NUM_TONES___S 24 +#define PHYA_DEMFRONT_1_MRC_CONTROL_0_L__QBPSK_DET_ENA___M 0x00010000 +#define PHYA_DEMFRONT_1_MRC_CONTROL_0_L__QBPSK_DET_ENA___S 16 +#define PHYA_DEMFRONT_1_MRC_CONTROL_0_L__MRC_TONE_INVERT___M 0x00000001 +#define PHYA_DEMFRONT_1_MRC_CONTROL_0_L__MRC_TONE_INVERT___S 0 +#define PHYA_DEMFRONT_1_MRC_CONTROL_0_L___M 0x3F010001 +#define PHYA_DEMFRONT_1_MRC_CONTROL_0_L___S 0 + +#define PHYA_DEMFRONT_1_MRC_CONTROL_0_U (0x005004DC) +#define PHYA_DEMFRONT_1_MRC_CONTROL_0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_MRC_CONTROL_0_U___POR 0x00003000 +#define PHYA_DEMFRONT_1_MRC_CONTROL_0_U__FORCE_IS_RLSIG___POR 0x0 +#define PHYA_DEMFRONT_1_MRC_CONTROL_0_U__FORCE_IS_QBPSK___POR 0x0 +#define PHYA_DEMFRONT_1_MRC_CONTROL_0_U__RLSIG_DET_NUM_TONES___POR 0x30 +#define PHYA_DEMFRONT_1_MRC_CONTROL_0_U__RLSIG_DET_ENA___POR 0x0 +#define PHYA_DEMFRONT_1_MRC_CONTROL_0_U__FORCE_IS_RLSIG___M 0x01000000 +#define PHYA_DEMFRONT_1_MRC_CONTROL_0_U__FORCE_IS_RLSIG___S 24 +#define PHYA_DEMFRONT_1_MRC_CONTROL_0_U__FORCE_IS_QBPSK___M 0x00010000 +#define PHYA_DEMFRONT_1_MRC_CONTROL_0_U__FORCE_IS_QBPSK___S 16 +#define PHYA_DEMFRONT_1_MRC_CONTROL_0_U__RLSIG_DET_NUM_TONES___M 0x00003F00 +#define PHYA_DEMFRONT_1_MRC_CONTROL_0_U__RLSIG_DET_NUM_TONES___S 8 +#define PHYA_DEMFRONT_1_MRC_CONTROL_0_U__RLSIG_DET_ENA___M 0x00000001 +#define PHYA_DEMFRONT_1_MRC_CONTROL_0_U__RLSIG_DET_ENA___S 0 +#define PHYA_DEMFRONT_1_MRC_CONTROL_0_U___M 0x01013F01 +#define PHYA_DEMFRONT_1_MRC_CONTROL_0_U___S 0 + +#define PHYA_DEMFRONT_1_MRC_CONTROL_1_L (0x005004E0) +#define PHYA_DEMFRONT_1_MRC_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_MRC_CONTROL_1_L___POR 0x08000000 +#define PHYA_DEMFRONT_1_MRC_CONTROL_1_L__ULMU_MIMO_N_LTF_IN_TRACKING___POR 0x8 +#define PHYA_DEMFRONT_1_MRC_CONTROL_1_L__ULMU_MIMO_LTF_TRACK_ENABLE___POR 0x0 +#define PHYA_DEMFRONT_1_MRC_CONTROL_1_L__BIN_RSHIFT_SCALE___POR 0x0 +#define PHYA_DEMFRONT_1_MRC_CONTROL_1_L__ENA_EQ_INV_SAT___POR 0x0 +#define PHYA_DEMFRONT_1_MRC_CONTROL_1_L__ULMU_MIMO_N_LTF_IN_TRACKING___M 0x0F000000 +#define PHYA_DEMFRONT_1_MRC_CONTROL_1_L__ULMU_MIMO_N_LTF_IN_TRACKING___S 24 +#define PHYA_DEMFRONT_1_MRC_CONTROL_1_L__ULMU_MIMO_LTF_TRACK_ENABLE___M 0x00010000 +#define PHYA_DEMFRONT_1_MRC_CONTROL_1_L__ULMU_MIMO_LTF_TRACK_ENABLE___S 16 +#define PHYA_DEMFRONT_1_MRC_CONTROL_1_L__BIN_RSHIFT_SCALE___M 0x00000300 +#define PHYA_DEMFRONT_1_MRC_CONTROL_1_L__BIN_RSHIFT_SCALE___S 8 +#define PHYA_DEMFRONT_1_MRC_CONTROL_1_L__ENA_EQ_INV_SAT___M 0x00000001 +#define PHYA_DEMFRONT_1_MRC_CONTROL_1_L__ENA_EQ_INV_SAT___S 0 +#define PHYA_DEMFRONT_1_MRC_CONTROL_1_L___M 0x0F010301 +#define PHYA_DEMFRONT_1_MRC_CONTROL_1_L___S 0 + +#define PHYA_DEMFRONT_1_USER_SPARE_1_L (0x005004E8) +#define PHYA_DEMFRONT_1_USER_SPARE_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_USER_SPARE_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_USER_SPARE_1_L__NEXT_DESC_WR_MRC_SPARE_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_USER_SPARE_1_L__NEXT_DESC_WR_MRC_SPARE_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_USER_SPARE_1_L__NEXT_DESC_WR_MRC_SPARE_0___S 0 +#define PHYA_DEMFRONT_1_USER_SPARE_1_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_USER_SPARE_1_L___S 0 + +#define PHYA_DEMFRONT_1_USER_SPARE_1_U (0x005004EC) +#define PHYA_DEMFRONT_1_USER_SPARE_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_USER_SPARE_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_USER_SPARE_1_U__NEXT_DESC_WR_MRC_SPARE_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_USER_SPARE_1_U__NEXT_DESC_WR_MRC_SPARE_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_USER_SPARE_1_U__NEXT_DESC_WR_MRC_SPARE_1___S 0 +#define PHYA_DEMFRONT_1_USER_SPARE_1_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_USER_SPARE_1_U___S 0 + +#define PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_L (0x005004F0) +#define PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_L__ENABLE_SM_CHE_COPY___POR 0x0 +#define PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_L__ENABLE_SM_BW___POR 0x0 +#define PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_L__ENABLE_SM_PTC___POR 0x0 +#define PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_L__ENABLE_SM_CHE___POR 0x0 +#define PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_L__ENABLE_SM_CHE_COPY___M 0x01000000 +#define PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_L__ENABLE_SM_CHE_COPY___S 24 +#define PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_L__ENABLE_SM_BW___M 0x00010000 +#define PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_L__ENABLE_SM_BW___S 16 +#define PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_L__ENABLE_SM_PTC___M 0x00000100 +#define PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_L__ENABLE_SM_PTC___S 8 +#define PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_L__ENABLE_SM_CHE___M 0x00000001 +#define PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_L__ENABLE_SM_CHE___S 0 +#define PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_L___M 0x01010101 +#define PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_L___S 0 + +#define PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_U (0x005004F4) +#define PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_U__DL_OFDMA_IS_EXT80___POR 0x0 +#define PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_U__DL_OFDMA_IS_EXT80___M 0x00000001 +#define PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_U__DL_OFDMA_IS_EXT80___S 0 +#define PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_U___M 0x00000001 +#define PHYA_DEMFRONT_1_SPUR_MAIN_CONTROL_U___S 0 + +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_0_L (0x005004F8) +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_0_L___POR 0x000001FF +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_0_L__SM0_SPUR_IDX___POR 0x01FF +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_0_L__SM0_SPUR_IDX___M 0x0000FFFF +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_0_L__SM0_SPUR_IDX___S 0 +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_0_L___M 0x0000FFFF +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_0_L___S 0 + +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_L (0x00500500) +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_L__SM0_3_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_L__SM0_2_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_L__SM0_1_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_L__SM0_0_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_L__SM0_3_SPUR_MASK___M 0x07000000 +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_L__SM0_3_SPUR_MASK___S 24 +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_L__SM0_2_SPUR_MASK___M 0x00070000 +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_L__SM0_2_SPUR_MASK___S 16 +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_L__SM0_1_SPUR_MASK___M 0x00000700 +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_L__SM0_1_SPUR_MASK___S 8 +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_L__SM0_0_SPUR_MASK___M 0x00000007 +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_L__SM0_0_SPUR_MASK___S 0 +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_L___M 0x07070707 +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_L___S 0 + +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_U (0x00500504) +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_U__SM0_4_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_U__SM0_4_SPUR_MASK___M 0x00000007 +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_U__SM0_4_SPUR_MASK___S 0 +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_U___M 0x00000007 +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_1_U___S 0 + +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_2_L (0x00500508) +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_2_L__SM0_SPUR_CP_OFFSET_R___POR 0x00 +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_2_L__SM0_SPUR_CP_OFFSET_L___POR 0x00 +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_2_L__SM0_SPUR_CP_OFFSET_R___M 0x0000FF00 +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_2_L__SM0_SPUR_CP_OFFSET_R___S 8 +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_2_L__SM0_SPUR_CP_OFFSET_L___M 0x000000FF +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_2_L__SM0_SPUR_CP_OFFSET_L___S 0 +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_2_L___M 0x0000FFFF +#define PHYA_DEMFRONT_1_SM0_SPUR_CONTROL_2_L___S 0 + +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_0_L (0x00500510) +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_0_L___POR 0x000001FF +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_0_L__SM1_SPUR_IDX___POR 0x01FF +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_0_L__SM1_SPUR_IDX___M 0x0000FFFF +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_0_L__SM1_SPUR_IDX___S 0 +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_0_L___M 0x0000FFFF +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_0_L___S 0 + +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_L (0x00500518) +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_L__SM1_3_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_L__SM1_2_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_L__SM1_1_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_L__SM1_0_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_L__SM1_3_SPUR_MASK___M 0x07000000 +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_L__SM1_3_SPUR_MASK___S 24 +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_L__SM1_2_SPUR_MASK___M 0x00070000 +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_L__SM1_2_SPUR_MASK___S 16 +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_L__SM1_1_SPUR_MASK___M 0x00000700 +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_L__SM1_1_SPUR_MASK___S 8 +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_L__SM1_0_SPUR_MASK___M 0x00000007 +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_L__SM1_0_SPUR_MASK___S 0 +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_L___M 0x07070707 +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_L___S 0 + +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_U (0x0050051C) +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_U__SM1_4_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_U__SM1_4_SPUR_MASK___M 0x00000007 +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_U__SM1_4_SPUR_MASK___S 0 +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_U___M 0x00000007 +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_1_U___S 0 + +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_2_L (0x00500520) +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_2_L__SM1_SPUR_CP_OFFSET_R___POR 0x00 +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_2_L__SM1_SPUR_CP_OFFSET_L___POR 0x00 +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_2_L__SM1_SPUR_CP_OFFSET_R___M 0x0000FF00 +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_2_L__SM1_SPUR_CP_OFFSET_R___S 8 +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_2_L__SM1_SPUR_CP_OFFSET_L___M 0x000000FF +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_2_L__SM1_SPUR_CP_OFFSET_L___S 0 +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_2_L___M 0x0000FFFF +#define PHYA_DEMFRONT_1_SM1_SPUR_CONTROL_2_L___S 0 + +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_0_L (0x00500528) +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_0_L___POR 0x000001FF +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_0_L__SM2_SPUR_IDX___POR 0x01FF +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_0_L__SM2_SPUR_IDX___M 0x0000FFFF +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_0_L__SM2_SPUR_IDX___S 0 +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_0_L___M 0x0000FFFF +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_0_L___S 0 + +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_L (0x00500530) +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_L__SM2_3_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_L__SM2_2_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_L__SM2_1_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_L__SM2_0_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_L__SM2_3_SPUR_MASK___M 0x07000000 +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_L__SM2_3_SPUR_MASK___S 24 +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_L__SM2_2_SPUR_MASK___M 0x00070000 +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_L__SM2_2_SPUR_MASK___S 16 +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_L__SM2_1_SPUR_MASK___M 0x00000700 +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_L__SM2_1_SPUR_MASK___S 8 +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_L__SM2_0_SPUR_MASK___M 0x00000007 +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_L__SM2_0_SPUR_MASK___S 0 +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_L___M 0x07070707 +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_L___S 0 + +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_U (0x00500534) +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_U__SM2_4_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_U__SM2_4_SPUR_MASK___M 0x00000007 +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_U__SM2_4_SPUR_MASK___S 0 +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_U___M 0x00000007 +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_1_U___S 0 + +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_2_L (0x00500538) +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_2_L__SM2_SPUR_CP_OFFSET_R___POR 0x00 +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_2_L__SM2_SPUR_CP_OFFSET_L___POR 0x00 +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_2_L__SM2_SPUR_CP_OFFSET_R___M 0x0000FF00 +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_2_L__SM2_SPUR_CP_OFFSET_R___S 8 +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_2_L__SM2_SPUR_CP_OFFSET_L___M 0x000000FF +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_2_L__SM2_SPUR_CP_OFFSET_L___S 0 +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_2_L___M 0x0000FFFF +#define PHYA_DEMFRONT_1_SM2_SPUR_CONTROL_2_L___S 0 + +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_0_L (0x00500540) +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_0_L___POR 0x000001FF +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_0_L__SM3_SPUR_IDX___POR 0x01FF +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_0_L__SM3_SPUR_IDX___M 0x0000FFFF +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_0_L__SM3_SPUR_IDX___S 0 +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_0_L___M 0x0000FFFF +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_0_L___S 0 + +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_L (0x00500548) +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_L__SM3_3_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_L__SM3_2_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_L__SM3_1_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_L__SM3_0_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_L__SM3_3_SPUR_MASK___M 0x07000000 +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_L__SM3_3_SPUR_MASK___S 24 +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_L__SM3_2_SPUR_MASK___M 0x00070000 +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_L__SM3_2_SPUR_MASK___S 16 +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_L__SM3_1_SPUR_MASK___M 0x00000700 +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_L__SM3_1_SPUR_MASK___S 8 +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_L__SM3_0_SPUR_MASK___M 0x00000007 +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_L__SM3_0_SPUR_MASK___S 0 +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_L___M 0x07070707 +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_L___S 0 + +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_U (0x0050054C) +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_U__SM3_4_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_U__SM3_4_SPUR_MASK___M 0x00000007 +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_U__SM3_4_SPUR_MASK___S 0 +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_U___M 0x00000007 +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_1_U___S 0 + +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_2_L (0x00500550) +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_2_L__SM3_SPUR_CP_OFFSET_R___POR 0x00 +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_2_L__SM3_SPUR_CP_OFFSET_L___POR 0x00 +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_2_L__SM3_SPUR_CP_OFFSET_R___M 0x0000FF00 +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_2_L__SM3_SPUR_CP_OFFSET_R___S 8 +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_2_L__SM3_SPUR_CP_OFFSET_L___M 0x000000FF +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_2_L__SM3_SPUR_CP_OFFSET_L___S 0 +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_2_L___M 0x0000FFFF +#define PHYA_DEMFRONT_1_SM3_SPUR_CONTROL_2_L___S 0 + +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_0_L (0x00500558) +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_0_L___POR 0x000001FF +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_0_L__SM4_SPUR_IDX___POR 0x01FF +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_0_L__SM4_SPUR_IDX___M 0x0000FFFF +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_0_L__SM4_SPUR_IDX___S 0 +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_0_L___M 0x0000FFFF +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_0_L___S 0 + +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_L (0x00500560) +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_L__SM4_3_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_L__SM4_2_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_L__SM4_1_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_L__SM4_0_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_L__SM4_3_SPUR_MASK___M 0x07000000 +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_L__SM4_3_SPUR_MASK___S 24 +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_L__SM4_2_SPUR_MASK___M 0x00070000 +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_L__SM4_2_SPUR_MASK___S 16 +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_L__SM4_1_SPUR_MASK___M 0x00000700 +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_L__SM4_1_SPUR_MASK___S 8 +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_L__SM4_0_SPUR_MASK___M 0x00000007 +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_L__SM4_0_SPUR_MASK___S 0 +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_L___M 0x07070707 +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_L___S 0 + +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_U (0x00500564) +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_U__SM4_4_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_U__SM4_4_SPUR_MASK___M 0x00000007 +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_U__SM4_4_SPUR_MASK___S 0 +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_U___M 0x00000007 +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_1_U___S 0 + +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_2_L (0x00500568) +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_2_L__SM4_SPUR_CP_OFFSET_R___POR 0x00 +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_2_L__SM4_SPUR_CP_OFFSET_L___POR 0x00 +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_2_L__SM4_SPUR_CP_OFFSET_R___M 0x0000FF00 +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_2_L__SM4_SPUR_CP_OFFSET_R___S 8 +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_2_L__SM4_SPUR_CP_OFFSET_L___M 0x000000FF +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_2_L__SM4_SPUR_CP_OFFSET_L___S 0 +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_2_L___M 0x0000FFFF +#define PHYA_DEMFRONT_1_SM4_SPUR_CONTROL_2_L___S 0 + +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_0_L (0x00500570) +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_0_L___POR 0x000001FF +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_0_L__SM5_SPUR_IDX___POR 0x01FF +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_0_L__SM5_SPUR_IDX___M 0x0000FFFF +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_0_L__SM5_SPUR_IDX___S 0 +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_0_L___M 0x0000FFFF +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_0_L___S 0 + +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_L (0x00500578) +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_L__SM5_3_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_L__SM5_2_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_L__SM5_1_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_L__SM5_0_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_L__SM5_3_SPUR_MASK___M 0x07000000 +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_L__SM5_3_SPUR_MASK___S 24 +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_L__SM5_2_SPUR_MASK___M 0x00070000 +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_L__SM5_2_SPUR_MASK___S 16 +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_L__SM5_1_SPUR_MASK___M 0x00000700 +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_L__SM5_1_SPUR_MASK___S 8 +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_L__SM5_0_SPUR_MASK___M 0x00000007 +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_L__SM5_0_SPUR_MASK___S 0 +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_L___M 0x07070707 +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_L___S 0 + +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_U (0x0050057C) +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_U__SM5_4_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_U__SM5_4_SPUR_MASK___M 0x00000007 +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_U__SM5_4_SPUR_MASK___S 0 +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_U___M 0x00000007 +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_1_U___S 0 + +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_2_L (0x00500580) +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_2_L__SM5_SPUR_CP_OFFSET_R___POR 0x00 +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_2_L__SM5_SPUR_CP_OFFSET_L___POR 0x00 +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_2_L__SM5_SPUR_CP_OFFSET_R___M 0x0000FF00 +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_2_L__SM5_SPUR_CP_OFFSET_R___S 8 +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_2_L__SM5_SPUR_CP_OFFSET_L___M 0x000000FF +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_2_L__SM5_SPUR_CP_OFFSET_L___S 0 +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_2_L___M 0x0000FFFF +#define PHYA_DEMFRONT_1_SM5_SPUR_CONTROL_2_L___S 0 + +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_0_L (0x00500588) +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_0_L___POR 0x000001FF +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_0_L__SM6_SPUR_IDX___POR 0x01FF +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_0_L__SM6_SPUR_IDX___M 0x0000FFFF +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_0_L__SM6_SPUR_IDX___S 0 +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_0_L___M 0x0000FFFF +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_0_L___S 0 + +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_L (0x00500590) +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_L__SM6_3_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_L__SM6_2_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_L__SM6_1_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_L__SM6_0_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_L__SM6_3_SPUR_MASK___M 0x07000000 +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_L__SM6_3_SPUR_MASK___S 24 +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_L__SM6_2_SPUR_MASK___M 0x00070000 +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_L__SM6_2_SPUR_MASK___S 16 +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_L__SM6_1_SPUR_MASK___M 0x00000700 +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_L__SM6_1_SPUR_MASK___S 8 +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_L__SM6_0_SPUR_MASK___M 0x00000007 +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_L__SM6_0_SPUR_MASK___S 0 +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_L___M 0x07070707 +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_L___S 0 + +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_U (0x00500594) +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_U__SM6_4_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_U__SM6_4_SPUR_MASK___M 0x00000007 +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_U__SM6_4_SPUR_MASK___S 0 +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_U___M 0x00000007 +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_1_U___S 0 + +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_2_L (0x00500598) +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_2_L__SM6_SPUR_CP_OFFSET_R___POR 0x00 +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_2_L__SM6_SPUR_CP_OFFSET_L___POR 0x00 +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_2_L__SM6_SPUR_CP_OFFSET_R___M 0x0000FF00 +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_2_L__SM6_SPUR_CP_OFFSET_R___S 8 +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_2_L__SM6_SPUR_CP_OFFSET_L___M 0x000000FF +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_2_L__SM6_SPUR_CP_OFFSET_L___S 0 +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_2_L___M 0x0000FFFF +#define PHYA_DEMFRONT_1_SM6_SPUR_CONTROL_2_L___S 0 + +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_0_L (0x005005A0) +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_0_L___POR 0x000001FF +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_0_L__SM7_SPUR_IDX___POR 0x01FF +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_0_L__SM7_SPUR_IDX___M 0x0000FFFF +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_0_L__SM7_SPUR_IDX___S 0 +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_0_L___M 0x0000FFFF +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_0_L___S 0 + +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_L (0x005005A8) +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_L__SM7_3_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_L__SM7_2_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_L__SM7_1_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_L__SM7_0_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_L__SM7_3_SPUR_MASK___M 0x07000000 +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_L__SM7_3_SPUR_MASK___S 24 +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_L__SM7_2_SPUR_MASK___M 0x00070000 +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_L__SM7_2_SPUR_MASK___S 16 +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_L__SM7_1_SPUR_MASK___M 0x00000700 +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_L__SM7_1_SPUR_MASK___S 8 +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_L__SM7_0_SPUR_MASK___M 0x00000007 +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_L__SM7_0_SPUR_MASK___S 0 +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_L___M 0x07070707 +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_L___S 0 + +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_U (0x005005AC) +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_U__SM7_4_SPUR_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_U__SM7_4_SPUR_MASK___M 0x00000007 +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_U__SM7_4_SPUR_MASK___S 0 +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_U___M 0x00000007 +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_1_U___S 0 + +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_2_L (0x005005B0) +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_2_L__SM7_SPUR_CP_OFFSET_R___POR 0x00 +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_2_L__SM7_SPUR_CP_OFFSET_L___POR 0x00 +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_2_L__SM7_SPUR_CP_OFFSET_R___M 0x0000FF00 +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_2_L__SM7_SPUR_CP_OFFSET_R___S 8 +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_2_L__SM7_SPUR_CP_OFFSET_L___M 0x000000FF +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_2_L__SM7_SPUR_CP_OFFSET_L___S 0 +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_2_L___M 0x0000FFFF +#define PHYA_DEMFRONT_1_SM7_SPUR_CONTROL_2_L___S 0 + +#define PHYA_DEMFRONT_1_CHE_CONTROL_0_L (0x005005B8) +#define PHYA_DEMFRONT_1_CHE_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CHE_CONTROL_0_L___POR 0x02000000 +#define PHYA_DEMFRONT_1_CHE_CONTROL_0_L__FREQ_SEL_ID_LAG_SEL___POR 0x2 +#define PHYA_DEMFRONT_1_CHE_CONTROL_0_L__SLOPE_SCALE___POR 0x0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_0_L__LOG2_FFT_SIZE___POR 0x0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_0_L__HE_INTERPOLATION___POR 0x0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_0_L__FREQ_SEL_ID_LAG_SEL___M 0x03000000 +#define PHYA_DEMFRONT_1_CHE_CONTROL_0_L__FREQ_SEL_ID_LAG_SEL___S 24 +#define PHYA_DEMFRONT_1_CHE_CONTROL_0_L__SLOPE_SCALE___M 0x00070000 +#define PHYA_DEMFRONT_1_CHE_CONTROL_0_L__SLOPE_SCALE___S 16 +#define PHYA_DEMFRONT_1_CHE_CONTROL_0_L__LOG2_FFT_SIZE___M 0x00000F00 +#define PHYA_DEMFRONT_1_CHE_CONTROL_0_L__LOG2_FFT_SIZE___S 8 +#define PHYA_DEMFRONT_1_CHE_CONTROL_0_L__HE_INTERPOLATION___M 0x00000003 +#define PHYA_DEMFRONT_1_CHE_CONTROL_0_L__HE_INTERPOLATION___S 0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_0_L___M 0x03070F03 +#define PHYA_DEMFRONT_1_CHE_CONTROL_0_L___S 0 + +#define PHYA_DEMFRONT_1_CHE_CONTROL_0_U (0x005005BC) +#define PHYA_DEMFRONT_1_CHE_CONTROL_0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CHE_CONTROL_0_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_CHE_CONTROL_0_U__SUBBAND_ROT_DIS___POR 0x0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_0_U__EN_CSD_REMOVAL___POR 0x0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_0_U__EN_SLOPE_ADDITION___POR 0x0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_0_U__EN_SLOPE_REMOVAL___POR 0x0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_0_U__SUBBAND_ROT_DIS___M 0x01000000 +#define PHYA_DEMFRONT_1_CHE_CONTROL_0_U__SUBBAND_ROT_DIS___S 24 +#define PHYA_DEMFRONT_1_CHE_CONTROL_0_U__EN_CSD_REMOVAL___M 0x00010000 +#define PHYA_DEMFRONT_1_CHE_CONTROL_0_U__EN_CSD_REMOVAL___S 16 +#define PHYA_DEMFRONT_1_CHE_CONTROL_0_U__EN_SLOPE_ADDITION___M 0x00000100 +#define PHYA_DEMFRONT_1_CHE_CONTROL_0_U__EN_SLOPE_ADDITION___S 8 +#define PHYA_DEMFRONT_1_CHE_CONTROL_0_U__EN_SLOPE_REMOVAL___M 0x00000001 +#define PHYA_DEMFRONT_1_CHE_CONTROL_0_U__EN_SLOPE_REMOVAL___S 0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_0_U___M 0x01010101 +#define PHYA_DEMFRONT_1_CHE_CONTROL_0_U___S 0 + +#define PHYA_DEMFRONT_1_CHE_CONTROL_1_L (0x005005C0) +#define PHYA_DEMFRONT_1_CHE_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CHE_CONTROL_1_L___POR 0x02000000 +#define PHYA_DEMFRONT_1_CHE_CONTROL_1_L__CC_START_TONE___POR 0x200 +#define PHYA_DEMFRONT_1_CHE_CONTROL_1_L__FE_FILTER_ROT_TABLE_SEL___POR 0x0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_1_L__EN_QRMEM_SPLIT___POR 0x0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_1_L__CC_START_TONE___M 0x03FF0000 +#define PHYA_DEMFRONT_1_CHE_CONTROL_1_L__CC_START_TONE___S 16 +#define PHYA_DEMFRONT_1_CHE_CONTROL_1_L__FE_FILTER_ROT_TABLE_SEL___M 0x00000300 +#define PHYA_DEMFRONT_1_CHE_CONTROL_1_L__FE_FILTER_ROT_TABLE_SEL___S 8 +#define PHYA_DEMFRONT_1_CHE_CONTROL_1_L__EN_QRMEM_SPLIT___M 0x00000001 +#define PHYA_DEMFRONT_1_CHE_CONTROL_1_L__EN_QRMEM_SPLIT___S 0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_1_L___M 0x03FF0301 +#define PHYA_DEMFRONT_1_CHE_CONTROL_1_L___S 0 + +#define PHYA_DEMFRONT_1_CHE_CONTROL_1_U (0x005005C4) +#define PHYA_DEMFRONT_1_CHE_CONTROL_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CHE_CONTROL_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_CHE_CONTROL_1_U__DFCHE_EN___POR 0x0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_1_U__DSRC_EN___POR 0x0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_1_U__LSIG_DF_EN___POR 0x0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_1_U__DSRC_ADAPTIVE_ADD_EN___POR 0x0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_1_U__DFCHE_EN___M 0x01000000 +#define PHYA_DEMFRONT_1_CHE_CONTROL_1_U__DFCHE_EN___S 24 +#define PHYA_DEMFRONT_1_CHE_CONTROL_1_U__DSRC_EN___M 0x00010000 +#define PHYA_DEMFRONT_1_CHE_CONTROL_1_U__DSRC_EN___S 16 +#define PHYA_DEMFRONT_1_CHE_CONTROL_1_U__LSIG_DF_EN___M 0x00000100 +#define PHYA_DEMFRONT_1_CHE_CONTROL_1_U__LSIG_DF_EN___S 8 +#define PHYA_DEMFRONT_1_CHE_CONTROL_1_U__DSRC_ADAPTIVE_ADD_EN___M 0x00000001 +#define PHYA_DEMFRONT_1_CHE_CONTROL_1_U__DSRC_ADAPTIVE_ADD_EN___S 0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_1_U___M 0x01010101 +#define PHYA_DEMFRONT_1_CHE_CONTROL_1_U___S 0 + +#define PHYA_DEMFRONT_1_CHE_CONTROL_2_L (0x005005C8) +#define PHYA_DEMFRONT_1_CHE_CONTROL_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CHE_CONTROL_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_CHE_CONTROL_2_L__ENA_CHE_AVERAGE___POR 0x0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_2_L__EN_RESCALE_AMT_SHIFT___POR 0x0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_2_L__COMPUTE_AMT_SHIFT___POR 0x0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_2_L__PBD_EN___POR 0x0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_2_L__ENA_CHE_AVERAGE___M 0x01000000 +#define PHYA_DEMFRONT_1_CHE_CONTROL_2_L__ENA_CHE_AVERAGE___S 24 +#define PHYA_DEMFRONT_1_CHE_CONTROL_2_L__EN_RESCALE_AMT_SHIFT___M 0x00010000 +#define PHYA_DEMFRONT_1_CHE_CONTROL_2_L__EN_RESCALE_AMT_SHIFT___S 16 +#define PHYA_DEMFRONT_1_CHE_CONTROL_2_L__COMPUTE_AMT_SHIFT___M 0x00000100 +#define PHYA_DEMFRONT_1_CHE_CONTROL_2_L__COMPUTE_AMT_SHIFT___S 8 +#define PHYA_DEMFRONT_1_CHE_CONTROL_2_L__PBD_EN___M 0x00000001 +#define PHYA_DEMFRONT_1_CHE_CONTROL_2_L__PBD_EN___S 0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_2_L___M 0x01010101 +#define PHYA_DEMFRONT_1_CHE_CONTROL_2_L___S 0 + +#define PHYA_DEMFRONT_1_CHE_CONTROL_2_U (0x005005CC) +#define PHYA_DEMFRONT_1_CHE_CONTROL_2_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CHE_CONTROL_2_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_CHE_CONTROL_2_U__DFHD_CMBN_ALPHA___POR 0x0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_2_U__EN_DFHD_CHAN_TRACK_ON_PILOT___POR 0x0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_2_U__EN_DFHD_CHAN_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_2_U__EN_DFHD_CHAN_FILTER___POR 0x0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_2_U__DFHD_CMBN_ALPHA___M 0x07000000 +#define PHYA_DEMFRONT_1_CHE_CONTROL_2_U__DFHD_CMBN_ALPHA___S 24 +#define PHYA_DEMFRONT_1_CHE_CONTROL_2_U__EN_DFHD_CHAN_TRACK_ON_PILOT___M 0x00010000 +#define PHYA_DEMFRONT_1_CHE_CONTROL_2_U__EN_DFHD_CHAN_TRACK_ON_PILOT___S 16 +#define PHYA_DEMFRONT_1_CHE_CONTROL_2_U__EN_DFHD_CHAN_MASK___M 0x00000100 +#define PHYA_DEMFRONT_1_CHE_CONTROL_2_U__EN_DFHD_CHAN_MASK___S 8 +#define PHYA_DEMFRONT_1_CHE_CONTROL_2_U__EN_DFHD_CHAN_FILTER___M 0x00000001 +#define PHYA_DEMFRONT_1_CHE_CONTROL_2_U__EN_DFHD_CHAN_FILTER___S 0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_2_U___M 0x07010101 +#define PHYA_DEMFRONT_1_CHE_CONTROL_2_U___S 0 + +#define PHYA_DEMFRONT_1_CHE_CONTROL_3_L (0x005005D0) +#define PHYA_DEMFRONT_1_CHE_CONTROL_3_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CHE_CONTROL_3_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_CHE_CONTROL_3_L__SDF_CODE_RATE___POR 0x0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_3_L__SDF_BUFFER_MODE___POR 0x0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_3_L__SDF_DTONE_BUFFER_IDX___POR 0x0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_3_L__SDF_DTONE_BUFFER_EN___POR 0x0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_3_L__SDF_CODE_RATE___M 0x03000000 +#define PHYA_DEMFRONT_1_CHE_CONTROL_3_L__SDF_CODE_RATE___S 24 +#define PHYA_DEMFRONT_1_CHE_CONTROL_3_L__SDF_BUFFER_MODE___M 0x00010000 +#define PHYA_DEMFRONT_1_CHE_CONTROL_3_L__SDF_BUFFER_MODE___S 16 +#define PHYA_DEMFRONT_1_CHE_CONTROL_3_L__SDF_DTONE_BUFFER_IDX___M 0x00000700 +#define PHYA_DEMFRONT_1_CHE_CONTROL_3_L__SDF_DTONE_BUFFER_IDX___S 8 +#define PHYA_DEMFRONT_1_CHE_CONTROL_3_L__SDF_DTONE_BUFFER_EN___M 0x00000001 +#define PHYA_DEMFRONT_1_CHE_CONTROL_3_L__SDF_DTONE_BUFFER_EN___S 0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_3_L___M 0x03010701 +#define PHYA_DEMFRONT_1_CHE_CONTROL_3_L___S 0 + +#define PHYA_DEMFRONT_1_CHE_CONTROL_3_U (0x005005D4) +#define PHYA_DEMFRONT_1_CHE_CONTROL_3_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CHE_CONTROL_3_U___POR 0x00010000 +#define PHYA_DEMFRONT_1_CHE_CONTROL_3_U__DSBL_SM_DC_EDGE_TONE_NUM___POR 0x0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_3_U__EN_TONE_REPLACEMENT___POR 0x1 +#define PHYA_DEMFRONT_1_CHE_CONTROL_3_U__CHE_CA_TONE_NUM___POR 0x000 +#define PHYA_DEMFRONT_1_CHE_CONTROL_3_U__DSBL_SM_DC_EDGE_TONE_NUM___M 0x0F000000 +#define PHYA_DEMFRONT_1_CHE_CONTROL_3_U__DSBL_SM_DC_EDGE_TONE_NUM___S 24 +#define PHYA_DEMFRONT_1_CHE_CONTROL_3_U__EN_TONE_REPLACEMENT___M 0x00010000 +#define PHYA_DEMFRONT_1_CHE_CONTROL_3_U__EN_TONE_REPLACEMENT___S 16 +#define PHYA_DEMFRONT_1_CHE_CONTROL_3_U__CHE_CA_TONE_NUM___M 0x000003FF +#define PHYA_DEMFRONT_1_CHE_CONTROL_3_U__CHE_CA_TONE_NUM___S 0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_3_U___M 0x0F0103FF +#define PHYA_DEMFRONT_1_CHE_CONTROL_3_U___S 0 + +#define PHYA_DEMFRONT_1_CHE_CONTROL_4_L (0x005005D8) +#define PHYA_DEMFRONT_1_CHE_CONTROL_4_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CHE_CONTROL_4_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_CHE_CONTROL_4_L__CC_TONE_DECIMATION___POR 0x0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_4_L__RTT_PACK_MODE___POR 0x0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_4_L__SM_FILTER_NOT_FLAT_OVERRIDE___POR 0x0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_4_L__CC_TONE_DECIMATION___M 0x00030000 +#define PHYA_DEMFRONT_1_CHE_CONTROL_4_L__CC_TONE_DECIMATION___S 16 +#define PHYA_DEMFRONT_1_CHE_CONTROL_4_L__RTT_PACK_MODE___M 0x00000300 +#define PHYA_DEMFRONT_1_CHE_CONTROL_4_L__RTT_PACK_MODE___S 8 +#define PHYA_DEMFRONT_1_CHE_CONTROL_4_L__SM_FILTER_NOT_FLAT_OVERRIDE___M 0x00000001 +#define PHYA_DEMFRONT_1_CHE_CONTROL_4_L__SM_FILTER_NOT_FLAT_OVERRIDE___S 0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_4_L___M 0x00030301 +#define PHYA_DEMFRONT_1_CHE_CONTROL_4_L___S 0 + +#define PHYA_DEMFRONT_1_CHE_CONTROL_4_U (0x005005DC) +#define PHYA_DEMFRONT_1_CHE_CONTROL_4_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CHE_CONTROL_4_U___POR 0x01010000 +#define PHYA_DEMFRONT_1_CHE_CONTROL_4_U__EN_HIGH_FREQ_SELECT_CHECK___POR 0x1 +#define PHYA_DEMFRONT_1_CHE_CONTROL_4_U__CHAN_SM_FILT_BACKOFF___POR 0x1 +#define PHYA_DEMFRONT_1_CHE_CONTROL_4_U__LTF_PATTERN_SHIFT___POR 0x000 +#define PHYA_DEMFRONT_1_CHE_CONTROL_4_U__EN_HIGH_FREQ_SELECT_CHECK___M 0x01000000 +#define PHYA_DEMFRONT_1_CHE_CONTROL_4_U__EN_HIGH_FREQ_SELECT_CHECK___S 24 +#define PHYA_DEMFRONT_1_CHE_CONTROL_4_U__CHAN_SM_FILT_BACKOFF___M 0x00010000 +#define PHYA_DEMFRONT_1_CHE_CONTROL_4_U__CHAN_SM_FILT_BACKOFF___S 16 +#define PHYA_DEMFRONT_1_CHE_CONTROL_4_U__LTF_PATTERN_SHIFT___M 0x000003FF +#define PHYA_DEMFRONT_1_CHE_CONTROL_4_U__LTF_PATTERN_SHIFT___S 0 +#define PHYA_DEMFRONT_1_CHE_CONTROL_4_U___M 0x010103FF +#define PHYA_DEMFRONT_1_CHE_CONTROL_4_U___S 0 + +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_L (0x005005E0) +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_L__DELTA_SLOPE_COEF_EXP_BW___POR 0x000 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_L__DELTA_SLOPE_COEF_MAN_BW___POR 0x0000 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_L__DELTA_SLOPE_COEF_EXP_BW___M 0x03FF0000 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_L__DELTA_SLOPE_COEF_EXP_BW___S 16 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_L__DELTA_SLOPE_COEF_MAN_BW___M 0x00007FFF +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_L__DELTA_SLOPE_COEF_MAN_BW___S 0 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_L___M 0x03FF7FFF +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_L___S 0 + +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_U (0x005005E4) +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_U__PTC_PHASE_OFFSET_BIAS___POR 0x0000 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_U__DELTAF_SIGN___POR 0x0 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_U__PTC_PHASE_OFFSET_BIAS___M 0xFFFF0000 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_U__PTC_PHASE_OFFSET_BIAS___S 16 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_U__DELTAF_SIGN___M 0x00000001 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_U__DELTAF_SIGN___S 0 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_U___M 0xFFFF0001 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_0_U___S 0 + +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_L (0x005005E8) +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_L__TARGET_SLOPE___POR 0x00000000 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_L__TARGET_SLOPE___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_L__TARGET_SLOPE___S 0 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_L___S 0 + +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_U (0x005005EC) +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_U__ENABLE_PPM_RESCUE___POR 0x0 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_U__ENABLE_OFFSET_FILTER___POR 0x0 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_U__SLOPE_MODE___POR 0x0 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_U__RESET_SLOPE___POR 0x0 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_U__ENABLE_PPM_RESCUE___M 0x01000000 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_U__ENABLE_PPM_RESCUE___S 24 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_U__ENABLE_OFFSET_FILTER___M 0x00010000 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_U__ENABLE_OFFSET_FILTER___S 16 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_U__SLOPE_MODE___M 0x00000300 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_U__SLOPE_MODE___S 8 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_U__RESET_SLOPE___M 0x00000001 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_U__RESET_SLOPE___S 0 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_U___M 0x01010301 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_1_U___S 0 + +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_L (0x005005F0) +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_L___POR 0x00000300 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_L__RESET_DATA_COUNT___POR 0x0 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_L__USE_CORDIC_HT___POR 0x0 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_L__PMAG_CORR_FILTER_SHIFT___POR 0x3 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_L__EN_SCALEUP_3DB___POR 0x0 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_L__RESET_DATA_COUNT___M 0x01000000 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_L__RESET_DATA_COUNT___S 24 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_L__USE_CORDIC_HT___M 0x00010000 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_L__USE_CORDIC_HT___S 16 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_L__PMAG_CORR_FILTER_SHIFT___M 0x00000300 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_L__PMAG_CORR_FILTER_SHIFT___S 8 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_L__EN_SCALEUP_3DB___M 0x00000001 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_L__EN_SCALEUP_3DB___S 0 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_L___M 0x01010301 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_L___S 0 + +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_U (0x005005F4) +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_U__PILOT_ROTATE_EN___POR 0x0 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_U__DLTF_SYMBOL___POR 0x0 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_U__PILOT_1SS___POR 0x0 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_U__PILOT_ROTATE_EN___M 0x00010000 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_U__PILOT_ROTATE_EN___S 16 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_U__DLTF_SYMBOL___M 0x00000100 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_U__DLTF_SYMBOL___S 8 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_U__PILOT_1SS___M 0x00000001 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_U__PILOT_1SS___S 0 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_U___M 0x00010101 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_2_U___S 0 + +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_L (0x005005F8) +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_L__CFO_CORR_SCALE_FRAC_SEL___POR 0x0 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_L__RESET_MAG_TRACK___POR 0x0 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_L__MRC_OFFSET_VHTDLTF_CORR___POR 0x000 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_L__CFO_CORR_SCALE_FRAC_SEL___M 0x01000000 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_L__CFO_CORR_SCALE_FRAC_SEL___S 24 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_L__RESET_MAG_TRACK___M 0x00010000 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_L__RESET_MAG_TRACK___S 16 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_L__MRC_OFFSET_VHTDLTF_CORR___M 0x000003FF +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_L__MRC_OFFSET_VHTDLTF_CORR___S 0 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_L___M 0x010103FF +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_L___S 0 + +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_U (0x005005FC) +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_U__ENABLE_MAGNITUDE_TRACK___POR 0x0 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_U__SEC_SEGMENT___POR 0x0 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_U__CFO_CORR_SCALE_FRAC_BW___POR 0x000 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_U__ENABLE_MAGNITUDE_TRACK___M 0x01000000 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_U__ENABLE_MAGNITUDE_TRACK___S 24 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_U__SEC_SEGMENT___M 0x00010000 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_U__SEC_SEGMENT___S 16 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_U__CFO_CORR_SCALE_FRAC_BW___M 0x000003FF +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_U__CFO_CORR_SCALE_FRAC_BW___S 0 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_U___M 0x010103FF +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_3_U___S 0 + +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_L (0x00500600) +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_L__COMPARE_REF___POR 0x0 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_L__COMPUTE_REF___POR 0x0 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_L__TIMING_BACKOFF___POR 0x00 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_L__ENABLE_LIN_EVM___POR 0x0 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_L__COMPARE_REF___M 0x01000000 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_L__COMPARE_REF___S 24 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_L__COMPUTE_REF___M 0x00010000 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_L__COMPUTE_REF___S 16 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_L__TIMING_BACKOFF___M 0x00001F00 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_L__TIMING_BACKOFF___S 8 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_L__ENABLE_LIN_EVM___M 0x00000001 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_L__ENABLE_LIN_EVM___S 0 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_L___M 0x01011F01 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_L___S 0 + +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_U (0x00500604) +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_U__DEMF_SYMBOL_CNT___POR 0x00000000 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_U__DEMF_SYMBOL_CNT___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_U__DEMF_SYMBOL_CNT___S 0 +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_PTC_PTC_CONTROL_4_U___S 0 + +#define PHYA_DEMFRONT_1_USER_SPARE_2_L (0x00500608) +#define PHYA_DEMFRONT_1_USER_SPARE_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_USER_SPARE_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_USER_SPARE_2_L__NEXT_DESC_WR_PTC_SPARE_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_USER_SPARE_2_L__NEXT_DESC_WR_PTC_SPARE_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_USER_SPARE_2_L__NEXT_DESC_WR_PTC_SPARE_0___S 0 +#define PHYA_DEMFRONT_1_USER_SPARE_2_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_USER_SPARE_2_L___S 0 + +#define PHYA_DEMFRONT_1_USER_SPARE_2_U (0x0050060C) +#define PHYA_DEMFRONT_1_USER_SPARE_2_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_USER_SPARE_2_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_USER_SPARE_2_U__NEXT_DESC_WR_PTC_SPARE_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_USER_SPARE_2_U__NEXT_DESC_WR_PTC_SPARE_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_USER_SPARE_2_U__NEXT_DESC_WR_PTC_SPARE_1___S 0 +#define PHYA_DEMFRONT_1_USER_SPARE_2_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_USER_SPARE_2_U___S 0 + +#define PHYA_DEMFRONT_1_DCN_CONTROL_L (0x00500610) +#define PHYA_DEMFRONT_1_DCN_CONTROL_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_DCN_CONTROL_L___POR 0x00000100 +#define PHYA_DEMFRONT_1_DCN_CONTROL_L__DCN_STRIDE_MODE___POR 0x0 +#define PHYA_DEMFRONT_1_DCN_CONTROL_L__DCN_MIRROR_EN_SEG1___POR 0x1 +#define PHYA_DEMFRONT_1_DCN_CONTROL_L__DCN_MIRROR_EN_SEG0___POR 0x0 +#define PHYA_DEMFRONT_1_DCN_CONTROL_L__DCN_STRIDE_MODE___M 0x00030000 +#define PHYA_DEMFRONT_1_DCN_CONTROL_L__DCN_STRIDE_MODE___S 16 +#define PHYA_DEMFRONT_1_DCN_CONTROL_L__DCN_MIRROR_EN_SEG1___M 0x00000100 +#define PHYA_DEMFRONT_1_DCN_CONTROL_L__DCN_MIRROR_EN_SEG1___S 8 +#define PHYA_DEMFRONT_1_DCN_CONTROL_L__DCN_MIRROR_EN_SEG0___M 0x00000001 +#define PHYA_DEMFRONT_1_DCN_CONTROL_L__DCN_MIRROR_EN_SEG0___S 0 +#define PHYA_DEMFRONT_1_DCN_CONTROL_L___M 0x00030101 +#define PHYA_DEMFRONT_1_DCN_CONTROL_L___S 0 + +#define PHYA_DEMFRONT_1_SYM_FDPP_CONTROL_L (0x00500618) +#define PHYA_DEMFRONT_1_SYM_FDPP_CONTROL_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SYM_FDPP_CONTROL_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SYM_FDPP_CONTROL_L__ENABLE_DC_NOTCH_COMP___POR 0x0 +#define PHYA_DEMFRONT_1_SYM_FDPP_CONTROL_L__ENABLE_GAIN_RATIO___POR 0x0 +#define PHYA_DEMFRONT_1_SYM_FDPP_CONTROL_L__ENABLE_DC_NOTCH_COMP___M 0x00000100 +#define PHYA_DEMFRONT_1_SYM_FDPP_CONTROL_L__ENABLE_DC_NOTCH_COMP___S 8 +#define PHYA_DEMFRONT_1_SYM_FDPP_CONTROL_L__ENABLE_GAIN_RATIO___M 0x00000001 +#define PHYA_DEMFRONT_1_SYM_FDPP_CONTROL_L__ENABLE_GAIN_RATIO___S 0 +#define PHYA_DEMFRONT_1_SYM_FDPP_CONTROL_L___M 0x00000101 +#define PHYA_DEMFRONT_1_SYM_FDPP_CONTROL_L___S 0 + +#define PHYA_DEMFRONT_1_SYM_QRE_CONTROL_L (0x00500620) +#define PHYA_DEMFRONT_1_SYM_QRE_CONTROL_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SYM_QRE_CONTROL_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SYM_QRE_CONTROL_L__QRE_CHAIN_MASK___POR 0x00 +#define PHYA_DEMFRONT_1_SYM_QRE_CONTROL_L__QRE_CHAIN_MASK___M 0x000000FF +#define PHYA_DEMFRONT_1_SYM_QRE_CONTROL_L__QRE_CHAIN_MASK___S 0 +#define PHYA_DEMFRONT_1_SYM_QRE_CONTROL_L___M 0x000000FF +#define PHYA_DEMFRONT_1_SYM_QRE_CONTROL_L___S 0 + +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_0_L (0x00500628) +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_0_L___POR 0x0FFFFFFF +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_0_L__NEXT_DESC_PROG_THR___POR 0xFFF +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_0_L__SYM_PROC_THR___POR 0xFFFF +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_0_L__NEXT_DESC_PROG_THR___M 0x0FFF0000 +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_0_L__NEXT_DESC_PROG_THR___S 16 +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_0_L__SYM_PROC_THR___M 0x0000FFFF +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_0_L__SYM_PROC_THR___S 0 +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_0_L___M 0x0FFFFFFF +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_0_L___S 0 + +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_1_L (0x00500630) +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_1_L__ERROR_STATE_MASK_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_1_L__ERROR_STATE_MASK_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_1_L__ERROR_STATE_MASK_0___S 0 +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_1_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_1_L___S 0 + +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_1_U (0x00500634) +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_1_U__ERROR_STATE_MASK_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_1_U__ERROR_STATE_MASK_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_1_U__ERROR_STATE_MASK_1___S 0 +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_1_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_1_U___S 0 + +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_L (0x00500638) +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_L__EN_RAW_CV_DUMP___POR 0x0 +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_L__RAW_FFT_DUMP_MEM_SEL___POR 0x0 +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_L__RAW_FFT_DUMP_ADR_OFFSET___POR 0x0000 +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_L__EN_RAW_CV_DUMP___M 0x01000000 +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_L__EN_RAW_CV_DUMP___S 24 +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_L__RAW_FFT_DUMP_MEM_SEL___M 0x00010000 +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_L__RAW_FFT_DUMP_MEM_SEL___S 16 +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_L__RAW_FFT_DUMP_ADR_OFFSET___M 0x0000FFFF +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_L__RAW_FFT_DUMP_ADR_OFFSET___S 0 +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_L___M 0x0101FFFF +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_L___S 0 + +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_U (0x0050063C) +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE2___POR 0x00 +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE1___POR 0x00 +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE0___POR 0x00 +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_U__EN_PHYDBG___POR 0x0 +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE2___M 0xFF000000 +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE2___S 24 +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE1___M 0x00FF0000 +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE1___S 16 +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE0___M 0x0000FF00 +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_U__NEXT_DESC_WR_SPARE0___S 8 +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_U__EN_PHYDBG___M 0x00000001 +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_U__EN_PHYDBG___S 0 +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_U___M 0xFFFFFF01 +#define PHYA_DEMFRONT_1_SYM_DEBUG_CONTROL_2_U___S 0 + +#define PHYA_DEMFRONT_1_RXTD_GAIN_RATIO0_L (0x00500640) +#define PHYA_DEMFRONT_1_RXTD_GAIN_RATIO0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RXTD_GAIN_RATIO0_L___POR 0x00000080 +#define PHYA_DEMFRONT_1_RXTD_GAIN_RATIO0_L__TOTAL_GAIN_0___POR 0x000 +#define PHYA_DEMFRONT_1_RXTD_GAIN_RATIO0_L__GAIN_RATIO_SQ_0___POR 0x00 +#define PHYA_DEMFRONT_1_RXTD_GAIN_RATIO0_L__FDPP_GAIN_RATIO_0___POR 0x80 +#define PHYA_DEMFRONT_1_RXTD_GAIN_RATIO0_L__TOTAL_GAIN_0___M 0x03FF0000 +#define PHYA_DEMFRONT_1_RXTD_GAIN_RATIO0_L__TOTAL_GAIN_0___S 16 +#define PHYA_DEMFRONT_1_RXTD_GAIN_RATIO0_L__GAIN_RATIO_SQ_0___M 0x0000FF00 +#define PHYA_DEMFRONT_1_RXTD_GAIN_RATIO0_L__GAIN_RATIO_SQ_0___S 8 +#define PHYA_DEMFRONT_1_RXTD_GAIN_RATIO0_L__FDPP_GAIN_RATIO_0___M 0x000000FF +#define PHYA_DEMFRONT_1_RXTD_GAIN_RATIO0_L__FDPP_GAIN_RATIO_0___S 0 +#define PHYA_DEMFRONT_1_RXTD_GAIN_RATIO0_L___M 0x03FFFFFF +#define PHYA_DEMFRONT_1_RXTD_GAIN_RATIO0_L___S 0 + +#define PHYA_DEMFRONT_1_RXTD_GAIN_RATIO1_L (0x00500648) +#define PHYA_DEMFRONT_1_RXTD_GAIN_RATIO1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_RXTD_GAIN_RATIO1_L___POR 0x00000080 +#define PHYA_DEMFRONT_1_RXTD_GAIN_RATIO1_L__TOTAL_GAIN_1___POR 0x000 +#define PHYA_DEMFRONT_1_RXTD_GAIN_RATIO1_L__GAIN_RATIO_SQ_1___POR 0x00 +#define PHYA_DEMFRONT_1_RXTD_GAIN_RATIO1_L__FDPP_GAIN_RATIO_1___POR 0x80 +#define PHYA_DEMFRONT_1_RXTD_GAIN_RATIO1_L__TOTAL_GAIN_1___M 0x03FF0000 +#define PHYA_DEMFRONT_1_RXTD_GAIN_RATIO1_L__TOTAL_GAIN_1___S 16 +#define PHYA_DEMFRONT_1_RXTD_GAIN_RATIO1_L__GAIN_RATIO_SQ_1___M 0x0000FF00 +#define PHYA_DEMFRONT_1_RXTD_GAIN_RATIO1_L__GAIN_RATIO_SQ_1___S 8 +#define PHYA_DEMFRONT_1_RXTD_GAIN_RATIO1_L__FDPP_GAIN_RATIO_1___M 0x000000FF +#define PHYA_DEMFRONT_1_RXTD_GAIN_RATIO1_L__FDPP_GAIN_RATIO_1___S 0 +#define PHYA_DEMFRONT_1_RXTD_GAIN_RATIO1_L___M 0x03FFFFFF +#define PHYA_DEMFRONT_1_RXTD_GAIN_RATIO1_L___S 0 + +#define PHYA_DEMFRONT_1_NOISE_PWR_0_L (0x00500660) +#define PHYA_DEMFRONT_1_NOISE_PWR_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_NOISE_PWR_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_NOISE_PWR_0_L__FRAME_END___POR 0x0 +#define PHYA_DEMFRONT_1_NOISE_PWR_0_L__RESTART___POR 0x0 +#define PHYA_DEMFRONT_1_NOISE_PWR_0_L__FRAME_DETECT___POR 0x0 +#define PHYA_DEMFRONT_1_NOISE_PWR_0_L__FRAME_END___M 0x00010000 +#define PHYA_DEMFRONT_1_NOISE_PWR_0_L__FRAME_END___S 16 +#define PHYA_DEMFRONT_1_NOISE_PWR_0_L__RESTART___M 0x00000100 +#define PHYA_DEMFRONT_1_NOISE_PWR_0_L__RESTART___S 8 +#define PHYA_DEMFRONT_1_NOISE_PWR_0_L__FRAME_DETECT___M 0x00000001 +#define PHYA_DEMFRONT_1_NOISE_PWR_0_L__FRAME_DETECT___S 0 +#define PHYA_DEMFRONT_1_NOISE_PWR_0_L___M 0x00010101 +#define PHYA_DEMFRONT_1_NOISE_PWR_0_L___S 0 + +#define PHYA_DEMFRONT_1_NOISE_PWR_0_U (0x00500664) +#define PHYA_DEMFRONT_1_NOISE_PWR_0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_NOISE_PWR_0_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_NOISE_PWR_0_U__BTCF_TIMING_EST_RESULT___POR 0x0000 +#define PHYA_DEMFRONT_1_NOISE_PWR_0_U__SYM_COUNT___POR 0x000 +#define PHYA_DEMFRONT_1_NOISE_PWR_0_U__BTCF_TIMING_EST_RESULT___M 0xFFFF0000 +#define PHYA_DEMFRONT_1_NOISE_PWR_0_U__BTCF_TIMING_EST_RESULT___S 16 +#define PHYA_DEMFRONT_1_NOISE_PWR_0_U__SYM_COUNT___M 0x000003FF +#define PHYA_DEMFRONT_1_NOISE_PWR_0_U__SYM_COUNT___S 0 +#define PHYA_DEMFRONT_1_NOISE_PWR_0_U___M 0xFFFF03FF +#define PHYA_DEMFRONT_1_NOISE_PWR_0_U___S 0 + +#define PHYA_DEMFRONT_1_NOISE_PWR_1_L (0x00500668) +#define PHYA_DEMFRONT_1_NOISE_PWR_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_NOISE_PWR_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_NOISE_PWR_1_L__COARSE_CFO_EST_RESULT___POR 0x0000 +#define PHYA_DEMFRONT_1_NOISE_PWR_1_L__BTCF_FINE_CFO_EST_RESULT___POR 0x0000 +#define PHYA_DEMFRONT_1_NOISE_PWR_1_L__COARSE_CFO_EST_RESULT___M 0xFFFF0000 +#define PHYA_DEMFRONT_1_NOISE_PWR_1_L__COARSE_CFO_EST_RESULT___S 16 +#define PHYA_DEMFRONT_1_NOISE_PWR_1_L__BTCF_FINE_CFO_EST_RESULT___M 0x0000FFFF +#define PHYA_DEMFRONT_1_NOISE_PWR_1_L__BTCF_FINE_CFO_EST_RESULT___S 0 +#define PHYA_DEMFRONT_1_NOISE_PWR_1_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_NOISE_PWR_1_L___S 0 + +#define PHYA_DEMFRONT_1_NOISE_PWR_1_U (0x0050066C) +#define PHYA_DEMFRONT_1_NOISE_PWR_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_NOISE_PWR_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_NOISE_PWR_1_U__NOISE_PWR_SQRT_EXP___POR 0x0 +#define PHYA_DEMFRONT_1_NOISE_PWR_1_U__NOISE_PWR_SQRT_MAN___POR 0x00 +#define PHYA_DEMFRONT_1_NOISE_PWR_1_U__SNR_EST_MMSE_IS___POR 0x00 +#define PHYA_DEMFRONT_1_NOISE_PWR_1_U__VSRC_DEPTH___POR 0x00 +#define PHYA_DEMFRONT_1_NOISE_PWR_1_U__NOISE_PWR_SQRT_EXP___M 0x0F000000 +#define PHYA_DEMFRONT_1_NOISE_PWR_1_U__NOISE_PWR_SQRT_EXP___S 24 +#define PHYA_DEMFRONT_1_NOISE_PWR_1_U__NOISE_PWR_SQRT_MAN___M 0x003F0000 +#define PHYA_DEMFRONT_1_NOISE_PWR_1_U__NOISE_PWR_SQRT_MAN___S 16 +#define PHYA_DEMFRONT_1_NOISE_PWR_1_U__SNR_EST_MMSE_IS___M 0x00003F00 +#define PHYA_DEMFRONT_1_NOISE_PWR_1_U__SNR_EST_MMSE_IS___S 8 +#define PHYA_DEMFRONT_1_NOISE_PWR_1_U__VSRC_DEPTH___M 0x000000FF +#define PHYA_DEMFRONT_1_NOISE_PWR_1_U__VSRC_DEPTH___S 0 +#define PHYA_DEMFRONT_1_NOISE_PWR_1_U___M 0x0F3F3FFF +#define PHYA_DEMFRONT_1_NOISE_PWR_1_U___S 0 + +#define PHYA_DEMFRONT_1_USER_SPARE_3_L (0x00500670) +#define PHYA_DEMFRONT_1_USER_SPARE_3_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_USER_SPARE_3_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_USER_SPARE_3_L__RXTD_NOISEPWR_BTCF_WR_SPARE_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_USER_SPARE_3_L__RXTD_NOISEPWR_BTCF_WR_SPARE_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_USER_SPARE_3_L__RXTD_NOISEPWR_BTCF_WR_SPARE_0___S 0 +#define PHYA_DEMFRONT_1_USER_SPARE_3_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_USER_SPARE_3_L___S 0 + +#define PHYA_DEMFRONT_1_USER_SPARE_3_U (0x00500674) +#define PHYA_DEMFRONT_1_USER_SPARE_3_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_USER_SPARE_3_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_USER_SPARE_3_U__RXTD_NOISEPWR_BTCF_WR_SPARE_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_USER_SPARE_3_U__RXTD_NOISEPWR_BTCF_WR_SPARE_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_USER_SPARE_3_U__RXTD_NOISEPWR_BTCF_WR_SPARE_1___S 0 +#define PHYA_DEMFRONT_1_USER_SPARE_3_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_USER_SPARE_3_U___S 0 + +#define PHYA_DEMFRONT_1_SCSR_CHE0_L (0x00500678) +#define PHYA_DEMFRONT_1_SCSR_CHE0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_CHE0_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SCSR_CHE0_L__CSD_VALUE_0___POR 0x000 +#define PHYA_DEMFRONT_1_SCSR_CHE0_L__CSD_VALUE_0___M 0x000001FF +#define PHYA_DEMFRONT_1_SCSR_CHE0_L__CSD_VALUE_0___S 0 +#define PHYA_DEMFRONT_1_SCSR_CHE0_L___M 0x000001FF +#define PHYA_DEMFRONT_1_SCSR_CHE0_L___S 0 + +#define PHYA_DEMFRONT_1_SCSR_CHE1_L (0x00500680) +#define PHYA_DEMFRONT_1_SCSR_CHE1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_CHE1_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SCSR_CHE1_L__CSD_VALUE_1___POR 0x000 +#define PHYA_DEMFRONT_1_SCSR_CHE1_L__CSD_VALUE_1___M 0x000001FF +#define PHYA_DEMFRONT_1_SCSR_CHE1_L__CSD_VALUE_1___S 0 +#define PHYA_DEMFRONT_1_SCSR_CHE1_L___M 0x000001FF +#define PHYA_DEMFRONT_1_SCSR_CHE1_L___S 0 + +#define PHYA_DEMFRONT_1_SCSR_CHE2_L (0x00500688) +#define PHYA_DEMFRONT_1_SCSR_CHE2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_CHE2_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SCSR_CHE2_L__CSD_VALUE_2___POR 0x000 +#define PHYA_DEMFRONT_1_SCSR_CHE2_L__CSD_VALUE_2___M 0x000001FF +#define PHYA_DEMFRONT_1_SCSR_CHE2_L__CSD_VALUE_2___S 0 +#define PHYA_DEMFRONT_1_SCSR_CHE2_L___M 0x000001FF +#define PHYA_DEMFRONT_1_SCSR_CHE2_L___S 0 + +#define PHYA_DEMFRONT_1_SCSR_CHE3_L (0x00500690) +#define PHYA_DEMFRONT_1_SCSR_CHE3_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_CHE3_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SCSR_CHE3_L__CSD_VALUE_3___POR 0x000 +#define PHYA_DEMFRONT_1_SCSR_CHE3_L__CSD_VALUE_3___M 0x000001FF +#define PHYA_DEMFRONT_1_SCSR_CHE3_L__CSD_VALUE_3___S 0 +#define PHYA_DEMFRONT_1_SCSR_CHE3_L___M 0x000001FF +#define PHYA_DEMFRONT_1_SCSR_CHE3_L___S 0 + +#define PHYA_DEMFRONT_1_SCSR_CHE4_L (0x00500698) +#define PHYA_DEMFRONT_1_SCSR_CHE4_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_CHE4_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SCSR_CHE4_L__CSD_VALUE_4___POR 0x000 +#define PHYA_DEMFRONT_1_SCSR_CHE4_L__CSD_VALUE_4___M 0x000001FF +#define PHYA_DEMFRONT_1_SCSR_CHE4_L__CSD_VALUE_4___S 0 +#define PHYA_DEMFRONT_1_SCSR_CHE4_L___M 0x000001FF +#define PHYA_DEMFRONT_1_SCSR_CHE4_L___S 0 + +#define PHYA_DEMFRONT_1_SCSR_CHE5_L (0x005006A0) +#define PHYA_DEMFRONT_1_SCSR_CHE5_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_CHE5_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SCSR_CHE5_L__CSD_VALUE_5___POR 0x000 +#define PHYA_DEMFRONT_1_SCSR_CHE5_L__CSD_VALUE_5___M 0x000001FF +#define PHYA_DEMFRONT_1_SCSR_CHE5_L__CSD_VALUE_5___S 0 +#define PHYA_DEMFRONT_1_SCSR_CHE5_L___M 0x000001FF +#define PHYA_DEMFRONT_1_SCSR_CHE5_L___S 0 + +#define PHYA_DEMFRONT_1_SCSR_CHE6_L (0x005006A8) +#define PHYA_DEMFRONT_1_SCSR_CHE6_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_CHE6_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SCSR_CHE6_L__CSD_VALUE_6___POR 0x000 +#define PHYA_DEMFRONT_1_SCSR_CHE6_L__CSD_VALUE_6___M 0x000001FF +#define PHYA_DEMFRONT_1_SCSR_CHE6_L__CSD_VALUE_6___S 0 +#define PHYA_DEMFRONT_1_SCSR_CHE6_L___M 0x000001FF +#define PHYA_DEMFRONT_1_SCSR_CHE6_L___S 0 + +#define PHYA_DEMFRONT_1_SCSR_CHE7_L (0x005006B0) +#define PHYA_DEMFRONT_1_SCSR_CHE7_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_CHE7_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SCSR_CHE7_L__CSD_VALUE_7___POR 0x000 +#define PHYA_DEMFRONT_1_SCSR_CHE7_L__CSD_VALUE_7___M 0x000001FF +#define PHYA_DEMFRONT_1_SCSR_CHE7_L__CSD_VALUE_7___S 0 +#define PHYA_DEMFRONT_1_SCSR_CHE7_L___M 0x000001FF +#define PHYA_DEMFRONT_1_SCSR_CHE7_L___S 0 + +#define PHYA_DEMFRONT_1_SCSR_LLR_0_L (0x005006B8) +#define PHYA_DEMFRONT_1_SCSR_LLR_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_LLR_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SCSR_LLR_0_L__QAM4096_LLR_INV___POR 0x0 +#define PHYA_DEMFRONT_1_SCSR_LLR_0_L__QAM4096_LLR_INV___M 0x00000001 +#define PHYA_DEMFRONT_1_SCSR_LLR_0_L__QAM4096_LLR_INV___S 0 +#define PHYA_DEMFRONT_1_SCSR_LLR_0_L___M 0x00000001 +#define PHYA_DEMFRONT_1_SCSR_LLR_0_L___S 0 + +#define PHYA_DEMFRONT_1_SCSR_LLR_1_L (0x005006C0) +#define PHYA_DEMFRONT_1_SCSR_LLR_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_LLR_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SCSR_LLR_1_L__QAM4096_LLR_ORDER___POR 0x0 +#define PHYA_DEMFRONT_1_SCSR_LLR_1_L__QAM4096_LLR_ORDER___M 0x00000001 +#define PHYA_DEMFRONT_1_SCSR_LLR_1_L__QAM4096_LLR_ORDER___S 0 +#define PHYA_DEMFRONT_1_SCSR_LLR_1_L___M 0x00000001 +#define PHYA_DEMFRONT_1_SCSR_LLR_1_L___S 0 + +#define PHYA_DEMFRONT_1_SCSR_LLR_2_L (0x005006C8) +#define PHYA_DEMFRONT_1_SCSR_LLR_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_LLR_2_L___POR 0x00007F01 +#define PHYA_DEMFRONT_1_SCSR_LLR_2_L__PILOT_POLARITY_SEQ___POR 0x7F +#define PHYA_DEMFRONT_1_SCSR_LLR_2_L__EN_SEG_DUPLICATE_WR___POR 0x1 +#define PHYA_DEMFRONT_1_SCSR_LLR_2_L__PILOT_POLARITY_SEQ___M 0x0000FF00 +#define PHYA_DEMFRONT_1_SCSR_LLR_2_L__PILOT_POLARITY_SEQ___S 8 +#define PHYA_DEMFRONT_1_SCSR_LLR_2_L__EN_SEG_DUPLICATE_WR___M 0x00000001 +#define PHYA_DEMFRONT_1_SCSR_LLR_2_L__EN_SEG_DUPLICATE_WR___S 0 +#define PHYA_DEMFRONT_1_SCSR_LLR_2_L___M 0x0000FF01 +#define PHYA_DEMFRONT_1_SCSR_LLR_2_L___S 0 + +#define PHYA_DEMFRONT_1_SCSR_DLMU_L (0x005006D0) +#define PHYA_DEMFRONT_1_SCSR_DLMU_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_DLMU_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SCSR_DLMU_L__DLMU_SS_OFFSET___POR 0x0 +#define PHYA_DEMFRONT_1_SCSR_DLMU_L__DLMU_NSS_TOTAL___POR 0x0 +#define PHYA_DEMFRONT_1_SCSR_DLMU_L__DLMU_NSS_USER___POR 0x0 +#define PHYA_DEMFRONT_1_SCSR_DLMU_L__DLMU_USER_ID___POR 0x00 +#define PHYA_DEMFRONT_1_SCSR_DLMU_L__DLMU_SS_OFFSET___M 0x07000000 +#define PHYA_DEMFRONT_1_SCSR_DLMU_L__DLMU_SS_OFFSET___S 24 +#define PHYA_DEMFRONT_1_SCSR_DLMU_L__DLMU_NSS_TOTAL___M 0x000F0000 +#define PHYA_DEMFRONT_1_SCSR_DLMU_L__DLMU_NSS_TOTAL___S 16 +#define PHYA_DEMFRONT_1_SCSR_DLMU_L__DLMU_NSS_USER___M 0x00000F00 +#define PHYA_DEMFRONT_1_SCSR_DLMU_L__DLMU_NSS_USER___S 8 +#define PHYA_DEMFRONT_1_SCSR_DLMU_L__DLMU_USER_ID___M 0x0000003F +#define PHYA_DEMFRONT_1_SCSR_DLMU_L__DLMU_USER_ID___S 0 +#define PHYA_DEMFRONT_1_SCSR_DLMU_L___M 0x070F0F3F +#define PHYA_DEMFRONT_1_SCSR_DLMU_L___S 0 + +#define PHYA_DEMFRONT_1_SCSR_DLMU_U (0x005006D4) +#define PHYA_DEMFRONT_1_SCSR_DLMU_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_DLMU_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_SCSR_DLMU_U__CBF_DISABLE_TXBF___POR 0x0 +#define PHYA_DEMFRONT_1_SCSR_DLMU_U__DLMU_LDPC_LLR_SCALE___POR 0x0 +#define PHYA_DEMFRONT_1_SCSR_DLMU_U__DLMU_IS_QAM___POR 0x0 +#define PHYA_DEMFRONT_1_SCSR_DLMU_U__DLMU_IS_LDPC___POR 0x0 +#define PHYA_DEMFRONT_1_SCSR_DLMU_U__CBF_DISABLE_TXBF___M 0x03000000 +#define PHYA_DEMFRONT_1_SCSR_DLMU_U__CBF_DISABLE_TXBF___S 24 +#define PHYA_DEMFRONT_1_SCSR_DLMU_U__DLMU_LDPC_LLR_SCALE___M 0x00070000 +#define PHYA_DEMFRONT_1_SCSR_DLMU_U__DLMU_LDPC_LLR_SCALE___S 16 +#define PHYA_DEMFRONT_1_SCSR_DLMU_U__DLMU_IS_QAM___M 0x00000700 +#define PHYA_DEMFRONT_1_SCSR_DLMU_U__DLMU_IS_QAM___S 8 +#define PHYA_DEMFRONT_1_SCSR_DLMU_U__DLMU_IS_LDPC___M 0x00000001 +#define PHYA_DEMFRONT_1_SCSR_DLMU_U__DLMU_IS_LDPC___S 0 +#define PHYA_DEMFRONT_1_SCSR_DLMU_U___M 0x03070701 +#define PHYA_DEMFRONT_1_SCSR_DLMU_U___S 0 + +#define PHYA_DEMFRONT_1_CBFG_CFG_0_L (0x005006D8) +#define PHYA_DEMFRONT_1_CBFG_CFG_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CBFG_CFG_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_CBFG_CFG_0_L__CBF_NG___POR 0x0 +#define PHYA_DEMFRONT_1_CBFG_CFG_0_L__CBF_PKB___POR 0x0 +#define PHYA_DEMFRONT_1_CBFG_CFG_0_L__CBF_PKT___POR 0x0 +#define PHYA_DEMFRONT_1_CBFG_CFG_0_L__CBF_CVMEM_SEL___POR 0x0 +#define PHYA_DEMFRONT_1_CBFG_CFG_0_L__CBF_NG___M 0x07000000 +#define PHYA_DEMFRONT_1_CBFG_CFG_0_L__CBF_NG___S 24 +#define PHYA_DEMFRONT_1_CBFG_CFG_0_L__CBF_PKB___M 0x00030000 +#define PHYA_DEMFRONT_1_CBFG_CFG_0_L__CBF_PKB___S 16 +#define PHYA_DEMFRONT_1_CBFG_CFG_0_L__CBF_PKT___M 0x00000300 +#define PHYA_DEMFRONT_1_CBFG_CFG_0_L__CBF_PKT___S 8 +#define PHYA_DEMFRONT_1_CBFG_CFG_0_L__CBF_CVMEM_SEL___M 0x00000001 +#define PHYA_DEMFRONT_1_CBFG_CFG_0_L__CBF_CVMEM_SEL___S 0 +#define PHYA_DEMFRONT_1_CBFG_CFG_0_L___M 0x07030301 +#define PHYA_DEMFRONT_1_CBFG_CFG_0_L___S 0 + +#define PHYA_DEMFRONT_1_CBFG_CFG_0_U (0x005006DC) +#define PHYA_DEMFRONT_1_CBFG_CFG_0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CBFG_CFG_0_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_CBFG_CFG_0_U__CBF_NC___POR 0x0 +#define PHYA_DEMFRONT_1_CBFG_CFG_0_U__CBF_NR___POR 0x0 +#define PHYA_DEMFRONT_1_CBFG_CFG_0_U__CBF_MU___POR 0x0 +#define PHYA_DEMFRONT_1_CBFG_CFG_0_U__CBF_CB___POR 0x0 +#define PHYA_DEMFRONT_1_CBFG_CFG_0_U__CBF_NC___M 0x07000000 +#define PHYA_DEMFRONT_1_CBFG_CFG_0_U__CBF_NC___S 24 +#define PHYA_DEMFRONT_1_CBFG_CFG_0_U__CBF_NR___M 0x00070000 +#define PHYA_DEMFRONT_1_CBFG_CFG_0_U__CBF_NR___S 16 +#define PHYA_DEMFRONT_1_CBFG_CFG_0_U__CBF_MU___M 0x00000100 +#define PHYA_DEMFRONT_1_CBFG_CFG_0_U__CBF_MU___S 8 +#define PHYA_DEMFRONT_1_CBFG_CFG_0_U__CBF_CB___M 0x00000001 +#define PHYA_DEMFRONT_1_CBFG_CFG_0_U__CBF_CB___S 0 +#define PHYA_DEMFRONT_1_CBFG_CFG_0_U___M 0x07070101 +#define PHYA_DEMFRONT_1_CBFG_CFG_0_U___S 0 + +#define PHYA_DEMFRONT_1_CBFG_CFG_1_L (0x005006E0) +#define PHYA_DEMFRONT_1_CBFG_CFG_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CBFG_CFG_1_L___POR 0x000A0000 +#define PHYA_DEMFRONT_1_CBFG_CFG_1_L__CBF_MAX_STREAM_SNR_CAP___POR 0x00 +#define PHYA_DEMFRONT_1_CBFG_CFG_1_L__CBF_SNR_RX1_BIAS___POR 0xA +#define PHYA_DEMFRONT_1_CBFG_CFG_1_L__CBF_RU_NUM___POR 0x00 +#define PHYA_DEMFRONT_1_CBFG_CFG_1_L__CBF_START_RU_IDX___POR 0x00 +#define PHYA_DEMFRONT_1_CBFG_CFG_1_L__CBF_MAX_STREAM_SNR_CAP___M 0x3F000000 +#define PHYA_DEMFRONT_1_CBFG_CFG_1_L__CBF_MAX_STREAM_SNR_CAP___S 24 +#define PHYA_DEMFRONT_1_CBFG_CFG_1_L__CBF_SNR_RX1_BIAS___M 0x000F0000 +#define PHYA_DEMFRONT_1_CBFG_CFG_1_L__CBF_SNR_RX1_BIAS___S 16 +#define PHYA_DEMFRONT_1_CBFG_CFG_1_L__CBF_RU_NUM___M 0x00003F00 +#define PHYA_DEMFRONT_1_CBFG_CFG_1_L__CBF_RU_NUM___S 8 +#define PHYA_DEMFRONT_1_CBFG_CFG_1_L__CBF_START_RU_IDX___M 0x0000003F +#define PHYA_DEMFRONT_1_CBFG_CFG_1_L__CBF_START_RU_IDX___S 0 +#define PHYA_DEMFRONT_1_CBFG_CFG_1_L___M 0x3F0F3F3F +#define PHYA_DEMFRONT_1_CBFG_CFG_1_L___S 0 + +#define PHYA_DEMFRONT_1_CBFG_CFG_1_U (0x005006E4) +#define PHYA_DEMFRONT_1_CBFG_CFG_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CBFG_CFG_1_U___POR 0x000C0000 +#define PHYA_DEMFRONT_1_CBFG_CFG_1_U__CBF_CNP_CTRL___POR 0x0C +#define PHYA_DEMFRONT_1_CBFG_CFG_1_U__CBF_INTER_CV_DSNR___POR 0x00 +#define PHYA_DEMFRONT_1_CBFG_CFG_1_U__CBF_INTER_ASNR_CV___POR 0x00 +#define PHYA_DEMFRONT_1_CBFG_CFG_1_U__CBF_CNP_CTRL___M 0x00FF0000 +#define PHYA_DEMFRONT_1_CBFG_CFG_1_U__CBF_CNP_CTRL___S 16 +#define PHYA_DEMFRONT_1_CBFG_CFG_1_U__CBF_INTER_CV_DSNR___M 0x0000FF00 +#define PHYA_DEMFRONT_1_CBFG_CFG_1_U__CBF_INTER_CV_DSNR___S 8 +#define PHYA_DEMFRONT_1_CBFG_CFG_1_U__CBF_INTER_ASNR_CV___M 0x000000FF +#define PHYA_DEMFRONT_1_CBFG_CFG_1_U__CBF_INTER_ASNR_CV___S 0 +#define PHYA_DEMFRONT_1_CBFG_CFG_1_U___M 0x00FFFFFF +#define PHYA_DEMFRONT_1_CBFG_CFG_1_U___S 0 + +#define PHYA_DEMFRONT_1_CBFG_CFG_2_L (0x005006E8) +#define PHYA_DEMFRONT_1_CBFG_CFG_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CBFG_CFG_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_CBFG_CFG_2_L__CBF_SNR_BIAS_1___POR 0x000 +#define PHYA_DEMFRONT_1_CBFG_CFG_2_L__CBF_SNR_BIAS_0___POR 0x000 +#define PHYA_DEMFRONT_1_CBFG_CFG_2_L__CBF_SNR_BIAS_1___M 0x03FF0000 +#define PHYA_DEMFRONT_1_CBFG_CFG_2_L__CBF_SNR_BIAS_1___S 16 +#define PHYA_DEMFRONT_1_CBFG_CFG_2_L__CBF_SNR_BIAS_0___M 0x000003FF +#define PHYA_DEMFRONT_1_CBFG_CFG_2_L__CBF_SNR_BIAS_0___S 0 +#define PHYA_DEMFRONT_1_CBFG_CFG_2_L___M 0x03FF03FF +#define PHYA_DEMFRONT_1_CBFG_CFG_2_L___S 0 + +#define PHYA_DEMFRONT_1_CBFG_CFG_3_L (0x005006F0) +#define PHYA_DEMFRONT_1_CBFG_CFG_3_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CBFG_CFG_3_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_CBFG_CFG_3_L__CBF_SEGMENT_SIZE___POR 0x0000 +#define PHYA_DEMFRONT_1_CBFG_CFG_3_L__SOUNDING_DIALOG_TOKEN___POR 0x00 +#define PHYA_DEMFRONT_1_CBFG_CFG_3_L__CBF_DISABLE_TXBF_THR___POR 0x00 +#define PHYA_DEMFRONT_1_CBFG_CFG_3_L__CBF_SEGMENT_SIZE___M 0xFFFF0000 +#define PHYA_DEMFRONT_1_CBFG_CFG_3_L__CBF_SEGMENT_SIZE___S 16 +#define PHYA_DEMFRONT_1_CBFG_CFG_3_L__SOUNDING_DIALOG_TOKEN___M 0x0000FF00 +#define PHYA_DEMFRONT_1_CBFG_CFG_3_L__SOUNDING_DIALOG_TOKEN___S 8 +#define PHYA_DEMFRONT_1_CBFG_CFG_3_L__CBF_DISABLE_TXBF_THR___M 0x000000FF +#define PHYA_DEMFRONT_1_CBFG_CFG_3_L__CBF_DISABLE_TXBF_THR___S 0 +#define PHYA_DEMFRONT_1_CBFG_CFG_3_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CBFG_CFG_3_L___S 0 + +#define PHYA_DEMFRONT_1_CBFG_CFG_3_U (0x005006F4) +#define PHYA_DEMFRONT_1_CBFG_CFG_3_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CBFG_CFG_3_U___POR 0x00000E00 +#define PHYA_DEMFRONT_1_CBFG_CFG_3_U__CBF_TOTAL_GAIN___POR 0x000 +#define PHYA_DEMFRONT_1_CBFG_CFG_3_U__CBF_SNR_ADC_SCALE___POR 0x0E +#define PHYA_DEMFRONT_1_CBFG_CFG_3_U__CBF_SEGMENT_NUM___POR 0x0 +#define PHYA_DEMFRONT_1_CBFG_CFG_3_U__CBF_TOTAL_GAIN___M 0x0FFF0000 +#define PHYA_DEMFRONT_1_CBFG_CFG_3_U__CBF_TOTAL_GAIN___S 16 +#define PHYA_DEMFRONT_1_CBFG_CFG_3_U__CBF_SNR_ADC_SCALE___M 0x00001F00 +#define PHYA_DEMFRONT_1_CBFG_CFG_3_U__CBF_SNR_ADC_SCALE___S 8 +#define PHYA_DEMFRONT_1_CBFG_CFG_3_U__CBF_SEGMENT_NUM___M 0x0000000F +#define PHYA_DEMFRONT_1_CBFG_CFG_3_U__CBF_SEGMENT_NUM___S 0 +#define PHYA_DEMFRONT_1_CBFG_CFG_3_U___M 0x0FFF1F0F +#define PHYA_DEMFRONT_1_CBFG_CFG_3_U___S 0 + +#define PHYA_DEMFRONT_1_CBFG_CFG_4_L (0x005006F8) +#define PHYA_DEMFRONT_1_CBFG_CFG_4_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CBFG_CFG_4_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_CBFG_CFG_4_L__CBF_CV_SEG0_END___POR 0x0000 +#define PHYA_DEMFRONT_1_CBFG_CFG_4_L__CBF_NOISE_PWR___POR 0x000 +#define PHYA_DEMFRONT_1_CBFG_CFG_4_L__CBF_CV_SEG0_END___M 0x1FFF0000 +#define PHYA_DEMFRONT_1_CBFG_CFG_4_L__CBF_CV_SEG0_END___S 16 +#define PHYA_DEMFRONT_1_CBFG_CFG_4_L__CBF_NOISE_PWR___M 0x00000FFF +#define PHYA_DEMFRONT_1_CBFG_CFG_4_L__CBF_NOISE_PWR___S 0 +#define PHYA_DEMFRONT_1_CBFG_CFG_4_L___M 0x1FFF0FFF +#define PHYA_DEMFRONT_1_CBFG_CFG_4_L___S 0 + +#define PHYA_DEMFRONT_1_CBFG_CFG_4_U (0x005006FC) +#define PHYA_DEMFRONT_1_CBFG_CFG_4_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CBFG_CFG_4_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_CBFG_CFG_4_U__CBF_CV_SEG1_START___POR 0x0000 +#define PHYA_DEMFRONT_1_CBFG_CFG_4_U__CBF_DSNR_SEG0_END___POR 0x0000 +#define PHYA_DEMFRONT_1_CBFG_CFG_4_U__CBF_CV_SEG1_START___M 0x1FFF0000 +#define PHYA_DEMFRONT_1_CBFG_CFG_4_U__CBF_CV_SEG1_START___S 16 +#define PHYA_DEMFRONT_1_CBFG_CFG_4_U__CBF_DSNR_SEG0_END___M 0x00001FFF +#define PHYA_DEMFRONT_1_CBFG_CFG_4_U__CBF_DSNR_SEG0_END___S 0 +#define PHYA_DEMFRONT_1_CBFG_CFG_4_U___M 0x1FFF1FFF +#define PHYA_DEMFRONT_1_CBFG_CFG_4_U___S 0 + +#define PHYA_DEMFRONT_1_CBFG_CFG_5_L (0x00500700) +#define PHYA_DEMFRONT_1_CBFG_CFG_5_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CBFG_CFG_5_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_CBFG_CFG_5_L__CBF_CV_SEG1_END___POR 0x0000 +#define PHYA_DEMFRONT_1_CBFG_CFG_5_L__CBF_DSNR_SEG1_START___POR 0x0000 +#define PHYA_DEMFRONT_1_CBFG_CFG_5_L__CBF_CV_SEG1_END___M 0x1FFF0000 +#define PHYA_DEMFRONT_1_CBFG_CFG_5_L__CBF_CV_SEG1_END___S 16 +#define PHYA_DEMFRONT_1_CBFG_CFG_5_L__CBF_DSNR_SEG1_START___M 0x00001FFF +#define PHYA_DEMFRONT_1_CBFG_CFG_5_L__CBF_DSNR_SEG1_START___S 0 +#define PHYA_DEMFRONT_1_CBFG_CFG_5_L___M 0x1FFF1FFF +#define PHYA_DEMFRONT_1_CBFG_CFG_5_L___S 0 + +#define PHYA_DEMFRONT_1_CBFG_CFG_5_U (0x00500704) +#define PHYA_DEMFRONT_1_CBFG_CFG_5_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CBFG_CFG_5_U___POR 0x00150000 +#define PHYA_DEMFRONT_1_CBFG_CFG_5_U__CBF_SPARE1___POR 0x00 +#define PHYA_DEMFRONT_1_CBFG_CFG_5_U__CBF_CATEGORY___POR 0x15 +#define PHYA_DEMFRONT_1_CBFG_CFG_5_U__CBF_DSNR_SEG0_START___POR 0x0000 +#define PHYA_DEMFRONT_1_CBFG_CFG_5_U__CBF_SPARE1___M 0xFF000000 +#define PHYA_DEMFRONT_1_CBFG_CFG_5_U__CBF_SPARE1___S 24 +#define PHYA_DEMFRONT_1_CBFG_CFG_5_U__CBF_CATEGORY___M 0x00FF0000 +#define PHYA_DEMFRONT_1_CBFG_CFG_5_U__CBF_CATEGORY___S 16 +#define PHYA_DEMFRONT_1_CBFG_CFG_5_U__CBF_DSNR_SEG0_START___M 0x00001FFF +#define PHYA_DEMFRONT_1_CBFG_CFG_5_U__CBF_DSNR_SEG0_START___S 0 +#define PHYA_DEMFRONT_1_CBFG_CFG_5_U___M 0xFFFF1FFF +#define PHYA_DEMFRONT_1_CBFG_CFG_5_U___S 0 + +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_L (0x00500708) +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_L___POR 0x00010000 +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_L__ENABLE_QRNP_MEM_WRITE___POR 0x0 +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_L__SINGLE_PHY___POR 0x1 +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_L__RX_CHAIN_MASK___POR 0x0 +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_L__CLKAXI_RATIO___POR 0x0 +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_L__ENABLE_QRNP_MEM_WRITE___M 0x01000000 +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_L__ENABLE_QRNP_MEM_WRITE___S 24 +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_L__SINGLE_PHY___M 0x00010000 +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_L__SINGLE_PHY___S 16 +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_L__RX_CHAIN_MASK___M 0x00000F00 +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_L__RX_CHAIN_MASK___S 8 +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_L__CLKAXI_RATIO___M 0x00000007 +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_L__CLKAXI_RATIO___S 0 +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_L___M 0x01010F07 +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_L___S 0 + +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_U (0x0050070C) +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_U___POR 0xFFFF0000 +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_U__ENABLE_CLKGATE___POR 0xFFFF +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_U__ENABLE_RXCVMEM_IDM_MODE___POR 0x0 +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_U__ENABLE_CLKGATE___M 0xFFFF0000 +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_U__ENABLE_CLKGATE___S 16 +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_U__ENABLE_RXCVMEM_IDM_MODE___M 0x00000100 +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_U__ENABLE_RXCVMEM_IDM_MODE___S 8 +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_U___M 0xFFFF0100 +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_0_U___S 8 + +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_1_L (0x00500710) +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_1_L___POR 0x00050100 +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_1_L__ML_QAM_THR___POR 0x5 +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_1_L__PILOT_MEM_EN___POR 0x1 +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_1_L__MSS_PHASE_CORR_MODE___POR 0x0 +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_1_L__ML_QAM_THR___M 0x00070000 +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_1_L__ML_QAM_THR___S 16 +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_1_L__PILOT_MEM_EN___M 0x00000100 +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_1_L__PILOT_MEM_EN___S 8 +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_1_L__MSS_PHASE_CORR_MODE___M 0x00000001 +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_1_L__MSS_PHASE_CORR_MODE___S 0 +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_1_L___M 0x00070101 +#define PHYA_DEMFRONT_1_DEMF_GEN_CONTROL_1_L___S 0 + +#define PHYA_DEMFRONT_1_SCSR_MRC_0_L (0x00500718) +#define PHYA_DEMFRONT_1_SCSR_MRC_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_MRC_0_L___POR 0x01070100 +#define PHYA_DEMFRONT_1_SCSR_MRC_0_L__QBPSK_BINW_SCALE_ENA___POR 0x1 +#define PHYA_DEMFRONT_1_SCSR_MRC_0_L__QBPSK_BINW_DISCARD_THR___POR 0x7 +#define PHYA_DEMFRONT_1_SCSR_MRC_0_L__FLAT_CH_THR_SMOOTH_MRC___POR 0x1 +#define PHYA_DEMFRONT_1_SCSR_MRC_0_L__FLAT_CH_THR_MRC___POR 0x0 +#define PHYA_DEMFRONT_1_SCSR_MRC_0_L__QBPSK_BINW_SCALE_ENA___M 0x01000000 +#define PHYA_DEMFRONT_1_SCSR_MRC_0_L__QBPSK_BINW_SCALE_ENA___S 24 +#define PHYA_DEMFRONT_1_SCSR_MRC_0_L__QBPSK_BINW_DISCARD_THR___M 0x00070000 +#define PHYA_DEMFRONT_1_SCSR_MRC_0_L__QBPSK_BINW_DISCARD_THR___S 16 +#define PHYA_DEMFRONT_1_SCSR_MRC_0_L__FLAT_CH_THR_SMOOTH_MRC___M 0x00000300 +#define PHYA_DEMFRONT_1_SCSR_MRC_0_L__FLAT_CH_THR_SMOOTH_MRC___S 8 +#define PHYA_DEMFRONT_1_SCSR_MRC_0_L__FLAT_CH_THR_MRC___M 0x00000003 +#define PHYA_DEMFRONT_1_SCSR_MRC_0_L__FLAT_CH_THR_MRC___S 0 +#define PHYA_DEMFRONT_1_SCSR_MRC_0_L___M 0x01070303 +#define PHYA_DEMFRONT_1_SCSR_MRC_0_L___S 0 + +#define PHYA_DEMFRONT_1_SCSR_MRC_0_U (0x0050071C) +#define PHYA_DEMFRONT_1_SCSR_MRC_0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_MRC_0_U___POR 0x02580107 +#define PHYA_DEMFRONT_1_SCSR_MRC_0_U__RLSIG_THR___POR 0x0258 +#define PHYA_DEMFRONT_1_SCSR_MRC_0_U__RLSIG_BINW_SCALE_ENA___POR 0x1 +#define PHYA_DEMFRONT_1_SCSR_MRC_0_U__RLSIG_BINW_DISCARD_THR___POR 0x7 +#define PHYA_DEMFRONT_1_SCSR_MRC_0_U__RLSIG_THR___M 0xFFFF0000 +#define PHYA_DEMFRONT_1_SCSR_MRC_0_U__RLSIG_THR___S 16 +#define PHYA_DEMFRONT_1_SCSR_MRC_0_U__RLSIG_BINW_SCALE_ENA___M 0x00000100 +#define PHYA_DEMFRONT_1_SCSR_MRC_0_U__RLSIG_BINW_SCALE_ENA___S 8 +#define PHYA_DEMFRONT_1_SCSR_MRC_0_U__RLSIG_BINW_DISCARD_THR___M 0x00000007 +#define PHYA_DEMFRONT_1_SCSR_MRC_0_U__RLSIG_BINW_DISCARD_THR___S 0 +#define PHYA_DEMFRONT_1_SCSR_MRC_0_U___M 0xFFFF0107 +#define PHYA_DEMFRONT_1_SCSR_MRC_0_U___S 0 + +#define PHYA_DEMFRONT_1_SCSR_MRC_1_L (0x00500720) +#define PHYA_DEMFRONT_1_SCSR_MRC_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_MRC_1_L___POR 0x00000001 +#define PHYA_DEMFRONT_1_SCSR_MRC_1_L__EN_BIN_WEIGHTING___POR 0x1 +#define PHYA_DEMFRONT_1_SCSR_MRC_1_L__EN_BIN_WEIGHTING___M 0x00000001 +#define PHYA_DEMFRONT_1_SCSR_MRC_1_L__EN_BIN_WEIGHTING___S 0 +#define PHYA_DEMFRONT_1_SCSR_MRC_1_L___M 0x00000001 +#define PHYA_DEMFRONT_1_SCSR_MRC_1_L___S 0 + +#define PHYA_DEMFRONT_1_SCSR_MRC_2_L (0x00500728) +#define PHYA_DEMFRONT_1_SCSR_MRC_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_MRC_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SCSR_MRC_2_L__MAX_BIN_IQ_EXP_1___POR 0x00 +#define PHYA_DEMFRONT_1_SCSR_MRC_2_L__MAX_BIN_IQ_EXP_0___POR 0x00 +#define PHYA_DEMFRONT_1_SCSR_MRC_2_L__MAX_BIN_IQ_EXP_1___M 0x00001F00 +#define PHYA_DEMFRONT_1_SCSR_MRC_2_L__MAX_BIN_IQ_EXP_1___S 8 +#define PHYA_DEMFRONT_1_SCSR_MRC_2_L__MAX_BIN_IQ_EXP_0___M 0x0000001F +#define PHYA_DEMFRONT_1_SCSR_MRC_2_L__MAX_BIN_IQ_EXP_0___S 0 +#define PHYA_DEMFRONT_1_SCSR_MRC_2_L___M 0x00001F1F +#define PHYA_DEMFRONT_1_SCSR_MRC_2_L___S 0 + +#define PHYA_DEMFRONT_1_SCSR_PTC_0_L (0x00500730) +#define PHYA_DEMFRONT_1_SCSR_PTC_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_PTC_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SCSR_PTC_0_L__ML_FLAT_CHAN_RATIO___POR 0x0 +#define PHYA_DEMFRONT_1_SCSR_PTC_0_L__MRC_SCALE_TABLE___POR 0x0 +#define PHYA_DEMFRONT_1_SCSR_PTC_0_L__LLR_SCALE_NONFLAT_MCS_THR___POR 0x0 +#define PHYA_DEMFRONT_1_SCSR_PTC_0_L__BYPASS_HW_SLOPE___POR 0x0 +#define PHYA_DEMFRONT_1_SCSR_PTC_0_L__ML_FLAT_CHAN_RATIO___M 0x07000000 +#define PHYA_DEMFRONT_1_SCSR_PTC_0_L__ML_FLAT_CHAN_RATIO___S 24 +#define PHYA_DEMFRONT_1_SCSR_PTC_0_L__MRC_SCALE_TABLE___M 0x00070000 +#define PHYA_DEMFRONT_1_SCSR_PTC_0_L__MRC_SCALE_TABLE___S 16 +#define PHYA_DEMFRONT_1_SCSR_PTC_0_L__LLR_SCALE_NONFLAT_MCS_THR___M 0x00000700 +#define PHYA_DEMFRONT_1_SCSR_PTC_0_L__LLR_SCALE_NONFLAT_MCS_THR___S 8 +#define PHYA_DEMFRONT_1_SCSR_PTC_0_L__BYPASS_HW_SLOPE___M 0x00000001 +#define PHYA_DEMFRONT_1_SCSR_PTC_0_L__BYPASS_HW_SLOPE___S 0 +#define PHYA_DEMFRONT_1_SCSR_PTC_0_L___M 0x07070701 +#define PHYA_DEMFRONT_1_SCSR_PTC_0_L___S 0 + +#define PHYA_DEMFRONT_1_SCSR_PTC_0_U (0x00500734) +#define PHYA_DEMFRONT_1_SCSR_PTC_0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_PTC_0_U___POR 0x000001FF +#define PHYA_DEMFRONT_1_SCSR_PTC_0_U__EN_SEGMENT_PTC___POR 0x0 +#define PHYA_DEMFRONT_1_SCSR_PTC_0_U__EN_MODE1P5___POR 0x0 +#define PHYA_DEMFRONT_1_SCSR_PTC_0_U__PCNT_STUCK_THR___POR 0x1FF +#define PHYA_DEMFRONT_1_SCSR_PTC_0_U__EN_SEGMENT_PTC___M 0x01000000 +#define PHYA_DEMFRONT_1_SCSR_PTC_0_U__EN_SEGMENT_PTC___S 24 +#define PHYA_DEMFRONT_1_SCSR_PTC_0_U__EN_MODE1P5___M 0x00010000 +#define PHYA_DEMFRONT_1_SCSR_PTC_0_U__EN_MODE1P5___S 16 +#define PHYA_DEMFRONT_1_SCSR_PTC_0_U__PCNT_STUCK_THR___M 0x000001FF +#define PHYA_DEMFRONT_1_SCSR_PTC_0_U__PCNT_STUCK_THR___S 0 +#define PHYA_DEMFRONT_1_SCSR_PTC_0_U___M 0x010101FF +#define PHYA_DEMFRONT_1_SCSR_PTC_0_U___S 0 + +#define PHYA_DEMFRONT_1_SCSR_PTC_1_L (0x00500738) +#define PHYA_DEMFRONT_1_SCSR_PTC_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_PTC_1_L___POR 0x03000001 +#define PHYA_DEMFRONT_1_SCSR_PTC_1_L__PTC_NON_HE_BETA___POR 0x3 +#define PHYA_DEMFRONT_1_SCSR_PTC_1_L__ENABLE_PTC_JQBPSK___POR 0x0 +#define PHYA_DEMFRONT_1_SCSR_PTC_1_L__DISABLE_CLK_AXI_GATING___POR 0x0 +#define PHYA_DEMFRONT_1_SCSR_PTC_1_L__EN_CHANNEL_CAPTURE___POR 0x1 +#define PHYA_DEMFRONT_1_SCSR_PTC_1_L__PTC_NON_HE_BETA___M 0x07000000 +#define PHYA_DEMFRONT_1_SCSR_PTC_1_L__PTC_NON_HE_BETA___S 24 +#define PHYA_DEMFRONT_1_SCSR_PTC_1_L__ENABLE_PTC_JQBPSK___M 0x00010000 +#define PHYA_DEMFRONT_1_SCSR_PTC_1_L__ENABLE_PTC_JQBPSK___S 16 +#define PHYA_DEMFRONT_1_SCSR_PTC_1_L__DISABLE_CLK_AXI_GATING___M 0x00000100 +#define PHYA_DEMFRONT_1_SCSR_PTC_1_L__DISABLE_CLK_AXI_GATING___S 8 +#define PHYA_DEMFRONT_1_SCSR_PTC_1_L__EN_CHANNEL_CAPTURE___M 0x00000001 +#define PHYA_DEMFRONT_1_SCSR_PTC_1_L__EN_CHANNEL_CAPTURE___S 0 +#define PHYA_DEMFRONT_1_SCSR_PTC_1_L___M 0x07010101 +#define PHYA_DEMFRONT_1_SCSR_PTC_1_L___S 0 + +#define PHYA_DEMFRONT_1_SCSR_PTC_1_U (0x0050073C) +#define PHYA_DEMFRONT_1_SCSR_PTC_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_PTC_1_U___POR 0x00070302 +#define PHYA_DEMFRONT_1_SCSR_PTC_1_U__ML_OFF_DIAG_THR_LLR___POR 0x007 +#define PHYA_DEMFRONT_1_SCSR_PTC_1_U__ML_DIAG_THR_LLR___POR 0x03 +#define PHYA_DEMFRONT_1_SCSR_PTC_1_U__PTC_HE_BETA___POR 0x2 +#define PHYA_DEMFRONT_1_SCSR_PTC_1_U__ML_OFF_DIAG_THR_LLR___M 0x03FF0000 +#define PHYA_DEMFRONT_1_SCSR_PTC_1_U__ML_OFF_DIAG_THR_LLR___S 16 +#define PHYA_DEMFRONT_1_SCSR_PTC_1_U__ML_DIAG_THR_LLR___M 0x00001F00 +#define PHYA_DEMFRONT_1_SCSR_PTC_1_U__ML_DIAG_THR_LLR___S 8 +#define PHYA_DEMFRONT_1_SCSR_PTC_1_U__PTC_HE_BETA___M 0x00000007 +#define PHYA_DEMFRONT_1_SCSR_PTC_1_U__PTC_HE_BETA___S 0 +#define PHYA_DEMFRONT_1_SCSR_PTC_1_U___M 0x03FF1F07 +#define PHYA_DEMFRONT_1_SCSR_PTC_1_U___S 0 + +#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_0_L (0x00500740) +#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_0_L__PM0_PILOT_MASK_IDX___POR 0x0000 +#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_0_L__PM0_PILOT_MASK_IDX___M 0x0000FFFF +#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_0_L__PM0_PILOT_MASK_IDX___S 0 +#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_0_L___M 0x0000FFFF +#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_0_L___S 0 + +#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_L (0x00500748) +#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_L__PM0_3_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_L__PM0_2_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_L__PM0_1_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_L__PM0_0_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_L__PM0_3_PMASK___M 0x1F000000 +#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_L__PM0_3_PMASK___S 24 +#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_L__PM0_2_PMASK___M 0x001F0000 +#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_L__PM0_2_PMASK___S 16 +#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_L__PM0_1_PMASK___M 0x00001F00 +#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_L__PM0_1_PMASK___S 8 +#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_L__PM0_0_PMASK___M 0x0000001F +#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_L__PM0_0_PMASK___S 0 +#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_L___M 0x1F1F1F1F +#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_L___S 0 + +#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_U (0x0050074C) +#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_U__PM0_4_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_U__PM0_4_PMASK___M 0x0000001F +#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_U__PM0_4_PMASK___S 0 +#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_U___M 0x0000001F +#define PHYA_DEMFRONT_1_PM0_PILOT_MASK_1_U___S 0 + +#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_0_L (0x00500750) +#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_0_L__PM1_PILOT_MASK_IDX___POR 0x0000 +#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_0_L__PM1_PILOT_MASK_IDX___M 0x0000FFFF +#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_0_L__PM1_PILOT_MASK_IDX___S 0 +#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_0_L___M 0x0000FFFF +#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_0_L___S 0 + +#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_L (0x00500758) +#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_L__PM1_3_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_L__PM1_2_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_L__PM1_1_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_L__PM1_0_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_L__PM1_3_PMASK___M 0x1F000000 +#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_L__PM1_3_PMASK___S 24 +#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_L__PM1_2_PMASK___M 0x001F0000 +#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_L__PM1_2_PMASK___S 16 +#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_L__PM1_1_PMASK___M 0x00001F00 +#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_L__PM1_1_PMASK___S 8 +#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_L__PM1_0_PMASK___M 0x0000001F +#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_L__PM1_0_PMASK___S 0 +#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_L___M 0x1F1F1F1F +#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_L___S 0 + +#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_U (0x0050075C) +#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_U__PM1_4_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_U__PM1_4_PMASK___M 0x0000001F +#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_U__PM1_4_PMASK___S 0 +#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_U___M 0x0000001F +#define PHYA_DEMFRONT_1_PM1_PILOT_MASK_1_U___S 0 + +#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_0_L (0x00500760) +#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_0_L__PM2_PILOT_MASK_IDX___POR 0x0000 +#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_0_L__PM2_PILOT_MASK_IDX___M 0x0000FFFF +#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_0_L__PM2_PILOT_MASK_IDX___S 0 +#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_0_L___M 0x0000FFFF +#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_0_L___S 0 + +#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_L (0x00500768) +#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_L__PM2_3_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_L__PM2_2_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_L__PM2_1_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_L__PM2_0_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_L__PM2_3_PMASK___M 0x1F000000 +#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_L__PM2_3_PMASK___S 24 +#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_L__PM2_2_PMASK___M 0x001F0000 +#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_L__PM2_2_PMASK___S 16 +#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_L__PM2_1_PMASK___M 0x00001F00 +#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_L__PM2_1_PMASK___S 8 +#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_L__PM2_0_PMASK___M 0x0000001F +#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_L__PM2_0_PMASK___S 0 +#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_L___M 0x1F1F1F1F +#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_L___S 0 + +#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_U (0x0050076C) +#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_U__PM2_4_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_U__PM2_4_PMASK___M 0x0000001F +#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_U__PM2_4_PMASK___S 0 +#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_U___M 0x0000001F +#define PHYA_DEMFRONT_1_PM2_PILOT_MASK_1_U___S 0 + +#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_0_L (0x00500770) +#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_0_L__PM3_PILOT_MASK_IDX___POR 0x0000 +#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_0_L__PM3_PILOT_MASK_IDX___M 0x0000FFFF +#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_0_L__PM3_PILOT_MASK_IDX___S 0 +#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_0_L___M 0x0000FFFF +#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_0_L___S 0 + +#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_L (0x00500778) +#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_L__PM3_3_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_L__PM3_2_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_L__PM3_1_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_L__PM3_0_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_L__PM3_3_PMASK___M 0x1F000000 +#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_L__PM3_3_PMASK___S 24 +#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_L__PM3_2_PMASK___M 0x001F0000 +#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_L__PM3_2_PMASK___S 16 +#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_L__PM3_1_PMASK___M 0x00001F00 +#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_L__PM3_1_PMASK___S 8 +#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_L__PM3_0_PMASK___M 0x0000001F +#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_L__PM3_0_PMASK___S 0 +#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_L___M 0x1F1F1F1F +#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_L___S 0 + +#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_U (0x0050077C) +#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_U__PM3_4_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_U__PM3_4_PMASK___M 0x0000001F +#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_U__PM3_4_PMASK___S 0 +#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_U___M 0x0000001F +#define PHYA_DEMFRONT_1_PM3_PILOT_MASK_1_U___S 0 + +#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_0_L (0x00500780) +#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_0_L__PM4_PILOT_MASK_IDX___POR 0x0000 +#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_0_L__PM4_PILOT_MASK_IDX___M 0x0000FFFF +#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_0_L__PM4_PILOT_MASK_IDX___S 0 +#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_0_L___M 0x0000FFFF +#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_0_L___S 0 + +#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_L (0x00500788) +#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_L__PM4_3_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_L__PM4_2_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_L__PM4_1_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_L__PM4_0_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_L__PM4_3_PMASK___M 0x1F000000 +#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_L__PM4_3_PMASK___S 24 +#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_L__PM4_2_PMASK___M 0x001F0000 +#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_L__PM4_2_PMASK___S 16 +#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_L__PM4_1_PMASK___M 0x00001F00 +#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_L__PM4_1_PMASK___S 8 +#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_L__PM4_0_PMASK___M 0x0000001F +#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_L__PM4_0_PMASK___S 0 +#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_L___M 0x1F1F1F1F +#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_L___S 0 + +#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_U (0x0050078C) +#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_U__PM4_4_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_U__PM4_4_PMASK___M 0x0000001F +#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_U__PM4_4_PMASK___S 0 +#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_U___M 0x0000001F +#define PHYA_DEMFRONT_1_PM4_PILOT_MASK_1_U___S 0 + +#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_0_L (0x00500790) +#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_0_L__PM5_PILOT_MASK_IDX___POR 0x0000 +#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_0_L__PM5_PILOT_MASK_IDX___M 0x0000FFFF +#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_0_L__PM5_PILOT_MASK_IDX___S 0 +#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_0_L___M 0x0000FFFF +#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_0_L___S 0 + +#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_L (0x00500798) +#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_L__PM5_3_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_L__PM5_2_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_L__PM5_1_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_L__PM5_0_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_L__PM5_3_PMASK___M 0x1F000000 +#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_L__PM5_3_PMASK___S 24 +#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_L__PM5_2_PMASK___M 0x001F0000 +#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_L__PM5_2_PMASK___S 16 +#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_L__PM5_1_PMASK___M 0x00001F00 +#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_L__PM5_1_PMASK___S 8 +#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_L__PM5_0_PMASK___M 0x0000001F +#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_L__PM5_0_PMASK___S 0 +#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_L___M 0x1F1F1F1F +#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_L___S 0 + +#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_U (0x0050079C) +#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_U__PM5_4_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_U__PM5_4_PMASK___M 0x0000001F +#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_U__PM5_4_PMASK___S 0 +#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_U___M 0x0000001F +#define PHYA_DEMFRONT_1_PM5_PILOT_MASK_1_U___S 0 + +#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_0_L (0x005007A0) +#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_0_L__PM6_PILOT_MASK_IDX___POR 0x0000 +#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_0_L__PM6_PILOT_MASK_IDX___M 0x0000FFFF +#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_0_L__PM6_PILOT_MASK_IDX___S 0 +#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_0_L___M 0x0000FFFF +#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_0_L___S 0 + +#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_L (0x005007A8) +#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_L__PM6_3_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_L__PM6_2_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_L__PM6_1_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_L__PM6_0_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_L__PM6_3_PMASK___M 0x1F000000 +#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_L__PM6_3_PMASK___S 24 +#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_L__PM6_2_PMASK___M 0x001F0000 +#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_L__PM6_2_PMASK___S 16 +#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_L__PM6_1_PMASK___M 0x00001F00 +#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_L__PM6_1_PMASK___S 8 +#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_L__PM6_0_PMASK___M 0x0000001F +#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_L__PM6_0_PMASK___S 0 +#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_L___M 0x1F1F1F1F +#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_L___S 0 + +#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_U (0x005007AC) +#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_U__PM6_4_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_U__PM6_4_PMASK___M 0x0000001F +#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_U__PM6_4_PMASK___S 0 +#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_U___M 0x0000001F +#define PHYA_DEMFRONT_1_PM6_PILOT_MASK_1_U___S 0 + +#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_0_L (0x005007B0) +#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_0_L__PM7_PILOT_MASK_IDX___POR 0x0000 +#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_0_L__PM7_PILOT_MASK_IDX___M 0x0000FFFF +#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_0_L__PM7_PILOT_MASK_IDX___S 0 +#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_0_L___M 0x0000FFFF +#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_0_L___S 0 + +#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_L (0x005007B8) +#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_L__PM7_3_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_L__PM7_2_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_L__PM7_1_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_L__PM7_0_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_L__PM7_3_PMASK___M 0x1F000000 +#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_L__PM7_3_PMASK___S 24 +#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_L__PM7_2_PMASK___M 0x001F0000 +#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_L__PM7_2_PMASK___S 16 +#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_L__PM7_1_PMASK___M 0x00001F00 +#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_L__PM7_1_PMASK___S 8 +#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_L__PM7_0_PMASK___M 0x0000001F +#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_L__PM7_0_PMASK___S 0 +#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_L___M 0x1F1F1F1F +#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_L___S 0 + +#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_U (0x005007BC) +#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_U__PM7_4_PMASK___POR 0x00 +#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_U__PM7_4_PMASK___M 0x0000001F +#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_U__PM7_4_PMASK___S 0 +#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_U___M 0x0000001F +#define PHYA_DEMFRONT_1_PM7_PILOT_MASK_1_U___S 0 + +#define PHYA_DEMFRONT_1_PTC_CONTROL_L (0x005007C0) +#define PHYA_DEMFRONT_1_PTC_CONTROL_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PTC_CONTROL_L___POR 0x00044E05 +#define PHYA_DEMFRONT_1_PTC_CONTROL_L__DELTA_SLOPE_COEF_EXP___POR 0x004 +#define PHYA_DEMFRONT_1_PTC_CONTROL_L__DELTA_SLOPE_COEF_MAN___POR 0x4E05 +#define PHYA_DEMFRONT_1_PTC_CONTROL_L__DELTA_SLOPE_COEF_EXP___M 0x03FF0000 +#define PHYA_DEMFRONT_1_PTC_CONTROL_L__DELTA_SLOPE_COEF_EXP___S 16 +#define PHYA_DEMFRONT_1_PTC_CONTROL_L__DELTA_SLOPE_COEF_MAN___M 0x00007FFF +#define PHYA_DEMFRONT_1_PTC_CONTROL_L__DELTA_SLOPE_COEF_MAN___S 0 +#define PHYA_DEMFRONT_1_PTC_CONTROL_L___M 0x03FF7FFF +#define PHYA_DEMFRONT_1_PTC_CONTROL_L___S 0 + +#define PHYA_DEMFRONT_1_SCSR_QRE_0_L (0x005007C8) +#define PHYA_DEMFRONT_1_SCSR_QRE_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_QRE_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SCSR_QRE_0_L__ML_DIAG_THR1___POR 0x0 +#define PHYA_DEMFRONT_1_SCSR_QRE_0_L__ML_DIAG_THR1___M 0x0000000F +#define PHYA_DEMFRONT_1_SCSR_QRE_0_L__ML_DIAG_THR1___S 0 +#define PHYA_DEMFRONT_1_SCSR_QRE_0_L___M 0x0000000F +#define PHYA_DEMFRONT_1_SCSR_QRE_0_L___S 0 + +#define PHYA_DEMFRONT_1_SCSR_QRE_1_L (0x005007D0) +#define PHYA_DEMFRONT_1_SCSR_QRE_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_QRE_1_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SCSR_QRE_1_L__ML_DIAG_THR2___POR 0x0 +#define PHYA_DEMFRONT_1_SCSR_QRE_1_L__ML_DIAG_THR2___M 0x0000000F +#define PHYA_DEMFRONT_1_SCSR_QRE_1_L__ML_DIAG_THR2___S 0 +#define PHYA_DEMFRONT_1_SCSR_QRE_1_L___M 0x0000000F +#define PHYA_DEMFRONT_1_SCSR_QRE_1_L___S 0 + +#define PHYA_DEMFRONT_1_SCSR_QRE_2_L (0x005007D8) +#define PHYA_DEMFRONT_1_SCSR_QRE_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_QRE_2_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SCSR_QRE_2_L__SIR_NORM_FACT___POR 0x000 +#define PHYA_DEMFRONT_1_SCSR_QRE_2_L__SIR_NORM_FACT___M 0x000001FF +#define PHYA_DEMFRONT_1_SCSR_QRE_2_L__SIR_NORM_FACT___S 0 +#define PHYA_DEMFRONT_1_SCSR_QRE_2_L___M 0x000001FF +#define PHYA_DEMFRONT_1_SCSR_QRE_2_L___S 0 + +#define PHYA_DEMFRONT_1_SCSR_QRE_3_L (0x005007E0) +#define PHYA_DEMFRONT_1_SCSR_QRE_3_L___RWC QCSR_REG_RO +#define PHYA_DEMFRONT_1_SCSR_QRE_3_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SCSR_QRE_3_L__SIR_DB_1___POR 0x00 +#define PHYA_DEMFRONT_1_SCSR_QRE_3_L__SIR_DB_0___POR 0x00 +#define PHYA_DEMFRONT_1_SCSR_QRE_3_L__SIR_DB_1___M 0x00003F00 +#define PHYA_DEMFRONT_1_SCSR_QRE_3_L__SIR_DB_1___S 8 +#define PHYA_DEMFRONT_1_SCSR_QRE_3_L__SIR_DB_0___M 0x0000003F +#define PHYA_DEMFRONT_1_SCSR_QRE_3_L__SIR_DB_0___S 0 +#define PHYA_DEMFRONT_1_SCSR_QRE_3_L___M 0x00003F3F +#define PHYA_DEMFRONT_1_SCSR_QRE_3_L___S 0 + +#define PHYA_DEMFRONT_1_CBFG_CFG1_L (0x00500830) +#define PHYA_DEMFRONT_1_CBFG_CFG1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CBFG_CFG1_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_CBFG_CFG1_L__CBFG_SYNC_RST___POR 0x0 +#define PHYA_DEMFRONT_1_CBFG_CFG1_L__USE_BFEE_SYNC_RST___POR 0x0 +#define PHYA_DEMFRONT_1_CBFG_CFG1_L__BFEE_SYNC_RST___POR 0x0 +#define PHYA_DEMFRONT_1_CBFG_CFG1_L__CBFG_SYNC_RST___M 0x00010000 +#define PHYA_DEMFRONT_1_CBFG_CFG1_L__CBFG_SYNC_RST___S 16 +#define PHYA_DEMFRONT_1_CBFG_CFG1_L__USE_BFEE_SYNC_RST___M 0x00000100 +#define PHYA_DEMFRONT_1_CBFG_CFG1_L__USE_BFEE_SYNC_RST___S 8 +#define PHYA_DEMFRONT_1_CBFG_CFG1_L__BFEE_SYNC_RST___M 0x00000001 +#define PHYA_DEMFRONT_1_CBFG_CFG1_L__BFEE_SYNC_RST___S 0 +#define PHYA_DEMFRONT_1_CBFG_CFG1_L___M 0x00010101 +#define PHYA_DEMFRONT_1_CBFG_CFG1_L___S 0 + +#define PHYA_DEMFRONT_1_DYNAMIC_ROOT_CLK_EN_L (0x00500840) +#define PHYA_DEMFRONT_1_DYNAMIC_ROOT_CLK_EN_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_DYNAMIC_ROOT_CLK_EN_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_DYNAMIC_ROOT_CLK_EN_L__ROOT_CLK_EN___POR 0x0 +#define PHYA_DEMFRONT_1_DYNAMIC_ROOT_CLK_EN_L__ROOT_CLK_EN___M 0x00000001 +#define PHYA_DEMFRONT_1_DYNAMIC_ROOT_CLK_EN_L__ROOT_CLK_EN___S 0 +#define PHYA_DEMFRONT_1_DYNAMIC_ROOT_CLK_EN_L___M 0x00000001 +#define PHYA_DEMFRONT_1_DYNAMIC_ROOT_CLK_EN_L___S 0 + +#define PHYA_DEMFRONT_1_ENA_DEMF_ASYNC_RST_L (0x00500848) +#define PHYA_DEMFRONT_1_ENA_DEMF_ASYNC_RST_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_ENA_DEMF_ASYNC_RST_L___POR 0x00000001 +#define PHYA_DEMFRONT_1_ENA_DEMF_ASYNC_RST_L__ENA_DEMF_ASYNC_RST___POR 0x1 +#define PHYA_DEMFRONT_1_ENA_DEMF_ASYNC_RST_L__ENA_DEMF_ASYNC_RST___M 0x00000001 +#define PHYA_DEMFRONT_1_ENA_DEMF_ASYNC_RST_L__ENA_DEMF_ASYNC_RST___S 0 +#define PHYA_DEMFRONT_1_ENA_DEMF_ASYNC_RST_L___M 0x00000001 +#define PHYA_DEMFRONT_1_ENA_DEMF_ASYNC_RST_L___S 0 + +#define PHYA_DEMFRONT_1_SCSR_CTRL_0_L (0x00500850) +#define PHYA_DEMFRONT_1_SCSR_CTRL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_CTRL_0_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SCSR_CTRL_0_L__AVG_1SS_OFDMA___POR 0x0 +#define PHYA_DEMFRONT_1_SCSR_CTRL_0_L__LISTEN_CHAIN___POR 0x0 +#define PHYA_DEMFRONT_1_SCSR_CTRL_0_L__SKIP_LLTF1_CHE___POR 0x0 +#define PHYA_DEMFRONT_1_SCSR_CTRL_0_L__ENABLE_ONE_CHAIN_SEARCH___POR 0x0 +#define PHYA_DEMFRONT_1_SCSR_CTRL_0_L__AVG_1SS_OFDMA___M 0x01000000 +#define PHYA_DEMFRONT_1_SCSR_CTRL_0_L__AVG_1SS_OFDMA___S 24 +#define PHYA_DEMFRONT_1_SCSR_CTRL_0_L__LISTEN_CHAIN___M 0x00010000 +#define PHYA_DEMFRONT_1_SCSR_CTRL_0_L__LISTEN_CHAIN___S 16 +#define PHYA_DEMFRONT_1_SCSR_CTRL_0_L__SKIP_LLTF1_CHE___M 0x00000100 +#define PHYA_DEMFRONT_1_SCSR_CTRL_0_L__SKIP_LLTF1_CHE___S 8 +#define PHYA_DEMFRONT_1_SCSR_CTRL_0_L__ENABLE_ONE_CHAIN_SEARCH___M 0x00000001 +#define PHYA_DEMFRONT_1_SCSR_CTRL_0_L__ENABLE_ONE_CHAIN_SEARCH___S 0 +#define PHYA_DEMFRONT_1_SCSR_CTRL_0_L___M 0x01010101 +#define PHYA_DEMFRONT_1_SCSR_CTRL_0_L___S 0 + +#define PHYA_DEMFRONT_1_SCSR_CTRL_0_U (0x00500854) +#define PHYA_DEMFRONT_1_SCSR_CTRL_0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_CTRL_0_U___POR 0x00010100 +#define PHYA_DEMFRONT_1_SCSR_CTRL_0_U__PTC_SYM_IDX_TO_SWITCH_BETA___POR 0x0 +#define PHYA_DEMFRONT_1_SCSR_CTRL_0_U__DISABLE_DF_PTC_MCS1_QPSK_LDPC___POR 0x1 +#define PHYA_DEMFRONT_1_SCSR_CTRL_0_U__DISABLE_DF_PTC_QPSK___POR 0x1 +#define PHYA_DEMFRONT_1_SCSR_CTRL_0_U__PTC_SYM_IDX_TO_SWITCH_BETA___M 0x03000000 +#define PHYA_DEMFRONT_1_SCSR_CTRL_0_U__PTC_SYM_IDX_TO_SWITCH_BETA___S 24 +#define PHYA_DEMFRONT_1_SCSR_CTRL_0_U__DISABLE_DF_PTC_MCS1_QPSK_LDPC___M 0x00010000 +#define PHYA_DEMFRONT_1_SCSR_CTRL_0_U__DISABLE_DF_PTC_MCS1_QPSK_LDPC___S 16 +#define PHYA_DEMFRONT_1_SCSR_CTRL_0_U__DISABLE_DF_PTC_QPSK___M 0x00000100 +#define PHYA_DEMFRONT_1_SCSR_CTRL_0_U__DISABLE_DF_PTC_QPSK___S 8 +#define PHYA_DEMFRONT_1_SCSR_CTRL_0_U___M 0x03010100 +#define PHYA_DEMFRONT_1_SCSR_CTRL_0_U___S 8 + +#define PHYA_DEMFRONT_1_SCSR_CTRL_1_L (0x00500858) +#define PHYA_DEMFRONT_1_SCSR_CTRL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_CTRL_1_L___POR 0x01010202 +#define PHYA_DEMFRONT_1_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_3___POR 0x1 +#define PHYA_DEMFRONT_1_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_2___POR 0x1 +#define PHYA_DEMFRONT_1_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_1___POR 0x2 +#define PHYA_DEMFRONT_1_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_0___POR 0x2 +#define PHYA_DEMFRONT_1_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_3___M 0x07000000 +#define PHYA_DEMFRONT_1_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_3___S 24 +#define PHYA_DEMFRONT_1_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_2___M 0x00070000 +#define PHYA_DEMFRONT_1_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_2___S 16 +#define PHYA_DEMFRONT_1_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_1___M 0x00000700 +#define PHYA_DEMFRONT_1_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_1___S 8 +#define PHYA_DEMFRONT_1_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_0___M 0x00000007 +#define PHYA_DEMFRONT_1_SCSR_CTRL_1_L__PTC_BETA_HE_INIT_SYM_0___S 0 +#define PHYA_DEMFRONT_1_SCSR_CTRL_1_L___M 0x07070707 +#define PHYA_DEMFRONT_1_SCSR_CTRL_1_L___S 0 + +#define PHYA_DEMFRONT_1_SCSR_CTRL_1_U (0x0050085C) +#define PHYA_DEMFRONT_1_SCSR_CTRL_1_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_CTRL_1_U___POR 0x02010101 +#define PHYA_DEMFRONT_1_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_7___POR 0x2 +#define PHYA_DEMFRONT_1_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_6___POR 0x1 +#define PHYA_DEMFRONT_1_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_5___POR 0x1 +#define PHYA_DEMFRONT_1_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_4___POR 0x1 +#define PHYA_DEMFRONT_1_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_7___M 0x07000000 +#define PHYA_DEMFRONT_1_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_7___S 24 +#define PHYA_DEMFRONT_1_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_6___M 0x00070000 +#define PHYA_DEMFRONT_1_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_6___S 16 +#define PHYA_DEMFRONT_1_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_5___M 0x00000700 +#define PHYA_DEMFRONT_1_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_5___S 8 +#define PHYA_DEMFRONT_1_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_4___M 0x00000007 +#define PHYA_DEMFRONT_1_SCSR_CTRL_1_U__PTC_BETA_HE_INIT_SYM_4___S 0 +#define PHYA_DEMFRONT_1_SCSR_CTRL_1_U___M 0x07070707 +#define PHYA_DEMFRONT_1_SCSR_CTRL_1_U___S 0 + +#define PHYA_DEMFRONT_1_SCSR_CTRL_2_L (0x00500860) +#define PHYA_DEMFRONT_1_SCSR_CTRL_2_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_CTRL_2_L___POR 0x02020303 +#define PHYA_DEMFRONT_1_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_3___POR 0x2 +#define PHYA_DEMFRONT_1_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_2___POR 0x2 +#define PHYA_DEMFRONT_1_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_1___POR 0x3 +#define PHYA_DEMFRONT_1_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_0___POR 0x3 +#define PHYA_DEMFRONT_1_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_3___M 0x07000000 +#define PHYA_DEMFRONT_1_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_3___S 24 +#define PHYA_DEMFRONT_1_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_2___M 0x00070000 +#define PHYA_DEMFRONT_1_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_2___S 16 +#define PHYA_DEMFRONT_1_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_1___M 0x00000700 +#define PHYA_DEMFRONT_1_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_1___S 8 +#define PHYA_DEMFRONT_1_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_0___M 0x00000007 +#define PHYA_DEMFRONT_1_SCSR_CTRL_2_L__PTC_BETA_NON_HE_INIT_SYM_0___S 0 +#define PHYA_DEMFRONT_1_SCSR_CTRL_2_L___M 0x07070707 +#define PHYA_DEMFRONT_1_SCSR_CTRL_2_L___S 0 + +#define PHYA_DEMFRONT_1_SCSR_CTRL_2_U (0x00500864) +#define PHYA_DEMFRONT_1_SCSR_CTRL_2_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_CTRL_2_U___POR 0x03010102 +#define PHYA_DEMFRONT_1_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_7___POR 0x3 +#define PHYA_DEMFRONT_1_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_6___POR 0x1 +#define PHYA_DEMFRONT_1_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_5___POR 0x1 +#define PHYA_DEMFRONT_1_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_4___POR 0x2 +#define PHYA_DEMFRONT_1_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_7___M 0x07000000 +#define PHYA_DEMFRONT_1_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_7___S 24 +#define PHYA_DEMFRONT_1_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_6___M 0x00070000 +#define PHYA_DEMFRONT_1_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_6___S 16 +#define PHYA_DEMFRONT_1_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_5___M 0x00000700 +#define PHYA_DEMFRONT_1_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_5___S 8 +#define PHYA_DEMFRONT_1_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_4___M 0x00000007 +#define PHYA_DEMFRONT_1_SCSR_CTRL_2_U__PTC_BETA_NON_HE_INIT_SYM_4___S 0 +#define PHYA_DEMFRONT_1_SCSR_CTRL_2_U___M 0x07070707 +#define PHYA_DEMFRONT_1_SCSR_CTRL_2_U___S 0 + +#define PHYA_DEMFRONT_1_SCSR_CTRL_3_L (0x00500868) +#define PHYA_DEMFRONT_1_SCSR_CTRL_3_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_CTRL_3_L___POR 0x02020202 +#define PHYA_DEMFRONT_1_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_3___POR 0x2 +#define PHYA_DEMFRONT_1_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_2___POR 0x2 +#define PHYA_DEMFRONT_1_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_1___POR 0x2 +#define PHYA_DEMFRONT_1_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_0___POR 0x2 +#define PHYA_DEMFRONT_1_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_3___M 0x07000000 +#define PHYA_DEMFRONT_1_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_3___S 24 +#define PHYA_DEMFRONT_1_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_2___M 0x00070000 +#define PHYA_DEMFRONT_1_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_2___S 16 +#define PHYA_DEMFRONT_1_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_1___M 0x00000700 +#define PHYA_DEMFRONT_1_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_1___S 8 +#define PHYA_DEMFRONT_1_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_0___M 0x00000007 +#define PHYA_DEMFRONT_1_SCSR_CTRL_3_L__PTC_BETA_HE_SYM_0___S 0 +#define PHYA_DEMFRONT_1_SCSR_CTRL_3_L___M 0x07070707 +#define PHYA_DEMFRONT_1_SCSR_CTRL_3_L___S 0 + +#define PHYA_DEMFRONT_1_SCSR_CTRL_3_U (0x0050086C) +#define PHYA_DEMFRONT_1_SCSR_CTRL_3_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_CTRL_3_U___POR 0x02010102 +#define PHYA_DEMFRONT_1_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_7___POR 0x2 +#define PHYA_DEMFRONT_1_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_6___POR 0x1 +#define PHYA_DEMFRONT_1_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_5___POR 0x1 +#define PHYA_DEMFRONT_1_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_4___POR 0x2 +#define PHYA_DEMFRONT_1_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_7___M 0x07000000 +#define PHYA_DEMFRONT_1_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_7___S 24 +#define PHYA_DEMFRONT_1_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_6___M 0x00070000 +#define PHYA_DEMFRONT_1_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_6___S 16 +#define PHYA_DEMFRONT_1_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_5___M 0x00000700 +#define PHYA_DEMFRONT_1_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_5___S 8 +#define PHYA_DEMFRONT_1_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_4___M 0x00000007 +#define PHYA_DEMFRONT_1_SCSR_CTRL_3_U__PTC_BETA_HE_SYM_4___S 0 +#define PHYA_DEMFRONT_1_SCSR_CTRL_3_U___M 0x07070707 +#define PHYA_DEMFRONT_1_SCSR_CTRL_3_U___S 0 + +#define PHYA_DEMFRONT_1_SCSR_CTRL_4_L (0x00500870) +#define PHYA_DEMFRONT_1_SCSR_CTRL_4_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_CTRL_4_L___POR 0x03030303 +#define PHYA_DEMFRONT_1_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_3___POR 0x3 +#define PHYA_DEMFRONT_1_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_2___POR 0x3 +#define PHYA_DEMFRONT_1_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_1___POR 0x3 +#define PHYA_DEMFRONT_1_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_0___POR 0x3 +#define PHYA_DEMFRONT_1_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_3___M 0x07000000 +#define PHYA_DEMFRONT_1_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_3___S 24 +#define PHYA_DEMFRONT_1_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_2___M 0x00070000 +#define PHYA_DEMFRONT_1_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_2___S 16 +#define PHYA_DEMFRONT_1_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_1___M 0x00000700 +#define PHYA_DEMFRONT_1_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_1___S 8 +#define PHYA_DEMFRONT_1_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_0___M 0x00000007 +#define PHYA_DEMFRONT_1_SCSR_CTRL_4_L__PTC_BETA_NON_HE_SYM_0___S 0 +#define PHYA_DEMFRONT_1_SCSR_CTRL_4_L___M 0x07070707 +#define PHYA_DEMFRONT_1_SCSR_CTRL_4_L___S 0 + +#define PHYA_DEMFRONT_1_SCSR_CTRL_4_U (0x00500874) +#define PHYA_DEMFRONT_1_SCSR_CTRL_4_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_CTRL_4_U___POR 0x03020203 +#define PHYA_DEMFRONT_1_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_7___POR 0x3 +#define PHYA_DEMFRONT_1_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_6___POR 0x2 +#define PHYA_DEMFRONT_1_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_5___POR 0x2 +#define PHYA_DEMFRONT_1_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_4___POR 0x3 +#define PHYA_DEMFRONT_1_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_7___M 0x07000000 +#define PHYA_DEMFRONT_1_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_7___S 24 +#define PHYA_DEMFRONT_1_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_6___M 0x00070000 +#define PHYA_DEMFRONT_1_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_6___S 16 +#define PHYA_DEMFRONT_1_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_5___M 0x00000700 +#define PHYA_DEMFRONT_1_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_5___S 8 +#define PHYA_DEMFRONT_1_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_4___M 0x00000007 +#define PHYA_DEMFRONT_1_SCSR_CTRL_4_U__PTC_BETA_NON_HE_SYM_4___S 0 +#define PHYA_DEMFRONT_1_SCSR_CTRL_4_U___M 0x07070707 +#define PHYA_DEMFRONT_1_SCSR_CTRL_4_U___S 0 + +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_L (0x00500DA0) +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_L___POR 0x0020000C +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_L__FREQ_SEL_ID_MIN_NUM_TONES___POR 0x020 +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_L__FREQ_SEL_ID_THRES___POR 0x0C +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_L__FREQ_SEL_ID_MIN_NUM_TONES___M 0x03FF0000 +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_L__FREQ_SEL_ID_MIN_NUM_TONES___S 16 +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_L__FREQ_SEL_ID_THRES___M 0x0000001F +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_L__FREQ_SEL_ID_THRES___S 0 +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_L___M 0x03FF001F +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_L___S 0 + +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_U (0x00500DA4) +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_U___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_U___POR 0x00070100 +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_U__SLOPE_EST_MIN_NUM_TONES___POR 0x007 +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_U__EN_SLOPE_ESTIMATION___POR 0x1 +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_U__SLOPE_EST_MIN_NUM_TONES___M 0x03FF0000 +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_U__SLOPE_EST_MIN_NUM_TONES___S 16 +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_U__EN_SLOPE_ESTIMATION___M 0x00000100 +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_U__EN_SLOPE_ESTIMATION___S 8 +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_U___M 0x03FF0100 +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_0_U___S 8 + +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_1_L (0x00500DA8) +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_1_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_1_L___POR 0x00000106 +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_1_L__SM_FILTER_SEL_OVERRIDE___POR 0x0 +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_1_L__EN_FLAT_CHANNEL_CHECK___POR 0x1 +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_1_L__IS_FLAT_CHANNEL_THR___POR 0x06 +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_1_L__SM_FILTER_SEL_OVERRIDE___M 0x00030000 +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_1_L__SM_FILTER_SEL_OVERRIDE___S 16 +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_1_L__EN_FLAT_CHANNEL_CHECK___M 0x00000100 +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_1_L__EN_FLAT_CHANNEL_CHECK___S 8 +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_1_L__IS_FLAT_CHANNEL_THR___M 0x0000007F +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_1_L__IS_FLAT_CHANNEL_THR___S 0 +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_1_L___M 0x0003017F +#define PHYA_DEMFRONT_1_SCSR_CHE_CONTROL_1_L___S 0 + +#define PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_L (0x00500DB0) +#define PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_L__PRI80_IS_UPPER80___POR 0x0 +#define PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_L__PHYDBG_SYM_CNT___POR 0x00 +#define PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_L__DEBUGMUX_CTRL_1___POR 0x00 +#define PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_L__DEBUGMUX_CTRL_0___POR 0x00 +#define PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_L__PRI80_IS_UPPER80___M 0x01000000 +#define PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_L__PRI80_IS_UPPER80___S 24 +#define PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_L__PHYDBG_SYM_CNT___M 0x00FF0000 +#define PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_L__PHYDBG_SYM_CNT___S 16 +#define PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_L__DEBUGMUX_CTRL_1___M 0x0000FF00 +#define PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_L__DEBUGMUX_CTRL_1___S 8 +#define PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_L__DEBUGMUX_CTRL_0___M 0x000000FF +#define PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_L__DEBUGMUX_CTRL_0___S 0 +#define PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_L___M 0x01FFFFFF +#define PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_L___S 0 + +#define PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_U (0x00500DB4) +#define PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_U___RWC QCSR_REG_RO +#define PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_U___POR 0x00000000 +#define PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_U__DEMF_HW_STATUS___POR 0x00000000 +#define PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_U__DEMF_HW_STATUS___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_U__DEMF_HW_STATUS___S 0 +#define PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_U___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_SCSR_CDEBUGCONTROL_U___S 0 + +#define PHYA_DEMFRONT_1_DC_MEM_L_n(n) (0x00500DB8+0x8*(n)) +#define PHYA_DEMFRONT_1_DC_MEM_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_DC_MEM_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_DC_MEM_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_DC_MEM_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_DC_MEM_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_DC_MEM_L_n__DC_MEM_1___POR 0x0000 +#define PHYA_DEMFRONT_1_DC_MEM_L_n__DC_MEM_0___POR 0x0000 +#define PHYA_DEMFRONT_1_DC_MEM_L_n__DC_MEM_1___M 0xFFFF0000 +#define PHYA_DEMFRONT_1_DC_MEM_L_n__DC_MEM_1___S 16 +#define PHYA_DEMFRONT_1_DC_MEM_L_n__DC_MEM_0___M 0x0000FFFF +#define PHYA_DEMFRONT_1_DC_MEM_L_n__DC_MEM_0___S 0 +#define PHYA_DEMFRONT_1_DC_MEM_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_DC_MEM_L_n___S 0 +#define PHYA_DEMFRONT_1_DC_MEM_L_0 (0x00500DB8) +#define PHYA_DEMFRONT_1_DC_MEM_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_DC_MEM_L_0__DC_MEM_1___M 0xFFFF0000 +#define PHYA_DEMFRONT_1_DC_MEM_L_0__DC_MEM_1___S 16 +#define PHYA_DEMFRONT_1_DC_MEM_L_0__DC_MEM_0___M 0x0000FFFF +#define PHYA_DEMFRONT_1_DC_MEM_L_0__DC_MEM_0___S 0 + +#define PHYA_DEMFRONT_1_DC_MEM_U_n(n) (0x00500DBC+0x8*(n)) +#define PHYA_DEMFRONT_1_DC_MEM_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_DC_MEM_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_DC_MEM_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_DC_MEM_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_DC_MEM_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_DC_MEM_U_n__DC_MEM_3___POR 0x0000 +#define PHYA_DEMFRONT_1_DC_MEM_U_n__DC_MEM_2___POR 0x0000 +#define PHYA_DEMFRONT_1_DC_MEM_U_n__DC_MEM_3___M 0xFFFF0000 +#define PHYA_DEMFRONT_1_DC_MEM_U_n__DC_MEM_3___S 16 +#define PHYA_DEMFRONT_1_DC_MEM_U_n__DC_MEM_2___M 0x0000FFFF +#define PHYA_DEMFRONT_1_DC_MEM_U_n__DC_MEM_2___S 0 +#define PHYA_DEMFRONT_1_DC_MEM_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_DC_MEM_U_n___S 0 +#define PHYA_DEMFRONT_1_DC_MEM_U_0 (0x00500DBC) +#define PHYA_DEMFRONT_1_DC_MEM_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_DC_MEM_U_0__DC_MEM_3___M 0xFFFF0000 +#define PHYA_DEMFRONT_1_DC_MEM_U_0__DC_MEM_3___S 16 +#define PHYA_DEMFRONT_1_DC_MEM_U_0__DC_MEM_2___M 0x0000FFFF +#define PHYA_DEMFRONT_1_DC_MEM_U_0__DC_MEM_2___S 0 + +#define PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_L_n(n) (0x005015B8+0x8*(n)) +#define PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_L_n__R_MEM_CHN0_63_0_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_L_n__R_MEM_CHN0_63_0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_L_n__R_MEM_CHN0_63_0_0___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_L_n___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_L_0 (0x005015B8) +#define PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_L_0__R_MEM_CHN0_63_0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_L_0__R_MEM_CHN0_63_0_0___S 0 + +#define PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_U_n(n) (0x005015BC+0x8*(n)) +#define PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_U_n__R_MEM_CHN0_63_0_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_U_n__R_MEM_CHN0_63_0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_U_n__R_MEM_CHN0_63_0_1___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_U_n___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_U_0 (0x005015BC) +#define PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_U_0__R_MEM_CHN0_63_0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN0_63_0_U_0__R_MEM_CHN0_63_0_1___S 0 + +#define PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_L_n(n) (0x005035B8+0x8*(n)) +#define PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_L_n__R_MEM_CHN0_127_64_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_L_n__R_MEM_CHN0_127_64_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_L_n__R_MEM_CHN0_127_64_0___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_L_n___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_L_0 (0x005035B8) +#define PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_L_0__R_MEM_CHN0_127_64_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_L_0__R_MEM_CHN0_127_64_0___S 0 + +#define PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_U_n(n) (0x005035BC+0x8*(n)) +#define PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_U_n__R_MEM_CHN0_127_64_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_U_n__R_MEM_CHN0_127_64_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_U_n__R_MEM_CHN0_127_64_1___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_U_n___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_U_0 (0x005035BC) +#define PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_U_0__R_MEM_CHN0_127_64_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN0_127_64_U_0__R_MEM_CHN0_127_64_1___S 0 + +#define PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_L_n(n) (0x005055B8+0x8*(n)) +#define PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_L_n__R_MEM_CHN0_191_128_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_L_n__R_MEM_CHN0_191_128_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_L_n__R_MEM_CHN0_191_128_0___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_L_n___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_L_0 (0x005055B8) +#define PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_L_0__R_MEM_CHN0_191_128_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_L_0__R_MEM_CHN0_191_128_0___S 0 + +#define PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_U_n(n) (0x005055BC+0x8*(n)) +#define PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_U_n__R_MEM_CHN0_191_128_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_U_n__R_MEM_CHN0_191_128_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_U_n__R_MEM_CHN0_191_128_1___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_U_n___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_U_0 (0x005055BC) +#define PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_U_0__R_MEM_CHN0_191_128_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN0_191_128_U_0__R_MEM_CHN0_191_128_1___S 0 + +#define PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_L_n(n) (0x005075B8+0x8*(n)) +#define PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_L_n__R_MEM_CHN0_255_192_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_L_n__R_MEM_CHN0_255_192_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_L_n__R_MEM_CHN0_255_192_0___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_L_n___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_L_0 (0x005075B8) +#define PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_L_0__R_MEM_CHN0_255_192_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_L_0__R_MEM_CHN0_255_192_0___S 0 + +#define PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_U_n(n) (0x005075BC+0x8*(n)) +#define PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_U_n__R_MEM_CHN0_255_192_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_U_n__R_MEM_CHN0_255_192_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_U_n__R_MEM_CHN0_255_192_1___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_U_n___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_U_0 (0x005075BC) +#define PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_U_0__R_MEM_CHN0_255_192_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN0_255_192_U_0__R_MEM_CHN0_255_192_1___S 0 + +#define PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_L_n(n) (0x005095B8+0x8*(n)) +#define PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_L_n__R_MEM_CHN1_63_0_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_L_n__R_MEM_CHN1_63_0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_L_n__R_MEM_CHN1_63_0_0___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_L_n___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_L_0 (0x005095B8) +#define PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_L_0__R_MEM_CHN1_63_0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_L_0__R_MEM_CHN1_63_0_0___S 0 + +#define PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_U_n(n) (0x005095BC+0x8*(n)) +#define PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_U_n__R_MEM_CHN1_63_0_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_U_n__R_MEM_CHN1_63_0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_U_n__R_MEM_CHN1_63_0_1___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_U_n___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_U_0 (0x005095BC) +#define PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_U_0__R_MEM_CHN1_63_0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN1_63_0_U_0__R_MEM_CHN1_63_0_1___S 0 + +#define PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_L_n(n) (0x0050B5B8+0x8*(n)) +#define PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_L_n__R_MEM_CHN1_127_64_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_L_n__R_MEM_CHN1_127_64_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_L_n__R_MEM_CHN1_127_64_0___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_L_n___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_L_0 (0x0050B5B8) +#define PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_L_0__R_MEM_CHN1_127_64_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_L_0__R_MEM_CHN1_127_64_0___S 0 + +#define PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_U_n(n) (0x0050B5BC+0x8*(n)) +#define PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_U_n__R_MEM_CHN1_127_64_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_U_n__R_MEM_CHN1_127_64_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_U_n__R_MEM_CHN1_127_64_1___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_U_n___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_U_0 (0x0050B5BC) +#define PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_U_0__R_MEM_CHN1_127_64_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN1_127_64_U_0__R_MEM_CHN1_127_64_1___S 0 + +#define PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_L_n(n) (0x0050D5B8+0x8*(n)) +#define PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_L_n__R_MEM_CHN1_191_128_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_L_n__R_MEM_CHN1_191_128_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_L_n__R_MEM_CHN1_191_128_0___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_L_n___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_L_0 (0x0050D5B8) +#define PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_L_0__R_MEM_CHN1_191_128_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_L_0__R_MEM_CHN1_191_128_0___S 0 + +#define PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_U_n(n) (0x0050D5BC+0x8*(n)) +#define PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_U_n__R_MEM_CHN1_191_128_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_U_n__R_MEM_CHN1_191_128_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_U_n__R_MEM_CHN1_191_128_1___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_U_n___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_U_0 (0x0050D5BC) +#define PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_U_0__R_MEM_CHN1_191_128_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN1_191_128_U_0__R_MEM_CHN1_191_128_1___S 0 + +#define PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_L_n(n) (0x0050F5B8+0x8*(n)) +#define PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_L_n__R_MEM_CHN1_255_192_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_L_n__R_MEM_CHN1_255_192_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_L_n__R_MEM_CHN1_255_192_0___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_L_n___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_L_0 (0x0050F5B8) +#define PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_L_0__R_MEM_CHN1_255_192_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_L_0__R_MEM_CHN1_255_192_0___S 0 + +#define PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_U_n(n) (0x0050F5BC+0x8*(n)) +#define PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_U_n__R_MEM_CHN1_255_192_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_U_n__R_MEM_CHN1_255_192_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_U_n__R_MEM_CHN1_255_192_1___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_U_n___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_U_0 (0x0050F5BC) +#define PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_U_0__R_MEM_CHN1_255_192_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN1_255_192_U_0__R_MEM_CHN1_255_192_1___S 0 + +#define PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_L_n(n) (0x005115B8+0x8*(n)) +#define PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_L_n__R_MEM_CHN2_63_0_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_L_n__R_MEM_CHN2_63_0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_L_n__R_MEM_CHN2_63_0_0___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_L_n___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_L_0 (0x005115B8) +#define PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_L_0__R_MEM_CHN2_63_0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_L_0__R_MEM_CHN2_63_0_0___S 0 + +#define PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_U_n(n) (0x005115BC+0x8*(n)) +#define PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_U_n__R_MEM_CHN2_63_0_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_U_n__R_MEM_CHN2_63_0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_U_n__R_MEM_CHN2_63_0_1___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_U_n___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_U_0 (0x005115BC) +#define PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_U_0__R_MEM_CHN2_63_0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN2_63_0_U_0__R_MEM_CHN2_63_0_1___S 0 + +#define PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_L_n(n) (0x005135B8+0x8*(n)) +#define PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_L_n__R_MEM_CHN2_127_64_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_L_n__R_MEM_CHN2_127_64_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_L_n__R_MEM_CHN2_127_64_0___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_L_n___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_L_0 (0x005135B8) +#define PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_L_0__R_MEM_CHN2_127_64_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_L_0__R_MEM_CHN2_127_64_0___S 0 + +#define PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_U_n(n) (0x005135BC+0x8*(n)) +#define PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_U_n__R_MEM_CHN2_127_64_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_U_n__R_MEM_CHN2_127_64_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_U_n__R_MEM_CHN2_127_64_1___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_U_n___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_U_0 (0x005135BC) +#define PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_U_0__R_MEM_CHN2_127_64_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN2_127_64_U_0__R_MEM_CHN2_127_64_1___S 0 + +#define PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_L_n(n) (0x005155B8+0x8*(n)) +#define PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_L_n__R_MEM_CHN2_191_128_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_L_n__R_MEM_CHN2_191_128_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_L_n__R_MEM_CHN2_191_128_0___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_L_n___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_L_0 (0x005155B8) +#define PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_L_0__R_MEM_CHN2_191_128_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_L_0__R_MEM_CHN2_191_128_0___S 0 + +#define PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_U_n(n) (0x005155BC+0x8*(n)) +#define PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_U_n__R_MEM_CHN2_191_128_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_U_n__R_MEM_CHN2_191_128_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_U_n__R_MEM_CHN2_191_128_1___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_U_n___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_U_0 (0x005155BC) +#define PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_U_0__R_MEM_CHN2_191_128_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN2_191_128_U_0__R_MEM_CHN2_191_128_1___S 0 + +#define PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_L_n(n) (0x005175B8+0x8*(n)) +#define PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_L_n__R_MEM_CHN2_255_192_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_L_n__R_MEM_CHN2_255_192_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_L_n__R_MEM_CHN2_255_192_0___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_L_n___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_L_0 (0x005175B8) +#define PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_L_0__R_MEM_CHN2_255_192_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_L_0__R_MEM_CHN2_255_192_0___S 0 + +#define PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_U_n(n) (0x005175BC+0x8*(n)) +#define PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_U_n__R_MEM_CHN2_255_192_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_U_n__R_MEM_CHN2_255_192_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_U_n__R_MEM_CHN2_255_192_1___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_U_n___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_U_0 (0x005175BC) +#define PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_U_0__R_MEM_CHN2_255_192_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN2_255_192_U_0__R_MEM_CHN2_255_192_1___S 0 + +#define PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_L_n(n) (0x005195B8+0x8*(n)) +#define PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_L_n__R_MEM_CHN3_63_0_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_L_n__R_MEM_CHN3_63_0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_L_n__R_MEM_CHN3_63_0_0___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_L_n___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_L_0 (0x005195B8) +#define PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_L_0__R_MEM_CHN3_63_0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_L_0__R_MEM_CHN3_63_0_0___S 0 + +#define PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_U_n(n) (0x005195BC+0x8*(n)) +#define PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_U_n__R_MEM_CHN3_63_0_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_U_n__R_MEM_CHN3_63_0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_U_n__R_MEM_CHN3_63_0_1___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_U_n___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_U_0 (0x005195BC) +#define PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_U_0__R_MEM_CHN3_63_0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN3_63_0_U_0__R_MEM_CHN3_63_0_1___S 0 + +#define PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_L_n(n) (0x0051B5B8+0x8*(n)) +#define PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_L_n__R_MEM_CHN3_127_64_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_L_n__R_MEM_CHN3_127_64_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_L_n__R_MEM_CHN3_127_64_0___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_L_n___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_L_0 (0x0051B5B8) +#define PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_L_0__R_MEM_CHN3_127_64_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_L_0__R_MEM_CHN3_127_64_0___S 0 + +#define PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_U_n(n) (0x0051B5BC+0x8*(n)) +#define PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_U_n__R_MEM_CHN3_127_64_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_U_n__R_MEM_CHN3_127_64_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_U_n__R_MEM_CHN3_127_64_1___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_U_n___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_U_0 (0x0051B5BC) +#define PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_U_0__R_MEM_CHN3_127_64_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN3_127_64_U_0__R_MEM_CHN3_127_64_1___S 0 + +#define PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_L_n(n) (0x0051D5B8+0x8*(n)) +#define PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_L_n__R_MEM_CHN3_191_128_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_L_n__R_MEM_CHN3_191_128_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_L_n__R_MEM_CHN3_191_128_0___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_L_n___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_L_0 (0x0051D5B8) +#define PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_L_0__R_MEM_CHN3_191_128_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_L_0__R_MEM_CHN3_191_128_0___S 0 + +#define PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_U_n(n) (0x0051D5BC+0x8*(n)) +#define PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_U_n__R_MEM_CHN3_191_128_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_U_n__R_MEM_CHN3_191_128_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_U_n__R_MEM_CHN3_191_128_1___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_U_n___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_U_0 (0x0051D5BC) +#define PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_U_0__R_MEM_CHN3_191_128_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN3_191_128_U_0__R_MEM_CHN3_191_128_1___S 0 + +#define PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_L_n(n) (0x0051F5B8+0x8*(n)) +#define PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_L_n__R_MEM_CHN3_255_192_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_L_n__R_MEM_CHN3_255_192_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_L_n__R_MEM_CHN3_255_192_0___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_L_n___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_L_0 (0x0051F5B8) +#define PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_L_0__R_MEM_CHN3_255_192_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_L_0__R_MEM_CHN3_255_192_0___S 0 + +#define PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_U_n(n) (0x0051F5BC+0x8*(n)) +#define PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_U_n__R_MEM_CHN3_255_192_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_U_n__R_MEM_CHN3_255_192_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_U_n__R_MEM_CHN3_255_192_1___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_U_n___S 0 +#define PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_U_0 (0x0051F5BC) +#define PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_U_0__R_MEM_CHN3_255_192_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_R_MEM_CHN3_255_192_U_0__R_MEM_CHN3_255_192_1___S 0 + +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_L_n(n) (0x005215B8+0x8*(n)) +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_L_n__Q_MEM_CHN0_63_0_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_L_n__Q_MEM_CHN0_63_0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_L_n__Q_MEM_CHN0_63_0_0___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_L_n___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_L_0 (0x005215B8) +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_L_0__Q_MEM_CHN0_63_0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_L_0__Q_MEM_CHN0_63_0_0___S 0 + +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_U_n(n) (0x005215BC+0x8*(n)) +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_U_n__Q_MEM_CHN0_63_0_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_U_n__Q_MEM_CHN0_63_0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_U_n__Q_MEM_CHN0_63_0_1___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_U_n___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_U_0 (0x005215BC) +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_U_0__Q_MEM_CHN0_63_0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_63_0_U_0__Q_MEM_CHN0_63_0_1___S 0 + +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_L_n(n) (0x005235B8+0x8*(n)) +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_L_n__Q_MEM_CHN0_127_64_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_L_n__Q_MEM_CHN0_127_64_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_L_n__Q_MEM_CHN0_127_64_0___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_L_n___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_L_0 (0x005235B8) +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_L_0__Q_MEM_CHN0_127_64_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_L_0__Q_MEM_CHN0_127_64_0___S 0 + +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_U_n(n) (0x005235BC+0x8*(n)) +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_U_n__Q_MEM_CHN0_127_64_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_U_n__Q_MEM_CHN0_127_64_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_U_n__Q_MEM_CHN0_127_64_1___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_U_n___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_U_0 (0x005235BC) +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_U_0__Q_MEM_CHN0_127_64_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_127_64_U_0__Q_MEM_CHN0_127_64_1___S 0 + +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_L_n(n) (0x005255B8+0x8*(n)) +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_L_n__Q_MEM_CHN0_191_128_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_L_n__Q_MEM_CHN0_191_128_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_L_n__Q_MEM_CHN0_191_128_0___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_L_n___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_L_0 (0x005255B8) +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_L_0__Q_MEM_CHN0_191_128_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_L_0__Q_MEM_CHN0_191_128_0___S 0 + +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_U_n(n) (0x005255BC+0x8*(n)) +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_U_n__Q_MEM_CHN0_191_128_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_U_n__Q_MEM_CHN0_191_128_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_U_n__Q_MEM_CHN0_191_128_1___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_U_n___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_U_0 (0x005255BC) +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_U_0__Q_MEM_CHN0_191_128_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN0_191_128_U_0__Q_MEM_CHN0_191_128_1___S 0 + +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_L_n(n) (0x005275B8+0x8*(n)) +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_L_n__Q_MEM_CHN1_63_0_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_L_n__Q_MEM_CHN1_63_0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_L_n__Q_MEM_CHN1_63_0_0___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_L_n___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_L_0 (0x005275B8) +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_L_0__Q_MEM_CHN1_63_0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_L_0__Q_MEM_CHN1_63_0_0___S 0 + +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_U_n(n) (0x005275BC+0x8*(n)) +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_U_n__Q_MEM_CHN1_63_0_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_U_n__Q_MEM_CHN1_63_0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_U_n__Q_MEM_CHN1_63_0_1___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_U_n___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_U_0 (0x005275BC) +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_U_0__Q_MEM_CHN1_63_0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_63_0_U_0__Q_MEM_CHN1_63_0_1___S 0 + +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_L_n(n) (0x005295B8+0x8*(n)) +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_L_n__Q_MEM_CHN1_127_64_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_L_n__Q_MEM_CHN1_127_64_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_L_n__Q_MEM_CHN1_127_64_0___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_L_n___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_L_0 (0x005295B8) +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_L_0__Q_MEM_CHN1_127_64_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_L_0__Q_MEM_CHN1_127_64_0___S 0 + +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_U_n(n) (0x005295BC+0x8*(n)) +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_U_n__Q_MEM_CHN1_127_64_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_U_n__Q_MEM_CHN1_127_64_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_U_n__Q_MEM_CHN1_127_64_1___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_U_n___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_U_0 (0x005295BC) +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_U_0__Q_MEM_CHN1_127_64_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_127_64_U_0__Q_MEM_CHN1_127_64_1___S 0 + +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_L_n(n) (0x0052B5B8+0x8*(n)) +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_L_n__Q_MEM_CHN1_191_128_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_L_n__Q_MEM_CHN1_191_128_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_L_n__Q_MEM_CHN1_191_128_0___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_L_n___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_L_0 (0x0052B5B8) +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_L_0__Q_MEM_CHN1_191_128_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_L_0__Q_MEM_CHN1_191_128_0___S 0 + +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_U_n(n) (0x0052B5BC+0x8*(n)) +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_U_n__Q_MEM_CHN1_191_128_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_U_n__Q_MEM_CHN1_191_128_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_U_n__Q_MEM_CHN1_191_128_1___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_U_n___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_U_0 (0x0052B5BC) +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_U_0__Q_MEM_CHN1_191_128_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN1_191_128_U_0__Q_MEM_CHN1_191_128_1___S 0 + +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_L_n(n) (0x0052D5B8+0x8*(n)) +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_L_n__Q_MEM_CHN2_63_0_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_L_n__Q_MEM_CHN2_63_0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_L_n__Q_MEM_CHN2_63_0_0___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_L_n___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_L_0 (0x0052D5B8) +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_L_0__Q_MEM_CHN2_63_0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_L_0__Q_MEM_CHN2_63_0_0___S 0 + +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_U_n(n) (0x0052D5BC+0x8*(n)) +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_U_n__Q_MEM_CHN2_63_0_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_U_n__Q_MEM_CHN2_63_0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_U_n__Q_MEM_CHN2_63_0_1___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_U_n___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_U_0 (0x0052D5BC) +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_U_0__Q_MEM_CHN2_63_0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_63_0_U_0__Q_MEM_CHN2_63_0_1___S 0 + +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_L_n(n) (0x0052F5B8+0x8*(n)) +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_L_n__Q_MEM_CHN2_127_64_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_L_n__Q_MEM_CHN2_127_64_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_L_n__Q_MEM_CHN2_127_64_0___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_L_n___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_L_0 (0x0052F5B8) +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_L_0__Q_MEM_CHN2_127_64_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_L_0__Q_MEM_CHN2_127_64_0___S 0 + +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_U_n(n) (0x0052F5BC+0x8*(n)) +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_U_n__Q_MEM_CHN2_127_64_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_U_n__Q_MEM_CHN2_127_64_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_U_n__Q_MEM_CHN2_127_64_1___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_U_n___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_U_0 (0x0052F5BC) +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_U_0__Q_MEM_CHN2_127_64_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_127_64_U_0__Q_MEM_CHN2_127_64_1___S 0 + +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_L_n(n) (0x005315B8+0x8*(n)) +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_L_n__Q_MEM_CHN2_191_128_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_L_n__Q_MEM_CHN2_191_128_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_L_n__Q_MEM_CHN2_191_128_0___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_L_n___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_L_0 (0x005315B8) +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_L_0__Q_MEM_CHN2_191_128_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_L_0__Q_MEM_CHN2_191_128_0___S 0 + +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_U_n(n) (0x005315BC+0x8*(n)) +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_U_n__Q_MEM_CHN2_191_128_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_U_n__Q_MEM_CHN2_191_128_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_U_n__Q_MEM_CHN2_191_128_1___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_U_n___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_U_0 (0x005315BC) +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_U_0__Q_MEM_CHN2_191_128_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN2_191_128_U_0__Q_MEM_CHN2_191_128_1___S 0 + +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_L_n(n) (0x005335B8+0x8*(n)) +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_L_n__Q_MEM_CHN3_63_0_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_L_n__Q_MEM_CHN3_63_0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_L_n__Q_MEM_CHN3_63_0_0___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_L_n___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_L_0 (0x005335B8) +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_L_0__Q_MEM_CHN3_63_0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_L_0__Q_MEM_CHN3_63_0_0___S 0 + +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_U_n(n) (0x005335BC+0x8*(n)) +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_U_n__Q_MEM_CHN3_63_0_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_U_n__Q_MEM_CHN3_63_0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_U_n__Q_MEM_CHN3_63_0_1___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_U_n___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_U_0 (0x005335BC) +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_U_0__Q_MEM_CHN3_63_0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_63_0_U_0__Q_MEM_CHN3_63_0_1___S 0 + +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_L_n(n) (0x005355B8+0x8*(n)) +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_L_n__Q_MEM_CHN3_127_64_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_L_n__Q_MEM_CHN3_127_64_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_L_n__Q_MEM_CHN3_127_64_0___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_L_n___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_L_0 (0x005355B8) +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_L_0__Q_MEM_CHN3_127_64_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_L_0__Q_MEM_CHN3_127_64_0___S 0 + +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_U_n(n) (0x005355BC+0x8*(n)) +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_U_n__Q_MEM_CHN3_127_64_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_U_n__Q_MEM_CHN3_127_64_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_U_n__Q_MEM_CHN3_127_64_1___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_U_n___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_U_0 (0x005355BC) +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_U_0__Q_MEM_CHN3_127_64_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_127_64_U_0__Q_MEM_CHN3_127_64_1___S 0 + +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_L_n(n) (0x005375B8+0x8*(n)) +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_L_n__Q_MEM_CHN3_191_128_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_L_n__Q_MEM_CHN3_191_128_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_L_n__Q_MEM_CHN3_191_128_0___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_L_n___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_L_0 (0x005375B8) +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_L_0__Q_MEM_CHN3_191_128_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_L_0__Q_MEM_CHN3_191_128_0___S 0 + +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_U_n(n) (0x005375BC+0x8*(n)) +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_U_n__Q_MEM_CHN3_191_128_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_U_n__Q_MEM_CHN3_191_128_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_U_n__Q_MEM_CHN3_191_128_1___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_U_n___S 0 +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_U_0 (0x005375BC) +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_U_0__Q_MEM_CHN3_191_128_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_Q_MEM_CHN3_191_128_U_0__Q_MEM_CHN3_191_128_1___S 0 + +#define PHYA_DEMFRONT_1_CV_IDM_RXMEM0_ADDR_L (0x005395D0) +#define PHYA_DEMFRONT_1_CV_IDM_RXMEM0_ADDR_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CV_IDM_RXMEM0_ADDR_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_IDM_RXMEM0_ADDR_L__CV_IDM_RXMEM0_ADDR___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_IDM_RXMEM0_ADDR_L__CV_IDM_RXMEM0_ADDR___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_IDM_RXMEM0_ADDR_L__CV_IDM_RXMEM0_ADDR___S 0 +#define PHYA_DEMFRONT_1_CV_IDM_RXMEM0_ADDR_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_IDM_RXMEM0_ADDR_L___S 0 + +#define PHYA_DEMFRONT_1_CV_IDM_RXMEM1_ADDR_L (0x005395D8) +#define PHYA_DEMFRONT_1_CV_IDM_RXMEM1_ADDR_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CV_IDM_RXMEM1_ADDR_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_IDM_RXMEM1_ADDR_L__CV_IDM_RXMEM1_ADDR___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_IDM_RXMEM1_ADDR_L__CV_IDM_RXMEM1_ADDR___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_IDM_RXMEM1_ADDR_L__CV_IDM_RXMEM1_ADDR___S 0 +#define PHYA_DEMFRONT_1_CV_IDM_RXMEM1_ADDR_L___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_IDM_RXMEM1_ADDR_L___S 0 + +#define PHYA_DEMFRONT_1_CV_RXMEM0_S0_L_n(n) (0x005415E0+0x8*(n)) +#define PHYA_DEMFRONT_1_CV_RXMEM0_S0_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S0_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S0_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S0_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CV_RXMEM0_S0_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S0_L_n__CV_RXMEM0_S0_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S0_L_n__CV_RXMEM0_S0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM0_S0_L_n__CV_RXMEM0_S0_0___S 0 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S0_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM0_S0_L_n___S 0 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S0_L_0 (0x005415E0) +#define PHYA_DEMFRONT_1_CV_RXMEM0_S0_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CV_RXMEM0_S0_L_0__CV_RXMEM0_S0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM0_S0_L_0__CV_RXMEM0_S0_0___S 0 + +#define PHYA_DEMFRONT_1_CV_RXMEM0_S0_U_n(n) (0x005415E4+0x8*(n)) +#define PHYA_DEMFRONT_1_CV_RXMEM0_S0_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S0_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S0_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S0_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CV_RXMEM0_S0_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S0_U_n__CV_RXMEM0_S0_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S0_U_n__CV_RXMEM0_S0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM0_S0_U_n__CV_RXMEM0_S0_1___S 0 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S0_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM0_S0_U_n___S 0 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S0_U_0 (0x005415E4) +#define PHYA_DEMFRONT_1_CV_RXMEM0_S0_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CV_RXMEM0_S0_U_0__CV_RXMEM0_S0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM0_S0_U_0__CV_RXMEM0_S0_1___S 0 + +#define PHYA_DEMFRONT_1_CV_RXMEM0_S1_L_n(n) (0x005435E0+0x8*(n)) +#define PHYA_DEMFRONT_1_CV_RXMEM0_S1_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S1_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S1_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S1_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CV_RXMEM0_S1_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S1_L_n__CV_RXMEM0_S1_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S1_L_n__CV_RXMEM0_S1_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM0_S1_L_n__CV_RXMEM0_S1_0___S 0 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S1_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM0_S1_L_n___S 0 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S1_L_0 (0x005435E0) +#define PHYA_DEMFRONT_1_CV_RXMEM0_S1_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CV_RXMEM0_S1_L_0__CV_RXMEM0_S1_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM0_S1_L_0__CV_RXMEM0_S1_0___S 0 + +#define PHYA_DEMFRONT_1_CV_RXMEM0_S1_U_n(n) (0x005435E4+0x8*(n)) +#define PHYA_DEMFRONT_1_CV_RXMEM0_S1_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S1_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S1_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S1_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CV_RXMEM0_S1_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S1_U_n__CV_RXMEM0_S1_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S1_U_n__CV_RXMEM0_S1_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM0_S1_U_n__CV_RXMEM0_S1_1___S 0 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S1_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM0_S1_U_n___S 0 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S1_U_0 (0x005435E4) +#define PHYA_DEMFRONT_1_CV_RXMEM0_S1_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CV_RXMEM0_S1_U_0__CV_RXMEM0_S1_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM0_S1_U_0__CV_RXMEM0_S1_1___S 0 + +#define PHYA_DEMFRONT_1_CV_RXMEM0_S2_L_n(n) (0x005455E0+0x8*(n)) +#define PHYA_DEMFRONT_1_CV_RXMEM0_S2_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S2_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S2_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S2_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CV_RXMEM0_S2_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S2_L_n__CV_RXMEM0_S2_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S2_L_n__CV_RXMEM0_S2_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM0_S2_L_n__CV_RXMEM0_S2_0___S 0 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S2_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM0_S2_L_n___S 0 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S2_L_0 (0x005455E0) +#define PHYA_DEMFRONT_1_CV_RXMEM0_S2_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CV_RXMEM0_S2_L_0__CV_RXMEM0_S2_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM0_S2_L_0__CV_RXMEM0_S2_0___S 0 + +#define PHYA_DEMFRONT_1_CV_RXMEM0_S2_U_n(n) (0x005455E4+0x8*(n)) +#define PHYA_DEMFRONT_1_CV_RXMEM0_S2_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S2_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S2_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S2_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CV_RXMEM0_S2_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S2_U_n__CV_RXMEM0_S2_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S2_U_n__CV_RXMEM0_S2_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM0_S2_U_n__CV_RXMEM0_S2_1___S 0 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S2_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM0_S2_U_n___S 0 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S2_U_0 (0x005455E4) +#define PHYA_DEMFRONT_1_CV_RXMEM0_S2_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CV_RXMEM0_S2_U_0__CV_RXMEM0_S2_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM0_S2_U_0__CV_RXMEM0_S2_1___S 0 + +#define PHYA_DEMFRONT_1_CV_RXMEM0_S3_L_n(n) (0x005475E0+0x8*(n)) +#define PHYA_DEMFRONT_1_CV_RXMEM0_S3_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S3_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S3_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S3_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CV_RXMEM0_S3_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S3_L_n__CV_RXMEM0_S3_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S3_L_n__CV_RXMEM0_S3_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM0_S3_L_n__CV_RXMEM0_S3_0___S 0 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S3_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM0_S3_L_n___S 0 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S3_L_0 (0x005475E0) +#define PHYA_DEMFRONT_1_CV_RXMEM0_S3_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CV_RXMEM0_S3_L_0__CV_RXMEM0_S3_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM0_S3_L_0__CV_RXMEM0_S3_0___S 0 + +#define PHYA_DEMFRONT_1_CV_RXMEM0_S3_U_n(n) (0x005475E4+0x8*(n)) +#define PHYA_DEMFRONT_1_CV_RXMEM0_S3_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S3_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S3_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S3_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CV_RXMEM0_S3_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S3_U_n__CV_RXMEM0_S3_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S3_U_n__CV_RXMEM0_S3_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM0_S3_U_n__CV_RXMEM0_S3_1___S 0 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S3_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM0_S3_U_n___S 0 +#define PHYA_DEMFRONT_1_CV_RXMEM0_S3_U_0 (0x005475E4) +#define PHYA_DEMFRONT_1_CV_RXMEM0_S3_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CV_RXMEM0_S3_U_0__CV_RXMEM0_S3_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM0_S3_U_0__CV_RXMEM0_S3_1___S 0 + +#define PHYA_DEMFRONT_1_CV_RXMEM1_S0_L_n(n) (0x005495E0+0x8*(n)) +#define PHYA_DEMFRONT_1_CV_RXMEM1_S0_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S0_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S0_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S0_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CV_RXMEM1_S0_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S0_L_n__CV_RXMEM1_S0_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S0_L_n__CV_RXMEM1_S0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM1_S0_L_n__CV_RXMEM1_S0_0___S 0 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S0_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM1_S0_L_n___S 0 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S0_L_0 (0x005495E0) +#define PHYA_DEMFRONT_1_CV_RXMEM1_S0_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CV_RXMEM1_S0_L_0__CV_RXMEM1_S0_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM1_S0_L_0__CV_RXMEM1_S0_0___S 0 + +#define PHYA_DEMFRONT_1_CV_RXMEM1_S0_U_n(n) (0x005495E4+0x8*(n)) +#define PHYA_DEMFRONT_1_CV_RXMEM1_S0_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S0_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S0_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S0_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CV_RXMEM1_S0_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S0_U_n__CV_RXMEM1_S0_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S0_U_n__CV_RXMEM1_S0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM1_S0_U_n__CV_RXMEM1_S0_1___S 0 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S0_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM1_S0_U_n___S 0 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S0_U_0 (0x005495E4) +#define PHYA_DEMFRONT_1_CV_RXMEM1_S0_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CV_RXMEM1_S0_U_0__CV_RXMEM1_S0_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM1_S0_U_0__CV_RXMEM1_S0_1___S 0 + +#define PHYA_DEMFRONT_1_CV_RXMEM1_S1_L_n(n) (0x0054B5E0+0x8*(n)) +#define PHYA_DEMFRONT_1_CV_RXMEM1_S1_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S1_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S1_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S1_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CV_RXMEM1_S1_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S1_L_n__CV_RXMEM1_S1_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S1_L_n__CV_RXMEM1_S1_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM1_S1_L_n__CV_RXMEM1_S1_0___S 0 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S1_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM1_S1_L_n___S 0 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S1_L_0 (0x0054B5E0) +#define PHYA_DEMFRONT_1_CV_RXMEM1_S1_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CV_RXMEM1_S1_L_0__CV_RXMEM1_S1_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM1_S1_L_0__CV_RXMEM1_S1_0___S 0 + +#define PHYA_DEMFRONT_1_CV_RXMEM1_S1_U_n(n) (0x0054B5E4+0x8*(n)) +#define PHYA_DEMFRONT_1_CV_RXMEM1_S1_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S1_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S1_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S1_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CV_RXMEM1_S1_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S1_U_n__CV_RXMEM1_S1_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S1_U_n__CV_RXMEM1_S1_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM1_S1_U_n__CV_RXMEM1_S1_1___S 0 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S1_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM1_S1_U_n___S 0 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S1_U_0 (0x0054B5E4) +#define PHYA_DEMFRONT_1_CV_RXMEM1_S1_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CV_RXMEM1_S1_U_0__CV_RXMEM1_S1_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM1_S1_U_0__CV_RXMEM1_S1_1___S 0 + +#define PHYA_DEMFRONT_1_CV_RXMEM1_S2_L_n(n) (0x0054D5E0+0x8*(n)) +#define PHYA_DEMFRONT_1_CV_RXMEM1_S2_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S2_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S2_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S2_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CV_RXMEM1_S2_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S2_L_n__CV_RXMEM1_S2_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S2_L_n__CV_RXMEM1_S2_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM1_S2_L_n__CV_RXMEM1_S2_0___S 0 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S2_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM1_S2_L_n___S 0 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S2_L_0 (0x0054D5E0) +#define PHYA_DEMFRONT_1_CV_RXMEM1_S2_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CV_RXMEM1_S2_L_0__CV_RXMEM1_S2_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM1_S2_L_0__CV_RXMEM1_S2_0___S 0 + +#define PHYA_DEMFRONT_1_CV_RXMEM1_S2_U_n(n) (0x0054D5E4+0x8*(n)) +#define PHYA_DEMFRONT_1_CV_RXMEM1_S2_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S2_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S2_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S2_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CV_RXMEM1_S2_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S2_U_n__CV_RXMEM1_S2_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S2_U_n__CV_RXMEM1_S2_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM1_S2_U_n__CV_RXMEM1_S2_1___S 0 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S2_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM1_S2_U_n___S 0 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S2_U_0 (0x0054D5E4) +#define PHYA_DEMFRONT_1_CV_RXMEM1_S2_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CV_RXMEM1_S2_U_0__CV_RXMEM1_S2_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM1_S2_U_0__CV_RXMEM1_S2_1___S 0 + +#define PHYA_DEMFRONT_1_CV_RXMEM1_S3_L_n(n) (0x0054F5E0+0x8*(n)) +#define PHYA_DEMFRONT_1_CV_RXMEM1_S3_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S3_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S3_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S3_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CV_RXMEM1_S3_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S3_L_n__CV_RXMEM1_S3_0___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S3_L_n__CV_RXMEM1_S3_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM1_S3_L_n__CV_RXMEM1_S3_0___S 0 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S3_L_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM1_S3_L_n___S 0 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S3_L_0 (0x0054F5E0) +#define PHYA_DEMFRONT_1_CV_RXMEM1_S3_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CV_RXMEM1_S3_L_0__CV_RXMEM1_S3_0___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM1_S3_L_0__CV_RXMEM1_S3_0___S 0 + +#define PHYA_DEMFRONT_1_CV_RXMEM1_S3_U_n(n) (0x0054F5E4+0x8*(n)) +#define PHYA_DEMFRONT_1_CV_RXMEM1_S3_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S3_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S3_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S3_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CV_RXMEM1_S3_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S3_U_n__CV_RXMEM1_S3_1___POR 0x00000000 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S3_U_n__CV_RXMEM1_S3_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM1_S3_U_n__CV_RXMEM1_S3_1___S 0 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S3_U_n___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM1_S3_U_n___S 0 +#define PHYA_DEMFRONT_1_CV_RXMEM1_S3_U_0 (0x0054F5E4) +#define PHYA_DEMFRONT_1_CV_RXMEM1_S3_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_CV_RXMEM1_S3_U_0__CV_RXMEM1_S3_1___M 0xFFFFFFFF +#define PHYA_DEMFRONT_1_CV_RXMEM1_S3_U_0__CV_RXMEM1_S3_1___S 0 + +#define PHYA_DEMFRONT_1_NPR_PHYB_CFG_L (0x005615E0) +#define PHYA_DEMFRONT_1_NPR_PHYB_CFG_L___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_NPR_PHYB_CFG_L___POR 0x00000000 +#define PHYA_DEMFRONT_1_NPR_PHYB_CFG_L__WFAX_DEMF_CSR_11AX_1X1_80___POR 0x0 +#define PHYA_DEMFRONT_1_NPR_PHYB_CFG_L__WFAX_DEMF_CSR_11AX_1X1_80___M 0x00000001 +#define PHYA_DEMFRONT_1_NPR_PHYB_CFG_L__WFAX_DEMF_CSR_11AX_1X1_80___S 0 +#define PHYA_DEMFRONT_1_NPR_PHYB_CFG_L___M 0x00000001 +#define PHYA_DEMFRONT_1_NPR_PHYB_CFG_L___S 0 + +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN0_L_n(n) (0x005615E8+0x8*(n)) +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN0_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN0_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN0_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN0_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN0_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN0_L_n__PILOT_MEM_CHN0_0___POR 0x0000000 +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN0_L_n__PILOT_MEM_CHN0_0___M 0x0FFFFFFF +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN0_L_n__PILOT_MEM_CHN0_0___S 0 +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN0_L_n___M 0x0FFFFFFF +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN0_L_n___S 0 +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN0_L_0 (0x005615E8) +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN0_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN0_L_0__PILOT_MEM_CHN0_0___M 0x0FFFFFFF +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN0_L_0__PILOT_MEM_CHN0_0___S 0 + +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN0_U_n(n) (0x005615EC+0x8*(n)) +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN0_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN0_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN0_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN0_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN0_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN0_U_n__PILOT_MEM_CHN0_1___POR 0x0000000 +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN0_U_n__PILOT_MEM_CHN0_1___M 0x0FFFFFFF +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN0_U_n__PILOT_MEM_CHN0_1___S 0 +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN0_U_n___M 0x0FFFFFFF +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN0_U_n___S 0 +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN0_U_0 (0x005615EC) +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN0_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN0_U_0__PILOT_MEM_CHN0_1___M 0x0FFFFFFF +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN0_U_0__PILOT_MEM_CHN0_1___S 0 + +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN1_L_n(n) (0x00561868+0x8*(n)) +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN1_L_n_nMIN 0 +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN1_L_n_nMAX 0 +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN1_L_n_ELEM 1 +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN1_L_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN1_L_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN1_L_n__PILOT_MEM_CHN1_0___POR 0x0000000 +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN1_L_n__PILOT_MEM_CHN1_0___M 0x0FFFFFFF +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN1_L_n__PILOT_MEM_CHN1_0___S 0 +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN1_L_n___M 0x0FFFFFFF +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN1_L_n___S 0 +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN1_L_0 (0x00561868) +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN1_L_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN1_L_0__PILOT_MEM_CHN1_0___M 0x0FFFFFFF +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN1_L_0__PILOT_MEM_CHN1_0___S 0 + +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN1_U_n(n) (0x0056186C+0x8*(n)) +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN1_U_n_nMIN 0 +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN1_U_n_nMAX 0 +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN1_U_n_ELEM 1 +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN1_U_n___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN1_U_n___POR 0x00000000 +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN1_U_n__PILOT_MEM_CHN1_1___POR 0x0000000 +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN1_U_n__PILOT_MEM_CHN1_1___M 0x0FFFFFFF +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN1_U_n__PILOT_MEM_CHN1_1___S 0 +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN1_U_n___M 0x0FFFFFFF +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN1_U_n___S 0 +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN1_U_0 (0x0056186C) +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN1_U_0___RWC QCSR_REG_RW +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN1_U_0__PILOT_MEM_CHN1_1___M 0x0FFFFFFF +#define PHYA_DEMFRONT_1_PILOT_MEM_CHN1_U_0__PILOT_MEM_CHN1_1___S 0 + +#define PHYA_IRON2G_RFA_WSI_SYSCTRL (0x005CF000) +#define PHYA_IRON2G_RFA_WSI_SYSCTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_SYSCTRL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_SYSCTRL__CLR_RESET_MASK___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_SYSCTRL__SET_RESET_MASK___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_SYSCTRL__SW_CHIP_RESET_WSI___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_SYSCTRL__CM_SW_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_SYSCTRL__WL_SW_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_SYSCTRL__CLR_RESET_MASK___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_SYSCTRL__CLR_RESET_MASK___S 11 +#define PHYA_IRON2G_RFA_WSI_SYSCTRL__SET_RESET_MASK___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_SYSCTRL__SET_RESET_MASK___S 10 +#define PHYA_IRON2G_RFA_WSI_SYSCTRL__SW_CHIP_RESET_WSI___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_SYSCTRL__SW_CHIP_RESET_WSI___S 2 +#define PHYA_IRON2G_RFA_WSI_SYSCTRL__CM_SW_RESET___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_SYSCTRL__CM_SW_RESET___S 1 +#define PHYA_IRON2G_RFA_WSI_SYSCTRL__WL_SW_RESET___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_SYSCTRL__WL_SW_RESET___S 0 +#define PHYA_IRON2G_RFA_WSI_SYSCTRL___M 0x00000C07 +#define PHYA_IRON2G_RFA_WSI_SYSCTRL___S 0 + +#define PHYA_IRON2G_RFA_WSI_PROT_UNLOCK (0x005CF004) +#define PHYA_IRON2G_RFA_WSI_PROT_UNLOCK___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_PROT_UNLOCK___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_PROT_UNLOCK__PROT_UNLOCK___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_PROT_UNLOCK__PROT_UNLOCK___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_PROT_UNLOCK__PROT_UNLOCK___S 0 +#define PHYA_IRON2G_RFA_WSI_PROT_UNLOCK___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_PROT_UNLOCK___S 0 + +#define PHYA_IRON2G_RFA_WSI_SYS_STAT (0x005CF008) +#define PHYA_IRON2G_RFA_WSI_SYS_STAT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_SYS_STAT___POR 0x00000038 +#define PHYA_IRON2G_RFA_WSI_SYS_STAT__PCM_STATE_1P8___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_SYS_STAT__OSCON_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_SYS_STAT__XO_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_SYS_STAT__CM_SYSRST_L___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_SYS_STAT__WL_SYSRST_L___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_SYS_STAT__BT_FM_SYSRST_L___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_SYS_STAT__CLK_SEL_VALID___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_SYS_STAT__CLK_FREQ_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_SYS_STAT__PCM_STATE_1P8___M 0x0000F000 +#define PHYA_IRON2G_RFA_WSI_SYS_STAT__PCM_STATE_1P8___S 12 +#define PHYA_IRON2G_RFA_WSI_SYS_STAT__OSCON_DONE___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_SYS_STAT__OSCON_DONE___S 7 +#define PHYA_IRON2G_RFA_WSI_SYS_STAT__XO_EN___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_SYS_STAT__XO_EN___S 6 +#define PHYA_IRON2G_RFA_WSI_SYS_STAT__CM_SYSRST_L___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_SYS_STAT__CM_SYSRST_L___S 5 +#define PHYA_IRON2G_RFA_WSI_SYS_STAT__WL_SYSRST_L___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_SYS_STAT__WL_SYSRST_L___S 4 +#define PHYA_IRON2G_RFA_WSI_SYS_STAT__BT_FM_SYSRST_L___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_SYS_STAT__BT_FM_SYSRST_L___S 3 +#define PHYA_IRON2G_RFA_WSI_SYS_STAT__CLK_SEL_VALID___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_SYS_STAT__CLK_SEL_VALID___S 2 +#define PHYA_IRON2G_RFA_WSI_SYS_STAT__CLK_FREQ_SEL___M 0x00000003 +#define PHYA_IRON2G_RFA_WSI_SYS_STAT__CLK_FREQ_SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_SYS_STAT___M 0x0000F0FF +#define PHYA_IRON2G_RFA_WSI_SYS_STAT___S 0 + +#define PHYA_IRON2G_RFA_WSI_SYS_STAT1 (0x005CF00C) +#define PHYA_IRON2G_RFA_WSI_SYS_STAT1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_SYS_STAT1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_SYS_STAT1__BOOTSTRAP___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_SYS_STAT1__AON_1P1_SM_DEBUG___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_SYS_STAT1__BOOTSTRAP___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_SYS_STAT1__BOOTSTRAP___S 8 +#define PHYA_IRON2G_RFA_WSI_SYS_STAT1__AON_1P1_SM_DEBUG___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_SYS_STAT1__AON_1P1_SM_DEBUG___S 0 +#define PHYA_IRON2G_RFA_WSI_SYS_STAT1___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_SYS_STAT1___S 0 + +#define PHYA_IRON2G_RFA_WSI_CHIP_ID (0x005CF010) +#define PHYA_IRON2G_RFA_WSI_CHIP_ID___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CHIP_ID___POR 0x00000100 +#define PHYA_IRON2G_RFA_WSI_CHIP_ID__CHIP_ID___POR 0x0100 +#define PHYA_IRON2G_RFA_WSI_CHIP_ID__CHIP_ID___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CHIP_ID__CHIP_ID___S 0 +#define PHYA_IRON2G_RFA_WSI_CHIP_ID___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CHIP_ID___S 0 + +#define PHYA_IRON2G_RFA_WSI_SYS_TEST (0x005CF014) +#define PHYA_IRON2G_RFA_WSI_SYS_TEST___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_SYS_TEST___POR 0x0000ABCD +#define PHYA_IRON2G_RFA_WSI_SYS_TEST__SYS_TEST___POR 0xABCD +#define PHYA_IRON2G_RFA_WSI_SYS_TEST__SYS_TEST___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_SYS_TEST__SYS_TEST___S 0 +#define PHYA_IRON2G_RFA_WSI_SYS_TEST___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_SYS_TEST___S 0 + +#define PHYA_IRON2G_RFA_WSI_SEC_UNLOCK (0x005CF018) +#define PHYA_IRON2G_RFA_WSI_SEC_UNLOCK___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_SEC_UNLOCK___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_SEC_UNLOCK__WSI_UNLOCK_JTAG_AHB___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_SEC_UNLOCK__WSI_UNLOCK_SCAN_DUMP___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_SEC_UNLOCK__WSI_UNLOCK_EJTAG___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_SEC_UNLOCK__WSI_UNLOCK_ALT_EJTAG___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_SEC_UNLOCK__WSI_UNLOCK_JTAG_AHB___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_SEC_UNLOCK__WSI_UNLOCK_JTAG_AHB___S 3 +#define PHYA_IRON2G_RFA_WSI_SEC_UNLOCK__WSI_UNLOCK_SCAN_DUMP___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_SEC_UNLOCK__WSI_UNLOCK_SCAN_DUMP___S 2 +#define PHYA_IRON2G_RFA_WSI_SEC_UNLOCK__WSI_UNLOCK_EJTAG___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_SEC_UNLOCK__WSI_UNLOCK_EJTAG___S 1 +#define PHYA_IRON2G_RFA_WSI_SEC_UNLOCK__WSI_UNLOCK_ALT_EJTAG___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_SEC_UNLOCK__WSI_UNLOCK_ALT_EJTAG___S 0 +#define PHYA_IRON2G_RFA_WSI_SEC_UNLOCK___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_SEC_UNLOCK___S 0 + +#define PHYA_IRON2G_RFA_WSI_BOOT_MISC (0x005CF01C) +#define PHYA_IRON2G_RFA_WSI_BOOT_MISC___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_BOOT_MISC___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_BOOT_MISC__DLDO_BYPASS_11___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BOOT_MISC__SLEEP_1P3_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BOOT_MISC__MNB_1P8_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BOOT_MISC__RETENTION_MODE_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BOOT_MISC__DLDO_BYPASS_11___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_BOOT_MISC__DLDO_BYPASS_11___S 3 +#define PHYA_IRON2G_RFA_WSI_BOOT_MISC__SLEEP_1P3_EN___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_BOOT_MISC__SLEEP_1P3_EN___S 2 +#define PHYA_IRON2G_RFA_WSI_BOOT_MISC__MNB_1P8_EN___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_BOOT_MISC__MNB_1P8_EN___S 1 +#define PHYA_IRON2G_RFA_WSI_BOOT_MISC__RETENTION_MODE_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_BOOT_MISC__RETENTION_MODE_EN___S 0 +#define PHYA_IRON2G_RFA_WSI_BOOT_MISC___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_BOOT_MISC___S 0 + +#define PHYA_IRON2G_RFA_WSI_PMU_CTRL (0x005CF020) +#define PHYA_IRON2G_RFA_WSI_PMU_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_PMU_CTRL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_PMU_CTRL__ATE_AODLDO_TRIM_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_PMU_CTRL__PMU_AODLDO_VSEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_PMU_CTRL__PMU_AODLDO_VSEL___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_PMU_CTRL__ATE_AODLDO_TRIM_EN___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_PMU_CTRL__ATE_AODLDO_TRIM_EN___S 9 +#define PHYA_IRON2G_RFA_WSI_PMU_CTRL__PMU_AODLDO_VSEL_OV___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_PMU_CTRL__PMU_AODLDO_VSEL_OV___S 8 +#define PHYA_IRON2G_RFA_WSI_PMU_CTRL__PMU_AODLDO_VSEL___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_PMU_CTRL__PMU_AODLDO_VSEL___S 0 +#define PHYA_IRON2G_RFA_WSI_PMU_CTRL___M 0x000003FF +#define PHYA_IRON2G_RFA_WSI_PMU_CTRL___S 0 + +#define PHYA_IRON2G_RFA_WSI_SUPPLY_STATE (0x005CF024) +#define PHYA_IRON2G_RFA_WSI_SUPPLY_STATE___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_SUPPLY_STATE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_SUPPLY_STATE__DEBUG___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_SUPPLY_STATE__DEBUG___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_SUPPLY_STATE__DEBUG___S 0 +#define PHYA_IRON2G_RFA_WSI_SUPPLY_STATE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_SUPPLY_STATE___S 0 + +#define PHYA_IRON2G_RFA_WSI_XO_SETTLE (0x005CF028) +#define PHYA_IRON2G_RFA_WSI_XO_SETTLE___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_XO_SETTLE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_XO_SETTLE__XO_TIME___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_XO_SETTLE__XO_TIME___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_XO_SETTLE__XO_TIME___S 0 +#define PHYA_IRON2G_RFA_WSI_XO_SETTLE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_XO_SETTLE___S 0 + +#define PHYA_IRON2G_RFA_WSI_CHIP_ID_U (0x005CF02C) +#define PHYA_IRON2G_RFA_WSI_CHIP_ID_U___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CHIP_ID_U___POR 0x0000400C +#define PHYA_IRON2G_RFA_WSI_CHIP_ID_U__CHIP_ID___POR 0x400C +#define PHYA_IRON2G_RFA_WSI_CHIP_ID_U__CHIP_ID___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CHIP_ID_U__CHIP_ID___S 0 +#define PHYA_IRON2G_RFA_WSI_CHIP_ID_U___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CHIP_ID_U___S 0 + +#define PHYA_IRON2G_RFA_WSI_GLOBAL_CONTROL (0x005CF030) +#define PHYA_IRON2G_RFA_WSI_GLOBAL_CONTROL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_GLOBAL_CONTROL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_GLOBAL_CONTROL__BT_AON_DBG_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_GLOBAL_CONTROL__TRC_CLK_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_GLOBAL_CONTROL__GLOBAL_SWITCH_OVRD___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_GLOBAL_CONTROL__BT_AON_DBG_SEL___M 0x00000070 +#define PHYA_IRON2G_RFA_WSI_GLOBAL_CONTROL__BT_AON_DBG_SEL___S 4 +#define PHYA_IRON2G_RFA_WSI_GLOBAL_CONTROL__TRC_CLK_EN___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_GLOBAL_CONTROL__TRC_CLK_EN___S 1 +#define PHYA_IRON2G_RFA_WSI_GLOBAL_CONTROL__GLOBAL_SWITCH_OVRD___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_GLOBAL_CONTROL__GLOBAL_SWITCH_OVRD___S 0 +#define PHYA_IRON2G_RFA_WSI_GLOBAL_CONTROL___M 0x00000073 +#define PHYA_IRON2G_RFA_WSI_GLOBAL_CONTROL___S 0 + +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE (0x005CF034) +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__S_PMU_TIMEOUT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__SEC_CTRL_OTP_TIMEOUT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__SR_CTL_EN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__OD_EN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__OD_EN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__HCI_UART_FR___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__SR_CTL_EN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__FM_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__BT_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__RTC_AON_DEBUG_MUX___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__S_PMU_TIMEOUT___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__S_PMU_TIMEOUT___S 31 +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__SEC_CTRL_OTP_TIMEOUT___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__SEC_CTRL_OTP_TIMEOUT___S 30 +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__SR_CTL_EN_1___M 0x00006000 +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__SR_CTL_EN_1___S 13 +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__OD_EN_1___M 0x00001800 +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__OD_EN_1___S 11 +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__OD_EN_0___M 0x00000600 +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__OD_EN_0___S 9 +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__HCI_UART_FR___M 0x000001E0 +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__HCI_UART_FR___S 5 +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__SR_CTL_EN_0___M 0x00000018 +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__SR_CTL_EN_0___S 3 +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__FM_RESET___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__FM_RESET___S 2 +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__BT_RESET___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__BT_RESET___S 1 +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__RTC_AON_DEBUG_MUX___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE__RTC_AON_DEBUG_MUX___S 0 +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE___M 0xC0007FFF +#define PHYA_IRON2G_RFA_WSI_DEBUG_AND_SPARE___S 0 + +#define PHYA_IRON2G_RFA_WSI_CHICKEN (0x005CF038) +#define PHYA_IRON2G_RFA_WSI_CHICKEN___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CHICKEN___POR 0x00000001 +#define PHYA_IRON2G_RFA_WSI_CHICKEN__BIT0___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CHICKEN__BIT0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_CHICKEN__BIT0___S 0 +#define PHYA_IRON2G_RFA_WSI_CHICKEN___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_CHICKEN___S 0 + +#define PHYA_IRON2G_RFA_WSI_BT_CLK_CNTL_KDF_REG (0x005CF040) +#define PHYA_IRON2G_RFA_WSI_BT_CLK_CNTL_KDF_REG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_BT_CLK_CNTL_KDF_REG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_BT_CLK_CNTL_KDF_REG__BT_CLK_CNTL_KDF_DISABLE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_CLK_CNTL_KDF_REG__BT_CLK_CNTL_KDF_DISABLE___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_BT_CLK_CNTL_KDF_REG__BT_CLK_CNTL_KDF_DISABLE___S 0 +#define PHYA_IRON2G_RFA_WSI_BT_CLK_CNTL_KDF_REG___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_BT_CLK_CNTL_KDF_REG___S 0 + +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG (0x005CF050) +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG___POR 0x00332002 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_PWR_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_STATE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_EN_REST_WAIT___POR 0x3 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_EN_FEW_WAIT___POR 0x3 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_CLK_DIS_WAIT___POR 0x2 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_RETAIN_FF_ENABLE_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_RESTORE_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_SAVE_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_RETAIN_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_ENR_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_ENF_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_CLAMP_IO_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_CLK_DISABLE_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_ARES_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_SW_OVERRIDE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_HW_CONTROL___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_COLLAPSE_EN_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_PWR_ON___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_PWR_ON___S 31 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_STATE___M 0x78000000 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_STATE___S 27 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_EN_REST_WAIT___M 0x00F00000 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_EN_REST_WAIT___S 20 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_EN_FEW_WAIT___M 0x000F0000 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_EN_FEW_WAIT___S 16 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_CLK_DIS_WAIT___M 0x0000F000 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_CLK_DIS_WAIT___S 12 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_RETAIN_FF_ENABLE_SW___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_RETAIN_FF_ENABLE_SW___S 11 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_RESTORE_SW___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_RESTORE_SW___S 10 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_SAVE_SW___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_SAVE_SW___S 9 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_RETAIN_SW___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_RETAIN_SW___S 8 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_ENR_SW___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_ENR_SW___S 7 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_ENF_SW___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_ENF_SW___S 6 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_CLAMP_IO_SW___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_CLAMP_IO_SW___S 5 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_CLK_DISABLE_SW___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_CLK_DISABLE_SW___S 4 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_ARES_SW___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_ARES_SW___S 3 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_SW_OVERRIDE___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_SW_OVERRIDE___S 2 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_HW_CONTROL___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_HW_CONTROL___S 1 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_COLLAPSE_EN_SW___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG__GDSCR_COLLAPSE_EN_SW___S 0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG___M 0xF8FFFFFF +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG___S 0 + +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1 (0x005CF054) +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1___POR 0x00008060 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_IN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_OUT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_PWR_DWN_START___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_PWR_UP_START___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_CFG_FSM_STATE_STATUS___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_MEM_PWR_ACK_STATUS___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_ENR_ACK_STATUS___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_ENF_ACK_STATUS___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_POWER_UP_COMPLETE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_POWER_DOWN_COMPLETE___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__SOFTWARE_CONTROL_OVERRIDE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_HANDSHAKE_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_MEM_PERI_FORCE_IN_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_MEM_CORE_FORCE_IN_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_EN_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_DELAY_COUNT_SW___POR 0x3 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_PSCBC_PWR_DWN_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__UNCLAMP_IO_SOFTWARE_OVERRIDE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_SAVE_RESTORE_SW_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__CLAMP_IO_SOFTWARE_OVERRIDE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__DISABLE_CLK_SOFTWARE_OVERRIDE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_IN___M 0xF0000000 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_IN___S 28 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_OUT___M 0x0C000000 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_OUT___S 26 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_PWR_DWN_START___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_PWR_DWN_START___S 25 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_PWR_UP_START___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_PWR_UP_START___S 24 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_CFG_FSM_STATE_STATUS___M 0x00F00000 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_CFG_FSM_STATE_STATUS___S 20 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_MEM_PWR_ACK_STATUS___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_MEM_PWR_ACK_STATUS___S 19 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_ENR_ACK_STATUS___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_ENR_ACK_STATUS___S 18 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_ENF_ACK_STATUS___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_ENF_ACK_STATUS___S 17 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_POWER_UP_COMPLETE___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_POWER_UP_COMPLETE___S 16 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_POWER_DOWN_COMPLETE___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_POWER_DOWN_COMPLETE___S 15 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__SOFTWARE_CONTROL_OVERRIDE___M 0x00007800 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__SOFTWARE_CONTROL_OVERRIDE___S 11 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_HANDSHAKE_DIS___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_HANDSHAKE_DIS___S 10 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_MEM_PERI_FORCE_IN_SW___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_MEM_PERI_FORCE_IN_SW___S 9 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_MEM_CORE_FORCE_IN_SW___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_MEM_CORE_FORCE_IN_SW___S 8 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_EN_SW___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_EN_SW___S 7 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_DELAY_COUNT_SW___M 0x00000060 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_DELAY_COUNT_SW___S 5 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_PSCBC_PWR_DWN_SW___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_PSCBC_PWR_DWN_SW___S 4 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__UNCLAMP_IO_SOFTWARE_OVERRIDE___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__UNCLAMP_IO_SOFTWARE_OVERRIDE___S 3 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_SAVE_RESTORE_SW_OVR___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__GDSC_SAVE_RESTORE_SW_OVR___S 2 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__CLAMP_IO_SOFTWARE_OVERRIDE___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__CLAMP_IO_SOFTWARE_OVERRIDE___S 1 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__DISABLE_CLK_SOFTWARE_OVERRIDE___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1__DISABLE_CLK_SOFTWARE_OVERRIDE___S 0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG1___S 0 + +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2 (0x005CF058) +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2___POR 0x0000222A +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2__GDSC_CLAMP_MEM_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2__DLY_MEM_PWR_UP___POR 0x2 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2__DLY_DEASSERT_CLAMP_MEM___POR 0x2 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2__DLY_ASSERT_CLAMP_MEM___POR 0x2 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2__MEM_PWR_DWN_TIMEOUT___POR 0xA +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2__GDSC_CLAMP_MEM_SW___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2__GDSC_CLAMP_MEM_SW___S 16 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2__DLY_MEM_PWR_UP___M 0x0000F000 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2__DLY_MEM_PWR_UP___S 12 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2__DLY_DEASSERT_CLAMP_MEM___M 0x00000F00 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2__DLY_DEASSERT_CLAMP_MEM___S 8 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2__DLY_ASSERT_CLAMP_MEM___M 0x000000F0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2__DLY_ASSERT_CLAMP_MEM___S 4 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2__MEM_PWR_DWN_TIMEOUT___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2__MEM_PWR_DWN_TIMEOUT___S 0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2___M 0x0001FFFF +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_CONTROL_REG2___S 0 + +#define PHYA_IRON2G_RFA_WSI_BT_SS_RAM_CORE_FORCE_REG (0x005CF05C) +#define PHYA_IRON2G_RFA_WSI_BT_SS_RAM_CORE_FORCE_REG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_BT_SS_RAM_CORE_FORCE_REG___POR 0x00003F3F +#define PHYA_IRON2G_RFA_WSI_BT_SS_RAM_CORE_FORCE_REG__BT_RAM_MEM_PERI_FORCE___POR 0x3F +#define PHYA_IRON2G_RFA_WSI_BT_SS_RAM_CORE_FORCE_REG__BT_RAM_MEM_CORE_FORCE___POR 0x3F +#define PHYA_IRON2G_RFA_WSI_BT_SS_RAM_CORE_FORCE_REG__BT_RAM_MEM_PERI_FORCE___M 0x00007F00 +#define PHYA_IRON2G_RFA_WSI_BT_SS_RAM_CORE_FORCE_REG__BT_RAM_MEM_PERI_FORCE___S 8 +#define PHYA_IRON2G_RFA_WSI_BT_SS_RAM_CORE_FORCE_REG__BT_RAM_MEM_CORE_FORCE___M 0x0000007F +#define PHYA_IRON2G_RFA_WSI_BT_SS_RAM_CORE_FORCE_REG__BT_RAM_MEM_CORE_FORCE___S 0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_RAM_CORE_FORCE_REG___M 0x00007F7F +#define PHYA_IRON2G_RFA_WSI_BT_SS_RAM_CORE_FORCE_REG___S 0 + +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG (0x005CF060) +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG___POR 0x00222002 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_PWR_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_STATE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_EN_REST_WAIT___POR 0x2 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_EN_FEW_WAIT___POR 0x2 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_CLK_DIS_WAIT___POR 0x2 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_RETAIN_FF_ENABLE_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_RESTORE_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_SAVE_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_RETAIN_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_ENR_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_ENF_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_CLAMP_IO_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_CLK_DISABLE_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_ARES_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_SW_OVERRIDE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_HW_CONTROL___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_COLLAPSE_EN_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_PWR_ON___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_PWR_ON___S 31 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_STATE___M 0x78000000 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_STATE___S 27 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_EN_REST_WAIT___M 0x00F00000 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_EN_REST_WAIT___S 20 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_EN_FEW_WAIT___M 0x000F0000 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_EN_FEW_WAIT___S 16 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_CLK_DIS_WAIT___M 0x0000F000 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_CLK_DIS_WAIT___S 12 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_RETAIN_FF_ENABLE_SW___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_RETAIN_FF_ENABLE_SW___S 11 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_RESTORE_SW___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_RESTORE_SW___S 10 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_SAVE_SW___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_SAVE_SW___S 9 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_RETAIN_SW___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_RETAIN_SW___S 8 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_ENR_SW___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_ENR_SW___S 7 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_ENF_SW___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_ENF_SW___S 6 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_CLAMP_IO_SW___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_CLAMP_IO_SW___S 5 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_CLK_DISABLE_SW___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_CLK_DISABLE_SW___S 4 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_ARES_SW___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_ARES_SW___S 3 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_SW_OVERRIDE___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_SW_OVERRIDE___S 2 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_HW_CONTROL___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_HW_CONTROL___S 1 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_COLLAPSE_EN_SW___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG__GDSCR_COLLAPSE_EN_SW___S 0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG___M 0xF8FFFFFF +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG___S 0 + +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1 (0x005CF064) +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1___POR 0x00008060 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_IN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_OUT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_PWR_DWN_START___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_PWR_UP_START___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_CFG_FSM_STATE_STATUS___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_MEM_PWR_ACK_STATUS___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_ENR_ACK_STATUS___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_ENF_ACK_STATUS___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_POWER_UP_COMPLETE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_POWER_DOWN_COMPLETE___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__SOFTWARE_CONTROL_OVERRIDE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_HANDSHAKE_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_MEM_PERI_FORCE_IN_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_MEM_CORE_FORCE_IN_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_EN_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_DELAY_COUNT_SW___POR 0x3 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_PSCBC_PWR_DWN_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__UNCLAMP_IO_SOFTWARE_OVERRIDE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_SAVE_RESTORE_SW_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__CLAMP_IO_SOFTWARE_OVERRIDE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__DISABLE_CLK_SOFTWARE_OVERRIDE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_IN___M 0xF0000000 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_IN___S 28 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_OUT___M 0x0C000000 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_OUT___S 26 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_PWR_DWN_START___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_PWR_DWN_START___S 25 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_PWR_UP_START___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_PWR_UP_START___S 24 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_CFG_FSM_STATE_STATUS___M 0x00F00000 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_CFG_FSM_STATE_STATUS___S 20 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_MEM_PWR_ACK_STATUS___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_MEM_PWR_ACK_STATUS___S 19 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_ENR_ACK_STATUS___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_ENR_ACK_STATUS___S 18 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_ENF_ACK_STATUS___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_ENF_ACK_STATUS___S 17 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_POWER_UP_COMPLETE___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_POWER_UP_COMPLETE___S 16 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_POWER_DOWN_COMPLETE___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_POWER_DOWN_COMPLETE___S 15 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__SOFTWARE_CONTROL_OVERRIDE___M 0x00007800 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__SOFTWARE_CONTROL_OVERRIDE___S 11 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_HANDSHAKE_DIS___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_HANDSHAKE_DIS___S 10 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_MEM_PERI_FORCE_IN_SW___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_MEM_PERI_FORCE_IN_SW___S 9 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_MEM_CORE_FORCE_IN_SW___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_MEM_CORE_FORCE_IN_SW___S 8 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_EN_SW___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_EN_SW___S 7 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_DELAY_COUNT_SW___M 0x00000060 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_DELAY_COUNT_SW___S 5 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_PSCBC_PWR_DWN_SW___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_PSCBC_PWR_DWN_SW___S 4 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__UNCLAMP_IO_SOFTWARE_OVERRIDE___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__UNCLAMP_IO_SOFTWARE_OVERRIDE___S 3 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_SAVE_RESTORE_SW_OVR___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__GDSC_SAVE_RESTORE_SW_OVR___S 2 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__CLAMP_IO_SOFTWARE_OVERRIDE___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__CLAMP_IO_SOFTWARE_OVERRIDE___S 1 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__DISABLE_CLK_SOFTWARE_OVERRIDE___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1__DISABLE_CLK_SOFTWARE_OVERRIDE___S 0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG1___S 0 + +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2 (0x005CF068) +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2___POR 0x0000222A +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2__GDSC_CLAMP_MEM_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2__DLY_MEM_PWR_UP___POR 0x2 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2__DLY_DEASSERT_CLAMP_MEM___POR 0x2 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2__DLY_ASSERT_CLAMP_MEM___POR 0x2 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2__MEM_PWR_DWN_TIMEOUT___POR 0xA +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2__GDSC_CLAMP_MEM_SW___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2__GDSC_CLAMP_MEM_SW___S 16 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2__DLY_MEM_PWR_UP___M 0x0000F000 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2__DLY_MEM_PWR_UP___S 12 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2__DLY_DEASSERT_CLAMP_MEM___M 0x00000F00 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2__DLY_DEASSERT_CLAMP_MEM___S 8 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2__DLY_ASSERT_CLAMP_MEM___M 0x000000F0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2__DLY_ASSERT_CLAMP_MEM___S 4 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2__MEM_PWR_DWN_TIMEOUT___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2__MEM_PWR_DWN_TIMEOUT___S 0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2___M 0x0001FFFF +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_CONTROL_REG2___S 0 + +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG (0x005CF070) +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG___POR 0x00222002 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_PWR_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_STATE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_EN_REST_WAIT___POR 0x2 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_EN_FEW_WAIT___POR 0x2 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_CLK_DIS_WAIT___POR 0x2 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_RETAIN_FF_ENABLE_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_RESTORE_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_SAVE_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_RETAIN_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_ENR_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_ENF_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_CLAMP_IO_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_CLK_DISABLE_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_ARES_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_SW_OVERRIDE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_HW_CONTROL___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_COLLAPSE_EN_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_PWR_ON___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_PWR_ON___S 31 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_STATE___M 0x78000000 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_STATE___S 27 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_EN_REST_WAIT___M 0x00F00000 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_EN_REST_WAIT___S 20 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_EN_FEW_WAIT___M 0x000F0000 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_EN_FEW_WAIT___S 16 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_CLK_DIS_WAIT___M 0x0000F000 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_CLK_DIS_WAIT___S 12 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_RETAIN_FF_ENABLE_SW___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_RETAIN_FF_ENABLE_SW___S 11 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_RESTORE_SW___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_RESTORE_SW___S 10 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_SAVE_SW___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_SAVE_SW___S 9 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_RETAIN_SW___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_RETAIN_SW___S 8 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_ENR_SW___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_ENR_SW___S 7 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_ENF_SW___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_ENF_SW___S 6 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_CLAMP_IO_SW___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_CLAMP_IO_SW___S 5 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_CLK_DISABLE_SW___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_CLK_DISABLE_SW___S 4 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_ARES_SW___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_ARES_SW___S 3 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_SW_OVERRIDE___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_SW_OVERRIDE___S 2 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_HW_CONTROL___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_HW_CONTROL___S 1 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_COLLAPSE_EN_SW___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG__GDSCR_COLLAPSE_EN_SW___S 0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG___M 0xF8FFFFFF +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG___S 0 + +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1 (0x005CF074) +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1___POR 0x00008060 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_IN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_OUT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_PWR_DWN_START___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_PWR_UP_START___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_CFG_FSM_STATE_STATUS___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_MEM_PWR_ACK_STATUS___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_ENR_ACK_STATUS___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_ENF_ACK_STATUS___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_POWER_UP_COMPLETE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_POWER_DOWN_COMPLETE___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__SOFTWARE_CONTROL_OVERRIDE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_HANDSHAKE_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_MEM_PERI_FORCE_IN_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_MEM_CORE_FORCE_IN_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_EN_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_DELAY_COUNT_SW___POR 0x3 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_PSCBC_PWR_DWN_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__UNCLAMP_IO_SOFTWARE_OVERRIDE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_SAVE_RESTORE_SW_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__CLAMP_IO_SOFTWARE_OVERRIDE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__DISABLE_CLK_SOFTWARE_OVERRIDE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_IN___M 0xF0000000 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_IN___S 28 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_OUT___M 0x0C000000 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSCR_SPARE_CONTROL_OUT___S 26 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_PWR_DWN_START___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_PWR_DWN_START___S 25 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_PWR_UP_START___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_PWR_UP_START___S 24 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_CFG_FSM_STATE_STATUS___M 0x00F00000 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_CFG_FSM_STATE_STATUS___S 20 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_MEM_PWR_ACK_STATUS___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_MEM_PWR_ACK_STATUS___S 19 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_ENR_ACK_STATUS___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_ENR_ACK_STATUS___S 18 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_ENF_ACK_STATUS___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_ENF_ACK_STATUS___S 17 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_POWER_UP_COMPLETE___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_POWER_UP_COMPLETE___S 16 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_POWER_DOWN_COMPLETE___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_POWER_DOWN_COMPLETE___S 15 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__SOFTWARE_CONTROL_OVERRIDE___M 0x00007800 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__SOFTWARE_CONTROL_OVERRIDE___S 11 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_HANDSHAKE_DIS___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_HANDSHAKE_DIS___S 10 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_MEM_PERI_FORCE_IN_SW___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_MEM_PERI_FORCE_IN_SW___S 9 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_MEM_CORE_FORCE_IN_SW___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_MEM_CORE_FORCE_IN_SW___S 8 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_EN_SW___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_EN_SW___S 7 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_DELAY_COUNT_SW___M 0x00000060 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_PHASE_RESET_DELAY_COUNT_SW___S 5 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_PSCBC_PWR_DWN_SW___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_PSCBC_PWR_DWN_SW___S 4 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__UNCLAMP_IO_SOFTWARE_OVERRIDE___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__UNCLAMP_IO_SOFTWARE_OVERRIDE___S 3 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_SAVE_RESTORE_SW_OVR___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__GDSC_SAVE_RESTORE_SW_OVR___S 2 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__CLAMP_IO_SOFTWARE_OVERRIDE___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__CLAMP_IO_SOFTWARE_OVERRIDE___S 1 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__DISABLE_CLK_SOFTWARE_OVERRIDE___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1__DISABLE_CLK_SOFTWARE_OVERRIDE___S 0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG1___S 0 + +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2 (0x005CF078) +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2___POR 0x0000222A +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2__GDSC_CLAMP_MEM_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2__DLY_MEM_PWR_UP___POR 0x2 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2__DLY_DEASSERT_CLAMP_MEM___POR 0x2 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2__DLY_ASSERT_CLAMP_MEM___POR 0x2 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2__MEM_PWR_DWN_TIMEOUT___POR 0xA +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2__GDSC_CLAMP_MEM_SW___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2__GDSC_CLAMP_MEM_SW___S 16 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2__DLY_MEM_PWR_UP___M 0x0000F000 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2__DLY_MEM_PWR_UP___S 12 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2__DLY_DEASSERT_CLAMP_MEM___M 0x00000F00 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2__DLY_DEASSERT_CLAMP_MEM___S 8 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2__DLY_ASSERT_CLAMP_MEM___M 0x000000F0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2__DLY_ASSERT_CLAMP_MEM___S 4 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2__MEM_PWR_DWN_TIMEOUT___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2__MEM_PWR_DWN_TIMEOUT___S 0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2___M 0x0001FFFF +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_CONTROL_REG2___S 0 + +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG (0x005CF080) +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__LDOBTCX_STATE___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__SPARE_CTRL_OUT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__PWR_DWN_START___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__PWR_UP_START___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__FSM_STATE_STATUS_MSB___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__MEM_PWR_ACK_STATUS___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__ENR_ACK_STATUS___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__ENF_ACK_STATUS___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__POWER_UP_COMPLETE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__POWER_DOWN_COMPLETE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__CLAMP_MEM___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__MEM_CORE_FORCE_OUT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__MEM_PERI_FORCE_OUT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__CLK_DISABLE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__CLAMP_IO___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__GDS_ENF___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__GDS_ENR___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__GDSC_ARES___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__GDSC_CTL_PWR_UP_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__GDSC_FSM_STATE_STATUS_LSB___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__LDOBTCX_STATE___M 0xFC000000 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__LDOBTCX_STATE___S 26 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__SPARE_CTRL_OUT___M 0x03000000 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__SPARE_CTRL_OUT___S 24 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__PWR_DWN_START___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__PWR_DWN_START___S 23 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__PWR_UP_START___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__PWR_UP_START___S 22 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__FSM_STATE_STATUS_MSB___M 0x003C0000 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__FSM_STATE_STATUS_MSB___S 18 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__MEM_PWR_ACK_STATUS___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__MEM_PWR_ACK_STATUS___S 17 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__ENR_ACK_STATUS___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__ENR_ACK_STATUS___S 16 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__ENF_ACK_STATUS___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__ENF_ACK_STATUS___S 15 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__POWER_UP_COMPLETE___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__POWER_UP_COMPLETE___S 14 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__POWER_DOWN_COMPLETE___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__POWER_DOWN_COMPLETE___S 13 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__CLAMP_MEM___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__CLAMP_MEM___S 12 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__MEM_CORE_FORCE_OUT___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__MEM_CORE_FORCE_OUT___S 11 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__MEM_PERI_FORCE_OUT___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__MEM_PERI_FORCE_OUT___S 10 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__CLK_DISABLE___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__CLK_DISABLE___S 9 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__CLAMP_IO___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__CLAMP_IO___S 8 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__GDS_ENF___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__GDS_ENF___S 7 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__GDS_ENR___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__GDS_ENR___S 6 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__GDSC_ARES___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__GDSC_ARES___S 5 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__GDSC_CTL_PWR_UP_DONE___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__GDSC_CTL_PWR_UP_DONE___S 4 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__GDSC_FSM_STATE_STATUS_LSB___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG__GDSC_FSM_STATE_STATUS_LSB___S 0 +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_BT_SS_GDSC_STATUS_REG___S 0 + +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG (0x005CF084) +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL1_REFCLK_READY___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL1_CLKOUT_REFCLK_READY___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL2_BT_BBPLL_READY___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL2_BT_TXRX_READY___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL2_WL_BBPLL_READY___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL2_WL_TXRX_READY___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__SPARE_CTRL_OUT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__PWR_DWN_START___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__PWR_UP_START___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__FSM_STATE_STATUS_MSB___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__MEM_PWR_ACK_STATUS___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__ENR_ACK_STATUS___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__ENF_ACK_STATUS___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__POWER_UP_COMPLETE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__POWER_DOWN_COMPLETE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__CLAMP_MEM___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__MEM_CORE_FORCE_OUT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__MEM_PERI_FORCE_OUT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__CLK_DISABLE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__CLAMP_IO___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__GDS_ENF___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__GDS_ENR___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__GDSC_ARES___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__GDSC_CTL_PWR_UP_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__GDSC_FSM_STATE_STATUS_LSB___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL1_REFCLK_READY___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL1_REFCLK_READY___S 31 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL1_CLKOUT_REFCLK_READY___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL1_CLKOUT_REFCLK_READY___S 30 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL2_BT_BBPLL_READY___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL2_BT_BBPLL_READY___S 29 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL2_BT_TXRX_READY___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL2_BT_TXRX_READY___S 28 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL2_WL_BBPLL_READY___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL2_WL_BBPLL_READY___S 27 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL2_WL_TXRX_READY___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__RFA_LEVEL2_WL_TXRX_READY___S 26 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__SPARE_CTRL_OUT___M 0x03000000 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__SPARE_CTRL_OUT___S 24 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__PWR_DWN_START___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__PWR_DWN_START___S 23 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__PWR_UP_START___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__PWR_UP_START___S 22 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__FSM_STATE_STATUS_MSB___M 0x003C0000 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__FSM_STATE_STATUS_MSB___S 18 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__MEM_PWR_ACK_STATUS___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__MEM_PWR_ACK_STATUS___S 17 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__ENR_ACK_STATUS___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__ENR_ACK_STATUS___S 16 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__ENF_ACK_STATUS___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__ENF_ACK_STATUS___S 15 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__POWER_UP_COMPLETE___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__POWER_UP_COMPLETE___S 14 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__POWER_DOWN_COMPLETE___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__POWER_DOWN_COMPLETE___S 13 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__CLAMP_MEM___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__CLAMP_MEM___S 12 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__MEM_CORE_FORCE_OUT___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__MEM_CORE_FORCE_OUT___S 11 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__MEM_PERI_FORCE_OUT___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__MEM_PERI_FORCE_OUT___S 10 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__CLK_DISABLE___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__CLK_DISABLE___S 9 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__CLAMP_IO___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__CLAMP_IO___S 8 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__GDS_ENF___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__GDS_ENF___S 7 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__GDS_ENR___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__GDS_ENR___S 6 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__GDSC_ARES___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__GDSC_ARES___S 5 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__GDSC_CTL_PWR_UP_DONE___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__GDSC_CTL_PWR_UP_DONE___S 4 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__GDSC_FSM_STATE_STATUS_LSB___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG__GDSC_FSM_STATE_STATUS_LSB___S 0 +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CMN_SS_GDSC_STATUS_REG___S 0 + +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG (0x005CF088) +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__XO_BG_READY___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__RFA_LEVEL0_BG_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__RFA_LEVEL1_REFCLK_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__RFA_LEVEL1_CLKOUT_REFCLK_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__RFA_LEVEL2_BT_BBPLL_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__RFA_LEVEL2_BT_TXRX_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__SPARE_CTRL_OUT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__PWR_DWN_START___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__PWR_UP_START___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__FSM_STATE_STATUS_MSB___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__MEM_PWR_ACK_STATUS___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__ENR_ACK_STATUS___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__ENF_ACK_STATUS___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__POWER_UP_COMPLETE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__POWER_DOWN_COMPLETE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__CLAMP_MEM___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__MEM_CORE_FORCE_OUT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__MEM_PERI_FORCE_OUT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__CLK_DISABLE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__CLAMP_IO___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__GDS_ENF___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__GDS_ENR___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__GDSC_ARES___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__GDSC_CTL_PWR_UP_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__GDSC_FSM_STATE_STATUS_LSB___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__XO_BG_READY___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__XO_BG_READY___S 31 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__RFA_LEVEL0_BG_REQ___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__RFA_LEVEL0_BG_REQ___S 30 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__RFA_LEVEL1_REFCLK_REQ___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__RFA_LEVEL1_REFCLK_REQ___S 29 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__RFA_LEVEL1_CLKOUT_REFCLK_REQ___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__RFA_LEVEL1_CLKOUT_REFCLK_REQ___S 28 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__RFA_LEVEL2_BT_BBPLL_REQ___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__RFA_LEVEL2_BT_BBPLL_REQ___S 27 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__RFA_LEVEL2_BT_TXRX_REQ___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__RFA_LEVEL2_BT_TXRX_REQ___S 26 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__SPARE_CTRL_OUT___M 0x03000000 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__SPARE_CTRL_OUT___S 24 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__PWR_DWN_START___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__PWR_DWN_START___S 23 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__PWR_UP_START___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__PWR_UP_START___S 22 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__FSM_STATE_STATUS_MSB___M 0x003C0000 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__FSM_STATE_STATUS_MSB___S 18 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__MEM_PWR_ACK_STATUS___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__MEM_PWR_ACK_STATUS___S 17 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__ENR_ACK_STATUS___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__ENR_ACK_STATUS___S 16 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__ENF_ACK_STATUS___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__ENF_ACK_STATUS___S 15 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__POWER_UP_COMPLETE___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__POWER_UP_COMPLETE___S 14 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__POWER_DOWN_COMPLETE___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__POWER_DOWN_COMPLETE___S 13 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__CLAMP_MEM___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__CLAMP_MEM___S 12 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__MEM_CORE_FORCE_OUT___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__MEM_CORE_FORCE_OUT___S 11 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__MEM_PERI_FORCE_OUT___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__MEM_PERI_FORCE_OUT___S 10 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__CLK_DISABLE___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__CLK_DISABLE___S 9 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__CLAMP_IO___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__CLAMP_IO___S 8 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__GDS_ENF___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__GDS_ENF___S 7 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__GDS_ENR___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__GDS_ENR___S 6 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__GDSC_ARES___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__GDSC_ARES___S 5 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__GDSC_CTL_PWR_UP_DONE___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__GDSC_CTL_PWR_UP_DONE___S 4 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__GDSC_FSM_STATE_STATUS_LSB___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG__GDSC_FSM_STATE_STATUS_LSB___S 0 +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_BT_USB_GDSC_STATUS_REG___S 0 + +#define PHYA_IRON2G_RFA_WSI_QFPROM_PWR_CTL (0x005CF08C) +#define PHYA_IRON2G_RFA_WSI_QFPROM_PWR_CTL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_QFPROM_PWR_CTL___POR 0x00000002 +#define PHYA_IRON2G_RFA_WSI_QFPROM_PWR_CTL__PWR_READY___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_QFPROM_PWR_CTL__VDD4BLOW_SW_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_QFPROM_PWR_CTL__SHUT_DN_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_QFPROM_PWR_CTL__PWR_READY___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_QFPROM_PWR_CTL__PWR_READY___S 2 +#define PHYA_IRON2G_RFA_WSI_QFPROM_PWR_CTL__VDD4BLOW_SW_EN___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_QFPROM_PWR_CTL__VDD4BLOW_SW_EN___S 1 +#define PHYA_IRON2G_RFA_WSI_QFPROM_PWR_CTL__SHUT_DN_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_QFPROM_PWR_CTL__SHUT_DN_EN___S 0 +#define PHYA_IRON2G_RFA_WSI_QFPROM_PWR_CTL___M 0x00000007 +#define PHYA_IRON2G_RFA_WSI_QFPROM_PWR_CTL___S 0 + +#define PHYA_IRON2G_RFA_WSI_BT_PMU_PWR_CTRL (0x005CF090) +#define PHYA_IRON2G_RFA_WSI_BT_PMU_PWR_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_BT_PMU_PWR_CTRL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_BT_PMU_PWR_CTRL__CMN_AON_SHUTDOWN_EN_BT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_BT_PMU_PWR_CTRL__BT_PMU_PWR_CTRL___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_BT_PMU_PWR_CTRL__CMN_AON_SHUTDOWN_EN_BT___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_BT_PMU_PWR_CTRL__CMN_AON_SHUTDOWN_EN_BT___S 31 +#define PHYA_IRON2G_RFA_WSI_BT_PMU_PWR_CTRL__BT_PMU_PWR_CTRL___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_BT_PMU_PWR_CTRL__BT_PMU_PWR_CTRL___S 0 +#define PHYA_IRON2G_RFA_WSI_BT_PMU_PWR_CTRL___M 0x800000FF +#define PHYA_IRON2G_RFA_WSI_BT_PMU_PWR_CTRL___S 0 + +#define PHYA_IRON2G_RFA_WSI_FUSE_TOP_AO_BT_AON_0 (0x005CF094) +#define PHYA_IRON2G_RFA_WSI_FUSE_TOP_AO_BT_AON_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_FUSE_TOP_AO_BT_AON_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_FUSE_TOP_AO_BT_AON_0__FUSE_TOP_BT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_FUSE_TOP_AO_BT_AON_0__FUSE_TOP_BT___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_FUSE_TOP_AO_BT_AON_0__FUSE_TOP_BT___S 0 +#define PHYA_IRON2G_RFA_WSI_FUSE_TOP_AO_BT_AON_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_FUSE_TOP_AO_BT_AON_0___S 0 + +#define PHYA_IRON2G_RFA_WSI_FUSE_TOP_AO_BT_AON_1 (0x005CF098) +#define PHYA_IRON2G_RFA_WSI_FUSE_TOP_AO_BT_AON_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_FUSE_TOP_AO_BT_AON_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_FUSE_TOP_AO_BT_AON_1__FUSE_TOP_BT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_FUSE_TOP_AO_BT_AON_1__FUSE_TOP_BT___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_FUSE_TOP_AO_BT_AON_1__FUSE_TOP_BT___S 0 +#define PHYA_IRON2G_RFA_WSI_FUSE_TOP_AO_BT_AON_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_FUSE_TOP_AO_BT_AON_1___S 0 + +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_WDATA (0x005CF09C) +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_WDATA___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_WDATA___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_WDATA__WL_SEC_CTRL_WDATA___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_WDATA__WL_SEC_CTRL_WDATA___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_WDATA__WL_SEC_CTRL_WDATA___S 0 +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_WDATA___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_WDATA___S 0 + +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_RDATA (0x005CF0A0) +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_RDATA___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_RDATA___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_RDATA__WL_SEC_CTRL_RDATA___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_RDATA__WL_SEC_CTRL_RDATA___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_RDATA__WL_SEC_CTRL_RDATA___S 0 +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_RDATA___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_RDATA___S 0 + +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ADDR (0x005CF0A4) +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ADDR___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ADDR___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ADDR__WL_SEC_CTRL_ADDR___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ADDR__WL_SEC_CTRL_ADDR___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ADDR__WL_SEC_CTRL_ADDR___S 0 +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ADDR___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ADDR___S 0 + +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ACCESS (0x005CF0A8) +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ACCESS___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ACCESS___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ACCESS__WL_SEC_CTRL_ACCESS_ERR___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ACCESS__WL_SEC_CTRL_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ACCESS__WL_SEC_CTRL_WR___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ACCESS__WL_SEC_CTRL_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ACCESS__WL_SEC_CTRL_ACCESS_ERR___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ACCESS__WL_SEC_CTRL_ACCESS_ERR___S 31 +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ACCESS__WL_SEC_CTRL_SEL___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ACCESS__WL_SEC_CTRL_SEL___S 2 +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ACCESS__WL_SEC_CTRL_WR___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ACCESS__WL_SEC_CTRL_WR___S 1 +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ACCESS__WL_SEC_CTRL_REQ___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ACCESS__WL_SEC_CTRL_REQ___S 0 +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ACCESS___M 0x80000007 +#define PHYA_IRON2G_RFA_WSI_WL_SEC_CTRL_ACCESS___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG (0x005CF400) +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG___POR 0x000001E0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_OUT_GPIO___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_HIHYS_CONTROL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_DS___POR 0x3 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_PUPD___POR 0x3 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_OE_GPIO___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_OUT_GPIO___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_OUT_GPIO___S 11 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_HIHYS_CONTROL___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_HIHYS_CONTROL___S 10 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_DS___M 0x00000380 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_DS___S 7 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_PUPD___M 0x00000060 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_PUPD___S 5 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_OE_GPIO___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_OE_GPIO___S 4 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_MODE___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG__BT_GPIO_0_MODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG___M 0x00000FFF +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_0_PAD_CFG___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG (0x005CF404) +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG___POR 0x000001A0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_OUT_GPIO___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_HIHYS_CONTROL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_DS___POR 0x3 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_PUPD___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_OE_GPIO___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_OUT_GPIO___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_OUT_GPIO___S 11 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_HIHYS_CONTROL___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_HIHYS_CONTROL___S 10 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_DS___M 0x00000380 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_DS___S 7 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_PUPD___M 0x00000060 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_PUPD___S 5 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_OE_GPIO___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_OE_GPIO___S 4 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_MODE___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG__BT_GPIO_1_MODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG___M 0x00000FFF +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_1_PAD_CFG___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG (0x005CF408) +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG___POR 0x000001A0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_OUT_GPIO___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_HIHYS_CONTROL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_DS___POR 0x3 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_PUPD___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_OE_GPIO___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_OUT_GPIO___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_OUT_GPIO___S 11 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_HIHYS_CONTROL___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_HIHYS_CONTROL___S 10 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_DS___M 0x00000380 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_DS___S 7 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_PUPD___M 0x00000060 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_PUPD___S 5 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_OE_GPIO___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_OE_GPIO___S 4 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_MODE___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG__BT_GPIO_2_MODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG___M 0x00000FFF +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_2_PAD_CFG___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG (0x005CF40C) +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG___POR 0x000001E0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_OUT_GPIO___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_HIHYS_CONTROL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_DS___POR 0x3 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_PUPD___POR 0x3 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_OE_GPIO___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_OUT_GPIO___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_OUT_GPIO___S 11 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_HIHYS_CONTROL___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_HIHYS_CONTROL___S 10 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_DS___M 0x00000380 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_DS___S 7 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_PUPD___M 0x00000060 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_PUPD___S 5 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_OE_GPIO___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_OE_GPIO___S 4 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_MODE___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG__BT_GPIO_3_MODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG___M 0x00000FFF +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_3_PAD_CFG___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG (0x005CF410) +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG___POR 0x00000180 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_OUT_GPIO___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_HIHYS_CONTROL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_DS___POR 0x3 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_PUPD___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_OE_GPIO___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_OUT_GPIO___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_OUT_GPIO___S 11 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_HIHYS_CONTROL___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_HIHYS_CONTROL___S 10 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_DS___M 0x00000380 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_DS___S 7 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_PUPD___M 0x00000060 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_PUPD___S 5 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_OE_GPIO___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_OE_GPIO___S 4 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_MODE___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG__BT_GPIO_4_MODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG___M 0x00000FFF +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_4_PAD_CFG___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG (0x005CF414) +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG___POR 0x000001E0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_OUT_GPIO___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_HIHYS_CONTROL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_DS___POR 0x3 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_PUPD___POR 0x3 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_OE_GPIO___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_OUT_GPIO___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_OUT_GPIO___S 11 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_HIHYS_CONTROL___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_HIHYS_CONTROL___S 10 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_DS___M 0x00000380 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_DS___S 7 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_PUPD___M 0x00000060 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_PUPD___S 5 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_OE_GPIO___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_OE_GPIO___S 4 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_MODE___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG__BT_GPIO_5_MODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG___M 0x00000FFF +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_5_PAD_CFG___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG (0x005CF418) +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG___POR 0x000001A0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_OUT_GPIO___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_HIHYS_CONTROL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_DS___POR 0x3 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_PUPD___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_OE_GPIO___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_OUT_GPIO___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_OUT_GPIO___S 11 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_HIHYS_CONTROL___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_HIHYS_CONTROL___S 10 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_DS___M 0x00000380 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_DS___S 7 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_PUPD___M 0x00000060 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_PUPD___S 5 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_OE_GPIO___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_OE_GPIO___S 4 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_MODE___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG__BT_GPIO_6_MODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG___M 0x00000FFF +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_6_PAD_CFG___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG (0x005CF41C) +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG___POR 0x00000180 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_OUT_GPIO___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_HIHYS_CONTROL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_DS___POR 0x3 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_PUPD___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_OE_GPIO___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_OUT_GPIO___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_OUT_GPIO___S 11 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_HIHYS_CONTROL___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_HIHYS_CONTROL___S 10 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_DS___M 0x00000380 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_DS___S 7 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_PUPD___M 0x00000060 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_PUPD___S 5 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_OE_GPIO___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_OE_GPIO___S 4 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_MODE___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG__BT_GPIO_7_MODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG___M 0x00000FFF +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_7_PAD_CFG___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG (0x005CF420) +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG___POR 0x000001A0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_OUT_GPIO___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_HIHYS_CONTROL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_DS___POR 0x3 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_PUPD___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_OE_GPIO___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_OUT_GPIO___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_OUT_GPIO___S 11 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_HIHYS_CONTROL___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_HIHYS_CONTROL___S 10 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_DS___M 0x00000380 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_DS___S 7 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_PUPD___M 0x00000060 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_PUPD___S 5 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_OE_GPIO___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_OE_GPIO___S 4 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_MODE___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG__BT_GPIO_8_MODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG___M 0x00000FFF +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_8_PAD_CFG___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG (0x005CF424) +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG___POR 0x000001E0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_OUT_GPIO___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_HIHYS_CONTROL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_DS___POR 0x3 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_PUPD___POR 0x3 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_OE_GPIO___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_OUT_GPIO___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_OUT_GPIO___S 11 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_HIHYS_CONTROL___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_HIHYS_CONTROL___S 10 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_DS___M 0x00000380 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_DS___S 7 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_PUPD___M 0x00000060 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_PUPD___S 5 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_OE_GPIO___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_OE_GPIO___S 4 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_MODE___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG__BT_GPIO_9_MODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG___M 0x00000FFF +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_9_PAD_CFG___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG (0x005CF428) +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG___POR 0x00000180 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_OUT_GPIO___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_HIHYS_CONTROL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_DS___POR 0x3 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_PUPD___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_OE_GPIO___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_OUT_GPIO___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_OUT_GPIO___S 11 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_HIHYS_CONTROL___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_HIHYS_CONTROL___S 10 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_DS___M 0x00000380 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_DS___S 7 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_PUPD___M 0x00000060 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_PUPD___S 5 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_OE_GPIO___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_OE_GPIO___S 4 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_MODE___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG__BT_GPIO_10_MODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG___M 0x00000FFF +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_10_PAD_CFG___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG (0x005CF42C) +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG___POR 0x000001A0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_OUT_GPIO___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_HIHYS_CONTROL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_DS___POR 0x3 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_PUPD___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_OE_GPIO___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_OUT_GPIO___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_OUT_GPIO___S 11 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_HIHYS_CONTROL___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_HIHYS_CONTROL___S 10 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_DS___M 0x00000380 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_DS___S 7 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_PUPD___M 0x00000060 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_PUPD___S 5 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_OE_GPIO___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_OE_GPIO___S 4 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_MODE___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG__BT_GPIO_11_MODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG___M 0x00000FFF +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_11_PAD_CFG___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG (0x005CF430) +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG___POR 0x00000180 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_OUT_GPIO___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_HIHYS_CONTROL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_DS___POR 0x3 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_PUPD___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_OE_GPIO___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_OUT_GPIO___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_OUT_GPIO___S 11 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_HIHYS_CONTROL___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_HIHYS_CONTROL___S 10 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_DS___M 0x00000380 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_DS___S 7 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_PUPD___M 0x00000060 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_PUPD___S 5 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_OE_GPIO___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_OE_GPIO___S 4 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_MODE___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG__BT_GPIO_12_MODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG___M 0x00000FFF +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_12_PAD_CFG___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG (0x005CF434) +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG___POR 0x00000180 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_OUT_GPIO___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_HIHYS_CONTROL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_DS___POR 0x3 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_PUPD___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_OE_GPIO___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_OUT_GPIO___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_OUT_GPIO___S 11 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_HIHYS_CONTROL___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_HIHYS_CONTROL___S 10 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_DS___M 0x00000380 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_DS___S 7 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_PUPD___M 0x00000060 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_PUPD___S 5 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_OE_GPIO___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_OE_GPIO___S 4 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_MODE___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG__BT_GPIO_13_MODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG___M 0x00000FFF +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_BT_GPIO_13_PAD_CFG___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_LF_CLK_IN (0x005CF438) +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_LF_CLK_IN___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_LF_CLK_IN___POR 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_LF_CLK_IN__MODE___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_LF_CLK_IN__MODE___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_LF_CLK_IN__MODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_LF_CLK_IN___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_LF_CLK_IN___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTR_STATUS (0x005CF43C) +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTR_STATUS___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTR_STATUS___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTR_STATUS__BT_GPIO_INTR___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTR_STATUS__BT_GPIO_INTR___M 0x00003FFF +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTR_STATUS__BT_GPIO_INTR___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTR_STATUS___M 0x00003FFF +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTR_STATUS___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_STATUS (0x005CF440) +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_STATUS___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_STATUS___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_STATUS__BT_GPIO_INTR___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_STATUS__BT_GPIO_INTR___M 0x00003FFF +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_STATUS__BT_GPIO_INTR___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_STATUS___M 0x00003FFF +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_STATUS___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_GPIO_READ (0x005CF444) +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_GPIO_READ___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_GPIO_READ___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_GPIO_READ__BT_GPIO___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_GPIO_READ__BT_GPIO___M 0x00003FFF +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_GPIO_READ__BT_GPIO___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_GPIO_READ___M 0x00003FFF +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_GPIO_READ___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTP_EN_REG (0x005CF448) +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTP_EN_REG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTP_EN_REG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTP_EN_REG__BT_GPIO___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTP_EN_REG__BT_GPIO___M 0x00003FFF +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTP_EN_REG__BT_GPIO___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTP_EN_REG___M 0x00003FFF +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTP_EN_REG___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTP_POL_REG (0x005CF44C) +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTP_POL_REG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTP_POL_REG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTP_POL_REG__BT_GPIO___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTP_POL_REG__BT_GPIO___M 0x00003FFF +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTP_POL_REG__BT_GPIO___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTP_POL_REG___M 0x00003FFF +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_INTP_POL_REG___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_EN_REG (0x005CF450) +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_EN_REG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_EN_REG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_EN_REG__BT_GPIO___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_EN_REG__BT_GPIO___M 0x00003FFF +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_EN_REG__BT_GPIO___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_EN_REG___M 0x00003FFF +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_EN_REG___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_POL_REG (0x005CF454) +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_POL_REG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_POL_REG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_POL_REG__BT_GPIO___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_POL_REG__BT_GPIO___M 0x00003FFF +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_POL_REG__BT_GPIO___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_POL_REG___M 0x00003FFF +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_WAKEUP_POL_REG___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_CROSS_WAKEUP_PULSE (0x005CF458) +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_CROSS_WAKEUP_PULSE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_CROSS_WAKEUP_PULSE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_CROSS_WAKEUP_PULSE__STATUS___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_CROSS_WAKEUP_PULSE__GEN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_CROSS_WAKEUP_PULSE__STATUS___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_CROSS_WAKEUP_PULSE__STATUS___S 1 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_CROSS_WAKEUP_PULSE__GEN___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_CROSS_WAKEUP_PULSE__GEN___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_CROSS_WAKEUP_PULSE___M 0x00000003 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_CROSS_WAKEUP_PULSE___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_SI_SRC_SEL (0x005CF45C) +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_SI_SRC_SEL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_SI_SRC_SEL___POR 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_SI_SRC_SEL__SPI_I2C_SEL___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_SI_SRC_SEL__SPI_I2C_SEL___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_SI_SRC_SEL__SPI_I2C_SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_SI_SRC_SEL___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_SI_SRC_SEL___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_SPARE_REG (0x005CF460) +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_SPARE_REG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_SPARE_REG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_SPARE_REG__AO_TLMM_SPARE_REG___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_SPARE_REG__AO_TLMM_SPARE_REG___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_SPARE_REG__AO_TLMM_SPARE_REG___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_SPARE_REG___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_SPARE_REG___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_0 (0x005CF464) +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_0__AO_TLMM_DBG_BUS_BIT_SEL3___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_0__AO_TLMM_DBG_BUS_BIT_SEL2___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_0__AO_TLMM_DBG_BUS_BIT_SEL1___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_0__AO_TLMM_DBG_BUS_BIT_SEL0___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_0__AO_TLMM_DBG_BUS_BIT_SEL3___M 0x1F000000 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_0__AO_TLMM_DBG_BUS_BIT_SEL3___S 24 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_0__AO_TLMM_DBG_BUS_BIT_SEL2___M 0x001F0000 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_0__AO_TLMM_DBG_BUS_BIT_SEL2___S 16 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_0__AO_TLMM_DBG_BUS_BIT_SEL1___M 0x00001F00 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_0__AO_TLMM_DBG_BUS_BIT_SEL1___S 8 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_0__AO_TLMM_DBG_BUS_BIT_SEL0___M 0x0000001F +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_0__AO_TLMM_DBG_BUS_BIT_SEL0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_0___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_0___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_1 (0x005CF468) +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_1__AO_TLMM_DBG_BUS_BIT_SEL7___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_1__AO_TLMM_DBG_BUS_BIT_SEL6___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_1__AO_TLMM_DBG_BUS_BIT_SEL5___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_1__AO_TLMM_DBG_BUS_BIT_SEL4___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_1__AO_TLMM_DBG_BUS_BIT_SEL7___M 0x1F000000 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_1__AO_TLMM_DBG_BUS_BIT_SEL7___S 24 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_1__AO_TLMM_DBG_BUS_BIT_SEL6___M 0x001F0000 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_1__AO_TLMM_DBG_BUS_BIT_SEL6___S 16 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_1__AO_TLMM_DBG_BUS_BIT_SEL5___M 0x00001F00 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_1__AO_TLMM_DBG_BUS_BIT_SEL5___S 8 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_1__AO_TLMM_DBG_BUS_BIT_SEL4___M 0x0000001F +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_1__AO_TLMM_DBG_BUS_BIT_SEL4___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_1___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_1___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_2 (0x005CF46C) +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_2__AO_TLMM_DBG_BUS_BIT_SEL11___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_2__AO_TLMM_DBG_BUS_BIT_SEL10___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_2__AO_TLMM_DBG_BUS_BIT_SEL9___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_2__AO_TLMM_DBG_BUS_BIT_SEL8___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_2__AO_TLMM_DBG_BUS_BIT_SEL11___M 0x1F000000 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_2__AO_TLMM_DBG_BUS_BIT_SEL11___S 24 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_2__AO_TLMM_DBG_BUS_BIT_SEL10___M 0x001F0000 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_2__AO_TLMM_DBG_BUS_BIT_SEL10___S 16 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_2__AO_TLMM_DBG_BUS_BIT_SEL9___M 0x00001F00 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_2__AO_TLMM_DBG_BUS_BIT_SEL9___S 8 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_2__AO_TLMM_DBG_BUS_BIT_SEL8___M 0x0000001F +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_2__AO_TLMM_DBG_BUS_BIT_SEL8___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_2___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_2___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_3 (0x005CF470) +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_3__AO_TLMM_DBG_BUS_BIT_SEL13___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_3__AO_TLMM_DBG_BUS_BIT_SEL12___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_3__AO_TLMM_DBG_BUS_BIT_SEL13___M 0x00001F00 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_3__AO_TLMM_DBG_BUS_BIT_SEL13___S 8 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_3__AO_TLMM_DBG_BUS_BIT_SEL12___M 0x0000001F +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_3__AO_TLMM_DBG_BUS_BIT_SEL12___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_3___M 0x00001F1F +#define PHYA_IRON2G_RFA_WSI_A_AO_TLMM_AO_TLMM_DBG_BUS_BIT_SEL_3___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_1 (0x005CF800) +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_1__CM_REFCLK_EN_OVRD___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_1__CLK_REQ_OVRD___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_1__CM_REFCLK_EN_OVRD___M 0x000000C0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_1__CM_REFCLK_EN_OVRD___S 6 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_1__CLK_REQ_OVRD___M 0x00000030 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_1__CLK_REQ_OVRD___S 4 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_1___M 0x000000F0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_1___S 4 + +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_2 (0x005CF804) +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_2__XO_EN_OVRD___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_2__OSCON_DONE_OVRD___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_2__XO_LDO_EN_OVRD___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_2__XO_EN_OVRD___M 0x000000C0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_2__XO_EN_OVRD___S 6 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_2__OSCON_DONE_OVRD___M 0x00000030 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_2__OSCON_DONE_OVRD___S 4 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_2__XO_LDO_EN_OVRD___M 0x0000000C +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_2__XO_LDO_EN_OVRD___S 2 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_2___M 0x000000FC +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_2___S 2 + +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_3 (0x005CF808) +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_3__PMU_CLK_EN_OVRD___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_3__BTSS_REFCLK_EN_OVRD___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_3__BT_AON_REFCLK_EN_OVRD___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_3__PMU_CLK_EN_OVRD___M 0x000000C0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_3__PMU_CLK_EN_OVRD___S 6 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_3__BTSS_REFCLK_EN_OVRD___M 0x00000030 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_3__BTSS_REFCLK_EN_OVRD___S 4 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_3__BT_AON_REFCLK_EN_OVRD___M 0x0000000C +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_3__BT_AON_REFCLK_EN_OVRD___S 2 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_3___M 0x000000FC +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_3___S 2 + +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_4 (0x005CF80C) +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_4__LDOBTCX_EN_OVRD___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_4__LDOBTCX_VSEL_OVRD___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_4__BTCX_CLAMP_IO_N_OVRD___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_4__LDOBTCX_EN_OVRD___M 0x00000030 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_4__LDOBTCX_EN_OVRD___S 4 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_4__LDOBTCX_VSEL_OVRD___M 0x0000000C +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_4__LDOBTCX_VSEL_OVRD___S 2 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_4__BTCX_CLAMP_IO_N_OVRD___M 0x00000003 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_4__BTCX_CLAMP_IO_N_OVRD___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_4___M 0x0000003F +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_4___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_5 (0x005CF810) +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_5__XO_CLK_OUT_REQ_OVRD___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_5__XO_CLK_OUT_CGC_EN_OVRD___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_5__CENT_BIAS_EN_OVRD___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_5__XO_CLK_OUT_REQ_OVRD___M 0x00000030 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_5__XO_CLK_OUT_REQ_OVRD___S 4 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_5__XO_CLK_OUT_CGC_EN_OVRD___M 0x0000000C +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_5__XO_CLK_OUT_CGC_EN_OVRD___S 2 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_5__CENT_BIAS_EN_OVRD___M 0x00000003 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_5__CENT_BIAS_EN_OVRD___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_5___M 0x0000003F +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_5___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_6 (0x005CF814) +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_6__RFA_LEVEL2_BT_TXRX_REQ_OVRD___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_6__RFA_LEVEL2_BT_BBPLL_REQ_OVRD___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_6__RFA_LEVEL1_CLKOUT_REFCLK_REQ_OVRD___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_6__RFA_LEVEL1_REFCLK_REQ_OVRD___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_6__RFA_LEVEL2_BT_TXRX_REQ_OVRD___M 0x000000C0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_6__RFA_LEVEL2_BT_TXRX_REQ_OVRD___S 6 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_6__RFA_LEVEL2_BT_BBPLL_REQ_OVRD___M 0x00000030 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_6__RFA_LEVEL2_BT_BBPLL_REQ_OVRD___S 4 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_6__RFA_LEVEL1_CLKOUT_REFCLK_REQ_OVRD___M 0x0000000C +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_6__RFA_LEVEL1_CLKOUT_REFCLK_REQ_OVRD___S 2 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_6__RFA_LEVEL1_REFCLK_REQ_OVRD___M 0x00000003 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_6__RFA_LEVEL1_REFCLK_REQ_OVRD___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_6___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_OUT_OVR_6___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_0 (0x005CF818) +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_0__CMN_AON_HFRC_CLK_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_0__RFA_CMN_LDO_READY___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_0__FIRST_BOOT_OVRD___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_0__CMN_AON_HFRC_CLK_ON___M 0x00000030 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_0__CMN_AON_HFRC_CLK_ON___S 4 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_0__RFA_CMN_LDO_READY___M 0x0000000C +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_0__RFA_CMN_LDO_READY___S 2 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_0__FIRST_BOOT_OVRD___M 0x00000003 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_0__FIRST_BOOT_OVRD___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_0___M 0x0000003F +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_0___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_1 (0x005CF81C) +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_1__WLAN_SS_EN_OVRD___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_1__BT_FM_SS_EN_OVRD___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_1__CLK_REQ_IN_OVRD___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_1__QOW_BOOT_OVRD___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_1__WLAN_SS_EN_OVRD___M 0x000000C0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_1__WLAN_SS_EN_OVRD___S 6 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_1__BT_FM_SS_EN_OVRD___M 0x00000030 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_1__BT_FM_SS_EN_OVRD___S 4 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_1__CLK_REQ_IN_OVRD___M 0x0000000C +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_1__CLK_REQ_IN_OVRD___S 2 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_1__QOW_BOOT_OVRD___M 0x00000003 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_1__QOW_BOOT_OVRD___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_1___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_2 (0x005CF820) +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_2__SOC_WLAN_XO_EN_OVRD___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_2__BT_SLEEP_OVRD___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_2__SOC_WLAN_XO_EN_OVRD___M 0x000000C0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_2__SOC_WLAN_XO_EN_OVRD___S 6 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_2__BT_SLEEP_OVRD___M 0x00000030 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_2__BT_SLEEP_OVRD___S 4 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_2___M 0x000000F0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_2___S 4 + +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_3 (0x005CF824) +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_3__EFUSE_RD_DONE_OVRD___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_3__WL_WAKEUP_EARLY_OVRD___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_3__EFUSE_RD_DONE_OVRD___M 0x00000030 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_3__EFUSE_RD_DONE_OVRD___S 4 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_3__WL_WAKEUP_EARLY_OVRD___M 0x0000000C +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_3__WL_WAKEUP_EARLY_OVRD___S 2 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_3___M 0x0000003C +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_3___S 2 + +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_4 (0x005CF828) +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_4__PMU_AUTO_FETCH_DONE_OVRD___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_4__PMU_AUTO_FETCH_DONE_OVRD___M 0x00000003 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_4__PMU_AUTO_FETCH_DONE_OVRD___S 0 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_4___M 0x00000003 +#define PHYA_IRON2G_RFA_WSI_A_AO_OVERRIDE_AO_IN_OVR_4___S 0 + +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW0_LSB (0x005CFC00) +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW0_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW0_LSB__SERIAL_NUM_31_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW0_LSB__SERIAL_NUM_31_0___S 0 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW0_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW0_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW0_MSB (0x005CFC04) +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW0_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW0_MSB__JTAG_ID_15_0___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW0_MSB__JTAG_ID_15_0___S 16 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW0_MSB__SERIAL_NUM_47_32___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW0_MSB__SERIAL_NUM_47_32___S 0 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW0_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW0_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB (0x005CFC08) +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__RSVD_R6_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__EXTERNAL_32K_SELECT___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__EXTERNAL_32K_SELECT___S 8 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__XO_CLK_SEL_VALID___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__XO_CLK_SEL_VALID___S 7 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__XO_CLK_SEL_RAW___M 0x00000060 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__XO_CLK_SEL_RAW___S 5 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__REFCLK_USE_TCXO___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__REFCLK_USE_TCXO___S 4 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__JTAG_ID_19_16___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB__JTAG_ID_19_16___S 0 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB (0x005CFC0C) +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B63___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B63___S 31 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B62___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B62___S 30 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B61___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B61___S 29 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B60___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B60___S 28 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B59___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B59___S 27 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B58___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B58___S 26 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B57___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B57___S 25 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B56___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B56___S 24 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB__RSVD_R6_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW1_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB (0x005CFC10) +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__RFA_CLAMP_IO_SETTLE___M 0xE0000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__RFA_CLAMP_IO_SETTLE___S 29 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__RFA_08_LDO_SETTLE___M 0x1C000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__RFA_08_LDO_SETTLE___S 26 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__RFA_12_LDO_DLY___M 0x03800000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__RFA_12_LDO_DLY___S 23 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__RFA_17_LDO_DLY___M 0x00700000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__RFA_17_LDO_DLY___S 20 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__VDD08AO_VLD___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__VDD08AO_VLD___S 19 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__VDD08AO_VALUE___M 0x0007F800 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__VDD08AO_VALUE___S 11 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__VDD08AO_VSEL___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__VDD08AO_VSEL___S 10 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__SW_CTRL_DLY___M 0x00000380 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__SW_CTRL_DLY___S 7 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__RFALDO_DLY___M 0x00000070 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__RFALDO_DLY___S 4 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__VDD08RFACMN_VSEL___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__VDD08RFACMN_VSEL___S 3 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__VDD08RFA_VSEL___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__VDD08RFA_VSEL___S 2 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__VDD12RFA_VSEL___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__VDD12RFA_VSEL___S 1 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__VDD17RFA_VSEL___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB__VDD17RFA_VSEL___S 0 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB (0x005CFC14) +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B63___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B63___S 31 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B62___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B62___S 30 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B61___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B61___S 29 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B60___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B60___S 28 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B59___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B59___S 27 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B58___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B58___S 26 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B57___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B57___S 25 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B56___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B56___S 24 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__RSVD_R7_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__VDD08AO_HFRC_VLD___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__VDD08AO_HFRC_VLD___S 4 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__VDD08AO_HFRC_TRIM___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB__VDD08AO_HFRC_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW2_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB (0x005CFC18) +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__RSVD_R8_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__TSENS_DBGBUS_DISABLE___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__TSENS_DBGBUS_DISABLE___S 17 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__OTP_PCIE_PHY_VDDA_SETTLE_DLY___M 0x0001E000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__OTP_PCIE_PHY_VDDA_SETTLE_DLY___S 13 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__OTP_PCIE_PHY_1P8_SETTLE_DLY___M 0x00001E00 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__OTP_PCIE_PHY_1P8_SETTLE_DLY___S 9 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__OTP_WLCX_SETTLE_DLY___M 0x000001E0 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__OTP_WLCX_SETTLE_DLY___S 5 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__OTP_WLMX_SETTLE_DLY___M 0x0000001E +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__OTP_WLMX_SETTLE_DLY___S 1 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__OTP_BLOWN_DONE___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB__OTP_BLOWN_DONE___S 0 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB (0x005CFC1C) +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__ATPG_JTAG_DISABLE___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__ATPG_JTAG_DISABLE___S 31 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B62___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B62___S 30 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B61___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B61___S 29 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B60___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B60___S 28 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B59___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B59___S 27 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B58___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B58___S 26 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B57___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B57___S 25 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B56___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B56___S 24 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB__RSVD_R8_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW3_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB (0x005CFC20) +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__RSVD_R9_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__WSI_WL_OTP_DISABLE___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__WSI_WL_OTP_DISABLE___S 12 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__BTC_DISABLE___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__BTC_DISABLE___S 11 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__ANT_DISABLE___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__ANT_DISABLE___S 10 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__BLE_DISABLE___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__BLE_DISABLE___S 9 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__WL_ONLY_WL_SLEEP___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__WL_ONLY_WL_SLEEP___S 8 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__LDOBTCX_RET_SETTLE_TIME___M 0x000000F0 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__LDOBTCX_RET_SETTLE_TIME___S 4 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__LDOBTCX_SETTLE_TIME___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB__LDOBTCX_SETTLE_TIME___S 0 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB (0x005CFC24) +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B63___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B63___S 31 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B62___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B62___S 30 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B61___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B61___S 29 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B60___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B60___S 28 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B59___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B59___S 27 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B58___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B58___S 26 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B57___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B57___S 25 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B56___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B56___S 24 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__RSVD_R9_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__BOOT_PATCH_SELECT___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__BOOT_PATCH_SELECT___S 2 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__BT_MODE___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__BT_MODE___S 1 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__BT_MANU_PGM___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB__BT_MANU_PGM___S 0 +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_AON_AUTO_SENSED_TOP_ROW4_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_00 (0x005C0000) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_00___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_00___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_00__SEL___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_00__SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_00__SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_00___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_00___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_01 (0x005C0004) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_01___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_01___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_01__SEL___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_01__SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_01__SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_01___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_01___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_02 (0x005C0008) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_02___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_02___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_02__SEL___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_02__SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_02__SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_02___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_02___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_03 (0x005C000C) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_03___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_03___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_03__SEL___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_03__SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_03__SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_03___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_03___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_04 (0x005C0010) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_04___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_04___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_04__SEL___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_04__SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_04__SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_04___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_04___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_05 (0x005C0014) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_05___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_05___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_05__SEL___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_05__SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_05__SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_05___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_05___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_06 (0x005C0018) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_06___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_06___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_06__SEL___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_06__SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_06__SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_06___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_06___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_07 (0x005C001C) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_07___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_07___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_07__SEL___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_07__SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_07__SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_07___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_07___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_08 (0x005C0020) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_08___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_08___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_08__SEL___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_08__SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_08__SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_08___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_08___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_09 (0x005C0024) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_09___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_09___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_09__SEL___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_09__SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_09__SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_09___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_09___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_10 (0x005C0028) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_10__SEL___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_10__SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_10__SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_10___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_10___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_11 (0x005C002C) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_11__SEL___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_11__SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_11__SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_11___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_11___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_12 (0x005C0030) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_12__SEL___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_12__SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_12__SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_12___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_12___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_13 (0x005C0034) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_13__SEL___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_13__SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_13__SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_13___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_13___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_14 (0x005C0038) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_14__SEL___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_14__SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_14__SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_14___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_14___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_15 (0x005C003C) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_15__SEL___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_15__SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_15__SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_15___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_15___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_16 (0x005C0040) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_16___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_16__SEL___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_16__SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_16__SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_16___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_16___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_17 (0x005C0044) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_17___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_17__SEL___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_17__SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_17__SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_17___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_17___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_18 (0x005C0048) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_18___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_18__SEL___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_18__SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_18__SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_18___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_18___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_19 (0x005C004C) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_19___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_19__SEL___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_19__SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_19__SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_19___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_19___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_20 (0x005C0050) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_20___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_20__SEL___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_20__SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_20__SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_20___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_20___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_21 (0x005C0054) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_21___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_21__SEL___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_21__SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_21__SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_21___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_21___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_22 (0x005C0058) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_22___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_22__SEL___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_22__SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_22__SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_22___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_22___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_23 (0x005C005C) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_23___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_23__SEL___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_23__SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_23__SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_23___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_23___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_24 (0x005C0060) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_24___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_24__SEL___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_24__SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_24__SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_24___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_24___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_25 (0x005C0064) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_25___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_25__SEL___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_25__SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_25__SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_25___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_25___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_26 (0x005C0068) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_26___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_26__SEL___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_26__SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_26__SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_26___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_26___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_27 (0x005C006C) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_27___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_27__SEL___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_27__SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_27__SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_27___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_27___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_28 (0x005C0070) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_28___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_28__SEL___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_28__SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_28__SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_28___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_28___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_29 (0x005C0074) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_29___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_29__SEL___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_29__SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_29__SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_29___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_29___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_30 (0x005C0078) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_30___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_30__SEL___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_30__SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_30__SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_30___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_30___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_31 (0x005C007C) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_31___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_31__SEL___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_31__SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_31__SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_31___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_XBAR_CFG_31___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_TMUX_CFG (0x005C0080) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_TMUX_CFG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_TMUX_CFG___POR 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_TMUX_CFG__OMATRIX_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_TMUX_CFG__OUT_LOW_SLICE_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_TMUX_CFG__IN_SLICE_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_TMUX_CFG__TMUX_SEL___POR 0xF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_TMUX_CFG__OMATRIX_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_TMUX_CFG__OMATRIX_EN___S 7 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_TMUX_CFG__OUT_LOW_SLICE_SEL___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_TMUX_CFG__OUT_LOW_SLICE_SEL___S 6 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_TMUX_CFG__IN_SLICE_SEL___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_TMUX_CFG__IN_SLICE_SEL___S 5 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_TMUX_CFG__TMUX_SEL___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_TMUX_CFG__TMUX_SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_TMUX_CFG___M 0x000000EF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TLMM_TMUX_CFG___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CTRL (0x005C0200) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CTRL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CTRL__TRC_CTRL_SPARE___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CTRL__TRC_ENABLE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CTRL__SW_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CTRL__TRC_CTRL_SPARE___M 0x0000FFFC +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CTRL__TRC_CTRL_SPARE___S 2 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CTRL__TRC_ENABLE___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CTRL__TRC_ENABLE___S 1 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CTRL__SW_RESET___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CTRL__SW_RESET___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CTRL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CTRL___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_BYTE_SWAP (0x005C0204) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_BYTE_SWAP___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_BYTE_SWAP___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_BYTE_SWAP__TRCBUS_BYTE_SWAP___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_BYTE_SWAP__TRCBUS_BYTE_SWAP___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_BYTE_SWAP__TRCBUS_BYTE_SWAP___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_BYTE_SWAP___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_BYTE_SWAP___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL3 (0x005C0208) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL3__TRCBUS_BIT15_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL3__TRCBUS_BIT14_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL3__TRCBUS_BIT13_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL3__TRCBUS_BIT12_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL3__TRCBUS_BIT15_SEL___M 0x00007000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL3__TRCBUS_BIT15_SEL___S 12 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL3__TRCBUS_BIT14_SEL___M 0x00000700 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL3__TRCBUS_BIT14_SEL___S 8 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL3__TRCBUS_BIT13_SEL___M 0x00000070 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL3__TRCBUS_BIT13_SEL___S 4 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL3__TRCBUS_BIT12_SEL___M 0x00000007 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL3__TRCBUS_BIT12_SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL3___M 0x00007777 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL3___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL2 (0x005C020C) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL2__TRCBUS_BIT11_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL2__TRCBUS_BIT10_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL2__TRCBUS_BIT09_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL2__TRCBUS_BIT08_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL2__TRCBUS_BIT11_SEL___M 0x00007000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL2__TRCBUS_BIT11_SEL___S 12 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL2__TRCBUS_BIT10_SEL___M 0x00000700 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL2__TRCBUS_BIT10_SEL___S 8 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL2__TRCBUS_BIT09_SEL___M 0x00000070 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL2__TRCBUS_BIT09_SEL___S 4 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL2__TRCBUS_BIT08_SEL___M 0x00000007 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL2__TRCBUS_BIT08_SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL2___M 0x00007777 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL2___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL1 (0x005C0210) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL1__TRCBUS_BIT07_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL1__TRCBUS_BIT06_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL1__TRCBUS_BIT05_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL1__TRCBUS_BIT04_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL1__TRCBUS_BIT07_SEL___M 0x00007000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL1__TRCBUS_BIT07_SEL___S 12 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL1__TRCBUS_BIT06_SEL___M 0x00000700 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL1__TRCBUS_BIT06_SEL___S 8 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL1__TRCBUS_BIT05_SEL___M 0x00000070 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL1__TRCBUS_BIT05_SEL___S 4 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL1__TRCBUS_BIT04_SEL___M 0x00000007 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL1__TRCBUS_BIT04_SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL1___M 0x00007777 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL1___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL0 (0x005C0214) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL0__TRCBUS_BIT03_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL0__TRCBUS_BIT02_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL0__TRCBUS_BIT01_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL0__TRCBUS_BIT00_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL0__TRCBUS_BIT03_SEL___M 0x00007000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL0__TRCBUS_BIT03_SEL___S 12 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL0__TRCBUS_BIT02_SEL___M 0x00000700 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL0__TRCBUS_BIT02_SEL___S 8 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL0__TRCBUS_BIT01_SEL___M 0x00000070 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL0__TRCBUS_BIT01_SEL___S 4 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL0__TRCBUS_BIT00_SEL___M 0x00000007 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL0__TRCBUS_BIT00_SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL0___M 0x00007777 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TRCBUS_SEL0___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_INPUT_MASK (0x005C0218) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_INPUT_MASK___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_INPUT_MASK___POR 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_INPUT_MASK__INPUT_MASK___POR 0xFFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_INPUT_MASK__INPUT_MASK___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_INPUT_MASK__INPUT_MASK___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_INPUT_MASK___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_INPUT_MASK___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0 (0x005C021C) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0___POR 0x00001070 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__INPUT_DEGLITCH___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__CMEM_CFG_OVWRITE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__CMEM_CFG_TSTAMP___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__CMEM_CFG_PDOWN___POR 0x3 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__CPU_PAGING___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__CPU_ACCESS_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__INPUT_DEGLITCH___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__INPUT_DEGLITCH___S 12 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__CMEM_CFG_OVWRITE___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__CMEM_CFG_OVWRITE___S 7 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__CMEM_CFG_TSTAMP___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__CMEM_CFG_TSTAMP___S 6 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__CMEM_CFG_PDOWN___M 0x00000030 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__CMEM_CFG_PDOWN___S 4 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__CPU_PAGING___M 0x0000000E +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__CPU_PAGING___S 1 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__CPU_ACCESS_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0__CPU_ACCESS_EN___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0___M 0x000010FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG0___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG1 (0x005C0220) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG1__SAMPLING_RATE___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG1__STAMP_SCALE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG1__SAMPLING_RATE___M 0x0000FFF0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG1__SAMPLING_RATE___S 4 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG1__STAMP_SCALE___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG1__STAMP_SCALE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG1___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CFG1___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_MASK (0x005C0224) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_MASK___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_MASK___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_MASK__WFT_CAPTURE_MASK___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_MASK__WFT_CAPTURE_MASK___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_MASK__WFT_CAPTURE_MASK___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_MASK___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_MASK___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_CTRL (0x005C0228) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_CTRL___POR 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_CTRL__WFT_CAPTURE_MODE___POR 0x2 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_CTRL__WFT_CAPTURE_MAX_COUNT___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_CTRL__WFT_NXT_TS_ENABLE___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_CTRL__WFT_CAPTURE_MODE___M 0x0000C000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_CTRL__WFT_CAPTURE_MODE___S 14 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_CTRL__WFT_CAPTURE_MAX_COUNT___M 0x00003FE0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_CTRL__WFT_CAPTURE_MAX_COUNT___S 5 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_CTRL__WFT_NXT_TS_ENABLE___M 0x0000001F +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_CTRL__WFT_NXT_TS_ENABLE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_CTRL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WFT_CAPTURE_CTRL___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_TRIG_MASK (0x005C022C) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_TRIG_MASK___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_TRIG_MASK___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_TRIG_MASK__TS1_TRIG_MASK___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_TRIG_MASK__TS1_TRIG_MASK___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_TRIG_MASK__TS1_TRIG_MASK___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_TRIG_MASK___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_TRIG_MASK___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_TRIG_VALUE (0x005C0230) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_TRIG_VALUE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_TRIG_VALUE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_TRIG_VALUE__TS1_TRIG_VALUE___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_TRIG_VALUE__TS1_TRIG_VALUE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_TRIG_VALUE__TS1_TRIG_VALUE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_TRIG_VALUE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_TRIG_VALUE___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_MASK (0x005C0234) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_MASK___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_MASK___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_MASK__TS1_CAPTURE_MASK___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_MASK__TS1_CAPTURE_MASK___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_MASK__TS1_CAPTURE_MASK___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_MASK___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_MASK___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_CTRL (0x005C0238) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_CTRL___POR 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_CTRL__TS1_CAPTURE_MODE___POR 0x2 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_CTRL__TS1_CAPTURE_MAX_COUNT___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_CTRL__TS1_NXT_TS_ENABLE___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_CTRL__TS1_CAPTURE_MODE___M 0x0000C000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_CTRL__TS1_CAPTURE_MODE___S 14 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_CTRL__TS1_CAPTURE_MAX_COUNT___M 0x00003FE0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_CTRL__TS1_CAPTURE_MAX_COUNT___S 5 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_CTRL__TS1_NXT_TS_ENABLE___M 0x0000001F +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_CTRL__TS1_NXT_TS_ENABLE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_CTRL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS1_CAPTURE_CTRL___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_TRIG_MASK (0x005C023C) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_TRIG_MASK___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_TRIG_MASK___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_TRIG_MASK__TS2_TRIG_MASK___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_TRIG_MASK__TS2_TRIG_MASK___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_TRIG_MASK__TS2_TRIG_MASK___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_TRIG_MASK___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_TRIG_MASK___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_TRIG_VALUE (0x005C0240) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_TRIG_VALUE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_TRIG_VALUE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_TRIG_VALUE__TS2_TRIG_VALUE___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_TRIG_VALUE__TS2_TRIG_VALUE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_TRIG_VALUE__TS2_TRIG_VALUE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_TRIG_VALUE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_TRIG_VALUE___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_MASK (0x005C0244) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_MASK___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_MASK___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_MASK__TS2_CAPTURE_MASK___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_MASK__TS2_CAPTURE_MASK___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_MASK__TS2_CAPTURE_MASK___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_MASK___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_MASK___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_CTRL (0x005C0248) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_CTRL___POR 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_CTRL__TS2_CAPTURE_MODE___POR 0x2 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_CTRL__TS2_CAPTURE_MAX_COUNT___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_CTRL__TS2_NXT_TS_ENABLE___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_CTRL__TS2_CAPTURE_MODE___M 0x0000C000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_CTRL__TS2_CAPTURE_MODE___S 14 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_CTRL__TS2_CAPTURE_MAX_COUNT___M 0x00003FE0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_CTRL__TS2_CAPTURE_MAX_COUNT___S 5 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_CTRL__TS2_NXT_TS_ENABLE___M 0x0000001F +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_CTRL__TS2_NXT_TS_ENABLE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_CTRL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS2_CAPTURE_CTRL___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_TRIG_MASK (0x005C024C) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_TRIG_MASK___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_TRIG_MASK___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_TRIG_MASK__TS3_TRIG_MASK___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_TRIG_MASK__TS3_TRIG_MASK___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_TRIG_MASK__TS3_TRIG_MASK___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_TRIG_MASK___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_TRIG_MASK___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_TRIG_VALUE (0x005C0250) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_TRIG_VALUE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_TRIG_VALUE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_TRIG_VALUE__TS3_TRIG_VALUE___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_TRIG_VALUE__TS3_TRIG_VALUE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_TRIG_VALUE__TS3_TRIG_VALUE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_TRIG_VALUE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_TRIG_VALUE___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_MASK (0x005C0254) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_MASK___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_MASK___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_MASK__TS3_CAPTURE_MASK___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_MASK__TS3_CAPTURE_MASK___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_MASK__TS3_CAPTURE_MASK___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_MASK___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_MASK___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_CTRL (0x005C0258) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_CTRL___POR 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_CTRL__TS3_CAPTURE_MODE___POR 0x2 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_CTRL__TS3_CAPTURE_MAX_COUNT___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_CTRL__TS3_NXT_TS_ENABLE___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_CTRL__TS3_CAPTURE_MODE___M 0x0000C000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_CTRL__TS3_CAPTURE_MODE___S 14 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_CTRL__TS3_CAPTURE_MAX_COUNT___M 0x00003FE0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_CTRL__TS3_CAPTURE_MAX_COUNT___S 5 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_CTRL__TS3_NXT_TS_ENABLE___M 0x0000001F +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_CTRL__TS3_NXT_TS_ENABLE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_CTRL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS3_CAPTURE_CTRL___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_TRIG_MASK (0x005C025C) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_TRIG_MASK___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_TRIG_MASK___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_TRIG_MASK__TS4_TRIG_MASK___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_TRIG_MASK__TS4_TRIG_MASK___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_TRIG_MASK__TS4_TRIG_MASK___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_TRIG_MASK___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_TRIG_MASK___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_TRIG_VALUE (0x005C0260) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_TRIG_VALUE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_TRIG_VALUE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_TRIG_VALUE__TS4_TRIG_VALUE___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_TRIG_VALUE__TS4_TRIG_VALUE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_TRIG_VALUE__TS4_TRIG_VALUE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_TRIG_VALUE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_TRIG_VALUE___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_MASK (0x005C0264) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_MASK___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_MASK___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_MASK__TS4_CAPTURE_MASK___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_MASK__TS4_CAPTURE_MASK___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_MASK__TS4_CAPTURE_MASK___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_MASK___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_MASK___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_CTRL (0x005C0268) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_CTRL___POR 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_CTRL__TS4_CAPTURE_MODE___POR 0x2 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_CTRL__TS4_CAPTURE_MAX_COUNT___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_CTRL__TS4_NXT_TS_ENABLE___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_CTRL__TS4_CAPTURE_MODE___M 0x0000C000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_CTRL__TS4_CAPTURE_MODE___S 14 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_CTRL__TS4_CAPTURE_MAX_COUNT___M 0x00003FE0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_CTRL__TS4_CAPTURE_MAX_COUNT___S 5 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_CTRL__TS4_NXT_TS_ENABLE___M 0x0000001F +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_CTRL__TS4_NXT_TS_ENABLE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_CTRL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS4_CAPTURE_CTRL___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_TRIG_MASK (0x005C026C) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_TRIG_MASK___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_TRIG_MASK___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_TRIG_MASK__TS5_TRIG_MASK___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_TRIG_MASK__TS5_TRIG_MASK___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_TRIG_MASK__TS5_TRIG_MASK___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_TRIG_MASK___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_TRIG_MASK___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_TRIG_VALUE (0x005C0270) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_TRIG_VALUE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_TRIG_VALUE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_TRIG_VALUE__TS5_TRIG_VALUE___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_TRIG_VALUE__TS5_TRIG_VALUE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_TRIG_VALUE__TS5_TRIG_VALUE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_TRIG_VALUE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_TRIG_VALUE___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_MASK (0x005C0274) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_MASK___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_MASK___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_MASK__TS5_CAPTURE_MASK___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_MASK__TS5_CAPTURE_MASK___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_MASK__TS5_CAPTURE_MASK___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_MASK___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_MASK___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_CTRL (0x005C0278) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_CTRL___POR 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_CTRL__TS5_CAPTURE_MODE___POR 0x2 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_CTRL__TS5_CAPTURE_MAX_COUNT___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_CTRL__TS5_NXT_TS_ENABLE___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_CTRL__TS5_CAPTURE_MODE___M 0x0000C000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_CTRL__TS5_CAPTURE_MODE___S 14 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_CTRL__TS5_CAPTURE_MAX_COUNT___M 0x00003FE0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_CTRL__TS5_CAPTURE_MAX_COUNT___S 5 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_CTRL__TS5_NXT_TS_ENABLE___M 0x0000001F +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_CTRL__TS5_NXT_TS_ENABLE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_CTRL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_TS5_CAPTURE_CTRL___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_CUR (0x005C027C) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_CUR___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_CUR___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_CUR__MAIN_STATE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_CUR__CMEM_STATE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_CUR__MAIN_STATE___M 0x00000070 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_CUR__MAIN_STATE___S 4 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_CUR__CMEM_STATE___M 0x00000007 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_CUR__CMEM_STATE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_CUR___M 0x00000077 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_CUR___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_LAST (0x005C0280) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_LAST___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_LAST___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_LAST__CMEM_FULL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_LAST__CMEM_OVERWRITTEN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_LAST__CMEM_LAST_ADDR___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_LAST__CMEM_FULL___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_LAST__CMEM_FULL___S 12 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_LAST__CMEM_OVERWRITTEN___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_LAST__CMEM_OVERWRITTEN___S 11 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_LAST__CMEM_LAST_ADDR___M 0x000007FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_LAST__CMEM_LAST_ADDR___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_LAST___M 0x00001FFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_LAST___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR0 (0x005C0284) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR0__CMEM_TRIGGER_ADDR0___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR0__CMEM_TRIGGER_ADDR0___M 0x000007FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR0__CMEM_TRIGGER_ADDR0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR0___M 0x000007FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR0___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR1 (0x005C0288) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR1__CMEM_TRIGGER_ADDR1___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR1__CMEM_TRIGGER_ADDR1___M 0x000007FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR1__CMEM_TRIGGER_ADDR1___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR1___M 0x000007FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR1___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR2 (0x005C028C) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR2__CMEM_TRIGGER_ADDR2___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR2__CMEM_TRIGGER_ADDR2___M 0x000007FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR2__CMEM_TRIGGER_ADDR2___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR2___M 0x000007FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR2___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR3 (0x005C0290) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR3__CMEM_TRIGGER_ADDR3___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR3__CMEM_TRIGGER_ADDR3___M 0x000007FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR3__CMEM_TRIGGER_ADDR3___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR3___M 0x000007FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_STAT_TRIG_ADDR3___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WRITE_POINTER (0x005C0294) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WRITE_POINTER___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WRITE_POINTER___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WRITE_POINTER__PTR___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WRITE_POINTER__PTR___M 0x000007FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WRITE_POINTER__PTR___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WRITE_POINTER___M 0x000007FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_WRITE_POINTER___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_READ_POINTER (0x005C0298) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_READ_POINTER___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_READ_POINTER___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_READ_POINTER__PTR___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_READ_POINTER__PTR___M 0x000007FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_READ_POINTER__PTR___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_READ_POINTER___M 0x000007FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_READ_POINTER___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRACER_EVENT (0x005C029C) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRACER_EVENT___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRACER_EVENT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRACER_EVENT__MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRACER_EVENT__MODE___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRACER_EVENT__MODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRACER_EVENT___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRACER_EVENT___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_EVENT_ENABLE (0x005C02A0) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_EVENT_ENABLE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_EVENT_ENABLE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_EVENT_ENABLE__V___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_EVENT_ENABLE__V___M 0x0000007F +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_EVENT_ENABLE__V___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_EVENT_ENABLE___M 0x0000007F +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_EVENT_ENABLE___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_CROSS_TRIGGER_ENABLE (0x005C02A4) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_CROSS_TRIGGER_ENABLE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_CROSS_TRIGGER_ENABLE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_CROSS_TRIGGER_ENABLE__V___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_CROSS_TRIGGER_ENABLE__V___M 0x0000001F +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_CROSS_TRIGGER_ENABLE__V___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_CROSS_TRIGGER_ENABLE___M 0x0000001F +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_CROSS_TRIGGER_ENABLE___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_INTERRUPT (0x005C02A8) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_INTERRUPT___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_INTERRUPT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_INTERRUPT__STATUS___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_INTERRUPT__EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_INTERRUPT__STATUS___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_INTERRUPT__STATUS___S 1 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_INTERRUPT__EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_INTERRUPT__EN___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_INTERRUPT___M 0x00000003 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_INTERRUPT___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_WATERMARK (0x005C02AC) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_WATERMARK___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_WATERMARK___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_WATERMARK__VAL___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_WATERMARK__VAL___M 0x00000FFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_WATERMARK__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_WATERMARK___M 0x00000FFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_WATERMARK___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CLK_SEL (0x005C02B0) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CLK_SEL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CLK_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CLK_SEL__VAL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CLK_SEL__VAL___M 0x00000003 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CLK_SEL__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CLK_SEL___M 0x00000003 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_CLK_SEL___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_CLK_GATE (0x005C02B4) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_CLK_GATE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_CLK_GATE___POR 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_CLK_GATE__TRC_CLK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_CLK_GATE__TRC_CLK___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_CLK_GATE__TRC_CLK___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_CLK_GATE___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_CLK_GATE___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_MEM_START_ADDR (0x005C02B8) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_MEM_START_ADDR___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_MEM_START_ADDR___POR 0x30001000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_MEM_START_ADDR__VAL___POR 0x30001000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_MEM_START_ADDR__VAL___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_MEM_START_ADDR__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_MEM_START_ADDR___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_TRC_MEM_START_ADDR___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_SPARE_0 (0x005C02BC) +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_SPARE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_SPARE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_SPARE_0__SPARE_BIT___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_SPARE_0__SPARE_BIT___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_SPARE_0__SPARE_BIT___S 0 +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_SPARE_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_HZ_TRC_SPARE_0___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_UART_DATA (0x005C5000) +#define PHYA_IRON2G_RFA_WSI_CXM_UART_DATA___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_UART_DATA___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_DATA__TX_CSR___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_DATA__RX_CSR___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_DATA__TXRX_DATA___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_DATA__TX_CSR___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_DATA__TX_CSR___S 9 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_DATA__RX_CSR___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_DATA__RX_CSR___S 8 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_DATA__TXRX_DATA___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_CXM_UART_DATA__TXRX_DATA___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_DATA___M 0x000003FF +#define PHYA_IRON2G_RFA_WSI_CXM_UART_DATA___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL (0x005C5004) +#define PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL__TDM_RX_ENA___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL__RX_BUSY___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL__TX_BUSY___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL__TX_BREAK___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL__RX_BREAK___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL__TDM_RX_ENA___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL__TDM_RX_ENA___S 4 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL__RX_BUSY___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL__RX_BUSY___S 3 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL__TX_BUSY___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL__TX_BUSY___S 2 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL__TX_BREAK___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL__TX_BREAK___S 1 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL__RX_BREAK___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL__RX_BREAK___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL___M 0x0000001F +#define PHYA_IRON2G_RFA_WSI_CXM_UART_CONTROL___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO1 (0x005C5008) +#define PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO1__TX_FIFO_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO1__DEPTH___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO1__AEPT_THR___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO1__TX_FIFO_RST___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO1__TX_FIFO_RST___S 17 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO1__DEPTH___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO1__DEPTH___S 8 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO1__AEPT_THR___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO1__AEPT_THR___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO1___M 0x0002FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO1___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO2 (0x005C500C) +#define PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO2__RB_CSR___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO2__RB_VALID___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO2__RB_VAL___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO2__RB_CSR___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO2__RB_CSR___S 9 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO2__RB_VALID___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO2__RB_VALID___S 8 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO2__RB_VAL___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO2__RB_VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO2___M 0x000003FF +#define PHYA_IRON2G_RFA_WSI_CXM_UART_TX_FIFO2___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_UART_RX_FIFO (0x005C5010) +#define PHYA_IRON2G_RFA_WSI_CXM_UART_RX_FIFO___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_UART_RX_FIFO___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_RX_FIFO__RX_FIFO_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_RX_FIFO__DEPTH___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_RX_FIFO__AFUL_THR___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_RX_FIFO__RX_FIFO_RST___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_RX_FIFO__RX_FIFO_RST___S 17 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_RX_FIFO__DEPTH___M 0x0001FF00 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_RX_FIFO__DEPTH___S 8 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_RX_FIFO__AFUL_THR___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_CXM_UART_RX_FIFO__AFUL_THR___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_RX_FIFO___M 0x0003FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_UART_RX_FIFO___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_UART_CLKDIV (0x005C5014) +#define PHYA_IRON2G_RFA_WSI_CXM_UART_CLKDIV___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_UART_CLKDIV___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_CLKDIV__CLK_SCALE___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_CLKDIV__CLK_STEP___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_CLKDIV__CLK_SCALE___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_CLKDIV__CLK_SCALE___S 16 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_CLKDIV__CLK_STEP___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_UART_CLKDIV__CLK_STEP___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_CLKDIV___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_UART_CLKDIV___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT (0x005C5018) +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TX_ENA_RE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TX_ENA_FE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__DIRECT_MSG_TXED___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TCM_NACK___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TCM_ACK___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TDM_MISALIGN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE7_MSG_RXED___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE6_MSG_RXED___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE5_MSG_RXED___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE4_MSG_RXED___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE3_MSG_RXED___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE2_MSG_RXED___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE1_MSG_RXED___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE0_MSG_RXED___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__CXM_TIMER1_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__CXM_TIMER0_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__MWS_RX_FE_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__MWS_RX_RE_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__MWS_TX_FE_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__MWS_TX_RE_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__EXT_FSYNC_RE_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__FSYNC_RE_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TX_FIFO_OVFL_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TX_FIFO_READY_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_FIFO_UDFL_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_FIFO_OVFL_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_FIFO_READY_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_BREAK_OFF_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_BREAK_ON_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_FRAMING_ERR_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TX_ENA_RE___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TX_ENA_RE___S 30 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TX_ENA_FE___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TX_ENA_FE___S 29 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__DIRECT_MSG_TXED___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__DIRECT_MSG_TXED___S 28 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TCM_NACK___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TCM_NACK___S 27 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TCM_ACK___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TCM_ACK___S 26 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TDM_MISALIGN___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TDM_MISALIGN___S 25 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE7_MSG_RXED___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE7_MSG_RXED___S 24 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE6_MSG_RXED___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE6_MSG_RXED___S 23 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE5_MSG_RXED___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE5_MSG_RXED___S 22 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE4_MSG_RXED___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE4_MSG_RXED___S 21 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE3_MSG_RXED___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE3_MSG_RXED___S 20 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE2_MSG_RXED___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE2_MSG_RXED___S 19 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE1_MSG_RXED___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE1_MSG_RXED___S 18 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE0_MSG_RXED___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TYPE0_MSG_RXED___S 17 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__CXM_TIMER1_INT___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__CXM_TIMER1_INT___S 16 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__CXM_TIMER0_INT___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__CXM_TIMER0_INT___S 15 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__MWS_RX_FE_INT___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__MWS_RX_FE_INT___S 14 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__MWS_RX_RE_INT___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__MWS_RX_RE_INT___S 13 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__MWS_TX_FE_INT___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__MWS_TX_FE_INT___S 12 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__MWS_TX_RE_INT___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__MWS_TX_RE_INT___S 11 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__EXT_FSYNC_RE_INT___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__EXT_FSYNC_RE_INT___S 9 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__FSYNC_RE_INT___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__FSYNC_RE_INT___S 8 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TX_FIFO_OVFL_INT___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TX_FIFO_OVFL_INT___S 7 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TX_FIFO_READY_INT___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__TX_FIFO_READY_INT___S 6 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_FIFO_UDFL_INT___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_FIFO_UDFL_INT___S 5 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_FIFO_OVFL_INT___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_FIFO_OVFL_INT___S 4 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_FIFO_READY_INT___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_FIFO_READY_INT___S 3 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_BREAK_OFF_INT___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_BREAK_OFF_INT___S 2 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_BREAK_ON_INT___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_BREAK_ON_INT___S 1 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_FRAMING_ERR_INT___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT__RX_FRAMING_ERR_INT___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT___M 0x7FFFFBFF +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN (0x005C501C) +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__HOST_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TX_ENA_RE_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TX_ENA_FE_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__DIRECT_MSG_TXED_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TCM_NACK_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TCM_ACK_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TDM_MISALIGN_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE7_MSG_RXED_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE6_MSG_RXED_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE5_MSG_RXED_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE4_MSG_RXED_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE3_MSG_RXED_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE2_MSG_RXED_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE1_MSG_RXED_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE0_MSG_RXED_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__CXM_TIMER1_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__CXM_TIMER0_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__MWS_RX_FE_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__MWS_RX_RE_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__MWS_TX_FE_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__MWS_TX_RE_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__EXT_FSYNC_RE_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__FSYNC_RE_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TX_FIFO_OVFL_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TX_FIFO_READY_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_FIFO_UDFL_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_FIFO_OVFL_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_FIFO_READY_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_BREAK_OFF_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_BREAK_ON_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_FRAMING_ERR_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__HOST_INT_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__HOST_INT_EN___S 31 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TX_ENA_RE_EN___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TX_ENA_RE_EN___S 30 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TX_ENA_FE_EN___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TX_ENA_FE_EN___S 29 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__DIRECT_MSG_TXED_EN___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__DIRECT_MSG_TXED_EN___S 28 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TCM_NACK_EN___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TCM_NACK_EN___S 27 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TCM_ACK_EN___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TCM_ACK_EN___S 26 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TDM_MISALIGN_EN___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TDM_MISALIGN_EN___S 25 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE7_MSG_RXED_EN___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE7_MSG_RXED_EN___S 24 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE6_MSG_RXED_EN___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE6_MSG_RXED_EN___S 23 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE5_MSG_RXED_EN___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE5_MSG_RXED_EN___S 22 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE4_MSG_RXED_EN___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE4_MSG_RXED_EN___S 21 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE3_MSG_RXED_EN___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE3_MSG_RXED_EN___S 20 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE2_MSG_RXED_EN___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE2_MSG_RXED_EN___S 19 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE1_MSG_RXED_EN___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE1_MSG_RXED_EN___S 18 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE0_MSG_RXED_EN___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TYPE0_MSG_RXED_EN___S 17 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__CXM_TIMER1_INT_EN___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__CXM_TIMER1_INT_EN___S 16 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__CXM_TIMER0_INT_EN___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__CXM_TIMER0_INT_EN___S 15 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__MWS_RX_FE_INT_EN___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__MWS_RX_FE_INT_EN___S 14 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__MWS_RX_RE_INT_EN___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__MWS_RX_RE_INT_EN___S 13 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__MWS_TX_FE_INT_EN___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__MWS_TX_FE_INT_EN___S 12 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__MWS_TX_RE_INT_EN___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__MWS_TX_RE_INT_EN___S 11 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__EXT_FSYNC_RE_INT_EN___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__EXT_FSYNC_RE_INT_EN___S 9 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__FSYNC_RE_INT_EN___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__FSYNC_RE_INT_EN___S 8 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TX_FIFO_OVFL_INT_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TX_FIFO_OVFL_INT_EN___S 7 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TX_FIFO_READY_INT_EN___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__TX_FIFO_READY_INT_EN___S 6 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_FIFO_UDFL_INT_EN___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_FIFO_UDFL_INT_EN___S 5 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_FIFO_OVFL_INT_EN___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_FIFO_OVFL_INT_EN___S 4 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_FIFO_READY_INT_EN___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_FIFO_READY_INT_EN___S 3 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_BREAK_OFF_INT_EN___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_BREAK_OFF_INT_EN___S 2 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_BREAK_ON_INT_EN___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_BREAK_ON_INT_EN___S 1 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_FRAMING_ERR_INT_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN__RX_FRAMING_ERR_INT_EN___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN___M 0xFFFFFBFF +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_EN___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_FSYNC_RE (0x005C5020) +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_FSYNC_RE___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_FSYNC_RE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_FSYNC_RE__VAL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_FSYNC_RE__VAL___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_FSYNC_RE__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_FSYNC_RE___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_FSYNC_RE___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_ACTIVE_RE (0x005C5024) +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_ACTIVE_RE___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_ACTIVE_RE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_ACTIVE_RE__VAL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_ACTIVE_RE__VAL___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_ACTIVE_RE__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_ACTIVE_RE___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_ACTIVE_RE___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_ACTIVE_FE (0x005C5028) +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_ACTIVE_FE___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_ACTIVE_FE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_ACTIVE_FE__VAL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_ACTIVE_FE__VAL___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_ACTIVE_FE__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_ACTIVE_FE___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_ACTIVE_FE___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_TX_RE (0x005C502C) +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_TX_RE___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_TX_RE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_TX_RE__VAL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_TX_RE__VAL___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_TX_RE__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_TX_RE___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_TX_RE___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_TX_FE (0x005C5030) +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_TX_FE___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_TX_FE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_TX_FE__VAL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_TX_FE__VAL___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_TX_FE__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_TX_FE___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_TX_FE___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_RX_RE (0x005C5034) +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_RX_RE___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_RX_RE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_RX_RE__VAL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_RX_RE__VAL___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_RX_RE__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_RX_RE___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_RX_RE___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_RX_FE (0x005C5038) +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_RX_FE___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_RX_FE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_RX_FE__VAL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_RX_FE__VAL___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_RX_FE__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_RX_FE___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_MWS_RX_FE___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE7 (0x005C503C) +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE7___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE7__VAL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE7__VAL___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE7__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE7___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE7___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE6 (0x005C5040) +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE6___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE6__VAL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE6__VAL___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE6__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE6___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE6___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE5 (0x005C5044) +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE5___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE5__VAL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE5__VAL___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE5__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE5___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE5___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE4 (0x005C5048) +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE4___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE4__VAL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE4__VAL___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE4__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE4___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE3 (0x005C504C) +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE3__VAL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE3__VAL___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE3__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE3___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE2 (0x005C5050) +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE2__VAL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE2__VAL___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE2__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE2___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE1 (0x005C5054) +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE1__VAL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE1__VAL___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE1__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE1___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE0 (0x005C5058) +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE0__VAL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE0__VAL___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE0__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_RX_TYPE0___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT1 (0x005C505C) +#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT1__TYPE3___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT1__TYPE2___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT1__TYPE1___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT1__TYPE0___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT1__TYPE3___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT1__TYPE3___S 24 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT1__TYPE2___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT1__TYPE2___S 16 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT1__TYPE1___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT1__TYPE1___S 8 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT1__TYPE0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT1__TYPE0___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT1___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT2 (0x005C5060) +#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT2__TYPE7___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT2__TYPE6___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT2__TYPE5___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT2__TYPE4___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT2__TYPE7___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT2__TYPE7___S 24 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT2__TYPE6___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT2__TYPE6___S 16 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT2__TYPE5___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT2__TYPE5___S 8 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT2__TYPE4___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT2__TYPE4___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_RX_CXM_MSG_CONTENT2___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1 (0x005C5064) +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_ORIDE_VAL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_ORIDE_ENA___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_VAL2___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_VAL1___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_ENA2___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_ENA1___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_BM___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_ORIDE_VAL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_ORIDE_ENA___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_VAL2___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_VAL1___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_ENA2___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_ENA1___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_BM___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_ORIDE_VAL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_ORIDE_ENA___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_VAL2___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_VAL1___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_ENA2___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_ENA1___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__INF_3W_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI___S 31 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_ORIDE_VAL___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_ORIDE_VAL___S 30 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_ORIDE_ENA___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_ORIDE_ENA___S 29 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_VAL2___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_VAL2___S 27 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_VAL1___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_VAL1___S 26 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_ENA2___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_ENA2___S 25 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_ENA1___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_PRI_ENA1___S 24 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT___S 23 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_BM___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_BM___S 22 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_SEL___M 0x00300000 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_SEL___S 20 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_ORIDE_VAL___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_ORIDE_VAL___S 19 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_ORIDE_ENA___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_ORIDE_ENA___S 18 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_VAL2___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_VAL2___S 16 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_VAL1___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_VAL1___S 15 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_ENA2___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_ENA2___S 14 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_ENA1___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__RX_GRANT_ENA1___S 13 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT___S 12 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_BM___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_BM___S 11 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_SEL___M 0x00000600 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_SEL___S 9 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_ORIDE_VAL___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_ORIDE_VAL___S 8 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_ORIDE_ENA___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_ORIDE_ENA___S 7 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_VAL2___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_VAL2___S 5 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_VAL1___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_VAL1___S 4 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_ENA2___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_ENA2___S 3 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_ENA1___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__TX_GRANT_ENA1___S 2 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__INF_3W_SEL___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1__INF_3W_SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1___M 0xEFFDFFBD +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL1___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL2 (0x005C5068) +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL2___POR 0x00000355 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL2__TOUT_VAL___POR 0x00000355 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL2__TOUT_VAL___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL2__TOUT_VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL2___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3 (0x005C506C) +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3___POR 0x00000003 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__FORCECLK_WBTMR___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__WB_CNT_LD_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__WB_CNT_LD_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER1_SW_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER0_SW_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__RST_UART___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__HOLD_SWITCH_TO_RX_END___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__BT_WAKEUP_OVWR___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__BT_WAKEUP_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__DIRECT_MSG_CONTENT___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER1_TRIGGER___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER0_TRIGGER___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER1_INT_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER0_INT_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__DIRECT_MSG_TX___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__WAKEUP_CLR_RTSM_DAT___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TX_MSG_ENA___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__FORCECLK_WBTMR___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__FORCECLK_WBTMR___S 24 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__WB_CNT_LD_SEL___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__WB_CNT_LD_SEL___S 23 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__WB_CNT_LD_EN___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__WB_CNT_LD_EN___S 22 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER1_SW_RST___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER1_SW_RST___S 21 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER0_SW_RST___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER0_SW_RST___S 20 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__RST_UART___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__RST_UART___S 19 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__HOLD_SWITCH_TO_RX_END___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__HOLD_SWITCH_TO_RX_END___S 18 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__BT_WAKEUP_OVWR___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__BT_WAKEUP_OVWR___S 17 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__BT_WAKEUP_SEL___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__BT_WAKEUP_SEL___S 16 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__DIRECT_MSG_CONTENT___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__DIRECT_MSG_CONTENT___S 8 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER1_TRIGGER___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER1_TRIGGER___S 7 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER0_TRIGGER___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER0_TRIGGER___S 6 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER1_INT_CTRL___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER1_INT_CTRL___S 4 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER0_INT_CTRL___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TIMER0_INT_CTRL___S 3 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__DIRECT_MSG_TX___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__DIRECT_MSG_TX___S 2 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__WAKEUP_CLR_RTSM_DAT___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__WAKEUP_CLR_RTSM_DAT___S 1 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TX_MSG_ENA___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3__TX_MSG_ENA___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3___M 0x01FFFFDF +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_CTRL3___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_TIMER0_INT_START (0x005C5070) +#define PHYA_IRON2G_RFA_WSI_CXM_TIMER0_INT_START___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_TIMER0_INT_START___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_TIMER0_INT_START__VAL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_TIMER0_INT_START__VAL___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_TIMER0_INT_START__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_TIMER0_INT_START___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_TIMER0_INT_START___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_TIMER0_INT_PERIOD (0x005C5074) +#define PHYA_IRON2G_RFA_WSI_CXM_TIMER0_INT_PERIOD___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_TIMER0_INT_PERIOD___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_TIMER0_INT_PERIOD__VAL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_TIMER0_INT_PERIOD__VAL___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_TIMER0_INT_PERIOD__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_TIMER0_INT_PERIOD___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_TIMER0_INT_PERIOD___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_TIMER1_INT_START (0x005C5078) +#define PHYA_IRON2G_RFA_WSI_CXM_TIMER1_INT_START___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_TIMER1_INT_START___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_TIMER1_INT_START__VAL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_TIMER1_INT_START__VAL___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_TIMER1_INT_START__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_TIMER1_INT_START___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_TIMER1_INT_START___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_TIMER1_INT_PERIOD (0x005C507C) +#define PHYA_IRON2G_RFA_WSI_CXM_TIMER1_INT_PERIOD___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_TIMER1_INT_PERIOD___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_TIMER1_INT_PERIOD__VAL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_TIMER1_INT_PERIOD__VAL___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_TIMER1_INT_PERIOD__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_TIMER1_INT_PERIOD___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_TIMER1_INT_PERIOD___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_TX_GRANT_THR1 (0x005C5080) +#define PHYA_IRON2G_RFA_WSI_CXM_TX_GRANT_THR1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_TX_GRANT_THR1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_TX_GRANT_THR1__VAL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_TX_GRANT_THR1__VAL___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_TX_GRANT_THR1__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_TX_GRANT_THR1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_TX_GRANT_THR1___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_TX_GRANT_THR2 (0x005C5084) +#define PHYA_IRON2G_RFA_WSI_CXM_TX_GRANT_THR2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_TX_GRANT_THR2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_TX_GRANT_THR2__VAL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_TX_GRANT_THR2__VAL___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_TX_GRANT_THR2__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_TX_GRANT_THR2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_TX_GRANT_THR2___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_RX_GRANT_THR1 (0x005C5088) +#define PHYA_IRON2G_RFA_WSI_CXM_RX_GRANT_THR1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_RX_GRANT_THR1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_GRANT_THR1__VAL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_GRANT_THR1__VAL___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_RX_GRANT_THR1__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_GRANT_THR1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_RX_GRANT_THR1___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_RX_GRANT_THR2 (0x005C508C) +#define PHYA_IRON2G_RFA_WSI_CXM_RX_GRANT_THR2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_RX_GRANT_THR2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_GRANT_THR2__VAL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_GRANT_THR2__VAL___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_RX_GRANT_THR2__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_GRANT_THR2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_RX_GRANT_THR2___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_RX_PRI_THR1 (0x005C5090) +#define PHYA_IRON2G_RFA_WSI_CXM_RX_PRI_THR1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_RX_PRI_THR1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_PRI_THR1__VAL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_PRI_THR1__VAL___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_RX_PRI_THR1__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_PRI_THR1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_RX_PRI_THR1___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_RX_PRI_THR2 (0x005C5094) +#define PHYA_IRON2G_RFA_WSI_CXM_RX_PRI_THR2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_RX_PRI_THR2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_PRI_THR2__VAL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_PRI_THR2__VAL___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_RX_PRI_THR2__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_RX_PRI_THR2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_RX_PRI_THR2___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_0 (0x005C50A0) +#define PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_0___POR 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_0__DBG_SEL___POR 0xFF +#define PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_0__FIFO_CONFIG___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_0__WL_DBG_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_0__DBG_SEL___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_0__DBG_SEL___S 24 +#define PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_0__FIFO_CONFIG___M 0x000C0000 +#define PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_0__FIFO_CONFIG___S 18 +#define PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_0__WL_DBG_SEL___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_0__WL_DBG_SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_0___M 0xFF0C000F +#define PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_0___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_1 (0x005C50A8) +#define PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_1___POR 0x00010000 +#define PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_1__DBG_EMPTY___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_1__DBG_VAL___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_1__DBG_EMPTY___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_1__DBG_EMPTY___S 16 +#define PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_1__DBG_VAL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_1__DBG_VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_1___M 0x0001FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_BT_DEBUG_1___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1 (0x005C50B0) +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1___POR 0x00000200 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WLAN_ST_OVERRIDE_VAL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WLAN_ST_OVERRIDE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WL_STATUS___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__SW_WL_STATUS_VAL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WL_STATUS_CLR_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WL_STATUS_SET_SEL___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__CRC8_EN___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WSIS_CFG_DESCRAMBLE_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WSI_SRC_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__INIT_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__INIT_START___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WLAN_ST_OVERRIDE_VAL___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WLAN_ST_OVERRIDE_VAL___S 14 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WLAN_ST_OVERRIDE___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WLAN_ST_OVERRIDE___S 13 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WL_STATUS___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WL_STATUS___S 12 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__SW_WL_STATUS_VAL___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__SW_WL_STATUS_VAL___S 11 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WL_STATUS_CLR_SEL___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WL_STATUS_CLR_SEL___S 10 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WL_STATUS_SET_SEL___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WL_STATUS_SET_SEL___S 9 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__CRC8_EN___M 0x000001F0 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__CRC8_EN___S 4 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WSIS_CFG_DESCRAMBLE_EN___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WSIS_CFG_DESCRAMBLE_EN___S 3 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WSI_SRC_SEL___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__WSI_SRC_SEL___S 2 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__INIT_DONE___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__INIT_DONE___S 1 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__INIT_START___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1__INIT_START___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1___M 0x00007FFF +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_1___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_2 (0x005C50B4) +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_2___RWC QCSR_REG_WO +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_2__WLAN_ODD_SEQ_SW_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_2__WLAN_SW_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_2__WLAN_ODD_SEQ_SW_RST___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_2__WLAN_ODD_SEQ_SW_RST___S 1 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_2__WLAN_SW_RST___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_2__WLAN_SW_RST___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_2___M 0x00000003 +#define PHYA_IRON2G_RFA_WSI_CXM_COMMON_CTRL_2___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1 (0x005C50B8) +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__LTE2WLAN_RST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__WLAN2LTE_RST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__COEX_WLAN2LTE_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__COEX_LTE2WLAN_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__TO_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__TO_CNT___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__LTE2WLAN_RST_EN___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__LTE2WLAN_RST_EN___S 12 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__WLAN2LTE_RST_EN___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__WLAN2LTE_RST_EN___S 11 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__COEX_WLAN2LTE_EN___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__COEX_WLAN2LTE_EN___S 10 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__COEX_LTE2WLAN_EN___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__COEX_LTE2WLAN_EN___S 9 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__TO_EN___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__TO_EN___S 8 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__TO_CNT___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1__TO_CNT___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1___M 0x00001FFF +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_CXM_CTRL_1___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_WSIS_CTRL_1 (0x005C50BC) +#define PHYA_IRON2G_RFA_WSI_CXM_WSIS_CTRL_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_WSIS_CTRL_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WSIS_CTRL_1__WSIS_DBG_FORCE_ERR___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WSIS_CTRL_1__WSIS_FORCE_NAK_STB___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WSIS_CTRL_1__WSIS_FORCE_IDLE_STB___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WSIS_CTRL_1__WSIS_SYNC_STATE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WSIS_CTRL_1__WSIS_DBG_FORCE_ERR___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_CXM_WSIS_CTRL_1__WSIS_DBG_FORCE_ERR___S 3 +#define PHYA_IRON2G_RFA_WSI_CXM_WSIS_CTRL_1__WSIS_FORCE_NAK_STB___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_CXM_WSIS_CTRL_1__WSIS_FORCE_NAK_STB___S 2 +#define PHYA_IRON2G_RFA_WSI_CXM_WSIS_CTRL_1__WSIS_FORCE_IDLE_STB___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_CXM_WSIS_CTRL_1__WSIS_FORCE_IDLE_STB___S 1 +#define PHYA_IRON2G_RFA_WSI_CXM_WSIS_CTRL_1__WSIS_SYNC_STATE___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_CXM_WSIS_CTRL_1__WSIS_SYNC_STATE___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_WSIS_CTRL_1___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_CXM_WSIS_CTRL_1___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST (0x005C50C0) +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST___RWC QCSR_REG_WO +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__TX_ASYNC_FIFO_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__TDM_TX_FIFO_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__WCI2_TX_FIFO_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__TDM_RX_FIFO_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__TDM_RX_ASFIFO_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__WCI2_RX_FIFO_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__WCI2_RX_ASFIFO_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__CPU_INTR_FIFO_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__CPU_INTR_ASFIFO_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__TX_ASYNC_FIFO_RST___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__TX_ASYNC_FIFO_RST___S 8 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__TDM_TX_FIFO_RST___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__TDM_TX_FIFO_RST___S 7 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__WCI2_TX_FIFO_RST___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__WCI2_TX_FIFO_RST___S 6 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__TDM_RX_FIFO_RST___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__TDM_RX_FIFO_RST___S 5 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__TDM_RX_ASFIFO_RST___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__TDM_RX_ASFIFO_RST___S 4 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__WCI2_RX_FIFO_RST___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__WCI2_RX_FIFO_RST___S 3 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__WCI2_RX_ASFIFO_RST___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__WCI2_RX_ASFIFO_RST___S 2 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__CPU_INTR_FIFO_RST___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__CPU_INTR_FIFO_RST___S 1 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__CPU_INTR_ASFIFO_RST___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST__CPU_INTR_ASFIFO_RST___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_FIFO_RST___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT (0x005C50C4) +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__MCI_CRC_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__WSIS_PARITY_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__MCI_MSG_STRUCT_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__MCI_MSG_TO_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RTSM_LIMIT_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RTSM_CNT1_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RTSM_CNT0_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__TX_ASYNC_FIFO_OVFL_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__TX_WCI2_FULL_OVFL_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__TX_TDM_FULL_OVFL_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_RTSM_FULL_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_WCI2_FULL_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_TDM_FULL_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_BREAK_OFF_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_BREAK_ON_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_FRAMING_ERR_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__MCI_CRC_INT___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__MCI_CRC_INT___S 15 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__WSIS_PARITY_INT___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__WSIS_PARITY_INT___S 14 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__MCI_MSG_STRUCT_INT___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__MCI_MSG_STRUCT_INT___S 13 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__MCI_MSG_TO_INT___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__MCI_MSG_TO_INT___S 12 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RTSM_LIMIT_INT___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RTSM_LIMIT_INT___S 11 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RTSM_CNT1_INT___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RTSM_CNT1_INT___S 10 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RTSM_CNT0_INT___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RTSM_CNT0_INT___S 9 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__TX_ASYNC_FIFO_OVFL_INT___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__TX_ASYNC_FIFO_OVFL_INT___S 8 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__TX_WCI2_FULL_OVFL_INT___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__TX_WCI2_FULL_OVFL_INT___S 7 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__TX_TDM_FULL_OVFL_INT___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__TX_TDM_FULL_OVFL_INT___S 6 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_RTSM_FULL_INT___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_RTSM_FULL_INT___S 5 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_WCI2_FULL_INT___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_WCI2_FULL_INT___S 4 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_TDM_FULL_INT___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_TDM_FULL_INT___S 3 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_BREAK_OFF_INT___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_BREAK_OFF_INT___S 2 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_BREAK_ON_INT___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_BREAK_ON_INT___S 1 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_FRAMING_ERR_INT___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT__RX_FRAMING_ERR_INT___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN (0x005C50C8) +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__MCI_CRC_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__WSIS_PARITY_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__MCI_MSG_STRUCT_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__MCI_MSG_TO_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RTSM_LIMIT_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RTSM_CNT1_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RTSM_CNT0_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__TX_ASYNC_FIFO_OVFL_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__TX_WCI2_FULL_OVFL_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__TX_TDM_FULL_OVFL_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_RTSM_FULL_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_WCI2_FULL_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_TDM_FULL_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_BREAK_OFF_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_BREAK_ON_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_FRAMING_ERR_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__MCI_CRC_INT_EN___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__MCI_CRC_INT_EN___S 15 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__WSIS_PARITY_INT_EN___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__WSIS_PARITY_INT_EN___S 14 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__MCI_MSG_STRUCT_INT_EN___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__MCI_MSG_STRUCT_INT_EN___S 13 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__MCI_MSG_TO_INT_EN___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__MCI_MSG_TO_INT_EN___S 12 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RTSM_LIMIT_INT_EN___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RTSM_LIMIT_INT_EN___S 11 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RTSM_CNT1_INT_EN___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RTSM_CNT1_INT_EN___S 10 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RTSM_CNT0_INT_EN___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RTSM_CNT0_INT_EN___S 9 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__TX_ASYNC_FIFO_OVFL_INT_EN___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__TX_ASYNC_FIFO_OVFL_INT_EN___S 8 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__TX_WCI2_FULL_OVFL_INT_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__TX_WCI2_FULL_OVFL_INT_EN___S 7 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__TX_TDM_FULL_OVFL_INT_EN___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__TX_TDM_FULL_OVFL_INT_EN___S 6 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_RTSM_FULL_INT_EN___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_RTSM_FULL_INT_EN___S 5 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_WCI2_FULL_INT_EN___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_WCI2_FULL_INT_EN___S 4 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_TDM_FULL_INT_EN___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_TDM_FULL_INT_EN___S 3 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_BREAK_OFF_INT_EN___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_BREAK_OFF_INT_EN___S 2 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_BREAK_ON_INT_EN___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_BREAK_ON_INT_EN___S 1 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_FRAMING_ERR_INT_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN__RX_FRAMING_ERR_INT_EN___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_EN___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK (0x005C50CC) +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK___POR 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__MCI_CRC_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__WSIS_PARITY_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__MCI_MSG_STRUCT_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__MCI_MSG_TO_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RTSM_LIMIT_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RTSM_CNT1_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RTSM_CNT0_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__TX_ASYNC_FIFO_OVFL_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__TX_WCI2_FULL_OVFL_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__TX_TDM_FULL_OVFL_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_RTSM_FULL_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_WCI2_FULL_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_TDM_FULL_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_BREAK_OFF_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_BREAK_ON_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_FRAMING_ERR_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__MCI_CRC_INT_UNMASK___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__MCI_CRC_INT_UNMASK___S 15 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__WSIS_PARITY_INT_UNMASK___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__WSIS_PARITY_INT_UNMASK___S 14 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__MCI_MSG_STRUCT_INT_UNMASK___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__MCI_MSG_STRUCT_INT_UNMASK___S 13 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__MCI_MSG_TO_INT_UNMASK___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__MCI_MSG_TO_INT_UNMASK___S 12 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RTSM_LIMIT_INT_UNMASK___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RTSM_LIMIT_INT_UNMASK___S 11 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RTSM_CNT1_INT_UNMASK___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RTSM_CNT1_INT_UNMASK___S 10 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RTSM_CNT0_INT_UNMASK___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RTSM_CNT0_INT_UNMASK___S 9 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__TX_ASYNC_FIFO_OVFL_INT_UNMASK___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__TX_ASYNC_FIFO_OVFL_INT_UNMASK___S 8 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__TX_WCI2_FULL_OVFL_INT_UNMASK___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__TX_WCI2_FULL_OVFL_INT_UNMASK___S 7 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__TX_TDM_FULL_OVFL_INT_UNMASK___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__TX_TDM_FULL_OVFL_INT_UNMASK___S 6 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_RTSM_FULL_INT_UNMASK___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_RTSM_FULL_INT_UNMASK___S 5 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_WCI2_FULL_INT_UNMASK___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_WCI2_FULL_INT_UNMASK___S 4 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_TDM_FULL_INT_UNMASK___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_TDM_FULL_INT_UNMASK___S 3 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_BREAK_OFF_INT_UNMASK___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_BREAK_OFF_INT_UNMASK___S 2 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_BREAK_ON_INT_UNMASK___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_BREAK_ON_INT_UNMASK___S 1 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_FRAMING_ERR_INT_UNMASK___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK__RX_FRAMING_ERR_INT_UNMASK___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WLAN_INT_UNMASK___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK (0x005C50E0) +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK___POR 0x7FFFFBFF +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TX_ENA_RE_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TX_ENA_FE_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__DIRECT_MSG_TXED_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TCM_NACK_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TCM_ACK_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TDM_MISALIGN_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE7_MSG_RXED_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE6_MSG_RXED_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE5_MSG_RXED_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE4_MSG_RXED_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE3_MSG_RXED_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE2_MSG_RXED_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE1_MSG_RXED_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE0_MSG_RXED_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__CXM_TIMER1_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__CXM_TIMER0_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__MWS_RX_FE_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__MWS_RX_RE_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__MWS_TX_FE_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__MWS_TX_RE_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__EXT_FSYNC_RE_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__FSYNC_RE_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TX_FIFO_OVFL_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TX_FIFO_READY_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_FIFO_UDFL_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_FIFO_OVFL_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_FIFO_READY_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_BREAK_OFF_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_BREAK_ON_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_FRAMING_ERR_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TX_ENA_RE_UNMASK___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TX_ENA_RE_UNMASK___S 30 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TX_ENA_FE_UNMASK___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TX_ENA_FE_UNMASK___S 29 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__DIRECT_MSG_TXED_UNMASK___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__DIRECT_MSG_TXED_UNMASK___S 28 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TCM_NACK_UNMASK___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TCM_NACK_UNMASK___S 27 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TCM_ACK_UNMASK___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TCM_ACK_UNMASK___S 26 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TDM_MISALIGN_UNMASK___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TDM_MISALIGN_UNMASK___S 25 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE7_MSG_RXED_UNMASK___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE7_MSG_RXED_UNMASK___S 24 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE6_MSG_RXED_UNMASK___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE6_MSG_RXED_UNMASK___S 23 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE5_MSG_RXED_UNMASK___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE5_MSG_RXED_UNMASK___S 22 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE4_MSG_RXED_UNMASK___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE4_MSG_RXED_UNMASK___S 21 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE3_MSG_RXED_UNMASK___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE3_MSG_RXED_UNMASK___S 20 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE2_MSG_RXED_UNMASK___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE2_MSG_RXED_UNMASK___S 19 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE1_MSG_RXED_UNMASK___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE1_MSG_RXED_UNMASK___S 18 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE0_MSG_RXED_UNMASK___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TYPE0_MSG_RXED_UNMASK___S 17 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__CXM_TIMER1_INT_UNMASK___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__CXM_TIMER1_INT_UNMASK___S 16 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__CXM_TIMER0_INT_UNMASK___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__CXM_TIMER0_INT_UNMASK___S 15 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__MWS_RX_FE_INT_UNMASK___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__MWS_RX_FE_INT_UNMASK___S 14 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__MWS_RX_RE_INT_UNMASK___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__MWS_RX_RE_INT_UNMASK___S 13 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__MWS_TX_FE_INT_UNMASK___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__MWS_TX_FE_INT_UNMASK___S 12 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__MWS_TX_RE_INT_UNMASK___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__MWS_TX_RE_INT_UNMASK___S 11 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__EXT_FSYNC_RE_INT_UNMASK___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__EXT_FSYNC_RE_INT_UNMASK___S 9 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__FSYNC_RE_INT_UNMASK___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__FSYNC_RE_INT_UNMASK___S 8 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TX_FIFO_OVFL_INT_UNMASK___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TX_FIFO_OVFL_INT_UNMASK___S 7 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TX_FIFO_READY_INT_UNMASK___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__TX_FIFO_READY_INT_UNMASK___S 6 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_FIFO_UDFL_INT_UNMASK___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_FIFO_UDFL_INT_UNMASK___S 5 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_FIFO_OVFL_INT_UNMASK___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_FIFO_OVFL_INT_UNMASK___S 4 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_FIFO_READY_INT_UNMASK___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_FIFO_READY_INT_UNMASK___S 3 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_BREAK_OFF_INT_UNMASK___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_BREAK_OFF_INT_UNMASK___S 2 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_BREAK_ON_INT_UNMASK___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_BREAK_ON_INT_UNMASK___S 1 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_FRAMING_ERR_INT_UNMASK___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK__RX_FRAMING_ERR_INT_UNMASK___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK___M 0x7FFFFBFF +#define PHYA_IRON2G_RFA_WSI_CXM_UART_INT_UNMASK___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_DTIM (0x005C50EC) +#define PHYA_IRON2G_RFA_WSI_CXM_DTIM___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_DTIM___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_DTIM__WIFI_PRI_HIGH___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_DTIM__WIFI_PRI_HIGH___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_CXM_DTIM__WIFI_PRI_HIGH___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_DTIM___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_CXM_DTIM___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE (0x005C5100) +#define PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE__TYPE6_RATS_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE__TYPE4_RATS_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE__TYPE3_RATS_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE__RATS_MODE1___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE__RATS_MODE0___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE__TYPE6_RATS_EN___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE__TYPE6_RATS_EN___S 4 +#define PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE__TYPE4_RATS_EN___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE__TYPE4_RATS_EN___S 3 +#define PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE__TYPE3_RATS_EN___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE__TYPE3_RATS_EN___S 2 +#define PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE__RATS_MODE1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE__RATS_MODE1___S 1 +#define PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE__RATS_MODE0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE__RATS_MODE0___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE___M 0x0000001F +#define PHYA_IRON2G_RFA_WSI_CXM_RATS_MODE___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG (0x005C5104) +#define PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG__RATS_RX_TO_CNT___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG__BT_TX_RATS_ID___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG__BT_RX_RATS_ID___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG__RATS_RX_TO_CNT___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG__RATS_RX_TO_CNT___S 8 +#define PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG__BT_TX_RATS_ID___M 0x000000F0 +#define PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG__BT_TX_RATS_ID___S 4 +#define PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG__BT_RX_RATS_ID___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG__BT_RX_RATS_ID___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT (0x005C5108) +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT__BT_MISSING_RATS_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT__BT_RATS_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT__BT_RATS_TO_INT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT__BT_MISSING_RATS_INT___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT__BT_MISSING_RATS_INT___S 2 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT__BT_RATS_INT___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT__BT_RATS_INT___S 1 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT__BT_RATS_TO_INT___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT__BT_RATS_TO_INT___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT___M 0x00000007 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_EN (0x005C510C) +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_EN___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_EN___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_EN__CXM_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_EN__BT_MISSING_RATS_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_EN__BT_RATS_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_EN__BT_RATS_TO_INT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_EN__CXM_INT_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_EN__CXM_INT_EN___S 31 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_EN__BT_MISSING_RATS_INT_EN___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_EN__BT_MISSING_RATS_INT_EN___S 2 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_EN__BT_RATS_INT_EN___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_EN__BT_RATS_INT_EN___S 1 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_EN__BT_RATS_TO_INT_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_EN__BT_RATS_TO_INT_EN___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_EN___M 0x80000007 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_EN___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_UNMASK (0x005C5110) +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_UNMASK___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_UNMASK___POR 0x00000007 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_UNMASK__BT_MISSING_RATS_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_UNMASK__BT_RATS_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_UNMASK__BT_RATS_TO_INT_UNMASK___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_UNMASK__BT_MISSING_RATS_INT_UNMASK___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_UNMASK__BT_MISSING_RATS_INT_UNMASK___S 2 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_UNMASK__BT_RATS_INT_UNMASK___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_UNMASK__BT_RATS_INT_UNMASK___S 1 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_UNMASK__BT_RATS_TO_INT_UNMASK___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_UNMASK__BT_RATS_TO_INT_UNMASK___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_UNMASK___M 0x00000007 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_INT_UNMASK___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_AOX_CTRL (0x005C5120) +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_AOX_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_AOX_CTRL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_AOX_CTRL__EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_AOX_CTRL__POS_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_AOX_CTRL__EN___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_AOX_CTRL__EN___S 2 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_AOX_CTRL__POS_SEL___M 0x00000003 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_AOX_CTRL__POS_SEL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_AOX_CTRL___M 0x00000007 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_AOX_CTRL___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL (0x005C5124) +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP2_RX_GNT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP1_RX_GNT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP0_RX_GNT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP2_TX_GNT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP1_TX_GNT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP0_TX_GNT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP2_RX_GNT_EN___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP2_RX_GNT_EN___S 10 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP1_RX_GNT_EN___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP1_RX_GNT_EN___S 9 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP0_RX_GNT_EN___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP0_RX_GNT_EN___S 8 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP2_TX_GNT_EN___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP2_TX_GNT_EN___S 2 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP1_TX_GNT_EN___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP1_TX_GNT_EN___S 1 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP0_TX_GNT_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL__PP0_TX_GNT_EN___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL___M 0x00000707 +#define PHYA_IRON2G_RFA_WSI_CXM_CXM_PP_CTRL___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_EXT_FS_RE (0x005C5128) +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_EXT_FS_RE___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_EXT_FS_RE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_EXT_FS_RE__VAL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_EXT_FS_RE__VAL___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_EXT_FS_RE__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_EXT_FS_RE___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_CXM_WB_CNT_EXT_FS_RE___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_SCAN_OBSERVE (0x005C512C) +#define PHYA_IRON2G_RFA_WSI_CXM_SCAN_OBSERVE___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_SCAN_OBSERVE___POR 0x00000001 +#define PHYA_IRON2G_RFA_WSI_CXM_SCAN_OBSERVE__TP_COMB_RST_XOR___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_SCAN_OBSERVE__TP_COMB_RST_XOR___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_CXM_SCAN_OBSERVE__TP_COMB_RST_XOR___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_SCAN_OBSERVE___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_CXM_SCAN_OBSERVE___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG2 (0x005C5130) +#define PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG2___POR 0x00000001 +#define PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG2__OLD_RTSM_DISCARD_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG2__WLAN_5G_XLNA_INSERT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG2__BT_TX_RATS_ID1___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG2__OLD_RTSM_DISCARD_EN___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG2__OLD_RTSM_DISCARD_EN___S 5 +#define PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG2__WLAN_5G_XLNA_INSERT_EN___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG2__WLAN_5G_XLNA_INSERT_EN___S 4 +#define PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG2__BT_TX_RATS_ID1___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG2__BT_TX_RATS_ID1___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG2___M 0x0000003F +#define PHYA_IRON2G_RFA_WSI_CXM_BT_RATS_CONFIG2___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RCVD_CNT (0x005C5134) +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RCVD_CNT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RCVD_CNT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RCVD_CNT__VAL___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RCVD_CNT__VAL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RCVD_CNT__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RCVD_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RCVD_CNT___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE1_RCVD_CNT (0x005C5138) +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE1_RCVD_CNT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE1_RCVD_CNT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE1_RCVD_CNT__VAL___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE1_RCVD_CNT__VAL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE1_RCVD_CNT__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE1_RCVD_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE1_RCVD_CNT___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_RCVD_CNT (0x005C513C) +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_RCVD_CNT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_RCVD_CNT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_RCVD_CNT__VAL___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_RCVD_CNT__VAL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_RCVD_CNT__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_RCVD_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_RCVD_CNT___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_LSB_NIBBLE_RCVD_CNT (0x005C5140) +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_LSB_NIBBLE_RCVD_CNT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_LSB_NIBBLE_RCVD_CNT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_LSB_NIBBLE_RCVD_CNT__VAL___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_LSB_NIBBLE_RCVD_CNT__VAL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_LSB_NIBBLE_RCVD_CNT__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_LSB_NIBBLE_RCVD_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_LSB_NIBBLE_RCVD_CNT___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_MSB_NIBBLE_RCVD_CNT (0x005C5144) +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_MSB_NIBBLE_RCVD_CNT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_MSB_NIBBLE_RCVD_CNT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_MSB_NIBBLE_RCVD_CNT__VAL___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_MSB_NIBBLE_RCVD_CNT__VAL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_MSB_NIBBLE_RCVD_CNT__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_MSB_NIBBLE_RCVD_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_MSB_NIBBLE_RCVD_CNT___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE3_RCVD_CNT (0x005C5148) +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE3_RCVD_CNT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE3_RCVD_CNT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE3_RCVD_CNT__VAL___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE3_RCVD_CNT__VAL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE3_RCVD_CNT__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE3_RCVD_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE3_RCVD_CNT___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE4_RCVD_CNT (0x005C514C) +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE4_RCVD_CNT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE4_RCVD_CNT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE4_RCVD_CNT__VAL___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE4_RCVD_CNT__VAL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE4_RCVD_CNT__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE4_RCVD_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE4_RCVD_CNT___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE5_RCVD_CNT (0x005C5150) +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE5_RCVD_CNT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE5_RCVD_CNT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE5_RCVD_CNT__VAL___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE5_RCVD_CNT__VAL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE5_RCVD_CNT__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE5_RCVD_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE5_RCVD_CNT___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE6_RCVD_CNT (0x005C5154) +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE6_RCVD_CNT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE6_RCVD_CNT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE6_RCVD_CNT__VAL___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE6_RCVD_CNT__VAL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE6_RCVD_CNT__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE6_RCVD_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE6_RCVD_CNT___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RCVD_CNT (0x005C5158) +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RCVD_CNT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RCVD_CNT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RCVD_CNT__VAL___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RCVD_CNT__VAL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RCVD_CNT__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RCVD_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RCVD_CNT___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_LEGACY_SENT_CNT (0x005C515C) +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_LEGACY_SENT_CNT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_LEGACY_SENT_CNT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_LEGACY_SENT_CNT__VAL___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_LEGACY_SENT_CNT__VAL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_LEGACY_SENT_CNT__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_LEGACY_SENT_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_LEGACY_SENT_CNT___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RATID0_SENT_CNT (0x005C5160) +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RATID0_SENT_CNT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RATID0_SENT_CNT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RATID0_SENT_CNT__VAL___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RATID0_SENT_CNT__VAL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RATID0_SENT_CNT__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RATID0_SENT_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RATID0_SENT_CNT___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RATID1_SENT_CNT (0x005C5164) +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RATID1_SENT_CNT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RATID1_SENT_CNT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RATID1_SENT_CNT__VAL___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RATID1_SENT_CNT__VAL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RATID1_SENT_CNT__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RATID1_SENT_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE0_RATID1_SENT_CNT___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE1_SENT_CNT (0x005C5168) +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE1_SENT_CNT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE1_SENT_CNT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE1_SENT_CNT__VAL___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE1_SENT_CNT__VAL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE1_SENT_CNT__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE1_SENT_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE1_SENT_CNT___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_SENT_CNT (0x005C516C) +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_SENT_CNT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_SENT_CNT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_SENT_CNT__VAL___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_SENT_CNT__VAL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_SENT_CNT__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_SENT_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_SENT_CNT___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_LSB_SENT_CNT (0x005C5170) +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_LSB_SENT_CNT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_LSB_SENT_CNT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_LSB_SENT_CNT__VAL___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_LSB_SENT_CNT__VAL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_LSB_SENT_CNT__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_LSB_SENT_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_LSB_SENT_CNT___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_MSB_SENT_CNT (0x005C5174) +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_MSB_SENT_CNT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_MSB_SENT_CNT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_MSB_SENT_CNT__VAL___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_MSB_SENT_CNT__VAL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_MSB_SENT_CNT__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_MSB_SENT_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE2_MSB_SENT_CNT___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE3_SENT_CNT (0x005C5178) +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE3_SENT_CNT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE3_SENT_CNT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE3_SENT_CNT__VAL___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE3_SENT_CNT__VAL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE3_SENT_CNT__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE3_SENT_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE3_SENT_CNT___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE4_SENT_CNT (0x005C517C) +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE4_SENT_CNT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE4_SENT_CNT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE4_SENT_CNT__VAL___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE4_SENT_CNT__VAL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE4_SENT_CNT__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE4_SENT_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE4_SENT_CNT___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE5_SENT_CNT (0x005C5180) +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE5_SENT_CNT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE5_SENT_CNT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE5_SENT_CNT__VAL___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE5_SENT_CNT__VAL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE5_SENT_CNT__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE5_SENT_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE5_SENT_CNT___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE6_SENT_CNT (0x005C5184) +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE6_SENT_CNT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE6_SENT_CNT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE6_SENT_CNT__VAL___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE6_SENT_CNT__VAL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE6_SENT_CNT__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE6_SENT_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE6_SENT_CNT___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_SENT_CNT (0x005C5188) +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_SENT_CNT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_SENT_CNT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_SENT_CNT__VAL___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_SENT_CNT__VAL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_SENT_CNT__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_SENT_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_SENT_CNT___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RATID0_SENT_CNT (0x005C518C) +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RATID0_SENT_CNT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RATID0_SENT_CNT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RATID0_SENT_CNT__VAL___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RATID0_SENT_CNT__VAL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RATID0_SENT_CNT__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RATID0_SENT_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RATID0_SENT_CNT___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RATID1_SENT_CNT (0x005C5190) +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RATID1_SENT_CNT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RATID1_SENT_CNT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RATID1_SENT_CNT__VAL___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RATID1_SENT_CNT__VAL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RATID1_SENT_CNT__VAL___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RATID1_SENT_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_TYPE7_RATID1_SENT_CNT___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN (0x005C5194) +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE7_RATID1_SENT_CNT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE7_RATID0_SENT_CNT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE7_SENT_CNT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE6_SENT_CNT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE5_SENT_CNT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE4_SENT_CNT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE3_SENT_CNT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_MSB_SENT_CNT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_LSB_SENT_CNT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_SENT_CNT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE1_SENT_CNT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE0_RATID1_SENT_CNT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE0_RATID0_SENT_CNT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE0_LEGACY_SENT_CNT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE7_RCVD_CNT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE6_RCVD_CNT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE5_RCVD_CNT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE4_RCVD_CNT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE3_RCVD_CNT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_MSB_NIBBLE_RCVD_CNT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_LSB_NIBBLE_RCVD_CNT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_RCVD_CNT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE1_RCVD_CNT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE0_RCVD_CNT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE7_RATID1_SENT_CNT_EN___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE7_RATID1_SENT_CNT_EN___S 29 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE7_RATID0_SENT_CNT_EN___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE7_RATID0_SENT_CNT_EN___S 28 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE7_SENT_CNT_EN___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE7_SENT_CNT_EN___S 27 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE6_SENT_CNT_EN___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE6_SENT_CNT_EN___S 26 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE5_SENT_CNT_EN___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE5_SENT_CNT_EN___S 25 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE4_SENT_CNT_EN___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE4_SENT_CNT_EN___S 24 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE3_SENT_CNT_EN___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE3_SENT_CNT_EN___S 23 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_MSB_SENT_CNT_EN___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_MSB_SENT_CNT_EN___S 22 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_LSB_SENT_CNT_EN___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_LSB_SENT_CNT_EN___S 21 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_SENT_CNT_EN___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_SENT_CNT_EN___S 20 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE1_SENT_CNT_EN___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE1_SENT_CNT_EN___S 19 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE0_RATID1_SENT_CNT_EN___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE0_RATID1_SENT_CNT_EN___S 18 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE0_RATID0_SENT_CNT_EN___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE0_RATID0_SENT_CNT_EN___S 17 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE0_LEGACY_SENT_CNT_EN___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE0_LEGACY_SENT_CNT_EN___S 16 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE7_RCVD_CNT_EN___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE7_RCVD_CNT_EN___S 9 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE6_RCVD_CNT_EN___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE6_RCVD_CNT_EN___S 8 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE5_RCVD_CNT_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE5_RCVD_CNT_EN___S 7 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE4_RCVD_CNT_EN___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE4_RCVD_CNT_EN___S 6 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE3_RCVD_CNT_EN___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE3_RCVD_CNT_EN___S 5 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_MSB_NIBBLE_RCVD_CNT_EN___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_MSB_NIBBLE_RCVD_CNT_EN___S 4 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_LSB_NIBBLE_RCVD_CNT_EN___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_LSB_NIBBLE_RCVD_CNT_EN___S 3 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_RCVD_CNT_EN___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE2_RCVD_CNT_EN___S 2 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE1_RCVD_CNT_EN___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE1_RCVD_CNT_EN___S 1 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE0_RCVD_CNT_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN__TYPE0_RCVD_CNT_EN___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN___M 0x3FFF03FF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_EN___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST (0x005C5198) +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST___RWC QCSR_REG_WO +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE7_RATID1_SENT_CNT_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE7_RATID0_SENT_CNT_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE7_SENT_CNT_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE6_SENT_CNT_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE5_SENT_CNT_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE4_SENT_CNT_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE3_SENT_CNT_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_MSB_SENT_CNT_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_LSB_SENT_CNT_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_SENT_CNT_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE1_SENT_CNT_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE0_RATID1_SENT_CNT_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE0_RATID0_SENT_CNT_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE0_LEGACY_SENT_CNT_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE7_RCVD_CNT_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE6_RCVD_CNT_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE5_RCVD_CNT_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE4_RCVD_CNT_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE3_RCVD_CNT_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_MSB_NIBBLE_RCVD_CNT_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_LSB_NIBBLE_RCVD_CNT_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_RCVD_CNT_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE1_RCVD_CNT_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE0_RCVD_CNT_RST___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE7_RATID1_SENT_CNT_RST___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE7_RATID1_SENT_CNT_RST___S 29 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE7_RATID0_SENT_CNT_RST___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE7_RATID0_SENT_CNT_RST___S 28 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE7_SENT_CNT_RST___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE7_SENT_CNT_RST___S 27 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE6_SENT_CNT_RST___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE6_SENT_CNT_RST___S 26 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE5_SENT_CNT_RST___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE5_SENT_CNT_RST___S 25 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE4_SENT_CNT_RST___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE4_SENT_CNT_RST___S 24 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE3_SENT_CNT_RST___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE3_SENT_CNT_RST___S 23 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_MSB_SENT_CNT_RST___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_MSB_SENT_CNT_RST___S 22 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_LSB_SENT_CNT_RST___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_LSB_SENT_CNT_RST___S 21 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_SENT_CNT_RST___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_SENT_CNT_RST___S 20 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE1_SENT_CNT_RST___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE1_SENT_CNT_RST___S 19 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE0_RATID1_SENT_CNT_RST___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE0_RATID1_SENT_CNT_RST___S 18 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE0_RATID0_SENT_CNT_RST___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE0_RATID0_SENT_CNT_RST___S 17 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE0_LEGACY_SENT_CNT_RST___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE0_LEGACY_SENT_CNT_RST___S 16 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE7_RCVD_CNT_RST___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE7_RCVD_CNT_RST___S 9 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE6_RCVD_CNT_RST___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE6_RCVD_CNT_RST___S 8 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE5_RCVD_CNT_RST___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE5_RCVD_CNT_RST___S 7 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE4_RCVD_CNT_RST___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE4_RCVD_CNT_RST___S 6 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE3_RCVD_CNT_RST___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE3_RCVD_CNT_RST___S 5 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_MSB_NIBBLE_RCVD_CNT_RST___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_MSB_NIBBLE_RCVD_CNT_RST___S 4 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_LSB_NIBBLE_RCVD_CNT_RST___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_LSB_NIBBLE_RCVD_CNT_RST___S 3 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_RCVD_CNT_RST___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE2_RCVD_CNT_RST___S 2 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE1_RCVD_CNT_RST___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE1_RCVD_CNT_RST___S 1 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE0_RCVD_CNT_RST___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST__TYPE0_RCVD_CNT_RST___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST___M 0x3FFF03FF +#define PHYA_IRON2G_RFA_WSI_CXM_CL_MCIM_CNTR_RST___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_0 (0x005C51F0) +#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_0__SPARE_REG___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_0__SPARE_REG___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_0__SPARE_REG___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_0___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_1 (0x005C51F4) +#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_1__SPARE_REG___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_1__SPARE_REG___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_1__SPARE_REG___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_1___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_2 (0x005C51F8) +#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_2__SPARE_REG___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_2__SPARE_REG___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_2__SPARE_REG___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_2___S 0 + +#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_3 (0x005C51FC) +#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_3__SPARE_REG___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_3__SPARE_REG___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_3__SPARE_REG___S 0 +#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_CXM_SPARE_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LPO2M (0x005D1000) +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LPO2M___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LPO2M___POR 0x00000008 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LPO2M__CORE_LPO2M_TRIM___POR 0x8 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LPO2M__CORE_LPO2M_TRIM___M 0x0000000F +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LPO2M__CORE_LPO2M_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LPO2M___M 0x0000000F +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LPO2M___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LFRC (0x005D1004) +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LFRC___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LFRC___POR 0x00000080 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LFRC__CORE_LFRC_TRIM___POR 0x80 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LFRC__CORE_LFRC_TRIM___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LFRC__CORE_LFRC_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LFRC___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LFRC___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_HFRC (0x005D1008) +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_HFRC___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_HFRC___POR 0x00000008 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_HFRC__CORE_HFRC_TRIM___POR 0x8 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_HFRC__CORE_HFRC_TRIM___M 0x0000000F +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_HFRC__CORE_HFRC_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_HFRC___M 0x0000000F +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_HFRC___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_0 (0x005D100C) +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_0___POR 0x000000AF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_0__CORE_LDOAO_VSET_HIGH___POR 0xAF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_0__CORE_LDOAO_VSET_HIGH___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_0__CORE_LDOAO_VSET_HIGH___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_1 (0x005D1010) +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_1___POR 0x0000005C +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_1__CORE_LDOAO_VSET_LOW___POR 0x5C +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_1__CORE_LDOAO_VSET_LOW___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_1__CORE_LDOAO_VSET_LOW___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_2 (0x005D1014) +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_2___POR 0x00000076 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_2__CORE_LDOAO_SVS_TRIM___POR 0x76 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_2__CORE_LDOAO_SVS_TRIM___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_2__CORE_LDOAO_SVS_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_3 (0x005D1018) +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_3___POR 0x0000005C +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_3__CORE_LDOAO_LSVS_TRIM___POR 0x5C +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_3__CORE_LDOAO_LSVS_TRIM___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_3__CORE_LDOAO_LSVS_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_CORE_LDO08AO_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_BTCMX_PROGRAMMING_0 (0x005D101C) +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_BTCMX_PROGRAMMING_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_BTCMX_PROGRAMMING_0___POR 0x000000AF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_BTCMX_PROGRAMMING_0__BTCMX_VSET_HIGH___POR 0xAF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_BTCMX_PROGRAMMING_0__BTCMX_VSET_HIGH___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_BTCMX_PROGRAMMING_0__BTCMX_VSET_HIGH___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_BTCMX_PROGRAMMING_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_BTCMX_PROGRAMMING_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_BTCMX_PROGRAMMING_1 (0x005D1020) +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_BTCMX_PROGRAMMING_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_BTCMX_PROGRAMMING_1___POR 0x0000003D +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_BTCMX_PROGRAMMING_1__BTCMX_VSET_LOW___POR 0x3D +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_BTCMX_PROGRAMMING_1__BTCMX_VSET_LOW___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_BTCMX_PROGRAMMING_1__BTCMX_VSET_LOW___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_BTCMX_PROGRAMMING_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_BTCMX_PROGRAMMING_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_0 (0x005D1024) +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_0___POR 0x0000009F +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_0__WLCX_VSET_HIGH___POR 0x9F +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_0__WLCX_VSET_HIGH___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_0__WLCX_VSET_HIGH___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_1 (0x005D1028) +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_1___POR 0x00000020 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_1__WLCX_VSET_LOW___POR 0x20 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_1__WLCX_VSET_LOW___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_1__WLCX_VSET_LOW___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_2 (0x005D102C) +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_2___POR 0x00000076 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_2__WLCX_SVS_TRIM___POR 0x76 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_2__WLCX_SVS_TRIM___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_2__WLCX_SVS_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_3 (0x005D1030) +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_3___POR 0x00000089 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_3__WLCX_L1_TRIM___POR 0x89 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_3__WLCX_L1_TRIM___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_3__WLCX_L1_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLCX_PROGRAMMING_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_0 (0x005D1034) +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_0___POR 0x000000AF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_0__WLMX_VSET_HIGH___POR 0xAF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_0__WLMX_VSET_HIGH___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_0__WLMX_VSET_HIGH___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_1 (0x005D1038) +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_1___POR 0x0000003D +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_1__WLMX_VSET_LOW___POR 0x3D +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_1__WLMX_VSET_LOW___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_1__WLMX_VSET_LOW___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_2 (0x005D103C) +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_2___POR 0x000000AF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_2__WLMX_SVS_TRIM___POR 0xAF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_2__WLMX_SVS_TRIM___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_2__WLMX_SVS_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_3 (0x005D1040) +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_3___POR 0x000000AF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_3__WLMX_LSVS_TRIM___POR 0xAF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_3__WLMX_LSVS_TRIM___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_3__WLMX_LSVS_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_4 (0x005D1044) +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_4___POR 0x000000AF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_4__WLMX_L1_TRIM___POR 0xAF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_4__WLMX_L1_TRIM___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_4__WLMX_L1_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_4___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_WLMX_PROGRAMMING_4___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFACMN_PROGRAMMING_0 (0x005D1048) +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFACMN_PROGRAMMING_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFACMN_PROGRAMMING_0___POR 0x0000009F +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFACMN_PROGRAMMING_0__RFACMN_VSET_HIGH___POR 0x9F +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFACMN_PROGRAMMING_0__RFACMN_VSET_HIGH___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFACMN_PROGRAMMING_0__RFACMN_VSET_HIGH___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFACMN_PROGRAMMING_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFACMN_PROGRAMMING_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFACMN_PROGRAMMING_1 (0x005D104C) +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFACMN_PROGRAMMING_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFACMN_PROGRAMMING_1___POR 0x00000020 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFACMN_PROGRAMMING_1__RFACMN_VSET_LOW___POR 0x20 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFACMN_PROGRAMMING_1__RFACMN_VSET_LOW___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFACMN_PROGRAMMING_1__RFACMN_VSET_LOW___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFACMN_PROGRAMMING_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFACMN_PROGRAMMING_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA08_PROGRAMMING_0 (0x005D1050) +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA08_PROGRAMMING_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA08_PROGRAMMING_0___POR 0x0000009F +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA08_PROGRAMMING_0__RFA08_VSET_HIGH___POR 0x9F +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA08_PROGRAMMING_0__RFA08_VSET_HIGH___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA08_PROGRAMMING_0__RFA08_VSET_HIGH___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA08_PROGRAMMING_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA08_PROGRAMMING_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA08_PROGRAMMING_1 (0x005D1054) +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA08_PROGRAMMING_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA08_PROGRAMMING_1___POR 0x0000009F +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA08_PROGRAMMING_1__RFA08_VSET_LOW___POR 0x9F +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA08_PROGRAMMING_1__RFA08_VSET_LOW___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA08_PROGRAMMING_1__RFA08_VSET_LOW___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA08_PROGRAMMING_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA08_PROGRAMMING_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA12_PROGRAMMING_0 (0x005D1058) +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA12_PROGRAMMING_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA12_PROGRAMMING_0___POR 0x00000039 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA12_PROGRAMMING_0__RFA12_VSET_HIGH___POR 0x39 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA12_PROGRAMMING_0__RFA12_VSET_HIGH___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA12_PROGRAMMING_0__RFA12_VSET_HIGH___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA12_PROGRAMMING_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA12_PROGRAMMING_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA12_PROGRAMMING_1 (0x005D105C) +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA12_PROGRAMMING_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA12_PROGRAMMING_1___POR 0x00000039 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA12_PROGRAMMING_1__RFA12_VSET_LOW___POR 0x39 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA12_PROGRAMMING_1__RFA12_VSET_LOW___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA12_PROGRAMMING_1__RFA12_VSET_LOW___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA12_PROGRAMMING_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA12_PROGRAMMING_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE09_PROGRAMMING_0 (0x005D1060) +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE09_PROGRAMMING_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE09_PROGRAMMING_0___POR 0x000000C6 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE09_PROGRAMMING_0__PCIE09_VSET_HIGH___POR 0xC6 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE09_PROGRAMMING_0__PCIE09_VSET_HIGH___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE09_PROGRAMMING_0__PCIE09_VSET_HIGH___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE09_PROGRAMMING_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE09_PROGRAMMING_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE09_PROGRAMMING_1 (0x005D1064) +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE09_PROGRAMMING_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE09_PROGRAMMING_1___POR 0x000000C6 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE09_PROGRAMMING_1__PCIE09_VSET_LOW___POR 0xC6 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE09_PROGRAMMING_1__PCIE09_VSET_LOW___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE09_PROGRAMMING_1__PCIE09_VSET_LOW___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE09_PROGRAMMING_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE09_PROGRAMMING_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA17_PROGRAMMING_0 (0x005D1068) +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA17_PROGRAMMING_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA17_PROGRAMMING_0___POR 0x00000079 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA17_PROGRAMMING_0__RFA17_VSET_HIGH___POR 0x79 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA17_PROGRAMMING_0__RFA17_VSET_HIGH___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA17_PROGRAMMING_0__RFA17_VSET_HIGH___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA17_PROGRAMMING_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA17_PROGRAMMING_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA17_PROGRAMMING_1 (0x005D106C) +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA17_PROGRAMMING_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA17_PROGRAMMING_1___POR 0x00000079 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA17_PROGRAMMING_1__RFA17_VSET_LOW___POR 0x79 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA17_PROGRAMMING_1__RFA17_VSET_LOW___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA17_PROGRAMMING_1__RFA17_VSET_LOW___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA17_PROGRAMMING_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_RFA17_PROGRAMMING_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE18_PROGRAMMING_0 (0x005D1070) +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE18_PROGRAMMING_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE18_PROGRAMMING_0___POR 0x00000086 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE18_PROGRAMMING_0__PCIE18_VSET_HIGH___POR 0x86 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE18_PROGRAMMING_0__PCIE18_VSET_HIGH___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE18_PROGRAMMING_0__PCIE18_VSET_HIGH___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE18_PROGRAMMING_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE18_PROGRAMMING_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE18_PROGRAMMING_1 (0x005D1074) +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE18_PROGRAMMING_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE18_PROGRAMMING_1___POR 0x00000086 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE18_PROGRAMMING_1__PCIE18_VSET_LOW___POR 0x86 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE18_PROGRAMMING_1__PCIE18_VSET_LOW___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE18_PROGRAMMING_1__PCIE18_VSET_LOW___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE18_PROGRAMMING_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_PCIE18_PROGRAMMING_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_SPAREA (0x005D1078) +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_SPAREA___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_SPAREA___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_SPAREA__TRIM_SPAREA___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_SPAREA__TRIM_SPAREA___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_SPAREA__TRIM_SPAREA___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_SPAREA___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_SPAREA___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_SPAREB (0x005D107C) +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_SPAREB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_SPAREB___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_SPAREB__TRIM_SPAREB___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_SPAREB__TRIM_SPAREB___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_SPAREB__TRIM_SPAREB___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_SPAREB___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_OTP_TRIM_PMU_SPAREB___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_AO_SVS (0x005D1080) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_AO_SVS___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_AO_SVS___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_AO_SVS__RO_OTP_TRIM_AO_SVS___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_AO_SVS__RO_OTP_TRIM_AO_SVS___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_AO_SVS__RO_OTP_TRIM_AO_SVS___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_AO_SVS___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_AO_SVS___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_AO_LSVS (0x005D1084) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_AO_LSVS___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_AO_LSVS___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_AO_LSVS__RO_OTP_TRIM_AO_LSVS___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_AO_LSVS__RO_OTP_TRIM_AO_LSVS___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_AO_LSVS__RO_OTP_TRIM_AO_LSVS___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_AO_LSVS___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_AO_LSVS___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLCX_SVS (0x005D1088) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLCX_SVS___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLCX_SVS___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLCX_SVS__RO_OTP_TRIM_WLCX_SVS___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLCX_SVS__RO_OTP_TRIM_WLCX_SVS___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLCX_SVS__RO_OTP_TRIM_WLCX_SVS___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLCX_SVS___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLCX_SVS___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLCX_L1 (0x005D108C) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLCX_L1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLCX_L1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLCX_L1__RO_OTP_TRIM_WLCX_L1___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLCX_L1__RO_OTP_TRIM_WLCX_L1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLCX_L1__RO_OTP_TRIM_WLCX_L1___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLCX_L1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLCX_L1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_SVS (0x005D1090) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_SVS___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_SVS___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_SVS__RO_OTP_TRIM_WLMX_SVS___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_SVS__RO_OTP_TRIM_WLMX_SVS___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_SVS__RO_OTP_TRIM_WLMX_SVS___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_SVS___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_SVS___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_LSVS (0x005D1094) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_LSVS___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_LSVS___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_LSVS__RO_OTP_TRIM_WLMX_LSVS___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_LSVS__RO_OTP_TRIM_WLMX_LSVS___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_LSVS__RO_OTP_TRIM_WLMX_LSVS___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_LSVS___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_LSVS___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_L1 (0x005D1098) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_L1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_L1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_L1__RO_OTP_TRIM_WLMX_L1___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_L1__RO_OTP_TRIM_WLMX_L1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_L1__RO_OTP_TRIM_WLMX_L1___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_L1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_WLMX_L1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_SPAREA (0x005D109C) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_SPAREA___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_SPAREA___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_SPAREA__RO_OTP_TRIM_SPAREA___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_SPAREA__RO_OTP_TRIM_SPAREA___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_SPAREA__RO_OTP_TRIM_SPAREA___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_SPAREA___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_SPAREA___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_SPAREB (0x005D10A0) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_SPAREB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_SPAREB___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_SPAREB__RO_OTP_TRIM_SPAREB___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_SPAREB__RO_OTP_TRIM_SPAREB___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_SPAREB__RO_OTP_TRIM_SPAREB___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_SPAREB___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_OTP_TRIM_PMU_SPAREB___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_VER (0x005D10C0) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_VER___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_VER___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_VER__RO_CORE_MAJOR_VERSION___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_VER__RO_CORE_MINOR_VERSION___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_VER__RO_CORE_MAJOR_VERSION___M 0x000000F0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_VER__RO_CORE_MAJOR_VERSION___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_VER__RO_CORE_MINOR_VERSION___M 0x0000000F +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_VER__RO_CORE_MINOR_VERSION___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_VER___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_VER___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LPO2M (0x005D10C4) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LPO2M___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LPO2M___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LPO2M__CORE_LPO2M_EN_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LPO2M__CORE_LPO2M_DTEST0_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LPO2M__CORE_LPO2M_DTEST1_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LPO2M__CORE_LPO2M_EN_OVR___M 0x0000000C +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LPO2M__CORE_LPO2M_EN_OVR___S 2 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LPO2M__CORE_LPO2M_DTEST0_EN___M 0x00000002 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LPO2M__CORE_LPO2M_DTEST0_EN___S 1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LPO2M__CORE_LPO2M_DTEST1_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LPO2M__CORE_LPO2M_DTEST1_EN___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LPO2M___M 0x0000000F +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LPO2M___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LFRC (0x005D10C8) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LFRC___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LFRC___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LFRC__CORE_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LFRC__CORE_LFRC_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LFRC__CORE_LFRC_EN_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LFRC__D_LFRC_DIV2_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LFRC__CORE_BYPASS___M 0x00000080 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LFRC__CORE_BYPASS___S 7 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LFRC__CORE_LFRC_DIS___M 0x00000040 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LFRC__CORE_LFRC_DIS___S 6 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LFRC__CORE_LFRC_EN_OVR___M 0x00000030 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LFRC__CORE_LFRC_EN_OVR___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LFRC__D_LFRC_DIV2_EN___M 0x00000008 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LFRC__D_LFRC_DIV2_EN___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LFRC___M 0x000000F8 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LFRC___S 3 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_HFRC (0x005D10CC) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_HFRC___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_HFRC___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_HFRC__CORE_SPAREB___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_HFRC__CORE_HFRC_EN_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_HFRC__CORE_SPAREB___M 0x000000C0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_HFRC__CORE_SPAREB___S 6 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_HFRC__CORE_HFRC_EN_OVR___M 0x00000030 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_HFRC__CORE_HFRC_EN_OVR___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_HFRC___M 0x000000F0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_HFRC___S 4 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDOAO_SET (0x005D10D0) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDOAO_SET___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDOAO_SET___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDOAO_SET__CORE_LDOAO_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDOAO_SET__CORE_VREG_TYPE___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDOAO_SET__CORE_SPARE4___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDOAO_SET__CORE_LDOAO_VSET_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDOAO_SET__CORE_LDOAO_DIS___M 0x00000080 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDOAO_SET__CORE_LDOAO_DIS___S 7 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDOAO_SET__CORE_VREG_TYPE___M 0x00000040 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDOAO_SET__CORE_VREG_TYPE___S 6 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDOAO_SET__CORE_SPARE4___M 0x0000003C +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDOAO_SET__CORE_SPARE4___S 2 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDOAO_SET__CORE_LDOAO_VSET_OVR___M 0x00000003 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDOAO_SET__CORE_LDOAO_VSET_OVR___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDOAO_SET___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDOAO_SET___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_CORE (0x005D10D4) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_CORE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_CORE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_CORE__CORE_ATB_ISEL___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_CORE__CORE_ATB_VSEL___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_CORE__CORE_ATB_ISEL___M 0x000000F0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_CORE__CORE_ATB_ISEL___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_CORE__CORE_ATB_VSEL___M 0x0000000F +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_CORE__CORE_ATB_VSEL___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_CORE___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_CORE___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG0 (0x005D10D8) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG0__CORE_ATB_REG0___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG0__CORE_ATB_REG0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG0__CORE_ATB_REG0___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG1 (0x005D10DC) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG1__CORE_ATB_REG1___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG1__CORE_ATB_REG1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG1__CORE_ATB_REG1___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG2 (0x005D10E0) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG2__CORE_ATB_REG2___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG2__CORE_ATB_REG2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG2__CORE_ATB_REG2___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG3 (0x005D10E4) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG3__CORE_ATB_REG3___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG3__CORE_ATB_REG3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG3__CORE_ATB_REG3___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG4 (0x005D10E8) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG4__CORE_ATB_REG4___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG4__CORE_ATB_REG4___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG4__CORE_ATB_REG4___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG4___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_ATB_REG4___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTEST (0x005D10EC) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTEST___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTEST___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTEST__CORE_DTEST1_CFG___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTEST__CORE_DTEST0_CFG___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTEST__CORE_DTEST1_CFG___M 0x000000F0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTEST__CORE_DTEST1_CFG___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTEST__CORE_DTEST0_CFG___M 0x0000000F +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTEST__CORE_DTEST0_CFG___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTEST___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTEST___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDO08AO_2 (0x005D10F0) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDO08AO_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDO08AO_2___POR 0x00000004 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDO08AO_2__CORE_LP_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDO08AO_2__CORE_SPARE2___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDO08AO_2__CORE_FAULT_TH___POR 0x2 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDO08AO_2__CORE_EN_FAULTMON___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDO08AO_2__CORE_LP_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDO08AO_2__CORE_LP_EN___S 7 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDO08AO_2__CORE_SPARE2___M 0x00000078 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDO08AO_2__CORE_SPARE2___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDO08AO_2__CORE_FAULT_TH___M 0x00000006 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDO08AO_2__CORE_FAULT_TH___S 1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDO08AO_2__CORE_EN_FAULTMON___M 0x00000001 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDO08AO_2__CORE_EN_FAULTMON___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDO08AO_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_LDO08AO_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_LDO08AO_3 (0x005D10F4) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_LDO08AO_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_LDO08AO_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT2_OS___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT2_US___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT1_OS___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT1_US___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT2_OS___M 0x00000020 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT2_OS___S 5 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT2_US___M 0x00000010 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT2_US___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT1_OS___M 0x00000002 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT1_OS___S 1 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT1_US___M 0x00000001 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_LDO08AO_3__RO_CORE_FAULT1_US___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_LDO08AO_3___M 0x00000033 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_LDO08AO_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_0 (0x005D10F8) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_0__CORE_DTESTO_0_IGNORE_H___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_0__CORE_DTESTO_0_IGNORE_H___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_0__CORE_DTESTO_0_IGNORE_H___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_1 (0x005D10FC) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_1__CORE_DTESTO_0_IGNORE_L___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_1__CORE_DTESTO_0_IGNORE_L___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_1__CORE_DTESTO_0_IGNORE_L___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_2 (0x005D1100) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_2__CORE_DTESTO_1_IGNORE_H___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_2__CORE_DTESTO_1_IGNORE_H___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_2__CORE_DTESTO_1_IGNORE_H___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_3 (0x005D1104) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_3__CORE_DTESTO_1_IGNORE_L___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_3__CORE_DTESTO_1_IGNORE_L___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_3__CORE_DTESTO_1_IGNORE_L___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_CORE_DTESTO_IGNORE_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_0 (0x005D1108) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_0__RO_CORE_FAULT1_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_0__RO_CORE_FAULT1_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_0__RO_CORE_FAULT1_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_1 (0x005D110C) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_1__RO_CORE_FAULT1_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_1__RO_CORE_FAULT1_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_1__RO_CORE_FAULT1_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_2 (0x005D1110) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_2__RO_CORE_FAULT1_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_2__RO_CORE_FAULT1_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_2__RO_CORE_FAULT1_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_3 (0x005D1114) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_3__RO_CORE_FAULT1_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_3__RO_CORE_FAULT1_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_3__RO_CORE_FAULT1_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT1_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_0 (0x005D1118) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_0__RO_CORE_FAULT2_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_0__RO_CORE_FAULT2_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_0__RO_CORE_FAULT2_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_1 (0x005D111C) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_1__RO_CORE_FAULT2_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_1__RO_CORE_FAULT2_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_1__RO_CORE_FAULT2_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_2 (0x005D1120) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_2__RO_CORE_FAULT2_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_2__RO_CORE_FAULT2_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_2__RO_CORE_FAULT2_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_3 (0x005D1124) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_3__RO_CORE_FAULT2_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_3__RO_CORE_FAULT2_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_3__RO_CORE_FAULT2_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_CORE_FAULT2_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2 (0x005D1128) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2___POR 0x00000065 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_LP_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_SS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_VS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_STEPPER_FORCE_TARGET___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_STEPPER_STEP___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_STEPPER_DELAY___POR 0x5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_LP_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_LP_EN___S 7 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_SS_EN___M 0x00000040 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_SS_EN___S 6 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_VS_EN___M 0x00000020 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_VS_EN___S 5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_STEPPER_FORCE_TARGET___M 0x00000010 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_STEPPER_FORCE_TARGET___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_STEPPER_STEP___M 0x00000008 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_STEPPER_STEP___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_STEPPER_DELAY___M 0x00000007 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2__BTCMX_STEPPER_DELAY___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_3 (0x005D112C) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_3__BTCMX_EN_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_3__BTCMX_VSET_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_3__BTCMX_TRIM___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_3__BTCMX_EN_OVR___M 0x000000E0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_3__BTCMX_EN_OVR___S 5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_3__BTCMX_VSET_OVR___M 0x00000018 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_3__BTCMX_VSET_OVR___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_3__BTCMX_TRIM___M 0x00000007 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_3__BTCMX_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_PROGRAMMING_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0 (0x005D1130) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0___POR 0x00000004 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0__BTCMX_VREG_TYPE___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0__BTCMX_MODE_FSM_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0__BTCMX_MODE_FSM_OVR_VALUE___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0__BTCMX_FAULT_THRESHOLD___POR 0x2 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0__BTCMX_ENABLE_FAULT_MONITORING___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0__BTCMX_VREG_TYPE___M 0x00000080 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0__BTCMX_VREG_TYPE___S 7 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0__BTCMX_MODE_FSM_OVR___M 0x00000040 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0__BTCMX_MODE_FSM_OVR___S 6 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0__BTCMX_MODE_FSM_OVR_VALUE___M 0x00000038 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0__BTCMX_MODE_FSM_OVR_VALUE___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0__BTCMX_FAULT_THRESHOLD___M 0x00000006 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0__BTCMX_FAULT_THRESHOLD___S 1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0__BTCMX_ENABLE_FAULT_MONITORING___M 0x00000001 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0__BTCMX_ENABLE_FAULT_MONITORING___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_1 (0x005D1134) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_1__RO_BTCMX_SPARE5___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_1__RO_BTCMX_OK_REG___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_1__RO_BTCMX_MODE_FSM_STATE___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_1__RO_BTCMX_SPARE5___M 0x000000F0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_1__RO_BTCMX_SPARE5___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_1__RO_BTCMX_OK_REG___M 0x00000008 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_1__RO_BTCMX_OK_REG___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_1__RO_BTCMX_MODE_FSM_STATE___M 0x00000007 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_1__RO_BTCMX_MODE_FSM_STATE___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_2 (0x005D1138) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_2___POR 0x00000010 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_2__BTCMX_SPARE6___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_2__BTCMX_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_2__BTCMX_EN_LIM___POR 0x1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_2__BTCMX_LIMIT___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_2__BTCMX_SPARE6___M 0x000000C0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_2__BTCMX_SPARE6___S 6 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_2__BTCMX_BYPASS___M 0x00000020 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_2__BTCMX_BYPASS___S 5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_2__BTCMX_EN_LIM___M 0x00000010 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_2__BTCMX_EN_LIM___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_2__BTCMX_LIMIT___M 0x0000000F +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_2__BTCMX_LIMIT___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BTCMX_STATE_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_3 (0x005D113C) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT2_OS___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT2_US___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT1_OS___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT1_US___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT2_OS___M 0x00000008 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT2_OS___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT2_US___M 0x00000004 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT2_US___S 2 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT1_OS___M 0x00000002 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT1_OS___S 1 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT1_US___M 0x00000001 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_3__RO_BTCMX_FAULT1_US___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_3___M 0x0000000F +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_STATE_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_0 (0x005D1140) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_0__RO_BTCMX_FAULT1_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_0__RO_BTCMX_FAULT1_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_0__RO_BTCMX_FAULT1_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_1 (0x005D1144) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_1__RO_BTCMX_FAULT1_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_1__RO_BTCMX_FAULT1_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_1__RO_BTCMX_FAULT1_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_2 (0x005D1148) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_2__RO_BTCMX_FAULT1_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_2__RO_BTCMX_FAULT1_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_2__RO_BTCMX_FAULT1_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_3 (0x005D114C) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_3__RO_BTCMX_FAULT1_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_3__RO_BTCMX_FAULT1_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_3__RO_BTCMX_FAULT1_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT1_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_0 (0x005D1150) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_0__RO_BTCMX_FAULT2_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_0__RO_BTCMX_FAULT2_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_0__RO_BTCMX_FAULT2_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_1 (0x005D1154) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_1__RO_BTCMX_FAULT2_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_1__RO_BTCMX_FAULT2_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_1__RO_BTCMX_FAULT2_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_2 (0x005D1158) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_2__RO_BTCMX_FAULT2_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_2__RO_BTCMX_FAULT2_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_2__RO_BTCMX_FAULT2_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_3 (0x005D115C) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_3__RO_BTCMX_FAULT2_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_3__RO_BTCMX_FAULT2_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_3__RO_BTCMX_FAULT2_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_BTCMX_FAULT2_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2 (0x005D1160) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2___POR 0x00000065 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_LP_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_SS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_VS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_STEPPER_FORCE_TARGET___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_STEPPER_STEP___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_STEPPER_DELAY___POR 0x5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_LP_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_LP_EN___S 7 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_SS_EN___M 0x00000040 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_SS_EN___S 6 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_VS_EN___M 0x00000020 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_VS_EN___S 5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_STEPPER_FORCE_TARGET___M 0x00000010 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_STEPPER_FORCE_TARGET___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_STEPPER_STEP___M 0x00000008 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_STEPPER_STEP___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_STEPPER_DELAY___M 0x00000007 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2__WLCX_STEPPER_DELAY___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_3 (0x005D1164) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_3__WLCX_EN_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_3__WLCX_VSET_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_3__WLCX_TRIM___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_3__WLCX_EN_OVR___M 0x000000E0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_3__WLCX_EN_OVR___S 5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_3__WLCX_VSET_OVR___M 0x00000018 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_3__WLCX_VSET_OVR___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_3__WLCX_TRIM___M 0x00000007 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_3__WLCX_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_PROGRAMMING_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0 (0x005D1168) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0___POR 0x00000004 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0__WLCX_VREG_TYPE___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0__WLCX_MODE_FSM_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0__WLCX_MODE_FSM_OVR_VALUE___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0__WLCX_FAULT_THRESHOLD___POR 0x2 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0__WLCX_ENABLE_FAULT_MONITORING___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0__WLCX_VREG_TYPE___M 0x00000080 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0__WLCX_VREG_TYPE___S 7 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0__WLCX_MODE_FSM_OVR___M 0x00000040 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0__WLCX_MODE_FSM_OVR___S 6 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0__WLCX_MODE_FSM_OVR_VALUE___M 0x00000038 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0__WLCX_MODE_FSM_OVR_VALUE___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0__WLCX_FAULT_THRESHOLD___M 0x00000006 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0__WLCX_FAULT_THRESHOLD___S 1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0__WLCX_ENABLE_FAULT_MONITORING___M 0x00000001 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0__WLCX_ENABLE_FAULT_MONITORING___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_1 (0x005D116C) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_1__RO_WLCX_SPARE5___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_1__RO_WLCX_OK_REG___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_1__RO_WLCX_MODE_FSM_STATE___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_1__RO_WLCX_SPARE5___M 0x000000F0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_1__RO_WLCX_SPARE5___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_1__RO_WLCX_OK_REG___M 0x00000008 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_1__RO_WLCX_OK_REG___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_1__RO_WLCX_MODE_FSM_STATE___M 0x00000007 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_1__RO_WLCX_MODE_FSM_STATE___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_2 (0x005D1170) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_2___POR 0x00000010 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_2__WLCX_SPARE6___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_2__WLCX_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_2__WLCX_EN_LIM___POR 0x1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_2__WLCX_LIMIT___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_2__WLCX_SPARE6___M 0x000000C0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_2__WLCX_SPARE6___S 6 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_2__WLCX_BYPASS___M 0x00000020 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_2__WLCX_BYPASS___S 5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_2__WLCX_EN_LIM___M 0x00000010 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_2__WLCX_EN_LIM___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_2__WLCX_LIMIT___M 0x0000000F +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_2__WLCX_LIMIT___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLCX_STATE_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_3 (0x005D1174) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT2_OS___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT2_US___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT1_OS___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT1_US___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT2_OS___M 0x00000008 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT2_OS___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT2_US___M 0x00000004 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT2_US___S 2 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT1_OS___M 0x00000002 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT1_OS___S 1 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT1_US___M 0x00000001 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_3__RO_WLCX_FAULT1_US___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_3___M 0x0000000F +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_STATE_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_0 (0x005D1178) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_0__RO_WLCX_FAULT1_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_0__RO_WLCX_FAULT1_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_0__RO_WLCX_FAULT1_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_1 (0x005D117C) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_1__RO_WLCX_FAULT1_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_1__RO_WLCX_FAULT1_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_1__RO_WLCX_FAULT1_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_2 (0x005D1180) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_2__RO_WLCX_FAULT1_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_2__RO_WLCX_FAULT1_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_2__RO_WLCX_FAULT1_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_3 (0x005D1184) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_3__RO_WLCX_FAULT1_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_3__RO_WLCX_FAULT1_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_3__RO_WLCX_FAULT1_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT1_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_0 (0x005D1188) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_0__RO_WLCX_FAULT2_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_0__RO_WLCX_FAULT2_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_0__RO_WLCX_FAULT2_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_1 (0x005D118C) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_1__RO_WLCX_FAULT2_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_1__RO_WLCX_FAULT2_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_1__RO_WLCX_FAULT2_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_2 (0x005D1190) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_2__RO_WLCX_FAULT2_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_2__RO_WLCX_FAULT2_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_2__RO_WLCX_FAULT2_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_3 (0x005D1194) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_3__RO_WLCX_FAULT2_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_3__RO_WLCX_FAULT2_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_3__RO_WLCX_FAULT2_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLCX_FAULT2_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2 (0x005D1198) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2___POR 0x00000065 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_LP_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_SS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_VS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_STEPPER_FORCE_TARGET___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_STEPPER_STEP___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_STEPPER_DELAY___POR 0x5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_LP_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_LP_EN___S 7 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_SS_EN___M 0x00000040 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_SS_EN___S 6 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_VS_EN___M 0x00000020 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_VS_EN___S 5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_STEPPER_FORCE_TARGET___M 0x00000010 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_STEPPER_FORCE_TARGET___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_STEPPER_STEP___M 0x00000008 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_STEPPER_STEP___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_STEPPER_DELAY___M 0x00000007 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2__WLMX_STEPPER_DELAY___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_3 (0x005D119C) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_3__WLMX_EN_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_3__WLMX_VSET_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_3__WLMX_TRIM___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_3__WLMX_EN_OVR___M 0x000000E0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_3__WLMX_EN_OVR___S 5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_3__WLMX_VSET_OVR___M 0x00000018 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_3__WLMX_VSET_OVR___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_3__WLMX_TRIM___M 0x00000007 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_3__WLMX_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_PROGRAMMING_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0 (0x005D11A0) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0___POR 0x00000004 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0__WLMX_VREG_TYPE___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0__WLMX_MODE_FSM_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0__WLMX_MODE_FSM_OVR_VALUE___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0__WLMX_FAULT_THRESHOLD___POR 0x2 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0__WLMX_ENABLE_FAULT_MONITORING___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0__WLMX_VREG_TYPE___M 0x00000080 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0__WLMX_VREG_TYPE___S 7 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0__WLMX_MODE_FSM_OVR___M 0x00000040 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0__WLMX_MODE_FSM_OVR___S 6 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0__WLMX_MODE_FSM_OVR_VALUE___M 0x00000038 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0__WLMX_MODE_FSM_OVR_VALUE___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0__WLMX_FAULT_THRESHOLD___M 0x00000006 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0__WLMX_FAULT_THRESHOLD___S 1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0__WLMX_ENABLE_FAULT_MONITORING___M 0x00000001 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0__WLMX_ENABLE_FAULT_MONITORING___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_1 (0x005D11A4) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_1__RO_WLMX_SPARE5___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_1__RO_WLMX_OK_REG___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_1__RO_WLMX_MODE_FSM_STATE___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_1__RO_WLMX_SPARE5___M 0x000000F0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_1__RO_WLMX_SPARE5___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_1__RO_WLMX_OK_REG___M 0x00000008 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_1__RO_WLMX_OK_REG___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_1__RO_WLMX_MODE_FSM_STATE___M 0x00000007 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_1__RO_WLMX_MODE_FSM_STATE___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_2 (0x005D11A8) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_2___POR 0x00000010 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_2__WLMX_SPARE6___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_2__WLMX_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_2__WLMX_EN_LIM___POR 0x1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_2__WLMX_LIMIT___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_2__WLMX_SPARE6___M 0x000000C0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_2__WLMX_SPARE6___S 6 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_2__WLMX_BYPASS___M 0x00000020 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_2__WLMX_BYPASS___S 5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_2__WLMX_EN_LIM___M 0x00000010 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_2__WLMX_EN_LIM___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_2__WLMX_LIMIT___M 0x0000000F +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_2__WLMX_LIMIT___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_WLMX_STATE_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_3 (0x005D11AC) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT2_OS___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT2_US___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT1_OS___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT1_US___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT2_OS___M 0x00000008 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT2_OS___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT2_US___M 0x00000004 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT2_US___S 2 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT1_OS___M 0x00000002 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT1_OS___S 1 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT1_US___M 0x00000001 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_3__RO_WLMX_FAULT1_US___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_3___M 0x0000000F +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_STATE_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_0 (0x005D11B0) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_0__RO_WLMX_FAULT1_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_0__RO_WLMX_FAULT1_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_0__RO_WLMX_FAULT1_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_1 (0x005D11B4) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_1__RO_WLMX_FAULT1_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_1__RO_WLMX_FAULT1_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_1__RO_WLMX_FAULT1_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_2 (0x005D11B8) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_2__RO_WLMX_FAULT1_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_2__RO_WLMX_FAULT1_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_2__RO_WLMX_FAULT1_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_3 (0x005D11BC) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_3__RO_WLMX_FAULT1_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_3__RO_WLMX_FAULT1_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_3__RO_WLMX_FAULT1_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT1_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_0 (0x005D11C0) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_0__RO_WLMX_FAULT2_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_0__RO_WLMX_FAULT2_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_0__RO_WLMX_FAULT2_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_1 (0x005D11C4) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_1__RO_WLMX_FAULT2_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_1__RO_WLMX_FAULT2_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_1__RO_WLMX_FAULT2_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_2 (0x005D11C8) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_2__RO_WLMX_FAULT2_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_2__RO_WLMX_FAULT2_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_2__RO_WLMX_FAULT2_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_3 (0x005D11CC) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_3__RO_WLMX_FAULT2_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_3__RO_WLMX_FAULT2_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_3__RO_WLMX_FAULT2_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_WLMX_FAULT2_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2 (0x005D11D0) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2___POR 0x00000065 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_LP_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_SS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_VS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_STEPPER_FORCE_TARGET___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_STEPPER_STEP___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_STEPPER_DELAY___POR 0x5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_LP_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_LP_EN___S 7 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_SS_EN___M 0x00000040 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_SS_EN___S 6 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_VS_EN___M 0x00000020 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_VS_EN___S 5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_STEPPER_FORCE_TARGET___M 0x00000010 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_STEPPER_FORCE_TARGET___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_STEPPER_STEP___M 0x00000008 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_STEPPER_STEP___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_STEPPER_DELAY___M 0x00000007 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2__RFACMN_STEPPER_DELAY___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_3 (0x005D11D4) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_3__RFACMN_EN_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_3__RFACMN_VSET_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_3__RFACMN_TRIM___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_3__RFACMN_EN_OVR___M 0x000000E0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_3__RFACMN_EN_OVR___S 5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_3__RFACMN_VSET_OVR___M 0x00000018 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_3__RFACMN_VSET_OVR___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_3__RFACMN_TRIM___M 0x00000007 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_3__RFACMN_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_PROGRAMMING_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0 (0x005D11D8) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0__RFACMN_VREG_TYPE___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0__RFACMN_MODE_FSM_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0__RFACMN_MODE_FSM_OVR_VALUE___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0__RFACMN_FAULT_THRESHOLD___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0__RFACMN_ENABLE_FAULT_MONITORING___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0__RFACMN_VREG_TYPE___M 0x00000080 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0__RFACMN_VREG_TYPE___S 7 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0__RFACMN_MODE_FSM_OVR___M 0x00000040 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0__RFACMN_MODE_FSM_OVR___S 6 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0__RFACMN_MODE_FSM_OVR_VALUE___M 0x00000038 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0__RFACMN_MODE_FSM_OVR_VALUE___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0__RFACMN_FAULT_THRESHOLD___M 0x00000006 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0__RFACMN_FAULT_THRESHOLD___S 1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0__RFACMN_ENABLE_FAULT_MONITORING___M 0x00000001 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0__RFACMN_ENABLE_FAULT_MONITORING___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_1 (0x005D11DC) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_1__RO_RFACMN_SPARE5___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_1__RO_RFACMN_OK_REG___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_1__RO_RFACMN_MODE_FSM_STATE___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_1__RO_RFACMN_SPARE5___M 0x000000F0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_1__RO_RFACMN_SPARE5___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_1__RO_RFACMN_OK_REG___M 0x00000008 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_1__RO_RFACMN_OK_REG___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_1__RO_RFACMN_MODE_FSM_STATE___M 0x00000007 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_1__RO_RFACMN_MODE_FSM_STATE___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_2 (0x005D11E0) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_2___POR 0x00000010 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_2__RFACMN_SPARE6___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_2__RFACMN_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_2__RFACMN_EN_LIM___POR 0x1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_2__RFACMN_LIMIT___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_2__RFACMN_SPARE6___M 0x000000C0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_2__RFACMN_SPARE6___S 6 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_2__RFACMN_BYPASS___M 0x00000020 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_2__RFACMN_BYPASS___S 5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_2__RFACMN_EN_LIM___M 0x00000010 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_2__RFACMN_EN_LIM___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_2__RFACMN_LIMIT___M 0x0000000F +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_2__RFACMN_LIMIT___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFACMN_STATE_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_3 (0x005D11E4) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT2_OS___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT2_US___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT1_OS___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT1_US___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT2_OS___M 0x00000008 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT2_OS___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT2_US___M 0x00000004 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT2_US___S 2 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT1_OS___M 0x00000002 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT1_OS___S 1 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT1_US___M 0x00000001 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_3__RO_RFACMN_FAULT1_US___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_3___M 0x0000000F +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_STATE_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_0 (0x005D11E8) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_0__RO_RFACMN_FAULT1_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_0__RO_RFACMN_FAULT1_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_0__RO_RFACMN_FAULT1_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_1 (0x005D11EC) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_1__RO_RFACMN_FAULT1_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_1__RO_RFACMN_FAULT1_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_1__RO_RFACMN_FAULT1_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_2 (0x005D11F0) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_2__RO_RFACMN_FAULT1_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_2__RO_RFACMN_FAULT1_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_2__RO_RFACMN_FAULT1_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_3 (0x005D11F4) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_3__RO_RFACMN_FAULT1_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_3__RO_RFACMN_FAULT1_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_3__RO_RFACMN_FAULT1_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT1_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_0 (0x005D11F8) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_0__RO_RFACMN_FAULT2_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_0__RO_RFACMN_FAULT2_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_0__RO_RFACMN_FAULT2_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_1 (0x005D11FC) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_1__RO_RFACMN_FAULT2_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_1__RO_RFACMN_FAULT2_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_1__RO_RFACMN_FAULT2_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_2 (0x005D1200) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_2__RO_RFACMN_FAULT2_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_2__RO_RFACMN_FAULT2_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_2__RO_RFACMN_FAULT2_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_3 (0x005D1204) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_3__RO_RFACMN_FAULT2_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_3__RO_RFACMN_FAULT2_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_3__RO_RFACMN_FAULT2_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFACMN_FAULT2_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2 (0x005D1208) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2___POR 0x00000065 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_LP_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_SS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_VS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_STEPPER_FORCE_TARGET___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_STEPPER_STEP___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_STEPPER_DELAY___POR 0x5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_LP_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_LP_EN___S 7 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_SS_EN___M 0x00000040 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_SS_EN___S 6 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_VS_EN___M 0x00000020 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_VS_EN___S 5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_STEPPER_FORCE_TARGET___M 0x00000010 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_STEPPER_FORCE_TARGET___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_STEPPER_STEP___M 0x00000008 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_STEPPER_STEP___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_STEPPER_DELAY___M 0x00000007 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2__RFA08_STEPPER_DELAY___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_3 (0x005D120C) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_3__RFA08_EN_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_3__RFA08_VSET_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_3__RFA08_TRIM___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_3__RFA08_EN_OVR___M 0x000000E0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_3__RFA08_EN_OVR___S 5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_3__RFA08_VSET_OVR___M 0x00000018 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_3__RFA08_VSET_OVR___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_3__RFA08_TRIM___M 0x00000007 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_3__RFA08_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_PROGRAMMING_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0 (0x005D1210) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0___POR 0x00000004 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0__RFA08_VREG_TYPE___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0__RFA08_MODE_FSM_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0__RFA08_MODE_FSM_OVR_VALUE___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0__RFA08_FAULT_THRESHOLD___POR 0x2 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0__RFA08_ENABLE_FAULT_MONITORING___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0__RFA08_VREG_TYPE___M 0x00000080 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0__RFA08_VREG_TYPE___S 7 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0__RFA08_MODE_FSM_OVR___M 0x00000040 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0__RFA08_MODE_FSM_OVR___S 6 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0__RFA08_MODE_FSM_OVR_VALUE___M 0x00000038 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0__RFA08_MODE_FSM_OVR_VALUE___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0__RFA08_FAULT_THRESHOLD___M 0x00000006 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0__RFA08_FAULT_THRESHOLD___S 1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0__RFA08_ENABLE_FAULT_MONITORING___M 0x00000001 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0__RFA08_ENABLE_FAULT_MONITORING___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_1 (0x005D1214) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_1__RO_RFA08_SPARE5___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_1__RO_RFA08_OK_REG___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_1__RO_RFA08_MODE_FSM_STATE___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_1__RO_RFA08_SPARE5___M 0x000000F0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_1__RO_RFA08_SPARE5___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_1__RO_RFA08_OK_REG___M 0x00000008 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_1__RO_RFA08_OK_REG___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_1__RO_RFA08_MODE_FSM_STATE___M 0x00000007 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_1__RO_RFA08_MODE_FSM_STATE___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_2 (0x005D1218) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_2___POR 0x00000010 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_2__RFA08_SPARE6___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_2__RFA08_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_2__RFA08_EN_LIM___POR 0x1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_2__RFA08_LIMIT___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_2__RFA08_SPARE6___M 0x000000C0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_2__RFA08_SPARE6___S 6 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_2__RFA08_BYPASS___M 0x00000020 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_2__RFA08_BYPASS___S 5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_2__RFA08_EN_LIM___M 0x00000010 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_2__RFA08_EN_LIM___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_2__RFA08_LIMIT___M 0x0000000F +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_2__RFA08_LIMIT___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA08_STATE_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_3 (0x005D121C) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT2_OS___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT2_US___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT1_OS___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT1_US___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT2_OS___M 0x00000008 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT2_OS___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT2_US___M 0x00000004 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT2_US___S 2 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT1_OS___M 0x00000002 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT1_OS___S 1 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT1_US___M 0x00000001 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_3__RO_RFA08_FAULT1_US___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_3___M 0x0000000F +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_STATE_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_0 (0x005D1220) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_0__RO_RFA08_FAULT1_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_0__RO_RFA08_FAULT1_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_0__RO_RFA08_FAULT1_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_1 (0x005D1224) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_1__RO_RFA08_FAULT1_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_1__RO_RFA08_FAULT1_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_1__RO_RFA08_FAULT1_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_2 (0x005D1228) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_2__RO_RFA08_FAULT1_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_2__RO_RFA08_FAULT1_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_2__RO_RFA08_FAULT1_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_3 (0x005D122C) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_3__RO_RFA08_FAULT1_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_3__RO_RFA08_FAULT1_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_3__RO_RFA08_FAULT1_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT1_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_0 (0x005D1230) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_0__RO_RFA08_FAULT2_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_0__RO_RFA08_FAULT2_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_0__RO_RFA08_FAULT2_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_1 (0x005D1234) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_1__RO_RFA08_FAULT2_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_1__RO_RFA08_FAULT2_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_1__RO_RFA08_FAULT2_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_2 (0x005D1238) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_2__RO_RFA08_FAULT2_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_2__RO_RFA08_FAULT2_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_2__RO_RFA08_FAULT2_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_3 (0x005D123C) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_3__RO_RFA08_FAULT2_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_3__RO_RFA08_FAULT2_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_3__RO_RFA08_FAULT2_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA08_FAULT2_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2 (0x005D1240) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2___POR 0x00000065 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_LP_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_SS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_VS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_STEPPER_FORCE_TARGET___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_STEPPER_STEP___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_STEPPER_DELAY___POR 0x5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_LP_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_LP_EN___S 7 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_SS_EN___M 0x00000040 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_SS_EN___S 6 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_VS_EN___M 0x00000020 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_VS_EN___S 5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_STEPPER_FORCE_TARGET___M 0x00000010 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_STEPPER_FORCE_TARGET___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_STEPPER_STEP___M 0x00000008 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_STEPPER_STEP___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_STEPPER_DELAY___M 0x00000007 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2__RFA12_STEPPER_DELAY___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_3 (0x005D1244) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_3__RFA12_EN_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_3__RFA12_VSET_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_3__RFA12_TRIM___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_3__RFA12_EN_OVR___M 0x000000E0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_3__RFA12_EN_OVR___S 5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_3__RFA12_VSET_OVR___M 0x00000018 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_3__RFA12_VSET_OVR___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_3__RFA12_TRIM___M 0x00000007 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_3__RFA12_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_PROGRAMMING_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0 (0x005D1248) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0___POR 0x00000084 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0__RFA12_VREG_TYPE___POR 0x1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0__RFA12_MODE_FSM_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0__RFA12_MODE_FSM_OVR_VALUE___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0__RFA12_FAULT_THRESHOLD___POR 0x2 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0__RFA12_ENABLE_FAULT_MONITORING___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0__RFA12_VREG_TYPE___M 0x00000080 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0__RFA12_VREG_TYPE___S 7 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0__RFA12_MODE_FSM_OVR___M 0x00000040 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0__RFA12_MODE_FSM_OVR___S 6 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0__RFA12_MODE_FSM_OVR_VALUE___M 0x00000038 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0__RFA12_MODE_FSM_OVR_VALUE___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0__RFA12_FAULT_THRESHOLD___M 0x00000006 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0__RFA12_FAULT_THRESHOLD___S 1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0__RFA12_ENABLE_FAULT_MONITORING___M 0x00000001 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0__RFA12_ENABLE_FAULT_MONITORING___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_1 (0x005D124C) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_1__RO_RFA12_SPARE5___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_1__RO_RFA12_OK_REG___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_1__RO_RFA12_MODE_FSM_STATE___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_1__RO_RFA12_SPARE5___M 0x000000F0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_1__RO_RFA12_SPARE5___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_1__RO_RFA12_OK_REG___M 0x00000008 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_1__RO_RFA12_OK_REG___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_1__RO_RFA12_MODE_FSM_STATE___M 0x00000007 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_1__RO_RFA12_MODE_FSM_STATE___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_2 (0x005D1250) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_2___POR 0x00000010 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_2__RFA12_SPARE6___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_2__RFA12_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_2__RFA12_EN_LIM___POR 0x1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_2__RFA12_LIMIT___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_2__RFA12_SPARE6___M 0x000000C0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_2__RFA12_SPARE6___S 6 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_2__RFA12_BYPASS___M 0x00000020 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_2__RFA12_BYPASS___S 5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_2__RFA12_EN_LIM___M 0x00000010 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_2__RFA12_EN_LIM___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_2__RFA12_LIMIT___M 0x0000000F +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_2__RFA12_LIMIT___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA12_STATE_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_3 (0x005D1254) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT2_OS___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT2_US___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT1_OS___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT1_US___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT2_OS___M 0x00000008 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT2_OS___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT2_US___M 0x00000004 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT2_US___S 2 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT1_OS___M 0x00000002 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT1_OS___S 1 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT1_US___M 0x00000001 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_3__RO_RFA12_FAULT1_US___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_3___M 0x0000000F +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_STATE_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_0 (0x005D1258) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_0__RO_RFA12_FAULT1_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_0__RO_RFA12_FAULT1_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_0__RO_RFA12_FAULT1_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_1 (0x005D125C) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_1__RO_RFA12_FAULT1_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_1__RO_RFA12_FAULT1_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_1__RO_RFA12_FAULT1_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_2 (0x005D1260) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_2__RO_RFA12_FAULT1_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_2__RO_RFA12_FAULT1_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_2__RO_RFA12_FAULT1_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_3 (0x005D1264) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_3__RO_RFA12_FAULT1_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_3__RO_RFA12_FAULT1_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_3__RO_RFA12_FAULT1_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT1_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_0 (0x005D1268) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_0__RO_RFA12_FAULT2_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_0__RO_RFA12_FAULT2_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_0__RO_RFA12_FAULT2_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_1 (0x005D126C) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_1__RO_RFA12_FAULT2_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_1__RO_RFA12_FAULT2_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_1__RO_RFA12_FAULT2_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_2 (0x005D1270) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_2__RO_RFA12_FAULT2_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_2__RO_RFA12_FAULT2_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_2__RO_RFA12_FAULT2_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_3 (0x005D1274) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_3__RO_RFA12_FAULT2_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_3__RO_RFA12_FAULT2_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_3__RO_RFA12_FAULT2_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA12_FAULT2_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2 (0x005D1278) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2___POR 0x00000065 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_LP_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_SS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_VS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_STEPPER_FORCE_TARGET___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_STEPPER_STEP___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_STEPPER_DELAY___POR 0x5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_LP_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_LP_EN___S 7 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_SS_EN___M 0x00000040 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_SS_EN___S 6 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_VS_EN___M 0x00000020 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_VS_EN___S 5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_STEPPER_FORCE_TARGET___M 0x00000010 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_STEPPER_FORCE_TARGET___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_STEPPER_STEP___M 0x00000008 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_STEPPER_STEP___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_STEPPER_DELAY___M 0x00000007 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2__PCIE09_STEPPER_DELAY___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_3 (0x005D127C) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_3__PCIE09_EN_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_3__PCIE09_VSET_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_3__PCIE09_TRIM___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_3__PCIE09_EN_OVR___M 0x000000E0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_3__PCIE09_EN_OVR___S 5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_3__PCIE09_VSET_OVR___M 0x00000018 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_3__PCIE09_VSET_OVR___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_3__PCIE09_TRIM___M 0x00000007 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_3__PCIE09_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_PROGRAMMING_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0 (0x005D1280) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0___POR 0x00000004 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0__PCIE09_VREG_TYPE___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0__PCIE09_MODE_FSM_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0__PCIE09_MODE_FSM_OVR_VALUE___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0__PCIE09_FAULT_THRESHOLD___POR 0x2 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0__PCIE09_ENABLE_FAULT_MONITORING___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0__PCIE09_VREG_TYPE___M 0x00000080 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0__PCIE09_VREG_TYPE___S 7 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0__PCIE09_MODE_FSM_OVR___M 0x00000040 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0__PCIE09_MODE_FSM_OVR___S 6 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0__PCIE09_MODE_FSM_OVR_VALUE___M 0x00000038 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0__PCIE09_MODE_FSM_OVR_VALUE___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0__PCIE09_FAULT_THRESHOLD___M 0x00000006 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0__PCIE09_FAULT_THRESHOLD___S 1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0__PCIE09_ENABLE_FAULT_MONITORING___M 0x00000001 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0__PCIE09_ENABLE_FAULT_MONITORING___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_1 (0x005D1284) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_1__RO_PCIE09_SPARE5___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_1__RO_PCIE09_OK_REG___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_1__RO_PCIE09_MODE_FSM_STATE___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_1__RO_PCIE09_SPARE5___M 0x000000F0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_1__RO_PCIE09_SPARE5___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_1__RO_PCIE09_OK_REG___M 0x00000008 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_1__RO_PCIE09_OK_REG___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_1__RO_PCIE09_MODE_FSM_STATE___M 0x00000007 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_1__RO_PCIE09_MODE_FSM_STATE___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_2 (0x005D1288) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_2___POR 0x00000010 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_2__PCIE09_SPARE6___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_2__PCIE09_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_2__PCIE09_EN_LIM___POR 0x1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_2__PCIE09_LIMIT___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_2__PCIE09_SPARE6___M 0x000000C0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_2__PCIE09_SPARE6___S 6 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_2__PCIE09_BYPASS___M 0x00000020 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_2__PCIE09_BYPASS___S 5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_2__PCIE09_EN_LIM___M 0x00000010 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_2__PCIE09_EN_LIM___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_2__PCIE09_LIMIT___M 0x0000000F +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_2__PCIE09_LIMIT___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE09_STATE_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_3 (0x005D128C) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT2_OS___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT2_US___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT1_OS___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT1_US___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT2_OS___M 0x00000008 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT2_OS___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT2_US___M 0x00000004 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT2_US___S 2 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT1_OS___M 0x00000002 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT1_OS___S 1 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT1_US___M 0x00000001 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_3__RO_PCIE09_FAULT1_US___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_3___M 0x0000000F +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_STATE_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_0 (0x005D1290) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_0__RO_PCIE09_FAULT1_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_0__RO_PCIE09_FAULT1_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_0__RO_PCIE09_FAULT1_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_1 (0x005D1294) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_1__RO_PCIE09_FAULT1_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_1__RO_PCIE09_FAULT1_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_1__RO_PCIE09_FAULT1_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_2 (0x005D1298) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_2__RO_PCIE09_FAULT1_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_2__RO_PCIE09_FAULT1_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_2__RO_PCIE09_FAULT1_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_3 (0x005D129C) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_3__RO_PCIE09_FAULT1_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_3__RO_PCIE09_FAULT1_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_3__RO_PCIE09_FAULT1_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT1_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_0 (0x005D12A0) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_0__RO_PCIE09_FAULT2_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_0__RO_PCIE09_FAULT2_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_0__RO_PCIE09_FAULT2_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_1 (0x005D12A4) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_1__RO_PCIE09_FAULT2_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_1__RO_PCIE09_FAULT2_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_1__RO_PCIE09_FAULT2_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_2 (0x005D12A8) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_2__RO_PCIE09_FAULT2_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_2__RO_PCIE09_FAULT2_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_2__RO_PCIE09_FAULT2_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_3 (0x005D12AC) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_3__RO_PCIE09_FAULT2_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_3__RO_PCIE09_FAULT2_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_3__RO_PCIE09_FAULT2_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE09_FAULT2_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2 (0x005D12B0) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2___POR 0x00000065 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_LP_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_SS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_VS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_STEPPER_FORCE_TARGET___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_STEPPER_STEP___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_STEPPER_DELAY___POR 0x5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_LP_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_LP_EN___S 7 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_SS_EN___M 0x00000040 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_SS_EN___S 6 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_VS_EN___M 0x00000020 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_VS_EN___S 5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_STEPPER_FORCE_TARGET___M 0x00000010 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_STEPPER_FORCE_TARGET___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_STEPPER_STEP___M 0x00000008 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_STEPPER_STEP___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_STEPPER_DELAY___M 0x00000007 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2__RFA17_STEPPER_DELAY___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_3 (0x005D12B4) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_3__RFA17_EN_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_3__RFA17_VSET_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_3__RFA17_TRIM___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_3__RFA17_EN_OVR___M 0x000000E0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_3__RFA17_EN_OVR___S 5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_3__RFA17_VSET_OVR___M 0x00000018 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_3__RFA17_VSET_OVR___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_3__RFA17_TRIM___M 0x00000007 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_3__RFA17_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_PROGRAMMING_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0 (0x005D12B8) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0___POR 0x00000084 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0__RFA17_VREG_TYPE___POR 0x1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0__RFA17_MODE_FSM_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0__RFA17_MODE_FSM_OVR_VALUE___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0__RFA17_FAULT_THRESHOLD___POR 0x2 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0__RFA17_ENABLE_FAULT_MONITORING___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0__RFA17_VREG_TYPE___M 0x00000080 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0__RFA17_VREG_TYPE___S 7 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0__RFA17_MODE_FSM_OVR___M 0x00000040 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0__RFA17_MODE_FSM_OVR___S 6 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0__RFA17_MODE_FSM_OVR_VALUE___M 0x00000038 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0__RFA17_MODE_FSM_OVR_VALUE___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0__RFA17_FAULT_THRESHOLD___M 0x00000006 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0__RFA17_FAULT_THRESHOLD___S 1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0__RFA17_ENABLE_FAULT_MONITORING___M 0x00000001 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0__RFA17_ENABLE_FAULT_MONITORING___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_1 (0x005D12BC) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_1__RO_RFA17_SPARE5___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_1__RO_RFA17_OK_REG___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_1__RO_RFA17_MODE_FSM_STATE___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_1__RO_RFA17_SPARE5___M 0x000000F0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_1__RO_RFA17_SPARE5___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_1__RO_RFA17_OK_REG___M 0x00000008 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_1__RO_RFA17_OK_REG___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_1__RO_RFA17_MODE_FSM_STATE___M 0x00000007 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_1__RO_RFA17_MODE_FSM_STATE___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_2 (0x005D12C0) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_2___POR 0x00000010 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_2__RFA17_SPARE6___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_2__RFA17_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_2__RFA17_EN_LIM___POR 0x1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_2__RFA17_LIMIT___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_2__RFA17_SPARE6___M 0x000000C0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_2__RFA17_SPARE6___S 6 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_2__RFA17_BYPASS___M 0x00000020 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_2__RFA17_BYPASS___S 5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_2__RFA17_EN_LIM___M 0x00000010 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_2__RFA17_EN_LIM___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_2__RFA17_LIMIT___M 0x0000000F +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_2__RFA17_LIMIT___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_RFA17_STATE_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_3 (0x005D12C4) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT2_OS___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT2_US___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT1_OS___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT1_US___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT2_OS___M 0x00000008 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT2_OS___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT2_US___M 0x00000004 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT2_US___S 2 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT1_OS___M 0x00000002 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT1_OS___S 1 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT1_US___M 0x00000001 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_3__RO_RFA17_FAULT1_US___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_3___M 0x0000000F +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_STATE_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_0 (0x005D12C8) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_0__RO_RFA17_FAULT1_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_0__RO_RFA17_FAULT1_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_0__RO_RFA17_FAULT1_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_1 (0x005D12CC) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_1__RO_RFA17_FAULT1_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_1__RO_RFA17_FAULT1_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_1__RO_RFA17_FAULT1_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_2 (0x005D12D0) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_2__RO_RFA17_FAULT1_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_2__RO_RFA17_FAULT1_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_2__RO_RFA17_FAULT1_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_3 (0x005D12D4) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_3__RO_RFA17_FAULT1_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_3__RO_RFA17_FAULT1_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_3__RO_RFA17_FAULT1_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT1_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_0 (0x005D12D8) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_0__RO_RFA17_FAULT2_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_0__RO_RFA17_FAULT2_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_0__RO_RFA17_FAULT2_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_1 (0x005D12DC) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_1__RO_RFA17_FAULT2_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_1__RO_RFA17_FAULT2_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_1__RO_RFA17_FAULT2_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_2 (0x005D12E0) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_2__RO_RFA17_FAULT2_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_2__RO_RFA17_FAULT2_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_2__RO_RFA17_FAULT2_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_3 (0x005D12E4) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_3__RO_RFA17_FAULT2_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_3__RO_RFA17_FAULT2_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_3__RO_RFA17_FAULT2_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_RFA17_FAULT2_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2 (0x005D12E8) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2___POR 0x00000065 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_LP_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_SS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_VS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_STEPPER_FORCE_TARGET___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_STEPPER_STEP___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_STEPPER_DELAY___POR 0x5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_LP_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_LP_EN___S 7 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_SS_EN___M 0x00000040 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_SS_EN___S 6 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_VS_EN___M 0x00000020 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_VS_EN___S 5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_STEPPER_FORCE_TARGET___M 0x00000010 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_STEPPER_FORCE_TARGET___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_STEPPER_STEP___M 0x00000008 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_STEPPER_STEP___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_STEPPER_DELAY___M 0x00000007 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2__PCIE18_STEPPER_DELAY___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_3 (0x005D12EC) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_3__PCIE18_EN_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_3__PCIE18_VSET_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_3__PCIE18_TRIM___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_3__PCIE18_EN_OVR___M 0x000000E0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_3__PCIE18_EN_OVR___S 5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_3__PCIE18_VSET_OVR___M 0x00000018 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_3__PCIE18_VSET_OVR___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_3__PCIE18_TRIM___M 0x00000007 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_3__PCIE18_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_PROGRAMMING_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0 (0x005D12F0) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0___POR 0x00000084 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0__PCIE18_VREG_TYPE___POR 0x1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0__PCIE18_MODE_FSM_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0__PCIE18_MODE_FSM_OVR_VALUE___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0__PCIE18_FAULT_THRESHOLD___POR 0x2 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0__PCIE18_ENABLE_FAULT_MONITORING___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0__PCIE18_VREG_TYPE___M 0x00000080 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0__PCIE18_VREG_TYPE___S 7 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0__PCIE18_MODE_FSM_OVR___M 0x00000040 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0__PCIE18_MODE_FSM_OVR___S 6 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0__PCIE18_MODE_FSM_OVR_VALUE___M 0x00000038 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0__PCIE18_MODE_FSM_OVR_VALUE___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0__PCIE18_FAULT_THRESHOLD___M 0x00000006 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0__PCIE18_FAULT_THRESHOLD___S 1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0__PCIE18_ENABLE_FAULT_MONITORING___M 0x00000001 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0__PCIE18_ENABLE_FAULT_MONITORING___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_1 (0x005D12F4) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_1__RO_PCIE18_SPARE5___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_1__RO_PCIE18_OK_REG___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_1__RO_PCIE18_MODE_FSM_STATE___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_1__RO_PCIE18_SPARE5___M 0x000000F0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_1__RO_PCIE18_SPARE5___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_1__RO_PCIE18_OK_REG___M 0x00000008 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_1__RO_PCIE18_OK_REG___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_1__RO_PCIE18_MODE_FSM_STATE___M 0x00000007 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_1__RO_PCIE18_MODE_FSM_STATE___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_2 (0x005D12F8) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_2___POR 0x00000010 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_2__PCIE18_SPARE6___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_2__PCIE18_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_2__PCIE18_EN_LIM___POR 0x1 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_2__PCIE18_LIMIT___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_2__PCIE18_SPARE6___M 0x000000C0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_2__PCIE18_SPARE6___S 6 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_2__PCIE18_BYPASS___M 0x00000020 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_2__PCIE18_BYPASS___S 5 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_2__PCIE18_EN_LIM___M 0x00000010 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_2__PCIE18_EN_LIM___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_2__PCIE18_LIMIT___M 0x0000000F +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_2__PCIE18_LIMIT___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_PCIE18_STATE_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_3 (0x005D12FC) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT2_OS___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT2_US___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT1_OS___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT1_US___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT2_OS___M 0x00000008 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT2_OS___S 3 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT2_US___M 0x00000004 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT2_US___S 2 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT1_OS___M 0x00000002 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT1_OS___S 1 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT1_US___M 0x00000001 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_3__RO_PCIE18_FAULT1_US___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_3___M 0x0000000F +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_STATE_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_0 (0x005D1300) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_0__RO_PCIE18_FAULT1_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_0__RO_PCIE18_FAULT1_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_0__RO_PCIE18_FAULT1_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_1 (0x005D1304) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_1__RO_PCIE18_FAULT1_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_1__RO_PCIE18_FAULT1_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_1__RO_PCIE18_FAULT1_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_2 (0x005D1308) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_2__RO_PCIE18_FAULT1_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_2__RO_PCIE18_FAULT1_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_2__RO_PCIE18_FAULT1_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_3 (0x005D130C) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_3__RO_PCIE18_FAULT1_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_3__RO_PCIE18_FAULT1_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_3__RO_PCIE18_FAULT1_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT1_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_0 (0x005D1310) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_0__RO_PCIE18_FAULT2_TIMESTAMP_L___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_0__RO_PCIE18_FAULT2_TIMESTAMP_L___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_0__RO_PCIE18_FAULT2_TIMESTAMP_L___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_0___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_1 (0x005D1314) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_1__RO_PCIE18_FAULT2_TIMESTAMP_ML___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_1__RO_PCIE18_FAULT2_TIMESTAMP_ML___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_1__RO_PCIE18_FAULT2_TIMESTAMP_ML___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_2 (0x005D1318) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_2__RO_PCIE18_FAULT2_TIMESTAMP_MH___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_2__RO_PCIE18_FAULT2_TIMESTAMP_MH___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_2__RO_PCIE18_FAULT2_TIMESTAMP_MH___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_3 (0x005D131C) +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_3__RO_PCIE18_FAULT2_TIMESTAMP_H___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_3__RO_PCIE18_FAULT2_TIMESTAMP_H___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_3__RO_PCIE18_FAULT2_TIMESTAMP_H___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_RO_PMU_PCIE18_FAULT2_TIMESTAMP_3___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_1 (0x005D1320) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_1__WL_EN_08AO_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_1__BT_EN_08AO_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_1__CLK_REQ_IN_08AO_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_1__LAA_AS_EN_08AO_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_1__WL_EN_08AO_OVR___M 0x000000C0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_1__WL_EN_08AO_OVR___S 6 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_1__BT_EN_08AO_OVR___M 0x00000030 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_1__BT_EN_08AO_OVR___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_1__CLK_REQ_IN_08AO_OVR___M 0x0000000C +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_1__CLK_REQ_IN_08AO_OVR___S 2 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_1__LAA_AS_EN_08AO_OVR___M 0x00000003 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_1__LAA_AS_EN_08AO_OVR___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_2 (0x005D1324) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_2__QOW_08AO_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_2__OK_VDD08AO_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_2__VDD08AO_VSEL_OTP_VLD_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_2__VDD08AO_HFRC_OTP_VLD_OVR___POR 0x0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_2__QOW_08AO_OVR___M 0x000000C0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_2__QOW_08AO_OVR___S 6 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_2__OK_VDD08AO_OVR___M 0x00000030 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_2__OK_VDD08AO_OVR___S 4 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_2__VDD08AO_VSEL_OTP_VLD_OVR___M 0x0000000C +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_2__VDD08AO_VSEL_OTP_VLD_OVR___S 2 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_2__VDD08AO_HFRC_OTP_VLD_OVR___M 0x00000003 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_2__VDD08AO_HFRC_OTP_VLD_OVR___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_MISC_OVR_2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BG1 (0x005D1328) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BG1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BG1___POR 0x00000005 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BG1__D_BG_TCOMP_TRIM___POR 0x05 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BG1__D_BG_TCOMP_TRIM___M 0x0000003F +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BG1__D_BG_TCOMP_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BG1___M 0x0000003F +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BG1___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BG2 (0x005D132C) +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BG2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BG2___POR 0x0000002C +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BG2__D_BG_IR_TRIM___POR 0x2C +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BG2__D_BG_IR_TRIM___M 0x0000003F +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BG2__D_BG_IR_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BG2___M 0x0000003F +#define PHYA_IRON2G_RFA_WSIM_PMU_PMU_BG2___S 0 + +#define PHYA_IRON2G_RFA_WSIM_PMU_SPARE (0x005D1334) +#define PHYA_IRON2G_RFA_WSIM_PMU_SPARE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSIM_PMU_SPARE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSIM_PMU_SPARE__D_PMU_SPARE___POR 0x00 +#define PHYA_IRON2G_RFA_WSIM_PMU_SPARE__D_PMU_SPARE___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_SPARE__D_PMU_SPARE___S 0 +#define PHYA_IRON2G_RFA_WSIM_PMU_SPARE___M 0x000000FF +#define PHYA_IRON2G_RFA_WSIM_PMU_SPARE___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_ANTI_ROLLBACK_M0 (0x005C9B04) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_ANTI_ROLLBACK_M0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_ANTI_ROLLBACK_M0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_ANTI_ROLLBACK_M0__ANTI_ROLLBACK_M0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_ANTI_ROLLBACK_M0__ANTI_ROLLBACK_M0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_ANTI_ROLLBACK_M0__ANTI_ROLLBACK_M0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_ANTI_ROLLBACK_M0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_ANTI_ROLLBACK_M0___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD0 (0x005C9B28) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD0__OEM_PK_HASH_M0_WORD0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD0__OEM_PK_HASH_M0_WORD0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD0__OEM_PK_HASH_M0_WORD0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD0___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD1 (0x005C9B2C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD1__OEM_PK_HASH_M0_WORD1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD1__OEM_PK_HASH_M0_WORD1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD1__OEM_PK_HASH_M0_WORD1___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD1___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD2 (0x005C9B30) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD2__OEM_PK_HASH_M0_WORD2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD2__OEM_PK_HASH_M0_WORD2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD2__OEM_PK_HASH_M0_WORD2___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD2___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD3 (0x005C9B34) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD3__OEM_PK_HASH_M0_WORD3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD3__OEM_PK_HASH_M0_WORD3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD3__OEM_PK_HASH_M0_WORD3___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD3___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD4 (0x005C9B38) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD4___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD4__OEM_PK_HASH_M0_WORD4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD4__OEM_PK_HASH_M0_WORD4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD4__OEM_PK_HASH_M0_WORD4___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD4___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD5 (0x005C9B3C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD5___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD5__OEM_PK_HASH_M0_WORD5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD5__OEM_PK_HASH_M0_WORD5___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD5__OEM_PK_HASH_M0_WORD5___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD5___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD5___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD6 (0x005C9B40) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD6___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD6__OEM_PK_HASH_M0_WORD6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD6__OEM_PK_HASH_M0_WORD6___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD6__OEM_PK_HASH_M0_WORD6___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD6___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD6___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD7 (0x005C9B44) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD7___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD7__OEM_PK_HASH_M0_WORD7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD7__OEM_PK_HASH_M0_WORD7___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD7__OEM_PK_HASH_M0_WORD7___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD7___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_OEM_PK_HASH_M0_WORD7___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT (0x005C9B48) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT3_RESERVED___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT3_USE_SERIAL_NUM___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT3_AUTH_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT2_RESERVED___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT2_USE_SERIAL_NUM___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT2_AUTH_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT1_RESERVED___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT1_USE_SERIAL_NUM___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT1_AUTH_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT0_RESERVED___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT0_USE_SERIAL_NUM___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT0_AUTH_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT3_RESERVED___M 0x0000C000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT3_RESERVED___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT3_USE_SERIAL_NUM___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT3_USE_SERIAL_NUM___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT3_AUTH_EN___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT3_AUTH_EN___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT2_RESERVED___M 0x00000C00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT2_RESERVED___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT2_USE_SERIAL_NUM___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT2_USE_SERIAL_NUM___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT2_AUTH_EN___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT2_AUTH_EN___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT1_RESERVED___M 0x000000C0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT1_RESERVED___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT1_USE_SERIAL_NUM___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT1_USE_SERIAL_NUM___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT1_AUTH_EN___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT1_AUTH_EN___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT0_RESERVED___M 0x0000000C +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT0_RESERVED___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT0_USE_SERIAL_NUM___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT0_USE_SERIAL_NUM___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT0_AUTH_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT__SECURE_BOOT0_AUTH_EN___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_SECURE_BOOT___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_FEATURE_BITS (0x005C9B4C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_FEATURE_BITS___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_FEATURE_BITS___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_FEATURE_BITS__BT_FEATURE_BITS___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_FEATURE_BITS__BT_FEATURE_BITS___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_FEATURE_BITS__BT_FEATURE_BITS___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_FEATURE_BITS___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_FEATURE_BITS___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0 (0x005C9B50) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0__SW_FUSE_PROG_DISABLE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0__ENUM_TIMEOUT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0__RAM_DUMP_USE_SN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0__ANTI_ROLLBACK_FEATURE_EN_M0___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0__HASH_INTEGRITY_CHECK_DISABLE_M0___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0__SW_FUSE_PROG_DISABLE___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0__SW_FUSE_PROG_DISABLE___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0__ENUM_TIMEOUT___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0__ENUM_TIMEOUT___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0__RAM_DUMP_USE_SN___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0__RAM_DUMP_USE_SN___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0__ANTI_ROLLBACK_FEATURE_EN_M0___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0__ANTI_ROLLBACK_FEATURE_EN_M0___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0__HASH_INTEGRITY_CHECK_DISABLE_M0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0__HASH_INTEGRITY_CHECK_DISABLE_M0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0___M 0x000000E9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG0___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG1 (0x005C9B54) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG1__MODEL_ID___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG1__OEM_ID___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG1__MODEL_ID___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG1__MODEL_ID___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG1__OEM_ID___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG1__OEM_ID___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_CONFIG1___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_DEBUG (0x005C9B58) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_DEBUG___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_DEBUG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_DEBUG__RAM_DUMP_DISABLE___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_DEBUG__DISABLE_QC_RMA___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_DEBUG__OEM_DEBUG_DISABLE_VECTOR___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_DEBUG__RAM_DUMP_DISABLE___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_DEBUG__RAM_DUMP_DISABLE___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_DEBUG__DISABLE_QC_RMA___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_DEBUG__DISABLE_QC_RMA___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_DEBUG__OEM_DEBUG_DISABLE_VECTOR___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_DEBUG__OEM_DEBUG_DISABLE_VECTOR___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_DEBUG___M 0x000003FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BT_OEM_DEBUG___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_OEM_AUTOMOTIVE_FEATURES (0x005C9B5C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_OEM_AUTOMOTIVE_FEATURES___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_OEM_AUTOMOTIVE_FEATURES___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_OEM_AUTOMOTIVE_FEATURES__BTFM_OEM_AUTOMOTIVE_FEATURES___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_OEM_AUTOMOTIVE_FEATURES__BTFM_OEM_AUTOMOTIVE_FEATURES___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_OEM_AUTOMOTIVE_FEATURES__BTFM_OEM_AUTOMOTIVE_FEATURES___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_OEM_AUTOMOTIVE_FEATURES___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_BTFM_OEM_AUTOMOTIVE_FEATURES___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CLK_CTL (0x005C9B6C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CLK_CTL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CLK_CTL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CLK_CTL__QFPROM_CLK_CTL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CLK_CTL__QFPROM_CLK_CTL___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CLK_CTL__QFPROM_CLK_CTL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CLK_CTL___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CLK_CTL___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_TEST_BUS_SEL (0x005C9B70) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_TEST_BUS_SEL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_TEST_BUS_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_TEST_BUS_SEL__TEST_BUS_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_TEST_BUS_SEL__TEST_BUS_SELECT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_TEST_BUS_SEL__TEST_BUS_EN___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_TEST_BUS_SEL__TEST_BUS_EN___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_TEST_BUS_SEL__TEST_BUS_SELECT___M 0x00000007 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_TEST_BUS_SEL__TEST_BUS_SELECT___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_TEST_BUS_SEL___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_TEST_BUS_SEL___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT (0x005C9B74) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION16_WRITE_DISABLE_STICKY_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION15_WRITE_DISABLE_STICKY_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION14_WRITE_DISABLE_STICKY_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION13_WRITE_DISABLE_STICKY_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION12_WRITE_DISABLE_STICKY_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION11_WRITE_DISABLE_STICKY_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION10_WRITE_DISABLE_STICKY_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION9_WRITE_DISABLE_STICKY_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION8_WRITE_DISABLE_STICKY_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION7_WRITE_DISABLE_STICKY_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION6_WRITE_DISABLE_STICKY_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION5_WRITE_DISABLE_STICKY_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION4_WRITE_DISABLE_STICKY_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION3_WRITE_DISABLE_STICKY_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION2_WRITE_DISABLE_STICKY_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION1_WRITE_DISABLE_STICKY_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION0_WRITE_DISABLE_STICKY_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION16_WRITE_DISABLE_STICKY_BIT___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION16_WRITE_DISABLE_STICKY_BIT___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION15_WRITE_DISABLE_STICKY_BIT___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION15_WRITE_DISABLE_STICKY_BIT___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION14_WRITE_DISABLE_STICKY_BIT___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION14_WRITE_DISABLE_STICKY_BIT___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION13_WRITE_DISABLE_STICKY_BIT___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION13_WRITE_DISABLE_STICKY_BIT___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION12_WRITE_DISABLE_STICKY_BIT___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION12_WRITE_DISABLE_STICKY_BIT___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION11_WRITE_DISABLE_STICKY_BIT___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION11_WRITE_DISABLE_STICKY_BIT___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION10_WRITE_DISABLE_STICKY_BIT___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION10_WRITE_DISABLE_STICKY_BIT___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION9_WRITE_DISABLE_STICKY_BIT___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION9_WRITE_DISABLE_STICKY_BIT___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION8_WRITE_DISABLE_STICKY_BIT___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION8_WRITE_DISABLE_STICKY_BIT___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION7_WRITE_DISABLE_STICKY_BIT___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION7_WRITE_DISABLE_STICKY_BIT___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION6_WRITE_DISABLE_STICKY_BIT___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION6_WRITE_DISABLE_STICKY_BIT___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION5_WRITE_DISABLE_STICKY_BIT___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION5_WRITE_DISABLE_STICKY_BIT___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION4_WRITE_DISABLE_STICKY_BIT___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION4_WRITE_DISABLE_STICKY_BIT___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION3_WRITE_DISABLE_STICKY_BIT___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION3_WRITE_DISABLE_STICKY_BIT___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION2_WRITE_DISABLE_STICKY_BIT___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION2_WRITE_DISABLE_STICKY_BIT___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION1_WRITE_DISABLE_STICKY_BIT___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION1_WRITE_DISABLE_STICKY_BIT___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION0_WRITE_DISABLE_STICKY_BIT___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT__REGION0_WRITE_DISABLE_STICKY_BIT___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT___M 0x0001FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_WRITE_DISABLE_STICKY_BIT___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_TIMER (0x005C9D00) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_TIMER___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_TIMER___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_TIMER__QFPROM_BLOW_TIMER___POR 0x000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_TIMER__QFPROM_BLOW_TIMER___M 0x00000FFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_TIMER__QFPROM_BLOW_TIMER___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_TIMER___M 0x00000FFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_TIMER___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_TEST_CTRL (0x005C9D04) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_TEST_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_TEST_CTRL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_TEST_CTRL__QFPROM_SEL_ROM_ROWS___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_TEST_CTRL__QFPROM_SEL_EXTRA_ROWS___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_TEST_CTRL__QFPROM_SEL_TSTBL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_TEST_CTRL__QFPROM_EN_FUSE_RES_MEAS___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_TEST_CTRL__QFPROM_SEL_ROM_ROWS___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_TEST_CTRL__QFPROM_SEL_ROM_ROWS___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_TEST_CTRL__QFPROM_SEL_EXTRA_ROWS___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_TEST_CTRL__QFPROM_SEL_EXTRA_ROWS___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_TEST_CTRL__QFPROM_SEL_TSTBL___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_TEST_CTRL__QFPROM_SEL_TSTBL___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_TEST_CTRL__QFPROM_EN_FUSE_RES_MEAS___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_TEST_CTRL__QFPROM_EN_FUSE_RES_MEAS___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_TEST_CTRL___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_TEST_CTRL___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ACCEL (0x005C9D08) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ACCEL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ACCEL___POR 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ACCEL__QFPROM_GATELAST___POR 0x1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ACCEL__QFPROM_TRIP_PT_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ACCEL__QFPROM_ACCEL_VALUE___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ACCEL__QFPROM_GATELAST___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ACCEL__QFPROM_GATELAST___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ACCEL__QFPROM_TRIP_PT_SEL___M 0x00000700 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ACCEL__QFPROM_TRIP_PT_SEL___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ACCEL__QFPROM_ACCEL_VALUE___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ACCEL__QFPROM_ACCEL_VALUE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ACCEL___M 0x00000FFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ACCEL___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_STATUS (0x005C9D0C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_STATUS___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_STATUS___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_STATUS__QFPROM_WR_ERR_STATUS___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_STATUS__QFPROM_BUSY___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_STATUS__QFPROM_WR_ERR_STATUS___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_STATUS__QFPROM_WR_ERR_STATUS___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_STATUS__QFPROM_BUSY___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_STATUS__QFPROM_BUSY___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_STATUS___M 0x00000003 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BLOW_STATUS___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BIST_CTRL (0x005C9D10) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BIST_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BIST_CTRL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BIST_CTRL__QFPROM_BIST_BUSY___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BIST_CTRL__QFPROM_BIST_BUSY___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BIST_CTRL__QFPROM_BIST_BUSY___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BIST_CTRL___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BIST_CTRL___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BIST_ERROR (0x005C9D14) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BIST_ERROR___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BIST_ERROR___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BIST_ERROR__QFPROM_BIST_ERR_STATUS___POR 0x00000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BIST_ERROR__QFPROM_BIST_ERR_STATUS___M 0x0001FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BIST_ERROR__QFPROM_BIST_ERR_STATUS___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BIST_ERROR___M 0x0001FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_BIST_ERROR___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_RESET_JDR_STATUS (0x005C9D18) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_RESET_JDR_STATUS___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_RESET_JDR_STATUS___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_RESET_JDR_STATUS__JDR_SYS_OUT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_RESET_JDR_STATUS__JDR_SYS_OUT___M 0x00000003 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_RESET_JDR_STATUS__JDR_SYS_OUT___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_RESET_JDR_STATUS___M 0x00000003 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_RESET_JDR_STATUS___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ROM_ERROR (0x005C9D1C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ROM_ERROR___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ROM_ERROR___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ROM_ERROR__QFPROM_ROM_ERROR___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ROM_ERROR__QFPROM_ROM_ERROR___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ROM_ERROR__QFPROM_ROM_ERROR___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ROM_ERROR___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ROM_ERROR___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ROM_IRQ (0x005C9D20) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ROM_IRQ___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ROM_IRQ___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ROM_IRQ__QFPROM_IRQ___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ROM_IRQ__QFPROM_IRQ___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ROM_IRQ__QFPROM_IRQ___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ROM_IRQ___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_ROM_IRQ___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR (0x005C9D24) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__FEC_SOURCE_CORRECT___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__CORRECT_MULT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__CORRECT_SEEN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__FEC_SOURCE_ERR___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__ERR_MULT___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__ERR_SEEN___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__FEC_SOURCE_CORRECT___M 0x00003E00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__FEC_SOURCE_CORRECT___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__CORRECT_MULT___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__CORRECT_MULT___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__CORRECT_SEEN___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__CORRECT_SEEN___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__FEC_SOURCE_ERR___M 0x0000007C +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__FEC_SOURCE_ERR___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__ERR_MULT___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__ERR_MULT___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__ERR_SEEN___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR__ERR_SEEN___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR___M 0x00003FFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_ESR___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_EAR (0x005C9D28) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_EAR___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_EAR___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_EAR__FEC_CORRECT_ADDRESS___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_EAR__FEC_ERR_ADDRESS___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_EAR__FEC_CORRECT_ADDRESS___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_EAR__FEC_CORRECT_ADDRESS___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_EAR__FEC_ERR_ADDRESS___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_EAR__FEC_ERR_ADDRESS___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_EAR___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_FEC_EAR___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_ERR_ADDR (0x005C9D2C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_ERR_ADDR___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_ERR_ADDR___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_ERR_ADDR__READ_SHADOW_ERR_SOURCE___POR 0x00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_ERR_ADDR__READ_SHADOW_ERR___POR 0x0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_ERR_ADDR__READ_SHADOW_ERR_ADDRESS___POR 0x0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_ERR_ADDR__READ_SHADOW_ERR_SOURCE___M 0x003E0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_ERR_ADDR__READ_SHADOW_ERR_SOURCE___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_ERR_ADDR__READ_SHADOW_ERR___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_ERR_ADDR__READ_SHADOW_ERR___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_ERR_ADDR__READ_SHADOW_ERR_ADDRESS___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_ERR_ADDR__READ_SHADOW_ERR_ADDRESS___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_ERR_ADDR___M 0x003FFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_ERR_ADDR___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q0_LOW_REG (0x005C9D30) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q0_LOW_REG___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q0_LOW_REG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q0_LOW_REG__QFPROM_ARB_Q0_FLAG_LOW___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q0_LOW_REG__QFPROM_ARB_Q0_FLAG_LOW___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q0_LOW_REG__QFPROM_ARB_Q0_FLAG_LOW___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q0_LOW_REG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q0_LOW_REG___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q0_HIGH_REG (0x005C9D34) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q0_HIGH_REG___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q0_HIGH_REG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q0_HIGH_REG__QFPROM_ARB_Q0_FLAG_HIGH___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q0_HIGH_REG__QFPROM_ARB_Q0_FLAG_HIGH___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q0_HIGH_REG__QFPROM_ARB_Q0_FLAG_HIGH___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q0_HIGH_REG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q0_HIGH_REG___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q1_LOW_REG (0x005C9D38) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q1_LOW_REG___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q1_LOW_REG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q1_LOW_REG__QFPROM_ARB_Q1_FLAG_LOW___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q1_LOW_REG__QFPROM_ARB_Q1_FLAG_LOW___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q1_LOW_REG__QFPROM_ARB_Q1_FLAG_LOW___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q1_LOW_REG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q1_LOW_REG___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q1_HIGH_REG (0x005C9D3C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q1_HIGH_REG___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q1_HIGH_REG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q1_HIGH_REG__QFPROM_ARB_Q1_FLAG_HIGH___POR 0x00000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q1_HIGH_REG__QFPROM_ARB_Q1_FLAG_HIGH___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q1_HIGH_REG__QFPROM_ARB_Q1_FLAG_HIGH___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q1_HIGH_REG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_SHADOW_Q1_HIGH_REG___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB (0x005C7000) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__RSVD_0_17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__SPARE_REGION_16_READ_DISABLE___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__SPARE_REGION_16_READ_DISABLE___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__SPARE_REGION_15_READ_DISABLE___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__SPARE_REGION_15_READ_DISABLE___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__OEM_WIP_READ_DISABLE___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__OEM_WIP_READ_DISABLE___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__OTP_PATCH_RSVD_READ_DISABLE___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__OTP_PATCH_RSVD_READ_DISABLE___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__OTP_PATCH_READ_DISABLE___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__OTP_PATCH_READ_DISABLE___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__WIP_READ_DISABLE___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__WIP_READ_DISABLE___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__BT_READ_DISABLE___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__BT_READ_DISABLE___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__PMU_RFA_SEQUENCE_READ_DISABLE___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__PMU_RFA_SEQUENCE_READ_DISABLE___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__MEMORY_CONFIG_READ_DISABLE___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__MEMORY_CONFIG_READ_DISABLE___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__FEC_CONTROL_READ_DISABLE___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__FEC_CONTROL_READ_DISABLE___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__OEM_PK_HASH_READ_DISABLE___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__OEM_PK_HASH_READ_DISABLE___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__QC_SECURE_READ_DISABLE___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__QC_SECURE_READ_DISABLE___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__ATE_READ_DISABLE___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__ATE_READ_DISABLE___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__TOP_READ_DISABLE___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__TOP_READ_DISABLE___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__OEM_SECURE_READ_DISABLE___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__OEM_SECURE_READ_DISABLE___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__ANTI_ROLLBACK_READ_DISABLE___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__ANTI_ROLLBACK_READ_DISABLE___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__PERMISSION_READ_DISABLE___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB__PERMISSION_READ_DISABLE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB (0x005C7004) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__QFPROM_CHECK_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__QFPROM_CHECK_EN___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_62___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_62___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_61___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_61___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_60___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_60___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_59___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_59___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_58___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_58___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_57___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_57___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_56___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_56___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__RSVD_0_49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__SPARE_REGION_16_WRITE_DISABLE___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__SPARE_REGION_16_WRITE_DISABLE___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__SPARE_REGION_15_WRITE_DISABLE___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__SPARE_REGION_15_WRITE_DISABLE___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__OEM_WIP_WRITE_DISABLE___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__OEM_WIP_WRITE_DISABLE___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__OTP_PATCH_RSVD_WRITE_DISABLE___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__OTP_PATCH_RSVD_WRITE_DISABLE___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__OTP_PATCH_WRITE_DISABLE___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__OTP_PATCH_WRITE_DISABLE___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__WIP_WRITE_DISABLE___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__WIP_WRITE_DISABLE___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__BT_WRITE_DISABLE___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__BT_WRITE_DISABLE___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__PMU_RFA_SEQUENCE_WRITE_DISABLE___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__PMU_RFA_SEQUENCE_WRITE_DISABLE___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__MEMORY_CONFIG_WRITE_DISABLE___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__MEMORY_CONFIG_WRITE_DISABLE___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__FEC_CONTROL_WRITE_DISABLE___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__FEC_CONTROL_WRITE_DISABLE___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__OEM_PK_HASH_WRITE_DISABLE___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__OEM_PK_HASH_WRITE_DISABLE___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__QC_SECURE_WRITE_DISABLE___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__QC_SECURE_WRITE_DISABLE___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__ATE_WRITE_DISABLE___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__ATE_WRITE_DISABLE___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__TOP_WRITE_DISABLE___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__TOP_WRITE_DISABLE___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__OEM_SECURE_WRITE_DISABLE___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__OEM_SECURE_WRITE_DISABLE___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__ANTI_ROLLBACK_WRITE_DISABLE___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__ANTI_ROLLBACK_WRITE_DISABLE___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__PERMISSION_WRITE_DISABLE___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB__PERMISSION_WRITE_DISABLE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_RD_WR_PERMISSION_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB (0x005C7008) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB__RSVD_R1_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_MSB (0x005C700C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_MSB__ANTI_ROLLBACK_M0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_MSB__ANTI_ROLLBACK_M0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ANTI_ROLLBACK_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB (0x005C7010) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__RSVD_R2_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT3_RSVD___M 0x0000C000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT3_RSVD___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT3_USE_SERIAL_NUM___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT3_USE_SERIAL_NUM___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT3_AUTH_EN___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT3_AUTH_EN___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT2_RSVD___M 0x00000C00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT2_RSVD___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT2_USE_SERIAL_NUM___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT2_USE_SERIAL_NUM___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT2_AUTH_EN___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT2_AUTH_EN___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT1_RSVD___M 0x000000C0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT1_RSVD___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT1_USE_SERIAL_NUM___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT1_USE_SERIAL_NUM___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT1_AUTH_EN___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT1_AUTH_EN___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT0_RSVD___M 0x0000000C +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT0_RSVD___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT0_USE_SERIAL_NUM___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT0_USE_SERIAL_NUM___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT0_AUTH_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB__SECURE_BOOT0_AUTH_EN___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_MSB (0x005C7014) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_MSB__BT_FEATURE_BITS___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_MSB__BT_FEATURE_BITS___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW0_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB (0x005C7018) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__SW_FUSE_PROG_DISABLE___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__SW_FUSE_PROG_DISABLE___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__ENUM_TIMEOUT___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__ENUM_TIMEOUT___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RAM_DUMP_USE_SN___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RAM_DUMP_USE_SN___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__ANTI_ROLLBACK_FEATURE_EN_M0___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__ANTI_ROLLBACK_FEATURE_EN_M0___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__RSVD_R3_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__HASH_INTEGRITY_CHECK_DISABLE_M0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB__HASH_INTEGRITY_CHECK_DISABLE_M0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_MSB (0x005C701C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_MSB__MODEL_ID___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_MSB__MODEL_ID___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_MSB__OEM_ID___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_MSB__OEM_ID___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW1_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB (0x005C7020) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RSVD_R4_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RAM_DUMP_DISABLE___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__RAM_DUMP_DISABLE___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__DISABLE_QC_RMA___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__DISABLE_QC_RMA___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__OEM_DEBUG_DISABLE_VECTOR___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB__OEM_DEBUG_DISABLE_VECTOR___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_MSB (0x005C7024) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_MSB__OEM_AUTOMOTIVE_FEATURES___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_MSB__OEM_AUTOMOTIVE_FEATURES___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_SECURE_ROW2_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW0_LSB (0x005C7028) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW0_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW0_LSB__SERIAL_NUM_31_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW0_LSB__SERIAL_NUM_31_0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW0_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW0_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW0_MSB (0x005C702C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW0_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW0_MSB__JTAG_ID_15_0___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW0_MSB__JTAG_ID_15_0___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW0_MSB__SERIAL_NUM_47_32___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW0_MSB__SERIAL_NUM_47_32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW0_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW0_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB (0x005C7030) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__RSVD_R6_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__SPARE_R6_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__SPARE_R6_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__EXTERNAL_32K_SELECT___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__EXTERNAL_32K_SELECT___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__XO_CLK_SEL_VALID___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__XO_CLK_SEL_VALID___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__XO_CLK_SEL_RAW___M 0x00000060 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__XO_CLK_SEL_RAW___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__REFCLK_USE_TCXO___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__REFCLK_USE_TCXO___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__JTAG_ID_19_16___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB__JTAG_ID_19_16___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB (0x005C7034) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B63___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B63___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B62___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B62___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B61___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B61___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B60___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B60___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B59___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B59___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B58___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B58___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B57___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B57___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B56___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B56___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB__RSVD_R6_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW1_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB (0x005C7038) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__RFA_CLAMP_IO_SETTLE___M 0xE0000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__RFA_CLAMP_IO_SETTLE___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__TOP08RFA_LDO_SETTLE___M 0x1C000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__TOP08RFA_LDO_SETTLE___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__TOP12RFA_LDO_DLY___M 0x03800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__TOP12RFA_LDO_DLY___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__TOP17RFA_LDO_DLY___M 0x00700000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__TOP17RFA_LDO_DLY___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__VDD08AO_VLD___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__VDD08AO_VLD___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__VDD08AO_VALUE___M 0x0007F800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__VDD08AO_VALUE___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__VDD08AO_VSEL___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__VDD08AO_VSEL___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__SW_CTRL_DLY___M 0x00000380 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__SW_CTRL_DLY___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__TOP08RFACMN_LDO_DLY___M 0x00000070 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__TOP08RFACMN_LDO_DLY___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__VDD08RFACMN_VSEL___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__VDD08RFACMN_VSEL___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__VDD08RFA_VSEL___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__VDD08RFA_VSEL___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__VDD12RFA_VSEL___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__VDD12RFA_VSEL___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__VDD17RFA_VSEL___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB__VDD17RFA_VSEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB (0x005C703C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B63___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B63___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B62___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B62___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B61___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B61___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B60___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B60___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B59___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B59___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B58___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B58___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B57___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B57___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B56___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B56___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__RSVD_R7_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__VDD08AO_HRFC_VLD___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__VDD08AO_HRFC_VLD___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__VDD08AO_HRFC_TRIM___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB__VDD08AO_HRFC_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW2_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB (0x005C7040) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__RSVD_R8_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__TSENS_DEBUGBUS_DISABLE___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__TSENS_DEBUGBUS_DISABLE___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__OTP_PCIE_PHY_VDDA_SETTLE_DLY___M 0x0001E000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__OTP_PCIE_PHY_VDDA_SETTLE_DLY___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__OTP_PCIE_PHY_1P8_SETTLE_DLY___M 0x00001E00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__OTP_PCIE_PHY_1P8_SETTLE_DLY___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__OTP_WLCX_SETTLE_DLY___M 0x000001E0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__OTP_WLCX_SETTLE_DLY___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__OTP_WLMX_SETTLE_DLY___M 0x0000001E +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__OTP_WLMX_SETTLE_DLY___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__OTP_BLOWN_DONE___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB__OTP_BLOWN_DONE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB (0x005C7044) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__APB2JTAG_DISABLE___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__APB2JTAG_DISABLE___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B62___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B62___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B61___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B61___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B60___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B60___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B59___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B59___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B58___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B58___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B57___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B57___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B56___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B56___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB__RSVD_R8_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW3_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB (0x005C7048) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__RSVD_R9_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__WL_SEC_CTRL_AHB_FUSE_DISABLE___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__WL_SEC_CTRL_AHB_FUSE_DISABLE___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__BTC_DISABLE___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__BTC_DISABLE___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__ANT_DISABLE___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__ANT_DISABLE___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__BLE_DISABLE___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__BLE_DISABLE___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__WL_ONLY_WL_SLEEP___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__WL_ONLY_WL_SLEEP___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__LDOBTCX_RET_SETT_TIME___M 0x000000F0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__LDOBTCX_RET_SETT_TIME___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__LDOBTCX_SETT_TIME___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB__LDOBTCX_SETT_TIME___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB (0x005C704C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B63___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B63___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B62___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B62___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B61___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B61___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B60___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B60___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B59___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B59___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B58___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B58___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B57___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B57___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B56___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B56___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__RSVD_R9_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__BOOT_PATCH_SELECT___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__BOOT_PATCH_SELECT___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__BT_MODE___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__BT_MODE___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__BT_MANU_PGM___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB__BT_MANU_PGM___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_TOP_ROW4_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_LSB (0x005C7050) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_LSB__LOT_ID_LOW_7_0___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_LSB__LOT_ID_LOW_7_0___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_LSB__DIE_Y___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_LSB__DIE_Y___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_LSB__DIE_X___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_LSB__DIE_X___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_LSB__WAFERID___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_LSB__WAFERID___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_MSB (0x005C7054) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_MSB__LOT_ID_HIGH_7_0___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_MSB__LOT_ID_HIGH_7_0___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_MSB__LOT_ID_LOW_31_8___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_MSB__LOT_ID_LOW_31_8___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW0_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_LSB (0x005C7058) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_LSB__PROGRAM_REVISION_LOW_15_0___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_LSB__PROGRAM_REVISION_LOW_15_0___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_LSB__PRODUCT_QUALITY_BINNING___M 0x0000F000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_LSB__PRODUCT_QUALITY_BINNING___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_LSB__TEST_INSERTION_MASK___M 0x00000F00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_LSB__TEST_INSERTION_MASK___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_LSB__LOT_ID_HIGH_15_8___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_LSB__LOT_ID_HIGH_15_8___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_MSB (0x005C705C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_MSB__PROGRAM_REVISION_HIGH___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_MSB__PROGRAM_REVISION_HIGH___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_MSB__PROGRAM_REVISION_LOW_31_16___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_MSB__PROGRAM_REVISION_LOW_31_16___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW1_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW2_LSB (0x005C7060) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW2_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW2_LSB__CMOS_RVT_PM_CODE___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW2_LSB__CMOS_RVT_PM_CODE___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW2_LSB__NMOS_RVT_PM_CODE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW2_LSB__NMOS_RVT_PM_CODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW2_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW2_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW2_MSB (0x005C7064) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW2_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW2_MSB__CMOS_LVT_PM_CODE___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW2_MSB__CMOS_LVT_PM_CODE___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW2_MSB__NMOS_LVT_PM_CODE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW2_MSB__NMOS_LVT_PM_CODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW2_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW2_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW3_LSB (0x005C7068) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW3_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW3_LSB__CMOS_EG_PM_CODE___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW3_LSB__CMOS_EG_PM_CODE___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW3_LSB__NMOS_EG_PM_CODE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW3_LSB__NMOS_EG_PM_CODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW3_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW3_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW3_MSB (0x005C706C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW3_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW3_MSB__CMOS_EGU_PM_CODE___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW3_MSB__CMOS_EGU_PM_CODE___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW3_MSB__NMOS_EGU_PM_CODE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW3_MSB__NMOS_EGU_PM_CODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW3_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW3_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW4_LSB (0x005C7070) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW4_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW4_LSB__QCCMOM_RF_6FF_CODE___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW4_LSB__QCCMOM_RF_6FF_CODE___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW4_LSB__QCCMOM_RF_3FF_CODE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW4_LSB__QCCMOM_RF_3FF_CODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW4_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW4_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW4_MSB (0x005C7074) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW4_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW4_MSB__QMOM_RCX_RF_PW_CODE___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW4_MSB__QMOM_RCX_RF_PW_CODE___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW4_MSB__QCCMOM_RF_12FF_CODE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW4_MSB__QCCMOM_RF_12FF_CODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW4_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW4_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_LSB (0x005C7078) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_LSB__QMOM_RCX_RF_M1_CODE___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_LSB__QMOM_RCX_RF_M1_CODE___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_LSB__QMOM_RCX_RF_BEOL_CODE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_LSB__QMOM_RCX_RF_BEOL_CODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB (0x005C707C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B63___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B63___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B62___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B62___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B61___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B61___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B60___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B60___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B59___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B59___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B58___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B58___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B57___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B57___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B56___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B56___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RSVD_R15_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RERR___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB__RERR___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW5_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB (0x005C7080) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__RSVD_R16_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__ATE_TEMPSENSOR0_CODE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB__ATE_TEMPSENSOR0_CODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB (0x005C7084) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B63___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B63___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B62___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B62___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B61___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B61___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B60___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B60___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B59___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B59___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B58___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B58___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B57___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B57___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B56___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B56___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB__RSVD_R16_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW6_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB (0x005C7088) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__RSVD_R17_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__ATE_DVS_FLAG___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__ATE_DVS_FLAG___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__FOUNDRY_ID___M 0x003C0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__FOUNDRY_ID___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__HW_BOARD_ID___M 0x0003FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__HW_BOARD_ID___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__OTP_REVISION___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB__OTP_REVISION___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB (0x005C708C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B63___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B63___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B62___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B62___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B61___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B61___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B60___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B60___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B59___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B59___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B58___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B58___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B57___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B57___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B56___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B56___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB__RSVD_R17_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_ATE_ROW7_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB (0x005C7090) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__RSVD_R18_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__CONST_PWD_DISABLE___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__CONST_PWD_DISABLE___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__UNIQUE_QA_PWD___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__UNIQUE_QA_PWD___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__QC_RTL_KEY_VERSION___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__QC_RTL_KEY_VERSION___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__QC_DEBUG_DISABLE_VECTOR___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB__QC_DEBUG_DISABLE_VECTOR___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB (0x005C7094) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__PKG_ID___M 0xFE000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__PKG_ID___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B56___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B56___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB__RSVD_R18_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_QC_SECURE_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB (0x005C7098) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB (0x005C709C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW0_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB (0x005C70A0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB (0x005C70A4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW1_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB (0x005C70A8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB (0x005C70AC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW2_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB (0x005C70B0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB (0x005C70B4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW3_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB (0x005C70B8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB (0x005C70BC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW4_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW5_LSB (0x005C70C0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW5_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW5_LSB__OEM_PK_HASH_M0_WORD0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW5_LSB__OEM_PK_HASH_M0_WORD0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW5_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW5_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW5_MSB (0x005C70C4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW5_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW5_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW5_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW5_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW5_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW5_MSB__OEM_PK_HASH_M0_WORD1___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW5_MSB__OEM_PK_HASH_M0_WORD1___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW5_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW5_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_LSB (0x005C70C8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_LSB__OEM_PK_HASH_M0_WORD2_23_0___M 0xFFFFFF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_LSB__OEM_PK_HASH_M0_WORD2_23_0___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_LSB__OEM_PK_HASH_M0_WORD1___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_LSB__OEM_PK_HASH_M0_WORD1___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_MSB (0x005C70CC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_MSB__OEM_PK_HASH_M0_WORD3___M 0x00FFFF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_MSB__OEM_PK_HASH_M0_WORD3___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_MSB__OEM_PK_HASH_M0_WORD2_31_24___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_MSB__OEM_PK_HASH_M0_WORD2_31_24___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW6_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_LSB (0x005C70D0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_LSB__OEM_PK_HASH_M0_WORD4_15_0___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_LSB__OEM_PK_HASH_M0_WORD4_15_0___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_LSB__OEM_PK_HASH_M0_WORD3___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_LSB__OEM_PK_HASH_M0_WORD3___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_MSB (0x005C70D4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_MSB__OEM_PK_HASH_M0_WORD5___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_MSB__OEM_PK_HASH_M0_WORD5___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_MSB__OEM_PK_HASH_M0_WORD4_31_16___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_MSB__OEM_PK_HASH_M0_WORD4_31_16___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW7_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_LSB (0x005C70D8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_LSB__OEM_PK_HASH_M0_WORD6_7_0___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_LSB__OEM_PK_HASH_M0_WORD6_7_0___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_LSB__OEM_PK_HASH_M0_WORD5___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_LSB__OEM_PK_HASH_M0_WORD5___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_MSB (0x005C70DC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_MSB__OEM_PK_HASH_M0_WORD6_31_8___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_MSB__OEM_PK_HASH_M0_WORD6_31_8___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW8_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_LSB (0x005C70E0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_LSB__OEM_PK_HASH_M0_WORD7___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_LSB__OEM_PK_HASH_M0_WORD7___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB (0x005C70E4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_PK_HASH_ROW9_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB (0x005C70E8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__SPARE_REGION_16_FEC_ENABLE___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__SPARE_REGION_16_FEC_ENABLE___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__SPARE_REGION_15_FEC_ENABLE___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__SPARE_REGION_15_FEC_ENABLE___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__OEM_WIP_FEC_ENABLE___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__OEM_WIP_FEC_ENABLE___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__OTP_PATCH_FEC_ENABLE___M 0x00003000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__OTP_PATCH_FEC_ENABLE___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__WIP_FEC_ENABLE___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__WIP_FEC_ENABLE___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__BT_FEC_ENABLE___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__BT_FEC_ENABLE___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__PMU_RFA_SEQUENCE_FEC_ENABLE___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__PMU_RFA_SEQUENCE_FEC_ENABLE___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__MEMORY_CONFIG_FEC_ENABLE___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__MEMORY_CONFIG_FEC_ENABLE___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__OEM_PK_HASH_FEC_ENABLE___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__OEM_PK_HASH_FEC_ENABLE___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB__RSVD_R29_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB (0x005C70EC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B63___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B63___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B62___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B62___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B61___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B61___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B60___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B60___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B59___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B59___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B58___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B58___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B57___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B57___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B56___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B56___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB__RSVD_R29_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_FEC_CONTROL_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW0_LSB (0x005C70F0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW0_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW0_LSB__FUSE_MEM_REDUN_WORD_31_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW0_LSB__FUSE_MEM_REDUN_WORD_31_0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW0_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW0_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW0_MSB (0x005C70F4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW0_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW0_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW0_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW0_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW0_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW0_MSB__FUSE_MEM_REDUN_WORD_55_32___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW0_MSB__FUSE_MEM_REDUN_WORD_55_32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW0_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW0_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB (0x005C70F8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__FUSE_MEM_REDUN_WORD___M 0x00000003 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB__FUSE_MEM_REDUN_WORD___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB (0x005C70FC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW1_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW2_LSB (0x005C7100) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW2_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW2_LSB__BTFM_FUSE_COMPILERMEM_ACC_WORD_31_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW2_LSB__BTFM_FUSE_COMPILERMEM_ACC_WORD_31_0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW2_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW2_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW2_MSB (0x005C7104) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW2_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW2_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW2_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW2_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW2_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW2_MSB__BTFM_FUSE_COMPILERMEM_ACC_WORD_55_32___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW2_MSB__BTFM_FUSE_COMPILERMEM_ACC_WORD_55_32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW2_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW2_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB (0x005C7108) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__BTFM_FUSE_CUSTOMMEM_ACC___M 0x00FFFF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__BTFM_FUSE_CUSTOMMEM_ACC___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__BTFM_FUSE_COMPILERMEM_ACC_WORD___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB__BTFM_FUSE_COMPILERMEM_ACC_WORD___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB (0x005C710C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_MEMORY_CONFIG_ROW3_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_LSB (0x005C7110) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_LSB__PMU_SEQUENCE_2_HFRC_TRIM_3_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_LSB__PMU_SEQUENCE_2_HFRC_TRIM_3_0___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_LSB__PMU_SEQUENCE_1_LFRC_TRIM___M 0x0FFFC000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_LSB__PMU_SEQUENCE_1_LFRC_TRIM___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_LSB__PMU_SEQUENCE_0_LPO2M_TRIM___M 0x00003FFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_LSB__PMU_SEQUENCE_0_LPO2M_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_MSB (0x005C7114) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_MSB__PMU_SEQUENCE_3_LDO_AO_NOM_TRIM___M 0x00FFFC00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_MSB__PMU_SEQUENCE_3_LDO_AO_NOM_TRIM___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_MSB__PMU_SEQUENCE_2_HFRC_TRIM_13_4___M 0x000003FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_MSB__PMU_SEQUENCE_2_HFRC_TRIM_13_4___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW0_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_LSB (0x005C7118) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_LSB__PMU_SEQUENCE_6_LDO_AO_LOWSVS_TRIM_3_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_LSB__PMU_SEQUENCE_6_LDO_AO_LOWSVS_TRIM_3_0___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_LSB__PMU_SEQUENCE_5_LDO_AO_SVS_TRIM___M 0x0FFFC000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_LSB__PMU_SEQUENCE_5_LDO_AO_SVS_TRIM___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_LSB__PMU_SEQUENCE_4_LDO_AO_RET_TRIM___M 0x00003FFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_LSB__PMU_SEQUENCE_4_LDO_AO_RET_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_MSB (0x005C711C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_MSB__PMU_SEQUENCE_7_LDO_BTCMX_NOM_TRIM___M 0x00FFFC00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_MSB__PMU_SEQUENCE_7_LDO_BTCMX_NOM_TRIM___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_MSB__PMU_SEQUENCE_6_LDO_AO_LOWSVS_TRIM_13_4___M 0x000003FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_MSB__PMU_SEQUENCE_6_LDO_AO_LOWSVS_TRIM_13_4___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW1_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_LSB (0x005C7120) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_LSB__PMU_SEQUENCE_10_LDO_WLCX_RET_TRIM_3_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_LSB__PMU_SEQUENCE_10_LDO_WLCX_RET_TRIM_3_0___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_LSB__PMU_SEQUENCE_9_LDO_WLCX_NOM_TRIM___M 0x0FFFC000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_LSB__PMU_SEQUENCE_9_LDO_WLCX_NOM_TRIM___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_LSB__PMU_SEQUENCE_8_LDO_BTCMX_RET_TRIM___M 0x00003FFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_LSB__PMU_SEQUENCE_8_LDO_BTCMX_RET_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_MSB (0x005C7124) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_MSB__PMU_SEQUENCE_11_LDO_WLCX_SVS_TRIM___M 0x00FFFC00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_MSB__PMU_SEQUENCE_11_LDO_WLCX_SVS_TRIM___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_MSB__PMU_SEQUENCE_10_LDO_WLCX_RET_TRIM_13_4___M 0x000003FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_MSB__PMU_SEQUENCE_10_LDO_WLCX_RET_TRIM_13_4___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW2_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_LSB (0x005C7128) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_LSB__PMU_SEQUENCE_14_LDO_WLMX_RET_TRIM_3_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_LSB__PMU_SEQUENCE_14_LDO_WLMX_RET_TRIM_3_0___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_LSB__PMU_SEQUENCE_13_LDO_WLMX_NOM_TRIM___M 0x0FFFC000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_LSB__PMU_SEQUENCE_13_LDO_WLMX_NOM_TRIM___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_LSB__PMU_SEQUENCE_12_LDO_WLCX_L1_TRIM___M 0x00003FFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_LSB__PMU_SEQUENCE_12_LDO_WLCX_L1_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_MSB (0x005C712C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_MSB__PMU_SEQUENCE_15_LDO_WLMX_SVS_TRIM___M 0x00FFFC00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_MSB__PMU_SEQUENCE_15_LDO_WLMX_SVS_TRIM___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_MSB__PMU_SEQUENCE_14_LDO_WLMX_RET_TRIM_13_4___M 0x000003FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_MSB__PMU_SEQUENCE_14_LDO_WLMX_RET_TRIM_13_4___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW3_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_LSB (0x005C7130) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_LSB__PMU_SEQUENCE_18_LDO_RFACMN_NOM_TRIM_3_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_LSB__PMU_SEQUENCE_18_LDO_RFACMN_NOM_TRIM_3_0___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_LSB__PMU_SEQUENCE_17_LDO_WLMX_L1_TRIM___M 0x0FFFC000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_LSB__PMU_SEQUENCE_17_LDO_WLMX_L1_TRIM___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_LSB__PMU_SEQUENCE_16_LDO_WLMX_LOWSVS_TRIM___M 0x00003FFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_LSB__PMU_SEQUENCE_16_LDO_WLMX_LOWSVS_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_MSB (0x005C7134) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_MSB__PMU_SEQUENCE_19_LDO_RFACMN_RET_TRIM___M 0x00FFFC00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_MSB__PMU_SEQUENCE_19_LDO_RFACMN_RET_TRIM___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_MSB__PMU_SEQUENCE_18_LDO_RFACMN_NOM_TRIM_13_4___M 0x000003FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_MSB__PMU_SEQUENCE_18_LDO_RFACMN_NOM_TRIM_13_4___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW4_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_LSB (0x005C7138) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_LSB__PMU_SEQUENCE_22_LDO_RFA1P2_NOM_TRIM_3_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_LSB__PMU_SEQUENCE_22_LDO_RFA1P2_NOM_TRIM_3_0___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_LSB__PMU_SEQUENCE_21_LDO_AO_NOM_TRIM_095___M 0x0FFFC000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_LSB__PMU_SEQUENCE_21_LDO_AO_NOM_TRIM_095___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_LSB__PMU_SEQUENCE_20_LDO_RFA0P8_NOM_TRIM___M 0x00003FFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_LSB__PMU_SEQUENCE_20_LDO_RFA0P8_NOM_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_MSB (0x005C713C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_MSB__PMU_SEQUENCE_23_LDO_AO_SVS_TRM_095___M 0x00FFFC00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_MSB__PMU_SEQUENCE_23_LDO_AO_SVS_TRM_095___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_MSB__PMU_SEQUENCE_22_LDO_RFA1P2_NOM_TRIM_13_4___M 0x000003FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_MSB__PMU_SEQUENCE_22_LDO_RFA1P2_NOM_TRIM_13_4___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW5_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_LSB (0x005C7140) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_LSB__PMU_SEQUENCE_26_LDO_RFA1P7_NOM_TRIM_3_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_LSB__PMU_SEQUENCE_26_LDO_RFA1P7_NOM_TRIM_3_0___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_LSB__PMU_SEQUENCE_25_LDO_PCIE0P9_RET_TRIM___M 0x0FFFC000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_LSB__PMU_SEQUENCE_25_LDO_PCIE0P9_RET_TRIM___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_LSB__PMU_SEQUENCE_24_LDO_PCIE0P9_NOM_TRIM___M 0x00003FFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_LSB__PMU_SEQUENCE_24_LDO_PCIE0P9_NOM_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_MSB (0x005C7144) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_MSB__PMU_SEQUENCE_27_LDO_AO_LOWSVS_TRIM_095___M 0x00FFFC00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_MSB__PMU_SEQUENCE_27_LDO_AO_LOWSVS_TRIM_095___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_MSB__PMU_SEQUENCE_26_LDO_RFA1P7_NOM_TRIM_13_4___M 0x000003FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_MSB__PMU_SEQUENCE_26_LDO_RFA1P7_NOM_TRIM_13_4___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW6_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_LSB (0x005C7148) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_LSB__PMU_SEQUENCE_30_LDO_RFACMN_NOM_TRIM_095_3_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_LSB__PMU_SEQUENCE_30_LDO_RFACMN_NOM_TRIM_095_3_0___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_LSB__PMU_SEQUENCE_29_LDO_PCIE1P8_RET_TRIM___M 0x0FFFC000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_LSB__PMU_SEQUENCE_29_LDO_PCIE1P8_RET_TRIM___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_LSB__PMU_SEQUENCE_28_LDO_PCIE1P8_NOM_TRIM___M 0x00003FFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_LSB__PMU_SEQUENCE_28_LDO_PCIE1P8_NOM_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_MSB (0x005C714C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_MSB__PMU_SEQUENCE_31_LDO_RFACMN_RET_TRIM_095___M 0x00FFFC00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_MSB__PMU_SEQUENCE_31_LDO_RFACMN_RET_TRIM_095___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_MSB__PMU_SEQUENCE_30_LDO_RFACMN_NOM_TRIM_095_13_4___M 0x000003FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_MSB__PMU_SEQUENCE_30_LDO_RFACMN_NOM_TRIM_095_13_4___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW7_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB (0x005C7150) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__TOP_BGU_PTAT_CODE___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__TOP_BGU_PTAT_CODE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__TOP_BGT_ICTRL___M 0x00C00000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__TOP_BGT_ICTRL___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__TOP_BGU_CTATN_CODE___M 0x003F0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__TOP_BGU_CTATN_CODE___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__RSVD_R42_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__RSVD_R42_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__APPLY_BG_PARAM___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__APPLY_BG_PARAM___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__TOP_BGU_CTATP_CODE___M 0x00003F00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__TOP_BGU_CTATP_CODE___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__RSVD_R42_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__RSVD_R42_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__APPLY_CLK_SEL_PARAM___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__APPLY_CLK_SEL_PARAM___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__CLK_OUT_FREQ_SEL___M 0x00000030 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__CLK_OUT_FREQ_SEL___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__CLK_SEL___M 0x0000000E +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__CLK_SEL___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__TCXO_MODE___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB__TCXO_MODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB (0x005C7154) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_BGT_PTAT_CODE___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_BGT_PTAT_CODE___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_BGU_ICTRL___M 0x0000C000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_BGU_ICTRL___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_BGT_CTATN_CODE___M 0x00003F00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_BGT_CTATN_CODE___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_PTT_ICTRL___M 0x000000C0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_PTT_ICTRL___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_BGT_CTATP_CODE___M 0x0000003F +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_BGT_CTATP_CODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW8_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_LSB (0x005C7158) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_LSB__XO_SLOPE_TRIM___M 0xF0000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_LSB__XO_SLOPE_TRIM___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_LSB__APPLY_XO_PARAM___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_LSB__APPLY_XO_PARAM___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_LSB__XO_CDACOUT___M 0x07FC0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_LSB__XO_CDACOUT___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_LSB__XO_CDACIN___M 0x0003FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_LSB__XO_CDACIN___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_LSB__TOP_PTT_RCODE___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_LSB__TOP_PTT_RCODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB (0x005C715C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__XO_DCC_VAR_DEL_96M___M 0x00E00000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__XO_DCC_VAR_DEL_96M___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__XO_DCC_VAR_DEL___M 0x001C0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__XO_DCC_VAR_DEL___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__XO_FLTRBWSW___M 0x00030000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__XO_FLTRBWSW___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__RSVD_R43_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__RSVD_R43_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__XO_GM_TRIM___M 0x00007000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__XO_GM_TRIM___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__XO_BUF_N___M 0x00000F00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__XO_BUF_N___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__XO_DBLR_SEL_EDGE___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__XO_DBLR_SEL_EDGE___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__XO_BIAS_TRIM___M 0x00000070 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__XO_BIAS_TRIM___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__XO_BUF_P___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB__XO_BUF_P___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW9_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB (0x005C7160) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__LDO_WL_SYNTH2_SDM_VREF___M 0xF0000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__LDO_WL_SYNTH2_SDM_VREF___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__OTP_APPLY_LDO_PARAM___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__OTP_APPLY_LDO_PARAM___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__XO_VREF_VSEL___M 0x07000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__XO_VREF_VSEL___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__XO_VREF_BWSEL___M 0x00C00000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__XO_VREF_BWSEL___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__XO_LDO08_ICTRL___M 0x00380000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__XO_LDO08_ICTRL___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__XO_LDO13_ICTRL___M 0x00070000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__XO_LDO13_ICTRL___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__XO_LDO08_VSEL___M 0x0000F000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__XO_LDO08_VSEL___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__XO_LDO13_VSEL___M 0x00000F00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__XO_LDO13_VSEL___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__RSVD_R44_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__RSVD_R44_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__APPLY_DLL_PARAM___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__APPLY_DLL_PARAM___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__DLL_DIFF_EN_DIS___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__DLL_DIFF_EN_DIS___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__DLL_CLK_MUX_SEL___M 0x0000001C +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__DLL_CLK_MUX_SEL___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__DLL_CLK_DRV___M 0x00000003 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB__DLL_CLK_DRV___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB (0x005C7164) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB__LDO2_BT_DPLL_VREF___M 0x00F00000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB__LDO2_BT_DPLL_VREF___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB__LDO1_BT_DPLL_VREF___M 0x000F0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB__LDO1_BT_DPLL_VREF___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB__LDO0_BT_DPLL_VREF___M 0x0000F000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB__LDO0_BT_DPLL_VREF___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB__LDO2_WL_DPLL_VREF___M 0x00000F00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB__LDO2_WL_DPLL_VREF___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB__LDO1_WL_DPLL_VREF___M 0x000000F0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB__LDO1_WL_DPLL_VREF___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB__LDO0_WL_DPLL_VREF___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB__LDO0_WL_DPLL_VREF___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW10_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB (0x005C7168) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_TXLO_VREF_5G_CH1___M 0xF0000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_TXLO_VREF_5G_CH1___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_TXLO_VREF_2G_CH1___M 0x0F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_TXLO_VREF_2G_CH1___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_TXLO_VREF_5G_CH0___M 0x00F00000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_TXLO_VREF_5G_CH0___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_TXLO_VREF_2G_CH0___M 0x000F0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_TXLO_VREF_2G_CH0___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_RXLO_VREF_5G_CH1___M 0x0000F000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_RXLO_VREF_5G_CH1___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_RXLO_VREF_2G_CH1___M 0x00000F00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_RXLO_VREF_2G_CH1___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_RXLO_VREF_5G_CH0___M 0x000000F0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_RXLO_VREF_5G_CH0___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_RXLO_VREF_2G_CH0___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_RXLO_VREF_2G_CH0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB (0x005C716C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_SYNTH0_LOGEN_VREF___M 0x00F00000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_SYNTH0_LOGEN_VREF___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_BT_TXLO_VREF___M 0x000F0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_BT_TXLO_VREF___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_DAC_VREF_5G_CH1___M 0x0000F000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_DAC_VREF_5G_CH1___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_DAC_VREF_2G_CH1___M 0x00000F00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_DAC_VREF_2G_CH1___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_DAC_VREF_5G_CH0___M 0x000000F0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_DAC_VREF_5G_CH0___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_DAC_VREF_2G_CH0___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_DAC_VREF_2G_CH0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW11_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB (0x005C7170) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_ADC_VREF_5G_CH1___M 0x38000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_ADC_VREF_5G_CH1___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_ADC_VREF_2G_CH1___M 0x07000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_ADC_VREF_2G_CH1___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_ADC_VREF_5G_CH0___M 0x00380000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_ADC_VREF_5G_CH0___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_ADC_VREF_2G_CH0___M 0x00070000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_ADC_VREF_2G_CH0___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_SYNTH2_VREF___M 0x00003800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_SYNTH2_VREF___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_SYNTH1_VREF___M 0x00000700 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_SYNTH1_VREF___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_SYNTH0_VREF___M 0x00000070 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_SYNTH0_VREF___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_SYNTH1_LOGEN_VREF___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_SYNTH1_LOGEN_VREF___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB (0x005C7174) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD_R46_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD_R46_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD_R46_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD_R46_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__APPLY_BOOTUP_PARAM___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__APPLY_BOOTUP_PARAM___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__TOP_BIAS_SETTLE_TIME___M 0x001C0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__TOP_BIAS_SETTLE_TIME___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__TOP_FC_WIDTH___M 0x00030000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__TOP_FC_WIDTH___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__TOP_STARTUP_WIDTH___M 0x0000C000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__TOP_STARTUP_WIDTH___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__SETTIME_TOP_FC___M 0x00003000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__SETTIME_TOP_FC___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__SETTIME_TOP_STARTUP___M 0x00000C00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__SETTIME_TOP_STARTUP___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__SETTIME_BGT_EN___M 0x00000300 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__SETTIME_BGT_EN___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD_R46_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD_R46_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD_R46_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD_R46_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__LDO_BT_SYNTH_LOLDO_VREF06___M 0x00000038 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__LDO_BT_SYNTH_LOLDO_VREF06___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__LDO_BT_SYNTH_REFGEN_VREF___M 0x00000007 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB__LDO_BT_SYNTH_REFGEN_VREF___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW12_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB (0x005C7178) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__WL_LDO_SETTLE_TIME___M 0xF0000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__WL_LDO_SETTLE_TIME___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__XO_LDO_SETTLE_TIME___M 0x0F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__XO_LDO_SETTLE_TIME___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__XO_SETTLE_TIME___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__XO_SETTLE_TIME___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__DBLR_SETTLE_TIME___M 0x00007F00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__DBLR_SETTLE_TIME___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__TCXO_SETTLE_TIME___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB__TCXO_SETTLE_TIME___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB (0x005C717C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB__BTFMPLL_SETTLE_TIME___M 0x00F00000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB__BTFMPLL_SETTLE_TIME___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB__BBPLL_SETTLE_TIME___M 0x000F0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB__BBPLL_SETTLE_TIME___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB__BTFMPLL_LDO_SETTLE_TIME___M 0x0000F000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB__BTFMPLL_LDO_SETTLE_TIME___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB__BBPLL_LDO_SETTLE_TIME___M 0x00000F00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB__BBPLL_LDO_SETTLE_TIME___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB__CM_LDO_SETTLE_TIME___M 0x000000F0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB__CM_LDO_SETTLE_TIME___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB__BT_LDO_SETTLE_TIME___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB__BT_LDO_SETTLE_TIME___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW13_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_LSB (0x005C7180) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_LSB__XO_SETTLE_TIME_CUSTOM___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_LSB__XO_SETTLE_TIME_CUSTOM___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_LSB__TCXO_SETTLE_TIME_CUSTOM___M 0x00F00000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_LSB__TCXO_SETTLE_TIME_CUSTOM___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_LSB__XO_CAP_CUSTOM_OVERWRITE___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_LSB__XO_CAP_CUSTOM_OVERWRITE___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_LSB__XO_CDACOUT_CUSTOM___M 0x0007FC00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_LSB__XO_CDACOUT_CUSTOM___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_LSB__XO_CDACIN_CUSTOM___M 0x000003FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_LSB__XO_CDACIN_CUSTOM___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB (0x005C7184) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__XO_SETTLE_CUSTOM_OVERWRITE___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB__XO_SETTLE_CUSTOM_OVERWRITE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_PMU_RFA_SEQUENCE_ROW14_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_LSB (0x005C7188) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_LSB__OTP_MAGIC_NUMBER___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_LSB__OTP_MAGIC_NUMBER___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB (0x005C718C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__BTUARTBAUD___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__BTUARTBAUD___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__RSVD_39_47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__RSVD_39_47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__RADIO_DISABLE___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__RADIO_DISABLE___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__LC_DISABLE___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__LC_DISABLE___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__COEX_MCI_EN___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__COEX_MCI_EN___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__DISABLE_DEBUG_VSC___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__DISABLE_DEBUG_VSC___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__DISABLE_DEBUG_SSR___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__DISABLE_DEBUG_SSR___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__EXT_NVM___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__EXT_NVM___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__EXT_DSET___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__EXT_DSET___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__HID_OFFLOAD___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__HID_OFFLOAD___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__HOGP_OFFLOAD___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__HOGP_OFFLOAD___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__F64M___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__F64M___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__EDL_OVR_DBGUART___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__EDL_OVR_DBGUART___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__AUTOBAUD___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__AUTOBAUD___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__PHY_MODE___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__PHY_MODE___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__EMULATION_MODE___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__EMULATION_MODE___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__RSVD_R49_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB__RSVD_R49_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW0_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_LSB (0x005C7190) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_LSB__PRIMARY_BD_ADDRESS_LOW___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_LSB__PRIMARY_BD_ADDRESS_LOW___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_MSB (0x005C7194) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_MSB__RFKILL___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_MSB__RFKILL___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_MSB__PRIMARY_BD_ADDRESS_HIGH___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_MSB__PRIMARY_BD_ADDRESS_HIGH___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW1_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_LSB (0x005C7198) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_LSB__SIDESWITCHDISABLEDELAY___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_LSB__SIDESWITCHDISABLEDELAY___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_LSB__SIDESWITCHENABLEDELAY___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_LSB__SIDESWITCHENABLEDELAY___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_MSB (0x005C719C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_MSB__OTP_REG_PRGM_END_ADDR___M 0x00FFFF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_MSB__OTP_REG_PRGM_END_ADDR___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_MSB__OTP_REG_PRGM_LEN___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_MSB__OTP_REG_PRGM_LEN___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW2_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB (0x005C71A0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RBIAS_ICON_CODE___M 0x000000FC +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RBIAS_ICON_CODE___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__RSVD_R52_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__SHA256_HW_SW___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB__SHA256_HW_SW___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB (0x005C71A4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB__RSVD_R52_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW3_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW4_LSB (0x005C71A8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW4_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW4_LSB__BT_OTP_PATCH_RSVD0_31_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW4_LSB__BT_OTP_PATCH_RSVD0_31_0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW4_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW4_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW4_MSB (0x005C71AC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW4_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW4_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW4_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW4_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW4_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW4_MSB__BT_OTP_PATCH_RSVD0_55_32___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW4_MSB__BT_OTP_PATCH_RSVD0_55_32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW4_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW4_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW5_LSB (0x005C71B0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW5_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW5_LSB__BT_OTP_PATCH_RSVD1_31_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW5_LSB__BT_OTP_PATCH_RSVD1_31_0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW5_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW5_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW5_MSB (0x005C71B4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW5_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW5_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW5_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW5_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW5_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW5_MSB__BT_OTP_PATCH_RSVD1_55_32___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW5_MSB__BT_OTP_PATCH_RSVD1_55_32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW5_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW5_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_LSB (0x005C71B8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_LSB__GPIO_PIN_SET_BLK0_7_0___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_LSB__GPIO_PIN_SET_BLK0_7_0___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_LSB__RSVD_R55_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_LSB__RSVD_R55_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_LSB__RSVD_R55_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_LSB__RSVD_R55_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_LSB__RSVD_R55_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_LSB__RSVD_R55_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_LSB__RSVD_R55_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_LSB__RSVD_R55_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_LSB__GPIO_ENABLE_FLAG___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_LSB__GPIO_ENABLE_FLAG___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_MSB (0x005C71BC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_MSB__GPIO_PIN_SET_BLK1___M 0x00FFFF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_MSB__GPIO_PIN_SET_BLK1___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_MSB__GPIO_PIN_SET_BLK0_15_8___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_MSB__GPIO_PIN_SET_BLK0_15_8___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW6_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_LSB (0x005C71C0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_LSB__GPIO_PIN_SET_BLK3___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_LSB__GPIO_PIN_SET_BLK3___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_LSB__GPIO_PIN_SET_BLK2___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_LSB__GPIO_PIN_SET_BLK2___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_MSB (0x005C71C4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_MSB__GPIO_PIN_SET_BLK5___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_MSB__GPIO_PIN_SET_BLK5___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_MSB__GPIO_PIN_SET_BLK4___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_MSB__GPIO_PIN_SET_BLK4___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW7_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_LSB (0x005C71C8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_LSB__GPIO_PIN_SET_BLK7_7_0___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_LSB__GPIO_PIN_SET_BLK7_7_0___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_LSB__GPIO_PIN_SET_BLK6___M 0x00FFFF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_LSB__GPIO_PIN_SET_BLK6___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_LSB__GPIO_PIN_SET_BLK5___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_LSB__GPIO_PIN_SET_BLK5___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_MSB (0x005C71CC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_MSB__GPIO_PIN_SET_BLK8___M 0x00FFFF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_MSB__GPIO_PIN_SET_BLK8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_MSB__GPIO_PIN_SET_BLK7_15_8___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_MSB__GPIO_PIN_SET_BLK7_15_8___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW8_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_LSB (0x005C71D0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_LSB__GPIO_PIN_SET_BLK10___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_LSB__GPIO_PIN_SET_BLK10___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_LSB__GPIO_PIN_SET_BLK9___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_LSB__GPIO_PIN_SET_BLK9___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_MSB (0x005C71D4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_MSB__GPIO_PIN_SET_BLK12_OR_GPIO_CFG_TBL10___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_MSB__GPIO_PIN_SET_BLK12_OR_GPIO_CFG_TBL10___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_MSB__GPIO_PIN_SET_BLK11___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_MSB__GPIO_PIN_SET_BLK11___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW9_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_LSB (0x005C71D8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_LSB__GPIO_PIN_SET_BLK14_OR_GPIO_CFG_TBL8_7_0___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_LSB__GPIO_PIN_SET_BLK14_OR_GPIO_CFG_TBL8_7_0___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_LSB__GPIO_PIN_SET_BLK13_OR_GPIO_CFG_TBL9___M 0x00FFFF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_LSB__GPIO_PIN_SET_BLK13_OR_GPIO_CFG_TBL9___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_LSB__GPIO_PIN_SET_BLK12_OR_GPIO_CFG_TBL10___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_LSB__GPIO_PIN_SET_BLK12_OR_GPIO_CFG_TBL10___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_MSB (0x005C71DC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_MSB__GPIO_PIN_SET_BLK15_OR_GPIO_CFG_TBL7___M 0x00FFFF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_MSB__GPIO_PIN_SET_BLK15_OR_GPIO_CFG_TBL7___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_MSB__GPIO_PIN_SET_BLK14_OR_GPIO_CFG_TBL8_15_8___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_MSB__GPIO_PIN_SET_BLK14_OR_GPIO_CFG_TBL8_15_8___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW10_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_LSB (0x005C71E0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_LSB__GPIO_PIN_SET_BLK17_OR_GPIO_CFG_TBL5___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_LSB__GPIO_PIN_SET_BLK17_OR_GPIO_CFG_TBL5___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_LSB__GPIO_PIN_SET_BLK16_OR_GPIO_CFG_TBL6___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_LSB__GPIO_PIN_SET_BLK16_OR_GPIO_CFG_TBL6___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_MSB (0x005C71E4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_MSB__GPIO_PIN_SET_BLK19_OR_GPIO_CFG_TBL3___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_MSB__GPIO_PIN_SET_BLK19_OR_GPIO_CFG_TBL3___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_MSB__GPIO_PIN_SET_BLK18_OR_GPIO_CFG_TBL4___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_MSB__GPIO_PIN_SET_BLK18_OR_GPIO_CFG_TBL4___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW11_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_LSB (0x005C71E8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_LSB__GPIO_CFG_TBL1_7_0___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_LSB__GPIO_CFG_TBL1_7_0___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_LSB__GPIO_CFG_TBL2___M 0x00FFFF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_LSB__GPIO_CFG_TBL2___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_LSB__GPIO_PIN_SET_BLK19_OR_GPIO_CFG_TBL3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_LSB__GPIO_PIN_SET_BLK19_OR_GPIO_CFG_TBL3___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_MSB (0x005C71EC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_MSB__GPIO_CFG_TBL0___M 0x00FFFF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_MSB__GPIO_CFG_TBL0___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_MSB__GPIO_CFG_TBL1_15_8___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_MSB__GPIO_CFG_TBL1_15_8___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW12_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB (0x005C71F0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__RSVD_R62_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__RSVD_R62_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__RSVD_R62_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__RSVD_R62_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_REFDIV_96M___M 0x30000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_REFDIV_96M___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_OUTDIV_96M___M 0x0C000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_OUTDIV_96M___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_KD_96M___M 0x03C00000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_KD_96M___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_KI_96M___M 0x00300000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_KI_96M___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_REFDIV_48M___M 0x000C0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_REFDIV_48M___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_OUTDIV_48M___M 0x00030000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_OUTDIV_48M___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_KD_48M___M 0x0000F000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_KD_48M___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_KI_48M___M 0x00000C00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_KI_48M___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_REFDIV_38M___M 0x00000300 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_REFDIV_38M___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_OUTDIV_38M___M 0x000000C0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_OUTDIV_38M___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_KD_38M___M 0x0000003C +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_KD_38M___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_KI_38M___M 0x00000003 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB__BTFMPLL_KI_38M___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB (0x005C71F4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__RSVD_R62_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__BT_FEATURE_CONTROL___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB__BT_FEATURE_CONTROL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_BT_ROW13_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB (0x005C71F8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB__RSVD_R63_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB (0x005C71FC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB__RSVD_R63_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW0_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB (0x005C7200) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB__RSVD_R64_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB (0x005C7204) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB__RSVD_R64_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW1_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB (0x005C7208) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB__RSVD_R65_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB (0x005C720C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB__RSVD_R65_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW2_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB (0x005C7210) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB__RSVD_R66_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB (0x005C7214) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB__RSVD_R66_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW3_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB (0x005C7218) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB__RSVD_R67_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB (0x005C721C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB__RSVD_R67_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW4_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB (0x005C7220) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB__RSVD_R68_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB (0x005C7224) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB__RSVD_R68_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW5_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB (0x005C7228) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB__RSVD_R69_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB (0x005C722C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB__RSVD_R69_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW6_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB (0x005C7230) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB__RSVD_R70_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB (0x005C7234) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB__RSVD_R70_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW7_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB (0x005C7238) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB__RSVD_R71_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB (0x005C723C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB__RSVD_R71_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW8_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB (0x005C7240) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB__RSVD_R72_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB (0x005C7244) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB__RSVD_R72_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW9_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB (0x005C7248) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB__RSVD_R73_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB (0x005C724C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB__RSVD_R73_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW10_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB (0x005C7250) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB__RSVD_R74_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB (0x005C7254) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB__RSVD_R74_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_WIP_ROW11_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW0_LSB (0x005C7258) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW0_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW0_LSB__OTP_PATCH_31_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW0_LSB__OTP_PATCH_31_0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW0_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW0_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW0_MSB (0x005C725C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW0_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW0_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW0_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW0_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW0_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW0_MSB__OTP_PATCH_55_32___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW0_MSB__OTP_PATCH_55_32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW0_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW0_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW1_LSB (0x005C7260) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW1_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW1_LSB__OTP_PATCH_87_56___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW1_LSB__OTP_PATCH_87_56___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW1_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW1_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW1_MSB (0x005C7264) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW1_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW1_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW1_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW1_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW1_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW1_MSB__OTP_PATCH_111_88___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW1_MSB__OTP_PATCH_111_88___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW1_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW1_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW2_LSB (0x005C7268) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW2_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW2_LSB__OTP_PATCH_143_112___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW2_LSB__OTP_PATCH_143_112___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW2_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW2_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW2_MSB (0x005C726C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW2_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW2_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW2_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW2_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW2_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW2_MSB__OTP_PATCH_167_144___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW2_MSB__OTP_PATCH_167_144___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW2_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW2_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW3_LSB (0x005C7270) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW3_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW3_LSB__OTP_PATCH_199_168___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW3_LSB__OTP_PATCH_199_168___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW3_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW3_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW3_MSB (0x005C7274) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW3_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW3_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW3_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW3_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW3_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW3_MSB__OTP_PATCH_223_200___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW3_MSB__OTP_PATCH_223_200___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW3_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW3_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW4_LSB (0x005C7278) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW4_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW4_LSB__OTP_PATCH_255_224___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW4_LSB__OTP_PATCH_255_224___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW4_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW4_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW4_MSB (0x005C727C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW4_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW4_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW4_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW4_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW4_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW4_MSB__OTP_PATCH_279_256___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW4_MSB__OTP_PATCH_279_256___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW4_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW4_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW5_LSB (0x005C7280) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW5_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW5_LSB__OTP_PATCH_311_280___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW5_LSB__OTP_PATCH_311_280___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW5_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW5_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW5_MSB (0x005C7284) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW5_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW5_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW5_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW5_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW5_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW5_MSB__OTP_PATCH_335_312___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW5_MSB__OTP_PATCH_335_312___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW5_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW5_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW6_LSB (0x005C7288) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW6_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW6_LSB__OTP_PATCH_367_336___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW6_LSB__OTP_PATCH_367_336___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW6_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW6_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW6_MSB (0x005C728C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW6_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW6_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW6_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW6_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW6_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW6_MSB__OTP_PATCH_391_368___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW6_MSB__OTP_PATCH_391_368___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW6_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW6_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW7_LSB (0x005C7290) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW7_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW7_LSB__OTP_PATCH_423_392___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW7_LSB__OTP_PATCH_423_392___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW7_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW7_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW7_MSB (0x005C7294) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW7_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW7_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW7_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW7_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW7_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW7_MSB__OTP_PATCH_447_424___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW7_MSB__OTP_PATCH_447_424___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW7_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW7_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW8_LSB (0x005C7298) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW8_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW8_LSB__OTP_PATCH_479_448___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW8_LSB__OTP_PATCH_479_448___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW8_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW8_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW8_MSB (0x005C729C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW8_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW8_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW8_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW8_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW8_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW8_MSB__OTP_PATCH_503_480___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW8_MSB__OTP_PATCH_503_480___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW8_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW8_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW9_LSB (0x005C72A0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW9_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW9_LSB__OTP_PATCH_535_504___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW9_LSB__OTP_PATCH_535_504___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW9_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW9_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW9_MSB (0x005C72A4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW9_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW9_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW9_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW9_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW9_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW9_MSB__OTP_PATCH_559_536___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW9_MSB__OTP_PATCH_559_536___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW9_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW9_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW10_LSB (0x005C72A8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW10_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW10_LSB__OTP_PATCH_591_560___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW10_LSB__OTP_PATCH_591_560___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW10_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW10_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW10_MSB (0x005C72AC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW10_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW10_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW10_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW10_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW10_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW10_MSB__OTP_PATCH_615_592___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW10_MSB__OTP_PATCH_615_592___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW10_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW10_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW11_LSB (0x005C72B0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW11_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW11_LSB__OTP_PATCH_647_616___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW11_LSB__OTP_PATCH_647_616___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW11_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW11_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW11_MSB (0x005C72B4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW11_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW11_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW11_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW11_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW11_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW11_MSB__OTP_PATCH_671_648___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW11_MSB__OTP_PATCH_671_648___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW11_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW11_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW12_LSB (0x005C72B8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW12_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW12_LSB__OTP_PATCH_703_672___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW12_LSB__OTP_PATCH_703_672___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW12_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW12_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW12_MSB (0x005C72BC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW12_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW12_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW12_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW12_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW12_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW12_MSB__OTP_PATCH_727_704___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW12_MSB__OTP_PATCH_727_704___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW12_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW12_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW13_LSB (0x005C72C0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW13_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW13_LSB__OTP_PATCH_759_728___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW13_LSB__OTP_PATCH_759_728___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW13_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW13_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW13_MSB (0x005C72C4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW13_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW13_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW13_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW13_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW13_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW13_MSB__OTP_PATCH_783_760___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW13_MSB__OTP_PATCH_783_760___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW13_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW13_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW14_LSB (0x005C72C8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW14_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW14_LSB__OTP_PATCH_815_784___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW14_LSB__OTP_PATCH_815_784___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW14_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW14_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW14_MSB (0x005C72CC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW14_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW14_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW14_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW14_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW14_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW14_MSB__OTP_PATCH_839_816___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW14_MSB__OTP_PATCH_839_816___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW14_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW14_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW15_LSB (0x005C72D0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW15_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW15_LSB__OTP_PATCH_871_840___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW15_LSB__OTP_PATCH_871_840___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW15_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW15_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW15_MSB (0x005C72D4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW15_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW15_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW15_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW15_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW15_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW15_MSB__OTP_PATCH_895_872___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW15_MSB__OTP_PATCH_895_872___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW15_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW15_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW16_LSB (0x005C72D8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW16_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW16_LSB__OTP_PATCH_927_896___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW16_LSB__OTP_PATCH_927_896___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW16_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW16_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW16_MSB (0x005C72DC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW16_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW16_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW16_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW16_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW16_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW16_MSB__OTP_PATCH_951_928___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW16_MSB__OTP_PATCH_951_928___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW16_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW16_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW17_LSB (0x005C72E0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW17_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW17_LSB__OTP_PATCH_983_952___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW17_LSB__OTP_PATCH_983_952___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW17_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW17_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW17_MSB (0x005C72E4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW17_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW17_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW17_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW17_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW17_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW17_MSB__OTP_PATCH_1007_984___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW17_MSB__OTP_PATCH_1007_984___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW17_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW17_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW18_LSB (0x005C72E8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW18_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW18_LSB__OTP_PATCH_1039_1008___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW18_LSB__OTP_PATCH_1039_1008___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW18_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW18_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW18_MSB (0x005C72EC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW18_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW18_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW18_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW18_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW18_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW18_MSB__OTP_PATCH_1063_1040___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW18_MSB__OTP_PATCH_1063_1040___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW18_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW18_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW19_LSB (0x005C72F0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW19_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW19_LSB__OTP_PATCH_1095_1064___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW19_LSB__OTP_PATCH_1095_1064___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW19_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW19_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW19_MSB (0x005C72F4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW19_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW19_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW19_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW19_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW19_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW19_MSB__OTP_PATCH_1119_1096___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW19_MSB__OTP_PATCH_1119_1096___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW19_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW19_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW20_LSB (0x005C72F8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW20_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW20_LSB__OTP_PATCH_1151_1120___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW20_LSB__OTP_PATCH_1151_1120___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW20_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW20_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW20_MSB (0x005C72FC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW20_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW20_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW20_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW20_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW20_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW20_MSB__OTP_PATCH_1175_1152___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW20_MSB__OTP_PATCH_1175_1152___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW20_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW20_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW21_LSB (0x005C7300) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW21_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW21_LSB__OTP_PATCH_1207_1176___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW21_LSB__OTP_PATCH_1207_1176___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW21_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW21_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW21_MSB (0x005C7304) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW21_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW21_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW21_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW21_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW21_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW21_MSB__OTP_PATCH_1231_1208___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW21_MSB__OTP_PATCH_1231_1208___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW21_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW21_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW22_LSB (0x005C7308) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW22_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW22_LSB__OTP_PATCH_1263_1232___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW22_LSB__OTP_PATCH_1263_1232___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW22_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW22_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW22_MSB (0x005C730C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW22_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW22_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW22_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW22_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW22_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW22_MSB__OTP_PATCH_1287_1264___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW22_MSB__OTP_PATCH_1287_1264___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW22_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW22_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW23_LSB (0x005C7310) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW23_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW23_LSB__OTP_PATCH_1319_1288___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW23_LSB__OTP_PATCH_1319_1288___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW23_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW23_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW23_MSB (0x005C7314) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW23_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW23_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW23_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW23_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW23_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW23_MSB__OTP_PATCH_1343_1320___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW23_MSB__OTP_PATCH_1343_1320___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW23_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW23_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW24_LSB (0x005C7318) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW24_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW24_LSB__OTP_PATCH_1375_1344___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW24_LSB__OTP_PATCH_1375_1344___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW24_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW24_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW24_MSB (0x005C731C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW24_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW24_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW24_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW24_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW24_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW24_MSB__OTP_PATCH_1399_1376___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW24_MSB__OTP_PATCH_1399_1376___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW24_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW24_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW25_LSB (0x005C7320) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW25_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW25_LSB__OTP_PATCH_1431_1400___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW25_LSB__OTP_PATCH_1431_1400___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW25_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW25_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW25_MSB (0x005C7324) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW25_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW25_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW25_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW25_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW25_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW25_MSB__OTP_PATCH_1455_1432___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW25_MSB__OTP_PATCH_1455_1432___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW25_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW25_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW26_LSB (0x005C7328) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW26_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW26_LSB__OTP_PATCH_1487_1456___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW26_LSB__OTP_PATCH_1487_1456___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW26_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW26_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW26_MSB (0x005C732C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW26_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW26_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW26_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW26_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW26_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW26_MSB__OTP_PATCH_1511_1488___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW26_MSB__OTP_PATCH_1511_1488___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW26_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW26_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW27_LSB (0x005C7330) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW27_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW27_LSB__OTP_PATCH_1543_1512___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW27_LSB__OTP_PATCH_1543_1512___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW27_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW27_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW27_MSB (0x005C7334) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW27_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW27_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW27_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW27_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW27_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW27_MSB__OTP_PATCH_1567_1544___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW27_MSB__OTP_PATCH_1567_1544___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW27_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW27_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW28_LSB (0x005C7338) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW28_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW28_LSB__OTP_PATCH_1599_1568___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW28_LSB__OTP_PATCH_1599_1568___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW28_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW28_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW28_MSB (0x005C733C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW28_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW28_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW28_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW28_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW28_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW28_MSB__OTP_PATCH_1623_1600___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW28_MSB__OTP_PATCH_1623_1600___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW28_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW28_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW29_LSB (0x005C7340) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW29_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW29_LSB__OTP_PATCH_1655_1624___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW29_LSB__OTP_PATCH_1655_1624___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW29_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW29_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW29_MSB (0x005C7344) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW29_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW29_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW29_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW29_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW29_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW29_MSB__OTP_PATCH_1679_1656___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW29_MSB__OTP_PATCH_1679_1656___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW29_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW29_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW30_LSB (0x005C7348) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW30_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW30_LSB__OTP_PATCH_1711_1680___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW30_LSB__OTP_PATCH_1711_1680___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW30_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW30_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW30_MSB (0x005C734C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW30_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW30_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW30_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW30_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW30_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW30_MSB__OTP_PATCH_1735_1712___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW30_MSB__OTP_PATCH_1735_1712___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW30_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW30_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW31_LSB (0x005C7350) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW31_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW31_LSB__OTP_PATCH_1767_1736___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW31_LSB__OTP_PATCH_1767_1736___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW31_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW31_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW31_MSB (0x005C7354) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW31_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW31_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW31_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW31_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW31_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW31_MSB__OTP_PATCH_1791_1768___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW31_MSB__OTP_PATCH_1791_1768___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW31_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_ROW31_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW0_LSB (0x005C7358) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW0_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW0_LSB__OTP_PATCH_RSVD_31_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW0_LSB__OTP_PATCH_RSVD_31_0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW0_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW0_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW0_MSB (0x005C735C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW0_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW0_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW0_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW0_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW0_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW0_MSB__OTP_PATCH_RSVD_55_32___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW0_MSB__OTP_PATCH_RSVD_55_32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW0_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW0_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW1_LSB (0x005C7360) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW1_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW1_LSB__OTP_PATCH_RSVD_87_56___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW1_LSB__OTP_PATCH_RSVD_87_56___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW1_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW1_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW1_MSB (0x005C7364) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW1_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW1_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW1_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW1_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW1_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW1_MSB__OTP_PATCH_RSVD_111_88___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW1_MSB__OTP_PATCH_RSVD_111_88___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW1_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW1_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW2_LSB (0x005C7368) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW2_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW2_LSB__OTP_PATCH_RSVD_143_112___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW2_LSB__OTP_PATCH_RSVD_143_112___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW2_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW2_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW2_MSB (0x005C736C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW2_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW2_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW2_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW2_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW2_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW2_MSB__OTP_PATCH_RSVD_167_144___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW2_MSB__OTP_PATCH_RSVD_167_144___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW2_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW2_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW3_LSB (0x005C7370) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW3_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW3_LSB__OTP_PATCH_RSVD_199_168___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW3_LSB__OTP_PATCH_RSVD_199_168___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW3_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW3_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW3_MSB (0x005C7374) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW3_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW3_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW3_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW3_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW3_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW3_MSB__OTP_PATCH_RSVD_223_200___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW3_MSB__OTP_PATCH_RSVD_223_200___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW3_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW3_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW4_LSB (0x005C7378) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW4_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW4_LSB__OTP_PATCH_RSVD_255_224___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW4_LSB__OTP_PATCH_RSVD_255_224___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW4_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW4_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW4_MSB (0x005C737C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW4_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW4_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW4_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW4_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW4_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW4_MSB__OTP_PATCH_RSVD_279_256___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW4_MSB__OTP_PATCH_RSVD_279_256___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW4_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW4_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW5_LSB (0x005C7380) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW5_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW5_LSB__OTP_PATCH_RSVD_311_280___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW5_LSB__OTP_PATCH_RSVD_311_280___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW5_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW5_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW5_MSB (0x005C7384) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW5_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW5_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW5_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW5_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW5_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW5_MSB__OTP_PATCH_RSVD_335_312___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW5_MSB__OTP_PATCH_RSVD_335_312___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW5_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW5_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW6_LSB (0x005C7388) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW6_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW6_LSB__OTP_PATCH_RSVD_367_336___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW6_LSB__OTP_PATCH_RSVD_367_336___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW6_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW6_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW6_MSB (0x005C738C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW6_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW6_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW6_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW6_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW6_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW6_MSB__OTP_PATCH_RSVD_391_368___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW6_MSB__OTP_PATCH_RSVD_391_368___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW6_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW6_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW7_LSB (0x005C7390) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW7_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW7_LSB__OTP_PATCH_RSVD_423_392___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW7_LSB__OTP_PATCH_RSVD_423_392___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW7_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW7_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW7_MSB (0x005C7394) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW7_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW7_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW7_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW7_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW7_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW7_MSB__OTP_PATCH_RSVD_447_424___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW7_MSB__OTP_PATCH_RSVD_447_424___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW7_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW7_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW8_LSB (0x005C7398) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW8_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW8_LSB__OTP_PATCH_RSVD_479_448___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW8_LSB__OTP_PATCH_RSVD_479_448___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW8_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW8_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW8_MSB (0x005C739C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW8_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW8_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW8_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW8_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW8_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW8_MSB__OTP_PATCH_RSVD_503_480___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW8_MSB__OTP_PATCH_RSVD_503_480___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW8_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW8_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW9_LSB (0x005C73A0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW9_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW9_LSB__OTP_PATCH_RSVD_535_504___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW9_LSB__OTP_PATCH_RSVD_535_504___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW9_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW9_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW9_MSB (0x005C73A4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW9_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW9_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW9_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW9_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW9_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW9_MSB__OTP_PATCH_RSVD_559_536___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW9_MSB__OTP_PATCH_RSVD_559_536___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW9_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW9_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW10_LSB (0x005C73A8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW10_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW10_LSB__OTP_PATCH_RSVD_591_560___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW10_LSB__OTP_PATCH_RSVD_591_560___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW10_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW10_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW10_MSB (0x005C73AC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW10_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW10_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW10_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW10_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW10_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW10_MSB__OTP_PATCH_RSVD_615_592___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW10_MSB__OTP_PATCH_RSVD_615_592___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW10_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW10_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW11_LSB (0x005C73B0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW11_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW11_LSB__OTP_PATCH_RSVD_647_616___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW11_LSB__OTP_PATCH_RSVD_647_616___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW11_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW11_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW11_MSB (0x005C73B4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW11_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW11_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW11_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW11_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW11_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW11_MSB__OTP_PATCH_RSVD_671_648___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW11_MSB__OTP_PATCH_RSVD_671_648___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW11_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW11_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW12_LSB (0x005C73B8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW12_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW12_LSB__OTP_PATCH_RSVD_703_672___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW12_LSB__OTP_PATCH_RSVD_703_672___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW12_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW12_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW12_MSB (0x005C73BC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW12_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW12_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW12_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW12_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW12_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW12_MSB__OTP_PATCH_RSVD_727_704___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW12_MSB__OTP_PATCH_RSVD_727_704___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW12_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW12_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW13_LSB (0x005C73C0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW13_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW13_LSB__OTP_PATCH_RSVD_759_728___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW13_LSB__OTP_PATCH_RSVD_759_728___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW13_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW13_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW13_MSB (0x005C73C4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW13_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW13_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW13_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW13_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW13_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW13_MSB__OTP_PATCH_RSVD_783_760___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW13_MSB__OTP_PATCH_RSVD_783_760___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW13_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW13_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW14_LSB (0x005C73C8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW14_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW14_LSB__OTP_PATCH_RSVD_815_784___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW14_LSB__OTP_PATCH_RSVD_815_784___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW14_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW14_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW14_MSB (0x005C73CC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW14_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW14_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW14_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW14_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW14_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW14_MSB__OTP_PATCH_RSVD_839_816___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW14_MSB__OTP_PATCH_RSVD_839_816___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW14_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW14_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW15_LSB (0x005C73D0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW15_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW15_LSB__OTP_PATCH_RSVD_871_840___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW15_LSB__OTP_PATCH_RSVD_871_840___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW15_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW15_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW15_MSB (0x005C73D4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW15_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW15_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW15_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW15_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW15_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW15_MSB__OTP_PATCH_RSVD_895_872___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW15_MSB__OTP_PATCH_RSVD_895_872___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW15_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OTP_PATCH_RSVD_ROW15_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_LSB (0x005C73D8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_LSB__BTCUSMAGIC___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_LSB__BTCUSMAGIC___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB (0x005C73DC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD_R123_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD_R123_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD_R123_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD_R123_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD_R123_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD_R123_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD_R123_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD_R123_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD_R123_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD_R123_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD_R123_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD_R123_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD_R123_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD_R123_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD_R123_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__RSVD_R123_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__BTCUSSWCONFIG___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB__BTCUSSWCONFIG___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW0_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_LSB (0x005C73E0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_LSB__BTCUSBDADDR1_3___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_LSB__BTCUSBDADDR1_3___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_LSB__BTCUSBDADDR1_2___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_LSB__BTCUSBDADDR1_2___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_LSB__BTCUSBDADDR1_1___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_LSB__BTCUSBDADDR1_1___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_LSB__BTCUSBDADDR1_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_LSB__BTCUSBDADDR1_0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB (0x005C73E4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD_R124_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD_R124_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD_R124_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD_R124_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD_R124_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD_R124_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD_R124_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD_R124_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD_R124_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD_R124_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD_R124_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD_R124_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD_R124_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD_R124_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD_R124_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__RSVD_R124_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__BTCUSBDADDR1_5___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__BTCUSBDADDR1_5___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__BTCUSBDADDR1_4___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB__BTCUSBDADDR1_4___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW1_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_LSB (0x005C73E8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_LSB__BTCUSADADDR2_3___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_LSB__BTCUSADADDR2_3___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_LSB__BTCUSADADDR2_2___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_LSB__BTCUSADADDR2_2___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_LSB__BTCUSADADDR2_1___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_LSB__BTCUSADADDR2_1___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_LSB__BTCUSADADDR2_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_LSB__BTCUSADADDR2_0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB (0x005C73EC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD_R125_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD_R125_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD_R125_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD_R125_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD_R125_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD_R125_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD_R125_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD_R125_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD_R125_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD_R125_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD_R125_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD_R125_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD_R125_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD_R125_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD_R125_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__RSVD_R125_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__BTCUSADADDR2_5___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__BTCUSADADDR2_5___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__BTCUSADADDR2_4___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB__BTCUSADADDR2_4___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW2_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_LSB (0x005C73F0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_LSB__BTCUSSECKEY3___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_LSB__BTCUSSECKEY3___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_LSB__BTCUSSECKEY2___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_LSB__BTCUSSECKEY2___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_LSB__BTCUSSECKEY1___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_LSB__BTCUSSECKEY1___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_LSB__BTCUSSECKEY0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_LSB__BTCUSSECKEY0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_MSB (0x005C73F4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_MSB__BTCUSSECKEY6___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_MSB__BTCUSSECKEY6___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_MSB__BTCUSSECKEY5___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_MSB__BTCUSSECKEY5___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_MSB__BTCUSSECKEY4___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_MSB__BTCUSSECKEY4___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW3_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_LSB (0x005C73F8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_LSB__BTCUSSECKEY10___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_LSB__BTCUSSECKEY10___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_LSB__BTCUSSECKEY9___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_LSB__BTCUSSECKEY9___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_LSB__BTCUSSECKEY8___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_LSB__BTCUSSECKEY8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_LSB__BTCUSSECKEY7___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_LSB__BTCUSSECKEY7___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_MSB (0x005C73FC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_MSB__BTCUSSECKEY13___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_MSB__BTCUSSECKEY13___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_MSB__BTCUSSECKEY12___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_MSB__BTCUSSECKEY12___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_MSB__BTCUSSECKEY11___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_MSB__BTCUSSECKEY11___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW4_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_LSB (0x005C7400) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_LSB__BTCUSSECKEY17___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_LSB__BTCUSSECKEY17___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_LSB__BTCUSSECKEY16___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_LSB__BTCUSSECKEY16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_LSB__BTCUSSECKEY15___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_LSB__BTCUSSECKEY15___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_LSB__BTCUSSECKEY14___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_LSB__BTCUSSECKEY14___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_MSB (0x005C7404) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_MSB__BTCUSSECKEY20___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_MSB__BTCUSSECKEY20___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_MSB__BTCUSSECKEY19___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_MSB__BTCUSSECKEY19___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_MSB__BTCUSSECKEY18___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_MSB__BTCUSSECKEY18___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW5_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_LSB (0x005C7408) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_LSB__BTCUSSECKEY24___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_LSB__BTCUSSECKEY24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_LSB__BTCUSSECKEY23___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_LSB__BTCUSSECKEY23___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_LSB__BTCUSSECKEY22___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_LSB__BTCUSSECKEY22___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_LSB__BTCUSSECKEY21___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_LSB__BTCUSSECKEY21___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_MSB (0x005C740C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_MSB__BTCUSSECKEY27___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_MSB__BTCUSSECKEY27___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_MSB__BTCUSSECKEY26___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_MSB__BTCUSSECKEY26___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_MSB__BTCUSSECKEY25___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_MSB__BTCUSSECKEY25___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW6_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_LSB (0x005C7410) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_LSB__BTCUSSECKEY31___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_LSB__BTCUSSECKEY31___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_LSB__BTCUSSECKEY30___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_LSB__BTCUSSECKEY30___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_LSB__BTCUSSECKEY29___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_LSB__BTCUSSECKEY29___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_LSB__BTCUSSECKEY28___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_LSB__BTCUSSECKEY28___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_MSB (0x005C7414) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_MSB__BTCUSMANUSTR2___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_MSB__BTCUSMANUSTR2___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_MSB__BTCUSMANUSTR1___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_MSB__BTCUSMANUSTR1___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_MSB__BTCUSMANUSTR0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_MSB__BTCUSMANUSTR0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW7_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_LSB (0x005C7418) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_LSB__BTCUSMANUSTR6___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_LSB__BTCUSMANUSTR6___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_LSB__BTCUSMANUSTR5___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_LSB__BTCUSMANUSTR5___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_LSB__BTCUSMANUSTR4___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_LSB__BTCUSMANUSTR4___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_LSB__BTCUSMANUSTR3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_LSB__BTCUSMANUSTR3___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_MSB (0x005C741C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_MSB__BTCUSMANUSTR9___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_MSB__BTCUSMANUSTR9___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_MSB__BTCUSMANUSTR8___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_MSB__BTCUSMANUSTR8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_MSB__BTCUSMANUSTR7___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_MSB__BTCUSMANUSTR7___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW8_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_LSB (0x005C7420) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_LSB__BTCUSMANUSTR13___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_LSB__BTCUSMANUSTR13___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_LSB__BTCUSMANUSTR12___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_LSB__BTCUSMANUSTR12___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_LSB__BTCUSMANUSTR11___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_LSB__BTCUSMANUSTR11___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_LSB__BTCUSMANUSTR10___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_LSB__BTCUSMANUSTR10___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_MSB (0x005C7424) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_MSB__BTCUSMANUSTR16___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_MSB__BTCUSMANUSTR16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_MSB__BTCUSMANUSTR15___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_MSB__BTCUSMANUSTR15___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_MSB__BTCUSMANUSTR14___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_MSB__BTCUSMANUSTR14___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW9_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_LSB (0x005C7428) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_LSB__BTCUSMANUSTR20___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_LSB__BTCUSMANUSTR20___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_LSB__BTCUSMANUSTR19___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_LSB__BTCUSMANUSTR19___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_LSB__BTCUSMANUSTR18___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_LSB__BTCUSMANUSTR18___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_LSB__BTCUSMANUSTR17___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_LSB__BTCUSMANUSTR17___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_MSB (0x005C742C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_MSB__BTCUSMANUSTR23___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_MSB__BTCUSMANUSTR23___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_MSB__BTCUSMANUSTR22___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_MSB__BTCUSMANUSTR22___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_MSB__BTCUSMANUSTR21___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_MSB__BTCUSMANUSTR21___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW10_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_LSB (0x005C7430) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_LSB__BTCUSMANUSTR27___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_LSB__BTCUSMANUSTR27___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_LSB__BTCUSMANUSTR26___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_LSB__BTCUSMANUSTR26___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_LSB__BTCUSMANUSTR25___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_LSB__BTCUSMANUSTR25___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_LSB__BTCUSMANUSTR24___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_LSB__BTCUSMANUSTR24___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_MSB (0x005C7434) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_MSB__BTCUSMANUSTR30___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_MSB__BTCUSMANUSTR30___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_MSB__BTCUSMANUSTR29___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_MSB__BTCUSMANUSTR29___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_MSB__BTCUSMANUSTR28___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_MSB__BTCUSMANUSTR28___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW11_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_LSB (0x005C7438) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_LSB__BTCUSCONFIG2___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_LSB__BTCUSCONFIG2___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_LSB__BTCUSCONFIG1___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_LSB__BTCUSCONFIG1___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_LSB__BTCUSCONFIG0___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_LSB__BTCUSCONFIG0___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_LSB__BTCUSMANUSTR31___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_LSB__BTCUSMANUSTR31___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_MSB (0x005C743C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_MSB__BTCUSCONFIG5___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_MSB__BTCUSCONFIG5___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_MSB__BTCUSCONFIG4___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_MSB__BTCUSCONFIG4___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_MSB__BTCUSCONFIG3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_MSB__BTCUSCONFIG3___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW12_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_LSB (0x005C7440) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_LSB__BTCUSCONFIG9___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_LSB__BTCUSCONFIG9___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_LSB__BTCUSCONFIG8___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_LSB__BTCUSCONFIG8___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_LSB__BTCUSCONFIG7___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_LSB__BTCUSCONFIG7___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_LSB__BTCUSCONFIG6___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_LSB__BTCUSCONFIG6___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_MSB (0x005C7444) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_MSB__BTCUSCONFIG12___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_MSB__BTCUSCONFIG12___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_MSB__BTCUSCONFIG11___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_MSB__BTCUSCONFIG11___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_MSB__BTCUSCONFIG10___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_MSB__BTCUSCONFIG10___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW13_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB (0x005C7448) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__RSVD_R137_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__RSVD_R137_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__RSVD_R137_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__RSVD_R137_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__RSVD_R137_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__RSVD_R137_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__RSVD_R137_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__RSVD_R137_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__RSVD_R137_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__RSVD_R137_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__RSVD_R137_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__RSVD_R137_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__RSVD_R137_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__RSVD_R137_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__RSVD_R137_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__RSVD_R137_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__BTCUSCONFIG15___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__BTCUSCONFIG15___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__BTCUSCONFIG14___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__BTCUSCONFIG14___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__BTCUSCONFIG13___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB__BTCUSCONFIG13___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB (0x005C744C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB__RSVD_R137_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_OEM_BT_ROW14_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_LSB (0x005C7450) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_LSB__IDDQ_MX_ON___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_LSB__IDDQ_MX_ON___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_LSB__IDDQ_CX_ON___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_LSB__IDDQ_CX_ON___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_LSB__RSVD_R138_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_LSB__RSVD_R138_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_LSB__IDDQ_PERF_APC_ON___M 0x00007FC0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_LSB__IDDQ_PERF_APC_ON___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_LSB__IDDQ_REV_CTRL___M 0x00000038 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_LSB__IDDQ_REV_CTRL___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_LSB__IDDQ_MULTI_BIT___M 0x00000007 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_LSB__IDDQ_MULTI_BIT___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB (0x005C7454) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB__RSVD_R138_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB__RSVD_R138_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB__RSVD_R138_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB__RSVD_R138_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB__IDDQ_APC_ON___M 0x003F0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB__IDDQ_APC_ON___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB__IDDQ_NPU_ON___M 0x0000FE00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB__IDDQ_NPU_ON___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB__IDDQ_WCSS_ON___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB__IDDQ_WCSS_ON___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW0_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB (0x005C7458) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__RSVD_R139_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__RSVD_R139_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__IDDQ_NPU_OFF___M 0x7E000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__IDDQ_NPU_OFF___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__IDDQ_WCSS_OFF___M 0x01FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__IDDQ_WCSS_OFF___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__RSVD_R139_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__RSVD_R139_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__RSVD_R139_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__RSVD_R139_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__RSVD_R139_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__RSVD_R139_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__IDDQ_MX_OFF___M 0x00001F00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__IDDQ_MX_OFF___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__RSVD_R139_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__RSVD_R139_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__IDDQ_CX_OFF___M 0x0000007F +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB__IDDQ_CX_OFF___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB (0x005C745C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB__RSVD_R139_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_CALIBRATION_ROW1_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB (0x005C7460) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB__RSVD_R140_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB (0x005C7464) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD0___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD0___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__FEC_VALUE___M 0x7F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__FEC_VALUE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB__RSVD_R140_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_RAW_SPARE_REGION_16_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB (0x005CB000) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__RSVD_0_17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__SPARE_REGION_16_READ_DISABLE___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__SPARE_REGION_16_READ_DISABLE___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__SPARE_REGION_15_READ_DISABLE___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__SPARE_REGION_15_READ_DISABLE___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__OEM_WIP_READ_DISABLE___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__OEM_WIP_READ_DISABLE___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__OTP_PATCH_RSVD_READ_DISABLE___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__OTP_PATCH_RSVD_READ_DISABLE___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__OTP_PATCH_READ_DISABLE___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__OTP_PATCH_READ_DISABLE___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__WIP_READ_DISABLE___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__WIP_READ_DISABLE___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__BT_READ_DISABLE___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__BT_READ_DISABLE___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__PMU_RFA_SEQUENCE_READ_DISABLE___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__PMU_RFA_SEQUENCE_READ_DISABLE___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__MEMORY_CONFIG_READ_DISABLE___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__MEMORY_CONFIG_READ_DISABLE___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__FEC_CONTROL_READ_DISABLE___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__FEC_CONTROL_READ_DISABLE___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__OEM_PK_HASH_READ_DISABLE___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__OEM_PK_HASH_READ_DISABLE___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__QC_SECURE_READ_DISABLE___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__QC_SECURE_READ_DISABLE___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__ATE_READ_DISABLE___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__ATE_READ_DISABLE___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__TOP_READ_DISABLE___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__TOP_READ_DISABLE___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__OEM_SECURE_READ_DISABLE___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__OEM_SECURE_READ_DISABLE___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__ANTI_ROLLBACK_READ_DISABLE___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__ANTI_ROLLBACK_READ_DISABLE___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__PERMISSION_READ_DISABLE___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB__PERMISSION_READ_DISABLE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB (0x005CB004) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__QFPROM_CHECK_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__QFPROM_CHECK_EN___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_62___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_62___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_61___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_61___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_60___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_60___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_59___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_59___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_58___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_58___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_57___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_57___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_56___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_56___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__RSVD_0_49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__SPARE_REGION_16_WRITE_DISABLE___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__SPARE_REGION_16_WRITE_DISABLE___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__SPARE_REGION_15_WRITE_DISABLE___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__SPARE_REGION_15_WRITE_DISABLE___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__OEM_WIP_WRITE_DISABLE___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__OEM_WIP_WRITE_DISABLE___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__OTP_PATCH_RSVD_WRITE_DISABLE___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__OTP_PATCH_RSVD_WRITE_DISABLE___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__OTP_PATCH_WRITE_DISABLE___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__OTP_PATCH_WRITE_DISABLE___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__WIP_WRITE_DISABLE___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__WIP_WRITE_DISABLE___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__BT_WRITE_DISABLE___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__BT_WRITE_DISABLE___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__PMU_RFA_SEQUENCE_WRITE_DISABLE___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__PMU_RFA_SEQUENCE_WRITE_DISABLE___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__MEMORY_CONFIG_WRITE_DISABLE___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__MEMORY_CONFIG_WRITE_DISABLE___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__FEC_CONTROL_WRITE_DISABLE___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__FEC_CONTROL_WRITE_DISABLE___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__OEM_PK_HASH_WRITE_DISABLE___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__OEM_PK_HASH_WRITE_DISABLE___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__QC_SECURE_WRITE_DISABLE___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__QC_SECURE_WRITE_DISABLE___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__ATE_WRITE_DISABLE___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__ATE_WRITE_DISABLE___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__TOP_WRITE_DISABLE___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__TOP_WRITE_DISABLE___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__OEM_SECURE_WRITE_DISABLE___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__OEM_SECURE_WRITE_DISABLE___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__ANTI_ROLLBACK_WRITE_DISABLE___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__ANTI_ROLLBACK_WRITE_DISABLE___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__PERMISSION_WRITE_DISABLE___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB__PERMISSION_WRITE_DISABLE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_RD_WR_PERMISSION_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB (0x005CB008) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB__RSVD_R1_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_MSB (0x005CB00C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_MSB__ANTI_ROLLBACK_M0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_MSB__ANTI_ROLLBACK_M0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ANTI_ROLLBACK_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB (0x005CB010) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__RSVD_R2_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT3_RSVD___M 0x0000C000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT3_RSVD___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT3_USE_SERIAL_NUM___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT3_USE_SERIAL_NUM___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT3_AUTH_EN___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT3_AUTH_EN___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT2_RSVD___M 0x00000C00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT2_RSVD___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT2_USE_SERIAL_NUM___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT2_USE_SERIAL_NUM___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT2_AUTH_EN___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT2_AUTH_EN___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT1_RSVD___M 0x000000C0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT1_RSVD___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT1_USE_SERIAL_NUM___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT1_USE_SERIAL_NUM___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT1_AUTH_EN___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT1_AUTH_EN___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT0_RSVD___M 0x0000000C +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT0_RSVD___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT0_USE_SERIAL_NUM___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT0_USE_SERIAL_NUM___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT0_AUTH_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB__SECURE_BOOT0_AUTH_EN___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_MSB (0x005CB014) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_MSB__BT_FEATURE_BITS___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_MSB__BT_FEATURE_BITS___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW0_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB (0x005CB018) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__SW_FUSE_PROG_DISABLE___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__SW_FUSE_PROG_DISABLE___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__ENUM_TIMEOUT___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__ENUM_TIMEOUT___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RAM_DUMP_USE_SN___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RAM_DUMP_USE_SN___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__ANTI_ROLLBACK_FEATURE_EN_M0___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__ANTI_ROLLBACK_FEATURE_EN_M0___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__RSVD_R3_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__HASH_INTEGRITY_CHECK_DISABLE_M0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB__HASH_INTEGRITY_CHECK_DISABLE_M0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_MSB (0x005CB01C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_MSB__MODEL_ID___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_MSB__MODEL_ID___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_MSB__OEM_ID___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_MSB__OEM_ID___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW1_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB (0x005CB020) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RSVD_R4_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RAM_DUMP_DISABLE___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__RAM_DUMP_DISABLE___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__DISABLE_QC_RMA___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__DISABLE_QC_RMA___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__OEM_DEBUG_DISABLE_VECTOR___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB__OEM_DEBUG_DISABLE_VECTOR___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_MSB (0x005CB024) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_MSB__OEM_AUTOMOTIVE_FEATURES___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_MSB__OEM_AUTOMOTIVE_FEATURES___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_SECURE_ROW2_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW0_LSB (0x005CB028) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW0_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW0_LSB__SERIAL_NUM_31_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW0_LSB__SERIAL_NUM_31_0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW0_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW0_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW0_MSB (0x005CB02C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW0_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW0_MSB__JTAG_ID_15_0___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW0_MSB__JTAG_ID_15_0___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW0_MSB__SERIAL_NUM_47_32___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW0_MSB__SERIAL_NUM_47_32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW0_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW0_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB (0x005CB030) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__RSVD_R6_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__SPARE_R6_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__SPARE_R6_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__EXTERNAL_32K_SELECT___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__EXTERNAL_32K_SELECT___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__XO_CLK_SEL_VALID___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__XO_CLK_SEL_VALID___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__XO_CLK_SEL_RAW___M 0x00000060 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__XO_CLK_SEL_RAW___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__REFCLK_USE_TCXO___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__REFCLK_USE_TCXO___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__JTAG_ID_19_16___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB__JTAG_ID_19_16___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB (0x005CB034) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B63___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B63___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B62___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B62___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B61___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B61___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B60___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B60___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B59___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B59___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B58___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B58___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B57___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B57___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B56___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B56___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB__RSVD_R6_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW1_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB (0x005CB038) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__RFA_CLAMP_IO_SETTLE___M 0xE0000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__RFA_CLAMP_IO_SETTLE___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__TOP08RFA_LDO_SETTLE___M 0x1C000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__TOP08RFA_LDO_SETTLE___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__TOP12RFA_LDO_DLY___M 0x03800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__TOP12RFA_LDO_DLY___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__TOP17RFA_LDO_DLY___M 0x00700000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__TOP17RFA_LDO_DLY___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__VDD08AO_VLD___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__VDD08AO_VLD___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__VDD08AO_VALUE___M 0x0007F800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__VDD08AO_VALUE___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__VDD08AO_VSEL___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__VDD08AO_VSEL___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__SW_CTRL_DLY___M 0x00000380 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__SW_CTRL_DLY___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__TOP08RFACMN_LDO_DLY___M 0x00000070 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__TOP08RFACMN_LDO_DLY___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__VDD08RFACMN_VSEL___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__VDD08RFACMN_VSEL___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__VDD08RFA_VSEL___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__VDD08RFA_VSEL___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__VDD12RFA_VSEL___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__VDD12RFA_VSEL___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__VDD17RFA_VSEL___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB__VDD17RFA_VSEL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB (0x005CB03C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B63___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B63___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B62___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B62___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B61___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B61___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B60___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B60___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B59___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B59___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B58___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B58___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B57___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B57___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B56___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B56___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__RSVD_R7_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__VDD08AO_HRFC_VLD___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__VDD08AO_HRFC_VLD___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__VDD08AO_HRFC_TRIM___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB__VDD08AO_HRFC_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW2_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB (0x005CB040) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__RSVD_R8_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__TSENS_DEBUGBUS_DISABLE___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__TSENS_DEBUGBUS_DISABLE___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__OTP_PCIE_PHY_VDDA_SETTLE_DLY___M 0x0001E000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__OTP_PCIE_PHY_VDDA_SETTLE_DLY___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__OTP_PCIE_PHY_1P8_SETTLE_DLY___M 0x00001E00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__OTP_PCIE_PHY_1P8_SETTLE_DLY___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__OTP_WLCX_SETTLE_DLY___M 0x000001E0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__OTP_WLCX_SETTLE_DLY___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__OTP_WLMX_SETTLE_DLY___M 0x0000001E +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__OTP_WLMX_SETTLE_DLY___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__OTP_BLOWN_DONE___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB__OTP_BLOWN_DONE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB (0x005CB044) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__APB2JTAG_DISABLE___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__APB2JTAG_DISABLE___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B62___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B62___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B61___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B61___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B60___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B60___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B59___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B59___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B58___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B58___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B57___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B57___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B56___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B56___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB__RSVD_R8_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW3_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB (0x005CB048) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__RSVD_R9_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__WL_SEC_CTRL_AHB_FUSE_DISABLE___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__WL_SEC_CTRL_AHB_FUSE_DISABLE___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__BTC_DISABLE___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__BTC_DISABLE___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__ANT_DISABLE___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__ANT_DISABLE___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__BLE_DISABLE___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__BLE_DISABLE___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__WL_ONLY_WL_SLEEP___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__WL_ONLY_WL_SLEEP___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__LDOBTCX_RET_SETT_TIME___M 0x000000F0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__LDOBTCX_RET_SETT_TIME___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__LDOBTCX_SETT_TIME___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB__LDOBTCX_SETT_TIME___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB (0x005CB04C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B63___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B63___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B62___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B62___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B61___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B61___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B60___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B60___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B59___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B59___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B58___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B58___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B57___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B57___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B56___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B56___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__RSVD_R9_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__BOOT_PATCH_SELECT___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__BOOT_PATCH_SELECT___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__BT_MODE___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__BT_MODE___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__BT_MANU_PGM___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB__BT_MANU_PGM___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_TOP_ROW4_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_LSB (0x005CB050) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_LSB__LOT_ID_LOW_7_0___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_LSB__LOT_ID_LOW_7_0___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_LSB__DIE_Y___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_LSB__DIE_Y___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_LSB__DIE_X___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_LSB__DIE_X___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_LSB__WAFERID___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_LSB__WAFERID___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_MSB (0x005CB054) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_MSB__LOT_ID_HIGH_7_0___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_MSB__LOT_ID_HIGH_7_0___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_MSB__LOT_ID_LOW_31_8___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_MSB__LOT_ID_LOW_31_8___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW0_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_LSB (0x005CB058) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_LSB__PROGRAM_REVISION_LOW_15_0___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_LSB__PROGRAM_REVISION_LOW_15_0___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_LSB__PRODUCT_QUALITY_BINNING___M 0x0000F000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_LSB__PRODUCT_QUALITY_BINNING___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_LSB__TEST_INSERTION_MASK___M 0x00000F00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_LSB__TEST_INSERTION_MASK___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_LSB__LOT_ID_HIGH_15_8___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_LSB__LOT_ID_HIGH_15_8___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_MSB (0x005CB05C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_MSB__PROGRAM_REVISION_HIGH___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_MSB__PROGRAM_REVISION_HIGH___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_MSB__PROGRAM_REVISION_LOW_31_16___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_MSB__PROGRAM_REVISION_LOW_31_16___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW1_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW2_LSB (0x005CB060) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW2_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW2_LSB__CMOS_RVT_PM_CODE___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW2_LSB__CMOS_RVT_PM_CODE___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW2_LSB__NMOS_RVT_PM_CODE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW2_LSB__NMOS_RVT_PM_CODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW2_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW2_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW2_MSB (0x005CB064) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW2_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW2_MSB__CMOS_LVT_PM_CODE___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW2_MSB__CMOS_LVT_PM_CODE___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW2_MSB__NMOS_LVT_PM_CODE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW2_MSB__NMOS_LVT_PM_CODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW2_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW2_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW3_LSB (0x005CB068) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW3_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW3_LSB__CMOS_EG_PM_CODE___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW3_LSB__CMOS_EG_PM_CODE___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW3_LSB__NMOS_EG_PM_CODE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW3_LSB__NMOS_EG_PM_CODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW3_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW3_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW3_MSB (0x005CB06C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW3_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW3_MSB__CMOS_EGU_PM_CODE___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW3_MSB__CMOS_EGU_PM_CODE___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW3_MSB__NMOS_EGU_PM_CODE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW3_MSB__NMOS_EGU_PM_CODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW3_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW3_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW4_LSB (0x005CB070) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW4_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW4_LSB__QCCMOM_RF_6FF_CODE___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW4_LSB__QCCMOM_RF_6FF_CODE___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW4_LSB__QCCMOM_RF_3FF_CODE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW4_LSB__QCCMOM_RF_3FF_CODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW4_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW4_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW4_MSB (0x005CB074) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW4_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW4_MSB__QMOM_RCX_RF_PW_CODE___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW4_MSB__QMOM_RCX_RF_PW_CODE___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW4_MSB__QCCMOM_RF_12FF_CODE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW4_MSB__QCCMOM_RF_12FF_CODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW4_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW4_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_LSB (0x005CB078) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_LSB__QMOM_RCX_RF_M1_CODE___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_LSB__QMOM_RCX_RF_M1_CODE___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_LSB__QMOM_RCX_RF_BEOL_CODE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_LSB__QMOM_RCX_RF_BEOL_CODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB (0x005CB07C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B63___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B63___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B62___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B62___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B61___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B61___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B60___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B60___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B59___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B59___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B58___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B58___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B57___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B57___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B56___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B56___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RSVD_R15_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RERR___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB__RERR___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW5_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB (0x005CB080) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__RSVD_R16_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__ATE_TEMPSENSOR0_CODE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB__ATE_TEMPSENSOR0_CODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB (0x005CB084) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B63___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B63___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B62___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B62___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B61___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B61___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B60___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B60___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B59___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B59___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B58___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B58___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B57___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B57___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B56___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B56___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB__RSVD_R16_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW6_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB (0x005CB088) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__RSVD_R17_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__ATE_DVS_FLAG___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__ATE_DVS_FLAG___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__FOUNDRY_ID___M 0x003C0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__FOUNDRY_ID___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__HW_BOARD_ID___M 0x0003FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__HW_BOARD_ID___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__OTP_REVISION___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB__OTP_REVISION___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB (0x005CB08C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B63___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B63___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B62___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B62___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B61___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B61___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B60___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B60___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B59___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B59___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B58___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B58___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B57___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B57___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B56___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B56___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB__RSVD_R17_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_ATE_ROW7_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB (0x005CB090) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__RSVD_R18_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__CONST_PWD_DISABLE___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__CONST_PWD_DISABLE___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__UNIQUE_QA_PWD___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__UNIQUE_QA_PWD___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__QC_RTL_KEY_VERSION___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__QC_RTL_KEY_VERSION___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__QC_DEBUG_DISABLE_VECTOR___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB__QC_DEBUG_DISABLE_VECTOR___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB (0x005CB094) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__PKG_ID___M 0xFE000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__PKG_ID___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B56___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B56___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB__RSVD_R18_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_QC_SECURE_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB (0x005CB098) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB__RSVD_R19_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB (0x005CB09C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB__RSVD_R19_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW0_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB (0x005CB0A0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB__RSVD_R20_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB (0x005CB0A4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB__RSVD_R20_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW1_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB (0x005CB0A8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB__RSVD_R21_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB (0x005CB0AC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB__RSVD_R21_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW2_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB (0x005CB0B0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB__RSVD_R22_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB (0x005CB0B4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB__RSVD_R22_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW3_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB (0x005CB0B8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB__RSVD_R23_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB (0x005CB0BC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB__RSVD_R23_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW4_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW5_LSB (0x005CB0C0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW5_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW5_LSB__OEM_PK_HASH_M0_WORD0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW5_LSB__OEM_PK_HASH_M0_WORD0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW5_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW5_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW5_MSB (0x005CB0C4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW5_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW5_MSB__OEM_PK_HASH_M0_WORD1_23_0___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW5_MSB__OEM_PK_HASH_M0_WORD1_23_0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW5_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW5_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW6_LSB (0x005CB0C8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW6_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW6_LSB__OEM_PK_HASH_M0_WORD2_23_0___M 0xFFFFFF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW6_LSB__OEM_PK_HASH_M0_WORD2_23_0___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW6_LSB__OEM_PK_HASH_M0_WORD1_31_24___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW6_LSB__OEM_PK_HASH_M0_WORD1_31_24___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW6_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW6_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW6_MSB (0x005CB0CC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW6_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW6_MSB__OEM_PK_HASH_M0_WORD3_15_0___M 0x00FFFF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW6_MSB__OEM_PK_HASH_M0_WORD3_15_0___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW6_MSB__OEM_PK_HASH_M0_WORD2_31_24___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW6_MSB__OEM_PK_HASH_M0_WORD2_31_24___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW6_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW6_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW7_LSB (0x005CB0D0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW7_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW7_LSB__OEM_PK_HASH_M0_WORD4_15_0___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW7_LSB__OEM_PK_HASH_M0_WORD4_15_0___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW7_LSB__OEM_PK_HASH_M0_WORD3_31_16___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW7_LSB__OEM_PK_HASH_M0_WORD3_31_16___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW7_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW7_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW7_MSB (0x005CB0D4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW7_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW7_MSB__OEM_PK_HASH_M0_WORD5_7_0___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW7_MSB__OEM_PK_HASH_M0_WORD5_7_0___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW7_MSB__OEM_PK_HASH_M0_WORD4_31_16___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW7_MSB__OEM_PK_HASH_M0_WORD4_31_16___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW7_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW7_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW8_LSB (0x005CB0D8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW8_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW8_LSB__OEM_PK_HASH_M0_WORD6_7_0___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW8_LSB__OEM_PK_HASH_M0_WORD6_7_0___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW8_LSB__OEM_PK_HASH_M0_WORD5_31_8___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW8_LSB__OEM_PK_HASH_M0_WORD5_31_8___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW8_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW8_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW8_MSB (0x005CB0DC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW8_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW8_MSB__OEM_PK_HASH_M0_WORD6_31_8___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW8_MSB__OEM_PK_HASH_M0_WORD6_31_8___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW8_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW8_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_LSB (0x005CB0E0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_LSB__OEM_PK_HASH_M0_WORD7___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_LSB__OEM_PK_HASH_M0_WORD7___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB (0x005CB0E4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB__RSVD_R28_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_PK_HASH_ROW9_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB (0x005CB0E8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__SPARE_REGION_16_FEC_ENABLE___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__SPARE_REGION_16_FEC_ENABLE___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__SPARE_REGION_15_FEC_ENABLE___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__SPARE_REGION_15_FEC_ENABLE___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__OEM_WIP_FEC_ENABLE___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__OEM_WIP_FEC_ENABLE___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__OTP_PATCH_FEC_ENABLE___M 0x00003000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__OTP_PATCH_FEC_ENABLE___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__WIP_FEC_ENABLE___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__WIP_FEC_ENABLE___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__BT_FEC_ENABLE___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__BT_FEC_ENABLE___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__PMU_RFA_SEQUENCE_FEC_ENABLE___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__PMU_RFA_SEQUENCE_FEC_ENABLE___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__MEMORY_CONFIG_FEC_ENABLE___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__MEMORY_CONFIG_FEC_ENABLE___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__OEM_PK_HASH_FEC_ENABLE___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__OEM_PK_HASH_FEC_ENABLE___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB__RSVD_R29_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB (0x005CB0EC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B63___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B63___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B62___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B62___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B61___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B61___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B60___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B60___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B59___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B59___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B58___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B58___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B57___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B57___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B56___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B56___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB__RSVD_R29_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_FEC_CONTROL_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW0_LSB (0x005CB0F0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW0_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW0_LSB__FUSE_MEM_REDUN_WORD_31_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW0_LSB__FUSE_MEM_REDUN_WORD_31_0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW0_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW0_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW0_MSB (0x005CB0F4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW0_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW0_MSB__FUSE_MEM_REDUN_WORD_55_32___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW0_MSB__FUSE_MEM_REDUN_WORD_55_32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW0_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW0_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB (0x005CB0F8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__RSVD_R31_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__FUSE_MEM_REDUN_WORD_57_56___M 0x00000003 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB__FUSE_MEM_REDUN_WORD_57_56___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB (0x005CB0FC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB__RSVD_R31_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW1_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW2_LSB (0x005CB100) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW2_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW2_LSB__BTFM_FUSE_COMPILERMEM_ACC_WORD_31_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW2_LSB__BTFM_FUSE_COMPILERMEM_ACC_WORD_31_0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW2_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW2_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW2_MSB (0x005CB104) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW2_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW2_MSB__BTFM_FUSE_COMPILERMEM_ACC_WORD_55_32___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW2_MSB__BTFM_FUSE_COMPILERMEM_ACC_WORD_55_32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW2_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW2_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB (0x005CB108) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__RSVD_R33_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__BTFM_FUSE_CUSTOMMEM_ACC___M 0x00FFFF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__BTFM_FUSE_CUSTOMMEM_ACC___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__BTFM_FUSE_COMPILERMEM_ACC_WORD_63_56___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB__BTFM_FUSE_COMPILERMEM_ACC_WORD_63_56___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB (0x005CB10C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB__RSVD_R33_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_MEMORY_CONFIG_ROW3_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_LSB (0x005CB110) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_LSB__PMU_SEQUENCE_2_HFRC_TRIM_3_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_LSB__PMU_SEQUENCE_2_HFRC_TRIM_3_0___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_LSB__PMU_SEQUENCE_1_LFRC_TRIM___M 0x0FFFC000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_LSB__PMU_SEQUENCE_1_LFRC_TRIM___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_LSB__PMU_SEQUENCE_0_LPO2M_TRIM___M 0x00003FFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_LSB__PMU_SEQUENCE_0_LPO2M_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_MSB (0x005CB114) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_MSB__PMU_SEQUENCE_3_LDO_AO_NOM_TRIM___M 0x00FFFC00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_MSB__PMU_SEQUENCE_3_LDO_AO_NOM_TRIM___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_MSB__PMU_SEQUENCE_2_HFRC_TRIM_13_4___M 0x000003FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_MSB__PMU_SEQUENCE_2_HFRC_TRIM_13_4___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW0_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_LSB (0x005CB118) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_LSB__PMU_SEQUENCE_6_LDO_AO_LOWSVS_TRIM_3_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_LSB__PMU_SEQUENCE_6_LDO_AO_LOWSVS_TRIM_3_0___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_LSB__PMU_SEQUENCE_5_LDO_AO_SVS_TRIM___M 0x0FFFC000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_LSB__PMU_SEQUENCE_5_LDO_AO_SVS_TRIM___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_LSB__PMU_SEQUENCE_4_LDO_AO_RET_TRIM___M 0x00003FFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_LSB__PMU_SEQUENCE_4_LDO_AO_RET_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_MSB (0x005CB11C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_MSB__PMU_SEQUENCE_7_LDO_BTCMX_NOM_TRIM___M 0x00FFFC00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_MSB__PMU_SEQUENCE_7_LDO_BTCMX_NOM_TRIM___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_MSB__PMU_SEQUENCE_6_LDO_AO_LOWSVS_TRIM_13_4___M 0x000003FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_MSB__PMU_SEQUENCE_6_LDO_AO_LOWSVS_TRIM_13_4___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW1_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_LSB (0x005CB120) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_LSB__PMU_SEQUENCE_10_LDO_WLCX_RET_TRIM_3_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_LSB__PMU_SEQUENCE_10_LDO_WLCX_RET_TRIM_3_0___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_LSB__PMU_SEQUENCE_9_LDO_WLCX_NOM_TRIM___M 0x0FFFC000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_LSB__PMU_SEQUENCE_9_LDO_WLCX_NOM_TRIM___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_LSB__PMU_SEQUENCE_8_LDO_BTCMX_RET_TRIM___M 0x00003FFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_LSB__PMU_SEQUENCE_8_LDO_BTCMX_RET_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_MSB (0x005CB124) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_MSB__PMU_SEQUENCE_11_LDO_WLCX_SVS_TRIM___M 0x00FFFC00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_MSB__PMU_SEQUENCE_11_LDO_WLCX_SVS_TRIM___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_MSB__PMU_SEQUENCE_10_LDO_WLCX_RET_TRIM_13_4___M 0x000003FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_MSB__PMU_SEQUENCE_10_LDO_WLCX_RET_TRIM_13_4___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW2_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_LSB (0x005CB128) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_LSB__PMU_SEQUENCE_14_LDO_WLMX_RET_TRIM_3_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_LSB__PMU_SEQUENCE_14_LDO_WLMX_RET_TRIM_3_0___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_LSB__PMU_SEQUENCE_13_LDO_WLMX_NOM_TRIM___M 0x0FFFC000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_LSB__PMU_SEQUENCE_13_LDO_WLMX_NOM_TRIM___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_LSB__PMU_SEQUENCE_12_LDO_WLCX_L1_TRIM___M 0x00003FFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_LSB__PMU_SEQUENCE_12_LDO_WLCX_L1_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_MSB (0x005CB12C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_MSB__PMU_SEQUENCE_15_LDO_WLMX_SVS_TRIM___M 0x00FFFC00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_MSB__PMU_SEQUENCE_15_LDO_WLMX_SVS_TRIM___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_MSB__PMU_SEQUENCE_14_LDO_WLMX_RET_TRIM_13_4___M 0x000003FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_MSB__PMU_SEQUENCE_14_LDO_WLMX_RET_TRIM_13_4___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW3_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_LSB (0x005CB130) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_LSB__PMU_SEQUENCE_18_LDO_RFACMN_NOM_TRIM_3_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_LSB__PMU_SEQUENCE_18_LDO_RFACMN_NOM_TRIM_3_0___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_LSB__PMU_SEQUENCE_17_LDO_WLMX_L1_TRIM___M 0x0FFFC000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_LSB__PMU_SEQUENCE_17_LDO_WLMX_L1_TRIM___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_LSB__PMU_SEQUENCE_16_LDO_WLMX_LOWSVS_TRIM___M 0x00003FFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_LSB__PMU_SEQUENCE_16_LDO_WLMX_LOWSVS_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_MSB (0x005CB134) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_MSB__PMU_SEQUENCE_19_LDO_RFACMN_RET_TRIM___M 0x00FFFC00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_MSB__PMU_SEQUENCE_19_LDO_RFACMN_RET_TRIM___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_MSB__PMU_SEQUENCE_18_LDO_RFACMN_NOM_TRIM_13_4___M 0x000003FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_MSB__PMU_SEQUENCE_18_LDO_RFACMN_NOM_TRIM_13_4___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW4_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_LSB (0x005CB138) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_LSB__PMU_SEQUENCE_22_LDO_RFA1P2_NOM_TRIM_3_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_LSB__PMU_SEQUENCE_22_LDO_RFA1P2_NOM_TRIM_3_0___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_LSB__PMU_SEQUENCE_21_LDO_AO_NOM_TRIM_095___M 0x0FFFC000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_LSB__PMU_SEQUENCE_21_LDO_AO_NOM_TRIM_095___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_LSB__PMU_SEQUENCE_20_LDO_RFA0P8_NOM_TRIM___M 0x00003FFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_LSB__PMU_SEQUENCE_20_LDO_RFA0P8_NOM_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_MSB (0x005CB13C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_MSB__PMU_SEQUENCE_23_LDO_AO_SVS_TRM_095___M 0x00FFFC00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_MSB__PMU_SEQUENCE_23_LDO_AO_SVS_TRM_095___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_MSB__PMU_SEQUENCE_22_LDO_RFA1P2_NOM_TRIM_13_4___M 0x000003FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_MSB__PMU_SEQUENCE_22_LDO_RFA1P2_NOM_TRIM_13_4___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW5_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_LSB (0x005CB140) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_LSB__PMU_SEQUENCE_26_LDO_RFA1P7_NOM_TRIM_3_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_LSB__PMU_SEQUENCE_26_LDO_RFA1P7_NOM_TRIM_3_0___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_LSB__PMU_SEQUENCE_25_LDO_PCIE0P9_RET_TRIM___M 0x0FFFC000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_LSB__PMU_SEQUENCE_25_LDO_PCIE0P9_RET_TRIM___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_LSB__PMU_SEQUENCE_24_LDO_PCIE0P9_NOM_TRIM___M 0x00003FFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_LSB__PMU_SEQUENCE_24_LDO_PCIE0P9_NOM_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_MSB (0x005CB144) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_MSB__PMU_SEQUENCE_27_LDO_AO_LOWSVS_TRIM_095___M 0x00FFFC00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_MSB__PMU_SEQUENCE_27_LDO_AO_LOWSVS_TRIM_095___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_MSB__PMU_SEQUENCE_26_LDO_RFA1P7_NOM_TRIM_13_4___M 0x000003FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_MSB__PMU_SEQUENCE_26_LDO_RFA1P7_NOM_TRIM_13_4___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW6_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_LSB (0x005CB148) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_LSB__PMU_SEQUENCE_30_LDO_RFACMN_NOM_TRIM_095_3_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_LSB__PMU_SEQUENCE_30_LDO_RFACMN_NOM_TRIM_095_3_0___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_LSB__PMU_SEQUENCE_29_LDO_PCIE1P8_RET_TRIM___M 0x0FFFC000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_LSB__PMU_SEQUENCE_29_LDO_PCIE1P8_RET_TRIM___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_LSB__PMU_SEQUENCE_28_LDO_PCIE1P8_NOM_TRIM___M 0x00003FFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_LSB__PMU_SEQUENCE_28_LDO_PCIE1P8_NOM_TRIM___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_MSB (0x005CB14C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_MSB__PMU_SEQUENCE_31_LDO_RFACMN_RET_TRIM_095___M 0x00FFFC00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_MSB__PMU_SEQUENCE_31_LDO_RFACMN_RET_TRIM_095___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_MSB__PMU_SEQUENCE_30_LDO_RFACMN_NOM_TRIM_095_13_4___M 0x000003FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_MSB__PMU_SEQUENCE_30_LDO_RFACMN_NOM_TRIM_095_13_4___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW7_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB (0x005CB150) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__TOP_BGU_PTAT_CODE___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__TOP_BGU_PTAT_CODE___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__TOP_BGT_ICTRL___M 0x00C00000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__TOP_BGT_ICTRL___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__TOP_BGU_CTATN_CODE___M 0x003F0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__TOP_BGU_CTATN_CODE___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__RSVD_R42_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__RSVD_R42_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__APPLY_BG_PARAM___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__APPLY_BG_PARAM___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__TOP_BGU_CTATP_CODE___M 0x00003F00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__TOP_BGU_CTATP_CODE___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__RSVD_R42_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__RSVD_R42_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__APPLY_CLK_SEL_PARAM___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__APPLY_CLK_SEL_PARAM___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__CLK_OUT_FREQ_SEL___M 0x00000030 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__CLK_OUT_FREQ_SEL___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__CLK_SEL___M 0x0000000E +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__CLK_SEL___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__TCXO_MODE___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB__TCXO_MODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_MSB (0x005CB154) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_BGT_PTAT_CODE___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_BGT_PTAT_CODE___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_BGU_ICTRL___M 0x0000C000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_BGU_ICTRL___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_BGT_CTATN_CODE___M 0x00003F00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_BGT_CTATN_CODE___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_PTT_ICTRL___M 0x000000C0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_PTT_ICTRL___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_BGT_CTATP_CODE___M 0x0000003F +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_MSB__TOP_BGT_CTATP_CODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW8_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_LSB (0x005CB158) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_LSB__XO_SLOPE_TRIM___M 0xF0000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_LSB__XO_SLOPE_TRIM___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_LSB__APPLY_XO_PARAM___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_LSB__APPLY_XO_PARAM___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_LSB__XO_CDACOUT___M 0x07FC0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_LSB__XO_CDACOUT___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_LSB__XO_CDACIN___M 0x0003FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_LSB__XO_CDACIN___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_LSB__TOP_PTT_RCODE___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_LSB__TOP_PTT_RCODE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB (0x005CB15C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__XO_DCC_VAR_DEL_96M___M 0x00E00000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__XO_DCC_VAR_DEL_96M___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__XO_DCC_VAR_DEL___M 0x001C0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__XO_DCC_VAR_DEL___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__XO_FLTRBWSW___M 0x00030000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__XO_FLTRBWSW___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__RSVD_R43_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__RSVD_R43_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__XO_GM_TRIM___M 0x00007000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__XO_GM_TRIM___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__XO_BUF_N___M 0x00000F00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__XO_BUF_N___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__XO_DBLR_SEL_EDGE___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__XO_DBLR_SEL_EDGE___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__XO_BIAS_TRIM___M 0x00000070 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__XO_BIAS_TRIM___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__XO_BUF_P___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB__XO_BUF_P___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW9_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB (0x005CB160) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__LDO_WL_SYNTH2_SDM_VREF___M 0xF0000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__LDO_WL_SYNTH2_SDM_VREF___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__OTP_APPLY_LDO_PARAM___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__OTP_APPLY_LDO_PARAM___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__XO_VREF_VSEL___M 0x07000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__XO_VREF_VSEL___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__XO_VREF_BWSEL___M 0x00C00000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__XO_VREF_BWSEL___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__XO_LDO08_ICTRL___M 0x00380000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__XO_LDO08_ICTRL___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__XO_LDO13_ICTRL___M 0x00070000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__XO_LDO13_ICTRL___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__XO_LDO08_VSEL___M 0x0000F000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__XO_LDO08_VSEL___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__XO_LDO13_VSEL___M 0x00000F00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__XO_LDO13_VSEL___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__RSVD_R44_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__RSVD_R44_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__APPLY_DLL_PARAM___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__APPLY_DLL_PARAM___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__DLL_DIFF_EN_DIS___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__DLL_DIFF_EN_DIS___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__DLL_CLK_MUX_SEL___M 0x0000001C +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__DLL_CLK_MUX_SEL___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__DLL_CLK_DRV___M 0x00000003 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB__DLL_CLK_DRV___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_MSB (0x005CB164) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_MSB__LDO2_BT_DPLL_VREF___M 0x00F00000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_MSB__LDO2_BT_DPLL_VREF___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_MSB__LDO1_BT_DPLL_VREF___M 0x000F0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_MSB__LDO1_BT_DPLL_VREF___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_MSB__LDO0_BT_DPLL_VREF___M 0x0000F000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_MSB__LDO0_BT_DPLL_VREF___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_MSB__LDO2_WL_DPLL_VREF___M 0x00000F00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_MSB__LDO2_WL_DPLL_VREF___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_MSB__LDO1_WL_DPLL_VREF___M 0x000000F0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_MSB__LDO1_WL_DPLL_VREF___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_MSB__LDO0_WL_DPLL_VREF___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_MSB__LDO0_WL_DPLL_VREF___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW10_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB (0x005CB168) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_TXLO_VREF_5G_CH1___M 0xF0000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_TXLO_VREF_5G_CH1___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_TXLO_VREF_2G_CH1___M 0x0F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_TXLO_VREF_2G_CH1___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_TXLO_VREF_5G_CH0___M 0x00F00000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_TXLO_VREF_5G_CH0___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_TXLO_VREF_2G_CH0___M 0x000F0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_TXLO_VREF_2G_CH0___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_RXLO_VREF_5G_CH1___M 0x0000F000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_RXLO_VREF_5G_CH1___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_RXLO_VREF_2G_CH1___M 0x00000F00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_RXLO_VREF_2G_CH1___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_RXLO_VREF_5G_CH0___M 0x000000F0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_RXLO_VREF_5G_CH0___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_RXLO_VREF_2G_CH0___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB__LDO_WL_RXLO_VREF_2G_CH0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_MSB (0x005CB16C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_SYNTH0_LOGEN_VREF___M 0x00F00000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_SYNTH0_LOGEN_VREF___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_BT_TXLO_VREF___M 0x000F0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_BT_TXLO_VREF___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_DAC_VREF_5G_CH1___M 0x0000F000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_DAC_VREF_5G_CH1___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_DAC_VREF_2G_CH1___M 0x00000F00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_DAC_VREF_2G_CH1___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_DAC_VREF_5G_CH0___M 0x000000F0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_DAC_VREF_5G_CH0___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_DAC_VREF_2G_CH0___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_MSB__LDO_WL_DAC_VREF_2G_CH0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW11_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB (0x005CB170) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_ADC_VREF_5G_CH1___M 0x38000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_ADC_VREF_5G_CH1___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_ADC_VREF_2G_CH1___M 0x07000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_ADC_VREF_2G_CH1___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_ADC_VREF_5G_CH0___M 0x00380000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_ADC_VREF_5G_CH0___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_ADC_VREF_2G_CH0___M 0x00070000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_ADC_VREF_2G_CH0___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_SYNTH2_VREF___M 0x00003800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_SYNTH2_VREF___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_SYNTH1_VREF___M 0x00000700 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_SYNTH1_VREF___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__RSVD_R46_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_SYNTH0_VREF___M 0x00000070 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_SYNTH0_VREF___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_SYNTH1_LOGEN_VREF___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB__LDO_WL_SYNTH1_LOGEN_VREF___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB (0x005CB174) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD_R46_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD_R46_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD_R46_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD_R46_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__APPLY_BOOTUP_PARAM___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__APPLY_BOOTUP_PARAM___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__TOP_BIAS_SETTLE_TIME___M 0x001C0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__TOP_BIAS_SETTLE_TIME___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__TOP_FC_WIDTH___M 0x00030000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__TOP_FC_WIDTH___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__TOP_STARTUP_WIDTH___M 0x0000C000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__TOP_STARTUP_WIDTH___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__SETTIME_TOP_FC___M 0x00003000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__SETTIME_TOP_FC___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__SETTIME_TOP_STARTUP___M 0x00000C00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__SETTIME_TOP_STARTUP___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__SETTIME_BGT_EN___M 0x00000300 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__SETTIME_BGT_EN___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD_R46_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD_R46_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD_R46_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__RSVD_R46_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__LDO_BT_SYNTH_LOLDO_VREF06___M 0x00000038 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__LDO_BT_SYNTH_LOLDO_VREF06___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__LDO_BT_SYNTH_REFGEN_VREF___M 0x00000007 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB__LDO_BT_SYNTH_REFGEN_VREF___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW12_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB (0x005CB178) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__WL_LDO_SETTLE_TIME___M 0xF0000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__WL_LDO_SETTLE_TIME___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__XO_LDO_SETTLE_TIME___M 0x0F000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__XO_LDO_SETTLE_TIME___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__XO_SETTLE_TIME___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__XO_SETTLE_TIME___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__DBLR_SETTLE_TIME___M 0x00007F00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__DBLR_SETTLE_TIME___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__RSVD_R47_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__TCXO_SETTLE_TIME___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB__TCXO_SETTLE_TIME___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_MSB (0x005CB17C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_MSB__BTFMPLL_SETTLE_TIME___M 0x00F00000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_MSB__BTFMPLL_SETTLE_TIME___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_MSB__BBPLL_SETTLE_TIME___M 0x000F0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_MSB__BBPLL_SETTLE_TIME___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_MSB__BTFMPLL_LDO_SETTLE_TIME___M 0x0000F000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_MSB__BTFMPLL_LDO_SETTLE_TIME___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_MSB__BBPLL_LDO_SETTLE_TIME___M 0x00000F00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_MSB__BBPLL_LDO_SETTLE_TIME___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_MSB__CM_LDO_SETTLE_TIME___M 0x000000F0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_MSB__CM_LDO_SETTLE_TIME___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_MSB__BT_LDO_SETTLE_TIME___M 0x0000000F +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_MSB__BT_LDO_SETTLE_TIME___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW13_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_LSB (0x005CB180) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_LSB__XO_SETTLE_TIME_CUSTOM___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_LSB__XO_SETTLE_TIME_CUSTOM___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_LSB__TCXO_SETTLE_TIME_CUSTOM___M 0x00F00000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_LSB__TCXO_SETTLE_TIME_CUSTOM___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_LSB__XO_CAP_CUSTOM_OVERWRITE___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_LSB__XO_CAP_CUSTOM_OVERWRITE___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_LSB__XO_CDACOUT_CUSTOM___M 0x0007FC00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_LSB__XO_CDACOUT_CUSTOM___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_LSB__XO_CDACIN_CUSTOM___M 0x000003FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_LSB__XO_CDACIN_CUSTOM___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB (0x005CB184) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__RSVD_R48_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__XO_SETTLE_CUSTOM_OVERWRITE___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB__XO_SETTLE_CUSTOM_OVERWRITE___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_PMU_RFA_SEQUENCE_ROW14_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_LSB (0x005CB188) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_LSB__OTP_MAGIC_NUMBER___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_LSB__OTP_MAGIC_NUMBER___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB (0x005CB18C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__BTUARTBAUD___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__BTUARTBAUD___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__RSVD_39_47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__RSVD_39_47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__RADIO_DISABLE___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__RADIO_DISABLE___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__LC_DISABLE___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__LC_DISABLE___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__COEX_MCI_EN___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__COEX_MCI_EN___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__DISABLE_DEBUG_VSC___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__DISABLE_DEBUG_VSC___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__DISABLE_DEBUG_SSR___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__DISABLE_DEBUG_SSR___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__EXT_NVM___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__EXT_NVM___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__EXT_DSET___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__EXT_DSET___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__HID_OFFLOAD___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__HID_OFFLOAD___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__HOGP_OFFLOAD___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__HOGP_OFFLOAD___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__F64M___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__F64M___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__EDL_OVR_DBGUART___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__EDL_OVR_DBGUART___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__AUTOBAUD___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__AUTOBAUD___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__PHY_MODE___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__PHY_MODE___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__EMULATION_MODE___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__EMULATION_MODE___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__RSVD_R49_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB__RSVD_R49_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW0_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW1_LSB (0x005CB190) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW1_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW1_LSB__PRIMARY_BD_ADDRESS_LOW___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW1_LSB__PRIMARY_BD_ADDRESS_LOW___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW1_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW1_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW1_MSB (0x005CB194) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW1_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW1_MSB__RFKILL___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW1_MSB__RFKILL___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW1_MSB__PRIMARY_BD_ADDRESS_HIGH___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW1_MSB__PRIMARY_BD_ADDRESS_HIGH___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW1_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW1_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW2_LSB (0x005CB198) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW2_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW2_LSB__SIDESWITCHDISABLEDELAY___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW2_LSB__SIDESWITCHDISABLEDELAY___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW2_LSB__SIDESWITCHENABLEDELAY___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW2_LSB__SIDESWITCHENABLEDELAY___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW2_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW2_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW2_MSB (0x005CB19C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW2_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW2_MSB__OTP_REG_PRGM_END_ADDR___M 0x00FFFF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW2_MSB__OTP_REG_PRGM_END_ADDR___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW2_MSB__OTP_REG_PRGM_LEN___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW2_MSB__OTP_REG_PRGM_LEN___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW2_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW2_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB (0x005CB1A0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RBIAS_ICON_CODE___M 0x000000FC +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RBIAS_ICON_CODE___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__RSVD_R52_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__SHA256_HW_SW___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB__SHA256_HW_SW___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB (0x005CB1A4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB__RSVD_R52_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW3_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW4_LSB (0x005CB1A8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW4_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW4_LSB__BT_OTP_PATCH_RSVD0_31_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW4_LSB__BT_OTP_PATCH_RSVD0_31_0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW4_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW4_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW4_MSB (0x005CB1AC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW4_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW4_MSB__BT_OTP_PATCH_RSVD0_55_32___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW4_MSB__BT_OTP_PATCH_RSVD0_55_32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW4_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW4_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW5_LSB (0x005CB1B0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW5_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW5_LSB__BT_OTP_PATCH_RSVD1_31_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW5_LSB__BT_OTP_PATCH_RSVD1_31_0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW5_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW5_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW5_MSB (0x005CB1B4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW5_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW5_MSB__BT_OTP_PATCH_RSVD1_55_32___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW5_MSB__BT_OTP_PATCH_RSVD1_55_32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW5_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW5_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_LSB (0x005CB1B8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_LSB__GPIO_PIN_SET_BLK0_7_0___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_LSB__GPIO_PIN_SET_BLK0_7_0___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_LSB__RSVD_R55_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_LSB__RSVD_R55_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_LSB__RSVD_R55_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_LSB__RSVD_R55_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_LSB__RSVD_R55_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_LSB__RSVD_R55_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_LSB__RSVD_R55_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_LSB__RSVD_R55_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_LSB__GPIO_ENABLE_FLAG___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_LSB__GPIO_ENABLE_FLAG___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_MSB (0x005CB1BC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_MSB__GPIO_PIN_SET_BLK1___M 0x00FFFF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_MSB__GPIO_PIN_SET_BLK1___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_MSB__GPIO_PIN_SET_BLK0_15_8___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_MSB__GPIO_PIN_SET_BLK0_15_8___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW6_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW7_LSB (0x005CB1C0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW7_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW7_LSB__GPIO_PIN_SET_BLK3___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW7_LSB__GPIO_PIN_SET_BLK3___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW7_LSB__GPIO_PIN_SET_BLK2___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW7_LSB__GPIO_PIN_SET_BLK2___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW7_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW7_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW7_MSB (0x005CB1C4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW7_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW7_MSB__GPIO_PIN_SET_BLK5_7_0___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW7_MSB__GPIO_PIN_SET_BLK5_7_0___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW7_MSB__GPIO_PIN_SET_BLK4___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW7_MSB__GPIO_PIN_SET_BLK4___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW7_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW7_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_LSB (0x005CB1C8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_LSB__GPIO_PIN_SET_BLK7_7_0___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_LSB__GPIO_PIN_SET_BLK7_7_0___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_LSB__GPIO_PIN_SET_BLK6___M 0x00FFFF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_LSB__GPIO_PIN_SET_BLK6___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_LSB__GPIO_PIN_SET_BLK5_15_8___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_LSB__GPIO_PIN_SET_BLK5_15_8___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_MSB (0x005CB1CC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_MSB__GPIO_PIN_SET_BLK8___M 0x00FFFF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_MSB__GPIO_PIN_SET_BLK8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_MSB__GPIO_PIN_SET_BLK7_15_8___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_MSB__GPIO_PIN_SET_BLK7_15_8___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW8_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW9_LSB (0x005CB1D0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW9_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW9_LSB__GPIO_PIN_SET_BLK10___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW9_LSB__GPIO_PIN_SET_BLK10___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW9_LSB__GPIO_PIN_SET_BLK9___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW9_LSB__GPIO_PIN_SET_BLK9___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW9_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW9_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW9_MSB (0x005CB1D4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW9_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW9_MSB__GPIO_PIN_SET_BLK12_OR_GPIO_CFG_TBL10_7_0___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW9_MSB__GPIO_PIN_SET_BLK12_OR_GPIO_CFG_TBL10_7_0___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW9_MSB__GPIO_PIN_SET_BLK11___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW9_MSB__GPIO_PIN_SET_BLK11___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW9_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW9_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_LSB (0x005CB1D8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_LSB__GPIO_PIN_SET_BLK14_OR_GPIO_CFG_TBL8_7_0___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_LSB__GPIO_PIN_SET_BLK14_OR_GPIO_CFG_TBL8_7_0___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_LSB__GPIO_PIN_SET_BLK13_OR_GPIO_CFG_TBL9___M 0x00FFFF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_LSB__GPIO_PIN_SET_BLK13_OR_GPIO_CFG_TBL9___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_LSB__GPIO_PIN_SET_BLK12_OR_GPIO_CFG_TBL10_15_8___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_LSB__GPIO_PIN_SET_BLK12_OR_GPIO_CFG_TBL10_15_8___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_MSB (0x005CB1DC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_MSB__GPIO_PIN_SET_BLK15_OR_GPIO_CFG_TBL7___M 0x00FFFF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_MSB__GPIO_PIN_SET_BLK15_OR_GPIO_CFG_TBL7___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_MSB__GPIO_PIN_SET_BLK14_OR_GPIO_CFG_TBL8_15_8___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_MSB__GPIO_PIN_SET_BLK14_OR_GPIO_CFG_TBL8_15_8___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW10_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW11_LSB (0x005CB1E0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW11_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW11_LSB__GPIO_PIN_SET_BLK17_OR_GPIO_CFG_TBL5___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW11_LSB__GPIO_PIN_SET_BLK17_OR_GPIO_CFG_TBL5___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW11_LSB__GPIO_PIN_SET_BLK16_OR_GPIO_CFG_TBL6___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW11_LSB__GPIO_PIN_SET_BLK16_OR_GPIO_CFG_TBL6___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW11_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW11_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW11_MSB (0x005CB1E4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW11_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW11_MSB__GPIO_PIN_SET_BLK19_OR_GPIO_CFG_TBL3_7_0___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW11_MSB__GPIO_PIN_SET_BLK19_OR_GPIO_CFG_TBL3_7_0___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW11_MSB__GPIO_PIN_SET_BLK18_OR_GPIO_CFG_TBL4___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW11_MSB__GPIO_PIN_SET_BLK18_OR_GPIO_CFG_TBL4___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW11_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW11_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_LSB (0x005CB1E8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_LSB__GPIO_CFG_TBL1_7_0___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_LSB__GPIO_CFG_TBL1_7_0___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_LSB__GPIO_CFG_TBL2___M 0x00FFFF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_LSB__GPIO_CFG_TBL2___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_LSB__GPIO_PIN_SET_BLK19_OR_GPIO_CFG_TBL3_15_8___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_LSB__GPIO_PIN_SET_BLK19_OR_GPIO_CFG_TBL3_15_8___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_MSB (0x005CB1EC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_MSB__GPIO_CFG_TBL0___M 0x00FFFF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_MSB__GPIO_CFG_TBL0___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_MSB__GPIO_CFG_TBL1_15_8___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_MSB__GPIO_CFG_TBL1_15_8___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW12_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB (0x005CB1F0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__RSVD_R62_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__RSVD_R62_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__RSVD_R62_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__RSVD_R62_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_REFDIV_96M___M 0x30000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_REFDIV_96M___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_OUTDIV_96M___M 0x0C000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_OUTDIV_96M___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_KD_96M___M 0x03C00000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_KD_96M___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_KI_96M___M 0x00300000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_KI_96M___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_REFDIV_48M___M 0x000C0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_REFDIV_48M___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_OUTDIV_48M___M 0x00030000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_OUTDIV_48M___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_KD_48M___M 0x0000F000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_KD_48M___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_KI_48M___M 0x00000C00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_KI_48M___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_REFDIV_38M___M 0x00000300 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_REFDIV_38M___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_OUTDIV_38M___M 0x000000C0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_OUTDIV_38M___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_KD_38M___M 0x0000003C +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_KD_38M___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_KI_38M___M 0x00000003 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB__BTFMPLL_KI_38M___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB (0x005CB1F4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__RSVD_R62_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__BT_FEATURE_CONTROL___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB__BT_FEATURE_CONTROL___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_BT_ROW13_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB (0x005CB1F8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB__RSVD_R63_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB (0x005CB1FC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB__RSVD_R63_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW0_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB (0x005CB200) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB__RSVD_R64_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB (0x005CB204) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB__RSVD_R64_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW1_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB (0x005CB208) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB__RSVD_R65_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB (0x005CB20C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB__RSVD_R65_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW2_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB (0x005CB210) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB__RSVD_R66_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB (0x005CB214) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB__RSVD_R66_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW3_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB (0x005CB218) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB__RSVD_R67_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB (0x005CB21C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB__RSVD_R67_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW4_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB (0x005CB220) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB__RSVD_R68_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB (0x005CB224) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB__RSVD_R68_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW5_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB (0x005CB228) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB__RSVD_R69_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB (0x005CB22C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB__RSVD_R69_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW6_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB (0x005CB230) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB__RSVD_R70_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB (0x005CB234) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB__RSVD_R70_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW7_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB (0x005CB238) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB__RSVD_R71_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB (0x005CB23C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB__RSVD_R71_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW8_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB (0x005CB240) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB__RSVD_R72_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB (0x005CB244) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB__RSVD_R72_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW9_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB (0x005CB248) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB__RSVD_R73_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB (0x005CB24C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB__RSVD_R73_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW10_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB (0x005CB250) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB__RSVD_R74_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB (0x005CB254) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB__RSVD_R74_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_WIP_ROW11_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW0_LSB (0x005CB258) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW0_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW0_LSB__OTP_PATCH_31_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW0_LSB__OTP_PATCH_31_0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW0_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW0_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW0_MSB (0x005CB25C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW0_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW0_MSB__OTP_PATCH_55_32___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW0_MSB__OTP_PATCH_55_32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW0_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW0_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW1_LSB (0x005CB260) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW1_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW1_LSB__OTP_PATCH_87_56___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW1_LSB__OTP_PATCH_87_56___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW1_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW1_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW1_MSB (0x005CB264) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW1_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW1_MSB__OTP_PATCH_111_88___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW1_MSB__OTP_PATCH_111_88___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW1_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW1_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW2_LSB (0x005CB268) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW2_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW2_LSB__OTP_PATCH_143_112___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW2_LSB__OTP_PATCH_143_112___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW2_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW2_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW2_MSB (0x005CB26C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW2_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW2_MSB__OTP_PATCH_167_144___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW2_MSB__OTP_PATCH_167_144___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW2_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW2_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW3_LSB (0x005CB270) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW3_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW3_LSB__OTP_PATCH_199_168___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW3_LSB__OTP_PATCH_199_168___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW3_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW3_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW3_MSB (0x005CB274) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW3_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW3_MSB__OTP_PATCH_223_200___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW3_MSB__OTP_PATCH_223_200___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW3_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW3_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW4_LSB (0x005CB278) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW4_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW4_LSB__OTP_PATCH_255_224___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW4_LSB__OTP_PATCH_255_224___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW4_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW4_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW4_MSB (0x005CB27C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW4_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW4_MSB__OTP_PATCH_279_256___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW4_MSB__OTP_PATCH_279_256___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW4_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW4_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW5_LSB (0x005CB280) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW5_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW5_LSB__OTP_PATCH_311_280___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW5_LSB__OTP_PATCH_311_280___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW5_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW5_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW5_MSB (0x005CB284) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW5_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW5_MSB__OTP_PATCH_335_312___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW5_MSB__OTP_PATCH_335_312___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW5_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW5_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW6_LSB (0x005CB288) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW6_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW6_LSB__OTP_PATCH_367_336___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW6_LSB__OTP_PATCH_367_336___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW6_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW6_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW6_MSB (0x005CB28C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW6_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW6_MSB__OTP_PATCH_391_368___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW6_MSB__OTP_PATCH_391_368___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW6_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW6_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW7_LSB (0x005CB290) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW7_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW7_LSB__OTP_PATCH_423_392___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW7_LSB__OTP_PATCH_423_392___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW7_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW7_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW7_MSB (0x005CB294) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW7_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW7_MSB__OTP_PATCH_447_424___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW7_MSB__OTP_PATCH_447_424___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW7_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW7_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW8_LSB (0x005CB298) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW8_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW8_LSB__OTP_PATCH_479_448___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW8_LSB__OTP_PATCH_479_448___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW8_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW8_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW8_MSB (0x005CB29C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW8_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW8_MSB__OTP_PATCH_503_480___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW8_MSB__OTP_PATCH_503_480___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW8_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW8_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW9_LSB (0x005CB2A0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW9_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW9_LSB__OTP_PATCH_535_504___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW9_LSB__OTP_PATCH_535_504___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW9_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW9_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW9_MSB (0x005CB2A4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW9_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW9_MSB__OTP_PATCH_559_536___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW9_MSB__OTP_PATCH_559_536___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW9_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW9_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW10_LSB (0x005CB2A8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW10_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW10_LSB__OTP_PATCH_591_560___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW10_LSB__OTP_PATCH_591_560___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW10_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW10_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW10_MSB (0x005CB2AC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW10_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW10_MSB__OTP_PATCH_615_592___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW10_MSB__OTP_PATCH_615_592___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW10_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW10_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW11_LSB (0x005CB2B0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW11_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW11_LSB__OTP_PATCH_647_616___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW11_LSB__OTP_PATCH_647_616___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW11_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW11_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW11_MSB (0x005CB2B4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW11_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW11_MSB__OTP_PATCH_671_648___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW11_MSB__OTP_PATCH_671_648___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW11_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW11_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW12_LSB (0x005CB2B8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW12_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW12_LSB__OTP_PATCH_703_672___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW12_LSB__OTP_PATCH_703_672___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW12_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW12_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW12_MSB (0x005CB2BC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW12_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW12_MSB__OTP_PATCH_727_704___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW12_MSB__OTP_PATCH_727_704___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW12_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW12_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW13_LSB (0x005CB2C0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW13_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW13_LSB__OTP_PATCH_759_728___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW13_LSB__OTP_PATCH_759_728___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW13_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW13_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW13_MSB (0x005CB2C4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW13_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW13_MSB__OTP_PATCH_783_760___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW13_MSB__OTP_PATCH_783_760___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW13_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW13_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW14_LSB (0x005CB2C8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW14_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW14_LSB__OTP_PATCH_815_784___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW14_LSB__OTP_PATCH_815_784___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW14_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW14_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW14_MSB (0x005CB2CC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW14_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW14_MSB__OTP_PATCH_839_816___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW14_MSB__OTP_PATCH_839_816___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW14_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW14_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW15_LSB (0x005CB2D0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW15_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW15_LSB__OTP_PATCH_871_840___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW15_LSB__OTP_PATCH_871_840___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW15_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW15_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW15_MSB (0x005CB2D4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW15_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW15_MSB__OTP_PATCH_895_872___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW15_MSB__OTP_PATCH_895_872___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW15_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW15_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW16_LSB (0x005CB2D8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW16_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW16_LSB__OTP_PATCH_927_896___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW16_LSB__OTP_PATCH_927_896___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW16_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW16_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW16_MSB (0x005CB2DC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW16_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW16_MSB__OTP_PATCH_951_928___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW16_MSB__OTP_PATCH_951_928___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW16_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW16_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW17_LSB (0x005CB2E0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW17_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW17_LSB__OTP_PATCH_983_952___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW17_LSB__OTP_PATCH_983_952___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW17_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW17_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW17_MSB (0x005CB2E4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW17_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW17_MSB__OTP_PATCH_1007_984___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW17_MSB__OTP_PATCH_1007_984___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW17_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW17_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW18_LSB (0x005CB2E8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW18_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW18_LSB__OTP_PATCH_1039_1008___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW18_LSB__OTP_PATCH_1039_1008___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW18_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW18_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW18_MSB (0x005CB2EC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW18_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW18_MSB__OTP_PATCH_1063_1040___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW18_MSB__OTP_PATCH_1063_1040___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW18_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW18_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW19_LSB (0x005CB2F0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW19_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW19_LSB__OTP_PATCH_1095_1064___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW19_LSB__OTP_PATCH_1095_1064___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW19_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW19_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW19_MSB (0x005CB2F4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW19_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW19_MSB__OTP_PATCH_1119_1096___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW19_MSB__OTP_PATCH_1119_1096___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW19_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW19_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW20_LSB (0x005CB2F8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW20_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW20_LSB__OTP_PATCH_1151_1120___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW20_LSB__OTP_PATCH_1151_1120___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW20_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW20_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW20_MSB (0x005CB2FC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW20_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW20_MSB__OTP_PATCH_1175_1152___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW20_MSB__OTP_PATCH_1175_1152___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW20_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW20_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW21_LSB (0x005CB300) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW21_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW21_LSB__OTP_PATCH_1207_1176___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW21_LSB__OTP_PATCH_1207_1176___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW21_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW21_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW21_MSB (0x005CB304) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW21_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW21_MSB__OTP_PATCH_1231_1208___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW21_MSB__OTP_PATCH_1231_1208___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW21_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW21_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW22_LSB (0x005CB308) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW22_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW22_LSB__OTP_PATCH_1263_1232___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW22_LSB__OTP_PATCH_1263_1232___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW22_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW22_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW22_MSB (0x005CB30C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW22_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW22_MSB__OTP_PATCH_1287_1264___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW22_MSB__OTP_PATCH_1287_1264___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW22_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW22_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW23_LSB (0x005CB310) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW23_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW23_LSB__OTP_PATCH_1319_1288___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW23_LSB__OTP_PATCH_1319_1288___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW23_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW23_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW23_MSB (0x005CB314) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW23_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW23_MSB__OTP_PATCH_1343_1320___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW23_MSB__OTP_PATCH_1343_1320___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW23_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW23_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW24_LSB (0x005CB318) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW24_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW24_LSB__OTP_PATCH_1375_1344___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW24_LSB__OTP_PATCH_1375_1344___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW24_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW24_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW24_MSB (0x005CB31C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW24_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW24_MSB__OTP_PATCH_1399_1376___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW24_MSB__OTP_PATCH_1399_1376___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW24_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW24_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW25_LSB (0x005CB320) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW25_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW25_LSB__OTP_PATCH_1431_1400___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW25_LSB__OTP_PATCH_1431_1400___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW25_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW25_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW25_MSB (0x005CB324) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW25_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW25_MSB__OTP_PATCH_1455_1432___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW25_MSB__OTP_PATCH_1455_1432___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW25_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW25_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW26_LSB (0x005CB328) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW26_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW26_LSB__OTP_PATCH_1487_1456___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW26_LSB__OTP_PATCH_1487_1456___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW26_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW26_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW26_MSB (0x005CB32C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW26_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW26_MSB__OTP_PATCH_1511_1488___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW26_MSB__OTP_PATCH_1511_1488___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW26_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW26_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW27_LSB (0x005CB330) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW27_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW27_LSB__OTP_PATCH_1543_1512___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW27_LSB__OTP_PATCH_1543_1512___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW27_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW27_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW27_MSB (0x005CB334) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW27_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW27_MSB__OTP_PATCH_1567_1544___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW27_MSB__OTP_PATCH_1567_1544___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW27_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW27_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW28_LSB (0x005CB338) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW28_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW28_LSB__OTP_PATCH_1599_1568___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW28_LSB__OTP_PATCH_1599_1568___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW28_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW28_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW28_MSB (0x005CB33C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW28_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW28_MSB__OTP_PATCH_1623_1600___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW28_MSB__OTP_PATCH_1623_1600___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW28_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW28_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW29_LSB (0x005CB340) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW29_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW29_LSB__OTP_PATCH_1655_1624___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW29_LSB__OTP_PATCH_1655_1624___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW29_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW29_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW29_MSB (0x005CB344) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW29_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW29_MSB__OTP_PATCH_1679_1656___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW29_MSB__OTP_PATCH_1679_1656___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW29_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW29_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW30_LSB (0x005CB348) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW30_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW30_LSB__OTP_PATCH_1711_1680___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW30_LSB__OTP_PATCH_1711_1680___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW30_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW30_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW30_MSB (0x005CB34C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW30_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW30_MSB__OTP_PATCH_1735_1712___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW30_MSB__OTP_PATCH_1735_1712___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW30_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW30_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW31_LSB (0x005CB350) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW31_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW31_LSB__OTP_PATCH_1767_1736___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW31_LSB__OTP_PATCH_1767_1736___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW31_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW31_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW31_MSB (0x005CB354) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW31_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW31_MSB__OTP_PATCH_1791_1768___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW31_MSB__OTP_PATCH_1791_1768___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW31_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_ROW31_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW0_LSB (0x005CB358) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW0_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW0_LSB__OTP_PATCH_RSVD_31_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW0_LSB__OTP_PATCH_RSVD_31_0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW0_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW0_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW0_MSB (0x005CB35C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW0_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW0_MSB__OTP_PATCH_RSVD_55_32___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW0_MSB__OTP_PATCH_RSVD_55_32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW0_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW0_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW1_LSB (0x005CB360) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW1_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW1_LSB__OTP_PATCH_RSVD_87_56___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW1_LSB__OTP_PATCH_RSVD_87_56___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW1_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW1_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW1_MSB (0x005CB364) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW1_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW1_MSB__OTP_PATCH_RSVD_111_88___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW1_MSB__OTP_PATCH_RSVD_111_88___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW1_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW1_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW2_LSB (0x005CB368) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW2_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW2_LSB__OTP_PATCH_RSVD_143_112___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW2_LSB__OTP_PATCH_RSVD_143_112___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW2_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW2_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW2_MSB (0x005CB36C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW2_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW2_MSB__OTP_PATCH_RSVD_167_144___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW2_MSB__OTP_PATCH_RSVD_167_144___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW2_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW2_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW3_LSB (0x005CB370) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW3_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW3_LSB__OTP_PATCH_RSVD_199_168___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW3_LSB__OTP_PATCH_RSVD_199_168___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW3_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW3_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW3_MSB (0x005CB374) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW3_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW3_MSB__OTP_PATCH_RSVD_223_200___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW3_MSB__OTP_PATCH_RSVD_223_200___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW3_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW3_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW4_LSB (0x005CB378) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW4_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW4_LSB__OTP_PATCH_RSVD_255_224___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW4_LSB__OTP_PATCH_RSVD_255_224___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW4_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW4_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW4_MSB (0x005CB37C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW4_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW4_MSB__OTP_PATCH_RSVD_279_256___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW4_MSB__OTP_PATCH_RSVD_279_256___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW4_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW4_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW5_LSB (0x005CB380) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW5_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW5_LSB__OTP_PATCH_RSVD_311_280___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW5_LSB__OTP_PATCH_RSVD_311_280___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW5_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW5_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW5_MSB (0x005CB384) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW5_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW5_MSB__OTP_PATCH_RSVD_335_312___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW5_MSB__OTP_PATCH_RSVD_335_312___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW5_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW5_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW6_LSB (0x005CB388) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW6_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW6_LSB__OTP_PATCH_RSVD_367_336___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW6_LSB__OTP_PATCH_RSVD_367_336___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW6_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW6_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW6_MSB (0x005CB38C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW6_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW6_MSB__OTP_PATCH_RSVD_391_368___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW6_MSB__OTP_PATCH_RSVD_391_368___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW6_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW6_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW7_LSB (0x005CB390) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW7_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW7_LSB__OTP_PATCH_RSVD_423_392___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW7_LSB__OTP_PATCH_RSVD_423_392___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW7_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW7_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW7_MSB (0x005CB394) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW7_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW7_MSB__OTP_PATCH_RSVD_447_424___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW7_MSB__OTP_PATCH_RSVD_447_424___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW7_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW7_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW8_LSB (0x005CB398) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW8_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW8_LSB__OTP_PATCH_RSVD_479_448___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW8_LSB__OTP_PATCH_RSVD_479_448___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW8_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW8_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW8_MSB (0x005CB39C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW8_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW8_MSB__OTP_PATCH_RSVD_503_480___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW8_MSB__OTP_PATCH_RSVD_503_480___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW8_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW8_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW9_LSB (0x005CB3A0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW9_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW9_LSB__OTP_PATCH_RSVD_535_504___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW9_LSB__OTP_PATCH_RSVD_535_504___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW9_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW9_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW9_MSB (0x005CB3A4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW9_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW9_MSB__OTP_PATCH_RSVD_559_536___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW9_MSB__OTP_PATCH_RSVD_559_536___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW9_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW9_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW10_LSB (0x005CB3A8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW10_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW10_LSB__OTP_PATCH_RSVD_591_560___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW10_LSB__OTP_PATCH_RSVD_591_560___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW10_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW10_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW10_MSB (0x005CB3AC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW10_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW10_MSB__OTP_PATCH_RSVD_615_592___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW10_MSB__OTP_PATCH_RSVD_615_592___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW10_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW10_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW11_LSB (0x005CB3B0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW11_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW11_LSB__OTP_PATCH_RSVD_647_616___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW11_LSB__OTP_PATCH_RSVD_647_616___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW11_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW11_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW11_MSB (0x005CB3B4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW11_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW11_MSB__OTP_PATCH_RSVD_671_648___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW11_MSB__OTP_PATCH_RSVD_671_648___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW11_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW11_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW12_LSB (0x005CB3B8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW12_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW12_LSB__OTP_PATCH_RSVD_703_672___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW12_LSB__OTP_PATCH_RSVD_703_672___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW12_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW12_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW12_MSB (0x005CB3BC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW12_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW12_MSB__OTP_PATCH_RSVD_727_704___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW12_MSB__OTP_PATCH_RSVD_727_704___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW12_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW12_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW13_LSB (0x005CB3C0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW13_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW13_LSB__OTP_PATCH_RSVD_759_728___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW13_LSB__OTP_PATCH_RSVD_759_728___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW13_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW13_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW13_MSB (0x005CB3C4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW13_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW13_MSB__OTP_PATCH_RSVD_783_760___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW13_MSB__OTP_PATCH_RSVD_783_760___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW13_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW13_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW14_LSB (0x005CB3C8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW14_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW14_LSB__OTP_PATCH_RSVD_815_784___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW14_LSB__OTP_PATCH_RSVD_815_784___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW14_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW14_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW14_MSB (0x005CB3CC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW14_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW14_MSB__OTP_PATCH_RSVD_839_816___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW14_MSB__OTP_PATCH_RSVD_839_816___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW14_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW14_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW15_LSB (0x005CB3D0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW15_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW15_LSB__OTP_PATCH_RSVD_871_840___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW15_LSB__OTP_PATCH_RSVD_871_840___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW15_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW15_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW15_MSB (0x005CB3D4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW15_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW15_MSB__OTP_PATCH_RSVD_895_872___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW15_MSB__OTP_PATCH_RSVD_895_872___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW15_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OTP_PATCH_RSVD_ROW15_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_LSB (0x005CB3D8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_LSB__BTCUSMAGIC___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_LSB__BTCUSMAGIC___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB (0x005CB3DC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__RSVD_R123_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__RSVD_R123_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__RSVD_R123_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__RSVD_R123_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__RSVD_R123_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__RSVD_R123_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__RSVD_R123_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__RSVD_R123_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__RSVD_R123_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__RSVD_R123_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__RSVD_R123_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__RSVD_R123_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__RSVD_R123_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__RSVD_R123_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__RSVD_R123_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__RSVD_R123_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__BTCUSSWCONFIG___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB__BTCUSSWCONFIG___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW0_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_LSB (0x005CB3E0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_LSB__BTCUSBDADDR1_3___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_LSB__BTCUSBDADDR1_3___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_LSB__BTCUSBDADDR1_2___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_LSB__BTCUSBDADDR1_2___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_LSB__BTCUSBDADDR1_1___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_LSB__BTCUSBDADDR1_1___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_LSB__BTCUSBDADDR1_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_LSB__BTCUSBDADDR1_0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB (0x005CB3E4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__RSVD_R124_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__RSVD_R124_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__RSVD_R124_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__RSVD_R124_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__RSVD_R124_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__RSVD_R124_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__RSVD_R124_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__RSVD_R124_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__RSVD_R124_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__RSVD_R124_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__RSVD_R124_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__RSVD_R124_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__RSVD_R124_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__RSVD_R124_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__RSVD_R124_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__RSVD_R124_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__BTCUSBDADDR1_5___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__BTCUSBDADDR1_5___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__BTCUSBDADDR1_4___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB__BTCUSBDADDR1_4___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW1_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_LSB (0x005CB3E8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_LSB__BTCUSADADDR2_3___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_LSB__BTCUSADADDR2_3___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_LSB__BTCUSADADDR2_2___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_LSB__BTCUSADADDR2_2___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_LSB__BTCUSADADDR2_1___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_LSB__BTCUSADADDR2_1___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_LSB__BTCUSADADDR2_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_LSB__BTCUSADADDR2_0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB (0x005CB3EC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__RSVD_R125_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__RSVD_R125_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__RSVD_R125_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__RSVD_R125_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__RSVD_R125_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__RSVD_R125_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__RSVD_R125_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__RSVD_R125_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__RSVD_R125_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__RSVD_R125_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__RSVD_R125_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__RSVD_R125_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__RSVD_R125_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__RSVD_R125_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__RSVD_R125_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__RSVD_R125_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__BTCUSADADDR2_5___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__BTCUSADADDR2_5___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__BTCUSADADDR2_4___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB__BTCUSADADDR2_4___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW2_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_LSB (0x005CB3F0) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_LSB__BTCUSSECKEY3___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_LSB__BTCUSSECKEY3___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_LSB__BTCUSSECKEY2___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_LSB__BTCUSSECKEY2___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_LSB__BTCUSSECKEY1___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_LSB__BTCUSSECKEY1___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_LSB__BTCUSSECKEY0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_LSB__BTCUSSECKEY0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_MSB (0x005CB3F4) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_MSB__BTCUSSECKEY6___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_MSB__BTCUSSECKEY6___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_MSB__BTCUSSECKEY5___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_MSB__BTCUSSECKEY5___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_MSB__BTCUSSECKEY4___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_MSB__BTCUSSECKEY4___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW3_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_LSB (0x005CB3F8) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_LSB__BTCUSSECKEY10___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_LSB__BTCUSSECKEY10___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_LSB__BTCUSSECKEY9___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_LSB__BTCUSSECKEY9___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_LSB__BTCUSSECKEY8___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_LSB__BTCUSSECKEY8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_LSB__BTCUSSECKEY7___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_LSB__BTCUSSECKEY7___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_MSB (0x005CB3FC) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_MSB__BTCUSSECKEY13___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_MSB__BTCUSSECKEY13___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_MSB__BTCUSSECKEY12___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_MSB__BTCUSSECKEY12___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_MSB__BTCUSSECKEY11___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_MSB__BTCUSSECKEY11___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW4_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_LSB (0x005CB400) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_LSB__BTCUSSECKEY17___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_LSB__BTCUSSECKEY17___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_LSB__BTCUSSECKEY16___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_LSB__BTCUSSECKEY16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_LSB__BTCUSSECKEY15___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_LSB__BTCUSSECKEY15___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_LSB__BTCUSSECKEY14___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_LSB__BTCUSSECKEY14___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_MSB (0x005CB404) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_MSB__BTCUSSECKEY20___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_MSB__BTCUSSECKEY20___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_MSB__BTCUSSECKEY19___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_MSB__BTCUSSECKEY19___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_MSB__BTCUSSECKEY18___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_MSB__BTCUSSECKEY18___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW5_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_LSB (0x005CB408) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_LSB__BTCUSSECKEY24___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_LSB__BTCUSSECKEY24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_LSB__BTCUSSECKEY23___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_LSB__BTCUSSECKEY23___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_LSB__BTCUSSECKEY22___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_LSB__BTCUSSECKEY22___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_LSB__BTCUSSECKEY21___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_LSB__BTCUSSECKEY21___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_MSB (0x005CB40C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_MSB__BTCUSSECKEY27___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_MSB__BTCUSSECKEY27___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_MSB__BTCUSSECKEY26___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_MSB__BTCUSSECKEY26___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_MSB__BTCUSSECKEY25___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_MSB__BTCUSSECKEY25___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW6_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_LSB (0x005CB410) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_LSB__BTCUSSECKEY31___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_LSB__BTCUSSECKEY31___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_LSB__BTCUSSECKEY30___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_LSB__BTCUSSECKEY30___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_LSB__BTCUSSECKEY29___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_LSB__BTCUSSECKEY29___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_LSB__BTCUSSECKEY28___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_LSB__BTCUSSECKEY28___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_MSB (0x005CB414) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_MSB__BTCUSMANUSTR2___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_MSB__BTCUSMANUSTR2___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_MSB__BTCUSMANUSTR1___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_MSB__BTCUSMANUSTR1___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_MSB__BTCUSMANUSTR0___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_MSB__BTCUSMANUSTR0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW7_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_LSB (0x005CB418) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_LSB__BTCUSMANUSTR6___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_LSB__BTCUSMANUSTR6___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_LSB__BTCUSMANUSTR5___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_LSB__BTCUSMANUSTR5___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_LSB__BTCUSMANUSTR4___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_LSB__BTCUSMANUSTR4___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_LSB__BTCUSMANUSTR3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_LSB__BTCUSMANUSTR3___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_MSB (0x005CB41C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_MSB__BTCUSMANUSTR9___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_MSB__BTCUSMANUSTR9___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_MSB__BTCUSMANUSTR8___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_MSB__BTCUSMANUSTR8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_MSB__BTCUSMANUSTR7___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_MSB__BTCUSMANUSTR7___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW8_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_LSB (0x005CB420) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_LSB__BTCUSMANUSTR13___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_LSB__BTCUSMANUSTR13___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_LSB__BTCUSMANUSTR12___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_LSB__BTCUSMANUSTR12___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_LSB__BTCUSMANUSTR11___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_LSB__BTCUSMANUSTR11___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_LSB__BTCUSMANUSTR10___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_LSB__BTCUSMANUSTR10___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_MSB (0x005CB424) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_MSB__BTCUSMANUSTR16___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_MSB__BTCUSMANUSTR16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_MSB__BTCUSMANUSTR15___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_MSB__BTCUSMANUSTR15___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_MSB__BTCUSMANUSTR14___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_MSB__BTCUSMANUSTR14___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW9_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_LSB (0x005CB428) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_LSB__BTCUSMANUSTR20___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_LSB__BTCUSMANUSTR20___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_LSB__BTCUSMANUSTR19___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_LSB__BTCUSMANUSTR19___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_LSB__BTCUSMANUSTR18___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_LSB__BTCUSMANUSTR18___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_LSB__BTCUSMANUSTR17___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_LSB__BTCUSMANUSTR17___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_MSB (0x005CB42C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_MSB__BTCUSMANUSTR23___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_MSB__BTCUSMANUSTR23___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_MSB__BTCUSMANUSTR22___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_MSB__BTCUSMANUSTR22___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_MSB__BTCUSMANUSTR21___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_MSB__BTCUSMANUSTR21___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW10_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_LSB (0x005CB430) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_LSB__BTCUSMANUSTR27___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_LSB__BTCUSMANUSTR27___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_LSB__BTCUSMANUSTR26___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_LSB__BTCUSMANUSTR26___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_LSB__BTCUSMANUSTR25___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_LSB__BTCUSMANUSTR25___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_LSB__BTCUSMANUSTR24___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_LSB__BTCUSMANUSTR24___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_MSB (0x005CB434) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_MSB__BTCUSMANUSTR30___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_MSB__BTCUSMANUSTR30___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_MSB__BTCUSMANUSTR29___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_MSB__BTCUSMANUSTR29___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_MSB__BTCUSMANUSTR28___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_MSB__BTCUSMANUSTR28___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW11_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_LSB (0x005CB438) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_LSB__BTCUSCONFIG2___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_LSB__BTCUSCONFIG2___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_LSB__BTCUSCONFIG1___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_LSB__BTCUSCONFIG1___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_LSB__BTCUSCONFIG0___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_LSB__BTCUSCONFIG0___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_LSB__BTCUSMANUSTR31___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_LSB__BTCUSMANUSTR31___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_MSB (0x005CB43C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_MSB__BTCUSCONFIG5___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_MSB__BTCUSCONFIG5___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_MSB__BTCUSCONFIG4___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_MSB__BTCUSCONFIG4___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_MSB__BTCUSCONFIG3___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_MSB__BTCUSCONFIG3___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW12_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_LSB (0x005CB440) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_LSB__BTCUSCONFIG9___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_LSB__BTCUSCONFIG9___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_LSB__BTCUSCONFIG8___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_LSB__BTCUSCONFIG8___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_LSB__BTCUSCONFIG7___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_LSB__BTCUSCONFIG7___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_LSB__BTCUSCONFIG6___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_LSB__BTCUSCONFIG6___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_MSB (0x005CB444) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_MSB__BTCUSCONFIG12___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_MSB__BTCUSCONFIG12___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_MSB__BTCUSCONFIG11___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_MSB__BTCUSCONFIG11___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_MSB__BTCUSCONFIG10___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_MSB__BTCUSCONFIG10___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW13_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB (0x005CB448) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__RSVD_R137_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__RSVD_R137_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__RSVD_R137_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__RSVD_R137_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__RSVD_R137_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__RSVD_R137_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__RSVD_R137_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__RSVD_R137_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__RSVD_R137_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__RSVD_R137_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__RSVD_R137_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__RSVD_R137_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__RSVD_R137_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__RSVD_R137_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__RSVD_R137_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__RSVD_R137_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__BTCUSCONFIG15___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__BTCUSCONFIG15___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__BTCUSCONFIG14___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__BTCUSCONFIG14___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__BTCUSCONFIG13___M 0x000000FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB__BTCUSCONFIG13___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB (0x005CB44C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB__RSVD_R137_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_OEM_BT_ROW14_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_LSB (0x005CB450) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_LSB__IDDQ_MX_ON___M 0xFF000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_LSB__IDDQ_MX_ON___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_LSB__IDDQ_CX_ON___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_LSB__IDDQ_CX_ON___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_LSB__RSVD_R138_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_LSB__RSVD_R138_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_LSB__IDDQ_PERF_APC_ON___M 0x00007FC0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_LSB__IDDQ_PERF_APC_ON___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_LSB__IDDQ_REV_CTRL___M 0x00000038 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_LSB__IDDQ_REV_CTRL___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_LSB__IDDQ_MULTI_BIT___M 0x00000007 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_LSB__IDDQ_MULTI_BIT___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_MSB (0x005CB454) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_MSB__RSVD_R138_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_MSB__RSVD_R138_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_MSB__RSVD_R138_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_MSB__RSVD_R138_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_MSB__IDDQ_APC_ON___M 0x003F0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_MSB__IDDQ_APC_ON___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_MSB__IDDQ_NPU_ON___M 0x0000FE00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_MSB__IDDQ_NPU_ON___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_MSB__IDDQ_WCSS_ON___M 0x000001FF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_MSB__IDDQ_WCSS_ON___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW0_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB (0x005CB458) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__RSVD_R139_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__RSVD_R139_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__IDDQ_NPU_OFF___M 0x7E000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__IDDQ_NPU_OFF___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__IDDQ_WCSS_OFF___M 0x01FF0000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__IDDQ_WCSS_OFF___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__RSVD_R139_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__RSVD_R139_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__RSVD_R139_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__RSVD_R139_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__RSVD_R139_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__RSVD_R139_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__IDDQ_MX_OFF___M 0x00001F00 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__IDDQ_MX_OFF___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__RSVD_R139_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__RSVD_R139_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__IDDQ_CX_OFF___M 0x0000007F +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB__IDDQ_CX_OFF___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB (0x005CB45C) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB__RSVD_R139_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_CALIBRATION_ROW1_MSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB (0x005CB460) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B31___M 0x80000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B31___S 31 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B30___M 0x40000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B30___S 30 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B29___M 0x20000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B29___S 29 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B28___M 0x10000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B28___S 28 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B27___M 0x08000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B27___S 27 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B26___M 0x04000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B26___S 26 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B25___M 0x02000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B25___S 25 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B24___M 0x01000000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B24___S 24 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B23___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B23___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B22___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B22___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B21___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B21___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B20___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B20___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B19___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B19___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B18___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B18___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B17___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B17___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B16___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B16___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B15___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B15___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B14___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B14___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B13___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B13___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B12___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B12___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B11___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B11___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B10___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B10___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B9___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B9___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B8___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B8___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B7___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B7___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B6___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B6___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B5___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B5___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B4___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B4___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B3___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B3___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B2___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B2___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B1___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B1___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B0___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB__RSVD_R140_B0___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_LSB___S 0 + +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB (0x005CB464) +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B55___M 0x00800000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B55___S 23 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B54___M 0x00400000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B54___S 22 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B53___M 0x00200000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B53___S 21 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B52___M 0x00100000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B52___S 20 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B51___M 0x00080000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B51___S 19 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B50___M 0x00040000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B50___S 18 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B49___M 0x00020000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B49___S 17 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B48___M 0x00010000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B48___S 16 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B47___M 0x00008000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B47___S 15 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B46___M 0x00004000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B46___S 14 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B45___M 0x00002000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B45___S 13 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B44___M 0x00001000 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B44___S 12 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B43___M 0x00000800 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B43___S 11 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B42___M 0x00000400 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B42___S 10 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B41___M 0x00000200 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B41___S 9 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B40___M 0x00000100 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B40___S 8 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B39___M 0x00000080 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B39___S 7 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B38___M 0x00000040 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B38___S 6 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B37___M 0x00000020 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B37___S 5 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B36___M 0x00000010 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B36___S 4 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B35___M 0x00000008 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B35___S 3 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B34___M 0x00000004 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B34___S 2 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B33___M 0x00000002 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B33___S 1 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B32___M 0x00000001 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB__RSVD_R140_B32___S 0 +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WSI_A_BT_FUSE_QFPROM_CORR_SPARE_REGION_16_MSB___S 0 + +#define PHYA_IRON2G_RFA_AON_TESTREG (0x005D4000) +#define PHYA_IRON2G_RFA_AON_TESTREG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_TESTREG___POR 0x1234ABCD +#define PHYA_IRON2G_RFA_AON_TESTREG__TESTREG___POR 0x1234ABCD +#define PHYA_IRON2G_RFA_AON_TESTREG__TESTREG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_AON_TESTREG__TESTREG___S 0 +#define PHYA_IRON2G_RFA_AON_TESTREG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_AON_TESTREG___S 0 + +#define PHYA_IRON2G_RFA_AON_RO_TESTREG (0x005D4004) +#define PHYA_IRON2G_RFA_AON_RO_TESTREG___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_RO_TESTREG___POR 0x8FAD7E57 +#define PHYA_IRON2G_RFA_AON_RO_TESTREG__RO_TESTREG___POR 0x8FAD7E57 +#define PHYA_IRON2G_RFA_AON_RO_TESTREG__RO_TESTREG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_AON_RO_TESTREG__RO_TESTREG___S 0 +#define PHYA_IRON2G_RFA_AON_RO_TESTREG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_AON_RO_TESTREG___S 0 + +#define PHYA_IRON2G_RFA_AON_CHIP_CONFIG (0x005D4008) +#define PHYA_IRON2G_RFA_AON_CHIP_CONFIG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_CHIP_CONFIG___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_CHIP_CONFIG__BROADCAST_WSI3___POR 0x0 +#define PHYA_IRON2G_RFA_AON_CHIP_CONFIG__BROADCAST_WSI2___POR 0x0 +#define PHYA_IRON2G_RFA_AON_CHIP_CONFIG__BROADCAST_WSI1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_CHIP_CONFIG__BROADCAST_WSI0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_CHIP_CONFIG__BROADCAST_WSI3___M 0x0000F000 +#define PHYA_IRON2G_RFA_AON_CHIP_CONFIG__BROADCAST_WSI3___S 12 +#define PHYA_IRON2G_RFA_AON_CHIP_CONFIG__BROADCAST_WSI2___M 0x00000F00 +#define PHYA_IRON2G_RFA_AON_CHIP_CONFIG__BROADCAST_WSI2___S 8 +#define PHYA_IRON2G_RFA_AON_CHIP_CONFIG__BROADCAST_WSI1___M 0x000000F0 +#define PHYA_IRON2G_RFA_AON_CHIP_CONFIG__BROADCAST_WSI1___S 4 +#define PHYA_IRON2G_RFA_AON_CHIP_CONFIG__BROADCAST_WSI0___M 0x0000000F +#define PHYA_IRON2G_RFA_AON_CHIP_CONFIG__BROADCAST_WSI0___S 0 +#define PHYA_IRON2G_RFA_AON_CHIP_CONFIG___M 0x0000FFFF +#define PHYA_IRON2G_RFA_AON_CHIP_CONFIG___S 0 + +#define PHYA_IRON2G_RFA_AON_RFA_GPIO_OUT (0x005D400C) +#define PHYA_IRON2G_RFA_AON_RFA_GPIO_OUT___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_RFA_GPIO_OUT___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RFA_GPIO_OUT__RFA_GPIO_OUT___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RFA_GPIO_OUT__RFA_GPIO_OUT___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_AON_RFA_GPIO_OUT__RFA_GPIO_OUT___S 0 +#define PHYA_IRON2G_RFA_AON_RFA_GPIO_OUT___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_AON_RFA_GPIO_OUT___S 0 + +#define PHYA_IRON2G_RFA_AON_RFA_GPIO_OE (0x005D4010) +#define PHYA_IRON2G_RFA_AON_RFA_GPIO_OE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_RFA_GPIO_OE___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RFA_GPIO_OE__RFA_GPIO_OE___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RFA_GPIO_OE__RFA_GPIO_OE___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_AON_RFA_GPIO_OE__RFA_GPIO_OE___S 0 +#define PHYA_IRON2G_RFA_AON_RFA_GPIO_OE___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_AON_RFA_GPIO_OE___S 0 + +#define PHYA_IRON2G_RFA_AON_RO_RFA_GPIO_IN (0x005D4014) +#define PHYA_IRON2G_RFA_AON_RO_RFA_GPIO_IN___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_RO_RFA_GPIO_IN___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RO_RFA_GPIO_IN__RO_RFA_GPIO_IN___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RO_RFA_GPIO_IN__RO_RFA_GPIO_IN___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_AON_RO_RFA_GPIO_IN__RO_RFA_GPIO_IN___S 0 +#define PHYA_IRON2G_RFA_AON_RO_RFA_GPIO_IN___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_AON_RO_RFA_GPIO_IN___S 0 + +#define PHYA_IRON2G_RFA_AON_BAND_CH0 (0x005D4018) +#define PHYA_IRON2G_RFA_AON_BAND_CH0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_BAND_CH0___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_BAND_CH0__BAND_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_BAND_CH0__BAND_CH0___M 0x00000001 +#define PHYA_IRON2G_RFA_AON_BAND_CH0__BAND_CH0___S 0 +#define PHYA_IRON2G_RFA_AON_BAND_CH0___M 0x00000001 +#define PHYA_IRON2G_RFA_AON_BAND_CH0___S 0 + +#define PHYA_IRON2G_RFA_AON_BAND_CH1 (0x005D401C) +#define PHYA_IRON2G_RFA_AON_BAND_CH1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_BAND_CH1___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_BAND_CH1__BAND_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_BAND_CH1__BAND_CH1___M 0x00000001 +#define PHYA_IRON2G_RFA_AON_BAND_CH1__BAND_CH1___S 0 +#define PHYA_IRON2G_RFA_AON_BAND_CH1___M 0x00000001 +#define PHYA_IRON2G_RFA_AON_BAND_CH1___S 0 + +#define PHYA_IRON2G_RFA_AON_AON_UNLOCK_CTRL (0x005D4020) +#define PHYA_IRON2G_RFA_AON_AON_UNLOCK_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_AON_UNLOCK_CTRL___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_AON_UNLOCK_CTRL__PROT_UNLOCK___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_AON_UNLOCK_CTRL__PROT_UNLOCK___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_AON_AON_UNLOCK_CTRL__PROT_UNLOCK___S 0 +#define PHYA_IRON2G_RFA_AON_AON_UNLOCK_CTRL___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_AON_AON_UNLOCK_CTRL___S 0 + +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0 (0x005D4024) +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_XO_ISO_EN_L_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BT_ISO_EN_L_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_FM_ISO_EN_L_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_WL_ISO_EN_L_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_CM_ISO_EN_L_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BBPLL_ISO_EN_L_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BTFMPLL_ISO_EN_L_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_AON_RST_L_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_XO_RST_L_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BT_RST_L_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_FM_RST_L_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_WL_RST_L_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_CM_RST_L_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BBPLL_RST_L_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BTFMPLL_RST_L_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__PRESET_L_SHRD_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_XO_ISO_EN_L_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_XO_ISO_EN_L_OVS___S 30 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BT_ISO_EN_L_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BT_ISO_EN_L_OVS___S 28 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_FM_ISO_EN_L_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_FM_ISO_EN_L_OVS___S 26 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_WL_ISO_EN_L_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_WL_ISO_EN_L_OVS___S 24 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_CM_ISO_EN_L_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_CM_ISO_EN_L_OVS___S 22 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BBPLL_ISO_EN_L_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BBPLL_ISO_EN_L_OVS___S 20 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BTFMPLL_ISO_EN_L_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BTFMPLL_ISO_EN_L_OVS___S 18 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_AON_RST_L_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_AON_RST_L_OVS___S 16 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_XO_RST_L_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_XO_RST_L_OVS___S 14 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BT_RST_L_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BT_RST_L_OVS___S 12 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_FM_RST_L_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_FM_RST_L_OVS___S 10 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_WL_RST_L_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_WL_RST_L_OVS___S 8 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_CM_RST_L_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_CM_RST_L_OVS___S 6 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BBPLL_RST_L_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BBPLL_RST_L_OVS___S 4 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BTFMPLL_RST_L_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__RFA_BTFMPLL_RST_L_OVS___S 2 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__PRESET_L_SHRD_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0__PRESET_L_SHRD_OVS___S 0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_0___S 0 + +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_1 (0x005D4028) +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_1__WL_SHUTDOWN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_1__WL_SHUTDOWN___M 0x00000001 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_1__WL_SHUTDOWN___S 0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_1___M 0x00000001 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_1___S 0 + +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_2 (0x005D402C) +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_2___POR 0x00000006 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_2__WLAN_TO_BTFMSS_WAKEUP___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_2__SPARE_C___POR 0x1 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_2__EMER_BOOT_REFCLK_SEL___POR 0x1 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_2__EMER_BOOT_LFCLK_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_2__WLAN_TO_BTFMSS_WAKEUP___M 0x00000008 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_2__WLAN_TO_BTFMSS_WAKEUP___S 3 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_2__SPARE_C___M 0x00000004 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_2__SPARE_C___S 2 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_2__EMER_BOOT_REFCLK_SEL___M 0x00000002 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_2__EMER_BOOT_REFCLK_SEL___S 1 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_2__EMER_BOOT_LFCLK_SEL___M 0x00000001 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_2__EMER_BOOT_LFCLK_SEL___S 0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_2___M 0x0000000F +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_2___S 0 + +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3 (0x005D4030) +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__XO_BG_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__CBG_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__CENTRAL_BIAS_LDO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__CENTRAL_BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__USE_CENTRAL_BIAS_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__WL_SWITCH_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__WL_SWITCH_EN_2_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__SPARE0_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__SPARE1_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_XO_LDO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_BT_LDO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_FM_LDO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_WL_LDO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_CM_LDO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_BBPLL_LDO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_BTFMPLL_LDO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__XO_BG_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__XO_BG_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__CBG_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__CBG_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__CENTRAL_BIAS_LDO_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__CENTRAL_BIAS_LDO_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__CENTRAL_BIAS_EN_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__CENTRAL_BIAS_EN_OVS___S 24 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__USE_CENTRAL_BIAS_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__USE_CENTRAL_BIAS_OVS___S 22 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__WL_SWITCH_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__WL_SWITCH_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__WL_SWITCH_EN_2_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__WL_SWITCH_EN_2_OVS___S 18 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__SPARE0_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__SPARE0_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__SPARE1_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__SPARE1_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_XO_LDO_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_XO_LDO_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_BT_LDO_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_BT_LDO_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_FM_LDO_EN_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_FM_LDO_EN_OVS___S 8 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_WL_LDO_EN_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_WL_LDO_EN_OVS___S 6 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_CM_LDO_EN_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_CM_LDO_EN_OVS___S 4 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_BBPLL_LDO_EN_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_BBPLL_LDO_EN_OVS___S 2 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_BTFMPLL_LDO_EN_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3__RFA_BTFMPLL_LDO_EN_OVS___S 0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_3___S 0 + +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4 (0x005D4034) +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL0_BG_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL1_CLKOUT_REFCLK_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL1_REFCLK_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL2_BTFM_BBPLL_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL2_BTFM_TXRX_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL2_WL_BBPLL_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL2_WL_TXRX_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL0_BG_REQ___M 0x00000040 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL0_BG_REQ___S 6 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL1_CLKOUT_REFCLK_REQ___M 0x00000020 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL1_CLKOUT_REFCLK_REQ___S 5 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL1_REFCLK_REQ___M 0x00000010 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL1_REFCLK_REQ___S 4 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL2_BTFM_BBPLL_REQ___M 0x00000008 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL2_BTFM_BBPLL_REQ___S 3 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL2_BTFM_TXRX_REQ___M 0x00000004 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL2_BTFM_TXRX_REQ___S 2 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL2_WL_BBPLL_REQ___M 0x00000002 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL2_WL_BBPLL_REQ___S 1 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL2_WL_TXRX_REQ___M 0x00000001 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4__ATEST_RFA_LEVEL2_WL_TXRX_REQ___S 0 +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4___M 0x0000007F +#define PHYA_IRON2G_RFA_AON_AON_PROTECT_REG_4___S 0 + +#define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG (0x005D4040) +#define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG___POR 0x00000001 +#define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__HW_DTIM_SLNA_CTRL_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__HW_DTIM_SLNA_CTRL_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__BT_TX_ON_SEL___POR 0x1 +#define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__HW_DTIM_SLNA_CTRL_CH0___M 0x00008000 +#define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__HW_DTIM_SLNA_CTRL_CH0___S 15 +#define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__HW_DTIM_SLNA_CTRL_CH1___M 0x00004000 +#define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__HW_DTIM_SLNA_CTRL_CH1___S 14 +#define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__BT_TX_ON_SEL___M 0x00000001 +#define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG__BT_TX_ON_SEL___S 0 +#define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG___M 0x0000C001 +#define PHYA_IRON2G_RFA_AON_WL_RFA_CONFIG___S 0 + +#define PHYA_IRON2G_RFA_AON_AOA (0x005D4044) +#define PHYA_IRON2G_RFA_AON_AOA___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_AOA___POR 0x0000007F +#define PHYA_IRON2G_RFA_AON_AOA__AOA_ACTIVE_TO_RFA_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_AOA__AOA_ACTIVE_MASK___POR 0x7F +#define PHYA_IRON2G_RFA_AON_AOA__AOA_ACTIVE_TO_RFA_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_AON_AOA__AOA_ACTIVE_TO_RFA_OVS___S 30 +#define PHYA_IRON2G_RFA_AON_AOA__AOA_ACTIVE_MASK___M 0x0000007F +#define PHYA_IRON2G_RFA_AON_AOA__AOA_ACTIVE_MASK___S 0 +#define PHYA_IRON2G_RFA_AON_AOA___M 0xC000007F +#define PHYA_IRON2G_RFA_AON_AOA___S 0 + +#define PHYA_IRON2G_RFA_AON_PM_0 (0x005D4048) +#define PHYA_IRON2G_RFA_AON_PM_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_PM_0___POR 0x00418000 +#define PHYA_IRON2G_RFA_AON_PM_0__D_RC_EN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_PM_0__D_PM_RINGOSC_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_AON_PM_0__D_PM_EN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_PM_0__RINGOSC_EN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_PM_0__SETTLE_TIMER___POR 0x0 +#define PHYA_IRON2G_RFA_AON_PM_0__SAMPLE_WIN___POR 0x4 +#define PHYA_IRON2G_RFA_AON_PM_0__D_RC_CAPTYPE_SEL___POR 0x1 +#define PHYA_IRON2G_RFA_AON_PM_0__D_PM_GRP_ADDR___POR 0x1 +#define PHYA_IRON2G_RFA_AON_PM_0__D_PM_OSC_ADDR___POR 0x0 +#define PHYA_IRON2G_RFA_AON_PM_0__D_PM_HGAIN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_PM_0__RC_IN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_PM_0__PM_IN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_PM_0__D_RC_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_PM_0__D_RC_EN___S 31 +#define PHYA_IRON2G_RFA_AON_PM_0__D_PM_RINGOSC_SEL___M 0x70000000 +#define PHYA_IRON2G_RFA_AON_PM_0__D_PM_RINGOSC_SEL___S 28 +#define PHYA_IRON2G_RFA_AON_PM_0__D_PM_EN___M 0x08000000 +#define PHYA_IRON2G_RFA_AON_PM_0__D_PM_EN___S 27 +#define PHYA_IRON2G_RFA_AON_PM_0__RINGOSC_EN___M 0x04000000 +#define PHYA_IRON2G_RFA_AON_PM_0__RINGOSC_EN___S 26 +#define PHYA_IRON2G_RFA_AON_PM_0__SETTLE_TIMER___M 0x03000000 +#define PHYA_IRON2G_RFA_AON_PM_0__SETTLE_TIMER___S 24 +#define PHYA_IRON2G_RFA_AON_PM_0__SAMPLE_WIN___M 0x00700000 +#define PHYA_IRON2G_RFA_AON_PM_0__SAMPLE_WIN___S 20 +#define PHYA_IRON2G_RFA_AON_PM_0__D_RC_CAPTYPE_SEL___M 0x000F0000 +#define PHYA_IRON2G_RFA_AON_PM_0__D_RC_CAPTYPE_SEL___S 16 +#define PHYA_IRON2G_RFA_AON_PM_0__D_PM_GRP_ADDR___M 0x00008000 +#define PHYA_IRON2G_RFA_AON_PM_0__D_PM_GRP_ADDR___S 15 +#define PHYA_IRON2G_RFA_AON_PM_0__D_PM_OSC_ADDR___M 0x00007000 +#define PHYA_IRON2G_RFA_AON_PM_0__D_PM_OSC_ADDR___S 12 +#define PHYA_IRON2G_RFA_AON_PM_0__D_PM_HGAIN___M 0x00000C00 +#define PHYA_IRON2G_RFA_AON_PM_0__D_PM_HGAIN___S 10 +#define PHYA_IRON2G_RFA_AON_PM_0__RC_IN_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_AON_PM_0__RC_IN_OVS___S 2 +#define PHYA_IRON2G_RFA_AON_PM_0__PM_IN_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_AON_PM_0__PM_IN_OVS___S 0 +#define PHYA_IRON2G_RFA_AON_PM_0___M 0xFF7FFC0F +#define PHYA_IRON2G_RFA_AON_PM_0___S 0 + +#define PHYA_IRON2G_RFA_AON_RO_PM (0x005D404C) +#define PHYA_IRON2G_RFA_AON_RO_PM___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_RO_PM___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RO_PM__RO_PM_COUNT_VALID___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_PM__RO_PM_COUNT___POR 0x0000 +#define PHYA_IRON2G_RFA_AON_RO_PM__RO_PM_COUNT_VALID___M 0x00010000 +#define PHYA_IRON2G_RFA_AON_RO_PM__RO_PM_COUNT_VALID___S 16 +#define PHYA_IRON2G_RFA_AON_RO_PM__RO_PM_COUNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_AON_RO_PM__RO_PM_COUNT___S 0 +#define PHYA_IRON2G_RFA_AON_RO_PM___M 0x0001FFFF +#define PHYA_IRON2G_RFA_AON_RO_PM___S 0 + +#define PHYA_IRON2G_RFA_AON_WL_BT_CONC (0x005D4050) +#define PHYA_IRON2G_RFA_AON_WL_BT_CONC___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_WL_BT_CONC___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH0_MASK___POR 0x0 +#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH1_MASK___POR 0x0 +#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__FORCE_WLAN_TX_2G___POR 0x0 +#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_EXT_TMR___POR 0x00 +#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH0_MASK_PTA___POR 0x0 +#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH1_MASK_PTA___POR 0x0 +#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__FORCE_WLAN_TX_2G_PTA___POR 0x0 +#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_CONTROL_EN_BT_TX_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WL_BT_CONCURRENT_TX_CFG___POR 0x0 +#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH0_MASK___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH0_MASK___S 31 +#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH1_MASK___M 0x40000000 +#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH1_MASK___S 30 +#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__FORCE_WLAN_TX_2G___M 0x20000000 +#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__FORCE_WLAN_TX_2G___S 29 +#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_EXT_TMR___M 0x1FC00000 +#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_EXT_TMR___S 22 +#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH0_MASK_PTA___M 0x00008000 +#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH0_MASK_PTA___S 15 +#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH1_MASK_PTA___M 0x00004000 +#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_TX_2G_CH1_MASK_PTA___S 14 +#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__FORCE_WLAN_TX_2G_PTA___M 0x00002000 +#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__FORCE_WLAN_TX_2G_PTA___S 13 +#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_CONTROL_EN_BT_TX_OVS___M 0x00000018 +#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WLAN_CONTROL_EN_BT_TX_OVS___S 3 +#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WL_BT_CONCURRENT_TX_CFG___M 0x00000001 +#define PHYA_IRON2G_RFA_AON_WL_BT_CONC__WL_BT_CONCURRENT_TX_CFG___S 0 +#define PHYA_IRON2G_RFA_AON_WL_BT_CONC___M 0xFFC0E019 +#define PHYA_IRON2G_RFA_AON_WL_BT_CONC___S 0 + +#define PHYA_IRON2G_RFA_AON_ATB (0x005D4054) +#define PHYA_IRON2G_RFA_AON_ATB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_ATB___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB17_SEL_BT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB12_SEL_BT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB08_SEL_BT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB17_SEL_WL_2G___POR 0x0 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB12_SEL_WL_2G___POR 0x0 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB08_SEL_WL_2G___POR 0x0 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB17_SEL_WL_5G_0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB12_SEL_WL_5G_0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB08_SEL_WL_5G_0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB17_SEL_WL_5G_1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB12_SEL_WL_5G_1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB08_SEL_WL_5G_1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB17_SEL_BT___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB17_SEL_BT___S 31 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB12_SEL_BT___M 0x40000000 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB12_SEL_BT___S 30 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB08_SEL_BT___M 0x20000000 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB08_SEL_BT___S 29 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB17_SEL_WL_2G___M 0x10000000 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB17_SEL_WL_2G___S 28 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB12_SEL_WL_2G___M 0x08000000 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB12_SEL_WL_2G___S 27 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB08_SEL_WL_2G___M 0x04000000 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB08_SEL_WL_2G___S 26 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB17_SEL_WL_5G_0___M 0x02000000 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB17_SEL_WL_5G_0___S 25 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB12_SEL_WL_5G_0___M 0x01000000 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB12_SEL_WL_5G_0___S 24 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB08_SEL_WL_5G_0___M 0x00800000 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB08_SEL_WL_5G_0___S 23 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB17_SEL_WL_5G_1___M 0x00400000 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB17_SEL_WL_5G_1___S 22 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB12_SEL_WL_5G_1___M 0x00200000 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB12_SEL_WL_5G_1___S 21 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB08_SEL_WL_5G_1___M 0x00100000 +#define PHYA_IRON2G_RFA_AON_ATB__D_ATB08_SEL_WL_5G_1___S 20 +#define PHYA_IRON2G_RFA_AON_ATB___M 0xFFF00000 +#define PHYA_IRON2G_RFA_AON_ATB___S 20 + +#define PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL (0x005D4058) +#define PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_WL_SYN_5G_GPIO_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_WL_LPSYN_5G_GPIO_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_WL_SYN_2G_GPIO_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_MDLL_2G_GPIO_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_BT_SYN_GPIO_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_BT_DPLL_GPIO_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_WL_DPLL_GPIO_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_WL_SYN_5G_GPIO_SEL___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_WL_SYN_5G_GPIO_SEL___S 31 +#define PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_WL_LPSYN_5G_GPIO_SEL___M 0x40000000 +#define PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_WL_LPSYN_5G_GPIO_SEL___S 30 +#define PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_WL_SYN_2G_GPIO_SEL___M 0x20000000 +#define PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_WL_SYN_2G_GPIO_SEL___S 29 +#define PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_MDLL_2G_GPIO_SEL___M 0x10000000 +#define PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_MDLL_2G_GPIO_SEL___S 28 +#define PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_BT_SYN_GPIO_SEL___M 0x08000000 +#define PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_BT_SYN_GPIO_SEL___S 27 +#define PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_BT_DPLL_GPIO_SEL___M 0x04000000 +#define PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_BT_DPLL_GPIO_SEL___S 26 +#define PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_WL_DPLL_GPIO_SEL___M 0x02000000 +#define PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL__D_RF_WL_DPLL_GPIO_SEL___S 25 +#define PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL___M 0xFE000000 +#define PHYA_IRON2G_RFA_AON_GPIO_MUX_SEL___S 25 + +#define PHYA_IRON2G_RFA_AON_RO_DBG_0 (0x005D405C) +#define PHYA_IRON2G_RFA_AON_RO_DBG_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_RO_DBG_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_WSIS_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RCB_BUS_MATRIX_RST___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_XO_ISO_EN_L___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_WL_ISO_EN_L___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_CM_ISO_EN_L___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BT_ISO_EN_L___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_FM_ISO_EN_L___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BBPLL_ISO_EN_L___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BTFMPLL_ISO_EN_L___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_AON_RST_L___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_XO_RST_L___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_WL_RST_L___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_CM_RST_L___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BT_RST_L___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_FM_RST_L___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BBPLL_RST_L___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BTFMPLL_RST_L___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_XO_LDO_EN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_WL_LDO_EN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_CM_LDO_EN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BT_LDO_EN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_FM_LDO_EN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BBPLL_LDO_EN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BTFMPLL_LDO_EN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_D_XO_BG_EN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_D_CBG_EN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_D_CENTRAL_BIAS_LDO_EN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_D_TOP_MASTER_BIAS_EN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_D_USE_CENTRAL_BIAS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_WL_SWITCH_EN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_WL_SWITCH_EN_2___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_WSIS_RESET___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_WSIS_RESET___S 31 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RCB_BUS_MATRIX_RST___M 0x40000000 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RCB_BUS_MATRIX_RST___S 30 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_XO_ISO_EN_L___M 0x20000000 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_XO_ISO_EN_L___S 29 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_WL_ISO_EN_L___M 0x10000000 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_WL_ISO_EN_L___S 28 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_CM_ISO_EN_L___M 0x08000000 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_CM_ISO_EN_L___S 27 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BT_ISO_EN_L___M 0x04000000 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BT_ISO_EN_L___S 26 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_FM_ISO_EN_L___M 0x02000000 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_FM_ISO_EN_L___S 25 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BBPLL_ISO_EN_L___M 0x01000000 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BBPLL_ISO_EN_L___S 24 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BTFMPLL_ISO_EN_L___M 0x00800000 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BTFMPLL_ISO_EN_L___S 23 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_AON_RST_L___M 0x00400000 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_AON_RST_L___S 22 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_XO_RST_L___M 0x00200000 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_XO_RST_L___S 21 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_WL_RST_L___M 0x00100000 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_WL_RST_L___S 20 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_CM_RST_L___M 0x00080000 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_CM_RST_L___S 19 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BT_RST_L___M 0x00040000 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BT_RST_L___S 18 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_FM_RST_L___M 0x00020000 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_FM_RST_L___S 17 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BBPLL_RST_L___M 0x00010000 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BBPLL_RST_L___S 16 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BTFMPLL_RST_L___M 0x00008000 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BTFMPLL_RST_L___S 15 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_XO_LDO_EN___M 0x00004000 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_XO_LDO_EN___S 14 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_WL_LDO_EN___M 0x00002000 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_WL_LDO_EN___S 13 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_CM_LDO_EN___M 0x00001000 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_CM_LDO_EN___S 12 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BT_LDO_EN___M 0x00000800 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BT_LDO_EN___S 11 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_FM_LDO_EN___M 0x00000400 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_FM_LDO_EN___S 10 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BBPLL_LDO_EN___M 0x00000200 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BBPLL_LDO_EN___S 9 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BTFMPLL_LDO_EN___M 0x00000100 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_RFA_BTFMPLL_LDO_EN___S 8 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_D_XO_BG_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_D_XO_BG_EN___S 7 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_D_CBG_EN___M 0x00000040 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_D_CBG_EN___S 6 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_D_CENTRAL_BIAS_LDO_EN___M 0x00000020 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_D_CENTRAL_BIAS_LDO_EN___S 5 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_D_TOP_MASTER_BIAS_EN___M 0x00000010 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_D_TOP_MASTER_BIAS_EN___S 4 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_D_USE_CENTRAL_BIAS___M 0x00000008 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_D_USE_CENTRAL_BIAS___S 3 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_WL_SWITCH_EN___M 0x00000004 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_WL_SWITCH_EN___S 2 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_WL_SWITCH_EN_2___M 0x00000002 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0__RO_WL_SWITCH_EN_2___S 1 +#define PHYA_IRON2G_RFA_AON_RO_DBG_0___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_AON_RO_DBG_0___S 1 + +#define PHYA_IRON2G_RFA_AON_RO_DBG_1 (0x005D4060) +#define PHYA_IRON2G_RFA_AON_RO_DBG_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_RO_DBG_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RO_DBG_1__RO_AOA_ACTIVE_TO_RFA___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_DBG_1__RO_BTD_TXRF_PREDA_EN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_DBG_1__RO_AOA_ACTIVE_TO_RFA___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_RO_DBG_1__RO_AOA_ACTIVE_TO_RFA___S 31 +#define PHYA_IRON2G_RFA_AON_RO_DBG_1__RO_BTD_TXRF_PREDA_EN___M 0x40000000 +#define PHYA_IRON2G_RFA_AON_RO_DBG_1__RO_BTD_TXRF_PREDA_EN___S 30 +#define PHYA_IRON2G_RFA_AON_RO_DBG_1___M 0xC0000000 +#define PHYA_IRON2G_RFA_AON_RO_DBG_1___S 30 + +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0 (0x005D4064) +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL0_BG_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL1_CLKOUT_REFCLK_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL1_REFCLK_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_BTFMPLL_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_BTFM_TXRX_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_BBPLL_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_WL_TXRX_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_CM_TXRX_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL0_BG_READY___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL1_CLKOUT_REFCLK_READY___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL1_REFCLK_READY___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_BTFM_BBPLL_READY___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_BTFM_TXRX_READY___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_WL_BBPLL_READY___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_WL_TXRX_READY___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_CM_TXRX_READY___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL0_BG_REQ___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL0_BG_REQ___S 31 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL1_CLKOUT_REFCLK_REQ___M 0x40000000 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL1_CLKOUT_REFCLK_REQ___S 30 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL1_REFCLK_REQ___M 0x20000000 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL1_REFCLK_REQ___S 29 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_BTFMPLL_REQ___M 0x10000000 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_BTFMPLL_REQ___S 28 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_BTFM_TXRX_REQ___M 0x08000000 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_BTFM_TXRX_REQ___S 27 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_BBPLL_REQ___M 0x04000000 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_BBPLL_REQ___S 26 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_WL_TXRX_REQ___M 0x02000000 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_WL_TXRX_REQ___S 25 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_CM_TXRX_REQ___M 0x01000000 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_CM_TXRX_REQ___S 24 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL0_BG_READY___M 0x00010000 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL0_BG_READY___S 16 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL1_CLKOUT_REFCLK_READY___M 0x00008000 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL1_CLKOUT_REFCLK_READY___S 15 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL1_REFCLK_READY___M 0x00004000 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL1_REFCLK_READY___S 14 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_BTFM_BBPLL_READY___M 0x00002000 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_BTFM_BBPLL_READY___S 13 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_BTFM_TXRX_READY___M 0x00001000 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_BTFM_TXRX_READY___S 12 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_WL_BBPLL_READY___M 0x00000800 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_WL_BBPLL_READY___S 11 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_WL_TXRX_READY___M 0x00000400 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_WL_TXRX_READY___S 10 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_CM_TXRX_READY___M 0x00000200 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0__RO_RFA_LEVEL2_CM_TXRX_READY___S 9 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0___M 0xFF01FE00 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG0___S 9 + +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1 (0x005D4068) +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL01_CST___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL2_CST_BBPLL___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL2_CST_BTFMPLL___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL2_CST_WL_TXRX___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL2_CST_BTFM_TXRX___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL2_CST_CM_TXRX___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL01_CST___M 0xF0000000 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL01_CST___S 28 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL2_CST_BBPLL___M 0x0F000000 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL2_CST_BBPLL___S 24 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL2_CST_BTFMPLL___M 0x00F00000 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL2_CST_BTFMPLL___S 20 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL2_CST_WL_TXRX___M 0x000F0000 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL2_CST_WL_TXRX___S 16 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL2_CST_BTFM_TXRX___M 0x0000F000 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL2_CST_BTFM_TXRX___S 12 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL2_CST_CM_TXRX___M 0x00000F00 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1__RO_LEVEL2_CST_CM_TXRX___S 8 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1___M 0xFFFFFF00 +#define PHYA_IRON2G_RFA_AON_RO_BOOTUP_DBG1___S 8 + +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0 (0x005D4080) +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_VHT160_MODE_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_RX_GAIN_TYPE_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_RX_GAIN_IDX_CT___POR 0x00 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_CLPC_PKT_TYPE_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_TPC_PDET_GAIN_IDX_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_TPC_ATTEN_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_TX_GAIN_IDX_CT___POR 0x00 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_ANT_SEL_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_TX_EN_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_RX_EN_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_TX_CH_BW_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_RX_CH_BW_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_VHT160_MODE_CT___M 0xC0000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_VHT160_MODE_CT___S 30 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_RX_GAIN_TYPE_CT___M 0x30000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_RX_GAIN_TYPE_CT___S 28 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_RX_GAIN_IDX_CT___M 0x0FE00000 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_RX_GAIN_IDX_CT___S 21 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_CLPC_PKT_TYPE_CT___M 0x00100000 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_CLPC_PKT_TYPE_CT___S 20 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_TPC_PDET_GAIN_IDX_CT___M 0x00080000 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_TPC_PDET_GAIN_IDX_CT___S 19 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_TPC_ATTEN_CT___M 0x00078000 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_TPC_ATTEN_CT___S 15 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_TX_GAIN_IDX_CT___M 0x00007E00 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_TX_GAIN_IDX_CT___S 9 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_ANT_SEL_CT___M 0x00000100 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_ANT_SEL_CT___S 8 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_TX_EN_CT___M 0x00000080 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_TX_EN_CT___S 7 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_RX_EN_CT___M 0x00000040 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_RX_EN_CT___S 6 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_TX_CH_BW_CT___M 0x00000038 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_TX_CH_BW_CT___S 3 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_RX_CH_BW_CT___M 0x00000007 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0__RO_WSI0_RX_CH_BW_CT___S 0 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_0___S 0 + +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_1 (0x005D4084) +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_1__RO_WSI0_MAIN_SYN_EN_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_1__RO_WSI0_LP_SYN_EN_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_1__RO_WSI0_LP_SYN_SEL_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_1__RO_WSI0_MAIN_SYN_EN_CT___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_1__RO_WSI0_MAIN_SYN_EN_CT___S 31 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_1__RO_WSI0_LP_SYN_EN_CT___M 0x40000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_1__RO_WSI0_LP_SYN_EN_CT___S 30 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_1__RO_WSI0_LP_SYN_SEL_CT___M 0x20000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_1__RO_WSI0_LP_SYN_SEL_CT___S 29 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_1___M 0xE0000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_MSG_1___S 29 + +#define PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL (0x005D4088) +#define PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL___POR 0x80000000 +#define PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_STAT_ENABLE___POR 0x1 +#define PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_SLAVE_INTR_FRAME_COUNT_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_MASTER_READ_FRAME_COUNT_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_SHORT_WRITE_FRAME_COUNT_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_LONG_WRITE_FRAME_COUNT_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_CMD_ABORTED_COUNT_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_PARITY_ERR_COUNT_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_STAT_ENABLE___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_STAT_ENABLE___S 31 +#define PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_SLAVE_INTR_FRAME_COUNT_RESET___M 0x00000020 +#define PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_SLAVE_INTR_FRAME_COUNT_RESET___S 5 +#define PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_MASTER_READ_FRAME_COUNT_RESET___M 0x00000010 +#define PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_MASTER_READ_FRAME_COUNT_RESET___S 4 +#define PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_SHORT_WRITE_FRAME_COUNT_RESET___M 0x00000008 +#define PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_SHORT_WRITE_FRAME_COUNT_RESET___S 3 +#define PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_LONG_WRITE_FRAME_COUNT_RESET___M 0x00000004 +#define PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_LONG_WRITE_FRAME_COUNT_RESET___S 2 +#define PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_CMD_ABORTED_COUNT_RESET___M 0x00000002 +#define PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_CMD_ABORTED_COUNT_RESET___S 1 +#define PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_PARITY_ERR_COUNT_RESET___M 0x00000001 +#define PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL__WSI0_PARITY_ERR_COUNT_RESET___S 0 +#define PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL___M 0x8000003F +#define PHYA_IRON2G_RFA_AON_WSI0_STAT_CTRL___S 0 + +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0 (0x005D408C) +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_SYNCH_STATE___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_RCB_BUSY___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_RCB_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_RCB_GNT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_SLAVE_INTR_FRAME_COUNT___POR 0x00 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_MASTER_READ_FRAME_COUNT___POR 0x00 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_SYNCH_STATE___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_SYNCH_STATE___S 31 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_RCB_BUSY___M 0x40000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_RCB_BUSY___S 30 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_RCB_REQ___M 0x20000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_RCB_REQ___S 29 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_RCB_GNT___M 0x10000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_RCB_GNT___S 28 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_SLAVE_INTR_FRAME_COUNT___M 0x0000FF00 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_SLAVE_INTR_FRAME_COUNT___S 8 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_MASTER_READ_FRAME_COUNT___M 0x000000FF +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0__RO_WSI0_MASTER_READ_FRAME_COUNT___S 0 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0___M 0xF000FFFF +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_0___S 0 + +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_1 (0x005D4090) +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_1__RO_WSI0_SHORT_WRITE_FRAME_COUNT___POR 0x00 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_1__RO_WSI0_LONG_WRITE_FRAME_COUNT___POR 0x00 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_1__RO_WSI0_CMD_ABORTED_COUNT___POR 0x00 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_1__RO_WSI0_PARITY_ERR_COUNT___POR 0x00 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_1__RO_WSI0_SHORT_WRITE_FRAME_COUNT___M 0xFF000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_1__RO_WSI0_SHORT_WRITE_FRAME_COUNT___S 24 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_1__RO_WSI0_LONG_WRITE_FRAME_COUNT___M 0x00FF0000 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_1__RO_WSI0_LONG_WRITE_FRAME_COUNT___S 16 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_1__RO_WSI0_CMD_ABORTED_COUNT___M 0x0000FF00 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_1__RO_WSI0_CMD_ABORTED_COUNT___S 8 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_1__RO_WSI0_PARITY_ERR_COUNT___M 0x000000FF +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_1__RO_WSI0_PARITY_ERR_COUNT___S 0 +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_AON_RO_WSI0_STAT_1___S 0 + +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0 (0x005D4094) +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_VHT160_MODE_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_RX_GAIN_TYPE_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_RX_GAIN_IDX_CT___POR 0x00 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_CLPC_PKT_TYPE_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_TPC_PDET_GAIN_IDX_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_TPC_ATTEN_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_TX_GAIN_IDX_CT___POR 0x00 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_ANT_SEL_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_TX_EN_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_RX_EN_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_TX_CH_BW_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_RX_CH_BW_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_VHT160_MODE_CT___M 0xC0000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_VHT160_MODE_CT___S 30 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_RX_GAIN_TYPE_CT___M 0x30000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_RX_GAIN_TYPE_CT___S 28 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_RX_GAIN_IDX_CT___M 0x0FE00000 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_RX_GAIN_IDX_CT___S 21 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_CLPC_PKT_TYPE_CT___M 0x00100000 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_CLPC_PKT_TYPE_CT___S 20 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_TPC_PDET_GAIN_IDX_CT___M 0x00080000 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_TPC_PDET_GAIN_IDX_CT___S 19 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_TPC_ATTEN_CT___M 0x00078000 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_TPC_ATTEN_CT___S 15 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_TX_GAIN_IDX_CT___M 0x00007E00 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_TX_GAIN_IDX_CT___S 9 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_ANT_SEL_CT___M 0x00000100 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_ANT_SEL_CT___S 8 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_TX_EN_CT___M 0x00000080 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_TX_EN_CT___S 7 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_RX_EN_CT___M 0x00000040 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_RX_EN_CT___S 6 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_TX_CH_BW_CT___M 0x00000038 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_TX_CH_BW_CT___S 3 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_RX_CH_BW_CT___M 0x00000007 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0__RO_WSI1_RX_CH_BW_CT___S 0 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_0___S 0 + +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_1 (0x005D4098) +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_1__RO_WSI1_MAIN_SYN_EN_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_1__RO_WSI1_LP_SYN_EN_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_1__RO_WSI1_LP_SYN_SEL_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_1__RO_WSI1_MAIN_SYN_EN_CT___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_1__RO_WSI1_MAIN_SYN_EN_CT___S 31 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_1__RO_WSI1_LP_SYN_EN_CT___M 0x40000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_1__RO_WSI1_LP_SYN_EN_CT___S 30 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_1__RO_WSI1_LP_SYN_SEL_CT___M 0x20000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_1__RO_WSI1_LP_SYN_SEL_CT___S 29 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_1___M 0xE0000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_MSG_1___S 29 + +#define PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL (0x005D409C) +#define PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL___POR 0x80000000 +#define PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_STAT_ENABLE___POR 0x1 +#define PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_SLAVE_INTR_FRAME_COUNT_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_MASTER_READ_FRAME_COUNT_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_SHORT_WRITE_FRAME_COUNT_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_LONG_WRITE_FRAME_COUNT_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_CMD_ABORTED_COUNT_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_PARITY_ERR_COUNT_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_STAT_ENABLE___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_STAT_ENABLE___S 31 +#define PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_SLAVE_INTR_FRAME_COUNT_RESET___M 0x00000020 +#define PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_SLAVE_INTR_FRAME_COUNT_RESET___S 5 +#define PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_MASTER_READ_FRAME_COUNT_RESET___M 0x00000010 +#define PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_MASTER_READ_FRAME_COUNT_RESET___S 4 +#define PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_SHORT_WRITE_FRAME_COUNT_RESET___M 0x00000008 +#define PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_SHORT_WRITE_FRAME_COUNT_RESET___S 3 +#define PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_LONG_WRITE_FRAME_COUNT_RESET___M 0x00000004 +#define PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_LONG_WRITE_FRAME_COUNT_RESET___S 2 +#define PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_CMD_ABORTED_COUNT_RESET___M 0x00000002 +#define PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_CMD_ABORTED_COUNT_RESET___S 1 +#define PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_PARITY_ERR_COUNT_RESET___M 0x00000001 +#define PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL__WSI1_PARITY_ERR_COUNT_RESET___S 0 +#define PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL___M 0x8000003F +#define PHYA_IRON2G_RFA_AON_WSI1_STAT_CTRL___S 0 + +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0 (0x005D40A0) +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_SYNCH_STATE___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_RCB_BUSY___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_RCB_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_RCB_GNT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_SLAVE_INTR_FRAME_COUNT___POR 0x00 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_MASTER_READ_FRAME_COUNT___POR 0x00 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_SYNCH_STATE___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_SYNCH_STATE___S 31 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_RCB_BUSY___M 0x40000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_RCB_BUSY___S 30 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_RCB_REQ___M 0x20000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_RCB_REQ___S 29 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_RCB_GNT___M 0x10000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_RCB_GNT___S 28 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_SLAVE_INTR_FRAME_COUNT___M 0x0000FF00 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_SLAVE_INTR_FRAME_COUNT___S 8 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_MASTER_READ_FRAME_COUNT___M 0x000000FF +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0__RO_WSI1_MASTER_READ_FRAME_COUNT___S 0 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0___M 0xF000FFFF +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_0___S 0 + +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_1 (0x005D40A4) +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_1__RO_WSI1_SHORT_WRITE_FRAME_COUNT___POR 0x00 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_1__RO_WSI1_LONG_WRITE_FRAME_COUNT___POR 0x00 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_1__RO_WSI1_CMD_ABORTED_COUNT___POR 0x00 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_1__RO_WSI1_PARITY_ERR_COUNT___POR 0x00 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_1__RO_WSI1_SHORT_WRITE_FRAME_COUNT___M 0xFF000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_1__RO_WSI1_SHORT_WRITE_FRAME_COUNT___S 24 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_1__RO_WSI1_LONG_WRITE_FRAME_COUNT___M 0x00FF0000 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_1__RO_WSI1_LONG_WRITE_FRAME_COUNT___S 16 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_1__RO_WSI1_CMD_ABORTED_COUNT___M 0x0000FF00 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_1__RO_WSI1_CMD_ABORTED_COUNT___S 8 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_1__RO_WSI1_PARITY_ERR_COUNT___M 0x000000FF +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_1__RO_WSI1_PARITY_ERR_COUNT___S 0 +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_AON_RO_WSI1_STAT_1___S 0 + +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG (0x005D40A8) +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_VHT160_MODE_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_RX_GAIN_TYPE_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_RX_GAIN_IDX_CT___POR 0x00 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_CLPC_PKT_TYPE_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_TPC_PDET_GAIN_IDX_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_TPC_ATTEN_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_TX_GAIN_IDX_CT___POR 0x00 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_ANT_SEL_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_TX_EN_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_RX_EN_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_TX_CH_BW_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_RX_CH_BW_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_VHT160_MODE_CT___M 0xC0000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_VHT160_MODE_CT___S 30 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_RX_GAIN_TYPE_CT___M 0x30000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_RX_GAIN_TYPE_CT___S 28 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_RX_GAIN_IDX_CT___M 0x0FE00000 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_RX_GAIN_IDX_CT___S 21 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_CLPC_PKT_TYPE_CT___M 0x00100000 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_CLPC_PKT_TYPE_CT___S 20 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_TPC_PDET_GAIN_IDX_CT___M 0x00080000 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_TPC_PDET_GAIN_IDX_CT___S 19 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_TPC_ATTEN_CT___M 0x00078000 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_TPC_ATTEN_CT___S 15 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_TX_GAIN_IDX_CT___M 0x00007E00 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_TX_GAIN_IDX_CT___S 9 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_ANT_SEL_CT___M 0x00000100 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_ANT_SEL_CT___S 8 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_TX_EN_CT___M 0x00000080 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_TX_EN_CT___S 7 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_RX_EN_CT___M 0x00000040 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_RX_EN_CT___S 6 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_TX_CH_BW_CT___M 0x00000038 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_TX_CH_BW_CT___S 3 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_RX_CH_BW_CT___M 0x00000007 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG__RO_WSI2_RX_CH_BW_CT___S 0 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG___S 0 + +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG_1 (0x005D40AC) +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG_1__RO_WSI2_MAIN_SYN_EN_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG_1__RO_WSI2_LP_SYN_EN_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG_1__RO_WSI2_LP_SYN_SEL_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG_1__RO_WSI2_MAIN_SYN_EN_CT___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG_1__RO_WSI2_MAIN_SYN_EN_CT___S 31 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG_1__RO_WSI2_LP_SYN_EN_CT___M 0x40000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG_1__RO_WSI2_LP_SYN_EN_CT___S 30 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG_1__RO_WSI2_LP_SYN_SEL_CT___M 0x20000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG_1__RO_WSI2_LP_SYN_SEL_CT___S 29 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG_1___M 0xE0000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_MSG_1___S 29 + +#define PHYA_IRON2G_RFA_AON_RO_WSI2_STAT_0 (0x005D40B0) +#define PHYA_IRON2G_RFA_AON_RO_WSI2_STAT_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_RO_WSI2_STAT_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_STAT_0__RO_WSI2_SYNCH_STATE___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_STAT_0__RO_WSI2_RCB_BUSY___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_STAT_0__RO_WSI2_RCB_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_STAT_0__RO_WSI2_RCB_GNT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_STAT_0__RO_WSI2_SYNCH_STATE___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_STAT_0__RO_WSI2_SYNCH_STATE___S 31 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_STAT_0__RO_WSI2_RCB_BUSY___M 0x40000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_STAT_0__RO_WSI2_RCB_BUSY___S 30 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_STAT_0__RO_WSI2_RCB_REQ___M 0x20000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_STAT_0__RO_WSI2_RCB_REQ___S 29 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_STAT_0__RO_WSI2_RCB_GNT___M 0x10000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_STAT_0__RO_WSI2_RCB_GNT___S 28 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_STAT_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI2_STAT_0___S 28 + +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG (0x005D40B4) +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_VHT160_MODE_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_RX_GAIN_TYPE_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_RX_GAIN_IDX_CT___POR 0x00 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_CLPC_PKT_TYPE_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_TPC_PDET_GAIN_IDX_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_TPC_ATTEN_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_TX_GAIN_IDX_CT___POR 0x00 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_ANT_SEL_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_TX_EN_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_RX_EN_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_TX_CH_BW_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_RX_CH_BW_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_VHT160_MODE_CT___M 0xC0000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_VHT160_MODE_CT___S 30 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_RX_GAIN_TYPE_CT___M 0x30000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_RX_GAIN_TYPE_CT___S 28 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_RX_GAIN_IDX_CT___M 0x0FE00000 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_RX_GAIN_IDX_CT___S 21 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_CLPC_PKT_TYPE_CT___M 0x00100000 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_CLPC_PKT_TYPE_CT___S 20 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_TPC_PDET_GAIN_IDX_CT___M 0x00080000 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_TPC_PDET_GAIN_IDX_CT___S 19 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_TPC_ATTEN_CT___M 0x00078000 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_TPC_ATTEN_CT___S 15 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_TX_GAIN_IDX_CT___M 0x00007E00 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_TX_GAIN_IDX_CT___S 9 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_ANT_SEL_CT___M 0x00000100 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_ANT_SEL_CT___S 8 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_TX_EN_CT___M 0x00000080 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_TX_EN_CT___S 7 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_RX_EN_CT___M 0x00000040 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_RX_EN_CT___S 6 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_TX_CH_BW_CT___M 0x00000038 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_TX_CH_BW_CT___S 3 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_RX_CH_BW_CT___M 0x00000007 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG__RO_WSI3_RX_CH_BW_CT___S 0 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG___S 0 + +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG_1 (0x005D40B8) +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG_1__RO_WSI3_MAIN_SYN_EN_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG_1__RO_WSI3_LP_SYN_EN_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG_1__RO_WSI3_LP_SYN_SEL_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG_1__RO_WSI3_MAIN_SYN_EN_CT___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG_1__RO_WSI3_MAIN_SYN_EN_CT___S 31 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG_1__RO_WSI3_LP_SYN_EN_CT___M 0x40000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG_1__RO_WSI3_LP_SYN_EN_CT___S 30 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG_1__RO_WSI3_LP_SYN_SEL_CT___M 0x20000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG_1__RO_WSI3_LP_SYN_SEL_CT___S 29 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG_1___M 0xE0000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_MSG_1___S 29 + +#define PHYA_IRON2G_RFA_AON_RO_WSI3_STAT_0 (0x005D40BC) +#define PHYA_IRON2G_RFA_AON_RO_WSI3_STAT_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_RO_WSI3_STAT_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_STAT_0__RO_WSI3_SYNCH_STATE___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_STAT_0__RO_WSI3_RCB_BUSY___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_STAT_0__RO_WSI3_RCB_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_STAT_0__RO_WSI3_RCB_GNT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_STAT_0__RO_WSI3_SYNCH_STATE___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_STAT_0__RO_WSI3_SYNCH_STATE___S 31 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_STAT_0__RO_WSI3_RCB_BUSY___M 0x40000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_STAT_0__RO_WSI3_RCB_BUSY___S 30 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_STAT_0__RO_WSI3_RCB_REQ___M 0x20000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_STAT_0__RO_WSI3_RCB_REQ___S 29 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_STAT_0__RO_WSI3_RCB_GNT___M 0x10000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_STAT_0__RO_WSI3_RCB_GNT___S 28 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_STAT_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI3_STAT_0___S 28 + +#define PHYA_IRON2G_RFA_AON_RO_WSI_STAT_0 (0x005D40C0) +#define PHYA_IRON2G_RFA_AON_RO_WSI_STAT_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_RO_WSI_STAT_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI_STAT_0__RO_RCB_BUSY_SCMN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI_STAT_0__RO_RCB_BUSY_M0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI_STAT_0__RO_RCB_REQ_M0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI_STAT_0__RO_RCB_GNT_M0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_WSI_STAT_0__RO_RCB_BUSY_SCMN___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI_STAT_0__RO_RCB_BUSY_SCMN___S 31 +#define PHYA_IRON2G_RFA_AON_RO_WSI_STAT_0__RO_RCB_BUSY_M0___M 0x40000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI_STAT_0__RO_RCB_BUSY_M0___S 30 +#define PHYA_IRON2G_RFA_AON_RO_WSI_STAT_0__RO_RCB_REQ_M0___M 0x20000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI_STAT_0__RO_RCB_REQ_M0___S 29 +#define PHYA_IRON2G_RFA_AON_RO_WSI_STAT_0__RO_RCB_GNT_M0___M 0x10000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI_STAT_0__RO_RCB_GNT_M0___S 28 +#define PHYA_IRON2G_RFA_AON_RO_WSI_STAT_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_AON_RO_WSI_STAT_0___S 28 + +#define PHYA_IRON2G_RFA_AON_BUS_MATRIX_CFG (0x005D40C4) +#define PHYA_IRON2G_RFA_AON_BUS_MATRIX_CFG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_BUS_MATRIX_CFG___POR 0x00010000 +#define PHYA_IRON2G_RFA_AON_BUS_MATRIX_CFG__WDT_TIMEOUT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_BUS_MATRIX_CFG__WDT_TIMEOUT_LEVEL___POR 0x1 +#define PHYA_IRON2G_RFA_AON_BUS_MATRIX_CFG__WDT_FLAG_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_AON_BUS_MATRIX_CFG__BUS_REQ_DISABLE___POR 0x00 +#define PHYA_IRON2G_RFA_AON_BUS_MATRIX_CFG__WDT_TIMEOUT_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_BUS_MATRIX_CFG__WDT_TIMEOUT_EN___S 31 +#define PHYA_IRON2G_RFA_AON_BUS_MATRIX_CFG__WDT_TIMEOUT_LEVEL___M 0x00030000 +#define PHYA_IRON2G_RFA_AON_BUS_MATRIX_CFG__WDT_TIMEOUT_LEVEL___S 16 +#define PHYA_IRON2G_RFA_AON_BUS_MATRIX_CFG__WDT_FLAG_RESET___M 0x00000100 +#define PHYA_IRON2G_RFA_AON_BUS_MATRIX_CFG__WDT_FLAG_RESET___S 8 +#define PHYA_IRON2G_RFA_AON_BUS_MATRIX_CFG__BUS_REQ_DISABLE___M 0x000000FF +#define PHYA_IRON2G_RFA_AON_BUS_MATRIX_CFG__BUS_REQ_DISABLE___S 0 +#define PHYA_IRON2G_RFA_AON_BUS_MATRIX_CFG___M 0x800301FF +#define PHYA_IRON2G_RFA_AON_BUS_MATRIX_CFG___S 0 + +#define PHYA_IRON2G_RFA_AON_RO_BUS_MATIRX_STAT (0x005D40C8) +#define PHYA_IRON2G_RFA_AON_RO_BUS_MATIRX_STAT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_RO_BUS_MATIRX_STAT___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RO_BUS_MATIRX_STAT__RO_WDT_TIMEOUT_FLAG___POR 0x00 +#define PHYA_IRON2G_RFA_AON_RO_BUS_MATIRX_STAT__RO_WDT_TIMEOUT___POR 0x00 +#define PHYA_IRON2G_RFA_AON_RO_BUS_MATIRX_STAT__RO_WDT_TIMEOUT_FLAG___M 0x00001F00 +#define PHYA_IRON2G_RFA_AON_RO_BUS_MATIRX_STAT__RO_WDT_TIMEOUT_FLAG___S 8 +#define PHYA_IRON2G_RFA_AON_RO_BUS_MATIRX_STAT__RO_WDT_TIMEOUT___M 0x0000001F +#define PHYA_IRON2G_RFA_AON_RO_BUS_MATIRX_STAT__RO_WDT_TIMEOUT___S 0 +#define PHYA_IRON2G_RFA_AON_RO_BUS_MATIRX_STAT___M 0x00001F1F +#define PHYA_IRON2G_RFA_AON_RO_BUS_MATIRX_STAT___S 0 + +#define PHYA_IRON2G_RFA_AON_LDO_EN (0x005D4100) +#define PHYA_IRON2G_RFA_AON_LDO_EN___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_LDO_EN___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_LDO_EN__LDO_CAL_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_AON_LDO_EN__LDO_CAL_DATA_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_EN__LDO_XO_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_EN__LDO_BTFMPLL_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_EN__LDO_BBPLL_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_EN__LDO_CM_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_EN__LDO_BT_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_EN__LDO_FM_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_EN__LDO_WL_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_EN__LDO_CAL_SEL___M 0xFC000000 +#define PHYA_IRON2G_RFA_AON_LDO_EN__LDO_CAL_SEL___S 26 +#define PHYA_IRON2G_RFA_AON_LDO_EN__LDO_CAL_DATA_SEL___M 0x03000000 +#define PHYA_IRON2G_RFA_AON_LDO_EN__LDO_CAL_DATA_SEL___S 24 +#define PHYA_IRON2G_RFA_AON_LDO_EN__LDO_XO_FC_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_AON_LDO_EN__LDO_XO_FC_OVS___S 14 +#define PHYA_IRON2G_RFA_AON_LDO_EN__LDO_BTFMPLL_FC_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_AON_LDO_EN__LDO_BTFMPLL_FC_OVS___S 12 +#define PHYA_IRON2G_RFA_AON_LDO_EN__LDO_BBPLL_FC_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_AON_LDO_EN__LDO_BBPLL_FC_OVS___S 10 +#define PHYA_IRON2G_RFA_AON_LDO_EN__LDO_CM_FC_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_AON_LDO_EN__LDO_CM_FC_OVS___S 8 +#define PHYA_IRON2G_RFA_AON_LDO_EN__LDO_BT_FC_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_AON_LDO_EN__LDO_BT_FC_OVS___S 6 +#define PHYA_IRON2G_RFA_AON_LDO_EN__LDO_FM_FC_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_AON_LDO_EN__LDO_FM_FC_OVS___S 4 +#define PHYA_IRON2G_RFA_AON_LDO_EN__LDO_WL_FC_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_AON_LDO_EN__LDO_WL_FC_OVS___S 2 +#define PHYA_IRON2G_RFA_AON_LDO_EN___M 0xFF00FFFC +#define PHYA_IRON2G_RFA_AON_LDO_EN___S 2 + +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G (0x005D4104) +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G___POR 0x01940194 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_EN_2G_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_BIAS_FASTCH_2G_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_BIAS_BWRSEL_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_SEL_VREF_2G_CH0___POR 0x3 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_ATBSEL_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_FASTCH_2G_CH0_WSI_SETTIME___POR 0x5 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_EN_2G_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_BIAS_FASTCH_2G_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_BIAS_BWRSEL_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_SEL_VREF_2G_CH1___POR 0x3 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_ATBSEL_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_FASTCH_2G_CH1_WSI_SETTIME___POR 0x5 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_EN_2G_CH0_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_EN_2G_CH0_OVS___S 30 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_BIAS_FASTCH_2G_CH0_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_BIAS_FASTCH_2G_CH0_OVS___S 28 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_BIAS_BWRSEL_2G_CH0___M 0x0C000000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_BIAS_BWRSEL_2G_CH0___S 26 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_SEL_VREF_2G_CH0___M 0x03800000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_SEL_VREF_2G_CH0___S 23 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_ATBSEL_2G_CH0___M 0x00400000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_ATBSEL_2G_CH0___S 22 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_FASTCH_2G_CH0_WSI_SETTIME___M 0x003C0000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_FASTCH_2G_CH0_WSI_SETTIME___S 18 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_EN_2G_CH1_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_EN_2G_CH1_OVS___S 14 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_BIAS_FASTCH_2G_CH1_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_BIAS_FASTCH_2G_CH1_OVS___S 12 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_BIAS_BWRSEL_2G_CH1___M 0x00000C00 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_BIAS_BWRSEL_2G_CH1___S 10 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_SEL_VREF_2G_CH1___M 0x00000380 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_SEL_VREF_2G_CH1___S 7 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_ATBSEL_2G_CH1___M 0x00000040 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__D_LDO_REFGEN_WL_TXRXLO_ATBSEL_2G_CH1___S 6 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_FASTCH_2G_CH1_WSI_SETTIME___M 0x0000003C +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G__LDO_REFGEN_WL_TXRXLO_FASTCH_2G_CH1_WSI_SETTIME___S 2 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G___M 0xFFFCFFFC +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_2G___S 2 + +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G (0x005D4108) +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G___POR 0x01940194 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_EN_5G_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_BIAS_FASTCH_5G_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_BIAS_BWRSEL_5G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_SEL_VREF_5G_CH0___POR 0x3 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_ATBSEL_5G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_FASTCH_5G_CH0_WSI_SETTIME___POR 0x5 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_EN_5G_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_BIAS_FASTCH_5G_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_BIAS_BWRSEL_5G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_SEL_VREF_5G_CH1___POR 0x3 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_ATBSEL_5G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_FASTCH_5G_CH1_WSI_SETTIME___POR 0x5 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_EN_5G_CH0_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_EN_5G_CH0_OVS___S 30 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_BIAS_FASTCH_5G_CH0_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_BIAS_FASTCH_5G_CH0_OVS___S 28 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_BIAS_BWRSEL_5G_CH0___M 0x0C000000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_BIAS_BWRSEL_5G_CH0___S 26 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_SEL_VREF_5G_CH0___M 0x03800000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_SEL_VREF_5G_CH0___S 23 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_ATBSEL_5G_CH0___M 0x00400000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_ATBSEL_5G_CH0___S 22 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_FASTCH_5G_CH0_WSI_SETTIME___M 0x003C0000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_FASTCH_5G_CH0_WSI_SETTIME___S 18 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_EN_5G_CH1_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_EN_5G_CH1_OVS___S 14 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_BIAS_FASTCH_5G_CH1_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_BIAS_FASTCH_5G_CH1_OVS___S 12 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_BIAS_BWRSEL_5G_CH1___M 0x00000C00 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_BIAS_BWRSEL_5G_CH1___S 10 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_SEL_VREF_5G_CH1___M 0x00000380 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_SEL_VREF_5G_CH1___S 7 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_ATBSEL_5G_CH1___M 0x00000040 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__D_LDO_REFGEN_WL_TXRXLO_ATBSEL_5G_CH1___S 6 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_FASTCH_5G_CH1_WSI_SETTIME___M 0x0000003C +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G__LDO_REFGEN_WL_TXRXLO_FASTCH_5G_CH1_WSI_SETTIME___S 2 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G___M 0xFFFCFFFC +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_TXRXLO_5G___S 2 + +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G (0x005D410C) +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G___POR 0x00800080 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__LDO_WL_RXLO_EN_2G_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__LDO_WL_RXLO_BIAS_EN_2G_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_BYPASS_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_LEAKER_ON_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_OTA_CUR_2G_CH0___POR 0x1 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_ATBSEL_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__LDO_WL_RXLO_EN_2G_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__LDO_WL_RXLO_BIAS_EN_2G_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_BYPASS_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_LEAKER_ON_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_OTA_CUR_2G_CH1___POR 0x1 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_ATBSEL_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__LDO_WL_RXLO_EN_2G_CH0_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__LDO_WL_RXLO_EN_2G_CH0_OVS___S 30 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__LDO_WL_RXLO_BIAS_EN_2G_CH0_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__LDO_WL_RXLO_BIAS_EN_2G_CH0_OVS___S 28 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_BYPASS_2G_CH0___M 0x08000000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_BYPASS_2G_CH0___S 27 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_LEAKER_ON_2G_CH0___M 0x04000000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_LEAKER_ON_2G_CH0___S 26 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_OTA_CUR_2G_CH0___M 0x03800000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_OTA_CUR_2G_CH0___S 23 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_ATBSEL_2G_CH0___M 0x00400000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_ATBSEL_2G_CH0___S 22 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__LDO_WL_RXLO_EN_2G_CH1_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__LDO_WL_RXLO_EN_2G_CH1_OVS___S 14 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__LDO_WL_RXLO_BIAS_EN_2G_CH1_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__LDO_WL_RXLO_BIAS_EN_2G_CH1_OVS___S 12 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_BYPASS_2G_CH1___M 0x00000800 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_BYPASS_2G_CH1___S 11 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_LEAKER_ON_2G_CH1___M 0x00000400 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_LEAKER_ON_2G_CH1___S 10 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_OTA_CUR_2G_CH1___M 0x00000380 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_OTA_CUR_2G_CH1___S 7 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_ATBSEL_2G_CH1___M 0x00000040 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G__D_LDO_WL_RXLO_ATBSEL_2G_CH1___S 6 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G___M 0xFFC0FFC0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_2G___S 6 + +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G (0x005D4110) +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G___POR 0x00800080 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__LDO_WL_RXLO_EN_5G_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__LDO_WL_RXLO_BIAS_EN_5G_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_BYPASS_5G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_LEAKER_ON_5G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_OTA_CUR_5G_CH0___POR 0x1 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_ATBSEL_5G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__LDO_WL_RXLO_EN_5G_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__LDO_WL_RXLO_BIAS_EN_5G_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_BYPASS_5G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_LEAKER_ON_5G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_OTA_CUR_5G_CH1___POR 0x1 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_ATBSEL_5G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__LDO_WL_RXLO_EN_5G_CH0_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__LDO_WL_RXLO_EN_5G_CH0_OVS___S 30 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__LDO_WL_RXLO_BIAS_EN_5G_CH0_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__LDO_WL_RXLO_BIAS_EN_5G_CH0_OVS___S 28 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_BYPASS_5G_CH0___M 0x08000000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_BYPASS_5G_CH0___S 27 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_LEAKER_ON_5G_CH0___M 0x04000000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_LEAKER_ON_5G_CH0___S 26 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_OTA_CUR_5G_CH0___M 0x03800000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_OTA_CUR_5G_CH0___S 23 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_ATBSEL_5G_CH0___M 0x00400000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_ATBSEL_5G_CH0___S 22 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__LDO_WL_RXLO_EN_5G_CH1_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__LDO_WL_RXLO_EN_5G_CH1_OVS___S 14 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__LDO_WL_RXLO_BIAS_EN_5G_CH1_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__LDO_WL_RXLO_BIAS_EN_5G_CH1_OVS___S 12 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_BYPASS_5G_CH1___M 0x00000800 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_BYPASS_5G_CH1___S 11 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_LEAKER_ON_5G_CH1___M 0x00000400 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_LEAKER_ON_5G_CH1___S 10 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_OTA_CUR_5G_CH1___M 0x00000380 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_OTA_CUR_5G_CH1___S 7 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_ATBSEL_5G_CH1___M 0x00000040 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G__D_LDO_WL_RXLO_ATBSEL_5G_CH1___S 6 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G___M 0xFFC0FFC0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_RXLO_5G___S 6 + +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G (0x005D4114) +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G___POR 0x00A000A0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_BIAS_EN_2G_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_BYPASS_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_LEAKER_ON_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_OTA_CUR_2G_CH0___POR 0x1 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_ATBSEL_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH0_SEL___POR 0x1 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_BIAS_EN_2G_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_BYPASS_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_LEAKER_ON_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_OTA_CUR_2G_CH1___POR 0x1 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_ATBSEL_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH1_SEL___POR 0x1 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH0_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH0_OVS___S 30 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_BIAS_EN_2G_CH0_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_BIAS_EN_2G_CH0_OVS___S 28 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_BYPASS_2G_CH0___M 0x08000000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_BYPASS_2G_CH0___S 27 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_LEAKER_ON_2G_CH0___M 0x04000000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_LEAKER_ON_2G_CH0___S 26 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_OTA_CUR_2G_CH0___M 0x03800000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_OTA_CUR_2G_CH0___S 23 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_ATBSEL_2G_CH0___M 0x00400000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_ATBSEL_2G_CH0___S 22 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH0_SEL___M 0x00200000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH0_SEL___S 21 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH1_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH1_OVS___S 14 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_BIAS_EN_2G_CH1_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_BIAS_EN_2G_CH1_OVS___S 12 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_BYPASS_2G_CH1___M 0x00000800 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_BYPASS_2G_CH1___S 11 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_LEAKER_ON_2G_CH1___M 0x00000400 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_LEAKER_ON_2G_CH1___S 10 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_OTA_CUR_2G_CH1___M 0x00000380 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_OTA_CUR_2G_CH1___S 7 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_ATBSEL_2G_CH1___M 0x00000040 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__D_LDO_WL_TXLO_ATBSEL_2G_CH1___S 6 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH1_SEL___M 0x00000020 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G__LDO_WL_TXLO_EN_2G_CH1_SEL___S 5 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G___M 0xFFE0FFE0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_2G___S 5 + +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G (0x005D4118) +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G___POR 0x00A000A0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_BIAS_EN_5G_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_BYPASS_5G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_LEAKER_ON_5G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_OTA_CUR_5G_CH0___POR 0x1 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_ATBSEL_5G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH0_SEL___POR 0x1 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_BIAS_EN_5G_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_BYPASS_5G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_LEAKER_ON_5G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_OTA_CUR_5G_CH1___POR 0x1 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_ATBSEL_5G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH1_SEL___POR 0x1 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH0_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH0_OVS___S 30 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_BIAS_EN_5G_CH0_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_BIAS_EN_5G_CH0_OVS___S 28 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_BYPASS_5G_CH0___M 0x08000000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_BYPASS_5G_CH0___S 27 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_LEAKER_ON_5G_CH0___M 0x04000000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_LEAKER_ON_5G_CH0___S 26 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_OTA_CUR_5G_CH0___M 0x03800000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_OTA_CUR_5G_CH0___S 23 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_ATBSEL_5G_CH0___M 0x00400000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_ATBSEL_5G_CH0___S 22 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH0_SEL___M 0x00200000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH0_SEL___S 21 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH1_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH1_OVS___S 14 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_BIAS_EN_5G_CH1_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_BIAS_EN_5G_CH1_OVS___S 12 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_BYPASS_5G_CH1___M 0x00000800 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_BYPASS_5G_CH1___S 11 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_LEAKER_ON_5G_CH1___M 0x00000400 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_LEAKER_ON_5G_CH1___S 10 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_OTA_CUR_5G_CH1___M 0x00000380 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_OTA_CUR_5G_CH1___S 7 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_ATBSEL_5G_CH1___M 0x00000040 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__D_LDO_WL_TXLO_ATBSEL_5G_CH1___S 6 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH1_SEL___M 0x00000020 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G__LDO_WL_TXLO_EN_5G_CH1_SEL___S 5 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G___M 0xFFE0FFE0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_TXLO_5G___S 5 + +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G (0x005D411C) +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G___POR 0x01800180 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__LDO_REFGEN_WL_DAC_EN_2G_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__LDO_REFGEN_WL_DAC_BIAS_FASTCH_2G_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_BIAS_BWRSEL_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_SEL_VREF_2G_CH0___POR 0x3 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_ATBSEL_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__LDO_REFGEN_WL_DAC_EN_2G_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__LDO_REFGEN_WL_DAC_BIAS_FASTCH_2G_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_BIAS_BWRSEL_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_SEL_VREF_2G_CH1___POR 0x3 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_ATBSEL_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__LDO_REFGEN_WL_DAC_EN_2G_CH0_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__LDO_REFGEN_WL_DAC_EN_2G_CH0_OVS___S 30 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__LDO_REFGEN_WL_DAC_BIAS_FASTCH_2G_CH0_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__LDO_REFGEN_WL_DAC_BIAS_FASTCH_2G_CH0_OVS___S 28 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_BIAS_BWRSEL_2G_CH0___M 0x0C000000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_BIAS_BWRSEL_2G_CH0___S 26 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_SEL_VREF_2G_CH0___M 0x03800000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_SEL_VREF_2G_CH0___S 23 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_ATBSEL_2G_CH0___M 0x00400000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_ATBSEL_2G_CH0___S 22 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__LDO_REFGEN_WL_DAC_EN_2G_CH1_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__LDO_REFGEN_WL_DAC_EN_2G_CH1_OVS___S 14 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__LDO_REFGEN_WL_DAC_BIAS_FASTCH_2G_CH1_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__LDO_REFGEN_WL_DAC_BIAS_FASTCH_2G_CH1_OVS___S 12 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_BIAS_BWRSEL_2G_CH1___M 0x00000C00 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_BIAS_BWRSEL_2G_CH1___S 10 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_SEL_VREF_2G_CH1___M 0x00000380 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_SEL_VREF_2G_CH1___S 7 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_ATBSEL_2G_CH1___M 0x00000040 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G__D_LDO_REFGEN_WL_DAC_ATBSEL_2G_CH1___S 6 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G___M 0xFFC0FFC0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_2G___S 6 + +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G (0x005D4120) +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G___POR 0x01800180 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__LDO_REFGEN_WL_DAC_EN_5G_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__LDO_REFGEN_WL_DAC_BIAS_FASTCH_5G_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_BIAS_BWRSEL_5G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_SEL_VREF_5G_CH0___POR 0x3 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_ATBSEL_5G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__LDO_REFGEN_WL_DAC_EN_5G_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__LDO_REFGEN_WL_DAC_BIAS_FASTCH_5G_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_BIAS_BWRSEL_5G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_SEL_VREF_5G_CH1___POR 0x3 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_ATBSEL_5G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__LDO_REFGEN_WL_DAC_EN_5G_CH0_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__LDO_REFGEN_WL_DAC_EN_5G_CH0_OVS___S 30 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__LDO_REFGEN_WL_DAC_BIAS_FASTCH_5G_CH0_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__LDO_REFGEN_WL_DAC_BIAS_FASTCH_5G_CH0_OVS___S 28 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_BIAS_BWRSEL_5G_CH0___M 0x0C000000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_BIAS_BWRSEL_5G_CH0___S 26 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_SEL_VREF_5G_CH0___M 0x03800000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_SEL_VREF_5G_CH0___S 23 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_ATBSEL_5G_CH0___M 0x00400000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_ATBSEL_5G_CH0___S 22 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__LDO_REFGEN_WL_DAC_EN_5G_CH1_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__LDO_REFGEN_WL_DAC_EN_5G_CH1_OVS___S 14 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__LDO_REFGEN_WL_DAC_BIAS_FASTCH_5G_CH1_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__LDO_REFGEN_WL_DAC_BIAS_FASTCH_5G_CH1_OVS___S 12 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_BIAS_BWRSEL_5G_CH1___M 0x00000C00 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_BIAS_BWRSEL_5G_CH1___S 10 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_SEL_VREF_5G_CH1___M 0x00000380 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_SEL_VREF_5G_CH1___S 7 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_ATBSEL_5G_CH1___M 0x00000040 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G__D_LDO_REFGEN_WL_DAC_ATBSEL_5G_CH1___S 6 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G___M 0xFFC0FFC0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_DAC_5G___S 6 + +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G (0x005D4124) +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G___POR 0x02000200 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__LDO_WL_DAC_EN_2G_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__LDO_WL_DAC_BIAS_EN_2G_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_BYPASS_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_LEAKER_ON_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_OTA_CUR_2G_CH0___POR 0x4 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_ATBSEL_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__LDO_WL_DAC_EN_2G_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__LDO_WL_DAC_BIAS_EN_2G_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_BYPASS_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_LEAKER_ON_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_OTA_CUR_2G_CH1___POR 0x4 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_ATBSEL_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__LDO_WL_DAC_EN_2G_CH0_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__LDO_WL_DAC_EN_2G_CH0_OVS___S 30 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__LDO_WL_DAC_BIAS_EN_2G_CH0_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__LDO_WL_DAC_BIAS_EN_2G_CH0_OVS___S 28 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_BYPASS_2G_CH0___M 0x08000000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_BYPASS_2G_CH0___S 27 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_LEAKER_ON_2G_CH0___M 0x04000000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_LEAKER_ON_2G_CH0___S 26 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_OTA_CUR_2G_CH0___M 0x03800000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_OTA_CUR_2G_CH0___S 23 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_ATBSEL_2G_CH0___M 0x00400000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_ATBSEL_2G_CH0___S 22 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__LDO_WL_DAC_EN_2G_CH1_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__LDO_WL_DAC_EN_2G_CH1_OVS___S 14 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__LDO_WL_DAC_BIAS_EN_2G_CH1_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__LDO_WL_DAC_BIAS_EN_2G_CH1_OVS___S 12 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_BYPASS_2G_CH1___M 0x00000800 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_BYPASS_2G_CH1___S 11 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_LEAKER_ON_2G_CH1___M 0x00000400 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_LEAKER_ON_2G_CH1___S 10 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_OTA_CUR_2G_CH1___M 0x00000380 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_OTA_CUR_2G_CH1___S 7 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_ATBSEL_2G_CH1___M 0x00000040 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G__D_LDO_WL_DAC_ATBSEL_2G_CH1___S 6 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G___M 0xFFC0FFC0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_2G___S 6 + +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G (0x005D4128) +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G___POR 0x02000200 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__LDO_WL_DAC_EN_5G_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__LDO_WL_DAC_BIAS_EN_5G_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_BYPASS_5G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_LEAKER_ON_5G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_OTA_CUR_5G_CH0___POR 0x4 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_ATBSEL_5G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__LDO_WL_DAC_EN_5G_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__LDO_WL_DAC_BIAS_EN_5G_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_BYPASS_5G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_LEAKER_ON_5G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_OTA_CUR_5G_CH1___POR 0x4 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_ATBSEL_5G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__LDO_WL_DAC_EN_5G_CH0_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__LDO_WL_DAC_EN_5G_CH0_OVS___S 30 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__LDO_WL_DAC_BIAS_EN_5G_CH0_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__LDO_WL_DAC_BIAS_EN_5G_CH0_OVS___S 28 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_BYPASS_5G_CH0___M 0x08000000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_BYPASS_5G_CH0___S 27 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_LEAKER_ON_5G_CH0___M 0x04000000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_LEAKER_ON_5G_CH0___S 26 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_OTA_CUR_5G_CH0___M 0x03800000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_OTA_CUR_5G_CH0___S 23 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_ATBSEL_5G_CH0___M 0x00400000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_ATBSEL_5G_CH0___S 22 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__LDO_WL_DAC_EN_5G_CH1_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__LDO_WL_DAC_EN_5G_CH1_OVS___S 14 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__LDO_WL_DAC_BIAS_EN_5G_CH1_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__LDO_WL_DAC_BIAS_EN_5G_CH1_OVS___S 12 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_BYPASS_5G_CH1___M 0x00000800 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_BYPASS_5G_CH1___S 11 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_LEAKER_ON_5G_CH1___M 0x00000400 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_LEAKER_ON_5G_CH1___S 10 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_OTA_CUR_5G_CH1___M 0x00000380 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_OTA_CUR_5G_CH1___S 7 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_ATBSEL_5G_CH1___M 0x00000040 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G__D_LDO_WL_DAC_ATBSEL_5G_CH1___S 6 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G___M 0xFFC0FFC0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_DAC_5G___S 6 + +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC (0x005D412C) +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__LDO_REFGEN_WL_ADC_EN_2G_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_BYPASS_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_SEL_VREF_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__LDO_REFGEN_WL_ADC_EN_2G_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_BYPASS_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_SEL_VREF_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__LDO_REFGEN_WL_ADC_EN_5G_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_BYPASS_5G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_SEL_VREF_5G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__LDO_REFGEN_WL_ADC_EN_5G_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_BYPASS_5G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_SEL_VREF_5G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__LDO_REFGEN_WL_ADC_EN_2G_CH0_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__LDO_REFGEN_WL_ADC_EN_2G_CH0_OVS___S 30 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_BYPASS_2G_CH0___M 0x20000000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_BYPASS_2G_CH0___S 29 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_SEL_VREF_2G_CH0___M 0x1C000000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_SEL_VREF_2G_CH0___S 26 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__LDO_REFGEN_WL_ADC_EN_2G_CH1_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__LDO_REFGEN_WL_ADC_EN_2G_CH1_OVS___S 22 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_BYPASS_2G_CH1___M 0x00200000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_BYPASS_2G_CH1___S 21 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_SEL_VREF_2G_CH1___M 0x001C0000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_SEL_VREF_2G_CH1___S 18 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__LDO_REFGEN_WL_ADC_EN_5G_CH0_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__LDO_REFGEN_WL_ADC_EN_5G_CH0_OVS___S 14 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_BYPASS_5G_CH0___M 0x00002000 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_BYPASS_5G_CH0___S 13 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_SEL_VREF_5G_CH0___M 0x00001C00 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_SEL_VREF_5G_CH0___S 10 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__LDO_REFGEN_WL_ADC_EN_5G_CH1_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__LDO_REFGEN_WL_ADC_EN_5G_CH1_OVS___S 6 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_BYPASS_5G_CH1___M 0x00000020 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_BYPASS_5G_CH1___S 5 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_SEL_VREF_5G_CH1___M 0x0000001C +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC__D_LDO_REFGEN_WL_ADC_SEL_VREF_5G_CH1___S 2 +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC___M 0xFCFCFCFC +#define PHYA_IRON2G_RFA_AON_LDO_REFGEN_WL_ADC___S 2 + +#define PHYA_IRON2G_RFA_AON_LDO_WL_ADC (0x005D4130) +#define PHYA_IRON2G_RFA_AON_LDO_WL_ADC___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_LDO_WL_ADC___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_ADC__LDO_WL_ADC_EN_2G_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_ADC__D_LDO_WL_ADC_BYPASS_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_ADC__LDO_WL_ADC_EN_2G_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_ADC__D_LDO_WL_ADC_BYPASS_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_ADC__LDO_WL_ADC_EN_5G_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_ADC__D_LDO_WL_ADC_BYPASS_5G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_ADC__LDO_WL_ADC_EN_5G_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_ADC__D_LDO_WL_ADC_BYPASS_5G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_ADC__LDO_WL_ADC_EN_2G_CH0_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_ADC__LDO_WL_ADC_EN_2G_CH0_OVS___S 30 +#define PHYA_IRON2G_RFA_AON_LDO_WL_ADC__D_LDO_WL_ADC_BYPASS_2G_CH0___M 0x10000000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_ADC__D_LDO_WL_ADC_BYPASS_2G_CH0___S 28 +#define PHYA_IRON2G_RFA_AON_LDO_WL_ADC__LDO_WL_ADC_EN_2G_CH1_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_ADC__LDO_WL_ADC_EN_2G_CH1_OVS___S 22 +#define PHYA_IRON2G_RFA_AON_LDO_WL_ADC__D_LDO_WL_ADC_BYPASS_2G_CH1___M 0x00200000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_ADC__D_LDO_WL_ADC_BYPASS_2G_CH1___S 21 +#define PHYA_IRON2G_RFA_AON_LDO_WL_ADC__LDO_WL_ADC_EN_5G_CH0_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_ADC__LDO_WL_ADC_EN_5G_CH0_OVS___S 14 +#define PHYA_IRON2G_RFA_AON_LDO_WL_ADC__D_LDO_WL_ADC_BYPASS_5G_CH0___M 0x00002000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_ADC__D_LDO_WL_ADC_BYPASS_5G_CH0___S 13 +#define PHYA_IRON2G_RFA_AON_LDO_WL_ADC__LDO_WL_ADC_EN_5G_CH1_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_ADC__LDO_WL_ADC_EN_5G_CH1_OVS___S 6 +#define PHYA_IRON2G_RFA_AON_LDO_WL_ADC__D_LDO_WL_ADC_BYPASS_5G_CH1___M 0x00000020 +#define PHYA_IRON2G_RFA_AON_LDO_WL_ADC__D_LDO_WL_ADC_BYPASS_5G_CH1___S 5 +#define PHYA_IRON2G_RFA_AON_LDO_WL_ADC___M 0xD0E0E0E0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_ADC___S 5 + +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM (0x005D4134) +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM___POR 0x03608000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__LDO_REFGEN_WL_SYNTH2_SDM_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__D_LDO_REFGEN_WL_SYNTH2_SDM_ISEL_IR12P5___POR 0x3 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__D_LDO_REFGEN_WL_SYNTH2_SDM_ISEL_IC25___POR 0x3 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__LDO_WL_SYNTH2_SDM_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__D_LDO_WL_SYNTH2_SDM_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__D_LDO_WL_SYNTH2_SDM_OTA_CUR___POR 0x1 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__LDO_REFGEN_WL_SYNTH2_SDM_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__LDO_REFGEN_WL_SYNTH2_SDM_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__D_LDO_REFGEN_WL_SYNTH2_SDM_ISEL_IR12P5___M 0x07000000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__D_LDO_REFGEN_WL_SYNTH2_SDM_ISEL_IR12P5___S 24 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__D_LDO_REFGEN_WL_SYNTH2_SDM_ISEL_IC25___M 0x00E00000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__D_LDO_REFGEN_WL_SYNTH2_SDM_ISEL_IC25___S 21 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__LDO_WL_SYNTH2_SDM_EN_OVS___M 0x00180000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__LDO_WL_SYNTH2_SDM_EN_OVS___S 19 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__D_LDO_WL_SYNTH2_SDM_BYPASS___M 0x00040000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__D_LDO_WL_SYNTH2_SDM_BYPASS___S 18 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__D_LDO_WL_SYNTH2_SDM_OTA_CUR___M 0x00038000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM__D_LDO_WL_SYNTH2_SDM_OTA_CUR___S 15 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM___M 0xC7FF8000 +#define PHYA_IRON2G_RFA_AON_LDO_WL_SYNTH2_SDM___S 15 + +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO (0x005D4138) +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO___POR 0x01802000 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__LDO_REFGEN_BT_TXLO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__LDO_REFGEN_BT_TXLO_BIAS_FASTCH_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_REFGEN_BT_TXLO_BIAS_BWRSEL___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_REFGEN_BT_TXLO_SEL_VREF___POR 0x3 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_REFGEN_BT_TXLO_ATBSEL___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__LDO_BT_TXLO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__LDO_BT_TXLO_BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_BT_TXLO_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_BT_TXLO_LEAKER_ON___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_BT_TXLO_OTA_CUR___POR 0x1 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_BT_TXLO_ATBSEL___POR 0x0 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__LDO_REFGEN_BT_TXLO_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__LDO_REFGEN_BT_TXLO_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__LDO_REFGEN_BT_TXLO_BIAS_FASTCH_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__LDO_REFGEN_BT_TXLO_BIAS_FASTCH_OVS___S 28 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_REFGEN_BT_TXLO_BIAS_BWRSEL___M 0x0C000000 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_REFGEN_BT_TXLO_BIAS_BWRSEL___S 26 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_REFGEN_BT_TXLO_SEL_VREF___M 0x03800000 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_REFGEN_BT_TXLO_SEL_VREF___S 23 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_REFGEN_BT_TXLO_ATBSEL___M 0x00400000 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_REFGEN_BT_TXLO_ATBSEL___S 22 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__LDO_BT_TXLO_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__LDO_BT_TXLO_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__LDO_BT_TXLO_BIAS_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__LDO_BT_TXLO_BIAS_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_BT_TXLO_BYPASS___M 0x00020000 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_BT_TXLO_BYPASS___S 17 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_BT_TXLO_LEAKER_ON___M 0x00010000 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_BT_TXLO_LEAKER_ON___S 16 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_BT_TXLO_OTA_CUR___M 0x0000E000 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_BT_TXLO_OTA_CUR___S 13 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_BT_TXLO_ATBSEL___M 0x00001000 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO__D_LDO_BT_TXLO_ATBSEL___S 12 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_AON_LDO_BT_TXLO___S 12 + +#define PHYA_IRON2G_RFA_AON_TOP_0 (0x005D4140) +#define PHYA_IRON2G_RFA_AON_TOP_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_TOP_0___POR 0x31848948 +#define PHYA_IRON2G_RFA_AON_TOP_0__TOP_T_STARTUP___POR 0x0 +#define PHYA_IRON2G_RFA_AON_TOP_0__TOP_T_STARTUP_WIDTH___POR 0x3 +#define PHYA_IRON2G_RFA_AON_TOP_0__TOP_UT_STARTUP___POR 0x0 +#define PHYA_IRON2G_RFA_AON_TOP_0__TOP_UT_STARTUP_WIDTH___POR 0x3 +#define PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_BGT_START_WIDTH___POR 0x2 +#define PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_BGT_END_WIDTH___POR 0x2 +#define PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_BGU_START_WIDTH___POR 0x1 +#define PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_BGU_END_WIDTH___POR 0x1 +#define PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_PTT_START_WIDTH___POR 0x2 +#define PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_PTT_END_WIDTH___POR 0x2 +#define PHYA_IRON2G_RFA_AON_TOP_0__D_TOP_BGT_STARTUP_CAL_EN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_TOP_0__D_TOP_BGU_STARTUP_CAL_EN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_TOP_0__TOP_T_STARTUP___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_TOP_0__TOP_T_STARTUP___S 31 +#define PHYA_IRON2G_RFA_AON_TOP_0__TOP_T_STARTUP_WIDTH___M 0x70000000 +#define PHYA_IRON2G_RFA_AON_TOP_0__TOP_T_STARTUP_WIDTH___S 28 +#define PHYA_IRON2G_RFA_AON_TOP_0__TOP_UT_STARTUP___M 0x08000000 +#define PHYA_IRON2G_RFA_AON_TOP_0__TOP_UT_STARTUP___S 27 +#define PHYA_IRON2G_RFA_AON_TOP_0__TOP_UT_STARTUP_WIDTH___M 0x07800000 +#define PHYA_IRON2G_RFA_AON_TOP_0__TOP_UT_STARTUP_WIDTH___S 23 +#define PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_BGT_START_WIDTH___M 0x000E0000 +#define PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_BGT_START_WIDTH___S 17 +#define PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_BGT_END_WIDTH___M 0x0001C000 +#define PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_BGT_END_WIDTH___S 14 +#define PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_BGU_START_WIDTH___M 0x00003800 +#define PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_BGU_START_WIDTH___S 11 +#define PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_BGU_END_WIDTH___M 0x00000700 +#define PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_BGU_END_WIDTH___S 8 +#define PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_PTT_START_WIDTH___M 0x000000E0 +#define PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_PTT_START_WIDTH___S 5 +#define PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_PTT_END_WIDTH___M 0x0000001C +#define PHYA_IRON2G_RFA_AON_TOP_0__TOP_FC_PULSE_PTT_END_WIDTH___S 2 +#define PHYA_IRON2G_RFA_AON_TOP_0__D_TOP_BGT_STARTUP_CAL_EN___M 0x00000002 +#define PHYA_IRON2G_RFA_AON_TOP_0__D_TOP_BGT_STARTUP_CAL_EN___S 1 +#define PHYA_IRON2G_RFA_AON_TOP_0__D_TOP_BGU_STARTUP_CAL_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_AON_TOP_0__D_TOP_BGU_STARTUP_CAL_EN___S 0 +#define PHYA_IRON2G_RFA_AON_TOP_0___M 0xFF8FFFFF +#define PHYA_IRON2G_RFA_AON_TOP_0___S 0 + +#define PHYA_IRON2G_RFA_AON_TOP_1 (0x005D4144) +#define PHYA_IRON2G_RFA_AON_TOP_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_TOP_1___POR 0x0000207E +#define PHYA_IRON2G_RFA_AON_TOP_1__TOP_PTT_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_TOP_1__TOP_BGT_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_TOP_1__TOP_BGU_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_TOP_1__TOP_T_STARTUP_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_TOP_1__TOP_UT_STARTUP_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_TOP_1__TOP_FC_PULSE_BGT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_TOP_1__TOP_FC_PULSE_BGU_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_TOP_1__TOP_FC_PULSE_PTT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_EN_MBIAS_RINT___POR 0x1 +#define PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_EN_MBIAS_RTUNER___POR 0x0 +#define PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_ICTRL_T___POR 0x0 +#define PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_BGT_TEST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_BGU_TEST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_PTT_TEST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_TOP_1__D_BGT_EN___POR 0x3F +#define PHYA_IRON2G_RFA_AON_TOP_1__TOP_PTT_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_AON_TOP_1__TOP_PTT_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_AON_TOP_1__TOP_BGT_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_AON_TOP_1__TOP_BGT_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_AON_TOP_1__TOP_BGU_EN_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_AON_TOP_1__TOP_BGU_EN_OVS___S 24 +#define PHYA_IRON2G_RFA_AON_TOP_1__TOP_T_STARTUP_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_AON_TOP_1__TOP_T_STARTUP_OVS___S 22 +#define PHYA_IRON2G_RFA_AON_TOP_1__TOP_UT_STARTUP_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_AON_TOP_1__TOP_UT_STARTUP_OVS___S 20 +#define PHYA_IRON2G_RFA_AON_TOP_1__TOP_FC_PULSE_BGT_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_AON_TOP_1__TOP_FC_PULSE_BGT_OVS___S 18 +#define PHYA_IRON2G_RFA_AON_TOP_1__TOP_FC_PULSE_BGU_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_AON_TOP_1__TOP_FC_PULSE_BGU_OVS___S 16 +#define PHYA_IRON2G_RFA_AON_TOP_1__TOP_FC_PULSE_PTT_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_AON_TOP_1__TOP_FC_PULSE_PTT_OVS___S 14 +#define PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_EN_MBIAS_RINT___M 0x00002000 +#define PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_EN_MBIAS_RINT___S 13 +#define PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_EN_MBIAS_RTUNER___M 0x00001000 +#define PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_EN_MBIAS_RTUNER___S 12 +#define PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_ICTRL_T___M 0x00000800 +#define PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_ICTRL_T___S 11 +#define PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_BGT_TEST_EN___M 0x00000400 +#define PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_BGT_TEST_EN___S 10 +#define PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_BGU_TEST_EN___M 0x00000200 +#define PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_BGU_TEST_EN___S 9 +#define PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_PTT_TEST_EN___M 0x00000100 +#define PHYA_IRON2G_RFA_AON_TOP_1__D_TOP_PTT_TEST_EN___S 8 +#define PHYA_IRON2G_RFA_AON_TOP_1__D_BGT_EN___M 0x000000FE +#define PHYA_IRON2G_RFA_AON_TOP_1__D_BGT_EN___S 1 +#define PHYA_IRON2G_RFA_AON_TOP_1___M 0x3FFFFFFE +#define PHYA_IRON2G_RFA_AON_TOP_1___S 1 + +#define PHYA_IRON2G_RFA_AON_TOP_2 (0x005D4148) +#define PHYA_IRON2G_RFA_AON_TOP_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_TOP_2___POR 0x7EFE1000 +#define PHYA_IRON2G_RFA_AON_TOP_2__D_PTT_EN___POR 0x3F +#define PHYA_IRON2G_RFA_AON_TOP_2__D_BGU_EN___POR 0x3F +#define PHYA_IRON2G_RFA_AON_TOP_2__D_MBIAS_BGT_IDAC___POR 0x8 +#define PHYA_IRON2G_RFA_AON_TOP_2__D_MBIAS_HSW_ANA_EN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_TOP_2__D_MBIAS_HSW_DIG_EN___POR 0x1 +#define PHYA_IRON2G_RFA_AON_TOP_2__D_PTT_EN___M 0xFE000000 +#define PHYA_IRON2G_RFA_AON_TOP_2__D_PTT_EN___S 25 +#define PHYA_IRON2G_RFA_AON_TOP_2__D_BGU_EN___M 0x01FC0000 +#define PHYA_IRON2G_RFA_AON_TOP_2__D_BGU_EN___S 18 +#define PHYA_IRON2G_RFA_AON_TOP_2__D_MBIAS_BGT_IDAC___M 0x0003C000 +#define PHYA_IRON2G_RFA_AON_TOP_2__D_MBIAS_BGT_IDAC___S 14 +#define PHYA_IRON2G_RFA_AON_TOP_2__D_MBIAS_HSW_ANA_EN___M 0x00002000 +#define PHYA_IRON2G_RFA_AON_TOP_2__D_MBIAS_HSW_ANA_EN___S 13 +#define PHYA_IRON2G_RFA_AON_TOP_2__D_MBIAS_HSW_DIG_EN___M 0x00001000 +#define PHYA_IRON2G_RFA_AON_TOP_2__D_MBIAS_HSW_DIG_EN___S 12 +#define PHYA_IRON2G_RFA_AON_TOP_2___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_AON_TOP_2___S 12 + +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS (0x005D414C) +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS___POR 0x16000000 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_EN_MODE_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_CTRL_MODE_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__SHRD_BIAS_MODE_2G_CH0___POR 0x1 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_EN_MODE_2G_CH1___POR 0x1 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_CTRL_MODE_2G_CH1___POR 0x1 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__SHRD_BIAS_MODE_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_EN_MODE_2G_CH0___M 0x40000000 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_EN_MODE_2G_CH0___S 30 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_CTRL_MODE_2G_CH0___M 0x20000000 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_CTRL_MODE_2G_CH0___S 29 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__SHRD_BIAS_MODE_2G_CH0___M 0x10000000 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__SHRD_BIAS_MODE_2G_CH0___S 28 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_EN_MODE_2G_CH1___M 0x04000000 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_EN_MODE_2G_CH1___S 26 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_CTRL_MODE_2G_CH1___M 0x02000000 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__CHAIN_BIAS_CTRL_MODE_2G_CH1___S 25 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__SHRD_BIAS_MODE_2G_CH1___M 0x01000000 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS__SHRD_BIAS_MODE_2G_CH1___S 24 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS___M 0x77000000 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS___S 24 + +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV (0x005D4150) +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WL_CURRENT_BIAS_EN_2G_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WL_CURRENT_BIAS_EN_2G_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WL_CURRENT_BIAS_EN_5G_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WL_CURRENT_BIAS_EN_5G_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_ISEL_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_ISEL_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_TX_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_TX_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_RX_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_RX_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WL_CURRENT_BIAS_EN_2G_CH0_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WL_CURRENT_BIAS_EN_2G_CH0_OVS___S 30 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WL_CURRENT_BIAS_EN_2G_CH1_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WL_CURRENT_BIAS_EN_2G_CH1_OVS___S 28 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WL_CURRENT_BIAS_EN_5G_CH0_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WL_CURRENT_BIAS_EN_5G_CH0_OVS___S 26 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WL_CURRENT_BIAS_EN_5G_CH1_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WL_CURRENT_BIAS_EN_5G_CH1_OVS___S 24 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_ISEL_CH0_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_ISEL_CH0_OVS___S 22 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_ISEL_CH1_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_ISEL_CH1_OVS___S 20 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_TX_CH0_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_TX_CH0_OVS___S 18 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_TX_CH1_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_TX_CH1_OVS___S 16 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_RX_CH0_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_RX_CH0_OVS___S 14 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_RX_CH1_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV__WLAN_CONTROL_EN_SHRD_BIAS_RX_CH1_OVS___S 12 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_AON_CHAIN_BIAS_OV___S 12 + +#define PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH0 (0x005D4154) +#define PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH0___POR 0x016800A0 +#define PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH0__TX_GAIN_LUT_THRES1_5G_CH0___POR 0x168 +#define PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH0__TX_GAIN_LUT_THRES0_5G_CH0___POR 0x0A0 +#define PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH0__TX_GAIN_LUT_THRES1_5G_CH0___M 0x01FF0000 +#define PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH0__TX_GAIN_LUT_THRES1_5G_CH0___S 16 +#define PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH0__TX_GAIN_LUT_THRES0_5G_CH0___M 0x000001FF +#define PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH0__TX_GAIN_LUT_THRES0_5G_CH0___S 0 +#define PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH0___M 0x01FF01FF +#define PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH0___S 0 + +#define PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH1 (0x005D4158) +#define PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH1___POR 0x016800A0 +#define PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH1__TX_GAIN_LUT_THRES1_5G_CH1___POR 0x168 +#define PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH1__TX_GAIN_LUT_THRES0_5G_CH1___POR 0x0A0 +#define PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH1__TX_GAIN_LUT_THRES1_5G_CH1___M 0x01FF0000 +#define PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH1__TX_GAIN_LUT_THRES1_5G_CH1___S 16 +#define PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH1__TX_GAIN_LUT_THRES0_5G_CH1___M 0x000001FF +#define PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH1__TX_GAIN_LUT_THRES0_5G_CH1___S 0 +#define PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH1___M 0x01FF01FF +#define PHYA_IRON2G_RFA_AON_TX_GAIN_LUT_THRES_5G_CH1___S 0 + +#define PHYA_IRON2G_RFA_AON_RX_GAIN_LUT_THRES_5G_CH0 (0x005D415C) +#define PHYA_IRON2G_RFA_AON_RX_GAIN_LUT_THRES_5G_CH0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_RX_GAIN_LUT_THRES_5G_CH0___POR 0x0000012C +#define PHYA_IRON2G_RFA_AON_RX_GAIN_LUT_THRES_5G_CH0__RX_GAIN_LUT_THRES_5G_CH0___POR 0x12C +#define PHYA_IRON2G_RFA_AON_RX_GAIN_LUT_THRES_5G_CH0__RX_GAIN_LUT_THRES_5G_CH0___M 0x000001FF +#define PHYA_IRON2G_RFA_AON_RX_GAIN_LUT_THRES_5G_CH0__RX_GAIN_LUT_THRES_5G_CH0___S 0 +#define PHYA_IRON2G_RFA_AON_RX_GAIN_LUT_THRES_5G_CH0___M 0x000001FF +#define PHYA_IRON2G_RFA_AON_RX_GAIN_LUT_THRES_5G_CH0___S 0 + +#define PHYA_IRON2G_RFA_AON_RX_GAIN_LUT_THRES_5G_CH1 (0x005D4160) +#define PHYA_IRON2G_RFA_AON_RX_GAIN_LUT_THRES_5G_CH1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_RX_GAIN_LUT_THRES_5G_CH1___POR 0x0000012C +#define PHYA_IRON2G_RFA_AON_RX_GAIN_LUT_THRES_5G_CH1__RX_GAIN_LUT_THRES_5G_CH1___POR 0x12C +#define PHYA_IRON2G_RFA_AON_RX_GAIN_LUT_THRES_5G_CH1__RX_GAIN_LUT_THRES_5G_CH1___M 0x000001FF +#define PHYA_IRON2G_RFA_AON_RX_GAIN_LUT_THRES_5G_CH1__RX_GAIN_LUT_THRES_5G_CH1___S 0 +#define PHYA_IRON2G_RFA_AON_RX_GAIN_LUT_THRES_5G_CH1___M 0x000001FF +#define PHYA_IRON2G_RFA_AON_RX_GAIN_LUT_THRES_5G_CH1___S 0 + +#define PHYA_IRON2G_RFA_AON_RBIST (0x005D4164) +#define PHYA_IRON2G_RFA_AON_RBIST___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_RBIST___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RBIST__RBIST_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RBIST__RBIST_MODE___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_RBIST__RBIST_MODE___S 31 +#define PHYA_IRON2G_RFA_AON_RBIST___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_RBIST___S 31 + +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_0 (0x005D4180) +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_0___POR 0x00000007 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_0__SYN_EN_VALID_WL_SYNTH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_0__SYN_MODE_WL_SYNTH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_0__CHAN_IDX_WL_SYNTH0___POR 0x07 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_0__SYN_EN_VALID_WL_SYNTH0___M 0xF0000000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_0__SYN_EN_VALID_WL_SYNTH0___S 28 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_0__SYN_MODE_WL_SYNTH0___M 0x07000000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_0__SYN_MODE_WL_SYNTH0___S 24 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_0__CHAN_IDX_WL_SYNTH0___M 0x000000FF +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_0__CHAN_IDX_WL_SYNTH0___S 0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_0___M 0xF70000FF +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_0___S 0 + +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_1 (0x005D4184) +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_1___POR 0x05000007 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_1__SYN_EN_VALID_WL_SYNTH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_1__SYN_MODE_WL_SYNTH1___POR 0x5 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_1__CHAN_IDX_WL_SYNTH1___POR 0x007 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_1__SYN_EN_VALID_WL_SYNTH1___M 0xF0000000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_1__SYN_EN_VALID_WL_SYNTH1___S 28 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_1__SYN_MODE_WL_SYNTH1___M 0x07000000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_1__SYN_MODE_WL_SYNTH1___S 24 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_1__CHAN_IDX_WL_SYNTH1___M 0x000001FF +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_1__CHAN_IDX_WL_SYNTH1___S 0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_1___M 0xF70001FF +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_1___S 0 + +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_2 (0x005D4188) +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_2___POR 0x07000000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_2__SYN_EN_VALID_WL_SYNTH2___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_2__SYN_MODE_WL_SYNTH2___POR 0x7 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_2__CHAN_IDX_WL_SYNTH2___POR 0x000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_2__SYN_EN_VALID_WL_SYNTH2___M 0xF0000000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_2__SYN_EN_VALID_WL_SYNTH2___S 28 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_2__SYN_MODE_WL_SYNTH2___M 0x07000000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_2__SYN_MODE_WL_SYNTH2___S 24 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_2__CHAN_IDX_WL_SYNTH2___M 0x000001FF +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_2__CHAN_IDX_WL_SYNTH2___S 0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_2___M 0xF70001FF +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_2___S 0 + +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3 (0x005D418C) +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3___POR 0x00AAA080 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_SL_ASSERT_DISABLE_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_SL_ASSERT_DISABLE_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_INTR_MASK_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_INTR_MASK_CH1___POR 0xA +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_INTR_MASK_CH2___POR 0xA +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_INTR_MASK_CH3___POR 0xA +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__BT_TEST_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__FM_TEST_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__JTAG_EN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__MODE_BIT_ENABLE_LNA_TAKE___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__RCB_BLIND_REQ_EN___POR 0x1 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__SW_DIS_80_80_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__RCB_SEL_PMU_TEST___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__CLPC_CFG_2G___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__CLPC_CFG_5G___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_SL_ASSERT_DISABLE_CH0___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_SL_ASSERT_DISABLE_CH0___S 31 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_SL_ASSERT_DISABLE_CH1___M 0x40000000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_SL_ASSERT_DISABLE_CH1___S 30 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_INTR_MASK_CH0___M 0x0F000000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_INTR_MASK_CH0___S 24 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_INTR_MASK_CH1___M 0x00F00000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_INTR_MASK_CH1___S 20 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_INTR_MASK_CH2___M 0x000F0000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_INTR_MASK_CH2___S 16 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_INTR_MASK_CH3___M 0x0000F000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__WSI_INTR_MASK_CH3___S 12 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__BT_TEST_MODE___M 0x00000800 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__BT_TEST_MODE___S 11 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__FM_TEST_MODE___M 0x00000400 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__FM_TEST_MODE___S 10 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__JTAG_EN___M 0x00000200 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__JTAG_EN___S 9 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__MODE_BIT_ENABLE_LNA_TAKE___M 0x00000100 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__MODE_BIT_ENABLE_LNA_TAKE___S 8 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__RCB_BLIND_REQ_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__RCB_BLIND_REQ_EN___S 7 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__SW_DIS_80_80_MODE___M 0x00000040 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__SW_DIS_80_80_MODE___S 6 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__RCB_SEL_PMU_TEST___M 0x00000020 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__RCB_SEL_PMU_TEST___S 5 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__CLPC_CFG_2G___M 0x00000010 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__CLPC_CFG_2G___S 4 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__CLPC_CFG_5G___M 0x00000008 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3__CLPC_CFG_5G___S 3 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3___M 0xCFFFFFF8 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_3___S 3 + +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4 (0x005D4190) +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_SLP_RET_N_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_SLP_NRET_N_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_CLAMP_MEM_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__MEM_FREEZE_CT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_MEM_SVS_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_RAM1P_ACC_OV___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_RAM1P_ACC_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_RAM2P_ACC_OV___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_RAM2P_ACC_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_SLP_RET_N_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_SLP_RET_N_OVS___S 30 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_SLP_NRET_N_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_SLP_NRET_N_OVS___S 28 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_CLAMP_MEM_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_CLAMP_MEM_OVS___S 26 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__MEM_FREEZE_CT___M 0x02000000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__MEM_FREEZE_CT___S 25 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_MEM_SVS_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_MEM_SVS_OVS___S 20 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_RAM1P_ACC_OV___M 0x00020000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_RAM1P_ACC_OV___S 17 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_RAM1P_ACC_OVD___M 0x0001FE00 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_RAM1P_ACC_OVD___S 9 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_RAM2P_ACC_OV___M 0x00000100 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_RAM2P_ACC_OV___S 8 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_RAM2P_ACC_OVD___M 0x000000FF +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4__RFA_RAM2P_ACC_OVD___S 0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4___M 0xFE33FFFF +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_4___S 0 + +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5 (0x005D4194) +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5__RFA_ROM_SLP_N_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5__RFA_ROM_ACC_OV___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5__RFA_ROM_ACC_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5__RFA_RAM1P_REDUN_ACC_OV___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5__RFA_RAM1P_REDUN_ACC_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5__RFA_ROM_SLP_N_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5__RFA_ROM_SLP_N_OVS___S 30 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5__RFA_ROM_ACC_OV___M 0x10000000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5__RFA_ROM_ACC_OV___S 28 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5__RFA_ROM_ACC_OVD___M 0x0FF00000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5__RFA_ROM_ACC_OVD___S 20 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5__RFA_RAM1P_REDUN_ACC_OV___M 0x00000100 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5__RFA_RAM1P_REDUN_ACC_OV___S 8 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5__RFA_RAM1P_REDUN_ACC_OVD___M 0x000000FF +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5__RFA_RAM1P_REDUN_ACC_OVD___S 0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5___M 0xDFF001FF +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_5___S 0 + +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6 (0x005D4198) +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__RFA_TMUX_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__WL_ADC_TEST_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__WL_PDADC_TEST_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_2G_CH0_I___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_2G_CH0_Q___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_5G_CH0_I___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_5G_CH0_Q___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_2G_CH1_I___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_2G_CH1_Q___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_5G_CH1_I___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_5G_CH1_Q___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__BT_ADC_CLKOUT_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__BT_CLK_TEST_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATB_TO_PAD___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_PMU_ATB_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__RFA_TMUX_SEL___M 0xF0000000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__RFA_TMUX_SEL___S 28 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__WL_ADC_TEST_SEL___M 0x04000000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__WL_ADC_TEST_SEL___S 26 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__WL_PDADC_TEST_SEL___M 0x03000000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__WL_PDADC_TEST_SEL___S 24 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_2G_CH0_I___M 0x00800000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_2G_CH0_I___S 23 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_2G_CH0_Q___M 0x00400000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_2G_CH0_Q___S 22 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_5G_CH0_I___M 0x00200000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_5G_CH0_I___S 21 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_5G_CH0_Q___M 0x00100000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_5G_CH0_Q___S 20 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_2G_CH1_I___M 0x00080000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_2G_CH1_I___S 19 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_2G_CH1_Q___M 0x00040000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_2G_CH1_Q___S 18 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_5G_CH1_I___M 0x00020000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_5G_CH1_I___S 17 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_5G_CH1_Q___M 0x00010000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATEST_EN_5G_CH1_Q___S 16 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__BT_ADC_CLKOUT_SEL___M 0x00000400 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__BT_ADC_CLKOUT_SEL___S 10 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__BT_CLK_TEST_MODE___M 0x00000200 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__BT_CLK_TEST_MODE___S 9 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATB_TO_PAD___M 0x00000100 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_ATB_TO_PAD___S 8 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_PMU_ATB_SEL___M 0x000000FF +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6__D_PMU_ATB_SEL___S 0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6___M 0xF7FF07FF +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_6___S 0 + +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7 (0x005D419C) +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__DCLK_COUNT_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__DTO_DAC_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__DTO_ADC_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__DTO_CT_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__ZZZ_SPARE___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__DTO_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__DCLK_COUNT_RESET___M 0x00000800 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__DCLK_COUNT_RESET___S 11 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__DTO_DAC_SEL___M 0x00000600 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__DTO_DAC_SEL___S 9 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__DTO_ADC_SEL___M 0x00000180 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__DTO_ADC_SEL___S 7 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__DTO_CT_SEL___M 0x00000070 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__DTO_CT_SEL___S 4 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__ZZZ_SPARE___M 0x00000008 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__ZZZ_SPARE___S 3 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__DTO_SEL___M 0x00000007 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7__DTO_SEL___S 0 +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7___M 0x00000FFF +#define PHYA_IRON2G_RFA_AON_RFA_AON_SYSCTRL_7___S 0 + +#define PHYA_IRON2G_RFA_AON_AON_SPARE_0 (0x005D41A0) +#define PHYA_IRON2G_RFA_AON_AON_SPARE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_AON_SPARE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_AON_SPARE_0__D_AON_SPARE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_AON_SPARE_0__D_AON_SPARE_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_AON_AON_SPARE_0__D_AON_SPARE_0___S 0 +#define PHYA_IRON2G_RFA_AON_AON_SPARE_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_AON_AON_SPARE_0___S 0 + +#define PHYA_IRON2G_RFA_AON_AON_SPARE_1 (0x005D41A4) +#define PHYA_IRON2G_RFA_AON_AON_SPARE_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_AON_SPARE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_AON_SPARE_1__D_AON_SPARE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_AON_SPARE_1__D_AON_SPARE_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_AON_AON_SPARE_1__D_AON_SPARE_1___S 0 +#define PHYA_IRON2G_RFA_AON_AON_SPARE_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_AON_AON_SPARE_1___S 0 + +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT (0x005D41A8) +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_MAIN_SYN_EN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_LP_SYN_EN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_LP_SYN_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_TX_EN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_DCLK_COUNT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_MAIN_SYN_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_MAIN_SYN_EN___S 31 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_LP_SYN_EN___M 0x40000000 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_LP_SYN_EN___S 30 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_LP_SYN_SEL___M 0x20000000 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_LP_SYN_SEL___S 29 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_TX_EN___M 0x10000000 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_WSI_UD_TX_EN___S 28 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_DCLK_COUNT___M 0x0F000000 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT__RO_DCLK_COUNT___S 24 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT___M 0xFF000000 +#define PHYA_IRON2G_RFA_AON_RO_RFA_AON_SYSSTAT___S 24 + +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG (0x005D41C0) +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG___POR 0x80000000 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG__ALLOW_WSI_CMD_DURING_TXRX___POR 0x1 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG__DEFAULT_SYN_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG__TX_MASK_2G_CH0_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG__TX_MASK_5G_CH0_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG__TX_MASK_2G_CH1_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG__TX_MASK_5G_CH1_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG__DYN_SYN_OFF_DELAY___POR 0x0 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG__ALLOW_WSI_CMD_DURING_TXRX___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG__ALLOW_WSI_CMD_DURING_TXRX___S 31 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG__DEFAULT_SYN_SEL___M 0x40000000 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG__DEFAULT_SYN_SEL___S 30 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG__TX_MASK_2G_CH0_RESET___M 0x20000000 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG__TX_MASK_2G_CH0_RESET___S 29 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG__TX_MASK_5G_CH0_RESET___M 0x10000000 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG__TX_MASK_5G_CH0_RESET___S 28 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG__TX_MASK_2G_CH1_RESET___M 0x08000000 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG__TX_MASK_2G_CH1_RESET___S 27 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG__TX_MASK_5G_CH1_RESET___M 0x04000000 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG__TX_MASK_5G_CH1_RESET___S 26 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG__DYN_SYN_OFF_DELAY___M 0x03000000 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG__DYN_SYN_OFF_DELAY___S 24 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG___M 0xFF000000 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG___S 24 + +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV (0x005D41C4) +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_MAIN_SYN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_LP_SYN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_LP_SYN_SEL_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__SYN_CAL_DONE_WL_SYNTH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__SYN_CAL_DONE_WL_SYNTH2_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_MAIN_SYN_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_MAIN_SYN_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_LP_SYN_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_LP_SYN_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_LP_SYN_SEL_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__RFA_LP_SYN_SEL_OVS___S 26 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__SYN_CAL_DONE_WL_SYNTH1_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__SYN_CAL_DONE_WL_SYNTH1_OVS___S 24 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__SYN_CAL_DONE_WL_SYNTH2_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV__SYN_CAL_DONE_WL_SYNTH2_OVS___S 22 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV___M 0xFFC00000 +#define PHYA_IRON2G_RFA_AON_SYNTH_CFG_OV___S 22 + +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG (0x005D41C8) +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_CST_SYNTH_WSI_SW___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_RFA_MAIN_SYN_EN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_RFA_LP_SYN_EN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_RFA_LP_SYN_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_CST_SYNTH_RES_CTRL_WL_SYNTH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RESTORE_WL_SYNTH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_EN_WL_SYNTH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_DONE_WL_SYNTH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RES_EN_WL_SYNTH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_EN_WL_SYNTH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_CST_SYNTH_RES_CTRL_WL_SYNTH2___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RESTORE_WL_SYNTH2___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_EN_WL_SYNTH2___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_DONE_WL_SYNTH2___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RES_EN_WL_SYNTH2___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_EN_WL_SYNTH2___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_CST_SYNTH_WSI_SW___M 0xE0000000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_CST_SYNTH_WSI_SW___S 29 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_RFA_MAIN_SYN_EN___M 0x10000000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_RFA_MAIN_SYN_EN___S 28 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_RFA_LP_SYN_EN___M 0x08000000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_RFA_LP_SYN_EN___S 27 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_RFA_LP_SYN_SEL___M 0x04000000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_RFA_LP_SYN_SEL___S 26 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_CST_SYNTH_RES_CTRL_WL_SYNTH1___M 0x0000C000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_CST_SYNTH_RES_CTRL_WL_SYNTH1___S 14 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RESTORE_WL_SYNTH1___M 0x00002000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RESTORE_WL_SYNTH1___S 13 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_EN_WL_SYNTH1___M 0x00001000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_EN_WL_SYNTH1___S 12 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_DONE_WL_SYNTH1___M 0x00000800 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_DONE_WL_SYNTH1___S 11 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RES_EN_WL_SYNTH1___M 0x00000400 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RES_EN_WL_SYNTH1___S 10 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_EN_WL_SYNTH1___M 0x00000200 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_EN_WL_SYNTH1___S 9 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_CST_SYNTH_RES_CTRL_WL_SYNTH2___M 0x000000C0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_CST_SYNTH_RES_CTRL_WL_SYNTH2___S 6 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RESTORE_WL_SYNTH2___M 0x00000020 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RESTORE_WL_SYNTH2___S 5 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_EN_WL_SYNTH2___M 0x00000010 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_EN_WL_SYNTH2___S 4 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_DONE_WL_SYNTH2___M 0x00000008 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_DONE_WL_SYNTH2___S 3 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RES_EN_WL_SYNTH2___M 0x00000004 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_RES_EN_WL_SYNTH2___S 2 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_EN_WL_SYNTH2___M 0x00000002 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG__RO_SYN_CAL_EN_WL_SYNTH2___S 1 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG___M 0xFC00FEFE +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_CFG___S 1 + +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG (0x005D41CC) +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG__RO_TX_MASK_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG__RO_TX_MASK_5G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG__RO_TX_MASK_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG__RO_TX_MASK_5G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG__RO_TX_MASK_2G_CH0___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG__RO_TX_MASK_2G_CH0___S 31 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG__RO_TX_MASK_5G_CH0___M 0x40000000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG__RO_TX_MASK_5G_CH0___S 30 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG__RO_TX_MASK_2G_CH1___M 0x20000000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG__RO_TX_MASK_2G_CH1___S 29 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG__RO_TX_MASK_5G_CH1___M 0x10000000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG__RO_TX_MASK_5G_CH1___S 28 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG___M 0xF0000000 +#define PHYA_IRON2G_RFA_AON_RO_SYNTH_DBG___S 28 + +#define PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE0 (0x005D4200) +#define PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE0___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE0__WL_SPARE_RFA2DIG___POR 0x0000 +#define PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE0__BT_SPARE_RFA2DIG___POR 0x0000 +#define PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE0__WL_SPARE_RFA2DIG___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE0__WL_SPARE_RFA2DIG___S 16 +#define PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE0__BT_SPARE_RFA2DIG___M 0x0000FFFF +#define PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE0__BT_SPARE_RFA2DIG___S 0 +#define PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE0___S 0 + +#define PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE1 (0x005D4204) +#define PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE1___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE1__CM_SPARE_RFA2DIG___POR 0x0000 +#define PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE1__CM_SPARE_RFA2DIG___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE1__CM_SPARE_RFA2DIG___S 16 +#define PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE1___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_AON_RFA2DIG_SPARE1___S 16 + +#define PHYA_IRON2G_RFA_AON_DRM_BT_DBG (0x005D4208) +#define PHYA_IRON2G_RFA_AON_DRM_BT_DBG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_DRM_BT_DBG___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_DRM_BT_DBG__DRM_TX_DBG_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_AON_DRM_BT_DBG__DRM_RX_DBG_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_AON_DRM_BT_DBG__DRM_TX_DBG_SEL___M 0x000000F0 +#define PHYA_IRON2G_RFA_AON_DRM_BT_DBG__DRM_TX_DBG_SEL___S 4 +#define PHYA_IRON2G_RFA_AON_DRM_BT_DBG__DRM_RX_DBG_SEL___M 0x0000000F +#define PHYA_IRON2G_RFA_AON_DRM_BT_DBG__DRM_RX_DBG_SEL___S 0 +#define PHYA_IRON2G_RFA_AON_DRM_BT_DBG___M 0x000000FF +#define PHYA_IRON2G_RFA_AON_DRM_BT_DBG___S 0 + +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_BT (0x005D4240) +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_BT___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_BT___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_BT__BT_DEDICATED_XPA___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_BT__BT_DEDICATED_XPA___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_BT__BT_DEDICATED_XPA___S 31 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_BT___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_BT___S 31 + +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0 (0x005D4244) +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0___POR 0xC0000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0__XPA_CFG_2G_CH0___POR 0x1 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0__XLNA_CFG_2G_CH0___POR 0x1 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0__XTRSW_CFG_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0__XPA_CFG_2G_CH0___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0__XPA_CFG_2G_CH0___S 31 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0__XLNA_CFG_2G_CH0___M 0x40000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0__XLNA_CFG_2G_CH0___S 30 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0__XTRSW_CFG_2G_CH0___M 0x20000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0__XTRSW_CFG_2G_CH0___S 29 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0___M 0xE0000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH0___S 29 + +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1 (0x005D4248) +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1___POR 0xC0000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1__XPA_CFG_2G_CH1___POR 0x1 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1__XLNA_CFG_2G_CH1___POR 0x1 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1__XTRSW_CFG_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1__XPA_CFG_2G_CH1___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1__XPA_CFG_2G_CH1___S 31 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1__XLNA_CFG_2G_CH1___M 0x40000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1__XLNA_CFG_2G_CH1___S 30 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1__XTRSW_CFG_2G_CH1___M 0x20000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1__XTRSW_CFG_2G_CH1___S 29 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1___M 0xE0000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_2G_CH1___S 29 + +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0 (0x005D424C) +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0___POR 0xC0000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0__XPA_CFG_5G_CH0___POR 0x1 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0__XLNA_CFG_5G_CH0___POR 0x1 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0__XTRSW_CFG_5G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0__XPA_CFG_5G_CH0___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0__XPA_CFG_5G_CH0___S 31 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0__XLNA_CFG_5G_CH0___M 0x40000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0__XLNA_CFG_5G_CH0___S 30 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0__XTRSW_CFG_5G_CH0___M 0x20000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0__XTRSW_CFG_5G_CH0___S 29 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0___M 0xE0000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH0___S 29 + +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1 (0x005D4250) +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1___POR 0xC0000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1__XPA_CFG_5G_CH1___POR 0x1 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1__XLNA_CFG_5G_CH1___POR 0x1 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1__XTRSW_CFG_5G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1__XPA_CFG_5G_CH1___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1__XPA_CFG_5G_CH1___S 31 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1__XLNA_CFG_5G_CH1___M 0x40000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1__XLNA_CFG_5G_CH1___S 30 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1__XTRSW_CFG_5G_CH1___M 0x20000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1__XTRSW_CFG_5G_CH1___S 29 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1___M 0xE0000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_WL_5G_CH1___S 29 + +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_6G_THRES (0x005D4254) +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_6G_THRES___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_6G_THRES___POR 0x00BA00BA +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_6G_THRES__XFEM_THRES_6G_CH1___POR 0x0BA +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_6G_THRES__XFEM_THRES_6G_CH0___POR 0x0BA +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_6G_THRES__XFEM_THRES_6G_CH1___M 0x01FF0000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_6G_THRES__XFEM_THRES_6G_CH1___S 16 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_6G_THRES__XFEM_THRES_6G_CH0___M 0x000001FF +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_6G_THRES__XFEM_THRES_6G_CH0___S 0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_6G_THRES___M 0x01FF01FF +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_6G_THRES___S 0 + +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7 (0x005D4258) +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7___POR 0xC89D7510 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_7___POR 0xC +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_6___POR 0x8 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_5___POR 0x9 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_4___POR 0xD +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_3___POR 0x7 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_2___POR 0x5 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_1___POR 0x1 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_7___M 0xF0000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_7___S 28 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_6___M 0x0F000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_6___S 24 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_5___M 0x00F00000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_5___S 20 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_4___M 0x000F0000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_4___S 16 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_3___M 0x0000F000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_3___S 12 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_2___M 0x00000F00 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_2___S 8 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_1___M 0x000000F0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_1___S 4 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_0___M 0x0000000F +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7__CFG_XFEM_CTRL_2G_CH0_0___S 0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_0T7___S 0 + +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12 (0x005D425C) +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12___POR 0x000642EA +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12__CFG_XFEM_CTRL_2G_CH0_12___POR 0x6 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12__CFG_XFEM_CTRL_2G_CH0_11___POR 0x4 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12__CFG_XFEM_CTRL_2G_CH0_10___POR 0x2 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12__CFG_XFEM_CTRL_2G_CH0_9___POR 0xE +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12__CFG_XFEM_CTRL_2G_CH0_8___POR 0xA +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12__CFG_XFEM_CTRL_2G_CH0_12___M 0x000F0000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12__CFG_XFEM_CTRL_2G_CH0_12___S 16 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12__CFG_XFEM_CTRL_2G_CH0_11___M 0x0000F000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12__CFG_XFEM_CTRL_2G_CH0_11___S 12 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12__CFG_XFEM_CTRL_2G_CH0_10___M 0x00000F00 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12__CFG_XFEM_CTRL_2G_CH0_10___S 8 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12__CFG_XFEM_CTRL_2G_CH0_9___M 0x000000F0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12__CFG_XFEM_CTRL_2G_CH0_9___S 4 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12__CFG_XFEM_CTRL_2G_CH0_8___M 0x0000000F +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12__CFG_XFEM_CTRL_2G_CH0_8___S 0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12___M 0x000FFFFF +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH0_8T12___S 0 + +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7 (0x005D4260) +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7___POR 0xC89D7510 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_7___POR 0xC +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_6___POR 0x8 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_5___POR 0x9 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_4___POR 0xD +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_3___POR 0x7 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_2___POR 0x5 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_1___POR 0x1 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_7___M 0xF0000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_7___S 28 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_6___M 0x0F000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_6___S 24 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_5___M 0x00F00000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_5___S 20 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_4___M 0x000F0000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_4___S 16 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_3___M 0x0000F000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_3___S 12 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_2___M 0x00000F00 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_2___S 8 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_1___M 0x000000F0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_1___S 4 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_0___M 0x0000000F +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7__CFG_XFEM_CTRL_2G_CH1_0___S 0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_0T7___S 0 + +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12 (0x005D4264) +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12___POR 0x000642EA +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12__CFG_XFEM_CTRL_2G_CH1_12___POR 0x6 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12__CFG_XFEM_CTRL_2G_CH1_11___POR 0x4 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12__CFG_XFEM_CTRL_2G_CH1_10___POR 0x2 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12__CFG_XFEM_CTRL_2G_CH1_9___POR 0xE +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12__CFG_XFEM_CTRL_2G_CH1_8___POR 0xA +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12__CFG_XFEM_CTRL_2G_CH1_12___M 0x000F0000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12__CFG_XFEM_CTRL_2G_CH1_12___S 16 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12__CFG_XFEM_CTRL_2G_CH1_11___M 0x0000F000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12__CFG_XFEM_CTRL_2G_CH1_11___S 12 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12__CFG_XFEM_CTRL_2G_CH1_10___M 0x00000F00 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12__CFG_XFEM_CTRL_2G_CH1_10___S 8 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12__CFG_XFEM_CTRL_2G_CH1_9___M 0x000000F0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12__CFG_XFEM_CTRL_2G_CH1_9___S 4 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12__CFG_XFEM_CTRL_2G_CH1_8___M 0x0000000F +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12__CFG_XFEM_CTRL_2G_CH1_8___S 0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12___M 0x000FFFFF +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_2G_CH1_8T12___S 0 + +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7 (0x005D4268) +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7___POR 0xD9467510 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_7___POR 0xD +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_6___POR 0x9 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_5___POR 0x4 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_4___POR 0x6 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_3___POR 0x7 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_2___POR 0x5 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_1___POR 0x1 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_7___M 0xF0000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_7___S 28 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_6___M 0x0F000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_6___S 24 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_5___M 0x00F00000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_5___S 20 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_4___M 0x000F0000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_4___S 16 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_3___M 0x0000F000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_3___S 12 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_2___M 0x00000F00 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_2___S 8 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_1___M 0x000000F0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_1___S 4 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_0___M 0x0000000F +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7__CFG_XFEM_CTRL_5G_CH0_0___S 0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_0T7___S 0 + +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11 (0x005D426C) +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11___POR 0x00032CEF +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11__CFG_XFEM_CTRL_5G_CH0_12___POR 0x3 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11__CFG_XFEM_CTRL_5G_CH0_11___POR 0x2 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11__CFG_XFEM_CTRL_5G_CH0_10___POR 0xC +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11__CFG_XFEM_CTRL_5G_CH0_9___POR 0xE +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11__CFG_XFEM_CTRL_5G_CH0_8___POR 0xF +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11__CFG_XFEM_CTRL_5G_CH0_12___M 0x000F0000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11__CFG_XFEM_CTRL_5G_CH0_12___S 16 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11__CFG_XFEM_CTRL_5G_CH0_11___M 0x0000F000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11__CFG_XFEM_CTRL_5G_CH0_11___S 12 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11__CFG_XFEM_CTRL_5G_CH0_10___M 0x00000F00 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11__CFG_XFEM_CTRL_5G_CH0_10___S 8 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11__CFG_XFEM_CTRL_5G_CH0_9___M 0x000000F0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11__CFG_XFEM_CTRL_5G_CH0_9___S 4 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11__CFG_XFEM_CTRL_5G_CH0_8___M 0x0000000F +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11__CFG_XFEM_CTRL_5G_CH0_8___S 0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11___M 0x000FFFFF +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH0_8T11___S 0 + +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7 (0x005D4270) +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7___POR 0xD9467510 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_7___POR 0xD +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_6___POR 0x9 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_5___POR 0x4 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_4___POR 0x6 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_3___POR 0x7 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_2___POR 0x5 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_1___POR 0x1 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_7___M 0xF0000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_7___S 28 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_6___M 0x0F000000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_6___S 24 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_5___M 0x00F00000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_5___S 20 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_4___M 0x000F0000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_4___S 16 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_3___M 0x0000F000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_3___S 12 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_2___M 0x00000F00 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_2___S 8 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_1___M 0x000000F0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_1___S 4 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_0___M 0x0000000F +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7__CFG_XFEM_CTRL_5G_CH1_0___S 0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_0T7___S 0 + +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11 (0x005D4274) +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11___POR 0x00032CEF +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11__CFG_XFEM_CTRL_5G_CH1_12___POR 0x3 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11__CFG_XFEM_CTRL_5G_CH1_11___POR 0x2 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11__CFG_XFEM_CTRL_5G_CH1_10___POR 0xC +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11__CFG_XFEM_CTRL_5G_CH1_9___POR 0xE +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11__CFG_XFEM_CTRL_5G_CH1_8___POR 0xF +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11__CFG_XFEM_CTRL_5G_CH1_12___M 0x000F0000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11__CFG_XFEM_CTRL_5G_CH1_12___S 16 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11__CFG_XFEM_CTRL_5G_CH1_11___M 0x0000F000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11__CFG_XFEM_CTRL_5G_CH1_11___S 12 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11__CFG_XFEM_CTRL_5G_CH1_10___M 0x00000F00 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11__CFG_XFEM_CTRL_5G_CH1_10___S 8 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11__CFG_XFEM_CTRL_5G_CH1_9___M 0x000000F0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11__CFG_XFEM_CTRL_5G_CH1_9___S 4 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11__CFG_XFEM_CTRL_5G_CH1_8___M 0x0000000F +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11__CFG_XFEM_CTRL_5G_CH1_8___S 0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11___M 0x000FFFFF +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_5G_CH1_8T11___S 0 + +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT (0x005D4278) +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT___POR 0x00013DB1 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_5___POR 0x2 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_4___POR 0x3 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_3___POR 0x6 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_2___POR 0x6 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_1___POR 0x6 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_0___POR 0x1 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_5___M 0x00038000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_5___S 15 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_4___M 0x00007000 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_4___S 12 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_3___M 0x00000E00 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_3___S 9 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_2___M 0x000001C0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_2___S 6 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_1___M 0x00000038 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_1___S 3 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_0___M 0x00000007 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT__CFG_XFEM_CTRL_BT_0___S 0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT___M 0x0003FFFF +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_BT___S 0 + +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM (0x005D427C) +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM___POR 0x00000618 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH1_2___POR 0x1 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH1_1___POR 0x2 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH1_0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH0_2___POR 0x1 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH0_1___POR 0x2 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH0_0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH1_2___M 0x00000C00 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH1_2___S 10 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH1_1___M 0x00000300 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH1_1___S 8 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH1_0___M 0x000000C0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH1_0___S 6 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH0_2___M 0x00000030 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH0_2___S 4 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH0_1___M 0x0000000C +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH0_1___S 2 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH0_0___M 0x00000003 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM__CFG_XFEM_CTRL_SLM_CH0_0___S 0 +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM___M 0x00000FFF +#define PHYA_IRON2G_RFA_AON_XFEM_CFG_XFEM_CTRL_SLM___S 0 + +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA (0x005D4280) +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA___POR 0x000D0000 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__LAA_TX_CFG___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__PA_MUTE_BT_MASK___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__PA_MUTE_5G_CH1_MASK___POR 0x1 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__PA_MUTE_5G_CH0_MASK___POR 0x1 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__PA_MUTE_2G_CH1_MASK___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__PA_MUTE_2G_CH0_MASK___POR 0x1 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__LAA_RX_5G_CH1_MASK___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__LAA_RX_5G_CH0_MASK___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__N79_TXEN_5G_CH1_MASK___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__N79_TXEN_5G_CH0_MASK___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__LAA_TXEN_5G_CH1_MASK___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__LAA_TXEN_5G_CH0_MASK___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__WL_XFEM_CTRL_WL_TXEN_TO_N79_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__WL_XFEM_CTRL_N79_TXEN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__WL_XFEM_CTRL_WL_TXEN_TO_LAA_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__WL_XFEM_CTRL_LAA_TXEN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__LAA_TX_CFG___M 0x00200000 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__LAA_TX_CFG___S 21 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__PA_MUTE_BT_MASK___M 0x00100000 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__PA_MUTE_BT_MASK___S 20 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__PA_MUTE_5G_CH1_MASK___M 0x00080000 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__PA_MUTE_5G_CH1_MASK___S 19 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__PA_MUTE_5G_CH0_MASK___M 0x00040000 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__PA_MUTE_5G_CH0_MASK___S 18 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__PA_MUTE_2G_CH1_MASK___M 0x00020000 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__PA_MUTE_2G_CH1_MASK___S 17 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__PA_MUTE_2G_CH0_MASK___M 0x00010000 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__PA_MUTE_2G_CH0_MASK___S 16 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__LAA_RX_5G_CH1_MASK___M 0x00002000 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__LAA_RX_5G_CH1_MASK___S 13 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__LAA_RX_5G_CH0_MASK___M 0x00001000 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__LAA_RX_5G_CH0_MASK___S 12 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__N79_TXEN_5G_CH1_MASK___M 0x00000800 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__N79_TXEN_5G_CH1_MASK___S 11 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__N79_TXEN_5G_CH0_MASK___M 0x00000400 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__N79_TXEN_5G_CH0_MASK___S 10 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__LAA_TXEN_5G_CH1_MASK___M 0x00000200 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__LAA_TXEN_5G_CH1_MASK___S 9 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__LAA_TXEN_5G_CH0_MASK___M 0x00000100 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__LAA_TXEN_5G_CH0_MASK___S 8 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__WL_XFEM_CTRL_WL_TXEN_TO_N79_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__WL_XFEM_CTRL_WL_TXEN_TO_N79_OVS___S 6 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__WL_XFEM_CTRL_N79_TXEN_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__WL_XFEM_CTRL_N79_TXEN_OVS___S 4 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__WL_XFEM_CTRL_WL_TXEN_TO_LAA_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__WL_XFEM_CTRL_WL_TXEN_TO_LAA_OVS___S 2 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__WL_XFEM_CTRL_LAA_TXEN_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA__WL_XFEM_CTRL_LAA_TXEN_OVS___S 0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA___M 0x003F3FFF +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_LAA___S 0 + +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_N79_TXEN (0x005D4284) +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_N79_TXEN___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_N79_TXEN___POR 0x00BA00BA +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_N79_TXEN__THRES_N79_TXEN_5G_CH1___POR 0x0BA +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_N79_TXEN__THRES_N79_TXEN_5G_CH0___POR 0x0BA +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_N79_TXEN__THRES_N79_TXEN_5G_CH1___M 0x01FF0000 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_N79_TXEN__THRES_N79_TXEN_5G_CH1___S 16 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_N79_TXEN__THRES_N79_TXEN_5G_CH0___M 0x000001FF +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_N79_TXEN__THRES_N79_TXEN_5G_CH0___S 0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_N79_TXEN___M 0x01FF01FF +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_N79_TXEN___S 0 + +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_WL_TXEN_TO_N79 (0x005D4288) +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_WL_TXEN_TO_N79___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_WL_TXEN_TO_N79___POR 0x00BA00BA +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_WL_TXEN_TO_N79__THRES_WL_TXEN_TO_N79_5G_CH1___POR 0x0BA +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_WL_TXEN_TO_N79__THRES_WL_TXEN_TO_N79_5G_CH0___POR 0x0BA +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_WL_TXEN_TO_N79__THRES_WL_TXEN_TO_N79_5G_CH1___M 0x01FF0000 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_WL_TXEN_TO_N79__THRES_WL_TXEN_TO_N79_5G_CH1___S 16 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_WL_TXEN_TO_N79__THRES_WL_TXEN_TO_N79_5G_CH0___M 0x000001FF +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_WL_TXEN_TO_N79__THRES_WL_TXEN_TO_N79_5G_CH0___S 0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_WL_TXEN_TO_N79___M 0x01FF01FF +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_CTRL_THRES_WL_TXEN_TO_N79___S 0 + +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE (0x005D428C) +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_SLM_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_SLM_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_BT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_5G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_5G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_SLM_CH1___M 0x00600000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_SLM_CH1___S 21 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_SLM_CH0___M 0x00180000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_SLM_CH0___S 19 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_BT___M 0x00070000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_BT___S 16 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_5G_CH1___M 0x0000F000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_5G_CH1___S 12 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_5G_CH0___M 0x00000F00 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_5G_CH0___S 8 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_2G_CH1___M 0x000000F0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_2G_CH1___S 4 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_2G_CH0___M 0x0000000F +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE__RO_XFEM_STATE_2G_CH0___S 0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE___M 0x007FFFFF +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_STATE___S 0 + +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA (0x005D4290) +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_PA_MUTE_5G_CH1_LATCH___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_PA_MUTE_5G_CH0_LATCH___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_PA_MUTE_2G_CH1_LATCH___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_PA_MUTE_2G_CH0_LATCH___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_PA_MUTE___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_LAA_RX___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_LAA_AS_EN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_WL_TXEN_TO_LAA___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_LAA_TXEN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_WL_TXEN_TO_N79___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_N79_TXEN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_PA_MUTE_5G_CH1_LATCH___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_PA_MUTE_5G_CH1_LATCH___S 31 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_PA_MUTE_5G_CH0_LATCH___M 0x40000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_PA_MUTE_5G_CH0_LATCH___S 30 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_PA_MUTE_2G_CH1_LATCH___M 0x20000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_PA_MUTE_2G_CH1_LATCH___S 29 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_PA_MUTE_2G_CH0_LATCH___M 0x10000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_PA_MUTE_2G_CH0_LATCH___S 28 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_PA_MUTE___M 0x08000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_PA_MUTE___S 27 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_LAA_RX___M 0x04000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_LAA_RX___S 26 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_LAA_AS_EN___M 0x02000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_LAA_AS_EN___S 25 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_WL_TXEN_TO_LAA___M 0x01000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_WL_TXEN_TO_LAA___S 24 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_LAA_TXEN___M 0x00800000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_LAA_TXEN___S 23 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_WL_TXEN_TO_N79___M 0x00400000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_WL_TXEN_TO_N79___S 22 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_N79_TXEN___M 0x00200000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA__RO_WL_XFEM_CTRL_N79_TXEN___S 21 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA___M 0xFFE00000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_LAA___S 21 + +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0 (0x005D4294) +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_WLAN_CONTROL_EN_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_WL_XPA_EN_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_WL_XPA_GAIN_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_WL_XLNA_EN_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_WL_XLNA_GAIN_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_XPA_EN_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_TX_USE_BT_ANT_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_USE_WL_IPA_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_XPA_GAIN_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_XLNA_EN_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_RX_USE_BT_ANT_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_XLNA_GAIN_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_WLAN_CONTROL_EN_2G_CH0___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_WLAN_CONTROL_EN_2G_CH0___S 31 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_WL_XPA_EN_2G_CH0___M 0x40000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_WL_XPA_EN_2G_CH0___S 30 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_WL_XPA_GAIN_2G_CH0___M 0x3C000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_WL_XPA_GAIN_2G_CH0___S 26 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_WL_XLNA_EN_2G_CH0___M 0x02000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_WL_XLNA_EN_2G_CH0___S 25 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_WL_XLNA_GAIN_2G_CH0___M 0x01000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_WL_XLNA_GAIN_2G_CH0___S 24 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_XPA_EN_2G_CH0___M 0x00800000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_XPA_EN_2G_CH0___S 23 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_TX_USE_BT_ANT_2G_CH0___M 0x00400000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_TX_USE_BT_ANT_2G_CH0___S 22 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_USE_WL_IPA_2G_CH0___M 0x00200000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_USE_WL_IPA_2G_CH0___S 21 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_XPA_GAIN_2G_CH0___M 0x00180000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_XPA_GAIN_2G_CH0___S 19 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_XLNA_EN_2G_CH0___M 0x00040000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_XLNA_EN_2G_CH0___S 18 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_RX_USE_BT_ANT_2G_CH0___M 0x00020000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_RX_USE_BT_ANT_2G_CH0___S 17 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_XLNA_GAIN_2G_CH0___M 0x00018000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0__RO_BT_XLNA_GAIN_2G_CH0___S 15 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0___M 0xFFFF8000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH0___S 15 + +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1 (0x005D4298) +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_WLAN_CONTROL_EN_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_WL_XPA_EN_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_WL_XPA_GAIN_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_WL_XLNA_EN_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_WL_XLNA_GAIN_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_XPA_EN_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_TX_USE_BT_ANT_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_USE_WL_IPA_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_XPA_GAIN_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_XLNA_EN_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_RX_USE_BT_ANT_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_XLNA_GAIN_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_WLAN_CONTROL_EN_2G_CH1___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_WLAN_CONTROL_EN_2G_CH1___S 31 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_WL_XPA_EN_2G_CH1___M 0x40000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_WL_XPA_EN_2G_CH1___S 30 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_WL_XPA_GAIN_2G_CH1___M 0x3C000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_WL_XPA_GAIN_2G_CH1___S 26 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_WL_XLNA_EN_2G_CH1___M 0x02000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_WL_XLNA_EN_2G_CH1___S 25 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_WL_XLNA_GAIN_2G_CH1___M 0x01000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_WL_XLNA_GAIN_2G_CH1___S 24 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_XPA_EN_2G_CH1___M 0x00800000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_XPA_EN_2G_CH1___S 23 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_TX_USE_BT_ANT_2G_CH1___M 0x00400000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_TX_USE_BT_ANT_2G_CH1___S 22 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_USE_WL_IPA_2G_CH1___M 0x00200000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_USE_WL_IPA_2G_CH1___S 21 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_XPA_GAIN_2G_CH1___M 0x00180000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_XPA_GAIN_2G_CH1___S 19 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_XLNA_EN_2G_CH1___M 0x00040000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_XLNA_EN_2G_CH1___S 18 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_RX_USE_BT_ANT_2G_CH1___M 0x00020000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_RX_USE_BT_ANT_2G_CH1___S 17 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_XLNA_GAIN_2G_CH1___M 0x00018000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1__RO_BT_XLNA_GAIN_2G_CH1___S 15 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1___M 0xFFFF8000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_2G_CH1___S 15 + +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0 (0x005D429C) +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_LAA_TX_REQ_ISO_5G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_LAA_RX_USE_XLNA_5G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_IS_6G_5G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_WL_XPA_EN_5G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_WL_XPA_GAIN_5G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_WL_XLNA_EN_5G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_WL_XLNA_GAIN_5G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_LAA_TX_REQ_ISO_5G_CH0___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_LAA_TX_REQ_ISO_5G_CH0___S 31 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_LAA_RX_USE_XLNA_5G_CH0___M 0x40000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_LAA_RX_USE_XLNA_5G_CH0___S 30 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_IS_6G_5G_CH0___M 0x20000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_IS_6G_5G_CH0___S 29 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_WL_XPA_EN_5G_CH0___M 0x10000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_WL_XPA_EN_5G_CH0___S 28 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_WL_XPA_GAIN_5G_CH0___M 0x0F000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_WL_XPA_GAIN_5G_CH0___S 24 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_WL_XLNA_EN_5G_CH0___M 0x00800000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_WL_XLNA_EN_5G_CH0___S 23 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_WL_XLNA_GAIN_5G_CH0___M 0x00400000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0__RO_WL_XLNA_GAIN_5G_CH0___S 22 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0___M 0xFFC00000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH0___S 22 + +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1 (0x005D42A0) +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_LAA_TX_REQ_ISO_5G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_LAA_RX_USE_XLNA_5G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_IS_6G_5G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_WL_XPA_EN_5G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_WL_XPA_GAIN_5G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_WL_XLNA_EN_5G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_WL_XLNA_GAIN_5G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_LAA_TX_REQ_ISO_5G_CH1___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_LAA_TX_REQ_ISO_5G_CH1___S 31 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_LAA_RX_USE_XLNA_5G_CH1___M 0x40000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_LAA_RX_USE_XLNA_5G_CH1___S 30 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_IS_6G_5G_CH1___M 0x20000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_IS_6G_5G_CH1___S 29 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_WL_XPA_EN_5G_CH1___M 0x10000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_WL_XPA_EN_5G_CH1___S 28 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_WL_XPA_GAIN_5G_CH1___M 0x0F000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_WL_XPA_GAIN_5G_CH1___S 24 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_WL_XLNA_EN_5G_CH1___M 0x00800000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_WL_XLNA_EN_5G_CH1___S 23 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_WL_XLNA_GAIN_5G_CH1___M 0x00400000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1__RO_WL_XLNA_GAIN_5G_CH1___S 22 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1___M 0xFFC00000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_5G_CH1___S 22 + +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT (0x005D42A4) +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT__RO_BT_XPA_EN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT__RO_BT_XPA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT__RO_BT_RX_USE_BT_ANT___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT__RO_BT_XLNA_EN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT__RO_BT_XLNA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT__RO_BT_XPA_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT__RO_BT_XPA_EN___S 31 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT__RO_BT_XPA_GAIN___M 0x30000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT__RO_BT_XPA_GAIN___S 28 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT__RO_BT_RX_USE_BT_ANT___M 0x08000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT__RO_BT_RX_USE_BT_ANT___S 27 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT__RO_BT_XLNA_EN___M 0x04000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT__RO_BT_XLNA_EN___S 26 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT__RO_BT_XLNA_GAIN___M 0x03000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT__RO_BT_XLNA_GAIN___S 24 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT___M 0xBF000000 +#define PHYA_IRON2G_RFA_AON_XFEM_RO_XFEM_DBG_BT___S 24 + +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0 (0x005D42A8) +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_15___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_14___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_13___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_12___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_11___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_10___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_9___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_8___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_7___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_6___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_5___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_4___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_3___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_2___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_15___M 0xC0000000 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_15___S 30 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_14___M 0x30000000 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_14___S 28 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_13___M 0x0C000000 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_13___S 26 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_12___M 0x03000000 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_12___S 24 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_11___M 0x00C00000 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_11___S 22 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_10___M 0x00300000 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_10___S 20 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_9___M 0x000C0000 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_9___S 18 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_8___M 0x00030000 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_8___S 16 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_7___M 0x0000C000 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_7___S 14 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_6___M 0x00003000 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_6___S 12 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_5___M 0x00000C00 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_5___S 10 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_4___M 0x00000300 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_4___S 8 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_3___M 0x000000C0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_3___S 6 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_2___M 0x00000030 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_2___S 4 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_1___M 0x0000000C +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_1___S 2 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_0___M 0x00000003 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0__XFEM_FUNC_SEL_0___S 0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG0___S 0 + +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1 (0x005D42AC) +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_28___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_27___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_26___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_25___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_24___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_23___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_22___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_21___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_20___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_19___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_18___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_17___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_16___POR 0x0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_28___M 0x03000000 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_28___S 24 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_27___M 0x00C00000 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_27___S 22 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_26___M 0x00300000 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_26___S 20 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_25___M 0x000C0000 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_25___S 18 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_24___M 0x00030000 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_24___S 16 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_23___M 0x0000C000 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_23___S 14 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_22___M 0x00003000 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_22___S 12 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_21___M 0x00000C00 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_21___S 10 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_20___M 0x00000300 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_20___S 8 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_19___M 0x000000C0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_19___S 6 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_18___M 0x00000030 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_18___S 4 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_17___M 0x0000000C +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_17___S 2 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_16___M 0x00000003 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1__XFEM_FUNC_SEL_16___S 0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_PIN_CFG1___S 0 + +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_GPO_CFG (0x005D42B0) +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_GPO_CFG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_GPO_CFG___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_GPO_CFG__RFA_XFEM_GPO___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_GPO_CFG__RFA_XFEM_GPO___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_GPO_CFG__RFA_XFEM_GPO___S 0 +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_GPO_CFG___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_AON_XFEM_XFEM_GPO_CFG___S 0 + +#define PHYA_IRON2G_RFA_AON_COEX_COEX (0x005D42C0) +#define PHYA_IRON2G_RFA_AON_COEX_COEX___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_COEX_COEX___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_COEX_COEX__HW_DTIM_RX_MODE_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_COEX__HW_DTIM_RX_MODE_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_COEX__BT_CONTROL_SLNA_L_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_COEX__BT_CONTROL_SLNA_L_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_COEX__WLAN_CONTROL_EN_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_COEX__WLAN_CONTROL_EN_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_COEX__AOA_HIGH_PRI_WL_RX___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_COEX__HW_DTIM_RX_MODE_CH1_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_AON_COEX_COEX__HW_DTIM_RX_MODE_CH1_OVS___S 30 +#define PHYA_IRON2G_RFA_AON_COEX_COEX__HW_DTIM_RX_MODE_CH0_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_AON_COEX_COEX__HW_DTIM_RX_MODE_CH0_OVS___S 28 +#define PHYA_IRON2G_RFA_AON_COEX_COEX__BT_CONTROL_SLNA_L_CH1_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_AON_COEX_COEX__BT_CONTROL_SLNA_L_CH1_OVS___S 26 +#define PHYA_IRON2G_RFA_AON_COEX_COEX__BT_CONTROL_SLNA_L_CH0_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_AON_COEX_COEX__BT_CONTROL_SLNA_L_CH0_OVS___S 24 +#define PHYA_IRON2G_RFA_AON_COEX_COEX__WLAN_CONTROL_EN_CH1_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_AON_COEX_COEX__WLAN_CONTROL_EN_CH1_OVS___S 22 +#define PHYA_IRON2G_RFA_AON_COEX_COEX__WLAN_CONTROL_EN_CH0_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_AON_COEX_COEX__WLAN_CONTROL_EN_CH0_OVS___S 20 +#define PHYA_IRON2G_RFA_AON_COEX_COEX__AOA_HIGH_PRI_WL_RX___M 0x00000001 +#define PHYA_IRON2G_RFA_AON_COEX_COEX__AOA_HIGH_PRI_WL_RX___S 0 +#define PHYA_IRON2G_RFA_AON_COEX_COEX___M 0xFFF00001 +#define PHYA_IRON2G_RFA_AON_COEX_COEX___S 0 + +#define PHYA_IRON2G_RFA_AON_COEX_COEX_DBG (0x005D42C4) +#define PHYA_IRON2G_RFA_AON_COEX_COEX_DBG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_AON_COEX_COEX_DBG___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_COEX_COEX_DBG__COEX_CNT_RESET_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_COEX_DBG__COEX_CNT_RESET_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_COEX_DBG__COEX_CNT_RESET_CH0___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_COEX_COEX_DBG__COEX_CNT_RESET_CH0___S 31 +#define PHYA_IRON2G_RFA_AON_COEX_COEX_DBG__COEX_CNT_RESET_CH1___M 0x40000000 +#define PHYA_IRON2G_RFA_AON_COEX_COEX_DBG__COEX_CNT_RESET_CH1___S 30 +#define PHYA_IRON2G_RFA_AON_COEX_COEX_DBG___M 0xC0000000 +#define PHYA_IRON2G_RFA_AON_COEX_COEX_DBG___S 30 + +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0 (0x005D42C8) +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_WLAN_CONTROL_EN_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_CONTROL_SLNA_L_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_WLAN_ACTIVE_2G_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_HW_DTIM_SLNA_CTRL_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_DTIM_WIFI_PRI_HIGH_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_AOA_ACTIVE_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_WL_RX_EN_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_WL_TX_EN_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_RX_EN_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_USE_BT_LNA_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_RX_USE_BT_ANT_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_TX_EN_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_USE_BT_PA_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_TX_USE_BT_ANT_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_WLAN_CONTROL_EN_CH0___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_WLAN_CONTROL_EN_CH0___S 31 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_CONTROL_SLNA_L_CH0___M 0x40000000 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_CONTROL_SLNA_L_CH0___S 30 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_WLAN_ACTIVE_2G_CH0___M 0x00010000 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_WLAN_ACTIVE_2G_CH0___S 16 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_HW_DTIM_SLNA_CTRL_CH0___M 0x00008000 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_HW_DTIM_SLNA_CTRL_CH0___S 15 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_DTIM_WIFI_PRI_HIGH_CH0___M 0x00004000 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_DTIM_WIFI_PRI_HIGH_CH0___S 14 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_AOA_ACTIVE_CH0___M 0x00002000 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_AOA_ACTIVE_CH0___S 13 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_WL_RX_EN_CH0___M 0x00001000 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_WL_RX_EN_CH0___S 12 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_WL_TX_EN_CH0___M 0x00000800 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_WL_TX_EN_CH0___S 11 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_RX_EN_CH0___M 0x00000400 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_RX_EN_CH0___S 10 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_USE_BT_LNA_CH0___M 0x00000200 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_USE_BT_LNA_CH0___S 9 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_RX_USE_BT_ANT_CH0___M 0x00000100 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_RX_USE_BT_ANT_CH0___S 8 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_TX_EN_CH0___M 0x00000080 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_TX_EN_CH0___S 7 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_USE_BT_PA_CH0___M 0x00000040 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_USE_BT_PA_CH0___S 6 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_TX_USE_BT_ANT_CH0___M 0x00000020 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0__RO_BT_TX_USE_BT_ANT_CH0___S 5 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0___M 0xC001FFE0 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH0___S 5 + +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH0 (0x005D42CC) +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH0___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH0__RO_CNT_WLTX_BTTX_CH0___POR 0x00 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH0__RO_CNT_WLTX_BTRX_CH0___POR 0x00 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH0__RO_CNT_WLNOP_BTTX_CH0___POR 0x00 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH0__RO_CNT_WLNOP_BTRX_CH0___POR 0x00 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH0__RO_CNT_WLTX_BTTX_CH0___M 0xFF000000 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH0__RO_CNT_WLTX_BTTX_CH0___S 24 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH0__RO_CNT_WLTX_BTRX_CH0___M 0x00FF0000 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH0__RO_CNT_WLTX_BTRX_CH0___S 16 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH0__RO_CNT_WLNOP_BTTX_CH0___M 0x0000FF00 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH0__RO_CNT_WLNOP_BTTX_CH0___S 8 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH0__RO_CNT_WLNOP_BTRX_CH0___M 0x000000FF +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH0__RO_CNT_WLNOP_BTRX_CH0___S 0 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH0___S 0 + +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH0 (0x005D42D0) +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH0___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH0__RO_CNT_WLTX_CH0___POR 0x00 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH0__RO_CNT_WLRX_CH0___POR 0x00 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH0__RO_CNT_BTTX_CH0___POR 0x00 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH0__RO_CNT_BTRX_CH0___POR 0x00 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH0__RO_CNT_WLTX_CH0___M 0xFF000000 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH0__RO_CNT_WLTX_CH0___S 24 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH0__RO_CNT_WLRX_CH0___M 0x00FF0000 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH0__RO_CNT_WLRX_CH0___S 16 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH0__RO_CNT_BTTX_CH0___M 0x0000FF00 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH0__RO_CNT_BTTX_CH0___S 8 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH0__RO_CNT_BTRX_CH0___M 0x000000FF +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH0__RO_CNT_BTRX_CH0___S 0 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH0___S 0 + +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1 (0x005D42D4) +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_WLAN_CONTROL_EN_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_CONTROL_SLNA_L_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_WLAN_ACTIVE_2G_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_HW_DTIM_SLNA_CTRL_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_DTIM_WIFI_PRI_HIGH_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_AOA_ACTIVE_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_WL_RX_EN_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_WL_TX_EN_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_RX_EN_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_USE_BT_LNA_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_RX_USE_BT_ANT_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_TX_EN_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_USE_BT_PA_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_TX_USE_BT_ANT_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_WLAN_CONTROL_EN_CH1___M 0x80000000 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_WLAN_CONTROL_EN_CH1___S 31 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_CONTROL_SLNA_L_CH1___M 0x40000000 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_CONTROL_SLNA_L_CH1___S 30 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_WLAN_ACTIVE_2G_CH1___M 0x00010000 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_WLAN_ACTIVE_2G_CH1___S 16 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_HW_DTIM_SLNA_CTRL_CH1___M 0x00008000 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_HW_DTIM_SLNA_CTRL_CH1___S 15 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_DTIM_WIFI_PRI_HIGH_CH1___M 0x00004000 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_DTIM_WIFI_PRI_HIGH_CH1___S 14 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_AOA_ACTIVE_CH1___M 0x00002000 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_AOA_ACTIVE_CH1___S 13 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_WL_RX_EN_CH1___M 0x00001000 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_WL_RX_EN_CH1___S 12 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_WL_TX_EN_CH1___M 0x00000800 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_WL_TX_EN_CH1___S 11 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_RX_EN_CH1___M 0x00000400 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_RX_EN_CH1___S 10 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_USE_BT_LNA_CH1___M 0x00000200 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_USE_BT_LNA_CH1___S 9 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_RX_USE_BT_ANT_CH1___M 0x00000100 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_RX_USE_BT_ANT_CH1___S 8 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_TX_EN_CH1___M 0x00000080 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_TX_EN_CH1___S 7 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_USE_BT_PA_CH1___M 0x00000040 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_USE_BT_PA_CH1___S 6 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_TX_USE_BT_ANT_CH1___M 0x00000020 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1__RO_BT_TX_USE_BT_ANT_CH1___S 5 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1___M 0xC001FFE0 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG0_CH1___S 5 + +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH1 (0x005D42D8) +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH1___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH1__RO_CNT_WLTX_BTRX_CH1___POR 0x00 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH1__RO_CNT_WLNOP_BTRX_CH1___POR 0x00 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH1__RO_CNT_WLTX_BTRX_CH1___M 0x00FF0000 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH1__RO_CNT_WLTX_BTRX_CH1___S 16 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH1__RO_CNT_WLNOP_BTRX_CH1___M 0x000000FF +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH1__RO_CNT_WLNOP_BTRX_CH1___S 0 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH1___M 0x00FF00FF +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG1_CH1___S 0 + +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH1 (0x005D42DC) +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH1___POR 0x00000000 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH1__RO_CNT_WLTX_CH1___POR 0x00 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH1__RO_CNT_WLRX_CH1___POR 0x00 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH1__RO_CNT_BTRX_CH1___POR 0x00 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH1__RO_CNT_WLTX_CH1___M 0xFF000000 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH1__RO_CNT_WLTX_CH1___S 24 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH1__RO_CNT_WLRX_CH1___M 0x00FF0000 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH1__RO_CNT_WLRX_CH1___S 16 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH1__RO_CNT_BTRX_CH1___M 0x000000FF +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH1__RO_CNT_BTRX_CH1___S 0 +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH1___M 0xFFFF00FF +#define PHYA_IRON2G_RFA_AON_COEX_RO_COEX_DBG2_CH1___S 0 + +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE (0x005D4300) +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_ERR___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_PGEN_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_SMSG_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_RBUF1_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_RBUF0_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF5_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF4_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF3_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF2_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF1_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF0_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_ERR___M 0x00010000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_ERR___S 16 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_PGEN_DONE___M 0x00000800 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_PGEN_DONE___S 11 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_SMSG_DONE___M 0x00000400 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_SMSG_DONE___S 10 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_RBUF1_DONE___M 0x00000200 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_RBUF1_DONE___S 9 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_RBUF0_DONE___M 0x00000100 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_RBUF0_DONE___S 8 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF5_DONE___M 0x00000020 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF5_DONE___S 5 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF4_DONE___M 0x00000010 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF4_DONE___S 4 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF3_DONE___M 0x00000008 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF3_DONE___S 3 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF2_DONE___M 0x00000004 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF2_DONE___S 2 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF1_DONE___M 0x00000002 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF1_DONE___S 1 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF0_DONE___M 0x00000001 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE__INTE_WBUF0_DONE___S 0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE___M 0x00010F3F +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTE___S 0 + +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF (0x005D4304) +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_ERR___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_PGEN_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_SMSG_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_RBUF1_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_RBUF0_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF5_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF4_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF3_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF2_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF1_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF0_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_ERR___M 0x00010000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_ERR___S 16 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_PGEN_DONE___M 0x00000800 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_PGEN_DONE___S 11 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_SMSG_DONE___M 0x00000400 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_SMSG_DONE___S 10 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_RBUF1_DONE___M 0x00000200 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_RBUF1_DONE___S 9 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_RBUF0_DONE___M 0x00000100 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_RBUF0_DONE___S 8 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF5_DONE___M 0x00000020 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF5_DONE___S 5 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF4_DONE___M 0x00000010 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF4_DONE___S 4 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF3_DONE___M 0x00000008 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF3_DONE___S 3 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF2_DONE___M 0x00000004 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF2_DONE___S 2 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF1_DONE___M 0x00000002 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF1_DONE___S 1 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF0_DONE___M 0x00000001 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF__INTF_WBUF0_DONE___S 0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF___M 0x00010F3F +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_INTF___S 0 + +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT (0x005D4308) +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_RFFE_RELEASE_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_RFFE_RELEASE_GNT___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_STATE___POR 0x00 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_PERR3___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_PERR2___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_PERR1___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_PERR0___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_ACT___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_ERR___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_PGEN___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_SMSG___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_RBUF1___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_RBUF0___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF5___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF4___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF3___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF2___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF1___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF0___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_RFFE_RELEASE_REQ___M 0x80000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_RFFE_RELEASE_REQ___S 31 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_RFFE_RELEASE_GNT___M 0x40000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_RFFE_RELEASE_GNT___S 30 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_STATE___M 0x1F000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_STATE___S 24 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_PERR3___M 0x00800000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_PERR3___S 23 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_PERR2___M 0x00400000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_PERR2___S 22 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_PERR1___M 0x00200000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_PERR1___S 21 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_PERR0___M 0x00100000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_PERR0___S 20 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_ACT___M 0x00020000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_ACT___S 17 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_ERR___M 0x00010000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_ERR___S 16 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_PGEN___M 0x00000800 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_PGEN___S 11 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_SMSG___M 0x00000400 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_SMSG___S 10 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_RBUF1___M 0x00000200 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_RBUF1___S 9 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_RBUF0___M 0x00000100 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_RBUF0___S 8 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF5___M 0x00000020 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF5___S 5 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF4___M 0x00000010 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF4___S 4 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF3___M 0x00000008 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF3___S 3 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF2___M 0x00000004 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF2___S 2 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF1___M 0x00000002 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF1___S 1 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF0___M 0x00000001 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT__STAT_WBUF0___S 0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT___M 0xDFF30F3F +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_STAT___S 0 + +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG (0x005D430C) +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG___POR 0x00042431 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__READ_EVENT_ENABLES___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__WRITE_EVENT_ENABLES___POR 0x00 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__SHORT_MSG_EN___POR 0x1 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__MODE___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__PULSE_LEN___POR 0x4 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__PULSE_SKEW___POR 0x1 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__SW_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__SCLK_DIV___POR 0x03 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__READBACK_DELAY_EN___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__READBACK_HALF_RATE___POR 0x1 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__READ_EVENT_ENABLES___M 0x30000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__READ_EVENT_ENABLES___S 28 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__WRITE_EVENT_ENABLES___M 0x03F00000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__WRITE_EVENT_ENABLES___S 20 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__SHORT_MSG_EN___M 0x00040000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__SHORT_MSG_EN___S 18 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__MODE___M 0x00030000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__MODE___S 16 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__PULSE_LEN___M 0x00003800 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__PULSE_LEN___S 11 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__PULSE_SKEW___M 0x00000400 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__PULSE_SKEW___S 10 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__SW_RESET___M 0x00000200 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__SW_RESET___S 9 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__SCLK_DIV___M 0x000001F0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__SCLK_DIV___S 4 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__READBACK_DELAY_EN___M 0x00000002 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__READBACK_DELAY_EN___S 1 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__READBACK_HALF_RATE___M 0x00000001 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG__READBACK_HALF_RATE___S 0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG___M 0x33F73FF3 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CFG___S 0 + +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CTRL (0x005D4310) +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CTRL___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CTRL__PGEN_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CTRL__PGEN_REQ___M 0x00000001 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CTRL__PGEN_REQ___S 0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CTRL___M 0x00000001 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_CTRL___S 0 + +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO (0x005D4314) +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SCLK_IN___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SCLK_OUT___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SCLK_OE___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SDATA_IN___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SDATA_OUT___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SDATA_OE___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SCLK_IN___M 0x00000040 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SCLK_IN___S 6 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SCLK_OUT___M 0x00000020 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SCLK_OUT___S 5 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SCLK_OE___M 0x00000010 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SCLK_OE___S 4 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SDATA_IN___M 0x00000004 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SDATA_IN___S 2 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SDATA_OUT___M 0x00000002 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SDATA_OUT___S 1 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SDATA_OE___M 0x00000001 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO__GPIO_SDATA_OE___S 0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO___M 0x00000077 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_GPIO___S 0 + +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_SMSG (0x005D4318) +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_SMSG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_SMSG___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_SMSG__SMSG_SA___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_SMSG__SMSG_ADDR___POR 0x00 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_SMSG__SMSG_SA___M 0x00000F00 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_SMSG__SMSG_SA___S 8 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_SMSG__SMSG_ADDR___M 0x000000FF +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_SMSG__SMSG_ADDR___S 0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_SMSG___M 0x00000FFF +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_SMSG___S 0 + +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF0_CTRL (0x005D4340) +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF0_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF0_CTRL___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF0_CTRL__WBUF0_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF0_CTRL__WBUF0_SA___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF0_CTRL__WBUF0_ADDR___POR 0x0000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF0_CTRL__WBUF0_DATA___POR 0x00 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF0_CTRL__WBUF0_REQ___M 0x80000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF0_CTRL__WBUF0_REQ___S 31 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF0_CTRL__WBUF0_SA___M 0x0F000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF0_CTRL__WBUF0_SA___S 24 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF0_CTRL__WBUF0_ADDR___M 0x00FFFF00 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF0_CTRL__WBUF0_ADDR___S 8 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF0_CTRL__WBUF0_DATA___M 0x000000FF +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF0_CTRL__WBUF0_DATA___S 0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF0_CTRL___M 0x8FFFFFFF +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF0_CTRL___S 0 + +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF1_CTRL (0x005D4344) +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF1_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF1_CTRL___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF1_CTRL__WBUF1_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF1_CTRL__WBUF1_SA___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF1_CTRL__WBUF1_ADDR___POR 0x0000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF1_CTRL__WBUF1_DATA___POR 0x00 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF1_CTRL__WBUF1_REQ___M 0x80000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF1_CTRL__WBUF1_REQ___S 31 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF1_CTRL__WBUF1_SA___M 0x0F000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF1_CTRL__WBUF1_SA___S 24 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF1_CTRL__WBUF1_ADDR___M 0x00FFFF00 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF1_CTRL__WBUF1_ADDR___S 8 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF1_CTRL__WBUF1_DATA___M 0x000000FF +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF1_CTRL__WBUF1_DATA___S 0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF1_CTRL___M 0x8FFFFFFF +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF1_CTRL___S 0 + +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF2_CTRL (0x005D4348) +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF2_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF2_CTRL___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF2_CTRL__WBUF2_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF2_CTRL__WBUF2_SA___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF2_CTRL__WBUF2_ADDR___POR 0x0000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF2_CTRL__WBUF2_DATA___POR 0x00 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF2_CTRL__WBUF2_REQ___M 0x80000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF2_CTRL__WBUF2_REQ___S 31 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF2_CTRL__WBUF2_SA___M 0x0F000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF2_CTRL__WBUF2_SA___S 24 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF2_CTRL__WBUF2_ADDR___M 0x00FFFF00 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF2_CTRL__WBUF2_ADDR___S 8 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF2_CTRL__WBUF2_DATA___M 0x000000FF +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF2_CTRL__WBUF2_DATA___S 0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF2_CTRL___M 0x8FFFFFFF +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF2_CTRL___S 0 + +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF3_CTRL (0x005D434C) +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF3_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF3_CTRL___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF3_CTRL__WBUF3_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF3_CTRL__WBUF3_SA___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF3_CTRL__WBUF3_ADDR___POR 0x0000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF3_CTRL__WBUF3_DATA___POR 0x00 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF3_CTRL__WBUF3_REQ___M 0x80000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF3_CTRL__WBUF3_REQ___S 31 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF3_CTRL__WBUF3_SA___M 0x0F000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF3_CTRL__WBUF3_SA___S 24 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF3_CTRL__WBUF3_ADDR___M 0x00FFFF00 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF3_CTRL__WBUF3_ADDR___S 8 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF3_CTRL__WBUF3_DATA___M 0x000000FF +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF3_CTRL__WBUF3_DATA___S 0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF3_CTRL___M 0x8FFFFFFF +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF3_CTRL___S 0 + +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_DATA (0x005D4350) +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_DATA___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_DATA___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_DATA__WBUF4_DATA___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_DATA__WBUF4_DATA___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_DATA__WBUF4_DATA___S 0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_DATA___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_DATA___S 0 + +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_CTRL (0x005D4354) +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_CTRL___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_CTRL__WBUF4_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_CTRL__WBUF4_SA___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_CTRL__WBUF4_BYTECNT___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_CTRL__WBUF4_ADDR___POR 0x0000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_CTRL__WBUF4_REQ___M 0x80000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_CTRL__WBUF4_REQ___S 31 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_CTRL__WBUF4_SA___M 0x0F000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_CTRL__WBUF4_SA___S 24 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_CTRL__WBUF4_BYTECNT___M 0x00030000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_CTRL__WBUF4_BYTECNT___S 16 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_CTRL__WBUF4_ADDR___M 0x0000FFFF +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_CTRL__WBUF4_ADDR___S 0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_CTRL___M 0x8F03FFFF +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF4_CTRL___S 0 + +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_DATA (0x005D4358) +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_DATA___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_DATA___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_DATA__WBUF5_DATA___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_DATA__WBUF5_DATA___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_DATA__WBUF5_DATA___S 0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_DATA___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_DATA___S 0 + +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_CTRL (0x005D435C) +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_CTRL___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_CTRL__WBUF5_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_CTRL__WBUF5_SA___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_CTRL__WBUF5_BYTECNT___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_CTRL__WBUF5_ADDR___POR 0x0000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_CTRL__WBUF5_REQ___M 0x80000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_CTRL__WBUF5_REQ___S 31 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_CTRL__WBUF5_SA___M 0x0F000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_CTRL__WBUF5_SA___S 24 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_CTRL__WBUF5_BYTECNT___M 0x00030000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_CTRL__WBUF5_BYTECNT___S 16 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_CTRL__WBUF5_ADDR___M 0x0000FFFF +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_CTRL__WBUF5_ADDR___S 0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_CTRL___M 0x8F03FFFF +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_WBUF5_CTRL___S 0 + +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_CTRL (0x005D4380) +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_CTRL___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_CTRL__RBUF0_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_CTRL__RBUF0_SA___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_CTRL__RBUF0_BYTECNT___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_CTRL__RBUF0_ADDR___POR 0x0000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_CTRL__RBUF0_REQ___M 0x80000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_CTRL__RBUF0_REQ___S 31 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_CTRL__RBUF0_SA___M 0x0F000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_CTRL__RBUF0_SA___S 24 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_CTRL__RBUF0_BYTECNT___M 0x00030000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_CTRL__RBUF0_BYTECNT___S 16 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_CTRL__RBUF0_ADDR___M 0x0000FFFF +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_CTRL__RBUF0_ADDR___S 0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_CTRL___M 0x8F03FFFF +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_CTRL___S 0 + +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_CTRL (0x005D4384) +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_CTRL___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_CTRL__RBUF1_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_CTRL__RBUF1_SA___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_CTRL__RBUF1_BYTECNT___POR 0x0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_CTRL__RBUF1_ADDR___POR 0x0000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_CTRL__RBUF1_REQ___M 0x80000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_CTRL__RBUF1_REQ___S 31 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_CTRL__RBUF1_SA___M 0x0F000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_CTRL__RBUF1_SA___S 24 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_CTRL__RBUF1_BYTECNT___M 0x00030000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_CTRL__RBUF1_BYTECNT___S 16 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_CTRL__RBUF1_ADDR___M 0x0000FFFF +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_CTRL__RBUF1_ADDR___S 0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_CTRL___M 0x8F03FFFF +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_CTRL___S 0 + +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_DATA (0x005D4388) +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_DATA___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_DATA___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_DATA__RBUF0_DATA___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_DATA__RBUF0_DATA___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_DATA__RBUF0_DATA___S 0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_DATA___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF0_DATA___S 0 + +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_DATA (0x005D438C) +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_DATA___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_DATA___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_DATA__RBUF1_DATA___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_DATA__RBUF1_DATA___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_DATA__RBUF1_DATA___S 0 +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_DATA___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RFFE_M_RFFE_RBUF1_DATA___S 0 + +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD0 (0x005D4400) +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD0___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD0__RFA_SHD_OTP_WORD0___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD0__RFA_SHD_OTP_WORD0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD0__RFA_SHD_OTP_WORD0___S 0 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD0___S 0 + +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD1 (0x005D4404) +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD1___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD1__RFA_SHD_OTP_WORD1___POR 0x000000 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD1__RFA_SHD_OTP_WORD1___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD1__RFA_SHD_OTP_WORD1___S 0 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD1___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD1___S 0 + +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD2 (0x005D4408) +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD2___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD2__RFA_SHD_OTP_WORD2___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD2__RFA_SHD_OTP_WORD2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD2__RFA_SHD_OTP_WORD2___S 0 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD2___S 0 + +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD3 (0x005D440C) +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD3___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD3__RFA_SHD_OTP_WORD3___POR 0x000000 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD3__RFA_SHD_OTP_WORD3___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD3__RFA_SHD_OTP_WORD3___S 0 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD3___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD3___S 0 + +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD4 (0x005D4410) +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD4___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD4__RFA_SHD_OTP_WORD4___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD4__RFA_SHD_OTP_WORD4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD4__RFA_SHD_OTP_WORD4___S 0 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD4___S 0 + +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD5 (0x005D4414) +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD5___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD5__RFA_SHD_OTP_WORD5___POR 0x000000 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD5__RFA_SHD_OTP_WORD5___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD5__RFA_SHD_OTP_WORD5___S 0 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD5___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD5___S 0 + +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD6 (0x005D4418) +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD6___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD6__RFA_SHD_OTP_WORD6___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD6__RFA_SHD_OTP_WORD6___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD6__RFA_SHD_OTP_WORD6___S 0 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD6___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD6___S 0 + +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD7 (0x005D441C) +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD7___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD7__RFA_SHD_OTP_WORD7___POR 0x000000 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD7__RFA_SHD_OTP_WORD7___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD7__RFA_SHD_OTP_WORD7___S 0 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD7___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD7___S 0 + +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD8 (0x005D4420) +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD8___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD8__RFA_SHD_OTP_WORD8___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD8__RFA_SHD_OTP_WORD8___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD8__RFA_SHD_OTP_WORD8___S 0 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD8___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD8___S 0 + +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD9 (0x005D4424) +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD9___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD9__RFA_SHD_OTP_WORD9___POR 0x000000 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD9__RFA_SHD_OTP_WORD9___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD9__RFA_SHD_OTP_WORD9___S 0 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD9___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD9___S 0 + +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD10 (0x005D4428) +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD10___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD10__RFA_SHD_OTP_WORD10___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD10__RFA_SHD_OTP_WORD10___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD10__RFA_SHD_OTP_WORD10___S 0 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD10___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD10___S 0 + +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD11 (0x005D442C) +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD11___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD11__RFA_SHD_OTP_WORD11___POR 0x000000 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD11__RFA_SHD_OTP_WORD11___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD11__RFA_SHD_OTP_WORD11___S 0 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD11___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD11___S 0 + +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD12 (0x005D4430) +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD12___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD12__RFA_SHD_OTP_WORD12___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD12__RFA_SHD_OTP_WORD12___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD12__RFA_SHD_OTP_WORD12___S 0 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD12___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD12___S 0 + +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD13 (0x005D4434) +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD13___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD13__RFA_SHD_OTP_WORD13___POR 0x000000 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD13__RFA_SHD_OTP_WORD13___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD13__RFA_SHD_OTP_WORD13___S 0 +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD13___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_RFA_SHD_OTP_RFA_SHD_OTP_WORD13___S 0 + +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0 (0x005D4480) +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_BOOTUP_PARAM_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_CLK_SEL_PARAM_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_BG_PARAM_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_LDO_PARAM_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_XO_PARAM_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_DLL_PARAM_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_JITTER_PARAM_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__XO_CAP_CUSTOM_OVERWRITE_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__XO_SETTLE_CUSTOM_OVERWRITE_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_BOOTUP_PARAM_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_BOOTUP_PARAM_OVS___S 30 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_CLK_SEL_PARAM_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_CLK_SEL_PARAM_OVS___S 28 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_BG_PARAM_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_BG_PARAM_OVS___S 26 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_LDO_PARAM_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_LDO_PARAM_OVS___S 24 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_XO_PARAM_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_XO_PARAM_OVS___S 22 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_DLL_PARAM_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_DLL_PARAM_OVS___S 20 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_JITTER_PARAM_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__APPLY_JITTER_PARAM_OVS___S 18 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__XO_CAP_CUSTOM_OVERWRITE_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__XO_CAP_CUSTOM_OVERWRITE_OVS___S 16 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__XO_SETTLE_CUSTOM_OVERWRITE_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0__XO_SETTLE_CUSTOM_OVERWRITE_OVS___S 14 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0___M 0xFFFFC000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_0___S 14 + +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1 (0x005D4484) +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TCXO_MODE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__CLK_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__CLK_OUT_FREQ_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_PTT_RCODE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_PTT_ICTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGT_PTAT_CODE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGU_PTAT_CODE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGT_CTATN_CODE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGT_CTATP_CODE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGU_CTATN_CODE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGU_CTATP_CODE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGT_ICTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGU_ICTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_CDACIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_CDACOUT_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_BUF_P_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_BUF_N_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_FLTRBWSW_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_DBLR_SEL_EDGE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_SLOPE_TRIM_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_BIAS_TRIM_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_GM_TRIM_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_DCC_VAR_DEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_DCC_VAR_DEL_96M_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_BUF_P_TCXO_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_BUF_N_TCXO_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__DLL_CLK_DRV_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__DLL_CLK_MUX_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__DLL_DIFF_EN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__DCC_OFF_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_LDO13_VSEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_LDO08_VSEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TCXO_MODE_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TCXO_MODE_OV___S 31 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__CLK_SEL_OV___M 0x40000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__CLK_SEL_OV___S 30 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__CLK_OUT_FREQ_SEL_OV___M 0x20000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__CLK_OUT_FREQ_SEL_OV___S 29 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_PTT_RCODE_OV___M 0x10000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_PTT_RCODE_OV___S 28 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_PTT_ICTRL_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_PTT_ICTRL_OV___S 27 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGT_PTAT_CODE_OV___M 0x04000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGT_PTAT_CODE_OV___S 26 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGU_PTAT_CODE_OV___M 0x02000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGU_PTAT_CODE_OV___S 25 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGT_CTATN_CODE_OV___M 0x01000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGT_CTATN_CODE_OV___S 24 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGT_CTATP_CODE_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGT_CTATP_CODE_OV___S 23 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGU_CTATN_CODE_OV___M 0x00400000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGU_CTATN_CODE_OV___S 22 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGU_CTATP_CODE_OV___M 0x00200000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGU_CTATP_CODE_OV___S 21 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGT_ICTRL_OV___M 0x00100000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGT_ICTRL_OV___S 20 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGU_ICTRL_OV___M 0x00080000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__TOP_BGU_ICTRL_OV___S 19 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_CDACIN_OV___M 0x00040000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_CDACIN_OV___S 18 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_CDACOUT_OV___M 0x00020000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_CDACOUT_OV___S 17 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_BUF_P_OV___M 0x00010000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_BUF_P_OV___S 16 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_BUF_N_OV___M 0x00008000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_BUF_N_OV___S 15 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_FLTRBWSW_OV___M 0x00004000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_FLTRBWSW_OV___S 14 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_DBLR_SEL_EDGE_OV___M 0x00002000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_DBLR_SEL_EDGE_OV___S 13 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_SLOPE_TRIM_OV___M 0x00001000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_SLOPE_TRIM_OV___S 12 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_BIAS_TRIM_OV___M 0x00000800 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_BIAS_TRIM_OV___S 11 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_GM_TRIM_OV___M 0x00000400 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_GM_TRIM_OV___S 10 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_DCC_VAR_DEL_OV___M 0x00000200 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_DCC_VAR_DEL_OV___S 9 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_DCC_VAR_DEL_96M_OV___M 0x00000100 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_DCC_VAR_DEL_96M_OV___S 8 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_BUF_P_TCXO_OV___M 0x00000080 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_BUF_P_TCXO_OV___S 7 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_BUF_N_TCXO_OV___M 0x00000040 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_BUF_N_TCXO_OV___S 6 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__DLL_CLK_DRV_OV___M 0x00000020 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__DLL_CLK_DRV_OV___S 5 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__DLL_CLK_MUX_SEL_OV___M 0x00000010 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__DLL_CLK_MUX_SEL_OV___S 4 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__DLL_DIFF_EN_OV___M 0x00000008 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__DLL_DIFF_EN_OV___S 3 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__DCC_OFF_OV___M 0x00000004 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__DCC_OFF_OV___S 2 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_LDO13_VSEL_OV___M 0x00000002 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_LDO13_VSEL_OV___S 1 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_LDO08_VSEL_OV___M 0x00000001 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1__XO_LDO08_VSEL_OV___S 0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_1___S 0 + +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2 (0x005D4488) +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__XO_LDO13_ICTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__XO_LDO08_ICTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__XO_VREF_BWSEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__XO_VREF_VSEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH2_SDM_VREF_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO0_WL_DPLL_VREF_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO1_WL_DPLL_VREF_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO2_WL_DPLL_VREF_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO0_BT_DPLL_VREF_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO1_BT_DPLL_VREF_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO2_BT_DPLL_VREF_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_RXLO_VREF_2G_CH0_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_RXLO_VREF_5G_CH0_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_RXLO_VREF_2G_CH1_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_RXLO_VREF_5G_CH1_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_TXLO_VREF_2G_CH0_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_TXLO_VREF_5G_CH0_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_TXLO_VREF_2G_CH1_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_TXLO_VREF_5G_CH1_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_DAC_VREF_2G_CH0_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_DAC_VREF_5G_CH0_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_DAC_VREF_2G_CH1_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_DAC_VREF_5G_CH1_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_ADC_VREF_2G_CH0_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_ADC_VREF_5G_CH0_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_ADC_VREF_2G_CH1_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_ADC_VREF_5G_CH1_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_BT_TXLO_VREF_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH0_LOGEN_VREF_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH1_LOGEN_VREF_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH0_VREF_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH1_VREF_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__XO_LDO13_ICTRL_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__XO_LDO13_ICTRL_OV___S 31 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__XO_LDO08_ICTRL_OV___M 0x40000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__XO_LDO08_ICTRL_OV___S 30 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__XO_VREF_BWSEL_OV___M 0x20000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__XO_VREF_BWSEL_OV___S 29 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__XO_VREF_VSEL_OV___M 0x10000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__XO_VREF_VSEL_OV___S 28 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH2_SDM_VREF_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH2_SDM_VREF_OV___S 27 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO0_WL_DPLL_VREF_OV___M 0x04000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO0_WL_DPLL_VREF_OV___S 26 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO1_WL_DPLL_VREF_OV___M 0x02000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO1_WL_DPLL_VREF_OV___S 25 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO2_WL_DPLL_VREF_OV___M 0x01000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO2_WL_DPLL_VREF_OV___S 24 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO0_BT_DPLL_VREF_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO0_BT_DPLL_VREF_OV___S 23 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO1_BT_DPLL_VREF_OV___M 0x00400000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO1_BT_DPLL_VREF_OV___S 22 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO2_BT_DPLL_VREF_OV___M 0x00200000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO2_BT_DPLL_VREF_OV___S 21 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_RXLO_VREF_2G_CH0_OV___M 0x00100000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_RXLO_VREF_2G_CH0_OV___S 20 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_RXLO_VREF_5G_CH0_OV___M 0x00080000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_RXLO_VREF_5G_CH0_OV___S 19 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_RXLO_VREF_2G_CH1_OV___M 0x00040000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_RXLO_VREF_2G_CH1_OV___S 18 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_RXLO_VREF_5G_CH1_OV___M 0x00020000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_RXLO_VREF_5G_CH1_OV___S 17 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_TXLO_VREF_2G_CH0_OV___M 0x00010000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_TXLO_VREF_2G_CH0_OV___S 16 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_TXLO_VREF_5G_CH0_OV___M 0x00008000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_TXLO_VREF_5G_CH0_OV___S 15 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_TXLO_VREF_2G_CH1_OV___M 0x00004000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_TXLO_VREF_2G_CH1_OV___S 14 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_TXLO_VREF_5G_CH1_OV___M 0x00002000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_TXLO_VREF_5G_CH1_OV___S 13 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_DAC_VREF_2G_CH0_OV___M 0x00001000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_DAC_VREF_2G_CH0_OV___S 12 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_DAC_VREF_5G_CH0_OV___M 0x00000800 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_DAC_VREF_5G_CH0_OV___S 11 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_DAC_VREF_2G_CH1_OV___M 0x00000400 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_DAC_VREF_2G_CH1_OV___S 10 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_DAC_VREF_5G_CH1_OV___M 0x00000200 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_DAC_VREF_5G_CH1_OV___S 9 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_ADC_VREF_2G_CH0_OV___M 0x00000100 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_ADC_VREF_2G_CH0_OV___S 8 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_ADC_VREF_5G_CH0_OV___M 0x00000080 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_ADC_VREF_5G_CH0_OV___S 7 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_ADC_VREF_2G_CH1_OV___M 0x00000040 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_ADC_VREF_2G_CH1_OV___S 6 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_ADC_VREF_5G_CH1_OV___M 0x00000020 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_ADC_VREF_5G_CH1_OV___S 5 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_BT_TXLO_VREF_OV___M 0x00000010 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_BT_TXLO_VREF_OV___S 4 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH0_LOGEN_VREF_OV___M 0x00000008 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH0_LOGEN_VREF_OV___S 3 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH1_LOGEN_VREF_OV___M 0x00000004 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH1_LOGEN_VREF_OV___S 2 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH0_VREF_OV___M 0x00000002 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH0_VREF_OV___S 1 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH1_VREF_OV___M 0x00000001 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2__LDO_WL_SYNTH1_VREF_OV___S 0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_2___S 0 + +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3 (0x005D448C) +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__LDO_WL_SYNTH2_VREF_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__LDO_BT_SYNTH_REFGEN_VREF_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__LDO_BT_SYNTH_LOLDO_VREF06_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__SETTIME_BGT_EN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__SETTIME_TOP_STARTUP_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__SETTIME_TOP_FC_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__TOP_STARTUP_WIDTH_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__TOP_FC_WIDTH_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__TOP_BIAS_SETTLE_TIME_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__XO_SETTLE_TIME_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__DBLR_SETTLE_TIME_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__TCXO_SETTLE_TIME_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__XO_LDO_SETTLE_TIME_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__WL_LDO_SETTLE_TIME_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__BT_LDO_SETTLE_TIME_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__CM_LDO_SETTLE_TIME_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__BBPLL_LDO_SETTLE_TIME_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__BTFMPLL_LDO_SETTLE_TIME_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__BBPLL_SETTLE_TIME_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__BTFMPLL_SETTLE_TIME_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__SETTIME_XO_FC_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__JITTER_WAR_DISABLE_WL_BBPLL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__JITTER_WAR_TMR_SEL_WL_BBPLL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__JITTER_WAR_DISABLE_BTFMPLL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__JITTER_WAR_TMR_SEL_BTFMPLL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__LDO_WL_SYNTH2_VREF_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__LDO_WL_SYNTH2_VREF_OV___S 31 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__LDO_BT_SYNTH_REFGEN_VREF_OV___M 0x40000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__LDO_BT_SYNTH_REFGEN_VREF_OV___S 30 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__LDO_BT_SYNTH_LOLDO_VREF06_OV___M 0x20000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__LDO_BT_SYNTH_LOLDO_VREF06_OV___S 29 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__SETTIME_BGT_EN_OV___M 0x10000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__SETTIME_BGT_EN_OV___S 28 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__SETTIME_TOP_STARTUP_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__SETTIME_TOP_STARTUP_OV___S 27 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__SETTIME_TOP_FC_OV___M 0x04000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__SETTIME_TOP_FC_OV___S 26 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__TOP_STARTUP_WIDTH_OV___M 0x02000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__TOP_STARTUP_WIDTH_OV___S 25 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__TOP_FC_WIDTH_OV___M 0x01000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__TOP_FC_WIDTH_OV___S 24 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__TOP_BIAS_SETTLE_TIME_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__TOP_BIAS_SETTLE_TIME_OV___S 23 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__XO_SETTLE_TIME_OV___M 0x00400000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__XO_SETTLE_TIME_OV___S 22 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__DBLR_SETTLE_TIME_OV___M 0x00200000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__DBLR_SETTLE_TIME_OV___S 21 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__TCXO_SETTLE_TIME_OV___M 0x00100000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__TCXO_SETTLE_TIME_OV___S 20 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__XO_LDO_SETTLE_TIME_OV___M 0x00080000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__XO_LDO_SETTLE_TIME_OV___S 19 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__WL_LDO_SETTLE_TIME_OV___M 0x00040000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__WL_LDO_SETTLE_TIME_OV___S 18 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__BT_LDO_SETTLE_TIME_OV___M 0x00020000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__BT_LDO_SETTLE_TIME_OV___S 17 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__CM_LDO_SETTLE_TIME_OV___M 0x00010000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__CM_LDO_SETTLE_TIME_OV___S 16 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__BBPLL_LDO_SETTLE_TIME_OV___M 0x00008000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__BBPLL_LDO_SETTLE_TIME_OV___S 15 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__BTFMPLL_LDO_SETTLE_TIME_OV___M 0x00004000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__BTFMPLL_LDO_SETTLE_TIME_OV___S 14 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__BBPLL_SETTLE_TIME_OV___M 0x00002000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__BBPLL_SETTLE_TIME_OV___S 13 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__BTFMPLL_SETTLE_TIME_OV___M 0x00001000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__BTFMPLL_SETTLE_TIME_OV___S 12 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__SETTIME_XO_FC_OV___M 0x00000800 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__SETTIME_XO_FC_OV___S 11 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__JITTER_WAR_DISABLE_WL_BBPLL_OV___M 0x00000400 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__JITTER_WAR_DISABLE_WL_BBPLL_OV___S 10 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__JITTER_WAR_TMR_SEL_WL_BBPLL_OV___M 0x00000200 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__JITTER_WAR_TMR_SEL_WL_BBPLL_OV___S 9 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__JITTER_WAR_DISABLE_BTFMPLL_OV___M 0x00000100 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__JITTER_WAR_DISABLE_BTFMPLL_OV___S 8 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__JITTER_WAR_TMR_SEL_BTFMPLL_OV___M 0x00000080 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3__JITTER_WAR_TMR_SEL_BTFMPLL_OV___S 7 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3___M 0xFFFFFF80 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_OV_3___S 7 + +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL (0x005D4490) +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL___POR 0x30000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL__TCXO_MODE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL__CLK_SEL_OVD___POR 0x3 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL__CLK_OUT_FREQ_SEL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL__TCXO_MODE_OVD___M 0x80000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL__TCXO_MODE_OVD___S 31 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL__CLK_SEL_OVD___M 0x70000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL__CLK_SEL_OVD___S 28 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL__CLK_OUT_FREQ_SEL_OVD___M 0x0C000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL__CLK_OUT_FREQ_SEL_OVD___S 26 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL___M 0xFC000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_CLK_SEL___S 26 + +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_0 (0x005D4494) +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_0___POR 0x87C1214C +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_0__TOP_PTT_RCODE_OVD___POR 0x87 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_0__TOP_PTT_ICTRL_OVD___POR 0x3 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_0__TOP_BGT_PTAT_CODE_OVD___POR 0x90 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_0__TOP_BGU_PTAT_CODE_OVD___POR 0xA6 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_0__TOP_PTT_RCODE_OVD___M 0xFF000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_0__TOP_PTT_RCODE_OVD___S 24 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_0__TOP_PTT_ICTRL_OVD___M 0x00C00000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_0__TOP_PTT_ICTRL_OVD___S 22 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_0__TOP_BGT_PTAT_CODE_OVD___M 0x0001FE00 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_0__TOP_BGT_PTAT_CODE_OVD___S 9 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_0__TOP_BGU_PTAT_CODE_OVD___M 0x000001FE +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_0__TOP_BGU_PTAT_CODE_OVD___S 1 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_0___M 0xFFC1FFFE +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_0___S 1 + +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1 (0x005D4498) +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1___POR 0x7DF71CF0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGT_CTATN_CODE_OVD___POR 0x1F +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGT_CTATP_CODE_OVD___POR 0x1F +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGU_CTATN_CODE_OVD___POR 0x1C +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGU_CTATP_CODE_OVD___POR 0x1C +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGT_ICTRL_OVD___POR 0x3 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGU_ICTRL_OVD___POR 0x3 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGT_CTATN_CODE_OVD___M 0xFC000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGT_CTATN_CODE_OVD___S 26 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGT_CTATP_CODE_OVD___M 0x03F00000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGT_CTATP_CODE_OVD___S 20 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGU_CTATN_CODE_OVD___M 0x000FC000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGU_CTATN_CODE_OVD___S 14 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGU_CTATP_CODE_OVD___M 0x00003F00 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGU_CTATP_CODE_OVD___S 8 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGT_ICTRL_OVD___M 0x000000C0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGT_ICTRL_OVD___S 6 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGU_ICTRL_OVD___M 0x00000030 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1__TOP_BGU_ICTRL_OVD___S 4 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1___M 0xFFFFFFF0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BG_1___S 4 + +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0 (0x005D449C) +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0___POR 0x7FDFE840 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_CDACIN_OVD___POR 0x1FF +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_CDACOUT_OVD___POR 0x0FF +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_BUF_P_OVD___POR 0x4 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_BUF_N_OVD___POR 0x2 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_FLTRBWSW_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_DBLR_SEL_EDGE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_CDACIN_OVD___M 0xFFC00000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_CDACIN_OVD___S 22 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_CDACOUT_OVD___M 0x003FE000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_CDACOUT_OVD___S 13 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_BUF_P_OVD___M 0x00001E00 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_BUF_P_OVD___S 9 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_BUF_N_OVD___M 0x000001E0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_BUF_N_OVD___S 5 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_FLTRBWSW_OVD___M 0x00000018 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_FLTRBWSW_OVD___S 3 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_DBLR_SEL_EDGE_OVD___M 0x00000004 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0__XO_DBLR_SEL_EDGE_OVD___S 2 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_0___S 2 + +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1 (0x005D44A0) +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1___POR 0x089C1100 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_SLOPE_TRIM_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_BIAS_TRIM_OVD___POR 0x4 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_GM_TRIM_OVD___POR 0x4 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_DCC_VAR_DEL_OVD___POR 0x7 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_DCC_VAR_DEL_96M_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_BUF_P_TCXO_OVD___POR 0x2 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_BUF_N_TCXO_OVD___POR 0x2 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_SLOPE_TRIM_OVD___M 0xF0000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_SLOPE_TRIM_OVD___S 28 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_BIAS_TRIM_OVD___M 0x0E000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_BIAS_TRIM_OVD___S 25 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_GM_TRIM_OVD___M 0x00E00000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_GM_TRIM_OVD___S 21 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_DCC_VAR_DEL_OVD___M 0x001C0000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_DCC_VAR_DEL_OVD___S 18 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_DCC_VAR_DEL_96M_OVD___M 0x00038000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_DCC_VAR_DEL_96M_OVD___S 15 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_BUF_P_TCXO_OVD___M 0x00007800 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_BUF_P_TCXO_OVD___S 11 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_BUF_N_TCXO_OVD___M 0x00000780 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1__XO_BUF_N_TCXO_OVD___S 7 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1___M 0xFEFFFF80 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_XO_1___S 7 + +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DLL (0x005D44A4) +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DLL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DLL___POR 0xD8000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DLL__DLL_CLK_DRV_OVD___POR 0x3 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DLL__DLL_CLK_MUX_SEL_OVD___POR 0x3 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DLL__DLL_DIFF_EN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DLL__DCC_OFF_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DLL__DLL_CLK_DRV_OVD___M 0xC0000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DLL__DLL_CLK_DRV_OVD___S 30 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DLL__DLL_CLK_MUX_SEL_OVD___M 0x38000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DLL__DLL_CLK_MUX_SEL_OVD___S 27 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DLL__DLL_DIFF_EN_OVD___M 0x04000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DLL__DLL_DIFF_EN_OVD___S 26 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DLL__DCC_OFF_OVD___M 0x02000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DLL__DCC_OFF_OVD___S 25 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DLL___M 0xFE000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DLL___S 25 + +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0 (0x005D44A8) +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0___POR 0x81446800 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_LDO13_VSEL_OVD___POR 0x8 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_LDO08_VSEL_OVD___POR 0x1 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_LDO13_ICTRL_OVD___POR 0x2 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_LDO08_ICTRL_OVD___POR 0x1 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_VREF_BWSEL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_VREF_VSEL_OVD___POR 0x3 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__LDO_WL_SYNTH2_SDM_VREF_OVD___POR 0x4 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_LDO13_VSEL_OVD___M 0xF0000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_LDO13_VSEL_OVD___S 28 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_LDO08_VSEL_OVD___M 0x0F000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_LDO08_VSEL_OVD___S 24 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_LDO13_ICTRL_OVD___M 0x00E00000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_LDO13_ICTRL_OVD___S 21 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_LDO08_ICTRL_OVD___M 0x001C0000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_LDO08_ICTRL_OVD___S 18 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_VREF_BWSEL_OVD___M 0x00030000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_VREF_BWSEL_OVD___S 16 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_VREF_VSEL_OVD___M 0x0000E000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__XO_VREF_VSEL_OVD___S 13 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__LDO_WL_SYNTH2_SDM_VREF_OVD___M 0x00001E00 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0__LDO_WL_SYNTH2_SDM_VREF_OVD___S 9 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_0___S 9 + +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1 (0x005D44AC) +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1___POR 0x5A55A544 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO0_WL_DPLL_VREF_OVD___POR 0x5 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO1_WL_DPLL_VREF_OVD___POR 0xA +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO2_WL_DPLL_VREF_OVD___POR 0x5 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO0_BT_DPLL_VREF_OVD___POR 0x5 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO1_BT_DPLL_VREF_OVD___POR 0xA +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO2_BT_DPLL_VREF_OVD___POR 0x5 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO_WL_RXLO_VREF_2G_CH0_OVD___POR 0x4 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO_WL_RXLO_VREF_5G_CH0_OVD___POR 0x4 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO0_WL_DPLL_VREF_OVD___M 0xF0000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO0_WL_DPLL_VREF_OVD___S 28 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO1_WL_DPLL_VREF_OVD___M 0x0F000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO1_WL_DPLL_VREF_OVD___S 24 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO2_WL_DPLL_VREF_OVD___M 0x00F00000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO2_WL_DPLL_VREF_OVD___S 20 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO0_BT_DPLL_VREF_OVD___M 0x000F0000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO0_BT_DPLL_VREF_OVD___S 16 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO1_BT_DPLL_VREF_OVD___M 0x0000F000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO1_BT_DPLL_VREF_OVD___S 12 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO2_BT_DPLL_VREF_OVD___M 0x00000F00 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO2_BT_DPLL_VREF_OVD___S 8 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO_WL_RXLO_VREF_2G_CH0_OVD___M 0x000000F0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO_WL_RXLO_VREF_2G_CH0_OVD___S 4 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO_WL_RXLO_VREF_5G_CH0_OVD___M 0x0000000F +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1__LDO_WL_RXLO_VREF_5G_CH0_OVD___S 0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_1___S 0 + +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2 (0x005D44B0) +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2___POR 0x447777BB +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_RXLO_VREF_2G_CH1_OVD___POR 0x4 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_RXLO_VREF_5G_CH1_OVD___POR 0x4 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_TXLO_VREF_2G_CH0_OVD___POR 0x7 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_TXLO_VREF_5G_CH0_OVD___POR 0x7 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_TXLO_VREF_2G_CH1_OVD___POR 0x7 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_TXLO_VREF_5G_CH1_OVD___POR 0x7 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_DAC_VREF_2G_CH0_OVD___POR 0xB +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_DAC_VREF_5G_CH0_OVD___POR 0xB +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_RXLO_VREF_2G_CH1_OVD___M 0xF0000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_RXLO_VREF_2G_CH1_OVD___S 28 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_RXLO_VREF_5G_CH1_OVD___M 0x0F000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_RXLO_VREF_5G_CH1_OVD___S 24 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_TXLO_VREF_2G_CH0_OVD___M 0x00F00000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_TXLO_VREF_2G_CH0_OVD___S 20 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_TXLO_VREF_5G_CH0_OVD___M 0x000F0000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_TXLO_VREF_5G_CH0_OVD___S 16 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_TXLO_VREF_2G_CH1_OVD___M 0x0000F000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_TXLO_VREF_2G_CH1_OVD___S 12 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_TXLO_VREF_5G_CH1_OVD___M 0x00000F00 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_TXLO_VREF_5G_CH1_OVD___S 8 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_DAC_VREF_2G_CH0_OVD___M 0x000000F0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_DAC_VREF_2G_CH0_OVD___S 4 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_DAC_VREF_5G_CH0_OVD___M 0x0000000F +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2__LDO_WL_DAC_VREF_5G_CH0_OVD___S 0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_2___S 0 + +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3 (0x005D44B4) +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3___POR 0xBB000444 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_DAC_VREF_2G_CH1_OVD___POR 0xB +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_DAC_VREF_5G_CH1_OVD___POR 0xB +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_ADC_VREF_2G_CH0_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_ADC_VREF_5G_CH0_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_ADC_VREF_2G_CH1_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_ADC_VREF_5G_CH1_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_BT_TXLO_VREF_OVD___POR 0x4 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_SYNTH0_LOGEN_VREF_OVD___POR 0x4 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_SYNTH1_LOGEN_VREF_OVD___POR 0x4 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_DAC_VREF_2G_CH1_OVD___M 0xF0000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_DAC_VREF_2G_CH1_OVD___S 28 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_DAC_VREF_5G_CH1_OVD___M 0x0F000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_DAC_VREF_5G_CH1_OVD___S 24 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_ADC_VREF_2G_CH0_OVD___M 0x00E00000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_ADC_VREF_2G_CH0_OVD___S 21 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_ADC_VREF_5G_CH0_OVD___M 0x001C0000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_ADC_VREF_5G_CH0_OVD___S 18 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_ADC_VREF_2G_CH1_OVD___M 0x00038000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_ADC_VREF_2G_CH1_OVD___S 15 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_ADC_VREF_5G_CH1_OVD___M 0x00007000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_ADC_VREF_5G_CH1_OVD___S 12 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_BT_TXLO_VREF_OVD___M 0x00000F00 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_BT_TXLO_VREF_OVD___S 8 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_SYNTH0_LOGEN_VREF_OVD___M 0x000000F0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_SYNTH0_LOGEN_VREF_OVD___S 4 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_SYNTH1_LOGEN_VREF_OVD___M 0x0000000F +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3__LDO_WL_SYNTH1_LOGEN_VREF_OVD___S 0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_3___S 0 + +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4 (0x005D44B8) +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4___POR 0x54333000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4__LDO_WL_SYNTH0_VREF_OVD___POR 0x5 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4__LDO_WL_SYNTH1_VREF_OVD___POR 0x4 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4__LDO_WL_SYNTH2_VREF_OVD___POR 0x3 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4__LDO_BT_SYNTH_REFGEN_VREF_OVD___POR 0x3 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4__LDO_BT_SYNTH_LOLDO_VREF06_OVD___POR 0x3 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4__LDO_WL_SYNTH0_VREF_OVD___M 0xF0000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4__LDO_WL_SYNTH0_VREF_OVD___S 28 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4__LDO_WL_SYNTH1_VREF_OVD___M 0x0F000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4__LDO_WL_SYNTH1_VREF_OVD___S 24 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4__LDO_WL_SYNTH2_VREF_OVD___M 0x00F00000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4__LDO_WL_SYNTH2_VREF_OVD___S 20 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4__LDO_BT_SYNTH_REFGEN_VREF_OVD___M 0x00070000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4__LDO_BT_SYNTH_REFGEN_VREF_OVD___S 16 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4__LDO_BT_SYNTH_LOLDO_VREF06_OVD___M 0x00007000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4__LDO_BT_SYNTH_LOLDO_VREF06_OVD___S 12 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4___M 0xFFF77000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_LDO_4___S 12 + +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0 (0x005D44BC) +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0___POR 0x695A2C59 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__SETTIME_BGT_EN_OVD___POR 0x1 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__SETTIME_TOP_STARTUP_OVD___POR 0x2 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__SETTIME_TOP_FC_OVD___POR 0x2 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__TOP_STARTUP_WIDTH_OVD___POR 0x1 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__TOP_FC_WIDTH_OVD___POR 0x1 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__TOP_BIAS_SETTLE_TIME_OVD___POR 0x3 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__XO_SETTLE_TIME_OVD___POR 0x45 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__DBLR_SETTLE_TIME_OVD___POR 0x45 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__TCXO_SETTLE_TIME_OVD___POR 0x9 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__SETTIME_BGT_EN_OVD___M 0xC0000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__SETTIME_BGT_EN_OVD___S 30 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__SETTIME_TOP_STARTUP_OVD___M 0x30000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__SETTIME_TOP_STARTUP_OVD___S 28 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__SETTIME_TOP_FC_OVD___M 0x0C000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__SETTIME_TOP_FC_OVD___S 26 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__TOP_STARTUP_WIDTH_OVD___M 0x03000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__TOP_STARTUP_WIDTH_OVD___S 24 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__TOP_FC_WIDTH_OVD___M 0x00C00000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__TOP_FC_WIDTH_OVD___S 22 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__TOP_BIAS_SETTLE_TIME_OVD___M 0x00380000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__TOP_BIAS_SETTLE_TIME_OVD___S 19 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__XO_SETTLE_TIME_OVD___M 0x0007F800 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__XO_SETTLE_TIME_OVD___S 11 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__DBLR_SETTLE_TIME_OVD___M 0x000007F0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__DBLR_SETTLE_TIME_OVD___S 4 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__TCXO_SETTLE_TIME_OVD___M 0x0000000F +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0__TCXO_SETTLE_TIME_OVD___S 0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_0___S 0 + +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1 (0x005D44C0) +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1___POR 0x71111133 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__XO_LDO_SETTLE_TIME_OVD___POR 0x7 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__WL_LDO_SETTLE_TIME_OVD___POR 0x1 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__BT_LDO_SETTLE_TIME_OVD___POR 0x1 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__CM_LDO_SETTLE_TIME_OVD___POR 0x1 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__BBPLL_LDO_SETTLE_TIME_OVD___POR 0x1 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__BTFMPLL_LDO_SETTLE_TIME_OVD___POR 0x1 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__BBPLL_SETTLE_TIME_OVD___POR 0x3 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__BTFMPLL_SETTLE_TIME_OVD___POR 0x3 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__XO_LDO_SETTLE_TIME_OVD___M 0xF0000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__XO_LDO_SETTLE_TIME_OVD___S 28 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__WL_LDO_SETTLE_TIME_OVD___M 0x0F000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__WL_LDO_SETTLE_TIME_OVD___S 24 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__BT_LDO_SETTLE_TIME_OVD___M 0x00F00000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__BT_LDO_SETTLE_TIME_OVD___S 20 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__CM_LDO_SETTLE_TIME_OVD___M 0x000F0000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__CM_LDO_SETTLE_TIME_OVD___S 16 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__BBPLL_LDO_SETTLE_TIME_OVD___M 0x0000F000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__BBPLL_LDO_SETTLE_TIME_OVD___S 12 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__BTFMPLL_LDO_SETTLE_TIME_OVD___M 0x00000F00 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__BTFMPLL_LDO_SETTLE_TIME_OVD___S 8 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__BBPLL_SETTLE_TIME_OVD___M 0x000000F0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__BBPLL_SETTLE_TIME_OVD___S 4 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__BTFMPLL_SETTLE_TIME_OVD___M 0x0000000F +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1__BTFMPLL_SETTLE_TIME_OVD___S 0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_1___S 0 + +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_2 (0x005D44C4) +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_2___POR 0xC0000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_2__SETTIME_XO_FC_OVD___POR 0x3 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_2__SETTIME_XO_FC_OVD___M 0xC0000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_2__SETTIME_XO_FC_OVD___S 30 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_2___M 0xC0000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_BOOTUP_2___S 30 + +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DPLL_JITTER (0x005D44C8) +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DPLL_JITTER___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DPLL_JITTER___POR 0x22000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DPLL_JITTER__JITTER_WAR_DISABLE_WL_BBPLL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DPLL_JITTER__JITTER_WAR_TMR_SEL_WL_BBPLL_OVD___POR 0x2 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DPLL_JITTER__JITTER_WAR_DISABLE_BTFMPLL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DPLL_JITTER__JITTER_WAR_TMR_SEL_BTFMPLL_OVD___POR 0x2 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DPLL_JITTER__JITTER_WAR_DISABLE_WL_BBPLL_OVD___M 0x80000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DPLL_JITTER__JITTER_WAR_DISABLE_WL_BBPLL_OVD___S 31 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DPLL_JITTER__JITTER_WAR_TMR_SEL_WL_BBPLL_OVD___M 0x30000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DPLL_JITTER__JITTER_WAR_TMR_SEL_WL_BBPLL_OVD___S 28 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DPLL_JITTER__JITTER_WAR_DISABLE_BTFMPLL_OVD___M 0x08000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DPLL_JITTER__JITTER_WAR_DISABLE_BTFMPLL_OVD___S 27 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DPLL_JITTER__JITTER_WAR_TMR_SEL_BTFMPLL_OVD___M 0x03000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DPLL_JITTER__JITTER_WAR_TMR_SEL_BTFMPLL_OVD___S 24 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DPLL_JITTER___M 0xBB000000 +#define PHYA_IRON2G_RFA_RFA_OTP_OTP_DPLL_JITTER___S 24 + +#define PHYA_IRON2G_RFA_RFA_OTP_RO_BOOTSTRAP (0x005D44CC) +#define PHYA_IRON2G_RFA_RFA_OTP_RO_BOOTSTRAP___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_RFA_OTP_RO_BOOTSTRAP___POR 0x00000000 +#define PHYA_IRON2G_RFA_RFA_OTP_RO_BOOTSTRAP__RO_BOOTSTRAP_CLK_CFG___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_RO_BOOTSTRAP__RO_BOOTSTRAP_CLK_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_RO_BOOTSTRAP__RO_BOOTSTRAP_TCXO_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_RFA_OTP_RO_BOOTSTRAP__RO_BOOTSTRAP_CLK_CFG___M 0x80000000 +#define PHYA_IRON2G_RFA_RFA_OTP_RO_BOOTSTRAP__RO_BOOTSTRAP_CLK_CFG___S 31 +#define PHYA_IRON2G_RFA_RFA_OTP_RO_BOOTSTRAP__RO_BOOTSTRAP_CLK_SEL___M 0x70000000 +#define PHYA_IRON2G_RFA_RFA_OTP_RO_BOOTSTRAP__RO_BOOTSTRAP_CLK_SEL___S 28 +#define PHYA_IRON2G_RFA_RFA_OTP_RO_BOOTSTRAP__RO_BOOTSTRAP_TCXO_MODE___M 0x08000000 +#define PHYA_IRON2G_RFA_RFA_OTP_RO_BOOTSTRAP__RO_BOOTSTRAP_TCXO_MODE___S 27 +#define PHYA_IRON2G_RFA_RFA_OTP_RO_BOOTSTRAP___M 0xF8000000 +#define PHYA_IRON2G_RFA_RFA_OTP_RO_BOOTSTRAP___S 27 + +#define PHYA_IRON2G_RFA_CLKGEN_TESTREG (0x005D4800) +#define PHYA_IRON2G_RFA_CLKGEN_TESTREG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_CLKGEN_TESTREG___POR 0x0C1036E0 +#define PHYA_IRON2G_RFA_CLKGEN_TESTREG__TESTREG___POR 0x0C1036E0 +#define PHYA_IRON2G_RFA_CLKGEN_TESTREG__TESTREG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_CLKGEN_TESTREG__TESTREG___S 0 +#define PHYA_IRON2G_RFA_CLKGEN_TESTREG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_CLKGEN_TESTREG___S 0 + +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0 (0x005D4804) +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0___POR 0x080BDD07 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VC_CHK_CNT___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__WAIT_DLLSM___POR 0x8 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_CHANGE_CAP_FIRST___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__MONITOR_DLL___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCL_SRCH___POR 0x5 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCH_SRCH___POR 0x7 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCL_MON___POR 0x3 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCH_MON___POR 0x5 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCOCAP_DEFAULT___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCOCUR_DEFAULT___POR 0x07 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VC_CHK_CNT___M 0xF0000000 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VC_CHK_CNT___S 28 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__WAIT_DLLSM___M 0x0F000000 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__WAIT_DLLSM___S 24 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_CHANGE_CAP_FIRST___M 0x00800000 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_CHANGE_CAP_FIRST___S 23 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__MONITOR_DLL___M 0x00300000 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__MONITOR_DLL___S 20 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCL_SRCH___M 0x000E0000 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCL_SRCH___S 17 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCH_SRCH___M 0x0001C000 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCH_SRCH___S 14 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCL_MON___M 0x00003800 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCL_MON___S 11 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCH_MON___M 0x00000700 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCH_MON___S 8 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCOCAP_DEFAULT___M 0x000000E0 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCOCAP_DEFAULT___S 5 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCOCUR_DEFAULT___M 0x0000001F +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0__DLL_VCOCUR_DEFAULT___S 0 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0___M 0xFFBFFFFF +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_0___S 0 + +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1 (0x005D4808) +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1___POR 0xF2000010 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_CP___POR 0xF +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_CPCAL___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_ICPBIAS___POR 0x2 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_PDCAL___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_CLKIN_EDGESEL___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_REG_TST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_IS_LOCKED_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_VCOCAP_OV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_VCOCAP_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_VCOCUR_OV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_VCOCUR_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_NDIVM1_OV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_NDIVM1_OVD___POR 0x1 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_ATBH_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_CP___M 0xF0000000 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_CP___S 28 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_CPCAL___M 0x0C000000 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_CPCAL___S 26 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_ICPBIAS___M 0x03000000 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_ICPBIAS___S 24 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_PDCAL___M 0x00800000 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_PDCAL___S 23 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_CLKIN_EDGESEL___M 0x00400000 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_CLKIN_EDGESEL___S 22 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_REG_TST_EN___M 0x00200000 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_REG_TST_EN___S 21 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_IS_LOCKED_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_IS_LOCKED_OVS___S 18 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_VCOCAP_OV___M 0x00020000 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_VCOCAP_OV___S 17 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_VCOCAP_OVD___M 0x0001C000 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_VCOCAP_OVD___S 14 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_VCOCUR_OV___M 0x00002000 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_VCOCUR_OV___S 13 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_VCOCUR_OVD___M 0x00001F00 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_VCOCUR_OVD___S 8 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_NDIVM1_OV___M 0x00000080 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_NDIVM1_OV___S 7 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_NDIVM1_OVD___M 0x00000070 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__DLL_NDIVM1_OVD___S 4 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_ATBH_SEL___M 0x0000000F +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1__D_DLL_ATBH_SEL___S 0 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1___M 0xFFEFFFFF +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_1___S 0 + +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2 (0x005D480C) +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2___POR 0x30000001 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__D_DLL_RFGPO_EN___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__D_DLL_RFGPO_DIFF_EN___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__D_DLL_RFGPO_DRV___POR 0x3 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__RESTORE_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__MDLL_MULT_OV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__MDLL_MULT_OVD___POR 0x1 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__D_DLL_RFGPO_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__D_DLL_RFGPO_EN___S 31 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__D_DLL_RFGPO_DIFF_EN___M 0x40000000 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__D_DLL_RFGPO_DIFF_EN___S 30 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__D_DLL_RFGPO_DRV___M 0x30000000 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__D_DLL_RFGPO_DRV___S 28 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__RESTORE_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__RESTORE_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__MDLL_MULT_OV___M 0x00000004 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__MDLL_MULT_OV___S 2 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__MDLL_MULT_OVD___M 0x00000003 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2__MDLL_MULT_OVD___S 0 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2___M 0xFC000007 +#define PHYA_IRON2G_RFA_CLKGEN_SYN_DLL_2___S 0 + +#define PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL (0x005D4810) +#define PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL___POR 0x00000000 +#define PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_CAPCUR_EXHAUSTED___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_IS_LOCKED___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_VC2HI___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_VC2LO___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_SM_STATE___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_VCOCAP___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_VCOCUR___POR 0x00 +#define PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_CAPCUR_EXHAUSTED___M 0x00002000 +#define PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_CAPCUR_EXHAUSTED___S 13 +#define PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_IS_LOCKED___M 0x00001000 +#define PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_IS_LOCKED___S 12 +#define PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_VC2HI___M 0x00000800 +#define PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_VC2HI___S 11 +#define PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_VC2LO___M 0x00000400 +#define PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_VC2LO___S 10 +#define PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_SM_STATE___M 0x00000300 +#define PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_SM_STATE___S 8 +#define PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_VCOCAP___M 0x000000E0 +#define PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_VCOCAP___S 5 +#define PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_VCOCUR___M 0x0000001F +#define PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL__RO_DLL_VCOCUR___S 0 +#define PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL___M 0x00003FFF +#define PHYA_IRON2G_RFA_CLKGEN_RO_SYN_DLL___S 0 + +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO0 (0x005D4814) +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO0___POR 0x00000200 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__LDO_REFGEN_XO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__LDO_REFGEN_XO_BIAS_FASTCH_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__D_LDO_REFGEN_XO_ATBSEL___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__LDO_XO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__LDO_XO_BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__D_LDO_XO_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__D_LDO_XO_LEAKER_ON___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__D_LDO_XO_OTA_CUR___POR 0x4 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__D_LDO_XO_ATBSEL___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__LDO_REFGEN_XO_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__LDO_REFGEN_XO_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__LDO_REFGEN_XO_BIAS_FASTCH_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__LDO_REFGEN_XO_BIAS_FASTCH_OVS___S 28 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__D_LDO_REFGEN_XO_ATBSEL___M 0x00400000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__D_LDO_REFGEN_XO_ATBSEL___S 22 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__LDO_XO_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__LDO_XO_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__LDO_XO_BIAS_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__LDO_XO_BIAS_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__D_LDO_XO_BYPASS___M 0x00000800 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__D_LDO_XO_BYPASS___S 11 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__D_LDO_XO_LEAKER_ON___M 0x00000400 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__D_LDO_XO_LEAKER_ON___S 10 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__D_LDO_XO_OTA_CUR___M 0x00000380 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__D_LDO_XO_OTA_CUR___S 7 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__D_LDO_XO_ATBSEL___M 0x00000040 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO0__D_LDO_XO_ATBSEL___S 6 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO0___M 0xF040FFC0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO0___S 6 + +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1 (0x005D4818) +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1___POR 0x02000128 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__LDO_TOP_CLKMUX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__LDO_TOP_CLKMUX_BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_TOP_CLKMUX_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_TOP_CLKMUX_LEAKER_ON___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_TOP_CLKMUX_OTA_CUR___POR 0x4 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_TOP_CLKMUX_ATBSEL___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__LDO_MDLL_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__LDO_MDLL_BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_MDLL_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_MDLL_LEAKER_ON___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_MDLL_OTA_CUR___POR 0x2 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_MDLL_ATBSEL___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_MDLL_VREF___POR 0xA +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__LDO_TOP_CLKMUX_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__LDO_TOP_CLKMUX_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__LDO_TOP_CLKMUX_BIAS_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__LDO_TOP_CLKMUX_BIAS_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_TOP_CLKMUX_BYPASS___M 0x08000000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_TOP_CLKMUX_BYPASS___S 27 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_TOP_CLKMUX_LEAKER_ON___M 0x04000000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_TOP_CLKMUX_LEAKER_ON___S 26 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_TOP_CLKMUX_OTA_CUR___M 0x03800000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_TOP_CLKMUX_OTA_CUR___S 23 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_TOP_CLKMUX_ATBSEL___M 0x00400000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_TOP_CLKMUX_ATBSEL___S 22 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__LDO_MDLL_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__LDO_MDLL_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__LDO_MDLL_BIAS_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__LDO_MDLL_BIAS_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_MDLL_BYPASS___M 0x00000800 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_MDLL_BYPASS___S 11 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_MDLL_LEAKER_ON___M 0x00000400 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_MDLL_LEAKER_ON___S 10 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_MDLL_OTA_CUR___M 0x00000380 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_MDLL_OTA_CUR___S 7 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_MDLL_ATBSEL___M 0x00000040 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_MDLL_ATBSEL___S 6 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_MDLL_VREF___M 0x0000003C +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1__D_LDO_MDLL_VREF___S 2 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1___M 0xFFC0FFFC +#define PHYA_IRON2G_RFA_CLKGEN_LDO_XO1___S 2 + +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL (0x005D481C) +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL___POR 0x0F840F84 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__LDO_REFGEN_BTPLL_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__LDO_REFGEN_BTPLL_BIAS_FASTCH_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_SEL_VREF___POR 0x7 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_BIAS_BWRSEL___POR 0x3 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_LEAKER_ON___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_OTA_CUR___POR 0x1 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_ATBSEL___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__LDO_REFGEN_WLPLL_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__LDO_REFGEN_WLPLL_BIAS_FASTCH_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_SEL_VREF___POR 0x7 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_BIAS_BWRSEL___POR 0x3 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_LEAKER_ON___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_OTA_CUR___POR 0x1 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_ATBSEL___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__LDO_REFGEN_BTPLL_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__LDO_REFGEN_BTPLL_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__LDO_REFGEN_BTPLL_BIAS_FASTCH_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__LDO_REFGEN_BTPLL_BIAS_FASTCH_OVS___S 28 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_SEL_VREF___M 0x0E000000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_SEL_VREF___S 25 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_BIAS_BWRSEL___M 0x01800000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_BIAS_BWRSEL___S 23 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_BYPASS___M 0x00400000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_BYPASS___S 22 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_LEAKER_ON___M 0x00200000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_LEAKER_ON___S 21 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_OTA_CUR___M 0x001C0000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_OTA_CUR___S 18 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_ATBSEL___M 0x00020000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_BTPLL_ATBSEL___S 17 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__LDO_REFGEN_WLPLL_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__LDO_REFGEN_WLPLL_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__LDO_REFGEN_WLPLL_BIAS_FASTCH_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__LDO_REFGEN_WLPLL_BIAS_FASTCH_OVS___S 12 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_SEL_VREF___M 0x00000E00 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_SEL_VREF___S 9 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_BIAS_BWRSEL___M 0x00000180 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_BIAS_BWRSEL___S 7 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_BYPASS___M 0x00000040 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_BYPASS___S 6 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_LEAKER_ON___M 0x00000020 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_LEAKER_ON___S 5 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_OTA_CUR___M 0x0000001C +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_OTA_CUR___S 2 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_ATBSEL___M 0x00000002 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL__D_LDO_REFGEN_WLPLL_ATBSEL___S 1 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL___M 0xFFFEFFFE +#define PHYA_IRON2G_RFA_CLKGEN_LDO_REFGEN_DPLL___S 1 + +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0 (0x005D4820) +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0___POR 0x01800080 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__LDO0_BT_DPLL_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__LDO0_BT_DPLL_BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO0_BT_DPLL_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO0_BT_DPLL_LEAKER_ON___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO0_BT_DPLL_OTA_CUR___POR 0x3 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO0_BT_DPLL_ATBSEL___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__LDO1_BT_DPLL_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__LDO1_BT_DPLL_BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO1_BT_DPLL_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO1_BT_DPLL_LEAKER_ON___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO1_BT_DPLL_OTA_CUR___POR 0x1 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO1_BT_DPLL_ATBSEL___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__LDO0_BT_DPLL_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__LDO0_BT_DPLL_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__LDO0_BT_DPLL_BIAS_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__LDO0_BT_DPLL_BIAS_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO0_BT_DPLL_BYPASS___M 0x08000000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO0_BT_DPLL_BYPASS___S 27 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO0_BT_DPLL_LEAKER_ON___M 0x04000000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO0_BT_DPLL_LEAKER_ON___S 26 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO0_BT_DPLL_OTA_CUR___M 0x03800000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO0_BT_DPLL_OTA_CUR___S 23 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO0_BT_DPLL_ATBSEL___M 0x00400000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO0_BT_DPLL_ATBSEL___S 22 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__LDO1_BT_DPLL_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__LDO1_BT_DPLL_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__LDO1_BT_DPLL_BIAS_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__LDO1_BT_DPLL_BIAS_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO1_BT_DPLL_BYPASS___M 0x00000800 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO1_BT_DPLL_BYPASS___S 11 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO1_BT_DPLL_LEAKER_ON___M 0x00000400 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO1_BT_DPLL_LEAKER_ON___S 10 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO1_BT_DPLL_OTA_CUR___M 0x00000380 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO1_BT_DPLL_OTA_CUR___S 7 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO1_BT_DPLL_ATBSEL___M 0x00000040 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0__D_LDO1_BT_DPLL_ATBSEL___S 6 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0___M 0xFFC0FFC0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL0___S 6 + +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1 (0x005D4824) +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1___POR 0x00800180 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__LDO2_BT_DPLL_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__LDO2_BT_DPLL_BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO2_BT_DPLL_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO2_BT_DPLL_LEAKER_ON___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO2_BT_DPLL_OTA_CUR___POR 0x1 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO2_BT_DPLL_ATBSEL___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__LDO0_WL_DPLL_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__LDO0_WL_DPLL_BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO0_WL_DPLL_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO0_WL_DPLL_LEAKER_ON___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO0_WL_DPLL_OTA_CUR___POR 0x3 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO0_WL_DPLL_ATBSEL___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__LDO2_BT_DPLL_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__LDO2_BT_DPLL_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__LDO2_BT_DPLL_BIAS_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__LDO2_BT_DPLL_BIAS_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO2_BT_DPLL_BYPASS___M 0x08000000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO2_BT_DPLL_BYPASS___S 27 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO2_BT_DPLL_LEAKER_ON___M 0x04000000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO2_BT_DPLL_LEAKER_ON___S 26 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO2_BT_DPLL_OTA_CUR___M 0x03800000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO2_BT_DPLL_OTA_CUR___S 23 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO2_BT_DPLL_ATBSEL___M 0x00400000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO2_BT_DPLL_ATBSEL___S 22 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__LDO0_WL_DPLL_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__LDO0_WL_DPLL_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__LDO0_WL_DPLL_BIAS_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__LDO0_WL_DPLL_BIAS_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO0_WL_DPLL_BYPASS___M 0x00000800 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO0_WL_DPLL_BYPASS___S 11 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO0_WL_DPLL_LEAKER_ON___M 0x00000400 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO0_WL_DPLL_LEAKER_ON___S 10 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO0_WL_DPLL_OTA_CUR___M 0x00000380 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO0_WL_DPLL_OTA_CUR___S 7 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO0_WL_DPLL_ATBSEL___M 0x00000040 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1__D_LDO0_WL_DPLL_ATBSEL___S 6 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1___M 0xFFC0FFC0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL1___S 6 + +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2 (0x005D4828) +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2___POR 0x00800080 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__LDO1_WL_DPLL_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__LDO1_WL_DPLL_BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO1_WL_DPLL_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO1_WL_DPLL_LEAKER_ON___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO1_WL_DPLL_OTA_CUR___POR 0x1 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO1_WL_DPLL_ATBSEL___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__LDO2_WL_DPLL_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__LDO2_WL_DPLL_BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO2_WL_DPLL_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO2_WL_DPLL_LEAKER_ON___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO2_WL_DPLL_OTA_CUR___POR 0x1 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO2_WL_DPLL_ATBSEL___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__LDO1_WL_DPLL_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__LDO1_WL_DPLL_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__LDO1_WL_DPLL_BIAS_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__LDO1_WL_DPLL_BIAS_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO1_WL_DPLL_BYPASS___M 0x08000000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO1_WL_DPLL_BYPASS___S 27 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO1_WL_DPLL_LEAKER_ON___M 0x04000000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO1_WL_DPLL_LEAKER_ON___S 26 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO1_WL_DPLL_OTA_CUR___M 0x03800000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO1_WL_DPLL_OTA_CUR___S 23 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO1_WL_DPLL_ATBSEL___M 0x00400000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO1_WL_DPLL_ATBSEL___S 22 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__LDO2_WL_DPLL_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__LDO2_WL_DPLL_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__LDO2_WL_DPLL_BIAS_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__LDO2_WL_DPLL_BIAS_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO2_WL_DPLL_BYPASS___M 0x00000800 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO2_WL_DPLL_BYPASS___S 11 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO2_WL_DPLL_LEAKER_ON___M 0x00000400 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO2_WL_DPLL_LEAKER_ON___S 10 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO2_WL_DPLL_OTA_CUR___M 0x00000380 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO2_WL_DPLL_OTA_CUR___S 7 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO2_WL_DPLL_ATBSEL___M 0x00000040 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2__D_LDO2_WL_DPLL_ATBSEL___S 6 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2___M 0xFFC0FFC0 +#define PHYA_IRON2G_RFA_CLKGEN_LDO_DPLL2___S 6 + +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN (0x005D482C) +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN___POR 0x00000000 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_TCXO_EN___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_XO_EN___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_CLKGEN_REFCLK_CHIPOUT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_CLKGEN_REFCLK_EN___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_PLL_EN_BTFMPLL___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_PLL_EN_WL_BBPLL___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_SYN_EN_BT_SYNTH___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_SYN_EN_WL_SYNTH2___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_SYN_EN_WL_SYNTH1___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_SYN_EN_WL_SYNTH0___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_CLK_SEL_VALID___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_CLK_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_TCXO_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_TCXO_EN___S 31 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_XO_EN___M 0x40000000 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_XO_EN___S 30 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_CLKGEN_REFCLK_CHIPOUT_EN___M 0x00000800 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_CLKGEN_REFCLK_CHIPOUT_EN___S 11 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_CLKGEN_REFCLK_EN___M 0x00000400 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_CLKGEN_REFCLK_EN___S 10 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_PLL_EN_BTFMPLL___M 0x00000200 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_PLL_EN_BTFMPLL___S 9 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_PLL_EN_WL_BBPLL___M 0x00000100 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_PLL_EN_WL_BBPLL___S 8 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_SYN_EN_BT_SYNTH___M 0x00000080 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_SYN_EN_BT_SYNTH___S 7 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_SYN_EN_WL_SYNTH2___M 0x00000040 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_SYN_EN_WL_SYNTH2___S 6 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_SYN_EN_WL_SYNTH1___M 0x00000020 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_SYN_EN_WL_SYNTH1___S 5 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_SYN_EN_WL_SYNTH0___M 0x00000010 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_SYN_EN_WL_SYNTH0___S 4 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_CLK_SEL_VALID___M 0x00000008 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_CLK_SEL_VALID___S 3 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_CLK_SEL___M 0x00000007 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN__RO_CLK_SEL___S 0 +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN___M 0xC0000FFF +#define PHYA_IRON2G_RFA_CLKGEN_RO_CLKGEN___S 0 + +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0 (0x005D4830) +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_MC_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_MC_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_MC_CH2_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_MC_CH3_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_RXFE_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_RXFE_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_RXFE_CH2_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_RXFE_CH3_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_TPC_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_TPC_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_TPC_CH2_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_TPC_CH3_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_MC_CH0_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_MC_CH0_OVS___S 30 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_MC_CH1_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_MC_CH1_OVS___S 28 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_MC_CH2_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_MC_CH2_OVS___S 26 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_MC_CH3_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_MC_CH3_OVS___S 24 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_RXFE_CH0_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_RXFE_CH0_OVS___S 22 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_RXFE_CH1_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_RXFE_CH1_OVS___S 20 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_RXFE_CH2_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_RXFE_CH2_OVS___S 18 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_RXFE_CH3_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_RXFE_CH3_OVS___S 16 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_TPC_CH0_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_TPC_CH0_OVS___S 14 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_TPC_CH1_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_TPC_CH1_OVS___S 12 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_TPC_CH2_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_TPC_CH2_OVS___S 10 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_TPC_CH3_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0__DCLK_EN_WL_TPC_CH3_OVS___S 8 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0___M 0xFFFFFF00 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_0___S 8 + +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1 (0x005D4834) +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__DCLK_EN_CLKGEN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_DIV2_0_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_DIV2_1_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_DBLR_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__DLL_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_D4_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_D2_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_1X_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_2X_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_4X_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_DCC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_BUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_BUF_START_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_CORE_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XTALO_HIGH_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__DCLK_EN_CLKGEN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__DCLK_EN_CLKGEN_OVS___S 30 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_DIV2_0_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_DIV2_0_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_DIV2_1_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_DIV2_1_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_DBLR_EN_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_DBLR_EN_OVS___S 24 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__DLL_EN_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__DLL_EN_OVS___S 22 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_D4_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_D4_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_D2_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_D2_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_1X_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_1X_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_2X_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_2X_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_4X_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_4X_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_DCC_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_DCC_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_EN_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_EN_OVS___S 8 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_BUF_EN_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_BUF_EN_OVS___S 6 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_BUF_START_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_BUF_START_OVS___S 4 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_CORE_EN_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XO_CORE_EN_OVS___S 2 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XTALO_HIGH_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1__XTALO_HIGH_OVS___S 0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_1___S 0 + +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2 (0x005D4838) +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__CLK_REQ_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__CLK_OUT_REQ_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__CLK_SEL_VALID_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__CLK_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__CLK_SEL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__D_XO_BIAS_SMALL_R___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__D_XO_SMALL_R___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__D_XO_REG_TST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__D_REG_DUMMY_EN___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__DLL_DIFF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__D_XO_SPARE_2___POR 0x00 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__ZZZ_SPARE___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__CLK_REQ_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__CLK_REQ_OVS___S 30 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__CLK_OUT_REQ_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__CLK_OUT_REQ_OVS___S 28 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__CLK_SEL_VALID_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__CLK_SEL_VALID_OVS___S 26 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__CLK_SEL_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__CLK_SEL_OV___S 23 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__CLK_SEL_OVD___M 0x00700000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__CLK_SEL_OVD___S 20 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__D_XO_BIAS_SMALL_R___M 0x00080000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__D_XO_BIAS_SMALL_R___S 19 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__D_XO_SMALL_R___M 0x00040000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__D_XO_SMALL_R___S 18 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__D_XO_REG_TST_EN___M 0x00020000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__D_XO_REG_TST_EN___S 17 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__D_REG_DUMMY_EN___M 0x00010000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__D_REG_DUMMY_EN___S 16 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__DLL_DIFF_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__DLL_DIFF_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__D_XO_SPARE_2___M 0x000000FE +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__D_XO_SPARE_2___S 1 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__ZZZ_SPARE___M 0x00000001 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2__ZZZ_SPARE___S 0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2___M 0xFCFFC0FF +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_2___S 0 + +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_3 (0x005D483C) +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_3__D_XO_SPARE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_3__D_XO_SPARE_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_3__D_XO_SPARE_0___S 0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_3___S 0 + +#define PHYA_IRON2G_RFA_CLKGEN_XO_SPARE1 (0x005D4840) +#define PHYA_IRON2G_RFA_CLKGEN_XO_SPARE1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_CLKGEN_XO_SPARE1___POR 0x00000000 +#define PHYA_IRON2G_RFA_CLKGEN_XO_SPARE1__D_XO_SPARE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_CLKGEN_XO_SPARE1__D_XO_SPARE_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_CLKGEN_XO_SPARE1__D_XO_SPARE_1___S 0 +#define PHYA_IRON2G_RFA_CLKGEN_XO_SPARE1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_CLKGEN_XO_SPARE1___S 0 + +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_SPARE0 (0x005D4844) +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_SPARE0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_SPARE0___POR 0x00000000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_SPARE0__D_CLKGEN_SPARE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_SPARE0__D_CLKGEN_SPARE_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_SPARE0__D_CLKGEN_SPARE_0___S 0 +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_SPARE0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_CLKGEN_CLKGEN_SPARE0___S 0 + +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL (0x005D4848) +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL___POR 0x000018A0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__REFCLK_FREQ_WL_SYNTH0_OV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__REFCLK_FREQ_WL_SYNTH0_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH0_OV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH0_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_CLK_MUX_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_CLK_MUX_SEL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_CLK_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__D_WL_SYNTH0_DIFF_EN___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__D_WL_SYNTH0_CLK_DRV___POR 0x3 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_DCLK_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_REFCLK_FREQ___POR 0x1 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_DTIM_REFCLK_FREQ___POR 0x1 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__REFCLK_FREQ_WL_SYNTH0_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__REFCLK_FREQ_WL_SYNTH0_OV___S 31 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__REFCLK_FREQ_WL_SYNTH0_OVD___M 0x3F000000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__REFCLK_FREQ_WL_SYNTH0_OVD___S 24 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH0_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH0_OV___S 23 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH0_OVD___M 0x00700000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH0_OVD___S 20 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_CLK_MUX_SEL_OV___M 0x00080000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_CLK_MUX_SEL_OV___S 19 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_CLK_MUX_SEL_OVD___M 0x00070000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_CLK_MUX_SEL_OVD___S 16 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_CLK_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_CLK_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__D_WL_SYNTH0_DIFF_EN___M 0x00002000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__D_WL_SYNTH0_DIFF_EN___S 13 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__D_WL_SYNTH0_CLK_DRV___M 0x00001800 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__D_WL_SYNTH0_CLK_DRV___S 11 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_DCLK_EN_OVS___M 0x00000600 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_DCLK_EN_OVS___S 9 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_REFCLK_FREQ___M 0x00000180 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_REFCLK_FREQ___S 7 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_DTIM_REFCLK_FREQ___M 0x00000060 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL__WL_SYNTH0_DTIM_REFCLK_FREQ___S 5 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL___M 0xBFFFFFE0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH0_CTRL___S 5 + +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL (0x005D484C) +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL___POR 0x00001800 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__REFCLK_FREQ_WL_SYNTH1_OV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__REFCLK_FREQ_WL_SYNTH1_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH1_OV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH1_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_CLK_MUX_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_CLK_MUX_SEL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_CLK_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__D_WL_SYNTH1_DIFF_EN___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__D_WL_SYNTH1_CLK_DRV___POR 0x3 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_DCLK_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_REFCLK_FREQ___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__REFCLK_FREQ_WL_SYNTH1_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__REFCLK_FREQ_WL_SYNTH1_OV___S 31 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__REFCLK_FREQ_WL_SYNTH1_OVD___M 0x3F000000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__REFCLK_FREQ_WL_SYNTH1_OVD___S 24 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH1_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH1_OV___S 23 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH1_OVD___M 0x00700000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH1_OVD___S 20 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_CLK_MUX_SEL_OV___M 0x00080000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_CLK_MUX_SEL_OV___S 19 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_CLK_MUX_SEL_OVD___M 0x00070000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_CLK_MUX_SEL_OVD___S 16 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_CLK_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_CLK_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__D_WL_SYNTH1_DIFF_EN___M 0x00002000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__D_WL_SYNTH1_DIFF_EN___S 13 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__D_WL_SYNTH1_CLK_DRV___M 0x00001800 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__D_WL_SYNTH1_CLK_DRV___S 11 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_DCLK_EN_OVS___M 0x00000600 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_DCLK_EN_OVS___S 9 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_REFCLK_FREQ___M 0x00000180 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL__WL_SYNTH1_REFCLK_FREQ___S 7 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL___M 0xBFFFFF80 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH1_CTRL___S 7 + +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL (0x005D4850) +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL___POR 0x00001880 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__REFCLK_FREQ_WL_SYNTH2_OV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__REFCLK_FREQ_WL_SYNTH2_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH2_OV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH2_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_CLK_MUX_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_CLK_MUX_SEL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_CLK_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__D_WL_SYNTH2_DIFF_EN___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__D_WL_SYNTH2_CLK_DRV___POR 0x3 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_DCLK_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_DTIM_REFCLK_FREQ___POR 0x1 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__REFCLK_FREQ_WL_SYNTH2_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__REFCLK_FREQ_WL_SYNTH2_OV___S 31 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__REFCLK_FREQ_WL_SYNTH2_OVD___M 0x3F000000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__REFCLK_FREQ_WL_SYNTH2_OVD___S 24 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH2_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH2_OV___S 23 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH2_OVD___M 0x00700000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__REFCLK_DCLK_RATIO_WL_SYNTH2_OVD___S 20 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_CLK_MUX_SEL_OV___M 0x00080000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_CLK_MUX_SEL_OV___S 19 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_CLK_MUX_SEL_OVD___M 0x00070000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_CLK_MUX_SEL_OVD___S 16 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_CLK_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_CLK_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__D_WL_SYNTH2_DIFF_EN___M 0x00002000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__D_WL_SYNTH2_DIFF_EN___S 13 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__D_WL_SYNTH2_CLK_DRV___M 0x00001800 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__D_WL_SYNTH2_CLK_DRV___S 11 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_DCLK_EN_OVS___M 0x00000600 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_DCLK_EN_OVS___S 9 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_DTIM_REFCLK_FREQ___M 0x00000180 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL__WL_SYNTH2_DTIM_REFCLK_FREQ___S 7 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL___M 0xBFFFFF80 +#define PHYA_IRON2G_RFA_CLKGEN_WL_SYNTH2_CTRL___S 7 + +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL (0x005D4854) +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL___POR 0x00001880 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__REFCLK_FREQ_BT_SYNTH_OV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__REFCLK_FREQ_BT_SYNTH_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__REFCLK_DCLK_RATIO_BT_SYNTH_OV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__REFCLK_DCLK_RATIO_BT_SYNTH_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__BT_SYNTH_CLK_MUX_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__BT_SYNTH_CLK_MUX_SEL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__BT_SYNTH_CLK_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__D_BT_SYNTH_DIFF_EN___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__D_BT_SYNTH_CLK_DRV___POR 0x3 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__BT_SYNTH_DCLK_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__BT_SYNTH_REFCLK_FREQ___POR 0x1 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__REFCLK_FREQ_BT_SYNTH_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__REFCLK_FREQ_BT_SYNTH_OV___S 31 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__REFCLK_FREQ_BT_SYNTH_OVD___M 0x3F000000 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__REFCLK_FREQ_BT_SYNTH_OVD___S 24 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__REFCLK_DCLK_RATIO_BT_SYNTH_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__REFCLK_DCLK_RATIO_BT_SYNTH_OV___S 23 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__REFCLK_DCLK_RATIO_BT_SYNTH_OVD___M 0x00700000 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__REFCLK_DCLK_RATIO_BT_SYNTH_OVD___S 20 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__BT_SYNTH_CLK_MUX_SEL_OV___M 0x00080000 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__BT_SYNTH_CLK_MUX_SEL_OV___S 19 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__BT_SYNTH_CLK_MUX_SEL_OVD___M 0x00070000 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__BT_SYNTH_CLK_MUX_SEL_OVD___S 16 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__BT_SYNTH_CLK_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__BT_SYNTH_CLK_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__D_BT_SYNTH_DIFF_EN___M 0x00002000 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__D_BT_SYNTH_DIFF_EN___S 13 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__D_BT_SYNTH_CLK_DRV___M 0x00001800 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__D_BT_SYNTH_CLK_DRV___S 11 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__BT_SYNTH_DCLK_EN_OVS___M 0x00000600 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__BT_SYNTH_DCLK_EN_OVS___S 9 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__BT_SYNTH_REFCLK_FREQ___M 0x00000180 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL__BT_SYNTH_REFCLK_FREQ___S 7 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL___M 0xBFFFFF80 +#define PHYA_IRON2G_RFA_CLKGEN_BT_SYNTH_CTRL___S 7 + +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0 (0x005D4858) +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0___POR 0x0000001C +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__WL_DLL_CLK_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__CM_DCLK_CLK_MUX_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__CM_DCLK_CLK_MUX_SEL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__CM_DCLK_CLK_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__D_CM_DCLK_DIFF_EN___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__D_CM_DCLK_CLK_DRV___POR 0x3 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__CM_DCLK_FREQ___POR 0x2 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__WL_DLL_CLK_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__WL_DLL_CLK_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__CM_DCLK_CLK_MUX_SEL_OV___M 0x00000800 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__CM_DCLK_CLK_MUX_SEL_OV___S 11 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__CM_DCLK_CLK_MUX_SEL_OVD___M 0x00000700 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__CM_DCLK_CLK_MUX_SEL_OVD___S 8 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__CM_DCLK_CLK_EN_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__CM_DCLK_CLK_EN_OVS___S 6 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__D_CM_DCLK_DIFF_EN___M 0x00000020 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__D_CM_DCLK_DIFF_EN___S 5 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__D_CM_DCLK_CLK_DRV___M 0x00000018 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__D_CM_DCLK_CLK_DRV___S 3 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__CM_DCLK_FREQ___M 0x00000006 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0__CM_DCLK_FREQ___S 1 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0___M 0x00030FFE +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_0___S 1 + +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2 (0x005D485C) +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2___POR 0x01C01800 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_MUX_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_MUX_SEL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__D_CLKGEN_REFCLK_DIFF_EN___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__D_CLKGEN_REFCLK_DRV___POR 0x3 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_FREQ___POR 0x2 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_CHIPOUT_MUX_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_CHIPOUT_MUX_SEL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_CHIPOUT_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__D_CLKGEN_REFCLK_CHIPOUT_DIFF_EN___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__D_CLKGEN_REFCLK_CHIPOUT_DRV___POR 0x3 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_MUX_SEL_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_MUX_SEL_OV___S 31 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_MUX_SEL_OVD___M 0x70000000 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_MUX_SEL_OVD___S 28 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__D_CLKGEN_REFCLK_DIFF_EN___M 0x02000000 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__D_CLKGEN_REFCLK_DIFF_EN___S 25 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__D_CLKGEN_REFCLK_DRV___M 0x01800000 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__D_CLKGEN_REFCLK_DRV___S 23 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_FREQ___M 0x00600000 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_FREQ___S 21 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_BYPASS___M 0x00100000 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_BYPASS___S 20 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_CHIPOUT_MUX_SEL_OV___M 0x00080000 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_CHIPOUT_MUX_SEL_OV___S 19 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_CHIPOUT_MUX_SEL_OVD___M 0x00070000 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_CHIPOUT_MUX_SEL_OVD___S 16 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_CHIPOUT_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__CLKGEN_REFCLK_CHIPOUT_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__D_CLKGEN_REFCLK_CHIPOUT_DIFF_EN___M 0x00002000 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__D_CLKGEN_REFCLK_CHIPOUT_DIFF_EN___S 13 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__D_CLKGEN_REFCLK_CHIPOUT_DRV___M 0x00001800 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2__D_CLKGEN_REFCLK_CHIPOUT_DRV___S 11 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2___M 0xFFFFF800 +#define PHYA_IRON2G_RFA_CLKGEN_TOPCLK_2___S 11 + +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0 (0x005D4860) +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0___POR 0x01C00000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__WL_BBPLL_CLK_MUX_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__WL_BBPLL_CLK_MUX_SEL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__WL_BBPLL_CLK_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__D_WL_BBPLL_DIFF_EN___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__D_WL_BBPLL_CLK_DRV___POR 0x3 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__WL_BBPLL_REFCLK_FREQ___POR 0x2 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__WL_BBPLL_CLK_MUX_SEL_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__WL_BBPLL_CLK_MUX_SEL_OV___S 31 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__WL_BBPLL_CLK_MUX_SEL_OVD___M 0x70000000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__WL_BBPLL_CLK_MUX_SEL_OVD___S 28 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__WL_BBPLL_CLK_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__WL_BBPLL_CLK_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__D_WL_BBPLL_DIFF_EN___M 0x02000000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__D_WL_BBPLL_DIFF_EN___S 25 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__D_WL_BBPLL_CLK_DRV___M 0x01800000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__D_WL_BBPLL_CLK_DRV___S 23 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__WL_BBPLL_REFCLK_FREQ___M 0x00600000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0__WL_BBPLL_REFCLK_FREQ___S 21 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0___M 0xFFE00000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_REFCLK_0___S 21 + +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0 (0x005D4864) +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0__WL_BBPLL_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0__WL_BBPLL_NINT_OV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0__WL_BBPLL_NINT_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0__WL_BBPLL_NFRAC_OV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0__WL_BBPLL_NFRAC_OVD___POR 0x00000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0__WL_BBPLL_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0__WL_BBPLL_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0__WL_BBPLL_NINT_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0__WL_BBPLL_NINT_OV___S 27 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0__WL_BBPLL_NINT_OVD___M 0x07F00000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0__WL_BBPLL_NINT_OVD___S 20 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0__WL_BBPLL_NFRAC_OV___M 0x00040000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0__WL_BBPLL_NFRAC_OV___S 18 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0__WL_BBPLL_NFRAC_OVD___M 0x0003FFFF +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0__WL_BBPLL_NFRAC_OVD___S 0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0___M 0x3FF7FFFF +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_0___S 0 + +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1 (0x005D4868) +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1___POR 0x00000C00 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_KD_OV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_KD_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_KI_OV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_KI_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_PHASE_SHIFT___POR 0x00 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_OUTDIV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__D_WL_BBPLL_REFDIV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_RNG_OV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_RNG_OVD___POR 0x3 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_EN_NEGTRIG___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_SVS_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_FREQ___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__D_WL_BBPLL_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_KD_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_KD_OV___S 31 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_KD_OVD___M 0x78000000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_KD_OVD___S 27 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_KI_OV___M 0x04000000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_KI_OV___S 26 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_KI_OVD___M 0x03000000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_KI_OVD___S 24 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_PHASE_SHIFT___M 0x00FE0000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_PHASE_SHIFT___S 17 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_OUTDIV___M 0x00018000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_OUTDIV___S 15 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__D_WL_BBPLL_REFDIV___M 0x00006000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__D_WL_BBPLL_REFDIV___S 13 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_RNG_OV___M 0x00001000 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_RNG_OV___S 12 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_RNG_OVD___M 0x00000C00 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_RNG_OVD___S 10 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_EN_NEGTRIG___M 0x00000200 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_EN_NEGTRIG___S 9 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_SVS_MODE___M 0x00000100 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_SVS_MODE___S 8 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_FREQ___M 0x000000C0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__WL_BBPLL_FREQ___S 6 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__D_WL_BBPLL_ATB_SEL___M 0x00000007 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1__D_WL_BBPLL_ATB_SEL___S 0 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1___M 0xFFFFFFC7 +#define PHYA_IRON2G_RFA_CLKGEN_WL_BBPLL_1___S 0 + +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0 (0x005D486C) +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0___POR 0x01C00000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__REFCLK_BTFMPLL_CLK_MUX_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__REFCLK_BTFMPLL_CLK_MUX_SEL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__REFCLK_BTFMPLL_CLK_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__D_REFCLK_BTFMPLL_DIFF_EN___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__D_REFCLK_BTFMPLL_CLK_DRV___POR 0x3 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__REFCLK_BTFMPLL_FREQ___POR 0x2 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__REFCLK_BTFMPLL_CLK_MUX_SEL_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__REFCLK_BTFMPLL_CLK_MUX_SEL_OV___S 31 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__REFCLK_BTFMPLL_CLK_MUX_SEL_OVD___M 0x70000000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__REFCLK_BTFMPLL_CLK_MUX_SEL_OVD___S 28 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__REFCLK_BTFMPLL_CLK_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__REFCLK_BTFMPLL_CLK_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__D_REFCLK_BTFMPLL_DIFF_EN___M 0x02000000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__D_REFCLK_BTFMPLL_DIFF_EN___S 25 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__D_REFCLK_BTFMPLL_CLK_DRV___M 0x01800000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__D_REFCLK_BTFMPLL_CLK_DRV___S 23 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__REFCLK_BTFMPLL_FREQ___M 0x00600000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0__REFCLK_BTFMPLL_FREQ___S 21 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0___M 0xFFE00000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_REFCLK_0___S 21 + +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0 (0x005D4870) +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0__BTFMPLL_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0__BTFMPLL_NINT_OV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0__BTFMPLL_NINT_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0__BTFMPLL_NFRAC_OV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0__BTFMPLL_NFRAC_OVD___POR 0x00000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0__BTFMPLL_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0__BTFMPLL_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0__BTFMPLL_NINT_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0__BTFMPLL_NINT_OV___S 27 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0__BTFMPLL_NINT_OVD___M 0x07F00000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0__BTFMPLL_NINT_OVD___S 20 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0__BTFMPLL_NFRAC_OV___M 0x00040000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0__BTFMPLL_NFRAC_OV___S 18 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0__BTFMPLL_NFRAC_OVD___M 0x0003FFFF +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0__BTFMPLL_NFRAC_OVD___S 0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0___M 0x3FF7FFFF +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_0___S 0 + +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1 (0x005D4874) +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_KD_OV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_KD_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_KI_OV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_KI_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_PHASE_SHIFT___POR 0x00 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_OUTDIV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__D_BTFMPLL_REFDIV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_RNG_OV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_RNG_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_EN_NEGTRIG___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__D_BTFMPLL_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_KD_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_KD_OV___S 31 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_KD_OVD___M 0x78000000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_KD_OVD___S 27 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_KI_OV___M 0x04000000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_KI_OV___S 26 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_KI_OVD___M 0x03000000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_KI_OVD___S 24 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_PHASE_SHIFT___M 0x00FE0000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_PHASE_SHIFT___S 17 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_OUTDIV___M 0x00018000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_OUTDIV___S 15 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__D_BTFMPLL_REFDIV___M 0x00006000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__D_BTFMPLL_REFDIV___S 13 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_RNG_OV___M 0x00001000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_RNG_OV___S 12 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_RNG_OVD___M 0x00000C00 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_RNG_OVD___S 10 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_EN_NEGTRIG___M 0x00000200 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__BTFMPLL_EN_NEGTRIG___S 9 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__D_BTFMPLL_ATB_SEL___M 0x00000007 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1__D_BTFMPLL_ATB_SEL___S 0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1___M 0xFFFFFE07 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CGPLL_1___S 0 + +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0 (0x005D4878) +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0___POR 0x00000030 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__D_CLKGEN_CLK_48M_DIFF_EN___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__D_CLKGEN_CLK_48M_DRV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__D_CLKGEN_PMU_CLK_DIFF_EN___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__D_CLKGEN_PMU_CLK_DRV___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__USB_CLK_DIG_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_CLK_DIG_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_CLK_ADC_EN_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_CLK_ADC_EN_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_CLK_DAC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_DIG_CLK_FLIP___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_DAC_CLK_CAPTURE_FLIP___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_DAC_CLK_FLIP___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_ADC_CLK_FLIP_CH0___POR 0x1 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_ADC_CLK_FLIP_CH1___POR 0x1 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_DAC_ATE_CLK_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_DAC_CAPTURE_ATE_CLK_EDGE_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_ADC_ATE_CLK_SEL_CH0___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_ADC_ATE_CLK_SEL_CH1___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__D_CLKGEN_CLK_48M_DIFF_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__D_CLKGEN_CLK_48M_DIFF_EN___S 31 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__D_CLKGEN_CLK_48M_DRV___M 0x60000000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__D_CLKGEN_CLK_48M_DRV___S 29 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__D_CLKGEN_PMU_CLK_DIFF_EN___M 0x10000000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__D_CLKGEN_PMU_CLK_DIFF_EN___S 28 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__D_CLKGEN_PMU_CLK_DRV___M 0x0C000000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__D_CLKGEN_PMU_CLK_DRV___S 26 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__USB_CLK_DIG_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__USB_CLK_DIG_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_CLK_DIG_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_CLK_DIG_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_CLK_ADC_EN_CH0_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_CLK_ADC_EN_CH0_OVS___S 16 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_CLK_ADC_EN_CH1_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_CLK_ADC_EN_CH1_OVS___S 14 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_CLK_DAC_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_CLK_DAC_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_DIG_CLK_FLIP___M 0x00000100 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_DIG_CLK_FLIP___S 8 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_DAC_CLK_CAPTURE_FLIP___M 0x00000080 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_DAC_CLK_CAPTURE_FLIP___S 7 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_DAC_CLK_FLIP___M 0x00000040 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_DAC_CLK_FLIP___S 6 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_ADC_CLK_FLIP_CH0___M 0x00000020 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_ADC_CLK_FLIP_CH0___S 5 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_ADC_CLK_FLIP_CH1___M 0x00000010 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_ADC_CLK_FLIP_CH1___S 4 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_DAC_ATE_CLK_SEL___M 0x00000008 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_DAC_ATE_CLK_SEL___S 3 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_DAC_CAPTURE_ATE_CLK_EDGE_SEL___M 0x00000004 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_DAC_CAPTURE_ATE_CLK_EDGE_SEL___S 2 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_ADC_ATE_CLK_SEL_CH0___M 0x00000002 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_ADC_ATE_CLK_SEL_CH0___S 1 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_ADC_ATE_CLK_SEL_CH1___M 0x00000001 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0__BT_ADC_ATE_CLK_SEL_CH1___S 0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0___M 0xFC3FF1FF +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_0___S 0 + +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_1 (0x005D487C) +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_1__TEST_CLK_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_1__BT_FM_CLKGEN_RST_L_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_1__TEST_CLK_SEL___M 0xF0000000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_1__TEST_CLK_SEL___S 28 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_1__BT_FM_CLKGEN_RST_L_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_1__BT_FM_CLKGEN_RST_L_OVS___S 26 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_1___M 0xFC000000 +#define PHYA_IRON2G_RFA_CLKGEN_BTFM_CLKGEN_1___S 26 + +#define PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_0 (0x005D4880) +#define PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_0__RO_RAW_PLL_EN_WL_BBPLL___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_0__RO_FRAC_MODE_WL_BBPLL___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_0__RO_TMR_WL_BBPLL___POR 0x0000 +#define PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_0__RO_RAW_PLL_EN_WL_BBPLL___M 0x80000000 +#define PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_0__RO_RAW_PLL_EN_WL_BBPLL___S 31 +#define PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_0__RO_FRAC_MODE_WL_BBPLL___M 0x40000000 +#define PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_0__RO_FRAC_MODE_WL_BBPLL___S 30 +#define PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_0__RO_TMR_WL_BBPLL___M 0x00007FFF +#define PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_0__RO_TMR_WL_BBPLL___S 0 +#define PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_0___M 0xC0007FFF +#define PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_0___S 0 + +#define PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_1 (0x005D4884) +#define PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_1__RO_RAW_PLL_EN_BTFMPLL___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_1__RO_FRAC_MODE_BTFMPLL___POR 0x0 +#define PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_1__RO_TMR_BTFMPLL___POR 0x0000 +#define PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_1__RO_RAW_PLL_EN_BTFMPLL___M 0x80000000 +#define PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_1__RO_RAW_PLL_EN_BTFMPLL___S 31 +#define PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_1__RO_FRAC_MODE_BTFMPLL___M 0x40000000 +#define PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_1__RO_FRAC_MODE_BTFMPLL___S 30 +#define PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_1__RO_TMR_BTFMPLL___M 0x00007FFF +#define PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_1__RO_TMR_BTFMPLL___S 0 +#define PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_1___M 0xC0007FFF +#define PHYA_IRON2G_RFA_CLKGEN_RO_DPLL_JITTER_WAR_1___S 0 + +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0 (0x005D4C00) +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0___POR 0x00001F08 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__D_REDUCE_R___POR 0x0 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__SEL_1SDM___POR 0x0 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__LOCK_CNT_SET___POR 0x01F +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__D_SDMCLK_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__D_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__LOCK_THRESHOLD___POR 0x08 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__D_REDUCE_R___M 0x00040000 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__D_REDUCE_R___S 18 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__SEL_1SDM___M 0x00020000 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__SEL_1SDM___S 17 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__LOCK_CNT_SET___M 0x0001FF00 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__LOCK_CNT_SET___S 8 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__D_SDMCLK_SEL___M 0x000000C0 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__D_SDMCLK_SEL___S 6 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__D_ATB_SEL___M 0x00000020 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__D_ATB_SEL___S 5 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__LOCK_THRESHOLD___M 0x0000001F +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0__LOCK_THRESHOLD___S 0 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0___M 0x0007FFFF +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG0___S 0 + +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1 (0x005D4C04) +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1___POR 0x00002300 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__VC_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__D_VCOCLKDIV_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__D_DPLL_OUT_DIV_EN___POR 0x1 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__D_DPLL_OUTDIV_PLL_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__D_DPLL_FLIP_SDMCLK___POR 0x0 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__D_ICOTDC_CAPSEL___POR 0x3 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__VC_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__VC_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__VC_OV___S 31 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__D_VCOCLKDIV_SEL___M 0x00018000 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__D_VCOCLKDIV_SEL___S 15 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__D_DPLL_OUT_DIV_EN___M 0x00006000 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__D_DPLL_OUT_DIV_EN___S 13 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__D_DPLL_OUTDIV_PLL_SEL___M 0x00001000 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__D_DPLL_OUTDIV_PLL_SEL___S 12 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__D_DPLL_FLIP_SDMCLK___M 0x00000800 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__D_DPLL_FLIP_SDMCLK___S 11 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__D_ICOTDC_CAPSEL___M 0x00000700 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__D_ICOTDC_CAPSEL___S 8 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__VC_OVD___M 0x000000FF +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1__VC_OVD___S 0 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1___M 0x8001FFFF +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG1___S 0 + +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG2 (0x005D4C08) +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG2__DO_MEAS___POR 0x0 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG2__DO_MEAS___M 0x80000000 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG2__DO_MEAS___S 31 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG2___M 0x80000000 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG2___S 31 + +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3 (0x005D4C0C) +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3___POR 0x00000000 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3__D_SPARE___POR 0x00000 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3__TEST_IN___POR 0x000 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3__SEL_COUNT___POR 0x0 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3__RESET_TEST___POR 0x0 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3__PLL_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3__D_SPARE___M 0xFFFFC000 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3__D_SPARE___S 14 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3__TEST_IN___M 0x00003FF0 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3__TEST_IN___S 4 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3__SEL_COUNT___M 0x00000008 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3__SEL_COUNT___S 3 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3__RESET_TEST___M 0x00000004 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3__RESET_TEST___S 2 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3__PLL_EN_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3__PLL_EN_OVS___S 0 +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BTFMPLL_DPLL_REG3___S 0 + +#define PHYA_IRON2G_RFA_BTFMPLL_RO_DPLL (0x005D4C10) +#define PHYA_IRON2G_RFA_BTFMPLL_RO_DPLL___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BTFMPLL_RO_DPLL___POR 0x00000000 +#define PHYA_IRON2G_RFA_BTFMPLL_RO_DPLL__RO_LOCKED___POR 0x0 +#define PHYA_IRON2G_RFA_BTFMPLL_RO_DPLL__RO_VC_MEAS0___POR 0x00000 +#define PHYA_IRON2G_RFA_BTFMPLL_RO_DPLL__RO_VC_DIFF0___POR 0x000 +#define PHYA_IRON2G_RFA_BTFMPLL_RO_DPLL__RO_LOCKED___M 0x40000000 +#define PHYA_IRON2G_RFA_BTFMPLL_RO_DPLL__RO_LOCKED___S 30 +#define PHYA_IRON2G_RFA_BTFMPLL_RO_DPLL__RO_VC_MEAS0___M 0x3FFFF000 +#define PHYA_IRON2G_RFA_BTFMPLL_RO_DPLL__RO_VC_MEAS0___S 12 +#define PHYA_IRON2G_RFA_BTFMPLL_RO_DPLL__RO_VC_DIFF0___M 0x000003FF +#define PHYA_IRON2G_RFA_BTFMPLL_RO_DPLL__RO_VC_DIFF0___S 0 +#define PHYA_IRON2G_RFA_BTFMPLL_RO_DPLL___M 0x7FFFF3FF +#define PHYA_IRON2G_RFA_BTFMPLL_RO_DPLL___S 0 + +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG0 (0x005D5000) +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG0___POR 0x00001F88 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__D_REDUCE_R___POR 0x0 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__SEL_1SDM___POR 0x0 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__LOCK_CNT_SET___POR 0x01F +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__D_SDMCLK_SEL___POR 0x2 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__D_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__LOCK_THRESHOLD___POR 0x08 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__D_REDUCE_R___M 0x00040000 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__D_REDUCE_R___S 18 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__SEL_1SDM___M 0x00020000 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__SEL_1SDM___S 17 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__LOCK_CNT_SET___M 0x0001FF00 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__LOCK_CNT_SET___S 8 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__D_SDMCLK_SEL___M 0x000000C0 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__D_SDMCLK_SEL___S 6 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__D_ATB_SEL___M 0x00000020 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__D_ATB_SEL___S 5 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__LOCK_THRESHOLD___M 0x0000001F +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG0__LOCK_THRESHOLD___S 0 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG0___M 0x0007FFFF +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG0___S 0 + +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG1 (0x005D5004) +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG1___POR 0x0001E300 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__VC_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__D_VCOCLKDIV_SEL___POR 0x3 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__D_DPLL_OUT_DIV_EN___POR 0x3 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__D_DPLL_OUTDIV_PLL_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__D_DPLL_FLIP_SDMCLK___POR 0x0 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__D_ICOTDC_CAPSEL___POR 0x3 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__VC_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__VC_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__VC_OV___S 31 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__D_VCOCLKDIV_SEL___M 0x00018000 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__D_VCOCLKDIV_SEL___S 15 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__D_DPLL_OUT_DIV_EN___M 0x00006000 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__D_DPLL_OUT_DIV_EN___S 13 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__D_DPLL_OUTDIV_PLL_SEL___M 0x00001000 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__D_DPLL_OUTDIV_PLL_SEL___S 12 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__D_DPLL_FLIP_SDMCLK___M 0x00000800 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__D_DPLL_FLIP_SDMCLK___S 11 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__D_ICOTDC_CAPSEL___M 0x00000700 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__D_ICOTDC_CAPSEL___S 8 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__VC_OVD___M 0x000000FF +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG1__VC_OVD___S 0 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG1___M 0x8001FFFF +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG1___S 0 + +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG2 (0x005D5008) +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG2__DO_MEAS___POR 0x0 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG2__DO_MEAS___M 0x80000000 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG2__DO_MEAS___S 31 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG2___M 0x80000000 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG2___S 31 + +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG3 (0x005D500C) +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG3___POR 0x80000000 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG3__D_SPARE___POR 0x20000 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG3__TEST_IN___POR 0x000 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG3__SEL_COUNT___POR 0x0 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG3__RESET_TEST___POR 0x0 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG3__PLL_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG3__D_SPARE___M 0xFFFFC000 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG3__D_SPARE___S 14 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG3__TEST_IN___M 0x00003FF0 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG3__TEST_IN___S 4 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG3__SEL_COUNT___M 0x00000008 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG3__SEL_COUNT___S 3 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG3__RESET_TEST___M 0x00000004 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG3__RESET_TEST___S 2 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG3__PLL_EN_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG3__PLL_EN_OVS___S 0 +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BBPLL_DPLL_REG3___S 0 + +#define PHYA_IRON2G_RFA_BBPLL_RO_DPLL (0x005D5010) +#define PHYA_IRON2G_RFA_BBPLL_RO_DPLL___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BBPLL_RO_DPLL___POR 0x00000000 +#define PHYA_IRON2G_RFA_BBPLL_RO_DPLL__RO_LOCKED___POR 0x0 +#define PHYA_IRON2G_RFA_BBPLL_RO_DPLL__RO_VC_MEAS0___POR 0x00000 +#define PHYA_IRON2G_RFA_BBPLL_RO_DPLL__RO_VC_DIFF0___POR 0x000 +#define PHYA_IRON2G_RFA_BBPLL_RO_DPLL__RO_LOCKED___M 0x40000000 +#define PHYA_IRON2G_RFA_BBPLL_RO_DPLL__RO_LOCKED___S 30 +#define PHYA_IRON2G_RFA_BBPLL_RO_DPLL__RO_VC_MEAS0___M 0x3FFFF000 +#define PHYA_IRON2G_RFA_BBPLL_RO_DPLL__RO_VC_MEAS0___S 12 +#define PHYA_IRON2G_RFA_BBPLL_RO_DPLL__RO_VC_DIFF0___M 0x000003FF +#define PHYA_IRON2G_RFA_BBPLL_RO_DPLL__RO_VC_DIFF0___S 0 +#define PHYA_IRON2G_RFA_BBPLL_RO_DPLL___M 0x7FFFF3FF +#define PHYA_IRON2G_RFA_BBPLL_RO_DPLL___S 0 + +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN (0x005D5400) +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN___POR 0x0000000C +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYA_RST_WLCLKGEN_L_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYB_RST_WLCLKGEN_L_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYA_WL_CLK_EN_ASYNC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYB_WL_CLK_EN_ASYNC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__D_WL_TOP_CLKGEN_PHYB_PLLBYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__D_WL_TOP_CLKGEN_PHYA_PLLBYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYA_DIGCLK480M_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYB_DIGCLK480M_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__D_PHYA_ANLGCLK480M_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__D_PHYB_ANLGCLK480M_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__C_PHYA_PLLCLK320M_EN_ATOP___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__RFA_WL_240M_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYA_RST_WLCLKGEN_L_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYA_RST_WLCLKGEN_L_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYB_RST_WLCLKGEN_L_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYB_RST_WLCLKGEN_L_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYA_WL_CLK_EN_ASYNC_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYA_WL_CLK_EN_ASYNC_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYB_WL_CLK_EN_ASYNC_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYB_WL_CLK_EN_ASYNC_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__D_WL_TOP_CLKGEN_PHYB_PLLBYPASS___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__D_WL_TOP_CLKGEN_PHYB_PLLBYPASS___S 14 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__D_WL_TOP_CLKGEN_PHYA_PLLBYPASS___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__D_WL_TOP_CLKGEN_PHYA_PLLBYPASS___S 12 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYA_DIGCLK480M_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYA_DIGCLK480M_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYB_DIGCLK480M_EN_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__PHYB_DIGCLK480M_EN_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__D_PHYA_ANLGCLK480M_EN_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__D_PHYA_ANLGCLK480M_EN_OVS___S 6 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__D_PHYB_ANLGCLK480M_EN_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__D_PHYB_ANLGCLK480M_EN_OVS___S 4 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__C_PHYA_PLLCLK320M_EN_ATOP___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__C_PHYA_PLLCLK320M_EN_ATOP___S 3 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__RFA_WL_240M_EN___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN__RFA_WL_240M_EN___S 2 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN___M 0x00FF5FFC +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN___S 2 + +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1 (0x005D5404) +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1___POR 0x0000000F +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1__D_DAC_CLK_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1__D_ANLG1920M_5G_CH1_BUF_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1__D_ANLG1920M_5G_COMMON_BUF_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1__D_ANLG1920M_2G_CH1_BUF_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1__D_ANLG1920M_2G_COMMON_BUF_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1__D_DAC_CLK_SEL___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1__D_DAC_CLK_SEL___S 4 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1__D_ANLG1920M_5G_CH1_BUF_EN___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1__D_ANLG1920M_5G_CH1_BUF_EN___S 3 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1__D_ANLG1920M_5G_COMMON_BUF_EN___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1__D_ANLG1920M_5G_COMMON_BUF_EN___S 2 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1__D_ANLG1920M_2G_CH1_BUF_EN___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1__D_ANLG1920M_2G_CH1_BUF_EN___S 1 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1__D_ANLG1920M_2G_COMMON_BUF_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1__D_ANLG1920M_2G_COMMON_BUF_EN___S 0 +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_TOP_CLKGEN_TOP_CLKGEN_1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH0 (0x005D6000) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH0___POR 0x0221D532 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH0__NBNA___POR 0x004 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH0__NF___POR 0x21D532 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH0__NBNA___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH0__NBNA___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH0__NF___M 0x007FFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH0__NF___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH0___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1 (0x005D6004) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__SD_NF_OFFSET___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__BSTARGET_OFS_COARSE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__BSTARGET_OFS_FINE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__BS_COARSE_FINE_BDRY___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__SD_NF_OFFSET___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__SD_NF_OFFSET___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__BSTARGET_OFS_COARSE___M 0x0000FC00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__BSTARGET_OFS_COARSE___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__BSTARGET_OFS_FINE___M 0x000003F0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__BSTARGET_OFS_FINE___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__BS_COARSE_FINE_BDRY___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1__BS_COARSE_FINE_BDRY___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2 (0x005D6008) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2___POR 0x0042AAAA +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_DELTA_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_BASE_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_START___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_DELTA___POR 0x42AAAA +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_DELTA_SEL___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_DELTA_SEL___S 27 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_BASE_SEL___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_BASE_SEL___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_DIS___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_DIS___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_START___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_START___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_DELTA___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2__FC_DELTA___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2___M 0x0FFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH2___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH3 (0x005D600C) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH3___POR 0x55000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH3__FC_DELTA_SUB___POR 0x0AA +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH3__FC_DELTA_SUB___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH3__FC_DELTA_SUB___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH3___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_CH3___S 23 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0 (0x005D6010) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0___POR 0x116C2599 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSSTART___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSMODE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BKSHFT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSSETT___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSWAIT___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSSAMPLE___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__LPF_VTUNEMON_TMR___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_RFCNT_OUT_TIME___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__RFCNTEN_DLY_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_VMID_NON_HB___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_VMID_HB___POR 0x9 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_CLBS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__NF0B___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__D_DTIM_FBDIV4_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__DISABLE_LPF_TMR___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSSTART___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSSTART___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSMODE___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSMODE___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BKSHFT___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BKSHFT___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSSETT___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSSETT___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSWAIT___M 0x00E00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSWAIT___S 21 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSSAMPLE___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BSSAMPLE___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__LPF_VTUNEMON_TMR___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__LPF_VTUNEMON_TMR___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_RFCNT_OUT_TIME___M 0x0000E000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_RFCNT_OUT_TIME___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__RFCNTEN_DLY_DIS___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__RFCNTEN_DLY_DIS___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_VMID_NON_HB___M 0x00000F00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_VMID_NON_HB___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_VMID_HB___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_VMID_HB___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_CLBS_EN___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__BS_CLBS_EN___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__NF0B___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__NF0B___S 2 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__D_DTIM_FBDIV4_SEL___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__D_DTIM_FBDIV4_SEL___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__DISABLE_LPF_TMR___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0__DISABLE_LPF_TMR___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS0___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1 (0x005D6014) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1___POR 0x80680000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SDM_SEL___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SDMOGAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__BSTESTEN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SDTESTEN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SD_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__D_PLLMD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__BS_OVCAL_BDRY___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__PLL_SLIP_DET_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__RESTORE_BS_CLBS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__DTEST2_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__DTEST1_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__DTEST0_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SDM_SEL___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SDM_SEL___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SDMOGAIN___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SDMOGAIN___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__BSTESTEN___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__BSTESTEN___S 27 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SDTESTEN___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SDTESTEN___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SD_RESET___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__SD_RESET___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__D_PLLMD___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__D_PLLMD___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__BS_OVCAL_BDRY___M 0x00E00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__BS_OVCAL_BDRY___S 21 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__PLL_SLIP_DET_RESET___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__PLL_SLIP_DET_RESET___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__RESTORE_BS_CLBS_EN___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__RESTORE_BS_CLBS_EN___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__DTEST2_SEL___M 0x00007C00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__DTEST2_SEL___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__DTEST1_SEL___M 0x000003E0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__DTEST1_SEL___S 5 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__DTEST0_SEL___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1__DTEST0_SEL___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1___M 0xFFF87FFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS2 (0x005D6018) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS2___POR 0x04000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS2__IVCOBK___POR 0x400 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS2__TSTCNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS2__IVCOBK___M 0x07FF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS2__IVCOBK___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS2__TSTCNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS2__TSTCNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS2___M 0x07FFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_WL_SYNTH_LP2G_BS2___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS0 (0x005D601C) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS0__RO_BSTARGET___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS0__RO_BSCOUNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS0__RO_BSTARGET___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS0__RO_BSTARGET___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS0__RO_BSCOUNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS0__RO_BSCOUNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS0___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1 (0x005D6020) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_VC_2HI___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_VC_2LO___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BIST_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_FVCOBK___POR 0x000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B3___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B3___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B2___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B2___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B1___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B1___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B0___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSDELTA_B0___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_VC_2HI___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_VC_2HI___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_VC_2LO___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_VC_2LO___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BIST_ON___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BIST_ON___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSON___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_BSON___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_FVCOBK___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1__RO_FVCOBK___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1___M 0xFFFF7FFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2 (0x005D6024) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_SYN_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_SYN_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_SYN_EN_REC_LO___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_ANY_RX_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_ANY_TX_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_CLBS_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_TX_MASK___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2HI_AT_VTUNEMON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2LO_AT_VTUNEMON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2HI_AFTER_VTUNEMON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2LO_AFTER_VTUNEMON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_PLL_LOCK_DET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_PLL_LOCK___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_DLL_LOCKED___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_NON_DTIM_5G___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_BS_VMID___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_CHAN_IDX___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_SYN_MODE___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_SYN_MODE___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_SYN_EN___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_SYN_EN___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_SYN_EN_REC_LO___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_SYN_EN_REC_LO___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_ANY_RX_EN___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_ANY_RX_EN___S 27 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_ANY_TX_EN___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_ANY_TX_EN___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_CLBS_ON___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_CLBS_ON___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_TX_MASK___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_TX_MASK___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2HI_AT_VTUNEMON___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2HI_AT_VTUNEMON___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2LO_AT_VTUNEMON___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2LO_AT_VTUNEMON___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2HI_AFTER_VTUNEMON___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2HI_AFTER_VTUNEMON___S 17 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2LO_AFTER_VTUNEMON___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_VC_2LO_AFTER_VTUNEMON___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_PLL_LOCK_DET___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_PLL_LOCK_DET___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_PLL_LOCK___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_PLL_LOCK___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_DLL_LOCKED___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_DLL_LOCKED___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_NON_DTIM_5G___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_NON_DTIM_5G___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_BS_VMID___M 0x00000F00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_BS_VMID___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_CHAN_IDX___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2__RO_CHAN_IDX___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2___M 0xFF0FFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS2___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS3 (0x005D6028) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS3__RO_NBNA___POR 0x000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS3__RO_NBNA___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS3__RO_NBNA___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS3___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS3___S 23 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS4 (0x005D602C) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS4___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS4__RO_NF___POR 0x000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS4__RO_NF___M 0x007FFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS4__RO_NF___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS4___M 0x007FFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS4___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS5 (0x005D6030) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS5___POR 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS5__CLBS_QS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS5__CLBS_QS_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS5__CLBS_QS_EN___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS5___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS5___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS6 (0x005D6034) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS6__BANK_DBG_OFFSET___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS6__RO_INIT_BANK___POR 0x000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS6__BANK_DBG_OFFSET___M 0x0001F800 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS6__BANK_DBG_OFFSET___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS6__RO_INIT_BANK___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS6__RO_INIT_BANK___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS6___M 0x0001FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BS_RO_WL_SYNTH_LP2G_BS6___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0 (0x005D6040) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0___POR 0x44A43E4A +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_START___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_ENABLE_VC___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_ENABLE_TX___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_ENABLE_RX___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_MODE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_COMP_REPEAT___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_SMPL_RATE___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_MAX_STEP___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_STEPSIZE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_HYBRID_BDRY___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_SETTIME___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_SAMPLE___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_MASK_SEL___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_PSYNC_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_START___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_START___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_ENABLE_VC___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_ENABLE_VC___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_ENABLE_TX___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_ENABLE_TX___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_ENABLE_RX___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_ENABLE_RX___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_MODE___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_MODE___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_COMP_REPEAT___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_COMP_REPEAT___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_SMPL_RATE___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_SMPL_RATE___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_MAX_STEP___M 0x00078000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_MAX_STEP___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_STEPSIZE___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_STEPSIZE___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_HYBRID_BDRY___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_HYBRID_BDRY___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_SETTIME___M 0x00000380 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_SETTIME___S 7 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_SAMPLE___M 0x00000070 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_SAMPLE___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_MASK_SEL___M 0x0000000C +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_MASK_SEL___S 2 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_PSYNC_EN___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0__CLBS_PSYNC_EN___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0___M 0xFCFFFFFE +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS0___S 1 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1 (0x005D6044) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1___POR 0xB4208000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_BDRY___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_INC___POR 0x08 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_DEC___POR 0x08 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_SAMPLE_RESTORE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_EN___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_BDRY___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_BDRY___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_INC___M 0x0F800000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_INC___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_DEC___M 0x007C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_OVSKIP_DEC___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_SAMPLE_RESTORE___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1__CLBS_SAMPLE_RESTORE___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1___M 0xFFFF8000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS1___S 15 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS (0x005D6048) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS__RO_CLBS_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS__RO_NON_DTIM_5G___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS__RO_CLBS_OFF_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS__RO_CLBS_MODE___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS__RO_CLBS_MODE___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS__RO_NON_DTIM_5G___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS__RO_NON_DTIM_5G___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS__RO_CLBS_OFF_SEL___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS__RO_CLBS_OFF_SEL___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_RO_WL_SYNTH_LP2G_CLBS___S 24 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2 (0x005D604C) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2__CLBS_OFF_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2__CLBS_OFF_SEL_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2__CLBS_LIN_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2__CLBS_OFF_SEL_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2__CLBS_OFF_SEL_OV___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2__CLBS_OFF_SEL_OVD___M 0x7C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2__CLBS_OFF_SEL_OVD___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2__CLBS_LIN_EN___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2__CLBS_LIN_EN___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS2___S 25 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_0 (0x005D6050) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_0___POR 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_0__CLBS_LIN_OFFSET_0___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_0__CLBS_LIN_OFFSET_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_0__CLBS_LIN_OFFSET_0___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_0___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_1 (0x005D6054) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_1___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_1__CLBS_LIN_OFFSET_1___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_1__CLBS_LIN_OFFSET_1___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_1__CLBS_LIN_OFFSET_1___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_1___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_1___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_2 (0x005D6058) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_2___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_2__CLBS_LIN_OFFSET_2___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_2__CLBS_LIN_OFFSET_2___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_2__CLBS_LIN_OFFSET_2___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_2___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_2___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_3 (0x005D605C) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_3___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_3__CLBS_LIN_OFFSET_3___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_3__CLBS_LIN_OFFSET_3___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_3__CLBS_LIN_OFFSET_3___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_3___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_3___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_4 (0x005D6060) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_4___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_4__CLBS_LIN_OFFSET_4___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_4__CLBS_LIN_OFFSET_4___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_4__CLBS_LIN_OFFSET_4___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_4___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_4___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_5 (0x005D6064) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_5___POR 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_5__CLBS_LIN_OFFSET_5___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_5__CLBS_LIN_OFFSET_5___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_5__CLBS_LIN_OFFSET_5___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_5___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_5___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_6 (0x005D6068) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_6___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_6__CLBS_LIN_OFFSET_6___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_6__CLBS_LIN_OFFSET_6___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_6__CLBS_LIN_OFFSET_6___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_6___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_6___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_7 (0x005D606C) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_7___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_7__CLBS_LIN_OFFSET_7___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_7__CLBS_LIN_OFFSET_7___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_7__CLBS_LIN_OFFSET_7___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_7___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_7___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_8 (0x005D6070) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_8___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_8__CLBS_LIN_OFFSET_8___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_8__CLBS_LIN_OFFSET_8___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_8__CLBS_LIN_OFFSET_8___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_8___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_8___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_9 (0x005D6074) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_9___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_9__CLBS_LIN_OFFSET_9___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_9__CLBS_LIN_OFFSET_9___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_9__CLBS_LIN_OFFSET_9___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_9___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_9___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_10 (0x005D6078) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_10___POR 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_10__CLBS_LIN_OFFSET_10___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_10__CLBS_LIN_OFFSET_10___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_10__CLBS_LIN_OFFSET_10___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_10___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_10___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_11 (0x005D607C) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_11___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_11__CLBS_LIN_OFFSET_11___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_11__CLBS_LIN_OFFSET_11___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_11__CLBS_LIN_OFFSET_11___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_11___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_11___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_12 (0x005D6080) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_12___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_12__CLBS_LIN_OFFSET_12___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_12__CLBS_LIN_OFFSET_12___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_12__CLBS_LIN_OFFSET_12___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_12___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_12___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_13 (0x005D6084) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_13___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_13__CLBS_LIN_OFFSET_13___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_13__CLBS_LIN_OFFSET_13___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_13__CLBS_LIN_OFFSET_13___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_13___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_13___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_14 (0x005D6088) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_14___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_14__CLBS_LIN_OFFSET_14___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_14__CLBS_LIN_OFFSET_14___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_14__CLBS_LIN_OFFSET_14___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_14___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_14___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_15 (0x005D608C) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_15___POR 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_15__CLBS_LIN_OFFSET_15___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_15__CLBS_LIN_OFFSET_15___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_15__CLBS_LIN_OFFSET_15___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_15___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_15___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_16 (0x005D6090) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_16___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_16__CLBS_LIN_OFFSET_16___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_16__CLBS_LIN_OFFSET_16___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_16__CLBS_LIN_OFFSET_16___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_16___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_16___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_17 (0x005D6094) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_17___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_17__CLBS_LIN_OFFSET_17___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_17__CLBS_LIN_OFFSET_17___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_17__CLBS_LIN_OFFSET_17___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_17___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_17___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_18 (0x005D6098) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_18___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_18__CLBS_LIN_OFFSET_18___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_18__CLBS_LIN_OFFSET_18___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_18__CLBS_LIN_OFFSET_18___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_18___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_18___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_19 (0x005D609C) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_19___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_19__CLBS_LIN_OFFSET_19___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_19__CLBS_LIN_OFFSET_19___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_19__CLBS_LIN_OFFSET_19___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_19___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_19___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_20 (0x005D60A0) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_20___POR 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_20__CLBS_LIN_OFFSET_20___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_20__CLBS_LIN_OFFSET_20___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_20__CLBS_LIN_OFFSET_20___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_20___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_20___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_21 (0x005D60A4) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_21___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_21__CLBS_LIN_OFFSET_21___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_21__CLBS_LIN_OFFSET_21___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_21__CLBS_LIN_OFFSET_21___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_21___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_21___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_22 (0x005D60A8) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_22___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_22__CLBS_LIN_OFFSET_22___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_22__CLBS_LIN_OFFSET_22___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_22__CLBS_LIN_OFFSET_22___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_22___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_22___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_23 (0x005D60AC) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_23___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_23__CLBS_LIN_OFFSET_23___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_23__CLBS_LIN_OFFSET_23___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_23__CLBS_LIN_OFFSET_23___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_23___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_23___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_24 (0x005D60B0) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_24___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_24__CLBS_LIN_OFFSET_24___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_24__CLBS_LIN_OFFSET_24___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_24__CLBS_LIN_OFFSET_24___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_24___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_24___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_25 (0x005D60B4) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_25___POR 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_25__CLBS_LIN_OFFSET_25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_25__CLBS_LIN_OFFSET_25___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_25__CLBS_LIN_OFFSET_25___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_25___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_25___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_26 (0x005D60B8) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_26___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_26__CLBS_LIN_OFFSET_26___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_26__CLBS_LIN_OFFSET_26___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_26__CLBS_LIN_OFFSET_26___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_26___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_26___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_27 (0x005D60BC) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_27___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_27__CLBS_LIN_OFFSET_27___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_27__CLBS_LIN_OFFSET_27___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_27__CLBS_LIN_OFFSET_27___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_27___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_27___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_28 (0x005D60C0) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_28___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_28__CLBS_LIN_OFFSET_28___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_28__CLBS_LIN_OFFSET_28___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_28__CLBS_LIN_OFFSET_28___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_28___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_28___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_29 (0x005D60C4) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_29___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_29__CLBS_LIN_OFFSET_29___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_29__CLBS_LIN_OFFSET_29___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_29__CLBS_LIN_OFFSET_29___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_29___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_29___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_30 (0x005D60C8) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_30___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_30__CLBS_LIN_OFFSET_30___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_30__CLBS_LIN_OFFSET_30___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_30__CLBS_LIN_OFFSET_30___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_30___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_30___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_31 (0x005D60CC) +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_31___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_31__CLBS_LIN_OFFSET_31___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_31__CLBS_LIN_OFFSET_31___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_31__CLBS_LIN_OFFSET_31___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_31___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_CLBS_WL_SYNTH_LP2G_CLBS_31___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST (0x005D6100) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST___POR 0x06C0F998 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_START___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_VMID_KVCOM___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_VMID_KVCOH___POR 0xC +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_VMID_KVCOL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__EN_VCO_BIST___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__EN_NDIV_BIST___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__EN_RFCNT_BIST___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_RFCNT_OUT_TIME___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_TIME___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_WAIT___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__NDIV_BIST_TIME___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_START___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_START___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_MODE___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_MODE___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_VMID_KVCOM___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_VMID_KVCOM___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_VMID_KVCOH___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_VMID_KVCOH___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_VMID_KVCOL___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_VMID_KVCOL___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__EN_VCO_BIST___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__EN_VCO_BIST___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__EN_NDIV_BIST___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__EN_NDIV_BIST___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__EN_RFCNT_BIST___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__EN_RFCNT_BIST___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_RFCNT_OUT_TIME___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_RFCNT_OUT_TIME___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_TIME___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_TIME___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_WAIT___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__BIST_WAIT___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__NDIV_BIST_TIME___M 0x00000038 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST__NDIV_BIST_TIME___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST___M 0xFFFFFFF8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_WL_SYNTH_LP2G_BIST___S 3 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0 (0x005D6104) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_RFCNT_BIST_PASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_RFCNT_LATCH_TYPE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_BIST_OVERLAP___POR 0x000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_BIST_MONO___POR 0x000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_RFCNT_BIST_PASS___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_RFCNT_BIST_PASS___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_RFCNT_LATCH_TYPE___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_RFCNT_LATCH_TYPE___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_BIST_OVERLAP___M 0x07FF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_BIST_OVERLAP___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_BIST_MONO___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0__RO_BIST_MONO___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0___M 0xC7FF07FF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST0___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST1 (0x005D6108) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST1___POR 0x7FFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST1__RO_OVERLAP_CNT_DIFF___POR 0x7FFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST1__RO_OVERLAP_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST1__RO_OVERLAP_CNT_DIFF___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST1__RO_OVERLAP_CNT_DIFF___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST1__RO_OVERLAP_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST1__RO_OVERLAP_CNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST2 (0x005D610C) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST2___POR 0x7FFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST2__RO_MONO_CNT_DIFF___POR 0x7FFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST2__RO_MONO_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST2__RO_MONO_CNT_DIFF___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST2__RO_MONO_CNT_DIFF___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST2__RO_MONO_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST2__RO_MONO_CNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST2___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST3 (0x005D6110) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST3__RO_MIN_BANK_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST3__RO_MAX_BANK_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST3__RO_MIN_BANK_CNT___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST3__RO_MIN_BANK_CNT___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST3__RO_MAX_BANK_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST3__RO_MAX_BANK_CNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST3___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST4 (0x005D6114) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST4___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST4__RO_ONEBANK_LOW_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST4__RO_ONEBANK_MID_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST4__RO_ONEBANK_LOW_CNT___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST4__RO_ONEBANK_LOW_CNT___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST4__RO_ONEBANK_MID_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST4__RO_ONEBANK_MID_CNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST4___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST5 (0x005D6118) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST5___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST5__RO_ONEBANK_HIGH_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST5__RO_RFCNT_BIST_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST5__RO_ONEBANK_HIGH_CNT___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST5__RO_ONEBANK_HIGH_CNT___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST5__RO_RFCNT_BIST_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST5__RO_RFCNT_BIST_CNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST5___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST5___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST6 (0x005D611C) +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST6___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST6__RO_NDIV_BIST_CNT_55___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST6__RO_NDIV_BIST_CNT_AA___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST6__RO_NDIV_BIST_CNT_55___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST6__RO_NDIV_BIST_CNT_55___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST6__RO_NDIV_BIST_CNT_AA___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST6__RO_NDIV_BIST_CNT_AA___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST6___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_BIST_RO_WL_SYNTH_LP2G_BIST6___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0 (0x005D6140) +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0___POR 0x00010000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__ATOP_ISO_DIS_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__SDM_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__EN_DCLK___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__VC_2HI_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__VC_2LO_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__SYN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__SYN_EN_REC_LO_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__FASTCH_TMR___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__FASTCH_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__RFCNT_BSCLK_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__RFCNT_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__RFCNT_OUT_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__PRES_RSTB_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__VCON_SW_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__DLL_LOCKED_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__ATOP_ISO_DIS_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__ATOP_ISO_DIS_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__SDM_EN___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__SDM_EN___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__EN_DCLK___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__EN_DCLK___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__VC_2HI_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__VC_2HI_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__VC_2LO_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__VC_2LO_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__SYN_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__SYN_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__SYN_EN_REC_LO_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__SYN_EN_REC_LO_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__FASTCH_TMR___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__FASTCH_TMR___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__FASTCH_SEL___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__FASTCH_SEL___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__RFCNT_BSCLK_EN_OVS___M 0x00001800 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__RFCNT_BSCLK_EN_OVS___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__RFCNT_EN_OVS___M 0x00000600 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__RFCNT_EN_OVS___S 9 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__RFCNT_OUT_EN_OVS___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__RFCNT_OUT_EN_OVS___S 7 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__PRES_RSTB_OVS___M 0x00000060 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__PRES_RSTB_OVS___S 5 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__VCON_SW_OVS___M 0x00000018 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__VCON_SW_OVS___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__DLL_LOCKED_OVS___M 0x00000006 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0__DLL_LOCKED_OVS___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC0___S 1 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1 (0x005D6144) +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__VMID_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__PRECH_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__PFD_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__CP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__PRNDIV_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LPF_VCMON_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__BIAS_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__CP_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__VCO_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_VCOBUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_VCO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_LOGEN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_PFD_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_CP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_FBDIV_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__VMID_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__VMID_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__PRECH_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__PRECH_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__PFD_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__PFD_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__CP_EN_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__CP_EN_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__BIAS_EN_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__BIAS_EN_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__PRNDIV_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__PRNDIV_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LPF_VCMON_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LPF_VCMON_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__BIAS_FC_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__BIAS_FC_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__CP_FC_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__CP_FC_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__VCO_FC_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__VCO_FC_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_VCOBUF_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_VCOBUF_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_VCO_EN_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_VCO_EN_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_LOGEN_EN_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_LOGEN_EN_OVS___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_PFD_EN_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_PFD_EN_OVS___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_CP_EN_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_CP_EN_OVS___S 2 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_FBDIV_EN_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1__LDO_FBDIV_EN_OVS___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2 (0x005D6148) +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_MODE_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_VCO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOGEN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOGEN_DIV2_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOMIX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOAMP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOBUF_CH0_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOBUF_CH1_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOSYNC_RX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOSYNC_TX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__VC_ISO_DIS_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_VCO_EN_6G_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_MODE_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_MODE_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_VCO_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_VCO_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOGEN_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOGEN_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOGEN_DIV2_EN_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOGEN_DIV2_EN_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOMIX_EN_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOMIX_EN_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOAMP_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOAMP_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOBUF_CH0_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOBUF_CH0_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOBUF_CH1_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOBUF_CH1_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOSYNC_RX_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOSYNC_RX_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOSYNC_TX_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_LOSYNC_TX_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__VC_ISO_DIS_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__VC_ISO_DIS_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_VCO_EN_6G_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2__HB_VCO_EN_6G_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2___M 0xFFFFFF00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC2___S 8 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3 (0x005D614C) +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_MODE_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_DIV2_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_DIV2BUF_FB_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_DIV2BUF_LO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_LOGEN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_LOGEN_DRV_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_FBN_BUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_BUF_CH0_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_BUF_CH1_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LDO_DTIM_VCO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LDO_DTIM_VCO_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_PRNDIV_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_DRV_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_LB_MODE_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_HB_MODE_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_MODE_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_MODE_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_DIV2_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_DIV2_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_DIV2BUF_FB_EN_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_DIV2BUF_FB_EN_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_DIV2BUF_LO_EN_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_VCO_DIV2BUF_LO_EN_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_LOGEN_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_LOGEN_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_LOGEN_DRV_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_LOGEN_DRV_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_FBN_BUF_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_FBN_BUF_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_BUF_CH0_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_BUF_CH0_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_BUF_CH1_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LB_BUF_CH1_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LDO_DTIM_VCO_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LDO_DTIM_VCO_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LDO_DTIM_VCO_FC_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__LDO_DTIM_VCO_FC_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_PRNDIV_EN_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_PRNDIV_EN_OVS___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_DRV_EN_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_DRV_EN_OVS___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_LB_MODE_EN_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_LB_MODE_EN_OVS___S 2 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_HB_MODE_EN_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3__DTIM_HB_MODE_EN_OVS___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC3___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4 (0x005D6150) +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__SYN_MODE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__SYN_MODE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__ANY_TX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__ANY_RX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__CHAN_IDX_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__CHAN_IDX_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__SYN_MODE_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__SYN_MODE_OV___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__SYN_MODE_OVD___M 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__SYN_MODE_OVD___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__ANY_TX_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__ANY_TX_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__ANY_RX_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__ANY_RX_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__CHAN_IDX_OV___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__CHAN_IDX_OV___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__CHAN_IDX_OVD___M 0x00007FC0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4__CHAN_IDX_OVD___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4___M 0xE00FFFC0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC4___S 6 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5 (0x005D6154) +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LDO_VCO_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LDO_CPLVL_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LOBIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LOBIAS_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2LATCH_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2OBUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2_IBUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2_CORE_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2_OBUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LPVCO_DIV2_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LPVCO_FBCLK_IP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LPVCO_FBCLK_IM_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LDO_VCO_FC_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LDO_VCO_FC_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LDO_CPLVL_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LDO_CPLVL_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LOBIAS_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LOBIAS_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LOBIAS_FC_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__LOBIAS_FC_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2LATCH_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2LATCH_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2OBUF_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2OBUF_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2_IBUF_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2_IBUF_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2_CORE_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2_CORE_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2_OBUF_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LODIV2_OBUF_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LPVCO_DIV2_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LPVCO_DIV2_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LPVCO_FBCLK_IP_EN_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LPVCO_FBCLK_IP_EN_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LPVCO_FBCLK_IM_EN_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5__HB_LPVCO_FBCLK_IM_EN_OVS___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5___M 0xFF3FFFC0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC5___S 6 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6 (0x005D6158) +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6___POR 0x00001C00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__LB_LODIV2_PREBUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__LB_LODIV2_CORE_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__LB_LODIV2_POSTBUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__VCO_VARAC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__FASTCH_TMR_RESTORE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2LATCH_EN_OPT___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2OBUF_EN_OPT___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LOMIX_EN_OPT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LOAMP_EN_OPT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2_IBUF_EN_OPT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2_CORE_EN_OPT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2_OBUF_EN_OPT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__LB_LODIV2_PREBUF_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__LB_LODIV2_PREBUF_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__LB_LODIV2_CORE_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__LB_LODIV2_CORE_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__LB_LODIV2_POSTBUF_EN_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__LB_LODIV2_POSTBUF_EN_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__VCO_VARAC_EN_OVS___M 0x00018000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__VCO_VARAC_EN_OVS___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__FASTCH_TMR_RESTORE___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__FASTCH_TMR_RESTORE___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2LATCH_EN_OPT___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2LATCH_EN_OPT___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2OBUF_EN_OPT___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2OBUF_EN_OPT___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LOMIX_EN_OPT___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LOMIX_EN_OPT___S 9 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LOAMP_EN_OPT___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LOAMP_EN_OPT___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2_IBUF_EN_OPT___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2_IBUF_EN_OPT___S 7 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2_CORE_EN_OPT___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2_CORE_EN_OPT___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2_OBUF_EN_OPT___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6__HB_LODIV2_OBUF_EN_OPT___S 5 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6___M 0x3F01FFE0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC6___S 5 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7 (0x005D615C) +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__ENBR_IN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__ENBF_IN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__SD_ISO_L_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__SD_PRESET_L_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__ENBR_IN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__ENBR_IN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__ENBF_IN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__ENBF_IN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__SD_ISO_L_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__SD_ISO_L_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__SD_PRESET_L_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7__SD_PRESET_L_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC7___S 24 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8 (0x005D6160) +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8___POR 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__VCON_SW_LEG___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__VCON_SW_OPT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__SEL_6G_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__FC_HB_LOGEN_DIV_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__FC_HB_LOGEN_DIV_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__VCON_SW_LEG___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__VCON_SW_LEG___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__VCON_SW_OPT___M 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__VCON_SW_OPT___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__SEL_6G_OVS___M 0x18000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__SEL_6G_OVS___S 27 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__FC_HB_LOGEN_DIV_OV___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__FC_HB_LOGEN_DIV_OV___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__FC_HB_LOGEN_DIV_OVD___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8__FC_HB_LOGEN_DIV_OVD___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_PC_WL_SYNTH_LP2G_PC8___S 23 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0 (0x005D6180) +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0___POR 0xAF682022 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__KVCO_0___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__IBIAS_0___POR 0x0F +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__LDO_VCO_VREG_0___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__VCO_CMTUNE_0___POR 0x20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__VCO_CMTUNEB_0___POR 0x20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__LOGEN_CAP_0___POR 0x22 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__KVCO_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__KVCO_0___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__IBIAS_0___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__IBIAS_0___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__LDO_VCO_VREG_0___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__LDO_VCO_VREG_0___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__VCO_CMTUNE_0___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__VCO_CMTUNE_0___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__VCO_CMTUNEB_0___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__VCO_CMTUNEB_0___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__LOGEN_CAP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0__LOGEN_CAP_0___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_0___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1 (0x005D6184) +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1___POR 0x8F669A44 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__KVCO_1___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__IBIAS_1___POR 0x0F +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__LDO_VCO_VREG_1___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__VCO_CMTUNE_1___POR 0x1A +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__VCO_CMTUNEB_1___POR 0x1A +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__LOGEN_CAP_1___POR 0x44 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__KVCO_1___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__KVCO_1___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__IBIAS_1___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__IBIAS_1___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__LDO_VCO_VREG_1___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__LDO_VCO_VREG_1___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__VCO_CMTUNE_1___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__VCO_CMTUNE_1___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__VCO_CMTUNEB_1___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__VCO_CMTUNEB_1___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__LOGEN_CAP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1__LOGEN_CAP_1___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2 (0x005D6188) +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2___POR 0x6F859677 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__KVCO_2___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__IBIAS_2___POR 0x0F +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__LDO_VCO_VREG_2___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__VCO_CMTUNE_2___POR 0x16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__VCO_CMTUNEB_2___POR 0x16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__LOGEN_CAP_2___POR 0x77 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__KVCO_2___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__KVCO_2___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__IBIAS_2___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__IBIAS_2___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__LDO_VCO_VREG_2___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__LDO_VCO_VREG_2___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__VCO_CMTUNE_2___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__VCO_CMTUNE_2___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__VCO_CMTUNEB_2___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__VCO_CMTUNEB_2___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__LOGEN_CAP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2__LOGEN_CAP_2___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_2___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3 (0x005D618C) +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3___POR 0x6F851499 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__KVCO_3___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__IBIAS_3___POR 0x0F +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__LDO_VCO_VREG_3___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__VCO_CMTUNE_3___POR 0x14 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__VCO_CMTUNEB_3___POR 0x14 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__LOGEN_CAP_3___POR 0x99 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__KVCO_3___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__KVCO_3___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__IBIAS_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__IBIAS_3___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__LDO_VCO_VREG_3___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__LDO_VCO_VREG_3___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__VCO_CMTUNE_3___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__VCO_CMTUNE_3___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__VCO_CMTUNEB_3___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__VCO_CMTUNEB_3___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__LOGEN_CAP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3__LOGEN_CAP_3___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_3___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4 (0x005D6190) +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4___POR 0xAF6820AA +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__KVCO_4___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__IBIAS_4___POR 0x0F +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__LDO_VCO_VREG_4___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__VCO_CMTUNE_4___POR 0x20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__VCO_CMTUNEB_4___POR 0x20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__LOGEN_CAP_4___POR 0xAA +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__KVCO_4___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__KVCO_4___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__IBIAS_4___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__IBIAS_4___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__LDO_VCO_VREG_4___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__LDO_VCO_VREG_4___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__VCO_CMTUNE_4___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__VCO_CMTUNE_4___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__VCO_CMTUNEB_4___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__VCO_CMTUNEB_4___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__LOGEN_CAP_4___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4__LOGEN_CAP_4___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_4___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5 (0x005D6194) +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5___POR 0x8F669ADD +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__KVCO_5___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__IBIAS_5___POR 0x0F +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__LDO_VCO_VREG_5___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__VCO_CMTUNE_5___POR 0x1A +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__VCO_CMTUNEB_5___POR 0x1A +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__LOGEN_CAP_5___POR 0xDD +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__KVCO_5___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__KVCO_5___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__IBIAS_5___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__IBIAS_5___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__LDO_VCO_VREG_5___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__LDO_VCO_VREG_5___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__VCO_CMTUNE_5___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__VCO_CMTUNE_5___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__VCO_CMTUNEB_5___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__VCO_CMTUNEB_5___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__LOGEN_CAP_5___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5__LOGEN_CAP_5___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_5___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6 (0x005D6198) +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6___POR 0x6F8596EE +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__KVCO_6___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__IBIAS_6___POR 0x0F +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__LDO_VCO_VREG_6___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__VCO_CMTUNE_6___POR 0x16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__VCO_CMTUNEB_6___POR 0x16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__LOGEN_CAP_6___POR 0xEE +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__KVCO_6___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__KVCO_6___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__IBIAS_6___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__IBIAS_6___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__LDO_VCO_VREG_6___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__LDO_VCO_VREG_6___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__VCO_CMTUNE_6___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__VCO_CMTUNE_6___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__VCO_CMTUNEB_6___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__VCO_CMTUNEB_6___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__LOGEN_CAP_6___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6__LOGEN_CAP_6___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_6___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7 (0x005D619C) +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7___POR 0x6F8514FF +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__KVCO_7___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__IBIAS_7___POR 0x0F +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__LDO_VCO_VREG_7___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__VCO_CMTUNE_7___POR 0x14 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__VCO_CMTUNEB_7___POR 0x14 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__LOGEN_CAP_7___POR 0xFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__KVCO_7___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__KVCO_7___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__IBIAS_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__IBIAS_7___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__LDO_VCO_VREG_7___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__LDO_VCO_VREG_7___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__VCO_CMTUNE_7___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__VCO_CMTUNE_7___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__VCO_CMTUNEB_7___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__VCO_CMTUNEB_7___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__LOGEN_CAP_7___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7__LOGEN_CAP_7___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCOMUX_7___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0 (0x005D61A8) +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0___POR 0x10120F00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0__KVCO_TH0___POR 0x020 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0__KVCO_TH1___POR 0x048 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0__KVCO_TH2___POR 0x078 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0__KVCO_TH0___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0__KVCO_TH0___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0__KVCO_TH1___M 0x007FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0__KVCO_TH1___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0__KVCO_TH2___M 0x00003FE0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0__KVCO_TH2___S 5 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0___M 0xFFFFFFE0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO0___S 5 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1 (0x005D61AC) +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1___POR 0x5C3EE7A0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1__KVCO_TH3___POR 0x0B8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1__KVCO_TH4___POR 0x0FB +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1__KVCO_TH5___POR 0x13D +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1__KVCO_TH3___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1__KVCO_TH3___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1__KVCO_TH4___M 0x007FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1__KVCO_TH4___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1__KVCO_TH5___M 0x00003FE0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1__KVCO_TH5___S 5 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1___M 0xFFFFFFE0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO1___S 5 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2 (0x005D61B0) +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2___POR 0xBE800000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_TH6___POR 0x17D +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_SEL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_GATE_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__HB_GATE_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__DTIM_GATE_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_TH6___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_TH6___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_SEL_OV___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_SEL_OV___S 7 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_SEL_OVD___M 0x00000070 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_SEL_OVD___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_GATE_DIS___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__KVCO_GATE_DIS___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__HB_GATE_DIS___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__HB_GATE_DIS___S 2 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__DTIM_GATE_DIS___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2__DTIM_GATE_DIS___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2___M 0xFF8000FE +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_WL_SYNTH_LP2G_KVCO2___S 1 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3 (0x005D61B4) +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_KVCO___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_IBIAS___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_LDO_VCO_VREG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_VCO_CMTUNE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_VCO_CMTUNEB___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_LOGEN_CAP___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_KVCO___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_KVCO___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_IBIAS___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_IBIAS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_LDO_VCO_VREG___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_LDO_VCO_VREG___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_VCO_CMTUNE___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_VCO_CMTUNE___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_VCO_CMTUNEB___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_VCO_CMTUNEB___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_LOGEN_CAP___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3__RO_LOGEN_CAP___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO3___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4 (0x005D61B8) +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_KVCO_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_KVCO_6G___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_VCO_CMTUNE_6G___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_VCO_CMTUNEB_6G___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_KVCO_SEL___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_KVCO_SEL___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_KVCO_6G___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_KVCO_6G___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_VCO_CMTUNE_6G___M 0x03F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_VCO_CMTUNE_6G___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_VCO_CMTUNEB_6G___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4__RO_VCO_CMTUNEB_6G___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4___M 0xFFFFC000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_KVCO_RO_WL_SYNTH_LP2G_KVCO4___S 14 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0 (0x005D61C0) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0___POR 0x00068000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_CP_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_VCO_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_PFD_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_FBDIV_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_LOGEN_VREF___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_LOGEN_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_LOGEN_LEAK___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_CP_LOW_BIAS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_PINVC___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_PFD_C_FILT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_FBDIV_C_FILT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_CP_BYPASS___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_CP_BYPASS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_VCO_BYPASS___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_VCO_BYPASS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_PFD_BYPASS___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_PFD_BYPASS___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_FBDIV_BYPASS___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_FBDIV_BYPASS___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_LOGEN_VREF___M 0x000E0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_LOGEN_VREF___S 17 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_LOGEN_BYPASS___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_LOGEN_BYPASS___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_LOGEN_LEAK___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_LOGEN_LEAK___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_CP_LOW_BIAS___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_CP_LOW_BIAS___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_PINVC___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_PINVC___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_PFD_C_FILT___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_PFD_C_FILT___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_FBDIV_C_FILT___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0__D_LDO_FBDIV_C_FILT___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0___M 0x11CFF800 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC0___S 11 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1 (0x005D61C4) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1___POR 0x0000301B +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1__D_CP_ISEL_IR25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1__D_SPARE_ISEL_IR25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1__D_SPARE_ISEL_IC25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1__D_CP_ISEL_IR25___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1__D_CP_ISEL_IR25___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1__D_SPARE_ISEL_IR25___M 0x00000038 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1__D_SPARE_ISEL_IR25___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1__D_SPARE_ISEL_IC25___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1__D_SPARE_ISEL_IC25___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1___M 0x0000703F +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2 (0x005D61C8) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2___POR 0x6D860000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_LDO_PFD_ISEL_IC25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_LDO_CP_ISEL_IC25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_VCMON_ISEL_IC25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_LDO_FBDIV_ISEL_IC25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_SEL_IC_IPT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_LDO_PFD_ISEL_IC25___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_LDO_PFD_ISEL_IC25___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_LDO_CP_ISEL_IC25___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_LDO_CP_ISEL_IC25___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_VCMON_ISEL_IC25___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_VCMON_ISEL_IC25___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_LDO_FBDIV_ISEL_IC25___M 0x000E0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_LDO_FBDIV_ISEL_IC25___S 17 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_SEL_IC_IPT___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2__D_SEL_IC_IPT___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2___M 0xFF8E0002 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC2___S 1 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3 (0x005D61CC) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3___POR 0x00300001 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_LB_LOBUF_DRVSTR___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_HB_LOGEN_NOTAIL_AMP_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_VCO_ISRC_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_PFD_HI_LK_MODE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_LB_LOBUF_DRVSTR___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_LB_LOBUF_DRVSTR___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_HB_LOGEN_NOTAIL_AMP_EN___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_HB_LOGEN_NOTAIL_AMP_EN___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_VCO_ISRC_BYPASS___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_VCO_ISRC_BYPASS___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_PFD_HI_LK_MODE___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3__D_PFD_HI_LK_MODE___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3___M 0x00308003 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC3___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4 (0x005D61D0) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__D_HB_VCO_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__SYN_ATB_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__D_VCO_TST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__D_HB_VARAC_BIAS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__D_HB_VCO_ATB_SEL___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__D_HB_VCO_ATB_SEL___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__SYN_ATB_SEL___M 0x03E00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__SYN_ATB_SEL___S 21 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__D_VCO_TST_EN___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__D_VCO_TST_EN___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__D_HB_VARAC_BIAS___M 0x000E0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4__D_HB_VARAC_BIAS___S 17 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4___M 0xE3FE0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC4___S 17 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC5 (0x005D61D4) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC5__D_SYN_SPARE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC5__D_SYN_SPARE_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC5__D_SYN_SPARE_0___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC5___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC5___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC6 (0x005D61D8) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC6__D_SYN_SPARE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC6__D_SYN_SPARE_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC6__D_SYN_SPARE_1___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC6___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC6___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7 (0x005D61DC) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7___POR 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__CLBS_LPF_VREF_ADJ_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_LO_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_LO_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_HI_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_HI_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__CLBS_LPF_VREF_ADJ_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__CLBS_LPF_VREF_ADJ_EN___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_LO_OV___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_LO_OV___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_LO_OVD___M 0x3C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_LO_OVD___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_HI_OV___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_HI_OV___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_HI_OVD___M 0x01E00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7__LPF_VREF_HI_OVD___S 21 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC7___S 21 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0 (0x005D61E0) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_RFCNT_SEL_BSC___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_PFDCP_CPI___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_CP_LEAKER___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_C2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_C3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_R1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_R2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_VREF_LO___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_VREF_HI___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_RFCNT_SEL_BSC___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_RFCNT_SEL_BSC___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_PFDCP_CPI___M 0x1F800000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_PFDCP_CPI___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_CP_LEAKER___M 0x00780000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_CP_LEAKER___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_C2___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_C2___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_C3___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_C3___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_R1___M 0x00003800 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_R1___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_R2___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_R2___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_VREF_LO___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_VREF_LO___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_VREF_HI___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0__RO_LPF_VREF_HI___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC0___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC1 (0x005D61E4) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC1__RO_LPF_R2_6G___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC1__RO_BAND___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC1__RO_LPF_R2_6G___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC1__RO_LPF_R2_6G___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC1__RO_BAND___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC1__RO_BAND___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC1___M 0xE0000003 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_RO_WL_SYNTH_LP2G_AC1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8 (0x005D61E8) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8___POR 0x1CA2B95C +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_VCOBUF_VREG___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_VCO_OTACUR___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_VCOBUF_OTACUR___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_CP_VREG___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_PFD_SEL___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_PFD_VREG___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_PFD_OTACUR___POR 0xC +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_FBDIV_SEL___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_FBDIV_VREG___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_FBDIV_OTACUR___POR 0xC +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_VCOBUF_VREG___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_VCOBUF_VREG___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_VCO_OTACUR___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_VCO_OTACUR___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_VCOBUF_OTACUR___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_VCOBUF_OTACUR___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_CP_VREG___M 0x003C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_CP_VREG___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_PFD_SEL___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_PFD_SEL___S 17 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_PFD_VREG___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_PFD_VREG___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_PFD_OTACUR___M 0x00001E00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_PFD_OTACUR___S 9 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_FBDIV_SEL___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_FBDIV_SEL___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_FBDIV_VREG___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_FBDIV_VREG___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_FBDIV_OTACUR___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8__D_LDO_FBDIV_OTACUR___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC8___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9 (0x005D61EC) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9___POR 0x1C7C6000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_PFD_LKRON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_FBDIV_LKRON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_LOGEN_VREG___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_LOGEN_LKRON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_LOGEN_OTACUR___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_PFD_CAPSEL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_FBDIV_CAPSEL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_VCOBUF_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_PFD_MERGE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_VCO_ISEL_IC25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_CPLVL_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LOBIAS_BWRSEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_PFD_LKRON___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_PFD_LKRON___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_FBDIV_LKRON___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_FBDIV_LKRON___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_LOGEN_VREG___M 0x3C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_LOGEN_VREG___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_LOGEN_LKRON___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_LOGEN_LKRON___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_LOGEN_OTACUR___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_LOGEN_OTACUR___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_PFD_CAPSEL___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_PFD_CAPSEL___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_FBDIV_CAPSEL___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_FBDIV_CAPSEL___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_VCOBUF_BYPASS___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_VCOBUF_BYPASS___S 17 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_PFD_MERGE___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_PFD_MERGE___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_VCO_ISEL_IC25___M 0x0000E000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_VCO_ISEL_IC25___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_CPLVL_BYPASS___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LDO_CPLVL_BYPASS___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LOBIAS_BWRSEL___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9__D_LOBIAS_BWRSEL___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC9___S 10 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10 (0x005D61F0) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10___POR 0x2210000F +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_DEGEN_PROG___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_LKR_DEGEN_PROG___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_VCO_DUALCORE_6G___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_SUPFILT_RES___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_NBIAS_RSEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_PBIAS_RSEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_LDO_MERGE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_LPF_C1___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_VCO_DUALCORE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_DEGEN_PROG___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_DEGEN_PROG___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_LKR_DEGEN_PROG___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_LKR_DEGEN_PROG___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_VCO_DUALCORE_6G___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_VCO_DUALCORE_6G___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_SUPFILT_RES___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_SUPFILT_RES___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_NBIAS_RSEL___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_NBIAS_RSEL___S 17 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_PBIAS_RSEL___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_PBIAS_RSEL___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_LDO_MERGE___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_CP_LDO_MERGE___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_LPF_C1___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_LPF_C1___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_VCO_DUALCORE___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10__D_VCO_DUALCORE___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10___M 0xFF1F800F +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC10___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11 (0x005D61F4) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11___POR 0x03000018 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_HB_LOAMP_CUR___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LOBUF_DRV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_VREF_FILT_RES___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_BIAS_FILT_RES___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LB_VCO_VRES09___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LB_VCO_VRES07___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_CP_DRAINSW_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LB_VCOBUF_DUMLOAD_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_HB_LOGEN_DIV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_HB_LOAMP_CUR___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_HB_LOAMP_CUR___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LOBUF_DRV___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LOBUF_DRV___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_VREF_FILT_RES___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_VREF_FILT_RES___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_BIAS_FILT_RES___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_BIAS_FILT_RES___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LB_VCO_VRES09___M 0x00078000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LB_VCO_VRES09___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LB_VCO_VRES07___M 0x00007800 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LB_VCO_VRES07___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_CP_DRAINSW_EN___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_CP_DRAINSW_EN___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LB_VCOBUF_DUMLOAD_EN___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_LB_VCOBUF_DUMLOAD_EN___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_HB_LOGEN_DIV___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11__D_HB_LOGEN_DIV___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11___M 0x0FFFF81F +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC11___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12 (0x005D61F8) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12___POR 0x007FF7FF +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANK_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANK_OVD___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANKA_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANKA_OVD___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANK_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANK_OV___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANK_OVD___M 0x007FF000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANK_OVD___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANKA_OV___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANKA_OV___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANKA_OVD___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12__BANKA_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC12___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13 (0x005D61FC) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13___POR 0x007FF7FF +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANK_6G_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANK_6G_OVD___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANKA_6G_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANKA_6G_OVD___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANK_6G_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANK_6G_OV___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANK_6G_OVD___M 0x007FF000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANK_6G_OVD___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANKA_6G_OV___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANKA_6G_OV___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANKA_6G_OVD___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13__BANKA_6G_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_AC13___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0 (0x005D6240) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0___POR 0x091B0C00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__RFCNT_SEL_BSC_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__PFDCP_CPI_0___POR 0x12 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__CP_LEAKER_0___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_C2_0___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_C3_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_R1_0___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_R2_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__RFCNT_SEL_BSC_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__RFCNT_SEL_BSC_0___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__PFDCP_CPI_0___M 0x1F800000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__PFDCP_CPI_0___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__CP_LEAKER_0___M 0x00780000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__CP_LEAKER_0___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_C2_0___M 0x00078000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_C2_0___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_C3_0___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_C3_0___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_R1_0___M 0x00001E00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_R1_0___S 9 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_R2_0___M 0x000001C0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0__LPF_R2_0___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0___M 0xFFFFFFC0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_0___S 6 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0 (0x005D6244) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0___POR 0x67850000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_LO_0___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_HI_0___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_LO_CLBS_0___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_HI_CLBS_0___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_LO_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_LO_0___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_HI_0___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_HI_0___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_LO_CLBS_0___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_LO_CLBS_0___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_HI_CLBS_0___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0__LPF_VREF_HI_CLBS_0___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_0___S 16 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1 (0x005D6248) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1___POR 0x212B8640 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__RFCNT_SEL_BSC_1___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__PFDCP_CPI_1___POR 0x02 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__CP_LEAKER_1___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_C2_1___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_C3_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_R1_1___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_R2_1___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__RFCNT_SEL_BSC_1___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__RFCNT_SEL_BSC_1___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__PFDCP_CPI_1___M 0x1F800000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__PFDCP_CPI_1___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__CP_LEAKER_1___M 0x00780000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__CP_LEAKER_1___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_C2_1___M 0x00078000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_C2_1___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_C3_1___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_C3_1___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_R1_1___M 0x00001E00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_R1_1___S 9 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_R2_1___M 0x000001C0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1__LPF_R2_1___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1___M 0xFFFFFFC0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_1___S 6 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1 (0x005D624C) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1___POR 0x38410000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_LO_1___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_HI_1___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_LO_CLBS_1___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_HI_CLBS_1___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_LO_1___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_LO_1___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_HI_1___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_HI_1___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_LO_CLBS_1___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_LO_CLBS_1___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_HI_CLBS_1___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1__LPF_VREF_HI_CLBS_1___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_1___S 16 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2 (0x005D6250) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2___POR 0x091B0C40 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__RFCNT_SEL_BSC_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__PFDCP_CPI_2___POR 0x12 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__CP_LEAKER_2___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_C2_2___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_C3_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_R1_2___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_R2_2___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__RFCNT_SEL_BSC_2___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__RFCNT_SEL_BSC_2___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__PFDCP_CPI_2___M 0x1F800000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__PFDCP_CPI_2___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__CP_LEAKER_2___M 0x00780000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__CP_LEAKER_2___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_C2_2___M 0x00078000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_C2_2___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_C3_2___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_C3_2___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_R1_2___M 0x00001E00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_R1_2___S 9 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_R2_2___M 0x000001C0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2__LPF_R2_2___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2___M 0xFFFFFFC0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_2___S 6 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2 (0x005D6254) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2___POR 0x67850000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_LO_2___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_HI_2___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_LO_CLBS_2___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_HI_CLBS_2___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_LO_2___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_LO_2___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_HI_2___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_HI_2___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_LO_CLBS_2___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_LO_CLBS_2___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_HI_CLBS_2___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2__LPF_VREF_HI_CLBS_2___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_2___S 16 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3 (0x005D6258) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3___POR 0x212B8640 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__RFCNT_SEL_BSC_3___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__PFDCP_CPI_3___POR 0x02 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__CP_LEAKER_3___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_C2_3___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_C3_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_R1_3___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_R2_3___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__RFCNT_SEL_BSC_3___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__RFCNT_SEL_BSC_3___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__PFDCP_CPI_3___M 0x1F800000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__PFDCP_CPI_3___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__CP_LEAKER_3___M 0x00780000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__CP_LEAKER_3___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_C2_3___M 0x00078000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_C2_3___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_C3_3___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_C3_3___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_R1_3___M 0x00001E00 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_R1_3___S 9 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_R2_3___M 0x000001C0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3__LPF_R2_3___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3___M 0xFFFFFFC0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX_3___S 6 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3 (0x005D625C) +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3___POR 0x38410000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_LO_3___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_HI_3___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_LO_CLBS_3___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_HI_CLBS_3___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_LO_3___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_LO_3___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_HI_3___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_HI_3___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_LO_CLBS_3___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_LO_CLBS_3___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_HI_CLBS_3___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3__LPF_VREF_HI_CLBS_3___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_AC_WL_SYNTH_LP2G_BANDMUX1_3___S 16 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL (0x005D6280) +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL___POR 0x10000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_REFBUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_REFDIV_EN_OVS___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_FLAG_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_FLAG_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_FLAG_RESET_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PSYNC_START___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PCAL_START___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_REFBUF_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_REFBUF_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_REFDIV_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_REFDIV_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_FLAG_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_FLAG_OV___S 27 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_FLAG_OVD___M 0x06000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_FLAG_OVD___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_FLAG_RESET_OVS___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PAL_FLAG_RESET_OVS___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PSYNC_START___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PSYNC_START___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PCAL_START___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL__PCAL_START___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL___M 0xFF800003 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_WL_SYNTH_LP2G_PAL___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_RO_WL_SYNTH_LP2G_LO (0x005D6288) +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_RO_WL_SYNTH_LP2G_LO___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_RO_WL_SYNTH_LP2G_LO___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_RO_WL_SYNTH_LP2G_LO__RO_LO_FREQ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_RO_WL_SYNTH_LP2G_LO__RO_LO_FREQ___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_RO_WL_SYNTH_LP2G_LO__RO_LO_FREQ___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_RO_WL_SYNTH_LP2G_LO___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_SYNTH0_LO_RO_WL_SYNTH_LP2G_LO___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH0 (0x005D6800) +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH0___POR 0x0221D532 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH0__NBNA___POR 0x004 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH0__NF___POR 0x21D532 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH0__NBNA___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH0__NBNA___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH0__NF___M 0x007FFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH0__NF___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH0___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH1 (0x005D6804) +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH1__SD_NF_OFFSET___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH1__BSTARGET_OFS_COARSE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH1__BSTARGET_OFS_FINE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH1__BS_COARSE_FINE_BDRY___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH1__SD_NF_OFFSET___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH1__SD_NF_OFFSET___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH1__BSTARGET_OFS_COARSE___M 0x0000FC00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH1__BSTARGET_OFS_COARSE___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH1__BSTARGET_OFS_FINE___M 0x000003F0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH1__BSTARGET_OFS_FINE___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH1__BS_COARSE_FINE_BDRY___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH1__BS_COARSE_FINE_BDRY___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2 (0x005D6808) +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2___POR 0x0042AAAA +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2__FC_DELTA_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2__FC_BASE_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2__FC_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2__FC_START___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2__FC_DELTA___POR 0x42AAAA +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2__FC_DELTA_SEL___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2__FC_DELTA_SEL___S 27 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2__FC_BASE_SEL___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2__FC_BASE_SEL___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2__FC_DIS___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2__FC_DIS___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2__FC_START___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2__FC_START___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2__FC_DELTA___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2__FC_DELTA___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2___M 0x0FFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH2___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH3 (0x005D680C) +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH3___POR 0x55000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH3__FC_DELTA_SUB___POR 0x0AA +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH3__FC_DELTA_SUB___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH3__FC_DELTA_SUB___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH3___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_CH3___S 23 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0 (0x005D6810) +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0___POR 0x116C2599 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BSSTART___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BSMODE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BKSHFT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BSSETT___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BSWAIT___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BSSAMPLE___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__LPF_VTUNEMON_TMR___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BS_RFCNT_OUT_TIME___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__RFCNTEN_DLY_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BS_VMID_NON_HB___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BS_VMID_HB___POR 0x9 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BS_CLBS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__NF0B___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__D_DTIM_FBDIV4_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__DISABLE_LPF_TMR___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BSSTART___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BSSTART___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BSMODE___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BSMODE___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BKSHFT___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BKSHFT___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BSSETT___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BSSETT___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BSWAIT___M 0x00E00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BSWAIT___S 21 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BSSAMPLE___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BSSAMPLE___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__LPF_VTUNEMON_TMR___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__LPF_VTUNEMON_TMR___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BS_RFCNT_OUT_TIME___M 0x0000E000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BS_RFCNT_OUT_TIME___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__RFCNTEN_DLY_DIS___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__RFCNTEN_DLY_DIS___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BS_VMID_NON_HB___M 0x00000F00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BS_VMID_NON_HB___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BS_VMID_HB___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BS_VMID_HB___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BS_CLBS_EN___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__BS_CLBS_EN___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__NF0B___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__NF0B___S 2 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__D_DTIM_FBDIV4_SEL___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__D_DTIM_FBDIV4_SEL___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__DISABLE_LPF_TMR___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0__DISABLE_LPF_TMR___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS0___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1 (0x005D6814) +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1___POR 0x80680000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__SDM_SEL___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__SDMOGAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__BSTESTEN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__SDTESTEN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__SD_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__D_PLLMD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__BS_OVCAL_BDRY___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__PLL_SLIP_DET_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__RESTORE_BS_CLBS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__DTEST2_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__DTEST1_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__DTEST0_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__SDM_SEL___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__SDM_SEL___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__SDMOGAIN___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__SDMOGAIN___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__BSTESTEN___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__BSTESTEN___S 27 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__SDTESTEN___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__SDTESTEN___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__SD_RESET___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__SD_RESET___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__D_PLLMD___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__D_PLLMD___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__BS_OVCAL_BDRY___M 0x00E00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__BS_OVCAL_BDRY___S 21 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__PLL_SLIP_DET_RESET___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__PLL_SLIP_DET_RESET___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__RESTORE_BS_CLBS_EN___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__RESTORE_BS_CLBS_EN___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__DTEST2_SEL___M 0x00007C00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__DTEST2_SEL___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__DTEST1_SEL___M 0x000003E0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__DTEST1_SEL___S 5 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__DTEST0_SEL___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1__DTEST0_SEL___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1___M 0xFFF87FFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS2 (0x005D6818) +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS2___POR 0x04000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS2__IVCOBK___POR 0x400 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS2__TSTCNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS2__IVCOBK___M 0x07FF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS2__IVCOBK___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS2__TSTCNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS2__TSTCNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS2___M 0x07FFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_WL_SYNTH_2G5G_BS2___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS0 (0x005D681C) +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS0__RO_BSTARGET___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS0__RO_BSCOUNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS0__RO_BSTARGET___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS0__RO_BSTARGET___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS0__RO_BSCOUNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS0__RO_BSCOUNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS0___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1 (0x005D6820) +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BSDELTA_B3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BSDELTA_B2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BSDELTA_B1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BSDELTA_B0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_VC_2HI___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_VC_2LO___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BIST_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BSON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_FVCOBK___POR 0x000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BSDELTA_B3___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BSDELTA_B3___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BSDELTA_B2___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BSDELTA_B2___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BSDELTA_B1___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BSDELTA_B1___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BSDELTA_B0___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BSDELTA_B0___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_VC_2HI___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_VC_2HI___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_VC_2LO___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_VC_2LO___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BIST_ON___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BIST_ON___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BSON___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_BSON___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_FVCOBK___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1__RO_FVCOBK___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1___M 0xFFFF7FFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2 (0x005D6824) +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_SYN_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_SYN_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_SYN_EN_REC_LO___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_ANY_RX_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_ANY_TX_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_CLBS_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_TX_MASK___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_VC_2HI_AT_VTUNEMON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_VC_2LO_AT_VTUNEMON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_VC_2HI_AFTER_VTUNEMON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_VC_2LO_AFTER_VTUNEMON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_PLL_LOCK_DET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_PLL_LOCK___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_DLL_LOCKED___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_NON_DTIM_5G___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_BS_VMID___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_CHAN_IDX___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_SYN_MODE___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_SYN_MODE___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_SYN_EN___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_SYN_EN___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_SYN_EN_REC_LO___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_SYN_EN_REC_LO___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_ANY_RX_EN___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_ANY_RX_EN___S 27 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_ANY_TX_EN___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_ANY_TX_EN___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_CLBS_ON___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_CLBS_ON___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_TX_MASK___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_TX_MASK___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_VC_2HI_AT_VTUNEMON___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_VC_2HI_AT_VTUNEMON___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_VC_2LO_AT_VTUNEMON___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_VC_2LO_AT_VTUNEMON___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_VC_2HI_AFTER_VTUNEMON___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_VC_2HI_AFTER_VTUNEMON___S 17 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_VC_2LO_AFTER_VTUNEMON___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_VC_2LO_AFTER_VTUNEMON___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_PLL_LOCK_DET___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_PLL_LOCK_DET___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_PLL_LOCK___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_PLL_LOCK___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_DLL_LOCKED___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_DLL_LOCKED___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_NON_DTIM_5G___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_NON_DTIM_5G___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_BS_VMID___M 0x00000F00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_BS_VMID___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_CHAN_IDX___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2__RO_CHAN_IDX___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2___M 0xFF0FFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS2___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS3 (0x005D6828) +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS3__RO_NBNA___POR 0x000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS3__RO_NBNA___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS3__RO_NBNA___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS3___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS3___S 23 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS4 (0x005D682C) +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS4___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS4__RO_NF___POR 0x000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS4__RO_NF___M 0x007FFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS4__RO_NF___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS4___M 0x007FFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS4___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS5 (0x005D6830) +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS5___POR 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS5__CLBS_QS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS5__CLBS_QS_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS5__CLBS_QS_EN___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS5___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS5___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS6 (0x005D6834) +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS6__BANK_DBG_OFFSET___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS6__RO_INIT_BANK___POR 0x000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS6__BANK_DBG_OFFSET___M 0x0001F800 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS6__BANK_DBG_OFFSET___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS6__RO_INIT_BANK___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS6__RO_INIT_BANK___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS6___M 0x0001FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BS_RO_WL_SYNTH_2G5G_BS6___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0 (0x005D6840) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0___POR 0x44A43E4A +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_START___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_ENABLE_VC___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_ENABLE_TX___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_ENABLE_RX___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_MODE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_COMP_REPEAT___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_SMPL_RATE___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_MAX_STEP___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_STEPSIZE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_HYBRID_BDRY___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_SETTIME___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_SAMPLE___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_MASK_SEL___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_PSYNC_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_START___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_START___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_ENABLE_VC___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_ENABLE_VC___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_ENABLE_TX___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_ENABLE_TX___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_ENABLE_RX___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_ENABLE_RX___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_MODE___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_MODE___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_COMP_REPEAT___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_COMP_REPEAT___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_SMPL_RATE___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_SMPL_RATE___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_MAX_STEP___M 0x00078000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_MAX_STEP___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_STEPSIZE___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_STEPSIZE___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_HYBRID_BDRY___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_HYBRID_BDRY___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_SETTIME___M 0x00000380 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_SETTIME___S 7 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_SAMPLE___M 0x00000070 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_SAMPLE___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_MASK_SEL___M 0x0000000C +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_MASK_SEL___S 2 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_PSYNC_EN___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0__CLBS_PSYNC_EN___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0___M 0xFCFFFFFE +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS0___S 1 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1 (0x005D6844) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1___POR 0xB4208000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1__CLBS_OVSKIP_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1__CLBS_OVSKIP_BDRY___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1__CLBS_OVSKIP_INC___POR 0x08 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1__CLBS_OVSKIP_DEC___POR 0x08 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1__CLBS_SAMPLE_RESTORE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1__CLBS_OVSKIP_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1__CLBS_OVSKIP_EN___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1__CLBS_OVSKIP_BDRY___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1__CLBS_OVSKIP_BDRY___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1__CLBS_OVSKIP_INC___M 0x0F800000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1__CLBS_OVSKIP_INC___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1__CLBS_OVSKIP_DEC___M 0x007C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1__CLBS_OVSKIP_DEC___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1__CLBS_SAMPLE_RESTORE___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1__CLBS_SAMPLE_RESTORE___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1___M 0xFFFF8000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS1___S 15 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_RO_WL_SYNTH_2G5G_CLBS (0x005D6848) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_RO_WL_SYNTH_2G5G_CLBS___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_RO_WL_SYNTH_2G5G_CLBS___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_RO_WL_SYNTH_2G5G_CLBS__RO_CLBS_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_RO_WL_SYNTH_2G5G_CLBS__RO_NON_DTIM_5G___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_RO_WL_SYNTH_2G5G_CLBS__RO_CLBS_OFF_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_RO_WL_SYNTH_2G5G_CLBS__RO_CLBS_MODE___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_RO_WL_SYNTH_2G5G_CLBS__RO_CLBS_MODE___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_RO_WL_SYNTH_2G5G_CLBS__RO_NON_DTIM_5G___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_RO_WL_SYNTH_2G5G_CLBS__RO_NON_DTIM_5G___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_RO_WL_SYNTH_2G5G_CLBS__RO_CLBS_OFF_SEL___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_RO_WL_SYNTH_2G5G_CLBS__RO_CLBS_OFF_SEL___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_RO_WL_SYNTH_2G5G_CLBS___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_RO_WL_SYNTH_2G5G_CLBS___S 24 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS2 (0x005D684C) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS2__CLBS_OFF_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS2__CLBS_OFF_SEL_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS2__CLBS_LIN_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS2__CLBS_OFF_SEL_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS2__CLBS_OFF_SEL_OV___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS2__CLBS_OFF_SEL_OVD___M 0x7C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS2__CLBS_OFF_SEL_OVD___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS2__CLBS_LIN_EN___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS2__CLBS_LIN_EN___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS2___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS2___S 25 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_0 (0x005D6850) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_0___POR 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_0__CLBS_LIN_OFFSET_0___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_0__CLBS_LIN_OFFSET_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_0__CLBS_LIN_OFFSET_0___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_0___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_1 (0x005D6854) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_1___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_1__CLBS_LIN_OFFSET_1___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_1__CLBS_LIN_OFFSET_1___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_1__CLBS_LIN_OFFSET_1___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_1___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_1___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_2 (0x005D6858) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_2___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_2__CLBS_LIN_OFFSET_2___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_2__CLBS_LIN_OFFSET_2___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_2__CLBS_LIN_OFFSET_2___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_2___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_2___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_3 (0x005D685C) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_3___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_3__CLBS_LIN_OFFSET_3___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_3__CLBS_LIN_OFFSET_3___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_3__CLBS_LIN_OFFSET_3___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_3___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_3___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_4 (0x005D6860) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_4___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_4__CLBS_LIN_OFFSET_4___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_4__CLBS_LIN_OFFSET_4___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_4__CLBS_LIN_OFFSET_4___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_4___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_4___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_5 (0x005D6864) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_5___POR 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_5__CLBS_LIN_OFFSET_5___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_5__CLBS_LIN_OFFSET_5___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_5__CLBS_LIN_OFFSET_5___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_5___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_5___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_6 (0x005D6868) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_6___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_6__CLBS_LIN_OFFSET_6___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_6__CLBS_LIN_OFFSET_6___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_6__CLBS_LIN_OFFSET_6___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_6___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_6___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_7 (0x005D686C) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_7___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_7__CLBS_LIN_OFFSET_7___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_7__CLBS_LIN_OFFSET_7___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_7__CLBS_LIN_OFFSET_7___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_7___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_7___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_8 (0x005D6870) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_8___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_8__CLBS_LIN_OFFSET_8___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_8__CLBS_LIN_OFFSET_8___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_8__CLBS_LIN_OFFSET_8___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_8___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_8___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_9 (0x005D6874) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_9___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_9__CLBS_LIN_OFFSET_9___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_9__CLBS_LIN_OFFSET_9___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_9__CLBS_LIN_OFFSET_9___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_9___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_9___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_10 (0x005D6878) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_10___POR 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_10__CLBS_LIN_OFFSET_10___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_10__CLBS_LIN_OFFSET_10___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_10__CLBS_LIN_OFFSET_10___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_10___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_10___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_11 (0x005D687C) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_11___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_11__CLBS_LIN_OFFSET_11___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_11__CLBS_LIN_OFFSET_11___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_11__CLBS_LIN_OFFSET_11___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_11___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_11___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_12 (0x005D6880) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_12___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_12__CLBS_LIN_OFFSET_12___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_12__CLBS_LIN_OFFSET_12___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_12__CLBS_LIN_OFFSET_12___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_12___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_12___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_13 (0x005D6884) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_13___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_13__CLBS_LIN_OFFSET_13___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_13__CLBS_LIN_OFFSET_13___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_13__CLBS_LIN_OFFSET_13___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_13___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_13___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_14 (0x005D6888) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_14___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_14__CLBS_LIN_OFFSET_14___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_14__CLBS_LIN_OFFSET_14___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_14__CLBS_LIN_OFFSET_14___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_14___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_14___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_15 (0x005D688C) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_15___POR 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_15__CLBS_LIN_OFFSET_15___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_15__CLBS_LIN_OFFSET_15___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_15__CLBS_LIN_OFFSET_15___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_15___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_15___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_16 (0x005D6890) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_16___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_16__CLBS_LIN_OFFSET_16___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_16__CLBS_LIN_OFFSET_16___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_16__CLBS_LIN_OFFSET_16___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_16___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_16___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_17 (0x005D6894) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_17___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_17__CLBS_LIN_OFFSET_17___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_17__CLBS_LIN_OFFSET_17___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_17__CLBS_LIN_OFFSET_17___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_17___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_17___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_18 (0x005D6898) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_18___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_18__CLBS_LIN_OFFSET_18___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_18__CLBS_LIN_OFFSET_18___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_18__CLBS_LIN_OFFSET_18___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_18___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_18___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_19 (0x005D689C) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_19___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_19__CLBS_LIN_OFFSET_19___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_19__CLBS_LIN_OFFSET_19___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_19__CLBS_LIN_OFFSET_19___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_19___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_19___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_20 (0x005D68A0) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_20___POR 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_20__CLBS_LIN_OFFSET_20___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_20__CLBS_LIN_OFFSET_20___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_20__CLBS_LIN_OFFSET_20___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_20___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_20___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_21 (0x005D68A4) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_21___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_21__CLBS_LIN_OFFSET_21___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_21__CLBS_LIN_OFFSET_21___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_21__CLBS_LIN_OFFSET_21___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_21___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_21___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_22 (0x005D68A8) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_22___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_22__CLBS_LIN_OFFSET_22___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_22__CLBS_LIN_OFFSET_22___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_22__CLBS_LIN_OFFSET_22___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_22___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_22___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_23 (0x005D68AC) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_23___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_23__CLBS_LIN_OFFSET_23___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_23__CLBS_LIN_OFFSET_23___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_23__CLBS_LIN_OFFSET_23___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_23___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_23___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_24 (0x005D68B0) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_24___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_24__CLBS_LIN_OFFSET_24___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_24__CLBS_LIN_OFFSET_24___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_24__CLBS_LIN_OFFSET_24___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_24___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_24___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_25 (0x005D68B4) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_25___POR 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_25__CLBS_LIN_OFFSET_25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_25__CLBS_LIN_OFFSET_25___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_25__CLBS_LIN_OFFSET_25___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_25___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_25___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_26 (0x005D68B8) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_26___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_26__CLBS_LIN_OFFSET_26___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_26__CLBS_LIN_OFFSET_26___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_26__CLBS_LIN_OFFSET_26___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_26___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_26___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_27 (0x005D68BC) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_27___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_27__CLBS_LIN_OFFSET_27___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_27__CLBS_LIN_OFFSET_27___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_27__CLBS_LIN_OFFSET_27___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_27___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_27___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_28 (0x005D68C0) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_28___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_28__CLBS_LIN_OFFSET_28___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_28__CLBS_LIN_OFFSET_28___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_28__CLBS_LIN_OFFSET_28___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_28___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_28___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_29 (0x005D68C4) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_29___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_29__CLBS_LIN_OFFSET_29___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_29__CLBS_LIN_OFFSET_29___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_29__CLBS_LIN_OFFSET_29___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_29___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_29___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_30 (0x005D68C8) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_30___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_30__CLBS_LIN_OFFSET_30___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_30__CLBS_LIN_OFFSET_30___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_30__CLBS_LIN_OFFSET_30___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_30___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_30___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_31 (0x005D68CC) +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_31___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_31__CLBS_LIN_OFFSET_31___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_31__CLBS_LIN_OFFSET_31___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_31__CLBS_LIN_OFFSET_31___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_31___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_CLBS_WL_SYNTH_2G5G_CLBS_31___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST (0x005D6900) +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST___POR 0x06C0F998 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_START___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_VMID_KVCOM___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_VMID_KVCOH___POR 0xC +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_VMID_KVCOL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__EN_VCO_BIST___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__EN_NDIV_BIST___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__EN_RFCNT_BIST___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_RFCNT_OUT_TIME___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_TIME___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_WAIT___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__NDIV_BIST_TIME___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_START___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_START___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_MODE___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_MODE___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_VMID_KVCOM___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_VMID_KVCOM___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_VMID_KVCOH___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_VMID_KVCOH___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_VMID_KVCOL___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_VMID_KVCOL___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__EN_VCO_BIST___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__EN_VCO_BIST___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__EN_NDIV_BIST___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__EN_NDIV_BIST___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__EN_RFCNT_BIST___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__EN_RFCNT_BIST___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_RFCNT_OUT_TIME___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_RFCNT_OUT_TIME___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_TIME___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_TIME___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_WAIT___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__BIST_WAIT___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__NDIV_BIST_TIME___M 0x00000038 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST__NDIV_BIST_TIME___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST___M 0xFFFFFFF8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_WL_SYNTH_2G5G_BIST___S 3 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST0 (0x005D6904) +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST0__RO_RFCNT_BIST_PASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST0__RO_RFCNT_LATCH_TYPE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST0__RO_BIST_OVERLAP___POR 0x000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST0__RO_BIST_MONO___POR 0x000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST0__RO_RFCNT_BIST_PASS___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST0__RO_RFCNT_BIST_PASS___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST0__RO_RFCNT_LATCH_TYPE___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST0__RO_RFCNT_LATCH_TYPE___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST0__RO_BIST_OVERLAP___M 0x07FF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST0__RO_BIST_OVERLAP___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST0__RO_BIST_MONO___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST0__RO_BIST_MONO___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST0___M 0xC7FF07FF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST0___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST1 (0x005D6908) +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST1___POR 0x7FFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST1__RO_OVERLAP_CNT_DIFF___POR 0x7FFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST1__RO_OVERLAP_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST1__RO_OVERLAP_CNT_DIFF___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST1__RO_OVERLAP_CNT_DIFF___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST1__RO_OVERLAP_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST1__RO_OVERLAP_CNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST2 (0x005D690C) +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST2___POR 0x7FFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST2__RO_MONO_CNT_DIFF___POR 0x7FFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST2__RO_MONO_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST2__RO_MONO_CNT_DIFF___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST2__RO_MONO_CNT_DIFF___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST2__RO_MONO_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST2__RO_MONO_CNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST2___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST3 (0x005D6910) +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST3__RO_MIN_BANK_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST3__RO_MAX_BANK_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST3__RO_MIN_BANK_CNT___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST3__RO_MIN_BANK_CNT___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST3__RO_MAX_BANK_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST3__RO_MAX_BANK_CNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST3___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST4 (0x005D6914) +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST4___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST4__RO_ONEBANK_LOW_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST4__RO_ONEBANK_MID_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST4__RO_ONEBANK_LOW_CNT___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST4__RO_ONEBANK_LOW_CNT___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST4__RO_ONEBANK_MID_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST4__RO_ONEBANK_MID_CNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST4___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST5 (0x005D6918) +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST5___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST5__RO_ONEBANK_HIGH_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST5__RO_RFCNT_BIST_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST5__RO_ONEBANK_HIGH_CNT___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST5__RO_ONEBANK_HIGH_CNT___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST5__RO_RFCNT_BIST_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST5__RO_RFCNT_BIST_CNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST5___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST5___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST6 (0x005D691C) +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST6___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST6__RO_NDIV_BIST_CNT_55___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST6__RO_NDIV_BIST_CNT_AA___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST6__RO_NDIV_BIST_CNT_55___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST6__RO_NDIV_BIST_CNT_55___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST6__RO_NDIV_BIST_CNT_AA___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST6__RO_NDIV_BIST_CNT_AA___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST6___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_BIST_RO_WL_SYNTH_2G5G_BIST6___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0 (0x005D6940) +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0___POR 0x00010000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__ATOP_ISO_DIS_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__SDM_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__EN_DCLK___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__VC_2HI_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__VC_2LO_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__SYN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__SYN_EN_REC_LO_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__FASTCH_TMR___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__FASTCH_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__RFCNT_BSCLK_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__RFCNT_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__RFCNT_OUT_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__PRES_RSTB_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__VCON_SW_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__DLL_LOCKED_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__ATOP_ISO_DIS_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__ATOP_ISO_DIS_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__SDM_EN___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__SDM_EN___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__EN_DCLK___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__EN_DCLK___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__VC_2HI_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__VC_2HI_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__VC_2LO_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__VC_2LO_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__SYN_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__SYN_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__SYN_EN_REC_LO_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__SYN_EN_REC_LO_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__FASTCH_TMR___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__FASTCH_TMR___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__FASTCH_SEL___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__FASTCH_SEL___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__RFCNT_BSCLK_EN_OVS___M 0x00001800 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__RFCNT_BSCLK_EN_OVS___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__RFCNT_EN_OVS___M 0x00000600 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__RFCNT_EN_OVS___S 9 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__RFCNT_OUT_EN_OVS___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__RFCNT_OUT_EN_OVS___S 7 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__PRES_RSTB_OVS___M 0x00000060 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__PRES_RSTB_OVS___S 5 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__VCON_SW_OVS___M 0x00000018 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__VCON_SW_OVS___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__DLL_LOCKED_OVS___M 0x00000006 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0__DLL_LOCKED_OVS___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC0___S 1 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1 (0x005D6944) +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__VMID_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__PRECH_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__PFD_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__CP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__PRNDIV_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LPF_VCMON_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__BIAS_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__CP_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__VCO_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_VCOBUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_VCO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_LOGEN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_PFD_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_CP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_FBDIV_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__VMID_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__VMID_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__PRECH_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__PRECH_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__PFD_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__PFD_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__CP_EN_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__CP_EN_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__BIAS_EN_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__BIAS_EN_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__PRNDIV_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__PRNDIV_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LPF_VCMON_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LPF_VCMON_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__BIAS_FC_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__BIAS_FC_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__CP_FC_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__CP_FC_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__VCO_FC_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__VCO_FC_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_VCOBUF_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_VCOBUF_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_VCO_EN_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_VCO_EN_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_LOGEN_EN_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_LOGEN_EN_OVS___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_PFD_EN_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_PFD_EN_OVS___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_CP_EN_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_CP_EN_OVS___S 2 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_FBDIV_EN_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1__LDO_FBDIV_EN_OVS___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2 (0x005D6948) +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_MODE_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_VCO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOGEN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOGEN_DIV2_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOMIX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOAMP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOBUF_CH0_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOBUF_CH1_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOSYNC_RX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOSYNC_TX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__VC_ISO_DIS_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_VCO_EN_6G_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_MODE_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_MODE_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_VCO_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_VCO_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOGEN_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOGEN_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOGEN_DIV2_EN_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOGEN_DIV2_EN_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOMIX_EN_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOMIX_EN_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOAMP_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOAMP_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOBUF_CH0_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOBUF_CH0_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOBUF_CH1_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOBUF_CH1_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOSYNC_RX_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOSYNC_RX_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOSYNC_TX_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_LOSYNC_TX_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__VC_ISO_DIS_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__VC_ISO_DIS_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_VCO_EN_6G_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2__HB_VCO_EN_6G_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2___M 0xFFFFFF00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC2___S 8 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3 (0x005D694C) +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_MODE_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_VCO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_VCO_DIV2_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_VCO_DIV2BUF_FB_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_VCO_DIV2BUF_LO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_LOGEN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_LOGEN_DRV_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_FBN_BUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_BUF_CH0_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_BUF_CH1_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LDO_DTIM_VCO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LDO_DTIM_VCO_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__DTIM_PRNDIV_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__DTIM_DRV_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__DTIM_LB_MODE_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__DTIM_HB_MODE_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_MODE_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_MODE_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_VCO_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_VCO_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_VCO_DIV2_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_VCO_DIV2_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_VCO_DIV2BUF_FB_EN_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_VCO_DIV2BUF_FB_EN_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_VCO_DIV2BUF_LO_EN_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_VCO_DIV2BUF_LO_EN_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_LOGEN_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_LOGEN_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_LOGEN_DRV_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_LOGEN_DRV_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_FBN_BUF_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_FBN_BUF_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_BUF_CH0_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_BUF_CH0_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_BUF_CH1_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LB_BUF_CH1_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LDO_DTIM_VCO_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LDO_DTIM_VCO_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LDO_DTIM_VCO_FC_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__LDO_DTIM_VCO_FC_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__DTIM_PRNDIV_EN_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__DTIM_PRNDIV_EN_OVS___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__DTIM_DRV_EN_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__DTIM_DRV_EN_OVS___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__DTIM_LB_MODE_EN_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__DTIM_LB_MODE_EN_OVS___S 2 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__DTIM_HB_MODE_EN_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3__DTIM_HB_MODE_EN_OVS___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC3___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4 (0x005D6950) +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__SYN_MODE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__SYN_MODE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__ANY_TX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__ANY_RX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__CHAN_IDX_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__CHAN_IDX_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__SYN_MODE_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__SYN_MODE_OV___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__SYN_MODE_OVD___M 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__SYN_MODE_OVD___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__ANY_TX_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__ANY_TX_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__ANY_RX_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__ANY_RX_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__CHAN_IDX_OV___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__CHAN_IDX_OV___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__CHAN_IDX_OVD___M 0x00007FC0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4__CHAN_IDX_OVD___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4___M 0xE00FFFC0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC4___S 6 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5 (0x005D6954) +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__LDO_VCO_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__LDO_CPLVL_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__LOBIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__LOBIAS_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LODIV2LATCH_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LODIV2OBUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LODIV2_IBUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LODIV2_CORE_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LODIV2_OBUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LPVCO_DIV2_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LPVCO_FBCLK_IP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LPVCO_FBCLK_IM_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__LDO_VCO_FC_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__LDO_VCO_FC_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__LDO_CPLVL_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__LDO_CPLVL_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__LOBIAS_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__LOBIAS_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__LOBIAS_FC_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__LOBIAS_FC_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LODIV2LATCH_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LODIV2LATCH_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LODIV2OBUF_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LODIV2OBUF_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LODIV2_IBUF_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LODIV2_IBUF_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LODIV2_CORE_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LODIV2_CORE_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LODIV2_OBUF_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LODIV2_OBUF_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LPVCO_DIV2_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LPVCO_DIV2_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LPVCO_FBCLK_IP_EN_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LPVCO_FBCLK_IP_EN_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LPVCO_FBCLK_IM_EN_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5__HB_LPVCO_FBCLK_IM_EN_OVS___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5___M 0xFF3FFFC0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC5___S 6 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6 (0x005D6958) +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6___POR 0x00001C00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__LB_LODIV2_PREBUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__LB_LODIV2_CORE_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__LB_LODIV2_POSTBUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__VCO_VARAC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__FASTCH_TMR_RESTORE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LODIV2LATCH_EN_OPT___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LODIV2OBUF_EN_OPT___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LOMIX_EN_OPT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LOAMP_EN_OPT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LODIV2_IBUF_EN_OPT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LODIV2_CORE_EN_OPT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LODIV2_OBUF_EN_OPT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__LB_LODIV2_PREBUF_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__LB_LODIV2_PREBUF_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__LB_LODIV2_CORE_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__LB_LODIV2_CORE_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__LB_LODIV2_POSTBUF_EN_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__LB_LODIV2_POSTBUF_EN_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__VCO_VARAC_EN_OVS___M 0x00018000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__VCO_VARAC_EN_OVS___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__FASTCH_TMR_RESTORE___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__FASTCH_TMR_RESTORE___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LODIV2LATCH_EN_OPT___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LODIV2LATCH_EN_OPT___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LODIV2OBUF_EN_OPT___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LODIV2OBUF_EN_OPT___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LOMIX_EN_OPT___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LOMIX_EN_OPT___S 9 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LOAMP_EN_OPT___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LOAMP_EN_OPT___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LODIV2_IBUF_EN_OPT___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LODIV2_IBUF_EN_OPT___S 7 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LODIV2_CORE_EN_OPT___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LODIV2_CORE_EN_OPT___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LODIV2_OBUF_EN_OPT___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6__HB_LODIV2_OBUF_EN_OPT___S 5 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6___M 0x3F01FFE0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC6___S 5 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7 (0x005D695C) +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7__ENBR_IN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7__ENBF_IN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7__SD_ISO_L_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7__SD_PRESET_L_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7__ENBR_IN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7__ENBR_IN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7__ENBF_IN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7__ENBF_IN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7__SD_ISO_L_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7__SD_ISO_L_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7__SD_PRESET_L_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7__SD_PRESET_L_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC7___S 24 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8 (0x005D6960) +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8___POR 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8__VCON_SW_LEG___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8__VCON_SW_OPT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8__SEL_6G_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8__FC_HB_LOGEN_DIV_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8__FC_HB_LOGEN_DIV_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8__VCON_SW_LEG___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8__VCON_SW_LEG___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8__VCON_SW_OPT___M 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8__VCON_SW_OPT___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8__SEL_6G_OVS___M 0x18000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8__SEL_6G_OVS___S 27 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8__FC_HB_LOGEN_DIV_OV___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8__FC_HB_LOGEN_DIV_OV___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8__FC_HB_LOGEN_DIV_OVD___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8__FC_HB_LOGEN_DIV_OVD___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_PC_WL_SYNTH_2G5G_PC8___S 23 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0 (0x005D6980) +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0___POR 0xAF682022 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__KVCO_0___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__IBIAS_0___POR 0x0F +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__LDO_VCO_VREG_0___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__VCO_CMTUNE_0___POR 0x20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__VCO_CMTUNEB_0___POR 0x20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__LOGEN_CAP_0___POR 0x22 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__KVCO_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__KVCO_0___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__IBIAS_0___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__IBIAS_0___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__LDO_VCO_VREG_0___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__LDO_VCO_VREG_0___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__VCO_CMTUNE_0___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__VCO_CMTUNE_0___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__VCO_CMTUNEB_0___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__VCO_CMTUNEB_0___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__LOGEN_CAP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0__LOGEN_CAP_0___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_0___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1 (0x005D6984) +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1___POR 0x8F669A44 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__KVCO_1___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__IBIAS_1___POR 0x0F +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__LDO_VCO_VREG_1___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__VCO_CMTUNE_1___POR 0x1A +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__VCO_CMTUNEB_1___POR 0x1A +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__LOGEN_CAP_1___POR 0x44 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__KVCO_1___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__KVCO_1___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__IBIAS_1___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__IBIAS_1___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__LDO_VCO_VREG_1___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__LDO_VCO_VREG_1___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__VCO_CMTUNE_1___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__VCO_CMTUNE_1___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__VCO_CMTUNEB_1___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__VCO_CMTUNEB_1___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__LOGEN_CAP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1__LOGEN_CAP_1___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2 (0x005D6988) +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2___POR 0x6F859677 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__KVCO_2___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__IBIAS_2___POR 0x0F +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__LDO_VCO_VREG_2___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__VCO_CMTUNE_2___POR 0x16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__VCO_CMTUNEB_2___POR 0x16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__LOGEN_CAP_2___POR 0x77 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__KVCO_2___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__KVCO_2___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__IBIAS_2___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__IBIAS_2___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__LDO_VCO_VREG_2___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__LDO_VCO_VREG_2___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__VCO_CMTUNE_2___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__VCO_CMTUNE_2___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__VCO_CMTUNEB_2___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__VCO_CMTUNEB_2___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__LOGEN_CAP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2__LOGEN_CAP_2___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_2___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3 (0x005D698C) +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3___POR 0x6F851499 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__KVCO_3___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__IBIAS_3___POR 0x0F +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__LDO_VCO_VREG_3___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__VCO_CMTUNE_3___POR 0x14 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__VCO_CMTUNEB_3___POR 0x14 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__LOGEN_CAP_3___POR 0x99 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__KVCO_3___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__KVCO_3___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__IBIAS_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__IBIAS_3___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__LDO_VCO_VREG_3___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__LDO_VCO_VREG_3___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__VCO_CMTUNE_3___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__VCO_CMTUNE_3___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__VCO_CMTUNEB_3___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__VCO_CMTUNEB_3___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__LOGEN_CAP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3__LOGEN_CAP_3___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_3___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4 (0x005D6990) +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4___POR 0xAF6820AA +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__KVCO_4___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__IBIAS_4___POR 0x0F +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__LDO_VCO_VREG_4___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__VCO_CMTUNE_4___POR 0x20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__VCO_CMTUNEB_4___POR 0x20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__LOGEN_CAP_4___POR 0xAA +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__KVCO_4___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__KVCO_4___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__IBIAS_4___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__IBIAS_4___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__LDO_VCO_VREG_4___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__LDO_VCO_VREG_4___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__VCO_CMTUNE_4___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__VCO_CMTUNE_4___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__VCO_CMTUNEB_4___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__VCO_CMTUNEB_4___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__LOGEN_CAP_4___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4__LOGEN_CAP_4___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_4___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5 (0x005D6994) +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5___POR 0x8F669ADD +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__KVCO_5___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__IBIAS_5___POR 0x0F +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__LDO_VCO_VREG_5___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__VCO_CMTUNE_5___POR 0x1A +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__VCO_CMTUNEB_5___POR 0x1A +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__LOGEN_CAP_5___POR 0xDD +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__KVCO_5___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__KVCO_5___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__IBIAS_5___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__IBIAS_5___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__LDO_VCO_VREG_5___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__LDO_VCO_VREG_5___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__VCO_CMTUNE_5___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__VCO_CMTUNE_5___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__VCO_CMTUNEB_5___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__VCO_CMTUNEB_5___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__LOGEN_CAP_5___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5__LOGEN_CAP_5___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_5___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6 (0x005D6998) +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6___POR 0x6F8596EE +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__KVCO_6___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__IBIAS_6___POR 0x0F +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__LDO_VCO_VREG_6___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__VCO_CMTUNE_6___POR 0x16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__VCO_CMTUNEB_6___POR 0x16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__LOGEN_CAP_6___POR 0xEE +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__KVCO_6___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__KVCO_6___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__IBIAS_6___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__IBIAS_6___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__LDO_VCO_VREG_6___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__LDO_VCO_VREG_6___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__VCO_CMTUNE_6___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__VCO_CMTUNE_6___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__VCO_CMTUNEB_6___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__VCO_CMTUNEB_6___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__LOGEN_CAP_6___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6__LOGEN_CAP_6___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_6___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7 (0x005D699C) +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7___POR 0x6F8514FF +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__KVCO_7___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__IBIAS_7___POR 0x0F +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__LDO_VCO_VREG_7___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__VCO_CMTUNE_7___POR 0x14 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__VCO_CMTUNEB_7___POR 0x14 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__LOGEN_CAP_7___POR 0xFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__KVCO_7___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__KVCO_7___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__IBIAS_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__IBIAS_7___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__LDO_VCO_VREG_7___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__LDO_VCO_VREG_7___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__VCO_CMTUNE_7___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__VCO_CMTUNE_7___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__VCO_CMTUNEB_7___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__VCO_CMTUNEB_7___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__LOGEN_CAP_7___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7__LOGEN_CAP_7___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCOMUX_7___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO0 (0x005D69A8) +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO0___POR 0x10120F00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO0__KVCO_TH0___POR 0x020 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO0__KVCO_TH1___POR 0x048 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO0__KVCO_TH2___POR 0x078 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO0__KVCO_TH0___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO0__KVCO_TH0___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO0__KVCO_TH1___M 0x007FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO0__KVCO_TH1___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO0__KVCO_TH2___M 0x00003FE0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO0__KVCO_TH2___S 5 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO0___M 0xFFFFFFE0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO0___S 5 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO1 (0x005D69AC) +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO1___POR 0x5C3EE7A0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO1__KVCO_TH3___POR 0x0B8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO1__KVCO_TH4___POR 0x0FB +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO1__KVCO_TH5___POR 0x13D +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO1__KVCO_TH3___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO1__KVCO_TH3___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO1__KVCO_TH4___M 0x007FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO1__KVCO_TH4___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO1__KVCO_TH5___M 0x00003FE0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO1__KVCO_TH5___S 5 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO1___M 0xFFFFFFE0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO1___S 5 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2 (0x005D69B0) +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2___POR 0xBE800000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_TH6___POR 0x17D +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_SEL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_GATE_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__HB_GATE_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__DTIM_GATE_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_TH6___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_TH6___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_SEL_OV___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_SEL_OV___S 7 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_SEL_OVD___M 0x00000070 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_SEL_OVD___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_GATE_DIS___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__KVCO_GATE_DIS___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__HB_GATE_DIS___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__HB_GATE_DIS___S 2 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__DTIM_GATE_DIS___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2__DTIM_GATE_DIS___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2___M 0xFF8000FE +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_WL_SYNTH_2G5G_KVCO2___S 1 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3 (0x005D69B4) +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_KVCO___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_IBIAS___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_LDO_VCO_VREG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_VCO_CMTUNE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_VCO_CMTUNEB___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_LOGEN_CAP___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_KVCO___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_KVCO___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_IBIAS___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_IBIAS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_LDO_VCO_VREG___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_LDO_VCO_VREG___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_VCO_CMTUNE___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_VCO_CMTUNE___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_VCO_CMTUNEB___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_VCO_CMTUNEB___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_LOGEN_CAP___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3__RO_LOGEN_CAP___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO3___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4 (0x005D69B8) +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_KVCO_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_KVCO_6G___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_VCO_CMTUNE_6G___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_VCO_CMTUNEB_6G___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_KVCO_SEL___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_KVCO_SEL___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_KVCO_6G___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_KVCO_6G___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_VCO_CMTUNE_6G___M 0x03F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_VCO_CMTUNE_6G___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_VCO_CMTUNEB_6G___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4__RO_VCO_CMTUNEB_6G___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4___M 0xFFFFC000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_KVCO_RO_WL_SYNTH_2G5G_KVCO4___S 14 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0 (0x005D69C0) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0___POR 0x00068000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_CP_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_VCO_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_PFD_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_FBDIV_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_LOGEN_VREF___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_LOGEN_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_LOGEN_LEAK___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_CP_LOW_BIAS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_PINVC___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_PFD_C_FILT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_FBDIV_C_FILT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_CP_BYPASS___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_CP_BYPASS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_VCO_BYPASS___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_VCO_BYPASS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_PFD_BYPASS___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_PFD_BYPASS___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_FBDIV_BYPASS___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_FBDIV_BYPASS___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_LOGEN_VREF___M 0x000E0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_LOGEN_VREF___S 17 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_LOGEN_BYPASS___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_LOGEN_BYPASS___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_LOGEN_LEAK___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_LOGEN_LEAK___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_CP_LOW_BIAS___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_CP_LOW_BIAS___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_PINVC___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_PINVC___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_PFD_C_FILT___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_PFD_C_FILT___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_FBDIV_C_FILT___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0__D_LDO_FBDIV_C_FILT___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0___M 0x11CFF800 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC0___S 11 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC1 (0x005D69C4) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC1___POR 0x0000301B +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC1__D_CP_ISEL_IR25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC1__D_SPARE_ISEL_IR25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC1__D_SPARE_ISEL_IC25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC1__D_CP_ISEL_IR25___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC1__D_CP_ISEL_IR25___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC1__D_SPARE_ISEL_IR25___M 0x00000038 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC1__D_SPARE_ISEL_IR25___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC1__D_SPARE_ISEL_IC25___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC1__D_SPARE_ISEL_IC25___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC1___M 0x0000703F +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2 (0x005D69C8) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2___POR 0x6D860000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2__D_LDO_PFD_ISEL_IC25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2__D_LDO_CP_ISEL_IC25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2__D_VCMON_ISEL_IC25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2__D_LDO_FBDIV_ISEL_IC25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2__D_SEL_IC_IPT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2__D_LDO_PFD_ISEL_IC25___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2__D_LDO_PFD_ISEL_IC25___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2__D_LDO_CP_ISEL_IC25___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2__D_LDO_CP_ISEL_IC25___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2__D_VCMON_ISEL_IC25___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2__D_VCMON_ISEL_IC25___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2__D_LDO_FBDIV_ISEL_IC25___M 0x000E0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2__D_LDO_FBDIV_ISEL_IC25___S 17 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2__D_SEL_IC_IPT___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2__D_SEL_IC_IPT___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2___M 0xFF8E0002 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC2___S 1 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC3 (0x005D69CC) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC3___POR 0x00300001 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC3__D_LB_LOBUF_DRVSTR___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC3__D_HB_LOGEN_NOTAIL_AMP_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC3__D_VCO_ISRC_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC3__D_PFD_HI_LK_MODE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC3__D_LB_LOBUF_DRVSTR___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC3__D_LB_LOBUF_DRVSTR___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC3__D_HB_LOGEN_NOTAIL_AMP_EN___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC3__D_HB_LOGEN_NOTAIL_AMP_EN___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC3__D_VCO_ISRC_BYPASS___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC3__D_VCO_ISRC_BYPASS___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC3__D_PFD_HI_LK_MODE___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC3__D_PFD_HI_LK_MODE___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC3___M 0x00308003 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC3___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC4 (0x005D69D0) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC4__D_HB_VCO_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC4__SYN_ATB_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC4__D_VCO_TST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC4__D_HB_VARAC_BIAS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC4__D_HB_VCO_ATB_SEL___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC4__D_HB_VCO_ATB_SEL___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC4__SYN_ATB_SEL___M 0x03E00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC4__SYN_ATB_SEL___S 21 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC4__D_VCO_TST_EN___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC4__D_VCO_TST_EN___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC4__D_HB_VARAC_BIAS___M 0x000E0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC4__D_HB_VARAC_BIAS___S 17 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC4___M 0xE3FE0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC4___S 17 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC5 (0x005D69D4) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC5__D_SYN_SPARE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC5__D_SYN_SPARE_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC5__D_SYN_SPARE_0___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC5___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC5___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC6 (0x005D69D8) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC6__D_SYN_SPARE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC6__D_SYN_SPARE_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC6__D_SYN_SPARE_1___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC6___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC6___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7 (0x005D69DC) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7___POR 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7__CLBS_LPF_VREF_ADJ_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7__LPF_VREF_LO_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7__LPF_VREF_LO_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7__LPF_VREF_HI_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7__LPF_VREF_HI_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7__CLBS_LPF_VREF_ADJ_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7__CLBS_LPF_VREF_ADJ_EN___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7__LPF_VREF_LO_OV___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7__LPF_VREF_LO_OV___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7__LPF_VREF_LO_OVD___M 0x3C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7__LPF_VREF_LO_OVD___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7__LPF_VREF_HI_OV___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7__LPF_VREF_HI_OV___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7__LPF_VREF_HI_OVD___M 0x01E00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7__LPF_VREF_HI_OVD___S 21 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC7___S 21 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0 (0x005D69E0) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_RFCNT_SEL_BSC___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_PFDCP_CPI___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_CP_LEAKER___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_C2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_C3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_R1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_R2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_VREF_LO___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_VREF_HI___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_RFCNT_SEL_BSC___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_RFCNT_SEL_BSC___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_PFDCP_CPI___M 0x1F800000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_PFDCP_CPI___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_CP_LEAKER___M 0x00780000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_CP_LEAKER___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_C2___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_C2___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_C3___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_C3___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_R1___M 0x00003800 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_R1___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_R2___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_R2___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_VREF_LO___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_VREF_LO___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_VREF_HI___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0__RO_LPF_VREF_HI___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC0___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC1 (0x005D69E4) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC1__RO_LPF_R2_6G___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC1__RO_BAND___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC1__RO_LPF_R2_6G___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC1__RO_LPF_R2_6G___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC1__RO_BAND___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC1__RO_BAND___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC1___M 0xE0000003 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_RO_WL_SYNTH_2G5G_AC1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8 (0x005D69E8) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8___POR 0x1CA2B95C +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_VCOBUF_VREG___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_VCO_OTACUR___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_VCOBUF_OTACUR___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_CP_VREG___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_PFD_SEL___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_PFD_VREG___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_PFD_OTACUR___POR 0xC +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_FBDIV_SEL___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_FBDIV_VREG___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_FBDIV_OTACUR___POR 0xC +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_VCOBUF_VREG___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_VCOBUF_VREG___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_VCO_OTACUR___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_VCO_OTACUR___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_VCOBUF_OTACUR___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_VCOBUF_OTACUR___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_CP_VREG___M 0x003C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_CP_VREG___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_PFD_SEL___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_PFD_SEL___S 17 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_PFD_VREG___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_PFD_VREG___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_PFD_OTACUR___M 0x00001E00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_PFD_OTACUR___S 9 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_FBDIV_SEL___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_FBDIV_SEL___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_FBDIV_VREG___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_FBDIV_VREG___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_FBDIV_OTACUR___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8__D_LDO_FBDIV_OTACUR___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC8___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9 (0x005D69EC) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9___POR 0x1C7C6000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_PFD_LKRON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_FBDIV_LKRON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_LOGEN_VREG___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_LOGEN_LKRON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_LOGEN_OTACUR___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_PFD_CAPSEL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_FBDIV_CAPSEL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_VCOBUF_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_PFD_MERGE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_VCO_ISEL_IC25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_CPLVL_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LOBIAS_BWRSEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_PFD_LKRON___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_PFD_LKRON___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_FBDIV_LKRON___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_FBDIV_LKRON___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_LOGEN_VREG___M 0x3C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_LOGEN_VREG___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_LOGEN_LKRON___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_LOGEN_LKRON___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_LOGEN_OTACUR___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_LOGEN_OTACUR___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_PFD_CAPSEL___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_PFD_CAPSEL___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_FBDIV_CAPSEL___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_FBDIV_CAPSEL___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_VCOBUF_BYPASS___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_VCOBUF_BYPASS___S 17 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_PFD_MERGE___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_PFD_MERGE___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_VCO_ISEL_IC25___M 0x0000E000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_VCO_ISEL_IC25___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_CPLVL_BYPASS___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LDO_CPLVL_BYPASS___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LOBIAS_BWRSEL___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9__D_LOBIAS_BWRSEL___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC9___S 10 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10 (0x005D69F0) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10___POR 0x2210000F +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_DEGEN_PROG___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_LKR_DEGEN_PROG___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_VCO_DUALCORE_6G___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_SUPFILT_RES___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_NBIAS_RSEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_PBIAS_RSEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_LDO_MERGE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_LPF_C1___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_VCO_DUALCORE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_DEGEN_PROG___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_DEGEN_PROG___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_LKR_DEGEN_PROG___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_LKR_DEGEN_PROG___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_VCO_DUALCORE_6G___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_VCO_DUALCORE_6G___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_SUPFILT_RES___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_SUPFILT_RES___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_NBIAS_RSEL___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_NBIAS_RSEL___S 17 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_PBIAS_RSEL___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_PBIAS_RSEL___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_LDO_MERGE___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_CP_LDO_MERGE___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_LPF_C1___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_LPF_C1___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_VCO_DUALCORE___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10__D_VCO_DUALCORE___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10___M 0xFF1F800F +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC10___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11 (0x005D69F4) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11___POR 0x03000018 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_HB_LOAMP_CUR___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_LOBUF_DRV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_VREF_FILT_RES___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_BIAS_FILT_RES___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_LB_VCO_VRES09___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_LB_VCO_VRES07___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_CP_DRAINSW_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_LB_VCOBUF_DUMLOAD_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_HB_LOGEN_DIV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_HB_LOAMP_CUR___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_HB_LOAMP_CUR___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_LOBUF_DRV___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_LOBUF_DRV___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_VREF_FILT_RES___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_VREF_FILT_RES___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_BIAS_FILT_RES___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_BIAS_FILT_RES___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_LB_VCO_VRES09___M 0x00078000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_LB_VCO_VRES09___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_LB_VCO_VRES07___M 0x00007800 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_LB_VCO_VRES07___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_CP_DRAINSW_EN___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_CP_DRAINSW_EN___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_LB_VCOBUF_DUMLOAD_EN___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_LB_VCOBUF_DUMLOAD_EN___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_HB_LOGEN_DIV___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11__D_HB_LOGEN_DIV___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11___M 0x0FFFF81F +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC11___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC12 (0x005D69F8) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC12___POR 0x007FF7FF +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC12__BANK_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC12__BANK_OVD___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC12__BANKA_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC12__BANKA_OVD___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC12__BANK_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC12__BANK_OV___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC12__BANK_OVD___M 0x007FF000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC12__BANK_OVD___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC12__BANKA_OV___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC12__BANKA_OV___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC12__BANKA_OVD___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC12__BANKA_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC12___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC12___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13 (0x005D69FC) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13___POR 0x007FF7FF +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13__BANK_6G_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13__BANK_6G_OVD___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13__BANKA_6G_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13__BANKA_6G_OVD___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13__BANK_6G_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13__BANK_6G_OV___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13__BANK_6G_OVD___M 0x007FF000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13__BANK_6G_OVD___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13__BANKA_6G_OV___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13__BANKA_6G_OV___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13__BANKA_6G_OVD___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13__BANKA_6G_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_AC13___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0 (0x005D6A40) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0___POR 0x091B0C00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__RFCNT_SEL_BSC_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__PFDCP_CPI_0___POR 0x12 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__CP_LEAKER_0___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_C2_0___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_C3_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_R1_0___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_R2_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__RFCNT_SEL_BSC_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__RFCNT_SEL_BSC_0___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__PFDCP_CPI_0___M 0x1F800000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__PFDCP_CPI_0___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__CP_LEAKER_0___M 0x00780000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__CP_LEAKER_0___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_C2_0___M 0x00078000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_C2_0___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_C3_0___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_C3_0___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_R1_0___M 0x00001E00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_R1_0___S 9 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_R2_0___M 0x000001C0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0__LPF_R2_0___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0___M 0xFFFFFFC0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_0___S 6 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0 (0x005D6A44) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0___POR 0x67850000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_LO_0___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_HI_0___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_LO_CLBS_0___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_HI_CLBS_0___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_LO_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_LO_0___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_HI_0___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_HI_0___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_LO_CLBS_0___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_LO_CLBS_0___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_HI_CLBS_0___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0__LPF_VREF_HI_CLBS_0___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_0___S 16 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1 (0x005D6A48) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1___POR 0x212B8640 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__RFCNT_SEL_BSC_1___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__PFDCP_CPI_1___POR 0x02 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__CP_LEAKER_1___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_C2_1___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_C3_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_R1_1___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_R2_1___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__RFCNT_SEL_BSC_1___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__RFCNT_SEL_BSC_1___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__PFDCP_CPI_1___M 0x1F800000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__PFDCP_CPI_1___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__CP_LEAKER_1___M 0x00780000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__CP_LEAKER_1___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_C2_1___M 0x00078000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_C2_1___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_C3_1___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_C3_1___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_R1_1___M 0x00001E00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_R1_1___S 9 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_R2_1___M 0x000001C0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1__LPF_R2_1___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1___M 0xFFFFFFC0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_1___S 6 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1 (0x005D6A4C) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1___POR 0x38410000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_LO_1___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_HI_1___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_LO_CLBS_1___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_HI_CLBS_1___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_LO_1___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_LO_1___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_HI_1___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_HI_1___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_LO_CLBS_1___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_LO_CLBS_1___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_HI_CLBS_1___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1__LPF_VREF_HI_CLBS_1___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_1___S 16 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2 (0x005D6A50) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2___POR 0x091B0C40 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__RFCNT_SEL_BSC_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__PFDCP_CPI_2___POR 0x12 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__CP_LEAKER_2___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_C2_2___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_C3_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_R1_2___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_R2_2___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__RFCNT_SEL_BSC_2___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__RFCNT_SEL_BSC_2___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__PFDCP_CPI_2___M 0x1F800000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__PFDCP_CPI_2___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__CP_LEAKER_2___M 0x00780000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__CP_LEAKER_2___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_C2_2___M 0x00078000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_C2_2___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_C3_2___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_C3_2___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_R1_2___M 0x00001E00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_R1_2___S 9 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_R2_2___M 0x000001C0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2__LPF_R2_2___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2___M 0xFFFFFFC0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_2___S 6 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2 (0x005D6A54) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2___POR 0x67850000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_LO_2___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_HI_2___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_LO_CLBS_2___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_HI_CLBS_2___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_LO_2___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_LO_2___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_HI_2___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_HI_2___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_LO_CLBS_2___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_LO_CLBS_2___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_HI_CLBS_2___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2__LPF_VREF_HI_CLBS_2___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_2___S 16 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3 (0x005D6A58) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3___POR 0x212B8640 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__RFCNT_SEL_BSC_3___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__PFDCP_CPI_3___POR 0x02 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__CP_LEAKER_3___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_C2_3___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_C3_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_R1_3___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_R2_3___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__RFCNT_SEL_BSC_3___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__RFCNT_SEL_BSC_3___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__PFDCP_CPI_3___M 0x1F800000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__PFDCP_CPI_3___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__CP_LEAKER_3___M 0x00780000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__CP_LEAKER_3___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_C2_3___M 0x00078000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_C2_3___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_C3_3___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_C3_3___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_R1_3___M 0x00001E00 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_R1_3___S 9 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_R2_3___M 0x000001C0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3__LPF_R2_3___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3___M 0xFFFFFFC0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX_3___S 6 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3 (0x005D6A5C) +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3___POR 0x38410000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_LO_3___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_HI_3___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_LO_CLBS_3___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_HI_CLBS_3___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_LO_3___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_LO_3___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_HI_3___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_HI_3___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_LO_CLBS_3___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_LO_CLBS_3___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_HI_CLBS_3___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3__LPF_VREF_HI_CLBS_3___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_AC_WL_SYNTH_2G5G_BANDMUX1_3___S 16 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL (0x005D6A80) +#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL___POR 0x10000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PAL_REFBUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PAL_REFDIV_EN_OVS___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PAL_FLAG_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PAL_FLAG_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PAL_FLAG_RESET_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PSYNC_START___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PCAL_START___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PAL_REFBUF_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PAL_REFBUF_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PAL_REFDIV_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PAL_REFDIV_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PAL_FLAG_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PAL_FLAG_OV___S 27 +#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PAL_FLAG_OVD___M 0x06000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PAL_FLAG_OVD___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PAL_FLAG_RESET_OVS___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PAL_FLAG_RESET_OVS___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PSYNC_START___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PSYNC_START___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PCAL_START___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL__PCAL_START___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL___M 0xFF800003 +#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_WL_SYNTH_2G5G_PAL___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_RO_WL_SYNTH_2G5G_LO (0x005D6A88) +#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_RO_WL_SYNTH_2G5G_LO___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_RO_WL_SYNTH_2G5G_LO___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_RO_WL_SYNTH_2G5G_LO__RO_LO_FREQ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_RO_WL_SYNTH_2G5G_LO__RO_LO_FREQ___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_RO_WL_SYNTH_2G5G_LO__RO_LO_FREQ___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_RO_WL_SYNTH_2G5G_LO___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_SYNTH1_LO_RO_WL_SYNTH_2G5G_LO___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH0 (0x005D7000) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH0___POR 0x0221D532 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH0__NBNA___POR 0x004 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH0__NF___POR 0x21D532 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH0__NBNA___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH0__NBNA___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH0__NF___M 0x007FFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH0__NF___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH0___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1 (0x005D7004) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__SD_NF_OFFSET___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__BSTARGET_OFS_COARSE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__BSTARGET_OFS_FINE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__BS_COARSE_FINE_BDRY___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__SD_NF_OFFSET___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__SD_NF_OFFSET___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__BSTARGET_OFS_COARSE___M 0x0000FC00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__BSTARGET_OFS_COARSE___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__BSTARGET_OFS_FINE___M 0x000003F0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__BSTARGET_OFS_FINE___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__BS_COARSE_FINE_BDRY___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1__BS_COARSE_FINE_BDRY___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2 (0x005D7008) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2___POR 0x0042AAAA +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_DELTA_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_BASE_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_START___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_DELTA___POR 0x42AAAA +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_DELTA_SEL___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_DELTA_SEL___S 27 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_BASE_SEL___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_BASE_SEL___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_DIS___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_DIS___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_START___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_START___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_DELTA___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2__FC_DELTA___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2___M 0x0FFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH2___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH3 (0x005D700C) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH3___POR 0x55000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH3__FC_DELTA_SUB___POR 0x0AA +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH3__FC_DELTA_SUB___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH3__FC_DELTA_SUB___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH3___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_CH3___S 23 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0 (0x005D7010) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0___POR 0x116C2599 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSSTART___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSMODE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BKSHFT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSSETT___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSWAIT___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSSAMPLE___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__LPF_VTUNEMON_TMR___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_RFCNT_OUT_TIME___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__RFCNTEN_DLY_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_VMID_NON_HB___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_VMID_HB___POR 0x9 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_CLBS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__NF0B___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__D_DTIM_FBDIV4_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__DISABLE_LPF_TMR___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSSTART___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSSTART___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSMODE___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSMODE___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BKSHFT___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BKSHFT___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSSETT___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSSETT___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSWAIT___M 0x00E00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSWAIT___S 21 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSSAMPLE___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BSSAMPLE___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__LPF_VTUNEMON_TMR___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__LPF_VTUNEMON_TMR___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_RFCNT_OUT_TIME___M 0x0000E000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_RFCNT_OUT_TIME___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__RFCNTEN_DLY_DIS___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__RFCNTEN_DLY_DIS___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_VMID_NON_HB___M 0x00000F00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_VMID_NON_HB___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_VMID_HB___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_VMID_HB___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_CLBS_EN___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__BS_CLBS_EN___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__NF0B___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__NF0B___S 2 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__D_DTIM_FBDIV4_SEL___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__D_DTIM_FBDIV4_SEL___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__DISABLE_LPF_TMR___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0__DISABLE_LPF_TMR___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS0___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1 (0x005D7014) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1___POR 0x80680000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SDM_SEL___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SDMOGAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__BSTESTEN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SDTESTEN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SD_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__D_PLLMD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__BS_OVCAL_BDRY___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__PLL_SLIP_DET_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__RESTORE_BS_CLBS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__DTEST2_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__DTEST1_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__DTEST0_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SDM_SEL___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SDM_SEL___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SDMOGAIN___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SDMOGAIN___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__BSTESTEN___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__BSTESTEN___S 27 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SDTESTEN___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SDTESTEN___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SD_RESET___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__SD_RESET___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__D_PLLMD___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__D_PLLMD___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__BS_OVCAL_BDRY___M 0x00E00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__BS_OVCAL_BDRY___S 21 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__PLL_SLIP_DET_RESET___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__PLL_SLIP_DET_RESET___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__RESTORE_BS_CLBS_EN___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__RESTORE_BS_CLBS_EN___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__DTEST2_SEL___M 0x00007C00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__DTEST2_SEL___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__DTEST1_SEL___M 0x000003E0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__DTEST1_SEL___S 5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__DTEST0_SEL___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1__DTEST0_SEL___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1___M 0xFFF87FFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS2 (0x005D7018) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS2___POR 0x04000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS2__IVCOBK___POR 0x400 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS2__TSTCNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS2__IVCOBK___M 0x07FF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS2__IVCOBK___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS2__TSTCNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS2__TSTCNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS2___M 0x07FFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_WL_SYNTH_LP5G_BS2___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS0 (0x005D701C) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS0__RO_BSTARGET___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS0__RO_BSCOUNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS0__RO_BSTARGET___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS0__RO_BSTARGET___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS0__RO_BSCOUNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS0__RO_BSCOUNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS0___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1 (0x005D7020) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_VC_2HI___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_VC_2LO___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BIST_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_FVCOBK___POR 0x000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B3___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B3___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B2___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B2___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B1___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B1___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B0___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSDELTA_B0___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_VC_2HI___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_VC_2HI___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_VC_2LO___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_VC_2LO___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BIST_ON___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BIST_ON___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSON___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_BSON___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_FVCOBK___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1__RO_FVCOBK___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1___M 0xFFFF7FFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2 (0x005D7024) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_SYN_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_SYN_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_SYN_EN_REC_LO___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_ANY_RX_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_ANY_TX_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_CLBS_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_TX_MASK___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2HI_AT_VTUNEMON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2LO_AT_VTUNEMON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2HI_AFTER_VTUNEMON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2LO_AFTER_VTUNEMON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_PLL_LOCK_DET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_PLL_LOCK___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_DLL_LOCKED___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_NON_DTIM_5G___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_BS_VMID___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_CHAN_IDX___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_SYN_MODE___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_SYN_MODE___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_SYN_EN___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_SYN_EN___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_SYN_EN_REC_LO___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_SYN_EN_REC_LO___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_ANY_RX_EN___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_ANY_RX_EN___S 27 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_ANY_TX_EN___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_ANY_TX_EN___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_CLBS_ON___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_CLBS_ON___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_TX_MASK___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_TX_MASK___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2HI_AT_VTUNEMON___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2HI_AT_VTUNEMON___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2LO_AT_VTUNEMON___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2LO_AT_VTUNEMON___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2HI_AFTER_VTUNEMON___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2HI_AFTER_VTUNEMON___S 17 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2LO_AFTER_VTUNEMON___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_VC_2LO_AFTER_VTUNEMON___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_PLL_LOCK_DET___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_PLL_LOCK_DET___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_PLL_LOCK___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_PLL_LOCK___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_DLL_LOCKED___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_DLL_LOCKED___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_NON_DTIM_5G___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_NON_DTIM_5G___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_BS_VMID___M 0x00000F00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_BS_VMID___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_CHAN_IDX___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2__RO_CHAN_IDX___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2___M 0xFF0FFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS2___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS3 (0x005D7028) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS3__RO_NBNA___POR 0x000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS3__RO_NBNA___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS3__RO_NBNA___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS3___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS3___S 23 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS4 (0x005D702C) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS4___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS4__RO_NF___POR 0x000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS4__RO_NF___M 0x007FFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS4__RO_NF___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS4___M 0x007FFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS4___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS5 (0x005D7030) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS5___POR 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS5__CLBS_QS_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS5__CLBS_QS_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS5__CLBS_QS_EN___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS5___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS5___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS6 (0x005D7034) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS6__BANK_DBG_OFFSET___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS6__RO_INIT_BANK___POR 0x000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS6__BANK_DBG_OFFSET___M 0x0001F800 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS6__BANK_DBG_OFFSET___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS6__RO_INIT_BANK___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS6__RO_INIT_BANK___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS6___M 0x0001FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BS_RO_WL_SYNTH_LP5G_BS6___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0 (0x005D7040) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0___POR 0x44A43E4A +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_START___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_ENABLE_VC___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_ENABLE_TX___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_ENABLE_RX___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_MODE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_COMP_REPEAT___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_SMPL_RATE___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_MAX_STEP___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_STEPSIZE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_HYBRID_BDRY___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_SETTIME___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_SAMPLE___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_MASK_SEL___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_PSYNC_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_START___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_START___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_ENABLE_VC___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_ENABLE_VC___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_ENABLE_TX___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_ENABLE_TX___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_ENABLE_RX___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_ENABLE_RX___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_MODE___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_MODE___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_COMP_REPEAT___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_COMP_REPEAT___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_SMPL_RATE___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_SMPL_RATE___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_MAX_STEP___M 0x00078000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_MAX_STEP___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_STEPSIZE___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_STEPSIZE___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_HYBRID_BDRY___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_HYBRID_BDRY___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_SETTIME___M 0x00000380 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_SETTIME___S 7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_SAMPLE___M 0x00000070 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_SAMPLE___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_MASK_SEL___M 0x0000000C +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_MASK_SEL___S 2 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_PSYNC_EN___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0__CLBS_PSYNC_EN___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0___M 0xFCFFFFFE +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS0___S 1 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1 (0x005D7044) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1___POR 0xB4208000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_BDRY___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_INC___POR 0x08 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_DEC___POR 0x08 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_SAMPLE_RESTORE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_EN___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_BDRY___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_BDRY___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_INC___M 0x0F800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_INC___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_DEC___M 0x007C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_OVSKIP_DEC___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_SAMPLE_RESTORE___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1__CLBS_SAMPLE_RESTORE___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1___M 0xFFFF8000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS1___S 15 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS (0x005D7048) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS__RO_CLBS_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS__RO_NON_DTIM_5G___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS__RO_CLBS_OFF_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS__RO_CLBS_MODE___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS__RO_CLBS_MODE___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS__RO_NON_DTIM_5G___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS__RO_NON_DTIM_5G___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS__RO_CLBS_OFF_SEL___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS__RO_CLBS_OFF_SEL___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_RO_WL_SYNTH_LP5G_CLBS___S 24 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2 (0x005D704C) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2__CLBS_OFF_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2__CLBS_OFF_SEL_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2__CLBS_LIN_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2__CLBS_OFF_SEL_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2__CLBS_OFF_SEL_OV___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2__CLBS_OFF_SEL_OVD___M 0x7C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2__CLBS_OFF_SEL_OVD___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2__CLBS_LIN_EN___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2__CLBS_LIN_EN___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS2___S 25 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_0 (0x005D7050) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_0___POR 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_0__CLBS_LIN_OFFSET_0___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_0__CLBS_LIN_OFFSET_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_0__CLBS_LIN_OFFSET_0___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_0___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_1 (0x005D7054) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_1___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_1__CLBS_LIN_OFFSET_1___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_1__CLBS_LIN_OFFSET_1___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_1__CLBS_LIN_OFFSET_1___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_1___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_1___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_2 (0x005D7058) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_2___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_2__CLBS_LIN_OFFSET_2___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_2__CLBS_LIN_OFFSET_2___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_2__CLBS_LIN_OFFSET_2___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_2___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_2___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_3 (0x005D705C) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_3___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_3__CLBS_LIN_OFFSET_3___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_3__CLBS_LIN_OFFSET_3___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_3__CLBS_LIN_OFFSET_3___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_3___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_3___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_4 (0x005D7060) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_4___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_4__CLBS_LIN_OFFSET_4___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_4__CLBS_LIN_OFFSET_4___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_4__CLBS_LIN_OFFSET_4___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_4___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_4___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_5 (0x005D7064) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_5___POR 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_5__CLBS_LIN_OFFSET_5___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_5__CLBS_LIN_OFFSET_5___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_5__CLBS_LIN_OFFSET_5___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_5___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_5___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_6 (0x005D7068) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_6___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_6__CLBS_LIN_OFFSET_6___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_6__CLBS_LIN_OFFSET_6___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_6__CLBS_LIN_OFFSET_6___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_6___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_6___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_7 (0x005D706C) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_7___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_7__CLBS_LIN_OFFSET_7___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_7__CLBS_LIN_OFFSET_7___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_7__CLBS_LIN_OFFSET_7___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_7___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_7___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_8 (0x005D7070) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_8___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_8__CLBS_LIN_OFFSET_8___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_8__CLBS_LIN_OFFSET_8___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_8__CLBS_LIN_OFFSET_8___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_8___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_8___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_9 (0x005D7074) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_9___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_9__CLBS_LIN_OFFSET_9___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_9__CLBS_LIN_OFFSET_9___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_9__CLBS_LIN_OFFSET_9___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_9___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_9___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_10 (0x005D7078) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_10___POR 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_10__CLBS_LIN_OFFSET_10___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_10__CLBS_LIN_OFFSET_10___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_10__CLBS_LIN_OFFSET_10___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_10___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_10___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_11 (0x005D707C) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_11___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_11__CLBS_LIN_OFFSET_11___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_11__CLBS_LIN_OFFSET_11___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_11__CLBS_LIN_OFFSET_11___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_11___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_11___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_12 (0x005D7080) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_12___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_12__CLBS_LIN_OFFSET_12___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_12__CLBS_LIN_OFFSET_12___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_12__CLBS_LIN_OFFSET_12___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_12___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_12___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_13 (0x005D7084) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_13___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_13__CLBS_LIN_OFFSET_13___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_13__CLBS_LIN_OFFSET_13___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_13__CLBS_LIN_OFFSET_13___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_13___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_13___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_14 (0x005D7088) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_14___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_14__CLBS_LIN_OFFSET_14___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_14__CLBS_LIN_OFFSET_14___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_14__CLBS_LIN_OFFSET_14___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_14___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_14___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_15 (0x005D708C) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_15___POR 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_15__CLBS_LIN_OFFSET_15___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_15__CLBS_LIN_OFFSET_15___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_15__CLBS_LIN_OFFSET_15___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_15___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_15___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_16 (0x005D7090) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_16___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_16__CLBS_LIN_OFFSET_16___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_16__CLBS_LIN_OFFSET_16___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_16__CLBS_LIN_OFFSET_16___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_16___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_16___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_17 (0x005D7094) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_17___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_17__CLBS_LIN_OFFSET_17___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_17__CLBS_LIN_OFFSET_17___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_17__CLBS_LIN_OFFSET_17___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_17___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_17___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_18 (0x005D7098) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_18___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_18__CLBS_LIN_OFFSET_18___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_18__CLBS_LIN_OFFSET_18___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_18__CLBS_LIN_OFFSET_18___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_18___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_18___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_19 (0x005D709C) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_19___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_19__CLBS_LIN_OFFSET_19___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_19__CLBS_LIN_OFFSET_19___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_19__CLBS_LIN_OFFSET_19___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_19___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_19___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_20 (0x005D70A0) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_20___POR 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_20__CLBS_LIN_OFFSET_20___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_20__CLBS_LIN_OFFSET_20___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_20__CLBS_LIN_OFFSET_20___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_20___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_20___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_21 (0x005D70A4) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_21___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_21__CLBS_LIN_OFFSET_21___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_21__CLBS_LIN_OFFSET_21___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_21__CLBS_LIN_OFFSET_21___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_21___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_21___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_22 (0x005D70A8) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_22___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_22__CLBS_LIN_OFFSET_22___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_22__CLBS_LIN_OFFSET_22___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_22__CLBS_LIN_OFFSET_22___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_22___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_22___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_23 (0x005D70AC) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_23___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_23__CLBS_LIN_OFFSET_23___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_23__CLBS_LIN_OFFSET_23___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_23__CLBS_LIN_OFFSET_23___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_23___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_23___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_24 (0x005D70B0) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_24___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_24__CLBS_LIN_OFFSET_24___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_24__CLBS_LIN_OFFSET_24___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_24__CLBS_LIN_OFFSET_24___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_24___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_24___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_25 (0x005D70B4) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_25___POR 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_25__CLBS_LIN_OFFSET_25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_25__CLBS_LIN_OFFSET_25___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_25__CLBS_LIN_OFFSET_25___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_25___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_25___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_26 (0x005D70B8) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_26___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_26__CLBS_LIN_OFFSET_26___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_26__CLBS_LIN_OFFSET_26___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_26__CLBS_LIN_OFFSET_26___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_26___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_26___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_27 (0x005D70BC) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_27___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_27__CLBS_LIN_OFFSET_27___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_27__CLBS_LIN_OFFSET_27___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_27__CLBS_LIN_OFFSET_27___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_27___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_27___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_28 (0x005D70C0) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_28___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_28__CLBS_LIN_OFFSET_28___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_28__CLBS_LIN_OFFSET_28___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_28__CLBS_LIN_OFFSET_28___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_28___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_28___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_29 (0x005D70C4) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_29___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_29__CLBS_LIN_OFFSET_29___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_29__CLBS_LIN_OFFSET_29___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_29__CLBS_LIN_OFFSET_29___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_29___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_29___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_30 (0x005D70C8) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_30___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_30__CLBS_LIN_OFFSET_30___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_30__CLBS_LIN_OFFSET_30___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_30__CLBS_LIN_OFFSET_30___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_30___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_30___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_31 (0x005D70CC) +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_31___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_31__CLBS_LIN_OFFSET_31___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_31__CLBS_LIN_OFFSET_31___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_31__CLBS_LIN_OFFSET_31___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_31___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_CLBS_WL_SYNTH_LP5G_CLBS_31___S 28 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST (0x005D7100) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST___POR 0x06C0F998 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_START___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_VMID_KVCOM___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_VMID_KVCOH___POR 0xC +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_VMID_KVCOL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__EN_VCO_BIST___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__EN_NDIV_BIST___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__EN_RFCNT_BIST___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_RFCNT_OUT_TIME___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_TIME___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_WAIT___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__NDIV_BIST_TIME___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_START___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_START___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_MODE___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_MODE___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_VMID_KVCOM___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_VMID_KVCOM___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_VMID_KVCOH___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_VMID_KVCOH___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_VMID_KVCOL___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_VMID_KVCOL___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__EN_VCO_BIST___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__EN_VCO_BIST___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__EN_NDIV_BIST___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__EN_NDIV_BIST___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__EN_RFCNT_BIST___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__EN_RFCNT_BIST___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_RFCNT_OUT_TIME___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_RFCNT_OUT_TIME___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_TIME___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_TIME___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_WAIT___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__BIST_WAIT___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__NDIV_BIST_TIME___M 0x00000038 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST__NDIV_BIST_TIME___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST___M 0xFFFFFFF8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_WL_SYNTH_LP5G_BIST___S 3 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0 (0x005D7104) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_RFCNT_BIST_PASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_RFCNT_LATCH_TYPE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_BIST_OVERLAP___POR 0x000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_BIST_MONO___POR 0x000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_RFCNT_BIST_PASS___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_RFCNT_BIST_PASS___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_RFCNT_LATCH_TYPE___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_RFCNT_LATCH_TYPE___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_BIST_OVERLAP___M 0x07FF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_BIST_OVERLAP___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_BIST_MONO___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0__RO_BIST_MONO___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0___M 0xC7FF07FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST0___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST1 (0x005D7108) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST1___POR 0x7FFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST1__RO_OVERLAP_CNT_DIFF___POR 0x7FFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST1__RO_OVERLAP_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST1__RO_OVERLAP_CNT_DIFF___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST1__RO_OVERLAP_CNT_DIFF___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST1__RO_OVERLAP_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST1__RO_OVERLAP_CNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST2 (0x005D710C) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST2___POR 0x7FFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST2__RO_MONO_CNT_DIFF___POR 0x7FFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST2__RO_MONO_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST2__RO_MONO_CNT_DIFF___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST2__RO_MONO_CNT_DIFF___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST2__RO_MONO_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST2__RO_MONO_CNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST2___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST3 (0x005D7110) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST3__RO_MIN_BANK_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST3__RO_MAX_BANK_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST3__RO_MIN_BANK_CNT___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST3__RO_MIN_BANK_CNT___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST3__RO_MAX_BANK_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST3__RO_MAX_BANK_CNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST3___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST4 (0x005D7114) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST4___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST4__RO_ONEBANK_LOW_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST4__RO_ONEBANK_MID_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST4__RO_ONEBANK_LOW_CNT___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST4__RO_ONEBANK_LOW_CNT___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST4__RO_ONEBANK_MID_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST4__RO_ONEBANK_MID_CNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST4___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST5 (0x005D7118) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST5___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST5__RO_ONEBANK_HIGH_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST5__RO_RFCNT_BIST_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST5__RO_ONEBANK_HIGH_CNT___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST5__RO_ONEBANK_HIGH_CNT___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST5__RO_RFCNT_BIST_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST5__RO_RFCNT_BIST_CNT___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST5___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST5___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST6 (0x005D711C) +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST6___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST6__RO_NDIV_BIST_CNT_55___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST6__RO_NDIV_BIST_CNT_AA___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST6__RO_NDIV_BIST_CNT_55___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST6__RO_NDIV_BIST_CNT_55___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST6__RO_NDIV_BIST_CNT_AA___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST6__RO_NDIV_BIST_CNT_AA___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST6___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_BIST_RO_WL_SYNTH_LP5G_BIST6___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0 (0x005D7140) +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0___POR 0x00010000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__ATOP_ISO_DIS_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__SDM_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__EN_DCLK___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__VC_2HI_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__VC_2LO_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__SYN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__SYN_EN_REC_LO_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__FASTCH_TMR___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__FASTCH_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__RFCNT_BSCLK_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__RFCNT_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__RFCNT_OUT_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__PRES_RSTB_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__VCON_SW_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__DLL_LOCKED_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__ATOP_ISO_DIS_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__ATOP_ISO_DIS_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__SDM_EN___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__SDM_EN___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__EN_DCLK___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__EN_DCLK___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__VC_2HI_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__VC_2HI_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__VC_2LO_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__VC_2LO_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__SYN_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__SYN_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__SYN_EN_REC_LO_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__SYN_EN_REC_LO_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__FASTCH_TMR___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__FASTCH_TMR___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__FASTCH_SEL___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__FASTCH_SEL___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__RFCNT_BSCLK_EN_OVS___M 0x00001800 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__RFCNT_BSCLK_EN_OVS___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__RFCNT_EN_OVS___M 0x00000600 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__RFCNT_EN_OVS___S 9 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__RFCNT_OUT_EN_OVS___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__RFCNT_OUT_EN_OVS___S 7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__PRES_RSTB_OVS___M 0x00000060 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__PRES_RSTB_OVS___S 5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__VCON_SW_OVS___M 0x00000018 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__VCON_SW_OVS___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__DLL_LOCKED_OVS___M 0x00000006 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0__DLL_LOCKED_OVS___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC0___S 1 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1 (0x005D7144) +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__VMID_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__PRECH_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__PFD_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__CP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__PRNDIV_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LPF_VCMON_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__BIAS_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__CP_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__VCO_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_VCOBUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_VCO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_LOGEN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_PFD_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_CP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_FBDIV_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__VMID_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__VMID_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__PRECH_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__PRECH_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__PFD_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__PFD_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__CP_EN_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__CP_EN_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__BIAS_EN_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__BIAS_EN_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__PRNDIV_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__PRNDIV_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LPF_VCMON_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LPF_VCMON_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__BIAS_FC_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__BIAS_FC_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__CP_FC_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__CP_FC_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__VCO_FC_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__VCO_FC_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_VCOBUF_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_VCOBUF_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_VCO_EN_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_VCO_EN_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_LOGEN_EN_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_LOGEN_EN_OVS___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_PFD_EN_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_PFD_EN_OVS___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_CP_EN_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_CP_EN_OVS___S 2 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_FBDIV_EN_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1__LDO_FBDIV_EN_OVS___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2 (0x005D7148) +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_MODE_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_VCO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOGEN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOGEN_DIV2_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOMIX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOAMP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOBUF_CH0_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOBUF_CH1_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOSYNC_RX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOSYNC_TX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__VC_ISO_DIS_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_VCO_EN_6G_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_MODE_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_MODE_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_VCO_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_VCO_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOGEN_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOGEN_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOGEN_DIV2_EN_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOGEN_DIV2_EN_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOMIX_EN_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOMIX_EN_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOAMP_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOAMP_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOBUF_CH0_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOBUF_CH0_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOBUF_CH1_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOBUF_CH1_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOSYNC_RX_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOSYNC_RX_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOSYNC_TX_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_LOSYNC_TX_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__VC_ISO_DIS_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__VC_ISO_DIS_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_VCO_EN_6G_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2__HB_VCO_EN_6G_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2___M 0xFFFFFF00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC2___S 8 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3 (0x005D714C) +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_MODE_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_DIV2_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_DIV2BUF_FB_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_DIV2BUF_LO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_LOGEN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_LOGEN_DRV_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_FBN_BUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_BUF_CH0_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_BUF_CH1_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LDO_DTIM_VCO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LDO_DTIM_VCO_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_PRNDIV_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_DRV_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_LB_MODE_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_HB_MODE_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_MODE_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_MODE_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_DIV2_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_DIV2_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_DIV2BUF_FB_EN_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_DIV2BUF_FB_EN_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_DIV2BUF_LO_EN_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_VCO_DIV2BUF_LO_EN_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_LOGEN_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_LOGEN_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_LOGEN_DRV_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_LOGEN_DRV_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_FBN_BUF_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_FBN_BUF_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_BUF_CH0_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_BUF_CH0_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_BUF_CH1_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LB_BUF_CH1_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LDO_DTIM_VCO_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LDO_DTIM_VCO_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LDO_DTIM_VCO_FC_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__LDO_DTIM_VCO_FC_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_PRNDIV_EN_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_PRNDIV_EN_OVS___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_DRV_EN_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_DRV_EN_OVS___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_LB_MODE_EN_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_LB_MODE_EN_OVS___S 2 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_HB_MODE_EN_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3__DTIM_HB_MODE_EN_OVS___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC3___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4 (0x005D7150) +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__SYN_MODE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__SYN_MODE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__ANY_TX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__ANY_RX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__CHAN_IDX_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__CHAN_IDX_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__SYN_MODE_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__SYN_MODE_OV___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__SYN_MODE_OVD___M 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__SYN_MODE_OVD___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__ANY_TX_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__ANY_TX_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__ANY_RX_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__ANY_RX_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__CHAN_IDX_OV___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__CHAN_IDX_OV___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__CHAN_IDX_OVD___M 0x00007FC0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4__CHAN_IDX_OVD___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4___M 0xE00FFFC0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC4___S 6 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5 (0x005D7154) +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LDO_VCO_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LDO_CPLVL_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LOBIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LOBIAS_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2LATCH_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2OBUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2_IBUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2_CORE_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2_OBUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LPVCO_DIV2_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LPVCO_FBCLK_IP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LPVCO_FBCLK_IM_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LDO_VCO_FC_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LDO_VCO_FC_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LDO_CPLVL_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LDO_CPLVL_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LOBIAS_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LOBIAS_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LOBIAS_FC_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__LOBIAS_FC_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2LATCH_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2LATCH_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2OBUF_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2OBUF_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2_IBUF_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2_IBUF_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2_CORE_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2_CORE_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2_OBUF_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LODIV2_OBUF_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LPVCO_DIV2_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LPVCO_DIV2_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LPVCO_FBCLK_IP_EN_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LPVCO_FBCLK_IP_EN_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LPVCO_FBCLK_IM_EN_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5__HB_LPVCO_FBCLK_IM_EN_OVS___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5___M 0xFF3FFFC0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC5___S 6 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6 (0x005D7158) +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6___POR 0x00001C00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__LB_LODIV2_PREBUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__LB_LODIV2_CORE_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__LB_LODIV2_POSTBUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__VCO_VARAC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__FASTCH_TMR_RESTORE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2LATCH_EN_OPT___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2OBUF_EN_OPT___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LOMIX_EN_OPT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LOAMP_EN_OPT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2_IBUF_EN_OPT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2_CORE_EN_OPT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2_OBUF_EN_OPT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__LB_LODIV2_PREBUF_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__LB_LODIV2_PREBUF_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__LB_LODIV2_CORE_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__LB_LODIV2_CORE_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__LB_LODIV2_POSTBUF_EN_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__LB_LODIV2_POSTBUF_EN_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__VCO_VARAC_EN_OVS___M 0x00018000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__VCO_VARAC_EN_OVS___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__FASTCH_TMR_RESTORE___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__FASTCH_TMR_RESTORE___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2LATCH_EN_OPT___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2LATCH_EN_OPT___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2OBUF_EN_OPT___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2OBUF_EN_OPT___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LOMIX_EN_OPT___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LOMIX_EN_OPT___S 9 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LOAMP_EN_OPT___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LOAMP_EN_OPT___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2_IBUF_EN_OPT___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2_IBUF_EN_OPT___S 7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2_CORE_EN_OPT___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2_CORE_EN_OPT___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2_OBUF_EN_OPT___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6__HB_LODIV2_OBUF_EN_OPT___S 5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6___M 0x3F01FFE0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC6___S 5 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7 (0x005D715C) +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__ENBR_IN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__ENBF_IN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__SD_ISO_L_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__SD_PRESET_L_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__ENBR_IN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__ENBR_IN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__ENBF_IN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__ENBF_IN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__SD_ISO_L_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__SD_ISO_L_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__SD_PRESET_L_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7__SD_PRESET_L_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC7___S 24 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8 (0x005D7160) +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8___POR 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__VCON_SW_LEG___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__VCON_SW_OPT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__SEL_6G_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__FC_HB_LOGEN_DIV_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__FC_HB_LOGEN_DIV_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__VCON_SW_LEG___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__VCON_SW_LEG___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__VCON_SW_OPT___M 0x60000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__VCON_SW_OPT___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__SEL_6G_OVS___M 0x18000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__SEL_6G_OVS___S 27 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__FC_HB_LOGEN_DIV_OV___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__FC_HB_LOGEN_DIV_OV___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__FC_HB_LOGEN_DIV_OVD___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8__FC_HB_LOGEN_DIV_OVD___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_PC_WL_SYNTH_LP5G_PC8___S 23 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0 (0x005D7180) +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0___POR 0xAF682022 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__KVCO_0___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__IBIAS_0___POR 0x0F +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__LDO_VCO_VREG_0___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__VCO_CMTUNE_0___POR 0x20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__VCO_CMTUNEB_0___POR 0x20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__LOGEN_CAP_0___POR 0x22 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__KVCO_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__KVCO_0___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__IBIAS_0___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__IBIAS_0___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__LDO_VCO_VREG_0___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__LDO_VCO_VREG_0___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__VCO_CMTUNE_0___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__VCO_CMTUNE_0___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__VCO_CMTUNEB_0___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__VCO_CMTUNEB_0___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__LOGEN_CAP_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0__LOGEN_CAP_0___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_0___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1 (0x005D7184) +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1___POR 0x8F669A44 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__KVCO_1___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__IBIAS_1___POR 0x0F +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__LDO_VCO_VREG_1___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__VCO_CMTUNE_1___POR 0x1A +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__VCO_CMTUNEB_1___POR 0x1A +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__LOGEN_CAP_1___POR 0x44 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__KVCO_1___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__KVCO_1___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__IBIAS_1___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__IBIAS_1___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__LDO_VCO_VREG_1___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__LDO_VCO_VREG_1___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__VCO_CMTUNE_1___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__VCO_CMTUNE_1___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__VCO_CMTUNEB_1___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__VCO_CMTUNEB_1___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__LOGEN_CAP_1___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1__LOGEN_CAP_1___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2 (0x005D7188) +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2___POR 0x6F859677 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__KVCO_2___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__IBIAS_2___POR 0x0F +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__LDO_VCO_VREG_2___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__VCO_CMTUNE_2___POR 0x16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__VCO_CMTUNEB_2___POR 0x16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__LOGEN_CAP_2___POR 0x77 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__KVCO_2___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__KVCO_2___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__IBIAS_2___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__IBIAS_2___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__LDO_VCO_VREG_2___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__LDO_VCO_VREG_2___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__VCO_CMTUNE_2___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__VCO_CMTUNE_2___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__VCO_CMTUNEB_2___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__VCO_CMTUNEB_2___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__LOGEN_CAP_2___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2__LOGEN_CAP_2___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_2___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3 (0x005D718C) +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3___POR 0x6F851499 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__KVCO_3___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__IBIAS_3___POR 0x0F +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__LDO_VCO_VREG_3___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__VCO_CMTUNE_3___POR 0x14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__VCO_CMTUNEB_3___POR 0x14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__LOGEN_CAP_3___POR 0x99 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__KVCO_3___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__KVCO_3___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__IBIAS_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__IBIAS_3___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__LDO_VCO_VREG_3___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__LDO_VCO_VREG_3___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__VCO_CMTUNE_3___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__VCO_CMTUNE_3___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__VCO_CMTUNEB_3___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__VCO_CMTUNEB_3___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__LOGEN_CAP_3___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3__LOGEN_CAP_3___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_3___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4 (0x005D7190) +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4___POR 0xAF6820AA +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__KVCO_4___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__IBIAS_4___POR 0x0F +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__LDO_VCO_VREG_4___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__VCO_CMTUNE_4___POR 0x20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__VCO_CMTUNEB_4___POR 0x20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__LOGEN_CAP_4___POR 0xAA +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__KVCO_4___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__KVCO_4___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__IBIAS_4___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__IBIAS_4___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__LDO_VCO_VREG_4___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__LDO_VCO_VREG_4___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__VCO_CMTUNE_4___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__VCO_CMTUNE_4___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__VCO_CMTUNEB_4___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__VCO_CMTUNEB_4___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__LOGEN_CAP_4___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4__LOGEN_CAP_4___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_4___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5 (0x005D7194) +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5___POR 0x8F669ADD +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__KVCO_5___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__IBIAS_5___POR 0x0F +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__LDO_VCO_VREG_5___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__VCO_CMTUNE_5___POR 0x1A +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__VCO_CMTUNEB_5___POR 0x1A +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__LOGEN_CAP_5___POR 0xDD +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__KVCO_5___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__KVCO_5___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__IBIAS_5___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__IBIAS_5___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__LDO_VCO_VREG_5___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__LDO_VCO_VREG_5___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__VCO_CMTUNE_5___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__VCO_CMTUNE_5___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__VCO_CMTUNEB_5___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__VCO_CMTUNEB_5___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__LOGEN_CAP_5___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5__LOGEN_CAP_5___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_5___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6 (0x005D7198) +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6___POR 0x6F8596EE +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__KVCO_6___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__IBIAS_6___POR 0x0F +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__LDO_VCO_VREG_6___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__VCO_CMTUNE_6___POR 0x16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__VCO_CMTUNEB_6___POR 0x16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__LOGEN_CAP_6___POR 0xEE +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__KVCO_6___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__KVCO_6___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__IBIAS_6___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__IBIAS_6___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__LDO_VCO_VREG_6___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__LDO_VCO_VREG_6___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__VCO_CMTUNE_6___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__VCO_CMTUNE_6___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__VCO_CMTUNEB_6___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__VCO_CMTUNEB_6___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__LOGEN_CAP_6___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6__LOGEN_CAP_6___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_6___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7 (0x005D719C) +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7___POR 0x6F8514FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__KVCO_7___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__IBIAS_7___POR 0x0F +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__LDO_VCO_VREG_7___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__VCO_CMTUNE_7___POR 0x14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__VCO_CMTUNEB_7___POR 0x14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__LOGEN_CAP_7___POR 0xFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__KVCO_7___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__KVCO_7___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__IBIAS_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__IBIAS_7___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__LDO_VCO_VREG_7___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__LDO_VCO_VREG_7___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__VCO_CMTUNE_7___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__VCO_CMTUNE_7___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__VCO_CMTUNEB_7___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__VCO_CMTUNEB_7___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__LOGEN_CAP_7___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7__LOGEN_CAP_7___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCOMUX_7___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0 (0x005D71A8) +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0___POR 0x10120F00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0__KVCO_TH0___POR 0x020 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0__KVCO_TH1___POR 0x048 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0__KVCO_TH2___POR 0x078 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0__KVCO_TH0___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0__KVCO_TH0___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0__KVCO_TH1___M 0x007FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0__KVCO_TH1___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0__KVCO_TH2___M 0x00003FE0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0__KVCO_TH2___S 5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0___M 0xFFFFFFE0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO0___S 5 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1 (0x005D71AC) +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1___POR 0x5C3EE7A0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1__KVCO_TH3___POR 0x0B8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1__KVCO_TH4___POR 0x0FB +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1__KVCO_TH5___POR 0x13D +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1__KVCO_TH3___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1__KVCO_TH3___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1__KVCO_TH4___M 0x007FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1__KVCO_TH4___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1__KVCO_TH5___M 0x00003FE0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1__KVCO_TH5___S 5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1___M 0xFFFFFFE0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO1___S 5 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2 (0x005D71B0) +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2___POR 0xBE800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_TH6___POR 0x17D +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_SEL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_GATE_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__HB_GATE_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__DTIM_GATE_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_TH6___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_TH6___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_SEL_OV___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_SEL_OV___S 7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_SEL_OVD___M 0x00000070 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_SEL_OVD___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_GATE_DIS___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__KVCO_GATE_DIS___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__HB_GATE_DIS___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__HB_GATE_DIS___S 2 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__DTIM_GATE_DIS___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2__DTIM_GATE_DIS___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2___M 0xFF8000FE +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_WL_SYNTH_LP5G_KVCO2___S 1 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3 (0x005D71B4) +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_KVCO___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_IBIAS___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_LDO_VCO_VREG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_VCO_CMTUNE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_VCO_CMTUNEB___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_LOGEN_CAP___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_KVCO___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_KVCO___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_IBIAS___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_IBIAS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_LDO_VCO_VREG___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_LDO_VCO_VREG___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_VCO_CMTUNE___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_VCO_CMTUNE___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_VCO_CMTUNEB___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_VCO_CMTUNEB___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_LOGEN_CAP___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3__RO_LOGEN_CAP___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO3___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4 (0x005D71B8) +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_KVCO_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_KVCO_6G___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_VCO_CMTUNE_6G___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_VCO_CMTUNEB_6G___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_KVCO_SEL___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_KVCO_SEL___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_KVCO_6G___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_KVCO_6G___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_VCO_CMTUNE_6G___M 0x03F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_VCO_CMTUNE_6G___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_VCO_CMTUNEB_6G___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4__RO_VCO_CMTUNEB_6G___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4___M 0xFFFFC000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_KVCO_RO_WL_SYNTH_LP5G_KVCO4___S 14 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0 (0x005D71C0) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0___POR 0x00068000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_CP_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_VCO_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_PFD_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_FBDIV_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_LOGEN_VREF___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_LOGEN_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_LOGEN_LEAK___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_CP_LOW_BIAS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_PINVC___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_PFD_C_FILT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_FBDIV_C_FILT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_CP_BYPASS___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_CP_BYPASS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_VCO_BYPASS___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_VCO_BYPASS___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_PFD_BYPASS___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_PFD_BYPASS___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_FBDIV_BYPASS___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_FBDIV_BYPASS___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_LOGEN_VREF___M 0x000E0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_LOGEN_VREF___S 17 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_LOGEN_BYPASS___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_LOGEN_BYPASS___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_LOGEN_LEAK___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_LOGEN_LEAK___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_CP_LOW_BIAS___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_CP_LOW_BIAS___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_PINVC___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_PINVC___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_PFD_C_FILT___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_PFD_C_FILT___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_FBDIV_C_FILT___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0__D_LDO_FBDIV_C_FILT___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0___M 0x11CFF800 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC0___S 11 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1 (0x005D71C4) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1___POR 0x0000301B +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1__D_CP_ISEL_IR25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1__D_SPARE_ISEL_IR25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1__D_SPARE_ISEL_IC25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1__D_CP_ISEL_IR25___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1__D_CP_ISEL_IR25___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1__D_SPARE_ISEL_IR25___M 0x00000038 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1__D_SPARE_ISEL_IR25___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1__D_SPARE_ISEL_IC25___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1__D_SPARE_ISEL_IC25___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1___M 0x0000703F +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2 (0x005D71C8) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2___POR 0x6D860000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_LDO_PFD_ISEL_IC25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_LDO_CP_ISEL_IC25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_VCMON_ISEL_IC25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_LDO_FBDIV_ISEL_IC25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_SEL_IC_IPT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_LDO_PFD_ISEL_IC25___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_LDO_PFD_ISEL_IC25___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_LDO_CP_ISEL_IC25___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_LDO_CP_ISEL_IC25___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_VCMON_ISEL_IC25___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_VCMON_ISEL_IC25___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_LDO_FBDIV_ISEL_IC25___M 0x000E0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_LDO_FBDIV_ISEL_IC25___S 17 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_SEL_IC_IPT___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2__D_SEL_IC_IPT___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2___M 0xFF8E0002 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC2___S 1 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3 (0x005D71CC) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3___POR 0x00300001 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_LB_LOBUF_DRVSTR___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_HB_LOGEN_NOTAIL_AMP_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_VCO_ISRC_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_PFD_HI_LK_MODE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_LB_LOBUF_DRVSTR___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_LB_LOBUF_DRVSTR___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_HB_LOGEN_NOTAIL_AMP_EN___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_HB_LOGEN_NOTAIL_AMP_EN___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_VCO_ISRC_BYPASS___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_VCO_ISRC_BYPASS___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_PFD_HI_LK_MODE___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3__D_PFD_HI_LK_MODE___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3___M 0x00308003 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC3___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4 (0x005D71D0) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__D_HB_VCO_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__SYN_ATB_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__D_VCO_TST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__D_HB_VARAC_BIAS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__D_HB_VCO_ATB_SEL___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__D_HB_VCO_ATB_SEL___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__SYN_ATB_SEL___M 0x03E00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__SYN_ATB_SEL___S 21 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__D_VCO_TST_EN___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__D_VCO_TST_EN___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__D_HB_VARAC_BIAS___M 0x000E0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4__D_HB_VARAC_BIAS___S 17 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4___M 0xE3FE0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC4___S 17 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC5 (0x005D71D4) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC5__D_SYN_SPARE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC5__D_SYN_SPARE_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC5__D_SYN_SPARE_0___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC5___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC5___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC6 (0x005D71D8) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC6__D_SYN_SPARE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC6__D_SYN_SPARE_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC6__D_SYN_SPARE_1___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC6___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC6___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7 (0x005D71DC) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7___POR 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__CLBS_LPF_VREF_ADJ_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_LO_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_LO_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_HI_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_HI_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__CLBS_LPF_VREF_ADJ_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__CLBS_LPF_VREF_ADJ_EN___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_LO_OV___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_LO_OV___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_LO_OVD___M 0x3C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_LO_OVD___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_HI_OV___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_HI_OV___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_HI_OVD___M 0x01E00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7__LPF_VREF_HI_OVD___S 21 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC7___S 21 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0 (0x005D71E0) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_RFCNT_SEL_BSC___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_PFDCP_CPI___POR 0x00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_CP_LEAKER___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_C2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_C3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_R1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_R2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_VREF_LO___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_VREF_HI___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_RFCNT_SEL_BSC___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_RFCNT_SEL_BSC___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_PFDCP_CPI___M 0x1F800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_PFDCP_CPI___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_CP_LEAKER___M 0x00780000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_CP_LEAKER___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_C2___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_C2___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_C3___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_C3___S 14 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_R1___M 0x00003800 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_R1___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_R2___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_R2___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_VREF_LO___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_VREF_LO___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_VREF_HI___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0__RO_LPF_VREF_HI___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC0___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC1 (0x005D71E4) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC1__RO_LPF_R2_6G___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC1__RO_BAND___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC1__RO_LPF_R2_6G___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC1__RO_LPF_R2_6G___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC1__RO_BAND___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC1__RO_BAND___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC1___M 0xE0000003 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_RO_WL_SYNTH_LP5G_AC1___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8 (0x005D71E8) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8___POR 0x1CA2B95C +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_VCOBUF_VREG___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_VCO_OTACUR___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_VCOBUF_OTACUR___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_CP_VREG___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_PFD_SEL___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_PFD_VREG___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_PFD_OTACUR___POR 0xC +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_FBDIV_SEL___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_FBDIV_VREG___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_FBDIV_OTACUR___POR 0xC +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_VCOBUF_VREG___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_VCOBUF_VREG___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_VCO_OTACUR___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_VCO_OTACUR___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_VCOBUF_OTACUR___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_VCOBUF_OTACUR___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_CP_VREG___M 0x003C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_CP_VREG___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_PFD_SEL___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_PFD_SEL___S 17 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_PFD_VREG___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_PFD_VREG___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_PFD_OTACUR___M 0x00001E00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_PFD_OTACUR___S 9 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_FBDIV_SEL___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_FBDIV_SEL___S 8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_FBDIV_VREG___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_FBDIV_VREG___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_FBDIV_OTACUR___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8__D_LDO_FBDIV_OTACUR___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC8___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9 (0x005D71EC) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9___POR 0x1C7C6000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_PFD_LKRON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_FBDIV_LKRON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_LOGEN_VREG___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_LOGEN_LKRON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_LOGEN_OTACUR___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_PFD_CAPSEL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_FBDIV_CAPSEL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_VCOBUF_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_PFD_MERGE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_VCO_ISEL_IC25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_CPLVL_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LOBIAS_BWRSEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_PFD_LKRON___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_PFD_LKRON___S 31 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_FBDIV_LKRON___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_FBDIV_LKRON___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_LOGEN_VREG___M 0x3C000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_LOGEN_VREG___S 26 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_LOGEN_LKRON___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_LOGEN_LKRON___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_LOGEN_OTACUR___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_LOGEN_OTACUR___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_PFD_CAPSEL___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_PFD_CAPSEL___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_FBDIV_CAPSEL___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_FBDIV_CAPSEL___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_VCOBUF_BYPASS___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_VCOBUF_BYPASS___S 17 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_PFD_MERGE___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_PFD_MERGE___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_VCO_ISEL_IC25___M 0x0000E000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_VCO_ISEL_IC25___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_CPLVL_BYPASS___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LDO_CPLVL_BYPASS___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LOBIAS_BWRSEL___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9__D_LOBIAS_BWRSEL___S 10 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC9___S 10 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10 (0x005D71F0) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10___POR 0x2210000F +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_DEGEN_PROG___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_LKR_DEGEN_PROG___POR 0x2 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_VCO_DUALCORE_6G___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_SUPFILT_RES___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_NBIAS_RSEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_PBIAS_RSEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_LDO_MERGE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_LPF_C1___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_VCO_DUALCORE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_DEGEN_PROG___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_DEGEN_PROG___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_LKR_DEGEN_PROG___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_LKR_DEGEN_PROG___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_VCO_DUALCORE_6G___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_VCO_DUALCORE_6G___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_SUPFILT_RES___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_SUPFILT_RES___S 18 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_NBIAS_RSEL___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_NBIAS_RSEL___S 17 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_PBIAS_RSEL___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_PBIAS_RSEL___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_LDO_MERGE___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_CP_LDO_MERGE___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_LPF_C1___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_LPF_C1___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_VCO_DUALCORE___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10__D_VCO_DUALCORE___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10___M 0xFF1F800F +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC10___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11 (0x005D71F4) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11___POR 0x03000018 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_HB_LOAMP_CUR___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LOBUF_DRV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_VREF_FILT_RES___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_BIAS_FILT_RES___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LB_VCO_VRES09___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LB_VCO_VRES07___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_CP_DRAINSW_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LB_VCOBUF_DUMLOAD_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_HB_LOGEN_DIV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_HB_LOAMP_CUR___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_HB_LOAMP_CUR___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LOBUF_DRV___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LOBUF_DRV___S 22 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_VREF_FILT_RES___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_VREF_FILT_RES___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_BIAS_FILT_RES___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_BIAS_FILT_RES___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LB_VCO_VRES09___M 0x00078000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LB_VCO_VRES09___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LB_VCO_VRES07___M 0x00007800 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LB_VCO_VRES07___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_CP_DRAINSW_EN___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_CP_DRAINSW_EN___S 4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LB_VCOBUF_DUMLOAD_EN___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_LB_VCOBUF_DUMLOAD_EN___S 3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_HB_LOGEN_DIV___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11__D_HB_LOGEN_DIV___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11___M 0x0FFFF81F +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC11___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12 (0x005D71F8) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12___POR 0x007FF7FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANK_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANK_OVD___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANKA_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANKA_OVD___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANK_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANK_OV___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANK_OVD___M 0x007FF000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANK_OVD___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANKA_OV___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANKA_OV___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANKA_OVD___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12__BANKA_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC12___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13 (0x005D71FC) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13___POR 0x007FF7FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANK_6G_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANK_6G_OVD___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANKA_6G_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANKA_6G_OVD___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANK_6G_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANK_6G_OV___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANK_6G_OVD___M 0x007FF000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANK_6G_OVD___S 12 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANKA_6G_OV___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANKA_6G_OV___S 11 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANKA_6G_OVD___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13__BANKA_6G_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_AC13___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0 (0x005D7240) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0___POR 0x091B0C00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__RFCNT_SEL_BSC_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__PFDCP_CPI_0___POR 0x12 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__CP_LEAKER_0___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_C2_0___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_C3_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_R1_0___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_R2_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__RFCNT_SEL_BSC_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__RFCNT_SEL_BSC_0___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__PFDCP_CPI_0___M 0x1F800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__PFDCP_CPI_0___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__CP_LEAKER_0___M 0x00780000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__CP_LEAKER_0___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_C2_0___M 0x00078000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_C2_0___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_C3_0___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_C3_0___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_R1_0___M 0x00001E00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_R1_0___S 9 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_R2_0___M 0x000001C0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0__LPF_R2_0___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0___M 0xFFFFFFC0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_0___S 6 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0 (0x005D7244) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0___POR 0x67850000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_LO_0___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_HI_0___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_LO_CLBS_0___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_HI_CLBS_0___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_LO_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_LO_0___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_HI_0___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_HI_0___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_LO_CLBS_0___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_LO_CLBS_0___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_HI_CLBS_0___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0__LPF_VREF_HI_CLBS_0___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_0___S 16 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1 (0x005D7248) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1___POR 0x212B8640 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__RFCNT_SEL_BSC_1___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__PFDCP_CPI_1___POR 0x02 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__CP_LEAKER_1___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_C2_1___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_C3_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_R1_1___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_R2_1___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__RFCNT_SEL_BSC_1___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__RFCNT_SEL_BSC_1___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__PFDCP_CPI_1___M 0x1F800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__PFDCP_CPI_1___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__CP_LEAKER_1___M 0x00780000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__CP_LEAKER_1___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_C2_1___M 0x00078000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_C2_1___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_C3_1___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_C3_1___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_R1_1___M 0x00001E00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_R1_1___S 9 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_R2_1___M 0x000001C0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1__LPF_R2_1___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1___M 0xFFFFFFC0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_1___S 6 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1 (0x005D724C) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1___POR 0x38410000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_LO_1___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_HI_1___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_LO_CLBS_1___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_HI_CLBS_1___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_LO_1___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_LO_1___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_HI_1___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_HI_1___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_LO_CLBS_1___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_LO_CLBS_1___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_HI_CLBS_1___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1__LPF_VREF_HI_CLBS_1___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_1___S 16 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2 (0x005D7250) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2___POR 0x091B0C40 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__RFCNT_SEL_BSC_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__PFDCP_CPI_2___POR 0x12 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__CP_LEAKER_2___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_C2_2___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_C3_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_R1_2___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_R2_2___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__RFCNT_SEL_BSC_2___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__RFCNT_SEL_BSC_2___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__PFDCP_CPI_2___M 0x1F800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__PFDCP_CPI_2___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__CP_LEAKER_2___M 0x00780000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__CP_LEAKER_2___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_C2_2___M 0x00078000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_C2_2___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_C3_2___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_C3_2___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_R1_2___M 0x00001E00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_R1_2___S 9 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_R2_2___M 0x000001C0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2__LPF_R2_2___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2___M 0xFFFFFFC0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_2___S 6 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2 (0x005D7254) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2___POR 0x67850000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_LO_2___POR 0x6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_HI_2___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_LO_CLBS_2___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_HI_CLBS_2___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_LO_2___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_LO_2___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_HI_2___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_HI_2___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_LO_CLBS_2___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_LO_CLBS_2___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_HI_CLBS_2___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2__LPF_VREF_HI_CLBS_2___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_2___S 16 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3 (0x005D7258) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3___POR 0x212B8640 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__RFCNT_SEL_BSC_3___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__PFDCP_CPI_3___POR 0x02 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__CP_LEAKER_3___POR 0x5 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_C2_3___POR 0x7 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_C3_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_R1_3___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_R2_3___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__RFCNT_SEL_BSC_3___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__RFCNT_SEL_BSC_3___S 29 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__PFDCP_CPI_3___M 0x1F800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__PFDCP_CPI_3___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__CP_LEAKER_3___M 0x00780000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__CP_LEAKER_3___S 19 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_C2_3___M 0x00078000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_C2_3___S 15 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_C3_3___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_C3_3___S 13 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_R1_3___M 0x00001E00 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_R1_3___S 9 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_R2_3___M 0x000001C0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3__LPF_R2_3___S 6 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3___M 0xFFFFFFC0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX_3___S 6 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3 (0x005D725C) +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3___POR 0x38410000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_LO_3___POR 0x3 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_HI_3___POR 0x8 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_LO_CLBS_3___POR 0x4 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_HI_CLBS_3___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_LO_3___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_LO_3___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_HI_3___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_HI_3___S 24 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_LO_CLBS_3___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_LO_CLBS_3___S 20 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_HI_CLBS_3___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3__LPF_VREF_HI_CLBS_3___S 16 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_AC_WL_SYNTH_LP5G_BANDMUX1_3___S 16 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL (0x005D7280) +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL___POR 0x10000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_REFBUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_REFDIV_EN_OVS___POR 0x1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_FLAG_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_FLAG_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_FLAG_RESET_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PSYNC_START___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PCAL_START___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_REFBUF_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_REFBUF_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_REFDIV_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_REFDIV_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_FLAG_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_FLAG_OV___S 27 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_FLAG_OVD___M 0x06000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_FLAG_OVD___S 25 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_FLAG_RESET_OVS___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PAL_FLAG_RESET_OVS___S 23 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PSYNC_START___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PSYNC_START___S 1 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PCAL_START___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL__PCAL_START___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL___M 0xFF800003 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_WL_SYNTH_LP5G_PAL___S 0 + +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_RO_WL_SYNTH_LP5G_LO (0x005D7288) +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_RO_WL_SYNTH_LP5G_LO___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_RO_WL_SYNTH_LP5G_LO___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_RO_WL_SYNTH_LP5G_LO__RO_LO_FREQ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_RO_WL_SYNTH_LP5G_LO__RO_LO_FREQ___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_RO_WL_SYNTH_LP5G_LO__RO_LO_FREQ___S 0 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_RO_WL_SYNTH_LP5G_LO___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_SYNTH2_LO_RO_WL_SYNTH_LP5G_LO___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_00 (0x005D7C00) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_00___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_00___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_00__DRM_REG_00___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_00__DRM_REG_00___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_00__DRM_REG_00___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_00___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_00___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_01 (0x005D7C04) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_01___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_01___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_01__DRM_REG_01___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_01__DRM_REG_01___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_01__DRM_REG_01___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_01___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_01___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_02 (0x005D7C08) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_02___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_02___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_02__DRM_REG_02___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_02__DRM_REG_02___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_02__DRM_REG_02___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_02___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_02___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_03 (0x005D7C0C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_03___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_03___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_03__DRM_REG_03___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_03__DRM_REG_03___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_03__DRM_REG_03___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_03___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_03___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_04 (0x005D7C10) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_04___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_04___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_04__DRM_REG_04___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_04__DRM_REG_04___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_04__DRM_REG_04___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_04___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_04___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_05 (0x005D7C14) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_05___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_05___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_05__DRM_REG_05___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_05__DRM_REG_05___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_05__DRM_REG_05___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_05___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_05___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_06 (0x005D7C18) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_06___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_06___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_06__DRM_REG_06___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_06__DRM_REG_06___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_06__DRM_REG_06___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_06___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_06___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_07 (0x005D7C1C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_07___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_07___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_07__DRM_REG_07___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_07__DRM_REG_07___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_07__DRM_REG_07___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_07___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_07___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_08 (0x005D7C20) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_08___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_08___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_08__DRM_REG_08___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_08__DRM_REG_08___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_08__DRM_REG_08___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_08___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_08___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_09 (0x005D7C24) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_09___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_09___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_09__DRM_REG_09___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_09__DRM_REG_09___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_09__DRM_REG_09___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_09___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_09___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_10 (0x005D7C28) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_10__DRM_REG_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_10__DRM_REG_10___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_10__DRM_REG_10___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_10___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_10___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_11 (0x005D7C2C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_11__DRM_REG_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_11__DRM_REG_11___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_11__DRM_REG_11___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_11___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_11___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_12 (0x005D7C30) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_12__DRM_REG_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_12__DRM_REG_12___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_12__DRM_REG_12___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_12___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_12___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_13 (0x005D7C34) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_13__DRM_REG_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_13__DRM_REG_13___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_13__DRM_REG_13___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_13___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_13___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_14 (0x005D7C38) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_14__DRM_REG_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_14__DRM_REG_14___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_14__DRM_REG_14___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_14___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_14___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_15 (0x005D7C3C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_15__DRM_REG_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_15__DRM_REG_15___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_15__DRM_REG_15___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_15___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_15___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_16 (0x005D7C40) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_16___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_16__DRM_REG_16___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_16__DRM_REG_16___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_16__DRM_REG_16___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_16___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_16___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_17 (0x005D7C44) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_17___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_17__DRM_REG_17___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_17__DRM_REG_17___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_17__DRM_REG_17___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_17___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_17___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_18 (0x005D7C48) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_18___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_18__DRM_REG_18___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_18__DRM_REG_18___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_18__DRM_REG_18___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_18___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_18___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_19 (0x005D7C4C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_19___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_19__DRM_REG_19___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_19__DRM_REG_19___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_19__DRM_REG_19___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_19___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_19___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_20 (0x005D7C50) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_20___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_20__DRM_REG_20___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_20__DRM_REG_20___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_20__DRM_REG_20___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_20___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_20___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_21 (0x005D7C54) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_21___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_21__DRM_REG_21___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_21__DRM_REG_21___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_21__DRM_REG_21___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_21___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_21___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_22 (0x005D7C58) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_22___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_22__DRM_REG_22___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_22__DRM_REG_22___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_22__DRM_REG_22___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_22___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_22___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_23 (0x005D7C5C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_23___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_23__DRM_REG_23___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_23__DRM_REG_23___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_23__DRM_REG_23___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_23___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_23___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_24 (0x005D7C60) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_24___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_24__DRM_REG_24___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_24__DRM_REG_24___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_24__DRM_REG_24___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_24___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_24___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_25 (0x005D7C64) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_25___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_25__DRM_REG_25___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_25__DRM_REG_25___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_25__DRM_REG_25___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_25___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_25___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_26 (0x005D7C68) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_26___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_26__DRM_REG_26___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_26__DRM_REG_26___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_26__DRM_REG_26___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_26___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_26___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_27 (0x005D7C6C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_27___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_27__DRM_REG_27___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_27__DRM_REG_27___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_27__DRM_REG_27___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_27___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_27___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_28 (0x005D7C70) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_28___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_28__DRM_REG_28___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_28__DRM_REG_28___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_28__DRM_REG_28___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_28___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_28___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_29 (0x005D7C74) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_29___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_29__DRM_REG_29___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_29__DRM_REG_29___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_29__DRM_REG_29___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_29___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_29___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_30 (0x005D7C78) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_30___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_30__DRM_REG_30___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_30__DRM_REG_30___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_30__DRM_REG_30___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_30___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_30___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_31 (0x005D7C7C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_31___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_31__DRM_REG_31___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_31__DRM_REG_31___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_31__DRM_REG_31___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_31___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_31___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_32 (0x005D7C80) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_32___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_32___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_32__DRM_REG_32___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_32__DRM_REG_32___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_32__DRM_REG_32___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_32___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_32___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_33 (0x005D7C84) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_33___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_33___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_33__DRM_REG_33___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_33__DRM_REG_33___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_33__DRM_REG_33___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_33___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_33___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_34 (0x005D7C88) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_34___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_34___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_34__DRM_REG_34___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_34__DRM_REG_34___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_34__DRM_REG_34___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_34___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_34___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_35 (0x005D7C8C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_35___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_35___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_35__DRM_REG_35___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_35__DRM_REG_35___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_35__DRM_REG_35___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_35___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_35___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_36 (0x005D7C90) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_36___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_36___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_36__DRM_REG_36___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_36__DRM_REG_36___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_36__DRM_REG_36___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_36___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_36___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_37 (0x005D7C94) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_37___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_37___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_37__DRM_REG_37___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_37__DRM_REG_37___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_37__DRM_REG_37___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_37___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_37___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_38 (0x005D7C98) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_38___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_38___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_38__DRM_REG_38___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_38__DRM_REG_38___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_38__DRM_REG_38___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_38___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_38___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_39 (0x005D7C9C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_39___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_39___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_39__DRM_REG_39___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_39__DRM_REG_39___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_39__DRM_REG_39___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_39___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_39___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_40 (0x005D7CA0) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_40___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_40___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_40__DRM_REG_40___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_40__DRM_REG_40___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_40__DRM_REG_40___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_40___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_40___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_41 (0x005D7CA4) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_41___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_41___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_41__DRM_REG_41___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_41__DRM_REG_41___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_41__DRM_REG_41___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_41___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_41___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_42 (0x005D7CA8) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_42___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_42___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_42__DRM_REG_42___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_42__DRM_REG_42___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_42__DRM_REG_42___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_42___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_42___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_43 (0x005D7CAC) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_43___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_43___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_43__DRM_REG_43___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_43__DRM_REG_43___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_43__DRM_REG_43___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_43___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_43___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_44 (0x005D7CB0) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_44___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_44___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_44__DRM_REG_44___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_44__DRM_REG_44___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_44__DRM_REG_44___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_44___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_44___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_45 (0x005D7CB4) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_45___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_45___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_45__DRM_REG_45___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_45__DRM_REG_45___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_45__DRM_REG_45___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_45___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_45___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_46 (0x005D7CB8) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_46___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_46___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_46__DRM_REG_46___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_46__DRM_REG_46___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_46__DRM_REG_46___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_46___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_46___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_47 (0x005D7CBC) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_47___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_47___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_47__DRM_REG_47___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_47__DRM_REG_47___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_47__DRM_REG_47___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_47___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_47___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_48 (0x005D7CC0) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_48___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_48___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_48__DRM_REG_48___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_48__DRM_REG_48___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_48__DRM_REG_48___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_48___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_48___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_49 (0x005D7CC4) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_49___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_49___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_49__DRM_REG_49___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_49__DRM_REG_49___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_49__DRM_REG_49___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_49___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_49___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_50 (0x005D7CC8) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_50___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_50___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_50__DRM_REG_50___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_50__DRM_REG_50___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_50__DRM_REG_50___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_50___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_50___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_51 (0x005D7CCC) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_51___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_51___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_51__DRM_REG_51___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_51__DRM_REG_51___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_51__DRM_REG_51___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_51___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_51___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_52 (0x005D7CD0) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_52___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_52___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_52__DRM_REG_52___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_52__DRM_REG_52___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_52__DRM_REG_52___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_52___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_52___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_53 (0x005D7CD4) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_53___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_53___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_53__DRM_REG_53___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_53__DRM_REG_53___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_53__DRM_REG_53___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_53___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_53___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_54 (0x005D7CD8) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_54___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_54___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_54__DRM_REG_54___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_54__DRM_REG_54___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_54__DRM_REG_54___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_54___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_54___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_55 (0x005D7CDC) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_55___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_55___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_55__DRM_REG_55___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_55__DRM_REG_55___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_55__DRM_REG_55___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_55___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_55___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_56 (0x005D7CE0) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_56___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_56___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_56__DRM_REG_56___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_56__DRM_REG_56___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_56__DRM_REG_56___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_56___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_56___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_57 (0x005D7CE4) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_57___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_57___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_57__DRM_REG_57___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_57__DRM_REG_57___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_57__DRM_REG_57___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_57___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_57___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_58 (0x005D7CE8) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_58___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_58___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_58__DRM_REG_58___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_58__DRM_REG_58___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_58__DRM_REG_58___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_58___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_58___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_59 (0x005D7CEC) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_59___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_59___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_59__DRM_REG_59___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_59__DRM_REG_59___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_59__DRM_REG_59___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_59___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_59___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_60 (0x005D7CF0) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_60___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_60___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_60__DRM_REG_60___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_60__DRM_REG_60___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_60__DRM_REG_60___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_60___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_60___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_61 (0x005D7CF4) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_61___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_61___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_61__DRM_REG_61___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_61__DRM_REG_61___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_61__DRM_REG_61___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_61___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_61___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_62 (0x005D7CF8) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_62___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_62___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_62__DRM_REG_62___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_62__DRM_REG_62___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_62__DRM_REG_62___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_62___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_62___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_63 (0x005D7CFC) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_63___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_63___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_63__DRM_REG_63___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_63__DRM_REG_63___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_63__DRM_REG_63___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_63___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_63___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_64 (0x005D7D00) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_64___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_64___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_64__DRM_REG_64___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_64__DRM_REG_64___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_64__DRM_REG_64___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_64___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_64___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_65 (0x005D7D04) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_65___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_65___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_65__DRM_REG_65___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_65__DRM_REG_65___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_65__DRM_REG_65___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_65___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_65___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_66 (0x005D7D08) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_66___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_66___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_66__DRM_REG_66___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_66__DRM_REG_66___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_66__DRM_REG_66___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_66___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_66___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_67 (0x005D7D0C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_67___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_67___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_67__DRM_REG_67___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_67__DRM_REG_67___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_67__DRM_REG_67___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_67___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_67___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_68 (0x005D7D10) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_68___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_68___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_68__DRM_REG_68___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_68__DRM_REG_68___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_68__DRM_REG_68___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_68___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_68___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_69 (0x005D7D14) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_69___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_69___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_69__DRM_REG_69___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_69__DRM_REG_69___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_69__DRM_REG_69___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_69___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_69___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_70 (0x005D7D18) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_70___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_70___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_70__DRM_REG_70___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_70__DRM_REG_70___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_70__DRM_REG_70___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_70___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_70___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_71 (0x005D7D1C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_71___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_71___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_71__DRM_REG_71___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_71__DRM_REG_71___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_71__DRM_REG_71___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_71___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_71___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_72 (0x005D7D20) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_72___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_72___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_72__DRM_REG_72___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_72__DRM_REG_72___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_72__DRM_REG_72___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_72___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_72___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_73 (0x005D7D24) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_73___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_73___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_73__DRM_REG_73___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_73__DRM_REG_73___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_73__DRM_REG_73___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_73___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_73___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_74 (0x005D7D28) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_74___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_74___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_74__DRM_REG_74___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_74__DRM_REG_74___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_74__DRM_REG_74___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_74___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_74___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_75 (0x005D7D2C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_75___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_75___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_75__DRM_REG_75___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_75__DRM_REG_75___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_75__DRM_REG_75___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_75___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_75___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_76 (0x005D7D30) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_76___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_76___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_76__DRM_REG_76___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_76__DRM_REG_76___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_76__DRM_REG_76___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_76___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_76___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_77 (0x005D7D34) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_77___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_77___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_77__DRM_REG_77___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_77__DRM_REG_77___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_77__DRM_REG_77___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_77___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_77___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_78 (0x005D7D38) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_78___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_78___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_78__DRM_REG_78___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_78__DRM_REG_78___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_78__DRM_REG_78___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_78___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_78___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_79 (0x005D7D3C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_79___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_79___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_79__DRM_REG_79___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_79__DRM_REG_79___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_79__DRM_REG_79___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_79___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_79___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_80 (0x005D7D40) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_80___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_80___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_80__DRM_REG_80___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_80__DRM_REG_80___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_80__DRM_REG_80___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_80___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_80___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_81 (0x005D7D44) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_81___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_81___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_81__DRM_REG_81___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_81__DRM_REG_81___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_81__DRM_REG_81___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_81___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_81___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_82 (0x005D7D48) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_82___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_82___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_82__DRM_REG_82___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_82__DRM_REG_82___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_82__DRM_REG_82___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_82___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_82___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_83 (0x005D7D4C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_83___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_83___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_83__DRM_REG_83___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_83__DRM_REG_83___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_83__DRM_REG_83___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_83___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_83___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_84 (0x005D7D50) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_84___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_84___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_84__DRM_REG_84___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_84__DRM_REG_84___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_84__DRM_REG_84___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_84___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_84___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_85 (0x005D7D54) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_85___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_85___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_85__DRM_REG_85___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_85__DRM_REG_85___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_85__DRM_REG_85___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_85___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_85___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_86 (0x005D7D58) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_86___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_86___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_86__DRM_REG_86___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_86__DRM_REG_86___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_86__DRM_REG_86___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_86___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_86___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_87 (0x005D7D5C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_87___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_87___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_87__DRM_REG_87___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_87__DRM_REG_87___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_87__DRM_REG_87___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_87___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_87___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_88 (0x005D7D60) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_88___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_88___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_88__DRM_REG_88___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_88__DRM_REG_88___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_88__DRM_REG_88___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_88___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_88___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_89 (0x005D7D64) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_89___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_89___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_89__DRM_REG_89___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_89__DRM_REG_89___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_89__DRM_REG_89___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_89___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_89___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_90 (0x005D7D68) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_90___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_90___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_90__DRM_REG_90___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_90__DRM_REG_90___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_90__DRM_REG_90___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_90___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_90___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_91 (0x005D7D6C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_91___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_91___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_91__DRM_REG_91___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_91__DRM_REG_91___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_91__DRM_REG_91___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_91___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_91___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_92 (0x005D7D70) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_92___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_92___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_92__DRM_REG_92___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_92__DRM_REG_92___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_92__DRM_REG_92___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_92___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_92___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_93 (0x005D7D74) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_93___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_93___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_93__DRM_REG_93___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_93__DRM_REG_93___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_93__DRM_REG_93___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_93___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_93___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_94 (0x005D7D78) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_94___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_94___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_94__DRM_REG_94___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_94__DRM_REG_94___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_94__DRM_REG_94___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_94___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_94___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_95 (0x005D7D7C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_95___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_95___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_95__DRM_REG_95___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_95__DRM_REG_95___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_95__DRM_REG_95___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_95___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_95___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_96 (0x005D7D80) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_96___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_96___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_96__DRM_REG_96___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_96__DRM_REG_96___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_96__DRM_REG_96___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_96___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_96___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_97 (0x005D7D84) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_97___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_97___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_97__DRM_REG_97___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_97__DRM_REG_97___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_97__DRM_REG_97___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_97___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_97___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_98 (0x005D7D88) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_98___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_98___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_98__DRM_REG_98___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_98__DRM_REG_98___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_98__DRM_REG_98___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_98___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_98___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_99 (0x005D7D8C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_99___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_99___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_99__DRM_REG_99___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_99__DRM_REG_99___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_99__DRM_REG_99___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_99___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_99___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_100 (0x005D7D90) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_100___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_100___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_100__DRM_REG_100___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_100__DRM_REG_100___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_100__DRM_REG_100___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_100___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_100___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_101 (0x005D7D94) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_101___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_101___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_101__DRM_REG_101___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_101__DRM_REG_101___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_101__DRM_REG_101___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_101___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_101___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_102 (0x005D7D98) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_102___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_102___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_102__DRM_REG_102___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_102__DRM_REG_102___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_102__DRM_REG_102___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_102___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_102___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_103 (0x005D7D9C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_103___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_103___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_103__DRM_REG_103___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_103__DRM_REG_103___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_103__DRM_REG_103___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_103___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_103___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_104 (0x005D7DA0) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_104___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_104___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_104__DRM_REG_104___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_104__DRM_REG_104___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_104__DRM_REG_104___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_104___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_104___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_105 (0x005D7DA4) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_105___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_105___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_105__DRM_REG_105___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_105__DRM_REG_105___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_105__DRM_REG_105___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_105___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_105___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_106 (0x005D7DA8) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_106___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_106___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_106__DRM_REG_106___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_106__DRM_REG_106___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_106__DRM_REG_106___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_106___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_106___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_107 (0x005D7DAC) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_107___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_107___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_107__DRM_REG_107___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_107__DRM_REG_107___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_107__DRM_REG_107___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_107___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_107___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_108 (0x005D7DB0) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_108___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_108___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_108__DRM_REG_108___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_108__DRM_REG_108___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_108__DRM_REG_108___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_108___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_108___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_109 (0x005D7DB4) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_109___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_109___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_109__DRM_REG_109___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_109__DRM_REG_109___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_109__DRM_REG_109___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_109___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_109___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_110 (0x005D7DB8) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_110___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_110___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_110__DRM_REG_110___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_110__DRM_REG_110___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_110__DRM_REG_110___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_110___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_110___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_111 (0x005D7DBC) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_111___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_111___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_111__DRM_REG_111___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_111__DRM_REG_111___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_111__DRM_REG_111___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_111___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_111___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_112 (0x005D7DC0) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_112___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_112___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_112__DRM_REG_112___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_112__DRM_REG_112___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_112__DRM_REG_112___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_112___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_112___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_113 (0x005D7DC4) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_113___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_113___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_113__DRM_REG_113___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_113__DRM_REG_113___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_113__DRM_REG_113___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_113___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_113___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_114 (0x005D7DC8) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_114___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_114___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_114__DRM_REG_114___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_114__DRM_REG_114___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_114__DRM_REG_114___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_114___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_114___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_115 (0x005D7DCC) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_115___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_115___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_115__DRM_REG_115___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_115__DRM_REG_115___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_115__DRM_REG_115___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_115___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_115___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_116 (0x005D7DD0) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_116___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_116___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_116__DRM_REG_116___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_116__DRM_REG_116___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_116__DRM_REG_116___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_116___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_116___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_117 (0x005D7DD4) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_117___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_117___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_117__DRM_REG_117___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_117__DRM_REG_117___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_117__DRM_REG_117___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_117___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_117___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_118 (0x005D7DD8) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_118___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_118___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_118__DRM_REG_118___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_118__DRM_REG_118___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_118__DRM_REG_118___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_118___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_118___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_119 (0x005D7DDC) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_119___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_119___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_119__DRM_REG_119___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_119__DRM_REG_119___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_119__DRM_REG_119___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_119___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_119___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_120 (0x005D7DE0) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_120___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_120___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_120__DRM_REG_120___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_120__DRM_REG_120___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_120__DRM_REG_120___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_120___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_120___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_121 (0x005D7DE4) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_121___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_121___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_121__DRM_REG_121___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_121__DRM_REG_121___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_121__DRM_REG_121___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_121___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_121___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_122 (0x005D7DE8) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_122___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_122___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_122__DRM_REG_122___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_122__DRM_REG_122___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_122__DRM_REG_122___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_122___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_122___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_123 (0x005D7DEC) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_123___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_123___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_123__DRM_REG_123___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_123__DRM_REG_123___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_123__DRM_REG_123___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_123___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_123___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_124 (0x005D7DF0) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_124___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_124___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_124__DRM_REG_124___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_124__DRM_REG_124___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_124__DRM_REG_124___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_124___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_124___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_125 (0x005D7DF4) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_125___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_125___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_125__DRM_REG_125___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_125__DRM_REG_125___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_125__DRM_REG_125___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_125___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_125___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_126 (0x005D7DF8) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_126___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_126___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_126__DRM_REG_126___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_126__DRM_REG_126___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_126__DRM_REG_126___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_126___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_126___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_127 (0x005D7DFC) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_127___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_127___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_127__DRM_REG_127___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_127__DRM_REG_127___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_127__DRM_REG_127___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_127___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_127___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_128 (0x005D7E00) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_128___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_128___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_128__DRM_REG_128___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_128__DRM_REG_128___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_128__DRM_REG_128___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_128___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_128___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_129 (0x005D7E04) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_129___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_129___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_129__DRM_REG_129___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_129__DRM_REG_129___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_129__DRM_REG_129___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_129___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_129___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_130 (0x005D7E08) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_130___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_130___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_130__DRM_REG_130___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_130__DRM_REG_130___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_130__DRM_REG_130___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_130___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_130___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_131 (0x005D7E0C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_131___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_131___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_131__DRM_REG_131___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_131__DRM_REG_131___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_131__DRM_REG_131___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_131___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_131___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_132 (0x005D7E10) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_132___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_132___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_132__DRM_REG_132___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_132__DRM_REG_132___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_132__DRM_REG_132___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_132___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_132___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_133 (0x005D7E14) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_133___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_133___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_133__DRM_REG_133___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_133__DRM_REG_133___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_133__DRM_REG_133___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_133___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_133___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_134 (0x005D7E18) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_134___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_134___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_134__DRM_REG_134___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_134__DRM_REG_134___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_134__DRM_REG_134___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_134___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_134___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_135 (0x005D7E1C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_135___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_135___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_135__DRM_REG_135___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_135__DRM_REG_135___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_135__DRM_REG_135___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_135___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_135___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_136 (0x005D7E20) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_136___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_136___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_136__DRM_REG_136___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_136__DRM_REG_136___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_136__DRM_REG_136___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_136___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_136___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_137 (0x005D7E24) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_137___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_137___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_137__DRM_REG_137___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_137__DRM_REG_137___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_137__DRM_REG_137___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_137___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_137___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_138 (0x005D7E28) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_138___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_138___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_138__DRM_REG_138___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_138__DRM_REG_138___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_138__DRM_REG_138___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_138___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_138___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_139 (0x005D7E2C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_139___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_139___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_139__DRM_REG_139___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_139__DRM_REG_139___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_139__DRM_REG_139___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_139___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_139___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_140 (0x005D7E30) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_140___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_140___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_140__DRM_REG_140___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_140__DRM_REG_140___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_140__DRM_REG_140___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_140___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_140___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_141 (0x005D7E34) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_141___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_141___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_141__DRM_REG_141___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_141__DRM_REG_141___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_141__DRM_REG_141___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_141___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_141___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_142 (0x005D7E38) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_142___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_142___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_142__DRM_REG_142___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_142__DRM_REG_142___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_142__DRM_REG_142___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_142___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_142___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_143 (0x005D7E3C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_143___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_143___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_143__DRM_REG_143___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_143__DRM_REG_143___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_143__DRM_REG_143___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_143___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_143___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_144 (0x005D7E40) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_144___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_144___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_144__DRM_REG_144___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_144__DRM_REG_144___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_144__DRM_REG_144___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_144___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_144___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_145 (0x005D7E44) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_145___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_145___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_145__DRM_REG_145___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_145__DRM_REG_145___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_145__DRM_REG_145___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_145___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_145___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_146 (0x005D7E48) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_146___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_146___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_146__DRM_REG_146___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_146__DRM_REG_146___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_146__DRM_REG_146___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_146___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_146___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_147 (0x005D7E4C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_147___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_147___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_147__DRM_REG_147___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_147__DRM_REG_147___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_147__DRM_REG_147___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_147___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_147___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_148 (0x005D7E50) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_148___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_148___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_148__DRM_REG_148___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_148__DRM_REG_148___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_148__DRM_REG_148___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_148___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_148___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_149 (0x005D7E54) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_149___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_149___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_149__DRM_REG_149___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_149__DRM_REG_149___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_149__DRM_REG_149___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_149___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_149___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_150 (0x005D7E58) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_150___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_150___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_150__DRM_REG_150___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_150__DRM_REG_150___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_150__DRM_REG_150___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_150___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_150___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_151 (0x005D7E5C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_151___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_151___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_151__DRM_REG_151___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_151__DRM_REG_151___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_151__DRM_REG_151___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_151___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_151___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_152 (0x005D7E60) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_152___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_152___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_152__DRM_REG_152___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_152__DRM_REG_152___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_152__DRM_REG_152___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_152___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_152___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_153 (0x005D7E64) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_153___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_153___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_153__DRM_REG_153___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_153__DRM_REG_153___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_153__DRM_REG_153___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_153___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_153___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_154 (0x005D7E68) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_154___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_154___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_154__DRM_REG_154___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_154__DRM_REG_154___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_154__DRM_REG_154___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_154___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_154___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_155 (0x005D7E6C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_155___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_155___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_155__DRM_REG_155___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_155__DRM_REG_155___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_155__DRM_REG_155___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_155___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_155___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_156 (0x005D7E70) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_156___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_156___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_156__DRM_REG_156___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_156__DRM_REG_156___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_156__DRM_REG_156___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_156___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_156___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_157 (0x005D7E74) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_157___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_157___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_157__DRM_REG_157___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_157__DRM_REG_157___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_157__DRM_REG_157___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_157___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_157___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_158 (0x005D7E78) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_158___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_158___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_158__DRM_REG_158___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_158__DRM_REG_158___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_158__DRM_REG_158___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_158___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_158___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_159 (0x005D7E7C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_159___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_159___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_159__DRM_REG_159___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_159__DRM_REG_159___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_159__DRM_REG_159___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_159___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_159___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_160 (0x005D7E80) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_160___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_160___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_160__DRM_REG_160___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_160__DRM_REG_160___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_160__DRM_REG_160___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_160___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_160___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_161 (0x005D7E84) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_161___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_161___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_161__DRM_REG_161___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_161__DRM_REG_161___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_161__DRM_REG_161___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_161___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_161___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_162 (0x005D7E88) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_162___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_162___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_162__DRM_REG_162___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_162__DRM_REG_162___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_162__DRM_REG_162___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_162___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_162___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_163 (0x005D7E8C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_163___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_163___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_163__DRM_REG_163___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_163__DRM_REG_163___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_163__DRM_REG_163___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_163___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_163___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_164 (0x005D7E90) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_164___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_164___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_164__DRM_REG_164___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_164__DRM_REG_164___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_164__DRM_REG_164___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_164___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_164___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_165 (0x005D7E94) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_165___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_165___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_165__DRM_REG_165___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_165__DRM_REG_165___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_165__DRM_REG_165___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_165___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_165___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_166 (0x005D7E98) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_166___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_166___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_166__DRM_REG_166___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_166__DRM_REG_166___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_166__DRM_REG_166___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_166___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_166___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_167 (0x005D7E9C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_167___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_167___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_167__DRM_REG_167___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_167__DRM_REG_167___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_167__DRM_REG_167___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_167___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_167___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_168 (0x005D7EA0) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_168___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_168___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_168__DRM_REG_168___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_168__DRM_REG_168___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_168__DRM_REG_168___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_168___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_168___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_169 (0x005D7EA4) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_169___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_169___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_169__DRM_REG_169___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_169__DRM_REG_169___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_169__DRM_REG_169___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_169___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_169___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_170 (0x005D7EA8) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_170___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_170___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_170__DRM_REG_170___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_170__DRM_REG_170___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_170__DRM_REG_170___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_170___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_170___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_171 (0x005D7EAC) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_171___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_171___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_171__DRM_REG_171___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_171__DRM_REG_171___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_171__DRM_REG_171___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_171___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_171___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_172 (0x005D7EB0) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_172___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_172___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_172__DRM_REG_172___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_172__DRM_REG_172___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_172__DRM_REG_172___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_172___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_172___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_173 (0x005D7EB4) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_173___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_173___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_173__DRM_REG_173___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_173__DRM_REG_173___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_173__DRM_REG_173___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_173___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_173___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_174 (0x005D7EB8) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_174___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_174___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_174__DRM_REG_174___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_174__DRM_REG_174___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_174__DRM_REG_174___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_174___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_174___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_175 (0x005D7EBC) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_175___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_175___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_175__DRM_REG_175___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_175__DRM_REG_175___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_175__DRM_REG_175___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_175___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_175___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_176 (0x005D7EC0) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_176___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_176___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_176__DRM_REG_176___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_176__DRM_REG_176___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_176__DRM_REG_176___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_176___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_176___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_177 (0x005D7EC4) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_177___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_177___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_177__DRM_REG_177___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_177__DRM_REG_177___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_177__DRM_REG_177___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_177___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_177___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_178 (0x005D7EC8) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_178___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_178___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_178__DRM_REG_178___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_178__DRM_REG_178___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_178__DRM_REG_178___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_178___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_178___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_179 (0x005D7ECC) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_179___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_179___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_179__DRM_REG_179___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_179__DRM_REG_179___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_179__DRM_REG_179___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_179___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_179___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_180 (0x005D7ED0) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_180___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_180___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_180__DRM_REG_180___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_180__DRM_REG_180___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_180__DRM_REG_180___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_180___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_180___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_181 (0x005D7ED4) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_181___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_181___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_181__DRM_REG_181___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_181__DRM_REG_181___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_181__DRM_REG_181___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_181___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_181___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_182 (0x005D7ED8) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_182___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_182___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_182__DRM_REG_182___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_182__DRM_REG_182___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_182__DRM_REG_182___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_182___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_182___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_183 (0x005D7EDC) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_183___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_183___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_183__DRM_REG_183___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_183__DRM_REG_183___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_183__DRM_REG_183___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_183___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_183___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_184 (0x005D7EE0) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_184___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_184___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_184__DRM_REG_184___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_184__DRM_REG_184___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_184__DRM_REG_184___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_184___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_184___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_185 (0x005D7EE4) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_185___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_185___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_185__DRM_REG_185___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_185__DRM_REG_185___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_185__DRM_REG_185___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_185___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_185___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_186 (0x005D7EE8) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_186___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_186___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_186__DRM_REG_186___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_186__DRM_REG_186___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_186__DRM_REG_186___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_186___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_186___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_187 (0x005D7EEC) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_187___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_187___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_187__DRM_REG_187___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_187__DRM_REG_187___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_187__DRM_REG_187___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_187___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_187___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_188 (0x005D7EF0) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_188___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_188___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_188__DRM_REG_188___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_188__DRM_REG_188___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_188__DRM_REG_188___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_188___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_188___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_189 (0x005D7EF4) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_189___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_189___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_189__DRM_REG_189___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_189__DRM_REG_189___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_189__DRM_REG_189___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_189___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_189___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_190 (0x005D7EF8) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_190___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_190___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_190__DRM_REG_190___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_190__DRM_REG_190___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_190__DRM_REG_190___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_190___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_190___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_191 (0x005D7EFC) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_191___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_191___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_191__DRM_REG_191___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_191__DRM_REG_191___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_191__DRM_REG_191___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_191___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_191___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_192 (0x005D7F00) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_192___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_192___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_192__DRM_REG_192___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_192__DRM_REG_192___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_192__DRM_REG_192___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_192___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_192___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_193 (0x005D7F04) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_193___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_193___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_193__DRM_REG_193___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_193__DRM_REG_193___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_193__DRM_REG_193___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_193___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_193___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_194 (0x005D7F08) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_194___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_194___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_194__DRM_REG_194___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_194__DRM_REG_194___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_194__DRM_REG_194___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_194___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_194___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_195 (0x005D7F0C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_195___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_195___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_195__DRM_REG_195___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_195__DRM_REG_195___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_195__DRM_REG_195___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_195___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_195___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_196 (0x005D7F10) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_196___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_196___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_196__DRM_REG_196___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_196__DRM_REG_196___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_196__DRM_REG_196___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_196___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_196___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_197 (0x005D7F14) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_197___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_197___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_197__DRM_REG_197___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_197__DRM_REG_197___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_197__DRM_REG_197___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_197___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_197___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_198 (0x005D7F18) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_198___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_198___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_198__DRM_REG_198___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_198__DRM_REG_198___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_198__DRM_REG_198___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_198___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_198___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_199 (0x005D7F1C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_199___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_199___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_199__DRM_REG_199___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_199__DRM_REG_199___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_199__DRM_REG_199___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_199___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_199___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_200 (0x005D7F20) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_200___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_200___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_200__DRM_REG_200___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_200__DRM_REG_200___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_200__DRM_REG_200___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_200___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_200___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_201 (0x005D7F24) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_201___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_201___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_201__DRM_REG_201___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_201__DRM_REG_201___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_201__DRM_REG_201___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_201___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_201___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_202 (0x005D7F28) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_202___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_202___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_202__DRM_REG_202___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_202__DRM_REG_202___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_202__DRM_REG_202___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_202___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_202___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_203 (0x005D7F2C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_203___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_203___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_203__DRM_REG_203___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_203__DRM_REG_203___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_203__DRM_REG_203___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_203___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_203___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_204 (0x005D7F30) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_204___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_204___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_204__DRM_REG_204___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_204__DRM_REG_204___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_204__DRM_REG_204___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_204___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_204___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_205 (0x005D7F34) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_205___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_205___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_205__DRM_REG_205___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_205__DRM_REG_205___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_205__DRM_REG_205___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_205___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_205___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_206 (0x005D7F38) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_206___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_206___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_206__DRM_REG_206___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_206__DRM_REG_206___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_206__DRM_REG_206___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_206___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_206___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_207 (0x005D7F3C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_207___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_207___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_207__DRM_REG_207___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_207__DRM_REG_207___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_207__DRM_REG_207___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_207___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_207___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_208 (0x005D7F40) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_208___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_208___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_208__DRM_REG_208___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_208__DRM_REG_208___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_208__DRM_REG_208___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_208___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_208___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_209 (0x005D7F44) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_209___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_209___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_209__DRM_REG_209___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_209__DRM_REG_209___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_209__DRM_REG_209___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_209___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_209___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_210 (0x005D7F48) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_210___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_210___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_210__DRM_REG_210___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_210__DRM_REG_210___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_210__DRM_REG_210___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_210___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_210___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_211 (0x005D7F4C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_211___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_211___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_211__DRM_REG_211___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_211__DRM_REG_211___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_211__DRM_REG_211___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_211___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_211___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_212 (0x005D7F50) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_212___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_212___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_212__DRM_REG_212___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_212__DRM_REG_212___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_212__DRM_REG_212___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_212___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_212___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_213 (0x005D7F54) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_213___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_213___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_213__DRM_REG_213___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_213__DRM_REG_213___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_213__DRM_REG_213___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_213___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_213___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_214 (0x005D7F58) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_214___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_214___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_214__DRM_REG_214___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_214__DRM_REG_214___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_214__DRM_REG_214___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_214___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_214___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_215 (0x005D7F5C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_215___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_215___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_215__DRM_REG_215___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_215__DRM_REG_215___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_215__DRM_REG_215___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_215___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_215___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_216 (0x005D7F60) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_216___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_216___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_216__DRM_REG_216___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_216__DRM_REG_216___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_216__DRM_REG_216___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_216___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_216___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_217 (0x005D7F64) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_217___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_217___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_217__DRM_REG_217___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_217__DRM_REG_217___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_217__DRM_REG_217___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_217___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_217___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_218 (0x005D7F68) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_218___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_218___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_218__DRM_REG_218___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_218__DRM_REG_218___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_218__DRM_REG_218___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_218___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_218___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_219 (0x005D7F6C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_219___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_219___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_219__DRM_REG_219___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_219__DRM_REG_219___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_219__DRM_REG_219___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_219___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_219___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_220 (0x005D7F70) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_220___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_220___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_220__DRM_REG_220___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_220__DRM_REG_220___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_220__DRM_REG_220___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_220___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_220___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_221 (0x005D7F74) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_221___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_221___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_221__DRM_REG_221___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_221__DRM_REG_221___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_221__DRM_REG_221___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_221___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_221___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_222 (0x005D7F78) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_222___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_222___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_222__DRM_REG_222___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_222__DRM_REG_222___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_222__DRM_REG_222___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_222___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_222___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_223 (0x005D7F7C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_223___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_223___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_223__DRM_REG_223___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_223__DRM_REG_223___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_223__DRM_REG_223___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_223___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_223___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_224 (0x005D7F80) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_224___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_224___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_224__DRM_REG_224___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_224__DRM_REG_224___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_224__DRM_REG_224___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_224___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_224___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_225 (0x005D7F84) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_225___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_225___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_225__DRM_REG_225___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_225__DRM_REG_225___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_225__DRM_REG_225___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_225___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_225___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_226 (0x005D7F88) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_226___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_226___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_226__DRM_REG_226___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_226__DRM_REG_226___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_226__DRM_REG_226___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_226___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_226___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_227 (0x005D7F8C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_227___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_227___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_227__DRM_REG_227___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_227__DRM_REG_227___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_227__DRM_REG_227___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_227___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_227___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_228 (0x005D7F90) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_228___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_228___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_228__DRM_REG_228___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_228__DRM_REG_228___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_228__DRM_REG_228___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_228___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_228___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_229 (0x005D7F94) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_229___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_229___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_229__DRM_REG_229___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_229__DRM_REG_229___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_229__DRM_REG_229___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_229___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_229___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_230 (0x005D7F98) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_230___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_230___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_230__DRM_REG_230___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_230__DRM_REG_230___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_230__DRM_REG_230___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_230___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_230___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_231 (0x005D7F9C) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_231___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_231___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_231__DRM_REG_231___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_231__DRM_REG_231___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_231__DRM_REG_231___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_231___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_231___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_232 (0x005D7FA0) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_232___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_232___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_232__DRM_REG_232___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_232__DRM_REG_232___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_232__DRM_REG_232___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_232___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_232___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_233 (0x005D7FA4) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_233___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_233___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_233__DRM_REG_233___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_233__DRM_REG_233___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_233__DRM_REG_233___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_233___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_233___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_234 (0x005D7FA8) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_234___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_234___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_234__DRM_REG_234___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_234__DRM_REG_234___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_234__DRM_REG_234___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_234___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_234___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_235 (0x005D7FAC) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_235___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_235___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_235__DRM_REG_235___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_235__DRM_REG_235___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_235__DRM_REG_235___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_235___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_235___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_236 (0x005D7FB0) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_236___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_236___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_236__DRM_REG_236___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_236__DRM_REG_236___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_236__DRM_REG_236___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_236___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_236___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_237 (0x005D7FB4) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_237___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_237___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_237__DRM_REG_237___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_237__DRM_REG_237___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_237__DRM_REG_237___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_237___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_237___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_238 (0x005D7FB8) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_238___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_238___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_238__DRM_REG_238___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_238__DRM_REG_238___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_238__DRM_REG_238___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_238___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_238___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_239 (0x005D7FBC) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_239___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_239___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_239__DRM_REG_239___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_239__DRM_REG_239___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_239__DRM_REG_239___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_239___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_239___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_240 (0x005D7FC0) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_240___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_240___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_240__DRM_REG_240___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_240__DRM_REG_240___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_240__DRM_REG_240___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_240___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_240___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_241 (0x005D7FC4) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_241___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_241___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_241__DRM_REG_241___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_241__DRM_REG_241___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_241__DRM_REG_241___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_241___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_241___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_242 (0x005D7FC8) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_242___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_242___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_242__DRM_REG_242___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_242__DRM_REG_242___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_242__DRM_REG_242___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_242___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_242___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_243 (0x005D7FCC) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_243___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_243___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_243__DRM_REG_243___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_243__DRM_REG_243___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_243__DRM_REG_243___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_243___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_243___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_244 (0x005D7FD0) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_244___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_244___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_244__DRM_REG_244___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_244__DRM_REG_244___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_244__DRM_REG_244___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_244___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_244___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_245 (0x005D7FD4) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_245___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_245___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_245__DRM_REG_245___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_245__DRM_REG_245___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_245__DRM_REG_245___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_245___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_245___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_246 (0x005D7FD8) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_246___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_246___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_246__DRM_REG_246___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_246__DRM_REG_246___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_246__DRM_REG_246___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_246___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_246___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_247 (0x005D7FDC) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_247___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_247___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_247__DRM_REG_247___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_247__DRM_REG_247___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_247__DRM_REG_247___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_247___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_247___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_248 (0x005D7FE0) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_248___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_248___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_248__DRM_REG_248___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_248__DRM_REG_248___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_248__DRM_REG_248___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_248___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_248___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_249 (0x005D7FE4) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_249___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_249___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_249__DRM_REG_249___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_249__DRM_REG_249___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_249__DRM_REG_249___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_249___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_249___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_250 (0x005D7FE8) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_250___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_250___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_250__DRM_REG_250___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_250__DRM_REG_250___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_250__DRM_REG_250___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_250___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_250___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_ADDR (0x005D7FEC) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_ADDR___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_ADDR___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_ADDR__DRM_INDIRECT_ADDR___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_ADDR__DRM_INDIRECT_ADDR___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_ADDR__DRM_INDIRECT_ADDR___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_ADDR___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_ADDR___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_WDATA (0x005D7FF0) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_WDATA___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_WDATA___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_WDATA__DRM_INDIRECT_WDATA___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_WDATA__DRM_INDIRECT_WDATA___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_WDATA__DRM_INDIRECT_WDATA___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_WDATA___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_WDATA___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_CTRL (0x005D7FF4) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_CTRL___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_CTRL__DRM_INDIRECT_RD_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_CTRL__DRM_INDIRECT_WR_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_CTRL__DRM_INDIRECT_RD_REQ___M 0x00000002 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_CTRL__DRM_INDIRECT_RD_REQ___S 1 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_CTRL__DRM_INDIRECT_WR_REQ___M 0x00000001 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_CTRL__DRM_INDIRECT_WR_REQ___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_CTRL___M 0x00000003 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_DRM_REG_CTRL___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_RO_DRM_REG_RDATA (0x005D7FF8) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_RO_DRM_REG_RDATA___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_RO_DRM_REG_RDATA___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_RO_DRM_REG_RDATA__RO_DRM_INDIRECT_RDATA___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_RO_DRM_REG_RDATA__RO_DRM_INDIRECT_RDATA___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_RO_DRM_REG_RDATA__RO_DRM_INDIRECT_RDATA___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_RO_DRM_REG_RDATA___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_RO_DRM_REG_RDATA___S 0 + +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_RO_DRM_REG_STATUS (0x005D7FFC) +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_RO_DRM_REG_STATUS___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_RO_DRM_REG_STATUS___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_RO_DRM_REG_STATUS__RO_DRM_INDIRECT_STATUS___POR 0x00000000 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_RO_DRM_REG_STATUS__RO_DRM_INDIRECT_STATUS___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_RO_DRM_REG_STATUS__RO_DRM_INDIRECT_STATUS___S 0 +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_RO_DRM_REG_STATUS___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_HLS_WL_REGFILE_RO_DRM_REG_STATUS___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS (0x005DC000) +#define PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS___POR 0x00000444 +#define PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_TSENS_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_IC_25U_TEST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_IPT_25U_TEST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_IR_25U_TEST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_ISEL_IC___POR 0x4 +#define PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_ISEL_ICPT___POR 0x4 +#define PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_ISEL_IR___POR 0x4 +#define PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_TSENS_EN___M 0x00004000 +#define PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_TSENS_EN___S 14 +#define PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_IC_25U_TEST_EN___M 0x00002000 +#define PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_IC_25U_TEST_EN___S 13 +#define PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_IPT_25U_TEST_EN___M 0x00001000 +#define PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_IPT_25U_TEST_EN___S 12 +#define PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_IR_25U_TEST_EN___M 0x00000800 +#define PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_IR_25U_TEST_EN___S 11 +#define PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_ISEL_IC___M 0x00000700 +#define PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_ISEL_IC___S 8 +#define PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_ISEL_ICPT___M 0x00000070 +#define PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_ISEL_ICPT___S 4 +#define PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_ISEL_IR___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS__D_ISEL_IR___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS___M 0x00007F77 +#define PHYA_IRON2G_RFA_BT_MTOP_RF_BIAS___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_0 (0x005DC004) +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_0__TSENS_CAL_RUN_TRIGGER___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_0__TSENS_CAL_RUN_TRIGGER___M 0x00000002 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_0__TSENS_CAL_RUN_TRIGGER___S 1 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_0___M 0x00000002 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_0___S 1 + +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1 (0x005DC008) +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_UNGATE_CLK___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_CALIB_TIMING_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_CAL_RUN_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_SW_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_CAL_RUN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_RUN_CONTINUOUS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_RESETB_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_UNGATE_CLK___M 0x00000080 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_UNGATE_CLK___S 7 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_CALIB_TIMING_BYPASS___M 0x00000040 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_CALIB_TIMING_BYPASS___S 6 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_CAL_RUN_SEL___M 0x00000020 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_CAL_RUN_SEL___S 5 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_SW_RESET___M 0x00000010 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_SW_RESET___S 4 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_CAL_RUN___M 0x00000008 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_CAL_RUN___S 3 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_RUN_CONTINUOUS___M 0x00000004 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_RUN_CONTINUOUS___S 2 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_RESETB_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1__TSENS_RESETB_OVS___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_1___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_2 (0x005DC00C) +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_2__RO_D_TSENS_OUT_RAW___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_2__RO_D_TSENS_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_2__RO_D_TSENS_OUTPUT___POR 0x000 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_2__RO_D_TSENS_OUT_RAW___M 0x00000800 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_2__RO_D_TSENS_OUT_RAW___S 11 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_2__RO_D_TSENS_DONE___M 0x00000400 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_2__RO_D_TSENS_DONE___S 10 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_2__RO_D_TSENS_OUTPUT___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_2__RO_D_TSENS_OUTPUT___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_2___M 0x00000DFF +#define PHYA_IRON2G_RFA_BT_MTOP_TEMP_SENSOR_2___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV (0x005DC010) +#define PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__RSBCAL1_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__RSBCAL0_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_LE_2MBW_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__BT_BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_RXEN_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_RXEN_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_TXEN_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_TXEN_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_LP_MODE_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__RSBCAL1_EN___M 0x00008000 +#define PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__RSBCAL1_EN___S 15 +#define PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__RSBCAL0_EN___M 0x00004000 +#define PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__RSBCAL0_EN___S 14 +#define PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_LE_2MBW_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_LE_2MBW_OVS___S 12 +#define PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__BT_BIAS_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__BT_BIAS_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_RXEN_CH1_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_RXEN_CH1_OVS___S 8 +#define PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_RXEN_CH0_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_RXEN_CH0_OVS___S 6 +#define PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_TXEN_CH1_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_TXEN_CH1_OVS___S 4 +#define PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_TXEN_CH0_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_TXEN_CH0_OVS___S 2 +#define PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_LP_MODE_EN_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV__SYNTH_LP_MODE_EN_OVS___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV___M 0x0000FFFF +#define PHYA_IRON2G_RFA_BT_MTOP_SYNTH_OV___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0 (0x005DC014) +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TXRF_TXLO_I_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TXRF_TXLO_Q_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__RCF_UPC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__DAC_CLK_EN_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TXRF_PREDA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TXRF_DA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__XPA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__DAC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TX_2MBPS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__PL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__PL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TX_CLASS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TX_CLASS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__AOA_ACTIVE_TO_RFA_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__DAC_RATE_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TXRF_TXLO_I_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TXRF_TXLO_I_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TXRF_TXLO_Q_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TXRF_TXLO_Q_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__RCF_UPC_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__RCF_UPC_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__DAC_CLK_EN_CH0_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__DAC_CLK_EN_CH0_OVS___S 24 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TXRF_PREDA_EN_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TXRF_PREDA_EN_OVS___S 22 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TXRF_DA_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TXRF_DA_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__XPA_EN_OVS___M 0x00060000 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__XPA_EN_OVS___S 17 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__DAC_EN_OVS___M 0x00018000 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__DAC_EN_OVS___S 15 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TX_2MBPS_EN_OVS___M 0x00006000 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TX_2MBPS_EN_OVS___S 13 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__PL_OV___M 0x00001000 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__PL_OV___S 12 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__PL_OVD___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__PL_OVD___S 8 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TX_CLASS_OV___M 0x00000040 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TX_CLASS_OV___S 6 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TX_CLASS_OVD___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__TX_CLASS_OVD___S 4 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__AOA_ACTIVE_TO_RFA_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__AOA_ACTIVE_TO_RFA_OVS___S 2 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__DAC_RATE_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0__DAC_RATE_OVS___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0___M 0xFFF7FF7F +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_0___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1 (0x005DC018) +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__IPA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__IPA_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__BBF_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__BBF_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__UPC_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__UPC_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__DA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__DA_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__TX_GAIN_CH0_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__TX_GAIN_CH0_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__TX_GAIN_CH1_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__TX_GAIN_CH1_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__IPA_GAIN_OV___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__IPA_GAIN_OV___S 29 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__IPA_GAIN_OVD___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__IPA_GAIN_OVD___S 24 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__BBF_GAIN_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__BBF_GAIN_OV___S 23 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__BBF_GAIN_OVD___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__BBF_GAIN_OVD___S 18 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__UPC_GAIN_OV___M 0x00020000 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__UPC_GAIN_OV___S 17 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__UPC_GAIN_OVD___M 0x0001F000 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__UPC_GAIN_OVD___S 12 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__DA_GAIN_OV___M 0x00000800 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__DA_GAIN_OV___S 11 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__DA_GAIN_OVD___M 0x000007C0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__DA_GAIN_OVD___S 6 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__TX_GAIN_CH0_OV___M 0x00000020 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__TX_GAIN_CH0_OV___S 5 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__TX_GAIN_CH0_OVD___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__TX_GAIN_CH0_OVD___S 3 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__TX_GAIN_CH1_OV___M 0x00000004 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__TX_GAIN_CH1_OV___S 2 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__TX_GAIN_CH1_OVD___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1__TX_GAIN_CH1_OVD___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1___M 0x3FFFFFFF +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_1___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_2 (0x005DC01C) +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_2__DAC_DIN_Q_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_2__DAC_DIN_Q_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_2__DAC_DIN_I_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_2__DAC_DIN_I_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_2__DAC_DIN_Q_OV___M 0x10000000 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_2__DAC_DIN_Q_OV___S 28 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_2__DAC_DIN_Q_OVD___M 0x0FFF0000 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_2__DAC_DIN_Q_OVD___S 16 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_2__DAC_DIN_I_OV___M 0x00001000 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_2__DAC_DIN_I_OV___S 12 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_2__DAC_DIN_I_OVD___M 0x00000FFF +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_2__DAC_DIN_I_OVD___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_2___M 0x1FFF1FFF +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_2___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_3 (0x005DC020) +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_3__WLAN_CONTROL_EN_BT_TX_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_3__WLAN_CONTROL_EN_BT_TX_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_3__BTD_TXRF_GAINSTEP_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_3__BTD_TXRF_GAINSTEP_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_3__WLAN_CONTROL_EN_BT_TX_CH0_OVS___M 0x00000180 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_3__WLAN_CONTROL_EN_BT_TX_CH0_OVS___S 7 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_3__WLAN_CONTROL_EN_BT_TX_CH1_OVS___M 0x00000060 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_3__WLAN_CONTROL_EN_BT_TX_CH1_OVS___S 5 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_3__BTD_TXRF_GAINSTEP_OV___M 0x00000010 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_3__BTD_TXRF_GAINSTEP_OV___S 4 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_3__BTD_TXRF_GAINSTEP_OVD___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_3__BTD_TXRF_GAINSTEP_OVD___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_3___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_MTOP_TX_OV_3___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_BT_SYNT_FREQ_OV (0x005DC024) +#define PHYA_IRON2G_RFA_BT_MTOP_BT_SYNT_FREQ_OV___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_BT_SYNT_FREQ_OV___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_MTOP_BT_SYNT_FREQ_OV__SYNTH_HOP_FREQ_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_BT_SYNT_FREQ_OV__SYNTH_HOP_FREQ_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_BT_SYNT_FREQ_OV__SYNTH_HOP_FREQ_OV___M 0x00000080 +#define PHYA_IRON2G_RFA_BT_MTOP_BT_SYNT_FREQ_OV__SYNTH_HOP_FREQ_OV___S 7 +#define PHYA_IRON2G_RFA_BT_MTOP_BT_SYNT_FREQ_OV__SYNTH_HOP_FREQ_OVD___M 0x0000007F +#define PHYA_IRON2G_RFA_BT_MTOP_BT_SYNT_FREQ_OV__SYNTH_HOP_FREQ_OVD___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_BT_SYNT_FREQ_OV___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_MTOP_BT_SYNT_FREQ_OV___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0 (0x005DC028) +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_PKDET_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__ADCLP_EN_REF_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXBB_ENI_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXBB_ENQ_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_LOBUF_I_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_LOBUF_Q_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_MIXER_I_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_MIXER_Q_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_LNA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_GM_CORE_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RX_GAIN_CH0_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RX_GAIN_CH0_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RX_GAIN_CH1_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RX_GAIN_CH1_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_PKDET_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_PKDET_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__ADCLP_EN_REF_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__ADCLP_EN_REF_OVS___S 28 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXBB_ENI_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXBB_ENI_OVS___S 26 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXBB_ENQ_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXBB_ENQ_OVS___S 24 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_LOBUF_I_EN_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_LOBUF_I_EN_OVS___S 22 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_LOBUF_Q_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_LOBUF_Q_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_MIXER_I_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_MIXER_I_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_MIXER_Q_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_MIXER_Q_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_LNA_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_LNA_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_GM_CORE_EN_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RXRF_GM_CORE_EN_OVS___S 8 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RX_GAIN_CH0_OV___M 0x00000020 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RX_GAIN_CH0_OV___S 5 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RX_GAIN_CH0_OVD___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RX_GAIN_CH0_OVD___S 3 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RX_GAIN_CH1_OV___M 0x00000004 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RX_GAIN_CH1_OV___S 2 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RX_GAIN_CH1_OVD___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0__RX_GAIN_CH1_OVD___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0___M 0xFFFF0F3F +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_0___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1 (0x005DC02C) +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__RXRF_XLNA_EN_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__RX_2MBPS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__WLAN_CONCURRENCY_EN_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__WLAN_CONCURRENCY_EN_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__BTD_AGC_PKDET_OUT_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__BTD_AGC_PKDET_OUT_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__ADC_CLK_EN_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__ADC_RATE_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__ADC_CLK_EN_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__ADC_RATE_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__RXRF_XLNA_EN_CH1_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__RXRF_XLNA_EN_CH1_OVS___S 30 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__RX_2MBPS_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__RX_2MBPS_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__WLAN_CONCURRENCY_EN_CH1_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__WLAN_CONCURRENCY_EN_CH1_OVS___S 14 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__WLAN_CONCURRENCY_EN_CH0_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__WLAN_CONCURRENCY_EN_CH0_OVS___S 12 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__BTD_AGC_PKDET_OUT_CH1_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__BTD_AGC_PKDET_OUT_CH1_OVS___S 10 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__BTD_AGC_PKDET_OUT_CH0_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__BTD_AGC_PKDET_OUT_CH0_OVS___S 8 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__ADC_CLK_EN_CH0_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__ADC_CLK_EN_CH0_OVS___S 6 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__ADC_RATE_CH0_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__ADC_RATE_CH0_OVS___S 4 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__ADC_CLK_EN_CH1_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__ADC_CLK_EN_CH1_OVS___S 2 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__ADC_RATE_CH1_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1__ADC_RATE_CH1_OVS___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1___M 0xF000FFFF +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_1___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2 (0x005DC030) +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_XLNA_EN_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_LNA_GAIN_CH1_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_LNA_GAIN_CH1_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_GM_GAIN_CH1_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_GM_GAIN_CH1_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXBB_TIA_GAIN_CH1_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXBB_TIA_GAIN_CH1_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_VGA_GAIN_CH1_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_VGA_GAIN_CH1_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_LNA_GAIN_CH0_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_LNA_GAIN_CH0_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_GM_GAIN_CH0_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_GM_GAIN_CH0_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXBB_TIA_GAIN_CH0_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXBB_TIA_GAIN_CH0_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_VGA_GAIN_CH0_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_VGA_GAIN_CH0_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_XLNA_EN_CH0_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_XLNA_EN_CH0_OVS___S 30 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_LNA_GAIN_CH1_OV___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_LNA_GAIN_CH1_OV___S 29 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_LNA_GAIN_CH1_OVD___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_LNA_GAIN_CH1_OVD___S 26 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_GM_GAIN_CH1_OV___M 0x02000000 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_GM_GAIN_CH1_OV___S 25 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_GM_GAIN_CH1_OVD___M 0x01C00000 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_GM_GAIN_CH1_OVD___S 22 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXBB_TIA_GAIN_CH1_OV___M 0x00200000 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXBB_TIA_GAIN_CH1_OV___S 21 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXBB_TIA_GAIN_CH1_OVD___M 0x00180000 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXBB_TIA_GAIN_CH1_OVD___S 19 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_VGA_GAIN_CH1_OV___M 0x00040000 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_VGA_GAIN_CH1_OV___S 18 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_VGA_GAIN_CH1_OVD___M 0x00038000 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_VGA_GAIN_CH1_OVD___S 15 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_LNA_GAIN_CH0_OV___M 0x00004000 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_LNA_GAIN_CH0_OV___S 14 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_LNA_GAIN_CH0_OVD___M 0x00003800 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_LNA_GAIN_CH0_OVD___S 11 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_GM_GAIN_CH0_OV___M 0x00000400 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_GM_GAIN_CH0_OV___S 10 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_GM_GAIN_CH0_OVD___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_GM_GAIN_CH0_OVD___S 7 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXBB_TIA_GAIN_CH0_OV___M 0x00000040 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXBB_TIA_GAIN_CH0_OV___S 6 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXBB_TIA_GAIN_CH0_OVD___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXBB_TIA_GAIN_CH0_OVD___S 4 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_VGA_GAIN_CH0_OV___M 0x00000008 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_VGA_GAIN_CH0_OV___S 3 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_VGA_GAIN_CH0_OVD___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2__RXRF_VGA_GAIN_CH0_OVD___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_2___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE (0x005DC034) +#define PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE__LATCH_RX_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE__GUARD_EN_TIMING_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE__CALIB_TIMING_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE__LOCAL_DTOP_TEST_MUX_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE__DTOP_TEST_MUX_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE__LATCH_RX_MODE___M 0x00040000 +#define PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE__LATCH_RX_MODE___S 18 +#define PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE__GUARD_EN_TIMING_BYPASS___M 0x00020000 +#define PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE__GUARD_EN_TIMING_BYPASS___S 17 +#define PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE__CALIB_TIMING_BYPASS___M 0x00010000 +#define PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE__CALIB_TIMING_BYPASS___S 16 +#define PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE__LOCAL_DTOP_TEST_MUX_SEL___M 0x00000700 +#define PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE__LOCAL_DTOP_TEST_MUX_SEL___S 8 +#define PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE__DTOP_TEST_MUX_SEL___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE__DTOP_TEST_MUX_SEL___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE___M 0x000707FF +#define PHYA_IRON2G_RFA_BT_MTOP_TEST_MODE___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_SPARE_0 (0x005DC038) +#define PHYA_IRON2G_RFA_BT_MTOP_SPARE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_SPARE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_MTOP_SPARE_0__SPARE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_MTOP_SPARE_0__SPARE_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_MTOP_SPARE_0__SPARE_0___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_SPARE_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_MTOP_SPARE_0___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_SPARE_1 (0x005DC03C) +#define PHYA_IRON2G_RFA_BT_MTOP_SPARE_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_SPARE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_MTOP_SPARE_1__SPARE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_MTOP_SPARE_1__SPARE_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_MTOP_SPARE_1__SPARE_1___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_SPARE_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_MTOP_SPARE_1___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV (0x005DC040) +#define PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV___POR 0x00000046 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_EN_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_EN_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_PATH_CH0_OV___POR 0x1 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_PATH_CH0_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_PATH_CH1_OV___POR 0x1 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_PATH_CH1_OVD___POR 0x2 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_EN_CH0_OVS___M 0x00000600 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_EN_CH0_OVS___S 9 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_EN_CH1_OVS___M 0x00000180 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_EN_CH1_OVS___S 7 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_PATH_CH0_OV___M 0x00000040 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_PATH_CH0_OV___S 6 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_PATH_CH0_OVD___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_PATH_CH0_OVD___S 4 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_PATH_CH1_OV___M 0x00000004 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_PATH_CH1_OV___S 2 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_PATH_CH1_OVD___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV__TX_PATH_CH1_OVD___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV___M 0x000007F7 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_PATH_OV___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV (0x005DC044) +#define PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV___POR 0x00000066 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_EN_CH0_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_EN_CH1_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_PATH_CH1_OV___POR 0x1 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_PATH_CH1_OVD___POR 0x2 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_PATH_CH0_OV___POR 0x1 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_PATH_CH0_OVD___POR 0x2 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_EN_CH0_OVS___M 0x00000600 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_EN_CH0_OVS___S 9 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_EN_CH1_OVS___M 0x00000180 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_EN_CH1_OVS___S 7 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_PATH_CH1_OV___M 0x00000040 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_PATH_CH1_OV___S 6 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_PATH_CH1_OVD___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_PATH_CH1_OVD___S 4 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_PATH_CH0_OV___M 0x00000004 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_PATH_CH0_OV___S 2 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_PATH_CH0_OVD___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV__RX_PATH_CH0_OVD___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV___M 0x000007F7 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_PATH_OV___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3 (0x005DC048) +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTQ_CH1_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTQ_CH1_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTI_CH1_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTI_CH1_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTQ_CH0_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTQ_CH0_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTI_CH0_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTI_CH0_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTQ_CH1_OV___M 0x10000000 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTQ_CH1_OV___S 28 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTQ_CH1_OVD___M 0x0F000000 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTQ_CH1_OVD___S 24 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTI_CH1_OV___M 0x00100000 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTI_CH1_OV___S 20 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTI_CH1_OVD___M 0x000F0000 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTI_CH1_OVD___S 16 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTQ_CH0_OV___M 0x00001000 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTQ_CH0_OV___S 12 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTQ_CH0_OVD___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTQ_CH0_OVD___S 8 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTI_CH0_OV___M 0x00000010 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTI_CH0_OV___S 4 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTI_CH0_OVD___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3__D_DOUTI_CH0_OVD___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_MTOP_RX_OV_3___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0 (0x005DC04C) +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_7_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_7_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_6_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_6_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_5_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_5_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_4_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_4_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_3_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_3_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_2_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_2_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_1_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_1_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_0_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_0_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_7_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_7_EN___S 31 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_7_BIT___M 0x70000000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_7_BIT___S 28 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_6_EN___M 0x08000000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_6_EN___S 27 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_6_BIT___M 0x07000000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_6_BIT___S 24 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_5_EN___M 0x00800000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_5_EN___S 23 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_5_BIT___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_5_BIT___S 20 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_4_EN___M 0x00080000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_4_EN___S 19 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_4_BIT___M 0x00070000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_4_BIT___S 16 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_3_EN___M 0x00008000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_3_EN___S 15 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_3_BIT___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_3_BIT___S 12 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_2_EN___M 0x00000800 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_2_EN___S 11 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_2_BIT___M 0x00000700 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_2_BIT___S 8 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_1_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_1_EN___S 7 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_1_BIT___M 0x00000070 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_1_BIT___S 4 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_0_EN___M 0x00000008 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_0_EN___S 3 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_0_BIT___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0__PIN_0_BIT___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_0___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1 (0x005DC050) +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_15_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_15_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_14_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_14_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_13_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_13_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_12_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_12_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_11_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_11_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_10_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_10_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_9_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_9_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_8_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_8_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_15_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_15_EN___S 31 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_15_BIT___M 0x70000000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_15_BIT___S 28 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_14_EN___M 0x08000000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_14_EN___S 27 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_14_BIT___M 0x07000000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_14_BIT___S 24 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_13_EN___M 0x00800000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_13_EN___S 23 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_13_BIT___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_13_BIT___S 20 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_12_EN___M 0x00080000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_12_EN___S 19 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_12_BIT___M 0x00070000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_12_BIT___S 16 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_11_EN___M 0x00008000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_11_EN___S 15 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_11_BIT___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_11_BIT___S 12 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_10_EN___M 0x00000800 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_10_EN___S 11 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_10_BIT___M 0x00000700 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_10_BIT___S 8 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_9_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_9_EN___S 7 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_9_BIT___M 0x00000070 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_9_BIT___S 4 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_8_EN___M 0x00000008 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_8_EN___S 3 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_8_BIT___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1__PIN_8_BIT___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_1___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2 (0x005DC054) +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_23_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_23_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_22_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_22_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_21_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_21_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_20_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_20_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_19_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_19_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_18_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_18_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_17_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_17_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_16_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_16_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_23_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_23_EN___S 31 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_23_BIT___M 0x70000000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_23_BIT___S 28 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_22_EN___M 0x08000000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_22_EN___S 27 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_22_BIT___M 0x07000000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_22_BIT___S 24 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_21_EN___M 0x00800000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_21_EN___S 23 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_21_BIT___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_21_BIT___S 20 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_20_EN___M 0x00080000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_20_EN___S 19 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_20_BIT___M 0x00070000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_20_BIT___S 16 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_19_EN___M 0x00008000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_19_EN___S 15 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_19_BIT___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_19_BIT___S 12 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_18_EN___M 0x00000800 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_18_EN___S 11 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_18_BIT___M 0x00000700 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_18_BIT___S 8 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_17_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_17_EN___S 7 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_17_BIT___M 0x00000070 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_17_BIT___S 4 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_16_EN___M 0x00000008 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_16_EN___S 3 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_16_BIT___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2__PIN_16_BIT___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_2___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3 (0x005DC058) +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_26_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_26_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_25_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_25_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_24_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_24_BIT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_26_EN___M 0x00000800 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_26_EN___S 11 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_26_BIT___M 0x00000700 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_26_BIT___S 8 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_25_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_25_EN___S 7 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_25_BIT___M 0x00000070 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_25_BIT___S 4 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_24_EN___M 0x00000008 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_24_EN___S 3 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_24_BIT___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3__PIN_24_BIT___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3___M 0x00000FFF +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_PIN_MUX_REG_3___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_OVR (0x005DC05C) +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_OVR___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_OVR___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_OVR__ANT_SW_CONTROL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_OVR__ANT_SW_CONTROL_OVD___POR 0x0000000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_OVR__ANT_SW_CONTROL_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_OVR__ANT_SW_CONTROL_OV___S 27 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_OVR__ANT_SW_CONTROL_OVD___M 0x07FFFFFF +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_OVR__ANT_SW_CONTROL_OVD___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_OVR___M 0x0FFFFFFF +#define PHYA_IRON2G_RFA_BT_MTOP_AOA_OVR___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_TX_CONFIG_0 (0x005DC060) +#define PHYA_IRON2G_RFA_BT_MTOP_TX_CONFIG_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_TX_CONFIG_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_CONFIG_0__WLAN_CONTROL_EN_BT_TX_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_CONFIG_0__WLAN_CONTROL_EN_BT_TX_DIS___M 0x00000004 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_CONFIG_0__WLAN_CONTROL_EN_BT_TX_DIS___S 2 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_CONFIG_0___M 0x00000004 +#define PHYA_IRON2G_RFA_BT_MTOP_TX_CONFIG_0___S 2 + +#define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS (0x005DC064) +#define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_BIAS_EN_CH0_TO_CT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_BIAS_EN_CH1_TO_CT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_IC_CH0_TO_CT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_IR_CH0_TO_CT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_ICPT_CH0_TO_CT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_IC_CH1_TO_CT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_IR_CH1_TO_CT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_ICPT_CH1_TO_CT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_BIAS_EN_CH0_TO_CT_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_BIAS_EN_CH0_TO_CT_OVS___S 30 +#define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_BIAS_EN_CH1_TO_CT_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_BIAS_EN_CH1_TO_CT_OVS___S 28 +#define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_IC_CH0_TO_CT___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_IC_CH0_TO_CT___S 20 +#define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_IR_CH0_TO_CT___M 0x00070000 +#define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_IR_CH0_TO_CT___S 16 +#define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_ICPT_CH0_TO_CT___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_ICPT_CH0_TO_CT___S 12 +#define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_IC_CH1_TO_CT___M 0x00000700 +#define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_IC_CH1_TO_CT___S 8 +#define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_IR_CH1_TO_CT___M 0x00000070 +#define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_IR_CH1_TO_CT___S 4 +#define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_ICPT_CH1_TO_CT___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS__BT_WL_ISEL_ICPT_CH1_TO_CT___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS___M 0xF0777777 +#define PHYA_IRON2G_RFA_BT_MTOP_WL_BIAS___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_RO_MTOP_LUT_IDX_SEL (0x005DC068) +#define PHYA_IRON2G_RFA_BT_MTOP_RO_MTOP_LUT_IDX_SEL___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BT_MTOP_RO_MTOP_LUT_IDX_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_MTOP_RO_MTOP_LUT_IDX_SEL__RO_BTD_TXRF_GAINSTEP___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_RO_MTOP_LUT_IDX_SEL__RO_BTD_TXRF_GAINSTEP___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_MTOP_RO_MTOP_LUT_IDX_SEL__RO_BTD_TXRF_GAINSTEP___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_RO_MTOP_LUT_IDX_SEL___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_MTOP_RO_MTOP_LUT_IDX_SEL___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0 (0x005DC06C) +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0___POR 0x01000002 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__TX_CLASS0___POR 0x2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__IPA_GAIN0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__BBF_GAIN0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__UPC_GAIN0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__DA_GAIN0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__XPA_GAIN0___POR 0x2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__TX_CLASS0___M 0x01800000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__TX_CLASS0___S 23 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__IPA_GAIN0___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__IPA_GAIN0___S 18 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__BBF_GAIN0___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__BBF_GAIN0___S 13 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__UPC_GAIN0___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__UPC_GAIN0___S 8 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__DA_GAIN0___M 0x000000FC +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__DA_GAIN0___S 2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__XPA_GAIN0___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0__XPA_GAIN0___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT0___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1 (0x005DC070) +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1___POR 0x01000002 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__TX_CLASS1___POR 0x2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__IPA_GAIN1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__BBF_GAIN1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__UPC_GAIN1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__DA_GAIN1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__XPA_GAIN1___POR 0x2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__TX_CLASS1___M 0x01800000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__TX_CLASS1___S 23 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__IPA_GAIN1___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__IPA_GAIN1___S 18 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__BBF_GAIN1___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__BBF_GAIN1___S 13 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__UPC_GAIN1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__UPC_GAIN1___S 8 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__DA_GAIN1___M 0x000000FC +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__DA_GAIN1___S 2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__XPA_GAIN1___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1__XPA_GAIN1___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT1___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2 (0x005DC074) +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2___POR 0x01000002 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__TX_CLASS2___POR 0x2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__IPA_GAIN2___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__BBF_GAIN2___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__UPC_GAIN2___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__DA_GAIN2___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__XPA_GAIN2___POR 0x2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__TX_CLASS2___M 0x01800000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__TX_CLASS2___S 23 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__IPA_GAIN2___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__IPA_GAIN2___S 18 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__BBF_GAIN2___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__BBF_GAIN2___S 13 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__UPC_GAIN2___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__UPC_GAIN2___S 8 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__DA_GAIN2___M 0x000000FC +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__DA_GAIN2___S 2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__XPA_GAIN2___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2__XPA_GAIN2___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT2___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3 (0x005DC078) +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3___POR 0x01000002 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__TX_CLASS3___POR 0x2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__IPA_GAIN3___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__BBF_GAIN3___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__UPC_GAIN3___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__DA_GAIN3___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__XPA_GAIN3___POR 0x2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__TX_CLASS3___M 0x01800000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__TX_CLASS3___S 23 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__IPA_GAIN3___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__IPA_GAIN3___S 18 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__BBF_GAIN3___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__BBF_GAIN3___S 13 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__UPC_GAIN3___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__UPC_GAIN3___S 8 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__DA_GAIN3___M 0x000000FC +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__DA_GAIN3___S 2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__XPA_GAIN3___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3__XPA_GAIN3___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT3___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4 (0x005DC07C) +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4___POR 0x01000002 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__TX_CLASS4___POR 0x2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__IPA_GAIN4___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__BBF_GAIN4___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__UPC_GAIN4___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__DA_GAIN4___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__XPA_GAIN4___POR 0x2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__TX_CLASS4___M 0x01800000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__TX_CLASS4___S 23 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__IPA_GAIN4___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__IPA_GAIN4___S 18 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__BBF_GAIN4___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__BBF_GAIN4___S 13 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__UPC_GAIN4___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__UPC_GAIN4___S 8 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__DA_GAIN4___M 0x000000FC +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__DA_GAIN4___S 2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__XPA_GAIN4___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4__XPA_GAIN4___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT4___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5 (0x005DC080) +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5___POR 0x01000002 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__TX_CLASS5___POR 0x2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__IPA_GAIN5___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__BBF_GAIN5___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__UPC_GAIN5___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__DA_GAIN5___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__XPA_GAIN5___POR 0x2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__TX_CLASS5___M 0x01800000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__TX_CLASS5___S 23 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__IPA_GAIN5___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__IPA_GAIN5___S 18 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__BBF_GAIN5___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__BBF_GAIN5___S 13 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__UPC_GAIN5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__UPC_GAIN5___S 8 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__DA_GAIN5___M 0x000000FC +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__DA_GAIN5___S 2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__XPA_GAIN5___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5__XPA_GAIN5___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT5___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6 (0x005DC084) +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6___POR 0x01000002 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__TX_CLASS6___POR 0x2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__IPA_GAIN6___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__BBF_GAIN6___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__UPC_GAIN6___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__DA_GAIN6___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__XPA_GAIN6___POR 0x2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__TX_CLASS6___M 0x01800000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__TX_CLASS6___S 23 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__IPA_GAIN6___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__IPA_GAIN6___S 18 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__BBF_GAIN6___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__BBF_GAIN6___S 13 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__UPC_GAIN6___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__UPC_GAIN6___S 8 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__DA_GAIN6___M 0x000000FC +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__DA_GAIN6___S 2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__XPA_GAIN6___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6__XPA_GAIN6___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT6___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7 (0x005DC088) +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7___POR 0x01000002 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__TX_CLASS7___POR 0x2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__IPA_GAIN7___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__BBF_GAIN7___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__UPC_GAIN7___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__DA_GAIN7___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__XPA_GAIN7___POR 0x2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__TX_CLASS7___M 0x01800000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__TX_CLASS7___S 23 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__IPA_GAIN7___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__IPA_GAIN7___S 18 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__BBF_GAIN7___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__BBF_GAIN7___S 13 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__UPC_GAIN7___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__UPC_GAIN7___S 8 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__DA_GAIN7___M 0x000000FC +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__DA_GAIN7___S 2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__XPA_GAIN7___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7__XPA_GAIN7___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT7___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8 (0x005DC08C) +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8___POR 0x00000002 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__TX_CLASS8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__IPA_GAIN8___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__BBF_GAIN8___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__UPC_GAIN8___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__DA_GAIN8___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__XPA_GAIN8___POR 0x2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__TX_CLASS8___M 0x01800000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__TX_CLASS8___S 23 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__IPA_GAIN8___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__IPA_GAIN8___S 18 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__BBF_GAIN8___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__BBF_GAIN8___S 13 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__UPC_GAIN8___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__UPC_GAIN8___S 8 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__DA_GAIN8___M 0x000000FC +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__DA_GAIN8___S 2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__XPA_GAIN8___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8__XPA_GAIN8___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT8___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9 (0x005DC090) +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9___POR 0x00000002 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__TX_CLASS9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__IPA_GAIN9___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__BBF_GAIN9___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__UPC_GAIN9___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__DA_GAIN9___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__XPA_GAIN9___POR 0x2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__TX_CLASS9___M 0x01800000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__TX_CLASS9___S 23 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__IPA_GAIN9___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__IPA_GAIN9___S 18 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__BBF_GAIN9___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__BBF_GAIN9___S 13 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__UPC_GAIN9___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__UPC_GAIN9___S 8 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__DA_GAIN9___M 0x000000FC +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__DA_GAIN9___S 2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__XPA_GAIN9___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9__XPA_GAIN9___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT9___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10 (0x005DC094) +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10___POR 0x00800002 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__TX_CLASS10___POR 0x1 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__IPA_GAIN10___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__BBF_GAIN10___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__UPC_GAIN10___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__DA_GAIN10___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__XPA_GAIN10___POR 0x2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__TX_CLASS10___M 0x01800000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__TX_CLASS10___S 23 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__IPA_GAIN10___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__IPA_GAIN10___S 18 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__BBF_GAIN10___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__BBF_GAIN10___S 13 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__UPC_GAIN10___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__UPC_GAIN10___S 8 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__DA_GAIN10___M 0x000000FC +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__DA_GAIN10___S 2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__XPA_GAIN10___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10__XPA_GAIN10___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT10___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11 (0x005DC098) +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11___POR 0x00800002 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__TX_CLASS11___POR 0x1 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__IPA_GAIN11___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__BBF_GAIN11___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__UPC_GAIN11___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__DA_GAIN11___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__XPA_GAIN11___POR 0x2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__TX_CLASS11___M 0x01800000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__TX_CLASS11___S 23 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__IPA_GAIN11___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__IPA_GAIN11___S 18 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__BBF_GAIN11___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__BBF_GAIN11___S 13 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__UPC_GAIN11___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__UPC_GAIN11___S 8 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__DA_GAIN11___M 0x000000FC +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__DA_GAIN11___S 2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__XPA_GAIN11___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11__XPA_GAIN11___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT11___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12 (0x005DC09C) +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12___POR 0x01000002 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__TX_CLASS12___POR 0x2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__IPA_GAIN12___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__BBF_GAIN12___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__UPC_GAIN12___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__DA_GAIN12___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__XPA_GAIN12___POR 0x2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__TX_CLASS12___M 0x01800000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__TX_CLASS12___S 23 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__IPA_GAIN12___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__IPA_GAIN12___S 18 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__BBF_GAIN12___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__BBF_GAIN12___S 13 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__UPC_GAIN12___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__UPC_GAIN12___S 8 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__DA_GAIN12___M 0x000000FC +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__DA_GAIN12___S 2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__XPA_GAIN12___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12__XPA_GAIN12___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT12___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13 (0x005DC0A0) +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13___POR 0x01000002 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__TX_CLASS13___POR 0x2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__IPA_GAIN13___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__BBF_GAIN13___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__UPC_GAIN13___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__DA_GAIN13___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__XPA_GAIN13___POR 0x2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__TX_CLASS13___M 0x01800000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__TX_CLASS13___S 23 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__IPA_GAIN13___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__IPA_GAIN13___S 18 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__BBF_GAIN13___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__BBF_GAIN13___S 13 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__UPC_GAIN13___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__UPC_GAIN13___S 8 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__DA_GAIN13___M 0x000000FC +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__DA_GAIN13___S 2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__XPA_GAIN13___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13__XPA_GAIN13___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT13___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14 (0x005DC0A4) +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14___POR 0x01000002 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__TX_CLASS14___POR 0x2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__IPA_GAIN14___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__BBF_GAIN14___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__UPC_GAIN14___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__DA_GAIN14___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__XPA_GAIN14___POR 0x2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__TX_CLASS14___M 0x01800000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__TX_CLASS14___S 23 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__IPA_GAIN14___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__IPA_GAIN14___S 18 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__BBF_GAIN14___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__BBF_GAIN14___S 13 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__UPC_GAIN14___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__UPC_GAIN14___S 8 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__DA_GAIN14___M 0x000000FC +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__DA_GAIN14___S 2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__XPA_GAIN14___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14__XPA_GAIN14___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT14___S 0 + +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15 (0x005DC0A8) +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15___POR 0x01000002 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__TX_CLASS15___POR 0x2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__IPA_GAIN15___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__BBF_GAIN15___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__UPC_GAIN15___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__DA_GAIN15___POR 0x00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__XPA_GAIN15___POR 0x2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__TX_CLASS15___M 0x01800000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__TX_CLASS15___S 23 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__IPA_GAIN15___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__IPA_GAIN15___S 18 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__BBF_GAIN15___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__BBF_GAIN15___S 13 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__UPC_GAIN15___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__UPC_GAIN15___S 8 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__DA_GAIN15___M 0x000000FC +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__DA_GAIN15___S 2 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__XPA_GAIN15___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15__XPA_GAIN15___S 0 +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_BT_MTOP_MTOP_TX_GAIN_LUT15___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0 (0x005DC800) +#define PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0___POR 0x00082E00 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_RCFUPC_SPARES___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_RCF_IOFFN___POR 0x08 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_ISINK_SEL___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_RCF_IOFFP___POR 0x0E +#define PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_RCF_FLT_BYP___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_RCFUPC_ATB___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_TX_TMX_OUT_EN_Q___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_TX_TMX_OUT_EN_I___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_RCFUPC_SPARES___M 0xF0000000 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_RCFUPC_SPARES___S 28 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_RCF_IOFFN___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_RCF_IOFFN___S 16 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_ISINK_SEL___M 0x00006000 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_ISINK_SEL___S 13 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_RCF_IOFFP___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_RCF_IOFFP___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_RCF_FLT_BYP___M 0x00000080 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_RCF_FLT_BYP___S 7 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_RCFUPC_ATB___M 0x0000003C +#define PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_RCFUPC_ATB___S 2 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_TX_TMX_OUT_EN_Q___M 0x00000002 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_TX_TMX_OUT_EN_Q___S 1 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_TX_TMX_OUT_EN_I___M 0x00000001 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0__D_TX_TMX_OUT_EN_I___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0___M 0xF01F7FBF +#define PHYA_IRON2G_RFA_BT_TXBB_TX_STATIC_0___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_TXBB_CAL_LUT (0x005DC804) +#define PHYA_IRON2G_RFA_BT_TXBB_TXBB_CAL_LUT___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_TXBB_CAL_LUT___POR 0x0000033E +#define PHYA_IRON2G_RFA_BT_TXBB_TXBB_CAL_LUT__D_RCF_RES___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXBB_TXBB_CAL_LUT__D_RCF_CAP_TUNE_2M___POR 0x3 +#define PHYA_IRON2G_RFA_BT_TXBB_TXBB_CAL_LUT__D_RCF_CAP_TUNE_1M___POR 0xE +#define PHYA_IRON2G_RFA_BT_TXBB_TXBB_CAL_LUT__D_RCF_RES___M 0x00000700 +#define PHYA_IRON2G_RFA_BT_TXBB_TXBB_CAL_LUT__D_RCF_RES___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_TXBB_CAL_LUT__D_RCF_CAP_TUNE_2M___M 0x000000F0 +#define PHYA_IRON2G_RFA_BT_TXBB_TXBB_CAL_LUT__D_RCF_CAP_TUNE_2M___S 4 +#define PHYA_IRON2G_RFA_BT_TXBB_TXBB_CAL_LUT__D_RCF_CAP_TUNE_1M___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_TXBB_TXBB_CAL_LUT__D_RCF_CAP_TUNE_1M___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_TXBB_CAL_LUT___M 0x000007FF +#define PHYA_IRON2G_RFA_BT_TXBB_TXBB_CAL_LUT___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0 (0x005DC808) +#define PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_TXMIX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_CAP_TUNE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_CAP_TUNE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_GAIN_CODE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_GAIN_CODE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_PC_CODE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_PC_CODE_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_TXMIX_EN_OVS___M 0x00600000 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_TXMIX_EN_OVS___S 21 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_CAP_TUNE_OV___M 0x00100000 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_CAP_TUNE_OV___S 20 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_CAP_TUNE_OVD___M 0x000F0000 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_CAP_TUNE_OVD___S 16 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_GAIN_CODE_OV___M 0x00001000 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_GAIN_CODE_OV___S 12 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_GAIN_CODE_OVD___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_GAIN_CODE_OVD___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_PC_CODE_OV___M 0x00000020 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_PC_CODE_OV___S 5 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_PC_CODE_OVD___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0__D_RCF_PC_CODE_OVD___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0___M 0x007F1F3F +#define PHYA_IRON2G_RFA_BT_TXBB_TX_OV_0___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_LUT_IDX_SEL (0x005DC80C) +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_LUT_IDX_SEL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_LUT_IDX_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_LUT_IDX_SEL__BBF_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_LUT_IDX_SEL__BBF_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_LUT_IDX_SEL__BBF_GAIN_OV___M 0x00000020 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_LUT_IDX_SEL__BBF_GAIN_OV___S 5 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_LUT_IDX_SEL__BBF_GAIN_OVD___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_LUT_IDX_SEL__BBF_GAIN_OVD___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_LUT_IDX_SEL___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_LUT_IDX_SEL___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_RO_TXBB_LUT_IDX_SEL (0x005DC810) +#define PHYA_IRON2G_RFA_BT_TXBB_RO_TXBB_LUT_IDX_SEL___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BT_TXBB_RO_TXBB_LUT_IDX_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXBB_RO_TXBB_LUT_IDX_SEL__RO_BBF_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_RO_TXBB_LUT_IDX_SEL__RO_BBF_GAIN___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_RO_TXBB_LUT_IDX_SEL__RO_BBF_GAIN___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_RO_TXBB_LUT_IDX_SEL___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_RO_TXBB_LUT_IDX_SEL___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_0 (0x005DC814) +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_0__RCF_GAIN_CODE_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_0__RCF_PC_CODE_0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_0__RCF_GAIN_CODE_0___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_0__RCF_GAIN_CODE_0___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_0__RCF_PC_CODE_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_0__RCF_PC_CODE_0___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_0___M 0x00000F1F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_0___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_1 (0x005DC818) +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_1__RCF_GAIN_CODE_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_1__RCF_PC_CODE_1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_1__RCF_GAIN_CODE_1___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_1__RCF_GAIN_CODE_1___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_1__RCF_PC_CODE_1___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_1__RCF_PC_CODE_1___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_1___M 0x00000F1F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_1___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_2 (0x005DC81C) +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_2__RCF_GAIN_CODE_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_2__RCF_PC_CODE_2___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_2__RCF_GAIN_CODE_2___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_2__RCF_GAIN_CODE_2___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_2__RCF_PC_CODE_2___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_2__RCF_PC_CODE_2___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_2___M 0x00000F1F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_2___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_3 (0x005DC820) +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_3__RCF_GAIN_CODE_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_3__RCF_PC_CODE_3___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_3__RCF_GAIN_CODE_3___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_3__RCF_GAIN_CODE_3___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_3__RCF_PC_CODE_3___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_3__RCF_PC_CODE_3___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_3___M 0x00000F1F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_3___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_4 (0x005DC824) +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_4__RCF_GAIN_CODE_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_4__RCF_PC_CODE_4___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_4__RCF_GAIN_CODE_4___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_4__RCF_GAIN_CODE_4___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_4__RCF_PC_CODE_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_4__RCF_PC_CODE_4___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_4___M 0x00000F1F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_4___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_5 (0x005DC828) +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_5__RCF_GAIN_CODE_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_5__RCF_PC_CODE_5___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_5__RCF_GAIN_CODE_5___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_5__RCF_GAIN_CODE_5___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_5__RCF_PC_CODE_5___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_5__RCF_PC_CODE_5___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_5___M 0x00000F1F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_5___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_6 (0x005DC82C) +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_6__RCF_GAIN_CODE_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_6__RCF_PC_CODE_6___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_6__RCF_GAIN_CODE_6___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_6__RCF_GAIN_CODE_6___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_6__RCF_PC_CODE_6___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_6__RCF_PC_CODE_6___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_6___M 0x00000F1F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_6___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_7 (0x005DC830) +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_7__RCF_GAIN_CODE_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_7__RCF_PC_CODE_7___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_7__RCF_GAIN_CODE_7___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_7__RCF_GAIN_CODE_7___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_7__RCF_PC_CODE_7___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_7__RCF_PC_CODE_7___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_7___M 0x00000F1F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_7___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_8 (0x005DC834) +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_8__RCF_GAIN_CODE_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_8__RCF_PC_CODE_8___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_8__RCF_GAIN_CODE_8___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_8__RCF_GAIN_CODE_8___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_8__RCF_PC_CODE_8___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_8__RCF_PC_CODE_8___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_8___M 0x00000F1F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_8___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_9 (0x005DC838) +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_9__RCF_GAIN_CODE_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_9__RCF_PC_CODE_9___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_9__RCF_GAIN_CODE_9___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_9__RCF_GAIN_CODE_9___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_9__RCF_PC_CODE_9___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_9__RCF_PC_CODE_9___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_9___M 0x00000F1F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_9___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_10 (0x005DC83C) +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_10__RCF_GAIN_CODE_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_10__RCF_PC_CODE_10___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_10__RCF_GAIN_CODE_10___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_10__RCF_GAIN_CODE_10___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_10__RCF_PC_CODE_10___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_10__RCF_PC_CODE_10___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_10___M 0x00000F1F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_10___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_11 (0x005DC840) +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_11__RCF_GAIN_CODE_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_11__RCF_PC_CODE_11___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_11__RCF_GAIN_CODE_11___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_11__RCF_GAIN_CODE_11___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_11__RCF_PC_CODE_11___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_11__RCF_PC_CODE_11___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_11___M 0x00000F1F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_11___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_12 (0x005DC844) +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_12__RCF_GAIN_CODE_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_12__RCF_PC_CODE_12___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_12__RCF_GAIN_CODE_12___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_12__RCF_GAIN_CODE_12___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_12__RCF_PC_CODE_12___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_12__RCF_PC_CODE_12___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_12___M 0x00000F1F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_12___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_13 (0x005DC848) +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_13__RCF_GAIN_CODE_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_13__RCF_PC_CODE_13___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_13__RCF_GAIN_CODE_13___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_13__RCF_GAIN_CODE_13___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_13__RCF_PC_CODE_13___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_13__RCF_PC_CODE_13___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_13___M 0x00000F1F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_13___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_14 (0x005DC84C) +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_14__RCF_GAIN_CODE_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_14__RCF_PC_CODE_14___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_14__RCF_GAIN_CODE_14___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_14__RCF_GAIN_CODE_14___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_14__RCF_PC_CODE_14___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_14__RCF_PC_CODE_14___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_14___M 0x00000F1F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_14___S 0 + +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15 (0x005DC850) +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15__RCF_GAIN_CODE_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15__RCF_PC_CODE_15___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15__RCF_GAIN_CODE_15___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15__RCF_GAIN_CODE_15___S 8 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15__RCF_PC_CODE_15___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15__RCF_PC_CODE_15___S 0 +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15___M 0x00000F1F +#define PHYA_IRON2G_RFA_BT_TXBB_BT_TXBB_RCF_0_15___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0 (0x005DCC00) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0___POR 0x70008884 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_BT_TXLO_POSTBUF_CTRL___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_PA_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_DA_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_PA_IBIAS_LOWER_LIM_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_DA_IBIAS_LOWER_LIM_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_BT_TXMIX_IQTIED_EN___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_PPA_INPUT_SW_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_PA_CAS_BIAS_AUX1_PD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_PA_CAS_BIAS_AUX0_PD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_BT_TXMIX_LOBIAS_Q___POR 0x8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_BT_TXMIX_LOBIAS_I___POR 0x8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_DA_BIAS_NOISE_CNCL_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_DA_BIAS_NOISE_CNCL_RES___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_BT_TXLO_POSTBUF_CTRL___M 0x70000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_BT_TXLO_POSTBUF_CTRL___S 28 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_PA_ATB_SEL___M 0x00E00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_PA_ATB_SEL___S 21 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_DA_ATB_SEL___M 0x001C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_DA_ATB_SEL___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_PA_IBIAS_LOWER_LIM_EN___M 0x00020000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_PA_IBIAS_LOWER_LIM_EN___S 17 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_DA_IBIAS_LOWER_LIM_EN___M 0x00010000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_DA_IBIAS_LOWER_LIM_EN___S 16 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_BT_TXMIX_IQTIED_EN___M 0x00008000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_BT_TXMIX_IQTIED_EN___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_PPA_INPUT_SW_EN___M 0x00004000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_PPA_INPUT_SW_EN___S 14 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_PA_CAS_BIAS_AUX1_PD___M 0x00002000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_PA_CAS_BIAS_AUX1_PD___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_PA_CAS_BIAS_AUX0_PD___M 0x00001000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_PA_CAS_BIAS_AUX0_PD___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_BT_TXMIX_LOBIAS_Q___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_BT_TXMIX_LOBIAS_Q___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_BT_TXMIX_LOBIAS_I___M 0x000000F0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_BT_TXMIX_LOBIAS_I___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_DA_BIAS_NOISE_CNCL_EN___M 0x00000008 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_DA_BIAS_NOISE_CNCL_EN___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_DA_BIAS_NOISE_CNCL_RES___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0__D_SHRD_DA_BIAS_NOISE_CNCL_RES___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0___M 0x70FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_0___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1 (0x005DCC04) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1__D_SHRD_DTOP_CAL_DUMMY1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1__D_SHRD_DTOP_CAL_DUMMY0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1__D_SHRD_DTOP_DUMMY1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1__D_SHRD_DTOP_DUMMY0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1__D_SHRD_DTOP_CAL_DUMMY1___M 0xFF000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1__D_SHRD_DTOP_CAL_DUMMY1___S 24 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1__D_SHRD_DTOP_CAL_DUMMY0___M 0x00FF0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1__D_SHRD_DTOP_CAL_DUMMY0___S 16 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1__D_SHRD_DTOP_DUMMY1___M 0x0000FF00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1__D_SHRD_DTOP_DUMMY1___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1__D_SHRD_DTOP_DUMMY0___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1__D_SHRD_DTOP_DUMMY0___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_STATIC_1___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET (0x005DCC08) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_ATTN_GM_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_RES_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_GC___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_SW_FLP___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_IBIAS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_PHASESHIFT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_ATB_ENN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_ATB_ENP___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_MODE_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_RECT_GC___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_RECT_BLD_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_ATTN_GM_EN___M 0x00040000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_ATTN_GM_EN___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_RES_CTRL___M 0x00020000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_RES_CTRL___S 17 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_GC___M 0x00018000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_GC___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_SW_FLP___M 0x00004000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_SW_FLP___S 14 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_IBIAS___M 0x00003000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_IBIAS___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_PHASESHIFT___M 0x00000800 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_SHRD_CALRTX_PHASESHIFT___S 11 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_ATB_ENN___M 0x00000200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_ATB_ENN___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_ATB_ENP___M 0x00000100 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_ATB_ENP___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_EN___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_MODE_CTRL___M 0x00000040 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_MODE_CTRL___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_RECT_GC___M 0x00000038 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_RECT_GC___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_RECT_BLD_EN___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET__D_BT_TXPDET_RECT_BLD_EN___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET___M 0x0007FBFB +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TX_PDET___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0 (0x005DCC0C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_UPC_CTUNE3FLO_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_UPC_CTUNE3FLO_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_UPC_CTUNE1FLO_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_UPC_CTUNE1FLO_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_IBIAS_LOWER_LIM_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_IBIAS_LOWER_LIM_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_ISLOPE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_ISLOPE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_CTUNE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_CTUNE_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_UPC_CTUNE3FLO_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_UPC_CTUNE3FLO_OV___S 27 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_UPC_CTUNE3FLO_OVD___M 0x07E00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_UPC_CTUNE3FLO_OVD___S 21 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_UPC_CTUNE1FLO_OV___M 0x00100000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_UPC_CTUNE1FLO_OV___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_UPC_CTUNE1FLO_OVD___M 0x000FC000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_UPC_CTUNE1FLO_OVD___S 14 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_IBIAS_LOWER_LIM_OV___M 0x00002000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_IBIAS_LOWER_LIM_OV___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_IBIAS_LOWER_LIM_OVD___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_IBIAS_LOWER_LIM_OVD___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_ISLOPE_OV___M 0x00000200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_ISLOPE_OV___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_ISLOPE_OVD___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_ISLOPE_OVD___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_CTUNE_OV___M 0x00000020 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_CTUNE_OV___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_CTUNE_OVD___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0__D_SHRD_DA_CTUNE_OVD___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0___M 0x0FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_0___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1 (0x005DCC10) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CAS_BIAS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CAS_BIAS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CASOFF_BIAS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CASOFF_BIAS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CELL_EN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CELL_EN_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CELL_AUX_EN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CELL_AUX_EN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CAS_BIAS_OV___M 0x04000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CAS_BIAS_OV___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CAS_BIAS_OVD___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CAS_BIAS_OVD___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CASOFF_BIAS_OV___M 0x00400000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CASOFF_BIAS_OV___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CASOFF_BIAS_OVD___M 0x00380000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CASOFF_BIAS_OVD___S 19 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CELL_EN_OV___M 0x00040000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CELL_EN_OV___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CELL_EN_OVD___M 0x0003FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CELL_EN_OVD___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CELL_AUX_EN_OV___M 0x00000100 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CELL_AUX_EN_OV___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CELL_AUX_EN_OVD___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1__D_SHRD_DA_CELL_AUX_EN_OVD___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1___M 0x07FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_1___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2 (0x005DCC14) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_CAS_BIAS_AUX_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_CAS_BIAS_AUX_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_ILEVEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_ILEVEL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_ILEVEL_COARSE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_ILEVEL_COARSE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_HS_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_HS_CTRL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_IBIAS_LOWER_LIM_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_IBIAS_LOWER_LIM_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_ISLOPE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_ISLOPE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_ILEVEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_ILEVEL_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_CAS_BIAS_AUX_OV___M 0x04000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_CAS_BIAS_AUX_OV___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_CAS_BIAS_AUX_OVD___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_CAS_BIAS_AUX_OVD___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_ILEVEL_OV___M 0x00400000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_ILEVEL_OV___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_ILEVEL_OVD___M 0x00300000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_ILEVEL_OVD___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_ILEVEL_COARSE_OV___M 0x00080000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_ILEVEL_COARSE_OV___S 19 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_ILEVEL_COARSE_OVD___M 0x00060000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_ILEVEL_COARSE_OVD___S 17 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_HS_CTRL_OV___M 0x00010000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_HS_CTRL_OV___S 16 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_HS_CTRL_OVD___M 0x0000C000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_DA_HS_CTRL_OVD___S 14 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_IBIAS_LOWER_LIM_OV___M 0x00002000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_IBIAS_LOWER_LIM_OV___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_IBIAS_LOWER_LIM_OVD___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_IBIAS_LOWER_LIM_OVD___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_ISLOPE_OV___M 0x00000200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_ISLOPE_OV___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_ISLOPE_OVD___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_ISLOPE_OVD___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_ILEVEL_OV___M 0x00000020 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_ILEVEL_OV___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_ILEVEL_OVD___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2__D_SHRD_PA_ILEVEL_OVD___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2___M 0x07FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_2___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3 (0x005DCC18) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX1_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX1_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX0_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX0_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CASOFF_BIAS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CASOFF_BIAS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CELL_EN1_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CELL_EN1_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX1_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX1_OV___S 27 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX1_OVD___M 0x07000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX1_OVD___S 24 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX0_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX0_OV___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX0_OVD___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX0_OVD___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_OV___M 0x00080000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_OV___S 19 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_OVD___M 0x00078000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_OVD___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CASOFF_BIAS_OV___M 0x00004000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CASOFF_BIAS_OV___S 14 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CASOFF_BIAS_OVD___M 0x00003800 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CASOFF_BIAS_OVD___S 11 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CELL_EN1_OV___M 0x00000400 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CELL_EN1_OV___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CELL_EN1_OVD___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3__D_SHRD_PA_CELL_EN1_OVD___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3___M 0x0FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_3___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4 (0x005DCC1C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_CELL_EN0_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_CELL_EN0_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_CELL_FB_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_CELL_FB_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_IBIAS_MODE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_IBIAS_MODE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OV___S 31 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OVD___M 0x7C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OVD___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_CELL_EN0_OV___M 0x01000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_CELL_EN0_OV___S 24 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_CELL_EN0_OVD___M 0x00FFC000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_CELL_EN0_OVD___S 14 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_CELL_FB_OV___M 0x00002000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_CELL_FB_OV___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_CELL_FB_OVD___M 0x00001FF8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_CELL_FB_OVD___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_IBIAS_MODE_OV___M 0x00000004 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_IBIAS_MODE_OV___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_IBIAS_MODE_OVD___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4__D_SHRD_PA_IBIAS_MODE_OVD___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4___M 0xFDFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_4___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5 (0x005DCC20) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_BT_TXLO_I_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_BT_TXLO_Q_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_BT_TXMIX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_SHRD_DA_BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_SHRD_PA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_BT_TXLO_I_EN_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_BT_TXLO_I_EN_OVS___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_BT_TXLO_Q_EN_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_BT_TXLO_Q_EN_OVS___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_BT_TXMIX_EN_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_BT_TXMIX_EN_OVS___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_SHRD_DA_BIAS_EN_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_SHRD_DA_BIAS_EN_OVS___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_SHRD_PA_EN_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5__D_SHRD_PA_EN_OVS___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_TXFE_OV_5___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL (0x005DCC24) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__DA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__DA_GAIN_OV___M 0x00020000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__DA_GAIN_OV___S 17 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___M 0x0001F000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___M 0x00000800 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___S 11 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___M 0x000007C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___M 0x00000020 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL___M 0x0003FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_LUT_IDX_SEL___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL (0x005DCC2C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL__RO_DA_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL__RO_IPA_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL__RO_UPC_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL__RO_DA_GAIN___M 0x0001F000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL__RO_DA_GAIN___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL__RO_IPA_GAIN___M 0x000007C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL__RO_IPA_GAIN___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL__RO_UPC_GAIN___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL__RO_UPC_GAIN___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL___M 0x0001F7DF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_RO_TXFE_LUT_IDX_SEL___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_0 (0x005DCC30) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_0__UPC_CTUNE3FLO_0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_0__UPC_CTUNE1FLO_0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_0__UPC_CTUNE3FLO_0___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_0__UPC_CTUNE3FLO_0___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_0__UPC_CTUNE1FLO_0___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_0__UPC_CTUNE1FLO_0___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_0___M 0x00003F3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_0___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_1 (0x005DCC34) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_1__UPC_CTUNE3FLO_1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_1__UPC_CTUNE1FLO_1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_1__UPC_CTUNE3FLO_1___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_1__UPC_CTUNE3FLO_1___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_1__UPC_CTUNE1FLO_1___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_1__UPC_CTUNE1FLO_1___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_1___M 0x00003F3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_1___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_2 (0x005DCC38) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_2__UPC_CTUNE3FLO_2___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_2__UPC_CTUNE1FLO_2___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_2__UPC_CTUNE3FLO_2___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_2__UPC_CTUNE3FLO_2___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_2__UPC_CTUNE1FLO_2___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_2__UPC_CTUNE1FLO_2___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_2___M 0x00003F3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_2___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_3 (0x005DCC3C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_3__UPC_CTUNE3FLO_3___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_3__UPC_CTUNE1FLO_3___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_3__UPC_CTUNE3FLO_3___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_3__UPC_CTUNE3FLO_3___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_3__UPC_CTUNE1FLO_3___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_3__UPC_CTUNE1FLO_3___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_3___M 0x00003F3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_3___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_4 (0x005DCC40) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_4__UPC_CTUNE3FLO_4___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_4__UPC_CTUNE1FLO_4___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_4__UPC_CTUNE3FLO_4___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_4__UPC_CTUNE3FLO_4___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_4__UPC_CTUNE1FLO_4___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_4__UPC_CTUNE1FLO_4___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_4___M 0x00003F3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_4___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_5 (0x005DCC44) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_5__UPC_CTUNE3FLO_5___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_5__UPC_CTUNE1FLO_5___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_5__UPC_CTUNE3FLO_5___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_5__UPC_CTUNE3FLO_5___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_5__UPC_CTUNE1FLO_5___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_5__UPC_CTUNE1FLO_5___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_5___M 0x00003F3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_5___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_6 (0x005DCC48) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_6__UPC_CTUNE3FLO_6___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_6__UPC_CTUNE1FLO_6___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_6__UPC_CTUNE3FLO_6___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_6__UPC_CTUNE3FLO_6___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_6__UPC_CTUNE1FLO_6___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_6__UPC_CTUNE1FLO_6___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_6___M 0x00003F3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_6___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_7 (0x005DCC4C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_7__UPC_CTUNE3FLO_7___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_7__UPC_CTUNE1FLO_7___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_7__UPC_CTUNE3FLO_7___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_7__UPC_CTUNE3FLO_7___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_7__UPC_CTUNE1FLO_7___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_7__UPC_CTUNE1FLO_7___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_7___M 0x00003F3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_7___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_8 (0x005DCC50) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_8__UPC_CTUNE3FLO_8___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_8__UPC_CTUNE1FLO_8___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_8__UPC_CTUNE3FLO_8___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_8__UPC_CTUNE3FLO_8___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_8__UPC_CTUNE1FLO_8___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_8__UPC_CTUNE1FLO_8___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_8___M 0x00003F3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_8___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_9 (0x005DCC54) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_9__UPC_CTUNE3FLO_9___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_9__UPC_CTUNE1FLO_9___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_9__UPC_CTUNE3FLO_9___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_9__UPC_CTUNE3FLO_9___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_9__UPC_CTUNE1FLO_9___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_9__UPC_CTUNE1FLO_9___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_9___M 0x00003F3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_9___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_10 (0x005DCC58) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_10__UPC_CTUNE3FLO_10___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_10__UPC_CTUNE1FLO_10___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_10__UPC_CTUNE3FLO_10___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_10__UPC_CTUNE3FLO_10___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_10__UPC_CTUNE1FLO_10___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_10__UPC_CTUNE1FLO_10___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_10___M 0x00003F3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_10___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_11 (0x005DCC5C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_11__UPC_CTUNE3FLO_11___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_11__UPC_CTUNE1FLO_11___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_11__UPC_CTUNE3FLO_11___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_11__UPC_CTUNE3FLO_11___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_11__UPC_CTUNE1FLO_11___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_11__UPC_CTUNE1FLO_11___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_11___M 0x00003F3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_11___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_12 (0x005DCC60) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_12__UPC_CTUNE3FLO_12___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_12__UPC_CTUNE1FLO_12___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_12__UPC_CTUNE3FLO_12___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_12__UPC_CTUNE3FLO_12___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_12__UPC_CTUNE1FLO_12___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_12__UPC_CTUNE1FLO_12___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_12___M 0x00003F3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_12___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_13 (0x005DCC64) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_13__UPC_CTUNE3FLO_13___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_13__UPC_CTUNE1FLO_13___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_13__UPC_CTUNE3FLO_13___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_13__UPC_CTUNE3FLO_13___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_13__UPC_CTUNE1FLO_13___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_13__UPC_CTUNE1FLO_13___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_13___M 0x00003F3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_13___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_14 (0x005DCC68) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_14__UPC_CTUNE3FLO_14___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_14__UPC_CTUNE1FLO_14___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_14__UPC_CTUNE3FLO_14___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_14__UPC_CTUNE3FLO_14___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_14__UPC_CTUNE1FLO_14___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_14__UPC_CTUNE1FLO_14___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_14___M 0x00003F3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_14___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_15 (0x005DCC6C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_15__UPC_CTUNE3FLO_15___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_15__UPC_CTUNE1FLO_15___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_15__UPC_CTUNE3FLO_15___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_15__UPC_CTUNE3FLO_15___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_15__UPC_CTUNE1FLO_15___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_15__UPC_CTUNE1FLO_15___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_15___M 0x00003F3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_UPC_0_15___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0 (0x005DCC70) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_IBIAS_LOWER_LIM_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_ISLOPE_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_CTUNE_0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_CAS_BIAS_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_CASOFF_BIAS_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_CELL_EN_0___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_IBIAS_LOWER_LIM_0___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_IBIAS_LOWER_LIM_0___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_ISLOPE_0___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_ISLOPE_0___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_CTUNE_0___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_CTUNE_0___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_CAS_BIAS_0___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_CAS_BIAS_0___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_CASOFF_BIAS_0___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_CASOFF_BIAS_0___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_CELL_EN_0___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0__DA_CELL_EN_0___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_0___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1 (0x005DCC74) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_IBIAS_LOWER_LIM_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_ISLOPE_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_CTUNE_1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_CAS_BIAS_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_CASOFF_BIAS_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_CELL_EN_1___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_IBIAS_LOWER_LIM_1___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_IBIAS_LOWER_LIM_1___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_ISLOPE_1___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_ISLOPE_1___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_CTUNE_1___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_CTUNE_1___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_CAS_BIAS_1___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_CAS_BIAS_1___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_CASOFF_BIAS_1___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_CASOFF_BIAS_1___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_CELL_EN_1___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1__DA_CELL_EN_1___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_1___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2 (0x005DCC78) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_IBIAS_LOWER_LIM_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_ISLOPE_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_CTUNE_2___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_CAS_BIAS_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_CASOFF_BIAS_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_CELL_EN_2___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_IBIAS_LOWER_LIM_2___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_IBIAS_LOWER_LIM_2___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_ISLOPE_2___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_ISLOPE_2___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_CTUNE_2___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_CTUNE_2___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_CAS_BIAS_2___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_CAS_BIAS_2___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_CASOFF_BIAS_2___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_CASOFF_BIAS_2___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_CELL_EN_2___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2__DA_CELL_EN_2___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_2___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3 (0x005DCC7C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_IBIAS_LOWER_LIM_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_ISLOPE_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_CTUNE_3___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_CAS_BIAS_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_CASOFF_BIAS_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_CELL_EN_3___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_IBIAS_LOWER_LIM_3___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_IBIAS_LOWER_LIM_3___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_ISLOPE_3___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_ISLOPE_3___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_CTUNE_3___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_CTUNE_3___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_CAS_BIAS_3___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_CAS_BIAS_3___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_CASOFF_BIAS_3___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_CASOFF_BIAS_3___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_CELL_EN_3___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3__DA_CELL_EN_3___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_3___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4 (0x005DCC80) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_IBIAS_LOWER_LIM_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_ISLOPE_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_CTUNE_4___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_CAS_BIAS_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_CASOFF_BIAS_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_CELL_EN_4___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_IBIAS_LOWER_LIM_4___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_IBIAS_LOWER_LIM_4___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_ISLOPE_4___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_ISLOPE_4___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_CTUNE_4___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_CTUNE_4___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_CAS_BIAS_4___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_CAS_BIAS_4___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_CASOFF_BIAS_4___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_CASOFF_BIAS_4___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_CELL_EN_4___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4__DA_CELL_EN_4___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_4___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5 (0x005DCC84) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_IBIAS_LOWER_LIM_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_ISLOPE_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_CTUNE_5___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_CAS_BIAS_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_CASOFF_BIAS_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_CELL_EN_5___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_IBIAS_LOWER_LIM_5___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_IBIAS_LOWER_LIM_5___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_ISLOPE_5___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_ISLOPE_5___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_CTUNE_5___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_CTUNE_5___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_CAS_BIAS_5___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_CAS_BIAS_5___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_CASOFF_BIAS_5___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_CASOFF_BIAS_5___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_CELL_EN_5___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5__DA_CELL_EN_5___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_5___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6 (0x005DCC88) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_IBIAS_LOWER_LIM_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_ISLOPE_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_CTUNE_6___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_CAS_BIAS_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_CASOFF_BIAS_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_CELL_EN_6___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_IBIAS_LOWER_LIM_6___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_IBIAS_LOWER_LIM_6___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_ISLOPE_6___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_ISLOPE_6___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_CTUNE_6___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_CTUNE_6___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_CAS_BIAS_6___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_CAS_BIAS_6___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_CASOFF_BIAS_6___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_CASOFF_BIAS_6___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_CELL_EN_6___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6__DA_CELL_EN_6___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_6___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7 (0x005DCC8C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_IBIAS_LOWER_LIM_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_ISLOPE_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_CTUNE_7___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_CAS_BIAS_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_CASOFF_BIAS_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_CELL_EN_7___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_IBIAS_LOWER_LIM_7___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_IBIAS_LOWER_LIM_7___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_ISLOPE_7___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_ISLOPE_7___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_CTUNE_7___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_CTUNE_7___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_CAS_BIAS_7___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_CAS_BIAS_7___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_CASOFF_BIAS_7___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_CASOFF_BIAS_7___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_CELL_EN_7___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7__DA_CELL_EN_7___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_7___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8 (0x005DCC90) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_IBIAS_LOWER_LIM_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_ISLOPE_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_CTUNE_8___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_CAS_BIAS_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_CASOFF_BIAS_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_CELL_EN_8___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_IBIAS_LOWER_LIM_8___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_IBIAS_LOWER_LIM_8___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_ISLOPE_8___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_ISLOPE_8___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_CTUNE_8___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_CTUNE_8___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_CAS_BIAS_8___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_CAS_BIAS_8___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_CASOFF_BIAS_8___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_CASOFF_BIAS_8___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_CELL_EN_8___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8__DA_CELL_EN_8___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_8___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9 (0x005DCC94) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_IBIAS_LOWER_LIM_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_ISLOPE_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_CTUNE_9___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_CAS_BIAS_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_CASOFF_BIAS_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_CELL_EN_9___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_IBIAS_LOWER_LIM_9___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_IBIAS_LOWER_LIM_9___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_ISLOPE_9___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_ISLOPE_9___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_CTUNE_9___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_CTUNE_9___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_CAS_BIAS_9___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_CAS_BIAS_9___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_CASOFF_BIAS_9___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_CASOFF_BIAS_9___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_CELL_EN_9___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9__DA_CELL_EN_9___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_9___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10 (0x005DCC98) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_IBIAS_LOWER_LIM_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_ISLOPE_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_CTUNE_10___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_CAS_BIAS_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_CASOFF_BIAS_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_CELL_EN_10___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_IBIAS_LOWER_LIM_10___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_IBIAS_LOWER_LIM_10___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_ISLOPE_10___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_ISLOPE_10___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_CTUNE_10___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_CTUNE_10___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_CAS_BIAS_10___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_CAS_BIAS_10___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_CASOFF_BIAS_10___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_CASOFF_BIAS_10___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_CELL_EN_10___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10__DA_CELL_EN_10___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_10___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11 (0x005DCC9C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_IBIAS_LOWER_LIM_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_ISLOPE_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_CTUNE_11___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_CAS_BIAS_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_CASOFF_BIAS_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_CELL_EN_11___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_IBIAS_LOWER_LIM_11___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_IBIAS_LOWER_LIM_11___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_ISLOPE_11___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_ISLOPE_11___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_CTUNE_11___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_CTUNE_11___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_CAS_BIAS_11___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_CAS_BIAS_11___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_CASOFF_BIAS_11___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_CASOFF_BIAS_11___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_CELL_EN_11___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11__DA_CELL_EN_11___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_11___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12 (0x005DCCA0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_IBIAS_LOWER_LIM_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_ISLOPE_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_CTUNE_12___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_CAS_BIAS_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_CASOFF_BIAS_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_CELL_EN_12___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_IBIAS_LOWER_LIM_12___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_IBIAS_LOWER_LIM_12___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_ISLOPE_12___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_ISLOPE_12___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_CTUNE_12___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_CTUNE_12___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_CAS_BIAS_12___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_CAS_BIAS_12___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_CASOFF_BIAS_12___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_CASOFF_BIAS_12___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_CELL_EN_12___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12__DA_CELL_EN_12___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_12___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13 (0x005DCCA4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_IBIAS_LOWER_LIM_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_ISLOPE_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_CTUNE_13___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_CAS_BIAS_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_CASOFF_BIAS_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_CELL_EN_13___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_IBIAS_LOWER_LIM_13___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_IBIAS_LOWER_LIM_13___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_ISLOPE_13___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_ISLOPE_13___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_CTUNE_13___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_CTUNE_13___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_CAS_BIAS_13___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_CAS_BIAS_13___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_CASOFF_BIAS_13___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_CASOFF_BIAS_13___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_CELL_EN_13___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13__DA_CELL_EN_13___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_13___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14 (0x005DCCA8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_IBIAS_LOWER_LIM_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_ISLOPE_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_CTUNE_14___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_CAS_BIAS_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_CASOFF_BIAS_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_CELL_EN_14___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_IBIAS_LOWER_LIM_14___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_IBIAS_LOWER_LIM_14___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_ISLOPE_14___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_ISLOPE_14___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_CTUNE_14___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_CTUNE_14___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_CAS_BIAS_14___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_CAS_BIAS_14___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_CASOFF_BIAS_14___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_CASOFF_BIAS_14___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_CELL_EN_14___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14__DA_CELL_EN_14___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_14___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15 (0x005DCCAC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_IBIAS_LOWER_LIM_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_ISLOPE_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_CTUNE_15___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_CAS_BIAS_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_CASOFF_BIAS_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_CELL_EN_15___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_IBIAS_LOWER_LIM_15___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_IBIAS_LOWER_LIM_15___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_ISLOPE_15___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_ISLOPE_15___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_CTUNE_15___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_CTUNE_15___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_CAS_BIAS_15___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_CAS_BIAS_15___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_CASOFF_BIAS_15___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_CASOFF_BIAS_15___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_CELL_EN_15___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15__DA_CELL_EN_15___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_0_15___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0 (0x005DCCB0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_CELL_AUX_EN_0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_CAS_BIAS_AUX_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_ILEVEL_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_ILEVEL_COARSE_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_HS_CTRL_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_CELL_AUX_EN_0___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_CELL_AUX_EN_0___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_CAS_BIAS_AUX_0___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_CAS_BIAS_AUX_0___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_ILEVEL_0___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_ILEVEL_0___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_ILEVEL_COARSE_0___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_ILEVEL_COARSE_0___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_HS_CTRL_0___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0__DA_HS_CTRL_0___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0___M 0x0001FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_0___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1 (0x005DCCB4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_CELL_AUX_EN_1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_CAS_BIAS_AUX_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_ILEVEL_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_ILEVEL_COARSE_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_HS_CTRL_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_CELL_AUX_EN_1___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_CELL_AUX_EN_1___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_CAS_BIAS_AUX_1___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_CAS_BIAS_AUX_1___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_ILEVEL_1___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_ILEVEL_1___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_ILEVEL_COARSE_1___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_ILEVEL_COARSE_1___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_HS_CTRL_1___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1__DA_HS_CTRL_1___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1___M 0x0001FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_1___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2 (0x005DCCB8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_CELL_AUX_EN_2___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_CAS_BIAS_AUX_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_ILEVEL_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_ILEVEL_COARSE_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_HS_CTRL_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_CELL_AUX_EN_2___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_CELL_AUX_EN_2___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_CAS_BIAS_AUX_2___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_CAS_BIAS_AUX_2___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_ILEVEL_2___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_ILEVEL_2___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_ILEVEL_COARSE_2___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_ILEVEL_COARSE_2___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_HS_CTRL_2___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2__DA_HS_CTRL_2___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2___M 0x0001FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_2___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3 (0x005DCCBC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_CELL_AUX_EN_3___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_CAS_BIAS_AUX_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_ILEVEL_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_ILEVEL_COARSE_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_HS_CTRL_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_CELL_AUX_EN_3___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_CELL_AUX_EN_3___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_CAS_BIAS_AUX_3___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_CAS_BIAS_AUX_3___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_ILEVEL_3___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_ILEVEL_3___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_ILEVEL_COARSE_3___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_ILEVEL_COARSE_3___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_HS_CTRL_3___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3__DA_HS_CTRL_3___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3___M 0x0001FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_3___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4 (0x005DCCC0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_CELL_AUX_EN_4___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_CAS_BIAS_AUX_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_ILEVEL_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_ILEVEL_COARSE_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_HS_CTRL_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_CELL_AUX_EN_4___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_CELL_AUX_EN_4___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_CAS_BIAS_AUX_4___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_CAS_BIAS_AUX_4___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_ILEVEL_4___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_ILEVEL_4___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_ILEVEL_COARSE_4___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_ILEVEL_COARSE_4___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_HS_CTRL_4___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4__DA_HS_CTRL_4___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4___M 0x0001FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_4___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5 (0x005DCCC4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_CELL_AUX_EN_5___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_CAS_BIAS_AUX_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_ILEVEL_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_ILEVEL_COARSE_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_HS_CTRL_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_CELL_AUX_EN_5___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_CELL_AUX_EN_5___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_CAS_BIAS_AUX_5___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_CAS_BIAS_AUX_5___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_ILEVEL_5___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_ILEVEL_5___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_ILEVEL_COARSE_5___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_ILEVEL_COARSE_5___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_HS_CTRL_5___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5__DA_HS_CTRL_5___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5___M 0x0001FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_5___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6 (0x005DCCC8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_CELL_AUX_EN_6___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_CAS_BIAS_AUX_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_ILEVEL_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_ILEVEL_COARSE_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_HS_CTRL_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_CELL_AUX_EN_6___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_CELL_AUX_EN_6___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_CAS_BIAS_AUX_6___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_CAS_BIAS_AUX_6___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_ILEVEL_6___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_ILEVEL_6___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_ILEVEL_COARSE_6___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_ILEVEL_COARSE_6___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_HS_CTRL_6___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6__DA_HS_CTRL_6___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6___M 0x0001FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_6___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7 (0x005DCCCC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_CELL_AUX_EN_7___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_CAS_BIAS_AUX_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_ILEVEL_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_ILEVEL_COARSE_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_HS_CTRL_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_CELL_AUX_EN_7___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_CELL_AUX_EN_7___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_CAS_BIAS_AUX_7___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_CAS_BIAS_AUX_7___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_ILEVEL_7___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_ILEVEL_7___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_ILEVEL_COARSE_7___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_ILEVEL_COARSE_7___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_HS_CTRL_7___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7__DA_HS_CTRL_7___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7___M 0x0001FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_7___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8 (0x005DCCD0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_CELL_AUX_EN_8___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_CAS_BIAS_AUX_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_ILEVEL_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_ILEVEL_COARSE_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_HS_CTRL_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_CELL_AUX_EN_8___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_CELL_AUX_EN_8___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_CAS_BIAS_AUX_8___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_CAS_BIAS_AUX_8___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_ILEVEL_8___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_ILEVEL_8___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_ILEVEL_COARSE_8___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_ILEVEL_COARSE_8___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_HS_CTRL_8___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8__DA_HS_CTRL_8___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8___M 0x0001FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_8___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9 (0x005DCCD4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_CELL_AUX_EN_9___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_CAS_BIAS_AUX_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_ILEVEL_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_ILEVEL_COARSE_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_HS_CTRL_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_CELL_AUX_EN_9___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_CELL_AUX_EN_9___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_CAS_BIAS_AUX_9___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_CAS_BIAS_AUX_9___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_ILEVEL_9___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_ILEVEL_9___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_ILEVEL_COARSE_9___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_ILEVEL_COARSE_9___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_HS_CTRL_9___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9__DA_HS_CTRL_9___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9___M 0x0001FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_9___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10 (0x005DCCD8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_CELL_AUX_EN_10___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_CAS_BIAS_AUX_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_ILEVEL_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_ILEVEL_COARSE_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_HS_CTRL_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_CELL_AUX_EN_10___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_CELL_AUX_EN_10___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_CAS_BIAS_AUX_10___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_CAS_BIAS_AUX_10___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_ILEVEL_10___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_ILEVEL_10___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_ILEVEL_COARSE_10___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_ILEVEL_COARSE_10___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_HS_CTRL_10___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10__DA_HS_CTRL_10___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10___M 0x0001FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_10___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11 (0x005DCCDC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_CELL_AUX_EN_11___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_CAS_BIAS_AUX_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_ILEVEL_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_ILEVEL_COARSE_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_HS_CTRL_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_CELL_AUX_EN_11___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_CELL_AUX_EN_11___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_CAS_BIAS_AUX_11___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_CAS_BIAS_AUX_11___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_ILEVEL_11___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_ILEVEL_11___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_ILEVEL_COARSE_11___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_ILEVEL_COARSE_11___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_HS_CTRL_11___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11__DA_HS_CTRL_11___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11___M 0x0001FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_11___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12 (0x005DCCE0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_CELL_AUX_EN_12___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_CAS_BIAS_AUX_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_ILEVEL_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_ILEVEL_COARSE_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_HS_CTRL_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_CELL_AUX_EN_12___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_CELL_AUX_EN_12___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_CAS_BIAS_AUX_12___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_CAS_BIAS_AUX_12___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_ILEVEL_12___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_ILEVEL_12___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_ILEVEL_COARSE_12___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_ILEVEL_COARSE_12___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_HS_CTRL_12___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12__DA_HS_CTRL_12___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12___M 0x0001FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_12___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13 (0x005DCCE4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_CELL_AUX_EN_13___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_CAS_BIAS_AUX_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_ILEVEL_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_ILEVEL_COARSE_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_HS_CTRL_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_CELL_AUX_EN_13___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_CELL_AUX_EN_13___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_CAS_BIAS_AUX_13___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_CAS_BIAS_AUX_13___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_ILEVEL_13___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_ILEVEL_13___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_ILEVEL_COARSE_13___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_ILEVEL_COARSE_13___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_HS_CTRL_13___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13__DA_HS_CTRL_13___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13___M 0x0001FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_13___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14 (0x005DCCE8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_CELL_AUX_EN_14___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_CAS_BIAS_AUX_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_ILEVEL_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_ILEVEL_COARSE_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_HS_CTRL_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_CELL_AUX_EN_14___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_CELL_AUX_EN_14___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_CAS_BIAS_AUX_14___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_CAS_BIAS_AUX_14___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_ILEVEL_14___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_ILEVEL_14___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_ILEVEL_COARSE_14___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_ILEVEL_COARSE_14___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_HS_CTRL_14___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14__DA_HS_CTRL_14___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14___M 0x0001FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_14___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15 (0x005DCCEC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_CELL_AUX_EN_15___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_CAS_BIAS_AUX_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_ILEVEL_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_ILEVEL_COARSE_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_HS_CTRL_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_CELL_AUX_EN_15___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_CELL_AUX_EN_15___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_CAS_BIAS_AUX_15___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_CAS_BIAS_AUX_15___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_ILEVEL_15___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_ILEVEL_15___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_ILEVEL_COARSE_15___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_ILEVEL_COARSE_15___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_HS_CTRL_15___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15__DA_HS_CTRL_15___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15___M 0x0001FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_DA_1_15___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0 (0x005DCCF0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_IBIAS_LOWER_LIM_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_ISLOPE_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_ILEVEL_0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_ILEVEL_B2_0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX1_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX0_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CAS_BIAS_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CASOFF_BIAS_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_IBIAS_LOWER_LIM_0___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_IBIAS_LOWER_LIM_0___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_ISLOPE_0___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_ISLOPE_0___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_ILEVEL_0___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_ILEVEL_0___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_ILEVEL_B2_0___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_ILEVEL_B2_0___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX1_0___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX1_0___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX0_0___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX0_0___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CAS_BIAS_0___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CAS_BIAS_0___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CASOFF_BIAS_0___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0__PA_CASOFF_BIAS_0___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_0___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1 (0x005DCCF4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_IBIAS_LOWER_LIM_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_ISLOPE_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_ILEVEL_1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_ILEVEL_B2_1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX1_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX0_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CAS_BIAS_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CASOFF_BIAS_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_IBIAS_LOWER_LIM_1___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_IBIAS_LOWER_LIM_1___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_ISLOPE_1___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_ISLOPE_1___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_ILEVEL_1___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_ILEVEL_1___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_ILEVEL_B2_1___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_ILEVEL_B2_1___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX1_1___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX1_1___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX0_1___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX0_1___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CAS_BIAS_1___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CAS_BIAS_1___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CASOFF_BIAS_1___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1__PA_CASOFF_BIAS_1___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_1___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2 (0x005DCCF8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_IBIAS_LOWER_LIM_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_ISLOPE_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_ILEVEL_2___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_ILEVEL_B2_2___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX1_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX0_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CAS_BIAS_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CASOFF_BIAS_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_IBIAS_LOWER_LIM_2___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_IBIAS_LOWER_LIM_2___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_ISLOPE_2___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_ISLOPE_2___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_ILEVEL_2___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_ILEVEL_2___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_ILEVEL_B2_2___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_ILEVEL_B2_2___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX1_2___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX1_2___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX0_2___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX0_2___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CAS_BIAS_2___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CAS_BIAS_2___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CASOFF_BIAS_2___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2__PA_CASOFF_BIAS_2___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_2___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3 (0x005DCCFC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_IBIAS_LOWER_LIM_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_ISLOPE_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_ILEVEL_3___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_ILEVEL_B2_3___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX1_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX0_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CAS_BIAS_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CASOFF_BIAS_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_IBIAS_LOWER_LIM_3___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_IBIAS_LOWER_LIM_3___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_ISLOPE_3___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_ISLOPE_3___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_ILEVEL_3___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_ILEVEL_3___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_ILEVEL_B2_3___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_ILEVEL_B2_3___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX1_3___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX1_3___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX0_3___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX0_3___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CAS_BIAS_3___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CAS_BIAS_3___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CASOFF_BIAS_3___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3__PA_CASOFF_BIAS_3___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_3___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4 (0x005DCD00) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_IBIAS_LOWER_LIM_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_ISLOPE_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_ILEVEL_4___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_ILEVEL_B2_4___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX1_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX0_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CAS_BIAS_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CASOFF_BIAS_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_IBIAS_LOWER_LIM_4___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_IBIAS_LOWER_LIM_4___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_ISLOPE_4___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_ISLOPE_4___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_ILEVEL_4___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_ILEVEL_4___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_ILEVEL_B2_4___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_ILEVEL_B2_4___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX1_4___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX1_4___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX0_4___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX0_4___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CAS_BIAS_4___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CAS_BIAS_4___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CASOFF_BIAS_4___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4__PA_CASOFF_BIAS_4___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_4___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5 (0x005DCD04) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_IBIAS_LOWER_LIM_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_ISLOPE_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_ILEVEL_5___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_ILEVEL_B2_5___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX1_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX0_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CAS_BIAS_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CASOFF_BIAS_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_IBIAS_LOWER_LIM_5___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_IBIAS_LOWER_LIM_5___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_ISLOPE_5___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_ISLOPE_5___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_ILEVEL_5___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_ILEVEL_5___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_ILEVEL_B2_5___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_ILEVEL_B2_5___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX1_5___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX1_5___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX0_5___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX0_5___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CAS_BIAS_5___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CAS_BIAS_5___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CASOFF_BIAS_5___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5__PA_CASOFF_BIAS_5___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_5___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6 (0x005DCD08) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_IBIAS_LOWER_LIM_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_ISLOPE_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_ILEVEL_6___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_ILEVEL_B2_6___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX1_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX0_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CAS_BIAS_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CASOFF_BIAS_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_IBIAS_LOWER_LIM_6___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_IBIAS_LOWER_LIM_6___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_ISLOPE_6___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_ISLOPE_6___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_ILEVEL_6___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_ILEVEL_6___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_ILEVEL_B2_6___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_ILEVEL_B2_6___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX1_6___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX1_6___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX0_6___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX0_6___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CAS_BIAS_6___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CAS_BIAS_6___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CASOFF_BIAS_6___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6__PA_CASOFF_BIAS_6___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_6___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7 (0x005DCD0C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_IBIAS_LOWER_LIM_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_ISLOPE_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_ILEVEL_7___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_ILEVEL_B2_7___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX1_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX0_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CAS_BIAS_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CASOFF_BIAS_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_IBIAS_LOWER_LIM_7___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_IBIAS_LOWER_LIM_7___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_ISLOPE_7___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_ISLOPE_7___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_ILEVEL_7___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_ILEVEL_7___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_ILEVEL_B2_7___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_ILEVEL_B2_7___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX1_7___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX1_7___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX0_7___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX0_7___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CAS_BIAS_7___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CAS_BIAS_7___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CASOFF_BIAS_7___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7__PA_CASOFF_BIAS_7___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_7___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8 (0x005DCD10) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_IBIAS_LOWER_LIM_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_ISLOPE_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_ILEVEL_8___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_ILEVEL_B2_8___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX1_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX0_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CAS_BIAS_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CASOFF_BIAS_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_IBIAS_LOWER_LIM_8___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_IBIAS_LOWER_LIM_8___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_ISLOPE_8___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_ISLOPE_8___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_ILEVEL_8___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_ILEVEL_8___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_ILEVEL_B2_8___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_ILEVEL_B2_8___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX1_8___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX1_8___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX0_8___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX0_8___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CAS_BIAS_8___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CAS_BIAS_8___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CASOFF_BIAS_8___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8__PA_CASOFF_BIAS_8___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_8___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9 (0x005DCD14) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_IBIAS_LOWER_LIM_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_ISLOPE_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_ILEVEL_9___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_ILEVEL_B2_9___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX1_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX0_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CAS_BIAS_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CASOFF_BIAS_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_IBIAS_LOWER_LIM_9___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_IBIAS_LOWER_LIM_9___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_ISLOPE_9___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_ISLOPE_9___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_ILEVEL_9___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_ILEVEL_9___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_ILEVEL_B2_9___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_ILEVEL_B2_9___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX1_9___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX1_9___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX0_9___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX0_9___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CAS_BIAS_9___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CAS_BIAS_9___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CASOFF_BIAS_9___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9__PA_CASOFF_BIAS_9___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_9___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10 (0x005DCD18) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_IBIAS_LOWER_LIM_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_ISLOPE_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_ILEVEL_10___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_ILEVEL_B2_10___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX1_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX0_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CAS_BIAS_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CASOFF_BIAS_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_IBIAS_LOWER_LIM_10___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_IBIAS_LOWER_LIM_10___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_ISLOPE_10___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_ISLOPE_10___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_ILEVEL_10___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_ILEVEL_10___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_ILEVEL_B2_10___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_ILEVEL_B2_10___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX1_10___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX1_10___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX0_10___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX0_10___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CAS_BIAS_10___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CAS_BIAS_10___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CASOFF_BIAS_10___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10__PA_CASOFF_BIAS_10___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_10___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11 (0x005DCD1C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_IBIAS_LOWER_LIM_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_ISLOPE_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_ILEVEL_11___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_ILEVEL_B2_11___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX1_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX0_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CAS_BIAS_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CASOFF_BIAS_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_IBIAS_LOWER_LIM_11___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_IBIAS_LOWER_LIM_11___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_ISLOPE_11___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_ISLOPE_11___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_ILEVEL_11___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_ILEVEL_11___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_ILEVEL_B2_11___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_ILEVEL_B2_11___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX1_11___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX1_11___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX0_11___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX0_11___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CAS_BIAS_11___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CAS_BIAS_11___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CASOFF_BIAS_11___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11__PA_CASOFF_BIAS_11___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_11___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12 (0x005DCD20) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_IBIAS_LOWER_LIM_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_ISLOPE_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_ILEVEL_12___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_ILEVEL_B2_12___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX1_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX0_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CAS_BIAS_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CASOFF_BIAS_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_IBIAS_LOWER_LIM_12___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_IBIAS_LOWER_LIM_12___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_ISLOPE_12___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_ISLOPE_12___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_ILEVEL_12___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_ILEVEL_12___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_ILEVEL_B2_12___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_ILEVEL_B2_12___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX1_12___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX1_12___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX0_12___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX0_12___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CAS_BIAS_12___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CAS_BIAS_12___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CASOFF_BIAS_12___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12__PA_CASOFF_BIAS_12___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_12___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13 (0x005DCD24) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_IBIAS_LOWER_LIM_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_ISLOPE_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_ILEVEL_13___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_ILEVEL_B2_13___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX1_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX0_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CAS_BIAS_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CASOFF_BIAS_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_IBIAS_LOWER_LIM_13___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_IBIAS_LOWER_LIM_13___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_ISLOPE_13___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_ISLOPE_13___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_ILEVEL_13___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_ILEVEL_13___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_ILEVEL_B2_13___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_ILEVEL_B2_13___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX1_13___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX1_13___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX0_13___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX0_13___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CAS_BIAS_13___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CAS_BIAS_13___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CASOFF_BIAS_13___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13__PA_CASOFF_BIAS_13___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_13___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14 (0x005DCD28) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_IBIAS_LOWER_LIM_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_ISLOPE_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_ILEVEL_14___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_ILEVEL_B2_14___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX1_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX0_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CAS_BIAS_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CASOFF_BIAS_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_IBIAS_LOWER_LIM_14___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_IBIAS_LOWER_LIM_14___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_ISLOPE_14___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_ISLOPE_14___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_ILEVEL_14___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_ILEVEL_14___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_ILEVEL_B2_14___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_ILEVEL_B2_14___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX1_14___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX1_14___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX0_14___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX0_14___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CAS_BIAS_14___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CAS_BIAS_14___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CASOFF_BIAS_14___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14__PA_CASOFF_BIAS_14___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_14___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15 (0x005DCD2C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_IBIAS_LOWER_LIM_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_ISLOPE_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_ILEVEL_15___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_ILEVEL_B2_15___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX1_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX0_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CAS_BIAS_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CASOFF_BIAS_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_IBIAS_LOWER_LIM_15___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_IBIAS_LOWER_LIM_15___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_ISLOPE_15___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_ISLOPE_15___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_ILEVEL_15___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_ILEVEL_15___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_ILEVEL_B2_15___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_ILEVEL_B2_15___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX1_15___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX1_15___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX0_15___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX0_15___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CAS_BIAS_15___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CAS_BIAS_15___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CASOFF_BIAS_15___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15__PA_CASOFF_BIAS_15___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_0_15___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0 (0x005DCD30) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_CELL_EN1_0___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_CELL_EN0_0___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_CELL_FB_0___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_IBIAS_MODE_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_CELL_EN1_0___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_CELL_EN1_0___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_CELL_EN0_0___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_CELL_EN0_0___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_CELL_FB_0___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_CELL_FB_0___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_IBIAS_MODE_0___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0__PA_IBIAS_MODE_0___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_0___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1 (0x005DCD34) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_CELL_EN1_1___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_CELL_EN0_1___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_CELL_FB_1___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_IBIAS_MODE_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_CELL_EN1_1___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_CELL_EN1_1___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_CELL_EN0_1___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_CELL_EN0_1___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_CELL_FB_1___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_CELL_FB_1___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_IBIAS_MODE_1___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1__PA_IBIAS_MODE_1___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_1___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2 (0x005DCD38) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_CELL_EN1_2___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_CELL_EN0_2___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_CELL_FB_2___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_IBIAS_MODE_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_CELL_EN1_2___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_CELL_EN1_2___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_CELL_EN0_2___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_CELL_EN0_2___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_CELL_FB_2___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_CELL_FB_2___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_IBIAS_MODE_2___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2__PA_IBIAS_MODE_2___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_2___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3 (0x005DCD3C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_CELL_EN1_3___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_CELL_EN0_3___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_CELL_FB_3___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_IBIAS_MODE_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_CELL_EN1_3___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_CELL_EN1_3___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_CELL_EN0_3___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_CELL_EN0_3___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_CELL_FB_3___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_CELL_FB_3___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_IBIAS_MODE_3___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3__PA_IBIAS_MODE_3___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_3___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4 (0x005DCD40) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_CELL_EN1_4___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_CELL_EN0_4___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_CELL_FB_4___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_IBIAS_MODE_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_CELL_EN1_4___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_CELL_EN1_4___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_CELL_EN0_4___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_CELL_EN0_4___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_CELL_FB_4___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_CELL_FB_4___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_IBIAS_MODE_4___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4__PA_IBIAS_MODE_4___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_4___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5 (0x005DCD44) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_CELL_EN1_5___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_CELL_EN0_5___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_CELL_FB_5___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_IBIAS_MODE_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_CELL_EN1_5___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_CELL_EN1_5___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_CELL_EN0_5___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_CELL_EN0_5___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_CELL_FB_5___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_CELL_FB_5___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_IBIAS_MODE_5___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5__PA_IBIAS_MODE_5___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_5___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6 (0x005DCD48) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_CELL_EN1_6___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_CELL_EN0_6___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_CELL_FB_6___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_IBIAS_MODE_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_CELL_EN1_6___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_CELL_EN1_6___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_CELL_EN0_6___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_CELL_EN0_6___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_CELL_FB_6___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_CELL_FB_6___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_IBIAS_MODE_6___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6__PA_IBIAS_MODE_6___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_6___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7 (0x005DCD4C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_CELL_EN1_7___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_CELL_EN0_7___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_CELL_FB_7___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_IBIAS_MODE_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_CELL_EN1_7___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_CELL_EN1_7___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_CELL_EN0_7___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_CELL_EN0_7___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_CELL_FB_7___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_CELL_FB_7___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_IBIAS_MODE_7___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7__PA_IBIAS_MODE_7___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_7___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8 (0x005DCD50) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_CELL_EN1_8___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_CELL_EN0_8___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_CELL_FB_8___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_IBIAS_MODE_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_CELL_EN1_8___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_CELL_EN1_8___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_CELL_EN0_8___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_CELL_EN0_8___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_CELL_FB_8___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_CELL_FB_8___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_IBIAS_MODE_8___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8__PA_IBIAS_MODE_8___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_8___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9 (0x005DCD54) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_CELL_EN1_9___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_CELL_EN0_9___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_CELL_FB_9___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_IBIAS_MODE_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_CELL_EN1_9___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_CELL_EN1_9___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_CELL_EN0_9___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_CELL_EN0_9___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_CELL_FB_9___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_CELL_FB_9___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_IBIAS_MODE_9___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9__PA_IBIAS_MODE_9___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_9___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10 (0x005DCD58) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_CELL_EN1_10___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_CELL_EN0_10___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_CELL_FB_10___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_IBIAS_MODE_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_CELL_EN1_10___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_CELL_EN1_10___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_CELL_EN0_10___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_CELL_EN0_10___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_CELL_FB_10___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_CELL_FB_10___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_IBIAS_MODE_10___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10__PA_IBIAS_MODE_10___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_10___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11 (0x005DCD5C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_CELL_EN1_11___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_CELL_EN0_11___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_CELL_FB_11___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_IBIAS_MODE_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_CELL_EN1_11___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_CELL_EN1_11___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_CELL_EN0_11___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_CELL_EN0_11___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_CELL_FB_11___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_CELL_FB_11___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_IBIAS_MODE_11___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11__PA_IBIAS_MODE_11___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_11___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12 (0x005DCD60) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12__PA_CELL_EN1_12___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12__PA_CELL_EN0_12___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12__PA_CELL_FB_12___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12__PA_IBIAS_MODE_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12__PA_CELL_EN1_12___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12__PA_CELL_EN1_12___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12__PA_CELL_EN0_12___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12__PA_CELL_EN0_12___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12__PA_CELL_FB_12___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12__PA_CELL_FB_12___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12__PA_IBIAS_MODE_12___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12__PA_IBIAS_MODE_12___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_12___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13 (0x005DCD64) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_CELL_EN1_13___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_CELL_EN0_13___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_CELL_FB_13___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_IBIAS_MODE_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_CELL_EN1_13___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_CELL_EN1_13___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_CELL_EN0_13___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_CELL_EN0_13___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_CELL_FB_13___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_CELL_FB_13___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_IBIAS_MODE_13___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13__PA_IBIAS_MODE_13___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_13___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14 (0x005DCD68) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_CELL_EN1_14___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_CELL_EN0_14___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_CELL_FB_14___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_IBIAS_MODE_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_CELL_EN1_14___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_CELL_EN1_14___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_CELL_EN0_14___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_CELL_EN0_14___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_CELL_FB_14___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_CELL_FB_14___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_IBIAS_MODE_14___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14__PA_IBIAS_MODE_14___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_14___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15 (0x005DCD6C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_CELL_EN1_15___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_CELL_EN0_15___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_CELL_FB_15___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_IBIAS_MODE_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_CELL_EN1_15___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_CELL_EN1_15___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_CELL_EN0_15___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_CELL_EN0_15___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_CELL_FB_15___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_CELL_FB_15___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_IBIAS_MODE_15___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15__PA_IBIAS_MODE_15___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH0_BT_TXFE_PA_1_15___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0 (0x005DD000) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0___POR 0x70008884 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_BT_TXLO_POSTBUF_CTRL___POR 0x7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_PA_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_DA_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_PA_IBIAS_LOWER_LIM_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_DA_IBIAS_LOWER_LIM_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_BT_TXMIX_IQTIED_EN___POR 0x1 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_PPA_INPUT_SW_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_PA_CAS_BIAS_AUX1_PD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_PA_CAS_BIAS_AUX0_PD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_BT_TXMIX_LOBIAS_Q___POR 0x8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_BT_TXMIX_LOBIAS_I___POR 0x8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_DA_BIAS_NOISE_CNCL_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_DA_BIAS_NOISE_CNCL_RES___POR 0x4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_BT_TXLO_POSTBUF_CTRL___M 0x70000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_BT_TXLO_POSTBUF_CTRL___S 28 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_PA_ATB_SEL___M 0x00E00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_PA_ATB_SEL___S 21 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_DA_ATB_SEL___M 0x001C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_DA_ATB_SEL___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_PA_IBIAS_LOWER_LIM_EN___M 0x00020000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_PA_IBIAS_LOWER_LIM_EN___S 17 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_DA_IBIAS_LOWER_LIM_EN___M 0x00010000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_DA_IBIAS_LOWER_LIM_EN___S 16 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_BT_TXMIX_IQTIED_EN___M 0x00008000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_BT_TXMIX_IQTIED_EN___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_PPA_INPUT_SW_EN___M 0x00004000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_PPA_INPUT_SW_EN___S 14 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_PA_CAS_BIAS_AUX1_PD___M 0x00002000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_PA_CAS_BIAS_AUX1_PD___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_PA_CAS_BIAS_AUX0_PD___M 0x00001000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_PA_CAS_BIAS_AUX0_PD___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_BT_TXMIX_LOBIAS_Q___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_BT_TXMIX_LOBIAS_Q___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_BT_TXMIX_LOBIAS_I___M 0x000000F0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_BT_TXMIX_LOBIAS_I___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_DA_BIAS_NOISE_CNCL_EN___M 0x00000008 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_DA_BIAS_NOISE_CNCL_EN___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_DA_BIAS_NOISE_CNCL_RES___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0__D_SHRD_DA_BIAS_NOISE_CNCL_RES___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0___M 0x70FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_0___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1 (0x005DD004) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1__D_SHRD_DTOP_CAL_DUMMY1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1__D_SHRD_DTOP_CAL_DUMMY0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1__D_SHRD_DTOP_DUMMY1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1__D_SHRD_DTOP_DUMMY0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1__D_SHRD_DTOP_CAL_DUMMY1___M 0xFF000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1__D_SHRD_DTOP_CAL_DUMMY1___S 24 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1__D_SHRD_DTOP_CAL_DUMMY0___M 0x00FF0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1__D_SHRD_DTOP_CAL_DUMMY0___S 16 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1__D_SHRD_DTOP_DUMMY1___M 0x0000FF00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1__D_SHRD_DTOP_DUMMY1___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1__D_SHRD_DTOP_DUMMY0___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1__D_SHRD_DTOP_DUMMY0___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_STATIC_1___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET (0x005DD008) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_ATTN_GM_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_RES_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_GC___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_SW_FLP___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_IBIAS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_PHASESHIFT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_ATB_ENN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_ATB_ENP___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_MODE_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_RECT_GC___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_RECT_BLD_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_ATTN_GM_EN___M 0x00040000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_ATTN_GM_EN___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_RES_CTRL___M 0x00020000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_RES_CTRL___S 17 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_GC___M 0x00018000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_GC___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_SW_FLP___M 0x00004000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_SW_FLP___S 14 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_IBIAS___M 0x00003000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_IBIAS___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_PHASESHIFT___M 0x00000800 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_SHRD_CALRTX_PHASESHIFT___S 11 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_ATB_ENN___M 0x00000200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_ATB_ENN___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_ATB_ENP___M 0x00000100 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_ATB_ENP___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_EN___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_MODE_CTRL___M 0x00000040 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_MODE_CTRL___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_RECT_GC___M 0x00000038 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_RECT_GC___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_RECT_BLD_EN___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET__D_BT_TXPDET_RECT_BLD_EN___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET___M 0x0007FBFB +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TX_PDET___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0 (0x005DD00C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_UPC_CTUNE3FLO_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_UPC_CTUNE3FLO_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_UPC_CTUNE1FLO_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_UPC_CTUNE1FLO_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_IBIAS_LOWER_LIM_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_IBIAS_LOWER_LIM_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_ISLOPE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_ISLOPE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_CTUNE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_CTUNE_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_UPC_CTUNE3FLO_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_UPC_CTUNE3FLO_OV___S 27 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_UPC_CTUNE3FLO_OVD___M 0x07E00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_UPC_CTUNE3FLO_OVD___S 21 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_UPC_CTUNE1FLO_OV___M 0x00100000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_UPC_CTUNE1FLO_OV___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_UPC_CTUNE1FLO_OVD___M 0x000FC000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_UPC_CTUNE1FLO_OVD___S 14 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_IBIAS_LOWER_LIM_OV___M 0x00002000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_IBIAS_LOWER_LIM_OV___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_IBIAS_LOWER_LIM_OVD___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_IBIAS_LOWER_LIM_OVD___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_ISLOPE_OV___M 0x00000200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_ISLOPE_OV___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_ISLOPE_OVD___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_ISLOPE_OVD___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_CTUNE_OV___M 0x00000020 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_CTUNE_OV___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_CTUNE_OVD___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0__D_SHRD_DA_CTUNE_OVD___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0___M 0x0FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_0___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1 (0x005DD010) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CAS_BIAS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CAS_BIAS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CASOFF_BIAS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CASOFF_BIAS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CELL_EN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CELL_EN_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CELL_AUX_EN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CELL_AUX_EN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CAS_BIAS_OV___M 0x04000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CAS_BIAS_OV___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CAS_BIAS_OVD___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CAS_BIAS_OVD___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CASOFF_BIAS_OV___M 0x00400000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CASOFF_BIAS_OV___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CASOFF_BIAS_OVD___M 0x00380000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CASOFF_BIAS_OVD___S 19 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CELL_EN_OV___M 0x00040000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CELL_EN_OV___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CELL_EN_OVD___M 0x0003FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CELL_EN_OVD___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CELL_AUX_EN_OV___M 0x00000100 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CELL_AUX_EN_OV___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CELL_AUX_EN_OVD___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1__D_SHRD_DA_CELL_AUX_EN_OVD___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1___M 0x07FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_1___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2 (0x005DD014) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_CAS_BIAS_AUX_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_CAS_BIAS_AUX_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_ILEVEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_ILEVEL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_ILEVEL_COARSE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_ILEVEL_COARSE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_HS_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_HS_CTRL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_IBIAS_LOWER_LIM_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_IBIAS_LOWER_LIM_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_ISLOPE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_ISLOPE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_ILEVEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_ILEVEL_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_CAS_BIAS_AUX_OV___M 0x04000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_CAS_BIAS_AUX_OV___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_CAS_BIAS_AUX_OVD___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_CAS_BIAS_AUX_OVD___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_ILEVEL_OV___M 0x00400000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_ILEVEL_OV___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_ILEVEL_OVD___M 0x00300000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_ILEVEL_OVD___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_ILEVEL_COARSE_OV___M 0x00080000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_ILEVEL_COARSE_OV___S 19 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_ILEVEL_COARSE_OVD___M 0x00060000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_ILEVEL_COARSE_OVD___S 17 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_HS_CTRL_OV___M 0x00010000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_HS_CTRL_OV___S 16 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_HS_CTRL_OVD___M 0x0000C000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_DA_HS_CTRL_OVD___S 14 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_IBIAS_LOWER_LIM_OV___M 0x00002000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_IBIAS_LOWER_LIM_OV___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_IBIAS_LOWER_LIM_OVD___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_IBIAS_LOWER_LIM_OVD___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_ISLOPE_OV___M 0x00000200 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_ISLOPE_OV___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_ISLOPE_OVD___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_ISLOPE_OVD___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_ILEVEL_OV___M 0x00000020 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_ILEVEL_OV___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_ILEVEL_OVD___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2__D_SHRD_PA_ILEVEL_OVD___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2___M 0x07FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_2___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3 (0x005DD018) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX1_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX1_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX0_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX0_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CASOFF_BIAS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CASOFF_BIAS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CELL_EN1_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CELL_EN1_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX1_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX1_OV___S 27 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX1_OVD___M 0x07000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX1_OVD___S 24 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX0_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX0_OV___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX0_OVD___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_AUX0_OVD___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_OV___M 0x00080000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_OV___S 19 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_OVD___M 0x00078000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CAS_BIAS_OVD___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CASOFF_BIAS_OV___M 0x00004000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CASOFF_BIAS_OV___S 14 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CASOFF_BIAS_OVD___M 0x00003800 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CASOFF_BIAS_OVD___S 11 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CELL_EN1_OV___M 0x00000400 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CELL_EN1_OV___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CELL_EN1_OVD___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3__D_SHRD_PA_CELL_EN1_OVD___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3___M 0x0FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_3___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4 (0x005DD01C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_CELL_EN0_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_CELL_EN0_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_CELL_FB_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_CELL_FB_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_IBIAS_MODE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_IBIAS_MODE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OV___S 31 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OVD___M 0x7C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_ILEVEL_B2_OVD___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_CELL_EN0_OV___M 0x01000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_CELL_EN0_OV___S 24 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_CELL_EN0_OVD___M 0x00FFC000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_CELL_EN0_OVD___S 14 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_CELL_FB_OV___M 0x00002000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_CELL_FB_OV___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_CELL_FB_OVD___M 0x00001FF8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_CELL_FB_OVD___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_IBIAS_MODE_OV___M 0x00000004 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_IBIAS_MODE_OV___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_IBIAS_MODE_OVD___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4__D_SHRD_PA_IBIAS_MODE_OVD___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4___M 0xFDFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_4___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5 (0x005DD020) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_BT_TXLO_I_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_BT_TXLO_Q_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_BT_TXMIX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_SHRD_DA_BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_SHRD_PA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_BT_TXLO_I_EN_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_BT_TXLO_I_EN_OVS___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_BT_TXLO_Q_EN_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_BT_TXLO_Q_EN_OVS___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_BT_TXMIX_EN_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_BT_TXMIX_EN_OVS___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_SHRD_DA_BIAS_EN_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_SHRD_DA_BIAS_EN_OVS___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_SHRD_PA_EN_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5__D_SHRD_PA_EN_OVS___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_TXFE_OV_5___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL (0x005DD024) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__DA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__DA_GAIN_OV___M 0x00020000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__DA_GAIN_OV___S 17 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___M 0x0001F000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___M 0x00000800 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___S 11 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___M 0x000007C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___M 0x00000020 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___S 5 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL___M 0x0003FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_LUT_IDX_SEL___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL (0x005DD02C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL__RO_DA_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL__RO_IPA_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL__RO_UPC_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL__RO_DA_GAIN___M 0x0001F000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL__RO_DA_GAIN___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL__RO_IPA_GAIN___M 0x000007C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL__RO_IPA_GAIN___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL__RO_UPC_GAIN___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL__RO_UPC_GAIN___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL___M 0x0001F7DF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_RO_TXFE_LUT_IDX_SEL___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_0 (0x005DD030) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_0__UPC_CTUNE3FLO_0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_0__UPC_CTUNE1FLO_0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_0__UPC_CTUNE3FLO_0___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_0__UPC_CTUNE3FLO_0___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_0__UPC_CTUNE1FLO_0___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_0__UPC_CTUNE1FLO_0___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_0___M 0x00003F3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_0___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_1 (0x005DD034) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_1__UPC_CTUNE3FLO_1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_1__UPC_CTUNE1FLO_1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_1__UPC_CTUNE3FLO_1___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_1__UPC_CTUNE3FLO_1___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_1__UPC_CTUNE1FLO_1___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_1__UPC_CTUNE1FLO_1___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_1___M 0x00003F3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_1___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_2 (0x005DD038) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_2__UPC_CTUNE3FLO_2___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_2__UPC_CTUNE1FLO_2___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_2__UPC_CTUNE3FLO_2___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_2__UPC_CTUNE3FLO_2___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_2__UPC_CTUNE1FLO_2___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_2__UPC_CTUNE1FLO_2___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_2___M 0x00003F3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_2___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_3 (0x005DD03C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_3__UPC_CTUNE3FLO_3___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_3__UPC_CTUNE1FLO_3___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_3__UPC_CTUNE3FLO_3___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_3__UPC_CTUNE3FLO_3___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_3__UPC_CTUNE1FLO_3___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_3__UPC_CTUNE1FLO_3___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_3___M 0x00003F3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_3___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_4 (0x005DD040) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_4__UPC_CTUNE3FLO_4___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_4__UPC_CTUNE1FLO_4___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_4__UPC_CTUNE3FLO_4___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_4__UPC_CTUNE3FLO_4___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_4__UPC_CTUNE1FLO_4___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_4__UPC_CTUNE1FLO_4___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_4___M 0x00003F3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_4___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_5 (0x005DD044) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_5__UPC_CTUNE3FLO_5___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_5__UPC_CTUNE1FLO_5___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_5__UPC_CTUNE3FLO_5___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_5__UPC_CTUNE3FLO_5___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_5__UPC_CTUNE1FLO_5___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_5__UPC_CTUNE1FLO_5___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_5___M 0x00003F3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_5___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_6 (0x005DD048) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_6__UPC_CTUNE3FLO_6___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_6__UPC_CTUNE1FLO_6___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_6__UPC_CTUNE3FLO_6___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_6__UPC_CTUNE3FLO_6___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_6__UPC_CTUNE1FLO_6___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_6__UPC_CTUNE1FLO_6___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_6___M 0x00003F3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_6___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_7 (0x005DD04C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_7__UPC_CTUNE3FLO_7___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_7__UPC_CTUNE1FLO_7___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_7__UPC_CTUNE3FLO_7___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_7__UPC_CTUNE3FLO_7___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_7__UPC_CTUNE1FLO_7___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_7__UPC_CTUNE1FLO_7___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_7___M 0x00003F3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_7___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_8 (0x005DD050) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_8__UPC_CTUNE3FLO_8___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_8__UPC_CTUNE1FLO_8___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_8__UPC_CTUNE3FLO_8___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_8__UPC_CTUNE3FLO_8___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_8__UPC_CTUNE1FLO_8___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_8__UPC_CTUNE1FLO_8___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_8___M 0x00003F3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_8___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_9 (0x005DD054) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_9__UPC_CTUNE3FLO_9___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_9__UPC_CTUNE1FLO_9___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_9__UPC_CTUNE3FLO_9___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_9__UPC_CTUNE3FLO_9___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_9__UPC_CTUNE1FLO_9___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_9__UPC_CTUNE1FLO_9___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_9___M 0x00003F3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_9___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_10 (0x005DD058) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_10__UPC_CTUNE3FLO_10___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_10__UPC_CTUNE1FLO_10___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_10__UPC_CTUNE3FLO_10___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_10__UPC_CTUNE3FLO_10___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_10__UPC_CTUNE1FLO_10___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_10__UPC_CTUNE1FLO_10___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_10___M 0x00003F3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_10___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_11 (0x005DD05C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_11__UPC_CTUNE3FLO_11___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_11__UPC_CTUNE1FLO_11___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_11__UPC_CTUNE3FLO_11___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_11__UPC_CTUNE3FLO_11___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_11__UPC_CTUNE1FLO_11___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_11__UPC_CTUNE1FLO_11___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_11___M 0x00003F3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_11___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_12 (0x005DD060) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_12__UPC_CTUNE3FLO_12___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_12__UPC_CTUNE1FLO_12___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_12__UPC_CTUNE3FLO_12___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_12__UPC_CTUNE3FLO_12___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_12__UPC_CTUNE1FLO_12___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_12__UPC_CTUNE1FLO_12___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_12___M 0x00003F3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_12___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_13 (0x005DD064) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_13__UPC_CTUNE3FLO_13___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_13__UPC_CTUNE1FLO_13___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_13__UPC_CTUNE3FLO_13___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_13__UPC_CTUNE3FLO_13___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_13__UPC_CTUNE1FLO_13___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_13__UPC_CTUNE1FLO_13___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_13___M 0x00003F3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_13___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_14 (0x005DD068) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_14__UPC_CTUNE3FLO_14___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_14__UPC_CTUNE1FLO_14___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_14__UPC_CTUNE3FLO_14___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_14__UPC_CTUNE3FLO_14___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_14__UPC_CTUNE1FLO_14___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_14__UPC_CTUNE1FLO_14___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_14___M 0x00003F3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_14___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_15 (0x005DD06C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_15__UPC_CTUNE3FLO_15___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_15__UPC_CTUNE1FLO_15___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_15__UPC_CTUNE3FLO_15___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_15__UPC_CTUNE3FLO_15___S 8 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_15__UPC_CTUNE1FLO_15___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_15__UPC_CTUNE1FLO_15___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_15___M 0x00003F3F +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_UPC_0_15___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0 (0x005DD070) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_IBIAS_LOWER_LIM_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_ISLOPE_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_CTUNE_0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_CAS_BIAS_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_CASOFF_BIAS_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_CELL_EN_0___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_IBIAS_LOWER_LIM_0___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_IBIAS_LOWER_LIM_0___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_ISLOPE_0___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_ISLOPE_0___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_CTUNE_0___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_CTUNE_0___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_CAS_BIAS_0___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_CAS_BIAS_0___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_CASOFF_BIAS_0___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_CASOFF_BIAS_0___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_CELL_EN_0___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0__DA_CELL_EN_0___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_0___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1 (0x005DD074) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_IBIAS_LOWER_LIM_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_ISLOPE_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_CTUNE_1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_CAS_BIAS_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_CASOFF_BIAS_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_CELL_EN_1___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_IBIAS_LOWER_LIM_1___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_IBIAS_LOWER_LIM_1___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_ISLOPE_1___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_ISLOPE_1___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_CTUNE_1___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_CTUNE_1___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_CAS_BIAS_1___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_CAS_BIAS_1___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_CASOFF_BIAS_1___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_CASOFF_BIAS_1___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_CELL_EN_1___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1__DA_CELL_EN_1___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_1___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2 (0x005DD078) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_IBIAS_LOWER_LIM_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_ISLOPE_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_CTUNE_2___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_CAS_BIAS_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_CASOFF_BIAS_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_CELL_EN_2___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_IBIAS_LOWER_LIM_2___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_IBIAS_LOWER_LIM_2___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_ISLOPE_2___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_ISLOPE_2___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_CTUNE_2___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_CTUNE_2___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_CAS_BIAS_2___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_CAS_BIAS_2___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_CASOFF_BIAS_2___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_CASOFF_BIAS_2___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_CELL_EN_2___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2__DA_CELL_EN_2___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_2___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3 (0x005DD07C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_IBIAS_LOWER_LIM_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_ISLOPE_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_CTUNE_3___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_CAS_BIAS_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_CASOFF_BIAS_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_CELL_EN_3___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_IBIAS_LOWER_LIM_3___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_IBIAS_LOWER_LIM_3___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_ISLOPE_3___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_ISLOPE_3___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_CTUNE_3___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_CTUNE_3___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_CAS_BIAS_3___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_CAS_BIAS_3___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_CASOFF_BIAS_3___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_CASOFF_BIAS_3___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_CELL_EN_3___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3__DA_CELL_EN_3___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_3___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4 (0x005DD080) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_IBIAS_LOWER_LIM_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_ISLOPE_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_CTUNE_4___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_CAS_BIAS_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_CASOFF_BIAS_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_CELL_EN_4___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_IBIAS_LOWER_LIM_4___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_IBIAS_LOWER_LIM_4___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_ISLOPE_4___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_ISLOPE_4___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_CTUNE_4___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_CTUNE_4___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_CAS_BIAS_4___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_CAS_BIAS_4___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_CASOFF_BIAS_4___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_CASOFF_BIAS_4___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_CELL_EN_4___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4__DA_CELL_EN_4___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_4___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5 (0x005DD084) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_IBIAS_LOWER_LIM_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_ISLOPE_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_CTUNE_5___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_CAS_BIAS_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_CASOFF_BIAS_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_CELL_EN_5___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_IBIAS_LOWER_LIM_5___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_IBIAS_LOWER_LIM_5___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_ISLOPE_5___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_ISLOPE_5___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_CTUNE_5___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_CTUNE_5___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_CAS_BIAS_5___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_CAS_BIAS_5___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_CASOFF_BIAS_5___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_CASOFF_BIAS_5___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_CELL_EN_5___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5__DA_CELL_EN_5___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_5___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6 (0x005DD088) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_IBIAS_LOWER_LIM_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_ISLOPE_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_CTUNE_6___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_CAS_BIAS_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_CASOFF_BIAS_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_CELL_EN_6___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_IBIAS_LOWER_LIM_6___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_IBIAS_LOWER_LIM_6___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_ISLOPE_6___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_ISLOPE_6___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_CTUNE_6___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_CTUNE_6___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_CAS_BIAS_6___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_CAS_BIAS_6___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_CASOFF_BIAS_6___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_CASOFF_BIAS_6___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_CELL_EN_6___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6__DA_CELL_EN_6___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_6___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7 (0x005DD08C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_IBIAS_LOWER_LIM_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_ISLOPE_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_CTUNE_7___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_CAS_BIAS_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_CASOFF_BIAS_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_CELL_EN_7___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_IBIAS_LOWER_LIM_7___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_IBIAS_LOWER_LIM_7___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_ISLOPE_7___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_ISLOPE_7___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_CTUNE_7___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_CTUNE_7___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_CAS_BIAS_7___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_CAS_BIAS_7___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_CASOFF_BIAS_7___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_CASOFF_BIAS_7___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_CELL_EN_7___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7__DA_CELL_EN_7___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_7___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8 (0x005DD090) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_IBIAS_LOWER_LIM_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_ISLOPE_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_CTUNE_8___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_CAS_BIAS_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_CASOFF_BIAS_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_CELL_EN_8___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_IBIAS_LOWER_LIM_8___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_IBIAS_LOWER_LIM_8___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_ISLOPE_8___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_ISLOPE_8___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_CTUNE_8___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_CTUNE_8___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_CAS_BIAS_8___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_CAS_BIAS_8___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_CASOFF_BIAS_8___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_CASOFF_BIAS_8___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_CELL_EN_8___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8__DA_CELL_EN_8___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_8___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9 (0x005DD094) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_IBIAS_LOWER_LIM_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_ISLOPE_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_CTUNE_9___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_CAS_BIAS_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_CASOFF_BIAS_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_CELL_EN_9___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_IBIAS_LOWER_LIM_9___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_IBIAS_LOWER_LIM_9___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_ISLOPE_9___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_ISLOPE_9___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_CTUNE_9___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_CTUNE_9___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_CAS_BIAS_9___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_CAS_BIAS_9___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_CASOFF_BIAS_9___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_CASOFF_BIAS_9___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_CELL_EN_9___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9__DA_CELL_EN_9___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_9___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10 (0x005DD098) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_IBIAS_LOWER_LIM_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_ISLOPE_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_CTUNE_10___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_CAS_BIAS_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_CASOFF_BIAS_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_CELL_EN_10___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_IBIAS_LOWER_LIM_10___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_IBIAS_LOWER_LIM_10___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_ISLOPE_10___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_ISLOPE_10___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_CTUNE_10___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_CTUNE_10___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_CAS_BIAS_10___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_CAS_BIAS_10___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_CASOFF_BIAS_10___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_CASOFF_BIAS_10___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_CELL_EN_10___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10__DA_CELL_EN_10___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_10___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11 (0x005DD09C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_IBIAS_LOWER_LIM_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_ISLOPE_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_CTUNE_11___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_CAS_BIAS_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_CASOFF_BIAS_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_CELL_EN_11___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_IBIAS_LOWER_LIM_11___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_IBIAS_LOWER_LIM_11___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_ISLOPE_11___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_ISLOPE_11___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_CTUNE_11___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_CTUNE_11___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_CAS_BIAS_11___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_CAS_BIAS_11___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_CASOFF_BIAS_11___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_CASOFF_BIAS_11___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_CELL_EN_11___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11__DA_CELL_EN_11___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_11___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12 (0x005DD0A0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_IBIAS_LOWER_LIM_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_ISLOPE_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_CTUNE_12___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_CAS_BIAS_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_CASOFF_BIAS_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_CELL_EN_12___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_IBIAS_LOWER_LIM_12___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_IBIAS_LOWER_LIM_12___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_ISLOPE_12___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_ISLOPE_12___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_CTUNE_12___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_CTUNE_12___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_CAS_BIAS_12___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_CAS_BIAS_12___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_CASOFF_BIAS_12___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_CASOFF_BIAS_12___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_CELL_EN_12___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12__DA_CELL_EN_12___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_12___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13 (0x005DD0A4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_IBIAS_LOWER_LIM_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_ISLOPE_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_CTUNE_13___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_CAS_BIAS_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_CASOFF_BIAS_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_CELL_EN_13___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_IBIAS_LOWER_LIM_13___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_IBIAS_LOWER_LIM_13___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_ISLOPE_13___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_ISLOPE_13___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_CTUNE_13___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_CTUNE_13___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_CAS_BIAS_13___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_CAS_BIAS_13___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_CASOFF_BIAS_13___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_CASOFF_BIAS_13___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_CELL_EN_13___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13__DA_CELL_EN_13___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_13___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14 (0x005DD0A8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_IBIAS_LOWER_LIM_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_ISLOPE_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_CTUNE_14___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_CAS_BIAS_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_CASOFF_BIAS_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_CELL_EN_14___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_IBIAS_LOWER_LIM_14___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_IBIAS_LOWER_LIM_14___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_ISLOPE_14___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_ISLOPE_14___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_CTUNE_14___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_CTUNE_14___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_CAS_BIAS_14___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_CAS_BIAS_14___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_CASOFF_BIAS_14___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_CASOFF_BIAS_14___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_CELL_EN_14___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14__DA_CELL_EN_14___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_14___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15 (0x005DD0AC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_IBIAS_LOWER_LIM_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_ISLOPE_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_CTUNE_15___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_CAS_BIAS_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_CASOFF_BIAS_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_CELL_EN_15___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_IBIAS_LOWER_LIM_15___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_IBIAS_LOWER_LIM_15___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_ISLOPE_15___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_ISLOPE_15___S 20 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_CTUNE_15___M 0x000F8000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_CTUNE_15___S 15 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_CAS_BIAS_15___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_CAS_BIAS_15___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_CASOFF_BIAS_15___M 0x00000E00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_CASOFF_BIAS_15___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_CELL_EN_15___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15__DA_CELL_EN_15___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_0_15___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0 (0x005DD0B0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_CELL_AUX_EN_0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_CAS_BIAS_AUX_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_ILEVEL_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_ILEVEL_COARSE_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_HS_CTRL_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_CELL_AUX_EN_0___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_CELL_AUX_EN_0___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_CAS_BIAS_AUX_0___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_CAS_BIAS_AUX_0___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_ILEVEL_0___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_ILEVEL_0___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_ILEVEL_COARSE_0___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_ILEVEL_COARSE_0___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_HS_CTRL_0___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0__DA_HS_CTRL_0___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0___M 0x0001FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_0___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1 (0x005DD0B4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_CELL_AUX_EN_1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_CAS_BIAS_AUX_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_ILEVEL_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_ILEVEL_COARSE_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_HS_CTRL_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_CELL_AUX_EN_1___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_CELL_AUX_EN_1___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_CAS_BIAS_AUX_1___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_CAS_BIAS_AUX_1___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_ILEVEL_1___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_ILEVEL_1___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_ILEVEL_COARSE_1___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_ILEVEL_COARSE_1___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_HS_CTRL_1___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1__DA_HS_CTRL_1___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1___M 0x0001FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_1___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2 (0x005DD0B8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_CELL_AUX_EN_2___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_CAS_BIAS_AUX_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_ILEVEL_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_ILEVEL_COARSE_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_HS_CTRL_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_CELL_AUX_EN_2___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_CELL_AUX_EN_2___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_CAS_BIAS_AUX_2___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_CAS_BIAS_AUX_2___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_ILEVEL_2___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_ILEVEL_2___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_ILEVEL_COARSE_2___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_ILEVEL_COARSE_2___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_HS_CTRL_2___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2__DA_HS_CTRL_2___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2___M 0x0001FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_2___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3 (0x005DD0BC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_CELL_AUX_EN_3___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_CAS_BIAS_AUX_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_ILEVEL_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_ILEVEL_COARSE_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_HS_CTRL_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_CELL_AUX_EN_3___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_CELL_AUX_EN_3___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_CAS_BIAS_AUX_3___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_CAS_BIAS_AUX_3___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_ILEVEL_3___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_ILEVEL_3___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_ILEVEL_COARSE_3___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_ILEVEL_COARSE_3___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_HS_CTRL_3___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3__DA_HS_CTRL_3___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3___M 0x0001FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_3___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4 (0x005DD0C0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_CELL_AUX_EN_4___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_CAS_BIAS_AUX_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_ILEVEL_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_ILEVEL_COARSE_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_HS_CTRL_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_CELL_AUX_EN_4___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_CELL_AUX_EN_4___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_CAS_BIAS_AUX_4___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_CAS_BIAS_AUX_4___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_ILEVEL_4___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_ILEVEL_4___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_ILEVEL_COARSE_4___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_ILEVEL_COARSE_4___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_HS_CTRL_4___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4__DA_HS_CTRL_4___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4___M 0x0001FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_4___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5 (0x005DD0C4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_CELL_AUX_EN_5___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_CAS_BIAS_AUX_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_ILEVEL_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_ILEVEL_COARSE_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_HS_CTRL_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_CELL_AUX_EN_5___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_CELL_AUX_EN_5___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_CAS_BIAS_AUX_5___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_CAS_BIAS_AUX_5___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_ILEVEL_5___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_ILEVEL_5___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_ILEVEL_COARSE_5___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_ILEVEL_COARSE_5___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_HS_CTRL_5___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5__DA_HS_CTRL_5___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5___M 0x0001FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_5___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6 (0x005DD0C8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_CELL_AUX_EN_6___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_CAS_BIAS_AUX_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_ILEVEL_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_ILEVEL_COARSE_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_HS_CTRL_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_CELL_AUX_EN_6___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_CELL_AUX_EN_6___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_CAS_BIAS_AUX_6___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_CAS_BIAS_AUX_6___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_ILEVEL_6___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_ILEVEL_6___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_ILEVEL_COARSE_6___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_ILEVEL_COARSE_6___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_HS_CTRL_6___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6__DA_HS_CTRL_6___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6___M 0x0001FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_6___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7 (0x005DD0CC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_CELL_AUX_EN_7___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_CAS_BIAS_AUX_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_ILEVEL_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_ILEVEL_COARSE_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_HS_CTRL_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_CELL_AUX_EN_7___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_CELL_AUX_EN_7___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_CAS_BIAS_AUX_7___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_CAS_BIAS_AUX_7___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_ILEVEL_7___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_ILEVEL_7___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_ILEVEL_COARSE_7___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_ILEVEL_COARSE_7___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_HS_CTRL_7___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7__DA_HS_CTRL_7___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7___M 0x0001FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_7___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8 (0x005DD0D0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_CELL_AUX_EN_8___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_CAS_BIAS_AUX_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_ILEVEL_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_ILEVEL_COARSE_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_HS_CTRL_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_CELL_AUX_EN_8___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_CELL_AUX_EN_8___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_CAS_BIAS_AUX_8___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_CAS_BIAS_AUX_8___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_ILEVEL_8___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_ILEVEL_8___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_ILEVEL_COARSE_8___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_ILEVEL_COARSE_8___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_HS_CTRL_8___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8__DA_HS_CTRL_8___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8___M 0x0001FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_8___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9 (0x005DD0D4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_CELL_AUX_EN_9___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_CAS_BIAS_AUX_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_ILEVEL_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_ILEVEL_COARSE_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_HS_CTRL_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_CELL_AUX_EN_9___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_CELL_AUX_EN_9___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_CAS_BIAS_AUX_9___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_CAS_BIAS_AUX_9___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_ILEVEL_9___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_ILEVEL_9___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_ILEVEL_COARSE_9___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_ILEVEL_COARSE_9___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_HS_CTRL_9___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9__DA_HS_CTRL_9___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9___M 0x0001FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_9___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10 (0x005DD0D8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_CELL_AUX_EN_10___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_CAS_BIAS_AUX_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_ILEVEL_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_ILEVEL_COARSE_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_HS_CTRL_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_CELL_AUX_EN_10___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_CELL_AUX_EN_10___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_CAS_BIAS_AUX_10___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_CAS_BIAS_AUX_10___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_ILEVEL_10___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_ILEVEL_10___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_ILEVEL_COARSE_10___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_ILEVEL_COARSE_10___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_HS_CTRL_10___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10__DA_HS_CTRL_10___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10___M 0x0001FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_10___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11 (0x005DD0DC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_CELL_AUX_EN_11___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_CAS_BIAS_AUX_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_ILEVEL_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_ILEVEL_COARSE_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_HS_CTRL_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_CELL_AUX_EN_11___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_CELL_AUX_EN_11___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_CAS_BIAS_AUX_11___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_CAS_BIAS_AUX_11___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_ILEVEL_11___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_ILEVEL_11___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_ILEVEL_COARSE_11___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_ILEVEL_COARSE_11___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_HS_CTRL_11___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11__DA_HS_CTRL_11___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11___M 0x0001FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_11___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12 (0x005DD0E0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_CELL_AUX_EN_12___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_CAS_BIAS_AUX_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_ILEVEL_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_ILEVEL_COARSE_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_HS_CTRL_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_CELL_AUX_EN_12___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_CELL_AUX_EN_12___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_CAS_BIAS_AUX_12___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_CAS_BIAS_AUX_12___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_ILEVEL_12___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_ILEVEL_12___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_ILEVEL_COARSE_12___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_ILEVEL_COARSE_12___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_HS_CTRL_12___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12__DA_HS_CTRL_12___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12___M 0x0001FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_12___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13 (0x005DD0E4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_CELL_AUX_EN_13___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_CAS_BIAS_AUX_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_ILEVEL_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_ILEVEL_COARSE_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_HS_CTRL_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_CELL_AUX_EN_13___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_CELL_AUX_EN_13___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_CAS_BIAS_AUX_13___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_CAS_BIAS_AUX_13___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_ILEVEL_13___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_ILEVEL_13___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_ILEVEL_COARSE_13___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_ILEVEL_COARSE_13___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_HS_CTRL_13___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13__DA_HS_CTRL_13___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13___M 0x0001FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_13___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14 (0x005DD0E8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_CELL_AUX_EN_14___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_CAS_BIAS_AUX_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_ILEVEL_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_ILEVEL_COARSE_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_HS_CTRL_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_CELL_AUX_EN_14___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_CELL_AUX_EN_14___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_CAS_BIAS_AUX_14___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_CAS_BIAS_AUX_14___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_ILEVEL_14___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_ILEVEL_14___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_ILEVEL_COARSE_14___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_ILEVEL_COARSE_14___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_HS_CTRL_14___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14__DA_HS_CTRL_14___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14___M 0x0001FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_14___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15 (0x005DD0EC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_CELL_AUX_EN_15___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_CAS_BIAS_AUX_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_ILEVEL_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_ILEVEL_COARSE_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_HS_CTRL_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_CELL_AUX_EN_15___M 0x0001FE00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_CELL_AUX_EN_15___S 9 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_CAS_BIAS_AUX_15___M 0x000001C0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_CAS_BIAS_AUX_15___S 6 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_ILEVEL_15___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_ILEVEL_15___S 4 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_ILEVEL_COARSE_15___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_ILEVEL_COARSE_15___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_HS_CTRL_15___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15__DA_HS_CTRL_15___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15___M 0x0001FFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_DA_1_15___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0 (0x005DD0F0) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_IBIAS_LOWER_LIM_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_ISLOPE_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_ILEVEL_0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_ILEVEL_B2_0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX1_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX0_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CAS_BIAS_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CASOFF_BIAS_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_IBIAS_LOWER_LIM_0___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_IBIAS_LOWER_LIM_0___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_ISLOPE_0___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_ISLOPE_0___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_ILEVEL_0___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_ILEVEL_0___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_ILEVEL_B2_0___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_ILEVEL_B2_0___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX1_0___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX1_0___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX0_0___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CAS_BIAS_AUX0_0___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CAS_BIAS_0___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CAS_BIAS_0___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CASOFF_BIAS_0___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0__PA_CASOFF_BIAS_0___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_0___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1 (0x005DD0F4) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_IBIAS_LOWER_LIM_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_ISLOPE_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_ILEVEL_1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_ILEVEL_B2_1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX1_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX0_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CAS_BIAS_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CASOFF_BIAS_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_IBIAS_LOWER_LIM_1___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_IBIAS_LOWER_LIM_1___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_ISLOPE_1___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_ISLOPE_1___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_ILEVEL_1___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_ILEVEL_1___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_ILEVEL_B2_1___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_ILEVEL_B2_1___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX1_1___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX1_1___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX0_1___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CAS_BIAS_AUX0_1___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CAS_BIAS_1___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CAS_BIAS_1___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CASOFF_BIAS_1___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1__PA_CASOFF_BIAS_1___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_1___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2 (0x005DD0F8) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_IBIAS_LOWER_LIM_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_ISLOPE_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_ILEVEL_2___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_ILEVEL_B2_2___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX1_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX0_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CAS_BIAS_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CASOFF_BIAS_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_IBIAS_LOWER_LIM_2___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_IBIAS_LOWER_LIM_2___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_ISLOPE_2___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_ISLOPE_2___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_ILEVEL_2___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_ILEVEL_2___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_ILEVEL_B2_2___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_ILEVEL_B2_2___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX1_2___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX1_2___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX0_2___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CAS_BIAS_AUX0_2___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CAS_BIAS_2___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CAS_BIAS_2___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CASOFF_BIAS_2___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2__PA_CASOFF_BIAS_2___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_2___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3 (0x005DD0FC) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_IBIAS_LOWER_LIM_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_ISLOPE_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_ILEVEL_3___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_ILEVEL_B2_3___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX1_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX0_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CAS_BIAS_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CASOFF_BIAS_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_IBIAS_LOWER_LIM_3___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_IBIAS_LOWER_LIM_3___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_ISLOPE_3___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_ISLOPE_3___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_ILEVEL_3___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_ILEVEL_3___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_ILEVEL_B2_3___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_ILEVEL_B2_3___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX1_3___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX1_3___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX0_3___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CAS_BIAS_AUX0_3___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CAS_BIAS_3___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CAS_BIAS_3___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CASOFF_BIAS_3___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3__PA_CASOFF_BIAS_3___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_3___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4 (0x005DD100) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_IBIAS_LOWER_LIM_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_ISLOPE_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_ILEVEL_4___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_ILEVEL_B2_4___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX1_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX0_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CAS_BIAS_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CASOFF_BIAS_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_IBIAS_LOWER_LIM_4___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_IBIAS_LOWER_LIM_4___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_ISLOPE_4___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_ISLOPE_4___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_ILEVEL_4___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_ILEVEL_4___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_ILEVEL_B2_4___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_ILEVEL_B2_4___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX1_4___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX1_4___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX0_4___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CAS_BIAS_AUX0_4___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CAS_BIAS_4___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CAS_BIAS_4___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CASOFF_BIAS_4___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4__PA_CASOFF_BIAS_4___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_4___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5 (0x005DD104) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_IBIAS_LOWER_LIM_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_ISLOPE_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_ILEVEL_5___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_ILEVEL_B2_5___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX1_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX0_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CAS_BIAS_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CASOFF_BIAS_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_IBIAS_LOWER_LIM_5___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_IBIAS_LOWER_LIM_5___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_ISLOPE_5___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_ISLOPE_5___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_ILEVEL_5___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_ILEVEL_5___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_ILEVEL_B2_5___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_ILEVEL_B2_5___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX1_5___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX1_5___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX0_5___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CAS_BIAS_AUX0_5___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CAS_BIAS_5___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CAS_BIAS_5___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CASOFF_BIAS_5___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5__PA_CASOFF_BIAS_5___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_5___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6 (0x005DD108) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_IBIAS_LOWER_LIM_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_ISLOPE_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_ILEVEL_6___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_ILEVEL_B2_6___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX1_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX0_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CAS_BIAS_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CASOFF_BIAS_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_IBIAS_LOWER_LIM_6___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_IBIAS_LOWER_LIM_6___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_ISLOPE_6___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_ISLOPE_6___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_ILEVEL_6___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_ILEVEL_6___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_ILEVEL_B2_6___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_ILEVEL_B2_6___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX1_6___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX1_6___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX0_6___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CAS_BIAS_AUX0_6___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CAS_BIAS_6___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CAS_BIAS_6___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CASOFF_BIAS_6___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6__PA_CASOFF_BIAS_6___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_6___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7 (0x005DD10C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_IBIAS_LOWER_LIM_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_ISLOPE_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_ILEVEL_7___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_ILEVEL_B2_7___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX1_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX0_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CAS_BIAS_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CASOFF_BIAS_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_IBIAS_LOWER_LIM_7___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_IBIAS_LOWER_LIM_7___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_ISLOPE_7___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_ISLOPE_7___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_ILEVEL_7___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_ILEVEL_7___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_ILEVEL_B2_7___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_ILEVEL_B2_7___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX1_7___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX1_7___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX0_7___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CAS_BIAS_AUX0_7___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CAS_BIAS_7___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CAS_BIAS_7___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CASOFF_BIAS_7___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7__PA_CASOFF_BIAS_7___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_7___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8 (0x005DD110) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_IBIAS_LOWER_LIM_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_ISLOPE_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_ILEVEL_8___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_ILEVEL_B2_8___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX1_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX0_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CAS_BIAS_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CASOFF_BIAS_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_IBIAS_LOWER_LIM_8___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_IBIAS_LOWER_LIM_8___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_ISLOPE_8___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_ISLOPE_8___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_ILEVEL_8___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_ILEVEL_8___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_ILEVEL_B2_8___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_ILEVEL_B2_8___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX1_8___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX1_8___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX0_8___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CAS_BIAS_AUX0_8___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CAS_BIAS_8___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CAS_BIAS_8___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CASOFF_BIAS_8___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8__PA_CASOFF_BIAS_8___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_8___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9 (0x005DD114) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_IBIAS_LOWER_LIM_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_ISLOPE_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_ILEVEL_9___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_ILEVEL_B2_9___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX1_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX0_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CAS_BIAS_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CASOFF_BIAS_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_IBIAS_LOWER_LIM_9___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_IBIAS_LOWER_LIM_9___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_ISLOPE_9___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_ISLOPE_9___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_ILEVEL_9___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_ILEVEL_9___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_ILEVEL_B2_9___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_ILEVEL_B2_9___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX1_9___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX1_9___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX0_9___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CAS_BIAS_AUX0_9___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CAS_BIAS_9___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CAS_BIAS_9___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CASOFF_BIAS_9___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9__PA_CASOFF_BIAS_9___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_9___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10 (0x005DD118) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_IBIAS_LOWER_LIM_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_ISLOPE_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_ILEVEL_10___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_ILEVEL_B2_10___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX1_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX0_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CAS_BIAS_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CASOFF_BIAS_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_IBIAS_LOWER_LIM_10___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_IBIAS_LOWER_LIM_10___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_ISLOPE_10___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_ISLOPE_10___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_ILEVEL_10___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_ILEVEL_10___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_ILEVEL_B2_10___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_ILEVEL_B2_10___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX1_10___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX1_10___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX0_10___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CAS_BIAS_AUX0_10___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CAS_BIAS_10___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CAS_BIAS_10___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CASOFF_BIAS_10___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10__PA_CASOFF_BIAS_10___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_10___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11 (0x005DD11C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_IBIAS_LOWER_LIM_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_ISLOPE_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_ILEVEL_11___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_ILEVEL_B2_11___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX1_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX0_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CAS_BIAS_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CASOFF_BIAS_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_IBIAS_LOWER_LIM_11___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_IBIAS_LOWER_LIM_11___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_ISLOPE_11___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_ISLOPE_11___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_ILEVEL_11___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_ILEVEL_11___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_ILEVEL_B2_11___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_ILEVEL_B2_11___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX1_11___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX1_11___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX0_11___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CAS_BIAS_AUX0_11___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CAS_BIAS_11___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CAS_BIAS_11___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CASOFF_BIAS_11___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11__PA_CASOFF_BIAS_11___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_11___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12 (0x005DD120) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_IBIAS_LOWER_LIM_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_ISLOPE_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_ILEVEL_12___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_ILEVEL_B2_12___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX1_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX0_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CAS_BIAS_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CASOFF_BIAS_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_IBIAS_LOWER_LIM_12___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_IBIAS_LOWER_LIM_12___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_ISLOPE_12___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_ISLOPE_12___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_ILEVEL_12___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_ILEVEL_12___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_ILEVEL_B2_12___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_ILEVEL_B2_12___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX1_12___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX1_12___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX0_12___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CAS_BIAS_AUX0_12___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CAS_BIAS_12___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CAS_BIAS_12___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CASOFF_BIAS_12___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12__PA_CASOFF_BIAS_12___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_12___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13 (0x005DD124) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_IBIAS_LOWER_LIM_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_ISLOPE_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_ILEVEL_13___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_ILEVEL_B2_13___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX1_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX0_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CAS_BIAS_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CASOFF_BIAS_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_IBIAS_LOWER_LIM_13___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_IBIAS_LOWER_LIM_13___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_ISLOPE_13___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_ISLOPE_13___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_ILEVEL_13___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_ILEVEL_13___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_ILEVEL_B2_13___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_ILEVEL_B2_13___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX1_13___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX1_13___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX0_13___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CAS_BIAS_AUX0_13___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CAS_BIAS_13___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CAS_BIAS_13___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CASOFF_BIAS_13___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13__PA_CASOFF_BIAS_13___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_13___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14 (0x005DD128) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_IBIAS_LOWER_LIM_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_ISLOPE_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_ILEVEL_14___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_ILEVEL_B2_14___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX1_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX0_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CAS_BIAS_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CASOFF_BIAS_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_IBIAS_LOWER_LIM_14___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_IBIAS_LOWER_LIM_14___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_ISLOPE_14___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_ISLOPE_14___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_ILEVEL_14___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_ILEVEL_14___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_ILEVEL_B2_14___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_ILEVEL_B2_14___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX1_14___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX1_14___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX0_14___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CAS_BIAS_AUX0_14___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CAS_BIAS_14___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CAS_BIAS_14___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CASOFF_BIAS_14___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14__PA_CASOFF_BIAS_14___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_14___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15 (0x005DD12C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_IBIAS_LOWER_LIM_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_ISLOPE_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_ILEVEL_15___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_ILEVEL_B2_15___POR 0x00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX1_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX0_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CAS_BIAS_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CASOFF_BIAS_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_IBIAS_LOWER_LIM_15___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_IBIAS_LOWER_LIM_15___S 26 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_ISLOPE_15___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_ISLOPE_15___S 23 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_ILEVEL_15___M 0x007C0000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_ILEVEL_15___S 18 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_ILEVEL_B2_15___M 0x0003E000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_ILEVEL_B2_15___S 13 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX1_15___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX1_15___S 10 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX0_15___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CAS_BIAS_AUX0_15___S 7 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CAS_BIAS_15___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CAS_BIAS_15___S 3 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CASOFF_BIAS_15___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15__PA_CASOFF_BIAS_15___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_0_15___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0 (0x005DD130) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_CELL_EN1_0___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_CELL_EN0_0___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_CELL_FB_0___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_IBIAS_MODE_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_CELL_EN1_0___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_CELL_EN1_0___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_CELL_EN0_0___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_CELL_EN0_0___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_CELL_FB_0___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_CELL_FB_0___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_IBIAS_MODE_0___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0__PA_IBIAS_MODE_0___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_0___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1 (0x005DD134) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_CELL_EN1_1___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_CELL_EN0_1___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_CELL_FB_1___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_IBIAS_MODE_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_CELL_EN1_1___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_CELL_EN1_1___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_CELL_EN0_1___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_CELL_EN0_1___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_CELL_FB_1___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_CELL_FB_1___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_IBIAS_MODE_1___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1__PA_IBIAS_MODE_1___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_1___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2 (0x005DD138) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_CELL_EN1_2___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_CELL_EN0_2___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_CELL_FB_2___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_IBIAS_MODE_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_CELL_EN1_2___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_CELL_EN1_2___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_CELL_EN0_2___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_CELL_EN0_2___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_CELL_FB_2___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_CELL_FB_2___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_IBIAS_MODE_2___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2__PA_IBIAS_MODE_2___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_2___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3 (0x005DD13C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_CELL_EN1_3___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_CELL_EN0_3___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_CELL_FB_3___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_IBIAS_MODE_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_CELL_EN1_3___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_CELL_EN1_3___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_CELL_EN0_3___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_CELL_EN0_3___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_CELL_FB_3___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_CELL_FB_3___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_IBIAS_MODE_3___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3__PA_IBIAS_MODE_3___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_3___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4 (0x005DD140) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_CELL_EN1_4___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_CELL_EN0_4___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_CELL_FB_4___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_IBIAS_MODE_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_CELL_EN1_4___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_CELL_EN1_4___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_CELL_EN0_4___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_CELL_EN0_4___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_CELL_FB_4___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_CELL_FB_4___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_IBIAS_MODE_4___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4__PA_IBIAS_MODE_4___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_4___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5 (0x005DD144) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_CELL_EN1_5___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_CELL_EN0_5___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_CELL_FB_5___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_IBIAS_MODE_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_CELL_EN1_5___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_CELL_EN1_5___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_CELL_EN0_5___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_CELL_EN0_5___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_CELL_FB_5___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_CELL_FB_5___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_IBIAS_MODE_5___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5__PA_IBIAS_MODE_5___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_5___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6 (0x005DD148) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_CELL_EN1_6___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_CELL_EN0_6___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_CELL_FB_6___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_IBIAS_MODE_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_CELL_EN1_6___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_CELL_EN1_6___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_CELL_EN0_6___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_CELL_EN0_6___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_CELL_FB_6___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_CELL_FB_6___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_IBIAS_MODE_6___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6__PA_IBIAS_MODE_6___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_6___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7 (0x005DD14C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_CELL_EN1_7___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_CELL_EN0_7___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_CELL_FB_7___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_IBIAS_MODE_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_CELL_EN1_7___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_CELL_EN1_7___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_CELL_EN0_7___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_CELL_EN0_7___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_CELL_FB_7___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_CELL_FB_7___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_IBIAS_MODE_7___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7__PA_IBIAS_MODE_7___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_7___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8 (0x005DD150) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_CELL_EN1_8___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_CELL_EN0_8___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_CELL_FB_8___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_IBIAS_MODE_8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_CELL_EN1_8___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_CELL_EN1_8___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_CELL_EN0_8___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_CELL_EN0_8___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_CELL_FB_8___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_CELL_FB_8___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_IBIAS_MODE_8___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8__PA_IBIAS_MODE_8___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_8___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9 (0x005DD154) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_CELL_EN1_9___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_CELL_EN0_9___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_CELL_FB_9___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_IBIAS_MODE_9___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_CELL_EN1_9___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_CELL_EN1_9___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_CELL_EN0_9___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_CELL_EN0_9___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_CELL_FB_9___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_CELL_FB_9___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_IBIAS_MODE_9___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9__PA_IBIAS_MODE_9___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_9___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10 (0x005DD158) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_CELL_EN1_10___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_CELL_EN0_10___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_CELL_FB_10___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_IBIAS_MODE_10___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_CELL_EN1_10___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_CELL_EN1_10___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_CELL_EN0_10___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_CELL_EN0_10___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_CELL_FB_10___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_CELL_FB_10___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_IBIAS_MODE_10___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10__PA_IBIAS_MODE_10___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_10___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11 (0x005DD15C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_CELL_EN1_11___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_CELL_EN0_11___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_CELL_FB_11___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_IBIAS_MODE_11___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_CELL_EN1_11___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_CELL_EN1_11___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_CELL_EN0_11___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_CELL_EN0_11___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_CELL_FB_11___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_CELL_FB_11___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_IBIAS_MODE_11___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11__PA_IBIAS_MODE_11___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_11___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12 (0x005DD160) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12__PA_CELL_EN1_12___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12__PA_CELL_EN0_12___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12__PA_CELL_FB_12___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12__PA_IBIAS_MODE_12___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12__PA_CELL_EN1_12___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12__PA_CELL_EN1_12___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12__PA_CELL_EN0_12___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12__PA_CELL_EN0_12___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12__PA_CELL_FB_12___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12__PA_CELL_FB_12___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12__PA_IBIAS_MODE_12___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12__PA_IBIAS_MODE_12___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_12___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13 (0x005DD164) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_CELL_EN1_13___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_CELL_EN0_13___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_CELL_FB_13___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_IBIAS_MODE_13___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_CELL_EN1_13___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_CELL_EN1_13___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_CELL_EN0_13___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_CELL_EN0_13___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_CELL_FB_13___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_CELL_FB_13___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_IBIAS_MODE_13___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13__PA_IBIAS_MODE_13___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_13___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14 (0x005DD168) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_CELL_EN1_14___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_CELL_EN0_14___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_CELL_FB_14___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_IBIAS_MODE_14___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_CELL_EN1_14___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_CELL_EN1_14___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_CELL_EN0_14___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_CELL_EN0_14___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_CELL_FB_14___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_CELL_FB_14___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_IBIAS_MODE_14___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14__PA_IBIAS_MODE_14___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_14___S 0 + +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15 (0x005DD16C) +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_CELL_EN1_15___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_CELL_EN0_15___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_CELL_FB_15___POR 0x000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_IBIAS_MODE_15___POR 0x0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_CELL_EN1_15___M 0xFFC00000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_CELL_EN1_15___S 22 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_CELL_EN0_15___M 0x003FF000 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_CELL_EN0_15___S 12 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_CELL_FB_15___M 0x00000FFC +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_CELL_FB_15___S 2 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_IBIAS_MODE_15___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15__PA_IBIAS_MODE_15___S 0 +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_TXFE_CH1_BT_TXFE_PA_1_15___S 0 + +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_MSIP_ID_REG (0x005DE800) +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_MSIP_ID_REG___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_MSIP_ID_REG___POR 0x10000000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_MSIP_ID_REG__MSIP_ID_MAJOR___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_MSIP_ID_REG__MSIP_ID_MINOR___POR 0x000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_MSIP_ID_REG__MSIP_ID_STEP___POR 0x0000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_MSIP_ID_REG__MSIP_ID_MAJOR___M 0xF0000000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_MSIP_ID_REG__MSIP_ID_MAJOR___S 28 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_MSIP_ID_REG__MSIP_ID_MINOR___M 0x0FFF0000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_MSIP_ID_REG__MSIP_ID_MINOR___S 16 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_MSIP_ID_REG__MSIP_ID_STEP___M 0x0000FFFF +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_MSIP_ID_REG__MSIP_ID_STEP___S 0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_MSIP_ID_REG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_MSIP_ID_REG___S 0 + +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TEST_REG_0 (0x005DE804) +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TEST_REG_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TEST_REG_0___POR 0xDAC1DAC0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TEST_REG_0__TEST_RO___POR 0xDAC1DAC0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TEST_REG_0__TEST_RO___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TEST_REG_0__TEST_RO___S 0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TEST_REG_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TEST_REG_0___S 0 + +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TEST_REG_1 (0x005DE808) +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TEST_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TEST_REG_1___POR 0x1234ABCD +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TEST_REG_1__TEST_RW___POR 0x1234ABCD +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TEST_REG_1__TEST_RW___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TEST_REG_1__TEST_RW___S 0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TEST_REG_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TEST_REG_1___S 0 + +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_GLOBAL (0x005DE80C) +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_GLOBAL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_GLOBAL___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_GLOBAL__RBIST_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_GLOBAL__ATE_WFM_START___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_GLOBAL__RBIST_TX_SW_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_GLOBAL__RBIST_SEL___M 0x00000004 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_GLOBAL__RBIST_SEL___S 2 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_GLOBAL__ATE_WFM_START___M 0x00000002 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_GLOBAL__ATE_WFM_START___S 1 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_GLOBAL__RBIST_TX_SW_RESET___M 0x00000001 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_GLOBAL__RBIST_TX_SW_RESET___S 0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_GLOBAL___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_GLOBAL___S 0 + +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_OUT_SCALING (0x005DE810) +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_OUT_SCALING___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_OUT_SCALING___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_OUT_SCALING__ATE_TONEGEN_SCALING_ENABLE___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_OUT_SCALING__ATE_TONEGEN_SCALING_I___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_OUT_SCALING__ATE_TONEGEN_SCALING_Q___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_OUT_SCALING__ATE_TONEGEN_SCALING_ENABLE___M 0x00000100 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_OUT_SCALING__ATE_TONEGEN_SCALING_ENABLE___S 8 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_OUT_SCALING__ATE_TONEGEN_SCALING_I___M 0x000000F0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_OUT_SCALING__ATE_TONEGEN_SCALING_I___S 4 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_OUT_SCALING__ATE_TONEGEN_SCALING_Q___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_OUT_SCALING__ATE_TONEGEN_SCALING_Q___S 0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_OUT_SCALING___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_OUT_SCALING___S 0 + +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_DC_OFFSET (0x005DE814) +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_DC_OFFSET___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_DC_OFFSET___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_DC_OFFSET__ATE_TONEGEN_DC_ENABLE___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_DC_OFFSET__ATE_TONEGEN_DC_I___POR 0x000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_DC_OFFSET__ATE_TONEGEN_DC_Q___POR 0x000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_DC_OFFSET__ATE_TONEGEN_DC_ENABLE___M 0x01000000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_DC_OFFSET__ATE_TONEGEN_DC_ENABLE___S 24 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_DC_OFFSET__ATE_TONEGEN_DC_I___M 0x00FFF000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_DC_OFFSET__ATE_TONEGEN_DC_I___S 12 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_DC_OFFSET__ATE_TONEGEN_DC_Q___M 0x00000FFF +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_DC_OFFSET__ATE_TONEGEN_DC_Q___S 0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_DC_OFFSET___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_DC_OFFSET___S 0 + +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0 (0x005DE818) +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0__ATE_TONEGEN_TONE0_ENABLE___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0__ATE_TONEGEN_TONE0_FREQ___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_6DB___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_1DB___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0__ATE_TONEGEN_TONE0_DELAY___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0__ATE_TONEGEN_TONE0_ENABLE___M 0x01000000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0__ATE_TONEGEN_TONE0_ENABLE___S 24 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0__ATE_TONEGEN_TONE0_FREQ___M 0x00FF0000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0__ATE_TONEGEN_TONE0_FREQ___S 16 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_6DB___M 0x0000F000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_6DB___S 12 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_1DB___M 0x00000700 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_1DB___S 8 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0__ATE_TONEGEN_TONE0_DELAY___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0__ATE_TONEGEN_TONE0_DELAY___S 0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0___M 0x01FFF7FF +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN0___S 0 + +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1 (0x005DE81C) +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1__ATE_TONEGEN_TONE1_ENABLE___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1__ATE_TONEGEN_TONE1_FREQ___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_6DB___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_1DB___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1__ATE_TONEGEN_TONE1_DELAY___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1__ATE_TONEGEN_TONE1_ENABLE___M 0x01000000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1__ATE_TONEGEN_TONE1_ENABLE___S 24 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1__ATE_TONEGEN_TONE1_FREQ___M 0x00FF0000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1__ATE_TONEGEN_TONE1_FREQ___S 16 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_6DB___M 0x0000F000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_6DB___S 12 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_1DB___M 0x00000700 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_1DB___S 8 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1__ATE_TONEGEN_TONE1_DELAY___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1__ATE_TONEGEN_TONE1_DELAY___S 0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1___M 0x01FFF7FF +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_TONEGEN1___S 0 + +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0 (0x005DE820) +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_ENABLE___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_FREQ___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_6DB___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_1DB___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_DELAY___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_ENABLE___M 0x01000000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_ENABLE___S 24 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_FREQ___M 0x00FF0000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_FREQ___S 16 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_6DB___M 0x0000F000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_6DB___S 12 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_1DB___M 0x00000700 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_1DB___S 8 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_DELAY___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_DELAY___S 0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0___M 0x01FFF7FF +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LFTONEGEN0___S 0 + +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_I (0x005DE824) +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_I___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_I___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_ENABLE_I___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_DWELL_I___POR 0x000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_STEP_I___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_INIT_I___POR 0x000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_ENABLE_I___M 0x10000000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_ENABLE_I___S 28 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_DWELL_I___M 0x0FFC0000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_DWELL_I___S 18 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_STEP_I___M 0x0003F000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_STEP_I___S 12 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_INIT_I___M 0x00000FFF +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_INIT_I___S 0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_I___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_I___S 0 + +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_Q (0x005DE828) +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_Q___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_Q___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_ENABLE_Q___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_DWELL_Q___POR 0x000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_STEP_Q___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_INIT_Q___POR 0x000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_ENABLE_Q___M 0x10000000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_ENABLE_Q___S 28 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_DWELL_Q___M 0x0FFC0000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_DWELL_Q___S 18 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_STEP_Q___M 0x0003F000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_STEP_Q___S 12 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_INIT_Q___M 0x00000FFF +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_INIT_Q___S 0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_Q___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_LINEAR_RAMP_Q___S 0 + +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_MAG (0x005DE82C) +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_MAG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_MAG___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_I___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_Q___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_I___POR 0x000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_Q___POR 0x000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_I___M 0x00800000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_I___S 23 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_Q___M 0x00400000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_Q___S 22 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_I___M 0x003FF800 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_I___S 11 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_Q___M 0x000007FF +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_Q___S 0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_MAG___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_MAG___S 0 + +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_SEED_I (0x005DE830) +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_SEED_I___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_SEED_I___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_SEED_I__ATE_TONEGEN_PRBS_SEED_I___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_SEED_I__ATE_TONEGEN_PRBS_SEED_I___M 0x7FFFFFFF +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_SEED_I__ATE_TONEGEN_PRBS_SEED_I___S 0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_SEED_I___M 0x7FFFFFFF +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_SEED_I___S 0 + +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_SEED_Q (0x005DE834) +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_SEED_Q___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_SEED_Q___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_SEED_Q__ATE_TONEGEN_PRBS_SEED_Q___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_SEED_Q__ATE_TONEGEN_PRBS_SEED_Q___M 0x7FFFFFFF +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_SEED_Q__ATE_TONEGEN_PRBS_SEED_Q___S 0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_SEED_Q___M 0x7FFFFFFF +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PRBS_SEED_Q___S 0 + +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM (0x005DE838) +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM___POR 0x000003FF +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_ENABLE___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_SCALING_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_MAGNITUDE___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_START___POR 0x000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_STOP___POR 0x3FF +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_ENABLE___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_ENABLE___S 29 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_SCALING_EN___M 0x10000000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_SCALING_EN___S 28 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_MAGNITUDE___M 0x0F000000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_MAGNITUDE___S 24 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_START___M 0x000FFC00 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_START___S 10 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_STOP___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_STOP___S 0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM___M 0x3F0FFFFF +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_TX_PREAMBLE_ROM___S 0 + +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_DIG_TEST_OUT_SEL (0x005DE83C) +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_DIG_TEST_OUT_SEL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_DIG_TEST_OUT_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_DIG_TEST_OUT_SEL__DIG_TEST_OUT_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_DIG_TEST_OUT_SEL__DIG_TEST_OUT_SEL___M 0x07800000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_DIG_TEST_OUT_SEL__DIG_TEST_OUT_SEL___S 23 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_DIG_TEST_OUT_SEL___M 0x07800000 +#define PHYA_IRON2G_RFA_BT_RBIST_TX_BAREBONE_DIG_TEST_OUT_SEL___S 23 + +#define PHYA_IRON2G_RFA_BT_DAC_MSIP_ID_REG (0x005DE980) +#define PHYA_IRON2G_RFA_BT_DAC_MSIP_ID_REG___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BT_DAC_MSIP_ID_REG___POR 0x10000000 +#define PHYA_IRON2G_RFA_BT_DAC_MSIP_ID_REG__MSIP_ID_MAJOR___POR 0x1 +#define PHYA_IRON2G_RFA_BT_DAC_MSIP_ID_REG__MSIP_ID_MINOR___POR 0x000 +#define PHYA_IRON2G_RFA_BT_DAC_MSIP_ID_REG__MSIP_ID_STEP___POR 0x0000 +#define PHYA_IRON2G_RFA_BT_DAC_MSIP_ID_REG__MSIP_ID_MAJOR___M 0xF0000000 +#define PHYA_IRON2G_RFA_BT_DAC_MSIP_ID_REG__MSIP_ID_MAJOR___S 28 +#define PHYA_IRON2G_RFA_BT_DAC_MSIP_ID_REG__MSIP_ID_MINOR___M 0x0FFF0000 +#define PHYA_IRON2G_RFA_BT_DAC_MSIP_ID_REG__MSIP_ID_MINOR___S 16 +#define PHYA_IRON2G_RFA_BT_DAC_MSIP_ID_REG__MSIP_ID_STEP___M 0x0000FFFF +#define PHYA_IRON2G_RFA_BT_DAC_MSIP_ID_REG__MSIP_ID_STEP___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_MSIP_ID_REG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_DAC_MSIP_ID_REG___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_CHIP_ID_REG (0x005DE984) +#define PHYA_IRON2G_RFA_BT_DAC_CHIP_ID_REG___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BT_DAC_CHIP_ID_REG___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_CHIP_ID_REG__CHIP_ID___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_CHIP_ID_REG__CHIP_ID___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_CHIP_ID_REG__CHIP_ID___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_CHIP_ID_REG___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_CHIP_ID_REG___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_TEST_REG_0 (0x005DE988) +#define PHYA_IRON2G_RFA_BT_DAC_TEST_REG_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BT_DAC_TEST_REG_0___POR 0xDAC1DAC0 +#define PHYA_IRON2G_RFA_BT_DAC_TEST_REG_0__TEST_RO___POR 0xDAC1DAC0 +#define PHYA_IRON2G_RFA_BT_DAC_TEST_REG_0__TEST_RO___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_DAC_TEST_REG_0__TEST_RO___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_TEST_REG_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_DAC_TEST_REG_0___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_TEST_REG_1 (0x005DE98C) +#define PHYA_IRON2G_RFA_BT_DAC_TEST_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_TEST_REG_1___POR 0x1234ABCD +#define PHYA_IRON2G_RFA_BT_DAC_TEST_REG_1__TEST_RW___POR 0x1234ABCD +#define PHYA_IRON2G_RFA_BT_DAC_TEST_REG_1__TEST_RW___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_DAC_TEST_REG_1__TEST_RW___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_TEST_REG_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_DAC_TEST_REG_1___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0 (0x005DE990) +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0___POR 0x00007000 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0__D_DAC_AMPLITUDE___POR 0x7 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0__CAL_WR_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0__DAC_SW_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0__DAC_SIGPATH_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0__DAC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0__D_DAC_AMPLITUDE___M 0x0000F000 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0__D_DAC_AMPLITUDE___S 12 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0__CAL_WR_EN___M 0x00000180 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0__CAL_WR_EN___S 7 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0__DAC_SW_RESET___M 0x00000040 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0__DAC_SW_RESET___S 6 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0__DAC_SIGPATH_EN_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0__DAC_SIGPATH_EN_OVS___S 4 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0__DAC_EN_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0__DAC_EN_OVS___S 2 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0___M 0x0000F1FC +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_0___S 2 + +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1 (0x005DE994) +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1___POR 0x00000010 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_Q_FORCEFULLSCALE___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_I_FORCEFULLSCALE___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_DISABLE_R2RBUFFER___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_CAL_DISABLE_OFFSETDAC___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_ATEST_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_Q_FORCEMIDSCALE___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_I_FORCEMIDSCALE___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_PWRDN_N___POR 0x1 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_Q_FORCEFULLSCALE___M 0x00080000 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_Q_FORCEFULLSCALE___S 19 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_I_FORCEFULLSCALE___M 0x00040000 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_I_FORCEFULLSCALE___S 18 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_DISABLE_R2RBUFFER___M 0x00020000 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_DISABLE_R2RBUFFER___S 17 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_CAL_DISABLE_OFFSETDAC___M 0x00010000 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_CAL_DISABLE_OFFSETDAC___S 16 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_ATEST_SEL___M 0x0000FF00 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_ATEST_SEL___S 8 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_Q_FORCEMIDSCALE___M 0x00000040 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_Q_FORCEMIDSCALE___S 6 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_I_FORCEMIDSCALE___M 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_I_FORCEMIDSCALE___S 5 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_PWRDN_N___M 0x00000010 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1__D_DAC_PWRDN_N___S 4 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1___M 0x000FFF70 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_CTRL_1___S 4 + +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG1 (0x005DE998) +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG1__DAC_REG1_SPARE___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG1__DAC_VLDO_SHORT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG1__DAC_VLDO_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG1__D_DAC_SINKDC_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG1__DAC_REG1_SPARE___M 0x00000060 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG1__DAC_REG1_SPARE___S 5 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG1__DAC_VLDO_SHORT___M 0x00000010 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG1__DAC_VLDO_SHORT___S 4 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG1__DAC_VLDO_SEL___M 0x0000000E +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG1__DAC_VLDO_SEL___S 1 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG1__D_DAC_SINKDC_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG1__D_DAC_SINKDC_EN___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG1___M 0x0000007F +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG1___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG2 (0x005DE99C) +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG2__DAC_REG2_SPARE___POR 0x00 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG2__DAC_REG2_SPARE___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG2__DAC_REG2_SPARE___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG2___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG2___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG3 (0x005DE9A0) +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG3___POR 0x00000070 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG3__DAC_CFG_1_SPARE2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG3__D_DAC_VREF___POR 0x7 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG3__DAC_CFG_1_SPARE1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG3__DISABLE_FIR___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG3__DAC_CFG_1_SPARE0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG3__DAC_CFG_1_SPARE2___M 0x00000100 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG3__DAC_CFG_1_SPARE2___S 8 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG3__D_DAC_VREF___M 0x000000F0 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG3__D_DAC_VREF___S 4 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG3__DAC_CFG_1_SPARE1___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG3__DAC_CFG_1_SPARE1___S 2 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG3__DISABLE_FIR___M 0x00000002 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG3__DISABLE_FIR___S 1 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG3__DAC_CFG_1_SPARE0___M 0x00000001 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG3__DAC_CFG_1_SPARE0___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG3___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG3___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG4 (0x005DE9A4) +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG4___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG4___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG4__DAC_REG3_SPARE___POR 0x00 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG4__DAC_REG3_SPARE___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG4__DAC_REG3_SPARE___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG4___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG4___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG5 (0x005DE9A8) +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG5___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG5__DAC_REG4_SPARE___POR 0x00 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG5__DAC_REG4_SPARE___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG5__DAC_REG4_SPARE___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG5___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG5___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG6 (0x005DE9AC) +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG6___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG6__DAC_REG5_SPARE___POR 0x00 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG6__DAC_REG5_SPARE___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG6__DAC_REG5_SPARE___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG6___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG6___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG7 (0x005DE9B0) +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG7___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG7__DAC_REG6_SPARE___POR 0x00 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG7__DAC_REG6_SPARE___M 0x0000007F +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG7__DAC_REG6_SPARE___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG7___M 0x0000007F +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG7___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG8 (0x005DE9B4) +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG8___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG8__DAC_REG7_SPARE___POR 0x00 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG8__DAC_REG7_SPARE___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG8__DAC_REG7_SPARE___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG8___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG8___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG9 (0x005DE9B8) +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG9___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG9__CAL_SM_WR___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG9__CAL_SM_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG9__CAL_SM_WR___M 0x00000002 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG9__CAL_SM_WR___S 1 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG9__CAL_SM_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG9__CAL_SM_EN___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG9___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG9___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG10 (0x005DE9BC) +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG10___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG10___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG10__CAL_SAT_ERR___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG10__CAL_BUSY___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG10__CAL_SAT_ERR___M 0x00000002 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG10__CAL_SAT_ERR___S 1 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG10__CAL_BUSY___M 0x00000001 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG10__CAL_BUSY___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG10___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_DAC_DAC_REG10___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I00 (0x005DE9C0) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I00___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I00___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I00__DAC_CAL_S_I00___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I00__DAC_CAL_S_I00___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I00__DAC_CAL_S_I00___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I00___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I00___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I01 (0x005DE9C4) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I01___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I01___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I01__DAC_CAL_S_I01___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I01__DAC_CAL_S_I01___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I01__DAC_CAL_S_I01___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I01___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I01___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I02 (0x005DE9C8) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I02___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I02___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I02__DAC_CAL_S_I02___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I02__DAC_CAL_S_I02___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I02__DAC_CAL_S_I02___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I02___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I02___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I03 (0x005DE9CC) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I03___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I03___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I03__DAC_CAL_S_I03___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I03__DAC_CAL_S_I03___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I03__DAC_CAL_S_I03___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I03___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I03___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I04 (0x005DE9D0) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I04___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I04___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I04__DAC_CAL_S_I04___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I04__DAC_CAL_S_I04___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I04__DAC_CAL_S_I04___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I04___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I04___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I05 (0x005DE9D4) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I05___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I05___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I05__DAC_CAL_S_I05___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I05__DAC_CAL_S_I05___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I05__DAC_CAL_S_I05___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I05___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I05___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I06 (0x005DE9D8) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I06___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I06___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I06__DAC_CAL_S_I06___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I06__DAC_CAL_S_I06___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I06__DAC_CAL_S_I06___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I06___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I06___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I07 (0x005DE9DC) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I07___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I07___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I07__DAC_CAL_S_I07___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I07__DAC_CAL_S_I07___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I07__DAC_CAL_S_I07___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I07___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I07___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I08 (0x005DE9E0) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I08___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I08___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I08__DAC_CAL_S_I08___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I08__DAC_CAL_S_I08___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I08__DAC_CAL_S_I08___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I08___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I08___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I09 (0x005DE9E4) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I09___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I09___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I09__DAC_CAL_S_I09___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I09__DAC_CAL_S_I09___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I09__DAC_CAL_S_I09___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I09___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I09___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I10 (0x005DE9E8) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I10___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I10__DAC_CAL_S_I10___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I10__DAC_CAL_S_I10___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I10__DAC_CAL_S_I10___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I10___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I10___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I11 (0x005DE9EC) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I11___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I11__DAC_CAL_S_I11___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I11__DAC_CAL_S_I11___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I11__DAC_CAL_S_I11___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I11___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I11___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I12 (0x005DE9F0) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I12___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I12__DAC_CAL_S_I12___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I12__DAC_CAL_S_I12___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I12__DAC_CAL_S_I12___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I12___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I12___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I13 (0x005DE9F4) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I13___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I13__DAC_CAL_S_I13___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I13__DAC_CAL_S_I13___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I13__DAC_CAL_S_I13___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I13___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I13___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I14 (0x005DE9F8) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I14___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I14__DAC_CAL_S_I14___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I14__DAC_CAL_S_I14___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I14__DAC_CAL_S_I14___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I14___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I14___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I15 (0x005DE9FC) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I15___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I15__DAC_CAL_S_I15___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I15__DAC_CAL_S_I15___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I15__DAC_CAL_S_I15___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I15___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I15___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I16 (0x005DEA00) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I16___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I16__DAC_CAL_S_I16___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I16__DAC_CAL_S_I16___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I16__DAC_CAL_S_I16___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I16___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I16___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I17 (0x005DEA04) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I17___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I17__DAC_CAL_S_I17___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I17__DAC_CAL_S_I17___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I17__DAC_CAL_S_I17___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I17___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I17___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I18 (0x005DEA08) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I18___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I18__DAC_CAL_S_I18___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I18__DAC_CAL_S_I18___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I18__DAC_CAL_S_I18___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I18___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I18___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I19 (0x005DEA0C) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I19___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I19__DAC_CAL_S_I19___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I19__DAC_CAL_S_I19___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I19__DAC_CAL_S_I19___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I19___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I19___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I20 (0x005DEA10) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I20___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I20__DAC_CAL_S_I20___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I20__DAC_CAL_S_I20___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I20__DAC_CAL_S_I20___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I20___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I20___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I21 (0x005DEA14) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I21___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I21__DAC_CAL_S_I21___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I21__DAC_CAL_S_I21___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I21__DAC_CAL_S_I21___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I21___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I21___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I22 (0x005DEA18) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I22___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I22__DAC_CAL_S_I22___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I22__DAC_CAL_S_I22___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I22__DAC_CAL_S_I22___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I22___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I22___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I23 (0x005DEA1C) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I23___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I23__DAC_CAL_S_I23___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I23__DAC_CAL_S_I23___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I23__DAC_CAL_S_I23___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I23___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I23___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I24 (0x005DEA20) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I24___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I24__DAC_CAL_S_I24___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I24__DAC_CAL_S_I24___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I24__DAC_CAL_S_I24___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I24___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I24___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I25 (0x005DEA24) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I25___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I25__DAC_CAL_S_I25___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I25__DAC_CAL_S_I25___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I25__DAC_CAL_S_I25___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I25___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I25___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I26 (0x005DEA28) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I26___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I26__DAC_CAL_S_I26___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I26__DAC_CAL_S_I26___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I26__DAC_CAL_S_I26___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I26___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I26___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I27 (0x005DEA2C) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I27___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I27__DAC_CAL_S_I27___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I27__DAC_CAL_S_I27___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I27__DAC_CAL_S_I27___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I27___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I27___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I28 (0x005DEA30) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I28___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I28__DAC_CAL_S_I28___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I28__DAC_CAL_S_I28___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I28__DAC_CAL_S_I28___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I28___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I28___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I29 (0x005DEA34) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I29___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I29__DAC_CAL_S_I29___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I29__DAC_CAL_S_I29___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I29__DAC_CAL_S_I29___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I29___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I29___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I30 (0x005DEA38) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I30___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I30__DAC_CAL_S_I30___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I30__DAC_CAL_S_I30___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I30__DAC_CAL_S_I30___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I30___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I30___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I31 (0x005DEA3C) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I31___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I31__DAC_CAL_S_I31___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I31__DAC_CAL_S_I31___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I31__DAC_CAL_S_I31___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I31___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_I31___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q00 (0x005DEA40) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q00___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q00___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q00__DAC_CAL_S_Q00___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q00__DAC_CAL_S_Q00___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q00__DAC_CAL_S_Q00___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q00___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q00___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q01 (0x005DEA44) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q01___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q01___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q01__DAC_CAL_S_Q01___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q01__DAC_CAL_S_Q01___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q01__DAC_CAL_S_Q01___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q01___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q01___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q02 (0x005DEA48) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q02___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q02___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q02__DAC_CAL_S_Q02___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q02__DAC_CAL_S_Q02___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q02__DAC_CAL_S_Q02___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q02___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q02___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q03 (0x005DEA4C) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q03___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q03___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q03__DAC_CAL_S_Q03___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q03__DAC_CAL_S_Q03___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q03__DAC_CAL_S_Q03___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q03___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q03___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q04 (0x005DEA50) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q04___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q04___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q04__DAC_CAL_S_Q04___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q04__DAC_CAL_S_Q04___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q04__DAC_CAL_S_Q04___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q04___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q04___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q05 (0x005DEA54) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q05___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q05___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q05__DAC_CAL_S_Q05___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q05__DAC_CAL_S_Q05___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q05__DAC_CAL_S_Q05___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q05___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q05___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q06 (0x005DEA58) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q06___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q06___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q06__DAC_CAL_S_Q06___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q06__DAC_CAL_S_Q06___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q06__DAC_CAL_S_Q06___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q06___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q06___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q07 (0x005DEA5C) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q07___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q07___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q07__DAC_CAL_S_Q07___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q07__DAC_CAL_S_Q07___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q07__DAC_CAL_S_Q07___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q07___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q07___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q08 (0x005DEA60) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q08___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q08___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q08__DAC_CAL_S_Q08___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q08__DAC_CAL_S_Q08___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q08__DAC_CAL_S_Q08___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q08___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q08___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q09 (0x005DEA64) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q09___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q09___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q09__DAC_CAL_S_Q09___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q09__DAC_CAL_S_Q09___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q09__DAC_CAL_S_Q09___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q09___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q09___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q10 (0x005DEA68) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q10___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q10__DAC_CAL_S_Q10___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q10__DAC_CAL_S_Q10___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q10__DAC_CAL_S_Q10___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q10___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q10___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q11 (0x005DEA6C) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q11___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q11__DAC_CAL_S_Q11___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q11__DAC_CAL_S_Q11___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q11__DAC_CAL_S_Q11___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q11___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q11___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q12 (0x005DEA70) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q12___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q12__DAC_CAL_S_Q12___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q12__DAC_CAL_S_Q12___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q12__DAC_CAL_S_Q12___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q12___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q12___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q13 (0x005DEA74) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q13___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q13__DAC_CAL_S_Q13___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q13__DAC_CAL_S_Q13___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q13__DAC_CAL_S_Q13___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q13___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q13___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q14 (0x005DEA78) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q14___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q14__DAC_CAL_S_Q14___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q14__DAC_CAL_S_Q14___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q14__DAC_CAL_S_Q14___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q14___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q14___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q15 (0x005DEA7C) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q15___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q15__DAC_CAL_S_Q15___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q15__DAC_CAL_S_Q15___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q15__DAC_CAL_S_Q15___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q15___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q15___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q16 (0x005DEA80) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q16___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q16__DAC_CAL_S_Q16___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q16__DAC_CAL_S_Q16___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q16__DAC_CAL_S_Q16___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q16___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q16___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q17 (0x005DEA84) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q17___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q17__DAC_CAL_S_Q17___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q17__DAC_CAL_S_Q17___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q17__DAC_CAL_S_Q17___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q17___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q17___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q18 (0x005DEA88) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q18___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q18__DAC_CAL_S_Q18___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q18__DAC_CAL_S_Q18___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q18__DAC_CAL_S_Q18___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q18___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q18___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q19 (0x005DEA8C) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q19___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q19__DAC_CAL_S_Q19___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q19__DAC_CAL_S_Q19___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q19__DAC_CAL_S_Q19___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q19___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q19___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q20 (0x005DEA90) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q20___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q20__DAC_CAL_S_Q20___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q20__DAC_CAL_S_Q20___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q20__DAC_CAL_S_Q20___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q20___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q20___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q21 (0x005DEA94) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q21___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q21__DAC_CAL_S_Q21___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q21__DAC_CAL_S_Q21___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q21__DAC_CAL_S_Q21___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q21___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q21___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q22 (0x005DEA98) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q22___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q22__DAC_CAL_S_Q22___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q22__DAC_CAL_S_Q22___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q22__DAC_CAL_S_Q22___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q22___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q22___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q23 (0x005DEA9C) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q23___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q23__DAC_CAL_S_Q23___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q23__DAC_CAL_S_Q23___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q23__DAC_CAL_S_Q23___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q23___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q23___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q24 (0x005DEAA0) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q24___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q24__DAC_CAL_S_Q24___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q24__DAC_CAL_S_Q24___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q24__DAC_CAL_S_Q24___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q24___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q24___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q25 (0x005DEAA4) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q25___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q25__DAC_CAL_S_Q25___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q25__DAC_CAL_S_Q25___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q25__DAC_CAL_S_Q25___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q25___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q25___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q26 (0x005DEAA8) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q26___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q26__DAC_CAL_S_Q26___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q26__DAC_CAL_S_Q26___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q26__DAC_CAL_S_Q26___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q26___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q26___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q27 (0x005DEAAC) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q27___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q27__DAC_CAL_S_Q27___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q27__DAC_CAL_S_Q27___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q27__DAC_CAL_S_Q27___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q27___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q27___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q28 (0x005DEAB0) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q28___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q28__DAC_CAL_S_Q28___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q28__DAC_CAL_S_Q28___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q28__DAC_CAL_S_Q28___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q28___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q28___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q29 (0x005DEAB4) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q29___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q29__DAC_CAL_S_Q29___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q29__DAC_CAL_S_Q29___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q29__DAC_CAL_S_Q29___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q29___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q29___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q30 (0x005DEAB8) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q30___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q30__DAC_CAL_S_Q30___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q30__DAC_CAL_S_Q30___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q30__DAC_CAL_S_Q30___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q30___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q30___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q31 (0x005DEABC) +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q31___POR 0x00000020 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q31__DAC_CAL_S_Q31___POR 0x20 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q31__DAC_CAL_S_Q31___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q31__DAC_CAL_S_Q31___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q31___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_DIG_CORRECTION_DAC_CAL_REG_Q31___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI0 (0x005DEAC0) +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI0__DAC_CAL_BIN_I0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI0__DAC_CAL_BIN_I0___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI0__DAC_CAL_BIN_I0___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI0___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI0___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI1 (0x005DEAC4) +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI1__DAC_CAL_BIN_I1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI1__DAC_CAL_BIN_I1___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI1__DAC_CAL_BIN_I1___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI1___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI1___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI2 (0x005DEAC8) +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI2__DAC_CAL_BIN_I2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI2__DAC_CAL_BIN_I2___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI2__DAC_CAL_BIN_I2___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI2___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI2___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI3 (0x005DEACC) +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI3___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI3__DAC_CAL_BIN_I3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI3__DAC_CAL_BIN_I3___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI3__DAC_CAL_BIN_I3___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI3___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI3___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI4 (0x005DEAD0) +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI4___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI4__DAC_CAL_BIN_I4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI4__DAC_CAL_BIN_I4___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI4__DAC_CAL_BIN_I4___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI4___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI4___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI5 (0x005DEAD4) +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI5___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI5__DAC_CAL_BIN_I5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI5__DAC_CAL_BIN_I5___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI5__DAC_CAL_BIN_I5___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI5___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI5___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI6 (0x005DEAD8) +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI6___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI6__DAC_CAL_BIN_I6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI6__DAC_CAL_BIN_I6___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI6__DAC_CAL_BIN_I6___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI6___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI6___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI7 (0x005DEADC) +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI7___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI7__DAC_CAL_BIN_I7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI7__DAC_CAL_BIN_I7___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI7__DAC_CAL_BIN_I7___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI7___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI7___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI8 (0x005DEAE0) +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI8___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI8__DAC_CAL_BIN_I8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI8__DAC_CAL_BIN_I8___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI8__DAC_CAL_BIN_I8___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI8___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGI8___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ0 (0x005DEAE4) +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ0__DAC_CAL_BIN_Q0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ0__DAC_CAL_BIN_Q0___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ0__DAC_CAL_BIN_Q0___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ0___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ0___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ1 (0x005DEAE8) +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ1__DAC_CAL_BIN_Q1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ1__DAC_CAL_BIN_Q1___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ1__DAC_CAL_BIN_Q1___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ1___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ1___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ2 (0x005DEAEC) +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ2__DAC_CAL_BIN_Q2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ2__DAC_CAL_BIN_Q2___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ2__DAC_CAL_BIN_Q2___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ2___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ2___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ3 (0x005DEAF0) +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ3___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ3__DAC_CAL_BIN_Q3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ3__DAC_CAL_BIN_Q3___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ3__DAC_CAL_BIN_Q3___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ3___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ3___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ4 (0x005DEAF4) +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ4___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ4__DAC_CAL_BIN_Q4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ4__DAC_CAL_BIN_Q4___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ4__DAC_CAL_BIN_Q4___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ4___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ4___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ5 (0x005DEAF8) +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ5___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ5__DAC_CAL_BIN_Q5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ5__DAC_CAL_BIN_Q5___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ5__DAC_CAL_BIN_Q5___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ5___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ5___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ6 (0x005DEAFC) +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ6___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ6__DAC_CAL_BIN_Q6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ6__DAC_CAL_BIN_Q6___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ6__DAC_CAL_BIN_Q6___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ6___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ6___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ7 (0x005DEB00) +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ7___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ7__DAC_CAL_BIN_Q7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ7__DAC_CAL_BIN_Q7___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ7__DAC_CAL_BIN_Q7___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ7___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ7___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ8 (0x005DEB04) +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ8___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ8__DAC_CAL_BIN_Q8___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ8__DAC_CAL_BIN_Q8___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ8__DAC_CAL_BIN_Q8___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ8___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_BIN_REGQ8___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1 (0x005DEB08) +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DAC_CAL_REG1_SPARE___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DAC_DTEST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DAC_DTEST_PLL_TEST_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DAC_DTEST_DBG_OUT_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__D_DAC_COMP_OFFSET_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__D_DAC_COMP_OFFSET_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__CAL_SA_OUTPUTS_INVERT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__COMP_IN_INVERT_OFFSET___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DBG_CAL_CLK___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DBG_CAL_CLK_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__COMP_IN_INVERT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__CAL_N_SAMPLES___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__CAL_STROBE_RESAMP_TMR___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__COMP_SETT_TMR___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__CAL_STROBE_TMR___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__CAL_FSM_FREEZE___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DAC_CAL_REG1_SPARE___M 0xC0000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DAC_CAL_REG1_SPARE___S 30 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DAC_DTEST_EN___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DAC_DTEST_EN___S 29 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DAC_DTEST_PLL_TEST_SEL___M 0x1C000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DAC_DTEST_PLL_TEST_SEL___S 26 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DAC_DTEST_DBG_OUT_SEL___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DAC_DTEST_DBG_OUT_SEL___S 23 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__D_DAC_COMP_OFFSET_OV___M 0x00400000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__D_DAC_COMP_OFFSET_OV___S 22 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__D_DAC_COMP_OFFSET_OVD___M 0x003F0000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__D_DAC_COMP_OFFSET_OVD___S 16 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__CAL_SA_OUTPUTS_INVERT___M 0x00008000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__CAL_SA_OUTPUTS_INVERT___S 15 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__COMP_IN_INVERT_OFFSET___M 0x00004000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__COMP_IN_INVERT_OFFSET___S 14 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DBG_CAL_CLK___M 0x00002000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DBG_CAL_CLK___S 13 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DBG_CAL_CLK_EN___M 0x00001000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__DBG_CAL_CLK_EN___S 12 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__COMP_IN_INVERT___M 0x00000800 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__COMP_IN_INVERT___S 11 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__CAL_N_SAMPLES___M 0x00000600 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__CAL_N_SAMPLES___S 9 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__CAL_STROBE_RESAMP_TMR___M 0x00000180 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__CAL_STROBE_RESAMP_TMR___S 7 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__COMP_SETT_TMR___M 0x00000060 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__COMP_SETT_TMR___S 5 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__CAL_STROBE_TMR___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__CAL_STROBE_TMR___S 3 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__CAL_FSM_FREEZE___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1__CAL_FSM_FREEZE___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG1___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2 (0x005DEB0C) +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DAC_CAL_REG2_SPARE1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_BIN_DATA___POR 0x000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_MSB_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_DATA_CARRY___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DAC_CAL_REG2_SPARE0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_MSB_VAL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_OFFSET___POR 0x00 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_COMP_STROBE___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_MODE_Q___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_MODE_I___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_FSM_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DAC_CAL_REG2_SPARE1___M 0x80000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DAC_CAL_REG2_SPARE1___S 31 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_BIN_DATA___M 0x7FC00000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_BIN_DATA___S 22 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_MSB_SEL___M 0x003E0000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_MSB_SEL___S 17 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_DATA_CARRY___M 0x00010000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_DATA_CARRY___S 16 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DAC_CAL_REG2_SPARE0___M 0x0000F800 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DAC_CAL_REG2_SPARE0___S 11 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_MSB_VAL___M 0x00000400 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_MSB_VAL___S 10 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_OFFSET___M 0x000003F0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_OFFSET___S 4 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_COMP_STROBE___M 0x00000008 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_COMP_STROBE___S 3 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_MODE_Q___M 0x00000004 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_MODE_Q___S 2 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_MODE_I___M 0x00000002 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_MODE_I___S 1 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_FSM_BYPASS___M 0x00000001 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2__DBG_CAL_FSM_BYPASS___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG2___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG3 (0x005DEB10) +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG3___POR 0x000001FF +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG3__DAC_CAL_REG3___POR 0x000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG3__D_DAC_CAL_BIN_SEL___POR 0x1FF +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG3__DAC_CAL_REG3___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG3__DAC_CAL_REG3___S 9 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG3__D_DAC_CAL_BIN_SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG3__D_DAC_CAL_BIN_SEL___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG3___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG4 (0x005DEB14) +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG4___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG4__DAC_CAL_REG4___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG4__DAC_CAL_REG4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG4__DAC_CAL_REG4___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_REG4___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1 (0x005DEB18) +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1__RO_CAL_SI_ACCUM___POR 0x0000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1__DAC_CAL_SM_STATUS1_SPARE___POR 0x0000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1__RO_CAL_Q_FROZE_AFTER_CI___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_SI___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_CI___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1__RO_CAL_SI_ACCUM___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1__RO_CAL_SI_ACCUM___S 16 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1__DAC_CAL_SM_STATUS1_SPARE___M 0x0000FFF8 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1__DAC_CAL_SM_STATUS1_SPARE___S 3 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1__RO_CAL_Q_FROZE_AFTER_CI___M 0x00000004 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1__RO_CAL_Q_FROZE_AFTER_CI___S 2 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_SI___M 0x00000002 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_SI___S 1 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_CI___M 0x00000001 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_CI___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG1___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG2 (0x005DEB1C) +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG2__RO_MAX_CLIP_Q___POR 0x00 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG2__RO_MIN_CLIP_Q___POR 0x00 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG2__RO_MAX_CLIP_I___POR 0x00 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG2__RO_MIN_CLIP_I___POR 0x00 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG2__RO_MAX_CLIP_Q___M 0xFF000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG2__RO_MAX_CLIP_Q___S 24 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG2__RO_MIN_CLIP_Q___M 0x00FF0000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG2__RO_MIN_CLIP_Q___S 16 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG2__RO_MAX_CLIP_I___M 0x0000FF00 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG2__RO_MAX_CLIP_I___S 8 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG2__RO_MIN_CLIP_I___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG2__RO_MIN_CLIP_I___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG2___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3 (0x005DEB20) +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CAL_BIN_DATA___POR 0x000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CAL_MSB_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CALDATA_CARRY___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_COMP_OFFSET___POR 0x00 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CAL_COMP_STROBE___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CAL_MODE_Q___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CAL_MODE_I___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_COMPOUT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE1___M 0x80000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE1___S 31 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CAL_BIN_DATA___M 0x7FC00000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CAL_BIN_DATA___S 22 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CAL_MSB_SEL___M 0x003E0000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CAL_MSB_SEL___S 17 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CALDATA_CARRY___M 0x00010000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CALDATA_CARRY___S 16 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE0___M 0x0000FC00 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE0___S 10 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_COMP_OFFSET___M 0x000003F0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_COMP_OFFSET___S 4 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CAL_COMP_STROBE___M 0x00000008 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CAL_COMP_STROBE___S 3 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CAL_MODE_Q___M 0x00000004 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CAL_MODE_Q___S 2 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CAL_MODE_I___M 0x00000002 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_CAL_MODE_I___S 1 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_COMPOUT___M 0x00000001 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3__RO_COMPOUT___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG3___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG4 (0x005DEB24) +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG4___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG4___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG4__DAC_CAL_SM_STATUS4_SPARE___POR 0x000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG4__RO_CAL_DC_VAL___POR 0x00 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG4__DAC_CAL_SM_STATUS4_SPARE___M 0xFFFFFF00 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG4__DAC_CAL_SM_STATUS4_SPARE___S 8 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG4__RO_CAL_DC_VAL___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG4__RO_CAL_DC_VAL___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_STATUS_REG4___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_CTRL (0x005DEB28) +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_CTRL___POR 0x00000004 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_CTRL__DAC_DISABLE_CORRECTION___POR 0x1 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_CTRL__DAC_CAL_RANGE___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_CTRL__DAC_DISABLE_CORRECTION___M 0x00000004 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_CTRL__DAC_DISABLE_CORRECTION___S 2 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_CTRL__DAC_CAL_RANGE___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_CTRL__DAC_CAL_RANGE___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_CTRL___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_SM_CTRL___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG (0x005DEB2C) +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG__MSB_SEL_OFFSET___POR 0x00 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG__CAL_MSB_VAL_OV_REG___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG__DAC_EN_D_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG__C_CLKDAC1X_INVERT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG__D_DAC_SPARE___POR 0x00 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG__MSB_SEL_OFFSET___M 0x0001F000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG__MSB_SEL_OFFSET___S 12 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG__CAL_MSB_VAL_OV_REG___M 0x00000800 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG__CAL_MSB_VAL_OV_REG___S 11 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG__DAC_EN_D_SEL___M 0x00000600 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG__DAC_EN_D_SEL___S 9 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG__C_CLKDAC1X_INVERT___M 0x00000100 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG__C_CLKDAC1X_INVERT___S 8 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG__D_DAC_SPARE___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG__D_DAC_SPARE___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG___M 0x0001FFFF +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_MISC_REG___S 0 + +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_RO_SPARE_REG (0x005DEB30) +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_RO_SPARE_REG___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_RO_SPARE_REG___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_RO_SPARE_REG__D_DAC_RO_SPARE___POR 0x0000 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_RO_SPARE_REG__D_DAC_RO_SPARE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_RO_SPARE_REG__D_DAC_RO_SPARE___S 0 +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_RO_SPARE_REG___M 0x0000FFFF +#define PHYA_IRON2G_RFA_BT_DAC_MISC_DAC_RO_SPARE_REG___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_0 (0x005DEC00) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_0__D_ADC_ATBSEL___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_0__D_ADC_ATBSEL___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_0__D_ADC_ATBSEL___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_0___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_0___S 8 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1 (0x005DEC04) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1___POR 0x7C007000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_ADC_CLK_PHASE_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIA_IR_EN___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIAI_IC_EN___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIAI_IPT_EN___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIAQ_IC_EN___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIAQ_IPT_EN___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIA_VCM___POR 0x7 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_ADC_BIAS_PROG___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_ADC_CLK_PHASE_SEL___M 0x80000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_ADC_CLK_PHASE_SEL___S 31 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIA_IR_EN___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIA_IR_EN___S 30 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIAI_IC_EN___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIAI_IC_EN___S 29 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIAI_IPT_EN___M 0x10000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIAI_IPT_EN___S 28 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIAQ_IC_EN___M 0x08000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIAQ_IC_EN___S 27 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIAQ_IPT_EN___M 0x04000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIAQ_IPT_EN___S 26 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIA_VCM___M 0x0000F000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_RXBB_TIA_VCM___S 12 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_ADC_BIAS_PROG___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1__D_ADC_BIAS_PROG___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1___M 0xFC00F003 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_STATIC_1___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_LUT (0x005DEC08) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_LUT___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_LUT___POR 0x1C081009 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_3___POR 0x1C +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_2___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_1___POR 0x10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_0___POR 0x09 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_LUT___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_LUT___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_0 (0x005DEC0C) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_0___POR 0x1A1A1A1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_3___POR 0x1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_2___POR 0x1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_1___POR 0x1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_0___POR 0x1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_0___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_0___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_1 (0x005DEC10) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_1___POR 0x14141A1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_7___POR 0x14 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_6___POR 0x14 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_5___POR 0x1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_4___POR 0x1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_1___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_1___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_2 (0x005DEC14) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_2___POR 0x12121A1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_3___POR 0x12 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_2___POR 0x12 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_1___POR 0x1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_0___POR 0x1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_2___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_2___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_3 (0x005DEC18) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_3___POR 0x0A0A1410 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_7___POR 0x0A +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_6___POR 0x0A +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_5___POR 0x14 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_4___POR 0x10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_3___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_3___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_4 (0x005DEC1C) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_4___POR 0x0C100E1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_3___POR 0x0C +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_2___POR 0x10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_1___POR 0x0E +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_0___POR 0x1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_4___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_4___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_5 (0x005DEC20) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_5___POR 0x0E0E0E0A +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_7___POR 0x0E +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_6___POR 0x0E +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_5___POR 0x0E +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_4___POR 0x0A +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_5___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_5___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_6 (0x005DEC24) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_6___POR 0x120E0E14 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_3___POR 0x12 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_2___POR 0x0E +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_1___POR 0x0E +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_0___POR 0x14 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_6___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_6___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_7 (0x005DEC28) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_7___POR 0x0E0E0C10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_7___POR 0x0E +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_6___POR 0x0E +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_5___POR 0x0C +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_4___POR 0x10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_7___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_GAIN_SLNA_LUT_7___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_LUT (0x005DEC2C) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_LUT___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_LUT___POR 0x17191016 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_3___POR 0x17 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_2___POR 0x19 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_1___POR 0x10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_0___POR 0x16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_LUT___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_LUT___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_0 (0x005DEC30) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_0___POR 0x08080808 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_3___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_2___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_1___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_0___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_0___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_0___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_1 (0x005DEC34) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_1___POR 0x0E0E0808 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_7___POR 0x0E +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_6___POR 0x0E +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_5___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_4___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_1___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_1___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_2 (0x005DEC38) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_2___POR 0x05110808 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_3___POR 0x05 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_2___POR 0x11 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_1___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_0___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_2___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_2___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_3 (0x005DEC3C) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_3___POR 0x0A0A1410 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_7___POR 0x0A +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_6___POR 0x0A +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_5___POR 0x14 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_4___POR 0x10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_3___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_3___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_4 (0x005DEC40) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_4___POR 0x18081608 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_3___POR 0x18 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_2___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_1___POR 0x16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_0___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_4___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_4___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_5 (0x005DEC44) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_5___POR 0x14141413 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_7___POR 0x14 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_6___POR 0x14 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_5___POR 0x14 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_4___POR 0x13 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_5___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_5___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_6 (0x005DEC48) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_6___POR 0x0A141404 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_3___POR 0x0A +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_2___POR 0x14 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_1___POR 0x14 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_0___POR 0x04 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_6___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_6___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_7 (0x005DEC4C) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_7___POR 0x07070F10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_7___POR 0x07 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_6___POR 0x07 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_5___POR 0x0F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_4___POR 0x10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_7___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_SLNA_LUT_7___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_LUT (0x005DEC50) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_LUT___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_LUT___POR 0x1011080E +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_3___POR 0x10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_2___POR 0x11 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_1___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_0___POR 0x0E +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_LUT___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_LUT___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_0 (0x005DEC54) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_3___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_2___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_0___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_0___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_1 (0x005DEC58) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_1___POR 0x03030000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_7___POR 0x03 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_6___POR 0x03 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_5___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_4___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_1___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_1___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_2 (0x005DEC5C) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_2___POR 0x05050000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_3___POR 0x05 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_2___POR 0x05 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_2___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_2___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_3 (0x005DEC60) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_3___POR 0x0C0C0208 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_7___POR 0x0C +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_6___POR 0x0C +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_5___POR 0x02 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_4___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_3___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_3___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_4 (0x005DEC64) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_4___POR 0x0A070800 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_3___POR 0x0A +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_2___POR 0x07 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_1___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_4___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_4___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_5 (0x005DEC68) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_5___POR 0x0C0C0C0C +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_7___POR 0x0C +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_6___POR 0x0C +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_5___POR 0x0C +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_4___POR 0x0C +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_5___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_5___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_6 (0x005DEC6C) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_6___POR 0x050C0C02 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_3___POR 0x05 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_2___POR 0x0C +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_1___POR 0x0C +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_0___POR 0x02 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_6___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_6___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_7 (0x005DEC70) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_7___POR 0x03030808 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_7___POR 0x03 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_6___POR 0x03 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_5___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_4___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_7___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_TIA_CAP_2M_SLNA_LUT_7___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_ADC_CAL (0x005DEC74) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_ADC_CAL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_ADC_CAL___POR 0x00000007 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_ADC_CAL__D_RXBB_ADC_VCM___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_ADC_CAL__D_ADC_RES___POR 0x7 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_ADC_CAL__D_RXBB_ADC_VCM___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_ADC_CAL__D_RXBB_ADC_VCM___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_ADC_CAL__D_ADC_RES___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_ADC_CAL__D_ADC_RES___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_ADC_CAL___M 0x00000F0F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_ADC_CAL___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT (0x005DEC78) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT___POR 0x999BBDCE +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_3___POR 0x9 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_3___POR 0x9 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_2___POR 0x9 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_2___POR 0xB +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_1___POR 0xB +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_1___POR 0xD +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_0___POR 0xC +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_0___POR 0xE +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_3___M 0xF0000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_3___S 28 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_3___M 0x0F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_2___M 0x00F00000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_2___S 20 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_2___M 0x000F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_1___M 0x0000F000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_1___S 12 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_1___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_0___M 0x000000F0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_0___S 4 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_0___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_CAP_LUT___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT (0x005DEC7C) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT___POR 0x0F0D0C0C +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_3___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_3___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_2___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_2___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_1___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_0___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_3___M 0x80000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_3___S 31 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_3___M 0x70000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_3___S 28 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_3___M 0x0C000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_3___S 26 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_3___M 0x03000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_2___M 0x00800000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_2___S 23 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_2___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_2___S 20 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_2___M 0x000C0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_2___S 18 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_2___M 0x00030000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_1___M 0x00008000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_1___S 15 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_1___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_1___S 12 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_1___M 0x00000C00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_1___S 10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_1___M 0x00000300 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_0___M 0x00000080 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_0___S 7 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_0___M 0x00000070 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_0___S 4 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_0___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_0___S 2 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_0___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_COARSE_GAIN_LUT___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX (0x005DEC80) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX__D_RXBB_TMX_OUT_EN_I___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX__D_RXBB_TMX_OUT_EN_Q___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX__D_RXBB_IQMUX_SWAP___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX__D_RXBB_TXPDET_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX__D_RXBB_TXPDET0_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX__D_RXBB_TMX_OUT_EN_I___M 0x00000060 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX__D_RXBB_TMX_OUT_EN_I___S 5 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX__D_RXBB_TMX_OUT_EN_Q___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX__D_RXBB_TMX_OUT_EN_Q___S 3 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX__D_RXBB_IQMUX_SWAP___M 0x00000004 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX__D_RXBB_IQMUX_SWAP___S 2 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX__D_RXBB_TXPDET_EN___M 0x00000002 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX__D_RXBB_TXPDET_EN___S 1 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX__D_RXBB_TXPDET0_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX__D_RXBB_TXPDET0_EN___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX___M 0x0000007F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_BB_MUX___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_0 (0x005DEC84) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_0__D_RXBB_TIA_EN_I_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_0__D_RXBB_TIA_EN_Q_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_0__D_ADC_BTLE_SEL_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_0__D_RXBB_TIA_EN_I_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_0__D_RXBB_TIA_EN_I_OVS___S 6 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_0__D_RXBB_TIA_EN_Q_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_0__D_RXBB_TIA_EN_Q_OVS___S 4 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_0__D_ADC_BTLE_SEL_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_0__D_ADC_BTLE_SEL_OVS___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_0___M 0x000000F3 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_0___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_1 (0x005DEC88) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_1__D_ADC_EN_I_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_1__D_ADC_EN_Q_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_1__D_ADC_EN64M_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_1__D_ADC_RESET_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_1__D_ADC_EN_I_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_1__D_ADC_EN_I_OVS___S 14 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_1__D_ADC_EN_Q_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_1__D_ADC_EN_Q_OVS___S 12 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_1__D_ADC_EN64M_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_1__D_ADC_EN64M_OVS___S 10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_1__D_ADC_RESET_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_1__D_ADC_RESET_OVS___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_1___M 0x0000FF00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_EN_OV_1___S 8 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_BB_OV (0x005DEC8C) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_BB_OV___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_BB_OV___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_BB_OV__BT_RXBB_TIA_GAIN_FINE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_BB_OV__BT_RXBB_TIA_GAIN_FINE_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_BB_OV__BT_RXBB_TIA_CAP_FINE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_BB_OV__BT_RXBB_TIA_CAP_FINE_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_BB_OV__BT_RXBB_TIA_GAIN_FINE_OV___M 0x00200000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_BB_OV__BT_RXBB_TIA_GAIN_FINE_OV___S 21 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_BB_OV__BT_RXBB_TIA_GAIN_FINE_OVD___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_BB_OV__BT_RXBB_TIA_GAIN_FINE_OVD___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_BB_OV__BT_RXBB_TIA_CAP_FINE_OV___M 0x00002000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_BB_OV__BT_RXBB_TIA_CAP_FINE_OV___S 13 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_BB_OV__BT_RXBB_TIA_CAP_FINE_OVD___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_BB_OV__BT_RXBB_TIA_CAP_FINE_OVD___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_BB_OV___M 0x003F3F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_BB_OV___S 8 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV (0x005DEC90) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_VLG_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_BOOST_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_BOOST_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_CAP_COARSE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_CAP_COARSE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_OA_CP_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_OA_CP_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_GAIN_COARSE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_GAIN_COARSE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_VLG_EN_OVS___M 0x00060000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_VLG_EN_OVS___S 17 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_BOOST_OV___M 0x00010000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_BOOST_OV___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_BOOST_OVD___M 0x0000E000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_BOOST_OVD___S 13 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_CAP_COARSE_OV___M 0x00001000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_CAP_COARSE_OV___S 12 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_CAP_COARSE_OVD___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_CAP_COARSE_OVD___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_OA_CP_OV___M 0x00000020 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_OA_CP_OV___S 5 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_OA_CP_OVD___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_OA_CP_OVD___S 3 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_GAIN_COARSE_OV___M 0x00000004 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_GAIN_COARSE_OV___S 2 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_GAIN_COARSE_OVD___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV__D_RXBB_TIA_GAIN_COARSE_OVD___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV___M 0x0007FF3F +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TIA_OV___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV (0x005DEC94) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV__D_ADC_RN_I_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV__D_ADC_RN_Q_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV__D_ADC_EN_DWA_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV__D_ADC_IC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV__D_ADC_IR_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV__D_ADC_RN_I_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV__D_ADC_RN_I_OVS___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV__D_ADC_RN_Q_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV__D_ADC_RN_Q_OVS___S 14 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV__D_ADC_EN_DWA_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV__D_ADC_EN_DWA_OVS___S 12 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV__D_ADC_IC_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV__D_ADC_IC_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV__D_ADC_IR_EN_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV__D_ADC_IR_EN_OVS___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV___M 0x0003FF00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_RX_OV___S 8 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_SPARE_0 (0x005DEC98) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_SPARE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_SPARE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_SPARE_0__SPARE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_SPARE_0__SPARE_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_SPARE_0__SPARE_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_SPARE_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_SPARE_0___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_SPARE_1 (0x005DEC9C) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_SPARE_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_SPARE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_SPARE_1__SPARE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_SPARE_1__SPARE_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_SPARE_1__SPARE_1___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_SPARE_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_SPARE_1___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TEST_MODE (0x005DECA0) +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TEST_MODE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TEST_MODE___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TEST_MODE__DTOP_TEST_MUX_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TEST_MODE__DTOP_TEST_MUX_SEL___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TEST_MODE__DTOP_TEST_MUX_SEL___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TEST_MODE___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_RXBB_CH0_TEST_MODE___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_0 (0x005DEE00) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_0__D_ADC_ATBSEL___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_0__D_ADC_ATBSEL___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_0__D_ADC_ATBSEL___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_0___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_0___S 8 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1 (0x005DEE04) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1___POR 0x7C007000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_ADC_CLK_PHASE_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIA_IR_EN___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIAI_IC_EN___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIAI_IPT_EN___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIAQ_IC_EN___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIAQ_IPT_EN___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIA_VCM___POR 0x7 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_ADC_BIAS_PROG___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_ADC_CLK_PHASE_SEL___M 0x80000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_ADC_CLK_PHASE_SEL___S 31 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIA_IR_EN___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIA_IR_EN___S 30 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIAI_IC_EN___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIAI_IC_EN___S 29 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIAI_IPT_EN___M 0x10000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIAI_IPT_EN___S 28 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIAQ_IC_EN___M 0x08000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIAQ_IC_EN___S 27 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIAQ_IPT_EN___M 0x04000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIAQ_IPT_EN___S 26 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIA_VCM___M 0x0000F000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_RXBB_TIA_VCM___S 12 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_ADC_BIAS_PROG___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1__D_ADC_BIAS_PROG___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1___M 0xFC00F003 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_STATIC_1___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_LUT (0x005DEE08) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_LUT___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_LUT___POR 0x1C081009 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_3___POR 0x1C +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_2___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_1___POR 0x10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_0___POR 0x09 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_LUT__D_RXBB_TIA_GAIN_FINE_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_LUT___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_LUT___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_0 (0x005DEE0C) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_0___POR 0x1A1A1A1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_3___POR 0x1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_2___POR 0x1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_1___POR 0x1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_0___POR 0x1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_0__D_RXBB_TIA_GAIN_FINE_3_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_0___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_0___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_1 (0x005DEE10) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_1___POR 0x14141A1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_7___POR 0x14 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_6___POR 0x14 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_5___POR 0x1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_4___POR 0x1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_1__D_RXBB_TIA_GAIN_FINE_3_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_1___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_1___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_2 (0x005DEE14) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_2___POR 0x12121A1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_3___POR 0x12 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_2___POR 0x12 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_1___POR 0x1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_0___POR 0x1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_2__D_RXBB_TIA_GAIN_FINE_2_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_2___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_2___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_3 (0x005DEE18) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_3___POR 0x0A0A1410 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_7___POR 0x0A +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_6___POR 0x0A +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_5___POR 0x14 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_4___POR 0x10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_3__D_RXBB_TIA_GAIN_FINE_2_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_3___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_3___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_4 (0x005DEE1C) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_4___POR 0x0C100E1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_3___POR 0x0C +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_2___POR 0x10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_1___POR 0x0E +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_0___POR 0x1A +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_4__D_RXBB_TIA_GAIN_FINE_1_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_4___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_4___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_5 (0x005DEE20) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_5___POR 0x0E0E0E0A +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_7___POR 0x0E +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_6___POR 0x0E +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_5___POR 0x0E +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_4___POR 0x0A +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_5__D_RXBB_TIA_GAIN_FINE_1_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_5___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_5___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_6 (0x005DEE24) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_6___POR 0x120E0E14 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_3___POR 0x12 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_2___POR 0x0E +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_1___POR 0x0E +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_0___POR 0x14 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_6__D_RXBB_TIA_GAIN_FINE_0_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_6___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_6___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_7 (0x005DEE28) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_7___POR 0x0E0E0C10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_7___POR 0x0E +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_6___POR 0x0E +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_5___POR 0x0C +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_4___POR 0x10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_7__D_RXBB_TIA_GAIN_FINE_0_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_7___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_GAIN_SLNA_LUT_7___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_LUT (0x005DEE2C) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_LUT___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_LUT___POR 0x17191016 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_3___POR 0x17 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_2___POR 0x19 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_1___POR 0x10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_0___POR 0x16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_LUT__D_RXBB_TIA_CAP_FINE_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_LUT___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_LUT___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_0 (0x005DEE30) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_0___POR 0x08080808 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_3___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_2___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_1___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_0___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_3_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_0___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_0___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_1 (0x005DEE34) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_1___POR 0x0E0E0808 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_7___POR 0x0E +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_6___POR 0x0E +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_5___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_4___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_3_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_1___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_1___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_2 (0x005DEE38) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_2___POR 0x05110808 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_3___POR 0x05 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_2___POR 0x11 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_1___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_0___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_2___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_2___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_3 (0x005DEE3C) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_3___POR 0x0A0A1410 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_7___POR 0x0A +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_6___POR 0x0A +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_5___POR 0x14 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_4___POR 0x10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_3___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_3___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_4 (0x005DEE40) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_4___POR 0x18081608 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_3___POR 0x18 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_2___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_1___POR 0x16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_0___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_1_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_4___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_4___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_5 (0x005DEE44) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_5___POR 0x14141413 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_7___POR 0x14 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_6___POR 0x14 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_5___POR 0x14 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_4___POR 0x13 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_1_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_5___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_5___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_6 (0x005DEE48) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_6___POR 0x0A141404 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_3___POR 0x0A +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_2___POR 0x14 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_1___POR 0x14 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_0___POR 0x04 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_0_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_6___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_6___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_7 (0x005DEE4C) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_7___POR 0x07070F10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_7___POR 0x07 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_6___POR 0x07 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_5___POR 0x0F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_4___POR 0x10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_0_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_7___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_SLNA_LUT_7___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_LUT (0x005DEE50) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_LUT___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_LUT___POR 0x1011080E +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_3___POR 0x10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_2___POR 0x11 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_1___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_0___POR 0x0E +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_LUT__D_RXBB_TIA_CAP_FINE_2M_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_LUT___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_LUT___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_0 (0x005DEE54) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_3___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_2___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_0__D_RXBB_TIA_CAP_FINE_2M_3_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_0___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_0___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_1 (0x005DEE58) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_1___POR 0x03030000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_7___POR 0x03 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_6___POR 0x03 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_5___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_4___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_1__D_RXBB_TIA_CAP_FINE_2M_3_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_1___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_1___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_2 (0x005DEE5C) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_2___POR 0x05050000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_3___POR 0x05 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_2___POR 0x05 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_2__D_RXBB_TIA_CAP_FINE_2M_2_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_2___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_2___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_3 (0x005DEE60) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_3___POR 0x0C0C0208 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_7___POR 0x0C +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_6___POR 0x0C +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_5___POR 0x02 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_4___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_3__D_RXBB_TIA_CAP_FINE_2M_2_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_3___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_3___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_4 (0x005DEE64) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_4___POR 0x0A070800 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_3___POR 0x0A +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_2___POR 0x07 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_1___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_4__D_RXBB_TIA_CAP_FINE_2M_1_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_4___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_4___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_5 (0x005DEE68) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_5___POR 0x0C0C0C0C +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_7___POR 0x0C +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_6___POR 0x0C +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_5___POR 0x0C +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_4___POR 0x0C +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_5__D_RXBB_TIA_CAP_FINE_2M_1_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_5___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_5___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_6 (0x005DEE6C) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_6___POR 0x050C0C02 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_3___POR 0x05 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_2___POR 0x0C +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_1___POR 0x0C +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_0___POR 0x02 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_3___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_0___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_6__D_RXBB_TIA_CAP_FINE_2M_0_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_6___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_6___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_7 (0x005DEE70) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_7___POR 0x03030808 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_7___POR 0x03 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_6___POR 0x03 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_5___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_4___POR 0x08 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_7___M 0x1F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_7___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_6___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_4___M 0x0000001F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_7__D_RXBB_TIA_CAP_FINE_2M_0_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_7___M 0x1F1F1F1F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_TIA_CAP_2M_SLNA_LUT_7___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_ADC_CAL (0x005DEE74) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_ADC_CAL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_ADC_CAL___POR 0x00000007 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_ADC_CAL__D_RXBB_ADC_VCM___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_ADC_CAL__D_ADC_RES___POR 0x7 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_ADC_CAL__D_RXBB_ADC_VCM___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_ADC_CAL__D_RXBB_ADC_VCM___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_ADC_CAL__D_ADC_RES___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_ADC_CAL__D_ADC_RES___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_ADC_CAL___M 0x00000F0F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_ADC_CAL___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT (0x005DEE78) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT___POR 0x999BBDCE +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_3___POR 0x9 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_3___POR 0x9 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_2___POR 0x9 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_2___POR 0xB +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_1___POR 0xB +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_1___POR 0xD +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_0___POR 0xC +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_0___POR 0xE +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_3___M 0xF0000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_3___S 28 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_3___M 0x0F000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_2___M 0x00F00000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_2___S 20 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_2___M 0x000F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_1___M 0x0000F000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_1___S 12 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_1___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_0___M 0x000000F0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_2M_0___S 4 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_0___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT__D_RXBB_TIA_CAP_COARSE_1M_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_CAP_LUT___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT (0x005DEE7C) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT___POR 0x0F0D0C0C +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_3___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_3___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_2___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_2___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_1___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_0___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_3___M 0x80000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_3___S 31 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_3___M 0x70000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_3___S 28 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_3___M 0x0C000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_3___S 26 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_3___M 0x03000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_2___M 0x00800000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_2___S 23 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_2___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_2___S 20 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_2___M 0x000C0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_2___S 18 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_2___M 0x00030000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_1___M 0x00008000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_1___S 15 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_1___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_1___S 12 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_1___M 0x00000C00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_1___S 10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_1___M 0x00000300 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_0___M 0x00000080 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_VLG_EN_0___S 7 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_0___M 0x00000070 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_BOOST_0___S 4 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_0___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_OA_CP_0___S 2 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_0___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT__D_RXBB_TIA_GAIN_COARSE_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_COARSE_GAIN_LUT___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX (0x005DEE80) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX__D_RXBB_TMX_OUT_EN_I___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX__D_RXBB_TMX_OUT_EN_Q___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX__D_RXBB_IQMUX_SWAP___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX__D_RXBB_TXPDET_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX__D_RXBB_TXPDET0_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX__D_RXBB_TMX_OUT_EN_I___M 0x00000060 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX__D_RXBB_TMX_OUT_EN_I___S 5 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX__D_RXBB_TMX_OUT_EN_Q___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX__D_RXBB_TMX_OUT_EN_Q___S 3 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX__D_RXBB_IQMUX_SWAP___M 0x00000004 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX__D_RXBB_IQMUX_SWAP___S 2 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX__D_RXBB_TXPDET_EN___M 0x00000002 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX__D_RXBB_TXPDET_EN___S 1 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX__D_RXBB_TXPDET0_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX__D_RXBB_TXPDET0_EN___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX___M 0x0000007F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_BB_MUX___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_0 (0x005DEE84) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_0__D_RXBB_TIA_EN_I_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_0__D_RXBB_TIA_EN_Q_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_0__D_ADC_BTLE_SEL_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_0__D_RXBB_TIA_EN_I_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_0__D_RXBB_TIA_EN_I_OVS___S 6 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_0__D_RXBB_TIA_EN_Q_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_0__D_RXBB_TIA_EN_Q_OVS___S 4 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_0__D_ADC_BTLE_SEL_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_0__D_ADC_BTLE_SEL_OVS___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_0___M 0x000000F3 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_0___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_1 (0x005DEE88) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_1__D_ADC_EN_I_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_1__D_ADC_EN_Q_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_1__D_ADC_EN64M_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_1__D_ADC_RESET_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_1__D_ADC_EN_I_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_1__D_ADC_EN_I_OVS___S 14 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_1__D_ADC_EN_Q_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_1__D_ADC_EN_Q_OVS___S 12 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_1__D_ADC_EN64M_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_1__D_ADC_EN64M_OVS___S 10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_1__D_ADC_RESET_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_1__D_ADC_RESET_OVS___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_1___M 0x0000FF00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_EN_OV_1___S 8 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_BB_OV (0x005DEE8C) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_BB_OV___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_BB_OV___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_BB_OV__BT_RXBB_TIA_GAIN_FINE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_BB_OV__BT_RXBB_TIA_GAIN_FINE_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_BB_OV__BT_RXBB_TIA_CAP_FINE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_BB_OV__BT_RXBB_TIA_CAP_FINE_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_BB_OV__BT_RXBB_TIA_GAIN_FINE_OV___M 0x00200000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_BB_OV__BT_RXBB_TIA_GAIN_FINE_OV___S 21 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_BB_OV__BT_RXBB_TIA_GAIN_FINE_OVD___M 0x001F0000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_BB_OV__BT_RXBB_TIA_GAIN_FINE_OVD___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_BB_OV__BT_RXBB_TIA_CAP_FINE_OV___M 0x00002000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_BB_OV__BT_RXBB_TIA_CAP_FINE_OV___S 13 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_BB_OV__BT_RXBB_TIA_CAP_FINE_OVD___M 0x00001F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_BB_OV__BT_RXBB_TIA_CAP_FINE_OVD___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_BB_OV___M 0x003F3F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_BB_OV___S 8 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV (0x005DEE90) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_VLG_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_BOOST_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_BOOST_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_CAP_COARSE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_CAP_COARSE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_OA_CP_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_OA_CP_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_GAIN_COARSE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_GAIN_COARSE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_VLG_EN_OVS___M 0x00060000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_VLG_EN_OVS___S 17 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_BOOST_OV___M 0x00010000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_BOOST_OV___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_BOOST_OVD___M 0x0000E000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_BOOST_OVD___S 13 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_CAP_COARSE_OV___M 0x00001000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_CAP_COARSE_OV___S 12 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_CAP_COARSE_OVD___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_CAP_COARSE_OVD___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_OA_CP_OV___M 0x00000020 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_OA_CP_OV___S 5 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_OA_CP_OVD___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_OA_CP_OVD___S 3 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_GAIN_COARSE_OV___M 0x00000004 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_GAIN_COARSE_OV___S 2 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_GAIN_COARSE_OVD___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV__D_RXBB_TIA_GAIN_COARSE_OVD___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV___M 0x0007FF3F +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TIA_OV___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV (0x005DEE94) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV__D_ADC_RN_I_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV__D_ADC_RN_Q_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV__D_ADC_EN_DWA_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV__D_ADC_IC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV__D_ADC_IR_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV__D_ADC_RN_I_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV__D_ADC_RN_I_OVS___S 16 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV__D_ADC_RN_Q_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV__D_ADC_RN_Q_OVS___S 14 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV__D_ADC_EN_DWA_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV__D_ADC_EN_DWA_OVS___S 12 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV__D_ADC_IC_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV__D_ADC_IC_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV__D_ADC_IR_EN_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV__D_ADC_IR_EN_OVS___S 8 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV___M 0x0003FF00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_RX_OV___S 8 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_SPARE_0 (0x005DEE98) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_SPARE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_SPARE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_SPARE_0__SPARE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_SPARE_0__SPARE_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_SPARE_0__SPARE_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_SPARE_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_SPARE_0___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_SPARE_1 (0x005DEE9C) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_SPARE_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_SPARE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_SPARE_1__SPARE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_SPARE_1__SPARE_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_SPARE_1__SPARE_1___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_SPARE_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_SPARE_1___S 0 + +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TEST_MODE (0x005DEEA0) +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TEST_MODE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TEST_MODE___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TEST_MODE__DTOP_TEST_MUX_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TEST_MODE__DTOP_TEST_MUX_SEL___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TEST_MODE__DTOP_TEST_MUX_SEL___S 0 +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TEST_MODE___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_RXBB_CH1_TEST_MODE___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0 (0x005DF000) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0___POR 0x04280E87 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXFE_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXRF_AGC_PKDET_OUT_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXRF_AGC_PKDET_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_LNA_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXRF_GM_IPT_EN___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXRF_GM_IC_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXFE_GM_ISEL___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_LNA_IC_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_LNA_IRTT_EN___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXRF_RXLO_ATB___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_RFPKDET_VREFNG___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IOFFSET_CTRL___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_LNA_OTA_BIAS_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_LNA_BIAS_OTA_SHORTR___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_SEL_2GNOTCH_TUNE___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IC_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IPT_CTRL___POR 0x7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXFE_ATB_SEL___M 0x80000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXFE_ATB_SEL___S 31 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXRF_AGC_PKDET_OUT_ATB_SEL___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXRF_AGC_PKDET_OUT_ATB_SEL___S 29 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXRF_AGC_PKDET_ATB_SEL___M 0x10000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXRF_AGC_PKDET_ATB_SEL___S 28 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_LNA_ATB_SEL___M 0x08000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_LNA_ATB_SEL___S 27 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXRF_GM_IPT_EN___M 0x04000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXRF_GM_IPT_EN___S 26 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXRF_GM_IC_EN___M 0x00400000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXRF_GM_IC_EN___S 22 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXFE_GM_ISEL___M 0x00200000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXFE_GM_ISEL___S 21 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_LNA_IC_EN___M 0x00100000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_LNA_IC_EN___S 20 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_LNA_IRTT_EN___M 0x00080000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_LNA_IRTT_EN___S 19 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXRF_RXLO_ATB___M 0x00070000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_BT_RXRF_RXLO_ATB___S 16 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_RFPKDET_VREFNG___M 0x0000C000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_RFPKDET_VREFNG___S 14 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IOFFSET_CTRL___M 0x00003800 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IOFFSET_CTRL___S 11 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_LNA_OTA_BIAS_CTRL___M 0x00000600 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_LNA_OTA_BIAS_CTRL___S 9 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_LNA_BIAS_OTA_SHORTR___M 0x00000100 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_LNA_BIAS_OTA_SHORTR___S 8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_SEL_2GNOTCH_TUNE___M 0x000000C0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_SEL_2GNOTCH_TUNE___S 6 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IC_CTRL___M 0x00000038 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IC_CTRL___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IPT_CTRL___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IPT_CTRL___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0___M 0xBC7FFFFF +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_0___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1 (0x005DF004) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1___POR 0x00C30006 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_RXLO_NAND_DUCY_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_MIXER_IR_EN___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_MXR_VCM___POR 0x4 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_RXLO_MXRDRV___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_RXLO_I_DELAY___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_RXLO_Q_DELAY___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__BT_LNA_LOAD_C___POR 0x6 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_RXLO_NAND_DUCY_CTRL___M 0x03000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_RXLO_NAND_DUCY_CTRL___S 24 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_MIXER_IR_EN___M 0x00800000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_MIXER_IR_EN___S 23 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_MXR_VCM___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_MXR_VCM___S 20 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_RXLO_MXRDRV___M 0x00070000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_RXLO_MXRDRV___S 16 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_RXLO_I_DELAY___M 0x00000700 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_RXLO_I_DELAY___S 8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_RXLO_Q_DELAY___M 0x00000070 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__D_BT_RXRF_RXLO_Q_DELAY___S 4 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__BT_LNA_LOAD_C___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1__BT_LNA_LOAD_C___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1___M 0x03F70777 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_STATIC_1___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_0 (0x005DF008) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_0__AGC_CAL_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_0__AGC_CAL_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_0__AGC_CAL_EN___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_0___M 0x00000001 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_0___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_1 (0x005DF00C) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_1__RO_PKDET0_DCOC___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_1__RO_AGC_CAL_SAT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_1__RO_AGC_CAL_VALID___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_1__RO_PKDET0_DCOC___M 0x0001FC00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_1__RO_PKDET0_DCOC___S 10 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_1__RO_AGC_CAL_SAT___M 0x00000002 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_1__RO_AGC_CAL_SAT___S 1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_1__RO_AGC_CAL_VALID___M 0x00000001 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_1__RO_AGC_CAL_VALID___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_1___M 0x0001FC03 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_1___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0 (0x005DF010) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_SHRD_AGC_PKDET_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_SHRD_CALRTX_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_SHRD_WL_AGC_PKDET_COMP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_GM_INPUT_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_MXR_I_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_MXR_Q_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_RXLO_I_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_RXLO_Q_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_GM_CAS_LOAD_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_GM_BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_SHRD_LNA_FASTCH_BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_AGC_PKDET_COMP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_SHRD_AGC_PKDET_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_SHRD_AGC_PKDET_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_SHRD_CALRTX_EN___M 0x00400000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_SHRD_CALRTX_EN___S 22 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_SHRD_WL_AGC_PKDET_COMP_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_SHRD_WL_AGC_PKDET_COMP_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_GM_INPUT_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_GM_INPUT_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_MXR_I_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_MXR_I_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_MXR_Q_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_MXR_Q_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_RXLO_I_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_RXLO_I_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_RXLO_Q_EN_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_RXLO_Q_EN_OVS___S 8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_GM_CAS_LOAD_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_GM_CAS_LOAD_OVS___S 6 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_GM_BIAS_EN_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_GM_BIAS_EN_OVS___S 4 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_SHRD_LNA_FASTCH_BIAS_EN_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_SHRD_LNA_FASTCH_BIAS_EN_OVS___S 2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_AGC_PKDET_COMP_EN_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0__D_BT_RXRF_AGC_PKDET_COMP_EN_OVS___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0___M 0xC07CFFFF +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RX_EN_OV_0___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0 (0x005DF014) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_MAINI_VREF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_BIAS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_BIAS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_BYPS_HG_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_OTA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_RMATCH_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_RMATCH_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_AUX_CAP_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_AUX_CAP_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_MAINI_VREF_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_MAINI_VREF_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_BIAS_OV___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_BIAS_OV___S 29 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_BIAS_OVD___M 0x1E000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_BIAS_OVD___S 25 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_BYPS_HG_OVS___M 0x01800000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_BYPS_HG_OVS___S 23 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_OTA_EN_OVS___M 0x00600000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_OTA_EN_OVS___S 21 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_GAIN_OV___M 0x00004000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_GAIN_OV___S 14 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_GAIN_OVD___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_GAIN_OVD___S 8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_RMATCH_OV___M 0x00000040 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_RMATCH_OV___S 6 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_RMATCH_OVD___M 0x00000038 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_RMATCH_OVD___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_AUX_CAP_OV___M 0x00000004 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_AUX_CAP_OV___S 2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_AUX_CAP_OVD___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0__D_SHRD_LNA_AUX_CAP_OVD___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0___M 0xFFE07F7F +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_0___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_1 (0x005DF018) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_1__D_SHRD_LNA_LOAD_R_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_1__D_SHRD_LNA_LOAD_R_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_1__D_SHRD_LNA_LOAD_R_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_1__D_SHRD_LNA_LOAD_R_OV___S 27 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_1__D_SHRD_LNA_LOAD_R_OVD___M 0x07000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_1__D_SHRD_LNA_LOAD_R_OVD___S 24 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_1___M 0x0F000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_1___S 24 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_3 (0x005DF01C) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_3__D_SHRD_LNA_GAINA_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_3__D_SHRD_LNA_GAINA_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_3__D_SHRD_LNA_MAIN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_3__D_SHRD_LNA_AUX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_3__D_SHRD_LNA_GAINA_OV___M 0x00080000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_3__D_SHRD_LNA_GAINA_OV___S 19 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_3__D_SHRD_LNA_GAINA_OVD___M 0x00078000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_3__D_SHRD_LNA_GAINA_OVD___S 15 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_3__D_SHRD_LNA_MAIN_EN_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_3__D_SHRD_LNA_MAIN_EN_OVS___S 6 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_3__D_SHRD_LNA_AUX_EN_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_3__D_SHRD_LNA_AUX_EN_OVS___S 4 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_3___M 0x000F80F0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_LNA_OV_3___S 4 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV (0x005DF020) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GM_IBIAS_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GM_IBIAS_CTRL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GMCAS_CGAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GMCAS_CGAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GM_FGAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GM_FGAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GM_IBIAS_CTRL_OV___M 0x04000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GM_IBIAS_CTRL_OV___S 26 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GM_IBIAS_CTRL_OVD___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GM_IBIAS_CTRL_OVD___S 23 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OV___M 0x00400000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OV___S 22 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OVD___M 0x00300000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OVD___S 20 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GMCAS_CGAIN_OV___M 0x00004000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GMCAS_CGAIN_OV___S 14 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GMCAS_CGAIN_OVD___M 0x00003000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GMCAS_CGAIN_OVD___S 12 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GM_FGAIN_OV___M 0x00000800 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GM_FGAIN_OV___S 11 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GM_FGAIN_OVD___M 0x00000700 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV__D_BT_RXRF_GM_FGAIN_OVD___S 8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV___M 0x07F07F00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_GM_OV___S 8 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_SPARE_0 (0x005DF024) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_SPARE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_SPARE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_SPARE_0__SPARE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_SPARE_0__SPARE_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_SPARE_0__SPARE_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_SPARE_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_SPARE_0___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_SPARE_1 (0x005DF028) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_SPARE_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_SPARE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_SPARE_1__SPARE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_SPARE_1__SPARE_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_SPARE_1__SPARE_1___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_SPARE_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_SPARE_1___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_TEST_MODE (0x005DF02C) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_TEST_MODE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_TEST_MODE___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_TEST_MODE__DTOP_TEST_MUX_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_TEST_MODE__DTOP_TEST_MUX_SEL___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_TEST_MODE__DTOP_TEST_MUX_SEL___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_TEST_MODE___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_TEST_MODE___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0 (0x005DF030) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0___POR 0x00004444 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_3___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_2___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_1___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_0___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_3___M 0x0000C000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_3___S 14 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_3___M 0x00003000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_3___S 12 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_2___M 0x00000C00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_2___S 10 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_2___M 0x00000300 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_2___S 8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_1___M 0x000000C0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_1___S 6 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_1___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_1___S 4 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_0___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_0___S 2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_0___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0___M 0x0000FFFF +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_0___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1 (0x005DF034) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1___POR 0x80808080 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_3___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_3___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_2___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_2___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_1___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_0___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_3___M 0x80000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_3___S 31 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_3___M 0x7F000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_2___M 0x00800000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_2___S 23 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_2___M 0x007F0000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_1___M 0x00008000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_1___S 15 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_1___M 0x00007F00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_0___M 0x00000080 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_0___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_0___M 0x0000007F +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_WL_AGC_PDET_LUT_1___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV (0x005DF038) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_SHRD_AGC_PKDET_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_SHRD_AGC_PKDET_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_SHRD_AGC_PKDET_DCOC_RANGE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_SHRD_AGC_PKDET_DCOC_RANGE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_BT_RXRF_AGC_PKDET_BW_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_BT_RXRF_AGC_CALTH_CTR_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_BT_RXRF_AGC_CALTH_CTR_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_SHRD_AGC_PKDET_GAIN_OV___M 0x00008000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_SHRD_AGC_PKDET_GAIN_OV___S 15 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_SHRD_AGC_PKDET_GAIN_OVD___M 0x00006000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_SHRD_AGC_PKDET_GAIN_OVD___S 13 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_SHRD_AGC_PKDET_DCOC_RANGE_OV___M 0x00001000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_SHRD_AGC_PKDET_DCOC_RANGE_OV___S 12 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_SHRD_AGC_PKDET_DCOC_RANGE_OVD___M 0x00000C00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_SHRD_AGC_PKDET_DCOC_RANGE_OVD___S 10 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_BT_RXRF_AGC_PKDET_BW_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_BT_RXRF_AGC_PKDET_BW_OVS___S 8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_BT_RXRF_AGC_CALTH_CTR_OV___M 0x00000080 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_BT_RXRF_AGC_CALTH_CTR_OV___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_BT_RXRF_AGC_CALTH_CTR_OVD___M 0x0000007F +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV__D_BT_RXRF_AGC_CALTH_CTR_OVD___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV___M 0x0000FFFF +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_PKDET_OV___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_2 (0x005DF03C) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_2__AGC_CAL_SETT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_2__AGC_CAL_SETT___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_2__AGC_CAL_SETT___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_2___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_AGC_CAL_2___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG (0x005DF040) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG___POR 0x000E0308 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__FAST_CHARGE_EN___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__CHARGE_AT_START___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__CHARGE_AT_GAIN_CHANGE___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__USE_LONG_PERIOD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__LNA_FC_PRD_LONG___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__LNA_FC_PRD_SHORT___POR 0x8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__FAST_CHARGE_EN___M 0x00080000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__FAST_CHARGE_EN___S 19 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__CHARGE_AT_START___M 0x00040000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__CHARGE_AT_START___S 18 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__CHARGE_AT_GAIN_CHANGE___M 0x00020000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__CHARGE_AT_GAIN_CHANGE___S 17 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__USE_LONG_PERIOD___M 0x00010000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__USE_LONG_PERIOD___S 16 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__LNA_FC_PRD_LONG___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__LNA_FC_PRD_LONG___S 8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__LNA_FC_PRD_SHORT___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG__LNA_FC_PRD_SHORT___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG___M 0x000F0F0F +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_FAST_CHARGE_CFG___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LUT_IDX_SEL (0x005DF044) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LUT_IDX_SEL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LUT_IDX_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LUT_IDX_SEL__LNA_GAIN_GATED_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LUT_IDX_SEL__LNA_GAIN_GATED_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LUT_IDX_SEL__GM_GAIN_GATED_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LUT_IDX_SEL__GM_GAIN_GATED_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LUT_IDX_SEL__LNA_GAIN_GATED_OV___M 0x00000080 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LUT_IDX_SEL__LNA_GAIN_GATED_OV___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LUT_IDX_SEL__LNA_GAIN_GATED_OVD___M 0x00000070 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LUT_IDX_SEL__LNA_GAIN_GATED_OVD___S 4 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LUT_IDX_SEL__GM_GAIN_GATED_OV___M 0x00000008 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LUT_IDX_SEL__GM_GAIN_GATED_OV___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LUT_IDX_SEL__GM_GAIN_GATED_OVD___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LUT_IDX_SEL__GM_GAIN_GATED_OVD___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LUT_IDX_SEL___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LUT_IDX_SEL___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RO_RXFE_LUT_IDX_SEL (0x005DF048) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RO_RXFE_LUT_IDX_SEL___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RO_RXFE_LUT_IDX_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN_GATED___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN_GATED___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN_GATED___M 0x00000070 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN_GATED___S 4 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN_GATED___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN_GATED___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RO_RXFE_LUT_IDX_SEL___M 0x00000077 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_RO_RXFE_LUT_IDX_SEL___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0 (0x005DF04C) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0___POR 0x40666401 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_RMATCH_0___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_GAINA_0___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_LOAD_R_0___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_OTA_EN_0___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_BIAS_0___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_AUX_CAP_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__BYPS_HG_0___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_MAINI_VREF_EN_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_MAIN_EN_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_AUX_EN_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_SH_GAIN_0___POR 0x01 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_RMATCH_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_RMATCH_0___S 29 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_GAINA_0___M 0x01E00000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_GAINA_0___S 21 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_LOAD_R_0___M 0x001C0000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_LOAD_R_0___S 18 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_OTA_EN_0___M 0x00020000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_OTA_EN_0___S 17 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_BIAS_0___M 0x0001E000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_BIAS_0___S 13 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_AUX_CAP_0___M 0x00001800 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_AUX_CAP_0___S 11 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__BYPS_HG_0___M 0x00000400 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__BYPS_HG_0___S 10 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_MAINI_VREF_EN_0___M 0x00000200 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_MAINI_VREF_EN_0___S 9 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_MAIN_EN_0___M 0x00000100 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_MAIN_EN_0___S 8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_AUX_EN_0___M 0x00000080 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_AUX_EN_0___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_SH_GAIN_0___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0__LNA_SH_GAIN_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_0___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1 (0x005DF050) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1___POR 0x40A26401 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_RMATCH_1___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_GAINA_1___POR 0x5 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_LOAD_R_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_OTA_EN_1___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_BIAS_1___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_AUX_CAP_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__BYPS_HG_1___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_MAINI_VREF_EN_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_MAIN_EN_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_AUX_EN_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_SH_GAIN_1___POR 0x01 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_RMATCH_1___M 0xE0000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_RMATCH_1___S 29 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_GAINA_1___M 0x01E00000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_GAINA_1___S 21 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_LOAD_R_1___M 0x001C0000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_LOAD_R_1___S 18 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_OTA_EN_1___M 0x00020000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_OTA_EN_1___S 17 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_BIAS_1___M 0x0001E000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_BIAS_1___S 13 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_AUX_CAP_1___M 0x00001800 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_AUX_CAP_1___S 11 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__BYPS_HG_1___M 0x00000400 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__BYPS_HG_1___S 10 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_MAINI_VREF_EN_1___M 0x00000200 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_MAINI_VREF_EN_1___S 9 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_MAIN_EN_1___M 0x00000100 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_MAIN_EN_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_AUX_EN_1___M 0x00000080 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_AUX_EN_1___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_SH_GAIN_1___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1__LNA_SH_GAIN_1___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_1___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2 (0x005DF054) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2___POR 0x41628501 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_RMATCH_2___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_GAINA_2___POR 0xB +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_LOAD_R_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_OTA_EN_2___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_BIAS_2___POR 0x4 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_AUX_CAP_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__BYPS_HG_2___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_MAINI_VREF_EN_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_MAIN_EN_2___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_AUX_EN_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_SH_GAIN_2___POR 0x01 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_RMATCH_2___M 0xE0000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_RMATCH_2___S 29 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_GAINA_2___M 0x01E00000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_GAINA_2___S 21 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_LOAD_R_2___M 0x001C0000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_LOAD_R_2___S 18 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_OTA_EN_2___M 0x00020000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_OTA_EN_2___S 17 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_BIAS_2___M 0x0001E000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_BIAS_2___S 13 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_AUX_CAP_2___M 0x00001800 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_AUX_CAP_2___S 11 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__BYPS_HG_2___M 0x00000400 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__BYPS_HG_2___S 10 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_MAINI_VREF_EN_2___M 0x00000200 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_MAINI_VREF_EN_2___S 9 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_MAIN_EN_2___M 0x00000100 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_MAIN_EN_2___S 8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_AUX_EN_2___M 0x00000080 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_AUX_EN_2___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_SH_GAIN_2___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2__LNA_SH_GAIN_2___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_2___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3 (0x005DF058) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3___POR 0x0002A380 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_RMATCH_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_GAINA_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_LOAD_R_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_OTA_EN_3___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_BIAS_3___POR 0x5 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_AUX_CAP_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__BYPS_HG_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_MAINI_VREF_EN_3___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_MAIN_EN_3___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_AUX_EN_3___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_SH_GAIN_3___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_RMATCH_3___M 0xE0000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_RMATCH_3___S 29 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_GAINA_3___M 0x01E00000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_GAINA_3___S 21 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_LOAD_R_3___M 0x001C0000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_LOAD_R_3___S 18 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_OTA_EN_3___M 0x00020000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_OTA_EN_3___S 17 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_BIAS_3___M 0x0001E000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_BIAS_3___S 13 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_AUX_CAP_3___M 0x00001800 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_AUX_CAP_3___S 11 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__BYPS_HG_3___M 0x00000400 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__BYPS_HG_3___S 10 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_MAINI_VREF_EN_3___M 0x00000200 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_MAINI_VREF_EN_3___S 9 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_MAIN_EN_3___M 0x00000100 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_MAIN_EN_3___S 8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_AUX_EN_3___M 0x00000080 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_AUX_EN_3___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_SH_GAIN_3___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3__LNA_SH_GAIN_3___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_3___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4 (0x005DF05C) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4___POR 0x001E4380 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_RMATCH_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_GAINA_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_LOAD_R_4___POR 0x7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_OTA_EN_4___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_BIAS_4___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_AUX_CAP_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__BYPS_HG_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_MAINI_VREF_EN_4___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_MAIN_EN_4___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_AUX_EN_4___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_SH_GAIN_4___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_RMATCH_4___M 0xE0000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_RMATCH_4___S 29 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_GAINA_4___M 0x01E00000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_GAINA_4___S 21 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_LOAD_R_4___M 0x001C0000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_LOAD_R_4___S 18 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_OTA_EN_4___M 0x00020000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_OTA_EN_4___S 17 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_BIAS_4___M 0x0001E000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_BIAS_4___S 13 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_AUX_CAP_4___M 0x00001800 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_AUX_CAP_4___S 11 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__BYPS_HG_4___M 0x00000400 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__BYPS_HG_4___S 10 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_MAINI_VREF_EN_4___M 0x00000200 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_MAINI_VREF_EN_4___S 9 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_MAIN_EN_4___M 0x00000100 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_MAIN_EN_4___S 8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_AUX_EN_4___M 0x00000080 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_AUX_EN_4___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_SH_GAIN_4___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4__LNA_SH_GAIN_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_4___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5 (0x005DF060) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5___POR 0x001E0380 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_RMATCH_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_GAINA_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_LOAD_R_5___POR 0x7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_OTA_EN_5___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_BIAS_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_AUX_CAP_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__BYPS_HG_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_MAINI_VREF_EN_5___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_MAIN_EN_5___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_AUX_EN_5___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_SH_GAIN_5___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_RMATCH_5___M 0xE0000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_RMATCH_5___S 29 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_GAINA_5___M 0x01E00000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_GAINA_5___S 21 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_LOAD_R_5___M 0x001C0000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_LOAD_R_5___S 18 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_OTA_EN_5___M 0x00020000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_OTA_EN_5___S 17 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_BIAS_5___M 0x0001E000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_BIAS_5___S 13 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_AUX_CAP_5___M 0x00001800 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_AUX_CAP_5___S 11 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__BYPS_HG_5___M 0x00000400 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__BYPS_HG_5___S 10 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_MAINI_VREF_EN_5___M 0x00000200 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_MAINI_VREF_EN_5___S 9 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_MAIN_EN_5___M 0x00000100 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_MAIN_EN_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_AUX_EN_5___M 0x00000080 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_AUX_EN_5___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_SH_GAIN_5___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5__LNA_SH_GAIN_5___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_5___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6 (0x005DF064) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6___POR 0x00020380 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_RMATCH_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_GAINA_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_LOAD_R_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_OTA_EN_6___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_BIAS_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_AUX_CAP_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__BYPS_HG_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_MAINI_VREF_EN_6___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_MAIN_EN_6___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_AUX_EN_6___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_SH_GAIN_6___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_RMATCH_6___M 0xE0000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_RMATCH_6___S 29 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_GAINA_6___M 0x01E00000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_GAINA_6___S 21 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_LOAD_R_6___M 0x001C0000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_LOAD_R_6___S 18 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_OTA_EN_6___M 0x00020000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_OTA_EN_6___S 17 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_BIAS_6___M 0x0001E000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_BIAS_6___S 13 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_AUX_CAP_6___M 0x00001800 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_AUX_CAP_6___S 11 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__BYPS_HG_6___M 0x00000400 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__BYPS_HG_6___S 10 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_MAINI_VREF_EN_6___M 0x00000200 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_MAINI_VREF_EN_6___S 9 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_MAIN_EN_6___M 0x00000100 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_MAIN_EN_6___S 8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_AUX_EN_6___M 0x00000080 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_AUX_EN_6___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_SH_GAIN_6___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6__LNA_SH_GAIN_6___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_6___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7 (0x005DF068) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7___POR 0x00026380 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_RMATCH_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_GAINA_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_LOAD_R_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_OTA_EN_7___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_BIAS_7___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_AUX_CAP_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__BYPS_HG_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_MAINI_VREF_EN_7___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_MAIN_EN_7___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_AUX_EN_7___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_SH_GAIN_7___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_RMATCH_7___M 0xE0000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_RMATCH_7___S 29 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_GAINA_7___M 0x01E00000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_GAINA_7___S 21 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_LOAD_R_7___M 0x001C0000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_LOAD_R_7___S 18 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_OTA_EN_7___M 0x00020000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_OTA_EN_7___S 17 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_BIAS_7___M 0x0001E000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_BIAS_7___S 13 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_AUX_CAP_7___M 0x00001800 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_AUX_CAP_7___S 11 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__BYPS_HG_7___M 0x00000400 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__BYPS_HG_7___S 10 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_MAINI_VREF_EN_7___M 0x00000200 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_MAINI_VREF_EN_7___S 9 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_MAIN_EN_7___M 0x00000100 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_MAIN_EN_7___S 8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_AUX_EN_7___M 0x00000080 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_AUX_EN_7___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_SH_GAIN_7___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7__LNA_SH_GAIN_7___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_LNA_0_7___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0 (0x005DF06C) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0___POR 0x00000001 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GM_FGAIN0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GMCAS_CGAIN0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GM_COARSE_GAIN0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GM_IBIAS_CTRL0___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GM_FGAIN0___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GM_FGAIN0___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GMCAS_CGAIN0___M 0x00000060 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GMCAS_CGAIN0___S 5 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GM_COARSE_GAIN0___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GM_COARSE_GAIN0___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GM_IBIAS_CTRL0___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0__GM_IBIAS_CTRL0___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_0___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1 (0x005DF070) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1___POR 0x00000082 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GM_FGAIN1___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GMCAS_CGAIN1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GM_COARSE_GAIN1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GM_IBIAS_CTRL1___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GM_FGAIN1___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GM_FGAIN1___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GMCAS_CGAIN1___M 0x00000060 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GMCAS_CGAIN1___S 5 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GM_COARSE_GAIN1___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GM_COARSE_GAIN1___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GM_IBIAS_CTRL1___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1__GM_IBIAS_CTRL1___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_1___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2 (0x005DF074) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2___POR 0x00000103 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GM_FGAIN2___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GMCAS_CGAIN2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GM_COARSE_GAIN2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GM_IBIAS_CTRL2___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GM_FGAIN2___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GM_FGAIN2___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GMCAS_CGAIN2___M 0x00000060 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GMCAS_CGAIN2___S 5 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GM_COARSE_GAIN2___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GM_COARSE_GAIN2___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GM_IBIAS_CTRL2___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2__GM_IBIAS_CTRL2___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_2___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3 (0x005DF078) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3___POR 0x000000D3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GM_FGAIN3___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GMCAS_CGAIN3___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GM_COARSE_GAIN3___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GM_IBIAS_CTRL3___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GM_FGAIN3___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GM_FGAIN3___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GMCAS_CGAIN3___M 0x00000060 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GMCAS_CGAIN3___S 5 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GM_COARSE_GAIN3___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GM_COARSE_GAIN3___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GM_IBIAS_CTRL3___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3__GM_IBIAS_CTRL3___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_3___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4 (0x005DF07C) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4___POR 0x00000153 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GM_FGAIN4___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GMCAS_CGAIN4___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GM_COARSE_GAIN4___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GM_IBIAS_CTRL4___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GM_FGAIN4___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GM_FGAIN4___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GMCAS_CGAIN4___M 0x00000060 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GMCAS_CGAIN4___S 5 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GM_COARSE_GAIN4___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GM_COARSE_GAIN4___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GM_IBIAS_CTRL4___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4__GM_IBIAS_CTRL4___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_4___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5 (0x005DF080) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5___POR 0x0000022B +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GM_FGAIN5___POR 0x4 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GMCAS_CGAIN5___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GM_COARSE_GAIN5___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GM_IBIAS_CTRL5___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GM_FGAIN5___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GM_FGAIN5___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GMCAS_CGAIN5___M 0x00000060 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GMCAS_CGAIN5___S 5 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GM_COARSE_GAIN5___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GM_COARSE_GAIN5___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GM_IBIAS_CTRL5___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5__GM_IBIAS_CTRL5___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_5___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6 (0x005DF084) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6___POR 0x0000027C +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GM_FGAIN6___POR 0x4 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GMCAS_CGAIN6___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GM_COARSE_GAIN6___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GM_IBIAS_CTRL6___POR 0x4 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GM_FGAIN6___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GM_FGAIN6___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GMCAS_CGAIN6___M 0x00000060 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GMCAS_CGAIN6___S 5 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GM_COARSE_GAIN6___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GM_COARSE_GAIN6___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GM_IBIAS_CTRL6___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6__GM_IBIAS_CTRL6___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_6___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7 (0x005DF088) +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7___POR 0x00000354 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GM_FGAIN7___POR 0x6 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GMCAS_CGAIN7___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GM_COARSE_GAIN7___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GM_IBIAS_CTRL7___POR 0x4 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GM_FGAIN7___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GM_FGAIN7___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GMCAS_CGAIN7___M 0x00000060 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GMCAS_CGAIN7___S 5 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GM_COARSE_GAIN7___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GM_COARSE_GAIN7___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GM_IBIAS_CTRL7___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7__GM_IBIAS_CTRL7___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_RXFE_CH0_BT_RXFE_GM_0_7___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0 (0x005DF200) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0___POR 0x04280E87 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXFE_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXRF_AGC_PKDET_OUT_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXRF_AGC_PKDET_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_LNA_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXRF_GM_IPT_EN___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXRF_GM_IC_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXFE_GM_ISEL___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_LNA_IC_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_LNA_IRTT_EN___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXRF_RXLO_ATB___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_RFPKDET_VREFNG___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IOFFSET_CTRL___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_LNA_OTA_BIAS_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_LNA_BIAS_OTA_SHORTR___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_SEL_2GNOTCH_TUNE___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IC_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IPT_CTRL___POR 0x7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXFE_ATB_SEL___M 0x80000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXFE_ATB_SEL___S 31 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXRF_AGC_PKDET_OUT_ATB_SEL___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXRF_AGC_PKDET_OUT_ATB_SEL___S 29 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXRF_AGC_PKDET_ATB_SEL___M 0x10000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXRF_AGC_PKDET_ATB_SEL___S 28 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_LNA_ATB_SEL___M 0x08000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_LNA_ATB_SEL___S 27 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXRF_GM_IPT_EN___M 0x04000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXRF_GM_IPT_EN___S 26 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXRF_GM_IC_EN___M 0x00400000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXRF_GM_IC_EN___S 22 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXFE_GM_ISEL___M 0x00200000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXFE_GM_ISEL___S 21 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_LNA_IC_EN___M 0x00100000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_LNA_IC_EN___S 20 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_LNA_IRTT_EN___M 0x00080000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_LNA_IRTT_EN___S 19 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXRF_RXLO_ATB___M 0x00070000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_BT_RXRF_RXLO_ATB___S 16 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_RFPKDET_VREFNG___M 0x0000C000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_RFPKDET_VREFNG___S 14 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IOFFSET_CTRL___M 0x00003800 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IOFFSET_CTRL___S 11 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_LNA_OTA_BIAS_CTRL___M 0x00000600 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_LNA_OTA_BIAS_CTRL___S 9 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_LNA_BIAS_OTA_SHORTR___M 0x00000100 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_LNA_BIAS_OTA_SHORTR___S 8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_SEL_2GNOTCH_TUNE___M 0x000000C0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_SEL_2GNOTCH_TUNE___S 6 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IC_CTRL___M 0x00000038 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IC_CTRL___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IPT_CTRL___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0__D_SHRD_WLRXFE2_RTT_IPT_CTRL___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0___M 0xBC7FFFFF +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_0___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1 (0x005DF204) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1___POR 0x00C30006 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_RXLO_NAND_DUCY_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_MIXER_IR_EN___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_MXR_VCM___POR 0x4 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_RXLO_MXRDRV___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_RXLO_I_DELAY___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_RXLO_Q_DELAY___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__BT_LNA_LOAD_C___POR 0x6 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_RXLO_NAND_DUCY_CTRL___M 0x03000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_RXLO_NAND_DUCY_CTRL___S 24 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_MIXER_IR_EN___M 0x00800000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_MIXER_IR_EN___S 23 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_MXR_VCM___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_MXR_VCM___S 20 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_RXLO_MXRDRV___M 0x00070000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_RXLO_MXRDRV___S 16 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_RXLO_I_DELAY___M 0x00000700 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_RXLO_I_DELAY___S 8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_RXLO_Q_DELAY___M 0x00000070 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__D_BT_RXRF_RXLO_Q_DELAY___S 4 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__BT_LNA_LOAD_C___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1__BT_LNA_LOAD_C___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1___M 0x03F70777 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_STATIC_1___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_0 (0x005DF208) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_0__AGC_CAL_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_0__AGC_CAL_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_0__AGC_CAL_EN___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_0___M 0x00000001 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_0___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_1 (0x005DF20C) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_1__RO_PKDET0_DCOC___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_1__RO_AGC_CAL_SAT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_1__RO_AGC_CAL_VALID___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_1__RO_PKDET0_DCOC___M 0x0001FC00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_1__RO_PKDET0_DCOC___S 10 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_1__RO_AGC_CAL_SAT___M 0x00000002 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_1__RO_AGC_CAL_SAT___S 1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_1__RO_AGC_CAL_VALID___M 0x00000001 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_1__RO_AGC_CAL_VALID___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_1___M 0x0001FC03 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_1___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0 (0x005DF210) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_SHRD_AGC_PKDET_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_SHRD_CALRTX_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_SHRD_WL_AGC_PKDET_COMP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_GM_INPUT_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_MXR_I_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_MXR_Q_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_RXLO_I_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_RXLO_Q_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_GM_CAS_LOAD_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_GM_BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_SHRD_LNA_FASTCH_BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_AGC_PKDET_COMP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_SHRD_AGC_PKDET_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_SHRD_AGC_PKDET_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_SHRD_CALRTX_EN___M 0x00400000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_SHRD_CALRTX_EN___S 22 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_SHRD_WL_AGC_PKDET_COMP_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_SHRD_WL_AGC_PKDET_COMP_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_GM_INPUT_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_GM_INPUT_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_MXR_I_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_MXR_I_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_MXR_Q_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_MXR_Q_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_RXLO_I_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_RXLO_I_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_RXLO_Q_EN_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_RXLO_Q_EN_OVS___S 8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_GM_CAS_LOAD_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_GM_CAS_LOAD_OVS___S 6 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_GM_BIAS_EN_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_GM_BIAS_EN_OVS___S 4 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_SHRD_LNA_FASTCH_BIAS_EN_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_SHRD_LNA_FASTCH_BIAS_EN_OVS___S 2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_AGC_PKDET_COMP_EN_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0__D_BT_RXRF_AGC_PKDET_COMP_EN_OVS___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0___M 0xC07CFFFF +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RX_EN_OV_0___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0 (0x005DF214) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_MAINI_VREF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_BIAS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_BIAS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_BYPS_HG_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_OTA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_RMATCH_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_RMATCH_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_AUX_CAP_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_AUX_CAP_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_MAINI_VREF_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_MAINI_VREF_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_BIAS_OV___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_BIAS_OV___S 29 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_BIAS_OVD___M 0x1E000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_BIAS_OVD___S 25 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_BYPS_HG_OVS___M 0x01800000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_BYPS_HG_OVS___S 23 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_OTA_EN_OVS___M 0x00600000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_OTA_EN_OVS___S 21 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_GAIN_OV___M 0x00004000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_GAIN_OV___S 14 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_GAIN_OVD___M 0x00003F00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_GAIN_OVD___S 8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_RMATCH_OV___M 0x00000040 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_RMATCH_OV___S 6 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_RMATCH_OVD___M 0x00000038 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_RMATCH_OVD___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_AUX_CAP_OV___M 0x00000004 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_AUX_CAP_OV___S 2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_AUX_CAP_OVD___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0__D_SHRD_LNA_AUX_CAP_OVD___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0___M 0xFFE07F7F +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_0___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_1 (0x005DF218) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_1__D_SHRD_LNA_LOAD_R_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_1__D_SHRD_LNA_LOAD_R_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_1__D_SHRD_LNA_LOAD_R_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_1__D_SHRD_LNA_LOAD_R_OV___S 27 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_1__D_SHRD_LNA_LOAD_R_OVD___M 0x07000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_1__D_SHRD_LNA_LOAD_R_OVD___S 24 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_1___M 0x0F000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_1___S 24 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_3 (0x005DF21C) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_3__D_SHRD_LNA_GAINA_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_3__D_SHRD_LNA_GAINA_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_3__D_SHRD_LNA_MAIN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_3__D_SHRD_LNA_AUX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_3__D_SHRD_LNA_GAINA_OV___M 0x00080000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_3__D_SHRD_LNA_GAINA_OV___S 19 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_3__D_SHRD_LNA_GAINA_OVD___M 0x00078000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_3__D_SHRD_LNA_GAINA_OVD___S 15 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_3__D_SHRD_LNA_MAIN_EN_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_3__D_SHRD_LNA_MAIN_EN_OVS___S 6 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_3__D_SHRD_LNA_AUX_EN_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_3__D_SHRD_LNA_AUX_EN_OVS___S 4 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_3___M 0x000F80F0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_LNA_OV_3___S 4 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV (0x005DF220) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GM_IBIAS_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GM_IBIAS_CTRL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GMCAS_CGAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GMCAS_CGAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GM_FGAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GM_FGAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GM_IBIAS_CTRL_OV___M 0x04000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GM_IBIAS_CTRL_OV___S 26 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GM_IBIAS_CTRL_OVD___M 0x03800000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GM_IBIAS_CTRL_OVD___S 23 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OV___M 0x00400000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OV___S 22 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OVD___M 0x00300000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXFE_GM_COARSE_GAIN_OVD___S 20 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GMCAS_CGAIN_OV___M 0x00004000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GMCAS_CGAIN_OV___S 14 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GMCAS_CGAIN_OVD___M 0x00003000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GMCAS_CGAIN_OVD___S 12 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GM_FGAIN_OV___M 0x00000800 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GM_FGAIN_OV___S 11 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GM_FGAIN_OVD___M 0x00000700 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV__D_BT_RXRF_GM_FGAIN_OVD___S 8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV___M 0x07F07F00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_GM_OV___S 8 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_SPARE_0 (0x005DF224) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_SPARE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_SPARE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_SPARE_0__SPARE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_SPARE_0__SPARE_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_SPARE_0__SPARE_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_SPARE_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_SPARE_0___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_SPARE_1 (0x005DF228) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_SPARE_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_SPARE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_SPARE_1__SPARE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_SPARE_1__SPARE_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_SPARE_1__SPARE_1___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_SPARE_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_SPARE_1___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_TEST_MODE (0x005DF22C) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_TEST_MODE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_TEST_MODE___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_TEST_MODE__DTOP_TEST_MUX_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_TEST_MODE__DTOP_TEST_MUX_SEL___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_TEST_MODE__DTOP_TEST_MUX_SEL___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_TEST_MODE___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_TEST_MODE___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0 (0x005DF230) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0___POR 0x00004444 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_3___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_2___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_1___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_0___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_3___M 0x0000C000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_3___S 14 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_3___M 0x00003000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_3___S 12 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_2___M 0x00000C00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_2___S 10 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_2___M 0x00000300 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_2___S 8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_1___M 0x000000C0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_1___S 6 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_1___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_1___S 4 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_0___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_GAIN_0___S 2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_0___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0__D_SHRD_AGC_PKDET_DCOC_RANGE_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0___M 0x0000FFFF +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_0___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1 (0x005DF234) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1___POR 0x80808080 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_3___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_3___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_2___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_2___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_1___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_1___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_0___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_0___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_3___M 0x80000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_3___S 31 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_3___M 0x7F000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_3___S 24 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_2___M 0x00800000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_2___S 23 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_2___M 0x007F0000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_2___S 16 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_1___M 0x00008000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_1___S 15 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_1___M 0x00007F00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_0___M 0x00000080 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_PKDET_BW_0___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_0___M 0x0000007F +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1__D_BT_RXRF_AGC_CALTH_CTR_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_WL_AGC_PDET_LUT_1___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV (0x005DF238) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_SHRD_AGC_PKDET_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_SHRD_AGC_PKDET_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_SHRD_AGC_PKDET_DCOC_RANGE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_SHRD_AGC_PKDET_DCOC_RANGE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_BT_RXRF_AGC_PKDET_BW_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_BT_RXRF_AGC_CALTH_CTR_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_BT_RXRF_AGC_CALTH_CTR_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_SHRD_AGC_PKDET_GAIN_OV___M 0x00008000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_SHRD_AGC_PKDET_GAIN_OV___S 15 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_SHRD_AGC_PKDET_GAIN_OVD___M 0x00006000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_SHRD_AGC_PKDET_GAIN_OVD___S 13 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_SHRD_AGC_PKDET_DCOC_RANGE_OV___M 0x00001000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_SHRD_AGC_PKDET_DCOC_RANGE_OV___S 12 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_SHRD_AGC_PKDET_DCOC_RANGE_OVD___M 0x00000C00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_SHRD_AGC_PKDET_DCOC_RANGE_OVD___S 10 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_BT_RXRF_AGC_PKDET_BW_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_BT_RXRF_AGC_PKDET_BW_OVS___S 8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_BT_RXRF_AGC_CALTH_CTR_OV___M 0x00000080 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_BT_RXRF_AGC_CALTH_CTR_OV___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_BT_RXRF_AGC_CALTH_CTR_OVD___M 0x0000007F +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV__D_BT_RXRF_AGC_CALTH_CTR_OVD___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV___M 0x0000FFFF +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_PKDET_OV___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_2 (0x005DF23C) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_2__AGC_CAL_SETT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_2__AGC_CAL_SETT___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_2__AGC_CAL_SETT___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_2___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_AGC_CAL_2___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG (0x005DF240) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG___POR 0x000E0308 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__FAST_CHARGE_EN___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__CHARGE_AT_START___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__CHARGE_AT_GAIN_CHANGE___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__USE_LONG_PERIOD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__LNA_FC_PRD_LONG___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__LNA_FC_PRD_SHORT___POR 0x8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__FAST_CHARGE_EN___M 0x00080000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__FAST_CHARGE_EN___S 19 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__CHARGE_AT_START___M 0x00040000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__CHARGE_AT_START___S 18 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__CHARGE_AT_GAIN_CHANGE___M 0x00020000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__CHARGE_AT_GAIN_CHANGE___S 17 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__USE_LONG_PERIOD___M 0x00010000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__USE_LONG_PERIOD___S 16 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__LNA_FC_PRD_LONG___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__LNA_FC_PRD_LONG___S 8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__LNA_FC_PRD_SHORT___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG__LNA_FC_PRD_SHORT___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG___M 0x000F0F0F +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_FAST_CHARGE_CFG___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LUT_IDX_SEL (0x005DF244) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LUT_IDX_SEL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LUT_IDX_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LUT_IDX_SEL__LNA_GAIN_GATED_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LUT_IDX_SEL__LNA_GAIN_GATED_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LUT_IDX_SEL__GM_GAIN_GATED_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LUT_IDX_SEL__GM_GAIN_GATED_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LUT_IDX_SEL__LNA_GAIN_GATED_OV___M 0x00000080 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LUT_IDX_SEL__LNA_GAIN_GATED_OV___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LUT_IDX_SEL__LNA_GAIN_GATED_OVD___M 0x00000070 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LUT_IDX_SEL__LNA_GAIN_GATED_OVD___S 4 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LUT_IDX_SEL__GM_GAIN_GATED_OV___M 0x00000008 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LUT_IDX_SEL__GM_GAIN_GATED_OV___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LUT_IDX_SEL__GM_GAIN_GATED_OVD___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LUT_IDX_SEL__GM_GAIN_GATED_OVD___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LUT_IDX_SEL___M 0x000000FF +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LUT_IDX_SEL___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RO_RXFE_LUT_IDX_SEL (0x005DF248) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RO_RXFE_LUT_IDX_SEL___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RO_RXFE_LUT_IDX_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN_GATED___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN_GATED___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN_GATED___M 0x00000070 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN_GATED___S 4 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN_GATED___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN_GATED___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RO_RXFE_LUT_IDX_SEL___M 0x00000077 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_RO_RXFE_LUT_IDX_SEL___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0 (0x005DF24C) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0___POR 0x40666401 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_RMATCH_0___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_GAINA_0___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_LOAD_R_0___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_OTA_EN_0___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_BIAS_0___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_AUX_CAP_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__BYPS_HG_0___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_MAINI_VREF_EN_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_MAIN_EN_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_AUX_EN_0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_SH_GAIN_0___POR 0x01 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_RMATCH_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_RMATCH_0___S 29 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_GAINA_0___M 0x01E00000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_GAINA_0___S 21 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_LOAD_R_0___M 0x001C0000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_LOAD_R_0___S 18 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_OTA_EN_0___M 0x00020000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_OTA_EN_0___S 17 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_BIAS_0___M 0x0001E000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_BIAS_0___S 13 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_AUX_CAP_0___M 0x00001800 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_AUX_CAP_0___S 11 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__BYPS_HG_0___M 0x00000400 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__BYPS_HG_0___S 10 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_MAINI_VREF_EN_0___M 0x00000200 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_MAINI_VREF_EN_0___S 9 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_MAIN_EN_0___M 0x00000100 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_MAIN_EN_0___S 8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_AUX_EN_0___M 0x00000080 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_AUX_EN_0___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_SH_GAIN_0___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0__LNA_SH_GAIN_0___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_0___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1 (0x005DF250) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1___POR 0x40A26401 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_RMATCH_1___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_GAINA_1___POR 0x5 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_LOAD_R_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_OTA_EN_1___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_BIAS_1___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_AUX_CAP_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__BYPS_HG_1___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_MAINI_VREF_EN_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_MAIN_EN_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_AUX_EN_1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_SH_GAIN_1___POR 0x01 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_RMATCH_1___M 0xE0000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_RMATCH_1___S 29 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_GAINA_1___M 0x01E00000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_GAINA_1___S 21 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_LOAD_R_1___M 0x001C0000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_LOAD_R_1___S 18 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_OTA_EN_1___M 0x00020000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_OTA_EN_1___S 17 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_BIAS_1___M 0x0001E000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_BIAS_1___S 13 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_AUX_CAP_1___M 0x00001800 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_AUX_CAP_1___S 11 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__BYPS_HG_1___M 0x00000400 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__BYPS_HG_1___S 10 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_MAINI_VREF_EN_1___M 0x00000200 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_MAINI_VREF_EN_1___S 9 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_MAIN_EN_1___M 0x00000100 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_MAIN_EN_1___S 8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_AUX_EN_1___M 0x00000080 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_AUX_EN_1___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_SH_GAIN_1___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1__LNA_SH_GAIN_1___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_1___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2 (0x005DF254) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2___POR 0x41628501 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_RMATCH_2___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_GAINA_2___POR 0xB +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_LOAD_R_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_OTA_EN_2___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_BIAS_2___POR 0x4 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_AUX_CAP_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__BYPS_HG_2___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_MAINI_VREF_EN_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_MAIN_EN_2___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_AUX_EN_2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_SH_GAIN_2___POR 0x01 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_RMATCH_2___M 0xE0000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_RMATCH_2___S 29 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_GAINA_2___M 0x01E00000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_GAINA_2___S 21 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_LOAD_R_2___M 0x001C0000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_LOAD_R_2___S 18 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_OTA_EN_2___M 0x00020000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_OTA_EN_2___S 17 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_BIAS_2___M 0x0001E000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_BIAS_2___S 13 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_AUX_CAP_2___M 0x00001800 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_AUX_CAP_2___S 11 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__BYPS_HG_2___M 0x00000400 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__BYPS_HG_2___S 10 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_MAINI_VREF_EN_2___M 0x00000200 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_MAINI_VREF_EN_2___S 9 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_MAIN_EN_2___M 0x00000100 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_MAIN_EN_2___S 8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_AUX_EN_2___M 0x00000080 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_AUX_EN_2___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_SH_GAIN_2___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2__LNA_SH_GAIN_2___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_2___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3 (0x005DF258) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3___POR 0x0002A380 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_RMATCH_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_GAINA_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_LOAD_R_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_OTA_EN_3___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_BIAS_3___POR 0x5 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_AUX_CAP_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__BYPS_HG_3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_MAINI_VREF_EN_3___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_MAIN_EN_3___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_AUX_EN_3___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_SH_GAIN_3___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_RMATCH_3___M 0xE0000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_RMATCH_3___S 29 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_GAINA_3___M 0x01E00000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_GAINA_3___S 21 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_LOAD_R_3___M 0x001C0000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_LOAD_R_3___S 18 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_OTA_EN_3___M 0x00020000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_OTA_EN_3___S 17 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_BIAS_3___M 0x0001E000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_BIAS_3___S 13 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_AUX_CAP_3___M 0x00001800 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_AUX_CAP_3___S 11 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__BYPS_HG_3___M 0x00000400 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__BYPS_HG_3___S 10 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_MAINI_VREF_EN_3___M 0x00000200 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_MAINI_VREF_EN_3___S 9 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_MAIN_EN_3___M 0x00000100 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_MAIN_EN_3___S 8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_AUX_EN_3___M 0x00000080 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_AUX_EN_3___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_SH_GAIN_3___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3__LNA_SH_GAIN_3___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_3___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4 (0x005DF25C) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4___POR 0x001E4380 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_RMATCH_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_GAINA_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_LOAD_R_4___POR 0x7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_OTA_EN_4___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_BIAS_4___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_AUX_CAP_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__BYPS_HG_4___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_MAINI_VREF_EN_4___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_MAIN_EN_4___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_AUX_EN_4___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_SH_GAIN_4___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_RMATCH_4___M 0xE0000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_RMATCH_4___S 29 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_GAINA_4___M 0x01E00000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_GAINA_4___S 21 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_LOAD_R_4___M 0x001C0000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_LOAD_R_4___S 18 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_OTA_EN_4___M 0x00020000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_OTA_EN_4___S 17 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_BIAS_4___M 0x0001E000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_BIAS_4___S 13 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_AUX_CAP_4___M 0x00001800 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_AUX_CAP_4___S 11 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__BYPS_HG_4___M 0x00000400 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__BYPS_HG_4___S 10 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_MAINI_VREF_EN_4___M 0x00000200 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_MAINI_VREF_EN_4___S 9 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_MAIN_EN_4___M 0x00000100 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_MAIN_EN_4___S 8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_AUX_EN_4___M 0x00000080 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_AUX_EN_4___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_SH_GAIN_4___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4__LNA_SH_GAIN_4___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_4___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5 (0x005DF260) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5___POR 0x001E0380 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_RMATCH_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_GAINA_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_LOAD_R_5___POR 0x7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_OTA_EN_5___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_BIAS_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_AUX_CAP_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__BYPS_HG_5___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_MAINI_VREF_EN_5___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_MAIN_EN_5___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_AUX_EN_5___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_SH_GAIN_5___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_RMATCH_5___M 0xE0000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_RMATCH_5___S 29 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_GAINA_5___M 0x01E00000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_GAINA_5___S 21 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_LOAD_R_5___M 0x001C0000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_LOAD_R_5___S 18 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_OTA_EN_5___M 0x00020000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_OTA_EN_5___S 17 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_BIAS_5___M 0x0001E000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_BIAS_5___S 13 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_AUX_CAP_5___M 0x00001800 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_AUX_CAP_5___S 11 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__BYPS_HG_5___M 0x00000400 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__BYPS_HG_5___S 10 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_MAINI_VREF_EN_5___M 0x00000200 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_MAINI_VREF_EN_5___S 9 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_MAIN_EN_5___M 0x00000100 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_MAIN_EN_5___S 8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_AUX_EN_5___M 0x00000080 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_AUX_EN_5___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_SH_GAIN_5___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5__LNA_SH_GAIN_5___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_5___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6 (0x005DF264) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6___POR 0x00020380 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_RMATCH_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_GAINA_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_LOAD_R_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_OTA_EN_6___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_BIAS_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_AUX_CAP_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__BYPS_HG_6___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_MAINI_VREF_EN_6___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_MAIN_EN_6___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_AUX_EN_6___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_SH_GAIN_6___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_RMATCH_6___M 0xE0000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_RMATCH_6___S 29 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_GAINA_6___M 0x01E00000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_GAINA_6___S 21 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_LOAD_R_6___M 0x001C0000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_LOAD_R_6___S 18 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_OTA_EN_6___M 0x00020000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_OTA_EN_6___S 17 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_BIAS_6___M 0x0001E000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_BIAS_6___S 13 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_AUX_CAP_6___M 0x00001800 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_AUX_CAP_6___S 11 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__BYPS_HG_6___M 0x00000400 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__BYPS_HG_6___S 10 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_MAINI_VREF_EN_6___M 0x00000200 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_MAINI_VREF_EN_6___S 9 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_MAIN_EN_6___M 0x00000100 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_MAIN_EN_6___S 8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_AUX_EN_6___M 0x00000080 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_AUX_EN_6___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_SH_GAIN_6___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6__LNA_SH_GAIN_6___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_6___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7 (0x005DF268) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7___POR 0x00026380 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_RMATCH_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_GAINA_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_LOAD_R_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_OTA_EN_7___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_BIAS_7___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_AUX_CAP_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__BYPS_HG_7___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_MAINI_VREF_EN_7___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_MAIN_EN_7___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_AUX_EN_7___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_SH_GAIN_7___POR 0x00 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_RMATCH_7___M 0xE0000000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_RMATCH_7___S 29 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_GAINA_7___M 0x01E00000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_GAINA_7___S 21 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_LOAD_R_7___M 0x001C0000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_LOAD_R_7___S 18 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_OTA_EN_7___M 0x00020000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_OTA_EN_7___S 17 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_BIAS_7___M 0x0001E000 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_BIAS_7___S 13 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_AUX_CAP_7___M 0x00001800 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_AUX_CAP_7___S 11 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__BYPS_HG_7___M 0x00000400 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__BYPS_HG_7___S 10 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_MAINI_VREF_EN_7___M 0x00000200 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_MAINI_VREF_EN_7___S 9 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_MAIN_EN_7___M 0x00000100 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_MAIN_EN_7___S 8 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_AUX_EN_7___M 0x00000080 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_AUX_EN_7___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_SH_GAIN_7___M 0x0000003F +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7__LNA_SH_GAIN_7___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_LNA_0_7___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0 (0x005DF26C) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0___POR 0x00000001 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GM_FGAIN0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GMCAS_CGAIN0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GM_COARSE_GAIN0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GM_IBIAS_CTRL0___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GM_FGAIN0___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GM_FGAIN0___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GMCAS_CGAIN0___M 0x00000060 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GMCAS_CGAIN0___S 5 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GM_COARSE_GAIN0___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GM_COARSE_GAIN0___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GM_IBIAS_CTRL0___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0__GM_IBIAS_CTRL0___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_0___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1 (0x005DF270) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1___POR 0x00000082 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GM_FGAIN1___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GMCAS_CGAIN1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GM_COARSE_GAIN1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GM_IBIAS_CTRL1___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GM_FGAIN1___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GM_FGAIN1___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GMCAS_CGAIN1___M 0x00000060 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GMCAS_CGAIN1___S 5 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GM_COARSE_GAIN1___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GM_COARSE_GAIN1___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GM_IBIAS_CTRL1___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1__GM_IBIAS_CTRL1___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_1___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2 (0x005DF274) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2___POR 0x00000103 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GM_FGAIN2___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GMCAS_CGAIN2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GM_COARSE_GAIN2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GM_IBIAS_CTRL2___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GM_FGAIN2___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GM_FGAIN2___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GMCAS_CGAIN2___M 0x00000060 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GMCAS_CGAIN2___S 5 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GM_COARSE_GAIN2___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GM_COARSE_GAIN2___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GM_IBIAS_CTRL2___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2__GM_IBIAS_CTRL2___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_2___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3 (0x005DF278) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3___POR 0x000000D3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GM_FGAIN3___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GMCAS_CGAIN3___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GM_COARSE_GAIN3___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GM_IBIAS_CTRL3___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GM_FGAIN3___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GM_FGAIN3___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GMCAS_CGAIN3___M 0x00000060 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GMCAS_CGAIN3___S 5 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GM_COARSE_GAIN3___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GM_COARSE_GAIN3___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GM_IBIAS_CTRL3___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3__GM_IBIAS_CTRL3___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_3___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4 (0x005DF27C) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4___POR 0x00000153 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GM_FGAIN4___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GMCAS_CGAIN4___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GM_COARSE_GAIN4___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GM_IBIAS_CTRL4___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GM_FGAIN4___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GM_FGAIN4___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GMCAS_CGAIN4___M 0x00000060 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GMCAS_CGAIN4___S 5 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GM_COARSE_GAIN4___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GM_COARSE_GAIN4___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GM_IBIAS_CTRL4___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4__GM_IBIAS_CTRL4___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_4___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5 (0x005DF280) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5___POR 0x0000022B +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GM_FGAIN5___POR 0x4 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GMCAS_CGAIN5___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GM_COARSE_GAIN5___POR 0x1 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GM_IBIAS_CTRL5___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GM_FGAIN5___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GM_FGAIN5___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GMCAS_CGAIN5___M 0x00000060 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GMCAS_CGAIN5___S 5 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GM_COARSE_GAIN5___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GM_COARSE_GAIN5___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GM_IBIAS_CTRL5___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5__GM_IBIAS_CTRL5___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_5___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6 (0x005DF284) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6___POR 0x0000027C +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GM_FGAIN6___POR 0x4 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GMCAS_CGAIN6___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GM_COARSE_GAIN6___POR 0x3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GM_IBIAS_CTRL6___POR 0x4 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GM_FGAIN6___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GM_FGAIN6___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GMCAS_CGAIN6___M 0x00000060 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GMCAS_CGAIN6___S 5 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GM_COARSE_GAIN6___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GM_COARSE_GAIN6___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GM_IBIAS_CTRL6___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6__GM_IBIAS_CTRL6___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_6___S 0 + +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7 (0x005DF288) +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7___POR 0x00000354 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GM_FGAIN7___POR 0x6 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GMCAS_CGAIN7___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GM_COARSE_GAIN7___POR 0x2 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GM_IBIAS_CTRL7___POR 0x4 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GM_FGAIN7___M 0x00000380 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GM_FGAIN7___S 7 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GMCAS_CGAIN7___M 0x00000060 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GMCAS_CGAIN7___S 5 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GM_COARSE_GAIN7___M 0x00000018 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GM_COARSE_GAIN7___S 3 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GM_IBIAS_CTRL7___M 0x00000007 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7__GM_IBIAS_CTRL7___S 0 +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7___M 0x000003FF +#define PHYA_IRON2G_RFA_BT_RXFE_CH1_BT_RXFE_GM_0_7___S 0 + +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH0 (0x005DFC00) +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH0___POR 0x32D55555 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH0__NBNA___POR 0x065 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH0__NF___POR 0x555555 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH0__NBNA___M 0xFF800000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH0__NBNA___S 23 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH0__NF___M 0x007FFFFF +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH0__NF___S 0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH0___S 0 + +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH1 (0x005DFC04) +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH1__SD_NF_OFFSET___POR 0x0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH1__BSTARGET_OFS_COARSE___POR 0x00 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH1__BSTARGET_OFS_FINE___POR 0x00 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH1__BS_COARSE_FINE_BDRY___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH1__SD_NF_OFFSET___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH1__SD_NF_OFFSET___S 16 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH1__BSTARGET_OFS_COARSE___M 0x0000FC00 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH1__BSTARGET_OFS_COARSE___S 10 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH1__BSTARGET_OFS_FINE___M 0x000003F0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH1__BSTARGET_OFS_FINE___S 4 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH1__BS_COARSE_FINE_BDRY___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH1__BS_COARSE_FINE_BDRY___S 0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH1___S 0 + +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2 (0x005DFC08) +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2___POR 0x0042AAAA +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_IF_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_DELTA_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_BASE_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_START___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_DELTA___POR 0x42AAAA +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_IF_SEL___M 0x10000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_IF_SEL___S 28 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_DELTA_SEL___M 0x08000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_DELTA_SEL___S 27 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_BASE_SEL___M 0x04000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_BASE_SEL___S 26 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_DIS___M 0x02000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_DIS___S 25 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_START___M 0x01000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_START___S 24 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_DELTA___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2__FC_DELTA___S 0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH2___S 0 + +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH3 (0x005DFC0C) +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH3___POR 0x00005100 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH3__IF_OFFSET___POR 0x000051 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH3__IF_OFFSET___M 0xFFFFFF00 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH3__IF_OFFSET___S 8 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH3___M 0xFFFFFF00 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_CH3___S 8 + +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0 (0x005DFC10) +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0___POR 0x00282680 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSSTART___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSMODE___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BKSHFT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSSETT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSWAIT___POR 0x1 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSSAMPLE___POR 0x2 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__LPF_VTUNEMON_TMR___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BS_RFCNT_OUT_TIME___POR 0x1 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__RFCNTEN_DLY_DIS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BS_VMID___POR 0x6 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__SDM_SEL___POR 0x2 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__SDMOGAIN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSTESTEN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__SDTESTEN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__SD_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__D_PLLMD___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSSTART___M 0x80000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSSTART___S 31 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSMODE___M 0x70000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSMODE___S 28 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BKSHFT___M 0x0C000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BKSHFT___S 26 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSSETT___M 0x03000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSSETT___S 24 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSWAIT___M 0x00E00000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSWAIT___S 21 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSSAMPLE___M 0x001C0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSSAMPLE___S 18 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__LPF_VTUNEMON_TMR___M 0x00030000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__LPF_VTUNEMON_TMR___S 16 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BS_RFCNT_OUT_TIME___M 0x0000E000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BS_RFCNT_OUT_TIME___S 13 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__RFCNTEN_DLY_DIS___M 0x00001000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__RFCNTEN_DLY_DIS___S 12 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BS_VMID___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BS_VMID___S 8 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__SDM_SEL___M 0x000000C0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__SDM_SEL___S 6 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__SDMOGAIN___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__SDMOGAIN___S 4 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSTESTEN___M 0x00000008 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__BSTESTEN___S 3 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__SDTESTEN___M 0x00000004 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__SDTESTEN___S 2 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__SD_RESET___M 0x00000002 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__SD_RESET___S 1 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__D_PLLMD___M 0x00000001 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0__D_PLLMD___S 0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS0___S 0 + +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS1 (0x005DFC14) +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS1___POR 0x04000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS1__NF0B___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS1__IVCOBK___POR 0x400 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS1__TSTCNT___POR 0x0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS1__NF0B___M 0x08000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS1__NF0B___S 27 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS1__IVCOBK___M 0x07FF0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS1__IVCOBK___S 16 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS1__TSTCNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS1__TSTCNT___S 0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS1___M 0x0FFFFFFF +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS1___S 0 + +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2 (0x005DFC18) +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2___POR 0x6002A000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__BS_OVCAL_BDRY___POR 0x3 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__PLL_SLIP_DET_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__SDM_SEL_RSBCAL___POR 0x2 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__SDM_SEL_TX___POR 0x2 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__SDM_SEL_RX___POR 0x2 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__DTEST2_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__DTEST1_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__DTEST0_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__BS_OVCAL_BDRY___M 0xE0000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__BS_OVCAL_BDRY___S 29 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__PLL_SLIP_DET_RESET___M 0x10000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__PLL_SLIP_DET_RESET___S 28 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__SDM_SEL_RSBCAL___M 0x00030000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__SDM_SEL_RSBCAL___S 16 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__SDM_SEL_TX___M 0x0000C000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__SDM_SEL_TX___S 14 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__SDM_SEL_RX___M 0x00003000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__SDM_SEL_RX___S 12 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__DTEST2_SEL___M 0x00000F00 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__DTEST2_SEL___S 8 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__DTEST1_SEL___M 0x000000F0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__DTEST1_SEL___S 4 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__DTEST0_SEL___M 0x0000000F +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2__DTEST0_SEL___S 0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2___M 0xF003FFFF +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_BT_SYNTH_BS2___S 0 + +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS0 (0x005DFC1C) +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS0__RO_BSTARGET___POR 0x0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS0__RO_BSCOUNT___POR 0x0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS0__RO_BSTARGET___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS0__RO_BSTARGET___S 16 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS0__RO_BSCOUNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS0__RO_BSCOUNT___S 0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS0___S 0 + +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1 (0x005DFC20) +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BSDELTA_B3___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BSDELTA_B2___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BSDELTA_B1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BSDELTA_B0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_VC_2HI___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_VC_2LO___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BIST_ON___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BSON___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BSDELTA_B3___M 0xF0000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BSDELTA_B3___S 28 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BSDELTA_B2___M 0x0F000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BSDELTA_B2___S 24 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BSDELTA_B1___M 0x00F00000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BSDELTA_B1___S 20 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BSDELTA_B0___M 0x000F0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BSDELTA_B0___S 16 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_VC_2HI___M 0x00004000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_VC_2HI___S 14 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_VC_2LO___M 0x00002000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_VC_2LO___S 13 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BIST_ON___M 0x00001000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BIST_ON___S 12 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BSON___M 0x00000800 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1__RO_BSON___S 11 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1___M 0xFFFF7800 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS1___S 11 + +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2 (0x005DFC24) +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_HI_INJECT___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_LPPS_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_LE_2MBW___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_SYN_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_RX_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_TX0_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_TX2_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_RSBCAL0_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_RSBCAL2_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_VC_2HI_AT_VTUNEMON___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_VC_2LO_AT_VTUNEMON___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_VC_2HI_AFTER_VTUNEMON___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_VC_2LO_AFTER_VTUNEMON___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_PLL_LOCK_DET___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_PLL_LOCK___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_HOP_FREQ___POR 0x00 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_HI_INJECT___M 0x80000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_HI_INJECT___S 31 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_LPPS_EN___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_LPPS_EN___S 30 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_LE_2MBW___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_LE_2MBW___S 29 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_SYN_EN___M 0x10000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_SYN_EN___S 28 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_RX_EN___M 0x08000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_RX_EN___S 27 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_TX0_EN___M 0x04000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_TX0_EN___S 26 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_TX2_EN___M 0x02000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_TX2_EN___S 25 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_RSBCAL0_EN___M 0x01000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_RSBCAL0_EN___S 24 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_RSBCAL2_EN___M 0x00800000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_RSBCAL2_EN___S 23 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_VC_2HI_AT_VTUNEMON___M 0x00001000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_VC_2HI_AT_VTUNEMON___S 12 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_VC_2LO_AT_VTUNEMON___M 0x00000800 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_VC_2LO_AT_VTUNEMON___S 11 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_VC_2HI_AFTER_VTUNEMON___M 0x00000400 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_VC_2HI_AFTER_VTUNEMON___S 10 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_VC_2LO_AFTER_VTUNEMON___M 0x00000200 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_VC_2LO_AFTER_VTUNEMON___S 9 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_PLL_LOCK_DET___M 0x00000100 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_PLL_LOCK_DET___S 8 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_PLL_LOCK___M 0x00000080 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_PLL_LOCK___S 7 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_HOP_FREQ___M 0x0000007F +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2__RO_HOP_FREQ___S 0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2___M 0xFF801FFF +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS2___S 0 + +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS3 (0x005DFC28) +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS3___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS3__RO_NBNA___POR 0x000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS3__RO_NF___POR 0x000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS3__RO_NBNA___M 0xFF800000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS3__RO_NBNA___S 23 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS3__RO_NF___M 0x007FFFFF +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS3__RO_NF___S 0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS3___S 0 + +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS4 (0x005DFC2C) +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS4___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS4___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS4__RO_FVCOBK___POR 0x000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS4__RO_FVCOBK___M 0x000007FF +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS4__RO_FVCOBK___S 0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS4___M 0x000007FF +#define PHYA_IRON2G_RFA_BT_SYNTH_BS_RO_BT_SYNTH_BS4___S 0 + +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0 (0x005DFC40) +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0___POR 0x07D2F998 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_START___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_VMID_KVCOM___POR 0x7 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_VMID_KVCOH___POR 0xD +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_VMID_KVCOL___POR 0x2 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__EN_VCO_BIST___POR 0x1 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__EN_NDIV_BIST___POR 0x1 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__EN_RFCNT_BIST___POR 0x1 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_RFCNT_OUT_TIME___POR 0x6 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_TIME___POR 0x1 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_WAIT___POR 0x2 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__NDIV_BIST_TIME___POR 0x3 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_START___M 0x80000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_START___S 31 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_MODE___M 0x70000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_MODE___S 28 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_VMID_KVCOM___M 0x0F000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_VMID_KVCOM___S 24 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_VMID_KVCOH___M 0x00F00000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_VMID_KVCOH___S 20 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_VMID_KVCOL___M 0x000F0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_VMID_KVCOL___S 16 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__EN_VCO_BIST___M 0x00008000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__EN_VCO_BIST___S 15 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__EN_NDIV_BIST___M 0x00004000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__EN_NDIV_BIST___S 14 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__EN_RFCNT_BIST___M 0x00002000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__EN_RFCNT_BIST___S 13 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_RFCNT_OUT_TIME___M 0x00001C00 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_RFCNT_OUT_TIME___S 10 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_TIME___M 0x00000300 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_TIME___S 8 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_WAIT___M 0x000000C0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__BIST_WAIT___S 6 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__NDIV_BIST_TIME___M 0x00000038 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0__NDIV_BIST_TIME___S 3 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0___M 0xFFFFFFF8 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_BT_SYNTH_BIST0___S 3 + +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST0 (0x005DFC44) +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST0___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST0__RO_RFCNT_BIST_PASS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST0__RO_RFCNT_LATCH_TYPE___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST0__RO_BIST_OVERLAP___POR 0x000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST0__RO_BIST_MONO___POR 0x000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST0__RO_RFCNT_BIST_PASS___M 0x80000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST0__RO_RFCNT_BIST_PASS___S 31 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST0__RO_RFCNT_LATCH_TYPE___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST0__RO_RFCNT_LATCH_TYPE___S 30 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST0__RO_BIST_OVERLAP___M 0x07FF0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST0__RO_BIST_OVERLAP___S 16 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST0__RO_BIST_MONO___M 0x000007FF +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST0__RO_BIST_MONO___S 0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST0___M 0xC7FF07FF +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST0___S 0 + +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST1 (0x005DFC48) +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST1___POR 0x7FFF0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST1__RO_OVERLAP_CNT_DIFF___POR 0x7FFF +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST1__RO_OVERLAP_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST1__RO_OVERLAP_CNT_DIFF___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST1__RO_OVERLAP_CNT_DIFF___S 16 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST1__RO_OVERLAP_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST1__RO_OVERLAP_CNT___S 0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST1___S 0 + +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST2 (0x005DFC4C) +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST2___POR 0x7FFF0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST2__RO_MONO_CNT_DIFF___POR 0x7FFF +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST2__RO_MONO_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST2__RO_MONO_CNT_DIFF___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST2__RO_MONO_CNT_DIFF___S 16 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST2__RO_MONO_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST2__RO_MONO_CNT___S 0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST2___S 0 + +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST3 (0x005DFC50) +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST3___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST3__RO_MIN_BANK_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST3__RO_MAX_BANK_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST3__RO_MIN_BANK_CNT___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST3__RO_MIN_BANK_CNT___S 16 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST3__RO_MAX_BANK_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST3__RO_MAX_BANK_CNT___S 0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST3___S 0 + +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST4 (0x005DFC54) +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST4___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST4___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST4__RO_ONEBANK_LOW_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST4__RO_ONEBANK_MID_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST4__RO_ONEBANK_LOW_CNT___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST4__RO_ONEBANK_LOW_CNT___S 16 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST4__RO_ONEBANK_MID_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST4__RO_ONEBANK_MID_CNT___S 0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST4___S 0 + +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST5 (0x005DFC58) +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST5___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST5___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST5__RO_ONEBANK_HIGH_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST5__RO_RFCNT_BIST_CNT___POR 0x0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST5__RO_ONEBANK_HIGH_CNT___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST5__RO_ONEBANK_HIGH_CNT___S 16 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST5__RO_RFCNT_BIST_CNT___M 0x0000FFFF +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST5__RO_RFCNT_BIST_CNT___S 0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST5___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST5___S 0 + +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST6 (0x005DFC5C) +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST6___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST6___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST6__RO_NDIV_BIST_CNT_55___POR 0x0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST6__RO_NDIV_BIST_CNT_AA___POR 0x0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST6__RO_NDIV_BIST_CNT_55___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST6__RO_NDIV_BIST_CNT_55___S 16 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST6__RO_NDIV_BIST_CNT_AA___M 0x0000FFFF +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST6__RO_NDIV_BIST_CNT_AA___S 0 +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST6___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_SYNTH_BIST_RO_BT_SYNTH_BIST6___S 0 + +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0 (0x005DFC80) +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0___POR 0x00040000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__SDM_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__EN_DCLK___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__VC_2HI_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__VC_2LO_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__SYN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__FASTCH_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__FASTCH_TMR___POR 0x2 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__RFCNT_SEL_BSC___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__RFCNT_BSCLK_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__RFCNT_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__RFCNT_OUT_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__VCON_SW_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__VCO_VMID_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__VCO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__SDM_EN___M 0xC0000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__SDM_EN___S 30 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__EN_DCLK___M 0x30000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__EN_DCLK___S 28 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__VC_2HI_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__VC_2HI_OVS___S 26 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__VC_2LO_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__VC_2LO_OVS___S 24 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__SYN_EN_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__SYN_EN_OVS___S 22 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__FASTCH_SEL___M 0x00300000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__FASTCH_SEL___S 20 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__FASTCH_TMR___M 0x000E0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__FASTCH_TMR___S 17 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__RFCNT_SEL_BSC___M 0x0001C000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__RFCNT_SEL_BSC___S 14 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__RFCNT_BSCLK_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__RFCNT_BSCLK_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__RFCNT_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__RFCNT_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__RFCNT_OUT_EN_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__RFCNT_OUT_EN_OVS___S 8 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__VCON_SW_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__VCON_SW_OVS___S 6 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__VCO_VMID_EN_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__VCO_VMID_EN_OVS___S 4 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__VCO_EN_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0__VCO_EN_OVS___S 2 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC0___S 2 + +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1 (0x005DFC84) +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__VCO_DIV2_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__LO_TXBUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__LO_RXBUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__VCO_SHORTR_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__PRNDIV_RSTB_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__PRNDIV_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__PFDCP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__LPF_PRECH_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__HI_INJECT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__LPPS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__LE_2MBW_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__RX0_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__TX0_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__RX1_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__RSBCAL0_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__VCO_DIV2_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__VCO_DIV2_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__LO_TXBUF_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__LO_TXBUF_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__LO_RXBUF_EN_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__LO_RXBUF_EN_OVS___S 24 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__VCO_SHORTR_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__VCO_SHORTR_OVS___S 22 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__PRNDIV_RSTB_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__PRNDIV_RSTB_OVS___S 20 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__PRNDIV_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__PRNDIV_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__PFDCP_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__PFDCP_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__LPF_PRECH_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__LPF_PRECH_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__HI_INJECT_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__HI_INJECT_OVS___S 12 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__LPPS_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__LPPS_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__LE_2MBW_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__LE_2MBW_OVS___S 8 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__RX0_EN_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__RX0_EN_OVS___S 6 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__TX0_EN_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__TX0_EN_OVS___S 4 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__RX1_EN_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__RX1_EN_OVS___S 2 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__RSBCAL0_EN_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1__RSBCAL0_EN_OVS___S 0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1___M 0xCFFFFFFF +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC1___S 0 + +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2 (0x005DFC88) +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__RSBCAL2_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__HOP_FREQ_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__HOP_FREQ_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__XTAL_BUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__MMD_LOAD_ASYN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__PRES_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__BS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__ATOP_ISO_DIS_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__LDO_VCO_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__LDO_VCO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__RSBCAL2_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__RSBCAL2_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__HOP_FREQ_OV___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__HOP_FREQ_OV___S 29 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__HOP_FREQ_OVD___M 0x1FC00000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__HOP_FREQ_OVD___S 22 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__XTAL_BUF_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__XTAL_BUF_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__MMD_LOAD_ASYN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__MMD_LOAD_ASYN_OVS___S 18 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__PRES_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__PRES_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__BS_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__BS_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__ATOP_ISO_DIS_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__ATOP_ISO_DIS_OVS___S 12 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__LDO_VCO_FC_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__LDO_VCO_FC_OVS___S 2 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__LDO_VCO_EN_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2__LDO_VCO_EN_OVS___S 0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2___M 0xFFFFF00F +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC2___S 0 + +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3 (0x005DFC8C) +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__VCO_DUAL_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__VCO_CBNK1_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__VCO_CBNK1_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__VCO_IBIAS_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__VCO_BUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__DIV2_5G_HS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__DIV2_10G_HS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__FBDIVBUF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__LDO0_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__LDO0_BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__VCO_DUAL_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__VCO_DUAL_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__VCO_CBNK1_OV___M 0x20000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__VCO_CBNK1_OV___S 29 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__VCO_CBNK1_OVD___M 0x1FFC0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__VCO_CBNK1_OVD___S 18 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__VCO_IBIAS_FC_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__VCO_IBIAS_FC_OVS___S 12 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__VCO_BUF_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__VCO_BUF_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__DIV2_5G_HS_EN_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__DIV2_5G_HS_EN_OVS___S 8 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__DIV2_10G_HS_EN_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__DIV2_10G_HS_EN_OVS___S 6 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__FBDIVBUF_EN_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__FBDIVBUF_EN_OVS___S 4 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__LDO0_EN_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__LDO0_EN_OVS___S 2 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__LDO0_BIAS_EN_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3__LDO0_BIAS_EN_OVS___S 0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3___M 0xFFFC3FFF +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC3___S 0 + +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4 (0x005DFC90) +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LDO1_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LDO1_BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LDO_REFGEN_BIAS_FASTCH_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LDO_REFGEN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO08_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO12_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO_BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO_LEAKER_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__VCOLDO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LPF_EN_VCO_VMID_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO_EN_FASTCH_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO_EN_REF_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__VC_ISO_DIS_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LDO1_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LDO1_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LDO1_BIAS_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LDO1_BIAS_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LDO_REFGEN_BIAS_FASTCH_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LDO_REFGEN_BIAS_FASTCH_OVS___S 26 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LDO_REFGEN_EN_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LDO_REFGEN_EN_OVS___S 24 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO08_EN_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO08_EN_OVS___S 22 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO12_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO12_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO_BIAS_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO_BIAS_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO_LEAKER_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO_LEAKER_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__VCOLDO_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__VCOLDO_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LPF_EN_VCO_VMID_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LPF_EN_VCO_VMID_OVS___S 12 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO_EN_FASTCH_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO_EN_FASTCH_OVS___S 10 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO_EN_REF_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO_EN_REF_OVS___S 8 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__VC_ISO_DIS_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__VC_ISO_DIS_OVS___S 6 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO_SEL___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4__LOLDO_SEL___S 4 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4___M 0xFFFFFFF0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC4___S 4 + +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC5 (0x005DFC94) +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC5___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC5__ENBF_IN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC5__ENBR_IN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC5__SD_ISO_L_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC5__SD_PRESET_L_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC5__ENBF_IN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC5__ENBF_IN_OVS___S 30 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC5__ENBR_IN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC5__ENBR_IN_OVS___S 28 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC5__SD_ISO_L_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC5__SD_ISO_L_OVS___S 26 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC5__SD_PRESET_L_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC5__SD_PRESET_L_OVS___S 24 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC5___M 0xFF000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC5___S 24 + +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC6 (0x005DFC98) +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC6___POR 0x58000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC6__LOLDO_VREGSEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC6__LOLDO_VREGSEL_OVD___POR 0xB +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC6__LOLDO_VREGSEL_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC6__LOLDO_VREGSEL_OV___S 31 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC6__LOLDO_VREGSEL_OVD___M 0x78000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC6__LOLDO_VREGSEL_OVD___S 27 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC6___M 0xF8000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_PC_BT_SYNTH_PC6___S 27 + +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0 (0x005DFCC0) +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0___POR 0x00494800 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_PFD_UP_DLY___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_PFD_DW_DLY___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_PFD_ENPFDDEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_CP_CPDIFF___POR 0x1 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_CP_LEAKEN___POR 0x2 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_CP_BIASMULT___POR 0x1 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_CP_BIASI___POR 0x1 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_CP_CPI___POR 0x2 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_PINVC___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_PFD_UP_DLY___M 0xF0000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_PFD_UP_DLY___S 28 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_PFD_DW_DLY___M 0x0F000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_PFD_DW_DLY___S 24 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_PFD_ENPFDDEL___M 0x00800000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_PFD_ENPFDDEL___S 23 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_CP_CPDIFF___M 0x00400000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_CP_CPDIFF___S 22 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_CP_LEAKEN___M 0x003C0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_CP_LEAKEN___S 18 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_CP_BIASMULT___M 0x00030000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_CP_BIASMULT___S 16 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_CP_BIASI___M 0x0000C000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_CP_BIASI___S 14 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_CP_CPI___M 0x00003C00 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_CP_CPI___S 10 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_PINVC___M 0x00000200 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0__D_PINVC___S 9 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC0___S 9 + +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1 (0x005DFCC4) +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1___POR 0x0F623200 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_R2BYP___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_EN_VCMONITOR___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_SEL_VCOMP_LOW___POR 0x1 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_SEL_VCOMP_HI___POR 0x7 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_RZ___POR 0x6 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_PINVTUNE___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_CINT___POR 0x4 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_VCO_RES_RC___POR 0x6 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_VCO_CAP_RC___POR 0x4 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPPS_LVL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_R2BYP___M 0x80000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_R2BYP___S 31 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_EN_VCMONITOR___M 0x40000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_EN_VCMONITOR___S 30 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_SEL_VCOMP_LOW___M 0x38000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_SEL_VCOMP_LOW___S 27 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_SEL_VCOMP_HI___M 0x07000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_SEL_VCOMP_HI___S 24 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_RZ___M 0x00F00000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_RZ___S 20 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_PINVTUNE___M 0x00080000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_PINVTUNE___S 19 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_CINT___M 0x00078000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPF_CINT___S 15 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_VCO_RES_RC___M 0x00007800 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_VCO_RES_RC___S 11 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_VCO_CAP_RC___M 0x00000780 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_VCO_CAP_RC___S 7 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPPS_LVL___M 0x00000060 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1__D_LPPS_LVL___S 5 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1___M 0xFFFFFFE0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC1___S 5 + +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2 (0x005DFCC8) +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2___POR 0x62007000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_KVCO_TUNE___POR 0x1 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_RBVAR___POR 0x2 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_FBDIV_EN_VCOTST___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_FBDIV_EN_PWE___POR 0x1 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_BIAS_LPF_COMP___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_BIAS_PFDCP___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_BIAS_VCO_REG0P85_REFDAC___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_LDO_VCO_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_LDO_VCO_VREF___POR 0x7 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_ATB_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__LP_MODE3_VALID___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_KVCO_TUNE___M 0xC0000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_KVCO_TUNE___S 30 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_RBVAR___M 0x30000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_RBVAR___S 28 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_FBDIV_EN_VCOTST___M 0x04000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_FBDIV_EN_VCOTST___S 26 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_FBDIV_EN_PWE___M 0x02000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_FBDIV_EN_PWE___S 25 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_BIAS_LPF_COMP___M 0x01C00000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_BIAS_LPF_COMP___S 22 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_BIAS_PFDCP___M 0x00380000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_BIAS_PFDCP___S 19 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_BIAS_VCO_REG0P85_REFDAC___M 0x00060000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_BIAS_VCO_REG0P85_REFDAC___S 17 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_LDO_VCO_BYPASS___M 0x00010000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_LDO_VCO_BYPASS___S 16 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_LDO_VCO_VREF___M 0x0000F000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_LDO_VCO_VREF___S 12 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_ATB_SEL___M 0x0000003E +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__D_ATB_SEL___S 1 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__LP_MODE3_VALID___M 0x00000001 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2__LP_MODE3_VALID___S 0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2___M 0xF7FFF03F +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC2___S 0 + +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC3 (0x005DFCCC) +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC3___POR 0x00000001 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC3__D_SYN_SPARE_0___POR 0x00000001 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC3__D_SYN_SPARE_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC3__D_SYN_SPARE_0___S 0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC3___S 0 + +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_RO_BT_SYNTH_AC (0x005DFCD0) +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_RO_BT_SYNTH_AC___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_RO_BT_SYNTH_AC___POR 0x00000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_RO_BT_SYNTH_AC__RO_LP_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_RO_BT_SYNTH_AC__RO_LP_MODE___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_RO_BT_SYNTH_AC__RO_LP_MODE___S 0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_RO_BT_SYNTH_AC___M 0x00000003 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_RO_BT_SYNTH_AC___S 0 + +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4 (0x005DFCD4) +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4___POR 0x01093814 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_FBDIVBUF_CTRL___POR 0x1 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_MMD_PULSEWIDTH_STRETCH___POR 0x1 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_MMD_VCOTST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_CP_LCP_CTRL___POR 0x1 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_VCO_IBIAS_BYP___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_VCO_CVAR___POR 0x3 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_VCO_IBIAS___POR 0x10 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_LDO0_LEAKER_ON___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_LDO0_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_LDO0_VREG___POR 0xA +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_FBDIVBUF_CTRL___M 0x03000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_FBDIVBUF_CTRL___S 24 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_MMD_PULSEWIDTH_STRETCH___M 0x00080000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_MMD_PULSEWIDTH_STRETCH___S 19 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_MMD_VCOTST_EN___M 0x00040000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_MMD_VCOTST_EN___S 18 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_CP_LCP_CTRL___M 0x00030000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_CP_LCP_CTRL___S 16 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_VCO_IBIAS_BYP___M 0x00008000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_VCO_IBIAS_BYP___S 15 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_VCO_CVAR___M 0x00007000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_VCO_CVAR___S 12 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_VCO_IBIAS___M 0x00000F80 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_VCO_IBIAS___S 7 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_LDO0_LEAKER_ON___M 0x00000040 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_LDO0_LEAKER_ON___S 6 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_LDO0_BYPASS___M 0x00000020 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_LDO0_BYPASS___S 5 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_LDO0_VREG___M 0x0000001E +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4__D_LDO0_VREG___S 1 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4___M 0x030FFFFE +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC4___S 1 + +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5 (0x005DFCD8) +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5___POR 0x26100A18 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO0_OTA_CUR___POR 0x1 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO1_LEAKER_ON___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO1_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO1_VREG___POR 0xC +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO1_OTA_CUR___POR 0x1 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO_REFGEN_BIAS_BWRSEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LOLDO_BYP___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LOLDO_OTACUR___POR 0x1 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LOLDO_VREGSEL_RX___POR 0x4 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_VCOLDO_BYP___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_VCOLDO_OTACUR___POR 0x3 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO0_OTA_CUR___M 0xE0000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO0_OTA_CUR___S 29 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO1_LEAKER_ON___M 0x10000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO1_LEAKER_ON___S 28 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO1_BYPASS___M 0x08000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO1_BYPASS___S 27 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO1_VREG___M 0x07800000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO1_VREG___S 23 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO1_OTA_CUR___M 0x00700000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO1_OTA_CUR___S 20 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO_REFGEN_BIAS_BWRSEL___M 0x000C0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LDO_REFGEN_BIAS_BWRSEL___S 18 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LOLDO_BYP___M 0x00004000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LOLDO_BYP___S 14 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LOLDO_OTACUR___M 0x00003800 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LOLDO_OTACUR___S 11 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LOLDO_VREGSEL_RX___M 0x00000780 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_LOLDO_VREGSEL_RX___S 7 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_VCOLDO_BYP___M 0x00000040 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_VCOLDO_BYP___S 6 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_VCOLDO_OTACUR___M 0x00000038 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5__D_VCOLDO_OTACUR___S 3 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5___M 0xFFFC7FF8 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC5___S 3 + +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6 (0x005DFCDC) +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6___POR 0xA6040000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_VCOLDO_VREG10SEL___POR 0xA +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_VCOLDO_VRES07SEL___POR 0x6 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_VCOLDO_VRES09SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_VCO_LPF_R3___POR 0x2 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_ATBSEL_REFGEN___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_ATBSEL_LDO0___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_ATBSEL_LDO1___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_ATBSEL_CP___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_ATBSEL_LPF___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_LOLDO_BW_RSEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_VCOLDO_VREG10SEL___M 0xF0000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_VCOLDO_VREG10SEL___S 28 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_VCOLDO_VRES07SEL___M 0x0F000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_VCOLDO_VRES07SEL___S 24 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_VCOLDO_VRES09SEL___M 0x00F00000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_VCOLDO_VRES09SEL___S 20 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_VCO_LPF_R3___M 0x000E0000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_VCO_LPF_R3___S 17 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_ATBSEL_REFGEN___M 0x00010000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_ATBSEL_REFGEN___S 16 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_ATBSEL_LDO0___M 0x00008000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_ATBSEL_LDO0___S 15 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_ATBSEL_LDO1___M 0x00004000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_ATBSEL_LDO1___S 14 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_ATBSEL_CP___M 0x00003C00 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_ATBSEL_CP___S 10 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_ATBSEL_LPF___M 0x000003C0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_ATBSEL_LPF___S 6 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_LOLDO_BW_RSEL___M 0x00000030 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6__D_LOLDO_BW_RSEL___S 4 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6___M 0xFFFFFFF0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC6___S 4 + +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC7 (0x005DFCE0) +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC7___POR 0xB0000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC7__D_LOLDO_VREGSEL_TX___POR 0xB +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC7__D_LOLDO_VREGSEL_TX___M 0xF0000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC7__D_LOLDO_VREGSEL_TX___S 28 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC7___M 0xF0000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_AC7___S 28 + +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0 (0x005DFD00) +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0___POR 0x90CAA000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__BIAS_VCO_0___POR 0x48 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__SEL_REGVCO_RCTRL_0___POR 0x6 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__LO_RXBUF_TUNE_0___POR 0x1 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__LO_TXBUF_TUNE_0___POR 0x1 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__LODIST_PREBUF_TUNE_0___POR 0x1 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__PRNDIV_BUF_TUNE_0___POR 0x1 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__BIAS_VCO_0___M 0xFE000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__BIAS_VCO_0___S 25 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__SEL_REGVCO_RCTRL_0___M 0x01E00000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__SEL_REGVCO_RCTRL_0___S 21 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__LO_RXBUF_TUNE_0___M 0x00180000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__LO_RXBUF_TUNE_0___S 19 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__LO_TXBUF_TUNE_0___M 0x00060000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__LO_TXBUF_TUNE_0___S 17 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__LODIST_PREBUF_TUNE_0___M 0x00018000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__LODIST_PREBUF_TUNE_0___S 15 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__PRNDIV_BUF_TUNE_0___M 0x00006000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0__PRNDIV_BUF_TUNE_0___S 13 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0___M 0xFFFFE000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_0___S 13 + +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1 (0x005DFD04) +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1___POR 0x90CAA000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__BIAS_VCO_1___POR 0x48 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__SEL_REGVCO_RCTRL_1___POR 0x6 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__LO_RXBUF_TUNE_1___POR 0x1 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__LO_TXBUF_TUNE_1___POR 0x1 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__LODIST_PREBUF_TUNE_1___POR 0x1 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__PRNDIV_BUF_TUNE_1___POR 0x1 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__BIAS_VCO_1___M 0xFE000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__BIAS_VCO_1___S 25 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__SEL_REGVCO_RCTRL_1___M 0x01E00000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__SEL_REGVCO_RCTRL_1___S 21 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__LO_RXBUF_TUNE_1___M 0x00180000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__LO_RXBUF_TUNE_1___S 19 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__LO_TXBUF_TUNE_1___M 0x00060000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__LO_TXBUF_TUNE_1___S 17 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__LODIST_PREBUF_TUNE_1___M 0x00018000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__LODIST_PREBUF_TUNE_1___S 15 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__PRNDIV_BUF_TUNE_1___M 0x00006000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1__PRNDIV_BUF_TUNE_1___S 13 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1___M 0xFFFFE000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_1___S 13 + +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2 (0x005DFD08) +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2___POR 0x90CAA000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__BIAS_VCO_2___POR 0x48 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__SEL_REGVCO_RCTRL_2___POR 0x6 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__LO_RXBUF_TUNE_2___POR 0x1 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__LO_TXBUF_TUNE_2___POR 0x1 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__LODIST_PREBUF_TUNE_2___POR 0x1 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__PRNDIV_BUF_TUNE_2___POR 0x1 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__BIAS_VCO_2___M 0xFE000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__BIAS_VCO_2___S 25 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__SEL_REGVCO_RCTRL_2___M 0x01E00000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__SEL_REGVCO_RCTRL_2___S 21 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__LO_RXBUF_TUNE_2___M 0x00180000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__LO_RXBUF_TUNE_2___S 19 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__LO_TXBUF_TUNE_2___M 0x00060000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__LO_TXBUF_TUNE_2___S 17 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__LODIST_PREBUF_TUNE_2___M 0x00018000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__LODIST_PREBUF_TUNE_2___S 15 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__PRNDIV_BUF_TUNE_2___M 0x00006000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2__PRNDIV_BUF_TUNE_2___S 13 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2___M 0xFFFFE000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_2___S 13 + +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3 (0x005DFD0C) +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3___POR 0x90CAA000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__BIAS_VCO_3___POR 0x48 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__SEL_REGVCO_RCTRL_3___POR 0x6 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__LO_RXBUF_TUNE_3___POR 0x1 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__LO_TXBUF_TUNE_3___POR 0x1 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__LODIST_PREBUF_TUNE_3___POR 0x1 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__PRNDIV_BUF_TUNE_3___POR 0x1 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__BIAS_VCO_3___M 0xFE000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__BIAS_VCO_3___S 25 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__SEL_REGVCO_RCTRL_3___M 0x01E00000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__SEL_REGVCO_RCTRL_3___S 21 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__LO_RXBUF_TUNE_3___M 0x00180000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__LO_RXBUF_TUNE_3___S 19 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__LO_TXBUF_TUNE_3___M 0x00060000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__LO_TXBUF_TUNE_3___S 17 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__LODIST_PREBUF_TUNE_3___M 0x00018000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__LODIST_PREBUF_TUNE_3___S 15 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__PRNDIV_BUF_TUNE_3___M 0x00006000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3__PRNDIV_BUF_TUNE_3___S 13 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3___M 0xFFFFE000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_LP_CONTROL_3___S 13 + +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0 (0x005DFD14) +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0___POR 0x00132320 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_PFD_UP_DLY___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_PFD_DW_DLY___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_PFD_ENPFDDEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_CP_LEAKEN___POR 0x2 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_LPF_RZ___POR 0x6 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_LPF_CINT___POR 0x4 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_VCO_RES_RC___POR 0x6 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_VCO_CAP_RC___POR 0x4 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RO_AC_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RSBCAL_AC_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_PFD_UP_DLY___M 0xF0000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_PFD_UP_DLY___S 28 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_PFD_DW_DLY___M 0x0F000000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_PFD_DW_DLY___S 24 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_PFD_ENPFDDEL___M 0x00800000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_PFD_ENPFDDEL___S 23 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_CP_LEAKEN___M 0x00780000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_CP_LEAKEN___S 19 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_LPF_RZ___M 0x00078000 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_LPF_RZ___S 15 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_LPF_CINT___M 0x00007800 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_LPF_CINT___S 11 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_VCO_RES_RC___M 0x00000780 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_VCO_RES_RC___S 7 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_VCO_CAP_RC___M 0x00000078 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RX_VCO_CAP_RC___S 3 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RO_AC_SEL___M 0x00000002 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RO_AC_SEL___S 1 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RSBCAL_AC_SEL___M 0x00000001 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0__RSBCAL_AC_SEL___S 0 +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0___M 0xFFFFFFFB +#define PHYA_IRON2G_RFA_BT_SYNTH_AC_BT_SYNTH_RX_AC0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_TESTREG (0x005E0000) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_TESTREG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_TESTREG___POR 0x0000AB80 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_TESTREG__TESTREG___POR 0x0000AB80 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_TESTREG__TESTREG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_TESTREG__TESTREG___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_TESTREG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_TESTREG___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_0 (0x005E0004) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_0__SYN_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_0__SYN_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_0__SYN_EN___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_0___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1 (0x005E0008) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__XPA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__IPA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__INJECT_TXLO_I_OFFSET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__LPBK_TX_CHAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__TX_RESIDUE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__RF_LPBK_PHASE_SHIFT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__CAL_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__XPA_EN_OVS___M 0x00001800 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__XPA_EN_OVS___S 11 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__IPA_EN_OVS___M 0x00000600 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__IPA_EN_OVS___S 9 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__INJECT_TXLO_I_OFFSET___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__INJECT_TXLO_I_OFFSET___S 7 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__LPBK_TX_CHAIN___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__LPBK_TX_CHAIN___S 6 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__TX_RESIDUE___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__TX_RESIDUE___S 5 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__RF_LPBK_PHASE_SHIFT___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__RF_LPBK_PHASE_SHIFT___S 4 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__CAL_MODE___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1__CAL_MODE___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_0 (0x005E000C) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_0___POR 0x00000010 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_0__TRSW_EN_RXGAIN_CAL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_0__TRSW_EN_DPD___POR 0x1 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_0__CAL_SUB_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_0__TRSW_EN_RXGAIN_CAL___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_0__TRSW_EN_RXGAIN_CAL___S 5 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_0__TRSW_EN_DPD___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_0__TRSW_EN_DPD___S 4 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_0__CAL_SUB_MODE___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_0__CAL_SUB_MODE___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_0___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_1 (0x005E0010) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_1___POR 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_1__FCS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_1__LP_RX_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_1__CLPC_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_1__FCS___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_1__FCS___S 2 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_1__LP_RX_EN___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_1__LP_RX_EN___S 1 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_1__CLPC_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_1__CLPC_EN___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_1___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2 (0x005E0014) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2___POR 0x0000C001 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__PMM_SYN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_CORE_RX_GAIN_ON___POR 0x1 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_CORE_RX_DCOC_ON___POR 0x1 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_CORE_TX_GAIN_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_CORE_TX_DCOC_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_PERIPH_RX_GAIN_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_PERIPH_RX_DCOC_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_PERIPH_TX_GAIN_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_PERIPH_TX_DCOC_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__RXIQ_CROSS_CHAIN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__PMM_SYN_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__PMM_SYN_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_CORE_RX_GAIN_ON___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_CORE_RX_GAIN_ON___S 15 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_CORE_RX_DCOC_ON___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_CORE_RX_DCOC_ON___S 14 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_CORE_TX_GAIN_ON___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_CORE_TX_GAIN_ON___S 13 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_CORE_TX_DCOC_ON___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_CORE_TX_DCOC_ON___S 12 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_PERIPH_RX_GAIN_ON___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_PERIPH_RX_GAIN_ON___S 11 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_PERIPH_RX_DCOC_ON___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_PERIPH_RX_DCOC_ON___S 10 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_PERIPH_TX_GAIN_ON___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_PERIPH_TX_GAIN_ON___S 9 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_PERIPH_TX_DCOC_ON___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__FORCE_PERIPH_TX_DCOC_ON___S 8 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__RXIQ_CROSS_CHAIN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2__RXIQ_CROSS_CHAIN___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2___M 0xC000FF01 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MODE_SEL_2___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_BBSAT_0 (0x005E0018) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_BBSAT_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_BBSAT_0___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_BBSAT_0__AGC_BBSAT_RESET_PERIOD___POR 0x14 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_BBSAT_0__AGC_BBSAT_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_BBSAT_0__AGC_BBSAT_FLAG_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_BBSAT_0__RX_SATDET_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_BBSAT_0__AGC_BBSAT_RESET_PERIOD___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_BBSAT_0__AGC_BBSAT_RESET_PERIOD___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_BBSAT_0__AGC_BBSAT_MODE___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_BBSAT_0__AGC_BBSAT_MODE___S 25 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_BBSAT_0__AGC_BBSAT_FLAG_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_BBSAT_0__AGC_BBSAT_FLAG_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_BBSAT_0__RX_SATDET_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_BBSAT_0__RX_SATDET_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_BBSAT_0___M 0xFECC0000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_BBSAT_0___S 18 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0 (0x005E001C) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0__AGC_PKDET_RESET_PERIOD___POR 0x14 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0__AGC_PKDET_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0__AGC_PKDET_FLAG_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0__AGC_EN_BY_RX_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0__AGC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0__AGC_PKDET_RESET_PERIOD___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0__AGC_PKDET_RESET_PERIOD___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0__AGC_PKDET_MODE___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0__AGC_PKDET_MODE___S 25 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0__AGC_PKDET_FLAG_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0__AGC_PKDET_FLAG_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0__AGC_EN_BY_RX_EN___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0__AGC_EN_BY_RX_EN___S 20 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0__AGC_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0__AGC_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0___M 0xFEDC0000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PKDET_0___S 18 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_PKDET (0x005E0020) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_PKDET___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_PKDET___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_PKDET__RO_AGC_PKDET_FLAG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_PKDET__RO_AGC_BBSAT_FLAG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_PKDET__RO_AGC_PKDET_FLAG___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_PKDET__RO_AGC_PKDET_FLAG___S 1 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_PKDET__RO_AGC_BBSAT_FLAG___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_PKDET__RO_AGC_BBSAT_FLAG___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_PKDET___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_PKDET___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0 (0x005E0024) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0___POR 0x06769292 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T0_START_PRD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T0_END_PRD___POR 0x6 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T1_START_PRD___POR 0x7 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T1_END_PRD___POR 0x6 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T2_START_PRD___POR 0x9 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T2_END_PRD___POR 0x2 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T3_START_PRD___POR 0x9 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T3_END_PRD___POR 0x2 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T0_START_PRD___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T0_START_PRD___S 28 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T0_END_PRD___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T0_END_PRD___S 24 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T1_START_PRD___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T1_START_PRD___S 20 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T1_END_PRD___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T1_END_PRD___S 16 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T2_START_PRD___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T2_START_PRD___S 12 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T2_END_PRD___M 0x00000F00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T2_END_PRD___S 8 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T3_START_PRD___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T3_START_PRD___S 4 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T3_END_PRD___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0__TX_T3_END_PRD___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_STAGGER_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0 (0x005E0028) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0___POR 0x00004142 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T0_START_PRD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T0_END_PRD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T1_START_PRD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T1_END_PRD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T2_START_PRD___POR 0x4 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T2_END_PRD___POR 0x1 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T3_START_PRD___POR 0x4 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T3_END_PRD___POR 0x2 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T0_START_PRD___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T0_START_PRD___S 28 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T0_END_PRD___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T0_END_PRD___S 24 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T1_START_PRD___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T1_START_PRD___S 20 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T1_END_PRD___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T1_END_PRD___S 16 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T2_START_PRD___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T2_START_PRD___S 12 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T2_END_PRD___M 0x00000F00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T2_END_PRD___S 8 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T3_START_PRD___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T3_START_PRD___S 4 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T3_END_PRD___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0__RX_T3_END_PRD___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_STAGGER_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_TIMER_0 (0x005E002C) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_TIMER_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_TIMER_0___POR 0x20000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_TIMER_0__LNA_FC_PRD___POR 0x1 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_TIMER_0__LNA_FC_PRD___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_TIMER_0__LNA_FC_PRD___S 29 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_TIMER_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_TIMER_0___S 29 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_XFEM_0 (0x005E0030) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_XFEM_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_XFEM_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_XFEM_0__ZZZ_SPARE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_XFEM_0__ZZZ_SPARE___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_XFEM_0__ZZZ_SPARE___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_XFEM_0___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_XFEM_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_SPARE_0 (0x005E0034) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_SPARE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_SPARE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_SPARE_0__D_CHAIN_SPARE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_SPARE_0__D_CHAIN_SPARE_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_SPARE_0__D_CHAIN_SPARE_0___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_SPARE_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_SPARE_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_SPARE_1 (0x005E0038) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_SPARE_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_SPARE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_SPARE_1__D_CHAIN_SPARE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_SPARE_1__D_CHAIN_SPARE_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_SPARE_1__D_CHAIN_SPARE_1___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_SPARE_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_SPARE_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_COEX_GAIN_CFG (0x005E003C) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_COEX_GAIN_CFG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_COEX_GAIN_CFG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_COEX_GAIN_CFG__COEX_LNA_GAIN_FREEZE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_COEX_GAIN_CFG__COEX_LNA_GAIN_FREEZE___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_COEX_GAIN_CFG__COEX_LNA_GAIN_FREEZE___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_COEX_GAIN_CFG___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_COEX_GAIN_CFG___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_2 (0x005E0040) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_2__COEX_XLNA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_2__COEX_LNA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_2__COEX_XLNA_GAIN___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_2__COEX_XLNA_GAIN___S 3 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_2__COEX_LNA_GAIN___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_2__COEX_LNA_GAIN___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_2___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_PHY_2___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0 (0x005E0044) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0___POR 0x09200000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__WL_ISEL_IC___POR 0x4 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__WL_ISEL_IR___POR 0x4 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__WL_ISEL_ICPT___POR 0x4 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__D_IC_25U_TEST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__D_IR_25U_TEST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__D_ICPT_25U_TEST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__WL_ISEL_IC___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__WL_ISEL_IC___S 25 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__WL_ISEL_IR___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__WL_ISEL_IR___S 22 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__WL_ISEL_ICPT___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__WL_ISEL_ICPT___S 19 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__D_IC_25U_TEST_EN___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__D_IC_25U_TEST_EN___S 2 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__D_IR_25U_TEST_EN___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__D_IR_25U_TEST_EN___S 1 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__D_ICPT_25U_TEST_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0__D_ICPT_25U_TEST_EN___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0___M 0x0FF80007 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_MC_ISEL_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_ADC_ATEST (0x005E0048) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_ADC_ATEST___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_ADC_ATEST___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_ADC_ATEST__D_ATEST_EN_ADC_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_ADC_ATEST__D_ATEST_EN_ADC_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_ADC_ATEST__D_ATEST_EN_ADC_I___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_ADC_ATEST__D_ATEST_EN_ADC_I___S 1 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_ADC_ATEST__D_ATEST_EN_ADC_Q___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_ADC_ATEST__D_ATEST_EN_ADC_Q___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_ADC_ATEST___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_ADC_ATEST___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_0 (0x005E0080) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_0___POR 0x005078A0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_REGULAR___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_LG___POR 0x50 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_VLG___POR 0x78 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_COEX___POR 0xA0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_REGULAR___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_REGULAR___S 24 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_LG___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_LG___S 16 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_VLG___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_VLG___S 8 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_COEX___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_COEX___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1 (0x005E0084) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1___POR 0xC8F00000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_DPD___POR 0xC8 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_RXDCCAL___POR 0xF0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_SEL_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__TX_GAIN_LUT_SEL_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_DPD___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_DPD___S 24 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_RXDCCAL___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_RXDCCAL___S 16 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_SEL_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_SEL_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OV___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OV___S 7 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OVD___M 0x00000060 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OVD___S 5 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__TX_GAIN_LUT_SEL_OVS___M 0x00000018 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__TX_GAIN_LUT_SEL_OVS___S 3 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OV___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OV___S 2 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OVD___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1___M 0xFFFF03FF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RXGC_BASE_ADDR_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_GC_RAM_CONTROL (0x005E0088) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_GC_RAM_CONTROL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_GC_RAM_CONTROL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_GC_RAM_CONTROL__GC_MEM_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_GC_RAM_CONTROL__RXDCCAL_GAIN_TBL_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_GC_RAM_CONTROL__GC_MEM_SEL___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_GC_RAM_CONTROL__GC_MEM_SEL___S 15 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_GC_RAM_CONTROL__RXDCCAL_GAIN_TBL_SEL___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_GC_RAM_CONTROL__RXDCCAL_GAIN_TBL_SEL___S 14 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_GC_RAM_CONTROL___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_GC_RAM_CONTROL___S 14 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0 (0x005E008C) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__SLM_XLNA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__XLNA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__LNA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__GM_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__TIA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__BQ_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__SLM_XLNA_GAIN_OV___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__SLM_XLNA_GAIN_OV___S 5 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__XLNA_GAIN_OV___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__XLNA_GAIN_OV___S 4 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__LNA_GAIN_OV___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__LNA_GAIN_OV___S 3 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__GM_GAIN_OV___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__GM_GAIN_OV___S 2 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__TIA_GAIN_OV___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__TIA_GAIN_OV___S 1 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__BQ_GAIN_OV___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0__BQ_GAIN_OV___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1 (0x005E0090) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__XLNA_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__LNA_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__GM_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__TIA_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__SLM_XLNA_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__BQ_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__XLNA_GAIN_OVD___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__XLNA_GAIN_OVD___S 15 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__LNA_GAIN_OVD___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__LNA_GAIN_OVD___S 12 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__GM_GAIN_OVD___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__GM_GAIN_OVD___S 9 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__TIA_GAIN_OVD___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__TIA_GAIN_OVD___S 7 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__SLM_XLNA_GAIN_OVD___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__SLM_XLNA_GAIN_OVD___S 5 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__BQ_GAIN_OVD___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1__BQ_GAIN_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1___M 0x0000FFBF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_GAIN_OV_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0 (0x005E0094) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_I_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_Q_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_I_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_Q_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OV___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OV___S 25 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OV___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OV___S 24 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_I_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_I_OV___S 23 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_Q_OV___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_Q_OV___S 22 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OVD___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OVD___S 20 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OVD___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OVD___S 18 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_I_OVD___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_I_OVD___S 9 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_Q_OVD___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_Q_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RX_DCOC_OV_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0 (0x005E0098) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__IPA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__DAC_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__TX_PWR_LV_LAA_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__TX_PWR_LV_N79_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__BBF_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__UPC_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__DA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__XPA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__IPA_GAIN_OV___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__IPA_GAIN_OV___S 7 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__DAC_GAIN_OV___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__DAC_GAIN_OV___S 6 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__TX_PWR_LV_LAA_OV___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__TX_PWR_LV_LAA_OV___S 5 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__TX_PWR_LV_N79_OV___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__TX_PWR_LV_N79_OV___S 4 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__BBF_GAIN_OV___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__BBF_GAIN_OV___S 3 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__UPC_GAIN_OV___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__UPC_GAIN_OV___S 2 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__DA_GAIN_OV___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__DA_GAIN_OV___S 1 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__XPA_GAIN_OV___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0__XPA_GAIN_OV___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1 (0x005E009C) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__IPA_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__DAC_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__TX_PWR_LV_LAA_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__TX_PWR_LV_N79_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__BBF_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__UPC_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__DA_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__XPA_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__IPA_GAIN_OVD___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__IPA_GAIN_OVD___S 23 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__DAC_GAIN_OVD___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__DAC_GAIN_OVD___S 20 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__TX_PWR_LV_LAA_OVD___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__TX_PWR_LV_LAA_OVD___S 19 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__TX_PWR_LV_N79_OVD___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__TX_PWR_LV_N79_OVD___S 18 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__BBF_GAIN_OVD___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__BBF_GAIN_OVD___S 12 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__UPC_GAIN_OVD___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__UPC_GAIN_OVD___S 9 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__DA_GAIN_OVD___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__DA_GAIN_OVD___S 4 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__XPA_GAIN_OVD___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1__XPA_GAIN_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_GAIN_OV_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0 (0x005E00A0) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_I_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_Q_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_I_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_Q_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_I_OV___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_I_OV___S 19 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_Q_OV___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_Q_OV___S 18 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_I_OVD___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_I_OVD___S 7 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_Q_OVD___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_Q_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0___M 0x000C3FFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_TX_DCOC_OV_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_IM2_0 (0x005E00A4) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_IM2_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_IM2_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_IM2_0__IM2_EN_MC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_IM2_0__IM2_EN_MC_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_IM2_0__IM2_EN_MC_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_IM2_0___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_IM2_0___S 30 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC (0x005E00A8) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC__RO_RX_DCOC_ADDR___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC__RO_RX_DCOC_RANGE_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC__RO_RX_DCOC_RANGE_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC__RO_RX_DCOC_RES_I___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC__RO_RX_DCOC_RES_Q___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC__RO_RX_DCOC_ADDR___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC__RO_RX_DCOC_ADDR___S 22 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC__RO_RX_DCOC_RANGE_I___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC__RO_RX_DCOC_RANGE_I___S 20 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC__RO_RX_DCOC_RANGE_Q___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC__RO_RX_DCOC_RANGE_Q___S 18 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC__RO_RX_DCOC_RES_I___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC__RO_RX_DCOC_RES_I___S 9 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC__RO_RX_DCOC_RES_Q___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC__RO_RX_DCOC_RES_Q___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_DCOC___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_DCOC (0x005E00AC) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_DCOC___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_DCOC___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_DCOC__RO_TX_DCOC_ADDR___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_DCOC__RO_TX_DCOC_RES_I___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_DCOC__RO_TX_DCOC_RES_Q___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_DCOC__RO_TX_DCOC_ADDR___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_DCOC__RO_TX_DCOC_ADDR___S 16 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_DCOC__RO_TX_DCOC_RES_I___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_DCOC__RO_TX_DCOC_RES_I___S 7 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_DCOC__RO_TX_DCOC_RES_Q___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_DCOC__RO_TX_DCOC_RES_Q___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_DCOC___M 0x007F3FFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_DCOC___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN (0x005E00B0) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_RX_GAIN_ADDR___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_XLNA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_LNA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_GM_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_TIA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_SLM_XLNA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_BQ_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_RX_GAIN_ADDR___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_RX_GAIN_ADDR___S 16 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_XLNA_GAIN___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_XLNA_GAIN___S 15 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_LNA_GAIN___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_LNA_GAIN___S 12 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_GM_GAIN___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_GM_GAIN___S 9 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_TIA_GAIN___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_TIA_GAIN___S 7 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_SLM_XLNA_GAIN___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_SLM_XLNA_GAIN___S 5 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_BQ_GAIN___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN__RO_BQ_GAIN___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN___M 0x00FFFFBF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_RX_GAIN___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0 (0x005E00B4) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_IPA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_DAC_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_TX_PWR_LV_LAA___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_TX_PWR_LV_N79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_BBF_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_UPC_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_DA_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_XPA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_IPA_GAIN___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_IPA_GAIN___S 23 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_DAC_GAIN___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_DAC_GAIN___S 20 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_TX_PWR_LV_LAA___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_TX_PWR_LV_LAA___S 19 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_TX_PWR_LV_N79___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_TX_PWR_LV_N79___S 18 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_BBF_GAIN___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_BBF_GAIN___S 12 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_UPC_GAIN___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_UPC_GAIN___S 9 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_DA_GAIN___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_DA_GAIN___S 4 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_XPA_GAIN___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0__RO_XPA_GAIN___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_1 (0x005E00B8) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_1__RO_TX_GAIN_ADDR___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_1__RO_RX_IDX___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_1__RO_TX_IDX___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_1__RO_TX_GAIN_ADDR___M 0x7F000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_1__RO_TX_GAIN_ADDR___S 24 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_1__RO_RX_IDX___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_1__RO_RX_IDX___S 16 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_1__RO_TX_IDX___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_1__RO_TX_IDX___S 8 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_1___M 0x7FFF3F00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_RO_TX_GAIN_1___S 8 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_0 (0x005E00C0) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_0__TX_DCOC_CAL_OFFSET_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_0__TX_DCOC_CAL_OFFSET_0___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_0__TX_DCOC_CAL_OFFSET_0___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_0___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_0___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_1 (0x005E00C4) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_1__TX_DCOC_CAL_OFFSET_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_1__TX_DCOC_CAL_OFFSET_1___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_1__TX_DCOC_CAL_OFFSET_1___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_1___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_1___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_2 (0x005E00C8) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_2__TX_DCOC_CAL_OFFSET_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_2__TX_DCOC_CAL_OFFSET_2___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_2__TX_DCOC_CAL_OFFSET_2___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_2___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_2___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_3 (0x005E00CC) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_3__TX_DCOC_CAL_OFFSET_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_3__TX_DCOC_CAL_OFFSET_3___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_3__TX_DCOC_CAL_OFFSET_3___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_3___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_3___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_4 (0x005E00D0) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_4__TX_DCOC_CAL_OFFSET_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_4__TX_DCOC_CAL_OFFSET_4___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_4__TX_DCOC_CAL_OFFSET_4___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_4___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_4___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_5 (0x005E00D4) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_5__TX_DCOC_CAL_OFFSET_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_5__TX_DCOC_CAL_OFFSET_5___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_5__TX_DCOC_CAL_OFFSET_5___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_5___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_5___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_6 (0x005E00D8) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_6__TX_DCOC_CAL_OFFSET_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_6__TX_DCOC_CAL_OFFSET_6___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_6__TX_DCOC_CAL_OFFSET_6___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_6___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_6___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_7 (0x005E00DC) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_7__TX_DCOC_CAL_OFFSET_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_7__TX_DCOC_CAL_OFFSET_7___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_7__TX_DCOC_CAL_OFFSET_7___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_7___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_7___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_8 (0x005E00E0) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_8__TX_DCOC_CAL_OFFSET_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_8__TX_DCOC_CAL_OFFSET_8___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_8__TX_DCOC_CAL_OFFSET_8___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_8___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_8___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_9 (0x005E00E4) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_9__TX_DCOC_CAL_OFFSET_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_9__TX_DCOC_CAL_OFFSET_9___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_9__TX_DCOC_CAL_OFFSET_9___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_9___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_9___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_10 (0x005E00E8) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_10__TX_DCOC_CAL_OFFSET_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_10__TX_DCOC_CAL_OFFSET_10___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_10__TX_DCOC_CAL_OFFSET_10___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_10___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_10___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_11 (0x005E00EC) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_11__TX_DCOC_CAL_OFFSET_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_11__TX_DCOC_CAL_OFFSET_11___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_11__TX_DCOC_CAL_OFFSET_11___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_11___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_11___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_12 (0x005E00F0) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_12__TX_DCOC_CAL_OFFSET_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_12__TX_DCOC_CAL_OFFSET_12___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_12__TX_DCOC_CAL_OFFSET_12___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_12___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_12___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_13 (0x005E00F4) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_13__TX_DCOC_CAL_OFFSET_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_13__TX_DCOC_CAL_OFFSET_13___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_13__TX_DCOC_CAL_OFFSET_13___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_13___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_13___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_14 (0x005E00F8) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_14__TX_DCOC_CAL_OFFSET_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_14__TX_DCOC_CAL_OFFSET_14___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_14__TX_DCOC_CAL_OFFSET_14___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_14___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_14___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_15 (0x005E00FC) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_15__TX_DCOC_CAL_OFFSET_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_15__TX_DCOC_CAL_OFFSET_15___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_15__TX_DCOC_CAL_OFFSET_15___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_15___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_15___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_16 (0x005E0100) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_16___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_16__TX_DCOC_CAL_OFFSET_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_16__TX_DCOC_CAL_OFFSET_16___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_16__TX_DCOC_CAL_OFFSET_16___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_16___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_16___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_17 (0x005E0104) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_17___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_17__TX_DCOC_CAL_OFFSET_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_17__TX_DCOC_CAL_OFFSET_17___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_17__TX_DCOC_CAL_OFFSET_17___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_17___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_17___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_18 (0x005E0108) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_18___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_18__TX_DCOC_CAL_OFFSET_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_18__TX_DCOC_CAL_OFFSET_18___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_18__TX_DCOC_CAL_OFFSET_18___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_18___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_18___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_19 (0x005E010C) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_19___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_19__TX_DCOC_CAL_OFFSET_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_19__TX_DCOC_CAL_OFFSET_19___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_19__TX_DCOC_CAL_OFFSET_19___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_19___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_19___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_20 (0x005E0110) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_20___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_20__TX_DCOC_CAL_OFFSET_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_20__TX_DCOC_CAL_OFFSET_20___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_20__TX_DCOC_CAL_OFFSET_20___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_20___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_20___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_21 (0x005E0114) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_21___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_21__TX_DCOC_CAL_OFFSET_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_21__TX_DCOC_CAL_OFFSET_21___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_21__TX_DCOC_CAL_OFFSET_21___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_21___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_21___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_22 (0x005E0118) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_22___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_22__TX_DCOC_CAL_OFFSET_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_22__TX_DCOC_CAL_OFFSET_22___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_22__TX_DCOC_CAL_OFFSET_22___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_22___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_22___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_23 (0x005E011C) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_23___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_23__TX_DCOC_CAL_OFFSET_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_23__TX_DCOC_CAL_OFFSET_23___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_23__TX_DCOC_CAL_OFFSET_23___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_23___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_23___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_24 (0x005E0120) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_24___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_24__TX_DCOC_CAL_OFFSET_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_24__TX_DCOC_CAL_OFFSET_24___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_24__TX_DCOC_CAL_OFFSET_24___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_24___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_24___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_25 (0x005E0124) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_25___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_25__TX_DCOC_CAL_OFFSET_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_25__TX_DCOC_CAL_OFFSET_25___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_25__TX_DCOC_CAL_OFFSET_25___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_25___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_25___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_26 (0x005E0128) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_26___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_26__TX_DCOC_CAL_OFFSET_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_26__TX_DCOC_CAL_OFFSET_26___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_26__TX_DCOC_CAL_OFFSET_26___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_26___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_26___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_27 (0x005E012C) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_27___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_27__TX_DCOC_CAL_OFFSET_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_27__TX_DCOC_CAL_OFFSET_27___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_27__TX_DCOC_CAL_OFFSET_27___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_27___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_27___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_28 (0x005E0130) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_28___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_28__TX_DCOC_CAL_OFFSET_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_28__TX_DCOC_CAL_OFFSET_28___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_28__TX_DCOC_CAL_OFFSET_28___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_28___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_28___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_29 (0x005E0134) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_29___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_29__TX_DCOC_CAL_OFFSET_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_29__TX_DCOC_CAL_OFFSET_29___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_29__TX_DCOC_CAL_OFFSET_29___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_29___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_29___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_30 (0x005E0138) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_30___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_30__TX_DCOC_CAL_OFFSET_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_30__TX_DCOC_CAL_OFFSET_30___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_30__TX_DCOC_CAL_OFFSET_30___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_30___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_30___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_31 (0x005E013C) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_31___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_31__TX_DCOC_CAL_OFFSET_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_31__TX_DCOC_CAL_OFFSET_31___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_31__TX_DCOC_CAL_OFFSET_31___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_31___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_31___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_32 (0x005E0140) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_32___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_32___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_32__TX_DCOC_CAL_OFFSET_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_32__TX_DCOC_CAL_OFFSET_32___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_32__TX_DCOC_CAL_OFFSET_32___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_32___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_32___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_33 (0x005E0144) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_33___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_33___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_33__TX_DCOC_CAL_OFFSET_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_33__TX_DCOC_CAL_OFFSET_33___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_33__TX_DCOC_CAL_OFFSET_33___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_33___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_33___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_34 (0x005E0148) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_34___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_34___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_34__TX_DCOC_CAL_OFFSET_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_34__TX_DCOC_CAL_OFFSET_34___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_34__TX_DCOC_CAL_OFFSET_34___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_34___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_34___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_35 (0x005E014C) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_35___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_35___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_35__TX_DCOC_CAL_OFFSET_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_35__TX_DCOC_CAL_OFFSET_35___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_35__TX_DCOC_CAL_OFFSET_35___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_35___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_35___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_36 (0x005E0150) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_36___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_36___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_36__TX_DCOC_CAL_OFFSET_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_36__TX_DCOC_CAL_OFFSET_36___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_36__TX_DCOC_CAL_OFFSET_36___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_36___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_36___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_37 (0x005E0154) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_37___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_37___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_37__TX_DCOC_CAL_OFFSET_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_37__TX_DCOC_CAL_OFFSET_37___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_37__TX_DCOC_CAL_OFFSET_37___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_37___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_37___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_38 (0x005E0158) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_38___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_38___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_38__TX_DCOC_CAL_OFFSET_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_38__TX_DCOC_CAL_OFFSET_38___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_38__TX_DCOC_CAL_OFFSET_38___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_38___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_38___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_39 (0x005E015C) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_39___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_39___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_39__TX_DCOC_CAL_OFFSET_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_39__TX_DCOC_CAL_OFFSET_39___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_39__TX_DCOC_CAL_OFFSET_39___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_39___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_39___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_40 (0x005E0160) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_40___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_40___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_40__TX_DCOC_CAL_OFFSET_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_40__TX_DCOC_CAL_OFFSET_40___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_40__TX_DCOC_CAL_OFFSET_40___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_40___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_40___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_41 (0x005E0164) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_41___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_41___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_41__TX_DCOC_CAL_OFFSET_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_41__TX_DCOC_CAL_OFFSET_41___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_41__TX_DCOC_CAL_OFFSET_41___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_41___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_41___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_42 (0x005E0168) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_42___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_42___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_42__TX_DCOC_CAL_OFFSET_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_42__TX_DCOC_CAL_OFFSET_42___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_42__TX_DCOC_CAL_OFFSET_42___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_42___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_42___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_43 (0x005E016C) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_43___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_43___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_43__TX_DCOC_CAL_OFFSET_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_43__TX_DCOC_CAL_OFFSET_43___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_43__TX_DCOC_CAL_OFFSET_43___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_43___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_43___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_44 (0x005E0170) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_44___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_44___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_44__TX_DCOC_CAL_OFFSET_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_44__TX_DCOC_CAL_OFFSET_44___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_44__TX_DCOC_CAL_OFFSET_44___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_44___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_44___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_45 (0x005E0174) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_45___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_45___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_45__TX_DCOC_CAL_OFFSET_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_45__TX_DCOC_CAL_OFFSET_45___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_45__TX_DCOC_CAL_OFFSET_45___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_45___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_45___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_46 (0x005E0178) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_46___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_46___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_46__TX_DCOC_CAL_OFFSET_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_46__TX_DCOC_CAL_OFFSET_46___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_46__TX_DCOC_CAL_OFFSET_46___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_46___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_46___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_47 (0x005E017C) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_47___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_47___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_47__TX_DCOC_CAL_OFFSET_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_47__TX_DCOC_CAL_OFFSET_47___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_47__TX_DCOC_CAL_OFFSET_47___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_47___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_47___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_48 (0x005E0180) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_48___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_48___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_48__TX_DCOC_CAL_OFFSET_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_48__TX_DCOC_CAL_OFFSET_48___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_48__TX_DCOC_CAL_OFFSET_48___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_48___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_48___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_49 (0x005E0184) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_49___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_49___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_49__TX_DCOC_CAL_OFFSET_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_49__TX_DCOC_CAL_OFFSET_49___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_49__TX_DCOC_CAL_OFFSET_49___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_49___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_49___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_50 (0x005E0188) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_50___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_50___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_50__TX_DCOC_CAL_OFFSET_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_50__TX_DCOC_CAL_OFFSET_50___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_50__TX_DCOC_CAL_OFFSET_50___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_50___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_50___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_51 (0x005E018C) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_51___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_51___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_51__TX_DCOC_CAL_OFFSET_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_51__TX_DCOC_CAL_OFFSET_51___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_51__TX_DCOC_CAL_OFFSET_51___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_51___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_51___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_52 (0x005E0190) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_52___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_52___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_52__TX_DCOC_CAL_OFFSET_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_52__TX_DCOC_CAL_OFFSET_52___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_52__TX_DCOC_CAL_OFFSET_52___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_52___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_52___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_53 (0x005E0194) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_53___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_53___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_53__TX_DCOC_CAL_OFFSET_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_53__TX_DCOC_CAL_OFFSET_53___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_53__TX_DCOC_CAL_OFFSET_53___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_53___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_53___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_54 (0x005E0198) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_54___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_54___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_54__TX_DCOC_CAL_OFFSET_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_54__TX_DCOC_CAL_OFFSET_54___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_54__TX_DCOC_CAL_OFFSET_54___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_54___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_54___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_55 (0x005E019C) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_55___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_55___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_55__TX_DCOC_CAL_OFFSET_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_55__TX_DCOC_CAL_OFFSET_55___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_55__TX_DCOC_CAL_OFFSET_55___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_55___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_55___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_56 (0x005E01A0) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_56___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_56___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_56__TX_DCOC_CAL_OFFSET_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_56__TX_DCOC_CAL_OFFSET_56___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_56__TX_DCOC_CAL_OFFSET_56___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_56___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_56___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_57 (0x005E01A4) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_57___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_57___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_57__TX_DCOC_CAL_OFFSET_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_57__TX_DCOC_CAL_OFFSET_57___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_57__TX_DCOC_CAL_OFFSET_57___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_57___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_57___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_58 (0x005E01A8) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_58___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_58___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_58__TX_DCOC_CAL_OFFSET_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_58__TX_DCOC_CAL_OFFSET_58___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_58__TX_DCOC_CAL_OFFSET_58___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_58___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_58___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_59 (0x005E01AC) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_59___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_59___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_59__TX_DCOC_CAL_OFFSET_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_59__TX_DCOC_CAL_OFFSET_59___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_59__TX_DCOC_CAL_OFFSET_59___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_59___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_59___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_60 (0x005E01B0) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_60___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_60___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_60__TX_DCOC_CAL_OFFSET_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_60__TX_DCOC_CAL_OFFSET_60___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_60__TX_DCOC_CAL_OFFSET_60___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_60___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_60___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_61 (0x005E01B4) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_61___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_61___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_61__TX_DCOC_CAL_OFFSET_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_61__TX_DCOC_CAL_OFFSET_61___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_61__TX_DCOC_CAL_OFFSET_61___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_61___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_61___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_62 (0x005E01B8) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_62___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_62___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_62__TX_DCOC_CAL_OFFSET_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_62__TX_DCOC_CAL_OFFSET_62___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_62__TX_DCOC_CAL_OFFSET_62___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_62___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_62___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_63 (0x005E01BC) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_63___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_63___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_63__TX_DCOC_CAL_OFFSET_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_63__TX_DCOC_CAL_OFFSET_63___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_63__TX_DCOC_CAL_OFFSET_63___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_63___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH0_LUT_63___S 26 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_TESTREG (0x005E1000) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_TESTREG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_TESTREG___POR 0x44FE2111 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_TESTREG__TESTREG___POR 0x44FE2111 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_TESTREG__TESTREG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_TESTREG__TESTREG___S 0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_TESTREG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_TESTREG___S 0 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL (0x005E1004) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL__FCS_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OV___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OVD___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OVD___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OV___S 27 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OVD___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OVD___S 24 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL__FCS_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL__FCS_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LUT_IDX_SEL___S 22 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_1_0 (0x005E1008) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_1_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_1_0___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_1_0__LNA_LOAD_C_0___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_1_0__LNA_LOAD_C_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_1_0__LNA_LOAD_C_0___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_1_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_1_0___S 29 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_1_1 (0x005E100C) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_1_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_1_1___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_1_1__LNA_LOAD_C_1___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_1_1__LNA_LOAD_C_1___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_1_1__LNA_LOAD_C_1___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_1_1___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_1_1___S 29 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0 (0x005E1010) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0___POR 0x60A25480 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_RMATCH_0___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_GAINA_0___POR 0x5 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_LOAD_R_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_OTA_EN_0___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_BIAS_0___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_AUX_CAP_0___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__BYPS_HG_0___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_MAINI_VREF_EN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_MAIN_EN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_AUX_EN_0___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_SH_GAIN_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_RMATCH_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_RMATCH_0___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_GAINA_0___M 0x01E00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_GAINA_0___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_LOAD_R_0___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_LOAD_R_0___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_OTA_EN_0___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_OTA_EN_0___S 17 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_BIAS_0___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_BIAS_0___S 13 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_AUX_CAP_0___M 0x00001800 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_AUX_CAP_0___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__BYPS_HG_0___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__BYPS_HG_0___S 10 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_MAINI_VREF_EN_0___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_MAINI_VREF_EN_0___S 9 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_MAIN_EN_0___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_MAIN_EN_0___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_AUX_EN_0___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_AUX_EN_0___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_SH_GAIN_0___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0__LNA_SH_GAIN_0___S 0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_0___S 0 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1 (0x005E1014) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1___POR 0x60E24480 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_RMATCH_1___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_GAINA_1___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_LOAD_R_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_OTA_EN_1___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_BIAS_1___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_AUX_CAP_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__BYPS_HG_1___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_MAINI_VREF_EN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_MAIN_EN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_AUX_EN_1___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_SH_GAIN_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_RMATCH_1___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_RMATCH_1___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_GAINA_1___M 0x01E00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_GAINA_1___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_LOAD_R_1___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_LOAD_R_1___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_OTA_EN_1___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_OTA_EN_1___S 17 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_BIAS_1___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_BIAS_1___S 13 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_AUX_CAP_1___M 0x00001800 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_AUX_CAP_1___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__BYPS_HG_1___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__BYPS_HG_1___S 10 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_MAINI_VREF_EN_1___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_MAINI_VREF_EN_1___S 9 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_MAIN_EN_1___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_MAIN_EN_1___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_AUX_EN_1___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_AUX_EN_1___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_SH_GAIN_1___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1__LNA_SH_GAIN_1___S 0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_1___S 0 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2 (0x005E1018) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2___POR 0x601E030A +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_RMATCH_2___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_GAINA_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_LOAD_R_2___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_OTA_EN_2___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_BIAS_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_AUX_CAP_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__BYPS_HG_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_MAINI_VREF_EN_2___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_MAIN_EN_2___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_AUX_EN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_SH_GAIN_2___POR 0x0A +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_RMATCH_2___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_RMATCH_2___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_GAINA_2___M 0x01E00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_GAINA_2___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_LOAD_R_2___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_LOAD_R_2___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_OTA_EN_2___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_OTA_EN_2___S 17 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_BIAS_2___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_BIAS_2___S 13 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_AUX_CAP_2___M 0x00001800 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_AUX_CAP_2___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__BYPS_HG_2___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__BYPS_HG_2___S 10 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_MAINI_VREF_EN_2___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_MAINI_VREF_EN_2___S 9 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_MAIN_EN_2___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_MAIN_EN_2___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_AUX_EN_2___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_AUX_EN_2___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_SH_GAIN_2___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2__LNA_SH_GAIN_2___S 0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_2___S 0 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3 (0x005E101C) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3___POR 0x60022304 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_RMATCH_3___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_GAINA_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_LOAD_R_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_OTA_EN_3___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_BIAS_3___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_AUX_CAP_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__BYPS_HG_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_MAINI_VREF_EN_3___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_MAIN_EN_3___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_AUX_EN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_SH_GAIN_3___POR 0x04 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_RMATCH_3___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_RMATCH_3___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_GAINA_3___M 0x01E00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_GAINA_3___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_LOAD_R_3___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_LOAD_R_3___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_OTA_EN_3___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_OTA_EN_3___S 17 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_BIAS_3___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_BIAS_3___S 13 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_AUX_CAP_3___M 0x00001800 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_AUX_CAP_3___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__BYPS_HG_3___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__BYPS_HG_3___S 10 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_MAINI_VREF_EN_3___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_MAINI_VREF_EN_3___S 9 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_MAIN_EN_3___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_MAIN_EN_3___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_AUX_EN_3___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_AUX_EN_3___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_SH_GAIN_3___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3__LNA_SH_GAIN_3___S 0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_3___S 0 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4 (0x005E1020) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4___POR 0x60022309 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_RMATCH_4___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_GAINA_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_LOAD_R_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_OTA_EN_4___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_BIAS_4___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_AUX_CAP_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__BYPS_HG_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_MAINI_VREF_EN_4___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_MAIN_EN_4___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_AUX_EN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_SH_GAIN_4___POR 0x09 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_RMATCH_4___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_RMATCH_4___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_GAINA_4___M 0x01E00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_GAINA_4___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_LOAD_R_4___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_LOAD_R_4___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_OTA_EN_4___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_OTA_EN_4___S 17 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_BIAS_4___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_BIAS_4___S 13 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_AUX_CAP_4___M 0x00001800 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_AUX_CAP_4___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__BYPS_HG_4___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__BYPS_HG_4___S 10 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_MAINI_VREF_EN_4___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_MAINI_VREF_EN_4___S 9 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_MAIN_EN_4___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_MAIN_EN_4___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_AUX_EN_4___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_AUX_EN_4___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_SH_GAIN_4___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4__LNA_SH_GAIN_4___S 0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_4___S 0 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5 (0x005E1024) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5___POR 0x60022312 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_RMATCH_5___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_GAINA_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_LOAD_R_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_OTA_EN_5___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_BIAS_5___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_AUX_CAP_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__BYPS_HG_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_MAINI_VREF_EN_5___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_MAIN_EN_5___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_AUX_EN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_SH_GAIN_5___POR 0x12 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_RMATCH_5___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_RMATCH_5___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_GAINA_5___M 0x01E00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_GAINA_5___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_LOAD_R_5___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_LOAD_R_5___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_OTA_EN_5___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_OTA_EN_5___S 17 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_BIAS_5___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_BIAS_5___S 13 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_AUX_CAP_5___M 0x00001800 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_AUX_CAP_5___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__BYPS_HG_5___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__BYPS_HG_5___S 10 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_MAINI_VREF_EN_5___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_MAINI_VREF_EN_5___S 9 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_MAIN_EN_5___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_MAIN_EN_5___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_AUX_EN_5___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_AUX_EN_5___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_SH_GAIN_5___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5__LNA_SH_GAIN_5___S 0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_5___S 0 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6 (0x005E1028) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6___POR 0x4002231C +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_RMATCH_6___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_GAINA_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_LOAD_R_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_OTA_EN_6___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_BIAS_6___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_AUX_CAP_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__BYPS_HG_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_MAINI_VREF_EN_6___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_MAIN_EN_6___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_AUX_EN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_SH_GAIN_6___POR 0x1C +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_RMATCH_6___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_RMATCH_6___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_GAINA_6___M 0x01E00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_GAINA_6___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_LOAD_R_6___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_LOAD_R_6___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_OTA_EN_6___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_OTA_EN_6___S 17 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_BIAS_6___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_BIAS_6___S 13 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_AUX_CAP_6___M 0x00001800 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_AUX_CAP_6___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__BYPS_HG_6___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__BYPS_HG_6___S 10 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_MAINI_VREF_EN_6___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_MAINI_VREF_EN_6___S 9 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_MAIN_EN_6___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_MAIN_EN_6___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_AUX_EN_6___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_AUX_EN_6___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_SH_GAIN_6___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6__LNA_SH_GAIN_6___S 0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_6___S 0 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7 (0x005E102C) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7___POR 0x00026339 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_RMATCH_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_GAINA_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_LOAD_R_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_OTA_EN_7___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_BIAS_7___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_AUX_CAP_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__BYPS_HG_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_MAINI_VREF_EN_7___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_MAIN_EN_7___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_AUX_EN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_SH_GAIN_7___POR 0x39 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_RMATCH_7___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_RMATCH_7___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_GAINA_7___M 0x01E00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_GAINA_7___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_LOAD_R_7___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_LOAD_R_7___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_OTA_EN_7___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_OTA_EN_7___S 17 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_BIAS_7___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_BIAS_7___S 13 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_AUX_CAP_7___M 0x00001800 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_AUX_CAP_7___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__BYPS_HG_7___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__BYPS_HG_7___S 10 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_MAINI_VREF_EN_7___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_MAINI_VREF_EN_7___S 9 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_MAIN_EN_7___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_MAIN_EN_7___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_AUX_EN_7___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_AUX_EN_7___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_SH_GAIN_7___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7__LNA_SH_GAIN_7___S 0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_LNA_0_7___S 0 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0 (0x005E1030) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0___POR 0x0A320000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0__WL_GM_BYP_EN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0__WL_GM_SH_GAIN_0___POR 0x05 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0__WL_GMP_GAIN_0___POR 0x06 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0__WL_GM_IBIAS_CTRL_0___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0__WL_GM_BYP_EN_0___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0__WL_GM_BYP_EN_0___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0__WL_GM_SH_GAIN_0___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0__WL_GM_SH_GAIN_0___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0__WL_GMP_GAIN_0___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0__WL_GMP_GAIN_0___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0__WL_GM_IBIAS_CTRL_0___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0__WL_GM_IBIAS_CTRL_0___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_0___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_1 (0x005E1034) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_1___POR 0x0A320000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_1__WL_GM_BYP_EN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_1__WL_GM_SH_GAIN_1___POR 0x05 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_1__WL_GMP_GAIN_1___POR 0x06 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_1__WL_GM_IBIAS_CTRL_1___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_1__WL_GM_BYP_EN_1___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_1__WL_GM_BYP_EN_1___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_1__WL_GM_SH_GAIN_1___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_1__WL_GM_SH_GAIN_1___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_1__WL_GMP_GAIN_1___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_1__WL_GMP_GAIN_1___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_1__WL_GM_IBIAS_CTRL_1___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_1__WL_GM_IBIAS_CTRL_1___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_1___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_1___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_2 (0x005E1038) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_2___POR 0x14520000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_2__WL_GM_BYP_EN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_2__WL_GM_SH_GAIN_2___POR 0x0A +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_2__WL_GMP_GAIN_2___POR 0x0A +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_2__WL_GM_IBIAS_CTRL_2___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_2__WL_GM_BYP_EN_2___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_2__WL_GM_BYP_EN_2___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_2__WL_GM_SH_GAIN_2___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_2__WL_GM_SH_GAIN_2___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_2__WL_GMP_GAIN_2___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_2__WL_GMP_GAIN_2___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_2__WL_GM_IBIAS_CTRL_2___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_2__WL_GM_IBIAS_CTRL_2___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_2___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_2___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_3 (0x005E103C) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_3___POR 0x1E7A0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_3__WL_GM_BYP_EN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_3__WL_GM_SH_GAIN_3___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_3__WL_GMP_GAIN_3___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_3__WL_GM_IBIAS_CTRL_3___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_3__WL_GM_BYP_EN_3___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_3__WL_GM_BYP_EN_3___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_3__WL_GM_SH_GAIN_3___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_3__WL_GM_SH_GAIN_3___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_3__WL_GMP_GAIN_3___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_3__WL_GMP_GAIN_3___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_3__WL_GM_IBIAS_CTRL_3___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_3__WL_GM_IBIAS_CTRL_3___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_3___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_3___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_4 (0x005E1040) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_4___POR 0x28930000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_4__WL_GM_BYP_EN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_4__WL_GM_SH_GAIN_4___POR 0x14 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_4__WL_GMP_GAIN_4___POR 0x12 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_4__WL_GM_IBIAS_CTRL_4___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_4__WL_GM_BYP_EN_4___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_4__WL_GM_BYP_EN_4___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_4__WL_GM_SH_GAIN_4___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_4__WL_GM_SH_GAIN_4___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_4__WL_GMP_GAIN_4___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_4__WL_GMP_GAIN_4___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_4__WL_GM_IBIAS_CTRL_4___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_4__WL_GM_IBIAS_CTRL_4___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_4___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_4___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_5 (0x005E1044) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_5___POR 0x3CC20000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_5__WL_GM_BYP_EN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_5__WL_GM_SH_GAIN_5___POR 0x1E +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_5__WL_GMP_GAIN_5___POR 0x18 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_5__WL_GM_IBIAS_CTRL_5___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_5__WL_GM_BYP_EN_5___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_5__WL_GM_BYP_EN_5___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_5__WL_GM_SH_GAIN_5___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_5__WL_GM_SH_GAIN_5___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_5__WL_GMP_GAIN_5___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_5__WL_GMP_GAIN_5___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_5__WL_GM_IBIAS_CTRL_5___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_5__WL_GM_IBIAS_CTRL_5___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_5___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_5___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_6 (0x005E1048) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_6___POR 0x65A90000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_6__WL_GM_BYP_EN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_6__WL_GM_SH_GAIN_6___POR 0x32 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_6__WL_GMP_GAIN_6___POR 0x35 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_6__WL_GM_IBIAS_CTRL_6___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_6__WL_GM_BYP_EN_6___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_6__WL_GM_BYP_EN_6___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_6__WL_GM_SH_GAIN_6___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_6__WL_GM_SH_GAIN_6___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_6__WL_GMP_GAIN_6___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_6__WL_GMP_GAIN_6___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_6__WL_GM_IBIAS_CTRL_6___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_6__WL_GM_IBIAS_CTRL_6___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_6___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_6___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_7 (0x005E104C) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_7___POR 0x65A90000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_7__WL_GM_BYP_EN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_7__WL_GM_SH_GAIN_7___POR 0x32 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_7__WL_GMP_GAIN_7___POR 0x35 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_7__WL_GM_IBIAS_CTRL_7___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_7__WL_GM_BYP_EN_7___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_7__WL_GM_BYP_EN_7___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_7__WL_GM_SH_GAIN_7___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_7__WL_GM_SH_GAIN_7___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_7__WL_GMP_GAIN_7___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_7__WL_GMP_GAIN_7___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_7__WL_GM_IBIAS_CTRL_7___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_7__WL_GM_IBIAS_CTRL_7___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_7___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_GM_0_7___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0 (0x005E1080) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_RMATCH_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_RMATCH_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_GAINA_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_GAINA_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_LOAD_R_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_LOAD_R_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_OTA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_BIAS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_BIAS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_AUX_CAP_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_AUX_CAP_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__BYPS_HG_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_MAINI_VREF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_RMATCH_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_RMATCH_OV___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_RMATCH_OVD___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_RMATCH_OVD___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_GAINA_OV___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_GAINA_OV___S 22 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_GAINA_OVD___M 0x003C0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_GAINA_OVD___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_LOAD_R_OV___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_LOAD_R_OV___S 17 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_LOAD_R_OVD___M 0x0001C000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_LOAD_R_OVD___S 14 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_OTA_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_OTA_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_BIAS_OV___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_BIAS_OV___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_BIAS_OVD___M 0x00000780 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_BIAS_OVD___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_AUX_CAP_OV___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_AUX_CAP_OV___S 6 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_AUX_CAP_OVD___M 0x00000030 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_AUX_CAP_OVD___S 4 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__BYPS_HG_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__BYPS_HG_OVS___S 2 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_MAINI_VREF_EN_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0__LNA_MAINI_VREF_EN_OVS___S 0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0___M 0xF07FFFFF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0___S 0 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT (0x005E1084) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_MAIN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_AUX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_SH_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_SH_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_MAIN_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_MAIN_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_AUX_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_AUX_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_SH_GAIN_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_SH_GAIN_OV___S 27 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_SH_GAIN_OVD___M 0x07E00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT__LNA_SH_GAIN_OVD___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV0_EXT___S 21 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1 (0x005E1088) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GM_BYP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GM_SH_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GM_SH_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GMP_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GMP_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GM_IBIAS_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GM_IBIAS_CTRL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GM_BYP_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GM_BYP_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GM_SH_GAIN_OV___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GM_SH_GAIN_OV___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GM_SH_GAIN_OVD___M 0x1F800000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GM_SH_GAIN_OVD___S 23 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GMP_GAIN_OV___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GMP_GAIN_OV___S 22 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GMP_GAIN_OVD___M 0x003F0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GMP_GAIN_OVD___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GM_IBIAS_CTRL_OV___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GM_IBIAS_CTRL_OV___S 15 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GM_IBIAS_CTRL_OVD___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1__WL_GM_IBIAS_CTRL_OVD___S 12 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV1___S 12 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV2 (0x005E108C) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV2__LNA_LOAD_C_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV2__LNA_LOAD_C_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV2__LNA_LOAD_C_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV2__LNA_LOAD_C_OV___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV2__LNA_LOAD_C_OVD___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV2__LNA_LOAD_C_OVD___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV2___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_LUT_OV2___S 28 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0 (0x005E1090) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__LNA_FASTCH_BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__CALRTX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__DPD_IPA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_GM_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_MIX_EN_I_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_MIX_EN_Q_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_RXLO_INBUF25DC1ST_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_RXLO_INBUF25DC2ND_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_RXLO_OBUF25DC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__LNA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_LPMIX_EN_I_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_LPMIX_EN_Q_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__LNA_FASTCH_BIAS_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__LNA_FASTCH_BIAS_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__CALRTX_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__CALRTX_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__DPD_IPA_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__DPD_IPA_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_GM_EN_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_GM_EN_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_MIX_EN_I_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_MIX_EN_I_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_MIX_EN_Q_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_MIX_EN_Q_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_RXLO_INBUF25DC1ST_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_RXLO_INBUF25DC1ST_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_RXLO_INBUF25DC2ND_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_RXLO_INBUF25DC2ND_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_RXLO_OBUF25DC_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_RXLO_OBUF25DC_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__LNA_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__LNA_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_LPMIX_EN_I_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_LPMIX_EN_I_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_LPMIX_EN_Q_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0__WL_LPMIX_EN_Q_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0___M 0xFFFFFF00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV0___S 8 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1 (0x005E1094) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__AGC_PKDET_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__WL_AGC_PKDET_COMP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__AGC_PKDET_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__AGC_PKDET_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__WL_AGC_PKDET_COMP_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__WL_AGC_PKDET_COMP_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OV___S 27 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OVD___M 0x07F00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OVD___S 20 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1___M 0xFFF00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_OV1___S 20 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_RXFE_LUT_IDX_SEL (0x005E1098) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_RXFE_LUT_IDX_SEL___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_RXFE_LUT_IDX_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_RXFE_LUT_IDX_SEL__RO_FCS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN___S 26 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_RXFE_LUT_IDX_SEL__RO_FCS___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_RXFE_LUT_IDX_SEL__RO_FCS___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_RXFE_LUT_IDX_SEL___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_RXFE_LUT_IDX_SEL___S 25 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0 (0x005E109C) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_RMATCH___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_GAINA___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_LOAD_R___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_OTA_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_BIAS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_AUX_CAP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_BYPS_HG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_MAINI_VREF_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_MAIN_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_AUX_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_SH_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_RMATCH___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_RMATCH___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_GAINA___M 0x01E00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_GAINA___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_LOAD_R___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_LOAD_R___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_OTA_EN___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_OTA_EN___S 17 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_BIAS___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_BIAS___S 13 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_AUX_CAP___M 0x00001800 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_AUX_CAP___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_BYPS_HG___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_BYPS_HG___S 10 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_MAINI_VREF_EN___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_MAINI_VREF_EN___S 9 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_MAIN_EN___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_MAIN_EN___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_AUX_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_AUX_EN___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_SH_GAIN___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0__RO_LNA_SH_GAIN___S 0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT0___S 0 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1 (0x005E10A0) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_WL_GM_BYP_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_WL_GM_SH_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_WL_GMP_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_WL_GM_IBIAS_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_WL_GM_BYP_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_WL_GM_BYP_EN___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_WL_GM_SH_GAIN___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_WL_GM_SH_GAIN___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_WL_GMP_GAIN___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_WL_GMP_GAIN___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_WL_GM_IBIAS_CTRL___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1__RO_WL_GM_IBIAS_CTRL___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT1___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT2 (0x005E10A4) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT2__RO_LNA_LOAD_C___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT2__RO_LNA_LOAD_C___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT2__RO_LNA_LOAD_C___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT2___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_WL_RXFE_LUT2___S 29 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0 (0x005E10A8) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0___POR 0xA201E000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__IWL_AGC_PKDET_GAIN___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__D_WL_AGC_PKDET_BW___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__D_WL_AGC_PKDET_DCOC_RANGE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__D_WL_AGC_PKDET_THRES___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__AGC_PKDET_DCOC_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__AGC_PKDET_DCOC_SETT___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__IWL_AGC_PKDET_DCOC_RANGE___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__IWL_AGC_PKDET_GAIN___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__IWL_AGC_PKDET_GAIN___S 30 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__D_WL_AGC_PKDET_BW___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__D_WL_AGC_PKDET_BW___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__D_WL_AGC_PKDET_DCOC_RANGE___M 0x06000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__D_WL_AGC_PKDET_DCOC_RANGE___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__D_WL_AGC_PKDET_THRES___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__D_WL_AGC_PKDET_THRES___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__AGC_PKDET_DCOC_EN___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__AGC_PKDET_DCOC_EN___S 17 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__AGC_PKDET_DCOC_SETT___M 0x0001C000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__AGC_PKDET_DCOC_SETT___S 14 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__IWL_AGC_PKDET_DCOC_RANGE___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0__IWL_AGC_PKDET_DCOC_RANGE___S 12 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0___M 0xE7FFF000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_AGC_CAL_0___S 12 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_AGC_CAL (0x005E10AC) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_AGC_CAL___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_AGC_CAL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_VALID___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_SAT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES_EFFECT___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_VALID___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_VALID___S 15 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_SAT___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_SAT___S 14 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES_EFFECT___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES_EFFECT___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES___S 0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_AGC_CAL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_RO_AGC_CAL___S 0 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0 (0x005E10B0) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0___POR 0x7011C800 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__WL_LNA_IC_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__WL_LNA_IRTT_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__WL_LNA_OTA_BIAS_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__WL_LNA_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__WL_LNA_BIAS_OTA_SHORTR___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__IWL_SEL_2GNOTCH_TUNE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IC_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IPT_CTRL___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IOFFSET_CTRL___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__WL_LNA_IC_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__WL_LNA_IC_EN___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__WL_LNA_IRTT_EN___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__WL_LNA_IRTT_EN___S 30 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__WL_LNA_OTA_BIAS_CTRL___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__WL_LNA_OTA_BIAS_CTRL___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__WL_LNA_ATB_SEL___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__WL_LNA_ATB_SEL___S 27 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__WL_LNA_BIAS_OTA_SHORTR___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__WL_LNA_BIAS_OTA_SHORTR___S 22 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__IWL_SEL_2GNOTCH_TUNE___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__IWL_SEL_2GNOTCH_TUNE___S 20 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IC_CTRL___M 0x000E0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IC_CTRL___S 17 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IPT_CTRL___M 0x0001C000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IPT_CTRL___S 14 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IOFFSET_CTRL___M 0x00003800 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IOFFSET_CTRL___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0___M 0xF87FF800 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_CONTROL0___S 11 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1 (0x005E10B4) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1___POR 0x52000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_GM_IC_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_GM_IRTT_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_GM_CM_IBIAS_CTRL___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_GM_VCM___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_GM_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_AGC_PKDET_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_GM_IC_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_GM_IC_EN___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_GM_IRTT_EN___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_GM_IRTT_EN___S 30 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_GM_CM_IBIAS_CTRL___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_GM_CM_IBIAS_CTRL___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_GM_VCM___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_GM_VCM___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_GM_ATB_SEL___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_GM_ATB_SEL___S 22 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_AGC_PKDET_ATB_SEL___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1__D_WL_AGC_PKDET_ATB_SEL___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL1___S 21 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2 (0x005E10B8) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2___POR 0xFF000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_LSB_I___POR 0xF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_LSB_Q___POR 0xF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_MSB_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_MSB_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_WL_RXLO_ATB_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__WL_CONC_TX_GRANT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_AGC_PKDET_OUT_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_RFPKDET_VREFRNG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_LSB_I___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_LSB_I___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_LSB_Q___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_LSB_Q___S 24 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_MSB_I___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_MSB_I___S 20 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_MSB_Q___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_MSB_Q___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_WL_RXLO_ATB_SEL___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_WL_RXLO_ATB_SEL___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__WL_CONC_TX_GRANT___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__WL_CONC_TX_GRANT___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_AGC_PKDET_OUT_ATB_SEL___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_AGC_PKDET_OUT_ATB_SEL___S 5 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_RFPKDET_VREFRNG___M 0x00000018 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2__D_RFPKDET_VREFRNG___S 3 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2___M 0xFFFFFFB8 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_W_RXFE_CONTROL2___S 3 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_SPARE (0x005E10BC) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_SPARE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_SPARE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_SPARE__D_BT_RXFE_SPARE___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_SPARE__D_WL_RXFE_SPARE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_SPARE__D_BT_RXFE_SPARE___M 0x0003FF00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_SPARE__D_BT_RXFE_SPARE___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_SPARE__D_WL_RXFE_SPARE___M 0x000000FE +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_SPARE__D_WL_RXFE_SPARE___S 1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_SPARE___M 0x0003FFFE +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH0_WL_RXFE_SPARE___S 1 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_TESTREG (0x005E1300) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_TESTREG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_TESTREG___POR 0x33FE2111 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_TESTREG__TESTREG___POR 0x33FE2111 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_TESTREG__TESTREG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_TESTREG__TESTREG___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_TESTREG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_TESTREG___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL (0x005E1304) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__FCS_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OV___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__FCS_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__FCS_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___M 0x00078000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL___M 0xFFFF8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LUT_IDX_SEL___S 15 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_0 (0x005E1308) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_0___POR 0x14500000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE3FLO_0___POR 0x05 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE1FLO_0___POR 0x05 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_0__DA_CTUNE_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE3FLO_0___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE3FLO_0___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE1FLO_0___M 0x03F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE1FLO_0___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_0__DA_CTUNE_0___M 0x0001F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_0__DA_CTUNE_0___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_0___M 0xFFF1F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_0___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_1 (0x005E130C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_1___POR 0x14500000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE3FLO_1___POR 0x05 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE1FLO_1___POR 0x05 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_1__DA_CTUNE_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE3FLO_1___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE3FLO_1___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE1FLO_1___M 0x03F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE1FLO_1___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_1__DA_CTUNE_1___M 0x0001F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_1__DA_CTUNE_1___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_1___M 0xFFF1F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CTUNE_LUT_1___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_0 (0x005E1310) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_0__DA_CELL_EN_0___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_0__DA_CELL_AUX_EN_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_0__DA_CASOFF_BIAS_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_0__DA_HS_CTRL_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_0__DA_CELL_EN_0___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_0__DA_CELL_EN_0___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_0__DA_CELL_AUX_EN_0___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_0__DA_CELL_AUX_EN_0___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_0__DA_CASOFF_BIAS_0___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_0__DA_CASOFF_BIAS_0___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_0__DA_HS_CTRL_0___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_0__DA_HS_CTRL_0___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_0___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_0___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_1 (0x005E1314) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_1__DA_CELL_EN_1___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_1__DA_CELL_AUX_EN_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_1__DA_CASOFF_BIAS_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_1__DA_HS_CTRL_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_1__DA_CELL_EN_1___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_1__DA_CELL_EN_1___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_1__DA_CELL_AUX_EN_1___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_1__DA_CELL_AUX_EN_1___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_1__DA_CASOFF_BIAS_1___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_1__DA_CASOFF_BIAS_1___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_1__DA_HS_CTRL_1___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_1__DA_HS_CTRL_1___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_1___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_1___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_2 (0x005E1318) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_2__DA_CELL_EN_2___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_2__DA_CELL_AUX_EN_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_2__DA_CASOFF_BIAS_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_2__DA_HS_CTRL_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_2__DA_CELL_EN_2___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_2__DA_CELL_EN_2___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_2__DA_CELL_AUX_EN_2___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_2__DA_CELL_AUX_EN_2___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_2__DA_CASOFF_BIAS_2___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_2__DA_CASOFF_BIAS_2___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_2__DA_HS_CTRL_2___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_2__DA_HS_CTRL_2___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_2___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_2___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_3 (0x005E131C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_3__DA_CELL_EN_3___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_3__DA_CELL_AUX_EN_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_3__DA_CASOFF_BIAS_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_3__DA_HS_CTRL_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_3__DA_CELL_EN_3___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_3__DA_CELL_EN_3___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_3__DA_CELL_AUX_EN_3___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_3__DA_CELL_AUX_EN_3___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_3__DA_CASOFF_BIAS_3___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_3__DA_CASOFF_BIAS_3___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_3__DA_HS_CTRL_3___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_3__DA_HS_CTRL_3___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_3___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_3___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_4 (0x005E1320) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_4__DA_CELL_EN_4___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_4__DA_CELL_AUX_EN_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_4__DA_CASOFF_BIAS_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_4__DA_HS_CTRL_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_4__DA_CELL_EN_4___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_4__DA_CELL_EN_4___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_4__DA_CELL_AUX_EN_4___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_4__DA_CELL_AUX_EN_4___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_4__DA_CASOFF_BIAS_4___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_4__DA_CASOFF_BIAS_4___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_4__DA_HS_CTRL_4___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_4__DA_HS_CTRL_4___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_4___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_4___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_5 (0x005E1324) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_5__DA_CELL_EN_5___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_5__DA_CELL_AUX_EN_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_5__DA_CASOFF_BIAS_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_5__DA_HS_CTRL_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_5__DA_CELL_EN_5___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_5__DA_CELL_EN_5___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_5__DA_CELL_AUX_EN_5___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_5__DA_CELL_AUX_EN_5___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_5__DA_CASOFF_BIAS_5___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_5__DA_CASOFF_BIAS_5___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_5__DA_HS_CTRL_5___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_5__DA_HS_CTRL_5___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_5___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_5___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_6 (0x005E1328) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_6___POR 0x04811000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_6__DA_CELL_EN_6___POR 0x009 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_6__DA_CELL_AUX_EN_6___POR 0x02 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_6__DA_CASOFF_BIAS_6___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_6__DA_HS_CTRL_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_6__DA_CELL_EN_6___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_6__DA_CELL_EN_6___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_6__DA_CELL_AUX_EN_6___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_6__DA_CELL_AUX_EN_6___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_6__DA_CASOFF_BIAS_6___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_6__DA_CASOFF_BIAS_6___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_6__DA_HS_CTRL_6___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_6__DA_HS_CTRL_6___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_6___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_6___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_7 (0x005E132C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_7___POR 0x05811000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_7__DA_CELL_EN_7___POR 0x00B +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_7__DA_CELL_AUX_EN_7___POR 0x02 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_7__DA_CASOFF_BIAS_7___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_7__DA_HS_CTRL_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_7__DA_CELL_EN_7___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_7__DA_CELL_EN_7___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_7__DA_CELL_AUX_EN_7___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_7__DA_CELL_AUX_EN_7___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_7__DA_CASOFF_BIAS_7___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_7__DA_CASOFF_BIAS_7___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_7__DA_HS_CTRL_7___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_7__DA_HS_CTRL_7___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_7___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_7___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_8 (0x005E1330) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_8___POR 0x06011000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_8__DA_CELL_EN_8___POR 0x00C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_8__DA_CELL_AUX_EN_8___POR 0x02 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_8__DA_CASOFF_BIAS_8___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_8__DA_HS_CTRL_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_8__DA_CELL_EN_8___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_8__DA_CELL_EN_8___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_8__DA_CELL_AUX_EN_8___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_8__DA_CELL_AUX_EN_8___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_8__DA_CASOFF_BIAS_8___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_8__DA_CASOFF_BIAS_8___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_8__DA_HS_CTRL_8___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_8__DA_HS_CTRL_8___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_8___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_8___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_9 (0x005E1334) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_9___POR 0x09011000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_9__DA_CELL_EN_9___POR 0x012 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_9__DA_CELL_AUX_EN_9___POR 0x02 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_9__DA_CASOFF_BIAS_9___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_9__DA_HS_CTRL_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_9__DA_CELL_EN_9___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_9__DA_CELL_EN_9___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_9__DA_CELL_AUX_EN_9___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_9__DA_CELL_AUX_EN_9___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_9__DA_CASOFF_BIAS_9___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_9__DA_CASOFF_BIAS_9___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_9__DA_HS_CTRL_9___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_9__DA_HS_CTRL_9___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_9___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_9___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_10 (0x005E1338) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_10___POR 0x0A011000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_10__DA_CELL_EN_10___POR 0x014 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_10__DA_CELL_AUX_EN_10___POR 0x02 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_10__DA_CASOFF_BIAS_10___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_10__DA_HS_CTRL_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_10__DA_CELL_EN_10___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_10__DA_CELL_EN_10___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_10__DA_CELL_AUX_EN_10___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_10__DA_CELL_AUX_EN_10___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_10__DA_CASOFF_BIAS_10___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_10__DA_CASOFF_BIAS_10___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_10__DA_HS_CTRL_10___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_10__DA_HS_CTRL_10___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_10___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_10___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_11 (0x005E133C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_11___POR 0x0B019000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_11__DA_CELL_EN_11___POR 0x016 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_11__DA_CELL_AUX_EN_11___POR 0x03 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_11__DA_CASOFF_BIAS_11___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_11__DA_HS_CTRL_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_11__DA_CELL_EN_11___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_11__DA_CELL_EN_11___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_11__DA_CELL_AUX_EN_11___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_11__DA_CELL_AUX_EN_11___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_11__DA_CASOFF_BIAS_11___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_11__DA_CASOFF_BIAS_11___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_11__DA_HS_CTRL_11___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_11__DA_HS_CTRL_11___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_11___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_11___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_12 (0x005E1340) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_12___POR 0x0C019000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_12__DA_CELL_EN_12___POR 0x018 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_12__DA_CELL_AUX_EN_12___POR 0x03 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_12__DA_CASOFF_BIAS_12___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_12__DA_HS_CTRL_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_12__DA_CELL_EN_12___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_12__DA_CELL_EN_12___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_12__DA_CELL_AUX_EN_12___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_12__DA_CELL_AUX_EN_12___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_12__DA_CASOFF_BIAS_12___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_12__DA_CASOFF_BIAS_12___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_12__DA_HS_CTRL_12___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_12__DA_HS_CTRL_12___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_12___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_12___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_13 (0x005E1344) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_13___POR 0x0D019000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_13__DA_CELL_EN_13___POR 0x01A +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_13__DA_CELL_AUX_EN_13___POR 0x03 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_13__DA_CASOFF_BIAS_13___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_13__DA_HS_CTRL_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_13__DA_CELL_EN_13___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_13__DA_CELL_EN_13___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_13__DA_CELL_AUX_EN_13___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_13__DA_CELL_AUX_EN_13___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_13__DA_CASOFF_BIAS_13___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_13__DA_CASOFF_BIAS_13___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_13__DA_HS_CTRL_13___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_13__DA_HS_CTRL_13___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_13___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_13___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_14 (0x005E1348) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_14___POR 0x13019000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_14__DA_CELL_EN_14___POR 0x026 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_14__DA_CELL_AUX_EN_14___POR 0x03 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_14__DA_CASOFF_BIAS_14___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_14__DA_HS_CTRL_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_14__DA_CELL_EN_14___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_14__DA_CELL_EN_14___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_14__DA_CELL_AUX_EN_14___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_14__DA_CELL_AUX_EN_14___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_14__DA_CASOFF_BIAS_14___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_14__DA_CASOFF_BIAS_14___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_14__DA_HS_CTRL_14___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_14__DA_HS_CTRL_14___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_14___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_14___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_15 (0x005E134C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_15___POR 0x14021000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_15__DA_CELL_EN_15___POR 0x028 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_15__DA_CELL_AUX_EN_15___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_15__DA_CASOFF_BIAS_15___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_15__DA_HS_CTRL_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_15__DA_CELL_EN_15___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_15__DA_CELL_EN_15___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_15__DA_CELL_AUX_EN_15___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_15__DA_CELL_AUX_EN_15___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_15__DA_CASOFF_BIAS_15___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_15__DA_CASOFF_BIAS_15___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_15__DA_HS_CTRL_15___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_15__DA_HS_CTRL_15___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_15___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_15___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_16 (0x005E1350) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_16___POR 0x15031000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_16__DA_CELL_EN_16___POR 0x02A +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_16__DA_CELL_AUX_EN_16___POR 0x06 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_16__DA_CASOFF_BIAS_16___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_16__DA_HS_CTRL_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_16__DA_CELL_EN_16___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_16__DA_CELL_EN_16___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_16__DA_CELL_AUX_EN_16___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_16__DA_CELL_AUX_EN_16___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_16__DA_CASOFF_BIAS_16___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_16__DA_CASOFF_BIAS_16___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_16__DA_HS_CTRL_16___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_16__DA_HS_CTRL_16___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_16___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_16___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_17 (0x005E1354) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_17___POR 0x19051000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_17__DA_CELL_EN_17___POR 0x032 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_17__DA_CELL_AUX_EN_17___POR 0x0A +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_17__DA_CASOFF_BIAS_17___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_17__DA_HS_CTRL_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_17__DA_CELL_EN_17___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_17__DA_CELL_EN_17___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_17__DA_CELL_AUX_EN_17___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_17__DA_CELL_AUX_EN_17___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_17__DA_CASOFF_BIAS_17___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_17__DA_CASOFF_BIAS_17___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_17__DA_HS_CTRL_17___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_17__DA_HS_CTRL_17___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_17___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_17___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_18 (0x005E1358) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_18___POR 0x1B061000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_18__DA_CELL_EN_18___POR 0x036 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_18__DA_CELL_AUX_EN_18___POR 0x0C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_18__DA_CASOFF_BIAS_18___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_18__DA_HS_CTRL_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_18__DA_CELL_EN_18___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_18__DA_CELL_EN_18___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_18__DA_CELL_AUX_EN_18___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_18__DA_CELL_AUX_EN_18___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_18__DA_CASOFF_BIAS_18___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_18__DA_CASOFF_BIAS_18___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_18__DA_HS_CTRL_18___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_18__DA_HS_CTRL_18___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_18___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_18___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_19 (0x005E135C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_19___POR 0x1D861000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_19__DA_CELL_EN_19___POR 0x03B +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_19__DA_CELL_AUX_EN_19___POR 0x0C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_19__DA_CASOFF_BIAS_19___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_19__DA_HS_CTRL_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_19__DA_CELL_EN_19___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_19__DA_CELL_EN_19___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_19__DA_CELL_AUX_EN_19___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_19__DA_CELL_AUX_EN_19___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_19__DA_CASOFF_BIAS_19___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_19__DA_CASOFF_BIAS_19___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_19__DA_HS_CTRL_19___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_19__DA_HS_CTRL_19___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_19___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_19___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_20 (0x005E1360) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_20___POR 0x25071000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_20__DA_CELL_EN_20___POR 0x04A +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_20__DA_CELL_AUX_EN_20___POR 0x0E +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_20__DA_CASOFF_BIAS_20___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_20__DA_HS_CTRL_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_20__DA_CELL_EN_20___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_20__DA_CELL_EN_20___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_20__DA_CELL_AUX_EN_20___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_20__DA_CELL_AUX_EN_20___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_20__DA_CASOFF_BIAS_20___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_20__DA_CASOFF_BIAS_20___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_20__DA_HS_CTRL_20___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_20__DA_HS_CTRL_20___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_20___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_20___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_21 (0x005E1364) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_21___POR 0x2A079000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_21__DA_CELL_EN_21___POR 0x054 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_21__DA_CELL_AUX_EN_21___POR 0x0F +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_21__DA_CASOFF_BIAS_21___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_21__DA_HS_CTRL_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_21__DA_CELL_EN_21___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_21__DA_CELL_EN_21___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_21__DA_CELL_AUX_EN_21___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_21__DA_CELL_AUX_EN_21___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_21__DA_CASOFF_BIAS_21___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_21__DA_CASOFF_BIAS_21___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_21__DA_HS_CTRL_21___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_21__DA_HS_CTRL_21___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_21___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_21___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_22 (0x005E1368) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_22___POR 0x2D091000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_22__DA_CELL_EN_22___POR 0x05A +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_22__DA_CELL_AUX_EN_22___POR 0x12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_22__DA_CASOFF_BIAS_22___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_22__DA_HS_CTRL_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_22__DA_CELL_EN_22___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_22__DA_CELL_EN_22___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_22__DA_CELL_AUX_EN_22___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_22__DA_CELL_AUX_EN_22___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_22__DA_CASOFF_BIAS_22___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_22__DA_CASOFF_BIAS_22___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_22__DA_HS_CTRL_22___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_22__DA_HS_CTRL_22___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_22___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_22___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_23 (0x005E136C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_23___POR 0x358C1000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_23__DA_CELL_EN_23___POR 0x06B +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_23__DA_CELL_AUX_EN_23___POR 0x18 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_23__DA_CASOFF_BIAS_23___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_23__DA_HS_CTRL_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_23__DA_CELL_EN_23___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_23__DA_CELL_EN_23___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_23__DA_CELL_AUX_EN_23___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_23__DA_CELL_AUX_EN_23___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_23__DA_CASOFF_BIAS_23___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_23__DA_CASOFF_BIAS_23___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_23__DA_HS_CTRL_23___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_23__DA_HS_CTRL_23___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_23___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_23___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_24 (0x005E1370) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_24___POR 0x3C0F9000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_24__DA_CELL_EN_24___POR 0x078 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_24__DA_CELL_AUX_EN_24___POR 0x1F +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_24__DA_CASOFF_BIAS_24___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_24__DA_HS_CTRL_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_24__DA_CELL_EN_24___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_24__DA_CELL_EN_24___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_24__DA_CELL_AUX_EN_24___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_24__DA_CELL_AUX_EN_24___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_24__DA_CASOFF_BIAS_24___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_24__DA_CASOFF_BIAS_24___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_24__DA_HS_CTRL_24___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_24__DA_HS_CTRL_24___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_24___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_24___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_25 (0x005E1374) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_25___POR 0x44951000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_25__DA_CELL_EN_25___POR 0x089 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_25__DA_CELL_AUX_EN_25___POR 0x2A +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_25__DA_CASOFF_BIAS_25___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_25__DA_HS_CTRL_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_25__DA_CELL_EN_25___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_25__DA_CELL_EN_25___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_25__DA_CELL_AUX_EN_25___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_25__DA_CELL_AUX_EN_25___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_25__DA_CASOFF_BIAS_25___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_25__DA_CASOFF_BIAS_25___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_25__DA_HS_CTRL_25___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_25__DA_HS_CTRL_25___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_25___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_25___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_26 (0x005E1378) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_26___POR 0x50199000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_26__DA_CELL_EN_26___POR 0x0A0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_26__DA_CELL_AUX_EN_26___POR 0x33 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_26__DA_CASOFF_BIAS_26___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_26__DA_HS_CTRL_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_26__DA_CELL_EN_26___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_26__DA_CELL_EN_26___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_26__DA_CELL_AUX_EN_26___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_26__DA_CELL_AUX_EN_26___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_26__DA_CASOFF_BIAS_26___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_26__DA_CASOFF_BIAS_26___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_26__DA_HS_CTRL_26___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_26__DA_HS_CTRL_26___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_26___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_26___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_27 (0x005E137C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_27___POR 0x569F9000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_27__DA_CELL_EN_27___POR 0x0AD +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_27__DA_CELL_AUX_EN_27___POR 0x3F +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_27__DA_CASOFF_BIAS_27___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_27__DA_HS_CTRL_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_27__DA_CELL_EN_27___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_27__DA_CELL_EN_27___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_27__DA_CELL_AUX_EN_27___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_27__DA_CELL_AUX_EN_27___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_27__DA_CASOFF_BIAS_27___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_27__DA_CASOFF_BIAS_27___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_27__DA_HS_CTRL_27___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_27__DA_HS_CTRL_27___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_27___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_27___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_28 (0x005E1380) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_28___POR 0x641F9000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_28__DA_CELL_EN_28___POR 0x0C8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_28__DA_CELL_AUX_EN_28___POR 0x3F +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_28__DA_CASOFF_BIAS_28___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_28__DA_HS_CTRL_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_28__DA_CELL_EN_28___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_28__DA_CELL_EN_28___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_28__DA_CELL_AUX_EN_28___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_28__DA_CELL_AUX_EN_28___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_28__DA_CASOFF_BIAS_28___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_28__DA_CASOFF_BIAS_28___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_28__DA_HS_CTRL_28___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_28__DA_HS_CTRL_28___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_28___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_28___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_29 (0x005E1384) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_29___POR 0x6E1F9000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_29__DA_CELL_EN_29___POR 0x0DC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_29__DA_CELL_AUX_EN_29___POR 0x3F +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_29__DA_CASOFF_BIAS_29___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_29__DA_HS_CTRL_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_29__DA_CELL_EN_29___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_29__DA_CELL_EN_29___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_29__DA_CELL_AUX_EN_29___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_29__DA_CELL_AUX_EN_29___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_29__DA_CASOFF_BIAS_29___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_29__DA_CASOFF_BIAS_29___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_29__DA_HS_CTRL_29___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_29__DA_HS_CTRL_29___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_29___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_29___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_30 (0x005E1388) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_30___POR 0x7D9F9000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_30__DA_CELL_EN_30___POR 0x0FB +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_30__DA_CELL_AUX_EN_30___POR 0x3F +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_30__DA_CASOFF_BIAS_30___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_30__DA_HS_CTRL_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_30__DA_CELL_EN_30___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_30__DA_CELL_EN_30___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_30__DA_CELL_AUX_EN_30___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_30__DA_CELL_AUX_EN_30___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_30__DA_CASOFF_BIAS_30___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_30__DA_CASOFF_BIAS_30___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_30__DA_HS_CTRL_30___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_30__DA_HS_CTRL_30___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_30___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_30___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_31 (0x005E138C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_31___POR 0xFE9F9000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_31__DA_CELL_EN_31___POR 0x1FD +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_31__DA_CELL_AUX_EN_31___POR 0x3F +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_31__DA_CASOFF_BIAS_31___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_31__DA_HS_CTRL_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_31__DA_CELL_EN_31___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_31__DA_CELL_EN_31___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_31__DA_CELL_AUX_EN_31___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_31__DA_CELL_AUX_EN_31___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_31__DA_CASOFF_BIAS_31___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_31__DA_CASOFF_BIAS_31___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_31__DA_HS_CTRL_31___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_31__DA_HS_CTRL_31___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_31___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA_LUT0_31___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_0 (0x005E1390) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_0__UPC_RGAIN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_0__UPC_RGAIN_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_0__UPC_RGAIN_0___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_0___S 29 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_1 (0x005E1394) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_1__UPC_RGAIN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_1__UPC_RGAIN_1___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_1__UPC_RGAIN_1___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_1___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_1___S 29 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_2 (0x005E1398) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_2__UPC_RGAIN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_2__UPC_RGAIN_2___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_2__UPC_RGAIN_2___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_2___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_2___S 29 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_3 (0x005E139C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_3__UPC_RGAIN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_3__UPC_RGAIN_3___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_3__UPC_RGAIN_3___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_3___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_3___S 29 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_4 (0x005E13A0) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_4__UPC_RGAIN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_4__UPC_RGAIN_4___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_4__UPC_RGAIN_4___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_4___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_4___S 29 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_5 (0x005E13A4) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_5__UPC_RGAIN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_5__UPC_RGAIN_5___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_5__UPC_RGAIN_5___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_5___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_5___S 29 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_6 (0x005E13A8) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_6__UPC_RGAIN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_6__UPC_RGAIN_6___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_6__UPC_RGAIN_6___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_6___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_6___S 29 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_7 (0x005E13AC) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_7__UPC_RGAIN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_7__UPC_RGAIN_7___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_7__UPC_RGAIN_7___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_7___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC_LUT_7___S 29 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0 (0x005E13B0) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0___POR 0x302E4000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_ILEVEL_0___POR 0x06 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_ILEVEL_B2_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX1_0___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX0_0___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_0___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_CASOFF_BIAS_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_ILEVEL_0___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_ILEVEL_0___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_ILEVEL_B2_0___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_ILEVEL_B2_0___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX1_0___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX1_0___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX0_0___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX0_0___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_0___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_0___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_CASOFF_BIAS_0___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0__PA_CASOFF_BIAS_0___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_0___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1 (0x005E13B4) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1___POR 0x302E4000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_ILEVEL_1___POR 0x06 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_ILEVEL_B2_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX1_1___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX0_1___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_1___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_CASOFF_BIAS_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_ILEVEL_1___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_ILEVEL_1___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_ILEVEL_B2_1___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_ILEVEL_B2_1___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX1_1___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX1_1___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX0_1___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX0_1___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_1___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_1___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_CASOFF_BIAS_1___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1__PA_CASOFF_BIAS_1___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_1___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2 (0x005E13B8) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2___POR 0x302E4000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_ILEVEL_2___POR 0x06 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_ILEVEL_B2_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX1_2___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX0_2___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_2___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_CASOFF_BIAS_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_ILEVEL_2___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_ILEVEL_2___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_ILEVEL_B2_2___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_ILEVEL_B2_2___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX1_2___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX1_2___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX0_2___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX0_2___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_2___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_2___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_CASOFF_BIAS_2___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2__PA_CASOFF_BIAS_2___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_2___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3 (0x005E13BC) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3___POR 0x302E4000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_ILEVEL_3___POR 0x06 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_ILEVEL_B2_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX1_3___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX0_3___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_3___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_CASOFF_BIAS_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_ILEVEL_3___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_ILEVEL_3___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_ILEVEL_B2_3___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_ILEVEL_B2_3___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX1_3___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX1_3___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX0_3___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX0_3___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_3___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_3___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_CASOFF_BIAS_3___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3__PA_CASOFF_BIAS_3___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_3___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4 (0x005E13C0) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4___POR 0x302E4000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_ILEVEL_4___POR 0x06 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_ILEVEL_B2_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX1_4___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX0_4___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_4___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_CASOFF_BIAS_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_ILEVEL_4___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_ILEVEL_4___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_ILEVEL_B2_4___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_ILEVEL_B2_4___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX1_4___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX1_4___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX0_4___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX0_4___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_4___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_4___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_CASOFF_BIAS_4___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4__PA_CASOFF_BIAS_4___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_4___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5 (0x005E13C4) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5___POR 0x302E4000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_ILEVEL_5___POR 0x06 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_ILEVEL_B2_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX1_5___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX0_5___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_5___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_CASOFF_BIAS_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_ILEVEL_5___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_ILEVEL_5___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_ILEVEL_B2_5___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_ILEVEL_B2_5___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX1_5___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX1_5___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX0_5___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX0_5___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_5___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_5___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_CASOFF_BIAS_5___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5__PA_CASOFF_BIAS_5___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_5___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6 (0x005E13C8) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6___POR 0x302E4000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_ILEVEL_6___POR 0x06 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_ILEVEL_B2_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_AUX1_6___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_AUX0_6___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_6___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_CASOFF_BIAS_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_ILEVEL_6___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_ILEVEL_6___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_ILEVEL_B2_6___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_ILEVEL_B2_6___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_AUX1_6___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_AUX1_6___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_AUX0_6___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_AUX0_6___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_6___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_6___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_CASOFF_BIAS_6___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6__PA_CASOFF_BIAS_6___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_6___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7 (0x005E13CC) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7___POR 0x302E4000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_ILEVEL_7___POR 0x06 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_ILEVEL_B2_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_AUX1_7___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_AUX0_7___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_7___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_CASOFF_BIAS_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_ILEVEL_7___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_ILEVEL_7___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_ILEVEL_B2_7___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_ILEVEL_B2_7___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_AUX1_7___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_AUX1_7___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_AUX0_7___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_AUX0_7___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_7___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_7___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_CASOFF_BIAS_7___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7__PA_CASOFF_BIAS_7___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_7___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8 (0x005E13D0) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8___POR 0x282EB000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_ILEVEL_8___POR 0x05 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_ILEVEL_B2_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_AUX1_8___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_AUX0_8___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_8___POR 0xB +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_CASOFF_BIAS_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_ILEVEL_8___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_ILEVEL_8___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_ILEVEL_B2_8___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_ILEVEL_B2_8___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_AUX1_8___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_AUX1_8___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_AUX0_8___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_AUX0_8___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_8___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_8___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_CASOFF_BIAS_8___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8__PA_CASOFF_BIAS_8___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_8___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9 (0x005E13D4) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9___POR 0x282EB000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_ILEVEL_9___POR 0x05 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_ILEVEL_B2_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_AUX1_9___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_AUX0_9___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_9___POR 0xB +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_CASOFF_BIAS_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_ILEVEL_9___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_ILEVEL_9___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_ILEVEL_B2_9___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_ILEVEL_B2_9___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_AUX1_9___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_AUX1_9___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_AUX0_9___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_AUX0_9___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_9___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_9___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_CASOFF_BIAS_9___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9__PA_CASOFF_BIAS_9___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_9___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10 (0x005E13D8) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10___POR 0x282EB000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_ILEVEL_10___POR 0x05 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_ILEVEL_B2_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_AUX1_10___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_AUX0_10___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_10___POR 0xB +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_CASOFF_BIAS_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_ILEVEL_10___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_ILEVEL_10___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_ILEVEL_B2_10___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_ILEVEL_B2_10___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_AUX1_10___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_AUX1_10___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_AUX0_10___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_AUX0_10___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_10___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_10___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_CASOFF_BIAS_10___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10__PA_CASOFF_BIAS_10___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_10___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11 (0x005E13DC) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11___POR 0x282EB000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_ILEVEL_11___POR 0x05 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_ILEVEL_B2_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_AUX1_11___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_AUX0_11___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_11___POR 0xB +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_CASOFF_BIAS_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_ILEVEL_11___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_ILEVEL_11___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_ILEVEL_B2_11___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_ILEVEL_B2_11___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_AUX1_11___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_AUX1_11___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_AUX0_11___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_AUX0_11___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_11___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_11___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_CASOFF_BIAS_11___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11__PA_CASOFF_BIAS_11___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_11___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12 (0x005E13E0) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12___POR 0x282EB000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_ILEVEL_12___POR 0x05 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_ILEVEL_B2_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_AUX1_12___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_AUX0_12___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_12___POR 0xB +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_CASOFF_BIAS_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_ILEVEL_12___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_ILEVEL_12___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_ILEVEL_B2_12___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_ILEVEL_B2_12___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_AUX1_12___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_AUX1_12___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_AUX0_12___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_AUX0_12___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_12___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_12___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_CASOFF_BIAS_12___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12__PA_CASOFF_BIAS_12___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_12___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13 (0x005E13E4) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13___POR 0x282EB000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_ILEVEL_13___POR 0x05 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_ILEVEL_B2_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_AUX1_13___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_AUX0_13___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_13___POR 0xB +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_CASOFF_BIAS_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_ILEVEL_13___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_ILEVEL_13___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_ILEVEL_B2_13___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_ILEVEL_B2_13___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_AUX1_13___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_AUX1_13___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_AUX0_13___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_AUX0_13___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_13___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_13___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_CASOFF_BIAS_13___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13__PA_CASOFF_BIAS_13___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_13___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14 (0x005E13E8) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14___POR 0x282EB000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_ILEVEL_14___POR 0x05 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_ILEVEL_B2_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_AUX1_14___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_AUX0_14___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_14___POR 0xB +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_CASOFF_BIAS_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_ILEVEL_14___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_ILEVEL_14___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_ILEVEL_B2_14___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_ILEVEL_B2_14___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_AUX1_14___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_AUX1_14___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_AUX0_14___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_AUX0_14___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_14___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_14___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_CASOFF_BIAS_14___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14__PA_CASOFF_BIAS_14___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_14___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15 (0x005E13EC) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15___POR 0x282EB000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_ILEVEL_15___POR 0x05 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_ILEVEL_B2_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_AUX1_15___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_AUX0_15___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_15___POR 0xB +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_CASOFF_BIAS_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_ILEVEL_15___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_ILEVEL_15___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_ILEVEL_B2_15___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_ILEVEL_B2_15___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_AUX1_15___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_AUX1_15___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_AUX0_15___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_AUX0_15___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_15___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_15___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_CASOFF_BIAS_15___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15__PA_CASOFF_BIAS_15___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT0_15___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0 (0x005E13F0) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0___POR 0xC0300500 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0__PA_CELL_EN1_0___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0__PA_CELL_EN0_0___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0__PA_IBIAS_MODE_0___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0__PA_LP_HS_CTRL_0___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0__PA_LP_CORE_XFRM_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0__PA_CELL_EN1_0___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0__PA_CELL_EN1_0___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0__PA_CELL_EN0_0___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0__PA_CELL_EN0_0___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0__PA_IBIAS_MODE_0___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0__PA_IBIAS_MODE_0___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0__PA_LP_HS_CTRL_0___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0__PA_LP_HS_CTRL_0___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0__PA_LP_CORE_XFRM_0___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0__PA_LP_CORE_XFRM_0___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0___M 0xFFFFFF80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_0___S 7 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1 (0x005E13F4) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1___POR 0xC0300500 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1__PA_CELL_EN1_1___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1__PA_CELL_EN0_1___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1__PA_IBIAS_MODE_1___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1__PA_LP_HS_CTRL_1___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1__PA_LP_CORE_XFRM_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1__PA_CELL_EN1_1___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1__PA_CELL_EN1_1___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1__PA_CELL_EN0_1___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1__PA_CELL_EN0_1___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1__PA_IBIAS_MODE_1___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1__PA_IBIAS_MODE_1___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1__PA_LP_HS_CTRL_1___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1__PA_LP_HS_CTRL_1___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1__PA_LP_CORE_XFRM_1___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1__PA_LP_CORE_XFRM_1___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1___M 0xFFFFFF80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_1___S 7 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2 (0x005E13F8) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2___POR 0xC0300500 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2__PA_CELL_EN1_2___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2__PA_CELL_EN0_2___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2__PA_IBIAS_MODE_2___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2__PA_LP_HS_CTRL_2___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2__PA_LP_CORE_XFRM_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2__PA_CELL_EN1_2___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2__PA_CELL_EN1_2___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2__PA_CELL_EN0_2___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2__PA_CELL_EN0_2___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2__PA_IBIAS_MODE_2___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2__PA_IBIAS_MODE_2___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2__PA_LP_HS_CTRL_2___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2__PA_LP_HS_CTRL_2___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2__PA_LP_CORE_XFRM_2___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2__PA_LP_CORE_XFRM_2___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2___M 0xFFFFFF80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_2___S 7 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3 (0x005E13FC) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3___POR 0xC0300500 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3__PA_CELL_EN1_3___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3__PA_CELL_EN0_3___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3__PA_IBIAS_MODE_3___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3__PA_LP_HS_CTRL_3___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3__PA_LP_CORE_XFRM_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3__PA_CELL_EN1_3___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3__PA_CELL_EN1_3___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3__PA_CELL_EN0_3___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3__PA_CELL_EN0_3___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3__PA_IBIAS_MODE_3___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3__PA_IBIAS_MODE_3___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3__PA_LP_HS_CTRL_3___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3__PA_LP_HS_CTRL_3___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3__PA_LP_CORE_XFRM_3___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3__PA_LP_CORE_XFRM_3___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3___M 0xFFFFFF80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_3___S 7 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4 (0x005E1400) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4___POR 0xC0300500 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4__PA_CELL_EN1_4___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4__PA_CELL_EN0_4___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4__PA_IBIAS_MODE_4___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4__PA_LP_HS_CTRL_4___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4__PA_LP_CORE_XFRM_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4__PA_CELL_EN1_4___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4__PA_CELL_EN1_4___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4__PA_CELL_EN0_4___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4__PA_CELL_EN0_4___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4__PA_IBIAS_MODE_4___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4__PA_IBIAS_MODE_4___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4__PA_LP_HS_CTRL_4___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4__PA_LP_HS_CTRL_4___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4__PA_LP_CORE_XFRM_4___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4__PA_LP_CORE_XFRM_4___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4___M 0xFFFFFF80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_4___S 7 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5 (0x005E1404) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5___POR 0xC0300500 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5__PA_CELL_EN1_5___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5__PA_CELL_EN0_5___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5__PA_IBIAS_MODE_5___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5__PA_LP_HS_CTRL_5___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5__PA_LP_CORE_XFRM_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5__PA_CELL_EN1_5___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5__PA_CELL_EN1_5___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5__PA_CELL_EN0_5___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5__PA_CELL_EN0_5___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5__PA_IBIAS_MODE_5___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5__PA_IBIAS_MODE_5___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5__PA_LP_HS_CTRL_5___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5__PA_LP_HS_CTRL_5___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5__PA_LP_CORE_XFRM_5___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5__PA_LP_CORE_XFRM_5___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5___M 0xFFFFFF80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_5___S 7 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6 (0x005E1408) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6___POR 0xC0300500 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6__PA_CELL_EN1_6___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6__PA_CELL_EN0_6___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6__PA_IBIAS_MODE_6___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6__PA_LP_HS_CTRL_6___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6__PA_LP_CORE_XFRM_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6__PA_CELL_EN1_6___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6__PA_CELL_EN1_6___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6__PA_CELL_EN0_6___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6__PA_CELL_EN0_6___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6__PA_IBIAS_MODE_6___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6__PA_IBIAS_MODE_6___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6__PA_LP_HS_CTRL_6___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6__PA_LP_HS_CTRL_6___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6__PA_LP_CORE_XFRM_6___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6__PA_LP_CORE_XFRM_6___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6___M 0xFFFFFF80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_6___S 7 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7 (0x005E140C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7___POR 0xC0300500 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7__PA_CELL_EN1_7___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7__PA_CELL_EN0_7___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7__PA_IBIAS_MODE_7___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7__PA_LP_HS_CTRL_7___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7__PA_LP_CORE_XFRM_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7__PA_CELL_EN1_7___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7__PA_CELL_EN1_7___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7__PA_CELL_EN0_7___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7__PA_CELL_EN0_7___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7__PA_IBIAS_MODE_7___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7__PA_IBIAS_MODE_7___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7__PA_LP_HS_CTRL_7___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7__PA_LP_HS_CTRL_7___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7__PA_LP_CORE_XFRM_7___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7__PA_LP_CORE_XFRM_7___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7___M 0xFFFFFF80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_7___S 7 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8 (0x005E1410) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8___POR 0x3FCFFD80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8__PA_CELL_EN1_8___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8__PA_CELL_EN0_8___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8__PA_IBIAS_MODE_8___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8__PA_LP_HS_CTRL_8___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8__PA_LP_CORE_XFRM_8___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8__PA_CELL_EN1_8___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8__PA_CELL_EN1_8___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8__PA_CELL_EN0_8___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8__PA_CELL_EN0_8___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8__PA_IBIAS_MODE_8___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8__PA_IBIAS_MODE_8___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8__PA_LP_HS_CTRL_8___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8__PA_LP_HS_CTRL_8___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8__PA_LP_CORE_XFRM_8___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8__PA_LP_CORE_XFRM_8___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8___M 0xFFFFFF80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_8___S 7 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9 (0x005E1414) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9___POR 0x3FCFFD80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9__PA_CELL_EN1_9___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9__PA_CELL_EN0_9___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9__PA_IBIAS_MODE_9___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9__PA_LP_HS_CTRL_9___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9__PA_LP_CORE_XFRM_9___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9__PA_CELL_EN1_9___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9__PA_CELL_EN1_9___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9__PA_CELL_EN0_9___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9__PA_CELL_EN0_9___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9__PA_IBIAS_MODE_9___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9__PA_IBIAS_MODE_9___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9__PA_LP_HS_CTRL_9___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9__PA_LP_HS_CTRL_9___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9__PA_LP_CORE_XFRM_9___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9__PA_LP_CORE_XFRM_9___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9___M 0xFFFFFF80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_9___S 7 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10 (0x005E1418) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10___POR 0x3FCFFD80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10__PA_CELL_EN1_10___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10__PA_CELL_EN0_10___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10__PA_IBIAS_MODE_10___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10__PA_LP_HS_CTRL_10___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10__PA_LP_CORE_XFRM_10___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10__PA_CELL_EN1_10___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10__PA_CELL_EN1_10___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10__PA_CELL_EN0_10___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10__PA_CELL_EN0_10___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10__PA_IBIAS_MODE_10___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10__PA_IBIAS_MODE_10___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10__PA_LP_HS_CTRL_10___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10__PA_LP_HS_CTRL_10___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10__PA_LP_CORE_XFRM_10___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10__PA_LP_CORE_XFRM_10___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10___M 0xFFFFFF80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_10___S 7 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11 (0x005E141C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11___POR 0x3FCFFD80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11__PA_CELL_EN1_11___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11__PA_CELL_EN0_11___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11__PA_IBIAS_MODE_11___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11__PA_LP_HS_CTRL_11___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11__PA_LP_CORE_XFRM_11___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11__PA_CELL_EN1_11___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11__PA_CELL_EN1_11___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11__PA_CELL_EN0_11___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11__PA_CELL_EN0_11___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11__PA_IBIAS_MODE_11___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11__PA_IBIAS_MODE_11___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11__PA_LP_HS_CTRL_11___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11__PA_LP_HS_CTRL_11___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11__PA_LP_CORE_XFRM_11___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11__PA_LP_CORE_XFRM_11___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11___M 0xFFFFFF80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_11___S 7 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12 (0x005E1420) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12___POR 0x3FCFFD80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12__PA_CELL_EN1_12___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12__PA_CELL_EN0_12___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12__PA_IBIAS_MODE_12___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12__PA_LP_HS_CTRL_12___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12__PA_LP_CORE_XFRM_12___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12__PA_CELL_EN1_12___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12__PA_CELL_EN1_12___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12__PA_CELL_EN0_12___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12__PA_CELL_EN0_12___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12__PA_IBIAS_MODE_12___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12__PA_IBIAS_MODE_12___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12__PA_LP_HS_CTRL_12___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12__PA_LP_HS_CTRL_12___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12__PA_LP_CORE_XFRM_12___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12__PA_LP_CORE_XFRM_12___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12___M 0xFFFFFF80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_12___S 7 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13 (0x005E1424) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13___POR 0x3FCFFD80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13__PA_CELL_EN1_13___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13__PA_CELL_EN0_13___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13__PA_IBIAS_MODE_13___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13__PA_LP_HS_CTRL_13___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13__PA_LP_CORE_XFRM_13___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13__PA_CELL_EN1_13___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13__PA_CELL_EN1_13___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13__PA_CELL_EN0_13___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13__PA_CELL_EN0_13___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13__PA_IBIAS_MODE_13___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13__PA_IBIAS_MODE_13___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13__PA_LP_HS_CTRL_13___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13__PA_LP_HS_CTRL_13___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13__PA_LP_CORE_XFRM_13___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13__PA_LP_CORE_XFRM_13___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13___M 0xFFFFFF80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_13___S 7 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14 (0x005E1428) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14___POR 0x3FCFFD80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14__PA_CELL_EN1_14___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14__PA_CELL_EN0_14___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14__PA_IBIAS_MODE_14___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14__PA_LP_HS_CTRL_14___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14__PA_LP_CORE_XFRM_14___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14__PA_CELL_EN1_14___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14__PA_CELL_EN1_14___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14__PA_CELL_EN0_14___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14__PA_CELL_EN0_14___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14__PA_IBIAS_MODE_14___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14__PA_IBIAS_MODE_14___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14__PA_LP_HS_CTRL_14___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14__PA_LP_HS_CTRL_14___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14__PA_LP_CORE_XFRM_14___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14__PA_LP_CORE_XFRM_14___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14___M 0xFFFFFF80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_14___S 7 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15 (0x005E142C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15___POR 0x3FCFFD80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15__PA_CELL_EN1_15___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15__PA_CELL_EN0_15___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15__PA_IBIAS_MODE_15___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15__PA_LP_HS_CTRL_15___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15__PA_LP_CORE_XFRM_15___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15__PA_CELL_EN1_15___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15__PA_CELL_EN1_15___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15__PA_CELL_EN0_15___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15__PA_CELL_EN0_15___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15__PA_IBIAS_MODE_15___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15__PA_IBIAS_MODE_15___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15__PA_LP_HS_CTRL_15___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15__PA_LP_HS_CTRL_15___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15__PA_LP_CORE_XFRM_15___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15__PA_LP_CORE_XFRM_15___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15___M 0xFFFFFF80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT1_15___S 7 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0 (0x005E1430) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__FE_RFIO_CAP_EN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__PA_CELL_FB_0___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__FE_RFIO_CAP_EN_0___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__FE_RFIO_CAP_EN_0___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__PA_CELL_FB_0___M 0x7FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0__PA_CELL_FB_0___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_0___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1 (0x005E1434) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__FE_RFIO_CAP_EN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__PA_CELL_FB_1___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__FE_RFIO_CAP_EN_1___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__FE_RFIO_CAP_EN_1___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__PA_CELL_FB_1___M 0x7FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1__PA_CELL_FB_1___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_1___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2 (0x005E1438) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__FE_RFIO_CAP_EN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__PA_CELL_FB_2___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__FE_RFIO_CAP_EN_2___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__FE_RFIO_CAP_EN_2___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__PA_CELL_FB_2___M 0x7FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2__PA_CELL_FB_2___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_2___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3 (0x005E143C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__FE_RFIO_CAP_EN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__PA_CELL_FB_3___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__FE_RFIO_CAP_EN_3___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__FE_RFIO_CAP_EN_3___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__PA_CELL_FB_3___M 0x7FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3__PA_CELL_FB_3___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_3___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4 (0x005E1440) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__FE_RFIO_CAP_EN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__PA_CELL_FB_4___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__FE_RFIO_CAP_EN_4___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__FE_RFIO_CAP_EN_4___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__PA_CELL_FB_4___M 0x7FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4__PA_CELL_FB_4___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_4___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5 (0x005E1444) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__FE_RFIO_CAP_EN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__PA_CELL_FB_5___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__FE_RFIO_CAP_EN_5___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__FE_RFIO_CAP_EN_5___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__PA_CELL_FB_5___M 0x7FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5__PA_CELL_FB_5___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_5___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6 (0x005E1448) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__FE_RFIO_CAP_EN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__PA_CELL_FB_6___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__FE_RFIO_CAP_EN_6___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__FE_RFIO_CAP_EN_6___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__PA_CELL_FB_6___M 0x7FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6__PA_CELL_FB_6___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_6___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7 (0x005E144C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__FE_RFIO_CAP_EN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__PA_CELL_FB_7___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__FE_RFIO_CAP_EN_7___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__FE_RFIO_CAP_EN_7___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__PA_CELL_FB_7___M 0x7FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7__PA_CELL_FB_7___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_7___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8 (0x005E1450) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8___POR 0x1FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__FE_RFIO_CAP_EN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__PA_CELL_FB_8___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__FE_RFIO_CAP_EN_8___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__FE_RFIO_CAP_EN_8___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__PA_CELL_FB_8___M 0x7FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8__PA_CELL_FB_8___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_8___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9 (0x005E1454) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9___POR 0x1FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__FE_RFIO_CAP_EN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__PA_CELL_FB_9___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__FE_RFIO_CAP_EN_9___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__FE_RFIO_CAP_EN_9___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__PA_CELL_FB_9___M 0x7FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9__PA_CELL_FB_9___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_9___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10 (0x005E1458) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10___POR 0x1FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__FE_RFIO_CAP_EN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__PA_CELL_FB_10___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__FE_RFIO_CAP_EN_10___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__FE_RFIO_CAP_EN_10___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__PA_CELL_FB_10___M 0x7FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10__PA_CELL_FB_10___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_10___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11 (0x005E145C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11___POR 0x1FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__FE_RFIO_CAP_EN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__PA_CELL_FB_11___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__FE_RFIO_CAP_EN_11___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__FE_RFIO_CAP_EN_11___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__PA_CELL_FB_11___M 0x7FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11__PA_CELL_FB_11___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_11___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12 (0x005E1460) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12___POR 0x1FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__FE_RFIO_CAP_EN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__PA_CELL_FB_12___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__FE_RFIO_CAP_EN_12___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__FE_RFIO_CAP_EN_12___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__PA_CELL_FB_12___M 0x7FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12__PA_CELL_FB_12___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_12___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13 (0x005E1464) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13___POR 0x1FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__FE_RFIO_CAP_EN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__PA_CELL_FB_13___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__FE_RFIO_CAP_EN_13___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__FE_RFIO_CAP_EN_13___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__PA_CELL_FB_13___M 0x7FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13__PA_CELL_FB_13___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_13___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14 (0x005E1468) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14___POR 0x1FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__FE_RFIO_CAP_EN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__PA_CELL_FB_14___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__FE_RFIO_CAP_EN_14___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__FE_RFIO_CAP_EN_14___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__PA_CELL_FB_14___M 0x7FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14__PA_CELL_FB_14___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_14___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15 (0x005E146C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15___POR 0x1FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__FE_RFIO_CAP_EN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__PA_CELL_FB_15___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__FE_RFIO_CAP_EN_15___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__FE_RFIO_CAP_EN_15___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__PA_CELL_FB_15___M 0x7FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15__PA_CELL_FB_15___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA_LUT2_15___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0 (0x005E1470) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_CTUNE3FLO_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_CTUNE3FLO_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_CTUNE1FLO_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_CTUNE1FLO_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__DA_CTUNE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__DA_CTUNE_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_RGAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_RGAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_CTUNE3FLO_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_CTUNE3FLO_OV___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_CTUNE3FLO_OVD___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_CTUNE3FLO_OVD___S 25 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_CTUNE1FLO_OV___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_CTUNE1FLO_OV___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_CTUNE1FLO_OVD___M 0x00FC0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_CTUNE1FLO_OVD___S 18 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__DA_CTUNE_OV___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__DA_CTUNE_OV___S 17 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__DA_CTUNE_OVD___M 0x0001F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__DA_CTUNE_OVD___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_RGAIN_OV___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_RGAIN_OV___S 11 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_RGAIN_OVD___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0__UPC_RGAIN_OVD___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0___M 0xFFFFFF00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV0___S 8 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1 (0x005E1474) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CELL_EN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CELL_EN_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CELL_AUX_EN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CELL_AUX_EN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CASOFF_BIAS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CASOFF_BIAS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_HS_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_HS_CTRL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CELL_EN_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CELL_EN_OV___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CELL_EN_OVD___M 0x7FC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CELL_EN_OVD___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CELL_AUX_EN_OV___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CELL_AUX_EN_OV___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CELL_AUX_EN_OVD___M 0x001FE000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CELL_AUX_EN_OVD___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CASOFF_BIAS_OV___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CASOFF_BIAS_OV___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CASOFF_BIAS_OVD___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_CASOFF_BIAS_OVD___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_HS_CTRL_OV___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_HS_CTRL_OV___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_HS_CTRL_OVD___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1__DA_HS_CTRL_OVD___S 6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1___M 0xFFFFFFC0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV1___S 6 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4 (0x005E1478) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_ILEVEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_ILEVEL_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_ILEVEL_B2_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_ILEVEL_B2_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_AUX1_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_AUX1_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_AUX0_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_AUX0_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CASOFF_BIAS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CASOFF_BIAS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_ILEVEL_OV___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_ILEVEL_OV___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_ILEVEL_OVD___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_ILEVEL_OVD___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_ILEVEL_B2_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_ILEVEL_B2_OV___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_ILEVEL_B2_OVD___M 0x007C0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_ILEVEL_B2_OVD___S 18 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_AUX1_OV___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_AUX1_OV___S 17 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_AUX1_OVD___M 0x0001C000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_AUX1_OVD___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_AUX0_OV___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_AUX0_OV___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_AUX0_OVD___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_AUX0_OVD___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_OV___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_OV___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_OVD___M 0x000001E0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CAS_BIAS_OVD___S 5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CASOFF_BIAS_OV___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CASOFF_BIAS_OV___S 4 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CASOFF_BIAS_OVD___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4__PA_CASOFF_BIAS_OVD___S 1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4___M 0x3FFFFFFE +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV4___S 1 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5 (0x005E147C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_CELL_EN1_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_CELL_EN1_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_CELL_EN0_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_CELL_EN0_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_IBIAS_MODE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_IBIAS_MODE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_LP_HS_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_LP_HS_CTRL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_LP_CORE_XFRM_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_CELL_EN1_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_CELL_EN1_OV___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_CELL_EN1_OVD___M 0x7FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_CELL_EN1_OVD___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_CELL_EN0_OV___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_CELL_EN0_OV___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_CELL_EN0_OVD___M 0x000FFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_CELL_EN0_OVD___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_IBIAS_MODE_OV___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_IBIAS_MODE_OV___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_IBIAS_MODE_OVD___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_IBIAS_MODE_OVD___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_LP_HS_CTRL_OV___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_LP_HS_CTRL_OV___S 6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_LP_HS_CTRL_OVD___M 0x00000030 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_LP_HS_CTRL_OVD___S 4 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_LP_CORE_XFRM_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5__PA_LP_CORE_XFRM_OVS___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV5___S 2 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6 (0x005E1480) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__FE_RFIO_CAP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_CELL_FB_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_CELL_FB_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__FE_RFIO_CAP_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__FE_RFIO_CAP_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_CELL_FB_OV___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_CELL_FB_OV___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_CELL_FB_OVD___M 0x1FF80000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6__PA_CELL_FB_OVD___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_LUT_OV6___S 19 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV0 (0x005E1484) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV0___POR 0x000C0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV0__TX_SINGLE_RU_OVS___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV0__TX_LO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV0__TX_LO_LP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV0__TX_SINGLE_RU_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV0__TX_SINGLE_RU_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV0__TX_LO_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV0__TX_LO_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV0__TX_LO_LP_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV0__TX_LO_LP_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV0___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV0___S 14 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1 (0x005E1488) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__CALRTX_ATTN_GM_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__CALRTX_PHASESHIFT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__DA_BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__TXLO_INBUF25DC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__TXLO_LP_INBUF25DC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_AUX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_LO_EN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_LO_EN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_EN_NMX_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_EN_NMX_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_EN_PMX_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_EN_PMX_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__CALRTX_ATTN_GM_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__CALRTX_ATTN_GM_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__CALRTX_PHASESHIFT_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__CALRTX_PHASESHIFT_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__DA_BIAS_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__DA_BIAS_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__TXLO_INBUF25DC_EN_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__TXLO_INBUF25DC_EN_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__TXLO_LP_INBUF25DC_EN_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__TXLO_LP_INBUF25DC_EN_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_AUX_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_AUX_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_LO_EN_OV___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_LO_EN_OV___S 18 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_LO_EN_OVD___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_LO_EN_OVD___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_EN_NMX_OV___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_EN_NMX_OV___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_EN_NMX_OVD___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_EN_NMX_OVD___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_EN_PMX_OV___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_EN_PMX_OV___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_EN_PMX_OVD___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1__UPC_EN_PMX_OVD___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1___M 0xFFF7FC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV1___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2 (0x005E148C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_BUFTLINE1ST_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_BUFTLINE2ND_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_LP_BUFTLINE1ST_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_LP_BUFTLINE2ND_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_OBUF25DC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_LP_OBUF25DC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__PA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_IPA_SW_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_IPA_CALTXSHIFT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_IPA_GM_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__PA_EN_SW_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_ATTN_HP_SW_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_ATTN_MP_SW_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_BUFTLINE1ST_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_BUFTLINE1ST_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_BUFTLINE2ND_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_BUFTLINE2ND_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_LP_BUFTLINE1ST_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_LP_BUFTLINE1ST_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_LP_BUFTLINE2ND_EN_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_LP_BUFTLINE2ND_EN_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_OBUF25DC_EN_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_OBUF25DC_EN_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_LP_OBUF25DC_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__TXLO_LP_OBUF25DC_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__PA_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__PA_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_IPA_SW_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_IPA_SW_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_IPA_CALTXSHIFT_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_IPA_CALTXSHIFT_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_IPA_GM_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_IPA_GM_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__PA_EN_SW_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__PA_EN_SW_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_ATTN_HP_SW_EN_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_ATTN_HP_SW_EN_OVS___S 6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_ATTN_MP_SW_EN_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2__WL_DPD2_ATTN_MP_SW_EN_OVS___S 4 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2___M 0xFFF3FFF0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_OV2___S 4 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0 (0x005E1490) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_UPC_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_DA_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_FCS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_DA_CTUNE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_TX_SINGLE_RU___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_IPA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_DA_CASOFF_BIAS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_DA_HS_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_UPC_GAIN___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_UPC_GAIN___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_DA_GAIN___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_DA_GAIN___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_FCS___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_FCS___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_DA_CTUNE___M 0x007C0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_DA_CTUNE___S 18 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_TX_SINGLE_RU___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_TX_SINGLE_RU___S 17 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_IPA_GAIN___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_IPA_GAIN___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_DA_CASOFF_BIAS___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_DA_CASOFF_BIAS___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_DA_HS_CTRL___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0__RO_DA_HS_CTRL___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0___M 0xFFFFFF00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT0___S 8 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1 (0x005E1494) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1__RO_DA_CELL_EN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1__RO_DA_CELL_AUX_EN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1__RO_UPC_RGAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1__RO_UPC_CTUNE3FLO___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1__RO_UPC_CTUNE1FLO___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1__RO_DA_CELL_EN___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1__RO_DA_CELL_EN___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1__RO_DA_CELL_AUX_EN___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1__RO_DA_CELL_AUX_EN___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1__RO_UPC_RGAIN___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1__RO_UPC_RGAIN___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1__RO_UPC_CTUNE3FLO___M 0x00000FC0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1__RO_UPC_CTUNE3FLO___S 6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1__RO_UPC_CTUNE1FLO___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1__RO_UPC_CTUNE1FLO___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT1___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3 (0x005E1498) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3__RO_PA_ILEVEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3__RO_PA_ILEVEL_B2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3__RO_PA_ILEVEL___M 0x000007C0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3__RO_PA_ILEVEL___S 6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3__RO_PA_ILEVEL_B2___M 0x0000003E +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3__RO_PA_ILEVEL_B2___S 1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3___M 0x000007FE +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT3___S 1 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4 (0x005E149C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CASOFF_BIAS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CELL_EN1___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX1___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX1___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX0___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX0___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CASOFF_BIAS___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CASOFF_BIAS___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CELL_EN1___M 0x0007FE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4__RO_PA_CELL_EN1___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT4___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5 (0x005E14A0) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_CELL_EN0___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_LP_HS_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_LP_CORE_XFRM___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_IBIAS_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_FE_RFIO_CAP_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_CELL_FB___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_CELL_EN0___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_CELL_EN0___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_LP_HS_CTRL___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_LP_HS_CTRL___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_LP_CORE_XFRM___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_LP_CORE_XFRM___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_IBIAS_MODE___M 0x00060000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_IBIAS_MODE___S 17 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_FE_RFIO_CAP_EN___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_FE_RFIO_CAP_EN___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_CELL_FB___M 0x0000FFC0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5__RO_PA_CELL_FB___S 6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5___M 0xFFFFFFC0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LUT5___S 6 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0 (0x005E14A4) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_PA_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_SW_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_CALTXSHIFT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_GM_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_PA_EN_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_ATTN_HP_SW_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_ATTN_MP_SW_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_PA_EN___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_PA_EN___S 30 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_SW_EN___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_SW_EN___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_CALTXSHIFT___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_CALTXSHIFT___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_GM_EN___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_GM_EN___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_PA_EN_SW___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_PA_EN_SW___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_ATTN_HP_SW_EN___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_ATTN_HP_SW_EN___S 25 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_ATTN_MP_SW_EN___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_ATTN_MP_SW_EN___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0___M 0x7F000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_RO_WL_TXFE_LOGIC0___S 24 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0 (0x005E14C0) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0___POR 0x26920D00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_IBIAS_LOWER_LIM_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_IBIAS_LOWER_LIM___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_ISLOPE___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_CAS_BIAS___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_CAS_BIAS_AUX___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_ILEVEL_COARSE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_ILEVEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_BIAS_NOISE_CNCL_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_BIAS_NOISE_CNCL_RES___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_IBIAS_LOWER_LIM_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_IBIAS_LOWER_LIM_EN___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_IBIAS_LOWER_LIM___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_IBIAS_LOWER_LIM___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_ISLOPE___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_ISLOPE___S 25 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_CAS_BIAS___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_CAS_BIAS___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_CAS_BIAS_AUX___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_CAS_BIAS_AUX___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_ILEVEL_COARSE___M 0x00060000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_ILEVEL_COARSE___S 17 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_ILEVEL___M 0x00018000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_ILEVEL___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_ATB_SEL___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_ATB_SEL___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_BIAS_NOISE_CNCL_EN___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_BIAS_NOISE_CNCL_EN___S 11 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_BIAS_NOISE_CNCL_RES___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0__WL_DA_BIAS_NOISE_CNCL_RES___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0___M 0xFFFFFF00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DA0___S 8 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC0 (0x005E14C4) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC0___POR 0xBC000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC0__D_UPC_RSHIFTN___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC0__D_UPC_RSHIFTP___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC0__D_UPC_RMXFILT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC0__D_UPC_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC0__D_UPC_RSHIFTN___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC0__D_UPC_RSHIFTN___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC0__D_UPC_RSHIFTP___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC0__D_UPC_RSHIFTP___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC0__D_UPC_RMXFILT___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC0__D_UPC_RMXFILT___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC0__D_UPC_ATB_SEL___M 0x00600000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC0__D_UPC_ATB_SEL___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC0___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_UPC0___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0 (0x005E14C8) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0___POR 0x00FF00FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_IP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_QP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_IP___POR 0xF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_QP___POR 0xF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_IP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_QP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_IP___POR 0xF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_QP___POR 0xF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_IP___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_IP___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_QP___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_QP___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_IP___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_IP___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_QP___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_QP___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_IP___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_IP___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_QP___M 0x00000F00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_QP___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_IP___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_IP___S 4 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_QP___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_QP___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO0___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1 (0x005E14CC) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1___POR 0x00FF00FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_IN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_QN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_IN___POR 0xF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_QN___POR 0xF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_IN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_QN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_IN___POR 0xF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_QN___POR 0xF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_IN___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_IN___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_QN___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_QN___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_IN___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_IN___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_QN___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_QN___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_IN___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_IN___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_QN___M 0x00000F00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_QN___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_IN___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_IN___S 4 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_QN___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_QN___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_LO1___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL (0x005E14D0) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL___POR 0x04000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL__WL_CALRTX_GC___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL__WL_CALRTX_SW_FLP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL__WL_CALRTX_RES_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL__WL_CALRTX_IBIAS___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL__WL_CALRTX_GC___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL__WL_CALRTX_GC___S 30 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL__WL_CALRTX_SW_FLP___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL__WL_CALRTX_SW_FLP___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL__WL_CALRTX_RES_CTRL___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL__WL_CALRTX_RES_CTRL___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL__WL_CALRTX_IBIAS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL__WL_CALRTX_IBIAS___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL___S 26 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_SPARE (0x005E14D4) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_SPARE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_SPARE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_SPARE__D_TXFE_SPARE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_SPARE__D_TXFE_SPARE___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_SPARE__D_TXFE_SPARE___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_SPARE___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_SPARE___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PPA0 (0x005E14D8) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PPA0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PPA0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PPA0__WL_PPA_INPUT_SW_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PPA0__WL_PPA_INPUT_SW_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PPA0__WL_PPA_INPUT_SW_EN___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PPA0___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PPA0___S 31 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0 (0x005E14DC) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0___POR 0xAA000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_IBIAS_LOWER_LIM_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_IBIAS_LOWER_LIM___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_ISLOPE___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX0_PD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX1_PD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_IBIAS_BOOST___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_IBIAS_LOWER_LIM_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_IBIAS_LOWER_LIM_EN___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_IBIAS_LOWER_LIM___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_IBIAS_LOWER_LIM___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_ISLOPE___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_ISLOPE___S 25 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_ATB_SEL___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_ATB_SEL___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX0_PD___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX0_PD___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX1_PD___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX1_PD___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_IBIAS_BOOST___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0__WL_PA_IBIAS_BOOST___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_PA0___S 19 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY (0x005E14E0) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY__WL_DTOP_CAL_DUMMY1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY__WL_DTOP_CAL_DUMMY0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY__WL_DTOP_DUMMY1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY__WL_DTOP_DUMMY0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY__WL_DTOP_CAL_DUMMY1___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY__WL_DTOP_CAL_DUMMY1___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY__WL_DTOP_CAL_DUMMY0___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY__WL_DTOP_CAL_DUMMY0___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY__WL_DTOP_DUMMY1___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY__WL_DTOP_DUMMY1___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY__WL_DTOP_DUMMY0___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY__WL_DTOP_DUMMY0___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_CAL_DUMMY___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD (0x005E14E4) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD___POR 0x08B80000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_NOTCH_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_CALTXSHIFT_RES_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_TAIL_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_IBIAS_CTRL___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_DEGEN_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_VCAS_CTRL___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_ATTN_CTRL___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_NOTCH_CTRL___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_NOTCH_CTRL___S 30 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_CALTXSHIFT_RES_CTRL___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_CALTXSHIFT_RES_CTRL___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_TAIL_SW___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_TAIL_SW___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_IBIAS_CTRL___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_IBIAS_CTRL___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_DEGEN_CTRL___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_DEGEN_CTRL___S 25 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_VCAS_CTRL___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_VCAS_CTRL___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_ATTN_CTRL___M 0x00780000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD__D_WL_DPD2_IPA_ATTN_CTRL___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_DPD___S 19 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR (0x005E1500) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR___POR 0x6C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR__D_TS_REF_RTUNE___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR__D_TS_RTUNE___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR__D_TS_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR__TS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR__TS_SRC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR__D_TS_REF_RTUNE___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR__D_TS_REF_RTUNE___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR__D_TS_RTUNE___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR__D_TS_RTUNE___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR__D_TS_ATB_SEL___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR__D_TS_ATB_SEL___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR__TS_EN_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR__TS_EN_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR__TS_SRC_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR__TS_SRC_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR___M 0xFDF00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH0_WL_TXFE_TSENSOR___S 20 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CTRL_0 (0x005E2000) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CTRL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CTRL_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CTRL_0__TPC_STOP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CTRL_0__TPC_STOP___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CTRL_0__TPC_STOP___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CTRL_0___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CTRL_0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT (0x005E2004) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_TEMP_VALID___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_FULLPKT_PWR_VALID___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_PREAMBLE_PWR_VALID___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_TEMP___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_FULLPKT_PWR___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_PREAMBLE_PWR___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_TEMP_VALID___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_TEMP_VALID___S 26 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_FULLPKT_PWR_VALID___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_FULLPKT_PWR_VALID___S 25 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_PREAMBLE_PWR_VALID___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_PREAMBLE_PWR_VALID___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_TEMP___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_TEMP___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_FULLPKT_PWR___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_FULLPKT_PWR___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_PREAMBLE_PWR___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT__RO_PREAMBLE_PWR___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT___M 0x07FFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_RESULT___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0 (0x005E2040) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0___POR 0x000A0026 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__PDADC_CLK_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__PDADC_TEST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_HI_IN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_MID_IN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_LO_IN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_BIAS_COMP_IN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_BIAS_REFBUFF_IN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_PRECHARGEC_IN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ATEST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ATEST_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_SPARE___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_FSMODE_IN___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__PDADC_CLK_SEL___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__PDADC_CLK_SEL___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__PDADC_TEST_EN___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__PDADC_TEST_EN___S 30 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_HI_IN___M 0x38000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_HI_IN___S 27 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_MID_IN___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_MID_IN___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_LO_IN___M 0x00E00000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_LO_IN___S 21 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_BIAS_COMP_IN___M 0x00180000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_BIAS_COMP_IN___S 19 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_BIAS_REFBUFF_IN___M 0x00060000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_BIAS_REFBUFF_IN___S 17 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_PRECHARGEC_IN___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_PRECHARGEC_IN___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ATEST_EN___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ATEST_EN___S 15 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ATEST_SEL___M 0x00007800 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_ATEST_SEL___S 11 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_SPARE___M 0x000007F8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_SPARE___S 3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_FSMODE_IN___M 0x00000006 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0__D_ADC_FSMODE_IN___S 1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_0___S 1 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_1 (0x005E2044) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_1___POR 0x00004020 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_1__PDADC_CLK_POL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_1__ADC_DATA_COMP_REF_HI_GAIN___POR 0x020 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_1__ADC_DATA_COMP_REF_LO_GAIN___POR 0x020 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_1__PDADC_CLK_POL___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_1__PDADC_CLK_POL___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_1__ADC_DATA_COMP_REF_HI_GAIN___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_1__ADC_DATA_COMP_REF_HI_GAIN___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_1__ADC_DATA_COMP_REF_LO_GAIN___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_1__ADC_DATA_COMP_REF_LO_GAIN___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_1___M 0x0007FFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_PDADC_CTRL_1___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_PDADC_DATA (0x005E2048) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_PDADC_DATA___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_PDADC_DATA___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_PDADC_DATA__RO_D_PDADC_DATA___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_PDADC_DATA__RO_D_PDADC_DATA___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_PDADC_DATA__RO_D_PDADC_DATA___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_PDADC_DATA___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_PDADC_DATA___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0 (0x005E2080) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0___POR 0x0200E8B6 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_RESET_L___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CLK_CFG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_PATH_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_DAC_EN___POR 0xE +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_POL___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_BIN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_SETT___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_SMPL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__DC_OFFSET_MODE_MAX_ATTN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_RESET_L___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_RESET_L___S 25 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CLK_CFG___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CLK_CFG___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_PATH_SEL___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_PATH_SEL___S 22 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_EN___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_EN___S 17 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_DAC_EN___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_DAC_EN___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_POL___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_POL___S 10 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_BIN___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_BIN___S 7 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_SETT___M 0x00000070 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_SETT___S 4 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_SMPL___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__TPC_CAL_SMPL___S 1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__DC_OFFSET_MODE_MAX_ATTN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0__DC_OFFSET_MODE_MAX_ATTN___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0___M 0x03C2FCFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1 (0x005E2084) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1___POR 0x00F80204 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_LG___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_PGA_GAIN_CTRL_HG___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___POR 0x10 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG___S 22 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_LG___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__FE_SQ_GAIN_LG___S 20 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_PGA_GAIN_CTRL_HG___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_PGA_GAIN_CTRL_HG___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___M 0x000003E0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___S 5 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1___M 0x00FF03FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2 (0x005E2088) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2___POR 0xECA86420 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_7___POR 0xE +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_6___POR 0xC +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_5___POR 0xA +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_4___POR 0x8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_3___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_2___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_1___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_7___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_7___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_6___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_6___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_5___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_5___S 20 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_4___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_4___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_3___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_3___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_2___M 0x00000F00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_2___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_1___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_1___S 4 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_0___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2__WL_PWR_IDX_0___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_2___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_3 (0x005E208C) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT___S 4 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT_EN___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_3___M 0x000000F1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_CFG_3___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0 (0x005E2090) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_HI___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_HI_CAL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_HI_CAL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_LO___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_LO_CAL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_LO_CAL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_HI___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_HI___S 30 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_HI_CAL___M 0x0FE00000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_HI_CAL___S 21 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_HI_CAL___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_HI_CAL___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_LO___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_LO___S 14 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_LO_CAL___M 0x00000FE0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_LO_CAL___S 5 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_LO_CAL___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_LO_CAL___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0___M 0x4FFF4FFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_BE_CAL_RESULT_0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0 (0x005E2094) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__BE_INT_PDET_PATH_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__FE_SQ_XPA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__FE_SQ_IPA_IS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__FE_SQ_IPA_PO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__FE_VDET_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__PDADC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__BE_TIA_SQBIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__ADC_VREF_IN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__BE_INT_PDET_PATH_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__BE_INT_PDET_PATH_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__FE_SQ_XPA_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__FE_SQ_XPA_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__FE_SQ_IPA_IS_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__FE_SQ_IPA_IS_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__FE_SQ_IPA_PO_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__FE_SQ_IPA_PO_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__FE_VDET_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__FE_VDET_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__PDADC_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__PDADC_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__BE_TIA_SQBIAS_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__BE_TIA_SQBIAS_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__ADC_VREF_IN_EN_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0__ADC_VREF_IN_EN_OVS___S 4 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0___M 0xC03FFC30 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_0___S 4 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1 (0x005E2098) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__PDET_GAIN_IDX_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_SQ_XPA_DUMMY_CURRENT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_SQ_IPA_IS_DUMMY_CURRENT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_SQ_IPA_PO_DUMMY_CURRENT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_XPA_RF_DISCONNECT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_IPA_IS_RF_DISCONNECT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_IPA_PO_RF_DISCONNECT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__PDET_GAIN_IDX_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__PDET_GAIN_IDX_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_SQ_XPA_DUMMY_CURRENT_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_SQ_XPA_DUMMY_CURRENT_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_SQ_IPA_IS_DUMMY_CURRENT_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_SQ_IPA_IS_DUMMY_CURRENT_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_SQ_IPA_PO_DUMMY_CURRENT_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_SQ_IPA_PO_DUMMY_CURRENT_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_XPA_RF_DISCONNECT_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_XPA_RF_DISCONNECT_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_IPA_IS_RF_DISCONNECT_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_IPA_IS_RF_DISCONNECT_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_IPA_PO_RF_DISCONNECT_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1__FE_IPA_PO_RF_DISCONNECT_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1___M 0x0CFFF000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_1___S 12 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2 (0x005E209C) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2___POR 0x000C1010 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__FE_R50_ADJ_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__FE_R50_ADJ_OVD___POR 0x30 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OVD___POR 0x10 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OVD___POR 0x10 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__FE_R50_ADJ_OV___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__FE_R50_ADJ_OV___S 20 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__FE_R50_ADJ_OVD___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__FE_R50_ADJ_OVD___S 14 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OV___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OV___S 13 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OVD___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OVD___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OV___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OV___S 5 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OVD___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2___M 0x001FFF3F +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_2___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3 (0x005E20A0) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3___POR 0x0000B880 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__FE_SQ_IPA_PO_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__FE_SQ_IPA_IS_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__FE_SQ_XPA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_TIA_GAIN_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_PGA_GAIN_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC2_OFFSET_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__TPC_SQR_IC_N_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__TPC_SQR_IC_P_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__TPC_SQR_IPTS_N_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__TPC_SQR_IPTS_P_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OV___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OVD___POR 0x38 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OV___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__FE_SQ_IPA_PO_GAIN_OV___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__FE_SQ_IPA_PO_GAIN_OV___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__FE_SQ_IPA_IS_GAIN_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__FE_SQ_IPA_IS_GAIN_OV___S 27 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__FE_SQ_XPA_GAIN_OV___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__FE_SQ_XPA_GAIN_OV___S 26 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_TIA_GAIN_CTRL_OV___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_TIA_GAIN_CTRL_OV___S 25 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_PGA_GAIN_CTRL_OV___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_PGA_GAIN_CTRL_OV___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_OV___S 23 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC2_OFFSET_OV___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC2_OFFSET_OV___S 22 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__TPC_SQR_IC_N_CTRL_OV___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__TPC_SQR_IC_N_CTRL_OV___S 21 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__TPC_SQR_IC_P_CTRL_OV___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__TPC_SQR_IC_P_CTRL_OV___S 20 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__TPC_SQR_IPTS_N_CTRL_OV___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__TPC_SQR_IPTS_N_CTRL_OV___S 19 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__TPC_SQR_IPTS_P_CTRL_OV___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__TPC_SQR_IPTS_P_CTRL_OV___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OV___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OV___S 15 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OVD___M 0x00007F00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OVD___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OV___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OV___S 7 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OVD___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3___M 0x1FFCFFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_3___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4 (0x005E20A4) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4___POR 0x01010840 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_R50_ADJ_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OVD___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OVD___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OVD___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OVD___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_R50_ADJ_CTRL_OV___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_R50_ADJ_CTRL_OV___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OV___S 27 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OVD___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OVD___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OV___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OV___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OVD___M 0x0003C000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OVD___S 14 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OV___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OV___S 13 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OVD___M 0x00001E00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OVD___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OV___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OV___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OVD___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OVD___S 4 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4___M 0x1B07FFF0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OVERRIDE_4___S 4 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0 (0x005E20A8) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0___POR 0x1D186008 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_FORCE_EN_2P5_CURRENT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_TIA_FB_LOWER_IR_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_TIA_FB_LOWER_IC_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_TIA_FB_TOP_IR_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_TIA_FB_TOP_IC_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_VREF_SET___POR 0x8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__FE_R50_ADJ_HG___POR 0x30 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__FE_R50_ADJ_LG___POR 0x30 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_BW_SEL___POR 0x8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_FORCE_EN_2P5_CURRENT___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_FORCE_EN_2P5_CURRENT___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_TIA_FB_LOWER_IR_EN___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_TIA_FB_LOWER_IR_EN___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_TIA_FB_LOWER_IC_EN___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_TIA_FB_LOWER_IC_EN___S 27 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_TIA_FB_TOP_IR_EN___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_TIA_FB_TOP_IR_EN___S 26 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_TIA_FB_TOP_IC_EN___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_TIA_FB_TOP_IC_EN___S 25 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_VREF_SET___M 0x01E00000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_VREF_SET___S 21 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__FE_R50_ADJ_HG___M 0x001F8000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__FE_R50_ADJ_HG___S 15 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__FE_R50_ADJ_LG___M 0x00007E00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__FE_R50_ADJ_LG___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_BW_SEL___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0__D_BE_BW_SEL___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0___M 0x9FFFFE0F +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_1 (0x005E20AC) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_1___POR 0x00000840 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_1__D_BE_ATB_MUX_SEL___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_1__D_BE_S2DOFFSET_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_1__D_BE_VREF_DEC_SEL___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_1__D_BE_ATB_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_1__D_BE_ATB_MUX_SEL___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_1__D_BE_ATB_MUX_SEL___S 10 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_1__D_BE_S2DOFFSET_SEL___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_1__D_BE_S2DOFFSET_SEL___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_1__D_BE_VREF_DEC_SEL___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_1__D_BE_VREF_DEC_SEL___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_1__D_BE_ATB_SEL___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_1__D_BE_ATB_SEL___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_1___M 0x00000DFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_1___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0 (0x005E20B0) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0___POR 0x036E36DC +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_ATB_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASN_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASP_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_IDAC_CTRL___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_IC_LPF_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_REFGEN_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_IC_VCMOUTGEN_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_TIA_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_VDAC_CTRL___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_ATB_CTRL___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_ATB_CTRL___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASN_CTRL___M 0x00E00000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASN_CTRL___S 21 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASP_CTRL___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASP_CTRL___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_IDAC_CTRL___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_IDAC_CTRL___S 15 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_IC_LPF_CTRL___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_IC_LPF_CTRL___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_REFGEN_CTRL___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_REFGEN_CTRL___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_IC_VCMOUTGEN_CTRL___M 0x000001C0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_IC_VCMOUTGEN_CTRL___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_TIA_CTRL___M 0x00000038 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_TIA_CTRL___S 3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_VDAC_CTRL___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_VDAC_CTRL___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0___M 0x07FFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1 (0x005E20B4) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1___POR 0x0001B6DA +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_IC_PDBUFFER_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IC_PDBUFFER_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_IC_SPARE_0_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_IC_SPARE_1_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IR_ATB_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IR_REFGEN_CTRL___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_IC_PDBUFFER_CTRL___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_IC_PDBUFFER_CTRL___S 15 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IC_PDBUFFER_CTRL___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IC_PDBUFFER_CTRL___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_IC_SPARE_0_CTRL___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_IC_SPARE_0_CTRL___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_IC_SPARE_1_CTRL___M 0x000001C0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_IC_SPARE_1_CTRL___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IR_ATB_CTRL___M 0x00000038 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IR_ATB_CTRL___S 3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IR_REFGEN_CTRL___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IR_REFGEN_CTRL___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1___M 0x0003FFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_1___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2 (0x005E20B8) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2___POR 0x0001B6DC +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_VCMOUTGEN_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_IR_SPARE_0_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_IR_SPARE_1_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_IC_TIA_FB_BIAS___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_OFFSET_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_TIA_FB_BIAS___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_VCMOUTGEN_CTRL___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_VCMOUTGEN_CTRL___S 15 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_IR_SPARE_0_CTRL___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_IR_SPARE_0_CTRL___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_IR_SPARE_1_CTRL___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_IR_SPARE_1_CTRL___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_IC_TIA_FB_BIAS___M 0x000001C0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_IC_TIA_FB_BIAS___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_OFFSET_CTRL___M 0x00000038 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_OFFSET_CTRL___S 3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_TIA_FB_BIAS___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_TIA_FB_BIAS___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2___M 0x0003FFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_IC_IR_BIAS_CTRL_2___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2 (0x005E20BC) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2___POR 0x68000104 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__D_VDET_VREF___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__D_VDET_ROUT_SEL___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__D_VDET_RFIN_DISCONNECT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__D_TPCDPD_SPARE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__D_BE_IR_SQR_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__TPC_SQR_IC_N_CTRL_HG___POR 0x02 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__TPC_SQR_IC_N_CTRL_LG___POR 0x02 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__D_VDET_VREF___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__D_VDET_VREF___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__D_VDET_ROUT_SEL___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__D_VDET_ROUT_SEL___S 25 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__D_VDET_RFIN_DISCONNECT___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__D_VDET_RFIN_DISCONNECT___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__D_TPCDPD_SPARE___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__D_TPCDPD_SPARE___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__D_BE_IR_SQR_CTRL___M 0x0000E000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__D_BE_IR_SQR_CTRL___S 13 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__TPC_SQR_IC_N_CTRL_HG___M 0x00001F80 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__TPC_SQR_IC_N_CTRL_HG___S 7 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__TPC_SQR_IC_N_CTRL_LG___M 0x0000007E +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2__TPC_SQR_IC_N_CTRL_LG___S 1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_2___S 1 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3 (0x005E20C0) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3___POR 0x000C5000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__TPC_SQR_IC_P_CTRL_HG___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__TPC_SQR_IC_P_CTRL_LG___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__D_WL_DPD_GC___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__D_WL_DPD_IBIAS_INV___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__D_WL_DPD_IBIAS_GM___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__D_WL_DPD_RES_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__WL_DPD_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__WL_DPD_CALSHIFT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__TPC_SQR_IC_P_CTRL_HG___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__TPC_SQR_IC_P_CTRL_HG___S 26 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__TPC_SQR_IC_P_CTRL_LG___M 0x03F00000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__TPC_SQR_IC_P_CTRL_LG___S 20 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__D_WL_DPD_GC___M 0x000E0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__D_WL_DPD_GC___S 17 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__D_WL_DPD_IBIAS_INV___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__D_WL_DPD_IBIAS_INV___S 13 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__D_WL_DPD_IBIAS_GM___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__D_WL_DPD_IBIAS_GM___S 10 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__D_WL_DPD_RES_CTRL___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__D_WL_DPD_RES_CTRL___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__WL_DPD_EN_OVS___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__WL_DPD_EN_OVS___S 7 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__WL_DPD_CALSHIFT_OVS___M 0x00000060 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3__WL_DPD_CALSHIFT_OVS___S 5 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3___M 0xFFFE7FE0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_3___S 5 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_4 (0x005E20C4) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_4___POR 0x00000492 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_HG___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_LG___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_HG___POR 0x12 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_LG___POR 0x12 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_HG___M 0x00FC0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_HG___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_LG___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_LG___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_HG___M 0x00000FC0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_HG___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_LG___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_LG___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_4___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_AC_4___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OV_5 (0x005E20C8) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OV_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OV_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OV_5__TPC_BE_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OV_5__VDET_VREF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OV_5__TPC_BE_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OV_5__TPC_BE_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OV_5__VDET_VREF_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OV_5__VDET_VREF_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OV_5___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_OV_5___S 28 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST (0x005E20CC) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST__RBIST_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST__RBIST_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST__RBIST_OV___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST___S 31 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST_OV (0x005E20D0) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST_OV___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST_OV___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST_OV__RBIST_CLPC_PKT_TYPE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST_OV__RBIST_TPC_PDET_GAIN_IDX_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST_OV__RBIST_TPC_ATTEN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST_OV__RBIST_CLPC_PKT_TYPE_OVD___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST_OV__RBIST_CLPC_PKT_TYPE_OVD___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST_OV__RBIST_TPC_PDET_GAIN_IDX_OVD___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST_OV__RBIST_TPC_PDET_GAIN_IDX_OVD___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST_OV__RBIST_TPC_ATTEN_OVD___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST_OV__RBIST_TPC_ATTEN_OVD___S 4 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST_OV___M 0x000003F0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_RBIST_OV___S 4 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0 (0x005E2100) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0___POR 0x1B000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_BIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_POL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_SETT___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_SMPL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_REF___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_BIN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_BIN___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_POL___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_POL___S 30 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_SETT___M 0x38000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_SETT___S 27 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_SMPL___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_SMPL___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_EN___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_EN___S 23 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_REF___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0__LDO_CAL_REF___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0___M 0xFF8001FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_LDO_CAL_0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_LDO_CAL_0 (0x005E2104) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_LDO_CAL_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_LDO_CAL_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_PDADC_DATA___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_RESULT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_PDADC_DATA___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_PDADC_DATA___S 23 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_DONE___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_DONE___S 4 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_RESULT___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_RESULT___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_LDO_CAL_0___M 0xFF80001F +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_LDO_CAL_0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_MEASURE_0 (0x005E2140) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_MEASURE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_MEASURE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_MEASURE_0__SW_MEASURE_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_MEASURE_0__SW_MEASURE_TMR_SETTING___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_MEASURE_0__SW_MEASURE_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_MEASURE_0__SW_MEASURE_EN___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_MEASURE_0__SW_MEASURE_TMR_SETTING___M 0x60000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_MEASURE_0__SW_MEASURE_TMR_SETTING___S 29 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_MEASURE_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_MEASURE_0___S 29 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_MEASURE_0 (0x005E2144) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_MEASURE_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_MEASURE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_MEASURE_0__RO_SW_MEASURE_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_MEASURE_0__RO_SW_MEASURE_RESULT___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_MEASURE_0__RO_SW_MEASURE_DONE___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_MEASURE_0__RO_SW_MEASURE_DONE___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_MEASURE_0__RO_SW_MEASURE_RESULT___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_MEASURE_0__RO_SW_MEASURE_RESULT___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_MEASURE_0___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_MEASURE_0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_AVG_0 (0x005E2148) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_AVG_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_AVG_0___POR 0x08000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_AVG_0__SW_AVG_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_AVG_0__SW_AVG_CFG___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_AVG_0__SW_AVG_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_AVG_0__SW_AVG_EN___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_AVG_0__SW_AVG_CFG___M 0x78000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_AVG_0__SW_AVG_CFG___S 27 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_AVG_0___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_SW_AVG_0___S 27 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_AVG_0 (0x005E214C) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_AVG_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_AVG_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_AVG_0__RO_SW_AVG_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_AVG_0__RO_SW_AVG_RESULT___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_AVG_0__RO_SW_AVG_DONE___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_AVG_0__RO_SW_AVG_DONE___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_AVG_0__RO_SW_AVG_RESULT___M 0x7FC00000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_AVG_0__RO_SW_AVG_RESULT___S 22 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_AVG_0___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_SW_AVG_0___S 22 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1 (0x005E2180) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1___POR 0x073D11C0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PDADC_STROBE_INV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PWR_MEAS_TRIG_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PDACC_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__ATB_MEAS_DUR___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__THERM_MEAS_DUR___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__VOLT_MEAS_DUR___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PD_ACC_WINDOW_CCK___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PD_ACC_WINDOW_OFDM___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PD_DC_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PD_DC_WIN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PD_DC_START___POR 0xC0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PDADC_STROBE_INV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PDADC_STROBE_INV___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS___S 30 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET___S 29 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PWR_MEAS_TRIG_SW___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PWR_MEAS_TRIG_SW___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PDACC_MODE___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PDACC_MODE___S 27 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__ATB_MEAS_DUR___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__ATB_MEAS_DUR___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__THERM_MEAS_DUR___M 0x00E00000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__THERM_MEAS_DUR___S 21 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__VOLT_MEAS_DUR___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__VOLT_MEAS_DUR___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PD_ACC_WINDOW_CCK___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PD_ACC_WINDOW_CCK___S 15 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PD_ACC_WINDOW_OFDM___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PD_ACC_WINDOW_OFDM___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PD_DC_SEL___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PD_DC_SEL___S 11 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PD_DC_WIN___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PD_DC_WIN___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PD_DC_START___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1__PD_DC_START___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_1___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_2 (0x005E2184) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_2___POR 0x00900090 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_2__CLPC_START_OFDM___POR 0x0090 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_2__CLPC_START_CCK___POR 0x0090 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_2__CLPC_START_OFDM___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_2__CLPC_START_OFDM___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_2__CLPC_START_CCK___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_2__CLPC_START_CCK___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_2___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_3_STAT_B0 (0x005E2188) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_3_STAT_B0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_3_STAT_B0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_4_CNT_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_3_CNT_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_2_CNT_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_1_CNT_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_4_CNT_0___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_4_CNT_0___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_3_CNT_0___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_3_CNT_0___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_2_CNT_0___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_2_CNT_0___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_1_CNT_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_1_CNT_0___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_3_STAT_B0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_3_STAT_B0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4 (0x005E218C) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4___POR 0x22685349 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__OLPC_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__FULL_PKT_PWR_ACC_SYM_CNT___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__FULL_PKT_PWR_MEAS_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_PWR_INIT_DUR___POR 0x4D +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_DC_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_ACC_DC_WIN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_DC_INIT_DUR___POR 0x4D +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_ACC_WIN_CCK___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_ACC_WIN_OFDM___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__OLPC_MODE___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__OLPC_MODE___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__FULL_PKT_PWR_ACC_SYM_CNT___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__FULL_PKT_PWR_ACC_SYM_CNT___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__FULL_PKT_PWR_MEAS_EN___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__FULL_PKT_PWR_MEAS_EN___S 27 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_PWR_INIT_DUR___M 0x07F80000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_PWR_INIT_DUR___S 19 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_DC_SEL___M 0x00060000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_DC_SEL___S 17 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_ACC_DC_WIN___M 0x0001C000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_ACC_DC_WIN___S 14 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_DC_INIT_DUR___M 0x00003FC0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_DC_INIT_DUR___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_ACC_WIN_CCK___M 0x00000038 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_ACC_WIN_CCK___S 3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_ACC_WIN_OFDM___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4__PSYM_ACC_WIN_OFDM___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_4___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_5 (0x005E2190) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_5___POR 0x004D4D4D +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_5__FULL_PKT_PWR_INIT_DUR___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_5__ATB_INI_DUR___POR 0x4D +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_5__THERM_INI_DUR___POR 0x4D +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_5__VOLT_INI_DUR___POR 0x4D +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_5__FULL_PKT_PWR_INIT_DUR___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_5__FULL_PKT_PWR_INIT_DUR___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_5__ATB_INI_DUR___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_5__ATB_INI_DUR___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_5__THERM_INI_DUR___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_5__THERM_INI_DUR___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_5__VOLT_INI_DUR___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_5__VOLT_INI_DUR___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_5___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_5___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6 (0x005E2194) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6___POR 0x079E79E7 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__PDADC_STROBE_DLY_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__FULL_PKT_PWR_VALID_THR___POR 0x07 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__ATB_MEAS_DUR_MULTIPLIER___POR 0x27 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__THERM_MEAS_DUR_MULTIPLIER___POR 0x27 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__VOLT_MEAS_DUR_MULTIPLIER___POR 0x27 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__PD_DC_WIN_MULTIPLIER___POR 0x27 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__PDADC_STROBE_DLY_SEL___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__PDADC_STROBE_DLY_SEL___S 30 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__FULL_PKT_PWR_VALID_THR___M 0x3F000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__FULL_PKT_PWR_VALID_THR___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__ATB_MEAS_DUR_MULTIPLIER___M 0x00FC0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__ATB_MEAS_DUR_MULTIPLIER___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__THERM_MEAS_DUR_MULTIPLIER___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__THERM_MEAS_DUR_MULTIPLIER___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__VOLT_MEAS_DUR_MULTIPLIER___M 0x00000FC0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__VOLT_MEAS_DUR_MULTIPLIER___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__PD_DC_WIN_MULTIPLIER___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6__PD_DC_WIN_MULTIPLIER___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_6___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7 (0x005E2198) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7___POR 0x27C27C27 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7__PSYM_ACC_DC_WIN_MULTIPLIER___POR 0x27 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7__PSYM_ACC_WIN_CCK_MULTIPLIER___POR 0x30 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7__PSYM_ACC_WIN_OFDM_MULTIPLIER___POR 0x27 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7__PD_ACC_WINDOW_CCK_MULTIPLIER___POR 0x30 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7__PD_ACC_WINDOW_OFDM_MULTIPLIER___POR 0x27 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7__PSYM_ACC_DC_WIN_MULTIPLIER___M 0x3F000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7__PSYM_ACC_DC_WIN_MULTIPLIER___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7__PSYM_ACC_WIN_CCK_MULTIPLIER___M 0x00FC0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7__PSYM_ACC_WIN_CCK_MULTIPLIER___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7__PSYM_ACC_WIN_OFDM_MULTIPLIER___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7__PSYM_ACC_WIN_OFDM_MULTIPLIER___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7__PD_ACC_WINDOW_CCK_MULTIPLIER___M 0x00000FC0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7__PD_ACC_WINDOW_CCK_MULTIPLIER___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7__PD_ACC_WINDOW_OFDM_MULTIPLIER___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7__PD_ACC_WINDOW_OFDM_MULTIPLIER___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7___M 0x3FFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_7___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_8_B0 (0x005E219C) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_8_B0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_8_B0___POR 0x00008399 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_8_B0__PDADC_BIAS___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_8_B0__INIT_ATB_SETTING_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_8_B0__INIT_VOLT_SETTING_0___POR 0x83 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_8_B0__INIT_THERM_SETTING_0___POR 0x99 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_8_B0__PDADC_BIAS___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_8_B0__PDADC_BIAS___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_8_B0__INIT_ATB_SETTING_0___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_8_B0__INIT_ATB_SETTING_0___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_8_B0__INIT_VOLT_SETTING_0___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_8_B0__INIT_VOLT_SETTING_0___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_8_B0__INIT_THERM_SETTING_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_8_B0__INIT_THERM_SETTING_0___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_8_B0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_8_B0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_9 (0x005E21A0) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_9___POR 0x000001FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_9__PDADC_CLIP_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_9__PDADC_CLIP_THRES___POR 0x1FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_9__PDADC_CLIP_EN___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_9__PDADC_CLIP_EN___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_9__PDADC_CLIP_THRES___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_9__PDADC_CLIP_THRES___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_9___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_9___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_10_B0 (0x005E21A4) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_10_B0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_10_B0___POR 0x01010000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_10_B0__THERM_RESOLUTION_OFFSET___POR 0x80 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_10_B0__THERM_ADC_SCALED_GAIN_0___POR 0x100 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_10_B0__THERM_ADC_OFFSET_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_10_B0__THERM_RESOLUTION_OFFSET___M 0x01FE0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_10_B0__THERM_RESOLUTION_OFFSET___S 17 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_10_B0__THERM_ADC_SCALED_GAIN_0___M 0x0001FF00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_10_B0__THERM_ADC_SCALED_GAIN_0___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_10_B0__THERM_ADC_OFFSET_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_10_B0__THERM_ADC_OFFSET_0___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_10_B0___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_10_B0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_11_STAT_B0 (0x005E21A8) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_11_STAT_B0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_11_STAT_B0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_ATB_VALUE_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_VOLT_VALUE_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_THERM_VALUE_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_ATB_VALUE_0___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_ATB_VALUE_0___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_VOLT_VALUE_0___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_VOLT_VALUE_0___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_THERM_VALUE_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_THERM_VALUE_0___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_11_STAT_B0___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_11_STAT_B0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_12_STAT_B0 (0x005E21AC) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_12_STAT_B0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_12_STAT_B0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_12_STAT_B0__RO_FULL_PKT_AVG_OUT_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_12_STAT_B0__RO_LATEST_DC_VALUE_0___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_12_STAT_B0__RO_PDACC_AVG_OUT_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_12_STAT_B0__RO_FULL_PKT_AVG_OUT_0___M 0x01FE0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_12_STAT_B0__RO_FULL_PKT_AVG_OUT_0___S 17 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_12_STAT_B0__RO_LATEST_DC_VALUE_0___M 0x0001FF00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_12_STAT_B0__RO_LATEST_DC_VALUE_0___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_12_STAT_B0__RO_PDACC_AVG_OUT_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_12_STAT_B0__RO_PDACC_AVG_OUT_0___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_12_STAT_B0___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_12_STAT_B0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_13 (0x005E21B0) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_13___POR 0x00000001 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_13__TEMP_MEAS_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_13__TPCRB_DELAY___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_13__TEMP_MEAS_SEL___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_13__TEMP_MEAS_SEL___S 3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_13__TPCRB_DELAY___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_13__TPCRB_DELAY___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_13___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_TPC_FB_13___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14 (0x005E21B4) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_GNT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_CS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_FB_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_VALID___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_PKT_PWR_MEAS_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_PKT_PWR_MEAS_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_ATB_MEAS_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_THERM_MEAS_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_VOLT_MEAS_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_FB_ABORT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_ACC_NXT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_FB_CS___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_GNT___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_GNT___S 19 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_REQ___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_REQ___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_CS___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_CS___S 15 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_FB_ON___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_FB_ON___S 14 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_VALID___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_VALID___S 13 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_EN___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_EN___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_PKT_PWR_MEAS_DONE___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_PKT_PWR_MEAS_DONE___S 11 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_PKT_PWR_MEAS_ON___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_PKT_PWR_MEAS_ON___S 10 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_ATB_MEAS_ON___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_ATB_MEAS_ON___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_THERM_MEAS_ON___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_THERM_MEAS_ON___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_VOLT_MEAS_ON___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_VOLT_MEAS_ON___S 7 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_FB_ABORT___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_FB_ABORT___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_ACC_NXT___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_ACC_NXT___S 5 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_FB_CS___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14__RO_FB_CS___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH0_RO_TPC_FB_14___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_0 (0x005E4000) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_0__RX_DCOC_RANGE_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_0__RX_DCOC_RES_I_0___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_0__RX_DCOC_RES_Q_0___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_0__RX_DCOC_RANGE_0___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_0__RX_DCOC_RANGE_0___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_0__RX_DCOC_RES_I_0___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_0__RX_DCOC_RES_I_0___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_0__RX_DCOC_RES_Q_0___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_0__RX_DCOC_RES_Q_0___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_0___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1 (0x005E4004) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1__RX_DCOC_RANGE_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1__RX_DCOC_RES_I_1___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1__RX_DCOC_RES_Q_1___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1__RX_DCOC_RANGE_1___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1__RX_DCOC_RANGE_1___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1__RX_DCOC_RES_I_1___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1__RX_DCOC_RES_I_1___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1__RX_DCOC_RES_Q_1___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1__RX_DCOC_RES_Q_1___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_2 (0x005E4008) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_2__RX_DCOC_RANGE_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_2__RX_DCOC_RES_I_2___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_2__RX_DCOC_RES_Q_2___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_2__RX_DCOC_RANGE_2___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_2__RX_DCOC_RANGE_2___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_2__RX_DCOC_RES_I_2___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_2__RX_DCOC_RES_I_2___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_2__RX_DCOC_RES_Q_2___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_2__RX_DCOC_RES_Q_2___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_2___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_2___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_3 (0x005E400C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_3__RX_DCOC_RANGE_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_3__RX_DCOC_RES_I_3___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_3__RX_DCOC_RES_Q_3___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_3__RX_DCOC_RANGE_3___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_3__RX_DCOC_RANGE_3___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_3__RX_DCOC_RES_I_3___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_3__RX_DCOC_RES_I_3___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_3__RX_DCOC_RES_Q_3___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_3__RX_DCOC_RES_Q_3___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_3___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_3___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_4 (0x005E4010) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_4__RX_DCOC_RANGE_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_4__RX_DCOC_RES_I_4___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_4__RX_DCOC_RES_Q_4___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_4__RX_DCOC_RANGE_4___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_4__RX_DCOC_RANGE_4___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_4__RX_DCOC_RES_I_4___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_4__RX_DCOC_RES_I_4___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_4__RX_DCOC_RES_Q_4___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_4__RX_DCOC_RES_Q_4___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_4___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_4___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_5 (0x005E4014) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_5__RX_DCOC_RANGE_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_5__RX_DCOC_RES_I_5___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_5__RX_DCOC_RES_Q_5___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_5__RX_DCOC_RANGE_5___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_5__RX_DCOC_RANGE_5___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_5__RX_DCOC_RES_I_5___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_5__RX_DCOC_RES_I_5___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_5__RX_DCOC_RES_Q_5___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_5__RX_DCOC_RES_Q_5___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_5___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_5___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_6 (0x005E4018) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_6__RX_DCOC_RANGE_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_6__RX_DCOC_RES_I_6___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_6__RX_DCOC_RES_Q_6___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_6__RX_DCOC_RANGE_6___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_6__RX_DCOC_RANGE_6___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_6__RX_DCOC_RES_I_6___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_6__RX_DCOC_RES_I_6___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_6__RX_DCOC_RES_Q_6___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_6__RX_DCOC_RES_Q_6___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_6___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_6___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_7 (0x005E401C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_7__RX_DCOC_RANGE_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_7__RX_DCOC_RES_I_7___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_7__RX_DCOC_RES_Q_7___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_7__RX_DCOC_RANGE_7___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_7__RX_DCOC_RANGE_7___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_7__RX_DCOC_RES_I_7___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_7__RX_DCOC_RES_I_7___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_7__RX_DCOC_RES_Q_7___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_7__RX_DCOC_RES_Q_7___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_7___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_7___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_8 (0x005E4020) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_8__RX_DCOC_RANGE_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_8__RX_DCOC_RES_I_8___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_8__RX_DCOC_RES_Q_8___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_8__RX_DCOC_RANGE_8___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_8__RX_DCOC_RANGE_8___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_8__RX_DCOC_RES_I_8___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_8__RX_DCOC_RES_I_8___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_8__RX_DCOC_RES_Q_8___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_8__RX_DCOC_RES_Q_8___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_8___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_8___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_9 (0x005E4024) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_9__RX_DCOC_RANGE_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_9__RX_DCOC_RES_I_9___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_9__RX_DCOC_RES_Q_9___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_9__RX_DCOC_RANGE_9___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_9__RX_DCOC_RANGE_9___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_9__RX_DCOC_RES_I_9___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_9__RX_DCOC_RES_I_9___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_9__RX_DCOC_RES_Q_9___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_9__RX_DCOC_RES_Q_9___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_9___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_9___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_10 (0x005E4028) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_10__RX_DCOC_RANGE_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_10__RX_DCOC_RES_I_10___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_10__RX_DCOC_RES_Q_10___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_10__RX_DCOC_RANGE_10___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_10__RX_DCOC_RANGE_10___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_10__RX_DCOC_RES_I_10___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_10__RX_DCOC_RES_I_10___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_10__RX_DCOC_RES_Q_10___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_10__RX_DCOC_RES_Q_10___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_10___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_10___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_11 (0x005E402C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_11__RX_DCOC_RANGE_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_11__RX_DCOC_RES_I_11___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_11__RX_DCOC_RES_Q_11___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_11__RX_DCOC_RANGE_11___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_11__RX_DCOC_RANGE_11___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_11__RX_DCOC_RES_I_11___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_11__RX_DCOC_RES_I_11___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_11__RX_DCOC_RES_Q_11___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_11__RX_DCOC_RES_Q_11___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_11___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_11___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_12 (0x005E4030) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_12__RX_DCOC_RANGE_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_12__RX_DCOC_RES_I_12___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_12__RX_DCOC_RES_Q_12___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_12__RX_DCOC_RANGE_12___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_12__RX_DCOC_RANGE_12___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_12__RX_DCOC_RES_I_12___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_12__RX_DCOC_RES_I_12___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_12__RX_DCOC_RES_Q_12___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_12__RX_DCOC_RES_Q_12___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_12___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_12___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_13 (0x005E4034) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_13__RX_DCOC_RANGE_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_13__RX_DCOC_RES_I_13___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_13__RX_DCOC_RES_Q_13___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_13__RX_DCOC_RANGE_13___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_13__RX_DCOC_RANGE_13___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_13__RX_DCOC_RES_I_13___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_13__RX_DCOC_RES_I_13___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_13__RX_DCOC_RES_Q_13___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_13__RX_DCOC_RES_Q_13___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_13___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_13___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_14 (0x005E4038) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_14__RX_DCOC_RANGE_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_14__RX_DCOC_RES_I_14___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_14__RX_DCOC_RES_Q_14___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_14__RX_DCOC_RANGE_14___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_14__RX_DCOC_RANGE_14___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_14__RX_DCOC_RES_I_14___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_14__RX_DCOC_RES_I_14___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_14__RX_DCOC_RES_Q_14___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_14__RX_DCOC_RES_Q_14___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_14___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_14___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_15 (0x005E403C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_15__RX_DCOC_RANGE_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_15__RX_DCOC_RES_I_15___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_15__RX_DCOC_RES_Q_15___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_15__RX_DCOC_RANGE_15___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_15__RX_DCOC_RANGE_15___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_15__RX_DCOC_RES_I_15___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_15__RX_DCOC_RES_I_15___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_15__RX_DCOC_RES_Q_15___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_15__RX_DCOC_RES_Q_15___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_15___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_15___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_16 (0x005E4040) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_16___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_16__RX_DCOC_RANGE_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_16__RX_DCOC_RES_I_16___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_16__RX_DCOC_RES_Q_16___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_16__RX_DCOC_RANGE_16___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_16__RX_DCOC_RANGE_16___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_16__RX_DCOC_RES_I_16___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_16__RX_DCOC_RES_I_16___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_16__RX_DCOC_RES_Q_16___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_16__RX_DCOC_RES_Q_16___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_16___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_16___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_17 (0x005E4044) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_17___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_17__RX_DCOC_RANGE_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_17__RX_DCOC_RES_I_17___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_17__RX_DCOC_RES_Q_17___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_17__RX_DCOC_RANGE_17___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_17__RX_DCOC_RANGE_17___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_17__RX_DCOC_RES_I_17___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_17__RX_DCOC_RES_I_17___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_17__RX_DCOC_RES_Q_17___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_17__RX_DCOC_RES_Q_17___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_17___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_17___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_18 (0x005E4048) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_18___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_18__RX_DCOC_RANGE_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_18__RX_DCOC_RES_I_18___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_18__RX_DCOC_RES_Q_18___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_18__RX_DCOC_RANGE_18___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_18__RX_DCOC_RANGE_18___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_18__RX_DCOC_RES_I_18___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_18__RX_DCOC_RES_I_18___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_18__RX_DCOC_RES_Q_18___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_18__RX_DCOC_RES_Q_18___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_18___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_18___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_19 (0x005E404C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_19___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_19__RX_DCOC_RANGE_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_19__RX_DCOC_RES_I_19___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_19__RX_DCOC_RES_Q_19___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_19__RX_DCOC_RANGE_19___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_19__RX_DCOC_RANGE_19___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_19__RX_DCOC_RES_I_19___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_19__RX_DCOC_RES_I_19___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_19__RX_DCOC_RES_Q_19___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_19__RX_DCOC_RES_Q_19___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_19___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_19___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_20 (0x005E4050) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_20___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_20__RX_DCOC_RANGE_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_20__RX_DCOC_RES_I_20___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_20__RX_DCOC_RES_Q_20___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_20__RX_DCOC_RANGE_20___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_20__RX_DCOC_RANGE_20___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_20__RX_DCOC_RES_I_20___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_20__RX_DCOC_RES_I_20___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_20__RX_DCOC_RES_Q_20___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_20__RX_DCOC_RES_Q_20___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_20___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_20___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_21 (0x005E4054) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_21___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_21__RX_DCOC_RANGE_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_21__RX_DCOC_RES_I_21___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_21__RX_DCOC_RES_Q_21___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_21__RX_DCOC_RANGE_21___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_21__RX_DCOC_RANGE_21___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_21__RX_DCOC_RES_I_21___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_21__RX_DCOC_RES_I_21___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_21__RX_DCOC_RES_Q_21___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_21__RX_DCOC_RES_Q_21___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_21___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_21___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_22 (0x005E4058) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_22___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_22__RX_DCOC_RANGE_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_22__RX_DCOC_RES_I_22___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_22__RX_DCOC_RES_Q_22___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_22__RX_DCOC_RANGE_22___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_22__RX_DCOC_RANGE_22___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_22__RX_DCOC_RES_I_22___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_22__RX_DCOC_RES_I_22___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_22__RX_DCOC_RES_Q_22___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_22__RX_DCOC_RES_Q_22___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_22___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_22___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_23 (0x005E405C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_23___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_23__RX_DCOC_RANGE_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_23__RX_DCOC_RES_I_23___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_23__RX_DCOC_RES_Q_23___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_23__RX_DCOC_RANGE_23___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_23__RX_DCOC_RANGE_23___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_23__RX_DCOC_RES_I_23___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_23__RX_DCOC_RES_I_23___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_23__RX_DCOC_RES_Q_23___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_23__RX_DCOC_RES_Q_23___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_23___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_23___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_24 (0x005E4060) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_24___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_24__RX_DCOC_RANGE_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_24__RX_DCOC_RES_I_24___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_24__RX_DCOC_RES_Q_24___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_24__RX_DCOC_RANGE_24___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_24__RX_DCOC_RANGE_24___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_24__RX_DCOC_RES_I_24___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_24__RX_DCOC_RES_I_24___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_24__RX_DCOC_RES_Q_24___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_24__RX_DCOC_RES_Q_24___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_24___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_24___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_25 (0x005E4064) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_25___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_25__RX_DCOC_RANGE_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_25__RX_DCOC_RES_I_25___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_25__RX_DCOC_RES_Q_25___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_25__RX_DCOC_RANGE_25___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_25__RX_DCOC_RANGE_25___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_25__RX_DCOC_RES_I_25___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_25__RX_DCOC_RES_I_25___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_25__RX_DCOC_RES_Q_25___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_25__RX_DCOC_RES_Q_25___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_25___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_25___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_26 (0x005E4068) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_26___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_26__RX_DCOC_RANGE_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_26__RX_DCOC_RES_I_26___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_26__RX_DCOC_RES_Q_26___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_26__RX_DCOC_RANGE_26___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_26__RX_DCOC_RANGE_26___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_26__RX_DCOC_RES_I_26___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_26__RX_DCOC_RES_I_26___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_26__RX_DCOC_RES_Q_26___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_26__RX_DCOC_RES_Q_26___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_26___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_26___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_27 (0x005E406C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_27___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_27__RX_DCOC_RANGE_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_27__RX_DCOC_RES_I_27___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_27__RX_DCOC_RES_Q_27___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_27__RX_DCOC_RANGE_27___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_27__RX_DCOC_RANGE_27___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_27__RX_DCOC_RES_I_27___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_27__RX_DCOC_RES_I_27___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_27__RX_DCOC_RES_Q_27___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_27__RX_DCOC_RES_Q_27___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_27___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_27___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_28 (0x005E4070) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_28___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_28__RX_DCOC_RANGE_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_28__RX_DCOC_RES_I_28___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_28__RX_DCOC_RES_Q_28___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_28__RX_DCOC_RANGE_28___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_28__RX_DCOC_RANGE_28___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_28__RX_DCOC_RES_I_28___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_28__RX_DCOC_RES_I_28___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_28__RX_DCOC_RES_Q_28___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_28__RX_DCOC_RES_Q_28___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_28___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_28___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_29 (0x005E4074) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_29___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_29__RX_DCOC_RANGE_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_29__RX_DCOC_RES_I_29___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_29__RX_DCOC_RES_Q_29___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_29__RX_DCOC_RANGE_29___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_29__RX_DCOC_RANGE_29___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_29__RX_DCOC_RES_I_29___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_29__RX_DCOC_RES_I_29___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_29__RX_DCOC_RES_Q_29___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_29__RX_DCOC_RES_Q_29___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_29___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_29___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_30 (0x005E4078) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_30___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_30__RX_DCOC_RANGE_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_30__RX_DCOC_RES_I_30___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_30__RX_DCOC_RES_Q_30___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_30__RX_DCOC_RANGE_30___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_30__RX_DCOC_RANGE_30___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_30__RX_DCOC_RES_I_30___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_30__RX_DCOC_RES_I_30___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_30__RX_DCOC_RES_Q_30___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_30__RX_DCOC_RES_Q_30___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_30___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_30___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_31 (0x005E407C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_31___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_31__RX_DCOC_RANGE_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_31__RX_DCOC_RES_I_31___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_31__RX_DCOC_RES_Q_31___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_31__RX_DCOC_RANGE_31___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_31__RX_DCOC_RANGE_31___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_31__RX_DCOC_RES_I_31___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_31__RX_DCOC_RES_I_31___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_31__RX_DCOC_RES_Q_31___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_31__RX_DCOC_RES_Q_31___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_31___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_31___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_32 (0x005E4080) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_32___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_32___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_32__RX_DCOC_RANGE_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_32__RX_DCOC_RES_I_32___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_32__RX_DCOC_RES_Q_32___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_32__RX_DCOC_RANGE_32___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_32__RX_DCOC_RANGE_32___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_32__RX_DCOC_RES_I_32___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_32__RX_DCOC_RES_I_32___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_32__RX_DCOC_RES_Q_32___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_32__RX_DCOC_RES_Q_32___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_32___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_32___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_33 (0x005E4084) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_33___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_33___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_33__RX_DCOC_RANGE_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_33__RX_DCOC_RES_I_33___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_33__RX_DCOC_RES_Q_33___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_33__RX_DCOC_RANGE_33___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_33__RX_DCOC_RANGE_33___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_33__RX_DCOC_RES_I_33___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_33__RX_DCOC_RES_I_33___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_33__RX_DCOC_RES_Q_33___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_33__RX_DCOC_RES_Q_33___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_33___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_33___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_34 (0x005E4088) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_34___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_34___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_34__RX_DCOC_RANGE_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_34__RX_DCOC_RES_I_34___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_34__RX_DCOC_RES_Q_34___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_34__RX_DCOC_RANGE_34___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_34__RX_DCOC_RANGE_34___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_34__RX_DCOC_RES_I_34___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_34__RX_DCOC_RES_I_34___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_34__RX_DCOC_RES_Q_34___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_34__RX_DCOC_RES_Q_34___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_34___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_34___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_35 (0x005E408C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_35___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_35___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_35__RX_DCOC_RANGE_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_35__RX_DCOC_RES_I_35___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_35__RX_DCOC_RES_Q_35___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_35__RX_DCOC_RANGE_35___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_35__RX_DCOC_RANGE_35___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_35__RX_DCOC_RES_I_35___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_35__RX_DCOC_RES_I_35___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_35__RX_DCOC_RES_Q_35___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_35__RX_DCOC_RES_Q_35___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_35___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_35___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_36 (0x005E4090) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_36___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_36___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_36__RX_DCOC_RANGE_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_36__RX_DCOC_RES_I_36___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_36__RX_DCOC_RES_Q_36___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_36__RX_DCOC_RANGE_36___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_36__RX_DCOC_RANGE_36___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_36__RX_DCOC_RES_I_36___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_36__RX_DCOC_RES_I_36___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_36__RX_DCOC_RES_Q_36___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_36__RX_DCOC_RES_Q_36___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_36___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_36___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_37 (0x005E4094) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_37___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_37___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_37__RX_DCOC_RANGE_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_37__RX_DCOC_RES_I_37___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_37__RX_DCOC_RES_Q_37___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_37__RX_DCOC_RANGE_37___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_37__RX_DCOC_RANGE_37___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_37__RX_DCOC_RES_I_37___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_37__RX_DCOC_RES_I_37___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_37__RX_DCOC_RES_Q_37___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_37__RX_DCOC_RES_Q_37___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_37___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_37___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_38 (0x005E4098) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_38___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_38___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_38__RX_DCOC_RANGE_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_38__RX_DCOC_RES_I_38___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_38__RX_DCOC_RES_Q_38___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_38__RX_DCOC_RANGE_38___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_38__RX_DCOC_RANGE_38___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_38__RX_DCOC_RES_I_38___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_38__RX_DCOC_RES_I_38___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_38__RX_DCOC_RES_Q_38___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_38__RX_DCOC_RES_Q_38___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_38___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_38___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_39 (0x005E409C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_39___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_39___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_39__RX_DCOC_RANGE_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_39__RX_DCOC_RES_I_39___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_39__RX_DCOC_RES_Q_39___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_39__RX_DCOC_RANGE_39___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_39__RX_DCOC_RANGE_39___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_39__RX_DCOC_RES_I_39___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_39__RX_DCOC_RES_I_39___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_39__RX_DCOC_RES_Q_39___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_39__RX_DCOC_RES_Q_39___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_39___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_39___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_40 (0x005E40A0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_40___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_40___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_40__RX_DCOC_RANGE_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_40__RX_DCOC_RES_I_40___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_40__RX_DCOC_RES_Q_40___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_40__RX_DCOC_RANGE_40___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_40__RX_DCOC_RANGE_40___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_40__RX_DCOC_RES_I_40___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_40__RX_DCOC_RES_I_40___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_40__RX_DCOC_RES_Q_40___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_40__RX_DCOC_RES_Q_40___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_40___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_40___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_41 (0x005E40A4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_41___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_41___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_41__RX_DCOC_RANGE_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_41__RX_DCOC_RES_I_41___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_41__RX_DCOC_RES_Q_41___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_41__RX_DCOC_RANGE_41___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_41__RX_DCOC_RANGE_41___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_41__RX_DCOC_RES_I_41___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_41__RX_DCOC_RES_I_41___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_41__RX_DCOC_RES_Q_41___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_41__RX_DCOC_RES_Q_41___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_41___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_41___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_42 (0x005E40A8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_42___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_42___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_42__RX_DCOC_RANGE_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_42__RX_DCOC_RES_I_42___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_42__RX_DCOC_RES_Q_42___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_42__RX_DCOC_RANGE_42___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_42__RX_DCOC_RANGE_42___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_42__RX_DCOC_RES_I_42___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_42__RX_DCOC_RES_I_42___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_42__RX_DCOC_RES_Q_42___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_42__RX_DCOC_RES_Q_42___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_42___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_42___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_43 (0x005E40AC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_43___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_43___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_43__RX_DCOC_RANGE_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_43__RX_DCOC_RES_I_43___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_43__RX_DCOC_RES_Q_43___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_43__RX_DCOC_RANGE_43___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_43__RX_DCOC_RANGE_43___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_43__RX_DCOC_RES_I_43___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_43__RX_DCOC_RES_I_43___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_43__RX_DCOC_RES_Q_43___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_43__RX_DCOC_RES_Q_43___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_43___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_43___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_44 (0x005E40B0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_44___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_44___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_44__RX_DCOC_RANGE_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_44__RX_DCOC_RES_I_44___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_44__RX_DCOC_RES_Q_44___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_44__RX_DCOC_RANGE_44___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_44__RX_DCOC_RANGE_44___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_44__RX_DCOC_RES_I_44___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_44__RX_DCOC_RES_I_44___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_44__RX_DCOC_RES_Q_44___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_44__RX_DCOC_RES_Q_44___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_44___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_44___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_45 (0x005E40B4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_45___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_45___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_45__RX_DCOC_RANGE_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_45__RX_DCOC_RES_I_45___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_45__RX_DCOC_RES_Q_45___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_45__RX_DCOC_RANGE_45___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_45__RX_DCOC_RANGE_45___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_45__RX_DCOC_RES_I_45___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_45__RX_DCOC_RES_I_45___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_45__RX_DCOC_RES_Q_45___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_45__RX_DCOC_RES_Q_45___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_45___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_45___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_46 (0x005E40B8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_46___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_46___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_46__RX_DCOC_RANGE_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_46__RX_DCOC_RES_I_46___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_46__RX_DCOC_RES_Q_46___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_46__RX_DCOC_RANGE_46___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_46__RX_DCOC_RANGE_46___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_46__RX_DCOC_RES_I_46___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_46__RX_DCOC_RES_I_46___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_46__RX_DCOC_RES_Q_46___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_46__RX_DCOC_RES_Q_46___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_46___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_46___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_47 (0x005E40BC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_47___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_47___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_47__RX_DCOC_RANGE_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_47__RX_DCOC_RES_I_47___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_47__RX_DCOC_RES_Q_47___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_47__RX_DCOC_RANGE_47___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_47__RX_DCOC_RANGE_47___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_47__RX_DCOC_RES_I_47___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_47__RX_DCOC_RES_I_47___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_47__RX_DCOC_RES_Q_47___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_47__RX_DCOC_RES_Q_47___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_47___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_47___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_48 (0x005E40C0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_48___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_48___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_48__RX_DCOC_RANGE_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_48__RX_DCOC_RES_I_48___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_48__RX_DCOC_RES_Q_48___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_48__RX_DCOC_RANGE_48___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_48__RX_DCOC_RANGE_48___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_48__RX_DCOC_RES_I_48___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_48__RX_DCOC_RES_I_48___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_48__RX_DCOC_RES_Q_48___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_48__RX_DCOC_RES_Q_48___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_48___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_48___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_49 (0x005E40C4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_49___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_49___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_49__RX_DCOC_RANGE_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_49__RX_DCOC_RES_I_49___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_49__RX_DCOC_RES_Q_49___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_49__RX_DCOC_RANGE_49___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_49__RX_DCOC_RANGE_49___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_49__RX_DCOC_RES_I_49___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_49__RX_DCOC_RES_I_49___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_49__RX_DCOC_RES_Q_49___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_49__RX_DCOC_RES_Q_49___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_49___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_49___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_50 (0x005E40C8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_50___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_50___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_50__RX_DCOC_RANGE_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_50__RX_DCOC_RES_I_50___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_50__RX_DCOC_RES_Q_50___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_50__RX_DCOC_RANGE_50___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_50__RX_DCOC_RANGE_50___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_50__RX_DCOC_RES_I_50___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_50__RX_DCOC_RES_I_50___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_50__RX_DCOC_RES_Q_50___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_50__RX_DCOC_RES_Q_50___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_50___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_50___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_51 (0x005E40CC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_51___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_51___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_51__RX_DCOC_RANGE_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_51__RX_DCOC_RES_I_51___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_51__RX_DCOC_RES_Q_51___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_51__RX_DCOC_RANGE_51___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_51__RX_DCOC_RANGE_51___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_51__RX_DCOC_RES_I_51___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_51__RX_DCOC_RES_I_51___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_51__RX_DCOC_RES_Q_51___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_51__RX_DCOC_RES_Q_51___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_51___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_51___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_52 (0x005E40D0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_52___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_52___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_52__RX_DCOC_RANGE_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_52__RX_DCOC_RES_I_52___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_52__RX_DCOC_RES_Q_52___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_52__RX_DCOC_RANGE_52___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_52__RX_DCOC_RANGE_52___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_52__RX_DCOC_RES_I_52___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_52__RX_DCOC_RES_I_52___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_52__RX_DCOC_RES_Q_52___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_52__RX_DCOC_RES_Q_52___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_52___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_52___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_53 (0x005E40D4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_53___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_53___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_53__RX_DCOC_RANGE_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_53__RX_DCOC_RES_I_53___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_53__RX_DCOC_RES_Q_53___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_53__RX_DCOC_RANGE_53___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_53__RX_DCOC_RANGE_53___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_53__RX_DCOC_RES_I_53___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_53__RX_DCOC_RES_I_53___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_53__RX_DCOC_RES_Q_53___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_53__RX_DCOC_RES_Q_53___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_53___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_53___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_54 (0x005E40D8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_54___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_54___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_54__RX_DCOC_RANGE_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_54__RX_DCOC_RES_I_54___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_54__RX_DCOC_RES_Q_54___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_54__RX_DCOC_RANGE_54___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_54__RX_DCOC_RANGE_54___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_54__RX_DCOC_RES_I_54___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_54__RX_DCOC_RES_I_54___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_54__RX_DCOC_RES_Q_54___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_54__RX_DCOC_RES_Q_54___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_54___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_54___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_55 (0x005E40DC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_55___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_55___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_55__RX_DCOC_RANGE_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_55__RX_DCOC_RES_I_55___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_55__RX_DCOC_RES_Q_55___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_55__RX_DCOC_RANGE_55___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_55__RX_DCOC_RANGE_55___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_55__RX_DCOC_RES_I_55___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_55__RX_DCOC_RES_I_55___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_55__RX_DCOC_RES_Q_55___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_55__RX_DCOC_RES_Q_55___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_55___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_55___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_56 (0x005E40E0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_56___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_56___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_56__RX_DCOC_RANGE_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_56__RX_DCOC_RES_I_56___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_56__RX_DCOC_RES_Q_56___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_56__RX_DCOC_RANGE_56___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_56__RX_DCOC_RANGE_56___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_56__RX_DCOC_RES_I_56___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_56__RX_DCOC_RES_I_56___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_56__RX_DCOC_RES_Q_56___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_56__RX_DCOC_RES_Q_56___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_56___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_56___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_57 (0x005E40E4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_57___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_57___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_57__RX_DCOC_RANGE_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_57__RX_DCOC_RES_I_57___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_57__RX_DCOC_RES_Q_57___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_57__RX_DCOC_RANGE_57___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_57__RX_DCOC_RANGE_57___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_57__RX_DCOC_RES_I_57___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_57__RX_DCOC_RES_I_57___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_57__RX_DCOC_RES_Q_57___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_57__RX_DCOC_RES_Q_57___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_57___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_57___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_58 (0x005E40E8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_58___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_58___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_58__RX_DCOC_RANGE_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_58__RX_DCOC_RES_I_58___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_58__RX_DCOC_RES_Q_58___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_58__RX_DCOC_RANGE_58___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_58__RX_DCOC_RANGE_58___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_58__RX_DCOC_RES_I_58___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_58__RX_DCOC_RES_I_58___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_58__RX_DCOC_RES_Q_58___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_58__RX_DCOC_RES_Q_58___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_58___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_58___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_59 (0x005E40EC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_59___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_59___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_59__RX_DCOC_RANGE_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_59__RX_DCOC_RES_I_59___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_59__RX_DCOC_RES_Q_59___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_59__RX_DCOC_RANGE_59___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_59__RX_DCOC_RANGE_59___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_59__RX_DCOC_RES_I_59___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_59__RX_DCOC_RES_I_59___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_59__RX_DCOC_RES_Q_59___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_59__RX_DCOC_RES_Q_59___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_59___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_59___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_60 (0x005E40F0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_60___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_60___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_60__RX_DCOC_RANGE_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_60__RX_DCOC_RES_I_60___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_60__RX_DCOC_RES_Q_60___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_60__RX_DCOC_RANGE_60___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_60__RX_DCOC_RANGE_60___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_60__RX_DCOC_RES_I_60___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_60__RX_DCOC_RES_I_60___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_60__RX_DCOC_RES_Q_60___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_60__RX_DCOC_RES_Q_60___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_60___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_60___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_61 (0x005E40F4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_61___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_61___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_61__RX_DCOC_RANGE_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_61__RX_DCOC_RES_I_61___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_61__RX_DCOC_RES_Q_61___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_61__RX_DCOC_RANGE_61___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_61__RX_DCOC_RANGE_61___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_61__RX_DCOC_RES_I_61___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_61__RX_DCOC_RES_I_61___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_61__RX_DCOC_RES_Q_61___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_61__RX_DCOC_RES_Q_61___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_61___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_61___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_62 (0x005E40F8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_62___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_62___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_62__RX_DCOC_RANGE_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_62__RX_DCOC_RES_I_62___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_62__RX_DCOC_RES_Q_62___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_62__RX_DCOC_RANGE_62___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_62__RX_DCOC_RANGE_62___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_62__RX_DCOC_RES_I_62___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_62__RX_DCOC_RES_I_62___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_62__RX_DCOC_RES_Q_62___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_62__RX_DCOC_RES_Q_62___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_62___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_62___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_63 (0x005E40FC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_63___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_63___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_63__RX_DCOC_RANGE_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_63__RX_DCOC_RES_I_63___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_63__RX_DCOC_RES_Q_63___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_63__RX_DCOC_RANGE_63___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_63__RX_DCOC_RANGE_63___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_63__RX_DCOC_RES_I_63___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_63__RX_DCOC_RES_I_63___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_63__RX_DCOC_RES_Q_63___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_63__RX_DCOC_RES_Q_63___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_63___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_63___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_64 (0x005E4100) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_64___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_64___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_64__RX_DCOC_RANGE_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_64__RX_DCOC_RES_I_64___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_64__RX_DCOC_RES_Q_64___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_64__RX_DCOC_RANGE_64___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_64__RX_DCOC_RANGE_64___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_64__RX_DCOC_RES_I_64___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_64__RX_DCOC_RES_I_64___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_64__RX_DCOC_RES_Q_64___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_64__RX_DCOC_RES_Q_64___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_64___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_64___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_65 (0x005E4104) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_65___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_65___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_65__RX_DCOC_RANGE_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_65__RX_DCOC_RES_I_65___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_65__RX_DCOC_RES_Q_65___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_65__RX_DCOC_RANGE_65___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_65__RX_DCOC_RANGE_65___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_65__RX_DCOC_RES_I_65___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_65__RX_DCOC_RES_I_65___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_65__RX_DCOC_RES_Q_65___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_65__RX_DCOC_RES_Q_65___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_65___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_65___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_66 (0x005E4108) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_66___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_66___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_66__RX_DCOC_RANGE_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_66__RX_DCOC_RES_I_66___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_66__RX_DCOC_RES_Q_66___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_66__RX_DCOC_RANGE_66___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_66__RX_DCOC_RANGE_66___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_66__RX_DCOC_RES_I_66___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_66__RX_DCOC_RES_I_66___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_66__RX_DCOC_RES_Q_66___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_66__RX_DCOC_RES_Q_66___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_66___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_66___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_67 (0x005E410C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_67___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_67___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_67__RX_DCOC_RANGE_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_67__RX_DCOC_RES_I_67___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_67__RX_DCOC_RES_Q_67___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_67__RX_DCOC_RANGE_67___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_67__RX_DCOC_RANGE_67___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_67__RX_DCOC_RES_I_67___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_67__RX_DCOC_RES_I_67___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_67__RX_DCOC_RES_Q_67___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_67__RX_DCOC_RES_Q_67___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_67___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_67___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_68 (0x005E4110) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_68___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_68___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_68__RX_DCOC_RANGE_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_68__RX_DCOC_RES_I_68___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_68__RX_DCOC_RES_Q_68___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_68__RX_DCOC_RANGE_68___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_68__RX_DCOC_RANGE_68___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_68__RX_DCOC_RES_I_68___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_68__RX_DCOC_RES_I_68___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_68__RX_DCOC_RES_Q_68___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_68__RX_DCOC_RES_Q_68___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_68___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_68___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_69 (0x005E4114) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_69___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_69___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_69__RX_DCOC_RANGE_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_69__RX_DCOC_RES_I_69___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_69__RX_DCOC_RES_Q_69___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_69__RX_DCOC_RANGE_69___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_69__RX_DCOC_RANGE_69___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_69__RX_DCOC_RES_I_69___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_69__RX_DCOC_RES_I_69___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_69__RX_DCOC_RES_Q_69___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_69__RX_DCOC_RES_Q_69___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_69___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_69___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_70 (0x005E4118) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_70___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_70___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_70__RX_DCOC_RANGE_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_70__RX_DCOC_RES_I_70___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_70__RX_DCOC_RES_Q_70___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_70__RX_DCOC_RANGE_70___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_70__RX_DCOC_RANGE_70___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_70__RX_DCOC_RES_I_70___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_70__RX_DCOC_RES_I_70___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_70__RX_DCOC_RES_Q_70___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_70__RX_DCOC_RES_Q_70___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_70___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_70___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_71 (0x005E411C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_71___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_71___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_71__RX_DCOC_RANGE_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_71__RX_DCOC_RES_I_71___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_71__RX_DCOC_RES_Q_71___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_71__RX_DCOC_RANGE_71___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_71__RX_DCOC_RANGE_71___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_71__RX_DCOC_RES_I_71___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_71__RX_DCOC_RES_I_71___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_71__RX_DCOC_RES_Q_71___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_71__RX_DCOC_RES_Q_71___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_71___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_71___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_72 (0x005E4120) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_72___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_72___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_72__RX_DCOC_RANGE_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_72__RX_DCOC_RES_I_72___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_72__RX_DCOC_RES_Q_72___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_72__RX_DCOC_RANGE_72___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_72__RX_DCOC_RANGE_72___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_72__RX_DCOC_RES_I_72___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_72__RX_DCOC_RES_I_72___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_72__RX_DCOC_RES_Q_72___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_72__RX_DCOC_RES_Q_72___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_72___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_72___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_73 (0x005E4124) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_73___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_73___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_73__RX_DCOC_RANGE_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_73__RX_DCOC_RES_I_73___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_73__RX_DCOC_RES_Q_73___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_73__RX_DCOC_RANGE_73___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_73__RX_DCOC_RANGE_73___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_73__RX_DCOC_RES_I_73___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_73__RX_DCOC_RES_I_73___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_73__RX_DCOC_RES_Q_73___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_73__RX_DCOC_RES_Q_73___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_73___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_73___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_74 (0x005E4128) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_74___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_74___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_74__RX_DCOC_RANGE_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_74__RX_DCOC_RES_I_74___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_74__RX_DCOC_RES_Q_74___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_74__RX_DCOC_RANGE_74___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_74__RX_DCOC_RANGE_74___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_74__RX_DCOC_RES_I_74___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_74__RX_DCOC_RES_I_74___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_74__RX_DCOC_RES_Q_74___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_74__RX_DCOC_RES_Q_74___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_74___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_74___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_75 (0x005E412C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_75___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_75___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_75__RX_DCOC_RANGE_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_75__RX_DCOC_RES_I_75___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_75__RX_DCOC_RES_Q_75___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_75__RX_DCOC_RANGE_75___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_75__RX_DCOC_RANGE_75___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_75__RX_DCOC_RES_I_75___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_75__RX_DCOC_RES_I_75___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_75__RX_DCOC_RES_Q_75___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_75__RX_DCOC_RES_Q_75___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_75___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_75___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_76 (0x005E4130) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_76___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_76___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_76__RX_DCOC_RANGE_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_76__RX_DCOC_RES_I_76___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_76__RX_DCOC_RES_Q_76___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_76__RX_DCOC_RANGE_76___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_76__RX_DCOC_RANGE_76___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_76__RX_DCOC_RES_I_76___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_76__RX_DCOC_RES_I_76___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_76__RX_DCOC_RES_Q_76___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_76__RX_DCOC_RES_Q_76___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_76___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_76___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_77 (0x005E4134) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_77___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_77___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_77__RX_DCOC_RANGE_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_77__RX_DCOC_RES_I_77___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_77__RX_DCOC_RES_Q_77___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_77__RX_DCOC_RANGE_77___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_77__RX_DCOC_RANGE_77___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_77__RX_DCOC_RES_I_77___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_77__RX_DCOC_RES_I_77___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_77__RX_DCOC_RES_Q_77___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_77__RX_DCOC_RES_Q_77___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_77___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_77___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_78 (0x005E4138) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_78___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_78___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_78__RX_DCOC_RANGE_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_78__RX_DCOC_RES_I_78___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_78__RX_DCOC_RES_Q_78___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_78__RX_DCOC_RANGE_78___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_78__RX_DCOC_RANGE_78___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_78__RX_DCOC_RES_I_78___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_78__RX_DCOC_RES_I_78___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_78__RX_DCOC_RES_Q_78___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_78__RX_DCOC_RES_Q_78___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_78___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_78___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_79 (0x005E413C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_79___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_79___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_79__RX_DCOC_RANGE_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_79__RX_DCOC_RES_I_79___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_79__RX_DCOC_RES_Q_79___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_79__RX_DCOC_RANGE_79___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_79__RX_DCOC_RANGE_79___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_79__RX_DCOC_RES_I_79___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_79__RX_DCOC_RES_I_79___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_79__RX_DCOC_RES_Q_79___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_79__RX_DCOC_RES_Q_79___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_79___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_79___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_80 (0x005E4140) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_80___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_80___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_80__RX_DCOC_RANGE_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_80__RX_DCOC_RES_I_80___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_80__RX_DCOC_RES_Q_80___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_80__RX_DCOC_RANGE_80___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_80__RX_DCOC_RANGE_80___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_80__RX_DCOC_RES_I_80___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_80__RX_DCOC_RES_I_80___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_80__RX_DCOC_RES_Q_80___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_80__RX_DCOC_RES_Q_80___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_80___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_80___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_81 (0x005E4144) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_81___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_81___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_81__RX_DCOC_RANGE_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_81__RX_DCOC_RES_I_81___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_81__RX_DCOC_RES_Q_81___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_81__RX_DCOC_RANGE_81___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_81__RX_DCOC_RANGE_81___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_81__RX_DCOC_RES_I_81___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_81__RX_DCOC_RES_I_81___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_81__RX_DCOC_RES_Q_81___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_81__RX_DCOC_RES_Q_81___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_81___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_81___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_82 (0x005E4148) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_82___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_82___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_82__RX_DCOC_RANGE_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_82__RX_DCOC_RES_I_82___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_82__RX_DCOC_RES_Q_82___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_82__RX_DCOC_RANGE_82___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_82__RX_DCOC_RANGE_82___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_82__RX_DCOC_RES_I_82___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_82__RX_DCOC_RES_I_82___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_82__RX_DCOC_RES_Q_82___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_82__RX_DCOC_RES_Q_82___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_82___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_82___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_83 (0x005E414C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_83___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_83___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_83__RX_DCOC_RANGE_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_83__RX_DCOC_RES_I_83___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_83__RX_DCOC_RES_Q_83___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_83__RX_DCOC_RANGE_83___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_83__RX_DCOC_RANGE_83___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_83__RX_DCOC_RES_I_83___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_83__RX_DCOC_RES_I_83___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_83__RX_DCOC_RES_Q_83___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_83__RX_DCOC_RES_Q_83___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_83___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_83___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_84 (0x005E4150) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_84___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_84___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_84__RX_DCOC_RANGE_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_84__RX_DCOC_RES_I_84___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_84__RX_DCOC_RES_Q_84___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_84__RX_DCOC_RANGE_84___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_84__RX_DCOC_RANGE_84___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_84__RX_DCOC_RES_I_84___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_84__RX_DCOC_RES_I_84___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_84__RX_DCOC_RES_Q_84___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_84__RX_DCOC_RES_Q_84___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_84___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_84___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_85 (0x005E4154) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_85___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_85___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_85__RX_DCOC_RANGE_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_85__RX_DCOC_RES_I_85___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_85__RX_DCOC_RES_Q_85___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_85__RX_DCOC_RANGE_85___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_85__RX_DCOC_RANGE_85___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_85__RX_DCOC_RES_I_85___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_85__RX_DCOC_RES_I_85___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_85__RX_DCOC_RES_Q_85___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_85__RX_DCOC_RES_Q_85___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_85___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_85___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_86 (0x005E4158) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_86___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_86___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_86__RX_DCOC_RANGE_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_86__RX_DCOC_RES_I_86___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_86__RX_DCOC_RES_Q_86___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_86__RX_DCOC_RANGE_86___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_86__RX_DCOC_RANGE_86___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_86__RX_DCOC_RES_I_86___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_86__RX_DCOC_RES_I_86___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_86__RX_DCOC_RES_Q_86___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_86__RX_DCOC_RES_Q_86___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_86___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_86___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_87 (0x005E415C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_87___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_87___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_87__RX_DCOC_RANGE_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_87__RX_DCOC_RES_I_87___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_87__RX_DCOC_RES_Q_87___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_87__RX_DCOC_RANGE_87___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_87__RX_DCOC_RANGE_87___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_87__RX_DCOC_RES_I_87___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_87__RX_DCOC_RES_I_87___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_87__RX_DCOC_RES_Q_87___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_87__RX_DCOC_RES_Q_87___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_87___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_87___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_88 (0x005E4160) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_88___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_88___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_88__RX_DCOC_RANGE_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_88__RX_DCOC_RES_I_88___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_88__RX_DCOC_RES_Q_88___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_88__RX_DCOC_RANGE_88___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_88__RX_DCOC_RANGE_88___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_88__RX_DCOC_RES_I_88___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_88__RX_DCOC_RES_I_88___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_88__RX_DCOC_RES_Q_88___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_88__RX_DCOC_RES_Q_88___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_88___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_88___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_89 (0x005E4164) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_89___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_89___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_89__RX_DCOC_RANGE_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_89__RX_DCOC_RES_I_89___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_89__RX_DCOC_RES_Q_89___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_89__RX_DCOC_RANGE_89___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_89__RX_DCOC_RANGE_89___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_89__RX_DCOC_RES_I_89___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_89__RX_DCOC_RES_I_89___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_89__RX_DCOC_RES_Q_89___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_89__RX_DCOC_RES_Q_89___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_89___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_89___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_90 (0x005E4168) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_90___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_90___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_90__RX_DCOC_RANGE_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_90__RX_DCOC_RES_I_90___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_90__RX_DCOC_RES_Q_90___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_90__RX_DCOC_RANGE_90___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_90__RX_DCOC_RANGE_90___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_90__RX_DCOC_RES_I_90___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_90__RX_DCOC_RES_I_90___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_90__RX_DCOC_RES_Q_90___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_90__RX_DCOC_RES_Q_90___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_90___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_90___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_91 (0x005E416C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_91___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_91___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_91__RX_DCOC_RANGE_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_91__RX_DCOC_RES_I_91___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_91__RX_DCOC_RES_Q_91___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_91__RX_DCOC_RANGE_91___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_91__RX_DCOC_RANGE_91___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_91__RX_DCOC_RES_I_91___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_91__RX_DCOC_RES_I_91___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_91__RX_DCOC_RES_Q_91___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_91__RX_DCOC_RES_Q_91___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_91___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_91___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_92 (0x005E4170) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_92___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_92___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_92__RX_DCOC_RANGE_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_92__RX_DCOC_RES_I_92___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_92__RX_DCOC_RES_Q_92___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_92__RX_DCOC_RANGE_92___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_92__RX_DCOC_RANGE_92___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_92__RX_DCOC_RES_I_92___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_92__RX_DCOC_RES_I_92___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_92__RX_DCOC_RES_Q_92___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_92__RX_DCOC_RES_Q_92___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_92___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_92___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_93 (0x005E4174) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_93___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_93___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_93__RX_DCOC_RANGE_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_93__RX_DCOC_RES_I_93___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_93__RX_DCOC_RES_Q_93___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_93__RX_DCOC_RANGE_93___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_93__RX_DCOC_RANGE_93___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_93__RX_DCOC_RES_I_93___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_93__RX_DCOC_RES_I_93___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_93__RX_DCOC_RES_Q_93___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_93__RX_DCOC_RES_Q_93___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_93___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_93___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_94 (0x005E4178) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_94___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_94___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_94__RX_DCOC_RANGE_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_94__RX_DCOC_RES_I_94___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_94__RX_DCOC_RES_Q_94___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_94__RX_DCOC_RANGE_94___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_94__RX_DCOC_RANGE_94___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_94__RX_DCOC_RES_I_94___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_94__RX_DCOC_RES_I_94___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_94__RX_DCOC_RES_Q_94___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_94__RX_DCOC_RES_Q_94___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_94___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_94___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_95 (0x005E417C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_95___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_95___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_95__RX_DCOC_RANGE_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_95__RX_DCOC_RES_I_95___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_95__RX_DCOC_RES_Q_95___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_95__RX_DCOC_RANGE_95___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_95__RX_DCOC_RANGE_95___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_95__RX_DCOC_RES_I_95___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_95__RX_DCOC_RES_I_95___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_95__RX_DCOC_RES_Q_95___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_95__RX_DCOC_RES_Q_95___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_95___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_95___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_96 (0x005E4180) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_96___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_96___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_96__RX_DCOC_RANGE_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_96__RX_DCOC_RES_I_96___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_96__RX_DCOC_RES_Q_96___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_96__RX_DCOC_RANGE_96___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_96__RX_DCOC_RANGE_96___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_96__RX_DCOC_RES_I_96___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_96__RX_DCOC_RES_I_96___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_96__RX_DCOC_RES_Q_96___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_96__RX_DCOC_RES_Q_96___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_96___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_96___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_97 (0x005E4184) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_97___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_97___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_97__RX_DCOC_RANGE_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_97__RX_DCOC_RES_I_97___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_97__RX_DCOC_RES_Q_97___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_97__RX_DCOC_RANGE_97___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_97__RX_DCOC_RANGE_97___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_97__RX_DCOC_RES_I_97___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_97__RX_DCOC_RES_I_97___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_97__RX_DCOC_RES_Q_97___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_97__RX_DCOC_RES_Q_97___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_97___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_97___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_98 (0x005E4188) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_98___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_98___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_98__RX_DCOC_RANGE_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_98__RX_DCOC_RES_I_98___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_98__RX_DCOC_RES_Q_98___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_98__RX_DCOC_RANGE_98___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_98__RX_DCOC_RANGE_98___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_98__RX_DCOC_RES_I_98___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_98__RX_DCOC_RES_I_98___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_98__RX_DCOC_RES_Q_98___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_98__RX_DCOC_RES_Q_98___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_98___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_98___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_99 (0x005E418C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_99___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_99___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_99__RX_DCOC_RANGE_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_99__RX_DCOC_RES_I_99___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_99__RX_DCOC_RES_Q_99___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_99__RX_DCOC_RANGE_99___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_99__RX_DCOC_RANGE_99___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_99__RX_DCOC_RES_I_99___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_99__RX_DCOC_RES_I_99___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_99__RX_DCOC_RES_Q_99___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_99__RX_DCOC_RES_Q_99___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_99___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_99___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_100 (0x005E4190) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_100___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_100___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_100__RX_DCOC_RANGE_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_100__RX_DCOC_RES_I_100___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_100__RX_DCOC_RES_Q_100___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_100__RX_DCOC_RANGE_100___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_100__RX_DCOC_RANGE_100___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_100__RX_DCOC_RES_I_100___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_100__RX_DCOC_RES_I_100___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_100__RX_DCOC_RES_Q_100___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_100__RX_DCOC_RES_Q_100___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_100___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_100___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_101 (0x005E4194) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_101___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_101___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_101__RX_DCOC_RANGE_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_101__RX_DCOC_RES_I_101___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_101__RX_DCOC_RES_Q_101___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_101__RX_DCOC_RANGE_101___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_101__RX_DCOC_RANGE_101___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_101__RX_DCOC_RES_I_101___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_101__RX_DCOC_RES_I_101___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_101__RX_DCOC_RES_Q_101___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_101__RX_DCOC_RES_Q_101___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_101___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_101___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_102 (0x005E4198) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_102___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_102___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_102__RX_DCOC_RANGE_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_102__RX_DCOC_RES_I_102___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_102__RX_DCOC_RES_Q_102___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_102__RX_DCOC_RANGE_102___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_102__RX_DCOC_RANGE_102___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_102__RX_DCOC_RES_I_102___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_102__RX_DCOC_RES_I_102___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_102__RX_DCOC_RES_Q_102___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_102__RX_DCOC_RES_Q_102___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_102___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_102___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_103 (0x005E419C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_103___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_103___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_103__RX_DCOC_RANGE_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_103__RX_DCOC_RES_I_103___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_103__RX_DCOC_RES_Q_103___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_103__RX_DCOC_RANGE_103___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_103__RX_DCOC_RANGE_103___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_103__RX_DCOC_RES_I_103___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_103__RX_DCOC_RES_I_103___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_103__RX_DCOC_RES_Q_103___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_103__RX_DCOC_RES_Q_103___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_103___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_103___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_104 (0x005E41A0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_104___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_104___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_104__RX_DCOC_RANGE_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_104__RX_DCOC_RES_I_104___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_104__RX_DCOC_RES_Q_104___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_104__RX_DCOC_RANGE_104___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_104__RX_DCOC_RANGE_104___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_104__RX_DCOC_RES_I_104___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_104__RX_DCOC_RES_I_104___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_104__RX_DCOC_RES_Q_104___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_104__RX_DCOC_RES_Q_104___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_104___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_104___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_105 (0x005E41A4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_105___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_105___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_105__RX_DCOC_RANGE_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_105__RX_DCOC_RES_I_105___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_105__RX_DCOC_RES_Q_105___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_105__RX_DCOC_RANGE_105___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_105__RX_DCOC_RANGE_105___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_105__RX_DCOC_RES_I_105___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_105__RX_DCOC_RES_I_105___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_105__RX_DCOC_RES_Q_105___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_105__RX_DCOC_RES_Q_105___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_105___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_105___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_106 (0x005E41A8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_106___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_106___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_106__RX_DCOC_RANGE_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_106__RX_DCOC_RES_I_106___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_106__RX_DCOC_RES_Q_106___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_106__RX_DCOC_RANGE_106___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_106__RX_DCOC_RANGE_106___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_106__RX_DCOC_RES_I_106___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_106__RX_DCOC_RES_I_106___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_106__RX_DCOC_RES_Q_106___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_106__RX_DCOC_RES_Q_106___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_106___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_106___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_107 (0x005E41AC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_107___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_107___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_107__RX_DCOC_RANGE_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_107__RX_DCOC_RES_I_107___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_107__RX_DCOC_RES_Q_107___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_107__RX_DCOC_RANGE_107___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_107__RX_DCOC_RANGE_107___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_107__RX_DCOC_RES_I_107___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_107__RX_DCOC_RES_I_107___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_107__RX_DCOC_RES_Q_107___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_107__RX_DCOC_RES_Q_107___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_107___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_107___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_108 (0x005E41B0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_108___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_108___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_108__RX_DCOC_RANGE_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_108__RX_DCOC_RES_I_108___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_108__RX_DCOC_RES_Q_108___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_108__RX_DCOC_RANGE_108___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_108__RX_DCOC_RANGE_108___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_108__RX_DCOC_RES_I_108___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_108__RX_DCOC_RES_I_108___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_108__RX_DCOC_RES_Q_108___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_108__RX_DCOC_RES_Q_108___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_108___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_108___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_109 (0x005E41B4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_109___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_109___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_109__RX_DCOC_RANGE_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_109__RX_DCOC_RES_I_109___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_109__RX_DCOC_RES_Q_109___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_109__RX_DCOC_RANGE_109___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_109__RX_DCOC_RANGE_109___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_109__RX_DCOC_RES_I_109___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_109__RX_DCOC_RES_I_109___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_109__RX_DCOC_RES_Q_109___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_109__RX_DCOC_RES_Q_109___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_109___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_109___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_110 (0x005E41B8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_110___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_110___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_110__RX_DCOC_RANGE_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_110__RX_DCOC_RES_I_110___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_110__RX_DCOC_RES_Q_110___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_110__RX_DCOC_RANGE_110___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_110__RX_DCOC_RANGE_110___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_110__RX_DCOC_RES_I_110___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_110__RX_DCOC_RES_I_110___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_110__RX_DCOC_RES_Q_110___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_110__RX_DCOC_RES_Q_110___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_110___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_110___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_111 (0x005E41BC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_111___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_111___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_111__RX_DCOC_RANGE_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_111__RX_DCOC_RES_I_111___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_111__RX_DCOC_RES_Q_111___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_111__RX_DCOC_RANGE_111___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_111__RX_DCOC_RANGE_111___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_111__RX_DCOC_RES_I_111___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_111__RX_DCOC_RES_I_111___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_111__RX_DCOC_RES_Q_111___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_111__RX_DCOC_RES_Q_111___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_111___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_111___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_112 (0x005E41C0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_112___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_112___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_112__RX_DCOC_RANGE_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_112__RX_DCOC_RES_I_112___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_112__RX_DCOC_RES_Q_112___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_112__RX_DCOC_RANGE_112___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_112__RX_DCOC_RANGE_112___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_112__RX_DCOC_RES_I_112___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_112__RX_DCOC_RES_I_112___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_112__RX_DCOC_RES_Q_112___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_112__RX_DCOC_RES_Q_112___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_112___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_112___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_113 (0x005E41C4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_113___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_113___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_113__RX_DCOC_RANGE_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_113__RX_DCOC_RES_I_113___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_113__RX_DCOC_RES_Q_113___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_113__RX_DCOC_RANGE_113___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_113__RX_DCOC_RANGE_113___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_113__RX_DCOC_RES_I_113___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_113__RX_DCOC_RES_I_113___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_113__RX_DCOC_RES_Q_113___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_113__RX_DCOC_RES_Q_113___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_113___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_113___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_114 (0x005E41C8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_114___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_114___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_114__RX_DCOC_RANGE_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_114__RX_DCOC_RES_I_114___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_114__RX_DCOC_RES_Q_114___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_114__RX_DCOC_RANGE_114___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_114__RX_DCOC_RANGE_114___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_114__RX_DCOC_RES_I_114___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_114__RX_DCOC_RES_I_114___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_114__RX_DCOC_RES_Q_114___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_114__RX_DCOC_RES_Q_114___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_114___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_114___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_115 (0x005E41CC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_115___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_115___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_115__RX_DCOC_RANGE_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_115__RX_DCOC_RES_I_115___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_115__RX_DCOC_RES_Q_115___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_115__RX_DCOC_RANGE_115___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_115__RX_DCOC_RANGE_115___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_115__RX_DCOC_RES_I_115___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_115__RX_DCOC_RES_I_115___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_115__RX_DCOC_RES_Q_115___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_115__RX_DCOC_RES_Q_115___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_115___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_115___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_116 (0x005E41D0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_116___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_116___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_116__RX_DCOC_RANGE_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_116__RX_DCOC_RES_I_116___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_116__RX_DCOC_RES_Q_116___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_116__RX_DCOC_RANGE_116___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_116__RX_DCOC_RANGE_116___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_116__RX_DCOC_RES_I_116___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_116__RX_DCOC_RES_I_116___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_116__RX_DCOC_RES_Q_116___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_116__RX_DCOC_RES_Q_116___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_116___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_116___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_117 (0x005E41D4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_117___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_117___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_117__RX_DCOC_RANGE_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_117__RX_DCOC_RES_I_117___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_117__RX_DCOC_RES_Q_117___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_117__RX_DCOC_RANGE_117___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_117__RX_DCOC_RANGE_117___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_117__RX_DCOC_RES_I_117___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_117__RX_DCOC_RES_I_117___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_117__RX_DCOC_RES_Q_117___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_117__RX_DCOC_RES_Q_117___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_117___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_117___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_118 (0x005E41D8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_118___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_118___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_118__RX_DCOC_RANGE_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_118__RX_DCOC_RES_I_118___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_118__RX_DCOC_RES_Q_118___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_118__RX_DCOC_RANGE_118___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_118__RX_DCOC_RANGE_118___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_118__RX_DCOC_RES_I_118___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_118__RX_DCOC_RES_I_118___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_118__RX_DCOC_RES_Q_118___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_118__RX_DCOC_RES_Q_118___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_118___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_118___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_119 (0x005E41DC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_119___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_119___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_119__RX_DCOC_RANGE_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_119__RX_DCOC_RES_I_119___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_119__RX_DCOC_RES_Q_119___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_119__RX_DCOC_RANGE_119___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_119__RX_DCOC_RANGE_119___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_119__RX_DCOC_RES_I_119___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_119__RX_DCOC_RES_I_119___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_119__RX_DCOC_RES_Q_119___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_119__RX_DCOC_RES_Q_119___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_119___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_119___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_120 (0x005E41E0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_120___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_120___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_120__RX_DCOC_RANGE_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_120__RX_DCOC_RES_I_120___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_120__RX_DCOC_RES_Q_120___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_120__RX_DCOC_RANGE_120___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_120__RX_DCOC_RANGE_120___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_120__RX_DCOC_RES_I_120___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_120__RX_DCOC_RES_I_120___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_120__RX_DCOC_RES_Q_120___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_120__RX_DCOC_RES_Q_120___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_120___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_120___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_121 (0x005E41E4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_121___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_121___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_121__RX_DCOC_RANGE_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_121__RX_DCOC_RES_I_121___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_121__RX_DCOC_RES_Q_121___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_121__RX_DCOC_RANGE_121___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_121__RX_DCOC_RANGE_121___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_121__RX_DCOC_RES_I_121___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_121__RX_DCOC_RES_I_121___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_121__RX_DCOC_RES_Q_121___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_121__RX_DCOC_RES_Q_121___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_121___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_121___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_122 (0x005E41E8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_122___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_122___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_122__RX_DCOC_RANGE_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_122__RX_DCOC_RES_I_122___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_122__RX_DCOC_RES_Q_122___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_122__RX_DCOC_RANGE_122___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_122__RX_DCOC_RANGE_122___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_122__RX_DCOC_RES_I_122___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_122__RX_DCOC_RES_I_122___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_122__RX_DCOC_RES_Q_122___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_122__RX_DCOC_RES_Q_122___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_122___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_122___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_123 (0x005E41EC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_123___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_123___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_123__RX_DCOC_RANGE_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_123__RX_DCOC_RES_I_123___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_123__RX_DCOC_RES_Q_123___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_123__RX_DCOC_RANGE_123___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_123__RX_DCOC_RANGE_123___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_123__RX_DCOC_RES_I_123___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_123__RX_DCOC_RES_I_123___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_123__RX_DCOC_RES_Q_123___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_123__RX_DCOC_RES_Q_123___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_123___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_123___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_124 (0x005E41F0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_124___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_124___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_124__RX_DCOC_RANGE_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_124__RX_DCOC_RES_I_124___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_124__RX_DCOC_RES_Q_124___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_124__RX_DCOC_RANGE_124___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_124__RX_DCOC_RANGE_124___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_124__RX_DCOC_RES_I_124___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_124__RX_DCOC_RES_I_124___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_124__RX_DCOC_RES_Q_124___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_124__RX_DCOC_RES_Q_124___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_124___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_124___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_125 (0x005E41F4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_125___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_125___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_125__RX_DCOC_RANGE_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_125__RX_DCOC_RES_I_125___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_125__RX_DCOC_RES_Q_125___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_125__RX_DCOC_RANGE_125___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_125__RX_DCOC_RANGE_125___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_125__RX_DCOC_RES_I_125___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_125__RX_DCOC_RES_I_125___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_125__RX_DCOC_RES_Q_125___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_125__RX_DCOC_RES_Q_125___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_125___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_125___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_126 (0x005E41F8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_126___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_126___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_126__RX_DCOC_RANGE_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_126__RX_DCOC_RES_I_126___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_126__RX_DCOC_RES_Q_126___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_126__RX_DCOC_RANGE_126___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_126__RX_DCOC_RANGE_126___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_126__RX_DCOC_RES_I_126___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_126__RX_DCOC_RES_I_126___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_126__RX_DCOC_RES_Q_126___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_126__RX_DCOC_RES_Q_126___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_126___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_126___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_127 (0x005E41FC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_127___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_127___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_127__RX_DCOC_RANGE_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_127__RX_DCOC_RES_I_127___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_127__RX_DCOC_RES_Q_127___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_127__RX_DCOC_RANGE_127___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_127__RX_DCOC_RANGE_127___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_127__RX_DCOC_RES_I_127___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_127__RX_DCOC_RES_I_127___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_127__RX_DCOC_RES_Q_127___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_127__RX_DCOC_RES_Q_127___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_127___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_127___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_128 (0x005E4200) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_128___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_128___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_128__RX_DCOC_RANGE_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_128__RX_DCOC_RES_I_128___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_128__RX_DCOC_RES_Q_128___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_128__RX_DCOC_RANGE_128___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_128__RX_DCOC_RANGE_128___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_128__RX_DCOC_RES_I_128___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_128__RX_DCOC_RES_I_128___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_128__RX_DCOC_RES_Q_128___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_128__RX_DCOC_RES_Q_128___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_128___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_128___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_129 (0x005E4204) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_129___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_129___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_129__RX_DCOC_RANGE_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_129__RX_DCOC_RES_I_129___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_129__RX_DCOC_RES_Q_129___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_129__RX_DCOC_RANGE_129___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_129__RX_DCOC_RANGE_129___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_129__RX_DCOC_RES_I_129___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_129__RX_DCOC_RES_I_129___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_129__RX_DCOC_RES_Q_129___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_129__RX_DCOC_RES_Q_129___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_129___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_129___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_130 (0x005E4208) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_130___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_130___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_130__RX_DCOC_RANGE_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_130__RX_DCOC_RES_I_130___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_130__RX_DCOC_RES_Q_130___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_130__RX_DCOC_RANGE_130___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_130__RX_DCOC_RANGE_130___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_130__RX_DCOC_RES_I_130___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_130__RX_DCOC_RES_I_130___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_130__RX_DCOC_RES_Q_130___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_130__RX_DCOC_RES_Q_130___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_130___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_130___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_131 (0x005E420C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_131___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_131___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_131__RX_DCOC_RANGE_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_131__RX_DCOC_RES_I_131___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_131__RX_DCOC_RES_Q_131___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_131__RX_DCOC_RANGE_131___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_131__RX_DCOC_RANGE_131___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_131__RX_DCOC_RES_I_131___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_131__RX_DCOC_RES_I_131___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_131__RX_DCOC_RES_Q_131___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_131__RX_DCOC_RES_Q_131___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_131___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_131___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_132 (0x005E4210) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_132___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_132___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_132__RX_DCOC_RANGE_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_132__RX_DCOC_RES_I_132___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_132__RX_DCOC_RES_Q_132___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_132__RX_DCOC_RANGE_132___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_132__RX_DCOC_RANGE_132___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_132__RX_DCOC_RES_I_132___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_132__RX_DCOC_RES_I_132___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_132__RX_DCOC_RES_Q_132___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_132__RX_DCOC_RES_Q_132___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_132___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_132___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_133 (0x005E4214) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_133___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_133___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_133__RX_DCOC_RANGE_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_133__RX_DCOC_RES_I_133___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_133__RX_DCOC_RES_Q_133___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_133__RX_DCOC_RANGE_133___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_133__RX_DCOC_RANGE_133___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_133__RX_DCOC_RES_I_133___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_133__RX_DCOC_RES_I_133___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_133__RX_DCOC_RES_Q_133___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_133__RX_DCOC_RES_Q_133___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_133___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_133___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_134 (0x005E4218) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_134___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_134___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_134__RX_DCOC_RANGE_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_134__RX_DCOC_RES_I_134___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_134__RX_DCOC_RES_Q_134___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_134__RX_DCOC_RANGE_134___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_134__RX_DCOC_RANGE_134___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_134__RX_DCOC_RES_I_134___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_134__RX_DCOC_RES_I_134___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_134__RX_DCOC_RES_Q_134___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_134__RX_DCOC_RES_Q_134___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_134___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_134___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_135 (0x005E421C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_135___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_135___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_135__RX_DCOC_RANGE_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_135__RX_DCOC_RES_I_135___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_135__RX_DCOC_RES_Q_135___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_135__RX_DCOC_RANGE_135___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_135__RX_DCOC_RANGE_135___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_135__RX_DCOC_RES_I_135___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_135__RX_DCOC_RES_I_135___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_135__RX_DCOC_RES_Q_135___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_135__RX_DCOC_RES_Q_135___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_135___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_135___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_136 (0x005E4220) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_136___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_136___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_136__RX_DCOC_RANGE_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_136__RX_DCOC_RES_I_136___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_136__RX_DCOC_RES_Q_136___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_136__RX_DCOC_RANGE_136___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_136__RX_DCOC_RANGE_136___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_136__RX_DCOC_RES_I_136___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_136__RX_DCOC_RES_I_136___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_136__RX_DCOC_RES_Q_136___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_136__RX_DCOC_RES_Q_136___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_136___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_136___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_137 (0x005E4224) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_137___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_137___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_137__RX_DCOC_RANGE_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_137__RX_DCOC_RES_I_137___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_137__RX_DCOC_RES_Q_137___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_137__RX_DCOC_RANGE_137___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_137__RX_DCOC_RANGE_137___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_137__RX_DCOC_RES_I_137___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_137__RX_DCOC_RES_I_137___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_137__RX_DCOC_RES_Q_137___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_137__RX_DCOC_RES_Q_137___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_137___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_137___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_138 (0x005E4228) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_138___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_138___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_138__RX_DCOC_RANGE_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_138__RX_DCOC_RES_I_138___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_138__RX_DCOC_RES_Q_138___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_138__RX_DCOC_RANGE_138___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_138__RX_DCOC_RANGE_138___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_138__RX_DCOC_RES_I_138___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_138__RX_DCOC_RES_I_138___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_138__RX_DCOC_RES_Q_138___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_138__RX_DCOC_RES_Q_138___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_138___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_138___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_139 (0x005E422C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_139___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_139___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_139__RX_DCOC_RANGE_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_139__RX_DCOC_RES_I_139___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_139__RX_DCOC_RES_Q_139___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_139__RX_DCOC_RANGE_139___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_139__RX_DCOC_RANGE_139___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_139__RX_DCOC_RES_I_139___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_139__RX_DCOC_RES_I_139___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_139__RX_DCOC_RES_Q_139___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_139__RX_DCOC_RES_Q_139___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_139___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_139___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_140 (0x005E4230) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_140___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_140___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_140__RX_DCOC_RANGE_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_140__RX_DCOC_RES_I_140___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_140__RX_DCOC_RES_Q_140___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_140__RX_DCOC_RANGE_140___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_140__RX_DCOC_RANGE_140___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_140__RX_DCOC_RES_I_140___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_140__RX_DCOC_RES_I_140___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_140__RX_DCOC_RES_Q_140___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_140__RX_DCOC_RES_Q_140___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_140___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_140___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_141 (0x005E4234) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_141___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_141___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_141__RX_DCOC_RANGE_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_141__RX_DCOC_RES_I_141___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_141__RX_DCOC_RES_Q_141___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_141__RX_DCOC_RANGE_141___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_141__RX_DCOC_RANGE_141___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_141__RX_DCOC_RES_I_141___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_141__RX_DCOC_RES_I_141___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_141__RX_DCOC_RES_Q_141___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_141__RX_DCOC_RES_Q_141___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_141___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_141___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_142 (0x005E4238) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_142___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_142___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_142__RX_DCOC_RANGE_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_142__RX_DCOC_RES_I_142___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_142__RX_DCOC_RES_Q_142___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_142__RX_DCOC_RANGE_142___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_142__RX_DCOC_RANGE_142___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_142__RX_DCOC_RES_I_142___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_142__RX_DCOC_RES_I_142___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_142__RX_DCOC_RES_Q_142___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_142__RX_DCOC_RES_Q_142___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_142___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_142___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_143 (0x005E423C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_143___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_143___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_143__RX_DCOC_RANGE_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_143__RX_DCOC_RES_I_143___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_143__RX_DCOC_RES_Q_143___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_143__RX_DCOC_RANGE_143___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_143__RX_DCOC_RANGE_143___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_143__RX_DCOC_RES_I_143___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_143__RX_DCOC_RES_I_143___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_143__RX_DCOC_RES_Q_143___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_143__RX_DCOC_RES_Q_143___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_143___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_143___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_144 (0x005E4240) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_144___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_144___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_144__RX_DCOC_RANGE_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_144__RX_DCOC_RES_I_144___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_144__RX_DCOC_RES_Q_144___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_144__RX_DCOC_RANGE_144___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_144__RX_DCOC_RANGE_144___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_144__RX_DCOC_RES_I_144___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_144__RX_DCOC_RES_I_144___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_144__RX_DCOC_RES_Q_144___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_144__RX_DCOC_RES_Q_144___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_144___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_144___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_145 (0x005E4244) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_145___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_145___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_145__RX_DCOC_RANGE_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_145__RX_DCOC_RES_I_145___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_145__RX_DCOC_RES_Q_145___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_145__RX_DCOC_RANGE_145___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_145__RX_DCOC_RANGE_145___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_145__RX_DCOC_RES_I_145___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_145__RX_DCOC_RES_I_145___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_145__RX_DCOC_RES_Q_145___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_145__RX_DCOC_RES_Q_145___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_145___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_145___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_146 (0x005E4248) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_146___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_146___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_146__RX_DCOC_RANGE_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_146__RX_DCOC_RES_I_146___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_146__RX_DCOC_RES_Q_146___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_146__RX_DCOC_RANGE_146___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_146__RX_DCOC_RANGE_146___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_146__RX_DCOC_RES_I_146___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_146__RX_DCOC_RES_I_146___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_146__RX_DCOC_RES_Q_146___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_146__RX_DCOC_RES_Q_146___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_146___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_146___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_147 (0x005E424C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_147___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_147___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_147__RX_DCOC_RANGE_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_147__RX_DCOC_RES_I_147___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_147__RX_DCOC_RES_Q_147___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_147__RX_DCOC_RANGE_147___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_147__RX_DCOC_RANGE_147___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_147__RX_DCOC_RES_I_147___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_147__RX_DCOC_RES_I_147___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_147__RX_DCOC_RES_Q_147___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_147__RX_DCOC_RES_Q_147___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_147___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_147___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_148 (0x005E4250) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_148___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_148___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_148__RX_DCOC_RANGE_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_148__RX_DCOC_RES_I_148___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_148__RX_DCOC_RES_Q_148___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_148__RX_DCOC_RANGE_148___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_148__RX_DCOC_RANGE_148___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_148__RX_DCOC_RES_I_148___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_148__RX_DCOC_RES_I_148___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_148__RX_DCOC_RES_Q_148___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_148__RX_DCOC_RES_Q_148___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_148___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_148___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_149 (0x005E4254) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_149___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_149___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_149__RX_DCOC_RANGE_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_149__RX_DCOC_RES_I_149___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_149__RX_DCOC_RES_Q_149___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_149__RX_DCOC_RANGE_149___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_149__RX_DCOC_RANGE_149___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_149__RX_DCOC_RES_I_149___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_149__RX_DCOC_RES_I_149___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_149__RX_DCOC_RES_Q_149___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_149__RX_DCOC_RES_Q_149___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_149___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_149___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_150 (0x005E4258) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_150___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_150___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_150__RX_DCOC_RANGE_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_150__RX_DCOC_RES_I_150___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_150__RX_DCOC_RES_Q_150___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_150__RX_DCOC_RANGE_150___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_150__RX_DCOC_RANGE_150___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_150__RX_DCOC_RES_I_150___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_150__RX_DCOC_RES_I_150___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_150__RX_DCOC_RES_Q_150___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_150__RX_DCOC_RES_Q_150___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_150___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_150___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_151 (0x005E425C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_151___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_151___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_151__RX_DCOC_RANGE_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_151__RX_DCOC_RES_I_151___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_151__RX_DCOC_RES_Q_151___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_151__RX_DCOC_RANGE_151___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_151__RX_DCOC_RANGE_151___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_151__RX_DCOC_RES_I_151___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_151__RX_DCOC_RES_I_151___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_151__RX_DCOC_RES_Q_151___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_151__RX_DCOC_RES_Q_151___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_151___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_151___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_152 (0x005E4260) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_152___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_152___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_152__RX_DCOC_RANGE_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_152__RX_DCOC_RES_I_152___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_152__RX_DCOC_RES_Q_152___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_152__RX_DCOC_RANGE_152___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_152__RX_DCOC_RANGE_152___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_152__RX_DCOC_RES_I_152___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_152__RX_DCOC_RES_I_152___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_152__RX_DCOC_RES_Q_152___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_152__RX_DCOC_RES_Q_152___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_152___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_152___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_153 (0x005E4264) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_153___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_153___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_153__RX_DCOC_RANGE_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_153__RX_DCOC_RES_I_153___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_153__RX_DCOC_RES_Q_153___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_153__RX_DCOC_RANGE_153___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_153__RX_DCOC_RANGE_153___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_153__RX_DCOC_RES_I_153___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_153__RX_DCOC_RES_I_153___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_153__RX_DCOC_RES_Q_153___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_153__RX_DCOC_RES_Q_153___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_153___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_153___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_154 (0x005E4268) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_154___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_154___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_154__RX_DCOC_RANGE_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_154__RX_DCOC_RES_I_154___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_154__RX_DCOC_RES_Q_154___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_154__RX_DCOC_RANGE_154___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_154__RX_DCOC_RANGE_154___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_154__RX_DCOC_RES_I_154___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_154__RX_DCOC_RES_I_154___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_154__RX_DCOC_RES_Q_154___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_154__RX_DCOC_RES_Q_154___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_154___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_154___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_155 (0x005E426C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_155___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_155___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_155__RX_DCOC_RANGE_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_155__RX_DCOC_RES_I_155___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_155__RX_DCOC_RES_Q_155___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_155__RX_DCOC_RANGE_155___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_155__RX_DCOC_RANGE_155___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_155__RX_DCOC_RES_I_155___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_155__RX_DCOC_RES_I_155___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_155__RX_DCOC_RES_Q_155___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_155__RX_DCOC_RES_Q_155___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_155___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_155___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_156 (0x005E4270) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_156___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_156___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_156__RX_DCOC_RANGE_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_156__RX_DCOC_RES_I_156___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_156__RX_DCOC_RES_Q_156___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_156__RX_DCOC_RANGE_156___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_156__RX_DCOC_RANGE_156___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_156__RX_DCOC_RES_I_156___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_156__RX_DCOC_RES_I_156___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_156__RX_DCOC_RES_Q_156___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_156__RX_DCOC_RES_Q_156___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_156___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_156___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_157 (0x005E4274) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_157___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_157___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_157__RX_DCOC_RANGE_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_157__RX_DCOC_RES_I_157___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_157__RX_DCOC_RES_Q_157___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_157__RX_DCOC_RANGE_157___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_157__RX_DCOC_RANGE_157___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_157__RX_DCOC_RES_I_157___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_157__RX_DCOC_RES_I_157___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_157__RX_DCOC_RES_Q_157___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_157__RX_DCOC_RES_Q_157___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_157___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_157___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_158 (0x005E4278) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_158___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_158___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_158__RX_DCOC_RANGE_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_158__RX_DCOC_RES_I_158___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_158__RX_DCOC_RES_Q_158___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_158__RX_DCOC_RANGE_158___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_158__RX_DCOC_RANGE_158___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_158__RX_DCOC_RES_I_158___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_158__RX_DCOC_RES_I_158___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_158__RX_DCOC_RES_Q_158___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_158__RX_DCOC_RES_Q_158___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_158___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_158___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_159 (0x005E427C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_159___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_159___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_159__RX_DCOC_RANGE_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_159__RX_DCOC_RES_I_159___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_159__RX_DCOC_RES_Q_159___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_159__RX_DCOC_RANGE_159___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_159__RX_DCOC_RANGE_159___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_159__RX_DCOC_RES_I_159___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_159__RX_DCOC_RES_I_159___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_159__RX_DCOC_RES_Q_159___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_159__RX_DCOC_RES_Q_159___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_159___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_159___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_160 (0x005E4280) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_160___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_160___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_160__RX_DCOC_RANGE_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_160__RX_DCOC_RES_I_160___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_160__RX_DCOC_RES_Q_160___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_160__RX_DCOC_RANGE_160___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_160__RX_DCOC_RANGE_160___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_160__RX_DCOC_RES_I_160___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_160__RX_DCOC_RES_I_160___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_160__RX_DCOC_RES_Q_160___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_160__RX_DCOC_RES_Q_160___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_160___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_160___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_161 (0x005E4284) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_161___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_161___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_161__RX_DCOC_RANGE_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_161__RX_DCOC_RES_I_161___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_161__RX_DCOC_RES_Q_161___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_161__RX_DCOC_RANGE_161___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_161__RX_DCOC_RANGE_161___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_161__RX_DCOC_RES_I_161___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_161__RX_DCOC_RES_I_161___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_161__RX_DCOC_RES_Q_161___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_161__RX_DCOC_RES_Q_161___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_161___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_161___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_162 (0x005E4288) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_162___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_162___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_162__RX_DCOC_RANGE_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_162__RX_DCOC_RES_I_162___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_162__RX_DCOC_RES_Q_162___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_162__RX_DCOC_RANGE_162___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_162__RX_DCOC_RANGE_162___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_162__RX_DCOC_RES_I_162___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_162__RX_DCOC_RES_I_162___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_162__RX_DCOC_RES_Q_162___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_162__RX_DCOC_RES_Q_162___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_162___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_162___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_163 (0x005E428C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_163___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_163___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_163__RX_DCOC_RANGE_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_163__RX_DCOC_RES_I_163___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_163__RX_DCOC_RES_Q_163___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_163__RX_DCOC_RANGE_163___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_163__RX_DCOC_RANGE_163___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_163__RX_DCOC_RES_I_163___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_163__RX_DCOC_RES_I_163___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_163__RX_DCOC_RES_Q_163___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_163__RX_DCOC_RES_Q_163___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_163___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_163___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_164 (0x005E4290) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_164___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_164___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_164__RX_DCOC_RANGE_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_164__RX_DCOC_RES_I_164___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_164__RX_DCOC_RES_Q_164___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_164__RX_DCOC_RANGE_164___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_164__RX_DCOC_RANGE_164___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_164__RX_DCOC_RES_I_164___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_164__RX_DCOC_RES_I_164___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_164__RX_DCOC_RES_Q_164___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_164__RX_DCOC_RES_Q_164___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_164___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_164___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_165 (0x005E4294) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_165___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_165___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_165__RX_DCOC_RANGE_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_165__RX_DCOC_RES_I_165___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_165__RX_DCOC_RES_Q_165___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_165__RX_DCOC_RANGE_165___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_165__RX_DCOC_RANGE_165___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_165__RX_DCOC_RES_I_165___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_165__RX_DCOC_RES_I_165___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_165__RX_DCOC_RES_Q_165___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_165__RX_DCOC_RES_Q_165___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_165___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_165___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_166 (0x005E4298) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_166___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_166___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_166__RX_DCOC_RANGE_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_166__RX_DCOC_RES_I_166___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_166__RX_DCOC_RES_Q_166___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_166__RX_DCOC_RANGE_166___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_166__RX_DCOC_RANGE_166___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_166__RX_DCOC_RES_I_166___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_166__RX_DCOC_RES_I_166___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_166__RX_DCOC_RES_Q_166___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_166__RX_DCOC_RES_Q_166___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_166___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_166___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_167 (0x005E429C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_167___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_167___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_167__RX_DCOC_RANGE_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_167__RX_DCOC_RES_I_167___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_167__RX_DCOC_RES_Q_167___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_167__RX_DCOC_RANGE_167___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_167__RX_DCOC_RANGE_167___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_167__RX_DCOC_RES_I_167___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_167__RX_DCOC_RES_I_167___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_167__RX_DCOC_RES_Q_167___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_167__RX_DCOC_RES_Q_167___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_167___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_167___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_168 (0x005E42A0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_168___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_168___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_168__RX_DCOC_RANGE_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_168__RX_DCOC_RES_I_168___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_168__RX_DCOC_RES_Q_168___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_168__RX_DCOC_RANGE_168___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_168__RX_DCOC_RANGE_168___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_168__RX_DCOC_RES_I_168___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_168__RX_DCOC_RES_I_168___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_168__RX_DCOC_RES_Q_168___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_168__RX_DCOC_RES_Q_168___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_168___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_168___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_169 (0x005E42A4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_169___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_169___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_169__RX_DCOC_RANGE_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_169__RX_DCOC_RES_I_169___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_169__RX_DCOC_RES_Q_169___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_169__RX_DCOC_RANGE_169___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_169__RX_DCOC_RANGE_169___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_169__RX_DCOC_RES_I_169___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_169__RX_DCOC_RES_I_169___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_169__RX_DCOC_RES_Q_169___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_169__RX_DCOC_RES_Q_169___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_169___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_169___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_170 (0x005E42A8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_170___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_170___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_170__RX_DCOC_RANGE_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_170__RX_DCOC_RES_I_170___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_170__RX_DCOC_RES_Q_170___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_170__RX_DCOC_RANGE_170___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_170__RX_DCOC_RANGE_170___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_170__RX_DCOC_RES_I_170___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_170__RX_DCOC_RES_I_170___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_170__RX_DCOC_RES_Q_170___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_170__RX_DCOC_RES_Q_170___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_170___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_170___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_171 (0x005E42AC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_171___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_171___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_171__RX_DCOC_RANGE_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_171__RX_DCOC_RES_I_171___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_171__RX_DCOC_RES_Q_171___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_171__RX_DCOC_RANGE_171___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_171__RX_DCOC_RANGE_171___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_171__RX_DCOC_RES_I_171___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_171__RX_DCOC_RES_I_171___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_171__RX_DCOC_RES_Q_171___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_171__RX_DCOC_RES_Q_171___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_171___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_171___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_172 (0x005E42B0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_172___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_172___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_172__RX_DCOC_RANGE_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_172__RX_DCOC_RES_I_172___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_172__RX_DCOC_RES_Q_172___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_172__RX_DCOC_RANGE_172___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_172__RX_DCOC_RANGE_172___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_172__RX_DCOC_RES_I_172___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_172__RX_DCOC_RES_I_172___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_172__RX_DCOC_RES_Q_172___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_172__RX_DCOC_RES_Q_172___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_172___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_172___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_173 (0x005E42B4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_173___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_173___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_173__RX_DCOC_RANGE_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_173__RX_DCOC_RES_I_173___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_173__RX_DCOC_RES_Q_173___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_173__RX_DCOC_RANGE_173___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_173__RX_DCOC_RANGE_173___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_173__RX_DCOC_RES_I_173___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_173__RX_DCOC_RES_I_173___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_173__RX_DCOC_RES_Q_173___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_173__RX_DCOC_RES_Q_173___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_173___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_173___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_174 (0x005E42B8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_174___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_174___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_174__RX_DCOC_RANGE_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_174__RX_DCOC_RES_I_174___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_174__RX_DCOC_RES_Q_174___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_174__RX_DCOC_RANGE_174___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_174__RX_DCOC_RANGE_174___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_174__RX_DCOC_RES_I_174___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_174__RX_DCOC_RES_I_174___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_174__RX_DCOC_RES_Q_174___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_174__RX_DCOC_RES_Q_174___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_174___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_174___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_175 (0x005E42BC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_175___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_175___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_175__RX_DCOC_RANGE_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_175__RX_DCOC_RES_I_175___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_175__RX_DCOC_RES_Q_175___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_175__RX_DCOC_RANGE_175___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_175__RX_DCOC_RANGE_175___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_175__RX_DCOC_RES_I_175___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_175__RX_DCOC_RES_I_175___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_175__RX_DCOC_RES_Q_175___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_175__RX_DCOC_RES_Q_175___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_175___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_175___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_176 (0x005E42C0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_176___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_176___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_176__RX_DCOC_RANGE_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_176__RX_DCOC_RES_I_176___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_176__RX_DCOC_RES_Q_176___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_176__RX_DCOC_RANGE_176___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_176__RX_DCOC_RANGE_176___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_176__RX_DCOC_RES_I_176___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_176__RX_DCOC_RES_I_176___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_176__RX_DCOC_RES_Q_176___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_176__RX_DCOC_RES_Q_176___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_176___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_176___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_177 (0x005E42C4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_177___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_177___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_177__RX_DCOC_RANGE_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_177__RX_DCOC_RES_I_177___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_177__RX_DCOC_RES_Q_177___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_177__RX_DCOC_RANGE_177___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_177__RX_DCOC_RANGE_177___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_177__RX_DCOC_RES_I_177___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_177__RX_DCOC_RES_I_177___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_177__RX_DCOC_RES_Q_177___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_177__RX_DCOC_RES_Q_177___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_177___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_177___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_178 (0x005E42C8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_178___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_178___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_178__RX_DCOC_RANGE_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_178__RX_DCOC_RES_I_178___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_178__RX_DCOC_RES_Q_178___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_178__RX_DCOC_RANGE_178___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_178__RX_DCOC_RANGE_178___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_178__RX_DCOC_RES_I_178___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_178__RX_DCOC_RES_I_178___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_178__RX_DCOC_RES_Q_178___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_178__RX_DCOC_RES_Q_178___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_178___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_178___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_179 (0x005E42CC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_179___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_179___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_179__RX_DCOC_RANGE_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_179__RX_DCOC_RES_I_179___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_179__RX_DCOC_RES_Q_179___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_179__RX_DCOC_RANGE_179___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_179__RX_DCOC_RANGE_179___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_179__RX_DCOC_RES_I_179___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_179__RX_DCOC_RES_I_179___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_179__RX_DCOC_RES_Q_179___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_179__RX_DCOC_RES_Q_179___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_179___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_179___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_180 (0x005E42D0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_180___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_180___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_180__RX_DCOC_RANGE_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_180__RX_DCOC_RES_I_180___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_180__RX_DCOC_RES_Q_180___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_180__RX_DCOC_RANGE_180___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_180__RX_DCOC_RANGE_180___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_180__RX_DCOC_RES_I_180___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_180__RX_DCOC_RES_I_180___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_180__RX_DCOC_RES_Q_180___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_180__RX_DCOC_RES_Q_180___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_180___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_180___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_181 (0x005E42D4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_181___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_181___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_181__RX_DCOC_RANGE_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_181__RX_DCOC_RES_I_181___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_181__RX_DCOC_RES_Q_181___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_181__RX_DCOC_RANGE_181___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_181__RX_DCOC_RANGE_181___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_181__RX_DCOC_RES_I_181___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_181__RX_DCOC_RES_I_181___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_181__RX_DCOC_RES_Q_181___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_181__RX_DCOC_RES_Q_181___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_181___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_181___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_182 (0x005E42D8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_182___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_182___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_182__RX_DCOC_RANGE_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_182__RX_DCOC_RES_I_182___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_182__RX_DCOC_RES_Q_182___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_182__RX_DCOC_RANGE_182___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_182__RX_DCOC_RANGE_182___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_182__RX_DCOC_RES_I_182___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_182__RX_DCOC_RES_I_182___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_182__RX_DCOC_RES_Q_182___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_182__RX_DCOC_RES_Q_182___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_182___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_182___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_183 (0x005E42DC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_183___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_183___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_183__RX_DCOC_RANGE_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_183__RX_DCOC_RES_I_183___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_183__RX_DCOC_RES_Q_183___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_183__RX_DCOC_RANGE_183___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_183__RX_DCOC_RANGE_183___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_183__RX_DCOC_RES_I_183___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_183__RX_DCOC_RES_I_183___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_183__RX_DCOC_RES_Q_183___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_183__RX_DCOC_RES_Q_183___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_183___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_183___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_184 (0x005E42E0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_184___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_184___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_184__RX_DCOC_RANGE_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_184__RX_DCOC_RES_I_184___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_184__RX_DCOC_RES_Q_184___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_184__RX_DCOC_RANGE_184___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_184__RX_DCOC_RANGE_184___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_184__RX_DCOC_RES_I_184___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_184__RX_DCOC_RES_I_184___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_184__RX_DCOC_RES_Q_184___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_184__RX_DCOC_RES_Q_184___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_184___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_184___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_185 (0x005E42E4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_185___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_185___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_185__RX_DCOC_RANGE_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_185__RX_DCOC_RES_I_185___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_185__RX_DCOC_RES_Q_185___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_185__RX_DCOC_RANGE_185___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_185__RX_DCOC_RANGE_185___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_185__RX_DCOC_RES_I_185___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_185__RX_DCOC_RES_I_185___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_185__RX_DCOC_RES_Q_185___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_185__RX_DCOC_RES_Q_185___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_185___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_185___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_186 (0x005E42E8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_186___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_186___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_186__RX_DCOC_RANGE_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_186__RX_DCOC_RES_I_186___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_186__RX_DCOC_RES_Q_186___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_186__RX_DCOC_RANGE_186___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_186__RX_DCOC_RANGE_186___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_186__RX_DCOC_RES_I_186___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_186__RX_DCOC_RES_I_186___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_186__RX_DCOC_RES_Q_186___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_186__RX_DCOC_RES_Q_186___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_186___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_186___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_187 (0x005E42EC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_187___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_187___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_187__RX_DCOC_RANGE_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_187__RX_DCOC_RES_I_187___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_187__RX_DCOC_RES_Q_187___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_187__RX_DCOC_RANGE_187___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_187__RX_DCOC_RANGE_187___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_187__RX_DCOC_RES_I_187___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_187__RX_DCOC_RES_I_187___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_187__RX_DCOC_RES_Q_187___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_187__RX_DCOC_RES_Q_187___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_187___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_187___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_188 (0x005E42F0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_188___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_188___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_188__RX_DCOC_RANGE_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_188__RX_DCOC_RES_I_188___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_188__RX_DCOC_RES_Q_188___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_188__RX_DCOC_RANGE_188___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_188__RX_DCOC_RANGE_188___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_188__RX_DCOC_RES_I_188___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_188__RX_DCOC_RES_I_188___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_188__RX_DCOC_RES_Q_188___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_188__RX_DCOC_RES_Q_188___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_188___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_188___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_189 (0x005E42F4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_189___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_189___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_189__RX_DCOC_RANGE_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_189__RX_DCOC_RES_I_189___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_189__RX_DCOC_RES_Q_189___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_189__RX_DCOC_RANGE_189___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_189__RX_DCOC_RANGE_189___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_189__RX_DCOC_RES_I_189___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_189__RX_DCOC_RES_I_189___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_189__RX_DCOC_RES_Q_189___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_189__RX_DCOC_RES_Q_189___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_189___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_189___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_190 (0x005E42F8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_190___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_190___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_190__RX_DCOC_RANGE_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_190__RX_DCOC_RES_I_190___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_190__RX_DCOC_RES_Q_190___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_190__RX_DCOC_RANGE_190___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_190__RX_DCOC_RANGE_190___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_190__RX_DCOC_RES_I_190___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_190__RX_DCOC_RES_I_190___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_190__RX_DCOC_RES_Q_190___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_190__RX_DCOC_RES_Q_190___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_190___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_190___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_191 (0x005E42FC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_191___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_191___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_191__RX_DCOC_RANGE_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_191__RX_DCOC_RES_I_191___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_191__RX_DCOC_RES_Q_191___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_191__RX_DCOC_RANGE_191___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_191__RX_DCOC_RANGE_191___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_191__RX_DCOC_RES_I_191___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_191__RX_DCOC_RES_I_191___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_191__RX_DCOC_RES_Q_191___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_191__RX_DCOC_RES_Q_191___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_191___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_191___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_192 (0x005E4300) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_192___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_192___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_192__RX_DCOC_RANGE_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_192__RX_DCOC_RES_I_192___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_192__RX_DCOC_RES_Q_192___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_192__RX_DCOC_RANGE_192___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_192__RX_DCOC_RANGE_192___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_192__RX_DCOC_RES_I_192___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_192__RX_DCOC_RES_I_192___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_192__RX_DCOC_RES_Q_192___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_192__RX_DCOC_RES_Q_192___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_192___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_192___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_193 (0x005E4304) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_193___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_193___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_193__RX_DCOC_RANGE_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_193__RX_DCOC_RES_I_193___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_193__RX_DCOC_RES_Q_193___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_193__RX_DCOC_RANGE_193___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_193__RX_DCOC_RANGE_193___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_193__RX_DCOC_RES_I_193___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_193__RX_DCOC_RES_I_193___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_193__RX_DCOC_RES_Q_193___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_193__RX_DCOC_RES_Q_193___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_193___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_193___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_194 (0x005E4308) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_194___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_194___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_194__RX_DCOC_RANGE_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_194__RX_DCOC_RES_I_194___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_194__RX_DCOC_RES_Q_194___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_194__RX_DCOC_RANGE_194___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_194__RX_DCOC_RANGE_194___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_194__RX_DCOC_RES_I_194___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_194__RX_DCOC_RES_I_194___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_194__RX_DCOC_RES_Q_194___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_194__RX_DCOC_RES_Q_194___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_194___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_194___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_195 (0x005E430C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_195___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_195___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_195__RX_DCOC_RANGE_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_195__RX_DCOC_RES_I_195___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_195__RX_DCOC_RES_Q_195___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_195__RX_DCOC_RANGE_195___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_195__RX_DCOC_RANGE_195___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_195__RX_DCOC_RES_I_195___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_195__RX_DCOC_RES_I_195___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_195__RX_DCOC_RES_Q_195___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_195__RX_DCOC_RES_Q_195___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_195___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_195___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_196 (0x005E4310) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_196___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_196___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_196__RX_DCOC_RANGE_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_196__RX_DCOC_RES_I_196___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_196__RX_DCOC_RES_Q_196___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_196__RX_DCOC_RANGE_196___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_196__RX_DCOC_RANGE_196___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_196__RX_DCOC_RES_I_196___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_196__RX_DCOC_RES_I_196___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_196__RX_DCOC_RES_Q_196___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_196__RX_DCOC_RES_Q_196___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_196___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_196___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_197 (0x005E4314) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_197___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_197___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_197__RX_DCOC_RANGE_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_197__RX_DCOC_RES_I_197___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_197__RX_DCOC_RES_Q_197___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_197__RX_DCOC_RANGE_197___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_197__RX_DCOC_RANGE_197___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_197__RX_DCOC_RES_I_197___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_197__RX_DCOC_RES_I_197___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_197__RX_DCOC_RES_Q_197___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_197__RX_DCOC_RES_Q_197___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_197___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_197___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_198 (0x005E4318) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_198___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_198___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_198__RX_DCOC_RANGE_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_198__RX_DCOC_RES_I_198___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_198__RX_DCOC_RES_Q_198___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_198__RX_DCOC_RANGE_198___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_198__RX_DCOC_RANGE_198___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_198__RX_DCOC_RES_I_198___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_198__RX_DCOC_RES_I_198___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_198__RX_DCOC_RES_Q_198___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_198__RX_DCOC_RES_Q_198___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_198___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_198___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_199 (0x005E431C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_199___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_199___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_199__RX_DCOC_RANGE_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_199__RX_DCOC_RES_I_199___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_199__RX_DCOC_RES_Q_199___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_199__RX_DCOC_RANGE_199___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_199__RX_DCOC_RANGE_199___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_199__RX_DCOC_RES_I_199___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_199__RX_DCOC_RES_I_199___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_199__RX_DCOC_RES_Q_199___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_199__RX_DCOC_RES_Q_199___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_199___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_199___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_200 (0x005E4320) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_200___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_200___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_200__RX_DCOC_RANGE_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_200__RX_DCOC_RES_I_200___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_200__RX_DCOC_RES_Q_200___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_200__RX_DCOC_RANGE_200___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_200__RX_DCOC_RANGE_200___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_200__RX_DCOC_RES_I_200___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_200__RX_DCOC_RES_I_200___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_200__RX_DCOC_RES_Q_200___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_200__RX_DCOC_RES_Q_200___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_200___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_200___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_201 (0x005E4324) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_201___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_201___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_201__RX_DCOC_RANGE_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_201__RX_DCOC_RES_I_201___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_201__RX_DCOC_RES_Q_201___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_201__RX_DCOC_RANGE_201___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_201__RX_DCOC_RANGE_201___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_201__RX_DCOC_RES_I_201___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_201__RX_DCOC_RES_I_201___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_201__RX_DCOC_RES_Q_201___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_201__RX_DCOC_RES_Q_201___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_201___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_201___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_202 (0x005E4328) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_202___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_202___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_202__RX_DCOC_RANGE_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_202__RX_DCOC_RES_I_202___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_202__RX_DCOC_RES_Q_202___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_202__RX_DCOC_RANGE_202___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_202__RX_DCOC_RANGE_202___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_202__RX_DCOC_RES_I_202___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_202__RX_DCOC_RES_I_202___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_202__RX_DCOC_RES_Q_202___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_202__RX_DCOC_RES_Q_202___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_202___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_202___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_203 (0x005E432C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_203___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_203___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_203__RX_DCOC_RANGE_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_203__RX_DCOC_RES_I_203___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_203__RX_DCOC_RES_Q_203___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_203__RX_DCOC_RANGE_203___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_203__RX_DCOC_RANGE_203___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_203__RX_DCOC_RES_I_203___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_203__RX_DCOC_RES_I_203___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_203__RX_DCOC_RES_Q_203___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_203__RX_DCOC_RES_Q_203___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_203___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_203___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_204 (0x005E4330) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_204___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_204___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_204__RX_DCOC_RANGE_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_204__RX_DCOC_RES_I_204___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_204__RX_DCOC_RES_Q_204___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_204__RX_DCOC_RANGE_204___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_204__RX_DCOC_RANGE_204___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_204__RX_DCOC_RES_I_204___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_204__RX_DCOC_RES_I_204___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_204__RX_DCOC_RES_Q_204___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_204__RX_DCOC_RES_Q_204___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_204___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_204___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_205 (0x005E4334) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_205___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_205___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_205__RX_DCOC_RANGE_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_205__RX_DCOC_RES_I_205___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_205__RX_DCOC_RES_Q_205___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_205__RX_DCOC_RANGE_205___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_205__RX_DCOC_RANGE_205___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_205__RX_DCOC_RES_I_205___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_205__RX_DCOC_RES_I_205___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_205__RX_DCOC_RES_Q_205___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_205__RX_DCOC_RES_Q_205___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_205___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_205___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_206 (0x005E4338) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_206___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_206___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_206__RX_DCOC_RANGE_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_206__RX_DCOC_RES_I_206___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_206__RX_DCOC_RES_Q_206___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_206__RX_DCOC_RANGE_206___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_206__RX_DCOC_RANGE_206___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_206__RX_DCOC_RES_I_206___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_206__RX_DCOC_RES_I_206___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_206__RX_DCOC_RES_Q_206___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_206__RX_DCOC_RES_Q_206___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_206___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_206___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_207 (0x005E433C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_207___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_207___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_207__RX_DCOC_RANGE_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_207__RX_DCOC_RES_I_207___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_207__RX_DCOC_RES_Q_207___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_207__RX_DCOC_RANGE_207___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_207__RX_DCOC_RANGE_207___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_207__RX_DCOC_RES_I_207___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_207__RX_DCOC_RES_I_207___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_207__RX_DCOC_RES_Q_207___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_207__RX_DCOC_RES_Q_207___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_207___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_207___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_208 (0x005E4340) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_208___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_208___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_208__RX_DCOC_RANGE_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_208__RX_DCOC_RES_I_208___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_208__RX_DCOC_RES_Q_208___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_208__RX_DCOC_RANGE_208___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_208__RX_DCOC_RANGE_208___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_208__RX_DCOC_RES_I_208___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_208__RX_DCOC_RES_I_208___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_208__RX_DCOC_RES_Q_208___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_208__RX_DCOC_RES_Q_208___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_208___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_208___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_209 (0x005E4344) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_209___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_209___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_209__RX_DCOC_RANGE_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_209__RX_DCOC_RES_I_209___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_209__RX_DCOC_RES_Q_209___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_209__RX_DCOC_RANGE_209___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_209__RX_DCOC_RANGE_209___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_209__RX_DCOC_RES_I_209___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_209__RX_DCOC_RES_I_209___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_209__RX_DCOC_RES_Q_209___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_209__RX_DCOC_RES_Q_209___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_209___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_209___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_210 (0x005E4348) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_210___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_210___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_210__RX_DCOC_RANGE_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_210__RX_DCOC_RES_I_210___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_210__RX_DCOC_RES_Q_210___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_210__RX_DCOC_RANGE_210___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_210__RX_DCOC_RANGE_210___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_210__RX_DCOC_RES_I_210___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_210__RX_DCOC_RES_I_210___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_210__RX_DCOC_RES_Q_210___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_210__RX_DCOC_RES_Q_210___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_210___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_210___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_211 (0x005E434C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_211___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_211___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_211__RX_DCOC_RANGE_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_211__RX_DCOC_RES_I_211___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_211__RX_DCOC_RES_Q_211___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_211__RX_DCOC_RANGE_211___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_211__RX_DCOC_RANGE_211___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_211__RX_DCOC_RES_I_211___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_211__RX_DCOC_RES_I_211___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_211__RX_DCOC_RES_Q_211___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_211__RX_DCOC_RES_Q_211___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_211___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_211___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_212 (0x005E4350) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_212___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_212___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_212__RX_DCOC_RANGE_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_212__RX_DCOC_RES_I_212___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_212__RX_DCOC_RES_Q_212___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_212__RX_DCOC_RANGE_212___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_212__RX_DCOC_RANGE_212___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_212__RX_DCOC_RES_I_212___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_212__RX_DCOC_RES_I_212___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_212__RX_DCOC_RES_Q_212___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_212__RX_DCOC_RES_Q_212___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_212___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_212___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_213 (0x005E4354) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_213___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_213___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_213__RX_DCOC_RANGE_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_213__RX_DCOC_RES_I_213___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_213__RX_DCOC_RES_Q_213___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_213__RX_DCOC_RANGE_213___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_213__RX_DCOC_RANGE_213___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_213__RX_DCOC_RES_I_213___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_213__RX_DCOC_RES_I_213___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_213__RX_DCOC_RES_Q_213___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_213__RX_DCOC_RES_Q_213___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_213___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_213___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_214 (0x005E4358) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_214___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_214___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_214__RX_DCOC_RANGE_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_214__RX_DCOC_RES_I_214___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_214__RX_DCOC_RES_Q_214___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_214__RX_DCOC_RANGE_214___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_214__RX_DCOC_RANGE_214___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_214__RX_DCOC_RES_I_214___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_214__RX_DCOC_RES_I_214___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_214__RX_DCOC_RES_Q_214___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_214__RX_DCOC_RES_Q_214___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_214___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_214___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_215 (0x005E435C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_215___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_215___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_215__RX_DCOC_RANGE_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_215__RX_DCOC_RES_I_215___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_215__RX_DCOC_RES_Q_215___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_215__RX_DCOC_RANGE_215___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_215__RX_DCOC_RANGE_215___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_215__RX_DCOC_RES_I_215___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_215__RX_DCOC_RES_I_215___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_215__RX_DCOC_RES_Q_215___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_215__RX_DCOC_RES_Q_215___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_215___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_215___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_216 (0x005E4360) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_216___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_216___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_216__RX_DCOC_RANGE_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_216__RX_DCOC_RES_I_216___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_216__RX_DCOC_RES_Q_216___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_216__RX_DCOC_RANGE_216___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_216__RX_DCOC_RANGE_216___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_216__RX_DCOC_RES_I_216___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_216__RX_DCOC_RES_I_216___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_216__RX_DCOC_RES_Q_216___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_216__RX_DCOC_RES_Q_216___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_216___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_216___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_217 (0x005E4364) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_217___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_217___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_217__RX_DCOC_RANGE_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_217__RX_DCOC_RES_I_217___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_217__RX_DCOC_RES_Q_217___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_217__RX_DCOC_RANGE_217___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_217__RX_DCOC_RANGE_217___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_217__RX_DCOC_RES_I_217___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_217__RX_DCOC_RES_I_217___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_217__RX_DCOC_RES_Q_217___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_217__RX_DCOC_RES_Q_217___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_217___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_217___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_218 (0x005E4368) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_218___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_218___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_218__RX_DCOC_RANGE_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_218__RX_DCOC_RES_I_218___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_218__RX_DCOC_RES_Q_218___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_218__RX_DCOC_RANGE_218___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_218__RX_DCOC_RANGE_218___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_218__RX_DCOC_RES_I_218___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_218__RX_DCOC_RES_I_218___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_218__RX_DCOC_RES_Q_218___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_218__RX_DCOC_RES_Q_218___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_218___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_218___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_219 (0x005E436C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_219___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_219___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_219__RX_DCOC_RANGE_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_219__RX_DCOC_RES_I_219___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_219__RX_DCOC_RES_Q_219___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_219__RX_DCOC_RANGE_219___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_219__RX_DCOC_RANGE_219___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_219__RX_DCOC_RES_I_219___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_219__RX_DCOC_RES_I_219___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_219__RX_DCOC_RES_Q_219___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_219__RX_DCOC_RES_Q_219___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_219___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_219___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_220 (0x005E4370) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_220___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_220___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_220__RX_DCOC_RANGE_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_220__RX_DCOC_RES_I_220___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_220__RX_DCOC_RES_Q_220___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_220__RX_DCOC_RANGE_220___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_220__RX_DCOC_RANGE_220___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_220__RX_DCOC_RES_I_220___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_220__RX_DCOC_RES_I_220___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_220__RX_DCOC_RES_Q_220___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_220__RX_DCOC_RES_Q_220___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_220___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_220___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_221 (0x005E4374) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_221___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_221___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_221__RX_DCOC_RANGE_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_221__RX_DCOC_RES_I_221___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_221__RX_DCOC_RES_Q_221___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_221__RX_DCOC_RANGE_221___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_221__RX_DCOC_RANGE_221___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_221__RX_DCOC_RES_I_221___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_221__RX_DCOC_RES_I_221___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_221__RX_DCOC_RES_Q_221___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_221__RX_DCOC_RES_Q_221___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_221___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_221___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_222 (0x005E4378) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_222___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_222___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_222__RX_DCOC_RANGE_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_222__RX_DCOC_RES_I_222___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_222__RX_DCOC_RES_Q_222___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_222__RX_DCOC_RANGE_222___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_222__RX_DCOC_RANGE_222___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_222__RX_DCOC_RES_I_222___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_222__RX_DCOC_RES_I_222___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_222__RX_DCOC_RES_Q_222___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_222__RX_DCOC_RES_Q_222___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_222___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_222___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_223 (0x005E437C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_223___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_223___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_223__RX_DCOC_RANGE_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_223__RX_DCOC_RES_I_223___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_223__RX_DCOC_RES_Q_223___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_223__RX_DCOC_RANGE_223___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_223__RX_DCOC_RANGE_223___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_223__RX_DCOC_RES_I_223___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_223__RX_DCOC_RES_I_223___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_223__RX_DCOC_RES_Q_223___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_223__RX_DCOC_RES_Q_223___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_223___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_223___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_224 (0x005E4380) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_224___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_224___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_224__RX_DCOC_RANGE_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_224__RX_DCOC_RES_I_224___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_224__RX_DCOC_RES_Q_224___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_224__RX_DCOC_RANGE_224___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_224__RX_DCOC_RANGE_224___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_224__RX_DCOC_RES_I_224___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_224__RX_DCOC_RES_I_224___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_224__RX_DCOC_RES_Q_224___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_224__RX_DCOC_RES_Q_224___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_224___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_224___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_225 (0x005E4384) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_225___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_225___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_225__RX_DCOC_RANGE_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_225__RX_DCOC_RES_I_225___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_225__RX_DCOC_RES_Q_225___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_225__RX_DCOC_RANGE_225___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_225__RX_DCOC_RANGE_225___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_225__RX_DCOC_RES_I_225___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_225__RX_DCOC_RES_I_225___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_225__RX_DCOC_RES_Q_225___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_225__RX_DCOC_RES_Q_225___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_225___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_225___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_226 (0x005E4388) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_226___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_226___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_226__RX_DCOC_RANGE_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_226__RX_DCOC_RES_I_226___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_226__RX_DCOC_RES_Q_226___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_226__RX_DCOC_RANGE_226___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_226__RX_DCOC_RANGE_226___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_226__RX_DCOC_RES_I_226___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_226__RX_DCOC_RES_I_226___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_226__RX_DCOC_RES_Q_226___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_226__RX_DCOC_RES_Q_226___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_226___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_226___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_227 (0x005E438C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_227___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_227___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_227__RX_DCOC_RANGE_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_227__RX_DCOC_RES_I_227___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_227__RX_DCOC_RES_Q_227___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_227__RX_DCOC_RANGE_227___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_227__RX_DCOC_RANGE_227___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_227__RX_DCOC_RES_I_227___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_227__RX_DCOC_RES_I_227___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_227__RX_DCOC_RES_Q_227___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_227__RX_DCOC_RES_Q_227___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_227___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_227___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_228 (0x005E4390) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_228___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_228___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_228__RX_DCOC_RANGE_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_228__RX_DCOC_RES_I_228___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_228__RX_DCOC_RES_Q_228___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_228__RX_DCOC_RANGE_228___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_228__RX_DCOC_RANGE_228___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_228__RX_DCOC_RES_I_228___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_228__RX_DCOC_RES_I_228___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_228__RX_DCOC_RES_Q_228___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_228__RX_DCOC_RES_Q_228___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_228___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_228___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_229 (0x005E4394) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_229___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_229___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_229__RX_DCOC_RANGE_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_229__RX_DCOC_RES_I_229___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_229__RX_DCOC_RES_Q_229___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_229__RX_DCOC_RANGE_229___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_229__RX_DCOC_RANGE_229___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_229__RX_DCOC_RES_I_229___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_229__RX_DCOC_RES_I_229___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_229__RX_DCOC_RES_Q_229___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_229__RX_DCOC_RES_Q_229___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_229___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_229___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_230 (0x005E4398) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_230___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_230___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_230__RX_DCOC_RANGE_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_230__RX_DCOC_RES_I_230___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_230__RX_DCOC_RES_Q_230___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_230__RX_DCOC_RANGE_230___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_230__RX_DCOC_RANGE_230___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_230__RX_DCOC_RES_I_230___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_230__RX_DCOC_RES_I_230___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_230__RX_DCOC_RES_Q_230___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_230__RX_DCOC_RES_Q_230___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_230___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_230___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_231 (0x005E439C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_231___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_231___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_231__RX_DCOC_RANGE_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_231__RX_DCOC_RES_I_231___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_231__RX_DCOC_RES_Q_231___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_231__RX_DCOC_RANGE_231___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_231__RX_DCOC_RANGE_231___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_231__RX_DCOC_RES_I_231___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_231__RX_DCOC_RES_I_231___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_231__RX_DCOC_RES_Q_231___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_231__RX_DCOC_RES_Q_231___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_231___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_231___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_232 (0x005E43A0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_232___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_232___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_232__RX_DCOC_RANGE_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_232__RX_DCOC_RES_I_232___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_232__RX_DCOC_RES_Q_232___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_232__RX_DCOC_RANGE_232___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_232__RX_DCOC_RANGE_232___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_232__RX_DCOC_RES_I_232___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_232__RX_DCOC_RES_I_232___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_232__RX_DCOC_RES_Q_232___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_232__RX_DCOC_RES_Q_232___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_232___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_232___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_233 (0x005E43A4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_233___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_233___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_233__RX_DCOC_RANGE_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_233__RX_DCOC_RES_I_233___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_233__RX_DCOC_RES_Q_233___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_233__RX_DCOC_RANGE_233___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_233__RX_DCOC_RANGE_233___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_233__RX_DCOC_RES_I_233___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_233__RX_DCOC_RES_I_233___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_233__RX_DCOC_RES_Q_233___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_233__RX_DCOC_RES_Q_233___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_233___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_233___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_234 (0x005E43A8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_234___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_234___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_234__RX_DCOC_RANGE_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_234__RX_DCOC_RES_I_234___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_234__RX_DCOC_RES_Q_234___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_234__RX_DCOC_RANGE_234___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_234__RX_DCOC_RANGE_234___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_234__RX_DCOC_RES_I_234___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_234__RX_DCOC_RES_I_234___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_234__RX_DCOC_RES_Q_234___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_234__RX_DCOC_RES_Q_234___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_234___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_234___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_235 (0x005E43AC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_235___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_235___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_235__RX_DCOC_RANGE_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_235__RX_DCOC_RES_I_235___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_235__RX_DCOC_RES_Q_235___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_235__RX_DCOC_RANGE_235___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_235__RX_DCOC_RANGE_235___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_235__RX_DCOC_RES_I_235___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_235__RX_DCOC_RES_I_235___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_235__RX_DCOC_RES_Q_235___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_235__RX_DCOC_RES_Q_235___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_235___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_235___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_236 (0x005E43B0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_236___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_236___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_236__RX_DCOC_RANGE_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_236__RX_DCOC_RES_I_236___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_236__RX_DCOC_RES_Q_236___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_236__RX_DCOC_RANGE_236___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_236__RX_DCOC_RANGE_236___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_236__RX_DCOC_RES_I_236___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_236__RX_DCOC_RES_I_236___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_236__RX_DCOC_RES_Q_236___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_236__RX_DCOC_RES_Q_236___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_236___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_236___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_237 (0x005E43B4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_237___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_237___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_237__RX_DCOC_RANGE_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_237__RX_DCOC_RES_I_237___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_237__RX_DCOC_RES_Q_237___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_237__RX_DCOC_RANGE_237___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_237__RX_DCOC_RANGE_237___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_237__RX_DCOC_RES_I_237___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_237__RX_DCOC_RES_I_237___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_237__RX_DCOC_RES_Q_237___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_237__RX_DCOC_RES_Q_237___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_237___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_237___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_238 (0x005E43B8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_238___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_238___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_238__RX_DCOC_RANGE_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_238__RX_DCOC_RES_I_238___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_238__RX_DCOC_RES_Q_238___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_238__RX_DCOC_RANGE_238___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_238__RX_DCOC_RANGE_238___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_238__RX_DCOC_RES_I_238___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_238__RX_DCOC_RES_I_238___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_238__RX_DCOC_RES_Q_238___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_238__RX_DCOC_RES_Q_238___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_238___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_238___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_239 (0x005E43BC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_239___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_239___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_239__RX_DCOC_RANGE_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_239__RX_DCOC_RES_I_239___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_239__RX_DCOC_RES_Q_239___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_239__RX_DCOC_RANGE_239___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_239__RX_DCOC_RANGE_239___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_239__RX_DCOC_RES_I_239___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_239__RX_DCOC_RES_I_239___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_239__RX_DCOC_RES_Q_239___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_239__RX_DCOC_RES_Q_239___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_239___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_239___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_240 (0x005E43C0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_240___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_240___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_240__RX_DCOC_RANGE_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_240__RX_DCOC_RES_I_240___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_240__RX_DCOC_RES_Q_240___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_240__RX_DCOC_RANGE_240___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_240__RX_DCOC_RANGE_240___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_240__RX_DCOC_RES_I_240___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_240__RX_DCOC_RES_I_240___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_240__RX_DCOC_RES_Q_240___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_240__RX_DCOC_RES_Q_240___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_240___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_240___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_241 (0x005E43C4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_241___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_241___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_241__RX_DCOC_RANGE_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_241__RX_DCOC_RES_I_241___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_241__RX_DCOC_RES_Q_241___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_241__RX_DCOC_RANGE_241___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_241__RX_DCOC_RANGE_241___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_241__RX_DCOC_RES_I_241___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_241__RX_DCOC_RES_I_241___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_241__RX_DCOC_RES_Q_241___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_241__RX_DCOC_RES_Q_241___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_241___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_241___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_242 (0x005E43C8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_242___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_242___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_242__RX_DCOC_RANGE_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_242__RX_DCOC_RES_I_242___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_242__RX_DCOC_RES_Q_242___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_242__RX_DCOC_RANGE_242___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_242__RX_DCOC_RANGE_242___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_242__RX_DCOC_RES_I_242___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_242__RX_DCOC_RES_I_242___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_242__RX_DCOC_RES_Q_242___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_242__RX_DCOC_RES_Q_242___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_242___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_242___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_243 (0x005E43CC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_243___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_243___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_243__RX_DCOC_RANGE_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_243__RX_DCOC_RES_I_243___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_243__RX_DCOC_RES_Q_243___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_243__RX_DCOC_RANGE_243___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_243__RX_DCOC_RANGE_243___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_243__RX_DCOC_RES_I_243___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_243__RX_DCOC_RES_I_243___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_243__RX_DCOC_RES_Q_243___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_243__RX_DCOC_RES_Q_243___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_243___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_243___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_244 (0x005E43D0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_244___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_244___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_244__RX_DCOC_RANGE_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_244__RX_DCOC_RES_I_244___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_244__RX_DCOC_RES_Q_244___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_244__RX_DCOC_RANGE_244___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_244__RX_DCOC_RANGE_244___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_244__RX_DCOC_RES_I_244___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_244__RX_DCOC_RES_I_244___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_244__RX_DCOC_RES_Q_244___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_244__RX_DCOC_RES_Q_244___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_244___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_244___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_245 (0x005E43D4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_245___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_245___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_245__RX_DCOC_RANGE_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_245__RX_DCOC_RES_I_245___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_245__RX_DCOC_RES_Q_245___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_245__RX_DCOC_RANGE_245___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_245__RX_DCOC_RANGE_245___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_245__RX_DCOC_RES_I_245___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_245__RX_DCOC_RES_I_245___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_245__RX_DCOC_RES_Q_245___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_245__RX_DCOC_RES_Q_245___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_245___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_245___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_246 (0x005E43D8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_246___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_246___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_246__RX_DCOC_RANGE_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_246__RX_DCOC_RES_I_246___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_246__RX_DCOC_RES_Q_246___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_246__RX_DCOC_RANGE_246___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_246__RX_DCOC_RANGE_246___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_246__RX_DCOC_RES_I_246___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_246__RX_DCOC_RES_I_246___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_246__RX_DCOC_RES_Q_246___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_246__RX_DCOC_RES_Q_246___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_246___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_246___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_247 (0x005E43DC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_247___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_247___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_247__RX_DCOC_RANGE_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_247__RX_DCOC_RES_I_247___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_247__RX_DCOC_RES_Q_247___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_247__RX_DCOC_RANGE_247___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_247__RX_DCOC_RANGE_247___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_247__RX_DCOC_RES_I_247___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_247__RX_DCOC_RES_I_247___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_247__RX_DCOC_RES_Q_247___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_247__RX_DCOC_RES_Q_247___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_247___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_247___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_248 (0x005E43E0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_248___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_248___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_248__RX_DCOC_RANGE_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_248__RX_DCOC_RES_I_248___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_248__RX_DCOC_RES_Q_248___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_248__RX_DCOC_RANGE_248___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_248__RX_DCOC_RANGE_248___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_248__RX_DCOC_RES_I_248___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_248__RX_DCOC_RES_I_248___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_248__RX_DCOC_RES_Q_248___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_248__RX_DCOC_RES_Q_248___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_248___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_248___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_249 (0x005E43E4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_249___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_249___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_249__RX_DCOC_RANGE_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_249__RX_DCOC_RES_I_249___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_249__RX_DCOC_RES_Q_249___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_249__RX_DCOC_RANGE_249___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_249__RX_DCOC_RANGE_249___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_249__RX_DCOC_RES_I_249___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_249__RX_DCOC_RES_I_249___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_249__RX_DCOC_RES_Q_249___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_249__RX_DCOC_RES_Q_249___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_249___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_249___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_250 (0x005E43E8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_250___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_250___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_250__RX_DCOC_RANGE_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_250__RX_DCOC_RES_I_250___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_250__RX_DCOC_RES_Q_250___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_250__RX_DCOC_RANGE_250___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_250__RX_DCOC_RANGE_250___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_250__RX_DCOC_RES_I_250___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_250__RX_DCOC_RES_I_250___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_250__RX_DCOC_RES_Q_250___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_250__RX_DCOC_RES_Q_250___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_250___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_250___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_251 (0x005E43EC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_251___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_251___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_251__RX_DCOC_RANGE_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_251__RX_DCOC_RES_I_251___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_251__RX_DCOC_RES_Q_251___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_251__RX_DCOC_RANGE_251___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_251__RX_DCOC_RANGE_251___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_251__RX_DCOC_RES_I_251___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_251__RX_DCOC_RES_I_251___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_251__RX_DCOC_RES_Q_251___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_251__RX_DCOC_RES_Q_251___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_251___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_251___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_252 (0x005E43F0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_252___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_252___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_252__RX_DCOC_RANGE_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_252__RX_DCOC_RES_I_252___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_252__RX_DCOC_RES_Q_252___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_252__RX_DCOC_RANGE_252___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_252__RX_DCOC_RANGE_252___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_252__RX_DCOC_RES_I_252___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_252__RX_DCOC_RES_I_252___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_252__RX_DCOC_RES_Q_252___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_252__RX_DCOC_RES_Q_252___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_252___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_252___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_253 (0x005E43F4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_253___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_253___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_253__RX_DCOC_RANGE_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_253__RX_DCOC_RES_I_253___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_253__RX_DCOC_RES_Q_253___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_253__RX_DCOC_RANGE_253___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_253__RX_DCOC_RANGE_253___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_253__RX_DCOC_RES_I_253___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_253__RX_DCOC_RES_I_253___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_253__RX_DCOC_RES_Q_253___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_253__RX_DCOC_RES_Q_253___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_253___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_253___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_254 (0x005E43F8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_254___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_254___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_254__RX_DCOC_RANGE_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_254__RX_DCOC_RES_I_254___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_254__RX_DCOC_RES_Q_254___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_254__RX_DCOC_RANGE_254___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_254__RX_DCOC_RANGE_254___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_254__RX_DCOC_RES_I_254___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_254__RX_DCOC_RES_I_254___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_254__RX_DCOC_RES_Q_254___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_254__RX_DCOC_RES_Q_254___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_254___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_254___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_255 (0x005E43FC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_255___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_255___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_255__RX_DCOC_RANGE_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_255__RX_DCOC_RES_I_255___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_255__RX_DCOC_RES_Q_255___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_255__RX_DCOC_RANGE_255___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_255__RX_DCOC_RANGE_255___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_255__RX_DCOC_RES_I_255___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_255__RX_DCOC_RES_I_255___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_255__RX_DCOC_RES_Q_255___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_255__RX_DCOC_RES_Q_255___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_255___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_255___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_256 (0x005E4400) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_256___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_256___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_256__RX_DCOC_RANGE_256___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_256__RX_DCOC_RES_I_256___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_256__RX_DCOC_RES_Q_256___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_256__RX_DCOC_RANGE_256___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_256__RX_DCOC_RANGE_256___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_256__RX_DCOC_RES_I_256___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_256__RX_DCOC_RES_I_256___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_256__RX_DCOC_RES_Q_256___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_256__RX_DCOC_RES_Q_256___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_256___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_256___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_257 (0x005E4404) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_257___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_257___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_257__RX_DCOC_RANGE_257___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_257__RX_DCOC_RES_I_257___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_257__RX_DCOC_RES_Q_257___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_257__RX_DCOC_RANGE_257___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_257__RX_DCOC_RANGE_257___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_257__RX_DCOC_RES_I_257___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_257__RX_DCOC_RES_I_257___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_257__RX_DCOC_RES_Q_257___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_257__RX_DCOC_RES_Q_257___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_257___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_257___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_258 (0x005E4408) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_258___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_258___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_258__RX_DCOC_RANGE_258___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_258__RX_DCOC_RES_I_258___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_258__RX_DCOC_RES_Q_258___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_258__RX_DCOC_RANGE_258___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_258__RX_DCOC_RANGE_258___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_258__RX_DCOC_RES_I_258___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_258__RX_DCOC_RES_I_258___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_258__RX_DCOC_RES_Q_258___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_258__RX_DCOC_RES_Q_258___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_258___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_258___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_259 (0x005E440C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_259___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_259___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_259__RX_DCOC_RANGE_259___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_259__RX_DCOC_RES_I_259___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_259__RX_DCOC_RES_Q_259___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_259__RX_DCOC_RANGE_259___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_259__RX_DCOC_RANGE_259___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_259__RX_DCOC_RES_I_259___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_259__RX_DCOC_RES_I_259___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_259__RX_DCOC_RES_Q_259___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_259__RX_DCOC_RES_Q_259___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_259___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_259___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_260 (0x005E4410) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_260___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_260___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_260__RX_DCOC_RANGE_260___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_260__RX_DCOC_RES_I_260___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_260__RX_DCOC_RES_Q_260___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_260__RX_DCOC_RANGE_260___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_260__RX_DCOC_RANGE_260___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_260__RX_DCOC_RES_I_260___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_260__RX_DCOC_RES_I_260___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_260__RX_DCOC_RES_Q_260___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_260__RX_DCOC_RES_Q_260___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_260___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_260___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_261 (0x005E4414) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_261___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_261___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_261__RX_DCOC_RANGE_261___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_261__RX_DCOC_RES_I_261___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_261__RX_DCOC_RES_Q_261___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_261__RX_DCOC_RANGE_261___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_261__RX_DCOC_RANGE_261___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_261__RX_DCOC_RES_I_261___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_261__RX_DCOC_RES_I_261___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_261__RX_DCOC_RES_Q_261___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_261__RX_DCOC_RES_Q_261___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_261___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_261___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_262 (0x005E4418) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_262___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_262___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_262__RX_DCOC_RANGE_262___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_262__RX_DCOC_RES_I_262___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_262__RX_DCOC_RES_Q_262___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_262__RX_DCOC_RANGE_262___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_262__RX_DCOC_RANGE_262___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_262__RX_DCOC_RES_I_262___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_262__RX_DCOC_RES_I_262___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_262__RX_DCOC_RES_Q_262___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_262__RX_DCOC_RES_Q_262___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_262___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_262___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_263 (0x005E441C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_263___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_263___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_263__RX_DCOC_RANGE_263___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_263__RX_DCOC_RES_I_263___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_263__RX_DCOC_RES_Q_263___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_263__RX_DCOC_RANGE_263___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_263__RX_DCOC_RANGE_263___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_263__RX_DCOC_RES_I_263___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_263__RX_DCOC_RES_I_263___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_263__RX_DCOC_RES_Q_263___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_263__RX_DCOC_RES_Q_263___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_263___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_263___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_264 (0x005E4420) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_264___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_264___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_264__RX_DCOC_RANGE_264___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_264__RX_DCOC_RES_I_264___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_264__RX_DCOC_RES_Q_264___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_264__RX_DCOC_RANGE_264___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_264__RX_DCOC_RANGE_264___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_264__RX_DCOC_RES_I_264___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_264__RX_DCOC_RES_I_264___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_264__RX_DCOC_RES_Q_264___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_264__RX_DCOC_RES_Q_264___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_264___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_264___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_265 (0x005E4424) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_265___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_265___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_265__RX_DCOC_RANGE_265___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_265__RX_DCOC_RES_I_265___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_265__RX_DCOC_RES_Q_265___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_265__RX_DCOC_RANGE_265___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_265__RX_DCOC_RANGE_265___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_265__RX_DCOC_RES_I_265___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_265__RX_DCOC_RES_I_265___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_265__RX_DCOC_RES_Q_265___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_265__RX_DCOC_RES_Q_265___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_265___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_265___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_266 (0x005E4428) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_266___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_266___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_266__RX_DCOC_RANGE_266___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_266__RX_DCOC_RES_I_266___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_266__RX_DCOC_RES_Q_266___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_266__RX_DCOC_RANGE_266___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_266__RX_DCOC_RANGE_266___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_266__RX_DCOC_RES_I_266___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_266__RX_DCOC_RES_I_266___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_266__RX_DCOC_RES_Q_266___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_266__RX_DCOC_RES_Q_266___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_266___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_266___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_267 (0x005E442C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_267___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_267___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_267__RX_DCOC_RANGE_267___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_267__RX_DCOC_RES_I_267___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_267__RX_DCOC_RES_Q_267___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_267__RX_DCOC_RANGE_267___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_267__RX_DCOC_RANGE_267___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_267__RX_DCOC_RES_I_267___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_267__RX_DCOC_RES_I_267___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_267__RX_DCOC_RES_Q_267___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_267__RX_DCOC_RES_Q_267___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_267___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_267___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_268 (0x005E4430) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_268___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_268___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_268__RX_DCOC_RANGE_268___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_268__RX_DCOC_RES_I_268___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_268__RX_DCOC_RES_Q_268___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_268__RX_DCOC_RANGE_268___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_268__RX_DCOC_RANGE_268___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_268__RX_DCOC_RES_I_268___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_268__RX_DCOC_RES_I_268___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_268__RX_DCOC_RES_Q_268___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_268__RX_DCOC_RES_Q_268___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_268___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_268___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_269 (0x005E4434) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_269___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_269___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_269__RX_DCOC_RANGE_269___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_269__RX_DCOC_RES_I_269___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_269__RX_DCOC_RES_Q_269___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_269__RX_DCOC_RANGE_269___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_269__RX_DCOC_RANGE_269___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_269__RX_DCOC_RES_I_269___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_269__RX_DCOC_RES_I_269___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_269__RX_DCOC_RES_Q_269___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_269__RX_DCOC_RES_Q_269___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_269___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_269___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_270 (0x005E4438) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_270___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_270___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_270__RX_DCOC_RANGE_270___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_270__RX_DCOC_RES_I_270___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_270__RX_DCOC_RES_Q_270___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_270__RX_DCOC_RANGE_270___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_270__RX_DCOC_RANGE_270___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_270__RX_DCOC_RES_I_270___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_270__RX_DCOC_RES_I_270___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_270__RX_DCOC_RES_Q_270___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_270__RX_DCOC_RES_Q_270___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_270___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_270___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_271 (0x005E443C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_271___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_271___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_271__RX_DCOC_RANGE_271___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_271__RX_DCOC_RES_I_271___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_271__RX_DCOC_RES_Q_271___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_271__RX_DCOC_RANGE_271___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_271__RX_DCOC_RANGE_271___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_271__RX_DCOC_RES_I_271___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_271__RX_DCOC_RES_I_271___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_271__RX_DCOC_RES_Q_271___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_271__RX_DCOC_RES_Q_271___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_271___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_271___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_272 (0x005E4440) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_272___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_272___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_272__RX_DCOC_RANGE_272___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_272__RX_DCOC_RES_I_272___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_272__RX_DCOC_RES_Q_272___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_272__RX_DCOC_RANGE_272___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_272__RX_DCOC_RANGE_272___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_272__RX_DCOC_RES_I_272___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_272__RX_DCOC_RES_I_272___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_272__RX_DCOC_RES_Q_272___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_272__RX_DCOC_RES_Q_272___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_272___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_272___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_273 (0x005E4444) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_273___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_273___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_273__RX_DCOC_RANGE_273___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_273__RX_DCOC_RES_I_273___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_273__RX_DCOC_RES_Q_273___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_273__RX_DCOC_RANGE_273___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_273__RX_DCOC_RANGE_273___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_273__RX_DCOC_RES_I_273___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_273__RX_DCOC_RES_I_273___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_273__RX_DCOC_RES_Q_273___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_273__RX_DCOC_RES_Q_273___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_273___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_273___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_274 (0x005E4448) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_274___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_274___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_274__RX_DCOC_RANGE_274___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_274__RX_DCOC_RES_I_274___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_274__RX_DCOC_RES_Q_274___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_274__RX_DCOC_RANGE_274___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_274__RX_DCOC_RANGE_274___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_274__RX_DCOC_RES_I_274___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_274__RX_DCOC_RES_I_274___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_274__RX_DCOC_RES_Q_274___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_274__RX_DCOC_RES_Q_274___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_274___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_274___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_275 (0x005E444C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_275___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_275___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_275__RX_DCOC_RANGE_275___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_275__RX_DCOC_RES_I_275___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_275__RX_DCOC_RES_Q_275___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_275__RX_DCOC_RANGE_275___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_275__RX_DCOC_RANGE_275___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_275__RX_DCOC_RES_I_275___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_275__RX_DCOC_RES_I_275___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_275__RX_DCOC_RES_Q_275___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_275__RX_DCOC_RES_Q_275___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_275___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_275___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_276 (0x005E4450) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_276___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_276___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_276__RX_DCOC_RANGE_276___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_276__RX_DCOC_RES_I_276___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_276__RX_DCOC_RES_Q_276___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_276__RX_DCOC_RANGE_276___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_276__RX_DCOC_RANGE_276___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_276__RX_DCOC_RES_I_276___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_276__RX_DCOC_RES_I_276___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_276__RX_DCOC_RES_Q_276___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_276__RX_DCOC_RES_Q_276___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_276___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_276___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_277 (0x005E4454) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_277___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_277___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_277__RX_DCOC_RANGE_277___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_277__RX_DCOC_RES_I_277___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_277__RX_DCOC_RES_Q_277___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_277__RX_DCOC_RANGE_277___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_277__RX_DCOC_RANGE_277___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_277__RX_DCOC_RES_I_277___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_277__RX_DCOC_RES_I_277___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_277__RX_DCOC_RES_Q_277___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_277__RX_DCOC_RES_Q_277___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_277___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_277___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_278 (0x005E4458) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_278___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_278___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_278__RX_DCOC_RANGE_278___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_278__RX_DCOC_RES_I_278___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_278__RX_DCOC_RES_Q_278___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_278__RX_DCOC_RANGE_278___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_278__RX_DCOC_RANGE_278___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_278__RX_DCOC_RES_I_278___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_278__RX_DCOC_RES_I_278___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_278__RX_DCOC_RES_Q_278___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_278__RX_DCOC_RES_Q_278___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_278___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_278___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_279 (0x005E445C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_279___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_279___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_279__RX_DCOC_RANGE_279___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_279__RX_DCOC_RES_I_279___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_279__RX_DCOC_RES_Q_279___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_279__RX_DCOC_RANGE_279___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_279__RX_DCOC_RANGE_279___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_279__RX_DCOC_RES_I_279___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_279__RX_DCOC_RES_I_279___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_279__RX_DCOC_RES_Q_279___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_279__RX_DCOC_RES_Q_279___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_279___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_279___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_280 (0x005E4460) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_280___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_280___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_280__RX_DCOC_RANGE_280___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_280__RX_DCOC_RES_I_280___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_280__RX_DCOC_RES_Q_280___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_280__RX_DCOC_RANGE_280___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_280__RX_DCOC_RANGE_280___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_280__RX_DCOC_RES_I_280___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_280__RX_DCOC_RES_I_280___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_280__RX_DCOC_RES_Q_280___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_280__RX_DCOC_RES_Q_280___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_280___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_280___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_281 (0x005E4464) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_281___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_281___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_281__RX_DCOC_RANGE_281___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_281__RX_DCOC_RES_I_281___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_281__RX_DCOC_RES_Q_281___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_281__RX_DCOC_RANGE_281___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_281__RX_DCOC_RANGE_281___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_281__RX_DCOC_RES_I_281___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_281__RX_DCOC_RES_I_281___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_281__RX_DCOC_RES_Q_281___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_281__RX_DCOC_RES_Q_281___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_281___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_281___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_282 (0x005E4468) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_282___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_282___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_282__RX_DCOC_RANGE_282___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_282__RX_DCOC_RES_I_282___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_282__RX_DCOC_RES_Q_282___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_282__RX_DCOC_RANGE_282___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_282__RX_DCOC_RANGE_282___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_282__RX_DCOC_RES_I_282___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_282__RX_DCOC_RES_I_282___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_282__RX_DCOC_RES_Q_282___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_282__RX_DCOC_RES_Q_282___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_282___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_282___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_283 (0x005E446C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_283___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_283___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_283__RX_DCOC_RANGE_283___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_283__RX_DCOC_RES_I_283___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_283__RX_DCOC_RES_Q_283___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_283__RX_DCOC_RANGE_283___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_283__RX_DCOC_RANGE_283___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_283__RX_DCOC_RES_I_283___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_283__RX_DCOC_RES_I_283___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_283__RX_DCOC_RES_Q_283___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_283__RX_DCOC_RES_Q_283___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_283___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_283___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_284 (0x005E4470) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_284___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_284___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_284__RX_DCOC_RANGE_284___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_284__RX_DCOC_RES_I_284___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_284__RX_DCOC_RES_Q_284___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_284__RX_DCOC_RANGE_284___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_284__RX_DCOC_RANGE_284___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_284__RX_DCOC_RES_I_284___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_284__RX_DCOC_RES_I_284___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_284__RX_DCOC_RES_Q_284___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_284__RX_DCOC_RES_Q_284___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_284___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_284___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_285 (0x005E4474) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_285___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_285___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_285__RX_DCOC_RANGE_285___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_285__RX_DCOC_RES_I_285___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_285__RX_DCOC_RES_Q_285___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_285__RX_DCOC_RANGE_285___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_285__RX_DCOC_RANGE_285___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_285__RX_DCOC_RES_I_285___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_285__RX_DCOC_RES_I_285___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_285__RX_DCOC_RES_Q_285___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_285__RX_DCOC_RES_Q_285___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_285___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_285___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_286 (0x005E4478) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_286___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_286___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_286__RX_DCOC_RANGE_286___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_286__RX_DCOC_RES_I_286___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_286__RX_DCOC_RES_Q_286___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_286__RX_DCOC_RANGE_286___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_286__RX_DCOC_RANGE_286___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_286__RX_DCOC_RES_I_286___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_286__RX_DCOC_RES_I_286___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_286__RX_DCOC_RES_Q_286___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_286__RX_DCOC_RES_Q_286___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_286___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_286___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_287 (0x005E447C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_287___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_287___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_287__RX_DCOC_RANGE_287___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_287__RX_DCOC_RES_I_287___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_287__RX_DCOC_RES_Q_287___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_287__RX_DCOC_RANGE_287___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_287__RX_DCOC_RANGE_287___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_287__RX_DCOC_RES_I_287___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_287__RX_DCOC_RES_I_287___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_287__RX_DCOC_RES_Q_287___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_287__RX_DCOC_RES_Q_287___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_287___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_287___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_288 (0x005E4480) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_288___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_288___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_288__RX_DCOC_RANGE_288___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_288__RX_DCOC_RES_I_288___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_288__RX_DCOC_RES_Q_288___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_288__RX_DCOC_RANGE_288___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_288__RX_DCOC_RANGE_288___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_288__RX_DCOC_RES_I_288___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_288__RX_DCOC_RES_I_288___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_288__RX_DCOC_RES_Q_288___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_288__RX_DCOC_RES_Q_288___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_288___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_288___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_289 (0x005E4484) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_289___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_289___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_289__RX_DCOC_RANGE_289___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_289__RX_DCOC_RES_I_289___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_289__RX_DCOC_RES_Q_289___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_289__RX_DCOC_RANGE_289___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_289__RX_DCOC_RANGE_289___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_289__RX_DCOC_RES_I_289___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_289__RX_DCOC_RES_I_289___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_289__RX_DCOC_RES_Q_289___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_289__RX_DCOC_RES_Q_289___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_289___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_289___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_290 (0x005E4488) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_290___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_290___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_290__RX_DCOC_RANGE_290___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_290__RX_DCOC_RES_I_290___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_290__RX_DCOC_RES_Q_290___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_290__RX_DCOC_RANGE_290___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_290__RX_DCOC_RANGE_290___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_290__RX_DCOC_RES_I_290___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_290__RX_DCOC_RES_I_290___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_290__RX_DCOC_RES_Q_290___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_290__RX_DCOC_RES_Q_290___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_290___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_290___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_291 (0x005E448C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_291___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_291___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_291__RX_DCOC_RANGE_291___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_291__RX_DCOC_RES_I_291___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_291__RX_DCOC_RES_Q_291___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_291__RX_DCOC_RANGE_291___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_291__RX_DCOC_RANGE_291___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_291__RX_DCOC_RES_I_291___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_291__RX_DCOC_RES_I_291___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_291__RX_DCOC_RES_Q_291___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_291__RX_DCOC_RES_Q_291___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_291___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_291___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_292 (0x005E4490) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_292___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_292___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_292__RX_DCOC_RANGE_292___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_292__RX_DCOC_RES_I_292___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_292__RX_DCOC_RES_Q_292___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_292__RX_DCOC_RANGE_292___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_292__RX_DCOC_RANGE_292___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_292__RX_DCOC_RES_I_292___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_292__RX_DCOC_RES_I_292___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_292__RX_DCOC_RES_Q_292___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_292__RX_DCOC_RES_Q_292___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_292___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_292___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_293 (0x005E4494) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_293___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_293___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_293__RX_DCOC_RANGE_293___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_293__RX_DCOC_RES_I_293___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_293__RX_DCOC_RES_Q_293___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_293__RX_DCOC_RANGE_293___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_293__RX_DCOC_RANGE_293___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_293__RX_DCOC_RES_I_293___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_293__RX_DCOC_RES_I_293___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_293__RX_DCOC_RES_Q_293___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_293__RX_DCOC_RES_Q_293___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_293___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_293___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_294 (0x005E4498) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_294___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_294___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_294__RX_DCOC_RANGE_294___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_294__RX_DCOC_RES_I_294___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_294__RX_DCOC_RES_Q_294___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_294__RX_DCOC_RANGE_294___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_294__RX_DCOC_RANGE_294___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_294__RX_DCOC_RES_I_294___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_294__RX_DCOC_RES_I_294___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_294__RX_DCOC_RES_Q_294___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_294__RX_DCOC_RES_Q_294___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_294___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_294___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_295 (0x005E449C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_295___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_295___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_295__RX_DCOC_RANGE_295___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_295__RX_DCOC_RES_I_295___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_295__RX_DCOC_RES_Q_295___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_295__RX_DCOC_RANGE_295___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_295__RX_DCOC_RANGE_295___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_295__RX_DCOC_RES_I_295___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_295__RX_DCOC_RES_I_295___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_295__RX_DCOC_RES_Q_295___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_295__RX_DCOC_RES_Q_295___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_295___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_295___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_296 (0x005E44A0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_296___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_296___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_296__RX_DCOC_RANGE_296___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_296__RX_DCOC_RES_I_296___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_296__RX_DCOC_RES_Q_296___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_296__RX_DCOC_RANGE_296___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_296__RX_DCOC_RANGE_296___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_296__RX_DCOC_RES_I_296___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_296__RX_DCOC_RES_I_296___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_296__RX_DCOC_RES_Q_296___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_296__RX_DCOC_RES_Q_296___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_296___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_296___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_297 (0x005E44A4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_297___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_297___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_297__RX_DCOC_RANGE_297___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_297__RX_DCOC_RES_I_297___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_297__RX_DCOC_RES_Q_297___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_297__RX_DCOC_RANGE_297___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_297__RX_DCOC_RANGE_297___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_297__RX_DCOC_RES_I_297___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_297__RX_DCOC_RES_I_297___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_297__RX_DCOC_RES_Q_297___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_297__RX_DCOC_RES_Q_297___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_297___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_297___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_298 (0x005E44A8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_298___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_298___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_298__RX_DCOC_RANGE_298___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_298__RX_DCOC_RES_I_298___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_298__RX_DCOC_RES_Q_298___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_298__RX_DCOC_RANGE_298___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_298__RX_DCOC_RANGE_298___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_298__RX_DCOC_RES_I_298___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_298__RX_DCOC_RES_I_298___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_298__RX_DCOC_RES_Q_298___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_298__RX_DCOC_RES_Q_298___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_298___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_298___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_299 (0x005E44AC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_299___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_299___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_299__RX_DCOC_RANGE_299___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_299__RX_DCOC_RES_I_299___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_299__RX_DCOC_RES_Q_299___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_299__RX_DCOC_RANGE_299___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_299__RX_DCOC_RANGE_299___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_299__RX_DCOC_RES_I_299___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_299__RX_DCOC_RES_I_299___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_299__RX_DCOC_RES_Q_299___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_299__RX_DCOC_RES_Q_299___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_299___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_299___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_300 (0x005E44B0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_300___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_300___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_300__RX_DCOC_RANGE_300___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_300__RX_DCOC_RES_I_300___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_300__RX_DCOC_RES_Q_300___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_300__RX_DCOC_RANGE_300___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_300__RX_DCOC_RANGE_300___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_300__RX_DCOC_RES_I_300___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_300__RX_DCOC_RES_I_300___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_300__RX_DCOC_RES_Q_300___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_300__RX_DCOC_RES_Q_300___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_300___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_300___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_301 (0x005E44B4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_301___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_301___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_301__RX_DCOC_RANGE_301___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_301__RX_DCOC_RES_I_301___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_301__RX_DCOC_RES_Q_301___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_301__RX_DCOC_RANGE_301___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_301__RX_DCOC_RANGE_301___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_301__RX_DCOC_RES_I_301___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_301__RX_DCOC_RES_I_301___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_301__RX_DCOC_RES_Q_301___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_301__RX_DCOC_RES_Q_301___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_301___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_301___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_302 (0x005E44B8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_302___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_302___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_302__RX_DCOC_RANGE_302___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_302__RX_DCOC_RES_I_302___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_302__RX_DCOC_RES_Q_302___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_302__RX_DCOC_RANGE_302___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_302__RX_DCOC_RANGE_302___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_302__RX_DCOC_RES_I_302___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_302__RX_DCOC_RES_I_302___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_302__RX_DCOC_RES_Q_302___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_302__RX_DCOC_RES_Q_302___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_302___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_302___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_303 (0x005E44BC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_303___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_303___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_303__RX_DCOC_RANGE_303___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_303__RX_DCOC_RES_I_303___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_303__RX_DCOC_RES_Q_303___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_303__RX_DCOC_RANGE_303___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_303__RX_DCOC_RANGE_303___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_303__RX_DCOC_RES_I_303___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_303__RX_DCOC_RES_I_303___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_303__RX_DCOC_RES_Q_303___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_303__RX_DCOC_RES_Q_303___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_303___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_303___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_304 (0x005E44C0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_304___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_304___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_304__RX_DCOC_RANGE_304___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_304__RX_DCOC_RES_I_304___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_304__RX_DCOC_RES_Q_304___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_304__RX_DCOC_RANGE_304___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_304__RX_DCOC_RANGE_304___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_304__RX_DCOC_RES_I_304___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_304__RX_DCOC_RES_I_304___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_304__RX_DCOC_RES_Q_304___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_304__RX_DCOC_RES_Q_304___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_304___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_304___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_305 (0x005E44C4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_305___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_305___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_305__RX_DCOC_RANGE_305___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_305__RX_DCOC_RES_I_305___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_305__RX_DCOC_RES_Q_305___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_305__RX_DCOC_RANGE_305___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_305__RX_DCOC_RANGE_305___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_305__RX_DCOC_RES_I_305___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_305__RX_DCOC_RES_I_305___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_305__RX_DCOC_RES_Q_305___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_305__RX_DCOC_RES_Q_305___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_305___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_305___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_306 (0x005E44C8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_306___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_306___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_306__RX_DCOC_RANGE_306___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_306__RX_DCOC_RES_I_306___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_306__RX_DCOC_RES_Q_306___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_306__RX_DCOC_RANGE_306___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_306__RX_DCOC_RANGE_306___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_306__RX_DCOC_RES_I_306___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_306__RX_DCOC_RES_I_306___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_306__RX_DCOC_RES_Q_306___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_306__RX_DCOC_RES_Q_306___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_306___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_306___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_307 (0x005E44CC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_307___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_307___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_307__RX_DCOC_RANGE_307___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_307__RX_DCOC_RES_I_307___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_307__RX_DCOC_RES_Q_307___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_307__RX_DCOC_RANGE_307___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_307__RX_DCOC_RANGE_307___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_307__RX_DCOC_RES_I_307___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_307__RX_DCOC_RES_I_307___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_307__RX_DCOC_RES_Q_307___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_307__RX_DCOC_RES_Q_307___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_307___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_307___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_308 (0x005E44D0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_308___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_308___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_308__RX_DCOC_RANGE_308___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_308__RX_DCOC_RES_I_308___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_308__RX_DCOC_RES_Q_308___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_308__RX_DCOC_RANGE_308___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_308__RX_DCOC_RANGE_308___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_308__RX_DCOC_RES_I_308___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_308__RX_DCOC_RES_I_308___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_308__RX_DCOC_RES_Q_308___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_308__RX_DCOC_RES_Q_308___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_308___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_308___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_309 (0x005E44D4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_309___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_309___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_309__RX_DCOC_RANGE_309___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_309__RX_DCOC_RES_I_309___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_309__RX_DCOC_RES_Q_309___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_309__RX_DCOC_RANGE_309___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_309__RX_DCOC_RANGE_309___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_309__RX_DCOC_RES_I_309___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_309__RX_DCOC_RES_I_309___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_309__RX_DCOC_RES_Q_309___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_309__RX_DCOC_RES_Q_309___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_309___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_309___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_310 (0x005E44D8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_310___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_310___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_310__RX_DCOC_RANGE_310___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_310__RX_DCOC_RES_I_310___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_310__RX_DCOC_RES_Q_310___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_310__RX_DCOC_RANGE_310___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_310__RX_DCOC_RANGE_310___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_310__RX_DCOC_RES_I_310___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_310__RX_DCOC_RES_I_310___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_310__RX_DCOC_RES_Q_310___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_310__RX_DCOC_RES_Q_310___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_310___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_310___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_311 (0x005E44DC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_311___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_311___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_311__RX_DCOC_RANGE_311___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_311__RX_DCOC_RES_I_311___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_311__RX_DCOC_RES_Q_311___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_311__RX_DCOC_RANGE_311___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_311__RX_DCOC_RANGE_311___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_311__RX_DCOC_RES_I_311___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_311__RX_DCOC_RES_I_311___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_311__RX_DCOC_RES_Q_311___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_311__RX_DCOC_RES_Q_311___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_311___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_311___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_312 (0x005E44E0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_312___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_312___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_312__RX_DCOC_RANGE_312___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_312__RX_DCOC_RES_I_312___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_312__RX_DCOC_RES_Q_312___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_312__RX_DCOC_RANGE_312___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_312__RX_DCOC_RANGE_312___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_312__RX_DCOC_RES_I_312___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_312__RX_DCOC_RES_I_312___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_312__RX_DCOC_RES_Q_312___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_312__RX_DCOC_RES_Q_312___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_312___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_312___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_313 (0x005E44E4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_313___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_313___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_313__RX_DCOC_RANGE_313___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_313__RX_DCOC_RES_I_313___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_313__RX_DCOC_RES_Q_313___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_313__RX_DCOC_RANGE_313___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_313__RX_DCOC_RANGE_313___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_313__RX_DCOC_RES_I_313___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_313__RX_DCOC_RES_I_313___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_313__RX_DCOC_RES_Q_313___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_313__RX_DCOC_RES_Q_313___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_313___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_313___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_314 (0x005E44E8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_314___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_314___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_314__RX_DCOC_RANGE_314___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_314__RX_DCOC_RES_I_314___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_314__RX_DCOC_RES_Q_314___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_314__RX_DCOC_RANGE_314___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_314__RX_DCOC_RANGE_314___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_314__RX_DCOC_RES_I_314___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_314__RX_DCOC_RES_I_314___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_314__RX_DCOC_RES_Q_314___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_314__RX_DCOC_RES_Q_314___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_314___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_314___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_315 (0x005E44EC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_315___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_315___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_315__RX_DCOC_RANGE_315___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_315__RX_DCOC_RES_I_315___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_315__RX_DCOC_RES_Q_315___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_315__RX_DCOC_RANGE_315___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_315__RX_DCOC_RANGE_315___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_315__RX_DCOC_RES_I_315___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_315__RX_DCOC_RES_I_315___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_315__RX_DCOC_RES_Q_315___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_315__RX_DCOC_RES_Q_315___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_315___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_315___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_316 (0x005E44F0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_316___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_316___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_316__RX_DCOC_RANGE_316___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_316__RX_DCOC_RES_I_316___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_316__RX_DCOC_RES_Q_316___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_316__RX_DCOC_RANGE_316___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_316__RX_DCOC_RANGE_316___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_316__RX_DCOC_RES_I_316___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_316__RX_DCOC_RES_I_316___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_316__RX_DCOC_RES_Q_316___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_316__RX_DCOC_RES_Q_316___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_316___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_316___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_317 (0x005E44F4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_317___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_317___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_317__RX_DCOC_RANGE_317___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_317__RX_DCOC_RES_I_317___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_317__RX_DCOC_RES_Q_317___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_317__RX_DCOC_RANGE_317___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_317__RX_DCOC_RANGE_317___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_317__RX_DCOC_RES_I_317___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_317__RX_DCOC_RES_I_317___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_317__RX_DCOC_RES_Q_317___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_317__RX_DCOC_RES_Q_317___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_317___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_317___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_318 (0x005E44F8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_318___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_318___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_318__RX_DCOC_RANGE_318___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_318__RX_DCOC_RES_I_318___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_318__RX_DCOC_RES_Q_318___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_318__RX_DCOC_RANGE_318___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_318__RX_DCOC_RANGE_318___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_318__RX_DCOC_RES_I_318___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_318__RX_DCOC_RES_I_318___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_318__RX_DCOC_RES_Q_318___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_318__RX_DCOC_RES_Q_318___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_318___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_318___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_319 (0x005E44FC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_319___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_319___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_319__RX_DCOC_RANGE_319___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_319__RX_DCOC_RES_I_319___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_319__RX_DCOC_RES_Q_319___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_319__RX_DCOC_RANGE_319___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_319__RX_DCOC_RANGE_319___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_319__RX_DCOC_RES_I_319___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_319__RX_DCOC_RES_I_319___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_319__RX_DCOC_RES_Q_319___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_319__RX_DCOC_RES_Q_319___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_319___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_319___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_320 (0x005E4500) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_320___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_320___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_320__RX_DCOC_RANGE_320___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_320__RX_DCOC_RES_I_320___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_320__RX_DCOC_RES_Q_320___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_320__RX_DCOC_RANGE_320___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_320__RX_DCOC_RANGE_320___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_320__RX_DCOC_RES_I_320___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_320__RX_DCOC_RES_I_320___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_320__RX_DCOC_RES_Q_320___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_320__RX_DCOC_RES_Q_320___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_320___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_320___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_321 (0x005E4504) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_321___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_321___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_321__RX_DCOC_RANGE_321___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_321__RX_DCOC_RES_I_321___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_321__RX_DCOC_RES_Q_321___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_321__RX_DCOC_RANGE_321___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_321__RX_DCOC_RANGE_321___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_321__RX_DCOC_RES_I_321___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_321__RX_DCOC_RES_I_321___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_321__RX_DCOC_RES_Q_321___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_321__RX_DCOC_RES_Q_321___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_321___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_321___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_322 (0x005E4508) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_322___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_322___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_322__RX_DCOC_RANGE_322___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_322__RX_DCOC_RES_I_322___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_322__RX_DCOC_RES_Q_322___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_322__RX_DCOC_RANGE_322___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_322__RX_DCOC_RANGE_322___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_322__RX_DCOC_RES_I_322___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_322__RX_DCOC_RES_I_322___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_322__RX_DCOC_RES_Q_322___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_322__RX_DCOC_RES_Q_322___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_322___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_322___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_323 (0x005E450C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_323___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_323___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_323__RX_DCOC_RANGE_323___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_323__RX_DCOC_RES_I_323___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_323__RX_DCOC_RES_Q_323___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_323__RX_DCOC_RANGE_323___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_323__RX_DCOC_RANGE_323___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_323__RX_DCOC_RES_I_323___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_323__RX_DCOC_RES_I_323___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_323__RX_DCOC_RES_Q_323___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_323__RX_DCOC_RES_Q_323___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_323___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_323___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_324 (0x005E4510) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_324___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_324___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_324__RX_DCOC_RANGE_324___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_324__RX_DCOC_RES_I_324___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_324__RX_DCOC_RES_Q_324___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_324__RX_DCOC_RANGE_324___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_324__RX_DCOC_RANGE_324___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_324__RX_DCOC_RES_I_324___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_324__RX_DCOC_RES_I_324___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_324__RX_DCOC_RES_Q_324___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_324__RX_DCOC_RES_Q_324___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_324___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_324___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_325 (0x005E4514) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_325___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_325___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_325__RX_DCOC_RANGE_325___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_325__RX_DCOC_RES_I_325___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_325__RX_DCOC_RES_Q_325___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_325__RX_DCOC_RANGE_325___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_325__RX_DCOC_RANGE_325___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_325__RX_DCOC_RES_I_325___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_325__RX_DCOC_RES_I_325___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_325__RX_DCOC_RES_Q_325___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_325__RX_DCOC_RES_Q_325___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_325___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_325___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_326 (0x005E4518) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_326___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_326___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_326__RX_DCOC_RANGE_326___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_326__RX_DCOC_RES_I_326___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_326__RX_DCOC_RES_Q_326___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_326__RX_DCOC_RANGE_326___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_326__RX_DCOC_RANGE_326___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_326__RX_DCOC_RES_I_326___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_326__RX_DCOC_RES_I_326___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_326__RX_DCOC_RES_Q_326___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_326__RX_DCOC_RES_Q_326___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_326___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_326___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_327 (0x005E451C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_327___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_327___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_327__RX_DCOC_RANGE_327___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_327__RX_DCOC_RES_I_327___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_327__RX_DCOC_RES_Q_327___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_327__RX_DCOC_RANGE_327___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_327__RX_DCOC_RANGE_327___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_327__RX_DCOC_RES_I_327___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_327__RX_DCOC_RES_I_327___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_327__RX_DCOC_RES_Q_327___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_327__RX_DCOC_RES_Q_327___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_327___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_327___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_328 (0x005E4520) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_328___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_328___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_328__RX_DCOC_RANGE_328___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_328__RX_DCOC_RES_I_328___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_328__RX_DCOC_RES_Q_328___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_328__RX_DCOC_RANGE_328___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_328__RX_DCOC_RANGE_328___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_328__RX_DCOC_RES_I_328___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_328__RX_DCOC_RES_I_328___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_328__RX_DCOC_RES_Q_328___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_328__RX_DCOC_RES_Q_328___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_328___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_328___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_329 (0x005E4524) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_329___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_329___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_329__RX_DCOC_RANGE_329___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_329__RX_DCOC_RES_I_329___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_329__RX_DCOC_RES_Q_329___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_329__RX_DCOC_RANGE_329___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_329__RX_DCOC_RANGE_329___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_329__RX_DCOC_RES_I_329___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_329__RX_DCOC_RES_I_329___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_329__RX_DCOC_RES_Q_329___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_329__RX_DCOC_RES_Q_329___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_329___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_329___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_330 (0x005E4528) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_330___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_330___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_330__RX_DCOC_RANGE_330___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_330__RX_DCOC_RES_I_330___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_330__RX_DCOC_RES_Q_330___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_330__RX_DCOC_RANGE_330___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_330__RX_DCOC_RANGE_330___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_330__RX_DCOC_RES_I_330___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_330__RX_DCOC_RES_I_330___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_330__RX_DCOC_RES_Q_330___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_330__RX_DCOC_RES_Q_330___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_330___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_330___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_331 (0x005E452C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_331___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_331___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_331__RX_DCOC_RANGE_331___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_331__RX_DCOC_RES_I_331___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_331__RX_DCOC_RES_Q_331___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_331__RX_DCOC_RANGE_331___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_331__RX_DCOC_RANGE_331___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_331__RX_DCOC_RES_I_331___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_331__RX_DCOC_RES_I_331___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_331__RX_DCOC_RES_Q_331___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_331__RX_DCOC_RES_Q_331___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_331___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_331___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_332 (0x005E4530) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_332___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_332___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_332__RX_DCOC_RANGE_332___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_332__RX_DCOC_RES_I_332___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_332__RX_DCOC_RES_Q_332___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_332__RX_DCOC_RANGE_332___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_332__RX_DCOC_RANGE_332___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_332__RX_DCOC_RES_I_332___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_332__RX_DCOC_RES_I_332___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_332__RX_DCOC_RES_Q_332___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_332__RX_DCOC_RES_Q_332___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_332___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_332___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_333 (0x005E4534) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_333___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_333___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_333__RX_DCOC_RANGE_333___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_333__RX_DCOC_RES_I_333___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_333__RX_DCOC_RES_Q_333___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_333__RX_DCOC_RANGE_333___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_333__RX_DCOC_RANGE_333___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_333__RX_DCOC_RES_I_333___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_333__RX_DCOC_RES_I_333___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_333__RX_DCOC_RES_Q_333___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_333__RX_DCOC_RES_Q_333___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_333___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_333___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_334 (0x005E4538) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_334___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_334___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_334__RX_DCOC_RANGE_334___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_334__RX_DCOC_RES_I_334___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_334__RX_DCOC_RES_Q_334___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_334__RX_DCOC_RANGE_334___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_334__RX_DCOC_RANGE_334___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_334__RX_DCOC_RES_I_334___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_334__RX_DCOC_RES_I_334___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_334__RX_DCOC_RES_Q_334___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_334__RX_DCOC_RES_Q_334___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_334___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_334___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_335 (0x005E453C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_335___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_335___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_335__RX_DCOC_RANGE_335___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_335__RX_DCOC_RES_I_335___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_335__RX_DCOC_RES_Q_335___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_335__RX_DCOC_RANGE_335___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_335__RX_DCOC_RANGE_335___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_335__RX_DCOC_RES_I_335___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_335__RX_DCOC_RES_I_335___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_335__RX_DCOC_RES_Q_335___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_335__RX_DCOC_RES_Q_335___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_335___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_335___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_336 (0x005E4540) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_336___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_336___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_336__RX_DCOC_RANGE_336___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_336__RX_DCOC_RES_I_336___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_336__RX_DCOC_RES_Q_336___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_336__RX_DCOC_RANGE_336___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_336__RX_DCOC_RANGE_336___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_336__RX_DCOC_RES_I_336___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_336__RX_DCOC_RES_I_336___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_336__RX_DCOC_RES_Q_336___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_336__RX_DCOC_RES_Q_336___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_336___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_336___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_337 (0x005E4544) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_337___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_337___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_337__RX_DCOC_RANGE_337___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_337__RX_DCOC_RES_I_337___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_337__RX_DCOC_RES_Q_337___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_337__RX_DCOC_RANGE_337___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_337__RX_DCOC_RANGE_337___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_337__RX_DCOC_RES_I_337___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_337__RX_DCOC_RES_I_337___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_337__RX_DCOC_RES_Q_337___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_337__RX_DCOC_RES_Q_337___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_337___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_337___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_338 (0x005E4548) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_338___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_338___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_338__RX_DCOC_RANGE_338___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_338__RX_DCOC_RES_I_338___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_338__RX_DCOC_RES_Q_338___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_338__RX_DCOC_RANGE_338___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_338__RX_DCOC_RANGE_338___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_338__RX_DCOC_RES_I_338___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_338__RX_DCOC_RES_I_338___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_338__RX_DCOC_RES_Q_338___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_338__RX_DCOC_RES_Q_338___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_338___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_338___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_339 (0x005E454C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_339___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_339___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_339__RX_DCOC_RANGE_339___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_339__RX_DCOC_RES_I_339___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_339__RX_DCOC_RES_Q_339___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_339__RX_DCOC_RANGE_339___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_339__RX_DCOC_RANGE_339___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_339__RX_DCOC_RES_I_339___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_339__RX_DCOC_RES_I_339___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_339__RX_DCOC_RES_Q_339___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_339__RX_DCOC_RES_Q_339___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_339___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_339___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_340 (0x005E4550) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_340___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_340___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_340__RX_DCOC_RANGE_340___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_340__RX_DCOC_RES_I_340___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_340__RX_DCOC_RES_Q_340___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_340__RX_DCOC_RANGE_340___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_340__RX_DCOC_RANGE_340___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_340__RX_DCOC_RES_I_340___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_340__RX_DCOC_RES_I_340___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_340__RX_DCOC_RES_Q_340___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_340__RX_DCOC_RES_Q_340___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_340___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_340___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_341 (0x005E4554) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_341___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_341___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_341__RX_DCOC_RANGE_341___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_341__RX_DCOC_RES_I_341___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_341__RX_DCOC_RES_Q_341___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_341__RX_DCOC_RANGE_341___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_341__RX_DCOC_RANGE_341___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_341__RX_DCOC_RES_I_341___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_341__RX_DCOC_RES_I_341___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_341__RX_DCOC_RES_Q_341___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_341__RX_DCOC_RES_Q_341___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_341___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_341___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_342 (0x005E4558) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_342___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_342___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_342__RX_DCOC_RANGE_342___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_342__RX_DCOC_RES_I_342___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_342__RX_DCOC_RES_Q_342___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_342__RX_DCOC_RANGE_342___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_342__RX_DCOC_RANGE_342___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_342__RX_DCOC_RES_I_342___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_342__RX_DCOC_RES_I_342___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_342__RX_DCOC_RES_Q_342___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_342__RX_DCOC_RES_Q_342___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_342___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_342___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_343 (0x005E455C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_343___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_343___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_343__RX_DCOC_RANGE_343___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_343__RX_DCOC_RES_I_343___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_343__RX_DCOC_RES_Q_343___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_343__RX_DCOC_RANGE_343___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_343__RX_DCOC_RANGE_343___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_343__RX_DCOC_RES_I_343___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_343__RX_DCOC_RES_I_343___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_343__RX_DCOC_RES_Q_343___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_343__RX_DCOC_RES_Q_343___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_343___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_343___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_344 (0x005E4560) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_344___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_344___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_344__RX_DCOC_RANGE_344___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_344__RX_DCOC_RES_I_344___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_344__RX_DCOC_RES_Q_344___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_344__RX_DCOC_RANGE_344___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_344__RX_DCOC_RANGE_344___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_344__RX_DCOC_RES_I_344___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_344__RX_DCOC_RES_I_344___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_344__RX_DCOC_RES_Q_344___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_344__RX_DCOC_RES_Q_344___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_344___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_344___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_345 (0x005E4564) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_345___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_345___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_345__RX_DCOC_RANGE_345___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_345__RX_DCOC_RES_I_345___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_345__RX_DCOC_RES_Q_345___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_345__RX_DCOC_RANGE_345___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_345__RX_DCOC_RANGE_345___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_345__RX_DCOC_RES_I_345___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_345__RX_DCOC_RES_I_345___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_345__RX_DCOC_RES_Q_345___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_345__RX_DCOC_RES_Q_345___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_345___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_345___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_346 (0x005E4568) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_346___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_346___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_346__RX_DCOC_RANGE_346___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_346__RX_DCOC_RES_I_346___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_346__RX_DCOC_RES_Q_346___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_346__RX_DCOC_RANGE_346___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_346__RX_DCOC_RANGE_346___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_346__RX_DCOC_RES_I_346___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_346__RX_DCOC_RES_I_346___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_346__RX_DCOC_RES_Q_346___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_346__RX_DCOC_RES_Q_346___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_346___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_346___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_347 (0x005E456C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_347___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_347___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_347__RX_DCOC_RANGE_347___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_347__RX_DCOC_RES_I_347___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_347__RX_DCOC_RES_Q_347___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_347__RX_DCOC_RANGE_347___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_347__RX_DCOC_RANGE_347___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_347__RX_DCOC_RES_I_347___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_347__RX_DCOC_RES_I_347___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_347__RX_DCOC_RES_Q_347___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_347__RX_DCOC_RES_Q_347___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_347___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_347___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_348 (0x005E4570) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_348___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_348___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_348__RX_DCOC_RANGE_348___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_348__RX_DCOC_RES_I_348___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_348__RX_DCOC_RES_Q_348___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_348__RX_DCOC_RANGE_348___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_348__RX_DCOC_RANGE_348___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_348__RX_DCOC_RES_I_348___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_348__RX_DCOC_RES_I_348___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_348__RX_DCOC_RES_Q_348___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_348__RX_DCOC_RES_Q_348___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_348___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_348___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_349 (0x005E4574) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_349___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_349___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_349__RX_DCOC_RANGE_349___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_349__RX_DCOC_RES_I_349___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_349__RX_DCOC_RES_Q_349___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_349__RX_DCOC_RANGE_349___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_349__RX_DCOC_RANGE_349___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_349__RX_DCOC_RES_I_349___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_349__RX_DCOC_RES_I_349___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_349__RX_DCOC_RES_Q_349___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_349__RX_DCOC_RES_Q_349___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_349___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_349___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_350 (0x005E4578) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_350___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_350___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_350__RX_DCOC_RANGE_350___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_350__RX_DCOC_RES_I_350___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_350__RX_DCOC_RES_Q_350___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_350__RX_DCOC_RANGE_350___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_350__RX_DCOC_RANGE_350___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_350__RX_DCOC_RES_I_350___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_350__RX_DCOC_RES_I_350___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_350__RX_DCOC_RES_Q_350___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_350__RX_DCOC_RES_Q_350___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_350___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_350___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_351 (0x005E457C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_351___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_351___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_351__RX_DCOC_RANGE_351___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_351__RX_DCOC_RES_I_351___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_351__RX_DCOC_RES_Q_351___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_351__RX_DCOC_RANGE_351___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_351__RX_DCOC_RANGE_351___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_351__RX_DCOC_RES_I_351___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_351__RX_DCOC_RES_I_351___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_351__RX_DCOC_RES_Q_351___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_351__RX_DCOC_RES_Q_351___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_351___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_351___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_352 (0x005E4580) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_352___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_352___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_352__RX_DCOC_RANGE_352___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_352__RX_DCOC_RES_I_352___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_352__RX_DCOC_RES_Q_352___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_352__RX_DCOC_RANGE_352___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_352__RX_DCOC_RANGE_352___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_352__RX_DCOC_RES_I_352___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_352__RX_DCOC_RES_I_352___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_352__RX_DCOC_RES_Q_352___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_352__RX_DCOC_RES_Q_352___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_352___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_352___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_353 (0x005E4584) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_353___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_353___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_353__RX_DCOC_RANGE_353___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_353__RX_DCOC_RES_I_353___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_353__RX_DCOC_RES_Q_353___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_353__RX_DCOC_RANGE_353___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_353__RX_DCOC_RANGE_353___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_353__RX_DCOC_RES_I_353___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_353__RX_DCOC_RES_I_353___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_353__RX_DCOC_RES_Q_353___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_353__RX_DCOC_RES_Q_353___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_353___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_353___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_354 (0x005E4588) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_354___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_354___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_354__RX_DCOC_RANGE_354___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_354__RX_DCOC_RES_I_354___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_354__RX_DCOC_RES_Q_354___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_354__RX_DCOC_RANGE_354___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_354__RX_DCOC_RANGE_354___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_354__RX_DCOC_RES_I_354___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_354__RX_DCOC_RES_I_354___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_354__RX_DCOC_RES_Q_354___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_354__RX_DCOC_RES_Q_354___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_354___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_354___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_355 (0x005E458C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_355___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_355___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_355__RX_DCOC_RANGE_355___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_355__RX_DCOC_RES_I_355___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_355__RX_DCOC_RES_Q_355___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_355__RX_DCOC_RANGE_355___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_355__RX_DCOC_RANGE_355___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_355__RX_DCOC_RES_I_355___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_355__RX_DCOC_RES_I_355___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_355__RX_DCOC_RES_Q_355___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_355__RX_DCOC_RES_Q_355___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_355___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_355___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_356 (0x005E4590) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_356___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_356___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_356__RX_DCOC_RANGE_356___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_356__RX_DCOC_RES_I_356___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_356__RX_DCOC_RES_Q_356___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_356__RX_DCOC_RANGE_356___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_356__RX_DCOC_RANGE_356___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_356__RX_DCOC_RES_I_356___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_356__RX_DCOC_RES_I_356___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_356__RX_DCOC_RES_Q_356___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_356__RX_DCOC_RES_Q_356___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_356___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_356___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_357 (0x005E4594) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_357___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_357___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_357__RX_DCOC_RANGE_357___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_357__RX_DCOC_RES_I_357___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_357__RX_DCOC_RES_Q_357___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_357__RX_DCOC_RANGE_357___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_357__RX_DCOC_RANGE_357___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_357__RX_DCOC_RES_I_357___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_357__RX_DCOC_RES_I_357___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_357__RX_DCOC_RES_Q_357___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_357__RX_DCOC_RES_Q_357___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_357___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_357___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_358 (0x005E4598) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_358___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_358___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_358__RX_DCOC_RANGE_358___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_358__RX_DCOC_RES_I_358___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_358__RX_DCOC_RES_Q_358___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_358__RX_DCOC_RANGE_358___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_358__RX_DCOC_RANGE_358___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_358__RX_DCOC_RES_I_358___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_358__RX_DCOC_RES_I_358___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_358__RX_DCOC_RES_Q_358___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_358__RX_DCOC_RES_Q_358___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_358___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_358___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_359 (0x005E459C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_359___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_359___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_359__RX_DCOC_RANGE_359___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_359__RX_DCOC_RES_I_359___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_359__RX_DCOC_RES_Q_359___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_359__RX_DCOC_RANGE_359___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_359__RX_DCOC_RANGE_359___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_359__RX_DCOC_RES_I_359___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_359__RX_DCOC_RES_I_359___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_359__RX_DCOC_RES_Q_359___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_359__RX_DCOC_RES_Q_359___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_359___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_359___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_360 (0x005E45A0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_360___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_360___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_360__RX_DCOC_RANGE_360___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_360__RX_DCOC_RES_I_360___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_360__RX_DCOC_RES_Q_360___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_360__RX_DCOC_RANGE_360___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_360__RX_DCOC_RANGE_360___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_360__RX_DCOC_RES_I_360___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_360__RX_DCOC_RES_I_360___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_360__RX_DCOC_RES_Q_360___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_360__RX_DCOC_RES_Q_360___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_360___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_360___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_361 (0x005E45A4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_361___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_361___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_361__RX_DCOC_RANGE_361___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_361__RX_DCOC_RES_I_361___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_361__RX_DCOC_RES_Q_361___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_361__RX_DCOC_RANGE_361___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_361__RX_DCOC_RANGE_361___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_361__RX_DCOC_RES_I_361___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_361__RX_DCOC_RES_I_361___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_361__RX_DCOC_RES_Q_361___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_361__RX_DCOC_RES_Q_361___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_361___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_361___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_362 (0x005E45A8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_362___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_362___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_362__RX_DCOC_RANGE_362___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_362__RX_DCOC_RES_I_362___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_362__RX_DCOC_RES_Q_362___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_362__RX_DCOC_RANGE_362___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_362__RX_DCOC_RANGE_362___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_362__RX_DCOC_RES_I_362___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_362__RX_DCOC_RES_I_362___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_362__RX_DCOC_RES_Q_362___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_362__RX_DCOC_RES_Q_362___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_362___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_362___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_363 (0x005E45AC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_363___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_363___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_363__RX_DCOC_RANGE_363___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_363__RX_DCOC_RES_I_363___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_363__RX_DCOC_RES_Q_363___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_363__RX_DCOC_RANGE_363___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_363__RX_DCOC_RANGE_363___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_363__RX_DCOC_RES_I_363___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_363__RX_DCOC_RES_I_363___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_363__RX_DCOC_RES_Q_363___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_363__RX_DCOC_RES_Q_363___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_363___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_363___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_364 (0x005E45B0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_364___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_364___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_364__RX_DCOC_RANGE_364___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_364__RX_DCOC_RES_I_364___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_364__RX_DCOC_RES_Q_364___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_364__RX_DCOC_RANGE_364___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_364__RX_DCOC_RANGE_364___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_364__RX_DCOC_RES_I_364___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_364__RX_DCOC_RES_I_364___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_364__RX_DCOC_RES_Q_364___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_364__RX_DCOC_RES_Q_364___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_364___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_364___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_365 (0x005E45B4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_365___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_365___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_365__RX_DCOC_RANGE_365___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_365__RX_DCOC_RES_I_365___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_365__RX_DCOC_RES_Q_365___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_365__RX_DCOC_RANGE_365___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_365__RX_DCOC_RANGE_365___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_365__RX_DCOC_RES_I_365___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_365__RX_DCOC_RES_I_365___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_365__RX_DCOC_RES_Q_365___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_365__RX_DCOC_RES_Q_365___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_365___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_365___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_366 (0x005E45B8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_366___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_366___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_366__RX_DCOC_RANGE_366___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_366__RX_DCOC_RES_I_366___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_366__RX_DCOC_RES_Q_366___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_366__RX_DCOC_RANGE_366___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_366__RX_DCOC_RANGE_366___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_366__RX_DCOC_RES_I_366___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_366__RX_DCOC_RES_I_366___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_366__RX_DCOC_RES_Q_366___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_366__RX_DCOC_RES_Q_366___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_366___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_366___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_367 (0x005E45BC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_367___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_367___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_367__RX_DCOC_RANGE_367___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_367__RX_DCOC_RES_I_367___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_367__RX_DCOC_RES_Q_367___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_367__RX_DCOC_RANGE_367___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_367__RX_DCOC_RANGE_367___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_367__RX_DCOC_RES_I_367___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_367__RX_DCOC_RES_I_367___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_367__RX_DCOC_RES_Q_367___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_367__RX_DCOC_RES_Q_367___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_367___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_367___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_368 (0x005E45C0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_368___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_368___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_368__RX_DCOC_RANGE_368___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_368__RX_DCOC_RES_I_368___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_368__RX_DCOC_RES_Q_368___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_368__RX_DCOC_RANGE_368___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_368__RX_DCOC_RANGE_368___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_368__RX_DCOC_RES_I_368___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_368__RX_DCOC_RES_I_368___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_368__RX_DCOC_RES_Q_368___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_368__RX_DCOC_RES_Q_368___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_368___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_368___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_369 (0x005E45C4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_369___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_369___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_369__RX_DCOC_RANGE_369___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_369__RX_DCOC_RES_I_369___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_369__RX_DCOC_RES_Q_369___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_369__RX_DCOC_RANGE_369___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_369__RX_DCOC_RANGE_369___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_369__RX_DCOC_RES_I_369___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_369__RX_DCOC_RES_I_369___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_369__RX_DCOC_RES_Q_369___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_369__RX_DCOC_RES_Q_369___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_369___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_369___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_370 (0x005E45C8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_370___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_370___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_370__RX_DCOC_RANGE_370___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_370__RX_DCOC_RES_I_370___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_370__RX_DCOC_RES_Q_370___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_370__RX_DCOC_RANGE_370___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_370__RX_DCOC_RANGE_370___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_370__RX_DCOC_RES_I_370___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_370__RX_DCOC_RES_I_370___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_370__RX_DCOC_RES_Q_370___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_370__RX_DCOC_RES_Q_370___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_370___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_370___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_371 (0x005E45CC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_371___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_371___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_371__RX_DCOC_RANGE_371___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_371__RX_DCOC_RES_I_371___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_371__RX_DCOC_RES_Q_371___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_371__RX_DCOC_RANGE_371___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_371__RX_DCOC_RANGE_371___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_371__RX_DCOC_RES_I_371___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_371__RX_DCOC_RES_I_371___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_371__RX_DCOC_RES_Q_371___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_371__RX_DCOC_RES_Q_371___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_371___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_371___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_372 (0x005E45D0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_372___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_372___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_372__RX_DCOC_RANGE_372___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_372__RX_DCOC_RES_I_372___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_372__RX_DCOC_RES_Q_372___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_372__RX_DCOC_RANGE_372___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_372__RX_DCOC_RANGE_372___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_372__RX_DCOC_RES_I_372___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_372__RX_DCOC_RES_I_372___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_372__RX_DCOC_RES_Q_372___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_372__RX_DCOC_RES_Q_372___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_372___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_372___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_373 (0x005E45D4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_373___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_373___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_373__RX_DCOC_RANGE_373___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_373__RX_DCOC_RES_I_373___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_373__RX_DCOC_RES_Q_373___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_373__RX_DCOC_RANGE_373___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_373__RX_DCOC_RANGE_373___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_373__RX_DCOC_RES_I_373___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_373__RX_DCOC_RES_I_373___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_373__RX_DCOC_RES_Q_373___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_373__RX_DCOC_RES_Q_373___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_373___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_373___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_374 (0x005E45D8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_374___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_374___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_374__RX_DCOC_RANGE_374___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_374__RX_DCOC_RES_I_374___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_374__RX_DCOC_RES_Q_374___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_374__RX_DCOC_RANGE_374___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_374__RX_DCOC_RANGE_374___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_374__RX_DCOC_RES_I_374___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_374__RX_DCOC_RES_I_374___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_374__RX_DCOC_RES_Q_374___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_374__RX_DCOC_RES_Q_374___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_374___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_374___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_375 (0x005E45DC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_375___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_375___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_375__RX_DCOC_RANGE_375___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_375__RX_DCOC_RES_I_375___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_375__RX_DCOC_RES_Q_375___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_375__RX_DCOC_RANGE_375___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_375__RX_DCOC_RANGE_375___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_375__RX_DCOC_RES_I_375___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_375__RX_DCOC_RES_I_375___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_375__RX_DCOC_RES_Q_375___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_375__RX_DCOC_RES_Q_375___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_375___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_375___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_376 (0x005E45E0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_376___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_376___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_376__RX_DCOC_RANGE_376___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_376__RX_DCOC_RES_I_376___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_376__RX_DCOC_RES_Q_376___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_376__RX_DCOC_RANGE_376___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_376__RX_DCOC_RANGE_376___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_376__RX_DCOC_RES_I_376___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_376__RX_DCOC_RES_I_376___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_376__RX_DCOC_RES_Q_376___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_376__RX_DCOC_RES_Q_376___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_376___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_376___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_377 (0x005E45E4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_377___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_377___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_377__RX_DCOC_RANGE_377___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_377__RX_DCOC_RES_I_377___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_377__RX_DCOC_RES_Q_377___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_377__RX_DCOC_RANGE_377___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_377__RX_DCOC_RANGE_377___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_377__RX_DCOC_RES_I_377___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_377__RX_DCOC_RES_I_377___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_377__RX_DCOC_RES_Q_377___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_377__RX_DCOC_RES_Q_377___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_377___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_377___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_378 (0x005E45E8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_378___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_378___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_378__RX_DCOC_RANGE_378___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_378__RX_DCOC_RES_I_378___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_378__RX_DCOC_RES_Q_378___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_378__RX_DCOC_RANGE_378___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_378__RX_DCOC_RANGE_378___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_378__RX_DCOC_RES_I_378___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_378__RX_DCOC_RES_I_378___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_378__RX_DCOC_RES_Q_378___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_378__RX_DCOC_RES_Q_378___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_378___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_378___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_379 (0x005E45EC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_379___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_379___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_379__RX_DCOC_RANGE_379___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_379__RX_DCOC_RES_I_379___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_379__RX_DCOC_RES_Q_379___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_379__RX_DCOC_RANGE_379___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_379__RX_DCOC_RANGE_379___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_379__RX_DCOC_RES_I_379___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_379__RX_DCOC_RES_I_379___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_379__RX_DCOC_RES_Q_379___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_379__RX_DCOC_RES_Q_379___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_379___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_379___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_380 (0x005E45F0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_380___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_380___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_380__RX_DCOC_RANGE_380___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_380__RX_DCOC_RES_I_380___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_380__RX_DCOC_RES_Q_380___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_380__RX_DCOC_RANGE_380___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_380__RX_DCOC_RANGE_380___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_380__RX_DCOC_RES_I_380___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_380__RX_DCOC_RES_I_380___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_380__RX_DCOC_RES_Q_380___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_380__RX_DCOC_RES_Q_380___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_380___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_380___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_381 (0x005E45F4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_381___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_381___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_381__RX_DCOC_RANGE_381___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_381__RX_DCOC_RES_I_381___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_381__RX_DCOC_RES_Q_381___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_381__RX_DCOC_RANGE_381___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_381__RX_DCOC_RANGE_381___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_381__RX_DCOC_RES_I_381___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_381__RX_DCOC_RES_I_381___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_381__RX_DCOC_RES_Q_381___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_381__RX_DCOC_RES_Q_381___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_381___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_381___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_382 (0x005E45F8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_382___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_382___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_382__RX_DCOC_RANGE_382___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_382__RX_DCOC_RES_I_382___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_382__RX_DCOC_RES_Q_382___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_382__RX_DCOC_RANGE_382___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_382__RX_DCOC_RANGE_382___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_382__RX_DCOC_RES_I_382___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_382__RX_DCOC_RES_I_382___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_382__RX_DCOC_RES_Q_382___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_382__RX_DCOC_RES_Q_382___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_382___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_382___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_383 (0x005E45FC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_383___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_383___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_383__RX_DCOC_RANGE_383___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_383__RX_DCOC_RES_I_383___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_383__RX_DCOC_RES_Q_383___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_383__RX_DCOC_RANGE_383___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_383__RX_DCOC_RANGE_383___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_383__RX_DCOC_RES_I_383___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_383__RX_DCOC_RES_I_383___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_383__RX_DCOC_RES_Q_383___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_383__RX_DCOC_RES_Q_383___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_383___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_383___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_384 (0x005E4600) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_384___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_384___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_384__RX_DCOC_RANGE_384___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_384__RX_DCOC_RES_I_384___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_384__RX_DCOC_RES_Q_384___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_384__RX_DCOC_RANGE_384___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_384__RX_DCOC_RANGE_384___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_384__RX_DCOC_RES_I_384___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_384__RX_DCOC_RES_I_384___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_384__RX_DCOC_RES_Q_384___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_384__RX_DCOC_RES_Q_384___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_384___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_384___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_385 (0x005E4604) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_385___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_385___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_385__RX_DCOC_RANGE_385___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_385__RX_DCOC_RES_I_385___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_385__RX_DCOC_RES_Q_385___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_385__RX_DCOC_RANGE_385___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_385__RX_DCOC_RANGE_385___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_385__RX_DCOC_RES_I_385___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_385__RX_DCOC_RES_I_385___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_385__RX_DCOC_RES_Q_385___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_385__RX_DCOC_RES_Q_385___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_385___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_385___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_386 (0x005E4608) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_386___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_386___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_386__RX_DCOC_RANGE_386___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_386__RX_DCOC_RES_I_386___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_386__RX_DCOC_RES_Q_386___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_386__RX_DCOC_RANGE_386___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_386__RX_DCOC_RANGE_386___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_386__RX_DCOC_RES_I_386___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_386__RX_DCOC_RES_I_386___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_386__RX_DCOC_RES_Q_386___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_386__RX_DCOC_RES_Q_386___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_386___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_386___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_387 (0x005E460C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_387___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_387___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_387__RX_DCOC_RANGE_387___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_387__RX_DCOC_RES_I_387___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_387__RX_DCOC_RES_Q_387___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_387__RX_DCOC_RANGE_387___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_387__RX_DCOC_RANGE_387___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_387__RX_DCOC_RES_I_387___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_387__RX_DCOC_RES_I_387___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_387__RX_DCOC_RES_Q_387___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_387__RX_DCOC_RES_Q_387___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_387___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_387___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_388 (0x005E4610) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_388___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_388___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_388__RX_DCOC_RANGE_388___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_388__RX_DCOC_RES_I_388___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_388__RX_DCOC_RES_Q_388___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_388__RX_DCOC_RANGE_388___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_388__RX_DCOC_RANGE_388___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_388__RX_DCOC_RES_I_388___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_388__RX_DCOC_RES_I_388___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_388__RX_DCOC_RES_Q_388___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_388__RX_DCOC_RES_Q_388___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_388___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_388___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_389 (0x005E4614) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_389___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_389___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_389__RX_DCOC_RANGE_389___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_389__RX_DCOC_RES_I_389___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_389__RX_DCOC_RES_Q_389___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_389__RX_DCOC_RANGE_389___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_389__RX_DCOC_RANGE_389___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_389__RX_DCOC_RES_I_389___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_389__RX_DCOC_RES_I_389___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_389__RX_DCOC_RES_Q_389___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_389__RX_DCOC_RES_Q_389___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_389___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_389___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_390 (0x005E4618) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_390___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_390___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_390__RX_DCOC_RANGE_390___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_390__RX_DCOC_RES_I_390___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_390__RX_DCOC_RES_Q_390___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_390__RX_DCOC_RANGE_390___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_390__RX_DCOC_RANGE_390___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_390__RX_DCOC_RES_I_390___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_390__RX_DCOC_RES_I_390___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_390__RX_DCOC_RES_Q_390___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_390__RX_DCOC_RES_Q_390___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_390___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_390___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_391 (0x005E461C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_391___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_391___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_391__RX_DCOC_RANGE_391___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_391__RX_DCOC_RES_I_391___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_391__RX_DCOC_RES_Q_391___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_391__RX_DCOC_RANGE_391___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_391__RX_DCOC_RANGE_391___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_391__RX_DCOC_RES_I_391___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_391__RX_DCOC_RES_I_391___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_391__RX_DCOC_RES_Q_391___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_391__RX_DCOC_RES_Q_391___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_391___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_391___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_392 (0x005E4620) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_392___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_392___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_392__RX_DCOC_RANGE_392___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_392__RX_DCOC_RES_I_392___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_392__RX_DCOC_RES_Q_392___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_392__RX_DCOC_RANGE_392___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_392__RX_DCOC_RANGE_392___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_392__RX_DCOC_RES_I_392___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_392__RX_DCOC_RES_I_392___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_392__RX_DCOC_RES_Q_392___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_392__RX_DCOC_RES_Q_392___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_392___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_392___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_393 (0x005E4624) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_393___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_393___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_393__RX_DCOC_RANGE_393___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_393__RX_DCOC_RES_I_393___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_393__RX_DCOC_RES_Q_393___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_393__RX_DCOC_RANGE_393___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_393__RX_DCOC_RANGE_393___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_393__RX_DCOC_RES_I_393___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_393__RX_DCOC_RES_I_393___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_393__RX_DCOC_RES_Q_393___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_393__RX_DCOC_RES_Q_393___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_393___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_393___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_394 (0x005E4628) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_394___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_394___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_394__RX_DCOC_RANGE_394___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_394__RX_DCOC_RES_I_394___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_394__RX_DCOC_RES_Q_394___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_394__RX_DCOC_RANGE_394___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_394__RX_DCOC_RANGE_394___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_394__RX_DCOC_RES_I_394___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_394__RX_DCOC_RES_I_394___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_394__RX_DCOC_RES_Q_394___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_394__RX_DCOC_RES_Q_394___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_394___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_394___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_395 (0x005E462C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_395___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_395___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_395__RX_DCOC_RANGE_395___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_395__RX_DCOC_RES_I_395___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_395__RX_DCOC_RES_Q_395___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_395__RX_DCOC_RANGE_395___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_395__RX_DCOC_RANGE_395___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_395__RX_DCOC_RES_I_395___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_395__RX_DCOC_RES_I_395___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_395__RX_DCOC_RES_Q_395___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_395__RX_DCOC_RES_Q_395___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_395___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_395___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_396 (0x005E4630) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_396___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_396___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_396__RX_DCOC_RANGE_396___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_396__RX_DCOC_RES_I_396___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_396__RX_DCOC_RES_Q_396___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_396__RX_DCOC_RANGE_396___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_396__RX_DCOC_RANGE_396___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_396__RX_DCOC_RES_I_396___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_396__RX_DCOC_RES_I_396___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_396__RX_DCOC_RES_Q_396___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_396__RX_DCOC_RES_Q_396___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_396___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_396___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_397 (0x005E4634) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_397___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_397___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_397__RX_DCOC_RANGE_397___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_397__RX_DCOC_RES_I_397___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_397__RX_DCOC_RES_Q_397___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_397__RX_DCOC_RANGE_397___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_397__RX_DCOC_RANGE_397___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_397__RX_DCOC_RES_I_397___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_397__RX_DCOC_RES_I_397___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_397__RX_DCOC_RES_Q_397___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_397__RX_DCOC_RES_Q_397___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_397___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_397___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_398 (0x005E4638) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_398___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_398___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_398__RX_DCOC_RANGE_398___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_398__RX_DCOC_RES_I_398___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_398__RX_DCOC_RES_Q_398___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_398__RX_DCOC_RANGE_398___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_398__RX_DCOC_RANGE_398___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_398__RX_DCOC_RES_I_398___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_398__RX_DCOC_RES_I_398___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_398__RX_DCOC_RES_Q_398___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_398__RX_DCOC_RES_Q_398___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_398___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_398___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_399 (0x005E463C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_399___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_399___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_399__RX_DCOC_RANGE_399___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_399__RX_DCOC_RES_I_399___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_399__RX_DCOC_RES_Q_399___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_399__RX_DCOC_RANGE_399___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_399__RX_DCOC_RANGE_399___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_399__RX_DCOC_RES_I_399___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_399__RX_DCOC_RES_I_399___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_399__RX_DCOC_RES_Q_399___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_399__RX_DCOC_RES_Q_399___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_399___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_399___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_400 (0x005E4640) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_400___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_400___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_400__RX_DCOC_RANGE_400___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_400__RX_DCOC_RES_I_400___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_400__RX_DCOC_RES_Q_400___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_400__RX_DCOC_RANGE_400___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_400__RX_DCOC_RANGE_400___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_400__RX_DCOC_RES_I_400___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_400__RX_DCOC_RES_I_400___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_400__RX_DCOC_RES_Q_400___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_400__RX_DCOC_RES_Q_400___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_400___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_400___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_401 (0x005E4644) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_401___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_401___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_401__RX_DCOC_RANGE_401___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_401__RX_DCOC_RES_I_401___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_401__RX_DCOC_RES_Q_401___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_401__RX_DCOC_RANGE_401___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_401__RX_DCOC_RANGE_401___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_401__RX_DCOC_RES_I_401___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_401__RX_DCOC_RES_I_401___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_401__RX_DCOC_RES_Q_401___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_401__RX_DCOC_RES_Q_401___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_401___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_401___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_402 (0x005E4648) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_402___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_402___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_402__RX_DCOC_RANGE_402___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_402__RX_DCOC_RES_I_402___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_402__RX_DCOC_RES_Q_402___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_402__RX_DCOC_RANGE_402___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_402__RX_DCOC_RANGE_402___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_402__RX_DCOC_RES_I_402___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_402__RX_DCOC_RES_I_402___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_402__RX_DCOC_RES_Q_402___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_402__RX_DCOC_RES_Q_402___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_402___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_402___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_403 (0x005E464C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_403___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_403___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_403__RX_DCOC_RANGE_403___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_403__RX_DCOC_RES_I_403___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_403__RX_DCOC_RES_Q_403___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_403__RX_DCOC_RANGE_403___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_403__RX_DCOC_RANGE_403___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_403__RX_DCOC_RES_I_403___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_403__RX_DCOC_RES_I_403___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_403__RX_DCOC_RES_Q_403___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_403__RX_DCOC_RES_Q_403___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_403___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_403___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_404 (0x005E4650) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_404___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_404___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_404__RX_DCOC_RANGE_404___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_404__RX_DCOC_RES_I_404___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_404__RX_DCOC_RES_Q_404___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_404__RX_DCOC_RANGE_404___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_404__RX_DCOC_RANGE_404___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_404__RX_DCOC_RES_I_404___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_404__RX_DCOC_RES_I_404___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_404__RX_DCOC_RES_Q_404___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_404__RX_DCOC_RES_Q_404___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_404___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_404___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_405 (0x005E4654) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_405___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_405___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_405__RX_DCOC_RANGE_405___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_405__RX_DCOC_RES_I_405___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_405__RX_DCOC_RES_Q_405___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_405__RX_DCOC_RANGE_405___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_405__RX_DCOC_RANGE_405___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_405__RX_DCOC_RES_I_405___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_405__RX_DCOC_RES_I_405___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_405__RX_DCOC_RES_Q_405___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_405__RX_DCOC_RES_Q_405___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_405___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_405___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_406 (0x005E4658) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_406___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_406___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_406__RX_DCOC_RANGE_406___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_406__RX_DCOC_RES_I_406___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_406__RX_DCOC_RES_Q_406___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_406__RX_DCOC_RANGE_406___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_406__RX_DCOC_RANGE_406___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_406__RX_DCOC_RES_I_406___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_406__RX_DCOC_RES_I_406___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_406__RX_DCOC_RES_Q_406___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_406__RX_DCOC_RES_Q_406___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_406___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_406___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_407 (0x005E465C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_407___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_407___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_407__RX_DCOC_RANGE_407___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_407__RX_DCOC_RES_I_407___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_407__RX_DCOC_RES_Q_407___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_407__RX_DCOC_RANGE_407___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_407__RX_DCOC_RANGE_407___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_407__RX_DCOC_RES_I_407___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_407__RX_DCOC_RES_I_407___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_407__RX_DCOC_RES_Q_407___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_407__RX_DCOC_RES_Q_407___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_407___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_407___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_408 (0x005E4660) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_408___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_408___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_408__RX_DCOC_RANGE_408___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_408__RX_DCOC_RES_I_408___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_408__RX_DCOC_RES_Q_408___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_408__RX_DCOC_RANGE_408___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_408__RX_DCOC_RANGE_408___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_408__RX_DCOC_RES_I_408___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_408__RX_DCOC_RES_I_408___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_408__RX_DCOC_RES_Q_408___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_408__RX_DCOC_RES_Q_408___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_408___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_408___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_409 (0x005E4664) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_409___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_409___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_409__RX_DCOC_RANGE_409___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_409__RX_DCOC_RES_I_409___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_409__RX_DCOC_RES_Q_409___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_409__RX_DCOC_RANGE_409___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_409__RX_DCOC_RANGE_409___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_409__RX_DCOC_RES_I_409___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_409__RX_DCOC_RES_I_409___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_409__RX_DCOC_RES_Q_409___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_409__RX_DCOC_RES_Q_409___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_409___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_409___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_410 (0x005E4668) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_410___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_410___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_410__RX_DCOC_RANGE_410___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_410__RX_DCOC_RES_I_410___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_410__RX_DCOC_RES_Q_410___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_410__RX_DCOC_RANGE_410___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_410__RX_DCOC_RANGE_410___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_410__RX_DCOC_RES_I_410___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_410__RX_DCOC_RES_I_410___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_410__RX_DCOC_RES_Q_410___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_410__RX_DCOC_RES_Q_410___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_410___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_410___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_411 (0x005E466C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_411___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_411___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_411__RX_DCOC_RANGE_411___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_411__RX_DCOC_RES_I_411___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_411__RX_DCOC_RES_Q_411___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_411__RX_DCOC_RANGE_411___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_411__RX_DCOC_RANGE_411___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_411__RX_DCOC_RES_I_411___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_411__RX_DCOC_RES_I_411___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_411__RX_DCOC_RES_Q_411___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_411__RX_DCOC_RES_Q_411___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_411___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_411___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_412 (0x005E4670) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_412___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_412___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_412__RX_DCOC_RANGE_412___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_412__RX_DCOC_RES_I_412___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_412__RX_DCOC_RES_Q_412___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_412__RX_DCOC_RANGE_412___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_412__RX_DCOC_RANGE_412___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_412__RX_DCOC_RES_I_412___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_412__RX_DCOC_RES_I_412___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_412__RX_DCOC_RES_Q_412___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_412__RX_DCOC_RES_Q_412___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_412___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_412___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_413 (0x005E4674) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_413___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_413___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_413__RX_DCOC_RANGE_413___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_413__RX_DCOC_RES_I_413___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_413__RX_DCOC_RES_Q_413___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_413__RX_DCOC_RANGE_413___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_413__RX_DCOC_RANGE_413___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_413__RX_DCOC_RES_I_413___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_413__RX_DCOC_RES_I_413___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_413__RX_DCOC_RES_Q_413___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_413__RX_DCOC_RES_Q_413___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_413___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_413___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_414 (0x005E4678) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_414___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_414___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_414__RX_DCOC_RANGE_414___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_414__RX_DCOC_RES_I_414___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_414__RX_DCOC_RES_Q_414___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_414__RX_DCOC_RANGE_414___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_414__RX_DCOC_RANGE_414___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_414__RX_DCOC_RES_I_414___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_414__RX_DCOC_RES_I_414___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_414__RX_DCOC_RES_Q_414___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_414__RX_DCOC_RES_Q_414___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_414___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_414___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_415 (0x005E467C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_415___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_415___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_415__RX_DCOC_RANGE_415___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_415__RX_DCOC_RES_I_415___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_415__RX_DCOC_RES_Q_415___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_415__RX_DCOC_RANGE_415___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_415__RX_DCOC_RANGE_415___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_415__RX_DCOC_RES_I_415___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_415__RX_DCOC_RES_I_415___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_415__RX_DCOC_RES_Q_415___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_415__RX_DCOC_RES_Q_415___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_415___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_415___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_416 (0x005E4680) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_416___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_416___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_416__RX_DCOC_RANGE_416___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_416__RX_DCOC_RES_I_416___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_416__RX_DCOC_RES_Q_416___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_416__RX_DCOC_RANGE_416___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_416__RX_DCOC_RANGE_416___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_416__RX_DCOC_RES_I_416___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_416__RX_DCOC_RES_I_416___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_416__RX_DCOC_RES_Q_416___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_416__RX_DCOC_RES_Q_416___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_416___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_416___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_417 (0x005E4684) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_417___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_417___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_417__RX_DCOC_RANGE_417___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_417__RX_DCOC_RES_I_417___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_417__RX_DCOC_RES_Q_417___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_417__RX_DCOC_RANGE_417___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_417__RX_DCOC_RANGE_417___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_417__RX_DCOC_RES_I_417___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_417__RX_DCOC_RES_I_417___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_417__RX_DCOC_RES_Q_417___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_417__RX_DCOC_RES_Q_417___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_417___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_417___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_418 (0x005E4688) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_418___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_418___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_418__RX_DCOC_RANGE_418___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_418__RX_DCOC_RES_I_418___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_418__RX_DCOC_RES_Q_418___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_418__RX_DCOC_RANGE_418___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_418__RX_DCOC_RANGE_418___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_418__RX_DCOC_RES_I_418___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_418__RX_DCOC_RES_I_418___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_418__RX_DCOC_RES_Q_418___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_418__RX_DCOC_RES_Q_418___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_418___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_418___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_419 (0x005E468C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_419___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_419___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_419__RX_DCOC_RANGE_419___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_419__RX_DCOC_RES_I_419___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_419__RX_DCOC_RES_Q_419___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_419__RX_DCOC_RANGE_419___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_419__RX_DCOC_RANGE_419___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_419__RX_DCOC_RES_I_419___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_419__RX_DCOC_RES_I_419___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_419__RX_DCOC_RES_Q_419___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_419__RX_DCOC_RES_Q_419___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_419___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_419___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_420 (0x005E4690) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_420___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_420___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_420__RX_DCOC_RANGE_420___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_420__RX_DCOC_RES_I_420___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_420__RX_DCOC_RES_Q_420___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_420__RX_DCOC_RANGE_420___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_420__RX_DCOC_RANGE_420___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_420__RX_DCOC_RES_I_420___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_420__RX_DCOC_RES_I_420___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_420__RX_DCOC_RES_Q_420___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_420__RX_DCOC_RES_Q_420___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_420___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_420___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_421 (0x005E4694) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_421___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_421___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_421__RX_DCOC_RANGE_421___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_421__RX_DCOC_RES_I_421___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_421__RX_DCOC_RES_Q_421___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_421__RX_DCOC_RANGE_421___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_421__RX_DCOC_RANGE_421___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_421__RX_DCOC_RES_I_421___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_421__RX_DCOC_RES_I_421___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_421__RX_DCOC_RES_Q_421___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_421__RX_DCOC_RES_Q_421___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_421___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_421___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_422 (0x005E4698) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_422___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_422___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_422__RX_DCOC_RANGE_422___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_422__RX_DCOC_RES_I_422___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_422__RX_DCOC_RES_Q_422___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_422__RX_DCOC_RANGE_422___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_422__RX_DCOC_RANGE_422___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_422__RX_DCOC_RES_I_422___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_422__RX_DCOC_RES_I_422___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_422__RX_DCOC_RES_Q_422___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_422__RX_DCOC_RES_Q_422___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_422___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_422___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_423 (0x005E469C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_423___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_423___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_423__RX_DCOC_RANGE_423___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_423__RX_DCOC_RES_I_423___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_423__RX_DCOC_RES_Q_423___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_423__RX_DCOC_RANGE_423___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_423__RX_DCOC_RANGE_423___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_423__RX_DCOC_RES_I_423___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_423__RX_DCOC_RES_I_423___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_423__RX_DCOC_RES_Q_423___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_423__RX_DCOC_RES_Q_423___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_423___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_423___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_424 (0x005E46A0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_424___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_424___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_424__RX_DCOC_RANGE_424___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_424__RX_DCOC_RES_I_424___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_424__RX_DCOC_RES_Q_424___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_424__RX_DCOC_RANGE_424___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_424__RX_DCOC_RANGE_424___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_424__RX_DCOC_RES_I_424___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_424__RX_DCOC_RES_I_424___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_424__RX_DCOC_RES_Q_424___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_424__RX_DCOC_RES_Q_424___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_424___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_424___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_425 (0x005E46A4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_425___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_425___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_425__RX_DCOC_RANGE_425___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_425__RX_DCOC_RES_I_425___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_425__RX_DCOC_RES_Q_425___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_425__RX_DCOC_RANGE_425___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_425__RX_DCOC_RANGE_425___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_425__RX_DCOC_RES_I_425___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_425__RX_DCOC_RES_I_425___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_425__RX_DCOC_RES_Q_425___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_425__RX_DCOC_RES_Q_425___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_425___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_425___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_426 (0x005E46A8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_426___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_426___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_426__RX_DCOC_RANGE_426___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_426__RX_DCOC_RES_I_426___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_426__RX_DCOC_RES_Q_426___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_426__RX_DCOC_RANGE_426___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_426__RX_DCOC_RANGE_426___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_426__RX_DCOC_RES_I_426___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_426__RX_DCOC_RES_I_426___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_426__RX_DCOC_RES_Q_426___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_426__RX_DCOC_RES_Q_426___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_426___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_426___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_427 (0x005E46AC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_427___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_427___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_427__RX_DCOC_RANGE_427___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_427__RX_DCOC_RES_I_427___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_427__RX_DCOC_RES_Q_427___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_427__RX_DCOC_RANGE_427___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_427__RX_DCOC_RANGE_427___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_427__RX_DCOC_RES_I_427___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_427__RX_DCOC_RES_I_427___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_427__RX_DCOC_RES_Q_427___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_427__RX_DCOC_RES_Q_427___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_427___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_427___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_428 (0x005E46B0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_428___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_428___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_428__RX_DCOC_RANGE_428___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_428__RX_DCOC_RES_I_428___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_428__RX_DCOC_RES_Q_428___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_428__RX_DCOC_RANGE_428___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_428__RX_DCOC_RANGE_428___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_428__RX_DCOC_RES_I_428___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_428__RX_DCOC_RES_I_428___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_428__RX_DCOC_RES_Q_428___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_428__RX_DCOC_RES_Q_428___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_428___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_428___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_429 (0x005E46B4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_429___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_429___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_429__RX_DCOC_RANGE_429___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_429__RX_DCOC_RES_I_429___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_429__RX_DCOC_RES_Q_429___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_429__RX_DCOC_RANGE_429___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_429__RX_DCOC_RANGE_429___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_429__RX_DCOC_RES_I_429___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_429__RX_DCOC_RES_I_429___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_429__RX_DCOC_RES_Q_429___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_429__RX_DCOC_RES_Q_429___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_429___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_429___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_430 (0x005E46B8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_430___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_430___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_430__RX_DCOC_RANGE_430___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_430__RX_DCOC_RES_I_430___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_430__RX_DCOC_RES_Q_430___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_430__RX_DCOC_RANGE_430___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_430__RX_DCOC_RANGE_430___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_430__RX_DCOC_RES_I_430___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_430__RX_DCOC_RES_I_430___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_430__RX_DCOC_RES_Q_430___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_430__RX_DCOC_RES_Q_430___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_430___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_430___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_431 (0x005E46BC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_431___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_431___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_431__RX_DCOC_RANGE_431___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_431__RX_DCOC_RES_I_431___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_431__RX_DCOC_RES_Q_431___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_431__RX_DCOC_RANGE_431___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_431__RX_DCOC_RANGE_431___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_431__RX_DCOC_RES_I_431___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_431__RX_DCOC_RES_I_431___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_431__RX_DCOC_RES_Q_431___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_431__RX_DCOC_RES_Q_431___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_431___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_431___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_432 (0x005E46C0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_432___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_432___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_432__RX_DCOC_RANGE_432___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_432__RX_DCOC_RES_I_432___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_432__RX_DCOC_RES_Q_432___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_432__RX_DCOC_RANGE_432___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_432__RX_DCOC_RANGE_432___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_432__RX_DCOC_RES_I_432___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_432__RX_DCOC_RES_I_432___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_432__RX_DCOC_RES_Q_432___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_432__RX_DCOC_RES_Q_432___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_432___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_432___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_433 (0x005E46C4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_433___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_433___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_433__RX_DCOC_RANGE_433___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_433__RX_DCOC_RES_I_433___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_433__RX_DCOC_RES_Q_433___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_433__RX_DCOC_RANGE_433___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_433__RX_DCOC_RANGE_433___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_433__RX_DCOC_RES_I_433___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_433__RX_DCOC_RES_I_433___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_433__RX_DCOC_RES_Q_433___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_433__RX_DCOC_RES_Q_433___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_433___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_433___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_434 (0x005E46C8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_434___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_434___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_434__RX_DCOC_RANGE_434___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_434__RX_DCOC_RES_I_434___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_434__RX_DCOC_RES_Q_434___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_434__RX_DCOC_RANGE_434___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_434__RX_DCOC_RANGE_434___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_434__RX_DCOC_RES_I_434___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_434__RX_DCOC_RES_I_434___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_434__RX_DCOC_RES_Q_434___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_434__RX_DCOC_RES_Q_434___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_434___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_434___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_435 (0x005E46CC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_435___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_435___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_435__RX_DCOC_RANGE_435___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_435__RX_DCOC_RES_I_435___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_435__RX_DCOC_RES_Q_435___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_435__RX_DCOC_RANGE_435___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_435__RX_DCOC_RANGE_435___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_435__RX_DCOC_RES_I_435___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_435__RX_DCOC_RES_I_435___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_435__RX_DCOC_RES_Q_435___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_435__RX_DCOC_RES_Q_435___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_435___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_435___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_436 (0x005E46D0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_436___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_436___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_436__RX_DCOC_RANGE_436___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_436__RX_DCOC_RES_I_436___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_436__RX_DCOC_RES_Q_436___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_436__RX_DCOC_RANGE_436___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_436__RX_DCOC_RANGE_436___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_436__RX_DCOC_RES_I_436___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_436__RX_DCOC_RES_I_436___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_436__RX_DCOC_RES_Q_436___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_436__RX_DCOC_RES_Q_436___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_436___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_436___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_437 (0x005E46D4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_437___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_437___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_437__RX_DCOC_RANGE_437___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_437__RX_DCOC_RES_I_437___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_437__RX_DCOC_RES_Q_437___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_437__RX_DCOC_RANGE_437___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_437__RX_DCOC_RANGE_437___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_437__RX_DCOC_RES_I_437___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_437__RX_DCOC_RES_I_437___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_437__RX_DCOC_RES_Q_437___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_437__RX_DCOC_RES_Q_437___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_437___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_437___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_438 (0x005E46D8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_438___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_438___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_438__RX_DCOC_RANGE_438___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_438__RX_DCOC_RES_I_438___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_438__RX_DCOC_RES_Q_438___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_438__RX_DCOC_RANGE_438___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_438__RX_DCOC_RANGE_438___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_438__RX_DCOC_RES_I_438___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_438__RX_DCOC_RES_I_438___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_438__RX_DCOC_RES_Q_438___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_438__RX_DCOC_RES_Q_438___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_438___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_438___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_439 (0x005E46DC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_439___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_439___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_439__RX_DCOC_RANGE_439___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_439__RX_DCOC_RES_I_439___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_439__RX_DCOC_RES_Q_439___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_439__RX_DCOC_RANGE_439___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_439__RX_DCOC_RANGE_439___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_439__RX_DCOC_RES_I_439___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_439__RX_DCOC_RES_I_439___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_439__RX_DCOC_RES_Q_439___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_439__RX_DCOC_RES_Q_439___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_439___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_439___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_440 (0x005E46E0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_440___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_440___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_440__RX_DCOC_RANGE_440___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_440__RX_DCOC_RES_I_440___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_440__RX_DCOC_RES_Q_440___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_440__RX_DCOC_RANGE_440___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_440__RX_DCOC_RANGE_440___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_440__RX_DCOC_RES_I_440___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_440__RX_DCOC_RES_I_440___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_440__RX_DCOC_RES_Q_440___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_440__RX_DCOC_RES_Q_440___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_440___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_440___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_441 (0x005E46E4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_441___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_441___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_441__RX_DCOC_RANGE_441___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_441__RX_DCOC_RES_I_441___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_441__RX_DCOC_RES_Q_441___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_441__RX_DCOC_RANGE_441___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_441__RX_DCOC_RANGE_441___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_441__RX_DCOC_RES_I_441___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_441__RX_DCOC_RES_I_441___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_441__RX_DCOC_RES_Q_441___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_441__RX_DCOC_RES_Q_441___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_441___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_441___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_442 (0x005E46E8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_442___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_442___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_442__RX_DCOC_RANGE_442___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_442__RX_DCOC_RES_I_442___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_442__RX_DCOC_RES_Q_442___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_442__RX_DCOC_RANGE_442___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_442__RX_DCOC_RANGE_442___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_442__RX_DCOC_RES_I_442___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_442__RX_DCOC_RES_I_442___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_442__RX_DCOC_RES_Q_442___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_442__RX_DCOC_RES_Q_442___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_442___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_442___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_443 (0x005E46EC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_443___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_443___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_443__RX_DCOC_RANGE_443___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_443__RX_DCOC_RES_I_443___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_443__RX_DCOC_RES_Q_443___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_443__RX_DCOC_RANGE_443___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_443__RX_DCOC_RANGE_443___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_443__RX_DCOC_RES_I_443___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_443__RX_DCOC_RES_I_443___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_443__RX_DCOC_RES_Q_443___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_443__RX_DCOC_RES_Q_443___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_443___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_443___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_444 (0x005E46F0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_444___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_444___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_444__RX_DCOC_RANGE_444___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_444__RX_DCOC_RES_I_444___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_444__RX_DCOC_RES_Q_444___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_444__RX_DCOC_RANGE_444___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_444__RX_DCOC_RANGE_444___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_444__RX_DCOC_RES_I_444___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_444__RX_DCOC_RES_I_444___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_444__RX_DCOC_RES_Q_444___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_444__RX_DCOC_RES_Q_444___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_444___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_444___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_445 (0x005E46F4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_445___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_445___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_445__RX_DCOC_RANGE_445___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_445__RX_DCOC_RES_I_445___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_445__RX_DCOC_RES_Q_445___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_445__RX_DCOC_RANGE_445___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_445__RX_DCOC_RANGE_445___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_445__RX_DCOC_RES_I_445___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_445__RX_DCOC_RES_I_445___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_445__RX_DCOC_RES_Q_445___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_445__RX_DCOC_RES_Q_445___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_445___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_445___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_446 (0x005E46F8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_446___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_446___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_446__RX_DCOC_RANGE_446___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_446__RX_DCOC_RES_I_446___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_446__RX_DCOC_RES_Q_446___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_446__RX_DCOC_RANGE_446___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_446__RX_DCOC_RANGE_446___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_446__RX_DCOC_RES_I_446___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_446__RX_DCOC_RES_I_446___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_446__RX_DCOC_RES_Q_446___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_446__RX_DCOC_RES_Q_446___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_446___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_446___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_447 (0x005E46FC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_447___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_447___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_447__RX_DCOC_RANGE_447___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_447__RX_DCOC_RES_I_447___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_447__RX_DCOC_RES_Q_447___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_447__RX_DCOC_RANGE_447___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_447__RX_DCOC_RANGE_447___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_447__RX_DCOC_RES_I_447___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_447__RX_DCOC_RES_I_447___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_447__RX_DCOC_RES_Q_447___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_447__RX_DCOC_RES_Q_447___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_447___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_447___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_448 (0x005E4700) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_448___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_448___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_448__RX_DCOC_RANGE_448___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_448__RX_DCOC_RES_I_448___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_448__RX_DCOC_RES_Q_448___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_448__RX_DCOC_RANGE_448___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_448__RX_DCOC_RANGE_448___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_448__RX_DCOC_RES_I_448___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_448__RX_DCOC_RES_I_448___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_448__RX_DCOC_RES_Q_448___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_448__RX_DCOC_RES_Q_448___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_448___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_448___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_449 (0x005E4704) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_449___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_449___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_449__RX_DCOC_RANGE_449___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_449__RX_DCOC_RES_I_449___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_449__RX_DCOC_RES_Q_449___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_449__RX_DCOC_RANGE_449___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_449__RX_DCOC_RANGE_449___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_449__RX_DCOC_RES_I_449___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_449__RX_DCOC_RES_I_449___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_449__RX_DCOC_RES_Q_449___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_449__RX_DCOC_RES_Q_449___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_449___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_449___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_450 (0x005E4708) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_450___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_450___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_450__RX_DCOC_RANGE_450___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_450__RX_DCOC_RES_I_450___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_450__RX_DCOC_RES_Q_450___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_450__RX_DCOC_RANGE_450___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_450__RX_DCOC_RANGE_450___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_450__RX_DCOC_RES_I_450___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_450__RX_DCOC_RES_I_450___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_450__RX_DCOC_RES_Q_450___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_450__RX_DCOC_RES_Q_450___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_450___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_450___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_451 (0x005E470C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_451___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_451___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_451__RX_DCOC_RANGE_451___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_451__RX_DCOC_RES_I_451___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_451__RX_DCOC_RES_Q_451___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_451__RX_DCOC_RANGE_451___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_451__RX_DCOC_RANGE_451___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_451__RX_DCOC_RES_I_451___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_451__RX_DCOC_RES_I_451___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_451__RX_DCOC_RES_Q_451___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_451__RX_DCOC_RES_Q_451___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_451___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_451___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_452 (0x005E4710) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_452___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_452___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_452__RX_DCOC_RANGE_452___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_452__RX_DCOC_RES_I_452___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_452__RX_DCOC_RES_Q_452___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_452__RX_DCOC_RANGE_452___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_452__RX_DCOC_RANGE_452___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_452__RX_DCOC_RES_I_452___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_452__RX_DCOC_RES_I_452___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_452__RX_DCOC_RES_Q_452___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_452__RX_DCOC_RES_Q_452___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_452___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_452___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_453 (0x005E4714) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_453___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_453___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_453__RX_DCOC_RANGE_453___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_453__RX_DCOC_RES_I_453___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_453__RX_DCOC_RES_Q_453___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_453__RX_DCOC_RANGE_453___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_453__RX_DCOC_RANGE_453___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_453__RX_DCOC_RES_I_453___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_453__RX_DCOC_RES_I_453___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_453__RX_DCOC_RES_Q_453___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_453__RX_DCOC_RES_Q_453___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_453___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_453___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_454 (0x005E4718) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_454___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_454___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_454__RX_DCOC_RANGE_454___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_454__RX_DCOC_RES_I_454___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_454__RX_DCOC_RES_Q_454___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_454__RX_DCOC_RANGE_454___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_454__RX_DCOC_RANGE_454___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_454__RX_DCOC_RES_I_454___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_454__RX_DCOC_RES_I_454___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_454__RX_DCOC_RES_Q_454___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_454__RX_DCOC_RES_Q_454___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_454___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_454___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_455 (0x005E471C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_455___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_455___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_455__RX_DCOC_RANGE_455___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_455__RX_DCOC_RES_I_455___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_455__RX_DCOC_RES_Q_455___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_455__RX_DCOC_RANGE_455___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_455__RX_DCOC_RANGE_455___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_455__RX_DCOC_RES_I_455___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_455__RX_DCOC_RES_I_455___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_455__RX_DCOC_RES_Q_455___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_455__RX_DCOC_RES_Q_455___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_455___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_455___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_456 (0x005E4720) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_456___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_456___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_456__RX_DCOC_RANGE_456___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_456__RX_DCOC_RES_I_456___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_456__RX_DCOC_RES_Q_456___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_456__RX_DCOC_RANGE_456___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_456__RX_DCOC_RANGE_456___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_456__RX_DCOC_RES_I_456___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_456__RX_DCOC_RES_I_456___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_456__RX_DCOC_RES_Q_456___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_456__RX_DCOC_RES_Q_456___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_456___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_456___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_457 (0x005E4724) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_457___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_457___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_457__RX_DCOC_RANGE_457___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_457__RX_DCOC_RES_I_457___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_457__RX_DCOC_RES_Q_457___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_457__RX_DCOC_RANGE_457___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_457__RX_DCOC_RANGE_457___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_457__RX_DCOC_RES_I_457___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_457__RX_DCOC_RES_I_457___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_457__RX_DCOC_RES_Q_457___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_457__RX_DCOC_RES_Q_457___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_457___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_457___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_458 (0x005E4728) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_458___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_458___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_458__RX_DCOC_RANGE_458___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_458__RX_DCOC_RES_I_458___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_458__RX_DCOC_RES_Q_458___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_458__RX_DCOC_RANGE_458___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_458__RX_DCOC_RANGE_458___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_458__RX_DCOC_RES_I_458___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_458__RX_DCOC_RES_I_458___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_458__RX_DCOC_RES_Q_458___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_458__RX_DCOC_RES_Q_458___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_458___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_458___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_459 (0x005E472C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_459___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_459___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_459__RX_DCOC_RANGE_459___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_459__RX_DCOC_RES_I_459___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_459__RX_DCOC_RES_Q_459___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_459__RX_DCOC_RANGE_459___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_459__RX_DCOC_RANGE_459___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_459__RX_DCOC_RES_I_459___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_459__RX_DCOC_RES_I_459___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_459__RX_DCOC_RES_Q_459___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_459__RX_DCOC_RES_Q_459___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_459___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_459___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_460 (0x005E4730) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_460___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_460___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_460__RX_DCOC_RANGE_460___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_460__RX_DCOC_RES_I_460___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_460__RX_DCOC_RES_Q_460___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_460__RX_DCOC_RANGE_460___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_460__RX_DCOC_RANGE_460___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_460__RX_DCOC_RES_I_460___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_460__RX_DCOC_RES_I_460___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_460__RX_DCOC_RES_Q_460___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_460__RX_DCOC_RES_Q_460___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_460___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_460___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_461 (0x005E4734) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_461___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_461___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_461__RX_DCOC_RANGE_461___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_461__RX_DCOC_RES_I_461___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_461__RX_DCOC_RES_Q_461___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_461__RX_DCOC_RANGE_461___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_461__RX_DCOC_RANGE_461___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_461__RX_DCOC_RES_I_461___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_461__RX_DCOC_RES_I_461___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_461__RX_DCOC_RES_Q_461___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_461__RX_DCOC_RES_Q_461___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_461___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_461___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_462 (0x005E4738) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_462___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_462___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_462__RX_DCOC_RANGE_462___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_462__RX_DCOC_RES_I_462___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_462__RX_DCOC_RES_Q_462___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_462__RX_DCOC_RANGE_462___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_462__RX_DCOC_RANGE_462___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_462__RX_DCOC_RES_I_462___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_462__RX_DCOC_RES_I_462___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_462__RX_DCOC_RES_Q_462___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_462__RX_DCOC_RES_Q_462___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_462___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_462___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_463 (0x005E473C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_463___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_463___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_463__RX_DCOC_RANGE_463___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_463__RX_DCOC_RES_I_463___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_463__RX_DCOC_RES_Q_463___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_463__RX_DCOC_RANGE_463___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_463__RX_DCOC_RANGE_463___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_463__RX_DCOC_RES_I_463___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_463__RX_DCOC_RES_I_463___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_463__RX_DCOC_RES_Q_463___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_463__RX_DCOC_RES_Q_463___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_463___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_463___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_464 (0x005E4740) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_464___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_464___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_464__RX_DCOC_RANGE_464___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_464__RX_DCOC_RES_I_464___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_464__RX_DCOC_RES_Q_464___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_464__RX_DCOC_RANGE_464___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_464__RX_DCOC_RANGE_464___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_464__RX_DCOC_RES_I_464___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_464__RX_DCOC_RES_I_464___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_464__RX_DCOC_RES_Q_464___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_464__RX_DCOC_RES_Q_464___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_464___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_464___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_465 (0x005E4744) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_465___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_465___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_465__RX_DCOC_RANGE_465___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_465__RX_DCOC_RES_I_465___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_465__RX_DCOC_RES_Q_465___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_465__RX_DCOC_RANGE_465___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_465__RX_DCOC_RANGE_465___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_465__RX_DCOC_RES_I_465___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_465__RX_DCOC_RES_I_465___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_465__RX_DCOC_RES_Q_465___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_465__RX_DCOC_RES_Q_465___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_465___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_465___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_466 (0x005E4748) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_466___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_466___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_466__RX_DCOC_RANGE_466___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_466__RX_DCOC_RES_I_466___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_466__RX_DCOC_RES_Q_466___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_466__RX_DCOC_RANGE_466___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_466__RX_DCOC_RANGE_466___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_466__RX_DCOC_RES_I_466___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_466__RX_DCOC_RES_I_466___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_466__RX_DCOC_RES_Q_466___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_466__RX_DCOC_RES_Q_466___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_466___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_466___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_467 (0x005E474C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_467___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_467___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_467__RX_DCOC_RANGE_467___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_467__RX_DCOC_RES_I_467___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_467__RX_DCOC_RES_Q_467___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_467__RX_DCOC_RANGE_467___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_467__RX_DCOC_RANGE_467___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_467__RX_DCOC_RES_I_467___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_467__RX_DCOC_RES_I_467___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_467__RX_DCOC_RES_Q_467___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_467__RX_DCOC_RES_Q_467___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_467___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_467___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_468 (0x005E4750) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_468___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_468___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_468__RX_DCOC_RANGE_468___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_468__RX_DCOC_RES_I_468___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_468__RX_DCOC_RES_Q_468___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_468__RX_DCOC_RANGE_468___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_468__RX_DCOC_RANGE_468___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_468__RX_DCOC_RES_I_468___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_468__RX_DCOC_RES_I_468___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_468__RX_DCOC_RES_Q_468___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_468__RX_DCOC_RES_Q_468___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_468___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_468___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_469 (0x005E4754) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_469___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_469___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_469__RX_DCOC_RANGE_469___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_469__RX_DCOC_RES_I_469___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_469__RX_DCOC_RES_Q_469___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_469__RX_DCOC_RANGE_469___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_469__RX_DCOC_RANGE_469___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_469__RX_DCOC_RES_I_469___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_469__RX_DCOC_RES_I_469___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_469__RX_DCOC_RES_Q_469___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_469__RX_DCOC_RES_Q_469___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_469___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_469___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_470 (0x005E4758) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_470___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_470___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_470__RX_DCOC_RANGE_470___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_470__RX_DCOC_RES_I_470___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_470__RX_DCOC_RES_Q_470___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_470__RX_DCOC_RANGE_470___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_470__RX_DCOC_RANGE_470___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_470__RX_DCOC_RES_I_470___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_470__RX_DCOC_RES_I_470___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_470__RX_DCOC_RES_Q_470___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_470__RX_DCOC_RES_Q_470___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_470___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_470___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_471 (0x005E475C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_471___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_471___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_471__RX_DCOC_RANGE_471___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_471__RX_DCOC_RES_I_471___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_471__RX_DCOC_RES_Q_471___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_471__RX_DCOC_RANGE_471___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_471__RX_DCOC_RANGE_471___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_471__RX_DCOC_RES_I_471___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_471__RX_DCOC_RES_I_471___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_471__RX_DCOC_RES_Q_471___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_471__RX_DCOC_RES_Q_471___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_471___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_471___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_472 (0x005E4760) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_472___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_472___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_472__RX_DCOC_RANGE_472___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_472__RX_DCOC_RES_I_472___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_472__RX_DCOC_RES_Q_472___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_472__RX_DCOC_RANGE_472___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_472__RX_DCOC_RANGE_472___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_472__RX_DCOC_RES_I_472___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_472__RX_DCOC_RES_I_472___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_472__RX_DCOC_RES_Q_472___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_472__RX_DCOC_RES_Q_472___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_472___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_472___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_473 (0x005E4764) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_473___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_473___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_473__RX_DCOC_RANGE_473___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_473__RX_DCOC_RES_I_473___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_473__RX_DCOC_RES_Q_473___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_473__RX_DCOC_RANGE_473___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_473__RX_DCOC_RANGE_473___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_473__RX_DCOC_RES_I_473___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_473__RX_DCOC_RES_I_473___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_473__RX_DCOC_RES_Q_473___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_473__RX_DCOC_RES_Q_473___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_473___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_473___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_474 (0x005E4768) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_474___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_474___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_474__RX_DCOC_RANGE_474___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_474__RX_DCOC_RES_I_474___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_474__RX_DCOC_RES_Q_474___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_474__RX_DCOC_RANGE_474___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_474__RX_DCOC_RANGE_474___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_474__RX_DCOC_RES_I_474___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_474__RX_DCOC_RES_I_474___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_474__RX_DCOC_RES_Q_474___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_474__RX_DCOC_RES_Q_474___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_474___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_474___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_475 (0x005E476C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_475___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_475___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_475__RX_DCOC_RANGE_475___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_475__RX_DCOC_RES_I_475___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_475__RX_DCOC_RES_Q_475___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_475__RX_DCOC_RANGE_475___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_475__RX_DCOC_RANGE_475___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_475__RX_DCOC_RES_I_475___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_475__RX_DCOC_RES_I_475___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_475__RX_DCOC_RES_Q_475___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_475__RX_DCOC_RES_Q_475___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_475___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_475___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_476 (0x005E4770) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_476___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_476___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_476__RX_DCOC_RANGE_476___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_476__RX_DCOC_RES_I_476___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_476__RX_DCOC_RES_Q_476___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_476__RX_DCOC_RANGE_476___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_476__RX_DCOC_RANGE_476___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_476__RX_DCOC_RES_I_476___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_476__RX_DCOC_RES_I_476___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_476__RX_DCOC_RES_Q_476___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_476__RX_DCOC_RES_Q_476___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_476___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_476___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_477 (0x005E4774) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_477___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_477___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_477__RX_DCOC_RANGE_477___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_477__RX_DCOC_RES_I_477___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_477__RX_DCOC_RES_Q_477___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_477__RX_DCOC_RANGE_477___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_477__RX_DCOC_RANGE_477___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_477__RX_DCOC_RES_I_477___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_477__RX_DCOC_RES_I_477___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_477__RX_DCOC_RES_Q_477___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_477__RX_DCOC_RES_Q_477___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_477___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_477___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_478 (0x005E4778) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_478___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_478___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_478__RX_DCOC_RANGE_478___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_478__RX_DCOC_RES_I_478___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_478__RX_DCOC_RES_Q_478___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_478__RX_DCOC_RANGE_478___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_478__RX_DCOC_RANGE_478___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_478__RX_DCOC_RES_I_478___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_478__RX_DCOC_RES_I_478___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_478__RX_DCOC_RES_Q_478___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_478__RX_DCOC_RES_Q_478___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_478___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_478___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_479 (0x005E477C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_479___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_479___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_479__RX_DCOC_RANGE_479___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_479__RX_DCOC_RES_I_479___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_479__RX_DCOC_RES_Q_479___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_479__RX_DCOC_RANGE_479___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_479__RX_DCOC_RANGE_479___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_479__RX_DCOC_RES_I_479___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_479__RX_DCOC_RES_I_479___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_479__RX_DCOC_RES_Q_479___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_479__RX_DCOC_RES_Q_479___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_479___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_479___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_480 (0x005E4780) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_480___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_480___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_480__RX_DCOC_RANGE_480___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_480__RX_DCOC_RES_I_480___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_480__RX_DCOC_RES_Q_480___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_480__RX_DCOC_RANGE_480___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_480__RX_DCOC_RANGE_480___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_480__RX_DCOC_RES_I_480___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_480__RX_DCOC_RES_I_480___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_480__RX_DCOC_RES_Q_480___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_480__RX_DCOC_RES_Q_480___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_480___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_480___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_481 (0x005E4784) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_481___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_481___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_481__RX_DCOC_RANGE_481___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_481__RX_DCOC_RES_I_481___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_481__RX_DCOC_RES_Q_481___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_481__RX_DCOC_RANGE_481___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_481__RX_DCOC_RANGE_481___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_481__RX_DCOC_RES_I_481___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_481__RX_DCOC_RES_I_481___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_481__RX_DCOC_RES_Q_481___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_481__RX_DCOC_RES_Q_481___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_481___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_481___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_482 (0x005E4788) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_482___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_482___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_482__RX_DCOC_RANGE_482___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_482__RX_DCOC_RES_I_482___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_482__RX_DCOC_RES_Q_482___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_482__RX_DCOC_RANGE_482___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_482__RX_DCOC_RANGE_482___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_482__RX_DCOC_RES_I_482___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_482__RX_DCOC_RES_I_482___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_482__RX_DCOC_RES_Q_482___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_482__RX_DCOC_RES_Q_482___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_482___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_482___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_483 (0x005E478C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_483___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_483___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_483__RX_DCOC_RANGE_483___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_483__RX_DCOC_RES_I_483___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_483__RX_DCOC_RES_Q_483___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_483__RX_DCOC_RANGE_483___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_483__RX_DCOC_RANGE_483___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_483__RX_DCOC_RES_I_483___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_483__RX_DCOC_RES_I_483___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_483__RX_DCOC_RES_Q_483___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_483__RX_DCOC_RES_Q_483___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_483___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_483___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_484 (0x005E4790) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_484___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_484___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_484__RX_DCOC_RANGE_484___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_484__RX_DCOC_RES_I_484___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_484__RX_DCOC_RES_Q_484___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_484__RX_DCOC_RANGE_484___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_484__RX_DCOC_RANGE_484___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_484__RX_DCOC_RES_I_484___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_484__RX_DCOC_RES_I_484___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_484__RX_DCOC_RES_Q_484___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_484__RX_DCOC_RES_Q_484___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_484___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_484___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_485 (0x005E4794) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_485___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_485___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_485__RX_DCOC_RANGE_485___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_485__RX_DCOC_RES_I_485___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_485__RX_DCOC_RES_Q_485___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_485__RX_DCOC_RANGE_485___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_485__RX_DCOC_RANGE_485___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_485__RX_DCOC_RES_I_485___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_485__RX_DCOC_RES_I_485___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_485__RX_DCOC_RES_Q_485___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_485__RX_DCOC_RES_Q_485___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_485___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_485___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_486 (0x005E4798) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_486___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_486___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_486__RX_DCOC_RANGE_486___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_486__RX_DCOC_RES_I_486___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_486__RX_DCOC_RES_Q_486___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_486__RX_DCOC_RANGE_486___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_486__RX_DCOC_RANGE_486___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_486__RX_DCOC_RES_I_486___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_486__RX_DCOC_RES_I_486___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_486__RX_DCOC_RES_Q_486___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_486__RX_DCOC_RES_Q_486___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_486___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_486___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_487 (0x005E479C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_487___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_487___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_487__RX_DCOC_RANGE_487___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_487__RX_DCOC_RES_I_487___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_487__RX_DCOC_RES_Q_487___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_487__RX_DCOC_RANGE_487___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_487__RX_DCOC_RANGE_487___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_487__RX_DCOC_RES_I_487___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_487__RX_DCOC_RES_I_487___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_487__RX_DCOC_RES_Q_487___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_487__RX_DCOC_RES_Q_487___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_487___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_487___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_488 (0x005E47A0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_488___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_488___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_488__RX_DCOC_RANGE_488___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_488__RX_DCOC_RES_I_488___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_488__RX_DCOC_RES_Q_488___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_488__RX_DCOC_RANGE_488___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_488__RX_DCOC_RANGE_488___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_488__RX_DCOC_RES_I_488___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_488__RX_DCOC_RES_I_488___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_488__RX_DCOC_RES_Q_488___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_488__RX_DCOC_RES_Q_488___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_488___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_488___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_489 (0x005E47A4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_489___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_489___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_489__RX_DCOC_RANGE_489___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_489__RX_DCOC_RES_I_489___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_489__RX_DCOC_RES_Q_489___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_489__RX_DCOC_RANGE_489___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_489__RX_DCOC_RANGE_489___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_489__RX_DCOC_RES_I_489___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_489__RX_DCOC_RES_I_489___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_489__RX_DCOC_RES_Q_489___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_489__RX_DCOC_RES_Q_489___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_489___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_489___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_490 (0x005E47A8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_490___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_490___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_490__RX_DCOC_RANGE_490___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_490__RX_DCOC_RES_I_490___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_490__RX_DCOC_RES_Q_490___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_490__RX_DCOC_RANGE_490___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_490__RX_DCOC_RANGE_490___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_490__RX_DCOC_RES_I_490___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_490__RX_DCOC_RES_I_490___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_490__RX_DCOC_RES_Q_490___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_490__RX_DCOC_RES_Q_490___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_490___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_490___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_491 (0x005E47AC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_491___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_491___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_491__RX_DCOC_RANGE_491___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_491__RX_DCOC_RES_I_491___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_491__RX_DCOC_RES_Q_491___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_491__RX_DCOC_RANGE_491___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_491__RX_DCOC_RANGE_491___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_491__RX_DCOC_RES_I_491___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_491__RX_DCOC_RES_I_491___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_491__RX_DCOC_RES_Q_491___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_491__RX_DCOC_RES_Q_491___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_491___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_491___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_492 (0x005E47B0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_492___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_492___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_492__RX_DCOC_RANGE_492___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_492__RX_DCOC_RES_I_492___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_492__RX_DCOC_RES_Q_492___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_492__RX_DCOC_RANGE_492___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_492__RX_DCOC_RANGE_492___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_492__RX_DCOC_RES_I_492___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_492__RX_DCOC_RES_I_492___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_492__RX_DCOC_RES_Q_492___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_492__RX_DCOC_RES_Q_492___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_492___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_492___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_493 (0x005E47B4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_493___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_493___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_493__RX_DCOC_RANGE_493___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_493__RX_DCOC_RES_I_493___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_493__RX_DCOC_RES_Q_493___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_493__RX_DCOC_RANGE_493___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_493__RX_DCOC_RANGE_493___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_493__RX_DCOC_RES_I_493___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_493__RX_DCOC_RES_I_493___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_493__RX_DCOC_RES_Q_493___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_493__RX_DCOC_RES_Q_493___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_493___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_493___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_494 (0x005E47B8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_494___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_494___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_494__RX_DCOC_RANGE_494___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_494__RX_DCOC_RES_I_494___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_494__RX_DCOC_RES_Q_494___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_494__RX_DCOC_RANGE_494___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_494__RX_DCOC_RANGE_494___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_494__RX_DCOC_RES_I_494___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_494__RX_DCOC_RES_I_494___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_494__RX_DCOC_RES_Q_494___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_494__RX_DCOC_RES_Q_494___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_494___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_494___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_495 (0x005E47BC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_495___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_495___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_495__RX_DCOC_RANGE_495___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_495__RX_DCOC_RES_I_495___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_495__RX_DCOC_RES_Q_495___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_495__RX_DCOC_RANGE_495___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_495__RX_DCOC_RANGE_495___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_495__RX_DCOC_RES_I_495___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_495__RX_DCOC_RES_I_495___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_495__RX_DCOC_RES_Q_495___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_495__RX_DCOC_RES_Q_495___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_495___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_495___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_496 (0x005E47C0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_496___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_496___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_496__RX_DCOC_RANGE_496___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_496__RX_DCOC_RES_I_496___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_496__RX_DCOC_RES_Q_496___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_496__RX_DCOC_RANGE_496___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_496__RX_DCOC_RANGE_496___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_496__RX_DCOC_RES_I_496___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_496__RX_DCOC_RES_I_496___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_496__RX_DCOC_RES_Q_496___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_496__RX_DCOC_RES_Q_496___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_496___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_496___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_497 (0x005E47C4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_497___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_497___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_497__RX_DCOC_RANGE_497___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_497__RX_DCOC_RES_I_497___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_497__RX_DCOC_RES_Q_497___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_497__RX_DCOC_RANGE_497___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_497__RX_DCOC_RANGE_497___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_497__RX_DCOC_RES_I_497___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_497__RX_DCOC_RES_I_497___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_497__RX_DCOC_RES_Q_497___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_497__RX_DCOC_RES_Q_497___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_497___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_497___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_498 (0x005E47C8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_498___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_498___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_498__RX_DCOC_RANGE_498___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_498__RX_DCOC_RES_I_498___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_498__RX_DCOC_RES_Q_498___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_498__RX_DCOC_RANGE_498___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_498__RX_DCOC_RANGE_498___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_498__RX_DCOC_RES_I_498___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_498__RX_DCOC_RES_I_498___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_498__RX_DCOC_RES_Q_498___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_498__RX_DCOC_RES_Q_498___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_498___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_498___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_499 (0x005E47CC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_499___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_499___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_499__RX_DCOC_RANGE_499___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_499__RX_DCOC_RES_I_499___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_499__RX_DCOC_RES_Q_499___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_499__RX_DCOC_RANGE_499___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_499__RX_DCOC_RANGE_499___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_499__RX_DCOC_RES_I_499___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_499__RX_DCOC_RES_I_499___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_499__RX_DCOC_RES_Q_499___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_499__RX_DCOC_RES_Q_499___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_499___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_499___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_500 (0x005E47D0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_500___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_500___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_500__RX_DCOC_RANGE_500___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_500__RX_DCOC_RES_I_500___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_500__RX_DCOC_RES_Q_500___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_500__RX_DCOC_RANGE_500___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_500__RX_DCOC_RANGE_500___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_500__RX_DCOC_RES_I_500___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_500__RX_DCOC_RES_I_500___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_500__RX_DCOC_RES_Q_500___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_500__RX_DCOC_RES_Q_500___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_500___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_500___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_501 (0x005E47D4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_501___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_501___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_501__RX_DCOC_RANGE_501___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_501__RX_DCOC_RES_I_501___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_501__RX_DCOC_RES_Q_501___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_501__RX_DCOC_RANGE_501___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_501__RX_DCOC_RANGE_501___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_501__RX_DCOC_RES_I_501___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_501__RX_DCOC_RES_I_501___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_501__RX_DCOC_RES_Q_501___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_501__RX_DCOC_RES_Q_501___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_501___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_501___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_502 (0x005E47D8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_502___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_502___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_502__RX_DCOC_RANGE_502___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_502__RX_DCOC_RES_I_502___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_502__RX_DCOC_RES_Q_502___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_502__RX_DCOC_RANGE_502___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_502__RX_DCOC_RANGE_502___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_502__RX_DCOC_RES_I_502___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_502__RX_DCOC_RES_I_502___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_502__RX_DCOC_RES_Q_502___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_502__RX_DCOC_RES_Q_502___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_502___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_502___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_503 (0x005E47DC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_503___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_503___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_503__RX_DCOC_RANGE_503___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_503__RX_DCOC_RES_I_503___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_503__RX_DCOC_RES_Q_503___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_503__RX_DCOC_RANGE_503___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_503__RX_DCOC_RANGE_503___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_503__RX_DCOC_RES_I_503___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_503__RX_DCOC_RES_I_503___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_503__RX_DCOC_RES_Q_503___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_503__RX_DCOC_RES_Q_503___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_503___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_503___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_504 (0x005E47E0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_504___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_504___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_504__RX_DCOC_RANGE_504___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_504__RX_DCOC_RES_I_504___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_504__RX_DCOC_RES_Q_504___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_504__RX_DCOC_RANGE_504___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_504__RX_DCOC_RANGE_504___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_504__RX_DCOC_RES_I_504___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_504__RX_DCOC_RES_I_504___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_504__RX_DCOC_RES_Q_504___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_504__RX_DCOC_RES_Q_504___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_504___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_504___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_505 (0x005E47E4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_505___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_505___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_505__RX_DCOC_RANGE_505___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_505__RX_DCOC_RES_I_505___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_505__RX_DCOC_RES_Q_505___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_505__RX_DCOC_RANGE_505___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_505__RX_DCOC_RANGE_505___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_505__RX_DCOC_RES_I_505___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_505__RX_DCOC_RES_I_505___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_505__RX_DCOC_RES_Q_505___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_505__RX_DCOC_RES_Q_505___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_505___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_505___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_506 (0x005E47E8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_506___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_506___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_506__RX_DCOC_RANGE_506___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_506__RX_DCOC_RES_I_506___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_506__RX_DCOC_RES_Q_506___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_506__RX_DCOC_RANGE_506___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_506__RX_DCOC_RANGE_506___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_506__RX_DCOC_RES_I_506___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_506__RX_DCOC_RES_I_506___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_506__RX_DCOC_RES_Q_506___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_506__RX_DCOC_RES_Q_506___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_506___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_506___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_507 (0x005E47EC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_507___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_507___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_507__RX_DCOC_RANGE_507___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_507__RX_DCOC_RES_I_507___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_507__RX_DCOC_RES_Q_507___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_507__RX_DCOC_RANGE_507___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_507__RX_DCOC_RANGE_507___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_507__RX_DCOC_RES_I_507___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_507__RX_DCOC_RES_I_507___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_507__RX_DCOC_RES_Q_507___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_507__RX_DCOC_RES_Q_507___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_507___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_507___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_508 (0x005E47F0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_508___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_508___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_508__RX_DCOC_RANGE_508___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_508__RX_DCOC_RES_I_508___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_508__RX_DCOC_RES_Q_508___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_508__RX_DCOC_RANGE_508___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_508__RX_DCOC_RANGE_508___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_508__RX_DCOC_RES_I_508___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_508__RX_DCOC_RES_I_508___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_508__RX_DCOC_RES_Q_508___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_508__RX_DCOC_RES_Q_508___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_508___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_508___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_509 (0x005E47F4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_509___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_509___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_509__RX_DCOC_RANGE_509___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_509__RX_DCOC_RES_I_509___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_509__RX_DCOC_RES_Q_509___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_509__RX_DCOC_RANGE_509___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_509__RX_DCOC_RANGE_509___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_509__RX_DCOC_RES_I_509___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_509__RX_DCOC_RES_I_509___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_509__RX_DCOC_RES_Q_509___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_509__RX_DCOC_RES_Q_509___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_509___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_509___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_510 (0x005E47F8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_510___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_510___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_510__RX_DCOC_RANGE_510___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_510__RX_DCOC_RES_I_510___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_510__RX_DCOC_RES_Q_510___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_510__RX_DCOC_RANGE_510___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_510__RX_DCOC_RANGE_510___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_510__RX_DCOC_RES_I_510___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_510__RX_DCOC_RES_I_510___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_510__RX_DCOC_RES_Q_510___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_510__RX_DCOC_RES_Q_510___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_510___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_510___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_511 (0x005E47FC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_511___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_511___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_511__RX_DCOC_RANGE_511___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_511__RX_DCOC_RES_I_511___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_511__RX_DCOC_RES_Q_511___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_511__RX_DCOC_RANGE_511___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_511__RX_DCOC_RANGE_511___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_511__RX_DCOC_RES_I_511___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_511__RX_DCOC_RES_I_511___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_511__RX_DCOC_RES_Q_511___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_511__RX_DCOC_RES_Q_511___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_511___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_511___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_512 (0x005E4800) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_512___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_512___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_512__RX_DCOC_RANGE_512___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_512__RX_DCOC_RES_I_512___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_512__RX_DCOC_RES_Q_512___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_512__RX_DCOC_RANGE_512___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_512__RX_DCOC_RANGE_512___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_512__RX_DCOC_RES_I_512___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_512__RX_DCOC_RES_I_512___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_512__RX_DCOC_RES_Q_512___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_512__RX_DCOC_RES_Q_512___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_512___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_512___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_513 (0x005E4804) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_513___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_513___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_513__RX_DCOC_RANGE_513___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_513__RX_DCOC_RES_I_513___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_513__RX_DCOC_RES_Q_513___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_513__RX_DCOC_RANGE_513___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_513__RX_DCOC_RANGE_513___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_513__RX_DCOC_RES_I_513___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_513__RX_DCOC_RES_I_513___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_513__RX_DCOC_RES_Q_513___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_513__RX_DCOC_RES_Q_513___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_513___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_513___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_514 (0x005E4808) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_514___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_514___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_514__RX_DCOC_RANGE_514___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_514__RX_DCOC_RES_I_514___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_514__RX_DCOC_RES_Q_514___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_514__RX_DCOC_RANGE_514___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_514__RX_DCOC_RANGE_514___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_514__RX_DCOC_RES_I_514___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_514__RX_DCOC_RES_I_514___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_514__RX_DCOC_RES_Q_514___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_514__RX_DCOC_RES_Q_514___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_514___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_514___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_515 (0x005E480C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_515___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_515___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_515__RX_DCOC_RANGE_515___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_515__RX_DCOC_RES_I_515___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_515__RX_DCOC_RES_Q_515___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_515__RX_DCOC_RANGE_515___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_515__RX_DCOC_RANGE_515___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_515__RX_DCOC_RES_I_515___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_515__RX_DCOC_RES_I_515___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_515__RX_DCOC_RES_Q_515___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_515__RX_DCOC_RES_Q_515___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_515___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_515___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_516 (0x005E4810) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_516___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_516___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_516__RX_DCOC_RANGE_516___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_516__RX_DCOC_RES_I_516___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_516__RX_DCOC_RES_Q_516___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_516__RX_DCOC_RANGE_516___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_516__RX_DCOC_RANGE_516___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_516__RX_DCOC_RES_I_516___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_516__RX_DCOC_RES_I_516___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_516__RX_DCOC_RES_Q_516___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_516__RX_DCOC_RES_Q_516___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_516___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_516___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_517 (0x005E4814) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_517___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_517___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_517__RX_DCOC_RANGE_517___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_517__RX_DCOC_RES_I_517___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_517__RX_DCOC_RES_Q_517___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_517__RX_DCOC_RANGE_517___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_517__RX_DCOC_RANGE_517___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_517__RX_DCOC_RES_I_517___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_517__RX_DCOC_RES_I_517___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_517__RX_DCOC_RES_Q_517___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_517__RX_DCOC_RES_Q_517___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_517___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_517___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_518 (0x005E4818) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_518___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_518___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_518__RX_DCOC_RANGE_518___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_518__RX_DCOC_RES_I_518___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_518__RX_DCOC_RES_Q_518___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_518__RX_DCOC_RANGE_518___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_518__RX_DCOC_RANGE_518___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_518__RX_DCOC_RES_I_518___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_518__RX_DCOC_RES_I_518___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_518__RX_DCOC_RES_Q_518___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_518__RX_DCOC_RES_Q_518___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_518___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_518___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_519 (0x005E481C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_519___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_519___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_519__RX_DCOC_RANGE_519___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_519__RX_DCOC_RES_I_519___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_519__RX_DCOC_RES_Q_519___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_519__RX_DCOC_RANGE_519___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_519__RX_DCOC_RANGE_519___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_519__RX_DCOC_RES_I_519___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_519__RX_DCOC_RES_I_519___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_519__RX_DCOC_RES_Q_519___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_519__RX_DCOC_RES_Q_519___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_519___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_519___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_520 (0x005E4820) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_520___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_520___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_520__RX_DCOC_RANGE_520___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_520__RX_DCOC_RES_I_520___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_520__RX_DCOC_RES_Q_520___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_520__RX_DCOC_RANGE_520___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_520__RX_DCOC_RANGE_520___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_520__RX_DCOC_RES_I_520___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_520__RX_DCOC_RES_I_520___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_520__RX_DCOC_RES_Q_520___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_520__RX_DCOC_RES_Q_520___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_520___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_520___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_521 (0x005E4824) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_521___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_521___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_521__RX_DCOC_RANGE_521___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_521__RX_DCOC_RES_I_521___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_521__RX_DCOC_RES_Q_521___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_521__RX_DCOC_RANGE_521___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_521__RX_DCOC_RANGE_521___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_521__RX_DCOC_RES_I_521___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_521__RX_DCOC_RES_I_521___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_521__RX_DCOC_RES_Q_521___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_521__RX_DCOC_RES_Q_521___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_521___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_521___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_522 (0x005E4828) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_522___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_522___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_522__RX_DCOC_RANGE_522___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_522__RX_DCOC_RES_I_522___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_522__RX_DCOC_RES_Q_522___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_522__RX_DCOC_RANGE_522___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_522__RX_DCOC_RANGE_522___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_522__RX_DCOC_RES_I_522___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_522__RX_DCOC_RES_I_522___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_522__RX_DCOC_RES_Q_522___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_522__RX_DCOC_RES_Q_522___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_522___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_522___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_523 (0x005E482C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_523___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_523___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_523__RX_DCOC_RANGE_523___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_523__RX_DCOC_RES_I_523___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_523__RX_DCOC_RES_Q_523___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_523__RX_DCOC_RANGE_523___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_523__RX_DCOC_RANGE_523___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_523__RX_DCOC_RES_I_523___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_523__RX_DCOC_RES_I_523___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_523__RX_DCOC_RES_Q_523___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_523__RX_DCOC_RES_Q_523___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_523___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_523___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_524 (0x005E4830) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_524___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_524___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_524__RX_DCOC_RANGE_524___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_524__RX_DCOC_RES_I_524___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_524__RX_DCOC_RES_Q_524___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_524__RX_DCOC_RANGE_524___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_524__RX_DCOC_RANGE_524___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_524__RX_DCOC_RES_I_524___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_524__RX_DCOC_RES_I_524___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_524__RX_DCOC_RES_Q_524___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_524__RX_DCOC_RES_Q_524___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_524___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_524___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_525 (0x005E4834) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_525___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_525___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_525__RX_DCOC_RANGE_525___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_525__RX_DCOC_RES_I_525___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_525__RX_DCOC_RES_Q_525___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_525__RX_DCOC_RANGE_525___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_525__RX_DCOC_RANGE_525___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_525__RX_DCOC_RES_I_525___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_525__RX_DCOC_RES_I_525___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_525__RX_DCOC_RES_Q_525___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_525__RX_DCOC_RES_Q_525___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_525___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_525___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_526 (0x005E4838) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_526___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_526___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_526__RX_DCOC_RANGE_526___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_526__RX_DCOC_RES_I_526___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_526__RX_DCOC_RES_Q_526___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_526__RX_DCOC_RANGE_526___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_526__RX_DCOC_RANGE_526___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_526__RX_DCOC_RES_I_526___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_526__RX_DCOC_RES_I_526___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_526__RX_DCOC_RES_Q_526___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_526__RX_DCOC_RES_Q_526___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_526___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_526___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_527 (0x005E483C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_527___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_527___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_527__RX_DCOC_RANGE_527___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_527__RX_DCOC_RES_I_527___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_527__RX_DCOC_RES_Q_527___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_527__RX_DCOC_RANGE_527___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_527__RX_DCOC_RANGE_527___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_527__RX_DCOC_RES_I_527___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_527__RX_DCOC_RES_I_527___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_527__RX_DCOC_RES_Q_527___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_527__RX_DCOC_RES_Q_527___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_527___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_527___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_528 (0x005E4840) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_528___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_528___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_528__RX_DCOC_RANGE_528___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_528__RX_DCOC_RES_I_528___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_528__RX_DCOC_RES_Q_528___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_528__RX_DCOC_RANGE_528___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_528__RX_DCOC_RANGE_528___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_528__RX_DCOC_RES_I_528___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_528__RX_DCOC_RES_I_528___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_528__RX_DCOC_RES_Q_528___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_528__RX_DCOC_RES_Q_528___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_528___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_528___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_529 (0x005E4844) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_529___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_529___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_529__RX_DCOC_RANGE_529___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_529__RX_DCOC_RES_I_529___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_529__RX_DCOC_RES_Q_529___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_529__RX_DCOC_RANGE_529___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_529__RX_DCOC_RANGE_529___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_529__RX_DCOC_RES_I_529___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_529__RX_DCOC_RES_I_529___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_529__RX_DCOC_RES_Q_529___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_529__RX_DCOC_RES_Q_529___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_529___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_529___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_530 (0x005E4848) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_530___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_530___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_530__RX_DCOC_RANGE_530___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_530__RX_DCOC_RES_I_530___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_530__RX_DCOC_RES_Q_530___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_530__RX_DCOC_RANGE_530___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_530__RX_DCOC_RANGE_530___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_530__RX_DCOC_RES_I_530___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_530__RX_DCOC_RES_I_530___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_530__RX_DCOC_RES_Q_530___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_530__RX_DCOC_RES_Q_530___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_530___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_530___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_531 (0x005E484C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_531___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_531___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_531__RX_DCOC_RANGE_531___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_531__RX_DCOC_RES_I_531___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_531__RX_DCOC_RES_Q_531___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_531__RX_DCOC_RANGE_531___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_531__RX_DCOC_RANGE_531___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_531__RX_DCOC_RES_I_531___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_531__RX_DCOC_RES_I_531___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_531__RX_DCOC_RES_Q_531___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_531__RX_DCOC_RES_Q_531___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_531___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_531___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_532 (0x005E4850) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_532___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_532___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_532__RX_DCOC_RANGE_532___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_532__RX_DCOC_RES_I_532___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_532__RX_DCOC_RES_Q_532___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_532__RX_DCOC_RANGE_532___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_532__RX_DCOC_RANGE_532___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_532__RX_DCOC_RES_I_532___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_532__RX_DCOC_RES_I_532___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_532__RX_DCOC_RES_Q_532___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_532__RX_DCOC_RES_Q_532___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_532___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_532___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_533 (0x005E4854) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_533___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_533___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_533__RX_DCOC_RANGE_533___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_533__RX_DCOC_RES_I_533___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_533__RX_DCOC_RES_Q_533___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_533__RX_DCOC_RANGE_533___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_533__RX_DCOC_RANGE_533___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_533__RX_DCOC_RES_I_533___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_533__RX_DCOC_RES_I_533___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_533__RX_DCOC_RES_Q_533___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_533__RX_DCOC_RES_Q_533___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_533___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_533___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_534 (0x005E4858) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_534___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_534___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_534__RX_DCOC_RANGE_534___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_534__RX_DCOC_RES_I_534___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_534__RX_DCOC_RES_Q_534___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_534__RX_DCOC_RANGE_534___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_534__RX_DCOC_RANGE_534___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_534__RX_DCOC_RES_I_534___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_534__RX_DCOC_RES_I_534___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_534__RX_DCOC_RES_Q_534___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_534__RX_DCOC_RES_Q_534___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_534___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_534___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_535 (0x005E485C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_535___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_535___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_535__RX_DCOC_RANGE_535___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_535__RX_DCOC_RES_I_535___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_535__RX_DCOC_RES_Q_535___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_535__RX_DCOC_RANGE_535___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_535__RX_DCOC_RANGE_535___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_535__RX_DCOC_RES_I_535___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_535__RX_DCOC_RES_I_535___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_535__RX_DCOC_RES_Q_535___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_535__RX_DCOC_RES_Q_535___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_535___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_535___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_536 (0x005E4860) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_536___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_536___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_536__RX_DCOC_RANGE_536___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_536__RX_DCOC_RES_I_536___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_536__RX_DCOC_RES_Q_536___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_536__RX_DCOC_RANGE_536___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_536__RX_DCOC_RANGE_536___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_536__RX_DCOC_RES_I_536___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_536__RX_DCOC_RES_I_536___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_536__RX_DCOC_RES_Q_536___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_536__RX_DCOC_RES_Q_536___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_536___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_536___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_537 (0x005E4864) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_537___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_537___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_537__RX_DCOC_RANGE_537___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_537__RX_DCOC_RES_I_537___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_537__RX_DCOC_RES_Q_537___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_537__RX_DCOC_RANGE_537___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_537__RX_DCOC_RANGE_537___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_537__RX_DCOC_RES_I_537___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_537__RX_DCOC_RES_I_537___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_537__RX_DCOC_RES_Q_537___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_537__RX_DCOC_RES_Q_537___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_537___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_537___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_538 (0x005E4868) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_538___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_538___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_538__RX_DCOC_RANGE_538___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_538__RX_DCOC_RES_I_538___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_538__RX_DCOC_RES_Q_538___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_538__RX_DCOC_RANGE_538___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_538__RX_DCOC_RANGE_538___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_538__RX_DCOC_RES_I_538___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_538__RX_DCOC_RES_I_538___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_538__RX_DCOC_RES_Q_538___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_538__RX_DCOC_RES_Q_538___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_538___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_538___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_539 (0x005E486C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_539___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_539___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_539__RX_DCOC_RANGE_539___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_539__RX_DCOC_RES_I_539___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_539__RX_DCOC_RES_Q_539___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_539__RX_DCOC_RANGE_539___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_539__RX_DCOC_RANGE_539___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_539__RX_DCOC_RES_I_539___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_539__RX_DCOC_RES_I_539___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_539__RX_DCOC_RES_Q_539___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_539__RX_DCOC_RES_Q_539___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_539___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_539___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_540 (0x005E4870) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_540___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_540___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_540__RX_DCOC_RANGE_540___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_540__RX_DCOC_RES_I_540___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_540__RX_DCOC_RES_Q_540___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_540__RX_DCOC_RANGE_540___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_540__RX_DCOC_RANGE_540___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_540__RX_DCOC_RES_I_540___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_540__RX_DCOC_RES_I_540___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_540__RX_DCOC_RES_Q_540___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_540__RX_DCOC_RES_Q_540___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_540___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_540___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_541 (0x005E4874) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_541___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_541___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_541__RX_DCOC_RANGE_541___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_541__RX_DCOC_RES_I_541___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_541__RX_DCOC_RES_Q_541___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_541__RX_DCOC_RANGE_541___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_541__RX_DCOC_RANGE_541___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_541__RX_DCOC_RES_I_541___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_541__RX_DCOC_RES_I_541___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_541__RX_DCOC_RES_Q_541___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_541__RX_DCOC_RES_Q_541___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_541___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_541___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_542 (0x005E4878) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_542___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_542___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_542__RX_DCOC_RANGE_542___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_542__RX_DCOC_RES_I_542___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_542__RX_DCOC_RES_Q_542___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_542__RX_DCOC_RANGE_542___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_542__RX_DCOC_RANGE_542___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_542__RX_DCOC_RES_I_542___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_542__RX_DCOC_RES_I_542___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_542__RX_DCOC_RES_Q_542___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_542__RX_DCOC_RES_Q_542___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_542___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_542___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_543 (0x005E487C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_543___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_543___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_543__RX_DCOC_RANGE_543___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_543__RX_DCOC_RES_I_543___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_543__RX_DCOC_RES_Q_543___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_543__RX_DCOC_RANGE_543___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_543__RX_DCOC_RANGE_543___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_543__RX_DCOC_RES_I_543___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_543__RX_DCOC_RES_I_543___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_543__RX_DCOC_RES_Q_543___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_543__RX_DCOC_RES_Q_543___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_543___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_543___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_544 (0x005E4880) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_544___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_544___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_544__RX_DCOC_RANGE_544___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_544__RX_DCOC_RES_I_544___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_544__RX_DCOC_RES_Q_544___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_544__RX_DCOC_RANGE_544___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_544__RX_DCOC_RANGE_544___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_544__RX_DCOC_RES_I_544___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_544__RX_DCOC_RES_I_544___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_544__RX_DCOC_RES_Q_544___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_544__RX_DCOC_RES_Q_544___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_544___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_544___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_545 (0x005E4884) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_545___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_545___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_545__RX_DCOC_RANGE_545___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_545__RX_DCOC_RES_I_545___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_545__RX_DCOC_RES_Q_545___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_545__RX_DCOC_RANGE_545___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_545__RX_DCOC_RANGE_545___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_545__RX_DCOC_RES_I_545___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_545__RX_DCOC_RES_I_545___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_545__RX_DCOC_RES_Q_545___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_545__RX_DCOC_RES_Q_545___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_545___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_545___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_546 (0x005E4888) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_546___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_546___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_546__RX_DCOC_RANGE_546___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_546__RX_DCOC_RES_I_546___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_546__RX_DCOC_RES_Q_546___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_546__RX_DCOC_RANGE_546___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_546__RX_DCOC_RANGE_546___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_546__RX_DCOC_RES_I_546___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_546__RX_DCOC_RES_I_546___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_546__RX_DCOC_RES_Q_546___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_546__RX_DCOC_RES_Q_546___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_546___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_546___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_547 (0x005E488C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_547___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_547___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_547__RX_DCOC_RANGE_547___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_547__RX_DCOC_RES_I_547___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_547__RX_DCOC_RES_Q_547___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_547__RX_DCOC_RANGE_547___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_547__RX_DCOC_RANGE_547___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_547__RX_DCOC_RES_I_547___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_547__RX_DCOC_RES_I_547___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_547__RX_DCOC_RES_Q_547___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_547__RX_DCOC_RES_Q_547___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_547___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_547___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_548 (0x005E4890) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_548___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_548___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_548__RX_DCOC_RANGE_548___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_548__RX_DCOC_RES_I_548___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_548__RX_DCOC_RES_Q_548___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_548__RX_DCOC_RANGE_548___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_548__RX_DCOC_RANGE_548___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_548__RX_DCOC_RES_I_548___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_548__RX_DCOC_RES_I_548___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_548__RX_DCOC_RES_Q_548___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_548__RX_DCOC_RES_Q_548___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_548___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_548___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_549 (0x005E4894) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_549___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_549___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_549__RX_DCOC_RANGE_549___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_549__RX_DCOC_RES_I_549___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_549__RX_DCOC_RES_Q_549___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_549__RX_DCOC_RANGE_549___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_549__RX_DCOC_RANGE_549___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_549__RX_DCOC_RES_I_549___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_549__RX_DCOC_RES_I_549___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_549__RX_DCOC_RES_Q_549___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_549__RX_DCOC_RES_Q_549___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_549___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_549___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_550 (0x005E4898) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_550___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_550___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_550__RX_DCOC_RANGE_550___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_550__RX_DCOC_RES_I_550___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_550__RX_DCOC_RES_Q_550___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_550__RX_DCOC_RANGE_550___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_550__RX_DCOC_RANGE_550___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_550__RX_DCOC_RES_I_550___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_550__RX_DCOC_RES_I_550___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_550__RX_DCOC_RES_Q_550___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_550__RX_DCOC_RES_Q_550___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_550___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_550___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_551 (0x005E489C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_551___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_551___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_551__RX_DCOC_RANGE_551___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_551__RX_DCOC_RES_I_551___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_551__RX_DCOC_RES_Q_551___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_551__RX_DCOC_RANGE_551___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_551__RX_DCOC_RANGE_551___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_551__RX_DCOC_RES_I_551___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_551__RX_DCOC_RES_I_551___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_551__RX_DCOC_RES_Q_551___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_551__RX_DCOC_RES_Q_551___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_551___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_551___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_552 (0x005E48A0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_552___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_552___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_552__RX_DCOC_RANGE_552___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_552__RX_DCOC_RES_I_552___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_552__RX_DCOC_RES_Q_552___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_552__RX_DCOC_RANGE_552___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_552__RX_DCOC_RANGE_552___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_552__RX_DCOC_RES_I_552___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_552__RX_DCOC_RES_I_552___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_552__RX_DCOC_RES_Q_552___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_552__RX_DCOC_RES_Q_552___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_552___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_552___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_553 (0x005E48A4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_553___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_553___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_553__RX_DCOC_RANGE_553___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_553__RX_DCOC_RES_I_553___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_553__RX_DCOC_RES_Q_553___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_553__RX_DCOC_RANGE_553___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_553__RX_DCOC_RANGE_553___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_553__RX_DCOC_RES_I_553___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_553__RX_DCOC_RES_I_553___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_553__RX_DCOC_RES_Q_553___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_553__RX_DCOC_RES_Q_553___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_553___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_553___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_554 (0x005E48A8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_554___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_554___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_554__RX_DCOC_RANGE_554___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_554__RX_DCOC_RES_I_554___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_554__RX_DCOC_RES_Q_554___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_554__RX_DCOC_RANGE_554___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_554__RX_DCOC_RANGE_554___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_554__RX_DCOC_RES_I_554___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_554__RX_DCOC_RES_I_554___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_554__RX_DCOC_RES_Q_554___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_554__RX_DCOC_RES_Q_554___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_554___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_554___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_555 (0x005E48AC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_555___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_555___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_555__RX_DCOC_RANGE_555___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_555__RX_DCOC_RES_I_555___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_555__RX_DCOC_RES_Q_555___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_555__RX_DCOC_RANGE_555___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_555__RX_DCOC_RANGE_555___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_555__RX_DCOC_RES_I_555___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_555__RX_DCOC_RES_I_555___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_555__RX_DCOC_RES_Q_555___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_555__RX_DCOC_RES_Q_555___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_555___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_555___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_556 (0x005E48B0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_556___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_556___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_556__RX_DCOC_RANGE_556___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_556__RX_DCOC_RES_I_556___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_556__RX_DCOC_RES_Q_556___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_556__RX_DCOC_RANGE_556___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_556__RX_DCOC_RANGE_556___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_556__RX_DCOC_RES_I_556___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_556__RX_DCOC_RES_I_556___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_556__RX_DCOC_RES_Q_556___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_556__RX_DCOC_RES_Q_556___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_556___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_556___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_557 (0x005E48B4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_557___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_557___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_557__RX_DCOC_RANGE_557___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_557__RX_DCOC_RES_I_557___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_557__RX_DCOC_RES_Q_557___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_557__RX_DCOC_RANGE_557___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_557__RX_DCOC_RANGE_557___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_557__RX_DCOC_RES_I_557___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_557__RX_DCOC_RES_I_557___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_557__RX_DCOC_RES_Q_557___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_557__RX_DCOC_RES_Q_557___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_557___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_557___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_558 (0x005E48B8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_558___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_558___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_558__RX_DCOC_RANGE_558___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_558__RX_DCOC_RES_I_558___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_558__RX_DCOC_RES_Q_558___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_558__RX_DCOC_RANGE_558___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_558__RX_DCOC_RANGE_558___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_558__RX_DCOC_RES_I_558___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_558__RX_DCOC_RES_I_558___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_558__RX_DCOC_RES_Q_558___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_558__RX_DCOC_RES_Q_558___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_558___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_558___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_559 (0x005E48BC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_559___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_559___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_559__RX_DCOC_RANGE_559___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_559__RX_DCOC_RES_I_559___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_559__RX_DCOC_RES_Q_559___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_559__RX_DCOC_RANGE_559___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_559__RX_DCOC_RANGE_559___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_559__RX_DCOC_RES_I_559___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_559__RX_DCOC_RES_I_559___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_559__RX_DCOC_RES_Q_559___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_559__RX_DCOC_RES_Q_559___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_559___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_559___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_560 (0x005E48C0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_560___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_560___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_560__RX_DCOC_RANGE_560___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_560__RX_DCOC_RES_I_560___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_560__RX_DCOC_RES_Q_560___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_560__RX_DCOC_RANGE_560___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_560__RX_DCOC_RANGE_560___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_560__RX_DCOC_RES_I_560___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_560__RX_DCOC_RES_I_560___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_560__RX_DCOC_RES_Q_560___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_560__RX_DCOC_RES_Q_560___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_560___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_560___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_561 (0x005E48C4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_561___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_561___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_561__RX_DCOC_RANGE_561___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_561__RX_DCOC_RES_I_561___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_561__RX_DCOC_RES_Q_561___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_561__RX_DCOC_RANGE_561___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_561__RX_DCOC_RANGE_561___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_561__RX_DCOC_RES_I_561___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_561__RX_DCOC_RES_I_561___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_561__RX_DCOC_RES_Q_561___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_561__RX_DCOC_RES_Q_561___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_561___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_561___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_562 (0x005E48C8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_562___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_562___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_562__RX_DCOC_RANGE_562___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_562__RX_DCOC_RES_I_562___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_562__RX_DCOC_RES_Q_562___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_562__RX_DCOC_RANGE_562___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_562__RX_DCOC_RANGE_562___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_562__RX_DCOC_RES_I_562___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_562__RX_DCOC_RES_I_562___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_562__RX_DCOC_RES_Q_562___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_562__RX_DCOC_RES_Q_562___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_562___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_562___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_563 (0x005E48CC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_563___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_563___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_563__RX_DCOC_RANGE_563___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_563__RX_DCOC_RES_I_563___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_563__RX_DCOC_RES_Q_563___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_563__RX_DCOC_RANGE_563___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_563__RX_DCOC_RANGE_563___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_563__RX_DCOC_RES_I_563___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_563__RX_DCOC_RES_I_563___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_563__RX_DCOC_RES_Q_563___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_563__RX_DCOC_RES_Q_563___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_563___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_563___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_564 (0x005E48D0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_564___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_564___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_564__RX_DCOC_RANGE_564___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_564__RX_DCOC_RES_I_564___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_564__RX_DCOC_RES_Q_564___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_564__RX_DCOC_RANGE_564___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_564__RX_DCOC_RANGE_564___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_564__RX_DCOC_RES_I_564___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_564__RX_DCOC_RES_I_564___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_564__RX_DCOC_RES_Q_564___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_564__RX_DCOC_RES_Q_564___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_564___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_564___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_565 (0x005E48D4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_565___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_565___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_565__RX_DCOC_RANGE_565___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_565__RX_DCOC_RES_I_565___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_565__RX_DCOC_RES_Q_565___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_565__RX_DCOC_RANGE_565___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_565__RX_DCOC_RANGE_565___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_565__RX_DCOC_RES_I_565___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_565__RX_DCOC_RES_I_565___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_565__RX_DCOC_RES_Q_565___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_565__RX_DCOC_RES_Q_565___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_565___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_565___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_566 (0x005E48D8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_566___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_566___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_566__RX_DCOC_RANGE_566___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_566__RX_DCOC_RES_I_566___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_566__RX_DCOC_RES_Q_566___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_566__RX_DCOC_RANGE_566___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_566__RX_DCOC_RANGE_566___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_566__RX_DCOC_RES_I_566___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_566__RX_DCOC_RES_I_566___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_566__RX_DCOC_RES_Q_566___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_566__RX_DCOC_RES_Q_566___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_566___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_566___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_567 (0x005E48DC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_567___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_567___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_567__RX_DCOC_RANGE_567___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_567__RX_DCOC_RES_I_567___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_567__RX_DCOC_RES_Q_567___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_567__RX_DCOC_RANGE_567___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_567__RX_DCOC_RANGE_567___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_567__RX_DCOC_RES_I_567___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_567__RX_DCOC_RES_I_567___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_567__RX_DCOC_RES_Q_567___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_567__RX_DCOC_RES_Q_567___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_567___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_567___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_568 (0x005E48E0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_568___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_568___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_568__RX_DCOC_RANGE_568___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_568__RX_DCOC_RES_I_568___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_568__RX_DCOC_RES_Q_568___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_568__RX_DCOC_RANGE_568___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_568__RX_DCOC_RANGE_568___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_568__RX_DCOC_RES_I_568___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_568__RX_DCOC_RES_I_568___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_568__RX_DCOC_RES_Q_568___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_568__RX_DCOC_RES_Q_568___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_568___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_568___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_569 (0x005E48E4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_569___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_569___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_569__RX_DCOC_RANGE_569___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_569__RX_DCOC_RES_I_569___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_569__RX_DCOC_RES_Q_569___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_569__RX_DCOC_RANGE_569___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_569__RX_DCOC_RANGE_569___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_569__RX_DCOC_RES_I_569___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_569__RX_DCOC_RES_I_569___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_569__RX_DCOC_RES_Q_569___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_569__RX_DCOC_RES_Q_569___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_569___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_569___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_570 (0x005E48E8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_570___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_570___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_570__RX_DCOC_RANGE_570___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_570__RX_DCOC_RES_I_570___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_570__RX_DCOC_RES_Q_570___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_570__RX_DCOC_RANGE_570___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_570__RX_DCOC_RANGE_570___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_570__RX_DCOC_RES_I_570___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_570__RX_DCOC_RES_I_570___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_570__RX_DCOC_RES_Q_570___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_570__RX_DCOC_RES_Q_570___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_570___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_570___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_571 (0x005E48EC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_571___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_571___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_571__RX_DCOC_RANGE_571___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_571__RX_DCOC_RES_I_571___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_571__RX_DCOC_RES_Q_571___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_571__RX_DCOC_RANGE_571___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_571__RX_DCOC_RANGE_571___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_571__RX_DCOC_RES_I_571___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_571__RX_DCOC_RES_I_571___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_571__RX_DCOC_RES_Q_571___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_571__RX_DCOC_RES_Q_571___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_571___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_571___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_572 (0x005E48F0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_572___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_572___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_572__RX_DCOC_RANGE_572___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_572__RX_DCOC_RES_I_572___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_572__RX_DCOC_RES_Q_572___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_572__RX_DCOC_RANGE_572___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_572__RX_DCOC_RANGE_572___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_572__RX_DCOC_RES_I_572___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_572__RX_DCOC_RES_I_572___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_572__RX_DCOC_RES_Q_572___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_572__RX_DCOC_RES_Q_572___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_572___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_572___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_573 (0x005E48F4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_573___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_573___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_573__RX_DCOC_RANGE_573___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_573__RX_DCOC_RES_I_573___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_573__RX_DCOC_RES_Q_573___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_573__RX_DCOC_RANGE_573___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_573__RX_DCOC_RANGE_573___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_573__RX_DCOC_RES_I_573___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_573__RX_DCOC_RES_I_573___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_573__RX_DCOC_RES_Q_573___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_573__RX_DCOC_RES_Q_573___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_573___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_573___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_574 (0x005E48F8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_574___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_574___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_574__RX_DCOC_RANGE_574___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_574__RX_DCOC_RES_I_574___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_574__RX_DCOC_RES_Q_574___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_574__RX_DCOC_RANGE_574___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_574__RX_DCOC_RANGE_574___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_574__RX_DCOC_RES_I_574___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_574__RX_DCOC_RES_I_574___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_574__RX_DCOC_RES_Q_574___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_574__RX_DCOC_RES_Q_574___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_574___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_574___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_575 (0x005E48FC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_575___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_575___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_575__RX_DCOC_RANGE_575___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_575__RX_DCOC_RES_I_575___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_575__RX_DCOC_RES_Q_575___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_575__RX_DCOC_RANGE_575___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_575__RX_DCOC_RANGE_575___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_575__RX_DCOC_RES_I_575___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_575__RX_DCOC_RES_I_575___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_575__RX_DCOC_RES_Q_575___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_575__RX_DCOC_RES_Q_575___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_575___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_575___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_576 (0x005E4900) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_576___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_576___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_576__RX_DCOC_RANGE_576___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_576__RX_DCOC_RES_I_576___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_576__RX_DCOC_RES_Q_576___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_576__RX_DCOC_RANGE_576___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_576__RX_DCOC_RANGE_576___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_576__RX_DCOC_RES_I_576___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_576__RX_DCOC_RES_I_576___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_576__RX_DCOC_RES_Q_576___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_576__RX_DCOC_RES_Q_576___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_576___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_576___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_577 (0x005E4904) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_577___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_577___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_577__RX_DCOC_RANGE_577___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_577__RX_DCOC_RES_I_577___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_577__RX_DCOC_RES_Q_577___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_577__RX_DCOC_RANGE_577___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_577__RX_DCOC_RANGE_577___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_577__RX_DCOC_RES_I_577___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_577__RX_DCOC_RES_I_577___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_577__RX_DCOC_RES_Q_577___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_577__RX_DCOC_RES_Q_577___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_577___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_577___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_578 (0x005E4908) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_578___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_578___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_578__RX_DCOC_RANGE_578___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_578__RX_DCOC_RES_I_578___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_578__RX_DCOC_RES_Q_578___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_578__RX_DCOC_RANGE_578___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_578__RX_DCOC_RANGE_578___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_578__RX_DCOC_RES_I_578___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_578__RX_DCOC_RES_I_578___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_578__RX_DCOC_RES_Q_578___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_578__RX_DCOC_RES_Q_578___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_578___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_578___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_579 (0x005E490C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_579___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_579___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_579__RX_DCOC_RANGE_579___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_579__RX_DCOC_RES_I_579___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_579__RX_DCOC_RES_Q_579___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_579__RX_DCOC_RANGE_579___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_579__RX_DCOC_RANGE_579___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_579__RX_DCOC_RES_I_579___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_579__RX_DCOC_RES_I_579___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_579__RX_DCOC_RES_Q_579___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_579__RX_DCOC_RES_Q_579___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_579___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_579___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_580 (0x005E4910) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_580___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_580___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_580__RX_DCOC_RANGE_580___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_580__RX_DCOC_RES_I_580___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_580__RX_DCOC_RES_Q_580___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_580__RX_DCOC_RANGE_580___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_580__RX_DCOC_RANGE_580___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_580__RX_DCOC_RES_I_580___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_580__RX_DCOC_RES_I_580___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_580__RX_DCOC_RES_Q_580___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_580__RX_DCOC_RES_Q_580___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_580___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_580___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_581 (0x005E4914) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_581___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_581___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_581__RX_DCOC_RANGE_581___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_581__RX_DCOC_RES_I_581___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_581__RX_DCOC_RES_Q_581___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_581__RX_DCOC_RANGE_581___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_581__RX_DCOC_RANGE_581___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_581__RX_DCOC_RES_I_581___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_581__RX_DCOC_RES_I_581___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_581__RX_DCOC_RES_Q_581___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_581__RX_DCOC_RES_Q_581___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_581___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_581___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_582 (0x005E4918) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_582___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_582___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_582__RX_DCOC_RANGE_582___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_582__RX_DCOC_RES_I_582___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_582__RX_DCOC_RES_Q_582___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_582__RX_DCOC_RANGE_582___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_582__RX_DCOC_RANGE_582___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_582__RX_DCOC_RES_I_582___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_582__RX_DCOC_RES_I_582___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_582__RX_DCOC_RES_Q_582___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_582__RX_DCOC_RES_Q_582___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_582___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_582___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_583 (0x005E491C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_583___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_583___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_583__RX_DCOC_RANGE_583___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_583__RX_DCOC_RES_I_583___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_583__RX_DCOC_RES_Q_583___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_583__RX_DCOC_RANGE_583___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_583__RX_DCOC_RANGE_583___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_583__RX_DCOC_RES_I_583___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_583__RX_DCOC_RES_I_583___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_583__RX_DCOC_RES_Q_583___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_583__RX_DCOC_RES_Q_583___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_583___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_583___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_584 (0x005E4920) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_584___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_584___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_584__RX_DCOC_RANGE_584___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_584__RX_DCOC_RES_I_584___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_584__RX_DCOC_RES_Q_584___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_584__RX_DCOC_RANGE_584___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_584__RX_DCOC_RANGE_584___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_584__RX_DCOC_RES_I_584___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_584__RX_DCOC_RES_I_584___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_584__RX_DCOC_RES_Q_584___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_584__RX_DCOC_RES_Q_584___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_584___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_584___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_585 (0x005E4924) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_585___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_585___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_585__RX_DCOC_RANGE_585___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_585__RX_DCOC_RES_I_585___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_585__RX_DCOC_RES_Q_585___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_585__RX_DCOC_RANGE_585___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_585__RX_DCOC_RANGE_585___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_585__RX_DCOC_RES_I_585___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_585__RX_DCOC_RES_I_585___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_585__RX_DCOC_RES_Q_585___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_585__RX_DCOC_RES_Q_585___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_585___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_585___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_586 (0x005E4928) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_586___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_586___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_586__RX_DCOC_RANGE_586___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_586__RX_DCOC_RES_I_586___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_586__RX_DCOC_RES_Q_586___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_586__RX_DCOC_RANGE_586___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_586__RX_DCOC_RANGE_586___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_586__RX_DCOC_RES_I_586___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_586__RX_DCOC_RES_I_586___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_586__RX_DCOC_RES_Q_586___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_586__RX_DCOC_RES_Q_586___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_586___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_586___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_587 (0x005E492C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_587___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_587___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_587__RX_DCOC_RANGE_587___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_587__RX_DCOC_RES_I_587___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_587__RX_DCOC_RES_Q_587___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_587__RX_DCOC_RANGE_587___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_587__RX_DCOC_RANGE_587___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_587__RX_DCOC_RES_I_587___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_587__RX_DCOC_RES_I_587___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_587__RX_DCOC_RES_Q_587___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_587__RX_DCOC_RES_Q_587___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_587___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_587___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_588 (0x005E4930) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_588___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_588___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_588__RX_DCOC_RANGE_588___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_588__RX_DCOC_RES_I_588___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_588__RX_DCOC_RES_Q_588___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_588__RX_DCOC_RANGE_588___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_588__RX_DCOC_RANGE_588___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_588__RX_DCOC_RES_I_588___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_588__RX_DCOC_RES_I_588___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_588__RX_DCOC_RES_Q_588___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_588__RX_DCOC_RES_Q_588___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_588___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_588___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_589 (0x005E4934) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_589___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_589___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_589__RX_DCOC_RANGE_589___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_589__RX_DCOC_RES_I_589___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_589__RX_DCOC_RES_Q_589___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_589__RX_DCOC_RANGE_589___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_589__RX_DCOC_RANGE_589___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_589__RX_DCOC_RES_I_589___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_589__RX_DCOC_RES_I_589___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_589__RX_DCOC_RES_Q_589___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_589__RX_DCOC_RES_Q_589___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_589___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_589___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_590 (0x005E4938) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_590___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_590___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_590__RX_DCOC_RANGE_590___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_590__RX_DCOC_RES_I_590___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_590__RX_DCOC_RES_Q_590___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_590__RX_DCOC_RANGE_590___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_590__RX_DCOC_RANGE_590___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_590__RX_DCOC_RES_I_590___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_590__RX_DCOC_RES_I_590___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_590__RX_DCOC_RES_Q_590___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_590__RX_DCOC_RES_Q_590___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_590___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_590___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_591 (0x005E493C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_591___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_591___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_591__RX_DCOC_RANGE_591___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_591__RX_DCOC_RES_I_591___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_591__RX_DCOC_RES_Q_591___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_591__RX_DCOC_RANGE_591___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_591__RX_DCOC_RANGE_591___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_591__RX_DCOC_RES_I_591___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_591__RX_DCOC_RES_I_591___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_591__RX_DCOC_RES_Q_591___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_591__RX_DCOC_RES_Q_591___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_591___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_591___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_592 (0x005E4940) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_592___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_592___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_592__RX_DCOC_RANGE_592___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_592__RX_DCOC_RES_I_592___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_592__RX_DCOC_RES_Q_592___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_592__RX_DCOC_RANGE_592___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_592__RX_DCOC_RANGE_592___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_592__RX_DCOC_RES_I_592___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_592__RX_DCOC_RES_I_592___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_592__RX_DCOC_RES_Q_592___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_592__RX_DCOC_RES_Q_592___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_592___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_592___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_593 (0x005E4944) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_593___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_593___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_593__RX_DCOC_RANGE_593___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_593__RX_DCOC_RES_I_593___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_593__RX_DCOC_RES_Q_593___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_593__RX_DCOC_RANGE_593___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_593__RX_DCOC_RANGE_593___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_593__RX_DCOC_RES_I_593___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_593__RX_DCOC_RES_I_593___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_593__RX_DCOC_RES_Q_593___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_593__RX_DCOC_RES_Q_593___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_593___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_593___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_594 (0x005E4948) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_594___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_594___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_594__RX_DCOC_RANGE_594___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_594__RX_DCOC_RES_I_594___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_594__RX_DCOC_RES_Q_594___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_594__RX_DCOC_RANGE_594___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_594__RX_DCOC_RANGE_594___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_594__RX_DCOC_RES_I_594___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_594__RX_DCOC_RES_I_594___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_594__RX_DCOC_RES_Q_594___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_594__RX_DCOC_RES_Q_594___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_594___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_594___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_595 (0x005E494C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_595___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_595___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_595__RX_DCOC_RANGE_595___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_595__RX_DCOC_RES_I_595___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_595__RX_DCOC_RES_Q_595___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_595__RX_DCOC_RANGE_595___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_595__RX_DCOC_RANGE_595___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_595__RX_DCOC_RES_I_595___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_595__RX_DCOC_RES_I_595___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_595__RX_DCOC_RES_Q_595___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_595__RX_DCOC_RES_Q_595___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_595___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_595___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_596 (0x005E4950) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_596___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_596___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_596__RX_DCOC_RANGE_596___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_596__RX_DCOC_RES_I_596___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_596__RX_DCOC_RES_Q_596___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_596__RX_DCOC_RANGE_596___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_596__RX_DCOC_RANGE_596___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_596__RX_DCOC_RES_I_596___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_596__RX_DCOC_RES_I_596___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_596__RX_DCOC_RES_Q_596___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_596__RX_DCOC_RES_Q_596___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_596___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_596___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_597 (0x005E4954) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_597___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_597___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_597__RX_DCOC_RANGE_597___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_597__RX_DCOC_RES_I_597___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_597__RX_DCOC_RES_Q_597___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_597__RX_DCOC_RANGE_597___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_597__RX_DCOC_RANGE_597___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_597__RX_DCOC_RES_I_597___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_597__RX_DCOC_RES_I_597___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_597__RX_DCOC_RES_Q_597___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_597__RX_DCOC_RES_Q_597___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_597___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_597___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_598 (0x005E4958) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_598___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_598___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_598__RX_DCOC_RANGE_598___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_598__RX_DCOC_RES_I_598___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_598__RX_DCOC_RES_Q_598___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_598__RX_DCOC_RANGE_598___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_598__RX_DCOC_RANGE_598___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_598__RX_DCOC_RES_I_598___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_598__RX_DCOC_RES_I_598___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_598__RX_DCOC_RES_Q_598___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_598__RX_DCOC_RES_Q_598___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_598___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_598___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_599 (0x005E495C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_599___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_599___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_599__RX_DCOC_RANGE_599___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_599__RX_DCOC_RES_I_599___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_599__RX_DCOC_RES_Q_599___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_599__RX_DCOC_RANGE_599___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_599__RX_DCOC_RANGE_599___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_599__RX_DCOC_RES_I_599___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_599__RX_DCOC_RES_I_599___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_599__RX_DCOC_RES_Q_599___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_599__RX_DCOC_RES_Q_599___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_599___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_599___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_600 (0x005E4960) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_600___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_600___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_600__RX_DCOC_RANGE_600___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_600__RX_DCOC_RES_I_600___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_600__RX_DCOC_RES_Q_600___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_600__RX_DCOC_RANGE_600___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_600__RX_DCOC_RANGE_600___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_600__RX_DCOC_RES_I_600___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_600__RX_DCOC_RES_I_600___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_600__RX_DCOC_RES_Q_600___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_600__RX_DCOC_RES_Q_600___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_600___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_600___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_601 (0x005E4964) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_601___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_601___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_601__RX_DCOC_RANGE_601___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_601__RX_DCOC_RES_I_601___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_601__RX_DCOC_RES_Q_601___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_601__RX_DCOC_RANGE_601___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_601__RX_DCOC_RANGE_601___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_601__RX_DCOC_RES_I_601___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_601__RX_DCOC_RES_I_601___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_601__RX_DCOC_RES_Q_601___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_601__RX_DCOC_RES_Q_601___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_601___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_601___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_602 (0x005E4968) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_602___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_602___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_602__RX_DCOC_RANGE_602___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_602__RX_DCOC_RES_I_602___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_602__RX_DCOC_RES_Q_602___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_602__RX_DCOC_RANGE_602___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_602__RX_DCOC_RANGE_602___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_602__RX_DCOC_RES_I_602___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_602__RX_DCOC_RES_I_602___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_602__RX_DCOC_RES_Q_602___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_602__RX_DCOC_RES_Q_602___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_602___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_602___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_603 (0x005E496C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_603___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_603___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_603__RX_DCOC_RANGE_603___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_603__RX_DCOC_RES_I_603___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_603__RX_DCOC_RES_Q_603___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_603__RX_DCOC_RANGE_603___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_603__RX_DCOC_RANGE_603___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_603__RX_DCOC_RES_I_603___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_603__RX_DCOC_RES_I_603___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_603__RX_DCOC_RES_Q_603___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_603__RX_DCOC_RES_Q_603___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_603___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_603___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_604 (0x005E4970) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_604___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_604___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_604__RX_DCOC_RANGE_604___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_604__RX_DCOC_RES_I_604___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_604__RX_DCOC_RES_Q_604___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_604__RX_DCOC_RANGE_604___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_604__RX_DCOC_RANGE_604___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_604__RX_DCOC_RES_I_604___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_604__RX_DCOC_RES_I_604___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_604__RX_DCOC_RES_Q_604___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_604__RX_DCOC_RES_Q_604___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_604___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_604___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_605 (0x005E4974) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_605___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_605___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_605__RX_DCOC_RANGE_605___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_605__RX_DCOC_RES_I_605___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_605__RX_DCOC_RES_Q_605___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_605__RX_DCOC_RANGE_605___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_605__RX_DCOC_RANGE_605___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_605__RX_DCOC_RES_I_605___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_605__RX_DCOC_RES_I_605___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_605__RX_DCOC_RES_Q_605___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_605__RX_DCOC_RES_Q_605___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_605___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_605___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_606 (0x005E4978) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_606___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_606___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_606__RX_DCOC_RANGE_606___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_606__RX_DCOC_RES_I_606___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_606__RX_DCOC_RES_Q_606___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_606__RX_DCOC_RANGE_606___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_606__RX_DCOC_RANGE_606___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_606__RX_DCOC_RES_I_606___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_606__RX_DCOC_RES_I_606___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_606__RX_DCOC_RES_Q_606___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_606__RX_DCOC_RES_Q_606___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_606___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_606___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_607 (0x005E497C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_607___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_607___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_607__RX_DCOC_RANGE_607___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_607__RX_DCOC_RES_I_607___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_607__RX_DCOC_RES_Q_607___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_607__RX_DCOC_RANGE_607___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_607__RX_DCOC_RANGE_607___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_607__RX_DCOC_RES_I_607___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_607__RX_DCOC_RES_I_607___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_607__RX_DCOC_RES_Q_607___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_607__RX_DCOC_RES_Q_607___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_607___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_607___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_608 (0x005E4980) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_608___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_608___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_608__RX_DCOC_RANGE_608___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_608__RX_DCOC_RES_I_608___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_608__RX_DCOC_RES_Q_608___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_608__RX_DCOC_RANGE_608___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_608__RX_DCOC_RANGE_608___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_608__RX_DCOC_RES_I_608___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_608__RX_DCOC_RES_I_608___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_608__RX_DCOC_RES_Q_608___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_608__RX_DCOC_RES_Q_608___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_608___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_608___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_609 (0x005E4984) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_609___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_609___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_609__RX_DCOC_RANGE_609___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_609__RX_DCOC_RES_I_609___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_609__RX_DCOC_RES_Q_609___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_609__RX_DCOC_RANGE_609___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_609__RX_DCOC_RANGE_609___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_609__RX_DCOC_RES_I_609___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_609__RX_DCOC_RES_I_609___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_609__RX_DCOC_RES_Q_609___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_609__RX_DCOC_RES_Q_609___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_609___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_609___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_610 (0x005E4988) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_610___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_610___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_610__RX_DCOC_RANGE_610___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_610__RX_DCOC_RES_I_610___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_610__RX_DCOC_RES_Q_610___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_610__RX_DCOC_RANGE_610___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_610__RX_DCOC_RANGE_610___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_610__RX_DCOC_RES_I_610___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_610__RX_DCOC_RES_I_610___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_610__RX_DCOC_RES_Q_610___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_610__RX_DCOC_RES_Q_610___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_610___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_610___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_611 (0x005E498C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_611___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_611___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_611__RX_DCOC_RANGE_611___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_611__RX_DCOC_RES_I_611___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_611__RX_DCOC_RES_Q_611___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_611__RX_DCOC_RANGE_611___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_611__RX_DCOC_RANGE_611___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_611__RX_DCOC_RES_I_611___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_611__RX_DCOC_RES_I_611___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_611__RX_DCOC_RES_Q_611___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_611__RX_DCOC_RES_Q_611___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_611___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_611___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_612 (0x005E4990) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_612___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_612___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_612__RX_DCOC_RANGE_612___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_612__RX_DCOC_RES_I_612___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_612__RX_DCOC_RES_Q_612___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_612__RX_DCOC_RANGE_612___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_612__RX_DCOC_RANGE_612___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_612__RX_DCOC_RES_I_612___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_612__RX_DCOC_RES_I_612___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_612__RX_DCOC_RES_Q_612___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_612__RX_DCOC_RES_Q_612___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_612___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_612___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_613 (0x005E4994) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_613___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_613___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_613__RX_DCOC_RANGE_613___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_613__RX_DCOC_RES_I_613___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_613__RX_DCOC_RES_Q_613___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_613__RX_DCOC_RANGE_613___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_613__RX_DCOC_RANGE_613___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_613__RX_DCOC_RES_I_613___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_613__RX_DCOC_RES_I_613___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_613__RX_DCOC_RES_Q_613___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_613__RX_DCOC_RES_Q_613___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_613___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_613___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_614 (0x005E4998) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_614___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_614___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_614__RX_DCOC_RANGE_614___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_614__RX_DCOC_RES_I_614___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_614__RX_DCOC_RES_Q_614___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_614__RX_DCOC_RANGE_614___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_614__RX_DCOC_RANGE_614___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_614__RX_DCOC_RES_I_614___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_614__RX_DCOC_RES_I_614___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_614__RX_DCOC_RES_Q_614___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_614__RX_DCOC_RES_Q_614___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_614___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_614___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_615 (0x005E499C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_615___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_615___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_615__RX_DCOC_RANGE_615___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_615__RX_DCOC_RES_I_615___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_615__RX_DCOC_RES_Q_615___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_615__RX_DCOC_RANGE_615___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_615__RX_DCOC_RANGE_615___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_615__RX_DCOC_RES_I_615___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_615__RX_DCOC_RES_I_615___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_615__RX_DCOC_RES_Q_615___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_615__RX_DCOC_RES_Q_615___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_615___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_615___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_616 (0x005E49A0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_616___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_616___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_616__RX_DCOC_RANGE_616___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_616__RX_DCOC_RES_I_616___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_616__RX_DCOC_RES_Q_616___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_616__RX_DCOC_RANGE_616___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_616__RX_DCOC_RANGE_616___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_616__RX_DCOC_RES_I_616___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_616__RX_DCOC_RES_I_616___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_616__RX_DCOC_RES_Q_616___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_616__RX_DCOC_RES_Q_616___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_616___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_616___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_617 (0x005E49A4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_617___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_617___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_617__RX_DCOC_RANGE_617___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_617__RX_DCOC_RES_I_617___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_617__RX_DCOC_RES_Q_617___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_617__RX_DCOC_RANGE_617___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_617__RX_DCOC_RANGE_617___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_617__RX_DCOC_RES_I_617___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_617__RX_DCOC_RES_I_617___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_617__RX_DCOC_RES_Q_617___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_617__RX_DCOC_RES_Q_617___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_617___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_617___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_618 (0x005E49A8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_618___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_618___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_618__RX_DCOC_RANGE_618___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_618__RX_DCOC_RES_I_618___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_618__RX_DCOC_RES_Q_618___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_618__RX_DCOC_RANGE_618___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_618__RX_DCOC_RANGE_618___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_618__RX_DCOC_RES_I_618___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_618__RX_DCOC_RES_I_618___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_618__RX_DCOC_RES_Q_618___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_618__RX_DCOC_RES_Q_618___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_618___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_618___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_619 (0x005E49AC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_619___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_619___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_619__RX_DCOC_RANGE_619___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_619__RX_DCOC_RES_I_619___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_619__RX_DCOC_RES_Q_619___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_619__RX_DCOC_RANGE_619___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_619__RX_DCOC_RANGE_619___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_619__RX_DCOC_RES_I_619___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_619__RX_DCOC_RES_I_619___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_619__RX_DCOC_RES_Q_619___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_619__RX_DCOC_RES_Q_619___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_619___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_619___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_620 (0x005E49B0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_620___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_620___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_620__RX_DCOC_RANGE_620___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_620__RX_DCOC_RES_I_620___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_620__RX_DCOC_RES_Q_620___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_620__RX_DCOC_RANGE_620___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_620__RX_DCOC_RANGE_620___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_620__RX_DCOC_RES_I_620___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_620__RX_DCOC_RES_I_620___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_620__RX_DCOC_RES_Q_620___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_620__RX_DCOC_RES_Q_620___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_620___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_620___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_621 (0x005E49B4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_621___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_621___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_621__RX_DCOC_RANGE_621___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_621__RX_DCOC_RES_I_621___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_621__RX_DCOC_RES_Q_621___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_621__RX_DCOC_RANGE_621___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_621__RX_DCOC_RANGE_621___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_621__RX_DCOC_RES_I_621___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_621__RX_DCOC_RES_I_621___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_621__RX_DCOC_RES_Q_621___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_621__RX_DCOC_RES_Q_621___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_621___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_621___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_622 (0x005E49B8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_622___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_622___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_622__RX_DCOC_RANGE_622___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_622__RX_DCOC_RES_I_622___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_622__RX_DCOC_RES_Q_622___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_622__RX_DCOC_RANGE_622___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_622__RX_DCOC_RANGE_622___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_622__RX_DCOC_RES_I_622___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_622__RX_DCOC_RES_I_622___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_622__RX_DCOC_RES_Q_622___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_622__RX_DCOC_RES_Q_622___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_622___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_622___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_623 (0x005E49BC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_623___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_623___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_623__RX_DCOC_RANGE_623___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_623__RX_DCOC_RES_I_623___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_623__RX_DCOC_RES_Q_623___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_623__RX_DCOC_RANGE_623___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_623__RX_DCOC_RANGE_623___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_623__RX_DCOC_RES_I_623___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_623__RX_DCOC_RES_I_623___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_623__RX_DCOC_RES_Q_623___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_623__RX_DCOC_RES_Q_623___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_623___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_623___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_624 (0x005E49C0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_624___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_624___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_624__RX_DCOC_RANGE_624___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_624__RX_DCOC_RES_I_624___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_624__RX_DCOC_RES_Q_624___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_624__RX_DCOC_RANGE_624___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_624__RX_DCOC_RANGE_624___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_624__RX_DCOC_RES_I_624___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_624__RX_DCOC_RES_I_624___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_624__RX_DCOC_RES_Q_624___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_624__RX_DCOC_RES_Q_624___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_624___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_624___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_625 (0x005E49C4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_625___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_625___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_625__RX_DCOC_RANGE_625___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_625__RX_DCOC_RES_I_625___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_625__RX_DCOC_RES_Q_625___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_625__RX_DCOC_RANGE_625___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_625__RX_DCOC_RANGE_625___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_625__RX_DCOC_RES_I_625___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_625__RX_DCOC_RES_I_625___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_625__RX_DCOC_RES_Q_625___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_625__RX_DCOC_RES_Q_625___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_625___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_625___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_626 (0x005E49C8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_626___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_626___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_626__RX_DCOC_RANGE_626___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_626__RX_DCOC_RES_I_626___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_626__RX_DCOC_RES_Q_626___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_626__RX_DCOC_RANGE_626___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_626__RX_DCOC_RANGE_626___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_626__RX_DCOC_RES_I_626___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_626__RX_DCOC_RES_I_626___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_626__RX_DCOC_RES_Q_626___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_626__RX_DCOC_RES_Q_626___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_626___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_626___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_627 (0x005E49CC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_627___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_627___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_627__RX_DCOC_RANGE_627___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_627__RX_DCOC_RES_I_627___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_627__RX_DCOC_RES_Q_627___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_627__RX_DCOC_RANGE_627___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_627__RX_DCOC_RANGE_627___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_627__RX_DCOC_RES_I_627___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_627__RX_DCOC_RES_I_627___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_627__RX_DCOC_RES_Q_627___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_627__RX_DCOC_RES_Q_627___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_627___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_627___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_628 (0x005E49D0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_628___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_628___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_628__RX_DCOC_RANGE_628___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_628__RX_DCOC_RES_I_628___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_628__RX_DCOC_RES_Q_628___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_628__RX_DCOC_RANGE_628___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_628__RX_DCOC_RANGE_628___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_628__RX_DCOC_RES_I_628___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_628__RX_DCOC_RES_I_628___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_628__RX_DCOC_RES_Q_628___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_628__RX_DCOC_RES_Q_628___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_628___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_628___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_629 (0x005E49D4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_629___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_629___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_629__RX_DCOC_RANGE_629___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_629__RX_DCOC_RES_I_629___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_629__RX_DCOC_RES_Q_629___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_629__RX_DCOC_RANGE_629___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_629__RX_DCOC_RANGE_629___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_629__RX_DCOC_RES_I_629___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_629__RX_DCOC_RES_I_629___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_629__RX_DCOC_RES_Q_629___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_629__RX_DCOC_RES_Q_629___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_629___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_629___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_630 (0x005E49D8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_630___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_630___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_630__RX_DCOC_RANGE_630___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_630__RX_DCOC_RES_I_630___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_630__RX_DCOC_RES_Q_630___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_630__RX_DCOC_RANGE_630___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_630__RX_DCOC_RANGE_630___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_630__RX_DCOC_RES_I_630___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_630__RX_DCOC_RES_I_630___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_630__RX_DCOC_RES_Q_630___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_630__RX_DCOC_RES_Q_630___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_630___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_630___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_631 (0x005E49DC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_631___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_631___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_631__RX_DCOC_RANGE_631___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_631__RX_DCOC_RES_I_631___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_631__RX_DCOC_RES_Q_631___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_631__RX_DCOC_RANGE_631___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_631__RX_DCOC_RANGE_631___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_631__RX_DCOC_RES_I_631___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_631__RX_DCOC_RES_I_631___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_631__RX_DCOC_RES_Q_631___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_631__RX_DCOC_RES_Q_631___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_631___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_631___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_632 (0x005E49E0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_632___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_632___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_632__RX_DCOC_RANGE_632___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_632__RX_DCOC_RES_I_632___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_632__RX_DCOC_RES_Q_632___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_632__RX_DCOC_RANGE_632___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_632__RX_DCOC_RANGE_632___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_632__RX_DCOC_RES_I_632___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_632__RX_DCOC_RES_I_632___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_632__RX_DCOC_RES_Q_632___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_632__RX_DCOC_RES_Q_632___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_632___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_632___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_633 (0x005E49E4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_633___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_633___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_633__RX_DCOC_RANGE_633___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_633__RX_DCOC_RES_I_633___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_633__RX_DCOC_RES_Q_633___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_633__RX_DCOC_RANGE_633___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_633__RX_DCOC_RANGE_633___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_633__RX_DCOC_RES_I_633___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_633__RX_DCOC_RES_I_633___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_633__RX_DCOC_RES_Q_633___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_633__RX_DCOC_RES_Q_633___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_633___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_633___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_634 (0x005E49E8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_634___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_634___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_634__RX_DCOC_RANGE_634___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_634__RX_DCOC_RES_I_634___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_634__RX_DCOC_RES_Q_634___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_634__RX_DCOC_RANGE_634___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_634__RX_DCOC_RANGE_634___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_634__RX_DCOC_RES_I_634___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_634__RX_DCOC_RES_I_634___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_634__RX_DCOC_RES_Q_634___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_634__RX_DCOC_RES_Q_634___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_634___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_634___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_635 (0x005E49EC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_635___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_635___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_635__RX_DCOC_RANGE_635___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_635__RX_DCOC_RES_I_635___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_635__RX_DCOC_RES_Q_635___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_635__RX_DCOC_RANGE_635___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_635__RX_DCOC_RANGE_635___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_635__RX_DCOC_RES_I_635___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_635__RX_DCOC_RES_I_635___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_635__RX_DCOC_RES_Q_635___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_635__RX_DCOC_RES_Q_635___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_635___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_635___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_636 (0x005E49F0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_636___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_636___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_636__RX_DCOC_RANGE_636___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_636__RX_DCOC_RES_I_636___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_636__RX_DCOC_RES_Q_636___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_636__RX_DCOC_RANGE_636___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_636__RX_DCOC_RANGE_636___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_636__RX_DCOC_RES_I_636___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_636__RX_DCOC_RES_I_636___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_636__RX_DCOC_RES_Q_636___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_636__RX_DCOC_RES_Q_636___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_636___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_636___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_637 (0x005E49F4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_637___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_637___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_637__RX_DCOC_RANGE_637___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_637__RX_DCOC_RES_I_637___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_637__RX_DCOC_RES_Q_637___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_637__RX_DCOC_RANGE_637___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_637__RX_DCOC_RANGE_637___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_637__RX_DCOC_RES_I_637___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_637__RX_DCOC_RES_I_637___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_637__RX_DCOC_RES_Q_637___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_637__RX_DCOC_RES_Q_637___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_637___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_637___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_638 (0x005E49F8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_638___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_638___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_638__RX_DCOC_RANGE_638___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_638__RX_DCOC_RES_I_638___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_638__RX_DCOC_RES_Q_638___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_638__RX_DCOC_RANGE_638___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_638__RX_DCOC_RANGE_638___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_638__RX_DCOC_RES_I_638___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_638__RX_DCOC_RES_I_638___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_638__RX_DCOC_RES_Q_638___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_638__RX_DCOC_RES_Q_638___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_638___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_638___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_639 (0x005E49FC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_639___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_639___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_639__RX_DCOC_RANGE_639___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_639__RX_DCOC_RES_I_639___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_639__RX_DCOC_RES_Q_639___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_639__RX_DCOC_RANGE_639___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_639__RX_DCOC_RANGE_639___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_639__RX_DCOC_RES_I_639___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_639__RX_DCOC_RES_I_639___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_639__RX_DCOC_RES_Q_639___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_639__RX_DCOC_RES_Q_639___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_639___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_639___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_640 (0x005E4A00) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_640___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_640___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_640__RX_DCOC_RANGE_640___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_640__RX_DCOC_RES_I_640___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_640__RX_DCOC_RES_Q_640___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_640__RX_DCOC_RANGE_640___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_640__RX_DCOC_RANGE_640___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_640__RX_DCOC_RES_I_640___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_640__RX_DCOC_RES_I_640___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_640__RX_DCOC_RES_Q_640___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_640__RX_DCOC_RES_Q_640___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_640___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_640___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_641 (0x005E4A04) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_641___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_641___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_641__RX_DCOC_RANGE_641___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_641__RX_DCOC_RES_I_641___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_641__RX_DCOC_RES_Q_641___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_641__RX_DCOC_RANGE_641___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_641__RX_DCOC_RANGE_641___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_641__RX_DCOC_RES_I_641___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_641__RX_DCOC_RES_I_641___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_641__RX_DCOC_RES_Q_641___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_641__RX_DCOC_RES_Q_641___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_641___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_641___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_642 (0x005E4A08) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_642___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_642___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_642__RX_DCOC_RANGE_642___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_642__RX_DCOC_RES_I_642___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_642__RX_DCOC_RES_Q_642___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_642__RX_DCOC_RANGE_642___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_642__RX_DCOC_RANGE_642___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_642__RX_DCOC_RES_I_642___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_642__RX_DCOC_RES_I_642___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_642__RX_DCOC_RES_Q_642___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_642__RX_DCOC_RES_Q_642___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_642___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_642___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_643 (0x005E4A0C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_643___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_643___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_643__RX_DCOC_RANGE_643___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_643__RX_DCOC_RES_I_643___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_643__RX_DCOC_RES_Q_643___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_643__RX_DCOC_RANGE_643___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_643__RX_DCOC_RANGE_643___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_643__RX_DCOC_RES_I_643___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_643__RX_DCOC_RES_I_643___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_643__RX_DCOC_RES_Q_643___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_643__RX_DCOC_RES_Q_643___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_643___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_643___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_644 (0x005E4A10) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_644___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_644___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_644__RX_DCOC_RANGE_644___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_644__RX_DCOC_RES_I_644___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_644__RX_DCOC_RES_Q_644___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_644__RX_DCOC_RANGE_644___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_644__RX_DCOC_RANGE_644___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_644__RX_DCOC_RES_I_644___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_644__RX_DCOC_RES_I_644___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_644__RX_DCOC_RES_Q_644___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_644__RX_DCOC_RES_Q_644___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_644___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_644___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_645 (0x005E4A14) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_645___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_645___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_645__RX_DCOC_RANGE_645___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_645__RX_DCOC_RES_I_645___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_645__RX_DCOC_RES_Q_645___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_645__RX_DCOC_RANGE_645___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_645__RX_DCOC_RANGE_645___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_645__RX_DCOC_RES_I_645___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_645__RX_DCOC_RES_I_645___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_645__RX_DCOC_RES_Q_645___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_645__RX_DCOC_RES_Q_645___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_645___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_645___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_646 (0x005E4A18) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_646___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_646___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_646__RX_DCOC_RANGE_646___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_646__RX_DCOC_RES_I_646___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_646__RX_DCOC_RES_Q_646___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_646__RX_DCOC_RANGE_646___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_646__RX_DCOC_RANGE_646___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_646__RX_DCOC_RES_I_646___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_646__RX_DCOC_RES_I_646___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_646__RX_DCOC_RES_Q_646___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_646__RX_DCOC_RES_Q_646___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_646___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_646___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_647 (0x005E4A1C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_647___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_647___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_647__RX_DCOC_RANGE_647___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_647__RX_DCOC_RES_I_647___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_647__RX_DCOC_RES_Q_647___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_647__RX_DCOC_RANGE_647___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_647__RX_DCOC_RANGE_647___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_647__RX_DCOC_RES_I_647___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_647__RX_DCOC_RES_I_647___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_647__RX_DCOC_RES_Q_647___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_647__RX_DCOC_RES_Q_647___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_647___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_647___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_648 (0x005E4A20) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_648___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_648___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_648__RX_DCOC_RANGE_648___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_648__RX_DCOC_RES_I_648___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_648__RX_DCOC_RES_Q_648___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_648__RX_DCOC_RANGE_648___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_648__RX_DCOC_RANGE_648___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_648__RX_DCOC_RES_I_648___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_648__RX_DCOC_RES_I_648___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_648__RX_DCOC_RES_Q_648___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_648__RX_DCOC_RES_Q_648___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_648___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_648___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_649 (0x005E4A24) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_649___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_649___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_649__RX_DCOC_RANGE_649___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_649__RX_DCOC_RES_I_649___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_649__RX_DCOC_RES_Q_649___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_649__RX_DCOC_RANGE_649___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_649__RX_DCOC_RANGE_649___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_649__RX_DCOC_RES_I_649___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_649__RX_DCOC_RES_I_649___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_649__RX_DCOC_RES_Q_649___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_649__RX_DCOC_RES_Q_649___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_649___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_649___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_650 (0x005E4A28) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_650___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_650___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_650__RX_DCOC_RANGE_650___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_650__RX_DCOC_RES_I_650___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_650__RX_DCOC_RES_Q_650___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_650__RX_DCOC_RANGE_650___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_650__RX_DCOC_RANGE_650___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_650__RX_DCOC_RES_I_650___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_650__RX_DCOC_RES_I_650___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_650__RX_DCOC_RES_Q_650___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_650__RX_DCOC_RES_Q_650___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_650___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_650___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_651 (0x005E4A2C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_651___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_651___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_651__RX_DCOC_RANGE_651___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_651__RX_DCOC_RES_I_651___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_651__RX_DCOC_RES_Q_651___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_651__RX_DCOC_RANGE_651___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_651__RX_DCOC_RANGE_651___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_651__RX_DCOC_RES_I_651___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_651__RX_DCOC_RES_I_651___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_651__RX_DCOC_RES_Q_651___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_651__RX_DCOC_RES_Q_651___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_651___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_651___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_652 (0x005E4A30) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_652___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_652___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_652__RX_DCOC_RANGE_652___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_652__RX_DCOC_RES_I_652___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_652__RX_DCOC_RES_Q_652___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_652__RX_DCOC_RANGE_652___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_652__RX_DCOC_RANGE_652___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_652__RX_DCOC_RES_I_652___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_652__RX_DCOC_RES_I_652___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_652__RX_DCOC_RES_Q_652___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_652__RX_DCOC_RES_Q_652___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_652___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_652___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_653 (0x005E4A34) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_653___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_653___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_653__RX_DCOC_RANGE_653___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_653__RX_DCOC_RES_I_653___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_653__RX_DCOC_RES_Q_653___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_653__RX_DCOC_RANGE_653___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_653__RX_DCOC_RANGE_653___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_653__RX_DCOC_RES_I_653___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_653__RX_DCOC_RES_I_653___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_653__RX_DCOC_RES_Q_653___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_653__RX_DCOC_RES_Q_653___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_653___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_653___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_654 (0x005E4A38) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_654___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_654___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_654__RX_DCOC_RANGE_654___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_654__RX_DCOC_RES_I_654___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_654__RX_DCOC_RES_Q_654___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_654__RX_DCOC_RANGE_654___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_654__RX_DCOC_RANGE_654___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_654__RX_DCOC_RES_I_654___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_654__RX_DCOC_RES_I_654___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_654__RX_DCOC_RES_Q_654___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_654__RX_DCOC_RES_Q_654___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_654___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_654___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_655 (0x005E4A3C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_655___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_655___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_655__RX_DCOC_RANGE_655___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_655__RX_DCOC_RES_I_655___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_655__RX_DCOC_RES_Q_655___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_655__RX_DCOC_RANGE_655___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_655__RX_DCOC_RANGE_655___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_655__RX_DCOC_RES_I_655___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_655__RX_DCOC_RES_I_655___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_655__RX_DCOC_RES_Q_655___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_655__RX_DCOC_RES_Q_655___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_655___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_655___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_656 (0x005E4A40) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_656___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_656___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_656__RX_DCOC_RANGE_656___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_656__RX_DCOC_RES_I_656___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_656__RX_DCOC_RES_Q_656___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_656__RX_DCOC_RANGE_656___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_656__RX_DCOC_RANGE_656___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_656__RX_DCOC_RES_I_656___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_656__RX_DCOC_RES_I_656___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_656__RX_DCOC_RES_Q_656___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_656__RX_DCOC_RES_Q_656___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_656___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_656___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_657 (0x005E4A44) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_657___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_657___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_657__RX_DCOC_RANGE_657___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_657__RX_DCOC_RES_I_657___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_657__RX_DCOC_RES_Q_657___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_657__RX_DCOC_RANGE_657___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_657__RX_DCOC_RANGE_657___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_657__RX_DCOC_RES_I_657___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_657__RX_DCOC_RES_I_657___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_657__RX_DCOC_RES_Q_657___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_657__RX_DCOC_RES_Q_657___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_657___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_657___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_658 (0x005E4A48) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_658___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_658___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_658__RX_DCOC_RANGE_658___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_658__RX_DCOC_RES_I_658___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_658__RX_DCOC_RES_Q_658___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_658__RX_DCOC_RANGE_658___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_658__RX_DCOC_RANGE_658___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_658__RX_DCOC_RES_I_658___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_658__RX_DCOC_RES_I_658___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_658__RX_DCOC_RES_Q_658___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_658__RX_DCOC_RES_Q_658___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_658___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_658___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_659 (0x005E4A4C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_659___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_659___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_659__RX_DCOC_RANGE_659___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_659__RX_DCOC_RES_I_659___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_659__RX_DCOC_RES_Q_659___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_659__RX_DCOC_RANGE_659___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_659__RX_DCOC_RANGE_659___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_659__RX_DCOC_RES_I_659___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_659__RX_DCOC_RES_I_659___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_659__RX_DCOC_RES_Q_659___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_659__RX_DCOC_RES_Q_659___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_659___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_659___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_660 (0x005E4A50) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_660___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_660___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_660__RX_DCOC_RANGE_660___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_660__RX_DCOC_RES_I_660___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_660__RX_DCOC_RES_Q_660___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_660__RX_DCOC_RANGE_660___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_660__RX_DCOC_RANGE_660___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_660__RX_DCOC_RES_I_660___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_660__RX_DCOC_RES_I_660___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_660__RX_DCOC_RES_Q_660___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_660__RX_DCOC_RES_Q_660___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_660___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_660___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_661 (0x005E4A54) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_661___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_661___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_661__RX_DCOC_RANGE_661___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_661__RX_DCOC_RES_I_661___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_661__RX_DCOC_RES_Q_661___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_661__RX_DCOC_RANGE_661___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_661__RX_DCOC_RANGE_661___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_661__RX_DCOC_RES_I_661___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_661__RX_DCOC_RES_I_661___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_661__RX_DCOC_RES_Q_661___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_661__RX_DCOC_RES_Q_661___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_661___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_661___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_662 (0x005E4A58) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_662___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_662___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_662__RX_DCOC_RANGE_662___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_662__RX_DCOC_RES_I_662___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_662__RX_DCOC_RES_Q_662___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_662__RX_DCOC_RANGE_662___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_662__RX_DCOC_RANGE_662___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_662__RX_DCOC_RES_I_662___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_662__RX_DCOC_RES_I_662___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_662__RX_DCOC_RES_Q_662___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_662__RX_DCOC_RES_Q_662___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_662___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_662___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_663 (0x005E4A5C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_663___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_663___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_663__RX_DCOC_RANGE_663___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_663__RX_DCOC_RES_I_663___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_663__RX_DCOC_RES_Q_663___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_663__RX_DCOC_RANGE_663___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_663__RX_DCOC_RANGE_663___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_663__RX_DCOC_RES_I_663___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_663__RX_DCOC_RES_I_663___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_663__RX_DCOC_RES_Q_663___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_663__RX_DCOC_RES_Q_663___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_663___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_663___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_664 (0x005E4A60) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_664___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_664___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_664__RX_DCOC_RANGE_664___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_664__RX_DCOC_RES_I_664___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_664__RX_DCOC_RES_Q_664___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_664__RX_DCOC_RANGE_664___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_664__RX_DCOC_RANGE_664___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_664__RX_DCOC_RES_I_664___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_664__RX_DCOC_RES_I_664___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_664__RX_DCOC_RES_Q_664___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_664__RX_DCOC_RES_Q_664___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_664___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_664___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_665 (0x005E4A64) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_665___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_665___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_665__RX_DCOC_RANGE_665___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_665__RX_DCOC_RES_I_665___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_665__RX_DCOC_RES_Q_665___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_665__RX_DCOC_RANGE_665___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_665__RX_DCOC_RANGE_665___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_665__RX_DCOC_RES_I_665___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_665__RX_DCOC_RES_I_665___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_665__RX_DCOC_RES_Q_665___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_665__RX_DCOC_RES_Q_665___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_665___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_665___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_666 (0x005E4A68) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_666___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_666___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_666__RX_DCOC_RANGE_666___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_666__RX_DCOC_RES_I_666___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_666__RX_DCOC_RES_Q_666___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_666__RX_DCOC_RANGE_666___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_666__RX_DCOC_RANGE_666___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_666__RX_DCOC_RES_I_666___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_666__RX_DCOC_RES_I_666___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_666__RX_DCOC_RES_Q_666___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_666__RX_DCOC_RES_Q_666___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_666___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_666___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_667 (0x005E4A6C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_667___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_667___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_667__RX_DCOC_RANGE_667___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_667__RX_DCOC_RES_I_667___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_667__RX_DCOC_RES_Q_667___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_667__RX_DCOC_RANGE_667___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_667__RX_DCOC_RANGE_667___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_667__RX_DCOC_RES_I_667___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_667__RX_DCOC_RES_I_667___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_667__RX_DCOC_RES_Q_667___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_667__RX_DCOC_RES_Q_667___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_667___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_667___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_668 (0x005E4A70) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_668___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_668___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_668__RX_DCOC_RANGE_668___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_668__RX_DCOC_RES_I_668___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_668__RX_DCOC_RES_Q_668___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_668__RX_DCOC_RANGE_668___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_668__RX_DCOC_RANGE_668___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_668__RX_DCOC_RES_I_668___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_668__RX_DCOC_RES_I_668___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_668__RX_DCOC_RES_Q_668___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_668__RX_DCOC_RES_Q_668___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_668___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_668___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_669 (0x005E4A74) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_669___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_669___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_669__RX_DCOC_RANGE_669___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_669__RX_DCOC_RES_I_669___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_669__RX_DCOC_RES_Q_669___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_669__RX_DCOC_RANGE_669___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_669__RX_DCOC_RANGE_669___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_669__RX_DCOC_RES_I_669___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_669__RX_DCOC_RES_I_669___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_669__RX_DCOC_RES_Q_669___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_669__RX_DCOC_RES_Q_669___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_669___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_669___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_670 (0x005E4A78) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_670___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_670___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_670__RX_DCOC_RANGE_670___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_670__RX_DCOC_RES_I_670___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_670__RX_DCOC_RES_Q_670___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_670__RX_DCOC_RANGE_670___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_670__RX_DCOC_RANGE_670___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_670__RX_DCOC_RES_I_670___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_670__RX_DCOC_RES_I_670___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_670__RX_DCOC_RES_Q_670___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_670__RX_DCOC_RES_Q_670___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_670___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_670___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_671 (0x005E4A7C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_671___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_671___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_671__RX_DCOC_RANGE_671___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_671__RX_DCOC_RES_I_671___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_671__RX_DCOC_RES_Q_671___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_671__RX_DCOC_RANGE_671___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_671__RX_DCOC_RANGE_671___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_671__RX_DCOC_RES_I_671___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_671__RX_DCOC_RES_I_671___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_671__RX_DCOC_RES_Q_671___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_671__RX_DCOC_RES_Q_671___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_671___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_671___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_672 (0x005E4A80) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_672___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_672___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_672__RX_DCOC_RANGE_672___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_672__RX_DCOC_RES_I_672___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_672__RX_DCOC_RES_Q_672___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_672__RX_DCOC_RANGE_672___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_672__RX_DCOC_RANGE_672___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_672__RX_DCOC_RES_I_672___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_672__RX_DCOC_RES_I_672___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_672__RX_DCOC_RES_Q_672___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_672__RX_DCOC_RES_Q_672___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_672___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_672___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_673 (0x005E4A84) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_673___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_673___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_673__RX_DCOC_RANGE_673___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_673__RX_DCOC_RES_I_673___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_673__RX_DCOC_RES_Q_673___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_673__RX_DCOC_RANGE_673___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_673__RX_DCOC_RANGE_673___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_673__RX_DCOC_RES_I_673___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_673__RX_DCOC_RES_I_673___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_673__RX_DCOC_RES_Q_673___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_673__RX_DCOC_RES_Q_673___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_673___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_673___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_674 (0x005E4A88) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_674___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_674___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_674__RX_DCOC_RANGE_674___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_674__RX_DCOC_RES_I_674___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_674__RX_DCOC_RES_Q_674___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_674__RX_DCOC_RANGE_674___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_674__RX_DCOC_RANGE_674___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_674__RX_DCOC_RES_I_674___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_674__RX_DCOC_RES_I_674___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_674__RX_DCOC_RES_Q_674___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_674__RX_DCOC_RES_Q_674___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_674___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_674___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_675 (0x005E4A8C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_675___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_675___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_675__RX_DCOC_RANGE_675___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_675__RX_DCOC_RES_I_675___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_675__RX_DCOC_RES_Q_675___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_675__RX_DCOC_RANGE_675___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_675__RX_DCOC_RANGE_675___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_675__RX_DCOC_RES_I_675___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_675__RX_DCOC_RES_I_675___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_675__RX_DCOC_RES_Q_675___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_675__RX_DCOC_RES_Q_675___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_675___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_675___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_676 (0x005E4A90) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_676___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_676___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_676__RX_DCOC_RANGE_676___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_676__RX_DCOC_RES_I_676___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_676__RX_DCOC_RES_Q_676___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_676__RX_DCOC_RANGE_676___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_676__RX_DCOC_RANGE_676___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_676__RX_DCOC_RES_I_676___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_676__RX_DCOC_RES_I_676___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_676__RX_DCOC_RES_Q_676___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_676__RX_DCOC_RES_Q_676___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_676___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_676___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_677 (0x005E4A94) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_677___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_677___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_677__RX_DCOC_RANGE_677___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_677__RX_DCOC_RES_I_677___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_677__RX_DCOC_RES_Q_677___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_677__RX_DCOC_RANGE_677___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_677__RX_DCOC_RANGE_677___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_677__RX_DCOC_RES_I_677___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_677__RX_DCOC_RES_I_677___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_677__RX_DCOC_RES_Q_677___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_677__RX_DCOC_RES_Q_677___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_677___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_677___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_678 (0x005E4A98) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_678___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_678___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_678__RX_DCOC_RANGE_678___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_678__RX_DCOC_RES_I_678___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_678__RX_DCOC_RES_Q_678___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_678__RX_DCOC_RANGE_678___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_678__RX_DCOC_RANGE_678___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_678__RX_DCOC_RES_I_678___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_678__RX_DCOC_RES_I_678___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_678__RX_DCOC_RES_Q_678___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_678__RX_DCOC_RES_Q_678___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_678___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_678___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_679 (0x005E4A9C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_679___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_679___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_679__RX_DCOC_RANGE_679___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_679__RX_DCOC_RES_I_679___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_679__RX_DCOC_RES_Q_679___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_679__RX_DCOC_RANGE_679___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_679__RX_DCOC_RANGE_679___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_679__RX_DCOC_RES_I_679___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_679__RX_DCOC_RES_I_679___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_679__RX_DCOC_RES_Q_679___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_679__RX_DCOC_RES_Q_679___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_679___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_679___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_680 (0x005E4AA0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_680___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_680___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_680__RX_DCOC_RANGE_680___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_680__RX_DCOC_RES_I_680___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_680__RX_DCOC_RES_Q_680___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_680__RX_DCOC_RANGE_680___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_680__RX_DCOC_RANGE_680___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_680__RX_DCOC_RES_I_680___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_680__RX_DCOC_RES_I_680___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_680__RX_DCOC_RES_Q_680___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_680__RX_DCOC_RES_Q_680___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_680___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_680___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_681 (0x005E4AA4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_681___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_681___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_681__RX_DCOC_RANGE_681___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_681__RX_DCOC_RES_I_681___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_681__RX_DCOC_RES_Q_681___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_681__RX_DCOC_RANGE_681___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_681__RX_DCOC_RANGE_681___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_681__RX_DCOC_RES_I_681___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_681__RX_DCOC_RES_I_681___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_681__RX_DCOC_RES_Q_681___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_681__RX_DCOC_RES_Q_681___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_681___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_681___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_682 (0x005E4AA8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_682___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_682___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_682__RX_DCOC_RANGE_682___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_682__RX_DCOC_RES_I_682___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_682__RX_DCOC_RES_Q_682___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_682__RX_DCOC_RANGE_682___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_682__RX_DCOC_RANGE_682___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_682__RX_DCOC_RES_I_682___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_682__RX_DCOC_RES_I_682___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_682__RX_DCOC_RES_Q_682___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_682__RX_DCOC_RES_Q_682___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_682___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_682___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_683 (0x005E4AAC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_683___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_683___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_683__RX_DCOC_RANGE_683___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_683__RX_DCOC_RES_I_683___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_683__RX_DCOC_RES_Q_683___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_683__RX_DCOC_RANGE_683___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_683__RX_DCOC_RANGE_683___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_683__RX_DCOC_RES_I_683___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_683__RX_DCOC_RES_I_683___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_683__RX_DCOC_RES_Q_683___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_683__RX_DCOC_RES_Q_683___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_683___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_683___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_684 (0x005E4AB0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_684___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_684___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_684__RX_DCOC_RANGE_684___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_684__RX_DCOC_RES_I_684___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_684__RX_DCOC_RES_Q_684___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_684__RX_DCOC_RANGE_684___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_684__RX_DCOC_RANGE_684___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_684__RX_DCOC_RES_I_684___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_684__RX_DCOC_RES_I_684___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_684__RX_DCOC_RES_Q_684___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_684__RX_DCOC_RES_Q_684___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_684___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_684___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_685 (0x005E4AB4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_685___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_685___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_685__RX_DCOC_RANGE_685___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_685__RX_DCOC_RES_I_685___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_685__RX_DCOC_RES_Q_685___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_685__RX_DCOC_RANGE_685___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_685__RX_DCOC_RANGE_685___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_685__RX_DCOC_RES_I_685___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_685__RX_DCOC_RES_I_685___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_685__RX_DCOC_RES_Q_685___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_685__RX_DCOC_RES_Q_685___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_685___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_685___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_686 (0x005E4AB8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_686___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_686___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_686__RX_DCOC_RANGE_686___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_686__RX_DCOC_RES_I_686___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_686__RX_DCOC_RES_Q_686___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_686__RX_DCOC_RANGE_686___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_686__RX_DCOC_RANGE_686___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_686__RX_DCOC_RES_I_686___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_686__RX_DCOC_RES_I_686___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_686__RX_DCOC_RES_Q_686___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_686__RX_DCOC_RES_Q_686___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_686___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_686___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_687 (0x005E4ABC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_687___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_687___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_687__RX_DCOC_RANGE_687___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_687__RX_DCOC_RES_I_687___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_687__RX_DCOC_RES_Q_687___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_687__RX_DCOC_RANGE_687___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_687__RX_DCOC_RANGE_687___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_687__RX_DCOC_RES_I_687___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_687__RX_DCOC_RES_I_687___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_687__RX_DCOC_RES_Q_687___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_687__RX_DCOC_RES_Q_687___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_687___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_687___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_688 (0x005E4AC0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_688___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_688___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_688__RX_DCOC_RANGE_688___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_688__RX_DCOC_RES_I_688___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_688__RX_DCOC_RES_Q_688___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_688__RX_DCOC_RANGE_688___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_688__RX_DCOC_RANGE_688___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_688__RX_DCOC_RES_I_688___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_688__RX_DCOC_RES_I_688___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_688__RX_DCOC_RES_Q_688___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_688__RX_DCOC_RES_Q_688___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_688___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_688___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_689 (0x005E4AC4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_689___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_689___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_689__RX_DCOC_RANGE_689___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_689__RX_DCOC_RES_I_689___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_689__RX_DCOC_RES_Q_689___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_689__RX_DCOC_RANGE_689___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_689__RX_DCOC_RANGE_689___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_689__RX_DCOC_RES_I_689___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_689__RX_DCOC_RES_I_689___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_689__RX_DCOC_RES_Q_689___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_689__RX_DCOC_RES_Q_689___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_689___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_689___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_690 (0x005E4AC8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_690___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_690___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_690__RX_DCOC_RANGE_690___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_690__RX_DCOC_RES_I_690___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_690__RX_DCOC_RES_Q_690___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_690__RX_DCOC_RANGE_690___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_690__RX_DCOC_RANGE_690___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_690__RX_DCOC_RES_I_690___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_690__RX_DCOC_RES_I_690___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_690__RX_DCOC_RES_Q_690___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_690__RX_DCOC_RES_Q_690___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_690___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_690___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_691 (0x005E4ACC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_691___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_691___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_691__RX_DCOC_RANGE_691___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_691__RX_DCOC_RES_I_691___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_691__RX_DCOC_RES_Q_691___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_691__RX_DCOC_RANGE_691___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_691__RX_DCOC_RANGE_691___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_691__RX_DCOC_RES_I_691___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_691__RX_DCOC_RES_I_691___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_691__RX_DCOC_RES_Q_691___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_691__RX_DCOC_RES_Q_691___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_691___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_691___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_692 (0x005E4AD0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_692___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_692___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_692__RX_DCOC_RANGE_692___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_692__RX_DCOC_RES_I_692___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_692__RX_DCOC_RES_Q_692___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_692__RX_DCOC_RANGE_692___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_692__RX_DCOC_RANGE_692___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_692__RX_DCOC_RES_I_692___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_692__RX_DCOC_RES_I_692___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_692__RX_DCOC_RES_Q_692___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_692__RX_DCOC_RES_Q_692___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_692___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_692___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_693 (0x005E4AD4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_693___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_693___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_693__RX_DCOC_RANGE_693___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_693__RX_DCOC_RES_I_693___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_693__RX_DCOC_RES_Q_693___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_693__RX_DCOC_RANGE_693___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_693__RX_DCOC_RANGE_693___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_693__RX_DCOC_RES_I_693___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_693__RX_DCOC_RES_I_693___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_693__RX_DCOC_RES_Q_693___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_693__RX_DCOC_RES_Q_693___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_693___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_693___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_694 (0x005E4AD8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_694___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_694___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_694__RX_DCOC_RANGE_694___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_694__RX_DCOC_RES_I_694___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_694__RX_DCOC_RES_Q_694___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_694__RX_DCOC_RANGE_694___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_694__RX_DCOC_RANGE_694___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_694__RX_DCOC_RES_I_694___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_694__RX_DCOC_RES_I_694___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_694__RX_DCOC_RES_Q_694___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_694__RX_DCOC_RES_Q_694___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_694___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_694___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_695 (0x005E4ADC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_695___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_695___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_695__RX_DCOC_RANGE_695___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_695__RX_DCOC_RES_I_695___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_695__RX_DCOC_RES_Q_695___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_695__RX_DCOC_RANGE_695___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_695__RX_DCOC_RANGE_695___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_695__RX_DCOC_RES_I_695___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_695__RX_DCOC_RES_I_695___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_695__RX_DCOC_RES_Q_695___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_695__RX_DCOC_RES_Q_695___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_695___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_695___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_696 (0x005E4AE0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_696___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_696___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_696__RX_DCOC_RANGE_696___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_696__RX_DCOC_RES_I_696___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_696__RX_DCOC_RES_Q_696___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_696__RX_DCOC_RANGE_696___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_696__RX_DCOC_RANGE_696___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_696__RX_DCOC_RES_I_696___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_696__RX_DCOC_RES_I_696___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_696__RX_DCOC_RES_Q_696___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_696__RX_DCOC_RES_Q_696___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_696___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_696___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_697 (0x005E4AE4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_697___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_697___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_697__RX_DCOC_RANGE_697___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_697__RX_DCOC_RES_I_697___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_697__RX_DCOC_RES_Q_697___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_697__RX_DCOC_RANGE_697___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_697__RX_DCOC_RANGE_697___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_697__RX_DCOC_RES_I_697___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_697__RX_DCOC_RES_I_697___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_697__RX_DCOC_RES_Q_697___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_697__RX_DCOC_RES_Q_697___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_697___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_697___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_698 (0x005E4AE8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_698___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_698___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_698__RX_DCOC_RANGE_698___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_698__RX_DCOC_RES_I_698___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_698__RX_DCOC_RES_Q_698___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_698__RX_DCOC_RANGE_698___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_698__RX_DCOC_RANGE_698___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_698__RX_DCOC_RES_I_698___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_698__RX_DCOC_RES_I_698___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_698__RX_DCOC_RES_Q_698___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_698__RX_DCOC_RES_Q_698___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_698___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_698___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_699 (0x005E4AEC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_699___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_699___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_699__RX_DCOC_RANGE_699___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_699__RX_DCOC_RES_I_699___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_699__RX_DCOC_RES_Q_699___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_699__RX_DCOC_RANGE_699___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_699__RX_DCOC_RANGE_699___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_699__RX_DCOC_RES_I_699___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_699__RX_DCOC_RES_I_699___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_699__RX_DCOC_RES_Q_699___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_699__RX_DCOC_RES_Q_699___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_699___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_699___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_700 (0x005E4AF0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_700___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_700___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_700__RX_DCOC_RANGE_700___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_700__RX_DCOC_RES_I_700___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_700__RX_DCOC_RES_Q_700___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_700__RX_DCOC_RANGE_700___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_700__RX_DCOC_RANGE_700___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_700__RX_DCOC_RES_I_700___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_700__RX_DCOC_RES_I_700___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_700__RX_DCOC_RES_Q_700___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_700__RX_DCOC_RES_Q_700___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_700___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_700___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_701 (0x005E4AF4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_701___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_701___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_701__RX_DCOC_RANGE_701___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_701__RX_DCOC_RES_I_701___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_701__RX_DCOC_RES_Q_701___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_701__RX_DCOC_RANGE_701___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_701__RX_DCOC_RANGE_701___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_701__RX_DCOC_RES_I_701___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_701__RX_DCOC_RES_I_701___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_701__RX_DCOC_RES_Q_701___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_701__RX_DCOC_RES_Q_701___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_701___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_701___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_702 (0x005E4AF8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_702___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_702___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_702__RX_DCOC_RANGE_702___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_702__RX_DCOC_RES_I_702___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_702__RX_DCOC_RES_Q_702___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_702__RX_DCOC_RANGE_702___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_702__RX_DCOC_RANGE_702___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_702__RX_DCOC_RES_I_702___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_702__RX_DCOC_RES_I_702___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_702__RX_DCOC_RES_Q_702___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_702__RX_DCOC_RES_Q_702___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_702___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_702___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_703 (0x005E4AFC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_703___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_703___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_703__RX_DCOC_RANGE_703___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_703__RX_DCOC_RES_I_703___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_703__RX_DCOC_RES_Q_703___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_703__RX_DCOC_RANGE_703___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_703__RX_DCOC_RANGE_703___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_703__RX_DCOC_RES_I_703___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_703__RX_DCOC_RES_I_703___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_703__RX_DCOC_RES_Q_703___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_703__RX_DCOC_RES_Q_703___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_703___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_703___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_704 (0x005E4B00) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_704___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_704___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_704__RX_DCOC_RANGE_704___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_704__RX_DCOC_RES_I_704___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_704__RX_DCOC_RES_Q_704___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_704__RX_DCOC_RANGE_704___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_704__RX_DCOC_RANGE_704___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_704__RX_DCOC_RES_I_704___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_704__RX_DCOC_RES_I_704___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_704__RX_DCOC_RES_Q_704___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_704__RX_DCOC_RES_Q_704___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_704___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_704___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_705 (0x005E4B04) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_705___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_705___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_705__RX_DCOC_RANGE_705___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_705__RX_DCOC_RES_I_705___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_705__RX_DCOC_RES_Q_705___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_705__RX_DCOC_RANGE_705___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_705__RX_DCOC_RANGE_705___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_705__RX_DCOC_RES_I_705___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_705__RX_DCOC_RES_I_705___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_705__RX_DCOC_RES_Q_705___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_705__RX_DCOC_RES_Q_705___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_705___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_705___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_706 (0x005E4B08) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_706___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_706___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_706__RX_DCOC_RANGE_706___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_706__RX_DCOC_RES_I_706___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_706__RX_DCOC_RES_Q_706___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_706__RX_DCOC_RANGE_706___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_706__RX_DCOC_RANGE_706___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_706__RX_DCOC_RES_I_706___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_706__RX_DCOC_RES_I_706___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_706__RX_DCOC_RES_Q_706___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_706__RX_DCOC_RES_Q_706___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_706___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_706___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_707 (0x005E4B0C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_707___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_707___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_707__RX_DCOC_RANGE_707___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_707__RX_DCOC_RES_I_707___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_707__RX_DCOC_RES_Q_707___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_707__RX_DCOC_RANGE_707___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_707__RX_DCOC_RANGE_707___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_707__RX_DCOC_RES_I_707___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_707__RX_DCOC_RES_I_707___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_707__RX_DCOC_RES_Q_707___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_707__RX_DCOC_RES_Q_707___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_707___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_707___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_708 (0x005E4B10) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_708___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_708___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_708__RX_DCOC_RANGE_708___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_708__RX_DCOC_RES_I_708___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_708__RX_DCOC_RES_Q_708___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_708__RX_DCOC_RANGE_708___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_708__RX_DCOC_RANGE_708___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_708__RX_DCOC_RES_I_708___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_708__RX_DCOC_RES_I_708___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_708__RX_DCOC_RES_Q_708___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_708__RX_DCOC_RES_Q_708___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_708___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_708___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_709 (0x005E4B14) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_709___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_709___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_709__RX_DCOC_RANGE_709___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_709__RX_DCOC_RES_I_709___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_709__RX_DCOC_RES_Q_709___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_709__RX_DCOC_RANGE_709___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_709__RX_DCOC_RANGE_709___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_709__RX_DCOC_RES_I_709___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_709__RX_DCOC_RES_I_709___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_709__RX_DCOC_RES_Q_709___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_709__RX_DCOC_RES_Q_709___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_709___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_709___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_710 (0x005E4B18) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_710___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_710___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_710__RX_DCOC_RANGE_710___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_710__RX_DCOC_RES_I_710___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_710__RX_DCOC_RES_Q_710___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_710__RX_DCOC_RANGE_710___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_710__RX_DCOC_RANGE_710___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_710__RX_DCOC_RES_I_710___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_710__RX_DCOC_RES_I_710___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_710__RX_DCOC_RES_Q_710___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_710__RX_DCOC_RES_Q_710___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_710___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_710___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_711 (0x005E4B1C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_711___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_711___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_711__RX_DCOC_RANGE_711___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_711__RX_DCOC_RES_I_711___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_711__RX_DCOC_RES_Q_711___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_711__RX_DCOC_RANGE_711___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_711__RX_DCOC_RANGE_711___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_711__RX_DCOC_RES_I_711___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_711__RX_DCOC_RES_I_711___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_711__RX_DCOC_RES_Q_711___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_711__RX_DCOC_RES_Q_711___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_711___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_711___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_712 (0x005E4B20) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_712___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_712___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_712__RX_DCOC_RANGE_712___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_712__RX_DCOC_RES_I_712___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_712__RX_DCOC_RES_Q_712___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_712__RX_DCOC_RANGE_712___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_712__RX_DCOC_RANGE_712___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_712__RX_DCOC_RES_I_712___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_712__RX_DCOC_RES_I_712___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_712__RX_DCOC_RES_Q_712___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_712__RX_DCOC_RES_Q_712___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_712___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_712___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_713 (0x005E4B24) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_713___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_713___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_713__RX_DCOC_RANGE_713___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_713__RX_DCOC_RES_I_713___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_713__RX_DCOC_RES_Q_713___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_713__RX_DCOC_RANGE_713___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_713__RX_DCOC_RANGE_713___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_713__RX_DCOC_RES_I_713___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_713__RX_DCOC_RES_I_713___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_713__RX_DCOC_RES_Q_713___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_713__RX_DCOC_RES_Q_713___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_713___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_713___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_714 (0x005E4B28) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_714___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_714___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_714__RX_DCOC_RANGE_714___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_714__RX_DCOC_RES_I_714___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_714__RX_DCOC_RES_Q_714___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_714__RX_DCOC_RANGE_714___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_714__RX_DCOC_RANGE_714___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_714__RX_DCOC_RES_I_714___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_714__RX_DCOC_RES_I_714___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_714__RX_DCOC_RES_Q_714___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_714__RX_DCOC_RES_Q_714___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_714___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_714___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_715 (0x005E4B2C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_715___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_715___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_715__RX_DCOC_RANGE_715___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_715__RX_DCOC_RES_I_715___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_715__RX_DCOC_RES_Q_715___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_715__RX_DCOC_RANGE_715___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_715__RX_DCOC_RANGE_715___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_715__RX_DCOC_RES_I_715___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_715__RX_DCOC_RES_I_715___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_715__RX_DCOC_RES_Q_715___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_715__RX_DCOC_RES_Q_715___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_715___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_715___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_716 (0x005E4B30) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_716___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_716___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_716__RX_DCOC_RANGE_716___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_716__RX_DCOC_RES_I_716___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_716__RX_DCOC_RES_Q_716___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_716__RX_DCOC_RANGE_716___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_716__RX_DCOC_RANGE_716___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_716__RX_DCOC_RES_I_716___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_716__RX_DCOC_RES_I_716___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_716__RX_DCOC_RES_Q_716___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_716__RX_DCOC_RES_Q_716___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_716___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_716___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_717 (0x005E4B34) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_717___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_717___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_717__RX_DCOC_RANGE_717___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_717__RX_DCOC_RES_I_717___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_717__RX_DCOC_RES_Q_717___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_717__RX_DCOC_RANGE_717___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_717__RX_DCOC_RANGE_717___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_717__RX_DCOC_RES_I_717___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_717__RX_DCOC_RES_I_717___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_717__RX_DCOC_RES_Q_717___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_717__RX_DCOC_RES_Q_717___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_717___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_717___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_718 (0x005E4B38) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_718___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_718___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_718__RX_DCOC_RANGE_718___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_718__RX_DCOC_RES_I_718___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_718__RX_DCOC_RES_Q_718___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_718__RX_DCOC_RANGE_718___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_718__RX_DCOC_RANGE_718___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_718__RX_DCOC_RES_I_718___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_718__RX_DCOC_RES_I_718___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_718__RX_DCOC_RES_Q_718___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_718__RX_DCOC_RES_Q_718___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_718___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_718___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_719 (0x005E4B3C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_719___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_719___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_719__RX_DCOC_RANGE_719___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_719__RX_DCOC_RES_I_719___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_719__RX_DCOC_RES_Q_719___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_719__RX_DCOC_RANGE_719___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_719__RX_DCOC_RANGE_719___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_719__RX_DCOC_RES_I_719___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_719__RX_DCOC_RES_I_719___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_719__RX_DCOC_RES_Q_719___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_719__RX_DCOC_RES_Q_719___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_719___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_719___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_720 (0x005E4B40) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_720___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_720___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_720__RX_DCOC_RANGE_720___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_720__RX_DCOC_RES_I_720___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_720__RX_DCOC_RES_Q_720___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_720__RX_DCOC_RANGE_720___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_720__RX_DCOC_RANGE_720___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_720__RX_DCOC_RES_I_720___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_720__RX_DCOC_RES_I_720___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_720__RX_DCOC_RES_Q_720___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_720__RX_DCOC_RES_Q_720___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_720___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_720___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_721 (0x005E4B44) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_721___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_721___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_721__RX_DCOC_RANGE_721___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_721__RX_DCOC_RES_I_721___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_721__RX_DCOC_RES_Q_721___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_721__RX_DCOC_RANGE_721___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_721__RX_DCOC_RANGE_721___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_721__RX_DCOC_RES_I_721___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_721__RX_DCOC_RES_I_721___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_721__RX_DCOC_RES_Q_721___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_721__RX_DCOC_RES_Q_721___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_721___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_721___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_722 (0x005E4B48) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_722___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_722___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_722__RX_DCOC_RANGE_722___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_722__RX_DCOC_RES_I_722___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_722__RX_DCOC_RES_Q_722___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_722__RX_DCOC_RANGE_722___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_722__RX_DCOC_RANGE_722___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_722__RX_DCOC_RES_I_722___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_722__RX_DCOC_RES_I_722___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_722__RX_DCOC_RES_Q_722___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_722__RX_DCOC_RES_Q_722___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_722___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_722___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_723 (0x005E4B4C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_723___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_723___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_723__RX_DCOC_RANGE_723___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_723__RX_DCOC_RES_I_723___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_723__RX_DCOC_RES_Q_723___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_723__RX_DCOC_RANGE_723___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_723__RX_DCOC_RANGE_723___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_723__RX_DCOC_RES_I_723___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_723__RX_DCOC_RES_I_723___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_723__RX_DCOC_RES_Q_723___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_723__RX_DCOC_RES_Q_723___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_723___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_723___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_724 (0x005E4B50) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_724___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_724___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_724__RX_DCOC_RANGE_724___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_724__RX_DCOC_RES_I_724___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_724__RX_DCOC_RES_Q_724___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_724__RX_DCOC_RANGE_724___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_724__RX_DCOC_RANGE_724___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_724__RX_DCOC_RES_I_724___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_724__RX_DCOC_RES_I_724___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_724__RX_DCOC_RES_Q_724___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_724__RX_DCOC_RES_Q_724___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_724___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_724___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_725 (0x005E4B54) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_725___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_725___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_725__RX_DCOC_RANGE_725___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_725__RX_DCOC_RES_I_725___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_725__RX_DCOC_RES_Q_725___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_725__RX_DCOC_RANGE_725___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_725__RX_DCOC_RANGE_725___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_725__RX_DCOC_RES_I_725___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_725__RX_DCOC_RES_I_725___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_725__RX_DCOC_RES_Q_725___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_725__RX_DCOC_RES_Q_725___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_725___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_725___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_726 (0x005E4B58) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_726___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_726___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_726__RX_DCOC_RANGE_726___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_726__RX_DCOC_RES_I_726___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_726__RX_DCOC_RES_Q_726___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_726__RX_DCOC_RANGE_726___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_726__RX_DCOC_RANGE_726___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_726__RX_DCOC_RES_I_726___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_726__RX_DCOC_RES_I_726___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_726__RX_DCOC_RES_Q_726___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_726__RX_DCOC_RES_Q_726___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_726___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_726___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_727 (0x005E4B5C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_727___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_727___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_727__RX_DCOC_RANGE_727___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_727__RX_DCOC_RES_I_727___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_727__RX_DCOC_RES_Q_727___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_727__RX_DCOC_RANGE_727___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_727__RX_DCOC_RANGE_727___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_727__RX_DCOC_RES_I_727___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_727__RX_DCOC_RES_I_727___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_727__RX_DCOC_RES_Q_727___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_727__RX_DCOC_RES_Q_727___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_727___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_727___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_728 (0x005E4B60) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_728___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_728___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_728__RX_DCOC_RANGE_728___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_728__RX_DCOC_RES_I_728___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_728__RX_DCOC_RES_Q_728___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_728__RX_DCOC_RANGE_728___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_728__RX_DCOC_RANGE_728___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_728__RX_DCOC_RES_I_728___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_728__RX_DCOC_RES_I_728___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_728__RX_DCOC_RES_Q_728___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_728__RX_DCOC_RES_Q_728___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_728___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_728___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_729 (0x005E4B64) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_729___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_729___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_729__RX_DCOC_RANGE_729___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_729__RX_DCOC_RES_I_729___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_729__RX_DCOC_RES_Q_729___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_729__RX_DCOC_RANGE_729___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_729__RX_DCOC_RANGE_729___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_729__RX_DCOC_RES_I_729___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_729__RX_DCOC_RES_I_729___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_729__RX_DCOC_RES_Q_729___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_729__RX_DCOC_RES_Q_729___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_729___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_729___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_730 (0x005E4B68) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_730___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_730___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_730__RX_DCOC_RANGE_730___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_730__RX_DCOC_RES_I_730___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_730__RX_DCOC_RES_Q_730___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_730__RX_DCOC_RANGE_730___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_730__RX_DCOC_RANGE_730___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_730__RX_DCOC_RES_I_730___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_730__RX_DCOC_RES_I_730___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_730__RX_DCOC_RES_Q_730___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_730__RX_DCOC_RES_Q_730___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_730___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_730___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_731 (0x005E4B6C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_731___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_731___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_731__RX_DCOC_RANGE_731___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_731__RX_DCOC_RES_I_731___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_731__RX_DCOC_RES_Q_731___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_731__RX_DCOC_RANGE_731___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_731__RX_DCOC_RANGE_731___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_731__RX_DCOC_RES_I_731___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_731__RX_DCOC_RES_I_731___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_731__RX_DCOC_RES_Q_731___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_731__RX_DCOC_RES_Q_731___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_731___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_731___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_732 (0x005E4B70) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_732___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_732___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_732__RX_DCOC_RANGE_732___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_732__RX_DCOC_RES_I_732___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_732__RX_DCOC_RES_Q_732___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_732__RX_DCOC_RANGE_732___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_732__RX_DCOC_RANGE_732___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_732__RX_DCOC_RES_I_732___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_732__RX_DCOC_RES_I_732___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_732__RX_DCOC_RES_Q_732___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_732__RX_DCOC_RES_Q_732___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_732___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_732___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_733 (0x005E4B74) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_733___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_733___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_733__RX_DCOC_RANGE_733___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_733__RX_DCOC_RES_I_733___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_733__RX_DCOC_RES_Q_733___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_733__RX_DCOC_RANGE_733___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_733__RX_DCOC_RANGE_733___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_733__RX_DCOC_RES_I_733___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_733__RX_DCOC_RES_I_733___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_733__RX_DCOC_RES_Q_733___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_733__RX_DCOC_RES_Q_733___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_733___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_733___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_734 (0x005E4B78) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_734___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_734___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_734__RX_DCOC_RANGE_734___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_734__RX_DCOC_RES_I_734___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_734__RX_DCOC_RES_Q_734___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_734__RX_DCOC_RANGE_734___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_734__RX_DCOC_RANGE_734___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_734__RX_DCOC_RES_I_734___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_734__RX_DCOC_RES_I_734___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_734__RX_DCOC_RES_Q_734___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_734__RX_DCOC_RES_Q_734___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_734___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_734___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_735 (0x005E4B7C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_735___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_735___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_735__RX_DCOC_RANGE_735___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_735__RX_DCOC_RES_I_735___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_735__RX_DCOC_RES_Q_735___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_735__RX_DCOC_RANGE_735___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_735__RX_DCOC_RANGE_735___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_735__RX_DCOC_RES_I_735___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_735__RX_DCOC_RES_I_735___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_735__RX_DCOC_RES_Q_735___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_735__RX_DCOC_RES_Q_735___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_735___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_735___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_736 (0x005E4B80) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_736___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_736___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_736__RX_DCOC_RANGE_736___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_736__RX_DCOC_RES_I_736___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_736__RX_DCOC_RES_Q_736___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_736__RX_DCOC_RANGE_736___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_736__RX_DCOC_RANGE_736___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_736__RX_DCOC_RES_I_736___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_736__RX_DCOC_RES_I_736___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_736__RX_DCOC_RES_Q_736___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_736__RX_DCOC_RES_Q_736___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_736___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_736___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_737 (0x005E4B84) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_737___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_737___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_737__RX_DCOC_RANGE_737___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_737__RX_DCOC_RES_I_737___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_737__RX_DCOC_RES_Q_737___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_737__RX_DCOC_RANGE_737___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_737__RX_DCOC_RANGE_737___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_737__RX_DCOC_RES_I_737___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_737__RX_DCOC_RES_I_737___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_737__RX_DCOC_RES_Q_737___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_737__RX_DCOC_RES_Q_737___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_737___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_737___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_738 (0x005E4B88) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_738___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_738___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_738__RX_DCOC_RANGE_738___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_738__RX_DCOC_RES_I_738___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_738__RX_DCOC_RES_Q_738___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_738__RX_DCOC_RANGE_738___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_738__RX_DCOC_RANGE_738___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_738__RX_DCOC_RES_I_738___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_738__RX_DCOC_RES_I_738___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_738__RX_DCOC_RES_Q_738___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_738__RX_DCOC_RES_Q_738___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_738___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_738___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_739 (0x005E4B8C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_739___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_739___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_739__RX_DCOC_RANGE_739___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_739__RX_DCOC_RES_I_739___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_739__RX_DCOC_RES_Q_739___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_739__RX_DCOC_RANGE_739___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_739__RX_DCOC_RANGE_739___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_739__RX_DCOC_RES_I_739___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_739__RX_DCOC_RES_I_739___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_739__RX_DCOC_RES_Q_739___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_739__RX_DCOC_RES_Q_739___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_739___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_739___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_740 (0x005E4B90) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_740___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_740___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_740__RX_DCOC_RANGE_740___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_740__RX_DCOC_RES_I_740___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_740__RX_DCOC_RES_Q_740___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_740__RX_DCOC_RANGE_740___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_740__RX_DCOC_RANGE_740___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_740__RX_DCOC_RES_I_740___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_740__RX_DCOC_RES_I_740___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_740__RX_DCOC_RES_Q_740___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_740__RX_DCOC_RES_Q_740___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_740___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_740___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_741 (0x005E4B94) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_741___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_741___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_741__RX_DCOC_RANGE_741___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_741__RX_DCOC_RES_I_741___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_741__RX_DCOC_RES_Q_741___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_741__RX_DCOC_RANGE_741___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_741__RX_DCOC_RANGE_741___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_741__RX_DCOC_RES_I_741___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_741__RX_DCOC_RES_I_741___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_741__RX_DCOC_RES_Q_741___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_741__RX_DCOC_RES_Q_741___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_741___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_741___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_742 (0x005E4B98) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_742___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_742___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_742__RX_DCOC_RANGE_742___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_742__RX_DCOC_RES_I_742___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_742__RX_DCOC_RES_Q_742___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_742__RX_DCOC_RANGE_742___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_742__RX_DCOC_RANGE_742___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_742__RX_DCOC_RES_I_742___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_742__RX_DCOC_RES_I_742___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_742__RX_DCOC_RES_Q_742___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_742__RX_DCOC_RES_Q_742___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_742___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_742___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_743 (0x005E4B9C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_743___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_743___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_743__RX_DCOC_RANGE_743___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_743__RX_DCOC_RES_I_743___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_743__RX_DCOC_RES_Q_743___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_743__RX_DCOC_RANGE_743___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_743__RX_DCOC_RANGE_743___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_743__RX_DCOC_RES_I_743___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_743__RX_DCOC_RES_I_743___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_743__RX_DCOC_RES_Q_743___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_743__RX_DCOC_RES_Q_743___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_743___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_743___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_744 (0x005E4BA0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_744___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_744___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_744__RX_DCOC_RANGE_744___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_744__RX_DCOC_RES_I_744___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_744__RX_DCOC_RES_Q_744___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_744__RX_DCOC_RANGE_744___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_744__RX_DCOC_RANGE_744___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_744__RX_DCOC_RES_I_744___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_744__RX_DCOC_RES_I_744___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_744__RX_DCOC_RES_Q_744___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_744__RX_DCOC_RES_Q_744___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_744___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_744___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_745 (0x005E4BA4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_745___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_745___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_745__RX_DCOC_RANGE_745___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_745__RX_DCOC_RES_I_745___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_745__RX_DCOC_RES_Q_745___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_745__RX_DCOC_RANGE_745___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_745__RX_DCOC_RANGE_745___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_745__RX_DCOC_RES_I_745___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_745__RX_DCOC_RES_I_745___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_745__RX_DCOC_RES_Q_745___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_745__RX_DCOC_RES_Q_745___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_745___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_745___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_746 (0x005E4BA8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_746___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_746___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_746__RX_DCOC_RANGE_746___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_746__RX_DCOC_RES_I_746___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_746__RX_DCOC_RES_Q_746___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_746__RX_DCOC_RANGE_746___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_746__RX_DCOC_RANGE_746___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_746__RX_DCOC_RES_I_746___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_746__RX_DCOC_RES_I_746___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_746__RX_DCOC_RES_Q_746___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_746__RX_DCOC_RES_Q_746___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_746___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_746___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_747 (0x005E4BAC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_747___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_747___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_747__RX_DCOC_RANGE_747___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_747__RX_DCOC_RES_I_747___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_747__RX_DCOC_RES_Q_747___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_747__RX_DCOC_RANGE_747___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_747__RX_DCOC_RANGE_747___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_747__RX_DCOC_RES_I_747___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_747__RX_DCOC_RES_I_747___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_747__RX_DCOC_RES_Q_747___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_747__RX_DCOC_RES_Q_747___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_747___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_747___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_748 (0x005E4BB0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_748___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_748___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_748__RX_DCOC_RANGE_748___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_748__RX_DCOC_RES_I_748___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_748__RX_DCOC_RES_Q_748___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_748__RX_DCOC_RANGE_748___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_748__RX_DCOC_RANGE_748___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_748__RX_DCOC_RES_I_748___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_748__RX_DCOC_RES_I_748___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_748__RX_DCOC_RES_Q_748___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_748__RX_DCOC_RES_Q_748___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_748___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_748___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_749 (0x005E4BB4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_749___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_749___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_749__RX_DCOC_RANGE_749___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_749__RX_DCOC_RES_I_749___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_749__RX_DCOC_RES_Q_749___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_749__RX_DCOC_RANGE_749___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_749__RX_DCOC_RANGE_749___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_749__RX_DCOC_RES_I_749___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_749__RX_DCOC_RES_I_749___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_749__RX_DCOC_RES_Q_749___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_749__RX_DCOC_RES_Q_749___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_749___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_749___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_750 (0x005E4BB8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_750___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_750___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_750__RX_DCOC_RANGE_750___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_750__RX_DCOC_RES_I_750___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_750__RX_DCOC_RES_Q_750___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_750__RX_DCOC_RANGE_750___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_750__RX_DCOC_RANGE_750___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_750__RX_DCOC_RES_I_750___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_750__RX_DCOC_RES_I_750___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_750__RX_DCOC_RES_Q_750___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_750__RX_DCOC_RES_Q_750___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_750___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_750___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_751 (0x005E4BBC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_751___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_751___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_751__RX_DCOC_RANGE_751___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_751__RX_DCOC_RES_I_751___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_751__RX_DCOC_RES_Q_751___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_751__RX_DCOC_RANGE_751___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_751__RX_DCOC_RANGE_751___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_751__RX_DCOC_RES_I_751___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_751__RX_DCOC_RES_I_751___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_751__RX_DCOC_RES_Q_751___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_751__RX_DCOC_RES_Q_751___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_751___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_751___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_752 (0x005E4BC0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_752___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_752___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_752__RX_DCOC_RANGE_752___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_752__RX_DCOC_RES_I_752___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_752__RX_DCOC_RES_Q_752___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_752__RX_DCOC_RANGE_752___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_752__RX_DCOC_RANGE_752___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_752__RX_DCOC_RES_I_752___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_752__RX_DCOC_RES_I_752___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_752__RX_DCOC_RES_Q_752___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_752__RX_DCOC_RES_Q_752___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_752___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_752___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_753 (0x005E4BC4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_753___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_753___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_753__RX_DCOC_RANGE_753___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_753__RX_DCOC_RES_I_753___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_753__RX_DCOC_RES_Q_753___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_753__RX_DCOC_RANGE_753___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_753__RX_DCOC_RANGE_753___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_753__RX_DCOC_RES_I_753___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_753__RX_DCOC_RES_I_753___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_753__RX_DCOC_RES_Q_753___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_753__RX_DCOC_RES_Q_753___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_753___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_753___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_754 (0x005E4BC8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_754___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_754___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_754__RX_DCOC_RANGE_754___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_754__RX_DCOC_RES_I_754___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_754__RX_DCOC_RES_Q_754___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_754__RX_DCOC_RANGE_754___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_754__RX_DCOC_RANGE_754___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_754__RX_DCOC_RES_I_754___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_754__RX_DCOC_RES_I_754___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_754__RX_DCOC_RES_Q_754___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_754__RX_DCOC_RES_Q_754___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_754___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_754___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_755 (0x005E4BCC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_755___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_755___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_755__RX_DCOC_RANGE_755___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_755__RX_DCOC_RES_I_755___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_755__RX_DCOC_RES_Q_755___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_755__RX_DCOC_RANGE_755___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_755__RX_DCOC_RANGE_755___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_755__RX_DCOC_RES_I_755___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_755__RX_DCOC_RES_I_755___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_755__RX_DCOC_RES_Q_755___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_755__RX_DCOC_RES_Q_755___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_755___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_755___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_756 (0x005E4BD0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_756___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_756___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_756__RX_DCOC_RANGE_756___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_756__RX_DCOC_RES_I_756___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_756__RX_DCOC_RES_Q_756___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_756__RX_DCOC_RANGE_756___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_756__RX_DCOC_RANGE_756___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_756__RX_DCOC_RES_I_756___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_756__RX_DCOC_RES_I_756___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_756__RX_DCOC_RES_Q_756___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_756__RX_DCOC_RES_Q_756___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_756___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_756___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_757 (0x005E4BD4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_757___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_757___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_757__RX_DCOC_RANGE_757___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_757__RX_DCOC_RES_I_757___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_757__RX_DCOC_RES_Q_757___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_757__RX_DCOC_RANGE_757___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_757__RX_DCOC_RANGE_757___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_757__RX_DCOC_RES_I_757___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_757__RX_DCOC_RES_I_757___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_757__RX_DCOC_RES_Q_757___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_757__RX_DCOC_RES_Q_757___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_757___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_757___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_758 (0x005E4BD8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_758___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_758___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_758__RX_DCOC_RANGE_758___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_758__RX_DCOC_RES_I_758___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_758__RX_DCOC_RES_Q_758___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_758__RX_DCOC_RANGE_758___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_758__RX_DCOC_RANGE_758___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_758__RX_DCOC_RES_I_758___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_758__RX_DCOC_RES_I_758___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_758__RX_DCOC_RES_Q_758___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_758__RX_DCOC_RES_Q_758___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_758___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_758___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_759 (0x005E4BDC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_759___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_759___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_759__RX_DCOC_RANGE_759___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_759__RX_DCOC_RES_I_759___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_759__RX_DCOC_RES_Q_759___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_759__RX_DCOC_RANGE_759___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_759__RX_DCOC_RANGE_759___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_759__RX_DCOC_RES_I_759___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_759__RX_DCOC_RES_I_759___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_759__RX_DCOC_RES_Q_759___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_759__RX_DCOC_RES_Q_759___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_759___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_759___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_760 (0x005E4BE0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_760___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_760___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_760__RX_DCOC_RANGE_760___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_760__RX_DCOC_RES_I_760___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_760__RX_DCOC_RES_Q_760___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_760__RX_DCOC_RANGE_760___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_760__RX_DCOC_RANGE_760___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_760__RX_DCOC_RES_I_760___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_760__RX_DCOC_RES_I_760___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_760__RX_DCOC_RES_Q_760___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_760__RX_DCOC_RES_Q_760___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_760___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_760___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_761 (0x005E4BE4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_761___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_761___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_761__RX_DCOC_RANGE_761___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_761__RX_DCOC_RES_I_761___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_761__RX_DCOC_RES_Q_761___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_761__RX_DCOC_RANGE_761___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_761__RX_DCOC_RANGE_761___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_761__RX_DCOC_RES_I_761___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_761__RX_DCOC_RES_I_761___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_761__RX_DCOC_RES_Q_761___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_761__RX_DCOC_RES_Q_761___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_761___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_761___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_762 (0x005E4BE8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_762___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_762___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_762__RX_DCOC_RANGE_762___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_762__RX_DCOC_RES_I_762___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_762__RX_DCOC_RES_Q_762___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_762__RX_DCOC_RANGE_762___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_762__RX_DCOC_RANGE_762___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_762__RX_DCOC_RES_I_762___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_762__RX_DCOC_RES_I_762___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_762__RX_DCOC_RES_Q_762___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_762__RX_DCOC_RES_Q_762___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_762___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_762___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_763 (0x005E4BEC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_763___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_763___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_763__RX_DCOC_RANGE_763___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_763__RX_DCOC_RES_I_763___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_763__RX_DCOC_RES_Q_763___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_763__RX_DCOC_RANGE_763___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_763__RX_DCOC_RANGE_763___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_763__RX_DCOC_RES_I_763___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_763__RX_DCOC_RES_I_763___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_763__RX_DCOC_RES_Q_763___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_763__RX_DCOC_RES_Q_763___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_763___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_763___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_764 (0x005E4BF0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_764___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_764___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_764__RX_DCOC_RANGE_764___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_764__RX_DCOC_RES_I_764___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_764__RX_DCOC_RES_Q_764___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_764__RX_DCOC_RANGE_764___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_764__RX_DCOC_RANGE_764___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_764__RX_DCOC_RES_I_764___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_764__RX_DCOC_RES_I_764___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_764__RX_DCOC_RES_Q_764___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_764__RX_DCOC_RES_Q_764___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_764___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_764___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_765 (0x005E4BF4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_765___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_765___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_765__RX_DCOC_RANGE_765___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_765__RX_DCOC_RES_I_765___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_765__RX_DCOC_RES_Q_765___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_765__RX_DCOC_RANGE_765___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_765__RX_DCOC_RANGE_765___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_765__RX_DCOC_RES_I_765___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_765__RX_DCOC_RES_I_765___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_765__RX_DCOC_RES_Q_765___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_765__RX_DCOC_RES_Q_765___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_765___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_765___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_766 (0x005E4BF8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_766___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_766___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_766__RX_DCOC_RANGE_766___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_766__RX_DCOC_RES_I_766___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_766__RX_DCOC_RES_Q_766___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_766__RX_DCOC_RANGE_766___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_766__RX_DCOC_RANGE_766___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_766__RX_DCOC_RES_I_766___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_766__RX_DCOC_RES_I_766___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_766__RX_DCOC_RES_Q_766___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_766__RX_DCOC_RES_Q_766___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_766___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_766___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_767 (0x005E4BFC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_767___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_767___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_767__RX_DCOC_RANGE_767___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_767__RX_DCOC_RES_I_767___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_767__RX_DCOC_RES_Q_767___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_767__RX_DCOC_RANGE_767___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_767__RX_DCOC_RANGE_767___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_767__RX_DCOC_RES_I_767___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_767__RX_DCOC_RES_I_767___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_767__RX_DCOC_RES_Q_767___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_767__RX_DCOC_RES_Q_767___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_767___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_767___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_768 (0x005E4C00) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_768___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_768___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_768__RX_DCOC_RANGE_768___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_768__RX_DCOC_RES_I_768___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_768__RX_DCOC_RES_Q_768___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_768__RX_DCOC_RANGE_768___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_768__RX_DCOC_RANGE_768___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_768__RX_DCOC_RES_I_768___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_768__RX_DCOC_RES_I_768___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_768__RX_DCOC_RES_Q_768___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_768__RX_DCOC_RES_Q_768___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_768___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_768___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_769 (0x005E4C04) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_769___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_769___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_769__RX_DCOC_RANGE_769___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_769__RX_DCOC_RES_I_769___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_769__RX_DCOC_RES_Q_769___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_769__RX_DCOC_RANGE_769___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_769__RX_DCOC_RANGE_769___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_769__RX_DCOC_RES_I_769___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_769__RX_DCOC_RES_I_769___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_769__RX_DCOC_RES_Q_769___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_769__RX_DCOC_RES_Q_769___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_769___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_769___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_770 (0x005E4C08) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_770___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_770___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_770__RX_DCOC_RANGE_770___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_770__RX_DCOC_RES_I_770___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_770__RX_DCOC_RES_Q_770___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_770__RX_DCOC_RANGE_770___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_770__RX_DCOC_RANGE_770___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_770__RX_DCOC_RES_I_770___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_770__RX_DCOC_RES_I_770___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_770__RX_DCOC_RES_Q_770___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_770__RX_DCOC_RES_Q_770___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_770___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_770___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_771 (0x005E4C0C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_771___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_771___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_771__RX_DCOC_RANGE_771___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_771__RX_DCOC_RES_I_771___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_771__RX_DCOC_RES_Q_771___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_771__RX_DCOC_RANGE_771___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_771__RX_DCOC_RANGE_771___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_771__RX_DCOC_RES_I_771___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_771__RX_DCOC_RES_I_771___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_771__RX_DCOC_RES_Q_771___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_771__RX_DCOC_RES_Q_771___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_771___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_771___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_772 (0x005E4C10) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_772___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_772___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_772__RX_DCOC_RANGE_772___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_772__RX_DCOC_RES_I_772___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_772__RX_DCOC_RES_Q_772___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_772__RX_DCOC_RANGE_772___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_772__RX_DCOC_RANGE_772___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_772__RX_DCOC_RES_I_772___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_772__RX_DCOC_RES_I_772___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_772__RX_DCOC_RES_Q_772___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_772__RX_DCOC_RES_Q_772___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_772___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_772___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_773 (0x005E4C14) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_773___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_773___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_773__RX_DCOC_RANGE_773___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_773__RX_DCOC_RES_I_773___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_773__RX_DCOC_RES_Q_773___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_773__RX_DCOC_RANGE_773___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_773__RX_DCOC_RANGE_773___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_773__RX_DCOC_RES_I_773___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_773__RX_DCOC_RES_I_773___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_773__RX_DCOC_RES_Q_773___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_773__RX_DCOC_RES_Q_773___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_773___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_773___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_774 (0x005E4C18) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_774___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_774___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_774__RX_DCOC_RANGE_774___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_774__RX_DCOC_RES_I_774___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_774__RX_DCOC_RES_Q_774___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_774__RX_DCOC_RANGE_774___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_774__RX_DCOC_RANGE_774___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_774__RX_DCOC_RES_I_774___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_774__RX_DCOC_RES_I_774___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_774__RX_DCOC_RES_Q_774___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_774__RX_DCOC_RES_Q_774___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_774___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_774___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_775 (0x005E4C1C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_775___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_775___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_775__RX_DCOC_RANGE_775___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_775__RX_DCOC_RES_I_775___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_775__RX_DCOC_RES_Q_775___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_775__RX_DCOC_RANGE_775___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_775__RX_DCOC_RANGE_775___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_775__RX_DCOC_RES_I_775___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_775__RX_DCOC_RES_I_775___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_775__RX_DCOC_RES_Q_775___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_775__RX_DCOC_RES_Q_775___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_775___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_775___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_776 (0x005E4C20) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_776___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_776___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_776__RX_DCOC_RANGE_776___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_776__RX_DCOC_RES_I_776___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_776__RX_DCOC_RES_Q_776___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_776__RX_DCOC_RANGE_776___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_776__RX_DCOC_RANGE_776___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_776__RX_DCOC_RES_I_776___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_776__RX_DCOC_RES_I_776___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_776__RX_DCOC_RES_Q_776___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_776__RX_DCOC_RES_Q_776___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_776___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_776___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_777 (0x005E4C24) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_777___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_777___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_777__RX_DCOC_RANGE_777___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_777__RX_DCOC_RES_I_777___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_777__RX_DCOC_RES_Q_777___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_777__RX_DCOC_RANGE_777___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_777__RX_DCOC_RANGE_777___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_777__RX_DCOC_RES_I_777___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_777__RX_DCOC_RES_I_777___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_777__RX_DCOC_RES_Q_777___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_777__RX_DCOC_RES_Q_777___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_777___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_777___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_778 (0x005E4C28) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_778___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_778___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_778__RX_DCOC_RANGE_778___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_778__RX_DCOC_RES_I_778___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_778__RX_DCOC_RES_Q_778___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_778__RX_DCOC_RANGE_778___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_778__RX_DCOC_RANGE_778___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_778__RX_DCOC_RES_I_778___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_778__RX_DCOC_RES_I_778___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_778__RX_DCOC_RES_Q_778___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_778__RX_DCOC_RES_Q_778___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_778___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_778___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_779 (0x005E4C2C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_779___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_779___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_779__RX_DCOC_RANGE_779___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_779__RX_DCOC_RES_I_779___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_779__RX_DCOC_RES_Q_779___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_779__RX_DCOC_RANGE_779___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_779__RX_DCOC_RANGE_779___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_779__RX_DCOC_RES_I_779___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_779__RX_DCOC_RES_I_779___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_779__RX_DCOC_RES_Q_779___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_779__RX_DCOC_RES_Q_779___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_779___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_779___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_780 (0x005E4C30) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_780___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_780___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_780__RX_DCOC_RANGE_780___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_780__RX_DCOC_RES_I_780___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_780__RX_DCOC_RES_Q_780___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_780__RX_DCOC_RANGE_780___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_780__RX_DCOC_RANGE_780___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_780__RX_DCOC_RES_I_780___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_780__RX_DCOC_RES_I_780___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_780__RX_DCOC_RES_Q_780___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_780__RX_DCOC_RES_Q_780___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_780___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_780___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_781 (0x005E4C34) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_781___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_781___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_781__RX_DCOC_RANGE_781___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_781__RX_DCOC_RES_I_781___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_781__RX_DCOC_RES_Q_781___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_781__RX_DCOC_RANGE_781___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_781__RX_DCOC_RANGE_781___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_781__RX_DCOC_RES_I_781___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_781__RX_DCOC_RES_I_781___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_781__RX_DCOC_RES_Q_781___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_781__RX_DCOC_RES_Q_781___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_781___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_781___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_782 (0x005E4C38) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_782___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_782___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_782__RX_DCOC_RANGE_782___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_782__RX_DCOC_RES_I_782___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_782__RX_DCOC_RES_Q_782___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_782__RX_DCOC_RANGE_782___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_782__RX_DCOC_RANGE_782___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_782__RX_DCOC_RES_I_782___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_782__RX_DCOC_RES_I_782___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_782__RX_DCOC_RES_Q_782___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_782__RX_DCOC_RES_Q_782___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_782___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_782___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_783 (0x005E4C3C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_783___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_783___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_783__RX_DCOC_RANGE_783___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_783__RX_DCOC_RES_I_783___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_783__RX_DCOC_RES_Q_783___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_783__RX_DCOC_RANGE_783___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_783__RX_DCOC_RANGE_783___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_783__RX_DCOC_RES_I_783___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_783__RX_DCOC_RES_I_783___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_783__RX_DCOC_RES_Q_783___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_783__RX_DCOC_RES_Q_783___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_783___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_783___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_784 (0x005E4C40) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_784___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_784___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_784__RX_DCOC_RANGE_784___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_784__RX_DCOC_RES_I_784___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_784__RX_DCOC_RES_Q_784___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_784__RX_DCOC_RANGE_784___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_784__RX_DCOC_RANGE_784___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_784__RX_DCOC_RES_I_784___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_784__RX_DCOC_RES_I_784___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_784__RX_DCOC_RES_Q_784___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_784__RX_DCOC_RES_Q_784___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_784___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_784___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_785 (0x005E4C44) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_785___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_785___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_785__RX_DCOC_RANGE_785___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_785__RX_DCOC_RES_I_785___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_785__RX_DCOC_RES_Q_785___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_785__RX_DCOC_RANGE_785___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_785__RX_DCOC_RANGE_785___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_785__RX_DCOC_RES_I_785___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_785__RX_DCOC_RES_I_785___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_785__RX_DCOC_RES_Q_785___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_785__RX_DCOC_RES_Q_785___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_785___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_785___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_786 (0x005E4C48) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_786___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_786___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_786__RX_DCOC_RANGE_786___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_786__RX_DCOC_RES_I_786___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_786__RX_DCOC_RES_Q_786___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_786__RX_DCOC_RANGE_786___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_786__RX_DCOC_RANGE_786___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_786__RX_DCOC_RES_I_786___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_786__RX_DCOC_RES_I_786___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_786__RX_DCOC_RES_Q_786___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_786__RX_DCOC_RES_Q_786___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_786___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_786___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_787 (0x005E4C4C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_787___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_787___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_787__RX_DCOC_RANGE_787___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_787__RX_DCOC_RES_I_787___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_787__RX_DCOC_RES_Q_787___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_787__RX_DCOC_RANGE_787___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_787__RX_DCOC_RANGE_787___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_787__RX_DCOC_RES_I_787___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_787__RX_DCOC_RES_I_787___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_787__RX_DCOC_RES_Q_787___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_787__RX_DCOC_RES_Q_787___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_787___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_787___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_788 (0x005E4C50) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_788___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_788___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_788__RX_DCOC_RANGE_788___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_788__RX_DCOC_RES_I_788___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_788__RX_DCOC_RES_Q_788___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_788__RX_DCOC_RANGE_788___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_788__RX_DCOC_RANGE_788___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_788__RX_DCOC_RES_I_788___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_788__RX_DCOC_RES_I_788___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_788__RX_DCOC_RES_Q_788___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_788__RX_DCOC_RES_Q_788___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_788___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_788___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_789 (0x005E4C54) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_789___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_789___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_789__RX_DCOC_RANGE_789___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_789__RX_DCOC_RES_I_789___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_789__RX_DCOC_RES_Q_789___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_789__RX_DCOC_RANGE_789___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_789__RX_DCOC_RANGE_789___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_789__RX_DCOC_RES_I_789___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_789__RX_DCOC_RES_I_789___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_789__RX_DCOC_RES_Q_789___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_789__RX_DCOC_RES_Q_789___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_789___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_789___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_790 (0x005E4C58) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_790___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_790___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_790__RX_DCOC_RANGE_790___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_790__RX_DCOC_RES_I_790___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_790__RX_DCOC_RES_Q_790___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_790__RX_DCOC_RANGE_790___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_790__RX_DCOC_RANGE_790___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_790__RX_DCOC_RES_I_790___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_790__RX_DCOC_RES_I_790___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_790__RX_DCOC_RES_Q_790___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_790__RX_DCOC_RES_Q_790___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_790___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_790___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_791 (0x005E4C5C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_791___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_791___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_791__RX_DCOC_RANGE_791___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_791__RX_DCOC_RES_I_791___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_791__RX_DCOC_RES_Q_791___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_791__RX_DCOC_RANGE_791___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_791__RX_DCOC_RANGE_791___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_791__RX_DCOC_RES_I_791___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_791__RX_DCOC_RES_I_791___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_791__RX_DCOC_RES_Q_791___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_791__RX_DCOC_RES_Q_791___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_791___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_791___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_792 (0x005E4C60) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_792___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_792___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_792__RX_DCOC_RANGE_792___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_792__RX_DCOC_RES_I_792___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_792__RX_DCOC_RES_Q_792___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_792__RX_DCOC_RANGE_792___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_792__RX_DCOC_RANGE_792___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_792__RX_DCOC_RES_I_792___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_792__RX_DCOC_RES_I_792___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_792__RX_DCOC_RES_Q_792___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_792__RX_DCOC_RES_Q_792___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_792___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_792___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_793 (0x005E4C64) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_793___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_793___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_793__RX_DCOC_RANGE_793___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_793__RX_DCOC_RES_I_793___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_793__RX_DCOC_RES_Q_793___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_793__RX_DCOC_RANGE_793___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_793__RX_DCOC_RANGE_793___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_793__RX_DCOC_RES_I_793___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_793__RX_DCOC_RES_I_793___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_793__RX_DCOC_RES_Q_793___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_793__RX_DCOC_RES_Q_793___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_793___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_793___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_794 (0x005E4C68) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_794___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_794___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_794__RX_DCOC_RANGE_794___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_794__RX_DCOC_RES_I_794___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_794__RX_DCOC_RES_Q_794___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_794__RX_DCOC_RANGE_794___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_794__RX_DCOC_RANGE_794___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_794__RX_DCOC_RES_I_794___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_794__RX_DCOC_RES_I_794___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_794__RX_DCOC_RES_Q_794___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_794__RX_DCOC_RES_Q_794___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_794___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_794___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_795 (0x005E4C6C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_795___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_795___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_795__RX_DCOC_RANGE_795___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_795__RX_DCOC_RES_I_795___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_795__RX_DCOC_RES_Q_795___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_795__RX_DCOC_RANGE_795___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_795__RX_DCOC_RANGE_795___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_795__RX_DCOC_RES_I_795___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_795__RX_DCOC_RES_I_795___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_795__RX_DCOC_RES_Q_795___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_795__RX_DCOC_RES_Q_795___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_795___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_795___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_796 (0x005E4C70) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_796___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_796___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_796__RX_DCOC_RANGE_796___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_796__RX_DCOC_RES_I_796___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_796__RX_DCOC_RES_Q_796___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_796__RX_DCOC_RANGE_796___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_796__RX_DCOC_RANGE_796___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_796__RX_DCOC_RES_I_796___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_796__RX_DCOC_RES_I_796___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_796__RX_DCOC_RES_Q_796___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_796__RX_DCOC_RES_Q_796___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_796___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_796___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_797 (0x005E4C74) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_797___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_797___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_797__RX_DCOC_RANGE_797___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_797__RX_DCOC_RES_I_797___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_797__RX_DCOC_RES_Q_797___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_797__RX_DCOC_RANGE_797___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_797__RX_DCOC_RANGE_797___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_797__RX_DCOC_RES_I_797___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_797__RX_DCOC_RES_I_797___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_797__RX_DCOC_RES_Q_797___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_797__RX_DCOC_RES_Q_797___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_797___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_797___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_798 (0x005E4C78) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_798___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_798___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_798__RX_DCOC_RANGE_798___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_798__RX_DCOC_RES_I_798___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_798__RX_DCOC_RES_Q_798___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_798__RX_DCOC_RANGE_798___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_798__RX_DCOC_RANGE_798___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_798__RX_DCOC_RES_I_798___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_798__RX_DCOC_RES_I_798___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_798__RX_DCOC_RES_Q_798___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_798__RX_DCOC_RES_Q_798___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_798___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_798___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_799 (0x005E4C7C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_799___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_799___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_799__RX_DCOC_RANGE_799___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_799__RX_DCOC_RES_I_799___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_799__RX_DCOC_RES_Q_799___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_799__RX_DCOC_RANGE_799___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_799__RX_DCOC_RANGE_799___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_799__RX_DCOC_RES_I_799___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_799__RX_DCOC_RES_I_799___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_799__RX_DCOC_RES_Q_799___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_799__RX_DCOC_RES_Q_799___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_799___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_799___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_800 (0x005E4C80) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_800___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_800___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_800__RX_DCOC_RANGE_800___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_800__RX_DCOC_RES_I_800___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_800__RX_DCOC_RES_Q_800___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_800__RX_DCOC_RANGE_800___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_800__RX_DCOC_RANGE_800___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_800__RX_DCOC_RES_I_800___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_800__RX_DCOC_RES_I_800___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_800__RX_DCOC_RES_Q_800___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_800__RX_DCOC_RES_Q_800___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_800___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_800___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_801 (0x005E4C84) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_801___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_801___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_801__RX_DCOC_RANGE_801___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_801__RX_DCOC_RES_I_801___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_801__RX_DCOC_RES_Q_801___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_801__RX_DCOC_RANGE_801___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_801__RX_DCOC_RANGE_801___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_801__RX_DCOC_RES_I_801___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_801__RX_DCOC_RES_I_801___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_801__RX_DCOC_RES_Q_801___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_801__RX_DCOC_RES_Q_801___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_801___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_801___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_802 (0x005E4C88) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_802___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_802___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_802__RX_DCOC_RANGE_802___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_802__RX_DCOC_RES_I_802___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_802__RX_DCOC_RES_Q_802___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_802__RX_DCOC_RANGE_802___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_802__RX_DCOC_RANGE_802___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_802__RX_DCOC_RES_I_802___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_802__RX_DCOC_RES_I_802___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_802__RX_DCOC_RES_Q_802___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_802__RX_DCOC_RES_Q_802___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_802___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_802___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_803 (0x005E4C8C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_803___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_803___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_803__RX_DCOC_RANGE_803___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_803__RX_DCOC_RES_I_803___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_803__RX_DCOC_RES_Q_803___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_803__RX_DCOC_RANGE_803___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_803__RX_DCOC_RANGE_803___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_803__RX_DCOC_RES_I_803___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_803__RX_DCOC_RES_I_803___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_803__RX_DCOC_RES_Q_803___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_803__RX_DCOC_RES_Q_803___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_803___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_803___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_804 (0x005E4C90) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_804___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_804___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_804__RX_DCOC_RANGE_804___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_804__RX_DCOC_RES_I_804___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_804__RX_DCOC_RES_Q_804___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_804__RX_DCOC_RANGE_804___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_804__RX_DCOC_RANGE_804___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_804__RX_DCOC_RES_I_804___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_804__RX_DCOC_RES_I_804___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_804__RX_DCOC_RES_Q_804___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_804__RX_DCOC_RES_Q_804___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_804___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_804___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_805 (0x005E4C94) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_805___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_805___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_805__RX_DCOC_RANGE_805___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_805__RX_DCOC_RES_I_805___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_805__RX_DCOC_RES_Q_805___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_805__RX_DCOC_RANGE_805___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_805__RX_DCOC_RANGE_805___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_805__RX_DCOC_RES_I_805___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_805__RX_DCOC_RES_I_805___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_805__RX_DCOC_RES_Q_805___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_805__RX_DCOC_RES_Q_805___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_805___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_805___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_806 (0x005E4C98) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_806___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_806___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_806__RX_DCOC_RANGE_806___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_806__RX_DCOC_RES_I_806___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_806__RX_DCOC_RES_Q_806___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_806__RX_DCOC_RANGE_806___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_806__RX_DCOC_RANGE_806___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_806__RX_DCOC_RES_I_806___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_806__RX_DCOC_RES_I_806___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_806__RX_DCOC_RES_Q_806___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_806__RX_DCOC_RES_Q_806___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_806___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_806___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_807 (0x005E4C9C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_807___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_807___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_807__RX_DCOC_RANGE_807___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_807__RX_DCOC_RES_I_807___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_807__RX_DCOC_RES_Q_807___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_807__RX_DCOC_RANGE_807___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_807__RX_DCOC_RANGE_807___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_807__RX_DCOC_RES_I_807___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_807__RX_DCOC_RES_I_807___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_807__RX_DCOC_RES_Q_807___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_807__RX_DCOC_RES_Q_807___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_807___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_807___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_808 (0x005E4CA0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_808___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_808___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_808__RX_DCOC_RANGE_808___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_808__RX_DCOC_RES_I_808___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_808__RX_DCOC_RES_Q_808___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_808__RX_DCOC_RANGE_808___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_808__RX_DCOC_RANGE_808___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_808__RX_DCOC_RES_I_808___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_808__RX_DCOC_RES_I_808___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_808__RX_DCOC_RES_Q_808___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_808__RX_DCOC_RES_Q_808___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_808___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_808___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_809 (0x005E4CA4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_809___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_809___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_809__RX_DCOC_RANGE_809___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_809__RX_DCOC_RES_I_809___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_809__RX_DCOC_RES_Q_809___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_809__RX_DCOC_RANGE_809___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_809__RX_DCOC_RANGE_809___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_809__RX_DCOC_RES_I_809___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_809__RX_DCOC_RES_I_809___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_809__RX_DCOC_RES_Q_809___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_809__RX_DCOC_RES_Q_809___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_809___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_809___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_810 (0x005E4CA8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_810___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_810___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_810__RX_DCOC_RANGE_810___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_810__RX_DCOC_RES_I_810___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_810__RX_DCOC_RES_Q_810___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_810__RX_DCOC_RANGE_810___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_810__RX_DCOC_RANGE_810___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_810__RX_DCOC_RES_I_810___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_810__RX_DCOC_RES_I_810___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_810__RX_DCOC_RES_Q_810___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_810__RX_DCOC_RES_Q_810___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_810___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_810___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_811 (0x005E4CAC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_811___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_811___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_811__RX_DCOC_RANGE_811___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_811__RX_DCOC_RES_I_811___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_811__RX_DCOC_RES_Q_811___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_811__RX_DCOC_RANGE_811___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_811__RX_DCOC_RANGE_811___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_811__RX_DCOC_RES_I_811___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_811__RX_DCOC_RES_I_811___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_811__RX_DCOC_RES_Q_811___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_811__RX_DCOC_RES_Q_811___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_811___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_811___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_812 (0x005E4CB0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_812___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_812___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_812__RX_DCOC_RANGE_812___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_812__RX_DCOC_RES_I_812___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_812__RX_DCOC_RES_Q_812___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_812__RX_DCOC_RANGE_812___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_812__RX_DCOC_RANGE_812___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_812__RX_DCOC_RES_I_812___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_812__RX_DCOC_RES_I_812___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_812__RX_DCOC_RES_Q_812___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_812__RX_DCOC_RES_Q_812___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_812___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_812___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_813 (0x005E4CB4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_813___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_813___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_813__RX_DCOC_RANGE_813___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_813__RX_DCOC_RES_I_813___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_813__RX_DCOC_RES_Q_813___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_813__RX_DCOC_RANGE_813___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_813__RX_DCOC_RANGE_813___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_813__RX_DCOC_RES_I_813___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_813__RX_DCOC_RES_I_813___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_813__RX_DCOC_RES_Q_813___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_813__RX_DCOC_RES_Q_813___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_813___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_813___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_814 (0x005E4CB8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_814___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_814___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_814__RX_DCOC_RANGE_814___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_814__RX_DCOC_RES_I_814___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_814__RX_DCOC_RES_Q_814___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_814__RX_DCOC_RANGE_814___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_814__RX_DCOC_RANGE_814___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_814__RX_DCOC_RES_I_814___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_814__RX_DCOC_RES_I_814___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_814__RX_DCOC_RES_Q_814___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_814__RX_DCOC_RES_Q_814___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_814___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_814___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_815 (0x005E4CBC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_815___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_815___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_815__RX_DCOC_RANGE_815___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_815__RX_DCOC_RES_I_815___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_815__RX_DCOC_RES_Q_815___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_815__RX_DCOC_RANGE_815___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_815__RX_DCOC_RANGE_815___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_815__RX_DCOC_RES_I_815___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_815__RX_DCOC_RES_I_815___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_815__RX_DCOC_RES_Q_815___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_815__RX_DCOC_RES_Q_815___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_815___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_815___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_816 (0x005E4CC0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_816___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_816___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_816__RX_DCOC_RANGE_816___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_816__RX_DCOC_RES_I_816___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_816__RX_DCOC_RES_Q_816___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_816__RX_DCOC_RANGE_816___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_816__RX_DCOC_RANGE_816___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_816__RX_DCOC_RES_I_816___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_816__RX_DCOC_RES_I_816___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_816__RX_DCOC_RES_Q_816___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_816__RX_DCOC_RES_Q_816___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_816___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_816___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_817 (0x005E4CC4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_817___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_817___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_817__RX_DCOC_RANGE_817___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_817__RX_DCOC_RES_I_817___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_817__RX_DCOC_RES_Q_817___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_817__RX_DCOC_RANGE_817___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_817__RX_DCOC_RANGE_817___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_817__RX_DCOC_RES_I_817___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_817__RX_DCOC_RES_I_817___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_817__RX_DCOC_RES_Q_817___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_817__RX_DCOC_RES_Q_817___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_817___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_817___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_818 (0x005E4CC8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_818___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_818___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_818__RX_DCOC_RANGE_818___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_818__RX_DCOC_RES_I_818___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_818__RX_DCOC_RES_Q_818___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_818__RX_DCOC_RANGE_818___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_818__RX_DCOC_RANGE_818___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_818__RX_DCOC_RES_I_818___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_818__RX_DCOC_RES_I_818___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_818__RX_DCOC_RES_Q_818___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_818__RX_DCOC_RES_Q_818___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_818___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_818___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_819 (0x005E4CCC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_819___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_819___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_819__RX_DCOC_RANGE_819___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_819__RX_DCOC_RES_I_819___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_819__RX_DCOC_RES_Q_819___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_819__RX_DCOC_RANGE_819___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_819__RX_DCOC_RANGE_819___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_819__RX_DCOC_RES_I_819___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_819__RX_DCOC_RES_I_819___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_819__RX_DCOC_RES_Q_819___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_819__RX_DCOC_RES_Q_819___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_819___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_819___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_820 (0x005E4CD0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_820___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_820___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_820__RX_DCOC_RANGE_820___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_820__RX_DCOC_RES_I_820___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_820__RX_DCOC_RES_Q_820___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_820__RX_DCOC_RANGE_820___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_820__RX_DCOC_RANGE_820___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_820__RX_DCOC_RES_I_820___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_820__RX_DCOC_RES_I_820___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_820__RX_DCOC_RES_Q_820___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_820__RX_DCOC_RES_Q_820___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_820___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_820___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_821 (0x005E4CD4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_821___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_821___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_821__RX_DCOC_RANGE_821___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_821__RX_DCOC_RES_I_821___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_821__RX_DCOC_RES_Q_821___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_821__RX_DCOC_RANGE_821___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_821__RX_DCOC_RANGE_821___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_821__RX_DCOC_RES_I_821___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_821__RX_DCOC_RES_I_821___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_821__RX_DCOC_RES_Q_821___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_821__RX_DCOC_RES_Q_821___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_821___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_821___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_822 (0x005E4CD8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_822___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_822___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_822__RX_DCOC_RANGE_822___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_822__RX_DCOC_RES_I_822___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_822__RX_DCOC_RES_Q_822___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_822__RX_DCOC_RANGE_822___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_822__RX_DCOC_RANGE_822___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_822__RX_DCOC_RES_I_822___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_822__RX_DCOC_RES_I_822___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_822__RX_DCOC_RES_Q_822___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_822__RX_DCOC_RES_Q_822___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_822___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_822___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_823 (0x005E4CDC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_823___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_823___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_823__RX_DCOC_RANGE_823___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_823__RX_DCOC_RES_I_823___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_823__RX_DCOC_RES_Q_823___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_823__RX_DCOC_RANGE_823___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_823__RX_DCOC_RANGE_823___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_823__RX_DCOC_RES_I_823___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_823__RX_DCOC_RES_I_823___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_823__RX_DCOC_RES_Q_823___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_823__RX_DCOC_RES_Q_823___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_823___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_823___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_824 (0x005E4CE0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_824___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_824___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_824__RX_DCOC_RANGE_824___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_824__RX_DCOC_RES_I_824___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_824__RX_DCOC_RES_Q_824___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_824__RX_DCOC_RANGE_824___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_824__RX_DCOC_RANGE_824___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_824__RX_DCOC_RES_I_824___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_824__RX_DCOC_RES_I_824___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_824__RX_DCOC_RES_Q_824___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_824__RX_DCOC_RES_Q_824___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_824___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_824___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_825 (0x005E4CE4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_825___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_825___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_825__RX_DCOC_RANGE_825___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_825__RX_DCOC_RES_I_825___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_825__RX_DCOC_RES_Q_825___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_825__RX_DCOC_RANGE_825___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_825__RX_DCOC_RANGE_825___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_825__RX_DCOC_RES_I_825___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_825__RX_DCOC_RES_I_825___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_825__RX_DCOC_RES_Q_825___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_825__RX_DCOC_RES_Q_825___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_825___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_825___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_826 (0x005E4CE8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_826___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_826___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_826__RX_DCOC_RANGE_826___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_826__RX_DCOC_RES_I_826___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_826__RX_DCOC_RES_Q_826___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_826__RX_DCOC_RANGE_826___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_826__RX_DCOC_RANGE_826___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_826__RX_DCOC_RES_I_826___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_826__RX_DCOC_RES_I_826___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_826__RX_DCOC_RES_Q_826___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_826__RX_DCOC_RES_Q_826___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_826___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_826___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_827 (0x005E4CEC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_827___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_827___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_827__RX_DCOC_RANGE_827___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_827__RX_DCOC_RES_I_827___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_827__RX_DCOC_RES_Q_827___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_827__RX_DCOC_RANGE_827___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_827__RX_DCOC_RANGE_827___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_827__RX_DCOC_RES_I_827___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_827__RX_DCOC_RES_I_827___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_827__RX_DCOC_RES_Q_827___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_827__RX_DCOC_RES_Q_827___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_827___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_827___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_828 (0x005E4CF0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_828___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_828___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_828__RX_DCOC_RANGE_828___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_828__RX_DCOC_RES_I_828___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_828__RX_DCOC_RES_Q_828___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_828__RX_DCOC_RANGE_828___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_828__RX_DCOC_RANGE_828___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_828__RX_DCOC_RES_I_828___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_828__RX_DCOC_RES_I_828___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_828__RX_DCOC_RES_Q_828___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_828__RX_DCOC_RES_Q_828___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_828___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_828___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_829 (0x005E4CF4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_829___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_829___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_829__RX_DCOC_RANGE_829___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_829__RX_DCOC_RES_I_829___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_829__RX_DCOC_RES_Q_829___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_829__RX_DCOC_RANGE_829___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_829__RX_DCOC_RANGE_829___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_829__RX_DCOC_RES_I_829___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_829__RX_DCOC_RES_I_829___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_829__RX_DCOC_RES_Q_829___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_829__RX_DCOC_RES_Q_829___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_829___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_829___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_830 (0x005E4CF8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_830___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_830___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_830__RX_DCOC_RANGE_830___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_830__RX_DCOC_RES_I_830___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_830__RX_DCOC_RES_Q_830___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_830__RX_DCOC_RANGE_830___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_830__RX_DCOC_RANGE_830___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_830__RX_DCOC_RES_I_830___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_830__RX_DCOC_RES_I_830___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_830__RX_DCOC_RES_Q_830___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_830__RX_DCOC_RES_Q_830___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_830___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_830___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_831 (0x005E4CFC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_831___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_831___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_831__RX_DCOC_RANGE_831___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_831__RX_DCOC_RES_I_831___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_831__RX_DCOC_RES_Q_831___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_831__RX_DCOC_RANGE_831___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_831__RX_DCOC_RANGE_831___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_831__RX_DCOC_RES_I_831___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_831__RX_DCOC_RES_I_831___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_831__RX_DCOC_RES_Q_831___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_831__RX_DCOC_RES_Q_831___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_831___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_831___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_832 (0x005E4D00) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_832___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_832___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_832__RX_DCOC_RANGE_832___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_832__RX_DCOC_RES_I_832___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_832__RX_DCOC_RES_Q_832___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_832__RX_DCOC_RANGE_832___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_832__RX_DCOC_RANGE_832___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_832__RX_DCOC_RES_I_832___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_832__RX_DCOC_RES_I_832___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_832__RX_DCOC_RES_Q_832___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_832__RX_DCOC_RES_Q_832___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_832___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_832___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_833 (0x005E4D04) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_833___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_833___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_833__RX_DCOC_RANGE_833___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_833__RX_DCOC_RES_I_833___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_833__RX_DCOC_RES_Q_833___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_833__RX_DCOC_RANGE_833___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_833__RX_DCOC_RANGE_833___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_833__RX_DCOC_RES_I_833___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_833__RX_DCOC_RES_I_833___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_833__RX_DCOC_RES_Q_833___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_833__RX_DCOC_RES_Q_833___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_833___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_833___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_834 (0x005E4D08) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_834___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_834___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_834__RX_DCOC_RANGE_834___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_834__RX_DCOC_RES_I_834___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_834__RX_DCOC_RES_Q_834___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_834__RX_DCOC_RANGE_834___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_834__RX_DCOC_RANGE_834___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_834__RX_DCOC_RES_I_834___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_834__RX_DCOC_RES_I_834___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_834__RX_DCOC_RES_Q_834___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_834__RX_DCOC_RES_Q_834___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_834___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_834___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_835 (0x005E4D0C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_835___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_835___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_835__RX_DCOC_RANGE_835___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_835__RX_DCOC_RES_I_835___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_835__RX_DCOC_RES_Q_835___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_835__RX_DCOC_RANGE_835___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_835__RX_DCOC_RANGE_835___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_835__RX_DCOC_RES_I_835___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_835__RX_DCOC_RES_I_835___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_835__RX_DCOC_RES_Q_835___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_835__RX_DCOC_RES_Q_835___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_835___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_835___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_836 (0x005E4D10) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_836___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_836___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_836__RX_DCOC_RANGE_836___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_836__RX_DCOC_RES_I_836___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_836__RX_DCOC_RES_Q_836___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_836__RX_DCOC_RANGE_836___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_836__RX_DCOC_RANGE_836___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_836__RX_DCOC_RES_I_836___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_836__RX_DCOC_RES_I_836___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_836__RX_DCOC_RES_Q_836___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_836__RX_DCOC_RES_Q_836___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_836___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_836___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_837 (0x005E4D14) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_837___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_837___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_837__RX_DCOC_RANGE_837___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_837__RX_DCOC_RES_I_837___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_837__RX_DCOC_RES_Q_837___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_837__RX_DCOC_RANGE_837___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_837__RX_DCOC_RANGE_837___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_837__RX_DCOC_RES_I_837___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_837__RX_DCOC_RES_I_837___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_837__RX_DCOC_RES_Q_837___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_837__RX_DCOC_RES_Q_837___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_837___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_837___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_838 (0x005E4D18) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_838___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_838___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_838__RX_DCOC_RANGE_838___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_838__RX_DCOC_RES_I_838___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_838__RX_DCOC_RES_Q_838___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_838__RX_DCOC_RANGE_838___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_838__RX_DCOC_RANGE_838___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_838__RX_DCOC_RES_I_838___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_838__RX_DCOC_RES_I_838___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_838__RX_DCOC_RES_Q_838___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_838__RX_DCOC_RES_Q_838___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_838___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_838___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_839 (0x005E4D1C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_839___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_839___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_839__RX_DCOC_RANGE_839___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_839__RX_DCOC_RES_I_839___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_839__RX_DCOC_RES_Q_839___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_839__RX_DCOC_RANGE_839___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_839__RX_DCOC_RANGE_839___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_839__RX_DCOC_RES_I_839___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_839__RX_DCOC_RES_I_839___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_839__RX_DCOC_RES_Q_839___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_839__RX_DCOC_RES_Q_839___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_839___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_839___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_840 (0x005E4D20) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_840___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_840___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_840__RX_DCOC_RANGE_840___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_840__RX_DCOC_RES_I_840___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_840__RX_DCOC_RES_Q_840___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_840__RX_DCOC_RANGE_840___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_840__RX_DCOC_RANGE_840___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_840__RX_DCOC_RES_I_840___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_840__RX_DCOC_RES_I_840___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_840__RX_DCOC_RES_Q_840___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_840__RX_DCOC_RES_Q_840___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_840___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_840___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_841 (0x005E4D24) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_841___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_841___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_841__RX_DCOC_RANGE_841___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_841__RX_DCOC_RES_I_841___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_841__RX_DCOC_RES_Q_841___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_841__RX_DCOC_RANGE_841___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_841__RX_DCOC_RANGE_841___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_841__RX_DCOC_RES_I_841___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_841__RX_DCOC_RES_I_841___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_841__RX_DCOC_RES_Q_841___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_841__RX_DCOC_RES_Q_841___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_841___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_841___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_842 (0x005E4D28) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_842___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_842___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_842__RX_DCOC_RANGE_842___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_842__RX_DCOC_RES_I_842___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_842__RX_DCOC_RES_Q_842___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_842__RX_DCOC_RANGE_842___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_842__RX_DCOC_RANGE_842___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_842__RX_DCOC_RES_I_842___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_842__RX_DCOC_RES_I_842___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_842__RX_DCOC_RES_Q_842___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_842__RX_DCOC_RES_Q_842___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_842___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_842___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_843 (0x005E4D2C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_843___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_843___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_843__RX_DCOC_RANGE_843___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_843__RX_DCOC_RES_I_843___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_843__RX_DCOC_RES_Q_843___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_843__RX_DCOC_RANGE_843___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_843__RX_DCOC_RANGE_843___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_843__RX_DCOC_RES_I_843___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_843__RX_DCOC_RES_I_843___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_843__RX_DCOC_RES_Q_843___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_843__RX_DCOC_RES_Q_843___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_843___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_843___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_844 (0x005E4D30) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_844___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_844___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_844__RX_DCOC_RANGE_844___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_844__RX_DCOC_RES_I_844___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_844__RX_DCOC_RES_Q_844___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_844__RX_DCOC_RANGE_844___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_844__RX_DCOC_RANGE_844___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_844__RX_DCOC_RES_I_844___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_844__RX_DCOC_RES_I_844___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_844__RX_DCOC_RES_Q_844___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_844__RX_DCOC_RES_Q_844___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_844___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_844___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_845 (0x005E4D34) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_845___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_845___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_845__RX_DCOC_RANGE_845___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_845__RX_DCOC_RES_I_845___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_845__RX_DCOC_RES_Q_845___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_845__RX_DCOC_RANGE_845___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_845__RX_DCOC_RANGE_845___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_845__RX_DCOC_RES_I_845___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_845__RX_DCOC_RES_I_845___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_845__RX_DCOC_RES_Q_845___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_845__RX_DCOC_RES_Q_845___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_845___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_845___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_846 (0x005E4D38) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_846___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_846___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_846__RX_DCOC_RANGE_846___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_846__RX_DCOC_RES_I_846___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_846__RX_DCOC_RES_Q_846___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_846__RX_DCOC_RANGE_846___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_846__RX_DCOC_RANGE_846___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_846__RX_DCOC_RES_I_846___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_846__RX_DCOC_RES_I_846___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_846__RX_DCOC_RES_Q_846___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_846__RX_DCOC_RES_Q_846___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_846___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_846___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_847 (0x005E4D3C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_847___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_847___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_847__RX_DCOC_RANGE_847___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_847__RX_DCOC_RES_I_847___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_847__RX_DCOC_RES_Q_847___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_847__RX_DCOC_RANGE_847___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_847__RX_DCOC_RANGE_847___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_847__RX_DCOC_RES_I_847___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_847__RX_DCOC_RES_I_847___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_847__RX_DCOC_RES_Q_847___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_847__RX_DCOC_RES_Q_847___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_847___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_847___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_848 (0x005E4D40) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_848___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_848___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_848__RX_DCOC_RANGE_848___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_848__RX_DCOC_RES_I_848___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_848__RX_DCOC_RES_Q_848___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_848__RX_DCOC_RANGE_848___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_848__RX_DCOC_RANGE_848___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_848__RX_DCOC_RES_I_848___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_848__RX_DCOC_RES_I_848___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_848__RX_DCOC_RES_Q_848___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_848__RX_DCOC_RES_Q_848___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_848___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_848___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_849 (0x005E4D44) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_849___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_849___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_849__RX_DCOC_RANGE_849___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_849__RX_DCOC_RES_I_849___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_849__RX_DCOC_RES_Q_849___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_849__RX_DCOC_RANGE_849___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_849__RX_DCOC_RANGE_849___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_849__RX_DCOC_RES_I_849___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_849__RX_DCOC_RES_I_849___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_849__RX_DCOC_RES_Q_849___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_849__RX_DCOC_RES_Q_849___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_849___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_849___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_850 (0x005E4D48) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_850___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_850___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_850__RX_DCOC_RANGE_850___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_850__RX_DCOC_RES_I_850___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_850__RX_DCOC_RES_Q_850___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_850__RX_DCOC_RANGE_850___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_850__RX_DCOC_RANGE_850___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_850__RX_DCOC_RES_I_850___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_850__RX_DCOC_RES_I_850___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_850__RX_DCOC_RES_Q_850___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_850__RX_DCOC_RES_Q_850___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_850___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_850___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_851 (0x005E4D4C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_851___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_851___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_851__RX_DCOC_RANGE_851___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_851__RX_DCOC_RES_I_851___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_851__RX_DCOC_RES_Q_851___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_851__RX_DCOC_RANGE_851___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_851__RX_DCOC_RANGE_851___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_851__RX_DCOC_RES_I_851___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_851__RX_DCOC_RES_I_851___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_851__RX_DCOC_RES_Q_851___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_851__RX_DCOC_RES_Q_851___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_851___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_851___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_852 (0x005E4D50) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_852___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_852___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_852__RX_DCOC_RANGE_852___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_852__RX_DCOC_RES_I_852___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_852__RX_DCOC_RES_Q_852___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_852__RX_DCOC_RANGE_852___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_852__RX_DCOC_RANGE_852___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_852__RX_DCOC_RES_I_852___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_852__RX_DCOC_RES_I_852___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_852__RX_DCOC_RES_Q_852___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_852__RX_DCOC_RES_Q_852___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_852___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_852___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_853 (0x005E4D54) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_853___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_853___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_853__RX_DCOC_RANGE_853___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_853__RX_DCOC_RES_I_853___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_853__RX_DCOC_RES_Q_853___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_853__RX_DCOC_RANGE_853___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_853__RX_DCOC_RANGE_853___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_853__RX_DCOC_RES_I_853___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_853__RX_DCOC_RES_I_853___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_853__RX_DCOC_RES_Q_853___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_853__RX_DCOC_RES_Q_853___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_853___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_853___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_854 (0x005E4D58) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_854___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_854___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_854__RX_DCOC_RANGE_854___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_854__RX_DCOC_RES_I_854___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_854__RX_DCOC_RES_Q_854___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_854__RX_DCOC_RANGE_854___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_854__RX_DCOC_RANGE_854___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_854__RX_DCOC_RES_I_854___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_854__RX_DCOC_RES_I_854___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_854__RX_DCOC_RES_Q_854___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_854__RX_DCOC_RES_Q_854___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_854___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_854___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_855 (0x005E4D5C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_855___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_855___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_855__RX_DCOC_RANGE_855___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_855__RX_DCOC_RES_I_855___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_855__RX_DCOC_RES_Q_855___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_855__RX_DCOC_RANGE_855___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_855__RX_DCOC_RANGE_855___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_855__RX_DCOC_RES_I_855___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_855__RX_DCOC_RES_I_855___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_855__RX_DCOC_RES_Q_855___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_855__RX_DCOC_RES_Q_855___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_855___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_855___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_856 (0x005E4D60) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_856___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_856___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_856__RX_DCOC_RANGE_856___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_856__RX_DCOC_RES_I_856___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_856__RX_DCOC_RES_Q_856___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_856__RX_DCOC_RANGE_856___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_856__RX_DCOC_RANGE_856___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_856__RX_DCOC_RES_I_856___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_856__RX_DCOC_RES_I_856___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_856__RX_DCOC_RES_Q_856___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_856__RX_DCOC_RES_Q_856___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_856___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_856___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_857 (0x005E4D64) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_857___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_857___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_857__RX_DCOC_RANGE_857___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_857__RX_DCOC_RES_I_857___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_857__RX_DCOC_RES_Q_857___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_857__RX_DCOC_RANGE_857___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_857__RX_DCOC_RANGE_857___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_857__RX_DCOC_RES_I_857___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_857__RX_DCOC_RES_I_857___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_857__RX_DCOC_RES_Q_857___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_857__RX_DCOC_RES_Q_857___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_857___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_857___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_858 (0x005E4D68) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_858___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_858___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_858__RX_DCOC_RANGE_858___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_858__RX_DCOC_RES_I_858___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_858__RX_DCOC_RES_Q_858___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_858__RX_DCOC_RANGE_858___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_858__RX_DCOC_RANGE_858___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_858__RX_DCOC_RES_I_858___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_858__RX_DCOC_RES_I_858___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_858__RX_DCOC_RES_Q_858___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_858__RX_DCOC_RES_Q_858___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_858___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_858___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_859 (0x005E4D6C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_859___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_859___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_859__RX_DCOC_RANGE_859___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_859__RX_DCOC_RES_I_859___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_859__RX_DCOC_RES_Q_859___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_859__RX_DCOC_RANGE_859___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_859__RX_DCOC_RANGE_859___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_859__RX_DCOC_RES_I_859___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_859__RX_DCOC_RES_I_859___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_859__RX_DCOC_RES_Q_859___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_859__RX_DCOC_RES_Q_859___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_859___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_859___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_860 (0x005E4D70) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_860___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_860___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_860__RX_DCOC_RANGE_860___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_860__RX_DCOC_RES_I_860___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_860__RX_DCOC_RES_Q_860___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_860__RX_DCOC_RANGE_860___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_860__RX_DCOC_RANGE_860___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_860__RX_DCOC_RES_I_860___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_860__RX_DCOC_RES_I_860___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_860__RX_DCOC_RES_Q_860___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_860__RX_DCOC_RES_Q_860___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_860___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_860___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_861 (0x005E4D74) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_861___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_861___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_861__RX_DCOC_RANGE_861___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_861__RX_DCOC_RES_I_861___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_861__RX_DCOC_RES_Q_861___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_861__RX_DCOC_RANGE_861___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_861__RX_DCOC_RANGE_861___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_861__RX_DCOC_RES_I_861___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_861__RX_DCOC_RES_I_861___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_861__RX_DCOC_RES_Q_861___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_861__RX_DCOC_RES_Q_861___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_861___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_861___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_862 (0x005E4D78) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_862___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_862___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_862__RX_DCOC_RANGE_862___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_862__RX_DCOC_RES_I_862___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_862__RX_DCOC_RES_Q_862___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_862__RX_DCOC_RANGE_862___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_862__RX_DCOC_RANGE_862___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_862__RX_DCOC_RES_I_862___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_862__RX_DCOC_RES_I_862___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_862__RX_DCOC_RES_Q_862___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_862__RX_DCOC_RES_Q_862___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_862___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_862___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_863 (0x005E4D7C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_863___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_863___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_863__RX_DCOC_RANGE_863___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_863__RX_DCOC_RES_I_863___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_863__RX_DCOC_RES_Q_863___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_863__RX_DCOC_RANGE_863___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_863__RX_DCOC_RANGE_863___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_863__RX_DCOC_RES_I_863___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_863__RX_DCOC_RES_I_863___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_863__RX_DCOC_RES_Q_863___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_863__RX_DCOC_RES_Q_863___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_863___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_863___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_864 (0x005E4D80) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_864___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_864___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_864__RX_DCOC_RANGE_864___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_864__RX_DCOC_RES_I_864___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_864__RX_DCOC_RES_Q_864___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_864__RX_DCOC_RANGE_864___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_864__RX_DCOC_RANGE_864___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_864__RX_DCOC_RES_I_864___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_864__RX_DCOC_RES_I_864___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_864__RX_DCOC_RES_Q_864___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_864__RX_DCOC_RES_Q_864___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_864___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_864___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_865 (0x005E4D84) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_865___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_865___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_865__RX_DCOC_RANGE_865___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_865__RX_DCOC_RES_I_865___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_865__RX_DCOC_RES_Q_865___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_865__RX_DCOC_RANGE_865___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_865__RX_DCOC_RANGE_865___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_865__RX_DCOC_RES_I_865___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_865__RX_DCOC_RES_I_865___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_865__RX_DCOC_RES_Q_865___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_865__RX_DCOC_RES_Q_865___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_865___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_865___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_866 (0x005E4D88) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_866___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_866___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_866__RX_DCOC_RANGE_866___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_866__RX_DCOC_RES_I_866___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_866__RX_DCOC_RES_Q_866___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_866__RX_DCOC_RANGE_866___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_866__RX_DCOC_RANGE_866___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_866__RX_DCOC_RES_I_866___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_866__RX_DCOC_RES_I_866___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_866__RX_DCOC_RES_Q_866___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_866__RX_DCOC_RES_Q_866___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_866___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_866___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_867 (0x005E4D8C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_867___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_867___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_867__RX_DCOC_RANGE_867___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_867__RX_DCOC_RES_I_867___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_867__RX_DCOC_RES_Q_867___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_867__RX_DCOC_RANGE_867___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_867__RX_DCOC_RANGE_867___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_867__RX_DCOC_RES_I_867___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_867__RX_DCOC_RES_I_867___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_867__RX_DCOC_RES_Q_867___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_867__RX_DCOC_RES_Q_867___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_867___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_867___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_868 (0x005E4D90) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_868___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_868___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_868__RX_DCOC_RANGE_868___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_868__RX_DCOC_RES_I_868___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_868__RX_DCOC_RES_Q_868___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_868__RX_DCOC_RANGE_868___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_868__RX_DCOC_RANGE_868___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_868__RX_DCOC_RES_I_868___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_868__RX_DCOC_RES_I_868___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_868__RX_DCOC_RES_Q_868___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_868__RX_DCOC_RES_Q_868___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_868___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_868___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_869 (0x005E4D94) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_869___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_869___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_869__RX_DCOC_RANGE_869___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_869__RX_DCOC_RES_I_869___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_869__RX_DCOC_RES_Q_869___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_869__RX_DCOC_RANGE_869___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_869__RX_DCOC_RANGE_869___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_869__RX_DCOC_RES_I_869___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_869__RX_DCOC_RES_I_869___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_869__RX_DCOC_RES_Q_869___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_869__RX_DCOC_RES_Q_869___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_869___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_869___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_870 (0x005E4D98) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_870___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_870___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_870__RX_DCOC_RANGE_870___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_870__RX_DCOC_RES_I_870___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_870__RX_DCOC_RES_Q_870___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_870__RX_DCOC_RANGE_870___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_870__RX_DCOC_RANGE_870___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_870__RX_DCOC_RES_I_870___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_870__RX_DCOC_RES_I_870___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_870__RX_DCOC_RES_Q_870___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_870__RX_DCOC_RES_Q_870___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_870___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_870___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_871 (0x005E4D9C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_871___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_871___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_871__RX_DCOC_RANGE_871___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_871__RX_DCOC_RES_I_871___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_871__RX_DCOC_RES_Q_871___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_871__RX_DCOC_RANGE_871___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_871__RX_DCOC_RANGE_871___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_871__RX_DCOC_RES_I_871___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_871__RX_DCOC_RES_I_871___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_871__RX_DCOC_RES_Q_871___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_871__RX_DCOC_RES_Q_871___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_871___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_871___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_872 (0x005E4DA0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_872___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_872___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_872__RX_DCOC_RANGE_872___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_872__RX_DCOC_RES_I_872___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_872__RX_DCOC_RES_Q_872___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_872__RX_DCOC_RANGE_872___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_872__RX_DCOC_RANGE_872___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_872__RX_DCOC_RES_I_872___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_872__RX_DCOC_RES_I_872___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_872__RX_DCOC_RES_Q_872___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_872__RX_DCOC_RES_Q_872___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_872___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_872___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_873 (0x005E4DA4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_873___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_873___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_873__RX_DCOC_RANGE_873___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_873__RX_DCOC_RES_I_873___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_873__RX_DCOC_RES_Q_873___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_873__RX_DCOC_RANGE_873___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_873__RX_DCOC_RANGE_873___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_873__RX_DCOC_RES_I_873___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_873__RX_DCOC_RES_I_873___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_873__RX_DCOC_RES_Q_873___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_873__RX_DCOC_RES_Q_873___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_873___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_873___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_874 (0x005E4DA8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_874___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_874___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_874__RX_DCOC_RANGE_874___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_874__RX_DCOC_RES_I_874___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_874__RX_DCOC_RES_Q_874___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_874__RX_DCOC_RANGE_874___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_874__RX_DCOC_RANGE_874___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_874__RX_DCOC_RES_I_874___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_874__RX_DCOC_RES_I_874___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_874__RX_DCOC_RES_Q_874___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_874__RX_DCOC_RES_Q_874___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_874___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_874___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_875 (0x005E4DAC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_875___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_875___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_875__RX_DCOC_RANGE_875___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_875__RX_DCOC_RES_I_875___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_875__RX_DCOC_RES_Q_875___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_875__RX_DCOC_RANGE_875___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_875__RX_DCOC_RANGE_875___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_875__RX_DCOC_RES_I_875___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_875__RX_DCOC_RES_I_875___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_875__RX_DCOC_RES_Q_875___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_875__RX_DCOC_RES_Q_875___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_875___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_875___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_876 (0x005E4DB0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_876___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_876___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_876__RX_DCOC_RANGE_876___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_876__RX_DCOC_RES_I_876___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_876__RX_DCOC_RES_Q_876___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_876__RX_DCOC_RANGE_876___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_876__RX_DCOC_RANGE_876___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_876__RX_DCOC_RES_I_876___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_876__RX_DCOC_RES_I_876___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_876__RX_DCOC_RES_Q_876___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_876__RX_DCOC_RES_Q_876___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_876___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_876___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_877 (0x005E4DB4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_877___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_877___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_877__RX_DCOC_RANGE_877___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_877__RX_DCOC_RES_I_877___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_877__RX_DCOC_RES_Q_877___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_877__RX_DCOC_RANGE_877___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_877__RX_DCOC_RANGE_877___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_877__RX_DCOC_RES_I_877___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_877__RX_DCOC_RES_I_877___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_877__RX_DCOC_RES_Q_877___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_877__RX_DCOC_RES_Q_877___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_877___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_877___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_878 (0x005E4DB8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_878___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_878___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_878__RX_DCOC_RANGE_878___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_878__RX_DCOC_RES_I_878___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_878__RX_DCOC_RES_Q_878___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_878__RX_DCOC_RANGE_878___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_878__RX_DCOC_RANGE_878___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_878__RX_DCOC_RES_I_878___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_878__RX_DCOC_RES_I_878___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_878__RX_DCOC_RES_Q_878___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_878__RX_DCOC_RES_Q_878___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_878___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_878___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_879 (0x005E4DBC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_879___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_879___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_879__RX_DCOC_RANGE_879___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_879__RX_DCOC_RES_I_879___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_879__RX_DCOC_RES_Q_879___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_879__RX_DCOC_RANGE_879___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_879__RX_DCOC_RANGE_879___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_879__RX_DCOC_RES_I_879___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_879__RX_DCOC_RES_I_879___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_879__RX_DCOC_RES_Q_879___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_879__RX_DCOC_RES_Q_879___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_879___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_879___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_880 (0x005E4DC0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_880___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_880___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_880__RX_DCOC_RANGE_880___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_880__RX_DCOC_RES_I_880___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_880__RX_DCOC_RES_Q_880___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_880__RX_DCOC_RANGE_880___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_880__RX_DCOC_RANGE_880___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_880__RX_DCOC_RES_I_880___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_880__RX_DCOC_RES_I_880___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_880__RX_DCOC_RES_Q_880___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_880__RX_DCOC_RES_Q_880___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_880___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_880___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_881 (0x005E4DC4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_881___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_881___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_881__RX_DCOC_RANGE_881___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_881__RX_DCOC_RES_I_881___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_881__RX_DCOC_RES_Q_881___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_881__RX_DCOC_RANGE_881___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_881__RX_DCOC_RANGE_881___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_881__RX_DCOC_RES_I_881___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_881__RX_DCOC_RES_I_881___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_881__RX_DCOC_RES_Q_881___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_881__RX_DCOC_RES_Q_881___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_881___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_881___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_882 (0x005E4DC8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_882___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_882___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_882__RX_DCOC_RANGE_882___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_882__RX_DCOC_RES_I_882___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_882__RX_DCOC_RES_Q_882___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_882__RX_DCOC_RANGE_882___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_882__RX_DCOC_RANGE_882___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_882__RX_DCOC_RES_I_882___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_882__RX_DCOC_RES_I_882___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_882__RX_DCOC_RES_Q_882___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_882__RX_DCOC_RES_Q_882___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_882___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_882___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_883 (0x005E4DCC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_883___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_883___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_883__RX_DCOC_RANGE_883___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_883__RX_DCOC_RES_I_883___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_883__RX_DCOC_RES_Q_883___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_883__RX_DCOC_RANGE_883___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_883__RX_DCOC_RANGE_883___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_883__RX_DCOC_RES_I_883___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_883__RX_DCOC_RES_I_883___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_883__RX_DCOC_RES_Q_883___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_883__RX_DCOC_RES_Q_883___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_883___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_883___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_884 (0x005E4DD0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_884___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_884___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_884__RX_DCOC_RANGE_884___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_884__RX_DCOC_RES_I_884___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_884__RX_DCOC_RES_Q_884___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_884__RX_DCOC_RANGE_884___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_884__RX_DCOC_RANGE_884___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_884__RX_DCOC_RES_I_884___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_884__RX_DCOC_RES_I_884___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_884__RX_DCOC_RES_Q_884___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_884__RX_DCOC_RES_Q_884___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_884___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_884___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_885 (0x005E4DD4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_885___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_885___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_885__RX_DCOC_RANGE_885___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_885__RX_DCOC_RES_I_885___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_885__RX_DCOC_RES_Q_885___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_885__RX_DCOC_RANGE_885___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_885__RX_DCOC_RANGE_885___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_885__RX_DCOC_RES_I_885___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_885__RX_DCOC_RES_I_885___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_885__RX_DCOC_RES_Q_885___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_885__RX_DCOC_RES_Q_885___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_885___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_885___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_886 (0x005E4DD8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_886___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_886___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_886__RX_DCOC_RANGE_886___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_886__RX_DCOC_RES_I_886___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_886__RX_DCOC_RES_Q_886___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_886__RX_DCOC_RANGE_886___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_886__RX_DCOC_RANGE_886___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_886__RX_DCOC_RES_I_886___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_886__RX_DCOC_RES_I_886___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_886__RX_DCOC_RES_Q_886___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_886__RX_DCOC_RES_Q_886___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_886___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_886___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_887 (0x005E4DDC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_887___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_887___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_887__RX_DCOC_RANGE_887___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_887__RX_DCOC_RES_I_887___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_887__RX_DCOC_RES_Q_887___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_887__RX_DCOC_RANGE_887___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_887__RX_DCOC_RANGE_887___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_887__RX_DCOC_RES_I_887___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_887__RX_DCOC_RES_I_887___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_887__RX_DCOC_RES_Q_887___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_887__RX_DCOC_RES_Q_887___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_887___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_887___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_888 (0x005E4DE0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_888___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_888___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_888__RX_DCOC_RANGE_888___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_888__RX_DCOC_RES_I_888___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_888__RX_DCOC_RES_Q_888___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_888__RX_DCOC_RANGE_888___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_888__RX_DCOC_RANGE_888___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_888__RX_DCOC_RES_I_888___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_888__RX_DCOC_RES_I_888___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_888__RX_DCOC_RES_Q_888___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_888__RX_DCOC_RES_Q_888___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_888___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_888___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_889 (0x005E4DE4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_889___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_889___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_889__RX_DCOC_RANGE_889___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_889__RX_DCOC_RES_I_889___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_889__RX_DCOC_RES_Q_889___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_889__RX_DCOC_RANGE_889___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_889__RX_DCOC_RANGE_889___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_889__RX_DCOC_RES_I_889___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_889__RX_DCOC_RES_I_889___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_889__RX_DCOC_RES_Q_889___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_889__RX_DCOC_RES_Q_889___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_889___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_889___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_890 (0x005E4DE8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_890___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_890___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_890__RX_DCOC_RANGE_890___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_890__RX_DCOC_RES_I_890___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_890__RX_DCOC_RES_Q_890___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_890__RX_DCOC_RANGE_890___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_890__RX_DCOC_RANGE_890___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_890__RX_DCOC_RES_I_890___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_890__RX_DCOC_RES_I_890___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_890__RX_DCOC_RES_Q_890___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_890__RX_DCOC_RES_Q_890___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_890___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_890___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_891 (0x005E4DEC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_891___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_891___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_891__RX_DCOC_RANGE_891___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_891__RX_DCOC_RES_I_891___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_891__RX_DCOC_RES_Q_891___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_891__RX_DCOC_RANGE_891___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_891__RX_DCOC_RANGE_891___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_891__RX_DCOC_RES_I_891___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_891__RX_DCOC_RES_I_891___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_891__RX_DCOC_RES_Q_891___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_891__RX_DCOC_RES_Q_891___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_891___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_891___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_892 (0x005E4DF0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_892___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_892___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_892__RX_DCOC_RANGE_892___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_892__RX_DCOC_RES_I_892___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_892__RX_DCOC_RES_Q_892___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_892__RX_DCOC_RANGE_892___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_892__RX_DCOC_RANGE_892___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_892__RX_DCOC_RES_I_892___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_892__RX_DCOC_RES_I_892___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_892__RX_DCOC_RES_Q_892___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_892__RX_DCOC_RES_Q_892___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_892___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_892___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_893 (0x005E4DF4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_893___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_893___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_893__RX_DCOC_RANGE_893___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_893__RX_DCOC_RES_I_893___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_893__RX_DCOC_RES_Q_893___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_893__RX_DCOC_RANGE_893___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_893__RX_DCOC_RANGE_893___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_893__RX_DCOC_RES_I_893___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_893__RX_DCOC_RES_I_893___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_893__RX_DCOC_RES_Q_893___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_893__RX_DCOC_RES_Q_893___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_893___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_893___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_894 (0x005E4DF8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_894___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_894___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_894__RX_DCOC_RANGE_894___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_894__RX_DCOC_RES_I_894___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_894__RX_DCOC_RES_Q_894___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_894__RX_DCOC_RANGE_894___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_894__RX_DCOC_RANGE_894___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_894__RX_DCOC_RES_I_894___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_894__RX_DCOC_RES_I_894___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_894__RX_DCOC_RES_Q_894___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_894__RX_DCOC_RES_Q_894___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_894___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_894___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_895 (0x005E4DFC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_895___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_895___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_895__RX_DCOC_RANGE_895___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_895__RX_DCOC_RES_I_895___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_895__RX_DCOC_RES_Q_895___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_895__RX_DCOC_RANGE_895___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_895__RX_DCOC_RANGE_895___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_895__RX_DCOC_RES_I_895___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_895__RX_DCOC_RES_I_895___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_895__RX_DCOC_RES_Q_895___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_895__RX_DCOC_RES_Q_895___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_895___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_895___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_896 (0x005E4E00) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_896___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_896___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_896__RX_DCOC_RANGE_896___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_896__RX_DCOC_RES_I_896___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_896__RX_DCOC_RES_Q_896___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_896__RX_DCOC_RANGE_896___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_896__RX_DCOC_RANGE_896___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_896__RX_DCOC_RES_I_896___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_896__RX_DCOC_RES_I_896___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_896__RX_DCOC_RES_Q_896___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_896__RX_DCOC_RES_Q_896___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_896___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_896___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_897 (0x005E4E04) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_897___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_897___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_897__RX_DCOC_RANGE_897___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_897__RX_DCOC_RES_I_897___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_897__RX_DCOC_RES_Q_897___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_897__RX_DCOC_RANGE_897___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_897__RX_DCOC_RANGE_897___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_897__RX_DCOC_RES_I_897___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_897__RX_DCOC_RES_I_897___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_897__RX_DCOC_RES_Q_897___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_897__RX_DCOC_RES_Q_897___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_897___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_897___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_898 (0x005E4E08) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_898___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_898___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_898__RX_DCOC_RANGE_898___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_898__RX_DCOC_RES_I_898___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_898__RX_DCOC_RES_Q_898___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_898__RX_DCOC_RANGE_898___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_898__RX_DCOC_RANGE_898___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_898__RX_DCOC_RES_I_898___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_898__RX_DCOC_RES_I_898___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_898__RX_DCOC_RES_Q_898___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_898__RX_DCOC_RES_Q_898___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_898___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_898___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_899 (0x005E4E0C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_899___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_899___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_899__RX_DCOC_RANGE_899___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_899__RX_DCOC_RES_I_899___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_899__RX_DCOC_RES_Q_899___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_899__RX_DCOC_RANGE_899___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_899__RX_DCOC_RANGE_899___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_899__RX_DCOC_RES_I_899___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_899__RX_DCOC_RES_I_899___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_899__RX_DCOC_RES_Q_899___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_899__RX_DCOC_RES_Q_899___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_899___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_899___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_900 (0x005E4E10) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_900___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_900___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_900__RX_DCOC_RANGE_900___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_900__RX_DCOC_RES_I_900___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_900__RX_DCOC_RES_Q_900___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_900__RX_DCOC_RANGE_900___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_900__RX_DCOC_RANGE_900___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_900__RX_DCOC_RES_I_900___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_900__RX_DCOC_RES_I_900___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_900__RX_DCOC_RES_Q_900___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_900__RX_DCOC_RES_Q_900___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_900___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_900___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_901 (0x005E4E14) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_901___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_901___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_901__RX_DCOC_RANGE_901___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_901__RX_DCOC_RES_I_901___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_901__RX_DCOC_RES_Q_901___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_901__RX_DCOC_RANGE_901___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_901__RX_DCOC_RANGE_901___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_901__RX_DCOC_RES_I_901___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_901__RX_DCOC_RES_I_901___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_901__RX_DCOC_RES_Q_901___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_901__RX_DCOC_RES_Q_901___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_901___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_901___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_902 (0x005E4E18) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_902___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_902___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_902__RX_DCOC_RANGE_902___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_902__RX_DCOC_RES_I_902___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_902__RX_DCOC_RES_Q_902___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_902__RX_DCOC_RANGE_902___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_902__RX_DCOC_RANGE_902___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_902__RX_DCOC_RES_I_902___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_902__RX_DCOC_RES_I_902___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_902__RX_DCOC_RES_Q_902___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_902__RX_DCOC_RES_Q_902___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_902___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_902___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_903 (0x005E4E1C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_903___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_903___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_903__RX_DCOC_RANGE_903___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_903__RX_DCOC_RES_I_903___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_903__RX_DCOC_RES_Q_903___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_903__RX_DCOC_RANGE_903___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_903__RX_DCOC_RANGE_903___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_903__RX_DCOC_RES_I_903___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_903__RX_DCOC_RES_I_903___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_903__RX_DCOC_RES_Q_903___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_903__RX_DCOC_RES_Q_903___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_903___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_903___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_904 (0x005E4E20) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_904___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_904___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_904__RX_DCOC_RANGE_904___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_904__RX_DCOC_RES_I_904___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_904__RX_DCOC_RES_Q_904___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_904__RX_DCOC_RANGE_904___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_904__RX_DCOC_RANGE_904___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_904__RX_DCOC_RES_I_904___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_904__RX_DCOC_RES_I_904___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_904__RX_DCOC_RES_Q_904___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_904__RX_DCOC_RES_Q_904___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_904___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_904___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_905 (0x005E4E24) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_905___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_905___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_905__RX_DCOC_RANGE_905___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_905__RX_DCOC_RES_I_905___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_905__RX_DCOC_RES_Q_905___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_905__RX_DCOC_RANGE_905___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_905__RX_DCOC_RANGE_905___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_905__RX_DCOC_RES_I_905___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_905__RX_DCOC_RES_I_905___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_905__RX_DCOC_RES_Q_905___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_905__RX_DCOC_RES_Q_905___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_905___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_905___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_906 (0x005E4E28) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_906___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_906___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_906__RX_DCOC_RANGE_906___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_906__RX_DCOC_RES_I_906___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_906__RX_DCOC_RES_Q_906___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_906__RX_DCOC_RANGE_906___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_906__RX_DCOC_RANGE_906___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_906__RX_DCOC_RES_I_906___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_906__RX_DCOC_RES_I_906___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_906__RX_DCOC_RES_Q_906___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_906__RX_DCOC_RES_Q_906___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_906___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_906___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_907 (0x005E4E2C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_907___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_907___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_907__RX_DCOC_RANGE_907___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_907__RX_DCOC_RES_I_907___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_907__RX_DCOC_RES_Q_907___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_907__RX_DCOC_RANGE_907___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_907__RX_DCOC_RANGE_907___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_907__RX_DCOC_RES_I_907___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_907__RX_DCOC_RES_I_907___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_907__RX_DCOC_RES_Q_907___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_907__RX_DCOC_RES_Q_907___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_907___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_907___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_908 (0x005E4E30) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_908___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_908___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_908__RX_DCOC_RANGE_908___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_908__RX_DCOC_RES_I_908___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_908__RX_DCOC_RES_Q_908___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_908__RX_DCOC_RANGE_908___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_908__RX_DCOC_RANGE_908___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_908__RX_DCOC_RES_I_908___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_908__RX_DCOC_RES_I_908___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_908__RX_DCOC_RES_Q_908___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_908__RX_DCOC_RES_Q_908___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_908___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_908___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_909 (0x005E4E34) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_909___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_909___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_909__RX_DCOC_RANGE_909___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_909__RX_DCOC_RES_I_909___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_909__RX_DCOC_RES_Q_909___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_909__RX_DCOC_RANGE_909___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_909__RX_DCOC_RANGE_909___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_909__RX_DCOC_RES_I_909___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_909__RX_DCOC_RES_I_909___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_909__RX_DCOC_RES_Q_909___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_909__RX_DCOC_RES_Q_909___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_909___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_909___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_910 (0x005E4E38) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_910___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_910___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_910__RX_DCOC_RANGE_910___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_910__RX_DCOC_RES_I_910___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_910__RX_DCOC_RES_Q_910___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_910__RX_DCOC_RANGE_910___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_910__RX_DCOC_RANGE_910___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_910__RX_DCOC_RES_I_910___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_910__RX_DCOC_RES_I_910___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_910__RX_DCOC_RES_Q_910___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_910__RX_DCOC_RES_Q_910___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_910___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_910___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_911 (0x005E4E3C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_911___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_911___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_911__RX_DCOC_RANGE_911___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_911__RX_DCOC_RES_I_911___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_911__RX_DCOC_RES_Q_911___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_911__RX_DCOC_RANGE_911___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_911__RX_DCOC_RANGE_911___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_911__RX_DCOC_RES_I_911___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_911__RX_DCOC_RES_I_911___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_911__RX_DCOC_RES_Q_911___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_911__RX_DCOC_RES_Q_911___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_911___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_911___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_912 (0x005E4E40) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_912___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_912___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_912__RX_DCOC_RANGE_912___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_912__RX_DCOC_RES_I_912___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_912__RX_DCOC_RES_Q_912___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_912__RX_DCOC_RANGE_912___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_912__RX_DCOC_RANGE_912___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_912__RX_DCOC_RES_I_912___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_912__RX_DCOC_RES_I_912___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_912__RX_DCOC_RES_Q_912___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_912__RX_DCOC_RES_Q_912___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_912___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_912___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_913 (0x005E4E44) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_913___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_913___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_913__RX_DCOC_RANGE_913___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_913__RX_DCOC_RES_I_913___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_913__RX_DCOC_RES_Q_913___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_913__RX_DCOC_RANGE_913___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_913__RX_DCOC_RANGE_913___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_913__RX_DCOC_RES_I_913___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_913__RX_DCOC_RES_I_913___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_913__RX_DCOC_RES_Q_913___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_913__RX_DCOC_RES_Q_913___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_913___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_913___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_914 (0x005E4E48) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_914___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_914___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_914__RX_DCOC_RANGE_914___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_914__RX_DCOC_RES_I_914___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_914__RX_DCOC_RES_Q_914___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_914__RX_DCOC_RANGE_914___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_914__RX_DCOC_RANGE_914___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_914__RX_DCOC_RES_I_914___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_914__RX_DCOC_RES_I_914___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_914__RX_DCOC_RES_Q_914___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_914__RX_DCOC_RES_Q_914___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_914___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_914___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_915 (0x005E4E4C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_915___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_915___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_915__RX_DCOC_RANGE_915___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_915__RX_DCOC_RES_I_915___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_915__RX_DCOC_RES_Q_915___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_915__RX_DCOC_RANGE_915___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_915__RX_DCOC_RANGE_915___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_915__RX_DCOC_RES_I_915___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_915__RX_DCOC_RES_I_915___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_915__RX_DCOC_RES_Q_915___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_915__RX_DCOC_RES_Q_915___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_915___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_915___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_916 (0x005E4E50) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_916___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_916___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_916__RX_DCOC_RANGE_916___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_916__RX_DCOC_RES_I_916___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_916__RX_DCOC_RES_Q_916___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_916__RX_DCOC_RANGE_916___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_916__RX_DCOC_RANGE_916___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_916__RX_DCOC_RES_I_916___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_916__RX_DCOC_RES_I_916___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_916__RX_DCOC_RES_Q_916___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_916__RX_DCOC_RES_Q_916___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_916___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_916___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_917 (0x005E4E54) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_917___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_917___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_917__RX_DCOC_RANGE_917___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_917__RX_DCOC_RES_I_917___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_917__RX_DCOC_RES_Q_917___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_917__RX_DCOC_RANGE_917___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_917__RX_DCOC_RANGE_917___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_917__RX_DCOC_RES_I_917___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_917__RX_DCOC_RES_I_917___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_917__RX_DCOC_RES_Q_917___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_917__RX_DCOC_RES_Q_917___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_917___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_917___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_918 (0x005E4E58) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_918___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_918___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_918__RX_DCOC_RANGE_918___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_918__RX_DCOC_RES_I_918___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_918__RX_DCOC_RES_Q_918___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_918__RX_DCOC_RANGE_918___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_918__RX_DCOC_RANGE_918___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_918__RX_DCOC_RES_I_918___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_918__RX_DCOC_RES_I_918___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_918__RX_DCOC_RES_Q_918___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_918__RX_DCOC_RES_Q_918___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_918___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_918___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_919 (0x005E4E5C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_919___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_919___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_919__RX_DCOC_RANGE_919___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_919__RX_DCOC_RES_I_919___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_919__RX_DCOC_RES_Q_919___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_919__RX_DCOC_RANGE_919___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_919__RX_DCOC_RANGE_919___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_919__RX_DCOC_RES_I_919___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_919__RX_DCOC_RES_I_919___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_919__RX_DCOC_RES_Q_919___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_919__RX_DCOC_RES_Q_919___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_919___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_919___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_920 (0x005E4E60) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_920___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_920___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_920__RX_DCOC_RANGE_920___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_920__RX_DCOC_RES_I_920___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_920__RX_DCOC_RES_Q_920___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_920__RX_DCOC_RANGE_920___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_920__RX_DCOC_RANGE_920___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_920__RX_DCOC_RES_I_920___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_920__RX_DCOC_RES_I_920___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_920__RX_DCOC_RES_Q_920___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_920__RX_DCOC_RES_Q_920___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_920___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_920___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_921 (0x005E4E64) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_921___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_921___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_921__RX_DCOC_RANGE_921___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_921__RX_DCOC_RES_I_921___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_921__RX_DCOC_RES_Q_921___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_921__RX_DCOC_RANGE_921___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_921__RX_DCOC_RANGE_921___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_921__RX_DCOC_RES_I_921___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_921__RX_DCOC_RES_I_921___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_921__RX_DCOC_RES_Q_921___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_921__RX_DCOC_RES_Q_921___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_921___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_921___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_922 (0x005E4E68) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_922___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_922___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_922__RX_DCOC_RANGE_922___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_922__RX_DCOC_RES_I_922___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_922__RX_DCOC_RES_Q_922___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_922__RX_DCOC_RANGE_922___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_922__RX_DCOC_RANGE_922___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_922__RX_DCOC_RES_I_922___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_922__RX_DCOC_RES_I_922___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_922__RX_DCOC_RES_Q_922___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_922__RX_DCOC_RES_Q_922___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_922___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_922___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_923 (0x005E4E6C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_923___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_923___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_923__RX_DCOC_RANGE_923___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_923__RX_DCOC_RES_I_923___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_923__RX_DCOC_RES_Q_923___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_923__RX_DCOC_RANGE_923___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_923__RX_DCOC_RANGE_923___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_923__RX_DCOC_RES_I_923___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_923__RX_DCOC_RES_I_923___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_923__RX_DCOC_RES_Q_923___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_923__RX_DCOC_RES_Q_923___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_923___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_923___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_924 (0x005E4E70) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_924___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_924___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_924__RX_DCOC_RANGE_924___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_924__RX_DCOC_RES_I_924___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_924__RX_DCOC_RES_Q_924___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_924__RX_DCOC_RANGE_924___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_924__RX_DCOC_RANGE_924___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_924__RX_DCOC_RES_I_924___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_924__RX_DCOC_RES_I_924___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_924__RX_DCOC_RES_Q_924___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_924__RX_DCOC_RES_Q_924___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_924___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_924___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_925 (0x005E4E74) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_925___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_925___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_925__RX_DCOC_RANGE_925___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_925__RX_DCOC_RES_I_925___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_925__RX_DCOC_RES_Q_925___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_925__RX_DCOC_RANGE_925___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_925__RX_DCOC_RANGE_925___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_925__RX_DCOC_RES_I_925___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_925__RX_DCOC_RES_I_925___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_925__RX_DCOC_RES_Q_925___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_925__RX_DCOC_RES_Q_925___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_925___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_925___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_926 (0x005E4E78) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_926___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_926___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_926__RX_DCOC_RANGE_926___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_926__RX_DCOC_RES_I_926___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_926__RX_DCOC_RES_Q_926___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_926__RX_DCOC_RANGE_926___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_926__RX_DCOC_RANGE_926___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_926__RX_DCOC_RES_I_926___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_926__RX_DCOC_RES_I_926___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_926__RX_DCOC_RES_Q_926___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_926__RX_DCOC_RES_Q_926___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_926___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_926___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_927 (0x005E4E7C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_927___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_927___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_927__RX_DCOC_RANGE_927___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_927__RX_DCOC_RES_I_927___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_927__RX_DCOC_RES_Q_927___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_927__RX_DCOC_RANGE_927___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_927__RX_DCOC_RANGE_927___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_927__RX_DCOC_RES_I_927___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_927__RX_DCOC_RES_I_927___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_927__RX_DCOC_RES_Q_927___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_927__RX_DCOC_RES_Q_927___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_927___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_927___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_928 (0x005E4E80) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_928___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_928___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_928__RX_DCOC_RANGE_928___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_928__RX_DCOC_RES_I_928___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_928__RX_DCOC_RES_Q_928___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_928__RX_DCOC_RANGE_928___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_928__RX_DCOC_RANGE_928___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_928__RX_DCOC_RES_I_928___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_928__RX_DCOC_RES_I_928___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_928__RX_DCOC_RES_Q_928___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_928__RX_DCOC_RES_Q_928___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_928___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_928___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_929 (0x005E4E84) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_929___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_929___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_929__RX_DCOC_RANGE_929___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_929__RX_DCOC_RES_I_929___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_929__RX_DCOC_RES_Q_929___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_929__RX_DCOC_RANGE_929___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_929__RX_DCOC_RANGE_929___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_929__RX_DCOC_RES_I_929___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_929__RX_DCOC_RES_I_929___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_929__RX_DCOC_RES_Q_929___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_929__RX_DCOC_RES_Q_929___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_929___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_929___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_930 (0x005E4E88) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_930___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_930___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_930__RX_DCOC_RANGE_930___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_930__RX_DCOC_RES_I_930___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_930__RX_DCOC_RES_Q_930___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_930__RX_DCOC_RANGE_930___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_930__RX_DCOC_RANGE_930___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_930__RX_DCOC_RES_I_930___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_930__RX_DCOC_RES_I_930___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_930__RX_DCOC_RES_Q_930___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_930__RX_DCOC_RES_Q_930___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_930___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_930___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_931 (0x005E4E8C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_931___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_931___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_931__RX_DCOC_RANGE_931___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_931__RX_DCOC_RES_I_931___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_931__RX_DCOC_RES_Q_931___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_931__RX_DCOC_RANGE_931___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_931__RX_DCOC_RANGE_931___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_931__RX_DCOC_RES_I_931___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_931__RX_DCOC_RES_I_931___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_931__RX_DCOC_RES_Q_931___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_931__RX_DCOC_RES_Q_931___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_931___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_931___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_932 (0x005E4E90) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_932___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_932___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_932__RX_DCOC_RANGE_932___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_932__RX_DCOC_RES_I_932___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_932__RX_DCOC_RES_Q_932___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_932__RX_DCOC_RANGE_932___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_932__RX_DCOC_RANGE_932___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_932__RX_DCOC_RES_I_932___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_932__RX_DCOC_RES_I_932___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_932__RX_DCOC_RES_Q_932___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_932__RX_DCOC_RES_Q_932___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_932___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_932___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_933 (0x005E4E94) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_933___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_933___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_933__RX_DCOC_RANGE_933___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_933__RX_DCOC_RES_I_933___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_933__RX_DCOC_RES_Q_933___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_933__RX_DCOC_RANGE_933___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_933__RX_DCOC_RANGE_933___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_933__RX_DCOC_RES_I_933___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_933__RX_DCOC_RES_I_933___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_933__RX_DCOC_RES_Q_933___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_933__RX_DCOC_RES_Q_933___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_933___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_933___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_934 (0x005E4E98) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_934___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_934___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_934__RX_DCOC_RANGE_934___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_934__RX_DCOC_RES_I_934___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_934__RX_DCOC_RES_Q_934___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_934__RX_DCOC_RANGE_934___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_934__RX_DCOC_RANGE_934___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_934__RX_DCOC_RES_I_934___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_934__RX_DCOC_RES_I_934___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_934__RX_DCOC_RES_Q_934___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_934__RX_DCOC_RES_Q_934___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_934___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_934___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_935 (0x005E4E9C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_935___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_935___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_935__RX_DCOC_RANGE_935___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_935__RX_DCOC_RES_I_935___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_935__RX_DCOC_RES_Q_935___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_935__RX_DCOC_RANGE_935___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_935__RX_DCOC_RANGE_935___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_935__RX_DCOC_RES_I_935___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_935__RX_DCOC_RES_I_935___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_935__RX_DCOC_RES_Q_935___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_935__RX_DCOC_RES_Q_935___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_935___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_935___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_936 (0x005E4EA0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_936___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_936___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_936__RX_DCOC_RANGE_936___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_936__RX_DCOC_RES_I_936___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_936__RX_DCOC_RES_Q_936___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_936__RX_DCOC_RANGE_936___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_936__RX_DCOC_RANGE_936___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_936__RX_DCOC_RES_I_936___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_936__RX_DCOC_RES_I_936___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_936__RX_DCOC_RES_Q_936___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_936__RX_DCOC_RES_Q_936___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_936___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_936___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_937 (0x005E4EA4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_937___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_937___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_937__RX_DCOC_RANGE_937___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_937__RX_DCOC_RES_I_937___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_937__RX_DCOC_RES_Q_937___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_937__RX_DCOC_RANGE_937___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_937__RX_DCOC_RANGE_937___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_937__RX_DCOC_RES_I_937___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_937__RX_DCOC_RES_I_937___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_937__RX_DCOC_RES_Q_937___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_937__RX_DCOC_RES_Q_937___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_937___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_937___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_938 (0x005E4EA8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_938___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_938___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_938__RX_DCOC_RANGE_938___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_938__RX_DCOC_RES_I_938___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_938__RX_DCOC_RES_Q_938___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_938__RX_DCOC_RANGE_938___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_938__RX_DCOC_RANGE_938___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_938__RX_DCOC_RES_I_938___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_938__RX_DCOC_RES_I_938___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_938__RX_DCOC_RES_Q_938___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_938__RX_DCOC_RES_Q_938___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_938___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_938___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_939 (0x005E4EAC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_939___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_939___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_939__RX_DCOC_RANGE_939___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_939__RX_DCOC_RES_I_939___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_939__RX_DCOC_RES_Q_939___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_939__RX_DCOC_RANGE_939___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_939__RX_DCOC_RANGE_939___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_939__RX_DCOC_RES_I_939___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_939__RX_DCOC_RES_I_939___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_939__RX_DCOC_RES_Q_939___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_939__RX_DCOC_RES_Q_939___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_939___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_939___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_940 (0x005E4EB0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_940___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_940___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_940__RX_DCOC_RANGE_940___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_940__RX_DCOC_RES_I_940___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_940__RX_DCOC_RES_Q_940___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_940__RX_DCOC_RANGE_940___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_940__RX_DCOC_RANGE_940___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_940__RX_DCOC_RES_I_940___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_940__RX_DCOC_RES_I_940___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_940__RX_DCOC_RES_Q_940___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_940__RX_DCOC_RES_Q_940___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_940___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_940___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_941 (0x005E4EB4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_941___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_941___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_941__RX_DCOC_RANGE_941___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_941__RX_DCOC_RES_I_941___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_941__RX_DCOC_RES_Q_941___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_941__RX_DCOC_RANGE_941___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_941__RX_DCOC_RANGE_941___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_941__RX_DCOC_RES_I_941___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_941__RX_DCOC_RES_I_941___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_941__RX_DCOC_RES_Q_941___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_941__RX_DCOC_RES_Q_941___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_941___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_941___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_942 (0x005E4EB8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_942___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_942___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_942__RX_DCOC_RANGE_942___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_942__RX_DCOC_RES_I_942___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_942__RX_DCOC_RES_Q_942___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_942__RX_DCOC_RANGE_942___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_942__RX_DCOC_RANGE_942___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_942__RX_DCOC_RES_I_942___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_942__RX_DCOC_RES_I_942___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_942__RX_DCOC_RES_Q_942___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_942__RX_DCOC_RES_Q_942___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_942___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_942___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_943 (0x005E4EBC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_943___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_943___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_943__RX_DCOC_RANGE_943___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_943__RX_DCOC_RES_I_943___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_943__RX_DCOC_RES_Q_943___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_943__RX_DCOC_RANGE_943___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_943__RX_DCOC_RANGE_943___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_943__RX_DCOC_RES_I_943___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_943__RX_DCOC_RES_I_943___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_943__RX_DCOC_RES_Q_943___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_943__RX_DCOC_RES_Q_943___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_943___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_943___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_944 (0x005E4EC0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_944___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_944___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_944__RX_DCOC_RANGE_944___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_944__RX_DCOC_RES_I_944___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_944__RX_DCOC_RES_Q_944___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_944__RX_DCOC_RANGE_944___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_944__RX_DCOC_RANGE_944___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_944__RX_DCOC_RES_I_944___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_944__RX_DCOC_RES_I_944___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_944__RX_DCOC_RES_Q_944___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_944__RX_DCOC_RES_Q_944___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_944___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_944___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_945 (0x005E4EC4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_945___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_945___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_945__RX_DCOC_RANGE_945___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_945__RX_DCOC_RES_I_945___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_945__RX_DCOC_RES_Q_945___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_945__RX_DCOC_RANGE_945___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_945__RX_DCOC_RANGE_945___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_945__RX_DCOC_RES_I_945___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_945__RX_DCOC_RES_I_945___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_945__RX_DCOC_RES_Q_945___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_945__RX_DCOC_RES_Q_945___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_945___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_945___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_946 (0x005E4EC8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_946___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_946___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_946__RX_DCOC_RANGE_946___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_946__RX_DCOC_RES_I_946___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_946__RX_DCOC_RES_Q_946___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_946__RX_DCOC_RANGE_946___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_946__RX_DCOC_RANGE_946___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_946__RX_DCOC_RES_I_946___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_946__RX_DCOC_RES_I_946___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_946__RX_DCOC_RES_Q_946___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_946__RX_DCOC_RES_Q_946___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_946___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_946___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_947 (0x005E4ECC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_947___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_947___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_947__RX_DCOC_RANGE_947___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_947__RX_DCOC_RES_I_947___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_947__RX_DCOC_RES_Q_947___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_947__RX_DCOC_RANGE_947___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_947__RX_DCOC_RANGE_947___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_947__RX_DCOC_RES_I_947___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_947__RX_DCOC_RES_I_947___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_947__RX_DCOC_RES_Q_947___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_947__RX_DCOC_RES_Q_947___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_947___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_947___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_948 (0x005E4ED0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_948___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_948___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_948__RX_DCOC_RANGE_948___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_948__RX_DCOC_RES_I_948___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_948__RX_DCOC_RES_Q_948___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_948__RX_DCOC_RANGE_948___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_948__RX_DCOC_RANGE_948___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_948__RX_DCOC_RES_I_948___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_948__RX_DCOC_RES_I_948___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_948__RX_DCOC_RES_Q_948___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_948__RX_DCOC_RES_Q_948___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_948___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_948___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_949 (0x005E4ED4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_949___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_949___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_949__RX_DCOC_RANGE_949___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_949__RX_DCOC_RES_I_949___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_949__RX_DCOC_RES_Q_949___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_949__RX_DCOC_RANGE_949___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_949__RX_DCOC_RANGE_949___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_949__RX_DCOC_RES_I_949___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_949__RX_DCOC_RES_I_949___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_949__RX_DCOC_RES_Q_949___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_949__RX_DCOC_RES_Q_949___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_949___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_949___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_950 (0x005E4ED8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_950___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_950___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_950__RX_DCOC_RANGE_950___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_950__RX_DCOC_RES_I_950___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_950__RX_DCOC_RES_Q_950___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_950__RX_DCOC_RANGE_950___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_950__RX_DCOC_RANGE_950___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_950__RX_DCOC_RES_I_950___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_950__RX_DCOC_RES_I_950___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_950__RX_DCOC_RES_Q_950___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_950__RX_DCOC_RES_Q_950___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_950___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_950___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_951 (0x005E4EDC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_951___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_951___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_951__RX_DCOC_RANGE_951___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_951__RX_DCOC_RES_I_951___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_951__RX_DCOC_RES_Q_951___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_951__RX_DCOC_RANGE_951___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_951__RX_DCOC_RANGE_951___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_951__RX_DCOC_RES_I_951___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_951__RX_DCOC_RES_I_951___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_951__RX_DCOC_RES_Q_951___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_951__RX_DCOC_RES_Q_951___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_951___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_951___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_952 (0x005E4EE0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_952___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_952___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_952__RX_DCOC_RANGE_952___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_952__RX_DCOC_RES_I_952___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_952__RX_DCOC_RES_Q_952___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_952__RX_DCOC_RANGE_952___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_952__RX_DCOC_RANGE_952___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_952__RX_DCOC_RES_I_952___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_952__RX_DCOC_RES_I_952___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_952__RX_DCOC_RES_Q_952___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_952__RX_DCOC_RES_Q_952___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_952___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_952___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_953 (0x005E4EE4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_953___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_953___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_953__RX_DCOC_RANGE_953___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_953__RX_DCOC_RES_I_953___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_953__RX_DCOC_RES_Q_953___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_953__RX_DCOC_RANGE_953___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_953__RX_DCOC_RANGE_953___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_953__RX_DCOC_RES_I_953___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_953__RX_DCOC_RES_I_953___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_953__RX_DCOC_RES_Q_953___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_953__RX_DCOC_RES_Q_953___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_953___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_953___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_954 (0x005E4EE8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_954___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_954___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_954__RX_DCOC_RANGE_954___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_954__RX_DCOC_RES_I_954___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_954__RX_DCOC_RES_Q_954___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_954__RX_DCOC_RANGE_954___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_954__RX_DCOC_RANGE_954___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_954__RX_DCOC_RES_I_954___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_954__RX_DCOC_RES_I_954___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_954__RX_DCOC_RES_Q_954___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_954__RX_DCOC_RES_Q_954___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_954___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_954___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_955 (0x005E4EEC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_955___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_955___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_955__RX_DCOC_RANGE_955___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_955__RX_DCOC_RES_I_955___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_955__RX_DCOC_RES_Q_955___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_955__RX_DCOC_RANGE_955___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_955__RX_DCOC_RANGE_955___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_955__RX_DCOC_RES_I_955___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_955__RX_DCOC_RES_I_955___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_955__RX_DCOC_RES_Q_955___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_955__RX_DCOC_RES_Q_955___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_955___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_955___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_956 (0x005E4EF0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_956___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_956___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_956__RX_DCOC_RANGE_956___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_956__RX_DCOC_RES_I_956___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_956__RX_DCOC_RES_Q_956___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_956__RX_DCOC_RANGE_956___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_956__RX_DCOC_RANGE_956___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_956__RX_DCOC_RES_I_956___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_956__RX_DCOC_RES_I_956___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_956__RX_DCOC_RES_Q_956___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_956__RX_DCOC_RES_Q_956___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_956___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_956___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_957 (0x005E4EF4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_957___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_957___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_957__RX_DCOC_RANGE_957___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_957__RX_DCOC_RES_I_957___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_957__RX_DCOC_RES_Q_957___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_957__RX_DCOC_RANGE_957___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_957__RX_DCOC_RANGE_957___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_957__RX_DCOC_RES_I_957___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_957__RX_DCOC_RES_I_957___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_957__RX_DCOC_RES_Q_957___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_957__RX_DCOC_RES_Q_957___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_957___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_957___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_958 (0x005E4EF8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_958___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_958___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_958__RX_DCOC_RANGE_958___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_958__RX_DCOC_RES_I_958___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_958__RX_DCOC_RES_Q_958___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_958__RX_DCOC_RANGE_958___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_958__RX_DCOC_RANGE_958___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_958__RX_DCOC_RES_I_958___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_958__RX_DCOC_RES_I_958___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_958__RX_DCOC_RES_Q_958___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_958__RX_DCOC_RES_Q_958___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_958___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_958___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_959 (0x005E4EFC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_959___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_959___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_959__RX_DCOC_RANGE_959___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_959__RX_DCOC_RES_I_959___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_959__RX_DCOC_RES_Q_959___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_959__RX_DCOC_RANGE_959___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_959__RX_DCOC_RANGE_959___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_959__RX_DCOC_RES_I_959___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_959__RX_DCOC_RES_I_959___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_959__RX_DCOC_RES_Q_959___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_959__RX_DCOC_RES_Q_959___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_959___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_959___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_960 (0x005E4F00) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_960___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_960___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_960__RX_DCOC_RANGE_960___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_960__RX_DCOC_RES_I_960___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_960__RX_DCOC_RES_Q_960___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_960__RX_DCOC_RANGE_960___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_960__RX_DCOC_RANGE_960___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_960__RX_DCOC_RES_I_960___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_960__RX_DCOC_RES_I_960___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_960__RX_DCOC_RES_Q_960___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_960__RX_DCOC_RES_Q_960___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_960___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_960___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_961 (0x005E4F04) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_961___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_961___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_961__RX_DCOC_RANGE_961___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_961__RX_DCOC_RES_I_961___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_961__RX_DCOC_RES_Q_961___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_961__RX_DCOC_RANGE_961___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_961__RX_DCOC_RANGE_961___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_961__RX_DCOC_RES_I_961___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_961__RX_DCOC_RES_I_961___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_961__RX_DCOC_RES_Q_961___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_961__RX_DCOC_RES_Q_961___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_961___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_961___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_962 (0x005E4F08) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_962___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_962___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_962__RX_DCOC_RANGE_962___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_962__RX_DCOC_RES_I_962___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_962__RX_DCOC_RES_Q_962___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_962__RX_DCOC_RANGE_962___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_962__RX_DCOC_RANGE_962___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_962__RX_DCOC_RES_I_962___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_962__RX_DCOC_RES_I_962___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_962__RX_DCOC_RES_Q_962___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_962__RX_DCOC_RES_Q_962___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_962___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_962___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_963 (0x005E4F0C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_963___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_963___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_963__RX_DCOC_RANGE_963___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_963__RX_DCOC_RES_I_963___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_963__RX_DCOC_RES_Q_963___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_963__RX_DCOC_RANGE_963___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_963__RX_DCOC_RANGE_963___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_963__RX_DCOC_RES_I_963___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_963__RX_DCOC_RES_I_963___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_963__RX_DCOC_RES_Q_963___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_963__RX_DCOC_RES_Q_963___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_963___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_963___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_964 (0x005E4F10) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_964___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_964___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_964__RX_DCOC_RANGE_964___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_964__RX_DCOC_RES_I_964___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_964__RX_DCOC_RES_Q_964___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_964__RX_DCOC_RANGE_964___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_964__RX_DCOC_RANGE_964___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_964__RX_DCOC_RES_I_964___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_964__RX_DCOC_RES_I_964___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_964__RX_DCOC_RES_Q_964___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_964__RX_DCOC_RES_Q_964___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_964___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_964___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_965 (0x005E4F14) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_965___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_965___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_965__RX_DCOC_RANGE_965___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_965__RX_DCOC_RES_I_965___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_965__RX_DCOC_RES_Q_965___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_965__RX_DCOC_RANGE_965___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_965__RX_DCOC_RANGE_965___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_965__RX_DCOC_RES_I_965___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_965__RX_DCOC_RES_I_965___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_965__RX_DCOC_RES_Q_965___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_965__RX_DCOC_RES_Q_965___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_965___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_965___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_966 (0x005E4F18) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_966___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_966___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_966__RX_DCOC_RANGE_966___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_966__RX_DCOC_RES_I_966___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_966__RX_DCOC_RES_Q_966___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_966__RX_DCOC_RANGE_966___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_966__RX_DCOC_RANGE_966___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_966__RX_DCOC_RES_I_966___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_966__RX_DCOC_RES_I_966___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_966__RX_DCOC_RES_Q_966___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_966__RX_DCOC_RES_Q_966___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_966___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_966___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_967 (0x005E4F1C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_967___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_967___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_967__RX_DCOC_RANGE_967___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_967__RX_DCOC_RES_I_967___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_967__RX_DCOC_RES_Q_967___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_967__RX_DCOC_RANGE_967___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_967__RX_DCOC_RANGE_967___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_967__RX_DCOC_RES_I_967___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_967__RX_DCOC_RES_I_967___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_967__RX_DCOC_RES_Q_967___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_967__RX_DCOC_RES_Q_967___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_967___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_967___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_968 (0x005E4F20) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_968___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_968___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_968__RX_DCOC_RANGE_968___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_968__RX_DCOC_RES_I_968___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_968__RX_DCOC_RES_Q_968___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_968__RX_DCOC_RANGE_968___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_968__RX_DCOC_RANGE_968___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_968__RX_DCOC_RES_I_968___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_968__RX_DCOC_RES_I_968___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_968__RX_DCOC_RES_Q_968___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_968__RX_DCOC_RES_Q_968___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_968___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_968___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_969 (0x005E4F24) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_969___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_969___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_969__RX_DCOC_RANGE_969___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_969__RX_DCOC_RES_I_969___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_969__RX_DCOC_RES_Q_969___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_969__RX_DCOC_RANGE_969___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_969__RX_DCOC_RANGE_969___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_969__RX_DCOC_RES_I_969___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_969__RX_DCOC_RES_I_969___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_969__RX_DCOC_RES_Q_969___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_969__RX_DCOC_RES_Q_969___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_969___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_969___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_970 (0x005E4F28) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_970___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_970___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_970__RX_DCOC_RANGE_970___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_970__RX_DCOC_RES_I_970___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_970__RX_DCOC_RES_Q_970___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_970__RX_DCOC_RANGE_970___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_970__RX_DCOC_RANGE_970___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_970__RX_DCOC_RES_I_970___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_970__RX_DCOC_RES_I_970___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_970__RX_DCOC_RES_Q_970___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_970__RX_DCOC_RES_Q_970___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_970___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_970___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_971 (0x005E4F2C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_971___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_971___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_971__RX_DCOC_RANGE_971___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_971__RX_DCOC_RES_I_971___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_971__RX_DCOC_RES_Q_971___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_971__RX_DCOC_RANGE_971___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_971__RX_DCOC_RANGE_971___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_971__RX_DCOC_RES_I_971___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_971__RX_DCOC_RES_I_971___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_971__RX_DCOC_RES_Q_971___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_971__RX_DCOC_RES_Q_971___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_971___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_971___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_972 (0x005E4F30) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_972___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_972___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_972__RX_DCOC_RANGE_972___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_972__RX_DCOC_RES_I_972___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_972__RX_DCOC_RES_Q_972___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_972__RX_DCOC_RANGE_972___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_972__RX_DCOC_RANGE_972___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_972__RX_DCOC_RES_I_972___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_972__RX_DCOC_RES_I_972___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_972__RX_DCOC_RES_Q_972___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_972__RX_DCOC_RES_Q_972___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_972___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_972___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_973 (0x005E4F34) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_973___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_973___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_973__RX_DCOC_RANGE_973___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_973__RX_DCOC_RES_I_973___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_973__RX_DCOC_RES_Q_973___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_973__RX_DCOC_RANGE_973___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_973__RX_DCOC_RANGE_973___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_973__RX_DCOC_RES_I_973___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_973__RX_DCOC_RES_I_973___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_973__RX_DCOC_RES_Q_973___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_973__RX_DCOC_RES_Q_973___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_973___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_973___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_974 (0x005E4F38) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_974___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_974___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_974__RX_DCOC_RANGE_974___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_974__RX_DCOC_RES_I_974___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_974__RX_DCOC_RES_Q_974___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_974__RX_DCOC_RANGE_974___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_974__RX_DCOC_RANGE_974___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_974__RX_DCOC_RES_I_974___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_974__RX_DCOC_RES_I_974___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_974__RX_DCOC_RES_Q_974___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_974__RX_DCOC_RES_Q_974___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_974___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_974___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_975 (0x005E4F3C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_975___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_975___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_975__RX_DCOC_RANGE_975___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_975__RX_DCOC_RES_I_975___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_975__RX_DCOC_RES_Q_975___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_975__RX_DCOC_RANGE_975___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_975__RX_DCOC_RANGE_975___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_975__RX_DCOC_RES_I_975___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_975__RX_DCOC_RES_I_975___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_975__RX_DCOC_RES_Q_975___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_975__RX_DCOC_RES_Q_975___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_975___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_975___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_976 (0x005E4F40) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_976___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_976___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_976__RX_DCOC_RANGE_976___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_976__RX_DCOC_RES_I_976___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_976__RX_DCOC_RES_Q_976___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_976__RX_DCOC_RANGE_976___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_976__RX_DCOC_RANGE_976___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_976__RX_DCOC_RES_I_976___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_976__RX_DCOC_RES_I_976___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_976__RX_DCOC_RES_Q_976___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_976__RX_DCOC_RES_Q_976___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_976___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_976___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_977 (0x005E4F44) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_977___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_977___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_977__RX_DCOC_RANGE_977___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_977__RX_DCOC_RES_I_977___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_977__RX_DCOC_RES_Q_977___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_977__RX_DCOC_RANGE_977___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_977__RX_DCOC_RANGE_977___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_977__RX_DCOC_RES_I_977___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_977__RX_DCOC_RES_I_977___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_977__RX_DCOC_RES_Q_977___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_977__RX_DCOC_RES_Q_977___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_977___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_977___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_978 (0x005E4F48) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_978___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_978___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_978__RX_DCOC_RANGE_978___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_978__RX_DCOC_RES_I_978___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_978__RX_DCOC_RES_Q_978___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_978__RX_DCOC_RANGE_978___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_978__RX_DCOC_RANGE_978___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_978__RX_DCOC_RES_I_978___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_978__RX_DCOC_RES_I_978___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_978__RX_DCOC_RES_Q_978___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_978__RX_DCOC_RES_Q_978___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_978___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_978___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_979 (0x005E4F4C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_979___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_979___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_979__RX_DCOC_RANGE_979___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_979__RX_DCOC_RES_I_979___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_979__RX_DCOC_RES_Q_979___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_979__RX_DCOC_RANGE_979___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_979__RX_DCOC_RANGE_979___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_979__RX_DCOC_RES_I_979___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_979__RX_DCOC_RES_I_979___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_979__RX_DCOC_RES_Q_979___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_979__RX_DCOC_RES_Q_979___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_979___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_979___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_980 (0x005E4F50) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_980___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_980___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_980__RX_DCOC_RANGE_980___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_980__RX_DCOC_RES_I_980___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_980__RX_DCOC_RES_Q_980___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_980__RX_DCOC_RANGE_980___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_980__RX_DCOC_RANGE_980___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_980__RX_DCOC_RES_I_980___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_980__RX_DCOC_RES_I_980___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_980__RX_DCOC_RES_Q_980___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_980__RX_DCOC_RES_Q_980___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_980___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_980___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_981 (0x005E4F54) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_981___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_981___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_981__RX_DCOC_RANGE_981___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_981__RX_DCOC_RES_I_981___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_981__RX_DCOC_RES_Q_981___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_981__RX_DCOC_RANGE_981___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_981__RX_DCOC_RANGE_981___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_981__RX_DCOC_RES_I_981___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_981__RX_DCOC_RES_I_981___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_981__RX_DCOC_RES_Q_981___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_981__RX_DCOC_RES_Q_981___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_981___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_981___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_982 (0x005E4F58) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_982___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_982___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_982__RX_DCOC_RANGE_982___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_982__RX_DCOC_RES_I_982___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_982__RX_DCOC_RES_Q_982___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_982__RX_DCOC_RANGE_982___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_982__RX_DCOC_RANGE_982___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_982__RX_DCOC_RES_I_982___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_982__RX_DCOC_RES_I_982___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_982__RX_DCOC_RES_Q_982___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_982__RX_DCOC_RES_Q_982___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_982___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_982___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_983 (0x005E4F5C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_983___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_983___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_983__RX_DCOC_RANGE_983___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_983__RX_DCOC_RES_I_983___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_983__RX_DCOC_RES_Q_983___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_983__RX_DCOC_RANGE_983___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_983__RX_DCOC_RANGE_983___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_983__RX_DCOC_RES_I_983___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_983__RX_DCOC_RES_I_983___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_983__RX_DCOC_RES_Q_983___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_983__RX_DCOC_RES_Q_983___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_983___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_983___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_984 (0x005E4F60) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_984___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_984___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_984__RX_DCOC_RANGE_984___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_984__RX_DCOC_RES_I_984___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_984__RX_DCOC_RES_Q_984___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_984__RX_DCOC_RANGE_984___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_984__RX_DCOC_RANGE_984___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_984__RX_DCOC_RES_I_984___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_984__RX_DCOC_RES_I_984___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_984__RX_DCOC_RES_Q_984___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_984__RX_DCOC_RES_Q_984___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_984___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_984___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_985 (0x005E4F64) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_985___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_985___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_985__RX_DCOC_RANGE_985___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_985__RX_DCOC_RES_I_985___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_985__RX_DCOC_RES_Q_985___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_985__RX_DCOC_RANGE_985___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_985__RX_DCOC_RANGE_985___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_985__RX_DCOC_RES_I_985___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_985__RX_DCOC_RES_I_985___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_985__RX_DCOC_RES_Q_985___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_985__RX_DCOC_RES_Q_985___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_985___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_985___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_986 (0x005E4F68) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_986___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_986___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_986__RX_DCOC_RANGE_986___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_986__RX_DCOC_RES_I_986___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_986__RX_DCOC_RES_Q_986___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_986__RX_DCOC_RANGE_986___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_986__RX_DCOC_RANGE_986___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_986__RX_DCOC_RES_I_986___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_986__RX_DCOC_RES_I_986___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_986__RX_DCOC_RES_Q_986___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_986__RX_DCOC_RES_Q_986___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_986___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_986___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_987 (0x005E4F6C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_987___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_987___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_987__RX_DCOC_RANGE_987___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_987__RX_DCOC_RES_I_987___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_987__RX_DCOC_RES_Q_987___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_987__RX_DCOC_RANGE_987___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_987__RX_DCOC_RANGE_987___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_987__RX_DCOC_RES_I_987___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_987__RX_DCOC_RES_I_987___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_987__RX_DCOC_RES_Q_987___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_987__RX_DCOC_RES_Q_987___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_987___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_987___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_988 (0x005E4F70) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_988___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_988___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_988__RX_DCOC_RANGE_988___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_988__RX_DCOC_RES_I_988___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_988__RX_DCOC_RES_Q_988___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_988__RX_DCOC_RANGE_988___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_988__RX_DCOC_RANGE_988___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_988__RX_DCOC_RES_I_988___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_988__RX_DCOC_RES_I_988___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_988__RX_DCOC_RES_Q_988___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_988__RX_DCOC_RES_Q_988___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_988___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_988___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_989 (0x005E4F74) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_989___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_989___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_989__RX_DCOC_RANGE_989___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_989__RX_DCOC_RES_I_989___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_989__RX_DCOC_RES_Q_989___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_989__RX_DCOC_RANGE_989___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_989__RX_DCOC_RANGE_989___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_989__RX_DCOC_RES_I_989___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_989__RX_DCOC_RES_I_989___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_989__RX_DCOC_RES_Q_989___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_989__RX_DCOC_RES_Q_989___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_989___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_989___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_990 (0x005E4F78) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_990___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_990___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_990__RX_DCOC_RANGE_990___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_990__RX_DCOC_RES_I_990___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_990__RX_DCOC_RES_Q_990___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_990__RX_DCOC_RANGE_990___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_990__RX_DCOC_RANGE_990___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_990__RX_DCOC_RES_I_990___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_990__RX_DCOC_RES_I_990___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_990__RX_DCOC_RES_Q_990___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_990__RX_DCOC_RES_Q_990___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_990___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_990___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_991 (0x005E4F7C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_991___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_991___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_991__RX_DCOC_RANGE_991___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_991__RX_DCOC_RES_I_991___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_991__RX_DCOC_RES_Q_991___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_991__RX_DCOC_RANGE_991___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_991__RX_DCOC_RANGE_991___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_991__RX_DCOC_RES_I_991___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_991__RX_DCOC_RES_I_991___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_991__RX_DCOC_RES_Q_991___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_991__RX_DCOC_RES_Q_991___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_991___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_991___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_992 (0x005E4F80) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_992___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_992___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_992__RX_DCOC_RANGE_992___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_992__RX_DCOC_RES_I_992___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_992__RX_DCOC_RES_Q_992___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_992__RX_DCOC_RANGE_992___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_992__RX_DCOC_RANGE_992___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_992__RX_DCOC_RES_I_992___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_992__RX_DCOC_RES_I_992___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_992__RX_DCOC_RES_Q_992___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_992__RX_DCOC_RES_Q_992___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_992___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_992___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_993 (0x005E4F84) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_993___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_993___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_993__RX_DCOC_RANGE_993___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_993__RX_DCOC_RES_I_993___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_993__RX_DCOC_RES_Q_993___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_993__RX_DCOC_RANGE_993___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_993__RX_DCOC_RANGE_993___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_993__RX_DCOC_RES_I_993___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_993__RX_DCOC_RES_I_993___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_993__RX_DCOC_RES_Q_993___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_993__RX_DCOC_RES_Q_993___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_993___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_993___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_994 (0x005E4F88) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_994___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_994___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_994__RX_DCOC_RANGE_994___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_994__RX_DCOC_RES_I_994___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_994__RX_DCOC_RES_Q_994___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_994__RX_DCOC_RANGE_994___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_994__RX_DCOC_RANGE_994___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_994__RX_DCOC_RES_I_994___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_994__RX_DCOC_RES_I_994___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_994__RX_DCOC_RES_Q_994___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_994__RX_DCOC_RES_Q_994___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_994___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_994___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_995 (0x005E4F8C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_995___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_995___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_995__RX_DCOC_RANGE_995___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_995__RX_DCOC_RES_I_995___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_995__RX_DCOC_RES_Q_995___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_995__RX_DCOC_RANGE_995___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_995__RX_DCOC_RANGE_995___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_995__RX_DCOC_RES_I_995___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_995__RX_DCOC_RES_I_995___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_995__RX_DCOC_RES_Q_995___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_995__RX_DCOC_RES_Q_995___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_995___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_995___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_996 (0x005E4F90) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_996___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_996___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_996__RX_DCOC_RANGE_996___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_996__RX_DCOC_RES_I_996___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_996__RX_DCOC_RES_Q_996___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_996__RX_DCOC_RANGE_996___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_996__RX_DCOC_RANGE_996___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_996__RX_DCOC_RES_I_996___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_996__RX_DCOC_RES_I_996___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_996__RX_DCOC_RES_Q_996___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_996__RX_DCOC_RES_Q_996___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_996___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_996___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_997 (0x005E4F94) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_997___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_997___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_997__RX_DCOC_RANGE_997___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_997__RX_DCOC_RES_I_997___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_997__RX_DCOC_RES_Q_997___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_997__RX_DCOC_RANGE_997___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_997__RX_DCOC_RANGE_997___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_997__RX_DCOC_RES_I_997___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_997__RX_DCOC_RES_I_997___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_997__RX_DCOC_RES_Q_997___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_997__RX_DCOC_RES_Q_997___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_997___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_997___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_998 (0x005E4F98) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_998___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_998___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_998__RX_DCOC_RANGE_998___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_998__RX_DCOC_RES_I_998___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_998__RX_DCOC_RES_Q_998___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_998__RX_DCOC_RANGE_998___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_998__RX_DCOC_RANGE_998___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_998__RX_DCOC_RES_I_998___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_998__RX_DCOC_RES_I_998___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_998__RX_DCOC_RES_Q_998___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_998__RX_DCOC_RES_Q_998___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_998___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_998___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_999 (0x005E4F9C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_999___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_999___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_999__RX_DCOC_RANGE_999___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_999__RX_DCOC_RES_I_999___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_999__RX_DCOC_RES_Q_999___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_999__RX_DCOC_RANGE_999___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_999__RX_DCOC_RANGE_999___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_999__RX_DCOC_RES_I_999___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_999__RX_DCOC_RES_I_999___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_999__RX_DCOC_RES_Q_999___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_999__RX_DCOC_RES_Q_999___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_999___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_999___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1000 (0x005E4FA0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1000___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1000___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1000__RX_DCOC_RANGE_1000___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1000__RX_DCOC_RES_I_1000___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1000__RX_DCOC_RES_Q_1000___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1000__RX_DCOC_RANGE_1000___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1000__RX_DCOC_RANGE_1000___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1000__RX_DCOC_RES_I_1000___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1000__RX_DCOC_RES_I_1000___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1000__RX_DCOC_RES_Q_1000___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1000__RX_DCOC_RES_Q_1000___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1000___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1000___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1001 (0x005E4FA4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1001___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1001___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1001__RX_DCOC_RANGE_1001___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1001__RX_DCOC_RES_I_1001___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1001__RX_DCOC_RES_Q_1001___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1001__RX_DCOC_RANGE_1001___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1001__RX_DCOC_RANGE_1001___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1001__RX_DCOC_RES_I_1001___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1001__RX_DCOC_RES_I_1001___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1001__RX_DCOC_RES_Q_1001___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1001__RX_DCOC_RES_Q_1001___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1001___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1001___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1002 (0x005E4FA8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1002___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1002___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1002__RX_DCOC_RANGE_1002___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1002__RX_DCOC_RES_I_1002___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1002__RX_DCOC_RES_Q_1002___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1002__RX_DCOC_RANGE_1002___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1002__RX_DCOC_RANGE_1002___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1002__RX_DCOC_RES_I_1002___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1002__RX_DCOC_RES_I_1002___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1002__RX_DCOC_RES_Q_1002___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1002__RX_DCOC_RES_Q_1002___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1002___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1002___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1003 (0x005E4FAC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1003___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1003___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1003__RX_DCOC_RANGE_1003___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1003__RX_DCOC_RES_I_1003___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1003__RX_DCOC_RES_Q_1003___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1003__RX_DCOC_RANGE_1003___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1003__RX_DCOC_RANGE_1003___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1003__RX_DCOC_RES_I_1003___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1003__RX_DCOC_RES_I_1003___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1003__RX_DCOC_RES_Q_1003___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1003__RX_DCOC_RES_Q_1003___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1003___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1003___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1004 (0x005E4FB0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1004___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1004___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1004__RX_DCOC_RANGE_1004___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1004__RX_DCOC_RES_I_1004___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1004__RX_DCOC_RES_Q_1004___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1004__RX_DCOC_RANGE_1004___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1004__RX_DCOC_RANGE_1004___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1004__RX_DCOC_RES_I_1004___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1004__RX_DCOC_RES_I_1004___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1004__RX_DCOC_RES_Q_1004___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1004__RX_DCOC_RES_Q_1004___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1004___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1004___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1005 (0x005E4FB4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1005___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1005___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1005__RX_DCOC_RANGE_1005___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1005__RX_DCOC_RES_I_1005___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1005__RX_DCOC_RES_Q_1005___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1005__RX_DCOC_RANGE_1005___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1005__RX_DCOC_RANGE_1005___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1005__RX_DCOC_RES_I_1005___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1005__RX_DCOC_RES_I_1005___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1005__RX_DCOC_RES_Q_1005___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1005__RX_DCOC_RES_Q_1005___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1005___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1005___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1006 (0x005E4FB8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1006___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1006___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1006__RX_DCOC_RANGE_1006___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1006__RX_DCOC_RES_I_1006___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1006__RX_DCOC_RES_Q_1006___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1006__RX_DCOC_RANGE_1006___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1006__RX_DCOC_RANGE_1006___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1006__RX_DCOC_RES_I_1006___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1006__RX_DCOC_RES_I_1006___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1006__RX_DCOC_RES_Q_1006___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1006__RX_DCOC_RES_Q_1006___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1006___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1006___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1007 (0x005E4FBC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1007___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1007___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1007__RX_DCOC_RANGE_1007___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1007__RX_DCOC_RES_I_1007___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1007__RX_DCOC_RES_Q_1007___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1007__RX_DCOC_RANGE_1007___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1007__RX_DCOC_RANGE_1007___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1007__RX_DCOC_RES_I_1007___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1007__RX_DCOC_RES_I_1007___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1007__RX_DCOC_RES_Q_1007___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1007__RX_DCOC_RES_Q_1007___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1007___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1007___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1008 (0x005E4FC0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1008___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1008___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1008__RX_DCOC_RANGE_1008___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1008__RX_DCOC_RES_I_1008___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1008__RX_DCOC_RES_Q_1008___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1008__RX_DCOC_RANGE_1008___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1008__RX_DCOC_RANGE_1008___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1008__RX_DCOC_RES_I_1008___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1008__RX_DCOC_RES_I_1008___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1008__RX_DCOC_RES_Q_1008___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1008__RX_DCOC_RES_Q_1008___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1008___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1008___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1009 (0x005E4FC4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1009___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1009___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1009__RX_DCOC_RANGE_1009___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1009__RX_DCOC_RES_I_1009___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1009__RX_DCOC_RES_Q_1009___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1009__RX_DCOC_RANGE_1009___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1009__RX_DCOC_RANGE_1009___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1009__RX_DCOC_RES_I_1009___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1009__RX_DCOC_RES_I_1009___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1009__RX_DCOC_RES_Q_1009___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1009__RX_DCOC_RES_Q_1009___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1009___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1009___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1010 (0x005E4FC8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1010___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1010___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1010__RX_DCOC_RANGE_1010___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1010__RX_DCOC_RES_I_1010___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1010__RX_DCOC_RES_Q_1010___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1010__RX_DCOC_RANGE_1010___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1010__RX_DCOC_RANGE_1010___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1010__RX_DCOC_RES_I_1010___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1010__RX_DCOC_RES_I_1010___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1010__RX_DCOC_RES_Q_1010___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1010__RX_DCOC_RES_Q_1010___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1010___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1010___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1011 (0x005E4FCC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1011___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1011___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1011__RX_DCOC_RANGE_1011___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1011__RX_DCOC_RES_I_1011___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1011__RX_DCOC_RES_Q_1011___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1011__RX_DCOC_RANGE_1011___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1011__RX_DCOC_RANGE_1011___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1011__RX_DCOC_RES_I_1011___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1011__RX_DCOC_RES_I_1011___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1011__RX_DCOC_RES_Q_1011___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1011__RX_DCOC_RES_Q_1011___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1011___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1011___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1012 (0x005E4FD0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1012___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1012___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1012__RX_DCOC_RANGE_1012___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1012__RX_DCOC_RES_I_1012___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1012__RX_DCOC_RES_Q_1012___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1012__RX_DCOC_RANGE_1012___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1012__RX_DCOC_RANGE_1012___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1012__RX_DCOC_RES_I_1012___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1012__RX_DCOC_RES_I_1012___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1012__RX_DCOC_RES_Q_1012___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1012__RX_DCOC_RES_Q_1012___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1012___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1012___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1013 (0x005E4FD4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1013___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1013___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1013__RX_DCOC_RANGE_1013___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1013__RX_DCOC_RES_I_1013___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1013__RX_DCOC_RES_Q_1013___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1013__RX_DCOC_RANGE_1013___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1013__RX_DCOC_RANGE_1013___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1013__RX_DCOC_RES_I_1013___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1013__RX_DCOC_RES_I_1013___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1013__RX_DCOC_RES_Q_1013___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1013__RX_DCOC_RES_Q_1013___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1013___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1013___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1014 (0x005E4FD8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1014___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1014___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1014__RX_DCOC_RANGE_1014___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1014__RX_DCOC_RES_I_1014___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1014__RX_DCOC_RES_Q_1014___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1014__RX_DCOC_RANGE_1014___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1014__RX_DCOC_RANGE_1014___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1014__RX_DCOC_RES_I_1014___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1014__RX_DCOC_RES_I_1014___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1014__RX_DCOC_RES_Q_1014___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1014__RX_DCOC_RES_Q_1014___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1014___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1014___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1015 (0x005E4FDC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1015___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1015___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1015__RX_DCOC_RANGE_1015___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1015__RX_DCOC_RES_I_1015___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1015__RX_DCOC_RES_Q_1015___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1015__RX_DCOC_RANGE_1015___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1015__RX_DCOC_RANGE_1015___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1015__RX_DCOC_RES_I_1015___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1015__RX_DCOC_RES_I_1015___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1015__RX_DCOC_RES_Q_1015___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1015__RX_DCOC_RES_Q_1015___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1015___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1015___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1016 (0x005E4FE0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1016___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1016___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1016__RX_DCOC_RANGE_1016___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1016__RX_DCOC_RES_I_1016___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1016__RX_DCOC_RES_Q_1016___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1016__RX_DCOC_RANGE_1016___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1016__RX_DCOC_RANGE_1016___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1016__RX_DCOC_RES_I_1016___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1016__RX_DCOC_RES_I_1016___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1016__RX_DCOC_RES_Q_1016___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1016__RX_DCOC_RES_Q_1016___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1016___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1016___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1017 (0x005E4FE4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1017___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1017___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1017__RX_DCOC_RANGE_1017___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1017__RX_DCOC_RES_I_1017___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1017__RX_DCOC_RES_Q_1017___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1017__RX_DCOC_RANGE_1017___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1017__RX_DCOC_RANGE_1017___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1017__RX_DCOC_RES_I_1017___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1017__RX_DCOC_RES_I_1017___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1017__RX_DCOC_RES_Q_1017___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1017__RX_DCOC_RES_Q_1017___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1017___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1017___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1018 (0x005E4FE8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1018___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1018___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1018__RX_DCOC_RANGE_1018___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1018__RX_DCOC_RES_I_1018___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1018__RX_DCOC_RES_Q_1018___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1018__RX_DCOC_RANGE_1018___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1018__RX_DCOC_RANGE_1018___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1018__RX_DCOC_RES_I_1018___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1018__RX_DCOC_RES_I_1018___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1018__RX_DCOC_RES_Q_1018___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1018__RX_DCOC_RES_Q_1018___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1018___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1018___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1019 (0x005E4FEC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1019___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1019___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1019__RX_DCOC_RANGE_1019___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1019__RX_DCOC_RES_I_1019___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1019__RX_DCOC_RES_Q_1019___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1019__RX_DCOC_RANGE_1019___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1019__RX_DCOC_RANGE_1019___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1019__RX_DCOC_RES_I_1019___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1019__RX_DCOC_RES_I_1019___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1019__RX_DCOC_RES_Q_1019___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1019__RX_DCOC_RES_Q_1019___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1019___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1019___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1020 (0x005E4FF0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1020___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1020___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1020__RX_DCOC_RANGE_1020___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1020__RX_DCOC_RES_I_1020___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1020__RX_DCOC_RES_Q_1020___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1020__RX_DCOC_RANGE_1020___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1020__RX_DCOC_RANGE_1020___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1020__RX_DCOC_RES_I_1020___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1020__RX_DCOC_RES_I_1020___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1020__RX_DCOC_RES_Q_1020___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1020__RX_DCOC_RES_Q_1020___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1020___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1020___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1021 (0x005E4FF4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1021___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1021___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1021__RX_DCOC_RANGE_1021___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1021__RX_DCOC_RES_I_1021___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1021__RX_DCOC_RES_Q_1021___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1021__RX_DCOC_RANGE_1021___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1021__RX_DCOC_RANGE_1021___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1021__RX_DCOC_RES_I_1021___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1021__RX_DCOC_RES_I_1021___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1021__RX_DCOC_RES_Q_1021___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1021__RX_DCOC_RES_Q_1021___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1021___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1021___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1022 (0x005E4FF8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1022___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1022___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1022__RX_DCOC_RANGE_1022___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1022__RX_DCOC_RES_I_1022___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1022__RX_DCOC_RES_Q_1022___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1022__RX_DCOC_RANGE_1022___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1022__RX_DCOC_RANGE_1022___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1022__RX_DCOC_RES_I_1022___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1022__RX_DCOC_RES_I_1022___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1022__RX_DCOC_RES_Q_1022___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1022__RX_DCOC_RES_Q_1022___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1022___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1022___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1023 (0x005E4FFC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1023___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1023___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1023__RX_DCOC_RANGE_1023___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1023__RX_DCOC_RES_I_1023___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1023__RX_DCOC_RES_Q_1023___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1023__RX_DCOC_RANGE_1023___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1023__RX_DCOC_RANGE_1023___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1023__RX_DCOC_RES_I_1023___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1023__RX_DCOC_RES_I_1023___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1023__RX_DCOC_RES_Q_1023___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1023__RX_DCOC_RES_Q_1023___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1023___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXDCOC_1023___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0 (0x005E5000) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__XLNA_GAIN_ODD_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__LNA_GAIN_ODD_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__GM_GAIN_ODD_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__TIA_GAIN_ODD_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__SLM_XLNA_ODD_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__BQ_GAIN_ODD_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__XLNA_GAIN_EVEN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__LNA_GAIN_EVEN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__GM_GAIN_EVEN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__TIA_GAIN_EVEN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__SLM_XLNA_EVEN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__BQ_GAIN_EVEN_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__XLNA_GAIN_ODD_0___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__XLNA_GAIN_ODD_0___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__LNA_GAIN_ODD_0___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__LNA_GAIN_ODD_0___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__GM_GAIN_ODD_0___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__GM_GAIN_ODD_0___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__TIA_GAIN_ODD_0___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__TIA_GAIN_ODD_0___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__SLM_XLNA_ODD_0___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__SLM_XLNA_ODD_0___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__BQ_GAIN_ODD_0___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__BQ_GAIN_ODD_0___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__XLNA_GAIN_EVEN_0___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__XLNA_GAIN_EVEN_0___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__LNA_GAIN_EVEN_0___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__LNA_GAIN_EVEN_0___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__GM_GAIN_EVEN_0___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__GM_GAIN_EVEN_0___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__TIA_GAIN_EVEN_0___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__TIA_GAIN_EVEN_0___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__SLM_XLNA_EVEN_0___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__SLM_XLNA_EVEN_0___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__BQ_GAIN_EVEN_0___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0__BQ_GAIN_EVEN_0___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1 (0x005E5004) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__XLNA_GAIN_ODD_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__LNA_GAIN_ODD_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__GM_GAIN_ODD_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__TIA_GAIN_ODD_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__SLM_XLNA_ODD_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__BQ_GAIN_ODD_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__XLNA_GAIN_EVEN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__LNA_GAIN_EVEN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__GM_GAIN_EVEN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__TIA_GAIN_EVEN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__SLM_XLNA_EVEN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__BQ_GAIN_EVEN_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__XLNA_GAIN_ODD_1___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__XLNA_GAIN_ODD_1___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__LNA_GAIN_ODD_1___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__LNA_GAIN_ODD_1___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__GM_GAIN_ODD_1___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__GM_GAIN_ODD_1___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__TIA_GAIN_ODD_1___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__TIA_GAIN_ODD_1___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__SLM_XLNA_ODD_1___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__SLM_XLNA_ODD_1___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__BQ_GAIN_ODD_1___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__BQ_GAIN_ODD_1___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__XLNA_GAIN_EVEN_1___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__XLNA_GAIN_EVEN_1___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__LNA_GAIN_EVEN_1___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__LNA_GAIN_EVEN_1___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__GM_GAIN_EVEN_1___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__GM_GAIN_EVEN_1___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__TIA_GAIN_EVEN_1___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__TIA_GAIN_EVEN_1___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__SLM_XLNA_EVEN_1___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__SLM_XLNA_EVEN_1___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__BQ_GAIN_EVEN_1___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1__BQ_GAIN_EVEN_1___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2 (0x005E5008) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__XLNA_GAIN_ODD_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__LNA_GAIN_ODD_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__GM_GAIN_ODD_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__TIA_GAIN_ODD_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__SLM_XLNA_ODD_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__BQ_GAIN_ODD_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__XLNA_GAIN_EVEN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__LNA_GAIN_EVEN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__GM_GAIN_EVEN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__TIA_GAIN_EVEN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__SLM_XLNA_EVEN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__BQ_GAIN_EVEN_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__XLNA_GAIN_ODD_2___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__XLNA_GAIN_ODD_2___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__LNA_GAIN_ODD_2___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__LNA_GAIN_ODD_2___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__GM_GAIN_ODD_2___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__GM_GAIN_ODD_2___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__TIA_GAIN_ODD_2___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__TIA_GAIN_ODD_2___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__SLM_XLNA_ODD_2___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__SLM_XLNA_ODD_2___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__BQ_GAIN_ODD_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__BQ_GAIN_ODD_2___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__XLNA_GAIN_EVEN_2___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__XLNA_GAIN_EVEN_2___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__LNA_GAIN_EVEN_2___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__LNA_GAIN_EVEN_2___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__GM_GAIN_EVEN_2___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__GM_GAIN_EVEN_2___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__TIA_GAIN_EVEN_2___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__TIA_GAIN_EVEN_2___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__SLM_XLNA_EVEN_2___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__SLM_XLNA_EVEN_2___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__BQ_GAIN_EVEN_2___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2__BQ_GAIN_EVEN_2___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_2___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3 (0x005E500C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__XLNA_GAIN_ODD_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__LNA_GAIN_ODD_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__GM_GAIN_ODD_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__TIA_GAIN_ODD_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__SLM_XLNA_ODD_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__BQ_GAIN_ODD_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__XLNA_GAIN_EVEN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__LNA_GAIN_EVEN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__GM_GAIN_EVEN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__TIA_GAIN_EVEN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__SLM_XLNA_EVEN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__BQ_GAIN_EVEN_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__XLNA_GAIN_ODD_3___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__XLNA_GAIN_ODD_3___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__LNA_GAIN_ODD_3___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__LNA_GAIN_ODD_3___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__GM_GAIN_ODD_3___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__GM_GAIN_ODD_3___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__TIA_GAIN_ODD_3___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__TIA_GAIN_ODD_3___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__SLM_XLNA_ODD_3___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__SLM_XLNA_ODD_3___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__BQ_GAIN_ODD_3___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__BQ_GAIN_ODD_3___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__XLNA_GAIN_EVEN_3___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__XLNA_GAIN_EVEN_3___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__LNA_GAIN_EVEN_3___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__LNA_GAIN_EVEN_3___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__GM_GAIN_EVEN_3___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__GM_GAIN_EVEN_3___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__TIA_GAIN_EVEN_3___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__TIA_GAIN_EVEN_3___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__SLM_XLNA_EVEN_3___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__SLM_XLNA_EVEN_3___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__BQ_GAIN_EVEN_3___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3__BQ_GAIN_EVEN_3___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_3___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4 (0x005E5010) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__XLNA_GAIN_ODD_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__LNA_GAIN_ODD_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__GM_GAIN_ODD_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__TIA_GAIN_ODD_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__SLM_XLNA_ODD_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__BQ_GAIN_ODD_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__XLNA_GAIN_EVEN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__LNA_GAIN_EVEN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__GM_GAIN_EVEN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__TIA_GAIN_EVEN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__SLM_XLNA_EVEN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__BQ_GAIN_EVEN_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__XLNA_GAIN_ODD_4___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__XLNA_GAIN_ODD_4___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__LNA_GAIN_ODD_4___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__LNA_GAIN_ODD_4___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__GM_GAIN_ODD_4___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__GM_GAIN_ODD_4___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__TIA_GAIN_ODD_4___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__TIA_GAIN_ODD_4___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__SLM_XLNA_ODD_4___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__SLM_XLNA_ODD_4___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__BQ_GAIN_ODD_4___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__BQ_GAIN_ODD_4___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__XLNA_GAIN_EVEN_4___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__XLNA_GAIN_EVEN_4___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__LNA_GAIN_EVEN_4___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__LNA_GAIN_EVEN_4___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__GM_GAIN_EVEN_4___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__GM_GAIN_EVEN_4___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__TIA_GAIN_EVEN_4___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__TIA_GAIN_EVEN_4___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__SLM_XLNA_EVEN_4___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__SLM_XLNA_EVEN_4___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__BQ_GAIN_EVEN_4___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4__BQ_GAIN_EVEN_4___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_4___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5 (0x005E5014) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__XLNA_GAIN_ODD_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__LNA_GAIN_ODD_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__GM_GAIN_ODD_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__TIA_GAIN_ODD_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__SLM_XLNA_ODD_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__BQ_GAIN_ODD_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__XLNA_GAIN_EVEN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__LNA_GAIN_EVEN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__GM_GAIN_EVEN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__TIA_GAIN_EVEN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__SLM_XLNA_EVEN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__BQ_GAIN_EVEN_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__XLNA_GAIN_ODD_5___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__XLNA_GAIN_ODD_5___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__LNA_GAIN_ODD_5___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__LNA_GAIN_ODD_5___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__GM_GAIN_ODD_5___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__GM_GAIN_ODD_5___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__TIA_GAIN_ODD_5___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__TIA_GAIN_ODD_5___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__SLM_XLNA_ODD_5___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__SLM_XLNA_ODD_5___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__BQ_GAIN_ODD_5___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__BQ_GAIN_ODD_5___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__XLNA_GAIN_EVEN_5___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__XLNA_GAIN_EVEN_5___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__LNA_GAIN_EVEN_5___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__LNA_GAIN_EVEN_5___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__GM_GAIN_EVEN_5___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__GM_GAIN_EVEN_5___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__TIA_GAIN_EVEN_5___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__TIA_GAIN_EVEN_5___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__SLM_XLNA_EVEN_5___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__SLM_XLNA_EVEN_5___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__BQ_GAIN_EVEN_5___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5__BQ_GAIN_EVEN_5___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_5___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6 (0x005E5018) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__XLNA_GAIN_ODD_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__LNA_GAIN_ODD_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__GM_GAIN_ODD_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__TIA_GAIN_ODD_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__SLM_XLNA_ODD_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__BQ_GAIN_ODD_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__XLNA_GAIN_EVEN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__LNA_GAIN_EVEN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__GM_GAIN_EVEN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__TIA_GAIN_EVEN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__SLM_XLNA_EVEN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__BQ_GAIN_EVEN_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__XLNA_GAIN_ODD_6___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__XLNA_GAIN_ODD_6___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__LNA_GAIN_ODD_6___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__LNA_GAIN_ODD_6___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__GM_GAIN_ODD_6___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__GM_GAIN_ODD_6___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__TIA_GAIN_ODD_6___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__TIA_GAIN_ODD_6___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__SLM_XLNA_ODD_6___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__SLM_XLNA_ODD_6___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__BQ_GAIN_ODD_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__BQ_GAIN_ODD_6___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__XLNA_GAIN_EVEN_6___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__XLNA_GAIN_EVEN_6___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__LNA_GAIN_EVEN_6___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__LNA_GAIN_EVEN_6___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__GM_GAIN_EVEN_6___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__GM_GAIN_EVEN_6___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__TIA_GAIN_EVEN_6___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__TIA_GAIN_EVEN_6___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__SLM_XLNA_EVEN_6___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__SLM_XLNA_EVEN_6___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__BQ_GAIN_EVEN_6___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6__BQ_GAIN_EVEN_6___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_6___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7 (0x005E501C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__XLNA_GAIN_ODD_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__LNA_GAIN_ODD_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__GM_GAIN_ODD_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__TIA_GAIN_ODD_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__SLM_XLNA_ODD_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__BQ_GAIN_ODD_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__XLNA_GAIN_EVEN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__LNA_GAIN_EVEN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__GM_GAIN_EVEN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__TIA_GAIN_EVEN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__SLM_XLNA_EVEN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__BQ_GAIN_EVEN_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__XLNA_GAIN_ODD_7___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__XLNA_GAIN_ODD_7___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__LNA_GAIN_ODD_7___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__LNA_GAIN_ODD_7___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__GM_GAIN_ODD_7___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__GM_GAIN_ODD_7___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__TIA_GAIN_ODD_7___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__TIA_GAIN_ODD_7___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__SLM_XLNA_ODD_7___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__SLM_XLNA_ODD_7___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__BQ_GAIN_ODD_7___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__BQ_GAIN_ODD_7___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__XLNA_GAIN_EVEN_7___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__XLNA_GAIN_EVEN_7___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__LNA_GAIN_EVEN_7___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__LNA_GAIN_EVEN_7___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__GM_GAIN_EVEN_7___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__GM_GAIN_EVEN_7___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__TIA_GAIN_EVEN_7___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__TIA_GAIN_EVEN_7___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__SLM_XLNA_EVEN_7___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__SLM_XLNA_EVEN_7___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__BQ_GAIN_EVEN_7___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7__BQ_GAIN_EVEN_7___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_7___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8 (0x005E5020) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__XLNA_GAIN_ODD_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__LNA_GAIN_ODD_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__GM_GAIN_ODD_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__TIA_GAIN_ODD_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__SLM_XLNA_ODD_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__BQ_GAIN_ODD_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__XLNA_GAIN_EVEN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__LNA_GAIN_EVEN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__GM_GAIN_EVEN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__TIA_GAIN_EVEN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__SLM_XLNA_EVEN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__BQ_GAIN_EVEN_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__XLNA_GAIN_ODD_8___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__XLNA_GAIN_ODD_8___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__LNA_GAIN_ODD_8___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__LNA_GAIN_ODD_8___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__GM_GAIN_ODD_8___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__GM_GAIN_ODD_8___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__TIA_GAIN_ODD_8___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__TIA_GAIN_ODD_8___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__SLM_XLNA_ODD_8___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__SLM_XLNA_ODD_8___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__BQ_GAIN_ODD_8___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__BQ_GAIN_ODD_8___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__XLNA_GAIN_EVEN_8___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__XLNA_GAIN_EVEN_8___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__LNA_GAIN_EVEN_8___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__LNA_GAIN_EVEN_8___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__GM_GAIN_EVEN_8___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__GM_GAIN_EVEN_8___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__TIA_GAIN_EVEN_8___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__TIA_GAIN_EVEN_8___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__SLM_XLNA_EVEN_8___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__SLM_XLNA_EVEN_8___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__BQ_GAIN_EVEN_8___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8__BQ_GAIN_EVEN_8___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_8___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9 (0x005E5024) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__XLNA_GAIN_ODD_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__LNA_GAIN_ODD_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__GM_GAIN_ODD_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__TIA_GAIN_ODD_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__SLM_XLNA_ODD_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__BQ_GAIN_ODD_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__XLNA_GAIN_EVEN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__LNA_GAIN_EVEN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__GM_GAIN_EVEN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__TIA_GAIN_EVEN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__SLM_XLNA_EVEN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__BQ_GAIN_EVEN_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__XLNA_GAIN_ODD_9___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__XLNA_GAIN_ODD_9___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__LNA_GAIN_ODD_9___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__LNA_GAIN_ODD_9___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__GM_GAIN_ODD_9___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__GM_GAIN_ODD_9___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__TIA_GAIN_ODD_9___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__TIA_GAIN_ODD_9___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__SLM_XLNA_ODD_9___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__SLM_XLNA_ODD_9___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__BQ_GAIN_ODD_9___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__BQ_GAIN_ODD_9___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__XLNA_GAIN_EVEN_9___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__XLNA_GAIN_EVEN_9___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__LNA_GAIN_EVEN_9___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__LNA_GAIN_EVEN_9___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__GM_GAIN_EVEN_9___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__GM_GAIN_EVEN_9___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__TIA_GAIN_EVEN_9___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__TIA_GAIN_EVEN_9___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__SLM_XLNA_EVEN_9___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__SLM_XLNA_EVEN_9___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__BQ_GAIN_EVEN_9___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9__BQ_GAIN_EVEN_9___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_9___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10 (0x005E5028) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__XLNA_GAIN_ODD_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__LNA_GAIN_ODD_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__GM_GAIN_ODD_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__TIA_GAIN_ODD_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__SLM_XLNA_ODD_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__BQ_GAIN_ODD_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__XLNA_GAIN_EVEN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__LNA_GAIN_EVEN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__GM_GAIN_EVEN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__TIA_GAIN_EVEN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__SLM_XLNA_EVEN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__BQ_GAIN_EVEN_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__XLNA_GAIN_ODD_10___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__XLNA_GAIN_ODD_10___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__LNA_GAIN_ODD_10___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__LNA_GAIN_ODD_10___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__GM_GAIN_ODD_10___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__GM_GAIN_ODD_10___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__TIA_GAIN_ODD_10___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__TIA_GAIN_ODD_10___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__SLM_XLNA_ODD_10___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__SLM_XLNA_ODD_10___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__BQ_GAIN_ODD_10___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__BQ_GAIN_ODD_10___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__XLNA_GAIN_EVEN_10___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__XLNA_GAIN_EVEN_10___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__LNA_GAIN_EVEN_10___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__LNA_GAIN_EVEN_10___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__GM_GAIN_EVEN_10___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__GM_GAIN_EVEN_10___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__TIA_GAIN_EVEN_10___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__TIA_GAIN_EVEN_10___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__SLM_XLNA_EVEN_10___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__SLM_XLNA_EVEN_10___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__BQ_GAIN_EVEN_10___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10__BQ_GAIN_EVEN_10___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_10___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11 (0x005E502C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__XLNA_GAIN_ODD_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__LNA_GAIN_ODD_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__GM_GAIN_ODD_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__TIA_GAIN_ODD_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__SLM_XLNA_ODD_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__BQ_GAIN_ODD_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__XLNA_GAIN_EVEN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__LNA_GAIN_EVEN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__GM_GAIN_EVEN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__TIA_GAIN_EVEN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__SLM_XLNA_EVEN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__BQ_GAIN_EVEN_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__XLNA_GAIN_ODD_11___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__XLNA_GAIN_ODD_11___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__LNA_GAIN_ODD_11___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__LNA_GAIN_ODD_11___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__GM_GAIN_ODD_11___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__GM_GAIN_ODD_11___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__TIA_GAIN_ODD_11___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__TIA_GAIN_ODD_11___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__SLM_XLNA_ODD_11___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__SLM_XLNA_ODD_11___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__BQ_GAIN_ODD_11___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__BQ_GAIN_ODD_11___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__XLNA_GAIN_EVEN_11___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__XLNA_GAIN_EVEN_11___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__LNA_GAIN_EVEN_11___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__LNA_GAIN_EVEN_11___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__GM_GAIN_EVEN_11___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__GM_GAIN_EVEN_11___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__TIA_GAIN_EVEN_11___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__TIA_GAIN_EVEN_11___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__SLM_XLNA_EVEN_11___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__SLM_XLNA_EVEN_11___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__BQ_GAIN_EVEN_11___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11__BQ_GAIN_EVEN_11___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_11___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12 (0x005E5030) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__XLNA_GAIN_ODD_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__LNA_GAIN_ODD_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__GM_GAIN_ODD_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__TIA_GAIN_ODD_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__SLM_XLNA_ODD_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__BQ_GAIN_ODD_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__XLNA_GAIN_EVEN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__LNA_GAIN_EVEN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__GM_GAIN_EVEN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__TIA_GAIN_EVEN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__SLM_XLNA_EVEN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__BQ_GAIN_EVEN_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__XLNA_GAIN_ODD_12___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__XLNA_GAIN_ODD_12___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__LNA_GAIN_ODD_12___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__LNA_GAIN_ODD_12___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__GM_GAIN_ODD_12___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__GM_GAIN_ODD_12___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__TIA_GAIN_ODD_12___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__TIA_GAIN_ODD_12___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__SLM_XLNA_ODD_12___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__SLM_XLNA_ODD_12___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__BQ_GAIN_ODD_12___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__BQ_GAIN_ODD_12___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__XLNA_GAIN_EVEN_12___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__XLNA_GAIN_EVEN_12___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__LNA_GAIN_EVEN_12___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__LNA_GAIN_EVEN_12___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__GM_GAIN_EVEN_12___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__GM_GAIN_EVEN_12___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__TIA_GAIN_EVEN_12___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__TIA_GAIN_EVEN_12___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__SLM_XLNA_EVEN_12___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__SLM_XLNA_EVEN_12___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__BQ_GAIN_EVEN_12___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12__BQ_GAIN_EVEN_12___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_12___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13 (0x005E5034) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__XLNA_GAIN_ODD_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__LNA_GAIN_ODD_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__GM_GAIN_ODD_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__TIA_GAIN_ODD_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__SLM_XLNA_ODD_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__BQ_GAIN_ODD_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__XLNA_GAIN_EVEN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__LNA_GAIN_EVEN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__GM_GAIN_EVEN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__TIA_GAIN_EVEN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__SLM_XLNA_EVEN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__BQ_GAIN_EVEN_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__XLNA_GAIN_ODD_13___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__XLNA_GAIN_ODD_13___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__LNA_GAIN_ODD_13___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__LNA_GAIN_ODD_13___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__GM_GAIN_ODD_13___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__GM_GAIN_ODD_13___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__TIA_GAIN_ODD_13___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__TIA_GAIN_ODD_13___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__SLM_XLNA_ODD_13___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__SLM_XLNA_ODD_13___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__BQ_GAIN_ODD_13___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__BQ_GAIN_ODD_13___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__XLNA_GAIN_EVEN_13___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__XLNA_GAIN_EVEN_13___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__LNA_GAIN_EVEN_13___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__LNA_GAIN_EVEN_13___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__GM_GAIN_EVEN_13___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__GM_GAIN_EVEN_13___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__TIA_GAIN_EVEN_13___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__TIA_GAIN_EVEN_13___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__SLM_XLNA_EVEN_13___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__SLM_XLNA_EVEN_13___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__BQ_GAIN_EVEN_13___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13__BQ_GAIN_EVEN_13___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_13___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14 (0x005E5038) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__XLNA_GAIN_ODD_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__LNA_GAIN_ODD_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__GM_GAIN_ODD_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__TIA_GAIN_ODD_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__SLM_XLNA_ODD_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__BQ_GAIN_ODD_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__XLNA_GAIN_EVEN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__LNA_GAIN_EVEN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__GM_GAIN_EVEN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__TIA_GAIN_EVEN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__SLM_XLNA_EVEN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__BQ_GAIN_EVEN_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__XLNA_GAIN_ODD_14___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__XLNA_GAIN_ODD_14___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__LNA_GAIN_ODD_14___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__LNA_GAIN_ODD_14___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__GM_GAIN_ODD_14___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__GM_GAIN_ODD_14___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__TIA_GAIN_ODD_14___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__TIA_GAIN_ODD_14___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__SLM_XLNA_ODD_14___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__SLM_XLNA_ODD_14___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__BQ_GAIN_ODD_14___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__BQ_GAIN_ODD_14___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__XLNA_GAIN_EVEN_14___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__XLNA_GAIN_EVEN_14___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__LNA_GAIN_EVEN_14___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__LNA_GAIN_EVEN_14___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__GM_GAIN_EVEN_14___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__GM_GAIN_EVEN_14___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__TIA_GAIN_EVEN_14___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__TIA_GAIN_EVEN_14___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__SLM_XLNA_EVEN_14___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__SLM_XLNA_EVEN_14___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__BQ_GAIN_EVEN_14___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14__BQ_GAIN_EVEN_14___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_14___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15 (0x005E503C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__XLNA_GAIN_ODD_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__LNA_GAIN_ODD_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__GM_GAIN_ODD_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__TIA_GAIN_ODD_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__SLM_XLNA_ODD_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__BQ_GAIN_ODD_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__XLNA_GAIN_EVEN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__LNA_GAIN_EVEN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__GM_GAIN_EVEN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__TIA_GAIN_EVEN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__SLM_XLNA_EVEN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__BQ_GAIN_EVEN_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__XLNA_GAIN_ODD_15___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__XLNA_GAIN_ODD_15___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__LNA_GAIN_ODD_15___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__LNA_GAIN_ODD_15___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__GM_GAIN_ODD_15___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__GM_GAIN_ODD_15___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__TIA_GAIN_ODD_15___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__TIA_GAIN_ODD_15___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__SLM_XLNA_ODD_15___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__SLM_XLNA_ODD_15___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__BQ_GAIN_ODD_15___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__BQ_GAIN_ODD_15___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__XLNA_GAIN_EVEN_15___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__XLNA_GAIN_EVEN_15___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__LNA_GAIN_EVEN_15___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__LNA_GAIN_EVEN_15___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__GM_GAIN_EVEN_15___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__GM_GAIN_EVEN_15___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__TIA_GAIN_EVEN_15___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__TIA_GAIN_EVEN_15___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__SLM_XLNA_EVEN_15___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__SLM_XLNA_EVEN_15___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__BQ_GAIN_EVEN_15___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15__BQ_GAIN_EVEN_15___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_15___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16 (0x005E5040) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__XLNA_GAIN_ODD_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__LNA_GAIN_ODD_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__GM_GAIN_ODD_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__TIA_GAIN_ODD_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__SLM_XLNA_ODD_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__BQ_GAIN_ODD_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__XLNA_GAIN_EVEN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__LNA_GAIN_EVEN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__GM_GAIN_EVEN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__TIA_GAIN_EVEN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__SLM_XLNA_EVEN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__BQ_GAIN_EVEN_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__XLNA_GAIN_ODD_16___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__XLNA_GAIN_ODD_16___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__LNA_GAIN_ODD_16___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__LNA_GAIN_ODD_16___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__GM_GAIN_ODD_16___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__GM_GAIN_ODD_16___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__TIA_GAIN_ODD_16___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__TIA_GAIN_ODD_16___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__SLM_XLNA_ODD_16___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__SLM_XLNA_ODD_16___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__BQ_GAIN_ODD_16___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__BQ_GAIN_ODD_16___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__XLNA_GAIN_EVEN_16___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__XLNA_GAIN_EVEN_16___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__LNA_GAIN_EVEN_16___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__LNA_GAIN_EVEN_16___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__GM_GAIN_EVEN_16___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__GM_GAIN_EVEN_16___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__TIA_GAIN_EVEN_16___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__TIA_GAIN_EVEN_16___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__SLM_XLNA_EVEN_16___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__SLM_XLNA_EVEN_16___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__BQ_GAIN_EVEN_16___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16__BQ_GAIN_EVEN_16___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_16___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17 (0x005E5044) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__XLNA_GAIN_ODD_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__LNA_GAIN_ODD_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__GM_GAIN_ODD_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__TIA_GAIN_ODD_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__SLM_XLNA_ODD_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__BQ_GAIN_ODD_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__XLNA_GAIN_EVEN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__LNA_GAIN_EVEN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__GM_GAIN_EVEN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__TIA_GAIN_EVEN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__SLM_XLNA_EVEN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__BQ_GAIN_EVEN_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__XLNA_GAIN_ODD_17___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__XLNA_GAIN_ODD_17___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__LNA_GAIN_ODD_17___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__LNA_GAIN_ODD_17___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__GM_GAIN_ODD_17___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__GM_GAIN_ODD_17___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__TIA_GAIN_ODD_17___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__TIA_GAIN_ODD_17___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__SLM_XLNA_ODD_17___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__SLM_XLNA_ODD_17___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__BQ_GAIN_ODD_17___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__BQ_GAIN_ODD_17___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__XLNA_GAIN_EVEN_17___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__XLNA_GAIN_EVEN_17___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__LNA_GAIN_EVEN_17___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__LNA_GAIN_EVEN_17___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__GM_GAIN_EVEN_17___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__GM_GAIN_EVEN_17___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__TIA_GAIN_EVEN_17___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__TIA_GAIN_EVEN_17___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__SLM_XLNA_EVEN_17___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__SLM_XLNA_EVEN_17___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__BQ_GAIN_EVEN_17___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17__BQ_GAIN_EVEN_17___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_17___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18 (0x005E5048) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__XLNA_GAIN_ODD_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__LNA_GAIN_ODD_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__GM_GAIN_ODD_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__TIA_GAIN_ODD_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__SLM_XLNA_ODD_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__BQ_GAIN_ODD_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__XLNA_GAIN_EVEN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__LNA_GAIN_EVEN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__GM_GAIN_EVEN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__TIA_GAIN_EVEN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__SLM_XLNA_EVEN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__BQ_GAIN_EVEN_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__XLNA_GAIN_ODD_18___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__XLNA_GAIN_ODD_18___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__LNA_GAIN_ODD_18___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__LNA_GAIN_ODD_18___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__GM_GAIN_ODD_18___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__GM_GAIN_ODD_18___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__TIA_GAIN_ODD_18___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__TIA_GAIN_ODD_18___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__SLM_XLNA_ODD_18___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__SLM_XLNA_ODD_18___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__BQ_GAIN_ODD_18___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__BQ_GAIN_ODD_18___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__XLNA_GAIN_EVEN_18___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__XLNA_GAIN_EVEN_18___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__LNA_GAIN_EVEN_18___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__LNA_GAIN_EVEN_18___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__GM_GAIN_EVEN_18___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__GM_GAIN_EVEN_18___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__TIA_GAIN_EVEN_18___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__TIA_GAIN_EVEN_18___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__SLM_XLNA_EVEN_18___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__SLM_XLNA_EVEN_18___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__BQ_GAIN_EVEN_18___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18__BQ_GAIN_EVEN_18___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_18___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19 (0x005E504C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__XLNA_GAIN_ODD_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__LNA_GAIN_ODD_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__GM_GAIN_ODD_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__TIA_GAIN_ODD_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__SLM_XLNA_ODD_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__BQ_GAIN_ODD_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__XLNA_GAIN_EVEN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__LNA_GAIN_EVEN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__GM_GAIN_EVEN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__TIA_GAIN_EVEN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__SLM_XLNA_EVEN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__BQ_GAIN_EVEN_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__XLNA_GAIN_ODD_19___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__XLNA_GAIN_ODD_19___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__LNA_GAIN_ODD_19___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__LNA_GAIN_ODD_19___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__GM_GAIN_ODD_19___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__GM_GAIN_ODD_19___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__TIA_GAIN_ODD_19___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__TIA_GAIN_ODD_19___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__SLM_XLNA_ODD_19___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__SLM_XLNA_ODD_19___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__BQ_GAIN_ODD_19___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__BQ_GAIN_ODD_19___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__XLNA_GAIN_EVEN_19___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__XLNA_GAIN_EVEN_19___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__LNA_GAIN_EVEN_19___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__LNA_GAIN_EVEN_19___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__GM_GAIN_EVEN_19___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__GM_GAIN_EVEN_19___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__TIA_GAIN_EVEN_19___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__TIA_GAIN_EVEN_19___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__SLM_XLNA_EVEN_19___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__SLM_XLNA_EVEN_19___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__BQ_GAIN_EVEN_19___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19__BQ_GAIN_EVEN_19___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_19___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20 (0x005E5050) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__XLNA_GAIN_ODD_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__LNA_GAIN_ODD_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__GM_GAIN_ODD_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__TIA_GAIN_ODD_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__SLM_XLNA_ODD_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__BQ_GAIN_ODD_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__XLNA_GAIN_EVEN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__LNA_GAIN_EVEN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__GM_GAIN_EVEN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__TIA_GAIN_EVEN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__SLM_XLNA_EVEN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__BQ_GAIN_EVEN_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__XLNA_GAIN_ODD_20___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__XLNA_GAIN_ODD_20___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__LNA_GAIN_ODD_20___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__LNA_GAIN_ODD_20___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__GM_GAIN_ODD_20___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__GM_GAIN_ODD_20___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__TIA_GAIN_ODD_20___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__TIA_GAIN_ODD_20___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__SLM_XLNA_ODD_20___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__SLM_XLNA_ODD_20___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__BQ_GAIN_ODD_20___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__BQ_GAIN_ODD_20___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__XLNA_GAIN_EVEN_20___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__XLNA_GAIN_EVEN_20___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__LNA_GAIN_EVEN_20___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__LNA_GAIN_EVEN_20___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__GM_GAIN_EVEN_20___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__GM_GAIN_EVEN_20___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__TIA_GAIN_EVEN_20___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__TIA_GAIN_EVEN_20___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__SLM_XLNA_EVEN_20___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__SLM_XLNA_EVEN_20___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__BQ_GAIN_EVEN_20___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20__BQ_GAIN_EVEN_20___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_20___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21 (0x005E5054) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__XLNA_GAIN_ODD_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__LNA_GAIN_ODD_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__GM_GAIN_ODD_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__TIA_GAIN_ODD_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__SLM_XLNA_ODD_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__BQ_GAIN_ODD_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__XLNA_GAIN_EVEN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__LNA_GAIN_EVEN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__GM_GAIN_EVEN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__TIA_GAIN_EVEN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__SLM_XLNA_EVEN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__BQ_GAIN_EVEN_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__XLNA_GAIN_ODD_21___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__XLNA_GAIN_ODD_21___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__LNA_GAIN_ODD_21___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__LNA_GAIN_ODD_21___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__GM_GAIN_ODD_21___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__GM_GAIN_ODD_21___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__TIA_GAIN_ODD_21___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__TIA_GAIN_ODD_21___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__SLM_XLNA_ODD_21___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__SLM_XLNA_ODD_21___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__BQ_GAIN_ODD_21___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__BQ_GAIN_ODD_21___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__XLNA_GAIN_EVEN_21___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__XLNA_GAIN_EVEN_21___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__LNA_GAIN_EVEN_21___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__LNA_GAIN_EVEN_21___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__GM_GAIN_EVEN_21___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__GM_GAIN_EVEN_21___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__TIA_GAIN_EVEN_21___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__TIA_GAIN_EVEN_21___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__SLM_XLNA_EVEN_21___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__SLM_XLNA_EVEN_21___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__BQ_GAIN_EVEN_21___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21__BQ_GAIN_EVEN_21___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_21___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22 (0x005E5058) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__XLNA_GAIN_ODD_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__LNA_GAIN_ODD_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__GM_GAIN_ODD_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__TIA_GAIN_ODD_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__SLM_XLNA_ODD_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__BQ_GAIN_ODD_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__XLNA_GAIN_EVEN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__LNA_GAIN_EVEN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__GM_GAIN_EVEN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__TIA_GAIN_EVEN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__SLM_XLNA_EVEN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__BQ_GAIN_EVEN_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__XLNA_GAIN_ODD_22___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__XLNA_GAIN_ODD_22___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__LNA_GAIN_ODD_22___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__LNA_GAIN_ODD_22___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__GM_GAIN_ODD_22___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__GM_GAIN_ODD_22___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__TIA_GAIN_ODD_22___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__TIA_GAIN_ODD_22___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__SLM_XLNA_ODD_22___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__SLM_XLNA_ODD_22___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__BQ_GAIN_ODD_22___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__BQ_GAIN_ODD_22___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__XLNA_GAIN_EVEN_22___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__XLNA_GAIN_EVEN_22___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__LNA_GAIN_EVEN_22___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__LNA_GAIN_EVEN_22___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__GM_GAIN_EVEN_22___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__GM_GAIN_EVEN_22___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__TIA_GAIN_EVEN_22___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__TIA_GAIN_EVEN_22___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__SLM_XLNA_EVEN_22___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__SLM_XLNA_EVEN_22___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__BQ_GAIN_EVEN_22___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22__BQ_GAIN_EVEN_22___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_22___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23 (0x005E505C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__XLNA_GAIN_ODD_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__LNA_GAIN_ODD_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__GM_GAIN_ODD_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__TIA_GAIN_ODD_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__SLM_XLNA_ODD_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__BQ_GAIN_ODD_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__XLNA_GAIN_EVEN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__LNA_GAIN_EVEN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__GM_GAIN_EVEN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__TIA_GAIN_EVEN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__SLM_XLNA_EVEN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__BQ_GAIN_EVEN_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__XLNA_GAIN_ODD_23___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__XLNA_GAIN_ODD_23___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__LNA_GAIN_ODD_23___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__LNA_GAIN_ODD_23___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__GM_GAIN_ODD_23___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__GM_GAIN_ODD_23___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__TIA_GAIN_ODD_23___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__TIA_GAIN_ODD_23___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__SLM_XLNA_ODD_23___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__SLM_XLNA_ODD_23___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__BQ_GAIN_ODD_23___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__BQ_GAIN_ODD_23___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__XLNA_GAIN_EVEN_23___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__XLNA_GAIN_EVEN_23___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__LNA_GAIN_EVEN_23___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__LNA_GAIN_EVEN_23___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__GM_GAIN_EVEN_23___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__GM_GAIN_EVEN_23___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__TIA_GAIN_EVEN_23___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__TIA_GAIN_EVEN_23___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__SLM_XLNA_EVEN_23___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__SLM_XLNA_EVEN_23___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__BQ_GAIN_EVEN_23___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23__BQ_GAIN_EVEN_23___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_23___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24 (0x005E5060) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__XLNA_GAIN_ODD_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__LNA_GAIN_ODD_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__GM_GAIN_ODD_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__TIA_GAIN_ODD_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__SLM_XLNA_ODD_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__BQ_GAIN_ODD_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__XLNA_GAIN_EVEN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__LNA_GAIN_EVEN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__GM_GAIN_EVEN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__TIA_GAIN_EVEN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__SLM_XLNA_EVEN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__BQ_GAIN_EVEN_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__XLNA_GAIN_ODD_24___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__XLNA_GAIN_ODD_24___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__LNA_GAIN_ODD_24___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__LNA_GAIN_ODD_24___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__GM_GAIN_ODD_24___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__GM_GAIN_ODD_24___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__TIA_GAIN_ODD_24___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__TIA_GAIN_ODD_24___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__SLM_XLNA_ODD_24___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__SLM_XLNA_ODD_24___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__BQ_GAIN_ODD_24___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__BQ_GAIN_ODD_24___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__XLNA_GAIN_EVEN_24___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__XLNA_GAIN_EVEN_24___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__LNA_GAIN_EVEN_24___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__LNA_GAIN_EVEN_24___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__GM_GAIN_EVEN_24___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__GM_GAIN_EVEN_24___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__TIA_GAIN_EVEN_24___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__TIA_GAIN_EVEN_24___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__SLM_XLNA_EVEN_24___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__SLM_XLNA_EVEN_24___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__BQ_GAIN_EVEN_24___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24__BQ_GAIN_EVEN_24___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_24___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25 (0x005E5064) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__XLNA_GAIN_ODD_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__LNA_GAIN_ODD_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__GM_GAIN_ODD_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__TIA_GAIN_ODD_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__SLM_XLNA_ODD_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__BQ_GAIN_ODD_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__XLNA_GAIN_EVEN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__LNA_GAIN_EVEN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__GM_GAIN_EVEN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__TIA_GAIN_EVEN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__SLM_XLNA_EVEN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__BQ_GAIN_EVEN_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__XLNA_GAIN_ODD_25___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__XLNA_GAIN_ODD_25___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__LNA_GAIN_ODD_25___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__LNA_GAIN_ODD_25___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__GM_GAIN_ODD_25___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__GM_GAIN_ODD_25___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__TIA_GAIN_ODD_25___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__TIA_GAIN_ODD_25___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__SLM_XLNA_ODD_25___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__SLM_XLNA_ODD_25___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__BQ_GAIN_ODD_25___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__BQ_GAIN_ODD_25___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__XLNA_GAIN_EVEN_25___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__XLNA_GAIN_EVEN_25___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__LNA_GAIN_EVEN_25___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__LNA_GAIN_EVEN_25___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__GM_GAIN_EVEN_25___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__GM_GAIN_EVEN_25___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__TIA_GAIN_EVEN_25___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__TIA_GAIN_EVEN_25___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__SLM_XLNA_EVEN_25___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__SLM_XLNA_EVEN_25___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__BQ_GAIN_EVEN_25___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25__BQ_GAIN_EVEN_25___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_25___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26 (0x005E5068) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__XLNA_GAIN_ODD_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__LNA_GAIN_ODD_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__GM_GAIN_ODD_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__TIA_GAIN_ODD_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__SLM_XLNA_ODD_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__BQ_GAIN_ODD_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__XLNA_GAIN_EVEN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__LNA_GAIN_EVEN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__GM_GAIN_EVEN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__TIA_GAIN_EVEN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__SLM_XLNA_EVEN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__BQ_GAIN_EVEN_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__XLNA_GAIN_ODD_26___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__XLNA_GAIN_ODD_26___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__LNA_GAIN_ODD_26___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__LNA_GAIN_ODD_26___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__GM_GAIN_ODD_26___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__GM_GAIN_ODD_26___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__TIA_GAIN_ODD_26___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__TIA_GAIN_ODD_26___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__SLM_XLNA_ODD_26___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__SLM_XLNA_ODD_26___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__BQ_GAIN_ODD_26___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__BQ_GAIN_ODD_26___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__XLNA_GAIN_EVEN_26___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__XLNA_GAIN_EVEN_26___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__LNA_GAIN_EVEN_26___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__LNA_GAIN_EVEN_26___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__GM_GAIN_EVEN_26___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__GM_GAIN_EVEN_26___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__TIA_GAIN_EVEN_26___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__TIA_GAIN_EVEN_26___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__SLM_XLNA_EVEN_26___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__SLM_XLNA_EVEN_26___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__BQ_GAIN_EVEN_26___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26__BQ_GAIN_EVEN_26___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_26___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27 (0x005E506C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__XLNA_GAIN_ODD_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__LNA_GAIN_ODD_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__GM_GAIN_ODD_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__TIA_GAIN_ODD_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__SLM_XLNA_ODD_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__BQ_GAIN_ODD_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__XLNA_GAIN_EVEN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__LNA_GAIN_EVEN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__GM_GAIN_EVEN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__TIA_GAIN_EVEN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__SLM_XLNA_EVEN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__BQ_GAIN_EVEN_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__XLNA_GAIN_ODD_27___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__XLNA_GAIN_ODD_27___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__LNA_GAIN_ODD_27___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__LNA_GAIN_ODD_27___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__GM_GAIN_ODD_27___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__GM_GAIN_ODD_27___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__TIA_GAIN_ODD_27___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__TIA_GAIN_ODD_27___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__SLM_XLNA_ODD_27___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__SLM_XLNA_ODD_27___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__BQ_GAIN_ODD_27___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__BQ_GAIN_ODD_27___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__XLNA_GAIN_EVEN_27___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__XLNA_GAIN_EVEN_27___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__LNA_GAIN_EVEN_27___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__LNA_GAIN_EVEN_27___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__GM_GAIN_EVEN_27___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__GM_GAIN_EVEN_27___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__TIA_GAIN_EVEN_27___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__TIA_GAIN_EVEN_27___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__SLM_XLNA_EVEN_27___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__SLM_XLNA_EVEN_27___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__BQ_GAIN_EVEN_27___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27__BQ_GAIN_EVEN_27___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_27___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28 (0x005E5070) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__XLNA_GAIN_ODD_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__LNA_GAIN_ODD_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__GM_GAIN_ODD_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__TIA_GAIN_ODD_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__SLM_XLNA_ODD_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__BQ_GAIN_ODD_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__XLNA_GAIN_EVEN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__LNA_GAIN_EVEN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__GM_GAIN_EVEN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__TIA_GAIN_EVEN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__SLM_XLNA_EVEN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__BQ_GAIN_EVEN_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__XLNA_GAIN_ODD_28___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__XLNA_GAIN_ODD_28___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__LNA_GAIN_ODD_28___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__LNA_GAIN_ODD_28___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__GM_GAIN_ODD_28___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__GM_GAIN_ODD_28___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__TIA_GAIN_ODD_28___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__TIA_GAIN_ODD_28___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__SLM_XLNA_ODD_28___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__SLM_XLNA_ODD_28___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__BQ_GAIN_ODD_28___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__BQ_GAIN_ODD_28___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__XLNA_GAIN_EVEN_28___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__XLNA_GAIN_EVEN_28___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__LNA_GAIN_EVEN_28___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__LNA_GAIN_EVEN_28___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__GM_GAIN_EVEN_28___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__GM_GAIN_EVEN_28___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__TIA_GAIN_EVEN_28___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__TIA_GAIN_EVEN_28___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__SLM_XLNA_EVEN_28___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__SLM_XLNA_EVEN_28___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__BQ_GAIN_EVEN_28___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28__BQ_GAIN_EVEN_28___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_28___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29 (0x005E5074) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__XLNA_GAIN_ODD_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__LNA_GAIN_ODD_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__GM_GAIN_ODD_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__TIA_GAIN_ODD_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__SLM_XLNA_ODD_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__BQ_GAIN_ODD_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__XLNA_GAIN_EVEN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__LNA_GAIN_EVEN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__GM_GAIN_EVEN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__TIA_GAIN_EVEN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__SLM_XLNA_EVEN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__BQ_GAIN_EVEN_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__XLNA_GAIN_ODD_29___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__XLNA_GAIN_ODD_29___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__LNA_GAIN_ODD_29___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__LNA_GAIN_ODD_29___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__GM_GAIN_ODD_29___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__GM_GAIN_ODD_29___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__TIA_GAIN_ODD_29___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__TIA_GAIN_ODD_29___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__SLM_XLNA_ODD_29___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__SLM_XLNA_ODD_29___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__BQ_GAIN_ODD_29___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__BQ_GAIN_ODD_29___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__XLNA_GAIN_EVEN_29___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__XLNA_GAIN_EVEN_29___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__LNA_GAIN_EVEN_29___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__LNA_GAIN_EVEN_29___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__GM_GAIN_EVEN_29___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__GM_GAIN_EVEN_29___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__TIA_GAIN_EVEN_29___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__TIA_GAIN_EVEN_29___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__SLM_XLNA_EVEN_29___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__SLM_XLNA_EVEN_29___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__BQ_GAIN_EVEN_29___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29__BQ_GAIN_EVEN_29___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_29___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30 (0x005E5078) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__XLNA_GAIN_ODD_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__LNA_GAIN_ODD_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__GM_GAIN_ODD_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__TIA_GAIN_ODD_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__SLM_XLNA_ODD_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__BQ_GAIN_ODD_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__XLNA_GAIN_EVEN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__LNA_GAIN_EVEN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__GM_GAIN_EVEN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__TIA_GAIN_EVEN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__SLM_XLNA_EVEN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__BQ_GAIN_EVEN_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__XLNA_GAIN_ODD_30___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__XLNA_GAIN_ODD_30___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__LNA_GAIN_ODD_30___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__LNA_GAIN_ODD_30___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__GM_GAIN_ODD_30___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__GM_GAIN_ODD_30___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__TIA_GAIN_ODD_30___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__TIA_GAIN_ODD_30___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__SLM_XLNA_ODD_30___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__SLM_XLNA_ODD_30___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__BQ_GAIN_ODD_30___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__BQ_GAIN_ODD_30___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__XLNA_GAIN_EVEN_30___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__XLNA_GAIN_EVEN_30___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__LNA_GAIN_EVEN_30___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__LNA_GAIN_EVEN_30___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__GM_GAIN_EVEN_30___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__GM_GAIN_EVEN_30___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__TIA_GAIN_EVEN_30___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__TIA_GAIN_EVEN_30___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__SLM_XLNA_EVEN_30___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__SLM_XLNA_EVEN_30___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__BQ_GAIN_EVEN_30___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30__BQ_GAIN_EVEN_30___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_30___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31 (0x005E507C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__XLNA_GAIN_ODD_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__LNA_GAIN_ODD_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__GM_GAIN_ODD_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__TIA_GAIN_ODD_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__SLM_XLNA_ODD_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__BQ_GAIN_ODD_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__XLNA_GAIN_EVEN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__LNA_GAIN_EVEN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__GM_GAIN_EVEN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__TIA_GAIN_EVEN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__SLM_XLNA_EVEN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__BQ_GAIN_EVEN_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__XLNA_GAIN_ODD_31___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__XLNA_GAIN_ODD_31___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__LNA_GAIN_ODD_31___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__LNA_GAIN_ODD_31___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__GM_GAIN_ODD_31___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__GM_GAIN_ODD_31___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__TIA_GAIN_ODD_31___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__TIA_GAIN_ODD_31___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__SLM_XLNA_ODD_31___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__SLM_XLNA_ODD_31___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__BQ_GAIN_ODD_31___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__BQ_GAIN_ODD_31___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__XLNA_GAIN_EVEN_31___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__XLNA_GAIN_EVEN_31___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__LNA_GAIN_EVEN_31___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__LNA_GAIN_EVEN_31___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__GM_GAIN_EVEN_31___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__GM_GAIN_EVEN_31___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__TIA_GAIN_EVEN_31___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__TIA_GAIN_EVEN_31___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__SLM_XLNA_EVEN_31___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__SLM_XLNA_EVEN_31___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__BQ_GAIN_EVEN_31___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31__BQ_GAIN_EVEN_31___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_31___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32 (0x005E5080) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__XLNA_GAIN_ODD_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__LNA_GAIN_ODD_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__GM_GAIN_ODD_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__TIA_GAIN_ODD_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__SLM_XLNA_ODD_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__BQ_GAIN_ODD_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__XLNA_GAIN_EVEN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__LNA_GAIN_EVEN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__GM_GAIN_EVEN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__TIA_GAIN_EVEN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__SLM_XLNA_EVEN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__BQ_GAIN_EVEN_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__XLNA_GAIN_ODD_32___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__XLNA_GAIN_ODD_32___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__LNA_GAIN_ODD_32___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__LNA_GAIN_ODD_32___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__GM_GAIN_ODD_32___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__GM_GAIN_ODD_32___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__TIA_GAIN_ODD_32___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__TIA_GAIN_ODD_32___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__SLM_XLNA_ODD_32___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__SLM_XLNA_ODD_32___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__BQ_GAIN_ODD_32___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__BQ_GAIN_ODD_32___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__XLNA_GAIN_EVEN_32___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__XLNA_GAIN_EVEN_32___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__LNA_GAIN_EVEN_32___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__LNA_GAIN_EVEN_32___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__GM_GAIN_EVEN_32___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__GM_GAIN_EVEN_32___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__TIA_GAIN_EVEN_32___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__TIA_GAIN_EVEN_32___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__SLM_XLNA_EVEN_32___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__SLM_XLNA_EVEN_32___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__BQ_GAIN_EVEN_32___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32__BQ_GAIN_EVEN_32___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_32___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33 (0x005E5084) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__XLNA_GAIN_ODD_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__LNA_GAIN_ODD_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__GM_GAIN_ODD_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__TIA_GAIN_ODD_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__SLM_XLNA_ODD_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__BQ_GAIN_ODD_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__XLNA_GAIN_EVEN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__LNA_GAIN_EVEN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__GM_GAIN_EVEN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__TIA_GAIN_EVEN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__SLM_XLNA_EVEN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__BQ_GAIN_EVEN_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__XLNA_GAIN_ODD_33___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__XLNA_GAIN_ODD_33___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__LNA_GAIN_ODD_33___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__LNA_GAIN_ODD_33___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__GM_GAIN_ODD_33___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__GM_GAIN_ODD_33___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__TIA_GAIN_ODD_33___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__TIA_GAIN_ODD_33___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__SLM_XLNA_ODD_33___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__SLM_XLNA_ODD_33___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__BQ_GAIN_ODD_33___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__BQ_GAIN_ODD_33___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__XLNA_GAIN_EVEN_33___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__XLNA_GAIN_EVEN_33___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__LNA_GAIN_EVEN_33___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__LNA_GAIN_EVEN_33___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__GM_GAIN_EVEN_33___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__GM_GAIN_EVEN_33___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__TIA_GAIN_EVEN_33___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__TIA_GAIN_EVEN_33___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__SLM_XLNA_EVEN_33___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__SLM_XLNA_EVEN_33___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__BQ_GAIN_EVEN_33___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33__BQ_GAIN_EVEN_33___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_33___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34 (0x005E5088) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__XLNA_GAIN_ODD_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__LNA_GAIN_ODD_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__GM_GAIN_ODD_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__TIA_GAIN_ODD_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__SLM_XLNA_ODD_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__BQ_GAIN_ODD_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__XLNA_GAIN_EVEN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__LNA_GAIN_EVEN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__GM_GAIN_EVEN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__TIA_GAIN_EVEN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__SLM_XLNA_EVEN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__BQ_GAIN_EVEN_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__XLNA_GAIN_ODD_34___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__XLNA_GAIN_ODD_34___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__LNA_GAIN_ODD_34___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__LNA_GAIN_ODD_34___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__GM_GAIN_ODD_34___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__GM_GAIN_ODD_34___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__TIA_GAIN_ODD_34___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__TIA_GAIN_ODD_34___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__SLM_XLNA_ODD_34___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__SLM_XLNA_ODD_34___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__BQ_GAIN_ODD_34___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__BQ_GAIN_ODD_34___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__XLNA_GAIN_EVEN_34___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__XLNA_GAIN_EVEN_34___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__LNA_GAIN_EVEN_34___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__LNA_GAIN_EVEN_34___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__GM_GAIN_EVEN_34___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__GM_GAIN_EVEN_34___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__TIA_GAIN_EVEN_34___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__TIA_GAIN_EVEN_34___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__SLM_XLNA_EVEN_34___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__SLM_XLNA_EVEN_34___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__BQ_GAIN_EVEN_34___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34__BQ_GAIN_EVEN_34___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_34___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35 (0x005E508C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__XLNA_GAIN_ODD_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__LNA_GAIN_ODD_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__GM_GAIN_ODD_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__TIA_GAIN_ODD_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__SLM_XLNA_ODD_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__BQ_GAIN_ODD_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__XLNA_GAIN_EVEN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__LNA_GAIN_EVEN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__GM_GAIN_EVEN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__TIA_GAIN_EVEN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__SLM_XLNA_EVEN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__BQ_GAIN_EVEN_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__XLNA_GAIN_ODD_35___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__XLNA_GAIN_ODD_35___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__LNA_GAIN_ODD_35___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__LNA_GAIN_ODD_35___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__GM_GAIN_ODD_35___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__GM_GAIN_ODD_35___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__TIA_GAIN_ODD_35___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__TIA_GAIN_ODD_35___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__SLM_XLNA_ODD_35___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__SLM_XLNA_ODD_35___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__BQ_GAIN_ODD_35___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__BQ_GAIN_ODD_35___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__XLNA_GAIN_EVEN_35___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__XLNA_GAIN_EVEN_35___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__LNA_GAIN_EVEN_35___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__LNA_GAIN_EVEN_35___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__GM_GAIN_EVEN_35___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__GM_GAIN_EVEN_35___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__TIA_GAIN_EVEN_35___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__TIA_GAIN_EVEN_35___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__SLM_XLNA_EVEN_35___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__SLM_XLNA_EVEN_35___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__BQ_GAIN_EVEN_35___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35__BQ_GAIN_EVEN_35___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_35___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36 (0x005E5090) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__XLNA_GAIN_ODD_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__LNA_GAIN_ODD_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__GM_GAIN_ODD_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__TIA_GAIN_ODD_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__SLM_XLNA_ODD_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__BQ_GAIN_ODD_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__XLNA_GAIN_EVEN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__LNA_GAIN_EVEN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__GM_GAIN_EVEN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__TIA_GAIN_EVEN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__SLM_XLNA_EVEN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__BQ_GAIN_EVEN_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__XLNA_GAIN_ODD_36___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__XLNA_GAIN_ODD_36___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__LNA_GAIN_ODD_36___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__LNA_GAIN_ODD_36___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__GM_GAIN_ODD_36___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__GM_GAIN_ODD_36___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__TIA_GAIN_ODD_36___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__TIA_GAIN_ODD_36___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__SLM_XLNA_ODD_36___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__SLM_XLNA_ODD_36___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__BQ_GAIN_ODD_36___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__BQ_GAIN_ODD_36___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__XLNA_GAIN_EVEN_36___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__XLNA_GAIN_EVEN_36___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__LNA_GAIN_EVEN_36___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__LNA_GAIN_EVEN_36___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__GM_GAIN_EVEN_36___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__GM_GAIN_EVEN_36___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__TIA_GAIN_EVEN_36___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__TIA_GAIN_EVEN_36___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__SLM_XLNA_EVEN_36___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__SLM_XLNA_EVEN_36___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__BQ_GAIN_EVEN_36___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36__BQ_GAIN_EVEN_36___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_36___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37 (0x005E5094) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__XLNA_GAIN_ODD_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__LNA_GAIN_ODD_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__GM_GAIN_ODD_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__TIA_GAIN_ODD_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__SLM_XLNA_ODD_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__BQ_GAIN_ODD_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__XLNA_GAIN_EVEN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__LNA_GAIN_EVEN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__GM_GAIN_EVEN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__TIA_GAIN_EVEN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__SLM_XLNA_EVEN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__BQ_GAIN_EVEN_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__XLNA_GAIN_ODD_37___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__XLNA_GAIN_ODD_37___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__LNA_GAIN_ODD_37___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__LNA_GAIN_ODD_37___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__GM_GAIN_ODD_37___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__GM_GAIN_ODD_37___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__TIA_GAIN_ODD_37___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__TIA_GAIN_ODD_37___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__SLM_XLNA_ODD_37___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__SLM_XLNA_ODD_37___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__BQ_GAIN_ODD_37___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__BQ_GAIN_ODD_37___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__XLNA_GAIN_EVEN_37___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__XLNA_GAIN_EVEN_37___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__LNA_GAIN_EVEN_37___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__LNA_GAIN_EVEN_37___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__GM_GAIN_EVEN_37___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__GM_GAIN_EVEN_37___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__TIA_GAIN_EVEN_37___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__TIA_GAIN_EVEN_37___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__SLM_XLNA_EVEN_37___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__SLM_XLNA_EVEN_37___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__BQ_GAIN_EVEN_37___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37__BQ_GAIN_EVEN_37___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_37___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38 (0x005E5098) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__XLNA_GAIN_ODD_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__LNA_GAIN_ODD_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__GM_GAIN_ODD_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__TIA_GAIN_ODD_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__SLM_XLNA_ODD_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__BQ_GAIN_ODD_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__XLNA_GAIN_EVEN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__LNA_GAIN_EVEN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__GM_GAIN_EVEN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__TIA_GAIN_EVEN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__SLM_XLNA_EVEN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__BQ_GAIN_EVEN_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__XLNA_GAIN_ODD_38___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__XLNA_GAIN_ODD_38___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__LNA_GAIN_ODD_38___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__LNA_GAIN_ODD_38___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__GM_GAIN_ODD_38___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__GM_GAIN_ODD_38___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__TIA_GAIN_ODD_38___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__TIA_GAIN_ODD_38___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__SLM_XLNA_ODD_38___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__SLM_XLNA_ODD_38___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__BQ_GAIN_ODD_38___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__BQ_GAIN_ODD_38___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__XLNA_GAIN_EVEN_38___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__XLNA_GAIN_EVEN_38___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__LNA_GAIN_EVEN_38___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__LNA_GAIN_EVEN_38___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__GM_GAIN_EVEN_38___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__GM_GAIN_EVEN_38___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__TIA_GAIN_EVEN_38___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__TIA_GAIN_EVEN_38___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__SLM_XLNA_EVEN_38___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__SLM_XLNA_EVEN_38___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__BQ_GAIN_EVEN_38___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38__BQ_GAIN_EVEN_38___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_38___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39 (0x005E509C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__XLNA_GAIN_ODD_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__LNA_GAIN_ODD_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__GM_GAIN_ODD_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__TIA_GAIN_ODD_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__SLM_XLNA_ODD_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__BQ_GAIN_ODD_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__XLNA_GAIN_EVEN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__LNA_GAIN_EVEN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__GM_GAIN_EVEN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__TIA_GAIN_EVEN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__SLM_XLNA_EVEN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__BQ_GAIN_EVEN_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__XLNA_GAIN_ODD_39___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__XLNA_GAIN_ODD_39___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__LNA_GAIN_ODD_39___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__LNA_GAIN_ODD_39___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__GM_GAIN_ODD_39___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__GM_GAIN_ODD_39___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__TIA_GAIN_ODD_39___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__TIA_GAIN_ODD_39___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__SLM_XLNA_ODD_39___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__SLM_XLNA_ODD_39___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__BQ_GAIN_ODD_39___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__BQ_GAIN_ODD_39___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__XLNA_GAIN_EVEN_39___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__XLNA_GAIN_EVEN_39___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__LNA_GAIN_EVEN_39___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__LNA_GAIN_EVEN_39___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__GM_GAIN_EVEN_39___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__GM_GAIN_EVEN_39___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__TIA_GAIN_EVEN_39___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__TIA_GAIN_EVEN_39___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__SLM_XLNA_EVEN_39___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__SLM_XLNA_EVEN_39___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__BQ_GAIN_EVEN_39___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39__BQ_GAIN_EVEN_39___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_39___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40 (0x005E50A0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__XLNA_GAIN_ODD_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__LNA_GAIN_ODD_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__GM_GAIN_ODD_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__TIA_GAIN_ODD_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__SLM_XLNA_ODD_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__BQ_GAIN_ODD_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__XLNA_GAIN_EVEN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__LNA_GAIN_EVEN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__GM_GAIN_EVEN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__TIA_GAIN_EVEN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__SLM_XLNA_EVEN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__BQ_GAIN_EVEN_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__XLNA_GAIN_ODD_40___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__XLNA_GAIN_ODD_40___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__LNA_GAIN_ODD_40___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__LNA_GAIN_ODD_40___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__GM_GAIN_ODD_40___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__GM_GAIN_ODD_40___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__TIA_GAIN_ODD_40___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__TIA_GAIN_ODD_40___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__SLM_XLNA_ODD_40___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__SLM_XLNA_ODD_40___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__BQ_GAIN_ODD_40___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__BQ_GAIN_ODD_40___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__XLNA_GAIN_EVEN_40___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__XLNA_GAIN_EVEN_40___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__LNA_GAIN_EVEN_40___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__LNA_GAIN_EVEN_40___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__GM_GAIN_EVEN_40___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__GM_GAIN_EVEN_40___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__TIA_GAIN_EVEN_40___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__TIA_GAIN_EVEN_40___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__SLM_XLNA_EVEN_40___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__SLM_XLNA_EVEN_40___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__BQ_GAIN_EVEN_40___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40__BQ_GAIN_EVEN_40___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_40___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41 (0x005E50A4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__XLNA_GAIN_ODD_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__LNA_GAIN_ODD_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__GM_GAIN_ODD_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__TIA_GAIN_ODD_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__SLM_XLNA_ODD_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__BQ_GAIN_ODD_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__XLNA_GAIN_EVEN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__LNA_GAIN_EVEN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__GM_GAIN_EVEN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__TIA_GAIN_EVEN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__SLM_XLNA_EVEN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__BQ_GAIN_EVEN_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__XLNA_GAIN_ODD_41___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__XLNA_GAIN_ODD_41___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__LNA_GAIN_ODD_41___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__LNA_GAIN_ODD_41___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__GM_GAIN_ODD_41___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__GM_GAIN_ODD_41___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__TIA_GAIN_ODD_41___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__TIA_GAIN_ODD_41___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__SLM_XLNA_ODD_41___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__SLM_XLNA_ODD_41___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__BQ_GAIN_ODD_41___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__BQ_GAIN_ODD_41___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__XLNA_GAIN_EVEN_41___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__XLNA_GAIN_EVEN_41___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__LNA_GAIN_EVEN_41___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__LNA_GAIN_EVEN_41___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__GM_GAIN_EVEN_41___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__GM_GAIN_EVEN_41___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__TIA_GAIN_EVEN_41___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__TIA_GAIN_EVEN_41___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__SLM_XLNA_EVEN_41___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__SLM_XLNA_EVEN_41___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__BQ_GAIN_EVEN_41___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41__BQ_GAIN_EVEN_41___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_41___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42 (0x005E50A8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__XLNA_GAIN_ODD_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__LNA_GAIN_ODD_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__GM_GAIN_ODD_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__TIA_GAIN_ODD_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__SLM_XLNA_ODD_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__BQ_GAIN_ODD_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__XLNA_GAIN_EVEN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__LNA_GAIN_EVEN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__GM_GAIN_EVEN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__TIA_GAIN_EVEN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__SLM_XLNA_EVEN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__BQ_GAIN_EVEN_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__XLNA_GAIN_ODD_42___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__XLNA_GAIN_ODD_42___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__LNA_GAIN_ODD_42___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__LNA_GAIN_ODD_42___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__GM_GAIN_ODD_42___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__GM_GAIN_ODD_42___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__TIA_GAIN_ODD_42___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__TIA_GAIN_ODD_42___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__SLM_XLNA_ODD_42___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__SLM_XLNA_ODD_42___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__BQ_GAIN_ODD_42___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__BQ_GAIN_ODD_42___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__XLNA_GAIN_EVEN_42___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__XLNA_GAIN_EVEN_42___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__LNA_GAIN_EVEN_42___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__LNA_GAIN_EVEN_42___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__GM_GAIN_EVEN_42___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__GM_GAIN_EVEN_42___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__TIA_GAIN_EVEN_42___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__TIA_GAIN_EVEN_42___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__SLM_XLNA_EVEN_42___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__SLM_XLNA_EVEN_42___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__BQ_GAIN_EVEN_42___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42__BQ_GAIN_EVEN_42___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_42___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43 (0x005E50AC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__XLNA_GAIN_ODD_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__LNA_GAIN_ODD_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__GM_GAIN_ODD_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__TIA_GAIN_ODD_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__SLM_XLNA_ODD_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__BQ_GAIN_ODD_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__XLNA_GAIN_EVEN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__LNA_GAIN_EVEN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__GM_GAIN_EVEN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__TIA_GAIN_EVEN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__SLM_XLNA_EVEN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__BQ_GAIN_EVEN_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__XLNA_GAIN_ODD_43___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__XLNA_GAIN_ODD_43___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__LNA_GAIN_ODD_43___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__LNA_GAIN_ODD_43___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__GM_GAIN_ODD_43___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__GM_GAIN_ODD_43___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__TIA_GAIN_ODD_43___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__TIA_GAIN_ODD_43___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__SLM_XLNA_ODD_43___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__SLM_XLNA_ODD_43___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__BQ_GAIN_ODD_43___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__BQ_GAIN_ODD_43___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__XLNA_GAIN_EVEN_43___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__XLNA_GAIN_EVEN_43___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__LNA_GAIN_EVEN_43___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__LNA_GAIN_EVEN_43___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__GM_GAIN_EVEN_43___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__GM_GAIN_EVEN_43___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__TIA_GAIN_EVEN_43___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__TIA_GAIN_EVEN_43___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__SLM_XLNA_EVEN_43___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__SLM_XLNA_EVEN_43___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__BQ_GAIN_EVEN_43___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43__BQ_GAIN_EVEN_43___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_43___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44 (0x005E50B0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__XLNA_GAIN_ODD_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__LNA_GAIN_ODD_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__GM_GAIN_ODD_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__TIA_GAIN_ODD_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__SLM_XLNA_ODD_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__BQ_GAIN_ODD_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__XLNA_GAIN_EVEN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__LNA_GAIN_EVEN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__GM_GAIN_EVEN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__TIA_GAIN_EVEN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__SLM_XLNA_EVEN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__BQ_GAIN_EVEN_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__XLNA_GAIN_ODD_44___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__XLNA_GAIN_ODD_44___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__LNA_GAIN_ODD_44___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__LNA_GAIN_ODD_44___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__GM_GAIN_ODD_44___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__GM_GAIN_ODD_44___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__TIA_GAIN_ODD_44___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__TIA_GAIN_ODD_44___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__SLM_XLNA_ODD_44___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__SLM_XLNA_ODD_44___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__BQ_GAIN_ODD_44___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__BQ_GAIN_ODD_44___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__XLNA_GAIN_EVEN_44___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__XLNA_GAIN_EVEN_44___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__LNA_GAIN_EVEN_44___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__LNA_GAIN_EVEN_44___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__GM_GAIN_EVEN_44___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__GM_GAIN_EVEN_44___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__TIA_GAIN_EVEN_44___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__TIA_GAIN_EVEN_44___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__SLM_XLNA_EVEN_44___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__SLM_XLNA_EVEN_44___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__BQ_GAIN_EVEN_44___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44__BQ_GAIN_EVEN_44___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_44___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45 (0x005E50B4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__XLNA_GAIN_ODD_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__LNA_GAIN_ODD_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__GM_GAIN_ODD_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__TIA_GAIN_ODD_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__SLM_XLNA_ODD_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__BQ_GAIN_ODD_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__XLNA_GAIN_EVEN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__LNA_GAIN_EVEN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__GM_GAIN_EVEN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__TIA_GAIN_EVEN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__SLM_XLNA_EVEN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__BQ_GAIN_EVEN_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__XLNA_GAIN_ODD_45___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__XLNA_GAIN_ODD_45___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__LNA_GAIN_ODD_45___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__LNA_GAIN_ODD_45___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__GM_GAIN_ODD_45___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__GM_GAIN_ODD_45___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__TIA_GAIN_ODD_45___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__TIA_GAIN_ODD_45___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__SLM_XLNA_ODD_45___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__SLM_XLNA_ODD_45___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__BQ_GAIN_ODD_45___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__BQ_GAIN_ODD_45___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__XLNA_GAIN_EVEN_45___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__XLNA_GAIN_EVEN_45___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__LNA_GAIN_EVEN_45___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__LNA_GAIN_EVEN_45___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__GM_GAIN_EVEN_45___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__GM_GAIN_EVEN_45___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__TIA_GAIN_EVEN_45___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__TIA_GAIN_EVEN_45___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__SLM_XLNA_EVEN_45___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__SLM_XLNA_EVEN_45___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__BQ_GAIN_EVEN_45___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45__BQ_GAIN_EVEN_45___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_45___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46 (0x005E50B8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__XLNA_GAIN_ODD_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__LNA_GAIN_ODD_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__GM_GAIN_ODD_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__TIA_GAIN_ODD_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__SLM_XLNA_ODD_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__BQ_GAIN_ODD_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__XLNA_GAIN_EVEN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__LNA_GAIN_EVEN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__GM_GAIN_EVEN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__TIA_GAIN_EVEN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__SLM_XLNA_EVEN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__BQ_GAIN_EVEN_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__XLNA_GAIN_ODD_46___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__XLNA_GAIN_ODD_46___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__LNA_GAIN_ODD_46___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__LNA_GAIN_ODD_46___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__GM_GAIN_ODD_46___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__GM_GAIN_ODD_46___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__TIA_GAIN_ODD_46___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__TIA_GAIN_ODD_46___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__SLM_XLNA_ODD_46___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__SLM_XLNA_ODD_46___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__BQ_GAIN_ODD_46___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__BQ_GAIN_ODD_46___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__XLNA_GAIN_EVEN_46___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__XLNA_GAIN_EVEN_46___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__LNA_GAIN_EVEN_46___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__LNA_GAIN_EVEN_46___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__GM_GAIN_EVEN_46___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__GM_GAIN_EVEN_46___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__TIA_GAIN_EVEN_46___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__TIA_GAIN_EVEN_46___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__SLM_XLNA_EVEN_46___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__SLM_XLNA_EVEN_46___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__BQ_GAIN_EVEN_46___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46__BQ_GAIN_EVEN_46___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_46___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47 (0x005E50BC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__XLNA_GAIN_ODD_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__LNA_GAIN_ODD_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__GM_GAIN_ODD_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__TIA_GAIN_ODD_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__SLM_XLNA_ODD_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__BQ_GAIN_ODD_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__XLNA_GAIN_EVEN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__LNA_GAIN_EVEN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__GM_GAIN_EVEN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__TIA_GAIN_EVEN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__SLM_XLNA_EVEN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__BQ_GAIN_EVEN_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__XLNA_GAIN_ODD_47___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__XLNA_GAIN_ODD_47___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__LNA_GAIN_ODD_47___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__LNA_GAIN_ODD_47___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__GM_GAIN_ODD_47___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__GM_GAIN_ODD_47___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__TIA_GAIN_ODD_47___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__TIA_GAIN_ODD_47___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__SLM_XLNA_ODD_47___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__SLM_XLNA_ODD_47___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__BQ_GAIN_ODD_47___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__BQ_GAIN_ODD_47___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__XLNA_GAIN_EVEN_47___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__XLNA_GAIN_EVEN_47___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__LNA_GAIN_EVEN_47___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__LNA_GAIN_EVEN_47___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__GM_GAIN_EVEN_47___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__GM_GAIN_EVEN_47___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__TIA_GAIN_EVEN_47___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__TIA_GAIN_EVEN_47___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__SLM_XLNA_EVEN_47___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__SLM_XLNA_EVEN_47___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__BQ_GAIN_EVEN_47___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47__BQ_GAIN_EVEN_47___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_47___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48 (0x005E50C0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__XLNA_GAIN_ODD_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__LNA_GAIN_ODD_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__GM_GAIN_ODD_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__TIA_GAIN_ODD_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__SLM_XLNA_ODD_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__BQ_GAIN_ODD_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__XLNA_GAIN_EVEN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__LNA_GAIN_EVEN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__GM_GAIN_EVEN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__TIA_GAIN_EVEN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__SLM_XLNA_EVEN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__BQ_GAIN_EVEN_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__XLNA_GAIN_ODD_48___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__XLNA_GAIN_ODD_48___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__LNA_GAIN_ODD_48___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__LNA_GAIN_ODD_48___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__GM_GAIN_ODD_48___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__GM_GAIN_ODD_48___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__TIA_GAIN_ODD_48___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__TIA_GAIN_ODD_48___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__SLM_XLNA_ODD_48___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__SLM_XLNA_ODD_48___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__BQ_GAIN_ODD_48___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__BQ_GAIN_ODD_48___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__XLNA_GAIN_EVEN_48___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__XLNA_GAIN_EVEN_48___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__LNA_GAIN_EVEN_48___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__LNA_GAIN_EVEN_48___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__GM_GAIN_EVEN_48___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__GM_GAIN_EVEN_48___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__TIA_GAIN_EVEN_48___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__TIA_GAIN_EVEN_48___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__SLM_XLNA_EVEN_48___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__SLM_XLNA_EVEN_48___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__BQ_GAIN_EVEN_48___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48__BQ_GAIN_EVEN_48___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_48___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49 (0x005E50C4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__XLNA_GAIN_ODD_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__LNA_GAIN_ODD_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__GM_GAIN_ODD_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__TIA_GAIN_ODD_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__SLM_XLNA_ODD_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__BQ_GAIN_ODD_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__XLNA_GAIN_EVEN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__LNA_GAIN_EVEN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__GM_GAIN_EVEN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__TIA_GAIN_EVEN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__SLM_XLNA_EVEN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__BQ_GAIN_EVEN_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__XLNA_GAIN_ODD_49___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__XLNA_GAIN_ODD_49___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__LNA_GAIN_ODD_49___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__LNA_GAIN_ODD_49___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__GM_GAIN_ODD_49___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__GM_GAIN_ODD_49___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__TIA_GAIN_ODD_49___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__TIA_GAIN_ODD_49___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__SLM_XLNA_ODD_49___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__SLM_XLNA_ODD_49___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__BQ_GAIN_ODD_49___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__BQ_GAIN_ODD_49___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__XLNA_GAIN_EVEN_49___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__XLNA_GAIN_EVEN_49___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__LNA_GAIN_EVEN_49___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__LNA_GAIN_EVEN_49___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__GM_GAIN_EVEN_49___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__GM_GAIN_EVEN_49___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__TIA_GAIN_EVEN_49___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__TIA_GAIN_EVEN_49___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__SLM_XLNA_EVEN_49___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__SLM_XLNA_EVEN_49___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__BQ_GAIN_EVEN_49___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49__BQ_GAIN_EVEN_49___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_49___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50 (0x005E50C8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__XLNA_GAIN_ODD_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__LNA_GAIN_ODD_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__GM_GAIN_ODD_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__TIA_GAIN_ODD_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__SLM_XLNA_ODD_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__BQ_GAIN_ODD_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__XLNA_GAIN_EVEN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__LNA_GAIN_EVEN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__GM_GAIN_EVEN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__TIA_GAIN_EVEN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__SLM_XLNA_EVEN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__BQ_GAIN_EVEN_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__XLNA_GAIN_ODD_50___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__XLNA_GAIN_ODD_50___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__LNA_GAIN_ODD_50___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__LNA_GAIN_ODD_50___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__GM_GAIN_ODD_50___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__GM_GAIN_ODD_50___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__TIA_GAIN_ODD_50___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__TIA_GAIN_ODD_50___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__SLM_XLNA_ODD_50___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__SLM_XLNA_ODD_50___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__BQ_GAIN_ODD_50___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__BQ_GAIN_ODD_50___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__XLNA_GAIN_EVEN_50___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__XLNA_GAIN_EVEN_50___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__LNA_GAIN_EVEN_50___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__LNA_GAIN_EVEN_50___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__GM_GAIN_EVEN_50___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__GM_GAIN_EVEN_50___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__TIA_GAIN_EVEN_50___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__TIA_GAIN_EVEN_50___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__SLM_XLNA_EVEN_50___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__SLM_XLNA_EVEN_50___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__BQ_GAIN_EVEN_50___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50__BQ_GAIN_EVEN_50___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_50___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51 (0x005E50CC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__XLNA_GAIN_ODD_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__LNA_GAIN_ODD_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__GM_GAIN_ODD_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__TIA_GAIN_ODD_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__SLM_XLNA_ODD_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__BQ_GAIN_ODD_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__XLNA_GAIN_EVEN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__LNA_GAIN_EVEN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__GM_GAIN_EVEN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__TIA_GAIN_EVEN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__SLM_XLNA_EVEN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__BQ_GAIN_EVEN_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__XLNA_GAIN_ODD_51___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__XLNA_GAIN_ODD_51___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__LNA_GAIN_ODD_51___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__LNA_GAIN_ODD_51___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__GM_GAIN_ODD_51___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__GM_GAIN_ODD_51___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__TIA_GAIN_ODD_51___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__TIA_GAIN_ODD_51___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__SLM_XLNA_ODD_51___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__SLM_XLNA_ODD_51___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__BQ_GAIN_ODD_51___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__BQ_GAIN_ODD_51___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__XLNA_GAIN_EVEN_51___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__XLNA_GAIN_EVEN_51___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__LNA_GAIN_EVEN_51___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__LNA_GAIN_EVEN_51___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__GM_GAIN_EVEN_51___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__GM_GAIN_EVEN_51___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__TIA_GAIN_EVEN_51___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__TIA_GAIN_EVEN_51___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__SLM_XLNA_EVEN_51___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__SLM_XLNA_EVEN_51___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__BQ_GAIN_EVEN_51___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51__BQ_GAIN_EVEN_51___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_51___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52 (0x005E50D0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__XLNA_GAIN_ODD_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__LNA_GAIN_ODD_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__GM_GAIN_ODD_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__TIA_GAIN_ODD_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__SLM_XLNA_ODD_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__BQ_GAIN_ODD_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__XLNA_GAIN_EVEN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__LNA_GAIN_EVEN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__GM_GAIN_EVEN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__TIA_GAIN_EVEN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__SLM_XLNA_EVEN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__BQ_GAIN_EVEN_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__XLNA_GAIN_ODD_52___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__XLNA_GAIN_ODD_52___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__LNA_GAIN_ODD_52___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__LNA_GAIN_ODD_52___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__GM_GAIN_ODD_52___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__GM_GAIN_ODD_52___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__TIA_GAIN_ODD_52___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__TIA_GAIN_ODD_52___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__SLM_XLNA_ODD_52___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__SLM_XLNA_ODD_52___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__BQ_GAIN_ODD_52___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__BQ_GAIN_ODD_52___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__XLNA_GAIN_EVEN_52___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__XLNA_GAIN_EVEN_52___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__LNA_GAIN_EVEN_52___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__LNA_GAIN_EVEN_52___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__GM_GAIN_EVEN_52___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__GM_GAIN_EVEN_52___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__TIA_GAIN_EVEN_52___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__TIA_GAIN_EVEN_52___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__SLM_XLNA_EVEN_52___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__SLM_XLNA_EVEN_52___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__BQ_GAIN_EVEN_52___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52__BQ_GAIN_EVEN_52___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_52___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53 (0x005E50D4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__XLNA_GAIN_ODD_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__LNA_GAIN_ODD_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__GM_GAIN_ODD_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__TIA_GAIN_ODD_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__SLM_XLNA_ODD_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__BQ_GAIN_ODD_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__XLNA_GAIN_EVEN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__LNA_GAIN_EVEN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__GM_GAIN_EVEN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__TIA_GAIN_EVEN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__SLM_XLNA_EVEN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__BQ_GAIN_EVEN_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__XLNA_GAIN_ODD_53___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__XLNA_GAIN_ODD_53___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__LNA_GAIN_ODD_53___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__LNA_GAIN_ODD_53___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__GM_GAIN_ODD_53___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__GM_GAIN_ODD_53___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__TIA_GAIN_ODD_53___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__TIA_GAIN_ODD_53___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__SLM_XLNA_ODD_53___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__SLM_XLNA_ODD_53___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__BQ_GAIN_ODD_53___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__BQ_GAIN_ODD_53___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__XLNA_GAIN_EVEN_53___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__XLNA_GAIN_EVEN_53___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__LNA_GAIN_EVEN_53___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__LNA_GAIN_EVEN_53___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__GM_GAIN_EVEN_53___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__GM_GAIN_EVEN_53___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__TIA_GAIN_EVEN_53___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__TIA_GAIN_EVEN_53___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__SLM_XLNA_EVEN_53___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__SLM_XLNA_EVEN_53___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__BQ_GAIN_EVEN_53___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53__BQ_GAIN_EVEN_53___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_53___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54 (0x005E50D8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__XLNA_GAIN_ODD_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__LNA_GAIN_ODD_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__GM_GAIN_ODD_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__TIA_GAIN_ODD_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__SLM_XLNA_ODD_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__BQ_GAIN_ODD_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__XLNA_GAIN_EVEN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__LNA_GAIN_EVEN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__GM_GAIN_EVEN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__TIA_GAIN_EVEN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__SLM_XLNA_EVEN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__BQ_GAIN_EVEN_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__XLNA_GAIN_ODD_54___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__XLNA_GAIN_ODD_54___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__LNA_GAIN_ODD_54___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__LNA_GAIN_ODD_54___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__GM_GAIN_ODD_54___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__GM_GAIN_ODD_54___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__TIA_GAIN_ODD_54___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__TIA_GAIN_ODD_54___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__SLM_XLNA_ODD_54___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__SLM_XLNA_ODD_54___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__BQ_GAIN_ODD_54___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__BQ_GAIN_ODD_54___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__XLNA_GAIN_EVEN_54___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__XLNA_GAIN_EVEN_54___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__LNA_GAIN_EVEN_54___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__LNA_GAIN_EVEN_54___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__GM_GAIN_EVEN_54___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__GM_GAIN_EVEN_54___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__TIA_GAIN_EVEN_54___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__TIA_GAIN_EVEN_54___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__SLM_XLNA_EVEN_54___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__SLM_XLNA_EVEN_54___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__BQ_GAIN_EVEN_54___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54__BQ_GAIN_EVEN_54___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_54___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55 (0x005E50DC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__XLNA_GAIN_ODD_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__LNA_GAIN_ODD_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__GM_GAIN_ODD_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__TIA_GAIN_ODD_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__SLM_XLNA_ODD_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__BQ_GAIN_ODD_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__XLNA_GAIN_EVEN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__LNA_GAIN_EVEN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__GM_GAIN_EVEN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__TIA_GAIN_EVEN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__SLM_XLNA_EVEN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__BQ_GAIN_EVEN_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__XLNA_GAIN_ODD_55___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__XLNA_GAIN_ODD_55___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__LNA_GAIN_ODD_55___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__LNA_GAIN_ODD_55___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__GM_GAIN_ODD_55___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__GM_GAIN_ODD_55___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__TIA_GAIN_ODD_55___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__TIA_GAIN_ODD_55___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__SLM_XLNA_ODD_55___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__SLM_XLNA_ODD_55___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__BQ_GAIN_ODD_55___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__BQ_GAIN_ODD_55___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__XLNA_GAIN_EVEN_55___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__XLNA_GAIN_EVEN_55___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__LNA_GAIN_EVEN_55___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__LNA_GAIN_EVEN_55___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__GM_GAIN_EVEN_55___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__GM_GAIN_EVEN_55___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__TIA_GAIN_EVEN_55___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__TIA_GAIN_EVEN_55___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__SLM_XLNA_EVEN_55___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__SLM_XLNA_EVEN_55___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__BQ_GAIN_EVEN_55___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55__BQ_GAIN_EVEN_55___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_55___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56 (0x005E50E0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__XLNA_GAIN_ODD_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__LNA_GAIN_ODD_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__GM_GAIN_ODD_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__TIA_GAIN_ODD_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__SLM_XLNA_ODD_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__BQ_GAIN_ODD_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__XLNA_GAIN_EVEN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__LNA_GAIN_EVEN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__GM_GAIN_EVEN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__TIA_GAIN_EVEN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__SLM_XLNA_EVEN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__BQ_GAIN_EVEN_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__XLNA_GAIN_ODD_56___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__XLNA_GAIN_ODD_56___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__LNA_GAIN_ODD_56___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__LNA_GAIN_ODD_56___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__GM_GAIN_ODD_56___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__GM_GAIN_ODD_56___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__TIA_GAIN_ODD_56___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__TIA_GAIN_ODD_56___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__SLM_XLNA_ODD_56___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__SLM_XLNA_ODD_56___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__BQ_GAIN_ODD_56___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__BQ_GAIN_ODD_56___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__XLNA_GAIN_EVEN_56___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__XLNA_GAIN_EVEN_56___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__LNA_GAIN_EVEN_56___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__LNA_GAIN_EVEN_56___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__GM_GAIN_EVEN_56___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__GM_GAIN_EVEN_56___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__TIA_GAIN_EVEN_56___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__TIA_GAIN_EVEN_56___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__SLM_XLNA_EVEN_56___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__SLM_XLNA_EVEN_56___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__BQ_GAIN_EVEN_56___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56__BQ_GAIN_EVEN_56___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_56___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57 (0x005E50E4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__XLNA_GAIN_ODD_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__LNA_GAIN_ODD_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__GM_GAIN_ODD_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__TIA_GAIN_ODD_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__SLM_XLNA_ODD_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__BQ_GAIN_ODD_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__XLNA_GAIN_EVEN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__LNA_GAIN_EVEN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__GM_GAIN_EVEN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__TIA_GAIN_EVEN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__SLM_XLNA_EVEN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__BQ_GAIN_EVEN_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__XLNA_GAIN_ODD_57___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__XLNA_GAIN_ODD_57___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__LNA_GAIN_ODD_57___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__LNA_GAIN_ODD_57___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__GM_GAIN_ODD_57___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__GM_GAIN_ODD_57___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__TIA_GAIN_ODD_57___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__TIA_GAIN_ODD_57___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__SLM_XLNA_ODD_57___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__SLM_XLNA_ODD_57___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__BQ_GAIN_ODD_57___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__BQ_GAIN_ODD_57___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__XLNA_GAIN_EVEN_57___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__XLNA_GAIN_EVEN_57___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__LNA_GAIN_EVEN_57___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__LNA_GAIN_EVEN_57___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__GM_GAIN_EVEN_57___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__GM_GAIN_EVEN_57___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__TIA_GAIN_EVEN_57___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__TIA_GAIN_EVEN_57___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__SLM_XLNA_EVEN_57___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__SLM_XLNA_EVEN_57___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__BQ_GAIN_EVEN_57___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57__BQ_GAIN_EVEN_57___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_57___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58 (0x005E50E8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__XLNA_GAIN_ODD_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__LNA_GAIN_ODD_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__GM_GAIN_ODD_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__TIA_GAIN_ODD_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__SLM_XLNA_ODD_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__BQ_GAIN_ODD_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__XLNA_GAIN_EVEN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__LNA_GAIN_EVEN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__GM_GAIN_EVEN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__TIA_GAIN_EVEN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__SLM_XLNA_EVEN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__BQ_GAIN_EVEN_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__XLNA_GAIN_ODD_58___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__XLNA_GAIN_ODD_58___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__LNA_GAIN_ODD_58___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__LNA_GAIN_ODD_58___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__GM_GAIN_ODD_58___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__GM_GAIN_ODD_58___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__TIA_GAIN_ODD_58___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__TIA_GAIN_ODD_58___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__SLM_XLNA_ODD_58___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__SLM_XLNA_ODD_58___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__BQ_GAIN_ODD_58___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__BQ_GAIN_ODD_58___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__XLNA_GAIN_EVEN_58___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__XLNA_GAIN_EVEN_58___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__LNA_GAIN_EVEN_58___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__LNA_GAIN_EVEN_58___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__GM_GAIN_EVEN_58___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__GM_GAIN_EVEN_58___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__TIA_GAIN_EVEN_58___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__TIA_GAIN_EVEN_58___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__SLM_XLNA_EVEN_58___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__SLM_XLNA_EVEN_58___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__BQ_GAIN_EVEN_58___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58__BQ_GAIN_EVEN_58___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_58___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59 (0x005E50EC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__XLNA_GAIN_ODD_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__LNA_GAIN_ODD_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__GM_GAIN_ODD_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__TIA_GAIN_ODD_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__SLM_XLNA_ODD_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__BQ_GAIN_ODD_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__XLNA_GAIN_EVEN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__LNA_GAIN_EVEN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__GM_GAIN_EVEN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__TIA_GAIN_EVEN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__SLM_XLNA_EVEN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__BQ_GAIN_EVEN_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__XLNA_GAIN_ODD_59___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__XLNA_GAIN_ODD_59___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__LNA_GAIN_ODD_59___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__LNA_GAIN_ODD_59___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__GM_GAIN_ODD_59___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__GM_GAIN_ODD_59___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__TIA_GAIN_ODD_59___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__TIA_GAIN_ODD_59___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__SLM_XLNA_ODD_59___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__SLM_XLNA_ODD_59___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__BQ_GAIN_ODD_59___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__BQ_GAIN_ODD_59___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__XLNA_GAIN_EVEN_59___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__XLNA_GAIN_EVEN_59___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__LNA_GAIN_EVEN_59___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__LNA_GAIN_EVEN_59___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__GM_GAIN_EVEN_59___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__GM_GAIN_EVEN_59___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__TIA_GAIN_EVEN_59___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__TIA_GAIN_EVEN_59___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__SLM_XLNA_EVEN_59___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__SLM_XLNA_EVEN_59___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__BQ_GAIN_EVEN_59___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59__BQ_GAIN_EVEN_59___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_59___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60 (0x005E50F0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__XLNA_GAIN_ODD_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__LNA_GAIN_ODD_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__GM_GAIN_ODD_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__TIA_GAIN_ODD_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__SLM_XLNA_ODD_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__BQ_GAIN_ODD_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__XLNA_GAIN_EVEN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__LNA_GAIN_EVEN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__GM_GAIN_EVEN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__TIA_GAIN_EVEN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__SLM_XLNA_EVEN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__BQ_GAIN_EVEN_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__XLNA_GAIN_ODD_60___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__XLNA_GAIN_ODD_60___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__LNA_GAIN_ODD_60___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__LNA_GAIN_ODD_60___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__GM_GAIN_ODD_60___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__GM_GAIN_ODD_60___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__TIA_GAIN_ODD_60___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__TIA_GAIN_ODD_60___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__SLM_XLNA_ODD_60___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__SLM_XLNA_ODD_60___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__BQ_GAIN_ODD_60___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__BQ_GAIN_ODD_60___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__XLNA_GAIN_EVEN_60___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__XLNA_GAIN_EVEN_60___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__LNA_GAIN_EVEN_60___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__LNA_GAIN_EVEN_60___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__GM_GAIN_EVEN_60___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__GM_GAIN_EVEN_60___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__TIA_GAIN_EVEN_60___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__TIA_GAIN_EVEN_60___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__SLM_XLNA_EVEN_60___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__SLM_XLNA_EVEN_60___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__BQ_GAIN_EVEN_60___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60__BQ_GAIN_EVEN_60___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_60___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61 (0x005E50F4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__XLNA_GAIN_ODD_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__LNA_GAIN_ODD_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__GM_GAIN_ODD_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__TIA_GAIN_ODD_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__SLM_XLNA_ODD_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__BQ_GAIN_ODD_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__XLNA_GAIN_EVEN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__LNA_GAIN_EVEN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__GM_GAIN_EVEN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__TIA_GAIN_EVEN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__SLM_XLNA_EVEN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__BQ_GAIN_EVEN_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__XLNA_GAIN_ODD_61___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__XLNA_GAIN_ODD_61___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__LNA_GAIN_ODD_61___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__LNA_GAIN_ODD_61___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__GM_GAIN_ODD_61___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__GM_GAIN_ODD_61___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__TIA_GAIN_ODD_61___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__TIA_GAIN_ODD_61___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__SLM_XLNA_ODD_61___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__SLM_XLNA_ODD_61___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__BQ_GAIN_ODD_61___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__BQ_GAIN_ODD_61___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__XLNA_GAIN_EVEN_61___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__XLNA_GAIN_EVEN_61___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__LNA_GAIN_EVEN_61___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__LNA_GAIN_EVEN_61___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__GM_GAIN_EVEN_61___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__GM_GAIN_EVEN_61___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__TIA_GAIN_EVEN_61___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__TIA_GAIN_EVEN_61___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__SLM_XLNA_EVEN_61___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__SLM_XLNA_EVEN_61___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__BQ_GAIN_EVEN_61___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61__BQ_GAIN_EVEN_61___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_61___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62 (0x005E50F8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__XLNA_GAIN_ODD_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__LNA_GAIN_ODD_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__GM_GAIN_ODD_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__TIA_GAIN_ODD_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__SLM_XLNA_ODD_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__BQ_GAIN_ODD_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__XLNA_GAIN_EVEN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__LNA_GAIN_EVEN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__GM_GAIN_EVEN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__TIA_GAIN_EVEN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__SLM_XLNA_EVEN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__BQ_GAIN_EVEN_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__XLNA_GAIN_ODD_62___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__XLNA_GAIN_ODD_62___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__LNA_GAIN_ODD_62___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__LNA_GAIN_ODD_62___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__GM_GAIN_ODD_62___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__GM_GAIN_ODD_62___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__TIA_GAIN_ODD_62___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__TIA_GAIN_ODD_62___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__SLM_XLNA_ODD_62___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__SLM_XLNA_ODD_62___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__BQ_GAIN_ODD_62___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__BQ_GAIN_ODD_62___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__XLNA_GAIN_EVEN_62___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__XLNA_GAIN_EVEN_62___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__LNA_GAIN_EVEN_62___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__LNA_GAIN_EVEN_62___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__GM_GAIN_EVEN_62___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__GM_GAIN_EVEN_62___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__TIA_GAIN_EVEN_62___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__TIA_GAIN_EVEN_62___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__SLM_XLNA_EVEN_62___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__SLM_XLNA_EVEN_62___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__BQ_GAIN_EVEN_62___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62__BQ_GAIN_EVEN_62___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_62___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63 (0x005E50FC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__XLNA_GAIN_ODD_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__LNA_GAIN_ODD_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__GM_GAIN_ODD_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__TIA_GAIN_ODD_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__SLM_XLNA_ODD_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__BQ_GAIN_ODD_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__XLNA_GAIN_EVEN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__LNA_GAIN_EVEN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__GM_GAIN_EVEN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__TIA_GAIN_EVEN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__SLM_XLNA_EVEN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__BQ_GAIN_EVEN_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__XLNA_GAIN_ODD_63___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__XLNA_GAIN_ODD_63___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__LNA_GAIN_ODD_63___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__LNA_GAIN_ODD_63___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__GM_GAIN_ODD_63___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__GM_GAIN_ODD_63___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__TIA_GAIN_ODD_63___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__TIA_GAIN_ODD_63___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__SLM_XLNA_ODD_63___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__SLM_XLNA_ODD_63___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__BQ_GAIN_ODD_63___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__BQ_GAIN_ODD_63___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__XLNA_GAIN_EVEN_63___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__XLNA_GAIN_EVEN_63___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__LNA_GAIN_EVEN_63___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__LNA_GAIN_EVEN_63___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__GM_GAIN_EVEN_63___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__GM_GAIN_EVEN_63___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__TIA_GAIN_EVEN_63___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__TIA_GAIN_EVEN_63___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__SLM_XLNA_EVEN_63___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__SLM_XLNA_EVEN_63___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__BQ_GAIN_EVEN_63___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63__BQ_GAIN_EVEN_63___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_63___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64 (0x005E5100) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__XLNA_GAIN_ODD_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__LNA_GAIN_ODD_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__GM_GAIN_ODD_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__TIA_GAIN_ODD_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__SLM_XLNA_ODD_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__BQ_GAIN_ODD_64___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__XLNA_GAIN_EVEN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__LNA_GAIN_EVEN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__GM_GAIN_EVEN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__TIA_GAIN_EVEN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__SLM_XLNA_EVEN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__BQ_GAIN_EVEN_64___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__XLNA_GAIN_ODD_64___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__XLNA_GAIN_ODD_64___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__LNA_GAIN_ODD_64___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__LNA_GAIN_ODD_64___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__GM_GAIN_ODD_64___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__GM_GAIN_ODD_64___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__TIA_GAIN_ODD_64___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__TIA_GAIN_ODD_64___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__SLM_XLNA_ODD_64___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__SLM_XLNA_ODD_64___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__BQ_GAIN_ODD_64___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__BQ_GAIN_ODD_64___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__XLNA_GAIN_EVEN_64___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__XLNA_GAIN_EVEN_64___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__LNA_GAIN_EVEN_64___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__LNA_GAIN_EVEN_64___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__GM_GAIN_EVEN_64___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__GM_GAIN_EVEN_64___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__TIA_GAIN_EVEN_64___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__TIA_GAIN_EVEN_64___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__SLM_XLNA_EVEN_64___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__SLM_XLNA_EVEN_64___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__BQ_GAIN_EVEN_64___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64__BQ_GAIN_EVEN_64___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_64___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65 (0x005E5104) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__XLNA_GAIN_ODD_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__LNA_GAIN_ODD_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__GM_GAIN_ODD_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__TIA_GAIN_ODD_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__SLM_XLNA_ODD_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__BQ_GAIN_ODD_65___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__XLNA_GAIN_EVEN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__LNA_GAIN_EVEN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__GM_GAIN_EVEN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__TIA_GAIN_EVEN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__SLM_XLNA_EVEN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__BQ_GAIN_EVEN_65___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__XLNA_GAIN_ODD_65___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__XLNA_GAIN_ODD_65___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__LNA_GAIN_ODD_65___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__LNA_GAIN_ODD_65___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__GM_GAIN_ODD_65___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__GM_GAIN_ODD_65___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__TIA_GAIN_ODD_65___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__TIA_GAIN_ODD_65___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__SLM_XLNA_ODD_65___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__SLM_XLNA_ODD_65___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__BQ_GAIN_ODD_65___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__BQ_GAIN_ODD_65___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__XLNA_GAIN_EVEN_65___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__XLNA_GAIN_EVEN_65___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__LNA_GAIN_EVEN_65___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__LNA_GAIN_EVEN_65___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__GM_GAIN_EVEN_65___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__GM_GAIN_EVEN_65___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__TIA_GAIN_EVEN_65___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__TIA_GAIN_EVEN_65___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__SLM_XLNA_EVEN_65___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__SLM_XLNA_EVEN_65___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__BQ_GAIN_EVEN_65___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65__BQ_GAIN_EVEN_65___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_65___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66 (0x005E5108) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__XLNA_GAIN_ODD_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__LNA_GAIN_ODD_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__GM_GAIN_ODD_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__TIA_GAIN_ODD_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__SLM_XLNA_ODD_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__BQ_GAIN_ODD_66___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__XLNA_GAIN_EVEN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__LNA_GAIN_EVEN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__GM_GAIN_EVEN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__TIA_GAIN_EVEN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__SLM_XLNA_EVEN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__BQ_GAIN_EVEN_66___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__XLNA_GAIN_ODD_66___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__XLNA_GAIN_ODD_66___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__LNA_GAIN_ODD_66___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__LNA_GAIN_ODD_66___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__GM_GAIN_ODD_66___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__GM_GAIN_ODD_66___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__TIA_GAIN_ODD_66___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__TIA_GAIN_ODD_66___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__SLM_XLNA_ODD_66___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__SLM_XLNA_ODD_66___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__BQ_GAIN_ODD_66___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__BQ_GAIN_ODD_66___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__XLNA_GAIN_EVEN_66___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__XLNA_GAIN_EVEN_66___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__LNA_GAIN_EVEN_66___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__LNA_GAIN_EVEN_66___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__GM_GAIN_EVEN_66___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__GM_GAIN_EVEN_66___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__TIA_GAIN_EVEN_66___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__TIA_GAIN_EVEN_66___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__SLM_XLNA_EVEN_66___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__SLM_XLNA_EVEN_66___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__BQ_GAIN_EVEN_66___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66__BQ_GAIN_EVEN_66___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_66___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67 (0x005E510C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__XLNA_GAIN_ODD_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__LNA_GAIN_ODD_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__GM_GAIN_ODD_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__TIA_GAIN_ODD_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__SLM_XLNA_ODD_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__BQ_GAIN_ODD_67___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__XLNA_GAIN_EVEN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__LNA_GAIN_EVEN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__GM_GAIN_EVEN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__TIA_GAIN_EVEN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__SLM_XLNA_EVEN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__BQ_GAIN_EVEN_67___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__XLNA_GAIN_ODD_67___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__XLNA_GAIN_ODD_67___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__LNA_GAIN_ODD_67___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__LNA_GAIN_ODD_67___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__GM_GAIN_ODD_67___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__GM_GAIN_ODD_67___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__TIA_GAIN_ODD_67___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__TIA_GAIN_ODD_67___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__SLM_XLNA_ODD_67___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__SLM_XLNA_ODD_67___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__BQ_GAIN_ODD_67___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__BQ_GAIN_ODD_67___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__XLNA_GAIN_EVEN_67___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__XLNA_GAIN_EVEN_67___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__LNA_GAIN_EVEN_67___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__LNA_GAIN_EVEN_67___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__GM_GAIN_EVEN_67___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__GM_GAIN_EVEN_67___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__TIA_GAIN_EVEN_67___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__TIA_GAIN_EVEN_67___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__SLM_XLNA_EVEN_67___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__SLM_XLNA_EVEN_67___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__BQ_GAIN_EVEN_67___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67__BQ_GAIN_EVEN_67___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_67___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68 (0x005E5110) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__XLNA_GAIN_ODD_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__LNA_GAIN_ODD_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__GM_GAIN_ODD_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__TIA_GAIN_ODD_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__SLM_XLNA_ODD_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__BQ_GAIN_ODD_68___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__XLNA_GAIN_EVEN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__LNA_GAIN_EVEN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__GM_GAIN_EVEN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__TIA_GAIN_EVEN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__SLM_XLNA_EVEN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__BQ_GAIN_EVEN_68___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__XLNA_GAIN_ODD_68___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__XLNA_GAIN_ODD_68___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__LNA_GAIN_ODD_68___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__LNA_GAIN_ODD_68___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__GM_GAIN_ODD_68___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__GM_GAIN_ODD_68___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__TIA_GAIN_ODD_68___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__TIA_GAIN_ODD_68___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__SLM_XLNA_ODD_68___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__SLM_XLNA_ODD_68___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__BQ_GAIN_ODD_68___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__BQ_GAIN_ODD_68___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__XLNA_GAIN_EVEN_68___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__XLNA_GAIN_EVEN_68___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__LNA_GAIN_EVEN_68___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__LNA_GAIN_EVEN_68___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__GM_GAIN_EVEN_68___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__GM_GAIN_EVEN_68___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__TIA_GAIN_EVEN_68___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__TIA_GAIN_EVEN_68___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__SLM_XLNA_EVEN_68___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__SLM_XLNA_EVEN_68___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__BQ_GAIN_EVEN_68___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68__BQ_GAIN_EVEN_68___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_68___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69 (0x005E5114) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__XLNA_GAIN_ODD_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__LNA_GAIN_ODD_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__GM_GAIN_ODD_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__TIA_GAIN_ODD_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__SLM_XLNA_ODD_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__BQ_GAIN_ODD_69___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__XLNA_GAIN_EVEN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__LNA_GAIN_EVEN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__GM_GAIN_EVEN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__TIA_GAIN_EVEN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__SLM_XLNA_EVEN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__BQ_GAIN_EVEN_69___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__XLNA_GAIN_ODD_69___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__XLNA_GAIN_ODD_69___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__LNA_GAIN_ODD_69___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__LNA_GAIN_ODD_69___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__GM_GAIN_ODD_69___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__GM_GAIN_ODD_69___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__TIA_GAIN_ODD_69___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__TIA_GAIN_ODD_69___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__SLM_XLNA_ODD_69___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__SLM_XLNA_ODD_69___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__BQ_GAIN_ODD_69___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__BQ_GAIN_ODD_69___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__XLNA_GAIN_EVEN_69___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__XLNA_GAIN_EVEN_69___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__LNA_GAIN_EVEN_69___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__LNA_GAIN_EVEN_69___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__GM_GAIN_EVEN_69___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__GM_GAIN_EVEN_69___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__TIA_GAIN_EVEN_69___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__TIA_GAIN_EVEN_69___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__SLM_XLNA_EVEN_69___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__SLM_XLNA_EVEN_69___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__BQ_GAIN_EVEN_69___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69__BQ_GAIN_EVEN_69___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_69___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70 (0x005E5118) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__XLNA_GAIN_ODD_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__LNA_GAIN_ODD_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__GM_GAIN_ODD_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__TIA_GAIN_ODD_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__SLM_XLNA_ODD_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__BQ_GAIN_ODD_70___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__XLNA_GAIN_EVEN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__LNA_GAIN_EVEN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__GM_GAIN_EVEN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__TIA_GAIN_EVEN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__SLM_XLNA_EVEN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__BQ_GAIN_EVEN_70___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__XLNA_GAIN_ODD_70___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__XLNA_GAIN_ODD_70___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__LNA_GAIN_ODD_70___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__LNA_GAIN_ODD_70___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__GM_GAIN_ODD_70___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__GM_GAIN_ODD_70___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__TIA_GAIN_ODD_70___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__TIA_GAIN_ODD_70___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__SLM_XLNA_ODD_70___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__SLM_XLNA_ODD_70___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__BQ_GAIN_ODD_70___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__BQ_GAIN_ODD_70___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__XLNA_GAIN_EVEN_70___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__XLNA_GAIN_EVEN_70___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__LNA_GAIN_EVEN_70___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__LNA_GAIN_EVEN_70___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__GM_GAIN_EVEN_70___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__GM_GAIN_EVEN_70___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__TIA_GAIN_EVEN_70___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__TIA_GAIN_EVEN_70___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__SLM_XLNA_EVEN_70___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__SLM_XLNA_EVEN_70___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__BQ_GAIN_EVEN_70___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70__BQ_GAIN_EVEN_70___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_70___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71 (0x005E511C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__XLNA_GAIN_ODD_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__LNA_GAIN_ODD_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__GM_GAIN_ODD_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__TIA_GAIN_ODD_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__SLM_XLNA_ODD_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__BQ_GAIN_ODD_71___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__XLNA_GAIN_EVEN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__LNA_GAIN_EVEN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__GM_GAIN_EVEN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__TIA_GAIN_EVEN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__SLM_XLNA_EVEN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__BQ_GAIN_EVEN_71___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__XLNA_GAIN_ODD_71___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__XLNA_GAIN_ODD_71___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__LNA_GAIN_ODD_71___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__LNA_GAIN_ODD_71___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__GM_GAIN_ODD_71___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__GM_GAIN_ODD_71___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__TIA_GAIN_ODD_71___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__TIA_GAIN_ODD_71___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__SLM_XLNA_ODD_71___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__SLM_XLNA_ODD_71___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__BQ_GAIN_ODD_71___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__BQ_GAIN_ODD_71___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__XLNA_GAIN_EVEN_71___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__XLNA_GAIN_EVEN_71___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__LNA_GAIN_EVEN_71___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__LNA_GAIN_EVEN_71___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__GM_GAIN_EVEN_71___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__GM_GAIN_EVEN_71___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__TIA_GAIN_EVEN_71___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__TIA_GAIN_EVEN_71___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__SLM_XLNA_EVEN_71___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__SLM_XLNA_EVEN_71___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__BQ_GAIN_EVEN_71___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71__BQ_GAIN_EVEN_71___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_71___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72 (0x005E5120) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__XLNA_GAIN_ODD_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__LNA_GAIN_ODD_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__GM_GAIN_ODD_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__TIA_GAIN_ODD_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__SLM_XLNA_ODD_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__BQ_GAIN_ODD_72___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__XLNA_GAIN_EVEN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__LNA_GAIN_EVEN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__GM_GAIN_EVEN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__TIA_GAIN_EVEN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__SLM_XLNA_EVEN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__BQ_GAIN_EVEN_72___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__XLNA_GAIN_ODD_72___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__XLNA_GAIN_ODD_72___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__LNA_GAIN_ODD_72___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__LNA_GAIN_ODD_72___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__GM_GAIN_ODD_72___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__GM_GAIN_ODD_72___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__TIA_GAIN_ODD_72___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__TIA_GAIN_ODD_72___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__SLM_XLNA_ODD_72___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__SLM_XLNA_ODD_72___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__BQ_GAIN_ODD_72___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__BQ_GAIN_ODD_72___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__XLNA_GAIN_EVEN_72___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__XLNA_GAIN_EVEN_72___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__LNA_GAIN_EVEN_72___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__LNA_GAIN_EVEN_72___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__GM_GAIN_EVEN_72___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__GM_GAIN_EVEN_72___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__TIA_GAIN_EVEN_72___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__TIA_GAIN_EVEN_72___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__SLM_XLNA_EVEN_72___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__SLM_XLNA_EVEN_72___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__BQ_GAIN_EVEN_72___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72__BQ_GAIN_EVEN_72___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_72___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73 (0x005E5124) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__XLNA_GAIN_ODD_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__LNA_GAIN_ODD_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__GM_GAIN_ODD_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__TIA_GAIN_ODD_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__SLM_XLNA_ODD_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__BQ_GAIN_ODD_73___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__XLNA_GAIN_EVEN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__LNA_GAIN_EVEN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__GM_GAIN_EVEN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__TIA_GAIN_EVEN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__SLM_XLNA_EVEN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__BQ_GAIN_EVEN_73___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__XLNA_GAIN_ODD_73___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__XLNA_GAIN_ODD_73___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__LNA_GAIN_ODD_73___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__LNA_GAIN_ODD_73___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__GM_GAIN_ODD_73___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__GM_GAIN_ODD_73___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__TIA_GAIN_ODD_73___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__TIA_GAIN_ODD_73___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__SLM_XLNA_ODD_73___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__SLM_XLNA_ODD_73___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__BQ_GAIN_ODD_73___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__BQ_GAIN_ODD_73___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__XLNA_GAIN_EVEN_73___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__XLNA_GAIN_EVEN_73___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__LNA_GAIN_EVEN_73___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__LNA_GAIN_EVEN_73___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__GM_GAIN_EVEN_73___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__GM_GAIN_EVEN_73___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__TIA_GAIN_EVEN_73___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__TIA_GAIN_EVEN_73___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__SLM_XLNA_EVEN_73___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__SLM_XLNA_EVEN_73___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__BQ_GAIN_EVEN_73___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73__BQ_GAIN_EVEN_73___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_73___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74 (0x005E5128) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__XLNA_GAIN_ODD_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__LNA_GAIN_ODD_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__GM_GAIN_ODD_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__TIA_GAIN_ODD_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__SLM_XLNA_ODD_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__BQ_GAIN_ODD_74___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__XLNA_GAIN_EVEN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__LNA_GAIN_EVEN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__GM_GAIN_EVEN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__TIA_GAIN_EVEN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__SLM_XLNA_EVEN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__BQ_GAIN_EVEN_74___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__XLNA_GAIN_ODD_74___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__XLNA_GAIN_ODD_74___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__LNA_GAIN_ODD_74___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__LNA_GAIN_ODD_74___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__GM_GAIN_ODD_74___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__GM_GAIN_ODD_74___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__TIA_GAIN_ODD_74___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__TIA_GAIN_ODD_74___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__SLM_XLNA_ODD_74___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__SLM_XLNA_ODD_74___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__BQ_GAIN_ODD_74___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__BQ_GAIN_ODD_74___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__XLNA_GAIN_EVEN_74___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__XLNA_GAIN_EVEN_74___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__LNA_GAIN_EVEN_74___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__LNA_GAIN_EVEN_74___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__GM_GAIN_EVEN_74___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__GM_GAIN_EVEN_74___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__TIA_GAIN_EVEN_74___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__TIA_GAIN_EVEN_74___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__SLM_XLNA_EVEN_74___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__SLM_XLNA_EVEN_74___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__BQ_GAIN_EVEN_74___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74__BQ_GAIN_EVEN_74___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_74___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75 (0x005E512C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__XLNA_GAIN_ODD_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__LNA_GAIN_ODD_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__GM_GAIN_ODD_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__TIA_GAIN_ODD_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__SLM_XLNA_ODD_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__BQ_GAIN_ODD_75___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__XLNA_GAIN_EVEN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__LNA_GAIN_EVEN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__GM_GAIN_EVEN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__TIA_GAIN_EVEN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__SLM_XLNA_EVEN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__BQ_GAIN_EVEN_75___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__XLNA_GAIN_ODD_75___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__XLNA_GAIN_ODD_75___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__LNA_GAIN_ODD_75___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__LNA_GAIN_ODD_75___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__GM_GAIN_ODD_75___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__GM_GAIN_ODD_75___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__TIA_GAIN_ODD_75___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__TIA_GAIN_ODD_75___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__SLM_XLNA_ODD_75___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__SLM_XLNA_ODD_75___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__BQ_GAIN_ODD_75___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__BQ_GAIN_ODD_75___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__XLNA_GAIN_EVEN_75___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__XLNA_GAIN_EVEN_75___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__LNA_GAIN_EVEN_75___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__LNA_GAIN_EVEN_75___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__GM_GAIN_EVEN_75___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__GM_GAIN_EVEN_75___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__TIA_GAIN_EVEN_75___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__TIA_GAIN_EVEN_75___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__SLM_XLNA_EVEN_75___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__SLM_XLNA_EVEN_75___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__BQ_GAIN_EVEN_75___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75__BQ_GAIN_EVEN_75___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_75___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76 (0x005E5130) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__XLNA_GAIN_ODD_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__LNA_GAIN_ODD_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__GM_GAIN_ODD_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__TIA_GAIN_ODD_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__SLM_XLNA_ODD_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__BQ_GAIN_ODD_76___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__XLNA_GAIN_EVEN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__LNA_GAIN_EVEN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__GM_GAIN_EVEN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__TIA_GAIN_EVEN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__SLM_XLNA_EVEN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__BQ_GAIN_EVEN_76___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__XLNA_GAIN_ODD_76___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__XLNA_GAIN_ODD_76___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__LNA_GAIN_ODD_76___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__LNA_GAIN_ODD_76___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__GM_GAIN_ODD_76___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__GM_GAIN_ODD_76___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__TIA_GAIN_ODD_76___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__TIA_GAIN_ODD_76___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__SLM_XLNA_ODD_76___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__SLM_XLNA_ODD_76___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__BQ_GAIN_ODD_76___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__BQ_GAIN_ODD_76___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__XLNA_GAIN_EVEN_76___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__XLNA_GAIN_EVEN_76___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__LNA_GAIN_EVEN_76___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__LNA_GAIN_EVEN_76___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__GM_GAIN_EVEN_76___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__GM_GAIN_EVEN_76___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__TIA_GAIN_EVEN_76___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__TIA_GAIN_EVEN_76___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__SLM_XLNA_EVEN_76___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__SLM_XLNA_EVEN_76___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__BQ_GAIN_EVEN_76___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76__BQ_GAIN_EVEN_76___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_76___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77 (0x005E5134) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__XLNA_GAIN_ODD_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__LNA_GAIN_ODD_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__GM_GAIN_ODD_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__TIA_GAIN_ODD_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__SLM_XLNA_ODD_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__BQ_GAIN_ODD_77___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__XLNA_GAIN_EVEN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__LNA_GAIN_EVEN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__GM_GAIN_EVEN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__TIA_GAIN_EVEN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__SLM_XLNA_EVEN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__BQ_GAIN_EVEN_77___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__XLNA_GAIN_ODD_77___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__XLNA_GAIN_ODD_77___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__LNA_GAIN_ODD_77___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__LNA_GAIN_ODD_77___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__GM_GAIN_ODD_77___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__GM_GAIN_ODD_77___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__TIA_GAIN_ODD_77___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__TIA_GAIN_ODD_77___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__SLM_XLNA_ODD_77___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__SLM_XLNA_ODD_77___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__BQ_GAIN_ODD_77___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__BQ_GAIN_ODD_77___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__XLNA_GAIN_EVEN_77___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__XLNA_GAIN_EVEN_77___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__LNA_GAIN_EVEN_77___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__LNA_GAIN_EVEN_77___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__GM_GAIN_EVEN_77___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__GM_GAIN_EVEN_77___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__TIA_GAIN_EVEN_77___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__TIA_GAIN_EVEN_77___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__SLM_XLNA_EVEN_77___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__SLM_XLNA_EVEN_77___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__BQ_GAIN_EVEN_77___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77__BQ_GAIN_EVEN_77___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_77___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78 (0x005E5138) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__XLNA_GAIN_ODD_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__LNA_GAIN_ODD_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__GM_GAIN_ODD_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__TIA_GAIN_ODD_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__SLM_XLNA_ODD_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__BQ_GAIN_ODD_78___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__XLNA_GAIN_EVEN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__LNA_GAIN_EVEN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__GM_GAIN_EVEN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__TIA_GAIN_EVEN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__SLM_XLNA_EVEN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__BQ_GAIN_EVEN_78___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__XLNA_GAIN_ODD_78___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__XLNA_GAIN_ODD_78___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__LNA_GAIN_ODD_78___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__LNA_GAIN_ODD_78___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__GM_GAIN_ODD_78___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__GM_GAIN_ODD_78___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__TIA_GAIN_ODD_78___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__TIA_GAIN_ODD_78___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__SLM_XLNA_ODD_78___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__SLM_XLNA_ODD_78___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__BQ_GAIN_ODD_78___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__BQ_GAIN_ODD_78___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__XLNA_GAIN_EVEN_78___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__XLNA_GAIN_EVEN_78___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__LNA_GAIN_EVEN_78___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__LNA_GAIN_EVEN_78___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__GM_GAIN_EVEN_78___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__GM_GAIN_EVEN_78___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__TIA_GAIN_EVEN_78___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__TIA_GAIN_EVEN_78___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__SLM_XLNA_EVEN_78___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__SLM_XLNA_EVEN_78___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__BQ_GAIN_EVEN_78___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78__BQ_GAIN_EVEN_78___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_78___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79 (0x005E513C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__XLNA_GAIN_ODD_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__LNA_GAIN_ODD_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__GM_GAIN_ODD_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__TIA_GAIN_ODD_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__SLM_XLNA_ODD_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__BQ_GAIN_ODD_79___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__XLNA_GAIN_EVEN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__LNA_GAIN_EVEN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__GM_GAIN_EVEN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__TIA_GAIN_EVEN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__SLM_XLNA_EVEN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__BQ_GAIN_EVEN_79___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__XLNA_GAIN_ODD_79___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__XLNA_GAIN_ODD_79___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__LNA_GAIN_ODD_79___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__LNA_GAIN_ODD_79___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__GM_GAIN_ODD_79___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__GM_GAIN_ODD_79___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__TIA_GAIN_ODD_79___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__TIA_GAIN_ODD_79___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__SLM_XLNA_ODD_79___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__SLM_XLNA_ODD_79___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__BQ_GAIN_ODD_79___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__BQ_GAIN_ODD_79___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__XLNA_GAIN_EVEN_79___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__XLNA_GAIN_EVEN_79___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__LNA_GAIN_EVEN_79___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__LNA_GAIN_EVEN_79___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__GM_GAIN_EVEN_79___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__GM_GAIN_EVEN_79___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__TIA_GAIN_EVEN_79___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__TIA_GAIN_EVEN_79___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__SLM_XLNA_EVEN_79___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__SLM_XLNA_EVEN_79___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__BQ_GAIN_EVEN_79___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79__BQ_GAIN_EVEN_79___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_79___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80 (0x005E5140) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__XLNA_GAIN_ODD_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__LNA_GAIN_ODD_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__GM_GAIN_ODD_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__TIA_GAIN_ODD_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__SLM_XLNA_ODD_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__BQ_GAIN_ODD_80___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__XLNA_GAIN_EVEN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__LNA_GAIN_EVEN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__GM_GAIN_EVEN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__TIA_GAIN_EVEN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__SLM_XLNA_EVEN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__BQ_GAIN_EVEN_80___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__XLNA_GAIN_ODD_80___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__XLNA_GAIN_ODD_80___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__LNA_GAIN_ODD_80___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__LNA_GAIN_ODD_80___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__GM_GAIN_ODD_80___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__GM_GAIN_ODD_80___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__TIA_GAIN_ODD_80___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__TIA_GAIN_ODD_80___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__SLM_XLNA_ODD_80___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__SLM_XLNA_ODD_80___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__BQ_GAIN_ODD_80___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__BQ_GAIN_ODD_80___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__XLNA_GAIN_EVEN_80___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__XLNA_GAIN_EVEN_80___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__LNA_GAIN_EVEN_80___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__LNA_GAIN_EVEN_80___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__GM_GAIN_EVEN_80___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__GM_GAIN_EVEN_80___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__TIA_GAIN_EVEN_80___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__TIA_GAIN_EVEN_80___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__SLM_XLNA_EVEN_80___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__SLM_XLNA_EVEN_80___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__BQ_GAIN_EVEN_80___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80__BQ_GAIN_EVEN_80___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_80___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81 (0x005E5144) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__XLNA_GAIN_ODD_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__LNA_GAIN_ODD_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__GM_GAIN_ODD_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__TIA_GAIN_ODD_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__SLM_XLNA_ODD_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__BQ_GAIN_ODD_81___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__XLNA_GAIN_EVEN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__LNA_GAIN_EVEN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__GM_GAIN_EVEN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__TIA_GAIN_EVEN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__SLM_XLNA_EVEN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__BQ_GAIN_EVEN_81___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__XLNA_GAIN_ODD_81___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__XLNA_GAIN_ODD_81___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__LNA_GAIN_ODD_81___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__LNA_GAIN_ODD_81___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__GM_GAIN_ODD_81___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__GM_GAIN_ODD_81___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__TIA_GAIN_ODD_81___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__TIA_GAIN_ODD_81___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__SLM_XLNA_ODD_81___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__SLM_XLNA_ODD_81___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__BQ_GAIN_ODD_81___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__BQ_GAIN_ODD_81___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__XLNA_GAIN_EVEN_81___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__XLNA_GAIN_EVEN_81___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__LNA_GAIN_EVEN_81___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__LNA_GAIN_EVEN_81___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__GM_GAIN_EVEN_81___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__GM_GAIN_EVEN_81___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__TIA_GAIN_EVEN_81___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__TIA_GAIN_EVEN_81___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__SLM_XLNA_EVEN_81___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__SLM_XLNA_EVEN_81___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__BQ_GAIN_EVEN_81___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81__BQ_GAIN_EVEN_81___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_81___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82 (0x005E5148) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__XLNA_GAIN_ODD_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__LNA_GAIN_ODD_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__GM_GAIN_ODD_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__TIA_GAIN_ODD_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__SLM_XLNA_ODD_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__BQ_GAIN_ODD_82___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__XLNA_GAIN_EVEN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__LNA_GAIN_EVEN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__GM_GAIN_EVEN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__TIA_GAIN_EVEN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__SLM_XLNA_EVEN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__BQ_GAIN_EVEN_82___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__XLNA_GAIN_ODD_82___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__XLNA_GAIN_ODD_82___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__LNA_GAIN_ODD_82___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__LNA_GAIN_ODD_82___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__GM_GAIN_ODD_82___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__GM_GAIN_ODD_82___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__TIA_GAIN_ODD_82___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__TIA_GAIN_ODD_82___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__SLM_XLNA_ODD_82___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__SLM_XLNA_ODD_82___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__BQ_GAIN_ODD_82___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__BQ_GAIN_ODD_82___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__XLNA_GAIN_EVEN_82___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__XLNA_GAIN_EVEN_82___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__LNA_GAIN_EVEN_82___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__LNA_GAIN_EVEN_82___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__GM_GAIN_EVEN_82___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__GM_GAIN_EVEN_82___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__TIA_GAIN_EVEN_82___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__TIA_GAIN_EVEN_82___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__SLM_XLNA_EVEN_82___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__SLM_XLNA_EVEN_82___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__BQ_GAIN_EVEN_82___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82__BQ_GAIN_EVEN_82___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_82___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83 (0x005E514C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__XLNA_GAIN_ODD_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__LNA_GAIN_ODD_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__GM_GAIN_ODD_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__TIA_GAIN_ODD_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__SLM_XLNA_ODD_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__BQ_GAIN_ODD_83___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__XLNA_GAIN_EVEN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__LNA_GAIN_EVEN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__GM_GAIN_EVEN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__TIA_GAIN_EVEN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__SLM_XLNA_EVEN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__BQ_GAIN_EVEN_83___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__XLNA_GAIN_ODD_83___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__XLNA_GAIN_ODD_83___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__LNA_GAIN_ODD_83___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__LNA_GAIN_ODD_83___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__GM_GAIN_ODD_83___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__GM_GAIN_ODD_83___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__TIA_GAIN_ODD_83___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__TIA_GAIN_ODD_83___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__SLM_XLNA_ODD_83___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__SLM_XLNA_ODD_83___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__BQ_GAIN_ODD_83___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__BQ_GAIN_ODD_83___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__XLNA_GAIN_EVEN_83___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__XLNA_GAIN_EVEN_83___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__LNA_GAIN_EVEN_83___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__LNA_GAIN_EVEN_83___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__GM_GAIN_EVEN_83___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__GM_GAIN_EVEN_83___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__TIA_GAIN_EVEN_83___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__TIA_GAIN_EVEN_83___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__SLM_XLNA_EVEN_83___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__SLM_XLNA_EVEN_83___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__BQ_GAIN_EVEN_83___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83__BQ_GAIN_EVEN_83___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_83___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84 (0x005E5150) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__XLNA_GAIN_ODD_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__LNA_GAIN_ODD_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__GM_GAIN_ODD_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__TIA_GAIN_ODD_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__SLM_XLNA_ODD_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__BQ_GAIN_ODD_84___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__XLNA_GAIN_EVEN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__LNA_GAIN_EVEN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__GM_GAIN_EVEN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__TIA_GAIN_EVEN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__SLM_XLNA_EVEN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__BQ_GAIN_EVEN_84___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__XLNA_GAIN_ODD_84___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__XLNA_GAIN_ODD_84___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__LNA_GAIN_ODD_84___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__LNA_GAIN_ODD_84___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__GM_GAIN_ODD_84___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__GM_GAIN_ODD_84___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__TIA_GAIN_ODD_84___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__TIA_GAIN_ODD_84___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__SLM_XLNA_ODD_84___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__SLM_XLNA_ODD_84___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__BQ_GAIN_ODD_84___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__BQ_GAIN_ODD_84___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__XLNA_GAIN_EVEN_84___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__XLNA_GAIN_EVEN_84___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__LNA_GAIN_EVEN_84___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__LNA_GAIN_EVEN_84___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__GM_GAIN_EVEN_84___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__GM_GAIN_EVEN_84___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__TIA_GAIN_EVEN_84___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__TIA_GAIN_EVEN_84___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__SLM_XLNA_EVEN_84___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__SLM_XLNA_EVEN_84___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__BQ_GAIN_EVEN_84___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84__BQ_GAIN_EVEN_84___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_84___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85 (0x005E5154) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__XLNA_GAIN_ODD_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__LNA_GAIN_ODD_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__GM_GAIN_ODD_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__TIA_GAIN_ODD_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__SLM_XLNA_ODD_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__BQ_GAIN_ODD_85___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__XLNA_GAIN_EVEN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__LNA_GAIN_EVEN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__GM_GAIN_EVEN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__TIA_GAIN_EVEN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__SLM_XLNA_EVEN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__BQ_GAIN_EVEN_85___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__XLNA_GAIN_ODD_85___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__XLNA_GAIN_ODD_85___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__LNA_GAIN_ODD_85___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__LNA_GAIN_ODD_85___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__GM_GAIN_ODD_85___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__GM_GAIN_ODD_85___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__TIA_GAIN_ODD_85___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__TIA_GAIN_ODD_85___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__SLM_XLNA_ODD_85___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__SLM_XLNA_ODD_85___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__BQ_GAIN_ODD_85___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__BQ_GAIN_ODD_85___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__XLNA_GAIN_EVEN_85___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__XLNA_GAIN_EVEN_85___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__LNA_GAIN_EVEN_85___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__LNA_GAIN_EVEN_85___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__GM_GAIN_EVEN_85___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__GM_GAIN_EVEN_85___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__TIA_GAIN_EVEN_85___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__TIA_GAIN_EVEN_85___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__SLM_XLNA_EVEN_85___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__SLM_XLNA_EVEN_85___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__BQ_GAIN_EVEN_85___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85__BQ_GAIN_EVEN_85___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_85___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86 (0x005E5158) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__XLNA_GAIN_ODD_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__LNA_GAIN_ODD_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__GM_GAIN_ODD_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__TIA_GAIN_ODD_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__SLM_XLNA_ODD_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__BQ_GAIN_ODD_86___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__XLNA_GAIN_EVEN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__LNA_GAIN_EVEN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__GM_GAIN_EVEN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__TIA_GAIN_EVEN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__SLM_XLNA_EVEN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__BQ_GAIN_EVEN_86___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__XLNA_GAIN_ODD_86___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__XLNA_GAIN_ODD_86___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__LNA_GAIN_ODD_86___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__LNA_GAIN_ODD_86___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__GM_GAIN_ODD_86___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__GM_GAIN_ODD_86___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__TIA_GAIN_ODD_86___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__TIA_GAIN_ODD_86___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__SLM_XLNA_ODD_86___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__SLM_XLNA_ODD_86___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__BQ_GAIN_ODD_86___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__BQ_GAIN_ODD_86___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__XLNA_GAIN_EVEN_86___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__XLNA_GAIN_EVEN_86___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__LNA_GAIN_EVEN_86___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__LNA_GAIN_EVEN_86___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__GM_GAIN_EVEN_86___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__GM_GAIN_EVEN_86___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__TIA_GAIN_EVEN_86___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__TIA_GAIN_EVEN_86___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__SLM_XLNA_EVEN_86___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__SLM_XLNA_EVEN_86___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__BQ_GAIN_EVEN_86___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86__BQ_GAIN_EVEN_86___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_86___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87 (0x005E515C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__XLNA_GAIN_ODD_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__LNA_GAIN_ODD_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__GM_GAIN_ODD_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__TIA_GAIN_ODD_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__SLM_XLNA_ODD_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__BQ_GAIN_ODD_87___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__XLNA_GAIN_EVEN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__LNA_GAIN_EVEN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__GM_GAIN_EVEN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__TIA_GAIN_EVEN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__SLM_XLNA_EVEN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__BQ_GAIN_EVEN_87___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__XLNA_GAIN_ODD_87___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__XLNA_GAIN_ODD_87___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__LNA_GAIN_ODD_87___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__LNA_GAIN_ODD_87___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__GM_GAIN_ODD_87___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__GM_GAIN_ODD_87___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__TIA_GAIN_ODD_87___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__TIA_GAIN_ODD_87___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__SLM_XLNA_ODD_87___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__SLM_XLNA_ODD_87___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__BQ_GAIN_ODD_87___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__BQ_GAIN_ODD_87___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__XLNA_GAIN_EVEN_87___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__XLNA_GAIN_EVEN_87___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__LNA_GAIN_EVEN_87___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__LNA_GAIN_EVEN_87___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__GM_GAIN_EVEN_87___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__GM_GAIN_EVEN_87___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__TIA_GAIN_EVEN_87___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__TIA_GAIN_EVEN_87___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__SLM_XLNA_EVEN_87___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__SLM_XLNA_EVEN_87___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__BQ_GAIN_EVEN_87___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87__BQ_GAIN_EVEN_87___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_87___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88 (0x005E5160) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__XLNA_GAIN_ODD_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__LNA_GAIN_ODD_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__GM_GAIN_ODD_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__TIA_GAIN_ODD_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__SLM_XLNA_ODD_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__BQ_GAIN_ODD_88___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__XLNA_GAIN_EVEN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__LNA_GAIN_EVEN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__GM_GAIN_EVEN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__TIA_GAIN_EVEN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__SLM_XLNA_EVEN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__BQ_GAIN_EVEN_88___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__XLNA_GAIN_ODD_88___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__XLNA_GAIN_ODD_88___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__LNA_GAIN_ODD_88___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__LNA_GAIN_ODD_88___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__GM_GAIN_ODD_88___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__GM_GAIN_ODD_88___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__TIA_GAIN_ODD_88___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__TIA_GAIN_ODD_88___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__SLM_XLNA_ODD_88___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__SLM_XLNA_ODD_88___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__BQ_GAIN_ODD_88___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__BQ_GAIN_ODD_88___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__XLNA_GAIN_EVEN_88___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__XLNA_GAIN_EVEN_88___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__LNA_GAIN_EVEN_88___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__LNA_GAIN_EVEN_88___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__GM_GAIN_EVEN_88___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__GM_GAIN_EVEN_88___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__TIA_GAIN_EVEN_88___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__TIA_GAIN_EVEN_88___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__SLM_XLNA_EVEN_88___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__SLM_XLNA_EVEN_88___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__BQ_GAIN_EVEN_88___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88__BQ_GAIN_EVEN_88___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_88___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89 (0x005E5164) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__XLNA_GAIN_ODD_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__LNA_GAIN_ODD_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__GM_GAIN_ODD_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__TIA_GAIN_ODD_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__SLM_XLNA_ODD_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__BQ_GAIN_ODD_89___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__XLNA_GAIN_EVEN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__LNA_GAIN_EVEN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__GM_GAIN_EVEN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__TIA_GAIN_EVEN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__SLM_XLNA_EVEN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__BQ_GAIN_EVEN_89___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__XLNA_GAIN_ODD_89___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__XLNA_GAIN_ODD_89___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__LNA_GAIN_ODD_89___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__LNA_GAIN_ODD_89___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__GM_GAIN_ODD_89___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__GM_GAIN_ODD_89___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__TIA_GAIN_ODD_89___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__TIA_GAIN_ODD_89___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__SLM_XLNA_ODD_89___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__SLM_XLNA_ODD_89___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__BQ_GAIN_ODD_89___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__BQ_GAIN_ODD_89___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__XLNA_GAIN_EVEN_89___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__XLNA_GAIN_EVEN_89___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__LNA_GAIN_EVEN_89___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__LNA_GAIN_EVEN_89___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__GM_GAIN_EVEN_89___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__GM_GAIN_EVEN_89___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__TIA_GAIN_EVEN_89___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__TIA_GAIN_EVEN_89___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__SLM_XLNA_EVEN_89___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__SLM_XLNA_EVEN_89___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__BQ_GAIN_EVEN_89___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89__BQ_GAIN_EVEN_89___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_89___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90 (0x005E5168) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__XLNA_GAIN_ODD_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__LNA_GAIN_ODD_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__GM_GAIN_ODD_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__TIA_GAIN_ODD_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__SLM_XLNA_ODD_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__BQ_GAIN_ODD_90___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__XLNA_GAIN_EVEN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__LNA_GAIN_EVEN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__GM_GAIN_EVEN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__TIA_GAIN_EVEN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__SLM_XLNA_EVEN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__BQ_GAIN_EVEN_90___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__XLNA_GAIN_ODD_90___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__XLNA_GAIN_ODD_90___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__LNA_GAIN_ODD_90___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__LNA_GAIN_ODD_90___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__GM_GAIN_ODD_90___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__GM_GAIN_ODD_90___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__TIA_GAIN_ODD_90___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__TIA_GAIN_ODD_90___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__SLM_XLNA_ODD_90___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__SLM_XLNA_ODD_90___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__BQ_GAIN_ODD_90___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__BQ_GAIN_ODD_90___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__XLNA_GAIN_EVEN_90___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__XLNA_GAIN_EVEN_90___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__LNA_GAIN_EVEN_90___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__LNA_GAIN_EVEN_90___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__GM_GAIN_EVEN_90___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__GM_GAIN_EVEN_90___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__TIA_GAIN_EVEN_90___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__TIA_GAIN_EVEN_90___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__SLM_XLNA_EVEN_90___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__SLM_XLNA_EVEN_90___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__BQ_GAIN_EVEN_90___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90__BQ_GAIN_EVEN_90___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_90___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91 (0x005E516C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__XLNA_GAIN_ODD_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__LNA_GAIN_ODD_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__GM_GAIN_ODD_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__TIA_GAIN_ODD_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__SLM_XLNA_ODD_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__BQ_GAIN_ODD_91___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__XLNA_GAIN_EVEN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__LNA_GAIN_EVEN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__GM_GAIN_EVEN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__TIA_GAIN_EVEN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__SLM_XLNA_EVEN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__BQ_GAIN_EVEN_91___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__XLNA_GAIN_ODD_91___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__XLNA_GAIN_ODD_91___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__LNA_GAIN_ODD_91___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__LNA_GAIN_ODD_91___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__GM_GAIN_ODD_91___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__GM_GAIN_ODD_91___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__TIA_GAIN_ODD_91___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__TIA_GAIN_ODD_91___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__SLM_XLNA_ODD_91___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__SLM_XLNA_ODD_91___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__BQ_GAIN_ODD_91___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__BQ_GAIN_ODD_91___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__XLNA_GAIN_EVEN_91___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__XLNA_GAIN_EVEN_91___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__LNA_GAIN_EVEN_91___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__LNA_GAIN_EVEN_91___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__GM_GAIN_EVEN_91___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__GM_GAIN_EVEN_91___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__TIA_GAIN_EVEN_91___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__TIA_GAIN_EVEN_91___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__SLM_XLNA_EVEN_91___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__SLM_XLNA_EVEN_91___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__BQ_GAIN_EVEN_91___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91__BQ_GAIN_EVEN_91___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_91___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92 (0x005E5170) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__XLNA_GAIN_ODD_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__LNA_GAIN_ODD_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__GM_GAIN_ODD_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__TIA_GAIN_ODD_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__SLM_XLNA_ODD_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__BQ_GAIN_ODD_92___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__XLNA_GAIN_EVEN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__LNA_GAIN_EVEN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__GM_GAIN_EVEN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__TIA_GAIN_EVEN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__SLM_XLNA_EVEN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__BQ_GAIN_EVEN_92___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__XLNA_GAIN_ODD_92___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__XLNA_GAIN_ODD_92___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__LNA_GAIN_ODD_92___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__LNA_GAIN_ODD_92___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__GM_GAIN_ODD_92___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__GM_GAIN_ODD_92___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__TIA_GAIN_ODD_92___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__TIA_GAIN_ODD_92___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__SLM_XLNA_ODD_92___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__SLM_XLNA_ODD_92___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__BQ_GAIN_ODD_92___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__BQ_GAIN_ODD_92___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__XLNA_GAIN_EVEN_92___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__XLNA_GAIN_EVEN_92___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__LNA_GAIN_EVEN_92___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__LNA_GAIN_EVEN_92___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__GM_GAIN_EVEN_92___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__GM_GAIN_EVEN_92___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__TIA_GAIN_EVEN_92___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__TIA_GAIN_EVEN_92___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__SLM_XLNA_EVEN_92___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__SLM_XLNA_EVEN_92___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__BQ_GAIN_EVEN_92___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92__BQ_GAIN_EVEN_92___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_92___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93 (0x005E5174) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__XLNA_GAIN_ODD_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__LNA_GAIN_ODD_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__GM_GAIN_ODD_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__TIA_GAIN_ODD_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__SLM_XLNA_ODD_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__BQ_GAIN_ODD_93___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__XLNA_GAIN_EVEN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__LNA_GAIN_EVEN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__GM_GAIN_EVEN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__TIA_GAIN_EVEN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__SLM_XLNA_EVEN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__BQ_GAIN_EVEN_93___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__XLNA_GAIN_ODD_93___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__XLNA_GAIN_ODD_93___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__LNA_GAIN_ODD_93___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__LNA_GAIN_ODD_93___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__GM_GAIN_ODD_93___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__GM_GAIN_ODD_93___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__TIA_GAIN_ODD_93___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__TIA_GAIN_ODD_93___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__SLM_XLNA_ODD_93___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__SLM_XLNA_ODD_93___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__BQ_GAIN_ODD_93___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__BQ_GAIN_ODD_93___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__XLNA_GAIN_EVEN_93___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__XLNA_GAIN_EVEN_93___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__LNA_GAIN_EVEN_93___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__LNA_GAIN_EVEN_93___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__GM_GAIN_EVEN_93___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__GM_GAIN_EVEN_93___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__TIA_GAIN_EVEN_93___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__TIA_GAIN_EVEN_93___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__SLM_XLNA_EVEN_93___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__SLM_XLNA_EVEN_93___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__BQ_GAIN_EVEN_93___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93__BQ_GAIN_EVEN_93___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_93___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94 (0x005E5178) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__XLNA_GAIN_ODD_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__LNA_GAIN_ODD_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__GM_GAIN_ODD_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__TIA_GAIN_ODD_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__SLM_XLNA_ODD_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__BQ_GAIN_ODD_94___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__XLNA_GAIN_EVEN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__LNA_GAIN_EVEN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__GM_GAIN_EVEN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__TIA_GAIN_EVEN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__SLM_XLNA_EVEN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__BQ_GAIN_EVEN_94___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__XLNA_GAIN_ODD_94___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__XLNA_GAIN_ODD_94___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__LNA_GAIN_ODD_94___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__LNA_GAIN_ODD_94___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__GM_GAIN_ODD_94___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__GM_GAIN_ODD_94___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__TIA_GAIN_ODD_94___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__TIA_GAIN_ODD_94___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__SLM_XLNA_ODD_94___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__SLM_XLNA_ODD_94___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__BQ_GAIN_ODD_94___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__BQ_GAIN_ODD_94___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__XLNA_GAIN_EVEN_94___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__XLNA_GAIN_EVEN_94___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__LNA_GAIN_EVEN_94___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__LNA_GAIN_EVEN_94___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__GM_GAIN_EVEN_94___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__GM_GAIN_EVEN_94___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__TIA_GAIN_EVEN_94___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__TIA_GAIN_EVEN_94___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__SLM_XLNA_EVEN_94___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__SLM_XLNA_EVEN_94___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__BQ_GAIN_EVEN_94___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94__BQ_GAIN_EVEN_94___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_94___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95 (0x005E517C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__XLNA_GAIN_ODD_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__LNA_GAIN_ODD_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__GM_GAIN_ODD_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__TIA_GAIN_ODD_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__SLM_XLNA_ODD_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__BQ_GAIN_ODD_95___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__XLNA_GAIN_EVEN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__LNA_GAIN_EVEN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__GM_GAIN_EVEN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__TIA_GAIN_EVEN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__SLM_XLNA_EVEN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__BQ_GAIN_EVEN_95___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__XLNA_GAIN_ODD_95___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__XLNA_GAIN_ODD_95___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__LNA_GAIN_ODD_95___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__LNA_GAIN_ODD_95___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__GM_GAIN_ODD_95___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__GM_GAIN_ODD_95___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__TIA_GAIN_ODD_95___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__TIA_GAIN_ODD_95___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__SLM_XLNA_ODD_95___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__SLM_XLNA_ODD_95___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__BQ_GAIN_ODD_95___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__BQ_GAIN_ODD_95___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__XLNA_GAIN_EVEN_95___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__XLNA_GAIN_EVEN_95___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__LNA_GAIN_EVEN_95___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__LNA_GAIN_EVEN_95___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__GM_GAIN_EVEN_95___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__GM_GAIN_EVEN_95___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__TIA_GAIN_EVEN_95___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__TIA_GAIN_EVEN_95___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__SLM_XLNA_EVEN_95___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__SLM_XLNA_EVEN_95___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__BQ_GAIN_EVEN_95___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95__BQ_GAIN_EVEN_95___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_95___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96 (0x005E5180) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__XLNA_GAIN_ODD_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__LNA_GAIN_ODD_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__GM_GAIN_ODD_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__TIA_GAIN_ODD_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__SLM_XLNA_ODD_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__BQ_GAIN_ODD_96___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__XLNA_GAIN_EVEN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__LNA_GAIN_EVEN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__GM_GAIN_EVEN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__TIA_GAIN_EVEN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__SLM_XLNA_EVEN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__BQ_GAIN_EVEN_96___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__XLNA_GAIN_ODD_96___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__XLNA_GAIN_ODD_96___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__LNA_GAIN_ODD_96___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__LNA_GAIN_ODD_96___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__GM_GAIN_ODD_96___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__GM_GAIN_ODD_96___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__TIA_GAIN_ODD_96___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__TIA_GAIN_ODD_96___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__SLM_XLNA_ODD_96___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__SLM_XLNA_ODD_96___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__BQ_GAIN_ODD_96___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__BQ_GAIN_ODD_96___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__XLNA_GAIN_EVEN_96___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__XLNA_GAIN_EVEN_96___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__LNA_GAIN_EVEN_96___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__LNA_GAIN_EVEN_96___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__GM_GAIN_EVEN_96___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__GM_GAIN_EVEN_96___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__TIA_GAIN_EVEN_96___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__TIA_GAIN_EVEN_96___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__SLM_XLNA_EVEN_96___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__SLM_XLNA_EVEN_96___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__BQ_GAIN_EVEN_96___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96__BQ_GAIN_EVEN_96___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_96___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97 (0x005E5184) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__XLNA_GAIN_ODD_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__LNA_GAIN_ODD_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__GM_GAIN_ODD_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__TIA_GAIN_ODD_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__SLM_XLNA_ODD_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__BQ_GAIN_ODD_97___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__XLNA_GAIN_EVEN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__LNA_GAIN_EVEN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__GM_GAIN_EVEN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__TIA_GAIN_EVEN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__SLM_XLNA_EVEN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__BQ_GAIN_EVEN_97___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__XLNA_GAIN_ODD_97___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__XLNA_GAIN_ODD_97___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__LNA_GAIN_ODD_97___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__LNA_GAIN_ODD_97___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__GM_GAIN_ODD_97___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__GM_GAIN_ODD_97___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__TIA_GAIN_ODD_97___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__TIA_GAIN_ODD_97___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__SLM_XLNA_ODD_97___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__SLM_XLNA_ODD_97___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__BQ_GAIN_ODD_97___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__BQ_GAIN_ODD_97___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__XLNA_GAIN_EVEN_97___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__XLNA_GAIN_EVEN_97___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__LNA_GAIN_EVEN_97___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__LNA_GAIN_EVEN_97___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__GM_GAIN_EVEN_97___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__GM_GAIN_EVEN_97___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__TIA_GAIN_EVEN_97___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__TIA_GAIN_EVEN_97___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__SLM_XLNA_EVEN_97___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__SLM_XLNA_EVEN_97___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__BQ_GAIN_EVEN_97___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97__BQ_GAIN_EVEN_97___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_97___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98 (0x005E5188) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__XLNA_GAIN_ODD_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__LNA_GAIN_ODD_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__GM_GAIN_ODD_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__TIA_GAIN_ODD_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__SLM_XLNA_ODD_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__BQ_GAIN_ODD_98___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__XLNA_GAIN_EVEN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__LNA_GAIN_EVEN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__GM_GAIN_EVEN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__TIA_GAIN_EVEN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__SLM_XLNA_EVEN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__BQ_GAIN_EVEN_98___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__XLNA_GAIN_ODD_98___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__XLNA_GAIN_ODD_98___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__LNA_GAIN_ODD_98___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__LNA_GAIN_ODD_98___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__GM_GAIN_ODD_98___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__GM_GAIN_ODD_98___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__TIA_GAIN_ODD_98___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__TIA_GAIN_ODD_98___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__SLM_XLNA_ODD_98___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__SLM_XLNA_ODD_98___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__BQ_GAIN_ODD_98___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__BQ_GAIN_ODD_98___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__XLNA_GAIN_EVEN_98___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__XLNA_GAIN_EVEN_98___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__LNA_GAIN_EVEN_98___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__LNA_GAIN_EVEN_98___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__GM_GAIN_EVEN_98___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__GM_GAIN_EVEN_98___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__TIA_GAIN_EVEN_98___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__TIA_GAIN_EVEN_98___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__SLM_XLNA_EVEN_98___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__SLM_XLNA_EVEN_98___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__BQ_GAIN_EVEN_98___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98__BQ_GAIN_EVEN_98___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_98___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99 (0x005E518C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__XLNA_GAIN_ODD_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__LNA_GAIN_ODD_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__GM_GAIN_ODD_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__TIA_GAIN_ODD_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__SLM_XLNA_ODD_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__BQ_GAIN_ODD_99___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__XLNA_GAIN_EVEN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__LNA_GAIN_EVEN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__GM_GAIN_EVEN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__TIA_GAIN_EVEN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__SLM_XLNA_EVEN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__BQ_GAIN_EVEN_99___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__XLNA_GAIN_ODD_99___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__XLNA_GAIN_ODD_99___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__LNA_GAIN_ODD_99___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__LNA_GAIN_ODD_99___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__GM_GAIN_ODD_99___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__GM_GAIN_ODD_99___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__TIA_GAIN_ODD_99___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__TIA_GAIN_ODD_99___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__SLM_XLNA_ODD_99___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__SLM_XLNA_ODD_99___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__BQ_GAIN_ODD_99___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__BQ_GAIN_ODD_99___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__XLNA_GAIN_EVEN_99___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__XLNA_GAIN_EVEN_99___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__LNA_GAIN_EVEN_99___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__LNA_GAIN_EVEN_99___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__GM_GAIN_EVEN_99___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__GM_GAIN_EVEN_99___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__TIA_GAIN_EVEN_99___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__TIA_GAIN_EVEN_99___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__SLM_XLNA_EVEN_99___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__SLM_XLNA_EVEN_99___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__BQ_GAIN_EVEN_99___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99__BQ_GAIN_EVEN_99___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_99___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100 (0x005E5190) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__XLNA_GAIN_ODD_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__LNA_GAIN_ODD_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__GM_GAIN_ODD_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__TIA_GAIN_ODD_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__SLM_XLNA_ODD_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__BQ_GAIN_ODD_100___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__XLNA_GAIN_EVEN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__LNA_GAIN_EVEN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__GM_GAIN_EVEN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__TIA_GAIN_EVEN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__SLM_XLNA_EVEN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__BQ_GAIN_EVEN_100___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__XLNA_GAIN_ODD_100___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__XLNA_GAIN_ODD_100___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__LNA_GAIN_ODD_100___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__LNA_GAIN_ODD_100___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__GM_GAIN_ODD_100___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__GM_GAIN_ODD_100___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__TIA_GAIN_ODD_100___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__TIA_GAIN_ODD_100___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__SLM_XLNA_ODD_100___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__SLM_XLNA_ODD_100___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__BQ_GAIN_ODD_100___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__BQ_GAIN_ODD_100___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__XLNA_GAIN_EVEN_100___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__XLNA_GAIN_EVEN_100___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__LNA_GAIN_EVEN_100___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__LNA_GAIN_EVEN_100___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__GM_GAIN_EVEN_100___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__GM_GAIN_EVEN_100___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__TIA_GAIN_EVEN_100___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__TIA_GAIN_EVEN_100___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__SLM_XLNA_EVEN_100___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__SLM_XLNA_EVEN_100___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__BQ_GAIN_EVEN_100___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100__BQ_GAIN_EVEN_100___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_100___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101 (0x005E5194) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__XLNA_GAIN_ODD_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__LNA_GAIN_ODD_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__GM_GAIN_ODD_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__TIA_GAIN_ODD_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__SLM_XLNA_ODD_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__BQ_GAIN_ODD_101___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__XLNA_GAIN_EVEN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__LNA_GAIN_EVEN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__GM_GAIN_EVEN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__TIA_GAIN_EVEN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__SLM_XLNA_EVEN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__BQ_GAIN_EVEN_101___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__XLNA_GAIN_ODD_101___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__XLNA_GAIN_ODD_101___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__LNA_GAIN_ODD_101___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__LNA_GAIN_ODD_101___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__GM_GAIN_ODD_101___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__GM_GAIN_ODD_101___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__TIA_GAIN_ODD_101___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__TIA_GAIN_ODD_101___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__SLM_XLNA_ODD_101___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__SLM_XLNA_ODD_101___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__BQ_GAIN_ODD_101___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__BQ_GAIN_ODD_101___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__XLNA_GAIN_EVEN_101___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__XLNA_GAIN_EVEN_101___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__LNA_GAIN_EVEN_101___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__LNA_GAIN_EVEN_101___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__GM_GAIN_EVEN_101___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__GM_GAIN_EVEN_101___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__TIA_GAIN_EVEN_101___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__TIA_GAIN_EVEN_101___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__SLM_XLNA_EVEN_101___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__SLM_XLNA_EVEN_101___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__BQ_GAIN_EVEN_101___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101__BQ_GAIN_EVEN_101___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_101___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102 (0x005E5198) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__XLNA_GAIN_ODD_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__LNA_GAIN_ODD_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__GM_GAIN_ODD_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__TIA_GAIN_ODD_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__SLM_XLNA_ODD_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__BQ_GAIN_ODD_102___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__XLNA_GAIN_EVEN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__LNA_GAIN_EVEN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__GM_GAIN_EVEN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__TIA_GAIN_EVEN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__SLM_XLNA_EVEN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__BQ_GAIN_EVEN_102___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__XLNA_GAIN_ODD_102___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__XLNA_GAIN_ODD_102___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__LNA_GAIN_ODD_102___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__LNA_GAIN_ODD_102___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__GM_GAIN_ODD_102___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__GM_GAIN_ODD_102___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__TIA_GAIN_ODD_102___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__TIA_GAIN_ODD_102___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__SLM_XLNA_ODD_102___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__SLM_XLNA_ODD_102___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__BQ_GAIN_ODD_102___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__BQ_GAIN_ODD_102___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__XLNA_GAIN_EVEN_102___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__XLNA_GAIN_EVEN_102___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__LNA_GAIN_EVEN_102___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__LNA_GAIN_EVEN_102___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__GM_GAIN_EVEN_102___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__GM_GAIN_EVEN_102___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__TIA_GAIN_EVEN_102___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__TIA_GAIN_EVEN_102___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__SLM_XLNA_EVEN_102___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__SLM_XLNA_EVEN_102___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__BQ_GAIN_EVEN_102___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102__BQ_GAIN_EVEN_102___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_102___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103 (0x005E519C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__XLNA_GAIN_ODD_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__LNA_GAIN_ODD_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__GM_GAIN_ODD_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__TIA_GAIN_ODD_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__SLM_XLNA_ODD_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__BQ_GAIN_ODD_103___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__XLNA_GAIN_EVEN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__LNA_GAIN_EVEN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__GM_GAIN_EVEN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__TIA_GAIN_EVEN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__SLM_XLNA_EVEN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__BQ_GAIN_EVEN_103___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__XLNA_GAIN_ODD_103___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__XLNA_GAIN_ODD_103___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__LNA_GAIN_ODD_103___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__LNA_GAIN_ODD_103___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__GM_GAIN_ODD_103___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__GM_GAIN_ODD_103___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__TIA_GAIN_ODD_103___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__TIA_GAIN_ODD_103___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__SLM_XLNA_ODD_103___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__SLM_XLNA_ODD_103___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__BQ_GAIN_ODD_103___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__BQ_GAIN_ODD_103___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__XLNA_GAIN_EVEN_103___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__XLNA_GAIN_EVEN_103___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__LNA_GAIN_EVEN_103___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__LNA_GAIN_EVEN_103___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__GM_GAIN_EVEN_103___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__GM_GAIN_EVEN_103___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__TIA_GAIN_EVEN_103___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__TIA_GAIN_EVEN_103___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__SLM_XLNA_EVEN_103___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__SLM_XLNA_EVEN_103___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__BQ_GAIN_EVEN_103___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103__BQ_GAIN_EVEN_103___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_103___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104 (0x005E51A0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__XLNA_GAIN_ODD_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__LNA_GAIN_ODD_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__GM_GAIN_ODD_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__TIA_GAIN_ODD_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__SLM_XLNA_ODD_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__BQ_GAIN_ODD_104___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__XLNA_GAIN_EVEN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__LNA_GAIN_EVEN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__GM_GAIN_EVEN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__TIA_GAIN_EVEN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__SLM_XLNA_EVEN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__BQ_GAIN_EVEN_104___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__XLNA_GAIN_ODD_104___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__XLNA_GAIN_ODD_104___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__LNA_GAIN_ODD_104___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__LNA_GAIN_ODD_104___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__GM_GAIN_ODD_104___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__GM_GAIN_ODD_104___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__TIA_GAIN_ODD_104___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__TIA_GAIN_ODD_104___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__SLM_XLNA_ODD_104___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__SLM_XLNA_ODD_104___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__BQ_GAIN_ODD_104___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__BQ_GAIN_ODD_104___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__XLNA_GAIN_EVEN_104___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__XLNA_GAIN_EVEN_104___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__LNA_GAIN_EVEN_104___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__LNA_GAIN_EVEN_104___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__GM_GAIN_EVEN_104___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__GM_GAIN_EVEN_104___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__TIA_GAIN_EVEN_104___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__TIA_GAIN_EVEN_104___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__SLM_XLNA_EVEN_104___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__SLM_XLNA_EVEN_104___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__BQ_GAIN_EVEN_104___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104__BQ_GAIN_EVEN_104___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_104___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105 (0x005E51A4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__XLNA_GAIN_ODD_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__LNA_GAIN_ODD_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__GM_GAIN_ODD_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__TIA_GAIN_ODD_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__SLM_XLNA_ODD_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__BQ_GAIN_ODD_105___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__XLNA_GAIN_EVEN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__LNA_GAIN_EVEN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__GM_GAIN_EVEN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__TIA_GAIN_EVEN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__SLM_XLNA_EVEN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__BQ_GAIN_EVEN_105___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__XLNA_GAIN_ODD_105___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__XLNA_GAIN_ODD_105___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__LNA_GAIN_ODD_105___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__LNA_GAIN_ODD_105___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__GM_GAIN_ODD_105___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__GM_GAIN_ODD_105___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__TIA_GAIN_ODD_105___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__TIA_GAIN_ODD_105___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__SLM_XLNA_ODD_105___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__SLM_XLNA_ODD_105___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__BQ_GAIN_ODD_105___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__BQ_GAIN_ODD_105___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__XLNA_GAIN_EVEN_105___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__XLNA_GAIN_EVEN_105___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__LNA_GAIN_EVEN_105___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__LNA_GAIN_EVEN_105___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__GM_GAIN_EVEN_105___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__GM_GAIN_EVEN_105___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__TIA_GAIN_EVEN_105___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__TIA_GAIN_EVEN_105___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__SLM_XLNA_EVEN_105___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__SLM_XLNA_EVEN_105___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__BQ_GAIN_EVEN_105___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105__BQ_GAIN_EVEN_105___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_105___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106 (0x005E51A8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__XLNA_GAIN_ODD_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__LNA_GAIN_ODD_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__GM_GAIN_ODD_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__TIA_GAIN_ODD_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__SLM_XLNA_ODD_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__BQ_GAIN_ODD_106___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__XLNA_GAIN_EVEN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__LNA_GAIN_EVEN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__GM_GAIN_EVEN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__TIA_GAIN_EVEN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__SLM_XLNA_EVEN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__BQ_GAIN_EVEN_106___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__XLNA_GAIN_ODD_106___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__XLNA_GAIN_ODD_106___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__LNA_GAIN_ODD_106___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__LNA_GAIN_ODD_106___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__GM_GAIN_ODD_106___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__GM_GAIN_ODD_106___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__TIA_GAIN_ODD_106___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__TIA_GAIN_ODD_106___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__SLM_XLNA_ODD_106___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__SLM_XLNA_ODD_106___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__BQ_GAIN_ODD_106___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__BQ_GAIN_ODD_106___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__XLNA_GAIN_EVEN_106___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__XLNA_GAIN_EVEN_106___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__LNA_GAIN_EVEN_106___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__LNA_GAIN_EVEN_106___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__GM_GAIN_EVEN_106___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__GM_GAIN_EVEN_106___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__TIA_GAIN_EVEN_106___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__TIA_GAIN_EVEN_106___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__SLM_XLNA_EVEN_106___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__SLM_XLNA_EVEN_106___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__BQ_GAIN_EVEN_106___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106__BQ_GAIN_EVEN_106___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_106___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107 (0x005E51AC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__XLNA_GAIN_ODD_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__LNA_GAIN_ODD_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__GM_GAIN_ODD_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__TIA_GAIN_ODD_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__SLM_XLNA_ODD_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__BQ_GAIN_ODD_107___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__XLNA_GAIN_EVEN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__LNA_GAIN_EVEN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__GM_GAIN_EVEN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__TIA_GAIN_EVEN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__SLM_XLNA_EVEN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__BQ_GAIN_EVEN_107___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__XLNA_GAIN_ODD_107___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__XLNA_GAIN_ODD_107___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__LNA_GAIN_ODD_107___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__LNA_GAIN_ODD_107___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__GM_GAIN_ODD_107___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__GM_GAIN_ODD_107___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__TIA_GAIN_ODD_107___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__TIA_GAIN_ODD_107___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__SLM_XLNA_ODD_107___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__SLM_XLNA_ODD_107___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__BQ_GAIN_ODD_107___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__BQ_GAIN_ODD_107___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__XLNA_GAIN_EVEN_107___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__XLNA_GAIN_EVEN_107___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__LNA_GAIN_EVEN_107___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__LNA_GAIN_EVEN_107___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__GM_GAIN_EVEN_107___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__GM_GAIN_EVEN_107___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__TIA_GAIN_EVEN_107___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__TIA_GAIN_EVEN_107___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__SLM_XLNA_EVEN_107___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__SLM_XLNA_EVEN_107___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__BQ_GAIN_EVEN_107___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107__BQ_GAIN_EVEN_107___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_107___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108 (0x005E51B0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__XLNA_GAIN_ODD_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__LNA_GAIN_ODD_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__GM_GAIN_ODD_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__TIA_GAIN_ODD_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__SLM_XLNA_ODD_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__BQ_GAIN_ODD_108___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__XLNA_GAIN_EVEN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__LNA_GAIN_EVEN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__GM_GAIN_EVEN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__TIA_GAIN_EVEN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__SLM_XLNA_EVEN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__BQ_GAIN_EVEN_108___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__XLNA_GAIN_ODD_108___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__XLNA_GAIN_ODD_108___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__LNA_GAIN_ODD_108___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__LNA_GAIN_ODD_108___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__GM_GAIN_ODD_108___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__GM_GAIN_ODD_108___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__TIA_GAIN_ODD_108___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__TIA_GAIN_ODD_108___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__SLM_XLNA_ODD_108___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__SLM_XLNA_ODD_108___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__BQ_GAIN_ODD_108___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__BQ_GAIN_ODD_108___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__XLNA_GAIN_EVEN_108___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__XLNA_GAIN_EVEN_108___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__LNA_GAIN_EVEN_108___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__LNA_GAIN_EVEN_108___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__GM_GAIN_EVEN_108___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__GM_GAIN_EVEN_108___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__TIA_GAIN_EVEN_108___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__TIA_GAIN_EVEN_108___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__SLM_XLNA_EVEN_108___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__SLM_XLNA_EVEN_108___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__BQ_GAIN_EVEN_108___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108__BQ_GAIN_EVEN_108___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_108___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109 (0x005E51B4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__XLNA_GAIN_ODD_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__LNA_GAIN_ODD_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__GM_GAIN_ODD_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__TIA_GAIN_ODD_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__SLM_XLNA_ODD_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__BQ_GAIN_ODD_109___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__XLNA_GAIN_EVEN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__LNA_GAIN_EVEN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__GM_GAIN_EVEN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__TIA_GAIN_EVEN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__SLM_XLNA_EVEN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__BQ_GAIN_EVEN_109___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__XLNA_GAIN_ODD_109___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__XLNA_GAIN_ODD_109___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__LNA_GAIN_ODD_109___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__LNA_GAIN_ODD_109___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__GM_GAIN_ODD_109___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__GM_GAIN_ODD_109___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__TIA_GAIN_ODD_109___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__TIA_GAIN_ODD_109___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__SLM_XLNA_ODD_109___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__SLM_XLNA_ODD_109___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__BQ_GAIN_ODD_109___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__BQ_GAIN_ODD_109___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__XLNA_GAIN_EVEN_109___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__XLNA_GAIN_EVEN_109___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__LNA_GAIN_EVEN_109___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__LNA_GAIN_EVEN_109___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__GM_GAIN_EVEN_109___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__GM_GAIN_EVEN_109___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__TIA_GAIN_EVEN_109___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__TIA_GAIN_EVEN_109___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__SLM_XLNA_EVEN_109___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__SLM_XLNA_EVEN_109___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__BQ_GAIN_EVEN_109___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109__BQ_GAIN_EVEN_109___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_109___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110 (0x005E51B8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__XLNA_GAIN_ODD_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__LNA_GAIN_ODD_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__GM_GAIN_ODD_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__TIA_GAIN_ODD_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__SLM_XLNA_ODD_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__BQ_GAIN_ODD_110___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__XLNA_GAIN_EVEN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__LNA_GAIN_EVEN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__GM_GAIN_EVEN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__TIA_GAIN_EVEN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__SLM_XLNA_EVEN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__BQ_GAIN_EVEN_110___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__XLNA_GAIN_ODD_110___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__XLNA_GAIN_ODD_110___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__LNA_GAIN_ODD_110___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__LNA_GAIN_ODD_110___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__GM_GAIN_ODD_110___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__GM_GAIN_ODD_110___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__TIA_GAIN_ODD_110___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__TIA_GAIN_ODD_110___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__SLM_XLNA_ODD_110___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__SLM_XLNA_ODD_110___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__BQ_GAIN_ODD_110___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__BQ_GAIN_ODD_110___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__XLNA_GAIN_EVEN_110___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__XLNA_GAIN_EVEN_110___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__LNA_GAIN_EVEN_110___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__LNA_GAIN_EVEN_110___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__GM_GAIN_EVEN_110___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__GM_GAIN_EVEN_110___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__TIA_GAIN_EVEN_110___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__TIA_GAIN_EVEN_110___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__SLM_XLNA_EVEN_110___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__SLM_XLNA_EVEN_110___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__BQ_GAIN_EVEN_110___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110__BQ_GAIN_EVEN_110___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_110___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111 (0x005E51BC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__XLNA_GAIN_ODD_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__LNA_GAIN_ODD_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__GM_GAIN_ODD_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__TIA_GAIN_ODD_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__SLM_XLNA_ODD_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__BQ_GAIN_ODD_111___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__XLNA_GAIN_EVEN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__LNA_GAIN_EVEN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__GM_GAIN_EVEN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__TIA_GAIN_EVEN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__SLM_XLNA_EVEN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__BQ_GAIN_EVEN_111___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__XLNA_GAIN_ODD_111___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__XLNA_GAIN_ODD_111___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__LNA_GAIN_ODD_111___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__LNA_GAIN_ODD_111___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__GM_GAIN_ODD_111___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__GM_GAIN_ODD_111___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__TIA_GAIN_ODD_111___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__TIA_GAIN_ODD_111___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__SLM_XLNA_ODD_111___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__SLM_XLNA_ODD_111___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__BQ_GAIN_ODD_111___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__BQ_GAIN_ODD_111___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__XLNA_GAIN_EVEN_111___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__XLNA_GAIN_EVEN_111___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__LNA_GAIN_EVEN_111___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__LNA_GAIN_EVEN_111___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__GM_GAIN_EVEN_111___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__GM_GAIN_EVEN_111___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__TIA_GAIN_EVEN_111___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__TIA_GAIN_EVEN_111___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__SLM_XLNA_EVEN_111___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__SLM_XLNA_EVEN_111___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__BQ_GAIN_EVEN_111___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111__BQ_GAIN_EVEN_111___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_111___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112 (0x005E51C0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__XLNA_GAIN_ODD_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__LNA_GAIN_ODD_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__GM_GAIN_ODD_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__TIA_GAIN_ODD_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__SLM_XLNA_ODD_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__BQ_GAIN_ODD_112___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__XLNA_GAIN_EVEN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__LNA_GAIN_EVEN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__GM_GAIN_EVEN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__TIA_GAIN_EVEN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__SLM_XLNA_EVEN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__BQ_GAIN_EVEN_112___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__XLNA_GAIN_ODD_112___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__XLNA_GAIN_ODD_112___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__LNA_GAIN_ODD_112___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__LNA_GAIN_ODD_112___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__GM_GAIN_ODD_112___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__GM_GAIN_ODD_112___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__TIA_GAIN_ODD_112___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__TIA_GAIN_ODD_112___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__SLM_XLNA_ODD_112___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__SLM_XLNA_ODD_112___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__BQ_GAIN_ODD_112___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__BQ_GAIN_ODD_112___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__XLNA_GAIN_EVEN_112___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__XLNA_GAIN_EVEN_112___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__LNA_GAIN_EVEN_112___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__LNA_GAIN_EVEN_112___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__GM_GAIN_EVEN_112___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__GM_GAIN_EVEN_112___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__TIA_GAIN_EVEN_112___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__TIA_GAIN_EVEN_112___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__SLM_XLNA_EVEN_112___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__SLM_XLNA_EVEN_112___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__BQ_GAIN_EVEN_112___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112__BQ_GAIN_EVEN_112___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_112___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113 (0x005E51C4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__XLNA_GAIN_ODD_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__LNA_GAIN_ODD_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__GM_GAIN_ODD_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__TIA_GAIN_ODD_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__SLM_XLNA_ODD_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__BQ_GAIN_ODD_113___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__XLNA_GAIN_EVEN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__LNA_GAIN_EVEN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__GM_GAIN_EVEN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__TIA_GAIN_EVEN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__SLM_XLNA_EVEN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__BQ_GAIN_EVEN_113___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__XLNA_GAIN_ODD_113___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__XLNA_GAIN_ODD_113___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__LNA_GAIN_ODD_113___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__LNA_GAIN_ODD_113___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__GM_GAIN_ODD_113___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__GM_GAIN_ODD_113___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__TIA_GAIN_ODD_113___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__TIA_GAIN_ODD_113___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__SLM_XLNA_ODD_113___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__SLM_XLNA_ODD_113___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__BQ_GAIN_ODD_113___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__BQ_GAIN_ODD_113___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__XLNA_GAIN_EVEN_113___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__XLNA_GAIN_EVEN_113___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__LNA_GAIN_EVEN_113___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__LNA_GAIN_EVEN_113___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__GM_GAIN_EVEN_113___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__GM_GAIN_EVEN_113___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__TIA_GAIN_EVEN_113___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__TIA_GAIN_EVEN_113___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__SLM_XLNA_EVEN_113___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__SLM_XLNA_EVEN_113___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__BQ_GAIN_EVEN_113___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113__BQ_GAIN_EVEN_113___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_113___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114 (0x005E51C8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__XLNA_GAIN_ODD_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__LNA_GAIN_ODD_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__GM_GAIN_ODD_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__TIA_GAIN_ODD_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__SLM_XLNA_ODD_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__BQ_GAIN_ODD_114___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__XLNA_GAIN_EVEN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__LNA_GAIN_EVEN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__GM_GAIN_EVEN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__TIA_GAIN_EVEN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__SLM_XLNA_EVEN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__BQ_GAIN_EVEN_114___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__XLNA_GAIN_ODD_114___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__XLNA_GAIN_ODD_114___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__LNA_GAIN_ODD_114___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__LNA_GAIN_ODD_114___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__GM_GAIN_ODD_114___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__GM_GAIN_ODD_114___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__TIA_GAIN_ODD_114___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__TIA_GAIN_ODD_114___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__SLM_XLNA_ODD_114___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__SLM_XLNA_ODD_114___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__BQ_GAIN_ODD_114___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__BQ_GAIN_ODD_114___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__XLNA_GAIN_EVEN_114___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__XLNA_GAIN_EVEN_114___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__LNA_GAIN_EVEN_114___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__LNA_GAIN_EVEN_114___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__GM_GAIN_EVEN_114___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__GM_GAIN_EVEN_114___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__TIA_GAIN_EVEN_114___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__TIA_GAIN_EVEN_114___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__SLM_XLNA_EVEN_114___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__SLM_XLNA_EVEN_114___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__BQ_GAIN_EVEN_114___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114__BQ_GAIN_EVEN_114___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_114___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115 (0x005E51CC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__XLNA_GAIN_ODD_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__LNA_GAIN_ODD_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__GM_GAIN_ODD_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__TIA_GAIN_ODD_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__SLM_XLNA_ODD_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__BQ_GAIN_ODD_115___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__XLNA_GAIN_EVEN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__LNA_GAIN_EVEN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__GM_GAIN_EVEN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__TIA_GAIN_EVEN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__SLM_XLNA_EVEN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__BQ_GAIN_EVEN_115___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__XLNA_GAIN_ODD_115___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__XLNA_GAIN_ODD_115___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__LNA_GAIN_ODD_115___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__LNA_GAIN_ODD_115___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__GM_GAIN_ODD_115___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__GM_GAIN_ODD_115___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__TIA_GAIN_ODD_115___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__TIA_GAIN_ODD_115___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__SLM_XLNA_ODD_115___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__SLM_XLNA_ODD_115___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__BQ_GAIN_ODD_115___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__BQ_GAIN_ODD_115___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__XLNA_GAIN_EVEN_115___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__XLNA_GAIN_EVEN_115___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__LNA_GAIN_EVEN_115___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__LNA_GAIN_EVEN_115___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__GM_GAIN_EVEN_115___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__GM_GAIN_EVEN_115___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__TIA_GAIN_EVEN_115___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__TIA_GAIN_EVEN_115___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__SLM_XLNA_EVEN_115___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__SLM_XLNA_EVEN_115___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__BQ_GAIN_EVEN_115___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115__BQ_GAIN_EVEN_115___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_115___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116 (0x005E51D0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__XLNA_GAIN_ODD_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__LNA_GAIN_ODD_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__GM_GAIN_ODD_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__TIA_GAIN_ODD_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__SLM_XLNA_ODD_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__BQ_GAIN_ODD_116___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__XLNA_GAIN_EVEN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__LNA_GAIN_EVEN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__GM_GAIN_EVEN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__TIA_GAIN_EVEN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__SLM_XLNA_EVEN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__BQ_GAIN_EVEN_116___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__XLNA_GAIN_ODD_116___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__XLNA_GAIN_ODD_116___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__LNA_GAIN_ODD_116___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__LNA_GAIN_ODD_116___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__GM_GAIN_ODD_116___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__GM_GAIN_ODD_116___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__TIA_GAIN_ODD_116___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__TIA_GAIN_ODD_116___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__SLM_XLNA_ODD_116___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__SLM_XLNA_ODD_116___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__BQ_GAIN_ODD_116___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__BQ_GAIN_ODD_116___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__XLNA_GAIN_EVEN_116___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__XLNA_GAIN_EVEN_116___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__LNA_GAIN_EVEN_116___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__LNA_GAIN_EVEN_116___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__GM_GAIN_EVEN_116___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__GM_GAIN_EVEN_116___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__TIA_GAIN_EVEN_116___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__TIA_GAIN_EVEN_116___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__SLM_XLNA_EVEN_116___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__SLM_XLNA_EVEN_116___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__BQ_GAIN_EVEN_116___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116__BQ_GAIN_EVEN_116___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_116___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117 (0x005E51D4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__XLNA_GAIN_ODD_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__LNA_GAIN_ODD_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__GM_GAIN_ODD_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__TIA_GAIN_ODD_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__SLM_XLNA_ODD_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__BQ_GAIN_ODD_117___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__XLNA_GAIN_EVEN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__LNA_GAIN_EVEN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__GM_GAIN_EVEN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__TIA_GAIN_EVEN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__SLM_XLNA_EVEN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__BQ_GAIN_EVEN_117___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__XLNA_GAIN_ODD_117___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__XLNA_GAIN_ODD_117___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__LNA_GAIN_ODD_117___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__LNA_GAIN_ODD_117___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__GM_GAIN_ODD_117___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__GM_GAIN_ODD_117___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__TIA_GAIN_ODD_117___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__TIA_GAIN_ODD_117___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__SLM_XLNA_ODD_117___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__SLM_XLNA_ODD_117___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__BQ_GAIN_ODD_117___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__BQ_GAIN_ODD_117___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__XLNA_GAIN_EVEN_117___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__XLNA_GAIN_EVEN_117___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__LNA_GAIN_EVEN_117___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__LNA_GAIN_EVEN_117___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__GM_GAIN_EVEN_117___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__GM_GAIN_EVEN_117___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__TIA_GAIN_EVEN_117___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__TIA_GAIN_EVEN_117___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__SLM_XLNA_EVEN_117___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__SLM_XLNA_EVEN_117___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__BQ_GAIN_EVEN_117___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117__BQ_GAIN_EVEN_117___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_117___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118 (0x005E51D8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__XLNA_GAIN_ODD_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__LNA_GAIN_ODD_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__GM_GAIN_ODD_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__TIA_GAIN_ODD_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__SLM_XLNA_ODD_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__BQ_GAIN_ODD_118___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__XLNA_GAIN_EVEN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__LNA_GAIN_EVEN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__GM_GAIN_EVEN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__TIA_GAIN_EVEN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__SLM_XLNA_EVEN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__BQ_GAIN_EVEN_118___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__XLNA_GAIN_ODD_118___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__XLNA_GAIN_ODD_118___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__LNA_GAIN_ODD_118___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__LNA_GAIN_ODD_118___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__GM_GAIN_ODD_118___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__GM_GAIN_ODD_118___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__TIA_GAIN_ODD_118___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__TIA_GAIN_ODD_118___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__SLM_XLNA_ODD_118___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__SLM_XLNA_ODD_118___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__BQ_GAIN_ODD_118___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__BQ_GAIN_ODD_118___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__XLNA_GAIN_EVEN_118___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__XLNA_GAIN_EVEN_118___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__LNA_GAIN_EVEN_118___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__LNA_GAIN_EVEN_118___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__GM_GAIN_EVEN_118___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__GM_GAIN_EVEN_118___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__TIA_GAIN_EVEN_118___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__TIA_GAIN_EVEN_118___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__SLM_XLNA_EVEN_118___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__SLM_XLNA_EVEN_118___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__BQ_GAIN_EVEN_118___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118__BQ_GAIN_EVEN_118___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_118___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119 (0x005E51DC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__XLNA_GAIN_ODD_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__LNA_GAIN_ODD_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__GM_GAIN_ODD_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__TIA_GAIN_ODD_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__SLM_XLNA_ODD_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__BQ_GAIN_ODD_119___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__XLNA_GAIN_EVEN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__LNA_GAIN_EVEN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__GM_GAIN_EVEN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__TIA_GAIN_EVEN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__SLM_XLNA_EVEN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__BQ_GAIN_EVEN_119___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__XLNA_GAIN_ODD_119___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__XLNA_GAIN_ODD_119___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__LNA_GAIN_ODD_119___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__LNA_GAIN_ODD_119___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__GM_GAIN_ODD_119___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__GM_GAIN_ODD_119___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__TIA_GAIN_ODD_119___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__TIA_GAIN_ODD_119___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__SLM_XLNA_ODD_119___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__SLM_XLNA_ODD_119___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__BQ_GAIN_ODD_119___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__BQ_GAIN_ODD_119___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__XLNA_GAIN_EVEN_119___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__XLNA_GAIN_EVEN_119___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__LNA_GAIN_EVEN_119___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__LNA_GAIN_EVEN_119___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__GM_GAIN_EVEN_119___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__GM_GAIN_EVEN_119___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__TIA_GAIN_EVEN_119___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__TIA_GAIN_EVEN_119___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__SLM_XLNA_EVEN_119___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__SLM_XLNA_EVEN_119___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__BQ_GAIN_EVEN_119___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119__BQ_GAIN_EVEN_119___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_119___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120 (0x005E51E0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__XLNA_GAIN_ODD_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__LNA_GAIN_ODD_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__GM_GAIN_ODD_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__TIA_GAIN_ODD_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__SLM_XLNA_ODD_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__BQ_GAIN_ODD_120___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__XLNA_GAIN_EVEN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__LNA_GAIN_EVEN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__GM_GAIN_EVEN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__TIA_GAIN_EVEN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__SLM_XLNA_EVEN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__BQ_GAIN_EVEN_120___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__XLNA_GAIN_ODD_120___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__XLNA_GAIN_ODD_120___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__LNA_GAIN_ODD_120___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__LNA_GAIN_ODD_120___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__GM_GAIN_ODD_120___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__GM_GAIN_ODD_120___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__TIA_GAIN_ODD_120___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__TIA_GAIN_ODD_120___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__SLM_XLNA_ODD_120___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__SLM_XLNA_ODD_120___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__BQ_GAIN_ODD_120___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__BQ_GAIN_ODD_120___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__XLNA_GAIN_EVEN_120___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__XLNA_GAIN_EVEN_120___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__LNA_GAIN_EVEN_120___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__LNA_GAIN_EVEN_120___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__GM_GAIN_EVEN_120___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__GM_GAIN_EVEN_120___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__TIA_GAIN_EVEN_120___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__TIA_GAIN_EVEN_120___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__SLM_XLNA_EVEN_120___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__SLM_XLNA_EVEN_120___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__BQ_GAIN_EVEN_120___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120__BQ_GAIN_EVEN_120___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_120___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121 (0x005E51E4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__XLNA_GAIN_ODD_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__LNA_GAIN_ODD_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__GM_GAIN_ODD_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__TIA_GAIN_ODD_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__SLM_XLNA_ODD_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__BQ_GAIN_ODD_121___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__XLNA_GAIN_EVEN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__LNA_GAIN_EVEN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__GM_GAIN_EVEN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__TIA_GAIN_EVEN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__SLM_XLNA_EVEN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__BQ_GAIN_EVEN_121___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__XLNA_GAIN_ODD_121___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__XLNA_GAIN_ODD_121___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__LNA_GAIN_ODD_121___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__LNA_GAIN_ODD_121___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__GM_GAIN_ODD_121___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__GM_GAIN_ODD_121___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__TIA_GAIN_ODD_121___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__TIA_GAIN_ODD_121___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__SLM_XLNA_ODD_121___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__SLM_XLNA_ODD_121___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__BQ_GAIN_ODD_121___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__BQ_GAIN_ODD_121___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__XLNA_GAIN_EVEN_121___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__XLNA_GAIN_EVEN_121___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__LNA_GAIN_EVEN_121___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__LNA_GAIN_EVEN_121___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__GM_GAIN_EVEN_121___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__GM_GAIN_EVEN_121___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__TIA_GAIN_EVEN_121___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__TIA_GAIN_EVEN_121___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__SLM_XLNA_EVEN_121___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__SLM_XLNA_EVEN_121___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__BQ_GAIN_EVEN_121___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121__BQ_GAIN_EVEN_121___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_121___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122 (0x005E51E8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__XLNA_GAIN_ODD_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__LNA_GAIN_ODD_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__GM_GAIN_ODD_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__TIA_GAIN_ODD_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__SLM_XLNA_ODD_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__BQ_GAIN_ODD_122___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__XLNA_GAIN_EVEN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__LNA_GAIN_EVEN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__GM_GAIN_EVEN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__TIA_GAIN_EVEN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__SLM_XLNA_EVEN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__BQ_GAIN_EVEN_122___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__XLNA_GAIN_ODD_122___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__XLNA_GAIN_ODD_122___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__LNA_GAIN_ODD_122___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__LNA_GAIN_ODD_122___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__GM_GAIN_ODD_122___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__GM_GAIN_ODD_122___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__TIA_GAIN_ODD_122___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__TIA_GAIN_ODD_122___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__SLM_XLNA_ODD_122___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__SLM_XLNA_ODD_122___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__BQ_GAIN_ODD_122___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__BQ_GAIN_ODD_122___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__XLNA_GAIN_EVEN_122___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__XLNA_GAIN_EVEN_122___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__LNA_GAIN_EVEN_122___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__LNA_GAIN_EVEN_122___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__GM_GAIN_EVEN_122___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__GM_GAIN_EVEN_122___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__TIA_GAIN_EVEN_122___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__TIA_GAIN_EVEN_122___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__SLM_XLNA_EVEN_122___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__SLM_XLNA_EVEN_122___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__BQ_GAIN_EVEN_122___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122__BQ_GAIN_EVEN_122___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_122___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123 (0x005E51EC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__XLNA_GAIN_ODD_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__LNA_GAIN_ODD_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__GM_GAIN_ODD_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__TIA_GAIN_ODD_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__SLM_XLNA_ODD_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__BQ_GAIN_ODD_123___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__XLNA_GAIN_EVEN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__LNA_GAIN_EVEN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__GM_GAIN_EVEN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__TIA_GAIN_EVEN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__SLM_XLNA_EVEN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__BQ_GAIN_EVEN_123___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__XLNA_GAIN_ODD_123___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__XLNA_GAIN_ODD_123___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__LNA_GAIN_ODD_123___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__LNA_GAIN_ODD_123___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__GM_GAIN_ODD_123___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__GM_GAIN_ODD_123___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__TIA_GAIN_ODD_123___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__TIA_GAIN_ODD_123___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__SLM_XLNA_ODD_123___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__SLM_XLNA_ODD_123___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__BQ_GAIN_ODD_123___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__BQ_GAIN_ODD_123___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__XLNA_GAIN_EVEN_123___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__XLNA_GAIN_EVEN_123___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__LNA_GAIN_EVEN_123___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__LNA_GAIN_EVEN_123___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__GM_GAIN_EVEN_123___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__GM_GAIN_EVEN_123___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__TIA_GAIN_EVEN_123___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__TIA_GAIN_EVEN_123___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__SLM_XLNA_EVEN_123___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__SLM_XLNA_EVEN_123___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__BQ_GAIN_EVEN_123___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123__BQ_GAIN_EVEN_123___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_123___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124 (0x005E51F0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__XLNA_GAIN_ODD_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__LNA_GAIN_ODD_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__GM_GAIN_ODD_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__TIA_GAIN_ODD_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__SLM_XLNA_ODD_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__BQ_GAIN_ODD_124___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__XLNA_GAIN_EVEN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__LNA_GAIN_EVEN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__GM_GAIN_EVEN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__TIA_GAIN_EVEN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__SLM_XLNA_EVEN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__BQ_GAIN_EVEN_124___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__XLNA_GAIN_ODD_124___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__XLNA_GAIN_ODD_124___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__LNA_GAIN_ODD_124___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__LNA_GAIN_ODD_124___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__GM_GAIN_ODD_124___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__GM_GAIN_ODD_124___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__TIA_GAIN_ODD_124___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__TIA_GAIN_ODD_124___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__SLM_XLNA_ODD_124___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__SLM_XLNA_ODD_124___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__BQ_GAIN_ODD_124___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__BQ_GAIN_ODD_124___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__XLNA_GAIN_EVEN_124___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__XLNA_GAIN_EVEN_124___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__LNA_GAIN_EVEN_124___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__LNA_GAIN_EVEN_124___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__GM_GAIN_EVEN_124___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__GM_GAIN_EVEN_124___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__TIA_GAIN_EVEN_124___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__TIA_GAIN_EVEN_124___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__SLM_XLNA_EVEN_124___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__SLM_XLNA_EVEN_124___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__BQ_GAIN_EVEN_124___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124__BQ_GAIN_EVEN_124___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_124___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125 (0x005E51F4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__XLNA_GAIN_ODD_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__LNA_GAIN_ODD_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__GM_GAIN_ODD_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__TIA_GAIN_ODD_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__SLM_XLNA_ODD_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__BQ_GAIN_ODD_125___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__XLNA_GAIN_EVEN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__LNA_GAIN_EVEN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__GM_GAIN_EVEN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__TIA_GAIN_EVEN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__SLM_XLNA_EVEN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__BQ_GAIN_EVEN_125___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__XLNA_GAIN_ODD_125___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__XLNA_GAIN_ODD_125___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__LNA_GAIN_ODD_125___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__LNA_GAIN_ODD_125___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__GM_GAIN_ODD_125___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__GM_GAIN_ODD_125___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__TIA_GAIN_ODD_125___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__TIA_GAIN_ODD_125___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__SLM_XLNA_ODD_125___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__SLM_XLNA_ODD_125___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__BQ_GAIN_ODD_125___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__BQ_GAIN_ODD_125___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__XLNA_GAIN_EVEN_125___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__XLNA_GAIN_EVEN_125___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__LNA_GAIN_EVEN_125___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__LNA_GAIN_EVEN_125___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__GM_GAIN_EVEN_125___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__GM_GAIN_EVEN_125___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__TIA_GAIN_EVEN_125___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__TIA_GAIN_EVEN_125___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__SLM_XLNA_EVEN_125___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__SLM_XLNA_EVEN_125___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__BQ_GAIN_EVEN_125___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125__BQ_GAIN_EVEN_125___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_125___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126 (0x005E51F8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__XLNA_GAIN_ODD_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__LNA_GAIN_ODD_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__GM_GAIN_ODD_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__TIA_GAIN_ODD_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__SLM_XLNA_ODD_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__BQ_GAIN_ODD_126___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__XLNA_GAIN_EVEN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__LNA_GAIN_EVEN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__GM_GAIN_EVEN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__TIA_GAIN_EVEN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__SLM_XLNA_EVEN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__BQ_GAIN_EVEN_126___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__XLNA_GAIN_ODD_126___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__XLNA_GAIN_ODD_126___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__LNA_GAIN_ODD_126___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__LNA_GAIN_ODD_126___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__GM_GAIN_ODD_126___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__GM_GAIN_ODD_126___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__TIA_GAIN_ODD_126___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__TIA_GAIN_ODD_126___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__SLM_XLNA_ODD_126___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__SLM_XLNA_ODD_126___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__BQ_GAIN_ODD_126___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__BQ_GAIN_ODD_126___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__XLNA_GAIN_EVEN_126___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__XLNA_GAIN_EVEN_126___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__LNA_GAIN_EVEN_126___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__LNA_GAIN_EVEN_126___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__GM_GAIN_EVEN_126___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__GM_GAIN_EVEN_126___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__TIA_GAIN_EVEN_126___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__TIA_GAIN_EVEN_126___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__SLM_XLNA_EVEN_126___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__SLM_XLNA_EVEN_126___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__BQ_GAIN_EVEN_126___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126__BQ_GAIN_EVEN_126___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_126___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127 (0x005E51FC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__XLNA_GAIN_ODD_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__LNA_GAIN_ODD_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__GM_GAIN_ODD_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__TIA_GAIN_ODD_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__SLM_XLNA_ODD_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__BQ_GAIN_ODD_127___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__XLNA_GAIN_EVEN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__LNA_GAIN_EVEN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__GM_GAIN_EVEN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__TIA_GAIN_EVEN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__SLM_XLNA_EVEN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__BQ_GAIN_EVEN_127___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__XLNA_GAIN_ODD_127___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__XLNA_GAIN_ODD_127___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__LNA_GAIN_ODD_127___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__LNA_GAIN_ODD_127___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__GM_GAIN_ODD_127___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__GM_GAIN_ODD_127___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__TIA_GAIN_ODD_127___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__TIA_GAIN_ODD_127___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__SLM_XLNA_ODD_127___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__SLM_XLNA_ODD_127___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__BQ_GAIN_ODD_127___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__BQ_GAIN_ODD_127___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__XLNA_GAIN_EVEN_127___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__XLNA_GAIN_EVEN_127___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__LNA_GAIN_EVEN_127___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__LNA_GAIN_EVEN_127___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__GM_GAIN_EVEN_127___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__GM_GAIN_EVEN_127___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__TIA_GAIN_EVEN_127___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__TIA_GAIN_EVEN_127___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__SLM_XLNA_EVEN_127___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__SLM_XLNA_EVEN_127___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__BQ_GAIN_EVEN_127___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127__BQ_GAIN_EVEN_127___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_127___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128 (0x005E5200) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__XLNA_GAIN_ODD_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__LNA_GAIN_ODD_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__GM_GAIN_ODD_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__TIA_GAIN_ODD_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__SLM_XLNA_ODD_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__BQ_GAIN_ODD_128___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__XLNA_GAIN_EVEN_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__LNA_GAIN_EVEN_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__GM_GAIN_EVEN_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__TIA_GAIN_EVEN_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__SLM_XLNA_EVEN_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__BQ_GAIN_EVEN_128___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__XLNA_GAIN_ODD_128___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__XLNA_GAIN_ODD_128___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__LNA_GAIN_ODD_128___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__LNA_GAIN_ODD_128___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__GM_GAIN_ODD_128___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__GM_GAIN_ODD_128___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__TIA_GAIN_ODD_128___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__TIA_GAIN_ODD_128___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__SLM_XLNA_ODD_128___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__SLM_XLNA_ODD_128___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__BQ_GAIN_ODD_128___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__BQ_GAIN_ODD_128___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__XLNA_GAIN_EVEN_128___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__XLNA_GAIN_EVEN_128___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__LNA_GAIN_EVEN_128___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__LNA_GAIN_EVEN_128___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__GM_GAIN_EVEN_128___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__GM_GAIN_EVEN_128___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__TIA_GAIN_EVEN_128___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__TIA_GAIN_EVEN_128___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__SLM_XLNA_EVEN_128___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__SLM_XLNA_EVEN_128___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__BQ_GAIN_EVEN_128___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128__BQ_GAIN_EVEN_128___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_128___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129 (0x005E5204) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__XLNA_GAIN_ODD_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__LNA_GAIN_ODD_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__GM_GAIN_ODD_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__TIA_GAIN_ODD_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__SLM_XLNA_ODD_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__BQ_GAIN_ODD_129___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__XLNA_GAIN_EVEN_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__LNA_GAIN_EVEN_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__GM_GAIN_EVEN_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__TIA_GAIN_EVEN_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__SLM_XLNA_EVEN_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__BQ_GAIN_EVEN_129___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__XLNA_GAIN_ODD_129___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__XLNA_GAIN_ODD_129___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__LNA_GAIN_ODD_129___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__LNA_GAIN_ODD_129___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__GM_GAIN_ODD_129___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__GM_GAIN_ODD_129___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__TIA_GAIN_ODD_129___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__TIA_GAIN_ODD_129___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__SLM_XLNA_ODD_129___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__SLM_XLNA_ODD_129___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__BQ_GAIN_ODD_129___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__BQ_GAIN_ODD_129___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__XLNA_GAIN_EVEN_129___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__XLNA_GAIN_EVEN_129___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__LNA_GAIN_EVEN_129___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__LNA_GAIN_EVEN_129___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__GM_GAIN_EVEN_129___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__GM_GAIN_EVEN_129___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__TIA_GAIN_EVEN_129___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__TIA_GAIN_EVEN_129___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__SLM_XLNA_EVEN_129___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__SLM_XLNA_EVEN_129___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__BQ_GAIN_EVEN_129___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129__BQ_GAIN_EVEN_129___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_129___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130 (0x005E5208) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__XLNA_GAIN_ODD_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__LNA_GAIN_ODD_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__GM_GAIN_ODD_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__TIA_GAIN_ODD_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__SLM_XLNA_ODD_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__BQ_GAIN_ODD_130___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__XLNA_GAIN_EVEN_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__LNA_GAIN_EVEN_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__GM_GAIN_EVEN_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__TIA_GAIN_EVEN_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__SLM_XLNA_EVEN_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__BQ_GAIN_EVEN_130___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__XLNA_GAIN_ODD_130___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__XLNA_GAIN_ODD_130___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__LNA_GAIN_ODD_130___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__LNA_GAIN_ODD_130___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__GM_GAIN_ODD_130___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__GM_GAIN_ODD_130___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__TIA_GAIN_ODD_130___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__TIA_GAIN_ODD_130___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__SLM_XLNA_ODD_130___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__SLM_XLNA_ODD_130___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__BQ_GAIN_ODD_130___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__BQ_GAIN_ODD_130___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__XLNA_GAIN_EVEN_130___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__XLNA_GAIN_EVEN_130___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__LNA_GAIN_EVEN_130___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__LNA_GAIN_EVEN_130___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__GM_GAIN_EVEN_130___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__GM_GAIN_EVEN_130___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__TIA_GAIN_EVEN_130___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__TIA_GAIN_EVEN_130___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__SLM_XLNA_EVEN_130___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__SLM_XLNA_EVEN_130___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__BQ_GAIN_EVEN_130___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130__BQ_GAIN_EVEN_130___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_130___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131 (0x005E520C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__XLNA_GAIN_ODD_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__LNA_GAIN_ODD_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__GM_GAIN_ODD_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__TIA_GAIN_ODD_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__SLM_XLNA_ODD_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__BQ_GAIN_ODD_131___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__XLNA_GAIN_EVEN_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__LNA_GAIN_EVEN_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__GM_GAIN_EVEN_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__TIA_GAIN_EVEN_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__SLM_XLNA_EVEN_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__BQ_GAIN_EVEN_131___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__XLNA_GAIN_ODD_131___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__XLNA_GAIN_ODD_131___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__LNA_GAIN_ODD_131___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__LNA_GAIN_ODD_131___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__GM_GAIN_ODD_131___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__GM_GAIN_ODD_131___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__TIA_GAIN_ODD_131___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__TIA_GAIN_ODD_131___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__SLM_XLNA_ODD_131___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__SLM_XLNA_ODD_131___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__BQ_GAIN_ODD_131___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__BQ_GAIN_ODD_131___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__XLNA_GAIN_EVEN_131___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__XLNA_GAIN_EVEN_131___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__LNA_GAIN_EVEN_131___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__LNA_GAIN_EVEN_131___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__GM_GAIN_EVEN_131___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__GM_GAIN_EVEN_131___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__TIA_GAIN_EVEN_131___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__TIA_GAIN_EVEN_131___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__SLM_XLNA_EVEN_131___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__SLM_XLNA_EVEN_131___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__BQ_GAIN_EVEN_131___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131__BQ_GAIN_EVEN_131___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_131___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132 (0x005E5210) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__XLNA_GAIN_ODD_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__LNA_GAIN_ODD_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__GM_GAIN_ODD_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__TIA_GAIN_ODD_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__SLM_XLNA_ODD_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__BQ_GAIN_ODD_132___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__XLNA_GAIN_EVEN_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__LNA_GAIN_EVEN_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__GM_GAIN_EVEN_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__TIA_GAIN_EVEN_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__SLM_XLNA_EVEN_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__BQ_GAIN_EVEN_132___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__XLNA_GAIN_ODD_132___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__XLNA_GAIN_ODD_132___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__LNA_GAIN_ODD_132___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__LNA_GAIN_ODD_132___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__GM_GAIN_ODD_132___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__GM_GAIN_ODD_132___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__TIA_GAIN_ODD_132___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__TIA_GAIN_ODD_132___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__SLM_XLNA_ODD_132___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__SLM_XLNA_ODD_132___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__BQ_GAIN_ODD_132___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__BQ_GAIN_ODD_132___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__XLNA_GAIN_EVEN_132___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__XLNA_GAIN_EVEN_132___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__LNA_GAIN_EVEN_132___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__LNA_GAIN_EVEN_132___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__GM_GAIN_EVEN_132___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__GM_GAIN_EVEN_132___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__TIA_GAIN_EVEN_132___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__TIA_GAIN_EVEN_132___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__SLM_XLNA_EVEN_132___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__SLM_XLNA_EVEN_132___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__BQ_GAIN_EVEN_132___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132__BQ_GAIN_EVEN_132___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_132___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133 (0x005E5214) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__XLNA_GAIN_ODD_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__LNA_GAIN_ODD_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__GM_GAIN_ODD_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__TIA_GAIN_ODD_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__SLM_XLNA_ODD_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__BQ_GAIN_ODD_133___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__XLNA_GAIN_EVEN_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__LNA_GAIN_EVEN_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__GM_GAIN_EVEN_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__TIA_GAIN_EVEN_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__SLM_XLNA_EVEN_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__BQ_GAIN_EVEN_133___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__XLNA_GAIN_ODD_133___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__XLNA_GAIN_ODD_133___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__LNA_GAIN_ODD_133___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__LNA_GAIN_ODD_133___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__GM_GAIN_ODD_133___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__GM_GAIN_ODD_133___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__TIA_GAIN_ODD_133___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__TIA_GAIN_ODD_133___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__SLM_XLNA_ODD_133___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__SLM_XLNA_ODD_133___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__BQ_GAIN_ODD_133___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__BQ_GAIN_ODD_133___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__XLNA_GAIN_EVEN_133___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__XLNA_GAIN_EVEN_133___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__LNA_GAIN_EVEN_133___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__LNA_GAIN_EVEN_133___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__GM_GAIN_EVEN_133___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__GM_GAIN_EVEN_133___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__TIA_GAIN_EVEN_133___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__TIA_GAIN_EVEN_133___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__SLM_XLNA_EVEN_133___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__SLM_XLNA_EVEN_133___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__BQ_GAIN_EVEN_133___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133__BQ_GAIN_EVEN_133___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_133___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134 (0x005E5218) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__XLNA_GAIN_ODD_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__LNA_GAIN_ODD_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__GM_GAIN_ODD_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__TIA_GAIN_ODD_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__SLM_XLNA_ODD_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__BQ_GAIN_ODD_134___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__XLNA_GAIN_EVEN_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__LNA_GAIN_EVEN_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__GM_GAIN_EVEN_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__TIA_GAIN_EVEN_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__SLM_XLNA_EVEN_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__BQ_GAIN_EVEN_134___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__XLNA_GAIN_ODD_134___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__XLNA_GAIN_ODD_134___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__LNA_GAIN_ODD_134___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__LNA_GAIN_ODD_134___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__GM_GAIN_ODD_134___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__GM_GAIN_ODD_134___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__TIA_GAIN_ODD_134___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__TIA_GAIN_ODD_134___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__SLM_XLNA_ODD_134___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__SLM_XLNA_ODD_134___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__BQ_GAIN_ODD_134___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__BQ_GAIN_ODD_134___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__XLNA_GAIN_EVEN_134___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__XLNA_GAIN_EVEN_134___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__LNA_GAIN_EVEN_134___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__LNA_GAIN_EVEN_134___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__GM_GAIN_EVEN_134___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__GM_GAIN_EVEN_134___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__TIA_GAIN_EVEN_134___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__TIA_GAIN_EVEN_134___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__SLM_XLNA_EVEN_134___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__SLM_XLNA_EVEN_134___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__BQ_GAIN_EVEN_134___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134__BQ_GAIN_EVEN_134___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_134___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135 (0x005E521C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__XLNA_GAIN_ODD_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__LNA_GAIN_ODD_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__GM_GAIN_ODD_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__TIA_GAIN_ODD_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__SLM_XLNA_ODD_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__BQ_GAIN_ODD_135___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__XLNA_GAIN_EVEN_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__LNA_GAIN_EVEN_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__GM_GAIN_EVEN_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__TIA_GAIN_EVEN_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__SLM_XLNA_EVEN_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__BQ_GAIN_EVEN_135___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__XLNA_GAIN_ODD_135___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__XLNA_GAIN_ODD_135___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__LNA_GAIN_ODD_135___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__LNA_GAIN_ODD_135___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__GM_GAIN_ODD_135___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__GM_GAIN_ODD_135___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__TIA_GAIN_ODD_135___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__TIA_GAIN_ODD_135___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__SLM_XLNA_ODD_135___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__SLM_XLNA_ODD_135___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__BQ_GAIN_ODD_135___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__BQ_GAIN_ODD_135___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__XLNA_GAIN_EVEN_135___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__XLNA_GAIN_EVEN_135___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__LNA_GAIN_EVEN_135___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__LNA_GAIN_EVEN_135___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__GM_GAIN_EVEN_135___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__GM_GAIN_EVEN_135___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__TIA_GAIN_EVEN_135___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__TIA_GAIN_EVEN_135___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__SLM_XLNA_EVEN_135___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__SLM_XLNA_EVEN_135___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__BQ_GAIN_EVEN_135___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135__BQ_GAIN_EVEN_135___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_135___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136 (0x005E5220) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__XLNA_GAIN_ODD_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__LNA_GAIN_ODD_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__GM_GAIN_ODD_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__TIA_GAIN_ODD_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__SLM_XLNA_ODD_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__BQ_GAIN_ODD_136___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__XLNA_GAIN_EVEN_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__LNA_GAIN_EVEN_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__GM_GAIN_EVEN_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__TIA_GAIN_EVEN_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__SLM_XLNA_EVEN_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__BQ_GAIN_EVEN_136___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__XLNA_GAIN_ODD_136___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__XLNA_GAIN_ODD_136___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__LNA_GAIN_ODD_136___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__LNA_GAIN_ODD_136___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__GM_GAIN_ODD_136___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__GM_GAIN_ODD_136___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__TIA_GAIN_ODD_136___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__TIA_GAIN_ODD_136___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__SLM_XLNA_ODD_136___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__SLM_XLNA_ODD_136___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__BQ_GAIN_ODD_136___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__BQ_GAIN_ODD_136___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__XLNA_GAIN_EVEN_136___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__XLNA_GAIN_EVEN_136___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__LNA_GAIN_EVEN_136___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__LNA_GAIN_EVEN_136___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__GM_GAIN_EVEN_136___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__GM_GAIN_EVEN_136___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__TIA_GAIN_EVEN_136___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__TIA_GAIN_EVEN_136___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__SLM_XLNA_EVEN_136___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__SLM_XLNA_EVEN_136___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__BQ_GAIN_EVEN_136___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136__BQ_GAIN_EVEN_136___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_136___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137 (0x005E5224) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__XLNA_GAIN_ODD_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__LNA_GAIN_ODD_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__GM_GAIN_ODD_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__TIA_GAIN_ODD_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__SLM_XLNA_ODD_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__BQ_GAIN_ODD_137___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__XLNA_GAIN_EVEN_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__LNA_GAIN_EVEN_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__GM_GAIN_EVEN_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__TIA_GAIN_EVEN_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__SLM_XLNA_EVEN_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__BQ_GAIN_EVEN_137___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__XLNA_GAIN_ODD_137___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__XLNA_GAIN_ODD_137___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__LNA_GAIN_ODD_137___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__LNA_GAIN_ODD_137___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__GM_GAIN_ODD_137___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__GM_GAIN_ODD_137___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__TIA_GAIN_ODD_137___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__TIA_GAIN_ODD_137___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__SLM_XLNA_ODD_137___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__SLM_XLNA_ODD_137___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__BQ_GAIN_ODD_137___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__BQ_GAIN_ODD_137___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__XLNA_GAIN_EVEN_137___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__XLNA_GAIN_EVEN_137___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__LNA_GAIN_EVEN_137___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__LNA_GAIN_EVEN_137___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__GM_GAIN_EVEN_137___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__GM_GAIN_EVEN_137___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__TIA_GAIN_EVEN_137___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__TIA_GAIN_EVEN_137___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__SLM_XLNA_EVEN_137___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__SLM_XLNA_EVEN_137___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__BQ_GAIN_EVEN_137___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137__BQ_GAIN_EVEN_137___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_137___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138 (0x005E5228) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__XLNA_GAIN_ODD_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__LNA_GAIN_ODD_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__GM_GAIN_ODD_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__TIA_GAIN_ODD_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__SLM_XLNA_ODD_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__BQ_GAIN_ODD_138___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__XLNA_GAIN_EVEN_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__LNA_GAIN_EVEN_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__GM_GAIN_EVEN_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__TIA_GAIN_EVEN_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__SLM_XLNA_EVEN_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__BQ_GAIN_EVEN_138___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__XLNA_GAIN_ODD_138___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__XLNA_GAIN_ODD_138___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__LNA_GAIN_ODD_138___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__LNA_GAIN_ODD_138___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__GM_GAIN_ODD_138___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__GM_GAIN_ODD_138___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__TIA_GAIN_ODD_138___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__TIA_GAIN_ODD_138___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__SLM_XLNA_ODD_138___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__SLM_XLNA_ODD_138___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__BQ_GAIN_ODD_138___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__BQ_GAIN_ODD_138___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__XLNA_GAIN_EVEN_138___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__XLNA_GAIN_EVEN_138___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__LNA_GAIN_EVEN_138___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__LNA_GAIN_EVEN_138___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__GM_GAIN_EVEN_138___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__GM_GAIN_EVEN_138___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__TIA_GAIN_EVEN_138___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__TIA_GAIN_EVEN_138___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__SLM_XLNA_EVEN_138___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__SLM_XLNA_EVEN_138___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__BQ_GAIN_EVEN_138___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138__BQ_GAIN_EVEN_138___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_138___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139 (0x005E522C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__XLNA_GAIN_ODD_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__LNA_GAIN_ODD_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__GM_GAIN_ODD_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__TIA_GAIN_ODD_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__SLM_XLNA_ODD_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__BQ_GAIN_ODD_139___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__XLNA_GAIN_EVEN_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__LNA_GAIN_EVEN_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__GM_GAIN_EVEN_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__TIA_GAIN_EVEN_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__SLM_XLNA_EVEN_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__BQ_GAIN_EVEN_139___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__XLNA_GAIN_ODD_139___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__XLNA_GAIN_ODD_139___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__LNA_GAIN_ODD_139___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__LNA_GAIN_ODD_139___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__GM_GAIN_ODD_139___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__GM_GAIN_ODD_139___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__TIA_GAIN_ODD_139___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__TIA_GAIN_ODD_139___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__SLM_XLNA_ODD_139___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__SLM_XLNA_ODD_139___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__BQ_GAIN_ODD_139___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__BQ_GAIN_ODD_139___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__XLNA_GAIN_EVEN_139___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__XLNA_GAIN_EVEN_139___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__LNA_GAIN_EVEN_139___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__LNA_GAIN_EVEN_139___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__GM_GAIN_EVEN_139___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__GM_GAIN_EVEN_139___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__TIA_GAIN_EVEN_139___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__TIA_GAIN_EVEN_139___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__SLM_XLNA_EVEN_139___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__SLM_XLNA_EVEN_139___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__BQ_GAIN_EVEN_139___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139__BQ_GAIN_EVEN_139___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_139___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140 (0x005E5230) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__XLNA_GAIN_ODD_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__LNA_GAIN_ODD_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__GM_GAIN_ODD_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__TIA_GAIN_ODD_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__SLM_XLNA_ODD_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__BQ_GAIN_ODD_140___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__XLNA_GAIN_EVEN_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__LNA_GAIN_EVEN_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__GM_GAIN_EVEN_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__TIA_GAIN_EVEN_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__SLM_XLNA_EVEN_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__BQ_GAIN_EVEN_140___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__XLNA_GAIN_ODD_140___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__XLNA_GAIN_ODD_140___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__LNA_GAIN_ODD_140___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__LNA_GAIN_ODD_140___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__GM_GAIN_ODD_140___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__GM_GAIN_ODD_140___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__TIA_GAIN_ODD_140___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__TIA_GAIN_ODD_140___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__SLM_XLNA_ODD_140___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__SLM_XLNA_ODD_140___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__BQ_GAIN_ODD_140___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__BQ_GAIN_ODD_140___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__XLNA_GAIN_EVEN_140___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__XLNA_GAIN_EVEN_140___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__LNA_GAIN_EVEN_140___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__LNA_GAIN_EVEN_140___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__GM_GAIN_EVEN_140___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__GM_GAIN_EVEN_140___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__TIA_GAIN_EVEN_140___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__TIA_GAIN_EVEN_140___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__SLM_XLNA_EVEN_140___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__SLM_XLNA_EVEN_140___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__BQ_GAIN_EVEN_140___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140__BQ_GAIN_EVEN_140___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_140___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141 (0x005E5234) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__XLNA_GAIN_ODD_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__LNA_GAIN_ODD_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__GM_GAIN_ODD_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__TIA_GAIN_ODD_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__SLM_XLNA_ODD_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__BQ_GAIN_ODD_141___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__XLNA_GAIN_EVEN_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__LNA_GAIN_EVEN_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__GM_GAIN_EVEN_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__TIA_GAIN_EVEN_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__SLM_XLNA_EVEN_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__BQ_GAIN_EVEN_141___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__XLNA_GAIN_ODD_141___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__XLNA_GAIN_ODD_141___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__LNA_GAIN_ODD_141___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__LNA_GAIN_ODD_141___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__GM_GAIN_ODD_141___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__GM_GAIN_ODD_141___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__TIA_GAIN_ODD_141___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__TIA_GAIN_ODD_141___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__SLM_XLNA_ODD_141___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__SLM_XLNA_ODD_141___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__BQ_GAIN_ODD_141___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__BQ_GAIN_ODD_141___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__XLNA_GAIN_EVEN_141___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__XLNA_GAIN_EVEN_141___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__LNA_GAIN_EVEN_141___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__LNA_GAIN_EVEN_141___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__GM_GAIN_EVEN_141___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__GM_GAIN_EVEN_141___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__TIA_GAIN_EVEN_141___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__TIA_GAIN_EVEN_141___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__SLM_XLNA_EVEN_141___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__SLM_XLNA_EVEN_141___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__BQ_GAIN_EVEN_141___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141__BQ_GAIN_EVEN_141___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_141___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142 (0x005E5238) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__XLNA_GAIN_ODD_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__LNA_GAIN_ODD_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__GM_GAIN_ODD_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__TIA_GAIN_ODD_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__SLM_XLNA_ODD_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__BQ_GAIN_ODD_142___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__XLNA_GAIN_EVEN_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__LNA_GAIN_EVEN_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__GM_GAIN_EVEN_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__TIA_GAIN_EVEN_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__SLM_XLNA_EVEN_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__BQ_GAIN_EVEN_142___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__XLNA_GAIN_ODD_142___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__XLNA_GAIN_ODD_142___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__LNA_GAIN_ODD_142___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__LNA_GAIN_ODD_142___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__GM_GAIN_ODD_142___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__GM_GAIN_ODD_142___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__TIA_GAIN_ODD_142___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__TIA_GAIN_ODD_142___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__SLM_XLNA_ODD_142___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__SLM_XLNA_ODD_142___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__BQ_GAIN_ODD_142___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__BQ_GAIN_ODD_142___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__XLNA_GAIN_EVEN_142___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__XLNA_GAIN_EVEN_142___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__LNA_GAIN_EVEN_142___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__LNA_GAIN_EVEN_142___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__GM_GAIN_EVEN_142___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__GM_GAIN_EVEN_142___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__TIA_GAIN_EVEN_142___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__TIA_GAIN_EVEN_142___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__SLM_XLNA_EVEN_142___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__SLM_XLNA_EVEN_142___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__BQ_GAIN_EVEN_142___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142__BQ_GAIN_EVEN_142___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_142___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143 (0x005E523C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__XLNA_GAIN_ODD_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__LNA_GAIN_ODD_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__GM_GAIN_ODD_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__TIA_GAIN_ODD_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__SLM_XLNA_ODD_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__BQ_GAIN_ODD_143___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__XLNA_GAIN_EVEN_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__LNA_GAIN_EVEN_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__GM_GAIN_EVEN_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__TIA_GAIN_EVEN_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__SLM_XLNA_EVEN_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__BQ_GAIN_EVEN_143___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__XLNA_GAIN_ODD_143___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__XLNA_GAIN_ODD_143___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__LNA_GAIN_ODD_143___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__LNA_GAIN_ODD_143___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__GM_GAIN_ODD_143___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__GM_GAIN_ODD_143___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__TIA_GAIN_ODD_143___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__TIA_GAIN_ODD_143___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__SLM_XLNA_ODD_143___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__SLM_XLNA_ODD_143___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__BQ_GAIN_ODD_143___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__BQ_GAIN_ODD_143___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__XLNA_GAIN_EVEN_143___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__XLNA_GAIN_EVEN_143___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__LNA_GAIN_EVEN_143___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__LNA_GAIN_EVEN_143___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__GM_GAIN_EVEN_143___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__GM_GAIN_EVEN_143___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__TIA_GAIN_EVEN_143___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__TIA_GAIN_EVEN_143___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__SLM_XLNA_EVEN_143___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__SLM_XLNA_EVEN_143___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__BQ_GAIN_EVEN_143___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143__BQ_GAIN_EVEN_143___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_143___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144 (0x005E5240) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__XLNA_GAIN_ODD_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__LNA_GAIN_ODD_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__GM_GAIN_ODD_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__TIA_GAIN_ODD_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__SLM_XLNA_ODD_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__BQ_GAIN_ODD_144___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__XLNA_GAIN_EVEN_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__LNA_GAIN_EVEN_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__GM_GAIN_EVEN_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__TIA_GAIN_EVEN_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__SLM_XLNA_EVEN_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__BQ_GAIN_EVEN_144___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__XLNA_GAIN_ODD_144___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__XLNA_GAIN_ODD_144___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__LNA_GAIN_ODD_144___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__LNA_GAIN_ODD_144___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__GM_GAIN_ODD_144___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__GM_GAIN_ODD_144___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__TIA_GAIN_ODD_144___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__TIA_GAIN_ODD_144___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__SLM_XLNA_ODD_144___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__SLM_XLNA_ODD_144___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__BQ_GAIN_ODD_144___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__BQ_GAIN_ODD_144___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__XLNA_GAIN_EVEN_144___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__XLNA_GAIN_EVEN_144___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__LNA_GAIN_EVEN_144___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__LNA_GAIN_EVEN_144___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__GM_GAIN_EVEN_144___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__GM_GAIN_EVEN_144___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__TIA_GAIN_EVEN_144___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__TIA_GAIN_EVEN_144___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__SLM_XLNA_EVEN_144___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__SLM_XLNA_EVEN_144___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__BQ_GAIN_EVEN_144___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144__BQ_GAIN_EVEN_144___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_144___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145 (0x005E5244) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__XLNA_GAIN_ODD_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__LNA_GAIN_ODD_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__GM_GAIN_ODD_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__TIA_GAIN_ODD_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__SLM_XLNA_ODD_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__BQ_GAIN_ODD_145___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__XLNA_GAIN_EVEN_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__LNA_GAIN_EVEN_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__GM_GAIN_EVEN_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__TIA_GAIN_EVEN_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__SLM_XLNA_EVEN_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__BQ_GAIN_EVEN_145___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__XLNA_GAIN_ODD_145___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__XLNA_GAIN_ODD_145___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__LNA_GAIN_ODD_145___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__LNA_GAIN_ODD_145___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__GM_GAIN_ODD_145___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__GM_GAIN_ODD_145___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__TIA_GAIN_ODD_145___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__TIA_GAIN_ODD_145___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__SLM_XLNA_ODD_145___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__SLM_XLNA_ODD_145___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__BQ_GAIN_ODD_145___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__BQ_GAIN_ODD_145___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__XLNA_GAIN_EVEN_145___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__XLNA_GAIN_EVEN_145___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__LNA_GAIN_EVEN_145___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__LNA_GAIN_EVEN_145___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__GM_GAIN_EVEN_145___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__GM_GAIN_EVEN_145___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__TIA_GAIN_EVEN_145___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__TIA_GAIN_EVEN_145___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__SLM_XLNA_EVEN_145___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__SLM_XLNA_EVEN_145___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__BQ_GAIN_EVEN_145___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145__BQ_GAIN_EVEN_145___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_145___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146 (0x005E5248) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__XLNA_GAIN_ODD_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__LNA_GAIN_ODD_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__GM_GAIN_ODD_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__TIA_GAIN_ODD_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__SLM_XLNA_ODD_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__BQ_GAIN_ODD_146___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__XLNA_GAIN_EVEN_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__LNA_GAIN_EVEN_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__GM_GAIN_EVEN_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__TIA_GAIN_EVEN_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__SLM_XLNA_EVEN_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__BQ_GAIN_EVEN_146___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__XLNA_GAIN_ODD_146___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__XLNA_GAIN_ODD_146___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__LNA_GAIN_ODD_146___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__LNA_GAIN_ODD_146___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__GM_GAIN_ODD_146___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__GM_GAIN_ODD_146___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__TIA_GAIN_ODD_146___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__TIA_GAIN_ODD_146___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__SLM_XLNA_ODD_146___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__SLM_XLNA_ODD_146___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__BQ_GAIN_ODD_146___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__BQ_GAIN_ODD_146___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__XLNA_GAIN_EVEN_146___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__XLNA_GAIN_EVEN_146___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__LNA_GAIN_EVEN_146___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__LNA_GAIN_EVEN_146___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__GM_GAIN_EVEN_146___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__GM_GAIN_EVEN_146___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__TIA_GAIN_EVEN_146___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__TIA_GAIN_EVEN_146___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__SLM_XLNA_EVEN_146___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__SLM_XLNA_EVEN_146___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__BQ_GAIN_EVEN_146___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146__BQ_GAIN_EVEN_146___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_146___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147 (0x005E524C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__XLNA_GAIN_ODD_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__LNA_GAIN_ODD_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__GM_GAIN_ODD_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__TIA_GAIN_ODD_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__SLM_XLNA_ODD_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__BQ_GAIN_ODD_147___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__XLNA_GAIN_EVEN_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__LNA_GAIN_EVEN_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__GM_GAIN_EVEN_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__TIA_GAIN_EVEN_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__SLM_XLNA_EVEN_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__BQ_GAIN_EVEN_147___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__XLNA_GAIN_ODD_147___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__XLNA_GAIN_ODD_147___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__LNA_GAIN_ODD_147___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__LNA_GAIN_ODD_147___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__GM_GAIN_ODD_147___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__GM_GAIN_ODD_147___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__TIA_GAIN_ODD_147___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__TIA_GAIN_ODD_147___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__SLM_XLNA_ODD_147___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__SLM_XLNA_ODD_147___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__BQ_GAIN_ODD_147___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__BQ_GAIN_ODD_147___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__XLNA_GAIN_EVEN_147___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__XLNA_GAIN_EVEN_147___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__LNA_GAIN_EVEN_147___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__LNA_GAIN_EVEN_147___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__GM_GAIN_EVEN_147___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__GM_GAIN_EVEN_147___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__TIA_GAIN_EVEN_147___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__TIA_GAIN_EVEN_147___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__SLM_XLNA_EVEN_147___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__SLM_XLNA_EVEN_147___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__BQ_GAIN_EVEN_147___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147__BQ_GAIN_EVEN_147___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_147___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148 (0x005E5250) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__XLNA_GAIN_ODD_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__LNA_GAIN_ODD_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__GM_GAIN_ODD_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__TIA_GAIN_ODD_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__SLM_XLNA_ODD_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__BQ_GAIN_ODD_148___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__XLNA_GAIN_EVEN_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__LNA_GAIN_EVEN_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__GM_GAIN_EVEN_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__TIA_GAIN_EVEN_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__SLM_XLNA_EVEN_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__BQ_GAIN_EVEN_148___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__XLNA_GAIN_ODD_148___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__XLNA_GAIN_ODD_148___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__LNA_GAIN_ODD_148___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__LNA_GAIN_ODD_148___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__GM_GAIN_ODD_148___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__GM_GAIN_ODD_148___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__TIA_GAIN_ODD_148___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__TIA_GAIN_ODD_148___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__SLM_XLNA_ODD_148___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__SLM_XLNA_ODD_148___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__BQ_GAIN_ODD_148___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__BQ_GAIN_ODD_148___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__XLNA_GAIN_EVEN_148___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__XLNA_GAIN_EVEN_148___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__LNA_GAIN_EVEN_148___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__LNA_GAIN_EVEN_148___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__GM_GAIN_EVEN_148___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__GM_GAIN_EVEN_148___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__TIA_GAIN_EVEN_148___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__TIA_GAIN_EVEN_148___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__SLM_XLNA_EVEN_148___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__SLM_XLNA_EVEN_148___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__BQ_GAIN_EVEN_148___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148__BQ_GAIN_EVEN_148___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_148___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149 (0x005E5254) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__XLNA_GAIN_ODD_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__LNA_GAIN_ODD_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__GM_GAIN_ODD_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__TIA_GAIN_ODD_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__SLM_XLNA_ODD_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__BQ_GAIN_ODD_149___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__XLNA_GAIN_EVEN_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__LNA_GAIN_EVEN_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__GM_GAIN_EVEN_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__TIA_GAIN_EVEN_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__SLM_XLNA_EVEN_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__BQ_GAIN_EVEN_149___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__XLNA_GAIN_ODD_149___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__XLNA_GAIN_ODD_149___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__LNA_GAIN_ODD_149___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__LNA_GAIN_ODD_149___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__GM_GAIN_ODD_149___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__GM_GAIN_ODD_149___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__TIA_GAIN_ODD_149___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__TIA_GAIN_ODD_149___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__SLM_XLNA_ODD_149___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__SLM_XLNA_ODD_149___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__BQ_GAIN_ODD_149___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__BQ_GAIN_ODD_149___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__XLNA_GAIN_EVEN_149___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__XLNA_GAIN_EVEN_149___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__LNA_GAIN_EVEN_149___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__LNA_GAIN_EVEN_149___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__GM_GAIN_EVEN_149___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__GM_GAIN_EVEN_149___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__TIA_GAIN_EVEN_149___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__TIA_GAIN_EVEN_149___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__SLM_XLNA_EVEN_149___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__SLM_XLNA_EVEN_149___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__BQ_GAIN_EVEN_149___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149__BQ_GAIN_EVEN_149___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_149___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150 (0x005E5258) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__XLNA_GAIN_ODD_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__LNA_GAIN_ODD_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__GM_GAIN_ODD_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__TIA_GAIN_ODD_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__SLM_XLNA_ODD_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__BQ_GAIN_ODD_150___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__XLNA_GAIN_EVEN_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__LNA_GAIN_EVEN_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__GM_GAIN_EVEN_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__TIA_GAIN_EVEN_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__SLM_XLNA_EVEN_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__BQ_GAIN_EVEN_150___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__XLNA_GAIN_ODD_150___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__XLNA_GAIN_ODD_150___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__LNA_GAIN_ODD_150___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__LNA_GAIN_ODD_150___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__GM_GAIN_ODD_150___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__GM_GAIN_ODD_150___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__TIA_GAIN_ODD_150___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__TIA_GAIN_ODD_150___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__SLM_XLNA_ODD_150___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__SLM_XLNA_ODD_150___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__BQ_GAIN_ODD_150___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__BQ_GAIN_ODD_150___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__XLNA_GAIN_EVEN_150___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__XLNA_GAIN_EVEN_150___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__LNA_GAIN_EVEN_150___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__LNA_GAIN_EVEN_150___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__GM_GAIN_EVEN_150___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__GM_GAIN_EVEN_150___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__TIA_GAIN_EVEN_150___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__TIA_GAIN_EVEN_150___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__SLM_XLNA_EVEN_150___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__SLM_XLNA_EVEN_150___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__BQ_GAIN_EVEN_150___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150__BQ_GAIN_EVEN_150___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_150___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151 (0x005E525C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__XLNA_GAIN_ODD_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__LNA_GAIN_ODD_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__GM_GAIN_ODD_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__TIA_GAIN_ODD_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__SLM_XLNA_ODD_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__BQ_GAIN_ODD_151___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__XLNA_GAIN_EVEN_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__LNA_GAIN_EVEN_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__GM_GAIN_EVEN_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__TIA_GAIN_EVEN_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__SLM_XLNA_EVEN_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__BQ_GAIN_EVEN_151___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__XLNA_GAIN_ODD_151___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__XLNA_GAIN_ODD_151___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__LNA_GAIN_ODD_151___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__LNA_GAIN_ODD_151___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__GM_GAIN_ODD_151___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__GM_GAIN_ODD_151___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__TIA_GAIN_ODD_151___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__TIA_GAIN_ODD_151___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__SLM_XLNA_ODD_151___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__SLM_XLNA_ODD_151___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__BQ_GAIN_ODD_151___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__BQ_GAIN_ODD_151___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__XLNA_GAIN_EVEN_151___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__XLNA_GAIN_EVEN_151___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__LNA_GAIN_EVEN_151___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__LNA_GAIN_EVEN_151___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__GM_GAIN_EVEN_151___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__GM_GAIN_EVEN_151___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__TIA_GAIN_EVEN_151___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__TIA_GAIN_EVEN_151___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__SLM_XLNA_EVEN_151___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__SLM_XLNA_EVEN_151___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__BQ_GAIN_EVEN_151___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151__BQ_GAIN_EVEN_151___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_151___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152 (0x005E5260) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__XLNA_GAIN_ODD_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__LNA_GAIN_ODD_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__GM_GAIN_ODD_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__TIA_GAIN_ODD_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__SLM_XLNA_ODD_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__BQ_GAIN_ODD_152___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__XLNA_GAIN_EVEN_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__LNA_GAIN_EVEN_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__GM_GAIN_EVEN_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__TIA_GAIN_EVEN_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__SLM_XLNA_EVEN_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__BQ_GAIN_EVEN_152___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__XLNA_GAIN_ODD_152___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__XLNA_GAIN_ODD_152___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__LNA_GAIN_ODD_152___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__LNA_GAIN_ODD_152___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__GM_GAIN_ODD_152___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__GM_GAIN_ODD_152___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__TIA_GAIN_ODD_152___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__TIA_GAIN_ODD_152___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__SLM_XLNA_ODD_152___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__SLM_XLNA_ODD_152___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__BQ_GAIN_ODD_152___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__BQ_GAIN_ODD_152___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__XLNA_GAIN_EVEN_152___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__XLNA_GAIN_EVEN_152___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__LNA_GAIN_EVEN_152___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__LNA_GAIN_EVEN_152___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__GM_GAIN_EVEN_152___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__GM_GAIN_EVEN_152___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__TIA_GAIN_EVEN_152___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__TIA_GAIN_EVEN_152___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__SLM_XLNA_EVEN_152___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__SLM_XLNA_EVEN_152___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__BQ_GAIN_EVEN_152___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152__BQ_GAIN_EVEN_152___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_152___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153 (0x005E5264) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__XLNA_GAIN_ODD_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__LNA_GAIN_ODD_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__GM_GAIN_ODD_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__TIA_GAIN_ODD_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__SLM_XLNA_ODD_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__BQ_GAIN_ODD_153___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__XLNA_GAIN_EVEN_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__LNA_GAIN_EVEN_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__GM_GAIN_EVEN_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__TIA_GAIN_EVEN_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__SLM_XLNA_EVEN_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__BQ_GAIN_EVEN_153___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__XLNA_GAIN_ODD_153___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__XLNA_GAIN_ODD_153___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__LNA_GAIN_ODD_153___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__LNA_GAIN_ODD_153___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__GM_GAIN_ODD_153___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__GM_GAIN_ODD_153___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__TIA_GAIN_ODD_153___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__TIA_GAIN_ODD_153___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__SLM_XLNA_ODD_153___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__SLM_XLNA_ODD_153___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__BQ_GAIN_ODD_153___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__BQ_GAIN_ODD_153___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__XLNA_GAIN_EVEN_153___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__XLNA_GAIN_EVEN_153___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__LNA_GAIN_EVEN_153___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__LNA_GAIN_EVEN_153___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__GM_GAIN_EVEN_153___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__GM_GAIN_EVEN_153___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__TIA_GAIN_EVEN_153___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__TIA_GAIN_EVEN_153___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__SLM_XLNA_EVEN_153___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__SLM_XLNA_EVEN_153___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__BQ_GAIN_EVEN_153___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153__BQ_GAIN_EVEN_153___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_153___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154 (0x005E5268) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__XLNA_GAIN_ODD_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__LNA_GAIN_ODD_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__GM_GAIN_ODD_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__TIA_GAIN_ODD_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__SLM_XLNA_ODD_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__BQ_GAIN_ODD_154___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__XLNA_GAIN_EVEN_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__LNA_GAIN_EVEN_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__GM_GAIN_EVEN_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__TIA_GAIN_EVEN_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__SLM_XLNA_EVEN_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__BQ_GAIN_EVEN_154___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__XLNA_GAIN_ODD_154___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__XLNA_GAIN_ODD_154___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__LNA_GAIN_ODD_154___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__LNA_GAIN_ODD_154___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__GM_GAIN_ODD_154___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__GM_GAIN_ODD_154___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__TIA_GAIN_ODD_154___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__TIA_GAIN_ODD_154___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__SLM_XLNA_ODD_154___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__SLM_XLNA_ODD_154___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__BQ_GAIN_ODD_154___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__BQ_GAIN_ODD_154___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__XLNA_GAIN_EVEN_154___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__XLNA_GAIN_EVEN_154___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__LNA_GAIN_EVEN_154___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__LNA_GAIN_EVEN_154___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__GM_GAIN_EVEN_154___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__GM_GAIN_EVEN_154___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__TIA_GAIN_EVEN_154___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__TIA_GAIN_EVEN_154___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__SLM_XLNA_EVEN_154___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__SLM_XLNA_EVEN_154___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__BQ_GAIN_EVEN_154___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154__BQ_GAIN_EVEN_154___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_154___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155 (0x005E526C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__XLNA_GAIN_ODD_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__LNA_GAIN_ODD_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__GM_GAIN_ODD_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__TIA_GAIN_ODD_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__SLM_XLNA_ODD_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__BQ_GAIN_ODD_155___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__XLNA_GAIN_EVEN_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__LNA_GAIN_EVEN_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__GM_GAIN_EVEN_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__TIA_GAIN_EVEN_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__SLM_XLNA_EVEN_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__BQ_GAIN_EVEN_155___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__XLNA_GAIN_ODD_155___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__XLNA_GAIN_ODD_155___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__LNA_GAIN_ODD_155___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__LNA_GAIN_ODD_155___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__GM_GAIN_ODD_155___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__GM_GAIN_ODD_155___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__TIA_GAIN_ODD_155___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__TIA_GAIN_ODD_155___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__SLM_XLNA_ODD_155___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__SLM_XLNA_ODD_155___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__BQ_GAIN_ODD_155___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__BQ_GAIN_ODD_155___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__XLNA_GAIN_EVEN_155___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__XLNA_GAIN_EVEN_155___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__LNA_GAIN_EVEN_155___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__LNA_GAIN_EVEN_155___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__GM_GAIN_EVEN_155___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__GM_GAIN_EVEN_155___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__TIA_GAIN_EVEN_155___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__TIA_GAIN_EVEN_155___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__SLM_XLNA_EVEN_155___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__SLM_XLNA_EVEN_155___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__BQ_GAIN_EVEN_155___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155__BQ_GAIN_EVEN_155___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_155___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156 (0x005E5270) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__XLNA_GAIN_ODD_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__LNA_GAIN_ODD_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__GM_GAIN_ODD_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__TIA_GAIN_ODD_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__SLM_XLNA_ODD_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__BQ_GAIN_ODD_156___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__XLNA_GAIN_EVEN_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__LNA_GAIN_EVEN_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__GM_GAIN_EVEN_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__TIA_GAIN_EVEN_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__SLM_XLNA_EVEN_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__BQ_GAIN_EVEN_156___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__XLNA_GAIN_ODD_156___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__XLNA_GAIN_ODD_156___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__LNA_GAIN_ODD_156___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__LNA_GAIN_ODD_156___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__GM_GAIN_ODD_156___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__GM_GAIN_ODD_156___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__TIA_GAIN_ODD_156___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__TIA_GAIN_ODD_156___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__SLM_XLNA_ODD_156___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__SLM_XLNA_ODD_156___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__BQ_GAIN_ODD_156___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__BQ_GAIN_ODD_156___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__XLNA_GAIN_EVEN_156___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__XLNA_GAIN_EVEN_156___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__LNA_GAIN_EVEN_156___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__LNA_GAIN_EVEN_156___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__GM_GAIN_EVEN_156___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__GM_GAIN_EVEN_156___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__TIA_GAIN_EVEN_156___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__TIA_GAIN_EVEN_156___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__SLM_XLNA_EVEN_156___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__SLM_XLNA_EVEN_156___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__BQ_GAIN_EVEN_156___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156__BQ_GAIN_EVEN_156___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_156___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157 (0x005E5274) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__XLNA_GAIN_ODD_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__LNA_GAIN_ODD_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__GM_GAIN_ODD_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__TIA_GAIN_ODD_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__SLM_XLNA_ODD_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__BQ_GAIN_ODD_157___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__XLNA_GAIN_EVEN_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__LNA_GAIN_EVEN_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__GM_GAIN_EVEN_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__TIA_GAIN_EVEN_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__SLM_XLNA_EVEN_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__BQ_GAIN_EVEN_157___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__XLNA_GAIN_ODD_157___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__XLNA_GAIN_ODD_157___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__LNA_GAIN_ODD_157___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__LNA_GAIN_ODD_157___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__GM_GAIN_ODD_157___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__GM_GAIN_ODD_157___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__TIA_GAIN_ODD_157___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__TIA_GAIN_ODD_157___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__SLM_XLNA_ODD_157___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__SLM_XLNA_ODD_157___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__BQ_GAIN_ODD_157___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__BQ_GAIN_ODD_157___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__XLNA_GAIN_EVEN_157___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__XLNA_GAIN_EVEN_157___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__LNA_GAIN_EVEN_157___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__LNA_GAIN_EVEN_157___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__GM_GAIN_EVEN_157___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__GM_GAIN_EVEN_157___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__TIA_GAIN_EVEN_157___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__TIA_GAIN_EVEN_157___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__SLM_XLNA_EVEN_157___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__SLM_XLNA_EVEN_157___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__BQ_GAIN_EVEN_157___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157__BQ_GAIN_EVEN_157___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_157___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158 (0x005E5278) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__XLNA_GAIN_ODD_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__LNA_GAIN_ODD_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__GM_GAIN_ODD_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__TIA_GAIN_ODD_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__SLM_XLNA_ODD_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__BQ_GAIN_ODD_158___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__XLNA_GAIN_EVEN_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__LNA_GAIN_EVEN_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__GM_GAIN_EVEN_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__TIA_GAIN_EVEN_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__SLM_XLNA_EVEN_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__BQ_GAIN_EVEN_158___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__XLNA_GAIN_ODD_158___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__XLNA_GAIN_ODD_158___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__LNA_GAIN_ODD_158___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__LNA_GAIN_ODD_158___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__GM_GAIN_ODD_158___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__GM_GAIN_ODD_158___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__TIA_GAIN_ODD_158___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__TIA_GAIN_ODD_158___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__SLM_XLNA_ODD_158___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__SLM_XLNA_ODD_158___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__BQ_GAIN_ODD_158___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__BQ_GAIN_ODD_158___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__XLNA_GAIN_EVEN_158___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__XLNA_GAIN_EVEN_158___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__LNA_GAIN_EVEN_158___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__LNA_GAIN_EVEN_158___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__GM_GAIN_EVEN_158___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__GM_GAIN_EVEN_158___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__TIA_GAIN_EVEN_158___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__TIA_GAIN_EVEN_158___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__SLM_XLNA_EVEN_158___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__SLM_XLNA_EVEN_158___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__BQ_GAIN_EVEN_158___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158__BQ_GAIN_EVEN_158___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_158___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159 (0x005E527C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__XLNA_GAIN_ODD_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__LNA_GAIN_ODD_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__GM_GAIN_ODD_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__TIA_GAIN_ODD_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__SLM_XLNA_ODD_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__BQ_GAIN_ODD_159___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__XLNA_GAIN_EVEN_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__LNA_GAIN_EVEN_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__GM_GAIN_EVEN_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__TIA_GAIN_EVEN_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__SLM_XLNA_EVEN_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__BQ_GAIN_EVEN_159___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__XLNA_GAIN_ODD_159___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__XLNA_GAIN_ODD_159___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__LNA_GAIN_ODD_159___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__LNA_GAIN_ODD_159___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__GM_GAIN_ODD_159___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__GM_GAIN_ODD_159___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__TIA_GAIN_ODD_159___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__TIA_GAIN_ODD_159___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__SLM_XLNA_ODD_159___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__SLM_XLNA_ODD_159___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__BQ_GAIN_ODD_159___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__BQ_GAIN_ODD_159___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__XLNA_GAIN_EVEN_159___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__XLNA_GAIN_EVEN_159___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__LNA_GAIN_EVEN_159___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__LNA_GAIN_EVEN_159___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__GM_GAIN_EVEN_159___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__GM_GAIN_EVEN_159___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__TIA_GAIN_EVEN_159___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__TIA_GAIN_EVEN_159___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__SLM_XLNA_EVEN_159___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__SLM_XLNA_EVEN_159___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__BQ_GAIN_EVEN_159___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159__BQ_GAIN_EVEN_159___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_159___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160 (0x005E5280) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__XLNA_GAIN_ODD_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__LNA_GAIN_ODD_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__GM_GAIN_ODD_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__TIA_GAIN_ODD_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__SLM_XLNA_ODD_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__BQ_GAIN_ODD_160___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__XLNA_GAIN_EVEN_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__LNA_GAIN_EVEN_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__GM_GAIN_EVEN_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__TIA_GAIN_EVEN_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__SLM_XLNA_EVEN_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__BQ_GAIN_EVEN_160___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__XLNA_GAIN_ODD_160___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__XLNA_GAIN_ODD_160___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__LNA_GAIN_ODD_160___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__LNA_GAIN_ODD_160___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__GM_GAIN_ODD_160___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__GM_GAIN_ODD_160___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__TIA_GAIN_ODD_160___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__TIA_GAIN_ODD_160___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__SLM_XLNA_ODD_160___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__SLM_XLNA_ODD_160___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__BQ_GAIN_ODD_160___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__BQ_GAIN_ODD_160___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__XLNA_GAIN_EVEN_160___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__XLNA_GAIN_EVEN_160___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__LNA_GAIN_EVEN_160___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__LNA_GAIN_EVEN_160___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__GM_GAIN_EVEN_160___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__GM_GAIN_EVEN_160___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__TIA_GAIN_EVEN_160___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__TIA_GAIN_EVEN_160___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__SLM_XLNA_EVEN_160___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__SLM_XLNA_EVEN_160___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__BQ_GAIN_EVEN_160___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160__BQ_GAIN_EVEN_160___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_160___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161 (0x005E5284) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__XLNA_GAIN_ODD_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__LNA_GAIN_ODD_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__GM_GAIN_ODD_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__TIA_GAIN_ODD_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__SLM_XLNA_ODD_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__BQ_GAIN_ODD_161___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__XLNA_GAIN_EVEN_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__LNA_GAIN_EVEN_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__GM_GAIN_EVEN_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__TIA_GAIN_EVEN_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__SLM_XLNA_EVEN_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__BQ_GAIN_EVEN_161___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__XLNA_GAIN_ODD_161___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__XLNA_GAIN_ODD_161___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__LNA_GAIN_ODD_161___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__LNA_GAIN_ODD_161___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__GM_GAIN_ODD_161___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__GM_GAIN_ODD_161___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__TIA_GAIN_ODD_161___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__TIA_GAIN_ODD_161___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__SLM_XLNA_ODD_161___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__SLM_XLNA_ODD_161___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__BQ_GAIN_ODD_161___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__BQ_GAIN_ODD_161___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__XLNA_GAIN_EVEN_161___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__XLNA_GAIN_EVEN_161___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__LNA_GAIN_EVEN_161___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__LNA_GAIN_EVEN_161___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__GM_GAIN_EVEN_161___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__GM_GAIN_EVEN_161___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__TIA_GAIN_EVEN_161___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__TIA_GAIN_EVEN_161___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__SLM_XLNA_EVEN_161___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__SLM_XLNA_EVEN_161___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__BQ_GAIN_EVEN_161___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161__BQ_GAIN_EVEN_161___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_161___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162 (0x005E5288) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__XLNA_GAIN_ODD_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__LNA_GAIN_ODD_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__GM_GAIN_ODD_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__TIA_GAIN_ODD_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__SLM_XLNA_ODD_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__BQ_GAIN_ODD_162___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__XLNA_GAIN_EVEN_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__LNA_GAIN_EVEN_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__GM_GAIN_EVEN_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__TIA_GAIN_EVEN_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__SLM_XLNA_EVEN_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__BQ_GAIN_EVEN_162___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__XLNA_GAIN_ODD_162___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__XLNA_GAIN_ODD_162___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__LNA_GAIN_ODD_162___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__LNA_GAIN_ODD_162___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__GM_GAIN_ODD_162___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__GM_GAIN_ODD_162___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__TIA_GAIN_ODD_162___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__TIA_GAIN_ODD_162___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__SLM_XLNA_ODD_162___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__SLM_XLNA_ODD_162___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__BQ_GAIN_ODD_162___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__BQ_GAIN_ODD_162___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__XLNA_GAIN_EVEN_162___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__XLNA_GAIN_EVEN_162___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__LNA_GAIN_EVEN_162___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__LNA_GAIN_EVEN_162___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__GM_GAIN_EVEN_162___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__GM_GAIN_EVEN_162___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__TIA_GAIN_EVEN_162___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__TIA_GAIN_EVEN_162___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__SLM_XLNA_EVEN_162___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__SLM_XLNA_EVEN_162___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__BQ_GAIN_EVEN_162___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162__BQ_GAIN_EVEN_162___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_162___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163 (0x005E528C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__XLNA_GAIN_ODD_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__LNA_GAIN_ODD_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__GM_GAIN_ODD_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__TIA_GAIN_ODD_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__SLM_XLNA_ODD_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__BQ_GAIN_ODD_163___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__XLNA_GAIN_EVEN_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__LNA_GAIN_EVEN_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__GM_GAIN_EVEN_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__TIA_GAIN_EVEN_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__SLM_XLNA_EVEN_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__BQ_GAIN_EVEN_163___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__XLNA_GAIN_ODD_163___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__XLNA_GAIN_ODD_163___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__LNA_GAIN_ODD_163___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__LNA_GAIN_ODD_163___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__GM_GAIN_ODD_163___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__GM_GAIN_ODD_163___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__TIA_GAIN_ODD_163___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__TIA_GAIN_ODD_163___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__SLM_XLNA_ODD_163___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__SLM_XLNA_ODD_163___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__BQ_GAIN_ODD_163___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__BQ_GAIN_ODD_163___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__XLNA_GAIN_EVEN_163___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__XLNA_GAIN_EVEN_163___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__LNA_GAIN_EVEN_163___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__LNA_GAIN_EVEN_163___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__GM_GAIN_EVEN_163___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__GM_GAIN_EVEN_163___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__TIA_GAIN_EVEN_163___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__TIA_GAIN_EVEN_163___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__SLM_XLNA_EVEN_163___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__SLM_XLNA_EVEN_163___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__BQ_GAIN_EVEN_163___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163__BQ_GAIN_EVEN_163___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_163___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164 (0x005E5290) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__XLNA_GAIN_ODD_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__LNA_GAIN_ODD_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__GM_GAIN_ODD_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__TIA_GAIN_ODD_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__SLM_XLNA_ODD_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__BQ_GAIN_ODD_164___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__XLNA_GAIN_EVEN_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__LNA_GAIN_EVEN_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__GM_GAIN_EVEN_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__TIA_GAIN_EVEN_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__SLM_XLNA_EVEN_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__BQ_GAIN_EVEN_164___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__XLNA_GAIN_ODD_164___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__XLNA_GAIN_ODD_164___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__LNA_GAIN_ODD_164___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__LNA_GAIN_ODD_164___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__GM_GAIN_ODD_164___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__GM_GAIN_ODD_164___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__TIA_GAIN_ODD_164___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__TIA_GAIN_ODD_164___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__SLM_XLNA_ODD_164___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__SLM_XLNA_ODD_164___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__BQ_GAIN_ODD_164___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__BQ_GAIN_ODD_164___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__XLNA_GAIN_EVEN_164___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__XLNA_GAIN_EVEN_164___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__LNA_GAIN_EVEN_164___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__LNA_GAIN_EVEN_164___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__GM_GAIN_EVEN_164___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__GM_GAIN_EVEN_164___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__TIA_GAIN_EVEN_164___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__TIA_GAIN_EVEN_164___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__SLM_XLNA_EVEN_164___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__SLM_XLNA_EVEN_164___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__BQ_GAIN_EVEN_164___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164__BQ_GAIN_EVEN_164___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_164___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165 (0x005E5294) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__XLNA_GAIN_ODD_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__LNA_GAIN_ODD_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__GM_GAIN_ODD_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__TIA_GAIN_ODD_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__SLM_XLNA_ODD_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__BQ_GAIN_ODD_165___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__XLNA_GAIN_EVEN_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__LNA_GAIN_EVEN_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__GM_GAIN_EVEN_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__TIA_GAIN_EVEN_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__SLM_XLNA_EVEN_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__BQ_GAIN_EVEN_165___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__XLNA_GAIN_ODD_165___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__XLNA_GAIN_ODD_165___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__LNA_GAIN_ODD_165___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__LNA_GAIN_ODD_165___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__GM_GAIN_ODD_165___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__GM_GAIN_ODD_165___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__TIA_GAIN_ODD_165___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__TIA_GAIN_ODD_165___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__SLM_XLNA_ODD_165___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__SLM_XLNA_ODD_165___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__BQ_GAIN_ODD_165___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__BQ_GAIN_ODD_165___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__XLNA_GAIN_EVEN_165___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__XLNA_GAIN_EVEN_165___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__LNA_GAIN_EVEN_165___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__LNA_GAIN_EVEN_165___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__GM_GAIN_EVEN_165___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__GM_GAIN_EVEN_165___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__TIA_GAIN_EVEN_165___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__TIA_GAIN_EVEN_165___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__SLM_XLNA_EVEN_165___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__SLM_XLNA_EVEN_165___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__BQ_GAIN_EVEN_165___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165__BQ_GAIN_EVEN_165___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_165___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166 (0x005E5298) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__XLNA_GAIN_ODD_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__LNA_GAIN_ODD_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__GM_GAIN_ODD_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__TIA_GAIN_ODD_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__SLM_XLNA_ODD_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__BQ_GAIN_ODD_166___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__XLNA_GAIN_EVEN_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__LNA_GAIN_EVEN_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__GM_GAIN_EVEN_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__TIA_GAIN_EVEN_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__SLM_XLNA_EVEN_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__BQ_GAIN_EVEN_166___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__XLNA_GAIN_ODD_166___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__XLNA_GAIN_ODD_166___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__LNA_GAIN_ODD_166___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__LNA_GAIN_ODD_166___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__GM_GAIN_ODD_166___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__GM_GAIN_ODD_166___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__TIA_GAIN_ODD_166___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__TIA_GAIN_ODD_166___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__SLM_XLNA_ODD_166___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__SLM_XLNA_ODD_166___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__BQ_GAIN_ODD_166___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__BQ_GAIN_ODD_166___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__XLNA_GAIN_EVEN_166___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__XLNA_GAIN_EVEN_166___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__LNA_GAIN_EVEN_166___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__LNA_GAIN_EVEN_166___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__GM_GAIN_EVEN_166___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__GM_GAIN_EVEN_166___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__TIA_GAIN_EVEN_166___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__TIA_GAIN_EVEN_166___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__SLM_XLNA_EVEN_166___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__SLM_XLNA_EVEN_166___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__BQ_GAIN_EVEN_166___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166__BQ_GAIN_EVEN_166___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_166___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167 (0x005E529C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__XLNA_GAIN_ODD_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__LNA_GAIN_ODD_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__GM_GAIN_ODD_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__TIA_GAIN_ODD_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__SLM_XLNA_ODD_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__BQ_GAIN_ODD_167___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__XLNA_GAIN_EVEN_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__LNA_GAIN_EVEN_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__GM_GAIN_EVEN_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__TIA_GAIN_EVEN_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__SLM_XLNA_EVEN_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__BQ_GAIN_EVEN_167___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__XLNA_GAIN_ODD_167___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__XLNA_GAIN_ODD_167___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__LNA_GAIN_ODD_167___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__LNA_GAIN_ODD_167___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__GM_GAIN_ODD_167___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__GM_GAIN_ODD_167___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__TIA_GAIN_ODD_167___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__TIA_GAIN_ODD_167___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__SLM_XLNA_ODD_167___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__SLM_XLNA_ODD_167___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__BQ_GAIN_ODD_167___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__BQ_GAIN_ODD_167___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__XLNA_GAIN_EVEN_167___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__XLNA_GAIN_EVEN_167___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__LNA_GAIN_EVEN_167___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__LNA_GAIN_EVEN_167___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__GM_GAIN_EVEN_167___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__GM_GAIN_EVEN_167___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__TIA_GAIN_EVEN_167___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__TIA_GAIN_EVEN_167___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__SLM_XLNA_EVEN_167___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__SLM_XLNA_EVEN_167___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__BQ_GAIN_EVEN_167___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167__BQ_GAIN_EVEN_167___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_167___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168 (0x005E52A0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__XLNA_GAIN_ODD_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__LNA_GAIN_ODD_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__GM_GAIN_ODD_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__TIA_GAIN_ODD_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__SLM_XLNA_ODD_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__BQ_GAIN_ODD_168___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__XLNA_GAIN_EVEN_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__LNA_GAIN_EVEN_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__GM_GAIN_EVEN_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__TIA_GAIN_EVEN_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__SLM_XLNA_EVEN_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__BQ_GAIN_EVEN_168___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__XLNA_GAIN_ODD_168___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__XLNA_GAIN_ODD_168___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__LNA_GAIN_ODD_168___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__LNA_GAIN_ODD_168___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__GM_GAIN_ODD_168___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__GM_GAIN_ODD_168___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__TIA_GAIN_ODD_168___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__TIA_GAIN_ODD_168___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__SLM_XLNA_ODD_168___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__SLM_XLNA_ODD_168___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__BQ_GAIN_ODD_168___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__BQ_GAIN_ODD_168___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__XLNA_GAIN_EVEN_168___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__XLNA_GAIN_EVEN_168___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__LNA_GAIN_EVEN_168___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__LNA_GAIN_EVEN_168___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__GM_GAIN_EVEN_168___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__GM_GAIN_EVEN_168___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__TIA_GAIN_EVEN_168___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__TIA_GAIN_EVEN_168___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__SLM_XLNA_EVEN_168___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__SLM_XLNA_EVEN_168___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__BQ_GAIN_EVEN_168___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168__BQ_GAIN_EVEN_168___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_168___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169 (0x005E52A4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__XLNA_GAIN_ODD_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__LNA_GAIN_ODD_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__GM_GAIN_ODD_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__TIA_GAIN_ODD_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__SLM_XLNA_ODD_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__BQ_GAIN_ODD_169___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__XLNA_GAIN_EVEN_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__LNA_GAIN_EVEN_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__GM_GAIN_EVEN_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__TIA_GAIN_EVEN_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__SLM_XLNA_EVEN_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__BQ_GAIN_EVEN_169___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__XLNA_GAIN_ODD_169___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__XLNA_GAIN_ODD_169___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__LNA_GAIN_ODD_169___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__LNA_GAIN_ODD_169___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__GM_GAIN_ODD_169___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__GM_GAIN_ODD_169___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__TIA_GAIN_ODD_169___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__TIA_GAIN_ODD_169___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__SLM_XLNA_ODD_169___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__SLM_XLNA_ODD_169___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__BQ_GAIN_ODD_169___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__BQ_GAIN_ODD_169___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__XLNA_GAIN_EVEN_169___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__XLNA_GAIN_EVEN_169___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__LNA_GAIN_EVEN_169___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__LNA_GAIN_EVEN_169___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__GM_GAIN_EVEN_169___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__GM_GAIN_EVEN_169___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__TIA_GAIN_EVEN_169___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__TIA_GAIN_EVEN_169___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__SLM_XLNA_EVEN_169___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__SLM_XLNA_EVEN_169___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__BQ_GAIN_EVEN_169___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169__BQ_GAIN_EVEN_169___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_169___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170 (0x005E52A8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__XLNA_GAIN_ODD_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__LNA_GAIN_ODD_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__GM_GAIN_ODD_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__TIA_GAIN_ODD_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__SLM_XLNA_ODD_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__BQ_GAIN_ODD_170___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__XLNA_GAIN_EVEN_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__LNA_GAIN_EVEN_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__GM_GAIN_EVEN_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__TIA_GAIN_EVEN_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__SLM_XLNA_EVEN_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__BQ_GAIN_EVEN_170___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__XLNA_GAIN_ODD_170___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__XLNA_GAIN_ODD_170___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__LNA_GAIN_ODD_170___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__LNA_GAIN_ODD_170___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__GM_GAIN_ODD_170___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__GM_GAIN_ODD_170___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__TIA_GAIN_ODD_170___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__TIA_GAIN_ODD_170___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__SLM_XLNA_ODD_170___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__SLM_XLNA_ODD_170___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__BQ_GAIN_ODD_170___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__BQ_GAIN_ODD_170___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__XLNA_GAIN_EVEN_170___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__XLNA_GAIN_EVEN_170___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__LNA_GAIN_EVEN_170___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__LNA_GAIN_EVEN_170___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__GM_GAIN_EVEN_170___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__GM_GAIN_EVEN_170___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__TIA_GAIN_EVEN_170___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__TIA_GAIN_EVEN_170___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__SLM_XLNA_EVEN_170___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__SLM_XLNA_EVEN_170___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__BQ_GAIN_EVEN_170___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170__BQ_GAIN_EVEN_170___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_170___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171 (0x005E52AC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__XLNA_GAIN_ODD_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__LNA_GAIN_ODD_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__GM_GAIN_ODD_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__TIA_GAIN_ODD_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__SLM_XLNA_ODD_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__BQ_GAIN_ODD_171___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__XLNA_GAIN_EVEN_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__LNA_GAIN_EVEN_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__GM_GAIN_EVEN_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__TIA_GAIN_EVEN_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__SLM_XLNA_EVEN_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__BQ_GAIN_EVEN_171___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__XLNA_GAIN_ODD_171___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__XLNA_GAIN_ODD_171___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__LNA_GAIN_ODD_171___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__LNA_GAIN_ODD_171___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__GM_GAIN_ODD_171___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__GM_GAIN_ODD_171___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__TIA_GAIN_ODD_171___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__TIA_GAIN_ODD_171___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__SLM_XLNA_ODD_171___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__SLM_XLNA_ODD_171___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__BQ_GAIN_ODD_171___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__BQ_GAIN_ODD_171___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__XLNA_GAIN_EVEN_171___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__XLNA_GAIN_EVEN_171___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__LNA_GAIN_EVEN_171___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__LNA_GAIN_EVEN_171___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__GM_GAIN_EVEN_171___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__GM_GAIN_EVEN_171___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__TIA_GAIN_EVEN_171___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__TIA_GAIN_EVEN_171___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__SLM_XLNA_EVEN_171___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__SLM_XLNA_EVEN_171___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__BQ_GAIN_EVEN_171___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171__BQ_GAIN_EVEN_171___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_171___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172 (0x005E52B0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__XLNA_GAIN_ODD_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__LNA_GAIN_ODD_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__GM_GAIN_ODD_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__TIA_GAIN_ODD_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__SLM_XLNA_ODD_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__BQ_GAIN_ODD_172___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__XLNA_GAIN_EVEN_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__LNA_GAIN_EVEN_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__GM_GAIN_EVEN_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__TIA_GAIN_EVEN_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__SLM_XLNA_EVEN_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__BQ_GAIN_EVEN_172___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__XLNA_GAIN_ODD_172___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__XLNA_GAIN_ODD_172___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__LNA_GAIN_ODD_172___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__LNA_GAIN_ODD_172___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__GM_GAIN_ODD_172___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__GM_GAIN_ODD_172___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__TIA_GAIN_ODD_172___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__TIA_GAIN_ODD_172___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__SLM_XLNA_ODD_172___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__SLM_XLNA_ODD_172___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__BQ_GAIN_ODD_172___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__BQ_GAIN_ODD_172___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__XLNA_GAIN_EVEN_172___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__XLNA_GAIN_EVEN_172___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__LNA_GAIN_EVEN_172___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__LNA_GAIN_EVEN_172___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__GM_GAIN_EVEN_172___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__GM_GAIN_EVEN_172___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__TIA_GAIN_EVEN_172___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__TIA_GAIN_EVEN_172___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__SLM_XLNA_EVEN_172___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__SLM_XLNA_EVEN_172___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__BQ_GAIN_EVEN_172___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172__BQ_GAIN_EVEN_172___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_172___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173 (0x005E52B4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__XLNA_GAIN_ODD_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__LNA_GAIN_ODD_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__GM_GAIN_ODD_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__TIA_GAIN_ODD_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__SLM_XLNA_ODD_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__BQ_GAIN_ODD_173___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__XLNA_GAIN_EVEN_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__LNA_GAIN_EVEN_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__GM_GAIN_EVEN_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__TIA_GAIN_EVEN_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__SLM_XLNA_EVEN_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__BQ_GAIN_EVEN_173___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__XLNA_GAIN_ODD_173___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__XLNA_GAIN_ODD_173___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__LNA_GAIN_ODD_173___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__LNA_GAIN_ODD_173___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__GM_GAIN_ODD_173___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__GM_GAIN_ODD_173___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__TIA_GAIN_ODD_173___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__TIA_GAIN_ODD_173___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__SLM_XLNA_ODD_173___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__SLM_XLNA_ODD_173___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__BQ_GAIN_ODD_173___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__BQ_GAIN_ODD_173___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__XLNA_GAIN_EVEN_173___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__XLNA_GAIN_EVEN_173___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__LNA_GAIN_EVEN_173___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__LNA_GAIN_EVEN_173___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__GM_GAIN_EVEN_173___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__GM_GAIN_EVEN_173___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__TIA_GAIN_EVEN_173___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__TIA_GAIN_EVEN_173___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__SLM_XLNA_EVEN_173___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__SLM_XLNA_EVEN_173___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__BQ_GAIN_EVEN_173___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173__BQ_GAIN_EVEN_173___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_173___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174 (0x005E52B8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__XLNA_GAIN_ODD_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__LNA_GAIN_ODD_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__GM_GAIN_ODD_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__TIA_GAIN_ODD_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__SLM_XLNA_ODD_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__BQ_GAIN_ODD_174___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__XLNA_GAIN_EVEN_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__LNA_GAIN_EVEN_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__GM_GAIN_EVEN_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__TIA_GAIN_EVEN_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__SLM_XLNA_EVEN_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__BQ_GAIN_EVEN_174___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__XLNA_GAIN_ODD_174___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__XLNA_GAIN_ODD_174___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__LNA_GAIN_ODD_174___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__LNA_GAIN_ODD_174___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__GM_GAIN_ODD_174___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__GM_GAIN_ODD_174___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__TIA_GAIN_ODD_174___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__TIA_GAIN_ODD_174___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__SLM_XLNA_ODD_174___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__SLM_XLNA_ODD_174___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__BQ_GAIN_ODD_174___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__BQ_GAIN_ODD_174___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__XLNA_GAIN_EVEN_174___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__XLNA_GAIN_EVEN_174___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__LNA_GAIN_EVEN_174___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__LNA_GAIN_EVEN_174___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__GM_GAIN_EVEN_174___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__GM_GAIN_EVEN_174___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__TIA_GAIN_EVEN_174___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__TIA_GAIN_EVEN_174___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__SLM_XLNA_EVEN_174___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__SLM_XLNA_EVEN_174___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__BQ_GAIN_EVEN_174___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174__BQ_GAIN_EVEN_174___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_174___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175 (0x005E52BC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__XLNA_GAIN_ODD_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__LNA_GAIN_ODD_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__GM_GAIN_ODD_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__TIA_GAIN_ODD_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__SLM_XLNA_ODD_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__BQ_GAIN_ODD_175___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__XLNA_GAIN_EVEN_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__LNA_GAIN_EVEN_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__GM_GAIN_EVEN_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__TIA_GAIN_EVEN_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__SLM_XLNA_EVEN_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__BQ_GAIN_EVEN_175___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__XLNA_GAIN_ODD_175___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__XLNA_GAIN_ODD_175___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__LNA_GAIN_ODD_175___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__LNA_GAIN_ODD_175___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__GM_GAIN_ODD_175___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__GM_GAIN_ODD_175___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__TIA_GAIN_ODD_175___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__TIA_GAIN_ODD_175___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__SLM_XLNA_ODD_175___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__SLM_XLNA_ODD_175___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__BQ_GAIN_ODD_175___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__BQ_GAIN_ODD_175___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__XLNA_GAIN_EVEN_175___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__XLNA_GAIN_EVEN_175___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__LNA_GAIN_EVEN_175___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__LNA_GAIN_EVEN_175___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__GM_GAIN_EVEN_175___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__GM_GAIN_EVEN_175___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__TIA_GAIN_EVEN_175___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__TIA_GAIN_EVEN_175___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__SLM_XLNA_EVEN_175___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__SLM_XLNA_EVEN_175___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__BQ_GAIN_EVEN_175___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175__BQ_GAIN_EVEN_175___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_175___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176 (0x005E52C0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__XLNA_GAIN_ODD_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__LNA_GAIN_ODD_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__GM_GAIN_ODD_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__TIA_GAIN_ODD_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__SLM_XLNA_ODD_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__BQ_GAIN_ODD_176___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__XLNA_GAIN_EVEN_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__LNA_GAIN_EVEN_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__GM_GAIN_EVEN_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__TIA_GAIN_EVEN_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__SLM_XLNA_EVEN_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__BQ_GAIN_EVEN_176___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__XLNA_GAIN_ODD_176___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__XLNA_GAIN_ODD_176___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__LNA_GAIN_ODD_176___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__LNA_GAIN_ODD_176___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__GM_GAIN_ODD_176___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__GM_GAIN_ODD_176___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__TIA_GAIN_ODD_176___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__TIA_GAIN_ODD_176___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__SLM_XLNA_ODD_176___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__SLM_XLNA_ODD_176___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__BQ_GAIN_ODD_176___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__BQ_GAIN_ODD_176___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__XLNA_GAIN_EVEN_176___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__XLNA_GAIN_EVEN_176___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__LNA_GAIN_EVEN_176___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__LNA_GAIN_EVEN_176___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__GM_GAIN_EVEN_176___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__GM_GAIN_EVEN_176___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__TIA_GAIN_EVEN_176___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__TIA_GAIN_EVEN_176___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__SLM_XLNA_EVEN_176___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__SLM_XLNA_EVEN_176___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__BQ_GAIN_EVEN_176___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176__BQ_GAIN_EVEN_176___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_176___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177 (0x005E52C4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__XLNA_GAIN_ODD_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__LNA_GAIN_ODD_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__GM_GAIN_ODD_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__TIA_GAIN_ODD_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__SLM_XLNA_ODD_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__BQ_GAIN_ODD_177___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__XLNA_GAIN_EVEN_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__LNA_GAIN_EVEN_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__GM_GAIN_EVEN_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__TIA_GAIN_EVEN_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__SLM_XLNA_EVEN_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__BQ_GAIN_EVEN_177___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__XLNA_GAIN_ODD_177___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__XLNA_GAIN_ODD_177___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__LNA_GAIN_ODD_177___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__LNA_GAIN_ODD_177___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__GM_GAIN_ODD_177___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__GM_GAIN_ODD_177___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__TIA_GAIN_ODD_177___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__TIA_GAIN_ODD_177___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__SLM_XLNA_ODD_177___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__SLM_XLNA_ODD_177___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__BQ_GAIN_ODD_177___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__BQ_GAIN_ODD_177___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__XLNA_GAIN_EVEN_177___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__XLNA_GAIN_EVEN_177___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__LNA_GAIN_EVEN_177___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__LNA_GAIN_EVEN_177___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__GM_GAIN_EVEN_177___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__GM_GAIN_EVEN_177___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__TIA_GAIN_EVEN_177___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__TIA_GAIN_EVEN_177___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__SLM_XLNA_EVEN_177___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__SLM_XLNA_EVEN_177___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__BQ_GAIN_EVEN_177___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177__BQ_GAIN_EVEN_177___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_177___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178 (0x005E52C8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__XLNA_GAIN_ODD_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__LNA_GAIN_ODD_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__GM_GAIN_ODD_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__TIA_GAIN_ODD_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__SLM_XLNA_ODD_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__BQ_GAIN_ODD_178___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__XLNA_GAIN_EVEN_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__LNA_GAIN_EVEN_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__GM_GAIN_EVEN_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__TIA_GAIN_EVEN_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__SLM_XLNA_EVEN_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__BQ_GAIN_EVEN_178___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__XLNA_GAIN_ODD_178___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__XLNA_GAIN_ODD_178___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__LNA_GAIN_ODD_178___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__LNA_GAIN_ODD_178___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__GM_GAIN_ODD_178___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__GM_GAIN_ODD_178___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__TIA_GAIN_ODD_178___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__TIA_GAIN_ODD_178___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__SLM_XLNA_ODD_178___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__SLM_XLNA_ODD_178___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__BQ_GAIN_ODD_178___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__BQ_GAIN_ODD_178___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__XLNA_GAIN_EVEN_178___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__XLNA_GAIN_EVEN_178___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__LNA_GAIN_EVEN_178___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__LNA_GAIN_EVEN_178___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__GM_GAIN_EVEN_178___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__GM_GAIN_EVEN_178___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__TIA_GAIN_EVEN_178___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__TIA_GAIN_EVEN_178___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__SLM_XLNA_EVEN_178___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__SLM_XLNA_EVEN_178___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__BQ_GAIN_EVEN_178___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178__BQ_GAIN_EVEN_178___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_178___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179 (0x005E52CC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__XLNA_GAIN_ODD_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__LNA_GAIN_ODD_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__GM_GAIN_ODD_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__TIA_GAIN_ODD_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__SLM_XLNA_ODD_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__BQ_GAIN_ODD_179___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__XLNA_GAIN_EVEN_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__LNA_GAIN_EVEN_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__GM_GAIN_EVEN_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__TIA_GAIN_EVEN_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__SLM_XLNA_EVEN_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__BQ_GAIN_EVEN_179___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__XLNA_GAIN_ODD_179___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__XLNA_GAIN_ODD_179___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__LNA_GAIN_ODD_179___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__LNA_GAIN_ODD_179___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__GM_GAIN_ODD_179___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__GM_GAIN_ODD_179___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__TIA_GAIN_ODD_179___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__TIA_GAIN_ODD_179___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__SLM_XLNA_ODD_179___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__SLM_XLNA_ODD_179___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__BQ_GAIN_ODD_179___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__BQ_GAIN_ODD_179___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__XLNA_GAIN_EVEN_179___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__XLNA_GAIN_EVEN_179___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__LNA_GAIN_EVEN_179___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__LNA_GAIN_EVEN_179___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__GM_GAIN_EVEN_179___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__GM_GAIN_EVEN_179___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__TIA_GAIN_EVEN_179___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__TIA_GAIN_EVEN_179___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__SLM_XLNA_EVEN_179___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__SLM_XLNA_EVEN_179___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__BQ_GAIN_EVEN_179___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179__BQ_GAIN_EVEN_179___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_179___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180 (0x005E52D0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__XLNA_GAIN_ODD_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__LNA_GAIN_ODD_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__GM_GAIN_ODD_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__TIA_GAIN_ODD_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__SLM_XLNA_ODD_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__BQ_GAIN_ODD_180___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__XLNA_GAIN_EVEN_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__LNA_GAIN_EVEN_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__GM_GAIN_EVEN_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__TIA_GAIN_EVEN_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__SLM_XLNA_EVEN_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__BQ_GAIN_EVEN_180___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__XLNA_GAIN_ODD_180___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__XLNA_GAIN_ODD_180___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__LNA_GAIN_ODD_180___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__LNA_GAIN_ODD_180___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__GM_GAIN_ODD_180___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__GM_GAIN_ODD_180___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__TIA_GAIN_ODD_180___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__TIA_GAIN_ODD_180___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__SLM_XLNA_ODD_180___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__SLM_XLNA_ODD_180___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__BQ_GAIN_ODD_180___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__BQ_GAIN_ODD_180___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__XLNA_GAIN_EVEN_180___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__XLNA_GAIN_EVEN_180___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__LNA_GAIN_EVEN_180___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__LNA_GAIN_EVEN_180___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__GM_GAIN_EVEN_180___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__GM_GAIN_EVEN_180___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__TIA_GAIN_EVEN_180___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__TIA_GAIN_EVEN_180___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__SLM_XLNA_EVEN_180___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__SLM_XLNA_EVEN_180___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__BQ_GAIN_EVEN_180___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180__BQ_GAIN_EVEN_180___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_180___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181 (0x005E52D4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__XLNA_GAIN_ODD_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__LNA_GAIN_ODD_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__GM_GAIN_ODD_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__TIA_GAIN_ODD_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__SLM_XLNA_ODD_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__BQ_GAIN_ODD_181___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__XLNA_GAIN_EVEN_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__LNA_GAIN_EVEN_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__GM_GAIN_EVEN_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__TIA_GAIN_EVEN_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__SLM_XLNA_EVEN_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__BQ_GAIN_EVEN_181___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__XLNA_GAIN_ODD_181___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__XLNA_GAIN_ODD_181___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__LNA_GAIN_ODD_181___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__LNA_GAIN_ODD_181___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__GM_GAIN_ODD_181___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__GM_GAIN_ODD_181___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__TIA_GAIN_ODD_181___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__TIA_GAIN_ODD_181___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__SLM_XLNA_ODD_181___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__SLM_XLNA_ODD_181___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__BQ_GAIN_ODD_181___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__BQ_GAIN_ODD_181___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__XLNA_GAIN_EVEN_181___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__XLNA_GAIN_EVEN_181___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__LNA_GAIN_EVEN_181___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__LNA_GAIN_EVEN_181___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__GM_GAIN_EVEN_181___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__GM_GAIN_EVEN_181___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__TIA_GAIN_EVEN_181___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__TIA_GAIN_EVEN_181___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__SLM_XLNA_EVEN_181___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__SLM_XLNA_EVEN_181___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__BQ_GAIN_EVEN_181___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181__BQ_GAIN_EVEN_181___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_181___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182 (0x005E52D8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__XLNA_GAIN_ODD_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__LNA_GAIN_ODD_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__GM_GAIN_ODD_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__TIA_GAIN_ODD_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__SLM_XLNA_ODD_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__BQ_GAIN_ODD_182___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__XLNA_GAIN_EVEN_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__LNA_GAIN_EVEN_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__GM_GAIN_EVEN_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__TIA_GAIN_EVEN_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__SLM_XLNA_EVEN_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__BQ_GAIN_EVEN_182___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__XLNA_GAIN_ODD_182___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__XLNA_GAIN_ODD_182___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__LNA_GAIN_ODD_182___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__LNA_GAIN_ODD_182___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__GM_GAIN_ODD_182___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__GM_GAIN_ODD_182___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__TIA_GAIN_ODD_182___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__TIA_GAIN_ODD_182___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__SLM_XLNA_ODD_182___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__SLM_XLNA_ODD_182___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__BQ_GAIN_ODD_182___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__BQ_GAIN_ODD_182___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__XLNA_GAIN_EVEN_182___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__XLNA_GAIN_EVEN_182___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__LNA_GAIN_EVEN_182___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__LNA_GAIN_EVEN_182___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__GM_GAIN_EVEN_182___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__GM_GAIN_EVEN_182___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__TIA_GAIN_EVEN_182___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__TIA_GAIN_EVEN_182___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__SLM_XLNA_EVEN_182___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__SLM_XLNA_EVEN_182___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__BQ_GAIN_EVEN_182___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182__BQ_GAIN_EVEN_182___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_182___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183 (0x005E52DC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__XLNA_GAIN_ODD_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__LNA_GAIN_ODD_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__GM_GAIN_ODD_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__TIA_GAIN_ODD_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__SLM_XLNA_ODD_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__BQ_GAIN_ODD_183___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__XLNA_GAIN_EVEN_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__LNA_GAIN_EVEN_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__GM_GAIN_EVEN_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__TIA_GAIN_EVEN_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__SLM_XLNA_EVEN_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__BQ_GAIN_EVEN_183___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__XLNA_GAIN_ODD_183___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__XLNA_GAIN_ODD_183___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__LNA_GAIN_ODD_183___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__LNA_GAIN_ODD_183___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__GM_GAIN_ODD_183___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__GM_GAIN_ODD_183___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__TIA_GAIN_ODD_183___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__TIA_GAIN_ODD_183___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__SLM_XLNA_ODD_183___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__SLM_XLNA_ODD_183___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__BQ_GAIN_ODD_183___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__BQ_GAIN_ODD_183___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__XLNA_GAIN_EVEN_183___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__XLNA_GAIN_EVEN_183___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__LNA_GAIN_EVEN_183___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__LNA_GAIN_EVEN_183___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__GM_GAIN_EVEN_183___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__GM_GAIN_EVEN_183___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__TIA_GAIN_EVEN_183___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__TIA_GAIN_EVEN_183___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__SLM_XLNA_EVEN_183___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__SLM_XLNA_EVEN_183___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__BQ_GAIN_EVEN_183___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183__BQ_GAIN_EVEN_183___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_183___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184 (0x005E52E0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__XLNA_GAIN_ODD_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__LNA_GAIN_ODD_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__GM_GAIN_ODD_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__TIA_GAIN_ODD_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__SLM_XLNA_ODD_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__BQ_GAIN_ODD_184___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__XLNA_GAIN_EVEN_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__LNA_GAIN_EVEN_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__GM_GAIN_EVEN_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__TIA_GAIN_EVEN_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__SLM_XLNA_EVEN_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__BQ_GAIN_EVEN_184___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__XLNA_GAIN_ODD_184___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__XLNA_GAIN_ODD_184___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__LNA_GAIN_ODD_184___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__LNA_GAIN_ODD_184___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__GM_GAIN_ODD_184___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__GM_GAIN_ODD_184___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__TIA_GAIN_ODD_184___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__TIA_GAIN_ODD_184___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__SLM_XLNA_ODD_184___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__SLM_XLNA_ODD_184___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__BQ_GAIN_ODD_184___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__BQ_GAIN_ODD_184___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__XLNA_GAIN_EVEN_184___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__XLNA_GAIN_EVEN_184___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__LNA_GAIN_EVEN_184___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__LNA_GAIN_EVEN_184___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__GM_GAIN_EVEN_184___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__GM_GAIN_EVEN_184___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__TIA_GAIN_EVEN_184___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__TIA_GAIN_EVEN_184___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__SLM_XLNA_EVEN_184___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__SLM_XLNA_EVEN_184___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__BQ_GAIN_EVEN_184___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184__BQ_GAIN_EVEN_184___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_184___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185 (0x005E52E4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__XLNA_GAIN_ODD_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__LNA_GAIN_ODD_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__GM_GAIN_ODD_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__TIA_GAIN_ODD_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__SLM_XLNA_ODD_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__BQ_GAIN_ODD_185___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__XLNA_GAIN_EVEN_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__LNA_GAIN_EVEN_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__GM_GAIN_EVEN_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__TIA_GAIN_EVEN_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__SLM_XLNA_EVEN_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__BQ_GAIN_EVEN_185___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__XLNA_GAIN_ODD_185___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__XLNA_GAIN_ODD_185___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__LNA_GAIN_ODD_185___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__LNA_GAIN_ODD_185___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__GM_GAIN_ODD_185___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__GM_GAIN_ODD_185___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__TIA_GAIN_ODD_185___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__TIA_GAIN_ODD_185___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__SLM_XLNA_ODD_185___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__SLM_XLNA_ODD_185___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__BQ_GAIN_ODD_185___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__BQ_GAIN_ODD_185___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__XLNA_GAIN_EVEN_185___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__XLNA_GAIN_EVEN_185___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__LNA_GAIN_EVEN_185___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__LNA_GAIN_EVEN_185___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__GM_GAIN_EVEN_185___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__GM_GAIN_EVEN_185___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__TIA_GAIN_EVEN_185___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__TIA_GAIN_EVEN_185___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__SLM_XLNA_EVEN_185___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__SLM_XLNA_EVEN_185___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__BQ_GAIN_EVEN_185___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185__BQ_GAIN_EVEN_185___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_185___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186 (0x005E52E8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__XLNA_GAIN_ODD_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__LNA_GAIN_ODD_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__GM_GAIN_ODD_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__TIA_GAIN_ODD_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__SLM_XLNA_ODD_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__BQ_GAIN_ODD_186___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__XLNA_GAIN_EVEN_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__LNA_GAIN_EVEN_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__GM_GAIN_EVEN_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__TIA_GAIN_EVEN_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__SLM_XLNA_EVEN_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__BQ_GAIN_EVEN_186___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__XLNA_GAIN_ODD_186___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__XLNA_GAIN_ODD_186___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__LNA_GAIN_ODD_186___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__LNA_GAIN_ODD_186___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__GM_GAIN_ODD_186___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__GM_GAIN_ODD_186___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__TIA_GAIN_ODD_186___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__TIA_GAIN_ODD_186___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__SLM_XLNA_ODD_186___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__SLM_XLNA_ODD_186___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__BQ_GAIN_ODD_186___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__BQ_GAIN_ODD_186___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__XLNA_GAIN_EVEN_186___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__XLNA_GAIN_EVEN_186___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__LNA_GAIN_EVEN_186___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__LNA_GAIN_EVEN_186___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__GM_GAIN_EVEN_186___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__GM_GAIN_EVEN_186___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__TIA_GAIN_EVEN_186___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__TIA_GAIN_EVEN_186___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__SLM_XLNA_EVEN_186___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__SLM_XLNA_EVEN_186___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__BQ_GAIN_EVEN_186___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186__BQ_GAIN_EVEN_186___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_186___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187 (0x005E52EC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__XLNA_GAIN_ODD_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__LNA_GAIN_ODD_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__GM_GAIN_ODD_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__TIA_GAIN_ODD_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__SLM_XLNA_ODD_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__BQ_GAIN_ODD_187___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__XLNA_GAIN_EVEN_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__LNA_GAIN_EVEN_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__GM_GAIN_EVEN_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__TIA_GAIN_EVEN_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__SLM_XLNA_EVEN_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__BQ_GAIN_EVEN_187___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__XLNA_GAIN_ODD_187___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__XLNA_GAIN_ODD_187___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__LNA_GAIN_ODD_187___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__LNA_GAIN_ODD_187___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__GM_GAIN_ODD_187___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__GM_GAIN_ODD_187___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__TIA_GAIN_ODD_187___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__TIA_GAIN_ODD_187___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__SLM_XLNA_ODD_187___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__SLM_XLNA_ODD_187___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__BQ_GAIN_ODD_187___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__BQ_GAIN_ODD_187___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__XLNA_GAIN_EVEN_187___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__XLNA_GAIN_EVEN_187___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__LNA_GAIN_EVEN_187___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__LNA_GAIN_EVEN_187___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__GM_GAIN_EVEN_187___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__GM_GAIN_EVEN_187___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__TIA_GAIN_EVEN_187___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__TIA_GAIN_EVEN_187___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__SLM_XLNA_EVEN_187___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__SLM_XLNA_EVEN_187___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__BQ_GAIN_EVEN_187___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187__BQ_GAIN_EVEN_187___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_187___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188 (0x005E52F0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__XLNA_GAIN_ODD_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__LNA_GAIN_ODD_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__GM_GAIN_ODD_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__TIA_GAIN_ODD_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__SLM_XLNA_ODD_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__BQ_GAIN_ODD_188___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__XLNA_GAIN_EVEN_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__LNA_GAIN_EVEN_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__GM_GAIN_EVEN_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__TIA_GAIN_EVEN_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__SLM_XLNA_EVEN_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__BQ_GAIN_EVEN_188___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__XLNA_GAIN_ODD_188___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__XLNA_GAIN_ODD_188___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__LNA_GAIN_ODD_188___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__LNA_GAIN_ODD_188___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__GM_GAIN_ODD_188___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__GM_GAIN_ODD_188___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__TIA_GAIN_ODD_188___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__TIA_GAIN_ODD_188___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__SLM_XLNA_ODD_188___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__SLM_XLNA_ODD_188___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__BQ_GAIN_ODD_188___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__BQ_GAIN_ODD_188___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__XLNA_GAIN_EVEN_188___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__XLNA_GAIN_EVEN_188___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__LNA_GAIN_EVEN_188___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__LNA_GAIN_EVEN_188___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__GM_GAIN_EVEN_188___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__GM_GAIN_EVEN_188___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__TIA_GAIN_EVEN_188___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__TIA_GAIN_EVEN_188___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__SLM_XLNA_EVEN_188___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__SLM_XLNA_EVEN_188___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__BQ_GAIN_EVEN_188___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188__BQ_GAIN_EVEN_188___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_188___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189 (0x005E52F4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__XLNA_GAIN_ODD_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__LNA_GAIN_ODD_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__GM_GAIN_ODD_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__TIA_GAIN_ODD_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__SLM_XLNA_ODD_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__BQ_GAIN_ODD_189___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__XLNA_GAIN_EVEN_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__LNA_GAIN_EVEN_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__GM_GAIN_EVEN_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__TIA_GAIN_EVEN_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__SLM_XLNA_EVEN_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__BQ_GAIN_EVEN_189___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__XLNA_GAIN_ODD_189___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__XLNA_GAIN_ODD_189___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__LNA_GAIN_ODD_189___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__LNA_GAIN_ODD_189___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__GM_GAIN_ODD_189___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__GM_GAIN_ODD_189___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__TIA_GAIN_ODD_189___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__TIA_GAIN_ODD_189___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__SLM_XLNA_ODD_189___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__SLM_XLNA_ODD_189___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__BQ_GAIN_ODD_189___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__BQ_GAIN_ODD_189___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__XLNA_GAIN_EVEN_189___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__XLNA_GAIN_EVEN_189___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__LNA_GAIN_EVEN_189___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__LNA_GAIN_EVEN_189___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__GM_GAIN_EVEN_189___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__GM_GAIN_EVEN_189___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__TIA_GAIN_EVEN_189___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__TIA_GAIN_EVEN_189___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__SLM_XLNA_EVEN_189___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__SLM_XLNA_EVEN_189___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__BQ_GAIN_EVEN_189___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189__BQ_GAIN_EVEN_189___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_189___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190 (0x005E52F8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__XLNA_GAIN_ODD_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__LNA_GAIN_ODD_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__GM_GAIN_ODD_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__TIA_GAIN_ODD_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__SLM_XLNA_ODD_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__BQ_GAIN_ODD_190___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__XLNA_GAIN_EVEN_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__LNA_GAIN_EVEN_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__GM_GAIN_EVEN_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__TIA_GAIN_EVEN_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__SLM_XLNA_EVEN_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__BQ_GAIN_EVEN_190___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__XLNA_GAIN_ODD_190___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__XLNA_GAIN_ODD_190___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__LNA_GAIN_ODD_190___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__LNA_GAIN_ODD_190___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__GM_GAIN_ODD_190___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__GM_GAIN_ODD_190___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__TIA_GAIN_ODD_190___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__TIA_GAIN_ODD_190___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__SLM_XLNA_ODD_190___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__SLM_XLNA_ODD_190___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__BQ_GAIN_ODD_190___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__BQ_GAIN_ODD_190___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__XLNA_GAIN_EVEN_190___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__XLNA_GAIN_EVEN_190___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__LNA_GAIN_EVEN_190___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__LNA_GAIN_EVEN_190___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__GM_GAIN_EVEN_190___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__GM_GAIN_EVEN_190___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__TIA_GAIN_EVEN_190___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__TIA_GAIN_EVEN_190___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__SLM_XLNA_EVEN_190___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__SLM_XLNA_EVEN_190___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__BQ_GAIN_EVEN_190___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190__BQ_GAIN_EVEN_190___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_190___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191 (0x005E52FC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__XLNA_GAIN_ODD_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__LNA_GAIN_ODD_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__GM_GAIN_ODD_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__TIA_GAIN_ODD_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__SLM_XLNA_ODD_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__BQ_GAIN_ODD_191___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__XLNA_GAIN_EVEN_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__LNA_GAIN_EVEN_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__GM_GAIN_EVEN_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__TIA_GAIN_EVEN_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__SLM_XLNA_EVEN_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__BQ_GAIN_EVEN_191___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__XLNA_GAIN_ODD_191___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__XLNA_GAIN_ODD_191___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__LNA_GAIN_ODD_191___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__LNA_GAIN_ODD_191___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__GM_GAIN_ODD_191___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__GM_GAIN_ODD_191___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__TIA_GAIN_ODD_191___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__TIA_GAIN_ODD_191___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__SLM_XLNA_ODD_191___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__SLM_XLNA_ODD_191___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__BQ_GAIN_ODD_191___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__BQ_GAIN_ODD_191___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__XLNA_GAIN_EVEN_191___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__XLNA_GAIN_EVEN_191___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__LNA_GAIN_EVEN_191___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__LNA_GAIN_EVEN_191___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__GM_GAIN_EVEN_191___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__GM_GAIN_EVEN_191___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__TIA_GAIN_EVEN_191___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__TIA_GAIN_EVEN_191___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__SLM_XLNA_EVEN_191___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__SLM_XLNA_EVEN_191___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__BQ_GAIN_EVEN_191___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191__BQ_GAIN_EVEN_191___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_191___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192 (0x005E5300) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__XLNA_GAIN_ODD_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__LNA_GAIN_ODD_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__GM_GAIN_ODD_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__TIA_GAIN_ODD_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__SLM_XLNA_ODD_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__BQ_GAIN_ODD_192___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__XLNA_GAIN_EVEN_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__LNA_GAIN_EVEN_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__GM_GAIN_EVEN_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__TIA_GAIN_EVEN_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__SLM_XLNA_EVEN_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__BQ_GAIN_EVEN_192___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__XLNA_GAIN_ODD_192___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__XLNA_GAIN_ODD_192___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__LNA_GAIN_ODD_192___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__LNA_GAIN_ODD_192___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__GM_GAIN_ODD_192___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__GM_GAIN_ODD_192___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__TIA_GAIN_ODD_192___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__TIA_GAIN_ODD_192___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__SLM_XLNA_ODD_192___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__SLM_XLNA_ODD_192___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__BQ_GAIN_ODD_192___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__BQ_GAIN_ODD_192___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__XLNA_GAIN_EVEN_192___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__XLNA_GAIN_EVEN_192___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__LNA_GAIN_EVEN_192___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__LNA_GAIN_EVEN_192___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__GM_GAIN_EVEN_192___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__GM_GAIN_EVEN_192___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__TIA_GAIN_EVEN_192___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__TIA_GAIN_EVEN_192___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__SLM_XLNA_EVEN_192___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__SLM_XLNA_EVEN_192___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__BQ_GAIN_EVEN_192___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192__BQ_GAIN_EVEN_192___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_192___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193 (0x005E5304) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__XLNA_GAIN_ODD_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__LNA_GAIN_ODD_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__GM_GAIN_ODD_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__TIA_GAIN_ODD_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__SLM_XLNA_ODD_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__BQ_GAIN_ODD_193___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__XLNA_GAIN_EVEN_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__LNA_GAIN_EVEN_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__GM_GAIN_EVEN_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__TIA_GAIN_EVEN_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__SLM_XLNA_EVEN_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__BQ_GAIN_EVEN_193___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__XLNA_GAIN_ODD_193___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__XLNA_GAIN_ODD_193___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__LNA_GAIN_ODD_193___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__LNA_GAIN_ODD_193___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__GM_GAIN_ODD_193___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__GM_GAIN_ODD_193___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__TIA_GAIN_ODD_193___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__TIA_GAIN_ODD_193___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__SLM_XLNA_ODD_193___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__SLM_XLNA_ODD_193___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__BQ_GAIN_ODD_193___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__BQ_GAIN_ODD_193___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__XLNA_GAIN_EVEN_193___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__XLNA_GAIN_EVEN_193___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__LNA_GAIN_EVEN_193___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__LNA_GAIN_EVEN_193___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__GM_GAIN_EVEN_193___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__GM_GAIN_EVEN_193___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__TIA_GAIN_EVEN_193___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__TIA_GAIN_EVEN_193___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__SLM_XLNA_EVEN_193___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__SLM_XLNA_EVEN_193___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__BQ_GAIN_EVEN_193___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193__BQ_GAIN_EVEN_193___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_193___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194 (0x005E5308) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__XLNA_GAIN_ODD_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__LNA_GAIN_ODD_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__GM_GAIN_ODD_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__TIA_GAIN_ODD_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__SLM_XLNA_ODD_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__BQ_GAIN_ODD_194___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__XLNA_GAIN_EVEN_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__LNA_GAIN_EVEN_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__GM_GAIN_EVEN_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__TIA_GAIN_EVEN_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__SLM_XLNA_EVEN_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__BQ_GAIN_EVEN_194___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__XLNA_GAIN_ODD_194___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__XLNA_GAIN_ODD_194___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__LNA_GAIN_ODD_194___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__LNA_GAIN_ODD_194___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__GM_GAIN_ODD_194___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__GM_GAIN_ODD_194___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__TIA_GAIN_ODD_194___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__TIA_GAIN_ODD_194___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__SLM_XLNA_ODD_194___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__SLM_XLNA_ODD_194___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__BQ_GAIN_ODD_194___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__BQ_GAIN_ODD_194___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__XLNA_GAIN_EVEN_194___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__XLNA_GAIN_EVEN_194___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__LNA_GAIN_EVEN_194___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__LNA_GAIN_EVEN_194___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__GM_GAIN_EVEN_194___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__GM_GAIN_EVEN_194___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__TIA_GAIN_EVEN_194___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__TIA_GAIN_EVEN_194___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__SLM_XLNA_EVEN_194___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__SLM_XLNA_EVEN_194___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__BQ_GAIN_EVEN_194___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194__BQ_GAIN_EVEN_194___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_194___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195 (0x005E530C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__XLNA_GAIN_ODD_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__LNA_GAIN_ODD_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__GM_GAIN_ODD_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__TIA_GAIN_ODD_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__SLM_XLNA_ODD_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__BQ_GAIN_ODD_195___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__XLNA_GAIN_EVEN_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__LNA_GAIN_EVEN_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__GM_GAIN_EVEN_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__TIA_GAIN_EVEN_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__SLM_XLNA_EVEN_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__BQ_GAIN_EVEN_195___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__XLNA_GAIN_ODD_195___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__XLNA_GAIN_ODD_195___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__LNA_GAIN_ODD_195___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__LNA_GAIN_ODD_195___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__GM_GAIN_ODD_195___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__GM_GAIN_ODD_195___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__TIA_GAIN_ODD_195___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__TIA_GAIN_ODD_195___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__SLM_XLNA_ODD_195___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__SLM_XLNA_ODD_195___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__BQ_GAIN_ODD_195___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__BQ_GAIN_ODD_195___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__XLNA_GAIN_EVEN_195___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__XLNA_GAIN_EVEN_195___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__LNA_GAIN_EVEN_195___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__LNA_GAIN_EVEN_195___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__GM_GAIN_EVEN_195___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__GM_GAIN_EVEN_195___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__TIA_GAIN_EVEN_195___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__TIA_GAIN_EVEN_195___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__SLM_XLNA_EVEN_195___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__SLM_XLNA_EVEN_195___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__BQ_GAIN_EVEN_195___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195__BQ_GAIN_EVEN_195___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_195___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196 (0x005E5310) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__XLNA_GAIN_ODD_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__LNA_GAIN_ODD_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__GM_GAIN_ODD_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__TIA_GAIN_ODD_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__SLM_XLNA_ODD_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__BQ_GAIN_ODD_196___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__XLNA_GAIN_EVEN_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__LNA_GAIN_EVEN_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__GM_GAIN_EVEN_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__TIA_GAIN_EVEN_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__SLM_XLNA_EVEN_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__BQ_GAIN_EVEN_196___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__XLNA_GAIN_ODD_196___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__XLNA_GAIN_ODD_196___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__LNA_GAIN_ODD_196___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__LNA_GAIN_ODD_196___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__GM_GAIN_ODD_196___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__GM_GAIN_ODD_196___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__TIA_GAIN_ODD_196___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__TIA_GAIN_ODD_196___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__SLM_XLNA_ODD_196___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__SLM_XLNA_ODD_196___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__BQ_GAIN_ODD_196___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__BQ_GAIN_ODD_196___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__XLNA_GAIN_EVEN_196___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__XLNA_GAIN_EVEN_196___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__LNA_GAIN_EVEN_196___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__LNA_GAIN_EVEN_196___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__GM_GAIN_EVEN_196___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__GM_GAIN_EVEN_196___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__TIA_GAIN_EVEN_196___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__TIA_GAIN_EVEN_196___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__SLM_XLNA_EVEN_196___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__SLM_XLNA_EVEN_196___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__BQ_GAIN_EVEN_196___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196__BQ_GAIN_EVEN_196___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_196___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197 (0x005E5314) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__XLNA_GAIN_ODD_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__LNA_GAIN_ODD_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__GM_GAIN_ODD_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__TIA_GAIN_ODD_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__SLM_XLNA_ODD_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__BQ_GAIN_ODD_197___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__XLNA_GAIN_EVEN_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__LNA_GAIN_EVEN_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__GM_GAIN_EVEN_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__TIA_GAIN_EVEN_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__SLM_XLNA_EVEN_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__BQ_GAIN_EVEN_197___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__XLNA_GAIN_ODD_197___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__XLNA_GAIN_ODD_197___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__LNA_GAIN_ODD_197___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__LNA_GAIN_ODD_197___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__GM_GAIN_ODD_197___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__GM_GAIN_ODD_197___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__TIA_GAIN_ODD_197___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__TIA_GAIN_ODD_197___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__SLM_XLNA_ODD_197___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__SLM_XLNA_ODD_197___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__BQ_GAIN_ODD_197___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__BQ_GAIN_ODD_197___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__XLNA_GAIN_EVEN_197___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__XLNA_GAIN_EVEN_197___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__LNA_GAIN_EVEN_197___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__LNA_GAIN_EVEN_197___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__GM_GAIN_EVEN_197___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__GM_GAIN_EVEN_197___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__TIA_GAIN_EVEN_197___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__TIA_GAIN_EVEN_197___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__SLM_XLNA_EVEN_197___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__SLM_XLNA_EVEN_197___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__BQ_GAIN_EVEN_197___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197__BQ_GAIN_EVEN_197___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_197___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198 (0x005E5318) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__XLNA_GAIN_ODD_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__LNA_GAIN_ODD_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__GM_GAIN_ODD_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__TIA_GAIN_ODD_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__SLM_XLNA_ODD_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__BQ_GAIN_ODD_198___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__XLNA_GAIN_EVEN_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__LNA_GAIN_EVEN_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__GM_GAIN_EVEN_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__TIA_GAIN_EVEN_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__SLM_XLNA_EVEN_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__BQ_GAIN_EVEN_198___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__XLNA_GAIN_ODD_198___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__XLNA_GAIN_ODD_198___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__LNA_GAIN_ODD_198___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__LNA_GAIN_ODD_198___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__GM_GAIN_ODD_198___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__GM_GAIN_ODD_198___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__TIA_GAIN_ODD_198___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__TIA_GAIN_ODD_198___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__SLM_XLNA_ODD_198___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__SLM_XLNA_ODD_198___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__BQ_GAIN_ODD_198___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__BQ_GAIN_ODD_198___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__XLNA_GAIN_EVEN_198___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__XLNA_GAIN_EVEN_198___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__LNA_GAIN_EVEN_198___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__LNA_GAIN_EVEN_198___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__GM_GAIN_EVEN_198___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__GM_GAIN_EVEN_198___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__TIA_GAIN_EVEN_198___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__TIA_GAIN_EVEN_198___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__SLM_XLNA_EVEN_198___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__SLM_XLNA_EVEN_198___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__BQ_GAIN_EVEN_198___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198__BQ_GAIN_EVEN_198___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_198___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199 (0x005E531C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__XLNA_GAIN_ODD_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__LNA_GAIN_ODD_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__GM_GAIN_ODD_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__TIA_GAIN_ODD_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__SLM_XLNA_ODD_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__BQ_GAIN_ODD_199___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__XLNA_GAIN_EVEN_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__LNA_GAIN_EVEN_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__GM_GAIN_EVEN_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__TIA_GAIN_EVEN_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__SLM_XLNA_EVEN_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__BQ_GAIN_EVEN_199___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__XLNA_GAIN_ODD_199___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__XLNA_GAIN_ODD_199___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__LNA_GAIN_ODD_199___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__LNA_GAIN_ODD_199___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__GM_GAIN_ODD_199___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__GM_GAIN_ODD_199___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__TIA_GAIN_ODD_199___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__TIA_GAIN_ODD_199___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__SLM_XLNA_ODD_199___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__SLM_XLNA_ODD_199___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__BQ_GAIN_ODD_199___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__BQ_GAIN_ODD_199___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__XLNA_GAIN_EVEN_199___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__XLNA_GAIN_EVEN_199___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__LNA_GAIN_EVEN_199___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__LNA_GAIN_EVEN_199___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__GM_GAIN_EVEN_199___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__GM_GAIN_EVEN_199___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__TIA_GAIN_EVEN_199___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__TIA_GAIN_EVEN_199___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__SLM_XLNA_EVEN_199___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__SLM_XLNA_EVEN_199___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__BQ_GAIN_EVEN_199___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199__BQ_GAIN_EVEN_199___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_199___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200 (0x005E5320) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__XLNA_GAIN_ODD_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__LNA_GAIN_ODD_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__GM_GAIN_ODD_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__TIA_GAIN_ODD_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__SLM_XLNA_ODD_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__BQ_GAIN_ODD_200___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__XLNA_GAIN_EVEN_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__LNA_GAIN_EVEN_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__GM_GAIN_EVEN_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__TIA_GAIN_EVEN_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__SLM_XLNA_EVEN_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__BQ_GAIN_EVEN_200___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__XLNA_GAIN_ODD_200___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__XLNA_GAIN_ODD_200___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__LNA_GAIN_ODD_200___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__LNA_GAIN_ODD_200___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__GM_GAIN_ODD_200___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__GM_GAIN_ODD_200___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__TIA_GAIN_ODD_200___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__TIA_GAIN_ODD_200___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__SLM_XLNA_ODD_200___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__SLM_XLNA_ODD_200___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__BQ_GAIN_ODD_200___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__BQ_GAIN_ODD_200___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__XLNA_GAIN_EVEN_200___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__XLNA_GAIN_EVEN_200___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__LNA_GAIN_EVEN_200___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__LNA_GAIN_EVEN_200___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__GM_GAIN_EVEN_200___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__GM_GAIN_EVEN_200___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__TIA_GAIN_EVEN_200___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__TIA_GAIN_EVEN_200___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__SLM_XLNA_EVEN_200___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__SLM_XLNA_EVEN_200___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__BQ_GAIN_EVEN_200___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200__BQ_GAIN_EVEN_200___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_200___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201 (0x005E5324) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__XLNA_GAIN_ODD_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__LNA_GAIN_ODD_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__GM_GAIN_ODD_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__TIA_GAIN_ODD_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__SLM_XLNA_ODD_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__BQ_GAIN_ODD_201___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__XLNA_GAIN_EVEN_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__LNA_GAIN_EVEN_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__GM_GAIN_EVEN_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__TIA_GAIN_EVEN_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__SLM_XLNA_EVEN_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__BQ_GAIN_EVEN_201___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__XLNA_GAIN_ODD_201___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__XLNA_GAIN_ODD_201___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__LNA_GAIN_ODD_201___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__LNA_GAIN_ODD_201___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__GM_GAIN_ODD_201___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__GM_GAIN_ODD_201___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__TIA_GAIN_ODD_201___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__TIA_GAIN_ODD_201___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__SLM_XLNA_ODD_201___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__SLM_XLNA_ODD_201___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__BQ_GAIN_ODD_201___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__BQ_GAIN_ODD_201___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__XLNA_GAIN_EVEN_201___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__XLNA_GAIN_EVEN_201___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__LNA_GAIN_EVEN_201___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__LNA_GAIN_EVEN_201___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__GM_GAIN_EVEN_201___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__GM_GAIN_EVEN_201___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__TIA_GAIN_EVEN_201___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__TIA_GAIN_EVEN_201___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__SLM_XLNA_EVEN_201___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__SLM_XLNA_EVEN_201___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__BQ_GAIN_EVEN_201___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201__BQ_GAIN_EVEN_201___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_201___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202 (0x005E5328) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__XLNA_GAIN_ODD_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__LNA_GAIN_ODD_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__GM_GAIN_ODD_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__TIA_GAIN_ODD_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__SLM_XLNA_ODD_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__BQ_GAIN_ODD_202___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__XLNA_GAIN_EVEN_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__LNA_GAIN_EVEN_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__GM_GAIN_EVEN_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__TIA_GAIN_EVEN_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__SLM_XLNA_EVEN_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__BQ_GAIN_EVEN_202___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__XLNA_GAIN_ODD_202___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__XLNA_GAIN_ODD_202___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__LNA_GAIN_ODD_202___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__LNA_GAIN_ODD_202___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__GM_GAIN_ODD_202___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__GM_GAIN_ODD_202___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__TIA_GAIN_ODD_202___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__TIA_GAIN_ODD_202___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__SLM_XLNA_ODD_202___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__SLM_XLNA_ODD_202___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__BQ_GAIN_ODD_202___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__BQ_GAIN_ODD_202___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__XLNA_GAIN_EVEN_202___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__XLNA_GAIN_EVEN_202___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__LNA_GAIN_EVEN_202___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__LNA_GAIN_EVEN_202___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__GM_GAIN_EVEN_202___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__GM_GAIN_EVEN_202___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__TIA_GAIN_EVEN_202___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__TIA_GAIN_EVEN_202___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__SLM_XLNA_EVEN_202___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__SLM_XLNA_EVEN_202___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__BQ_GAIN_EVEN_202___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202__BQ_GAIN_EVEN_202___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_202___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203 (0x005E532C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__XLNA_GAIN_ODD_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__LNA_GAIN_ODD_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__GM_GAIN_ODD_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__TIA_GAIN_ODD_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__SLM_XLNA_ODD_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__BQ_GAIN_ODD_203___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__XLNA_GAIN_EVEN_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__LNA_GAIN_EVEN_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__GM_GAIN_EVEN_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__TIA_GAIN_EVEN_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__SLM_XLNA_EVEN_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__BQ_GAIN_EVEN_203___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__XLNA_GAIN_ODD_203___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__XLNA_GAIN_ODD_203___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__LNA_GAIN_ODD_203___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__LNA_GAIN_ODD_203___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__GM_GAIN_ODD_203___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__GM_GAIN_ODD_203___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__TIA_GAIN_ODD_203___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__TIA_GAIN_ODD_203___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__SLM_XLNA_ODD_203___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__SLM_XLNA_ODD_203___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__BQ_GAIN_ODD_203___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__BQ_GAIN_ODD_203___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__XLNA_GAIN_EVEN_203___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__XLNA_GAIN_EVEN_203___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__LNA_GAIN_EVEN_203___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__LNA_GAIN_EVEN_203___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__GM_GAIN_EVEN_203___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__GM_GAIN_EVEN_203___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__TIA_GAIN_EVEN_203___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__TIA_GAIN_EVEN_203___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__SLM_XLNA_EVEN_203___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__SLM_XLNA_EVEN_203___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__BQ_GAIN_EVEN_203___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203__BQ_GAIN_EVEN_203___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_203___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204 (0x005E5330) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__XLNA_GAIN_ODD_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__LNA_GAIN_ODD_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__GM_GAIN_ODD_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__TIA_GAIN_ODD_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__SLM_XLNA_ODD_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__BQ_GAIN_ODD_204___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__XLNA_GAIN_EVEN_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__LNA_GAIN_EVEN_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__GM_GAIN_EVEN_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__TIA_GAIN_EVEN_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__SLM_XLNA_EVEN_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__BQ_GAIN_EVEN_204___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__XLNA_GAIN_ODD_204___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__XLNA_GAIN_ODD_204___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__LNA_GAIN_ODD_204___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__LNA_GAIN_ODD_204___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__GM_GAIN_ODD_204___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__GM_GAIN_ODD_204___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__TIA_GAIN_ODD_204___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__TIA_GAIN_ODD_204___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__SLM_XLNA_ODD_204___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__SLM_XLNA_ODD_204___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__BQ_GAIN_ODD_204___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__BQ_GAIN_ODD_204___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__XLNA_GAIN_EVEN_204___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__XLNA_GAIN_EVEN_204___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__LNA_GAIN_EVEN_204___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__LNA_GAIN_EVEN_204___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__GM_GAIN_EVEN_204___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__GM_GAIN_EVEN_204___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__TIA_GAIN_EVEN_204___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__TIA_GAIN_EVEN_204___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__SLM_XLNA_EVEN_204___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__SLM_XLNA_EVEN_204___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__BQ_GAIN_EVEN_204___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204__BQ_GAIN_EVEN_204___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_204___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205 (0x005E5334) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__XLNA_GAIN_ODD_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__LNA_GAIN_ODD_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__GM_GAIN_ODD_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__TIA_GAIN_ODD_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__SLM_XLNA_ODD_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__BQ_GAIN_ODD_205___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__XLNA_GAIN_EVEN_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__LNA_GAIN_EVEN_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__GM_GAIN_EVEN_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__TIA_GAIN_EVEN_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__SLM_XLNA_EVEN_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__BQ_GAIN_EVEN_205___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__XLNA_GAIN_ODD_205___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__XLNA_GAIN_ODD_205___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__LNA_GAIN_ODD_205___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__LNA_GAIN_ODD_205___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__GM_GAIN_ODD_205___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__GM_GAIN_ODD_205___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__TIA_GAIN_ODD_205___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__TIA_GAIN_ODD_205___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__SLM_XLNA_ODD_205___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__SLM_XLNA_ODD_205___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__BQ_GAIN_ODD_205___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__BQ_GAIN_ODD_205___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__XLNA_GAIN_EVEN_205___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__XLNA_GAIN_EVEN_205___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__LNA_GAIN_EVEN_205___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__LNA_GAIN_EVEN_205___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__GM_GAIN_EVEN_205___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__GM_GAIN_EVEN_205___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__TIA_GAIN_EVEN_205___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__TIA_GAIN_EVEN_205___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__SLM_XLNA_EVEN_205___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__SLM_XLNA_EVEN_205___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__BQ_GAIN_EVEN_205___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205__BQ_GAIN_EVEN_205___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_205___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206 (0x005E5338) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__XLNA_GAIN_ODD_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__LNA_GAIN_ODD_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__GM_GAIN_ODD_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__TIA_GAIN_ODD_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__SLM_XLNA_ODD_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__BQ_GAIN_ODD_206___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__XLNA_GAIN_EVEN_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__LNA_GAIN_EVEN_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__GM_GAIN_EVEN_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__TIA_GAIN_EVEN_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__SLM_XLNA_EVEN_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__BQ_GAIN_EVEN_206___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__XLNA_GAIN_ODD_206___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__XLNA_GAIN_ODD_206___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__LNA_GAIN_ODD_206___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__LNA_GAIN_ODD_206___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__GM_GAIN_ODD_206___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__GM_GAIN_ODD_206___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__TIA_GAIN_ODD_206___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__TIA_GAIN_ODD_206___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__SLM_XLNA_ODD_206___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__SLM_XLNA_ODD_206___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__BQ_GAIN_ODD_206___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__BQ_GAIN_ODD_206___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__XLNA_GAIN_EVEN_206___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__XLNA_GAIN_EVEN_206___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__LNA_GAIN_EVEN_206___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__LNA_GAIN_EVEN_206___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__GM_GAIN_EVEN_206___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__GM_GAIN_EVEN_206___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__TIA_GAIN_EVEN_206___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__TIA_GAIN_EVEN_206___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__SLM_XLNA_EVEN_206___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__SLM_XLNA_EVEN_206___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__BQ_GAIN_EVEN_206___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206__BQ_GAIN_EVEN_206___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_206___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207 (0x005E533C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__XLNA_GAIN_ODD_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__LNA_GAIN_ODD_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__GM_GAIN_ODD_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__TIA_GAIN_ODD_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__SLM_XLNA_ODD_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__BQ_GAIN_ODD_207___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__XLNA_GAIN_EVEN_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__LNA_GAIN_EVEN_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__GM_GAIN_EVEN_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__TIA_GAIN_EVEN_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__SLM_XLNA_EVEN_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__BQ_GAIN_EVEN_207___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__XLNA_GAIN_ODD_207___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__XLNA_GAIN_ODD_207___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__LNA_GAIN_ODD_207___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__LNA_GAIN_ODD_207___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__GM_GAIN_ODD_207___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__GM_GAIN_ODD_207___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__TIA_GAIN_ODD_207___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__TIA_GAIN_ODD_207___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__SLM_XLNA_ODD_207___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__SLM_XLNA_ODD_207___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__BQ_GAIN_ODD_207___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__BQ_GAIN_ODD_207___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__XLNA_GAIN_EVEN_207___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__XLNA_GAIN_EVEN_207___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__LNA_GAIN_EVEN_207___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__LNA_GAIN_EVEN_207___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__GM_GAIN_EVEN_207___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__GM_GAIN_EVEN_207___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__TIA_GAIN_EVEN_207___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__TIA_GAIN_EVEN_207___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__SLM_XLNA_EVEN_207___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__SLM_XLNA_EVEN_207___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__BQ_GAIN_EVEN_207___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207__BQ_GAIN_EVEN_207___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_207___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208 (0x005E5340) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__XLNA_GAIN_ODD_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__LNA_GAIN_ODD_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__GM_GAIN_ODD_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__TIA_GAIN_ODD_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__SLM_XLNA_ODD_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__BQ_GAIN_ODD_208___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__XLNA_GAIN_EVEN_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__LNA_GAIN_EVEN_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__GM_GAIN_EVEN_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__TIA_GAIN_EVEN_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__SLM_XLNA_EVEN_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__BQ_GAIN_EVEN_208___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__XLNA_GAIN_ODD_208___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__XLNA_GAIN_ODD_208___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__LNA_GAIN_ODD_208___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__LNA_GAIN_ODD_208___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__GM_GAIN_ODD_208___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__GM_GAIN_ODD_208___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__TIA_GAIN_ODD_208___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__TIA_GAIN_ODD_208___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__SLM_XLNA_ODD_208___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__SLM_XLNA_ODD_208___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__BQ_GAIN_ODD_208___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__BQ_GAIN_ODD_208___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__XLNA_GAIN_EVEN_208___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__XLNA_GAIN_EVEN_208___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__LNA_GAIN_EVEN_208___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__LNA_GAIN_EVEN_208___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__GM_GAIN_EVEN_208___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__GM_GAIN_EVEN_208___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__TIA_GAIN_EVEN_208___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__TIA_GAIN_EVEN_208___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__SLM_XLNA_EVEN_208___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__SLM_XLNA_EVEN_208___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__BQ_GAIN_EVEN_208___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208__BQ_GAIN_EVEN_208___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_208___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209 (0x005E5344) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__XLNA_GAIN_ODD_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__LNA_GAIN_ODD_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__GM_GAIN_ODD_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__TIA_GAIN_ODD_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__SLM_XLNA_ODD_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__BQ_GAIN_ODD_209___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__XLNA_GAIN_EVEN_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__LNA_GAIN_EVEN_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__GM_GAIN_EVEN_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__TIA_GAIN_EVEN_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__SLM_XLNA_EVEN_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__BQ_GAIN_EVEN_209___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__XLNA_GAIN_ODD_209___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__XLNA_GAIN_ODD_209___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__LNA_GAIN_ODD_209___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__LNA_GAIN_ODD_209___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__GM_GAIN_ODD_209___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__GM_GAIN_ODD_209___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__TIA_GAIN_ODD_209___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__TIA_GAIN_ODD_209___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__SLM_XLNA_ODD_209___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__SLM_XLNA_ODD_209___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__BQ_GAIN_ODD_209___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__BQ_GAIN_ODD_209___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__XLNA_GAIN_EVEN_209___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__XLNA_GAIN_EVEN_209___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__LNA_GAIN_EVEN_209___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__LNA_GAIN_EVEN_209___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__GM_GAIN_EVEN_209___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__GM_GAIN_EVEN_209___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__TIA_GAIN_EVEN_209___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__TIA_GAIN_EVEN_209___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__SLM_XLNA_EVEN_209___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__SLM_XLNA_EVEN_209___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__BQ_GAIN_EVEN_209___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209__BQ_GAIN_EVEN_209___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_209___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210 (0x005E5348) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__XLNA_GAIN_ODD_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__LNA_GAIN_ODD_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__GM_GAIN_ODD_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__TIA_GAIN_ODD_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__SLM_XLNA_ODD_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__BQ_GAIN_ODD_210___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__XLNA_GAIN_EVEN_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__LNA_GAIN_EVEN_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__GM_GAIN_EVEN_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__TIA_GAIN_EVEN_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__SLM_XLNA_EVEN_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__BQ_GAIN_EVEN_210___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__XLNA_GAIN_ODD_210___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__XLNA_GAIN_ODD_210___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__LNA_GAIN_ODD_210___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__LNA_GAIN_ODD_210___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__GM_GAIN_ODD_210___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__GM_GAIN_ODD_210___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__TIA_GAIN_ODD_210___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__TIA_GAIN_ODD_210___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__SLM_XLNA_ODD_210___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__SLM_XLNA_ODD_210___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__BQ_GAIN_ODD_210___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__BQ_GAIN_ODD_210___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__XLNA_GAIN_EVEN_210___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__XLNA_GAIN_EVEN_210___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__LNA_GAIN_EVEN_210___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__LNA_GAIN_EVEN_210___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__GM_GAIN_EVEN_210___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__GM_GAIN_EVEN_210___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__TIA_GAIN_EVEN_210___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__TIA_GAIN_EVEN_210___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__SLM_XLNA_EVEN_210___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__SLM_XLNA_EVEN_210___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__BQ_GAIN_EVEN_210___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210__BQ_GAIN_EVEN_210___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_210___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211 (0x005E534C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__XLNA_GAIN_ODD_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__LNA_GAIN_ODD_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__GM_GAIN_ODD_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__TIA_GAIN_ODD_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__SLM_XLNA_ODD_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__BQ_GAIN_ODD_211___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__XLNA_GAIN_EVEN_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__LNA_GAIN_EVEN_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__GM_GAIN_EVEN_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__TIA_GAIN_EVEN_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__SLM_XLNA_EVEN_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__BQ_GAIN_EVEN_211___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__XLNA_GAIN_ODD_211___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__XLNA_GAIN_ODD_211___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__LNA_GAIN_ODD_211___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__LNA_GAIN_ODD_211___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__GM_GAIN_ODD_211___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__GM_GAIN_ODD_211___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__TIA_GAIN_ODD_211___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__TIA_GAIN_ODD_211___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__SLM_XLNA_ODD_211___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__SLM_XLNA_ODD_211___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__BQ_GAIN_ODD_211___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__BQ_GAIN_ODD_211___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__XLNA_GAIN_EVEN_211___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__XLNA_GAIN_EVEN_211___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__LNA_GAIN_EVEN_211___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__LNA_GAIN_EVEN_211___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__GM_GAIN_EVEN_211___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__GM_GAIN_EVEN_211___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__TIA_GAIN_EVEN_211___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__TIA_GAIN_EVEN_211___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__SLM_XLNA_EVEN_211___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__SLM_XLNA_EVEN_211___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__BQ_GAIN_EVEN_211___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211__BQ_GAIN_EVEN_211___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_211___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212 (0x005E5350) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__XLNA_GAIN_ODD_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__LNA_GAIN_ODD_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__GM_GAIN_ODD_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__TIA_GAIN_ODD_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__SLM_XLNA_ODD_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__BQ_GAIN_ODD_212___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__XLNA_GAIN_EVEN_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__LNA_GAIN_EVEN_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__GM_GAIN_EVEN_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__TIA_GAIN_EVEN_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__SLM_XLNA_EVEN_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__BQ_GAIN_EVEN_212___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__XLNA_GAIN_ODD_212___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__XLNA_GAIN_ODD_212___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__LNA_GAIN_ODD_212___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__LNA_GAIN_ODD_212___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__GM_GAIN_ODD_212___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__GM_GAIN_ODD_212___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__TIA_GAIN_ODD_212___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__TIA_GAIN_ODD_212___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__SLM_XLNA_ODD_212___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__SLM_XLNA_ODD_212___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__BQ_GAIN_ODD_212___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__BQ_GAIN_ODD_212___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__XLNA_GAIN_EVEN_212___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__XLNA_GAIN_EVEN_212___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__LNA_GAIN_EVEN_212___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__LNA_GAIN_EVEN_212___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__GM_GAIN_EVEN_212___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__GM_GAIN_EVEN_212___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__TIA_GAIN_EVEN_212___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__TIA_GAIN_EVEN_212___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__SLM_XLNA_EVEN_212___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__SLM_XLNA_EVEN_212___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__BQ_GAIN_EVEN_212___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212__BQ_GAIN_EVEN_212___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_212___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213 (0x005E5354) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__XLNA_GAIN_ODD_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__LNA_GAIN_ODD_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__GM_GAIN_ODD_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__TIA_GAIN_ODD_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__SLM_XLNA_ODD_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__BQ_GAIN_ODD_213___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__XLNA_GAIN_EVEN_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__LNA_GAIN_EVEN_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__GM_GAIN_EVEN_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__TIA_GAIN_EVEN_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__SLM_XLNA_EVEN_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__BQ_GAIN_EVEN_213___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__XLNA_GAIN_ODD_213___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__XLNA_GAIN_ODD_213___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__LNA_GAIN_ODD_213___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__LNA_GAIN_ODD_213___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__GM_GAIN_ODD_213___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__GM_GAIN_ODD_213___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__TIA_GAIN_ODD_213___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__TIA_GAIN_ODD_213___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__SLM_XLNA_ODD_213___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__SLM_XLNA_ODD_213___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__BQ_GAIN_ODD_213___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__BQ_GAIN_ODD_213___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__XLNA_GAIN_EVEN_213___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__XLNA_GAIN_EVEN_213___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__LNA_GAIN_EVEN_213___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__LNA_GAIN_EVEN_213___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__GM_GAIN_EVEN_213___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__GM_GAIN_EVEN_213___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__TIA_GAIN_EVEN_213___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__TIA_GAIN_EVEN_213___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__SLM_XLNA_EVEN_213___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__SLM_XLNA_EVEN_213___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__BQ_GAIN_EVEN_213___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213__BQ_GAIN_EVEN_213___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_213___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214 (0x005E5358) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__XLNA_GAIN_ODD_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__LNA_GAIN_ODD_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__GM_GAIN_ODD_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__TIA_GAIN_ODD_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__SLM_XLNA_ODD_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__BQ_GAIN_ODD_214___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__XLNA_GAIN_EVEN_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__LNA_GAIN_EVEN_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__GM_GAIN_EVEN_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__TIA_GAIN_EVEN_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__SLM_XLNA_EVEN_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__BQ_GAIN_EVEN_214___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__XLNA_GAIN_ODD_214___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__XLNA_GAIN_ODD_214___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__LNA_GAIN_ODD_214___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__LNA_GAIN_ODD_214___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__GM_GAIN_ODD_214___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__GM_GAIN_ODD_214___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__TIA_GAIN_ODD_214___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__TIA_GAIN_ODD_214___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__SLM_XLNA_ODD_214___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__SLM_XLNA_ODD_214___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__BQ_GAIN_ODD_214___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__BQ_GAIN_ODD_214___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__XLNA_GAIN_EVEN_214___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__XLNA_GAIN_EVEN_214___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__LNA_GAIN_EVEN_214___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__LNA_GAIN_EVEN_214___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__GM_GAIN_EVEN_214___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__GM_GAIN_EVEN_214___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__TIA_GAIN_EVEN_214___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__TIA_GAIN_EVEN_214___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__SLM_XLNA_EVEN_214___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__SLM_XLNA_EVEN_214___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__BQ_GAIN_EVEN_214___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214__BQ_GAIN_EVEN_214___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_214___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215 (0x005E535C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__XLNA_GAIN_ODD_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__LNA_GAIN_ODD_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__GM_GAIN_ODD_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__TIA_GAIN_ODD_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__SLM_XLNA_ODD_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__BQ_GAIN_ODD_215___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__XLNA_GAIN_EVEN_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__LNA_GAIN_EVEN_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__GM_GAIN_EVEN_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__TIA_GAIN_EVEN_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__SLM_XLNA_EVEN_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__BQ_GAIN_EVEN_215___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__XLNA_GAIN_ODD_215___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__XLNA_GAIN_ODD_215___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__LNA_GAIN_ODD_215___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__LNA_GAIN_ODD_215___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__GM_GAIN_ODD_215___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__GM_GAIN_ODD_215___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__TIA_GAIN_ODD_215___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__TIA_GAIN_ODD_215___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__SLM_XLNA_ODD_215___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__SLM_XLNA_ODD_215___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__BQ_GAIN_ODD_215___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__BQ_GAIN_ODD_215___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__XLNA_GAIN_EVEN_215___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__XLNA_GAIN_EVEN_215___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__LNA_GAIN_EVEN_215___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__LNA_GAIN_EVEN_215___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__GM_GAIN_EVEN_215___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__GM_GAIN_EVEN_215___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__TIA_GAIN_EVEN_215___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__TIA_GAIN_EVEN_215___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__SLM_XLNA_EVEN_215___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__SLM_XLNA_EVEN_215___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__BQ_GAIN_EVEN_215___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215__BQ_GAIN_EVEN_215___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_215___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216 (0x005E5360) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__XLNA_GAIN_ODD_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__LNA_GAIN_ODD_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__GM_GAIN_ODD_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__TIA_GAIN_ODD_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__SLM_XLNA_ODD_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__BQ_GAIN_ODD_216___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__XLNA_GAIN_EVEN_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__LNA_GAIN_EVEN_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__GM_GAIN_EVEN_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__TIA_GAIN_EVEN_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__SLM_XLNA_EVEN_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__BQ_GAIN_EVEN_216___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__XLNA_GAIN_ODD_216___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__XLNA_GAIN_ODD_216___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__LNA_GAIN_ODD_216___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__LNA_GAIN_ODD_216___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__GM_GAIN_ODD_216___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__GM_GAIN_ODD_216___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__TIA_GAIN_ODD_216___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__TIA_GAIN_ODD_216___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__SLM_XLNA_ODD_216___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__SLM_XLNA_ODD_216___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__BQ_GAIN_ODD_216___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__BQ_GAIN_ODD_216___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__XLNA_GAIN_EVEN_216___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__XLNA_GAIN_EVEN_216___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__LNA_GAIN_EVEN_216___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__LNA_GAIN_EVEN_216___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__GM_GAIN_EVEN_216___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__GM_GAIN_EVEN_216___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__TIA_GAIN_EVEN_216___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__TIA_GAIN_EVEN_216___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__SLM_XLNA_EVEN_216___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__SLM_XLNA_EVEN_216___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__BQ_GAIN_EVEN_216___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216__BQ_GAIN_EVEN_216___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_216___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217 (0x005E5364) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__XLNA_GAIN_ODD_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__LNA_GAIN_ODD_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__GM_GAIN_ODD_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__TIA_GAIN_ODD_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__SLM_XLNA_ODD_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__BQ_GAIN_ODD_217___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__XLNA_GAIN_EVEN_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__LNA_GAIN_EVEN_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__GM_GAIN_EVEN_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__TIA_GAIN_EVEN_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__SLM_XLNA_EVEN_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__BQ_GAIN_EVEN_217___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__XLNA_GAIN_ODD_217___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__XLNA_GAIN_ODD_217___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__LNA_GAIN_ODD_217___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__LNA_GAIN_ODD_217___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__GM_GAIN_ODD_217___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__GM_GAIN_ODD_217___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__TIA_GAIN_ODD_217___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__TIA_GAIN_ODD_217___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__SLM_XLNA_ODD_217___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__SLM_XLNA_ODD_217___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__BQ_GAIN_ODD_217___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__BQ_GAIN_ODD_217___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__XLNA_GAIN_EVEN_217___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__XLNA_GAIN_EVEN_217___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__LNA_GAIN_EVEN_217___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__LNA_GAIN_EVEN_217___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__GM_GAIN_EVEN_217___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__GM_GAIN_EVEN_217___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__TIA_GAIN_EVEN_217___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__TIA_GAIN_EVEN_217___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__SLM_XLNA_EVEN_217___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__SLM_XLNA_EVEN_217___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__BQ_GAIN_EVEN_217___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217__BQ_GAIN_EVEN_217___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_217___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218 (0x005E5368) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__XLNA_GAIN_ODD_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__LNA_GAIN_ODD_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__GM_GAIN_ODD_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__TIA_GAIN_ODD_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__SLM_XLNA_ODD_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__BQ_GAIN_ODD_218___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__XLNA_GAIN_EVEN_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__LNA_GAIN_EVEN_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__GM_GAIN_EVEN_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__TIA_GAIN_EVEN_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__SLM_XLNA_EVEN_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__BQ_GAIN_EVEN_218___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__XLNA_GAIN_ODD_218___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__XLNA_GAIN_ODD_218___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__LNA_GAIN_ODD_218___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__LNA_GAIN_ODD_218___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__GM_GAIN_ODD_218___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__GM_GAIN_ODD_218___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__TIA_GAIN_ODD_218___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__TIA_GAIN_ODD_218___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__SLM_XLNA_ODD_218___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__SLM_XLNA_ODD_218___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__BQ_GAIN_ODD_218___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__BQ_GAIN_ODD_218___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__XLNA_GAIN_EVEN_218___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__XLNA_GAIN_EVEN_218___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__LNA_GAIN_EVEN_218___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__LNA_GAIN_EVEN_218___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__GM_GAIN_EVEN_218___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__GM_GAIN_EVEN_218___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__TIA_GAIN_EVEN_218___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__TIA_GAIN_EVEN_218___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__SLM_XLNA_EVEN_218___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__SLM_XLNA_EVEN_218___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__BQ_GAIN_EVEN_218___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218__BQ_GAIN_EVEN_218___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_218___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219 (0x005E536C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__XLNA_GAIN_ODD_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__LNA_GAIN_ODD_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__GM_GAIN_ODD_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__TIA_GAIN_ODD_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__SLM_XLNA_ODD_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__BQ_GAIN_ODD_219___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__XLNA_GAIN_EVEN_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__LNA_GAIN_EVEN_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__GM_GAIN_EVEN_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__TIA_GAIN_EVEN_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__SLM_XLNA_EVEN_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__BQ_GAIN_EVEN_219___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__XLNA_GAIN_ODD_219___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__XLNA_GAIN_ODD_219___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__LNA_GAIN_ODD_219___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__LNA_GAIN_ODD_219___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__GM_GAIN_ODD_219___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__GM_GAIN_ODD_219___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__TIA_GAIN_ODD_219___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__TIA_GAIN_ODD_219___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__SLM_XLNA_ODD_219___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__SLM_XLNA_ODD_219___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__BQ_GAIN_ODD_219___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__BQ_GAIN_ODD_219___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__XLNA_GAIN_EVEN_219___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__XLNA_GAIN_EVEN_219___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__LNA_GAIN_EVEN_219___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__LNA_GAIN_EVEN_219___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__GM_GAIN_EVEN_219___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__GM_GAIN_EVEN_219___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__TIA_GAIN_EVEN_219___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__TIA_GAIN_EVEN_219___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__SLM_XLNA_EVEN_219___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__SLM_XLNA_EVEN_219___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__BQ_GAIN_EVEN_219___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219__BQ_GAIN_EVEN_219___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_219___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220 (0x005E5370) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__XLNA_GAIN_ODD_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__LNA_GAIN_ODD_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__GM_GAIN_ODD_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__TIA_GAIN_ODD_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__SLM_XLNA_ODD_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__BQ_GAIN_ODD_220___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__XLNA_GAIN_EVEN_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__LNA_GAIN_EVEN_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__GM_GAIN_EVEN_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__TIA_GAIN_EVEN_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__SLM_XLNA_EVEN_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__BQ_GAIN_EVEN_220___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__XLNA_GAIN_ODD_220___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__XLNA_GAIN_ODD_220___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__LNA_GAIN_ODD_220___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__LNA_GAIN_ODD_220___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__GM_GAIN_ODD_220___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__GM_GAIN_ODD_220___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__TIA_GAIN_ODD_220___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__TIA_GAIN_ODD_220___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__SLM_XLNA_ODD_220___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__SLM_XLNA_ODD_220___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__BQ_GAIN_ODD_220___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__BQ_GAIN_ODD_220___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__XLNA_GAIN_EVEN_220___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__XLNA_GAIN_EVEN_220___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__LNA_GAIN_EVEN_220___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__LNA_GAIN_EVEN_220___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__GM_GAIN_EVEN_220___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__GM_GAIN_EVEN_220___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__TIA_GAIN_EVEN_220___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__TIA_GAIN_EVEN_220___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__SLM_XLNA_EVEN_220___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__SLM_XLNA_EVEN_220___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__BQ_GAIN_EVEN_220___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220__BQ_GAIN_EVEN_220___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_220___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221 (0x005E5374) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__XLNA_GAIN_ODD_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__LNA_GAIN_ODD_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__GM_GAIN_ODD_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__TIA_GAIN_ODD_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__SLM_XLNA_ODD_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__BQ_GAIN_ODD_221___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__XLNA_GAIN_EVEN_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__LNA_GAIN_EVEN_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__GM_GAIN_EVEN_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__TIA_GAIN_EVEN_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__SLM_XLNA_EVEN_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__BQ_GAIN_EVEN_221___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__XLNA_GAIN_ODD_221___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__XLNA_GAIN_ODD_221___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__LNA_GAIN_ODD_221___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__LNA_GAIN_ODD_221___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__GM_GAIN_ODD_221___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__GM_GAIN_ODD_221___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__TIA_GAIN_ODD_221___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__TIA_GAIN_ODD_221___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__SLM_XLNA_ODD_221___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__SLM_XLNA_ODD_221___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__BQ_GAIN_ODD_221___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__BQ_GAIN_ODD_221___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__XLNA_GAIN_EVEN_221___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__XLNA_GAIN_EVEN_221___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__LNA_GAIN_EVEN_221___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__LNA_GAIN_EVEN_221___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__GM_GAIN_EVEN_221___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__GM_GAIN_EVEN_221___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__TIA_GAIN_EVEN_221___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__TIA_GAIN_EVEN_221___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__SLM_XLNA_EVEN_221___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__SLM_XLNA_EVEN_221___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__BQ_GAIN_EVEN_221___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221__BQ_GAIN_EVEN_221___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_221___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222 (0x005E5378) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__XLNA_GAIN_ODD_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__LNA_GAIN_ODD_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__GM_GAIN_ODD_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__TIA_GAIN_ODD_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__SLM_XLNA_ODD_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__BQ_GAIN_ODD_222___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__XLNA_GAIN_EVEN_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__LNA_GAIN_EVEN_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__GM_GAIN_EVEN_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__TIA_GAIN_EVEN_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__SLM_XLNA_EVEN_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__BQ_GAIN_EVEN_222___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__XLNA_GAIN_ODD_222___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__XLNA_GAIN_ODD_222___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__LNA_GAIN_ODD_222___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__LNA_GAIN_ODD_222___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__GM_GAIN_ODD_222___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__GM_GAIN_ODD_222___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__TIA_GAIN_ODD_222___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__TIA_GAIN_ODD_222___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__SLM_XLNA_ODD_222___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__SLM_XLNA_ODD_222___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__BQ_GAIN_ODD_222___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__BQ_GAIN_ODD_222___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__XLNA_GAIN_EVEN_222___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__XLNA_GAIN_EVEN_222___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__LNA_GAIN_EVEN_222___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__LNA_GAIN_EVEN_222___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__GM_GAIN_EVEN_222___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__GM_GAIN_EVEN_222___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__TIA_GAIN_EVEN_222___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__TIA_GAIN_EVEN_222___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__SLM_XLNA_EVEN_222___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__SLM_XLNA_EVEN_222___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__BQ_GAIN_EVEN_222___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222__BQ_GAIN_EVEN_222___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_222___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223 (0x005E537C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__XLNA_GAIN_ODD_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__LNA_GAIN_ODD_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__GM_GAIN_ODD_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__TIA_GAIN_ODD_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__SLM_XLNA_ODD_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__BQ_GAIN_ODD_223___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__XLNA_GAIN_EVEN_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__LNA_GAIN_EVEN_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__GM_GAIN_EVEN_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__TIA_GAIN_EVEN_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__SLM_XLNA_EVEN_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__BQ_GAIN_EVEN_223___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__XLNA_GAIN_ODD_223___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__XLNA_GAIN_ODD_223___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__LNA_GAIN_ODD_223___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__LNA_GAIN_ODD_223___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__GM_GAIN_ODD_223___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__GM_GAIN_ODD_223___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__TIA_GAIN_ODD_223___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__TIA_GAIN_ODD_223___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__SLM_XLNA_ODD_223___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__SLM_XLNA_ODD_223___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__BQ_GAIN_ODD_223___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__BQ_GAIN_ODD_223___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__XLNA_GAIN_EVEN_223___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__XLNA_GAIN_EVEN_223___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__LNA_GAIN_EVEN_223___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__LNA_GAIN_EVEN_223___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__GM_GAIN_EVEN_223___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__GM_GAIN_EVEN_223___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__TIA_GAIN_EVEN_223___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__TIA_GAIN_EVEN_223___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__SLM_XLNA_EVEN_223___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__SLM_XLNA_EVEN_223___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__BQ_GAIN_EVEN_223___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223__BQ_GAIN_EVEN_223___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_223___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224 (0x005E5380) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__XLNA_GAIN_ODD_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__LNA_GAIN_ODD_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__GM_GAIN_ODD_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__TIA_GAIN_ODD_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__SLM_XLNA_ODD_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__BQ_GAIN_ODD_224___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__XLNA_GAIN_EVEN_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__LNA_GAIN_EVEN_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__GM_GAIN_EVEN_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__TIA_GAIN_EVEN_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__SLM_XLNA_EVEN_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__BQ_GAIN_EVEN_224___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__XLNA_GAIN_ODD_224___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__XLNA_GAIN_ODD_224___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__LNA_GAIN_ODD_224___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__LNA_GAIN_ODD_224___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__GM_GAIN_ODD_224___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__GM_GAIN_ODD_224___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__TIA_GAIN_ODD_224___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__TIA_GAIN_ODD_224___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__SLM_XLNA_ODD_224___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__SLM_XLNA_ODD_224___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__BQ_GAIN_ODD_224___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__BQ_GAIN_ODD_224___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__XLNA_GAIN_EVEN_224___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__XLNA_GAIN_EVEN_224___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__LNA_GAIN_EVEN_224___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__LNA_GAIN_EVEN_224___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__GM_GAIN_EVEN_224___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__GM_GAIN_EVEN_224___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__TIA_GAIN_EVEN_224___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__TIA_GAIN_EVEN_224___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__SLM_XLNA_EVEN_224___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__SLM_XLNA_EVEN_224___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__BQ_GAIN_EVEN_224___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224__BQ_GAIN_EVEN_224___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_224___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225 (0x005E5384) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__XLNA_GAIN_ODD_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__LNA_GAIN_ODD_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__GM_GAIN_ODD_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__TIA_GAIN_ODD_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__SLM_XLNA_ODD_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__BQ_GAIN_ODD_225___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__XLNA_GAIN_EVEN_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__LNA_GAIN_EVEN_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__GM_GAIN_EVEN_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__TIA_GAIN_EVEN_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__SLM_XLNA_EVEN_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__BQ_GAIN_EVEN_225___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__XLNA_GAIN_ODD_225___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__XLNA_GAIN_ODD_225___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__LNA_GAIN_ODD_225___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__LNA_GAIN_ODD_225___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__GM_GAIN_ODD_225___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__GM_GAIN_ODD_225___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__TIA_GAIN_ODD_225___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__TIA_GAIN_ODD_225___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__SLM_XLNA_ODD_225___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__SLM_XLNA_ODD_225___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__BQ_GAIN_ODD_225___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__BQ_GAIN_ODD_225___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__XLNA_GAIN_EVEN_225___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__XLNA_GAIN_EVEN_225___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__LNA_GAIN_EVEN_225___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__LNA_GAIN_EVEN_225___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__GM_GAIN_EVEN_225___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__GM_GAIN_EVEN_225___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__TIA_GAIN_EVEN_225___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__TIA_GAIN_EVEN_225___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__SLM_XLNA_EVEN_225___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__SLM_XLNA_EVEN_225___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__BQ_GAIN_EVEN_225___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225__BQ_GAIN_EVEN_225___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_225___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226 (0x005E5388) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__XLNA_GAIN_ODD_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__LNA_GAIN_ODD_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__GM_GAIN_ODD_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__TIA_GAIN_ODD_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__SLM_XLNA_ODD_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__BQ_GAIN_ODD_226___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__XLNA_GAIN_EVEN_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__LNA_GAIN_EVEN_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__GM_GAIN_EVEN_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__TIA_GAIN_EVEN_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__SLM_XLNA_EVEN_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__BQ_GAIN_EVEN_226___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__XLNA_GAIN_ODD_226___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__XLNA_GAIN_ODD_226___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__LNA_GAIN_ODD_226___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__LNA_GAIN_ODD_226___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__GM_GAIN_ODD_226___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__GM_GAIN_ODD_226___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__TIA_GAIN_ODD_226___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__TIA_GAIN_ODD_226___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__SLM_XLNA_ODD_226___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__SLM_XLNA_ODD_226___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__BQ_GAIN_ODD_226___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__BQ_GAIN_ODD_226___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__XLNA_GAIN_EVEN_226___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__XLNA_GAIN_EVEN_226___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__LNA_GAIN_EVEN_226___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__LNA_GAIN_EVEN_226___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__GM_GAIN_EVEN_226___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__GM_GAIN_EVEN_226___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__TIA_GAIN_EVEN_226___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__TIA_GAIN_EVEN_226___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__SLM_XLNA_EVEN_226___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__SLM_XLNA_EVEN_226___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__BQ_GAIN_EVEN_226___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226__BQ_GAIN_EVEN_226___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_226___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227 (0x005E538C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__XLNA_GAIN_ODD_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__LNA_GAIN_ODD_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__GM_GAIN_ODD_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__TIA_GAIN_ODD_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__SLM_XLNA_ODD_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__BQ_GAIN_ODD_227___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__XLNA_GAIN_EVEN_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__LNA_GAIN_EVEN_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__GM_GAIN_EVEN_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__TIA_GAIN_EVEN_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__SLM_XLNA_EVEN_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__BQ_GAIN_EVEN_227___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__XLNA_GAIN_ODD_227___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__XLNA_GAIN_ODD_227___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__LNA_GAIN_ODD_227___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__LNA_GAIN_ODD_227___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__GM_GAIN_ODD_227___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__GM_GAIN_ODD_227___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__TIA_GAIN_ODD_227___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__TIA_GAIN_ODD_227___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__SLM_XLNA_ODD_227___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__SLM_XLNA_ODD_227___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__BQ_GAIN_ODD_227___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__BQ_GAIN_ODD_227___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__XLNA_GAIN_EVEN_227___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__XLNA_GAIN_EVEN_227___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__LNA_GAIN_EVEN_227___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__LNA_GAIN_EVEN_227___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__GM_GAIN_EVEN_227___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__GM_GAIN_EVEN_227___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__TIA_GAIN_EVEN_227___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__TIA_GAIN_EVEN_227___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__SLM_XLNA_EVEN_227___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__SLM_XLNA_EVEN_227___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__BQ_GAIN_EVEN_227___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227__BQ_GAIN_EVEN_227___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_227___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228 (0x005E5390) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__XLNA_GAIN_ODD_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__LNA_GAIN_ODD_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__GM_GAIN_ODD_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__TIA_GAIN_ODD_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__SLM_XLNA_ODD_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__BQ_GAIN_ODD_228___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__XLNA_GAIN_EVEN_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__LNA_GAIN_EVEN_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__GM_GAIN_EVEN_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__TIA_GAIN_EVEN_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__SLM_XLNA_EVEN_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__BQ_GAIN_EVEN_228___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__XLNA_GAIN_ODD_228___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__XLNA_GAIN_ODD_228___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__LNA_GAIN_ODD_228___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__LNA_GAIN_ODD_228___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__GM_GAIN_ODD_228___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__GM_GAIN_ODD_228___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__TIA_GAIN_ODD_228___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__TIA_GAIN_ODD_228___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__SLM_XLNA_ODD_228___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__SLM_XLNA_ODD_228___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__BQ_GAIN_ODD_228___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__BQ_GAIN_ODD_228___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__XLNA_GAIN_EVEN_228___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__XLNA_GAIN_EVEN_228___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__LNA_GAIN_EVEN_228___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__LNA_GAIN_EVEN_228___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__GM_GAIN_EVEN_228___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__GM_GAIN_EVEN_228___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__TIA_GAIN_EVEN_228___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__TIA_GAIN_EVEN_228___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__SLM_XLNA_EVEN_228___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__SLM_XLNA_EVEN_228___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__BQ_GAIN_EVEN_228___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228__BQ_GAIN_EVEN_228___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_228___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229 (0x005E5394) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__XLNA_GAIN_ODD_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__LNA_GAIN_ODD_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__GM_GAIN_ODD_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__TIA_GAIN_ODD_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__SLM_XLNA_ODD_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__BQ_GAIN_ODD_229___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__XLNA_GAIN_EVEN_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__LNA_GAIN_EVEN_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__GM_GAIN_EVEN_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__TIA_GAIN_EVEN_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__SLM_XLNA_EVEN_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__BQ_GAIN_EVEN_229___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__XLNA_GAIN_ODD_229___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__XLNA_GAIN_ODD_229___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__LNA_GAIN_ODD_229___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__LNA_GAIN_ODD_229___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__GM_GAIN_ODD_229___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__GM_GAIN_ODD_229___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__TIA_GAIN_ODD_229___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__TIA_GAIN_ODD_229___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__SLM_XLNA_ODD_229___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__SLM_XLNA_ODD_229___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__BQ_GAIN_ODD_229___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__BQ_GAIN_ODD_229___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__XLNA_GAIN_EVEN_229___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__XLNA_GAIN_EVEN_229___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__LNA_GAIN_EVEN_229___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__LNA_GAIN_EVEN_229___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__GM_GAIN_EVEN_229___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__GM_GAIN_EVEN_229___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__TIA_GAIN_EVEN_229___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__TIA_GAIN_EVEN_229___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__SLM_XLNA_EVEN_229___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__SLM_XLNA_EVEN_229___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__BQ_GAIN_EVEN_229___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229__BQ_GAIN_EVEN_229___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_229___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230 (0x005E5398) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__XLNA_GAIN_ODD_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__LNA_GAIN_ODD_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__GM_GAIN_ODD_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__TIA_GAIN_ODD_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__SLM_XLNA_ODD_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__BQ_GAIN_ODD_230___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__XLNA_GAIN_EVEN_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__LNA_GAIN_EVEN_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__GM_GAIN_EVEN_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__TIA_GAIN_EVEN_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__SLM_XLNA_EVEN_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__BQ_GAIN_EVEN_230___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__XLNA_GAIN_ODD_230___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__XLNA_GAIN_ODD_230___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__LNA_GAIN_ODD_230___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__LNA_GAIN_ODD_230___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__GM_GAIN_ODD_230___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__GM_GAIN_ODD_230___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__TIA_GAIN_ODD_230___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__TIA_GAIN_ODD_230___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__SLM_XLNA_ODD_230___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__SLM_XLNA_ODD_230___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__BQ_GAIN_ODD_230___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__BQ_GAIN_ODD_230___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__XLNA_GAIN_EVEN_230___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__XLNA_GAIN_EVEN_230___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__LNA_GAIN_EVEN_230___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__LNA_GAIN_EVEN_230___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__GM_GAIN_EVEN_230___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__GM_GAIN_EVEN_230___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__TIA_GAIN_EVEN_230___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__TIA_GAIN_EVEN_230___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__SLM_XLNA_EVEN_230___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__SLM_XLNA_EVEN_230___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__BQ_GAIN_EVEN_230___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230__BQ_GAIN_EVEN_230___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_230___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231 (0x005E539C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__XLNA_GAIN_ODD_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__LNA_GAIN_ODD_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__GM_GAIN_ODD_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__TIA_GAIN_ODD_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__SLM_XLNA_ODD_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__BQ_GAIN_ODD_231___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__XLNA_GAIN_EVEN_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__LNA_GAIN_EVEN_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__GM_GAIN_EVEN_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__TIA_GAIN_EVEN_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__SLM_XLNA_EVEN_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__BQ_GAIN_EVEN_231___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__XLNA_GAIN_ODD_231___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__XLNA_GAIN_ODD_231___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__LNA_GAIN_ODD_231___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__LNA_GAIN_ODD_231___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__GM_GAIN_ODD_231___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__GM_GAIN_ODD_231___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__TIA_GAIN_ODD_231___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__TIA_GAIN_ODD_231___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__SLM_XLNA_ODD_231___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__SLM_XLNA_ODD_231___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__BQ_GAIN_ODD_231___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__BQ_GAIN_ODD_231___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__XLNA_GAIN_EVEN_231___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__XLNA_GAIN_EVEN_231___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__LNA_GAIN_EVEN_231___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__LNA_GAIN_EVEN_231___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__GM_GAIN_EVEN_231___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__GM_GAIN_EVEN_231___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__TIA_GAIN_EVEN_231___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__TIA_GAIN_EVEN_231___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__SLM_XLNA_EVEN_231___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__SLM_XLNA_EVEN_231___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__BQ_GAIN_EVEN_231___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231__BQ_GAIN_EVEN_231___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_231___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232 (0x005E53A0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__XLNA_GAIN_ODD_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__LNA_GAIN_ODD_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__GM_GAIN_ODD_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__TIA_GAIN_ODD_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__SLM_XLNA_ODD_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__BQ_GAIN_ODD_232___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__XLNA_GAIN_EVEN_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__LNA_GAIN_EVEN_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__GM_GAIN_EVEN_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__TIA_GAIN_EVEN_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__SLM_XLNA_EVEN_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__BQ_GAIN_EVEN_232___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__XLNA_GAIN_ODD_232___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__XLNA_GAIN_ODD_232___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__LNA_GAIN_ODD_232___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__LNA_GAIN_ODD_232___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__GM_GAIN_ODD_232___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__GM_GAIN_ODD_232___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__TIA_GAIN_ODD_232___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__TIA_GAIN_ODD_232___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__SLM_XLNA_ODD_232___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__SLM_XLNA_ODD_232___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__BQ_GAIN_ODD_232___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__BQ_GAIN_ODD_232___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__XLNA_GAIN_EVEN_232___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__XLNA_GAIN_EVEN_232___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__LNA_GAIN_EVEN_232___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__LNA_GAIN_EVEN_232___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__GM_GAIN_EVEN_232___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__GM_GAIN_EVEN_232___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__TIA_GAIN_EVEN_232___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__TIA_GAIN_EVEN_232___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__SLM_XLNA_EVEN_232___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__SLM_XLNA_EVEN_232___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__BQ_GAIN_EVEN_232___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232__BQ_GAIN_EVEN_232___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_232___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233 (0x005E53A4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__XLNA_GAIN_ODD_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__LNA_GAIN_ODD_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__GM_GAIN_ODD_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__TIA_GAIN_ODD_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__SLM_XLNA_ODD_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__BQ_GAIN_ODD_233___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__XLNA_GAIN_EVEN_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__LNA_GAIN_EVEN_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__GM_GAIN_EVEN_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__TIA_GAIN_EVEN_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__SLM_XLNA_EVEN_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__BQ_GAIN_EVEN_233___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__XLNA_GAIN_ODD_233___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__XLNA_GAIN_ODD_233___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__LNA_GAIN_ODD_233___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__LNA_GAIN_ODD_233___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__GM_GAIN_ODD_233___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__GM_GAIN_ODD_233___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__TIA_GAIN_ODD_233___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__TIA_GAIN_ODD_233___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__SLM_XLNA_ODD_233___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__SLM_XLNA_ODD_233___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__BQ_GAIN_ODD_233___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__BQ_GAIN_ODD_233___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__XLNA_GAIN_EVEN_233___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__XLNA_GAIN_EVEN_233___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__LNA_GAIN_EVEN_233___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__LNA_GAIN_EVEN_233___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__GM_GAIN_EVEN_233___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__GM_GAIN_EVEN_233___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__TIA_GAIN_EVEN_233___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__TIA_GAIN_EVEN_233___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__SLM_XLNA_EVEN_233___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__SLM_XLNA_EVEN_233___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__BQ_GAIN_EVEN_233___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233__BQ_GAIN_EVEN_233___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_233___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234 (0x005E53A8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__XLNA_GAIN_ODD_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__LNA_GAIN_ODD_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__GM_GAIN_ODD_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__TIA_GAIN_ODD_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__SLM_XLNA_ODD_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__BQ_GAIN_ODD_234___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__XLNA_GAIN_EVEN_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__LNA_GAIN_EVEN_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__GM_GAIN_EVEN_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__TIA_GAIN_EVEN_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__SLM_XLNA_EVEN_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__BQ_GAIN_EVEN_234___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__XLNA_GAIN_ODD_234___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__XLNA_GAIN_ODD_234___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__LNA_GAIN_ODD_234___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__LNA_GAIN_ODD_234___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__GM_GAIN_ODD_234___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__GM_GAIN_ODD_234___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__TIA_GAIN_ODD_234___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__TIA_GAIN_ODD_234___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__SLM_XLNA_ODD_234___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__SLM_XLNA_ODD_234___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__BQ_GAIN_ODD_234___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__BQ_GAIN_ODD_234___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__XLNA_GAIN_EVEN_234___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__XLNA_GAIN_EVEN_234___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__LNA_GAIN_EVEN_234___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__LNA_GAIN_EVEN_234___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__GM_GAIN_EVEN_234___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__GM_GAIN_EVEN_234___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__TIA_GAIN_EVEN_234___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__TIA_GAIN_EVEN_234___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__SLM_XLNA_EVEN_234___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__SLM_XLNA_EVEN_234___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__BQ_GAIN_EVEN_234___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234__BQ_GAIN_EVEN_234___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_234___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235 (0x005E53AC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__XLNA_GAIN_ODD_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__LNA_GAIN_ODD_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__GM_GAIN_ODD_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__TIA_GAIN_ODD_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__SLM_XLNA_ODD_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__BQ_GAIN_ODD_235___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__XLNA_GAIN_EVEN_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__LNA_GAIN_EVEN_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__GM_GAIN_EVEN_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__TIA_GAIN_EVEN_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__SLM_XLNA_EVEN_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__BQ_GAIN_EVEN_235___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__XLNA_GAIN_ODD_235___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__XLNA_GAIN_ODD_235___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__LNA_GAIN_ODD_235___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__LNA_GAIN_ODD_235___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__GM_GAIN_ODD_235___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__GM_GAIN_ODD_235___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__TIA_GAIN_ODD_235___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__TIA_GAIN_ODD_235___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__SLM_XLNA_ODD_235___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__SLM_XLNA_ODD_235___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__BQ_GAIN_ODD_235___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__BQ_GAIN_ODD_235___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__XLNA_GAIN_EVEN_235___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__XLNA_GAIN_EVEN_235___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__LNA_GAIN_EVEN_235___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__LNA_GAIN_EVEN_235___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__GM_GAIN_EVEN_235___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__GM_GAIN_EVEN_235___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__TIA_GAIN_EVEN_235___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__TIA_GAIN_EVEN_235___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__SLM_XLNA_EVEN_235___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__SLM_XLNA_EVEN_235___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__BQ_GAIN_EVEN_235___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235__BQ_GAIN_EVEN_235___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_235___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236 (0x005E53B0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__XLNA_GAIN_ODD_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__LNA_GAIN_ODD_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__GM_GAIN_ODD_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__TIA_GAIN_ODD_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__SLM_XLNA_ODD_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__BQ_GAIN_ODD_236___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__XLNA_GAIN_EVEN_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__LNA_GAIN_EVEN_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__GM_GAIN_EVEN_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__TIA_GAIN_EVEN_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__SLM_XLNA_EVEN_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__BQ_GAIN_EVEN_236___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__XLNA_GAIN_ODD_236___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__XLNA_GAIN_ODD_236___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__LNA_GAIN_ODD_236___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__LNA_GAIN_ODD_236___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__GM_GAIN_ODD_236___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__GM_GAIN_ODD_236___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__TIA_GAIN_ODD_236___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__TIA_GAIN_ODD_236___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__SLM_XLNA_ODD_236___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__SLM_XLNA_ODD_236___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__BQ_GAIN_ODD_236___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__BQ_GAIN_ODD_236___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__XLNA_GAIN_EVEN_236___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__XLNA_GAIN_EVEN_236___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__LNA_GAIN_EVEN_236___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__LNA_GAIN_EVEN_236___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__GM_GAIN_EVEN_236___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__GM_GAIN_EVEN_236___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__TIA_GAIN_EVEN_236___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__TIA_GAIN_EVEN_236___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__SLM_XLNA_EVEN_236___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__SLM_XLNA_EVEN_236___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__BQ_GAIN_EVEN_236___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236__BQ_GAIN_EVEN_236___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_236___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237 (0x005E53B4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__XLNA_GAIN_ODD_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__LNA_GAIN_ODD_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__GM_GAIN_ODD_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__TIA_GAIN_ODD_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__SLM_XLNA_ODD_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__BQ_GAIN_ODD_237___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__XLNA_GAIN_EVEN_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__LNA_GAIN_EVEN_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__GM_GAIN_EVEN_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__TIA_GAIN_EVEN_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__SLM_XLNA_EVEN_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__BQ_GAIN_EVEN_237___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__XLNA_GAIN_ODD_237___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__XLNA_GAIN_ODD_237___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__LNA_GAIN_ODD_237___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__LNA_GAIN_ODD_237___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__GM_GAIN_ODD_237___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__GM_GAIN_ODD_237___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__TIA_GAIN_ODD_237___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__TIA_GAIN_ODD_237___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__SLM_XLNA_ODD_237___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__SLM_XLNA_ODD_237___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__BQ_GAIN_ODD_237___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__BQ_GAIN_ODD_237___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__XLNA_GAIN_EVEN_237___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__XLNA_GAIN_EVEN_237___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__LNA_GAIN_EVEN_237___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__LNA_GAIN_EVEN_237___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__GM_GAIN_EVEN_237___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__GM_GAIN_EVEN_237___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__TIA_GAIN_EVEN_237___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__TIA_GAIN_EVEN_237___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__SLM_XLNA_EVEN_237___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__SLM_XLNA_EVEN_237___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__BQ_GAIN_EVEN_237___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237__BQ_GAIN_EVEN_237___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_237___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238 (0x005E53B8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__XLNA_GAIN_ODD_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__LNA_GAIN_ODD_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__GM_GAIN_ODD_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__TIA_GAIN_ODD_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__SLM_XLNA_ODD_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__BQ_GAIN_ODD_238___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__XLNA_GAIN_EVEN_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__LNA_GAIN_EVEN_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__GM_GAIN_EVEN_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__TIA_GAIN_EVEN_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__SLM_XLNA_EVEN_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__BQ_GAIN_EVEN_238___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__XLNA_GAIN_ODD_238___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__XLNA_GAIN_ODD_238___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__LNA_GAIN_ODD_238___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__LNA_GAIN_ODD_238___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__GM_GAIN_ODD_238___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__GM_GAIN_ODD_238___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__TIA_GAIN_ODD_238___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__TIA_GAIN_ODD_238___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__SLM_XLNA_ODD_238___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__SLM_XLNA_ODD_238___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__BQ_GAIN_ODD_238___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__BQ_GAIN_ODD_238___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__XLNA_GAIN_EVEN_238___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__XLNA_GAIN_EVEN_238___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__LNA_GAIN_EVEN_238___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__LNA_GAIN_EVEN_238___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__GM_GAIN_EVEN_238___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__GM_GAIN_EVEN_238___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__TIA_GAIN_EVEN_238___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__TIA_GAIN_EVEN_238___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__SLM_XLNA_EVEN_238___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__SLM_XLNA_EVEN_238___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__BQ_GAIN_EVEN_238___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238__BQ_GAIN_EVEN_238___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_238___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239 (0x005E53BC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__XLNA_GAIN_ODD_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__LNA_GAIN_ODD_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__GM_GAIN_ODD_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__TIA_GAIN_ODD_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__SLM_XLNA_ODD_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__BQ_GAIN_ODD_239___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__XLNA_GAIN_EVEN_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__LNA_GAIN_EVEN_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__GM_GAIN_EVEN_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__TIA_GAIN_EVEN_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__SLM_XLNA_EVEN_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__BQ_GAIN_EVEN_239___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__XLNA_GAIN_ODD_239___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__XLNA_GAIN_ODD_239___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__LNA_GAIN_ODD_239___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__LNA_GAIN_ODD_239___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__GM_GAIN_ODD_239___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__GM_GAIN_ODD_239___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__TIA_GAIN_ODD_239___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__TIA_GAIN_ODD_239___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__SLM_XLNA_ODD_239___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__SLM_XLNA_ODD_239___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__BQ_GAIN_ODD_239___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__BQ_GAIN_ODD_239___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__XLNA_GAIN_EVEN_239___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__XLNA_GAIN_EVEN_239___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__LNA_GAIN_EVEN_239___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__LNA_GAIN_EVEN_239___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__GM_GAIN_EVEN_239___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__GM_GAIN_EVEN_239___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__TIA_GAIN_EVEN_239___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__TIA_GAIN_EVEN_239___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__SLM_XLNA_EVEN_239___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__SLM_XLNA_EVEN_239___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__BQ_GAIN_EVEN_239___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239__BQ_GAIN_EVEN_239___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_239___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240 (0x005E53C0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__XLNA_GAIN_ODD_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__LNA_GAIN_ODD_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__GM_GAIN_ODD_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__TIA_GAIN_ODD_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__SLM_XLNA_ODD_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__BQ_GAIN_ODD_240___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__XLNA_GAIN_EVEN_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__LNA_GAIN_EVEN_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__GM_GAIN_EVEN_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__TIA_GAIN_EVEN_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__SLM_XLNA_EVEN_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__BQ_GAIN_EVEN_240___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__XLNA_GAIN_ODD_240___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__XLNA_GAIN_ODD_240___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__LNA_GAIN_ODD_240___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__LNA_GAIN_ODD_240___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__GM_GAIN_ODD_240___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__GM_GAIN_ODD_240___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__TIA_GAIN_ODD_240___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__TIA_GAIN_ODD_240___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__SLM_XLNA_ODD_240___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__SLM_XLNA_ODD_240___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__BQ_GAIN_ODD_240___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__BQ_GAIN_ODD_240___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__XLNA_GAIN_EVEN_240___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__XLNA_GAIN_EVEN_240___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__LNA_GAIN_EVEN_240___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__LNA_GAIN_EVEN_240___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__GM_GAIN_EVEN_240___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__GM_GAIN_EVEN_240___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__TIA_GAIN_EVEN_240___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__TIA_GAIN_EVEN_240___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__SLM_XLNA_EVEN_240___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__SLM_XLNA_EVEN_240___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__BQ_GAIN_EVEN_240___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240__BQ_GAIN_EVEN_240___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_240___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241 (0x005E53C4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__XLNA_GAIN_ODD_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__LNA_GAIN_ODD_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__GM_GAIN_ODD_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__TIA_GAIN_ODD_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__SLM_XLNA_ODD_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__BQ_GAIN_ODD_241___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__XLNA_GAIN_EVEN_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__LNA_GAIN_EVEN_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__GM_GAIN_EVEN_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__TIA_GAIN_EVEN_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__SLM_XLNA_EVEN_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__BQ_GAIN_EVEN_241___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__XLNA_GAIN_ODD_241___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__XLNA_GAIN_ODD_241___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__LNA_GAIN_ODD_241___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__LNA_GAIN_ODD_241___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__GM_GAIN_ODD_241___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__GM_GAIN_ODD_241___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__TIA_GAIN_ODD_241___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__TIA_GAIN_ODD_241___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__SLM_XLNA_ODD_241___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__SLM_XLNA_ODD_241___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__BQ_GAIN_ODD_241___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__BQ_GAIN_ODD_241___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__XLNA_GAIN_EVEN_241___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__XLNA_GAIN_EVEN_241___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__LNA_GAIN_EVEN_241___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__LNA_GAIN_EVEN_241___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__GM_GAIN_EVEN_241___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__GM_GAIN_EVEN_241___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__TIA_GAIN_EVEN_241___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__TIA_GAIN_EVEN_241___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__SLM_XLNA_EVEN_241___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__SLM_XLNA_EVEN_241___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__BQ_GAIN_EVEN_241___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241__BQ_GAIN_EVEN_241___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_241___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242 (0x005E53C8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__XLNA_GAIN_ODD_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__LNA_GAIN_ODD_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__GM_GAIN_ODD_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__TIA_GAIN_ODD_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__SLM_XLNA_ODD_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__BQ_GAIN_ODD_242___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__XLNA_GAIN_EVEN_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__LNA_GAIN_EVEN_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__GM_GAIN_EVEN_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__TIA_GAIN_EVEN_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__SLM_XLNA_EVEN_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__BQ_GAIN_EVEN_242___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__XLNA_GAIN_ODD_242___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__XLNA_GAIN_ODD_242___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__LNA_GAIN_ODD_242___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__LNA_GAIN_ODD_242___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__GM_GAIN_ODD_242___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__GM_GAIN_ODD_242___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__TIA_GAIN_ODD_242___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__TIA_GAIN_ODD_242___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__SLM_XLNA_ODD_242___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__SLM_XLNA_ODD_242___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__BQ_GAIN_ODD_242___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__BQ_GAIN_ODD_242___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__XLNA_GAIN_EVEN_242___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__XLNA_GAIN_EVEN_242___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__LNA_GAIN_EVEN_242___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__LNA_GAIN_EVEN_242___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__GM_GAIN_EVEN_242___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__GM_GAIN_EVEN_242___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__TIA_GAIN_EVEN_242___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__TIA_GAIN_EVEN_242___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__SLM_XLNA_EVEN_242___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__SLM_XLNA_EVEN_242___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__BQ_GAIN_EVEN_242___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242__BQ_GAIN_EVEN_242___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_242___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243 (0x005E53CC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__XLNA_GAIN_ODD_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__LNA_GAIN_ODD_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__GM_GAIN_ODD_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__TIA_GAIN_ODD_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__SLM_XLNA_ODD_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__BQ_GAIN_ODD_243___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__XLNA_GAIN_EVEN_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__LNA_GAIN_EVEN_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__GM_GAIN_EVEN_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__TIA_GAIN_EVEN_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__SLM_XLNA_EVEN_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__BQ_GAIN_EVEN_243___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__XLNA_GAIN_ODD_243___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__XLNA_GAIN_ODD_243___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__LNA_GAIN_ODD_243___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__LNA_GAIN_ODD_243___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__GM_GAIN_ODD_243___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__GM_GAIN_ODD_243___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__TIA_GAIN_ODD_243___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__TIA_GAIN_ODD_243___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__SLM_XLNA_ODD_243___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__SLM_XLNA_ODD_243___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__BQ_GAIN_ODD_243___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__BQ_GAIN_ODD_243___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__XLNA_GAIN_EVEN_243___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__XLNA_GAIN_EVEN_243___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__LNA_GAIN_EVEN_243___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__LNA_GAIN_EVEN_243___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__GM_GAIN_EVEN_243___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__GM_GAIN_EVEN_243___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__TIA_GAIN_EVEN_243___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__TIA_GAIN_EVEN_243___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__SLM_XLNA_EVEN_243___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__SLM_XLNA_EVEN_243___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__BQ_GAIN_EVEN_243___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243__BQ_GAIN_EVEN_243___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_243___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244 (0x005E53D0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__XLNA_GAIN_ODD_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__LNA_GAIN_ODD_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__GM_GAIN_ODD_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__TIA_GAIN_ODD_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__SLM_XLNA_ODD_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__BQ_GAIN_ODD_244___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__XLNA_GAIN_EVEN_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__LNA_GAIN_EVEN_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__GM_GAIN_EVEN_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__TIA_GAIN_EVEN_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__SLM_XLNA_EVEN_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__BQ_GAIN_EVEN_244___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__XLNA_GAIN_ODD_244___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__XLNA_GAIN_ODD_244___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__LNA_GAIN_ODD_244___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__LNA_GAIN_ODD_244___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__GM_GAIN_ODD_244___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__GM_GAIN_ODD_244___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__TIA_GAIN_ODD_244___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__TIA_GAIN_ODD_244___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__SLM_XLNA_ODD_244___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__SLM_XLNA_ODD_244___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__BQ_GAIN_ODD_244___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__BQ_GAIN_ODD_244___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__XLNA_GAIN_EVEN_244___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__XLNA_GAIN_EVEN_244___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__LNA_GAIN_EVEN_244___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__LNA_GAIN_EVEN_244___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__GM_GAIN_EVEN_244___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__GM_GAIN_EVEN_244___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__TIA_GAIN_EVEN_244___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__TIA_GAIN_EVEN_244___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__SLM_XLNA_EVEN_244___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__SLM_XLNA_EVEN_244___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__BQ_GAIN_EVEN_244___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244__BQ_GAIN_EVEN_244___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_244___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245 (0x005E53D4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__XLNA_GAIN_ODD_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__LNA_GAIN_ODD_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__GM_GAIN_ODD_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__TIA_GAIN_ODD_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__SLM_XLNA_ODD_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__BQ_GAIN_ODD_245___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__XLNA_GAIN_EVEN_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__LNA_GAIN_EVEN_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__GM_GAIN_EVEN_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__TIA_GAIN_EVEN_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__SLM_XLNA_EVEN_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__BQ_GAIN_EVEN_245___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__XLNA_GAIN_ODD_245___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__XLNA_GAIN_ODD_245___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__LNA_GAIN_ODD_245___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__LNA_GAIN_ODD_245___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__GM_GAIN_ODD_245___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__GM_GAIN_ODD_245___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__TIA_GAIN_ODD_245___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__TIA_GAIN_ODD_245___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__SLM_XLNA_ODD_245___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__SLM_XLNA_ODD_245___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__BQ_GAIN_ODD_245___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__BQ_GAIN_ODD_245___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__XLNA_GAIN_EVEN_245___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__XLNA_GAIN_EVEN_245___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__LNA_GAIN_EVEN_245___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__LNA_GAIN_EVEN_245___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__GM_GAIN_EVEN_245___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__GM_GAIN_EVEN_245___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__TIA_GAIN_EVEN_245___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__TIA_GAIN_EVEN_245___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__SLM_XLNA_EVEN_245___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__SLM_XLNA_EVEN_245___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__BQ_GAIN_EVEN_245___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245__BQ_GAIN_EVEN_245___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_245___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246 (0x005E53D8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__XLNA_GAIN_ODD_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__LNA_GAIN_ODD_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__GM_GAIN_ODD_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__TIA_GAIN_ODD_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__SLM_XLNA_ODD_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__BQ_GAIN_ODD_246___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__XLNA_GAIN_EVEN_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__LNA_GAIN_EVEN_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__GM_GAIN_EVEN_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__TIA_GAIN_EVEN_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__SLM_XLNA_EVEN_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__BQ_GAIN_EVEN_246___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__XLNA_GAIN_ODD_246___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__XLNA_GAIN_ODD_246___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__LNA_GAIN_ODD_246___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__LNA_GAIN_ODD_246___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__GM_GAIN_ODD_246___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__GM_GAIN_ODD_246___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__TIA_GAIN_ODD_246___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__TIA_GAIN_ODD_246___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__SLM_XLNA_ODD_246___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__SLM_XLNA_ODD_246___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__BQ_GAIN_ODD_246___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__BQ_GAIN_ODD_246___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__XLNA_GAIN_EVEN_246___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__XLNA_GAIN_EVEN_246___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__LNA_GAIN_EVEN_246___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__LNA_GAIN_EVEN_246___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__GM_GAIN_EVEN_246___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__GM_GAIN_EVEN_246___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__TIA_GAIN_EVEN_246___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__TIA_GAIN_EVEN_246___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__SLM_XLNA_EVEN_246___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__SLM_XLNA_EVEN_246___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__BQ_GAIN_EVEN_246___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246__BQ_GAIN_EVEN_246___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_246___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247 (0x005E53DC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__XLNA_GAIN_ODD_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__LNA_GAIN_ODD_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__GM_GAIN_ODD_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__TIA_GAIN_ODD_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__SLM_XLNA_ODD_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__BQ_GAIN_ODD_247___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__XLNA_GAIN_EVEN_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__LNA_GAIN_EVEN_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__GM_GAIN_EVEN_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__TIA_GAIN_EVEN_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__SLM_XLNA_EVEN_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__BQ_GAIN_EVEN_247___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__XLNA_GAIN_ODD_247___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__XLNA_GAIN_ODD_247___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__LNA_GAIN_ODD_247___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__LNA_GAIN_ODD_247___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__GM_GAIN_ODD_247___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__GM_GAIN_ODD_247___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__TIA_GAIN_ODD_247___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__TIA_GAIN_ODD_247___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__SLM_XLNA_ODD_247___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__SLM_XLNA_ODD_247___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__BQ_GAIN_ODD_247___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__BQ_GAIN_ODD_247___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__XLNA_GAIN_EVEN_247___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__XLNA_GAIN_EVEN_247___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__LNA_GAIN_EVEN_247___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__LNA_GAIN_EVEN_247___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__GM_GAIN_EVEN_247___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__GM_GAIN_EVEN_247___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__TIA_GAIN_EVEN_247___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__TIA_GAIN_EVEN_247___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__SLM_XLNA_EVEN_247___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__SLM_XLNA_EVEN_247___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__BQ_GAIN_EVEN_247___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247__BQ_GAIN_EVEN_247___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_247___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248 (0x005E53E0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__XLNA_GAIN_ODD_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__LNA_GAIN_ODD_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__GM_GAIN_ODD_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__TIA_GAIN_ODD_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__SLM_XLNA_ODD_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__BQ_GAIN_ODD_248___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__XLNA_GAIN_EVEN_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__LNA_GAIN_EVEN_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__GM_GAIN_EVEN_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__TIA_GAIN_EVEN_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__SLM_XLNA_EVEN_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__BQ_GAIN_EVEN_248___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__XLNA_GAIN_ODD_248___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__XLNA_GAIN_ODD_248___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__LNA_GAIN_ODD_248___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__LNA_GAIN_ODD_248___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__GM_GAIN_ODD_248___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__GM_GAIN_ODD_248___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__TIA_GAIN_ODD_248___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__TIA_GAIN_ODD_248___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__SLM_XLNA_ODD_248___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__SLM_XLNA_ODD_248___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__BQ_GAIN_ODD_248___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__BQ_GAIN_ODD_248___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__XLNA_GAIN_EVEN_248___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__XLNA_GAIN_EVEN_248___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__LNA_GAIN_EVEN_248___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__LNA_GAIN_EVEN_248___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__GM_GAIN_EVEN_248___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__GM_GAIN_EVEN_248___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__TIA_GAIN_EVEN_248___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__TIA_GAIN_EVEN_248___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__SLM_XLNA_EVEN_248___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__SLM_XLNA_EVEN_248___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__BQ_GAIN_EVEN_248___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248__BQ_GAIN_EVEN_248___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_248___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249 (0x005E53E4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__XLNA_GAIN_ODD_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__LNA_GAIN_ODD_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__GM_GAIN_ODD_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__TIA_GAIN_ODD_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__SLM_XLNA_ODD_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__BQ_GAIN_ODD_249___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__XLNA_GAIN_EVEN_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__LNA_GAIN_EVEN_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__GM_GAIN_EVEN_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__TIA_GAIN_EVEN_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__SLM_XLNA_EVEN_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__BQ_GAIN_EVEN_249___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__XLNA_GAIN_ODD_249___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__XLNA_GAIN_ODD_249___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__LNA_GAIN_ODD_249___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__LNA_GAIN_ODD_249___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__GM_GAIN_ODD_249___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__GM_GAIN_ODD_249___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__TIA_GAIN_ODD_249___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__TIA_GAIN_ODD_249___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__SLM_XLNA_ODD_249___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__SLM_XLNA_ODD_249___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__BQ_GAIN_ODD_249___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__BQ_GAIN_ODD_249___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__XLNA_GAIN_EVEN_249___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__XLNA_GAIN_EVEN_249___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__LNA_GAIN_EVEN_249___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__LNA_GAIN_EVEN_249___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__GM_GAIN_EVEN_249___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__GM_GAIN_EVEN_249___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__TIA_GAIN_EVEN_249___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__TIA_GAIN_EVEN_249___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__SLM_XLNA_EVEN_249___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__SLM_XLNA_EVEN_249___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__BQ_GAIN_EVEN_249___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249__BQ_GAIN_EVEN_249___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_249___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250 (0x005E53E8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__XLNA_GAIN_ODD_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__LNA_GAIN_ODD_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__GM_GAIN_ODD_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__TIA_GAIN_ODD_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__SLM_XLNA_ODD_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__BQ_GAIN_ODD_250___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__XLNA_GAIN_EVEN_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__LNA_GAIN_EVEN_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__GM_GAIN_EVEN_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__TIA_GAIN_EVEN_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__SLM_XLNA_EVEN_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__BQ_GAIN_EVEN_250___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__XLNA_GAIN_ODD_250___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__XLNA_GAIN_ODD_250___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__LNA_GAIN_ODD_250___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__LNA_GAIN_ODD_250___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__GM_GAIN_ODD_250___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__GM_GAIN_ODD_250___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__TIA_GAIN_ODD_250___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__TIA_GAIN_ODD_250___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__SLM_XLNA_ODD_250___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__SLM_XLNA_ODD_250___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__BQ_GAIN_ODD_250___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__BQ_GAIN_ODD_250___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__XLNA_GAIN_EVEN_250___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__XLNA_GAIN_EVEN_250___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__LNA_GAIN_EVEN_250___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__LNA_GAIN_EVEN_250___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__GM_GAIN_EVEN_250___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__GM_GAIN_EVEN_250___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__TIA_GAIN_EVEN_250___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__TIA_GAIN_EVEN_250___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__SLM_XLNA_EVEN_250___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__SLM_XLNA_EVEN_250___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__BQ_GAIN_EVEN_250___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250__BQ_GAIN_EVEN_250___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_250___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251 (0x005E53EC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__XLNA_GAIN_ODD_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__LNA_GAIN_ODD_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__GM_GAIN_ODD_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__TIA_GAIN_ODD_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__SLM_XLNA_ODD_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__BQ_GAIN_ODD_251___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__XLNA_GAIN_EVEN_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__LNA_GAIN_EVEN_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__GM_GAIN_EVEN_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__TIA_GAIN_EVEN_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__SLM_XLNA_EVEN_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__BQ_GAIN_EVEN_251___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__XLNA_GAIN_ODD_251___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__XLNA_GAIN_ODD_251___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__LNA_GAIN_ODD_251___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__LNA_GAIN_ODD_251___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__GM_GAIN_ODD_251___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__GM_GAIN_ODD_251___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__TIA_GAIN_ODD_251___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__TIA_GAIN_ODD_251___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__SLM_XLNA_ODD_251___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__SLM_XLNA_ODD_251___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__BQ_GAIN_ODD_251___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__BQ_GAIN_ODD_251___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__XLNA_GAIN_EVEN_251___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__XLNA_GAIN_EVEN_251___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__LNA_GAIN_EVEN_251___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__LNA_GAIN_EVEN_251___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__GM_GAIN_EVEN_251___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__GM_GAIN_EVEN_251___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__TIA_GAIN_EVEN_251___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__TIA_GAIN_EVEN_251___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__SLM_XLNA_EVEN_251___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__SLM_XLNA_EVEN_251___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__BQ_GAIN_EVEN_251___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251__BQ_GAIN_EVEN_251___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_251___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252 (0x005E53F0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__XLNA_GAIN_ODD_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__LNA_GAIN_ODD_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__GM_GAIN_ODD_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__TIA_GAIN_ODD_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__SLM_XLNA_ODD_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__BQ_GAIN_ODD_252___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__XLNA_GAIN_EVEN_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__LNA_GAIN_EVEN_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__GM_GAIN_EVEN_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__TIA_GAIN_EVEN_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__SLM_XLNA_EVEN_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__BQ_GAIN_EVEN_252___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__XLNA_GAIN_ODD_252___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__XLNA_GAIN_ODD_252___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__LNA_GAIN_ODD_252___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__LNA_GAIN_ODD_252___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__GM_GAIN_ODD_252___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__GM_GAIN_ODD_252___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__TIA_GAIN_ODD_252___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__TIA_GAIN_ODD_252___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__SLM_XLNA_ODD_252___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__SLM_XLNA_ODD_252___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__BQ_GAIN_ODD_252___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__BQ_GAIN_ODD_252___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__XLNA_GAIN_EVEN_252___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__XLNA_GAIN_EVEN_252___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__LNA_GAIN_EVEN_252___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__LNA_GAIN_EVEN_252___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__GM_GAIN_EVEN_252___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__GM_GAIN_EVEN_252___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__TIA_GAIN_EVEN_252___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__TIA_GAIN_EVEN_252___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__SLM_XLNA_EVEN_252___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__SLM_XLNA_EVEN_252___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__BQ_GAIN_EVEN_252___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252__BQ_GAIN_EVEN_252___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_252___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253 (0x005E53F4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__XLNA_GAIN_ODD_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__LNA_GAIN_ODD_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__GM_GAIN_ODD_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__TIA_GAIN_ODD_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__SLM_XLNA_ODD_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__BQ_GAIN_ODD_253___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__XLNA_GAIN_EVEN_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__LNA_GAIN_EVEN_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__GM_GAIN_EVEN_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__TIA_GAIN_EVEN_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__SLM_XLNA_EVEN_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__BQ_GAIN_EVEN_253___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__XLNA_GAIN_ODD_253___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__XLNA_GAIN_ODD_253___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__LNA_GAIN_ODD_253___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__LNA_GAIN_ODD_253___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__GM_GAIN_ODD_253___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__GM_GAIN_ODD_253___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__TIA_GAIN_ODD_253___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__TIA_GAIN_ODD_253___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__SLM_XLNA_ODD_253___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__SLM_XLNA_ODD_253___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__BQ_GAIN_ODD_253___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__BQ_GAIN_ODD_253___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__XLNA_GAIN_EVEN_253___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__XLNA_GAIN_EVEN_253___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__LNA_GAIN_EVEN_253___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__LNA_GAIN_EVEN_253___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__GM_GAIN_EVEN_253___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__GM_GAIN_EVEN_253___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__TIA_GAIN_EVEN_253___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__TIA_GAIN_EVEN_253___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__SLM_XLNA_EVEN_253___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__SLM_XLNA_EVEN_253___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__BQ_GAIN_EVEN_253___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253__BQ_GAIN_EVEN_253___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_253___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254 (0x005E53F8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__XLNA_GAIN_ODD_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__LNA_GAIN_ODD_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__GM_GAIN_ODD_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__TIA_GAIN_ODD_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__SLM_XLNA_ODD_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__BQ_GAIN_ODD_254___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__XLNA_GAIN_EVEN_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__LNA_GAIN_EVEN_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__GM_GAIN_EVEN_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__TIA_GAIN_EVEN_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__SLM_XLNA_EVEN_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__BQ_GAIN_EVEN_254___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__XLNA_GAIN_ODD_254___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__XLNA_GAIN_ODD_254___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__LNA_GAIN_ODD_254___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__LNA_GAIN_ODD_254___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__GM_GAIN_ODD_254___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__GM_GAIN_ODD_254___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__TIA_GAIN_ODD_254___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__TIA_GAIN_ODD_254___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__SLM_XLNA_ODD_254___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__SLM_XLNA_ODD_254___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__BQ_GAIN_ODD_254___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__BQ_GAIN_ODD_254___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__XLNA_GAIN_EVEN_254___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__XLNA_GAIN_EVEN_254___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__LNA_GAIN_EVEN_254___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__LNA_GAIN_EVEN_254___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__GM_GAIN_EVEN_254___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__GM_GAIN_EVEN_254___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__TIA_GAIN_EVEN_254___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__TIA_GAIN_EVEN_254___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__SLM_XLNA_EVEN_254___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__SLM_XLNA_EVEN_254___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__BQ_GAIN_EVEN_254___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254__BQ_GAIN_EVEN_254___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_254___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255 (0x005E53FC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__XLNA_GAIN_ODD_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__LNA_GAIN_ODD_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__GM_GAIN_ODD_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__TIA_GAIN_ODD_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__SLM_XLNA_ODD_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__BQ_GAIN_ODD_255___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__XLNA_GAIN_EVEN_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__LNA_GAIN_EVEN_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__GM_GAIN_EVEN_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__TIA_GAIN_EVEN_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__SLM_XLNA_EVEN_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__BQ_GAIN_EVEN_255___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__XLNA_GAIN_ODD_255___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__XLNA_GAIN_ODD_255___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__LNA_GAIN_ODD_255___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__LNA_GAIN_ODD_255___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__GM_GAIN_ODD_255___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__GM_GAIN_ODD_255___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__TIA_GAIN_ODD_255___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__TIA_GAIN_ODD_255___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__SLM_XLNA_ODD_255___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__SLM_XLNA_ODD_255___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__BQ_GAIN_ODD_255___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__BQ_GAIN_ODD_255___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__XLNA_GAIN_EVEN_255___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__XLNA_GAIN_EVEN_255___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__LNA_GAIN_EVEN_255___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__LNA_GAIN_EVEN_255___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__GM_GAIN_EVEN_255___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__GM_GAIN_EVEN_255___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__TIA_GAIN_EVEN_255___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__TIA_GAIN_EVEN_255___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__SLM_XLNA_EVEN_255___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__SLM_XLNA_EVEN_255___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__BQ_GAIN_EVEN_255___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255__BQ_GAIN_EVEN_255___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_RXGAIN_255___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_0 (0x005E5800) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_0__TX_DCOC_RES_I_ODD_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_0__TX_DCOC_RES_Q_ODD_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_0__TX_DCOC_RES_I_EVEN_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_0__TX_DCOC_RES_Q_EVEN_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_0__TX_DCOC_RES_I_ODD_0___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_0__TX_DCOC_RES_I_ODD_0___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_0__TX_DCOC_RES_Q_ODD_0___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_0__TX_DCOC_RES_Q_ODD_0___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_0__TX_DCOC_RES_I_EVEN_0___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_0__TX_DCOC_RES_I_EVEN_0___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_0__TX_DCOC_RES_Q_EVEN_0___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_0__TX_DCOC_RES_Q_EVEN_0___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_0___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_1 (0x005E5804) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_1__TX_DCOC_RES_I_ODD_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_1__TX_DCOC_RES_Q_ODD_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_1__TX_DCOC_RES_I_EVEN_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_1__TX_DCOC_RES_Q_EVEN_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_1__TX_DCOC_RES_I_ODD_1___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_1__TX_DCOC_RES_I_ODD_1___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_1__TX_DCOC_RES_Q_ODD_1___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_1__TX_DCOC_RES_Q_ODD_1___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_1__TX_DCOC_RES_I_EVEN_1___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_1__TX_DCOC_RES_I_EVEN_1___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_1__TX_DCOC_RES_Q_EVEN_1___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_1__TX_DCOC_RES_Q_EVEN_1___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_1___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_2 (0x005E5808) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_2__TX_DCOC_RES_I_ODD_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_2__TX_DCOC_RES_Q_ODD_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_2__TX_DCOC_RES_I_EVEN_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_2__TX_DCOC_RES_Q_EVEN_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_2__TX_DCOC_RES_I_ODD_2___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_2__TX_DCOC_RES_I_ODD_2___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_2__TX_DCOC_RES_Q_ODD_2___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_2__TX_DCOC_RES_Q_ODD_2___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_2__TX_DCOC_RES_I_EVEN_2___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_2__TX_DCOC_RES_I_EVEN_2___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_2__TX_DCOC_RES_Q_EVEN_2___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_2__TX_DCOC_RES_Q_EVEN_2___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_2___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_2___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_3 (0x005E580C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_3__TX_DCOC_RES_I_ODD_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_3__TX_DCOC_RES_Q_ODD_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_3__TX_DCOC_RES_I_EVEN_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_3__TX_DCOC_RES_Q_EVEN_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_3__TX_DCOC_RES_I_ODD_3___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_3__TX_DCOC_RES_I_ODD_3___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_3__TX_DCOC_RES_Q_ODD_3___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_3__TX_DCOC_RES_Q_ODD_3___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_3__TX_DCOC_RES_I_EVEN_3___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_3__TX_DCOC_RES_I_EVEN_3___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_3__TX_DCOC_RES_Q_EVEN_3___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_3__TX_DCOC_RES_Q_EVEN_3___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_3___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_3___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_4 (0x005E5810) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_4__TX_DCOC_RES_I_ODD_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_4__TX_DCOC_RES_Q_ODD_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_4__TX_DCOC_RES_I_EVEN_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_4__TX_DCOC_RES_Q_EVEN_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_4__TX_DCOC_RES_I_ODD_4___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_4__TX_DCOC_RES_I_ODD_4___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_4__TX_DCOC_RES_Q_ODD_4___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_4__TX_DCOC_RES_Q_ODD_4___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_4__TX_DCOC_RES_I_EVEN_4___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_4__TX_DCOC_RES_I_EVEN_4___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_4__TX_DCOC_RES_Q_EVEN_4___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_4__TX_DCOC_RES_Q_EVEN_4___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_4___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_4___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_5 (0x005E5814) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_5__TX_DCOC_RES_I_ODD_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_5__TX_DCOC_RES_Q_ODD_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_5__TX_DCOC_RES_I_EVEN_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_5__TX_DCOC_RES_Q_EVEN_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_5__TX_DCOC_RES_I_ODD_5___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_5__TX_DCOC_RES_I_ODD_5___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_5__TX_DCOC_RES_Q_ODD_5___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_5__TX_DCOC_RES_Q_ODD_5___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_5__TX_DCOC_RES_I_EVEN_5___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_5__TX_DCOC_RES_I_EVEN_5___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_5__TX_DCOC_RES_Q_EVEN_5___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_5__TX_DCOC_RES_Q_EVEN_5___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_5___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_5___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_6 (0x005E5818) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_6__TX_DCOC_RES_I_ODD_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_6__TX_DCOC_RES_Q_ODD_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_6__TX_DCOC_RES_I_EVEN_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_6__TX_DCOC_RES_Q_EVEN_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_6__TX_DCOC_RES_I_ODD_6___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_6__TX_DCOC_RES_I_ODD_6___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_6__TX_DCOC_RES_Q_ODD_6___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_6__TX_DCOC_RES_Q_ODD_6___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_6__TX_DCOC_RES_I_EVEN_6___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_6__TX_DCOC_RES_I_EVEN_6___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_6__TX_DCOC_RES_Q_EVEN_6___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_6__TX_DCOC_RES_Q_EVEN_6___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_6___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_6___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_7 (0x005E581C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_7__TX_DCOC_RES_I_ODD_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_7__TX_DCOC_RES_Q_ODD_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_7__TX_DCOC_RES_I_EVEN_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_7__TX_DCOC_RES_Q_EVEN_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_7__TX_DCOC_RES_I_ODD_7___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_7__TX_DCOC_RES_I_ODD_7___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_7__TX_DCOC_RES_Q_ODD_7___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_7__TX_DCOC_RES_Q_ODD_7___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_7__TX_DCOC_RES_I_EVEN_7___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_7__TX_DCOC_RES_I_EVEN_7___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_7__TX_DCOC_RES_Q_EVEN_7___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_7__TX_DCOC_RES_Q_EVEN_7___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_7___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_7___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_8 (0x005E5820) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_8__TX_DCOC_RES_I_ODD_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_8__TX_DCOC_RES_Q_ODD_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_8__TX_DCOC_RES_I_EVEN_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_8__TX_DCOC_RES_Q_EVEN_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_8__TX_DCOC_RES_I_ODD_8___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_8__TX_DCOC_RES_I_ODD_8___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_8__TX_DCOC_RES_Q_ODD_8___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_8__TX_DCOC_RES_Q_ODD_8___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_8__TX_DCOC_RES_I_EVEN_8___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_8__TX_DCOC_RES_I_EVEN_8___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_8__TX_DCOC_RES_Q_EVEN_8___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_8__TX_DCOC_RES_Q_EVEN_8___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_8___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_8___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_9 (0x005E5824) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_9__TX_DCOC_RES_I_ODD_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_9__TX_DCOC_RES_Q_ODD_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_9__TX_DCOC_RES_I_EVEN_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_9__TX_DCOC_RES_Q_EVEN_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_9__TX_DCOC_RES_I_ODD_9___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_9__TX_DCOC_RES_I_ODD_9___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_9__TX_DCOC_RES_Q_ODD_9___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_9__TX_DCOC_RES_Q_ODD_9___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_9__TX_DCOC_RES_I_EVEN_9___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_9__TX_DCOC_RES_I_EVEN_9___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_9__TX_DCOC_RES_Q_EVEN_9___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_9__TX_DCOC_RES_Q_EVEN_9___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_9___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_9___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_10 (0x005E5828) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_10__TX_DCOC_RES_I_ODD_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_10__TX_DCOC_RES_Q_ODD_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_10__TX_DCOC_RES_I_EVEN_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_10__TX_DCOC_RES_Q_EVEN_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_10__TX_DCOC_RES_I_ODD_10___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_10__TX_DCOC_RES_I_ODD_10___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_10__TX_DCOC_RES_Q_ODD_10___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_10__TX_DCOC_RES_Q_ODD_10___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_10__TX_DCOC_RES_I_EVEN_10___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_10__TX_DCOC_RES_I_EVEN_10___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_10__TX_DCOC_RES_Q_EVEN_10___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_10__TX_DCOC_RES_Q_EVEN_10___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_10___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_10___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_11 (0x005E582C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_11__TX_DCOC_RES_I_ODD_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_11__TX_DCOC_RES_Q_ODD_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_11__TX_DCOC_RES_I_EVEN_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_11__TX_DCOC_RES_Q_EVEN_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_11__TX_DCOC_RES_I_ODD_11___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_11__TX_DCOC_RES_I_ODD_11___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_11__TX_DCOC_RES_Q_ODD_11___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_11__TX_DCOC_RES_Q_ODD_11___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_11__TX_DCOC_RES_I_EVEN_11___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_11__TX_DCOC_RES_I_EVEN_11___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_11__TX_DCOC_RES_Q_EVEN_11___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_11__TX_DCOC_RES_Q_EVEN_11___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_11___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_11___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_12 (0x005E5830) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_12__TX_DCOC_RES_I_ODD_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_12__TX_DCOC_RES_Q_ODD_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_12__TX_DCOC_RES_I_EVEN_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_12__TX_DCOC_RES_Q_EVEN_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_12__TX_DCOC_RES_I_ODD_12___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_12__TX_DCOC_RES_I_ODD_12___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_12__TX_DCOC_RES_Q_ODD_12___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_12__TX_DCOC_RES_Q_ODD_12___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_12__TX_DCOC_RES_I_EVEN_12___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_12__TX_DCOC_RES_I_EVEN_12___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_12__TX_DCOC_RES_Q_EVEN_12___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_12__TX_DCOC_RES_Q_EVEN_12___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_12___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_12___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_13 (0x005E5834) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_13__TX_DCOC_RES_I_ODD_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_13__TX_DCOC_RES_Q_ODD_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_13__TX_DCOC_RES_I_EVEN_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_13__TX_DCOC_RES_Q_EVEN_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_13__TX_DCOC_RES_I_ODD_13___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_13__TX_DCOC_RES_I_ODD_13___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_13__TX_DCOC_RES_Q_ODD_13___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_13__TX_DCOC_RES_Q_ODD_13___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_13__TX_DCOC_RES_I_EVEN_13___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_13__TX_DCOC_RES_I_EVEN_13___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_13__TX_DCOC_RES_Q_EVEN_13___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_13__TX_DCOC_RES_Q_EVEN_13___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_13___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_13___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_14 (0x005E5838) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_14__TX_DCOC_RES_I_ODD_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_14__TX_DCOC_RES_Q_ODD_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_14__TX_DCOC_RES_I_EVEN_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_14__TX_DCOC_RES_Q_EVEN_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_14__TX_DCOC_RES_I_ODD_14___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_14__TX_DCOC_RES_I_ODD_14___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_14__TX_DCOC_RES_Q_ODD_14___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_14__TX_DCOC_RES_Q_ODD_14___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_14__TX_DCOC_RES_I_EVEN_14___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_14__TX_DCOC_RES_I_EVEN_14___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_14__TX_DCOC_RES_Q_EVEN_14___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_14__TX_DCOC_RES_Q_EVEN_14___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_14___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_14___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_15 (0x005E583C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_15__TX_DCOC_RES_I_ODD_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_15__TX_DCOC_RES_Q_ODD_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_15__TX_DCOC_RES_I_EVEN_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_15__TX_DCOC_RES_Q_EVEN_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_15__TX_DCOC_RES_I_ODD_15___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_15__TX_DCOC_RES_I_ODD_15___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_15__TX_DCOC_RES_Q_ODD_15___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_15__TX_DCOC_RES_Q_ODD_15___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_15__TX_DCOC_RES_I_EVEN_15___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_15__TX_DCOC_RES_I_EVEN_15___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_15__TX_DCOC_RES_Q_EVEN_15___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_15__TX_DCOC_RES_Q_EVEN_15___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_15___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_15___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_16 (0x005E5840) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_16___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_16__TX_DCOC_RES_I_ODD_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_16__TX_DCOC_RES_Q_ODD_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_16__TX_DCOC_RES_I_EVEN_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_16__TX_DCOC_RES_Q_EVEN_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_16__TX_DCOC_RES_I_ODD_16___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_16__TX_DCOC_RES_I_ODD_16___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_16__TX_DCOC_RES_Q_ODD_16___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_16__TX_DCOC_RES_Q_ODD_16___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_16__TX_DCOC_RES_I_EVEN_16___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_16__TX_DCOC_RES_I_EVEN_16___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_16__TX_DCOC_RES_Q_EVEN_16___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_16__TX_DCOC_RES_Q_EVEN_16___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_16___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_16___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_17 (0x005E5844) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_17___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_17__TX_DCOC_RES_I_ODD_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_17__TX_DCOC_RES_Q_ODD_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_17__TX_DCOC_RES_I_EVEN_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_17__TX_DCOC_RES_Q_EVEN_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_17__TX_DCOC_RES_I_ODD_17___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_17__TX_DCOC_RES_I_ODD_17___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_17__TX_DCOC_RES_Q_ODD_17___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_17__TX_DCOC_RES_Q_ODD_17___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_17__TX_DCOC_RES_I_EVEN_17___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_17__TX_DCOC_RES_I_EVEN_17___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_17__TX_DCOC_RES_Q_EVEN_17___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_17__TX_DCOC_RES_Q_EVEN_17___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_17___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_17___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_18 (0x005E5848) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_18___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_18__TX_DCOC_RES_I_ODD_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_18__TX_DCOC_RES_Q_ODD_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_18__TX_DCOC_RES_I_EVEN_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_18__TX_DCOC_RES_Q_EVEN_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_18__TX_DCOC_RES_I_ODD_18___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_18__TX_DCOC_RES_I_ODD_18___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_18__TX_DCOC_RES_Q_ODD_18___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_18__TX_DCOC_RES_Q_ODD_18___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_18__TX_DCOC_RES_I_EVEN_18___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_18__TX_DCOC_RES_I_EVEN_18___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_18__TX_DCOC_RES_Q_EVEN_18___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_18__TX_DCOC_RES_Q_EVEN_18___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_18___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_18___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_19 (0x005E584C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_19___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_19__TX_DCOC_RES_I_ODD_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_19__TX_DCOC_RES_Q_ODD_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_19__TX_DCOC_RES_I_EVEN_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_19__TX_DCOC_RES_Q_EVEN_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_19__TX_DCOC_RES_I_ODD_19___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_19__TX_DCOC_RES_I_ODD_19___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_19__TX_DCOC_RES_Q_ODD_19___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_19__TX_DCOC_RES_Q_ODD_19___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_19__TX_DCOC_RES_I_EVEN_19___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_19__TX_DCOC_RES_I_EVEN_19___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_19__TX_DCOC_RES_Q_EVEN_19___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_19__TX_DCOC_RES_Q_EVEN_19___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_19___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_19___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_20 (0x005E5850) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_20___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_20__TX_DCOC_RES_I_ODD_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_20__TX_DCOC_RES_Q_ODD_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_20__TX_DCOC_RES_I_EVEN_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_20__TX_DCOC_RES_Q_EVEN_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_20__TX_DCOC_RES_I_ODD_20___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_20__TX_DCOC_RES_I_ODD_20___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_20__TX_DCOC_RES_Q_ODD_20___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_20__TX_DCOC_RES_Q_ODD_20___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_20__TX_DCOC_RES_I_EVEN_20___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_20__TX_DCOC_RES_I_EVEN_20___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_20__TX_DCOC_RES_Q_EVEN_20___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_20__TX_DCOC_RES_Q_EVEN_20___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_20___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_20___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_21 (0x005E5854) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_21___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_21__TX_DCOC_RES_I_ODD_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_21__TX_DCOC_RES_Q_ODD_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_21__TX_DCOC_RES_I_EVEN_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_21__TX_DCOC_RES_Q_EVEN_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_21__TX_DCOC_RES_I_ODD_21___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_21__TX_DCOC_RES_I_ODD_21___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_21__TX_DCOC_RES_Q_ODD_21___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_21__TX_DCOC_RES_Q_ODD_21___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_21__TX_DCOC_RES_I_EVEN_21___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_21__TX_DCOC_RES_I_EVEN_21___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_21__TX_DCOC_RES_Q_EVEN_21___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_21__TX_DCOC_RES_Q_EVEN_21___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_21___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_21___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_22 (0x005E5858) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_22___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_22__TX_DCOC_RES_I_ODD_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_22__TX_DCOC_RES_Q_ODD_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_22__TX_DCOC_RES_I_EVEN_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_22__TX_DCOC_RES_Q_EVEN_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_22__TX_DCOC_RES_I_ODD_22___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_22__TX_DCOC_RES_I_ODD_22___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_22__TX_DCOC_RES_Q_ODD_22___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_22__TX_DCOC_RES_Q_ODD_22___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_22__TX_DCOC_RES_I_EVEN_22___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_22__TX_DCOC_RES_I_EVEN_22___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_22__TX_DCOC_RES_Q_EVEN_22___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_22__TX_DCOC_RES_Q_EVEN_22___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_22___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_22___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_23 (0x005E585C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_23___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_23__TX_DCOC_RES_I_ODD_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_23__TX_DCOC_RES_Q_ODD_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_23__TX_DCOC_RES_I_EVEN_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_23__TX_DCOC_RES_Q_EVEN_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_23__TX_DCOC_RES_I_ODD_23___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_23__TX_DCOC_RES_I_ODD_23___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_23__TX_DCOC_RES_Q_ODD_23___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_23__TX_DCOC_RES_Q_ODD_23___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_23__TX_DCOC_RES_I_EVEN_23___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_23__TX_DCOC_RES_I_EVEN_23___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_23__TX_DCOC_RES_Q_EVEN_23___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_23__TX_DCOC_RES_Q_EVEN_23___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_23___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_23___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_24 (0x005E5860) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_24___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_24__TX_DCOC_RES_I_ODD_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_24__TX_DCOC_RES_Q_ODD_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_24__TX_DCOC_RES_I_EVEN_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_24__TX_DCOC_RES_Q_EVEN_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_24__TX_DCOC_RES_I_ODD_24___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_24__TX_DCOC_RES_I_ODD_24___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_24__TX_DCOC_RES_Q_ODD_24___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_24__TX_DCOC_RES_Q_ODD_24___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_24__TX_DCOC_RES_I_EVEN_24___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_24__TX_DCOC_RES_I_EVEN_24___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_24__TX_DCOC_RES_Q_EVEN_24___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_24__TX_DCOC_RES_Q_EVEN_24___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_24___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_24___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_25 (0x005E5864) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_25___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_25__TX_DCOC_RES_I_ODD_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_25__TX_DCOC_RES_Q_ODD_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_25__TX_DCOC_RES_I_EVEN_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_25__TX_DCOC_RES_Q_EVEN_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_25__TX_DCOC_RES_I_ODD_25___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_25__TX_DCOC_RES_I_ODD_25___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_25__TX_DCOC_RES_Q_ODD_25___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_25__TX_DCOC_RES_Q_ODD_25___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_25__TX_DCOC_RES_I_EVEN_25___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_25__TX_DCOC_RES_I_EVEN_25___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_25__TX_DCOC_RES_Q_EVEN_25___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_25__TX_DCOC_RES_Q_EVEN_25___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_25___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_25___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_26 (0x005E5868) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_26___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_26__TX_DCOC_RES_I_ODD_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_26__TX_DCOC_RES_Q_ODD_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_26__TX_DCOC_RES_I_EVEN_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_26__TX_DCOC_RES_Q_EVEN_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_26__TX_DCOC_RES_I_ODD_26___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_26__TX_DCOC_RES_I_ODD_26___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_26__TX_DCOC_RES_Q_ODD_26___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_26__TX_DCOC_RES_Q_ODD_26___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_26__TX_DCOC_RES_I_EVEN_26___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_26__TX_DCOC_RES_I_EVEN_26___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_26__TX_DCOC_RES_Q_EVEN_26___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_26__TX_DCOC_RES_Q_EVEN_26___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_26___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_26___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_27 (0x005E586C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_27___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_27__TX_DCOC_RES_I_ODD_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_27__TX_DCOC_RES_Q_ODD_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_27__TX_DCOC_RES_I_EVEN_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_27__TX_DCOC_RES_Q_EVEN_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_27__TX_DCOC_RES_I_ODD_27___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_27__TX_DCOC_RES_I_ODD_27___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_27__TX_DCOC_RES_Q_ODD_27___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_27__TX_DCOC_RES_Q_ODD_27___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_27__TX_DCOC_RES_I_EVEN_27___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_27__TX_DCOC_RES_I_EVEN_27___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_27__TX_DCOC_RES_Q_EVEN_27___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_27__TX_DCOC_RES_Q_EVEN_27___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_27___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_27___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_28 (0x005E5870) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_28___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_28__TX_DCOC_RES_I_ODD_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_28__TX_DCOC_RES_Q_ODD_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_28__TX_DCOC_RES_I_EVEN_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_28__TX_DCOC_RES_Q_EVEN_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_28__TX_DCOC_RES_I_ODD_28___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_28__TX_DCOC_RES_I_ODD_28___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_28__TX_DCOC_RES_Q_ODD_28___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_28__TX_DCOC_RES_Q_ODD_28___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_28__TX_DCOC_RES_I_EVEN_28___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_28__TX_DCOC_RES_I_EVEN_28___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_28__TX_DCOC_RES_Q_EVEN_28___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_28__TX_DCOC_RES_Q_EVEN_28___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_28___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_28___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_29 (0x005E5874) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_29___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_29__TX_DCOC_RES_I_ODD_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_29__TX_DCOC_RES_Q_ODD_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_29__TX_DCOC_RES_I_EVEN_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_29__TX_DCOC_RES_Q_EVEN_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_29__TX_DCOC_RES_I_ODD_29___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_29__TX_DCOC_RES_I_ODD_29___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_29__TX_DCOC_RES_Q_ODD_29___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_29__TX_DCOC_RES_Q_ODD_29___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_29__TX_DCOC_RES_I_EVEN_29___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_29__TX_DCOC_RES_I_EVEN_29___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_29__TX_DCOC_RES_Q_EVEN_29___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_29__TX_DCOC_RES_Q_EVEN_29___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_29___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_29___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_30 (0x005E5878) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_30___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_30__TX_DCOC_RES_I_ODD_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_30__TX_DCOC_RES_Q_ODD_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_30__TX_DCOC_RES_I_EVEN_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_30__TX_DCOC_RES_Q_EVEN_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_30__TX_DCOC_RES_I_ODD_30___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_30__TX_DCOC_RES_I_ODD_30___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_30__TX_DCOC_RES_Q_ODD_30___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_30__TX_DCOC_RES_Q_ODD_30___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_30__TX_DCOC_RES_I_EVEN_30___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_30__TX_DCOC_RES_I_EVEN_30___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_30__TX_DCOC_RES_Q_EVEN_30___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_30__TX_DCOC_RES_Q_EVEN_30___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_30___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_30___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_31 (0x005E587C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_31___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_31__TX_DCOC_RES_I_ODD_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_31__TX_DCOC_RES_Q_ODD_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_31__TX_DCOC_RES_I_EVEN_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_31__TX_DCOC_RES_Q_EVEN_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_31__TX_DCOC_RES_I_ODD_31___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_31__TX_DCOC_RES_I_ODD_31___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_31__TX_DCOC_RES_Q_ODD_31___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_31__TX_DCOC_RES_Q_ODD_31___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_31__TX_DCOC_RES_I_EVEN_31___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_31__TX_DCOC_RES_I_EVEN_31___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_31__TX_DCOC_RES_Q_EVEN_31___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_31__TX_DCOC_RES_Q_EVEN_31___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_31___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_31___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_32 (0x005E5880) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_32___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_32___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_32__TX_DCOC_RES_I_ODD_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_32__TX_DCOC_RES_Q_ODD_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_32__TX_DCOC_RES_I_EVEN_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_32__TX_DCOC_RES_Q_EVEN_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_32__TX_DCOC_RES_I_ODD_32___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_32__TX_DCOC_RES_I_ODD_32___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_32__TX_DCOC_RES_Q_ODD_32___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_32__TX_DCOC_RES_Q_ODD_32___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_32__TX_DCOC_RES_I_EVEN_32___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_32__TX_DCOC_RES_I_EVEN_32___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_32__TX_DCOC_RES_Q_EVEN_32___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_32__TX_DCOC_RES_Q_EVEN_32___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_32___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_32___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_33 (0x005E5884) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_33___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_33___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_33__TX_DCOC_RES_I_ODD_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_33__TX_DCOC_RES_Q_ODD_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_33__TX_DCOC_RES_I_EVEN_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_33__TX_DCOC_RES_Q_EVEN_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_33__TX_DCOC_RES_I_ODD_33___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_33__TX_DCOC_RES_I_ODD_33___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_33__TX_DCOC_RES_Q_ODD_33___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_33__TX_DCOC_RES_Q_ODD_33___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_33__TX_DCOC_RES_I_EVEN_33___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_33__TX_DCOC_RES_I_EVEN_33___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_33__TX_DCOC_RES_Q_EVEN_33___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_33__TX_DCOC_RES_Q_EVEN_33___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_33___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_33___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_34 (0x005E5888) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_34___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_34___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_34__TX_DCOC_RES_I_ODD_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_34__TX_DCOC_RES_Q_ODD_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_34__TX_DCOC_RES_I_EVEN_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_34__TX_DCOC_RES_Q_EVEN_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_34__TX_DCOC_RES_I_ODD_34___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_34__TX_DCOC_RES_I_ODD_34___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_34__TX_DCOC_RES_Q_ODD_34___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_34__TX_DCOC_RES_Q_ODD_34___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_34__TX_DCOC_RES_I_EVEN_34___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_34__TX_DCOC_RES_I_EVEN_34___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_34__TX_DCOC_RES_Q_EVEN_34___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_34__TX_DCOC_RES_Q_EVEN_34___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_34___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_34___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_35 (0x005E588C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_35___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_35___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_35__TX_DCOC_RES_I_ODD_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_35__TX_DCOC_RES_Q_ODD_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_35__TX_DCOC_RES_I_EVEN_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_35__TX_DCOC_RES_Q_EVEN_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_35__TX_DCOC_RES_I_ODD_35___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_35__TX_DCOC_RES_I_ODD_35___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_35__TX_DCOC_RES_Q_ODD_35___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_35__TX_DCOC_RES_Q_ODD_35___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_35__TX_DCOC_RES_I_EVEN_35___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_35__TX_DCOC_RES_I_EVEN_35___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_35__TX_DCOC_RES_Q_EVEN_35___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_35__TX_DCOC_RES_Q_EVEN_35___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_35___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_35___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_36 (0x005E5890) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_36___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_36___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_36__TX_DCOC_RES_I_ODD_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_36__TX_DCOC_RES_Q_ODD_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_36__TX_DCOC_RES_I_EVEN_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_36__TX_DCOC_RES_Q_EVEN_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_36__TX_DCOC_RES_I_ODD_36___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_36__TX_DCOC_RES_I_ODD_36___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_36__TX_DCOC_RES_Q_ODD_36___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_36__TX_DCOC_RES_Q_ODD_36___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_36__TX_DCOC_RES_I_EVEN_36___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_36__TX_DCOC_RES_I_EVEN_36___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_36__TX_DCOC_RES_Q_EVEN_36___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_36__TX_DCOC_RES_Q_EVEN_36___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_36___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_36___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_37 (0x005E5894) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_37___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_37___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_37__TX_DCOC_RES_I_ODD_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_37__TX_DCOC_RES_Q_ODD_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_37__TX_DCOC_RES_I_EVEN_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_37__TX_DCOC_RES_Q_EVEN_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_37__TX_DCOC_RES_I_ODD_37___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_37__TX_DCOC_RES_I_ODD_37___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_37__TX_DCOC_RES_Q_ODD_37___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_37__TX_DCOC_RES_Q_ODD_37___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_37__TX_DCOC_RES_I_EVEN_37___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_37__TX_DCOC_RES_I_EVEN_37___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_37__TX_DCOC_RES_Q_EVEN_37___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_37__TX_DCOC_RES_Q_EVEN_37___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_37___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_37___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_38 (0x005E5898) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_38___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_38___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_38__TX_DCOC_RES_I_ODD_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_38__TX_DCOC_RES_Q_ODD_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_38__TX_DCOC_RES_I_EVEN_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_38__TX_DCOC_RES_Q_EVEN_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_38__TX_DCOC_RES_I_ODD_38___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_38__TX_DCOC_RES_I_ODD_38___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_38__TX_DCOC_RES_Q_ODD_38___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_38__TX_DCOC_RES_Q_ODD_38___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_38__TX_DCOC_RES_I_EVEN_38___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_38__TX_DCOC_RES_I_EVEN_38___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_38__TX_DCOC_RES_Q_EVEN_38___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_38__TX_DCOC_RES_Q_EVEN_38___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_38___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_38___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_39 (0x005E589C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_39___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_39___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_39__TX_DCOC_RES_I_ODD_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_39__TX_DCOC_RES_Q_ODD_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_39__TX_DCOC_RES_I_EVEN_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_39__TX_DCOC_RES_Q_EVEN_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_39__TX_DCOC_RES_I_ODD_39___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_39__TX_DCOC_RES_I_ODD_39___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_39__TX_DCOC_RES_Q_ODD_39___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_39__TX_DCOC_RES_Q_ODD_39___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_39__TX_DCOC_RES_I_EVEN_39___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_39__TX_DCOC_RES_I_EVEN_39___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_39__TX_DCOC_RES_Q_EVEN_39___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_39__TX_DCOC_RES_Q_EVEN_39___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_39___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_39___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_40 (0x005E58A0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_40___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_40___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_40__TX_DCOC_RES_I_ODD_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_40__TX_DCOC_RES_Q_ODD_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_40__TX_DCOC_RES_I_EVEN_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_40__TX_DCOC_RES_Q_EVEN_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_40__TX_DCOC_RES_I_ODD_40___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_40__TX_DCOC_RES_I_ODD_40___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_40__TX_DCOC_RES_Q_ODD_40___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_40__TX_DCOC_RES_Q_ODD_40___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_40__TX_DCOC_RES_I_EVEN_40___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_40__TX_DCOC_RES_I_EVEN_40___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_40__TX_DCOC_RES_Q_EVEN_40___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_40__TX_DCOC_RES_Q_EVEN_40___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_40___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_40___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_41 (0x005E58A4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_41___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_41___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_41__TX_DCOC_RES_I_ODD_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_41__TX_DCOC_RES_Q_ODD_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_41__TX_DCOC_RES_I_EVEN_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_41__TX_DCOC_RES_Q_EVEN_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_41__TX_DCOC_RES_I_ODD_41___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_41__TX_DCOC_RES_I_ODD_41___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_41__TX_DCOC_RES_Q_ODD_41___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_41__TX_DCOC_RES_Q_ODD_41___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_41__TX_DCOC_RES_I_EVEN_41___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_41__TX_DCOC_RES_I_EVEN_41___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_41__TX_DCOC_RES_Q_EVEN_41___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_41__TX_DCOC_RES_Q_EVEN_41___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_41___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_41___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_42 (0x005E58A8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_42___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_42___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_42__TX_DCOC_RES_I_ODD_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_42__TX_DCOC_RES_Q_ODD_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_42__TX_DCOC_RES_I_EVEN_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_42__TX_DCOC_RES_Q_EVEN_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_42__TX_DCOC_RES_I_ODD_42___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_42__TX_DCOC_RES_I_ODD_42___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_42__TX_DCOC_RES_Q_ODD_42___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_42__TX_DCOC_RES_Q_ODD_42___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_42__TX_DCOC_RES_I_EVEN_42___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_42__TX_DCOC_RES_I_EVEN_42___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_42__TX_DCOC_RES_Q_EVEN_42___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_42__TX_DCOC_RES_Q_EVEN_42___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_42___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_42___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_43 (0x005E58AC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_43___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_43___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_43__TX_DCOC_RES_I_ODD_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_43__TX_DCOC_RES_Q_ODD_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_43__TX_DCOC_RES_I_EVEN_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_43__TX_DCOC_RES_Q_EVEN_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_43__TX_DCOC_RES_I_ODD_43___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_43__TX_DCOC_RES_I_ODD_43___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_43__TX_DCOC_RES_Q_ODD_43___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_43__TX_DCOC_RES_Q_ODD_43___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_43__TX_DCOC_RES_I_EVEN_43___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_43__TX_DCOC_RES_I_EVEN_43___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_43__TX_DCOC_RES_Q_EVEN_43___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_43__TX_DCOC_RES_Q_EVEN_43___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_43___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_43___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_44 (0x005E58B0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_44___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_44___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_44__TX_DCOC_RES_I_ODD_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_44__TX_DCOC_RES_Q_ODD_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_44__TX_DCOC_RES_I_EVEN_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_44__TX_DCOC_RES_Q_EVEN_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_44__TX_DCOC_RES_I_ODD_44___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_44__TX_DCOC_RES_I_ODD_44___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_44__TX_DCOC_RES_Q_ODD_44___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_44__TX_DCOC_RES_Q_ODD_44___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_44__TX_DCOC_RES_I_EVEN_44___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_44__TX_DCOC_RES_I_EVEN_44___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_44__TX_DCOC_RES_Q_EVEN_44___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_44__TX_DCOC_RES_Q_EVEN_44___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_44___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_44___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_45 (0x005E58B4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_45___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_45___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_45__TX_DCOC_RES_I_ODD_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_45__TX_DCOC_RES_Q_ODD_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_45__TX_DCOC_RES_I_EVEN_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_45__TX_DCOC_RES_Q_EVEN_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_45__TX_DCOC_RES_I_ODD_45___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_45__TX_DCOC_RES_I_ODD_45___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_45__TX_DCOC_RES_Q_ODD_45___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_45__TX_DCOC_RES_Q_ODD_45___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_45__TX_DCOC_RES_I_EVEN_45___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_45__TX_DCOC_RES_I_EVEN_45___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_45__TX_DCOC_RES_Q_EVEN_45___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_45__TX_DCOC_RES_Q_EVEN_45___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_45___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_45___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_46 (0x005E58B8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_46___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_46___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_46__TX_DCOC_RES_I_ODD_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_46__TX_DCOC_RES_Q_ODD_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_46__TX_DCOC_RES_I_EVEN_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_46__TX_DCOC_RES_Q_EVEN_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_46__TX_DCOC_RES_I_ODD_46___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_46__TX_DCOC_RES_I_ODD_46___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_46__TX_DCOC_RES_Q_ODD_46___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_46__TX_DCOC_RES_Q_ODD_46___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_46__TX_DCOC_RES_I_EVEN_46___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_46__TX_DCOC_RES_I_EVEN_46___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_46__TX_DCOC_RES_Q_EVEN_46___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_46__TX_DCOC_RES_Q_EVEN_46___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_46___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_46___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_47 (0x005E58BC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_47___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_47___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_47__TX_DCOC_RES_I_ODD_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_47__TX_DCOC_RES_Q_ODD_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_47__TX_DCOC_RES_I_EVEN_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_47__TX_DCOC_RES_Q_EVEN_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_47__TX_DCOC_RES_I_ODD_47___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_47__TX_DCOC_RES_I_ODD_47___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_47__TX_DCOC_RES_Q_ODD_47___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_47__TX_DCOC_RES_Q_ODD_47___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_47__TX_DCOC_RES_I_EVEN_47___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_47__TX_DCOC_RES_I_EVEN_47___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_47__TX_DCOC_RES_Q_EVEN_47___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_47__TX_DCOC_RES_Q_EVEN_47___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_47___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_47___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_48 (0x005E58C0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_48___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_48___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_48__TX_DCOC_RES_I_ODD_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_48__TX_DCOC_RES_Q_ODD_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_48__TX_DCOC_RES_I_EVEN_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_48__TX_DCOC_RES_Q_EVEN_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_48__TX_DCOC_RES_I_ODD_48___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_48__TX_DCOC_RES_I_ODD_48___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_48__TX_DCOC_RES_Q_ODD_48___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_48__TX_DCOC_RES_Q_ODD_48___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_48__TX_DCOC_RES_I_EVEN_48___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_48__TX_DCOC_RES_I_EVEN_48___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_48__TX_DCOC_RES_Q_EVEN_48___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_48__TX_DCOC_RES_Q_EVEN_48___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_48___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_48___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_49 (0x005E58C4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_49___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_49___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_49__TX_DCOC_RES_I_ODD_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_49__TX_DCOC_RES_Q_ODD_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_49__TX_DCOC_RES_I_EVEN_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_49__TX_DCOC_RES_Q_EVEN_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_49__TX_DCOC_RES_I_ODD_49___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_49__TX_DCOC_RES_I_ODD_49___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_49__TX_DCOC_RES_Q_ODD_49___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_49__TX_DCOC_RES_Q_ODD_49___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_49__TX_DCOC_RES_I_EVEN_49___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_49__TX_DCOC_RES_I_EVEN_49___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_49__TX_DCOC_RES_Q_EVEN_49___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_49__TX_DCOC_RES_Q_EVEN_49___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_49___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_49___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_50 (0x005E58C8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_50___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_50___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_50__TX_DCOC_RES_I_ODD_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_50__TX_DCOC_RES_Q_ODD_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_50__TX_DCOC_RES_I_EVEN_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_50__TX_DCOC_RES_Q_EVEN_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_50__TX_DCOC_RES_I_ODD_50___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_50__TX_DCOC_RES_I_ODD_50___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_50__TX_DCOC_RES_Q_ODD_50___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_50__TX_DCOC_RES_Q_ODD_50___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_50__TX_DCOC_RES_I_EVEN_50___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_50__TX_DCOC_RES_I_EVEN_50___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_50__TX_DCOC_RES_Q_EVEN_50___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_50__TX_DCOC_RES_Q_EVEN_50___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_50___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_50___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_51 (0x005E58CC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_51___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_51___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_51__TX_DCOC_RES_I_ODD_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_51__TX_DCOC_RES_Q_ODD_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_51__TX_DCOC_RES_I_EVEN_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_51__TX_DCOC_RES_Q_EVEN_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_51__TX_DCOC_RES_I_ODD_51___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_51__TX_DCOC_RES_I_ODD_51___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_51__TX_DCOC_RES_Q_ODD_51___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_51__TX_DCOC_RES_Q_ODD_51___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_51__TX_DCOC_RES_I_EVEN_51___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_51__TX_DCOC_RES_I_EVEN_51___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_51__TX_DCOC_RES_Q_EVEN_51___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_51__TX_DCOC_RES_Q_EVEN_51___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_51___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_51___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_52 (0x005E58D0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_52___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_52___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_52__TX_DCOC_RES_I_ODD_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_52__TX_DCOC_RES_Q_ODD_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_52__TX_DCOC_RES_I_EVEN_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_52__TX_DCOC_RES_Q_EVEN_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_52__TX_DCOC_RES_I_ODD_52___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_52__TX_DCOC_RES_I_ODD_52___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_52__TX_DCOC_RES_Q_ODD_52___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_52__TX_DCOC_RES_Q_ODD_52___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_52__TX_DCOC_RES_I_EVEN_52___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_52__TX_DCOC_RES_I_EVEN_52___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_52__TX_DCOC_RES_Q_EVEN_52___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_52__TX_DCOC_RES_Q_EVEN_52___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_52___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_52___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_53 (0x005E58D4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_53___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_53___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_53__TX_DCOC_RES_I_ODD_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_53__TX_DCOC_RES_Q_ODD_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_53__TX_DCOC_RES_I_EVEN_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_53__TX_DCOC_RES_Q_EVEN_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_53__TX_DCOC_RES_I_ODD_53___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_53__TX_DCOC_RES_I_ODD_53___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_53__TX_DCOC_RES_Q_ODD_53___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_53__TX_DCOC_RES_Q_ODD_53___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_53__TX_DCOC_RES_I_EVEN_53___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_53__TX_DCOC_RES_I_EVEN_53___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_53__TX_DCOC_RES_Q_EVEN_53___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_53__TX_DCOC_RES_Q_EVEN_53___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_53___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_53___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_54 (0x005E58D8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_54___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_54___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_54__TX_DCOC_RES_I_ODD_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_54__TX_DCOC_RES_Q_ODD_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_54__TX_DCOC_RES_I_EVEN_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_54__TX_DCOC_RES_Q_EVEN_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_54__TX_DCOC_RES_I_ODD_54___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_54__TX_DCOC_RES_I_ODD_54___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_54__TX_DCOC_RES_Q_ODD_54___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_54__TX_DCOC_RES_Q_ODD_54___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_54__TX_DCOC_RES_I_EVEN_54___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_54__TX_DCOC_RES_I_EVEN_54___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_54__TX_DCOC_RES_Q_EVEN_54___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_54__TX_DCOC_RES_Q_EVEN_54___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_54___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_54___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_55 (0x005E58DC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_55___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_55___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_55__TX_DCOC_RES_I_ODD_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_55__TX_DCOC_RES_Q_ODD_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_55__TX_DCOC_RES_I_EVEN_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_55__TX_DCOC_RES_Q_EVEN_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_55__TX_DCOC_RES_I_ODD_55___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_55__TX_DCOC_RES_I_ODD_55___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_55__TX_DCOC_RES_Q_ODD_55___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_55__TX_DCOC_RES_Q_ODD_55___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_55__TX_DCOC_RES_I_EVEN_55___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_55__TX_DCOC_RES_I_EVEN_55___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_55__TX_DCOC_RES_Q_EVEN_55___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_55__TX_DCOC_RES_Q_EVEN_55___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_55___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_55___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_56 (0x005E58E0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_56___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_56___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_56__TX_DCOC_RES_I_ODD_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_56__TX_DCOC_RES_Q_ODD_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_56__TX_DCOC_RES_I_EVEN_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_56__TX_DCOC_RES_Q_EVEN_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_56__TX_DCOC_RES_I_ODD_56___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_56__TX_DCOC_RES_I_ODD_56___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_56__TX_DCOC_RES_Q_ODD_56___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_56__TX_DCOC_RES_Q_ODD_56___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_56__TX_DCOC_RES_I_EVEN_56___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_56__TX_DCOC_RES_I_EVEN_56___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_56__TX_DCOC_RES_Q_EVEN_56___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_56__TX_DCOC_RES_Q_EVEN_56___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_56___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_56___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_57 (0x005E58E4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_57___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_57___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_57__TX_DCOC_RES_I_ODD_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_57__TX_DCOC_RES_Q_ODD_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_57__TX_DCOC_RES_I_EVEN_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_57__TX_DCOC_RES_Q_EVEN_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_57__TX_DCOC_RES_I_ODD_57___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_57__TX_DCOC_RES_I_ODD_57___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_57__TX_DCOC_RES_Q_ODD_57___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_57__TX_DCOC_RES_Q_ODD_57___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_57__TX_DCOC_RES_I_EVEN_57___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_57__TX_DCOC_RES_I_EVEN_57___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_57__TX_DCOC_RES_Q_EVEN_57___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_57__TX_DCOC_RES_Q_EVEN_57___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_57___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_57___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_58 (0x005E58E8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_58___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_58___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_58__TX_DCOC_RES_I_ODD_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_58__TX_DCOC_RES_Q_ODD_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_58__TX_DCOC_RES_I_EVEN_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_58__TX_DCOC_RES_Q_EVEN_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_58__TX_DCOC_RES_I_ODD_58___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_58__TX_DCOC_RES_I_ODD_58___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_58__TX_DCOC_RES_Q_ODD_58___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_58__TX_DCOC_RES_Q_ODD_58___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_58__TX_DCOC_RES_I_EVEN_58___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_58__TX_DCOC_RES_I_EVEN_58___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_58__TX_DCOC_RES_Q_EVEN_58___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_58__TX_DCOC_RES_Q_EVEN_58___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_58___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_58___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_59 (0x005E58EC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_59___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_59___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_59__TX_DCOC_RES_I_ODD_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_59__TX_DCOC_RES_Q_ODD_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_59__TX_DCOC_RES_I_EVEN_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_59__TX_DCOC_RES_Q_EVEN_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_59__TX_DCOC_RES_I_ODD_59___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_59__TX_DCOC_RES_I_ODD_59___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_59__TX_DCOC_RES_Q_ODD_59___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_59__TX_DCOC_RES_Q_ODD_59___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_59__TX_DCOC_RES_I_EVEN_59___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_59__TX_DCOC_RES_I_EVEN_59___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_59__TX_DCOC_RES_Q_EVEN_59___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_59__TX_DCOC_RES_Q_EVEN_59___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_59___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_59___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_60 (0x005E58F0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_60___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_60___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_60__TX_DCOC_RES_I_ODD_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_60__TX_DCOC_RES_Q_ODD_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_60__TX_DCOC_RES_I_EVEN_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_60__TX_DCOC_RES_Q_EVEN_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_60__TX_DCOC_RES_I_ODD_60___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_60__TX_DCOC_RES_I_ODD_60___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_60__TX_DCOC_RES_Q_ODD_60___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_60__TX_DCOC_RES_Q_ODD_60___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_60__TX_DCOC_RES_I_EVEN_60___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_60__TX_DCOC_RES_I_EVEN_60___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_60__TX_DCOC_RES_Q_EVEN_60___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_60__TX_DCOC_RES_Q_EVEN_60___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_60___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_60___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_61 (0x005E58F4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_61___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_61___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_61__TX_DCOC_RES_I_ODD_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_61__TX_DCOC_RES_Q_ODD_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_61__TX_DCOC_RES_I_EVEN_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_61__TX_DCOC_RES_Q_EVEN_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_61__TX_DCOC_RES_I_ODD_61___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_61__TX_DCOC_RES_I_ODD_61___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_61__TX_DCOC_RES_Q_ODD_61___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_61__TX_DCOC_RES_Q_ODD_61___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_61__TX_DCOC_RES_I_EVEN_61___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_61__TX_DCOC_RES_I_EVEN_61___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_61__TX_DCOC_RES_Q_EVEN_61___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_61__TX_DCOC_RES_Q_EVEN_61___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_61___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_61___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_62 (0x005E58F8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_62___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_62___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_62__TX_DCOC_RES_I_ODD_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_62__TX_DCOC_RES_Q_ODD_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_62__TX_DCOC_RES_I_EVEN_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_62__TX_DCOC_RES_Q_EVEN_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_62__TX_DCOC_RES_I_ODD_62___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_62__TX_DCOC_RES_I_ODD_62___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_62__TX_DCOC_RES_Q_ODD_62___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_62__TX_DCOC_RES_Q_ODD_62___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_62__TX_DCOC_RES_I_EVEN_62___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_62__TX_DCOC_RES_I_EVEN_62___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_62__TX_DCOC_RES_Q_EVEN_62___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_62__TX_DCOC_RES_Q_EVEN_62___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_62___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_62___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_63 (0x005E58FC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_63___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_63___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_63__TX_DCOC_RES_I_ODD_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_63__TX_DCOC_RES_Q_ODD_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_63__TX_DCOC_RES_I_EVEN_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_63__TX_DCOC_RES_Q_EVEN_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_63__TX_DCOC_RES_I_ODD_63___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_63__TX_DCOC_RES_I_ODD_63___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_63__TX_DCOC_RES_Q_ODD_63___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_63__TX_DCOC_RES_Q_ODD_63___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_63__TX_DCOC_RES_I_EVEN_63___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_63__TX_DCOC_RES_I_EVEN_63___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_63__TX_DCOC_RES_Q_EVEN_63___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_63__TX_DCOC_RES_Q_EVEN_63___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_63___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_63___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_64 (0x005E5900) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_64___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_64___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_64__TX_DCOC_RES_I_ODD_64___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_64__TX_DCOC_RES_Q_ODD_64___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_64__TX_DCOC_RES_I_EVEN_64___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_64__TX_DCOC_RES_Q_EVEN_64___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_64__TX_DCOC_RES_I_ODD_64___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_64__TX_DCOC_RES_I_ODD_64___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_64__TX_DCOC_RES_Q_ODD_64___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_64__TX_DCOC_RES_Q_ODD_64___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_64__TX_DCOC_RES_I_EVEN_64___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_64__TX_DCOC_RES_I_EVEN_64___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_64__TX_DCOC_RES_Q_EVEN_64___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_64__TX_DCOC_RES_Q_EVEN_64___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_64___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_64___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_65 (0x005E5904) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_65___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_65___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_65__TX_DCOC_RES_I_ODD_65___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_65__TX_DCOC_RES_Q_ODD_65___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_65__TX_DCOC_RES_I_EVEN_65___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_65__TX_DCOC_RES_Q_EVEN_65___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_65__TX_DCOC_RES_I_ODD_65___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_65__TX_DCOC_RES_I_ODD_65___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_65__TX_DCOC_RES_Q_ODD_65___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_65__TX_DCOC_RES_Q_ODD_65___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_65__TX_DCOC_RES_I_EVEN_65___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_65__TX_DCOC_RES_I_EVEN_65___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_65__TX_DCOC_RES_Q_EVEN_65___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_65__TX_DCOC_RES_Q_EVEN_65___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_65___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_65___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_66 (0x005E5908) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_66___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_66___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_66__TX_DCOC_RES_I_ODD_66___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_66__TX_DCOC_RES_Q_ODD_66___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_66__TX_DCOC_RES_I_EVEN_66___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_66__TX_DCOC_RES_Q_EVEN_66___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_66__TX_DCOC_RES_I_ODD_66___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_66__TX_DCOC_RES_I_ODD_66___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_66__TX_DCOC_RES_Q_ODD_66___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_66__TX_DCOC_RES_Q_ODD_66___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_66__TX_DCOC_RES_I_EVEN_66___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_66__TX_DCOC_RES_I_EVEN_66___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_66__TX_DCOC_RES_Q_EVEN_66___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_66__TX_DCOC_RES_Q_EVEN_66___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_66___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_66___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_67 (0x005E590C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_67___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_67___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_67__TX_DCOC_RES_I_ODD_67___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_67__TX_DCOC_RES_Q_ODD_67___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_67__TX_DCOC_RES_I_EVEN_67___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_67__TX_DCOC_RES_Q_EVEN_67___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_67__TX_DCOC_RES_I_ODD_67___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_67__TX_DCOC_RES_I_ODD_67___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_67__TX_DCOC_RES_Q_ODD_67___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_67__TX_DCOC_RES_Q_ODD_67___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_67__TX_DCOC_RES_I_EVEN_67___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_67__TX_DCOC_RES_I_EVEN_67___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_67__TX_DCOC_RES_Q_EVEN_67___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_67__TX_DCOC_RES_Q_EVEN_67___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_67___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_67___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_68 (0x005E5910) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_68___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_68___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_68__TX_DCOC_RES_I_ODD_68___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_68__TX_DCOC_RES_Q_ODD_68___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_68__TX_DCOC_RES_I_EVEN_68___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_68__TX_DCOC_RES_Q_EVEN_68___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_68__TX_DCOC_RES_I_ODD_68___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_68__TX_DCOC_RES_I_ODD_68___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_68__TX_DCOC_RES_Q_ODD_68___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_68__TX_DCOC_RES_Q_ODD_68___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_68__TX_DCOC_RES_I_EVEN_68___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_68__TX_DCOC_RES_I_EVEN_68___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_68__TX_DCOC_RES_Q_EVEN_68___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_68__TX_DCOC_RES_Q_EVEN_68___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_68___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_68___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_69 (0x005E5914) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_69___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_69___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_69__TX_DCOC_RES_I_ODD_69___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_69__TX_DCOC_RES_Q_ODD_69___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_69__TX_DCOC_RES_I_EVEN_69___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_69__TX_DCOC_RES_Q_EVEN_69___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_69__TX_DCOC_RES_I_ODD_69___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_69__TX_DCOC_RES_I_ODD_69___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_69__TX_DCOC_RES_Q_ODD_69___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_69__TX_DCOC_RES_Q_ODD_69___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_69__TX_DCOC_RES_I_EVEN_69___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_69__TX_DCOC_RES_I_EVEN_69___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_69__TX_DCOC_RES_Q_EVEN_69___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_69__TX_DCOC_RES_Q_EVEN_69___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_69___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_69___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_70 (0x005E5918) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_70___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_70___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_70__TX_DCOC_RES_I_ODD_70___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_70__TX_DCOC_RES_Q_ODD_70___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_70__TX_DCOC_RES_I_EVEN_70___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_70__TX_DCOC_RES_Q_EVEN_70___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_70__TX_DCOC_RES_I_ODD_70___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_70__TX_DCOC_RES_I_ODD_70___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_70__TX_DCOC_RES_Q_ODD_70___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_70__TX_DCOC_RES_Q_ODD_70___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_70__TX_DCOC_RES_I_EVEN_70___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_70__TX_DCOC_RES_I_EVEN_70___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_70__TX_DCOC_RES_Q_EVEN_70___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_70__TX_DCOC_RES_Q_EVEN_70___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_70___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_70___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_71 (0x005E591C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_71___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_71___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_71__TX_DCOC_RES_I_ODD_71___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_71__TX_DCOC_RES_Q_ODD_71___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_71__TX_DCOC_RES_I_EVEN_71___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_71__TX_DCOC_RES_Q_EVEN_71___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_71__TX_DCOC_RES_I_ODD_71___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_71__TX_DCOC_RES_I_ODD_71___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_71__TX_DCOC_RES_Q_ODD_71___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_71__TX_DCOC_RES_Q_ODD_71___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_71__TX_DCOC_RES_I_EVEN_71___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_71__TX_DCOC_RES_I_EVEN_71___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_71__TX_DCOC_RES_Q_EVEN_71___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_71__TX_DCOC_RES_Q_EVEN_71___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_71___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_71___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_72 (0x005E5920) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_72___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_72___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_72__TX_DCOC_RES_I_ODD_72___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_72__TX_DCOC_RES_Q_ODD_72___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_72__TX_DCOC_RES_I_EVEN_72___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_72__TX_DCOC_RES_Q_EVEN_72___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_72__TX_DCOC_RES_I_ODD_72___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_72__TX_DCOC_RES_I_ODD_72___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_72__TX_DCOC_RES_Q_ODD_72___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_72__TX_DCOC_RES_Q_ODD_72___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_72__TX_DCOC_RES_I_EVEN_72___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_72__TX_DCOC_RES_I_EVEN_72___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_72__TX_DCOC_RES_Q_EVEN_72___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_72__TX_DCOC_RES_Q_EVEN_72___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_72___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_72___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_73 (0x005E5924) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_73___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_73___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_73__TX_DCOC_RES_I_ODD_73___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_73__TX_DCOC_RES_Q_ODD_73___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_73__TX_DCOC_RES_I_EVEN_73___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_73__TX_DCOC_RES_Q_EVEN_73___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_73__TX_DCOC_RES_I_ODD_73___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_73__TX_DCOC_RES_I_ODD_73___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_73__TX_DCOC_RES_Q_ODD_73___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_73__TX_DCOC_RES_Q_ODD_73___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_73__TX_DCOC_RES_I_EVEN_73___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_73__TX_DCOC_RES_I_EVEN_73___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_73__TX_DCOC_RES_Q_EVEN_73___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_73__TX_DCOC_RES_Q_EVEN_73___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_73___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_73___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_74 (0x005E5928) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_74___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_74___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_74__TX_DCOC_RES_I_ODD_74___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_74__TX_DCOC_RES_Q_ODD_74___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_74__TX_DCOC_RES_I_EVEN_74___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_74__TX_DCOC_RES_Q_EVEN_74___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_74__TX_DCOC_RES_I_ODD_74___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_74__TX_DCOC_RES_I_ODD_74___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_74__TX_DCOC_RES_Q_ODD_74___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_74__TX_DCOC_RES_Q_ODD_74___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_74__TX_DCOC_RES_I_EVEN_74___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_74__TX_DCOC_RES_I_EVEN_74___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_74__TX_DCOC_RES_Q_EVEN_74___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_74__TX_DCOC_RES_Q_EVEN_74___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_74___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_74___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_75 (0x005E592C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_75___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_75___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_75__TX_DCOC_RES_I_ODD_75___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_75__TX_DCOC_RES_Q_ODD_75___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_75__TX_DCOC_RES_I_EVEN_75___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_75__TX_DCOC_RES_Q_EVEN_75___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_75__TX_DCOC_RES_I_ODD_75___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_75__TX_DCOC_RES_I_ODD_75___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_75__TX_DCOC_RES_Q_ODD_75___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_75__TX_DCOC_RES_Q_ODD_75___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_75__TX_DCOC_RES_I_EVEN_75___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_75__TX_DCOC_RES_I_EVEN_75___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_75__TX_DCOC_RES_Q_EVEN_75___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_75__TX_DCOC_RES_Q_EVEN_75___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_75___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_75___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_76 (0x005E5930) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_76___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_76___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_76__TX_DCOC_RES_I_ODD_76___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_76__TX_DCOC_RES_Q_ODD_76___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_76__TX_DCOC_RES_I_EVEN_76___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_76__TX_DCOC_RES_Q_EVEN_76___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_76__TX_DCOC_RES_I_ODD_76___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_76__TX_DCOC_RES_I_ODD_76___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_76__TX_DCOC_RES_Q_ODD_76___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_76__TX_DCOC_RES_Q_ODD_76___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_76__TX_DCOC_RES_I_EVEN_76___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_76__TX_DCOC_RES_I_EVEN_76___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_76__TX_DCOC_RES_Q_EVEN_76___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_76__TX_DCOC_RES_Q_EVEN_76___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_76___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_76___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_77 (0x005E5934) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_77___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_77___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_77__TX_DCOC_RES_I_ODD_77___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_77__TX_DCOC_RES_Q_ODD_77___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_77__TX_DCOC_RES_I_EVEN_77___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_77__TX_DCOC_RES_Q_EVEN_77___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_77__TX_DCOC_RES_I_ODD_77___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_77__TX_DCOC_RES_I_ODD_77___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_77__TX_DCOC_RES_Q_ODD_77___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_77__TX_DCOC_RES_Q_ODD_77___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_77__TX_DCOC_RES_I_EVEN_77___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_77__TX_DCOC_RES_I_EVEN_77___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_77__TX_DCOC_RES_Q_EVEN_77___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_77__TX_DCOC_RES_Q_EVEN_77___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_77___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_77___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_78 (0x005E5938) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_78___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_78___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_78__TX_DCOC_RES_I_ODD_78___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_78__TX_DCOC_RES_Q_ODD_78___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_78__TX_DCOC_RES_I_EVEN_78___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_78__TX_DCOC_RES_Q_EVEN_78___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_78__TX_DCOC_RES_I_ODD_78___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_78__TX_DCOC_RES_I_ODD_78___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_78__TX_DCOC_RES_Q_ODD_78___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_78__TX_DCOC_RES_Q_ODD_78___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_78__TX_DCOC_RES_I_EVEN_78___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_78__TX_DCOC_RES_I_EVEN_78___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_78__TX_DCOC_RES_Q_EVEN_78___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_78__TX_DCOC_RES_Q_EVEN_78___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_78___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_78___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_79 (0x005E593C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_79___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_79___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_79__TX_DCOC_RES_I_ODD_79___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_79__TX_DCOC_RES_Q_ODD_79___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_79__TX_DCOC_RES_I_EVEN_79___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_79__TX_DCOC_RES_Q_EVEN_79___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_79__TX_DCOC_RES_I_ODD_79___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_79__TX_DCOC_RES_I_ODD_79___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_79__TX_DCOC_RES_Q_ODD_79___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_79__TX_DCOC_RES_Q_ODD_79___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_79__TX_DCOC_RES_I_EVEN_79___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_79__TX_DCOC_RES_I_EVEN_79___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_79__TX_DCOC_RES_Q_EVEN_79___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_79__TX_DCOC_RES_Q_EVEN_79___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_79___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_79___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_80 (0x005E5940) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_80___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_80___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_80__TX_DCOC_RES_I_ODD_80___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_80__TX_DCOC_RES_Q_ODD_80___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_80__TX_DCOC_RES_I_EVEN_80___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_80__TX_DCOC_RES_Q_EVEN_80___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_80__TX_DCOC_RES_I_ODD_80___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_80__TX_DCOC_RES_I_ODD_80___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_80__TX_DCOC_RES_Q_ODD_80___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_80__TX_DCOC_RES_Q_ODD_80___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_80__TX_DCOC_RES_I_EVEN_80___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_80__TX_DCOC_RES_I_EVEN_80___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_80__TX_DCOC_RES_Q_EVEN_80___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_80__TX_DCOC_RES_Q_EVEN_80___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_80___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_80___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_81 (0x005E5944) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_81___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_81___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_81__TX_DCOC_RES_I_ODD_81___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_81__TX_DCOC_RES_Q_ODD_81___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_81__TX_DCOC_RES_I_EVEN_81___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_81__TX_DCOC_RES_Q_EVEN_81___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_81__TX_DCOC_RES_I_ODD_81___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_81__TX_DCOC_RES_I_ODD_81___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_81__TX_DCOC_RES_Q_ODD_81___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_81__TX_DCOC_RES_Q_ODD_81___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_81__TX_DCOC_RES_I_EVEN_81___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_81__TX_DCOC_RES_I_EVEN_81___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_81__TX_DCOC_RES_Q_EVEN_81___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_81__TX_DCOC_RES_Q_EVEN_81___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_81___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_81___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_82 (0x005E5948) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_82___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_82___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_82__TX_DCOC_RES_I_ODD_82___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_82__TX_DCOC_RES_Q_ODD_82___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_82__TX_DCOC_RES_I_EVEN_82___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_82__TX_DCOC_RES_Q_EVEN_82___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_82__TX_DCOC_RES_I_ODD_82___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_82__TX_DCOC_RES_I_ODD_82___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_82__TX_DCOC_RES_Q_ODD_82___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_82__TX_DCOC_RES_Q_ODD_82___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_82__TX_DCOC_RES_I_EVEN_82___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_82__TX_DCOC_RES_I_EVEN_82___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_82__TX_DCOC_RES_Q_EVEN_82___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_82__TX_DCOC_RES_Q_EVEN_82___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_82___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_82___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_83 (0x005E594C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_83___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_83___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_83__TX_DCOC_RES_I_ODD_83___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_83__TX_DCOC_RES_Q_ODD_83___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_83__TX_DCOC_RES_I_EVEN_83___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_83__TX_DCOC_RES_Q_EVEN_83___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_83__TX_DCOC_RES_I_ODD_83___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_83__TX_DCOC_RES_I_ODD_83___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_83__TX_DCOC_RES_Q_ODD_83___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_83__TX_DCOC_RES_Q_ODD_83___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_83__TX_DCOC_RES_I_EVEN_83___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_83__TX_DCOC_RES_I_EVEN_83___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_83__TX_DCOC_RES_Q_EVEN_83___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_83__TX_DCOC_RES_Q_EVEN_83___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_83___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_83___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_84 (0x005E5950) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_84___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_84___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_84__TX_DCOC_RES_I_ODD_84___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_84__TX_DCOC_RES_Q_ODD_84___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_84__TX_DCOC_RES_I_EVEN_84___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_84__TX_DCOC_RES_Q_EVEN_84___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_84__TX_DCOC_RES_I_ODD_84___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_84__TX_DCOC_RES_I_ODD_84___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_84__TX_DCOC_RES_Q_ODD_84___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_84__TX_DCOC_RES_Q_ODD_84___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_84__TX_DCOC_RES_I_EVEN_84___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_84__TX_DCOC_RES_I_EVEN_84___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_84__TX_DCOC_RES_Q_EVEN_84___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_84__TX_DCOC_RES_Q_EVEN_84___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_84___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_84___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_85 (0x005E5954) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_85___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_85___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_85__TX_DCOC_RES_I_ODD_85___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_85__TX_DCOC_RES_Q_ODD_85___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_85__TX_DCOC_RES_I_EVEN_85___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_85__TX_DCOC_RES_Q_EVEN_85___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_85__TX_DCOC_RES_I_ODD_85___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_85__TX_DCOC_RES_I_ODD_85___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_85__TX_DCOC_RES_Q_ODD_85___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_85__TX_DCOC_RES_Q_ODD_85___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_85__TX_DCOC_RES_I_EVEN_85___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_85__TX_DCOC_RES_I_EVEN_85___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_85__TX_DCOC_RES_Q_EVEN_85___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_85__TX_DCOC_RES_Q_EVEN_85___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_85___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_85___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_86 (0x005E5958) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_86___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_86___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_86__TX_DCOC_RES_I_ODD_86___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_86__TX_DCOC_RES_Q_ODD_86___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_86__TX_DCOC_RES_I_EVEN_86___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_86__TX_DCOC_RES_Q_EVEN_86___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_86__TX_DCOC_RES_I_ODD_86___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_86__TX_DCOC_RES_I_ODD_86___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_86__TX_DCOC_RES_Q_ODD_86___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_86__TX_DCOC_RES_Q_ODD_86___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_86__TX_DCOC_RES_I_EVEN_86___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_86__TX_DCOC_RES_I_EVEN_86___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_86__TX_DCOC_RES_Q_EVEN_86___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_86__TX_DCOC_RES_Q_EVEN_86___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_86___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_86___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_87 (0x005E595C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_87___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_87___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_87__TX_DCOC_RES_I_ODD_87___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_87__TX_DCOC_RES_Q_ODD_87___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_87__TX_DCOC_RES_I_EVEN_87___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_87__TX_DCOC_RES_Q_EVEN_87___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_87__TX_DCOC_RES_I_ODD_87___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_87__TX_DCOC_RES_I_ODD_87___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_87__TX_DCOC_RES_Q_ODD_87___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_87__TX_DCOC_RES_Q_ODD_87___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_87__TX_DCOC_RES_I_EVEN_87___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_87__TX_DCOC_RES_I_EVEN_87___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_87__TX_DCOC_RES_Q_EVEN_87___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_87__TX_DCOC_RES_Q_EVEN_87___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_87___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_87___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_88 (0x005E5960) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_88___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_88___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_88__TX_DCOC_RES_I_ODD_88___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_88__TX_DCOC_RES_Q_ODD_88___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_88__TX_DCOC_RES_I_EVEN_88___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_88__TX_DCOC_RES_Q_EVEN_88___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_88__TX_DCOC_RES_I_ODD_88___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_88__TX_DCOC_RES_I_ODD_88___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_88__TX_DCOC_RES_Q_ODD_88___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_88__TX_DCOC_RES_Q_ODD_88___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_88__TX_DCOC_RES_I_EVEN_88___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_88__TX_DCOC_RES_I_EVEN_88___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_88__TX_DCOC_RES_Q_EVEN_88___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_88__TX_DCOC_RES_Q_EVEN_88___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_88___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_88___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_89 (0x005E5964) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_89___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_89___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_89__TX_DCOC_RES_I_ODD_89___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_89__TX_DCOC_RES_Q_ODD_89___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_89__TX_DCOC_RES_I_EVEN_89___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_89__TX_DCOC_RES_Q_EVEN_89___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_89__TX_DCOC_RES_I_ODD_89___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_89__TX_DCOC_RES_I_ODD_89___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_89__TX_DCOC_RES_Q_ODD_89___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_89__TX_DCOC_RES_Q_ODD_89___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_89__TX_DCOC_RES_I_EVEN_89___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_89__TX_DCOC_RES_I_EVEN_89___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_89__TX_DCOC_RES_Q_EVEN_89___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_89__TX_DCOC_RES_Q_EVEN_89___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_89___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_89___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_90 (0x005E5968) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_90___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_90___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_90__TX_DCOC_RES_I_ODD_90___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_90__TX_DCOC_RES_Q_ODD_90___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_90__TX_DCOC_RES_I_EVEN_90___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_90__TX_DCOC_RES_Q_EVEN_90___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_90__TX_DCOC_RES_I_ODD_90___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_90__TX_DCOC_RES_I_ODD_90___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_90__TX_DCOC_RES_Q_ODD_90___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_90__TX_DCOC_RES_Q_ODD_90___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_90__TX_DCOC_RES_I_EVEN_90___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_90__TX_DCOC_RES_I_EVEN_90___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_90__TX_DCOC_RES_Q_EVEN_90___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_90__TX_DCOC_RES_Q_EVEN_90___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_90___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_90___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_91 (0x005E596C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_91___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_91___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_91__TX_DCOC_RES_I_ODD_91___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_91__TX_DCOC_RES_Q_ODD_91___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_91__TX_DCOC_RES_I_EVEN_91___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_91__TX_DCOC_RES_Q_EVEN_91___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_91__TX_DCOC_RES_I_ODD_91___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_91__TX_DCOC_RES_I_ODD_91___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_91__TX_DCOC_RES_Q_ODD_91___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_91__TX_DCOC_RES_Q_ODD_91___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_91__TX_DCOC_RES_I_EVEN_91___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_91__TX_DCOC_RES_I_EVEN_91___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_91__TX_DCOC_RES_Q_EVEN_91___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_91__TX_DCOC_RES_Q_EVEN_91___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_91___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_91___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_92 (0x005E5970) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_92___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_92___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_92__TX_DCOC_RES_I_ODD_92___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_92__TX_DCOC_RES_Q_ODD_92___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_92__TX_DCOC_RES_I_EVEN_92___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_92__TX_DCOC_RES_Q_EVEN_92___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_92__TX_DCOC_RES_I_ODD_92___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_92__TX_DCOC_RES_I_ODD_92___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_92__TX_DCOC_RES_Q_ODD_92___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_92__TX_DCOC_RES_Q_ODD_92___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_92__TX_DCOC_RES_I_EVEN_92___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_92__TX_DCOC_RES_I_EVEN_92___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_92__TX_DCOC_RES_Q_EVEN_92___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_92__TX_DCOC_RES_Q_EVEN_92___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_92___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_92___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_93 (0x005E5974) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_93___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_93___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_93__TX_DCOC_RES_I_ODD_93___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_93__TX_DCOC_RES_Q_ODD_93___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_93__TX_DCOC_RES_I_EVEN_93___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_93__TX_DCOC_RES_Q_EVEN_93___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_93__TX_DCOC_RES_I_ODD_93___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_93__TX_DCOC_RES_I_ODD_93___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_93__TX_DCOC_RES_Q_ODD_93___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_93__TX_DCOC_RES_Q_ODD_93___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_93__TX_DCOC_RES_I_EVEN_93___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_93__TX_DCOC_RES_I_EVEN_93___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_93__TX_DCOC_RES_Q_EVEN_93___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_93__TX_DCOC_RES_Q_EVEN_93___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_93___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_93___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_94 (0x005E5978) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_94___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_94___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_94__TX_DCOC_RES_I_ODD_94___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_94__TX_DCOC_RES_Q_ODD_94___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_94__TX_DCOC_RES_I_EVEN_94___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_94__TX_DCOC_RES_Q_EVEN_94___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_94__TX_DCOC_RES_I_ODD_94___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_94__TX_DCOC_RES_I_ODD_94___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_94__TX_DCOC_RES_Q_ODD_94___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_94__TX_DCOC_RES_Q_ODD_94___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_94__TX_DCOC_RES_I_EVEN_94___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_94__TX_DCOC_RES_I_EVEN_94___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_94__TX_DCOC_RES_Q_EVEN_94___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_94__TX_DCOC_RES_Q_EVEN_94___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_94___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_94___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_95 (0x005E597C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_95___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_95___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_95__TX_DCOC_RES_I_ODD_95___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_95__TX_DCOC_RES_Q_ODD_95___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_95__TX_DCOC_RES_I_EVEN_95___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_95__TX_DCOC_RES_Q_EVEN_95___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_95__TX_DCOC_RES_I_ODD_95___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_95__TX_DCOC_RES_I_ODD_95___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_95__TX_DCOC_RES_Q_ODD_95___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_95__TX_DCOC_RES_Q_ODD_95___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_95__TX_DCOC_RES_I_EVEN_95___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_95__TX_DCOC_RES_I_EVEN_95___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_95__TX_DCOC_RES_Q_EVEN_95___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_95__TX_DCOC_RES_Q_EVEN_95___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_95___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_95___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_96 (0x005E5980) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_96___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_96___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_96__TX_DCOC_RES_I_ODD_96___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_96__TX_DCOC_RES_Q_ODD_96___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_96__TX_DCOC_RES_I_EVEN_96___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_96__TX_DCOC_RES_Q_EVEN_96___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_96__TX_DCOC_RES_I_ODD_96___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_96__TX_DCOC_RES_I_ODD_96___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_96__TX_DCOC_RES_Q_ODD_96___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_96__TX_DCOC_RES_Q_ODD_96___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_96__TX_DCOC_RES_I_EVEN_96___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_96__TX_DCOC_RES_I_EVEN_96___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_96__TX_DCOC_RES_Q_EVEN_96___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_96__TX_DCOC_RES_Q_EVEN_96___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_96___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_96___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_97 (0x005E5984) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_97___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_97___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_97__TX_DCOC_RES_I_ODD_97___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_97__TX_DCOC_RES_Q_ODD_97___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_97__TX_DCOC_RES_I_EVEN_97___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_97__TX_DCOC_RES_Q_EVEN_97___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_97__TX_DCOC_RES_I_ODD_97___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_97__TX_DCOC_RES_I_ODD_97___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_97__TX_DCOC_RES_Q_ODD_97___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_97__TX_DCOC_RES_Q_ODD_97___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_97__TX_DCOC_RES_I_EVEN_97___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_97__TX_DCOC_RES_I_EVEN_97___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_97__TX_DCOC_RES_Q_EVEN_97___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_97__TX_DCOC_RES_Q_EVEN_97___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_97___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_97___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_98 (0x005E5988) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_98___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_98___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_98__TX_DCOC_RES_I_ODD_98___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_98__TX_DCOC_RES_Q_ODD_98___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_98__TX_DCOC_RES_I_EVEN_98___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_98__TX_DCOC_RES_Q_EVEN_98___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_98__TX_DCOC_RES_I_ODD_98___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_98__TX_DCOC_RES_I_ODD_98___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_98__TX_DCOC_RES_Q_ODD_98___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_98__TX_DCOC_RES_Q_ODD_98___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_98__TX_DCOC_RES_I_EVEN_98___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_98__TX_DCOC_RES_I_EVEN_98___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_98__TX_DCOC_RES_Q_EVEN_98___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_98__TX_DCOC_RES_Q_EVEN_98___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_98___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_98___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_99 (0x005E598C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_99___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_99___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_99__TX_DCOC_RES_I_ODD_99___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_99__TX_DCOC_RES_Q_ODD_99___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_99__TX_DCOC_RES_I_EVEN_99___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_99__TX_DCOC_RES_Q_EVEN_99___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_99__TX_DCOC_RES_I_ODD_99___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_99__TX_DCOC_RES_I_ODD_99___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_99__TX_DCOC_RES_Q_ODD_99___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_99__TX_DCOC_RES_Q_ODD_99___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_99__TX_DCOC_RES_I_EVEN_99___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_99__TX_DCOC_RES_I_EVEN_99___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_99__TX_DCOC_RES_Q_EVEN_99___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_99__TX_DCOC_RES_Q_EVEN_99___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_99___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_99___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_100 (0x005E5990) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_100___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_100___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_100__TX_DCOC_RES_I_ODD_100___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_100__TX_DCOC_RES_Q_ODD_100___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_100__TX_DCOC_RES_I_EVEN_100___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_100__TX_DCOC_RES_Q_EVEN_100___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_100__TX_DCOC_RES_I_ODD_100___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_100__TX_DCOC_RES_I_ODD_100___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_100__TX_DCOC_RES_Q_ODD_100___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_100__TX_DCOC_RES_Q_ODD_100___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_100__TX_DCOC_RES_I_EVEN_100___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_100__TX_DCOC_RES_I_EVEN_100___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_100__TX_DCOC_RES_Q_EVEN_100___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_100__TX_DCOC_RES_Q_EVEN_100___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_100___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_100___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_101 (0x005E5994) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_101___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_101___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_101__TX_DCOC_RES_I_ODD_101___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_101__TX_DCOC_RES_Q_ODD_101___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_101__TX_DCOC_RES_I_EVEN_101___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_101__TX_DCOC_RES_Q_EVEN_101___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_101__TX_DCOC_RES_I_ODD_101___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_101__TX_DCOC_RES_I_ODD_101___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_101__TX_DCOC_RES_Q_ODD_101___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_101__TX_DCOC_RES_Q_ODD_101___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_101__TX_DCOC_RES_I_EVEN_101___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_101__TX_DCOC_RES_I_EVEN_101___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_101__TX_DCOC_RES_Q_EVEN_101___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_101__TX_DCOC_RES_Q_EVEN_101___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_101___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_101___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_102 (0x005E5998) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_102___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_102___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_102__TX_DCOC_RES_I_ODD_102___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_102__TX_DCOC_RES_Q_ODD_102___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_102__TX_DCOC_RES_I_EVEN_102___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_102__TX_DCOC_RES_Q_EVEN_102___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_102__TX_DCOC_RES_I_ODD_102___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_102__TX_DCOC_RES_I_ODD_102___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_102__TX_DCOC_RES_Q_ODD_102___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_102__TX_DCOC_RES_Q_ODD_102___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_102__TX_DCOC_RES_I_EVEN_102___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_102__TX_DCOC_RES_I_EVEN_102___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_102__TX_DCOC_RES_Q_EVEN_102___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_102__TX_DCOC_RES_Q_EVEN_102___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_102___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_102___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_103 (0x005E599C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_103___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_103___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_103__TX_DCOC_RES_I_ODD_103___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_103__TX_DCOC_RES_Q_ODD_103___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_103__TX_DCOC_RES_I_EVEN_103___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_103__TX_DCOC_RES_Q_EVEN_103___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_103__TX_DCOC_RES_I_ODD_103___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_103__TX_DCOC_RES_I_ODD_103___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_103__TX_DCOC_RES_Q_ODD_103___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_103__TX_DCOC_RES_Q_ODD_103___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_103__TX_DCOC_RES_I_EVEN_103___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_103__TX_DCOC_RES_I_EVEN_103___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_103__TX_DCOC_RES_Q_EVEN_103___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_103__TX_DCOC_RES_Q_EVEN_103___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_103___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_103___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_104 (0x005E59A0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_104___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_104___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_104__TX_DCOC_RES_I_ODD_104___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_104__TX_DCOC_RES_Q_ODD_104___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_104__TX_DCOC_RES_I_EVEN_104___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_104__TX_DCOC_RES_Q_EVEN_104___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_104__TX_DCOC_RES_I_ODD_104___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_104__TX_DCOC_RES_I_ODD_104___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_104__TX_DCOC_RES_Q_ODD_104___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_104__TX_DCOC_RES_Q_ODD_104___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_104__TX_DCOC_RES_I_EVEN_104___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_104__TX_DCOC_RES_I_EVEN_104___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_104__TX_DCOC_RES_Q_EVEN_104___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_104__TX_DCOC_RES_Q_EVEN_104___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_104___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_104___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_105 (0x005E59A4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_105___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_105___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_105__TX_DCOC_RES_I_ODD_105___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_105__TX_DCOC_RES_Q_ODD_105___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_105__TX_DCOC_RES_I_EVEN_105___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_105__TX_DCOC_RES_Q_EVEN_105___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_105__TX_DCOC_RES_I_ODD_105___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_105__TX_DCOC_RES_I_ODD_105___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_105__TX_DCOC_RES_Q_ODD_105___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_105__TX_DCOC_RES_Q_ODD_105___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_105__TX_DCOC_RES_I_EVEN_105___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_105__TX_DCOC_RES_I_EVEN_105___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_105__TX_DCOC_RES_Q_EVEN_105___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_105__TX_DCOC_RES_Q_EVEN_105___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_105___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_105___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_106 (0x005E59A8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_106___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_106___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_106__TX_DCOC_RES_I_ODD_106___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_106__TX_DCOC_RES_Q_ODD_106___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_106__TX_DCOC_RES_I_EVEN_106___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_106__TX_DCOC_RES_Q_EVEN_106___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_106__TX_DCOC_RES_I_ODD_106___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_106__TX_DCOC_RES_I_ODD_106___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_106__TX_DCOC_RES_Q_ODD_106___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_106__TX_DCOC_RES_Q_ODD_106___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_106__TX_DCOC_RES_I_EVEN_106___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_106__TX_DCOC_RES_I_EVEN_106___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_106__TX_DCOC_RES_Q_EVEN_106___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_106__TX_DCOC_RES_Q_EVEN_106___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_106___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_106___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_107 (0x005E59AC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_107___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_107___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_107__TX_DCOC_RES_I_ODD_107___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_107__TX_DCOC_RES_Q_ODD_107___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_107__TX_DCOC_RES_I_EVEN_107___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_107__TX_DCOC_RES_Q_EVEN_107___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_107__TX_DCOC_RES_I_ODD_107___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_107__TX_DCOC_RES_I_ODD_107___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_107__TX_DCOC_RES_Q_ODD_107___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_107__TX_DCOC_RES_Q_ODD_107___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_107__TX_DCOC_RES_I_EVEN_107___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_107__TX_DCOC_RES_I_EVEN_107___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_107__TX_DCOC_RES_Q_EVEN_107___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_107__TX_DCOC_RES_Q_EVEN_107___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_107___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_107___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_108 (0x005E59B0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_108___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_108___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_108__TX_DCOC_RES_I_ODD_108___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_108__TX_DCOC_RES_Q_ODD_108___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_108__TX_DCOC_RES_I_EVEN_108___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_108__TX_DCOC_RES_Q_EVEN_108___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_108__TX_DCOC_RES_I_ODD_108___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_108__TX_DCOC_RES_I_ODD_108___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_108__TX_DCOC_RES_Q_ODD_108___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_108__TX_DCOC_RES_Q_ODD_108___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_108__TX_DCOC_RES_I_EVEN_108___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_108__TX_DCOC_RES_I_EVEN_108___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_108__TX_DCOC_RES_Q_EVEN_108___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_108__TX_DCOC_RES_Q_EVEN_108___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_108___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_108___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_109 (0x005E59B4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_109___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_109___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_109__TX_DCOC_RES_I_ODD_109___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_109__TX_DCOC_RES_Q_ODD_109___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_109__TX_DCOC_RES_I_EVEN_109___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_109__TX_DCOC_RES_Q_EVEN_109___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_109__TX_DCOC_RES_I_ODD_109___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_109__TX_DCOC_RES_I_ODD_109___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_109__TX_DCOC_RES_Q_ODD_109___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_109__TX_DCOC_RES_Q_ODD_109___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_109__TX_DCOC_RES_I_EVEN_109___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_109__TX_DCOC_RES_I_EVEN_109___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_109__TX_DCOC_RES_Q_EVEN_109___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_109__TX_DCOC_RES_Q_EVEN_109___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_109___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_109___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_110 (0x005E59B8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_110___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_110___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_110__TX_DCOC_RES_I_ODD_110___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_110__TX_DCOC_RES_Q_ODD_110___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_110__TX_DCOC_RES_I_EVEN_110___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_110__TX_DCOC_RES_Q_EVEN_110___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_110__TX_DCOC_RES_I_ODD_110___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_110__TX_DCOC_RES_I_ODD_110___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_110__TX_DCOC_RES_Q_ODD_110___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_110__TX_DCOC_RES_Q_ODD_110___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_110__TX_DCOC_RES_I_EVEN_110___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_110__TX_DCOC_RES_I_EVEN_110___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_110__TX_DCOC_RES_Q_EVEN_110___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_110__TX_DCOC_RES_Q_EVEN_110___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_110___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_110___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_111 (0x005E59BC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_111___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_111___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_111__TX_DCOC_RES_I_ODD_111___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_111__TX_DCOC_RES_Q_ODD_111___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_111__TX_DCOC_RES_I_EVEN_111___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_111__TX_DCOC_RES_Q_EVEN_111___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_111__TX_DCOC_RES_I_ODD_111___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_111__TX_DCOC_RES_I_ODD_111___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_111__TX_DCOC_RES_Q_ODD_111___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_111__TX_DCOC_RES_Q_ODD_111___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_111__TX_DCOC_RES_I_EVEN_111___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_111__TX_DCOC_RES_I_EVEN_111___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_111__TX_DCOC_RES_Q_EVEN_111___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_111__TX_DCOC_RES_Q_EVEN_111___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_111___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_111___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_112 (0x005E59C0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_112___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_112___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_112__TX_DCOC_RES_I_ODD_112___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_112__TX_DCOC_RES_Q_ODD_112___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_112__TX_DCOC_RES_I_EVEN_112___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_112__TX_DCOC_RES_Q_EVEN_112___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_112__TX_DCOC_RES_I_ODD_112___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_112__TX_DCOC_RES_I_ODD_112___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_112__TX_DCOC_RES_Q_ODD_112___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_112__TX_DCOC_RES_Q_ODD_112___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_112__TX_DCOC_RES_I_EVEN_112___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_112__TX_DCOC_RES_I_EVEN_112___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_112__TX_DCOC_RES_Q_EVEN_112___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_112__TX_DCOC_RES_Q_EVEN_112___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_112___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_112___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_113 (0x005E59C4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_113___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_113___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_113__TX_DCOC_RES_I_ODD_113___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_113__TX_DCOC_RES_Q_ODD_113___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_113__TX_DCOC_RES_I_EVEN_113___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_113__TX_DCOC_RES_Q_EVEN_113___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_113__TX_DCOC_RES_I_ODD_113___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_113__TX_DCOC_RES_I_ODD_113___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_113__TX_DCOC_RES_Q_ODD_113___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_113__TX_DCOC_RES_Q_ODD_113___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_113__TX_DCOC_RES_I_EVEN_113___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_113__TX_DCOC_RES_I_EVEN_113___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_113__TX_DCOC_RES_Q_EVEN_113___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_113__TX_DCOC_RES_Q_EVEN_113___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_113___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_113___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_114 (0x005E59C8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_114___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_114___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_114__TX_DCOC_RES_I_ODD_114___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_114__TX_DCOC_RES_Q_ODD_114___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_114__TX_DCOC_RES_I_EVEN_114___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_114__TX_DCOC_RES_Q_EVEN_114___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_114__TX_DCOC_RES_I_ODD_114___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_114__TX_DCOC_RES_I_ODD_114___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_114__TX_DCOC_RES_Q_ODD_114___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_114__TX_DCOC_RES_Q_ODD_114___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_114__TX_DCOC_RES_I_EVEN_114___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_114__TX_DCOC_RES_I_EVEN_114___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_114__TX_DCOC_RES_Q_EVEN_114___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_114__TX_DCOC_RES_Q_EVEN_114___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_114___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_114___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_115 (0x005E59CC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_115___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_115___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_115__TX_DCOC_RES_I_ODD_115___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_115__TX_DCOC_RES_Q_ODD_115___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_115__TX_DCOC_RES_I_EVEN_115___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_115__TX_DCOC_RES_Q_EVEN_115___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_115__TX_DCOC_RES_I_ODD_115___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_115__TX_DCOC_RES_I_ODD_115___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_115__TX_DCOC_RES_Q_ODD_115___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_115__TX_DCOC_RES_Q_ODD_115___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_115__TX_DCOC_RES_I_EVEN_115___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_115__TX_DCOC_RES_I_EVEN_115___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_115__TX_DCOC_RES_Q_EVEN_115___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_115__TX_DCOC_RES_Q_EVEN_115___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_115___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_115___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_116 (0x005E59D0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_116___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_116___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_116__TX_DCOC_RES_I_ODD_116___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_116__TX_DCOC_RES_Q_ODD_116___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_116__TX_DCOC_RES_I_EVEN_116___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_116__TX_DCOC_RES_Q_EVEN_116___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_116__TX_DCOC_RES_I_ODD_116___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_116__TX_DCOC_RES_I_ODD_116___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_116__TX_DCOC_RES_Q_ODD_116___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_116__TX_DCOC_RES_Q_ODD_116___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_116__TX_DCOC_RES_I_EVEN_116___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_116__TX_DCOC_RES_I_EVEN_116___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_116__TX_DCOC_RES_Q_EVEN_116___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_116__TX_DCOC_RES_Q_EVEN_116___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_116___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_116___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_117 (0x005E59D4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_117___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_117___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_117__TX_DCOC_RES_I_ODD_117___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_117__TX_DCOC_RES_Q_ODD_117___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_117__TX_DCOC_RES_I_EVEN_117___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_117__TX_DCOC_RES_Q_EVEN_117___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_117__TX_DCOC_RES_I_ODD_117___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_117__TX_DCOC_RES_I_ODD_117___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_117__TX_DCOC_RES_Q_ODD_117___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_117__TX_DCOC_RES_Q_ODD_117___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_117__TX_DCOC_RES_I_EVEN_117___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_117__TX_DCOC_RES_I_EVEN_117___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_117__TX_DCOC_RES_Q_EVEN_117___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_117__TX_DCOC_RES_Q_EVEN_117___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_117___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_117___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_118 (0x005E59D8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_118___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_118___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_118__TX_DCOC_RES_I_ODD_118___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_118__TX_DCOC_RES_Q_ODD_118___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_118__TX_DCOC_RES_I_EVEN_118___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_118__TX_DCOC_RES_Q_EVEN_118___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_118__TX_DCOC_RES_I_ODD_118___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_118__TX_DCOC_RES_I_ODD_118___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_118__TX_DCOC_RES_Q_ODD_118___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_118__TX_DCOC_RES_Q_ODD_118___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_118__TX_DCOC_RES_I_EVEN_118___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_118__TX_DCOC_RES_I_EVEN_118___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_118__TX_DCOC_RES_Q_EVEN_118___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_118__TX_DCOC_RES_Q_EVEN_118___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_118___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_118___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_119 (0x005E59DC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_119___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_119___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_119__TX_DCOC_RES_I_ODD_119___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_119__TX_DCOC_RES_Q_ODD_119___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_119__TX_DCOC_RES_I_EVEN_119___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_119__TX_DCOC_RES_Q_EVEN_119___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_119__TX_DCOC_RES_I_ODD_119___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_119__TX_DCOC_RES_I_ODD_119___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_119__TX_DCOC_RES_Q_ODD_119___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_119__TX_DCOC_RES_Q_ODD_119___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_119__TX_DCOC_RES_I_EVEN_119___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_119__TX_DCOC_RES_I_EVEN_119___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_119__TX_DCOC_RES_Q_EVEN_119___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_119__TX_DCOC_RES_Q_EVEN_119___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_119___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_119___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_120 (0x005E59E0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_120___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_120___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_120__TX_DCOC_RES_I_ODD_120___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_120__TX_DCOC_RES_Q_ODD_120___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_120__TX_DCOC_RES_I_EVEN_120___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_120__TX_DCOC_RES_Q_EVEN_120___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_120__TX_DCOC_RES_I_ODD_120___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_120__TX_DCOC_RES_I_ODD_120___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_120__TX_DCOC_RES_Q_ODD_120___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_120__TX_DCOC_RES_Q_ODD_120___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_120__TX_DCOC_RES_I_EVEN_120___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_120__TX_DCOC_RES_I_EVEN_120___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_120__TX_DCOC_RES_Q_EVEN_120___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_120__TX_DCOC_RES_Q_EVEN_120___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_120___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_120___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_121 (0x005E59E4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_121___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_121___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_121__TX_DCOC_RES_I_ODD_121___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_121__TX_DCOC_RES_Q_ODD_121___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_121__TX_DCOC_RES_I_EVEN_121___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_121__TX_DCOC_RES_Q_EVEN_121___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_121__TX_DCOC_RES_I_ODD_121___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_121__TX_DCOC_RES_I_ODD_121___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_121__TX_DCOC_RES_Q_ODD_121___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_121__TX_DCOC_RES_Q_ODD_121___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_121__TX_DCOC_RES_I_EVEN_121___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_121__TX_DCOC_RES_I_EVEN_121___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_121__TX_DCOC_RES_Q_EVEN_121___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_121__TX_DCOC_RES_Q_EVEN_121___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_121___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_121___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_122 (0x005E59E8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_122___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_122___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_122__TX_DCOC_RES_I_ODD_122___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_122__TX_DCOC_RES_Q_ODD_122___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_122__TX_DCOC_RES_I_EVEN_122___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_122__TX_DCOC_RES_Q_EVEN_122___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_122__TX_DCOC_RES_I_ODD_122___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_122__TX_DCOC_RES_I_ODD_122___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_122__TX_DCOC_RES_Q_ODD_122___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_122__TX_DCOC_RES_Q_ODD_122___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_122__TX_DCOC_RES_I_EVEN_122___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_122__TX_DCOC_RES_I_EVEN_122___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_122__TX_DCOC_RES_Q_EVEN_122___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_122__TX_DCOC_RES_Q_EVEN_122___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_122___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_122___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_123 (0x005E59EC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_123___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_123___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_123__TX_DCOC_RES_I_ODD_123___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_123__TX_DCOC_RES_Q_ODD_123___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_123__TX_DCOC_RES_I_EVEN_123___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_123__TX_DCOC_RES_Q_EVEN_123___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_123__TX_DCOC_RES_I_ODD_123___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_123__TX_DCOC_RES_I_ODD_123___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_123__TX_DCOC_RES_Q_ODD_123___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_123__TX_DCOC_RES_Q_ODD_123___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_123__TX_DCOC_RES_I_EVEN_123___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_123__TX_DCOC_RES_I_EVEN_123___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_123__TX_DCOC_RES_Q_EVEN_123___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_123__TX_DCOC_RES_Q_EVEN_123___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_123___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_123___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_124 (0x005E59F0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_124___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_124___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_124__TX_DCOC_RES_I_ODD_124___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_124__TX_DCOC_RES_Q_ODD_124___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_124__TX_DCOC_RES_I_EVEN_124___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_124__TX_DCOC_RES_Q_EVEN_124___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_124__TX_DCOC_RES_I_ODD_124___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_124__TX_DCOC_RES_I_ODD_124___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_124__TX_DCOC_RES_Q_ODD_124___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_124__TX_DCOC_RES_Q_ODD_124___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_124__TX_DCOC_RES_I_EVEN_124___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_124__TX_DCOC_RES_I_EVEN_124___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_124__TX_DCOC_RES_Q_EVEN_124___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_124__TX_DCOC_RES_Q_EVEN_124___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_124___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_124___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_125 (0x005E59F4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_125___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_125___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_125__TX_DCOC_RES_I_ODD_125___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_125__TX_DCOC_RES_Q_ODD_125___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_125__TX_DCOC_RES_I_EVEN_125___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_125__TX_DCOC_RES_Q_EVEN_125___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_125__TX_DCOC_RES_I_ODD_125___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_125__TX_DCOC_RES_I_ODD_125___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_125__TX_DCOC_RES_Q_ODD_125___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_125__TX_DCOC_RES_Q_ODD_125___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_125__TX_DCOC_RES_I_EVEN_125___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_125__TX_DCOC_RES_I_EVEN_125___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_125__TX_DCOC_RES_Q_EVEN_125___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_125__TX_DCOC_RES_Q_EVEN_125___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_125___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_125___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_126 (0x005E59F8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_126___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_126___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_126__TX_DCOC_RES_I_ODD_126___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_126__TX_DCOC_RES_Q_ODD_126___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_126__TX_DCOC_RES_I_EVEN_126___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_126__TX_DCOC_RES_Q_EVEN_126___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_126__TX_DCOC_RES_I_ODD_126___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_126__TX_DCOC_RES_I_ODD_126___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_126__TX_DCOC_RES_Q_ODD_126___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_126__TX_DCOC_RES_Q_ODD_126___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_126__TX_DCOC_RES_I_EVEN_126___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_126__TX_DCOC_RES_I_EVEN_126___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_126__TX_DCOC_RES_Q_EVEN_126___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_126__TX_DCOC_RES_Q_EVEN_126___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_126___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_126___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_127 (0x005E59FC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_127___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_127___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_127__TX_DCOC_RES_I_ODD_127___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_127__TX_DCOC_RES_Q_ODD_127___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_127__TX_DCOC_RES_I_EVEN_127___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_127__TX_DCOC_RES_Q_EVEN_127___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_127__TX_DCOC_RES_I_ODD_127___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_127__TX_DCOC_RES_I_ODD_127___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_127__TX_DCOC_RES_Q_ODD_127___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_127__TX_DCOC_RES_Q_ODD_127___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_127__TX_DCOC_RES_I_EVEN_127___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_127__TX_DCOC_RES_I_EVEN_127___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_127__TX_DCOC_RES_Q_EVEN_127___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_127__TX_DCOC_RES_Q_EVEN_127___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_127___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXDCOC_127___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0 (0x005E5C00) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__IPA_GAIN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__DAC_GAIN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__TX_PWR_LV_LAA_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__TX_PWR_LV_N79_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__BBF_GAIN_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__UPC_GAIN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__DA_GAIN_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__XPA_GAIN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__IPA_GAIN_0___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__IPA_GAIN_0___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__DAC_GAIN_0___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__DAC_GAIN_0___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__TX_PWR_LV_LAA_0___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__TX_PWR_LV_LAA_0___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__TX_PWR_LV_N79_0___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__TX_PWR_LV_N79_0___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__BBF_GAIN_0___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__BBF_GAIN_0___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__UPC_GAIN_0___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__UPC_GAIN_0___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__DA_GAIN_0___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__DA_GAIN_0___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__XPA_GAIN_0___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0__XPA_GAIN_0___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1 (0x005E5C04) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__IPA_GAIN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__DAC_GAIN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__TX_PWR_LV_LAA_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__TX_PWR_LV_N79_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__BBF_GAIN_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__UPC_GAIN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__DA_GAIN_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__XPA_GAIN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__IPA_GAIN_1___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__IPA_GAIN_1___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__DAC_GAIN_1___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__DAC_GAIN_1___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__TX_PWR_LV_LAA_1___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__TX_PWR_LV_LAA_1___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__TX_PWR_LV_N79_1___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__TX_PWR_LV_N79_1___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__BBF_GAIN_1___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__BBF_GAIN_1___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__UPC_GAIN_1___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__UPC_GAIN_1___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__DA_GAIN_1___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__DA_GAIN_1___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__XPA_GAIN_1___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1__XPA_GAIN_1___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2 (0x005E5C08) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__IPA_GAIN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__DAC_GAIN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__TX_PWR_LV_LAA_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__TX_PWR_LV_N79_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__BBF_GAIN_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__UPC_GAIN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__DA_GAIN_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__XPA_GAIN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__IPA_GAIN_2___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__IPA_GAIN_2___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__DAC_GAIN_2___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__DAC_GAIN_2___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__TX_PWR_LV_LAA_2___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__TX_PWR_LV_LAA_2___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__TX_PWR_LV_N79_2___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__TX_PWR_LV_N79_2___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__BBF_GAIN_2___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__BBF_GAIN_2___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__UPC_GAIN_2___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__UPC_GAIN_2___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__DA_GAIN_2___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__DA_GAIN_2___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__XPA_GAIN_2___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2__XPA_GAIN_2___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_2___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3 (0x005E5C0C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__IPA_GAIN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__DAC_GAIN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__TX_PWR_LV_LAA_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__TX_PWR_LV_N79_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__BBF_GAIN_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__UPC_GAIN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__DA_GAIN_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__XPA_GAIN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__IPA_GAIN_3___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__IPA_GAIN_3___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__DAC_GAIN_3___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__DAC_GAIN_3___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__TX_PWR_LV_LAA_3___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__TX_PWR_LV_LAA_3___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__TX_PWR_LV_N79_3___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__TX_PWR_LV_N79_3___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__BBF_GAIN_3___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__BBF_GAIN_3___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__UPC_GAIN_3___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__UPC_GAIN_3___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__DA_GAIN_3___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__DA_GAIN_3___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__XPA_GAIN_3___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3__XPA_GAIN_3___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_3___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4 (0x005E5C10) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__IPA_GAIN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__DAC_GAIN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__TX_PWR_LV_LAA_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__TX_PWR_LV_N79_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__BBF_GAIN_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__UPC_GAIN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__DA_GAIN_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__XPA_GAIN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__IPA_GAIN_4___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__IPA_GAIN_4___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__DAC_GAIN_4___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__DAC_GAIN_4___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__TX_PWR_LV_LAA_4___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__TX_PWR_LV_LAA_4___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__TX_PWR_LV_N79_4___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__TX_PWR_LV_N79_4___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__BBF_GAIN_4___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__BBF_GAIN_4___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__UPC_GAIN_4___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__UPC_GAIN_4___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__DA_GAIN_4___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__DA_GAIN_4___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__XPA_GAIN_4___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4__XPA_GAIN_4___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_4___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5 (0x005E5C14) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__IPA_GAIN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__DAC_GAIN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__TX_PWR_LV_LAA_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__TX_PWR_LV_N79_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__BBF_GAIN_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__UPC_GAIN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__DA_GAIN_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__XPA_GAIN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__IPA_GAIN_5___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__IPA_GAIN_5___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__DAC_GAIN_5___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__DAC_GAIN_5___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__TX_PWR_LV_LAA_5___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__TX_PWR_LV_LAA_5___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__TX_PWR_LV_N79_5___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__TX_PWR_LV_N79_5___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__BBF_GAIN_5___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__BBF_GAIN_5___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__UPC_GAIN_5___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__UPC_GAIN_5___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__DA_GAIN_5___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__DA_GAIN_5___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__XPA_GAIN_5___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5__XPA_GAIN_5___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_5___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6 (0x005E5C18) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__IPA_GAIN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__DAC_GAIN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__TX_PWR_LV_LAA_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__TX_PWR_LV_N79_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__BBF_GAIN_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__UPC_GAIN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__DA_GAIN_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__XPA_GAIN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__IPA_GAIN_6___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__IPA_GAIN_6___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__DAC_GAIN_6___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__DAC_GAIN_6___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__TX_PWR_LV_LAA_6___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__TX_PWR_LV_LAA_6___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__TX_PWR_LV_N79_6___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__TX_PWR_LV_N79_6___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__BBF_GAIN_6___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__BBF_GAIN_6___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__UPC_GAIN_6___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__UPC_GAIN_6___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__DA_GAIN_6___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__DA_GAIN_6___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__XPA_GAIN_6___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6__XPA_GAIN_6___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_6___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7 (0x005E5C1C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__IPA_GAIN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__DAC_GAIN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__TX_PWR_LV_LAA_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__TX_PWR_LV_N79_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__BBF_GAIN_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__UPC_GAIN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__DA_GAIN_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__XPA_GAIN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__IPA_GAIN_7___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__IPA_GAIN_7___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__DAC_GAIN_7___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__DAC_GAIN_7___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__TX_PWR_LV_LAA_7___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__TX_PWR_LV_LAA_7___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__TX_PWR_LV_N79_7___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__TX_PWR_LV_N79_7___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__BBF_GAIN_7___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__BBF_GAIN_7___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__UPC_GAIN_7___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__UPC_GAIN_7___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__DA_GAIN_7___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__DA_GAIN_7___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__XPA_GAIN_7___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7__XPA_GAIN_7___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_7___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8 (0x005E5C20) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__IPA_GAIN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__DAC_GAIN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__TX_PWR_LV_LAA_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__TX_PWR_LV_N79_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__BBF_GAIN_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__UPC_GAIN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__DA_GAIN_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__XPA_GAIN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__IPA_GAIN_8___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__IPA_GAIN_8___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__DAC_GAIN_8___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__DAC_GAIN_8___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__TX_PWR_LV_LAA_8___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__TX_PWR_LV_LAA_8___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__TX_PWR_LV_N79_8___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__TX_PWR_LV_N79_8___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__BBF_GAIN_8___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__BBF_GAIN_8___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__UPC_GAIN_8___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__UPC_GAIN_8___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__DA_GAIN_8___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__DA_GAIN_8___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__XPA_GAIN_8___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8__XPA_GAIN_8___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_8___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9 (0x005E5C24) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__IPA_GAIN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__DAC_GAIN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__TX_PWR_LV_LAA_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__TX_PWR_LV_N79_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__BBF_GAIN_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__UPC_GAIN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__DA_GAIN_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__XPA_GAIN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__IPA_GAIN_9___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__IPA_GAIN_9___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__DAC_GAIN_9___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__DAC_GAIN_9___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__TX_PWR_LV_LAA_9___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__TX_PWR_LV_LAA_9___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__TX_PWR_LV_N79_9___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__TX_PWR_LV_N79_9___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__BBF_GAIN_9___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__BBF_GAIN_9___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__UPC_GAIN_9___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__UPC_GAIN_9___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__DA_GAIN_9___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__DA_GAIN_9___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__XPA_GAIN_9___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9__XPA_GAIN_9___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_9___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10 (0x005E5C28) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__IPA_GAIN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__DAC_GAIN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__TX_PWR_LV_LAA_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__TX_PWR_LV_N79_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__BBF_GAIN_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__UPC_GAIN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__DA_GAIN_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__XPA_GAIN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__IPA_GAIN_10___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__IPA_GAIN_10___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__DAC_GAIN_10___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__DAC_GAIN_10___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__TX_PWR_LV_LAA_10___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__TX_PWR_LV_LAA_10___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__TX_PWR_LV_N79_10___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__TX_PWR_LV_N79_10___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__BBF_GAIN_10___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__BBF_GAIN_10___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__UPC_GAIN_10___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__UPC_GAIN_10___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__DA_GAIN_10___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__DA_GAIN_10___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__XPA_GAIN_10___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10__XPA_GAIN_10___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_10___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11 (0x005E5C2C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__IPA_GAIN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__DAC_GAIN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__TX_PWR_LV_LAA_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__TX_PWR_LV_N79_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__BBF_GAIN_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__UPC_GAIN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__DA_GAIN_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__XPA_GAIN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__IPA_GAIN_11___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__IPA_GAIN_11___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__DAC_GAIN_11___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__DAC_GAIN_11___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__TX_PWR_LV_LAA_11___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__TX_PWR_LV_LAA_11___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__TX_PWR_LV_N79_11___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__TX_PWR_LV_N79_11___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__BBF_GAIN_11___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__BBF_GAIN_11___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__UPC_GAIN_11___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__UPC_GAIN_11___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__DA_GAIN_11___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__DA_GAIN_11___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__XPA_GAIN_11___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11__XPA_GAIN_11___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_11___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12 (0x005E5C30) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__IPA_GAIN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__DAC_GAIN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__TX_PWR_LV_LAA_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__TX_PWR_LV_N79_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__BBF_GAIN_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__UPC_GAIN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__DA_GAIN_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__XPA_GAIN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__IPA_GAIN_12___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__IPA_GAIN_12___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__DAC_GAIN_12___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__DAC_GAIN_12___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__TX_PWR_LV_LAA_12___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__TX_PWR_LV_LAA_12___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__TX_PWR_LV_N79_12___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__TX_PWR_LV_N79_12___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__BBF_GAIN_12___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__BBF_GAIN_12___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__UPC_GAIN_12___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__UPC_GAIN_12___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__DA_GAIN_12___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__DA_GAIN_12___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__XPA_GAIN_12___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12__XPA_GAIN_12___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_12___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13 (0x005E5C34) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__IPA_GAIN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__DAC_GAIN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__TX_PWR_LV_LAA_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__TX_PWR_LV_N79_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__BBF_GAIN_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__UPC_GAIN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__DA_GAIN_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__XPA_GAIN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__IPA_GAIN_13___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__IPA_GAIN_13___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__DAC_GAIN_13___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__DAC_GAIN_13___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__TX_PWR_LV_LAA_13___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__TX_PWR_LV_LAA_13___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__TX_PWR_LV_N79_13___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__TX_PWR_LV_N79_13___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__BBF_GAIN_13___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__BBF_GAIN_13___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__UPC_GAIN_13___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__UPC_GAIN_13___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__DA_GAIN_13___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__DA_GAIN_13___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__XPA_GAIN_13___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13__XPA_GAIN_13___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_13___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14 (0x005E5C38) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__IPA_GAIN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__DAC_GAIN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__TX_PWR_LV_LAA_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__TX_PWR_LV_N79_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__BBF_GAIN_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__UPC_GAIN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__DA_GAIN_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__XPA_GAIN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__IPA_GAIN_14___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__IPA_GAIN_14___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__DAC_GAIN_14___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__DAC_GAIN_14___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__TX_PWR_LV_LAA_14___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__TX_PWR_LV_LAA_14___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__TX_PWR_LV_N79_14___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__TX_PWR_LV_N79_14___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__BBF_GAIN_14___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__BBF_GAIN_14___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__UPC_GAIN_14___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__UPC_GAIN_14___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__DA_GAIN_14___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__DA_GAIN_14___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__XPA_GAIN_14___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14__XPA_GAIN_14___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_14___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15 (0x005E5C3C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__IPA_GAIN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__DAC_GAIN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__TX_PWR_LV_LAA_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__TX_PWR_LV_N79_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__BBF_GAIN_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__UPC_GAIN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__DA_GAIN_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__XPA_GAIN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__IPA_GAIN_15___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__IPA_GAIN_15___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__DAC_GAIN_15___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__DAC_GAIN_15___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__TX_PWR_LV_LAA_15___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__TX_PWR_LV_LAA_15___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__TX_PWR_LV_N79_15___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__TX_PWR_LV_N79_15___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__BBF_GAIN_15___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__BBF_GAIN_15___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__UPC_GAIN_15___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__UPC_GAIN_15___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__DA_GAIN_15___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__DA_GAIN_15___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__XPA_GAIN_15___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15__XPA_GAIN_15___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_15___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16 (0x005E5C40) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__IPA_GAIN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__DAC_GAIN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__TX_PWR_LV_LAA_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__TX_PWR_LV_N79_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__BBF_GAIN_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__UPC_GAIN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__DA_GAIN_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__XPA_GAIN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__IPA_GAIN_16___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__IPA_GAIN_16___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__DAC_GAIN_16___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__DAC_GAIN_16___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__TX_PWR_LV_LAA_16___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__TX_PWR_LV_LAA_16___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__TX_PWR_LV_N79_16___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__TX_PWR_LV_N79_16___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__BBF_GAIN_16___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__BBF_GAIN_16___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__UPC_GAIN_16___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__UPC_GAIN_16___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__DA_GAIN_16___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__DA_GAIN_16___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__XPA_GAIN_16___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16__XPA_GAIN_16___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_16___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17 (0x005E5C44) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__IPA_GAIN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__DAC_GAIN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__TX_PWR_LV_LAA_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__TX_PWR_LV_N79_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__BBF_GAIN_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__UPC_GAIN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__DA_GAIN_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__XPA_GAIN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__IPA_GAIN_17___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__IPA_GAIN_17___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__DAC_GAIN_17___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__DAC_GAIN_17___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__TX_PWR_LV_LAA_17___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__TX_PWR_LV_LAA_17___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__TX_PWR_LV_N79_17___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__TX_PWR_LV_N79_17___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__BBF_GAIN_17___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__BBF_GAIN_17___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__UPC_GAIN_17___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__UPC_GAIN_17___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__DA_GAIN_17___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__DA_GAIN_17___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__XPA_GAIN_17___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17__XPA_GAIN_17___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_17___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18 (0x005E5C48) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__IPA_GAIN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__DAC_GAIN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__TX_PWR_LV_LAA_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__TX_PWR_LV_N79_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__BBF_GAIN_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__UPC_GAIN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__DA_GAIN_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__XPA_GAIN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__IPA_GAIN_18___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__IPA_GAIN_18___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__DAC_GAIN_18___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__DAC_GAIN_18___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__TX_PWR_LV_LAA_18___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__TX_PWR_LV_LAA_18___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__TX_PWR_LV_N79_18___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__TX_PWR_LV_N79_18___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__BBF_GAIN_18___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__BBF_GAIN_18___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__UPC_GAIN_18___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__UPC_GAIN_18___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__DA_GAIN_18___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__DA_GAIN_18___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__XPA_GAIN_18___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18__XPA_GAIN_18___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_18___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19 (0x005E5C4C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__IPA_GAIN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__DAC_GAIN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__TX_PWR_LV_LAA_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__TX_PWR_LV_N79_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__BBF_GAIN_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__UPC_GAIN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__DA_GAIN_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__XPA_GAIN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__IPA_GAIN_19___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__IPA_GAIN_19___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__DAC_GAIN_19___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__DAC_GAIN_19___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__TX_PWR_LV_LAA_19___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__TX_PWR_LV_LAA_19___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__TX_PWR_LV_N79_19___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__TX_PWR_LV_N79_19___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__BBF_GAIN_19___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__BBF_GAIN_19___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__UPC_GAIN_19___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__UPC_GAIN_19___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__DA_GAIN_19___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__DA_GAIN_19___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__XPA_GAIN_19___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19__XPA_GAIN_19___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_19___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20 (0x005E5C50) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__IPA_GAIN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__DAC_GAIN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__TX_PWR_LV_LAA_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__TX_PWR_LV_N79_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__BBF_GAIN_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__UPC_GAIN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__DA_GAIN_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__XPA_GAIN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__IPA_GAIN_20___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__IPA_GAIN_20___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__DAC_GAIN_20___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__DAC_GAIN_20___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__TX_PWR_LV_LAA_20___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__TX_PWR_LV_LAA_20___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__TX_PWR_LV_N79_20___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__TX_PWR_LV_N79_20___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__BBF_GAIN_20___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__BBF_GAIN_20___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__UPC_GAIN_20___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__UPC_GAIN_20___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__DA_GAIN_20___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__DA_GAIN_20___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__XPA_GAIN_20___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20__XPA_GAIN_20___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_20___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21 (0x005E5C54) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__IPA_GAIN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__DAC_GAIN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__TX_PWR_LV_LAA_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__TX_PWR_LV_N79_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__BBF_GAIN_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__UPC_GAIN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__DA_GAIN_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__XPA_GAIN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__IPA_GAIN_21___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__IPA_GAIN_21___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__DAC_GAIN_21___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__DAC_GAIN_21___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__TX_PWR_LV_LAA_21___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__TX_PWR_LV_LAA_21___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__TX_PWR_LV_N79_21___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__TX_PWR_LV_N79_21___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__BBF_GAIN_21___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__BBF_GAIN_21___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__UPC_GAIN_21___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__UPC_GAIN_21___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__DA_GAIN_21___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__DA_GAIN_21___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__XPA_GAIN_21___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21__XPA_GAIN_21___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_21___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22 (0x005E5C58) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__IPA_GAIN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__DAC_GAIN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__TX_PWR_LV_LAA_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__TX_PWR_LV_N79_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__BBF_GAIN_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__UPC_GAIN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__DA_GAIN_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__XPA_GAIN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__IPA_GAIN_22___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__IPA_GAIN_22___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__DAC_GAIN_22___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__DAC_GAIN_22___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__TX_PWR_LV_LAA_22___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__TX_PWR_LV_LAA_22___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__TX_PWR_LV_N79_22___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__TX_PWR_LV_N79_22___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__BBF_GAIN_22___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__BBF_GAIN_22___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__UPC_GAIN_22___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__UPC_GAIN_22___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__DA_GAIN_22___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__DA_GAIN_22___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__XPA_GAIN_22___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22__XPA_GAIN_22___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_22___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23 (0x005E5C5C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__IPA_GAIN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__DAC_GAIN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__TX_PWR_LV_LAA_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__TX_PWR_LV_N79_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__BBF_GAIN_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__UPC_GAIN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__DA_GAIN_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__XPA_GAIN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__IPA_GAIN_23___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__IPA_GAIN_23___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__DAC_GAIN_23___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__DAC_GAIN_23___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__TX_PWR_LV_LAA_23___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__TX_PWR_LV_LAA_23___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__TX_PWR_LV_N79_23___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__TX_PWR_LV_N79_23___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__BBF_GAIN_23___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__BBF_GAIN_23___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__UPC_GAIN_23___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__UPC_GAIN_23___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__DA_GAIN_23___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__DA_GAIN_23___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__XPA_GAIN_23___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23__XPA_GAIN_23___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_23___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24 (0x005E5C60) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__IPA_GAIN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__DAC_GAIN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__TX_PWR_LV_LAA_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__TX_PWR_LV_N79_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__BBF_GAIN_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__UPC_GAIN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__DA_GAIN_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__XPA_GAIN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__IPA_GAIN_24___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__IPA_GAIN_24___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__DAC_GAIN_24___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__DAC_GAIN_24___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__TX_PWR_LV_LAA_24___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__TX_PWR_LV_LAA_24___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__TX_PWR_LV_N79_24___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__TX_PWR_LV_N79_24___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__BBF_GAIN_24___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__BBF_GAIN_24___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__UPC_GAIN_24___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__UPC_GAIN_24___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__DA_GAIN_24___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__DA_GAIN_24___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__XPA_GAIN_24___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24__XPA_GAIN_24___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_24___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25 (0x005E5C64) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__IPA_GAIN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__DAC_GAIN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__TX_PWR_LV_LAA_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__TX_PWR_LV_N79_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__BBF_GAIN_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__UPC_GAIN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__DA_GAIN_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__XPA_GAIN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__IPA_GAIN_25___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__IPA_GAIN_25___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__DAC_GAIN_25___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__DAC_GAIN_25___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__TX_PWR_LV_LAA_25___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__TX_PWR_LV_LAA_25___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__TX_PWR_LV_N79_25___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__TX_PWR_LV_N79_25___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__BBF_GAIN_25___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__BBF_GAIN_25___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__UPC_GAIN_25___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__UPC_GAIN_25___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__DA_GAIN_25___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__DA_GAIN_25___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__XPA_GAIN_25___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25__XPA_GAIN_25___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_25___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26 (0x005E5C68) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__IPA_GAIN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__DAC_GAIN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__TX_PWR_LV_LAA_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__TX_PWR_LV_N79_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__BBF_GAIN_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__UPC_GAIN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__DA_GAIN_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__XPA_GAIN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__IPA_GAIN_26___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__IPA_GAIN_26___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__DAC_GAIN_26___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__DAC_GAIN_26___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__TX_PWR_LV_LAA_26___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__TX_PWR_LV_LAA_26___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__TX_PWR_LV_N79_26___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__TX_PWR_LV_N79_26___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__BBF_GAIN_26___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__BBF_GAIN_26___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__UPC_GAIN_26___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__UPC_GAIN_26___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__DA_GAIN_26___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__DA_GAIN_26___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__XPA_GAIN_26___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26__XPA_GAIN_26___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_26___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27 (0x005E5C6C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__IPA_GAIN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__DAC_GAIN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__TX_PWR_LV_LAA_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__TX_PWR_LV_N79_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__BBF_GAIN_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__UPC_GAIN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__DA_GAIN_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__XPA_GAIN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__IPA_GAIN_27___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__IPA_GAIN_27___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__DAC_GAIN_27___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__DAC_GAIN_27___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__TX_PWR_LV_LAA_27___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__TX_PWR_LV_LAA_27___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__TX_PWR_LV_N79_27___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__TX_PWR_LV_N79_27___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__BBF_GAIN_27___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__BBF_GAIN_27___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__UPC_GAIN_27___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__UPC_GAIN_27___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__DA_GAIN_27___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__DA_GAIN_27___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__XPA_GAIN_27___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27__XPA_GAIN_27___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_27___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28 (0x005E5C70) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__IPA_GAIN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__DAC_GAIN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__TX_PWR_LV_LAA_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__TX_PWR_LV_N79_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__BBF_GAIN_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__UPC_GAIN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__DA_GAIN_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__XPA_GAIN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__IPA_GAIN_28___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__IPA_GAIN_28___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__DAC_GAIN_28___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__DAC_GAIN_28___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__TX_PWR_LV_LAA_28___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__TX_PWR_LV_LAA_28___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__TX_PWR_LV_N79_28___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__TX_PWR_LV_N79_28___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__BBF_GAIN_28___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__BBF_GAIN_28___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__UPC_GAIN_28___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__UPC_GAIN_28___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__DA_GAIN_28___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__DA_GAIN_28___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__XPA_GAIN_28___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28__XPA_GAIN_28___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_28___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29 (0x005E5C74) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__IPA_GAIN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__DAC_GAIN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__TX_PWR_LV_LAA_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__TX_PWR_LV_N79_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__BBF_GAIN_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__UPC_GAIN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__DA_GAIN_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__XPA_GAIN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__IPA_GAIN_29___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__IPA_GAIN_29___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__DAC_GAIN_29___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__DAC_GAIN_29___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__TX_PWR_LV_LAA_29___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__TX_PWR_LV_LAA_29___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__TX_PWR_LV_N79_29___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__TX_PWR_LV_N79_29___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__BBF_GAIN_29___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__BBF_GAIN_29___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__UPC_GAIN_29___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__UPC_GAIN_29___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__DA_GAIN_29___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__DA_GAIN_29___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__XPA_GAIN_29___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29__XPA_GAIN_29___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_29___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30 (0x005E5C78) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__IPA_GAIN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__DAC_GAIN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__TX_PWR_LV_LAA_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__TX_PWR_LV_N79_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__BBF_GAIN_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__UPC_GAIN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__DA_GAIN_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__XPA_GAIN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__IPA_GAIN_30___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__IPA_GAIN_30___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__DAC_GAIN_30___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__DAC_GAIN_30___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__TX_PWR_LV_LAA_30___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__TX_PWR_LV_LAA_30___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__TX_PWR_LV_N79_30___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__TX_PWR_LV_N79_30___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__BBF_GAIN_30___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__BBF_GAIN_30___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__UPC_GAIN_30___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__UPC_GAIN_30___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__DA_GAIN_30___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__DA_GAIN_30___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__XPA_GAIN_30___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30__XPA_GAIN_30___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_30___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31 (0x005E5C7C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__IPA_GAIN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__DAC_GAIN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__TX_PWR_LV_LAA_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__TX_PWR_LV_N79_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__BBF_GAIN_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__UPC_GAIN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__DA_GAIN_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__XPA_GAIN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__IPA_GAIN_31___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__IPA_GAIN_31___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__DAC_GAIN_31___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__DAC_GAIN_31___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__TX_PWR_LV_LAA_31___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__TX_PWR_LV_LAA_31___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__TX_PWR_LV_N79_31___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__TX_PWR_LV_N79_31___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__BBF_GAIN_31___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__BBF_GAIN_31___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__UPC_GAIN_31___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__UPC_GAIN_31___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__DA_GAIN_31___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__DA_GAIN_31___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__XPA_GAIN_31___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31__XPA_GAIN_31___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_31___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32 (0x005E5C80) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__IPA_GAIN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__DAC_GAIN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__TX_PWR_LV_LAA_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__TX_PWR_LV_N79_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__BBF_GAIN_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__UPC_GAIN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__DA_GAIN_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__XPA_GAIN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__IPA_GAIN_32___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__IPA_GAIN_32___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__DAC_GAIN_32___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__DAC_GAIN_32___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__TX_PWR_LV_LAA_32___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__TX_PWR_LV_LAA_32___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__TX_PWR_LV_N79_32___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__TX_PWR_LV_N79_32___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__BBF_GAIN_32___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__BBF_GAIN_32___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__UPC_GAIN_32___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__UPC_GAIN_32___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__DA_GAIN_32___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__DA_GAIN_32___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__XPA_GAIN_32___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32__XPA_GAIN_32___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_32___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33 (0x005E5C84) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__IPA_GAIN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__DAC_GAIN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__TX_PWR_LV_LAA_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__TX_PWR_LV_N79_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__BBF_GAIN_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__UPC_GAIN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__DA_GAIN_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__XPA_GAIN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__IPA_GAIN_33___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__IPA_GAIN_33___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__DAC_GAIN_33___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__DAC_GAIN_33___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__TX_PWR_LV_LAA_33___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__TX_PWR_LV_LAA_33___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__TX_PWR_LV_N79_33___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__TX_PWR_LV_N79_33___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__BBF_GAIN_33___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__BBF_GAIN_33___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__UPC_GAIN_33___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__UPC_GAIN_33___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__DA_GAIN_33___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__DA_GAIN_33___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__XPA_GAIN_33___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33__XPA_GAIN_33___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_33___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34 (0x005E5C88) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__IPA_GAIN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__DAC_GAIN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__TX_PWR_LV_LAA_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__TX_PWR_LV_N79_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__BBF_GAIN_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__UPC_GAIN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__DA_GAIN_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__XPA_GAIN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__IPA_GAIN_34___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__IPA_GAIN_34___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__DAC_GAIN_34___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__DAC_GAIN_34___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__TX_PWR_LV_LAA_34___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__TX_PWR_LV_LAA_34___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__TX_PWR_LV_N79_34___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__TX_PWR_LV_N79_34___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__BBF_GAIN_34___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__BBF_GAIN_34___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__UPC_GAIN_34___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__UPC_GAIN_34___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__DA_GAIN_34___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__DA_GAIN_34___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__XPA_GAIN_34___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34__XPA_GAIN_34___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_34___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35 (0x005E5C8C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__IPA_GAIN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__DAC_GAIN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__TX_PWR_LV_LAA_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__TX_PWR_LV_N79_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__BBF_GAIN_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__UPC_GAIN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__DA_GAIN_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__XPA_GAIN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__IPA_GAIN_35___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__IPA_GAIN_35___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__DAC_GAIN_35___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__DAC_GAIN_35___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__TX_PWR_LV_LAA_35___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__TX_PWR_LV_LAA_35___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__TX_PWR_LV_N79_35___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__TX_PWR_LV_N79_35___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__BBF_GAIN_35___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__BBF_GAIN_35___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__UPC_GAIN_35___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__UPC_GAIN_35___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__DA_GAIN_35___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__DA_GAIN_35___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__XPA_GAIN_35___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35__XPA_GAIN_35___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_35___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36 (0x005E5C90) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__IPA_GAIN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__DAC_GAIN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__TX_PWR_LV_LAA_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__TX_PWR_LV_N79_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__BBF_GAIN_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__UPC_GAIN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__DA_GAIN_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__XPA_GAIN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__IPA_GAIN_36___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__IPA_GAIN_36___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__DAC_GAIN_36___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__DAC_GAIN_36___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__TX_PWR_LV_LAA_36___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__TX_PWR_LV_LAA_36___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__TX_PWR_LV_N79_36___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__TX_PWR_LV_N79_36___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__BBF_GAIN_36___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__BBF_GAIN_36___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__UPC_GAIN_36___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__UPC_GAIN_36___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__DA_GAIN_36___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__DA_GAIN_36___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__XPA_GAIN_36___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36__XPA_GAIN_36___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_36___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37 (0x005E5C94) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__IPA_GAIN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__DAC_GAIN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__TX_PWR_LV_LAA_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__TX_PWR_LV_N79_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__BBF_GAIN_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__UPC_GAIN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__DA_GAIN_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__XPA_GAIN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__IPA_GAIN_37___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__IPA_GAIN_37___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__DAC_GAIN_37___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__DAC_GAIN_37___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__TX_PWR_LV_LAA_37___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__TX_PWR_LV_LAA_37___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__TX_PWR_LV_N79_37___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__TX_PWR_LV_N79_37___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__BBF_GAIN_37___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__BBF_GAIN_37___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__UPC_GAIN_37___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__UPC_GAIN_37___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__DA_GAIN_37___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__DA_GAIN_37___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__XPA_GAIN_37___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37__XPA_GAIN_37___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_37___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38 (0x005E5C98) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__IPA_GAIN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__DAC_GAIN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__TX_PWR_LV_LAA_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__TX_PWR_LV_N79_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__BBF_GAIN_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__UPC_GAIN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__DA_GAIN_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__XPA_GAIN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__IPA_GAIN_38___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__IPA_GAIN_38___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__DAC_GAIN_38___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__DAC_GAIN_38___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__TX_PWR_LV_LAA_38___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__TX_PWR_LV_LAA_38___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__TX_PWR_LV_N79_38___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__TX_PWR_LV_N79_38___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__BBF_GAIN_38___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__BBF_GAIN_38___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__UPC_GAIN_38___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__UPC_GAIN_38___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__DA_GAIN_38___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__DA_GAIN_38___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__XPA_GAIN_38___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38__XPA_GAIN_38___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_38___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39 (0x005E5C9C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__IPA_GAIN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__DAC_GAIN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__TX_PWR_LV_LAA_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__TX_PWR_LV_N79_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__BBF_GAIN_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__UPC_GAIN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__DA_GAIN_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__XPA_GAIN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__IPA_GAIN_39___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__IPA_GAIN_39___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__DAC_GAIN_39___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__DAC_GAIN_39___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__TX_PWR_LV_LAA_39___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__TX_PWR_LV_LAA_39___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__TX_PWR_LV_N79_39___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__TX_PWR_LV_N79_39___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__BBF_GAIN_39___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__BBF_GAIN_39___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__UPC_GAIN_39___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__UPC_GAIN_39___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__DA_GAIN_39___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__DA_GAIN_39___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__XPA_GAIN_39___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39__XPA_GAIN_39___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_39___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40 (0x005E5CA0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__IPA_GAIN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__DAC_GAIN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__TX_PWR_LV_LAA_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__TX_PWR_LV_N79_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__BBF_GAIN_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__UPC_GAIN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__DA_GAIN_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__XPA_GAIN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__IPA_GAIN_40___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__IPA_GAIN_40___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__DAC_GAIN_40___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__DAC_GAIN_40___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__TX_PWR_LV_LAA_40___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__TX_PWR_LV_LAA_40___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__TX_PWR_LV_N79_40___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__TX_PWR_LV_N79_40___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__BBF_GAIN_40___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__BBF_GAIN_40___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__UPC_GAIN_40___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__UPC_GAIN_40___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__DA_GAIN_40___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__DA_GAIN_40___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__XPA_GAIN_40___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40__XPA_GAIN_40___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_40___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41 (0x005E5CA4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__IPA_GAIN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__DAC_GAIN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__TX_PWR_LV_LAA_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__TX_PWR_LV_N79_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__BBF_GAIN_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__UPC_GAIN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__DA_GAIN_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__XPA_GAIN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__IPA_GAIN_41___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__IPA_GAIN_41___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__DAC_GAIN_41___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__DAC_GAIN_41___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__TX_PWR_LV_LAA_41___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__TX_PWR_LV_LAA_41___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__TX_PWR_LV_N79_41___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__TX_PWR_LV_N79_41___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__BBF_GAIN_41___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__BBF_GAIN_41___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__UPC_GAIN_41___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__UPC_GAIN_41___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__DA_GAIN_41___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__DA_GAIN_41___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__XPA_GAIN_41___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41__XPA_GAIN_41___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_41___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42 (0x005E5CA8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__IPA_GAIN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__DAC_GAIN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__TX_PWR_LV_LAA_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__TX_PWR_LV_N79_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__BBF_GAIN_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__UPC_GAIN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__DA_GAIN_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__XPA_GAIN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__IPA_GAIN_42___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__IPA_GAIN_42___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__DAC_GAIN_42___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__DAC_GAIN_42___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__TX_PWR_LV_LAA_42___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__TX_PWR_LV_LAA_42___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__TX_PWR_LV_N79_42___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__TX_PWR_LV_N79_42___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__BBF_GAIN_42___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__BBF_GAIN_42___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__UPC_GAIN_42___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__UPC_GAIN_42___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__DA_GAIN_42___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__DA_GAIN_42___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__XPA_GAIN_42___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42__XPA_GAIN_42___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_42___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43 (0x005E5CAC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__IPA_GAIN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__DAC_GAIN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__TX_PWR_LV_LAA_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__TX_PWR_LV_N79_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__BBF_GAIN_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__UPC_GAIN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__DA_GAIN_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__XPA_GAIN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__IPA_GAIN_43___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__IPA_GAIN_43___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__DAC_GAIN_43___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__DAC_GAIN_43___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__TX_PWR_LV_LAA_43___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__TX_PWR_LV_LAA_43___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__TX_PWR_LV_N79_43___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__TX_PWR_LV_N79_43___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__BBF_GAIN_43___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__BBF_GAIN_43___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__UPC_GAIN_43___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__UPC_GAIN_43___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__DA_GAIN_43___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__DA_GAIN_43___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__XPA_GAIN_43___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43__XPA_GAIN_43___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_43___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44 (0x005E5CB0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__IPA_GAIN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__DAC_GAIN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__TX_PWR_LV_LAA_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__TX_PWR_LV_N79_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__BBF_GAIN_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__UPC_GAIN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__DA_GAIN_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__XPA_GAIN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__IPA_GAIN_44___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__IPA_GAIN_44___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__DAC_GAIN_44___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__DAC_GAIN_44___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__TX_PWR_LV_LAA_44___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__TX_PWR_LV_LAA_44___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__TX_PWR_LV_N79_44___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__TX_PWR_LV_N79_44___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__BBF_GAIN_44___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__BBF_GAIN_44___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__UPC_GAIN_44___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__UPC_GAIN_44___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__DA_GAIN_44___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__DA_GAIN_44___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__XPA_GAIN_44___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44__XPA_GAIN_44___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_44___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45 (0x005E5CB4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__IPA_GAIN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__DAC_GAIN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__TX_PWR_LV_LAA_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__TX_PWR_LV_N79_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__BBF_GAIN_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__UPC_GAIN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__DA_GAIN_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__XPA_GAIN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__IPA_GAIN_45___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__IPA_GAIN_45___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__DAC_GAIN_45___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__DAC_GAIN_45___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__TX_PWR_LV_LAA_45___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__TX_PWR_LV_LAA_45___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__TX_PWR_LV_N79_45___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__TX_PWR_LV_N79_45___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__BBF_GAIN_45___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__BBF_GAIN_45___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__UPC_GAIN_45___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__UPC_GAIN_45___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__DA_GAIN_45___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__DA_GAIN_45___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__XPA_GAIN_45___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45__XPA_GAIN_45___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_45___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46 (0x005E5CB8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__IPA_GAIN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__DAC_GAIN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__TX_PWR_LV_LAA_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__TX_PWR_LV_N79_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__BBF_GAIN_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__UPC_GAIN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__DA_GAIN_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__XPA_GAIN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__IPA_GAIN_46___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__IPA_GAIN_46___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__DAC_GAIN_46___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__DAC_GAIN_46___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__TX_PWR_LV_LAA_46___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__TX_PWR_LV_LAA_46___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__TX_PWR_LV_N79_46___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__TX_PWR_LV_N79_46___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__BBF_GAIN_46___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__BBF_GAIN_46___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__UPC_GAIN_46___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__UPC_GAIN_46___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__DA_GAIN_46___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__DA_GAIN_46___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__XPA_GAIN_46___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46__XPA_GAIN_46___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_46___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47 (0x005E5CBC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__IPA_GAIN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__DAC_GAIN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__TX_PWR_LV_LAA_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__TX_PWR_LV_N79_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__BBF_GAIN_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__UPC_GAIN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__DA_GAIN_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__XPA_GAIN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__IPA_GAIN_47___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__IPA_GAIN_47___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__DAC_GAIN_47___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__DAC_GAIN_47___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__TX_PWR_LV_LAA_47___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__TX_PWR_LV_LAA_47___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__TX_PWR_LV_N79_47___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__TX_PWR_LV_N79_47___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__BBF_GAIN_47___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__BBF_GAIN_47___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__UPC_GAIN_47___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__UPC_GAIN_47___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__DA_GAIN_47___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__DA_GAIN_47___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__XPA_GAIN_47___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47__XPA_GAIN_47___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_47___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48 (0x005E5CC0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__IPA_GAIN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__DAC_GAIN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__TX_PWR_LV_LAA_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__TX_PWR_LV_N79_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__BBF_GAIN_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__UPC_GAIN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__DA_GAIN_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__XPA_GAIN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__IPA_GAIN_48___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__IPA_GAIN_48___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__DAC_GAIN_48___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__DAC_GAIN_48___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__TX_PWR_LV_LAA_48___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__TX_PWR_LV_LAA_48___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__TX_PWR_LV_N79_48___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__TX_PWR_LV_N79_48___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__BBF_GAIN_48___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__BBF_GAIN_48___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__UPC_GAIN_48___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__UPC_GAIN_48___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__DA_GAIN_48___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__DA_GAIN_48___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__XPA_GAIN_48___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48__XPA_GAIN_48___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_48___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49 (0x005E5CC4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__IPA_GAIN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__DAC_GAIN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__TX_PWR_LV_LAA_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__TX_PWR_LV_N79_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__BBF_GAIN_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__UPC_GAIN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__DA_GAIN_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__XPA_GAIN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__IPA_GAIN_49___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__IPA_GAIN_49___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__DAC_GAIN_49___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__DAC_GAIN_49___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__TX_PWR_LV_LAA_49___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__TX_PWR_LV_LAA_49___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__TX_PWR_LV_N79_49___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__TX_PWR_LV_N79_49___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__BBF_GAIN_49___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__BBF_GAIN_49___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__UPC_GAIN_49___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__UPC_GAIN_49___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__DA_GAIN_49___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__DA_GAIN_49___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__XPA_GAIN_49___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49__XPA_GAIN_49___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_49___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50 (0x005E5CC8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__IPA_GAIN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__DAC_GAIN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__TX_PWR_LV_LAA_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__TX_PWR_LV_N79_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__BBF_GAIN_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__UPC_GAIN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__DA_GAIN_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__XPA_GAIN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__IPA_GAIN_50___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__IPA_GAIN_50___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__DAC_GAIN_50___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__DAC_GAIN_50___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__TX_PWR_LV_LAA_50___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__TX_PWR_LV_LAA_50___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__TX_PWR_LV_N79_50___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__TX_PWR_LV_N79_50___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__BBF_GAIN_50___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__BBF_GAIN_50___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__UPC_GAIN_50___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__UPC_GAIN_50___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__DA_GAIN_50___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__DA_GAIN_50___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__XPA_GAIN_50___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50__XPA_GAIN_50___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_50___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51 (0x005E5CCC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__IPA_GAIN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__DAC_GAIN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__TX_PWR_LV_LAA_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__TX_PWR_LV_N79_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__BBF_GAIN_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__UPC_GAIN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__DA_GAIN_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__XPA_GAIN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__IPA_GAIN_51___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__IPA_GAIN_51___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__DAC_GAIN_51___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__DAC_GAIN_51___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__TX_PWR_LV_LAA_51___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__TX_PWR_LV_LAA_51___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__TX_PWR_LV_N79_51___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__TX_PWR_LV_N79_51___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__BBF_GAIN_51___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__BBF_GAIN_51___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__UPC_GAIN_51___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__UPC_GAIN_51___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__DA_GAIN_51___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__DA_GAIN_51___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__XPA_GAIN_51___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51__XPA_GAIN_51___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_51___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52 (0x005E5CD0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__IPA_GAIN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__DAC_GAIN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__TX_PWR_LV_LAA_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__TX_PWR_LV_N79_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__BBF_GAIN_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__UPC_GAIN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__DA_GAIN_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__XPA_GAIN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__IPA_GAIN_52___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__IPA_GAIN_52___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__DAC_GAIN_52___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__DAC_GAIN_52___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__TX_PWR_LV_LAA_52___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__TX_PWR_LV_LAA_52___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__TX_PWR_LV_N79_52___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__TX_PWR_LV_N79_52___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__BBF_GAIN_52___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__BBF_GAIN_52___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__UPC_GAIN_52___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__UPC_GAIN_52___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__DA_GAIN_52___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__DA_GAIN_52___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__XPA_GAIN_52___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52__XPA_GAIN_52___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_52___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53 (0x005E5CD4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__IPA_GAIN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__DAC_GAIN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__TX_PWR_LV_LAA_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__TX_PWR_LV_N79_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__BBF_GAIN_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__UPC_GAIN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__DA_GAIN_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__XPA_GAIN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__IPA_GAIN_53___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__IPA_GAIN_53___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__DAC_GAIN_53___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__DAC_GAIN_53___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__TX_PWR_LV_LAA_53___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__TX_PWR_LV_LAA_53___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__TX_PWR_LV_N79_53___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__TX_PWR_LV_N79_53___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__BBF_GAIN_53___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__BBF_GAIN_53___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__UPC_GAIN_53___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__UPC_GAIN_53___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__DA_GAIN_53___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__DA_GAIN_53___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__XPA_GAIN_53___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53__XPA_GAIN_53___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_53___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54 (0x005E5CD8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__IPA_GAIN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__DAC_GAIN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__TX_PWR_LV_LAA_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__TX_PWR_LV_N79_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__BBF_GAIN_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__UPC_GAIN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__DA_GAIN_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__XPA_GAIN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__IPA_GAIN_54___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__IPA_GAIN_54___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__DAC_GAIN_54___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__DAC_GAIN_54___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__TX_PWR_LV_LAA_54___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__TX_PWR_LV_LAA_54___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__TX_PWR_LV_N79_54___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__TX_PWR_LV_N79_54___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__BBF_GAIN_54___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__BBF_GAIN_54___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__UPC_GAIN_54___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__UPC_GAIN_54___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__DA_GAIN_54___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__DA_GAIN_54___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__XPA_GAIN_54___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54__XPA_GAIN_54___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_54___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55 (0x005E5CDC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__IPA_GAIN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__DAC_GAIN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__TX_PWR_LV_LAA_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__TX_PWR_LV_N79_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__BBF_GAIN_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__UPC_GAIN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__DA_GAIN_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__XPA_GAIN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__IPA_GAIN_55___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__IPA_GAIN_55___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__DAC_GAIN_55___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__DAC_GAIN_55___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__TX_PWR_LV_LAA_55___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__TX_PWR_LV_LAA_55___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__TX_PWR_LV_N79_55___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__TX_PWR_LV_N79_55___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__BBF_GAIN_55___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__BBF_GAIN_55___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__UPC_GAIN_55___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__UPC_GAIN_55___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__DA_GAIN_55___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__DA_GAIN_55___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__XPA_GAIN_55___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55__XPA_GAIN_55___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_55___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56 (0x005E5CE0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__IPA_GAIN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__DAC_GAIN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__TX_PWR_LV_LAA_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__TX_PWR_LV_N79_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__BBF_GAIN_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__UPC_GAIN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__DA_GAIN_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__XPA_GAIN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__IPA_GAIN_56___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__IPA_GAIN_56___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__DAC_GAIN_56___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__DAC_GAIN_56___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__TX_PWR_LV_LAA_56___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__TX_PWR_LV_LAA_56___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__TX_PWR_LV_N79_56___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__TX_PWR_LV_N79_56___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__BBF_GAIN_56___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__BBF_GAIN_56___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__UPC_GAIN_56___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__UPC_GAIN_56___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__DA_GAIN_56___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__DA_GAIN_56___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__XPA_GAIN_56___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56__XPA_GAIN_56___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_56___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57 (0x005E5CE4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__IPA_GAIN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__DAC_GAIN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__TX_PWR_LV_LAA_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__TX_PWR_LV_N79_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__BBF_GAIN_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__UPC_GAIN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__DA_GAIN_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__XPA_GAIN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__IPA_GAIN_57___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__IPA_GAIN_57___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__DAC_GAIN_57___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__DAC_GAIN_57___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__TX_PWR_LV_LAA_57___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__TX_PWR_LV_LAA_57___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__TX_PWR_LV_N79_57___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__TX_PWR_LV_N79_57___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__BBF_GAIN_57___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__BBF_GAIN_57___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__UPC_GAIN_57___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__UPC_GAIN_57___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__DA_GAIN_57___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__DA_GAIN_57___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__XPA_GAIN_57___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57__XPA_GAIN_57___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_57___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58 (0x005E5CE8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__IPA_GAIN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__DAC_GAIN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__TX_PWR_LV_LAA_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__TX_PWR_LV_N79_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__BBF_GAIN_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__UPC_GAIN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__DA_GAIN_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__XPA_GAIN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__IPA_GAIN_58___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__IPA_GAIN_58___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__DAC_GAIN_58___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__DAC_GAIN_58___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__TX_PWR_LV_LAA_58___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__TX_PWR_LV_LAA_58___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__TX_PWR_LV_N79_58___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__TX_PWR_LV_N79_58___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__BBF_GAIN_58___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__BBF_GAIN_58___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__UPC_GAIN_58___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__UPC_GAIN_58___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__DA_GAIN_58___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__DA_GAIN_58___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__XPA_GAIN_58___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58__XPA_GAIN_58___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_58___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59 (0x005E5CEC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__IPA_GAIN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__DAC_GAIN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__TX_PWR_LV_LAA_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__TX_PWR_LV_N79_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__BBF_GAIN_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__UPC_GAIN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__DA_GAIN_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__XPA_GAIN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__IPA_GAIN_59___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__IPA_GAIN_59___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__DAC_GAIN_59___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__DAC_GAIN_59___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__TX_PWR_LV_LAA_59___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__TX_PWR_LV_LAA_59___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__TX_PWR_LV_N79_59___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__TX_PWR_LV_N79_59___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__BBF_GAIN_59___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__BBF_GAIN_59___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__UPC_GAIN_59___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__UPC_GAIN_59___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__DA_GAIN_59___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__DA_GAIN_59___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__XPA_GAIN_59___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59__XPA_GAIN_59___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_59___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60 (0x005E5CF0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__IPA_GAIN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__DAC_GAIN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__TX_PWR_LV_LAA_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__TX_PWR_LV_N79_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__BBF_GAIN_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__UPC_GAIN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__DA_GAIN_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__XPA_GAIN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__IPA_GAIN_60___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__IPA_GAIN_60___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__DAC_GAIN_60___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__DAC_GAIN_60___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__TX_PWR_LV_LAA_60___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__TX_PWR_LV_LAA_60___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__TX_PWR_LV_N79_60___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__TX_PWR_LV_N79_60___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__BBF_GAIN_60___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__BBF_GAIN_60___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__UPC_GAIN_60___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__UPC_GAIN_60___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__DA_GAIN_60___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__DA_GAIN_60___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__XPA_GAIN_60___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60__XPA_GAIN_60___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_60___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61 (0x005E5CF4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__IPA_GAIN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__DAC_GAIN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__TX_PWR_LV_LAA_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__TX_PWR_LV_N79_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__BBF_GAIN_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__UPC_GAIN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__DA_GAIN_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__XPA_GAIN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__IPA_GAIN_61___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__IPA_GAIN_61___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__DAC_GAIN_61___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__DAC_GAIN_61___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__TX_PWR_LV_LAA_61___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__TX_PWR_LV_LAA_61___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__TX_PWR_LV_N79_61___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__TX_PWR_LV_N79_61___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__BBF_GAIN_61___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__BBF_GAIN_61___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__UPC_GAIN_61___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__UPC_GAIN_61___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__DA_GAIN_61___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__DA_GAIN_61___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__XPA_GAIN_61___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61__XPA_GAIN_61___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_61___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62 (0x005E5CF8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__IPA_GAIN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__DAC_GAIN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__TX_PWR_LV_LAA_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__TX_PWR_LV_N79_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__BBF_GAIN_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__UPC_GAIN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__DA_GAIN_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__XPA_GAIN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__IPA_GAIN_62___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__IPA_GAIN_62___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__DAC_GAIN_62___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__DAC_GAIN_62___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__TX_PWR_LV_LAA_62___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__TX_PWR_LV_LAA_62___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__TX_PWR_LV_N79_62___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__TX_PWR_LV_N79_62___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__BBF_GAIN_62___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__BBF_GAIN_62___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__UPC_GAIN_62___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__UPC_GAIN_62___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__DA_GAIN_62___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__DA_GAIN_62___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__XPA_GAIN_62___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62__XPA_GAIN_62___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_62___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63 (0x005E5CFC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__IPA_GAIN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__DAC_GAIN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__TX_PWR_LV_LAA_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__TX_PWR_LV_N79_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__BBF_GAIN_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__UPC_GAIN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__DA_GAIN_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__XPA_GAIN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__IPA_GAIN_63___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__IPA_GAIN_63___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__DAC_GAIN_63___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__DAC_GAIN_63___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__TX_PWR_LV_LAA_63___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__TX_PWR_LV_LAA_63___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__TX_PWR_LV_N79_63___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__TX_PWR_LV_N79_63___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__BBF_GAIN_63___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__BBF_GAIN_63___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__UPC_GAIN_63___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__UPC_GAIN_63___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__DA_GAIN_63___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__DA_GAIN_63___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__XPA_GAIN_63___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63__XPA_GAIN_63___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_63___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64 (0x005E5D00) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__IPA_GAIN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__DAC_GAIN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__TX_PWR_LV_LAA_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__TX_PWR_LV_N79_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__BBF_GAIN_64___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__UPC_GAIN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__DA_GAIN_64___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__XPA_GAIN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__IPA_GAIN_64___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__IPA_GAIN_64___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__DAC_GAIN_64___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__DAC_GAIN_64___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__TX_PWR_LV_LAA_64___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__TX_PWR_LV_LAA_64___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__TX_PWR_LV_N79_64___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__TX_PWR_LV_N79_64___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__BBF_GAIN_64___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__BBF_GAIN_64___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__UPC_GAIN_64___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__UPC_GAIN_64___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__DA_GAIN_64___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__DA_GAIN_64___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__XPA_GAIN_64___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64__XPA_GAIN_64___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_64___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65 (0x005E5D04) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__IPA_GAIN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__DAC_GAIN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__TX_PWR_LV_LAA_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__TX_PWR_LV_N79_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__BBF_GAIN_65___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__UPC_GAIN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__DA_GAIN_65___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__XPA_GAIN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__IPA_GAIN_65___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__IPA_GAIN_65___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__DAC_GAIN_65___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__DAC_GAIN_65___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__TX_PWR_LV_LAA_65___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__TX_PWR_LV_LAA_65___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__TX_PWR_LV_N79_65___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__TX_PWR_LV_N79_65___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__BBF_GAIN_65___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__BBF_GAIN_65___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__UPC_GAIN_65___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__UPC_GAIN_65___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__DA_GAIN_65___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__DA_GAIN_65___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__XPA_GAIN_65___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65__XPA_GAIN_65___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_65___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66 (0x005E5D08) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__IPA_GAIN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__DAC_GAIN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__TX_PWR_LV_LAA_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__TX_PWR_LV_N79_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__BBF_GAIN_66___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__UPC_GAIN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__DA_GAIN_66___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__XPA_GAIN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__IPA_GAIN_66___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__IPA_GAIN_66___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__DAC_GAIN_66___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__DAC_GAIN_66___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__TX_PWR_LV_LAA_66___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__TX_PWR_LV_LAA_66___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__TX_PWR_LV_N79_66___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__TX_PWR_LV_N79_66___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__BBF_GAIN_66___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__BBF_GAIN_66___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__UPC_GAIN_66___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__UPC_GAIN_66___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__DA_GAIN_66___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__DA_GAIN_66___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__XPA_GAIN_66___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66__XPA_GAIN_66___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_66___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67 (0x005E5D0C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__IPA_GAIN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__DAC_GAIN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__TX_PWR_LV_LAA_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__TX_PWR_LV_N79_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__BBF_GAIN_67___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__UPC_GAIN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__DA_GAIN_67___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__XPA_GAIN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__IPA_GAIN_67___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__IPA_GAIN_67___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__DAC_GAIN_67___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__DAC_GAIN_67___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__TX_PWR_LV_LAA_67___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__TX_PWR_LV_LAA_67___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__TX_PWR_LV_N79_67___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__TX_PWR_LV_N79_67___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__BBF_GAIN_67___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__BBF_GAIN_67___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__UPC_GAIN_67___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__UPC_GAIN_67___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__DA_GAIN_67___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__DA_GAIN_67___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__XPA_GAIN_67___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67__XPA_GAIN_67___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_67___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68 (0x005E5D10) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__IPA_GAIN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__DAC_GAIN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__TX_PWR_LV_LAA_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__TX_PWR_LV_N79_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__BBF_GAIN_68___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__UPC_GAIN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__DA_GAIN_68___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__XPA_GAIN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__IPA_GAIN_68___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__IPA_GAIN_68___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__DAC_GAIN_68___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__DAC_GAIN_68___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__TX_PWR_LV_LAA_68___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__TX_PWR_LV_LAA_68___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__TX_PWR_LV_N79_68___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__TX_PWR_LV_N79_68___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__BBF_GAIN_68___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__BBF_GAIN_68___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__UPC_GAIN_68___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__UPC_GAIN_68___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__DA_GAIN_68___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__DA_GAIN_68___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__XPA_GAIN_68___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68__XPA_GAIN_68___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_68___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69 (0x005E5D14) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__IPA_GAIN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__DAC_GAIN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__TX_PWR_LV_LAA_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__TX_PWR_LV_N79_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__BBF_GAIN_69___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__UPC_GAIN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__DA_GAIN_69___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__XPA_GAIN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__IPA_GAIN_69___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__IPA_GAIN_69___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__DAC_GAIN_69___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__DAC_GAIN_69___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__TX_PWR_LV_LAA_69___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__TX_PWR_LV_LAA_69___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__TX_PWR_LV_N79_69___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__TX_PWR_LV_N79_69___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__BBF_GAIN_69___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__BBF_GAIN_69___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__UPC_GAIN_69___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__UPC_GAIN_69___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__DA_GAIN_69___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__DA_GAIN_69___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__XPA_GAIN_69___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69__XPA_GAIN_69___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_69___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70 (0x005E5D18) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__IPA_GAIN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__DAC_GAIN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__TX_PWR_LV_LAA_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__TX_PWR_LV_N79_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__BBF_GAIN_70___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__UPC_GAIN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__DA_GAIN_70___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__XPA_GAIN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__IPA_GAIN_70___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__IPA_GAIN_70___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__DAC_GAIN_70___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__DAC_GAIN_70___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__TX_PWR_LV_LAA_70___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__TX_PWR_LV_LAA_70___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__TX_PWR_LV_N79_70___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__TX_PWR_LV_N79_70___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__BBF_GAIN_70___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__BBF_GAIN_70___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__UPC_GAIN_70___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__UPC_GAIN_70___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__DA_GAIN_70___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__DA_GAIN_70___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__XPA_GAIN_70___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70__XPA_GAIN_70___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_70___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71 (0x005E5D1C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__IPA_GAIN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__DAC_GAIN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__TX_PWR_LV_LAA_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__TX_PWR_LV_N79_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__BBF_GAIN_71___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__UPC_GAIN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__DA_GAIN_71___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__XPA_GAIN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__IPA_GAIN_71___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__IPA_GAIN_71___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__DAC_GAIN_71___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__DAC_GAIN_71___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__TX_PWR_LV_LAA_71___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__TX_PWR_LV_LAA_71___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__TX_PWR_LV_N79_71___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__TX_PWR_LV_N79_71___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__BBF_GAIN_71___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__BBF_GAIN_71___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__UPC_GAIN_71___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__UPC_GAIN_71___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__DA_GAIN_71___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__DA_GAIN_71___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__XPA_GAIN_71___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71__XPA_GAIN_71___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_71___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72 (0x005E5D20) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__IPA_GAIN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__DAC_GAIN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__TX_PWR_LV_LAA_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__TX_PWR_LV_N79_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__BBF_GAIN_72___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__UPC_GAIN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__DA_GAIN_72___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__XPA_GAIN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__IPA_GAIN_72___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__IPA_GAIN_72___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__DAC_GAIN_72___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__DAC_GAIN_72___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__TX_PWR_LV_LAA_72___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__TX_PWR_LV_LAA_72___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__TX_PWR_LV_N79_72___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__TX_PWR_LV_N79_72___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__BBF_GAIN_72___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__BBF_GAIN_72___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__UPC_GAIN_72___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__UPC_GAIN_72___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__DA_GAIN_72___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__DA_GAIN_72___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__XPA_GAIN_72___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72__XPA_GAIN_72___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_72___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73 (0x005E5D24) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__IPA_GAIN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__DAC_GAIN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__TX_PWR_LV_LAA_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__TX_PWR_LV_N79_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__BBF_GAIN_73___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__UPC_GAIN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__DA_GAIN_73___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__XPA_GAIN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__IPA_GAIN_73___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__IPA_GAIN_73___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__DAC_GAIN_73___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__DAC_GAIN_73___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__TX_PWR_LV_LAA_73___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__TX_PWR_LV_LAA_73___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__TX_PWR_LV_N79_73___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__TX_PWR_LV_N79_73___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__BBF_GAIN_73___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__BBF_GAIN_73___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__UPC_GAIN_73___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__UPC_GAIN_73___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__DA_GAIN_73___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__DA_GAIN_73___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__XPA_GAIN_73___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73__XPA_GAIN_73___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_73___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74 (0x005E5D28) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__IPA_GAIN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__DAC_GAIN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__TX_PWR_LV_LAA_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__TX_PWR_LV_N79_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__BBF_GAIN_74___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__UPC_GAIN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__DA_GAIN_74___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__XPA_GAIN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__IPA_GAIN_74___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__IPA_GAIN_74___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__DAC_GAIN_74___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__DAC_GAIN_74___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__TX_PWR_LV_LAA_74___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__TX_PWR_LV_LAA_74___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__TX_PWR_LV_N79_74___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__TX_PWR_LV_N79_74___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__BBF_GAIN_74___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__BBF_GAIN_74___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__UPC_GAIN_74___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__UPC_GAIN_74___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__DA_GAIN_74___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__DA_GAIN_74___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__XPA_GAIN_74___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74__XPA_GAIN_74___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_74___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75 (0x005E5D2C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__IPA_GAIN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__DAC_GAIN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__TX_PWR_LV_LAA_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__TX_PWR_LV_N79_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__BBF_GAIN_75___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__UPC_GAIN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__DA_GAIN_75___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__XPA_GAIN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__IPA_GAIN_75___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__IPA_GAIN_75___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__DAC_GAIN_75___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__DAC_GAIN_75___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__TX_PWR_LV_LAA_75___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__TX_PWR_LV_LAA_75___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__TX_PWR_LV_N79_75___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__TX_PWR_LV_N79_75___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__BBF_GAIN_75___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__BBF_GAIN_75___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__UPC_GAIN_75___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__UPC_GAIN_75___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__DA_GAIN_75___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__DA_GAIN_75___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__XPA_GAIN_75___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75__XPA_GAIN_75___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_75___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76 (0x005E5D30) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__IPA_GAIN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__DAC_GAIN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__TX_PWR_LV_LAA_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__TX_PWR_LV_N79_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__BBF_GAIN_76___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__UPC_GAIN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__DA_GAIN_76___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__XPA_GAIN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__IPA_GAIN_76___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__IPA_GAIN_76___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__DAC_GAIN_76___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__DAC_GAIN_76___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__TX_PWR_LV_LAA_76___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__TX_PWR_LV_LAA_76___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__TX_PWR_LV_N79_76___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__TX_PWR_LV_N79_76___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__BBF_GAIN_76___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__BBF_GAIN_76___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__UPC_GAIN_76___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__UPC_GAIN_76___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__DA_GAIN_76___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__DA_GAIN_76___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__XPA_GAIN_76___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76__XPA_GAIN_76___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_76___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77 (0x005E5D34) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__IPA_GAIN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__DAC_GAIN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__TX_PWR_LV_LAA_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__TX_PWR_LV_N79_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__BBF_GAIN_77___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__UPC_GAIN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__DA_GAIN_77___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__XPA_GAIN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__IPA_GAIN_77___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__IPA_GAIN_77___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__DAC_GAIN_77___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__DAC_GAIN_77___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__TX_PWR_LV_LAA_77___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__TX_PWR_LV_LAA_77___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__TX_PWR_LV_N79_77___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__TX_PWR_LV_N79_77___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__BBF_GAIN_77___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__BBF_GAIN_77___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__UPC_GAIN_77___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__UPC_GAIN_77___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__DA_GAIN_77___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__DA_GAIN_77___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__XPA_GAIN_77___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77__XPA_GAIN_77___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_77___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78 (0x005E5D38) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__IPA_GAIN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__DAC_GAIN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__TX_PWR_LV_LAA_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__TX_PWR_LV_N79_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__BBF_GAIN_78___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__UPC_GAIN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__DA_GAIN_78___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__XPA_GAIN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__IPA_GAIN_78___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__IPA_GAIN_78___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__DAC_GAIN_78___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__DAC_GAIN_78___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__TX_PWR_LV_LAA_78___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__TX_PWR_LV_LAA_78___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__TX_PWR_LV_N79_78___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__TX_PWR_LV_N79_78___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__BBF_GAIN_78___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__BBF_GAIN_78___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__UPC_GAIN_78___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__UPC_GAIN_78___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__DA_GAIN_78___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__DA_GAIN_78___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__XPA_GAIN_78___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78__XPA_GAIN_78___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_78___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79 (0x005E5D3C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__IPA_GAIN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__DAC_GAIN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__TX_PWR_LV_LAA_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__TX_PWR_LV_N79_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__BBF_GAIN_79___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__UPC_GAIN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__DA_GAIN_79___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__XPA_GAIN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__IPA_GAIN_79___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__IPA_GAIN_79___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__DAC_GAIN_79___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__DAC_GAIN_79___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__TX_PWR_LV_LAA_79___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__TX_PWR_LV_LAA_79___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__TX_PWR_LV_N79_79___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__TX_PWR_LV_N79_79___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__BBF_GAIN_79___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__BBF_GAIN_79___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__UPC_GAIN_79___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__UPC_GAIN_79___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__DA_GAIN_79___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__DA_GAIN_79___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__XPA_GAIN_79___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79__XPA_GAIN_79___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_79___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80 (0x005E5D40) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__IPA_GAIN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__DAC_GAIN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__TX_PWR_LV_LAA_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__TX_PWR_LV_N79_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__BBF_GAIN_80___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__UPC_GAIN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__DA_GAIN_80___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__XPA_GAIN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__IPA_GAIN_80___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__IPA_GAIN_80___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__DAC_GAIN_80___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__DAC_GAIN_80___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__TX_PWR_LV_LAA_80___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__TX_PWR_LV_LAA_80___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__TX_PWR_LV_N79_80___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__TX_PWR_LV_N79_80___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__BBF_GAIN_80___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__BBF_GAIN_80___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__UPC_GAIN_80___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__UPC_GAIN_80___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__DA_GAIN_80___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__DA_GAIN_80___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__XPA_GAIN_80___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80__XPA_GAIN_80___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_80___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81 (0x005E5D44) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__IPA_GAIN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__DAC_GAIN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__TX_PWR_LV_LAA_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__TX_PWR_LV_N79_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__BBF_GAIN_81___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__UPC_GAIN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__DA_GAIN_81___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__XPA_GAIN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__IPA_GAIN_81___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__IPA_GAIN_81___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__DAC_GAIN_81___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__DAC_GAIN_81___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__TX_PWR_LV_LAA_81___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__TX_PWR_LV_LAA_81___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__TX_PWR_LV_N79_81___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__TX_PWR_LV_N79_81___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__BBF_GAIN_81___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__BBF_GAIN_81___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__UPC_GAIN_81___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__UPC_GAIN_81___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__DA_GAIN_81___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__DA_GAIN_81___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__XPA_GAIN_81___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81__XPA_GAIN_81___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_81___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82 (0x005E5D48) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__IPA_GAIN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__DAC_GAIN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__TX_PWR_LV_LAA_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__TX_PWR_LV_N79_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__BBF_GAIN_82___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__UPC_GAIN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__DA_GAIN_82___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__XPA_GAIN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__IPA_GAIN_82___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__IPA_GAIN_82___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__DAC_GAIN_82___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__DAC_GAIN_82___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__TX_PWR_LV_LAA_82___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__TX_PWR_LV_LAA_82___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__TX_PWR_LV_N79_82___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__TX_PWR_LV_N79_82___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__BBF_GAIN_82___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__BBF_GAIN_82___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__UPC_GAIN_82___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__UPC_GAIN_82___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__DA_GAIN_82___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__DA_GAIN_82___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__XPA_GAIN_82___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82__XPA_GAIN_82___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_82___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83 (0x005E5D4C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__IPA_GAIN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__DAC_GAIN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__TX_PWR_LV_LAA_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__TX_PWR_LV_N79_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__BBF_GAIN_83___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__UPC_GAIN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__DA_GAIN_83___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__XPA_GAIN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__IPA_GAIN_83___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__IPA_GAIN_83___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__DAC_GAIN_83___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__DAC_GAIN_83___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__TX_PWR_LV_LAA_83___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__TX_PWR_LV_LAA_83___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__TX_PWR_LV_N79_83___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__TX_PWR_LV_N79_83___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__BBF_GAIN_83___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__BBF_GAIN_83___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__UPC_GAIN_83___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__UPC_GAIN_83___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__DA_GAIN_83___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__DA_GAIN_83___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__XPA_GAIN_83___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83__XPA_GAIN_83___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_83___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84 (0x005E5D50) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__IPA_GAIN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__DAC_GAIN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__TX_PWR_LV_LAA_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__TX_PWR_LV_N79_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__BBF_GAIN_84___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__UPC_GAIN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__DA_GAIN_84___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__XPA_GAIN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__IPA_GAIN_84___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__IPA_GAIN_84___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__DAC_GAIN_84___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__DAC_GAIN_84___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__TX_PWR_LV_LAA_84___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__TX_PWR_LV_LAA_84___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__TX_PWR_LV_N79_84___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__TX_PWR_LV_N79_84___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__BBF_GAIN_84___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__BBF_GAIN_84___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__UPC_GAIN_84___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__UPC_GAIN_84___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__DA_GAIN_84___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__DA_GAIN_84___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__XPA_GAIN_84___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84__XPA_GAIN_84___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_84___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85 (0x005E5D54) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__IPA_GAIN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__DAC_GAIN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__TX_PWR_LV_LAA_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__TX_PWR_LV_N79_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__BBF_GAIN_85___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__UPC_GAIN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__DA_GAIN_85___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__XPA_GAIN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__IPA_GAIN_85___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__IPA_GAIN_85___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__DAC_GAIN_85___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__DAC_GAIN_85___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__TX_PWR_LV_LAA_85___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__TX_PWR_LV_LAA_85___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__TX_PWR_LV_N79_85___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__TX_PWR_LV_N79_85___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__BBF_GAIN_85___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__BBF_GAIN_85___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__UPC_GAIN_85___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__UPC_GAIN_85___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__DA_GAIN_85___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__DA_GAIN_85___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__XPA_GAIN_85___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85__XPA_GAIN_85___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_85___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86 (0x005E5D58) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__IPA_GAIN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__DAC_GAIN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__TX_PWR_LV_LAA_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__TX_PWR_LV_N79_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__BBF_GAIN_86___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__UPC_GAIN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__DA_GAIN_86___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__XPA_GAIN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__IPA_GAIN_86___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__IPA_GAIN_86___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__DAC_GAIN_86___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__DAC_GAIN_86___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__TX_PWR_LV_LAA_86___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__TX_PWR_LV_LAA_86___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__TX_PWR_LV_N79_86___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__TX_PWR_LV_N79_86___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__BBF_GAIN_86___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__BBF_GAIN_86___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__UPC_GAIN_86___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__UPC_GAIN_86___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__DA_GAIN_86___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__DA_GAIN_86___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__XPA_GAIN_86___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86__XPA_GAIN_86___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_86___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87 (0x005E5D5C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__IPA_GAIN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__DAC_GAIN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__TX_PWR_LV_LAA_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__TX_PWR_LV_N79_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__BBF_GAIN_87___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__UPC_GAIN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__DA_GAIN_87___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__XPA_GAIN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__IPA_GAIN_87___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__IPA_GAIN_87___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__DAC_GAIN_87___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__DAC_GAIN_87___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__TX_PWR_LV_LAA_87___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__TX_PWR_LV_LAA_87___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__TX_PWR_LV_N79_87___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__TX_PWR_LV_N79_87___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__BBF_GAIN_87___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__BBF_GAIN_87___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__UPC_GAIN_87___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__UPC_GAIN_87___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__DA_GAIN_87___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__DA_GAIN_87___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__XPA_GAIN_87___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87__XPA_GAIN_87___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_87___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88 (0x005E5D60) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__IPA_GAIN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__DAC_GAIN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__TX_PWR_LV_LAA_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__TX_PWR_LV_N79_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__BBF_GAIN_88___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__UPC_GAIN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__DA_GAIN_88___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__XPA_GAIN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__IPA_GAIN_88___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__IPA_GAIN_88___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__DAC_GAIN_88___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__DAC_GAIN_88___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__TX_PWR_LV_LAA_88___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__TX_PWR_LV_LAA_88___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__TX_PWR_LV_N79_88___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__TX_PWR_LV_N79_88___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__BBF_GAIN_88___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__BBF_GAIN_88___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__UPC_GAIN_88___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__UPC_GAIN_88___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__DA_GAIN_88___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__DA_GAIN_88___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__XPA_GAIN_88___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88__XPA_GAIN_88___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_88___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89 (0x005E5D64) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__IPA_GAIN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__DAC_GAIN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__TX_PWR_LV_LAA_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__TX_PWR_LV_N79_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__BBF_GAIN_89___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__UPC_GAIN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__DA_GAIN_89___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__XPA_GAIN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__IPA_GAIN_89___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__IPA_GAIN_89___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__DAC_GAIN_89___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__DAC_GAIN_89___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__TX_PWR_LV_LAA_89___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__TX_PWR_LV_LAA_89___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__TX_PWR_LV_N79_89___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__TX_PWR_LV_N79_89___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__BBF_GAIN_89___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__BBF_GAIN_89___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__UPC_GAIN_89___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__UPC_GAIN_89___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__DA_GAIN_89___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__DA_GAIN_89___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__XPA_GAIN_89___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89__XPA_GAIN_89___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_89___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90 (0x005E5D68) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__IPA_GAIN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__DAC_GAIN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__TX_PWR_LV_LAA_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__TX_PWR_LV_N79_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__BBF_GAIN_90___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__UPC_GAIN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__DA_GAIN_90___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__XPA_GAIN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__IPA_GAIN_90___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__IPA_GAIN_90___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__DAC_GAIN_90___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__DAC_GAIN_90___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__TX_PWR_LV_LAA_90___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__TX_PWR_LV_LAA_90___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__TX_PWR_LV_N79_90___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__TX_PWR_LV_N79_90___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__BBF_GAIN_90___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__BBF_GAIN_90___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__UPC_GAIN_90___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__UPC_GAIN_90___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__DA_GAIN_90___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__DA_GAIN_90___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__XPA_GAIN_90___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90__XPA_GAIN_90___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_90___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91 (0x005E5D6C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__IPA_GAIN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__DAC_GAIN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__TX_PWR_LV_LAA_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__TX_PWR_LV_N79_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__BBF_GAIN_91___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__UPC_GAIN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__DA_GAIN_91___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__XPA_GAIN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__IPA_GAIN_91___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__IPA_GAIN_91___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__DAC_GAIN_91___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__DAC_GAIN_91___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__TX_PWR_LV_LAA_91___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__TX_PWR_LV_LAA_91___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__TX_PWR_LV_N79_91___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__TX_PWR_LV_N79_91___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__BBF_GAIN_91___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__BBF_GAIN_91___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__UPC_GAIN_91___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__UPC_GAIN_91___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__DA_GAIN_91___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__DA_GAIN_91___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__XPA_GAIN_91___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91__XPA_GAIN_91___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_91___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92 (0x005E5D70) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__IPA_GAIN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__DAC_GAIN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__TX_PWR_LV_LAA_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__TX_PWR_LV_N79_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__BBF_GAIN_92___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__UPC_GAIN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__DA_GAIN_92___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__XPA_GAIN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__IPA_GAIN_92___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__IPA_GAIN_92___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__DAC_GAIN_92___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__DAC_GAIN_92___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__TX_PWR_LV_LAA_92___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__TX_PWR_LV_LAA_92___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__TX_PWR_LV_N79_92___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__TX_PWR_LV_N79_92___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__BBF_GAIN_92___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__BBF_GAIN_92___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__UPC_GAIN_92___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__UPC_GAIN_92___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__DA_GAIN_92___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__DA_GAIN_92___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__XPA_GAIN_92___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92__XPA_GAIN_92___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_92___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93 (0x005E5D74) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__IPA_GAIN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__DAC_GAIN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__TX_PWR_LV_LAA_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__TX_PWR_LV_N79_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__BBF_GAIN_93___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__UPC_GAIN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__DA_GAIN_93___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__XPA_GAIN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__IPA_GAIN_93___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__IPA_GAIN_93___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__DAC_GAIN_93___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__DAC_GAIN_93___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__TX_PWR_LV_LAA_93___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__TX_PWR_LV_LAA_93___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__TX_PWR_LV_N79_93___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__TX_PWR_LV_N79_93___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__BBF_GAIN_93___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__BBF_GAIN_93___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__UPC_GAIN_93___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__UPC_GAIN_93___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__DA_GAIN_93___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__DA_GAIN_93___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__XPA_GAIN_93___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93__XPA_GAIN_93___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_93___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94 (0x005E5D78) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__IPA_GAIN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__DAC_GAIN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__TX_PWR_LV_LAA_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__TX_PWR_LV_N79_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__BBF_GAIN_94___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__UPC_GAIN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__DA_GAIN_94___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__XPA_GAIN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__IPA_GAIN_94___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__IPA_GAIN_94___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__DAC_GAIN_94___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__DAC_GAIN_94___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__TX_PWR_LV_LAA_94___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__TX_PWR_LV_LAA_94___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__TX_PWR_LV_N79_94___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__TX_PWR_LV_N79_94___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__BBF_GAIN_94___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__BBF_GAIN_94___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__UPC_GAIN_94___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__UPC_GAIN_94___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__DA_GAIN_94___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__DA_GAIN_94___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__XPA_GAIN_94___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94__XPA_GAIN_94___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_94___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95 (0x005E5D7C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__IPA_GAIN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__DAC_GAIN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__TX_PWR_LV_LAA_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__TX_PWR_LV_N79_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__BBF_GAIN_95___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__UPC_GAIN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__DA_GAIN_95___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__XPA_GAIN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__IPA_GAIN_95___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__IPA_GAIN_95___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__DAC_GAIN_95___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__DAC_GAIN_95___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__TX_PWR_LV_LAA_95___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__TX_PWR_LV_LAA_95___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__TX_PWR_LV_N79_95___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__TX_PWR_LV_N79_95___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__BBF_GAIN_95___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__BBF_GAIN_95___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__UPC_GAIN_95___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__UPC_GAIN_95___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__DA_GAIN_95___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__DA_GAIN_95___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__XPA_GAIN_95___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95__XPA_GAIN_95___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_95___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96 (0x005E5D80) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__IPA_GAIN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__DAC_GAIN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__TX_PWR_LV_LAA_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__TX_PWR_LV_N79_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__BBF_GAIN_96___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__UPC_GAIN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__DA_GAIN_96___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__XPA_GAIN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__IPA_GAIN_96___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__IPA_GAIN_96___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__DAC_GAIN_96___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__DAC_GAIN_96___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__TX_PWR_LV_LAA_96___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__TX_PWR_LV_LAA_96___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__TX_PWR_LV_N79_96___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__TX_PWR_LV_N79_96___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__BBF_GAIN_96___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__BBF_GAIN_96___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__UPC_GAIN_96___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__UPC_GAIN_96___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__DA_GAIN_96___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__DA_GAIN_96___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__XPA_GAIN_96___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96__XPA_GAIN_96___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_96___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97 (0x005E5D84) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__IPA_GAIN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__DAC_GAIN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__TX_PWR_LV_LAA_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__TX_PWR_LV_N79_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__BBF_GAIN_97___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__UPC_GAIN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__DA_GAIN_97___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__XPA_GAIN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__IPA_GAIN_97___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__IPA_GAIN_97___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__DAC_GAIN_97___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__DAC_GAIN_97___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__TX_PWR_LV_LAA_97___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__TX_PWR_LV_LAA_97___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__TX_PWR_LV_N79_97___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__TX_PWR_LV_N79_97___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__BBF_GAIN_97___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__BBF_GAIN_97___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__UPC_GAIN_97___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__UPC_GAIN_97___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__DA_GAIN_97___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__DA_GAIN_97___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__XPA_GAIN_97___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97__XPA_GAIN_97___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_97___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98 (0x005E5D88) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__IPA_GAIN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__DAC_GAIN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__TX_PWR_LV_LAA_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__TX_PWR_LV_N79_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__BBF_GAIN_98___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__UPC_GAIN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__DA_GAIN_98___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__XPA_GAIN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__IPA_GAIN_98___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__IPA_GAIN_98___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__DAC_GAIN_98___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__DAC_GAIN_98___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__TX_PWR_LV_LAA_98___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__TX_PWR_LV_LAA_98___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__TX_PWR_LV_N79_98___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__TX_PWR_LV_N79_98___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__BBF_GAIN_98___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__BBF_GAIN_98___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__UPC_GAIN_98___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__UPC_GAIN_98___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__DA_GAIN_98___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__DA_GAIN_98___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__XPA_GAIN_98___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98__XPA_GAIN_98___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_98___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99 (0x005E5D8C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__IPA_GAIN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__DAC_GAIN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__TX_PWR_LV_LAA_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__TX_PWR_LV_N79_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__BBF_GAIN_99___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__UPC_GAIN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__DA_GAIN_99___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__XPA_GAIN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__IPA_GAIN_99___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__IPA_GAIN_99___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__DAC_GAIN_99___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__DAC_GAIN_99___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__TX_PWR_LV_LAA_99___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__TX_PWR_LV_LAA_99___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__TX_PWR_LV_N79_99___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__TX_PWR_LV_N79_99___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__BBF_GAIN_99___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__BBF_GAIN_99___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__UPC_GAIN_99___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__UPC_GAIN_99___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__DA_GAIN_99___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__DA_GAIN_99___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__XPA_GAIN_99___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99__XPA_GAIN_99___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_99___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100 (0x005E5D90) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__IPA_GAIN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__DAC_GAIN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__TX_PWR_LV_LAA_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__TX_PWR_LV_N79_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__BBF_GAIN_100___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__UPC_GAIN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__DA_GAIN_100___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__XPA_GAIN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__IPA_GAIN_100___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__IPA_GAIN_100___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__DAC_GAIN_100___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__DAC_GAIN_100___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__TX_PWR_LV_LAA_100___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__TX_PWR_LV_LAA_100___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__TX_PWR_LV_N79_100___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__TX_PWR_LV_N79_100___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__BBF_GAIN_100___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__BBF_GAIN_100___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__UPC_GAIN_100___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__UPC_GAIN_100___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__DA_GAIN_100___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__DA_GAIN_100___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__XPA_GAIN_100___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100__XPA_GAIN_100___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_100___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101 (0x005E5D94) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__IPA_GAIN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__DAC_GAIN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__TX_PWR_LV_LAA_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__TX_PWR_LV_N79_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__BBF_GAIN_101___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__UPC_GAIN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__DA_GAIN_101___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__XPA_GAIN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__IPA_GAIN_101___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__IPA_GAIN_101___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__DAC_GAIN_101___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__DAC_GAIN_101___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__TX_PWR_LV_LAA_101___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__TX_PWR_LV_LAA_101___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__TX_PWR_LV_N79_101___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__TX_PWR_LV_N79_101___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__BBF_GAIN_101___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__BBF_GAIN_101___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__UPC_GAIN_101___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__UPC_GAIN_101___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__DA_GAIN_101___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__DA_GAIN_101___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__XPA_GAIN_101___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101__XPA_GAIN_101___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_101___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102 (0x005E5D98) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__IPA_GAIN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__DAC_GAIN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__TX_PWR_LV_LAA_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__TX_PWR_LV_N79_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__BBF_GAIN_102___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__UPC_GAIN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__DA_GAIN_102___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__XPA_GAIN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__IPA_GAIN_102___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__IPA_GAIN_102___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__DAC_GAIN_102___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__DAC_GAIN_102___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__TX_PWR_LV_LAA_102___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__TX_PWR_LV_LAA_102___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__TX_PWR_LV_N79_102___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__TX_PWR_LV_N79_102___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__BBF_GAIN_102___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__BBF_GAIN_102___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__UPC_GAIN_102___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__UPC_GAIN_102___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__DA_GAIN_102___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__DA_GAIN_102___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__XPA_GAIN_102___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102__XPA_GAIN_102___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_102___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103 (0x005E5D9C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__IPA_GAIN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__DAC_GAIN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__TX_PWR_LV_LAA_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__TX_PWR_LV_N79_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__BBF_GAIN_103___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__UPC_GAIN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__DA_GAIN_103___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__XPA_GAIN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__IPA_GAIN_103___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__IPA_GAIN_103___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__DAC_GAIN_103___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__DAC_GAIN_103___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__TX_PWR_LV_LAA_103___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__TX_PWR_LV_LAA_103___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__TX_PWR_LV_N79_103___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__TX_PWR_LV_N79_103___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__BBF_GAIN_103___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__BBF_GAIN_103___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__UPC_GAIN_103___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__UPC_GAIN_103___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__DA_GAIN_103___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__DA_GAIN_103___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__XPA_GAIN_103___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103__XPA_GAIN_103___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_103___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104 (0x005E5DA0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__IPA_GAIN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__DAC_GAIN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__TX_PWR_LV_LAA_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__TX_PWR_LV_N79_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__BBF_GAIN_104___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__UPC_GAIN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__DA_GAIN_104___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__XPA_GAIN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__IPA_GAIN_104___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__IPA_GAIN_104___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__DAC_GAIN_104___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__DAC_GAIN_104___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__TX_PWR_LV_LAA_104___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__TX_PWR_LV_LAA_104___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__TX_PWR_LV_N79_104___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__TX_PWR_LV_N79_104___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__BBF_GAIN_104___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__BBF_GAIN_104___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__UPC_GAIN_104___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__UPC_GAIN_104___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__DA_GAIN_104___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__DA_GAIN_104___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__XPA_GAIN_104___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104__XPA_GAIN_104___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_104___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105 (0x005E5DA4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__IPA_GAIN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__DAC_GAIN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__TX_PWR_LV_LAA_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__TX_PWR_LV_N79_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__BBF_GAIN_105___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__UPC_GAIN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__DA_GAIN_105___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__XPA_GAIN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__IPA_GAIN_105___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__IPA_GAIN_105___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__DAC_GAIN_105___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__DAC_GAIN_105___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__TX_PWR_LV_LAA_105___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__TX_PWR_LV_LAA_105___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__TX_PWR_LV_N79_105___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__TX_PWR_LV_N79_105___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__BBF_GAIN_105___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__BBF_GAIN_105___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__UPC_GAIN_105___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__UPC_GAIN_105___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__DA_GAIN_105___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__DA_GAIN_105___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__XPA_GAIN_105___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105__XPA_GAIN_105___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_105___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106 (0x005E5DA8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__IPA_GAIN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__DAC_GAIN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__TX_PWR_LV_LAA_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__TX_PWR_LV_N79_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__BBF_GAIN_106___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__UPC_GAIN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__DA_GAIN_106___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__XPA_GAIN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__IPA_GAIN_106___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__IPA_GAIN_106___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__DAC_GAIN_106___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__DAC_GAIN_106___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__TX_PWR_LV_LAA_106___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__TX_PWR_LV_LAA_106___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__TX_PWR_LV_N79_106___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__TX_PWR_LV_N79_106___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__BBF_GAIN_106___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__BBF_GAIN_106___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__UPC_GAIN_106___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__UPC_GAIN_106___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__DA_GAIN_106___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__DA_GAIN_106___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__XPA_GAIN_106___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106__XPA_GAIN_106___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_106___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107 (0x005E5DAC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__IPA_GAIN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__DAC_GAIN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__TX_PWR_LV_LAA_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__TX_PWR_LV_N79_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__BBF_GAIN_107___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__UPC_GAIN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__DA_GAIN_107___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__XPA_GAIN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__IPA_GAIN_107___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__IPA_GAIN_107___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__DAC_GAIN_107___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__DAC_GAIN_107___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__TX_PWR_LV_LAA_107___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__TX_PWR_LV_LAA_107___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__TX_PWR_LV_N79_107___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__TX_PWR_LV_N79_107___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__BBF_GAIN_107___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__BBF_GAIN_107___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__UPC_GAIN_107___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__UPC_GAIN_107___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__DA_GAIN_107___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__DA_GAIN_107___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__XPA_GAIN_107___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107__XPA_GAIN_107___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_107___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108 (0x005E5DB0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__IPA_GAIN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__DAC_GAIN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__TX_PWR_LV_LAA_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__TX_PWR_LV_N79_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__BBF_GAIN_108___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__UPC_GAIN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__DA_GAIN_108___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__XPA_GAIN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__IPA_GAIN_108___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__IPA_GAIN_108___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__DAC_GAIN_108___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__DAC_GAIN_108___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__TX_PWR_LV_LAA_108___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__TX_PWR_LV_LAA_108___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__TX_PWR_LV_N79_108___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__TX_PWR_LV_N79_108___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__BBF_GAIN_108___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__BBF_GAIN_108___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__UPC_GAIN_108___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__UPC_GAIN_108___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__DA_GAIN_108___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__DA_GAIN_108___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__XPA_GAIN_108___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108__XPA_GAIN_108___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_108___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109 (0x005E5DB4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__IPA_GAIN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__DAC_GAIN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__TX_PWR_LV_LAA_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__TX_PWR_LV_N79_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__BBF_GAIN_109___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__UPC_GAIN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__DA_GAIN_109___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__XPA_GAIN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__IPA_GAIN_109___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__IPA_GAIN_109___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__DAC_GAIN_109___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__DAC_GAIN_109___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__TX_PWR_LV_LAA_109___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__TX_PWR_LV_LAA_109___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__TX_PWR_LV_N79_109___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__TX_PWR_LV_N79_109___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__BBF_GAIN_109___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__BBF_GAIN_109___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__UPC_GAIN_109___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__UPC_GAIN_109___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__DA_GAIN_109___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__DA_GAIN_109___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__XPA_GAIN_109___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109__XPA_GAIN_109___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_109___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110 (0x005E5DB8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__IPA_GAIN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__DAC_GAIN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__TX_PWR_LV_LAA_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__TX_PWR_LV_N79_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__BBF_GAIN_110___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__UPC_GAIN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__DA_GAIN_110___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__XPA_GAIN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__IPA_GAIN_110___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__IPA_GAIN_110___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__DAC_GAIN_110___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__DAC_GAIN_110___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__TX_PWR_LV_LAA_110___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__TX_PWR_LV_LAA_110___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__TX_PWR_LV_N79_110___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__TX_PWR_LV_N79_110___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__BBF_GAIN_110___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__BBF_GAIN_110___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__UPC_GAIN_110___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__UPC_GAIN_110___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__DA_GAIN_110___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__DA_GAIN_110___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__XPA_GAIN_110___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110__XPA_GAIN_110___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_110___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111 (0x005E5DBC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__IPA_GAIN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__DAC_GAIN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__TX_PWR_LV_LAA_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__TX_PWR_LV_N79_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__BBF_GAIN_111___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__UPC_GAIN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__DA_GAIN_111___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__XPA_GAIN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__IPA_GAIN_111___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__IPA_GAIN_111___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__DAC_GAIN_111___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__DAC_GAIN_111___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__TX_PWR_LV_LAA_111___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__TX_PWR_LV_LAA_111___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__TX_PWR_LV_N79_111___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__TX_PWR_LV_N79_111___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__BBF_GAIN_111___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__BBF_GAIN_111___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__UPC_GAIN_111___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__UPC_GAIN_111___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__DA_GAIN_111___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__DA_GAIN_111___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__XPA_GAIN_111___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111__XPA_GAIN_111___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_111___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112 (0x005E5DC0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__IPA_GAIN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__DAC_GAIN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__TX_PWR_LV_LAA_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__TX_PWR_LV_N79_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__BBF_GAIN_112___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__UPC_GAIN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__DA_GAIN_112___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__XPA_GAIN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__IPA_GAIN_112___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__IPA_GAIN_112___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__DAC_GAIN_112___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__DAC_GAIN_112___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__TX_PWR_LV_LAA_112___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__TX_PWR_LV_LAA_112___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__TX_PWR_LV_N79_112___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__TX_PWR_LV_N79_112___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__BBF_GAIN_112___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__BBF_GAIN_112___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__UPC_GAIN_112___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__UPC_GAIN_112___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__DA_GAIN_112___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__DA_GAIN_112___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__XPA_GAIN_112___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112__XPA_GAIN_112___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_112___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113 (0x005E5DC4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__IPA_GAIN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__DAC_GAIN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__TX_PWR_LV_LAA_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__TX_PWR_LV_N79_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__BBF_GAIN_113___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__UPC_GAIN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__DA_GAIN_113___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__XPA_GAIN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__IPA_GAIN_113___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__IPA_GAIN_113___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__DAC_GAIN_113___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__DAC_GAIN_113___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__TX_PWR_LV_LAA_113___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__TX_PWR_LV_LAA_113___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__TX_PWR_LV_N79_113___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__TX_PWR_LV_N79_113___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__BBF_GAIN_113___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__BBF_GAIN_113___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__UPC_GAIN_113___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__UPC_GAIN_113___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__DA_GAIN_113___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__DA_GAIN_113___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__XPA_GAIN_113___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113__XPA_GAIN_113___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_113___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114 (0x005E5DC8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__IPA_GAIN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__DAC_GAIN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__TX_PWR_LV_LAA_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__TX_PWR_LV_N79_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__BBF_GAIN_114___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__UPC_GAIN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__DA_GAIN_114___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__XPA_GAIN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__IPA_GAIN_114___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__IPA_GAIN_114___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__DAC_GAIN_114___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__DAC_GAIN_114___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__TX_PWR_LV_LAA_114___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__TX_PWR_LV_LAA_114___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__TX_PWR_LV_N79_114___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__TX_PWR_LV_N79_114___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__BBF_GAIN_114___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__BBF_GAIN_114___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__UPC_GAIN_114___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__UPC_GAIN_114___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__DA_GAIN_114___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__DA_GAIN_114___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__XPA_GAIN_114___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114__XPA_GAIN_114___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_114___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115 (0x005E5DCC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__IPA_GAIN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__DAC_GAIN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__TX_PWR_LV_LAA_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__TX_PWR_LV_N79_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__BBF_GAIN_115___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__UPC_GAIN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__DA_GAIN_115___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__XPA_GAIN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__IPA_GAIN_115___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__IPA_GAIN_115___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__DAC_GAIN_115___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__DAC_GAIN_115___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__TX_PWR_LV_LAA_115___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__TX_PWR_LV_LAA_115___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__TX_PWR_LV_N79_115___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__TX_PWR_LV_N79_115___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__BBF_GAIN_115___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__BBF_GAIN_115___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__UPC_GAIN_115___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__UPC_GAIN_115___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__DA_GAIN_115___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__DA_GAIN_115___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__XPA_GAIN_115___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115__XPA_GAIN_115___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_115___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116 (0x005E5DD0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__IPA_GAIN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__DAC_GAIN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__TX_PWR_LV_LAA_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__TX_PWR_LV_N79_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__BBF_GAIN_116___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__UPC_GAIN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__DA_GAIN_116___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__XPA_GAIN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__IPA_GAIN_116___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__IPA_GAIN_116___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__DAC_GAIN_116___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__DAC_GAIN_116___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__TX_PWR_LV_LAA_116___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__TX_PWR_LV_LAA_116___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__TX_PWR_LV_N79_116___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__TX_PWR_LV_N79_116___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__BBF_GAIN_116___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__BBF_GAIN_116___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__UPC_GAIN_116___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__UPC_GAIN_116___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__DA_GAIN_116___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__DA_GAIN_116___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__XPA_GAIN_116___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116__XPA_GAIN_116___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_116___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117 (0x005E5DD4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__IPA_GAIN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__DAC_GAIN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__TX_PWR_LV_LAA_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__TX_PWR_LV_N79_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__BBF_GAIN_117___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__UPC_GAIN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__DA_GAIN_117___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__XPA_GAIN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__IPA_GAIN_117___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__IPA_GAIN_117___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__DAC_GAIN_117___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__DAC_GAIN_117___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__TX_PWR_LV_LAA_117___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__TX_PWR_LV_LAA_117___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__TX_PWR_LV_N79_117___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__TX_PWR_LV_N79_117___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__BBF_GAIN_117___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__BBF_GAIN_117___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__UPC_GAIN_117___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__UPC_GAIN_117___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__DA_GAIN_117___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__DA_GAIN_117___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__XPA_GAIN_117___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117__XPA_GAIN_117___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_117___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118 (0x005E5DD8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__IPA_GAIN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__DAC_GAIN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__TX_PWR_LV_LAA_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__TX_PWR_LV_N79_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__BBF_GAIN_118___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__UPC_GAIN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__DA_GAIN_118___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__XPA_GAIN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__IPA_GAIN_118___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__IPA_GAIN_118___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__DAC_GAIN_118___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__DAC_GAIN_118___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__TX_PWR_LV_LAA_118___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__TX_PWR_LV_LAA_118___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__TX_PWR_LV_N79_118___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__TX_PWR_LV_N79_118___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__BBF_GAIN_118___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__BBF_GAIN_118___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__UPC_GAIN_118___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__UPC_GAIN_118___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__DA_GAIN_118___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__DA_GAIN_118___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__XPA_GAIN_118___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118__XPA_GAIN_118___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_118___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119 (0x005E5DDC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__IPA_GAIN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__DAC_GAIN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__TX_PWR_LV_LAA_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__TX_PWR_LV_N79_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__BBF_GAIN_119___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__UPC_GAIN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__DA_GAIN_119___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__XPA_GAIN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__IPA_GAIN_119___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__IPA_GAIN_119___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__DAC_GAIN_119___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__DAC_GAIN_119___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__TX_PWR_LV_LAA_119___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__TX_PWR_LV_LAA_119___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__TX_PWR_LV_N79_119___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__TX_PWR_LV_N79_119___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__BBF_GAIN_119___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__BBF_GAIN_119___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__UPC_GAIN_119___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__UPC_GAIN_119___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__DA_GAIN_119___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__DA_GAIN_119___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__XPA_GAIN_119___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119__XPA_GAIN_119___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_119___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120 (0x005E5DE0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__IPA_GAIN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__DAC_GAIN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__TX_PWR_LV_LAA_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__TX_PWR_LV_N79_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__BBF_GAIN_120___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__UPC_GAIN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__DA_GAIN_120___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__XPA_GAIN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__IPA_GAIN_120___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__IPA_GAIN_120___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__DAC_GAIN_120___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__DAC_GAIN_120___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__TX_PWR_LV_LAA_120___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__TX_PWR_LV_LAA_120___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__TX_PWR_LV_N79_120___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__TX_PWR_LV_N79_120___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__BBF_GAIN_120___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__BBF_GAIN_120___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__UPC_GAIN_120___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__UPC_GAIN_120___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__DA_GAIN_120___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__DA_GAIN_120___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__XPA_GAIN_120___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120__XPA_GAIN_120___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_120___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121 (0x005E5DE4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__IPA_GAIN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__DAC_GAIN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__TX_PWR_LV_LAA_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__TX_PWR_LV_N79_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__BBF_GAIN_121___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__UPC_GAIN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__DA_GAIN_121___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__XPA_GAIN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__IPA_GAIN_121___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__IPA_GAIN_121___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__DAC_GAIN_121___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__DAC_GAIN_121___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__TX_PWR_LV_LAA_121___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__TX_PWR_LV_LAA_121___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__TX_PWR_LV_N79_121___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__TX_PWR_LV_N79_121___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__BBF_GAIN_121___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__BBF_GAIN_121___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__UPC_GAIN_121___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__UPC_GAIN_121___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__DA_GAIN_121___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__DA_GAIN_121___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__XPA_GAIN_121___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121__XPA_GAIN_121___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_121___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122 (0x005E5DE8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__IPA_GAIN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__DAC_GAIN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__TX_PWR_LV_LAA_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__TX_PWR_LV_N79_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__BBF_GAIN_122___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__UPC_GAIN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__DA_GAIN_122___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__XPA_GAIN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__IPA_GAIN_122___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__IPA_GAIN_122___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__DAC_GAIN_122___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__DAC_GAIN_122___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__TX_PWR_LV_LAA_122___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__TX_PWR_LV_LAA_122___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__TX_PWR_LV_N79_122___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__TX_PWR_LV_N79_122___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__BBF_GAIN_122___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__BBF_GAIN_122___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__UPC_GAIN_122___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__UPC_GAIN_122___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__DA_GAIN_122___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__DA_GAIN_122___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__XPA_GAIN_122___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122__XPA_GAIN_122___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_122___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123 (0x005E5DEC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__IPA_GAIN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__DAC_GAIN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__TX_PWR_LV_LAA_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__TX_PWR_LV_N79_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__BBF_GAIN_123___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__UPC_GAIN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__DA_GAIN_123___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__XPA_GAIN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__IPA_GAIN_123___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__IPA_GAIN_123___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__DAC_GAIN_123___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__DAC_GAIN_123___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__TX_PWR_LV_LAA_123___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__TX_PWR_LV_LAA_123___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__TX_PWR_LV_N79_123___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__TX_PWR_LV_N79_123___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__BBF_GAIN_123___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__BBF_GAIN_123___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__UPC_GAIN_123___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__UPC_GAIN_123___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__DA_GAIN_123___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__DA_GAIN_123___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__XPA_GAIN_123___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123__XPA_GAIN_123___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_123___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124 (0x005E5DF0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__IPA_GAIN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__DAC_GAIN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__TX_PWR_LV_LAA_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__TX_PWR_LV_N79_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__BBF_GAIN_124___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__UPC_GAIN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__DA_GAIN_124___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__XPA_GAIN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__IPA_GAIN_124___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__IPA_GAIN_124___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__DAC_GAIN_124___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__DAC_GAIN_124___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__TX_PWR_LV_LAA_124___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__TX_PWR_LV_LAA_124___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__TX_PWR_LV_N79_124___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__TX_PWR_LV_N79_124___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__BBF_GAIN_124___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__BBF_GAIN_124___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__UPC_GAIN_124___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__UPC_GAIN_124___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__DA_GAIN_124___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__DA_GAIN_124___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__XPA_GAIN_124___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124__XPA_GAIN_124___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_124___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125 (0x005E5DF4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__IPA_GAIN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__DAC_GAIN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__TX_PWR_LV_LAA_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__TX_PWR_LV_N79_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__BBF_GAIN_125___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__UPC_GAIN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__DA_GAIN_125___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__XPA_GAIN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__IPA_GAIN_125___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__IPA_GAIN_125___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__DAC_GAIN_125___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__DAC_GAIN_125___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__TX_PWR_LV_LAA_125___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__TX_PWR_LV_LAA_125___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__TX_PWR_LV_N79_125___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__TX_PWR_LV_N79_125___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__BBF_GAIN_125___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__BBF_GAIN_125___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__UPC_GAIN_125___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__UPC_GAIN_125___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__DA_GAIN_125___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__DA_GAIN_125___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__XPA_GAIN_125___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125__XPA_GAIN_125___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_125___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126 (0x005E5DF8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__IPA_GAIN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__DAC_GAIN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__TX_PWR_LV_LAA_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__TX_PWR_LV_N79_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__BBF_GAIN_126___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__UPC_GAIN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__DA_GAIN_126___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__XPA_GAIN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__IPA_GAIN_126___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__IPA_GAIN_126___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__DAC_GAIN_126___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__DAC_GAIN_126___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__TX_PWR_LV_LAA_126___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__TX_PWR_LV_LAA_126___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__TX_PWR_LV_N79_126___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__TX_PWR_LV_N79_126___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__BBF_GAIN_126___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__BBF_GAIN_126___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__UPC_GAIN_126___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__UPC_GAIN_126___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__DA_GAIN_126___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__DA_GAIN_126___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__XPA_GAIN_126___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126__XPA_GAIN_126___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_126___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127 (0x005E5DFC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__IPA_GAIN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__DAC_GAIN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__TX_PWR_LV_LAA_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__TX_PWR_LV_N79_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__BBF_GAIN_127___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__UPC_GAIN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__DA_GAIN_127___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__XPA_GAIN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__IPA_GAIN_127___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__IPA_GAIN_127___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__DAC_GAIN_127___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__DAC_GAIN_127___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__TX_PWR_LV_LAA_127___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__TX_PWR_LV_LAA_127___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__TX_PWR_LV_N79_127___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__TX_PWR_LV_N79_127___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__BBF_GAIN_127___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__BBF_GAIN_127___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__UPC_GAIN_127___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__UPC_GAIN_127___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__DA_GAIN_127___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__DA_GAIN_127___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__XPA_GAIN_127___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127__XPA_GAIN_127___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH0_TXGAIN_127___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_TESTREG (0x005E8000) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_TESTREG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_TESTREG___POR 0x0000AB80 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_TESTREG__TESTREG___POR 0x0000AB80 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_TESTREG__TESTREG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_TESTREG__TESTREG___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_TESTREG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_TESTREG___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_0 (0x005E8004) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_0__SYN_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_0__SYN_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_0__SYN_EN___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_0___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1 (0x005E8008) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__XPA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__IPA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__INJECT_TXLO_I_OFFSET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__LPBK_TX_CHAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__TX_RESIDUE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__RF_LPBK_PHASE_SHIFT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__CAL_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__XPA_EN_OVS___M 0x00001800 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__XPA_EN_OVS___S 11 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__IPA_EN_OVS___M 0x00000600 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__IPA_EN_OVS___S 9 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__INJECT_TXLO_I_OFFSET___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__INJECT_TXLO_I_OFFSET___S 7 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__LPBK_TX_CHAIN___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__LPBK_TX_CHAIN___S 6 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__TX_RESIDUE___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__TX_RESIDUE___S 5 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__RF_LPBK_PHASE_SHIFT___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__RF_LPBK_PHASE_SHIFT___S 4 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__CAL_MODE___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1__CAL_MODE___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_0 (0x005E800C) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_0___POR 0x00000010 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_0__TRSW_EN_RXGAIN_CAL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_0__TRSW_EN_DPD___POR 0x1 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_0__CAL_SUB_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_0__TRSW_EN_RXGAIN_CAL___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_0__TRSW_EN_RXGAIN_CAL___S 5 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_0__TRSW_EN_DPD___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_0__TRSW_EN_DPD___S 4 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_0__CAL_SUB_MODE___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_0__CAL_SUB_MODE___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_0___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_1 (0x005E8010) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_1___POR 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_1__FCS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_1__LP_RX_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_1__CLPC_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_1__FCS___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_1__FCS___S 2 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_1__LP_RX_EN___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_1__LP_RX_EN___S 1 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_1__CLPC_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_1__CLPC_EN___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_1___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2 (0x005E8014) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2___POR 0x0000C001 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__PMM_SYN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_CORE_RX_GAIN_ON___POR 0x1 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_CORE_RX_DCOC_ON___POR 0x1 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_CORE_TX_GAIN_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_CORE_TX_DCOC_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_PERIPH_RX_GAIN_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_PERIPH_RX_DCOC_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_PERIPH_TX_GAIN_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_PERIPH_TX_DCOC_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__RXIQ_CROSS_CHAIN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__PMM_SYN_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__PMM_SYN_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_CORE_RX_GAIN_ON___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_CORE_RX_GAIN_ON___S 15 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_CORE_RX_DCOC_ON___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_CORE_RX_DCOC_ON___S 14 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_CORE_TX_GAIN_ON___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_CORE_TX_GAIN_ON___S 13 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_CORE_TX_DCOC_ON___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_CORE_TX_DCOC_ON___S 12 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_PERIPH_RX_GAIN_ON___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_PERIPH_RX_GAIN_ON___S 11 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_PERIPH_RX_DCOC_ON___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_PERIPH_RX_DCOC_ON___S 10 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_PERIPH_TX_GAIN_ON___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_PERIPH_TX_GAIN_ON___S 9 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_PERIPH_TX_DCOC_ON___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__FORCE_PERIPH_TX_DCOC_ON___S 8 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__RXIQ_CROSS_CHAIN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2__RXIQ_CROSS_CHAIN___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2___M 0xC000FF01 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MODE_SEL_2___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_BBSAT_0 (0x005E8018) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_BBSAT_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_BBSAT_0___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_BBSAT_0__AGC_BBSAT_RESET_PERIOD___POR 0x14 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_BBSAT_0__AGC_BBSAT_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_BBSAT_0__AGC_BBSAT_FLAG_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_BBSAT_0__RX_SATDET_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_BBSAT_0__AGC_BBSAT_RESET_PERIOD___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_BBSAT_0__AGC_BBSAT_RESET_PERIOD___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_BBSAT_0__AGC_BBSAT_MODE___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_BBSAT_0__AGC_BBSAT_MODE___S 25 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_BBSAT_0__AGC_BBSAT_FLAG_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_BBSAT_0__AGC_BBSAT_FLAG_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_BBSAT_0__RX_SATDET_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_BBSAT_0__RX_SATDET_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_BBSAT_0___M 0xFECC0000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_BBSAT_0___S 18 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0 (0x005E801C) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0__AGC_PKDET_RESET_PERIOD___POR 0x14 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0__AGC_PKDET_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0__AGC_PKDET_FLAG_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0__AGC_EN_BY_RX_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0__AGC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0__AGC_PKDET_RESET_PERIOD___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0__AGC_PKDET_RESET_PERIOD___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0__AGC_PKDET_MODE___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0__AGC_PKDET_MODE___S 25 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0__AGC_PKDET_FLAG_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0__AGC_PKDET_FLAG_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0__AGC_EN_BY_RX_EN___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0__AGC_EN_BY_RX_EN___S 20 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0__AGC_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0__AGC_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0___M 0xFEDC0000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PKDET_0___S 18 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_PKDET (0x005E8020) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_PKDET___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_PKDET___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_PKDET__RO_AGC_PKDET_FLAG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_PKDET__RO_AGC_BBSAT_FLAG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_PKDET__RO_AGC_PKDET_FLAG___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_PKDET__RO_AGC_PKDET_FLAG___S 1 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_PKDET__RO_AGC_BBSAT_FLAG___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_PKDET__RO_AGC_BBSAT_FLAG___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_PKDET___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_PKDET___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0 (0x005E8024) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0___POR 0x06769292 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T0_START_PRD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T0_END_PRD___POR 0x6 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T1_START_PRD___POR 0x7 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T1_END_PRD___POR 0x6 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T2_START_PRD___POR 0x9 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T2_END_PRD___POR 0x2 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T3_START_PRD___POR 0x9 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T3_END_PRD___POR 0x2 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T0_START_PRD___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T0_START_PRD___S 28 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T0_END_PRD___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T0_END_PRD___S 24 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T1_START_PRD___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T1_START_PRD___S 20 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T1_END_PRD___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T1_END_PRD___S 16 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T2_START_PRD___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T2_START_PRD___S 12 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T2_END_PRD___M 0x00000F00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T2_END_PRD___S 8 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T3_START_PRD___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T3_START_PRD___S 4 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T3_END_PRD___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0__TX_T3_END_PRD___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_STAGGER_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0 (0x005E8028) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0___POR 0x00004142 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T0_START_PRD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T0_END_PRD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T1_START_PRD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T1_END_PRD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T2_START_PRD___POR 0x4 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T2_END_PRD___POR 0x1 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T3_START_PRD___POR 0x4 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T3_END_PRD___POR 0x2 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T0_START_PRD___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T0_START_PRD___S 28 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T0_END_PRD___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T0_END_PRD___S 24 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T1_START_PRD___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T1_START_PRD___S 20 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T1_END_PRD___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T1_END_PRD___S 16 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T2_START_PRD___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T2_START_PRD___S 12 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T2_END_PRD___M 0x00000F00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T2_END_PRD___S 8 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T3_START_PRD___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T3_START_PRD___S 4 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T3_END_PRD___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0__RX_T3_END_PRD___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_STAGGER_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_TIMER_0 (0x005E802C) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_TIMER_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_TIMER_0___POR 0x20000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_TIMER_0__LNA_FC_PRD___POR 0x1 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_TIMER_0__LNA_FC_PRD___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_TIMER_0__LNA_FC_PRD___S 29 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_TIMER_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_TIMER_0___S 29 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_XFEM_0 (0x005E8030) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_XFEM_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_XFEM_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_XFEM_0__ZZZ_SPARE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_XFEM_0__ZZZ_SPARE___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_XFEM_0__ZZZ_SPARE___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_XFEM_0___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_XFEM_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_SPARE_0 (0x005E8034) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_SPARE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_SPARE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_SPARE_0__D_CHAIN_SPARE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_SPARE_0__D_CHAIN_SPARE_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_SPARE_0__D_CHAIN_SPARE_0___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_SPARE_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_SPARE_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_SPARE_1 (0x005E8038) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_SPARE_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_SPARE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_SPARE_1__D_CHAIN_SPARE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_SPARE_1__D_CHAIN_SPARE_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_SPARE_1__D_CHAIN_SPARE_1___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_SPARE_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_SPARE_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_COEX_GAIN_CFG (0x005E803C) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_COEX_GAIN_CFG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_COEX_GAIN_CFG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_COEX_GAIN_CFG__COEX_LNA_GAIN_FREEZE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_COEX_GAIN_CFG__COEX_LNA_GAIN_FREEZE___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_COEX_GAIN_CFG__COEX_LNA_GAIN_FREEZE___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_COEX_GAIN_CFG___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_COEX_GAIN_CFG___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_2 (0x005E8040) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_2__COEX_XLNA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_2__COEX_LNA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_2__COEX_XLNA_GAIN___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_2__COEX_XLNA_GAIN___S 3 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_2__COEX_LNA_GAIN___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_2__COEX_LNA_GAIN___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_2___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_PHY_2___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0 (0x005E8044) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0___POR 0x09200000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__WL_ISEL_IC___POR 0x4 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__WL_ISEL_IR___POR 0x4 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__WL_ISEL_ICPT___POR 0x4 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__D_IC_25U_TEST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__D_IR_25U_TEST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__D_ICPT_25U_TEST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__WL_ISEL_IC___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__WL_ISEL_IC___S 25 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__WL_ISEL_IR___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__WL_ISEL_IR___S 22 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__WL_ISEL_ICPT___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__WL_ISEL_ICPT___S 19 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__D_IC_25U_TEST_EN___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__D_IC_25U_TEST_EN___S 2 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__D_IR_25U_TEST_EN___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__D_IR_25U_TEST_EN___S 1 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__D_ICPT_25U_TEST_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0__D_ICPT_25U_TEST_EN___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0___M 0x0FF80007 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_MC_ISEL_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_ADC_ATEST (0x005E8048) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_ADC_ATEST___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_ADC_ATEST___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_ADC_ATEST__D_ATEST_EN_ADC_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_ADC_ATEST__D_ATEST_EN_ADC_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_ADC_ATEST__D_ATEST_EN_ADC_I___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_ADC_ATEST__D_ATEST_EN_ADC_I___S 1 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_ADC_ATEST__D_ATEST_EN_ADC_Q___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_ADC_ATEST__D_ATEST_EN_ADC_Q___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_ADC_ATEST___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_ADC_ATEST___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_0 (0x005E8080) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_0___POR 0x005078A0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_REGULAR___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_LG___POR 0x50 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_VLG___POR 0x78 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_COEX___POR 0xA0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_REGULAR___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_REGULAR___S 24 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_LG___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_LG___S 16 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_VLG___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_VLG___S 8 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_COEX___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_COEX___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1 (0x005E8084) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1___POR 0xC8F00000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_DPD___POR 0xC8 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_RXDCCAL___POR 0xF0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_SEL_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__TX_GAIN_LUT_SEL_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_DPD___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_DPD___S 24 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_RXDCCAL___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_RXDCCAL___S 16 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_SEL_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__RX_GAIN_LUT_SEL_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OV___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OV___S 7 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OVD___M 0x00000060 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OVD___S 5 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__TX_GAIN_LUT_SEL_OVS___M 0x00000018 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__TX_GAIN_LUT_SEL_OVS___S 3 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OV___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OV___S 2 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OVD___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1___M 0xFFFF03FF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RXGC_BASE_ADDR_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_GC_RAM_CONTROL (0x005E8088) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_GC_RAM_CONTROL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_GC_RAM_CONTROL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_GC_RAM_CONTROL__GC_MEM_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_GC_RAM_CONTROL__RXDCCAL_GAIN_TBL_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_GC_RAM_CONTROL__GC_MEM_SEL___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_GC_RAM_CONTROL__GC_MEM_SEL___S 15 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_GC_RAM_CONTROL__RXDCCAL_GAIN_TBL_SEL___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_GC_RAM_CONTROL__RXDCCAL_GAIN_TBL_SEL___S 14 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_GC_RAM_CONTROL___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_GC_RAM_CONTROL___S 14 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0 (0x005E808C) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__SLM_XLNA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__XLNA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__LNA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__GM_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__TIA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__BQ_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__SLM_XLNA_GAIN_OV___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__SLM_XLNA_GAIN_OV___S 5 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__XLNA_GAIN_OV___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__XLNA_GAIN_OV___S 4 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__LNA_GAIN_OV___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__LNA_GAIN_OV___S 3 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__GM_GAIN_OV___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__GM_GAIN_OV___S 2 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__TIA_GAIN_OV___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__TIA_GAIN_OV___S 1 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__BQ_GAIN_OV___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0__BQ_GAIN_OV___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1 (0x005E8090) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__XLNA_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__LNA_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__GM_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__TIA_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__SLM_XLNA_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__BQ_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__XLNA_GAIN_OVD___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__XLNA_GAIN_OVD___S 15 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__LNA_GAIN_OVD___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__LNA_GAIN_OVD___S 12 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__GM_GAIN_OVD___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__GM_GAIN_OVD___S 9 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__TIA_GAIN_OVD___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__TIA_GAIN_OVD___S 7 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__SLM_XLNA_GAIN_OVD___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__SLM_XLNA_GAIN_OVD___S 5 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__BQ_GAIN_OVD___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1__BQ_GAIN_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1___M 0x0000FFBF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_GAIN_OV_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0 (0x005E8094) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_I_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_Q_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_I_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_Q_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OV___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OV___S 25 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OV___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OV___S 24 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_I_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_I_OV___S 23 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_Q_OV___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_Q_OV___S 22 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OVD___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OVD___S 20 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OVD___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OVD___S 18 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_I_OVD___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_I_OVD___S 9 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_Q_OVD___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0__RX_DCOC_RES_Q_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RX_DCOC_OV_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0 (0x005E8098) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__IPA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__DAC_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__TX_PWR_LV_LAA_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__TX_PWR_LV_N79_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__BBF_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__UPC_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__DA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__XPA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__IPA_GAIN_OV___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__IPA_GAIN_OV___S 7 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__DAC_GAIN_OV___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__DAC_GAIN_OV___S 6 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__TX_PWR_LV_LAA_OV___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__TX_PWR_LV_LAA_OV___S 5 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__TX_PWR_LV_N79_OV___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__TX_PWR_LV_N79_OV___S 4 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__BBF_GAIN_OV___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__BBF_GAIN_OV___S 3 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__UPC_GAIN_OV___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__UPC_GAIN_OV___S 2 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__DA_GAIN_OV___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__DA_GAIN_OV___S 1 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__XPA_GAIN_OV___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0__XPA_GAIN_OV___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1 (0x005E809C) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__IPA_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__DAC_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__TX_PWR_LV_LAA_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__TX_PWR_LV_N79_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__BBF_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__UPC_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__DA_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__XPA_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__IPA_GAIN_OVD___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__IPA_GAIN_OVD___S 23 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__DAC_GAIN_OVD___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__DAC_GAIN_OVD___S 20 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__TX_PWR_LV_LAA_OVD___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__TX_PWR_LV_LAA_OVD___S 19 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__TX_PWR_LV_N79_OVD___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__TX_PWR_LV_N79_OVD___S 18 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__BBF_GAIN_OVD___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__BBF_GAIN_OVD___S 12 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__UPC_GAIN_OVD___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__UPC_GAIN_OVD___S 9 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__DA_GAIN_OVD___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__DA_GAIN_OVD___S 4 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__XPA_GAIN_OVD___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1__XPA_GAIN_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_GAIN_OV_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0 (0x005E80A0) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_I_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_Q_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_I_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_Q_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_I_OV___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_I_OV___S 19 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_Q_OV___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_Q_OV___S 18 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_I_OVD___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_I_OVD___S 7 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_Q_OVD___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0__TX_DCOC_RES_Q_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0___M 0x000C3FFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_TX_DCOC_OV_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_IM2_0 (0x005E80A4) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_IM2_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_IM2_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_IM2_0__IM2_EN_MC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_IM2_0__IM2_EN_MC_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_IM2_0__IM2_EN_MC_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_IM2_0___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_IM2_0___S 30 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC (0x005E80A8) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC__RO_RX_DCOC_ADDR___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC__RO_RX_DCOC_RANGE_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC__RO_RX_DCOC_RANGE_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC__RO_RX_DCOC_RES_I___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC__RO_RX_DCOC_RES_Q___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC__RO_RX_DCOC_ADDR___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC__RO_RX_DCOC_ADDR___S 22 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC__RO_RX_DCOC_RANGE_I___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC__RO_RX_DCOC_RANGE_I___S 20 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC__RO_RX_DCOC_RANGE_Q___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC__RO_RX_DCOC_RANGE_Q___S 18 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC__RO_RX_DCOC_RES_I___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC__RO_RX_DCOC_RES_I___S 9 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC__RO_RX_DCOC_RES_Q___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC__RO_RX_DCOC_RES_Q___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_DCOC___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_DCOC (0x005E80AC) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_DCOC___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_DCOC___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_DCOC__RO_TX_DCOC_ADDR___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_DCOC__RO_TX_DCOC_RES_I___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_DCOC__RO_TX_DCOC_RES_Q___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_DCOC__RO_TX_DCOC_ADDR___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_DCOC__RO_TX_DCOC_ADDR___S 16 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_DCOC__RO_TX_DCOC_RES_I___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_DCOC__RO_TX_DCOC_RES_I___S 7 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_DCOC__RO_TX_DCOC_RES_Q___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_DCOC__RO_TX_DCOC_RES_Q___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_DCOC___M 0x007F3FFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_DCOC___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN (0x005E80B0) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_RX_GAIN_ADDR___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_XLNA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_LNA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_GM_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_TIA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_SLM_XLNA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_BQ_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_RX_GAIN_ADDR___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_RX_GAIN_ADDR___S 16 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_XLNA_GAIN___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_XLNA_GAIN___S 15 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_LNA_GAIN___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_LNA_GAIN___S 12 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_GM_GAIN___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_GM_GAIN___S 9 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_TIA_GAIN___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_TIA_GAIN___S 7 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_SLM_XLNA_GAIN___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_SLM_XLNA_GAIN___S 5 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_BQ_GAIN___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN__RO_BQ_GAIN___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN___M 0x00FFFFBF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_RX_GAIN___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0 (0x005E80B4) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_IPA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_DAC_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_TX_PWR_LV_LAA___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_TX_PWR_LV_N79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_BBF_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_UPC_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_DA_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_XPA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_IPA_GAIN___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_IPA_GAIN___S 23 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_DAC_GAIN___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_DAC_GAIN___S 20 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_TX_PWR_LV_LAA___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_TX_PWR_LV_LAA___S 19 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_TX_PWR_LV_N79___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_TX_PWR_LV_N79___S 18 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_BBF_GAIN___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_BBF_GAIN___S 12 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_UPC_GAIN___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_UPC_GAIN___S 9 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_DA_GAIN___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_DA_GAIN___S 4 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_XPA_GAIN___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0__RO_XPA_GAIN___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_1 (0x005E80B8) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_1__RO_TX_GAIN_ADDR___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_1__RO_RX_IDX___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_1__RO_TX_IDX___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_1__RO_TX_GAIN_ADDR___M 0x7F000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_1__RO_TX_GAIN_ADDR___S 24 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_1__RO_RX_IDX___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_1__RO_RX_IDX___S 16 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_1__RO_TX_IDX___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_1__RO_TX_IDX___S 8 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_1___M 0x7FFF3F00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_RO_TX_GAIN_1___S 8 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_0 (0x005E80C0) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_0__TX_DCOC_CAL_OFFSET_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_0__TX_DCOC_CAL_OFFSET_0___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_0__TX_DCOC_CAL_OFFSET_0___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_0___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_0___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_1 (0x005E80C4) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_1__TX_DCOC_CAL_OFFSET_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_1__TX_DCOC_CAL_OFFSET_1___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_1__TX_DCOC_CAL_OFFSET_1___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_1___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_1___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_2 (0x005E80C8) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_2__TX_DCOC_CAL_OFFSET_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_2__TX_DCOC_CAL_OFFSET_2___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_2__TX_DCOC_CAL_OFFSET_2___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_2___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_2___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_3 (0x005E80CC) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_3__TX_DCOC_CAL_OFFSET_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_3__TX_DCOC_CAL_OFFSET_3___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_3__TX_DCOC_CAL_OFFSET_3___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_3___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_3___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_4 (0x005E80D0) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_4__TX_DCOC_CAL_OFFSET_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_4__TX_DCOC_CAL_OFFSET_4___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_4__TX_DCOC_CAL_OFFSET_4___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_4___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_4___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_5 (0x005E80D4) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_5__TX_DCOC_CAL_OFFSET_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_5__TX_DCOC_CAL_OFFSET_5___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_5__TX_DCOC_CAL_OFFSET_5___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_5___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_5___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_6 (0x005E80D8) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_6__TX_DCOC_CAL_OFFSET_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_6__TX_DCOC_CAL_OFFSET_6___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_6__TX_DCOC_CAL_OFFSET_6___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_6___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_6___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_7 (0x005E80DC) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_7__TX_DCOC_CAL_OFFSET_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_7__TX_DCOC_CAL_OFFSET_7___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_7__TX_DCOC_CAL_OFFSET_7___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_7___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_7___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_8 (0x005E80E0) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_8__TX_DCOC_CAL_OFFSET_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_8__TX_DCOC_CAL_OFFSET_8___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_8__TX_DCOC_CAL_OFFSET_8___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_8___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_8___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_9 (0x005E80E4) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_9__TX_DCOC_CAL_OFFSET_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_9__TX_DCOC_CAL_OFFSET_9___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_9__TX_DCOC_CAL_OFFSET_9___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_9___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_9___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_10 (0x005E80E8) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_10__TX_DCOC_CAL_OFFSET_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_10__TX_DCOC_CAL_OFFSET_10___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_10__TX_DCOC_CAL_OFFSET_10___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_10___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_10___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_11 (0x005E80EC) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_11__TX_DCOC_CAL_OFFSET_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_11__TX_DCOC_CAL_OFFSET_11___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_11__TX_DCOC_CAL_OFFSET_11___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_11___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_11___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_12 (0x005E80F0) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_12__TX_DCOC_CAL_OFFSET_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_12__TX_DCOC_CAL_OFFSET_12___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_12__TX_DCOC_CAL_OFFSET_12___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_12___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_12___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_13 (0x005E80F4) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_13__TX_DCOC_CAL_OFFSET_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_13__TX_DCOC_CAL_OFFSET_13___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_13__TX_DCOC_CAL_OFFSET_13___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_13___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_13___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_14 (0x005E80F8) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_14__TX_DCOC_CAL_OFFSET_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_14__TX_DCOC_CAL_OFFSET_14___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_14__TX_DCOC_CAL_OFFSET_14___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_14___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_14___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_15 (0x005E80FC) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_15__TX_DCOC_CAL_OFFSET_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_15__TX_DCOC_CAL_OFFSET_15___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_15__TX_DCOC_CAL_OFFSET_15___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_15___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_15___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_16 (0x005E8100) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_16___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_16__TX_DCOC_CAL_OFFSET_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_16__TX_DCOC_CAL_OFFSET_16___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_16__TX_DCOC_CAL_OFFSET_16___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_16___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_16___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_17 (0x005E8104) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_17___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_17__TX_DCOC_CAL_OFFSET_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_17__TX_DCOC_CAL_OFFSET_17___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_17__TX_DCOC_CAL_OFFSET_17___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_17___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_17___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_18 (0x005E8108) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_18___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_18__TX_DCOC_CAL_OFFSET_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_18__TX_DCOC_CAL_OFFSET_18___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_18__TX_DCOC_CAL_OFFSET_18___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_18___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_18___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_19 (0x005E810C) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_19___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_19__TX_DCOC_CAL_OFFSET_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_19__TX_DCOC_CAL_OFFSET_19___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_19__TX_DCOC_CAL_OFFSET_19___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_19___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_19___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_20 (0x005E8110) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_20___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_20__TX_DCOC_CAL_OFFSET_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_20__TX_DCOC_CAL_OFFSET_20___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_20__TX_DCOC_CAL_OFFSET_20___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_20___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_20___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_21 (0x005E8114) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_21___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_21__TX_DCOC_CAL_OFFSET_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_21__TX_DCOC_CAL_OFFSET_21___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_21__TX_DCOC_CAL_OFFSET_21___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_21___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_21___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_22 (0x005E8118) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_22___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_22__TX_DCOC_CAL_OFFSET_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_22__TX_DCOC_CAL_OFFSET_22___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_22__TX_DCOC_CAL_OFFSET_22___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_22___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_22___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_23 (0x005E811C) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_23___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_23__TX_DCOC_CAL_OFFSET_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_23__TX_DCOC_CAL_OFFSET_23___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_23__TX_DCOC_CAL_OFFSET_23___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_23___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_23___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_24 (0x005E8120) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_24___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_24__TX_DCOC_CAL_OFFSET_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_24__TX_DCOC_CAL_OFFSET_24___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_24__TX_DCOC_CAL_OFFSET_24___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_24___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_24___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_25 (0x005E8124) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_25___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_25__TX_DCOC_CAL_OFFSET_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_25__TX_DCOC_CAL_OFFSET_25___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_25__TX_DCOC_CAL_OFFSET_25___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_25___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_25___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_26 (0x005E8128) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_26___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_26__TX_DCOC_CAL_OFFSET_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_26__TX_DCOC_CAL_OFFSET_26___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_26__TX_DCOC_CAL_OFFSET_26___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_26___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_26___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_27 (0x005E812C) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_27___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_27__TX_DCOC_CAL_OFFSET_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_27__TX_DCOC_CAL_OFFSET_27___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_27__TX_DCOC_CAL_OFFSET_27___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_27___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_27___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_28 (0x005E8130) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_28___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_28__TX_DCOC_CAL_OFFSET_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_28__TX_DCOC_CAL_OFFSET_28___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_28__TX_DCOC_CAL_OFFSET_28___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_28___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_28___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_29 (0x005E8134) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_29___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_29__TX_DCOC_CAL_OFFSET_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_29__TX_DCOC_CAL_OFFSET_29___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_29__TX_DCOC_CAL_OFFSET_29___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_29___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_29___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_30 (0x005E8138) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_30___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_30__TX_DCOC_CAL_OFFSET_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_30__TX_DCOC_CAL_OFFSET_30___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_30__TX_DCOC_CAL_OFFSET_30___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_30___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_30___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_31 (0x005E813C) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_31___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_31__TX_DCOC_CAL_OFFSET_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_31__TX_DCOC_CAL_OFFSET_31___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_31__TX_DCOC_CAL_OFFSET_31___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_31___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_31___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_32 (0x005E8140) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_32___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_32___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_32__TX_DCOC_CAL_OFFSET_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_32__TX_DCOC_CAL_OFFSET_32___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_32__TX_DCOC_CAL_OFFSET_32___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_32___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_32___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_33 (0x005E8144) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_33___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_33___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_33__TX_DCOC_CAL_OFFSET_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_33__TX_DCOC_CAL_OFFSET_33___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_33__TX_DCOC_CAL_OFFSET_33___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_33___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_33___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_34 (0x005E8148) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_34___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_34___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_34__TX_DCOC_CAL_OFFSET_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_34__TX_DCOC_CAL_OFFSET_34___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_34__TX_DCOC_CAL_OFFSET_34___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_34___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_34___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_35 (0x005E814C) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_35___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_35___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_35__TX_DCOC_CAL_OFFSET_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_35__TX_DCOC_CAL_OFFSET_35___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_35__TX_DCOC_CAL_OFFSET_35___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_35___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_35___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_36 (0x005E8150) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_36___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_36___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_36__TX_DCOC_CAL_OFFSET_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_36__TX_DCOC_CAL_OFFSET_36___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_36__TX_DCOC_CAL_OFFSET_36___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_36___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_36___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_37 (0x005E8154) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_37___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_37___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_37__TX_DCOC_CAL_OFFSET_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_37__TX_DCOC_CAL_OFFSET_37___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_37__TX_DCOC_CAL_OFFSET_37___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_37___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_37___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_38 (0x005E8158) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_38___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_38___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_38__TX_DCOC_CAL_OFFSET_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_38__TX_DCOC_CAL_OFFSET_38___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_38__TX_DCOC_CAL_OFFSET_38___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_38___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_38___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_39 (0x005E815C) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_39___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_39___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_39__TX_DCOC_CAL_OFFSET_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_39__TX_DCOC_CAL_OFFSET_39___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_39__TX_DCOC_CAL_OFFSET_39___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_39___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_39___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_40 (0x005E8160) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_40___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_40___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_40__TX_DCOC_CAL_OFFSET_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_40__TX_DCOC_CAL_OFFSET_40___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_40__TX_DCOC_CAL_OFFSET_40___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_40___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_40___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_41 (0x005E8164) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_41___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_41___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_41__TX_DCOC_CAL_OFFSET_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_41__TX_DCOC_CAL_OFFSET_41___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_41__TX_DCOC_CAL_OFFSET_41___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_41___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_41___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_42 (0x005E8168) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_42___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_42___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_42__TX_DCOC_CAL_OFFSET_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_42__TX_DCOC_CAL_OFFSET_42___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_42__TX_DCOC_CAL_OFFSET_42___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_42___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_42___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_43 (0x005E816C) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_43___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_43___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_43__TX_DCOC_CAL_OFFSET_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_43__TX_DCOC_CAL_OFFSET_43___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_43__TX_DCOC_CAL_OFFSET_43___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_43___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_43___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_44 (0x005E8170) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_44___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_44___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_44__TX_DCOC_CAL_OFFSET_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_44__TX_DCOC_CAL_OFFSET_44___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_44__TX_DCOC_CAL_OFFSET_44___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_44___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_44___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_45 (0x005E8174) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_45___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_45___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_45__TX_DCOC_CAL_OFFSET_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_45__TX_DCOC_CAL_OFFSET_45___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_45__TX_DCOC_CAL_OFFSET_45___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_45___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_45___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_46 (0x005E8178) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_46___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_46___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_46__TX_DCOC_CAL_OFFSET_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_46__TX_DCOC_CAL_OFFSET_46___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_46__TX_DCOC_CAL_OFFSET_46___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_46___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_46___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_47 (0x005E817C) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_47___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_47___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_47__TX_DCOC_CAL_OFFSET_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_47__TX_DCOC_CAL_OFFSET_47___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_47__TX_DCOC_CAL_OFFSET_47___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_47___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_47___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_48 (0x005E8180) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_48___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_48___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_48__TX_DCOC_CAL_OFFSET_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_48__TX_DCOC_CAL_OFFSET_48___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_48__TX_DCOC_CAL_OFFSET_48___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_48___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_48___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_49 (0x005E8184) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_49___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_49___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_49__TX_DCOC_CAL_OFFSET_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_49__TX_DCOC_CAL_OFFSET_49___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_49__TX_DCOC_CAL_OFFSET_49___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_49___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_49___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_50 (0x005E8188) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_50___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_50___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_50__TX_DCOC_CAL_OFFSET_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_50__TX_DCOC_CAL_OFFSET_50___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_50__TX_DCOC_CAL_OFFSET_50___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_50___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_50___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_51 (0x005E818C) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_51___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_51___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_51__TX_DCOC_CAL_OFFSET_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_51__TX_DCOC_CAL_OFFSET_51___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_51__TX_DCOC_CAL_OFFSET_51___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_51___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_51___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_52 (0x005E8190) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_52___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_52___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_52__TX_DCOC_CAL_OFFSET_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_52__TX_DCOC_CAL_OFFSET_52___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_52__TX_DCOC_CAL_OFFSET_52___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_52___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_52___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_53 (0x005E8194) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_53___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_53___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_53__TX_DCOC_CAL_OFFSET_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_53__TX_DCOC_CAL_OFFSET_53___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_53__TX_DCOC_CAL_OFFSET_53___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_53___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_53___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_54 (0x005E8198) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_54___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_54___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_54__TX_DCOC_CAL_OFFSET_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_54__TX_DCOC_CAL_OFFSET_54___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_54__TX_DCOC_CAL_OFFSET_54___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_54___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_54___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_55 (0x005E819C) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_55___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_55___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_55__TX_DCOC_CAL_OFFSET_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_55__TX_DCOC_CAL_OFFSET_55___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_55__TX_DCOC_CAL_OFFSET_55___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_55___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_55___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_56 (0x005E81A0) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_56___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_56___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_56__TX_DCOC_CAL_OFFSET_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_56__TX_DCOC_CAL_OFFSET_56___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_56__TX_DCOC_CAL_OFFSET_56___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_56___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_56___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_57 (0x005E81A4) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_57___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_57___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_57__TX_DCOC_CAL_OFFSET_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_57__TX_DCOC_CAL_OFFSET_57___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_57__TX_DCOC_CAL_OFFSET_57___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_57___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_57___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_58 (0x005E81A8) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_58___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_58___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_58__TX_DCOC_CAL_OFFSET_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_58__TX_DCOC_CAL_OFFSET_58___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_58__TX_DCOC_CAL_OFFSET_58___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_58___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_58___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_59 (0x005E81AC) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_59___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_59___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_59__TX_DCOC_CAL_OFFSET_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_59__TX_DCOC_CAL_OFFSET_59___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_59__TX_DCOC_CAL_OFFSET_59___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_59___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_59___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_60 (0x005E81B0) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_60___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_60___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_60__TX_DCOC_CAL_OFFSET_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_60__TX_DCOC_CAL_OFFSET_60___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_60__TX_DCOC_CAL_OFFSET_60___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_60___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_60___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_61 (0x005E81B4) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_61___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_61___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_61__TX_DCOC_CAL_OFFSET_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_61__TX_DCOC_CAL_OFFSET_61___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_61__TX_DCOC_CAL_OFFSET_61___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_61___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_61___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_62 (0x005E81B8) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_62___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_62___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_62__TX_DCOC_CAL_OFFSET_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_62__TX_DCOC_CAL_OFFSET_62___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_62__TX_DCOC_CAL_OFFSET_62___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_62___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_62___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_63 (0x005E81BC) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_63___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_63___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_63__TX_DCOC_CAL_OFFSET_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_63__TX_DCOC_CAL_OFFSET_63___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_63__TX_DCOC_CAL_OFFSET_63___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_63___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH0_LUT_63___S 26 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL (0x005E8400) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL__TIA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL__TIA_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL__BQ_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL__BQ_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL__TIA_GAIN_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL__TIA_GAIN_OV___S 31 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL__TIA_GAIN_OVD___M 0x60000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL__TIA_GAIN_OVD___S 29 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL__BQ_GAIN_OV___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL__BQ_GAIN_OV___S 28 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL__BQ_GAIN_OVD___M 0x0F800000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL__BQ_GAIN_OVD___S 23 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_LUT_IDX_SEL___S 23 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB_CFG (0x005E8404) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB_CFG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB_CFG___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB_CFG__DCOCBB_FORMAT___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB_CFG__DCOCBB_FORMAT___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB_CFG__DCOCBB_FORMAT___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB_CFG___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB_CFG___S 30 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB (0x005E8408) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RANGE_I_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RANGE_Q_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RES_I_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RES_Q_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RANGE_I_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RANGE_Q_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RES_I_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RES_Q_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RANGE_I_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RANGE_I_OV___S 31 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RANGE_Q_OV___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RANGE_Q_OV___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RES_I_OV___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RES_I_OV___S 29 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RES_Q_OV___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RES_Q_OV___S 28 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RANGE_I_OVD___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RANGE_I_OVD___S 26 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RANGE_Q_OVD___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RANGE_Q_OVD___S 24 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RES_I_OVD___M 0x00FF8000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RES_I_OVD___S 15 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RES_Q_OVD___M 0x00007FC0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB__DCOCBB_RES_Q_OVD___S 6 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB___M 0xFFFFFFC0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DCOCBB___S 6 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC (0x005E840C) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC___POR 0x92492400 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_TIA_BW___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_BW___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_CC1ADJ___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_CC2ADJ___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_ZR1___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_ZR2___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_SELQ___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BOOST_BQ___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_TIA_BW___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_TIA_BW___S 29 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_BW___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_BW___S 26 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_CC1ADJ___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_CC1ADJ___S 23 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_CC2ADJ___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_CC2ADJ___S 20 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_ZR1___M 0x000E0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_ZR1___S 17 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_ZR2___M 0x0001C000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_ZR2___S 14 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_SELQ___M 0x00003800 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BQ_SELQ___S 11 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BOOST_BQ___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC__D_BOOST_BQ___S 10 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_CH_BW_AC___S 10 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0 (0x005E8410) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0___POR 0x87CCD234 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_CCADJ0___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_CFBCAL_0___POR 0x03E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_ICQADJ0___POR 0x6 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_VCMINTADJ0___POR 0x6 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_ISEL_IR25_IP0___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_ISEL_IC25_OP0___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_ISEL_OP_OS0___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_ISEL_IPTAT25_OP0___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_CCADJ0___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_CCADJ0___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_CFBCAL_0___M 0x3FE00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_CFBCAL_0___S 21 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_ICQADJ0___M 0x001E0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_ICQADJ0___S 17 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_VCMINTADJ0___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_VCMINTADJ0___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_ISEL_IR25_IP0___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_ISEL_IR25_IP0___S 10 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_ISEL_IC25_OP0___M 0x00000380 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_ISEL_IC25_OP0___S 7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_ISEL_OP_OS0___M 0x00000070 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_ISEL_OP_OS0___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_ISEL_IPTAT25_OP0___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0__TIA_ISEL_IPTAT25_OP0___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_0___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1 (0x005E8414) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1___POR 0x07CCD234 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_CCADJ1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_CFBCAL_1___POR 0x03E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_ICQADJ1___POR 0x6 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_VCMINTADJ1___POR 0x6 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_ISEL_IR25_IP1___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_ISEL_IC25_OP1___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_ISEL_OP_OS1___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_ISEL_IPTAT25_OP1___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_CCADJ1___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_CCADJ1___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_CFBCAL_1___M 0x3FE00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_CFBCAL_1___S 21 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_ICQADJ1___M 0x001E0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_ICQADJ1___S 17 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_VCMINTADJ1___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_VCMINTADJ1___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_ISEL_IR25_IP1___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_ISEL_IR25_IP1___S 10 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_ISEL_IC25_OP1___M 0x00000380 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_ISEL_IC25_OP1___S 7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_ISEL_OP_OS1___M 0x00000070 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_ISEL_OP_OS1___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_ISEL_IPTAT25_OP1___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1__TIA_ISEL_IPTAT25_OP1___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_1___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2 (0x005E8418) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2___POR 0x07CCD234 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_CCADJ2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_CFBCAL_2___POR 0x03E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_ICQADJ2___POR 0x6 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_VCMINTADJ2___POR 0x6 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_ISEL_IR25_IP2___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_ISEL_IC25_OP2___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_ISEL_OP_OS2___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_ISEL_IPTAT25_OP2___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_CCADJ2___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_CCADJ2___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_CFBCAL_2___M 0x3FE00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_CFBCAL_2___S 21 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_ICQADJ2___M 0x001E0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_ICQADJ2___S 17 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_VCMINTADJ2___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_VCMINTADJ2___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_ISEL_IR25_IP2___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_ISEL_IR25_IP2___S 10 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_ISEL_IC25_OP2___M 0x00000380 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_ISEL_IC25_OP2___S 7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_ISEL_OP_OS2___M 0x00000070 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_ISEL_OP_OS2___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_ISEL_IPTAT25_OP2___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2__TIA_ISEL_IPTAT25_OP2___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_2___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3 (0x005E841C) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3___POR 0x07C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_CCADJ3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_CFBCAL_3___POR 0x03E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_ICQADJ3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_VCMINTADJ3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_ISEL_IR25_IP3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_ISEL_IC25_OP3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_ISEL_OP_OS3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_ISEL_IPTAT25_OP3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_CCADJ3___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_CCADJ3___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_CFBCAL_3___M 0x3FE00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_CFBCAL_3___S 21 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_ICQADJ3___M 0x001E0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_ICQADJ3___S 17 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_VCMINTADJ3___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_VCMINTADJ3___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_ISEL_IR25_IP3___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_ISEL_IR25_IP3___S 10 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_ISEL_IC25_OP3___M 0x00000380 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_ISEL_IC25_OP3___S 7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_ISEL_OP_OS3___M 0x00000070 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_ISEL_OP_OS3___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_ISEL_IPTAT25_OP3___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3__TIA_ISEL_IPTAT25_OP3___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_3___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0 (0x005E8420) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0___POR 0x7EC8AF76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_CFBCAL_0___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_ISEL_OP_OS_0___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_CIN_CT_0___POR 0x045 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_ISEL_IC25_IP_0___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_ISEL_IC25_OP_0___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_ISEL_IPTAT25_OP_0___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_CFBCAL_0___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_CFBCAL_0___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_ISEL_OP_OS_0___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_ISEL_OP_OS_0___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_CIN_CT_0___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_CIN_CT_0___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_ISEL_IC25_IP_0___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_ISEL_IC25_IP_0___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_ISEL_IC25_OP_0___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_ISEL_IC25_OP_0___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_ISEL_IPTAT25_OP_0___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0__BQ_ISEL_IPTAT25_OP_0___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_0___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1 (0x005E8424) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1___POR 0x7EC9CF76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_CFBCAL_1___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_ISEL_OP_OS_1___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_CIN_CT_1___POR 0x04E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_ISEL_IC25_IP_1___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_ISEL_IC25_OP_1___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_ISEL_IPTAT25_OP_1___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_CFBCAL_1___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_CFBCAL_1___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_ISEL_OP_OS_1___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_ISEL_OP_OS_1___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_CIN_CT_1___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_CIN_CT_1___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_ISEL_IC25_IP_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_ISEL_IC25_IP_1___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_ISEL_IC25_OP_1___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_ISEL_IC25_OP_1___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_ISEL_IPTAT25_OP_1___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1__BQ_ISEL_IPTAT25_OP_1___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_1___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2 (0x005E8428) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2___POR 0x7ECAEF76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_CFBCAL_2___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_ISEL_OP_OS_2___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_CIN_CT_2___POR 0x057 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_ISEL_IC25_IP_2___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_ISEL_IC25_OP_2___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_ISEL_IPTAT25_OP_2___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_CFBCAL_2___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_CFBCAL_2___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_ISEL_OP_OS_2___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_ISEL_OP_OS_2___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_CIN_CT_2___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_CIN_CT_2___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_ISEL_IC25_IP_2___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_ISEL_IC25_IP_2___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_ISEL_IC25_OP_2___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_ISEL_IC25_OP_2___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_ISEL_IPTAT25_OP_2___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2__BQ_ISEL_IPTAT25_OP_2___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_2___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3 (0x005E842C) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3___POR 0x7ECC4F76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_CFBCAL_3___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_ISEL_OP_OS_3___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_CIN_CT_3___POR 0x062 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_ISEL_IC25_IP_3___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_ISEL_IC25_OP_3___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_ISEL_IPTAT25_OP_3___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_CFBCAL_3___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_CFBCAL_3___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_ISEL_OP_OS_3___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_ISEL_OP_OS_3___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_CIN_CT_3___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_CIN_CT_3___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_ISEL_IC25_IP_3___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_ISEL_IC25_IP_3___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_ISEL_IC25_OP_3___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_ISEL_IC25_OP_3___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_ISEL_IPTAT25_OP_3___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3__BQ_ISEL_IPTAT25_OP_3___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_3___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4 (0x005E8430) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4___POR 0x7ECDCF76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_CFBCAL_4___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_ISEL_OP_OS_4___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_CIN_CT_4___POR 0x06E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_ISEL_IC25_IP_4___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_ISEL_IC25_OP_4___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_ISEL_IPTAT25_OP_4___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_CFBCAL_4___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_CFBCAL_4___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_ISEL_OP_OS_4___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_ISEL_OP_OS_4___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_CIN_CT_4___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_CIN_CT_4___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_ISEL_IC25_IP_4___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_ISEL_IC25_IP_4___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_ISEL_IC25_OP_4___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_ISEL_IC25_OP_4___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_ISEL_IPTAT25_OP_4___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4__BQ_ISEL_IPTAT25_OP_4___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_4___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5 (0x005E8434) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5___POR 0x7ECF6F76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_CFBCAL_5___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_ISEL_OP_OS_5___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_CIN_CT_5___POR 0x07B +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_ISEL_IC25_IP_5___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_ISEL_IC25_OP_5___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_ISEL_IPTAT25_OP_5___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_CFBCAL_5___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_CFBCAL_5___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_ISEL_OP_OS_5___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_ISEL_OP_OS_5___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_CIN_CT_5___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_CIN_CT_5___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_ISEL_IC25_IP_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_ISEL_IC25_IP_5___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_ISEL_IC25_OP_5___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_ISEL_IC25_OP_5___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_ISEL_IPTAT25_OP_5___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5__BQ_ISEL_IPTAT25_OP_5___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_5___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6 (0x005E8438) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6___POR 0x7ED14F76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_CFBCAL_6___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_ISEL_OP_OS_6___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_CIN_CT_6___POR 0x08A +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_ISEL_IC25_IP_6___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_ISEL_IC25_OP_6___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_ISEL_IPTAT25_OP_6___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_CFBCAL_6___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_CFBCAL_6___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_ISEL_OP_OS_6___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_ISEL_OP_OS_6___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_CIN_CT_6___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_CIN_CT_6___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_ISEL_IC25_IP_6___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_ISEL_IC25_IP_6___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_ISEL_IC25_OP_6___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_ISEL_IC25_OP_6___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_ISEL_IPTAT25_OP_6___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6__BQ_ISEL_IPTAT25_OP_6___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_6___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7 (0x005E843C) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7___POR 0x7ED36F76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_CFBCAL_7___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_ISEL_OP_OS_7___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_CIN_CT_7___POR 0x09B +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_ISEL_IC25_IP_7___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_ISEL_IC25_OP_7___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_ISEL_IPTAT25_OP_7___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_CFBCAL_7___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_CFBCAL_7___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_ISEL_OP_OS_7___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_ISEL_OP_OS_7___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_CIN_CT_7___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_CIN_CT_7___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_ISEL_IC25_IP_7___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_ISEL_IC25_IP_7___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_ISEL_IC25_OP_7___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_ISEL_IC25_OP_7___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_ISEL_IPTAT25_OP_7___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7__BQ_ISEL_IPTAT25_OP_7___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_7___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8 (0x005E8440) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8___POR 0x7ED5CF76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_CFBCAL_8___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_ISEL_OP_OS_8___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_CIN_CT_8___POR 0x0AE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_ISEL_IC25_IP_8___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_ISEL_IC25_OP_8___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_ISEL_IPTAT25_OP_8___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_CFBCAL_8___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_CFBCAL_8___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_ISEL_OP_OS_8___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_ISEL_OP_OS_8___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_CIN_CT_8___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_CIN_CT_8___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_ISEL_IC25_IP_8___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_ISEL_IC25_IP_8___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_ISEL_IC25_OP_8___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_ISEL_IC25_OP_8___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_ISEL_IPTAT25_OP_8___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8__BQ_ISEL_IPTAT25_OP_8___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_8___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9 (0x005E8444) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9___POR 0x7ED5CF76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_CFBCAL_9___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_ISEL_OP_OS_9___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_CIN_CT_9___POR 0x0AE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_ISEL_IC25_IP_9___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_ISEL_IC25_OP_9___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_ISEL_IPTAT25_OP_9___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_CFBCAL_9___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_CFBCAL_9___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_ISEL_OP_OS_9___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_ISEL_OP_OS_9___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_CIN_CT_9___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_CIN_CT_9___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_ISEL_IC25_IP_9___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_ISEL_IC25_IP_9___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_ISEL_IC25_OP_9___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_ISEL_IC25_OP_9___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_ISEL_IPTAT25_OP_9___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9__BQ_ISEL_IPTAT25_OP_9___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_9___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10 (0x005E8448) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10___POR 0x7ED5CF76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_CFBCAL_10___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_ISEL_OP_OS_10___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_CIN_CT_10___POR 0x0AE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_ISEL_IC25_IP_10___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_ISEL_IC25_OP_10___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_ISEL_IPTAT25_OP_10___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_CFBCAL_10___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_CFBCAL_10___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_ISEL_OP_OS_10___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_ISEL_OP_OS_10___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_CIN_CT_10___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_CIN_CT_10___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_ISEL_IC25_IP_10___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_ISEL_IC25_IP_10___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_ISEL_IC25_OP_10___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_ISEL_IC25_OP_10___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_ISEL_IPTAT25_OP_10___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10__BQ_ISEL_IPTAT25_OP_10___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_10___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11 (0x005E844C) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11___POR 0x7ED5CF76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_CFBCAL_11___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_ISEL_OP_OS_11___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_CIN_CT_11___POR 0x0AE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_ISEL_IC25_IP_11___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_ISEL_IC25_OP_11___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_ISEL_IPTAT25_OP_11___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_CFBCAL_11___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_CFBCAL_11___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_ISEL_OP_OS_11___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_ISEL_OP_OS_11___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_CIN_CT_11___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_CIN_CT_11___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_ISEL_IC25_IP_11___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_ISEL_IC25_IP_11___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_ISEL_IC25_OP_11___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_ISEL_IC25_OP_11___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_ISEL_IPTAT25_OP_11___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11__BQ_ISEL_IPTAT25_OP_11___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_11___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12 (0x005E8450) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12___POR 0x7ED5CF76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_CFBCAL_12___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_ISEL_OP_OS_12___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_CIN_CT_12___POR 0x0AE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_ISEL_IC25_IP_12___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_ISEL_IC25_OP_12___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_ISEL_IPTAT25_OP_12___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_CFBCAL_12___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_CFBCAL_12___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_ISEL_OP_OS_12___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_ISEL_OP_OS_12___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_CIN_CT_12___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_CIN_CT_12___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_ISEL_IC25_IP_12___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_ISEL_IC25_IP_12___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_ISEL_IC25_OP_12___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_ISEL_IC25_OP_12___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_ISEL_IPTAT25_OP_12___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12__BQ_ISEL_IPTAT25_OP_12___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_12___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13 (0x005E8454) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13___POR 0x7ED5CF76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_CFBCAL_13___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_ISEL_OP_OS_13___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_CIN_CT_13___POR 0x0AE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_ISEL_IC25_IP_13___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_ISEL_IC25_OP_13___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_ISEL_IPTAT25_OP_13___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_CFBCAL_13___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_CFBCAL_13___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_ISEL_OP_OS_13___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_ISEL_OP_OS_13___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_CIN_CT_13___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_CIN_CT_13___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_ISEL_IC25_IP_13___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_ISEL_IC25_IP_13___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_ISEL_IC25_OP_13___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_ISEL_IC25_OP_13___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_ISEL_IPTAT25_OP_13___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13__BQ_ISEL_IPTAT25_OP_13___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_13___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14 (0x005E8458) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14___POR 0x7ED5CF76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_CFBCAL_14___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_ISEL_OP_OS_14___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_CIN_CT_14___POR 0x0AE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_ISEL_IC25_IP_14___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_ISEL_IC25_OP_14___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_ISEL_IPTAT25_OP_14___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_CFBCAL_14___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_CFBCAL_14___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_ISEL_OP_OS_14___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_ISEL_OP_OS_14___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_CIN_CT_14___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_CIN_CT_14___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_ISEL_IC25_IP_14___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_ISEL_IC25_IP_14___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_ISEL_IC25_OP_14___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_ISEL_IC25_OP_14___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_ISEL_IPTAT25_OP_14___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14__BQ_ISEL_IPTAT25_OP_14___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_14___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15 (0x005E845C) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15___POR 0x7ED5CF76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_CFBCAL_15___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_ISEL_OP_OS_15___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_CIN_CT_15___POR 0x0AE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_ISEL_IC25_IP_15___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_ISEL_IC25_OP_15___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_ISEL_IPTAT25_OP_15___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_CFBCAL_15___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_CFBCAL_15___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_ISEL_OP_OS_15___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_ISEL_OP_OS_15___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_CIN_CT_15___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_CIN_CT_15___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_ISEL_IC25_IP_15___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_ISEL_IC25_IP_15___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_ISEL_IC25_OP_15___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_ISEL_IC25_OP_15___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_ISEL_IPTAT25_OP_15___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15__BQ_ISEL_IPTAT25_OP_15___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_15___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16 (0x005E8460) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16___POR 0x7EC00F76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_CFBCAL_16___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_ISEL_OP_OS_16___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_CIN_CT_16___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_ISEL_IC25_IP_16___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_ISEL_IC25_OP_16___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_ISEL_IPTAT25_OP_16___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_CFBCAL_16___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_CFBCAL_16___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_ISEL_OP_OS_16___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_ISEL_OP_OS_16___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_CIN_CT_16___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_CIN_CT_16___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_ISEL_IC25_IP_16___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_ISEL_IC25_IP_16___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_ISEL_IC25_OP_16___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_ISEL_IC25_OP_16___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_ISEL_IPTAT25_OP_16___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16__BQ_ISEL_IPTAT25_OP_16___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_16___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17 (0x005E8464) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17___POR 0x7EC00F76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_CFBCAL_17___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_ISEL_OP_OS_17___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_CIN_CT_17___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_ISEL_IC25_IP_17___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_ISEL_IC25_OP_17___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_ISEL_IPTAT25_OP_17___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_CFBCAL_17___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_CFBCAL_17___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_ISEL_OP_OS_17___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_ISEL_OP_OS_17___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_CIN_CT_17___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_CIN_CT_17___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_ISEL_IC25_IP_17___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_ISEL_IC25_IP_17___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_ISEL_IC25_OP_17___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_ISEL_IC25_OP_17___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_ISEL_IPTAT25_OP_17___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17__BQ_ISEL_IPTAT25_OP_17___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_17___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18 (0x005E8468) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18___POR 0x7EC00F76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_CFBCAL_18___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_ISEL_OP_OS_18___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_CIN_CT_18___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_ISEL_IC25_IP_18___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_ISEL_IC25_OP_18___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_ISEL_IPTAT25_OP_18___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_CFBCAL_18___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_CFBCAL_18___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_ISEL_OP_OS_18___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_ISEL_OP_OS_18___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_CIN_CT_18___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_CIN_CT_18___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_ISEL_IC25_IP_18___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_ISEL_IC25_IP_18___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_ISEL_IC25_OP_18___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_ISEL_IC25_OP_18___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_ISEL_IPTAT25_OP_18___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18__BQ_ISEL_IPTAT25_OP_18___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_18___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19 (0x005E846C) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19___POR 0x7EC00F76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_CFBCAL_19___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_ISEL_OP_OS_19___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_CIN_CT_19___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_ISEL_IC25_IP_19___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_ISEL_IC25_OP_19___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_ISEL_IPTAT25_OP_19___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_CFBCAL_19___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_CFBCAL_19___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_ISEL_OP_OS_19___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_ISEL_OP_OS_19___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_CIN_CT_19___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_CIN_CT_19___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_ISEL_IC25_IP_19___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_ISEL_IC25_IP_19___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_ISEL_IC25_OP_19___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_ISEL_IC25_OP_19___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_ISEL_IPTAT25_OP_19___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19__BQ_ISEL_IPTAT25_OP_19___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_19___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20 (0x005E8470) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20___POR 0x7EC00F76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_CFBCAL_20___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_ISEL_OP_OS_20___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_CIN_CT_20___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_ISEL_IC25_IP_20___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_ISEL_IC25_OP_20___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_ISEL_IPTAT25_OP_20___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_CFBCAL_20___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_CFBCAL_20___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_ISEL_OP_OS_20___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_ISEL_OP_OS_20___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_CIN_CT_20___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_CIN_CT_20___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_ISEL_IC25_IP_20___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_ISEL_IC25_IP_20___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_ISEL_IC25_OP_20___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_ISEL_IC25_OP_20___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_ISEL_IPTAT25_OP_20___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20__BQ_ISEL_IPTAT25_OP_20___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_20___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21 (0x005E8474) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21___POR 0x7EC00F76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_CFBCAL_21___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_ISEL_OP_OS_21___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_CIN_CT_21___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_ISEL_IC25_IP_21___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_ISEL_IC25_OP_21___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_ISEL_IPTAT25_OP_21___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_CFBCAL_21___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_CFBCAL_21___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_ISEL_OP_OS_21___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_ISEL_OP_OS_21___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_CIN_CT_21___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_CIN_CT_21___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_ISEL_IC25_IP_21___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_ISEL_IC25_IP_21___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_ISEL_IC25_OP_21___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_ISEL_IC25_OP_21___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_ISEL_IPTAT25_OP_21___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21__BQ_ISEL_IPTAT25_OP_21___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_21___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22 (0x005E8478) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22___POR 0x7EC00F76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_CFBCAL_22___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_ISEL_OP_OS_22___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_CIN_CT_22___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_ISEL_IC25_IP_22___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_ISEL_IC25_OP_22___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_ISEL_IPTAT25_OP_22___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_CFBCAL_22___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_CFBCAL_22___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_ISEL_OP_OS_22___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_ISEL_OP_OS_22___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_CIN_CT_22___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_CIN_CT_22___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_ISEL_IC25_IP_22___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_ISEL_IC25_IP_22___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_ISEL_IC25_OP_22___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_ISEL_IC25_OP_22___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_ISEL_IPTAT25_OP_22___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22__BQ_ISEL_IPTAT25_OP_22___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_22___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_0 (0x005E847C) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_0__TIA_GAIN_CTRL_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_0__TIA_GAIN_CTRL_0___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_0__TIA_GAIN_CTRL_0___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_0___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_0___S 30 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_1 (0x005E8480) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_1___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_1__TIA_GAIN_CTRL_1___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_1__TIA_GAIN_CTRL_1___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_1__TIA_GAIN_CTRL_1___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_1___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_1___S 30 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_2 (0x005E8484) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_2___POR 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_2__TIA_GAIN_CTRL_2___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_2__TIA_GAIN_CTRL_2___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_2__TIA_GAIN_CTRL_2___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_2___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_2___S 30 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_3 (0x005E8488) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_3__TIA_GAIN_CTRL_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_3__TIA_GAIN_CTRL_3___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_3__TIA_GAIN_CTRL_3___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_3___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT0_3___S 30 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_0 (0x005E848C) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_0__BQ_GAIN_CTRL_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_0__BQ_GAIN_CTRL_0___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_0__BQ_GAIN_CTRL_0___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_0___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_0___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_1 (0x005E8490) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_1___POR 0x08000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_1__BQ_GAIN_CTRL_1___POR 0x01 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_1__BQ_GAIN_CTRL_1___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_1__BQ_GAIN_CTRL_1___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_1___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_1___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_2 (0x005E8494) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_2___POR 0x10000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_2__BQ_GAIN_CTRL_2___POR 0x02 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_2__BQ_GAIN_CTRL_2___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_2__BQ_GAIN_CTRL_2___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_2___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_2___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_3 (0x005E8498) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_3___POR 0x18000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_3__BQ_GAIN_CTRL_3___POR 0x03 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_3__BQ_GAIN_CTRL_3___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_3__BQ_GAIN_CTRL_3___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_3___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_3___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_4 (0x005E849C) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_4___POR 0x20000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_4__BQ_GAIN_CTRL_4___POR 0x04 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_4__BQ_GAIN_CTRL_4___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_4__BQ_GAIN_CTRL_4___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_4___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_4___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_5 (0x005E84A0) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_5___POR 0x28000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_5__BQ_GAIN_CTRL_5___POR 0x05 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_5__BQ_GAIN_CTRL_5___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_5__BQ_GAIN_CTRL_5___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_5___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_5___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_6 (0x005E84A4) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_6___POR 0x30000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_6__BQ_GAIN_CTRL_6___POR 0x06 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_6__BQ_GAIN_CTRL_6___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_6__BQ_GAIN_CTRL_6___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_6___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_6___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_7 (0x005E84A8) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_7___POR 0x38000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_7__BQ_GAIN_CTRL_7___POR 0x07 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_7__BQ_GAIN_CTRL_7___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_7__BQ_GAIN_CTRL_7___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_7___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_7___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_8 (0x005E84AC) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_8___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_8__BQ_GAIN_CTRL_8___POR 0x08 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_8__BQ_GAIN_CTRL_8___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_8__BQ_GAIN_CTRL_8___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_8___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_8___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_9 (0x005E84B0) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_9___POR 0x48000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_9__BQ_GAIN_CTRL_9___POR 0x09 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_9__BQ_GAIN_CTRL_9___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_9__BQ_GAIN_CTRL_9___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_9___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_9___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_10 (0x005E84B4) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_10___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_10__BQ_GAIN_CTRL_10___POR 0x0A +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_10__BQ_GAIN_CTRL_10___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_10__BQ_GAIN_CTRL_10___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_10___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_10___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_11 (0x005E84B8) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_11___POR 0x58000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_11__BQ_GAIN_CTRL_11___POR 0x0B +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_11__BQ_GAIN_CTRL_11___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_11__BQ_GAIN_CTRL_11___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_11___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_11___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_12 (0x005E84BC) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_12___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_12__BQ_GAIN_CTRL_12___POR 0x0C +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_12__BQ_GAIN_CTRL_12___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_12__BQ_GAIN_CTRL_12___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_12___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_12___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_13 (0x005E84C0) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_13___POR 0x68000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_13__BQ_GAIN_CTRL_13___POR 0x0D +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_13__BQ_GAIN_CTRL_13___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_13__BQ_GAIN_CTRL_13___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_13___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_13___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_14 (0x005E84C4) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_14___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_14__BQ_GAIN_CTRL_14___POR 0x0E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_14__BQ_GAIN_CTRL_14___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_14__BQ_GAIN_CTRL_14___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_14___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_14___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_15 (0x005E84C8) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_15___POR 0x78000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_15__BQ_GAIN_CTRL_15___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_15__BQ_GAIN_CTRL_15___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_15__BQ_GAIN_CTRL_15___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_15___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_15___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_16 (0x005E84CC) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_16___POR 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_16__BQ_GAIN_CTRL_16___POR 0x10 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_16__BQ_GAIN_CTRL_16___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_16__BQ_GAIN_CTRL_16___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_16___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_16___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_17 (0x005E84D0) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_17___POR 0x88000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_17__BQ_GAIN_CTRL_17___POR 0x11 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_17__BQ_GAIN_CTRL_17___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_17__BQ_GAIN_CTRL_17___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_17___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_17___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_18 (0x005E84D4) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_18___POR 0x90000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_18__BQ_GAIN_CTRL_18___POR 0x12 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_18__BQ_GAIN_CTRL_18___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_18__BQ_GAIN_CTRL_18___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_18___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_18___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_19 (0x005E84D8) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_19___POR 0x98000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_19__BQ_GAIN_CTRL_19___POR 0x13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_19__BQ_GAIN_CTRL_19___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_19__BQ_GAIN_CTRL_19___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_19___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_19___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_20 (0x005E84DC) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_20___POR 0xA0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_20__BQ_GAIN_CTRL_20___POR 0x14 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_20__BQ_GAIN_CTRL_20___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_20__BQ_GAIN_CTRL_20___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_20___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_20___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_21 (0x005E84E0) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_21___POR 0xA8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_21__BQ_GAIN_CTRL_21___POR 0x15 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_21__BQ_GAIN_CTRL_21___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_21__BQ_GAIN_CTRL_21___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_21___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_21___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_22 (0x005E84E4) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_22___POR 0xB0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_22__BQ_GAIN_CTRL_22___POR 0x16 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_22__BQ_GAIN_CTRL_22___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_22__BQ_GAIN_CTRL_22___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_22___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT0_22___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0 (0x005E84E8) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CCADJ_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CCADJ_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CFBCAL_I_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CFBCAL_I_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CFBCAL_Q_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CFBCAL_Q_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_ICQADJ_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_ICQADJ_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CCADJ_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CCADJ_OV___S 31 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CCADJ_OVD___M 0x60000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CCADJ_OVD___S 29 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CFBCAL_I_OV___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CFBCAL_I_OV___S 28 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CFBCAL_I_OVD___M 0x0FF80000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CFBCAL_I_OVD___S 19 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CFBCAL_Q_OV___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CFBCAL_Q_OV___S 18 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CFBCAL_Q_OVD___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_CFBCAL_Q_OVD___S 9 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_ICQADJ_OV___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_ICQADJ_OV___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_ICQADJ_OVD___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0__TIA_ICQADJ_OVD___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0___M 0xFFFFFFF0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV0___S 4 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1 (0x005E84EC) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_VCMINTADJ_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_VCMINTADJ_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IR25_IP_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IR25_IP_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IC25_OP_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IC25_OP_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_OP_OS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_OP_OS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IPTAT25_OP_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IPTAT25_OP_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_GAIN_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_GAIN_CTRL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_VCMINTADJ_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_VCMINTADJ_OV___S 31 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_VCMINTADJ_OVD___M 0x78000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_VCMINTADJ_OVD___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IR25_IP_OV___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IR25_IP_OV___S 26 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IR25_IP_OVD___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IR25_IP_OVD___S 23 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IC25_OP_OV___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IC25_OP_OV___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IC25_OP_OVD___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IC25_OP_OVD___S 19 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_OP_OS_OV___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_OP_OS_OV___S 18 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_OP_OS_OVD___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_OP_OS_OVD___S 15 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IPTAT25_OP_OV___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IPTAT25_OP_OV___S 14 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IPTAT25_OP_OVD___M 0x00003800 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_ISEL_IPTAT25_OP_OVD___S 11 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_GAIN_CTRL_OV___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_GAIN_CTRL_OV___S 10 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_GAIN_CTRL_OVD___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1__TIA_GAIN_CTRL_OVD___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1___M 0xFFFFFF00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA_LUT_OV1___S 8 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0 (0x005E84F0) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_GAIN_CTRL_PDET_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_GAIN_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_GAIN_CTRL_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_ISEL_OP_OS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_ISEL_OP_OS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_CIN_CT_I_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_CIN_CT_I_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_CIN_CT_Q_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_CIN_CT_Q_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_GAIN_CTRL_PDET_OV___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_GAIN_CTRL_PDET_OV___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_GAIN_CTRL_OV___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_GAIN_CTRL_OV___S 29 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_GAIN_CTRL_OVD___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_GAIN_CTRL_OVD___S 24 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_ISEL_OP_OS_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_ISEL_OP_OS_OV___S 23 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_ISEL_OP_OS_OVD___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_ISEL_OP_OS_OVD___S 20 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_CIN_CT_I_OV___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_CIN_CT_I_OV___S 19 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_CIN_CT_I_OVD___M 0x0007FC00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_CIN_CT_I_OVD___S 10 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_CIN_CT_Q_OV___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_CIN_CT_Q_OV___S 9 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_CIN_CT_Q_OVD___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0__BQ_CIN_CT_Q_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0___M 0x7FFFFFFF +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV0___S 0 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1 (0x005E84F4) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IC25_IP_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IC25_IP_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IC25_OP_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IC25_OP_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IPTAT25_OP_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IPTAT25_OP_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_CFBCAL_I_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_CFBCAL_I_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_CFBCAL_Q_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_CFBCAL_Q_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IC25_IP_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IC25_IP_OV___S 31 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IC25_IP_OVD___M 0x7C000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IC25_IP_OVD___S 26 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IC25_OP_OV___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IC25_OP_OV___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IC25_OP_OVD___M 0x01E00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IC25_OP_OVD___S 21 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IPTAT25_OP_OV___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IPTAT25_OP_OV___S 20 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IPTAT25_OP_OVD___M 0x000E0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_ISEL_IPTAT25_OP_OVD___S 17 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_CFBCAL_I_OV___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_CFBCAL_I_OV___S 16 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_CFBCAL_I_OVD___M 0x0000FE00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_CFBCAL_I_OVD___S 9 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_CFBCAL_Q_OV___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_CFBCAL_Q_OV___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_CFBCAL_Q_OVD___M 0x000000FE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1__BQ_CFBCAL_Q_OVD___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ_LUT_OV1___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT_OV (0x005E84F8) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT_OV___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT_OV___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT_OV__TIA_SATDET_EN_I_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT_OV__TIA_SATDET_EN_Q_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT_OV__TIA_SATDET_EN_I_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT_OV__TIA_SATDET_EN_I_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT_OV__TIA_SATDET_EN_Q_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT_OV__TIA_SATDET_EN_Q_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT_OV___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT_OV___S 28 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0 (0x005E84FC) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__DCOC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__TIA_EN_I_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__TIA_EN_Q_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BQ_EN_I_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BQ_EN_Q_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__IM2_BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__IM2_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__IM2_OTA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BIAS_RTT_TIA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BIAS_RTT_BQ_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__TIA_EN_HSW_I_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__TIA_EN_HSW_Q_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BQ_EN_HSW_I_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BQ_EN_HSW_Q_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__TPC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BIAS_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BIAS_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__DCOC_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__DCOC_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__TIA_EN_I_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__TIA_EN_I_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__TIA_EN_Q_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__TIA_EN_Q_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BQ_EN_I_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BQ_EN_I_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BQ_EN_Q_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BQ_EN_Q_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__IM2_BIAS_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__IM2_BIAS_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__IM2_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__IM2_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__IM2_OTA_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__IM2_OTA_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BIAS_RTT_TIA_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BIAS_RTT_TIA_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BIAS_RTT_BQ_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BIAS_RTT_BQ_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__TIA_EN_HSW_I_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__TIA_EN_HSW_I_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__TIA_EN_HSW_Q_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__TIA_EN_HSW_Q_OVS___S 6 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BQ_EN_HSW_I_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BQ_EN_HSW_I_OVS___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BQ_EN_HSW_Q_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__BQ_EN_HSW_Q_OVS___S 2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__TPC_EN_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0__TPC_EN_OVS___S 0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_EN0___S 0 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_LUT_IDX (0x005E8500) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_LUT_IDX___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_LUT_IDX___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_LUT_IDX__RO_TIA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_LUT_IDX__RO_BQ_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_LUT_IDX__RO_TIA_GAIN___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_LUT_IDX__RO_TIA_GAIN___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_LUT_IDX__RO_BQ_GAIN___M 0x3E000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_LUT_IDX__RO_BQ_GAIN___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_LUT_IDX___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_LUT_IDX___S 25 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT0 (0x005E8504) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT0__RO_TIA_CCADJ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT0__RO_TIA_CFBCAL_I___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT0__RO_TIA_CFBCAL_Q___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT0__RO_TIA_ICQADJ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT0__RO_TIA_CCADJ___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT0__RO_TIA_CCADJ___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT0__RO_TIA_CFBCAL_I___M 0x3FE00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT0__RO_TIA_CFBCAL_I___S 21 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT0__RO_TIA_CFBCAL_Q___M 0x001FF000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT0__RO_TIA_CFBCAL_Q___S 12 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT0__RO_TIA_ICQADJ___M 0x00000F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT0__RO_TIA_ICQADJ___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT0___M 0xFFFFFF00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT0___S 8 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1 (0x005E8508) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_VCMINTADJ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_ISEL_IR25_IP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_ISEL_IC25_OP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_ISEL_OP_OS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_ISEL_IPTAT25_OP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_GAIN_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_VCMINTADJ___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_VCMINTADJ___S 28 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_ISEL_IR25_IP___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_ISEL_IR25_IP___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_ISEL_IC25_OP___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_ISEL_IC25_OP___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_ISEL_OP_OS___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_ISEL_OP_OS___S 19 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_ISEL_IPTAT25_OP___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_ISEL_IPTAT25_OP___S 16 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_GAIN_CTRL___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1__RO_TIA_GAIN_CTRL___S 14 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1___M 0xFFFFC000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_TIA_LUT1___S 14 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT0 (0x005E850C) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT0__RO_BQ_GAIN_CTRL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT0__RO_BQ_ISEL_OP_OS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT0__RO_BQ_CIN_CT_I___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT0__RO_BQ_CIN_CT_Q___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT0__RO_BQ_GAIN_CTRL___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT0__RO_BQ_GAIN_CTRL___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT0__RO_BQ_ISEL_OP_OS___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT0__RO_BQ_ISEL_OP_OS___S 24 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT0__RO_BQ_CIN_CT_I___M 0x00FF8000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT0__RO_BQ_CIN_CT_I___S 15 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT0__RO_BQ_CIN_CT_Q___M 0x00007FC0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT0__RO_BQ_CIN_CT_Q___S 6 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT0___M 0xFFFFFFC0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT0___S 6 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1 (0x005E8510) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1__RO_BQ_ISEL_IC25_IP___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1__RO_BQ_ISEL_IC25_OP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1__RO_BQ_ISEL_IPTAT25_OP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1__RO_BQ_CFBCAL_I___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1__RO_BQ_CFBCAL_Q___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1__RO_BQ_ISEL_IC25_IP___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1__RO_BQ_ISEL_IC25_IP___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1__RO_BQ_ISEL_IC25_OP___M 0x07800000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1__RO_BQ_ISEL_IC25_OP___S 23 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1__RO_BQ_ISEL_IPTAT25_OP___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1__RO_BQ_ISEL_IPTAT25_OP___S 20 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1__RO_BQ_CFBCAL_I___M 0x000FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1__RO_BQ_CFBCAL_I___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1__RO_BQ_CFBCAL_Q___M 0x00001FC0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1__RO_BQ_CFBCAL_Q___S 6 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1___M 0xFFFFFFC0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_BQ_LUT1___S 6 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_DCOCBB (0x005E8514) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_DCOCBB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_DCOCBB___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_DCOCBB__RO_DCOCBB_RANGE_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_DCOCBB__RO_DCOCBB_RANGE_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_DCOCBB__RO_DCOCBB_RES_I___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_DCOCBB__RO_DCOCBB_RES_Q___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_DCOCBB__RO_DCOCBB_RANGE_I___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_DCOCBB__RO_DCOCBB_RANGE_I___S 20 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_DCOCBB__RO_DCOCBB_RANGE_Q___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_DCOCBB__RO_DCOCBB_RANGE_Q___S 18 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_DCOCBB__RO_DCOCBB_RES_I___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_DCOCBB__RO_DCOCBB_RES_I___S 9 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_DCOCBB__RO_DCOCBB_RES_Q___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_DCOCBB__RO_DCOCBB_RES_Q___S 0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_DCOCBB___M 0x003FFFFF +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RO_DCOCBB___S 0 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT (0x005E8518) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT___POR 0x58000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT__D_TIA_SATDET_LEVEL___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT__D_TIA_SATDET_BOOST_I___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT__D_TIA_SATDET_BOOST_Q___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT__D_TIA_SATDET_LEVEL___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT__D_TIA_SATDET_LEVEL___S 29 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT__D_TIA_SATDET_BOOST_I___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT__D_TIA_SATDET_BOOST_I___S 28 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT__D_TIA_SATDET_BOOST_Q___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT__D_TIA_SATDET_BOOST_Q___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SAT___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA (0x005E851C) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA___POR 0x37000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA__D_TIA_RMCAP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA__D_TIA_RFB_I___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA__D_TIA_RFB_Q___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA__D_TIA_VICMADJ___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA__D_TIA_RMCAP___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA__D_TIA_RMCAP___S 31 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA__D_TIA_RFB_I___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA__D_TIA_RFB_I___S 28 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA__D_TIA_RFB_Q___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA__D_TIA_RFB_Q___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA__D_TIA_VICMADJ___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA__D_TIA_VICMADJ___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TIA___S 22 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ (0x005E8520) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ___POR 0x20000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ__D_BQ_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ__D_BQ_VCM_SEL___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ__D_BQ_BYPASS___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ__D_BQ_BYPASS___S 31 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ__D_BQ_VCM_SEL___M 0x78000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ__D_BQ_VCM_SEL___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_BQ___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2 (0x005E8524) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_VCAL_DAC_I___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_VCAL_DAC_Q___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_CONT_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_CONT_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_RCTRL_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_RCTRL_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_VGF_MIX___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_TEST___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_VCAL_DAC_I___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_VCAL_DAC_I___S 24 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_VCAL_DAC_Q___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_VCAL_DAC_Q___S 16 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_CONT_I___M 0x0000E000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_CONT_I___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_CONT_Q___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_CONT_Q___S 10 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_RCTRL_I___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_RCTRL_I___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_RCTRL_Q___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_RCTRL_Q___S 6 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_VGF_MIX___M 0x00000030 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_VGF_MIX___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_TEST___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2__D_IM2_TEST___S 3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2___M 0xFFFFFFF8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_IM2___S 3 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0 (0x005E8528) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2A_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2B_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2C_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW4A_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW5_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW6A_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW6B_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW7_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2A_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2B_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2C_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW4A_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW5_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW6A_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW6B_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW7_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2A_I___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2A_I___S 31 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2B_I___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2B_I___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2C_I___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2C_I___S 29 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW4A_I___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW4A_I___S 28 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW5_I___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW5_I___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW6A_I___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW6A_I___S 26 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW6B_I___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW6B_I___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW7_I___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW7_I___S 24 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2A_Q___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2A_Q___S 23 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2B_Q___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2B_Q___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2C_Q___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW2C_Q___S 21 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW4A_Q___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW4A_Q___S 20 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW5_Q___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW5_Q___S 19 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW6A_Q___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW6A_Q___S 18 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW6B_Q___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW6B_Q___S 17 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW7_Q___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0__D_TSTBUF_SW7_Q___S 16 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER0___S 16 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1 (0x005E852C) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1___POR 0x80426300 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_RIN_CTRL___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_RFB_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_CFB_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_IN___POR 0x10 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_OUT___POR 0x9 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_ZR___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_CCADJ___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_OUT_PTAT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_RTT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_EN_HSW_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_EN_HSW_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_RIN_CTRL___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_RIN_CTRL___S 29 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_RFB_CTRL___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_RFB_CTRL___S 26 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_CFB_CTRL___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_CFB_CTRL___S 23 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_IN___M 0x007C0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_IN___S 18 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_OUT___M 0x0003C000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_OUT___S 14 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_ZR___M 0x00003800 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_ZR___S 11 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_CCADJ___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_CCADJ___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_OUT_PTAT___M 0x000000E0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_OUT_PTAT___S 5 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_RTT_EN___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_RTT_EN___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_EN_HSW_I___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_EN_HSW_I___S 3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_EN_HSW_Q___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1__D_TSTBUF_EN_HSW_Q___S 2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_RX_TEST_BUFFER1___S 2 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL (0x005E8530) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_ADC_VCM_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_TPC_PATH_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_TS_PATH_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_LPBKSEL_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_LPBKSEL_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_BLOCK_TEST_SEL_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_BLOCK_TEST_SEL_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_BIAS_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_ATB_CTRL_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_ATB_CTRL_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_ADC_VCM_SEL___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_ADC_VCM_SEL___S 31 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_TPC_PATH_EN___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_TPC_PATH_EN___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_TS_PATH_EN___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_TS_PATH_EN___S 29 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_LPBKSEL_I___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_LPBKSEL_I___S 28 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_LPBKSEL_Q___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_LPBKSEL_Q___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_BLOCK_TEST_SEL_I___M 0x06000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_BLOCK_TEST_SEL_I___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_BLOCK_TEST_SEL_Q___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_BLOCK_TEST_SEL_Q___S 23 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_BIAS_ATB_SEL___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_BIAS_ATB_SEL___S 20 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_ATB_CTRL_I___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_ATB_CTRL_I___S 18 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_ATB_CTRL_Q___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL__D_ATB_CTRL_Q___S 16 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_OTHER_ANALOG_CONTROL___S 16 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SPARE0 (0x005E8534) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SPARE0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SPARE0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SPARE0__D_RXBB_SPARE___POR 0x00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SPARE0__D_RXBB_SPARE___M 0x0003FFFF +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SPARE0__D_RXBB_SPARE___S 0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SPARE0___M 0x0003FFFF +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_SPARE0___S 0 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0 (0x005E8538) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0___POR 0xD8049248 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__TIA_BW_VDET___POR 0x6 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__TIA_BW_PDET___POR 0x6 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_BW_VDET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_BW_PDET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_CC1ADJ_VDET___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_CC1ADJ_PDET___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_CC2ADJ_VDET___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_CC2ADJ_PDET___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_ZR1_VDET___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_ZR1_PDET___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__TIA_BW_VDET___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__TIA_BW_VDET___S 29 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__TIA_BW_PDET___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__TIA_BW_PDET___S 26 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_BW_VDET___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_BW_VDET___S 23 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_BW_PDET___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_BW_PDET___S 20 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_CC1ADJ_VDET___M 0x000E0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_CC1ADJ_VDET___S 17 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_CC1ADJ_PDET___M 0x0001C000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_CC1ADJ_PDET___S 14 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_CC2ADJ_VDET___M 0x00003800 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_CC2ADJ_VDET___S 11 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_CC2ADJ_PDET___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_CC2ADJ_PDET___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_ZR1_VDET___M 0x000000E0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_ZR1_VDET___S 5 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_ZR1_PDET___M 0x0000001C +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0__BQ_ZR1_PDET___S 2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC0___S 2 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1 (0x005E853C) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1___POR 0x4800006C +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BQ_ZR2_VDET___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BQ_ZR2_PDET___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BQ_SELQ_VDET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BQ_SELQ_PDET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BOOST_BQ_VDET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BOOST_BQ_PDET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BQ_GAIN_CTRL_VDET___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__TIA_ISEL_OP_OS_VDET___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__TIA_ISEL_OP_OS_PDET___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BQ_ZR2_VDET___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BQ_ZR2_VDET___S 29 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BQ_ZR2_PDET___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BQ_ZR2_PDET___S 26 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BQ_SELQ_VDET___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BQ_SELQ_VDET___S 23 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BQ_SELQ_PDET___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BQ_SELQ_PDET___S 20 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BOOST_BQ_VDET___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BOOST_BQ_VDET___S 19 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BOOST_BQ_PDET___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BOOST_BQ_PDET___S 18 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BQ_GAIN_CTRL_VDET___M 0x0003E000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__BQ_GAIN_CTRL_VDET___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__TIA_ISEL_OP_OS_VDET___M 0x000000E0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__TIA_ISEL_OP_OS_VDET___S 5 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__TIA_ISEL_OP_OS_PDET___M 0x0000001C +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1__TIA_ISEL_OP_OS_PDET___S 2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1___M 0xFFFFE0FC +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC1___S 2 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2 (0x005E8540) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2___POR 0x1088B000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__BQ_ISEL_IC25_IP_VDET___POR 0x02 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__BQ_ISEL_IC25_IP_PDET___POR 0x02 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__BQ_ISEL_IC25_OP_VDET___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__BQ_ISEL_IC25_OP_PDET___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__TIA_RMCAP_VDET___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__TIA_RMCAP_PDET___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__BQ_ISEL_IC25_IP_VDET___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__BQ_ISEL_IC25_IP_VDET___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__BQ_ISEL_IC25_IP_PDET___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__BQ_ISEL_IC25_IP_PDET___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__BQ_ISEL_IC25_OP_VDET___M 0x003C0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__BQ_ISEL_IC25_OP_VDET___S 18 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__BQ_ISEL_IC25_OP_PDET___M 0x0003C000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__BQ_ISEL_IC25_OP_PDET___S 14 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__TIA_RMCAP_VDET___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__TIA_RMCAP_VDET___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__TIA_RMCAP_PDET___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2__TIA_RMCAP_PDET___S 12 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC2___S 12 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC3 (0x005E8544) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC3___POR 0x00005E2F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC3__BQ_CIN_CT_I_VDET___POR 0x02F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC3__BQ_CIN_CT_I_PDET___POR 0x02F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC3__BQ_CIN_CT_I_VDET___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC3__BQ_CIN_CT_I_VDET___S 9 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC3__BQ_CIN_CT_I_PDET___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC3__BQ_CIN_CT_I_PDET___S 0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC3___M 0x0003FFFF +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC3___S 0 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC4 (0x005E8548) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC4___POR 0x178BDCB9 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC4__BQ_CIN_CT_Q_VDET___POR 0x02F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC4__BQ_CIN_CT_Q_PDET___POR 0x02F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC4__BQ_CFBCAL_I_VDET___POR 0x39 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC4__BQ_CFBCAL_I_PDET___POR 0x39 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC4__BQ_CIN_CT_Q_VDET___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC4__BQ_CIN_CT_Q_VDET___S 23 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC4__BQ_CIN_CT_Q_PDET___M 0x007FC000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC4__BQ_CIN_CT_Q_PDET___S 14 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC4__BQ_CFBCAL_I_VDET___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC4__BQ_CFBCAL_I_VDET___S 7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC4__BQ_CFBCAL_I_PDET___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC4__BQ_CFBCAL_I_PDET___S 0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC4___S 0 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5 (0x005E854C) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5___POR 0x72E49630 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_CFBCAL_Q_VDET___POR 0x39 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_CFBCAL_Q_PDET___POR 0x39 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_ISEL_IPTAT25_OP_VDET___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_ISEL_IPTAT25_OP_PDET___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_GAIN_CTRL_PDET_HG___POR 0x0C +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_GAIN_CTRL_PDET_LG___POR 0x0C +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_CFBCAL_Q_VDET___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_CFBCAL_Q_VDET___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_CFBCAL_Q_PDET___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_CFBCAL_Q_PDET___S 18 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_ISEL_IPTAT25_OP_VDET___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_ISEL_IPTAT25_OP_VDET___S 15 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_ISEL_IPTAT25_OP_PDET___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_ISEL_IPTAT25_OP_PDET___S 12 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_GAIN_CTRL_PDET_HG___M 0x00000F80 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_GAIN_CTRL_PDET_HG___S 7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_GAIN_CTRL_PDET_LG___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5__BQ_GAIN_CTRL_PDET_LG___S 2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_TPC5___S 2 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DET_MODE (0x005E8550) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DET_MODE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DET_MODE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DET_MODE__PDET_MODE_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DET_MODE__PDET_MODE_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DET_MODE__PDET_MODE_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DET_MODE___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DET_MODE___S 30 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC (0x005E8554) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC___POR 0xDADB7400 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_TIA_BW___POR 0x6 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_BW___POR 0x6 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_CC1ADJ___POR 0x5 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_CC2ADJ___POR 0x5 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_ZR1___POR 0x5 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_ZR2___POR 0x5 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_SELQ___POR 0x6 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BOOST_BQ___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_TIA_BW___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_TIA_BW___S 29 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_BW___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_BW___S 26 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_CC1ADJ___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_CC1ADJ___S 23 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_CC2ADJ___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_CC2ADJ___S 20 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_ZR1___M 0x000E0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_ZR1___S 17 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_ZR2___M 0x0001C000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_ZR2___S 14 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_SELQ___M 0x00003800 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BQ_SELQ___S 11 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BOOST_BQ___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC__DPD_BOOST_BQ___S 10 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_CH_BW_AC___S 10 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT (0x005E8558) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT___POR 0x00BFF234 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_CCADJ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_CFBCAL___POR 0x005 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ICQADJ___POR 0xF +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_VCMINTADJ___POR 0xF +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_IR25_IP___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_IC25_OP___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_OP_OS___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_IPTAT25_OP___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_CCADJ___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_CCADJ___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_CFBCAL___M 0x3FE00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_CFBCAL___S 21 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ICQADJ___M 0x001E0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ICQADJ___S 17 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_VCMINTADJ___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_VCMINTADJ___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_IR25_IP___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_IR25_IP___S 10 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_IC25_OP___M 0x00000380 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_IC25_OP___S 7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_OP_OS___M 0x00000070 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_OP_OS___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_IPTAT25_OP___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT__DPD_TIA_ISEL_IPTAT25_OP___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA_LUT___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT (0x005E855C) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT___POR 0x2AC01776 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_CFBCAL___POR 0x15 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_OP_OS___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_CIN_CT___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_IP___POR 0x17 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_OP___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_IPTAT25_OP___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_CFBCAL___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_CFBCAL___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_OP_OS___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_OP_OS___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_CIN_CT___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_CIN_CT___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_IP___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_IP___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_OP___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_OP___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_IPTAT25_OP___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT__DPD_BQ_ISEL_IPTAT25_OP___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ_LUT___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA (0x005E8560) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA___POR 0x37000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_TIA_RMCAP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_TIA_RFB_I___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_TIA_RFB_Q___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_TIA_VICMADJ___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_TIA_RMCAP___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_TIA_RMCAP___S 31 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_TIA_RFB_I___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_TIA_RFB_I___S 28 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_TIA_RFB_Q___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_TIA_RFB_Q___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_TIA_VICMADJ___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA__DPD_TIA_VICMADJ___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_TIA___S 22 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ (0x005E8564) +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_VCM_SEL___POR 0x8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_BYPASS___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_BYPASS___S 31 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_VCM_SEL___M 0x78000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ__DPD_BQ_VCM_SEL___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH0_DPD_BQ___S 27 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_TESTREG (0x005E8800) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_TESTREG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_TESTREG___POR 0x22BB1212 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_TESTREG__TESTREG___POR 0x22BB1212 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_TESTREG__TESTREG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_TESTREG__TESTREG___S 0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_TESTREG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_TESTREG___S 0 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_IDX_SEL (0x005E8804) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_IDX_SEL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_IDX_SEL___POR 0x00000010 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_IDX_SEL__BBF_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_IDX_SEL__BBF_GAIN_OVD___POR 0x10 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_IDX_SEL__BBF_GAIN_OV___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_IDX_SEL__BBF_GAIN_OV___S 6 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_IDX_SEL__BBF_GAIN_OVD___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_IDX_SEL__BBF_GAIN_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_IDX_SEL___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_IDX_SEL___S 0 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC_CFG (0x005E8808) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC_CFG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC_CFG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC_CFG__DCOC_FORMAT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC_CFG__DCOC_FORMAT___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC_CFG__DCOC_FORMAT___S 30 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC_CFG___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC_CFG___S 30 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC (0x005E880C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC__DCOC_RES_I_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC__DCOC_RES_I_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC__DCOC_RES_Q_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC__DCOC_RES_Q_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC__DCOC_RES_I_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC__DCOC_RES_I_OV___S 31 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC__DCOC_RES_I_OVD___M 0x7F000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC__DCOC_RES_I_OVD___S 24 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC__DCOC_RES_Q_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC__DCOC_RES_Q_OV___S 23 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC__DCOC_RES_Q_OVD___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC__DCOC_RES_Q_OVD___S 16 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_DCOC___S 16 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0 (0x005E8810) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0___POR 0x04040434 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0__D_TIA_CTUNE___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0__D_BQ_C1_CTUNE___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0__D_BQ_C2_CTUNE___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0__D_IC25U_TIA_SEL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0__D_IC120U_TIA_SEL___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0__D_TIA_CTUNE___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0__D_TIA_CTUNE___S 24 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0__D_BQ_C1_CTUNE___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0__D_BQ_C1_CTUNE___S 16 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0__D_BQ_C2_CTUNE___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0__D_BQ_C2_CTUNE___S 8 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0__D_IC25U_TIA_SEL___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0__D_IC25U_TIA_SEL___S 4 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0__D_IC120U_TIA_SEL___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0__D_IC120U_TIA_SEL___S 0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC0___S 0 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1 (0x005E8814) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1___POR 0x5268DB71 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_TIA_CCOMP___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_TIA_CFWRD___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_IC25U_BQ_SEL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_IC120U_BQ_SEL___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_BQ_R1_RTUNE___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_BQ_R2_RTUNE___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_BQ_R3_RTUNE___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_IC25U_TIA_SLOPE___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_IC25U_BQ_SLOPE___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_IC25U_DCOC_SEL___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_TIA_CCOMP___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_TIA_CCOMP___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_TIA_CFWRD___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_TIA_CFWRD___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_IC25U_BQ_SEL___M 0x01E00000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_IC25U_BQ_SEL___S 21 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_IC120U_BQ_SEL___M 0x001E0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_IC120U_BQ_SEL___S 17 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_BQ_R1_RTUNE___M 0x0001C000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_BQ_R1_RTUNE___S 14 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_BQ_R2_RTUNE___M 0x00003800 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_BQ_R2_RTUNE___S 11 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_BQ_R3_RTUNE___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_BQ_R3_RTUNE___S 8 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_IC25U_TIA_SLOPE___M 0x000000E0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_IC25U_TIA_SLOPE___S 5 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_IC25U_BQ_SLOPE___M 0x0000001C +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_IC25U_BQ_SLOPE___S 2 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_IC25U_DCOC_SEL___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1__D_IC25U_DCOC_SEL___S 0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC1___S 0 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC2 (0x005E8818) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC2___POR 0x2B000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC2__D_BQ_CMFB_POLE_TUNE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC2__D_BQ_CMFB_ZERO_TUNE___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC2__D_TIA_CMFB_POLE_TUNE___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC2__D_TIA_CMFB_ZERO_TUNE___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC2__D_BQ_CMFB_POLE_TUNE___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC2__D_BQ_CMFB_POLE_TUNE___S 30 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC2__D_BQ_CMFB_ZERO_TUNE___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC2__D_BQ_CMFB_ZERO_TUNE___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC2__D_TIA_CMFB_POLE_TUNE___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC2__D_TIA_CMFB_POLE_TUNE___S 26 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC2__D_TIA_CMFB_ZERO_TUNE___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC2__D_TIA_CMFB_ZERO_TUNE___S 24 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC2___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_CH_BW_AC2___S 24 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_0 (0x005E881C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_0___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_0__BQ_CCOMP0___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_0__BQ_CFWRD0___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_0__BQ_CCOMP0___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_0__BQ_CCOMP0___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_0__BQ_CFWRD0___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_0__BQ_CFWRD0___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_0___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_0___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_1 (0x005E8820) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_1___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_1__BQ_CCOMP1___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_1__BQ_CFWRD1___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_1__BQ_CCOMP1___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_1__BQ_CCOMP1___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_1__BQ_CFWRD1___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_1__BQ_CFWRD1___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_1___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_1___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_2 (0x005E8824) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_2___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_2__BQ_CCOMP2___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_2__BQ_CFWRD2___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_2__BQ_CCOMP2___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_2__BQ_CCOMP2___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_2__BQ_CFWRD2___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_2__BQ_CFWRD2___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_2___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_2___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_3 (0x005E8828) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_3___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_3__BQ_CCOMP3___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_3__BQ_CFWRD3___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_3__BQ_CCOMP3___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_3__BQ_CCOMP3___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_3__BQ_CFWRD3___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_3__BQ_CFWRD3___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_3___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_3___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_4 (0x005E882C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_4___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_4__BQ_CCOMP4___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_4__BQ_CFWRD4___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_4__BQ_CCOMP4___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_4__BQ_CCOMP4___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_4__BQ_CFWRD4___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_4__BQ_CFWRD4___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_4___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_4___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_5 (0x005E8830) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_5___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_5__BQ_CCOMP5___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_5__BQ_CFWRD5___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_5__BQ_CCOMP5___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_5__BQ_CCOMP5___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_5__BQ_CFWRD5___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_5__BQ_CFWRD5___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_5___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_5___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_6 (0x005E8834) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_6___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_6__BQ_CCOMP6___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_6__BQ_CFWRD6___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_6__BQ_CCOMP6___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_6__BQ_CCOMP6___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_6__BQ_CFWRD6___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_6__BQ_CFWRD6___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_6___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_6___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_7 (0x005E8838) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_7___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_7__BQ_CCOMP7___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_7__BQ_CFWRD7___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_7__BQ_CCOMP7___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_7__BQ_CCOMP7___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_7__BQ_CFWRD7___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_7__BQ_CFWRD7___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_7___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_7___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_8 (0x005E883C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_8___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_8__BQ_CCOMP8___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_8__BQ_CFWRD8___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_8__BQ_CCOMP8___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_8__BQ_CCOMP8___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_8__BQ_CFWRD8___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_8__BQ_CFWRD8___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_8___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_8___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_9 (0x005E8840) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_9___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_9__BQ_CCOMP9___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_9__BQ_CFWRD9___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_9__BQ_CCOMP9___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_9__BQ_CCOMP9___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_9__BQ_CFWRD9___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_9__BQ_CFWRD9___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_9___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_9___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_10 (0x005E8844) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_10___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_10__BQ_CCOMP10___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_10__BQ_CFWRD10___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_10__BQ_CCOMP10___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_10__BQ_CCOMP10___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_10__BQ_CFWRD10___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_10__BQ_CFWRD10___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_10___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_10___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_11 (0x005E8848) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_11___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_11__BQ_CCOMP11___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_11__BQ_CFWRD11___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_11__BQ_CCOMP11___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_11__BQ_CCOMP11___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_11__BQ_CFWRD11___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_11__BQ_CFWRD11___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_11___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_11___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_12 (0x005E884C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_12___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_12__BQ_CCOMP12___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_12__BQ_CFWRD12___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_12__BQ_CCOMP12___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_12__BQ_CCOMP12___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_12__BQ_CFWRD12___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_12__BQ_CFWRD12___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_12___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_12___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_13 (0x005E8850) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_13___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_13__BQ_CCOMP13___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_13__BQ_CFWRD13___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_13__BQ_CCOMP13___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_13__BQ_CCOMP13___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_13__BQ_CFWRD13___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_13__BQ_CFWRD13___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_13___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_13___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_14 (0x005E8854) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_14___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_14__BQ_CCOMP14___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_14__BQ_CFWRD14___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_14__BQ_CCOMP14___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_14__BQ_CCOMP14___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_14__BQ_CFWRD14___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_14__BQ_CFWRD14___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_14___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_14___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_15 (0x005E8858) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_15___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_15__BQ_CCOMP15___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_15__BQ_CFWRD15___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_15__BQ_CCOMP15___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_15__BQ_CCOMP15___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_15__BQ_CFWRD15___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_15__BQ_CFWRD15___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_15___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_15___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_16 (0x005E885C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_16___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_16__BQ_CCOMP16___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_16__BQ_CFWRD16___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_16__BQ_CCOMP16___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_16__BQ_CCOMP16___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_16__BQ_CFWRD16___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_16__BQ_CFWRD16___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_16___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_16___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_17 (0x005E8860) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_17___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_17__BQ_CCOMP17___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_17__BQ_CFWRD17___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_17__BQ_CCOMP17___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_17__BQ_CCOMP17___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_17__BQ_CFWRD17___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_17__BQ_CFWRD17___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_17___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_17___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_18 (0x005E8864) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_18___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_18__BQ_CCOMP18___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_18__BQ_CFWRD18___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_18__BQ_CCOMP18___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_18__BQ_CCOMP18___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_18__BQ_CFWRD18___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_18__BQ_CFWRD18___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_18___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_18___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_19 (0x005E8868) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_19___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_19__BQ_CCOMP19___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_19__BQ_CFWRD19___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_19__BQ_CCOMP19___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_19__BQ_CCOMP19___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_19__BQ_CFWRD19___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_19__BQ_CFWRD19___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_19___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_19___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_20 (0x005E886C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_20___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_20__BQ_CCOMP20___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_20__BQ_CFWRD20___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_20__BQ_CCOMP20___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_20__BQ_CCOMP20___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_20__BQ_CFWRD20___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_20__BQ_CFWRD20___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_20___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_20___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_21 (0x005E8870) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_21___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_21__BQ_CCOMP21___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_21__BQ_CFWRD21___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_21__BQ_CCOMP21___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_21__BQ_CCOMP21___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_21__BQ_CFWRD21___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_21__BQ_CFWRD21___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_21___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_21___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_22 (0x005E8874) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_22___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_22__BQ_CCOMP22___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_22__BQ_CFWRD22___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_22__BQ_CCOMP22___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_22__BQ_CCOMP22___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_22__BQ_CFWRD22___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_22__BQ_CFWRD22___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_22___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_22___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_23 (0x005E8878) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_23___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_23__BQ_CCOMP23___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_23__BQ_CFWRD23___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_23__BQ_CCOMP23___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_23__BQ_CCOMP23___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_23__BQ_CFWRD23___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_23__BQ_CFWRD23___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_23___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_23___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_24 (0x005E887C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_24___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_24__BQ_CCOMP24___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_24__BQ_CFWRD24___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_24__BQ_CCOMP24___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_24__BQ_CCOMP24___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_24__BQ_CFWRD24___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_24__BQ_CFWRD24___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_24___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_24___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_25 (0x005E8880) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_25___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_25__BQ_CCOMP25___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_25__BQ_CFWRD25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_25__BQ_CCOMP25___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_25__BQ_CCOMP25___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_25__BQ_CFWRD25___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_25__BQ_CFWRD25___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_25___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_25___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_26 (0x005E8884) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_26___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_26__BQ_CCOMP26___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_26__BQ_CFWRD26___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_26__BQ_CCOMP26___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_26__BQ_CCOMP26___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_26__BQ_CFWRD26___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_26__BQ_CFWRD26___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_26___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_26___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_27 (0x005E8888) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_27___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_27__BQ_CCOMP27___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_27__BQ_CFWRD27___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_27__BQ_CCOMP27___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_27__BQ_CCOMP27___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_27__BQ_CFWRD27___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_27__BQ_CFWRD27___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_27___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_27___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_28 (0x005E888C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_28___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_28__BQ_CCOMP28___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_28__BQ_CFWRD28___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_28__BQ_CCOMP28___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_28__BQ_CCOMP28___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_28__BQ_CFWRD28___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_28__BQ_CFWRD28___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_28___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_28___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_29 (0x005E8890) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_29___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_29__BQ_CCOMP29___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_29__BQ_CFWRD29___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_29__BQ_CCOMP29___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_29__BQ_CCOMP29___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_29__BQ_CFWRD29___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_29__BQ_CFWRD29___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_29___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_29___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_30 (0x005E8894) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_30___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_30__BQ_CCOMP30___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_30__BQ_CFWRD30___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_30__BQ_CCOMP30___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_30__BQ_CCOMP30___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_30__BQ_CFWRD30___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_30__BQ_CFWRD30___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_30___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_30___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_31 (0x005E8898) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_31___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_31__BQ_CCOMP31___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_31__BQ_CFWRD31___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_31__BQ_CCOMP31___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_31__BQ_CCOMP31___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_31__BQ_CFWRD31___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_31__BQ_CFWRD31___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_31___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_31___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_32 (0x005E889C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_32___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_32___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_32__BQ_CCOMP32___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_32__BQ_CFWRD32___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_32__BQ_CCOMP32___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_32__BQ_CCOMP32___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_32__BQ_CFWRD32___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_32__BQ_CFWRD32___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_32___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_32___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_33 (0x005E88A0) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_33___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_33___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_33__BQ_CCOMP33___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_33__BQ_CFWRD33___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_33__BQ_CCOMP33___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_33__BQ_CCOMP33___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_33__BQ_CFWRD33___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_33__BQ_CFWRD33___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_33___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_33___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_34 (0x005E88A4) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_34___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_34___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_34__BQ_CCOMP34___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_34__BQ_CFWRD34___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_34__BQ_CCOMP34___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_34__BQ_CCOMP34___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_34__BQ_CFWRD34___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_34__BQ_CFWRD34___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_34___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_34___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_35 (0x005E88A8) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_35___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_35___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_35__BQ_CCOMP35___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_35__BQ_CFWRD35___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_35__BQ_CCOMP35___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_35__BQ_CCOMP35___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_35__BQ_CFWRD35___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_35__BQ_CFWRD35___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_35___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_35___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_36 (0x005E88AC) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_36___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_36___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_36__BQ_CCOMP36___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_36__BQ_CFWRD36___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_36__BQ_CCOMP36___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_36__BQ_CCOMP36___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_36__BQ_CFWRD36___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_36__BQ_CFWRD36___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_36___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_36___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_37 (0x005E88B0) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_37___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_37___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_37__BQ_CCOMP37___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_37__BQ_CFWRD37___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_37__BQ_CCOMP37___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_37__BQ_CCOMP37___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_37__BQ_CFWRD37___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_37__BQ_CFWRD37___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_37___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_37___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_38 (0x005E88B4) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_38___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_38___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_38__BQ_CCOMP38___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_38__BQ_CFWRD38___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_38__BQ_CCOMP38___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_38__BQ_CCOMP38___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_38__BQ_CFWRD38___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_38__BQ_CFWRD38___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_38___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_38___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_39 (0x005E88B8) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_39___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_39___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_39__BQ_CCOMP39___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_39__BQ_CFWRD39___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_39__BQ_CCOMP39___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_39__BQ_CCOMP39___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_39__BQ_CFWRD39___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_39__BQ_CFWRD39___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_39___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_39___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_40 (0x005E88BC) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_40___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_40___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_40__BQ_CCOMP40___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_40__BQ_CFWRD40___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_40__BQ_CCOMP40___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_40__BQ_CCOMP40___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_40__BQ_CFWRD40___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_40__BQ_CFWRD40___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_40___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_40___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_41 (0x005E88C0) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_41___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_41___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_41__BQ_CCOMP41___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_41__BQ_CFWRD41___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_41__BQ_CCOMP41___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_41__BQ_CCOMP41___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_41__BQ_CFWRD41___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_41__BQ_CFWRD41___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_41___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_41___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_42 (0x005E88C4) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_42___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_42___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_42__BQ_CCOMP42___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_42__BQ_CFWRD42___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_42__BQ_CCOMP42___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_42__BQ_CCOMP42___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_42__BQ_CFWRD42___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_42__BQ_CFWRD42___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_42___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_42___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_43 (0x005E88C8) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_43___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_43___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_43__BQ_CCOMP43___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_43__BQ_CFWRD43___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_43__BQ_CCOMP43___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_43__BQ_CCOMP43___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_43__BQ_CFWRD43___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_43__BQ_CFWRD43___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_43___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_43___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_44 (0x005E88CC) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_44___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_44___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_44__BQ_CCOMP44___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_44__BQ_CFWRD44___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_44__BQ_CCOMP44___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_44__BQ_CCOMP44___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_44__BQ_CFWRD44___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_44__BQ_CFWRD44___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_44___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_44___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_45 (0x005E88D0) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_45___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_45___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_45__BQ_CCOMP45___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_45__BQ_CFWRD45___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_45__BQ_CCOMP45___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_45__BQ_CCOMP45___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_45__BQ_CFWRD45___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_45__BQ_CFWRD45___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_45___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_45___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_46 (0x005E88D4) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_46___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_46___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_46__BQ_CCOMP46___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_46__BQ_CFWRD46___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_46__BQ_CCOMP46___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_46__BQ_CCOMP46___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_46__BQ_CFWRD46___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_46__BQ_CFWRD46___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_46___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_46___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_47 (0x005E88D8) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_47___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_47___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_47__BQ_CCOMP47___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_47__BQ_CFWRD47___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_47__BQ_CCOMP47___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_47__BQ_CCOMP47___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_47__BQ_CFWRD47___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_47__BQ_CFWRD47___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_47___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_47___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_48 (0x005E88DC) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_48___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_48___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_48__BQ_CCOMP48___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_48__BQ_CFWRD48___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_48__BQ_CCOMP48___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_48__BQ_CCOMP48___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_48__BQ_CFWRD48___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_48__BQ_CFWRD48___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_48___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_48___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_49 (0x005E88E0) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_49___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_49___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_49__BQ_CCOMP49___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_49__BQ_CFWRD49___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_49__BQ_CCOMP49___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_49__BQ_CCOMP49___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_49__BQ_CFWRD49___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_49__BQ_CFWRD49___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_49___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_49___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_50 (0x005E88E4) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_50___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_50___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_50__BQ_CCOMP50___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_50__BQ_CFWRD50___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_50__BQ_CCOMP50___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_50__BQ_CCOMP50___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_50__BQ_CFWRD50___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_50__BQ_CFWRD50___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_50___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_50___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_51 (0x005E88E8) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_51___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_51___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_51__BQ_CCOMP51___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_51__BQ_CFWRD51___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_51__BQ_CCOMP51___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_51__BQ_CCOMP51___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_51__BQ_CFWRD51___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_51__BQ_CFWRD51___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_51___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_51___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_52 (0x005E88EC) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_52___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_52___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_52__BQ_CCOMP52___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_52__BQ_CFWRD52___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_52__BQ_CCOMP52___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_52__BQ_CCOMP52___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_52__BQ_CFWRD52___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_52__BQ_CFWRD52___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_52___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_52___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_53 (0x005E88F0) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_53___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_53___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_53__BQ_CCOMP53___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_53__BQ_CFWRD53___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_53__BQ_CCOMP53___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_53__BQ_CCOMP53___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_53__BQ_CFWRD53___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_53__BQ_CFWRD53___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_53___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_53___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_54 (0x005E88F4) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_54___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_54___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_54__BQ_CCOMP54___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_54__BQ_CFWRD54___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_54__BQ_CCOMP54___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_54__BQ_CCOMP54___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_54__BQ_CFWRD54___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_54__BQ_CFWRD54___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_54___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_54___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_55 (0x005E88F8) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_55___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_55___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_55__BQ_CCOMP55___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_55__BQ_CFWRD55___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_55__BQ_CCOMP55___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_55__BQ_CCOMP55___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_55__BQ_CFWRD55___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_55__BQ_CFWRD55___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_55___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_55___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_56 (0x005E88FC) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_56___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_56___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_56__BQ_CCOMP56___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_56__BQ_CFWRD56___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_56__BQ_CCOMP56___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_56__BQ_CCOMP56___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_56__BQ_CFWRD56___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_56__BQ_CFWRD56___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_56___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_56___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_57 (0x005E8900) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_57___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_57___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_57__BQ_CCOMP57___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_57__BQ_CFWRD57___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_57__BQ_CCOMP57___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_57__BQ_CCOMP57___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_57__BQ_CFWRD57___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_57__BQ_CFWRD57___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_57___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_57___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_58 (0x005E8904) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_58___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_58___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_58__BQ_CCOMP58___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_58__BQ_CFWRD58___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_58__BQ_CCOMP58___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_58__BQ_CCOMP58___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_58__BQ_CFWRD58___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_58__BQ_CFWRD58___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_58___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_58___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_59 (0x005E8908) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_59___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_59___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_59__BQ_CCOMP59___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_59__BQ_CFWRD59___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_59__BQ_CCOMP59___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_59__BQ_CCOMP59___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_59__BQ_CFWRD59___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_59__BQ_CFWRD59___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_59___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_59___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_60 (0x005E890C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_60___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_60___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_60__BQ_CCOMP60___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_60__BQ_CFWRD60___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_60__BQ_CCOMP60___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_60__BQ_CCOMP60___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_60__BQ_CFWRD60___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_60__BQ_CFWRD60___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_60___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_60___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_61 (0x005E8910) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_61___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_61___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_61__BQ_CCOMP61___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_61__BQ_CFWRD61___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_61__BQ_CCOMP61___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_61__BQ_CCOMP61___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_61__BQ_CFWRD61___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_61__BQ_CFWRD61___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_61___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_61___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_62 (0x005E8914) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_62___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_62___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_62__BQ_CCOMP62___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_62__BQ_CFWRD62___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_62__BQ_CCOMP62___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_62__BQ_CCOMP62___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_62__BQ_CFWRD62___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_62__BQ_CFWRD62___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_62___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_62___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_63 (0x005E8918) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_63___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_63___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_63__BQ_CCOMP63___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_63__BQ_CFWRD63___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_63__BQ_CCOMP63___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_63__BQ_CCOMP63___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_63__BQ_CFWRD63___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_63__BQ_CFWRD63___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_63___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BBF_GAIN_63___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_0 (0x005E891C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_0__ATTEN_SWA0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_0__ATTEN_SWB0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_0__ATTEN_SWA0___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_0__ATTEN_SWA0___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_0__ATTEN_SWB0___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_0__ATTEN_SWB0___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_0___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_0___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_1 (0x005E8920) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_1__ATTEN_SWA1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_1__ATTEN_SWB1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_1__ATTEN_SWA1___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_1__ATTEN_SWA1___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_1__ATTEN_SWB1___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_1__ATTEN_SWB1___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_1___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_1___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_2 (0x005E8924) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_2__ATTEN_SWA2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_2__ATTEN_SWB2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_2__ATTEN_SWA2___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_2__ATTEN_SWA2___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_2__ATTEN_SWB2___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_2__ATTEN_SWB2___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_2___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_2___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_3 (0x005E8928) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_3__ATTEN_SWA3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_3__ATTEN_SWB3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_3__ATTEN_SWA3___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_3__ATTEN_SWA3___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_3__ATTEN_SWB3___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_3__ATTEN_SWB3___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_3___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_3___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_4 (0x005E892C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_4__ATTEN_SWA4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_4__ATTEN_SWB4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_4__ATTEN_SWA4___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_4__ATTEN_SWA4___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_4__ATTEN_SWB4___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_4__ATTEN_SWB4___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_4___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_4___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_5 (0x005E8930) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_5__ATTEN_SWA5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_5__ATTEN_SWB5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_5__ATTEN_SWA5___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_5__ATTEN_SWA5___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_5__ATTEN_SWB5___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_5__ATTEN_SWB5___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_5___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_5___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_6 (0x005E8934) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_6__ATTEN_SWA6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_6__ATTEN_SWB6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_6__ATTEN_SWA6___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_6__ATTEN_SWA6___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_6__ATTEN_SWB6___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_6__ATTEN_SWB6___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_6___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_6___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_7 (0x005E8938) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_7__ATTEN_SWA7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_7__ATTEN_SWB7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_7__ATTEN_SWA7___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_7__ATTEN_SWA7___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_7__ATTEN_SWB7___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_7__ATTEN_SWB7___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_7___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_7___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_8 (0x005E893C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_8__ATTEN_SWA8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_8__ATTEN_SWB8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_8__ATTEN_SWA8___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_8__ATTEN_SWA8___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_8__ATTEN_SWB8___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_8__ATTEN_SWB8___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_8___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_8___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_9 (0x005E8940) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_9__ATTEN_SWA9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_9__ATTEN_SWB9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_9__ATTEN_SWA9___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_9__ATTEN_SWA9___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_9__ATTEN_SWB9___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_9__ATTEN_SWB9___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_9___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_9___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_10 (0x005E8944) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_10__ATTEN_SWA10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_10__ATTEN_SWB10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_10__ATTEN_SWA10___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_10__ATTEN_SWA10___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_10__ATTEN_SWB10___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_10__ATTEN_SWB10___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_10___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_10___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_11 (0x005E8948) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_11___POR 0x42400000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_11__ATTEN_SWA11___POR 0x21 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_11__ATTEN_SWB11___POR 0x10 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_11__ATTEN_SWA11___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_11__ATTEN_SWA11___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_11__ATTEN_SWB11___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_11__ATTEN_SWB11___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_11___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_11___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_12 (0x005E894C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_12___POR 0x40200000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_12__ATTEN_SWA12___POR 0x20 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_12__ATTEN_SWB12___POR 0x08 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_12__ATTEN_SWA12___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_12__ATTEN_SWA12___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_12__ATTEN_SWB12___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_12__ATTEN_SWB12___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_12___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_12___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_13 (0x005E8950) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_13___POR 0x10080000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_13__ATTEN_SWA13___POR 0x08 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_13__ATTEN_SWB13___POR 0x02 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_13__ATTEN_SWA13___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_13__ATTEN_SWA13___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_13__ATTEN_SWB13___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_13__ATTEN_SWB13___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_13___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_13___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_14 (0x005E8954) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_14___POR 0x08040000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_14__ATTEN_SWA14___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_14__ATTEN_SWB14___POR 0x01 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_14__ATTEN_SWA14___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_14__ATTEN_SWA14___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_14__ATTEN_SWB14___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_14__ATTEN_SWB14___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_14___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_14___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_15 (0x005E8958) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_15___POR 0x04000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_15__ATTEN_SWA15___POR 0x02 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_15__ATTEN_SWB15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_15__ATTEN_SWA15___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_15__ATTEN_SWA15___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_15__ATTEN_SWB15___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_15__ATTEN_SWB15___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_15___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_15___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_16 (0x005E895C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_16___POR 0x40100000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_16__ATTEN_SWA16___POR 0x20 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_16__ATTEN_SWB16___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_16__ATTEN_SWA16___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_16__ATTEN_SWA16___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_16__ATTEN_SWB16___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_16__ATTEN_SWB16___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_16___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_16___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_17 (0x005E8960) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_17___POR 0x20080000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_17__ATTEN_SWA17___POR 0x10 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_17__ATTEN_SWB17___POR 0x02 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_17__ATTEN_SWA17___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_17__ATTEN_SWA17___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_17__ATTEN_SWB17___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_17__ATTEN_SWB17___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_17___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_17___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_18 (0x005E8964) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_18___POR 0x42100000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_18__ATTEN_SWA18___POR 0x21 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_18__ATTEN_SWB18___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_18__ATTEN_SWA18___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_18__ATTEN_SWA18___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_18__ATTEN_SWB18___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_18__ATTEN_SWB18___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_18___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_18___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_19 (0x005E8968) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_19___POR 0x80200000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_19__ATTEN_SWA19___POR 0x40 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_19__ATTEN_SWB19___POR 0x08 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_19__ATTEN_SWA19___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_19__ATTEN_SWA19___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_19__ATTEN_SWB19___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_19__ATTEN_SWB19___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_19___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_19___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_20 (0x005E896C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_20___POR 0x44100000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_20__ATTEN_SWA20___POR 0x22 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_20__ATTEN_SWB20___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_20__ATTEN_SWA20___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_20__ATTEN_SWA20___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_20__ATTEN_SWB20___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_20__ATTEN_SWB20___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_20___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_20___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_21 (0x005E8970) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_21___POR 0x30100000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_21__ATTEN_SWA21___POR 0x18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_21__ATTEN_SWB21___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_21__ATTEN_SWA21___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_21__ATTEN_SWA21___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_21__ATTEN_SWB21___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_21__ATTEN_SWB21___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_21___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_21___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_22 (0x005E8974) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_22___POR 0x50100000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_22__ATTEN_SWA22___POR 0x28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_22__ATTEN_SWB22___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_22__ATTEN_SWA22___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_22__ATTEN_SWA22___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_22__ATTEN_SWB22___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_22__ATTEN_SWB22___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_22___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_22___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_23 (0x005E8978) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_23___POR 0x84100000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_23__ATTEN_SWA23___POR 0x42 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_23__ATTEN_SWB23___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_23__ATTEN_SWA23___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_23__ATTEN_SWA23___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_23__ATTEN_SWB23___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_23__ATTEN_SWB23___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_23___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_23___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_24 (0x005E897C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_24___POR 0x90100000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_24__ATTEN_SWA24___POR 0x48 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_24__ATTEN_SWB24___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_24__ATTEN_SWA24___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_24__ATTEN_SWA24___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_24__ATTEN_SWB24___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_24__ATTEN_SWB24___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_24___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_24___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_25 (0x005E8980) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_25___POR 0x88080000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_25__ATTEN_SWA25___POR 0x44 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_25__ATTEN_SWB25___POR 0x02 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_25__ATTEN_SWA25___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_25__ATTEN_SWA25___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_25__ATTEN_SWB25___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_25__ATTEN_SWB25___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_25___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_25___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_26 (0x005E8984) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_26___POR 0x88040000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_26__ATTEN_SWA26___POR 0x44 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_26__ATTEN_SWB26___POR 0x01 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_26__ATTEN_SWA26___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_26__ATTEN_SWA26___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_26__ATTEN_SWB26___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_26__ATTEN_SWB26___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_26___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_26___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_27 (0x005E8988) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_27___POR 0xA0040000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_27__ATTEN_SWA27___POR 0x50 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_27__ATTEN_SWB27___POR 0x01 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_27__ATTEN_SWA27___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_27__ATTEN_SWA27___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_27__ATTEN_SWB27___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_27__ATTEN_SWB27___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_27___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_27___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_28 (0x005E898C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_28___POR 0xC8040000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_28__ATTEN_SWA28___POR 0x64 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_28__ATTEN_SWB28___POR 0x01 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_28__ATTEN_SWA28___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_28__ATTEN_SWA28___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_28__ATTEN_SWB28___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_28__ATTEN_SWB28___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_28___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_28___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_29 (0x005E8990) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_29___POR 0xD8040000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_29__ATTEN_SWA29___POR 0x6C +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_29__ATTEN_SWB29___POR 0x01 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_29__ATTEN_SWA29___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_29__ATTEN_SWA29___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_29__ATTEN_SWB29___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_29__ATTEN_SWB29___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_29___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_29___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_30 (0x005E8994) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_30___POR 0xF2000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_30__ATTEN_SWA30___POR 0x79 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_30__ATTEN_SWB30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_30__ATTEN_SWA30___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_30__ATTEN_SWA30___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_30__ATTEN_SWB30___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_30__ATTEN_SWB30___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_30___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_30___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_31 (0x005E8998) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_31___POR 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_31__ATTEN_SWA31___POR 0x7F +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_31__ATTEN_SWB31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_31__ATTEN_SWA31___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_31__ATTEN_SWA31___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_31__ATTEN_SWB31___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_31__ATTEN_SWB31___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_31___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_31___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_32 (0x005E899C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_32___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_32___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_32__ATTEN_SWA32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_32__ATTEN_SWB32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_32__ATTEN_SWA32___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_32__ATTEN_SWA32___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_32__ATTEN_SWB32___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_32__ATTEN_SWB32___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_32___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_32___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_33 (0x005E89A0) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_33___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_33___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_33__ATTEN_SWA33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_33__ATTEN_SWB33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_33__ATTEN_SWA33___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_33__ATTEN_SWA33___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_33__ATTEN_SWB33___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_33__ATTEN_SWB33___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_33___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_33___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_34 (0x005E89A4) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_34___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_34___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_34__ATTEN_SWA34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_34__ATTEN_SWB34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_34__ATTEN_SWA34___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_34__ATTEN_SWA34___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_34__ATTEN_SWB34___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_34__ATTEN_SWB34___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_34___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_34___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_35 (0x005E89A8) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_35___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_35___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_35__ATTEN_SWA35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_35__ATTEN_SWB35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_35__ATTEN_SWA35___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_35__ATTEN_SWA35___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_35__ATTEN_SWB35___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_35__ATTEN_SWB35___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_35___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_35___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_36 (0x005E89AC) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_36___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_36___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_36__ATTEN_SWA36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_36__ATTEN_SWB36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_36__ATTEN_SWA36___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_36__ATTEN_SWA36___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_36__ATTEN_SWB36___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_36__ATTEN_SWB36___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_36___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_36___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_37 (0x005E89B0) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_37___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_37___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_37__ATTEN_SWA37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_37__ATTEN_SWB37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_37__ATTEN_SWA37___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_37__ATTEN_SWA37___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_37__ATTEN_SWB37___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_37__ATTEN_SWB37___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_37___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_37___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_38 (0x005E89B4) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_38___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_38___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_38__ATTEN_SWA38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_38__ATTEN_SWB38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_38__ATTEN_SWA38___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_38__ATTEN_SWA38___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_38__ATTEN_SWB38___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_38__ATTEN_SWB38___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_38___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_38___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_39 (0x005E89B8) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_39___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_39___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_39__ATTEN_SWA39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_39__ATTEN_SWB39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_39__ATTEN_SWA39___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_39__ATTEN_SWA39___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_39__ATTEN_SWB39___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_39__ATTEN_SWB39___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_39___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_39___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_40 (0x005E89BC) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_40___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_40___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_40__ATTEN_SWA40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_40__ATTEN_SWB40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_40__ATTEN_SWA40___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_40__ATTEN_SWA40___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_40__ATTEN_SWB40___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_40__ATTEN_SWB40___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_40___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_40___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_41 (0x005E89C0) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_41___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_41___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_41__ATTEN_SWA41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_41__ATTEN_SWB41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_41__ATTEN_SWA41___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_41__ATTEN_SWA41___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_41__ATTEN_SWB41___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_41__ATTEN_SWB41___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_41___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_41___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_42 (0x005E89C4) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_42___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_42___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_42__ATTEN_SWA42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_42__ATTEN_SWB42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_42__ATTEN_SWA42___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_42__ATTEN_SWA42___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_42__ATTEN_SWB42___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_42__ATTEN_SWB42___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_42___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_42___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_43 (0x005E89C8) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_43___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_43___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_43__ATTEN_SWA43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_43__ATTEN_SWB43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_43__ATTEN_SWA43___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_43__ATTEN_SWA43___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_43__ATTEN_SWB43___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_43__ATTEN_SWB43___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_43___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_43___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_44 (0x005E89CC) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_44___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_44___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_44__ATTEN_SWA44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_44__ATTEN_SWB44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_44__ATTEN_SWA44___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_44__ATTEN_SWA44___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_44__ATTEN_SWB44___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_44__ATTEN_SWB44___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_44___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_44___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_45 (0x005E89D0) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_45___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_45___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_45__ATTEN_SWA45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_45__ATTEN_SWB45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_45__ATTEN_SWA45___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_45__ATTEN_SWA45___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_45__ATTEN_SWB45___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_45__ATTEN_SWB45___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_45___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_45___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_46 (0x005E89D4) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_46___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_46___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_46__ATTEN_SWA46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_46__ATTEN_SWB46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_46__ATTEN_SWA46___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_46__ATTEN_SWA46___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_46__ATTEN_SWB46___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_46__ATTEN_SWB46___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_46___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_46___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_47 (0x005E89D8) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_47___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_47___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_47__ATTEN_SWA47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_47__ATTEN_SWB47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_47__ATTEN_SWA47___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_47__ATTEN_SWA47___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_47__ATTEN_SWB47___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_47__ATTEN_SWB47___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_47___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_47___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_48 (0x005E89DC) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_48___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_48___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_48__ATTEN_SWA48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_48__ATTEN_SWB48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_48__ATTEN_SWA48___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_48__ATTEN_SWA48___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_48__ATTEN_SWB48___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_48__ATTEN_SWB48___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_48___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_48___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_49 (0x005E89E0) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_49___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_49___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_49__ATTEN_SWA49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_49__ATTEN_SWB49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_49__ATTEN_SWA49___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_49__ATTEN_SWA49___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_49__ATTEN_SWB49___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_49__ATTEN_SWB49___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_49___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_49___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_50 (0x005E89E4) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_50___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_50___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_50__ATTEN_SWA50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_50__ATTEN_SWB50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_50__ATTEN_SWA50___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_50__ATTEN_SWA50___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_50__ATTEN_SWB50___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_50__ATTEN_SWB50___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_50___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_50___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_51 (0x005E89E8) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_51___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_51___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_51__ATTEN_SWA51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_51__ATTEN_SWB51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_51__ATTEN_SWA51___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_51__ATTEN_SWA51___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_51__ATTEN_SWB51___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_51__ATTEN_SWB51___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_51___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_51___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_52 (0x005E89EC) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_52___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_52___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_52__ATTEN_SWA52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_52__ATTEN_SWB52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_52__ATTEN_SWA52___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_52__ATTEN_SWA52___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_52__ATTEN_SWB52___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_52__ATTEN_SWB52___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_52___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_52___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_53 (0x005E89F0) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_53___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_53___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_53__ATTEN_SWA53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_53__ATTEN_SWB53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_53__ATTEN_SWA53___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_53__ATTEN_SWA53___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_53__ATTEN_SWB53___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_53__ATTEN_SWB53___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_53___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_53___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_54 (0x005E89F4) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_54___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_54___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_54__ATTEN_SWA54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_54__ATTEN_SWB54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_54__ATTEN_SWA54___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_54__ATTEN_SWA54___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_54__ATTEN_SWB54___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_54__ATTEN_SWB54___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_54___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_54___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_55 (0x005E89F8) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_55___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_55___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_55__ATTEN_SWA55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_55__ATTEN_SWB55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_55__ATTEN_SWA55___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_55__ATTEN_SWA55___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_55__ATTEN_SWB55___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_55__ATTEN_SWB55___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_55___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_55___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_56 (0x005E89FC) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_56___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_56___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_56__ATTEN_SWA56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_56__ATTEN_SWB56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_56__ATTEN_SWA56___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_56__ATTEN_SWA56___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_56__ATTEN_SWB56___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_56__ATTEN_SWB56___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_56___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_56___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_57 (0x005E8A00) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_57___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_57___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_57__ATTEN_SWA57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_57__ATTEN_SWB57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_57__ATTEN_SWA57___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_57__ATTEN_SWA57___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_57__ATTEN_SWB57___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_57__ATTEN_SWB57___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_57___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_57___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_58 (0x005E8A04) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_58___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_58___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_58__ATTEN_SWA58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_58__ATTEN_SWB58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_58__ATTEN_SWA58___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_58__ATTEN_SWA58___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_58__ATTEN_SWB58___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_58__ATTEN_SWB58___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_58___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_58___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_59 (0x005E8A08) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_59___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_59___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_59__ATTEN_SWA59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_59__ATTEN_SWB59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_59__ATTEN_SWA59___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_59__ATTEN_SWA59___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_59__ATTEN_SWB59___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_59__ATTEN_SWB59___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_59___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_59___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_60 (0x005E8A0C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_60___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_60___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_60__ATTEN_SWA60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_60__ATTEN_SWB60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_60__ATTEN_SWA60___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_60__ATTEN_SWA60___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_60__ATTEN_SWB60___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_60__ATTEN_SWB60___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_60___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_60___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_61 (0x005E8A10) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_61___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_61___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_61__ATTEN_SWA61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_61__ATTEN_SWB61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_61__ATTEN_SWA61___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_61__ATTEN_SWA61___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_61__ATTEN_SWB61___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_61__ATTEN_SWB61___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_61___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_61___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_62 (0x005E8A14) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_62___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_62___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_62__ATTEN_SWA62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_62__ATTEN_SWB62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_62__ATTEN_SWA62___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_62__ATTEN_SWA62___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_62__ATTEN_SWB62___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_62__ATTEN_SWB62___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_62___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_62___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_63 (0x005E8A18) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_63___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_63___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_63__ATTEN_SWA63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_63__ATTEN_SWB63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_63__ATTEN_SWA63___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_63__ATTEN_SWA63___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_63__ATTEN_SWB63___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_63__ATTEN_SWB63___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_63___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATTEN_GAIN_63___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV0 (0x005E8A1C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV0__BQ_CCOMP_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV0__BQ_CCOMP_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV0__BQ_CFWRD_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV0__BQ_CFWRD_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV0__BQ_CCOMP_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV0__BQ_CCOMP_OV___S 31 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV0__BQ_CCOMP_OVD___M 0x78000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV0__BQ_CCOMP_OVD___S 27 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV0__BQ_CFWRD_OV___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV0__BQ_CFWRD_OV___S 26 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV0__BQ_CFWRD_OVD___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV0__BQ_CFWRD_OVD___S 23 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV0___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV0___S 23 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV1 (0x005E8A20) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV1__ATTEN_SWA_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV1__ATTEN_SWA_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV1__ATTEN_SWB_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV1__ATTEN_SWB_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV1__ATTEN_SWA_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV1__ATTEN_SWA_OV___S 31 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV1__ATTEN_SWA_OVD___M 0x7F000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV1__ATTEN_SWA_OVD___S 24 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV1__ATTEN_SWB_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV1__ATTEN_SWB_OV___S 23 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV1__ATTEN_SWB_OVD___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV1__ATTEN_SWB_OVD___S 16 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV1___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_LUT_OV1___S 16 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0 (0x005E8A24) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__BBF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__BQ_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__PEF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__DCOC_DAC_EN_I_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__DCOC_DAC_EN_Q_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__TIA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__BBF_BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__TIA_HSW_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__BQ_HSW_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__BBF_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__BBF_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__BQ_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__BQ_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__PEF_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__PEF_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__DCOC_DAC_EN_I_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__DCOC_DAC_EN_I_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__DCOC_DAC_EN_Q_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__DCOC_DAC_EN_Q_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__TIA_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__TIA_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__BBF_BIAS_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__BBF_BIAS_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__TIA_HSW_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__TIA_HSW_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__BQ_HSW_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0__BQ_HSW_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0___M 0xFFFFC000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_EN0___S 14 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT (0x005E8A28) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT__RO_BQ_CCOMP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT__RO_BQ_CFWRD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT__RO_ATTEN_SWA___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT__RO_ATTEN_SWB___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT__RO_BBF_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT__RO_BQ_CCOMP___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT__RO_BQ_CCOMP___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT__RO_BQ_CFWRD___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT__RO_BQ_CFWRD___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT__RO_ATTEN_SWA___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT__RO_ATTEN_SWA___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT__RO_ATTEN_SWB___M 0x0003F800 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT__RO_ATTEN_SWB___S 11 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT__RO_BBF_GAIN___M 0x000007E0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT__RO_BBF_GAIN___S 5 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT___M 0xFFFFFFE0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_RO_LUT___S 5 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0 (0x005E8A30) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0___POR 0x6D55B000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_VINCM_BBF_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_VOUTCM_BBF_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_TIA_R_NBIAS___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_TIA_R_PBIAS___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_BQ_R_NBIAS___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_BQ_R_PBIAS___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_MIDREF_BQ___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_MIDREF_TIA___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_VINCM_BBF_CTRL___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_VINCM_BBF_CTRL___S 29 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_VOUTCM_BBF_CTRL___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_VOUTCM_BBF_CTRL___S 26 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_TIA_R_NBIAS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_TIA_R_NBIAS___S 24 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_TIA_R_PBIAS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_TIA_R_PBIAS___S 22 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_BQ_R_NBIAS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_BQ_R_NBIAS___S 20 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_BQ_R_PBIAS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_BQ_R_PBIAS___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_MIDREF_BQ___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_MIDREF_BQ___S 15 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_MIDREF_TIA___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0__D_MIDREF_TIA___S 12 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_BIAS0___S 12 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_RTUNE (0x005E8A34) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_RTUNE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_RTUNE___POR 0xB4000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_RTUNE__D_LVL_RTUNE___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_RTUNE__D_TIA_RTUNE___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_RTUNE__D_LVL_RTUNE___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_RTUNE__D_LVL_RTUNE___S 29 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_RTUNE__D_TIA_RTUNE___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_RTUNE__D_TIA_RTUNE___S 26 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_RTUNE___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_RTUNE___S 26 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATB (0x005E8A38) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATB___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATB__D_TESTBB_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATB__D_TESTBB_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATB__D_BBF_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATB__D_TESTBB_I___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATB__D_TESTBB_I___S 29 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATB__D_TESTBB_Q___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATB__D_TESTBB_Q___S 26 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATB__D_BBF_ATB_SEL___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATB__D_BBF_ATB_SEL___S 23 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATB___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_ATB___S 23 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_SPARE0 (0x005E8A3C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_SPARE0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_SPARE0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_SPARE0__D_TXBB_SPARE0___POR 0x000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_SPARE0__D_TXBB_SPARE0___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_SPARE0__D_TXBB_SPARE0___S 0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_SPARE0___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_SPARE0___S 0 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_SPARE1 (0x005E8A40) +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_SPARE1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_SPARE1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_SPARE1__D_TXBB_SPARE1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_SPARE1__D_TXBB_SPARE1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_SPARE1__D_TXBB_SPARE1___S 0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_SPARE1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXBB_CH0_SPARE1___S 0 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_TESTREG (0x005E9000) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_TESTREG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_TESTREG___POR 0x44FE5111 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_TESTREG__TESTREG___POR 0x44FE5111 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_TESTREG__TESTREG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_TESTREG__TESTREG___S 0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_TESTREG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_TESTREG___S 0 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL (0x005E9004) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL__FCS_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OV___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OVD___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OVD___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OV___S 27 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OVD___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OVD___S 24 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL__FCS_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL__FCS_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LUT_IDX_SEL___S 22 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_0 (0x005E9008) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_0___POR 0x8C000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_0__LNA_LOAD_C_0___POR 0x8 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_0__LNA_INP_NOTCH_CTUNE_0___POR 0xC +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_0__LNA_INP_NOTCH_CTUNE_SW_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_0__LNA_INP_SRC_IND_SW_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_0__LNA_LOAD_C_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_0__LNA_LOAD_C_0___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_0__LNA_INP_NOTCH_CTUNE_0___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_0__LNA_INP_NOTCH_CTUNE_0___S 24 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_0__LNA_INP_NOTCH_CTUNE_SW_0___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_0__LNA_INP_NOTCH_CTUNE_SW_0___S 20 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_0__LNA_INP_SRC_IND_SW_0___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_0__LNA_INP_SRC_IND_SW_0___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_0___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_0___S 19 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_1 (0x005E900C) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_1___POR 0x30C00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_1__LNA_LOAD_C_1___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_1__LNA_INP_NOTCH_CTUNE_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_1__LNA_INP_NOTCH_CTUNE_SW_1___POR 0xC +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_1__LNA_INP_SRC_IND_SW_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_1__LNA_LOAD_C_1___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_1__LNA_LOAD_C_1___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_1__LNA_INP_NOTCH_CTUNE_1___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_1__LNA_INP_NOTCH_CTUNE_1___S 24 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_1__LNA_INP_NOTCH_CTUNE_SW_1___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_1__LNA_INP_NOTCH_CTUNE_SW_1___S 20 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_1__LNA_INP_SRC_IND_SW_1___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_1__LNA_INP_SRC_IND_SW_1___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_1___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_1_1___S 19 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0 (0x005E9010) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0___POR 0x62409760 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_RMATCH_0___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_GAIN_CTRL_0___POR 0x12 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_LOAD_R_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_OTA_EN_0___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_BIAS_0___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_AUX_CAP_0___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_MAIN_EN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_AUX_EN_0___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__NA_BIAS_OTA_BYPASS_0___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_RMATCH_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_RMATCH_0___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_GAIN_CTRL_0___M 0x1FE00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_GAIN_CTRL_0___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_LOAD_R_0___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_LOAD_R_0___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_OTA_EN_0___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_OTA_EN_0___S 15 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_BIAS_0___M 0x00007800 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_BIAS_0___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_AUX_CAP_0___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_AUX_CAP_0___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_MAIN_EN_0___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_MAIN_EN_0___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_AUX_EN_0___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__LNA_AUX_EN_0___S 6 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__NA_BIAS_OTA_BYPASS_0___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0__NA_BIAS_OTA_BYPASS_0___S 5 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0___M 0xFFFFFFE0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_0___S 5 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1 (0x005E9014) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1___POR 0x63009D60 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_RMATCH_1___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_GAIN_CTRL_1___POR 0x18 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_LOAD_R_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_OTA_EN_1___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_BIAS_1___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_AUX_CAP_1___POR 0x5 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_MAIN_EN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_AUX_EN_1___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__NA_BIAS_OTA_BYPASS_1___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_RMATCH_1___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_RMATCH_1___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_GAIN_CTRL_1___M 0x1FE00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_GAIN_CTRL_1___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_LOAD_R_1___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_LOAD_R_1___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_OTA_EN_1___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_OTA_EN_1___S 15 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_BIAS_1___M 0x00007800 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_BIAS_1___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_AUX_CAP_1___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_AUX_CAP_1___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_MAIN_EN_1___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_MAIN_EN_1___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_AUX_EN_1___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__LNA_AUX_EN_1___S 6 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__NA_BIAS_OTA_BYPASS_1___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1__NA_BIAS_OTA_BYPASS_1___S 5 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1___M 0xFFFFFFE0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_1___S 5 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2 (0x005E9018) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2___POR 0x6360A360 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_RMATCH_2___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_GAIN_CTRL_2___POR 0x1B +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_LOAD_R_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_OTA_EN_2___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_BIAS_2___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_AUX_CAP_2___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_MAIN_EN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_AUX_EN_2___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__NA_BIAS_OTA_BYPASS_2___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_RMATCH_2___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_RMATCH_2___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_GAIN_CTRL_2___M 0x1FE00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_GAIN_CTRL_2___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_LOAD_R_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_LOAD_R_2___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_OTA_EN_2___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_OTA_EN_2___S 15 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_BIAS_2___M 0x00007800 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_BIAS_2___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_AUX_CAP_2___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_AUX_CAP_2___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_MAIN_EN_2___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_MAIN_EN_2___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_AUX_EN_2___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__LNA_AUX_EN_2___S 6 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__NA_BIAS_OTA_BYPASS_2___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2__NA_BIAS_OTA_BYPASS_2___S 5 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2___M 0xFFFFFFE0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_2___S 5 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3 (0x005E901C) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3___POR 0x6380A860 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_RMATCH_3___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_GAIN_CTRL_3___POR 0x1C +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_LOAD_R_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_OTA_EN_3___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_BIAS_3___POR 0x5 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_AUX_CAP_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_MAIN_EN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_AUX_EN_3___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__NA_BIAS_OTA_BYPASS_3___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_RMATCH_3___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_RMATCH_3___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_GAIN_CTRL_3___M 0x1FE00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_GAIN_CTRL_3___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_LOAD_R_3___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_LOAD_R_3___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_OTA_EN_3___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_OTA_EN_3___S 15 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_BIAS_3___M 0x00007800 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_BIAS_3___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_AUX_CAP_3___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_AUX_CAP_3___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_MAIN_EN_3___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_MAIN_EN_3___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_AUX_EN_3___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__LNA_AUX_EN_3___S 6 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__NA_BIAS_OTA_BYPASS_3___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3__NA_BIAS_OTA_BYPASS_3___S 5 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3___M 0xFFFFFFE0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_3___S 5 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4 (0x005E9020) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4___POR 0x628E9080 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_RMATCH_4___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_GAIN_CTRL_4___POR 0x14 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_LOAD_R_4___POR 0x0E +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_OTA_EN_4___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_BIAS_4___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_AUX_CAP_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_MAIN_EN_4___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_AUX_EN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__NA_BIAS_OTA_BYPASS_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_RMATCH_4___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_RMATCH_4___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_GAIN_CTRL_4___M 0x1FE00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_GAIN_CTRL_4___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_LOAD_R_4___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_LOAD_R_4___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_OTA_EN_4___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_OTA_EN_4___S 15 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_BIAS_4___M 0x00007800 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_BIAS_4___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_AUX_CAP_4___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_AUX_CAP_4___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_MAIN_EN_4___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_MAIN_EN_4___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_AUX_EN_4___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__LNA_AUX_EN_4___S 6 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__NA_BIAS_OTA_BYPASS_4___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4__NA_BIAS_OTA_BYPASS_4___S 5 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4___M 0xFFFFFFE0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_4___S 5 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5 (0x005E9024) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5___POR 0x62809080 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_RMATCH_5___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_GAIN_CTRL_5___POR 0x14 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_LOAD_R_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_OTA_EN_5___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_BIAS_5___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_AUX_CAP_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_MAIN_EN_5___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_AUX_EN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__NA_BIAS_OTA_BYPASS_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_RMATCH_5___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_RMATCH_5___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_GAIN_CTRL_5___M 0x1FE00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_GAIN_CTRL_5___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_LOAD_R_5___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_LOAD_R_5___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_OTA_EN_5___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_OTA_EN_5___S 15 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_BIAS_5___M 0x00007800 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_BIAS_5___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_AUX_CAP_5___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_AUX_CAP_5___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_MAIN_EN_5___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_MAIN_EN_5___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_AUX_EN_5___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__LNA_AUX_EN_5___S 6 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__NA_BIAS_OTA_BYPASS_5___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5__NA_BIAS_OTA_BYPASS_5___S 5 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5___M 0xFFFFFFE0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_5___S 5 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6 (0x005E9028) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6___POR 0x03E29880 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_RMATCH_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_GAIN_CTRL_6___POR 0x1F +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_LOAD_R_6___POR 0x02 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_OTA_EN_6___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_BIAS_6___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_AUX_CAP_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_MAIN_EN_6___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_AUX_EN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__NA_BIAS_OTA_BYPASS_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_RMATCH_6___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_RMATCH_6___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_GAIN_CTRL_6___M 0x1FE00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_GAIN_CTRL_6___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_LOAD_R_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_LOAD_R_6___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_OTA_EN_6___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_OTA_EN_6___S 15 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_BIAS_6___M 0x00007800 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_BIAS_6___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_AUX_CAP_6___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_AUX_CAP_6___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_MAIN_EN_6___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_MAIN_EN_6___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_AUX_EN_6___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__LNA_AUX_EN_6___S 6 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__NA_BIAS_OTA_BYPASS_6___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6__NA_BIAS_OTA_BYPASS_6___S 5 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6___M 0xFFFFFFE0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_6___S 5 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7 (0x005E902C) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7___POR 0x06209080 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_RMATCH_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_GAIN_CTRL_7___POR 0x31 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_LOAD_R_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_OTA_EN_7___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_BIAS_7___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_AUX_CAP_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_MAIN_EN_7___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_AUX_EN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__NA_BIAS_OTA_BYPASS_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_RMATCH_7___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_RMATCH_7___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_GAIN_CTRL_7___M 0x1FE00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_GAIN_CTRL_7___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_LOAD_R_7___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_LOAD_R_7___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_OTA_EN_7___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_OTA_EN_7___S 15 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_BIAS_7___M 0x00007800 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_BIAS_7___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_AUX_CAP_7___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_AUX_CAP_7___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_MAIN_EN_7___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_MAIN_EN_7___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_AUX_EN_7___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__LNA_AUX_EN_7___S 6 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__NA_BIAS_OTA_BYPASS_7___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7__NA_BIAS_OTA_BYPASS_7___S 5 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7___M 0xFFFFFFE0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_LNA_0_7___S 5 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_0 (0x005E9030) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_0___POR 0x0A320000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_0__GM_GAIN_BYP_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_0__GM_GAIN_NCTRL_0___POR 0x05 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_0__GM_GAIN_PCTRL_0___POR 0x06 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_0__GM_BIAS_0___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_0__GM_GAIN_BYP_0___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_0__GM_GAIN_BYP_0___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_0__GM_GAIN_NCTRL_0___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_0__GM_GAIN_NCTRL_0___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_0__GM_GAIN_PCTRL_0___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_0__GM_GAIN_PCTRL_0___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_0__GM_BIAS_0___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_0__GM_BIAS_0___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_0___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_0___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_1 (0x005E9034) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_1___POR 0x0A320000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_1__GM_GAIN_BYP_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_1__GM_GAIN_NCTRL_1___POR 0x05 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_1__GM_GAIN_PCTRL_1___POR 0x06 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_1__GM_BIAS_1___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_1__GM_GAIN_BYP_1___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_1__GM_GAIN_BYP_1___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_1__GM_GAIN_NCTRL_1___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_1__GM_GAIN_NCTRL_1___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_1__GM_GAIN_PCTRL_1___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_1__GM_GAIN_PCTRL_1___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_1__GM_BIAS_1___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_1__GM_BIAS_1___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_1___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_1___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_2 (0x005E9038) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_2___POR 0x14520000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_2__GM_GAIN_BYP_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_2__GM_GAIN_NCTRL_2___POR 0x0A +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_2__GM_GAIN_PCTRL_2___POR 0x0A +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_2__GM_BIAS_2___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_2__GM_GAIN_BYP_2___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_2__GM_GAIN_BYP_2___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_2__GM_GAIN_NCTRL_2___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_2__GM_GAIN_NCTRL_2___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_2__GM_GAIN_PCTRL_2___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_2__GM_GAIN_PCTRL_2___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_2__GM_BIAS_2___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_2__GM_BIAS_2___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_2___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_2___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_3 (0x005E903C) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_3___POR 0x1E7A0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_3__GM_GAIN_BYP_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_3__GM_GAIN_NCTRL_3___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_3__GM_GAIN_PCTRL_3___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_3__GM_BIAS_3___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_3__GM_GAIN_BYP_3___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_3__GM_GAIN_BYP_3___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_3__GM_GAIN_NCTRL_3___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_3__GM_GAIN_NCTRL_3___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_3__GM_GAIN_PCTRL_3___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_3__GM_GAIN_PCTRL_3___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_3__GM_BIAS_3___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_3__GM_BIAS_3___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_3___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_3___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_4 (0x005E9040) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_4___POR 0x28930000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_4__GM_GAIN_BYP_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_4__GM_GAIN_NCTRL_4___POR 0x14 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_4__GM_GAIN_PCTRL_4___POR 0x12 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_4__GM_BIAS_4___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_4__GM_GAIN_BYP_4___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_4__GM_GAIN_BYP_4___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_4__GM_GAIN_NCTRL_4___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_4__GM_GAIN_NCTRL_4___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_4__GM_GAIN_PCTRL_4___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_4__GM_GAIN_PCTRL_4___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_4__GM_BIAS_4___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_4__GM_BIAS_4___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_4___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_4___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_5 (0x005E9044) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_5___POR 0x3CC20000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_5__GM_GAIN_BYP_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_5__GM_GAIN_NCTRL_5___POR 0x1E +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_5__GM_GAIN_PCTRL_5___POR 0x18 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_5__GM_BIAS_5___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_5__GM_GAIN_BYP_5___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_5__GM_GAIN_BYP_5___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_5__GM_GAIN_NCTRL_5___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_5__GM_GAIN_NCTRL_5___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_5__GM_GAIN_PCTRL_5___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_5__GM_GAIN_PCTRL_5___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_5__GM_BIAS_5___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_5__GM_BIAS_5___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_5___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_5___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_6 (0x005E9048) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_6___POR 0x65A90000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_6__GM_GAIN_BYP_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_6__GM_GAIN_NCTRL_6___POR 0x32 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_6__GM_GAIN_PCTRL_6___POR 0x35 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_6__GM_BIAS_6___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_6__GM_GAIN_BYP_6___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_6__GM_GAIN_BYP_6___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_6__GM_GAIN_NCTRL_6___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_6__GM_GAIN_NCTRL_6___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_6__GM_GAIN_PCTRL_6___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_6__GM_GAIN_PCTRL_6___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_6__GM_BIAS_6___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_6__GM_BIAS_6___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_6___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_6___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_7 (0x005E904C) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_7___POR 0x65A90000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_7__GM_GAIN_BYP_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_7__GM_GAIN_NCTRL_7___POR 0x32 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_7__GM_GAIN_PCTRL_7___POR 0x35 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_7__GM_BIAS_7___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_7__GM_GAIN_BYP_7___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_7__GM_GAIN_BYP_7___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_7__GM_GAIN_NCTRL_7___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_7__GM_GAIN_NCTRL_7___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_7__GM_GAIN_PCTRL_7___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_7__GM_GAIN_PCTRL_7___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_7__GM_BIAS_7___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_7__GM_BIAS_7___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_7___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_GM_0_7___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0 (0x005E9080) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_RMATCH_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_RMATCH_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_GAIN_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_GAIN_CTRL_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_LOAD_R_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_LOAD_R_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_OTA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_BIAS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_BIAS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_AUX_CAP_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_AUX_CAP_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_RMATCH_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_RMATCH_OV___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_RMATCH_OVD___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_RMATCH_OVD___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_GAIN_CTRL_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_GAIN_CTRL_OV___S 27 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_GAIN_CTRL_OVD___M 0x07F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_GAIN_CTRL_OVD___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_LOAD_R_OV___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_LOAD_R_OV___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_LOAD_R_OVD___M 0x0003E000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_LOAD_R_OVD___S 13 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_OTA_EN_OVS___M 0x00001800 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_OTA_EN_OVS___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_BIAS_OV___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_BIAS_OV___S 10 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_BIAS_OVD___M 0x000003C0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_BIAS_OVD___S 6 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_AUX_CAP_OV___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_AUX_CAP_OV___S 5 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_AUX_CAP_OVD___M 0x0000001C +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0__LNA_AUX_CAP_OVD___S 2 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0___S 2 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0_EXT (0x005E9084) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0_EXT___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0_EXT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0_EXT__LNA_MAIN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0_EXT__LNA_AUX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0_EXT__LNA_BIAS_OTA_BYPASS_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0_EXT__LNA_MAIN_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0_EXT__LNA_MAIN_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0_EXT__LNA_AUX_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0_EXT__LNA_AUX_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0_EXT__LNA_BIAS_OTA_BYPASS_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0_EXT__LNA_BIAS_OTA_BYPASS_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0_EXT___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV0_EXT___S 26 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1 (0x005E9088) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_GAIN_BYP_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_GAIN_NCTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_GAIN_NCTRL_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_GAIN_PCTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_GAIN_PCTRL_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_BIAS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_BIAS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_GAIN_BYP_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_GAIN_BYP_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_GAIN_NCTRL_OV___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_GAIN_NCTRL_OV___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_GAIN_NCTRL_OVD___M 0x1F800000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_GAIN_NCTRL_OVD___S 23 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_GAIN_PCTRL_OV___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_GAIN_PCTRL_OV___S 22 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_GAIN_PCTRL_OVD___M 0x003F0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_GAIN_PCTRL_OVD___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_BIAS_OV___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_BIAS_OV___S 15 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_BIAS_OVD___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1__GM_BIAS_OVD___S 12 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV1___S 12 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2 (0x005E908C) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_LOAD_C_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_LOAD_C_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_INP_NOTCH_CTUNE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_INP_NOTCH_CTUNE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_INP_NOTCH_CTUNE_SW_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_INP_NOTCH_CTUNE_SW_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_INP_SRC_IND_SW_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_LOAD_C_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_LOAD_C_OV___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_LOAD_C_OVD___M 0x78000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_LOAD_C_OVD___S 27 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_INP_NOTCH_CTUNE_OV___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_INP_NOTCH_CTUNE_OV___S 26 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_INP_NOTCH_CTUNE_OVD___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_INP_NOTCH_CTUNE_OVD___S 22 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_INP_NOTCH_CTUNE_SW_OV___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_INP_NOTCH_CTUNE_SW_OV___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_INP_NOTCH_CTUNE_SW_OVD___M 0x001E0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_INP_NOTCH_CTUNE_SW_OVD___S 17 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_INP_SRC_IND_SW_OVS___M 0x00018000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2__LNA_INP_SRC_IND_SW_OVS___S 15 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2___M 0xFFFF8000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_LUT_OV2___S 15 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0 (0x005E9090) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__GM_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__LNA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__LNA_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__MIX_EN_I_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__MIX_EN_Q_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__CALRTX_SW_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__DPD_XPA_SW_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__DPD_IPA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_OBUF25DC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_LP_OBUF25DC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_INBUF25DC1ST_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_LP_INBUF25DC1ST_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_INBUF25DC2ND_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_LP_INBUF25DC2ND_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__MIXLP_EN_I_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__MIXLP_EN_Q_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__GM_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__GM_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__LNA_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__LNA_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__LNA_FC_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__LNA_FC_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__MIX_EN_I_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__MIX_EN_I_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__MIX_EN_Q_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__MIX_EN_Q_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__CALRTX_SW_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__CALRTX_SW_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__DPD_XPA_SW_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__DPD_XPA_SW_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__DPD_IPA_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__DPD_IPA_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_OBUF25DC_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_OBUF25DC_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_LP_OBUF25DC_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_LP_OBUF25DC_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_INBUF25DC1ST_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_INBUF25DC1ST_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_LP_INBUF25DC1ST_EN_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_LP_INBUF25DC1ST_EN_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_INBUF25DC2ND_EN_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_INBUF25DC2ND_EN_OVS___S 6 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_LP_INBUF25DC2ND_EN_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__RXLO_LP_INBUF25DC2ND_EN_OVS___S 4 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__MIXLP_EN_I_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__MIXLP_EN_I_OVS___S 2 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__MIXLP_EN_Q_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0__MIXLP_EN_Q_OVS___S 0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV0___S 0 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV1 (0x005E9094) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV1__AGC_PKDET_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV1__AGC_PKDET_COMP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV1__AGC_PKDET_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV1__AGC_PKDET_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV1__AGC_PKDET_COMP_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV1__AGC_PKDET_COMP_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OV___S 27 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OVD___M 0x07F00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OVD___S 20 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV1___M 0xFFF00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_OV1___S 20 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_RXFE_LUT_IDX_SEL (0x005E9098) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_RXFE_LUT_IDX_SEL___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_RXFE_LUT_IDX_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_RXFE_LUT_IDX_SEL__RO_FCS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN___S 26 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_RXFE_LUT_IDX_SEL__RO_FCS___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_RXFE_LUT_IDX_SEL__RO_FCS___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_RXFE_LUT_IDX_SEL___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_RXFE_LUT_IDX_SEL___S 25 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0 (0x005E909C) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_RMATCH___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_GAIN_CTRL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_LOAD_R___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_OTA_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_BIAS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_AUX_CAP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_MAIN_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_AUX_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_BIAS_OTA_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_RMATCH___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_RMATCH___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_GAIN_CTRL___M 0x1FE00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_GAIN_CTRL___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_LOAD_R___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_LOAD_R___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_OTA_EN___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_OTA_EN___S 15 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_BIAS___M 0x00007800 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_BIAS___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_AUX_CAP___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_AUX_CAP___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_MAIN_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_MAIN_EN___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_AUX_EN___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_AUX_EN___S 6 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_BIAS_OTA_BYPASS___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0__RO_LNA_BIAS_OTA_BYPASS___S 5 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0___M 0xFFFFFFE0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT0___S 5 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT1 (0x005E90A0) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT1__RO_GM_GAIN_BYP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT1__RO_GM_GAIN_NCTRL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT1__RO_GM_GAIN_PCTRL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT1__RO_GM_BIAS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT1__RO_GM_GAIN_BYP___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT1__RO_GM_GAIN_BYP___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT1__RO_GM_GAIN_NCTRL___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT1__RO_GM_GAIN_NCTRL___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT1__RO_GM_GAIN_PCTRL___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT1__RO_GM_GAIN_PCTRL___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT1__RO_GM_BIAS___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT1__RO_GM_BIAS___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT1___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT1___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT2 (0x005E90A4) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT2__RO_LNA_LOAD_C___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT2__RO_LNA_INP_NOTCH_CTUNE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT2__RO_LNA_INP_NOTCH_CTUNE_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT2__RO_LNA_INP_SRC_IND_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT2__RO_LNA_LOAD_C___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT2__RO_LNA_LOAD_C___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT2__RO_LNA_INP_NOTCH_CTUNE___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT2__RO_LNA_INP_NOTCH_CTUNE___S 24 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT2__RO_LNA_INP_NOTCH_CTUNE_SW___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT2__RO_LNA_INP_NOTCH_CTUNE_SW___S 20 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT2__RO_LNA_INP_SRC_IND_SW___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT2__RO_LNA_INP_SRC_IND_SW___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT2___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_WL_RXFE_LUT2___S 19 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0 (0x005E90A8) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0___POR 0x20280E00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__D_AGC_PKDET_BW___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__D_AGC_PKDET_THRES___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__D_AGC_PKDET_DCOC_RANGE___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__D_AGC_PKDET_GAIN___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__D_AGC_PKDET_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__AGC_PKDET_DCOC_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__AGC_PKDET_DCOC_SETT___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__D_AGC_PKDET_BW___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__D_AGC_PKDET_BW___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__D_AGC_PKDET_THRES___M 0x1FC00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__D_AGC_PKDET_THRES___S 22 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__D_AGC_PKDET_DCOC_RANGE___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__D_AGC_PKDET_DCOC_RANGE___S 20 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__D_AGC_PKDET_GAIN___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__D_AGC_PKDET_GAIN___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__D_AGC_PKDET_ATB_SEL___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__D_AGC_PKDET_ATB_SEL___S 17 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__AGC_PKDET_DCOC_EN___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__AGC_PKDET_DCOC_EN___S 12 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__AGC_PKDET_DCOC_SETT___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0__AGC_PKDET_DCOC_SETT___S 9 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0___M 0xFFFE1E00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_AGC_CAL_0___S 9 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_AGC_CAL (0x005E90AC) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_AGC_CAL___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_AGC_CAL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_VALID___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_SAT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES_EFFECT___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_VALID___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_VALID___S 15 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_SAT___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_SAT___S 14 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES_EFFECT___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES_EFFECT___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES___S 0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_AGC_CAL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_RO_AGC_CAL___S 0 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0 (0x005E90B0) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0___POR 0x520103C0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_CM_BIAS___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_IC_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_IRTT_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_VCM___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_RDGEN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_IC_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_IRTT_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_BIAS_SHORTR_OTA___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_CM_BIAS___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_CASOFF_MAIN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_CASOFF_AUX___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_CM_BIAS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_CM_BIAS___S 30 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_IC_EN___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_IC_EN___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_IRTT_EN___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_IRTT_EN___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_VCM___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_VCM___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_RDGEN___M 0x01E00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_RDGEN___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_ATB_SEL___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_GM_ATB_SEL___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_IC_EN___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_IC_EN___S 17 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_IRTT_EN___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_IRTT_EN___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_BIAS_SHORTR_OTA___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_BIAS_SHORTR_OTA___S 15 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_ATB_SEL___M 0x00003C00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_ATB_SEL___S 10 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_CM_BIAS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_CM_BIAS___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_CASOFF_MAIN___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_CASOFF_MAIN___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_CASOFF_AUX___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0__D_LNA_CASOFF_AUX___S 6 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0___M 0xFFFFBFC0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_CONTROL0___S 6 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1 (0x005E90B4) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1___POR 0x00FF00FF +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_ATB_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_LSB_I___POR 0xF +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_LSB_Q___POR 0xF +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_MSB_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_MSB_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_LPDUTYCODE_LSB_I___POR 0xF +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_LPDUTYCODE_LSB_Q___POR 0xF +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_ATB_SEL___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_ATB_SEL___S 24 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_LSB_I___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_LSB_I___S 20 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_LSB_Q___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_LSB_Q___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_MSB_I___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_MSB_I___S 12 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_MSB_Q___M 0x00000F00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_MSB_Q___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_LPDUTYCODE_LSB_I___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_LPDUTYCODE_LSB_I___S 4 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_LPDUTYCODE_LSB_Q___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1__D_RXLO_LPDUTYCODE_LSB_Q___S 0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL1___S 0 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2 (0x005E90B8) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2___POR 0x00968000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_RXLO_LPDUTYCODE_MSB_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_RXLO_LPDUTYCODE_MSB_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_BIAS_IC_CTRL___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_BIAS_IRTT_OFFSET___POR 0x5 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_BIAS_IP_CTRL___POR 0x5 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_AGC_PKDET_OUT_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_AGC_PKDET_VREFRNG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_RXLO_LPDUTYCODE_MSB_I___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_RXLO_LPDUTYCODE_MSB_I___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_RXLO_LPDUTYCODE_MSB_Q___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_RXLO_LPDUTYCODE_MSB_Q___S 24 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_BIAS_IC_CTRL___M 0x00E00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_BIAS_IC_CTRL___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_BIAS_IRTT_OFFSET___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_BIAS_IRTT_OFFSET___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_BIAS_IP_CTRL___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_BIAS_IP_CTRL___S 15 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_AGC_PKDET_OUT_ATB_SEL___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_AGC_PKDET_OUT_ATB_SEL___S 14 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_AGC_PKDET_VREFRNG___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2__D_AGC_PKDET_VREFRNG___S 12 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_W_RXFE_CONTROL2___S 12 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_SPARE (0x005E90BC) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_SPARE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_SPARE___POR 0x00000200 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_SPARE__D_RXFE_SPARE___POR 0x000002 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_SPARE__D_RXFE_SPARE___M 0xFFFFFF00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_SPARE__D_RXFE_SPARE___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_SPARE___M 0xFFFFFF00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH0_WL_RXFE_SPARE___S 8 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_TESTREG (0x005E9300) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_TESTREG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_TESTREG___POR 0x33FE5111 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_TESTREG__TESTREG___POR 0x33FE5111 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_TESTREG__TESTREG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_TESTREG__TESTREG___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_TESTREG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_TESTREG___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL (0x005E9304) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__FCS_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OV___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__FCS_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__FCS_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LUT_IDX_SEL___S 16 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_0 (0x005E9308) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_0___POR 0x04101800 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE3FLO_0___POR 0x01 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE1FLO_0___POR 0x01 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_0__DA_CTUNE_0___POR 0x01 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_0__UPC_LSW_EN_0___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE3FLO_0___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE3FLO_0___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE1FLO_0___M 0x03F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE1FLO_0___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_0__DA_CTUNE_0___M 0x0001F000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_0__DA_CTUNE_0___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_0__UPC_LSW_EN_0___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_0__UPC_LSW_EN_0___S 11 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_0___M 0xFFF1F800 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_0___S 11 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_1 (0x005E930C) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_1___POR 0x04101800 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE3FLO_1___POR 0x01 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE1FLO_1___POR 0x01 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_1__DA_CTUNE_1___POR 0x01 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_1__UPC_LSW_EN_1___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE3FLO_1___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE3FLO_1___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE1FLO_1___M 0x03F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE1FLO_1___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_1__DA_CTUNE_1___M 0x0001F000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_1__DA_CTUNE_1___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_1__UPC_LSW_EN_1___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_1__UPC_LSW_EN_1___S 11 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_1___M 0xFFF1F800 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CTUNE_LUT_1___S 11 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_0 (0x005E9310) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_0__DA_CELL_EN_0___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_0__DA_CELL_AUX_EN_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_0__DA_CASOFF_BIAS_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_0__DA_CELL_EN_0___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_0__DA_CELL_EN_0___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_0__DA_CELL_AUX_EN_0___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_0__DA_CELL_AUX_EN_0___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_0__DA_CASOFF_BIAS_0___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_0__DA_CASOFF_BIAS_0___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_0___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_0___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_1 (0x005E9314) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_1__DA_CELL_EN_1___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_1__DA_CELL_AUX_EN_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_1__DA_CASOFF_BIAS_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_1__DA_CELL_EN_1___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_1__DA_CELL_EN_1___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_1__DA_CELL_AUX_EN_1___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_1__DA_CELL_AUX_EN_1___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_1__DA_CASOFF_BIAS_1___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_1__DA_CASOFF_BIAS_1___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_1___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_1___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_2 (0x005E9318) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_2__DA_CELL_EN_2___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_2__DA_CELL_AUX_EN_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_2__DA_CASOFF_BIAS_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_2__DA_CELL_EN_2___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_2__DA_CELL_EN_2___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_2__DA_CELL_AUX_EN_2___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_2__DA_CELL_AUX_EN_2___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_2__DA_CASOFF_BIAS_2___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_2__DA_CASOFF_BIAS_2___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_2___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_2___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_3 (0x005E931C) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_3__DA_CELL_EN_3___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_3__DA_CELL_AUX_EN_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_3__DA_CASOFF_BIAS_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_3__DA_CELL_EN_3___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_3__DA_CELL_EN_3___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_3__DA_CELL_AUX_EN_3___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_3__DA_CELL_AUX_EN_3___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_3__DA_CASOFF_BIAS_3___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_3__DA_CASOFF_BIAS_3___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_3___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_3___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_4 (0x005E9320) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_4__DA_CELL_EN_4___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_4__DA_CELL_AUX_EN_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_4__DA_CASOFF_BIAS_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_4__DA_CELL_EN_4___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_4__DA_CELL_EN_4___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_4__DA_CELL_AUX_EN_4___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_4__DA_CELL_AUX_EN_4___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_4__DA_CASOFF_BIAS_4___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_4__DA_CASOFF_BIAS_4___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_4___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_4___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_5 (0x005E9324) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_5__DA_CELL_EN_5___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_5__DA_CELL_AUX_EN_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_5__DA_CASOFF_BIAS_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_5__DA_CELL_EN_5___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_5__DA_CELL_EN_5___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_5__DA_CELL_AUX_EN_5___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_5__DA_CELL_AUX_EN_5___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_5__DA_CASOFF_BIAS_5___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_5__DA_CASOFF_BIAS_5___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_5___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_5___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_6 (0x005E9328) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_6__DA_CELL_EN_6___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_6__DA_CELL_AUX_EN_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_6__DA_CASOFF_BIAS_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_6__DA_CELL_EN_6___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_6__DA_CELL_EN_6___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_6__DA_CELL_AUX_EN_6___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_6__DA_CELL_AUX_EN_6___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_6__DA_CASOFF_BIAS_6___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_6__DA_CASOFF_BIAS_6___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_6___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_6___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_7 (0x005E932C) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_7__DA_CELL_EN_7___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_7__DA_CELL_AUX_EN_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_7__DA_CASOFF_BIAS_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_7__DA_CELL_EN_7___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_7__DA_CELL_EN_7___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_7__DA_CELL_AUX_EN_7___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_7__DA_CELL_AUX_EN_7___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_7__DA_CASOFF_BIAS_7___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_7__DA_CASOFF_BIAS_7___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_7___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_7___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_8 (0x005E9330) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_8__DA_CELL_EN_8___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_8__DA_CELL_AUX_EN_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_8__DA_CASOFF_BIAS_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_8__DA_CELL_EN_8___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_8__DA_CELL_EN_8___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_8__DA_CELL_AUX_EN_8___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_8__DA_CELL_AUX_EN_8___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_8__DA_CASOFF_BIAS_8___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_8__DA_CASOFF_BIAS_8___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_8___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_8___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_9 (0x005E9334) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_9___POR 0x06009000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_9__DA_CELL_EN_9___POR 0x00C +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_9__DA_CELL_AUX_EN_9___POR 0x01 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_9__DA_CASOFF_BIAS_9___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_9__DA_CELL_EN_9___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_9__DA_CELL_EN_9___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_9__DA_CELL_AUX_EN_9___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_9__DA_CELL_AUX_EN_9___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_9__DA_CASOFF_BIAS_9___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_9__DA_CASOFF_BIAS_9___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_9___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_9___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_10 (0x005E9338) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_10___POR 0x07009000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_10__DA_CELL_EN_10___POR 0x00E +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_10__DA_CELL_AUX_EN_10___POR 0x01 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_10__DA_CASOFF_BIAS_10___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_10__DA_CELL_EN_10___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_10__DA_CELL_EN_10___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_10__DA_CELL_AUX_EN_10___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_10__DA_CELL_AUX_EN_10___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_10__DA_CASOFF_BIAS_10___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_10__DA_CASOFF_BIAS_10___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_10___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_10___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_11 (0x005E933C) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_11___POR 0x07819000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_11__DA_CELL_EN_11___POR 0x00F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_11__DA_CELL_AUX_EN_11___POR 0x03 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_11__DA_CASOFF_BIAS_11___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_11__DA_CELL_EN_11___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_11__DA_CELL_EN_11___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_11__DA_CELL_AUX_EN_11___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_11__DA_CELL_AUX_EN_11___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_11__DA_CASOFF_BIAS_11___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_11__DA_CASOFF_BIAS_11___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_11___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_11___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_12 (0x005E9340) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_12___POR 0x0A821000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_12__DA_CELL_EN_12___POR 0x015 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_12__DA_CELL_AUX_EN_12___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_12__DA_CASOFF_BIAS_12___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_12__DA_CELL_EN_12___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_12__DA_CELL_EN_12___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_12__DA_CELL_AUX_EN_12___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_12__DA_CELL_AUX_EN_12___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_12__DA_CASOFF_BIAS_12___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_12__DA_CASOFF_BIAS_12___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_12___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_12___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_13 (0x005E9344) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_13___POR 0x0B821000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_13__DA_CELL_EN_13___POR 0x017 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_13__DA_CELL_AUX_EN_13___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_13__DA_CASOFF_BIAS_13___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_13__DA_CELL_EN_13___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_13__DA_CELL_EN_13___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_13__DA_CELL_AUX_EN_13___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_13__DA_CELL_AUX_EN_13___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_13__DA_CASOFF_BIAS_13___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_13__DA_CASOFF_BIAS_13___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_13___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_13___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_14 (0x005E9348) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_14___POR 0x10821000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_14__DA_CELL_EN_14___POR 0x021 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_14__DA_CELL_AUX_EN_14___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_14__DA_CASOFF_BIAS_14___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_14__DA_CELL_EN_14___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_14__DA_CELL_EN_14___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_14__DA_CELL_AUX_EN_14___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_14__DA_CELL_AUX_EN_14___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_14__DA_CASOFF_BIAS_14___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_14__DA_CASOFF_BIAS_14___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_14___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_14___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_15 (0x005E934C) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_15___POR 0x11829000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_15__DA_CELL_EN_15___POR 0x023 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_15__DA_CELL_AUX_EN_15___POR 0x05 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_15__DA_CASOFF_BIAS_15___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_15__DA_CELL_EN_15___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_15__DA_CELL_EN_15___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_15__DA_CELL_AUX_EN_15___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_15__DA_CELL_AUX_EN_15___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_15__DA_CASOFF_BIAS_15___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_15__DA_CASOFF_BIAS_15___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_15___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_15___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_16 (0x005E9350) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_16___POR 0x13029000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_16__DA_CELL_EN_16___POR 0x026 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_16__DA_CELL_AUX_EN_16___POR 0x05 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_16__DA_CASOFF_BIAS_16___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_16__DA_CELL_EN_16___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_16__DA_CELL_EN_16___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_16__DA_CELL_AUX_EN_16___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_16__DA_CELL_AUX_EN_16___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_16__DA_CASOFF_BIAS_16___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_16__DA_CASOFF_BIAS_16___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_16___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_16___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_17 (0x005E9354) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_17___POR 0x14831000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_17__DA_CELL_EN_17___POR 0x029 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_17__DA_CELL_AUX_EN_17___POR 0x06 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_17__DA_CASOFF_BIAS_17___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_17__DA_CELL_EN_17___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_17__DA_CELL_EN_17___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_17__DA_CELL_AUX_EN_17___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_17__DA_CELL_AUX_EN_17___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_17__DA_CASOFF_BIAS_17___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_17__DA_CASOFF_BIAS_17___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_17___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_17___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_18 (0x005E9358) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_18___POR 0x18831000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_18__DA_CELL_EN_18___POR 0x031 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_18__DA_CELL_AUX_EN_18___POR 0x06 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_18__DA_CASOFF_BIAS_18___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_18__DA_CELL_EN_18___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_18__DA_CELL_EN_18___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_18__DA_CELL_AUX_EN_18___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_18__DA_CELL_AUX_EN_18___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_18__DA_CASOFF_BIAS_18___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_18__DA_CASOFF_BIAS_18___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_18___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_18___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_19 (0x005E935C) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_19___POR 0x1B031000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_19__DA_CELL_EN_19___POR 0x036 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_19__DA_CELL_AUX_EN_19___POR 0x06 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_19__DA_CASOFF_BIAS_19___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_19__DA_CELL_EN_19___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_19__DA_CELL_EN_19___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_19__DA_CELL_AUX_EN_19___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_19__DA_CELL_AUX_EN_19___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_19__DA_CASOFF_BIAS_19___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_19__DA_CASOFF_BIAS_19___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_19___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_19___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_20 (0x005E9360) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_20___POR 0x1D839000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_20__DA_CELL_EN_20___POR 0x03B +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_20__DA_CELL_AUX_EN_20___POR 0x07 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_20__DA_CASOFF_BIAS_20___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_20__DA_CELL_EN_20___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_20__DA_CELL_EN_20___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_20__DA_CELL_AUX_EN_20___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_20__DA_CELL_AUX_EN_20___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_20__DA_CASOFF_BIAS_20___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_20__DA_CASOFF_BIAS_20___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_20___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_20___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_21 (0x005E9364) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_21___POR 0x24841000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_21__DA_CELL_EN_21___POR 0x049 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_21__DA_CELL_AUX_EN_21___POR 0x08 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_21__DA_CASOFF_BIAS_21___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_21__DA_CELL_EN_21___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_21__DA_CELL_EN_21___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_21__DA_CELL_AUX_EN_21___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_21__DA_CELL_AUX_EN_21___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_21__DA_CASOFF_BIAS_21___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_21__DA_CASOFF_BIAS_21___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_21___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_21___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_22 (0x005E9368) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_22___POR 0x29849000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_22__DA_CELL_EN_22___POR 0x053 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_22__DA_CELL_AUX_EN_22___POR 0x09 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_22__DA_CASOFF_BIAS_22___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_22__DA_CELL_EN_22___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_22__DA_CELL_EN_22___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_22__DA_CELL_AUX_EN_22___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_22__DA_CELL_AUX_EN_22___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_22__DA_CASOFF_BIAS_22___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_22__DA_CASOFF_BIAS_22___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_22___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_22___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_23 (0x005E936C) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_23___POR 0x30861000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_23__DA_CELL_EN_23___POR 0x061 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_23__DA_CELL_AUX_EN_23___POR 0x0C +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_23__DA_CASOFF_BIAS_23___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_23__DA_CELL_EN_23___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_23__DA_CELL_EN_23___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_23__DA_CELL_AUX_EN_23___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_23__DA_CELL_AUX_EN_23___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_23__DA_CASOFF_BIAS_23___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_23__DA_CASOFF_BIAS_23___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_23___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_23___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_24 (0x005E9370) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_24___POR 0x34079000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_24__DA_CELL_EN_24___POR 0x068 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_24__DA_CELL_AUX_EN_24___POR 0x0F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_24__DA_CASOFF_BIAS_24___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_24__DA_CELL_EN_24___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_24__DA_CELL_EN_24___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_24__DA_CELL_AUX_EN_24___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_24__DA_CELL_AUX_EN_24___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_24__DA_CASOFF_BIAS_24___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_24__DA_CASOFF_BIAS_24___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_24___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_24___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_25 (0x005E9374) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_25___POR 0x3A0A1000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_25__DA_CELL_EN_25___POR 0x074 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_25__DA_CELL_AUX_EN_25___POR 0x14 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_25__DA_CASOFF_BIAS_25___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_25__DA_CELL_EN_25___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_25__DA_CELL_EN_25___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_25__DA_CELL_AUX_EN_25___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_25__DA_CELL_AUX_EN_25___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_25__DA_CASOFF_BIAS_25___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_25__DA_CASOFF_BIAS_25___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_25___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_25___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_26 (0x005E9378) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_26___POR 0x3E0C9000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_26__DA_CELL_EN_26___POR 0x07C +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_26__DA_CELL_AUX_EN_26___POR 0x19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_26__DA_CASOFF_BIAS_26___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_26__DA_CELL_EN_26___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_26__DA_CELL_EN_26___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_26__DA_CELL_AUX_EN_26___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_26__DA_CELL_AUX_EN_26___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_26__DA_CASOFF_BIAS_26___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_26__DA_CASOFF_BIAS_26___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_26___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_26___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_27 (0x005E937C) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_27___POR 0x4A0F9000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_27__DA_CELL_EN_27___POR 0x094 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_27__DA_CELL_AUX_EN_27___POR 0x1F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_27__DA_CASOFF_BIAS_27___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_27__DA_CELL_EN_27___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_27__DA_CELL_EN_27___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_27__DA_CELL_AUX_EN_27___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_27__DA_CELL_AUX_EN_27___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_27__DA_CASOFF_BIAS_27___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_27__DA_CASOFF_BIAS_27___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_27___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_27___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_28 (0x005E9380) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_28___POR 0x550F9000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_28__DA_CELL_EN_28___POR 0x0AA +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_28__DA_CELL_AUX_EN_28___POR 0x1F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_28__DA_CASOFF_BIAS_28___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_28__DA_CELL_EN_28___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_28__DA_CELL_EN_28___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_28__DA_CELL_AUX_EN_28___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_28__DA_CELL_AUX_EN_28___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_28__DA_CASOFF_BIAS_28___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_28__DA_CASOFF_BIAS_28___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_28___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_28___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_29 (0x005E9384) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_29___POR 0x5E0F9000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_29__DA_CELL_EN_29___POR 0x0BC +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_29__DA_CELL_AUX_EN_29___POR 0x1F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_29__DA_CASOFF_BIAS_29___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_29__DA_CELL_EN_29___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_29__DA_CELL_EN_29___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_29__DA_CELL_AUX_EN_29___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_29__DA_CELL_AUX_EN_29___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_29__DA_CASOFF_BIAS_29___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_29__DA_CASOFF_BIAS_29___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_29___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_29___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_30 (0x005E9388) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_30___POR 0x6D8F9000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_30__DA_CELL_EN_30___POR 0x0DB +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_30__DA_CELL_AUX_EN_30___POR 0x1F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_30__DA_CASOFF_BIAS_30___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_30__DA_CELL_EN_30___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_30__DA_CELL_EN_30___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_30__DA_CELL_AUX_EN_30___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_30__DA_CELL_AUX_EN_30___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_30__DA_CASOFF_BIAS_30___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_30__DA_CASOFF_BIAS_30___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_30___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_30___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_31 (0x005E938C) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_31___POR 0x7F8F9000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_31__DA_CELL_EN_31___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_31__DA_CELL_AUX_EN_31___POR 0x1F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_31__DA_CASOFF_BIAS_31___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_31__DA_CELL_EN_31___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_31__DA_CELL_EN_31___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_31__DA_CELL_AUX_EN_31___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_31__DA_CELL_AUX_EN_31___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_31__DA_CASOFF_BIAS_31___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_31__DA_CASOFF_BIAS_31___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_31___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA_LUT0_31___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_0 (0x005E9390) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_0__UPC_RGAIN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_0__UPC_RGAIN_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_0__UPC_RGAIN_0___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_0___S 29 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_1 (0x005E9394) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_1__UPC_RGAIN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_1__UPC_RGAIN_1___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_1__UPC_RGAIN_1___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_1___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_1___S 29 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_2 (0x005E9398) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_2__UPC_RGAIN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_2__UPC_RGAIN_2___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_2__UPC_RGAIN_2___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_2___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_2___S 29 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_3 (0x005E939C) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_3__UPC_RGAIN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_3__UPC_RGAIN_3___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_3__UPC_RGAIN_3___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_3___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_3___S 29 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_4 (0x005E93A0) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_4__UPC_RGAIN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_4__UPC_RGAIN_4___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_4__UPC_RGAIN_4___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_4___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_4___S 29 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_5 (0x005E93A4) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_5__UPC_RGAIN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_5__UPC_RGAIN_5___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_5__UPC_RGAIN_5___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_5___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_5___S 29 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_6 (0x005E93A8) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_6__UPC_RGAIN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_6__UPC_RGAIN_6___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_6__UPC_RGAIN_6___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_6___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_6___S 29 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_7 (0x005E93AC) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_7__UPC_RGAIN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_7__UPC_RGAIN_7___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_7__UPC_RGAIN_7___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_7___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC_LUT_7___S 29 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0 (0x005E93B0) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0___POR 0xD02EE80E +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_ILEVEL_0___POR 0x1A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_ILEVEL_B2_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_AUX1_0___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_AUX0_0___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_0___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_CASOFF_BIAS_0___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_CELL_EN_0___POR 0x007 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_VDD_SW_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_ILEVEL_0___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_ILEVEL_0___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_ILEVEL_B2_0___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_ILEVEL_B2_0___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_AUX1_0___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_AUX1_0___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_AUX0_0___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_AUX0_0___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_0___M 0x0000E000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_0___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_CASOFF_BIAS_0___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_CASOFF_BIAS_0___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_CELL_EN_0___M 0x000003FE +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_CELL_EN_0___S 1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_VDD_SW_0___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0__PPA_VDD_SW_0___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_0___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1 (0x005E93B4) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1___POR 0xD02EE80E +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_ILEVEL_1___POR 0x1A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_ILEVEL_B2_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_AUX1_1___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_AUX0_1___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_1___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_CASOFF_BIAS_1___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_CELL_EN_1___POR 0x007 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_VDD_SW_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_ILEVEL_1___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_ILEVEL_1___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_ILEVEL_B2_1___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_ILEVEL_B2_1___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_AUX1_1___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_AUX1_1___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_AUX0_1___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_AUX0_1___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_1___M 0x0000E000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_1___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_CASOFF_BIAS_1___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_CASOFF_BIAS_1___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_CELL_EN_1___M 0x000003FE +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_CELL_EN_1___S 1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_VDD_SW_1___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1__PPA_VDD_SW_1___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_1___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2 (0x005E93B8) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2___POR 0xD02EE81E +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_ILEVEL_2___POR 0x1A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_ILEVEL_B2_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_AUX1_2___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_AUX0_2___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_2___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_CASOFF_BIAS_2___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_CELL_EN_2___POR 0x00F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_VDD_SW_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_ILEVEL_2___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_ILEVEL_2___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_ILEVEL_B2_2___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_ILEVEL_B2_2___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_AUX1_2___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_AUX1_2___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_AUX0_2___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_AUX0_2___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_2___M 0x0000E000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_2___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_CASOFF_BIAS_2___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_CASOFF_BIAS_2___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_CELL_EN_2___M 0x000003FE +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_CELL_EN_2___S 1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_VDD_SW_2___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2__PPA_VDD_SW_2___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_2___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3 (0x005E93BC) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3___POR 0xD02EE81E +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_ILEVEL_3___POR 0x1A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_ILEVEL_B2_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_AUX1_3___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_AUX0_3___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_3___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_CASOFF_BIAS_3___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_CELL_EN_3___POR 0x00F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_VDD_SW_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_ILEVEL_3___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_ILEVEL_3___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_ILEVEL_B2_3___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_ILEVEL_B2_3___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_AUX1_3___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_AUX1_3___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_AUX0_3___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_AUX0_3___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_3___M 0x0000E000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_3___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_CASOFF_BIAS_3___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_CASOFF_BIAS_3___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_CELL_EN_3___M 0x000003FE +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_CELL_EN_3___S 1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_VDD_SW_3___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3__PPA_VDD_SW_3___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_3___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4 (0x005E93C0) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4___POR 0xD02EE87E +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_ILEVEL_4___POR 0x1A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_ILEVEL_B2_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_AUX1_4___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_AUX0_4___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_4___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_CASOFF_BIAS_4___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_CELL_EN_4___POR 0x03F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_VDD_SW_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_ILEVEL_4___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_ILEVEL_4___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_ILEVEL_B2_4___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_ILEVEL_B2_4___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_AUX1_4___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_AUX1_4___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_AUX0_4___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_AUX0_4___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_4___M 0x0000E000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_4___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_CASOFF_BIAS_4___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_CASOFF_BIAS_4___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_CELL_EN_4___M 0x000003FE +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_CELL_EN_4___S 1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_VDD_SW_4___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4__PPA_VDD_SW_4___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_4___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5 (0x005E93C4) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5___POR 0xD02EE87E +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_ILEVEL_5___POR 0x1A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_ILEVEL_B2_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_AUX1_5___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_AUX0_5___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_5___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_CASOFF_BIAS_5___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_CELL_EN_5___POR 0x03F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_VDD_SW_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_ILEVEL_5___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_ILEVEL_5___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_ILEVEL_B2_5___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_ILEVEL_B2_5___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_AUX1_5___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_AUX1_5___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_AUX0_5___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_AUX0_5___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_5___M 0x0000E000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_5___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_CASOFF_BIAS_5___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_CASOFF_BIAS_5___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_CELL_EN_5___M 0x000003FE +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_CELL_EN_5___S 1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_VDD_SW_5___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5__PPA_VDD_SW_5___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT0_5___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_0 (0x005E93D0) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_0___POR 0x57000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_0__PPA_CTUNE_0_FCSA___POR 0x0A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_0__PPA_CTUNE_DEQ_0_FCSA___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_0__PPA_RTUNE_0_FCSA___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_0__PPA_XFMR_SW_EN_0_FCSA___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_0__PPA_CTUNE_0_FCSA___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_0__PPA_CTUNE_0_FCSA___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_0__PPA_CTUNE_DEQ_0_FCSA___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_0__PPA_CTUNE_DEQ_0_FCSA___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_0__PPA_RTUNE_0_FCSA___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_0__PPA_RTUNE_0_FCSA___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_0__PPA_XFMR_SW_EN_0_FCSA___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_0__PPA_XFMR_SW_EN_0_FCSA___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_0___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_0___S 19 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_1 (0x005E93D4) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_1___POR 0x57000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_1__PPA_CTUNE_1_FCSA___POR 0x0A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_1__PPA_CTUNE_DEQ_1_FCSA___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_1__PPA_RTUNE_1_FCSA___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_1__PPA_XFMR_SW_EN_1_FCSA___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_1__PPA_CTUNE_1_FCSA___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_1__PPA_CTUNE_1_FCSA___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_1__PPA_CTUNE_DEQ_1_FCSA___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_1__PPA_CTUNE_DEQ_1_FCSA___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_1__PPA_RTUNE_1_FCSA___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_1__PPA_RTUNE_1_FCSA___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_1__PPA_XFMR_SW_EN_1_FCSA___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_1__PPA_XFMR_SW_EN_1_FCSA___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_1___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_1___S 19 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_2 (0x005E93D8) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_2___POR 0x57000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_2__PPA_CTUNE_2_FCSA___POR 0x0A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_2__PPA_CTUNE_DEQ_2_FCSA___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_2__PPA_RTUNE_2_FCSA___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_2__PPA_XFMR_SW_EN_2_FCSA___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_2__PPA_CTUNE_2_FCSA___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_2__PPA_CTUNE_2_FCSA___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_2__PPA_CTUNE_DEQ_2_FCSA___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_2__PPA_CTUNE_DEQ_2_FCSA___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_2__PPA_RTUNE_2_FCSA___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_2__PPA_RTUNE_2_FCSA___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_2__PPA_XFMR_SW_EN_2_FCSA___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_2__PPA_XFMR_SW_EN_2_FCSA___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_2___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_2___S 19 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_3 (0x005E93DC) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_3___POR 0x57000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_3__PPA_CTUNE_3_FCSA___POR 0x0A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_3__PPA_CTUNE_DEQ_3_FCSA___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_3__PPA_RTUNE_3_FCSA___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_3__PPA_XFMR_SW_EN_3_FCSA___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_3__PPA_CTUNE_3_FCSA___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_3__PPA_CTUNE_3_FCSA___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_3__PPA_CTUNE_DEQ_3_FCSA___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_3__PPA_CTUNE_DEQ_3_FCSA___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_3__PPA_RTUNE_3_FCSA___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_3__PPA_RTUNE_3_FCSA___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_3__PPA_XFMR_SW_EN_3_FCSA___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_3__PPA_XFMR_SW_EN_3_FCSA___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_3___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_3___S 19 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_4 (0x005E93E0) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_4___POR 0x57000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_4__PPA_CTUNE_4_FCSA___POR 0x0A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_4__PPA_CTUNE_DEQ_4_FCSA___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_4__PPA_RTUNE_4_FCSA___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_4__PPA_XFMR_SW_EN_4_FCSA___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_4__PPA_CTUNE_4_FCSA___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_4__PPA_CTUNE_4_FCSA___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_4__PPA_CTUNE_DEQ_4_FCSA___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_4__PPA_CTUNE_DEQ_4_FCSA___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_4__PPA_RTUNE_4_FCSA___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_4__PPA_RTUNE_4_FCSA___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_4__PPA_XFMR_SW_EN_4_FCSA___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_4__PPA_XFMR_SW_EN_4_FCSA___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_4___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_4___S 19 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_5 (0x005E93E4) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_5___POR 0x57000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_5__PPA_CTUNE_5_FCSA___POR 0x0A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_5__PPA_CTUNE_DEQ_5_FCSA___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_5__PPA_RTUNE_5_FCSA___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_5__PPA_XFMR_SW_EN_5_FCSA___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_5__PPA_CTUNE_5_FCSA___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_5__PPA_CTUNE_5_FCSA___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_5__PPA_CTUNE_DEQ_5_FCSA___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_5__PPA_CTUNE_DEQ_5_FCSA___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_5__PPA_RTUNE_5_FCSA___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_5__PPA_RTUNE_5_FCSA___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_5__PPA_XFMR_SW_EN_5_FCSA___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_5__PPA_XFMR_SW_EN_5_FCSA___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_5___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT1_5___S 19 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_0 (0x005E93F0) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_0___POR 0x57000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_0__PPA_CTUNE_0_FCSB___POR 0x0A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_0__PPA_CTUNE_DEQ_0_FCSB___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_0__PPA_RTUNE_0_FCSB___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_0__PPA_XFMR_SW_EN_0_FCSB___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_0__PPA_CTUNE_0_FCSB___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_0__PPA_CTUNE_0_FCSB___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_0__PPA_CTUNE_DEQ_0_FCSB___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_0__PPA_CTUNE_DEQ_0_FCSB___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_0__PPA_RTUNE_0_FCSB___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_0__PPA_RTUNE_0_FCSB___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_0__PPA_XFMR_SW_EN_0_FCSB___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_0__PPA_XFMR_SW_EN_0_FCSB___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_0___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_0___S 19 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_1 (0x005E93F4) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_1___POR 0x57000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_1__PPA_CTUNE_1_FCSB___POR 0x0A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_1__PPA_CTUNE_DEQ_1_FCSB___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_1__PPA_RTUNE_1_FCSB___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_1__PPA_XFMR_SW_EN_1_FCSB___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_1__PPA_CTUNE_1_FCSB___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_1__PPA_CTUNE_1_FCSB___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_1__PPA_CTUNE_DEQ_1_FCSB___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_1__PPA_CTUNE_DEQ_1_FCSB___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_1__PPA_RTUNE_1_FCSB___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_1__PPA_RTUNE_1_FCSB___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_1__PPA_XFMR_SW_EN_1_FCSB___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_1__PPA_XFMR_SW_EN_1_FCSB___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_1___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_1___S 19 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_2 (0x005E93F8) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_2___POR 0x57000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_2__PPA_CTUNE_2_FCSB___POR 0x0A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_2__PPA_CTUNE_DEQ_2_FCSB___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_2__PPA_RTUNE_2_FCSB___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_2__PPA_XFMR_SW_EN_2_FCSB___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_2__PPA_CTUNE_2_FCSB___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_2__PPA_CTUNE_2_FCSB___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_2__PPA_CTUNE_DEQ_2_FCSB___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_2__PPA_CTUNE_DEQ_2_FCSB___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_2__PPA_RTUNE_2_FCSB___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_2__PPA_RTUNE_2_FCSB___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_2__PPA_XFMR_SW_EN_2_FCSB___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_2__PPA_XFMR_SW_EN_2_FCSB___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_2___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_2___S 19 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_3 (0x005E93FC) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_3___POR 0x57000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_3__PPA_CTUNE_3_FCSB___POR 0x0A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_3__PPA_CTUNE_DEQ_3_FCSB___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_3__PPA_RTUNE_3_FCSB___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_3__PPA_XFMR_SW_EN_3_FCSB___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_3__PPA_CTUNE_3_FCSB___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_3__PPA_CTUNE_3_FCSB___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_3__PPA_CTUNE_DEQ_3_FCSB___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_3__PPA_CTUNE_DEQ_3_FCSB___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_3__PPA_RTUNE_3_FCSB___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_3__PPA_RTUNE_3_FCSB___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_3__PPA_XFMR_SW_EN_3_FCSB___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_3__PPA_XFMR_SW_EN_3_FCSB___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_3___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_3___S 19 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_4 (0x005E9400) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_4___POR 0x57000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_4__PPA_CTUNE_4_FCSB___POR 0x0A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_4__PPA_CTUNE_DEQ_4_FCSB___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_4__PPA_RTUNE_4_FCSB___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_4__PPA_XFMR_SW_EN_4_FCSB___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_4__PPA_CTUNE_4_FCSB___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_4__PPA_CTUNE_4_FCSB___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_4__PPA_CTUNE_DEQ_4_FCSB___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_4__PPA_CTUNE_DEQ_4_FCSB___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_4__PPA_RTUNE_4_FCSB___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_4__PPA_RTUNE_4_FCSB___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_4__PPA_XFMR_SW_EN_4_FCSB___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_4__PPA_XFMR_SW_EN_4_FCSB___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_4___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_4___S 19 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_5 (0x005E9404) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_5___POR 0x57000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_5__PPA_CTUNE_5_FCSB___POR 0x0A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_5__PPA_CTUNE_DEQ_5_FCSB___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_5__PPA_RTUNE_5_FCSB___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_5__PPA_XFMR_SW_EN_5_FCSB___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_5__PPA_CTUNE_5_FCSB___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_5__PPA_CTUNE_5_FCSB___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_5__PPA_CTUNE_DEQ_5_FCSB___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_5__PPA_CTUNE_DEQ_5_FCSB___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_5__PPA_RTUNE_5_FCSB___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_5__PPA_RTUNE_5_FCSB___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_5__PPA_XFMR_SW_EN_5_FCSB___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_5__PPA_XFMR_SW_EN_5_FCSB___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_5___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT2_5___S 19 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_0 (0x005E9410) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_0___POR 0x07000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_0__PPA_CELL_AUX_EN_0___POR 0x07 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_0__PPA_CELL_AUX_EN_0___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_0__PPA_CELL_AUX_EN_0___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_0___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_0___S 24 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_1 (0x005E9414) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_1___POR 0x07000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_1__PPA_CELL_AUX_EN_1___POR 0x07 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_1__PPA_CELL_AUX_EN_1___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_1__PPA_CELL_AUX_EN_1___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_1___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_1___S 24 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_2 (0x005E9418) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_2___POR 0x0F000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_2__PPA_CELL_AUX_EN_2___POR 0x0F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_2__PPA_CELL_AUX_EN_2___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_2__PPA_CELL_AUX_EN_2___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_2___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_2___S 24 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_3 (0x005E941C) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_3___POR 0x0F000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_3__PPA_CELL_AUX_EN_3___POR 0x0F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_3__PPA_CELL_AUX_EN_3___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_3__PPA_CELL_AUX_EN_3___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_3___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_3___S 24 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_4 (0x005E9420) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_4___POR 0x3F000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_4__PPA_CELL_AUX_EN_4___POR 0x3F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_4__PPA_CELL_AUX_EN_4___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_4__PPA_CELL_AUX_EN_4___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_4___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_4___S 24 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_5 (0x005E9424) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_5___POR 0x3F000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_5__PPA_CELL_AUX_EN_5___POR 0x3F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_5__PPA_CELL_AUX_EN_5___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_5__PPA_CELL_AUX_EN_5___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_5___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA_LUT3_5___S 24 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0 (0x005E9430) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0___POR 0x882E3400 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_ILEVEL_0___POR 0x11 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_ILEVEL_B2_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX1_0___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX0_0___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_0___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_CASOFF_BIAS_0___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_ILEVEL_0___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_ILEVEL_0___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_ILEVEL_B2_0___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_ILEVEL_B2_0___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX1_0___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX1_0___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX0_0___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX0_0___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_0___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_0___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_CASOFF_BIAS_0___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0__PA_CASOFF_BIAS_0___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_0___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1 (0x005E9434) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1___POR 0x882E3400 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_ILEVEL_1___POR 0x11 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_ILEVEL_B2_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX1_1___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX0_1___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_1___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_CASOFF_BIAS_1___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_ILEVEL_1___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_ILEVEL_1___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_ILEVEL_B2_1___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_ILEVEL_B2_1___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX1_1___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX1_1___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX0_1___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX0_1___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_1___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_1___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_CASOFF_BIAS_1___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1__PA_CASOFF_BIAS_1___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_1___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2 (0x005E9438) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2___POR 0x882E3400 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_ILEVEL_2___POR 0x11 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_ILEVEL_B2_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX1_2___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX0_2___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_2___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_CASOFF_BIAS_2___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_ILEVEL_2___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_ILEVEL_2___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_ILEVEL_B2_2___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_ILEVEL_B2_2___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX1_2___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX1_2___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX0_2___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX0_2___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_2___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_2___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_CASOFF_BIAS_2___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2__PA_CASOFF_BIAS_2___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_2___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3 (0x005E943C) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3___POR 0x882E3400 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_ILEVEL_3___POR 0x11 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_ILEVEL_B2_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX1_3___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX0_3___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_3___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_CASOFF_BIAS_3___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_ILEVEL_3___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_ILEVEL_3___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_ILEVEL_B2_3___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_ILEVEL_B2_3___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX1_3___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX1_3___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX0_3___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX0_3___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_3___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_3___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_CASOFF_BIAS_3___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3__PA_CASOFF_BIAS_3___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_3___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4 (0x005E9440) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4___POR 0x882E3400 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_ILEVEL_4___POR 0x11 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_ILEVEL_B2_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX1_4___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX0_4___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_4___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_CASOFF_BIAS_4___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_ILEVEL_4___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_ILEVEL_4___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_ILEVEL_B2_4___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_ILEVEL_B2_4___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX1_4___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX1_4___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX0_4___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX0_4___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_4___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_4___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_CASOFF_BIAS_4___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4__PA_CASOFF_BIAS_4___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_4___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5 (0x005E9444) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5___POR 0x882E3400 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_ILEVEL_5___POR 0x11 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_ILEVEL_B2_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX1_5___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX0_5___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_5___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_CASOFF_BIAS_5___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_ILEVEL_5___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_ILEVEL_5___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_ILEVEL_B2_5___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_ILEVEL_B2_5___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX1_5___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX1_5___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX0_5___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX0_5___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_5___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_5___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_CASOFF_BIAS_5___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5__PA_CASOFF_BIAS_5___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT0_5___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_0 (0x005E9450) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_0___POR 0x10040000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_0__PA_CELL_EN1_0___POR 0x040 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_0__PA_CELL_EN0_0___POR 0x040 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_0__PA_CELL_EN1_0___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_0__PA_CELL_EN1_0___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_0__PA_CELL_EN0_0___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_0__PA_CELL_EN0_0___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_0___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_0___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_1 (0x005E9454) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_1___POR 0x18050000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_1__PA_CELL_EN1_1___POR 0x060 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_1__PA_CELL_EN0_1___POR 0x050 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_1__PA_CELL_EN1_1___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_1__PA_CELL_EN1_1___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_1__PA_CELL_EN0_1___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_1__PA_CELL_EN0_1___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_1___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_1___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_2 (0x005E9458) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_2___POR 0x18050000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_2__PA_CELL_EN1_2___POR 0x060 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_2__PA_CELL_EN0_2___POR 0x050 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_2__PA_CELL_EN1_2___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_2__PA_CELL_EN1_2___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_2__PA_CELL_EN0_2___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_2__PA_CELL_EN0_2___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_2___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_2___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_3 (0x005E945C) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_3___POR 0x1B05C000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_3__PA_CELL_EN1_3___POR 0x06C +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_3__PA_CELL_EN0_3___POR 0x05C +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_3__PA_CELL_EN1_3___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_3__PA_CELL_EN1_3___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_3__PA_CELL_EN0_3___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_3__PA_CELL_EN0_3___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_3___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_3___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_4 (0x005E9460) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_4___POR 0x1B05C000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_4__PA_CELL_EN1_4___POR 0x06C +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_4__PA_CELL_EN0_4___POR 0x05C +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_4__PA_CELL_EN1_4___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_4__PA_CELL_EN1_4___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_4__PA_CELL_EN0_4___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_4__PA_CELL_EN0_4___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_4___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_4___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_5 (0x005E9464) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_5___POR 0x1BC5F000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_5__PA_CELL_EN1_5___POR 0x06F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_5__PA_CELL_EN0_5___POR 0x05F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_5__PA_CELL_EN1_5___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_5__PA_CELL_EN1_5___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_5__PA_CELL_EN0_5___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_5__PA_CELL_EN0_5___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_5___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA_LUT1_5___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0 (0x005E9470) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_CTUNE3FLO_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_CTUNE3FLO_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_CTUNE1FLO_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_CTUNE1FLO_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__DA_CTUNE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__DA_CTUNE_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_RGAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_RGAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_LSW_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_CTUNE3FLO_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_CTUNE3FLO_OV___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_CTUNE3FLO_OVD___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_CTUNE3FLO_OVD___S 25 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_CTUNE1FLO_OV___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_CTUNE1FLO_OV___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_CTUNE1FLO_OVD___M 0x00FC0000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_CTUNE1FLO_OVD___S 18 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__DA_CTUNE_OV___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__DA_CTUNE_OV___S 17 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__DA_CTUNE_OVD___M 0x0001F000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__DA_CTUNE_OVD___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_RGAIN_OV___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_RGAIN_OV___S 11 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_RGAIN_OVD___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_RGAIN_OVD___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_LSW_EN_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0__UPC_LSW_EN_OVS___S 6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0___M 0xFFFFFFC0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV0___S 6 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1 (0x005E9474) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CELL_EN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CELL_EN_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CELL_AUX_EN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CELL_AUX_EN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CASOFF_BIAS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CASOFF_BIAS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CELL_EN_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CELL_EN_OV___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CELL_EN_OVD___M 0x7FC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CELL_EN_OVD___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CELL_AUX_EN_OV___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CELL_AUX_EN_OV___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CELL_AUX_EN_OVD___M 0x001FE000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CELL_AUX_EN_OVD___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CASOFF_BIAS_OV___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CASOFF_BIAS_OV___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CASOFF_BIAS_OVD___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1__DA_CASOFF_BIAS_OVD___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV1___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2 (0x005E9478) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CTUNE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CTUNE_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CTUNE_DEQ_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CTUNE_DEQ_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_RTUNE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_RTUNE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_ILEVEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_ILEVEL_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_ILEVEL_B2_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_ILEVEL_B2_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CAS_BIAS_AUX1_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CAS_BIAS_AUX1_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CTUNE_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CTUNE_OV___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CTUNE_OVD___M 0x7C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CTUNE_OVD___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CTUNE_DEQ_OV___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CTUNE_DEQ_OV___S 25 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CTUNE_DEQ_OVD___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CTUNE_DEQ_OVD___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_RTUNE_OV___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_RTUNE_OV___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_RTUNE_OVD___M 0x001E0000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_RTUNE_OVD___S 17 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_ILEVEL_OV___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_ILEVEL_OV___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_ILEVEL_OVD___M 0x0000F800 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_ILEVEL_OVD___S 11 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_ILEVEL_B2_OV___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_ILEVEL_B2_OV___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_ILEVEL_B2_OVD___M 0x000003E0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_ILEVEL_B2_OVD___S 5 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CAS_BIAS_AUX1_OV___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CAS_BIAS_AUX1_OV___S 4 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CAS_BIAS_AUX1_OVD___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2__PPA_CAS_BIAS_AUX1_OVD___S 1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV2___S 1 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3 (0x005E947C) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CAS_BIAS_AUX0_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CAS_BIAS_AUX0_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CAS_BIAS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CAS_BIAS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CASOFF_BIAS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CASOFF_BIAS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CELL_EN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CELL_EN_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CELL_AUX_EN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CELL_AUX_EN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CAS_BIAS_AUX0_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CAS_BIAS_AUX0_OV___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CAS_BIAS_AUX0_OVD___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CAS_BIAS_AUX0_OVD___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CAS_BIAS_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CAS_BIAS_OV___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CAS_BIAS_OVD___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CAS_BIAS_OVD___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CASOFF_BIAS_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CASOFF_BIAS_OV___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CASOFF_BIAS_OVD___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CASOFF_BIAS_OVD___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CELL_EN_OV___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CELL_EN_OV___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CELL_EN_OVD___M 0x0007FC00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CELL_EN_OVD___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CELL_AUX_EN_OV___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CELL_AUX_EN_OV___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CELL_AUX_EN_OVD___M 0x000001FE +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3__PPA_CELL_AUX_EN_OVD___S 1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV3___S 1 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4 (0x005E9480) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PPA_XFMR_SW_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PPA_VDD_SW_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_ILEVEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_ILEVEL_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_ILEVEL_B2_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_ILEVEL_B2_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_AUX1_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_AUX1_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_AUX0_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_AUX0_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PPA_XFMR_SW_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PPA_XFMR_SW_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PPA_VDD_SW_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PPA_VDD_SW_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_ILEVEL_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_ILEVEL_OV___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_ILEVEL_OVD___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_ILEVEL_OVD___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_ILEVEL_B2_OV___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_ILEVEL_B2_OV___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_ILEVEL_B2_OVD___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_ILEVEL_B2_OVD___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_AUX1_OV___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_AUX1_OV___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_AUX1_OVD___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_AUX1_OVD___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_AUX0_OV___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_AUX0_OV___S 11 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_AUX0_OVD___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_AUX0_OVD___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_OV___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_OV___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_OVD___M 0x00000078 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4__PA_CAS_BIAS_OVD___S 3 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4___M 0xFFFFFFF8 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV4___S 3 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5 (0x005E9484) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CASOFF_BIAS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CASOFF_BIAS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CELL_EN1_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CELL_EN1_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CELL_EN0_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CELL_EN0_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CASOFF_BIAS_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CASOFF_BIAS_OV___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CASOFF_BIAS_OVD___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CASOFF_BIAS_OVD___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CELL_EN1_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CELL_EN1_OV___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CELL_EN1_OVD___M 0x07FE0000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CELL_EN1_OVD___S 17 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CELL_EN0_OV___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CELL_EN0_OV___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CELL_EN0_OVD___M 0x0000FFC0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5__PA_CELL_EN0_OVD___S 6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5___M 0xFFFFFFC0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_LUT_OV5___S 6 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV0 (0x005E9488) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV0___POR 0x000C0000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV0__TX_SINGLE_RU_OVS___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV0__TX_LO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV0__TX_LO_LP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV0__TX_SINGLE_RU_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV0__TX_SINGLE_RU_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV0__TX_LO_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV0__TX_LO_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV0__TX_LO_LP_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV0__TX_LO_LP_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV0___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV0___S 14 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1 (0x005E948C) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__CALRTX_ATTN_GM_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__CALRTX_PHASESHIFT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__DA_BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__TXLO_INBUF25DC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__TXLO_LP_INBUF25DC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_AUX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_LO_EN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_LO_EN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_EN_NMX_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_EN_NMX_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_EN_PMX_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_EN_PMX_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__CALRTX_ATTN_GM_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__CALRTX_ATTN_GM_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__CALRTX_PHASESHIFT_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__CALRTX_PHASESHIFT_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__DA_BIAS_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__DA_BIAS_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__TXLO_INBUF25DC_EN_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__TXLO_INBUF25DC_EN_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__TXLO_LP_INBUF25DC_EN_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__TXLO_LP_INBUF25DC_EN_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_AUX_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_AUX_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_LO_EN_OV___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_LO_EN_OV___S 18 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_LO_EN_OVD___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_LO_EN_OVD___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_EN_NMX_OV___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_EN_NMX_OV___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_EN_NMX_OVD___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_EN_NMX_OVD___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_EN_PMX_OV___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_EN_PMX_OV___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_EN_PMX_OVD___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1__UPC_EN_PMX_OVD___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1___M 0xFFF7FC00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV1___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2 (0x005E9490) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_BUFTLINE1ST_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_BUFTLINE2ND_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_LP_BUFTLINE1ST_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_LP_BUFTLINE2ND_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_OBUF25DC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_LP_OBUF25DC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__PPA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__PA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__WL_DPD5_IPA_SW_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__WL_DPD5_IPA_CALTXSHIFT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__WL_DPD5_IPA_GM_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__DA_IPA_PATH_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_BUFTLINE1ST_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_BUFTLINE1ST_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_BUFTLINE2ND_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_BUFTLINE2ND_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_LP_BUFTLINE1ST_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_LP_BUFTLINE1ST_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_LP_BUFTLINE2ND_EN_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_LP_BUFTLINE2ND_EN_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_OBUF25DC_EN_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_OBUF25DC_EN_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_LP_OBUF25DC_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__TXLO_LP_OBUF25DC_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__PPA_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__PPA_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__PA_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__PA_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__WL_DPD5_IPA_SW_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__WL_DPD5_IPA_SW_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__WL_DPD5_IPA_CALTXSHIFT_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__WL_DPD5_IPA_CALTXSHIFT_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__WL_DPD5_IPA_GM_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__WL_DPD5_IPA_GM_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__DA_IPA_PATH_EN_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2__DA_IPA_PATH_EN_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2___M 0xFFFFFF00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_OV2___S 8 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0 (0x005E9494) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_UPC_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_DA_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_FCS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_DA_CTUNE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_TX_SINGLE_RU___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_IPA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_DA_CASOFF_BIAS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_UPC_GAIN___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_UPC_GAIN___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_DA_GAIN___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_DA_GAIN___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_FCS___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_FCS___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_DA_CTUNE___M 0x007C0000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_DA_CTUNE___S 18 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_TX_SINGLE_RU___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_TX_SINGLE_RU___S 17 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_IPA_GAIN___M 0x0001C000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_IPA_GAIN___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_DA_CASOFF_BIAS___M 0x00003800 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0__RO_DA_CASOFF_BIAS___S 11 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0___M 0xFFFFF800 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT0___S 11 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1 (0x005E9498) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1__RO_DA_CELL_EN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1__RO_DA_CELL_AUX_EN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1__RO_UPC_RGAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1__RO_UPC_CTUNE3FLO___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1__RO_UPC_CTUNE1FLO___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1__RO_DA_CELL_EN___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1__RO_DA_CELL_EN___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1__RO_DA_CELL_AUX_EN___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1__RO_DA_CELL_AUX_EN___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1__RO_UPC_RGAIN___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1__RO_UPC_RGAIN___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1__RO_UPC_CTUNE3FLO___M 0x00000FC0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1__RO_UPC_CTUNE3FLO___S 6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1__RO_UPC_CTUNE1FLO___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1__RO_UPC_CTUNE1FLO___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT1___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2 (0x005E949C) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_UPC_LSW_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_ILEVEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_ILEVEL_B2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_CTUNE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_CTUNE_DEQ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_RTUNE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS_AUX1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS_AUX0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_UPC_LSW_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_UPC_LSW_EN___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_ILEVEL___M 0x7C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_ILEVEL___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_ILEVEL_B2___M 0x03E00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_ILEVEL_B2___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_CTUNE___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_CTUNE___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_CTUNE_DEQ___M 0x0000E000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_CTUNE_DEQ___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_RTUNE___M 0x00001E00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_RTUNE___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS_AUX1___M 0x000001C0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS_AUX1___S 6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS_AUX0___M 0x00000038 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS_AUX0___S 3 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT2___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3 (0x005E94A0) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PPA_CASOFF_BIAS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PPA_CELL_EN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PPA_CELL_AUX_EN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PPA_XFMR_SW_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PPA_VDD_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PA_ILEVEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PA_ILEVEL_B2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PPA_CASOFF_BIAS___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PPA_CASOFF_BIAS___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PPA_CELL_EN___M 0x1FF00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PPA_CELL_EN___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PPA_CELL_AUX_EN___M 0x000FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PPA_CELL_AUX_EN___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PPA_XFMR_SW_EN___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PPA_XFMR_SW_EN___S 11 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PPA_VDD_SW___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PPA_VDD_SW___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PA_ILEVEL___M 0x000003E0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PA_ILEVEL___S 5 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PA_ILEVEL_B2___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3__RO_PA_ILEVEL_B2___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT3___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4 (0x005E94A4) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4__RO_PA_CASOFF_BIAS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4__RO_PA_CELL_EN1___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX1___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX1___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX0___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX0___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4__RO_PA_CASOFF_BIAS___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4__RO_PA_CASOFF_BIAS___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4__RO_PA_CELL_EN1___M 0x0007FE00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4__RO_PA_CELL_EN1___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT4___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT5 (0x005E94A8) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT5___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT5__RO_PA_CELL_EN0___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT5__RO_PA_CELL_EN0___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT5__RO_PA_CELL_EN0___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT5___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LUT5___S 22 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0 (0x005E94AC) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0__RO_PPA_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0__RO_PA_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_SW_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_CALTXSHIFT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_GM_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0__RO_PPA_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0__RO_PPA_EN___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0__RO_PA_EN___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0__RO_PA_EN___S 30 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_SW_EN___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_SW_EN___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_CALTXSHIFT___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_CALTXSHIFT___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_GM_EN___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_GM_EN___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_RO_WL_TXFE_LOGIC0___S 27 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0 (0x005E94B0) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0___POR 0x118A0E00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_IBIAS_LOWER_LIM_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_IBIAS_LOWER_LIM___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_ISLOPE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_CAS_BIAS___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_CAS_BIAS_AUX___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_ILEVEL_COARSE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_ILEVEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_BIAS_NOISE_CNCL_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_BIAS_NOISE_CNCL_RES___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_IBIAS_LOWER_LIM_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_IBIAS_LOWER_LIM_EN___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_IBIAS_LOWER_LIM___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_IBIAS_LOWER_LIM___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_ISLOPE___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_ISLOPE___S 25 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_CAS_BIAS___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_CAS_BIAS___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_CAS_BIAS_AUX___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_CAS_BIAS_AUX___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_ILEVEL_COARSE___M 0x00060000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_ILEVEL_COARSE___S 17 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_ILEVEL___M 0x00018000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_ILEVEL___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_ATB_SEL___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_ATB_SEL___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_BIAS_NOISE_CNCL_EN___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_BIAS_NOISE_CNCL_EN___S 11 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_BIAS_NOISE_CNCL_RES___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0__D_DA_BIAS_NOISE_CNCL_RES___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0___M 0xFFFFFF00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DA0___S 8 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC0 (0x005E94B4) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC0___POR 0x74000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC0__D_UPC_RSHIFTN___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC0__D_UPC_RSHIFTP___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC0__D_UPC_RMXFILT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC0__D_UPC_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC0__D_UPC_RSHIFTN___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC0__D_UPC_RSHIFTN___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC0__D_UPC_RSHIFTP___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC0__D_UPC_RSHIFTP___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC0__D_UPC_RMXFILT___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC0__D_UPC_RMXFILT___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC0__D_UPC_ATB_SEL___M 0x00600000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC0__D_UPC_ATB_SEL___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC0___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_UPC0___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0 (0x005E94B8) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0___POR 0x00FF00FF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_IP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_QP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_IP___POR 0xF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_QP___POR 0xF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_IP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_QP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_IP___POR 0xF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_QP___POR 0xF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_IP___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_IP___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_QP___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_QP___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_IP___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_IP___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_QP___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_QP___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_IP___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_IP___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_QP___M 0x00000F00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_QP___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_IP___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_IP___S 4 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_QP___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_QP___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO0___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1 (0x005E94BC) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1___POR 0x00FF00FF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_IN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_QN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_IN___POR 0xF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_QN___POR 0xF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_IN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_QN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_IN___POR 0xF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_QN___POR 0xF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_IN___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_IN___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_QN___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_QN___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_IN___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_IN___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_QN___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_QN___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_IN___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_IN___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_QN___M 0x00000F00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_QN___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_IN___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_IN___S 4 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_QN___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_QN___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_LO1___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL (0x005E94C0) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL___POR 0x04000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL__D_CALRTX_GC___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL__D_CALRTX_SW_FLP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL__D_CALRTX_RES_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL__D_CALRTX_IBIAS___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL__D_CALRTX_GC___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL__D_CALRTX_GC___S 30 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL__D_CALRTX_SW_FLP___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL__D_CALRTX_SW_FLP___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL__D_CALRTX_RES_CTRL___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL__D_CALRTX_RES_CTRL___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL__D_CALRTX_IBIAS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL__D_CALRTX_IBIAS___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL___S 26 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_SPARE (0x005E94C4) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_SPARE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_SPARE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_SPARE__D_TXFE_SPARE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_SPARE__D_TXFE_SPARE___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_SPARE__D_TXFE_SPARE___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_SPARE___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_SPARE___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0 (0x005E94C8) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0___POR 0xAE000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0__D_PPA_IBIAS_LOWER_LIM_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0__D_PPA_IBIAS_LOWER_LIM___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0__D_PPA_ISLOPE___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0__D_PPA_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0__D_PPA_INPUT_SW_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0__D_PPA_IBIAS_LOWER_LIM_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0__D_PPA_IBIAS_LOWER_LIM_EN___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0__D_PPA_IBIAS_LOWER_LIM___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0__D_PPA_IBIAS_LOWER_LIM___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0__D_PPA_ISLOPE___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0__D_PPA_ISLOPE___S 25 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0__D_PPA_ATB_SEL___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0__D_PPA_ATB_SEL___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0__D_PPA_INPUT_SW_EN___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0__D_PPA_INPUT_SW_EN___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PPA0___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA0 (0x005E94CC) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA0___POR 0xAA000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA0__D_PA_IBIAS_LOWER_LIM_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA0__D_PA_IBIAS_LOWER_LIM___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA0__D_PA_ISLOPE___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA0__D_PA_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA0__D_PA_IBIAS_LOWER_LIM_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA0__D_PA_IBIAS_LOWER_LIM_EN___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA0__D_PA_IBIAS_LOWER_LIM___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA0__D_PA_IBIAS_LOWER_LIM___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA0__D_PA_ISLOPE___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA0__D_PA_ISLOPE___S 25 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA0__D_PA_ATB_SEL___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA0__D_PA_ATB_SEL___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA0___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_PA0___S 22 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL_DUMMY (0x005E94D0) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL_DUMMY___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL_DUMMY___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL_DUMMY__D_DTOP_CAL_DUMMY1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL_DUMMY__D_DTOP_CAL_DUMMY0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL_DUMMY__D_DTOP_DUMMY1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL_DUMMY__D_DTOP_DUMMY0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL_DUMMY__D_DTOP_CAL_DUMMY1___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL_DUMMY__D_DTOP_CAL_DUMMY1___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL_DUMMY__D_DTOP_CAL_DUMMY0___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL_DUMMY__D_DTOP_CAL_DUMMY0___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL_DUMMY__D_DTOP_DUMMY1___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL_DUMMY__D_DTOP_DUMMY1___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL_DUMMY__D_DTOP_DUMMY0___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL_DUMMY__D_DTOP_DUMMY0___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL_DUMMY___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_CAL_DUMMY___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD (0x005E94D4) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD___POR 0x08B80000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_NOTCH_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_CALTXSHIFT_RES_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_TAIL_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_IBIAS_CTRL___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_DEGEN_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_VCAS_CTRL___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_ATTN_CTRL___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_NOTCH_CTRL___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_NOTCH_CTRL___S 30 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_CALTXSHIFT_RES_CTRL___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_CALTXSHIFT_RES_CTRL___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_TAIL_SW___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_TAIL_SW___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_IBIAS_CTRL___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_IBIAS_CTRL___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_DEGEN_CTRL___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_DEGEN_CTRL___S 25 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_VCAS_CTRL___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_VCAS_CTRL___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_ATTN_CTRL___M 0x00780000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD__D_WL_DPD5_IPA_ATTN_CTRL___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_DPD___S 19 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR (0x005E94D8) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR___POR 0x6C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR__D_TS_REF_RTUNE___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR__D_TS_RTUNE___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR__D_TS_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR__TS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR__TS_SRC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR__D_TS_REF_RTUNE___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR__D_TS_REF_RTUNE___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR__D_TS_RTUNE___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR__D_TS_RTUNE___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR__D_TS_ATB_SEL___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR__D_TS_ATB_SEL___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR__TS_EN_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR__TS_EN_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR__TS_SRC_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR__TS_SRC_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR___M 0xFDF00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH0_WL_TXFE_TSENSOR___S 20 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CTRL_0 (0x005EA000) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CTRL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CTRL_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CTRL_0__TPC_STOP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CTRL_0__TPC_STOP___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CTRL_0__TPC_STOP___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CTRL_0___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CTRL_0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT (0x005EA004) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_TEMP_VALID___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_FULLPKT_PWR_VALID___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_PREAMBLE_PWR_VALID___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_TEMP___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_FULLPKT_PWR___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_PREAMBLE_PWR___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_TEMP_VALID___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_TEMP_VALID___S 26 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_FULLPKT_PWR_VALID___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_FULLPKT_PWR_VALID___S 25 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_PREAMBLE_PWR_VALID___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_PREAMBLE_PWR_VALID___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_TEMP___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_TEMP___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_FULLPKT_PWR___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_FULLPKT_PWR___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_PREAMBLE_PWR___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT__RO_PREAMBLE_PWR___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT___M 0x07FFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_RESULT___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0 (0x005EA040) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0___POR 0x000A0026 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__PDADC_CLK_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__PDADC_TEST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_HI_IN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_MID_IN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_LO_IN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_BIAS_COMP_IN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_BIAS_REFBUFF_IN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_PRECHARGEC_IN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ATEST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ATEST_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_SPARE___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_FSMODE_IN___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__PDADC_CLK_SEL___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__PDADC_CLK_SEL___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__PDADC_TEST_EN___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__PDADC_TEST_EN___S 30 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_HI_IN___M 0x38000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_HI_IN___S 27 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_MID_IN___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_MID_IN___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_LO_IN___M 0x00E00000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_LO_IN___S 21 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_BIAS_COMP_IN___M 0x00180000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_BIAS_COMP_IN___S 19 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_BIAS_REFBUFF_IN___M 0x00060000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_BIAS_REFBUFF_IN___S 17 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_PRECHARGEC_IN___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ADJ_VREF_PRECHARGEC_IN___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ATEST_EN___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ATEST_EN___S 15 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ATEST_SEL___M 0x00007800 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_ATEST_SEL___S 11 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_SPARE___M 0x000007F8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_SPARE___S 3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_FSMODE_IN___M 0x00000006 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0__D_ADC_FSMODE_IN___S 1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_0___S 1 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_1 (0x005EA044) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_1___POR 0x00004020 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_1__PDADC_CLK_POL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_1__ADC_DATA_COMP_REF_HI_GAIN___POR 0x020 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_1__ADC_DATA_COMP_REF_LO_GAIN___POR 0x020 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_1__PDADC_CLK_POL___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_1__PDADC_CLK_POL___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_1__ADC_DATA_COMP_REF_HI_GAIN___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_1__ADC_DATA_COMP_REF_HI_GAIN___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_1__ADC_DATA_COMP_REF_LO_GAIN___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_1__ADC_DATA_COMP_REF_LO_GAIN___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_1___M 0x0007FFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_PDADC_CTRL_1___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_PDADC_DATA (0x005EA048) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_PDADC_DATA___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_PDADC_DATA___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_PDADC_DATA__RO_D_PDADC_DATA___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_PDADC_DATA__RO_D_PDADC_DATA___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_PDADC_DATA__RO_D_PDADC_DATA___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_PDADC_DATA___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_PDADC_DATA___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0 (0x005EA080) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0___POR 0x0200E8B6 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_RESET_L___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CLK_CFG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_PATH_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_DAC_EN___POR 0xE +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_POL___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_BIN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_SETT___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_SMPL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__DC_OFFSET_MODE_MAX_ATTN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_RESET_L___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_RESET_L___S 25 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CLK_CFG___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CLK_CFG___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_PATH_SEL___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_PATH_SEL___S 22 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_EN___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_EN___S 17 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_DAC_EN___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_DAC_EN___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_POL___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_POL___S 10 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_BIN___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_BIN___S 7 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_SETT___M 0x00000070 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_SETT___S 4 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_SMPL___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__TPC_CAL_SMPL___S 1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__DC_OFFSET_MODE_MAX_ATTN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0__DC_OFFSET_MODE_MAX_ATTN___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0___M 0x03C2FCFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1 (0x005EA084) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1___POR 0x00F80204 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_LG___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_PGA_GAIN_CTRL_HG___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___POR 0x10 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_HG___S 22 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_LG___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__FE_SQ_GAIN_LG___S 20 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_PGA_GAIN_CTRL_HG___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_PGA_GAIN_CTRL_HG___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___M 0x000003E0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___S 5 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1___M 0x00FF03FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2 (0x005EA088) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2___POR 0xECA86420 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_7___POR 0xE +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_6___POR 0xC +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_5___POR 0xA +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_4___POR 0x8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_3___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_2___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_1___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_7___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_7___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_6___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_6___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_5___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_5___S 20 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_4___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_4___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_3___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_3___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_2___M 0x00000F00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_2___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_1___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_1___S 4 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_0___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2__WL_PWR_IDX_0___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_2___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_3 (0x005EA08C) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT___S 4 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT_EN___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_3___M 0x000000F1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_CFG_3___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0 (0x005EA090) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_HI___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_HI_CAL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_HI_CAL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_LO___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_LO_CAL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_LO_CAL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_HI___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_HI___S 30 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_HI_CAL___M 0x0FE00000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_HI_CAL___S 21 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_HI_CAL___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_HI_CAL___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_LO___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_LO___S 14 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_LO_CAL___M 0x00000FE0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_LO_CAL___S 5 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_LO_CAL___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_LO_CAL___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0___M 0x4FFF4FFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_BE_CAL_RESULT_0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0 (0x005EA094) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__BE_INT_PDET_PATH_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__FE_SQ_XPA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__FE_SQ_IPA_IS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__FE_SQ_IPA_PO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__FE_VDET_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__PDADC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__BE_TIA_SQBIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__ADC_VREF_IN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__BE_INT_PDET_PATH_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__BE_INT_PDET_PATH_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__FE_SQ_XPA_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__FE_SQ_XPA_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__FE_SQ_IPA_IS_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__FE_SQ_IPA_IS_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__FE_SQ_IPA_PO_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__FE_SQ_IPA_PO_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__FE_VDET_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__FE_VDET_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__PDADC_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__PDADC_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__BE_TIA_SQBIAS_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__BE_TIA_SQBIAS_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__ADC_VREF_IN_EN_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0__ADC_VREF_IN_EN_OVS___S 4 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0___M 0xC03FFC30 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_0___S 4 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1 (0x005EA098) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__PDET_GAIN_IDX_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_SQ_XPA_DUMMY_CURRENT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_SQ_IPA_IS_DUMMY_CURRENT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_SQ_IPA_PO_DUMMY_CURRENT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_XPA_RF_DISCONNECT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_IPA_IS_RF_DISCONNECT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_IPA_PO_RF_DISCONNECT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__PDET_GAIN_IDX_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__PDET_GAIN_IDX_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_SQ_XPA_DUMMY_CURRENT_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_SQ_XPA_DUMMY_CURRENT_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_SQ_IPA_IS_DUMMY_CURRENT_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_SQ_IPA_IS_DUMMY_CURRENT_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_SQ_IPA_PO_DUMMY_CURRENT_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_SQ_IPA_PO_DUMMY_CURRENT_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_XPA_RF_DISCONNECT_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_XPA_RF_DISCONNECT_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_IPA_IS_RF_DISCONNECT_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_IPA_IS_RF_DISCONNECT_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_IPA_PO_RF_DISCONNECT_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1__FE_IPA_PO_RF_DISCONNECT_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1___M 0x0CFFF000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_1___S 12 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2 (0x005EA09C) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2___POR 0x000C1010 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__FE_R50_ADJ_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__FE_R50_ADJ_OVD___POR 0x30 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OVD___POR 0x10 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OVD___POR 0x10 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__FE_R50_ADJ_OV___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__FE_R50_ADJ_OV___S 20 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__FE_R50_ADJ_OVD___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__FE_R50_ADJ_OVD___S 14 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OV___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OV___S 13 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OVD___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OVD___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OV___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OV___S 5 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OVD___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2___M 0x001FFF3F +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_2___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3 (0x005EA0A0) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3___POR 0x0000B880 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__FE_SQ_IPA_PO_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__FE_SQ_IPA_IS_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__FE_SQ_XPA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_TIA_GAIN_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_PGA_GAIN_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC2_OFFSET_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__TPC_SQR_IC_N_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__TPC_SQR_IC_P_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__TPC_SQR_IPTS_N_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__TPC_SQR_IPTS_P_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OV___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OVD___POR 0x38 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OV___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__FE_SQ_IPA_PO_GAIN_OV___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__FE_SQ_IPA_PO_GAIN_OV___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__FE_SQ_IPA_IS_GAIN_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__FE_SQ_IPA_IS_GAIN_OV___S 27 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__FE_SQ_XPA_GAIN_OV___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__FE_SQ_XPA_GAIN_OV___S 26 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_TIA_GAIN_CTRL_OV___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_TIA_GAIN_CTRL_OV___S 25 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_PGA_GAIN_CTRL_OV___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_PGA_GAIN_CTRL_OV___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_OV___S 23 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC2_OFFSET_OV___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC2_OFFSET_OV___S 22 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__TPC_SQR_IC_N_CTRL_OV___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__TPC_SQR_IC_N_CTRL_OV___S 21 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__TPC_SQR_IC_P_CTRL_OV___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__TPC_SQR_IC_P_CTRL_OV___S 20 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__TPC_SQR_IPTS_N_CTRL_OV___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__TPC_SQR_IPTS_N_CTRL_OV___S 19 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__TPC_SQR_IPTS_P_CTRL_OV___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__TPC_SQR_IPTS_P_CTRL_OV___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OV___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OV___S 15 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OVD___M 0x00007F00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OVD___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OV___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OV___S 7 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OVD___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3___M 0x1FFCFFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_3___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4 (0x005EA0A4) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4___POR 0x01010840 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_R50_ADJ_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OVD___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OVD___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OVD___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OVD___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_R50_ADJ_CTRL_OV___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_R50_ADJ_CTRL_OV___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OV___S 27 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OVD___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OVD___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OV___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OV___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OVD___M 0x0003C000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OVD___S 14 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OV___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OV___S 13 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OVD___M 0x00001E00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OVD___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OV___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OV___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OVD___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OVD___S 4 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4___M 0x1B07FFF0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OVERRIDE_4___S 4 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0 (0x005EA0A8) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0___POR 0x1D186008 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_FORCE_EN_2P5_CURRENT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_TIA_FB_LOWER_IR_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_TIA_FB_LOWER_IC_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_TIA_FB_TOP_IR_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_TIA_FB_TOP_IC_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_VREF_SET___POR 0x8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__FE_R50_ADJ_HG___POR 0x30 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__FE_R50_ADJ_LG___POR 0x30 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_BW_SEL___POR 0x8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_FORCE_EN_2P5_CURRENT___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_FORCE_EN_2P5_CURRENT___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_TIA_FB_LOWER_IR_EN___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_TIA_FB_LOWER_IR_EN___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_TIA_FB_LOWER_IC_EN___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_TIA_FB_LOWER_IC_EN___S 27 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_TIA_FB_TOP_IR_EN___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_TIA_FB_TOP_IR_EN___S 26 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_TIA_FB_TOP_IC_EN___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_TIA_FB_TOP_IC_EN___S 25 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_VREF_SET___M 0x01E00000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_VREF_SET___S 21 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__FE_R50_ADJ_HG___M 0x001F8000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__FE_R50_ADJ_HG___S 15 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__FE_R50_ADJ_LG___M 0x00007E00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__FE_R50_ADJ_LG___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_BW_SEL___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0__D_BE_BW_SEL___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0___M 0x9FFFFE0F +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_1 (0x005EA0AC) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_1___POR 0x00000840 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_1__D_BE_ATB_MUX_SEL___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_1__D_BE_S2DOFFSET_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_1__D_BE_VREF_DEC_SEL___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_1__D_BE_ATB_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_1__D_BE_ATB_MUX_SEL___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_1__D_BE_ATB_MUX_SEL___S 10 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_1__D_BE_S2DOFFSET_SEL___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_1__D_BE_S2DOFFSET_SEL___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_1__D_BE_VREF_DEC_SEL___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_1__D_BE_VREF_DEC_SEL___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_1__D_BE_ATB_SEL___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_1__D_BE_ATB_SEL___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_1___M 0x00000DFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_1___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0 (0x005EA0B0) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0___POR 0x036E36DC +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_ATB_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASN_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASP_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_IDAC_CTRL___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_IC_LPF_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_REFGEN_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_IC_VCMOUTGEN_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_TIA_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_VDAC_CTRL___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_ATB_CTRL___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_ATB_CTRL___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASN_CTRL___M 0x00E00000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASN_CTRL___S 21 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASP_CTRL___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASP_CTRL___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_IDAC_CTRL___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_IDAC_CTRL___S 15 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_IC_LPF_CTRL___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_IC_LPF_CTRL___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_REFGEN_CTRL___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_REFGEN_CTRL___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_IC_VCMOUTGEN_CTRL___M 0x000001C0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_IC_VCMOUTGEN_CTRL___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_TIA_CTRL___M 0x00000038 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_TIA_CTRL___S 3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_VDAC_CTRL___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0__D_BE_IC_VDAC_CTRL___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0___M 0x07FFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1 (0x005EA0B4) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1___POR 0x0001B6DA +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_IC_PDBUFFER_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IC_PDBUFFER_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_IC_SPARE_0_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_IC_SPARE_1_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IR_ATB_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IR_REFGEN_CTRL___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_IC_PDBUFFER_CTRL___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_IC_PDBUFFER_CTRL___S 15 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IC_PDBUFFER_CTRL___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IC_PDBUFFER_CTRL___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_IC_SPARE_0_CTRL___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_IC_SPARE_0_CTRL___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_IC_SPARE_1_CTRL___M 0x000001C0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_IC_SPARE_1_CTRL___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IR_ATB_CTRL___M 0x00000038 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IR_ATB_CTRL___S 3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IR_REFGEN_CTRL___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1__D_BE_IR_REFGEN_CTRL___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1___M 0x0003FFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_1___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2 (0x005EA0B8) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2___POR 0x0001B6DC +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_VCMOUTGEN_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_IR_SPARE_0_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_IR_SPARE_1_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_IC_TIA_FB_BIAS___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_OFFSET_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_TIA_FB_BIAS___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_VCMOUTGEN_CTRL___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_VCMOUTGEN_CTRL___S 15 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_IR_SPARE_0_CTRL___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_IR_SPARE_0_CTRL___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_IR_SPARE_1_CTRL___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_IR_SPARE_1_CTRL___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_IC_TIA_FB_BIAS___M 0x000001C0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_IC_TIA_FB_BIAS___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_OFFSET_CTRL___M 0x00000038 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_OFFSET_CTRL___S 3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_TIA_FB_BIAS___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2__D_BE_IR_TIA_FB_BIAS___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2___M 0x0003FFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_IC_IR_BIAS_CTRL_2___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2 (0x005EA0BC) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2___POR 0x68000104 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__D_VDET_VREF___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__D_VDET_ROUT_SEL___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__D_VDET_RFIN_DISCONNECT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__D_TPCDPD_SPARE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__D_BE_IR_SQR_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__TPC_SQR_IC_N_CTRL_HG___POR 0x02 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__TPC_SQR_IC_N_CTRL_LG___POR 0x02 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__D_VDET_VREF___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__D_VDET_VREF___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__D_VDET_ROUT_SEL___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__D_VDET_ROUT_SEL___S 25 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__D_VDET_RFIN_DISCONNECT___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__D_VDET_RFIN_DISCONNECT___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__D_TPCDPD_SPARE___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__D_TPCDPD_SPARE___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__D_BE_IR_SQR_CTRL___M 0x0000E000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__D_BE_IR_SQR_CTRL___S 13 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__TPC_SQR_IC_N_CTRL_HG___M 0x00001F80 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__TPC_SQR_IC_N_CTRL_HG___S 7 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__TPC_SQR_IC_N_CTRL_LG___M 0x0000007E +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2__TPC_SQR_IC_N_CTRL_LG___S 1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_2___S 1 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3 (0x005EA0C0) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3___POR 0x000C5000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__TPC_SQR_IC_P_CTRL_HG___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__TPC_SQR_IC_P_CTRL_LG___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__D_WL_DPD_GC___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__D_WL_DPD_IBIAS_INV___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__D_WL_DPD_IBIAS_GM___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__D_WL_DPD_RES_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__WL_DPD_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__WL_DPD_CALSHIFT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__TPC_SQR_IC_P_CTRL_HG___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__TPC_SQR_IC_P_CTRL_HG___S 26 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__TPC_SQR_IC_P_CTRL_LG___M 0x03F00000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__TPC_SQR_IC_P_CTRL_LG___S 20 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__D_WL_DPD_GC___M 0x000E0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__D_WL_DPD_GC___S 17 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__D_WL_DPD_IBIAS_INV___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__D_WL_DPD_IBIAS_INV___S 13 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__D_WL_DPD_IBIAS_GM___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__D_WL_DPD_IBIAS_GM___S 10 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__D_WL_DPD_RES_CTRL___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__D_WL_DPD_RES_CTRL___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__WL_DPD_EN_OVS___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__WL_DPD_EN_OVS___S 7 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__WL_DPD_CALSHIFT_OVS___M 0x00000060 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3__WL_DPD_CALSHIFT_OVS___S 5 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3___M 0xFFFE7FE0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_3___S 5 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_4 (0x005EA0C4) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_4___POR 0x00000492 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_HG___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_LG___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_HG___POR 0x12 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_LG___POR 0x12 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_HG___M 0x00FC0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_HG___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_LG___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_LG___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_HG___M 0x00000FC0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_HG___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_LG___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_LG___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_4___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_AC_4___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OV_5 (0x005EA0C8) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OV_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OV_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OV_5__TPC_BE_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OV_5__VDET_VREF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OV_5__TPC_BE_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OV_5__TPC_BE_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OV_5__VDET_VREF_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OV_5__VDET_VREF_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OV_5___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_OV_5___S 28 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST (0x005EA0CC) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST__RBIST_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST__RBIST_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST__RBIST_OV___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST___S 31 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST_OV (0x005EA0D0) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST_OV___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST_OV___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST_OV__RBIST_CLPC_PKT_TYPE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST_OV__RBIST_TPC_PDET_GAIN_IDX_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST_OV__RBIST_TPC_ATTEN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST_OV__RBIST_CLPC_PKT_TYPE_OVD___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST_OV__RBIST_CLPC_PKT_TYPE_OVD___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST_OV__RBIST_TPC_PDET_GAIN_IDX_OVD___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST_OV__RBIST_TPC_PDET_GAIN_IDX_OVD___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST_OV__RBIST_TPC_ATTEN_OVD___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST_OV__RBIST_TPC_ATTEN_OVD___S 4 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST_OV___M 0x000003F0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_RBIST_OV___S 4 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0 (0x005EA100) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0___POR 0x1B000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_BIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_POL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_SETT___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_SMPL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_REF___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_BIN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_BIN___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_POL___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_POL___S 30 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_SETT___M 0x38000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_SETT___S 27 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_SMPL___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_SMPL___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_EN___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_EN___S 23 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_REF___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0__LDO_CAL_REF___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0___M 0xFF8001FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_LDO_CAL_0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_LDO_CAL_0 (0x005EA104) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_LDO_CAL_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_LDO_CAL_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_PDADC_DATA___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_RESULT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_PDADC_DATA___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_PDADC_DATA___S 23 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_DONE___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_DONE___S 4 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_RESULT___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_LDO_CAL_0__RO_LDO_CAL_RESULT___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_LDO_CAL_0___M 0xFF80001F +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_LDO_CAL_0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_MEASURE_0 (0x005EA140) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_MEASURE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_MEASURE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_MEASURE_0__SW_MEASURE_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_MEASURE_0__SW_MEASURE_TMR_SETTING___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_MEASURE_0__SW_MEASURE_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_MEASURE_0__SW_MEASURE_EN___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_MEASURE_0__SW_MEASURE_TMR_SETTING___M 0x60000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_MEASURE_0__SW_MEASURE_TMR_SETTING___S 29 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_MEASURE_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_MEASURE_0___S 29 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_MEASURE_0 (0x005EA144) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_MEASURE_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_MEASURE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_MEASURE_0__RO_SW_MEASURE_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_MEASURE_0__RO_SW_MEASURE_RESULT___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_MEASURE_0__RO_SW_MEASURE_DONE___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_MEASURE_0__RO_SW_MEASURE_DONE___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_MEASURE_0__RO_SW_MEASURE_RESULT___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_MEASURE_0__RO_SW_MEASURE_RESULT___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_MEASURE_0___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_MEASURE_0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_AVG_0 (0x005EA148) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_AVG_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_AVG_0___POR 0x08000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_AVG_0__SW_AVG_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_AVG_0__SW_AVG_CFG___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_AVG_0__SW_AVG_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_AVG_0__SW_AVG_EN___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_AVG_0__SW_AVG_CFG___M 0x78000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_AVG_0__SW_AVG_CFG___S 27 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_AVG_0___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_SW_AVG_0___S 27 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_AVG_0 (0x005EA14C) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_AVG_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_AVG_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_AVG_0__RO_SW_AVG_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_AVG_0__RO_SW_AVG_RESULT___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_AVG_0__RO_SW_AVG_DONE___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_AVG_0__RO_SW_AVG_DONE___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_AVG_0__RO_SW_AVG_RESULT___M 0x7FC00000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_AVG_0__RO_SW_AVG_RESULT___S 22 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_AVG_0___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_SW_AVG_0___S 22 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1 (0x005EA180) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1___POR 0x073D11C0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PDADC_STROBE_INV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PWR_MEAS_TRIG_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PDACC_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__ATB_MEAS_DUR___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__THERM_MEAS_DUR___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__VOLT_MEAS_DUR___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PD_ACC_WINDOW_CCK___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PD_ACC_WINDOW_OFDM___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PD_DC_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PD_DC_WIN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PD_DC_START___POR 0xC0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PDADC_STROBE_INV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PDADC_STROBE_INV___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS___S 30 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET___S 29 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PWR_MEAS_TRIG_SW___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PWR_MEAS_TRIG_SW___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PDACC_MODE___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PDACC_MODE___S 27 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__ATB_MEAS_DUR___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__ATB_MEAS_DUR___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__THERM_MEAS_DUR___M 0x00E00000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__THERM_MEAS_DUR___S 21 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__VOLT_MEAS_DUR___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__VOLT_MEAS_DUR___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PD_ACC_WINDOW_CCK___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PD_ACC_WINDOW_CCK___S 15 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PD_ACC_WINDOW_OFDM___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PD_ACC_WINDOW_OFDM___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PD_DC_SEL___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PD_DC_SEL___S 11 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PD_DC_WIN___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PD_DC_WIN___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PD_DC_START___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1__PD_DC_START___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_1___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_2 (0x005EA184) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_2___POR 0x00900090 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_2__CLPC_START_OFDM___POR 0x0090 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_2__CLPC_START_CCK___POR 0x0090 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_2__CLPC_START_OFDM___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_2__CLPC_START_OFDM___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_2__CLPC_START_CCK___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_2__CLPC_START_CCK___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_2___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_3_STAT_B0 (0x005EA188) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_3_STAT_B0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_3_STAT_B0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_4_CNT_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_3_CNT_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_2_CNT_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_1_CNT_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_4_CNT_0___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_4_CNT_0___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_3_CNT_0___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_3_CNT_0___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_2_CNT_0___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_2_CNT_0___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_1_CNT_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_1_CNT_0___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_3_STAT_B0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_3_STAT_B0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4 (0x005EA18C) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4___POR 0x22685349 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__OLPC_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__FULL_PKT_PWR_ACC_SYM_CNT___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__FULL_PKT_PWR_MEAS_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_PWR_INIT_DUR___POR 0x4D +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_DC_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_ACC_DC_WIN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_DC_INIT_DUR___POR 0x4D +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_ACC_WIN_CCK___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_ACC_WIN_OFDM___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__OLPC_MODE___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__OLPC_MODE___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__FULL_PKT_PWR_ACC_SYM_CNT___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__FULL_PKT_PWR_ACC_SYM_CNT___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__FULL_PKT_PWR_MEAS_EN___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__FULL_PKT_PWR_MEAS_EN___S 27 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_PWR_INIT_DUR___M 0x07F80000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_PWR_INIT_DUR___S 19 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_DC_SEL___M 0x00060000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_DC_SEL___S 17 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_ACC_DC_WIN___M 0x0001C000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_ACC_DC_WIN___S 14 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_DC_INIT_DUR___M 0x00003FC0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_DC_INIT_DUR___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_ACC_WIN_CCK___M 0x00000038 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_ACC_WIN_CCK___S 3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_ACC_WIN_OFDM___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4__PSYM_ACC_WIN_OFDM___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_4___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_5 (0x005EA190) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_5___POR 0x004D4D4D +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_5__FULL_PKT_PWR_INIT_DUR___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_5__ATB_INI_DUR___POR 0x4D +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_5__THERM_INI_DUR___POR 0x4D +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_5__VOLT_INI_DUR___POR 0x4D +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_5__FULL_PKT_PWR_INIT_DUR___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_5__FULL_PKT_PWR_INIT_DUR___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_5__ATB_INI_DUR___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_5__ATB_INI_DUR___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_5__THERM_INI_DUR___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_5__THERM_INI_DUR___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_5__VOLT_INI_DUR___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_5__VOLT_INI_DUR___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_5___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_5___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6 (0x005EA194) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6___POR 0x079E79E7 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__PDADC_STROBE_DLY_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__FULL_PKT_PWR_VALID_THR___POR 0x07 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__ATB_MEAS_DUR_MULTIPLIER___POR 0x27 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__THERM_MEAS_DUR_MULTIPLIER___POR 0x27 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__VOLT_MEAS_DUR_MULTIPLIER___POR 0x27 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__PD_DC_WIN_MULTIPLIER___POR 0x27 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__PDADC_STROBE_DLY_SEL___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__PDADC_STROBE_DLY_SEL___S 30 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__FULL_PKT_PWR_VALID_THR___M 0x3F000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__FULL_PKT_PWR_VALID_THR___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__ATB_MEAS_DUR_MULTIPLIER___M 0x00FC0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__ATB_MEAS_DUR_MULTIPLIER___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__THERM_MEAS_DUR_MULTIPLIER___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__THERM_MEAS_DUR_MULTIPLIER___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__VOLT_MEAS_DUR_MULTIPLIER___M 0x00000FC0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__VOLT_MEAS_DUR_MULTIPLIER___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__PD_DC_WIN_MULTIPLIER___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6__PD_DC_WIN_MULTIPLIER___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_6___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7 (0x005EA198) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7___POR 0x27C27C27 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7__PSYM_ACC_DC_WIN_MULTIPLIER___POR 0x27 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7__PSYM_ACC_WIN_CCK_MULTIPLIER___POR 0x30 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7__PSYM_ACC_WIN_OFDM_MULTIPLIER___POR 0x27 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7__PD_ACC_WINDOW_CCK_MULTIPLIER___POR 0x30 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7__PD_ACC_WINDOW_OFDM_MULTIPLIER___POR 0x27 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7__PSYM_ACC_DC_WIN_MULTIPLIER___M 0x3F000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7__PSYM_ACC_DC_WIN_MULTIPLIER___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7__PSYM_ACC_WIN_CCK_MULTIPLIER___M 0x00FC0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7__PSYM_ACC_WIN_CCK_MULTIPLIER___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7__PSYM_ACC_WIN_OFDM_MULTIPLIER___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7__PSYM_ACC_WIN_OFDM_MULTIPLIER___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7__PD_ACC_WINDOW_CCK_MULTIPLIER___M 0x00000FC0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7__PD_ACC_WINDOW_CCK_MULTIPLIER___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7__PD_ACC_WINDOW_OFDM_MULTIPLIER___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7__PD_ACC_WINDOW_OFDM_MULTIPLIER___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7___M 0x3FFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_7___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_8_B0 (0x005EA19C) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_8_B0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_8_B0___POR 0x00008399 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_8_B0__PDADC_BIAS___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_8_B0__INIT_ATB_SETTING_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_8_B0__INIT_VOLT_SETTING_0___POR 0x83 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_8_B0__INIT_THERM_SETTING_0___POR 0x99 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_8_B0__PDADC_BIAS___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_8_B0__PDADC_BIAS___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_8_B0__INIT_ATB_SETTING_0___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_8_B0__INIT_ATB_SETTING_0___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_8_B0__INIT_VOLT_SETTING_0___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_8_B0__INIT_VOLT_SETTING_0___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_8_B0__INIT_THERM_SETTING_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_8_B0__INIT_THERM_SETTING_0___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_8_B0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_8_B0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_9 (0x005EA1A0) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_9___POR 0x000001FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_9__PDADC_CLIP_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_9__PDADC_CLIP_THRES___POR 0x1FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_9__PDADC_CLIP_EN___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_9__PDADC_CLIP_EN___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_9__PDADC_CLIP_THRES___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_9__PDADC_CLIP_THRES___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_9___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_9___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_10_B0 (0x005EA1A4) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_10_B0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_10_B0___POR 0x01010000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_10_B0__THERM_RESOLUTION_OFFSET___POR 0x80 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_10_B0__THERM_ADC_SCALED_GAIN_0___POR 0x100 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_10_B0__THERM_ADC_OFFSET_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_10_B0__THERM_RESOLUTION_OFFSET___M 0x01FE0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_10_B0__THERM_RESOLUTION_OFFSET___S 17 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_10_B0__THERM_ADC_SCALED_GAIN_0___M 0x0001FF00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_10_B0__THERM_ADC_SCALED_GAIN_0___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_10_B0__THERM_ADC_OFFSET_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_10_B0__THERM_ADC_OFFSET_0___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_10_B0___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_10_B0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_11_STAT_B0 (0x005EA1A8) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_11_STAT_B0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_11_STAT_B0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_ATB_VALUE_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_VOLT_VALUE_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_THERM_VALUE_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_ATB_VALUE_0___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_ATB_VALUE_0___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_VOLT_VALUE_0___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_VOLT_VALUE_0___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_THERM_VALUE_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_11_STAT_B0__RO_LATEST_THERM_VALUE_0___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_11_STAT_B0___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_11_STAT_B0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_12_STAT_B0 (0x005EA1AC) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_12_STAT_B0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_12_STAT_B0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_12_STAT_B0__RO_FULL_PKT_AVG_OUT_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_12_STAT_B0__RO_LATEST_DC_VALUE_0___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_12_STAT_B0__RO_PDACC_AVG_OUT_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_12_STAT_B0__RO_FULL_PKT_AVG_OUT_0___M 0x01FE0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_12_STAT_B0__RO_FULL_PKT_AVG_OUT_0___S 17 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_12_STAT_B0__RO_LATEST_DC_VALUE_0___M 0x0001FF00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_12_STAT_B0__RO_LATEST_DC_VALUE_0___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_12_STAT_B0__RO_PDACC_AVG_OUT_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_12_STAT_B0__RO_PDACC_AVG_OUT_0___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_12_STAT_B0___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_12_STAT_B0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_13 (0x005EA1B0) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_13___POR 0x00000001 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_13__TEMP_MEAS_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_13__TPCRB_DELAY___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_13__TEMP_MEAS_SEL___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_13__TEMP_MEAS_SEL___S 3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_13__TPCRB_DELAY___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_13__TPCRB_DELAY___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_13___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_TPC_FB_13___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14 (0x005EA1B4) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_GNT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_CS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_FB_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_VALID___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_PKT_PWR_MEAS_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_PKT_PWR_MEAS_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_ATB_MEAS_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_THERM_MEAS_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_VOLT_MEAS_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_FB_ABORT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_ACC_NXT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_FB_CS___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_GNT___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_GNT___S 19 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_REQ___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_REQ___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_CS___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_TPC_CTRL_CS___S 15 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_FB_ON___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_FB_ON___S 14 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_VALID___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_VALID___S 13 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_EN___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_EN___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_PKT_PWR_MEAS_DONE___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_PKT_PWR_MEAS_DONE___S 11 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_PKT_PWR_MEAS_ON___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_PKT_PWR_MEAS_ON___S 10 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_ATB_MEAS_ON___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_ATB_MEAS_ON___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_THERM_MEAS_ON___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_THERM_MEAS_ON___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_VOLT_MEAS_ON___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_VOLT_MEAS_ON___S 7 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_FB_ABORT___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_FB_ABORT___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_ACC_NXT___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_ACC_NXT___S 5 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_FB_CS___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14__RO_FB_CS___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH0_RO_TPC_FB_14___S 0 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_MSIP_ID_REG (0x005EA400) +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_MSIP_ID_REG___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_MSIP_ID_REG___POR 0x10000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_MSIP_ID_REG__MSIP_ID_MAJOR___POR 0x1 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_MSIP_ID_REG__MSIP_ID_MINOR___POR 0x000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_MSIP_ID_REG__MSIP_ID_STEP___POR 0x0000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_MSIP_ID_REG__MSIP_ID_MAJOR___M 0xF0000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_MSIP_ID_REG__MSIP_ID_MAJOR___S 28 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_MSIP_ID_REG__MSIP_ID_MINOR___M 0x0FFF0000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_MSIP_ID_REG__MSIP_ID_MINOR___S 16 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_MSIP_ID_REG__MSIP_ID_STEP___M 0x0000FFFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_MSIP_ID_REG__MSIP_ID_STEP___S 0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_MSIP_ID_REG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_MSIP_ID_REG___S 0 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TEST_REG_0 (0x005EA404) +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TEST_REG_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TEST_REG_0___POR 0xDAC1DAC0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TEST_REG_0__TEST_RO___POR 0xDAC1DAC0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TEST_REG_0__TEST_RO___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TEST_REG_0__TEST_RO___S 0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TEST_REG_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TEST_REG_0___S 0 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TEST_REG_1 (0x005EA408) +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TEST_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TEST_REG_1___POR 0x1234ABCD +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TEST_REG_1__TEST_RW___POR 0x1234ABCD +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TEST_REG_1__TEST_RW___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TEST_REG_1__TEST_RW___S 0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TEST_REG_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TEST_REG_1___S 0 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_GLOBAL (0x005EA40C) +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_GLOBAL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_GLOBAL___POR 0x00000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_GLOBAL__RBIST_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_GLOBAL__ATE_WFM_START___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_GLOBAL__RBIST_TX_SW_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_GLOBAL__RBIST_SEL___M 0x00000004 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_GLOBAL__RBIST_SEL___S 2 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_GLOBAL__ATE_WFM_START___M 0x00000002 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_GLOBAL__ATE_WFM_START___S 1 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_GLOBAL__RBIST_TX_SW_RESET___M 0x00000001 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_GLOBAL__RBIST_TX_SW_RESET___S 0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_GLOBAL___M 0x00000007 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_GLOBAL___S 0 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_OUT_SCALING (0x005EA410) +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_OUT_SCALING___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_OUT_SCALING___POR 0x00000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_OUT_SCALING__ATE_TONEGEN_SCALING_ENABLE___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_OUT_SCALING__ATE_TONEGEN_SCALING_I___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_OUT_SCALING__ATE_TONEGEN_SCALING_Q___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_OUT_SCALING__ATE_TONEGEN_SCALING_ENABLE___M 0x00000100 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_OUT_SCALING__ATE_TONEGEN_SCALING_ENABLE___S 8 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_OUT_SCALING__ATE_TONEGEN_SCALING_I___M 0x000000F0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_OUT_SCALING__ATE_TONEGEN_SCALING_I___S 4 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_OUT_SCALING__ATE_TONEGEN_SCALING_Q___M 0x0000000F +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_OUT_SCALING__ATE_TONEGEN_SCALING_Q___S 0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_OUT_SCALING___M 0x000001FF +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_OUT_SCALING___S 0 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_DC_OFFSET (0x005EA414) +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_DC_OFFSET___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_DC_OFFSET___POR 0x00000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_DC_OFFSET__ATE_TONEGEN_DC_ENABLE___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_DC_OFFSET__ATE_TONEGEN_DC_I___POR 0x000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_DC_OFFSET__ATE_TONEGEN_DC_Q___POR 0x000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_DC_OFFSET__ATE_TONEGEN_DC_ENABLE___M 0x01000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_DC_OFFSET__ATE_TONEGEN_DC_ENABLE___S 24 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_DC_OFFSET__ATE_TONEGEN_DC_I___M 0x00FFF000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_DC_OFFSET__ATE_TONEGEN_DC_I___S 12 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_DC_OFFSET__ATE_TONEGEN_DC_Q___M 0x00000FFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_DC_OFFSET__ATE_TONEGEN_DC_Q___S 0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_DC_OFFSET___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_DC_OFFSET___S 0 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0 (0x005EA418) +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0___POR 0x00000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0__ATE_TONEGEN_TONE0_ENABLE___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0__ATE_TONEGEN_TONE0_FREQ___POR 0x00 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_6DB___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_1DB___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0__ATE_TONEGEN_TONE0_DELAY___POR 0x00 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0__ATE_TONEGEN_TONE0_ENABLE___M 0x01000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0__ATE_TONEGEN_TONE0_ENABLE___S 24 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0__ATE_TONEGEN_TONE0_FREQ___M 0x00FF0000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0__ATE_TONEGEN_TONE0_FREQ___S 16 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_6DB___M 0x0000F000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_6DB___S 12 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_1DB___M 0x00000700 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_1DB___S 8 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0__ATE_TONEGEN_TONE0_DELAY___M 0x000000FF +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0__ATE_TONEGEN_TONE0_DELAY___S 0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0___M 0x01FFF7FF +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN0___S 0 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1 (0x005EA41C) +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1___POR 0x00000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1__ATE_TONEGEN_TONE1_ENABLE___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1__ATE_TONEGEN_TONE1_FREQ___POR 0x00 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_6DB___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_1DB___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1__ATE_TONEGEN_TONE1_DELAY___POR 0x00 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1__ATE_TONEGEN_TONE1_ENABLE___M 0x01000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1__ATE_TONEGEN_TONE1_ENABLE___S 24 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1__ATE_TONEGEN_TONE1_FREQ___M 0x00FF0000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1__ATE_TONEGEN_TONE1_FREQ___S 16 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_6DB___M 0x0000F000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_6DB___S 12 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_1DB___M 0x00000700 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_1DB___S 8 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1__ATE_TONEGEN_TONE1_DELAY___M 0x000000FF +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1__ATE_TONEGEN_TONE1_DELAY___S 0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1___M 0x01FFF7FF +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_TONEGEN1___S 0 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0 (0x005EA420) +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0___POR 0x00000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_ENABLE___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_FREQ___POR 0x00 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_6DB___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_1DB___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_DELAY___POR 0x00 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_ENABLE___M 0x01000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_ENABLE___S 24 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_FREQ___M 0x00FF0000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_FREQ___S 16 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_6DB___M 0x0000F000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_6DB___S 12 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_1DB___M 0x00000700 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_1DB___S 8 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_DELAY___M 0x000000FF +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_DELAY___S 0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0___M 0x01FFF7FF +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LFTONEGEN0___S 0 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_I (0x005EA424) +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_I___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_I___POR 0x00000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_ENABLE_I___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_DWELL_I___POR 0x000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_STEP_I___POR 0x00 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_INIT_I___POR 0x000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_ENABLE_I___M 0x10000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_ENABLE_I___S 28 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_DWELL_I___M 0x0FFC0000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_DWELL_I___S 18 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_STEP_I___M 0x0003F000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_STEP_I___S 12 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_INIT_I___M 0x00000FFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_INIT_I___S 0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_I___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_I___S 0 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_Q (0x005EA428) +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_Q___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_Q___POR 0x00000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_ENABLE_Q___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_DWELL_Q___POR 0x000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_STEP_Q___POR 0x00 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_INIT_Q___POR 0x000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_ENABLE_Q___M 0x10000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_ENABLE_Q___S 28 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_DWELL_Q___M 0x0FFC0000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_DWELL_Q___S 18 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_STEP_Q___M 0x0003F000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_STEP_Q___S 12 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_INIT_Q___M 0x00000FFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_INIT_Q___S 0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_Q___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_LINEAR_RAMP_Q___S 0 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_MAG (0x005EA42C) +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_MAG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_MAG___POR 0x00000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_I___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_Q___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_I___POR 0x000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_Q___POR 0x000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_I___M 0x00800000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_I___S 23 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_Q___M 0x00400000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_Q___S 22 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_I___M 0x003FF800 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_I___S 11 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_Q___M 0x000007FF +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_Q___S 0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_MAG___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_MAG___S 0 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_SEED_I (0x005EA430) +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_SEED_I___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_SEED_I___POR 0x00000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_SEED_I__ATE_TONEGEN_PRBS_SEED_I___POR 0x00000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_SEED_I__ATE_TONEGEN_PRBS_SEED_I___M 0x7FFFFFFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_SEED_I__ATE_TONEGEN_PRBS_SEED_I___S 0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_SEED_I___M 0x7FFFFFFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_SEED_I___S 0 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_SEED_Q (0x005EA434) +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_SEED_Q___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_SEED_Q___POR 0x00000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_SEED_Q__ATE_TONEGEN_PRBS_SEED_Q___POR 0x00000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_SEED_Q__ATE_TONEGEN_PRBS_SEED_Q___M 0x7FFFFFFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_SEED_Q__ATE_TONEGEN_PRBS_SEED_Q___S 0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_SEED_Q___M 0x7FFFFFFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PRBS_SEED_Q___S 0 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM (0x005EA438) +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM___POR 0x000003FF +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_ENABLE___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_SCALING_EN___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_MAGNITUDE___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_START___POR 0x000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_STOP___POR 0x3FF +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_ENABLE___M 0x20000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_ENABLE___S 29 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_SCALING_EN___M 0x10000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_SCALING_EN___S 28 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_MAGNITUDE___M 0x0F000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_MAGNITUDE___S 24 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_START___M 0x000FFC00 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_START___S 10 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_STOP___M 0x000003FF +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_STOP___S 0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM___M 0x3F0FFFFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_PREAMBLE_ROM___S 0 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_DIG_TEST_OUT_SEL (0x005EA43C) +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_DIG_TEST_OUT_SEL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_DIG_TEST_OUT_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_DIG_TEST_OUT_SEL__DIG_TEST_OUT_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_DIG_TEST_OUT_SEL__DIG_TEST_OUT_SEL___M 0x07800000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_DIG_TEST_OUT_SEL__DIG_TEST_OUT_SEL___S 23 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_DIG_TEST_OUT_SEL___M 0x07800000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_DIG_TEST_OUT_SEL___S 23 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0 (0x005EA440) +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ENABLE___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_MAIN_TAB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_0___POR 0x000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_1___POR 0x000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_2___POR 0x000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ENABLE___M 0x20000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ENABLE___S 29 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_MAIN_TAB_SEL___M 0x18000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_MAIN_TAB_SEL___S 27 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_0___M 0x07FC0000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_0___S 18 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_1___M 0x0003FE00 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_1___S 9 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_2___M 0x000001FF +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_2___S 0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0___M 0x3FFFFFFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_0___S 0 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_1 (0x005EA444) +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_0___POR 0x000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_1___POR 0x000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_2___POR 0x000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_0___M 0x07FC0000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_0___S 18 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_1___M 0x0003FE00 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_1___S 9 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_2___M 0x000001FF +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_2___S 0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_1___M 0x07FFFFFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH0_TX_FILTER_CTRL_1___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_CH0_MSIP_ID_REG (0x005EA580) +#define PHYA_IRON2G_RFA_WL_DAC_CH0_MSIP_ID_REG___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_DAC_CH0_MSIP_ID_REG___POR 0x10000000 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_MSIP_ID_REG__MSIP_ID_MAJOR___POR 0x1 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_MSIP_ID_REG__MSIP_ID_MINOR___POR 0x000 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_MSIP_ID_REG__MSIP_ID_STEP___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_MSIP_ID_REG__MSIP_ID_MAJOR___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_MSIP_ID_REG__MSIP_ID_MAJOR___S 28 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_MSIP_ID_REG__MSIP_ID_MINOR___M 0x0FFF0000 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_MSIP_ID_REG__MSIP_ID_MINOR___S 16 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_MSIP_ID_REG__MSIP_ID_STEP___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_DAC_CH0_MSIP_ID_REG__MSIP_ID_STEP___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_MSIP_ID_REG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_DAC_CH0_MSIP_ID_REG___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_CH0_CHIP_ID_REG (0x005EA584) +#define PHYA_IRON2G_RFA_WL_DAC_CH0_CHIP_ID_REG___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_DAC_CH0_CHIP_ID_REG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_CHIP_ID_REG__CHIP_ID___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_CHIP_ID_REG__CHIP_ID___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_CH0_CHIP_ID_REG__CHIP_ID___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_CHIP_ID_REG___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_CH0_CHIP_ID_REG___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_CH0_TEST_REG_0 (0x005EA588) +#define PHYA_IRON2G_RFA_WL_DAC_CH0_TEST_REG_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_DAC_CH0_TEST_REG_0___POR 0xDAC1DAC0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_TEST_REG_0__TEST_RO___POR 0xDAC1DAC0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_TEST_REG_0__TEST_RO___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_DAC_CH0_TEST_REG_0__TEST_RO___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_TEST_REG_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_DAC_CH0_TEST_REG_0___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_CH0_TEST_REG_1 (0x005EA58C) +#define PHYA_IRON2G_RFA_WL_DAC_CH0_TEST_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_CH0_TEST_REG_1___POR 0x1234ABCD +#define PHYA_IRON2G_RFA_WL_DAC_CH0_TEST_REG_1__TEST_RW___POR 0x1234ABCD +#define PHYA_IRON2G_RFA_WL_DAC_CH0_TEST_REG_1__TEST_RW___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_DAC_CH0_TEST_REG_1__TEST_RW___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_TEST_REG_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_DAC_CH0_TEST_REG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0 (0x005EA590) +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0___POR 0x000C5000 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__RBIST_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__D_DAC_AMPLITUDE_GAIN_1___POR 0xC +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__D_DAC_AMPLITUDE_GAIN_0___POR 0x5 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__DAC_SEL_PHYA_PHYB___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__DAC_ATE_TMUX_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__CAL_WR_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__DAC_SW_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__DAC_SIGPATH_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__DAC_CLK_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__RBIST_OV___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__RBIST_OV___S 20 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__D_DAC_AMPLITUDE_GAIN_1___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__D_DAC_AMPLITUDE_GAIN_1___S 16 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__D_DAC_AMPLITUDE_GAIN_0___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__D_DAC_AMPLITUDE_GAIN_0___S 12 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__DAC_SEL_PHYA_PHYB___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__DAC_SEL_PHYA_PHYB___S 10 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__DAC_ATE_TMUX_EN___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__DAC_ATE_TMUX_EN___S 9 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__CAL_WR_EN___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__CAL_WR_EN___S 7 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__DAC_SW_RESET___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__DAC_SW_RESET___S 6 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__DAC_SIGPATH_EN_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__DAC_SIGPATH_EN_OVS___S 4 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__DAC_CLK_EN_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0__DAC_CLK_EN_OVS___S 2 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0___M 0x001FF7FC +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_0___S 2 + +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1 (0x005EA594) +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1___POR 0x00000010 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_WARMUP_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__C_DAC_CLKDIVRST_B_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_Q_FORCEFULLSCALE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_I_FORCEFULLSCALE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_DISABLE_R2RBUFFER___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_CAL_DISABLE_OFFSETDAC___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_ATEST_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_Q_FORCEMIDSCALE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_I_FORCEMIDSCALE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_PWRDN_N___POR 0x1 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_DISABLE_SINK___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_WARMUP_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_WARMUP_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_BIAS_EN_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_BIAS_EN_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__C_DAC_CLKDIVRST_B_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__C_DAC_CLKDIVRST_B_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_Q_FORCEFULLSCALE___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_Q_FORCEFULLSCALE___S 19 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_I_FORCEFULLSCALE___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_I_FORCEFULLSCALE___S 18 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_DISABLE_R2RBUFFER___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_DISABLE_R2RBUFFER___S 17 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_CAL_DISABLE_OFFSETDAC___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_CAL_DISABLE_OFFSETDAC___S 16 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_ATEST_SEL___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_ATEST_SEL___S 8 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_Q_FORCEMIDSCALE___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_Q_FORCEMIDSCALE___S 6 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_I_FORCEMIDSCALE___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_I_FORCEMIDSCALE___S 5 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_PWRDN_N___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_PWRDN_N___S 4 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_DISABLE_SINK___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1__D_DAC_DISABLE_SINK___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1___M 0x03FFFF71 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_CTRL_1___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG1 (0x005EA598) +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG1__DAC_REG2_SPARE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG1__DAC_REG2_SPARE___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG1__DAC_REG2_SPARE___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG1___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG1___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2 (0x005EA59C) +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2___POR 0x00000030 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2__DAC_CFG_1_SPARE2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2__D_DAC_VREF___POR 0x3 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2__DAC_CFG_1_SPARE1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2__DISABLE_FIR___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2__DAC_CFG_1_SPARE0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2__DAC_CFG_1_SPARE2___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2__DAC_CFG_1_SPARE2___S 8 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2__D_DAC_VREF___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2__D_DAC_VREF___S 4 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2__DAC_CFG_1_SPARE1___M 0x0000000C +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2__DAC_CFG_1_SPARE1___S 2 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2__DISABLE_FIR___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2__DISABLE_FIR___S 1 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2__DAC_CFG_1_SPARE0___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2__DAC_CFG_1_SPARE0___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG2___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG3 (0x005EA5A0) +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG3__DAC_REG3_SPARE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG3__DAC_REG3_SPARE___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG3__DAC_REG3_SPARE___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG3___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG3___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG4 (0x005EA5A4) +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG4__DAC_REG4_SPARE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG4__DAC_REG4_SPARE___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG4__DAC_REG4_SPARE___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG4___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG4___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG5 (0x005EA5A8) +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG5__DAC_REG5_SPARE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG5__DAC_REG5_SPARE___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG5__DAC_REG5_SPARE___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG5___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG5___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG6 (0x005EA5AC) +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG6__DAC_REG6_SPARE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG6__DAC_REG6_SPARE___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG6__DAC_REG6_SPARE___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG6___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG6___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG7 (0x005EA5B0) +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG7__DAC_REG7_SPARE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG7__DAC_REG7_SPARE___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG7__DAC_REG7_SPARE___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG7___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG7___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG8 (0x005EA5B4) +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG8___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG8__CAL_SM_WR___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG8__CAL_SM_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG8__CAL_SM_WR___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG8__CAL_SM_WR___S 1 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG8__CAL_SM_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG8__CAL_SM_EN___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG8___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG8___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG9 (0x005EA5B8) +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG9___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG9___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG9__CAL_SAT_ERR___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG9__CAL_BUSY___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG9__CAL_SAT_ERR___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG9__CAL_SAT_ERR___S 1 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG9__CAL_BUSY___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG9__CAL_BUSY___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG9___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_DAC_CH0_DAC_REG9___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I00 (0x005EA5C0) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I00___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I00___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I00__DAC_CAL_S_I00___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I00__DAC_CAL_S_I00___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I00__DAC_CAL_S_I00___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I00___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I00___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I01 (0x005EA5C4) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I01___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I01___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I01__DAC_CAL_S_I01___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I01__DAC_CAL_S_I01___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I01__DAC_CAL_S_I01___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I01___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I01___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I02 (0x005EA5C8) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I02___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I02___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I02__DAC_CAL_S_I02___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I02__DAC_CAL_S_I02___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I02__DAC_CAL_S_I02___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I02___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I02___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I03 (0x005EA5CC) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I03___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I03___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I03__DAC_CAL_S_I03___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I03__DAC_CAL_S_I03___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I03__DAC_CAL_S_I03___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I03___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I03___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I04 (0x005EA5D0) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I04___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I04___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I04__DAC_CAL_S_I04___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I04__DAC_CAL_S_I04___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I04__DAC_CAL_S_I04___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I04___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I04___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I05 (0x005EA5D4) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I05___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I05___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I05__DAC_CAL_S_I05___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I05__DAC_CAL_S_I05___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I05__DAC_CAL_S_I05___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I05___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I05___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I06 (0x005EA5D8) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I06___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I06___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I06__DAC_CAL_S_I06___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I06__DAC_CAL_S_I06___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I06__DAC_CAL_S_I06___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I06___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I06___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I07 (0x005EA5DC) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I07___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I07___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I07__DAC_CAL_S_I07___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I07__DAC_CAL_S_I07___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I07__DAC_CAL_S_I07___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I07___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I07___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I08 (0x005EA5E0) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I08___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I08___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I08__DAC_CAL_S_I08___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I08__DAC_CAL_S_I08___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I08__DAC_CAL_S_I08___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I08___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I08___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I09 (0x005EA5E4) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I09___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I09___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I09__DAC_CAL_S_I09___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I09__DAC_CAL_S_I09___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I09__DAC_CAL_S_I09___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I09___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I09___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I10 (0x005EA5E8) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I10___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I10__DAC_CAL_S_I10___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I10__DAC_CAL_S_I10___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I10__DAC_CAL_S_I10___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I10___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I10___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I11 (0x005EA5EC) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I11___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I11__DAC_CAL_S_I11___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I11__DAC_CAL_S_I11___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I11__DAC_CAL_S_I11___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I11___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I11___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I12 (0x005EA5F0) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I12___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I12__DAC_CAL_S_I12___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I12__DAC_CAL_S_I12___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I12__DAC_CAL_S_I12___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I12___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I12___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I13 (0x005EA5F4) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I13___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I13__DAC_CAL_S_I13___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I13__DAC_CAL_S_I13___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I13__DAC_CAL_S_I13___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I13___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I13___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I14 (0x005EA5F8) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I14___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I14__DAC_CAL_S_I14___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I14__DAC_CAL_S_I14___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I14__DAC_CAL_S_I14___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I14___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I14___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I15 (0x005EA5FC) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I15___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I15__DAC_CAL_S_I15___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I15__DAC_CAL_S_I15___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I15__DAC_CAL_S_I15___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I15___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I15___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I16 (0x005EA600) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I16___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I16__DAC_CAL_S_I16___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I16__DAC_CAL_S_I16___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I16__DAC_CAL_S_I16___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I16___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I16___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I17 (0x005EA604) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I17___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I17__DAC_CAL_S_I17___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I17__DAC_CAL_S_I17___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I17__DAC_CAL_S_I17___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I17___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I17___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I18 (0x005EA608) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I18___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I18__DAC_CAL_S_I18___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I18__DAC_CAL_S_I18___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I18__DAC_CAL_S_I18___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I18___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I18___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I19 (0x005EA60C) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I19___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I19__DAC_CAL_S_I19___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I19__DAC_CAL_S_I19___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I19__DAC_CAL_S_I19___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I19___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I19___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I20 (0x005EA610) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I20___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I20__DAC_CAL_S_I20___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I20__DAC_CAL_S_I20___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I20__DAC_CAL_S_I20___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I20___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I20___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I21 (0x005EA614) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I21___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I21__DAC_CAL_S_I21___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I21__DAC_CAL_S_I21___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I21__DAC_CAL_S_I21___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I21___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I21___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I22 (0x005EA618) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I22___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I22__DAC_CAL_S_I22___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I22__DAC_CAL_S_I22___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I22__DAC_CAL_S_I22___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I22___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I22___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I23 (0x005EA61C) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I23___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I23__DAC_CAL_S_I23___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I23__DAC_CAL_S_I23___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I23__DAC_CAL_S_I23___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I23___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I23___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I24 (0x005EA620) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I24___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I24__DAC_CAL_S_I24___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I24__DAC_CAL_S_I24___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I24__DAC_CAL_S_I24___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I24___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I24___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I25 (0x005EA624) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I25___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I25__DAC_CAL_S_I25___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I25__DAC_CAL_S_I25___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I25__DAC_CAL_S_I25___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I25___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I25___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I26 (0x005EA628) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I26___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I26__DAC_CAL_S_I26___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I26__DAC_CAL_S_I26___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I26__DAC_CAL_S_I26___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I26___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I26___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I27 (0x005EA62C) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I27___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I27__DAC_CAL_S_I27___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I27__DAC_CAL_S_I27___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I27__DAC_CAL_S_I27___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I27___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I27___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I28 (0x005EA630) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I28___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I28__DAC_CAL_S_I28___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I28__DAC_CAL_S_I28___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I28__DAC_CAL_S_I28___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I28___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I28___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I29 (0x005EA634) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I29___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I29__DAC_CAL_S_I29___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I29__DAC_CAL_S_I29___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I29__DAC_CAL_S_I29___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I29___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I29___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I30 (0x005EA638) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I30___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I30__DAC_CAL_S_I30___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I30__DAC_CAL_S_I30___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I30__DAC_CAL_S_I30___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I30___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I30___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I31 (0x005EA63C) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I31___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I31__DAC_CAL_S_I31___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I31__DAC_CAL_S_I31___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I31__DAC_CAL_S_I31___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I31___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_I31___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q00 (0x005EA640) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q00___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q00___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q00__DAC_CAL_S_Q00___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q00__DAC_CAL_S_Q00___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q00__DAC_CAL_S_Q00___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q00___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q00___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q01 (0x005EA644) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q01___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q01___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q01__DAC_CAL_S_Q01___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q01__DAC_CAL_S_Q01___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q01__DAC_CAL_S_Q01___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q01___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q01___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q02 (0x005EA648) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q02___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q02___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q02__DAC_CAL_S_Q02___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q02__DAC_CAL_S_Q02___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q02__DAC_CAL_S_Q02___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q02___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q02___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q03 (0x005EA64C) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q03___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q03___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q03__DAC_CAL_S_Q03___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q03__DAC_CAL_S_Q03___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q03__DAC_CAL_S_Q03___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q03___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q03___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q04 (0x005EA650) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q04___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q04___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q04__DAC_CAL_S_Q04___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q04__DAC_CAL_S_Q04___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q04__DAC_CAL_S_Q04___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q04___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q04___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q05 (0x005EA654) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q05___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q05___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q05__DAC_CAL_S_Q05___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q05__DAC_CAL_S_Q05___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q05__DAC_CAL_S_Q05___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q05___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q05___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q06 (0x005EA658) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q06___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q06___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q06__DAC_CAL_S_Q06___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q06__DAC_CAL_S_Q06___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q06__DAC_CAL_S_Q06___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q06___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q06___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q07 (0x005EA65C) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q07___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q07___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q07__DAC_CAL_S_Q07___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q07__DAC_CAL_S_Q07___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q07__DAC_CAL_S_Q07___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q07___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q07___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q08 (0x005EA660) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q08___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q08___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q08__DAC_CAL_S_Q08___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q08__DAC_CAL_S_Q08___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q08__DAC_CAL_S_Q08___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q08___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q08___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q09 (0x005EA664) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q09___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q09___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q09__DAC_CAL_S_Q09___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q09__DAC_CAL_S_Q09___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q09__DAC_CAL_S_Q09___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q09___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q09___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q10 (0x005EA668) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q10___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q10__DAC_CAL_S_Q10___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q10__DAC_CAL_S_Q10___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q10__DAC_CAL_S_Q10___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q10___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q10___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q11 (0x005EA66C) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q11___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q11__DAC_CAL_S_Q11___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q11__DAC_CAL_S_Q11___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q11__DAC_CAL_S_Q11___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q11___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q11___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q12 (0x005EA670) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q12___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q12__DAC_CAL_S_Q12___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q12__DAC_CAL_S_Q12___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q12__DAC_CAL_S_Q12___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q12___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q12___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q13 (0x005EA674) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q13___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q13__DAC_CAL_S_Q13___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q13__DAC_CAL_S_Q13___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q13__DAC_CAL_S_Q13___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q13___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q13___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q14 (0x005EA678) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q14___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q14__DAC_CAL_S_Q14___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q14__DAC_CAL_S_Q14___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q14__DAC_CAL_S_Q14___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q14___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q14___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q15 (0x005EA67C) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q15___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q15__DAC_CAL_S_Q15___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q15__DAC_CAL_S_Q15___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q15__DAC_CAL_S_Q15___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q15___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q15___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q16 (0x005EA680) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q16___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q16__DAC_CAL_S_Q16___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q16__DAC_CAL_S_Q16___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q16__DAC_CAL_S_Q16___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q16___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q16___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q17 (0x005EA684) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q17___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q17__DAC_CAL_S_Q17___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q17__DAC_CAL_S_Q17___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q17__DAC_CAL_S_Q17___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q17___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q17___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q18 (0x005EA688) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q18___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q18__DAC_CAL_S_Q18___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q18__DAC_CAL_S_Q18___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q18__DAC_CAL_S_Q18___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q18___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q18___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q19 (0x005EA68C) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q19___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q19__DAC_CAL_S_Q19___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q19__DAC_CAL_S_Q19___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q19__DAC_CAL_S_Q19___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q19___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q19___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q20 (0x005EA690) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q20___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q20__DAC_CAL_S_Q20___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q20__DAC_CAL_S_Q20___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q20__DAC_CAL_S_Q20___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q20___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q20___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q21 (0x005EA694) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q21___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q21__DAC_CAL_S_Q21___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q21__DAC_CAL_S_Q21___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q21__DAC_CAL_S_Q21___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q21___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q21___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q22 (0x005EA698) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q22___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q22__DAC_CAL_S_Q22___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q22__DAC_CAL_S_Q22___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q22__DAC_CAL_S_Q22___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q22___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q22___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q23 (0x005EA69C) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q23___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q23__DAC_CAL_S_Q23___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q23__DAC_CAL_S_Q23___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q23__DAC_CAL_S_Q23___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q23___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q23___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q24 (0x005EA6A0) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q24___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q24__DAC_CAL_S_Q24___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q24__DAC_CAL_S_Q24___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q24__DAC_CAL_S_Q24___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q24___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q24___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q25 (0x005EA6A4) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q25___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q25__DAC_CAL_S_Q25___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q25__DAC_CAL_S_Q25___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q25__DAC_CAL_S_Q25___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q25___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q25___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q26 (0x005EA6A8) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q26___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q26__DAC_CAL_S_Q26___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q26__DAC_CAL_S_Q26___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q26__DAC_CAL_S_Q26___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q26___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q26___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q27 (0x005EA6AC) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q27___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q27__DAC_CAL_S_Q27___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q27__DAC_CAL_S_Q27___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q27__DAC_CAL_S_Q27___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q27___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q27___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q28 (0x005EA6B0) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q28___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q28__DAC_CAL_S_Q28___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q28__DAC_CAL_S_Q28___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q28__DAC_CAL_S_Q28___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q28___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q28___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q29 (0x005EA6B4) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q29___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q29__DAC_CAL_S_Q29___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q29__DAC_CAL_S_Q29___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q29__DAC_CAL_S_Q29___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q29___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q29___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q30 (0x005EA6B8) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q30___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q30__DAC_CAL_S_Q30___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q30__DAC_CAL_S_Q30___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q30__DAC_CAL_S_Q30___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q30___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q30___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q31 (0x005EA6BC) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q31___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q31__DAC_CAL_S_Q31___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q31__DAC_CAL_S_Q31___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q31__DAC_CAL_S_Q31___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q31___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH0_DAC_CAL_REG_Q31___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI0 (0x005EA6C0) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI0__DAC_CAL_BIN_I0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI0__DAC_CAL_BIN_I0___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI0__DAC_CAL_BIN_I0___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI0___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI0___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI1 (0x005EA6C4) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI1__DAC_CAL_BIN_I1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI1__DAC_CAL_BIN_I1___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI1__DAC_CAL_BIN_I1___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI1___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI1___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI2 (0x005EA6C8) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI2__DAC_CAL_BIN_I2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI2__DAC_CAL_BIN_I2___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI2__DAC_CAL_BIN_I2___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI2___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI2___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI3 (0x005EA6CC) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI3__DAC_CAL_BIN_I3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI3__DAC_CAL_BIN_I3___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI3__DAC_CAL_BIN_I3___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI3___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI3___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI4 (0x005EA6D0) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI4__DAC_CAL_BIN_I4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI4__DAC_CAL_BIN_I4___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI4__DAC_CAL_BIN_I4___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI4___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI4___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI5 (0x005EA6D4) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI5__DAC_CAL_BIN_I5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI5__DAC_CAL_BIN_I5___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI5__DAC_CAL_BIN_I5___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI5___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI5___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI6 (0x005EA6D8) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI6__DAC_CAL_BIN_I6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI6__DAC_CAL_BIN_I6___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI6__DAC_CAL_BIN_I6___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI6___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI6___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI7 (0x005EA6DC) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI7__DAC_CAL_BIN_I7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI7__DAC_CAL_BIN_I7___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI7__DAC_CAL_BIN_I7___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI7___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI7___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI8 (0x005EA6E0) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI8___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI8__DAC_CAL_BIN_I8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI8__DAC_CAL_BIN_I8___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI8__DAC_CAL_BIN_I8___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI8___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGI8___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ0 (0x005EA6E4) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ0__DAC_CAL_BIN_Q0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ0__DAC_CAL_BIN_Q0___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ0__DAC_CAL_BIN_Q0___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ0___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ0___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ1 (0x005EA6E8) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ1__DAC_CAL_BIN_Q1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ1__DAC_CAL_BIN_Q1___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ1__DAC_CAL_BIN_Q1___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ1___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ1___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ2 (0x005EA6EC) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ2__DAC_CAL_BIN_Q2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ2__DAC_CAL_BIN_Q2___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ2__DAC_CAL_BIN_Q2___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ2___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ2___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ3 (0x005EA6F0) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ3__DAC_CAL_BIN_Q3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ3__DAC_CAL_BIN_Q3___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ3__DAC_CAL_BIN_Q3___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ3___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ3___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ4 (0x005EA6F4) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ4__DAC_CAL_BIN_Q4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ4__DAC_CAL_BIN_Q4___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ4__DAC_CAL_BIN_Q4___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ4___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ4___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ5 (0x005EA6F8) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ5__DAC_CAL_BIN_Q5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ5__DAC_CAL_BIN_Q5___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ5__DAC_CAL_BIN_Q5___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ5___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ5___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ6 (0x005EA6FC) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ6__DAC_CAL_BIN_Q6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ6__DAC_CAL_BIN_Q6___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ6__DAC_CAL_BIN_Q6___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ6___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ6___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ7 (0x005EA700) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ7__DAC_CAL_BIN_Q7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ7__DAC_CAL_BIN_Q7___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ7__DAC_CAL_BIN_Q7___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ7___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ7___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ8 (0x005EA704) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ8___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ8__DAC_CAL_BIN_Q8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ8__DAC_CAL_BIN_Q8___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ8__DAC_CAL_BIN_Q8___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ8___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_BIN_REGQ8___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1 (0x005EA708) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__DAC_DTEST_PLL_TEST_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__DAC_DTEST_DBG_OUT_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__D_DAC_COMP_OFFSET_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__D_DAC_COMP_OFFSET_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__CAL_SA_OUTPUTS_INVERT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__COMP_IN_INVERT_OFFSET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__DBG_CAL_CLK___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__DBG_CAL_CLK_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__COMP_IN_INVERT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__CAL_N_SAMPLES___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__CAL_STROBE_RESAMP_TMR___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__COMP_SETT_TMR___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__CAL_STROBE_TMR___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__CAL_FSM_FREEZE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__DAC_DTEST_PLL_TEST_SEL___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__DAC_DTEST_PLL_TEST_SEL___S 26 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__DAC_DTEST_DBG_OUT_SEL___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__DAC_DTEST_DBG_OUT_SEL___S 23 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__D_DAC_COMP_OFFSET_OV___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__D_DAC_COMP_OFFSET_OV___S 22 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__D_DAC_COMP_OFFSET_OVD___M 0x003F0000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__D_DAC_COMP_OFFSET_OVD___S 16 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__CAL_SA_OUTPUTS_INVERT___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__CAL_SA_OUTPUTS_INVERT___S 15 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__COMP_IN_INVERT_OFFSET___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__COMP_IN_INVERT_OFFSET___S 14 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__DBG_CAL_CLK___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__DBG_CAL_CLK___S 13 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__DBG_CAL_CLK_EN___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__DBG_CAL_CLK_EN___S 12 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__COMP_IN_INVERT___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__COMP_IN_INVERT___S 11 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__CAL_N_SAMPLES___M 0x00000600 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__CAL_N_SAMPLES___S 9 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__CAL_STROBE_RESAMP_TMR___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__CAL_STROBE_RESAMP_TMR___S 7 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__COMP_SETT_TMR___M 0x00000060 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__COMP_SETT_TMR___S 5 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__CAL_STROBE_TMR___M 0x00000018 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__CAL_STROBE_TMR___S 3 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__CAL_FSM_FREEZE___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1__CAL_FSM_FREEZE___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG1___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2 (0x005EA70C) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DAC_CAL_REG2_SPARE1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_BIN_DATA___POR 0x000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_MSB_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_DATA_CARRY___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DAC_CAL_REG2_SPARE0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_MSB_VAL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_OFFSET___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_COMP_STROBE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_MODE_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_MODE_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_FSM_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DAC_CAL_REG2_SPARE1___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DAC_CAL_REG2_SPARE1___S 31 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_BIN_DATA___M 0x7FC00000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_BIN_DATA___S 22 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_MSB_SEL___M 0x003E0000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_MSB_SEL___S 17 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_DATA_CARRY___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_DATA_CARRY___S 16 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DAC_CAL_REG2_SPARE0___M 0x0000F800 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DAC_CAL_REG2_SPARE0___S 11 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_MSB_VAL___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_MSB_VAL___S 10 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_OFFSET___M 0x000003F0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_OFFSET___S 4 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_COMP_STROBE___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_COMP_STROBE___S 3 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_MODE_Q___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_MODE_Q___S 2 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_MODE_I___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_MODE_I___S 1 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_FSM_BYPASS___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2__DBG_CAL_FSM_BYPASS___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG2___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG3 (0x005EA710) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG3___POR 0x000001FF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG3__DAC_CAL_REG3___POR 0x000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG3__D_DAC_CAL_BIN_SEL___POR 0x1FF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG3__DAC_CAL_REG3___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG3__DAC_CAL_REG3___S 9 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG3__D_DAC_CAL_BIN_SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG3__D_DAC_CAL_BIN_SEL___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG3___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG4 (0x005EA714) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG4__DAC_CAL_REG4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG4__DAC_CAL_REG4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG4__DAC_CAL_REG4___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_REG4___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1 (0x005EA718) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1__RO_CAL_SI_ACCUM___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1__DAC_CAL_SM_STATUS1_SPARE___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1__RO_CAL_Q_FROZE_AFTER_CI___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_SI___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_CI___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1__RO_CAL_SI_ACCUM___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1__RO_CAL_SI_ACCUM___S 16 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1__DAC_CAL_SM_STATUS1_SPARE___M 0x0000FFF8 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1__DAC_CAL_SM_STATUS1_SPARE___S 3 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1__RO_CAL_Q_FROZE_AFTER_CI___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1__RO_CAL_Q_FROZE_AFTER_CI___S 2 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_SI___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_SI___S 1 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_CI___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_CI___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG1___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG2 (0x005EA71C) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG2__RO_MAX_CLIP_Q___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG2__RO_MIN_CLIP_Q___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG2__RO_MAX_CLIP_I___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG2__RO_MIN_CLIP_I___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG2__RO_MAX_CLIP_Q___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG2__RO_MAX_CLIP_Q___S 24 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG2__RO_MIN_CLIP_Q___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG2__RO_MIN_CLIP_Q___S 16 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG2__RO_MAX_CLIP_I___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG2__RO_MAX_CLIP_I___S 8 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG2__RO_MIN_CLIP_I___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG2__RO_MIN_CLIP_I___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG2___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3 (0x005EA720) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CAL_BIN_DATA___POR 0x000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CAL_MSB_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CALDATA_CARRY___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_COMP_OFFSET___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CAL_COMP_STROBE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CAL_MODE_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CAL_MODE_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_COMPOUT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE1___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE1___S 31 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CAL_BIN_DATA___M 0x7FC00000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CAL_BIN_DATA___S 22 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CAL_MSB_SEL___M 0x003E0000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CAL_MSB_SEL___S 17 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CALDATA_CARRY___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CALDATA_CARRY___S 16 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE0___M 0x0000FC00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE0___S 10 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_COMP_OFFSET___M 0x000003F0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_COMP_OFFSET___S 4 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CAL_COMP_STROBE___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CAL_COMP_STROBE___S 3 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CAL_MODE_Q___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CAL_MODE_Q___S 2 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CAL_MODE_I___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_CAL_MODE_I___S 1 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_COMPOUT___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3__RO_COMPOUT___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG3___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG4 (0x005EA724) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG4___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG4__DAC_CAL_SM_STATUS4_SPARE___POR 0x000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG4__RO_CAL_DC_VAL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG4__DAC_CAL_SM_STATUS4_SPARE___M 0xFFFFFF00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG4__DAC_CAL_SM_STATUS4_SPARE___S 8 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG4__RO_CAL_DC_VAL___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG4__RO_CAL_DC_VAL___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_STATUS_REG4___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_CTRL (0x005EA728) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_CTRL___POR 0x00000004 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_CTRL__DAC_DISABLE_CORRECTION___POR 0x1 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_CTRL__DAC_CAL_RANGE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_CTRL__DAC_DISABLE_CORRECTION___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_CTRL__DAC_DISABLE_CORRECTION___S 2 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_CTRL__DAC_CAL_RANGE___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_CTRL__DAC_CAL_RANGE___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_CTRL___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_SM_CTRL___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG (0x005EA72C) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG__MSB_SEL_OFFSET___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG__CAL_MSB_VAL_OV_REG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG__DAC_EN_D_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG__C_CLKDAC1X_INVERT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG__D_DAC_SPARE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG__MSB_SEL_OFFSET___M 0x0001F000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG__MSB_SEL_OFFSET___S 12 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG__CAL_MSB_VAL_OV_REG___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG__CAL_MSB_VAL_OV_REG___S 11 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG__DAC_EN_D_SEL___M 0x00000600 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG__DAC_EN_D_SEL___S 9 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG__C_CLKDAC1X_INVERT___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG__C_CLKDAC1X_INVERT___S 8 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG__D_DAC_SPARE___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG__D_DAC_SPARE___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG___M 0x0001FFFF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_MISC_REG___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_RO_SPARE_REG (0x005EA730) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_RO_SPARE_REG___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_RO_SPARE_REG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_RO_SPARE_REG__D_DAC_RO_SPARE___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_RO_SPARE_REG__D_DAC_RO_SPARE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_RO_SPARE_REG__D_DAC_RO_SPARE___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_RO_SPARE_REG___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH0_DAC_RO_SPARE_REG___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0 (0x005EA734) +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKDAC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKDAC_FREQ_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKDAC_FREQ_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKDAC_CAL_FREQ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLK60_FREQ0P5X___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLK60_PHASE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKDAC_PHASE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKDAC_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKDAC_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKDAC_FREQ_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKDAC_FREQ_OV___S 23 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKDAC_FREQ_OVD___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKDAC_FREQ_OVD___S 20 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKDAC_CAL_FREQ___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKDAC_CAL_FREQ___S 18 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLK60_FREQ0P5X___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLK60_FREQ0P5X___S 17 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLK60_PHASE___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLK60_PHASE___S 12 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKDAC_PHASE___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKDAC_PHASE___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0___M 0x30B67007 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH0_BB_CLKGEN_0___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_MSIP_ID_REG (0x005EA740) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_MSIP_ID_REG___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_MSIP_ID_REG___POR 0x10000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_MSIP_ID_REG__RO_MSIP_ID_MAJOR___POR 0x1 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_MSIP_ID_REG__RO_MSIP_ID_MINOR___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_MSIP_ID_REG__RO_MSIP_ID_STEP___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_MSIP_ID_REG__RO_MSIP_ID_MAJOR___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_MSIP_ID_REG__RO_MSIP_ID_MAJOR___S 28 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_MSIP_ID_REG__RO_MSIP_ID_MINOR___M 0x0FFF0000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_MSIP_ID_REG__RO_MSIP_ID_MINOR___S 16 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_MSIP_ID_REG__RO_MSIP_ID_STEP___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_MSIP_ID_REG__RO_MSIP_ID_STEP___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_MSIP_ID_REG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_MSIP_ID_REG___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_TEST_REG_0 (0x005EA744) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_TEST_REG_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_TEST_REG_0___POR 0xADC1ADC0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_TEST_REG_0__RO_TEST___POR 0xADC1ADC0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_TEST_REG_0__RO_TEST___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_TEST_REG_0__RO_TEST___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_TEST_REG_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_TEST_REG_0___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_TEST_REG_1 (0x005EA748) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_TEST_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH0_TEST_REG_1___POR 0x1234ABCD +#define PHYA_IRON2G_RFA_WL_ADC_CH0_TEST_REG_1__TEST_RW___POR 0x1234ABCD +#define PHYA_IRON2G_RFA_WL_ADC_CH0_TEST_REG_1__TEST_RW___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_TEST_REG_1__TEST_RW___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_TEST_REG_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_TEST_REG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL (0x005EA74C) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL___POR 0x00003000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__D_ADC_EN_Q_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__D_ADC_EN_I_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__ADC_DATA_GPIO_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__RBIST_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__SEL_NATIVE_CHAIN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__D_ADC_PWRDN_N___POR 0x1 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__PHY_ADC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__ADC_EN_Q_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__ADC_EN_I_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__CAL_START___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__OUTDISBL_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__OUTDISBL_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__D_TI_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__D_DIGITAL_CLAMP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__D_ADC_EN_Q_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__D_ADC_EN_Q_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__D_ADC_EN_I_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__D_ADC_EN_I_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__ADC_DATA_GPIO_SEL___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__ADC_DATA_GPIO_SEL___S 16 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__RBIST_OV___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__RBIST_OV___S 14 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__SEL_NATIVE_CHAIN___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__SEL_NATIVE_CHAIN___S 13 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__D_ADC_PWRDN_N___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__D_ADC_PWRDN_N___S 12 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__PHY_ADC_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__PHY_ADC_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__ADC_EN_Q_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__ADC_EN_Q_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__ADC_EN_I_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__ADC_EN_I_OVS___S 6 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__CAL_START___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__CAL_START___S 5 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__OUTDISBL_Q___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__OUTDISBL_Q___S 4 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__OUTDISBL_I___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__OUTDISBL_I___S 3 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__D_TI_MODE___M 0x00000006 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__D_TI_MODE___S 1 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__D_DIGITAL_CLAMP___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL__D_DIGITAL_CLAMP___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL___M 0x003F7FFF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CTRL___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG (0x005EA750) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__D_ADC_TI_MODE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__D_ADC_TI_MODE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__USE_ODD_CORE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__ADC_ATE_DEC_RATIO___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__ADC_ATE_RX_PATH_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__ADC_ATE_TMUX_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__ADC_SW_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__D_ADC_TI_MODE_OV___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__D_ADC_TI_MODE_OV___S 10 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__D_ADC_TI_MODE_OVD___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__D_ADC_TI_MODE_OVD___S 8 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__USE_ODD_CORE___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__USE_ODD_CORE___S 7 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__ADC_ATE_DEC_RATIO___M 0x00000070 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__ADC_ATE_DEC_RATIO___S 4 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__ADC_ATE_RX_PATH_EN___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__ADC_ATE_RX_PATH_EN___S 3 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__ADC_ATE_TMUX_EN___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__ADC_ATE_TMUX_EN___S 2 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__ADC_SW_RESET___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG__ADC_SW_RESET___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG___M 0x000007FD +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CONFIG___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_STATUS (0x005EA754) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_STATUS___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_STATUS___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_STATUS__RO_CAL_ERROR___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_STATUS__RO_CAL_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_STATUS__RO_CAL_ERROR___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_STATUS__RO_CAL_ERROR___S 1 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_STATUS__RO_CAL_DONE___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_STATUS__RO_CAL_DONE___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_STATUS___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_STATUS___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0 (0x005EA758) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_IN_CLAMP_DISABLE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_TP_ANA_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_DTEST_INVERT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_DTEST_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_DTEST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_ATEST_V_OR_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_ATEST_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_RED_ENB___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_RST_WIDTH_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_IN_CLAMP_DISABLE___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_IN_CLAMP_DISABLE___S 31 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_TP_ANA_EN___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_TP_ANA_EN___S 30 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_DTEST_INVERT___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_DTEST_INVERT___S 29 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_DTEST_SEL___M 0x1F800000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_DTEST_SEL___S 23 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_DTEST_EN___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_DTEST_EN___S 22 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_ATEST_V_OR_I___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_ATEST_V_OR_I___S 21 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_ATEST_SEL___M 0x001E0000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_ATEST_SEL___S 17 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_RED_ENB___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_RED_ENB___S 16 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_RST_WIDTH_SEL___M 0x0000FC00 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0__D_RST_WIDTH_SEL___S 10 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG0___S 10 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG1 (0x005EA75C) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG1__D_CMP_VCM_SEL_Q___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG1__D_CMP_VCM_SEL_I___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG1__D_TP_ANA_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG1__D_CMP_VCM_SEL_Q___M 0x03FE0000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG1__D_CMP_VCM_SEL_Q___S 17 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG1__D_CMP_VCM_SEL_I___M 0x00001FF0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG1__D_CMP_VCM_SEL_I___S 4 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG1__D_TP_ANA_SEL___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG1__D_TP_ANA_SEL___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG1___M 0x03FE1FF3 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG1___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG2 (0x005EA760) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG2__D_DTEST_DIV3_INVERT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG2__D_DTEST_DIV3_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG2__D_CLKGEN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG2__D_AAF_MISC___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG2__D_DTEST_DIV3_INVERT___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG2__D_DTEST_DIV3_INVERT___S 17 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG2__D_DTEST_DIV3_EN___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG2__D_DTEST_DIV3_EN___S 16 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG2__D_CLKGEN___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG2__D_CLKGEN___S 8 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG2__D_AAF_MISC___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG2__D_AAF_MISC___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG2___M 0x0003FF07 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG2___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG3 (0x005EA764) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG3__D_DBG___POR 0x00 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG3__D_SPARE___POR 0x000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG3__D_DBG___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG3__D_DBG___S 24 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG3__D_SPARE___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG3__D_SPARE___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_AC_REG3___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0 (0x005EA768) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0___POR 0x00003000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__TIGEC_FR_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_LSB_CAL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__SW_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__FR_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__REDC_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__SRST_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__D_OS_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__CAL_WR_EN___POR 0x3 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__D_BP_BYPASS_NC___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__CLK_EDGE_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__REDC_POSTP_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_TIGEC_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_SDM_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_CAL_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_TIGEC_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_SDM_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_CAL_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__CAL_ST_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__TIGEC_FR_SEL___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__TIGEC_FR_SEL___S 23 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_LSB_CAL___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_LSB_CAL___S 22 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__SW_SEL___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__SW_SEL___S 20 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__FR_SEL___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__FR_SEL___S 18 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__REDC_SEL___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__REDC_SEL___S 16 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__SRST_SEL___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__SRST_SEL___S 15 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__D_OS_SEL___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__D_OS_SEL___S 14 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__CAL_WR_EN___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__CAL_WR_EN___S 12 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__D_BP_BYPASS_NC___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__D_BP_BYPASS_NC___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__CLK_EDGE_SEL___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__CLK_EDGE_SEL___S 10 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__REDC_POSTP_SEL___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__REDC_POSTP_SEL___S 8 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_TIGEC_Q___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_TIGEC_Q___S 7 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_SDM_Q___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_SDM_Q___S 6 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_CAL_Q___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_CAL_Q___S 5 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_TIGEC_I___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_TIGEC_I___S 4 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_SDM_I___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_SDM_I___S 3 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_CAL_I___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__BYPASS_CAL_I___S 2 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__CAL_ST_SEL___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0__CAL_ST_SEL___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_CAL_REG_0___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG (0x005EA76C) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__CAL_ENGINE_CORE_ENABLE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TEST_ADC_STATE_EN_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TEST_ADC_STATE_EN_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TEST_PATTERN_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TEST_PATTERN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TI_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__CHANNEL_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__ENABLE_CAL_READ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TEST_PATTERN_IN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__DIN_DBG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__CLK_DBG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__CAL_HS_DBG_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__CAL_DBG_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__CAL_ENGINE_CORE_ENABLE___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__CAL_ENGINE_CORE_ENABLE___S 25 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TEST_ADC_STATE_EN_Q___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TEST_ADC_STATE_EN_Q___S 24 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TEST_ADC_STATE_EN_I___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TEST_ADC_STATE_EN_I___S 23 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TEST_PATTERN_EN___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TEST_PATTERN_EN___S 22 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TEST_PATTERN___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TEST_PATTERN___S 19 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TI_SEL___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TI_SEL___S 18 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__CHANNEL_SEL___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__CHANNEL_SEL___S 17 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__ENABLE_CAL_READ___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__ENABLE_CAL_READ___S 16 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TEST_PATTERN_IN___M 0x0000FFF0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__TEST_PATTERN_IN___S 4 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__DIN_DBG___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__DIN_DBG___S 3 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__CLK_DBG___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__CLK_DBG___S 2 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__CAL_HS_DBG_EN___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__CAL_HS_DBG_EN___S 1 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__CAL_DBG_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG__CAL_DBG_EN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG___M 0x0FFFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_DBG_REG___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_0 (0x005EA770) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_0___POR 0x02020410 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_0__W2_I_EVEN___POR 0x80 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_0__W1_I_EVEN___POR 0x40 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_0__W0P5LSB_I_EVEN___POR 0x20 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_0__W0P25LSB_I_EVEN___POR 0x10 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_0__W2_I_EVEN___M 0x03FC0000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_0__W2_I_EVEN___S 18 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_0__W1_I_EVEN___M 0x0003F800 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_0__W1_I_EVEN___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_0__W0P5LSB_I_EVEN___M 0x000007E0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_0__W0P5LSB_I_EVEN___S 5 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_0__W0P25LSB_I_EVEN___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_0__W0P25LSB_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_0___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_0___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_1 (0x005EA774) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_1___POR 0x10040100 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_1__WREDC_I_EVEN___POR 0x200 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_1__W4_I_EVEN___POR 0x200 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_1__W3_I_EVEN___POR 0x100 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_1__WREDC_I_EVEN___M 0x3FF80000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_1__WREDC_I_EVEN___S 19 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_1__W4_I_EVEN___M 0x0007FE00 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_1__W4_I_EVEN___S 9 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_1__W3_I_EVEN___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_1__W3_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_1___M 0x3FFFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_2 (0x005EA778) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_2___POR 0x00000200 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_2__WREDC_POSTP_I_EVEN___POR 0x200 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_2__WREDC_POSTP_I_EVEN___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_2__WREDC_POSTP_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_2___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_EVEN_LSB_WEIGHT_REG_2___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_0 (0x005EA77C) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_0___POR 0x02020410 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_0__W2_I_ODD___POR 0x80 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_0__W1_I_ODD___POR 0x40 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_0__W0P5LSB_I_ODD___POR 0x20 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_0__W0P25LSB_I_ODD___POR 0x10 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_0__W2_I_ODD___M 0x03FC0000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_0__W2_I_ODD___S 18 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_0__W1_I_ODD___M 0x0003F800 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_0__W1_I_ODD___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_0__W0P5LSB_I_ODD___M 0x000007E0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_0__W0P5LSB_I_ODD___S 5 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_0__W0P25LSB_I_ODD___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_0__W0P25LSB_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_0___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_0___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_1 (0x005EA780) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_1___POR 0x10040100 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_1__WREDC_I_ODD___POR 0x200 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_1__W4_I_ODD___POR 0x200 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_1__W3_I_ODD___POR 0x100 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_1__WREDC_I_ODD___M 0x3FF80000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_1__WREDC_I_ODD___S 19 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_1__W4_I_ODD___M 0x0007FE00 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_1__W4_I_ODD___S 9 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_1__W3_I_ODD___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_1__W3_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_1___M 0x3FFFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_2 (0x005EA784) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_2___POR 0x00000200 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_2__WREDC_POSTP_I_ODD___POR 0x200 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_2__WREDC_POSTP_I_ODD___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_2__WREDC_POSTP_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_2___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_I_ODD_LSB_WEIGHT_REG_2___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_0 (0x005EA788) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_0___POR 0x02020410 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W2_Q_EVEN___POR 0x80 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W1_Q_EVEN___POR 0x40 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W0P5LSB_Q_EVEN___POR 0x20 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W0P25LSB_Q_EVEN___POR 0x10 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W2_Q_EVEN___M 0x03FC0000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W2_Q_EVEN___S 18 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W1_Q_EVEN___M 0x0003F800 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W1_Q_EVEN___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W0P5LSB_Q_EVEN___M 0x000007E0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W0P5LSB_Q_EVEN___S 5 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W0P25LSB_Q_EVEN___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W0P25LSB_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_0___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_0___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_1 (0x005EA78C) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_1___POR 0x10040100 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_1__WREDC_Q_EVEN___POR 0x200 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_1__W4_Q_EVEN___POR 0x200 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_1__W3_Q_EVEN___POR 0x100 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_1__WREDC_Q_EVEN___M 0x3FF80000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_1__WREDC_Q_EVEN___S 19 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_1__W4_Q_EVEN___M 0x0007FE00 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_1__W4_Q_EVEN___S 9 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_1__W3_Q_EVEN___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_1__W3_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_1___M 0x3FFFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_2 (0x005EA790) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_2___POR 0x00000200 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_2__WREDC_POSTP_Q_EVEN___POR 0x200 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_2__WREDC_POSTP_Q_EVEN___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_2__WREDC_POSTP_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_2___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_EVEN_LSB_WEIGHT_REG_2___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_0 (0x005EA794) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_0___POR 0x02020410 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_0__W2_Q_ODD___POR 0x80 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_0__W1_Q_ODD___POR 0x40 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_0__W0P5LSB_Q_ODD___POR 0x20 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_0__W0P25LSB_Q_ODD___POR 0x10 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_0__W2_Q_ODD___M 0x03FC0000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_0__W2_Q_ODD___S 18 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_0__W1_Q_ODD___M 0x0003F800 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_0__W1_Q_ODD___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_0__W0P5LSB_Q_ODD___M 0x000007E0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_0__W0P5LSB_Q_ODD___S 5 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_0__W0P25LSB_Q_ODD___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_0__W0P25LSB_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_0___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_0___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_1 (0x005EA798) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_1___POR 0x10040100 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_1__WREDC_Q_ODD___POR 0x200 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_1__W4_Q_ODD___POR 0x200 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_1__W3_Q_ODD___POR 0x100 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_1__WREDC_Q_ODD___M 0x3FF80000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_1__WREDC_Q_ODD___S 19 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_1__W4_Q_ODD___M 0x0007FE00 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_1__W4_Q_ODD___S 9 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_1__W3_Q_ODD___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_1__W3_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_1___M 0x3FFFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_2 (0x005EA79C) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_2___POR 0x00000200 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_2__WREDC_POSTP_Q_ODD___POR 0x200 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_2__WREDC_POSTP_Q_ODD___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_2__WREDC_POSTP_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_2___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_Q_ODD_LSB_WEIGHT_REG_2___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0 (0x005EA7A0) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0___POR 0x00400001 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME___POR 0x00 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_FLIP_EVEN_ODD___POR 0x1 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_IGNORE_LIN_SEARCH___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_IGNORE_BIN_SEARCH___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_Q_ODD_DISABLE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_Q_EVEN_DISABLE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_I_ODD_DISABLE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_I_EVEN_DISABLE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_LIN_STEP_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_BIN_STEP_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME_SEL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_SETT_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_ST_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_RETIMED_CLK___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_IGNORE_FLAG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME___S 24 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_FLIP_EVEN_ODD___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_FLIP_EVEN_ODD___S 22 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_IGNORE_LIN_SEARCH___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_IGNORE_LIN_SEARCH___S 21 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_IGNORE_BIN_SEARCH___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_IGNORE_BIN_SEARCH___S 20 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_Q_ODD_DISABLE___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_Q_ODD_DISABLE___S 19 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_Q_EVEN_DISABLE___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_Q_EVEN_DISABLE___S 18 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_I_ODD_DISABLE___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_I_ODD_DISABLE___S 17 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_I_EVEN_DISABLE___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_I_EVEN_DISABLE___S 16 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_LIN_STEP_SEL___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_LIN_STEP_SEL___S 14 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_BIN_STEP_SEL___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_BIN_STEP_SEL___S 12 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME_SEL_OV___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME_SEL_OV___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME_SEL_OVD___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME_SEL_OVD___S 8 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_SETT_SEL___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_SETT_SEL___S 6 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_ST_SEL___M 0x00000030 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_ST_SEL___S 4 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_RETIMED_CLK___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_RETIMED_CLK___S 2 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_IGNORE_FLAG___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_IGNORE_FLAG___S 1 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0__VCM_TRACK_EN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0___M 0xFF7FFFF7 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_0___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_1 (0x005EA7A4) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_1__VCM_TRACK_Q_ODD_ADJ_PN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_1__VCM_TRACK_Q_EVEN_ADJ_PN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_1__VCM_TRACK_I_ODD_ADJ_PN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_1__VCM_TRACK_I_EVEN_ADJ_PN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_1__VCM_TRACK_Q_ODD_ADJ_PN___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_1__VCM_TRACK_Q_ODD_ADJ_PN___S 3 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_1__VCM_TRACK_Q_EVEN_ADJ_PN___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_1__VCM_TRACK_Q_EVEN_ADJ_PN___S 2 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_1__VCM_TRACK_I_ODD_ADJ_PN___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_1__VCM_TRACK_I_ODD_ADJ_PN___S 1 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_1__VCM_TRACK_I_EVEN_ADJ_PN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_1__VCM_TRACK_I_EVEN_ADJ_PN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_1___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_REG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0 (0x005EA7A8) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_FAIL_I_EVEN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PN_OVERFLOW_I_EVEN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_I_EVEN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PN_I_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PP_I_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_FAIL_I_EVEN___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_FAIL_I_EVEN___S 24 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PN_OVERFLOW_I_EVEN___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PN_OVERFLOW_I_EVEN___S 23 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_I_EVEN___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_I_EVEN___S 22 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PN_I_EVEN___M 0x003FF800 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PN_I_EVEN___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PP_I_EVEN___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PP_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_EVEN_REG_0___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_1 (0x005EA7AC) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_1___POR 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PP_PN_OVERRIDE_I_EVEN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PN_I_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PP_I_EVEN___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PP_PN_OVERRIDE_I_EVEN___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PP_PN_OVERRIDE_I_EVEN___S 22 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PN_I_EVEN___M 0x003FF800 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PN_I_EVEN___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PP_I_EVEN___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PP_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_1___M 0x007FFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_2 (0x005EA7B0) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_2___POR 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_2__VCM_TRACK_PN_I_EVEN_INIT___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_2__VCM_TRACK_PP_I_EVEN_INIT___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_2__VCM_TRACK_PN_I_EVEN_INIT___M 0x003FF800 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_2__VCM_TRACK_PN_I_EVEN_INIT___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_2__VCM_TRACK_PP_I_EVEN_INIT___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_2__VCM_TRACK_PP_I_EVEN_INIT___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_2___M 0x003FFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_EVEN_REG_2___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0 (0x005EA7B4) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_FAIL_I_ODD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PN_OVERFLOW_I_ODD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_I_ODD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PN_I_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PP_I_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_FAIL_I_ODD___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_FAIL_I_ODD___S 24 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PN_OVERFLOW_I_ODD___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PN_OVERFLOW_I_ODD___S 23 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_I_ODD___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_I_ODD___S 22 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PN_I_ODD___M 0x003FF800 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PN_I_ODD___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PP_I_ODD___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PP_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_I_ODD_REG_0___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_1 (0x005EA7B8) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_1___POR 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PP_PN_OVERRIDE_I_ODD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PN_I_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PP_I_ODD___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PP_PN_OVERRIDE_I_ODD___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PP_PN_OVERRIDE_I_ODD___S 22 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PN_I_ODD___M 0x003FF800 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PN_I_ODD___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PP_I_ODD___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PP_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_1___M 0x007FFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_2 (0x005EA7BC) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_2___POR 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_2__VCM_TRACK_PN_I_ODD_INIT___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_2__VCM_TRACK_PP_I_ODD_INIT___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_2__VCM_TRACK_PN_I_ODD_INIT___M 0x003FF800 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_2__VCM_TRACK_PN_I_ODD_INIT___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_2__VCM_TRACK_PP_I_ODD_INIT___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_2__VCM_TRACK_PP_I_ODD_INIT___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_2___M 0x003FFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_I_ODD_REG_2___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0 (0x005EA7C0) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_FAIL_Q_EVEN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PN_OVERFLOW_Q_EVEN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_Q_EVEN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PN_Q_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PP_Q_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_FAIL_Q_EVEN___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_FAIL_Q_EVEN___S 24 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PN_OVERFLOW_Q_EVEN___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PN_OVERFLOW_Q_EVEN___S 23 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_Q_EVEN___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_Q_EVEN___S 22 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PN_Q_EVEN___M 0x003FF800 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PN_Q_EVEN___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PP_Q_EVEN___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PP_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_EVEN_REG_0___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_1 (0x005EA7C4) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_1___POR 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PP_PN_OVERRIDE_Q_EVEN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PN_Q_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PP_Q_EVEN___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PP_PN_OVERRIDE_Q_EVEN___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PP_PN_OVERRIDE_Q_EVEN___S 22 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PN_Q_EVEN___M 0x003FF800 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PN_Q_EVEN___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PP_Q_EVEN___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PP_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_1___M 0x007FFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_2 (0x005EA7C8) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_2___POR 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_2__VCM_TRACK_PN_Q_EVEN_INIT___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_2__VCM_TRACK_PP_Q_EVEN_INIT___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_2__VCM_TRACK_PN_Q_EVEN_INIT___M 0x003FF800 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_2__VCM_TRACK_PN_Q_EVEN_INIT___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_2__VCM_TRACK_PP_Q_EVEN_INIT___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_2__VCM_TRACK_PP_Q_EVEN_INIT___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_2___M 0x003FFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_EVEN_REG_2___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0 (0x005EA7CC) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_FAIL_Q_ODD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PN_OVERFLOW_Q_ODD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_Q_ODD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PN_Q_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PP_Q_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_FAIL_Q_ODD___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_FAIL_Q_ODD___S 24 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PN_OVERFLOW_Q_ODD___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PN_OVERFLOW_Q_ODD___S 23 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_Q_ODD___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_Q_ODD___S 22 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PN_Q_ODD___M 0x003FF800 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PN_Q_ODD___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PP_Q_ODD___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PP_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_RO_ADC_VCM_TRACK_Q_ODD_REG_0___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_1 (0x005EA7D0) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_1___POR 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PP_PN_OVERRIDE_Q_ODD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PN_Q_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PP_Q_ODD___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PP_PN_OVERRIDE_Q_ODD___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PP_PN_OVERRIDE_Q_ODD___S 22 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PN_Q_ODD___M 0x003FF800 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PN_Q_ODD___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PP_Q_ODD___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PP_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_1___M 0x007FFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_2 (0x005EA7D4) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_2___POR 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_2__VCM_TRACK_PN_Q_ODD_INIT___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_2__VCM_TRACK_PP_Q_ODD_INIT___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_2__VCM_TRACK_PN_Q_ODD_INIT___M 0x003FF800 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_2__VCM_TRACK_PN_Q_ODD_INIT___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_2__VCM_TRACK_PP_Q_ODD_INIT___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_2__VCM_TRACK_PP_Q_ODD_INIT___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_2___M 0x003FFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH0_ADC_VCM_TRACK_Q_ODD_REG_2___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH0_PDADC_CTRL_REG (0x005EA7D8) +#define PHYA_IRON2G_RFA_WL_ADC_CH0_PDADC_CTRL_REG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH0_PDADC_CTRL_REG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_PDADC_CTRL_REG__PDADC_SEL_I_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_PDADC_CTRL_REG__PDADC_STROBE_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_PDADC_CTRL_REG__PDADC_SEL_I_Q___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_PDADC_CTRL_REG__PDADC_SEL_I_Q___S 3 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_PDADC_CTRL_REG__PDADC_STROBE_EN___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_PDADC_CTRL_REG__PDADC_STROBE_EN___S 2 +#define PHYA_IRON2G_RFA_WL_ADC_CH0_PDADC_CTRL_REG___M 0x0000000C +#define PHYA_IRON2G_RFA_WL_ADC_CH0_PDADC_CTRL_REG___S 2 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_1 (0x005EA800) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_1__WOS_C_I_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_1__WOS_C_I_EVEN___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_1__WOS_C_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_1___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_2 (0x005EA804) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_2__WOS_F_I_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_2__WOS_F_I_EVEN___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_2__WOS_F_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_2___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_2___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_3 (0x005EA808) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_3___POR 0x00000400 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_3__W5_I_EVEN___POR 0x400 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_3__W5_I_EVEN___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_3__W5_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_3___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_3___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_4 (0x005EA80C) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_4___POR 0x00000800 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_4__W6_I_EVEN___POR 0x800 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_4__W6_I_EVEN___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_4__W6_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_4___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_4___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_5 (0x005EA810) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_5___POR 0x00001000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_5__W7_I_EVEN___POR 0x1000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_5__W7_I_EVEN___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_5__W7_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_5___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_5___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_6 (0x005EA814) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_6___POR 0x00002000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_6__W8_I_EVEN___POR 0x2000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_6__W8_I_EVEN___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_6__W8_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_6___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_6___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_7 (0x005EA818) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_7___POR 0x00004000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_7__W9_I_EVEN___POR 0x4000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_7__W9_I_EVEN___M 0x00007FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_7__W9_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_7___M 0x00007FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH0_ADC_POST_PROC_I_EVEN_REG_7___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_1 (0x005EA840) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_1__WOS_C_I_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_1__WOS_C_I_ODD___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_1__WOS_C_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_1___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_2 (0x005EA844) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_2__WOS_F_I_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_2__WOS_F_I_ODD___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_2__WOS_F_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_2___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_2___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_3 (0x005EA848) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_3___POR 0x00000400 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_3__W5_I_ODD___POR 0x400 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_3__W5_I_ODD___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_3__W5_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_3___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_3___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_4 (0x005EA84C) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_4___POR 0x00000800 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_4__W6_I_ODD___POR 0x800 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_4__W6_I_ODD___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_4__W6_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_4___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_4___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_5 (0x005EA850) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_5___POR 0x00001000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_5__W7_I_ODD___POR 0x1000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_5__W7_I_ODD___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_5__W7_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_5___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_5___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_6 (0x005EA854) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_6___POR 0x00002000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_6__W8_I_ODD___POR 0x2000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_6__W8_I_ODD___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_6__W8_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_6___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_6___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_7 (0x005EA858) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_7___POR 0x00004000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_7__W9_I_ODD___POR 0x4000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_7__W9_I_ODD___M 0x00007FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_7__W9_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_7___M 0x00007FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH0_ADC_POST_PROC_I_ODD_REG_7___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_1 (0x005EA880) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_1__WOS_C_Q_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_1__WOS_C_Q_EVEN___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_1__WOS_C_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_1___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_2 (0x005EA884) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_2__WOS_F_Q_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_2__WOS_F_Q_EVEN___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_2__WOS_F_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_2___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_2___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_3 (0x005EA888) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_3___POR 0x00000400 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_3__W5_Q_EVEN___POR 0x400 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_3__W5_Q_EVEN___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_3__W5_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_3___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_3___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_4 (0x005EA88C) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_4___POR 0x00000800 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_4__W6_Q_EVEN___POR 0x800 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_4__W6_Q_EVEN___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_4__W6_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_4___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_4___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_5 (0x005EA890) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_5___POR 0x00001000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_5__W7_Q_EVEN___POR 0x1000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_5__W7_Q_EVEN___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_5__W7_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_5___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_5___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_6 (0x005EA894) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_6___POR 0x00002000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_6__W8_Q_EVEN___POR 0x2000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_6__W8_Q_EVEN___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_6__W8_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_6___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_6___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_7 (0x005EA898) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_7___POR 0x00004000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_7__W9_Q_EVEN___POR 0x4000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_7__W9_Q_EVEN___M 0x00007FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_7__W9_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_7___M 0x00007FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH0_ADC_POST_PROC_Q_EVEN_REG_7___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_1 (0x005EA8C0) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_1__WOS_C_Q_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_1__WOS_C_Q_ODD___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_1__WOS_C_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_1___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_2 (0x005EA8C4) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_2__WOS_F_Q_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_2__WOS_F_Q_ODD___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_2__WOS_F_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_2___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_2___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_3 (0x005EA8C8) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_3___POR 0x00000400 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_3__W5_Q_ODD___POR 0x400 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_3__W5_Q_ODD___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_3__W5_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_3___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_3___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_4 (0x005EA8CC) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_4___POR 0x00000800 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_4__W6_Q_ODD___POR 0x800 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_4__W6_Q_ODD___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_4__W6_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_4___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_4___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_5 (0x005EA8D0) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_5___POR 0x00001000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_5__W7_Q_ODD___POR 0x1000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_5__W7_Q_ODD___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_5__W7_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_5___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_5___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_6 (0x005EA8D4) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_6___POR 0x00002000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_6__W8_Q_ODD___POR 0x2000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_6__W8_Q_ODD___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_6__W8_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_6___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_6___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_7 (0x005EA8D8) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_7___POR 0x00004000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_7__W9_Q_ODD___POR 0x4000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_7__W9_Q_ODD___M 0x00007FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_7__W9_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_7___M 0x00007FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH0_ADC_POST_PROC_Q_ODD_REG_7___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_1 (0x005EA900) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_1__RO_WOS_C_I_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_1__RO_WOS_C_I_EVEN___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_1__RO_WOS_C_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_1___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_2 (0x005EA904) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_2__RO_WOS_F_I_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_2__RO_WOS_F_I_EVEN___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_2__RO_WOS_F_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_2___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_2___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_3 (0x005EA908) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_3__RO_W5_I_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_3__RO_W5_I_EVEN___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_3__RO_W5_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_3___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_3___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_4 (0x005EA90C) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_4___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_4__RO_W6_I_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_4__RO_W6_I_EVEN___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_4__RO_W6_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_4___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_4___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_5 (0x005EA910) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_5___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_5__RO_W7_I_EVEN___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_5__RO_W7_I_EVEN___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_5__RO_W7_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_5___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_5___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_6 (0x005EA914) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_6___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_6__RO_W8_I_EVEN___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_6__RO_W8_I_EVEN___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_6__RO_W8_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_6___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_6___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_7 (0x005EA918) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_7___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_7__RO_W9_I_EVEN___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_7__RO_W9_I_EVEN___M 0x00007FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_7__RO_W9_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_7___M 0x00007FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_7___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_8 (0x005EA91C) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_8___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_8__RO_CAL_DONE_I_EVEN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_8__RO_WCAL_FLAG_I_EVEN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_8__RO_CAL_DONE_I_EVEN___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_8__RO_CAL_DONE_I_EVEN___S 7 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_8__RO_WCAL_FLAG_I_EVEN___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_8__RO_WCAL_FLAG_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_8___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_8___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_9 (0x005EA920) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_9___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_9__RO_WOS_C_I_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_9__RO_WOS_C_I_ODD___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_9__RO_WOS_C_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_9___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_9___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_10 (0x005EA924) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_10___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_10__RO_WOS_F_I_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_10__RO_WOS_F_I_ODD___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_10__RO_WOS_F_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_10___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_10___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_11 (0x005EA928) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_11___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_11__RO_W5_I_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_11__RO_W5_I_ODD___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_11__RO_W5_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_11___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_11___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_12 (0x005EA92C) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_12___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_12__RO_W6_I_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_12__RO_W6_I_ODD___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_12__RO_W6_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_12___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_12___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_13 (0x005EA930) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_13___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_13__RO_W7_I_ODD___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_13__RO_W7_I_ODD___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_13__RO_W7_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_13___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_13___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_14 (0x005EA934) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_14___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_14__RO_W8_I_ODD___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_14__RO_W8_I_ODD___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_14__RO_W8_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_14___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_14___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_15 (0x005EA938) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_15___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_15__RO_W9_I_ODD___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_15__RO_W9_I_ODD___M 0x00007FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_15__RO_W9_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_15___M 0x00007FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_15___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_16 (0x005EA93C) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_16___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_16___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_16__RO_CAL_DONE_I_ODD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_16__RO_WCAL_FLAG_I_ODD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_16__RO_CAL_DONE_I_ODD___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_16__RO_CAL_DONE_I_ODD___S 7 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_16__RO_WCAL_FLAG_I_ODD___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_16__RO_WCAL_FLAG_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_16___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_16___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_17 (0x005EA940) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_17___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_17___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_17__RO_WOS_C_Q_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_17__RO_WOS_C_Q_EVEN___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_17__RO_WOS_C_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_17___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_17___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_18 (0x005EA944) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_18___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_18___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_18__RO_WOS_F_Q_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_18__RO_WOS_F_Q_EVEN___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_18__RO_WOS_F_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_18___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_18___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_19 (0x005EA948) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_19___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_19___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_19__RO_W5_Q_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_19__RO_W5_Q_EVEN___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_19__RO_W5_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_19___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_19___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_20 (0x005EA94C) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_20___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_20___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_20__RO_W6_Q_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_20__RO_W6_Q_EVEN___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_20__RO_W6_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_20___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_20___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_21 (0x005EA950) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_21___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_21___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_21__RO_W7_Q_EVEN___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_21__RO_W7_Q_EVEN___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_21__RO_W7_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_21___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_21___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_22 (0x005EA954) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_22___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_22___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_22__RO_W8_Q_EVEN___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_22__RO_W8_Q_EVEN___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_22__RO_W8_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_22___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_22___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_23 (0x005EA958) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_23___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_23___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_23__RO_W9_Q_EVEN___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_23__RO_W9_Q_EVEN___M 0x00007FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_23__RO_W9_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_23___M 0x00007FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_23___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_24 (0x005EA95C) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_24___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_24___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_24__RO_CAL_DONE_Q_EVEN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_24__RO_WCAL_FLAG_Q_EVEN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_24__RO_CAL_DONE_Q_EVEN___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_24__RO_CAL_DONE_Q_EVEN___S 7 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_24__RO_WCAL_FLAG_Q_EVEN___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_24__RO_WCAL_FLAG_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_24___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_24___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_25 (0x005EA960) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_25___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_25___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_25__RO_WOS_C_Q_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_25__RO_WOS_C_Q_ODD___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_25__RO_WOS_C_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_25___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_25___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_26 (0x005EA964) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_26___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_26___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_26__RO_WOS_F_Q_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_26__RO_WOS_F_Q_ODD___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_26__RO_WOS_F_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_26___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_26___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_27 (0x005EA968) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_27___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_27___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_27__RO_W5_Q_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_27__RO_W5_Q_ODD___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_27__RO_W5_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_27___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_27___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_28 (0x005EA96C) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_28___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_28___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_28__RO_W6_Q_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_28__RO_W6_Q_ODD___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_28__RO_W6_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_28___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_28___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_29 (0x005EA970) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_29___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_29___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_29__RO_W7_Q_ODD___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_29__RO_W7_Q_ODD___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_29__RO_W7_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_29___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_29___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_30 (0x005EA974) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_30___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_30___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_30__RO_W8_Q_ODD___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_30__RO_W8_Q_ODD___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_30__RO_W8_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_30___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_30___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_31 (0x005EA978) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_31___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_31___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_31__RO_W9_Q_ODD___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_31__RO_W9_Q_ODD___M 0x00007FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_31__RO_W9_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_31___M 0x00007FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_31___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_32 (0x005EA97C) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_32___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_32___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_32__RO_CAL_DONE_Q_ODD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_32__RO_WCAL_FLAG_Q_ODD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_32__RO_CAL_DONE_Q_ODD___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_32__RO_CAL_DONE_Q_ODD___S 7 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_32__RO_WCAL_FLAG_Q_ODD___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_32__RO_WCAL_FLAG_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_32___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_32___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_33 (0x005EA980) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_33___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_33___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_33__RO_K_FACTOR_I_EVEN___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_33__RO_K_FACTOR_I_EVEN___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_33__RO_K_FACTOR_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_33___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_33___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_34 (0x005EA984) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_34___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_34___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_34__RO_K_FACTOR_I_ODD___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_34__RO_K_FACTOR_I_ODD___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_34__RO_K_FACTOR_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_34___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_34___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_35 (0x005EA988) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_35___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_35___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_35__RO_K_FACTOR_Q_EVEN___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_35__RO_K_FACTOR_Q_EVEN___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_35__RO_K_FACTOR_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_35___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_35___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_36 (0x005EA98C) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_36___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_36___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_36__RO_K_FACTOR_Q_ODD___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_36__RO_K_FACTOR_Q_ODD___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_36__RO_K_FACTOR_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_36___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_POST_PROC_RO_REG_36___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_WOUT_REG (0x005EA990) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_WOUT_REG___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_WOUT_REG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_WOUT_REG__RO_WOUT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_WOUT_REG__RO_WOUT1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_WOUT_REG__RO_WOUT___M 0x00FFFF00 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_WOUT_REG__RO_WOUT___S 8 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_WOUT_REG__RO_WOUT1___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_WOUT_REG__RO_WOUT1___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_WOUT_REG___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_WOUT_REG___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_ADC_SPARE (0x005EA994) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_ADC_SPARE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_ADC_SPARE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_ADC_SPARE__D_ADC_SPARE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_ADC_SPARE__D_ADC_SPARE___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_ADC_SPARE__D_ADC_SPARE___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_ADC_SPARE___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_ADC_SPARE___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_SPARE (0x005EA998) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_SPARE___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_SPARE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_SPARE__D_ADC_RO_SPARE___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_SPARE__D_ADC_RO_SPARE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_SPARE__D_ADC_RO_SPARE___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_SPARE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH0_RO_ADC_SPARE___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0 (0x005EA99C) +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKADC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKADC_FREQ_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKADC_FREQ_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLK60_PHASE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKADC_CAL_FREQ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKADC_PHASE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__RXADC_CLK_SEL_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__PDADC_CLK_SEL_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKADC_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKADC_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKADC_FREQ_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKADC_FREQ_OV___S 27 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKADC_FREQ_OVD___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKADC_FREQ_OVD___S 24 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLK60_PHASE___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLK60_PHASE___S 12 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKADC_CAL_FREQ___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKADC_CAL_FREQ___S 8 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKADC_PHASE___M 0x00000070 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__CLKADC_PHASE___S 4 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__RXADC_CLK_SEL_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__RXADC_CLK_SEL_OVS___S 2 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__PDADC_CLK_SEL_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0__PDADC_CLK_SEL_OVS___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0___M 0xCF00737F +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_0___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_1 (0x005EA9A0) +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_1__SAMPLED_ADC_EN_EXT_MUX_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_1__D_CLKADC_TEST_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_1__SAMPLED_ADC_EN_EXT_MUX_SEL___M 0x0000000C +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_1__SAMPLED_ADC_EN_EXT_MUX_SEL___S 2 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_1__D_CLKADC_TEST_SEL___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_1__D_CLKADC_TEST_SEL___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_1___M 0x0000000D +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH0_BB_CLKGEN_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_0 (0x005EC000) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_0__RX_DCOC_RANGE_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_0__RX_DCOC_RES_I_0___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_0__RX_DCOC_RES_Q_0___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_0__RX_DCOC_RANGE_0___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_0__RX_DCOC_RANGE_0___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_0__RX_DCOC_RES_I_0___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_0__RX_DCOC_RES_I_0___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_0__RX_DCOC_RES_Q_0___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_0__RX_DCOC_RES_Q_0___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_0___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1 (0x005EC004) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1__RX_DCOC_RANGE_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1__RX_DCOC_RES_I_1___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1__RX_DCOC_RES_Q_1___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1__RX_DCOC_RANGE_1___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1__RX_DCOC_RANGE_1___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1__RX_DCOC_RES_I_1___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1__RX_DCOC_RES_I_1___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1__RX_DCOC_RES_Q_1___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1__RX_DCOC_RES_Q_1___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_2 (0x005EC008) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_2__RX_DCOC_RANGE_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_2__RX_DCOC_RES_I_2___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_2__RX_DCOC_RES_Q_2___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_2__RX_DCOC_RANGE_2___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_2__RX_DCOC_RANGE_2___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_2__RX_DCOC_RES_I_2___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_2__RX_DCOC_RES_I_2___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_2__RX_DCOC_RES_Q_2___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_2__RX_DCOC_RES_Q_2___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_2___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_2___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_3 (0x005EC00C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_3__RX_DCOC_RANGE_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_3__RX_DCOC_RES_I_3___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_3__RX_DCOC_RES_Q_3___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_3__RX_DCOC_RANGE_3___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_3__RX_DCOC_RANGE_3___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_3__RX_DCOC_RES_I_3___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_3__RX_DCOC_RES_I_3___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_3__RX_DCOC_RES_Q_3___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_3__RX_DCOC_RES_Q_3___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_3___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_3___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_4 (0x005EC010) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_4__RX_DCOC_RANGE_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_4__RX_DCOC_RES_I_4___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_4__RX_DCOC_RES_Q_4___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_4__RX_DCOC_RANGE_4___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_4__RX_DCOC_RANGE_4___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_4__RX_DCOC_RES_I_4___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_4__RX_DCOC_RES_I_4___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_4__RX_DCOC_RES_Q_4___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_4__RX_DCOC_RES_Q_4___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_4___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_4___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_5 (0x005EC014) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_5__RX_DCOC_RANGE_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_5__RX_DCOC_RES_I_5___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_5__RX_DCOC_RES_Q_5___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_5__RX_DCOC_RANGE_5___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_5__RX_DCOC_RANGE_5___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_5__RX_DCOC_RES_I_5___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_5__RX_DCOC_RES_I_5___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_5__RX_DCOC_RES_Q_5___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_5__RX_DCOC_RES_Q_5___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_5___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_5___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_6 (0x005EC018) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_6__RX_DCOC_RANGE_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_6__RX_DCOC_RES_I_6___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_6__RX_DCOC_RES_Q_6___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_6__RX_DCOC_RANGE_6___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_6__RX_DCOC_RANGE_6___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_6__RX_DCOC_RES_I_6___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_6__RX_DCOC_RES_I_6___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_6__RX_DCOC_RES_Q_6___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_6__RX_DCOC_RES_Q_6___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_6___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_6___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_7 (0x005EC01C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_7__RX_DCOC_RANGE_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_7__RX_DCOC_RES_I_7___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_7__RX_DCOC_RES_Q_7___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_7__RX_DCOC_RANGE_7___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_7__RX_DCOC_RANGE_7___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_7__RX_DCOC_RES_I_7___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_7__RX_DCOC_RES_I_7___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_7__RX_DCOC_RES_Q_7___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_7__RX_DCOC_RES_Q_7___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_7___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_7___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_8 (0x005EC020) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_8__RX_DCOC_RANGE_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_8__RX_DCOC_RES_I_8___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_8__RX_DCOC_RES_Q_8___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_8__RX_DCOC_RANGE_8___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_8__RX_DCOC_RANGE_8___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_8__RX_DCOC_RES_I_8___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_8__RX_DCOC_RES_I_8___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_8__RX_DCOC_RES_Q_8___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_8__RX_DCOC_RES_Q_8___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_8___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_8___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_9 (0x005EC024) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_9__RX_DCOC_RANGE_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_9__RX_DCOC_RES_I_9___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_9__RX_DCOC_RES_Q_9___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_9__RX_DCOC_RANGE_9___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_9__RX_DCOC_RANGE_9___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_9__RX_DCOC_RES_I_9___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_9__RX_DCOC_RES_I_9___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_9__RX_DCOC_RES_Q_9___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_9__RX_DCOC_RES_Q_9___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_9___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_9___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_10 (0x005EC028) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_10__RX_DCOC_RANGE_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_10__RX_DCOC_RES_I_10___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_10__RX_DCOC_RES_Q_10___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_10__RX_DCOC_RANGE_10___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_10__RX_DCOC_RANGE_10___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_10__RX_DCOC_RES_I_10___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_10__RX_DCOC_RES_I_10___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_10__RX_DCOC_RES_Q_10___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_10__RX_DCOC_RES_Q_10___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_10___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_10___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_11 (0x005EC02C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_11__RX_DCOC_RANGE_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_11__RX_DCOC_RES_I_11___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_11__RX_DCOC_RES_Q_11___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_11__RX_DCOC_RANGE_11___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_11__RX_DCOC_RANGE_11___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_11__RX_DCOC_RES_I_11___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_11__RX_DCOC_RES_I_11___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_11__RX_DCOC_RES_Q_11___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_11__RX_DCOC_RES_Q_11___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_11___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_11___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_12 (0x005EC030) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_12__RX_DCOC_RANGE_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_12__RX_DCOC_RES_I_12___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_12__RX_DCOC_RES_Q_12___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_12__RX_DCOC_RANGE_12___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_12__RX_DCOC_RANGE_12___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_12__RX_DCOC_RES_I_12___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_12__RX_DCOC_RES_I_12___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_12__RX_DCOC_RES_Q_12___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_12__RX_DCOC_RES_Q_12___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_12___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_12___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_13 (0x005EC034) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_13__RX_DCOC_RANGE_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_13__RX_DCOC_RES_I_13___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_13__RX_DCOC_RES_Q_13___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_13__RX_DCOC_RANGE_13___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_13__RX_DCOC_RANGE_13___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_13__RX_DCOC_RES_I_13___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_13__RX_DCOC_RES_I_13___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_13__RX_DCOC_RES_Q_13___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_13__RX_DCOC_RES_Q_13___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_13___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_13___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_14 (0x005EC038) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_14__RX_DCOC_RANGE_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_14__RX_DCOC_RES_I_14___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_14__RX_DCOC_RES_Q_14___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_14__RX_DCOC_RANGE_14___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_14__RX_DCOC_RANGE_14___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_14__RX_DCOC_RES_I_14___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_14__RX_DCOC_RES_I_14___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_14__RX_DCOC_RES_Q_14___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_14__RX_DCOC_RES_Q_14___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_14___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_14___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_15 (0x005EC03C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_15__RX_DCOC_RANGE_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_15__RX_DCOC_RES_I_15___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_15__RX_DCOC_RES_Q_15___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_15__RX_DCOC_RANGE_15___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_15__RX_DCOC_RANGE_15___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_15__RX_DCOC_RES_I_15___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_15__RX_DCOC_RES_I_15___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_15__RX_DCOC_RES_Q_15___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_15__RX_DCOC_RES_Q_15___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_15___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_15___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_16 (0x005EC040) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_16___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_16__RX_DCOC_RANGE_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_16__RX_DCOC_RES_I_16___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_16__RX_DCOC_RES_Q_16___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_16__RX_DCOC_RANGE_16___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_16__RX_DCOC_RANGE_16___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_16__RX_DCOC_RES_I_16___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_16__RX_DCOC_RES_I_16___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_16__RX_DCOC_RES_Q_16___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_16__RX_DCOC_RES_Q_16___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_16___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_16___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_17 (0x005EC044) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_17___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_17__RX_DCOC_RANGE_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_17__RX_DCOC_RES_I_17___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_17__RX_DCOC_RES_Q_17___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_17__RX_DCOC_RANGE_17___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_17__RX_DCOC_RANGE_17___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_17__RX_DCOC_RES_I_17___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_17__RX_DCOC_RES_I_17___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_17__RX_DCOC_RES_Q_17___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_17__RX_DCOC_RES_Q_17___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_17___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_17___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_18 (0x005EC048) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_18___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_18__RX_DCOC_RANGE_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_18__RX_DCOC_RES_I_18___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_18__RX_DCOC_RES_Q_18___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_18__RX_DCOC_RANGE_18___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_18__RX_DCOC_RANGE_18___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_18__RX_DCOC_RES_I_18___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_18__RX_DCOC_RES_I_18___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_18__RX_DCOC_RES_Q_18___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_18__RX_DCOC_RES_Q_18___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_18___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_18___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_19 (0x005EC04C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_19___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_19__RX_DCOC_RANGE_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_19__RX_DCOC_RES_I_19___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_19__RX_DCOC_RES_Q_19___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_19__RX_DCOC_RANGE_19___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_19__RX_DCOC_RANGE_19___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_19__RX_DCOC_RES_I_19___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_19__RX_DCOC_RES_I_19___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_19__RX_DCOC_RES_Q_19___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_19__RX_DCOC_RES_Q_19___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_19___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_19___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_20 (0x005EC050) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_20___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_20__RX_DCOC_RANGE_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_20__RX_DCOC_RES_I_20___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_20__RX_DCOC_RES_Q_20___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_20__RX_DCOC_RANGE_20___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_20__RX_DCOC_RANGE_20___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_20__RX_DCOC_RES_I_20___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_20__RX_DCOC_RES_I_20___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_20__RX_DCOC_RES_Q_20___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_20__RX_DCOC_RES_Q_20___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_20___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_20___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_21 (0x005EC054) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_21___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_21__RX_DCOC_RANGE_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_21__RX_DCOC_RES_I_21___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_21__RX_DCOC_RES_Q_21___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_21__RX_DCOC_RANGE_21___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_21__RX_DCOC_RANGE_21___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_21__RX_DCOC_RES_I_21___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_21__RX_DCOC_RES_I_21___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_21__RX_DCOC_RES_Q_21___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_21__RX_DCOC_RES_Q_21___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_21___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_21___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_22 (0x005EC058) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_22___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_22__RX_DCOC_RANGE_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_22__RX_DCOC_RES_I_22___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_22__RX_DCOC_RES_Q_22___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_22__RX_DCOC_RANGE_22___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_22__RX_DCOC_RANGE_22___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_22__RX_DCOC_RES_I_22___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_22__RX_DCOC_RES_I_22___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_22__RX_DCOC_RES_Q_22___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_22__RX_DCOC_RES_Q_22___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_22___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_22___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_23 (0x005EC05C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_23___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_23__RX_DCOC_RANGE_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_23__RX_DCOC_RES_I_23___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_23__RX_DCOC_RES_Q_23___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_23__RX_DCOC_RANGE_23___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_23__RX_DCOC_RANGE_23___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_23__RX_DCOC_RES_I_23___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_23__RX_DCOC_RES_I_23___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_23__RX_DCOC_RES_Q_23___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_23__RX_DCOC_RES_Q_23___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_23___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_23___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_24 (0x005EC060) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_24___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_24__RX_DCOC_RANGE_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_24__RX_DCOC_RES_I_24___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_24__RX_DCOC_RES_Q_24___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_24__RX_DCOC_RANGE_24___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_24__RX_DCOC_RANGE_24___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_24__RX_DCOC_RES_I_24___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_24__RX_DCOC_RES_I_24___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_24__RX_DCOC_RES_Q_24___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_24__RX_DCOC_RES_Q_24___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_24___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_24___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_25 (0x005EC064) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_25___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_25__RX_DCOC_RANGE_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_25__RX_DCOC_RES_I_25___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_25__RX_DCOC_RES_Q_25___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_25__RX_DCOC_RANGE_25___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_25__RX_DCOC_RANGE_25___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_25__RX_DCOC_RES_I_25___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_25__RX_DCOC_RES_I_25___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_25__RX_DCOC_RES_Q_25___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_25__RX_DCOC_RES_Q_25___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_25___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_25___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_26 (0x005EC068) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_26___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_26__RX_DCOC_RANGE_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_26__RX_DCOC_RES_I_26___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_26__RX_DCOC_RES_Q_26___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_26__RX_DCOC_RANGE_26___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_26__RX_DCOC_RANGE_26___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_26__RX_DCOC_RES_I_26___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_26__RX_DCOC_RES_I_26___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_26__RX_DCOC_RES_Q_26___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_26__RX_DCOC_RES_Q_26___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_26___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_26___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_27 (0x005EC06C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_27___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_27__RX_DCOC_RANGE_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_27__RX_DCOC_RES_I_27___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_27__RX_DCOC_RES_Q_27___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_27__RX_DCOC_RANGE_27___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_27__RX_DCOC_RANGE_27___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_27__RX_DCOC_RES_I_27___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_27__RX_DCOC_RES_I_27___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_27__RX_DCOC_RES_Q_27___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_27__RX_DCOC_RES_Q_27___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_27___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_27___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_28 (0x005EC070) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_28___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_28__RX_DCOC_RANGE_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_28__RX_DCOC_RES_I_28___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_28__RX_DCOC_RES_Q_28___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_28__RX_DCOC_RANGE_28___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_28__RX_DCOC_RANGE_28___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_28__RX_DCOC_RES_I_28___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_28__RX_DCOC_RES_I_28___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_28__RX_DCOC_RES_Q_28___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_28__RX_DCOC_RES_Q_28___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_28___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_28___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_29 (0x005EC074) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_29___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_29__RX_DCOC_RANGE_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_29__RX_DCOC_RES_I_29___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_29__RX_DCOC_RES_Q_29___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_29__RX_DCOC_RANGE_29___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_29__RX_DCOC_RANGE_29___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_29__RX_DCOC_RES_I_29___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_29__RX_DCOC_RES_I_29___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_29__RX_DCOC_RES_Q_29___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_29__RX_DCOC_RES_Q_29___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_29___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_29___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_30 (0x005EC078) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_30___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_30__RX_DCOC_RANGE_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_30__RX_DCOC_RES_I_30___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_30__RX_DCOC_RES_Q_30___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_30__RX_DCOC_RANGE_30___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_30__RX_DCOC_RANGE_30___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_30__RX_DCOC_RES_I_30___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_30__RX_DCOC_RES_I_30___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_30__RX_DCOC_RES_Q_30___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_30__RX_DCOC_RES_Q_30___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_30___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_30___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_31 (0x005EC07C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_31___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_31__RX_DCOC_RANGE_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_31__RX_DCOC_RES_I_31___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_31__RX_DCOC_RES_Q_31___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_31__RX_DCOC_RANGE_31___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_31__RX_DCOC_RANGE_31___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_31__RX_DCOC_RES_I_31___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_31__RX_DCOC_RES_I_31___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_31__RX_DCOC_RES_Q_31___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_31__RX_DCOC_RES_Q_31___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_31___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_31___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_32 (0x005EC080) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_32___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_32___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_32__RX_DCOC_RANGE_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_32__RX_DCOC_RES_I_32___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_32__RX_DCOC_RES_Q_32___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_32__RX_DCOC_RANGE_32___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_32__RX_DCOC_RANGE_32___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_32__RX_DCOC_RES_I_32___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_32__RX_DCOC_RES_I_32___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_32__RX_DCOC_RES_Q_32___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_32__RX_DCOC_RES_Q_32___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_32___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_32___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_33 (0x005EC084) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_33___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_33___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_33__RX_DCOC_RANGE_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_33__RX_DCOC_RES_I_33___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_33__RX_DCOC_RES_Q_33___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_33__RX_DCOC_RANGE_33___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_33__RX_DCOC_RANGE_33___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_33__RX_DCOC_RES_I_33___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_33__RX_DCOC_RES_I_33___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_33__RX_DCOC_RES_Q_33___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_33__RX_DCOC_RES_Q_33___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_33___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_33___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_34 (0x005EC088) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_34___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_34___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_34__RX_DCOC_RANGE_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_34__RX_DCOC_RES_I_34___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_34__RX_DCOC_RES_Q_34___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_34__RX_DCOC_RANGE_34___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_34__RX_DCOC_RANGE_34___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_34__RX_DCOC_RES_I_34___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_34__RX_DCOC_RES_I_34___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_34__RX_DCOC_RES_Q_34___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_34__RX_DCOC_RES_Q_34___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_34___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_34___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_35 (0x005EC08C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_35___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_35___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_35__RX_DCOC_RANGE_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_35__RX_DCOC_RES_I_35___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_35__RX_DCOC_RES_Q_35___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_35__RX_DCOC_RANGE_35___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_35__RX_DCOC_RANGE_35___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_35__RX_DCOC_RES_I_35___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_35__RX_DCOC_RES_I_35___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_35__RX_DCOC_RES_Q_35___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_35__RX_DCOC_RES_Q_35___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_35___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_35___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_36 (0x005EC090) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_36___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_36___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_36__RX_DCOC_RANGE_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_36__RX_DCOC_RES_I_36___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_36__RX_DCOC_RES_Q_36___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_36__RX_DCOC_RANGE_36___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_36__RX_DCOC_RANGE_36___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_36__RX_DCOC_RES_I_36___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_36__RX_DCOC_RES_I_36___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_36__RX_DCOC_RES_Q_36___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_36__RX_DCOC_RES_Q_36___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_36___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_36___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_37 (0x005EC094) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_37___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_37___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_37__RX_DCOC_RANGE_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_37__RX_DCOC_RES_I_37___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_37__RX_DCOC_RES_Q_37___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_37__RX_DCOC_RANGE_37___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_37__RX_DCOC_RANGE_37___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_37__RX_DCOC_RES_I_37___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_37__RX_DCOC_RES_I_37___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_37__RX_DCOC_RES_Q_37___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_37__RX_DCOC_RES_Q_37___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_37___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_37___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_38 (0x005EC098) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_38___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_38___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_38__RX_DCOC_RANGE_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_38__RX_DCOC_RES_I_38___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_38__RX_DCOC_RES_Q_38___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_38__RX_DCOC_RANGE_38___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_38__RX_DCOC_RANGE_38___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_38__RX_DCOC_RES_I_38___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_38__RX_DCOC_RES_I_38___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_38__RX_DCOC_RES_Q_38___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_38__RX_DCOC_RES_Q_38___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_38___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_38___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_39 (0x005EC09C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_39___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_39___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_39__RX_DCOC_RANGE_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_39__RX_DCOC_RES_I_39___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_39__RX_DCOC_RES_Q_39___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_39__RX_DCOC_RANGE_39___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_39__RX_DCOC_RANGE_39___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_39__RX_DCOC_RES_I_39___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_39__RX_DCOC_RES_I_39___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_39__RX_DCOC_RES_Q_39___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_39__RX_DCOC_RES_Q_39___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_39___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_39___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_40 (0x005EC0A0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_40___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_40___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_40__RX_DCOC_RANGE_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_40__RX_DCOC_RES_I_40___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_40__RX_DCOC_RES_Q_40___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_40__RX_DCOC_RANGE_40___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_40__RX_DCOC_RANGE_40___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_40__RX_DCOC_RES_I_40___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_40__RX_DCOC_RES_I_40___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_40__RX_DCOC_RES_Q_40___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_40__RX_DCOC_RES_Q_40___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_40___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_40___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_41 (0x005EC0A4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_41___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_41___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_41__RX_DCOC_RANGE_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_41__RX_DCOC_RES_I_41___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_41__RX_DCOC_RES_Q_41___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_41__RX_DCOC_RANGE_41___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_41__RX_DCOC_RANGE_41___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_41__RX_DCOC_RES_I_41___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_41__RX_DCOC_RES_I_41___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_41__RX_DCOC_RES_Q_41___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_41__RX_DCOC_RES_Q_41___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_41___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_41___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_42 (0x005EC0A8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_42___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_42___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_42__RX_DCOC_RANGE_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_42__RX_DCOC_RES_I_42___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_42__RX_DCOC_RES_Q_42___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_42__RX_DCOC_RANGE_42___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_42__RX_DCOC_RANGE_42___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_42__RX_DCOC_RES_I_42___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_42__RX_DCOC_RES_I_42___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_42__RX_DCOC_RES_Q_42___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_42__RX_DCOC_RES_Q_42___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_42___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_42___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_43 (0x005EC0AC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_43___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_43___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_43__RX_DCOC_RANGE_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_43__RX_DCOC_RES_I_43___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_43__RX_DCOC_RES_Q_43___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_43__RX_DCOC_RANGE_43___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_43__RX_DCOC_RANGE_43___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_43__RX_DCOC_RES_I_43___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_43__RX_DCOC_RES_I_43___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_43__RX_DCOC_RES_Q_43___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_43__RX_DCOC_RES_Q_43___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_43___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_43___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_44 (0x005EC0B0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_44___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_44___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_44__RX_DCOC_RANGE_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_44__RX_DCOC_RES_I_44___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_44__RX_DCOC_RES_Q_44___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_44__RX_DCOC_RANGE_44___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_44__RX_DCOC_RANGE_44___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_44__RX_DCOC_RES_I_44___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_44__RX_DCOC_RES_I_44___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_44__RX_DCOC_RES_Q_44___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_44__RX_DCOC_RES_Q_44___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_44___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_44___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_45 (0x005EC0B4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_45___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_45___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_45__RX_DCOC_RANGE_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_45__RX_DCOC_RES_I_45___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_45__RX_DCOC_RES_Q_45___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_45__RX_DCOC_RANGE_45___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_45__RX_DCOC_RANGE_45___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_45__RX_DCOC_RES_I_45___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_45__RX_DCOC_RES_I_45___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_45__RX_DCOC_RES_Q_45___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_45__RX_DCOC_RES_Q_45___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_45___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_45___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_46 (0x005EC0B8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_46___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_46___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_46__RX_DCOC_RANGE_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_46__RX_DCOC_RES_I_46___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_46__RX_DCOC_RES_Q_46___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_46__RX_DCOC_RANGE_46___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_46__RX_DCOC_RANGE_46___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_46__RX_DCOC_RES_I_46___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_46__RX_DCOC_RES_I_46___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_46__RX_DCOC_RES_Q_46___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_46__RX_DCOC_RES_Q_46___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_46___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_46___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_47 (0x005EC0BC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_47___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_47___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_47__RX_DCOC_RANGE_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_47__RX_DCOC_RES_I_47___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_47__RX_DCOC_RES_Q_47___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_47__RX_DCOC_RANGE_47___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_47__RX_DCOC_RANGE_47___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_47__RX_DCOC_RES_I_47___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_47__RX_DCOC_RES_I_47___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_47__RX_DCOC_RES_Q_47___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_47__RX_DCOC_RES_Q_47___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_47___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_47___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_48 (0x005EC0C0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_48___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_48___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_48__RX_DCOC_RANGE_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_48__RX_DCOC_RES_I_48___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_48__RX_DCOC_RES_Q_48___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_48__RX_DCOC_RANGE_48___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_48__RX_DCOC_RANGE_48___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_48__RX_DCOC_RES_I_48___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_48__RX_DCOC_RES_I_48___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_48__RX_DCOC_RES_Q_48___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_48__RX_DCOC_RES_Q_48___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_48___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_48___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_49 (0x005EC0C4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_49___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_49___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_49__RX_DCOC_RANGE_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_49__RX_DCOC_RES_I_49___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_49__RX_DCOC_RES_Q_49___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_49__RX_DCOC_RANGE_49___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_49__RX_DCOC_RANGE_49___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_49__RX_DCOC_RES_I_49___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_49__RX_DCOC_RES_I_49___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_49__RX_DCOC_RES_Q_49___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_49__RX_DCOC_RES_Q_49___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_49___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_49___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_50 (0x005EC0C8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_50___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_50___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_50__RX_DCOC_RANGE_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_50__RX_DCOC_RES_I_50___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_50__RX_DCOC_RES_Q_50___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_50__RX_DCOC_RANGE_50___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_50__RX_DCOC_RANGE_50___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_50__RX_DCOC_RES_I_50___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_50__RX_DCOC_RES_I_50___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_50__RX_DCOC_RES_Q_50___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_50__RX_DCOC_RES_Q_50___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_50___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_50___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_51 (0x005EC0CC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_51___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_51___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_51__RX_DCOC_RANGE_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_51__RX_DCOC_RES_I_51___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_51__RX_DCOC_RES_Q_51___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_51__RX_DCOC_RANGE_51___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_51__RX_DCOC_RANGE_51___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_51__RX_DCOC_RES_I_51___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_51__RX_DCOC_RES_I_51___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_51__RX_DCOC_RES_Q_51___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_51__RX_DCOC_RES_Q_51___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_51___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_51___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_52 (0x005EC0D0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_52___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_52___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_52__RX_DCOC_RANGE_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_52__RX_DCOC_RES_I_52___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_52__RX_DCOC_RES_Q_52___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_52__RX_DCOC_RANGE_52___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_52__RX_DCOC_RANGE_52___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_52__RX_DCOC_RES_I_52___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_52__RX_DCOC_RES_I_52___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_52__RX_DCOC_RES_Q_52___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_52__RX_DCOC_RES_Q_52___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_52___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_52___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_53 (0x005EC0D4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_53___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_53___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_53__RX_DCOC_RANGE_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_53__RX_DCOC_RES_I_53___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_53__RX_DCOC_RES_Q_53___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_53__RX_DCOC_RANGE_53___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_53__RX_DCOC_RANGE_53___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_53__RX_DCOC_RES_I_53___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_53__RX_DCOC_RES_I_53___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_53__RX_DCOC_RES_Q_53___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_53__RX_DCOC_RES_Q_53___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_53___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_53___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_54 (0x005EC0D8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_54___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_54___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_54__RX_DCOC_RANGE_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_54__RX_DCOC_RES_I_54___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_54__RX_DCOC_RES_Q_54___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_54__RX_DCOC_RANGE_54___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_54__RX_DCOC_RANGE_54___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_54__RX_DCOC_RES_I_54___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_54__RX_DCOC_RES_I_54___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_54__RX_DCOC_RES_Q_54___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_54__RX_DCOC_RES_Q_54___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_54___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_54___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_55 (0x005EC0DC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_55___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_55___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_55__RX_DCOC_RANGE_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_55__RX_DCOC_RES_I_55___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_55__RX_DCOC_RES_Q_55___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_55__RX_DCOC_RANGE_55___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_55__RX_DCOC_RANGE_55___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_55__RX_DCOC_RES_I_55___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_55__RX_DCOC_RES_I_55___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_55__RX_DCOC_RES_Q_55___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_55__RX_DCOC_RES_Q_55___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_55___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_55___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_56 (0x005EC0E0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_56___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_56___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_56__RX_DCOC_RANGE_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_56__RX_DCOC_RES_I_56___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_56__RX_DCOC_RES_Q_56___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_56__RX_DCOC_RANGE_56___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_56__RX_DCOC_RANGE_56___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_56__RX_DCOC_RES_I_56___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_56__RX_DCOC_RES_I_56___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_56__RX_DCOC_RES_Q_56___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_56__RX_DCOC_RES_Q_56___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_56___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_56___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_57 (0x005EC0E4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_57___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_57___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_57__RX_DCOC_RANGE_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_57__RX_DCOC_RES_I_57___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_57__RX_DCOC_RES_Q_57___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_57__RX_DCOC_RANGE_57___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_57__RX_DCOC_RANGE_57___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_57__RX_DCOC_RES_I_57___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_57__RX_DCOC_RES_I_57___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_57__RX_DCOC_RES_Q_57___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_57__RX_DCOC_RES_Q_57___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_57___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_57___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_58 (0x005EC0E8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_58___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_58___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_58__RX_DCOC_RANGE_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_58__RX_DCOC_RES_I_58___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_58__RX_DCOC_RES_Q_58___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_58__RX_DCOC_RANGE_58___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_58__RX_DCOC_RANGE_58___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_58__RX_DCOC_RES_I_58___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_58__RX_DCOC_RES_I_58___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_58__RX_DCOC_RES_Q_58___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_58__RX_DCOC_RES_Q_58___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_58___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_58___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_59 (0x005EC0EC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_59___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_59___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_59__RX_DCOC_RANGE_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_59__RX_DCOC_RES_I_59___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_59__RX_DCOC_RES_Q_59___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_59__RX_DCOC_RANGE_59___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_59__RX_DCOC_RANGE_59___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_59__RX_DCOC_RES_I_59___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_59__RX_DCOC_RES_I_59___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_59__RX_DCOC_RES_Q_59___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_59__RX_DCOC_RES_Q_59___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_59___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_59___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_60 (0x005EC0F0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_60___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_60___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_60__RX_DCOC_RANGE_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_60__RX_DCOC_RES_I_60___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_60__RX_DCOC_RES_Q_60___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_60__RX_DCOC_RANGE_60___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_60__RX_DCOC_RANGE_60___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_60__RX_DCOC_RES_I_60___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_60__RX_DCOC_RES_I_60___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_60__RX_DCOC_RES_Q_60___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_60__RX_DCOC_RES_Q_60___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_60___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_60___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_61 (0x005EC0F4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_61___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_61___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_61__RX_DCOC_RANGE_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_61__RX_DCOC_RES_I_61___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_61__RX_DCOC_RES_Q_61___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_61__RX_DCOC_RANGE_61___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_61__RX_DCOC_RANGE_61___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_61__RX_DCOC_RES_I_61___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_61__RX_DCOC_RES_I_61___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_61__RX_DCOC_RES_Q_61___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_61__RX_DCOC_RES_Q_61___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_61___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_61___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_62 (0x005EC0F8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_62___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_62___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_62__RX_DCOC_RANGE_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_62__RX_DCOC_RES_I_62___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_62__RX_DCOC_RES_Q_62___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_62__RX_DCOC_RANGE_62___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_62__RX_DCOC_RANGE_62___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_62__RX_DCOC_RES_I_62___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_62__RX_DCOC_RES_I_62___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_62__RX_DCOC_RES_Q_62___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_62__RX_DCOC_RES_Q_62___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_62___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_62___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_63 (0x005EC0FC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_63___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_63___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_63__RX_DCOC_RANGE_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_63__RX_DCOC_RES_I_63___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_63__RX_DCOC_RES_Q_63___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_63__RX_DCOC_RANGE_63___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_63__RX_DCOC_RANGE_63___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_63__RX_DCOC_RES_I_63___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_63__RX_DCOC_RES_I_63___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_63__RX_DCOC_RES_Q_63___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_63__RX_DCOC_RES_Q_63___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_63___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_63___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_64 (0x005EC100) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_64___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_64___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_64__RX_DCOC_RANGE_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_64__RX_DCOC_RES_I_64___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_64__RX_DCOC_RES_Q_64___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_64__RX_DCOC_RANGE_64___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_64__RX_DCOC_RANGE_64___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_64__RX_DCOC_RES_I_64___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_64__RX_DCOC_RES_I_64___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_64__RX_DCOC_RES_Q_64___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_64__RX_DCOC_RES_Q_64___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_64___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_64___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_65 (0x005EC104) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_65___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_65___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_65__RX_DCOC_RANGE_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_65__RX_DCOC_RES_I_65___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_65__RX_DCOC_RES_Q_65___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_65__RX_DCOC_RANGE_65___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_65__RX_DCOC_RANGE_65___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_65__RX_DCOC_RES_I_65___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_65__RX_DCOC_RES_I_65___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_65__RX_DCOC_RES_Q_65___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_65__RX_DCOC_RES_Q_65___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_65___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_65___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_66 (0x005EC108) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_66___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_66___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_66__RX_DCOC_RANGE_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_66__RX_DCOC_RES_I_66___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_66__RX_DCOC_RES_Q_66___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_66__RX_DCOC_RANGE_66___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_66__RX_DCOC_RANGE_66___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_66__RX_DCOC_RES_I_66___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_66__RX_DCOC_RES_I_66___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_66__RX_DCOC_RES_Q_66___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_66__RX_DCOC_RES_Q_66___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_66___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_66___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_67 (0x005EC10C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_67___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_67___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_67__RX_DCOC_RANGE_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_67__RX_DCOC_RES_I_67___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_67__RX_DCOC_RES_Q_67___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_67__RX_DCOC_RANGE_67___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_67__RX_DCOC_RANGE_67___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_67__RX_DCOC_RES_I_67___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_67__RX_DCOC_RES_I_67___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_67__RX_DCOC_RES_Q_67___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_67__RX_DCOC_RES_Q_67___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_67___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_67___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_68 (0x005EC110) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_68___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_68___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_68__RX_DCOC_RANGE_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_68__RX_DCOC_RES_I_68___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_68__RX_DCOC_RES_Q_68___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_68__RX_DCOC_RANGE_68___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_68__RX_DCOC_RANGE_68___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_68__RX_DCOC_RES_I_68___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_68__RX_DCOC_RES_I_68___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_68__RX_DCOC_RES_Q_68___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_68__RX_DCOC_RES_Q_68___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_68___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_68___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_69 (0x005EC114) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_69___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_69___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_69__RX_DCOC_RANGE_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_69__RX_DCOC_RES_I_69___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_69__RX_DCOC_RES_Q_69___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_69__RX_DCOC_RANGE_69___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_69__RX_DCOC_RANGE_69___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_69__RX_DCOC_RES_I_69___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_69__RX_DCOC_RES_I_69___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_69__RX_DCOC_RES_Q_69___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_69__RX_DCOC_RES_Q_69___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_69___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_69___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_70 (0x005EC118) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_70___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_70___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_70__RX_DCOC_RANGE_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_70__RX_DCOC_RES_I_70___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_70__RX_DCOC_RES_Q_70___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_70__RX_DCOC_RANGE_70___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_70__RX_DCOC_RANGE_70___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_70__RX_DCOC_RES_I_70___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_70__RX_DCOC_RES_I_70___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_70__RX_DCOC_RES_Q_70___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_70__RX_DCOC_RES_Q_70___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_70___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_70___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_71 (0x005EC11C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_71___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_71___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_71__RX_DCOC_RANGE_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_71__RX_DCOC_RES_I_71___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_71__RX_DCOC_RES_Q_71___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_71__RX_DCOC_RANGE_71___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_71__RX_DCOC_RANGE_71___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_71__RX_DCOC_RES_I_71___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_71__RX_DCOC_RES_I_71___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_71__RX_DCOC_RES_Q_71___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_71__RX_DCOC_RES_Q_71___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_71___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_71___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_72 (0x005EC120) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_72___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_72___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_72__RX_DCOC_RANGE_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_72__RX_DCOC_RES_I_72___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_72__RX_DCOC_RES_Q_72___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_72__RX_DCOC_RANGE_72___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_72__RX_DCOC_RANGE_72___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_72__RX_DCOC_RES_I_72___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_72__RX_DCOC_RES_I_72___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_72__RX_DCOC_RES_Q_72___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_72__RX_DCOC_RES_Q_72___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_72___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_72___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_73 (0x005EC124) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_73___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_73___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_73__RX_DCOC_RANGE_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_73__RX_DCOC_RES_I_73___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_73__RX_DCOC_RES_Q_73___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_73__RX_DCOC_RANGE_73___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_73__RX_DCOC_RANGE_73___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_73__RX_DCOC_RES_I_73___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_73__RX_DCOC_RES_I_73___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_73__RX_DCOC_RES_Q_73___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_73__RX_DCOC_RES_Q_73___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_73___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_73___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_74 (0x005EC128) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_74___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_74___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_74__RX_DCOC_RANGE_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_74__RX_DCOC_RES_I_74___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_74__RX_DCOC_RES_Q_74___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_74__RX_DCOC_RANGE_74___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_74__RX_DCOC_RANGE_74___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_74__RX_DCOC_RES_I_74___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_74__RX_DCOC_RES_I_74___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_74__RX_DCOC_RES_Q_74___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_74__RX_DCOC_RES_Q_74___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_74___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_74___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_75 (0x005EC12C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_75___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_75___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_75__RX_DCOC_RANGE_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_75__RX_DCOC_RES_I_75___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_75__RX_DCOC_RES_Q_75___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_75__RX_DCOC_RANGE_75___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_75__RX_DCOC_RANGE_75___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_75__RX_DCOC_RES_I_75___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_75__RX_DCOC_RES_I_75___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_75__RX_DCOC_RES_Q_75___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_75__RX_DCOC_RES_Q_75___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_75___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_75___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_76 (0x005EC130) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_76___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_76___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_76__RX_DCOC_RANGE_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_76__RX_DCOC_RES_I_76___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_76__RX_DCOC_RES_Q_76___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_76__RX_DCOC_RANGE_76___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_76__RX_DCOC_RANGE_76___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_76__RX_DCOC_RES_I_76___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_76__RX_DCOC_RES_I_76___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_76__RX_DCOC_RES_Q_76___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_76__RX_DCOC_RES_Q_76___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_76___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_76___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_77 (0x005EC134) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_77___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_77___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_77__RX_DCOC_RANGE_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_77__RX_DCOC_RES_I_77___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_77__RX_DCOC_RES_Q_77___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_77__RX_DCOC_RANGE_77___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_77__RX_DCOC_RANGE_77___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_77__RX_DCOC_RES_I_77___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_77__RX_DCOC_RES_I_77___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_77__RX_DCOC_RES_Q_77___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_77__RX_DCOC_RES_Q_77___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_77___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_77___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_78 (0x005EC138) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_78___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_78___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_78__RX_DCOC_RANGE_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_78__RX_DCOC_RES_I_78___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_78__RX_DCOC_RES_Q_78___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_78__RX_DCOC_RANGE_78___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_78__RX_DCOC_RANGE_78___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_78__RX_DCOC_RES_I_78___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_78__RX_DCOC_RES_I_78___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_78__RX_DCOC_RES_Q_78___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_78__RX_DCOC_RES_Q_78___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_78___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_78___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_79 (0x005EC13C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_79___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_79___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_79__RX_DCOC_RANGE_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_79__RX_DCOC_RES_I_79___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_79__RX_DCOC_RES_Q_79___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_79__RX_DCOC_RANGE_79___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_79__RX_DCOC_RANGE_79___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_79__RX_DCOC_RES_I_79___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_79__RX_DCOC_RES_I_79___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_79__RX_DCOC_RES_Q_79___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_79__RX_DCOC_RES_Q_79___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_79___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_79___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_80 (0x005EC140) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_80___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_80___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_80__RX_DCOC_RANGE_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_80__RX_DCOC_RES_I_80___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_80__RX_DCOC_RES_Q_80___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_80__RX_DCOC_RANGE_80___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_80__RX_DCOC_RANGE_80___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_80__RX_DCOC_RES_I_80___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_80__RX_DCOC_RES_I_80___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_80__RX_DCOC_RES_Q_80___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_80__RX_DCOC_RES_Q_80___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_80___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_80___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_81 (0x005EC144) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_81___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_81___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_81__RX_DCOC_RANGE_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_81__RX_DCOC_RES_I_81___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_81__RX_DCOC_RES_Q_81___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_81__RX_DCOC_RANGE_81___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_81__RX_DCOC_RANGE_81___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_81__RX_DCOC_RES_I_81___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_81__RX_DCOC_RES_I_81___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_81__RX_DCOC_RES_Q_81___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_81__RX_DCOC_RES_Q_81___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_81___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_81___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_82 (0x005EC148) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_82___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_82___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_82__RX_DCOC_RANGE_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_82__RX_DCOC_RES_I_82___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_82__RX_DCOC_RES_Q_82___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_82__RX_DCOC_RANGE_82___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_82__RX_DCOC_RANGE_82___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_82__RX_DCOC_RES_I_82___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_82__RX_DCOC_RES_I_82___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_82__RX_DCOC_RES_Q_82___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_82__RX_DCOC_RES_Q_82___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_82___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_82___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_83 (0x005EC14C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_83___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_83___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_83__RX_DCOC_RANGE_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_83__RX_DCOC_RES_I_83___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_83__RX_DCOC_RES_Q_83___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_83__RX_DCOC_RANGE_83___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_83__RX_DCOC_RANGE_83___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_83__RX_DCOC_RES_I_83___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_83__RX_DCOC_RES_I_83___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_83__RX_DCOC_RES_Q_83___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_83__RX_DCOC_RES_Q_83___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_83___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_83___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_84 (0x005EC150) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_84___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_84___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_84__RX_DCOC_RANGE_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_84__RX_DCOC_RES_I_84___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_84__RX_DCOC_RES_Q_84___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_84__RX_DCOC_RANGE_84___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_84__RX_DCOC_RANGE_84___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_84__RX_DCOC_RES_I_84___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_84__RX_DCOC_RES_I_84___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_84__RX_DCOC_RES_Q_84___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_84__RX_DCOC_RES_Q_84___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_84___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_84___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_85 (0x005EC154) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_85___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_85___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_85__RX_DCOC_RANGE_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_85__RX_DCOC_RES_I_85___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_85__RX_DCOC_RES_Q_85___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_85__RX_DCOC_RANGE_85___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_85__RX_DCOC_RANGE_85___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_85__RX_DCOC_RES_I_85___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_85__RX_DCOC_RES_I_85___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_85__RX_DCOC_RES_Q_85___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_85__RX_DCOC_RES_Q_85___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_85___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_85___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_86 (0x005EC158) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_86___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_86___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_86__RX_DCOC_RANGE_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_86__RX_DCOC_RES_I_86___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_86__RX_DCOC_RES_Q_86___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_86__RX_DCOC_RANGE_86___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_86__RX_DCOC_RANGE_86___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_86__RX_DCOC_RES_I_86___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_86__RX_DCOC_RES_I_86___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_86__RX_DCOC_RES_Q_86___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_86__RX_DCOC_RES_Q_86___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_86___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_86___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_87 (0x005EC15C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_87___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_87___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_87__RX_DCOC_RANGE_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_87__RX_DCOC_RES_I_87___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_87__RX_DCOC_RES_Q_87___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_87__RX_DCOC_RANGE_87___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_87__RX_DCOC_RANGE_87___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_87__RX_DCOC_RES_I_87___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_87__RX_DCOC_RES_I_87___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_87__RX_DCOC_RES_Q_87___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_87__RX_DCOC_RES_Q_87___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_87___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_87___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_88 (0x005EC160) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_88___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_88___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_88__RX_DCOC_RANGE_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_88__RX_DCOC_RES_I_88___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_88__RX_DCOC_RES_Q_88___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_88__RX_DCOC_RANGE_88___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_88__RX_DCOC_RANGE_88___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_88__RX_DCOC_RES_I_88___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_88__RX_DCOC_RES_I_88___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_88__RX_DCOC_RES_Q_88___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_88__RX_DCOC_RES_Q_88___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_88___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_88___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_89 (0x005EC164) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_89___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_89___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_89__RX_DCOC_RANGE_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_89__RX_DCOC_RES_I_89___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_89__RX_DCOC_RES_Q_89___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_89__RX_DCOC_RANGE_89___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_89__RX_DCOC_RANGE_89___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_89__RX_DCOC_RES_I_89___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_89__RX_DCOC_RES_I_89___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_89__RX_DCOC_RES_Q_89___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_89__RX_DCOC_RES_Q_89___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_89___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_89___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_90 (0x005EC168) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_90___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_90___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_90__RX_DCOC_RANGE_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_90__RX_DCOC_RES_I_90___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_90__RX_DCOC_RES_Q_90___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_90__RX_DCOC_RANGE_90___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_90__RX_DCOC_RANGE_90___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_90__RX_DCOC_RES_I_90___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_90__RX_DCOC_RES_I_90___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_90__RX_DCOC_RES_Q_90___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_90__RX_DCOC_RES_Q_90___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_90___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_90___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_91 (0x005EC16C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_91___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_91___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_91__RX_DCOC_RANGE_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_91__RX_DCOC_RES_I_91___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_91__RX_DCOC_RES_Q_91___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_91__RX_DCOC_RANGE_91___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_91__RX_DCOC_RANGE_91___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_91__RX_DCOC_RES_I_91___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_91__RX_DCOC_RES_I_91___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_91__RX_DCOC_RES_Q_91___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_91__RX_DCOC_RES_Q_91___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_91___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_91___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_92 (0x005EC170) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_92___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_92___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_92__RX_DCOC_RANGE_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_92__RX_DCOC_RES_I_92___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_92__RX_DCOC_RES_Q_92___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_92__RX_DCOC_RANGE_92___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_92__RX_DCOC_RANGE_92___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_92__RX_DCOC_RES_I_92___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_92__RX_DCOC_RES_I_92___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_92__RX_DCOC_RES_Q_92___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_92__RX_DCOC_RES_Q_92___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_92___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_92___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_93 (0x005EC174) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_93___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_93___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_93__RX_DCOC_RANGE_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_93__RX_DCOC_RES_I_93___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_93__RX_DCOC_RES_Q_93___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_93__RX_DCOC_RANGE_93___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_93__RX_DCOC_RANGE_93___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_93__RX_DCOC_RES_I_93___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_93__RX_DCOC_RES_I_93___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_93__RX_DCOC_RES_Q_93___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_93__RX_DCOC_RES_Q_93___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_93___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_93___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_94 (0x005EC178) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_94___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_94___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_94__RX_DCOC_RANGE_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_94__RX_DCOC_RES_I_94___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_94__RX_DCOC_RES_Q_94___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_94__RX_DCOC_RANGE_94___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_94__RX_DCOC_RANGE_94___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_94__RX_DCOC_RES_I_94___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_94__RX_DCOC_RES_I_94___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_94__RX_DCOC_RES_Q_94___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_94__RX_DCOC_RES_Q_94___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_94___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_94___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_95 (0x005EC17C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_95___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_95___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_95__RX_DCOC_RANGE_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_95__RX_DCOC_RES_I_95___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_95__RX_DCOC_RES_Q_95___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_95__RX_DCOC_RANGE_95___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_95__RX_DCOC_RANGE_95___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_95__RX_DCOC_RES_I_95___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_95__RX_DCOC_RES_I_95___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_95__RX_DCOC_RES_Q_95___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_95__RX_DCOC_RES_Q_95___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_95___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_95___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_96 (0x005EC180) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_96___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_96___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_96__RX_DCOC_RANGE_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_96__RX_DCOC_RES_I_96___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_96__RX_DCOC_RES_Q_96___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_96__RX_DCOC_RANGE_96___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_96__RX_DCOC_RANGE_96___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_96__RX_DCOC_RES_I_96___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_96__RX_DCOC_RES_I_96___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_96__RX_DCOC_RES_Q_96___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_96__RX_DCOC_RES_Q_96___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_96___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_96___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_97 (0x005EC184) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_97___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_97___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_97__RX_DCOC_RANGE_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_97__RX_DCOC_RES_I_97___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_97__RX_DCOC_RES_Q_97___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_97__RX_DCOC_RANGE_97___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_97__RX_DCOC_RANGE_97___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_97__RX_DCOC_RES_I_97___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_97__RX_DCOC_RES_I_97___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_97__RX_DCOC_RES_Q_97___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_97__RX_DCOC_RES_Q_97___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_97___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_97___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_98 (0x005EC188) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_98___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_98___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_98__RX_DCOC_RANGE_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_98__RX_DCOC_RES_I_98___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_98__RX_DCOC_RES_Q_98___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_98__RX_DCOC_RANGE_98___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_98__RX_DCOC_RANGE_98___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_98__RX_DCOC_RES_I_98___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_98__RX_DCOC_RES_I_98___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_98__RX_DCOC_RES_Q_98___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_98__RX_DCOC_RES_Q_98___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_98___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_98___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_99 (0x005EC18C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_99___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_99___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_99__RX_DCOC_RANGE_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_99__RX_DCOC_RES_I_99___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_99__RX_DCOC_RES_Q_99___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_99__RX_DCOC_RANGE_99___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_99__RX_DCOC_RANGE_99___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_99__RX_DCOC_RES_I_99___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_99__RX_DCOC_RES_I_99___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_99__RX_DCOC_RES_Q_99___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_99__RX_DCOC_RES_Q_99___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_99___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_99___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_100 (0x005EC190) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_100___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_100___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_100__RX_DCOC_RANGE_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_100__RX_DCOC_RES_I_100___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_100__RX_DCOC_RES_Q_100___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_100__RX_DCOC_RANGE_100___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_100__RX_DCOC_RANGE_100___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_100__RX_DCOC_RES_I_100___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_100__RX_DCOC_RES_I_100___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_100__RX_DCOC_RES_Q_100___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_100__RX_DCOC_RES_Q_100___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_100___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_100___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_101 (0x005EC194) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_101___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_101___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_101__RX_DCOC_RANGE_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_101__RX_DCOC_RES_I_101___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_101__RX_DCOC_RES_Q_101___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_101__RX_DCOC_RANGE_101___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_101__RX_DCOC_RANGE_101___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_101__RX_DCOC_RES_I_101___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_101__RX_DCOC_RES_I_101___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_101__RX_DCOC_RES_Q_101___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_101__RX_DCOC_RES_Q_101___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_101___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_101___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_102 (0x005EC198) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_102___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_102___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_102__RX_DCOC_RANGE_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_102__RX_DCOC_RES_I_102___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_102__RX_DCOC_RES_Q_102___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_102__RX_DCOC_RANGE_102___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_102__RX_DCOC_RANGE_102___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_102__RX_DCOC_RES_I_102___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_102__RX_DCOC_RES_I_102___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_102__RX_DCOC_RES_Q_102___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_102__RX_DCOC_RES_Q_102___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_102___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_102___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_103 (0x005EC19C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_103___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_103___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_103__RX_DCOC_RANGE_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_103__RX_DCOC_RES_I_103___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_103__RX_DCOC_RES_Q_103___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_103__RX_DCOC_RANGE_103___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_103__RX_DCOC_RANGE_103___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_103__RX_DCOC_RES_I_103___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_103__RX_DCOC_RES_I_103___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_103__RX_DCOC_RES_Q_103___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_103__RX_DCOC_RES_Q_103___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_103___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_103___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_104 (0x005EC1A0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_104___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_104___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_104__RX_DCOC_RANGE_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_104__RX_DCOC_RES_I_104___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_104__RX_DCOC_RES_Q_104___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_104__RX_DCOC_RANGE_104___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_104__RX_DCOC_RANGE_104___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_104__RX_DCOC_RES_I_104___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_104__RX_DCOC_RES_I_104___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_104__RX_DCOC_RES_Q_104___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_104__RX_DCOC_RES_Q_104___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_104___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_104___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_105 (0x005EC1A4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_105___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_105___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_105__RX_DCOC_RANGE_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_105__RX_DCOC_RES_I_105___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_105__RX_DCOC_RES_Q_105___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_105__RX_DCOC_RANGE_105___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_105__RX_DCOC_RANGE_105___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_105__RX_DCOC_RES_I_105___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_105__RX_DCOC_RES_I_105___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_105__RX_DCOC_RES_Q_105___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_105__RX_DCOC_RES_Q_105___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_105___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_105___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_106 (0x005EC1A8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_106___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_106___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_106__RX_DCOC_RANGE_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_106__RX_DCOC_RES_I_106___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_106__RX_DCOC_RES_Q_106___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_106__RX_DCOC_RANGE_106___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_106__RX_DCOC_RANGE_106___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_106__RX_DCOC_RES_I_106___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_106__RX_DCOC_RES_I_106___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_106__RX_DCOC_RES_Q_106___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_106__RX_DCOC_RES_Q_106___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_106___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_106___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_107 (0x005EC1AC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_107___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_107___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_107__RX_DCOC_RANGE_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_107__RX_DCOC_RES_I_107___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_107__RX_DCOC_RES_Q_107___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_107__RX_DCOC_RANGE_107___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_107__RX_DCOC_RANGE_107___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_107__RX_DCOC_RES_I_107___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_107__RX_DCOC_RES_I_107___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_107__RX_DCOC_RES_Q_107___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_107__RX_DCOC_RES_Q_107___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_107___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_107___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_108 (0x005EC1B0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_108___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_108___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_108__RX_DCOC_RANGE_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_108__RX_DCOC_RES_I_108___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_108__RX_DCOC_RES_Q_108___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_108__RX_DCOC_RANGE_108___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_108__RX_DCOC_RANGE_108___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_108__RX_DCOC_RES_I_108___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_108__RX_DCOC_RES_I_108___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_108__RX_DCOC_RES_Q_108___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_108__RX_DCOC_RES_Q_108___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_108___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_108___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_109 (0x005EC1B4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_109___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_109___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_109__RX_DCOC_RANGE_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_109__RX_DCOC_RES_I_109___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_109__RX_DCOC_RES_Q_109___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_109__RX_DCOC_RANGE_109___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_109__RX_DCOC_RANGE_109___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_109__RX_DCOC_RES_I_109___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_109__RX_DCOC_RES_I_109___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_109__RX_DCOC_RES_Q_109___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_109__RX_DCOC_RES_Q_109___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_109___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_109___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_110 (0x005EC1B8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_110___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_110___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_110__RX_DCOC_RANGE_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_110__RX_DCOC_RES_I_110___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_110__RX_DCOC_RES_Q_110___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_110__RX_DCOC_RANGE_110___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_110__RX_DCOC_RANGE_110___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_110__RX_DCOC_RES_I_110___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_110__RX_DCOC_RES_I_110___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_110__RX_DCOC_RES_Q_110___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_110__RX_DCOC_RES_Q_110___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_110___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_110___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_111 (0x005EC1BC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_111___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_111___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_111__RX_DCOC_RANGE_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_111__RX_DCOC_RES_I_111___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_111__RX_DCOC_RES_Q_111___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_111__RX_DCOC_RANGE_111___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_111__RX_DCOC_RANGE_111___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_111__RX_DCOC_RES_I_111___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_111__RX_DCOC_RES_I_111___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_111__RX_DCOC_RES_Q_111___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_111__RX_DCOC_RES_Q_111___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_111___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_111___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_112 (0x005EC1C0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_112___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_112___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_112__RX_DCOC_RANGE_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_112__RX_DCOC_RES_I_112___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_112__RX_DCOC_RES_Q_112___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_112__RX_DCOC_RANGE_112___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_112__RX_DCOC_RANGE_112___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_112__RX_DCOC_RES_I_112___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_112__RX_DCOC_RES_I_112___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_112__RX_DCOC_RES_Q_112___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_112__RX_DCOC_RES_Q_112___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_112___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_112___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_113 (0x005EC1C4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_113___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_113___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_113__RX_DCOC_RANGE_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_113__RX_DCOC_RES_I_113___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_113__RX_DCOC_RES_Q_113___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_113__RX_DCOC_RANGE_113___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_113__RX_DCOC_RANGE_113___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_113__RX_DCOC_RES_I_113___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_113__RX_DCOC_RES_I_113___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_113__RX_DCOC_RES_Q_113___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_113__RX_DCOC_RES_Q_113___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_113___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_113___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_114 (0x005EC1C8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_114___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_114___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_114__RX_DCOC_RANGE_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_114__RX_DCOC_RES_I_114___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_114__RX_DCOC_RES_Q_114___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_114__RX_DCOC_RANGE_114___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_114__RX_DCOC_RANGE_114___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_114__RX_DCOC_RES_I_114___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_114__RX_DCOC_RES_I_114___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_114__RX_DCOC_RES_Q_114___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_114__RX_DCOC_RES_Q_114___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_114___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_114___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_115 (0x005EC1CC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_115___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_115___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_115__RX_DCOC_RANGE_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_115__RX_DCOC_RES_I_115___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_115__RX_DCOC_RES_Q_115___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_115__RX_DCOC_RANGE_115___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_115__RX_DCOC_RANGE_115___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_115__RX_DCOC_RES_I_115___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_115__RX_DCOC_RES_I_115___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_115__RX_DCOC_RES_Q_115___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_115__RX_DCOC_RES_Q_115___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_115___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_115___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_116 (0x005EC1D0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_116___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_116___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_116__RX_DCOC_RANGE_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_116__RX_DCOC_RES_I_116___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_116__RX_DCOC_RES_Q_116___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_116__RX_DCOC_RANGE_116___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_116__RX_DCOC_RANGE_116___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_116__RX_DCOC_RES_I_116___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_116__RX_DCOC_RES_I_116___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_116__RX_DCOC_RES_Q_116___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_116__RX_DCOC_RES_Q_116___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_116___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_116___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_117 (0x005EC1D4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_117___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_117___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_117__RX_DCOC_RANGE_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_117__RX_DCOC_RES_I_117___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_117__RX_DCOC_RES_Q_117___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_117__RX_DCOC_RANGE_117___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_117__RX_DCOC_RANGE_117___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_117__RX_DCOC_RES_I_117___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_117__RX_DCOC_RES_I_117___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_117__RX_DCOC_RES_Q_117___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_117__RX_DCOC_RES_Q_117___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_117___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_117___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_118 (0x005EC1D8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_118___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_118___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_118__RX_DCOC_RANGE_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_118__RX_DCOC_RES_I_118___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_118__RX_DCOC_RES_Q_118___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_118__RX_DCOC_RANGE_118___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_118__RX_DCOC_RANGE_118___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_118__RX_DCOC_RES_I_118___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_118__RX_DCOC_RES_I_118___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_118__RX_DCOC_RES_Q_118___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_118__RX_DCOC_RES_Q_118___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_118___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_118___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_119 (0x005EC1DC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_119___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_119___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_119__RX_DCOC_RANGE_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_119__RX_DCOC_RES_I_119___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_119__RX_DCOC_RES_Q_119___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_119__RX_DCOC_RANGE_119___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_119__RX_DCOC_RANGE_119___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_119__RX_DCOC_RES_I_119___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_119__RX_DCOC_RES_I_119___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_119__RX_DCOC_RES_Q_119___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_119__RX_DCOC_RES_Q_119___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_119___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_119___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_120 (0x005EC1E0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_120___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_120___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_120__RX_DCOC_RANGE_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_120__RX_DCOC_RES_I_120___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_120__RX_DCOC_RES_Q_120___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_120__RX_DCOC_RANGE_120___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_120__RX_DCOC_RANGE_120___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_120__RX_DCOC_RES_I_120___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_120__RX_DCOC_RES_I_120___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_120__RX_DCOC_RES_Q_120___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_120__RX_DCOC_RES_Q_120___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_120___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_120___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_121 (0x005EC1E4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_121___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_121___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_121__RX_DCOC_RANGE_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_121__RX_DCOC_RES_I_121___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_121__RX_DCOC_RES_Q_121___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_121__RX_DCOC_RANGE_121___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_121__RX_DCOC_RANGE_121___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_121__RX_DCOC_RES_I_121___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_121__RX_DCOC_RES_I_121___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_121__RX_DCOC_RES_Q_121___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_121__RX_DCOC_RES_Q_121___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_121___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_121___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_122 (0x005EC1E8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_122___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_122___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_122__RX_DCOC_RANGE_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_122__RX_DCOC_RES_I_122___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_122__RX_DCOC_RES_Q_122___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_122__RX_DCOC_RANGE_122___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_122__RX_DCOC_RANGE_122___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_122__RX_DCOC_RES_I_122___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_122__RX_DCOC_RES_I_122___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_122__RX_DCOC_RES_Q_122___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_122__RX_DCOC_RES_Q_122___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_122___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_122___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_123 (0x005EC1EC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_123___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_123___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_123__RX_DCOC_RANGE_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_123__RX_DCOC_RES_I_123___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_123__RX_DCOC_RES_Q_123___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_123__RX_DCOC_RANGE_123___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_123__RX_DCOC_RANGE_123___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_123__RX_DCOC_RES_I_123___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_123__RX_DCOC_RES_I_123___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_123__RX_DCOC_RES_Q_123___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_123__RX_DCOC_RES_Q_123___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_123___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_123___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_124 (0x005EC1F0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_124___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_124___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_124__RX_DCOC_RANGE_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_124__RX_DCOC_RES_I_124___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_124__RX_DCOC_RES_Q_124___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_124__RX_DCOC_RANGE_124___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_124__RX_DCOC_RANGE_124___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_124__RX_DCOC_RES_I_124___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_124__RX_DCOC_RES_I_124___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_124__RX_DCOC_RES_Q_124___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_124__RX_DCOC_RES_Q_124___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_124___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_124___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_125 (0x005EC1F4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_125___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_125___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_125__RX_DCOC_RANGE_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_125__RX_DCOC_RES_I_125___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_125__RX_DCOC_RES_Q_125___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_125__RX_DCOC_RANGE_125___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_125__RX_DCOC_RANGE_125___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_125__RX_DCOC_RES_I_125___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_125__RX_DCOC_RES_I_125___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_125__RX_DCOC_RES_Q_125___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_125__RX_DCOC_RES_Q_125___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_125___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_125___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_126 (0x005EC1F8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_126___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_126___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_126__RX_DCOC_RANGE_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_126__RX_DCOC_RES_I_126___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_126__RX_DCOC_RES_Q_126___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_126__RX_DCOC_RANGE_126___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_126__RX_DCOC_RANGE_126___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_126__RX_DCOC_RES_I_126___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_126__RX_DCOC_RES_I_126___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_126__RX_DCOC_RES_Q_126___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_126__RX_DCOC_RES_Q_126___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_126___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_126___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_127 (0x005EC1FC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_127___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_127___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_127__RX_DCOC_RANGE_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_127__RX_DCOC_RES_I_127___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_127__RX_DCOC_RES_Q_127___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_127__RX_DCOC_RANGE_127___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_127__RX_DCOC_RANGE_127___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_127__RX_DCOC_RES_I_127___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_127__RX_DCOC_RES_I_127___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_127__RX_DCOC_RES_Q_127___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_127__RX_DCOC_RES_Q_127___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_127___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_127___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_128 (0x005EC200) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_128___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_128___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_128__RX_DCOC_RANGE_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_128__RX_DCOC_RES_I_128___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_128__RX_DCOC_RES_Q_128___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_128__RX_DCOC_RANGE_128___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_128__RX_DCOC_RANGE_128___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_128__RX_DCOC_RES_I_128___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_128__RX_DCOC_RES_I_128___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_128__RX_DCOC_RES_Q_128___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_128__RX_DCOC_RES_Q_128___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_128___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_128___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_129 (0x005EC204) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_129___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_129___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_129__RX_DCOC_RANGE_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_129__RX_DCOC_RES_I_129___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_129__RX_DCOC_RES_Q_129___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_129__RX_DCOC_RANGE_129___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_129__RX_DCOC_RANGE_129___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_129__RX_DCOC_RES_I_129___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_129__RX_DCOC_RES_I_129___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_129__RX_DCOC_RES_Q_129___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_129__RX_DCOC_RES_Q_129___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_129___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_129___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_130 (0x005EC208) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_130___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_130___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_130__RX_DCOC_RANGE_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_130__RX_DCOC_RES_I_130___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_130__RX_DCOC_RES_Q_130___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_130__RX_DCOC_RANGE_130___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_130__RX_DCOC_RANGE_130___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_130__RX_DCOC_RES_I_130___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_130__RX_DCOC_RES_I_130___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_130__RX_DCOC_RES_Q_130___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_130__RX_DCOC_RES_Q_130___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_130___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_130___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_131 (0x005EC20C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_131___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_131___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_131__RX_DCOC_RANGE_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_131__RX_DCOC_RES_I_131___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_131__RX_DCOC_RES_Q_131___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_131__RX_DCOC_RANGE_131___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_131__RX_DCOC_RANGE_131___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_131__RX_DCOC_RES_I_131___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_131__RX_DCOC_RES_I_131___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_131__RX_DCOC_RES_Q_131___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_131__RX_DCOC_RES_Q_131___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_131___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_131___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_132 (0x005EC210) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_132___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_132___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_132__RX_DCOC_RANGE_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_132__RX_DCOC_RES_I_132___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_132__RX_DCOC_RES_Q_132___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_132__RX_DCOC_RANGE_132___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_132__RX_DCOC_RANGE_132___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_132__RX_DCOC_RES_I_132___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_132__RX_DCOC_RES_I_132___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_132__RX_DCOC_RES_Q_132___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_132__RX_DCOC_RES_Q_132___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_132___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_132___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_133 (0x005EC214) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_133___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_133___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_133__RX_DCOC_RANGE_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_133__RX_DCOC_RES_I_133___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_133__RX_DCOC_RES_Q_133___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_133__RX_DCOC_RANGE_133___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_133__RX_DCOC_RANGE_133___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_133__RX_DCOC_RES_I_133___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_133__RX_DCOC_RES_I_133___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_133__RX_DCOC_RES_Q_133___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_133__RX_DCOC_RES_Q_133___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_133___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_133___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_134 (0x005EC218) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_134___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_134___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_134__RX_DCOC_RANGE_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_134__RX_DCOC_RES_I_134___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_134__RX_DCOC_RES_Q_134___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_134__RX_DCOC_RANGE_134___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_134__RX_DCOC_RANGE_134___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_134__RX_DCOC_RES_I_134___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_134__RX_DCOC_RES_I_134___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_134__RX_DCOC_RES_Q_134___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_134__RX_DCOC_RES_Q_134___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_134___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_134___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_135 (0x005EC21C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_135___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_135___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_135__RX_DCOC_RANGE_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_135__RX_DCOC_RES_I_135___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_135__RX_DCOC_RES_Q_135___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_135__RX_DCOC_RANGE_135___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_135__RX_DCOC_RANGE_135___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_135__RX_DCOC_RES_I_135___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_135__RX_DCOC_RES_I_135___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_135__RX_DCOC_RES_Q_135___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_135__RX_DCOC_RES_Q_135___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_135___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_135___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_136 (0x005EC220) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_136___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_136___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_136__RX_DCOC_RANGE_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_136__RX_DCOC_RES_I_136___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_136__RX_DCOC_RES_Q_136___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_136__RX_DCOC_RANGE_136___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_136__RX_DCOC_RANGE_136___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_136__RX_DCOC_RES_I_136___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_136__RX_DCOC_RES_I_136___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_136__RX_DCOC_RES_Q_136___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_136__RX_DCOC_RES_Q_136___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_136___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_136___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_137 (0x005EC224) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_137___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_137___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_137__RX_DCOC_RANGE_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_137__RX_DCOC_RES_I_137___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_137__RX_DCOC_RES_Q_137___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_137__RX_DCOC_RANGE_137___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_137__RX_DCOC_RANGE_137___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_137__RX_DCOC_RES_I_137___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_137__RX_DCOC_RES_I_137___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_137__RX_DCOC_RES_Q_137___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_137__RX_DCOC_RES_Q_137___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_137___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_137___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_138 (0x005EC228) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_138___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_138___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_138__RX_DCOC_RANGE_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_138__RX_DCOC_RES_I_138___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_138__RX_DCOC_RES_Q_138___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_138__RX_DCOC_RANGE_138___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_138__RX_DCOC_RANGE_138___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_138__RX_DCOC_RES_I_138___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_138__RX_DCOC_RES_I_138___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_138__RX_DCOC_RES_Q_138___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_138__RX_DCOC_RES_Q_138___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_138___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_138___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_139 (0x005EC22C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_139___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_139___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_139__RX_DCOC_RANGE_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_139__RX_DCOC_RES_I_139___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_139__RX_DCOC_RES_Q_139___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_139__RX_DCOC_RANGE_139___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_139__RX_DCOC_RANGE_139___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_139__RX_DCOC_RES_I_139___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_139__RX_DCOC_RES_I_139___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_139__RX_DCOC_RES_Q_139___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_139__RX_DCOC_RES_Q_139___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_139___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_139___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_140 (0x005EC230) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_140___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_140___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_140__RX_DCOC_RANGE_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_140__RX_DCOC_RES_I_140___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_140__RX_DCOC_RES_Q_140___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_140__RX_DCOC_RANGE_140___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_140__RX_DCOC_RANGE_140___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_140__RX_DCOC_RES_I_140___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_140__RX_DCOC_RES_I_140___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_140__RX_DCOC_RES_Q_140___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_140__RX_DCOC_RES_Q_140___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_140___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_140___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_141 (0x005EC234) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_141___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_141___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_141__RX_DCOC_RANGE_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_141__RX_DCOC_RES_I_141___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_141__RX_DCOC_RES_Q_141___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_141__RX_DCOC_RANGE_141___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_141__RX_DCOC_RANGE_141___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_141__RX_DCOC_RES_I_141___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_141__RX_DCOC_RES_I_141___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_141__RX_DCOC_RES_Q_141___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_141__RX_DCOC_RES_Q_141___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_141___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_141___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_142 (0x005EC238) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_142___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_142___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_142__RX_DCOC_RANGE_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_142__RX_DCOC_RES_I_142___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_142__RX_DCOC_RES_Q_142___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_142__RX_DCOC_RANGE_142___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_142__RX_DCOC_RANGE_142___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_142__RX_DCOC_RES_I_142___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_142__RX_DCOC_RES_I_142___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_142__RX_DCOC_RES_Q_142___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_142__RX_DCOC_RES_Q_142___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_142___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_142___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_143 (0x005EC23C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_143___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_143___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_143__RX_DCOC_RANGE_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_143__RX_DCOC_RES_I_143___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_143__RX_DCOC_RES_Q_143___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_143__RX_DCOC_RANGE_143___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_143__RX_DCOC_RANGE_143___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_143__RX_DCOC_RES_I_143___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_143__RX_DCOC_RES_I_143___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_143__RX_DCOC_RES_Q_143___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_143__RX_DCOC_RES_Q_143___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_143___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_143___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_144 (0x005EC240) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_144___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_144___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_144__RX_DCOC_RANGE_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_144__RX_DCOC_RES_I_144___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_144__RX_DCOC_RES_Q_144___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_144__RX_DCOC_RANGE_144___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_144__RX_DCOC_RANGE_144___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_144__RX_DCOC_RES_I_144___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_144__RX_DCOC_RES_I_144___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_144__RX_DCOC_RES_Q_144___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_144__RX_DCOC_RES_Q_144___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_144___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_144___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_145 (0x005EC244) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_145___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_145___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_145__RX_DCOC_RANGE_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_145__RX_DCOC_RES_I_145___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_145__RX_DCOC_RES_Q_145___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_145__RX_DCOC_RANGE_145___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_145__RX_DCOC_RANGE_145___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_145__RX_DCOC_RES_I_145___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_145__RX_DCOC_RES_I_145___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_145__RX_DCOC_RES_Q_145___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_145__RX_DCOC_RES_Q_145___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_145___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_145___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_146 (0x005EC248) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_146___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_146___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_146__RX_DCOC_RANGE_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_146__RX_DCOC_RES_I_146___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_146__RX_DCOC_RES_Q_146___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_146__RX_DCOC_RANGE_146___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_146__RX_DCOC_RANGE_146___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_146__RX_DCOC_RES_I_146___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_146__RX_DCOC_RES_I_146___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_146__RX_DCOC_RES_Q_146___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_146__RX_DCOC_RES_Q_146___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_146___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_146___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_147 (0x005EC24C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_147___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_147___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_147__RX_DCOC_RANGE_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_147__RX_DCOC_RES_I_147___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_147__RX_DCOC_RES_Q_147___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_147__RX_DCOC_RANGE_147___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_147__RX_DCOC_RANGE_147___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_147__RX_DCOC_RES_I_147___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_147__RX_DCOC_RES_I_147___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_147__RX_DCOC_RES_Q_147___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_147__RX_DCOC_RES_Q_147___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_147___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_147___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_148 (0x005EC250) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_148___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_148___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_148__RX_DCOC_RANGE_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_148__RX_DCOC_RES_I_148___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_148__RX_DCOC_RES_Q_148___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_148__RX_DCOC_RANGE_148___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_148__RX_DCOC_RANGE_148___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_148__RX_DCOC_RES_I_148___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_148__RX_DCOC_RES_I_148___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_148__RX_DCOC_RES_Q_148___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_148__RX_DCOC_RES_Q_148___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_148___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_148___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_149 (0x005EC254) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_149___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_149___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_149__RX_DCOC_RANGE_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_149__RX_DCOC_RES_I_149___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_149__RX_DCOC_RES_Q_149___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_149__RX_DCOC_RANGE_149___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_149__RX_DCOC_RANGE_149___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_149__RX_DCOC_RES_I_149___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_149__RX_DCOC_RES_I_149___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_149__RX_DCOC_RES_Q_149___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_149__RX_DCOC_RES_Q_149___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_149___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_149___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_150 (0x005EC258) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_150___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_150___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_150__RX_DCOC_RANGE_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_150__RX_DCOC_RES_I_150___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_150__RX_DCOC_RES_Q_150___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_150__RX_DCOC_RANGE_150___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_150__RX_DCOC_RANGE_150___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_150__RX_DCOC_RES_I_150___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_150__RX_DCOC_RES_I_150___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_150__RX_DCOC_RES_Q_150___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_150__RX_DCOC_RES_Q_150___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_150___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_150___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_151 (0x005EC25C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_151___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_151___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_151__RX_DCOC_RANGE_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_151__RX_DCOC_RES_I_151___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_151__RX_DCOC_RES_Q_151___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_151__RX_DCOC_RANGE_151___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_151__RX_DCOC_RANGE_151___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_151__RX_DCOC_RES_I_151___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_151__RX_DCOC_RES_I_151___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_151__RX_DCOC_RES_Q_151___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_151__RX_DCOC_RES_Q_151___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_151___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_151___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_152 (0x005EC260) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_152___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_152___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_152__RX_DCOC_RANGE_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_152__RX_DCOC_RES_I_152___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_152__RX_DCOC_RES_Q_152___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_152__RX_DCOC_RANGE_152___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_152__RX_DCOC_RANGE_152___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_152__RX_DCOC_RES_I_152___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_152__RX_DCOC_RES_I_152___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_152__RX_DCOC_RES_Q_152___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_152__RX_DCOC_RES_Q_152___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_152___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_152___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_153 (0x005EC264) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_153___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_153___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_153__RX_DCOC_RANGE_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_153__RX_DCOC_RES_I_153___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_153__RX_DCOC_RES_Q_153___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_153__RX_DCOC_RANGE_153___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_153__RX_DCOC_RANGE_153___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_153__RX_DCOC_RES_I_153___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_153__RX_DCOC_RES_I_153___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_153__RX_DCOC_RES_Q_153___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_153__RX_DCOC_RES_Q_153___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_153___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_153___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_154 (0x005EC268) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_154___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_154___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_154__RX_DCOC_RANGE_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_154__RX_DCOC_RES_I_154___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_154__RX_DCOC_RES_Q_154___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_154__RX_DCOC_RANGE_154___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_154__RX_DCOC_RANGE_154___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_154__RX_DCOC_RES_I_154___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_154__RX_DCOC_RES_I_154___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_154__RX_DCOC_RES_Q_154___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_154__RX_DCOC_RES_Q_154___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_154___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_154___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_155 (0x005EC26C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_155___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_155___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_155__RX_DCOC_RANGE_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_155__RX_DCOC_RES_I_155___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_155__RX_DCOC_RES_Q_155___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_155__RX_DCOC_RANGE_155___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_155__RX_DCOC_RANGE_155___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_155__RX_DCOC_RES_I_155___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_155__RX_DCOC_RES_I_155___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_155__RX_DCOC_RES_Q_155___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_155__RX_DCOC_RES_Q_155___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_155___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_155___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_156 (0x005EC270) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_156___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_156___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_156__RX_DCOC_RANGE_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_156__RX_DCOC_RES_I_156___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_156__RX_DCOC_RES_Q_156___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_156__RX_DCOC_RANGE_156___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_156__RX_DCOC_RANGE_156___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_156__RX_DCOC_RES_I_156___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_156__RX_DCOC_RES_I_156___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_156__RX_DCOC_RES_Q_156___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_156__RX_DCOC_RES_Q_156___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_156___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_156___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_157 (0x005EC274) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_157___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_157___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_157__RX_DCOC_RANGE_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_157__RX_DCOC_RES_I_157___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_157__RX_DCOC_RES_Q_157___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_157__RX_DCOC_RANGE_157___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_157__RX_DCOC_RANGE_157___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_157__RX_DCOC_RES_I_157___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_157__RX_DCOC_RES_I_157___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_157__RX_DCOC_RES_Q_157___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_157__RX_DCOC_RES_Q_157___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_157___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_157___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_158 (0x005EC278) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_158___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_158___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_158__RX_DCOC_RANGE_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_158__RX_DCOC_RES_I_158___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_158__RX_DCOC_RES_Q_158___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_158__RX_DCOC_RANGE_158___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_158__RX_DCOC_RANGE_158___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_158__RX_DCOC_RES_I_158___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_158__RX_DCOC_RES_I_158___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_158__RX_DCOC_RES_Q_158___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_158__RX_DCOC_RES_Q_158___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_158___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_158___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_159 (0x005EC27C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_159___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_159___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_159__RX_DCOC_RANGE_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_159__RX_DCOC_RES_I_159___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_159__RX_DCOC_RES_Q_159___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_159__RX_DCOC_RANGE_159___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_159__RX_DCOC_RANGE_159___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_159__RX_DCOC_RES_I_159___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_159__RX_DCOC_RES_I_159___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_159__RX_DCOC_RES_Q_159___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_159__RX_DCOC_RES_Q_159___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_159___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_159___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_160 (0x005EC280) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_160___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_160___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_160__RX_DCOC_RANGE_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_160__RX_DCOC_RES_I_160___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_160__RX_DCOC_RES_Q_160___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_160__RX_DCOC_RANGE_160___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_160__RX_DCOC_RANGE_160___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_160__RX_DCOC_RES_I_160___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_160__RX_DCOC_RES_I_160___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_160__RX_DCOC_RES_Q_160___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_160__RX_DCOC_RES_Q_160___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_160___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_160___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_161 (0x005EC284) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_161___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_161___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_161__RX_DCOC_RANGE_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_161__RX_DCOC_RES_I_161___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_161__RX_DCOC_RES_Q_161___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_161__RX_DCOC_RANGE_161___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_161__RX_DCOC_RANGE_161___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_161__RX_DCOC_RES_I_161___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_161__RX_DCOC_RES_I_161___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_161__RX_DCOC_RES_Q_161___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_161__RX_DCOC_RES_Q_161___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_161___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_161___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_162 (0x005EC288) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_162___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_162___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_162__RX_DCOC_RANGE_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_162__RX_DCOC_RES_I_162___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_162__RX_DCOC_RES_Q_162___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_162__RX_DCOC_RANGE_162___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_162__RX_DCOC_RANGE_162___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_162__RX_DCOC_RES_I_162___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_162__RX_DCOC_RES_I_162___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_162__RX_DCOC_RES_Q_162___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_162__RX_DCOC_RES_Q_162___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_162___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_162___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_163 (0x005EC28C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_163___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_163___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_163__RX_DCOC_RANGE_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_163__RX_DCOC_RES_I_163___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_163__RX_DCOC_RES_Q_163___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_163__RX_DCOC_RANGE_163___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_163__RX_DCOC_RANGE_163___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_163__RX_DCOC_RES_I_163___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_163__RX_DCOC_RES_I_163___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_163__RX_DCOC_RES_Q_163___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_163__RX_DCOC_RES_Q_163___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_163___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_163___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_164 (0x005EC290) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_164___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_164___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_164__RX_DCOC_RANGE_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_164__RX_DCOC_RES_I_164___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_164__RX_DCOC_RES_Q_164___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_164__RX_DCOC_RANGE_164___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_164__RX_DCOC_RANGE_164___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_164__RX_DCOC_RES_I_164___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_164__RX_DCOC_RES_I_164___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_164__RX_DCOC_RES_Q_164___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_164__RX_DCOC_RES_Q_164___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_164___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_164___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_165 (0x005EC294) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_165___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_165___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_165__RX_DCOC_RANGE_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_165__RX_DCOC_RES_I_165___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_165__RX_DCOC_RES_Q_165___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_165__RX_DCOC_RANGE_165___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_165__RX_DCOC_RANGE_165___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_165__RX_DCOC_RES_I_165___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_165__RX_DCOC_RES_I_165___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_165__RX_DCOC_RES_Q_165___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_165__RX_DCOC_RES_Q_165___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_165___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_165___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_166 (0x005EC298) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_166___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_166___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_166__RX_DCOC_RANGE_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_166__RX_DCOC_RES_I_166___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_166__RX_DCOC_RES_Q_166___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_166__RX_DCOC_RANGE_166___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_166__RX_DCOC_RANGE_166___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_166__RX_DCOC_RES_I_166___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_166__RX_DCOC_RES_I_166___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_166__RX_DCOC_RES_Q_166___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_166__RX_DCOC_RES_Q_166___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_166___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_166___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_167 (0x005EC29C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_167___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_167___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_167__RX_DCOC_RANGE_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_167__RX_DCOC_RES_I_167___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_167__RX_DCOC_RES_Q_167___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_167__RX_DCOC_RANGE_167___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_167__RX_DCOC_RANGE_167___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_167__RX_DCOC_RES_I_167___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_167__RX_DCOC_RES_I_167___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_167__RX_DCOC_RES_Q_167___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_167__RX_DCOC_RES_Q_167___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_167___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_167___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_168 (0x005EC2A0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_168___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_168___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_168__RX_DCOC_RANGE_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_168__RX_DCOC_RES_I_168___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_168__RX_DCOC_RES_Q_168___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_168__RX_DCOC_RANGE_168___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_168__RX_DCOC_RANGE_168___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_168__RX_DCOC_RES_I_168___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_168__RX_DCOC_RES_I_168___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_168__RX_DCOC_RES_Q_168___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_168__RX_DCOC_RES_Q_168___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_168___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_168___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_169 (0x005EC2A4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_169___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_169___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_169__RX_DCOC_RANGE_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_169__RX_DCOC_RES_I_169___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_169__RX_DCOC_RES_Q_169___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_169__RX_DCOC_RANGE_169___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_169__RX_DCOC_RANGE_169___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_169__RX_DCOC_RES_I_169___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_169__RX_DCOC_RES_I_169___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_169__RX_DCOC_RES_Q_169___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_169__RX_DCOC_RES_Q_169___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_169___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_169___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_170 (0x005EC2A8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_170___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_170___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_170__RX_DCOC_RANGE_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_170__RX_DCOC_RES_I_170___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_170__RX_DCOC_RES_Q_170___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_170__RX_DCOC_RANGE_170___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_170__RX_DCOC_RANGE_170___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_170__RX_DCOC_RES_I_170___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_170__RX_DCOC_RES_I_170___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_170__RX_DCOC_RES_Q_170___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_170__RX_DCOC_RES_Q_170___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_170___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_170___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_171 (0x005EC2AC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_171___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_171___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_171__RX_DCOC_RANGE_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_171__RX_DCOC_RES_I_171___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_171__RX_DCOC_RES_Q_171___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_171__RX_DCOC_RANGE_171___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_171__RX_DCOC_RANGE_171___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_171__RX_DCOC_RES_I_171___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_171__RX_DCOC_RES_I_171___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_171__RX_DCOC_RES_Q_171___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_171__RX_DCOC_RES_Q_171___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_171___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_171___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_172 (0x005EC2B0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_172___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_172___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_172__RX_DCOC_RANGE_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_172__RX_DCOC_RES_I_172___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_172__RX_DCOC_RES_Q_172___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_172__RX_DCOC_RANGE_172___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_172__RX_DCOC_RANGE_172___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_172__RX_DCOC_RES_I_172___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_172__RX_DCOC_RES_I_172___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_172__RX_DCOC_RES_Q_172___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_172__RX_DCOC_RES_Q_172___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_172___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_172___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_173 (0x005EC2B4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_173___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_173___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_173__RX_DCOC_RANGE_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_173__RX_DCOC_RES_I_173___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_173__RX_DCOC_RES_Q_173___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_173__RX_DCOC_RANGE_173___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_173__RX_DCOC_RANGE_173___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_173__RX_DCOC_RES_I_173___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_173__RX_DCOC_RES_I_173___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_173__RX_DCOC_RES_Q_173___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_173__RX_DCOC_RES_Q_173___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_173___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_173___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_174 (0x005EC2B8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_174___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_174___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_174__RX_DCOC_RANGE_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_174__RX_DCOC_RES_I_174___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_174__RX_DCOC_RES_Q_174___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_174__RX_DCOC_RANGE_174___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_174__RX_DCOC_RANGE_174___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_174__RX_DCOC_RES_I_174___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_174__RX_DCOC_RES_I_174___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_174__RX_DCOC_RES_Q_174___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_174__RX_DCOC_RES_Q_174___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_174___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_174___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_175 (0x005EC2BC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_175___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_175___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_175__RX_DCOC_RANGE_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_175__RX_DCOC_RES_I_175___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_175__RX_DCOC_RES_Q_175___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_175__RX_DCOC_RANGE_175___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_175__RX_DCOC_RANGE_175___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_175__RX_DCOC_RES_I_175___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_175__RX_DCOC_RES_I_175___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_175__RX_DCOC_RES_Q_175___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_175__RX_DCOC_RES_Q_175___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_175___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_175___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_176 (0x005EC2C0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_176___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_176___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_176__RX_DCOC_RANGE_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_176__RX_DCOC_RES_I_176___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_176__RX_DCOC_RES_Q_176___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_176__RX_DCOC_RANGE_176___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_176__RX_DCOC_RANGE_176___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_176__RX_DCOC_RES_I_176___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_176__RX_DCOC_RES_I_176___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_176__RX_DCOC_RES_Q_176___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_176__RX_DCOC_RES_Q_176___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_176___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_176___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_177 (0x005EC2C4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_177___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_177___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_177__RX_DCOC_RANGE_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_177__RX_DCOC_RES_I_177___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_177__RX_DCOC_RES_Q_177___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_177__RX_DCOC_RANGE_177___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_177__RX_DCOC_RANGE_177___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_177__RX_DCOC_RES_I_177___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_177__RX_DCOC_RES_I_177___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_177__RX_DCOC_RES_Q_177___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_177__RX_DCOC_RES_Q_177___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_177___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_177___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_178 (0x005EC2C8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_178___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_178___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_178__RX_DCOC_RANGE_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_178__RX_DCOC_RES_I_178___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_178__RX_DCOC_RES_Q_178___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_178__RX_DCOC_RANGE_178___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_178__RX_DCOC_RANGE_178___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_178__RX_DCOC_RES_I_178___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_178__RX_DCOC_RES_I_178___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_178__RX_DCOC_RES_Q_178___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_178__RX_DCOC_RES_Q_178___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_178___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_178___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_179 (0x005EC2CC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_179___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_179___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_179__RX_DCOC_RANGE_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_179__RX_DCOC_RES_I_179___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_179__RX_DCOC_RES_Q_179___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_179__RX_DCOC_RANGE_179___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_179__RX_DCOC_RANGE_179___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_179__RX_DCOC_RES_I_179___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_179__RX_DCOC_RES_I_179___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_179__RX_DCOC_RES_Q_179___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_179__RX_DCOC_RES_Q_179___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_179___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_179___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_180 (0x005EC2D0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_180___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_180___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_180__RX_DCOC_RANGE_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_180__RX_DCOC_RES_I_180___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_180__RX_DCOC_RES_Q_180___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_180__RX_DCOC_RANGE_180___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_180__RX_DCOC_RANGE_180___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_180__RX_DCOC_RES_I_180___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_180__RX_DCOC_RES_I_180___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_180__RX_DCOC_RES_Q_180___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_180__RX_DCOC_RES_Q_180___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_180___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_180___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_181 (0x005EC2D4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_181___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_181___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_181__RX_DCOC_RANGE_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_181__RX_DCOC_RES_I_181___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_181__RX_DCOC_RES_Q_181___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_181__RX_DCOC_RANGE_181___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_181__RX_DCOC_RANGE_181___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_181__RX_DCOC_RES_I_181___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_181__RX_DCOC_RES_I_181___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_181__RX_DCOC_RES_Q_181___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_181__RX_DCOC_RES_Q_181___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_181___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_181___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_182 (0x005EC2D8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_182___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_182___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_182__RX_DCOC_RANGE_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_182__RX_DCOC_RES_I_182___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_182__RX_DCOC_RES_Q_182___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_182__RX_DCOC_RANGE_182___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_182__RX_DCOC_RANGE_182___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_182__RX_DCOC_RES_I_182___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_182__RX_DCOC_RES_I_182___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_182__RX_DCOC_RES_Q_182___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_182__RX_DCOC_RES_Q_182___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_182___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_182___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_183 (0x005EC2DC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_183___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_183___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_183__RX_DCOC_RANGE_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_183__RX_DCOC_RES_I_183___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_183__RX_DCOC_RES_Q_183___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_183__RX_DCOC_RANGE_183___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_183__RX_DCOC_RANGE_183___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_183__RX_DCOC_RES_I_183___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_183__RX_DCOC_RES_I_183___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_183__RX_DCOC_RES_Q_183___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_183__RX_DCOC_RES_Q_183___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_183___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_183___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_184 (0x005EC2E0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_184___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_184___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_184__RX_DCOC_RANGE_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_184__RX_DCOC_RES_I_184___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_184__RX_DCOC_RES_Q_184___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_184__RX_DCOC_RANGE_184___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_184__RX_DCOC_RANGE_184___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_184__RX_DCOC_RES_I_184___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_184__RX_DCOC_RES_I_184___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_184__RX_DCOC_RES_Q_184___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_184__RX_DCOC_RES_Q_184___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_184___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_184___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_185 (0x005EC2E4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_185___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_185___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_185__RX_DCOC_RANGE_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_185__RX_DCOC_RES_I_185___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_185__RX_DCOC_RES_Q_185___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_185__RX_DCOC_RANGE_185___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_185__RX_DCOC_RANGE_185___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_185__RX_DCOC_RES_I_185___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_185__RX_DCOC_RES_I_185___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_185__RX_DCOC_RES_Q_185___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_185__RX_DCOC_RES_Q_185___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_185___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_185___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_186 (0x005EC2E8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_186___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_186___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_186__RX_DCOC_RANGE_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_186__RX_DCOC_RES_I_186___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_186__RX_DCOC_RES_Q_186___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_186__RX_DCOC_RANGE_186___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_186__RX_DCOC_RANGE_186___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_186__RX_DCOC_RES_I_186___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_186__RX_DCOC_RES_I_186___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_186__RX_DCOC_RES_Q_186___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_186__RX_DCOC_RES_Q_186___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_186___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_186___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_187 (0x005EC2EC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_187___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_187___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_187__RX_DCOC_RANGE_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_187__RX_DCOC_RES_I_187___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_187__RX_DCOC_RES_Q_187___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_187__RX_DCOC_RANGE_187___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_187__RX_DCOC_RANGE_187___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_187__RX_DCOC_RES_I_187___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_187__RX_DCOC_RES_I_187___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_187__RX_DCOC_RES_Q_187___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_187__RX_DCOC_RES_Q_187___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_187___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_187___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_188 (0x005EC2F0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_188___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_188___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_188__RX_DCOC_RANGE_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_188__RX_DCOC_RES_I_188___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_188__RX_DCOC_RES_Q_188___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_188__RX_DCOC_RANGE_188___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_188__RX_DCOC_RANGE_188___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_188__RX_DCOC_RES_I_188___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_188__RX_DCOC_RES_I_188___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_188__RX_DCOC_RES_Q_188___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_188__RX_DCOC_RES_Q_188___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_188___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_188___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_189 (0x005EC2F4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_189___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_189___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_189__RX_DCOC_RANGE_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_189__RX_DCOC_RES_I_189___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_189__RX_DCOC_RES_Q_189___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_189__RX_DCOC_RANGE_189___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_189__RX_DCOC_RANGE_189___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_189__RX_DCOC_RES_I_189___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_189__RX_DCOC_RES_I_189___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_189__RX_DCOC_RES_Q_189___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_189__RX_DCOC_RES_Q_189___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_189___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_189___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_190 (0x005EC2F8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_190___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_190___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_190__RX_DCOC_RANGE_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_190__RX_DCOC_RES_I_190___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_190__RX_DCOC_RES_Q_190___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_190__RX_DCOC_RANGE_190___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_190__RX_DCOC_RANGE_190___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_190__RX_DCOC_RES_I_190___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_190__RX_DCOC_RES_I_190___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_190__RX_DCOC_RES_Q_190___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_190__RX_DCOC_RES_Q_190___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_190___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_190___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_191 (0x005EC2FC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_191___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_191___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_191__RX_DCOC_RANGE_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_191__RX_DCOC_RES_I_191___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_191__RX_DCOC_RES_Q_191___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_191__RX_DCOC_RANGE_191___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_191__RX_DCOC_RANGE_191___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_191__RX_DCOC_RES_I_191___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_191__RX_DCOC_RES_I_191___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_191__RX_DCOC_RES_Q_191___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_191__RX_DCOC_RES_Q_191___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_191___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_191___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_192 (0x005EC300) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_192___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_192___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_192__RX_DCOC_RANGE_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_192__RX_DCOC_RES_I_192___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_192__RX_DCOC_RES_Q_192___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_192__RX_DCOC_RANGE_192___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_192__RX_DCOC_RANGE_192___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_192__RX_DCOC_RES_I_192___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_192__RX_DCOC_RES_I_192___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_192__RX_DCOC_RES_Q_192___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_192__RX_DCOC_RES_Q_192___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_192___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_192___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_193 (0x005EC304) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_193___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_193___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_193__RX_DCOC_RANGE_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_193__RX_DCOC_RES_I_193___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_193__RX_DCOC_RES_Q_193___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_193__RX_DCOC_RANGE_193___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_193__RX_DCOC_RANGE_193___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_193__RX_DCOC_RES_I_193___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_193__RX_DCOC_RES_I_193___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_193__RX_DCOC_RES_Q_193___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_193__RX_DCOC_RES_Q_193___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_193___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_193___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_194 (0x005EC308) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_194___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_194___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_194__RX_DCOC_RANGE_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_194__RX_DCOC_RES_I_194___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_194__RX_DCOC_RES_Q_194___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_194__RX_DCOC_RANGE_194___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_194__RX_DCOC_RANGE_194___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_194__RX_DCOC_RES_I_194___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_194__RX_DCOC_RES_I_194___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_194__RX_DCOC_RES_Q_194___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_194__RX_DCOC_RES_Q_194___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_194___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_194___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_195 (0x005EC30C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_195___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_195___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_195__RX_DCOC_RANGE_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_195__RX_DCOC_RES_I_195___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_195__RX_DCOC_RES_Q_195___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_195__RX_DCOC_RANGE_195___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_195__RX_DCOC_RANGE_195___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_195__RX_DCOC_RES_I_195___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_195__RX_DCOC_RES_I_195___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_195__RX_DCOC_RES_Q_195___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_195__RX_DCOC_RES_Q_195___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_195___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_195___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_196 (0x005EC310) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_196___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_196___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_196__RX_DCOC_RANGE_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_196__RX_DCOC_RES_I_196___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_196__RX_DCOC_RES_Q_196___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_196__RX_DCOC_RANGE_196___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_196__RX_DCOC_RANGE_196___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_196__RX_DCOC_RES_I_196___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_196__RX_DCOC_RES_I_196___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_196__RX_DCOC_RES_Q_196___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_196__RX_DCOC_RES_Q_196___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_196___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_196___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_197 (0x005EC314) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_197___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_197___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_197__RX_DCOC_RANGE_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_197__RX_DCOC_RES_I_197___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_197__RX_DCOC_RES_Q_197___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_197__RX_DCOC_RANGE_197___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_197__RX_DCOC_RANGE_197___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_197__RX_DCOC_RES_I_197___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_197__RX_DCOC_RES_I_197___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_197__RX_DCOC_RES_Q_197___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_197__RX_DCOC_RES_Q_197___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_197___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_197___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_198 (0x005EC318) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_198___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_198___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_198__RX_DCOC_RANGE_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_198__RX_DCOC_RES_I_198___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_198__RX_DCOC_RES_Q_198___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_198__RX_DCOC_RANGE_198___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_198__RX_DCOC_RANGE_198___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_198__RX_DCOC_RES_I_198___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_198__RX_DCOC_RES_I_198___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_198__RX_DCOC_RES_Q_198___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_198__RX_DCOC_RES_Q_198___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_198___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_198___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_199 (0x005EC31C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_199___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_199___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_199__RX_DCOC_RANGE_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_199__RX_DCOC_RES_I_199___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_199__RX_DCOC_RES_Q_199___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_199__RX_DCOC_RANGE_199___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_199__RX_DCOC_RANGE_199___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_199__RX_DCOC_RES_I_199___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_199__RX_DCOC_RES_I_199___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_199__RX_DCOC_RES_Q_199___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_199__RX_DCOC_RES_Q_199___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_199___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_199___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_200 (0x005EC320) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_200___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_200___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_200__RX_DCOC_RANGE_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_200__RX_DCOC_RES_I_200___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_200__RX_DCOC_RES_Q_200___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_200__RX_DCOC_RANGE_200___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_200__RX_DCOC_RANGE_200___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_200__RX_DCOC_RES_I_200___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_200__RX_DCOC_RES_I_200___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_200__RX_DCOC_RES_Q_200___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_200__RX_DCOC_RES_Q_200___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_200___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_200___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_201 (0x005EC324) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_201___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_201___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_201__RX_DCOC_RANGE_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_201__RX_DCOC_RES_I_201___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_201__RX_DCOC_RES_Q_201___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_201__RX_DCOC_RANGE_201___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_201__RX_DCOC_RANGE_201___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_201__RX_DCOC_RES_I_201___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_201__RX_DCOC_RES_I_201___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_201__RX_DCOC_RES_Q_201___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_201__RX_DCOC_RES_Q_201___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_201___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_201___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_202 (0x005EC328) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_202___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_202___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_202__RX_DCOC_RANGE_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_202__RX_DCOC_RES_I_202___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_202__RX_DCOC_RES_Q_202___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_202__RX_DCOC_RANGE_202___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_202__RX_DCOC_RANGE_202___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_202__RX_DCOC_RES_I_202___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_202__RX_DCOC_RES_I_202___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_202__RX_DCOC_RES_Q_202___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_202__RX_DCOC_RES_Q_202___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_202___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_202___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_203 (0x005EC32C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_203___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_203___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_203__RX_DCOC_RANGE_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_203__RX_DCOC_RES_I_203___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_203__RX_DCOC_RES_Q_203___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_203__RX_DCOC_RANGE_203___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_203__RX_DCOC_RANGE_203___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_203__RX_DCOC_RES_I_203___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_203__RX_DCOC_RES_I_203___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_203__RX_DCOC_RES_Q_203___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_203__RX_DCOC_RES_Q_203___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_203___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_203___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_204 (0x005EC330) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_204___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_204___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_204__RX_DCOC_RANGE_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_204__RX_DCOC_RES_I_204___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_204__RX_DCOC_RES_Q_204___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_204__RX_DCOC_RANGE_204___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_204__RX_DCOC_RANGE_204___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_204__RX_DCOC_RES_I_204___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_204__RX_DCOC_RES_I_204___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_204__RX_DCOC_RES_Q_204___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_204__RX_DCOC_RES_Q_204___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_204___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_204___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_205 (0x005EC334) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_205___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_205___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_205__RX_DCOC_RANGE_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_205__RX_DCOC_RES_I_205___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_205__RX_DCOC_RES_Q_205___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_205__RX_DCOC_RANGE_205___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_205__RX_DCOC_RANGE_205___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_205__RX_DCOC_RES_I_205___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_205__RX_DCOC_RES_I_205___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_205__RX_DCOC_RES_Q_205___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_205__RX_DCOC_RES_Q_205___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_205___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_205___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_206 (0x005EC338) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_206___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_206___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_206__RX_DCOC_RANGE_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_206__RX_DCOC_RES_I_206___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_206__RX_DCOC_RES_Q_206___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_206__RX_DCOC_RANGE_206___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_206__RX_DCOC_RANGE_206___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_206__RX_DCOC_RES_I_206___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_206__RX_DCOC_RES_I_206___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_206__RX_DCOC_RES_Q_206___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_206__RX_DCOC_RES_Q_206___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_206___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_206___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_207 (0x005EC33C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_207___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_207___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_207__RX_DCOC_RANGE_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_207__RX_DCOC_RES_I_207___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_207__RX_DCOC_RES_Q_207___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_207__RX_DCOC_RANGE_207___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_207__RX_DCOC_RANGE_207___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_207__RX_DCOC_RES_I_207___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_207__RX_DCOC_RES_I_207___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_207__RX_DCOC_RES_Q_207___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_207__RX_DCOC_RES_Q_207___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_207___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_207___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_208 (0x005EC340) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_208___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_208___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_208__RX_DCOC_RANGE_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_208__RX_DCOC_RES_I_208___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_208__RX_DCOC_RES_Q_208___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_208__RX_DCOC_RANGE_208___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_208__RX_DCOC_RANGE_208___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_208__RX_DCOC_RES_I_208___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_208__RX_DCOC_RES_I_208___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_208__RX_DCOC_RES_Q_208___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_208__RX_DCOC_RES_Q_208___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_208___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_208___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_209 (0x005EC344) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_209___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_209___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_209__RX_DCOC_RANGE_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_209__RX_DCOC_RES_I_209___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_209__RX_DCOC_RES_Q_209___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_209__RX_DCOC_RANGE_209___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_209__RX_DCOC_RANGE_209___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_209__RX_DCOC_RES_I_209___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_209__RX_DCOC_RES_I_209___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_209__RX_DCOC_RES_Q_209___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_209__RX_DCOC_RES_Q_209___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_209___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_209___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_210 (0x005EC348) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_210___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_210___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_210__RX_DCOC_RANGE_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_210__RX_DCOC_RES_I_210___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_210__RX_DCOC_RES_Q_210___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_210__RX_DCOC_RANGE_210___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_210__RX_DCOC_RANGE_210___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_210__RX_DCOC_RES_I_210___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_210__RX_DCOC_RES_I_210___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_210__RX_DCOC_RES_Q_210___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_210__RX_DCOC_RES_Q_210___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_210___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_210___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_211 (0x005EC34C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_211___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_211___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_211__RX_DCOC_RANGE_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_211__RX_DCOC_RES_I_211___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_211__RX_DCOC_RES_Q_211___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_211__RX_DCOC_RANGE_211___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_211__RX_DCOC_RANGE_211___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_211__RX_DCOC_RES_I_211___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_211__RX_DCOC_RES_I_211___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_211__RX_DCOC_RES_Q_211___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_211__RX_DCOC_RES_Q_211___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_211___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_211___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_212 (0x005EC350) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_212___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_212___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_212__RX_DCOC_RANGE_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_212__RX_DCOC_RES_I_212___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_212__RX_DCOC_RES_Q_212___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_212__RX_DCOC_RANGE_212___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_212__RX_DCOC_RANGE_212___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_212__RX_DCOC_RES_I_212___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_212__RX_DCOC_RES_I_212___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_212__RX_DCOC_RES_Q_212___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_212__RX_DCOC_RES_Q_212___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_212___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_212___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_213 (0x005EC354) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_213___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_213___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_213__RX_DCOC_RANGE_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_213__RX_DCOC_RES_I_213___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_213__RX_DCOC_RES_Q_213___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_213__RX_DCOC_RANGE_213___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_213__RX_DCOC_RANGE_213___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_213__RX_DCOC_RES_I_213___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_213__RX_DCOC_RES_I_213___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_213__RX_DCOC_RES_Q_213___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_213__RX_DCOC_RES_Q_213___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_213___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_213___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_214 (0x005EC358) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_214___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_214___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_214__RX_DCOC_RANGE_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_214__RX_DCOC_RES_I_214___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_214__RX_DCOC_RES_Q_214___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_214__RX_DCOC_RANGE_214___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_214__RX_DCOC_RANGE_214___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_214__RX_DCOC_RES_I_214___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_214__RX_DCOC_RES_I_214___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_214__RX_DCOC_RES_Q_214___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_214__RX_DCOC_RES_Q_214___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_214___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_214___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_215 (0x005EC35C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_215___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_215___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_215__RX_DCOC_RANGE_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_215__RX_DCOC_RES_I_215___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_215__RX_DCOC_RES_Q_215___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_215__RX_DCOC_RANGE_215___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_215__RX_DCOC_RANGE_215___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_215__RX_DCOC_RES_I_215___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_215__RX_DCOC_RES_I_215___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_215__RX_DCOC_RES_Q_215___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_215__RX_DCOC_RES_Q_215___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_215___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_215___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_216 (0x005EC360) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_216___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_216___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_216__RX_DCOC_RANGE_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_216__RX_DCOC_RES_I_216___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_216__RX_DCOC_RES_Q_216___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_216__RX_DCOC_RANGE_216___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_216__RX_DCOC_RANGE_216___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_216__RX_DCOC_RES_I_216___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_216__RX_DCOC_RES_I_216___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_216__RX_DCOC_RES_Q_216___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_216__RX_DCOC_RES_Q_216___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_216___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_216___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_217 (0x005EC364) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_217___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_217___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_217__RX_DCOC_RANGE_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_217__RX_DCOC_RES_I_217___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_217__RX_DCOC_RES_Q_217___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_217__RX_DCOC_RANGE_217___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_217__RX_DCOC_RANGE_217___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_217__RX_DCOC_RES_I_217___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_217__RX_DCOC_RES_I_217___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_217__RX_DCOC_RES_Q_217___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_217__RX_DCOC_RES_Q_217___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_217___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_217___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_218 (0x005EC368) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_218___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_218___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_218__RX_DCOC_RANGE_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_218__RX_DCOC_RES_I_218___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_218__RX_DCOC_RES_Q_218___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_218__RX_DCOC_RANGE_218___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_218__RX_DCOC_RANGE_218___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_218__RX_DCOC_RES_I_218___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_218__RX_DCOC_RES_I_218___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_218__RX_DCOC_RES_Q_218___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_218__RX_DCOC_RES_Q_218___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_218___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_218___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_219 (0x005EC36C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_219___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_219___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_219__RX_DCOC_RANGE_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_219__RX_DCOC_RES_I_219___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_219__RX_DCOC_RES_Q_219___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_219__RX_DCOC_RANGE_219___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_219__RX_DCOC_RANGE_219___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_219__RX_DCOC_RES_I_219___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_219__RX_DCOC_RES_I_219___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_219__RX_DCOC_RES_Q_219___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_219__RX_DCOC_RES_Q_219___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_219___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_219___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_220 (0x005EC370) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_220___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_220___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_220__RX_DCOC_RANGE_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_220__RX_DCOC_RES_I_220___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_220__RX_DCOC_RES_Q_220___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_220__RX_DCOC_RANGE_220___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_220__RX_DCOC_RANGE_220___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_220__RX_DCOC_RES_I_220___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_220__RX_DCOC_RES_I_220___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_220__RX_DCOC_RES_Q_220___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_220__RX_DCOC_RES_Q_220___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_220___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_220___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_221 (0x005EC374) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_221___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_221___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_221__RX_DCOC_RANGE_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_221__RX_DCOC_RES_I_221___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_221__RX_DCOC_RES_Q_221___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_221__RX_DCOC_RANGE_221___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_221__RX_DCOC_RANGE_221___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_221__RX_DCOC_RES_I_221___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_221__RX_DCOC_RES_I_221___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_221__RX_DCOC_RES_Q_221___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_221__RX_DCOC_RES_Q_221___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_221___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_221___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_222 (0x005EC378) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_222___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_222___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_222__RX_DCOC_RANGE_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_222__RX_DCOC_RES_I_222___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_222__RX_DCOC_RES_Q_222___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_222__RX_DCOC_RANGE_222___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_222__RX_DCOC_RANGE_222___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_222__RX_DCOC_RES_I_222___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_222__RX_DCOC_RES_I_222___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_222__RX_DCOC_RES_Q_222___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_222__RX_DCOC_RES_Q_222___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_222___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_222___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_223 (0x005EC37C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_223___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_223___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_223__RX_DCOC_RANGE_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_223__RX_DCOC_RES_I_223___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_223__RX_DCOC_RES_Q_223___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_223__RX_DCOC_RANGE_223___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_223__RX_DCOC_RANGE_223___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_223__RX_DCOC_RES_I_223___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_223__RX_DCOC_RES_I_223___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_223__RX_DCOC_RES_Q_223___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_223__RX_DCOC_RES_Q_223___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_223___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_223___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_224 (0x005EC380) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_224___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_224___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_224__RX_DCOC_RANGE_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_224__RX_DCOC_RES_I_224___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_224__RX_DCOC_RES_Q_224___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_224__RX_DCOC_RANGE_224___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_224__RX_DCOC_RANGE_224___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_224__RX_DCOC_RES_I_224___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_224__RX_DCOC_RES_I_224___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_224__RX_DCOC_RES_Q_224___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_224__RX_DCOC_RES_Q_224___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_224___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_224___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_225 (0x005EC384) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_225___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_225___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_225__RX_DCOC_RANGE_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_225__RX_DCOC_RES_I_225___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_225__RX_DCOC_RES_Q_225___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_225__RX_DCOC_RANGE_225___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_225__RX_DCOC_RANGE_225___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_225__RX_DCOC_RES_I_225___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_225__RX_DCOC_RES_I_225___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_225__RX_DCOC_RES_Q_225___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_225__RX_DCOC_RES_Q_225___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_225___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_225___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_226 (0x005EC388) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_226___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_226___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_226__RX_DCOC_RANGE_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_226__RX_DCOC_RES_I_226___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_226__RX_DCOC_RES_Q_226___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_226__RX_DCOC_RANGE_226___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_226__RX_DCOC_RANGE_226___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_226__RX_DCOC_RES_I_226___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_226__RX_DCOC_RES_I_226___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_226__RX_DCOC_RES_Q_226___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_226__RX_DCOC_RES_Q_226___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_226___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_226___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_227 (0x005EC38C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_227___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_227___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_227__RX_DCOC_RANGE_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_227__RX_DCOC_RES_I_227___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_227__RX_DCOC_RES_Q_227___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_227__RX_DCOC_RANGE_227___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_227__RX_DCOC_RANGE_227___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_227__RX_DCOC_RES_I_227___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_227__RX_DCOC_RES_I_227___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_227__RX_DCOC_RES_Q_227___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_227__RX_DCOC_RES_Q_227___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_227___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_227___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_228 (0x005EC390) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_228___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_228___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_228__RX_DCOC_RANGE_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_228__RX_DCOC_RES_I_228___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_228__RX_DCOC_RES_Q_228___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_228__RX_DCOC_RANGE_228___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_228__RX_DCOC_RANGE_228___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_228__RX_DCOC_RES_I_228___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_228__RX_DCOC_RES_I_228___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_228__RX_DCOC_RES_Q_228___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_228__RX_DCOC_RES_Q_228___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_228___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_228___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_229 (0x005EC394) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_229___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_229___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_229__RX_DCOC_RANGE_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_229__RX_DCOC_RES_I_229___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_229__RX_DCOC_RES_Q_229___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_229__RX_DCOC_RANGE_229___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_229__RX_DCOC_RANGE_229___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_229__RX_DCOC_RES_I_229___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_229__RX_DCOC_RES_I_229___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_229__RX_DCOC_RES_Q_229___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_229__RX_DCOC_RES_Q_229___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_229___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_229___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_230 (0x005EC398) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_230___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_230___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_230__RX_DCOC_RANGE_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_230__RX_DCOC_RES_I_230___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_230__RX_DCOC_RES_Q_230___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_230__RX_DCOC_RANGE_230___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_230__RX_DCOC_RANGE_230___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_230__RX_DCOC_RES_I_230___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_230__RX_DCOC_RES_I_230___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_230__RX_DCOC_RES_Q_230___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_230__RX_DCOC_RES_Q_230___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_230___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_230___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_231 (0x005EC39C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_231___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_231___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_231__RX_DCOC_RANGE_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_231__RX_DCOC_RES_I_231___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_231__RX_DCOC_RES_Q_231___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_231__RX_DCOC_RANGE_231___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_231__RX_DCOC_RANGE_231___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_231__RX_DCOC_RES_I_231___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_231__RX_DCOC_RES_I_231___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_231__RX_DCOC_RES_Q_231___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_231__RX_DCOC_RES_Q_231___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_231___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_231___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_232 (0x005EC3A0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_232___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_232___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_232__RX_DCOC_RANGE_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_232__RX_DCOC_RES_I_232___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_232__RX_DCOC_RES_Q_232___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_232__RX_DCOC_RANGE_232___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_232__RX_DCOC_RANGE_232___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_232__RX_DCOC_RES_I_232___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_232__RX_DCOC_RES_I_232___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_232__RX_DCOC_RES_Q_232___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_232__RX_DCOC_RES_Q_232___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_232___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_232___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_233 (0x005EC3A4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_233___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_233___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_233__RX_DCOC_RANGE_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_233__RX_DCOC_RES_I_233___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_233__RX_DCOC_RES_Q_233___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_233__RX_DCOC_RANGE_233___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_233__RX_DCOC_RANGE_233___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_233__RX_DCOC_RES_I_233___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_233__RX_DCOC_RES_I_233___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_233__RX_DCOC_RES_Q_233___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_233__RX_DCOC_RES_Q_233___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_233___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_233___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_234 (0x005EC3A8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_234___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_234___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_234__RX_DCOC_RANGE_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_234__RX_DCOC_RES_I_234___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_234__RX_DCOC_RES_Q_234___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_234__RX_DCOC_RANGE_234___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_234__RX_DCOC_RANGE_234___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_234__RX_DCOC_RES_I_234___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_234__RX_DCOC_RES_I_234___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_234__RX_DCOC_RES_Q_234___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_234__RX_DCOC_RES_Q_234___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_234___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_234___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_235 (0x005EC3AC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_235___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_235___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_235__RX_DCOC_RANGE_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_235__RX_DCOC_RES_I_235___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_235__RX_DCOC_RES_Q_235___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_235__RX_DCOC_RANGE_235___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_235__RX_DCOC_RANGE_235___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_235__RX_DCOC_RES_I_235___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_235__RX_DCOC_RES_I_235___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_235__RX_DCOC_RES_Q_235___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_235__RX_DCOC_RES_Q_235___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_235___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_235___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_236 (0x005EC3B0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_236___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_236___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_236__RX_DCOC_RANGE_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_236__RX_DCOC_RES_I_236___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_236__RX_DCOC_RES_Q_236___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_236__RX_DCOC_RANGE_236___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_236__RX_DCOC_RANGE_236___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_236__RX_DCOC_RES_I_236___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_236__RX_DCOC_RES_I_236___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_236__RX_DCOC_RES_Q_236___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_236__RX_DCOC_RES_Q_236___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_236___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_236___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_237 (0x005EC3B4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_237___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_237___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_237__RX_DCOC_RANGE_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_237__RX_DCOC_RES_I_237___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_237__RX_DCOC_RES_Q_237___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_237__RX_DCOC_RANGE_237___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_237__RX_DCOC_RANGE_237___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_237__RX_DCOC_RES_I_237___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_237__RX_DCOC_RES_I_237___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_237__RX_DCOC_RES_Q_237___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_237__RX_DCOC_RES_Q_237___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_237___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_237___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_238 (0x005EC3B8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_238___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_238___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_238__RX_DCOC_RANGE_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_238__RX_DCOC_RES_I_238___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_238__RX_DCOC_RES_Q_238___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_238__RX_DCOC_RANGE_238___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_238__RX_DCOC_RANGE_238___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_238__RX_DCOC_RES_I_238___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_238__RX_DCOC_RES_I_238___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_238__RX_DCOC_RES_Q_238___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_238__RX_DCOC_RES_Q_238___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_238___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_238___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_239 (0x005EC3BC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_239___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_239___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_239__RX_DCOC_RANGE_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_239__RX_DCOC_RES_I_239___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_239__RX_DCOC_RES_Q_239___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_239__RX_DCOC_RANGE_239___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_239__RX_DCOC_RANGE_239___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_239__RX_DCOC_RES_I_239___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_239__RX_DCOC_RES_I_239___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_239__RX_DCOC_RES_Q_239___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_239__RX_DCOC_RES_Q_239___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_239___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_239___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_240 (0x005EC3C0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_240___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_240___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_240__RX_DCOC_RANGE_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_240__RX_DCOC_RES_I_240___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_240__RX_DCOC_RES_Q_240___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_240__RX_DCOC_RANGE_240___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_240__RX_DCOC_RANGE_240___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_240__RX_DCOC_RES_I_240___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_240__RX_DCOC_RES_I_240___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_240__RX_DCOC_RES_Q_240___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_240__RX_DCOC_RES_Q_240___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_240___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_240___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_241 (0x005EC3C4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_241___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_241___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_241__RX_DCOC_RANGE_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_241__RX_DCOC_RES_I_241___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_241__RX_DCOC_RES_Q_241___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_241__RX_DCOC_RANGE_241___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_241__RX_DCOC_RANGE_241___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_241__RX_DCOC_RES_I_241___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_241__RX_DCOC_RES_I_241___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_241__RX_DCOC_RES_Q_241___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_241__RX_DCOC_RES_Q_241___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_241___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_241___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_242 (0x005EC3C8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_242___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_242___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_242__RX_DCOC_RANGE_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_242__RX_DCOC_RES_I_242___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_242__RX_DCOC_RES_Q_242___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_242__RX_DCOC_RANGE_242___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_242__RX_DCOC_RANGE_242___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_242__RX_DCOC_RES_I_242___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_242__RX_DCOC_RES_I_242___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_242__RX_DCOC_RES_Q_242___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_242__RX_DCOC_RES_Q_242___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_242___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_242___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_243 (0x005EC3CC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_243___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_243___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_243__RX_DCOC_RANGE_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_243__RX_DCOC_RES_I_243___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_243__RX_DCOC_RES_Q_243___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_243__RX_DCOC_RANGE_243___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_243__RX_DCOC_RANGE_243___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_243__RX_DCOC_RES_I_243___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_243__RX_DCOC_RES_I_243___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_243__RX_DCOC_RES_Q_243___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_243__RX_DCOC_RES_Q_243___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_243___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_243___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_244 (0x005EC3D0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_244___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_244___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_244__RX_DCOC_RANGE_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_244__RX_DCOC_RES_I_244___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_244__RX_DCOC_RES_Q_244___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_244__RX_DCOC_RANGE_244___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_244__RX_DCOC_RANGE_244___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_244__RX_DCOC_RES_I_244___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_244__RX_DCOC_RES_I_244___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_244__RX_DCOC_RES_Q_244___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_244__RX_DCOC_RES_Q_244___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_244___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_244___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_245 (0x005EC3D4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_245___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_245___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_245__RX_DCOC_RANGE_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_245__RX_DCOC_RES_I_245___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_245__RX_DCOC_RES_Q_245___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_245__RX_DCOC_RANGE_245___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_245__RX_DCOC_RANGE_245___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_245__RX_DCOC_RES_I_245___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_245__RX_DCOC_RES_I_245___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_245__RX_DCOC_RES_Q_245___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_245__RX_DCOC_RES_Q_245___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_245___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_245___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_246 (0x005EC3D8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_246___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_246___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_246__RX_DCOC_RANGE_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_246__RX_DCOC_RES_I_246___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_246__RX_DCOC_RES_Q_246___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_246__RX_DCOC_RANGE_246___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_246__RX_DCOC_RANGE_246___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_246__RX_DCOC_RES_I_246___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_246__RX_DCOC_RES_I_246___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_246__RX_DCOC_RES_Q_246___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_246__RX_DCOC_RES_Q_246___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_246___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_246___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_247 (0x005EC3DC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_247___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_247___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_247__RX_DCOC_RANGE_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_247__RX_DCOC_RES_I_247___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_247__RX_DCOC_RES_Q_247___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_247__RX_DCOC_RANGE_247___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_247__RX_DCOC_RANGE_247___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_247__RX_DCOC_RES_I_247___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_247__RX_DCOC_RES_I_247___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_247__RX_DCOC_RES_Q_247___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_247__RX_DCOC_RES_Q_247___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_247___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_247___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_248 (0x005EC3E0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_248___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_248___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_248__RX_DCOC_RANGE_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_248__RX_DCOC_RES_I_248___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_248__RX_DCOC_RES_Q_248___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_248__RX_DCOC_RANGE_248___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_248__RX_DCOC_RANGE_248___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_248__RX_DCOC_RES_I_248___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_248__RX_DCOC_RES_I_248___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_248__RX_DCOC_RES_Q_248___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_248__RX_DCOC_RES_Q_248___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_248___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_248___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_249 (0x005EC3E4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_249___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_249___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_249__RX_DCOC_RANGE_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_249__RX_DCOC_RES_I_249___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_249__RX_DCOC_RES_Q_249___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_249__RX_DCOC_RANGE_249___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_249__RX_DCOC_RANGE_249___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_249__RX_DCOC_RES_I_249___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_249__RX_DCOC_RES_I_249___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_249__RX_DCOC_RES_Q_249___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_249__RX_DCOC_RES_Q_249___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_249___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_249___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_250 (0x005EC3E8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_250___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_250___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_250__RX_DCOC_RANGE_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_250__RX_DCOC_RES_I_250___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_250__RX_DCOC_RES_Q_250___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_250__RX_DCOC_RANGE_250___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_250__RX_DCOC_RANGE_250___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_250__RX_DCOC_RES_I_250___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_250__RX_DCOC_RES_I_250___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_250__RX_DCOC_RES_Q_250___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_250__RX_DCOC_RES_Q_250___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_250___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_250___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_251 (0x005EC3EC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_251___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_251___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_251__RX_DCOC_RANGE_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_251__RX_DCOC_RES_I_251___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_251__RX_DCOC_RES_Q_251___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_251__RX_DCOC_RANGE_251___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_251__RX_DCOC_RANGE_251___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_251__RX_DCOC_RES_I_251___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_251__RX_DCOC_RES_I_251___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_251__RX_DCOC_RES_Q_251___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_251__RX_DCOC_RES_Q_251___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_251___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_251___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_252 (0x005EC3F0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_252___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_252___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_252__RX_DCOC_RANGE_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_252__RX_DCOC_RES_I_252___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_252__RX_DCOC_RES_Q_252___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_252__RX_DCOC_RANGE_252___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_252__RX_DCOC_RANGE_252___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_252__RX_DCOC_RES_I_252___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_252__RX_DCOC_RES_I_252___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_252__RX_DCOC_RES_Q_252___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_252__RX_DCOC_RES_Q_252___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_252___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_252___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_253 (0x005EC3F4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_253___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_253___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_253__RX_DCOC_RANGE_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_253__RX_DCOC_RES_I_253___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_253__RX_DCOC_RES_Q_253___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_253__RX_DCOC_RANGE_253___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_253__RX_DCOC_RANGE_253___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_253__RX_DCOC_RES_I_253___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_253__RX_DCOC_RES_I_253___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_253__RX_DCOC_RES_Q_253___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_253__RX_DCOC_RES_Q_253___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_253___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_253___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_254 (0x005EC3F8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_254___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_254___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_254__RX_DCOC_RANGE_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_254__RX_DCOC_RES_I_254___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_254__RX_DCOC_RES_Q_254___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_254__RX_DCOC_RANGE_254___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_254__RX_DCOC_RANGE_254___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_254__RX_DCOC_RES_I_254___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_254__RX_DCOC_RES_I_254___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_254__RX_DCOC_RES_Q_254___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_254__RX_DCOC_RES_Q_254___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_254___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_254___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_255 (0x005EC3FC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_255___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_255___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_255__RX_DCOC_RANGE_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_255__RX_DCOC_RES_I_255___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_255__RX_DCOC_RES_Q_255___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_255__RX_DCOC_RANGE_255___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_255__RX_DCOC_RANGE_255___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_255__RX_DCOC_RES_I_255___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_255__RX_DCOC_RES_I_255___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_255__RX_DCOC_RES_Q_255___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_255__RX_DCOC_RES_Q_255___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_255___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_255___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_256 (0x005EC400) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_256___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_256___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_256__RX_DCOC_RANGE_256___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_256__RX_DCOC_RES_I_256___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_256__RX_DCOC_RES_Q_256___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_256__RX_DCOC_RANGE_256___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_256__RX_DCOC_RANGE_256___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_256__RX_DCOC_RES_I_256___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_256__RX_DCOC_RES_I_256___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_256__RX_DCOC_RES_Q_256___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_256__RX_DCOC_RES_Q_256___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_256___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_256___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_257 (0x005EC404) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_257___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_257___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_257__RX_DCOC_RANGE_257___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_257__RX_DCOC_RES_I_257___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_257__RX_DCOC_RES_Q_257___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_257__RX_DCOC_RANGE_257___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_257__RX_DCOC_RANGE_257___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_257__RX_DCOC_RES_I_257___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_257__RX_DCOC_RES_I_257___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_257__RX_DCOC_RES_Q_257___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_257__RX_DCOC_RES_Q_257___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_257___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_257___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_258 (0x005EC408) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_258___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_258___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_258__RX_DCOC_RANGE_258___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_258__RX_DCOC_RES_I_258___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_258__RX_DCOC_RES_Q_258___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_258__RX_DCOC_RANGE_258___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_258__RX_DCOC_RANGE_258___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_258__RX_DCOC_RES_I_258___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_258__RX_DCOC_RES_I_258___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_258__RX_DCOC_RES_Q_258___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_258__RX_DCOC_RES_Q_258___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_258___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_258___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_259 (0x005EC40C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_259___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_259___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_259__RX_DCOC_RANGE_259___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_259__RX_DCOC_RES_I_259___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_259__RX_DCOC_RES_Q_259___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_259__RX_DCOC_RANGE_259___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_259__RX_DCOC_RANGE_259___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_259__RX_DCOC_RES_I_259___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_259__RX_DCOC_RES_I_259___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_259__RX_DCOC_RES_Q_259___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_259__RX_DCOC_RES_Q_259___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_259___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_259___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_260 (0x005EC410) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_260___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_260___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_260__RX_DCOC_RANGE_260___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_260__RX_DCOC_RES_I_260___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_260__RX_DCOC_RES_Q_260___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_260__RX_DCOC_RANGE_260___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_260__RX_DCOC_RANGE_260___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_260__RX_DCOC_RES_I_260___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_260__RX_DCOC_RES_I_260___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_260__RX_DCOC_RES_Q_260___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_260__RX_DCOC_RES_Q_260___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_260___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_260___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_261 (0x005EC414) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_261___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_261___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_261__RX_DCOC_RANGE_261___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_261__RX_DCOC_RES_I_261___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_261__RX_DCOC_RES_Q_261___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_261__RX_DCOC_RANGE_261___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_261__RX_DCOC_RANGE_261___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_261__RX_DCOC_RES_I_261___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_261__RX_DCOC_RES_I_261___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_261__RX_DCOC_RES_Q_261___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_261__RX_DCOC_RES_Q_261___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_261___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_261___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_262 (0x005EC418) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_262___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_262___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_262__RX_DCOC_RANGE_262___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_262__RX_DCOC_RES_I_262___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_262__RX_DCOC_RES_Q_262___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_262__RX_DCOC_RANGE_262___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_262__RX_DCOC_RANGE_262___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_262__RX_DCOC_RES_I_262___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_262__RX_DCOC_RES_I_262___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_262__RX_DCOC_RES_Q_262___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_262__RX_DCOC_RES_Q_262___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_262___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_262___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_263 (0x005EC41C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_263___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_263___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_263__RX_DCOC_RANGE_263___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_263__RX_DCOC_RES_I_263___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_263__RX_DCOC_RES_Q_263___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_263__RX_DCOC_RANGE_263___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_263__RX_DCOC_RANGE_263___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_263__RX_DCOC_RES_I_263___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_263__RX_DCOC_RES_I_263___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_263__RX_DCOC_RES_Q_263___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_263__RX_DCOC_RES_Q_263___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_263___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_263___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_264 (0x005EC420) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_264___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_264___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_264__RX_DCOC_RANGE_264___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_264__RX_DCOC_RES_I_264___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_264__RX_DCOC_RES_Q_264___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_264__RX_DCOC_RANGE_264___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_264__RX_DCOC_RANGE_264___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_264__RX_DCOC_RES_I_264___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_264__RX_DCOC_RES_I_264___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_264__RX_DCOC_RES_Q_264___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_264__RX_DCOC_RES_Q_264___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_264___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_264___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_265 (0x005EC424) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_265___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_265___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_265__RX_DCOC_RANGE_265___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_265__RX_DCOC_RES_I_265___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_265__RX_DCOC_RES_Q_265___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_265__RX_DCOC_RANGE_265___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_265__RX_DCOC_RANGE_265___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_265__RX_DCOC_RES_I_265___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_265__RX_DCOC_RES_I_265___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_265__RX_DCOC_RES_Q_265___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_265__RX_DCOC_RES_Q_265___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_265___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_265___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_266 (0x005EC428) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_266___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_266___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_266__RX_DCOC_RANGE_266___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_266__RX_DCOC_RES_I_266___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_266__RX_DCOC_RES_Q_266___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_266__RX_DCOC_RANGE_266___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_266__RX_DCOC_RANGE_266___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_266__RX_DCOC_RES_I_266___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_266__RX_DCOC_RES_I_266___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_266__RX_DCOC_RES_Q_266___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_266__RX_DCOC_RES_Q_266___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_266___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_266___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_267 (0x005EC42C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_267___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_267___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_267__RX_DCOC_RANGE_267___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_267__RX_DCOC_RES_I_267___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_267__RX_DCOC_RES_Q_267___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_267__RX_DCOC_RANGE_267___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_267__RX_DCOC_RANGE_267___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_267__RX_DCOC_RES_I_267___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_267__RX_DCOC_RES_I_267___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_267__RX_DCOC_RES_Q_267___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_267__RX_DCOC_RES_Q_267___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_267___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_267___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_268 (0x005EC430) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_268___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_268___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_268__RX_DCOC_RANGE_268___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_268__RX_DCOC_RES_I_268___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_268__RX_DCOC_RES_Q_268___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_268__RX_DCOC_RANGE_268___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_268__RX_DCOC_RANGE_268___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_268__RX_DCOC_RES_I_268___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_268__RX_DCOC_RES_I_268___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_268__RX_DCOC_RES_Q_268___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_268__RX_DCOC_RES_Q_268___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_268___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_268___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_269 (0x005EC434) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_269___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_269___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_269__RX_DCOC_RANGE_269___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_269__RX_DCOC_RES_I_269___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_269__RX_DCOC_RES_Q_269___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_269__RX_DCOC_RANGE_269___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_269__RX_DCOC_RANGE_269___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_269__RX_DCOC_RES_I_269___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_269__RX_DCOC_RES_I_269___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_269__RX_DCOC_RES_Q_269___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_269__RX_DCOC_RES_Q_269___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_269___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_269___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_270 (0x005EC438) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_270___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_270___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_270__RX_DCOC_RANGE_270___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_270__RX_DCOC_RES_I_270___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_270__RX_DCOC_RES_Q_270___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_270__RX_DCOC_RANGE_270___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_270__RX_DCOC_RANGE_270___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_270__RX_DCOC_RES_I_270___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_270__RX_DCOC_RES_I_270___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_270__RX_DCOC_RES_Q_270___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_270__RX_DCOC_RES_Q_270___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_270___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_270___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_271 (0x005EC43C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_271___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_271___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_271__RX_DCOC_RANGE_271___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_271__RX_DCOC_RES_I_271___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_271__RX_DCOC_RES_Q_271___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_271__RX_DCOC_RANGE_271___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_271__RX_DCOC_RANGE_271___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_271__RX_DCOC_RES_I_271___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_271__RX_DCOC_RES_I_271___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_271__RX_DCOC_RES_Q_271___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_271__RX_DCOC_RES_Q_271___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_271___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_271___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_272 (0x005EC440) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_272___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_272___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_272__RX_DCOC_RANGE_272___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_272__RX_DCOC_RES_I_272___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_272__RX_DCOC_RES_Q_272___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_272__RX_DCOC_RANGE_272___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_272__RX_DCOC_RANGE_272___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_272__RX_DCOC_RES_I_272___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_272__RX_DCOC_RES_I_272___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_272__RX_DCOC_RES_Q_272___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_272__RX_DCOC_RES_Q_272___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_272___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_272___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_273 (0x005EC444) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_273___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_273___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_273__RX_DCOC_RANGE_273___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_273__RX_DCOC_RES_I_273___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_273__RX_DCOC_RES_Q_273___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_273__RX_DCOC_RANGE_273___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_273__RX_DCOC_RANGE_273___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_273__RX_DCOC_RES_I_273___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_273__RX_DCOC_RES_I_273___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_273__RX_DCOC_RES_Q_273___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_273__RX_DCOC_RES_Q_273___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_273___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_273___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_274 (0x005EC448) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_274___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_274___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_274__RX_DCOC_RANGE_274___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_274__RX_DCOC_RES_I_274___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_274__RX_DCOC_RES_Q_274___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_274__RX_DCOC_RANGE_274___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_274__RX_DCOC_RANGE_274___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_274__RX_DCOC_RES_I_274___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_274__RX_DCOC_RES_I_274___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_274__RX_DCOC_RES_Q_274___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_274__RX_DCOC_RES_Q_274___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_274___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_274___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_275 (0x005EC44C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_275___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_275___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_275__RX_DCOC_RANGE_275___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_275__RX_DCOC_RES_I_275___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_275__RX_DCOC_RES_Q_275___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_275__RX_DCOC_RANGE_275___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_275__RX_DCOC_RANGE_275___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_275__RX_DCOC_RES_I_275___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_275__RX_DCOC_RES_I_275___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_275__RX_DCOC_RES_Q_275___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_275__RX_DCOC_RES_Q_275___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_275___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_275___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_276 (0x005EC450) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_276___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_276___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_276__RX_DCOC_RANGE_276___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_276__RX_DCOC_RES_I_276___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_276__RX_DCOC_RES_Q_276___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_276__RX_DCOC_RANGE_276___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_276__RX_DCOC_RANGE_276___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_276__RX_DCOC_RES_I_276___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_276__RX_DCOC_RES_I_276___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_276__RX_DCOC_RES_Q_276___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_276__RX_DCOC_RES_Q_276___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_276___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_276___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_277 (0x005EC454) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_277___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_277___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_277__RX_DCOC_RANGE_277___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_277__RX_DCOC_RES_I_277___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_277__RX_DCOC_RES_Q_277___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_277__RX_DCOC_RANGE_277___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_277__RX_DCOC_RANGE_277___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_277__RX_DCOC_RES_I_277___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_277__RX_DCOC_RES_I_277___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_277__RX_DCOC_RES_Q_277___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_277__RX_DCOC_RES_Q_277___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_277___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_277___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_278 (0x005EC458) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_278___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_278___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_278__RX_DCOC_RANGE_278___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_278__RX_DCOC_RES_I_278___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_278__RX_DCOC_RES_Q_278___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_278__RX_DCOC_RANGE_278___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_278__RX_DCOC_RANGE_278___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_278__RX_DCOC_RES_I_278___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_278__RX_DCOC_RES_I_278___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_278__RX_DCOC_RES_Q_278___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_278__RX_DCOC_RES_Q_278___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_278___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_278___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_279 (0x005EC45C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_279___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_279___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_279__RX_DCOC_RANGE_279___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_279__RX_DCOC_RES_I_279___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_279__RX_DCOC_RES_Q_279___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_279__RX_DCOC_RANGE_279___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_279__RX_DCOC_RANGE_279___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_279__RX_DCOC_RES_I_279___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_279__RX_DCOC_RES_I_279___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_279__RX_DCOC_RES_Q_279___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_279__RX_DCOC_RES_Q_279___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_279___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_279___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_280 (0x005EC460) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_280___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_280___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_280__RX_DCOC_RANGE_280___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_280__RX_DCOC_RES_I_280___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_280__RX_DCOC_RES_Q_280___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_280__RX_DCOC_RANGE_280___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_280__RX_DCOC_RANGE_280___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_280__RX_DCOC_RES_I_280___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_280__RX_DCOC_RES_I_280___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_280__RX_DCOC_RES_Q_280___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_280__RX_DCOC_RES_Q_280___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_280___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_280___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_281 (0x005EC464) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_281___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_281___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_281__RX_DCOC_RANGE_281___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_281__RX_DCOC_RES_I_281___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_281__RX_DCOC_RES_Q_281___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_281__RX_DCOC_RANGE_281___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_281__RX_DCOC_RANGE_281___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_281__RX_DCOC_RES_I_281___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_281__RX_DCOC_RES_I_281___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_281__RX_DCOC_RES_Q_281___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_281__RX_DCOC_RES_Q_281___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_281___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_281___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_282 (0x005EC468) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_282___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_282___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_282__RX_DCOC_RANGE_282___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_282__RX_DCOC_RES_I_282___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_282__RX_DCOC_RES_Q_282___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_282__RX_DCOC_RANGE_282___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_282__RX_DCOC_RANGE_282___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_282__RX_DCOC_RES_I_282___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_282__RX_DCOC_RES_I_282___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_282__RX_DCOC_RES_Q_282___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_282__RX_DCOC_RES_Q_282___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_282___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_282___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_283 (0x005EC46C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_283___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_283___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_283__RX_DCOC_RANGE_283___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_283__RX_DCOC_RES_I_283___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_283__RX_DCOC_RES_Q_283___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_283__RX_DCOC_RANGE_283___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_283__RX_DCOC_RANGE_283___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_283__RX_DCOC_RES_I_283___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_283__RX_DCOC_RES_I_283___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_283__RX_DCOC_RES_Q_283___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_283__RX_DCOC_RES_Q_283___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_283___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_283___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_284 (0x005EC470) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_284___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_284___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_284__RX_DCOC_RANGE_284___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_284__RX_DCOC_RES_I_284___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_284__RX_DCOC_RES_Q_284___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_284__RX_DCOC_RANGE_284___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_284__RX_DCOC_RANGE_284___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_284__RX_DCOC_RES_I_284___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_284__RX_DCOC_RES_I_284___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_284__RX_DCOC_RES_Q_284___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_284__RX_DCOC_RES_Q_284___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_284___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_284___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_285 (0x005EC474) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_285___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_285___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_285__RX_DCOC_RANGE_285___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_285__RX_DCOC_RES_I_285___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_285__RX_DCOC_RES_Q_285___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_285__RX_DCOC_RANGE_285___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_285__RX_DCOC_RANGE_285___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_285__RX_DCOC_RES_I_285___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_285__RX_DCOC_RES_I_285___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_285__RX_DCOC_RES_Q_285___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_285__RX_DCOC_RES_Q_285___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_285___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_285___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_286 (0x005EC478) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_286___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_286___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_286__RX_DCOC_RANGE_286___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_286__RX_DCOC_RES_I_286___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_286__RX_DCOC_RES_Q_286___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_286__RX_DCOC_RANGE_286___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_286__RX_DCOC_RANGE_286___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_286__RX_DCOC_RES_I_286___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_286__RX_DCOC_RES_I_286___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_286__RX_DCOC_RES_Q_286___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_286__RX_DCOC_RES_Q_286___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_286___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_286___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_287 (0x005EC47C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_287___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_287___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_287__RX_DCOC_RANGE_287___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_287__RX_DCOC_RES_I_287___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_287__RX_DCOC_RES_Q_287___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_287__RX_DCOC_RANGE_287___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_287__RX_DCOC_RANGE_287___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_287__RX_DCOC_RES_I_287___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_287__RX_DCOC_RES_I_287___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_287__RX_DCOC_RES_Q_287___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_287__RX_DCOC_RES_Q_287___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_287___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_287___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_288 (0x005EC480) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_288___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_288___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_288__RX_DCOC_RANGE_288___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_288__RX_DCOC_RES_I_288___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_288__RX_DCOC_RES_Q_288___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_288__RX_DCOC_RANGE_288___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_288__RX_DCOC_RANGE_288___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_288__RX_DCOC_RES_I_288___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_288__RX_DCOC_RES_I_288___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_288__RX_DCOC_RES_Q_288___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_288__RX_DCOC_RES_Q_288___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_288___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_288___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_289 (0x005EC484) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_289___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_289___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_289__RX_DCOC_RANGE_289___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_289__RX_DCOC_RES_I_289___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_289__RX_DCOC_RES_Q_289___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_289__RX_DCOC_RANGE_289___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_289__RX_DCOC_RANGE_289___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_289__RX_DCOC_RES_I_289___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_289__RX_DCOC_RES_I_289___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_289__RX_DCOC_RES_Q_289___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_289__RX_DCOC_RES_Q_289___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_289___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_289___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_290 (0x005EC488) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_290___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_290___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_290__RX_DCOC_RANGE_290___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_290__RX_DCOC_RES_I_290___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_290__RX_DCOC_RES_Q_290___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_290__RX_DCOC_RANGE_290___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_290__RX_DCOC_RANGE_290___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_290__RX_DCOC_RES_I_290___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_290__RX_DCOC_RES_I_290___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_290__RX_DCOC_RES_Q_290___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_290__RX_DCOC_RES_Q_290___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_290___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_290___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_291 (0x005EC48C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_291___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_291___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_291__RX_DCOC_RANGE_291___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_291__RX_DCOC_RES_I_291___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_291__RX_DCOC_RES_Q_291___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_291__RX_DCOC_RANGE_291___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_291__RX_DCOC_RANGE_291___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_291__RX_DCOC_RES_I_291___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_291__RX_DCOC_RES_I_291___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_291__RX_DCOC_RES_Q_291___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_291__RX_DCOC_RES_Q_291___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_291___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_291___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_292 (0x005EC490) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_292___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_292___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_292__RX_DCOC_RANGE_292___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_292__RX_DCOC_RES_I_292___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_292__RX_DCOC_RES_Q_292___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_292__RX_DCOC_RANGE_292___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_292__RX_DCOC_RANGE_292___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_292__RX_DCOC_RES_I_292___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_292__RX_DCOC_RES_I_292___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_292__RX_DCOC_RES_Q_292___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_292__RX_DCOC_RES_Q_292___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_292___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_292___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_293 (0x005EC494) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_293___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_293___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_293__RX_DCOC_RANGE_293___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_293__RX_DCOC_RES_I_293___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_293__RX_DCOC_RES_Q_293___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_293__RX_DCOC_RANGE_293___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_293__RX_DCOC_RANGE_293___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_293__RX_DCOC_RES_I_293___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_293__RX_DCOC_RES_I_293___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_293__RX_DCOC_RES_Q_293___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_293__RX_DCOC_RES_Q_293___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_293___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_293___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_294 (0x005EC498) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_294___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_294___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_294__RX_DCOC_RANGE_294___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_294__RX_DCOC_RES_I_294___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_294__RX_DCOC_RES_Q_294___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_294__RX_DCOC_RANGE_294___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_294__RX_DCOC_RANGE_294___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_294__RX_DCOC_RES_I_294___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_294__RX_DCOC_RES_I_294___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_294__RX_DCOC_RES_Q_294___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_294__RX_DCOC_RES_Q_294___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_294___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_294___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_295 (0x005EC49C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_295___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_295___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_295__RX_DCOC_RANGE_295___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_295__RX_DCOC_RES_I_295___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_295__RX_DCOC_RES_Q_295___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_295__RX_DCOC_RANGE_295___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_295__RX_DCOC_RANGE_295___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_295__RX_DCOC_RES_I_295___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_295__RX_DCOC_RES_I_295___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_295__RX_DCOC_RES_Q_295___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_295__RX_DCOC_RES_Q_295___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_295___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_295___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_296 (0x005EC4A0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_296___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_296___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_296__RX_DCOC_RANGE_296___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_296__RX_DCOC_RES_I_296___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_296__RX_DCOC_RES_Q_296___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_296__RX_DCOC_RANGE_296___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_296__RX_DCOC_RANGE_296___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_296__RX_DCOC_RES_I_296___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_296__RX_DCOC_RES_I_296___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_296__RX_DCOC_RES_Q_296___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_296__RX_DCOC_RES_Q_296___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_296___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_296___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_297 (0x005EC4A4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_297___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_297___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_297__RX_DCOC_RANGE_297___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_297__RX_DCOC_RES_I_297___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_297__RX_DCOC_RES_Q_297___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_297__RX_DCOC_RANGE_297___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_297__RX_DCOC_RANGE_297___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_297__RX_DCOC_RES_I_297___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_297__RX_DCOC_RES_I_297___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_297__RX_DCOC_RES_Q_297___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_297__RX_DCOC_RES_Q_297___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_297___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_297___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_298 (0x005EC4A8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_298___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_298___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_298__RX_DCOC_RANGE_298___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_298__RX_DCOC_RES_I_298___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_298__RX_DCOC_RES_Q_298___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_298__RX_DCOC_RANGE_298___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_298__RX_DCOC_RANGE_298___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_298__RX_DCOC_RES_I_298___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_298__RX_DCOC_RES_I_298___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_298__RX_DCOC_RES_Q_298___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_298__RX_DCOC_RES_Q_298___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_298___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_298___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_299 (0x005EC4AC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_299___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_299___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_299__RX_DCOC_RANGE_299___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_299__RX_DCOC_RES_I_299___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_299__RX_DCOC_RES_Q_299___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_299__RX_DCOC_RANGE_299___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_299__RX_DCOC_RANGE_299___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_299__RX_DCOC_RES_I_299___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_299__RX_DCOC_RES_I_299___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_299__RX_DCOC_RES_Q_299___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_299__RX_DCOC_RES_Q_299___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_299___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_299___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_300 (0x005EC4B0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_300___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_300___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_300__RX_DCOC_RANGE_300___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_300__RX_DCOC_RES_I_300___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_300__RX_DCOC_RES_Q_300___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_300__RX_DCOC_RANGE_300___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_300__RX_DCOC_RANGE_300___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_300__RX_DCOC_RES_I_300___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_300__RX_DCOC_RES_I_300___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_300__RX_DCOC_RES_Q_300___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_300__RX_DCOC_RES_Q_300___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_300___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_300___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_301 (0x005EC4B4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_301___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_301___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_301__RX_DCOC_RANGE_301___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_301__RX_DCOC_RES_I_301___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_301__RX_DCOC_RES_Q_301___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_301__RX_DCOC_RANGE_301___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_301__RX_DCOC_RANGE_301___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_301__RX_DCOC_RES_I_301___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_301__RX_DCOC_RES_I_301___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_301__RX_DCOC_RES_Q_301___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_301__RX_DCOC_RES_Q_301___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_301___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_301___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_302 (0x005EC4B8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_302___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_302___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_302__RX_DCOC_RANGE_302___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_302__RX_DCOC_RES_I_302___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_302__RX_DCOC_RES_Q_302___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_302__RX_DCOC_RANGE_302___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_302__RX_DCOC_RANGE_302___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_302__RX_DCOC_RES_I_302___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_302__RX_DCOC_RES_I_302___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_302__RX_DCOC_RES_Q_302___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_302__RX_DCOC_RES_Q_302___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_302___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_302___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_303 (0x005EC4BC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_303___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_303___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_303__RX_DCOC_RANGE_303___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_303__RX_DCOC_RES_I_303___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_303__RX_DCOC_RES_Q_303___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_303__RX_DCOC_RANGE_303___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_303__RX_DCOC_RANGE_303___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_303__RX_DCOC_RES_I_303___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_303__RX_DCOC_RES_I_303___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_303__RX_DCOC_RES_Q_303___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_303__RX_DCOC_RES_Q_303___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_303___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_303___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_304 (0x005EC4C0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_304___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_304___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_304__RX_DCOC_RANGE_304___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_304__RX_DCOC_RES_I_304___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_304__RX_DCOC_RES_Q_304___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_304__RX_DCOC_RANGE_304___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_304__RX_DCOC_RANGE_304___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_304__RX_DCOC_RES_I_304___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_304__RX_DCOC_RES_I_304___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_304__RX_DCOC_RES_Q_304___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_304__RX_DCOC_RES_Q_304___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_304___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_304___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_305 (0x005EC4C4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_305___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_305___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_305__RX_DCOC_RANGE_305___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_305__RX_DCOC_RES_I_305___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_305__RX_DCOC_RES_Q_305___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_305__RX_DCOC_RANGE_305___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_305__RX_DCOC_RANGE_305___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_305__RX_DCOC_RES_I_305___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_305__RX_DCOC_RES_I_305___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_305__RX_DCOC_RES_Q_305___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_305__RX_DCOC_RES_Q_305___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_305___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_305___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_306 (0x005EC4C8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_306___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_306___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_306__RX_DCOC_RANGE_306___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_306__RX_DCOC_RES_I_306___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_306__RX_DCOC_RES_Q_306___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_306__RX_DCOC_RANGE_306___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_306__RX_DCOC_RANGE_306___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_306__RX_DCOC_RES_I_306___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_306__RX_DCOC_RES_I_306___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_306__RX_DCOC_RES_Q_306___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_306__RX_DCOC_RES_Q_306___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_306___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_306___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_307 (0x005EC4CC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_307___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_307___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_307__RX_DCOC_RANGE_307___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_307__RX_DCOC_RES_I_307___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_307__RX_DCOC_RES_Q_307___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_307__RX_DCOC_RANGE_307___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_307__RX_DCOC_RANGE_307___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_307__RX_DCOC_RES_I_307___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_307__RX_DCOC_RES_I_307___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_307__RX_DCOC_RES_Q_307___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_307__RX_DCOC_RES_Q_307___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_307___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_307___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_308 (0x005EC4D0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_308___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_308___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_308__RX_DCOC_RANGE_308___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_308__RX_DCOC_RES_I_308___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_308__RX_DCOC_RES_Q_308___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_308__RX_DCOC_RANGE_308___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_308__RX_DCOC_RANGE_308___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_308__RX_DCOC_RES_I_308___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_308__RX_DCOC_RES_I_308___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_308__RX_DCOC_RES_Q_308___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_308__RX_DCOC_RES_Q_308___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_308___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_308___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_309 (0x005EC4D4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_309___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_309___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_309__RX_DCOC_RANGE_309___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_309__RX_DCOC_RES_I_309___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_309__RX_DCOC_RES_Q_309___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_309__RX_DCOC_RANGE_309___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_309__RX_DCOC_RANGE_309___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_309__RX_DCOC_RES_I_309___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_309__RX_DCOC_RES_I_309___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_309__RX_DCOC_RES_Q_309___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_309__RX_DCOC_RES_Q_309___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_309___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_309___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_310 (0x005EC4D8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_310___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_310___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_310__RX_DCOC_RANGE_310___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_310__RX_DCOC_RES_I_310___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_310__RX_DCOC_RES_Q_310___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_310__RX_DCOC_RANGE_310___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_310__RX_DCOC_RANGE_310___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_310__RX_DCOC_RES_I_310___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_310__RX_DCOC_RES_I_310___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_310__RX_DCOC_RES_Q_310___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_310__RX_DCOC_RES_Q_310___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_310___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_310___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_311 (0x005EC4DC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_311___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_311___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_311__RX_DCOC_RANGE_311___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_311__RX_DCOC_RES_I_311___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_311__RX_DCOC_RES_Q_311___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_311__RX_DCOC_RANGE_311___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_311__RX_DCOC_RANGE_311___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_311__RX_DCOC_RES_I_311___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_311__RX_DCOC_RES_I_311___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_311__RX_DCOC_RES_Q_311___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_311__RX_DCOC_RES_Q_311___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_311___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_311___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_312 (0x005EC4E0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_312___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_312___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_312__RX_DCOC_RANGE_312___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_312__RX_DCOC_RES_I_312___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_312__RX_DCOC_RES_Q_312___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_312__RX_DCOC_RANGE_312___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_312__RX_DCOC_RANGE_312___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_312__RX_DCOC_RES_I_312___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_312__RX_DCOC_RES_I_312___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_312__RX_DCOC_RES_Q_312___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_312__RX_DCOC_RES_Q_312___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_312___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_312___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_313 (0x005EC4E4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_313___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_313___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_313__RX_DCOC_RANGE_313___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_313__RX_DCOC_RES_I_313___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_313__RX_DCOC_RES_Q_313___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_313__RX_DCOC_RANGE_313___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_313__RX_DCOC_RANGE_313___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_313__RX_DCOC_RES_I_313___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_313__RX_DCOC_RES_I_313___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_313__RX_DCOC_RES_Q_313___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_313__RX_DCOC_RES_Q_313___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_313___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_313___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_314 (0x005EC4E8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_314___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_314___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_314__RX_DCOC_RANGE_314___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_314__RX_DCOC_RES_I_314___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_314__RX_DCOC_RES_Q_314___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_314__RX_DCOC_RANGE_314___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_314__RX_DCOC_RANGE_314___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_314__RX_DCOC_RES_I_314___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_314__RX_DCOC_RES_I_314___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_314__RX_DCOC_RES_Q_314___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_314__RX_DCOC_RES_Q_314___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_314___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_314___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_315 (0x005EC4EC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_315___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_315___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_315__RX_DCOC_RANGE_315___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_315__RX_DCOC_RES_I_315___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_315__RX_DCOC_RES_Q_315___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_315__RX_DCOC_RANGE_315___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_315__RX_DCOC_RANGE_315___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_315__RX_DCOC_RES_I_315___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_315__RX_DCOC_RES_I_315___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_315__RX_DCOC_RES_Q_315___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_315__RX_DCOC_RES_Q_315___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_315___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_315___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_316 (0x005EC4F0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_316___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_316___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_316__RX_DCOC_RANGE_316___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_316__RX_DCOC_RES_I_316___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_316__RX_DCOC_RES_Q_316___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_316__RX_DCOC_RANGE_316___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_316__RX_DCOC_RANGE_316___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_316__RX_DCOC_RES_I_316___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_316__RX_DCOC_RES_I_316___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_316__RX_DCOC_RES_Q_316___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_316__RX_DCOC_RES_Q_316___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_316___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_316___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_317 (0x005EC4F4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_317___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_317___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_317__RX_DCOC_RANGE_317___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_317__RX_DCOC_RES_I_317___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_317__RX_DCOC_RES_Q_317___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_317__RX_DCOC_RANGE_317___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_317__RX_DCOC_RANGE_317___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_317__RX_DCOC_RES_I_317___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_317__RX_DCOC_RES_I_317___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_317__RX_DCOC_RES_Q_317___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_317__RX_DCOC_RES_Q_317___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_317___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_317___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_318 (0x005EC4F8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_318___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_318___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_318__RX_DCOC_RANGE_318___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_318__RX_DCOC_RES_I_318___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_318__RX_DCOC_RES_Q_318___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_318__RX_DCOC_RANGE_318___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_318__RX_DCOC_RANGE_318___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_318__RX_DCOC_RES_I_318___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_318__RX_DCOC_RES_I_318___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_318__RX_DCOC_RES_Q_318___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_318__RX_DCOC_RES_Q_318___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_318___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_318___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_319 (0x005EC4FC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_319___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_319___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_319__RX_DCOC_RANGE_319___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_319__RX_DCOC_RES_I_319___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_319__RX_DCOC_RES_Q_319___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_319__RX_DCOC_RANGE_319___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_319__RX_DCOC_RANGE_319___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_319__RX_DCOC_RES_I_319___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_319__RX_DCOC_RES_I_319___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_319__RX_DCOC_RES_Q_319___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_319__RX_DCOC_RES_Q_319___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_319___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_319___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_320 (0x005EC500) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_320___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_320___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_320__RX_DCOC_RANGE_320___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_320__RX_DCOC_RES_I_320___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_320__RX_DCOC_RES_Q_320___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_320__RX_DCOC_RANGE_320___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_320__RX_DCOC_RANGE_320___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_320__RX_DCOC_RES_I_320___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_320__RX_DCOC_RES_I_320___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_320__RX_DCOC_RES_Q_320___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_320__RX_DCOC_RES_Q_320___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_320___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_320___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_321 (0x005EC504) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_321___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_321___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_321__RX_DCOC_RANGE_321___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_321__RX_DCOC_RES_I_321___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_321__RX_DCOC_RES_Q_321___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_321__RX_DCOC_RANGE_321___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_321__RX_DCOC_RANGE_321___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_321__RX_DCOC_RES_I_321___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_321__RX_DCOC_RES_I_321___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_321__RX_DCOC_RES_Q_321___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_321__RX_DCOC_RES_Q_321___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_321___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_321___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_322 (0x005EC508) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_322___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_322___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_322__RX_DCOC_RANGE_322___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_322__RX_DCOC_RES_I_322___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_322__RX_DCOC_RES_Q_322___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_322__RX_DCOC_RANGE_322___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_322__RX_DCOC_RANGE_322___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_322__RX_DCOC_RES_I_322___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_322__RX_DCOC_RES_I_322___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_322__RX_DCOC_RES_Q_322___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_322__RX_DCOC_RES_Q_322___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_322___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_322___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_323 (0x005EC50C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_323___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_323___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_323__RX_DCOC_RANGE_323___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_323__RX_DCOC_RES_I_323___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_323__RX_DCOC_RES_Q_323___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_323__RX_DCOC_RANGE_323___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_323__RX_DCOC_RANGE_323___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_323__RX_DCOC_RES_I_323___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_323__RX_DCOC_RES_I_323___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_323__RX_DCOC_RES_Q_323___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_323__RX_DCOC_RES_Q_323___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_323___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_323___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_324 (0x005EC510) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_324___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_324___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_324__RX_DCOC_RANGE_324___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_324__RX_DCOC_RES_I_324___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_324__RX_DCOC_RES_Q_324___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_324__RX_DCOC_RANGE_324___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_324__RX_DCOC_RANGE_324___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_324__RX_DCOC_RES_I_324___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_324__RX_DCOC_RES_I_324___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_324__RX_DCOC_RES_Q_324___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_324__RX_DCOC_RES_Q_324___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_324___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_324___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_325 (0x005EC514) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_325___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_325___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_325__RX_DCOC_RANGE_325___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_325__RX_DCOC_RES_I_325___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_325__RX_DCOC_RES_Q_325___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_325__RX_DCOC_RANGE_325___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_325__RX_DCOC_RANGE_325___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_325__RX_DCOC_RES_I_325___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_325__RX_DCOC_RES_I_325___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_325__RX_DCOC_RES_Q_325___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_325__RX_DCOC_RES_Q_325___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_325___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_325___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_326 (0x005EC518) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_326___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_326___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_326__RX_DCOC_RANGE_326___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_326__RX_DCOC_RES_I_326___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_326__RX_DCOC_RES_Q_326___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_326__RX_DCOC_RANGE_326___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_326__RX_DCOC_RANGE_326___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_326__RX_DCOC_RES_I_326___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_326__RX_DCOC_RES_I_326___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_326__RX_DCOC_RES_Q_326___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_326__RX_DCOC_RES_Q_326___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_326___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_326___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_327 (0x005EC51C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_327___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_327___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_327__RX_DCOC_RANGE_327___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_327__RX_DCOC_RES_I_327___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_327__RX_DCOC_RES_Q_327___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_327__RX_DCOC_RANGE_327___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_327__RX_DCOC_RANGE_327___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_327__RX_DCOC_RES_I_327___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_327__RX_DCOC_RES_I_327___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_327__RX_DCOC_RES_Q_327___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_327__RX_DCOC_RES_Q_327___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_327___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_327___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_328 (0x005EC520) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_328___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_328___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_328__RX_DCOC_RANGE_328___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_328__RX_DCOC_RES_I_328___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_328__RX_DCOC_RES_Q_328___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_328__RX_DCOC_RANGE_328___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_328__RX_DCOC_RANGE_328___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_328__RX_DCOC_RES_I_328___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_328__RX_DCOC_RES_I_328___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_328__RX_DCOC_RES_Q_328___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_328__RX_DCOC_RES_Q_328___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_328___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_328___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_329 (0x005EC524) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_329___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_329___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_329__RX_DCOC_RANGE_329___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_329__RX_DCOC_RES_I_329___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_329__RX_DCOC_RES_Q_329___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_329__RX_DCOC_RANGE_329___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_329__RX_DCOC_RANGE_329___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_329__RX_DCOC_RES_I_329___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_329__RX_DCOC_RES_I_329___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_329__RX_DCOC_RES_Q_329___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_329__RX_DCOC_RES_Q_329___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_329___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_329___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_330 (0x005EC528) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_330___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_330___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_330__RX_DCOC_RANGE_330___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_330__RX_DCOC_RES_I_330___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_330__RX_DCOC_RES_Q_330___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_330__RX_DCOC_RANGE_330___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_330__RX_DCOC_RANGE_330___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_330__RX_DCOC_RES_I_330___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_330__RX_DCOC_RES_I_330___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_330__RX_DCOC_RES_Q_330___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_330__RX_DCOC_RES_Q_330___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_330___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_330___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_331 (0x005EC52C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_331___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_331___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_331__RX_DCOC_RANGE_331___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_331__RX_DCOC_RES_I_331___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_331__RX_DCOC_RES_Q_331___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_331__RX_DCOC_RANGE_331___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_331__RX_DCOC_RANGE_331___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_331__RX_DCOC_RES_I_331___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_331__RX_DCOC_RES_I_331___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_331__RX_DCOC_RES_Q_331___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_331__RX_DCOC_RES_Q_331___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_331___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_331___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_332 (0x005EC530) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_332___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_332___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_332__RX_DCOC_RANGE_332___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_332__RX_DCOC_RES_I_332___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_332__RX_DCOC_RES_Q_332___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_332__RX_DCOC_RANGE_332___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_332__RX_DCOC_RANGE_332___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_332__RX_DCOC_RES_I_332___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_332__RX_DCOC_RES_I_332___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_332__RX_DCOC_RES_Q_332___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_332__RX_DCOC_RES_Q_332___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_332___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_332___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_333 (0x005EC534) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_333___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_333___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_333__RX_DCOC_RANGE_333___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_333__RX_DCOC_RES_I_333___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_333__RX_DCOC_RES_Q_333___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_333__RX_DCOC_RANGE_333___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_333__RX_DCOC_RANGE_333___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_333__RX_DCOC_RES_I_333___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_333__RX_DCOC_RES_I_333___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_333__RX_DCOC_RES_Q_333___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_333__RX_DCOC_RES_Q_333___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_333___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_333___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_334 (0x005EC538) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_334___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_334___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_334__RX_DCOC_RANGE_334___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_334__RX_DCOC_RES_I_334___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_334__RX_DCOC_RES_Q_334___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_334__RX_DCOC_RANGE_334___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_334__RX_DCOC_RANGE_334___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_334__RX_DCOC_RES_I_334___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_334__RX_DCOC_RES_I_334___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_334__RX_DCOC_RES_Q_334___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_334__RX_DCOC_RES_Q_334___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_334___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_334___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_335 (0x005EC53C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_335___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_335___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_335__RX_DCOC_RANGE_335___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_335__RX_DCOC_RES_I_335___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_335__RX_DCOC_RES_Q_335___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_335__RX_DCOC_RANGE_335___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_335__RX_DCOC_RANGE_335___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_335__RX_DCOC_RES_I_335___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_335__RX_DCOC_RES_I_335___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_335__RX_DCOC_RES_Q_335___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_335__RX_DCOC_RES_Q_335___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_335___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_335___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_336 (0x005EC540) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_336___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_336___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_336__RX_DCOC_RANGE_336___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_336__RX_DCOC_RES_I_336___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_336__RX_DCOC_RES_Q_336___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_336__RX_DCOC_RANGE_336___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_336__RX_DCOC_RANGE_336___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_336__RX_DCOC_RES_I_336___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_336__RX_DCOC_RES_I_336___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_336__RX_DCOC_RES_Q_336___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_336__RX_DCOC_RES_Q_336___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_336___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_336___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_337 (0x005EC544) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_337___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_337___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_337__RX_DCOC_RANGE_337___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_337__RX_DCOC_RES_I_337___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_337__RX_DCOC_RES_Q_337___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_337__RX_DCOC_RANGE_337___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_337__RX_DCOC_RANGE_337___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_337__RX_DCOC_RES_I_337___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_337__RX_DCOC_RES_I_337___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_337__RX_DCOC_RES_Q_337___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_337__RX_DCOC_RES_Q_337___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_337___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_337___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_338 (0x005EC548) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_338___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_338___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_338__RX_DCOC_RANGE_338___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_338__RX_DCOC_RES_I_338___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_338__RX_DCOC_RES_Q_338___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_338__RX_DCOC_RANGE_338___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_338__RX_DCOC_RANGE_338___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_338__RX_DCOC_RES_I_338___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_338__RX_DCOC_RES_I_338___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_338__RX_DCOC_RES_Q_338___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_338__RX_DCOC_RES_Q_338___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_338___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_338___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_339 (0x005EC54C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_339___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_339___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_339__RX_DCOC_RANGE_339___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_339__RX_DCOC_RES_I_339___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_339__RX_DCOC_RES_Q_339___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_339__RX_DCOC_RANGE_339___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_339__RX_DCOC_RANGE_339___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_339__RX_DCOC_RES_I_339___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_339__RX_DCOC_RES_I_339___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_339__RX_DCOC_RES_Q_339___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_339__RX_DCOC_RES_Q_339___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_339___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_339___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_340 (0x005EC550) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_340___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_340___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_340__RX_DCOC_RANGE_340___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_340__RX_DCOC_RES_I_340___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_340__RX_DCOC_RES_Q_340___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_340__RX_DCOC_RANGE_340___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_340__RX_DCOC_RANGE_340___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_340__RX_DCOC_RES_I_340___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_340__RX_DCOC_RES_I_340___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_340__RX_DCOC_RES_Q_340___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_340__RX_DCOC_RES_Q_340___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_340___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_340___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_341 (0x005EC554) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_341___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_341___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_341__RX_DCOC_RANGE_341___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_341__RX_DCOC_RES_I_341___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_341__RX_DCOC_RES_Q_341___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_341__RX_DCOC_RANGE_341___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_341__RX_DCOC_RANGE_341___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_341__RX_DCOC_RES_I_341___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_341__RX_DCOC_RES_I_341___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_341__RX_DCOC_RES_Q_341___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_341__RX_DCOC_RES_Q_341___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_341___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_341___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_342 (0x005EC558) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_342___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_342___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_342__RX_DCOC_RANGE_342___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_342__RX_DCOC_RES_I_342___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_342__RX_DCOC_RES_Q_342___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_342__RX_DCOC_RANGE_342___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_342__RX_DCOC_RANGE_342___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_342__RX_DCOC_RES_I_342___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_342__RX_DCOC_RES_I_342___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_342__RX_DCOC_RES_Q_342___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_342__RX_DCOC_RES_Q_342___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_342___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_342___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_343 (0x005EC55C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_343___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_343___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_343__RX_DCOC_RANGE_343___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_343__RX_DCOC_RES_I_343___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_343__RX_DCOC_RES_Q_343___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_343__RX_DCOC_RANGE_343___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_343__RX_DCOC_RANGE_343___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_343__RX_DCOC_RES_I_343___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_343__RX_DCOC_RES_I_343___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_343__RX_DCOC_RES_Q_343___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_343__RX_DCOC_RES_Q_343___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_343___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_343___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_344 (0x005EC560) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_344___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_344___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_344__RX_DCOC_RANGE_344___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_344__RX_DCOC_RES_I_344___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_344__RX_DCOC_RES_Q_344___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_344__RX_DCOC_RANGE_344___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_344__RX_DCOC_RANGE_344___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_344__RX_DCOC_RES_I_344___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_344__RX_DCOC_RES_I_344___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_344__RX_DCOC_RES_Q_344___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_344__RX_DCOC_RES_Q_344___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_344___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_344___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_345 (0x005EC564) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_345___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_345___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_345__RX_DCOC_RANGE_345___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_345__RX_DCOC_RES_I_345___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_345__RX_DCOC_RES_Q_345___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_345__RX_DCOC_RANGE_345___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_345__RX_DCOC_RANGE_345___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_345__RX_DCOC_RES_I_345___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_345__RX_DCOC_RES_I_345___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_345__RX_DCOC_RES_Q_345___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_345__RX_DCOC_RES_Q_345___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_345___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_345___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_346 (0x005EC568) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_346___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_346___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_346__RX_DCOC_RANGE_346___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_346__RX_DCOC_RES_I_346___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_346__RX_DCOC_RES_Q_346___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_346__RX_DCOC_RANGE_346___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_346__RX_DCOC_RANGE_346___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_346__RX_DCOC_RES_I_346___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_346__RX_DCOC_RES_I_346___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_346__RX_DCOC_RES_Q_346___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_346__RX_DCOC_RES_Q_346___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_346___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_346___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_347 (0x005EC56C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_347___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_347___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_347__RX_DCOC_RANGE_347___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_347__RX_DCOC_RES_I_347___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_347__RX_DCOC_RES_Q_347___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_347__RX_DCOC_RANGE_347___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_347__RX_DCOC_RANGE_347___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_347__RX_DCOC_RES_I_347___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_347__RX_DCOC_RES_I_347___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_347__RX_DCOC_RES_Q_347___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_347__RX_DCOC_RES_Q_347___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_347___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_347___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_348 (0x005EC570) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_348___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_348___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_348__RX_DCOC_RANGE_348___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_348__RX_DCOC_RES_I_348___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_348__RX_DCOC_RES_Q_348___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_348__RX_DCOC_RANGE_348___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_348__RX_DCOC_RANGE_348___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_348__RX_DCOC_RES_I_348___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_348__RX_DCOC_RES_I_348___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_348__RX_DCOC_RES_Q_348___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_348__RX_DCOC_RES_Q_348___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_348___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_348___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_349 (0x005EC574) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_349___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_349___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_349__RX_DCOC_RANGE_349___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_349__RX_DCOC_RES_I_349___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_349__RX_DCOC_RES_Q_349___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_349__RX_DCOC_RANGE_349___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_349__RX_DCOC_RANGE_349___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_349__RX_DCOC_RES_I_349___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_349__RX_DCOC_RES_I_349___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_349__RX_DCOC_RES_Q_349___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_349__RX_DCOC_RES_Q_349___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_349___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_349___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_350 (0x005EC578) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_350___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_350___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_350__RX_DCOC_RANGE_350___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_350__RX_DCOC_RES_I_350___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_350__RX_DCOC_RES_Q_350___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_350__RX_DCOC_RANGE_350___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_350__RX_DCOC_RANGE_350___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_350__RX_DCOC_RES_I_350___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_350__RX_DCOC_RES_I_350___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_350__RX_DCOC_RES_Q_350___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_350__RX_DCOC_RES_Q_350___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_350___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_350___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_351 (0x005EC57C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_351___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_351___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_351__RX_DCOC_RANGE_351___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_351__RX_DCOC_RES_I_351___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_351__RX_DCOC_RES_Q_351___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_351__RX_DCOC_RANGE_351___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_351__RX_DCOC_RANGE_351___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_351__RX_DCOC_RES_I_351___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_351__RX_DCOC_RES_I_351___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_351__RX_DCOC_RES_Q_351___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_351__RX_DCOC_RES_Q_351___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_351___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_351___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_352 (0x005EC580) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_352___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_352___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_352__RX_DCOC_RANGE_352___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_352__RX_DCOC_RES_I_352___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_352__RX_DCOC_RES_Q_352___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_352__RX_DCOC_RANGE_352___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_352__RX_DCOC_RANGE_352___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_352__RX_DCOC_RES_I_352___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_352__RX_DCOC_RES_I_352___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_352__RX_DCOC_RES_Q_352___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_352__RX_DCOC_RES_Q_352___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_352___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_352___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_353 (0x005EC584) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_353___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_353___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_353__RX_DCOC_RANGE_353___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_353__RX_DCOC_RES_I_353___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_353__RX_DCOC_RES_Q_353___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_353__RX_DCOC_RANGE_353___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_353__RX_DCOC_RANGE_353___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_353__RX_DCOC_RES_I_353___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_353__RX_DCOC_RES_I_353___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_353__RX_DCOC_RES_Q_353___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_353__RX_DCOC_RES_Q_353___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_353___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_353___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_354 (0x005EC588) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_354___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_354___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_354__RX_DCOC_RANGE_354___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_354__RX_DCOC_RES_I_354___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_354__RX_DCOC_RES_Q_354___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_354__RX_DCOC_RANGE_354___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_354__RX_DCOC_RANGE_354___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_354__RX_DCOC_RES_I_354___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_354__RX_DCOC_RES_I_354___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_354__RX_DCOC_RES_Q_354___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_354__RX_DCOC_RES_Q_354___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_354___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_354___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_355 (0x005EC58C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_355___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_355___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_355__RX_DCOC_RANGE_355___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_355__RX_DCOC_RES_I_355___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_355__RX_DCOC_RES_Q_355___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_355__RX_DCOC_RANGE_355___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_355__RX_DCOC_RANGE_355___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_355__RX_DCOC_RES_I_355___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_355__RX_DCOC_RES_I_355___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_355__RX_DCOC_RES_Q_355___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_355__RX_DCOC_RES_Q_355___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_355___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_355___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_356 (0x005EC590) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_356___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_356___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_356__RX_DCOC_RANGE_356___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_356__RX_DCOC_RES_I_356___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_356__RX_DCOC_RES_Q_356___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_356__RX_DCOC_RANGE_356___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_356__RX_DCOC_RANGE_356___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_356__RX_DCOC_RES_I_356___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_356__RX_DCOC_RES_I_356___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_356__RX_DCOC_RES_Q_356___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_356__RX_DCOC_RES_Q_356___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_356___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_356___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_357 (0x005EC594) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_357___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_357___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_357__RX_DCOC_RANGE_357___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_357__RX_DCOC_RES_I_357___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_357__RX_DCOC_RES_Q_357___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_357__RX_DCOC_RANGE_357___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_357__RX_DCOC_RANGE_357___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_357__RX_DCOC_RES_I_357___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_357__RX_DCOC_RES_I_357___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_357__RX_DCOC_RES_Q_357___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_357__RX_DCOC_RES_Q_357___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_357___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_357___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_358 (0x005EC598) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_358___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_358___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_358__RX_DCOC_RANGE_358___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_358__RX_DCOC_RES_I_358___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_358__RX_DCOC_RES_Q_358___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_358__RX_DCOC_RANGE_358___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_358__RX_DCOC_RANGE_358___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_358__RX_DCOC_RES_I_358___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_358__RX_DCOC_RES_I_358___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_358__RX_DCOC_RES_Q_358___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_358__RX_DCOC_RES_Q_358___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_358___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_358___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_359 (0x005EC59C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_359___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_359___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_359__RX_DCOC_RANGE_359___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_359__RX_DCOC_RES_I_359___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_359__RX_DCOC_RES_Q_359___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_359__RX_DCOC_RANGE_359___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_359__RX_DCOC_RANGE_359___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_359__RX_DCOC_RES_I_359___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_359__RX_DCOC_RES_I_359___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_359__RX_DCOC_RES_Q_359___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_359__RX_DCOC_RES_Q_359___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_359___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_359___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_360 (0x005EC5A0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_360___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_360___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_360__RX_DCOC_RANGE_360___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_360__RX_DCOC_RES_I_360___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_360__RX_DCOC_RES_Q_360___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_360__RX_DCOC_RANGE_360___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_360__RX_DCOC_RANGE_360___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_360__RX_DCOC_RES_I_360___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_360__RX_DCOC_RES_I_360___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_360__RX_DCOC_RES_Q_360___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_360__RX_DCOC_RES_Q_360___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_360___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_360___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_361 (0x005EC5A4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_361___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_361___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_361__RX_DCOC_RANGE_361___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_361__RX_DCOC_RES_I_361___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_361__RX_DCOC_RES_Q_361___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_361__RX_DCOC_RANGE_361___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_361__RX_DCOC_RANGE_361___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_361__RX_DCOC_RES_I_361___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_361__RX_DCOC_RES_I_361___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_361__RX_DCOC_RES_Q_361___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_361__RX_DCOC_RES_Q_361___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_361___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_361___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_362 (0x005EC5A8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_362___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_362___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_362__RX_DCOC_RANGE_362___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_362__RX_DCOC_RES_I_362___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_362__RX_DCOC_RES_Q_362___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_362__RX_DCOC_RANGE_362___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_362__RX_DCOC_RANGE_362___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_362__RX_DCOC_RES_I_362___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_362__RX_DCOC_RES_I_362___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_362__RX_DCOC_RES_Q_362___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_362__RX_DCOC_RES_Q_362___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_362___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_362___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_363 (0x005EC5AC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_363___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_363___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_363__RX_DCOC_RANGE_363___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_363__RX_DCOC_RES_I_363___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_363__RX_DCOC_RES_Q_363___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_363__RX_DCOC_RANGE_363___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_363__RX_DCOC_RANGE_363___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_363__RX_DCOC_RES_I_363___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_363__RX_DCOC_RES_I_363___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_363__RX_DCOC_RES_Q_363___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_363__RX_DCOC_RES_Q_363___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_363___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_363___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_364 (0x005EC5B0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_364___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_364___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_364__RX_DCOC_RANGE_364___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_364__RX_DCOC_RES_I_364___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_364__RX_DCOC_RES_Q_364___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_364__RX_DCOC_RANGE_364___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_364__RX_DCOC_RANGE_364___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_364__RX_DCOC_RES_I_364___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_364__RX_DCOC_RES_I_364___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_364__RX_DCOC_RES_Q_364___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_364__RX_DCOC_RES_Q_364___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_364___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_364___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_365 (0x005EC5B4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_365___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_365___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_365__RX_DCOC_RANGE_365___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_365__RX_DCOC_RES_I_365___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_365__RX_DCOC_RES_Q_365___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_365__RX_DCOC_RANGE_365___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_365__RX_DCOC_RANGE_365___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_365__RX_DCOC_RES_I_365___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_365__RX_DCOC_RES_I_365___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_365__RX_DCOC_RES_Q_365___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_365__RX_DCOC_RES_Q_365___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_365___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_365___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_366 (0x005EC5B8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_366___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_366___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_366__RX_DCOC_RANGE_366___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_366__RX_DCOC_RES_I_366___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_366__RX_DCOC_RES_Q_366___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_366__RX_DCOC_RANGE_366___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_366__RX_DCOC_RANGE_366___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_366__RX_DCOC_RES_I_366___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_366__RX_DCOC_RES_I_366___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_366__RX_DCOC_RES_Q_366___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_366__RX_DCOC_RES_Q_366___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_366___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_366___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_367 (0x005EC5BC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_367___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_367___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_367__RX_DCOC_RANGE_367___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_367__RX_DCOC_RES_I_367___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_367__RX_DCOC_RES_Q_367___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_367__RX_DCOC_RANGE_367___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_367__RX_DCOC_RANGE_367___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_367__RX_DCOC_RES_I_367___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_367__RX_DCOC_RES_I_367___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_367__RX_DCOC_RES_Q_367___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_367__RX_DCOC_RES_Q_367___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_367___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_367___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_368 (0x005EC5C0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_368___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_368___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_368__RX_DCOC_RANGE_368___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_368__RX_DCOC_RES_I_368___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_368__RX_DCOC_RES_Q_368___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_368__RX_DCOC_RANGE_368___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_368__RX_DCOC_RANGE_368___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_368__RX_DCOC_RES_I_368___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_368__RX_DCOC_RES_I_368___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_368__RX_DCOC_RES_Q_368___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_368__RX_DCOC_RES_Q_368___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_368___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_368___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_369 (0x005EC5C4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_369___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_369___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_369__RX_DCOC_RANGE_369___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_369__RX_DCOC_RES_I_369___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_369__RX_DCOC_RES_Q_369___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_369__RX_DCOC_RANGE_369___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_369__RX_DCOC_RANGE_369___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_369__RX_DCOC_RES_I_369___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_369__RX_DCOC_RES_I_369___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_369__RX_DCOC_RES_Q_369___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_369__RX_DCOC_RES_Q_369___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_369___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_369___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_370 (0x005EC5C8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_370___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_370___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_370__RX_DCOC_RANGE_370___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_370__RX_DCOC_RES_I_370___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_370__RX_DCOC_RES_Q_370___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_370__RX_DCOC_RANGE_370___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_370__RX_DCOC_RANGE_370___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_370__RX_DCOC_RES_I_370___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_370__RX_DCOC_RES_I_370___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_370__RX_DCOC_RES_Q_370___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_370__RX_DCOC_RES_Q_370___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_370___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_370___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_371 (0x005EC5CC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_371___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_371___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_371__RX_DCOC_RANGE_371___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_371__RX_DCOC_RES_I_371___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_371__RX_DCOC_RES_Q_371___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_371__RX_DCOC_RANGE_371___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_371__RX_DCOC_RANGE_371___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_371__RX_DCOC_RES_I_371___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_371__RX_DCOC_RES_I_371___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_371__RX_DCOC_RES_Q_371___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_371__RX_DCOC_RES_Q_371___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_371___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_371___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_372 (0x005EC5D0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_372___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_372___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_372__RX_DCOC_RANGE_372___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_372__RX_DCOC_RES_I_372___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_372__RX_DCOC_RES_Q_372___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_372__RX_DCOC_RANGE_372___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_372__RX_DCOC_RANGE_372___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_372__RX_DCOC_RES_I_372___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_372__RX_DCOC_RES_I_372___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_372__RX_DCOC_RES_Q_372___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_372__RX_DCOC_RES_Q_372___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_372___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_372___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_373 (0x005EC5D4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_373___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_373___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_373__RX_DCOC_RANGE_373___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_373__RX_DCOC_RES_I_373___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_373__RX_DCOC_RES_Q_373___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_373__RX_DCOC_RANGE_373___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_373__RX_DCOC_RANGE_373___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_373__RX_DCOC_RES_I_373___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_373__RX_DCOC_RES_I_373___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_373__RX_DCOC_RES_Q_373___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_373__RX_DCOC_RES_Q_373___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_373___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_373___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_374 (0x005EC5D8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_374___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_374___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_374__RX_DCOC_RANGE_374___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_374__RX_DCOC_RES_I_374___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_374__RX_DCOC_RES_Q_374___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_374__RX_DCOC_RANGE_374___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_374__RX_DCOC_RANGE_374___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_374__RX_DCOC_RES_I_374___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_374__RX_DCOC_RES_I_374___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_374__RX_DCOC_RES_Q_374___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_374__RX_DCOC_RES_Q_374___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_374___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_374___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_375 (0x005EC5DC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_375___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_375___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_375__RX_DCOC_RANGE_375___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_375__RX_DCOC_RES_I_375___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_375__RX_DCOC_RES_Q_375___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_375__RX_DCOC_RANGE_375___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_375__RX_DCOC_RANGE_375___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_375__RX_DCOC_RES_I_375___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_375__RX_DCOC_RES_I_375___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_375__RX_DCOC_RES_Q_375___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_375__RX_DCOC_RES_Q_375___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_375___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_375___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_376 (0x005EC5E0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_376___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_376___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_376__RX_DCOC_RANGE_376___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_376__RX_DCOC_RES_I_376___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_376__RX_DCOC_RES_Q_376___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_376__RX_DCOC_RANGE_376___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_376__RX_DCOC_RANGE_376___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_376__RX_DCOC_RES_I_376___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_376__RX_DCOC_RES_I_376___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_376__RX_DCOC_RES_Q_376___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_376__RX_DCOC_RES_Q_376___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_376___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_376___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_377 (0x005EC5E4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_377___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_377___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_377__RX_DCOC_RANGE_377___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_377__RX_DCOC_RES_I_377___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_377__RX_DCOC_RES_Q_377___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_377__RX_DCOC_RANGE_377___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_377__RX_DCOC_RANGE_377___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_377__RX_DCOC_RES_I_377___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_377__RX_DCOC_RES_I_377___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_377__RX_DCOC_RES_Q_377___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_377__RX_DCOC_RES_Q_377___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_377___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_377___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_378 (0x005EC5E8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_378___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_378___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_378__RX_DCOC_RANGE_378___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_378__RX_DCOC_RES_I_378___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_378__RX_DCOC_RES_Q_378___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_378__RX_DCOC_RANGE_378___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_378__RX_DCOC_RANGE_378___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_378__RX_DCOC_RES_I_378___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_378__RX_DCOC_RES_I_378___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_378__RX_DCOC_RES_Q_378___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_378__RX_DCOC_RES_Q_378___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_378___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_378___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_379 (0x005EC5EC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_379___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_379___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_379__RX_DCOC_RANGE_379___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_379__RX_DCOC_RES_I_379___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_379__RX_DCOC_RES_Q_379___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_379__RX_DCOC_RANGE_379___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_379__RX_DCOC_RANGE_379___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_379__RX_DCOC_RES_I_379___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_379__RX_DCOC_RES_I_379___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_379__RX_DCOC_RES_Q_379___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_379__RX_DCOC_RES_Q_379___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_379___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_379___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_380 (0x005EC5F0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_380___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_380___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_380__RX_DCOC_RANGE_380___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_380__RX_DCOC_RES_I_380___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_380__RX_DCOC_RES_Q_380___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_380__RX_DCOC_RANGE_380___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_380__RX_DCOC_RANGE_380___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_380__RX_DCOC_RES_I_380___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_380__RX_DCOC_RES_I_380___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_380__RX_DCOC_RES_Q_380___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_380__RX_DCOC_RES_Q_380___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_380___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_380___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_381 (0x005EC5F4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_381___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_381___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_381__RX_DCOC_RANGE_381___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_381__RX_DCOC_RES_I_381___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_381__RX_DCOC_RES_Q_381___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_381__RX_DCOC_RANGE_381___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_381__RX_DCOC_RANGE_381___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_381__RX_DCOC_RES_I_381___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_381__RX_DCOC_RES_I_381___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_381__RX_DCOC_RES_Q_381___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_381__RX_DCOC_RES_Q_381___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_381___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_381___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_382 (0x005EC5F8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_382___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_382___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_382__RX_DCOC_RANGE_382___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_382__RX_DCOC_RES_I_382___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_382__RX_DCOC_RES_Q_382___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_382__RX_DCOC_RANGE_382___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_382__RX_DCOC_RANGE_382___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_382__RX_DCOC_RES_I_382___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_382__RX_DCOC_RES_I_382___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_382__RX_DCOC_RES_Q_382___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_382__RX_DCOC_RES_Q_382___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_382___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_382___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_383 (0x005EC5FC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_383___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_383___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_383__RX_DCOC_RANGE_383___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_383__RX_DCOC_RES_I_383___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_383__RX_DCOC_RES_Q_383___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_383__RX_DCOC_RANGE_383___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_383__RX_DCOC_RANGE_383___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_383__RX_DCOC_RES_I_383___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_383__RX_DCOC_RES_I_383___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_383__RX_DCOC_RES_Q_383___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_383__RX_DCOC_RES_Q_383___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_383___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_383___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_384 (0x005EC600) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_384___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_384___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_384__RX_DCOC_RANGE_384___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_384__RX_DCOC_RES_I_384___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_384__RX_DCOC_RES_Q_384___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_384__RX_DCOC_RANGE_384___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_384__RX_DCOC_RANGE_384___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_384__RX_DCOC_RES_I_384___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_384__RX_DCOC_RES_I_384___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_384__RX_DCOC_RES_Q_384___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_384__RX_DCOC_RES_Q_384___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_384___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_384___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_385 (0x005EC604) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_385___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_385___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_385__RX_DCOC_RANGE_385___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_385__RX_DCOC_RES_I_385___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_385__RX_DCOC_RES_Q_385___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_385__RX_DCOC_RANGE_385___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_385__RX_DCOC_RANGE_385___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_385__RX_DCOC_RES_I_385___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_385__RX_DCOC_RES_I_385___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_385__RX_DCOC_RES_Q_385___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_385__RX_DCOC_RES_Q_385___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_385___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_385___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_386 (0x005EC608) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_386___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_386___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_386__RX_DCOC_RANGE_386___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_386__RX_DCOC_RES_I_386___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_386__RX_DCOC_RES_Q_386___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_386__RX_DCOC_RANGE_386___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_386__RX_DCOC_RANGE_386___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_386__RX_DCOC_RES_I_386___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_386__RX_DCOC_RES_I_386___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_386__RX_DCOC_RES_Q_386___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_386__RX_DCOC_RES_Q_386___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_386___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_386___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_387 (0x005EC60C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_387___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_387___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_387__RX_DCOC_RANGE_387___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_387__RX_DCOC_RES_I_387___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_387__RX_DCOC_RES_Q_387___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_387__RX_DCOC_RANGE_387___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_387__RX_DCOC_RANGE_387___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_387__RX_DCOC_RES_I_387___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_387__RX_DCOC_RES_I_387___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_387__RX_DCOC_RES_Q_387___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_387__RX_DCOC_RES_Q_387___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_387___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_387___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_388 (0x005EC610) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_388___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_388___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_388__RX_DCOC_RANGE_388___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_388__RX_DCOC_RES_I_388___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_388__RX_DCOC_RES_Q_388___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_388__RX_DCOC_RANGE_388___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_388__RX_DCOC_RANGE_388___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_388__RX_DCOC_RES_I_388___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_388__RX_DCOC_RES_I_388___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_388__RX_DCOC_RES_Q_388___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_388__RX_DCOC_RES_Q_388___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_388___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_388___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_389 (0x005EC614) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_389___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_389___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_389__RX_DCOC_RANGE_389___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_389__RX_DCOC_RES_I_389___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_389__RX_DCOC_RES_Q_389___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_389__RX_DCOC_RANGE_389___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_389__RX_DCOC_RANGE_389___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_389__RX_DCOC_RES_I_389___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_389__RX_DCOC_RES_I_389___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_389__RX_DCOC_RES_Q_389___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_389__RX_DCOC_RES_Q_389___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_389___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_389___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_390 (0x005EC618) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_390___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_390___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_390__RX_DCOC_RANGE_390___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_390__RX_DCOC_RES_I_390___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_390__RX_DCOC_RES_Q_390___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_390__RX_DCOC_RANGE_390___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_390__RX_DCOC_RANGE_390___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_390__RX_DCOC_RES_I_390___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_390__RX_DCOC_RES_I_390___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_390__RX_DCOC_RES_Q_390___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_390__RX_DCOC_RES_Q_390___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_390___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_390___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_391 (0x005EC61C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_391___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_391___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_391__RX_DCOC_RANGE_391___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_391__RX_DCOC_RES_I_391___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_391__RX_DCOC_RES_Q_391___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_391__RX_DCOC_RANGE_391___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_391__RX_DCOC_RANGE_391___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_391__RX_DCOC_RES_I_391___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_391__RX_DCOC_RES_I_391___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_391__RX_DCOC_RES_Q_391___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_391__RX_DCOC_RES_Q_391___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_391___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_391___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_392 (0x005EC620) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_392___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_392___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_392__RX_DCOC_RANGE_392___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_392__RX_DCOC_RES_I_392___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_392__RX_DCOC_RES_Q_392___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_392__RX_DCOC_RANGE_392___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_392__RX_DCOC_RANGE_392___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_392__RX_DCOC_RES_I_392___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_392__RX_DCOC_RES_I_392___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_392__RX_DCOC_RES_Q_392___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_392__RX_DCOC_RES_Q_392___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_392___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_392___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_393 (0x005EC624) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_393___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_393___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_393__RX_DCOC_RANGE_393___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_393__RX_DCOC_RES_I_393___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_393__RX_DCOC_RES_Q_393___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_393__RX_DCOC_RANGE_393___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_393__RX_DCOC_RANGE_393___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_393__RX_DCOC_RES_I_393___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_393__RX_DCOC_RES_I_393___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_393__RX_DCOC_RES_Q_393___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_393__RX_DCOC_RES_Q_393___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_393___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_393___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_394 (0x005EC628) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_394___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_394___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_394__RX_DCOC_RANGE_394___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_394__RX_DCOC_RES_I_394___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_394__RX_DCOC_RES_Q_394___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_394__RX_DCOC_RANGE_394___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_394__RX_DCOC_RANGE_394___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_394__RX_DCOC_RES_I_394___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_394__RX_DCOC_RES_I_394___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_394__RX_DCOC_RES_Q_394___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_394__RX_DCOC_RES_Q_394___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_394___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_394___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_395 (0x005EC62C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_395___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_395___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_395__RX_DCOC_RANGE_395___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_395__RX_DCOC_RES_I_395___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_395__RX_DCOC_RES_Q_395___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_395__RX_DCOC_RANGE_395___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_395__RX_DCOC_RANGE_395___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_395__RX_DCOC_RES_I_395___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_395__RX_DCOC_RES_I_395___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_395__RX_DCOC_RES_Q_395___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_395__RX_DCOC_RES_Q_395___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_395___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_395___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_396 (0x005EC630) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_396___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_396___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_396__RX_DCOC_RANGE_396___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_396__RX_DCOC_RES_I_396___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_396__RX_DCOC_RES_Q_396___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_396__RX_DCOC_RANGE_396___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_396__RX_DCOC_RANGE_396___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_396__RX_DCOC_RES_I_396___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_396__RX_DCOC_RES_I_396___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_396__RX_DCOC_RES_Q_396___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_396__RX_DCOC_RES_Q_396___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_396___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_396___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_397 (0x005EC634) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_397___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_397___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_397__RX_DCOC_RANGE_397___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_397__RX_DCOC_RES_I_397___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_397__RX_DCOC_RES_Q_397___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_397__RX_DCOC_RANGE_397___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_397__RX_DCOC_RANGE_397___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_397__RX_DCOC_RES_I_397___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_397__RX_DCOC_RES_I_397___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_397__RX_DCOC_RES_Q_397___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_397__RX_DCOC_RES_Q_397___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_397___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_397___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_398 (0x005EC638) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_398___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_398___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_398__RX_DCOC_RANGE_398___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_398__RX_DCOC_RES_I_398___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_398__RX_DCOC_RES_Q_398___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_398__RX_DCOC_RANGE_398___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_398__RX_DCOC_RANGE_398___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_398__RX_DCOC_RES_I_398___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_398__RX_DCOC_RES_I_398___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_398__RX_DCOC_RES_Q_398___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_398__RX_DCOC_RES_Q_398___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_398___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_398___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_399 (0x005EC63C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_399___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_399___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_399__RX_DCOC_RANGE_399___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_399__RX_DCOC_RES_I_399___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_399__RX_DCOC_RES_Q_399___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_399__RX_DCOC_RANGE_399___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_399__RX_DCOC_RANGE_399___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_399__RX_DCOC_RES_I_399___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_399__RX_DCOC_RES_I_399___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_399__RX_DCOC_RES_Q_399___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_399__RX_DCOC_RES_Q_399___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_399___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_399___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_400 (0x005EC640) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_400___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_400___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_400__RX_DCOC_RANGE_400___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_400__RX_DCOC_RES_I_400___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_400__RX_DCOC_RES_Q_400___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_400__RX_DCOC_RANGE_400___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_400__RX_DCOC_RANGE_400___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_400__RX_DCOC_RES_I_400___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_400__RX_DCOC_RES_I_400___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_400__RX_DCOC_RES_Q_400___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_400__RX_DCOC_RES_Q_400___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_400___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_400___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_401 (0x005EC644) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_401___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_401___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_401__RX_DCOC_RANGE_401___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_401__RX_DCOC_RES_I_401___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_401__RX_DCOC_RES_Q_401___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_401__RX_DCOC_RANGE_401___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_401__RX_DCOC_RANGE_401___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_401__RX_DCOC_RES_I_401___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_401__RX_DCOC_RES_I_401___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_401__RX_DCOC_RES_Q_401___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_401__RX_DCOC_RES_Q_401___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_401___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_401___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_402 (0x005EC648) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_402___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_402___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_402__RX_DCOC_RANGE_402___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_402__RX_DCOC_RES_I_402___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_402__RX_DCOC_RES_Q_402___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_402__RX_DCOC_RANGE_402___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_402__RX_DCOC_RANGE_402___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_402__RX_DCOC_RES_I_402___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_402__RX_DCOC_RES_I_402___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_402__RX_DCOC_RES_Q_402___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_402__RX_DCOC_RES_Q_402___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_402___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_402___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_403 (0x005EC64C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_403___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_403___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_403__RX_DCOC_RANGE_403___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_403__RX_DCOC_RES_I_403___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_403__RX_DCOC_RES_Q_403___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_403__RX_DCOC_RANGE_403___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_403__RX_DCOC_RANGE_403___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_403__RX_DCOC_RES_I_403___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_403__RX_DCOC_RES_I_403___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_403__RX_DCOC_RES_Q_403___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_403__RX_DCOC_RES_Q_403___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_403___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_403___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_404 (0x005EC650) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_404___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_404___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_404__RX_DCOC_RANGE_404___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_404__RX_DCOC_RES_I_404___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_404__RX_DCOC_RES_Q_404___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_404__RX_DCOC_RANGE_404___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_404__RX_DCOC_RANGE_404___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_404__RX_DCOC_RES_I_404___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_404__RX_DCOC_RES_I_404___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_404__RX_DCOC_RES_Q_404___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_404__RX_DCOC_RES_Q_404___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_404___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_404___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_405 (0x005EC654) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_405___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_405___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_405__RX_DCOC_RANGE_405___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_405__RX_DCOC_RES_I_405___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_405__RX_DCOC_RES_Q_405___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_405__RX_DCOC_RANGE_405___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_405__RX_DCOC_RANGE_405___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_405__RX_DCOC_RES_I_405___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_405__RX_DCOC_RES_I_405___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_405__RX_DCOC_RES_Q_405___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_405__RX_DCOC_RES_Q_405___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_405___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_405___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_406 (0x005EC658) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_406___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_406___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_406__RX_DCOC_RANGE_406___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_406__RX_DCOC_RES_I_406___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_406__RX_DCOC_RES_Q_406___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_406__RX_DCOC_RANGE_406___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_406__RX_DCOC_RANGE_406___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_406__RX_DCOC_RES_I_406___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_406__RX_DCOC_RES_I_406___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_406__RX_DCOC_RES_Q_406___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_406__RX_DCOC_RES_Q_406___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_406___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_406___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_407 (0x005EC65C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_407___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_407___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_407__RX_DCOC_RANGE_407___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_407__RX_DCOC_RES_I_407___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_407__RX_DCOC_RES_Q_407___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_407__RX_DCOC_RANGE_407___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_407__RX_DCOC_RANGE_407___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_407__RX_DCOC_RES_I_407___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_407__RX_DCOC_RES_I_407___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_407__RX_DCOC_RES_Q_407___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_407__RX_DCOC_RES_Q_407___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_407___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_407___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_408 (0x005EC660) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_408___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_408___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_408__RX_DCOC_RANGE_408___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_408__RX_DCOC_RES_I_408___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_408__RX_DCOC_RES_Q_408___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_408__RX_DCOC_RANGE_408___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_408__RX_DCOC_RANGE_408___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_408__RX_DCOC_RES_I_408___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_408__RX_DCOC_RES_I_408___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_408__RX_DCOC_RES_Q_408___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_408__RX_DCOC_RES_Q_408___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_408___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_408___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_409 (0x005EC664) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_409___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_409___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_409__RX_DCOC_RANGE_409___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_409__RX_DCOC_RES_I_409___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_409__RX_DCOC_RES_Q_409___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_409__RX_DCOC_RANGE_409___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_409__RX_DCOC_RANGE_409___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_409__RX_DCOC_RES_I_409___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_409__RX_DCOC_RES_I_409___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_409__RX_DCOC_RES_Q_409___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_409__RX_DCOC_RES_Q_409___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_409___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_409___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_410 (0x005EC668) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_410___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_410___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_410__RX_DCOC_RANGE_410___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_410__RX_DCOC_RES_I_410___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_410__RX_DCOC_RES_Q_410___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_410__RX_DCOC_RANGE_410___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_410__RX_DCOC_RANGE_410___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_410__RX_DCOC_RES_I_410___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_410__RX_DCOC_RES_I_410___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_410__RX_DCOC_RES_Q_410___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_410__RX_DCOC_RES_Q_410___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_410___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_410___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_411 (0x005EC66C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_411___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_411___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_411__RX_DCOC_RANGE_411___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_411__RX_DCOC_RES_I_411___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_411__RX_DCOC_RES_Q_411___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_411__RX_DCOC_RANGE_411___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_411__RX_DCOC_RANGE_411___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_411__RX_DCOC_RES_I_411___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_411__RX_DCOC_RES_I_411___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_411__RX_DCOC_RES_Q_411___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_411__RX_DCOC_RES_Q_411___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_411___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_411___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_412 (0x005EC670) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_412___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_412___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_412__RX_DCOC_RANGE_412___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_412__RX_DCOC_RES_I_412___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_412__RX_DCOC_RES_Q_412___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_412__RX_DCOC_RANGE_412___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_412__RX_DCOC_RANGE_412___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_412__RX_DCOC_RES_I_412___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_412__RX_DCOC_RES_I_412___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_412__RX_DCOC_RES_Q_412___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_412__RX_DCOC_RES_Q_412___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_412___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_412___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_413 (0x005EC674) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_413___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_413___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_413__RX_DCOC_RANGE_413___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_413__RX_DCOC_RES_I_413___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_413__RX_DCOC_RES_Q_413___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_413__RX_DCOC_RANGE_413___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_413__RX_DCOC_RANGE_413___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_413__RX_DCOC_RES_I_413___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_413__RX_DCOC_RES_I_413___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_413__RX_DCOC_RES_Q_413___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_413__RX_DCOC_RES_Q_413___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_413___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_413___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_414 (0x005EC678) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_414___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_414___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_414__RX_DCOC_RANGE_414___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_414__RX_DCOC_RES_I_414___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_414__RX_DCOC_RES_Q_414___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_414__RX_DCOC_RANGE_414___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_414__RX_DCOC_RANGE_414___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_414__RX_DCOC_RES_I_414___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_414__RX_DCOC_RES_I_414___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_414__RX_DCOC_RES_Q_414___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_414__RX_DCOC_RES_Q_414___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_414___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_414___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_415 (0x005EC67C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_415___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_415___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_415__RX_DCOC_RANGE_415___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_415__RX_DCOC_RES_I_415___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_415__RX_DCOC_RES_Q_415___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_415__RX_DCOC_RANGE_415___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_415__RX_DCOC_RANGE_415___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_415__RX_DCOC_RES_I_415___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_415__RX_DCOC_RES_I_415___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_415__RX_DCOC_RES_Q_415___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_415__RX_DCOC_RES_Q_415___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_415___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_415___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_416 (0x005EC680) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_416___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_416___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_416__RX_DCOC_RANGE_416___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_416__RX_DCOC_RES_I_416___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_416__RX_DCOC_RES_Q_416___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_416__RX_DCOC_RANGE_416___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_416__RX_DCOC_RANGE_416___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_416__RX_DCOC_RES_I_416___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_416__RX_DCOC_RES_I_416___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_416__RX_DCOC_RES_Q_416___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_416__RX_DCOC_RES_Q_416___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_416___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_416___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_417 (0x005EC684) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_417___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_417___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_417__RX_DCOC_RANGE_417___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_417__RX_DCOC_RES_I_417___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_417__RX_DCOC_RES_Q_417___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_417__RX_DCOC_RANGE_417___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_417__RX_DCOC_RANGE_417___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_417__RX_DCOC_RES_I_417___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_417__RX_DCOC_RES_I_417___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_417__RX_DCOC_RES_Q_417___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_417__RX_DCOC_RES_Q_417___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_417___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_417___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_418 (0x005EC688) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_418___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_418___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_418__RX_DCOC_RANGE_418___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_418__RX_DCOC_RES_I_418___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_418__RX_DCOC_RES_Q_418___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_418__RX_DCOC_RANGE_418___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_418__RX_DCOC_RANGE_418___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_418__RX_DCOC_RES_I_418___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_418__RX_DCOC_RES_I_418___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_418__RX_DCOC_RES_Q_418___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_418__RX_DCOC_RES_Q_418___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_418___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_418___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_419 (0x005EC68C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_419___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_419___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_419__RX_DCOC_RANGE_419___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_419__RX_DCOC_RES_I_419___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_419__RX_DCOC_RES_Q_419___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_419__RX_DCOC_RANGE_419___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_419__RX_DCOC_RANGE_419___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_419__RX_DCOC_RES_I_419___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_419__RX_DCOC_RES_I_419___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_419__RX_DCOC_RES_Q_419___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_419__RX_DCOC_RES_Q_419___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_419___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_419___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_420 (0x005EC690) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_420___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_420___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_420__RX_DCOC_RANGE_420___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_420__RX_DCOC_RES_I_420___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_420__RX_DCOC_RES_Q_420___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_420__RX_DCOC_RANGE_420___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_420__RX_DCOC_RANGE_420___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_420__RX_DCOC_RES_I_420___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_420__RX_DCOC_RES_I_420___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_420__RX_DCOC_RES_Q_420___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_420__RX_DCOC_RES_Q_420___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_420___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_420___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_421 (0x005EC694) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_421___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_421___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_421__RX_DCOC_RANGE_421___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_421__RX_DCOC_RES_I_421___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_421__RX_DCOC_RES_Q_421___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_421__RX_DCOC_RANGE_421___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_421__RX_DCOC_RANGE_421___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_421__RX_DCOC_RES_I_421___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_421__RX_DCOC_RES_I_421___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_421__RX_DCOC_RES_Q_421___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_421__RX_DCOC_RES_Q_421___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_421___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_421___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_422 (0x005EC698) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_422___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_422___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_422__RX_DCOC_RANGE_422___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_422__RX_DCOC_RES_I_422___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_422__RX_DCOC_RES_Q_422___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_422__RX_DCOC_RANGE_422___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_422__RX_DCOC_RANGE_422___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_422__RX_DCOC_RES_I_422___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_422__RX_DCOC_RES_I_422___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_422__RX_DCOC_RES_Q_422___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_422__RX_DCOC_RES_Q_422___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_422___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_422___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_423 (0x005EC69C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_423___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_423___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_423__RX_DCOC_RANGE_423___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_423__RX_DCOC_RES_I_423___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_423__RX_DCOC_RES_Q_423___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_423__RX_DCOC_RANGE_423___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_423__RX_DCOC_RANGE_423___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_423__RX_DCOC_RES_I_423___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_423__RX_DCOC_RES_I_423___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_423__RX_DCOC_RES_Q_423___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_423__RX_DCOC_RES_Q_423___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_423___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_423___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_424 (0x005EC6A0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_424___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_424___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_424__RX_DCOC_RANGE_424___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_424__RX_DCOC_RES_I_424___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_424__RX_DCOC_RES_Q_424___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_424__RX_DCOC_RANGE_424___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_424__RX_DCOC_RANGE_424___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_424__RX_DCOC_RES_I_424___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_424__RX_DCOC_RES_I_424___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_424__RX_DCOC_RES_Q_424___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_424__RX_DCOC_RES_Q_424___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_424___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_424___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_425 (0x005EC6A4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_425___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_425___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_425__RX_DCOC_RANGE_425___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_425__RX_DCOC_RES_I_425___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_425__RX_DCOC_RES_Q_425___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_425__RX_DCOC_RANGE_425___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_425__RX_DCOC_RANGE_425___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_425__RX_DCOC_RES_I_425___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_425__RX_DCOC_RES_I_425___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_425__RX_DCOC_RES_Q_425___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_425__RX_DCOC_RES_Q_425___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_425___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_425___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_426 (0x005EC6A8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_426___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_426___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_426__RX_DCOC_RANGE_426___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_426__RX_DCOC_RES_I_426___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_426__RX_DCOC_RES_Q_426___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_426__RX_DCOC_RANGE_426___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_426__RX_DCOC_RANGE_426___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_426__RX_DCOC_RES_I_426___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_426__RX_DCOC_RES_I_426___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_426__RX_DCOC_RES_Q_426___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_426__RX_DCOC_RES_Q_426___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_426___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_426___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_427 (0x005EC6AC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_427___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_427___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_427__RX_DCOC_RANGE_427___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_427__RX_DCOC_RES_I_427___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_427__RX_DCOC_RES_Q_427___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_427__RX_DCOC_RANGE_427___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_427__RX_DCOC_RANGE_427___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_427__RX_DCOC_RES_I_427___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_427__RX_DCOC_RES_I_427___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_427__RX_DCOC_RES_Q_427___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_427__RX_DCOC_RES_Q_427___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_427___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_427___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_428 (0x005EC6B0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_428___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_428___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_428__RX_DCOC_RANGE_428___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_428__RX_DCOC_RES_I_428___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_428__RX_DCOC_RES_Q_428___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_428__RX_DCOC_RANGE_428___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_428__RX_DCOC_RANGE_428___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_428__RX_DCOC_RES_I_428___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_428__RX_DCOC_RES_I_428___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_428__RX_DCOC_RES_Q_428___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_428__RX_DCOC_RES_Q_428___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_428___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_428___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_429 (0x005EC6B4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_429___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_429___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_429__RX_DCOC_RANGE_429___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_429__RX_DCOC_RES_I_429___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_429__RX_DCOC_RES_Q_429___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_429__RX_DCOC_RANGE_429___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_429__RX_DCOC_RANGE_429___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_429__RX_DCOC_RES_I_429___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_429__RX_DCOC_RES_I_429___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_429__RX_DCOC_RES_Q_429___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_429__RX_DCOC_RES_Q_429___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_429___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_429___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_430 (0x005EC6B8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_430___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_430___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_430__RX_DCOC_RANGE_430___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_430__RX_DCOC_RES_I_430___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_430__RX_DCOC_RES_Q_430___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_430__RX_DCOC_RANGE_430___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_430__RX_DCOC_RANGE_430___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_430__RX_DCOC_RES_I_430___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_430__RX_DCOC_RES_I_430___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_430__RX_DCOC_RES_Q_430___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_430__RX_DCOC_RES_Q_430___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_430___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_430___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_431 (0x005EC6BC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_431___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_431___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_431__RX_DCOC_RANGE_431___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_431__RX_DCOC_RES_I_431___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_431__RX_DCOC_RES_Q_431___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_431__RX_DCOC_RANGE_431___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_431__RX_DCOC_RANGE_431___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_431__RX_DCOC_RES_I_431___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_431__RX_DCOC_RES_I_431___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_431__RX_DCOC_RES_Q_431___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_431__RX_DCOC_RES_Q_431___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_431___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_431___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_432 (0x005EC6C0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_432___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_432___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_432__RX_DCOC_RANGE_432___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_432__RX_DCOC_RES_I_432___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_432__RX_DCOC_RES_Q_432___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_432__RX_DCOC_RANGE_432___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_432__RX_DCOC_RANGE_432___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_432__RX_DCOC_RES_I_432___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_432__RX_DCOC_RES_I_432___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_432__RX_DCOC_RES_Q_432___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_432__RX_DCOC_RES_Q_432___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_432___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_432___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_433 (0x005EC6C4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_433___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_433___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_433__RX_DCOC_RANGE_433___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_433__RX_DCOC_RES_I_433___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_433__RX_DCOC_RES_Q_433___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_433__RX_DCOC_RANGE_433___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_433__RX_DCOC_RANGE_433___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_433__RX_DCOC_RES_I_433___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_433__RX_DCOC_RES_I_433___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_433__RX_DCOC_RES_Q_433___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_433__RX_DCOC_RES_Q_433___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_433___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_433___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_434 (0x005EC6C8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_434___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_434___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_434__RX_DCOC_RANGE_434___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_434__RX_DCOC_RES_I_434___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_434__RX_DCOC_RES_Q_434___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_434__RX_DCOC_RANGE_434___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_434__RX_DCOC_RANGE_434___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_434__RX_DCOC_RES_I_434___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_434__RX_DCOC_RES_I_434___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_434__RX_DCOC_RES_Q_434___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_434__RX_DCOC_RES_Q_434___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_434___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_434___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_435 (0x005EC6CC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_435___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_435___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_435__RX_DCOC_RANGE_435___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_435__RX_DCOC_RES_I_435___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_435__RX_DCOC_RES_Q_435___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_435__RX_DCOC_RANGE_435___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_435__RX_DCOC_RANGE_435___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_435__RX_DCOC_RES_I_435___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_435__RX_DCOC_RES_I_435___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_435__RX_DCOC_RES_Q_435___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_435__RX_DCOC_RES_Q_435___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_435___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_435___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_436 (0x005EC6D0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_436___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_436___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_436__RX_DCOC_RANGE_436___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_436__RX_DCOC_RES_I_436___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_436__RX_DCOC_RES_Q_436___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_436__RX_DCOC_RANGE_436___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_436__RX_DCOC_RANGE_436___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_436__RX_DCOC_RES_I_436___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_436__RX_DCOC_RES_I_436___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_436__RX_DCOC_RES_Q_436___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_436__RX_DCOC_RES_Q_436___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_436___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_436___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_437 (0x005EC6D4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_437___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_437___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_437__RX_DCOC_RANGE_437___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_437__RX_DCOC_RES_I_437___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_437__RX_DCOC_RES_Q_437___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_437__RX_DCOC_RANGE_437___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_437__RX_DCOC_RANGE_437___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_437__RX_DCOC_RES_I_437___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_437__RX_DCOC_RES_I_437___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_437__RX_DCOC_RES_Q_437___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_437__RX_DCOC_RES_Q_437___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_437___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_437___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_438 (0x005EC6D8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_438___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_438___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_438__RX_DCOC_RANGE_438___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_438__RX_DCOC_RES_I_438___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_438__RX_DCOC_RES_Q_438___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_438__RX_DCOC_RANGE_438___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_438__RX_DCOC_RANGE_438___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_438__RX_DCOC_RES_I_438___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_438__RX_DCOC_RES_I_438___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_438__RX_DCOC_RES_Q_438___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_438__RX_DCOC_RES_Q_438___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_438___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_438___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_439 (0x005EC6DC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_439___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_439___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_439__RX_DCOC_RANGE_439___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_439__RX_DCOC_RES_I_439___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_439__RX_DCOC_RES_Q_439___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_439__RX_DCOC_RANGE_439___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_439__RX_DCOC_RANGE_439___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_439__RX_DCOC_RES_I_439___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_439__RX_DCOC_RES_I_439___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_439__RX_DCOC_RES_Q_439___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_439__RX_DCOC_RES_Q_439___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_439___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_439___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_440 (0x005EC6E0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_440___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_440___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_440__RX_DCOC_RANGE_440___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_440__RX_DCOC_RES_I_440___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_440__RX_DCOC_RES_Q_440___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_440__RX_DCOC_RANGE_440___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_440__RX_DCOC_RANGE_440___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_440__RX_DCOC_RES_I_440___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_440__RX_DCOC_RES_I_440___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_440__RX_DCOC_RES_Q_440___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_440__RX_DCOC_RES_Q_440___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_440___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_440___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_441 (0x005EC6E4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_441___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_441___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_441__RX_DCOC_RANGE_441___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_441__RX_DCOC_RES_I_441___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_441__RX_DCOC_RES_Q_441___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_441__RX_DCOC_RANGE_441___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_441__RX_DCOC_RANGE_441___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_441__RX_DCOC_RES_I_441___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_441__RX_DCOC_RES_I_441___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_441__RX_DCOC_RES_Q_441___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_441__RX_DCOC_RES_Q_441___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_441___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_441___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_442 (0x005EC6E8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_442___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_442___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_442__RX_DCOC_RANGE_442___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_442__RX_DCOC_RES_I_442___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_442__RX_DCOC_RES_Q_442___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_442__RX_DCOC_RANGE_442___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_442__RX_DCOC_RANGE_442___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_442__RX_DCOC_RES_I_442___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_442__RX_DCOC_RES_I_442___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_442__RX_DCOC_RES_Q_442___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_442__RX_DCOC_RES_Q_442___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_442___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_442___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_443 (0x005EC6EC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_443___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_443___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_443__RX_DCOC_RANGE_443___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_443__RX_DCOC_RES_I_443___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_443__RX_DCOC_RES_Q_443___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_443__RX_DCOC_RANGE_443___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_443__RX_DCOC_RANGE_443___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_443__RX_DCOC_RES_I_443___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_443__RX_DCOC_RES_I_443___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_443__RX_DCOC_RES_Q_443___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_443__RX_DCOC_RES_Q_443___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_443___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_443___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_444 (0x005EC6F0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_444___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_444___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_444__RX_DCOC_RANGE_444___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_444__RX_DCOC_RES_I_444___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_444__RX_DCOC_RES_Q_444___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_444__RX_DCOC_RANGE_444___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_444__RX_DCOC_RANGE_444___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_444__RX_DCOC_RES_I_444___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_444__RX_DCOC_RES_I_444___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_444__RX_DCOC_RES_Q_444___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_444__RX_DCOC_RES_Q_444___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_444___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_444___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_445 (0x005EC6F4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_445___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_445___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_445__RX_DCOC_RANGE_445___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_445__RX_DCOC_RES_I_445___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_445__RX_DCOC_RES_Q_445___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_445__RX_DCOC_RANGE_445___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_445__RX_DCOC_RANGE_445___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_445__RX_DCOC_RES_I_445___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_445__RX_DCOC_RES_I_445___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_445__RX_DCOC_RES_Q_445___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_445__RX_DCOC_RES_Q_445___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_445___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_445___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_446 (0x005EC6F8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_446___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_446___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_446__RX_DCOC_RANGE_446___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_446__RX_DCOC_RES_I_446___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_446__RX_DCOC_RES_Q_446___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_446__RX_DCOC_RANGE_446___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_446__RX_DCOC_RANGE_446___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_446__RX_DCOC_RES_I_446___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_446__RX_DCOC_RES_I_446___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_446__RX_DCOC_RES_Q_446___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_446__RX_DCOC_RES_Q_446___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_446___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_446___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_447 (0x005EC6FC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_447___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_447___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_447__RX_DCOC_RANGE_447___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_447__RX_DCOC_RES_I_447___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_447__RX_DCOC_RES_Q_447___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_447__RX_DCOC_RANGE_447___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_447__RX_DCOC_RANGE_447___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_447__RX_DCOC_RES_I_447___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_447__RX_DCOC_RES_I_447___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_447__RX_DCOC_RES_Q_447___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_447__RX_DCOC_RES_Q_447___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_447___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_447___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_448 (0x005EC700) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_448___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_448___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_448__RX_DCOC_RANGE_448___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_448__RX_DCOC_RES_I_448___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_448__RX_DCOC_RES_Q_448___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_448__RX_DCOC_RANGE_448___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_448__RX_DCOC_RANGE_448___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_448__RX_DCOC_RES_I_448___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_448__RX_DCOC_RES_I_448___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_448__RX_DCOC_RES_Q_448___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_448__RX_DCOC_RES_Q_448___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_448___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_448___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_449 (0x005EC704) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_449___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_449___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_449__RX_DCOC_RANGE_449___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_449__RX_DCOC_RES_I_449___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_449__RX_DCOC_RES_Q_449___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_449__RX_DCOC_RANGE_449___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_449__RX_DCOC_RANGE_449___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_449__RX_DCOC_RES_I_449___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_449__RX_DCOC_RES_I_449___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_449__RX_DCOC_RES_Q_449___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_449__RX_DCOC_RES_Q_449___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_449___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_449___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_450 (0x005EC708) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_450___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_450___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_450__RX_DCOC_RANGE_450___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_450__RX_DCOC_RES_I_450___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_450__RX_DCOC_RES_Q_450___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_450__RX_DCOC_RANGE_450___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_450__RX_DCOC_RANGE_450___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_450__RX_DCOC_RES_I_450___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_450__RX_DCOC_RES_I_450___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_450__RX_DCOC_RES_Q_450___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_450__RX_DCOC_RES_Q_450___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_450___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_450___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_451 (0x005EC70C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_451___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_451___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_451__RX_DCOC_RANGE_451___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_451__RX_DCOC_RES_I_451___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_451__RX_DCOC_RES_Q_451___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_451__RX_DCOC_RANGE_451___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_451__RX_DCOC_RANGE_451___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_451__RX_DCOC_RES_I_451___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_451__RX_DCOC_RES_I_451___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_451__RX_DCOC_RES_Q_451___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_451__RX_DCOC_RES_Q_451___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_451___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_451___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_452 (0x005EC710) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_452___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_452___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_452__RX_DCOC_RANGE_452___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_452__RX_DCOC_RES_I_452___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_452__RX_DCOC_RES_Q_452___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_452__RX_DCOC_RANGE_452___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_452__RX_DCOC_RANGE_452___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_452__RX_DCOC_RES_I_452___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_452__RX_DCOC_RES_I_452___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_452__RX_DCOC_RES_Q_452___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_452__RX_DCOC_RES_Q_452___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_452___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_452___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_453 (0x005EC714) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_453___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_453___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_453__RX_DCOC_RANGE_453___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_453__RX_DCOC_RES_I_453___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_453__RX_DCOC_RES_Q_453___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_453__RX_DCOC_RANGE_453___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_453__RX_DCOC_RANGE_453___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_453__RX_DCOC_RES_I_453___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_453__RX_DCOC_RES_I_453___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_453__RX_DCOC_RES_Q_453___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_453__RX_DCOC_RES_Q_453___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_453___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_453___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_454 (0x005EC718) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_454___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_454___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_454__RX_DCOC_RANGE_454___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_454__RX_DCOC_RES_I_454___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_454__RX_DCOC_RES_Q_454___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_454__RX_DCOC_RANGE_454___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_454__RX_DCOC_RANGE_454___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_454__RX_DCOC_RES_I_454___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_454__RX_DCOC_RES_I_454___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_454__RX_DCOC_RES_Q_454___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_454__RX_DCOC_RES_Q_454___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_454___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_454___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_455 (0x005EC71C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_455___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_455___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_455__RX_DCOC_RANGE_455___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_455__RX_DCOC_RES_I_455___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_455__RX_DCOC_RES_Q_455___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_455__RX_DCOC_RANGE_455___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_455__RX_DCOC_RANGE_455___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_455__RX_DCOC_RES_I_455___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_455__RX_DCOC_RES_I_455___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_455__RX_DCOC_RES_Q_455___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_455__RX_DCOC_RES_Q_455___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_455___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_455___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_456 (0x005EC720) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_456___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_456___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_456__RX_DCOC_RANGE_456___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_456__RX_DCOC_RES_I_456___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_456__RX_DCOC_RES_Q_456___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_456__RX_DCOC_RANGE_456___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_456__RX_DCOC_RANGE_456___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_456__RX_DCOC_RES_I_456___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_456__RX_DCOC_RES_I_456___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_456__RX_DCOC_RES_Q_456___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_456__RX_DCOC_RES_Q_456___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_456___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_456___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_457 (0x005EC724) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_457___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_457___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_457__RX_DCOC_RANGE_457___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_457__RX_DCOC_RES_I_457___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_457__RX_DCOC_RES_Q_457___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_457__RX_DCOC_RANGE_457___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_457__RX_DCOC_RANGE_457___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_457__RX_DCOC_RES_I_457___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_457__RX_DCOC_RES_I_457___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_457__RX_DCOC_RES_Q_457___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_457__RX_DCOC_RES_Q_457___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_457___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_457___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_458 (0x005EC728) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_458___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_458___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_458__RX_DCOC_RANGE_458___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_458__RX_DCOC_RES_I_458___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_458__RX_DCOC_RES_Q_458___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_458__RX_DCOC_RANGE_458___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_458__RX_DCOC_RANGE_458___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_458__RX_DCOC_RES_I_458___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_458__RX_DCOC_RES_I_458___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_458__RX_DCOC_RES_Q_458___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_458__RX_DCOC_RES_Q_458___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_458___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_458___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_459 (0x005EC72C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_459___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_459___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_459__RX_DCOC_RANGE_459___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_459__RX_DCOC_RES_I_459___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_459__RX_DCOC_RES_Q_459___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_459__RX_DCOC_RANGE_459___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_459__RX_DCOC_RANGE_459___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_459__RX_DCOC_RES_I_459___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_459__RX_DCOC_RES_I_459___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_459__RX_DCOC_RES_Q_459___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_459__RX_DCOC_RES_Q_459___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_459___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_459___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_460 (0x005EC730) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_460___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_460___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_460__RX_DCOC_RANGE_460___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_460__RX_DCOC_RES_I_460___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_460__RX_DCOC_RES_Q_460___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_460__RX_DCOC_RANGE_460___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_460__RX_DCOC_RANGE_460___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_460__RX_DCOC_RES_I_460___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_460__RX_DCOC_RES_I_460___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_460__RX_DCOC_RES_Q_460___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_460__RX_DCOC_RES_Q_460___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_460___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_460___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_461 (0x005EC734) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_461___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_461___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_461__RX_DCOC_RANGE_461___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_461__RX_DCOC_RES_I_461___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_461__RX_DCOC_RES_Q_461___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_461__RX_DCOC_RANGE_461___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_461__RX_DCOC_RANGE_461___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_461__RX_DCOC_RES_I_461___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_461__RX_DCOC_RES_I_461___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_461__RX_DCOC_RES_Q_461___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_461__RX_DCOC_RES_Q_461___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_461___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_461___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_462 (0x005EC738) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_462___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_462___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_462__RX_DCOC_RANGE_462___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_462__RX_DCOC_RES_I_462___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_462__RX_DCOC_RES_Q_462___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_462__RX_DCOC_RANGE_462___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_462__RX_DCOC_RANGE_462___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_462__RX_DCOC_RES_I_462___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_462__RX_DCOC_RES_I_462___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_462__RX_DCOC_RES_Q_462___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_462__RX_DCOC_RES_Q_462___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_462___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_462___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_463 (0x005EC73C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_463___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_463___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_463__RX_DCOC_RANGE_463___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_463__RX_DCOC_RES_I_463___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_463__RX_DCOC_RES_Q_463___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_463__RX_DCOC_RANGE_463___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_463__RX_DCOC_RANGE_463___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_463__RX_DCOC_RES_I_463___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_463__RX_DCOC_RES_I_463___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_463__RX_DCOC_RES_Q_463___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_463__RX_DCOC_RES_Q_463___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_463___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_463___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_464 (0x005EC740) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_464___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_464___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_464__RX_DCOC_RANGE_464___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_464__RX_DCOC_RES_I_464___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_464__RX_DCOC_RES_Q_464___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_464__RX_DCOC_RANGE_464___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_464__RX_DCOC_RANGE_464___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_464__RX_DCOC_RES_I_464___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_464__RX_DCOC_RES_I_464___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_464__RX_DCOC_RES_Q_464___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_464__RX_DCOC_RES_Q_464___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_464___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_464___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_465 (0x005EC744) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_465___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_465___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_465__RX_DCOC_RANGE_465___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_465__RX_DCOC_RES_I_465___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_465__RX_DCOC_RES_Q_465___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_465__RX_DCOC_RANGE_465___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_465__RX_DCOC_RANGE_465___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_465__RX_DCOC_RES_I_465___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_465__RX_DCOC_RES_I_465___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_465__RX_DCOC_RES_Q_465___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_465__RX_DCOC_RES_Q_465___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_465___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_465___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_466 (0x005EC748) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_466___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_466___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_466__RX_DCOC_RANGE_466___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_466__RX_DCOC_RES_I_466___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_466__RX_DCOC_RES_Q_466___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_466__RX_DCOC_RANGE_466___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_466__RX_DCOC_RANGE_466___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_466__RX_DCOC_RES_I_466___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_466__RX_DCOC_RES_I_466___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_466__RX_DCOC_RES_Q_466___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_466__RX_DCOC_RES_Q_466___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_466___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_466___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_467 (0x005EC74C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_467___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_467___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_467__RX_DCOC_RANGE_467___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_467__RX_DCOC_RES_I_467___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_467__RX_DCOC_RES_Q_467___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_467__RX_DCOC_RANGE_467___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_467__RX_DCOC_RANGE_467___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_467__RX_DCOC_RES_I_467___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_467__RX_DCOC_RES_I_467___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_467__RX_DCOC_RES_Q_467___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_467__RX_DCOC_RES_Q_467___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_467___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_467___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_468 (0x005EC750) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_468___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_468___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_468__RX_DCOC_RANGE_468___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_468__RX_DCOC_RES_I_468___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_468__RX_DCOC_RES_Q_468___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_468__RX_DCOC_RANGE_468___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_468__RX_DCOC_RANGE_468___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_468__RX_DCOC_RES_I_468___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_468__RX_DCOC_RES_I_468___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_468__RX_DCOC_RES_Q_468___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_468__RX_DCOC_RES_Q_468___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_468___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_468___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_469 (0x005EC754) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_469___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_469___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_469__RX_DCOC_RANGE_469___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_469__RX_DCOC_RES_I_469___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_469__RX_DCOC_RES_Q_469___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_469__RX_DCOC_RANGE_469___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_469__RX_DCOC_RANGE_469___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_469__RX_DCOC_RES_I_469___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_469__RX_DCOC_RES_I_469___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_469__RX_DCOC_RES_Q_469___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_469__RX_DCOC_RES_Q_469___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_469___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_469___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_470 (0x005EC758) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_470___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_470___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_470__RX_DCOC_RANGE_470___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_470__RX_DCOC_RES_I_470___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_470__RX_DCOC_RES_Q_470___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_470__RX_DCOC_RANGE_470___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_470__RX_DCOC_RANGE_470___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_470__RX_DCOC_RES_I_470___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_470__RX_DCOC_RES_I_470___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_470__RX_DCOC_RES_Q_470___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_470__RX_DCOC_RES_Q_470___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_470___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_470___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_471 (0x005EC75C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_471___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_471___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_471__RX_DCOC_RANGE_471___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_471__RX_DCOC_RES_I_471___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_471__RX_DCOC_RES_Q_471___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_471__RX_DCOC_RANGE_471___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_471__RX_DCOC_RANGE_471___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_471__RX_DCOC_RES_I_471___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_471__RX_DCOC_RES_I_471___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_471__RX_DCOC_RES_Q_471___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_471__RX_DCOC_RES_Q_471___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_471___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_471___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_472 (0x005EC760) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_472___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_472___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_472__RX_DCOC_RANGE_472___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_472__RX_DCOC_RES_I_472___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_472__RX_DCOC_RES_Q_472___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_472__RX_DCOC_RANGE_472___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_472__RX_DCOC_RANGE_472___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_472__RX_DCOC_RES_I_472___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_472__RX_DCOC_RES_I_472___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_472__RX_DCOC_RES_Q_472___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_472__RX_DCOC_RES_Q_472___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_472___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_472___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_473 (0x005EC764) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_473___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_473___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_473__RX_DCOC_RANGE_473___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_473__RX_DCOC_RES_I_473___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_473__RX_DCOC_RES_Q_473___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_473__RX_DCOC_RANGE_473___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_473__RX_DCOC_RANGE_473___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_473__RX_DCOC_RES_I_473___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_473__RX_DCOC_RES_I_473___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_473__RX_DCOC_RES_Q_473___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_473__RX_DCOC_RES_Q_473___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_473___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_473___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_474 (0x005EC768) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_474___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_474___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_474__RX_DCOC_RANGE_474___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_474__RX_DCOC_RES_I_474___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_474__RX_DCOC_RES_Q_474___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_474__RX_DCOC_RANGE_474___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_474__RX_DCOC_RANGE_474___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_474__RX_DCOC_RES_I_474___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_474__RX_DCOC_RES_I_474___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_474__RX_DCOC_RES_Q_474___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_474__RX_DCOC_RES_Q_474___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_474___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_474___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_475 (0x005EC76C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_475___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_475___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_475__RX_DCOC_RANGE_475___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_475__RX_DCOC_RES_I_475___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_475__RX_DCOC_RES_Q_475___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_475__RX_DCOC_RANGE_475___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_475__RX_DCOC_RANGE_475___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_475__RX_DCOC_RES_I_475___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_475__RX_DCOC_RES_I_475___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_475__RX_DCOC_RES_Q_475___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_475__RX_DCOC_RES_Q_475___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_475___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_475___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_476 (0x005EC770) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_476___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_476___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_476__RX_DCOC_RANGE_476___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_476__RX_DCOC_RES_I_476___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_476__RX_DCOC_RES_Q_476___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_476__RX_DCOC_RANGE_476___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_476__RX_DCOC_RANGE_476___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_476__RX_DCOC_RES_I_476___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_476__RX_DCOC_RES_I_476___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_476__RX_DCOC_RES_Q_476___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_476__RX_DCOC_RES_Q_476___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_476___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_476___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_477 (0x005EC774) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_477___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_477___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_477__RX_DCOC_RANGE_477___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_477__RX_DCOC_RES_I_477___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_477__RX_DCOC_RES_Q_477___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_477__RX_DCOC_RANGE_477___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_477__RX_DCOC_RANGE_477___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_477__RX_DCOC_RES_I_477___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_477__RX_DCOC_RES_I_477___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_477__RX_DCOC_RES_Q_477___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_477__RX_DCOC_RES_Q_477___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_477___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_477___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_478 (0x005EC778) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_478___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_478___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_478__RX_DCOC_RANGE_478___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_478__RX_DCOC_RES_I_478___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_478__RX_DCOC_RES_Q_478___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_478__RX_DCOC_RANGE_478___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_478__RX_DCOC_RANGE_478___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_478__RX_DCOC_RES_I_478___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_478__RX_DCOC_RES_I_478___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_478__RX_DCOC_RES_Q_478___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_478__RX_DCOC_RES_Q_478___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_478___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_478___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_479 (0x005EC77C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_479___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_479___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_479__RX_DCOC_RANGE_479___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_479__RX_DCOC_RES_I_479___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_479__RX_DCOC_RES_Q_479___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_479__RX_DCOC_RANGE_479___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_479__RX_DCOC_RANGE_479___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_479__RX_DCOC_RES_I_479___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_479__RX_DCOC_RES_I_479___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_479__RX_DCOC_RES_Q_479___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_479__RX_DCOC_RES_Q_479___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_479___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_479___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_480 (0x005EC780) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_480___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_480___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_480__RX_DCOC_RANGE_480___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_480__RX_DCOC_RES_I_480___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_480__RX_DCOC_RES_Q_480___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_480__RX_DCOC_RANGE_480___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_480__RX_DCOC_RANGE_480___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_480__RX_DCOC_RES_I_480___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_480__RX_DCOC_RES_I_480___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_480__RX_DCOC_RES_Q_480___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_480__RX_DCOC_RES_Q_480___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_480___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_480___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_481 (0x005EC784) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_481___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_481___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_481__RX_DCOC_RANGE_481___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_481__RX_DCOC_RES_I_481___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_481__RX_DCOC_RES_Q_481___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_481__RX_DCOC_RANGE_481___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_481__RX_DCOC_RANGE_481___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_481__RX_DCOC_RES_I_481___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_481__RX_DCOC_RES_I_481___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_481__RX_DCOC_RES_Q_481___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_481__RX_DCOC_RES_Q_481___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_481___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_481___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_482 (0x005EC788) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_482___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_482___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_482__RX_DCOC_RANGE_482___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_482__RX_DCOC_RES_I_482___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_482__RX_DCOC_RES_Q_482___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_482__RX_DCOC_RANGE_482___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_482__RX_DCOC_RANGE_482___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_482__RX_DCOC_RES_I_482___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_482__RX_DCOC_RES_I_482___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_482__RX_DCOC_RES_Q_482___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_482__RX_DCOC_RES_Q_482___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_482___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_482___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_483 (0x005EC78C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_483___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_483___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_483__RX_DCOC_RANGE_483___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_483__RX_DCOC_RES_I_483___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_483__RX_DCOC_RES_Q_483___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_483__RX_DCOC_RANGE_483___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_483__RX_DCOC_RANGE_483___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_483__RX_DCOC_RES_I_483___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_483__RX_DCOC_RES_I_483___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_483__RX_DCOC_RES_Q_483___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_483__RX_DCOC_RES_Q_483___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_483___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_483___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_484 (0x005EC790) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_484___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_484___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_484__RX_DCOC_RANGE_484___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_484__RX_DCOC_RES_I_484___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_484__RX_DCOC_RES_Q_484___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_484__RX_DCOC_RANGE_484___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_484__RX_DCOC_RANGE_484___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_484__RX_DCOC_RES_I_484___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_484__RX_DCOC_RES_I_484___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_484__RX_DCOC_RES_Q_484___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_484__RX_DCOC_RES_Q_484___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_484___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_484___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_485 (0x005EC794) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_485___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_485___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_485__RX_DCOC_RANGE_485___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_485__RX_DCOC_RES_I_485___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_485__RX_DCOC_RES_Q_485___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_485__RX_DCOC_RANGE_485___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_485__RX_DCOC_RANGE_485___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_485__RX_DCOC_RES_I_485___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_485__RX_DCOC_RES_I_485___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_485__RX_DCOC_RES_Q_485___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_485__RX_DCOC_RES_Q_485___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_485___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_485___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_486 (0x005EC798) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_486___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_486___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_486__RX_DCOC_RANGE_486___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_486__RX_DCOC_RES_I_486___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_486__RX_DCOC_RES_Q_486___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_486__RX_DCOC_RANGE_486___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_486__RX_DCOC_RANGE_486___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_486__RX_DCOC_RES_I_486___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_486__RX_DCOC_RES_I_486___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_486__RX_DCOC_RES_Q_486___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_486__RX_DCOC_RES_Q_486___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_486___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_486___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_487 (0x005EC79C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_487___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_487___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_487__RX_DCOC_RANGE_487___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_487__RX_DCOC_RES_I_487___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_487__RX_DCOC_RES_Q_487___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_487__RX_DCOC_RANGE_487___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_487__RX_DCOC_RANGE_487___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_487__RX_DCOC_RES_I_487___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_487__RX_DCOC_RES_I_487___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_487__RX_DCOC_RES_Q_487___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_487__RX_DCOC_RES_Q_487___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_487___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_487___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_488 (0x005EC7A0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_488___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_488___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_488__RX_DCOC_RANGE_488___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_488__RX_DCOC_RES_I_488___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_488__RX_DCOC_RES_Q_488___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_488__RX_DCOC_RANGE_488___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_488__RX_DCOC_RANGE_488___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_488__RX_DCOC_RES_I_488___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_488__RX_DCOC_RES_I_488___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_488__RX_DCOC_RES_Q_488___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_488__RX_DCOC_RES_Q_488___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_488___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_488___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_489 (0x005EC7A4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_489___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_489___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_489__RX_DCOC_RANGE_489___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_489__RX_DCOC_RES_I_489___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_489__RX_DCOC_RES_Q_489___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_489__RX_DCOC_RANGE_489___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_489__RX_DCOC_RANGE_489___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_489__RX_DCOC_RES_I_489___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_489__RX_DCOC_RES_I_489___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_489__RX_DCOC_RES_Q_489___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_489__RX_DCOC_RES_Q_489___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_489___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_489___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_490 (0x005EC7A8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_490___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_490___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_490__RX_DCOC_RANGE_490___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_490__RX_DCOC_RES_I_490___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_490__RX_DCOC_RES_Q_490___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_490__RX_DCOC_RANGE_490___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_490__RX_DCOC_RANGE_490___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_490__RX_DCOC_RES_I_490___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_490__RX_DCOC_RES_I_490___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_490__RX_DCOC_RES_Q_490___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_490__RX_DCOC_RES_Q_490___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_490___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_490___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_491 (0x005EC7AC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_491___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_491___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_491__RX_DCOC_RANGE_491___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_491__RX_DCOC_RES_I_491___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_491__RX_DCOC_RES_Q_491___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_491__RX_DCOC_RANGE_491___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_491__RX_DCOC_RANGE_491___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_491__RX_DCOC_RES_I_491___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_491__RX_DCOC_RES_I_491___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_491__RX_DCOC_RES_Q_491___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_491__RX_DCOC_RES_Q_491___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_491___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_491___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_492 (0x005EC7B0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_492___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_492___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_492__RX_DCOC_RANGE_492___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_492__RX_DCOC_RES_I_492___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_492__RX_DCOC_RES_Q_492___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_492__RX_DCOC_RANGE_492___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_492__RX_DCOC_RANGE_492___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_492__RX_DCOC_RES_I_492___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_492__RX_DCOC_RES_I_492___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_492__RX_DCOC_RES_Q_492___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_492__RX_DCOC_RES_Q_492___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_492___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_492___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_493 (0x005EC7B4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_493___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_493___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_493__RX_DCOC_RANGE_493___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_493__RX_DCOC_RES_I_493___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_493__RX_DCOC_RES_Q_493___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_493__RX_DCOC_RANGE_493___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_493__RX_DCOC_RANGE_493___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_493__RX_DCOC_RES_I_493___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_493__RX_DCOC_RES_I_493___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_493__RX_DCOC_RES_Q_493___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_493__RX_DCOC_RES_Q_493___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_493___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_493___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_494 (0x005EC7B8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_494___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_494___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_494__RX_DCOC_RANGE_494___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_494__RX_DCOC_RES_I_494___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_494__RX_DCOC_RES_Q_494___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_494__RX_DCOC_RANGE_494___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_494__RX_DCOC_RANGE_494___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_494__RX_DCOC_RES_I_494___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_494__RX_DCOC_RES_I_494___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_494__RX_DCOC_RES_Q_494___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_494__RX_DCOC_RES_Q_494___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_494___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_494___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_495 (0x005EC7BC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_495___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_495___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_495__RX_DCOC_RANGE_495___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_495__RX_DCOC_RES_I_495___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_495__RX_DCOC_RES_Q_495___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_495__RX_DCOC_RANGE_495___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_495__RX_DCOC_RANGE_495___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_495__RX_DCOC_RES_I_495___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_495__RX_DCOC_RES_I_495___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_495__RX_DCOC_RES_Q_495___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_495__RX_DCOC_RES_Q_495___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_495___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_495___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_496 (0x005EC7C0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_496___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_496___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_496__RX_DCOC_RANGE_496___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_496__RX_DCOC_RES_I_496___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_496__RX_DCOC_RES_Q_496___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_496__RX_DCOC_RANGE_496___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_496__RX_DCOC_RANGE_496___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_496__RX_DCOC_RES_I_496___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_496__RX_DCOC_RES_I_496___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_496__RX_DCOC_RES_Q_496___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_496__RX_DCOC_RES_Q_496___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_496___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_496___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_497 (0x005EC7C4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_497___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_497___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_497__RX_DCOC_RANGE_497___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_497__RX_DCOC_RES_I_497___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_497__RX_DCOC_RES_Q_497___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_497__RX_DCOC_RANGE_497___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_497__RX_DCOC_RANGE_497___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_497__RX_DCOC_RES_I_497___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_497__RX_DCOC_RES_I_497___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_497__RX_DCOC_RES_Q_497___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_497__RX_DCOC_RES_Q_497___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_497___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_497___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_498 (0x005EC7C8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_498___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_498___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_498__RX_DCOC_RANGE_498___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_498__RX_DCOC_RES_I_498___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_498__RX_DCOC_RES_Q_498___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_498__RX_DCOC_RANGE_498___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_498__RX_DCOC_RANGE_498___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_498__RX_DCOC_RES_I_498___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_498__RX_DCOC_RES_I_498___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_498__RX_DCOC_RES_Q_498___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_498__RX_DCOC_RES_Q_498___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_498___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_498___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_499 (0x005EC7CC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_499___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_499___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_499__RX_DCOC_RANGE_499___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_499__RX_DCOC_RES_I_499___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_499__RX_DCOC_RES_Q_499___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_499__RX_DCOC_RANGE_499___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_499__RX_DCOC_RANGE_499___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_499__RX_DCOC_RES_I_499___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_499__RX_DCOC_RES_I_499___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_499__RX_DCOC_RES_Q_499___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_499__RX_DCOC_RES_Q_499___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_499___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_499___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_500 (0x005EC7D0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_500___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_500___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_500__RX_DCOC_RANGE_500___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_500__RX_DCOC_RES_I_500___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_500__RX_DCOC_RES_Q_500___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_500__RX_DCOC_RANGE_500___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_500__RX_DCOC_RANGE_500___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_500__RX_DCOC_RES_I_500___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_500__RX_DCOC_RES_I_500___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_500__RX_DCOC_RES_Q_500___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_500__RX_DCOC_RES_Q_500___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_500___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_500___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_501 (0x005EC7D4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_501___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_501___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_501__RX_DCOC_RANGE_501___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_501__RX_DCOC_RES_I_501___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_501__RX_DCOC_RES_Q_501___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_501__RX_DCOC_RANGE_501___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_501__RX_DCOC_RANGE_501___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_501__RX_DCOC_RES_I_501___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_501__RX_DCOC_RES_I_501___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_501__RX_DCOC_RES_Q_501___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_501__RX_DCOC_RES_Q_501___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_501___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_501___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_502 (0x005EC7D8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_502___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_502___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_502__RX_DCOC_RANGE_502___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_502__RX_DCOC_RES_I_502___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_502__RX_DCOC_RES_Q_502___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_502__RX_DCOC_RANGE_502___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_502__RX_DCOC_RANGE_502___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_502__RX_DCOC_RES_I_502___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_502__RX_DCOC_RES_I_502___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_502__RX_DCOC_RES_Q_502___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_502__RX_DCOC_RES_Q_502___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_502___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_502___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_503 (0x005EC7DC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_503___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_503___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_503__RX_DCOC_RANGE_503___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_503__RX_DCOC_RES_I_503___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_503__RX_DCOC_RES_Q_503___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_503__RX_DCOC_RANGE_503___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_503__RX_DCOC_RANGE_503___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_503__RX_DCOC_RES_I_503___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_503__RX_DCOC_RES_I_503___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_503__RX_DCOC_RES_Q_503___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_503__RX_DCOC_RES_Q_503___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_503___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_503___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_504 (0x005EC7E0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_504___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_504___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_504__RX_DCOC_RANGE_504___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_504__RX_DCOC_RES_I_504___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_504__RX_DCOC_RES_Q_504___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_504__RX_DCOC_RANGE_504___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_504__RX_DCOC_RANGE_504___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_504__RX_DCOC_RES_I_504___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_504__RX_DCOC_RES_I_504___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_504__RX_DCOC_RES_Q_504___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_504__RX_DCOC_RES_Q_504___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_504___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_504___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_505 (0x005EC7E4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_505___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_505___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_505__RX_DCOC_RANGE_505___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_505__RX_DCOC_RES_I_505___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_505__RX_DCOC_RES_Q_505___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_505__RX_DCOC_RANGE_505___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_505__RX_DCOC_RANGE_505___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_505__RX_DCOC_RES_I_505___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_505__RX_DCOC_RES_I_505___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_505__RX_DCOC_RES_Q_505___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_505__RX_DCOC_RES_Q_505___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_505___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_505___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_506 (0x005EC7E8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_506___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_506___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_506__RX_DCOC_RANGE_506___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_506__RX_DCOC_RES_I_506___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_506__RX_DCOC_RES_Q_506___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_506__RX_DCOC_RANGE_506___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_506__RX_DCOC_RANGE_506___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_506__RX_DCOC_RES_I_506___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_506__RX_DCOC_RES_I_506___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_506__RX_DCOC_RES_Q_506___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_506__RX_DCOC_RES_Q_506___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_506___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_506___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_507 (0x005EC7EC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_507___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_507___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_507__RX_DCOC_RANGE_507___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_507__RX_DCOC_RES_I_507___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_507__RX_DCOC_RES_Q_507___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_507__RX_DCOC_RANGE_507___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_507__RX_DCOC_RANGE_507___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_507__RX_DCOC_RES_I_507___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_507__RX_DCOC_RES_I_507___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_507__RX_DCOC_RES_Q_507___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_507__RX_DCOC_RES_Q_507___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_507___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_507___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_508 (0x005EC7F0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_508___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_508___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_508__RX_DCOC_RANGE_508___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_508__RX_DCOC_RES_I_508___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_508__RX_DCOC_RES_Q_508___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_508__RX_DCOC_RANGE_508___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_508__RX_DCOC_RANGE_508___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_508__RX_DCOC_RES_I_508___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_508__RX_DCOC_RES_I_508___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_508__RX_DCOC_RES_Q_508___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_508__RX_DCOC_RES_Q_508___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_508___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_508___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_509 (0x005EC7F4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_509___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_509___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_509__RX_DCOC_RANGE_509___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_509__RX_DCOC_RES_I_509___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_509__RX_DCOC_RES_Q_509___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_509__RX_DCOC_RANGE_509___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_509__RX_DCOC_RANGE_509___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_509__RX_DCOC_RES_I_509___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_509__RX_DCOC_RES_I_509___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_509__RX_DCOC_RES_Q_509___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_509__RX_DCOC_RES_Q_509___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_509___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_509___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_510 (0x005EC7F8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_510___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_510___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_510__RX_DCOC_RANGE_510___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_510__RX_DCOC_RES_I_510___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_510__RX_DCOC_RES_Q_510___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_510__RX_DCOC_RANGE_510___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_510__RX_DCOC_RANGE_510___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_510__RX_DCOC_RES_I_510___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_510__RX_DCOC_RES_I_510___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_510__RX_DCOC_RES_Q_510___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_510__RX_DCOC_RES_Q_510___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_510___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_510___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_511 (0x005EC7FC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_511___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_511___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_511__RX_DCOC_RANGE_511___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_511__RX_DCOC_RES_I_511___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_511__RX_DCOC_RES_Q_511___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_511__RX_DCOC_RANGE_511___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_511__RX_DCOC_RANGE_511___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_511__RX_DCOC_RES_I_511___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_511__RX_DCOC_RES_I_511___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_511__RX_DCOC_RES_Q_511___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_511__RX_DCOC_RES_Q_511___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_511___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_511___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_512 (0x005EC800) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_512___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_512___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_512__RX_DCOC_RANGE_512___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_512__RX_DCOC_RES_I_512___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_512__RX_DCOC_RES_Q_512___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_512__RX_DCOC_RANGE_512___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_512__RX_DCOC_RANGE_512___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_512__RX_DCOC_RES_I_512___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_512__RX_DCOC_RES_I_512___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_512__RX_DCOC_RES_Q_512___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_512__RX_DCOC_RES_Q_512___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_512___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_512___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_513 (0x005EC804) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_513___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_513___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_513__RX_DCOC_RANGE_513___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_513__RX_DCOC_RES_I_513___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_513__RX_DCOC_RES_Q_513___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_513__RX_DCOC_RANGE_513___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_513__RX_DCOC_RANGE_513___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_513__RX_DCOC_RES_I_513___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_513__RX_DCOC_RES_I_513___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_513__RX_DCOC_RES_Q_513___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_513__RX_DCOC_RES_Q_513___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_513___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_513___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_514 (0x005EC808) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_514___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_514___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_514__RX_DCOC_RANGE_514___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_514__RX_DCOC_RES_I_514___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_514__RX_DCOC_RES_Q_514___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_514__RX_DCOC_RANGE_514___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_514__RX_DCOC_RANGE_514___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_514__RX_DCOC_RES_I_514___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_514__RX_DCOC_RES_I_514___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_514__RX_DCOC_RES_Q_514___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_514__RX_DCOC_RES_Q_514___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_514___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_514___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_515 (0x005EC80C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_515___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_515___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_515__RX_DCOC_RANGE_515___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_515__RX_DCOC_RES_I_515___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_515__RX_DCOC_RES_Q_515___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_515__RX_DCOC_RANGE_515___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_515__RX_DCOC_RANGE_515___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_515__RX_DCOC_RES_I_515___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_515__RX_DCOC_RES_I_515___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_515__RX_DCOC_RES_Q_515___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_515__RX_DCOC_RES_Q_515___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_515___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_515___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_516 (0x005EC810) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_516___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_516___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_516__RX_DCOC_RANGE_516___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_516__RX_DCOC_RES_I_516___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_516__RX_DCOC_RES_Q_516___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_516__RX_DCOC_RANGE_516___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_516__RX_DCOC_RANGE_516___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_516__RX_DCOC_RES_I_516___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_516__RX_DCOC_RES_I_516___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_516__RX_DCOC_RES_Q_516___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_516__RX_DCOC_RES_Q_516___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_516___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_516___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_517 (0x005EC814) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_517___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_517___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_517__RX_DCOC_RANGE_517___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_517__RX_DCOC_RES_I_517___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_517__RX_DCOC_RES_Q_517___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_517__RX_DCOC_RANGE_517___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_517__RX_DCOC_RANGE_517___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_517__RX_DCOC_RES_I_517___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_517__RX_DCOC_RES_I_517___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_517__RX_DCOC_RES_Q_517___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_517__RX_DCOC_RES_Q_517___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_517___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_517___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_518 (0x005EC818) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_518___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_518___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_518__RX_DCOC_RANGE_518___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_518__RX_DCOC_RES_I_518___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_518__RX_DCOC_RES_Q_518___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_518__RX_DCOC_RANGE_518___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_518__RX_DCOC_RANGE_518___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_518__RX_DCOC_RES_I_518___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_518__RX_DCOC_RES_I_518___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_518__RX_DCOC_RES_Q_518___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_518__RX_DCOC_RES_Q_518___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_518___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_518___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_519 (0x005EC81C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_519___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_519___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_519__RX_DCOC_RANGE_519___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_519__RX_DCOC_RES_I_519___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_519__RX_DCOC_RES_Q_519___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_519__RX_DCOC_RANGE_519___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_519__RX_DCOC_RANGE_519___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_519__RX_DCOC_RES_I_519___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_519__RX_DCOC_RES_I_519___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_519__RX_DCOC_RES_Q_519___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_519__RX_DCOC_RES_Q_519___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_519___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_519___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_520 (0x005EC820) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_520___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_520___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_520__RX_DCOC_RANGE_520___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_520__RX_DCOC_RES_I_520___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_520__RX_DCOC_RES_Q_520___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_520__RX_DCOC_RANGE_520___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_520__RX_DCOC_RANGE_520___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_520__RX_DCOC_RES_I_520___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_520__RX_DCOC_RES_I_520___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_520__RX_DCOC_RES_Q_520___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_520__RX_DCOC_RES_Q_520___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_520___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_520___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_521 (0x005EC824) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_521___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_521___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_521__RX_DCOC_RANGE_521___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_521__RX_DCOC_RES_I_521___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_521__RX_DCOC_RES_Q_521___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_521__RX_DCOC_RANGE_521___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_521__RX_DCOC_RANGE_521___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_521__RX_DCOC_RES_I_521___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_521__RX_DCOC_RES_I_521___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_521__RX_DCOC_RES_Q_521___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_521__RX_DCOC_RES_Q_521___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_521___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_521___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_522 (0x005EC828) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_522___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_522___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_522__RX_DCOC_RANGE_522___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_522__RX_DCOC_RES_I_522___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_522__RX_DCOC_RES_Q_522___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_522__RX_DCOC_RANGE_522___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_522__RX_DCOC_RANGE_522___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_522__RX_DCOC_RES_I_522___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_522__RX_DCOC_RES_I_522___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_522__RX_DCOC_RES_Q_522___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_522__RX_DCOC_RES_Q_522___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_522___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_522___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_523 (0x005EC82C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_523___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_523___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_523__RX_DCOC_RANGE_523___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_523__RX_DCOC_RES_I_523___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_523__RX_DCOC_RES_Q_523___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_523__RX_DCOC_RANGE_523___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_523__RX_DCOC_RANGE_523___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_523__RX_DCOC_RES_I_523___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_523__RX_DCOC_RES_I_523___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_523__RX_DCOC_RES_Q_523___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_523__RX_DCOC_RES_Q_523___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_523___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_523___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_524 (0x005EC830) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_524___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_524___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_524__RX_DCOC_RANGE_524___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_524__RX_DCOC_RES_I_524___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_524__RX_DCOC_RES_Q_524___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_524__RX_DCOC_RANGE_524___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_524__RX_DCOC_RANGE_524___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_524__RX_DCOC_RES_I_524___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_524__RX_DCOC_RES_I_524___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_524__RX_DCOC_RES_Q_524___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_524__RX_DCOC_RES_Q_524___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_524___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_524___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_525 (0x005EC834) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_525___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_525___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_525__RX_DCOC_RANGE_525___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_525__RX_DCOC_RES_I_525___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_525__RX_DCOC_RES_Q_525___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_525__RX_DCOC_RANGE_525___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_525__RX_DCOC_RANGE_525___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_525__RX_DCOC_RES_I_525___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_525__RX_DCOC_RES_I_525___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_525__RX_DCOC_RES_Q_525___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_525__RX_DCOC_RES_Q_525___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_525___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_525___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_526 (0x005EC838) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_526___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_526___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_526__RX_DCOC_RANGE_526___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_526__RX_DCOC_RES_I_526___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_526__RX_DCOC_RES_Q_526___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_526__RX_DCOC_RANGE_526___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_526__RX_DCOC_RANGE_526___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_526__RX_DCOC_RES_I_526___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_526__RX_DCOC_RES_I_526___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_526__RX_DCOC_RES_Q_526___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_526__RX_DCOC_RES_Q_526___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_526___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_526___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_527 (0x005EC83C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_527___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_527___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_527__RX_DCOC_RANGE_527___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_527__RX_DCOC_RES_I_527___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_527__RX_DCOC_RES_Q_527___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_527__RX_DCOC_RANGE_527___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_527__RX_DCOC_RANGE_527___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_527__RX_DCOC_RES_I_527___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_527__RX_DCOC_RES_I_527___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_527__RX_DCOC_RES_Q_527___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_527__RX_DCOC_RES_Q_527___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_527___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_527___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_528 (0x005EC840) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_528___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_528___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_528__RX_DCOC_RANGE_528___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_528__RX_DCOC_RES_I_528___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_528__RX_DCOC_RES_Q_528___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_528__RX_DCOC_RANGE_528___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_528__RX_DCOC_RANGE_528___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_528__RX_DCOC_RES_I_528___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_528__RX_DCOC_RES_I_528___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_528__RX_DCOC_RES_Q_528___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_528__RX_DCOC_RES_Q_528___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_528___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_528___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_529 (0x005EC844) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_529___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_529___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_529__RX_DCOC_RANGE_529___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_529__RX_DCOC_RES_I_529___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_529__RX_DCOC_RES_Q_529___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_529__RX_DCOC_RANGE_529___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_529__RX_DCOC_RANGE_529___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_529__RX_DCOC_RES_I_529___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_529__RX_DCOC_RES_I_529___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_529__RX_DCOC_RES_Q_529___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_529__RX_DCOC_RES_Q_529___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_529___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_529___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_530 (0x005EC848) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_530___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_530___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_530__RX_DCOC_RANGE_530___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_530__RX_DCOC_RES_I_530___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_530__RX_DCOC_RES_Q_530___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_530__RX_DCOC_RANGE_530___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_530__RX_DCOC_RANGE_530___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_530__RX_DCOC_RES_I_530___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_530__RX_DCOC_RES_I_530___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_530__RX_DCOC_RES_Q_530___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_530__RX_DCOC_RES_Q_530___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_530___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_530___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_531 (0x005EC84C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_531___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_531___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_531__RX_DCOC_RANGE_531___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_531__RX_DCOC_RES_I_531___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_531__RX_DCOC_RES_Q_531___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_531__RX_DCOC_RANGE_531___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_531__RX_DCOC_RANGE_531___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_531__RX_DCOC_RES_I_531___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_531__RX_DCOC_RES_I_531___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_531__RX_DCOC_RES_Q_531___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_531__RX_DCOC_RES_Q_531___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_531___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_531___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_532 (0x005EC850) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_532___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_532___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_532__RX_DCOC_RANGE_532___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_532__RX_DCOC_RES_I_532___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_532__RX_DCOC_RES_Q_532___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_532__RX_DCOC_RANGE_532___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_532__RX_DCOC_RANGE_532___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_532__RX_DCOC_RES_I_532___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_532__RX_DCOC_RES_I_532___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_532__RX_DCOC_RES_Q_532___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_532__RX_DCOC_RES_Q_532___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_532___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_532___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_533 (0x005EC854) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_533___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_533___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_533__RX_DCOC_RANGE_533___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_533__RX_DCOC_RES_I_533___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_533__RX_DCOC_RES_Q_533___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_533__RX_DCOC_RANGE_533___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_533__RX_DCOC_RANGE_533___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_533__RX_DCOC_RES_I_533___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_533__RX_DCOC_RES_I_533___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_533__RX_DCOC_RES_Q_533___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_533__RX_DCOC_RES_Q_533___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_533___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_533___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_534 (0x005EC858) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_534___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_534___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_534__RX_DCOC_RANGE_534___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_534__RX_DCOC_RES_I_534___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_534__RX_DCOC_RES_Q_534___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_534__RX_DCOC_RANGE_534___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_534__RX_DCOC_RANGE_534___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_534__RX_DCOC_RES_I_534___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_534__RX_DCOC_RES_I_534___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_534__RX_DCOC_RES_Q_534___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_534__RX_DCOC_RES_Q_534___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_534___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_534___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_535 (0x005EC85C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_535___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_535___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_535__RX_DCOC_RANGE_535___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_535__RX_DCOC_RES_I_535___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_535__RX_DCOC_RES_Q_535___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_535__RX_DCOC_RANGE_535___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_535__RX_DCOC_RANGE_535___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_535__RX_DCOC_RES_I_535___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_535__RX_DCOC_RES_I_535___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_535__RX_DCOC_RES_Q_535___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_535__RX_DCOC_RES_Q_535___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_535___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_535___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_536 (0x005EC860) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_536___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_536___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_536__RX_DCOC_RANGE_536___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_536__RX_DCOC_RES_I_536___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_536__RX_DCOC_RES_Q_536___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_536__RX_DCOC_RANGE_536___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_536__RX_DCOC_RANGE_536___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_536__RX_DCOC_RES_I_536___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_536__RX_DCOC_RES_I_536___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_536__RX_DCOC_RES_Q_536___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_536__RX_DCOC_RES_Q_536___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_536___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_536___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_537 (0x005EC864) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_537___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_537___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_537__RX_DCOC_RANGE_537___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_537__RX_DCOC_RES_I_537___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_537__RX_DCOC_RES_Q_537___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_537__RX_DCOC_RANGE_537___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_537__RX_DCOC_RANGE_537___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_537__RX_DCOC_RES_I_537___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_537__RX_DCOC_RES_I_537___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_537__RX_DCOC_RES_Q_537___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_537__RX_DCOC_RES_Q_537___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_537___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_537___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_538 (0x005EC868) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_538___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_538___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_538__RX_DCOC_RANGE_538___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_538__RX_DCOC_RES_I_538___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_538__RX_DCOC_RES_Q_538___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_538__RX_DCOC_RANGE_538___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_538__RX_DCOC_RANGE_538___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_538__RX_DCOC_RES_I_538___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_538__RX_DCOC_RES_I_538___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_538__RX_DCOC_RES_Q_538___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_538__RX_DCOC_RES_Q_538___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_538___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_538___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_539 (0x005EC86C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_539___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_539___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_539__RX_DCOC_RANGE_539___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_539__RX_DCOC_RES_I_539___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_539__RX_DCOC_RES_Q_539___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_539__RX_DCOC_RANGE_539___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_539__RX_DCOC_RANGE_539___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_539__RX_DCOC_RES_I_539___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_539__RX_DCOC_RES_I_539___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_539__RX_DCOC_RES_Q_539___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_539__RX_DCOC_RES_Q_539___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_539___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_539___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_540 (0x005EC870) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_540___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_540___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_540__RX_DCOC_RANGE_540___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_540__RX_DCOC_RES_I_540___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_540__RX_DCOC_RES_Q_540___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_540__RX_DCOC_RANGE_540___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_540__RX_DCOC_RANGE_540___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_540__RX_DCOC_RES_I_540___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_540__RX_DCOC_RES_I_540___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_540__RX_DCOC_RES_Q_540___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_540__RX_DCOC_RES_Q_540___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_540___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_540___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_541 (0x005EC874) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_541___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_541___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_541__RX_DCOC_RANGE_541___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_541__RX_DCOC_RES_I_541___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_541__RX_DCOC_RES_Q_541___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_541__RX_DCOC_RANGE_541___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_541__RX_DCOC_RANGE_541___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_541__RX_DCOC_RES_I_541___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_541__RX_DCOC_RES_I_541___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_541__RX_DCOC_RES_Q_541___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_541__RX_DCOC_RES_Q_541___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_541___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_541___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_542 (0x005EC878) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_542___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_542___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_542__RX_DCOC_RANGE_542___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_542__RX_DCOC_RES_I_542___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_542__RX_DCOC_RES_Q_542___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_542__RX_DCOC_RANGE_542___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_542__RX_DCOC_RANGE_542___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_542__RX_DCOC_RES_I_542___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_542__RX_DCOC_RES_I_542___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_542__RX_DCOC_RES_Q_542___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_542__RX_DCOC_RES_Q_542___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_542___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_542___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_543 (0x005EC87C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_543___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_543___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_543__RX_DCOC_RANGE_543___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_543__RX_DCOC_RES_I_543___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_543__RX_DCOC_RES_Q_543___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_543__RX_DCOC_RANGE_543___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_543__RX_DCOC_RANGE_543___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_543__RX_DCOC_RES_I_543___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_543__RX_DCOC_RES_I_543___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_543__RX_DCOC_RES_Q_543___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_543__RX_DCOC_RES_Q_543___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_543___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_543___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_544 (0x005EC880) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_544___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_544___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_544__RX_DCOC_RANGE_544___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_544__RX_DCOC_RES_I_544___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_544__RX_DCOC_RES_Q_544___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_544__RX_DCOC_RANGE_544___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_544__RX_DCOC_RANGE_544___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_544__RX_DCOC_RES_I_544___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_544__RX_DCOC_RES_I_544___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_544__RX_DCOC_RES_Q_544___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_544__RX_DCOC_RES_Q_544___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_544___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_544___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_545 (0x005EC884) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_545___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_545___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_545__RX_DCOC_RANGE_545___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_545__RX_DCOC_RES_I_545___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_545__RX_DCOC_RES_Q_545___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_545__RX_DCOC_RANGE_545___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_545__RX_DCOC_RANGE_545___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_545__RX_DCOC_RES_I_545___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_545__RX_DCOC_RES_I_545___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_545__RX_DCOC_RES_Q_545___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_545__RX_DCOC_RES_Q_545___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_545___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_545___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_546 (0x005EC888) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_546___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_546___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_546__RX_DCOC_RANGE_546___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_546__RX_DCOC_RES_I_546___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_546__RX_DCOC_RES_Q_546___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_546__RX_DCOC_RANGE_546___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_546__RX_DCOC_RANGE_546___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_546__RX_DCOC_RES_I_546___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_546__RX_DCOC_RES_I_546___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_546__RX_DCOC_RES_Q_546___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_546__RX_DCOC_RES_Q_546___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_546___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_546___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_547 (0x005EC88C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_547___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_547___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_547__RX_DCOC_RANGE_547___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_547__RX_DCOC_RES_I_547___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_547__RX_DCOC_RES_Q_547___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_547__RX_DCOC_RANGE_547___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_547__RX_DCOC_RANGE_547___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_547__RX_DCOC_RES_I_547___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_547__RX_DCOC_RES_I_547___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_547__RX_DCOC_RES_Q_547___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_547__RX_DCOC_RES_Q_547___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_547___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_547___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_548 (0x005EC890) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_548___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_548___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_548__RX_DCOC_RANGE_548___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_548__RX_DCOC_RES_I_548___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_548__RX_DCOC_RES_Q_548___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_548__RX_DCOC_RANGE_548___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_548__RX_DCOC_RANGE_548___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_548__RX_DCOC_RES_I_548___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_548__RX_DCOC_RES_I_548___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_548__RX_DCOC_RES_Q_548___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_548__RX_DCOC_RES_Q_548___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_548___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_548___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_549 (0x005EC894) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_549___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_549___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_549__RX_DCOC_RANGE_549___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_549__RX_DCOC_RES_I_549___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_549__RX_DCOC_RES_Q_549___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_549__RX_DCOC_RANGE_549___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_549__RX_DCOC_RANGE_549___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_549__RX_DCOC_RES_I_549___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_549__RX_DCOC_RES_I_549___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_549__RX_DCOC_RES_Q_549___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_549__RX_DCOC_RES_Q_549___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_549___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_549___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_550 (0x005EC898) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_550___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_550___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_550__RX_DCOC_RANGE_550___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_550__RX_DCOC_RES_I_550___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_550__RX_DCOC_RES_Q_550___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_550__RX_DCOC_RANGE_550___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_550__RX_DCOC_RANGE_550___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_550__RX_DCOC_RES_I_550___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_550__RX_DCOC_RES_I_550___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_550__RX_DCOC_RES_Q_550___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_550__RX_DCOC_RES_Q_550___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_550___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_550___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_551 (0x005EC89C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_551___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_551___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_551__RX_DCOC_RANGE_551___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_551__RX_DCOC_RES_I_551___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_551__RX_DCOC_RES_Q_551___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_551__RX_DCOC_RANGE_551___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_551__RX_DCOC_RANGE_551___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_551__RX_DCOC_RES_I_551___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_551__RX_DCOC_RES_I_551___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_551__RX_DCOC_RES_Q_551___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_551__RX_DCOC_RES_Q_551___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_551___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_551___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_552 (0x005EC8A0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_552___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_552___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_552__RX_DCOC_RANGE_552___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_552__RX_DCOC_RES_I_552___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_552__RX_DCOC_RES_Q_552___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_552__RX_DCOC_RANGE_552___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_552__RX_DCOC_RANGE_552___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_552__RX_DCOC_RES_I_552___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_552__RX_DCOC_RES_I_552___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_552__RX_DCOC_RES_Q_552___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_552__RX_DCOC_RES_Q_552___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_552___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_552___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_553 (0x005EC8A4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_553___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_553___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_553__RX_DCOC_RANGE_553___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_553__RX_DCOC_RES_I_553___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_553__RX_DCOC_RES_Q_553___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_553__RX_DCOC_RANGE_553___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_553__RX_DCOC_RANGE_553___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_553__RX_DCOC_RES_I_553___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_553__RX_DCOC_RES_I_553___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_553__RX_DCOC_RES_Q_553___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_553__RX_DCOC_RES_Q_553___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_553___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_553___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_554 (0x005EC8A8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_554___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_554___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_554__RX_DCOC_RANGE_554___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_554__RX_DCOC_RES_I_554___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_554__RX_DCOC_RES_Q_554___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_554__RX_DCOC_RANGE_554___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_554__RX_DCOC_RANGE_554___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_554__RX_DCOC_RES_I_554___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_554__RX_DCOC_RES_I_554___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_554__RX_DCOC_RES_Q_554___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_554__RX_DCOC_RES_Q_554___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_554___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_554___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_555 (0x005EC8AC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_555___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_555___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_555__RX_DCOC_RANGE_555___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_555__RX_DCOC_RES_I_555___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_555__RX_DCOC_RES_Q_555___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_555__RX_DCOC_RANGE_555___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_555__RX_DCOC_RANGE_555___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_555__RX_DCOC_RES_I_555___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_555__RX_DCOC_RES_I_555___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_555__RX_DCOC_RES_Q_555___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_555__RX_DCOC_RES_Q_555___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_555___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_555___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_556 (0x005EC8B0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_556___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_556___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_556__RX_DCOC_RANGE_556___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_556__RX_DCOC_RES_I_556___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_556__RX_DCOC_RES_Q_556___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_556__RX_DCOC_RANGE_556___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_556__RX_DCOC_RANGE_556___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_556__RX_DCOC_RES_I_556___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_556__RX_DCOC_RES_I_556___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_556__RX_DCOC_RES_Q_556___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_556__RX_DCOC_RES_Q_556___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_556___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_556___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_557 (0x005EC8B4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_557___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_557___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_557__RX_DCOC_RANGE_557___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_557__RX_DCOC_RES_I_557___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_557__RX_DCOC_RES_Q_557___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_557__RX_DCOC_RANGE_557___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_557__RX_DCOC_RANGE_557___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_557__RX_DCOC_RES_I_557___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_557__RX_DCOC_RES_I_557___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_557__RX_DCOC_RES_Q_557___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_557__RX_DCOC_RES_Q_557___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_557___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_557___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_558 (0x005EC8B8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_558___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_558___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_558__RX_DCOC_RANGE_558___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_558__RX_DCOC_RES_I_558___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_558__RX_DCOC_RES_Q_558___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_558__RX_DCOC_RANGE_558___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_558__RX_DCOC_RANGE_558___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_558__RX_DCOC_RES_I_558___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_558__RX_DCOC_RES_I_558___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_558__RX_DCOC_RES_Q_558___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_558__RX_DCOC_RES_Q_558___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_558___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_558___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_559 (0x005EC8BC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_559___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_559___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_559__RX_DCOC_RANGE_559___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_559__RX_DCOC_RES_I_559___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_559__RX_DCOC_RES_Q_559___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_559__RX_DCOC_RANGE_559___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_559__RX_DCOC_RANGE_559___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_559__RX_DCOC_RES_I_559___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_559__RX_DCOC_RES_I_559___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_559__RX_DCOC_RES_Q_559___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_559__RX_DCOC_RES_Q_559___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_559___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_559___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_560 (0x005EC8C0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_560___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_560___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_560__RX_DCOC_RANGE_560___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_560__RX_DCOC_RES_I_560___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_560__RX_DCOC_RES_Q_560___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_560__RX_DCOC_RANGE_560___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_560__RX_DCOC_RANGE_560___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_560__RX_DCOC_RES_I_560___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_560__RX_DCOC_RES_I_560___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_560__RX_DCOC_RES_Q_560___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_560__RX_DCOC_RES_Q_560___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_560___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_560___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_561 (0x005EC8C4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_561___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_561___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_561__RX_DCOC_RANGE_561___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_561__RX_DCOC_RES_I_561___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_561__RX_DCOC_RES_Q_561___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_561__RX_DCOC_RANGE_561___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_561__RX_DCOC_RANGE_561___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_561__RX_DCOC_RES_I_561___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_561__RX_DCOC_RES_I_561___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_561__RX_DCOC_RES_Q_561___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_561__RX_DCOC_RES_Q_561___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_561___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_561___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_562 (0x005EC8C8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_562___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_562___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_562__RX_DCOC_RANGE_562___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_562__RX_DCOC_RES_I_562___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_562__RX_DCOC_RES_Q_562___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_562__RX_DCOC_RANGE_562___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_562__RX_DCOC_RANGE_562___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_562__RX_DCOC_RES_I_562___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_562__RX_DCOC_RES_I_562___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_562__RX_DCOC_RES_Q_562___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_562__RX_DCOC_RES_Q_562___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_562___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_562___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_563 (0x005EC8CC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_563___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_563___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_563__RX_DCOC_RANGE_563___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_563__RX_DCOC_RES_I_563___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_563__RX_DCOC_RES_Q_563___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_563__RX_DCOC_RANGE_563___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_563__RX_DCOC_RANGE_563___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_563__RX_DCOC_RES_I_563___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_563__RX_DCOC_RES_I_563___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_563__RX_DCOC_RES_Q_563___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_563__RX_DCOC_RES_Q_563___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_563___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_563___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_564 (0x005EC8D0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_564___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_564___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_564__RX_DCOC_RANGE_564___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_564__RX_DCOC_RES_I_564___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_564__RX_DCOC_RES_Q_564___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_564__RX_DCOC_RANGE_564___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_564__RX_DCOC_RANGE_564___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_564__RX_DCOC_RES_I_564___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_564__RX_DCOC_RES_I_564___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_564__RX_DCOC_RES_Q_564___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_564__RX_DCOC_RES_Q_564___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_564___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_564___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_565 (0x005EC8D4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_565___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_565___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_565__RX_DCOC_RANGE_565___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_565__RX_DCOC_RES_I_565___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_565__RX_DCOC_RES_Q_565___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_565__RX_DCOC_RANGE_565___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_565__RX_DCOC_RANGE_565___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_565__RX_DCOC_RES_I_565___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_565__RX_DCOC_RES_I_565___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_565__RX_DCOC_RES_Q_565___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_565__RX_DCOC_RES_Q_565___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_565___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_565___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_566 (0x005EC8D8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_566___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_566___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_566__RX_DCOC_RANGE_566___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_566__RX_DCOC_RES_I_566___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_566__RX_DCOC_RES_Q_566___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_566__RX_DCOC_RANGE_566___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_566__RX_DCOC_RANGE_566___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_566__RX_DCOC_RES_I_566___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_566__RX_DCOC_RES_I_566___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_566__RX_DCOC_RES_Q_566___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_566__RX_DCOC_RES_Q_566___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_566___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_566___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_567 (0x005EC8DC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_567___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_567___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_567__RX_DCOC_RANGE_567___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_567__RX_DCOC_RES_I_567___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_567__RX_DCOC_RES_Q_567___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_567__RX_DCOC_RANGE_567___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_567__RX_DCOC_RANGE_567___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_567__RX_DCOC_RES_I_567___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_567__RX_DCOC_RES_I_567___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_567__RX_DCOC_RES_Q_567___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_567__RX_DCOC_RES_Q_567___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_567___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_567___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_568 (0x005EC8E0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_568___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_568___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_568__RX_DCOC_RANGE_568___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_568__RX_DCOC_RES_I_568___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_568__RX_DCOC_RES_Q_568___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_568__RX_DCOC_RANGE_568___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_568__RX_DCOC_RANGE_568___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_568__RX_DCOC_RES_I_568___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_568__RX_DCOC_RES_I_568___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_568__RX_DCOC_RES_Q_568___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_568__RX_DCOC_RES_Q_568___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_568___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_568___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_569 (0x005EC8E4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_569___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_569___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_569__RX_DCOC_RANGE_569___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_569__RX_DCOC_RES_I_569___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_569__RX_DCOC_RES_Q_569___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_569__RX_DCOC_RANGE_569___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_569__RX_DCOC_RANGE_569___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_569__RX_DCOC_RES_I_569___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_569__RX_DCOC_RES_I_569___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_569__RX_DCOC_RES_Q_569___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_569__RX_DCOC_RES_Q_569___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_569___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_569___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_570 (0x005EC8E8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_570___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_570___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_570__RX_DCOC_RANGE_570___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_570__RX_DCOC_RES_I_570___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_570__RX_DCOC_RES_Q_570___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_570__RX_DCOC_RANGE_570___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_570__RX_DCOC_RANGE_570___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_570__RX_DCOC_RES_I_570___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_570__RX_DCOC_RES_I_570___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_570__RX_DCOC_RES_Q_570___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_570__RX_DCOC_RES_Q_570___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_570___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_570___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_571 (0x005EC8EC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_571___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_571___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_571__RX_DCOC_RANGE_571___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_571__RX_DCOC_RES_I_571___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_571__RX_DCOC_RES_Q_571___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_571__RX_DCOC_RANGE_571___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_571__RX_DCOC_RANGE_571___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_571__RX_DCOC_RES_I_571___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_571__RX_DCOC_RES_I_571___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_571__RX_DCOC_RES_Q_571___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_571__RX_DCOC_RES_Q_571___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_571___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_571___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_572 (0x005EC8F0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_572___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_572___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_572__RX_DCOC_RANGE_572___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_572__RX_DCOC_RES_I_572___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_572__RX_DCOC_RES_Q_572___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_572__RX_DCOC_RANGE_572___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_572__RX_DCOC_RANGE_572___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_572__RX_DCOC_RES_I_572___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_572__RX_DCOC_RES_I_572___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_572__RX_DCOC_RES_Q_572___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_572__RX_DCOC_RES_Q_572___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_572___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_572___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_573 (0x005EC8F4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_573___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_573___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_573__RX_DCOC_RANGE_573___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_573__RX_DCOC_RES_I_573___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_573__RX_DCOC_RES_Q_573___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_573__RX_DCOC_RANGE_573___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_573__RX_DCOC_RANGE_573___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_573__RX_DCOC_RES_I_573___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_573__RX_DCOC_RES_I_573___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_573__RX_DCOC_RES_Q_573___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_573__RX_DCOC_RES_Q_573___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_573___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_573___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_574 (0x005EC8F8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_574___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_574___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_574__RX_DCOC_RANGE_574___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_574__RX_DCOC_RES_I_574___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_574__RX_DCOC_RES_Q_574___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_574__RX_DCOC_RANGE_574___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_574__RX_DCOC_RANGE_574___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_574__RX_DCOC_RES_I_574___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_574__RX_DCOC_RES_I_574___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_574__RX_DCOC_RES_Q_574___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_574__RX_DCOC_RES_Q_574___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_574___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_574___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_575 (0x005EC8FC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_575___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_575___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_575__RX_DCOC_RANGE_575___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_575__RX_DCOC_RES_I_575___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_575__RX_DCOC_RES_Q_575___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_575__RX_DCOC_RANGE_575___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_575__RX_DCOC_RANGE_575___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_575__RX_DCOC_RES_I_575___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_575__RX_DCOC_RES_I_575___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_575__RX_DCOC_RES_Q_575___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_575__RX_DCOC_RES_Q_575___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_575___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_575___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_576 (0x005EC900) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_576___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_576___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_576__RX_DCOC_RANGE_576___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_576__RX_DCOC_RES_I_576___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_576__RX_DCOC_RES_Q_576___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_576__RX_DCOC_RANGE_576___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_576__RX_DCOC_RANGE_576___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_576__RX_DCOC_RES_I_576___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_576__RX_DCOC_RES_I_576___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_576__RX_DCOC_RES_Q_576___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_576__RX_DCOC_RES_Q_576___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_576___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_576___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_577 (0x005EC904) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_577___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_577___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_577__RX_DCOC_RANGE_577___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_577__RX_DCOC_RES_I_577___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_577__RX_DCOC_RES_Q_577___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_577__RX_DCOC_RANGE_577___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_577__RX_DCOC_RANGE_577___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_577__RX_DCOC_RES_I_577___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_577__RX_DCOC_RES_I_577___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_577__RX_DCOC_RES_Q_577___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_577__RX_DCOC_RES_Q_577___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_577___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_577___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_578 (0x005EC908) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_578___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_578___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_578__RX_DCOC_RANGE_578___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_578__RX_DCOC_RES_I_578___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_578__RX_DCOC_RES_Q_578___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_578__RX_DCOC_RANGE_578___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_578__RX_DCOC_RANGE_578___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_578__RX_DCOC_RES_I_578___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_578__RX_DCOC_RES_I_578___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_578__RX_DCOC_RES_Q_578___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_578__RX_DCOC_RES_Q_578___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_578___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_578___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_579 (0x005EC90C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_579___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_579___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_579__RX_DCOC_RANGE_579___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_579__RX_DCOC_RES_I_579___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_579__RX_DCOC_RES_Q_579___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_579__RX_DCOC_RANGE_579___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_579__RX_DCOC_RANGE_579___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_579__RX_DCOC_RES_I_579___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_579__RX_DCOC_RES_I_579___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_579__RX_DCOC_RES_Q_579___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_579__RX_DCOC_RES_Q_579___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_579___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_579___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_580 (0x005EC910) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_580___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_580___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_580__RX_DCOC_RANGE_580___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_580__RX_DCOC_RES_I_580___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_580__RX_DCOC_RES_Q_580___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_580__RX_DCOC_RANGE_580___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_580__RX_DCOC_RANGE_580___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_580__RX_DCOC_RES_I_580___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_580__RX_DCOC_RES_I_580___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_580__RX_DCOC_RES_Q_580___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_580__RX_DCOC_RES_Q_580___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_580___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_580___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_581 (0x005EC914) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_581___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_581___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_581__RX_DCOC_RANGE_581___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_581__RX_DCOC_RES_I_581___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_581__RX_DCOC_RES_Q_581___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_581__RX_DCOC_RANGE_581___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_581__RX_DCOC_RANGE_581___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_581__RX_DCOC_RES_I_581___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_581__RX_DCOC_RES_I_581___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_581__RX_DCOC_RES_Q_581___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_581__RX_DCOC_RES_Q_581___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_581___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_581___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_582 (0x005EC918) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_582___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_582___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_582__RX_DCOC_RANGE_582___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_582__RX_DCOC_RES_I_582___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_582__RX_DCOC_RES_Q_582___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_582__RX_DCOC_RANGE_582___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_582__RX_DCOC_RANGE_582___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_582__RX_DCOC_RES_I_582___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_582__RX_DCOC_RES_I_582___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_582__RX_DCOC_RES_Q_582___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_582__RX_DCOC_RES_Q_582___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_582___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_582___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_583 (0x005EC91C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_583___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_583___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_583__RX_DCOC_RANGE_583___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_583__RX_DCOC_RES_I_583___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_583__RX_DCOC_RES_Q_583___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_583__RX_DCOC_RANGE_583___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_583__RX_DCOC_RANGE_583___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_583__RX_DCOC_RES_I_583___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_583__RX_DCOC_RES_I_583___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_583__RX_DCOC_RES_Q_583___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_583__RX_DCOC_RES_Q_583___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_583___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_583___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_584 (0x005EC920) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_584___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_584___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_584__RX_DCOC_RANGE_584___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_584__RX_DCOC_RES_I_584___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_584__RX_DCOC_RES_Q_584___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_584__RX_DCOC_RANGE_584___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_584__RX_DCOC_RANGE_584___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_584__RX_DCOC_RES_I_584___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_584__RX_DCOC_RES_I_584___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_584__RX_DCOC_RES_Q_584___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_584__RX_DCOC_RES_Q_584___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_584___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_584___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_585 (0x005EC924) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_585___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_585___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_585__RX_DCOC_RANGE_585___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_585__RX_DCOC_RES_I_585___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_585__RX_DCOC_RES_Q_585___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_585__RX_DCOC_RANGE_585___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_585__RX_DCOC_RANGE_585___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_585__RX_DCOC_RES_I_585___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_585__RX_DCOC_RES_I_585___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_585__RX_DCOC_RES_Q_585___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_585__RX_DCOC_RES_Q_585___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_585___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_585___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_586 (0x005EC928) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_586___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_586___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_586__RX_DCOC_RANGE_586___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_586__RX_DCOC_RES_I_586___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_586__RX_DCOC_RES_Q_586___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_586__RX_DCOC_RANGE_586___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_586__RX_DCOC_RANGE_586___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_586__RX_DCOC_RES_I_586___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_586__RX_DCOC_RES_I_586___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_586__RX_DCOC_RES_Q_586___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_586__RX_DCOC_RES_Q_586___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_586___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_586___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_587 (0x005EC92C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_587___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_587___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_587__RX_DCOC_RANGE_587___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_587__RX_DCOC_RES_I_587___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_587__RX_DCOC_RES_Q_587___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_587__RX_DCOC_RANGE_587___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_587__RX_DCOC_RANGE_587___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_587__RX_DCOC_RES_I_587___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_587__RX_DCOC_RES_I_587___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_587__RX_DCOC_RES_Q_587___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_587__RX_DCOC_RES_Q_587___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_587___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_587___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_588 (0x005EC930) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_588___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_588___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_588__RX_DCOC_RANGE_588___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_588__RX_DCOC_RES_I_588___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_588__RX_DCOC_RES_Q_588___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_588__RX_DCOC_RANGE_588___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_588__RX_DCOC_RANGE_588___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_588__RX_DCOC_RES_I_588___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_588__RX_DCOC_RES_I_588___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_588__RX_DCOC_RES_Q_588___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_588__RX_DCOC_RES_Q_588___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_588___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_588___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_589 (0x005EC934) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_589___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_589___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_589__RX_DCOC_RANGE_589___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_589__RX_DCOC_RES_I_589___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_589__RX_DCOC_RES_Q_589___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_589__RX_DCOC_RANGE_589___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_589__RX_DCOC_RANGE_589___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_589__RX_DCOC_RES_I_589___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_589__RX_DCOC_RES_I_589___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_589__RX_DCOC_RES_Q_589___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_589__RX_DCOC_RES_Q_589___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_589___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_589___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_590 (0x005EC938) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_590___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_590___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_590__RX_DCOC_RANGE_590___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_590__RX_DCOC_RES_I_590___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_590__RX_DCOC_RES_Q_590___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_590__RX_DCOC_RANGE_590___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_590__RX_DCOC_RANGE_590___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_590__RX_DCOC_RES_I_590___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_590__RX_DCOC_RES_I_590___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_590__RX_DCOC_RES_Q_590___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_590__RX_DCOC_RES_Q_590___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_590___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_590___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_591 (0x005EC93C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_591___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_591___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_591__RX_DCOC_RANGE_591___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_591__RX_DCOC_RES_I_591___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_591__RX_DCOC_RES_Q_591___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_591__RX_DCOC_RANGE_591___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_591__RX_DCOC_RANGE_591___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_591__RX_DCOC_RES_I_591___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_591__RX_DCOC_RES_I_591___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_591__RX_DCOC_RES_Q_591___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_591__RX_DCOC_RES_Q_591___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_591___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_591___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_592 (0x005EC940) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_592___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_592___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_592__RX_DCOC_RANGE_592___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_592__RX_DCOC_RES_I_592___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_592__RX_DCOC_RES_Q_592___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_592__RX_DCOC_RANGE_592___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_592__RX_DCOC_RANGE_592___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_592__RX_DCOC_RES_I_592___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_592__RX_DCOC_RES_I_592___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_592__RX_DCOC_RES_Q_592___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_592__RX_DCOC_RES_Q_592___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_592___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_592___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_593 (0x005EC944) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_593___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_593___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_593__RX_DCOC_RANGE_593___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_593__RX_DCOC_RES_I_593___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_593__RX_DCOC_RES_Q_593___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_593__RX_DCOC_RANGE_593___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_593__RX_DCOC_RANGE_593___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_593__RX_DCOC_RES_I_593___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_593__RX_DCOC_RES_I_593___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_593__RX_DCOC_RES_Q_593___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_593__RX_DCOC_RES_Q_593___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_593___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_593___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_594 (0x005EC948) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_594___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_594___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_594__RX_DCOC_RANGE_594___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_594__RX_DCOC_RES_I_594___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_594__RX_DCOC_RES_Q_594___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_594__RX_DCOC_RANGE_594___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_594__RX_DCOC_RANGE_594___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_594__RX_DCOC_RES_I_594___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_594__RX_DCOC_RES_I_594___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_594__RX_DCOC_RES_Q_594___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_594__RX_DCOC_RES_Q_594___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_594___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_594___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_595 (0x005EC94C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_595___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_595___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_595__RX_DCOC_RANGE_595___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_595__RX_DCOC_RES_I_595___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_595__RX_DCOC_RES_Q_595___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_595__RX_DCOC_RANGE_595___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_595__RX_DCOC_RANGE_595___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_595__RX_DCOC_RES_I_595___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_595__RX_DCOC_RES_I_595___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_595__RX_DCOC_RES_Q_595___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_595__RX_DCOC_RES_Q_595___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_595___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_595___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_596 (0x005EC950) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_596___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_596___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_596__RX_DCOC_RANGE_596___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_596__RX_DCOC_RES_I_596___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_596__RX_DCOC_RES_Q_596___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_596__RX_DCOC_RANGE_596___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_596__RX_DCOC_RANGE_596___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_596__RX_DCOC_RES_I_596___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_596__RX_DCOC_RES_I_596___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_596__RX_DCOC_RES_Q_596___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_596__RX_DCOC_RES_Q_596___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_596___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_596___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_597 (0x005EC954) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_597___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_597___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_597__RX_DCOC_RANGE_597___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_597__RX_DCOC_RES_I_597___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_597__RX_DCOC_RES_Q_597___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_597__RX_DCOC_RANGE_597___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_597__RX_DCOC_RANGE_597___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_597__RX_DCOC_RES_I_597___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_597__RX_DCOC_RES_I_597___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_597__RX_DCOC_RES_Q_597___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_597__RX_DCOC_RES_Q_597___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_597___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_597___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_598 (0x005EC958) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_598___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_598___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_598__RX_DCOC_RANGE_598___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_598__RX_DCOC_RES_I_598___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_598__RX_DCOC_RES_Q_598___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_598__RX_DCOC_RANGE_598___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_598__RX_DCOC_RANGE_598___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_598__RX_DCOC_RES_I_598___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_598__RX_DCOC_RES_I_598___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_598__RX_DCOC_RES_Q_598___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_598__RX_DCOC_RES_Q_598___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_598___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_598___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_599 (0x005EC95C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_599___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_599___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_599__RX_DCOC_RANGE_599___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_599__RX_DCOC_RES_I_599___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_599__RX_DCOC_RES_Q_599___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_599__RX_DCOC_RANGE_599___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_599__RX_DCOC_RANGE_599___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_599__RX_DCOC_RES_I_599___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_599__RX_DCOC_RES_I_599___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_599__RX_DCOC_RES_Q_599___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_599__RX_DCOC_RES_Q_599___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_599___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_599___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_600 (0x005EC960) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_600___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_600___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_600__RX_DCOC_RANGE_600___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_600__RX_DCOC_RES_I_600___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_600__RX_DCOC_RES_Q_600___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_600__RX_DCOC_RANGE_600___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_600__RX_DCOC_RANGE_600___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_600__RX_DCOC_RES_I_600___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_600__RX_DCOC_RES_I_600___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_600__RX_DCOC_RES_Q_600___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_600__RX_DCOC_RES_Q_600___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_600___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_600___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_601 (0x005EC964) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_601___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_601___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_601__RX_DCOC_RANGE_601___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_601__RX_DCOC_RES_I_601___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_601__RX_DCOC_RES_Q_601___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_601__RX_DCOC_RANGE_601___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_601__RX_DCOC_RANGE_601___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_601__RX_DCOC_RES_I_601___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_601__RX_DCOC_RES_I_601___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_601__RX_DCOC_RES_Q_601___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_601__RX_DCOC_RES_Q_601___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_601___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_601___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_602 (0x005EC968) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_602___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_602___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_602__RX_DCOC_RANGE_602___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_602__RX_DCOC_RES_I_602___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_602__RX_DCOC_RES_Q_602___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_602__RX_DCOC_RANGE_602___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_602__RX_DCOC_RANGE_602___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_602__RX_DCOC_RES_I_602___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_602__RX_DCOC_RES_I_602___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_602__RX_DCOC_RES_Q_602___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_602__RX_DCOC_RES_Q_602___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_602___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_602___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_603 (0x005EC96C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_603___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_603___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_603__RX_DCOC_RANGE_603___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_603__RX_DCOC_RES_I_603___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_603__RX_DCOC_RES_Q_603___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_603__RX_DCOC_RANGE_603___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_603__RX_DCOC_RANGE_603___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_603__RX_DCOC_RES_I_603___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_603__RX_DCOC_RES_I_603___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_603__RX_DCOC_RES_Q_603___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_603__RX_DCOC_RES_Q_603___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_603___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_603___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_604 (0x005EC970) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_604___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_604___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_604__RX_DCOC_RANGE_604___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_604__RX_DCOC_RES_I_604___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_604__RX_DCOC_RES_Q_604___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_604__RX_DCOC_RANGE_604___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_604__RX_DCOC_RANGE_604___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_604__RX_DCOC_RES_I_604___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_604__RX_DCOC_RES_I_604___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_604__RX_DCOC_RES_Q_604___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_604__RX_DCOC_RES_Q_604___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_604___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_604___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_605 (0x005EC974) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_605___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_605___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_605__RX_DCOC_RANGE_605___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_605__RX_DCOC_RES_I_605___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_605__RX_DCOC_RES_Q_605___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_605__RX_DCOC_RANGE_605___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_605__RX_DCOC_RANGE_605___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_605__RX_DCOC_RES_I_605___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_605__RX_DCOC_RES_I_605___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_605__RX_DCOC_RES_Q_605___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_605__RX_DCOC_RES_Q_605___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_605___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_605___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_606 (0x005EC978) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_606___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_606___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_606__RX_DCOC_RANGE_606___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_606__RX_DCOC_RES_I_606___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_606__RX_DCOC_RES_Q_606___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_606__RX_DCOC_RANGE_606___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_606__RX_DCOC_RANGE_606___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_606__RX_DCOC_RES_I_606___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_606__RX_DCOC_RES_I_606___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_606__RX_DCOC_RES_Q_606___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_606__RX_DCOC_RES_Q_606___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_606___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_606___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_607 (0x005EC97C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_607___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_607___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_607__RX_DCOC_RANGE_607___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_607__RX_DCOC_RES_I_607___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_607__RX_DCOC_RES_Q_607___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_607__RX_DCOC_RANGE_607___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_607__RX_DCOC_RANGE_607___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_607__RX_DCOC_RES_I_607___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_607__RX_DCOC_RES_I_607___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_607__RX_DCOC_RES_Q_607___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_607__RX_DCOC_RES_Q_607___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_607___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_607___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_608 (0x005EC980) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_608___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_608___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_608__RX_DCOC_RANGE_608___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_608__RX_DCOC_RES_I_608___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_608__RX_DCOC_RES_Q_608___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_608__RX_DCOC_RANGE_608___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_608__RX_DCOC_RANGE_608___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_608__RX_DCOC_RES_I_608___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_608__RX_DCOC_RES_I_608___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_608__RX_DCOC_RES_Q_608___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_608__RX_DCOC_RES_Q_608___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_608___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_608___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_609 (0x005EC984) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_609___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_609___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_609__RX_DCOC_RANGE_609___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_609__RX_DCOC_RES_I_609___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_609__RX_DCOC_RES_Q_609___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_609__RX_DCOC_RANGE_609___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_609__RX_DCOC_RANGE_609___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_609__RX_DCOC_RES_I_609___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_609__RX_DCOC_RES_I_609___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_609__RX_DCOC_RES_Q_609___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_609__RX_DCOC_RES_Q_609___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_609___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_609___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_610 (0x005EC988) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_610___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_610___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_610__RX_DCOC_RANGE_610___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_610__RX_DCOC_RES_I_610___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_610__RX_DCOC_RES_Q_610___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_610__RX_DCOC_RANGE_610___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_610__RX_DCOC_RANGE_610___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_610__RX_DCOC_RES_I_610___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_610__RX_DCOC_RES_I_610___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_610__RX_DCOC_RES_Q_610___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_610__RX_DCOC_RES_Q_610___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_610___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_610___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_611 (0x005EC98C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_611___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_611___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_611__RX_DCOC_RANGE_611___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_611__RX_DCOC_RES_I_611___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_611__RX_DCOC_RES_Q_611___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_611__RX_DCOC_RANGE_611___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_611__RX_DCOC_RANGE_611___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_611__RX_DCOC_RES_I_611___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_611__RX_DCOC_RES_I_611___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_611__RX_DCOC_RES_Q_611___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_611__RX_DCOC_RES_Q_611___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_611___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_611___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_612 (0x005EC990) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_612___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_612___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_612__RX_DCOC_RANGE_612___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_612__RX_DCOC_RES_I_612___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_612__RX_DCOC_RES_Q_612___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_612__RX_DCOC_RANGE_612___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_612__RX_DCOC_RANGE_612___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_612__RX_DCOC_RES_I_612___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_612__RX_DCOC_RES_I_612___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_612__RX_DCOC_RES_Q_612___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_612__RX_DCOC_RES_Q_612___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_612___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_612___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_613 (0x005EC994) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_613___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_613___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_613__RX_DCOC_RANGE_613___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_613__RX_DCOC_RES_I_613___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_613__RX_DCOC_RES_Q_613___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_613__RX_DCOC_RANGE_613___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_613__RX_DCOC_RANGE_613___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_613__RX_DCOC_RES_I_613___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_613__RX_DCOC_RES_I_613___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_613__RX_DCOC_RES_Q_613___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_613__RX_DCOC_RES_Q_613___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_613___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_613___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_614 (0x005EC998) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_614___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_614___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_614__RX_DCOC_RANGE_614___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_614__RX_DCOC_RES_I_614___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_614__RX_DCOC_RES_Q_614___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_614__RX_DCOC_RANGE_614___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_614__RX_DCOC_RANGE_614___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_614__RX_DCOC_RES_I_614___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_614__RX_DCOC_RES_I_614___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_614__RX_DCOC_RES_Q_614___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_614__RX_DCOC_RES_Q_614___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_614___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_614___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_615 (0x005EC99C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_615___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_615___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_615__RX_DCOC_RANGE_615___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_615__RX_DCOC_RES_I_615___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_615__RX_DCOC_RES_Q_615___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_615__RX_DCOC_RANGE_615___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_615__RX_DCOC_RANGE_615___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_615__RX_DCOC_RES_I_615___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_615__RX_DCOC_RES_I_615___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_615__RX_DCOC_RES_Q_615___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_615__RX_DCOC_RES_Q_615___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_615___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_615___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_616 (0x005EC9A0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_616___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_616___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_616__RX_DCOC_RANGE_616___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_616__RX_DCOC_RES_I_616___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_616__RX_DCOC_RES_Q_616___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_616__RX_DCOC_RANGE_616___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_616__RX_DCOC_RANGE_616___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_616__RX_DCOC_RES_I_616___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_616__RX_DCOC_RES_I_616___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_616__RX_DCOC_RES_Q_616___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_616__RX_DCOC_RES_Q_616___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_616___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_616___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_617 (0x005EC9A4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_617___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_617___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_617__RX_DCOC_RANGE_617___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_617__RX_DCOC_RES_I_617___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_617__RX_DCOC_RES_Q_617___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_617__RX_DCOC_RANGE_617___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_617__RX_DCOC_RANGE_617___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_617__RX_DCOC_RES_I_617___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_617__RX_DCOC_RES_I_617___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_617__RX_DCOC_RES_Q_617___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_617__RX_DCOC_RES_Q_617___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_617___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_617___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_618 (0x005EC9A8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_618___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_618___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_618__RX_DCOC_RANGE_618___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_618__RX_DCOC_RES_I_618___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_618__RX_DCOC_RES_Q_618___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_618__RX_DCOC_RANGE_618___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_618__RX_DCOC_RANGE_618___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_618__RX_DCOC_RES_I_618___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_618__RX_DCOC_RES_I_618___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_618__RX_DCOC_RES_Q_618___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_618__RX_DCOC_RES_Q_618___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_618___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_618___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_619 (0x005EC9AC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_619___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_619___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_619__RX_DCOC_RANGE_619___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_619__RX_DCOC_RES_I_619___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_619__RX_DCOC_RES_Q_619___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_619__RX_DCOC_RANGE_619___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_619__RX_DCOC_RANGE_619___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_619__RX_DCOC_RES_I_619___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_619__RX_DCOC_RES_I_619___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_619__RX_DCOC_RES_Q_619___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_619__RX_DCOC_RES_Q_619___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_619___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_619___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_620 (0x005EC9B0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_620___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_620___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_620__RX_DCOC_RANGE_620___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_620__RX_DCOC_RES_I_620___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_620__RX_DCOC_RES_Q_620___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_620__RX_DCOC_RANGE_620___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_620__RX_DCOC_RANGE_620___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_620__RX_DCOC_RES_I_620___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_620__RX_DCOC_RES_I_620___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_620__RX_DCOC_RES_Q_620___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_620__RX_DCOC_RES_Q_620___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_620___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_620___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_621 (0x005EC9B4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_621___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_621___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_621__RX_DCOC_RANGE_621___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_621__RX_DCOC_RES_I_621___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_621__RX_DCOC_RES_Q_621___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_621__RX_DCOC_RANGE_621___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_621__RX_DCOC_RANGE_621___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_621__RX_DCOC_RES_I_621___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_621__RX_DCOC_RES_I_621___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_621__RX_DCOC_RES_Q_621___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_621__RX_DCOC_RES_Q_621___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_621___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_621___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_622 (0x005EC9B8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_622___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_622___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_622__RX_DCOC_RANGE_622___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_622__RX_DCOC_RES_I_622___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_622__RX_DCOC_RES_Q_622___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_622__RX_DCOC_RANGE_622___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_622__RX_DCOC_RANGE_622___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_622__RX_DCOC_RES_I_622___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_622__RX_DCOC_RES_I_622___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_622__RX_DCOC_RES_Q_622___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_622__RX_DCOC_RES_Q_622___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_622___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_622___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_623 (0x005EC9BC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_623___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_623___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_623__RX_DCOC_RANGE_623___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_623__RX_DCOC_RES_I_623___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_623__RX_DCOC_RES_Q_623___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_623__RX_DCOC_RANGE_623___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_623__RX_DCOC_RANGE_623___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_623__RX_DCOC_RES_I_623___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_623__RX_DCOC_RES_I_623___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_623__RX_DCOC_RES_Q_623___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_623__RX_DCOC_RES_Q_623___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_623___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_623___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_624 (0x005EC9C0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_624___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_624___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_624__RX_DCOC_RANGE_624___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_624__RX_DCOC_RES_I_624___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_624__RX_DCOC_RES_Q_624___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_624__RX_DCOC_RANGE_624___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_624__RX_DCOC_RANGE_624___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_624__RX_DCOC_RES_I_624___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_624__RX_DCOC_RES_I_624___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_624__RX_DCOC_RES_Q_624___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_624__RX_DCOC_RES_Q_624___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_624___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_624___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_625 (0x005EC9C4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_625___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_625___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_625__RX_DCOC_RANGE_625___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_625__RX_DCOC_RES_I_625___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_625__RX_DCOC_RES_Q_625___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_625__RX_DCOC_RANGE_625___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_625__RX_DCOC_RANGE_625___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_625__RX_DCOC_RES_I_625___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_625__RX_DCOC_RES_I_625___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_625__RX_DCOC_RES_Q_625___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_625__RX_DCOC_RES_Q_625___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_625___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_625___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_626 (0x005EC9C8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_626___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_626___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_626__RX_DCOC_RANGE_626___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_626__RX_DCOC_RES_I_626___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_626__RX_DCOC_RES_Q_626___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_626__RX_DCOC_RANGE_626___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_626__RX_DCOC_RANGE_626___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_626__RX_DCOC_RES_I_626___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_626__RX_DCOC_RES_I_626___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_626__RX_DCOC_RES_Q_626___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_626__RX_DCOC_RES_Q_626___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_626___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_626___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_627 (0x005EC9CC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_627___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_627___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_627__RX_DCOC_RANGE_627___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_627__RX_DCOC_RES_I_627___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_627__RX_DCOC_RES_Q_627___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_627__RX_DCOC_RANGE_627___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_627__RX_DCOC_RANGE_627___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_627__RX_DCOC_RES_I_627___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_627__RX_DCOC_RES_I_627___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_627__RX_DCOC_RES_Q_627___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_627__RX_DCOC_RES_Q_627___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_627___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_627___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_628 (0x005EC9D0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_628___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_628___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_628__RX_DCOC_RANGE_628___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_628__RX_DCOC_RES_I_628___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_628__RX_DCOC_RES_Q_628___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_628__RX_DCOC_RANGE_628___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_628__RX_DCOC_RANGE_628___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_628__RX_DCOC_RES_I_628___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_628__RX_DCOC_RES_I_628___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_628__RX_DCOC_RES_Q_628___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_628__RX_DCOC_RES_Q_628___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_628___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_628___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_629 (0x005EC9D4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_629___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_629___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_629__RX_DCOC_RANGE_629___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_629__RX_DCOC_RES_I_629___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_629__RX_DCOC_RES_Q_629___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_629__RX_DCOC_RANGE_629___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_629__RX_DCOC_RANGE_629___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_629__RX_DCOC_RES_I_629___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_629__RX_DCOC_RES_I_629___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_629__RX_DCOC_RES_Q_629___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_629__RX_DCOC_RES_Q_629___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_629___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_629___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_630 (0x005EC9D8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_630___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_630___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_630__RX_DCOC_RANGE_630___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_630__RX_DCOC_RES_I_630___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_630__RX_DCOC_RES_Q_630___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_630__RX_DCOC_RANGE_630___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_630__RX_DCOC_RANGE_630___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_630__RX_DCOC_RES_I_630___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_630__RX_DCOC_RES_I_630___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_630__RX_DCOC_RES_Q_630___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_630__RX_DCOC_RES_Q_630___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_630___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_630___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_631 (0x005EC9DC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_631___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_631___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_631__RX_DCOC_RANGE_631___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_631__RX_DCOC_RES_I_631___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_631__RX_DCOC_RES_Q_631___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_631__RX_DCOC_RANGE_631___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_631__RX_DCOC_RANGE_631___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_631__RX_DCOC_RES_I_631___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_631__RX_DCOC_RES_I_631___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_631__RX_DCOC_RES_Q_631___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_631__RX_DCOC_RES_Q_631___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_631___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_631___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_632 (0x005EC9E0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_632___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_632___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_632__RX_DCOC_RANGE_632___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_632__RX_DCOC_RES_I_632___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_632__RX_DCOC_RES_Q_632___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_632__RX_DCOC_RANGE_632___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_632__RX_DCOC_RANGE_632___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_632__RX_DCOC_RES_I_632___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_632__RX_DCOC_RES_I_632___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_632__RX_DCOC_RES_Q_632___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_632__RX_DCOC_RES_Q_632___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_632___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_632___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_633 (0x005EC9E4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_633___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_633___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_633__RX_DCOC_RANGE_633___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_633__RX_DCOC_RES_I_633___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_633__RX_DCOC_RES_Q_633___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_633__RX_DCOC_RANGE_633___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_633__RX_DCOC_RANGE_633___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_633__RX_DCOC_RES_I_633___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_633__RX_DCOC_RES_I_633___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_633__RX_DCOC_RES_Q_633___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_633__RX_DCOC_RES_Q_633___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_633___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_633___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_634 (0x005EC9E8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_634___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_634___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_634__RX_DCOC_RANGE_634___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_634__RX_DCOC_RES_I_634___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_634__RX_DCOC_RES_Q_634___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_634__RX_DCOC_RANGE_634___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_634__RX_DCOC_RANGE_634___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_634__RX_DCOC_RES_I_634___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_634__RX_DCOC_RES_I_634___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_634__RX_DCOC_RES_Q_634___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_634__RX_DCOC_RES_Q_634___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_634___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_634___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_635 (0x005EC9EC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_635___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_635___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_635__RX_DCOC_RANGE_635___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_635__RX_DCOC_RES_I_635___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_635__RX_DCOC_RES_Q_635___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_635__RX_DCOC_RANGE_635___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_635__RX_DCOC_RANGE_635___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_635__RX_DCOC_RES_I_635___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_635__RX_DCOC_RES_I_635___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_635__RX_DCOC_RES_Q_635___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_635__RX_DCOC_RES_Q_635___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_635___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_635___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_636 (0x005EC9F0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_636___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_636___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_636__RX_DCOC_RANGE_636___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_636__RX_DCOC_RES_I_636___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_636__RX_DCOC_RES_Q_636___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_636__RX_DCOC_RANGE_636___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_636__RX_DCOC_RANGE_636___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_636__RX_DCOC_RES_I_636___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_636__RX_DCOC_RES_I_636___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_636__RX_DCOC_RES_Q_636___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_636__RX_DCOC_RES_Q_636___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_636___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_636___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_637 (0x005EC9F4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_637___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_637___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_637__RX_DCOC_RANGE_637___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_637__RX_DCOC_RES_I_637___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_637__RX_DCOC_RES_Q_637___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_637__RX_DCOC_RANGE_637___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_637__RX_DCOC_RANGE_637___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_637__RX_DCOC_RES_I_637___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_637__RX_DCOC_RES_I_637___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_637__RX_DCOC_RES_Q_637___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_637__RX_DCOC_RES_Q_637___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_637___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_637___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_638 (0x005EC9F8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_638___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_638___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_638__RX_DCOC_RANGE_638___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_638__RX_DCOC_RES_I_638___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_638__RX_DCOC_RES_Q_638___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_638__RX_DCOC_RANGE_638___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_638__RX_DCOC_RANGE_638___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_638__RX_DCOC_RES_I_638___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_638__RX_DCOC_RES_I_638___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_638__RX_DCOC_RES_Q_638___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_638__RX_DCOC_RES_Q_638___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_638___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_638___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_639 (0x005EC9FC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_639___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_639___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_639__RX_DCOC_RANGE_639___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_639__RX_DCOC_RES_I_639___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_639__RX_DCOC_RES_Q_639___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_639__RX_DCOC_RANGE_639___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_639__RX_DCOC_RANGE_639___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_639__RX_DCOC_RES_I_639___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_639__RX_DCOC_RES_I_639___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_639__RX_DCOC_RES_Q_639___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_639__RX_DCOC_RES_Q_639___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_639___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_639___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_640 (0x005ECA00) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_640___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_640___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_640__RX_DCOC_RANGE_640___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_640__RX_DCOC_RES_I_640___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_640__RX_DCOC_RES_Q_640___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_640__RX_DCOC_RANGE_640___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_640__RX_DCOC_RANGE_640___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_640__RX_DCOC_RES_I_640___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_640__RX_DCOC_RES_I_640___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_640__RX_DCOC_RES_Q_640___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_640__RX_DCOC_RES_Q_640___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_640___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_640___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_641 (0x005ECA04) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_641___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_641___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_641__RX_DCOC_RANGE_641___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_641__RX_DCOC_RES_I_641___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_641__RX_DCOC_RES_Q_641___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_641__RX_DCOC_RANGE_641___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_641__RX_DCOC_RANGE_641___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_641__RX_DCOC_RES_I_641___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_641__RX_DCOC_RES_I_641___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_641__RX_DCOC_RES_Q_641___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_641__RX_DCOC_RES_Q_641___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_641___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_641___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_642 (0x005ECA08) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_642___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_642___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_642__RX_DCOC_RANGE_642___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_642__RX_DCOC_RES_I_642___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_642__RX_DCOC_RES_Q_642___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_642__RX_DCOC_RANGE_642___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_642__RX_DCOC_RANGE_642___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_642__RX_DCOC_RES_I_642___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_642__RX_DCOC_RES_I_642___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_642__RX_DCOC_RES_Q_642___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_642__RX_DCOC_RES_Q_642___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_642___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_642___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_643 (0x005ECA0C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_643___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_643___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_643__RX_DCOC_RANGE_643___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_643__RX_DCOC_RES_I_643___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_643__RX_DCOC_RES_Q_643___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_643__RX_DCOC_RANGE_643___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_643__RX_DCOC_RANGE_643___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_643__RX_DCOC_RES_I_643___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_643__RX_DCOC_RES_I_643___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_643__RX_DCOC_RES_Q_643___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_643__RX_DCOC_RES_Q_643___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_643___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_643___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_644 (0x005ECA10) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_644___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_644___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_644__RX_DCOC_RANGE_644___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_644__RX_DCOC_RES_I_644___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_644__RX_DCOC_RES_Q_644___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_644__RX_DCOC_RANGE_644___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_644__RX_DCOC_RANGE_644___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_644__RX_DCOC_RES_I_644___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_644__RX_DCOC_RES_I_644___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_644__RX_DCOC_RES_Q_644___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_644__RX_DCOC_RES_Q_644___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_644___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_644___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_645 (0x005ECA14) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_645___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_645___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_645__RX_DCOC_RANGE_645___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_645__RX_DCOC_RES_I_645___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_645__RX_DCOC_RES_Q_645___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_645__RX_DCOC_RANGE_645___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_645__RX_DCOC_RANGE_645___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_645__RX_DCOC_RES_I_645___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_645__RX_DCOC_RES_I_645___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_645__RX_DCOC_RES_Q_645___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_645__RX_DCOC_RES_Q_645___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_645___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_645___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_646 (0x005ECA18) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_646___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_646___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_646__RX_DCOC_RANGE_646___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_646__RX_DCOC_RES_I_646___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_646__RX_DCOC_RES_Q_646___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_646__RX_DCOC_RANGE_646___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_646__RX_DCOC_RANGE_646___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_646__RX_DCOC_RES_I_646___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_646__RX_DCOC_RES_I_646___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_646__RX_DCOC_RES_Q_646___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_646__RX_DCOC_RES_Q_646___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_646___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_646___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_647 (0x005ECA1C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_647___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_647___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_647__RX_DCOC_RANGE_647___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_647__RX_DCOC_RES_I_647___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_647__RX_DCOC_RES_Q_647___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_647__RX_DCOC_RANGE_647___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_647__RX_DCOC_RANGE_647___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_647__RX_DCOC_RES_I_647___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_647__RX_DCOC_RES_I_647___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_647__RX_DCOC_RES_Q_647___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_647__RX_DCOC_RES_Q_647___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_647___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_647___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_648 (0x005ECA20) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_648___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_648___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_648__RX_DCOC_RANGE_648___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_648__RX_DCOC_RES_I_648___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_648__RX_DCOC_RES_Q_648___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_648__RX_DCOC_RANGE_648___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_648__RX_DCOC_RANGE_648___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_648__RX_DCOC_RES_I_648___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_648__RX_DCOC_RES_I_648___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_648__RX_DCOC_RES_Q_648___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_648__RX_DCOC_RES_Q_648___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_648___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_648___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_649 (0x005ECA24) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_649___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_649___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_649__RX_DCOC_RANGE_649___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_649__RX_DCOC_RES_I_649___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_649__RX_DCOC_RES_Q_649___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_649__RX_DCOC_RANGE_649___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_649__RX_DCOC_RANGE_649___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_649__RX_DCOC_RES_I_649___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_649__RX_DCOC_RES_I_649___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_649__RX_DCOC_RES_Q_649___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_649__RX_DCOC_RES_Q_649___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_649___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_649___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_650 (0x005ECA28) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_650___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_650___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_650__RX_DCOC_RANGE_650___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_650__RX_DCOC_RES_I_650___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_650__RX_DCOC_RES_Q_650___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_650__RX_DCOC_RANGE_650___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_650__RX_DCOC_RANGE_650___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_650__RX_DCOC_RES_I_650___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_650__RX_DCOC_RES_I_650___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_650__RX_DCOC_RES_Q_650___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_650__RX_DCOC_RES_Q_650___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_650___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_650___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_651 (0x005ECA2C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_651___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_651___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_651__RX_DCOC_RANGE_651___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_651__RX_DCOC_RES_I_651___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_651__RX_DCOC_RES_Q_651___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_651__RX_DCOC_RANGE_651___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_651__RX_DCOC_RANGE_651___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_651__RX_DCOC_RES_I_651___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_651__RX_DCOC_RES_I_651___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_651__RX_DCOC_RES_Q_651___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_651__RX_DCOC_RES_Q_651___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_651___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_651___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_652 (0x005ECA30) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_652___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_652___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_652__RX_DCOC_RANGE_652___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_652__RX_DCOC_RES_I_652___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_652__RX_DCOC_RES_Q_652___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_652__RX_DCOC_RANGE_652___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_652__RX_DCOC_RANGE_652___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_652__RX_DCOC_RES_I_652___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_652__RX_DCOC_RES_I_652___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_652__RX_DCOC_RES_Q_652___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_652__RX_DCOC_RES_Q_652___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_652___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_652___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_653 (0x005ECA34) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_653___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_653___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_653__RX_DCOC_RANGE_653___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_653__RX_DCOC_RES_I_653___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_653__RX_DCOC_RES_Q_653___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_653__RX_DCOC_RANGE_653___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_653__RX_DCOC_RANGE_653___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_653__RX_DCOC_RES_I_653___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_653__RX_DCOC_RES_I_653___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_653__RX_DCOC_RES_Q_653___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_653__RX_DCOC_RES_Q_653___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_653___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_653___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_654 (0x005ECA38) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_654___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_654___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_654__RX_DCOC_RANGE_654___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_654__RX_DCOC_RES_I_654___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_654__RX_DCOC_RES_Q_654___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_654__RX_DCOC_RANGE_654___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_654__RX_DCOC_RANGE_654___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_654__RX_DCOC_RES_I_654___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_654__RX_DCOC_RES_I_654___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_654__RX_DCOC_RES_Q_654___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_654__RX_DCOC_RES_Q_654___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_654___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_654___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_655 (0x005ECA3C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_655___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_655___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_655__RX_DCOC_RANGE_655___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_655__RX_DCOC_RES_I_655___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_655__RX_DCOC_RES_Q_655___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_655__RX_DCOC_RANGE_655___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_655__RX_DCOC_RANGE_655___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_655__RX_DCOC_RES_I_655___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_655__RX_DCOC_RES_I_655___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_655__RX_DCOC_RES_Q_655___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_655__RX_DCOC_RES_Q_655___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_655___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_655___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_656 (0x005ECA40) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_656___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_656___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_656__RX_DCOC_RANGE_656___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_656__RX_DCOC_RES_I_656___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_656__RX_DCOC_RES_Q_656___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_656__RX_DCOC_RANGE_656___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_656__RX_DCOC_RANGE_656___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_656__RX_DCOC_RES_I_656___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_656__RX_DCOC_RES_I_656___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_656__RX_DCOC_RES_Q_656___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_656__RX_DCOC_RES_Q_656___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_656___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_656___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_657 (0x005ECA44) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_657___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_657___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_657__RX_DCOC_RANGE_657___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_657__RX_DCOC_RES_I_657___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_657__RX_DCOC_RES_Q_657___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_657__RX_DCOC_RANGE_657___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_657__RX_DCOC_RANGE_657___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_657__RX_DCOC_RES_I_657___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_657__RX_DCOC_RES_I_657___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_657__RX_DCOC_RES_Q_657___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_657__RX_DCOC_RES_Q_657___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_657___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_657___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_658 (0x005ECA48) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_658___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_658___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_658__RX_DCOC_RANGE_658___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_658__RX_DCOC_RES_I_658___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_658__RX_DCOC_RES_Q_658___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_658__RX_DCOC_RANGE_658___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_658__RX_DCOC_RANGE_658___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_658__RX_DCOC_RES_I_658___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_658__RX_DCOC_RES_I_658___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_658__RX_DCOC_RES_Q_658___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_658__RX_DCOC_RES_Q_658___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_658___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_658___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_659 (0x005ECA4C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_659___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_659___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_659__RX_DCOC_RANGE_659___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_659__RX_DCOC_RES_I_659___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_659__RX_DCOC_RES_Q_659___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_659__RX_DCOC_RANGE_659___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_659__RX_DCOC_RANGE_659___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_659__RX_DCOC_RES_I_659___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_659__RX_DCOC_RES_I_659___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_659__RX_DCOC_RES_Q_659___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_659__RX_DCOC_RES_Q_659___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_659___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_659___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_660 (0x005ECA50) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_660___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_660___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_660__RX_DCOC_RANGE_660___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_660__RX_DCOC_RES_I_660___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_660__RX_DCOC_RES_Q_660___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_660__RX_DCOC_RANGE_660___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_660__RX_DCOC_RANGE_660___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_660__RX_DCOC_RES_I_660___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_660__RX_DCOC_RES_I_660___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_660__RX_DCOC_RES_Q_660___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_660__RX_DCOC_RES_Q_660___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_660___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_660___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_661 (0x005ECA54) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_661___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_661___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_661__RX_DCOC_RANGE_661___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_661__RX_DCOC_RES_I_661___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_661__RX_DCOC_RES_Q_661___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_661__RX_DCOC_RANGE_661___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_661__RX_DCOC_RANGE_661___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_661__RX_DCOC_RES_I_661___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_661__RX_DCOC_RES_I_661___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_661__RX_DCOC_RES_Q_661___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_661__RX_DCOC_RES_Q_661___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_661___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_661___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_662 (0x005ECA58) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_662___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_662___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_662__RX_DCOC_RANGE_662___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_662__RX_DCOC_RES_I_662___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_662__RX_DCOC_RES_Q_662___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_662__RX_DCOC_RANGE_662___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_662__RX_DCOC_RANGE_662___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_662__RX_DCOC_RES_I_662___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_662__RX_DCOC_RES_I_662___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_662__RX_DCOC_RES_Q_662___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_662__RX_DCOC_RES_Q_662___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_662___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_662___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_663 (0x005ECA5C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_663___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_663___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_663__RX_DCOC_RANGE_663___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_663__RX_DCOC_RES_I_663___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_663__RX_DCOC_RES_Q_663___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_663__RX_DCOC_RANGE_663___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_663__RX_DCOC_RANGE_663___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_663__RX_DCOC_RES_I_663___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_663__RX_DCOC_RES_I_663___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_663__RX_DCOC_RES_Q_663___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_663__RX_DCOC_RES_Q_663___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_663___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_663___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_664 (0x005ECA60) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_664___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_664___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_664__RX_DCOC_RANGE_664___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_664__RX_DCOC_RES_I_664___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_664__RX_DCOC_RES_Q_664___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_664__RX_DCOC_RANGE_664___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_664__RX_DCOC_RANGE_664___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_664__RX_DCOC_RES_I_664___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_664__RX_DCOC_RES_I_664___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_664__RX_DCOC_RES_Q_664___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_664__RX_DCOC_RES_Q_664___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_664___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_664___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_665 (0x005ECA64) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_665___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_665___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_665__RX_DCOC_RANGE_665___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_665__RX_DCOC_RES_I_665___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_665__RX_DCOC_RES_Q_665___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_665__RX_DCOC_RANGE_665___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_665__RX_DCOC_RANGE_665___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_665__RX_DCOC_RES_I_665___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_665__RX_DCOC_RES_I_665___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_665__RX_DCOC_RES_Q_665___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_665__RX_DCOC_RES_Q_665___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_665___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_665___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_666 (0x005ECA68) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_666___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_666___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_666__RX_DCOC_RANGE_666___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_666__RX_DCOC_RES_I_666___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_666__RX_DCOC_RES_Q_666___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_666__RX_DCOC_RANGE_666___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_666__RX_DCOC_RANGE_666___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_666__RX_DCOC_RES_I_666___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_666__RX_DCOC_RES_I_666___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_666__RX_DCOC_RES_Q_666___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_666__RX_DCOC_RES_Q_666___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_666___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_666___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_667 (0x005ECA6C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_667___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_667___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_667__RX_DCOC_RANGE_667___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_667__RX_DCOC_RES_I_667___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_667__RX_DCOC_RES_Q_667___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_667__RX_DCOC_RANGE_667___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_667__RX_DCOC_RANGE_667___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_667__RX_DCOC_RES_I_667___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_667__RX_DCOC_RES_I_667___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_667__RX_DCOC_RES_Q_667___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_667__RX_DCOC_RES_Q_667___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_667___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_667___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_668 (0x005ECA70) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_668___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_668___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_668__RX_DCOC_RANGE_668___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_668__RX_DCOC_RES_I_668___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_668__RX_DCOC_RES_Q_668___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_668__RX_DCOC_RANGE_668___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_668__RX_DCOC_RANGE_668___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_668__RX_DCOC_RES_I_668___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_668__RX_DCOC_RES_I_668___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_668__RX_DCOC_RES_Q_668___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_668__RX_DCOC_RES_Q_668___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_668___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_668___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_669 (0x005ECA74) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_669___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_669___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_669__RX_DCOC_RANGE_669___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_669__RX_DCOC_RES_I_669___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_669__RX_DCOC_RES_Q_669___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_669__RX_DCOC_RANGE_669___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_669__RX_DCOC_RANGE_669___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_669__RX_DCOC_RES_I_669___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_669__RX_DCOC_RES_I_669___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_669__RX_DCOC_RES_Q_669___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_669__RX_DCOC_RES_Q_669___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_669___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_669___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_670 (0x005ECA78) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_670___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_670___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_670__RX_DCOC_RANGE_670___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_670__RX_DCOC_RES_I_670___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_670__RX_DCOC_RES_Q_670___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_670__RX_DCOC_RANGE_670___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_670__RX_DCOC_RANGE_670___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_670__RX_DCOC_RES_I_670___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_670__RX_DCOC_RES_I_670___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_670__RX_DCOC_RES_Q_670___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_670__RX_DCOC_RES_Q_670___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_670___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_670___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_671 (0x005ECA7C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_671___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_671___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_671__RX_DCOC_RANGE_671___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_671__RX_DCOC_RES_I_671___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_671__RX_DCOC_RES_Q_671___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_671__RX_DCOC_RANGE_671___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_671__RX_DCOC_RANGE_671___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_671__RX_DCOC_RES_I_671___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_671__RX_DCOC_RES_I_671___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_671__RX_DCOC_RES_Q_671___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_671__RX_DCOC_RES_Q_671___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_671___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_671___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_672 (0x005ECA80) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_672___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_672___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_672__RX_DCOC_RANGE_672___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_672__RX_DCOC_RES_I_672___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_672__RX_DCOC_RES_Q_672___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_672__RX_DCOC_RANGE_672___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_672__RX_DCOC_RANGE_672___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_672__RX_DCOC_RES_I_672___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_672__RX_DCOC_RES_I_672___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_672__RX_DCOC_RES_Q_672___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_672__RX_DCOC_RES_Q_672___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_672___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_672___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_673 (0x005ECA84) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_673___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_673___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_673__RX_DCOC_RANGE_673___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_673__RX_DCOC_RES_I_673___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_673__RX_DCOC_RES_Q_673___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_673__RX_DCOC_RANGE_673___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_673__RX_DCOC_RANGE_673___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_673__RX_DCOC_RES_I_673___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_673__RX_DCOC_RES_I_673___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_673__RX_DCOC_RES_Q_673___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_673__RX_DCOC_RES_Q_673___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_673___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_673___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_674 (0x005ECA88) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_674___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_674___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_674__RX_DCOC_RANGE_674___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_674__RX_DCOC_RES_I_674___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_674__RX_DCOC_RES_Q_674___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_674__RX_DCOC_RANGE_674___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_674__RX_DCOC_RANGE_674___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_674__RX_DCOC_RES_I_674___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_674__RX_DCOC_RES_I_674___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_674__RX_DCOC_RES_Q_674___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_674__RX_DCOC_RES_Q_674___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_674___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_674___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_675 (0x005ECA8C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_675___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_675___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_675__RX_DCOC_RANGE_675___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_675__RX_DCOC_RES_I_675___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_675__RX_DCOC_RES_Q_675___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_675__RX_DCOC_RANGE_675___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_675__RX_DCOC_RANGE_675___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_675__RX_DCOC_RES_I_675___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_675__RX_DCOC_RES_I_675___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_675__RX_DCOC_RES_Q_675___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_675__RX_DCOC_RES_Q_675___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_675___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_675___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_676 (0x005ECA90) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_676___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_676___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_676__RX_DCOC_RANGE_676___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_676__RX_DCOC_RES_I_676___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_676__RX_DCOC_RES_Q_676___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_676__RX_DCOC_RANGE_676___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_676__RX_DCOC_RANGE_676___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_676__RX_DCOC_RES_I_676___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_676__RX_DCOC_RES_I_676___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_676__RX_DCOC_RES_Q_676___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_676__RX_DCOC_RES_Q_676___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_676___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_676___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_677 (0x005ECA94) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_677___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_677___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_677__RX_DCOC_RANGE_677___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_677__RX_DCOC_RES_I_677___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_677__RX_DCOC_RES_Q_677___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_677__RX_DCOC_RANGE_677___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_677__RX_DCOC_RANGE_677___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_677__RX_DCOC_RES_I_677___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_677__RX_DCOC_RES_I_677___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_677__RX_DCOC_RES_Q_677___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_677__RX_DCOC_RES_Q_677___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_677___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_677___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_678 (0x005ECA98) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_678___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_678___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_678__RX_DCOC_RANGE_678___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_678__RX_DCOC_RES_I_678___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_678__RX_DCOC_RES_Q_678___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_678__RX_DCOC_RANGE_678___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_678__RX_DCOC_RANGE_678___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_678__RX_DCOC_RES_I_678___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_678__RX_DCOC_RES_I_678___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_678__RX_DCOC_RES_Q_678___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_678__RX_DCOC_RES_Q_678___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_678___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_678___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_679 (0x005ECA9C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_679___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_679___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_679__RX_DCOC_RANGE_679___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_679__RX_DCOC_RES_I_679___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_679__RX_DCOC_RES_Q_679___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_679__RX_DCOC_RANGE_679___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_679__RX_DCOC_RANGE_679___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_679__RX_DCOC_RES_I_679___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_679__RX_DCOC_RES_I_679___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_679__RX_DCOC_RES_Q_679___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_679__RX_DCOC_RES_Q_679___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_679___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_679___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_680 (0x005ECAA0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_680___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_680___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_680__RX_DCOC_RANGE_680___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_680__RX_DCOC_RES_I_680___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_680__RX_DCOC_RES_Q_680___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_680__RX_DCOC_RANGE_680___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_680__RX_DCOC_RANGE_680___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_680__RX_DCOC_RES_I_680___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_680__RX_DCOC_RES_I_680___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_680__RX_DCOC_RES_Q_680___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_680__RX_DCOC_RES_Q_680___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_680___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_680___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_681 (0x005ECAA4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_681___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_681___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_681__RX_DCOC_RANGE_681___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_681__RX_DCOC_RES_I_681___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_681__RX_DCOC_RES_Q_681___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_681__RX_DCOC_RANGE_681___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_681__RX_DCOC_RANGE_681___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_681__RX_DCOC_RES_I_681___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_681__RX_DCOC_RES_I_681___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_681__RX_DCOC_RES_Q_681___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_681__RX_DCOC_RES_Q_681___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_681___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_681___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_682 (0x005ECAA8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_682___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_682___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_682__RX_DCOC_RANGE_682___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_682__RX_DCOC_RES_I_682___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_682__RX_DCOC_RES_Q_682___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_682__RX_DCOC_RANGE_682___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_682__RX_DCOC_RANGE_682___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_682__RX_DCOC_RES_I_682___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_682__RX_DCOC_RES_I_682___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_682__RX_DCOC_RES_Q_682___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_682__RX_DCOC_RES_Q_682___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_682___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_682___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_683 (0x005ECAAC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_683___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_683___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_683__RX_DCOC_RANGE_683___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_683__RX_DCOC_RES_I_683___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_683__RX_DCOC_RES_Q_683___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_683__RX_DCOC_RANGE_683___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_683__RX_DCOC_RANGE_683___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_683__RX_DCOC_RES_I_683___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_683__RX_DCOC_RES_I_683___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_683__RX_DCOC_RES_Q_683___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_683__RX_DCOC_RES_Q_683___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_683___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_683___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_684 (0x005ECAB0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_684___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_684___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_684__RX_DCOC_RANGE_684___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_684__RX_DCOC_RES_I_684___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_684__RX_DCOC_RES_Q_684___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_684__RX_DCOC_RANGE_684___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_684__RX_DCOC_RANGE_684___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_684__RX_DCOC_RES_I_684___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_684__RX_DCOC_RES_I_684___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_684__RX_DCOC_RES_Q_684___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_684__RX_DCOC_RES_Q_684___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_684___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_684___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_685 (0x005ECAB4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_685___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_685___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_685__RX_DCOC_RANGE_685___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_685__RX_DCOC_RES_I_685___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_685__RX_DCOC_RES_Q_685___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_685__RX_DCOC_RANGE_685___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_685__RX_DCOC_RANGE_685___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_685__RX_DCOC_RES_I_685___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_685__RX_DCOC_RES_I_685___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_685__RX_DCOC_RES_Q_685___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_685__RX_DCOC_RES_Q_685___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_685___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_685___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_686 (0x005ECAB8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_686___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_686___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_686__RX_DCOC_RANGE_686___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_686__RX_DCOC_RES_I_686___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_686__RX_DCOC_RES_Q_686___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_686__RX_DCOC_RANGE_686___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_686__RX_DCOC_RANGE_686___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_686__RX_DCOC_RES_I_686___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_686__RX_DCOC_RES_I_686___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_686__RX_DCOC_RES_Q_686___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_686__RX_DCOC_RES_Q_686___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_686___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_686___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_687 (0x005ECABC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_687___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_687___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_687__RX_DCOC_RANGE_687___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_687__RX_DCOC_RES_I_687___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_687__RX_DCOC_RES_Q_687___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_687__RX_DCOC_RANGE_687___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_687__RX_DCOC_RANGE_687___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_687__RX_DCOC_RES_I_687___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_687__RX_DCOC_RES_I_687___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_687__RX_DCOC_RES_Q_687___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_687__RX_DCOC_RES_Q_687___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_687___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_687___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_688 (0x005ECAC0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_688___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_688___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_688__RX_DCOC_RANGE_688___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_688__RX_DCOC_RES_I_688___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_688__RX_DCOC_RES_Q_688___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_688__RX_DCOC_RANGE_688___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_688__RX_DCOC_RANGE_688___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_688__RX_DCOC_RES_I_688___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_688__RX_DCOC_RES_I_688___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_688__RX_DCOC_RES_Q_688___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_688__RX_DCOC_RES_Q_688___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_688___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_688___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_689 (0x005ECAC4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_689___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_689___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_689__RX_DCOC_RANGE_689___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_689__RX_DCOC_RES_I_689___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_689__RX_DCOC_RES_Q_689___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_689__RX_DCOC_RANGE_689___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_689__RX_DCOC_RANGE_689___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_689__RX_DCOC_RES_I_689___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_689__RX_DCOC_RES_I_689___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_689__RX_DCOC_RES_Q_689___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_689__RX_DCOC_RES_Q_689___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_689___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_689___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_690 (0x005ECAC8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_690___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_690___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_690__RX_DCOC_RANGE_690___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_690__RX_DCOC_RES_I_690___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_690__RX_DCOC_RES_Q_690___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_690__RX_DCOC_RANGE_690___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_690__RX_DCOC_RANGE_690___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_690__RX_DCOC_RES_I_690___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_690__RX_DCOC_RES_I_690___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_690__RX_DCOC_RES_Q_690___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_690__RX_DCOC_RES_Q_690___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_690___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_690___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_691 (0x005ECACC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_691___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_691___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_691__RX_DCOC_RANGE_691___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_691__RX_DCOC_RES_I_691___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_691__RX_DCOC_RES_Q_691___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_691__RX_DCOC_RANGE_691___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_691__RX_DCOC_RANGE_691___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_691__RX_DCOC_RES_I_691___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_691__RX_DCOC_RES_I_691___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_691__RX_DCOC_RES_Q_691___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_691__RX_DCOC_RES_Q_691___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_691___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_691___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_692 (0x005ECAD0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_692___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_692___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_692__RX_DCOC_RANGE_692___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_692__RX_DCOC_RES_I_692___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_692__RX_DCOC_RES_Q_692___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_692__RX_DCOC_RANGE_692___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_692__RX_DCOC_RANGE_692___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_692__RX_DCOC_RES_I_692___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_692__RX_DCOC_RES_I_692___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_692__RX_DCOC_RES_Q_692___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_692__RX_DCOC_RES_Q_692___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_692___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_692___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_693 (0x005ECAD4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_693___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_693___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_693__RX_DCOC_RANGE_693___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_693__RX_DCOC_RES_I_693___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_693__RX_DCOC_RES_Q_693___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_693__RX_DCOC_RANGE_693___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_693__RX_DCOC_RANGE_693___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_693__RX_DCOC_RES_I_693___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_693__RX_DCOC_RES_I_693___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_693__RX_DCOC_RES_Q_693___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_693__RX_DCOC_RES_Q_693___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_693___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_693___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_694 (0x005ECAD8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_694___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_694___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_694__RX_DCOC_RANGE_694___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_694__RX_DCOC_RES_I_694___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_694__RX_DCOC_RES_Q_694___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_694__RX_DCOC_RANGE_694___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_694__RX_DCOC_RANGE_694___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_694__RX_DCOC_RES_I_694___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_694__RX_DCOC_RES_I_694___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_694__RX_DCOC_RES_Q_694___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_694__RX_DCOC_RES_Q_694___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_694___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_694___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_695 (0x005ECADC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_695___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_695___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_695__RX_DCOC_RANGE_695___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_695__RX_DCOC_RES_I_695___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_695__RX_DCOC_RES_Q_695___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_695__RX_DCOC_RANGE_695___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_695__RX_DCOC_RANGE_695___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_695__RX_DCOC_RES_I_695___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_695__RX_DCOC_RES_I_695___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_695__RX_DCOC_RES_Q_695___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_695__RX_DCOC_RES_Q_695___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_695___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_695___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_696 (0x005ECAE0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_696___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_696___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_696__RX_DCOC_RANGE_696___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_696__RX_DCOC_RES_I_696___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_696__RX_DCOC_RES_Q_696___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_696__RX_DCOC_RANGE_696___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_696__RX_DCOC_RANGE_696___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_696__RX_DCOC_RES_I_696___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_696__RX_DCOC_RES_I_696___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_696__RX_DCOC_RES_Q_696___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_696__RX_DCOC_RES_Q_696___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_696___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_696___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_697 (0x005ECAE4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_697___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_697___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_697__RX_DCOC_RANGE_697___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_697__RX_DCOC_RES_I_697___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_697__RX_DCOC_RES_Q_697___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_697__RX_DCOC_RANGE_697___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_697__RX_DCOC_RANGE_697___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_697__RX_DCOC_RES_I_697___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_697__RX_DCOC_RES_I_697___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_697__RX_DCOC_RES_Q_697___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_697__RX_DCOC_RES_Q_697___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_697___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_697___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_698 (0x005ECAE8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_698___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_698___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_698__RX_DCOC_RANGE_698___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_698__RX_DCOC_RES_I_698___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_698__RX_DCOC_RES_Q_698___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_698__RX_DCOC_RANGE_698___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_698__RX_DCOC_RANGE_698___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_698__RX_DCOC_RES_I_698___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_698__RX_DCOC_RES_I_698___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_698__RX_DCOC_RES_Q_698___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_698__RX_DCOC_RES_Q_698___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_698___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_698___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_699 (0x005ECAEC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_699___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_699___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_699__RX_DCOC_RANGE_699___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_699__RX_DCOC_RES_I_699___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_699__RX_DCOC_RES_Q_699___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_699__RX_DCOC_RANGE_699___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_699__RX_DCOC_RANGE_699___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_699__RX_DCOC_RES_I_699___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_699__RX_DCOC_RES_I_699___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_699__RX_DCOC_RES_Q_699___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_699__RX_DCOC_RES_Q_699___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_699___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_699___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_700 (0x005ECAF0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_700___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_700___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_700__RX_DCOC_RANGE_700___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_700__RX_DCOC_RES_I_700___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_700__RX_DCOC_RES_Q_700___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_700__RX_DCOC_RANGE_700___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_700__RX_DCOC_RANGE_700___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_700__RX_DCOC_RES_I_700___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_700__RX_DCOC_RES_I_700___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_700__RX_DCOC_RES_Q_700___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_700__RX_DCOC_RES_Q_700___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_700___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_700___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_701 (0x005ECAF4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_701___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_701___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_701__RX_DCOC_RANGE_701___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_701__RX_DCOC_RES_I_701___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_701__RX_DCOC_RES_Q_701___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_701__RX_DCOC_RANGE_701___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_701__RX_DCOC_RANGE_701___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_701__RX_DCOC_RES_I_701___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_701__RX_DCOC_RES_I_701___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_701__RX_DCOC_RES_Q_701___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_701__RX_DCOC_RES_Q_701___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_701___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_701___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_702 (0x005ECAF8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_702___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_702___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_702__RX_DCOC_RANGE_702___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_702__RX_DCOC_RES_I_702___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_702__RX_DCOC_RES_Q_702___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_702__RX_DCOC_RANGE_702___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_702__RX_DCOC_RANGE_702___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_702__RX_DCOC_RES_I_702___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_702__RX_DCOC_RES_I_702___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_702__RX_DCOC_RES_Q_702___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_702__RX_DCOC_RES_Q_702___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_702___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_702___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_703 (0x005ECAFC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_703___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_703___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_703__RX_DCOC_RANGE_703___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_703__RX_DCOC_RES_I_703___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_703__RX_DCOC_RES_Q_703___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_703__RX_DCOC_RANGE_703___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_703__RX_DCOC_RANGE_703___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_703__RX_DCOC_RES_I_703___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_703__RX_DCOC_RES_I_703___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_703__RX_DCOC_RES_Q_703___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_703__RX_DCOC_RES_Q_703___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_703___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_703___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_704 (0x005ECB00) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_704___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_704___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_704__RX_DCOC_RANGE_704___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_704__RX_DCOC_RES_I_704___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_704__RX_DCOC_RES_Q_704___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_704__RX_DCOC_RANGE_704___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_704__RX_DCOC_RANGE_704___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_704__RX_DCOC_RES_I_704___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_704__RX_DCOC_RES_I_704___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_704__RX_DCOC_RES_Q_704___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_704__RX_DCOC_RES_Q_704___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_704___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_704___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_705 (0x005ECB04) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_705___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_705___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_705__RX_DCOC_RANGE_705___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_705__RX_DCOC_RES_I_705___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_705__RX_DCOC_RES_Q_705___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_705__RX_DCOC_RANGE_705___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_705__RX_DCOC_RANGE_705___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_705__RX_DCOC_RES_I_705___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_705__RX_DCOC_RES_I_705___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_705__RX_DCOC_RES_Q_705___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_705__RX_DCOC_RES_Q_705___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_705___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_705___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_706 (0x005ECB08) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_706___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_706___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_706__RX_DCOC_RANGE_706___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_706__RX_DCOC_RES_I_706___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_706__RX_DCOC_RES_Q_706___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_706__RX_DCOC_RANGE_706___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_706__RX_DCOC_RANGE_706___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_706__RX_DCOC_RES_I_706___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_706__RX_DCOC_RES_I_706___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_706__RX_DCOC_RES_Q_706___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_706__RX_DCOC_RES_Q_706___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_706___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_706___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_707 (0x005ECB0C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_707___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_707___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_707__RX_DCOC_RANGE_707___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_707__RX_DCOC_RES_I_707___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_707__RX_DCOC_RES_Q_707___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_707__RX_DCOC_RANGE_707___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_707__RX_DCOC_RANGE_707___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_707__RX_DCOC_RES_I_707___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_707__RX_DCOC_RES_I_707___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_707__RX_DCOC_RES_Q_707___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_707__RX_DCOC_RES_Q_707___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_707___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_707___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_708 (0x005ECB10) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_708___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_708___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_708__RX_DCOC_RANGE_708___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_708__RX_DCOC_RES_I_708___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_708__RX_DCOC_RES_Q_708___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_708__RX_DCOC_RANGE_708___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_708__RX_DCOC_RANGE_708___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_708__RX_DCOC_RES_I_708___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_708__RX_DCOC_RES_I_708___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_708__RX_DCOC_RES_Q_708___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_708__RX_DCOC_RES_Q_708___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_708___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_708___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_709 (0x005ECB14) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_709___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_709___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_709__RX_DCOC_RANGE_709___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_709__RX_DCOC_RES_I_709___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_709__RX_DCOC_RES_Q_709___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_709__RX_DCOC_RANGE_709___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_709__RX_DCOC_RANGE_709___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_709__RX_DCOC_RES_I_709___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_709__RX_DCOC_RES_I_709___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_709__RX_DCOC_RES_Q_709___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_709__RX_DCOC_RES_Q_709___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_709___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_709___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_710 (0x005ECB18) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_710___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_710___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_710__RX_DCOC_RANGE_710___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_710__RX_DCOC_RES_I_710___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_710__RX_DCOC_RES_Q_710___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_710__RX_DCOC_RANGE_710___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_710__RX_DCOC_RANGE_710___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_710__RX_DCOC_RES_I_710___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_710__RX_DCOC_RES_I_710___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_710__RX_DCOC_RES_Q_710___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_710__RX_DCOC_RES_Q_710___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_710___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_710___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_711 (0x005ECB1C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_711___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_711___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_711__RX_DCOC_RANGE_711___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_711__RX_DCOC_RES_I_711___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_711__RX_DCOC_RES_Q_711___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_711__RX_DCOC_RANGE_711___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_711__RX_DCOC_RANGE_711___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_711__RX_DCOC_RES_I_711___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_711__RX_DCOC_RES_I_711___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_711__RX_DCOC_RES_Q_711___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_711__RX_DCOC_RES_Q_711___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_711___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_711___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_712 (0x005ECB20) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_712___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_712___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_712__RX_DCOC_RANGE_712___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_712__RX_DCOC_RES_I_712___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_712__RX_DCOC_RES_Q_712___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_712__RX_DCOC_RANGE_712___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_712__RX_DCOC_RANGE_712___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_712__RX_DCOC_RES_I_712___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_712__RX_DCOC_RES_I_712___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_712__RX_DCOC_RES_Q_712___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_712__RX_DCOC_RES_Q_712___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_712___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_712___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_713 (0x005ECB24) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_713___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_713___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_713__RX_DCOC_RANGE_713___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_713__RX_DCOC_RES_I_713___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_713__RX_DCOC_RES_Q_713___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_713__RX_DCOC_RANGE_713___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_713__RX_DCOC_RANGE_713___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_713__RX_DCOC_RES_I_713___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_713__RX_DCOC_RES_I_713___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_713__RX_DCOC_RES_Q_713___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_713__RX_DCOC_RES_Q_713___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_713___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_713___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_714 (0x005ECB28) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_714___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_714___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_714__RX_DCOC_RANGE_714___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_714__RX_DCOC_RES_I_714___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_714__RX_DCOC_RES_Q_714___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_714__RX_DCOC_RANGE_714___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_714__RX_DCOC_RANGE_714___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_714__RX_DCOC_RES_I_714___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_714__RX_DCOC_RES_I_714___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_714__RX_DCOC_RES_Q_714___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_714__RX_DCOC_RES_Q_714___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_714___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_714___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_715 (0x005ECB2C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_715___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_715___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_715__RX_DCOC_RANGE_715___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_715__RX_DCOC_RES_I_715___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_715__RX_DCOC_RES_Q_715___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_715__RX_DCOC_RANGE_715___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_715__RX_DCOC_RANGE_715___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_715__RX_DCOC_RES_I_715___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_715__RX_DCOC_RES_I_715___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_715__RX_DCOC_RES_Q_715___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_715__RX_DCOC_RES_Q_715___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_715___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_715___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_716 (0x005ECB30) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_716___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_716___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_716__RX_DCOC_RANGE_716___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_716__RX_DCOC_RES_I_716___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_716__RX_DCOC_RES_Q_716___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_716__RX_DCOC_RANGE_716___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_716__RX_DCOC_RANGE_716___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_716__RX_DCOC_RES_I_716___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_716__RX_DCOC_RES_I_716___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_716__RX_DCOC_RES_Q_716___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_716__RX_DCOC_RES_Q_716___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_716___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_716___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_717 (0x005ECB34) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_717___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_717___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_717__RX_DCOC_RANGE_717___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_717__RX_DCOC_RES_I_717___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_717__RX_DCOC_RES_Q_717___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_717__RX_DCOC_RANGE_717___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_717__RX_DCOC_RANGE_717___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_717__RX_DCOC_RES_I_717___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_717__RX_DCOC_RES_I_717___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_717__RX_DCOC_RES_Q_717___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_717__RX_DCOC_RES_Q_717___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_717___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_717___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_718 (0x005ECB38) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_718___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_718___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_718__RX_DCOC_RANGE_718___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_718__RX_DCOC_RES_I_718___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_718__RX_DCOC_RES_Q_718___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_718__RX_DCOC_RANGE_718___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_718__RX_DCOC_RANGE_718___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_718__RX_DCOC_RES_I_718___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_718__RX_DCOC_RES_I_718___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_718__RX_DCOC_RES_Q_718___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_718__RX_DCOC_RES_Q_718___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_718___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_718___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_719 (0x005ECB3C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_719___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_719___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_719__RX_DCOC_RANGE_719___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_719__RX_DCOC_RES_I_719___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_719__RX_DCOC_RES_Q_719___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_719__RX_DCOC_RANGE_719___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_719__RX_DCOC_RANGE_719___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_719__RX_DCOC_RES_I_719___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_719__RX_DCOC_RES_I_719___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_719__RX_DCOC_RES_Q_719___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_719__RX_DCOC_RES_Q_719___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_719___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_719___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_720 (0x005ECB40) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_720___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_720___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_720__RX_DCOC_RANGE_720___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_720__RX_DCOC_RES_I_720___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_720__RX_DCOC_RES_Q_720___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_720__RX_DCOC_RANGE_720___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_720__RX_DCOC_RANGE_720___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_720__RX_DCOC_RES_I_720___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_720__RX_DCOC_RES_I_720___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_720__RX_DCOC_RES_Q_720___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_720__RX_DCOC_RES_Q_720___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_720___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_720___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_721 (0x005ECB44) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_721___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_721___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_721__RX_DCOC_RANGE_721___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_721__RX_DCOC_RES_I_721___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_721__RX_DCOC_RES_Q_721___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_721__RX_DCOC_RANGE_721___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_721__RX_DCOC_RANGE_721___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_721__RX_DCOC_RES_I_721___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_721__RX_DCOC_RES_I_721___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_721__RX_DCOC_RES_Q_721___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_721__RX_DCOC_RES_Q_721___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_721___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_721___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_722 (0x005ECB48) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_722___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_722___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_722__RX_DCOC_RANGE_722___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_722__RX_DCOC_RES_I_722___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_722__RX_DCOC_RES_Q_722___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_722__RX_DCOC_RANGE_722___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_722__RX_DCOC_RANGE_722___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_722__RX_DCOC_RES_I_722___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_722__RX_DCOC_RES_I_722___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_722__RX_DCOC_RES_Q_722___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_722__RX_DCOC_RES_Q_722___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_722___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_722___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_723 (0x005ECB4C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_723___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_723___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_723__RX_DCOC_RANGE_723___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_723__RX_DCOC_RES_I_723___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_723__RX_DCOC_RES_Q_723___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_723__RX_DCOC_RANGE_723___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_723__RX_DCOC_RANGE_723___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_723__RX_DCOC_RES_I_723___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_723__RX_DCOC_RES_I_723___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_723__RX_DCOC_RES_Q_723___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_723__RX_DCOC_RES_Q_723___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_723___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_723___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_724 (0x005ECB50) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_724___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_724___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_724__RX_DCOC_RANGE_724___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_724__RX_DCOC_RES_I_724___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_724__RX_DCOC_RES_Q_724___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_724__RX_DCOC_RANGE_724___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_724__RX_DCOC_RANGE_724___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_724__RX_DCOC_RES_I_724___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_724__RX_DCOC_RES_I_724___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_724__RX_DCOC_RES_Q_724___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_724__RX_DCOC_RES_Q_724___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_724___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_724___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_725 (0x005ECB54) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_725___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_725___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_725__RX_DCOC_RANGE_725___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_725__RX_DCOC_RES_I_725___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_725__RX_DCOC_RES_Q_725___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_725__RX_DCOC_RANGE_725___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_725__RX_DCOC_RANGE_725___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_725__RX_DCOC_RES_I_725___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_725__RX_DCOC_RES_I_725___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_725__RX_DCOC_RES_Q_725___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_725__RX_DCOC_RES_Q_725___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_725___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_725___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_726 (0x005ECB58) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_726___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_726___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_726__RX_DCOC_RANGE_726___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_726__RX_DCOC_RES_I_726___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_726__RX_DCOC_RES_Q_726___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_726__RX_DCOC_RANGE_726___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_726__RX_DCOC_RANGE_726___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_726__RX_DCOC_RES_I_726___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_726__RX_DCOC_RES_I_726___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_726__RX_DCOC_RES_Q_726___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_726__RX_DCOC_RES_Q_726___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_726___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_726___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_727 (0x005ECB5C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_727___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_727___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_727__RX_DCOC_RANGE_727___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_727__RX_DCOC_RES_I_727___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_727__RX_DCOC_RES_Q_727___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_727__RX_DCOC_RANGE_727___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_727__RX_DCOC_RANGE_727___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_727__RX_DCOC_RES_I_727___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_727__RX_DCOC_RES_I_727___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_727__RX_DCOC_RES_Q_727___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_727__RX_DCOC_RES_Q_727___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_727___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_727___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_728 (0x005ECB60) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_728___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_728___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_728__RX_DCOC_RANGE_728___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_728__RX_DCOC_RES_I_728___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_728__RX_DCOC_RES_Q_728___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_728__RX_DCOC_RANGE_728___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_728__RX_DCOC_RANGE_728___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_728__RX_DCOC_RES_I_728___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_728__RX_DCOC_RES_I_728___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_728__RX_DCOC_RES_Q_728___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_728__RX_DCOC_RES_Q_728___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_728___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_728___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_729 (0x005ECB64) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_729___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_729___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_729__RX_DCOC_RANGE_729___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_729__RX_DCOC_RES_I_729___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_729__RX_DCOC_RES_Q_729___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_729__RX_DCOC_RANGE_729___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_729__RX_DCOC_RANGE_729___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_729__RX_DCOC_RES_I_729___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_729__RX_DCOC_RES_I_729___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_729__RX_DCOC_RES_Q_729___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_729__RX_DCOC_RES_Q_729___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_729___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_729___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_730 (0x005ECB68) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_730___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_730___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_730__RX_DCOC_RANGE_730___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_730__RX_DCOC_RES_I_730___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_730__RX_DCOC_RES_Q_730___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_730__RX_DCOC_RANGE_730___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_730__RX_DCOC_RANGE_730___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_730__RX_DCOC_RES_I_730___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_730__RX_DCOC_RES_I_730___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_730__RX_DCOC_RES_Q_730___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_730__RX_DCOC_RES_Q_730___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_730___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_730___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_731 (0x005ECB6C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_731___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_731___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_731__RX_DCOC_RANGE_731___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_731__RX_DCOC_RES_I_731___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_731__RX_DCOC_RES_Q_731___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_731__RX_DCOC_RANGE_731___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_731__RX_DCOC_RANGE_731___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_731__RX_DCOC_RES_I_731___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_731__RX_DCOC_RES_I_731___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_731__RX_DCOC_RES_Q_731___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_731__RX_DCOC_RES_Q_731___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_731___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_731___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_732 (0x005ECB70) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_732___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_732___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_732__RX_DCOC_RANGE_732___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_732__RX_DCOC_RES_I_732___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_732__RX_DCOC_RES_Q_732___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_732__RX_DCOC_RANGE_732___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_732__RX_DCOC_RANGE_732___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_732__RX_DCOC_RES_I_732___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_732__RX_DCOC_RES_I_732___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_732__RX_DCOC_RES_Q_732___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_732__RX_DCOC_RES_Q_732___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_732___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_732___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_733 (0x005ECB74) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_733___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_733___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_733__RX_DCOC_RANGE_733___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_733__RX_DCOC_RES_I_733___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_733__RX_DCOC_RES_Q_733___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_733__RX_DCOC_RANGE_733___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_733__RX_DCOC_RANGE_733___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_733__RX_DCOC_RES_I_733___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_733__RX_DCOC_RES_I_733___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_733__RX_DCOC_RES_Q_733___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_733__RX_DCOC_RES_Q_733___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_733___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_733___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_734 (0x005ECB78) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_734___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_734___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_734__RX_DCOC_RANGE_734___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_734__RX_DCOC_RES_I_734___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_734__RX_DCOC_RES_Q_734___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_734__RX_DCOC_RANGE_734___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_734__RX_DCOC_RANGE_734___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_734__RX_DCOC_RES_I_734___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_734__RX_DCOC_RES_I_734___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_734__RX_DCOC_RES_Q_734___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_734__RX_DCOC_RES_Q_734___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_734___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_734___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_735 (0x005ECB7C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_735___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_735___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_735__RX_DCOC_RANGE_735___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_735__RX_DCOC_RES_I_735___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_735__RX_DCOC_RES_Q_735___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_735__RX_DCOC_RANGE_735___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_735__RX_DCOC_RANGE_735___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_735__RX_DCOC_RES_I_735___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_735__RX_DCOC_RES_I_735___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_735__RX_DCOC_RES_Q_735___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_735__RX_DCOC_RES_Q_735___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_735___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_735___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_736 (0x005ECB80) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_736___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_736___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_736__RX_DCOC_RANGE_736___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_736__RX_DCOC_RES_I_736___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_736__RX_DCOC_RES_Q_736___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_736__RX_DCOC_RANGE_736___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_736__RX_DCOC_RANGE_736___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_736__RX_DCOC_RES_I_736___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_736__RX_DCOC_RES_I_736___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_736__RX_DCOC_RES_Q_736___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_736__RX_DCOC_RES_Q_736___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_736___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_736___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_737 (0x005ECB84) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_737___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_737___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_737__RX_DCOC_RANGE_737___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_737__RX_DCOC_RES_I_737___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_737__RX_DCOC_RES_Q_737___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_737__RX_DCOC_RANGE_737___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_737__RX_DCOC_RANGE_737___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_737__RX_DCOC_RES_I_737___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_737__RX_DCOC_RES_I_737___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_737__RX_DCOC_RES_Q_737___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_737__RX_DCOC_RES_Q_737___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_737___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_737___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_738 (0x005ECB88) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_738___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_738___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_738__RX_DCOC_RANGE_738___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_738__RX_DCOC_RES_I_738___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_738__RX_DCOC_RES_Q_738___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_738__RX_DCOC_RANGE_738___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_738__RX_DCOC_RANGE_738___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_738__RX_DCOC_RES_I_738___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_738__RX_DCOC_RES_I_738___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_738__RX_DCOC_RES_Q_738___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_738__RX_DCOC_RES_Q_738___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_738___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_738___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_739 (0x005ECB8C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_739___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_739___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_739__RX_DCOC_RANGE_739___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_739__RX_DCOC_RES_I_739___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_739__RX_DCOC_RES_Q_739___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_739__RX_DCOC_RANGE_739___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_739__RX_DCOC_RANGE_739___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_739__RX_DCOC_RES_I_739___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_739__RX_DCOC_RES_I_739___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_739__RX_DCOC_RES_Q_739___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_739__RX_DCOC_RES_Q_739___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_739___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_739___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_740 (0x005ECB90) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_740___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_740___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_740__RX_DCOC_RANGE_740___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_740__RX_DCOC_RES_I_740___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_740__RX_DCOC_RES_Q_740___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_740__RX_DCOC_RANGE_740___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_740__RX_DCOC_RANGE_740___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_740__RX_DCOC_RES_I_740___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_740__RX_DCOC_RES_I_740___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_740__RX_DCOC_RES_Q_740___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_740__RX_DCOC_RES_Q_740___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_740___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_740___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_741 (0x005ECB94) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_741___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_741___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_741__RX_DCOC_RANGE_741___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_741__RX_DCOC_RES_I_741___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_741__RX_DCOC_RES_Q_741___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_741__RX_DCOC_RANGE_741___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_741__RX_DCOC_RANGE_741___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_741__RX_DCOC_RES_I_741___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_741__RX_DCOC_RES_I_741___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_741__RX_DCOC_RES_Q_741___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_741__RX_DCOC_RES_Q_741___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_741___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_741___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_742 (0x005ECB98) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_742___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_742___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_742__RX_DCOC_RANGE_742___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_742__RX_DCOC_RES_I_742___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_742__RX_DCOC_RES_Q_742___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_742__RX_DCOC_RANGE_742___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_742__RX_DCOC_RANGE_742___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_742__RX_DCOC_RES_I_742___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_742__RX_DCOC_RES_I_742___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_742__RX_DCOC_RES_Q_742___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_742__RX_DCOC_RES_Q_742___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_742___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_742___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_743 (0x005ECB9C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_743___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_743___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_743__RX_DCOC_RANGE_743___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_743__RX_DCOC_RES_I_743___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_743__RX_DCOC_RES_Q_743___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_743__RX_DCOC_RANGE_743___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_743__RX_DCOC_RANGE_743___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_743__RX_DCOC_RES_I_743___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_743__RX_DCOC_RES_I_743___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_743__RX_DCOC_RES_Q_743___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_743__RX_DCOC_RES_Q_743___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_743___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_743___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_744 (0x005ECBA0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_744___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_744___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_744__RX_DCOC_RANGE_744___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_744__RX_DCOC_RES_I_744___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_744__RX_DCOC_RES_Q_744___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_744__RX_DCOC_RANGE_744___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_744__RX_DCOC_RANGE_744___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_744__RX_DCOC_RES_I_744___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_744__RX_DCOC_RES_I_744___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_744__RX_DCOC_RES_Q_744___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_744__RX_DCOC_RES_Q_744___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_744___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_744___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_745 (0x005ECBA4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_745___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_745___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_745__RX_DCOC_RANGE_745___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_745__RX_DCOC_RES_I_745___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_745__RX_DCOC_RES_Q_745___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_745__RX_DCOC_RANGE_745___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_745__RX_DCOC_RANGE_745___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_745__RX_DCOC_RES_I_745___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_745__RX_DCOC_RES_I_745___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_745__RX_DCOC_RES_Q_745___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_745__RX_DCOC_RES_Q_745___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_745___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_745___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_746 (0x005ECBA8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_746___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_746___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_746__RX_DCOC_RANGE_746___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_746__RX_DCOC_RES_I_746___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_746__RX_DCOC_RES_Q_746___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_746__RX_DCOC_RANGE_746___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_746__RX_DCOC_RANGE_746___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_746__RX_DCOC_RES_I_746___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_746__RX_DCOC_RES_I_746___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_746__RX_DCOC_RES_Q_746___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_746__RX_DCOC_RES_Q_746___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_746___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_746___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_747 (0x005ECBAC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_747___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_747___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_747__RX_DCOC_RANGE_747___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_747__RX_DCOC_RES_I_747___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_747__RX_DCOC_RES_Q_747___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_747__RX_DCOC_RANGE_747___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_747__RX_DCOC_RANGE_747___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_747__RX_DCOC_RES_I_747___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_747__RX_DCOC_RES_I_747___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_747__RX_DCOC_RES_Q_747___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_747__RX_DCOC_RES_Q_747___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_747___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_747___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_748 (0x005ECBB0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_748___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_748___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_748__RX_DCOC_RANGE_748___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_748__RX_DCOC_RES_I_748___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_748__RX_DCOC_RES_Q_748___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_748__RX_DCOC_RANGE_748___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_748__RX_DCOC_RANGE_748___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_748__RX_DCOC_RES_I_748___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_748__RX_DCOC_RES_I_748___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_748__RX_DCOC_RES_Q_748___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_748__RX_DCOC_RES_Q_748___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_748___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_748___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_749 (0x005ECBB4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_749___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_749___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_749__RX_DCOC_RANGE_749___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_749__RX_DCOC_RES_I_749___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_749__RX_DCOC_RES_Q_749___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_749__RX_DCOC_RANGE_749___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_749__RX_DCOC_RANGE_749___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_749__RX_DCOC_RES_I_749___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_749__RX_DCOC_RES_I_749___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_749__RX_DCOC_RES_Q_749___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_749__RX_DCOC_RES_Q_749___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_749___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_749___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_750 (0x005ECBB8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_750___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_750___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_750__RX_DCOC_RANGE_750___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_750__RX_DCOC_RES_I_750___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_750__RX_DCOC_RES_Q_750___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_750__RX_DCOC_RANGE_750___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_750__RX_DCOC_RANGE_750___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_750__RX_DCOC_RES_I_750___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_750__RX_DCOC_RES_I_750___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_750__RX_DCOC_RES_Q_750___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_750__RX_DCOC_RES_Q_750___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_750___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_750___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_751 (0x005ECBBC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_751___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_751___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_751__RX_DCOC_RANGE_751___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_751__RX_DCOC_RES_I_751___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_751__RX_DCOC_RES_Q_751___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_751__RX_DCOC_RANGE_751___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_751__RX_DCOC_RANGE_751___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_751__RX_DCOC_RES_I_751___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_751__RX_DCOC_RES_I_751___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_751__RX_DCOC_RES_Q_751___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_751__RX_DCOC_RES_Q_751___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_751___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_751___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_752 (0x005ECBC0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_752___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_752___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_752__RX_DCOC_RANGE_752___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_752__RX_DCOC_RES_I_752___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_752__RX_DCOC_RES_Q_752___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_752__RX_DCOC_RANGE_752___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_752__RX_DCOC_RANGE_752___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_752__RX_DCOC_RES_I_752___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_752__RX_DCOC_RES_I_752___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_752__RX_DCOC_RES_Q_752___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_752__RX_DCOC_RES_Q_752___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_752___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_752___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_753 (0x005ECBC4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_753___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_753___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_753__RX_DCOC_RANGE_753___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_753__RX_DCOC_RES_I_753___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_753__RX_DCOC_RES_Q_753___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_753__RX_DCOC_RANGE_753___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_753__RX_DCOC_RANGE_753___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_753__RX_DCOC_RES_I_753___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_753__RX_DCOC_RES_I_753___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_753__RX_DCOC_RES_Q_753___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_753__RX_DCOC_RES_Q_753___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_753___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_753___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_754 (0x005ECBC8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_754___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_754___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_754__RX_DCOC_RANGE_754___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_754__RX_DCOC_RES_I_754___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_754__RX_DCOC_RES_Q_754___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_754__RX_DCOC_RANGE_754___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_754__RX_DCOC_RANGE_754___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_754__RX_DCOC_RES_I_754___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_754__RX_DCOC_RES_I_754___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_754__RX_DCOC_RES_Q_754___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_754__RX_DCOC_RES_Q_754___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_754___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_754___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_755 (0x005ECBCC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_755___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_755___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_755__RX_DCOC_RANGE_755___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_755__RX_DCOC_RES_I_755___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_755__RX_DCOC_RES_Q_755___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_755__RX_DCOC_RANGE_755___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_755__RX_DCOC_RANGE_755___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_755__RX_DCOC_RES_I_755___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_755__RX_DCOC_RES_I_755___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_755__RX_DCOC_RES_Q_755___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_755__RX_DCOC_RES_Q_755___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_755___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_755___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_756 (0x005ECBD0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_756___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_756___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_756__RX_DCOC_RANGE_756___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_756__RX_DCOC_RES_I_756___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_756__RX_DCOC_RES_Q_756___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_756__RX_DCOC_RANGE_756___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_756__RX_DCOC_RANGE_756___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_756__RX_DCOC_RES_I_756___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_756__RX_DCOC_RES_I_756___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_756__RX_DCOC_RES_Q_756___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_756__RX_DCOC_RES_Q_756___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_756___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_756___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_757 (0x005ECBD4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_757___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_757___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_757__RX_DCOC_RANGE_757___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_757__RX_DCOC_RES_I_757___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_757__RX_DCOC_RES_Q_757___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_757__RX_DCOC_RANGE_757___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_757__RX_DCOC_RANGE_757___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_757__RX_DCOC_RES_I_757___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_757__RX_DCOC_RES_I_757___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_757__RX_DCOC_RES_Q_757___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_757__RX_DCOC_RES_Q_757___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_757___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_757___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_758 (0x005ECBD8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_758___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_758___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_758__RX_DCOC_RANGE_758___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_758__RX_DCOC_RES_I_758___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_758__RX_DCOC_RES_Q_758___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_758__RX_DCOC_RANGE_758___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_758__RX_DCOC_RANGE_758___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_758__RX_DCOC_RES_I_758___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_758__RX_DCOC_RES_I_758___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_758__RX_DCOC_RES_Q_758___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_758__RX_DCOC_RES_Q_758___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_758___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_758___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_759 (0x005ECBDC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_759___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_759___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_759__RX_DCOC_RANGE_759___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_759__RX_DCOC_RES_I_759___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_759__RX_DCOC_RES_Q_759___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_759__RX_DCOC_RANGE_759___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_759__RX_DCOC_RANGE_759___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_759__RX_DCOC_RES_I_759___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_759__RX_DCOC_RES_I_759___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_759__RX_DCOC_RES_Q_759___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_759__RX_DCOC_RES_Q_759___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_759___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_759___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_760 (0x005ECBE0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_760___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_760___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_760__RX_DCOC_RANGE_760___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_760__RX_DCOC_RES_I_760___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_760__RX_DCOC_RES_Q_760___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_760__RX_DCOC_RANGE_760___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_760__RX_DCOC_RANGE_760___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_760__RX_DCOC_RES_I_760___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_760__RX_DCOC_RES_I_760___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_760__RX_DCOC_RES_Q_760___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_760__RX_DCOC_RES_Q_760___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_760___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_760___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_761 (0x005ECBE4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_761___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_761___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_761__RX_DCOC_RANGE_761___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_761__RX_DCOC_RES_I_761___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_761__RX_DCOC_RES_Q_761___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_761__RX_DCOC_RANGE_761___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_761__RX_DCOC_RANGE_761___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_761__RX_DCOC_RES_I_761___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_761__RX_DCOC_RES_I_761___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_761__RX_DCOC_RES_Q_761___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_761__RX_DCOC_RES_Q_761___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_761___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_761___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_762 (0x005ECBE8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_762___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_762___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_762__RX_DCOC_RANGE_762___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_762__RX_DCOC_RES_I_762___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_762__RX_DCOC_RES_Q_762___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_762__RX_DCOC_RANGE_762___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_762__RX_DCOC_RANGE_762___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_762__RX_DCOC_RES_I_762___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_762__RX_DCOC_RES_I_762___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_762__RX_DCOC_RES_Q_762___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_762__RX_DCOC_RES_Q_762___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_762___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_762___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_763 (0x005ECBEC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_763___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_763___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_763__RX_DCOC_RANGE_763___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_763__RX_DCOC_RES_I_763___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_763__RX_DCOC_RES_Q_763___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_763__RX_DCOC_RANGE_763___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_763__RX_DCOC_RANGE_763___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_763__RX_DCOC_RES_I_763___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_763__RX_DCOC_RES_I_763___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_763__RX_DCOC_RES_Q_763___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_763__RX_DCOC_RES_Q_763___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_763___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_763___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_764 (0x005ECBF0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_764___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_764___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_764__RX_DCOC_RANGE_764___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_764__RX_DCOC_RES_I_764___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_764__RX_DCOC_RES_Q_764___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_764__RX_DCOC_RANGE_764___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_764__RX_DCOC_RANGE_764___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_764__RX_DCOC_RES_I_764___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_764__RX_DCOC_RES_I_764___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_764__RX_DCOC_RES_Q_764___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_764__RX_DCOC_RES_Q_764___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_764___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_764___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_765 (0x005ECBF4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_765___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_765___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_765__RX_DCOC_RANGE_765___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_765__RX_DCOC_RES_I_765___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_765__RX_DCOC_RES_Q_765___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_765__RX_DCOC_RANGE_765___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_765__RX_DCOC_RANGE_765___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_765__RX_DCOC_RES_I_765___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_765__RX_DCOC_RES_I_765___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_765__RX_DCOC_RES_Q_765___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_765__RX_DCOC_RES_Q_765___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_765___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_765___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_766 (0x005ECBF8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_766___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_766___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_766__RX_DCOC_RANGE_766___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_766__RX_DCOC_RES_I_766___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_766__RX_DCOC_RES_Q_766___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_766__RX_DCOC_RANGE_766___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_766__RX_DCOC_RANGE_766___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_766__RX_DCOC_RES_I_766___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_766__RX_DCOC_RES_I_766___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_766__RX_DCOC_RES_Q_766___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_766__RX_DCOC_RES_Q_766___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_766___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_766___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_767 (0x005ECBFC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_767___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_767___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_767__RX_DCOC_RANGE_767___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_767__RX_DCOC_RES_I_767___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_767__RX_DCOC_RES_Q_767___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_767__RX_DCOC_RANGE_767___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_767__RX_DCOC_RANGE_767___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_767__RX_DCOC_RES_I_767___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_767__RX_DCOC_RES_I_767___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_767__RX_DCOC_RES_Q_767___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_767__RX_DCOC_RES_Q_767___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_767___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_767___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_768 (0x005ECC00) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_768___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_768___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_768__RX_DCOC_RANGE_768___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_768__RX_DCOC_RES_I_768___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_768__RX_DCOC_RES_Q_768___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_768__RX_DCOC_RANGE_768___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_768__RX_DCOC_RANGE_768___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_768__RX_DCOC_RES_I_768___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_768__RX_DCOC_RES_I_768___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_768__RX_DCOC_RES_Q_768___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_768__RX_DCOC_RES_Q_768___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_768___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_768___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_769 (0x005ECC04) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_769___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_769___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_769__RX_DCOC_RANGE_769___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_769__RX_DCOC_RES_I_769___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_769__RX_DCOC_RES_Q_769___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_769__RX_DCOC_RANGE_769___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_769__RX_DCOC_RANGE_769___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_769__RX_DCOC_RES_I_769___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_769__RX_DCOC_RES_I_769___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_769__RX_DCOC_RES_Q_769___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_769__RX_DCOC_RES_Q_769___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_769___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_769___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_770 (0x005ECC08) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_770___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_770___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_770__RX_DCOC_RANGE_770___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_770__RX_DCOC_RES_I_770___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_770__RX_DCOC_RES_Q_770___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_770__RX_DCOC_RANGE_770___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_770__RX_DCOC_RANGE_770___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_770__RX_DCOC_RES_I_770___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_770__RX_DCOC_RES_I_770___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_770__RX_DCOC_RES_Q_770___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_770__RX_DCOC_RES_Q_770___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_770___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_770___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_771 (0x005ECC0C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_771___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_771___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_771__RX_DCOC_RANGE_771___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_771__RX_DCOC_RES_I_771___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_771__RX_DCOC_RES_Q_771___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_771__RX_DCOC_RANGE_771___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_771__RX_DCOC_RANGE_771___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_771__RX_DCOC_RES_I_771___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_771__RX_DCOC_RES_I_771___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_771__RX_DCOC_RES_Q_771___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_771__RX_DCOC_RES_Q_771___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_771___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_771___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_772 (0x005ECC10) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_772___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_772___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_772__RX_DCOC_RANGE_772___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_772__RX_DCOC_RES_I_772___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_772__RX_DCOC_RES_Q_772___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_772__RX_DCOC_RANGE_772___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_772__RX_DCOC_RANGE_772___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_772__RX_DCOC_RES_I_772___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_772__RX_DCOC_RES_I_772___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_772__RX_DCOC_RES_Q_772___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_772__RX_DCOC_RES_Q_772___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_772___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_772___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_773 (0x005ECC14) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_773___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_773___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_773__RX_DCOC_RANGE_773___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_773__RX_DCOC_RES_I_773___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_773__RX_DCOC_RES_Q_773___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_773__RX_DCOC_RANGE_773___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_773__RX_DCOC_RANGE_773___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_773__RX_DCOC_RES_I_773___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_773__RX_DCOC_RES_I_773___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_773__RX_DCOC_RES_Q_773___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_773__RX_DCOC_RES_Q_773___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_773___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_773___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_774 (0x005ECC18) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_774___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_774___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_774__RX_DCOC_RANGE_774___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_774__RX_DCOC_RES_I_774___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_774__RX_DCOC_RES_Q_774___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_774__RX_DCOC_RANGE_774___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_774__RX_DCOC_RANGE_774___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_774__RX_DCOC_RES_I_774___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_774__RX_DCOC_RES_I_774___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_774__RX_DCOC_RES_Q_774___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_774__RX_DCOC_RES_Q_774___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_774___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_774___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_775 (0x005ECC1C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_775___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_775___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_775__RX_DCOC_RANGE_775___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_775__RX_DCOC_RES_I_775___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_775__RX_DCOC_RES_Q_775___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_775__RX_DCOC_RANGE_775___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_775__RX_DCOC_RANGE_775___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_775__RX_DCOC_RES_I_775___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_775__RX_DCOC_RES_I_775___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_775__RX_DCOC_RES_Q_775___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_775__RX_DCOC_RES_Q_775___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_775___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_775___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_776 (0x005ECC20) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_776___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_776___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_776__RX_DCOC_RANGE_776___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_776__RX_DCOC_RES_I_776___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_776__RX_DCOC_RES_Q_776___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_776__RX_DCOC_RANGE_776___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_776__RX_DCOC_RANGE_776___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_776__RX_DCOC_RES_I_776___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_776__RX_DCOC_RES_I_776___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_776__RX_DCOC_RES_Q_776___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_776__RX_DCOC_RES_Q_776___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_776___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_776___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_777 (0x005ECC24) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_777___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_777___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_777__RX_DCOC_RANGE_777___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_777__RX_DCOC_RES_I_777___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_777__RX_DCOC_RES_Q_777___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_777__RX_DCOC_RANGE_777___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_777__RX_DCOC_RANGE_777___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_777__RX_DCOC_RES_I_777___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_777__RX_DCOC_RES_I_777___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_777__RX_DCOC_RES_Q_777___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_777__RX_DCOC_RES_Q_777___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_777___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_777___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_778 (0x005ECC28) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_778___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_778___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_778__RX_DCOC_RANGE_778___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_778__RX_DCOC_RES_I_778___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_778__RX_DCOC_RES_Q_778___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_778__RX_DCOC_RANGE_778___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_778__RX_DCOC_RANGE_778___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_778__RX_DCOC_RES_I_778___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_778__RX_DCOC_RES_I_778___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_778__RX_DCOC_RES_Q_778___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_778__RX_DCOC_RES_Q_778___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_778___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_778___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_779 (0x005ECC2C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_779___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_779___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_779__RX_DCOC_RANGE_779___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_779__RX_DCOC_RES_I_779___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_779__RX_DCOC_RES_Q_779___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_779__RX_DCOC_RANGE_779___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_779__RX_DCOC_RANGE_779___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_779__RX_DCOC_RES_I_779___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_779__RX_DCOC_RES_I_779___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_779__RX_DCOC_RES_Q_779___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_779__RX_DCOC_RES_Q_779___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_779___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_779___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_780 (0x005ECC30) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_780___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_780___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_780__RX_DCOC_RANGE_780___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_780__RX_DCOC_RES_I_780___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_780__RX_DCOC_RES_Q_780___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_780__RX_DCOC_RANGE_780___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_780__RX_DCOC_RANGE_780___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_780__RX_DCOC_RES_I_780___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_780__RX_DCOC_RES_I_780___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_780__RX_DCOC_RES_Q_780___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_780__RX_DCOC_RES_Q_780___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_780___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_780___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_781 (0x005ECC34) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_781___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_781___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_781__RX_DCOC_RANGE_781___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_781__RX_DCOC_RES_I_781___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_781__RX_DCOC_RES_Q_781___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_781__RX_DCOC_RANGE_781___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_781__RX_DCOC_RANGE_781___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_781__RX_DCOC_RES_I_781___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_781__RX_DCOC_RES_I_781___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_781__RX_DCOC_RES_Q_781___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_781__RX_DCOC_RES_Q_781___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_781___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_781___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_782 (0x005ECC38) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_782___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_782___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_782__RX_DCOC_RANGE_782___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_782__RX_DCOC_RES_I_782___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_782__RX_DCOC_RES_Q_782___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_782__RX_DCOC_RANGE_782___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_782__RX_DCOC_RANGE_782___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_782__RX_DCOC_RES_I_782___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_782__RX_DCOC_RES_I_782___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_782__RX_DCOC_RES_Q_782___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_782__RX_DCOC_RES_Q_782___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_782___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_782___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_783 (0x005ECC3C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_783___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_783___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_783__RX_DCOC_RANGE_783___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_783__RX_DCOC_RES_I_783___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_783__RX_DCOC_RES_Q_783___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_783__RX_DCOC_RANGE_783___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_783__RX_DCOC_RANGE_783___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_783__RX_DCOC_RES_I_783___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_783__RX_DCOC_RES_I_783___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_783__RX_DCOC_RES_Q_783___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_783__RX_DCOC_RES_Q_783___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_783___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_783___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_784 (0x005ECC40) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_784___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_784___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_784__RX_DCOC_RANGE_784___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_784__RX_DCOC_RES_I_784___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_784__RX_DCOC_RES_Q_784___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_784__RX_DCOC_RANGE_784___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_784__RX_DCOC_RANGE_784___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_784__RX_DCOC_RES_I_784___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_784__RX_DCOC_RES_I_784___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_784__RX_DCOC_RES_Q_784___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_784__RX_DCOC_RES_Q_784___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_784___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_784___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_785 (0x005ECC44) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_785___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_785___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_785__RX_DCOC_RANGE_785___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_785__RX_DCOC_RES_I_785___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_785__RX_DCOC_RES_Q_785___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_785__RX_DCOC_RANGE_785___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_785__RX_DCOC_RANGE_785___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_785__RX_DCOC_RES_I_785___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_785__RX_DCOC_RES_I_785___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_785__RX_DCOC_RES_Q_785___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_785__RX_DCOC_RES_Q_785___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_785___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_785___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_786 (0x005ECC48) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_786___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_786___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_786__RX_DCOC_RANGE_786___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_786__RX_DCOC_RES_I_786___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_786__RX_DCOC_RES_Q_786___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_786__RX_DCOC_RANGE_786___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_786__RX_DCOC_RANGE_786___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_786__RX_DCOC_RES_I_786___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_786__RX_DCOC_RES_I_786___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_786__RX_DCOC_RES_Q_786___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_786__RX_DCOC_RES_Q_786___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_786___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_786___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_787 (0x005ECC4C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_787___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_787___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_787__RX_DCOC_RANGE_787___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_787__RX_DCOC_RES_I_787___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_787__RX_DCOC_RES_Q_787___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_787__RX_DCOC_RANGE_787___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_787__RX_DCOC_RANGE_787___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_787__RX_DCOC_RES_I_787___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_787__RX_DCOC_RES_I_787___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_787__RX_DCOC_RES_Q_787___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_787__RX_DCOC_RES_Q_787___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_787___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_787___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_788 (0x005ECC50) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_788___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_788___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_788__RX_DCOC_RANGE_788___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_788__RX_DCOC_RES_I_788___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_788__RX_DCOC_RES_Q_788___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_788__RX_DCOC_RANGE_788___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_788__RX_DCOC_RANGE_788___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_788__RX_DCOC_RES_I_788___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_788__RX_DCOC_RES_I_788___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_788__RX_DCOC_RES_Q_788___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_788__RX_DCOC_RES_Q_788___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_788___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_788___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_789 (0x005ECC54) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_789___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_789___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_789__RX_DCOC_RANGE_789___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_789__RX_DCOC_RES_I_789___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_789__RX_DCOC_RES_Q_789___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_789__RX_DCOC_RANGE_789___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_789__RX_DCOC_RANGE_789___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_789__RX_DCOC_RES_I_789___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_789__RX_DCOC_RES_I_789___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_789__RX_DCOC_RES_Q_789___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_789__RX_DCOC_RES_Q_789___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_789___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_789___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_790 (0x005ECC58) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_790___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_790___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_790__RX_DCOC_RANGE_790___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_790__RX_DCOC_RES_I_790___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_790__RX_DCOC_RES_Q_790___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_790__RX_DCOC_RANGE_790___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_790__RX_DCOC_RANGE_790___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_790__RX_DCOC_RES_I_790___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_790__RX_DCOC_RES_I_790___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_790__RX_DCOC_RES_Q_790___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_790__RX_DCOC_RES_Q_790___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_790___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_790___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_791 (0x005ECC5C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_791___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_791___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_791__RX_DCOC_RANGE_791___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_791__RX_DCOC_RES_I_791___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_791__RX_DCOC_RES_Q_791___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_791__RX_DCOC_RANGE_791___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_791__RX_DCOC_RANGE_791___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_791__RX_DCOC_RES_I_791___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_791__RX_DCOC_RES_I_791___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_791__RX_DCOC_RES_Q_791___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_791__RX_DCOC_RES_Q_791___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_791___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_791___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_792 (0x005ECC60) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_792___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_792___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_792__RX_DCOC_RANGE_792___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_792__RX_DCOC_RES_I_792___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_792__RX_DCOC_RES_Q_792___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_792__RX_DCOC_RANGE_792___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_792__RX_DCOC_RANGE_792___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_792__RX_DCOC_RES_I_792___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_792__RX_DCOC_RES_I_792___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_792__RX_DCOC_RES_Q_792___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_792__RX_DCOC_RES_Q_792___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_792___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_792___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_793 (0x005ECC64) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_793___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_793___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_793__RX_DCOC_RANGE_793___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_793__RX_DCOC_RES_I_793___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_793__RX_DCOC_RES_Q_793___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_793__RX_DCOC_RANGE_793___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_793__RX_DCOC_RANGE_793___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_793__RX_DCOC_RES_I_793___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_793__RX_DCOC_RES_I_793___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_793__RX_DCOC_RES_Q_793___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_793__RX_DCOC_RES_Q_793___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_793___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_793___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_794 (0x005ECC68) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_794___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_794___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_794__RX_DCOC_RANGE_794___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_794__RX_DCOC_RES_I_794___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_794__RX_DCOC_RES_Q_794___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_794__RX_DCOC_RANGE_794___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_794__RX_DCOC_RANGE_794___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_794__RX_DCOC_RES_I_794___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_794__RX_DCOC_RES_I_794___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_794__RX_DCOC_RES_Q_794___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_794__RX_DCOC_RES_Q_794___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_794___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_794___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_795 (0x005ECC6C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_795___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_795___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_795__RX_DCOC_RANGE_795___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_795__RX_DCOC_RES_I_795___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_795__RX_DCOC_RES_Q_795___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_795__RX_DCOC_RANGE_795___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_795__RX_DCOC_RANGE_795___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_795__RX_DCOC_RES_I_795___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_795__RX_DCOC_RES_I_795___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_795__RX_DCOC_RES_Q_795___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_795__RX_DCOC_RES_Q_795___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_795___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_795___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_796 (0x005ECC70) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_796___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_796___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_796__RX_DCOC_RANGE_796___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_796__RX_DCOC_RES_I_796___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_796__RX_DCOC_RES_Q_796___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_796__RX_DCOC_RANGE_796___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_796__RX_DCOC_RANGE_796___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_796__RX_DCOC_RES_I_796___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_796__RX_DCOC_RES_I_796___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_796__RX_DCOC_RES_Q_796___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_796__RX_DCOC_RES_Q_796___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_796___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_796___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_797 (0x005ECC74) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_797___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_797___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_797__RX_DCOC_RANGE_797___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_797__RX_DCOC_RES_I_797___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_797__RX_DCOC_RES_Q_797___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_797__RX_DCOC_RANGE_797___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_797__RX_DCOC_RANGE_797___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_797__RX_DCOC_RES_I_797___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_797__RX_DCOC_RES_I_797___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_797__RX_DCOC_RES_Q_797___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_797__RX_DCOC_RES_Q_797___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_797___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_797___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_798 (0x005ECC78) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_798___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_798___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_798__RX_DCOC_RANGE_798___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_798__RX_DCOC_RES_I_798___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_798__RX_DCOC_RES_Q_798___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_798__RX_DCOC_RANGE_798___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_798__RX_DCOC_RANGE_798___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_798__RX_DCOC_RES_I_798___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_798__RX_DCOC_RES_I_798___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_798__RX_DCOC_RES_Q_798___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_798__RX_DCOC_RES_Q_798___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_798___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_798___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_799 (0x005ECC7C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_799___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_799___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_799__RX_DCOC_RANGE_799___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_799__RX_DCOC_RES_I_799___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_799__RX_DCOC_RES_Q_799___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_799__RX_DCOC_RANGE_799___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_799__RX_DCOC_RANGE_799___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_799__RX_DCOC_RES_I_799___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_799__RX_DCOC_RES_I_799___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_799__RX_DCOC_RES_Q_799___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_799__RX_DCOC_RES_Q_799___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_799___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_799___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_800 (0x005ECC80) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_800___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_800___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_800__RX_DCOC_RANGE_800___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_800__RX_DCOC_RES_I_800___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_800__RX_DCOC_RES_Q_800___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_800__RX_DCOC_RANGE_800___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_800__RX_DCOC_RANGE_800___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_800__RX_DCOC_RES_I_800___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_800__RX_DCOC_RES_I_800___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_800__RX_DCOC_RES_Q_800___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_800__RX_DCOC_RES_Q_800___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_800___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_800___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_801 (0x005ECC84) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_801___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_801___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_801__RX_DCOC_RANGE_801___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_801__RX_DCOC_RES_I_801___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_801__RX_DCOC_RES_Q_801___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_801__RX_DCOC_RANGE_801___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_801__RX_DCOC_RANGE_801___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_801__RX_DCOC_RES_I_801___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_801__RX_DCOC_RES_I_801___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_801__RX_DCOC_RES_Q_801___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_801__RX_DCOC_RES_Q_801___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_801___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_801___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_802 (0x005ECC88) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_802___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_802___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_802__RX_DCOC_RANGE_802___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_802__RX_DCOC_RES_I_802___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_802__RX_DCOC_RES_Q_802___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_802__RX_DCOC_RANGE_802___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_802__RX_DCOC_RANGE_802___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_802__RX_DCOC_RES_I_802___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_802__RX_DCOC_RES_I_802___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_802__RX_DCOC_RES_Q_802___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_802__RX_DCOC_RES_Q_802___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_802___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_802___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_803 (0x005ECC8C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_803___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_803___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_803__RX_DCOC_RANGE_803___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_803__RX_DCOC_RES_I_803___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_803__RX_DCOC_RES_Q_803___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_803__RX_DCOC_RANGE_803___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_803__RX_DCOC_RANGE_803___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_803__RX_DCOC_RES_I_803___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_803__RX_DCOC_RES_I_803___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_803__RX_DCOC_RES_Q_803___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_803__RX_DCOC_RES_Q_803___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_803___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_803___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_804 (0x005ECC90) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_804___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_804___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_804__RX_DCOC_RANGE_804___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_804__RX_DCOC_RES_I_804___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_804__RX_DCOC_RES_Q_804___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_804__RX_DCOC_RANGE_804___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_804__RX_DCOC_RANGE_804___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_804__RX_DCOC_RES_I_804___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_804__RX_DCOC_RES_I_804___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_804__RX_DCOC_RES_Q_804___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_804__RX_DCOC_RES_Q_804___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_804___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_804___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_805 (0x005ECC94) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_805___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_805___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_805__RX_DCOC_RANGE_805___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_805__RX_DCOC_RES_I_805___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_805__RX_DCOC_RES_Q_805___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_805__RX_DCOC_RANGE_805___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_805__RX_DCOC_RANGE_805___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_805__RX_DCOC_RES_I_805___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_805__RX_DCOC_RES_I_805___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_805__RX_DCOC_RES_Q_805___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_805__RX_DCOC_RES_Q_805___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_805___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_805___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_806 (0x005ECC98) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_806___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_806___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_806__RX_DCOC_RANGE_806___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_806__RX_DCOC_RES_I_806___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_806__RX_DCOC_RES_Q_806___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_806__RX_DCOC_RANGE_806___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_806__RX_DCOC_RANGE_806___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_806__RX_DCOC_RES_I_806___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_806__RX_DCOC_RES_I_806___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_806__RX_DCOC_RES_Q_806___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_806__RX_DCOC_RES_Q_806___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_806___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_806___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_807 (0x005ECC9C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_807___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_807___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_807__RX_DCOC_RANGE_807___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_807__RX_DCOC_RES_I_807___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_807__RX_DCOC_RES_Q_807___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_807__RX_DCOC_RANGE_807___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_807__RX_DCOC_RANGE_807___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_807__RX_DCOC_RES_I_807___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_807__RX_DCOC_RES_I_807___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_807__RX_DCOC_RES_Q_807___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_807__RX_DCOC_RES_Q_807___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_807___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_807___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_808 (0x005ECCA0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_808___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_808___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_808__RX_DCOC_RANGE_808___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_808__RX_DCOC_RES_I_808___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_808__RX_DCOC_RES_Q_808___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_808__RX_DCOC_RANGE_808___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_808__RX_DCOC_RANGE_808___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_808__RX_DCOC_RES_I_808___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_808__RX_DCOC_RES_I_808___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_808__RX_DCOC_RES_Q_808___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_808__RX_DCOC_RES_Q_808___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_808___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_808___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_809 (0x005ECCA4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_809___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_809___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_809__RX_DCOC_RANGE_809___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_809__RX_DCOC_RES_I_809___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_809__RX_DCOC_RES_Q_809___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_809__RX_DCOC_RANGE_809___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_809__RX_DCOC_RANGE_809___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_809__RX_DCOC_RES_I_809___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_809__RX_DCOC_RES_I_809___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_809__RX_DCOC_RES_Q_809___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_809__RX_DCOC_RES_Q_809___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_809___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_809___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_810 (0x005ECCA8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_810___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_810___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_810__RX_DCOC_RANGE_810___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_810__RX_DCOC_RES_I_810___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_810__RX_DCOC_RES_Q_810___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_810__RX_DCOC_RANGE_810___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_810__RX_DCOC_RANGE_810___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_810__RX_DCOC_RES_I_810___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_810__RX_DCOC_RES_I_810___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_810__RX_DCOC_RES_Q_810___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_810__RX_DCOC_RES_Q_810___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_810___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_810___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_811 (0x005ECCAC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_811___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_811___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_811__RX_DCOC_RANGE_811___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_811__RX_DCOC_RES_I_811___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_811__RX_DCOC_RES_Q_811___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_811__RX_DCOC_RANGE_811___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_811__RX_DCOC_RANGE_811___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_811__RX_DCOC_RES_I_811___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_811__RX_DCOC_RES_I_811___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_811__RX_DCOC_RES_Q_811___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_811__RX_DCOC_RES_Q_811___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_811___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_811___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_812 (0x005ECCB0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_812___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_812___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_812__RX_DCOC_RANGE_812___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_812__RX_DCOC_RES_I_812___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_812__RX_DCOC_RES_Q_812___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_812__RX_DCOC_RANGE_812___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_812__RX_DCOC_RANGE_812___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_812__RX_DCOC_RES_I_812___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_812__RX_DCOC_RES_I_812___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_812__RX_DCOC_RES_Q_812___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_812__RX_DCOC_RES_Q_812___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_812___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_812___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_813 (0x005ECCB4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_813___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_813___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_813__RX_DCOC_RANGE_813___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_813__RX_DCOC_RES_I_813___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_813__RX_DCOC_RES_Q_813___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_813__RX_DCOC_RANGE_813___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_813__RX_DCOC_RANGE_813___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_813__RX_DCOC_RES_I_813___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_813__RX_DCOC_RES_I_813___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_813__RX_DCOC_RES_Q_813___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_813__RX_DCOC_RES_Q_813___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_813___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_813___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_814 (0x005ECCB8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_814___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_814___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_814__RX_DCOC_RANGE_814___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_814__RX_DCOC_RES_I_814___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_814__RX_DCOC_RES_Q_814___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_814__RX_DCOC_RANGE_814___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_814__RX_DCOC_RANGE_814___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_814__RX_DCOC_RES_I_814___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_814__RX_DCOC_RES_I_814___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_814__RX_DCOC_RES_Q_814___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_814__RX_DCOC_RES_Q_814___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_814___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_814___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_815 (0x005ECCBC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_815___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_815___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_815__RX_DCOC_RANGE_815___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_815__RX_DCOC_RES_I_815___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_815__RX_DCOC_RES_Q_815___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_815__RX_DCOC_RANGE_815___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_815__RX_DCOC_RANGE_815___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_815__RX_DCOC_RES_I_815___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_815__RX_DCOC_RES_I_815___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_815__RX_DCOC_RES_Q_815___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_815__RX_DCOC_RES_Q_815___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_815___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_815___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_816 (0x005ECCC0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_816___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_816___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_816__RX_DCOC_RANGE_816___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_816__RX_DCOC_RES_I_816___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_816__RX_DCOC_RES_Q_816___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_816__RX_DCOC_RANGE_816___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_816__RX_DCOC_RANGE_816___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_816__RX_DCOC_RES_I_816___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_816__RX_DCOC_RES_I_816___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_816__RX_DCOC_RES_Q_816___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_816__RX_DCOC_RES_Q_816___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_816___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_816___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_817 (0x005ECCC4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_817___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_817___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_817__RX_DCOC_RANGE_817___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_817__RX_DCOC_RES_I_817___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_817__RX_DCOC_RES_Q_817___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_817__RX_DCOC_RANGE_817___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_817__RX_DCOC_RANGE_817___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_817__RX_DCOC_RES_I_817___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_817__RX_DCOC_RES_I_817___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_817__RX_DCOC_RES_Q_817___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_817__RX_DCOC_RES_Q_817___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_817___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_817___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_818 (0x005ECCC8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_818___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_818___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_818__RX_DCOC_RANGE_818___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_818__RX_DCOC_RES_I_818___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_818__RX_DCOC_RES_Q_818___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_818__RX_DCOC_RANGE_818___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_818__RX_DCOC_RANGE_818___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_818__RX_DCOC_RES_I_818___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_818__RX_DCOC_RES_I_818___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_818__RX_DCOC_RES_Q_818___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_818__RX_DCOC_RES_Q_818___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_818___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_818___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_819 (0x005ECCCC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_819___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_819___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_819__RX_DCOC_RANGE_819___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_819__RX_DCOC_RES_I_819___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_819__RX_DCOC_RES_Q_819___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_819__RX_DCOC_RANGE_819___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_819__RX_DCOC_RANGE_819___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_819__RX_DCOC_RES_I_819___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_819__RX_DCOC_RES_I_819___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_819__RX_DCOC_RES_Q_819___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_819__RX_DCOC_RES_Q_819___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_819___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_819___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_820 (0x005ECCD0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_820___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_820___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_820__RX_DCOC_RANGE_820___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_820__RX_DCOC_RES_I_820___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_820__RX_DCOC_RES_Q_820___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_820__RX_DCOC_RANGE_820___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_820__RX_DCOC_RANGE_820___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_820__RX_DCOC_RES_I_820___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_820__RX_DCOC_RES_I_820___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_820__RX_DCOC_RES_Q_820___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_820__RX_DCOC_RES_Q_820___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_820___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_820___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_821 (0x005ECCD4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_821___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_821___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_821__RX_DCOC_RANGE_821___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_821__RX_DCOC_RES_I_821___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_821__RX_DCOC_RES_Q_821___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_821__RX_DCOC_RANGE_821___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_821__RX_DCOC_RANGE_821___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_821__RX_DCOC_RES_I_821___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_821__RX_DCOC_RES_I_821___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_821__RX_DCOC_RES_Q_821___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_821__RX_DCOC_RES_Q_821___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_821___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_821___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_822 (0x005ECCD8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_822___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_822___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_822__RX_DCOC_RANGE_822___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_822__RX_DCOC_RES_I_822___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_822__RX_DCOC_RES_Q_822___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_822__RX_DCOC_RANGE_822___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_822__RX_DCOC_RANGE_822___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_822__RX_DCOC_RES_I_822___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_822__RX_DCOC_RES_I_822___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_822__RX_DCOC_RES_Q_822___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_822__RX_DCOC_RES_Q_822___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_822___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_822___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_823 (0x005ECCDC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_823___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_823___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_823__RX_DCOC_RANGE_823___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_823__RX_DCOC_RES_I_823___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_823__RX_DCOC_RES_Q_823___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_823__RX_DCOC_RANGE_823___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_823__RX_DCOC_RANGE_823___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_823__RX_DCOC_RES_I_823___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_823__RX_DCOC_RES_I_823___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_823__RX_DCOC_RES_Q_823___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_823__RX_DCOC_RES_Q_823___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_823___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_823___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_824 (0x005ECCE0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_824___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_824___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_824__RX_DCOC_RANGE_824___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_824__RX_DCOC_RES_I_824___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_824__RX_DCOC_RES_Q_824___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_824__RX_DCOC_RANGE_824___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_824__RX_DCOC_RANGE_824___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_824__RX_DCOC_RES_I_824___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_824__RX_DCOC_RES_I_824___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_824__RX_DCOC_RES_Q_824___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_824__RX_DCOC_RES_Q_824___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_824___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_824___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_825 (0x005ECCE4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_825___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_825___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_825__RX_DCOC_RANGE_825___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_825__RX_DCOC_RES_I_825___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_825__RX_DCOC_RES_Q_825___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_825__RX_DCOC_RANGE_825___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_825__RX_DCOC_RANGE_825___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_825__RX_DCOC_RES_I_825___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_825__RX_DCOC_RES_I_825___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_825__RX_DCOC_RES_Q_825___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_825__RX_DCOC_RES_Q_825___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_825___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_825___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_826 (0x005ECCE8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_826___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_826___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_826__RX_DCOC_RANGE_826___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_826__RX_DCOC_RES_I_826___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_826__RX_DCOC_RES_Q_826___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_826__RX_DCOC_RANGE_826___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_826__RX_DCOC_RANGE_826___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_826__RX_DCOC_RES_I_826___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_826__RX_DCOC_RES_I_826___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_826__RX_DCOC_RES_Q_826___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_826__RX_DCOC_RES_Q_826___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_826___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_826___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_827 (0x005ECCEC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_827___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_827___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_827__RX_DCOC_RANGE_827___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_827__RX_DCOC_RES_I_827___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_827__RX_DCOC_RES_Q_827___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_827__RX_DCOC_RANGE_827___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_827__RX_DCOC_RANGE_827___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_827__RX_DCOC_RES_I_827___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_827__RX_DCOC_RES_I_827___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_827__RX_DCOC_RES_Q_827___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_827__RX_DCOC_RES_Q_827___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_827___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_827___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_828 (0x005ECCF0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_828___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_828___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_828__RX_DCOC_RANGE_828___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_828__RX_DCOC_RES_I_828___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_828__RX_DCOC_RES_Q_828___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_828__RX_DCOC_RANGE_828___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_828__RX_DCOC_RANGE_828___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_828__RX_DCOC_RES_I_828___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_828__RX_DCOC_RES_I_828___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_828__RX_DCOC_RES_Q_828___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_828__RX_DCOC_RES_Q_828___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_828___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_828___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_829 (0x005ECCF4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_829___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_829___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_829__RX_DCOC_RANGE_829___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_829__RX_DCOC_RES_I_829___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_829__RX_DCOC_RES_Q_829___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_829__RX_DCOC_RANGE_829___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_829__RX_DCOC_RANGE_829___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_829__RX_DCOC_RES_I_829___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_829__RX_DCOC_RES_I_829___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_829__RX_DCOC_RES_Q_829___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_829__RX_DCOC_RES_Q_829___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_829___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_829___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_830 (0x005ECCF8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_830___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_830___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_830__RX_DCOC_RANGE_830___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_830__RX_DCOC_RES_I_830___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_830__RX_DCOC_RES_Q_830___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_830__RX_DCOC_RANGE_830___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_830__RX_DCOC_RANGE_830___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_830__RX_DCOC_RES_I_830___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_830__RX_DCOC_RES_I_830___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_830__RX_DCOC_RES_Q_830___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_830__RX_DCOC_RES_Q_830___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_830___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_830___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_831 (0x005ECCFC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_831___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_831___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_831__RX_DCOC_RANGE_831___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_831__RX_DCOC_RES_I_831___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_831__RX_DCOC_RES_Q_831___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_831__RX_DCOC_RANGE_831___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_831__RX_DCOC_RANGE_831___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_831__RX_DCOC_RES_I_831___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_831__RX_DCOC_RES_I_831___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_831__RX_DCOC_RES_Q_831___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_831__RX_DCOC_RES_Q_831___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_831___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_831___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_832 (0x005ECD00) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_832___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_832___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_832__RX_DCOC_RANGE_832___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_832__RX_DCOC_RES_I_832___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_832__RX_DCOC_RES_Q_832___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_832__RX_DCOC_RANGE_832___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_832__RX_DCOC_RANGE_832___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_832__RX_DCOC_RES_I_832___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_832__RX_DCOC_RES_I_832___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_832__RX_DCOC_RES_Q_832___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_832__RX_DCOC_RES_Q_832___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_832___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_832___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_833 (0x005ECD04) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_833___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_833___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_833__RX_DCOC_RANGE_833___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_833__RX_DCOC_RES_I_833___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_833__RX_DCOC_RES_Q_833___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_833__RX_DCOC_RANGE_833___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_833__RX_DCOC_RANGE_833___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_833__RX_DCOC_RES_I_833___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_833__RX_DCOC_RES_I_833___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_833__RX_DCOC_RES_Q_833___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_833__RX_DCOC_RES_Q_833___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_833___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_833___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_834 (0x005ECD08) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_834___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_834___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_834__RX_DCOC_RANGE_834___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_834__RX_DCOC_RES_I_834___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_834__RX_DCOC_RES_Q_834___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_834__RX_DCOC_RANGE_834___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_834__RX_DCOC_RANGE_834___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_834__RX_DCOC_RES_I_834___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_834__RX_DCOC_RES_I_834___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_834__RX_DCOC_RES_Q_834___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_834__RX_DCOC_RES_Q_834___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_834___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_834___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_835 (0x005ECD0C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_835___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_835___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_835__RX_DCOC_RANGE_835___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_835__RX_DCOC_RES_I_835___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_835__RX_DCOC_RES_Q_835___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_835__RX_DCOC_RANGE_835___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_835__RX_DCOC_RANGE_835___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_835__RX_DCOC_RES_I_835___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_835__RX_DCOC_RES_I_835___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_835__RX_DCOC_RES_Q_835___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_835__RX_DCOC_RES_Q_835___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_835___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_835___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_836 (0x005ECD10) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_836___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_836___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_836__RX_DCOC_RANGE_836___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_836__RX_DCOC_RES_I_836___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_836__RX_DCOC_RES_Q_836___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_836__RX_DCOC_RANGE_836___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_836__RX_DCOC_RANGE_836___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_836__RX_DCOC_RES_I_836___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_836__RX_DCOC_RES_I_836___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_836__RX_DCOC_RES_Q_836___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_836__RX_DCOC_RES_Q_836___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_836___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_836___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_837 (0x005ECD14) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_837___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_837___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_837__RX_DCOC_RANGE_837___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_837__RX_DCOC_RES_I_837___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_837__RX_DCOC_RES_Q_837___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_837__RX_DCOC_RANGE_837___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_837__RX_DCOC_RANGE_837___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_837__RX_DCOC_RES_I_837___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_837__RX_DCOC_RES_I_837___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_837__RX_DCOC_RES_Q_837___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_837__RX_DCOC_RES_Q_837___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_837___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_837___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_838 (0x005ECD18) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_838___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_838___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_838__RX_DCOC_RANGE_838___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_838__RX_DCOC_RES_I_838___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_838__RX_DCOC_RES_Q_838___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_838__RX_DCOC_RANGE_838___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_838__RX_DCOC_RANGE_838___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_838__RX_DCOC_RES_I_838___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_838__RX_DCOC_RES_I_838___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_838__RX_DCOC_RES_Q_838___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_838__RX_DCOC_RES_Q_838___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_838___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_838___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_839 (0x005ECD1C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_839___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_839___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_839__RX_DCOC_RANGE_839___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_839__RX_DCOC_RES_I_839___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_839__RX_DCOC_RES_Q_839___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_839__RX_DCOC_RANGE_839___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_839__RX_DCOC_RANGE_839___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_839__RX_DCOC_RES_I_839___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_839__RX_DCOC_RES_I_839___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_839__RX_DCOC_RES_Q_839___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_839__RX_DCOC_RES_Q_839___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_839___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_839___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_840 (0x005ECD20) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_840___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_840___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_840__RX_DCOC_RANGE_840___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_840__RX_DCOC_RES_I_840___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_840__RX_DCOC_RES_Q_840___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_840__RX_DCOC_RANGE_840___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_840__RX_DCOC_RANGE_840___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_840__RX_DCOC_RES_I_840___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_840__RX_DCOC_RES_I_840___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_840__RX_DCOC_RES_Q_840___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_840__RX_DCOC_RES_Q_840___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_840___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_840___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_841 (0x005ECD24) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_841___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_841___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_841__RX_DCOC_RANGE_841___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_841__RX_DCOC_RES_I_841___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_841__RX_DCOC_RES_Q_841___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_841__RX_DCOC_RANGE_841___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_841__RX_DCOC_RANGE_841___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_841__RX_DCOC_RES_I_841___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_841__RX_DCOC_RES_I_841___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_841__RX_DCOC_RES_Q_841___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_841__RX_DCOC_RES_Q_841___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_841___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_841___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_842 (0x005ECD28) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_842___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_842___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_842__RX_DCOC_RANGE_842___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_842__RX_DCOC_RES_I_842___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_842__RX_DCOC_RES_Q_842___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_842__RX_DCOC_RANGE_842___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_842__RX_DCOC_RANGE_842___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_842__RX_DCOC_RES_I_842___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_842__RX_DCOC_RES_I_842___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_842__RX_DCOC_RES_Q_842___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_842__RX_DCOC_RES_Q_842___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_842___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_842___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_843 (0x005ECD2C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_843___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_843___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_843__RX_DCOC_RANGE_843___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_843__RX_DCOC_RES_I_843___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_843__RX_DCOC_RES_Q_843___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_843__RX_DCOC_RANGE_843___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_843__RX_DCOC_RANGE_843___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_843__RX_DCOC_RES_I_843___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_843__RX_DCOC_RES_I_843___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_843__RX_DCOC_RES_Q_843___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_843__RX_DCOC_RES_Q_843___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_843___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_843___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_844 (0x005ECD30) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_844___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_844___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_844__RX_DCOC_RANGE_844___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_844__RX_DCOC_RES_I_844___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_844__RX_DCOC_RES_Q_844___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_844__RX_DCOC_RANGE_844___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_844__RX_DCOC_RANGE_844___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_844__RX_DCOC_RES_I_844___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_844__RX_DCOC_RES_I_844___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_844__RX_DCOC_RES_Q_844___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_844__RX_DCOC_RES_Q_844___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_844___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_844___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_845 (0x005ECD34) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_845___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_845___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_845__RX_DCOC_RANGE_845___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_845__RX_DCOC_RES_I_845___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_845__RX_DCOC_RES_Q_845___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_845__RX_DCOC_RANGE_845___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_845__RX_DCOC_RANGE_845___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_845__RX_DCOC_RES_I_845___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_845__RX_DCOC_RES_I_845___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_845__RX_DCOC_RES_Q_845___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_845__RX_DCOC_RES_Q_845___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_845___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_845___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_846 (0x005ECD38) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_846___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_846___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_846__RX_DCOC_RANGE_846___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_846__RX_DCOC_RES_I_846___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_846__RX_DCOC_RES_Q_846___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_846__RX_DCOC_RANGE_846___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_846__RX_DCOC_RANGE_846___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_846__RX_DCOC_RES_I_846___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_846__RX_DCOC_RES_I_846___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_846__RX_DCOC_RES_Q_846___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_846__RX_DCOC_RES_Q_846___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_846___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_846___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_847 (0x005ECD3C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_847___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_847___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_847__RX_DCOC_RANGE_847___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_847__RX_DCOC_RES_I_847___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_847__RX_DCOC_RES_Q_847___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_847__RX_DCOC_RANGE_847___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_847__RX_DCOC_RANGE_847___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_847__RX_DCOC_RES_I_847___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_847__RX_DCOC_RES_I_847___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_847__RX_DCOC_RES_Q_847___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_847__RX_DCOC_RES_Q_847___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_847___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_847___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_848 (0x005ECD40) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_848___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_848___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_848__RX_DCOC_RANGE_848___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_848__RX_DCOC_RES_I_848___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_848__RX_DCOC_RES_Q_848___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_848__RX_DCOC_RANGE_848___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_848__RX_DCOC_RANGE_848___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_848__RX_DCOC_RES_I_848___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_848__RX_DCOC_RES_I_848___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_848__RX_DCOC_RES_Q_848___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_848__RX_DCOC_RES_Q_848___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_848___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_848___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_849 (0x005ECD44) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_849___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_849___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_849__RX_DCOC_RANGE_849___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_849__RX_DCOC_RES_I_849___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_849__RX_DCOC_RES_Q_849___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_849__RX_DCOC_RANGE_849___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_849__RX_DCOC_RANGE_849___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_849__RX_DCOC_RES_I_849___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_849__RX_DCOC_RES_I_849___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_849__RX_DCOC_RES_Q_849___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_849__RX_DCOC_RES_Q_849___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_849___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_849___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_850 (0x005ECD48) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_850___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_850___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_850__RX_DCOC_RANGE_850___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_850__RX_DCOC_RES_I_850___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_850__RX_DCOC_RES_Q_850___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_850__RX_DCOC_RANGE_850___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_850__RX_DCOC_RANGE_850___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_850__RX_DCOC_RES_I_850___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_850__RX_DCOC_RES_I_850___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_850__RX_DCOC_RES_Q_850___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_850__RX_DCOC_RES_Q_850___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_850___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_850___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_851 (0x005ECD4C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_851___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_851___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_851__RX_DCOC_RANGE_851___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_851__RX_DCOC_RES_I_851___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_851__RX_DCOC_RES_Q_851___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_851__RX_DCOC_RANGE_851___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_851__RX_DCOC_RANGE_851___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_851__RX_DCOC_RES_I_851___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_851__RX_DCOC_RES_I_851___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_851__RX_DCOC_RES_Q_851___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_851__RX_DCOC_RES_Q_851___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_851___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_851___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_852 (0x005ECD50) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_852___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_852___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_852__RX_DCOC_RANGE_852___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_852__RX_DCOC_RES_I_852___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_852__RX_DCOC_RES_Q_852___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_852__RX_DCOC_RANGE_852___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_852__RX_DCOC_RANGE_852___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_852__RX_DCOC_RES_I_852___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_852__RX_DCOC_RES_I_852___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_852__RX_DCOC_RES_Q_852___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_852__RX_DCOC_RES_Q_852___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_852___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_852___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_853 (0x005ECD54) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_853___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_853___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_853__RX_DCOC_RANGE_853___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_853__RX_DCOC_RES_I_853___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_853__RX_DCOC_RES_Q_853___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_853__RX_DCOC_RANGE_853___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_853__RX_DCOC_RANGE_853___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_853__RX_DCOC_RES_I_853___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_853__RX_DCOC_RES_I_853___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_853__RX_DCOC_RES_Q_853___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_853__RX_DCOC_RES_Q_853___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_853___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_853___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_854 (0x005ECD58) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_854___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_854___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_854__RX_DCOC_RANGE_854___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_854__RX_DCOC_RES_I_854___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_854__RX_DCOC_RES_Q_854___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_854__RX_DCOC_RANGE_854___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_854__RX_DCOC_RANGE_854___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_854__RX_DCOC_RES_I_854___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_854__RX_DCOC_RES_I_854___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_854__RX_DCOC_RES_Q_854___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_854__RX_DCOC_RES_Q_854___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_854___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_854___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_855 (0x005ECD5C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_855___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_855___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_855__RX_DCOC_RANGE_855___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_855__RX_DCOC_RES_I_855___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_855__RX_DCOC_RES_Q_855___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_855__RX_DCOC_RANGE_855___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_855__RX_DCOC_RANGE_855___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_855__RX_DCOC_RES_I_855___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_855__RX_DCOC_RES_I_855___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_855__RX_DCOC_RES_Q_855___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_855__RX_DCOC_RES_Q_855___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_855___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_855___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_856 (0x005ECD60) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_856___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_856___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_856__RX_DCOC_RANGE_856___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_856__RX_DCOC_RES_I_856___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_856__RX_DCOC_RES_Q_856___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_856__RX_DCOC_RANGE_856___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_856__RX_DCOC_RANGE_856___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_856__RX_DCOC_RES_I_856___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_856__RX_DCOC_RES_I_856___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_856__RX_DCOC_RES_Q_856___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_856__RX_DCOC_RES_Q_856___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_856___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_856___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_857 (0x005ECD64) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_857___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_857___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_857__RX_DCOC_RANGE_857___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_857__RX_DCOC_RES_I_857___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_857__RX_DCOC_RES_Q_857___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_857__RX_DCOC_RANGE_857___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_857__RX_DCOC_RANGE_857___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_857__RX_DCOC_RES_I_857___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_857__RX_DCOC_RES_I_857___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_857__RX_DCOC_RES_Q_857___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_857__RX_DCOC_RES_Q_857___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_857___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_857___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_858 (0x005ECD68) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_858___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_858___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_858__RX_DCOC_RANGE_858___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_858__RX_DCOC_RES_I_858___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_858__RX_DCOC_RES_Q_858___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_858__RX_DCOC_RANGE_858___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_858__RX_DCOC_RANGE_858___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_858__RX_DCOC_RES_I_858___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_858__RX_DCOC_RES_I_858___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_858__RX_DCOC_RES_Q_858___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_858__RX_DCOC_RES_Q_858___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_858___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_858___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_859 (0x005ECD6C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_859___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_859___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_859__RX_DCOC_RANGE_859___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_859__RX_DCOC_RES_I_859___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_859__RX_DCOC_RES_Q_859___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_859__RX_DCOC_RANGE_859___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_859__RX_DCOC_RANGE_859___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_859__RX_DCOC_RES_I_859___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_859__RX_DCOC_RES_I_859___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_859__RX_DCOC_RES_Q_859___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_859__RX_DCOC_RES_Q_859___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_859___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_859___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_860 (0x005ECD70) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_860___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_860___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_860__RX_DCOC_RANGE_860___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_860__RX_DCOC_RES_I_860___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_860__RX_DCOC_RES_Q_860___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_860__RX_DCOC_RANGE_860___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_860__RX_DCOC_RANGE_860___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_860__RX_DCOC_RES_I_860___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_860__RX_DCOC_RES_I_860___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_860__RX_DCOC_RES_Q_860___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_860__RX_DCOC_RES_Q_860___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_860___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_860___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_861 (0x005ECD74) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_861___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_861___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_861__RX_DCOC_RANGE_861___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_861__RX_DCOC_RES_I_861___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_861__RX_DCOC_RES_Q_861___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_861__RX_DCOC_RANGE_861___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_861__RX_DCOC_RANGE_861___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_861__RX_DCOC_RES_I_861___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_861__RX_DCOC_RES_I_861___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_861__RX_DCOC_RES_Q_861___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_861__RX_DCOC_RES_Q_861___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_861___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_861___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_862 (0x005ECD78) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_862___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_862___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_862__RX_DCOC_RANGE_862___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_862__RX_DCOC_RES_I_862___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_862__RX_DCOC_RES_Q_862___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_862__RX_DCOC_RANGE_862___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_862__RX_DCOC_RANGE_862___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_862__RX_DCOC_RES_I_862___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_862__RX_DCOC_RES_I_862___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_862__RX_DCOC_RES_Q_862___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_862__RX_DCOC_RES_Q_862___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_862___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_862___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_863 (0x005ECD7C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_863___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_863___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_863__RX_DCOC_RANGE_863___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_863__RX_DCOC_RES_I_863___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_863__RX_DCOC_RES_Q_863___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_863__RX_DCOC_RANGE_863___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_863__RX_DCOC_RANGE_863___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_863__RX_DCOC_RES_I_863___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_863__RX_DCOC_RES_I_863___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_863__RX_DCOC_RES_Q_863___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_863__RX_DCOC_RES_Q_863___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_863___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_863___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_864 (0x005ECD80) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_864___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_864___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_864__RX_DCOC_RANGE_864___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_864__RX_DCOC_RES_I_864___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_864__RX_DCOC_RES_Q_864___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_864__RX_DCOC_RANGE_864___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_864__RX_DCOC_RANGE_864___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_864__RX_DCOC_RES_I_864___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_864__RX_DCOC_RES_I_864___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_864__RX_DCOC_RES_Q_864___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_864__RX_DCOC_RES_Q_864___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_864___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_864___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_865 (0x005ECD84) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_865___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_865___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_865__RX_DCOC_RANGE_865___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_865__RX_DCOC_RES_I_865___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_865__RX_DCOC_RES_Q_865___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_865__RX_DCOC_RANGE_865___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_865__RX_DCOC_RANGE_865___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_865__RX_DCOC_RES_I_865___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_865__RX_DCOC_RES_I_865___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_865__RX_DCOC_RES_Q_865___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_865__RX_DCOC_RES_Q_865___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_865___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_865___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_866 (0x005ECD88) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_866___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_866___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_866__RX_DCOC_RANGE_866___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_866__RX_DCOC_RES_I_866___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_866__RX_DCOC_RES_Q_866___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_866__RX_DCOC_RANGE_866___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_866__RX_DCOC_RANGE_866___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_866__RX_DCOC_RES_I_866___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_866__RX_DCOC_RES_I_866___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_866__RX_DCOC_RES_Q_866___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_866__RX_DCOC_RES_Q_866___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_866___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_866___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_867 (0x005ECD8C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_867___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_867___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_867__RX_DCOC_RANGE_867___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_867__RX_DCOC_RES_I_867___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_867__RX_DCOC_RES_Q_867___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_867__RX_DCOC_RANGE_867___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_867__RX_DCOC_RANGE_867___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_867__RX_DCOC_RES_I_867___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_867__RX_DCOC_RES_I_867___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_867__RX_DCOC_RES_Q_867___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_867__RX_DCOC_RES_Q_867___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_867___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_867___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_868 (0x005ECD90) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_868___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_868___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_868__RX_DCOC_RANGE_868___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_868__RX_DCOC_RES_I_868___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_868__RX_DCOC_RES_Q_868___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_868__RX_DCOC_RANGE_868___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_868__RX_DCOC_RANGE_868___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_868__RX_DCOC_RES_I_868___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_868__RX_DCOC_RES_I_868___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_868__RX_DCOC_RES_Q_868___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_868__RX_DCOC_RES_Q_868___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_868___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_868___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_869 (0x005ECD94) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_869___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_869___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_869__RX_DCOC_RANGE_869___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_869__RX_DCOC_RES_I_869___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_869__RX_DCOC_RES_Q_869___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_869__RX_DCOC_RANGE_869___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_869__RX_DCOC_RANGE_869___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_869__RX_DCOC_RES_I_869___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_869__RX_DCOC_RES_I_869___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_869__RX_DCOC_RES_Q_869___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_869__RX_DCOC_RES_Q_869___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_869___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_869___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_870 (0x005ECD98) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_870___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_870___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_870__RX_DCOC_RANGE_870___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_870__RX_DCOC_RES_I_870___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_870__RX_DCOC_RES_Q_870___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_870__RX_DCOC_RANGE_870___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_870__RX_DCOC_RANGE_870___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_870__RX_DCOC_RES_I_870___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_870__RX_DCOC_RES_I_870___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_870__RX_DCOC_RES_Q_870___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_870__RX_DCOC_RES_Q_870___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_870___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_870___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_871 (0x005ECD9C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_871___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_871___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_871__RX_DCOC_RANGE_871___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_871__RX_DCOC_RES_I_871___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_871__RX_DCOC_RES_Q_871___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_871__RX_DCOC_RANGE_871___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_871__RX_DCOC_RANGE_871___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_871__RX_DCOC_RES_I_871___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_871__RX_DCOC_RES_I_871___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_871__RX_DCOC_RES_Q_871___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_871__RX_DCOC_RES_Q_871___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_871___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_871___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_872 (0x005ECDA0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_872___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_872___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_872__RX_DCOC_RANGE_872___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_872__RX_DCOC_RES_I_872___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_872__RX_DCOC_RES_Q_872___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_872__RX_DCOC_RANGE_872___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_872__RX_DCOC_RANGE_872___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_872__RX_DCOC_RES_I_872___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_872__RX_DCOC_RES_I_872___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_872__RX_DCOC_RES_Q_872___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_872__RX_DCOC_RES_Q_872___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_872___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_872___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_873 (0x005ECDA4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_873___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_873___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_873__RX_DCOC_RANGE_873___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_873__RX_DCOC_RES_I_873___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_873__RX_DCOC_RES_Q_873___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_873__RX_DCOC_RANGE_873___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_873__RX_DCOC_RANGE_873___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_873__RX_DCOC_RES_I_873___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_873__RX_DCOC_RES_I_873___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_873__RX_DCOC_RES_Q_873___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_873__RX_DCOC_RES_Q_873___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_873___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_873___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_874 (0x005ECDA8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_874___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_874___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_874__RX_DCOC_RANGE_874___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_874__RX_DCOC_RES_I_874___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_874__RX_DCOC_RES_Q_874___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_874__RX_DCOC_RANGE_874___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_874__RX_DCOC_RANGE_874___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_874__RX_DCOC_RES_I_874___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_874__RX_DCOC_RES_I_874___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_874__RX_DCOC_RES_Q_874___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_874__RX_DCOC_RES_Q_874___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_874___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_874___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_875 (0x005ECDAC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_875___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_875___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_875__RX_DCOC_RANGE_875___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_875__RX_DCOC_RES_I_875___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_875__RX_DCOC_RES_Q_875___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_875__RX_DCOC_RANGE_875___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_875__RX_DCOC_RANGE_875___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_875__RX_DCOC_RES_I_875___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_875__RX_DCOC_RES_I_875___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_875__RX_DCOC_RES_Q_875___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_875__RX_DCOC_RES_Q_875___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_875___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_875___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_876 (0x005ECDB0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_876___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_876___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_876__RX_DCOC_RANGE_876___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_876__RX_DCOC_RES_I_876___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_876__RX_DCOC_RES_Q_876___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_876__RX_DCOC_RANGE_876___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_876__RX_DCOC_RANGE_876___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_876__RX_DCOC_RES_I_876___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_876__RX_DCOC_RES_I_876___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_876__RX_DCOC_RES_Q_876___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_876__RX_DCOC_RES_Q_876___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_876___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_876___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_877 (0x005ECDB4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_877___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_877___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_877__RX_DCOC_RANGE_877___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_877__RX_DCOC_RES_I_877___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_877__RX_DCOC_RES_Q_877___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_877__RX_DCOC_RANGE_877___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_877__RX_DCOC_RANGE_877___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_877__RX_DCOC_RES_I_877___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_877__RX_DCOC_RES_I_877___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_877__RX_DCOC_RES_Q_877___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_877__RX_DCOC_RES_Q_877___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_877___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_877___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_878 (0x005ECDB8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_878___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_878___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_878__RX_DCOC_RANGE_878___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_878__RX_DCOC_RES_I_878___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_878__RX_DCOC_RES_Q_878___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_878__RX_DCOC_RANGE_878___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_878__RX_DCOC_RANGE_878___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_878__RX_DCOC_RES_I_878___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_878__RX_DCOC_RES_I_878___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_878__RX_DCOC_RES_Q_878___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_878__RX_DCOC_RES_Q_878___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_878___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_878___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_879 (0x005ECDBC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_879___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_879___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_879__RX_DCOC_RANGE_879___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_879__RX_DCOC_RES_I_879___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_879__RX_DCOC_RES_Q_879___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_879__RX_DCOC_RANGE_879___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_879__RX_DCOC_RANGE_879___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_879__RX_DCOC_RES_I_879___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_879__RX_DCOC_RES_I_879___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_879__RX_DCOC_RES_Q_879___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_879__RX_DCOC_RES_Q_879___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_879___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_879___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_880 (0x005ECDC0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_880___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_880___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_880__RX_DCOC_RANGE_880___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_880__RX_DCOC_RES_I_880___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_880__RX_DCOC_RES_Q_880___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_880__RX_DCOC_RANGE_880___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_880__RX_DCOC_RANGE_880___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_880__RX_DCOC_RES_I_880___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_880__RX_DCOC_RES_I_880___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_880__RX_DCOC_RES_Q_880___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_880__RX_DCOC_RES_Q_880___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_880___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_880___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_881 (0x005ECDC4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_881___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_881___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_881__RX_DCOC_RANGE_881___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_881__RX_DCOC_RES_I_881___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_881__RX_DCOC_RES_Q_881___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_881__RX_DCOC_RANGE_881___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_881__RX_DCOC_RANGE_881___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_881__RX_DCOC_RES_I_881___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_881__RX_DCOC_RES_I_881___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_881__RX_DCOC_RES_Q_881___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_881__RX_DCOC_RES_Q_881___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_881___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_881___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_882 (0x005ECDC8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_882___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_882___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_882__RX_DCOC_RANGE_882___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_882__RX_DCOC_RES_I_882___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_882__RX_DCOC_RES_Q_882___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_882__RX_DCOC_RANGE_882___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_882__RX_DCOC_RANGE_882___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_882__RX_DCOC_RES_I_882___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_882__RX_DCOC_RES_I_882___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_882__RX_DCOC_RES_Q_882___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_882__RX_DCOC_RES_Q_882___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_882___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_882___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_883 (0x005ECDCC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_883___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_883___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_883__RX_DCOC_RANGE_883___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_883__RX_DCOC_RES_I_883___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_883__RX_DCOC_RES_Q_883___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_883__RX_DCOC_RANGE_883___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_883__RX_DCOC_RANGE_883___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_883__RX_DCOC_RES_I_883___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_883__RX_DCOC_RES_I_883___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_883__RX_DCOC_RES_Q_883___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_883__RX_DCOC_RES_Q_883___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_883___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_883___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_884 (0x005ECDD0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_884___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_884___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_884__RX_DCOC_RANGE_884___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_884__RX_DCOC_RES_I_884___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_884__RX_DCOC_RES_Q_884___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_884__RX_DCOC_RANGE_884___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_884__RX_DCOC_RANGE_884___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_884__RX_DCOC_RES_I_884___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_884__RX_DCOC_RES_I_884___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_884__RX_DCOC_RES_Q_884___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_884__RX_DCOC_RES_Q_884___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_884___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_884___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_885 (0x005ECDD4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_885___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_885___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_885__RX_DCOC_RANGE_885___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_885__RX_DCOC_RES_I_885___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_885__RX_DCOC_RES_Q_885___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_885__RX_DCOC_RANGE_885___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_885__RX_DCOC_RANGE_885___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_885__RX_DCOC_RES_I_885___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_885__RX_DCOC_RES_I_885___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_885__RX_DCOC_RES_Q_885___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_885__RX_DCOC_RES_Q_885___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_885___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_885___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_886 (0x005ECDD8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_886___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_886___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_886__RX_DCOC_RANGE_886___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_886__RX_DCOC_RES_I_886___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_886__RX_DCOC_RES_Q_886___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_886__RX_DCOC_RANGE_886___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_886__RX_DCOC_RANGE_886___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_886__RX_DCOC_RES_I_886___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_886__RX_DCOC_RES_I_886___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_886__RX_DCOC_RES_Q_886___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_886__RX_DCOC_RES_Q_886___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_886___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_886___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_887 (0x005ECDDC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_887___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_887___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_887__RX_DCOC_RANGE_887___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_887__RX_DCOC_RES_I_887___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_887__RX_DCOC_RES_Q_887___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_887__RX_DCOC_RANGE_887___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_887__RX_DCOC_RANGE_887___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_887__RX_DCOC_RES_I_887___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_887__RX_DCOC_RES_I_887___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_887__RX_DCOC_RES_Q_887___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_887__RX_DCOC_RES_Q_887___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_887___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_887___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_888 (0x005ECDE0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_888___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_888___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_888__RX_DCOC_RANGE_888___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_888__RX_DCOC_RES_I_888___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_888__RX_DCOC_RES_Q_888___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_888__RX_DCOC_RANGE_888___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_888__RX_DCOC_RANGE_888___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_888__RX_DCOC_RES_I_888___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_888__RX_DCOC_RES_I_888___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_888__RX_DCOC_RES_Q_888___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_888__RX_DCOC_RES_Q_888___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_888___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_888___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_889 (0x005ECDE4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_889___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_889___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_889__RX_DCOC_RANGE_889___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_889__RX_DCOC_RES_I_889___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_889__RX_DCOC_RES_Q_889___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_889__RX_DCOC_RANGE_889___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_889__RX_DCOC_RANGE_889___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_889__RX_DCOC_RES_I_889___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_889__RX_DCOC_RES_I_889___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_889__RX_DCOC_RES_Q_889___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_889__RX_DCOC_RES_Q_889___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_889___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_889___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_890 (0x005ECDE8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_890___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_890___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_890__RX_DCOC_RANGE_890___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_890__RX_DCOC_RES_I_890___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_890__RX_DCOC_RES_Q_890___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_890__RX_DCOC_RANGE_890___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_890__RX_DCOC_RANGE_890___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_890__RX_DCOC_RES_I_890___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_890__RX_DCOC_RES_I_890___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_890__RX_DCOC_RES_Q_890___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_890__RX_DCOC_RES_Q_890___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_890___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_890___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_891 (0x005ECDEC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_891___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_891___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_891__RX_DCOC_RANGE_891___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_891__RX_DCOC_RES_I_891___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_891__RX_DCOC_RES_Q_891___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_891__RX_DCOC_RANGE_891___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_891__RX_DCOC_RANGE_891___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_891__RX_DCOC_RES_I_891___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_891__RX_DCOC_RES_I_891___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_891__RX_DCOC_RES_Q_891___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_891__RX_DCOC_RES_Q_891___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_891___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_891___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_892 (0x005ECDF0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_892___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_892___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_892__RX_DCOC_RANGE_892___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_892__RX_DCOC_RES_I_892___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_892__RX_DCOC_RES_Q_892___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_892__RX_DCOC_RANGE_892___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_892__RX_DCOC_RANGE_892___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_892__RX_DCOC_RES_I_892___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_892__RX_DCOC_RES_I_892___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_892__RX_DCOC_RES_Q_892___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_892__RX_DCOC_RES_Q_892___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_892___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_892___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_893 (0x005ECDF4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_893___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_893___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_893__RX_DCOC_RANGE_893___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_893__RX_DCOC_RES_I_893___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_893__RX_DCOC_RES_Q_893___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_893__RX_DCOC_RANGE_893___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_893__RX_DCOC_RANGE_893___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_893__RX_DCOC_RES_I_893___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_893__RX_DCOC_RES_I_893___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_893__RX_DCOC_RES_Q_893___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_893__RX_DCOC_RES_Q_893___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_893___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_893___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_894 (0x005ECDF8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_894___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_894___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_894__RX_DCOC_RANGE_894___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_894__RX_DCOC_RES_I_894___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_894__RX_DCOC_RES_Q_894___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_894__RX_DCOC_RANGE_894___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_894__RX_DCOC_RANGE_894___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_894__RX_DCOC_RES_I_894___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_894__RX_DCOC_RES_I_894___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_894__RX_DCOC_RES_Q_894___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_894__RX_DCOC_RES_Q_894___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_894___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_894___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_895 (0x005ECDFC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_895___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_895___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_895__RX_DCOC_RANGE_895___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_895__RX_DCOC_RES_I_895___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_895__RX_DCOC_RES_Q_895___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_895__RX_DCOC_RANGE_895___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_895__RX_DCOC_RANGE_895___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_895__RX_DCOC_RES_I_895___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_895__RX_DCOC_RES_I_895___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_895__RX_DCOC_RES_Q_895___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_895__RX_DCOC_RES_Q_895___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_895___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_895___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_896 (0x005ECE00) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_896___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_896___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_896__RX_DCOC_RANGE_896___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_896__RX_DCOC_RES_I_896___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_896__RX_DCOC_RES_Q_896___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_896__RX_DCOC_RANGE_896___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_896__RX_DCOC_RANGE_896___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_896__RX_DCOC_RES_I_896___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_896__RX_DCOC_RES_I_896___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_896__RX_DCOC_RES_Q_896___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_896__RX_DCOC_RES_Q_896___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_896___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_896___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_897 (0x005ECE04) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_897___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_897___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_897__RX_DCOC_RANGE_897___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_897__RX_DCOC_RES_I_897___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_897__RX_DCOC_RES_Q_897___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_897__RX_DCOC_RANGE_897___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_897__RX_DCOC_RANGE_897___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_897__RX_DCOC_RES_I_897___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_897__RX_DCOC_RES_I_897___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_897__RX_DCOC_RES_Q_897___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_897__RX_DCOC_RES_Q_897___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_897___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_897___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_898 (0x005ECE08) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_898___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_898___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_898__RX_DCOC_RANGE_898___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_898__RX_DCOC_RES_I_898___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_898__RX_DCOC_RES_Q_898___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_898__RX_DCOC_RANGE_898___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_898__RX_DCOC_RANGE_898___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_898__RX_DCOC_RES_I_898___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_898__RX_DCOC_RES_I_898___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_898__RX_DCOC_RES_Q_898___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_898__RX_DCOC_RES_Q_898___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_898___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_898___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_899 (0x005ECE0C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_899___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_899___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_899__RX_DCOC_RANGE_899___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_899__RX_DCOC_RES_I_899___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_899__RX_DCOC_RES_Q_899___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_899__RX_DCOC_RANGE_899___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_899__RX_DCOC_RANGE_899___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_899__RX_DCOC_RES_I_899___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_899__RX_DCOC_RES_I_899___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_899__RX_DCOC_RES_Q_899___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_899__RX_DCOC_RES_Q_899___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_899___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_899___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_900 (0x005ECE10) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_900___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_900___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_900__RX_DCOC_RANGE_900___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_900__RX_DCOC_RES_I_900___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_900__RX_DCOC_RES_Q_900___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_900__RX_DCOC_RANGE_900___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_900__RX_DCOC_RANGE_900___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_900__RX_DCOC_RES_I_900___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_900__RX_DCOC_RES_I_900___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_900__RX_DCOC_RES_Q_900___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_900__RX_DCOC_RES_Q_900___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_900___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_900___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_901 (0x005ECE14) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_901___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_901___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_901__RX_DCOC_RANGE_901___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_901__RX_DCOC_RES_I_901___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_901__RX_DCOC_RES_Q_901___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_901__RX_DCOC_RANGE_901___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_901__RX_DCOC_RANGE_901___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_901__RX_DCOC_RES_I_901___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_901__RX_DCOC_RES_I_901___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_901__RX_DCOC_RES_Q_901___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_901__RX_DCOC_RES_Q_901___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_901___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_901___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_902 (0x005ECE18) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_902___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_902___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_902__RX_DCOC_RANGE_902___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_902__RX_DCOC_RES_I_902___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_902__RX_DCOC_RES_Q_902___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_902__RX_DCOC_RANGE_902___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_902__RX_DCOC_RANGE_902___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_902__RX_DCOC_RES_I_902___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_902__RX_DCOC_RES_I_902___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_902__RX_DCOC_RES_Q_902___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_902__RX_DCOC_RES_Q_902___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_902___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_902___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_903 (0x005ECE1C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_903___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_903___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_903__RX_DCOC_RANGE_903___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_903__RX_DCOC_RES_I_903___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_903__RX_DCOC_RES_Q_903___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_903__RX_DCOC_RANGE_903___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_903__RX_DCOC_RANGE_903___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_903__RX_DCOC_RES_I_903___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_903__RX_DCOC_RES_I_903___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_903__RX_DCOC_RES_Q_903___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_903__RX_DCOC_RES_Q_903___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_903___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_903___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_904 (0x005ECE20) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_904___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_904___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_904__RX_DCOC_RANGE_904___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_904__RX_DCOC_RES_I_904___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_904__RX_DCOC_RES_Q_904___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_904__RX_DCOC_RANGE_904___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_904__RX_DCOC_RANGE_904___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_904__RX_DCOC_RES_I_904___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_904__RX_DCOC_RES_I_904___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_904__RX_DCOC_RES_Q_904___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_904__RX_DCOC_RES_Q_904___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_904___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_904___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_905 (0x005ECE24) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_905___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_905___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_905__RX_DCOC_RANGE_905___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_905__RX_DCOC_RES_I_905___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_905__RX_DCOC_RES_Q_905___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_905__RX_DCOC_RANGE_905___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_905__RX_DCOC_RANGE_905___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_905__RX_DCOC_RES_I_905___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_905__RX_DCOC_RES_I_905___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_905__RX_DCOC_RES_Q_905___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_905__RX_DCOC_RES_Q_905___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_905___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_905___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_906 (0x005ECE28) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_906___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_906___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_906__RX_DCOC_RANGE_906___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_906__RX_DCOC_RES_I_906___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_906__RX_DCOC_RES_Q_906___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_906__RX_DCOC_RANGE_906___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_906__RX_DCOC_RANGE_906___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_906__RX_DCOC_RES_I_906___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_906__RX_DCOC_RES_I_906___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_906__RX_DCOC_RES_Q_906___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_906__RX_DCOC_RES_Q_906___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_906___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_906___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_907 (0x005ECE2C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_907___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_907___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_907__RX_DCOC_RANGE_907___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_907__RX_DCOC_RES_I_907___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_907__RX_DCOC_RES_Q_907___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_907__RX_DCOC_RANGE_907___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_907__RX_DCOC_RANGE_907___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_907__RX_DCOC_RES_I_907___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_907__RX_DCOC_RES_I_907___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_907__RX_DCOC_RES_Q_907___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_907__RX_DCOC_RES_Q_907___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_907___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_907___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_908 (0x005ECE30) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_908___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_908___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_908__RX_DCOC_RANGE_908___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_908__RX_DCOC_RES_I_908___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_908__RX_DCOC_RES_Q_908___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_908__RX_DCOC_RANGE_908___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_908__RX_DCOC_RANGE_908___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_908__RX_DCOC_RES_I_908___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_908__RX_DCOC_RES_I_908___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_908__RX_DCOC_RES_Q_908___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_908__RX_DCOC_RES_Q_908___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_908___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_908___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_909 (0x005ECE34) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_909___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_909___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_909__RX_DCOC_RANGE_909___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_909__RX_DCOC_RES_I_909___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_909__RX_DCOC_RES_Q_909___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_909__RX_DCOC_RANGE_909___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_909__RX_DCOC_RANGE_909___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_909__RX_DCOC_RES_I_909___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_909__RX_DCOC_RES_I_909___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_909__RX_DCOC_RES_Q_909___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_909__RX_DCOC_RES_Q_909___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_909___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_909___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_910 (0x005ECE38) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_910___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_910___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_910__RX_DCOC_RANGE_910___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_910__RX_DCOC_RES_I_910___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_910__RX_DCOC_RES_Q_910___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_910__RX_DCOC_RANGE_910___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_910__RX_DCOC_RANGE_910___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_910__RX_DCOC_RES_I_910___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_910__RX_DCOC_RES_I_910___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_910__RX_DCOC_RES_Q_910___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_910__RX_DCOC_RES_Q_910___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_910___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_910___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_911 (0x005ECE3C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_911___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_911___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_911__RX_DCOC_RANGE_911___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_911__RX_DCOC_RES_I_911___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_911__RX_DCOC_RES_Q_911___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_911__RX_DCOC_RANGE_911___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_911__RX_DCOC_RANGE_911___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_911__RX_DCOC_RES_I_911___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_911__RX_DCOC_RES_I_911___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_911__RX_DCOC_RES_Q_911___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_911__RX_DCOC_RES_Q_911___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_911___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_911___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_912 (0x005ECE40) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_912___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_912___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_912__RX_DCOC_RANGE_912___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_912__RX_DCOC_RES_I_912___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_912__RX_DCOC_RES_Q_912___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_912__RX_DCOC_RANGE_912___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_912__RX_DCOC_RANGE_912___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_912__RX_DCOC_RES_I_912___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_912__RX_DCOC_RES_I_912___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_912__RX_DCOC_RES_Q_912___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_912__RX_DCOC_RES_Q_912___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_912___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_912___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_913 (0x005ECE44) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_913___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_913___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_913__RX_DCOC_RANGE_913___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_913__RX_DCOC_RES_I_913___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_913__RX_DCOC_RES_Q_913___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_913__RX_DCOC_RANGE_913___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_913__RX_DCOC_RANGE_913___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_913__RX_DCOC_RES_I_913___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_913__RX_DCOC_RES_I_913___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_913__RX_DCOC_RES_Q_913___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_913__RX_DCOC_RES_Q_913___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_913___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_913___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_914 (0x005ECE48) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_914___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_914___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_914__RX_DCOC_RANGE_914___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_914__RX_DCOC_RES_I_914___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_914__RX_DCOC_RES_Q_914___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_914__RX_DCOC_RANGE_914___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_914__RX_DCOC_RANGE_914___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_914__RX_DCOC_RES_I_914___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_914__RX_DCOC_RES_I_914___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_914__RX_DCOC_RES_Q_914___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_914__RX_DCOC_RES_Q_914___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_914___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_914___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_915 (0x005ECE4C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_915___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_915___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_915__RX_DCOC_RANGE_915___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_915__RX_DCOC_RES_I_915___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_915__RX_DCOC_RES_Q_915___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_915__RX_DCOC_RANGE_915___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_915__RX_DCOC_RANGE_915___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_915__RX_DCOC_RES_I_915___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_915__RX_DCOC_RES_I_915___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_915__RX_DCOC_RES_Q_915___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_915__RX_DCOC_RES_Q_915___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_915___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_915___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_916 (0x005ECE50) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_916___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_916___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_916__RX_DCOC_RANGE_916___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_916__RX_DCOC_RES_I_916___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_916__RX_DCOC_RES_Q_916___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_916__RX_DCOC_RANGE_916___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_916__RX_DCOC_RANGE_916___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_916__RX_DCOC_RES_I_916___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_916__RX_DCOC_RES_I_916___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_916__RX_DCOC_RES_Q_916___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_916__RX_DCOC_RES_Q_916___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_916___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_916___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_917 (0x005ECE54) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_917___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_917___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_917__RX_DCOC_RANGE_917___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_917__RX_DCOC_RES_I_917___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_917__RX_DCOC_RES_Q_917___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_917__RX_DCOC_RANGE_917___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_917__RX_DCOC_RANGE_917___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_917__RX_DCOC_RES_I_917___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_917__RX_DCOC_RES_I_917___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_917__RX_DCOC_RES_Q_917___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_917__RX_DCOC_RES_Q_917___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_917___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_917___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_918 (0x005ECE58) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_918___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_918___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_918__RX_DCOC_RANGE_918___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_918__RX_DCOC_RES_I_918___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_918__RX_DCOC_RES_Q_918___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_918__RX_DCOC_RANGE_918___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_918__RX_DCOC_RANGE_918___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_918__RX_DCOC_RES_I_918___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_918__RX_DCOC_RES_I_918___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_918__RX_DCOC_RES_Q_918___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_918__RX_DCOC_RES_Q_918___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_918___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_918___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_919 (0x005ECE5C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_919___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_919___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_919__RX_DCOC_RANGE_919___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_919__RX_DCOC_RES_I_919___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_919__RX_DCOC_RES_Q_919___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_919__RX_DCOC_RANGE_919___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_919__RX_DCOC_RANGE_919___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_919__RX_DCOC_RES_I_919___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_919__RX_DCOC_RES_I_919___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_919__RX_DCOC_RES_Q_919___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_919__RX_DCOC_RES_Q_919___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_919___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_919___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_920 (0x005ECE60) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_920___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_920___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_920__RX_DCOC_RANGE_920___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_920__RX_DCOC_RES_I_920___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_920__RX_DCOC_RES_Q_920___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_920__RX_DCOC_RANGE_920___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_920__RX_DCOC_RANGE_920___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_920__RX_DCOC_RES_I_920___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_920__RX_DCOC_RES_I_920___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_920__RX_DCOC_RES_Q_920___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_920__RX_DCOC_RES_Q_920___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_920___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_920___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_921 (0x005ECE64) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_921___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_921___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_921__RX_DCOC_RANGE_921___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_921__RX_DCOC_RES_I_921___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_921__RX_DCOC_RES_Q_921___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_921__RX_DCOC_RANGE_921___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_921__RX_DCOC_RANGE_921___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_921__RX_DCOC_RES_I_921___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_921__RX_DCOC_RES_I_921___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_921__RX_DCOC_RES_Q_921___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_921__RX_DCOC_RES_Q_921___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_921___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_921___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_922 (0x005ECE68) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_922___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_922___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_922__RX_DCOC_RANGE_922___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_922__RX_DCOC_RES_I_922___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_922__RX_DCOC_RES_Q_922___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_922__RX_DCOC_RANGE_922___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_922__RX_DCOC_RANGE_922___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_922__RX_DCOC_RES_I_922___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_922__RX_DCOC_RES_I_922___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_922__RX_DCOC_RES_Q_922___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_922__RX_DCOC_RES_Q_922___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_922___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_922___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_923 (0x005ECE6C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_923___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_923___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_923__RX_DCOC_RANGE_923___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_923__RX_DCOC_RES_I_923___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_923__RX_DCOC_RES_Q_923___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_923__RX_DCOC_RANGE_923___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_923__RX_DCOC_RANGE_923___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_923__RX_DCOC_RES_I_923___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_923__RX_DCOC_RES_I_923___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_923__RX_DCOC_RES_Q_923___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_923__RX_DCOC_RES_Q_923___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_923___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_923___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_924 (0x005ECE70) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_924___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_924___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_924__RX_DCOC_RANGE_924___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_924__RX_DCOC_RES_I_924___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_924__RX_DCOC_RES_Q_924___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_924__RX_DCOC_RANGE_924___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_924__RX_DCOC_RANGE_924___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_924__RX_DCOC_RES_I_924___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_924__RX_DCOC_RES_I_924___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_924__RX_DCOC_RES_Q_924___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_924__RX_DCOC_RES_Q_924___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_924___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_924___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_925 (0x005ECE74) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_925___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_925___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_925__RX_DCOC_RANGE_925___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_925__RX_DCOC_RES_I_925___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_925__RX_DCOC_RES_Q_925___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_925__RX_DCOC_RANGE_925___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_925__RX_DCOC_RANGE_925___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_925__RX_DCOC_RES_I_925___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_925__RX_DCOC_RES_I_925___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_925__RX_DCOC_RES_Q_925___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_925__RX_DCOC_RES_Q_925___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_925___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_925___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_926 (0x005ECE78) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_926___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_926___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_926__RX_DCOC_RANGE_926___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_926__RX_DCOC_RES_I_926___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_926__RX_DCOC_RES_Q_926___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_926__RX_DCOC_RANGE_926___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_926__RX_DCOC_RANGE_926___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_926__RX_DCOC_RES_I_926___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_926__RX_DCOC_RES_I_926___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_926__RX_DCOC_RES_Q_926___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_926__RX_DCOC_RES_Q_926___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_926___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_926___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_927 (0x005ECE7C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_927___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_927___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_927__RX_DCOC_RANGE_927___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_927__RX_DCOC_RES_I_927___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_927__RX_DCOC_RES_Q_927___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_927__RX_DCOC_RANGE_927___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_927__RX_DCOC_RANGE_927___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_927__RX_DCOC_RES_I_927___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_927__RX_DCOC_RES_I_927___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_927__RX_DCOC_RES_Q_927___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_927__RX_DCOC_RES_Q_927___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_927___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_927___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_928 (0x005ECE80) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_928___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_928___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_928__RX_DCOC_RANGE_928___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_928__RX_DCOC_RES_I_928___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_928__RX_DCOC_RES_Q_928___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_928__RX_DCOC_RANGE_928___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_928__RX_DCOC_RANGE_928___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_928__RX_DCOC_RES_I_928___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_928__RX_DCOC_RES_I_928___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_928__RX_DCOC_RES_Q_928___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_928__RX_DCOC_RES_Q_928___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_928___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_928___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_929 (0x005ECE84) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_929___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_929___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_929__RX_DCOC_RANGE_929___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_929__RX_DCOC_RES_I_929___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_929__RX_DCOC_RES_Q_929___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_929__RX_DCOC_RANGE_929___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_929__RX_DCOC_RANGE_929___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_929__RX_DCOC_RES_I_929___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_929__RX_DCOC_RES_I_929___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_929__RX_DCOC_RES_Q_929___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_929__RX_DCOC_RES_Q_929___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_929___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_929___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_930 (0x005ECE88) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_930___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_930___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_930__RX_DCOC_RANGE_930___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_930__RX_DCOC_RES_I_930___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_930__RX_DCOC_RES_Q_930___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_930__RX_DCOC_RANGE_930___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_930__RX_DCOC_RANGE_930___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_930__RX_DCOC_RES_I_930___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_930__RX_DCOC_RES_I_930___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_930__RX_DCOC_RES_Q_930___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_930__RX_DCOC_RES_Q_930___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_930___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_930___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_931 (0x005ECE8C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_931___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_931___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_931__RX_DCOC_RANGE_931___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_931__RX_DCOC_RES_I_931___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_931__RX_DCOC_RES_Q_931___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_931__RX_DCOC_RANGE_931___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_931__RX_DCOC_RANGE_931___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_931__RX_DCOC_RES_I_931___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_931__RX_DCOC_RES_I_931___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_931__RX_DCOC_RES_Q_931___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_931__RX_DCOC_RES_Q_931___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_931___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_931___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_932 (0x005ECE90) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_932___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_932___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_932__RX_DCOC_RANGE_932___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_932__RX_DCOC_RES_I_932___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_932__RX_DCOC_RES_Q_932___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_932__RX_DCOC_RANGE_932___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_932__RX_DCOC_RANGE_932___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_932__RX_DCOC_RES_I_932___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_932__RX_DCOC_RES_I_932___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_932__RX_DCOC_RES_Q_932___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_932__RX_DCOC_RES_Q_932___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_932___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_932___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_933 (0x005ECE94) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_933___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_933___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_933__RX_DCOC_RANGE_933___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_933__RX_DCOC_RES_I_933___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_933__RX_DCOC_RES_Q_933___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_933__RX_DCOC_RANGE_933___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_933__RX_DCOC_RANGE_933___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_933__RX_DCOC_RES_I_933___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_933__RX_DCOC_RES_I_933___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_933__RX_DCOC_RES_Q_933___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_933__RX_DCOC_RES_Q_933___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_933___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_933___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_934 (0x005ECE98) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_934___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_934___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_934__RX_DCOC_RANGE_934___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_934__RX_DCOC_RES_I_934___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_934__RX_DCOC_RES_Q_934___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_934__RX_DCOC_RANGE_934___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_934__RX_DCOC_RANGE_934___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_934__RX_DCOC_RES_I_934___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_934__RX_DCOC_RES_I_934___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_934__RX_DCOC_RES_Q_934___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_934__RX_DCOC_RES_Q_934___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_934___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_934___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_935 (0x005ECE9C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_935___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_935___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_935__RX_DCOC_RANGE_935___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_935__RX_DCOC_RES_I_935___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_935__RX_DCOC_RES_Q_935___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_935__RX_DCOC_RANGE_935___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_935__RX_DCOC_RANGE_935___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_935__RX_DCOC_RES_I_935___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_935__RX_DCOC_RES_I_935___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_935__RX_DCOC_RES_Q_935___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_935__RX_DCOC_RES_Q_935___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_935___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_935___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_936 (0x005ECEA0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_936___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_936___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_936__RX_DCOC_RANGE_936___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_936__RX_DCOC_RES_I_936___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_936__RX_DCOC_RES_Q_936___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_936__RX_DCOC_RANGE_936___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_936__RX_DCOC_RANGE_936___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_936__RX_DCOC_RES_I_936___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_936__RX_DCOC_RES_I_936___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_936__RX_DCOC_RES_Q_936___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_936__RX_DCOC_RES_Q_936___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_936___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_936___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_937 (0x005ECEA4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_937___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_937___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_937__RX_DCOC_RANGE_937___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_937__RX_DCOC_RES_I_937___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_937__RX_DCOC_RES_Q_937___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_937__RX_DCOC_RANGE_937___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_937__RX_DCOC_RANGE_937___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_937__RX_DCOC_RES_I_937___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_937__RX_DCOC_RES_I_937___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_937__RX_DCOC_RES_Q_937___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_937__RX_DCOC_RES_Q_937___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_937___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_937___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_938 (0x005ECEA8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_938___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_938___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_938__RX_DCOC_RANGE_938___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_938__RX_DCOC_RES_I_938___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_938__RX_DCOC_RES_Q_938___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_938__RX_DCOC_RANGE_938___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_938__RX_DCOC_RANGE_938___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_938__RX_DCOC_RES_I_938___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_938__RX_DCOC_RES_I_938___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_938__RX_DCOC_RES_Q_938___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_938__RX_DCOC_RES_Q_938___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_938___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_938___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_939 (0x005ECEAC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_939___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_939___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_939__RX_DCOC_RANGE_939___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_939__RX_DCOC_RES_I_939___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_939__RX_DCOC_RES_Q_939___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_939__RX_DCOC_RANGE_939___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_939__RX_DCOC_RANGE_939___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_939__RX_DCOC_RES_I_939___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_939__RX_DCOC_RES_I_939___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_939__RX_DCOC_RES_Q_939___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_939__RX_DCOC_RES_Q_939___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_939___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_939___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_940 (0x005ECEB0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_940___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_940___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_940__RX_DCOC_RANGE_940___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_940__RX_DCOC_RES_I_940___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_940__RX_DCOC_RES_Q_940___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_940__RX_DCOC_RANGE_940___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_940__RX_DCOC_RANGE_940___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_940__RX_DCOC_RES_I_940___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_940__RX_DCOC_RES_I_940___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_940__RX_DCOC_RES_Q_940___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_940__RX_DCOC_RES_Q_940___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_940___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_940___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_941 (0x005ECEB4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_941___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_941___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_941__RX_DCOC_RANGE_941___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_941__RX_DCOC_RES_I_941___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_941__RX_DCOC_RES_Q_941___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_941__RX_DCOC_RANGE_941___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_941__RX_DCOC_RANGE_941___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_941__RX_DCOC_RES_I_941___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_941__RX_DCOC_RES_I_941___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_941__RX_DCOC_RES_Q_941___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_941__RX_DCOC_RES_Q_941___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_941___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_941___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_942 (0x005ECEB8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_942___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_942___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_942__RX_DCOC_RANGE_942___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_942__RX_DCOC_RES_I_942___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_942__RX_DCOC_RES_Q_942___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_942__RX_DCOC_RANGE_942___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_942__RX_DCOC_RANGE_942___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_942__RX_DCOC_RES_I_942___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_942__RX_DCOC_RES_I_942___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_942__RX_DCOC_RES_Q_942___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_942__RX_DCOC_RES_Q_942___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_942___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_942___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_943 (0x005ECEBC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_943___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_943___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_943__RX_DCOC_RANGE_943___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_943__RX_DCOC_RES_I_943___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_943__RX_DCOC_RES_Q_943___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_943__RX_DCOC_RANGE_943___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_943__RX_DCOC_RANGE_943___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_943__RX_DCOC_RES_I_943___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_943__RX_DCOC_RES_I_943___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_943__RX_DCOC_RES_Q_943___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_943__RX_DCOC_RES_Q_943___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_943___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_943___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_944 (0x005ECEC0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_944___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_944___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_944__RX_DCOC_RANGE_944___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_944__RX_DCOC_RES_I_944___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_944__RX_DCOC_RES_Q_944___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_944__RX_DCOC_RANGE_944___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_944__RX_DCOC_RANGE_944___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_944__RX_DCOC_RES_I_944___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_944__RX_DCOC_RES_I_944___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_944__RX_DCOC_RES_Q_944___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_944__RX_DCOC_RES_Q_944___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_944___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_944___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_945 (0x005ECEC4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_945___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_945___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_945__RX_DCOC_RANGE_945___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_945__RX_DCOC_RES_I_945___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_945__RX_DCOC_RES_Q_945___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_945__RX_DCOC_RANGE_945___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_945__RX_DCOC_RANGE_945___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_945__RX_DCOC_RES_I_945___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_945__RX_DCOC_RES_I_945___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_945__RX_DCOC_RES_Q_945___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_945__RX_DCOC_RES_Q_945___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_945___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_945___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_946 (0x005ECEC8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_946___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_946___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_946__RX_DCOC_RANGE_946___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_946__RX_DCOC_RES_I_946___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_946__RX_DCOC_RES_Q_946___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_946__RX_DCOC_RANGE_946___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_946__RX_DCOC_RANGE_946___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_946__RX_DCOC_RES_I_946___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_946__RX_DCOC_RES_I_946___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_946__RX_DCOC_RES_Q_946___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_946__RX_DCOC_RES_Q_946___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_946___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_946___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_947 (0x005ECECC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_947___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_947___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_947__RX_DCOC_RANGE_947___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_947__RX_DCOC_RES_I_947___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_947__RX_DCOC_RES_Q_947___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_947__RX_DCOC_RANGE_947___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_947__RX_DCOC_RANGE_947___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_947__RX_DCOC_RES_I_947___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_947__RX_DCOC_RES_I_947___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_947__RX_DCOC_RES_Q_947___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_947__RX_DCOC_RES_Q_947___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_947___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_947___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_948 (0x005ECED0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_948___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_948___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_948__RX_DCOC_RANGE_948___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_948__RX_DCOC_RES_I_948___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_948__RX_DCOC_RES_Q_948___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_948__RX_DCOC_RANGE_948___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_948__RX_DCOC_RANGE_948___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_948__RX_DCOC_RES_I_948___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_948__RX_DCOC_RES_I_948___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_948__RX_DCOC_RES_Q_948___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_948__RX_DCOC_RES_Q_948___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_948___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_948___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_949 (0x005ECED4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_949___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_949___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_949__RX_DCOC_RANGE_949___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_949__RX_DCOC_RES_I_949___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_949__RX_DCOC_RES_Q_949___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_949__RX_DCOC_RANGE_949___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_949__RX_DCOC_RANGE_949___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_949__RX_DCOC_RES_I_949___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_949__RX_DCOC_RES_I_949___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_949__RX_DCOC_RES_Q_949___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_949__RX_DCOC_RES_Q_949___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_949___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_949___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_950 (0x005ECED8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_950___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_950___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_950__RX_DCOC_RANGE_950___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_950__RX_DCOC_RES_I_950___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_950__RX_DCOC_RES_Q_950___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_950__RX_DCOC_RANGE_950___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_950__RX_DCOC_RANGE_950___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_950__RX_DCOC_RES_I_950___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_950__RX_DCOC_RES_I_950___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_950__RX_DCOC_RES_Q_950___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_950__RX_DCOC_RES_Q_950___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_950___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_950___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_951 (0x005ECEDC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_951___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_951___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_951__RX_DCOC_RANGE_951___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_951__RX_DCOC_RES_I_951___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_951__RX_DCOC_RES_Q_951___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_951__RX_DCOC_RANGE_951___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_951__RX_DCOC_RANGE_951___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_951__RX_DCOC_RES_I_951___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_951__RX_DCOC_RES_I_951___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_951__RX_DCOC_RES_Q_951___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_951__RX_DCOC_RES_Q_951___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_951___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_951___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_952 (0x005ECEE0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_952___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_952___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_952__RX_DCOC_RANGE_952___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_952__RX_DCOC_RES_I_952___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_952__RX_DCOC_RES_Q_952___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_952__RX_DCOC_RANGE_952___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_952__RX_DCOC_RANGE_952___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_952__RX_DCOC_RES_I_952___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_952__RX_DCOC_RES_I_952___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_952__RX_DCOC_RES_Q_952___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_952__RX_DCOC_RES_Q_952___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_952___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_952___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_953 (0x005ECEE4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_953___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_953___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_953__RX_DCOC_RANGE_953___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_953__RX_DCOC_RES_I_953___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_953__RX_DCOC_RES_Q_953___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_953__RX_DCOC_RANGE_953___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_953__RX_DCOC_RANGE_953___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_953__RX_DCOC_RES_I_953___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_953__RX_DCOC_RES_I_953___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_953__RX_DCOC_RES_Q_953___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_953__RX_DCOC_RES_Q_953___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_953___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_953___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_954 (0x005ECEE8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_954___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_954___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_954__RX_DCOC_RANGE_954___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_954__RX_DCOC_RES_I_954___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_954__RX_DCOC_RES_Q_954___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_954__RX_DCOC_RANGE_954___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_954__RX_DCOC_RANGE_954___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_954__RX_DCOC_RES_I_954___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_954__RX_DCOC_RES_I_954___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_954__RX_DCOC_RES_Q_954___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_954__RX_DCOC_RES_Q_954___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_954___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_954___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_955 (0x005ECEEC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_955___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_955___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_955__RX_DCOC_RANGE_955___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_955__RX_DCOC_RES_I_955___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_955__RX_DCOC_RES_Q_955___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_955__RX_DCOC_RANGE_955___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_955__RX_DCOC_RANGE_955___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_955__RX_DCOC_RES_I_955___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_955__RX_DCOC_RES_I_955___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_955__RX_DCOC_RES_Q_955___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_955__RX_DCOC_RES_Q_955___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_955___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_955___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_956 (0x005ECEF0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_956___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_956___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_956__RX_DCOC_RANGE_956___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_956__RX_DCOC_RES_I_956___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_956__RX_DCOC_RES_Q_956___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_956__RX_DCOC_RANGE_956___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_956__RX_DCOC_RANGE_956___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_956__RX_DCOC_RES_I_956___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_956__RX_DCOC_RES_I_956___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_956__RX_DCOC_RES_Q_956___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_956__RX_DCOC_RES_Q_956___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_956___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_956___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_957 (0x005ECEF4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_957___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_957___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_957__RX_DCOC_RANGE_957___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_957__RX_DCOC_RES_I_957___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_957__RX_DCOC_RES_Q_957___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_957__RX_DCOC_RANGE_957___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_957__RX_DCOC_RANGE_957___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_957__RX_DCOC_RES_I_957___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_957__RX_DCOC_RES_I_957___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_957__RX_DCOC_RES_Q_957___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_957__RX_DCOC_RES_Q_957___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_957___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_957___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_958 (0x005ECEF8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_958___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_958___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_958__RX_DCOC_RANGE_958___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_958__RX_DCOC_RES_I_958___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_958__RX_DCOC_RES_Q_958___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_958__RX_DCOC_RANGE_958___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_958__RX_DCOC_RANGE_958___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_958__RX_DCOC_RES_I_958___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_958__RX_DCOC_RES_I_958___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_958__RX_DCOC_RES_Q_958___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_958__RX_DCOC_RES_Q_958___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_958___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_958___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_959 (0x005ECEFC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_959___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_959___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_959__RX_DCOC_RANGE_959___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_959__RX_DCOC_RES_I_959___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_959__RX_DCOC_RES_Q_959___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_959__RX_DCOC_RANGE_959___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_959__RX_DCOC_RANGE_959___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_959__RX_DCOC_RES_I_959___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_959__RX_DCOC_RES_I_959___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_959__RX_DCOC_RES_Q_959___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_959__RX_DCOC_RES_Q_959___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_959___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_959___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_960 (0x005ECF00) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_960___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_960___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_960__RX_DCOC_RANGE_960___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_960__RX_DCOC_RES_I_960___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_960__RX_DCOC_RES_Q_960___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_960__RX_DCOC_RANGE_960___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_960__RX_DCOC_RANGE_960___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_960__RX_DCOC_RES_I_960___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_960__RX_DCOC_RES_I_960___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_960__RX_DCOC_RES_Q_960___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_960__RX_DCOC_RES_Q_960___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_960___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_960___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_961 (0x005ECF04) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_961___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_961___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_961__RX_DCOC_RANGE_961___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_961__RX_DCOC_RES_I_961___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_961__RX_DCOC_RES_Q_961___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_961__RX_DCOC_RANGE_961___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_961__RX_DCOC_RANGE_961___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_961__RX_DCOC_RES_I_961___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_961__RX_DCOC_RES_I_961___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_961__RX_DCOC_RES_Q_961___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_961__RX_DCOC_RES_Q_961___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_961___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_961___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_962 (0x005ECF08) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_962___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_962___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_962__RX_DCOC_RANGE_962___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_962__RX_DCOC_RES_I_962___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_962__RX_DCOC_RES_Q_962___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_962__RX_DCOC_RANGE_962___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_962__RX_DCOC_RANGE_962___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_962__RX_DCOC_RES_I_962___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_962__RX_DCOC_RES_I_962___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_962__RX_DCOC_RES_Q_962___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_962__RX_DCOC_RES_Q_962___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_962___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_962___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_963 (0x005ECF0C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_963___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_963___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_963__RX_DCOC_RANGE_963___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_963__RX_DCOC_RES_I_963___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_963__RX_DCOC_RES_Q_963___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_963__RX_DCOC_RANGE_963___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_963__RX_DCOC_RANGE_963___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_963__RX_DCOC_RES_I_963___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_963__RX_DCOC_RES_I_963___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_963__RX_DCOC_RES_Q_963___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_963__RX_DCOC_RES_Q_963___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_963___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_963___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_964 (0x005ECF10) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_964___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_964___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_964__RX_DCOC_RANGE_964___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_964__RX_DCOC_RES_I_964___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_964__RX_DCOC_RES_Q_964___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_964__RX_DCOC_RANGE_964___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_964__RX_DCOC_RANGE_964___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_964__RX_DCOC_RES_I_964___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_964__RX_DCOC_RES_I_964___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_964__RX_DCOC_RES_Q_964___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_964__RX_DCOC_RES_Q_964___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_964___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_964___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_965 (0x005ECF14) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_965___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_965___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_965__RX_DCOC_RANGE_965___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_965__RX_DCOC_RES_I_965___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_965__RX_DCOC_RES_Q_965___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_965__RX_DCOC_RANGE_965___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_965__RX_DCOC_RANGE_965___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_965__RX_DCOC_RES_I_965___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_965__RX_DCOC_RES_I_965___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_965__RX_DCOC_RES_Q_965___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_965__RX_DCOC_RES_Q_965___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_965___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_965___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_966 (0x005ECF18) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_966___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_966___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_966__RX_DCOC_RANGE_966___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_966__RX_DCOC_RES_I_966___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_966__RX_DCOC_RES_Q_966___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_966__RX_DCOC_RANGE_966___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_966__RX_DCOC_RANGE_966___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_966__RX_DCOC_RES_I_966___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_966__RX_DCOC_RES_I_966___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_966__RX_DCOC_RES_Q_966___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_966__RX_DCOC_RES_Q_966___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_966___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_966___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_967 (0x005ECF1C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_967___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_967___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_967__RX_DCOC_RANGE_967___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_967__RX_DCOC_RES_I_967___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_967__RX_DCOC_RES_Q_967___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_967__RX_DCOC_RANGE_967___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_967__RX_DCOC_RANGE_967___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_967__RX_DCOC_RES_I_967___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_967__RX_DCOC_RES_I_967___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_967__RX_DCOC_RES_Q_967___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_967__RX_DCOC_RES_Q_967___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_967___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_967___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_968 (0x005ECF20) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_968___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_968___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_968__RX_DCOC_RANGE_968___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_968__RX_DCOC_RES_I_968___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_968__RX_DCOC_RES_Q_968___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_968__RX_DCOC_RANGE_968___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_968__RX_DCOC_RANGE_968___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_968__RX_DCOC_RES_I_968___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_968__RX_DCOC_RES_I_968___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_968__RX_DCOC_RES_Q_968___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_968__RX_DCOC_RES_Q_968___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_968___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_968___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_969 (0x005ECF24) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_969___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_969___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_969__RX_DCOC_RANGE_969___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_969__RX_DCOC_RES_I_969___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_969__RX_DCOC_RES_Q_969___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_969__RX_DCOC_RANGE_969___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_969__RX_DCOC_RANGE_969___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_969__RX_DCOC_RES_I_969___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_969__RX_DCOC_RES_I_969___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_969__RX_DCOC_RES_Q_969___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_969__RX_DCOC_RES_Q_969___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_969___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_969___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_970 (0x005ECF28) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_970___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_970___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_970__RX_DCOC_RANGE_970___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_970__RX_DCOC_RES_I_970___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_970__RX_DCOC_RES_Q_970___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_970__RX_DCOC_RANGE_970___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_970__RX_DCOC_RANGE_970___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_970__RX_DCOC_RES_I_970___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_970__RX_DCOC_RES_I_970___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_970__RX_DCOC_RES_Q_970___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_970__RX_DCOC_RES_Q_970___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_970___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_970___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_971 (0x005ECF2C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_971___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_971___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_971__RX_DCOC_RANGE_971___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_971__RX_DCOC_RES_I_971___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_971__RX_DCOC_RES_Q_971___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_971__RX_DCOC_RANGE_971___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_971__RX_DCOC_RANGE_971___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_971__RX_DCOC_RES_I_971___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_971__RX_DCOC_RES_I_971___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_971__RX_DCOC_RES_Q_971___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_971__RX_DCOC_RES_Q_971___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_971___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_971___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_972 (0x005ECF30) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_972___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_972___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_972__RX_DCOC_RANGE_972___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_972__RX_DCOC_RES_I_972___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_972__RX_DCOC_RES_Q_972___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_972__RX_DCOC_RANGE_972___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_972__RX_DCOC_RANGE_972___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_972__RX_DCOC_RES_I_972___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_972__RX_DCOC_RES_I_972___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_972__RX_DCOC_RES_Q_972___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_972__RX_DCOC_RES_Q_972___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_972___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_972___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_973 (0x005ECF34) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_973___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_973___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_973__RX_DCOC_RANGE_973___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_973__RX_DCOC_RES_I_973___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_973__RX_DCOC_RES_Q_973___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_973__RX_DCOC_RANGE_973___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_973__RX_DCOC_RANGE_973___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_973__RX_DCOC_RES_I_973___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_973__RX_DCOC_RES_I_973___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_973__RX_DCOC_RES_Q_973___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_973__RX_DCOC_RES_Q_973___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_973___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_973___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_974 (0x005ECF38) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_974___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_974___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_974__RX_DCOC_RANGE_974___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_974__RX_DCOC_RES_I_974___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_974__RX_DCOC_RES_Q_974___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_974__RX_DCOC_RANGE_974___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_974__RX_DCOC_RANGE_974___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_974__RX_DCOC_RES_I_974___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_974__RX_DCOC_RES_I_974___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_974__RX_DCOC_RES_Q_974___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_974__RX_DCOC_RES_Q_974___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_974___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_974___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_975 (0x005ECF3C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_975___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_975___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_975__RX_DCOC_RANGE_975___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_975__RX_DCOC_RES_I_975___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_975__RX_DCOC_RES_Q_975___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_975__RX_DCOC_RANGE_975___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_975__RX_DCOC_RANGE_975___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_975__RX_DCOC_RES_I_975___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_975__RX_DCOC_RES_I_975___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_975__RX_DCOC_RES_Q_975___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_975__RX_DCOC_RES_Q_975___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_975___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_975___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_976 (0x005ECF40) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_976___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_976___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_976__RX_DCOC_RANGE_976___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_976__RX_DCOC_RES_I_976___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_976__RX_DCOC_RES_Q_976___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_976__RX_DCOC_RANGE_976___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_976__RX_DCOC_RANGE_976___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_976__RX_DCOC_RES_I_976___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_976__RX_DCOC_RES_I_976___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_976__RX_DCOC_RES_Q_976___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_976__RX_DCOC_RES_Q_976___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_976___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_976___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_977 (0x005ECF44) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_977___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_977___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_977__RX_DCOC_RANGE_977___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_977__RX_DCOC_RES_I_977___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_977__RX_DCOC_RES_Q_977___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_977__RX_DCOC_RANGE_977___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_977__RX_DCOC_RANGE_977___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_977__RX_DCOC_RES_I_977___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_977__RX_DCOC_RES_I_977___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_977__RX_DCOC_RES_Q_977___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_977__RX_DCOC_RES_Q_977___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_977___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_977___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_978 (0x005ECF48) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_978___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_978___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_978__RX_DCOC_RANGE_978___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_978__RX_DCOC_RES_I_978___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_978__RX_DCOC_RES_Q_978___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_978__RX_DCOC_RANGE_978___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_978__RX_DCOC_RANGE_978___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_978__RX_DCOC_RES_I_978___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_978__RX_DCOC_RES_I_978___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_978__RX_DCOC_RES_Q_978___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_978__RX_DCOC_RES_Q_978___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_978___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_978___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_979 (0x005ECF4C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_979___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_979___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_979__RX_DCOC_RANGE_979___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_979__RX_DCOC_RES_I_979___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_979__RX_DCOC_RES_Q_979___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_979__RX_DCOC_RANGE_979___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_979__RX_DCOC_RANGE_979___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_979__RX_DCOC_RES_I_979___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_979__RX_DCOC_RES_I_979___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_979__RX_DCOC_RES_Q_979___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_979__RX_DCOC_RES_Q_979___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_979___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_979___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_980 (0x005ECF50) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_980___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_980___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_980__RX_DCOC_RANGE_980___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_980__RX_DCOC_RES_I_980___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_980__RX_DCOC_RES_Q_980___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_980__RX_DCOC_RANGE_980___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_980__RX_DCOC_RANGE_980___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_980__RX_DCOC_RES_I_980___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_980__RX_DCOC_RES_I_980___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_980__RX_DCOC_RES_Q_980___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_980__RX_DCOC_RES_Q_980___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_980___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_980___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_981 (0x005ECF54) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_981___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_981___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_981__RX_DCOC_RANGE_981___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_981__RX_DCOC_RES_I_981___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_981__RX_DCOC_RES_Q_981___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_981__RX_DCOC_RANGE_981___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_981__RX_DCOC_RANGE_981___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_981__RX_DCOC_RES_I_981___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_981__RX_DCOC_RES_I_981___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_981__RX_DCOC_RES_Q_981___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_981__RX_DCOC_RES_Q_981___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_981___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_981___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_982 (0x005ECF58) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_982___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_982___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_982__RX_DCOC_RANGE_982___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_982__RX_DCOC_RES_I_982___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_982__RX_DCOC_RES_Q_982___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_982__RX_DCOC_RANGE_982___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_982__RX_DCOC_RANGE_982___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_982__RX_DCOC_RES_I_982___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_982__RX_DCOC_RES_I_982___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_982__RX_DCOC_RES_Q_982___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_982__RX_DCOC_RES_Q_982___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_982___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_982___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_983 (0x005ECF5C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_983___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_983___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_983__RX_DCOC_RANGE_983___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_983__RX_DCOC_RES_I_983___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_983__RX_DCOC_RES_Q_983___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_983__RX_DCOC_RANGE_983___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_983__RX_DCOC_RANGE_983___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_983__RX_DCOC_RES_I_983___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_983__RX_DCOC_RES_I_983___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_983__RX_DCOC_RES_Q_983___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_983__RX_DCOC_RES_Q_983___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_983___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_983___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_984 (0x005ECF60) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_984___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_984___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_984__RX_DCOC_RANGE_984___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_984__RX_DCOC_RES_I_984___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_984__RX_DCOC_RES_Q_984___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_984__RX_DCOC_RANGE_984___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_984__RX_DCOC_RANGE_984___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_984__RX_DCOC_RES_I_984___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_984__RX_DCOC_RES_I_984___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_984__RX_DCOC_RES_Q_984___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_984__RX_DCOC_RES_Q_984___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_984___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_984___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_985 (0x005ECF64) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_985___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_985___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_985__RX_DCOC_RANGE_985___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_985__RX_DCOC_RES_I_985___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_985__RX_DCOC_RES_Q_985___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_985__RX_DCOC_RANGE_985___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_985__RX_DCOC_RANGE_985___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_985__RX_DCOC_RES_I_985___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_985__RX_DCOC_RES_I_985___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_985__RX_DCOC_RES_Q_985___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_985__RX_DCOC_RES_Q_985___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_985___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_985___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_986 (0x005ECF68) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_986___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_986___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_986__RX_DCOC_RANGE_986___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_986__RX_DCOC_RES_I_986___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_986__RX_DCOC_RES_Q_986___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_986__RX_DCOC_RANGE_986___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_986__RX_DCOC_RANGE_986___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_986__RX_DCOC_RES_I_986___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_986__RX_DCOC_RES_I_986___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_986__RX_DCOC_RES_Q_986___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_986__RX_DCOC_RES_Q_986___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_986___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_986___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_987 (0x005ECF6C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_987___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_987___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_987__RX_DCOC_RANGE_987___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_987__RX_DCOC_RES_I_987___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_987__RX_DCOC_RES_Q_987___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_987__RX_DCOC_RANGE_987___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_987__RX_DCOC_RANGE_987___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_987__RX_DCOC_RES_I_987___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_987__RX_DCOC_RES_I_987___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_987__RX_DCOC_RES_Q_987___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_987__RX_DCOC_RES_Q_987___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_987___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_987___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_988 (0x005ECF70) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_988___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_988___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_988__RX_DCOC_RANGE_988___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_988__RX_DCOC_RES_I_988___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_988__RX_DCOC_RES_Q_988___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_988__RX_DCOC_RANGE_988___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_988__RX_DCOC_RANGE_988___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_988__RX_DCOC_RES_I_988___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_988__RX_DCOC_RES_I_988___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_988__RX_DCOC_RES_Q_988___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_988__RX_DCOC_RES_Q_988___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_988___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_988___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_989 (0x005ECF74) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_989___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_989___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_989__RX_DCOC_RANGE_989___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_989__RX_DCOC_RES_I_989___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_989__RX_DCOC_RES_Q_989___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_989__RX_DCOC_RANGE_989___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_989__RX_DCOC_RANGE_989___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_989__RX_DCOC_RES_I_989___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_989__RX_DCOC_RES_I_989___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_989__RX_DCOC_RES_Q_989___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_989__RX_DCOC_RES_Q_989___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_989___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_989___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_990 (0x005ECF78) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_990___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_990___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_990__RX_DCOC_RANGE_990___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_990__RX_DCOC_RES_I_990___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_990__RX_DCOC_RES_Q_990___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_990__RX_DCOC_RANGE_990___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_990__RX_DCOC_RANGE_990___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_990__RX_DCOC_RES_I_990___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_990__RX_DCOC_RES_I_990___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_990__RX_DCOC_RES_Q_990___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_990__RX_DCOC_RES_Q_990___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_990___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_990___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_991 (0x005ECF7C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_991___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_991___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_991__RX_DCOC_RANGE_991___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_991__RX_DCOC_RES_I_991___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_991__RX_DCOC_RES_Q_991___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_991__RX_DCOC_RANGE_991___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_991__RX_DCOC_RANGE_991___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_991__RX_DCOC_RES_I_991___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_991__RX_DCOC_RES_I_991___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_991__RX_DCOC_RES_Q_991___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_991__RX_DCOC_RES_Q_991___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_991___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_991___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_992 (0x005ECF80) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_992___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_992___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_992__RX_DCOC_RANGE_992___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_992__RX_DCOC_RES_I_992___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_992__RX_DCOC_RES_Q_992___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_992__RX_DCOC_RANGE_992___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_992__RX_DCOC_RANGE_992___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_992__RX_DCOC_RES_I_992___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_992__RX_DCOC_RES_I_992___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_992__RX_DCOC_RES_Q_992___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_992__RX_DCOC_RES_Q_992___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_992___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_992___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_993 (0x005ECF84) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_993___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_993___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_993__RX_DCOC_RANGE_993___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_993__RX_DCOC_RES_I_993___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_993__RX_DCOC_RES_Q_993___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_993__RX_DCOC_RANGE_993___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_993__RX_DCOC_RANGE_993___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_993__RX_DCOC_RES_I_993___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_993__RX_DCOC_RES_I_993___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_993__RX_DCOC_RES_Q_993___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_993__RX_DCOC_RES_Q_993___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_993___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_993___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_994 (0x005ECF88) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_994___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_994___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_994__RX_DCOC_RANGE_994___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_994__RX_DCOC_RES_I_994___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_994__RX_DCOC_RES_Q_994___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_994__RX_DCOC_RANGE_994___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_994__RX_DCOC_RANGE_994___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_994__RX_DCOC_RES_I_994___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_994__RX_DCOC_RES_I_994___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_994__RX_DCOC_RES_Q_994___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_994__RX_DCOC_RES_Q_994___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_994___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_994___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_995 (0x005ECF8C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_995___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_995___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_995__RX_DCOC_RANGE_995___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_995__RX_DCOC_RES_I_995___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_995__RX_DCOC_RES_Q_995___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_995__RX_DCOC_RANGE_995___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_995__RX_DCOC_RANGE_995___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_995__RX_DCOC_RES_I_995___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_995__RX_DCOC_RES_I_995___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_995__RX_DCOC_RES_Q_995___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_995__RX_DCOC_RES_Q_995___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_995___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_995___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_996 (0x005ECF90) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_996___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_996___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_996__RX_DCOC_RANGE_996___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_996__RX_DCOC_RES_I_996___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_996__RX_DCOC_RES_Q_996___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_996__RX_DCOC_RANGE_996___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_996__RX_DCOC_RANGE_996___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_996__RX_DCOC_RES_I_996___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_996__RX_DCOC_RES_I_996___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_996__RX_DCOC_RES_Q_996___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_996__RX_DCOC_RES_Q_996___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_996___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_996___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_997 (0x005ECF94) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_997___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_997___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_997__RX_DCOC_RANGE_997___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_997__RX_DCOC_RES_I_997___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_997__RX_DCOC_RES_Q_997___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_997__RX_DCOC_RANGE_997___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_997__RX_DCOC_RANGE_997___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_997__RX_DCOC_RES_I_997___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_997__RX_DCOC_RES_I_997___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_997__RX_DCOC_RES_Q_997___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_997__RX_DCOC_RES_Q_997___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_997___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_997___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_998 (0x005ECF98) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_998___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_998___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_998__RX_DCOC_RANGE_998___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_998__RX_DCOC_RES_I_998___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_998__RX_DCOC_RES_Q_998___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_998__RX_DCOC_RANGE_998___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_998__RX_DCOC_RANGE_998___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_998__RX_DCOC_RES_I_998___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_998__RX_DCOC_RES_I_998___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_998__RX_DCOC_RES_Q_998___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_998__RX_DCOC_RES_Q_998___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_998___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_998___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_999 (0x005ECF9C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_999___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_999___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_999__RX_DCOC_RANGE_999___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_999__RX_DCOC_RES_I_999___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_999__RX_DCOC_RES_Q_999___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_999__RX_DCOC_RANGE_999___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_999__RX_DCOC_RANGE_999___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_999__RX_DCOC_RES_I_999___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_999__RX_DCOC_RES_I_999___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_999__RX_DCOC_RES_Q_999___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_999__RX_DCOC_RES_Q_999___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_999___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_999___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1000 (0x005ECFA0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1000___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1000___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1000__RX_DCOC_RANGE_1000___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1000__RX_DCOC_RES_I_1000___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1000__RX_DCOC_RES_Q_1000___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1000__RX_DCOC_RANGE_1000___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1000__RX_DCOC_RANGE_1000___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1000__RX_DCOC_RES_I_1000___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1000__RX_DCOC_RES_I_1000___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1000__RX_DCOC_RES_Q_1000___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1000__RX_DCOC_RES_Q_1000___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1000___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1000___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1001 (0x005ECFA4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1001___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1001___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1001__RX_DCOC_RANGE_1001___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1001__RX_DCOC_RES_I_1001___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1001__RX_DCOC_RES_Q_1001___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1001__RX_DCOC_RANGE_1001___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1001__RX_DCOC_RANGE_1001___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1001__RX_DCOC_RES_I_1001___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1001__RX_DCOC_RES_I_1001___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1001__RX_DCOC_RES_Q_1001___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1001__RX_DCOC_RES_Q_1001___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1001___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1001___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1002 (0x005ECFA8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1002___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1002___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1002__RX_DCOC_RANGE_1002___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1002__RX_DCOC_RES_I_1002___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1002__RX_DCOC_RES_Q_1002___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1002__RX_DCOC_RANGE_1002___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1002__RX_DCOC_RANGE_1002___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1002__RX_DCOC_RES_I_1002___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1002__RX_DCOC_RES_I_1002___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1002__RX_DCOC_RES_Q_1002___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1002__RX_DCOC_RES_Q_1002___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1002___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1002___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1003 (0x005ECFAC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1003___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1003___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1003__RX_DCOC_RANGE_1003___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1003__RX_DCOC_RES_I_1003___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1003__RX_DCOC_RES_Q_1003___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1003__RX_DCOC_RANGE_1003___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1003__RX_DCOC_RANGE_1003___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1003__RX_DCOC_RES_I_1003___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1003__RX_DCOC_RES_I_1003___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1003__RX_DCOC_RES_Q_1003___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1003__RX_DCOC_RES_Q_1003___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1003___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1003___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1004 (0x005ECFB0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1004___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1004___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1004__RX_DCOC_RANGE_1004___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1004__RX_DCOC_RES_I_1004___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1004__RX_DCOC_RES_Q_1004___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1004__RX_DCOC_RANGE_1004___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1004__RX_DCOC_RANGE_1004___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1004__RX_DCOC_RES_I_1004___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1004__RX_DCOC_RES_I_1004___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1004__RX_DCOC_RES_Q_1004___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1004__RX_DCOC_RES_Q_1004___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1004___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1004___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1005 (0x005ECFB4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1005___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1005___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1005__RX_DCOC_RANGE_1005___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1005__RX_DCOC_RES_I_1005___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1005__RX_DCOC_RES_Q_1005___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1005__RX_DCOC_RANGE_1005___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1005__RX_DCOC_RANGE_1005___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1005__RX_DCOC_RES_I_1005___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1005__RX_DCOC_RES_I_1005___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1005__RX_DCOC_RES_Q_1005___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1005__RX_DCOC_RES_Q_1005___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1005___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1005___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1006 (0x005ECFB8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1006___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1006___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1006__RX_DCOC_RANGE_1006___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1006__RX_DCOC_RES_I_1006___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1006__RX_DCOC_RES_Q_1006___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1006__RX_DCOC_RANGE_1006___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1006__RX_DCOC_RANGE_1006___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1006__RX_DCOC_RES_I_1006___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1006__RX_DCOC_RES_I_1006___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1006__RX_DCOC_RES_Q_1006___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1006__RX_DCOC_RES_Q_1006___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1006___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1006___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1007 (0x005ECFBC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1007___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1007___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1007__RX_DCOC_RANGE_1007___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1007__RX_DCOC_RES_I_1007___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1007__RX_DCOC_RES_Q_1007___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1007__RX_DCOC_RANGE_1007___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1007__RX_DCOC_RANGE_1007___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1007__RX_DCOC_RES_I_1007___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1007__RX_DCOC_RES_I_1007___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1007__RX_DCOC_RES_Q_1007___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1007__RX_DCOC_RES_Q_1007___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1007___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1007___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1008 (0x005ECFC0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1008___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1008___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1008__RX_DCOC_RANGE_1008___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1008__RX_DCOC_RES_I_1008___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1008__RX_DCOC_RES_Q_1008___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1008__RX_DCOC_RANGE_1008___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1008__RX_DCOC_RANGE_1008___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1008__RX_DCOC_RES_I_1008___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1008__RX_DCOC_RES_I_1008___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1008__RX_DCOC_RES_Q_1008___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1008__RX_DCOC_RES_Q_1008___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1008___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1008___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1009 (0x005ECFC4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1009___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1009___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1009__RX_DCOC_RANGE_1009___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1009__RX_DCOC_RES_I_1009___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1009__RX_DCOC_RES_Q_1009___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1009__RX_DCOC_RANGE_1009___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1009__RX_DCOC_RANGE_1009___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1009__RX_DCOC_RES_I_1009___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1009__RX_DCOC_RES_I_1009___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1009__RX_DCOC_RES_Q_1009___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1009__RX_DCOC_RES_Q_1009___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1009___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1009___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1010 (0x005ECFC8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1010___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1010___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1010__RX_DCOC_RANGE_1010___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1010__RX_DCOC_RES_I_1010___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1010__RX_DCOC_RES_Q_1010___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1010__RX_DCOC_RANGE_1010___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1010__RX_DCOC_RANGE_1010___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1010__RX_DCOC_RES_I_1010___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1010__RX_DCOC_RES_I_1010___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1010__RX_DCOC_RES_Q_1010___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1010__RX_DCOC_RES_Q_1010___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1010___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1010___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1011 (0x005ECFCC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1011___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1011___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1011__RX_DCOC_RANGE_1011___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1011__RX_DCOC_RES_I_1011___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1011__RX_DCOC_RES_Q_1011___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1011__RX_DCOC_RANGE_1011___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1011__RX_DCOC_RANGE_1011___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1011__RX_DCOC_RES_I_1011___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1011__RX_DCOC_RES_I_1011___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1011__RX_DCOC_RES_Q_1011___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1011__RX_DCOC_RES_Q_1011___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1011___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1011___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1012 (0x005ECFD0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1012___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1012___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1012__RX_DCOC_RANGE_1012___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1012__RX_DCOC_RES_I_1012___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1012__RX_DCOC_RES_Q_1012___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1012__RX_DCOC_RANGE_1012___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1012__RX_DCOC_RANGE_1012___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1012__RX_DCOC_RES_I_1012___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1012__RX_DCOC_RES_I_1012___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1012__RX_DCOC_RES_Q_1012___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1012__RX_DCOC_RES_Q_1012___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1012___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1012___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1013 (0x005ECFD4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1013___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1013___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1013__RX_DCOC_RANGE_1013___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1013__RX_DCOC_RES_I_1013___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1013__RX_DCOC_RES_Q_1013___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1013__RX_DCOC_RANGE_1013___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1013__RX_DCOC_RANGE_1013___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1013__RX_DCOC_RES_I_1013___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1013__RX_DCOC_RES_I_1013___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1013__RX_DCOC_RES_Q_1013___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1013__RX_DCOC_RES_Q_1013___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1013___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1013___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1014 (0x005ECFD8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1014___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1014___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1014__RX_DCOC_RANGE_1014___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1014__RX_DCOC_RES_I_1014___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1014__RX_DCOC_RES_Q_1014___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1014__RX_DCOC_RANGE_1014___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1014__RX_DCOC_RANGE_1014___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1014__RX_DCOC_RES_I_1014___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1014__RX_DCOC_RES_I_1014___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1014__RX_DCOC_RES_Q_1014___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1014__RX_DCOC_RES_Q_1014___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1014___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1014___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1015 (0x005ECFDC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1015___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1015___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1015__RX_DCOC_RANGE_1015___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1015__RX_DCOC_RES_I_1015___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1015__RX_DCOC_RES_Q_1015___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1015__RX_DCOC_RANGE_1015___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1015__RX_DCOC_RANGE_1015___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1015__RX_DCOC_RES_I_1015___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1015__RX_DCOC_RES_I_1015___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1015__RX_DCOC_RES_Q_1015___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1015__RX_DCOC_RES_Q_1015___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1015___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1015___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1016 (0x005ECFE0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1016___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1016___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1016__RX_DCOC_RANGE_1016___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1016__RX_DCOC_RES_I_1016___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1016__RX_DCOC_RES_Q_1016___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1016__RX_DCOC_RANGE_1016___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1016__RX_DCOC_RANGE_1016___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1016__RX_DCOC_RES_I_1016___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1016__RX_DCOC_RES_I_1016___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1016__RX_DCOC_RES_Q_1016___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1016__RX_DCOC_RES_Q_1016___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1016___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1016___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1017 (0x005ECFE4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1017___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1017___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1017__RX_DCOC_RANGE_1017___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1017__RX_DCOC_RES_I_1017___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1017__RX_DCOC_RES_Q_1017___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1017__RX_DCOC_RANGE_1017___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1017__RX_DCOC_RANGE_1017___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1017__RX_DCOC_RES_I_1017___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1017__RX_DCOC_RES_I_1017___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1017__RX_DCOC_RES_Q_1017___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1017__RX_DCOC_RES_Q_1017___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1017___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1017___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1018 (0x005ECFE8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1018___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1018___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1018__RX_DCOC_RANGE_1018___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1018__RX_DCOC_RES_I_1018___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1018__RX_DCOC_RES_Q_1018___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1018__RX_DCOC_RANGE_1018___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1018__RX_DCOC_RANGE_1018___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1018__RX_DCOC_RES_I_1018___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1018__RX_DCOC_RES_I_1018___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1018__RX_DCOC_RES_Q_1018___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1018__RX_DCOC_RES_Q_1018___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1018___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1018___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1019 (0x005ECFEC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1019___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1019___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1019__RX_DCOC_RANGE_1019___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1019__RX_DCOC_RES_I_1019___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1019__RX_DCOC_RES_Q_1019___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1019__RX_DCOC_RANGE_1019___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1019__RX_DCOC_RANGE_1019___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1019__RX_DCOC_RES_I_1019___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1019__RX_DCOC_RES_I_1019___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1019__RX_DCOC_RES_Q_1019___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1019__RX_DCOC_RES_Q_1019___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1019___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1019___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1020 (0x005ECFF0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1020___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1020___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1020__RX_DCOC_RANGE_1020___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1020__RX_DCOC_RES_I_1020___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1020__RX_DCOC_RES_Q_1020___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1020__RX_DCOC_RANGE_1020___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1020__RX_DCOC_RANGE_1020___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1020__RX_DCOC_RES_I_1020___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1020__RX_DCOC_RES_I_1020___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1020__RX_DCOC_RES_Q_1020___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1020__RX_DCOC_RES_Q_1020___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1020___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1020___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1021 (0x005ECFF4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1021___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1021___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1021__RX_DCOC_RANGE_1021___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1021__RX_DCOC_RES_I_1021___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1021__RX_DCOC_RES_Q_1021___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1021__RX_DCOC_RANGE_1021___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1021__RX_DCOC_RANGE_1021___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1021__RX_DCOC_RES_I_1021___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1021__RX_DCOC_RES_I_1021___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1021__RX_DCOC_RES_Q_1021___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1021__RX_DCOC_RES_Q_1021___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1021___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1021___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1022 (0x005ECFF8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1022___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1022___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1022__RX_DCOC_RANGE_1022___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1022__RX_DCOC_RES_I_1022___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1022__RX_DCOC_RES_Q_1022___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1022__RX_DCOC_RANGE_1022___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1022__RX_DCOC_RANGE_1022___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1022__RX_DCOC_RES_I_1022___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1022__RX_DCOC_RES_I_1022___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1022__RX_DCOC_RES_Q_1022___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1022__RX_DCOC_RES_Q_1022___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1022___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1022___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1023 (0x005ECFFC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1023___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1023___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1023__RX_DCOC_RANGE_1023___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1023__RX_DCOC_RES_I_1023___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1023__RX_DCOC_RES_Q_1023___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1023__RX_DCOC_RANGE_1023___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1023__RX_DCOC_RANGE_1023___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1023__RX_DCOC_RES_I_1023___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1023__RX_DCOC_RES_I_1023___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1023__RX_DCOC_RES_Q_1023___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1023__RX_DCOC_RES_Q_1023___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1023___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXDCOC_1023___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0 (0x005ED000) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__XLNA_GAIN_ODD_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__LNA_GAIN_ODD_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__GM_GAIN_ODD_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__TIA_GAIN_ODD_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__SLM_XLNA_ODD_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__BQ_GAIN_ODD_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__XLNA_GAIN_EVEN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__LNA_GAIN_EVEN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__GM_GAIN_EVEN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__TIA_GAIN_EVEN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__SLM_XLNA_EVEN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__BQ_GAIN_EVEN_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__XLNA_GAIN_ODD_0___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__XLNA_GAIN_ODD_0___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__LNA_GAIN_ODD_0___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__LNA_GAIN_ODD_0___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__GM_GAIN_ODD_0___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__GM_GAIN_ODD_0___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__TIA_GAIN_ODD_0___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__TIA_GAIN_ODD_0___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__SLM_XLNA_ODD_0___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__SLM_XLNA_ODD_0___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__BQ_GAIN_ODD_0___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__BQ_GAIN_ODD_0___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__XLNA_GAIN_EVEN_0___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__XLNA_GAIN_EVEN_0___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__LNA_GAIN_EVEN_0___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__LNA_GAIN_EVEN_0___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__GM_GAIN_EVEN_0___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__GM_GAIN_EVEN_0___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__TIA_GAIN_EVEN_0___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__TIA_GAIN_EVEN_0___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__SLM_XLNA_EVEN_0___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__SLM_XLNA_EVEN_0___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__BQ_GAIN_EVEN_0___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0__BQ_GAIN_EVEN_0___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1 (0x005ED004) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__XLNA_GAIN_ODD_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__LNA_GAIN_ODD_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__GM_GAIN_ODD_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__TIA_GAIN_ODD_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__SLM_XLNA_ODD_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__BQ_GAIN_ODD_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__XLNA_GAIN_EVEN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__LNA_GAIN_EVEN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__GM_GAIN_EVEN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__TIA_GAIN_EVEN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__SLM_XLNA_EVEN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__BQ_GAIN_EVEN_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__XLNA_GAIN_ODD_1___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__XLNA_GAIN_ODD_1___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__LNA_GAIN_ODD_1___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__LNA_GAIN_ODD_1___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__GM_GAIN_ODD_1___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__GM_GAIN_ODD_1___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__TIA_GAIN_ODD_1___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__TIA_GAIN_ODD_1___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__SLM_XLNA_ODD_1___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__SLM_XLNA_ODD_1___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__BQ_GAIN_ODD_1___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__BQ_GAIN_ODD_1___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__XLNA_GAIN_EVEN_1___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__XLNA_GAIN_EVEN_1___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__LNA_GAIN_EVEN_1___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__LNA_GAIN_EVEN_1___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__GM_GAIN_EVEN_1___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__GM_GAIN_EVEN_1___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__TIA_GAIN_EVEN_1___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__TIA_GAIN_EVEN_1___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__SLM_XLNA_EVEN_1___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__SLM_XLNA_EVEN_1___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__BQ_GAIN_EVEN_1___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1__BQ_GAIN_EVEN_1___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2 (0x005ED008) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__XLNA_GAIN_ODD_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__LNA_GAIN_ODD_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__GM_GAIN_ODD_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__TIA_GAIN_ODD_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__SLM_XLNA_ODD_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__BQ_GAIN_ODD_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__XLNA_GAIN_EVEN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__LNA_GAIN_EVEN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__GM_GAIN_EVEN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__TIA_GAIN_EVEN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__SLM_XLNA_EVEN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__BQ_GAIN_EVEN_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__XLNA_GAIN_ODD_2___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__XLNA_GAIN_ODD_2___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__LNA_GAIN_ODD_2___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__LNA_GAIN_ODD_2___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__GM_GAIN_ODD_2___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__GM_GAIN_ODD_2___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__TIA_GAIN_ODD_2___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__TIA_GAIN_ODD_2___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__SLM_XLNA_ODD_2___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__SLM_XLNA_ODD_2___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__BQ_GAIN_ODD_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__BQ_GAIN_ODD_2___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__XLNA_GAIN_EVEN_2___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__XLNA_GAIN_EVEN_2___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__LNA_GAIN_EVEN_2___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__LNA_GAIN_EVEN_2___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__GM_GAIN_EVEN_2___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__GM_GAIN_EVEN_2___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__TIA_GAIN_EVEN_2___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__TIA_GAIN_EVEN_2___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__SLM_XLNA_EVEN_2___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__SLM_XLNA_EVEN_2___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__BQ_GAIN_EVEN_2___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2__BQ_GAIN_EVEN_2___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_2___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3 (0x005ED00C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__XLNA_GAIN_ODD_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__LNA_GAIN_ODD_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__GM_GAIN_ODD_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__TIA_GAIN_ODD_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__SLM_XLNA_ODD_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__BQ_GAIN_ODD_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__XLNA_GAIN_EVEN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__LNA_GAIN_EVEN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__GM_GAIN_EVEN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__TIA_GAIN_EVEN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__SLM_XLNA_EVEN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__BQ_GAIN_EVEN_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__XLNA_GAIN_ODD_3___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__XLNA_GAIN_ODD_3___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__LNA_GAIN_ODD_3___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__LNA_GAIN_ODD_3___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__GM_GAIN_ODD_3___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__GM_GAIN_ODD_3___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__TIA_GAIN_ODD_3___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__TIA_GAIN_ODD_3___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__SLM_XLNA_ODD_3___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__SLM_XLNA_ODD_3___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__BQ_GAIN_ODD_3___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__BQ_GAIN_ODD_3___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__XLNA_GAIN_EVEN_3___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__XLNA_GAIN_EVEN_3___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__LNA_GAIN_EVEN_3___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__LNA_GAIN_EVEN_3___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__GM_GAIN_EVEN_3___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__GM_GAIN_EVEN_3___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__TIA_GAIN_EVEN_3___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__TIA_GAIN_EVEN_3___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__SLM_XLNA_EVEN_3___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__SLM_XLNA_EVEN_3___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__BQ_GAIN_EVEN_3___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3__BQ_GAIN_EVEN_3___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_3___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4 (0x005ED010) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__XLNA_GAIN_ODD_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__LNA_GAIN_ODD_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__GM_GAIN_ODD_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__TIA_GAIN_ODD_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__SLM_XLNA_ODD_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__BQ_GAIN_ODD_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__XLNA_GAIN_EVEN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__LNA_GAIN_EVEN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__GM_GAIN_EVEN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__TIA_GAIN_EVEN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__SLM_XLNA_EVEN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__BQ_GAIN_EVEN_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__XLNA_GAIN_ODD_4___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__XLNA_GAIN_ODD_4___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__LNA_GAIN_ODD_4___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__LNA_GAIN_ODD_4___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__GM_GAIN_ODD_4___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__GM_GAIN_ODD_4___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__TIA_GAIN_ODD_4___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__TIA_GAIN_ODD_4___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__SLM_XLNA_ODD_4___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__SLM_XLNA_ODD_4___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__BQ_GAIN_ODD_4___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__BQ_GAIN_ODD_4___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__XLNA_GAIN_EVEN_4___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__XLNA_GAIN_EVEN_4___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__LNA_GAIN_EVEN_4___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__LNA_GAIN_EVEN_4___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__GM_GAIN_EVEN_4___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__GM_GAIN_EVEN_4___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__TIA_GAIN_EVEN_4___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__TIA_GAIN_EVEN_4___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__SLM_XLNA_EVEN_4___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__SLM_XLNA_EVEN_4___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__BQ_GAIN_EVEN_4___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4__BQ_GAIN_EVEN_4___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_4___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5 (0x005ED014) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__XLNA_GAIN_ODD_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__LNA_GAIN_ODD_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__GM_GAIN_ODD_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__TIA_GAIN_ODD_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__SLM_XLNA_ODD_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__BQ_GAIN_ODD_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__XLNA_GAIN_EVEN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__LNA_GAIN_EVEN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__GM_GAIN_EVEN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__TIA_GAIN_EVEN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__SLM_XLNA_EVEN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__BQ_GAIN_EVEN_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__XLNA_GAIN_ODD_5___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__XLNA_GAIN_ODD_5___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__LNA_GAIN_ODD_5___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__LNA_GAIN_ODD_5___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__GM_GAIN_ODD_5___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__GM_GAIN_ODD_5___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__TIA_GAIN_ODD_5___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__TIA_GAIN_ODD_5___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__SLM_XLNA_ODD_5___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__SLM_XLNA_ODD_5___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__BQ_GAIN_ODD_5___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__BQ_GAIN_ODD_5___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__XLNA_GAIN_EVEN_5___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__XLNA_GAIN_EVEN_5___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__LNA_GAIN_EVEN_5___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__LNA_GAIN_EVEN_5___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__GM_GAIN_EVEN_5___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__GM_GAIN_EVEN_5___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__TIA_GAIN_EVEN_5___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__TIA_GAIN_EVEN_5___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__SLM_XLNA_EVEN_5___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__SLM_XLNA_EVEN_5___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__BQ_GAIN_EVEN_5___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5__BQ_GAIN_EVEN_5___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_5___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6 (0x005ED018) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__XLNA_GAIN_ODD_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__LNA_GAIN_ODD_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__GM_GAIN_ODD_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__TIA_GAIN_ODD_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__SLM_XLNA_ODD_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__BQ_GAIN_ODD_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__XLNA_GAIN_EVEN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__LNA_GAIN_EVEN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__GM_GAIN_EVEN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__TIA_GAIN_EVEN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__SLM_XLNA_EVEN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__BQ_GAIN_EVEN_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__XLNA_GAIN_ODD_6___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__XLNA_GAIN_ODD_6___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__LNA_GAIN_ODD_6___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__LNA_GAIN_ODD_6___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__GM_GAIN_ODD_6___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__GM_GAIN_ODD_6___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__TIA_GAIN_ODD_6___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__TIA_GAIN_ODD_6___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__SLM_XLNA_ODD_6___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__SLM_XLNA_ODD_6___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__BQ_GAIN_ODD_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__BQ_GAIN_ODD_6___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__XLNA_GAIN_EVEN_6___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__XLNA_GAIN_EVEN_6___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__LNA_GAIN_EVEN_6___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__LNA_GAIN_EVEN_6___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__GM_GAIN_EVEN_6___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__GM_GAIN_EVEN_6___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__TIA_GAIN_EVEN_6___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__TIA_GAIN_EVEN_6___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__SLM_XLNA_EVEN_6___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__SLM_XLNA_EVEN_6___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__BQ_GAIN_EVEN_6___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6__BQ_GAIN_EVEN_6___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_6___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7 (0x005ED01C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__XLNA_GAIN_ODD_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__LNA_GAIN_ODD_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__GM_GAIN_ODD_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__TIA_GAIN_ODD_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__SLM_XLNA_ODD_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__BQ_GAIN_ODD_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__XLNA_GAIN_EVEN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__LNA_GAIN_EVEN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__GM_GAIN_EVEN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__TIA_GAIN_EVEN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__SLM_XLNA_EVEN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__BQ_GAIN_EVEN_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__XLNA_GAIN_ODD_7___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__XLNA_GAIN_ODD_7___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__LNA_GAIN_ODD_7___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__LNA_GAIN_ODD_7___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__GM_GAIN_ODD_7___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__GM_GAIN_ODD_7___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__TIA_GAIN_ODD_7___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__TIA_GAIN_ODD_7___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__SLM_XLNA_ODD_7___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__SLM_XLNA_ODD_7___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__BQ_GAIN_ODD_7___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__BQ_GAIN_ODD_7___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__XLNA_GAIN_EVEN_7___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__XLNA_GAIN_EVEN_7___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__LNA_GAIN_EVEN_7___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__LNA_GAIN_EVEN_7___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__GM_GAIN_EVEN_7___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__GM_GAIN_EVEN_7___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__TIA_GAIN_EVEN_7___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__TIA_GAIN_EVEN_7___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__SLM_XLNA_EVEN_7___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__SLM_XLNA_EVEN_7___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__BQ_GAIN_EVEN_7___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7__BQ_GAIN_EVEN_7___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_7___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8 (0x005ED020) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__XLNA_GAIN_ODD_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__LNA_GAIN_ODD_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__GM_GAIN_ODD_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__TIA_GAIN_ODD_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__SLM_XLNA_ODD_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__BQ_GAIN_ODD_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__XLNA_GAIN_EVEN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__LNA_GAIN_EVEN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__GM_GAIN_EVEN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__TIA_GAIN_EVEN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__SLM_XLNA_EVEN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__BQ_GAIN_EVEN_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__XLNA_GAIN_ODD_8___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__XLNA_GAIN_ODD_8___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__LNA_GAIN_ODD_8___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__LNA_GAIN_ODD_8___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__GM_GAIN_ODD_8___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__GM_GAIN_ODD_8___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__TIA_GAIN_ODD_8___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__TIA_GAIN_ODD_8___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__SLM_XLNA_ODD_8___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__SLM_XLNA_ODD_8___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__BQ_GAIN_ODD_8___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__BQ_GAIN_ODD_8___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__XLNA_GAIN_EVEN_8___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__XLNA_GAIN_EVEN_8___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__LNA_GAIN_EVEN_8___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__LNA_GAIN_EVEN_8___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__GM_GAIN_EVEN_8___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__GM_GAIN_EVEN_8___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__TIA_GAIN_EVEN_8___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__TIA_GAIN_EVEN_8___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__SLM_XLNA_EVEN_8___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__SLM_XLNA_EVEN_8___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__BQ_GAIN_EVEN_8___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8__BQ_GAIN_EVEN_8___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_8___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9 (0x005ED024) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__XLNA_GAIN_ODD_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__LNA_GAIN_ODD_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__GM_GAIN_ODD_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__TIA_GAIN_ODD_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__SLM_XLNA_ODD_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__BQ_GAIN_ODD_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__XLNA_GAIN_EVEN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__LNA_GAIN_EVEN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__GM_GAIN_EVEN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__TIA_GAIN_EVEN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__SLM_XLNA_EVEN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__BQ_GAIN_EVEN_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__XLNA_GAIN_ODD_9___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__XLNA_GAIN_ODD_9___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__LNA_GAIN_ODD_9___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__LNA_GAIN_ODD_9___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__GM_GAIN_ODD_9___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__GM_GAIN_ODD_9___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__TIA_GAIN_ODD_9___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__TIA_GAIN_ODD_9___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__SLM_XLNA_ODD_9___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__SLM_XLNA_ODD_9___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__BQ_GAIN_ODD_9___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__BQ_GAIN_ODD_9___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__XLNA_GAIN_EVEN_9___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__XLNA_GAIN_EVEN_9___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__LNA_GAIN_EVEN_9___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__LNA_GAIN_EVEN_9___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__GM_GAIN_EVEN_9___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__GM_GAIN_EVEN_9___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__TIA_GAIN_EVEN_9___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__TIA_GAIN_EVEN_9___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__SLM_XLNA_EVEN_9___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__SLM_XLNA_EVEN_9___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__BQ_GAIN_EVEN_9___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9__BQ_GAIN_EVEN_9___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_9___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10 (0x005ED028) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__XLNA_GAIN_ODD_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__LNA_GAIN_ODD_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__GM_GAIN_ODD_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__TIA_GAIN_ODD_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__SLM_XLNA_ODD_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__BQ_GAIN_ODD_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__XLNA_GAIN_EVEN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__LNA_GAIN_EVEN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__GM_GAIN_EVEN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__TIA_GAIN_EVEN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__SLM_XLNA_EVEN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__BQ_GAIN_EVEN_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__XLNA_GAIN_ODD_10___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__XLNA_GAIN_ODD_10___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__LNA_GAIN_ODD_10___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__LNA_GAIN_ODD_10___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__GM_GAIN_ODD_10___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__GM_GAIN_ODD_10___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__TIA_GAIN_ODD_10___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__TIA_GAIN_ODD_10___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__SLM_XLNA_ODD_10___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__SLM_XLNA_ODD_10___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__BQ_GAIN_ODD_10___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__BQ_GAIN_ODD_10___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__XLNA_GAIN_EVEN_10___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__XLNA_GAIN_EVEN_10___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__LNA_GAIN_EVEN_10___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__LNA_GAIN_EVEN_10___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__GM_GAIN_EVEN_10___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__GM_GAIN_EVEN_10___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__TIA_GAIN_EVEN_10___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__TIA_GAIN_EVEN_10___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__SLM_XLNA_EVEN_10___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__SLM_XLNA_EVEN_10___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__BQ_GAIN_EVEN_10___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10__BQ_GAIN_EVEN_10___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_10___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11 (0x005ED02C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__XLNA_GAIN_ODD_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__LNA_GAIN_ODD_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__GM_GAIN_ODD_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__TIA_GAIN_ODD_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__SLM_XLNA_ODD_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__BQ_GAIN_ODD_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__XLNA_GAIN_EVEN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__LNA_GAIN_EVEN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__GM_GAIN_EVEN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__TIA_GAIN_EVEN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__SLM_XLNA_EVEN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__BQ_GAIN_EVEN_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__XLNA_GAIN_ODD_11___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__XLNA_GAIN_ODD_11___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__LNA_GAIN_ODD_11___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__LNA_GAIN_ODD_11___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__GM_GAIN_ODD_11___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__GM_GAIN_ODD_11___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__TIA_GAIN_ODD_11___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__TIA_GAIN_ODD_11___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__SLM_XLNA_ODD_11___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__SLM_XLNA_ODD_11___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__BQ_GAIN_ODD_11___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__BQ_GAIN_ODD_11___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__XLNA_GAIN_EVEN_11___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__XLNA_GAIN_EVEN_11___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__LNA_GAIN_EVEN_11___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__LNA_GAIN_EVEN_11___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__GM_GAIN_EVEN_11___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__GM_GAIN_EVEN_11___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__TIA_GAIN_EVEN_11___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__TIA_GAIN_EVEN_11___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__SLM_XLNA_EVEN_11___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__SLM_XLNA_EVEN_11___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__BQ_GAIN_EVEN_11___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11__BQ_GAIN_EVEN_11___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_11___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12 (0x005ED030) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__XLNA_GAIN_ODD_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__LNA_GAIN_ODD_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__GM_GAIN_ODD_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__TIA_GAIN_ODD_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__SLM_XLNA_ODD_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__BQ_GAIN_ODD_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__XLNA_GAIN_EVEN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__LNA_GAIN_EVEN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__GM_GAIN_EVEN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__TIA_GAIN_EVEN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__SLM_XLNA_EVEN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__BQ_GAIN_EVEN_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__XLNA_GAIN_ODD_12___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__XLNA_GAIN_ODD_12___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__LNA_GAIN_ODD_12___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__LNA_GAIN_ODD_12___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__GM_GAIN_ODD_12___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__GM_GAIN_ODD_12___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__TIA_GAIN_ODD_12___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__TIA_GAIN_ODD_12___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__SLM_XLNA_ODD_12___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__SLM_XLNA_ODD_12___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__BQ_GAIN_ODD_12___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__BQ_GAIN_ODD_12___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__XLNA_GAIN_EVEN_12___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__XLNA_GAIN_EVEN_12___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__LNA_GAIN_EVEN_12___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__LNA_GAIN_EVEN_12___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__GM_GAIN_EVEN_12___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__GM_GAIN_EVEN_12___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__TIA_GAIN_EVEN_12___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__TIA_GAIN_EVEN_12___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__SLM_XLNA_EVEN_12___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__SLM_XLNA_EVEN_12___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__BQ_GAIN_EVEN_12___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12__BQ_GAIN_EVEN_12___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_12___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13 (0x005ED034) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__XLNA_GAIN_ODD_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__LNA_GAIN_ODD_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__GM_GAIN_ODD_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__TIA_GAIN_ODD_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__SLM_XLNA_ODD_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__BQ_GAIN_ODD_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__XLNA_GAIN_EVEN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__LNA_GAIN_EVEN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__GM_GAIN_EVEN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__TIA_GAIN_EVEN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__SLM_XLNA_EVEN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__BQ_GAIN_EVEN_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__XLNA_GAIN_ODD_13___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__XLNA_GAIN_ODD_13___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__LNA_GAIN_ODD_13___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__LNA_GAIN_ODD_13___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__GM_GAIN_ODD_13___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__GM_GAIN_ODD_13___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__TIA_GAIN_ODD_13___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__TIA_GAIN_ODD_13___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__SLM_XLNA_ODD_13___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__SLM_XLNA_ODD_13___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__BQ_GAIN_ODD_13___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__BQ_GAIN_ODD_13___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__XLNA_GAIN_EVEN_13___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__XLNA_GAIN_EVEN_13___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__LNA_GAIN_EVEN_13___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__LNA_GAIN_EVEN_13___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__GM_GAIN_EVEN_13___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__GM_GAIN_EVEN_13___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__TIA_GAIN_EVEN_13___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__TIA_GAIN_EVEN_13___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__SLM_XLNA_EVEN_13___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__SLM_XLNA_EVEN_13___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__BQ_GAIN_EVEN_13___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13__BQ_GAIN_EVEN_13___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_13___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14 (0x005ED038) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__XLNA_GAIN_ODD_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__LNA_GAIN_ODD_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__GM_GAIN_ODD_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__TIA_GAIN_ODD_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__SLM_XLNA_ODD_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__BQ_GAIN_ODD_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__XLNA_GAIN_EVEN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__LNA_GAIN_EVEN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__GM_GAIN_EVEN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__TIA_GAIN_EVEN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__SLM_XLNA_EVEN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__BQ_GAIN_EVEN_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__XLNA_GAIN_ODD_14___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__XLNA_GAIN_ODD_14___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__LNA_GAIN_ODD_14___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__LNA_GAIN_ODD_14___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__GM_GAIN_ODD_14___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__GM_GAIN_ODD_14___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__TIA_GAIN_ODD_14___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__TIA_GAIN_ODD_14___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__SLM_XLNA_ODD_14___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__SLM_XLNA_ODD_14___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__BQ_GAIN_ODD_14___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__BQ_GAIN_ODD_14___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__XLNA_GAIN_EVEN_14___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__XLNA_GAIN_EVEN_14___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__LNA_GAIN_EVEN_14___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__LNA_GAIN_EVEN_14___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__GM_GAIN_EVEN_14___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__GM_GAIN_EVEN_14___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__TIA_GAIN_EVEN_14___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__TIA_GAIN_EVEN_14___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__SLM_XLNA_EVEN_14___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__SLM_XLNA_EVEN_14___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__BQ_GAIN_EVEN_14___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14__BQ_GAIN_EVEN_14___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_14___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15 (0x005ED03C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__XLNA_GAIN_ODD_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__LNA_GAIN_ODD_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__GM_GAIN_ODD_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__TIA_GAIN_ODD_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__SLM_XLNA_ODD_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__BQ_GAIN_ODD_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__XLNA_GAIN_EVEN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__LNA_GAIN_EVEN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__GM_GAIN_EVEN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__TIA_GAIN_EVEN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__SLM_XLNA_EVEN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__BQ_GAIN_EVEN_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__XLNA_GAIN_ODD_15___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__XLNA_GAIN_ODD_15___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__LNA_GAIN_ODD_15___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__LNA_GAIN_ODD_15___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__GM_GAIN_ODD_15___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__GM_GAIN_ODD_15___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__TIA_GAIN_ODD_15___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__TIA_GAIN_ODD_15___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__SLM_XLNA_ODD_15___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__SLM_XLNA_ODD_15___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__BQ_GAIN_ODD_15___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__BQ_GAIN_ODD_15___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__XLNA_GAIN_EVEN_15___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__XLNA_GAIN_EVEN_15___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__LNA_GAIN_EVEN_15___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__LNA_GAIN_EVEN_15___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__GM_GAIN_EVEN_15___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__GM_GAIN_EVEN_15___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__TIA_GAIN_EVEN_15___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__TIA_GAIN_EVEN_15___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__SLM_XLNA_EVEN_15___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__SLM_XLNA_EVEN_15___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__BQ_GAIN_EVEN_15___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15__BQ_GAIN_EVEN_15___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_15___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16 (0x005ED040) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__XLNA_GAIN_ODD_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__LNA_GAIN_ODD_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__GM_GAIN_ODD_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__TIA_GAIN_ODD_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__SLM_XLNA_ODD_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__BQ_GAIN_ODD_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__XLNA_GAIN_EVEN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__LNA_GAIN_EVEN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__GM_GAIN_EVEN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__TIA_GAIN_EVEN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__SLM_XLNA_EVEN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__BQ_GAIN_EVEN_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__XLNA_GAIN_ODD_16___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__XLNA_GAIN_ODD_16___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__LNA_GAIN_ODD_16___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__LNA_GAIN_ODD_16___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__GM_GAIN_ODD_16___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__GM_GAIN_ODD_16___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__TIA_GAIN_ODD_16___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__TIA_GAIN_ODD_16___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__SLM_XLNA_ODD_16___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__SLM_XLNA_ODD_16___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__BQ_GAIN_ODD_16___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__BQ_GAIN_ODD_16___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__XLNA_GAIN_EVEN_16___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__XLNA_GAIN_EVEN_16___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__LNA_GAIN_EVEN_16___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__LNA_GAIN_EVEN_16___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__GM_GAIN_EVEN_16___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__GM_GAIN_EVEN_16___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__TIA_GAIN_EVEN_16___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__TIA_GAIN_EVEN_16___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__SLM_XLNA_EVEN_16___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__SLM_XLNA_EVEN_16___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__BQ_GAIN_EVEN_16___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16__BQ_GAIN_EVEN_16___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_16___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17 (0x005ED044) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__XLNA_GAIN_ODD_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__LNA_GAIN_ODD_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__GM_GAIN_ODD_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__TIA_GAIN_ODD_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__SLM_XLNA_ODD_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__BQ_GAIN_ODD_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__XLNA_GAIN_EVEN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__LNA_GAIN_EVEN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__GM_GAIN_EVEN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__TIA_GAIN_EVEN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__SLM_XLNA_EVEN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__BQ_GAIN_EVEN_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__XLNA_GAIN_ODD_17___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__XLNA_GAIN_ODD_17___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__LNA_GAIN_ODD_17___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__LNA_GAIN_ODD_17___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__GM_GAIN_ODD_17___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__GM_GAIN_ODD_17___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__TIA_GAIN_ODD_17___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__TIA_GAIN_ODD_17___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__SLM_XLNA_ODD_17___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__SLM_XLNA_ODD_17___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__BQ_GAIN_ODD_17___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__BQ_GAIN_ODD_17___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__XLNA_GAIN_EVEN_17___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__XLNA_GAIN_EVEN_17___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__LNA_GAIN_EVEN_17___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__LNA_GAIN_EVEN_17___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__GM_GAIN_EVEN_17___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__GM_GAIN_EVEN_17___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__TIA_GAIN_EVEN_17___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__TIA_GAIN_EVEN_17___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__SLM_XLNA_EVEN_17___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__SLM_XLNA_EVEN_17___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__BQ_GAIN_EVEN_17___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17__BQ_GAIN_EVEN_17___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_17___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18 (0x005ED048) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__XLNA_GAIN_ODD_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__LNA_GAIN_ODD_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__GM_GAIN_ODD_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__TIA_GAIN_ODD_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__SLM_XLNA_ODD_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__BQ_GAIN_ODD_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__XLNA_GAIN_EVEN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__LNA_GAIN_EVEN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__GM_GAIN_EVEN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__TIA_GAIN_EVEN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__SLM_XLNA_EVEN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__BQ_GAIN_EVEN_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__XLNA_GAIN_ODD_18___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__XLNA_GAIN_ODD_18___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__LNA_GAIN_ODD_18___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__LNA_GAIN_ODD_18___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__GM_GAIN_ODD_18___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__GM_GAIN_ODD_18___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__TIA_GAIN_ODD_18___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__TIA_GAIN_ODD_18___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__SLM_XLNA_ODD_18___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__SLM_XLNA_ODD_18___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__BQ_GAIN_ODD_18___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__BQ_GAIN_ODD_18___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__XLNA_GAIN_EVEN_18___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__XLNA_GAIN_EVEN_18___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__LNA_GAIN_EVEN_18___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__LNA_GAIN_EVEN_18___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__GM_GAIN_EVEN_18___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__GM_GAIN_EVEN_18___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__TIA_GAIN_EVEN_18___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__TIA_GAIN_EVEN_18___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__SLM_XLNA_EVEN_18___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__SLM_XLNA_EVEN_18___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__BQ_GAIN_EVEN_18___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18__BQ_GAIN_EVEN_18___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_18___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19 (0x005ED04C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__XLNA_GAIN_ODD_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__LNA_GAIN_ODD_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__GM_GAIN_ODD_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__TIA_GAIN_ODD_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__SLM_XLNA_ODD_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__BQ_GAIN_ODD_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__XLNA_GAIN_EVEN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__LNA_GAIN_EVEN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__GM_GAIN_EVEN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__TIA_GAIN_EVEN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__SLM_XLNA_EVEN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__BQ_GAIN_EVEN_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__XLNA_GAIN_ODD_19___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__XLNA_GAIN_ODD_19___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__LNA_GAIN_ODD_19___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__LNA_GAIN_ODD_19___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__GM_GAIN_ODD_19___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__GM_GAIN_ODD_19___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__TIA_GAIN_ODD_19___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__TIA_GAIN_ODD_19___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__SLM_XLNA_ODD_19___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__SLM_XLNA_ODD_19___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__BQ_GAIN_ODD_19___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__BQ_GAIN_ODD_19___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__XLNA_GAIN_EVEN_19___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__XLNA_GAIN_EVEN_19___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__LNA_GAIN_EVEN_19___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__LNA_GAIN_EVEN_19___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__GM_GAIN_EVEN_19___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__GM_GAIN_EVEN_19___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__TIA_GAIN_EVEN_19___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__TIA_GAIN_EVEN_19___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__SLM_XLNA_EVEN_19___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__SLM_XLNA_EVEN_19___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__BQ_GAIN_EVEN_19___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19__BQ_GAIN_EVEN_19___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_19___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20 (0x005ED050) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__XLNA_GAIN_ODD_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__LNA_GAIN_ODD_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__GM_GAIN_ODD_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__TIA_GAIN_ODD_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__SLM_XLNA_ODD_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__BQ_GAIN_ODD_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__XLNA_GAIN_EVEN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__LNA_GAIN_EVEN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__GM_GAIN_EVEN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__TIA_GAIN_EVEN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__SLM_XLNA_EVEN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__BQ_GAIN_EVEN_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__XLNA_GAIN_ODD_20___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__XLNA_GAIN_ODD_20___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__LNA_GAIN_ODD_20___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__LNA_GAIN_ODD_20___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__GM_GAIN_ODD_20___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__GM_GAIN_ODD_20___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__TIA_GAIN_ODD_20___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__TIA_GAIN_ODD_20___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__SLM_XLNA_ODD_20___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__SLM_XLNA_ODD_20___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__BQ_GAIN_ODD_20___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__BQ_GAIN_ODD_20___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__XLNA_GAIN_EVEN_20___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__XLNA_GAIN_EVEN_20___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__LNA_GAIN_EVEN_20___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__LNA_GAIN_EVEN_20___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__GM_GAIN_EVEN_20___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__GM_GAIN_EVEN_20___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__TIA_GAIN_EVEN_20___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__TIA_GAIN_EVEN_20___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__SLM_XLNA_EVEN_20___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__SLM_XLNA_EVEN_20___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__BQ_GAIN_EVEN_20___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20__BQ_GAIN_EVEN_20___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_20___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21 (0x005ED054) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__XLNA_GAIN_ODD_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__LNA_GAIN_ODD_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__GM_GAIN_ODD_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__TIA_GAIN_ODD_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__SLM_XLNA_ODD_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__BQ_GAIN_ODD_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__XLNA_GAIN_EVEN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__LNA_GAIN_EVEN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__GM_GAIN_EVEN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__TIA_GAIN_EVEN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__SLM_XLNA_EVEN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__BQ_GAIN_EVEN_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__XLNA_GAIN_ODD_21___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__XLNA_GAIN_ODD_21___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__LNA_GAIN_ODD_21___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__LNA_GAIN_ODD_21___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__GM_GAIN_ODD_21___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__GM_GAIN_ODD_21___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__TIA_GAIN_ODD_21___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__TIA_GAIN_ODD_21___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__SLM_XLNA_ODD_21___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__SLM_XLNA_ODD_21___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__BQ_GAIN_ODD_21___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__BQ_GAIN_ODD_21___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__XLNA_GAIN_EVEN_21___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__XLNA_GAIN_EVEN_21___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__LNA_GAIN_EVEN_21___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__LNA_GAIN_EVEN_21___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__GM_GAIN_EVEN_21___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__GM_GAIN_EVEN_21___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__TIA_GAIN_EVEN_21___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__TIA_GAIN_EVEN_21___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__SLM_XLNA_EVEN_21___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__SLM_XLNA_EVEN_21___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__BQ_GAIN_EVEN_21___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21__BQ_GAIN_EVEN_21___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_21___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22 (0x005ED058) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__XLNA_GAIN_ODD_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__LNA_GAIN_ODD_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__GM_GAIN_ODD_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__TIA_GAIN_ODD_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__SLM_XLNA_ODD_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__BQ_GAIN_ODD_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__XLNA_GAIN_EVEN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__LNA_GAIN_EVEN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__GM_GAIN_EVEN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__TIA_GAIN_EVEN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__SLM_XLNA_EVEN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__BQ_GAIN_EVEN_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__XLNA_GAIN_ODD_22___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__XLNA_GAIN_ODD_22___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__LNA_GAIN_ODD_22___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__LNA_GAIN_ODD_22___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__GM_GAIN_ODD_22___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__GM_GAIN_ODD_22___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__TIA_GAIN_ODD_22___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__TIA_GAIN_ODD_22___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__SLM_XLNA_ODD_22___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__SLM_XLNA_ODD_22___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__BQ_GAIN_ODD_22___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__BQ_GAIN_ODD_22___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__XLNA_GAIN_EVEN_22___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__XLNA_GAIN_EVEN_22___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__LNA_GAIN_EVEN_22___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__LNA_GAIN_EVEN_22___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__GM_GAIN_EVEN_22___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__GM_GAIN_EVEN_22___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__TIA_GAIN_EVEN_22___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__TIA_GAIN_EVEN_22___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__SLM_XLNA_EVEN_22___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__SLM_XLNA_EVEN_22___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__BQ_GAIN_EVEN_22___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22__BQ_GAIN_EVEN_22___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_22___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23 (0x005ED05C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__XLNA_GAIN_ODD_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__LNA_GAIN_ODD_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__GM_GAIN_ODD_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__TIA_GAIN_ODD_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__SLM_XLNA_ODD_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__BQ_GAIN_ODD_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__XLNA_GAIN_EVEN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__LNA_GAIN_EVEN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__GM_GAIN_EVEN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__TIA_GAIN_EVEN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__SLM_XLNA_EVEN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__BQ_GAIN_EVEN_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__XLNA_GAIN_ODD_23___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__XLNA_GAIN_ODD_23___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__LNA_GAIN_ODD_23___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__LNA_GAIN_ODD_23___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__GM_GAIN_ODD_23___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__GM_GAIN_ODD_23___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__TIA_GAIN_ODD_23___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__TIA_GAIN_ODD_23___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__SLM_XLNA_ODD_23___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__SLM_XLNA_ODD_23___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__BQ_GAIN_ODD_23___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__BQ_GAIN_ODD_23___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__XLNA_GAIN_EVEN_23___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__XLNA_GAIN_EVEN_23___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__LNA_GAIN_EVEN_23___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__LNA_GAIN_EVEN_23___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__GM_GAIN_EVEN_23___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__GM_GAIN_EVEN_23___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__TIA_GAIN_EVEN_23___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__TIA_GAIN_EVEN_23___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__SLM_XLNA_EVEN_23___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__SLM_XLNA_EVEN_23___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__BQ_GAIN_EVEN_23___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23__BQ_GAIN_EVEN_23___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_23___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24 (0x005ED060) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__XLNA_GAIN_ODD_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__LNA_GAIN_ODD_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__GM_GAIN_ODD_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__TIA_GAIN_ODD_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__SLM_XLNA_ODD_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__BQ_GAIN_ODD_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__XLNA_GAIN_EVEN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__LNA_GAIN_EVEN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__GM_GAIN_EVEN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__TIA_GAIN_EVEN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__SLM_XLNA_EVEN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__BQ_GAIN_EVEN_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__XLNA_GAIN_ODD_24___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__XLNA_GAIN_ODD_24___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__LNA_GAIN_ODD_24___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__LNA_GAIN_ODD_24___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__GM_GAIN_ODD_24___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__GM_GAIN_ODD_24___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__TIA_GAIN_ODD_24___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__TIA_GAIN_ODD_24___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__SLM_XLNA_ODD_24___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__SLM_XLNA_ODD_24___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__BQ_GAIN_ODD_24___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__BQ_GAIN_ODD_24___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__XLNA_GAIN_EVEN_24___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__XLNA_GAIN_EVEN_24___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__LNA_GAIN_EVEN_24___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__LNA_GAIN_EVEN_24___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__GM_GAIN_EVEN_24___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__GM_GAIN_EVEN_24___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__TIA_GAIN_EVEN_24___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__TIA_GAIN_EVEN_24___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__SLM_XLNA_EVEN_24___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__SLM_XLNA_EVEN_24___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__BQ_GAIN_EVEN_24___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24__BQ_GAIN_EVEN_24___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_24___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25 (0x005ED064) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__XLNA_GAIN_ODD_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__LNA_GAIN_ODD_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__GM_GAIN_ODD_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__TIA_GAIN_ODD_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__SLM_XLNA_ODD_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__BQ_GAIN_ODD_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__XLNA_GAIN_EVEN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__LNA_GAIN_EVEN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__GM_GAIN_EVEN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__TIA_GAIN_EVEN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__SLM_XLNA_EVEN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__BQ_GAIN_EVEN_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__XLNA_GAIN_ODD_25___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__XLNA_GAIN_ODD_25___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__LNA_GAIN_ODD_25___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__LNA_GAIN_ODD_25___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__GM_GAIN_ODD_25___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__GM_GAIN_ODD_25___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__TIA_GAIN_ODD_25___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__TIA_GAIN_ODD_25___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__SLM_XLNA_ODD_25___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__SLM_XLNA_ODD_25___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__BQ_GAIN_ODD_25___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__BQ_GAIN_ODD_25___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__XLNA_GAIN_EVEN_25___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__XLNA_GAIN_EVEN_25___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__LNA_GAIN_EVEN_25___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__LNA_GAIN_EVEN_25___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__GM_GAIN_EVEN_25___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__GM_GAIN_EVEN_25___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__TIA_GAIN_EVEN_25___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__TIA_GAIN_EVEN_25___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__SLM_XLNA_EVEN_25___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__SLM_XLNA_EVEN_25___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__BQ_GAIN_EVEN_25___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25__BQ_GAIN_EVEN_25___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_25___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26 (0x005ED068) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__XLNA_GAIN_ODD_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__LNA_GAIN_ODD_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__GM_GAIN_ODD_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__TIA_GAIN_ODD_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__SLM_XLNA_ODD_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__BQ_GAIN_ODD_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__XLNA_GAIN_EVEN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__LNA_GAIN_EVEN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__GM_GAIN_EVEN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__TIA_GAIN_EVEN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__SLM_XLNA_EVEN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__BQ_GAIN_EVEN_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__XLNA_GAIN_ODD_26___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__XLNA_GAIN_ODD_26___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__LNA_GAIN_ODD_26___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__LNA_GAIN_ODD_26___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__GM_GAIN_ODD_26___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__GM_GAIN_ODD_26___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__TIA_GAIN_ODD_26___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__TIA_GAIN_ODD_26___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__SLM_XLNA_ODD_26___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__SLM_XLNA_ODD_26___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__BQ_GAIN_ODD_26___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__BQ_GAIN_ODD_26___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__XLNA_GAIN_EVEN_26___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__XLNA_GAIN_EVEN_26___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__LNA_GAIN_EVEN_26___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__LNA_GAIN_EVEN_26___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__GM_GAIN_EVEN_26___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__GM_GAIN_EVEN_26___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__TIA_GAIN_EVEN_26___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__TIA_GAIN_EVEN_26___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__SLM_XLNA_EVEN_26___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__SLM_XLNA_EVEN_26___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__BQ_GAIN_EVEN_26___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26__BQ_GAIN_EVEN_26___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_26___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27 (0x005ED06C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__XLNA_GAIN_ODD_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__LNA_GAIN_ODD_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__GM_GAIN_ODD_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__TIA_GAIN_ODD_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__SLM_XLNA_ODD_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__BQ_GAIN_ODD_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__XLNA_GAIN_EVEN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__LNA_GAIN_EVEN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__GM_GAIN_EVEN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__TIA_GAIN_EVEN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__SLM_XLNA_EVEN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__BQ_GAIN_EVEN_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__XLNA_GAIN_ODD_27___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__XLNA_GAIN_ODD_27___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__LNA_GAIN_ODD_27___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__LNA_GAIN_ODD_27___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__GM_GAIN_ODD_27___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__GM_GAIN_ODD_27___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__TIA_GAIN_ODD_27___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__TIA_GAIN_ODD_27___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__SLM_XLNA_ODD_27___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__SLM_XLNA_ODD_27___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__BQ_GAIN_ODD_27___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__BQ_GAIN_ODD_27___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__XLNA_GAIN_EVEN_27___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__XLNA_GAIN_EVEN_27___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__LNA_GAIN_EVEN_27___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__LNA_GAIN_EVEN_27___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__GM_GAIN_EVEN_27___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__GM_GAIN_EVEN_27___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__TIA_GAIN_EVEN_27___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__TIA_GAIN_EVEN_27___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__SLM_XLNA_EVEN_27___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__SLM_XLNA_EVEN_27___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__BQ_GAIN_EVEN_27___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27__BQ_GAIN_EVEN_27___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_27___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28 (0x005ED070) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__XLNA_GAIN_ODD_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__LNA_GAIN_ODD_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__GM_GAIN_ODD_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__TIA_GAIN_ODD_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__SLM_XLNA_ODD_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__BQ_GAIN_ODD_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__XLNA_GAIN_EVEN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__LNA_GAIN_EVEN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__GM_GAIN_EVEN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__TIA_GAIN_EVEN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__SLM_XLNA_EVEN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__BQ_GAIN_EVEN_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__XLNA_GAIN_ODD_28___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__XLNA_GAIN_ODD_28___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__LNA_GAIN_ODD_28___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__LNA_GAIN_ODD_28___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__GM_GAIN_ODD_28___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__GM_GAIN_ODD_28___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__TIA_GAIN_ODD_28___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__TIA_GAIN_ODD_28___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__SLM_XLNA_ODD_28___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__SLM_XLNA_ODD_28___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__BQ_GAIN_ODD_28___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__BQ_GAIN_ODD_28___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__XLNA_GAIN_EVEN_28___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__XLNA_GAIN_EVEN_28___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__LNA_GAIN_EVEN_28___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__LNA_GAIN_EVEN_28___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__GM_GAIN_EVEN_28___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__GM_GAIN_EVEN_28___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__TIA_GAIN_EVEN_28___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__TIA_GAIN_EVEN_28___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__SLM_XLNA_EVEN_28___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__SLM_XLNA_EVEN_28___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__BQ_GAIN_EVEN_28___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28__BQ_GAIN_EVEN_28___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_28___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29 (0x005ED074) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__XLNA_GAIN_ODD_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__LNA_GAIN_ODD_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__GM_GAIN_ODD_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__TIA_GAIN_ODD_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__SLM_XLNA_ODD_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__BQ_GAIN_ODD_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__XLNA_GAIN_EVEN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__LNA_GAIN_EVEN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__GM_GAIN_EVEN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__TIA_GAIN_EVEN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__SLM_XLNA_EVEN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__BQ_GAIN_EVEN_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__XLNA_GAIN_ODD_29___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__XLNA_GAIN_ODD_29___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__LNA_GAIN_ODD_29___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__LNA_GAIN_ODD_29___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__GM_GAIN_ODD_29___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__GM_GAIN_ODD_29___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__TIA_GAIN_ODD_29___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__TIA_GAIN_ODD_29___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__SLM_XLNA_ODD_29___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__SLM_XLNA_ODD_29___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__BQ_GAIN_ODD_29___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__BQ_GAIN_ODD_29___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__XLNA_GAIN_EVEN_29___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__XLNA_GAIN_EVEN_29___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__LNA_GAIN_EVEN_29___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__LNA_GAIN_EVEN_29___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__GM_GAIN_EVEN_29___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__GM_GAIN_EVEN_29___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__TIA_GAIN_EVEN_29___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__TIA_GAIN_EVEN_29___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__SLM_XLNA_EVEN_29___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__SLM_XLNA_EVEN_29___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__BQ_GAIN_EVEN_29___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29__BQ_GAIN_EVEN_29___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_29___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30 (0x005ED078) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__XLNA_GAIN_ODD_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__LNA_GAIN_ODD_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__GM_GAIN_ODD_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__TIA_GAIN_ODD_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__SLM_XLNA_ODD_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__BQ_GAIN_ODD_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__XLNA_GAIN_EVEN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__LNA_GAIN_EVEN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__GM_GAIN_EVEN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__TIA_GAIN_EVEN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__SLM_XLNA_EVEN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__BQ_GAIN_EVEN_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__XLNA_GAIN_ODD_30___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__XLNA_GAIN_ODD_30___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__LNA_GAIN_ODD_30___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__LNA_GAIN_ODD_30___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__GM_GAIN_ODD_30___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__GM_GAIN_ODD_30___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__TIA_GAIN_ODD_30___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__TIA_GAIN_ODD_30___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__SLM_XLNA_ODD_30___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__SLM_XLNA_ODD_30___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__BQ_GAIN_ODD_30___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__BQ_GAIN_ODD_30___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__XLNA_GAIN_EVEN_30___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__XLNA_GAIN_EVEN_30___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__LNA_GAIN_EVEN_30___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__LNA_GAIN_EVEN_30___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__GM_GAIN_EVEN_30___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__GM_GAIN_EVEN_30___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__TIA_GAIN_EVEN_30___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__TIA_GAIN_EVEN_30___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__SLM_XLNA_EVEN_30___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__SLM_XLNA_EVEN_30___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__BQ_GAIN_EVEN_30___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30__BQ_GAIN_EVEN_30___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_30___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31 (0x005ED07C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__XLNA_GAIN_ODD_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__LNA_GAIN_ODD_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__GM_GAIN_ODD_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__TIA_GAIN_ODD_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__SLM_XLNA_ODD_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__BQ_GAIN_ODD_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__XLNA_GAIN_EVEN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__LNA_GAIN_EVEN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__GM_GAIN_EVEN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__TIA_GAIN_EVEN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__SLM_XLNA_EVEN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__BQ_GAIN_EVEN_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__XLNA_GAIN_ODD_31___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__XLNA_GAIN_ODD_31___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__LNA_GAIN_ODD_31___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__LNA_GAIN_ODD_31___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__GM_GAIN_ODD_31___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__GM_GAIN_ODD_31___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__TIA_GAIN_ODD_31___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__TIA_GAIN_ODD_31___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__SLM_XLNA_ODD_31___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__SLM_XLNA_ODD_31___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__BQ_GAIN_ODD_31___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__BQ_GAIN_ODD_31___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__XLNA_GAIN_EVEN_31___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__XLNA_GAIN_EVEN_31___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__LNA_GAIN_EVEN_31___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__LNA_GAIN_EVEN_31___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__GM_GAIN_EVEN_31___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__GM_GAIN_EVEN_31___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__TIA_GAIN_EVEN_31___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__TIA_GAIN_EVEN_31___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__SLM_XLNA_EVEN_31___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__SLM_XLNA_EVEN_31___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__BQ_GAIN_EVEN_31___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31__BQ_GAIN_EVEN_31___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_31___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32 (0x005ED080) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__XLNA_GAIN_ODD_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__LNA_GAIN_ODD_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__GM_GAIN_ODD_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__TIA_GAIN_ODD_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__SLM_XLNA_ODD_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__BQ_GAIN_ODD_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__XLNA_GAIN_EVEN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__LNA_GAIN_EVEN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__GM_GAIN_EVEN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__TIA_GAIN_EVEN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__SLM_XLNA_EVEN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__BQ_GAIN_EVEN_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__XLNA_GAIN_ODD_32___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__XLNA_GAIN_ODD_32___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__LNA_GAIN_ODD_32___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__LNA_GAIN_ODD_32___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__GM_GAIN_ODD_32___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__GM_GAIN_ODD_32___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__TIA_GAIN_ODD_32___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__TIA_GAIN_ODD_32___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__SLM_XLNA_ODD_32___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__SLM_XLNA_ODD_32___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__BQ_GAIN_ODD_32___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__BQ_GAIN_ODD_32___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__XLNA_GAIN_EVEN_32___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__XLNA_GAIN_EVEN_32___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__LNA_GAIN_EVEN_32___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__LNA_GAIN_EVEN_32___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__GM_GAIN_EVEN_32___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__GM_GAIN_EVEN_32___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__TIA_GAIN_EVEN_32___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__TIA_GAIN_EVEN_32___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__SLM_XLNA_EVEN_32___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__SLM_XLNA_EVEN_32___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__BQ_GAIN_EVEN_32___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32__BQ_GAIN_EVEN_32___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_32___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33 (0x005ED084) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__XLNA_GAIN_ODD_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__LNA_GAIN_ODD_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__GM_GAIN_ODD_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__TIA_GAIN_ODD_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__SLM_XLNA_ODD_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__BQ_GAIN_ODD_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__XLNA_GAIN_EVEN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__LNA_GAIN_EVEN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__GM_GAIN_EVEN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__TIA_GAIN_EVEN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__SLM_XLNA_EVEN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__BQ_GAIN_EVEN_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__XLNA_GAIN_ODD_33___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__XLNA_GAIN_ODD_33___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__LNA_GAIN_ODD_33___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__LNA_GAIN_ODD_33___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__GM_GAIN_ODD_33___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__GM_GAIN_ODD_33___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__TIA_GAIN_ODD_33___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__TIA_GAIN_ODD_33___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__SLM_XLNA_ODD_33___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__SLM_XLNA_ODD_33___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__BQ_GAIN_ODD_33___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__BQ_GAIN_ODD_33___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__XLNA_GAIN_EVEN_33___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__XLNA_GAIN_EVEN_33___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__LNA_GAIN_EVEN_33___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__LNA_GAIN_EVEN_33___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__GM_GAIN_EVEN_33___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__GM_GAIN_EVEN_33___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__TIA_GAIN_EVEN_33___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__TIA_GAIN_EVEN_33___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__SLM_XLNA_EVEN_33___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__SLM_XLNA_EVEN_33___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__BQ_GAIN_EVEN_33___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33__BQ_GAIN_EVEN_33___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_33___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34 (0x005ED088) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__XLNA_GAIN_ODD_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__LNA_GAIN_ODD_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__GM_GAIN_ODD_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__TIA_GAIN_ODD_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__SLM_XLNA_ODD_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__BQ_GAIN_ODD_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__XLNA_GAIN_EVEN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__LNA_GAIN_EVEN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__GM_GAIN_EVEN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__TIA_GAIN_EVEN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__SLM_XLNA_EVEN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__BQ_GAIN_EVEN_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__XLNA_GAIN_ODD_34___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__XLNA_GAIN_ODD_34___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__LNA_GAIN_ODD_34___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__LNA_GAIN_ODD_34___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__GM_GAIN_ODD_34___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__GM_GAIN_ODD_34___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__TIA_GAIN_ODD_34___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__TIA_GAIN_ODD_34___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__SLM_XLNA_ODD_34___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__SLM_XLNA_ODD_34___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__BQ_GAIN_ODD_34___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__BQ_GAIN_ODD_34___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__XLNA_GAIN_EVEN_34___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__XLNA_GAIN_EVEN_34___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__LNA_GAIN_EVEN_34___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__LNA_GAIN_EVEN_34___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__GM_GAIN_EVEN_34___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__GM_GAIN_EVEN_34___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__TIA_GAIN_EVEN_34___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__TIA_GAIN_EVEN_34___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__SLM_XLNA_EVEN_34___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__SLM_XLNA_EVEN_34___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__BQ_GAIN_EVEN_34___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34__BQ_GAIN_EVEN_34___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_34___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35 (0x005ED08C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__XLNA_GAIN_ODD_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__LNA_GAIN_ODD_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__GM_GAIN_ODD_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__TIA_GAIN_ODD_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__SLM_XLNA_ODD_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__BQ_GAIN_ODD_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__XLNA_GAIN_EVEN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__LNA_GAIN_EVEN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__GM_GAIN_EVEN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__TIA_GAIN_EVEN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__SLM_XLNA_EVEN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__BQ_GAIN_EVEN_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__XLNA_GAIN_ODD_35___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__XLNA_GAIN_ODD_35___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__LNA_GAIN_ODD_35___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__LNA_GAIN_ODD_35___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__GM_GAIN_ODD_35___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__GM_GAIN_ODD_35___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__TIA_GAIN_ODD_35___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__TIA_GAIN_ODD_35___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__SLM_XLNA_ODD_35___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__SLM_XLNA_ODD_35___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__BQ_GAIN_ODD_35___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__BQ_GAIN_ODD_35___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__XLNA_GAIN_EVEN_35___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__XLNA_GAIN_EVEN_35___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__LNA_GAIN_EVEN_35___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__LNA_GAIN_EVEN_35___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__GM_GAIN_EVEN_35___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__GM_GAIN_EVEN_35___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__TIA_GAIN_EVEN_35___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__TIA_GAIN_EVEN_35___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__SLM_XLNA_EVEN_35___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__SLM_XLNA_EVEN_35___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__BQ_GAIN_EVEN_35___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35__BQ_GAIN_EVEN_35___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_35___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36 (0x005ED090) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__XLNA_GAIN_ODD_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__LNA_GAIN_ODD_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__GM_GAIN_ODD_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__TIA_GAIN_ODD_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__SLM_XLNA_ODD_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__BQ_GAIN_ODD_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__XLNA_GAIN_EVEN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__LNA_GAIN_EVEN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__GM_GAIN_EVEN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__TIA_GAIN_EVEN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__SLM_XLNA_EVEN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__BQ_GAIN_EVEN_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__XLNA_GAIN_ODD_36___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__XLNA_GAIN_ODD_36___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__LNA_GAIN_ODD_36___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__LNA_GAIN_ODD_36___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__GM_GAIN_ODD_36___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__GM_GAIN_ODD_36___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__TIA_GAIN_ODD_36___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__TIA_GAIN_ODD_36___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__SLM_XLNA_ODD_36___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__SLM_XLNA_ODD_36___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__BQ_GAIN_ODD_36___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__BQ_GAIN_ODD_36___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__XLNA_GAIN_EVEN_36___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__XLNA_GAIN_EVEN_36___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__LNA_GAIN_EVEN_36___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__LNA_GAIN_EVEN_36___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__GM_GAIN_EVEN_36___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__GM_GAIN_EVEN_36___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__TIA_GAIN_EVEN_36___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__TIA_GAIN_EVEN_36___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__SLM_XLNA_EVEN_36___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__SLM_XLNA_EVEN_36___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__BQ_GAIN_EVEN_36___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36__BQ_GAIN_EVEN_36___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_36___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37 (0x005ED094) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__XLNA_GAIN_ODD_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__LNA_GAIN_ODD_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__GM_GAIN_ODD_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__TIA_GAIN_ODD_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__SLM_XLNA_ODD_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__BQ_GAIN_ODD_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__XLNA_GAIN_EVEN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__LNA_GAIN_EVEN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__GM_GAIN_EVEN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__TIA_GAIN_EVEN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__SLM_XLNA_EVEN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__BQ_GAIN_EVEN_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__XLNA_GAIN_ODD_37___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__XLNA_GAIN_ODD_37___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__LNA_GAIN_ODD_37___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__LNA_GAIN_ODD_37___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__GM_GAIN_ODD_37___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__GM_GAIN_ODD_37___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__TIA_GAIN_ODD_37___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__TIA_GAIN_ODD_37___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__SLM_XLNA_ODD_37___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__SLM_XLNA_ODD_37___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__BQ_GAIN_ODD_37___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__BQ_GAIN_ODD_37___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__XLNA_GAIN_EVEN_37___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__XLNA_GAIN_EVEN_37___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__LNA_GAIN_EVEN_37___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__LNA_GAIN_EVEN_37___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__GM_GAIN_EVEN_37___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__GM_GAIN_EVEN_37___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__TIA_GAIN_EVEN_37___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__TIA_GAIN_EVEN_37___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__SLM_XLNA_EVEN_37___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__SLM_XLNA_EVEN_37___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__BQ_GAIN_EVEN_37___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37__BQ_GAIN_EVEN_37___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_37___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38 (0x005ED098) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__XLNA_GAIN_ODD_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__LNA_GAIN_ODD_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__GM_GAIN_ODD_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__TIA_GAIN_ODD_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__SLM_XLNA_ODD_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__BQ_GAIN_ODD_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__XLNA_GAIN_EVEN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__LNA_GAIN_EVEN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__GM_GAIN_EVEN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__TIA_GAIN_EVEN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__SLM_XLNA_EVEN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__BQ_GAIN_EVEN_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__XLNA_GAIN_ODD_38___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__XLNA_GAIN_ODD_38___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__LNA_GAIN_ODD_38___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__LNA_GAIN_ODD_38___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__GM_GAIN_ODD_38___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__GM_GAIN_ODD_38___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__TIA_GAIN_ODD_38___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__TIA_GAIN_ODD_38___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__SLM_XLNA_ODD_38___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__SLM_XLNA_ODD_38___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__BQ_GAIN_ODD_38___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__BQ_GAIN_ODD_38___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__XLNA_GAIN_EVEN_38___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__XLNA_GAIN_EVEN_38___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__LNA_GAIN_EVEN_38___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__LNA_GAIN_EVEN_38___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__GM_GAIN_EVEN_38___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__GM_GAIN_EVEN_38___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__TIA_GAIN_EVEN_38___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__TIA_GAIN_EVEN_38___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__SLM_XLNA_EVEN_38___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__SLM_XLNA_EVEN_38___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__BQ_GAIN_EVEN_38___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38__BQ_GAIN_EVEN_38___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_38___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39 (0x005ED09C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__XLNA_GAIN_ODD_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__LNA_GAIN_ODD_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__GM_GAIN_ODD_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__TIA_GAIN_ODD_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__SLM_XLNA_ODD_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__BQ_GAIN_ODD_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__XLNA_GAIN_EVEN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__LNA_GAIN_EVEN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__GM_GAIN_EVEN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__TIA_GAIN_EVEN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__SLM_XLNA_EVEN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__BQ_GAIN_EVEN_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__XLNA_GAIN_ODD_39___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__XLNA_GAIN_ODD_39___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__LNA_GAIN_ODD_39___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__LNA_GAIN_ODD_39___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__GM_GAIN_ODD_39___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__GM_GAIN_ODD_39___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__TIA_GAIN_ODD_39___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__TIA_GAIN_ODD_39___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__SLM_XLNA_ODD_39___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__SLM_XLNA_ODD_39___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__BQ_GAIN_ODD_39___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__BQ_GAIN_ODD_39___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__XLNA_GAIN_EVEN_39___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__XLNA_GAIN_EVEN_39___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__LNA_GAIN_EVEN_39___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__LNA_GAIN_EVEN_39___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__GM_GAIN_EVEN_39___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__GM_GAIN_EVEN_39___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__TIA_GAIN_EVEN_39___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__TIA_GAIN_EVEN_39___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__SLM_XLNA_EVEN_39___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__SLM_XLNA_EVEN_39___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__BQ_GAIN_EVEN_39___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39__BQ_GAIN_EVEN_39___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_39___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40 (0x005ED0A0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__XLNA_GAIN_ODD_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__LNA_GAIN_ODD_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__GM_GAIN_ODD_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__TIA_GAIN_ODD_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__SLM_XLNA_ODD_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__BQ_GAIN_ODD_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__XLNA_GAIN_EVEN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__LNA_GAIN_EVEN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__GM_GAIN_EVEN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__TIA_GAIN_EVEN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__SLM_XLNA_EVEN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__BQ_GAIN_EVEN_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__XLNA_GAIN_ODD_40___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__XLNA_GAIN_ODD_40___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__LNA_GAIN_ODD_40___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__LNA_GAIN_ODD_40___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__GM_GAIN_ODD_40___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__GM_GAIN_ODD_40___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__TIA_GAIN_ODD_40___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__TIA_GAIN_ODD_40___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__SLM_XLNA_ODD_40___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__SLM_XLNA_ODD_40___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__BQ_GAIN_ODD_40___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__BQ_GAIN_ODD_40___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__XLNA_GAIN_EVEN_40___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__XLNA_GAIN_EVEN_40___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__LNA_GAIN_EVEN_40___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__LNA_GAIN_EVEN_40___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__GM_GAIN_EVEN_40___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__GM_GAIN_EVEN_40___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__TIA_GAIN_EVEN_40___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__TIA_GAIN_EVEN_40___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__SLM_XLNA_EVEN_40___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__SLM_XLNA_EVEN_40___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__BQ_GAIN_EVEN_40___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40__BQ_GAIN_EVEN_40___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_40___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41 (0x005ED0A4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__XLNA_GAIN_ODD_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__LNA_GAIN_ODD_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__GM_GAIN_ODD_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__TIA_GAIN_ODD_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__SLM_XLNA_ODD_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__BQ_GAIN_ODD_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__XLNA_GAIN_EVEN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__LNA_GAIN_EVEN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__GM_GAIN_EVEN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__TIA_GAIN_EVEN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__SLM_XLNA_EVEN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__BQ_GAIN_EVEN_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__XLNA_GAIN_ODD_41___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__XLNA_GAIN_ODD_41___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__LNA_GAIN_ODD_41___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__LNA_GAIN_ODD_41___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__GM_GAIN_ODD_41___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__GM_GAIN_ODD_41___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__TIA_GAIN_ODD_41___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__TIA_GAIN_ODD_41___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__SLM_XLNA_ODD_41___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__SLM_XLNA_ODD_41___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__BQ_GAIN_ODD_41___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__BQ_GAIN_ODD_41___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__XLNA_GAIN_EVEN_41___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__XLNA_GAIN_EVEN_41___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__LNA_GAIN_EVEN_41___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__LNA_GAIN_EVEN_41___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__GM_GAIN_EVEN_41___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__GM_GAIN_EVEN_41___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__TIA_GAIN_EVEN_41___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__TIA_GAIN_EVEN_41___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__SLM_XLNA_EVEN_41___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__SLM_XLNA_EVEN_41___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__BQ_GAIN_EVEN_41___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41__BQ_GAIN_EVEN_41___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_41___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42 (0x005ED0A8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__XLNA_GAIN_ODD_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__LNA_GAIN_ODD_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__GM_GAIN_ODD_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__TIA_GAIN_ODD_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__SLM_XLNA_ODD_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__BQ_GAIN_ODD_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__XLNA_GAIN_EVEN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__LNA_GAIN_EVEN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__GM_GAIN_EVEN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__TIA_GAIN_EVEN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__SLM_XLNA_EVEN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__BQ_GAIN_EVEN_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__XLNA_GAIN_ODD_42___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__XLNA_GAIN_ODD_42___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__LNA_GAIN_ODD_42___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__LNA_GAIN_ODD_42___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__GM_GAIN_ODD_42___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__GM_GAIN_ODD_42___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__TIA_GAIN_ODD_42___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__TIA_GAIN_ODD_42___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__SLM_XLNA_ODD_42___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__SLM_XLNA_ODD_42___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__BQ_GAIN_ODD_42___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__BQ_GAIN_ODD_42___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__XLNA_GAIN_EVEN_42___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__XLNA_GAIN_EVEN_42___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__LNA_GAIN_EVEN_42___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__LNA_GAIN_EVEN_42___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__GM_GAIN_EVEN_42___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__GM_GAIN_EVEN_42___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__TIA_GAIN_EVEN_42___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__TIA_GAIN_EVEN_42___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__SLM_XLNA_EVEN_42___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__SLM_XLNA_EVEN_42___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__BQ_GAIN_EVEN_42___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42__BQ_GAIN_EVEN_42___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_42___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43 (0x005ED0AC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__XLNA_GAIN_ODD_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__LNA_GAIN_ODD_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__GM_GAIN_ODD_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__TIA_GAIN_ODD_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__SLM_XLNA_ODD_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__BQ_GAIN_ODD_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__XLNA_GAIN_EVEN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__LNA_GAIN_EVEN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__GM_GAIN_EVEN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__TIA_GAIN_EVEN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__SLM_XLNA_EVEN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__BQ_GAIN_EVEN_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__XLNA_GAIN_ODD_43___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__XLNA_GAIN_ODD_43___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__LNA_GAIN_ODD_43___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__LNA_GAIN_ODD_43___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__GM_GAIN_ODD_43___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__GM_GAIN_ODD_43___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__TIA_GAIN_ODD_43___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__TIA_GAIN_ODD_43___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__SLM_XLNA_ODD_43___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__SLM_XLNA_ODD_43___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__BQ_GAIN_ODD_43___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__BQ_GAIN_ODD_43___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__XLNA_GAIN_EVEN_43___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__XLNA_GAIN_EVEN_43___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__LNA_GAIN_EVEN_43___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__LNA_GAIN_EVEN_43___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__GM_GAIN_EVEN_43___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__GM_GAIN_EVEN_43___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__TIA_GAIN_EVEN_43___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__TIA_GAIN_EVEN_43___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__SLM_XLNA_EVEN_43___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__SLM_XLNA_EVEN_43___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__BQ_GAIN_EVEN_43___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43__BQ_GAIN_EVEN_43___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_43___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44 (0x005ED0B0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__XLNA_GAIN_ODD_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__LNA_GAIN_ODD_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__GM_GAIN_ODD_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__TIA_GAIN_ODD_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__SLM_XLNA_ODD_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__BQ_GAIN_ODD_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__XLNA_GAIN_EVEN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__LNA_GAIN_EVEN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__GM_GAIN_EVEN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__TIA_GAIN_EVEN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__SLM_XLNA_EVEN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__BQ_GAIN_EVEN_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__XLNA_GAIN_ODD_44___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__XLNA_GAIN_ODD_44___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__LNA_GAIN_ODD_44___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__LNA_GAIN_ODD_44___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__GM_GAIN_ODD_44___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__GM_GAIN_ODD_44___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__TIA_GAIN_ODD_44___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__TIA_GAIN_ODD_44___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__SLM_XLNA_ODD_44___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__SLM_XLNA_ODD_44___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__BQ_GAIN_ODD_44___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__BQ_GAIN_ODD_44___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__XLNA_GAIN_EVEN_44___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__XLNA_GAIN_EVEN_44___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__LNA_GAIN_EVEN_44___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__LNA_GAIN_EVEN_44___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__GM_GAIN_EVEN_44___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__GM_GAIN_EVEN_44___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__TIA_GAIN_EVEN_44___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__TIA_GAIN_EVEN_44___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__SLM_XLNA_EVEN_44___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__SLM_XLNA_EVEN_44___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__BQ_GAIN_EVEN_44___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44__BQ_GAIN_EVEN_44___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_44___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45 (0x005ED0B4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__XLNA_GAIN_ODD_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__LNA_GAIN_ODD_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__GM_GAIN_ODD_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__TIA_GAIN_ODD_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__SLM_XLNA_ODD_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__BQ_GAIN_ODD_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__XLNA_GAIN_EVEN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__LNA_GAIN_EVEN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__GM_GAIN_EVEN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__TIA_GAIN_EVEN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__SLM_XLNA_EVEN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__BQ_GAIN_EVEN_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__XLNA_GAIN_ODD_45___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__XLNA_GAIN_ODD_45___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__LNA_GAIN_ODD_45___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__LNA_GAIN_ODD_45___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__GM_GAIN_ODD_45___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__GM_GAIN_ODD_45___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__TIA_GAIN_ODD_45___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__TIA_GAIN_ODD_45___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__SLM_XLNA_ODD_45___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__SLM_XLNA_ODD_45___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__BQ_GAIN_ODD_45___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__BQ_GAIN_ODD_45___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__XLNA_GAIN_EVEN_45___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__XLNA_GAIN_EVEN_45___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__LNA_GAIN_EVEN_45___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__LNA_GAIN_EVEN_45___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__GM_GAIN_EVEN_45___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__GM_GAIN_EVEN_45___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__TIA_GAIN_EVEN_45___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__TIA_GAIN_EVEN_45___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__SLM_XLNA_EVEN_45___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__SLM_XLNA_EVEN_45___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__BQ_GAIN_EVEN_45___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45__BQ_GAIN_EVEN_45___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_45___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46 (0x005ED0B8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__XLNA_GAIN_ODD_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__LNA_GAIN_ODD_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__GM_GAIN_ODD_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__TIA_GAIN_ODD_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__SLM_XLNA_ODD_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__BQ_GAIN_ODD_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__XLNA_GAIN_EVEN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__LNA_GAIN_EVEN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__GM_GAIN_EVEN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__TIA_GAIN_EVEN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__SLM_XLNA_EVEN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__BQ_GAIN_EVEN_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__XLNA_GAIN_ODD_46___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__XLNA_GAIN_ODD_46___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__LNA_GAIN_ODD_46___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__LNA_GAIN_ODD_46___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__GM_GAIN_ODD_46___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__GM_GAIN_ODD_46___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__TIA_GAIN_ODD_46___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__TIA_GAIN_ODD_46___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__SLM_XLNA_ODD_46___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__SLM_XLNA_ODD_46___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__BQ_GAIN_ODD_46___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__BQ_GAIN_ODD_46___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__XLNA_GAIN_EVEN_46___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__XLNA_GAIN_EVEN_46___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__LNA_GAIN_EVEN_46___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__LNA_GAIN_EVEN_46___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__GM_GAIN_EVEN_46___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__GM_GAIN_EVEN_46___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__TIA_GAIN_EVEN_46___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__TIA_GAIN_EVEN_46___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__SLM_XLNA_EVEN_46___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__SLM_XLNA_EVEN_46___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__BQ_GAIN_EVEN_46___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46__BQ_GAIN_EVEN_46___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_46___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47 (0x005ED0BC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__XLNA_GAIN_ODD_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__LNA_GAIN_ODD_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__GM_GAIN_ODD_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__TIA_GAIN_ODD_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__SLM_XLNA_ODD_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__BQ_GAIN_ODD_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__XLNA_GAIN_EVEN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__LNA_GAIN_EVEN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__GM_GAIN_EVEN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__TIA_GAIN_EVEN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__SLM_XLNA_EVEN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__BQ_GAIN_EVEN_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__XLNA_GAIN_ODD_47___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__XLNA_GAIN_ODD_47___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__LNA_GAIN_ODD_47___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__LNA_GAIN_ODD_47___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__GM_GAIN_ODD_47___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__GM_GAIN_ODD_47___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__TIA_GAIN_ODD_47___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__TIA_GAIN_ODD_47___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__SLM_XLNA_ODD_47___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__SLM_XLNA_ODD_47___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__BQ_GAIN_ODD_47___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__BQ_GAIN_ODD_47___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__XLNA_GAIN_EVEN_47___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__XLNA_GAIN_EVEN_47___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__LNA_GAIN_EVEN_47___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__LNA_GAIN_EVEN_47___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__GM_GAIN_EVEN_47___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__GM_GAIN_EVEN_47___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__TIA_GAIN_EVEN_47___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__TIA_GAIN_EVEN_47___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__SLM_XLNA_EVEN_47___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__SLM_XLNA_EVEN_47___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__BQ_GAIN_EVEN_47___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47__BQ_GAIN_EVEN_47___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_47___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48 (0x005ED0C0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__XLNA_GAIN_ODD_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__LNA_GAIN_ODD_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__GM_GAIN_ODD_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__TIA_GAIN_ODD_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__SLM_XLNA_ODD_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__BQ_GAIN_ODD_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__XLNA_GAIN_EVEN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__LNA_GAIN_EVEN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__GM_GAIN_EVEN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__TIA_GAIN_EVEN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__SLM_XLNA_EVEN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__BQ_GAIN_EVEN_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__XLNA_GAIN_ODD_48___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__XLNA_GAIN_ODD_48___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__LNA_GAIN_ODD_48___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__LNA_GAIN_ODD_48___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__GM_GAIN_ODD_48___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__GM_GAIN_ODD_48___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__TIA_GAIN_ODD_48___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__TIA_GAIN_ODD_48___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__SLM_XLNA_ODD_48___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__SLM_XLNA_ODD_48___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__BQ_GAIN_ODD_48___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__BQ_GAIN_ODD_48___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__XLNA_GAIN_EVEN_48___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__XLNA_GAIN_EVEN_48___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__LNA_GAIN_EVEN_48___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__LNA_GAIN_EVEN_48___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__GM_GAIN_EVEN_48___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__GM_GAIN_EVEN_48___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__TIA_GAIN_EVEN_48___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__TIA_GAIN_EVEN_48___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__SLM_XLNA_EVEN_48___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__SLM_XLNA_EVEN_48___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__BQ_GAIN_EVEN_48___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48__BQ_GAIN_EVEN_48___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_48___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49 (0x005ED0C4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__XLNA_GAIN_ODD_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__LNA_GAIN_ODD_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__GM_GAIN_ODD_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__TIA_GAIN_ODD_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__SLM_XLNA_ODD_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__BQ_GAIN_ODD_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__XLNA_GAIN_EVEN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__LNA_GAIN_EVEN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__GM_GAIN_EVEN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__TIA_GAIN_EVEN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__SLM_XLNA_EVEN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__BQ_GAIN_EVEN_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__XLNA_GAIN_ODD_49___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__XLNA_GAIN_ODD_49___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__LNA_GAIN_ODD_49___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__LNA_GAIN_ODD_49___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__GM_GAIN_ODD_49___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__GM_GAIN_ODD_49___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__TIA_GAIN_ODD_49___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__TIA_GAIN_ODD_49___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__SLM_XLNA_ODD_49___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__SLM_XLNA_ODD_49___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__BQ_GAIN_ODD_49___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__BQ_GAIN_ODD_49___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__XLNA_GAIN_EVEN_49___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__XLNA_GAIN_EVEN_49___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__LNA_GAIN_EVEN_49___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__LNA_GAIN_EVEN_49___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__GM_GAIN_EVEN_49___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__GM_GAIN_EVEN_49___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__TIA_GAIN_EVEN_49___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__TIA_GAIN_EVEN_49___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__SLM_XLNA_EVEN_49___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__SLM_XLNA_EVEN_49___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__BQ_GAIN_EVEN_49___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49__BQ_GAIN_EVEN_49___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_49___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50 (0x005ED0C8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__XLNA_GAIN_ODD_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__LNA_GAIN_ODD_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__GM_GAIN_ODD_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__TIA_GAIN_ODD_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__SLM_XLNA_ODD_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__BQ_GAIN_ODD_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__XLNA_GAIN_EVEN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__LNA_GAIN_EVEN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__GM_GAIN_EVEN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__TIA_GAIN_EVEN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__SLM_XLNA_EVEN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__BQ_GAIN_EVEN_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__XLNA_GAIN_ODD_50___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__XLNA_GAIN_ODD_50___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__LNA_GAIN_ODD_50___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__LNA_GAIN_ODD_50___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__GM_GAIN_ODD_50___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__GM_GAIN_ODD_50___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__TIA_GAIN_ODD_50___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__TIA_GAIN_ODD_50___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__SLM_XLNA_ODD_50___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__SLM_XLNA_ODD_50___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__BQ_GAIN_ODD_50___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__BQ_GAIN_ODD_50___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__XLNA_GAIN_EVEN_50___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__XLNA_GAIN_EVEN_50___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__LNA_GAIN_EVEN_50___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__LNA_GAIN_EVEN_50___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__GM_GAIN_EVEN_50___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__GM_GAIN_EVEN_50___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__TIA_GAIN_EVEN_50___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__TIA_GAIN_EVEN_50___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__SLM_XLNA_EVEN_50___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__SLM_XLNA_EVEN_50___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__BQ_GAIN_EVEN_50___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50__BQ_GAIN_EVEN_50___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_50___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51 (0x005ED0CC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__XLNA_GAIN_ODD_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__LNA_GAIN_ODD_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__GM_GAIN_ODD_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__TIA_GAIN_ODD_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__SLM_XLNA_ODD_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__BQ_GAIN_ODD_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__XLNA_GAIN_EVEN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__LNA_GAIN_EVEN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__GM_GAIN_EVEN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__TIA_GAIN_EVEN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__SLM_XLNA_EVEN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__BQ_GAIN_EVEN_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__XLNA_GAIN_ODD_51___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__XLNA_GAIN_ODD_51___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__LNA_GAIN_ODD_51___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__LNA_GAIN_ODD_51___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__GM_GAIN_ODD_51___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__GM_GAIN_ODD_51___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__TIA_GAIN_ODD_51___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__TIA_GAIN_ODD_51___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__SLM_XLNA_ODD_51___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__SLM_XLNA_ODD_51___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__BQ_GAIN_ODD_51___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__BQ_GAIN_ODD_51___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__XLNA_GAIN_EVEN_51___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__XLNA_GAIN_EVEN_51___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__LNA_GAIN_EVEN_51___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__LNA_GAIN_EVEN_51___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__GM_GAIN_EVEN_51___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__GM_GAIN_EVEN_51___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__TIA_GAIN_EVEN_51___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__TIA_GAIN_EVEN_51___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__SLM_XLNA_EVEN_51___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__SLM_XLNA_EVEN_51___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__BQ_GAIN_EVEN_51___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51__BQ_GAIN_EVEN_51___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_51___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52 (0x005ED0D0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__XLNA_GAIN_ODD_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__LNA_GAIN_ODD_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__GM_GAIN_ODD_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__TIA_GAIN_ODD_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__SLM_XLNA_ODD_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__BQ_GAIN_ODD_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__XLNA_GAIN_EVEN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__LNA_GAIN_EVEN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__GM_GAIN_EVEN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__TIA_GAIN_EVEN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__SLM_XLNA_EVEN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__BQ_GAIN_EVEN_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__XLNA_GAIN_ODD_52___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__XLNA_GAIN_ODD_52___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__LNA_GAIN_ODD_52___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__LNA_GAIN_ODD_52___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__GM_GAIN_ODD_52___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__GM_GAIN_ODD_52___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__TIA_GAIN_ODD_52___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__TIA_GAIN_ODD_52___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__SLM_XLNA_ODD_52___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__SLM_XLNA_ODD_52___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__BQ_GAIN_ODD_52___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__BQ_GAIN_ODD_52___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__XLNA_GAIN_EVEN_52___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__XLNA_GAIN_EVEN_52___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__LNA_GAIN_EVEN_52___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__LNA_GAIN_EVEN_52___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__GM_GAIN_EVEN_52___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__GM_GAIN_EVEN_52___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__TIA_GAIN_EVEN_52___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__TIA_GAIN_EVEN_52___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__SLM_XLNA_EVEN_52___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__SLM_XLNA_EVEN_52___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__BQ_GAIN_EVEN_52___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52__BQ_GAIN_EVEN_52___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_52___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53 (0x005ED0D4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__XLNA_GAIN_ODD_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__LNA_GAIN_ODD_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__GM_GAIN_ODD_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__TIA_GAIN_ODD_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__SLM_XLNA_ODD_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__BQ_GAIN_ODD_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__XLNA_GAIN_EVEN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__LNA_GAIN_EVEN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__GM_GAIN_EVEN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__TIA_GAIN_EVEN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__SLM_XLNA_EVEN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__BQ_GAIN_EVEN_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__XLNA_GAIN_ODD_53___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__XLNA_GAIN_ODD_53___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__LNA_GAIN_ODD_53___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__LNA_GAIN_ODD_53___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__GM_GAIN_ODD_53___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__GM_GAIN_ODD_53___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__TIA_GAIN_ODD_53___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__TIA_GAIN_ODD_53___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__SLM_XLNA_ODD_53___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__SLM_XLNA_ODD_53___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__BQ_GAIN_ODD_53___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__BQ_GAIN_ODD_53___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__XLNA_GAIN_EVEN_53___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__XLNA_GAIN_EVEN_53___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__LNA_GAIN_EVEN_53___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__LNA_GAIN_EVEN_53___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__GM_GAIN_EVEN_53___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__GM_GAIN_EVEN_53___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__TIA_GAIN_EVEN_53___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__TIA_GAIN_EVEN_53___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__SLM_XLNA_EVEN_53___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__SLM_XLNA_EVEN_53___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__BQ_GAIN_EVEN_53___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53__BQ_GAIN_EVEN_53___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_53___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54 (0x005ED0D8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__XLNA_GAIN_ODD_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__LNA_GAIN_ODD_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__GM_GAIN_ODD_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__TIA_GAIN_ODD_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__SLM_XLNA_ODD_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__BQ_GAIN_ODD_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__XLNA_GAIN_EVEN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__LNA_GAIN_EVEN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__GM_GAIN_EVEN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__TIA_GAIN_EVEN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__SLM_XLNA_EVEN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__BQ_GAIN_EVEN_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__XLNA_GAIN_ODD_54___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__XLNA_GAIN_ODD_54___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__LNA_GAIN_ODD_54___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__LNA_GAIN_ODD_54___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__GM_GAIN_ODD_54___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__GM_GAIN_ODD_54___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__TIA_GAIN_ODD_54___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__TIA_GAIN_ODD_54___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__SLM_XLNA_ODD_54___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__SLM_XLNA_ODD_54___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__BQ_GAIN_ODD_54___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__BQ_GAIN_ODD_54___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__XLNA_GAIN_EVEN_54___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__XLNA_GAIN_EVEN_54___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__LNA_GAIN_EVEN_54___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__LNA_GAIN_EVEN_54___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__GM_GAIN_EVEN_54___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__GM_GAIN_EVEN_54___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__TIA_GAIN_EVEN_54___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__TIA_GAIN_EVEN_54___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__SLM_XLNA_EVEN_54___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__SLM_XLNA_EVEN_54___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__BQ_GAIN_EVEN_54___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54__BQ_GAIN_EVEN_54___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_54___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55 (0x005ED0DC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__XLNA_GAIN_ODD_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__LNA_GAIN_ODD_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__GM_GAIN_ODD_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__TIA_GAIN_ODD_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__SLM_XLNA_ODD_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__BQ_GAIN_ODD_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__XLNA_GAIN_EVEN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__LNA_GAIN_EVEN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__GM_GAIN_EVEN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__TIA_GAIN_EVEN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__SLM_XLNA_EVEN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__BQ_GAIN_EVEN_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__XLNA_GAIN_ODD_55___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__XLNA_GAIN_ODD_55___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__LNA_GAIN_ODD_55___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__LNA_GAIN_ODD_55___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__GM_GAIN_ODD_55___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__GM_GAIN_ODD_55___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__TIA_GAIN_ODD_55___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__TIA_GAIN_ODD_55___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__SLM_XLNA_ODD_55___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__SLM_XLNA_ODD_55___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__BQ_GAIN_ODD_55___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__BQ_GAIN_ODD_55___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__XLNA_GAIN_EVEN_55___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__XLNA_GAIN_EVEN_55___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__LNA_GAIN_EVEN_55___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__LNA_GAIN_EVEN_55___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__GM_GAIN_EVEN_55___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__GM_GAIN_EVEN_55___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__TIA_GAIN_EVEN_55___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__TIA_GAIN_EVEN_55___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__SLM_XLNA_EVEN_55___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__SLM_XLNA_EVEN_55___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__BQ_GAIN_EVEN_55___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55__BQ_GAIN_EVEN_55___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_55___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56 (0x005ED0E0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__XLNA_GAIN_ODD_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__LNA_GAIN_ODD_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__GM_GAIN_ODD_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__TIA_GAIN_ODD_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__SLM_XLNA_ODD_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__BQ_GAIN_ODD_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__XLNA_GAIN_EVEN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__LNA_GAIN_EVEN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__GM_GAIN_EVEN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__TIA_GAIN_EVEN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__SLM_XLNA_EVEN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__BQ_GAIN_EVEN_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__XLNA_GAIN_ODD_56___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__XLNA_GAIN_ODD_56___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__LNA_GAIN_ODD_56___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__LNA_GAIN_ODD_56___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__GM_GAIN_ODD_56___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__GM_GAIN_ODD_56___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__TIA_GAIN_ODD_56___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__TIA_GAIN_ODD_56___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__SLM_XLNA_ODD_56___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__SLM_XLNA_ODD_56___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__BQ_GAIN_ODD_56___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__BQ_GAIN_ODD_56___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__XLNA_GAIN_EVEN_56___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__XLNA_GAIN_EVEN_56___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__LNA_GAIN_EVEN_56___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__LNA_GAIN_EVEN_56___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__GM_GAIN_EVEN_56___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__GM_GAIN_EVEN_56___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__TIA_GAIN_EVEN_56___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__TIA_GAIN_EVEN_56___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__SLM_XLNA_EVEN_56___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__SLM_XLNA_EVEN_56___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__BQ_GAIN_EVEN_56___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56__BQ_GAIN_EVEN_56___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_56___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57 (0x005ED0E4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__XLNA_GAIN_ODD_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__LNA_GAIN_ODD_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__GM_GAIN_ODD_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__TIA_GAIN_ODD_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__SLM_XLNA_ODD_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__BQ_GAIN_ODD_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__XLNA_GAIN_EVEN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__LNA_GAIN_EVEN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__GM_GAIN_EVEN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__TIA_GAIN_EVEN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__SLM_XLNA_EVEN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__BQ_GAIN_EVEN_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__XLNA_GAIN_ODD_57___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__XLNA_GAIN_ODD_57___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__LNA_GAIN_ODD_57___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__LNA_GAIN_ODD_57___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__GM_GAIN_ODD_57___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__GM_GAIN_ODD_57___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__TIA_GAIN_ODD_57___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__TIA_GAIN_ODD_57___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__SLM_XLNA_ODD_57___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__SLM_XLNA_ODD_57___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__BQ_GAIN_ODD_57___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__BQ_GAIN_ODD_57___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__XLNA_GAIN_EVEN_57___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__XLNA_GAIN_EVEN_57___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__LNA_GAIN_EVEN_57___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__LNA_GAIN_EVEN_57___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__GM_GAIN_EVEN_57___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__GM_GAIN_EVEN_57___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__TIA_GAIN_EVEN_57___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__TIA_GAIN_EVEN_57___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__SLM_XLNA_EVEN_57___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__SLM_XLNA_EVEN_57___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__BQ_GAIN_EVEN_57___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57__BQ_GAIN_EVEN_57___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_57___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58 (0x005ED0E8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__XLNA_GAIN_ODD_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__LNA_GAIN_ODD_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__GM_GAIN_ODD_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__TIA_GAIN_ODD_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__SLM_XLNA_ODD_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__BQ_GAIN_ODD_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__XLNA_GAIN_EVEN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__LNA_GAIN_EVEN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__GM_GAIN_EVEN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__TIA_GAIN_EVEN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__SLM_XLNA_EVEN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__BQ_GAIN_EVEN_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__XLNA_GAIN_ODD_58___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__XLNA_GAIN_ODD_58___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__LNA_GAIN_ODD_58___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__LNA_GAIN_ODD_58___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__GM_GAIN_ODD_58___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__GM_GAIN_ODD_58___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__TIA_GAIN_ODD_58___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__TIA_GAIN_ODD_58___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__SLM_XLNA_ODD_58___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__SLM_XLNA_ODD_58___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__BQ_GAIN_ODD_58___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__BQ_GAIN_ODD_58___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__XLNA_GAIN_EVEN_58___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__XLNA_GAIN_EVEN_58___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__LNA_GAIN_EVEN_58___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__LNA_GAIN_EVEN_58___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__GM_GAIN_EVEN_58___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__GM_GAIN_EVEN_58___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__TIA_GAIN_EVEN_58___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__TIA_GAIN_EVEN_58___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__SLM_XLNA_EVEN_58___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__SLM_XLNA_EVEN_58___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__BQ_GAIN_EVEN_58___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58__BQ_GAIN_EVEN_58___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_58___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59 (0x005ED0EC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__XLNA_GAIN_ODD_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__LNA_GAIN_ODD_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__GM_GAIN_ODD_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__TIA_GAIN_ODD_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__SLM_XLNA_ODD_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__BQ_GAIN_ODD_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__XLNA_GAIN_EVEN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__LNA_GAIN_EVEN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__GM_GAIN_EVEN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__TIA_GAIN_EVEN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__SLM_XLNA_EVEN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__BQ_GAIN_EVEN_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__XLNA_GAIN_ODD_59___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__XLNA_GAIN_ODD_59___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__LNA_GAIN_ODD_59___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__LNA_GAIN_ODD_59___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__GM_GAIN_ODD_59___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__GM_GAIN_ODD_59___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__TIA_GAIN_ODD_59___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__TIA_GAIN_ODD_59___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__SLM_XLNA_ODD_59___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__SLM_XLNA_ODD_59___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__BQ_GAIN_ODD_59___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__BQ_GAIN_ODD_59___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__XLNA_GAIN_EVEN_59___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__XLNA_GAIN_EVEN_59___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__LNA_GAIN_EVEN_59___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__LNA_GAIN_EVEN_59___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__GM_GAIN_EVEN_59___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__GM_GAIN_EVEN_59___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__TIA_GAIN_EVEN_59___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__TIA_GAIN_EVEN_59___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__SLM_XLNA_EVEN_59___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__SLM_XLNA_EVEN_59___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__BQ_GAIN_EVEN_59___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59__BQ_GAIN_EVEN_59___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_59___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60 (0x005ED0F0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__XLNA_GAIN_ODD_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__LNA_GAIN_ODD_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__GM_GAIN_ODD_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__TIA_GAIN_ODD_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__SLM_XLNA_ODD_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__BQ_GAIN_ODD_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__XLNA_GAIN_EVEN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__LNA_GAIN_EVEN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__GM_GAIN_EVEN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__TIA_GAIN_EVEN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__SLM_XLNA_EVEN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__BQ_GAIN_EVEN_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__XLNA_GAIN_ODD_60___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__XLNA_GAIN_ODD_60___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__LNA_GAIN_ODD_60___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__LNA_GAIN_ODD_60___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__GM_GAIN_ODD_60___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__GM_GAIN_ODD_60___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__TIA_GAIN_ODD_60___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__TIA_GAIN_ODD_60___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__SLM_XLNA_ODD_60___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__SLM_XLNA_ODD_60___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__BQ_GAIN_ODD_60___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__BQ_GAIN_ODD_60___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__XLNA_GAIN_EVEN_60___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__XLNA_GAIN_EVEN_60___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__LNA_GAIN_EVEN_60___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__LNA_GAIN_EVEN_60___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__GM_GAIN_EVEN_60___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__GM_GAIN_EVEN_60___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__TIA_GAIN_EVEN_60___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__TIA_GAIN_EVEN_60___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__SLM_XLNA_EVEN_60___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__SLM_XLNA_EVEN_60___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__BQ_GAIN_EVEN_60___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60__BQ_GAIN_EVEN_60___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_60___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61 (0x005ED0F4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__XLNA_GAIN_ODD_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__LNA_GAIN_ODD_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__GM_GAIN_ODD_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__TIA_GAIN_ODD_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__SLM_XLNA_ODD_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__BQ_GAIN_ODD_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__XLNA_GAIN_EVEN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__LNA_GAIN_EVEN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__GM_GAIN_EVEN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__TIA_GAIN_EVEN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__SLM_XLNA_EVEN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__BQ_GAIN_EVEN_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__XLNA_GAIN_ODD_61___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__XLNA_GAIN_ODD_61___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__LNA_GAIN_ODD_61___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__LNA_GAIN_ODD_61___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__GM_GAIN_ODD_61___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__GM_GAIN_ODD_61___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__TIA_GAIN_ODD_61___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__TIA_GAIN_ODD_61___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__SLM_XLNA_ODD_61___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__SLM_XLNA_ODD_61___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__BQ_GAIN_ODD_61___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__BQ_GAIN_ODD_61___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__XLNA_GAIN_EVEN_61___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__XLNA_GAIN_EVEN_61___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__LNA_GAIN_EVEN_61___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__LNA_GAIN_EVEN_61___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__GM_GAIN_EVEN_61___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__GM_GAIN_EVEN_61___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__TIA_GAIN_EVEN_61___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__TIA_GAIN_EVEN_61___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__SLM_XLNA_EVEN_61___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__SLM_XLNA_EVEN_61___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__BQ_GAIN_EVEN_61___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61__BQ_GAIN_EVEN_61___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_61___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62 (0x005ED0F8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__XLNA_GAIN_ODD_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__LNA_GAIN_ODD_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__GM_GAIN_ODD_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__TIA_GAIN_ODD_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__SLM_XLNA_ODD_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__BQ_GAIN_ODD_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__XLNA_GAIN_EVEN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__LNA_GAIN_EVEN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__GM_GAIN_EVEN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__TIA_GAIN_EVEN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__SLM_XLNA_EVEN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__BQ_GAIN_EVEN_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__XLNA_GAIN_ODD_62___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__XLNA_GAIN_ODD_62___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__LNA_GAIN_ODD_62___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__LNA_GAIN_ODD_62___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__GM_GAIN_ODD_62___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__GM_GAIN_ODD_62___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__TIA_GAIN_ODD_62___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__TIA_GAIN_ODD_62___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__SLM_XLNA_ODD_62___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__SLM_XLNA_ODD_62___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__BQ_GAIN_ODD_62___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__BQ_GAIN_ODD_62___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__XLNA_GAIN_EVEN_62___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__XLNA_GAIN_EVEN_62___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__LNA_GAIN_EVEN_62___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__LNA_GAIN_EVEN_62___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__GM_GAIN_EVEN_62___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__GM_GAIN_EVEN_62___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__TIA_GAIN_EVEN_62___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__TIA_GAIN_EVEN_62___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__SLM_XLNA_EVEN_62___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__SLM_XLNA_EVEN_62___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__BQ_GAIN_EVEN_62___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62__BQ_GAIN_EVEN_62___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_62___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63 (0x005ED0FC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__XLNA_GAIN_ODD_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__LNA_GAIN_ODD_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__GM_GAIN_ODD_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__TIA_GAIN_ODD_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__SLM_XLNA_ODD_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__BQ_GAIN_ODD_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__XLNA_GAIN_EVEN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__LNA_GAIN_EVEN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__GM_GAIN_EVEN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__TIA_GAIN_EVEN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__SLM_XLNA_EVEN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__BQ_GAIN_EVEN_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__XLNA_GAIN_ODD_63___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__XLNA_GAIN_ODD_63___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__LNA_GAIN_ODD_63___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__LNA_GAIN_ODD_63___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__GM_GAIN_ODD_63___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__GM_GAIN_ODD_63___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__TIA_GAIN_ODD_63___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__TIA_GAIN_ODD_63___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__SLM_XLNA_ODD_63___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__SLM_XLNA_ODD_63___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__BQ_GAIN_ODD_63___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__BQ_GAIN_ODD_63___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__XLNA_GAIN_EVEN_63___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__XLNA_GAIN_EVEN_63___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__LNA_GAIN_EVEN_63___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__LNA_GAIN_EVEN_63___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__GM_GAIN_EVEN_63___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__GM_GAIN_EVEN_63___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__TIA_GAIN_EVEN_63___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__TIA_GAIN_EVEN_63___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__SLM_XLNA_EVEN_63___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__SLM_XLNA_EVEN_63___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__BQ_GAIN_EVEN_63___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63__BQ_GAIN_EVEN_63___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_63___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64 (0x005ED100) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__XLNA_GAIN_ODD_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__LNA_GAIN_ODD_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__GM_GAIN_ODD_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__TIA_GAIN_ODD_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__SLM_XLNA_ODD_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__BQ_GAIN_ODD_64___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__XLNA_GAIN_EVEN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__LNA_GAIN_EVEN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__GM_GAIN_EVEN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__TIA_GAIN_EVEN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__SLM_XLNA_EVEN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__BQ_GAIN_EVEN_64___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__XLNA_GAIN_ODD_64___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__XLNA_GAIN_ODD_64___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__LNA_GAIN_ODD_64___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__LNA_GAIN_ODD_64___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__GM_GAIN_ODD_64___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__GM_GAIN_ODD_64___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__TIA_GAIN_ODD_64___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__TIA_GAIN_ODD_64___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__SLM_XLNA_ODD_64___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__SLM_XLNA_ODD_64___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__BQ_GAIN_ODD_64___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__BQ_GAIN_ODD_64___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__XLNA_GAIN_EVEN_64___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__XLNA_GAIN_EVEN_64___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__LNA_GAIN_EVEN_64___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__LNA_GAIN_EVEN_64___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__GM_GAIN_EVEN_64___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__GM_GAIN_EVEN_64___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__TIA_GAIN_EVEN_64___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__TIA_GAIN_EVEN_64___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__SLM_XLNA_EVEN_64___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__SLM_XLNA_EVEN_64___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__BQ_GAIN_EVEN_64___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64__BQ_GAIN_EVEN_64___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_64___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65 (0x005ED104) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__XLNA_GAIN_ODD_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__LNA_GAIN_ODD_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__GM_GAIN_ODD_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__TIA_GAIN_ODD_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__SLM_XLNA_ODD_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__BQ_GAIN_ODD_65___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__XLNA_GAIN_EVEN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__LNA_GAIN_EVEN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__GM_GAIN_EVEN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__TIA_GAIN_EVEN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__SLM_XLNA_EVEN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__BQ_GAIN_EVEN_65___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__XLNA_GAIN_ODD_65___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__XLNA_GAIN_ODD_65___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__LNA_GAIN_ODD_65___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__LNA_GAIN_ODD_65___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__GM_GAIN_ODD_65___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__GM_GAIN_ODD_65___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__TIA_GAIN_ODD_65___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__TIA_GAIN_ODD_65___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__SLM_XLNA_ODD_65___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__SLM_XLNA_ODD_65___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__BQ_GAIN_ODD_65___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__BQ_GAIN_ODD_65___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__XLNA_GAIN_EVEN_65___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__XLNA_GAIN_EVEN_65___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__LNA_GAIN_EVEN_65___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__LNA_GAIN_EVEN_65___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__GM_GAIN_EVEN_65___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__GM_GAIN_EVEN_65___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__TIA_GAIN_EVEN_65___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__TIA_GAIN_EVEN_65___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__SLM_XLNA_EVEN_65___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__SLM_XLNA_EVEN_65___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__BQ_GAIN_EVEN_65___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65__BQ_GAIN_EVEN_65___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_65___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66 (0x005ED108) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__XLNA_GAIN_ODD_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__LNA_GAIN_ODD_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__GM_GAIN_ODD_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__TIA_GAIN_ODD_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__SLM_XLNA_ODD_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__BQ_GAIN_ODD_66___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__XLNA_GAIN_EVEN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__LNA_GAIN_EVEN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__GM_GAIN_EVEN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__TIA_GAIN_EVEN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__SLM_XLNA_EVEN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__BQ_GAIN_EVEN_66___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__XLNA_GAIN_ODD_66___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__XLNA_GAIN_ODD_66___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__LNA_GAIN_ODD_66___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__LNA_GAIN_ODD_66___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__GM_GAIN_ODD_66___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__GM_GAIN_ODD_66___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__TIA_GAIN_ODD_66___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__TIA_GAIN_ODD_66___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__SLM_XLNA_ODD_66___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__SLM_XLNA_ODD_66___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__BQ_GAIN_ODD_66___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__BQ_GAIN_ODD_66___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__XLNA_GAIN_EVEN_66___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__XLNA_GAIN_EVEN_66___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__LNA_GAIN_EVEN_66___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__LNA_GAIN_EVEN_66___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__GM_GAIN_EVEN_66___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__GM_GAIN_EVEN_66___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__TIA_GAIN_EVEN_66___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__TIA_GAIN_EVEN_66___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__SLM_XLNA_EVEN_66___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__SLM_XLNA_EVEN_66___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__BQ_GAIN_EVEN_66___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66__BQ_GAIN_EVEN_66___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_66___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67 (0x005ED10C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__XLNA_GAIN_ODD_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__LNA_GAIN_ODD_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__GM_GAIN_ODD_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__TIA_GAIN_ODD_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__SLM_XLNA_ODD_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__BQ_GAIN_ODD_67___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__XLNA_GAIN_EVEN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__LNA_GAIN_EVEN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__GM_GAIN_EVEN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__TIA_GAIN_EVEN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__SLM_XLNA_EVEN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__BQ_GAIN_EVEN_67___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__XLNA_GAIN_ODD_67___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__XLNA_GAIN_ODD_67___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__LNA_GAIN_ODD_67___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__LNA_GAIN_ODD_67___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__GM_GAIN_ODD_67___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__GM_GAIN_ODD_67___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__TIA_GAIN_ODD_67___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__TIA_GAIN_ODD_67___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__SLM_XLNA_ODD_67___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__SLM_XLNA_ODD_67___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__BQ_GAIN_ODD_67___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__BQ_GAIN_ODD_67___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__XLNA_GAIN_EVEN_67___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__XLNA_GAIN_EVEN_67___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__LNA_GAIN_EVEN_67___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__LNA_GAIN_EVEN_67___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__GM_GAIN_EVEN_67___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__GM_GAIN_EVEN_67___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__TIA_GAIN_EVEN_67___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__TIA_GAIN_EVEN_67___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__SLM_XLNA_EVEN_67___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__SLM_XLNA_EVEN_67___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__BQ_GAIN_EVEN_67___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67__BQ_GAIN_EVEN_67___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_67___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68 (0x005ED110) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__XLNA_GAIN_ODD_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__LNA_GAIN_ODD_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__GM_GAIN_ODD_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__TIA_GAIN_ODD_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__SLM_XLNA_ODD_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__BQ_GAIN_ODD_68___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__XLNA_GAIN_EVEN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__LNA_GAIN_EVEN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__GM_GAIN_EVEN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__TIA_GAIN_EVEN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__SLM_XLNA_EVEN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__BQ_GAIN_EVEN_68___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__XLNA_GAIN_ODD_68___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__XLNA_GAIN_ODD_68___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__LNA_GAIN_ODD_68___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__LNA_GAIN_ODD_68___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__GM_GAIN_ODD_68___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__GM_GAIN_ODD_68___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__TIA_GAIN_ODD_68___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__TIA_GAIN_ODD_68___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__SLM_XLNA_ODD_68___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__SLM_XLNA_ODD_68___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__BQ_GAIN_ODD_68___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__BQ_GAIN_ODD_68___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__XLNA_GAIN_EVEN_68___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__XLNA_GAIN_EVEN_68___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__LNA_GAIN_EVEN_68___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__LNA_GAIN_EVEN_68___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__GM_GAIN_EVEN_68___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__GM_GAIN_EVEN_68___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__TIA_GAIN_EVEN_68___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__TIA_GAIN_EVEN_68___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__SLM_XLNA_EVEN_68___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__SLM_XLNA_EVEN_68___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__BQ_GAIN_EVEN_68___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68__BQ_GAIN_EVEN_68___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_68___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69 (0x005ED114) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__XLNA_GAIN_ODD_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__LNA_GAIN_ODD_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__GM_GAIN_ODD_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__TIA_GAIN_ODD_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__SLM_XLNA_ODD_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__BQ_GAIN_ODD_69___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__XLNA_GAIN_EVEN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__LNA_GAIN_EVEN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__GM_GAIN_EVEN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__TIA_GAIN_EVEN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__SLM_XLNA_EVEN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__BQ_GAIN_EVEN_69___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__XLNA_GAIN_ODD_69___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__XLNA_GAIN_ODD_69___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__LNA_GAIN_ODD_69___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__LNA_GAIN_ODD_69___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__GM_GAIN_ODD_69___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__GM_GAIN_ODD_69___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__TIA_GAIN_ODD_69___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__TIA_GAIN_ODD_69___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__SLM_XLNA_ODD_69___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__SLM_XLNA_ODD_69___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__BQ_GAIN_ODD_69___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__BQ_GAIN_ODD_69___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__XLNA_GAIN_EVEN_69___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__XLNA_GAIN_EVEN_69___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__LNA_GAIN_EVEN_69___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__LNA_GAIN_EVEN_69___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__GM_GAIN_EVEN_69___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__GM_GAIN_EVEN_69___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__TIA_GAIN_EVEN_69___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__TIA_GAIN_EVEN_69___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__SLM_XLNA_EVEN_69___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__SLM_XLNA_EVEN_69___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__BQ_GAIN_EVEN_69___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69__BQ_GAIN_EVEN_69___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_69___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70 (0x005ED118) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__XLNA_GAIN_ODD_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__LNA_GAIN_ODD_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__GM_GAIN_ODD_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__TIA_GAIN_ODD_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__SLM_XLNA_ODD_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__BQ_GAIN_ODD_70___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__XLNA_GAIN_EVEN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__LNA_GAIN_EVEN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__GM_GAIN_EVEN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__TIA_GAIN_EVEN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__SLM_XLNA_EVEN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__BQ_GAIN_EVEN_70___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__XLNA_GAIN_ODD_70___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__XLNA_GAIN_ODD_70___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__LNA_GAIN_ODD_70___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__LNA_GAIN_ODD_70___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__GM_GAIN_ODD_70___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__GM_GAIN_ODD_70___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__TIA_GAIN_ODD_70___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__TIA_GAIN_ODD_70___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__SLM_XLNA_ODD_70___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__SLM_XLNA_ODD_70___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__BQ_GAIN_ODD_70___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__BQ_GAIN_ODD_70___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__XLNA_GAIN_EVEN_70___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__XLNA_GAIN_EVEN_70___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__LNA_GAIN_EVEN_70___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__LNA_GAIN_EVEN_70___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__GM_GAIN_EVEN_70___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__GM_GAIN_EVEN_70___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__TIA_GAIN_EVEN_70___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__TIA_GAIN_EVEN_70___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__SLM_XLNA_EVEN_70___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__SLM_XLNA_EVEN_70___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__BQ_GAIN_EVEN_70___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70__BQ_GAIN_EVEN_70___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_70___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71 (0x005ED11C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__XLNA_GAIN_ODD_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__LNA_GAIN_ODD_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__GM_GAIN_ODD_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__TIA_GAIN_ODD_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__SLM_XLNA_ODD_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__BQ_GAIN_ODD_71___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__XLNA_GAIN_EVEN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__LNA_GAIN_EVEN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__GM_GAIN_EVEN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__TIA_GAIN_EVEN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__SLM_XLNA_EVEN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__BQ_GAIN_EVEN_71___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__XLNA_GAIN_ODD_71___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__XLNA_GAIN_ODD_71___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__LNA_GAIN_ODD_71___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__LNA_GAIN_ODD_71___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__GM_GAIN_ODD_71___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__GM_GAIN_ODD_71___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__TIA_GAIN_ODD_71___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__TIA_GAIN_ODD_71___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__SLM_XLNA_ODD_71___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__SLM_XLNA_ODD_71___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__BQ_GAIN_ODD_71___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__BQ_GAIN_ODD_71___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__XLNA_GAIN_EVEN_71___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__XLNA_GAIN_EVEN_71___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__LNA_GAIN_EVEN_71___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__LNA_GAIN_EVEN_71___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__GM_GAIN_EVEN_71___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__GM_GAIN_EVEN_71___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__TIA_GAIN_EVEN_71___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__TIA_GAIN_EVEN_71___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__SLM_XLNA_EVEN_71___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__SLM_XLNA_EVEN_71___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__BQ_GAIN_EVEN_71___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71__BQ_GAIN_EVEN_71___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_71___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72 (0x005ED120) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__XLNA_GAIN_ODD_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__LNA_GAIN_ODD_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__GM_GAIN_ODD_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__TIA_GAIN_ODD_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__SLM_XLNA_ODD_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__BQ_GAIN_ODD_72___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__XLNA_GAIN_EVEN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__LNA_GAIN_EVEN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__GM_GAIN_EVEN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__TIA_GAIN_EVEN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__SLM_XLNA_EVEN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__BQ_GAIN_EVEN_72___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__XLNA_GAIN_ODD_72___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__XLNA_GAIN_ODD_72___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__LNA_GAIN_ODD_72___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__LNA_GAIN_ODD_72___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__GM_GAIN_ODD_72___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__GM_GAIN_ODD_72___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__TIA_GAIN_ODD_72___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__TIA_GAIN_ODD_72___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__SLM_XLNA_ODD_72___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__SLM_XLNA_ODD_72___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__BQ_GAIN_ODD_72___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__BQ_GAIN_ODD_72___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__XLNA_GAIN_EVEN_72___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__XLNA_GAIN_EVEN_72___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__LNA_GAIN_EVEN_72___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__LNA_GAIN_EVEN_72___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__GM_GAIN_EVEN_72___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__GM_GAIN_EVEN_72___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__TIA_GAIN_EVEN_72___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__TIA_GAIN_EVEN_72___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__SLM_XLNA_EVEN_72___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__SLM_XLNA_EVEN_72___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__BQ_GAIN_EVEN_72___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72__BQ_GAIN_EVEN_72___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_72___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73 (0x005ED124) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__XLNA_GAIN_ODD_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__LNA_GAIN_ODD_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__GM_GAIN_ODD_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__TIA_GAIN_ODD_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__SLM_XLNA_ODD_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__BQ_GAIN_ODD_73___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__XLNA_GAIN_EVEN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__LNA_GAIN_EVEN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__GM_GAIN_EVEN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__TIA_GAIN_EVEN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__SLM_XLNA_EVEN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__BQ_GAIN_EVEN_73___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__XLNA_GAIN_ODD_73___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__XLNA_GAIN_ODD_73___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__LNA_GAIN_ODD_73___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__LNA_GAIN_ODD_73___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__GM_GAIN_ODD_73___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__GM_GAIN_ODD_73___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__TIA_GAIN_ODD_73___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__TIA_GAIN_ODD_73___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__SLM_XLNA_ODD_73___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__SLM_XLNA_ODD_73___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__BQ_GAIN_ODD_73___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__BQ_GAIN_ODD_73___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__XLNA_GAIN_EVEN_73___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__XLNA_GAIN_EVEN_73___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__LNA_GAIN_EVEN_73___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__LNA_GAIN_EVEN_73___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__GM_GAIN_EVEN_73___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__GM_GAIN_EVEN_73___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__TIA_GAIN_EVEN_73___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__TIA_GAIN_EVEN_73___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__SLM_XLNA_EVEN_73___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__SLM_XLNA_EVEN_73___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__BQ_GAIN_EVEN_73___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73__BQ_GAIN_EVEN_73___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_73___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74 (0x005ED128) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__XLNA_GAIN_ODD_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__LNA_GAIN_ODD_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__GM_GAIN_ODD_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__TIA_GAIN_ODD_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__SLM_XLNA_ODD_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__BQ_GAIN_ODD_74___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__XLNA_GAIN_EVEN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__LNA_GAIN_EVEN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__GM_GAIN_EVEN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__TIA_GAIN_EVEN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__SLM_XLNA_EVEN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__BQ_GAIN_EVEN_74___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__XLNA_GAIN_ODD_74___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__XLNA_GAIN_ODD_74___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__LNA_GAIN_ODD_74___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__LNA_GAIN_ODD_74___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__GM_GAIN_ODD_74___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__GM_GAIN_ODD_74___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__TIA_GAIN_ODD_74___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__TIA_GAIN_ODD_74___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__SLM_XLNA_ODD_74___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__SLM_XLNA_ODD_74___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__BQ_GAIN_ODD_74___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__BQ_GAIN_ODD_74___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__XLNA_GAIN_EVEN_74___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__XLNA_GAIN_EVEN_74___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__LNA_GAIN_EVEN_74___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__LNA_GAIN_EVEN_74___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__GM_GAIN_EVEN_74___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__GM_GAIN_EVEN_74___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__TIA_GAIN_EVEN_74___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__TIA_GAIN_EVEN_74___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__SLM_XLNA_EVEN_74___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__SLM_XLNA_EVEN_74___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__BQ_GAIN_EVEN_74___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74__BQ_GAIN_EVEN_74___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_74___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75 (0x005ED12C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__XLNA_GAIN_ODD_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__LNA_GAIN_ODD_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__GM_GAIN_ODD_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__TIA_GAIN_ODD_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__SLM_XLNA_ODD_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__BQ_GAIN_ODD_75___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__XLNA_GAIN_EVEN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__LNA_GAIN_EVEN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__GM_GAIN_EVEN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__TIA_GAIN_EVEN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__SLM_XLNA_EVEN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__BQ_GAIN_EVEN_75___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__XLNA_GAIN_ODD_75___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__XLNA_GAIN_ODD_75___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__LNA_GAIN_ODD_75___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__LNA_GAIN_ODD_75___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__GM_GAIN_ODD_75___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__GM_GAIN_ODD_75___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__TIA_GAIN_ODD_75___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__TIA_GAIN_ODD_75___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__SLM_XLNA_ODD_75___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__SLM_XLNA_ODD_75___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__BQ_GAIN_ODD_75___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__BQ_GAIN_ODD_75___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__XLNA_GAIN_EVEN_75___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__XLNA_GAIN_EVEN_75___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__LNA_GAIN_EVEN_75___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__LNA_GAIN_EVEN_75___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__GM_GAIN_EVEN_75___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__GM_GAIN_EVEN_75___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__TIA_GAIN_EVEN_75___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__TIA_GAIN_EVEN_75___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__SLM_XLNA_EVEN_75___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__SLM_XLNA_EVEN_75___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__BQ_GAIN_EVEN_75___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75__BQ_GAIN_EVEN_75___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_75___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76 (0x005ED130) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__XLNA_GAIN_ODD_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__LNA_GAIN_ODD_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__GM_GAIN_ODD_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__TIA_GAIN_ODD_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__SLM_XLNA_ODD_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__BQ_GAIN_ODD_76___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__XLNA_GAIN_EVEN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__LNA_GAIN_EVEN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__GM_GAIN_EVEN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__TIA_GAIN_EVEN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__SLM_XLNA_EVEN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__BQ_GAIN_EVEN_76___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__XLNA_GAIN_ODD_76___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__XLNA_GAIN_ODD_76___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__LNA_GAIN_ODD_76___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__LNA_GAIN_ODD_76___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__GM_GAIN_ODD_76___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__GM_GAIN_ODD_76___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__TIA_GAIN_ODD_76___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__TIA_GAIN_ODD_76___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__SLM_XLNA_ODD_76___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__SLM_XLNA_ODD_76___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__BQ_GAIN_ODD_76___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__BQ_GAIN_ODD_76___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__XLNA_GAIN_EVEN_76___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__XLNA_GAIN_EVEN_76___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__LNA_GAIN_EVEN_76___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__LNA_GAIN_EVEN_76___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__GM_GAIN_EVEN_76___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__GM_GAIN_EVEN_76___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__TIA_GAIN_EVEN_76___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__TIA_GAIN_EVEN_76___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__SLM_XLNA_EVEN_76___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__SLM_XLNA_EVEN_76___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__BQ_GAIN_EVEN_76___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76__BQ_GAIN_EVEN_76___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_76___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77 (0x005ED134) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__XLNA_GAIN_ODD_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__LNA_GAIN_ODD_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__GM_GAIN_ODD_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__TIA_GAIN_ODD_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__SLM_XLNA_ODD_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__BQ_GAIN_ODD_77___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__XLNA_GAIN_EVEN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__LNA_GAIN_EVEN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__GM_GAIN_EVEN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__TIA_GAIN_EVEN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__SLM_XLNA_EVEN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__BQ_GAIN_EVEN_77___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__XLNA_GAIN_ODD_77___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__XLNA_GAIN_ODD_77___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__LNA_GAIN_ODD_77___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__LNA_GAIN_ODD_77___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__GM_GAIN_ODD_77___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__GM_GAIN_ODD_77___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__TIA_GAIN_ODD_77___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__TIA_GAIN_ODD_77___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__SLM_XLNA_ODD_77___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__SLM_XLNA_ODD_77___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__BQ_GAIN_ODD_77___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__BQ_GAIN_ODD_77___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__XLNA_GAIN_EVEN_77___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__XLNA_GAIN_EVEN_77___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__LNA_GAIN_EVEN_77___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__LNA_GAIN_EVEN_77___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__GM_GAIN_EVEN_77___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__GM_GAIN_EVEN_77___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__TIA_GAIN_EVEN_77___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__TIA_GAIN_EVEN_77___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__SLM_XLNA_EVEN_77___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__SLM_XLNA_EVEN_77___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__BQ_GAIN_EVEN_77___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77__BQ_GAIN_EVEN_77___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_77___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78 (0x005ED138) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__XLNA_GAIN_ODD_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__LNA_GAIN_ODD_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__GM_GAIN_ODD_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__TIA_GAIN_ODD_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__SLM_XLNA_ODD_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__BQ_GAIN_ODD_78___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__XLNA_GAIN_EVEN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__LNA_GAIN_EVEN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__GM_GAIN_EVEN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__TIA_GAIN_EVEN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__SLM_XLNA_EVEN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__BQ_GAIN_EVEN_78___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__XLNA_GAIN_ODD_78___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__XLNA_GAIN_ODD_78___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__LNA_GAIN_ODD_78___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__LNA_GAIN_ODD_78___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__GM_GAIN_ODD_78___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__GM_GAIN_ODD_78___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__TIA_GAIN_ODD_78___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__TIA_GAIN_ODD_78___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__SLM_XLNA_ODD_78___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__SLM_XLNA_ODD_78___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__BQ_GAIN_ODD_78___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__BQ_GAIN_ODD_78___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__XLNA_GAIN_EVEN_78___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__XLNA_GAIN_EVEN_78___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__LNA_GAIN_EVEN_78___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__LNA_GAIN_EVEN_78___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__GM_GAIN_EVEN_78___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__GM_GAIN_EVEN_78___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__TIA_GAIN_EVEN_78___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__TIA_GAIN_EVEN_78___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__SLM_XLNA_EVEN_78___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__SLM_XLNA_EVEN_78___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__BQ_GAIN_EVEN_78___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78__BQ_GAIN_EVEN_78___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_78___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79 (0x005ED13C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__XLNA_GAIN_ODD_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__LNA_GAIN_ODD_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__GM_GAIN_ODD_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__TIA_GAIN_ODD_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__SLM_XLNA_ODD_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__BQ_GAIN_ODD_79___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__XLNA_GAIN_EVEN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__LNA_GAIN_EVEN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__GM_GAIN_EVEN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__TIA_GAIN_EVEN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__SLM_XLNA_EVEN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__BQ_GAIN_EVEN_79___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__XLNA_GAIN_ODD_79___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__XLNA_GAIN_ODD_79___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__LNA_GAIN_ODD_79___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__LNA_GAIN_ODD_79___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__GM_GAIN_ODD_79___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__GM_GAIN_ODD_79___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__TIA_GAIN_ODD_79___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__TIA_GAIN_ODD_79___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__SLM_XLNA_ODD_79___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__SLM_XLNA_ODD_79___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__BQ_GAIN_ODD_79___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__BQ_GAIN_ODD_79___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__XLNA_GAIN_EVEN_79___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__XLNA_GAIN_EVEN_79___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__LNA_GAIN_EVEN_79___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__LNA_GAIN_EVEN_79___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__GM_GAIN_EVEN_79___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__GM_GAIN_EVEN_79___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__TIA_GAIN_EVEN_79___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__TIA_GAIN_EVEN_79___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__SLM_XLNA_EVEN_79___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__SLM_XLNA_EVEN_79___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__BQ_GAIN_EVEN_79___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79__BQ_GAIN_EVEN_79___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_79___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80 (0x005ED140) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__XLNA_GAIN_ODD_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__LNA_GAIN_ODD_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__GM_GAIN_ODD_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__TIA_GAIN_ODD_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__SLM_XLNA_ODD_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__BQ_GAIN_ODD_80___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__XLNA_GAIN_EVEN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__LNA_GAIN_EVEN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__GM_GAIN_EVEN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__TIA_GAIN_EVEN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__SLM_XLNA_EVEN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__BQ_GAIN_EVEN_80___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__XLNA_GAIN_ODD_80___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__XLNA_GAIN_ODD_80___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__LNA_GAIN_ODD_80___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__LNA_GAIN_ODD_80___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__GM_GAIN_ODD_80___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__GM_GAIN_ODD_80___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__TIA_GAIN_ODD_80___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__TIA_GAIN_ODD_80___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__SLM_XLNA_ODD_80___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__SLM_XLNA_ODD_80___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__BQ_GAIN_ODD_80___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__BQ_GAIN_ODD_80___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__XLNA_GAIN_EVEN_80___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__XLNA_GAIN_EVEN_80___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__LNA_GAIN_EVEN_80___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__LNA_GAIN_EVEN_80___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__GM_GAIN_EVEN_80___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__GM_GAIN_EVEN_80___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__TIA_GAIN_EVEN_80___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__TIA_GAIN_EVEN_80___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__SLM_XLNA_EVEN_80___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__SLM_XLNA_EVEN_80___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__BQ_GAIN_EVEN_80___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80__BQ_GAIN_EVEN_80___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_80___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81 (0x005ED144) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__XLNA_GAIN_ODD_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__LNA_GAIN_ODD_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__GM_GAIN_ODD_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__TIA_GAIN_ODD_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__SLM_XLNA_ODD_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__BQ_GAIN_ODD_81___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__XLNA_GAIN_EVEN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__LNA_GAIN_EVEN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__GM_GAIN_EVEN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__TIA_GAIN_EVEN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__SLM_XLNA_EVEN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__BQ_GAIN_EVEN_81___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__XLNA_GAIN_ODD_81___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__XLNA_GAIN_ODD_81___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__LNA_GAIN_ODD_81___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__LNA_GAIN_ODD_81___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__GM_GAIN_ODD_81___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__GM_GAIN_ODD_81___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__TIA_GAIN_ODD_81___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__TIA_GAIN_ODD_81___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__SLM_XLNA_ODD_81___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__SLM_XLNA_ODD_81___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__BQ_GAIN_ODD_81___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__BQ_GAIN_ODD_81___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__XLNA_GAIN_EVEN_81___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__XLNA_GAIN_EVEN_81___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__LNA_GAIN_EVEN_81___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__LNA_GAIN_EVEN_81___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__GM_GAIN_EVEN_81___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__GM_GAIN_EVEN_81___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__TIA_GAIN_EVEN_81___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__TIA_GAIN_EVEN_81___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__SLM_XLNA_EVEN_81___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__SLM_XLNA_EVEN_81___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__BQ_GAIN_EVEN_81___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81__BQ_GAIN_EVEN_81___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_81___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82 (0x005ED148) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__XLNA_GAIN_ODD_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__LNA_GAIN_ODD_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__GM_GAIN_ODD_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__TIA_GAIN_ODD_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__SLM_XLNA_ODD_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__BQ_GAIN_ODD_82___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__XLNA_GAIN_EVEN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__LNA_GAIN_EVEN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__GM_GAIN_EVEN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__TIA_GAIN_EVEN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__SLM_XLNA_EVEN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__BQ_GAIN_EVEN_82___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__XLNA_GAIN_ODD_82___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__XLNA_GAIN_ODD_82___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__LNA_GAIN_ODD_82___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__LNA_GAIN_ODD_82___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__GM_GAIN_ODD_82___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__GM_GAIN_ODD_82___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__TIA_GAIN_ODD_82___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__TIA_GAIN_ODD_82___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__SLM_XLNA_ODD_82___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__SLM_XLNA_ODD_82___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__BQ_GAIN_ODD_82___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__BQ_GAIN_ODD_82___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__XLNA_GAIN_EVEN_82___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__XLNA_GAIN_EVEN_82___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__LNA_GAIN_EVEN_82___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__LNA_GAIN_EVEN_82___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__GM_GAIN_EVEN_82___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__GM_GAIN_EVEN_82___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__TIA_GAIN_EVEN_82___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__TIA_GAIN_EVEN_82___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__SLM_XLNA_EVEN_82___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__SLM_XLNA_EVEN_82___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__BQ_GAIN_EVEN_82___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82__BQ_GAIN_EVEN_82___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_82___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83 (0x005ED14C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__XLNA_GAIN_ODD_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__LNA_GAIN_ODD_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__GM_GAIN_ODD_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__TIA_GAIN_ODD_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__SLM_XLNA_ODD_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__BQ_GAIN_ODD_83___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__XLNA_GAIN_EVEN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__LNA_GAIN_EVEN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__GM_GAIN_EVEN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__TIA_GAIN_EVEN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__SLM_XLNA_EVEN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__BQ_GAIN_EVEN_83___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__XLNA_GAIN_ODD_83___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__XLNA_GAIN_ODD_83___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__LNA_GAIN_ODD_83___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__LNA_GAIN_ODD_83___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__GM_GAIN_ODD_83___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__GM_GAIN_ODD_83___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__TIA_GAIN_ODD_83___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__TIA_GAIN_ODD_83___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__SLM_XLNA_ODD_83___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__SLM_XLNA_ODD_83___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__BQ_GAIN_ODD_83___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__BQ_GAIN_ODD_83___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__XLNA_GAIN_EVEN_83___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__XLNA_GAIN_EVEN_83___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__LNA_GAIN_EVEN_83___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__LNA_GAIN_EVEN_83___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__GM_GAIN_EVEN_83___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__GM_GAIN_EVEN_83___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__TIA_GAIN_EVEN_83___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__TIA_GAIN_EVEN_83___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__SLM_XLNA_EVEN_83___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__SLM_XLNA_EVEN_83___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__BQ_GAIN_EVEN_83___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83__BQ_GAIN_EVEN_83___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_83___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84 (0x005ED150) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__XLNA_GAIN_ODD_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__LNA_GAIN_ODD_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__GM_GAIN_ODD_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__TIA_GAIN_ODD_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__SLM_XLNA_ODD_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__BQ_GAIN_ODD_84___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__XLNA_GAIN_EVEN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__LNA_GAIN_EVEN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__GM_GAIN_EVEN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__TIA_GAIN_EVEN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__SLM_XLNA_EVEN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__BQ_GAIN_EVEN_84___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__XLNA_GAIN_ODD_84___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__XLNA_GAIN_ODD_84___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__LNA_GAIN_ODD_84___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__LNA_GAIN_ODD_84___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__GM_GAIN_ODD_84___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__GM_GAIN_ODD_84___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__TIA_GAIN_ODD_84___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__TIA_GAIN_ODD_84___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__SLM_XLNA_ODD_84___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__SLM_XLNA_ODD_84___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__BQ_GAIN_ODD_84___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__BQ_GAIN_ODD_84___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__XLNA_GAIN_EVEN_84___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__XLNA_GAIN_EVEN_84___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__LNA_GAIN_EVEN_84___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__LNA_GAIN_EVEN_84___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__GM_GAIN_EVEN_84___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__GM_GAIN_EVEN_84___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__TIA_GAIN_EVEN_84___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__TIA_GAIN_EVEN_84___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__SLM_XLNA_EVEN_84___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__SLM_XLNA_EVEN_84___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__BQ_GAIN_EVEN_84___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84__BQ_GAIN_EVEN_84___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_84___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85 (0x005ED154) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__XLNA_GAIN_ODD_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__LNA_GAIN_ODD_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__GM_GAIN_ODD_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__TIA_GAIN_ODD_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__SLM_XLNA_ODD_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__BQ_GAIN_ODD_85___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__XLNA_GAIN_EVEN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__LNA_GAIN_EVEN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__GM_GAIN_EVEN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__TIA_GAIN_EVEN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__SLM_XLNA_EVEN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__BQ_GAIN_EVEN_85___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__XLNA_GAIN_ODD_85___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__XLNA_GAIN_ODD_85___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__LNA_GAIN_ODD_85___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__LNA_GAIN_ODD_85___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__GM_GAIN_ODD_85___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__GM_GAIN_ODD_85___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__TIA_GAIN_ODD_85___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__TIA_GAIN_ODD_85___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__SLM_XLNA_ODD_85___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__SLM_XLNA_ODD_85___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__BQ_GAIN_ODD_85___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__BQ_GAIN_ODD_85___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__XLNA_GAIN_EVEN_85___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__XLNA_GAIN_EVEN_85___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__LNA_GAIN_EVEN_85___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__LNA_GAIN_EVEN_85___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__GM_GAIN_EVEN_85___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__GM_GAIN_EVEN_85___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__TIA_GAIN_EVEN_85___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__TIA_GAIN_EVEN_85___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__SLM_XLNA_EVEN_85___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__SLM_XLNA_EVEN_85___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__BQ_GAIN_EVEN_85___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85__BQ_GAIN_EVEN_85___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_85___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86 (0x005ED158) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__XLNA_GAIN_ODD_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__LNA_GAIN_ODD_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__GM_GAIN_ODD_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__TIA_GAIN_ODD_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__SLM_XLNA_ODD_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__BQ_GAIN_ODD_86___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__XLNA_GAIN_EVEN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__LNA_GAIN_EVEN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__GM_GAIN_EVEN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__TIA_GAIN_EVEN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__SLM_XLNA_EVEN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__BQ_GAIN_EVEN_86___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__XLNA_GAIN_ODD_86___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__XLNA_GAIN_ODD_86___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__LNA_GAIN_ODD_86___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__LNA_GAIN_ODD_86___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__GM_GAIN_ODD_86___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__GM_GAIN_ODD_86___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__TIA_GAIN_ODD_86___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__TIA_GAIN_ODD_86___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__SLM_XLNA_ODD_86___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__SLM_XLNA_ODD_86___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__BQ_GAIN_ODD_86___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__BQ_GAIN_ODD_86___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__XLNA_GAIN_EVEN_86___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__XLNA_GAIN_EVEN_86___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__LNA_GAIN_EVEN_86___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__LNA_GAIN_EVEN_86___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__GM_GAIN_EVEN_86___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__GM_GAIN_EVEN_86___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__TIA_GAIN_EVEN_86___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__TIA_GAIN_EVEN_86___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__SLM_XLNA_EVEN_86___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__SLM_XLNA_EVEN_86___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__BQ_GAIN_EVEN_86___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86__BQ_GAIN_EVEN_86___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_86___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87 (0x005ED15C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__XLNA_GAIN_ODD_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__LNA_GAIN_ODD_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__GM_GAIN_ODD_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__TIA_GAIN_ODD_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__SLM_XLNA_ODD_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__BQ_GAIN_ODD_87___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__XLNA_GAIN_EVEN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__LNA_GAIN_EVEN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__GM_GAIN_EVEN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__TIA_GAIN_EVEN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__SLM_XLNA_EVEN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__BQ_GAIN_EVEN_87___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__XLNA_GAIN_ODD_87___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__XLNA_GAIN_ODD_87___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__LNA_GAIN_ODD_87___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__LNA_GAIN_ODD_87___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__GM_GAIN_ODD_87___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__GM_GAIN_ODD_87___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__TIA_GAIN_ODD_87___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__TIA_GAIN_ODD_87___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__SLM_XLNA_ODD_87___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__SLM_XLNA_ODD_87___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__BQ_GAIN_ODD_87___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__BQ_GAIN_ODD_87___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__XLNA_GAIN_EVEN_87___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__XLNA_GAIN_EVEN_87___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__LNA_GAIN_EVEN_87___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__LNA_GAIN_EVEN_87___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__GM_GAIN_EVEN_87___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__GM_GAIN_EVEN_87___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__TIA_GAIN_EVEN_87___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__TIA_GAIN_EVEN_87___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__SLM_XLNA_EVEN_87___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__SLM_XLNA_EVEN_87___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__BQ_GAIN_EVEN_87___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87__BQ_GAIN_EVEN_87___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_87___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88 (0x005ED160) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__XLNA_GAIN_ODD_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__LNA_GAIN_ODD_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__GM_GAIN_ODD_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__TIA_GAIN_ODD_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__SLM_XLNA_ODD_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__BQ_GAIN_ODD_88___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__XLNA_GAIN_EVEN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__LNA_GAIN_EVEN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__GM_GAIN_EVEN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__TIA_GAIN_EVEN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__SLM_XLNA_EVEN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__BQ_GAIN_EVEN_88___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__XLNA_GAIN_ODD_88___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__XLNA_GAIN_ODD_88___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__LNA_GAIN_ODD_88___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__LNA_GAIN_ODD_88___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__GM_GAIN_ODD_88___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__GM_GAIN_ODD_88___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__TIA_GAIN_ODD_88___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__TIA_GAIN_ODD_88___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__SLM_XLNA_ODD_88___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__SLM_XLNA_ODD_88___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__BQ_GAIN_ODD_88___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__BQ_GAIN_ODD_88___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__XLNA_GAIN_EVEN_88___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__XLNA_GAIN_EVEN_88___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__LNA_GAIN_EVEN_88___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__LNA_GAIN_EVEN_88___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__GM_GAIN_EVEN_88___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__GM_GAIN_EVEN_88___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__TIA_GAIN_EVEN_88___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__TIA_GAIN_EVEN_88___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__SLM_XLNA_EVEN_88___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__SLM_XLNA_EVEN_88___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__BQ_GAIN_EVEN_88___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88__BQ_GAIN_EVEN_88___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_88___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89 (0x005ED164) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__XLNA_GAIN_ODD_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__LNA_GAIN_ODD_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__GM_GAIN_ODD_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__TIA_GAIN_ODD_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__SLM_XLNA_ODD_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__BQ_GAIN_ODD_89___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__XLNA_GAIN_EVEN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__LNA_GAIN_EVEN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__GM_GAIN_EVEN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__TIA_GAIN_EVEN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__SLM_XLNA_EVEN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__BQ_GAIN_EVEN_89___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__XLNA_GAIN_ODD_89___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__XLNA_GAIN_ODD_89___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__LNA_GAIN_ODD_89___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__LNA_GAIN_ODD_89___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__GM_GAIN_ODD_89___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__GM_GAIN_ODD_89___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__TIA_GAIN_ODD_89___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__TIA_GAIN_ODD_89___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__SLM_XLNA_ODD_89___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__SLM_XLNA_ODD_89___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__BQ_GAIN_ODD_89___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__BQ_GAIN_ODD_89___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__XLNA_GAIN_EVEN_89___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__XLNA_GAIN_EVEN_89___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__LNA_GAIN_EVEN_89___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__LNA_GAIN_EVEN_89___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__GM_GAIN_EVEN_89___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__GM_GAIN_EVEN_89___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__TIA_GAIN_EVEN_89___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__TIA_GAIN_EVEN_89___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__SLM_XLNA_EVEN_89___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__SLM_XLNA_EVEN_89___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__BQ_GAIN_EVEN_89___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89__BQ_GAIN_EVEN_89___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_89___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90 (0x005ED168) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__XLNA_GAIN_ODD_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__LNA_GAIN_ODD_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__GM_GAIN_ODD_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__TIA_GAIN_ODD_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__SLM_XLNA_ODD_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__BQ_GAIN_ODD_90___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__XLNA_GAIN_EVEN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__LNA_GAIN_EVEN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__GM_GAIN_EVEN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__TIA_GAIN_EVEN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__SLM_XLNA_EVEN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__BQ_GAIN_EVEN_90___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__XLNA_GAIN_ODD_90___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__XLNA_GAIN_ODD_90___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__LNA_GAIN_ODD_90___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__LNA_GAIN_ODD_90___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__GM_GAIN_ODD_90___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__GM_GAIN_ODD_90___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__TIA_GAIN_ODD_90___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__TIA_GAIN_ODD_90___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__SLM_XLNA_ODD_90___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__SLM_XLNA_ODD_90___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__BQ_GAIN_ODD_90___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__BQ_GAIN_ODD_90___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__XLNA_GAIN_EVEN_90___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__XLNA_GAIN_EVEN_90___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__LNA_GAIN_EVEN_90___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__LNA_GAIN_EVEN_90___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__GM_GAIN_EVEN_90___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__GM_GAIN_EVEN_90___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__TIA_GAIN_EVEN_90___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__TIA_GAIN_EVEN_90___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__SLM_XLNA_EVEN_90___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__SLM_XLNA_EVEN_90___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__BQ_GAIN_EVEN_90___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90__BQ_GAIN_EVEN_90___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_90___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91 (0x005ED16C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__XLNA_GAIN_ODD_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__LNA_GAIN_ODD_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__GM_GAIN_ODD_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__TIA_GAIN_ODD_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__SLM_XLNA_ODD_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__BQ_GAIN_ODD_91___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__XLNA_GAIN_EVEN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__LNA_GAIN_EVEN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__GM_GAIN_EVEN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__TIA_GAIN_EVEN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__SLM_XLNA_EVEN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__BQ_GAIN_EVEN_91___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__XLNA_GAIN_ODD_91___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__XLNA_GAIN_ODD_91___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__LNA_GAIN_ODD_91___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__LNA_GAIN_ODD_91___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__GM_GAIN_ODD_91___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__GM_GAIN_ODD_91___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__TIA_GAIN_ODD_91___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__TIA_GAIN_ODD_91___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__SLM_XLNA_ODD_91___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__SLM_XLNA_ODD_91___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__BQ_GAIN_ODD_91___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__BQ_GAIN_ODD_91___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__XLNA_GAIN_EVEN_91___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__XLNA_GAIN_EVEN_91___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__LNA_GAIN_EVEN_91___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__LNA_GAIN_EVEN_91___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__GM_GAIN_EVEN_91___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__GM_GAIN_EVEN_91___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__TIA_GAIN_EVEN_91___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__TIA_GAIN_EVEN_91___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__SLM_XLNA_EVEN_91___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__SLM_XLNA_EVEN_91___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__BQ_GAIN_EVEN_91___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91__BQ_GAIN_EVEN_91___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_91___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92 (0x005ED170) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__XLNA_GAIN_ODD_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__LNA_GAIN_ODD_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__GM_GAIN_ODD_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__TIA_GAIN_ODD_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__SLM_XLNA_ODD_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__BQ_GAIN_ODD_92___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__XLNA_GAIN_EVEN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__LNA_GAIN_EVEN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__GM_GAIN_EVEN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__TIA_GAIN_EVEN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__SLM_XLNA_EVEN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__BQ_GAIN_EVEN_92___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__XLNA_GAIN_ODD_92___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__XLNA_GAIN_ODD_92___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__LNA_GAIN_ODD_92___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__LNA_GAIN_ODD_92___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__GM_GAIN_ODD_92___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__GM_GAIN_ODD_92___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__TIA_GAIN_ODD_92___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__TIA_GAIN_ODD_92___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__SLM_XLNA_ODD_92___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__SLM_XLNA_ODD_92___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__BQ_GAIN_ODD_92___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__BQ_GAIN_ODD_92___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__XLNA_GAIN_EVEN_92___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__XLNA_GAIN_EVEN_92___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__LNA_GAIN_EVEN_92___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__LNA_GAIN_EVEN_92___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__GM_GAIN_EVEN_92___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__GM_GAIN_EVEN_92___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__TIA_GAIN_EVEN_92___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__TIA_GAIN_EVEN_92___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__SLM_XLNA_EVEN_92___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__SLM_XLNA_EVEN_92___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__BQ_GAIN_EVEN_92___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92__BQ_GAIN_EVEN_92___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_92___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93 (0x005ED174) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__XLNA_GAIN_ODD_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__LNA_GAIN_ODD_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__GM_GAIN_ODD_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__TIA_GAIN_ODD_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__SLM_XLNA_ODD_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__BQ_GAIN_ODD_93___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__XLNA_GAIN_EVEN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__LNA_GAIN_EVEN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__GM_GAIN_EVEN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__TIA_GAIN_EVEN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__SLM_XLNA_EVEN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__BQ_GAIN_EVEN_93___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__XLNA_GAIN_ODD_93___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__XLNA_GAIN_ODD_93___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__LNA_GAIN_ODD_93___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__LNA_GAIN_ODD_93___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__GM_GAIN_ODD_93___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__GM_GAIN_ODD_93___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__TIA_GAIN_ODD_93___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__TIA_GAIN_ODD_93___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__SLM_XLNA_ODD_93___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__SLM_XLNA_ODD_93___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__BQ_GAIN_ODD_93___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__BQ_GAIN_ODD_93___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__XLNA_GAIN_EVEN_93___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__XLNA_GAIN_EVEN_93___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__LNA_GAIN_EVEN_93___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__LNA_GAIN_EVEN_93___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__GM_GAIN_EVEN_93___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__GM_GAIN_EVEN_93___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__TIA_GAIN_EVEN_93___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__TIA_GAIN_EVEN_93___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__SLM_XLNA_EVEN_93___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__SLM_XLNA_EVEN_93___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__BQ_GAIN_EVEN_93___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93__BQ_GAIN_EVEN_93___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_93___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94 (0x005ED178) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__XLNA_GAIN_ODD_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__LNA_GAIN_ODD_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__GM_GAIN_ODD_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__TIA_GAIN_ODD_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__SLM_XLNA_ODD_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__BQ_GAIN_ODD_94___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__XLNA_GAIN_EVEN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__LNA_GAIN_EVEN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__GM_GAIN_EVEN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__TIA_GAIN_EVEN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__SLM_XLNA_EVEN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__BQ_GAIN_EVEN_94___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__XLNA_GAIN_ODD_94___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__XLNA_GAIN_ODD_94___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__LNA_GAIN_ODD_94___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__LNA_GAIN_ODD_94___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__GM_GAIN_ODD_94___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__GM_GAIN_ODD_94___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__TIA_GAIN_ODD_94___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__TIA_GAIN_ODD_94___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__SLM_XLNA_ODD_94___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__SLM_XLNA_ODD_94___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__BQ_GAIN_ODD_94___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__BQ_GAIN_ODD_94___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__XLNA_GAIN_EVEN_94___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__XLNA_GAIN_EVEN_94___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__LNA_GAIN_EVEN_94___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__LNA_GAIN_EVEN_94___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__GM_GAIN_EVEN_94___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__GM_GAIN_EVEN_94___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__TIA_GAIN_EVEN_94___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__TIA_GAIN_EVEN_94___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__SLM_XLNA_EVEN_94___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__SLM_XLNA_EVEN_94___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__BQ_GAIN_EVEN_94___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94__BQ_GAIN_EVEN_94___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_94___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95 (0x005ED17C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__XLNA_GAIN_ODD_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__LNA_GAIN_ODD_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__GM_GAIN_ODD_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__TIA_GAIN_ODD_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__SLM_XLNA_ODD_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__BQ_GAIN_ODD_95___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__XLNA_GAIN_EVEN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__LNA_GAIN_EVEN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__GM_GAIN_EVEN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__TIA_GAIN_EVEN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__SLM_XLNA_EVEN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__BQ_GAIN_EVEN_95___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__XLNA_GAIN_ODD_95___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__XLNA_GAIN_ODD_95___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__LNA_GAIN_ODD_95___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__LNA_GAIN_ODD_95___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__GM_GAIN_ODD_95___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__GM_GAIN_ODD_95___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__TIA_GAIN_ODD_95___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__TIA_GAIN_ODD_95___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__SLM_XLNA_ODD_95___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__SLM_XLNA_ODD_95___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__BQ_GAIN_ODD_95___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__BQ_GAIN_ODD_95___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__XLNA_GAIN_EVEN_95___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__XLNA_GAIN_EVEN_95___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__LNA_GAIN_EVEN_95___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__LNA_GAIN_EVEN_95___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__GM_GAIN_EVEN_95___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__GM_GAIN_EVEN_95___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__TIA_GAIN_EVEN_95___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__TIA_GAIN_EVEN_95___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__SLM_XLNA_EVEN_95___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__SLM_XLNA_EVEN_95___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__BQ_GAIN_EVEN_95___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95__BQ_GAIN_EVEN_95___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_95___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96 (0x005ED180) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__XLNA_GAIN_ODD_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__LNA_GAIN_ODD_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__GM_GAIN_ODD_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__TIA_GAIN_ODD_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__SLM_XLNA_ODD_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__BQ_GAIN_ODD_96___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__XLNA_GAIN_EVEN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__LNA_GAIN_EVEN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__GM_GAIN_EVEN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__TIA_GAIN_EVEN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__SLM_XLNA_EVEN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__BQ_GAIN_EVEN_96___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__XLNA_GAIN_ODD_96___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__XLNA_GAIN_ODD_96___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__LNA_GAIN_ODD_96___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__LNA_GAIN_ODD_96___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__GM_GAIN_ODD_96___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__GM_GAIN_ODD_96___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__TIA_GAIN_ODD_96___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__TIA_GAIN_ODD_96___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__SLM_XLNA_ODD_96___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__SLM_XLNA_ODD_96___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__BQ_GAIN_ODD_96___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__BQ_GAIN_ODD_96___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__XLNA_GAIN_EVEN_96___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__XLNA_GAIN_EVEN_96___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__LNA_GAIN_EVEN_96___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__LNA_GAIN_EVEN_96___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__GM_GAIN_EVEN_96___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__GM_GAIN_EVEN_96___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__TIA_GAIN_EVEN_96___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__TIA_GAIN_EVEN_96___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__SLM_XLNA_EVEN_96___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__SLM_XLNA_EVEN_96___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__BQ_GAIN_EVEN_96___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96__BQ_GAIN_EVEN_96___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_96___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97 (0x005ED184) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__XLNA_GAIN_ODD_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__LNA_GAIN_ODD_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__GM_GAIN_ODD_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__TIA_GAIN_ODD_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__SLM_XLNA_ODD_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__BQ_GAIN_ODD_97___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__XLNA_GAIN_EVEN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__LNA_GAIN_EVEN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__GM_GAIN_EVEN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__TIA_GAIN_EVEN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__SLM_XLNA_EVEN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__BQ_GAIN_EVEN_97___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__XLNA_GAIN_ODD_97___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__XLNA_GAIN_ODD_97___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__LNA_GAIN_ODD_97___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__LNA_GAIN_ODD_97___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__GM_GAIN_ODD_97___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__GM_GAIN_ODD_97___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__TIA_GAIN_ODD_97___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__TIA_GAIN_ODD_97___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__SLM_XLNA_ODD_97___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__SLM_XLNA_ODD_97___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__BQ_GAIN_ODD_97___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__BQ_GAIN_ODD_97___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__XLNA_GAIN_EVEN_97___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__XLNA_GAIN_EVEN_97___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__LNA_GAIN_EVEN_97___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__LNA_GAIN_EVEN_97___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__GM_GAIN_EVEN_97___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__GM_GAIN_EVEN_97___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__TIA_GAIN_EVEN_97___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__TIA_GAIN_EVEN_97___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__SLM_XLNA_EVEN_97___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__SLM_XLNA_EVEN_97___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__BQ_GAIN_EVEN_97___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97__BQ_GAIN_EVEN_97___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_97___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98 (0x005ED188) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__XLNA_GAIN_ODD_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__LNA_GAIN_ODD_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__GM_GAIN_ODD_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__TIA_GAIN_ODD_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__SLM_XLNA_ODD_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__BQ_GAIN_ODD_98___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__XLNA_GAIN_EVEN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__LNA_GAIN_EVEN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__GM_GAIN_EVEN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__TIA_GAIN_EVEN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__SLM_XLNA_EVEN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__BQ_GAIN_EVEN_98___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__XLNA_GAIN_ODD_98___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__XLNA_GAIN_ODD_98___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__LNA_GAIN_ODD_98___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__LNA_GAIN_ODD_98___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__GM_GAIN_ODD_98___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__GM_GAIN_ODD_98___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__TIA_GAIN_ODD_98___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__TIA_GAIN_ODD_98___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__SLM_XLNA_ODD_98___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__SLM_XLNA_ODD_98___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__BQ_GAIN_ODD_98___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__BQ_GAIN_ODD_98___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__XLNA_GAIN_EVEN_98___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__XLNA_GAIN_EVEN_98___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__LNA_GAIN_EVEN_98___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__LNA_GAIN_EVEN_98___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__GM_GAIN_EVEN_98___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__GM_GAIN_EVEN_98___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__TIA_GAIN_EVEN_98___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__TIA_GAIN_EVEN_98___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__SLM_XLNA_EVEN_98___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__SLM_XLNA_EVEN_98___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__BQ_GAIN_EVEN_98___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98__BQ_GAIN_EVEN_98___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_98___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99 (0x005ED18C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__XLNA_GAIN_ODD_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__LNA_GAIN_ODD_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__GM_GAIN_ODD_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__TIA_GAIN_ODD_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__SLM_XLNA_ODD_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__BQ_GAIN_ODD_99___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__XLNA_GAIN_EVEN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__LNA_GAIN_EVEN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__GM_GAIN_EVEN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__TIA_GAIN_EVEN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__SLM_XLNA_EVEN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__BQ_GAIN_EVEN_99___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__XLNA_GAIN_ODD_99___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__XLNA_GAIN_ODD_99___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__LNA_GAIN_ODD_99___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__LNA_GAIN_ODD_99___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__GM_GAIN_ODD_99___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__GM_GAIN_ODD_99___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__TIA_GAIN_ODD_99___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__TIA_GAIN_ODD_99___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__SLM_XLNA_ODD_99___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__SLM_XLNA_ODD_99___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__BQ_GAIN_ODD_99___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__BQ_GAIN_ODD_99___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__XLNA_GAIN_EVEN_99___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__XLNA_GAIN_EVEN_99___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__LNA_GAIN_EVEN_99___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__LNA_GAIN_EVEN_99___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__GM_GAIN_EVEN_99___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__GM_GAIN_EVEN_99___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__TIA_GAIN_EVEN_99___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__TIA_GAIN_EVEN_99___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__SLM_XLNA_EVEN_99___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__SLM_XLNA_EVEN_99___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__BQ_GAIN_EVEN_99___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99__BQ_GAIN_EVEN_99___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_99___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100 (0x005ED190) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__XLNA_GAIN_ODD_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__LNA_GAIN_ODD_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__GM_GAIN_ODD_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__TIA_GAIN_ODD_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__SLM_XLNA_ODD_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__BQ_GAIN_ODD_100___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__XLNA_GAIN_EVEN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__LNA_GAIN_EVEN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__GM_GAIN_EVEN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__TIA_GAIN_EVEN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__SLM_XLNA_EVEN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__BQ_GAIN_EVEN_100___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__XLNA_GAIN_ODD_100___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__XLNA_GAIN_ODD_100___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__LNA_GAIN_ODD_100___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__LNA_GAIN_ODD_100___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__GM_GAIN_ODD_100___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__GM_GAIN_ODD_100___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__TIA_GAIN_ODD_100___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__TIA_GAIN_ODD_100___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__SLM_XLNA_ODD_100___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__SLM_XLNA_ODD_100___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__BQ_GAIN_ODD_100___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__BQ_GAIN_ODD_100___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__XLNA_GAIN_EVEN_100___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__XLNA_GAIN_EVEN_100___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__LNA_GAIN_EVEN_100___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__LNA_GAIN_EVEN_100___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__GM_GAIN_EVEN_100___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__GM_GAIN_EVEN_100___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__TIA_GAIN_EVEN_100___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__TIA_GAIN_EVEN_100___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__SLM_XLNA_EVEN_100___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__SLM_XLNA_EVEN_100___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__BQ_GAIN_EVEN_100___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100__BQ_GAIN_EVEN_100___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_100___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101 (0x005ED194) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__XLNA_GAIN_ODD_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__LNA_GAIN_ODD_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__GM_GAIN_ODD_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__TIA_GAIN_ODD_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__SLM_XLNA_ODD_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__BQ_GAIN_ODD_101___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__XLNA_GAIN_EVEN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__LNA_GAIN_EVEN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__GM_GAIN_EVEN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__TIA_GAIN_EVEN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__SLM_XLNA_EVEN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__BQ_GAIN_EVEN_101___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__XLNA_GAIN_ODD_101___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__XLNA_GAIN_ODD_101___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__LNA_GAIN_ODD_101___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__LNA_GAIN_ODD_101___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__GM_GAIN_ODD_101___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__GM_GAIN_ODD_101___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__TIA_GAIN_ODD_101___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__TIA_GAIN_ODD_101___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__SLM_XLNA_ODD_101___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__SLM_XLNA_ODD_101___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__BQ_GAIN_ODD_101___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__BQ_GAIN_ODD_101___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__XLNA_GAIN_EVEN_101___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__XLNA_GAIN_EVEN_101___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__LNA_GAIN_EVEN_101___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__LNA_GAIN_EVEN_101___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__GM_GAIN_EVEN_101___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__GM_GAIN_EVEN_101___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__TIA_GAIN_EVEN_101___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__TIA_GAIN_EVEN_101___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__SLM_XLNA_EVEN_101___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__SLM_XLNA_EVEN_101___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__BQ_GAIN_EVEN_101___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101__BQ_GAIN_EVEN_101___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_101___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102 (0x005ED198) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__XLNA_GAIN_ODD_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__LNA_GAIN_ODD_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__GM_GAIN_ODD_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__TIA_GAIN_ODD_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__SLM_XLNA_ODD_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__BQ_GAIN_ODD_102___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__XLNA_GAIN_EVEN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__LNA_GAIN_EVEN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__GM_GAIN_EVEN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__TIA_GAIN_EVEN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__SLM_XLNA_EVEN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__BQ_GAIN_EVEN_102___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__XLNA_GAIN_ODD_102___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__XLNA_GAIN_ODD_102___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__LNA_GAIN_ODD_102___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__LNA_GAIN_ODD_102___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__GM_GAIN_ODD_102___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__GM_GAIN_ODD_102___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__TIA_GAIN_ODD_102___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__TIA_GAIN_ODD_102___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__SLM_XLNA_ODD_102___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__SLM_XLNA_ODD_102___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__BQ_GAIN_ODD_102___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__BQ_GAIN_ODD_102___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__XLNA_GAIN_EVEN_102___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__XLNA_GAIN_EVEN_102___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__LNA_GAIN_EVEN_102___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__LNA_GAIN_EVEN_102___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__GM_GAIN_EVEN_102___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__GM_GAIN_EVEN_102___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__TIA_GAIN_EVEN_102___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__TIA_GAIN_EVEN_102___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__SLM_XLNA_EVEN_102___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__SLM_XLNA_EVEN_102___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__BQ_GAIN_EVEN_102___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102__BQ_GAIN_EVEN_102___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_102___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103 (0x005ED19C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__XLNA_GAIN_ODD_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__LNA_GAIN_ODD_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__GM_GAIN_ODD_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__TIA_GAIN_ODD_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__SLM_XLNA_ODD_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__BQ_GAIN_ODD_103___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__XLNA_GAIN_EVEN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__LNA_GAIN_EVEN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__GM_GAIN_EVEN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__TIA_GAIN_EVEN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__SLM_XLNA_EVEN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__BQ_GAIN_EVEN_103___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__XLNA_GAIN_ODD_103___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__XLNA_GAIN_ODD_103___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__LNA_GAIN_ODD_103___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__LNA_GAIN_ODD_103___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__GM_GAIN_ODD_103___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__GM_GAIN_ODD_103___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__TIA_GAIN_ODD_103___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__TIA_GAIN_ODD_103___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__SLM_XLNA_ODD_103___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__SLM_XLNA_ODD_103___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__BQ_GAIN_ODD_103___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__BQ_GAIN_ODD_103___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__XLNA_GAIN_EVEN_103___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__XLNA_GAIN_EVEN_103___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__LNA_GAIN_EVEN_103___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__LNA_GAIN_EVEN_103___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__GM_GAIN_EVEN_103___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__GM_GAIN_EVEN_103___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__TIA_GAIN_EVEN_103___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__TIA_GAIN_EVEN_103___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__SLM_XLNA_EVEN_103___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__SLM_XLNA_EVEN_103___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__BQ_GAIN_EVEN_103___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103__BQ_GAIN_EVEN_103___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_103___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104 (0x005ED1A0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__XLNA_GAIN_ODD_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__LNA_GAIN_ODD_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__GM_GAIN_ODD_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__TIA_GAIN_ODD_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__SLM_XLNA_ODD_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__BQ_GAIN_ODD_104___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__XLNA_GAIN_EVEN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__LNA_GAIN_EVEN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__GM_GAIN_EVEN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__TIA_GAIN_EVEN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__SLM_XLNA_EVEN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__BQ_GAIN_EVEN_104___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__XLNA_GAIN_ODD_104___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__XLNA_GAIN_ODD_104___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__LNA_GAIN_ODD_104___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__LNA_GAIN_ODD_104___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__GM_GAIN_ODD_104___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__GM_GAIN_ODD_104___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__TIA_GAIN_ODD_104___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__TIA_GAIN_ODD_104___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__SLM_XLNA_ODD_104___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__SLM_XLNA_ODD_104___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__BQ_GAIN_ODD_104___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__BQ_GAIN_ODD_104___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__XLNA_GAIN_EVEN_104___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__XLNA_GAIN_EVEN_104___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__LNA_GAIN_EVEN_104___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__LNA_GAIN_EVEN_104___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__GM_GAIN_EVEN_104___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__GM_GAIN_EVEN_104___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__TIA_GAIN_EVEN_104___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__TIA_GAIN_EVEN_104___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__SLM_XLNA_EVEN_104___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__SLM_XLNA_EVEN_104___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__BQ_GAIN_EVEN_104___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104__BQ_GAIN_EVEN_104___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_104___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105 (0x005ED1A4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__XLNA_GAIN_ODD_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__LNA_GAIN_ODD_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__GM_GAIN_ODD_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__TIA_GAIN_ODD_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__SLM_XLNA_ODD_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__BQ_GAIN_ODD_105___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__XLNA_GAIN_EVEN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__LNA_GAIN_EVEN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__GM_GAIN_EVEN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__TIA_GAIN_EVEN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__SLM_XLNA_EVEN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__BQ_GAIN_EVEN_105___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__XLNA_GAIN_ODD_105___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__XLNA_GAIN_ODD_105___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__LNA_GAIN_ODD_105___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__LNA_GAIN_ODD_105___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__GM_GAIN_ODD_105___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__GM_GAIN_ODD_105___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__TIA_GAIN_ODD_105___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__TIA_GAIN_ODD_105___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__SLM_XLNA_ODD_105___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__SLM_XLNA_ODD_105___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__BQ_GAIN_ODD_105___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__BQ_GAIN_ODD_105___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__XLNA_GAIN_EVEN_105___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__XLNA_GAIN_EVEN_105___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__LNA_GAIN_EVEN_105___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__LNA_GAIN_EVEN_105___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__GM_GAIN_EVEN_105___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__GM_GAIN_EVEN_105___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__TIA_GAIN_EVEN_105___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__TIA_GAIN_EVEN_105___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__SLM_XLNA_EVEN_105___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__SLM_XLNA_EVEN_105___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__BQ_GAIN_EVEN_105___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105__BQ_GAIN_EVEN_105___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_105___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106 (0x005ED1A8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__XLNA_GAIN_ODD_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__LNA_GAIN_ODD_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__GM_GAIN_ODD_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__TIA_GAIN_ODD_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__SLM_XLNA_ODD_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__BQ_GAIN_ODD_106___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__XLNA_GAIN_EVEN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__LNA_GAIN_EVEN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__GM_GAIN_EVEN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__TIA_GAIN_EVEN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__SLM_XLNA_EVEN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__BQ_GAIN_EVEN_106___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__XLNA_GAIN_ODD_106___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__XLNA_GAIN_ODD_106___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__LNA_GAIN_ODD_106___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__LNA_GAIN_ODD_106___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__GM_GAIN_ODD_106___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__GM_GAIN_ODD_106___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__TIA_GAIN_ODD_106___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__TIA_GAIN_ODD_106___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__SLM_XLNA_ODD_106___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__SLM_XLNA_ODD_106___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__BQ_GAIN_ODD_106___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__BQ_GAIN_ODD_106___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__XLNA_GAIN_EVEN_106___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__XLNA_GAIN_EVEN_106___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__LNA_GAIN_EVEN_106___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__LNA_GAIN_EVEN_106___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__GM_GAIN_EVEN_106___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__GM_GAIN_EVEN_106___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__TIA_GAIN_EVEN_106___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__TIA_GAIN_EVEN_106___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__SLM_XLNA_EVEN_106___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__SLM_XLNA_EVEN_106___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__BQ_GAIN_EVEN_106___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106__BQ_GAIN_EVEN_106___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_106___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107 (0x005ED1AC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__XLNA_GAIN_ODD_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__LNA_GAIN_ODD_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__GM_GAIN_ODD_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__TIA_GAIN_ODD_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__SLM_XLNA_ODD_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__BQ_GAIN_ODD_107___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__XLNA_GAIN_EVEN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__LNA_GAIN_EVEN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__GM_GAIN_EVEN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__TIA_GAIN_EVEN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__SLM_XLNA_EVEN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__BQ_GAIN_EVEN_107___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__XLNA_GAIN_ODD_107___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__XLNA_GAIN_ODD_107___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__LNA_GAIN_ODD_107___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__LNA_GAIN_ODD_107___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__GM_GAIN_ODD_107___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__GM_GAIN_ODD_107___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__TIA_GAIN_ODD_107___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__TIA_GAIN_ODD_107___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__SLM_XLNA_ODD_107___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__SLM_XLNA_ODD_107___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__BQ_GAIN_ODD_107___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__BQ_GAIN_ODD_107___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__XLNA_GAIN_EVEN_107___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__XLNA_GAIN_EVEN_107___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__LNA_GAIN_EVEN_107___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__LNA_GAIN_EVEN_107___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__GM_GAIN_EVEN_107___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__GM_GAIN_EVEN_107___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__TIA_GAIN_EVEN_107___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__TIA_GAIN_EVEN_107___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__SLM_XLNA_EVEN_107___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__SLM_XLNA_EVEN_107___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__BQ_GAIN_EVEN_107___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107__BQ_GAIN_EVEN_107___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_107___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108 (0x005ED1B0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__XLNA_GAIN_ODD_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__LNA_GAIN_ODD_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__GM_GAIN_ODD_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__TIA_GAIN_ODD_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__SLM_XLNA_ODD_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__BQ_GAIN_ODD_108___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__XLNA_GAIN_EVEN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__LNA_GAIN_EVEN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__GM_GAIN_EVEN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__TIA_GAIN_EVEN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__SLM_XLNA_EVEN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__BQ_GAIN_EVEN_108___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__XLNA_GAIN_ODD_108___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__XLNA_GAIN_ODD_108___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__LNA_GAIN_ODD_108___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__LNA_GAIN_ODD_108___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__GM_GAIN_ODD_108___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__GM_GAIN_ODD_108___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__TIA_GAIN_ODD_108___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__TIA_GAIN_ODD_108___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__SLM_XLNA_ODD_108___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__SLM_XLNA_ODD_108___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__BQ_GAIN_ODD_108___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__BQ_GAIN_ODD_108___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__XLNA_GAIN_EVEN_108___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__XLNA_GAIN_EVEN_108___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__LNA_GAIN_EVEN_108___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__LNA_GAIN_EVEN_108___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__GM_GAIN_EVEN_108___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__GM_GAIN_EVEN_108___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__TIA_GAIN_EVEN_108___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__TIA_GAIN_EVEN_108___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__SLM_XLNA_EVEN_108___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__SLM_XLNA_EVEN_108___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__BQ_GAIN_EVEN_108___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108__BQ_GAIN_EVEN_108___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_108___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109 (0x005ED1B4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__XLNA_GAIN_ODD_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__LNA_GAIN_ODD_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__GM_GAIN_ODD_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__TIA_GAIN_ODD_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__SLM_XLNA_ODD_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__BQ_GAIN_ODD_109___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__XLNA_GAIN_EVEN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__LNA_GAIN_EVEN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__GM_GAIN_EVEN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__TIA_GAIN_EVEN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__SLM_XLNA_EVEN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__BQ_GAIN_EVEN_109___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__XLNA_GAIN_ODD_109___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__XLNA_GAIN_ODD_109___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__LNA_GAIN_ODD_109___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__LNA_GAIN_ODD_109___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__GM_GAIN_ODD_109___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__GM_GAIN_ODD_109___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__TIA_GAIN_ODD_109___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__TIA_GAIN_ODD_109___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__SLM_XLNA_ODD_109___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__SLM_XLNA_ODD_109___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__BQ_GAIN_ODD_109___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__BQ_GAIN_ODD_109___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__XLNA_GAIN_EVEN_109___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__XLNA_GAIN_EVEN_109___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__LNA_GAIN_EVEN_109___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__LNA_GAIN_EVEN_109___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__GM_GAIN_EVEN_109___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__GM_GAIN_EVEN_109___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__TIA_GAIN_EVEN_109___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__TIA_GAIN_EVEN_109___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__SLM_XLNA_EVEN_109___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__SLM_XLNA_EVEN_109___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__BQ_GAIN_EVEN_109___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109__BQ_GAIN_EVEN_109___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_109___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110 (0x005ED1B8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__XLNA_GAIN_ODD_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__LNA_GAIN_ODD_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__GM_GAIN_ODD_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__TIA_GAIN_ODD_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__SLM_XLNA_ODD_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__BQ_GAIN_ODD_110___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__XLNA_GAIN_EVEN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__LNA_GAIN_EVEN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__GM_GAIN_EVEN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__TIA_GAIN_EVEN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__SLM_XLNA_EVEN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__BQ_GAIN_EVEN_110___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__XLNA_GAIN_ODD_110___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__XLNA_GAIN_ODD_110___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__LNA_GAIN_ODD_110___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__LNA_GAIN_ODD_110___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__GM_GAIN_ODD_110___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__GM_GAIN_ODD_110___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__TIA_GAIN_ODD_110___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__TIA_GAIN_ODD_110___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__SLM_XLNA_ODD_110___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__SLM_XLNA_ODD_110___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__BQ_GAIN_ODD_110___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__BQ_GAIN_ODD_110___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__XLNA_GAIN_EVEN_110___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__XLNA_GAIN_EVEN_110___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__LNA_GAIN_EVEN_110___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__LNA_GAIN_EVEN_110___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__GM_GAIN_EVEN_110___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__GM_GAIN_EVEN_110___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__TIA_GAIN_EVEN_110___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__TIA_GAIN_EVEN_110___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__SLM_XLNA_EVEN_110___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__SLM_XLNA_EVEN_110___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__BQ_GAIN_EVEN_110___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110__BQ_GAIN_EVEN_110___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_110___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111 (0x005ED1BC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__XLNA_GAIN_ODD_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__LNA_GAIN_ODD_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__GM_GAIN_ODD_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__TIA_GAIN_ODD_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__SLM_XLNA_ODD_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__BQ_GAIN_ODD_111___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__XLNA_GAIN_EVEN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__LNA_GAIN_EVEN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__GM_GAIN_EVEN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__TIA_GAIN_EVEN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__SLM_XLNA_EVEN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__BQ_GAIN_EVEN_111___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__XLNA_GAIN_ODD_111___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__XLNA_GAIN_ODD_111___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__LNA_GAIN_ODD_111___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__LNA_GAIN_ODD_111___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__GM_GAIN_ODD_111___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__GM_GAIN_ODD_111___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__TIA_GAIN_ODD_111___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__TIA_GAIN_ODD_111___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__SLM_XLNA_ODD_111___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__SLM_XLNA_ODD_111___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__BQ_GAIN_ODD_111___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__BQ_GAIN_ODD_111___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__XLNA_GAIN_EVEN_111___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__XLNA_GAIN_EVEN_111___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__LNA_GAIN_EVEN_111___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__LNA_GAIN_EVEN_111___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__GM_GAIN_EVEN_111___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__GM_GAIN_EVEN_111___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__TIA_GAIN_EVEN_111___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__TIA_GAIN_EVEN_111___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__SLM_XLNA_EVEN_111___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__SLM_XLNA_EVEN_111___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__BQ_GAIN_EVEN_111___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111__BQ_GAIN_EVEN_111___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_111___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112 (0x005ED1C0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__XLNA_GAIN_ODD_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__LNA_GAIN_ODD_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__GM_GAIN_ODD_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__TIA_GAIN_ODD_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__SLM_XLNA_ODD_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__BQ_GAIN_ODD_112___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__XLNA_GAIN_EVEN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__LNA_GAIN_EVEN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__GM_GAIN_EVEN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__TIA_GAIN_EVEN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__SLM_XLNA_EVEN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__BQ_GAIN_EVEN_112___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__XLNA_GAIN_ODD_112___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__XLNA_GAIN_ODD_112___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__LNA_GAIN_ODD_112___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__LNA_GAIN_ODD_112___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__GM_GAIN_ODD_112___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__GM_GAIN_ODD_112___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__TIA_GAIN_ODD_112___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__TIA_GAIN_ODD_112___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__SLM_XLNA_ODD_112___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__SLM_XLNA_ODD_112___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__BQ_GAIN_ODD_112___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__BQ_GAIN_ODD_112___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__XLNA_GAIN_EVEN_112___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__XLNA_GAIN_EVEN_112___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__LNA_GAIN_EVEN_112___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__LNA_GAIN_EVEN_112___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__GM_GAIN_EVEN_112___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__GM_GAIN_EVEN_112___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__TIA_GAIN_EVEN_112___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__TIA_GAIN_EVEN_112___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__SLM_XLNA_EVEN_112___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__SLM_XLNA_EVEN_112___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__BQ_GAIN_EVEN_112___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112__BQ_GAIN_EVEN_112___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_112___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113 (0x005ED1C4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__XLNA_GAIN_ODD_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__LNA_GAIN_ODD_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__GM_GAIN_ODD_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__TIA_GAIN_ODD_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__SLM_XLNA_ODD_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__BQ_GAIN_ODD_113___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__XLNA_GAIN_EVEN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__LNA_GAIN_EVEN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__GM_GAIN_EVEN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__TIA_GAIN_EVEN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__SLM_XLNA_EVEN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__BQ_GAIN_EVEN_113___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__XLNA_GAIN_ODD_113___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__XLNA_GAIN_ODD_113___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__LNA_GAIN_ODD_113___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__LNA_GAIN_ODD_113___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__GM_GAIN_ODD_113___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__GM_GAIN_ODD_113___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__TIA_GAIN_ODD_113___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__TIA_GAIN_ODD_113___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__SLM_XLNA_ODD_113___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__SLM_XLNA_ODD_113___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__BQ_GAIN_ODD_113___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__BQ_GAIN_ODD_113___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__XLNA_GAIN_EVEN_113___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__XLNA_GAIN_EVEN_113___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__LNA_GAIN_EVEN_113___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__LNA_GAIN_EVEN_113___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__GM_GAIN_EVEN_113___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__GM_GAIN_EVEN_113___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__TIA_GAIN_EVEN_113___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__TIA_GAIN_EVEN_113___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__SLM_XLNA_EVEN_113___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__SLM_XLNA_EVEN_113___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__BQ_GAIN_EVEN_113___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113__BQ_GAIN_EVEN_113___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_113___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114 (0x005ED1C8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__XLNA_GAIN_ODD_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__LNA_GAIN_ODD_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__GM_GAIN_ODD_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__TIA_GAIN_ODD_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__SLM_XLNA_ODD_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__BQ_GAIN_ODD_114___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__XLNA_GAIN_EVEN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__LNA_GAIN_EVEN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__GM_GAIN_EVEN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__TIA_GAIN_EVEN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__SLM_XLNA_EVEN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__BQ_GAIN_EVEN_114___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__XLNA_GAIN_ODD_114___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__XLNA_GAIN_ODD_114___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__LNA_GAIN_ODD_114___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__LNA_GAIN_ODD_114___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__GM_GAIN_ODD_114___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__GM_GAIN_ODD_114___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__TIA_GAIN_ODD_114___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__TIA_GAIN_ODD_114___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__SLM_XLNA_ODD_114___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__SLM_XLNA_ODD_114___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__BQ_GAIN_ODD_114___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__BQ_GAIN_ODD_114___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__XLNA_GAIN_EVEN_114___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__XLNA_GAIN_EVEN_114___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__LNA_GAIN_EVEN_114___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__LNA_GAIN_EVEN_114___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__GM_GAIN_EVEN_114___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__GM_GAIN_EVEN_114___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__TIA_GAIN_EVEN_114___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__TIA_GAIN_EVEN_114___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__SLM_XLNA_EVEN_114___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__SLM_XLNA_EVEN_114___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__BQ_GAIN_EVEN_114___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114__BQ_GAIN_EVEN_114___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_114___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115 (0x005ED1CC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__XLNA_GAIN_ODD_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__LNA_GAIN_ODD_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__GM_GAIN_ODD_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__TIA_GAIN_ODD_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__SLM_XLNA_ODD_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__BQ_GAIN_ODD_115___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__XLNA_GAIN_EVEN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__LNA_GAIN_EVEN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__GM_GAIN_EVEN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__TIA_GAIN_EVEN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__SLM_XLNA_EVEN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__BQ_GAIN_EVEN_115___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__XLNA_GAIN_ODD_115___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__XLNA_GAIN_ODD_115___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__LNA_GAIN_ODD_115___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__LNA_GAIN_ODD_115___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__GM_GAIN_ODD_115___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__GM_GAIN_ODD_115___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__TIA_GAIN_ODD_115___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__TIA_GAIN_ODD_115___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__SLM_XLNA_ODD_115___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__SLM_XLNA_ODD_115___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__BQ_GAIN_ODD_115___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__BQ_GAIN_ODD_115___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__XLNA_GAIN_EVEN_115___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__XLNA_GAIN_EVEN_115___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__LNA_GAIN_EVEN_115___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__LNA_GAIN_EVEN_115___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__GM_GAIN_EVEN_115___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__GM_GAIN_EVEN_115___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__TIA_GAIN_EVEN_115___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__TIA_GAIN_EVEN_115___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__SLM_XLNA_EVEN_115___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__SLM_XLNA_EVEN_115___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__BQ_GAIN_EVEN_115___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115__BQ_GAIN_EVEN_115___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_115___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116 (0x005ED1D0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__XLNA_GAIN_ODD_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__LNA_GAIN_ODD_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__GM_GAIN_ODD_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__TIA_GAIN_ODD_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__SLM_XLNA_ODD_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__BQ_GAIN_ODD_116___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__XLNA_GAIN_EVEN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__LNA_GAIN_EVEN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__GM_GAIN_EVEN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__TIA_GAIN_EVEN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__SLM_XLNA_EVEN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__BQ_GAIN_EVEN_116___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__XLNA_GAIN_ODD_116___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__XLNA_GAIN_ODD_116___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__LNA_GAIN_ODD_116___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__LNA_GAIN_ODD_116___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__GM_GAIN_ODD_116___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__GM_GAIN_ODD_116___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__TIA_GAIN_ODD_116___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__TIA_GAIN_ODD_116___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__SLM_XLNA_ODD_116___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__SLM_XLNA_ODD_116___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__BQ_GAIN_ODD_116___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__BQ_GAIN_ODD_116___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__XLNA_GAIN_EVEN_116___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__XLNA_GAIN_EVEN_116___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__LNA_GAIN_EVEN_116___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__LNA_GAIN_EVEN_116___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__GM_GAIN_EVEN_116___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__GM_GAIN_EVEN_116___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__TIA_GAIN_EVEN_116___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__TIA_GAIN_EVEN_116___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__SLM_XLNA_EVEN_116___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__SLM_XLNA_EVEN_116___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__BQ_GAIN_EVEN_116___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116__BQ_GAIN_EVEN_116___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_116___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117 (0x005ED1D4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__XLNA_GAIN_ODD_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__LNA_GAIN_ODD_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__GM_GAIN_ODD_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__TIA_GAIN_ODD_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__SLM_XLNA_ODD_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__BQ_GAIN_ODD_117___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__XLNA_GAIN_EVEN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__LNA_GAIN_EVEN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__GM_GAIN_EVEN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__TIA_GAIN_EVEN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__SLM_XLNA_EVEN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__BQ_GAIN_EVEN_117___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__XLNA_GAIN_ODD_117___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__XLNA_GAIN_ODD_117___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__LNA_GAIN_ODD_117___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__LNA_GAIN_ODD_117___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__GM_GAIN_ODD_117___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__GM_GAIN_ODD_117___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__TIA_GAIN_ODD_117___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__TIA_GAIN_ODD_117___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__SLM_XLNA_ODD_117___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__SLM_XLNA_ODD_117___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__BQ_GAIN_ODD_117___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__BQ_GAIN_ODD_117___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__XLNA_GAIN_EVEN_117___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__XLNA_GAIN_EVEN_117___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__LNA_GAIN_EVEN_117___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__LNA_GAIN_EVEN_117___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__GM_GAIN_EVEN_117___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__GM_GAIN_EVEN_117___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__TIA_GAIN_EVEN_117___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__TIA_GAIN_EVEN_117___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__SLM_XLNA_EVEN_117___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__SLM_XLNA_EVEN_117___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__BQ_GAIN_EVEN_117___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117__BQ_GAIN_EVEN_117___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_117___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118 (0x005ED1D8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__XLNA_GAIN_ODD_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__LNA_GAIN_ODD_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__GM_GAIN_ODD_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__TIA_GAIN_ODD_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__SLM_XLNA_ODD_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__BQ_GAIN_ODD_118___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__XLNA_GAIN_EVEN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__LNA_GAIN_EVEN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__GM_GAIN_EVEN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__TIA_GAIN_EVEN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__SLM_XLNA_EVEN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__BQ_GAIN_EVEN_118___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__XLNA_GAIN_ODD_118___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__XLNA_GAIN_ODD_118___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__LNA_GAIN_ODD_118___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__LNA_GAIN_ODD_118___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__GM_GAIN_ODD_118___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__GM_GAIN_ODD_118___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__TIA_GAIN_ODD_118___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__TIA_GAIN_ODD_118___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__SLM_XLNA_ODD_118___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__SLM_XLNA_ODD_118___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__BQ_GAIN_ODD_118___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__BQ_GAIN_ODD_118___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__XLNA_GAIN_EVEN_118___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__XLNA_GAIN_EVEN_118___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__LNA_GAIN_EVEN_118___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__LNA_GAIN_EVEN_118___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__GM_GAIN_EVEN_118___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__GM_GAIN_EVEN_118___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__TIA_GAIN_EVEN_118___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__TIA_GAIN_EVEN_118___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__SLM_XLNA_EVEN_118___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__SLM_XLNA_EVEN_118___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__BQ_GAIN_EVEN_118___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118__BQ_GAIN_EVEN_118___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_118___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119 (0x005ED1DC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__XLNA_GAIN_ODD_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__LNA_GAIN_ODD_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__GM_GAIN_ODD_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__TIA_GAIN_ODD_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__SLM_XLNA_ODD_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__BQ_GAIN_ODD_119___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__XLNA_GAIN_EVEN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__LNA_GAIN_EVEN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__GM_GAIN_EVEN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__TIA_GAIN_EVEN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__SLM_XLNA_EVEN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__BQ_GAIN_EVEN_119___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__XLNA_GAIN_ODD_119___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__XLNA_GAIN_ODD_119___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__LNA_GAIN_ODD_119___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__LNA_GAIN_ODD_119___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__GM_GAIN_ODD_119___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__GM_GAIN_ODD_119___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__TIA_GAIN_ODD_119___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__TIA_GAIN_ODD_119___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__SLM_XLNA_ODD_119___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__SLM_XLNA_ODD_119___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__BQ_GAIN_ODD_119___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__BQ_GAIN_ODD_119___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__XLNA_GAIN_EVEN_119___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__XLNA_GAIN_EVEN_119___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__LNA_GAIN_EVEN_119___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__LNA_GAIN_EVEN_119___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__GM_GAIN_EVEN_119___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__GM_GAIN_EVEN_119___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__TIA_GAIN_EVEN_119___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__TIA_GAIN_EVEN_119___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__SLM_XLNA_EVEN_119___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__SLM_XLNA_EVEN_119___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__BQ_GAIN_EVEN_119___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119__BQ_GAIN_EVEN_119___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_119___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120 (0x005ED1E0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__XLNA_GAIN_ODD_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__LNA_GAIN_ODD_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__GM_GAIN_ODD_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__TIA_GAIN_ODD_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__SLM_XLNA_ODD_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__BQ_GAIN_ODD_120___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__XLNA_GAIN_EVEN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__LNA_GAIN_EVEN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__GM_GAIN_EVEN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__TIA_GAIN_EVEN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__SLM_XLNA_EVEN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__BQ_GAIN_EVEN_120___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__XLNA_GAIN_ODD_120___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__XLNA_GAIN_ODD_120___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__LNA_GAIN_ODD_120___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__LNA_GAIN_ODD_120___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__GM_GAIN_ODD_120___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__GM_GAIN_ODD_120___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__TIA_GAIN_ODD_120___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__TIA_GAIN_ODD_120___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__SLM_XLNA_ODD_120___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__SLM_XLNA_ODD_120___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__BQ_GAIN_ODD_120___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__BQ_GAIN_ODD_120___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__XLNA_GAIN_EVEN_120___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__XLNA_GAIN_EVEN_120___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__LNA_GAIN_EVEN_120___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__LNA_GAIN_EVEN_120___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__GM_GAIN_EVEN_120___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__GM_GAIN_EVEN_120___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__TIA_GAIN_EVEN_120___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__TIA_GAIN_EVEN_120___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__SLM_XLNA_EVEN_120___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__SLM_XLNA_EVEN_120___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__BQ_GAIN_EVEN_120___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120__BQ_GAIN_EVEN_120___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_120___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121 (0x005ED1E4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__XLNA_GAIN_ODD_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__LNA_GAIN_ODD_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__GM_GAIN_ODD_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__TIA_GAIN_ODD_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__SLM_XLNA_ODD_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__BQ_GAIN_ODD_121___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__XLNA_GAIN_EVEN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__LNA_GAIN_EVEN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__GM_GAIN_EVEN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__TIA_GAIN_EVEN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__SLM_XLNA_EVEN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__BQ_GAIN_EVEN_121___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__XLNA_GAIN_ODD_121___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__XLNA_GAIN_ODD_121___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__LNA_GAIN_ODD_121___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__LNA_GAIN_ODD_121___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__GM_GAIN_ODD_121___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__GM_GAIN_ODD_121___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__TIA_GAIN_ODD_121___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__TIA_GAIN_ODD_121___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__SLM_XLNA_ODD_121___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__SLM_XLNA_ODD_121___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__BQ_GAIN_ODD_121___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__BQ_GAIN_ODD_121___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__XLNA_GAIN_EVEN_121___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__XLNA_GAIN_EVEN_121___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__LNA_GAIN_EVEN_121___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__LNA_GAIN_EVEN_121___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__GM_GAIN_EVEN_121___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__GM_GAIN_EVEN_121___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__TIA_GAIN_EVEN_121___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__TIA_GAIN_EVEN_121___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__SLM_XLNA_EVEN_121___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__SLM_XLNA_EVEN_121___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__BQ_GAIN_EVEN_121___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121__BQ_GAIN_EVEN_121___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_121___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122 (0x005ED1E8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__XLNA_GAIN_ODD_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__LNA_GAIN_ODD_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__GM_GAIN_ODD_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__TIA_GAIN_ODD_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__SLM_XLNA_ODD_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__BQ_GAIN_ODD_122___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__XLNA_GAIN_EVEN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__LNA_GAIN_EVEN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__GM_GAIN_EVEN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__TIA_GAIN_EVEN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__SLM_XLNA_EVEN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__BQ_GAIN_EVEN_122___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__XLNA_GAIN_ODD_122___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__XLNA_GAIN_ODD_122___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__LNA_GAIN_ODD_122___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__LNA_GAIN_ODD_122___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__GM_GAIN_ODD_122___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__GM_GAIN_ODD_122___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__TIA_GAIN_ODD_122___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__TIA_GAIN_ODD_122___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__SLM_XLNA_ODD_122___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__SLM_XLNA_ODD_122___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__BQ_GAIN_ODD_122___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__BQ_GAIN_ODD_122___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__XLNA_GAIN_EVEN_122___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__XLNA_GAIN_EVEN_122___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__LNA_GAIN_EVEN_122___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__LNA_GAIN_EVEN_122___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__GM_GAIN_EVEN_122___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__GM_GAIN_EVEN_122___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__TIA_GAIN_EVEN_122___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__TIA_GAIN_EVEN_122___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__SLM_XLNA_EVEN_122___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__SLM_XLNA_EVEN_122___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__BQ_GAIN_EVEN_122___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122__BQ_GAIN_EVEN_122___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_122___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123 (0x005ED1EC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__XLNA_GAIN_ODD_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__LNA_GAIN_ODD_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__GM_GAIN_ODD_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__TIA_GAIN_ODD_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__SLM_XLNA_ODD_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__BQ_GAIN_ODD_123___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__XLNA_GAIN_EVEN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__LNA_GAIN_EVEN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__GM_GAIN_EVEN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__TIA_GAIN_EVEN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__SLM_XLNA_EVEN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__BQ_GAIN_EVEN_123___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__XLNA_GAIN_ODD_123___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__XLNA_GAIN_ODD_123___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__LNA_GAIN_ODD_123___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__LNA_GAIN_ODD_123___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__GM_GAIN_ODD_123___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__GM_GAIN_ODD_123___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__TIA_GAIN_ODD_123___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__TIA_GAIN_ODD_123___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__SLM_XLNA_ODD_123___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__SLM_XLNA_ODD_123___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__BQ_GAIN_ODD_123___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__BQ_GAIN_ODD_123___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__XLNA_GAIN_EVEN_123___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__XLNA_GAIN_EVEN_123___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__LNA_GAIN_EVEN_123___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__LNA_GAIN_EVEN_123___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__GM_GAIN_EVEN_123___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__GM_GAIN_EVEN_123___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__TIA_GAIN_EVEN_123___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__TIA_GAIN_EVEN_123___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__SLM_XLNA_EVEN_123___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__SLM_XLNA_EVEN_123___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__BQ_GAIN_EVEN_123___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123__BQ_GAIN_EVEN_123___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_123___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124 (0x005ED1F0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__XLNA_GAIN_ODD_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__LNA_GAIN_ODD_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__GM_GAIN_ODD_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__TIA_GAIN_ODD_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__SLM_XLNA_ODD_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__BQ_GAIN_ODD_124___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__XLNA_GAIN_EVEN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__LNA_GAIN_EVEN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__GM_GAIN_EVEN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__TIA_GAIN_EVEN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__SLM_XLNA_EVEN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__BQ_GAIN_EVEN_124___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__XLNA_GAIN_ODD_124___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__XLNA_GAIN_ODD_124___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__LNA_GAIN_ODD_124___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__LNA_GAIN_ODD_124___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__GM_GAIN_ODD_124___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__GM_GAIN_ODD_124___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__TIA_GAIN_ODD_124___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__TIA_GAIN_ODD_124___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__SLM_XLNA_ODD_124___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__SLM_XLNA_ODD_124___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__BQ_GAIN_ODD_124___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__BQ_GAIN_ODD_124___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__XLNA_GAIN_EVEN_124___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__XLNA_GAIN_EVEN_124___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__LNA_GAIN_EVEN_124___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__LNA_GAIN_EVEN_124___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__GM_GAIN_EVEN_124___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__GM_GAIN_EVEN_124___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__TIA_GAIN_EVEN_124___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__TIA_GAIN_EVEN_124___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__SLM_XLNA_EVEN_124___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__SLM_XLNA_EVEN_124___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__BQ_GAIN_EVEN_124___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124__BQ_GAIN_EVEN_124___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_124___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125 (0x005ED1F4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__XLNA_GAIN_ODD_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__LNA_GAIN_ODD_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__GM_GAIN_ODD_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__TIA_GAIN_ODD_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__SLM_XLNA_ODD_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__BQ_GAIN_ODD_125___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__XLNA_GAIN_EVEN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__LNA_GAIN_EVEN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__GM_GAIN_EVEN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__TIA_GAIN_EVEN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__SLM_XLNA_EVEN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__BQ_GAIN_EVEN_125___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__XLNA_GAIN_ODD_125___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__XLNA_GAIN_ODD_125___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__LNA_GAIN_ODD_125___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__LNA_GAIN_ODD_125___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__GM_GAIN_ODD_125___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__GM_GAIN_ODD_125___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__TIA_GAIN_ODD_125___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__TIA_GAIN_ODD_125___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__SLM_XLNA_ODD_125___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__SLM_XLNA_ODD_125___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__BQ_GAIN_ODD_125___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__BQ_GAIN_ODD_125___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__XLNA_GAIN_EVEN_125___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__XLNA_GAIN_EVEN_125___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__LNA_GAIN_EVEN_125___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__LNA_GAIN_EVEN_125___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__GM_GAIN_EVEN_125___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__GM_GAIN_EVEN_125___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__TIA_GAIN_EVEN_125___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__TIA_GAIN_EVEN_125___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__SLM_XLNA_EVEN_125___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__SLM_XLNA_EVEN_125___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__BQ_GAIN_EVEN_125___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125__BQ_GAIN_EVEN_125___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_125___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126 (0x005ED1F8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__XLNA_GAIN_ODD_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__LNA_GAIN_ODD_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__GM_GAIN_ODD_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__TIA_GAIN_ODD_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__SLM_XLNA_ODD_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__BQ_GAIN_ODD_126___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__XLNA_GAIN_EVEN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__LNA_GAIN_EVEN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__GM_GAIN_EVEN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__TIA_GAIN_EVEN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__SLM_XLNA_EVEN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__BQ_GAIN_EVEN_126___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__XLNA_GAIN_ODD_126___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__XLNA_GAIN_ODD_126___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__LNA_GAIN_ODD_126___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__LNA_GAIN_ODD_126___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__GM_GAIN_ODD_126___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__GM_GAIN_ODD_126___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__TIA_GAIN_ODD_126___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__TIA_GAIN_ODD_126___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__SLM_XLNA_ODD_126___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__SLM_XLNA_ODD_126___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__BQ_GAIN_ODD_126___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__BQ_GAIN_ODD_126___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__XLNA_GAIN_EVEN_126___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__XLNA_GAIN_EVEN_126___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__LNA_GAIN_EVEN_126___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__LNA_GAIN_EVEN_126___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__GM_GAIN_EVEN_126___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__GM_GAIN_EVEN_126___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__TIA_GAIN_EVEN_126___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__TIA_GAIN_EVEN_126___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__SLM_XLNA_EVEN_126___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__SLM_XLNA_EVEN_126___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__BQ_GAIN_EVEN_126___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126__BQ_GAIN_EVEN_126___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_126___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127 (0x005ED1FC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__XLNA_GAIN_ODD_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__LNA_GAIN_ODD_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__GM_GAIN_ODD_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__TIA_GAIN_ODD_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__SLM_XLNA_ODD_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__BQ_GAIN_ODD_127___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__XLNA_GAIN_EVEN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__LNA_GAIN_EVEN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__GM_GAIN_EVEN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__TIA_GAIN_EVEN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__SLM_XLNA_EVEN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__BQ_GAIN_EVEN_127___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__XLNA_GAIN_ODD_127___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__XLNA_GAIN_ODD_127___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__LNA_GAIN_ODD_127___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__LNA_GAIN_ODD_127___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__GM_GAIN_ODD_127___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__GM_GAIN_ODD_127___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__TIA_GAIN_ODD_127___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__TIA_GAIN_ODD_127___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__SLM_XLNA_ODD_127___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__SLM_XLNA_ODD_127___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__BQ_GAIN_ODD_127___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__BQ_GAIN_ODD_127___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__XLNA_GAIN_EVEN_127___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__XLNA_GAIN_EVEN_127___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__LNA_GAIN_EVEN_127___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__LNA_GAIN_EVEN_127___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__GM_GAIN_EVEN_127___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__GM_GAIN_EVEN_127___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__TIA_GAIN_EVEN_127___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__TIA_GAIN_EVEN_127___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__SLM_XLNA_EVEN_127___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__SLM_XLNA_EVEN_127___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__BQ_GAIN_EVEN_127___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127__BQ_GAIN_EVEN_127___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_127___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128 (0x005ED200) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__XLNA_GAIN_ODD_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__LNA_GAIN_ODD_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__GM_GAIN_ODD_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__TIA_GAIN_ODD_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__SLM_XLNA_ODD_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__BQ_GAIN_ODD_128___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__XLNA_GAIN_EVEN_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__LNA_GAIN_EVEN_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__GM_GAIN_EVEN_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__TIA_GAIN_EVEN_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__SLM_XLNA_EVEN_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__BQ_GAIN_EVEN_128___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__XLNA_GAIN_ODD_128___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__XLNA_GAIN_ODD_128___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__LNA_GAIN_ODD_128___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__LNA_GAIN_ODD_128___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__GM_GAIN_ODD_128___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__GM_GAIN_ODD_128___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__TIA_GAIN_ODD_128___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__TIA_GAIN_ODD_128___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__SLM_XLNA_ODD_128___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__SLM_XLNA_ODD_128___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__BQ_GAIN_ODD_128___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__BQ_GAIN_ODD_128___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__XLNA_GAIN_EVEN_128___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__XLNA_GAIN_EVEN_128___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__LNA_GAIN_EVEN_128___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__LNA_GAIN_EVEN_128___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__GM_GAIN_EVEN_128___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__GM_GAIN_EVEN_128___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__TIA_GAIN_EVEN_128___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__TIA_GAIN_EVEN_128___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__SLM_XLNA_EVEN_128___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__SLM_XLNA_EVEN_128___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__BQ_GAIN_EVEN_128___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128__BQ_GAIN_EVEN_128___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_128___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129 (0x005ED204) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__XLNA_GAIN_ODD_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__LNA_GAIN_ODD_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__GM_GAIN_ODD_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__TIA_GAIN_ODD_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__SLM_XLNA_ODD_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__BQ_GAIN_ODD_129___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__XLNA_GAIN_EVEN_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__LNA_GAIN_EVEN_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__GM_GAIN_EVEN_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__TIA_GAIN_EVEN_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__SLM_XLNA_EVEN_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__BQ_GAIN_EVEN_129___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__XLNA_GAIN_ODD_129___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__XLNA_GAIN_ODD_129___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__LNA_GAIN_ODD_129___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__LNA_GAIN_ODD_129___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__GM_GAIN_ODD_129___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__GM_GAIN_ODD_129___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__TIA_GAIN_ODD_129___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__TIA_GAIN_ODD_129___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__SLM_XLNA_ODD_129___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__SLM_XLNA_ODD_129___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__BQ_GAIN_ODD_129___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__BQ_GAIN_ODD_129___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__XLNA_GAIN_EVEN_129___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__XLNA_GAIN_EVEN_129___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__LNA_GAIN_EVEN_129___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__LNA_GAIN_EVEN_129___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__GM_GAIN_EVEN_129___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__GM_GAIN_EVEN_129___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__TIA_GAIN_EVEN_129___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__TIA_GAIN_EVEN_129___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__SLM_XLNA_EVEN_129___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__SLM_XLNA_EVEN_129___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__BQ_GAIN_EVEN_129___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129__BQ_GAIN_EVEN_129___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_129___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130 (0x005ED208) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__XLNA_GAIN_ODD_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__LNA_GAIN_ODD_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__GM_GAIN_ODD_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__TIA_GAIN_ODD_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__SLM_XLNA_ODD_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__BQ_GAIN_ODD_130___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__XLNA_GAIN_EVEN_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__LNA_GAIN_EVEN_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__GM_GAIN_EVEN_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__TIA_GAIN_EVEN_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__SLM_XLNA_EVEN_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__BQ_GAIN_EVEN_130___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__XLNA_GAIN_ODD_130___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__XLNA_GAIN_ODD_130___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__LNA_GAIN_ODD_130___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__LNA_GAIN_ODD_130___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__GM_GAIN_ODD_130___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__GM_GAIN_ODD_130___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__TIA_GAIN_ODD_130___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__TIA_GAIN_ODD_130___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__SLM_XLNA_ODD_130___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__SLM_XLNA_ODD_130___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__BQ_GAIN_ODD_130___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__BQ_GAIN_ODD_130___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__XLNA_GAIN_EVEN_130___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__XLNA_GAIN_EVEN_130___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__LNA_GAIN_EVEN_130___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__LNA_GAIN_EVEN_130___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__GM_GAIN_EVEN_130___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__GM_GAIN_EVEN_130___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__TIA_GAIN_EVEN_130___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__TIA_GAIN_EVEN_130___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__SLM_XLNA_EVEN_130___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__SLM_XLNA_EVEN_130___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__BQ_GAIN_EVEN_130___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130__BQ_GAIN_EVEN_130___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_130___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131 (0x005ED20C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__XLNA_GAIN_ODD_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__LNA_GAIN_ODD_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__GM_GAIN_ODD_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__TIA_GAIN_ODD_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__SLM_XLNA_ODD_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__BQ_GAIN_ODD_131___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__XLNA_GAIN_EVEN_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__LNA_GAIN_EVEN_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__GM_GAIN_EVEN_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__TIA_GAIN_EVEN_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__SLM_XLNA_EVEN_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__BQ_GAIN_EVEN_131___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__XLNA_GAIN_ODD_131___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__XLNA_GAIN_ODD_131___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__LNA_GAIN_ODD_131___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__LNA_GAIN_ODD_131___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__GM_GAIN_ODD_131___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__GM_GAIN_ODD_131___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__TIA_GAIN_ODD_131___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__TIA_GAIN_ODD_131___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__SLM_XLNA_ODD_131___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__SLM_XLNA_ODD_131___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__BQ_GAIN_ODD_131___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__BQ_GAIN_ODD_131___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__XLNA_GAIN_EVEN_131___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__XLNA_GAIN_EVEN_131___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__LNA_GAIN_EVEN_131___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__LNA_GAIN_EVEN_131___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__GM_GAIN_EVEN_131___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__GM_GAIN_EVEN_131___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__TIA_GAIN_EVEN_131___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__TIA_GAIN_EVEN_131___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__SLM_XLNA_EVEN_131___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__SLM_XLNA_EVEN_131___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__BQ_GAIN_EVEN_131___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131__BQ_GAIN_EVEN_131___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_131___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132 (0x005ED210) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__XLNA_GAIN_ODD_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__LNA_GAIN_ODD_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__GM_GAIN_ODD_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__TIA_GAIN_ODD_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__SLM_XLNA_ODD_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__BQ_GAIN_ODD_132___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__XLNA_GAIN_EVEN_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__LNA_GAIN_EVEN_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__GM_GAIN_EVEN_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__TIA_GAIN_EVEN_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__SLM_XLNA_EVEN_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__BQ_GAIN_EVEN_132___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__XLNA_GAIN_ODD_132___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__XLNA_GAIN_ODD_132___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__LNA_GAIN_ODD_132___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__LNA_GAIN_ODD_132___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__GM_GAIN_ODD_132___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__GM_GAIN_ODD_132___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__TIA_GAIN_ODD_132___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__TIA_GAIN_ODD_132___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__SLM_XLNA_ODD_132___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__SLM_XLNA_ODD_132___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__BQ_GAIN_ODD_132___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__BQ_GAIN_ODD_132___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__XLNA_GAIN_EVEN_132___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__XLNA_GAIN_EVEN_132___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__LNA_GAIN_EVEN_132___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__LNA_GAIN_EVEN_132___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__GM_GAIN_EVEN_132___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__GM_GAIN_EVEN_132___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__TIA_GAIN_EVEN_132___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__TIA_GAIN_EVEN_132___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__SLM_XLNA_EVEN_132___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__SLM_XLNA_EVEN_132___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__BQ_GAIN_EVEN_132___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132__BQ_GAIN_EVEN_132___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_132___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133 (0x005ED214) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__XLNA_GAIN_ODD_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__LNA_GAIN_ODD_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__GM_GAIN_ODD_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__TIA_GAIN_ODD_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__SLM_XLNA_ODD_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__BQ_GAIN_ODD_133___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__XLNA_GAIN_EVEN_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__LNA_GAIN_EVEN_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__GM_GAIN_EVEN_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__TIA_GAIN_EVEN_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__SLM_XLNA_EVEN_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__BQ_GAIN_EVEN_133___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__XLNA_GAIN_ODD_133___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__XLNA_GAIN_ODD_133___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__LNA_GAIN_ODD_133___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__LNA_GAIN_ODD_133___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__GM_GAIN_ODD_133___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__GM_GAIN_ODD_133___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__TIA_GAIN_ODD_133___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__TIA_GAIN_ODD_133___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__SLM_XLNA_ODD_133___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__SLM_XLNA_ODD_133___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__BQ_GAIN_ODD_133___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__BQ_GAIN_ODD_133___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__XLNA_GAIN_EVEN_133___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__XLNA_GAIN_EVEN_133___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__LNA_GAIN_EVEN_133___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__LNA_GAIN_EVEN_133___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__GM_GAIN_EVEN_133___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__GM_GAIN_EVEN_133___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__TIA_GAIN_EVEN_133___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__TIA_GAIN_EVEN_133___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__SLM_XLNA_EVEN_133___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__SLM_XLNA_EVEN_133___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__BQ_GAIN_EVEN_133___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133__BQ_GAIN_EVEN_133___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_133___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134 (0x005ED218) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__XLNA_GAIN_ODD_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__LNA_GAIN_ODD_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__GM_GAIN_ODD_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__TIA_GAIN_ODD_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__SLM_XLNA_ODD_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__BQ_GAIN_ODD_134___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__XLNA_GAIN_EVEN_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__LNA_GAIN_EVEN_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__GM_GAIN_EVEN_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__TIA_GAIN_EVEN_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__SLM_XLNA_EVEN_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__BQ_GAIN_EVEN_134___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__XLNA_GAIN_ODD_134___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__XLNA_GAIN_ODD_134___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__LNA_GAIN_ODD_134___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__LNA_GAIN_ODD_134___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__GM_GAIN_ODD_134___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__GM_GAIN_ODD_134___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__TIA_GAIN_ODD_134___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__TIA_GAIN_ODD_134___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__SLM_XLNA_ODD_134___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__SLM_XLNA_ODD_134___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__BQ_GAIN_ODD_134___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__BQ_GAIN_ODD_134___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__XLNA_GAIN_EVEN_134___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__XLNA_GAIN_EVEN_134___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__LNA_GAIN_EVEN_134___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__LNA_GAIN_EVEN_134___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__GM_GAIN_EVEN_134___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__GM_GAIN_EVEN_134___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__TIA_GAIN_EVEN_134___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__TIA_GAIN_EVEN_134___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__SLM_XLNA_EVEN_134___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__SLM_XLNA_EVEN_134___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__BQ_GAIN_EVEN_134___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134__BQ_GAIN_EVEN_134___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_134___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135 (0x005ED21C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__XLNA_GAIN_ODD_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__LNA_GAIN_ODD_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__GM_GAIN_ODD_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__TIA_GAIN_ODD_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__SLM_XLNA_ODD_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__BQ_GAIN_ODD_135___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__XLNA_GAIN_EVEN_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__LNA_GAIN_EVEN_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__GM_GAIN_EVEN_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__TIA_GAIN_EVEN_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__SLM_XLNA_EVEN_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__BQ_GAIN_EVEN_135___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__XLNA_GAIN_ODD_135___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__XLNA_GAIN_ODD_135___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__LNA_GAIN_ODD_135___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__LNA_GAIN_ODD_135___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__GM_GAIN_ODD_135___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__GM_GAIN_ODD_135___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__TIA_GAIN_ODD_135___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__TIA_GAIN_ODD_135___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__SLM_XLNA_ODD_135___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__SLM_XLNA_ODD_135___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__BQ_GAIN_ODD_135___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__BQ_GAIN_ODD_135___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__XLNA_GAIN_EVEN_135___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__XLNA_GAIN_EVEN_135___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__LNA_GAIN_EVEN_135___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__LNA_GAIN_EVEN_135___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__GM_GAIN_EVEN_135___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__GM_GAIN_EVEN_135___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__TIA_GAIN_EVEN_135___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__TIA_GAIN_EVEN_135___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__SLM_XLNA_EVEN_135___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__SLM_XLNA_EVEN_135___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__BQ_GAIN_EVEN_135___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135__BQ_GAIN_EVEN_135___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_135___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136 (0x005ED220) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__XLNA_GAIN_ODD_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__LNA_GAIN_ODD_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__GM_GAIN_ODD_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__TIA_GAIN_ODD_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__SLM_XLNA_ODD_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__BQ_GAIN_ODD_136___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__XLNA_GAIN_EVEN_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__LNA_GAIN_EVEN_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__GM_GAIN_EVEN_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__TIA_GAIN_EVEN_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__SLM_XLNA_EVEN_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__BQ_GAIN_EVEN_136___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__XLNA_GAIN_ODD_136___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__XLNA_GAIN_ODD_136___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__LNA_GAIN_ODD_136___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__LNA_GAIN_ODD_136___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__GM_GAIN_ODD_136___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__GM_GAIN_ODD_136___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__TIA_GAIN_ODD_136___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__TIA_GAIN_ODD_136___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__SLM_XLNA_ODD_136___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__SLM_XLNA_ODD_136___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__BQ_GAIN_ODD_136___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__BQ_GAIN_ODD_136___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__XLNA_GAIN_EVEN_136___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__XLNA_GAIN_EVEN_136___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__LNA_GAIN_EVEN_136___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__LNA_GAIN_EVEN_136___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__GM_GAIN_EVEN_136___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__GM_GAIN_EVEN_136___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__TIA_GAIN_EVEN_136___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__TIA_GAIN_EVEN_136___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__SLM_XLNA_EVEN_136___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__SLM_XLNA_EVEN_136___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__BQ_GAIN_EVEN_136___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136__BQ_GAIN_EVEN_136___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_136___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137 (0x005ED224) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__XLNA_GAIN_ODD_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__LNA_GAIN_ODD_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__GM_GAIN_ODD_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__TIA_GAIN_ODD_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__SLM_XLNA_ODD_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__BQ_GAIN_ODD_137___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__XLNA_GAIN_EVEN_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__LNA_GAIN_EVEN_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__GM_GAIN_EVEN_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__TIA_GAIN_EVEN_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__SLM_XLNA_EVEN_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__BQ_GAIN_EVEN_137___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__XLNA_GAIN_ODD_137___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__XLNA_GAIN_ODD_137___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__LNA_GAIN_ODD_137___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__LNA_GAIN_ODD_137___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__GM_GAIN_ODD_137___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__GM_GAIN_ODD_137___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__TIA_GAIN_ODD_137___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__TIA_GAIN_ODD_137___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__SLM_XLNA_ODD_137___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__SLM_XLNA_ODD_137___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__BQ_GAIN_ODD_137___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__BQ_GAIN_ODD_137___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__XLNA_GAIN_EVEN_137___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__XLNA_GAIN_EVEN_137___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__LNA_GAIN_EVEN_137___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__LNA_GAIN_EVEN_137___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__GM_GAIN_EVEN_137___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__GM_GAIN_EVEN_137___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__TIA_GAIN_EVEN_137___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__TIA_GAIN_EVEN_137___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__SLM_XLNA_EVEN_137___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__SLM_XLNA_EVEN_137___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__BQ_GAIN_EVEN_137___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137__BQ_GAIN_EVEN_137___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_137___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138 (0x005ED228) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__XLNA_GAIN_ODD_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__LNA_GAIN_ODD_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__GM_GAIN_ODD_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__TIA_GAIN_ODD_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__SLM_XLNA_ODD_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__BQ_GAIN_ODD_138___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__XLNA_GAIN_EVEN_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__LNA_GAIN_EVEN_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__GM_GAIN_EVEN_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__TIA_GAIN_EVEN_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__SLM_XLNA_EVEN_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__BQ_GAIN_EVEN_138___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__XLNA_GAIN_ODD_138___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__XLNA_GAIN_ODD_138___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__LNA_GAIN_ODD_138___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__LNA_GAIN_ODD_138___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__GM_GAIN_ODD_138___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__GM_GAIN_ODD_138___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__TIA_GAIN_ODD_138___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__TIA_GAIN_ODD_138___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__SLM_XLNA_ODD_138___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__SLM_XLNA_ODD_138___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__BQ_GAIN_ODD_138___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__BQ_GAIN_ODD_138___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__XLNA_GAIN_EVEN_138___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__XLNA_GAIN_EVEN_138___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__LNA_GAIN_EVEN_138___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__LNA_GAIN_EVEN_138___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__GM_GAIN_EVEN_138___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__GM_GAIN_EVEN_138___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__TIA_GAIN_EVEN_138___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__TIA_GAIN_EVEN_138___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__SLM_XLNA_EVEN_138___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__SLM_XLNA_EVEN_138___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__BQ_GAIN_EVEN_138___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138__BQ_GAIN_EVEN_138___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_138___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139 (0x005ED22C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__XLNA_GAIN_ODD_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__LNA_GAIN_ODD_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__GM_GAIN_ODD_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__TIA_GAIN_ODD_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__SLM_XLNA_ODD_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__BQ_GAIN_ODD_139___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__XLNA_GAIN_EVEN_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__LNA_GAIN_EVEN_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__GM_GAIN_EVEN_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__TIA_GAIN_EVEN_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__SLM_XLNA_EVEN_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__BQ_GAIN_EVEN_139___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__XLNA_GAIN_ODD_139___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__XLNA_GAIN_ODD_139___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__LNA_GAIN_ODD_139___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__LNA_GAIN_ODD_139___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__GM_GAIN_ODD_139___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__GM_GAIN_ODD_139___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__TIA_GAIN_ODD_139___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__TIA_GAIN_ODD_139___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__SLM_XLNA_ODD_139___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__SLM_XLNA_ODD_139___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__BQ_GAIN_ODD_139___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__BQ_GAIN_ODD_139___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__XLNA_GAIN_EVEN_139___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__XLNA_GAIN_EVEN_139___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__LNA_GAIN_EVEN_139___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__LNA_GAIN_EVEN_139___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__GM_GAIN_EVEN_139___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__GM_GAIN_EVEN_139___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__TIA_GAIN_EVEN_139___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__TIA_GAIN_EVEN_139___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__SLM_XLNA_EVEN_139___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__SLM_XLNA_EVEN_139___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__BQ_GAIN_EVEN_139___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139__BQ_GAIN_EVEN_139___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_139___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140 (0x005ED230) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__XLNA_GAIN_ODD_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__LNA_GAIN_ODD_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__GM_GAIN_ODD_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__TIA_GAIN_ODD_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__SLM_XLNA_ODD_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__BQ_GAIN_ODD_140___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__XLNA_GAIN_EVEN_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__LNA_GAIN_EVEN_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__GM_GAIN_EVEN_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__TIA_GAIN_EVEN_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__SLM_XLNA_EVEN_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__BQ_GAIN_EVEN_140___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__XLNA_GAIN_ODD_140___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__XLNA_GAIN_ODD_140___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__LNA_GAIN_ODD_140___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__LNA_GAIN_ODD_140___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__GM_GAIN_ODD_140___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__GM_GAIN_ODD_140___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__TIA_GAIN_ODD_140___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__TIA_GAIN_ODD_140___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__SLM_XLNA_ODD_140___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__SLM_XLNA_ODD_140___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__BQ_GAIN_ODD_140___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__BQ_GAIN_ODD_140___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__XLNA_GAIN_EVEN_140___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__XLNA_GAIN_EVEN_140___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__LNA_GAIN_EVEN_140___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__LNA_GAIN_EVEN_140___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__GM_GAIN_EVEN_140___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__GM_GAIN_EVEN_140___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__TIA_GAIN_EVEN_140___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__TIA_GAIN_EVEN_140___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__SLM_XLNA_EVEN_140___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__SLM_XLNA_EVEN_140___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__BQ_GAIN_EVEN_140___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140__BQ_GAIN_EVEN_140___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_140___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141 (0x005ED234) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__XLNA_GAIN_ODD_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__LNA_GAIN_ODD_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__GM_GAIN_ODD_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__TIA_GAIN_ODD_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__SLM_XLNA_ODD_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__BQ_GAIN_ODD_141___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__XLNA_GAIN_EVEN_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__LNA_GAIN_EVEN_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__GM_GAIN_EVEN_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__TIA_GAIN_EVEN_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__SLM_XLNA_EVEN_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__BQ_GAIN_EVEN_141___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__XLNA_GAIN_ODD_141___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__XLNA_GAIN_ODD_141___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__LNA_GAIN_ODD_141___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__LNA_GAIN_ODD_141___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__GM_GAIN_ODD_141___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__GM_GAIN_ODD_141___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__TIA_GAIN_ODD_141___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__TIA_GAIN_ODD_141___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__SLM_XLNA_ODD_141___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__SLM_XLNA_ODD_141___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__BQ_GAIN_ODD_141___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__BQ_GAIN_ODD_141___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__XLNA_GAIN_EVEN_141___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__XLNA_GAIN_EVEN_141___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__LNA_GAIN_EVEN_141___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__LNA_GAIN_EVEN_141___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__GM_GAIN_EVEN_141___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__GM_GAIN_EVEN_141___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__TIA_GAIN_EVEN_141___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__TIA_GAIN_EVEN_141___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__SLM_XLNA_EVEN_141___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__SLM_XLNA_EVEN_141___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__BQ_GAIN_EVEN_141___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141__BQ_GAIN_EVEN_141___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_141___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142 (0x005ED238) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__XLNA_GAIN_ODD_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__LNA_GAIN_ODD_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__GM_GAIN_ODD_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__TIA_GAIN_ODD_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__SLM_XLNA_ODD_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__BQ_GAIN_ODD_142___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__XLNA_GAIN_EVEN_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__LNA_GAIN_EVEN_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__GM_GAIN_EVEN_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__TIA_GAIN_EVEN_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__SLM_XLNA_EVEN_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__BQ_GAIN_EVEN_142___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__XLNA_GAIN_ODD_142___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__XLNA_GAIN_ODD_142___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__LNA_GAIN_ODD_142___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__LNA_GAIN_ODD_142___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__GM_GAIN_ODD_142___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__GM_GAIN_ODD_142___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__TIA_GAIN_ODD_142___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__TIA_GAIN_ODD_142___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__SLM_XLNA_ODD_142___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__SLM_XLNA_ODD_142___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__BQ_GAIN_ODD_142___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__BQ_GAIN_ODD_142___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__XLNA_GAIN_EVEN_142___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__XLNA_GAIN_EVEN_142___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__LNA_GAIN_EVEN_142___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__LNA_GAIN_EVEN_142___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__GM_GAIN_EVEN_142___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__GM_GAIN_EVEN_142___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__TIA_GAIN_EVEN_142___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__TIA_GAIN_EVEN_142___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__SLM_XLNA_EVEN_142___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__SLM_XLNA_EVEN_142___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__BQ_GAIN_EVEN_142___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142__BQ_GAIN_EVEN_142___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_142___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143 (0x005ED23C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__XLNA_GAIN_ODD_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__LNA_GAIN_ODD_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__GM_GAIN_ODD_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__TIA_GAIN_ODD_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__SLM_XLNA_ODD_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__BQ_GAIN_ODD_143___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__XLNA_GAIN_EVEN_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__LNA_GAIN_EVEN_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__GM_GAIN_EVEN_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__TIA_GAIN_EVEN_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__SLM_XLNA_EVEN_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__BQ_GAIN_EVEN_143___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__XLNA_GAIN_ODD_143___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__XLNA_GAIN_ODD_143___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__LNA_GAIN_ODD_143___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__LNA_GAIN_ODD_143___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__GM_GAIN_ODD_143___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__GM_GAIN_ODD_143___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__TIA_GAIN_ODD_143___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__TIA_GAIN_ODD_143___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__SLM_XLNA_ODD_143___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__SLM_XLNA_ODD_143___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__BQ_GAIN_ODD_143___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__BQ_GAIN_ODD_143___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__XLNA_GAIN_EVEN_143___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__XLNA_GAIN_EVEN_143___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__LNA_GAIN_EVEN_143___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__LNA_GAIN_EVEN_143___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__GM_GAIN_EVEN_143___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__GM_GAIN_EVEN_143___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__TIA_GAIN_EVEN_143___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__TIA_GAIN_EVEN_143___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__SLM_XLNA_EVEN_143___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__SLM_XLNA_EVEN_143___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__BQ_GAIN_EVEN_143___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143__BQ_GAIN_EVEN_143___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_143___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144 (0x005ED240) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__XLNA_GAIN_ODD_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__LNA_GAIN_ODD_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__GM_GAIN_ODD_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__TIA_GAIN_ODD_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__SLM_XLNA_ODD_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__BQ_GAIN_ODD_144___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__XLNA_GAIN_EVEN_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__LNA_GAIN_EVEN_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__GM_GAIN_EVEN_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__TIA_GAIN_EVEN_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__SLM_XLNA_EVEN_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__BQ_GAIN_EVEN_144___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__XLNA_GAIN_ODD_144___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__XLNA_GAIN_ODD_144___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__LNA_GAIN_ODD_144___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__LNA_GAIN_ODD_144___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__GM_GAIN_ODD_144___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__GM_GAIN_ODD_144___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__TIA_GAIN_ODD_144___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__TIA_GAIN_ODD_144___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__SLM_XLNA_ODD_144___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__SLM_XLNA_ODD_144___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__BQ_GAIN_ODD_144___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__BQ_GAIN_ODD_144___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__XLNA_GAIN_EVEN_144___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__XLNA_GAIN_EVEN_144___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__LNA_GAIN_EVEN_144___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__LNA_GAIN_EVEN_144___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__GM_GAIN_EVEN_144___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__GM_GAIN_EVEN_144___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__TIA_GAIN_EVEN_144___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__TIA_GAIN_EVEN_144___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__SLM_XLNA_EVEN_144___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__SLM_XLNA_EVEN_144___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__BQ_GAIN_EVEN_144___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144__BQ_GAIN_EVEN_144___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_144___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145 (0x005ED244) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__XLNA_GAIN_ODD_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__LNA_GAIN_ODD_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__GM_GAIN_ODD_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__TIA_GAIN_ODD_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__SLM_XLNA_ODD_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__BQ_GAIN_ODD_145___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__XLNA_GAIN_EVEN_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__LNA_GAIN_EVEN_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__GM_GAIN_EVEN_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__TIA_GAIN_EVEN_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__SLM_XLNA_EVEN_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__BQ_GAIN_EVEN_145___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__XLNA_GAIN_ODD_145___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__XLNA_GAIN_ODD_145___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__LNA_GAIN_ODD_145___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__LNA_GAIN_ODD_145___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__GM_GAIN_ODD_145___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__GM_GAIN_ODD_145___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__TIA_GAIN_ODD_145___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__TIA_GAIN_ODD_145___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__SLM_XLNA_ODD_145___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__SLM_XLNA_ODD_145___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__BQ_GAIN_ODD_145___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__BQ_GAIN_ODD_145___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__XLNA_GAIN_EVEN_145___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__XLNA_GAIN_EVEN_145___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__LNA_GAIN_EVEN_145___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__LNA_GAIN_EVEN_145___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__GM_GAIN_EVEN_145___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__GM_GAIN_EVEN_145___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__TIA_GAIN_EVEN_145___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__TIA_GAIN_EVEN_145___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__SLM_XLNA_EVEN_145___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__SLM_XLNA_EVEN_145___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__BQ_GAIN_EVEN_145___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145__BQ_GAIN_EVEN_145___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_145___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146 (0x005ED248) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__XLNA_GAIN_ODD_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__LNA_GAIN_ODD_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__GM_GAIN_ODD_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__TIA_GAIN_ODD_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__SLM_XLNA_ODD_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__BQ_GAIN_ODD_146___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__XLNA_GAIN_EVEN_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__LNA_GAIN_EVEN_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__GM_GAIN_EVEN_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__TIA_GAIN_EVEN_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__SLM_XLNA_EVEN_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__BQ_GAIN_EVEN_146___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__XLNA_GAIN_ODD_146___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__XLNA_GAIN_ODD_146___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__LNA_GAIN_ODD_146___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__LNA_GAIN_ODD_146___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__GM_GAIN_ODD_146___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__GM_GAIN_ODD_146___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__TIA_GAIN_ODD_146___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__TIA_GAIN_ODD_146___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__SLM_XLNA_ODD_146___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__SLM_XLNA_ODD_146___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__BQ_GAIN_ODD_146___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__BQ_GAIN_ODD_146___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__XLNA_GAIN_EVEN_146___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__XLNA_GAIN_EVEN_146___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__LNA_GAIN_EVEN_146___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__LNA_GAIN_EVEN_146___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__GM_GAIN_EVEN_146___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__GM_GAIN_EVEN_146___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__TIA_GAIN_EVEN_146___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__TIA_GAIN_EVEN_146___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__SLM_XLNA_EVEN_146___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__SLM_XLNA_EVEN_146___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__BQ_GAIN_EVEN_146___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146__BQ_GAIN_EVEN_146___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_146___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147 (0x005ED24C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__XLNA_GAIN_ODD_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__LNA_GAIN_ODD_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__GM_GAIN_ODD_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__TIA_GAIN_ODD_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__SLM_XLNA_ODD_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__BQ_GAIN_ODD_147___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__XLNA_GAIN_EVEN_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__LNA_GAIN_EVEN_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__GM_GAIN_EVEN_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__TIA_GAIN_EVEN_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__SLM_XLNA_EVEN_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__BQ_GAIN_EVEN_147___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__XLNA_GAIN_ODD_147___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__XLNA_GAIN_ODD_147___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__LNA_GAIN_ODD_147___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__LNA_GAIN_ODD_147___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__GM_GAIN_ODD_147___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__GM_GAIN_ODD_147___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__TIA_GAIN_ODD_147___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__TIA_GAIN_ODD_147___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__SLM_XLNA_ODD_147___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__SLM_XLNA_ODD_147___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__BQ_GAIN_ODD_147___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__BQ_GAIN_ODD_147___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__XLNA_GAIN_EVEN_147___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__XLNA_GAIN_EVEN_147___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__LNA_GAIN_EVEN_147___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__LNA_GAIN_EVEN_147___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__GM_GAIN_EVEN_147___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__GM_GAIN_EVEN_147___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__TIA_GAIN_EVEN_147___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__TIA_GAIN_EVEN_147___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__SLM_XLNA_EVEN_147___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__SLM_XLNA_EVEN_147___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__BQ_GAIN_EVEN_147___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147__BQ_GAIN_EVEN_147___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_147___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148 (0x005ED250) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__XLNA_GAIN_ODD_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__LNA_GAIN_ODD_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__GM_GAIN_ODD_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__TIA_GAIN_ODD_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__SLM_XLNA_ODD_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__BQ_GAIN_ODD_148___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__XLNA_GAIN_EVEN_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__LNA_GAIN_EVEN_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__GM_GAIN_EVEN_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__TIA_GAIN_EVEN_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__SLM_XLNA_EVEN_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__BQ_GAIN_EVEN_148___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__XLNA_GAIN_ODD_148___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__XLNA_GAIN_ODD_148___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__LNA_GAIN_ODD_148___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__LNA_GAIN_ODD_148___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__GM_GAIN_ODD_148___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__GM_GAIN_ODD_148___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__TIA_GAIN_ODD_148___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__TIA_GAIN_ODD_148___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__SLM_XLNA_ODD_148___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__SLM_XLNA_ODD_148___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__BQ_GAIN_ODD_148___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__BQ_GAIN_ODD_148___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__XLNA_GAIN_EVEN_148___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__XLNA_GAIN_EVEN_148___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__LNA_GAIN_EVEN_148___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__LNA_GAIN_EVEN_148___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__GM_GAIN_EVEN_148___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__GM_GAIN_EVEN_148___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__TIA_GAIN_EVEN_148___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__TIA_GAIN_EVEN_148___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__SLM_XLNA_EVEN_148___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__SLM_XLNA_EVEN_148___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__BQ_GAIN_EVEN_148___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148__BQ_GAIN_EVEN_148___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_148___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149 (0x005ED254) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__XLNA_GAIN_ODD_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__LNA_GAIN_ODD_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__GM_GAIN_ODD_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__TIA_GAIN_ODD_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__SLM_XLNA_ODD_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__BQ_GAIN_ODD_149___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__XLNA_GAIN_EVEN_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__LNA_GAIN_EVEN_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__GM_GAIN_EVEN_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__TIA_GAIN_EVEN_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__SLM_XLNA_EVEN_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__BQ_GAIN_EVEN_149___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__XLNA_GAIN_ODD_149___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__XLNA_GAIN_ODD_149___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__LNA_GAIN_ODD_149___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__LNA_GAIN_ODD_149___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__GM_GAIN_ODD_149___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__GM_GAIN_ODD_149___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__TIA_GAIN_ODD_149___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__TIA_GAIN_ODD_149___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__SLM_XLNA_ODD_149___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__SLM_XLNA_ODD_149___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__BQ_GAIN_ODD_149___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__BQ_GAIN_ODD_149___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__XLNA_GAIN_EVEN_149___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__XLNA_GAIN_EVEN_149___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__LNA_GAIN_EVEN_149___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__LNA_GAIN_EVEN_149___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__GM_GAIN_EVEN_149___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__GM_GAIN_EVEN_149___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__TIA_GAIN_EVEN_149___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__TIA_GAIN_EVEN_149___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__SLM_XLNA_EVEN_149___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__SLM_XLNA_EVEN_149___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__BQ_GAIN_EVEN_149___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149__BQ_GAIN_EVEN_149___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_149___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150 (0x005ED258) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__XLNA_GAIN_ODD_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__LNA_GAIN_ODD_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__GM_GAIN_ODD_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__TIA_GAIN_ODD_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__SLM_XLNA_ODD_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__BQ_GAIN_ODD_150___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__XLNA_GAIN_EVEN_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__LNA_GAIN_EVEN_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__GM_GAIN_EVEN_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__TIA_GAIN_EVEN_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__SLM_XLNA_EVEN_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__BQ_GAIN_EVEN_150___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__XLNA_GAIN_ODD_150___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__XLNA_GAIN_ODD_150___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__LNA_GAIN_ODD_150___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__LNA_GAIN_ODD_150___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__GM_GAIN_ODD_150___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__GM_GAIN_ODD_150___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__TIA_GAIN_ODD_150___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__TIA_GAIN_ODD_150___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__SLM_XLNA_ODD_150___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__SLM_XLNA_ODD_150___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__BQ_GAIN_ODD_150___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__BQ_GAIN_ODD_150___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__XLNA_GAIN_EVEN_150___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__XLNA_GAIN_EVEN_150___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__LNA_GAIN_EVEN_150___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__LNA_GAIN_EVEN_150___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__GM_GAIN_EVEN_150___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__GM_GAIN_EVEN_150___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__TIA_GAIN_EVEN_150___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__TIA_GAIN_EVEN_150___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__SLM_XLNA_EVEN_150___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__SLM_XLNA_EVEN_150___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__BQ_GAIN_EVEN_150___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150__BQ_GAIN_EVEN_150___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_150___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151 (0x005ED25C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__XLNA_GAIN_ODD_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__LNA_GAIN_ODD_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__GM_GAIN_ODD_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__TIA_GAIN_ODD_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__SLM_XLNA_ODD_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__BQ_GAIN_ODD_151___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__XLNA_GAIN_EVEN_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__LNA_GAIN_EVEN_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__GM_GAIN_EVEN_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__TIA_GAIN_EVEN_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__SLM_XLNA_EVEN_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__BQ_GAIN_EVEN_151___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__XLNA_GAIN_ODD_151___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__XLNA_GAIN_ODD_151___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__LNA_GAIN_ODD_151___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__LNA_GAIN_ODD_151___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__GM_GAIN_ODD_151___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__GM_GAIN_ODD_151___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__TIA_GAIN_ODD_151___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__TIA_GAIN_ODD_151___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__SLM_XLNA_ODD_151___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__SLM_XLNA_ODD_151___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__BQ_GAIN_ODD_151___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__BQ_GAIN_ODD_151___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__XLNA_GAIN_EVEN_151___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__XLNA_GAIN_EVEN_151___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__LNA_GAIN_EVEN_151___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__LNA_GAIN_EVEN_151___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__GM_GAIN_EVEN_151___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__GM_GAIN_EVEN_151___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__TIA_GAIN_EVEN_151___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__TIA_GAIN_EVEN_151___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__SLM_XLNA_EVEN_151___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__SLM_XLNA_EVEN_151___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__BQ_GAIN_EVEN_151___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151__BQ_GAIN_EVEN_151___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_151___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152 (0x005ED260) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__XLNA_GAIN_ODD_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__LNA_GAIN_ODD_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__GM_GAIN_ODD_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__TIA_GAIN_ODD_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__SLM_XLNA_ODD_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__BQ_GAIN_ODD_152___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__XLNA_GAIN_EVEN_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__LNA_GAIN_EVEN_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__GM_GAIN_EVEN_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__TIA_GAIN_EVEN_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__SLM_XLNA_EVEN_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__BQ_GAIN_EVEN_152___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__XLNA_GAIN_ODD_152___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__XLNA_GAIN_ODD_152___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__LNA_GAIN_ODD_152___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__LNA_GAIN_ODD_152___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__GM_GAIN_ODD_152___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__GM_GAIN_ODD_152___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__TIA_GAIN_ODD_152___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__TIA_GAIN_ODD_152___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__SLM_XLNA_ODD_152___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__SLM_XLNA_ODD_152___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__BQ_GAIN_ODD_152___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__BQ_GAIN_ODD_152___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__XLNA_GAIN_EVEN_152___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__XLNA_GAIN_EVEN_152___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__LNA_GAIN_EVEN_152___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__LNA_GAIN_EVEN_152___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__GM_GAIN_EVEN_152___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__GM_GAIN_EVEN_152___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__TIA_GAIN_EVEN_152___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__TIA_GAIN_EVEN_152___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__SLM_XLNA_EVEN_152___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__SLM_XLNA_EVEN_152___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__BQ_GAIN_EVEN_152___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152__BQ_GAIN_EVEN_152___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_152___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153 (0x005ED264) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__XLNA_GAIN_ODD_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__LNA_GAIN_ODD_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__GM_GAIN_ODD_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__TIA_GAIN_ODD_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__SLM_XLNA_ODD_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__BQ_GAIN_ODD_153___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__XLNA_GAIN_EVEN_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__LNA_GAIN_EVEN_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__GM_GAIN_EVEN_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__TIA_GAIN_EVEN_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__SLM_XLNA_EVEN_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__BQ_GAIN_EVEN_153___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__XLNA_GAIN_ODD_153___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__XLNA_GAIN_ODD_153___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__LNA_GAIN_ODD_153___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__LNA_GAIN_ODD_153___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__GM_GAIN_ODD_153___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__GM_GAIN_ODD_153___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__TIA_GAIN_ODD_153___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__TIA_GAIN_ODD_153___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__SLM_XLNA_ODD_153___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__SLM_XLNA_ODD_153___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__BQ_GAIN_ODD_153___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__BQ_GAIN_ODD_153___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__XLNA_GAIN_EVEN_153___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__XLNA_GAIN_EVEN_153___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__LNA_GAIN_EVEN_153___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__LNA_GAIN_EVEN_153___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__GM_GAIN_EVEN_153___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__GM_GAIN_EVEN_153___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__TIA_GAIN_EVEN_153___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__TIA_GAIN_EVEN_153___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__SLM_XLNA_EVEN_153___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__SLM_XLNA_EVEN_153___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__BQ_GAIN_EVEN_153___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153__BQ_GAIN_EVEN_153___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_153___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154 (0x005ED268) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__XLNA_GAIN_ODD_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__LNA_GAIN_ODD_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__GM_GAIN_ODD_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__TIA_GAIN_ODD_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__SLM_XLNA_ODD_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__BQ_GAIN_ODD_154___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__XLNA_GAIN_EVEN_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__LNA_GAIN_EVEN_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__GM_GAIN_EVEN_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__TIA_GAIN_EVEN_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__SLM_XLNA_EVEN_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__BQ_GAIN_EVEN_154___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__XLNA_GAIN_ODD_154___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__XLNA_GAIN_ODD_154___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__LNA_GAIN_ODD_154___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__LNA_GAIN_ODD_154___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__GM_GAIN_ODD_154___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__GM_GAIN_ODD_154___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__TIA_GAIN_ODD_154___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__TIA_GAIN_ODD_154___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__SLM_XLNA_ODD_154___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__SLM_XLNA_ODD_154___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__BQ_GAIN_ODD_154___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__BQ_GAIN_ODD_154___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__XLNA_GAIN_EVEN_154___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__XLNA_GAIN_EVEN_154___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__LNA_GAIN_EVEN_154___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__LNA_GAIN_EVEN_154___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__GM_GAIN_EVEN_154___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__GM_GAIN_EVEN_154___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__TIA_GAIN_EVEN_154___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__TIA_GAIN_EVEN_154___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__SLM_XLNA_EVEN_154___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__SLM_XLNA_EVEN_154___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__BQ_GAIN_EVEN_154___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154__BQ_GAIN_EVEN_154___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_154___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155 (0x005ED26C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__XLNA_GAIN_ODD_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__LNA_GAIN_ODD_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__GM_GAIN_ODD_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__TIA_GAIN_ODD_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__SLM_XLNA_ODD_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__BQ_GAIN_ODD_155___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__XLNA_GAIN_EVEN_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__LNA_GAIN_EVEN_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__GM_GAIN_EVEN_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__TIA_GAIN_EVEN_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__SLM_XLNA_EVEN_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__BQ_GAIN_EVEN_155___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__XLNA_GAIN_ODD_155___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__XLNA_GAIN_ODD_155___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__LNA_GAIN_ODD_155___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__LNA_GAIN_ODD_155___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__GM_GAIN_ODD_155___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__GM_GAIN_ODD_155___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__TIA_GAIN_ODD_155___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__TIA_GAIN_ODD_155___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__SLM_XLNA_ODD_155___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__SLM_XLNA_ODD_155___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__BQ_GAIN_ODD_155___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__BQ_GAIN_ODD_155___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__XLNA_GAIN_EVEN_155___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__XLNA_GAIN_EVEN_155___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__LNA_GAIN_EVEN_155___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__LNA_GAIN_EVEN_155___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__GM_GAIN_EVEN_155___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__GM_GAIN_EVEN_155___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__TIA_GAIN_EVEN_155___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__TIA_GAIN_EVEN_155___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__SLM_XLNA_EVEN_155___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__SLM_XLNA_EVEN_155___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__BQ_GAIN_EVEN_155___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155__BQ_GAIN_EVEN_155___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_155___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156 (0x005ED270) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__XLNA_GAIN_ODD_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__LNA_GAIN_ODD_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__GM_GAIN_ODD_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__TIA_GAIN_ODD_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__SLM_XLNA_ODD_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__BQ_GAIN_ODD_156___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__XLNA_GAIN_EVEN_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__LNA_GAIN_EVEN_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__GM_GAIN_EVEN_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__TIA_GAIN_EVEN_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__SLM_XLNA_EVEN_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__BQ_GAIN_EVEN_156___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__XLNA_GAIN_ODD_156___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__XLNA_GAIN_ODD_156___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__LNA_GAIN_ODD_156___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__LNA_GAIN_ODD_156___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__GM_GAIN_ODD_156___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__GM_GAIN_ODD_156___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__TIA_GAIN_ODD_156___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__TIA_GAIN_ODD_156___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__SLM_XLNA_ODD_156___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__SLM_XLNA_ODD_156___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__BQ_GAIN_ODD_156___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__BQ_GAIN_ODD_156___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__XLNA_GAIN_EVEN_156___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__XLNA_GAIN_EVEN_156___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__LNA_GAIN_EVEN_156___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__LNA_GAIN_EVEN_156___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__GM_GAIN_EVEN_156___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__GM_GAIN_EVEN_156___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__TIA_GAIN_EVEN_156___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__TIA_GAIN_EVEN_156___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__SLM_XLNA_EVEN_156___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__SLM_XLNA_EVEN_156___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__BQ_GAIN_EVEN_156___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156__BQ_GAIN_EVEN_156___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_156___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157 (0x005ED274) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__XLNA_GAIN_ODD_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__LNA_GAIN_ODD_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__GM_GAIN_ODD_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__TIA_GAIN_ODD_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__SLM_XLNA_ODD_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__BQ_GAIN_ODD_157___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__XLNA_GAIN_EVEN_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__LNA_GAIN_EVEN_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__GM_GAIN_EVEN_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__TIA_GAIN_EVEN_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__SLM_XLNA_EVEN_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__BQ_GAIN_EVEN_157___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__XLNA_GAIN_ODD_157___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__XLNA_GAIN_ODD_157___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__LNA_GAIN_ODD_157___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__LNA_GAIN_ODD_157___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__GM_GAIN_ODD_157___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__GM_GAIN_ODD_157___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__TIA_GAIN_ODD_157___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__TIA_GAIN_ODD_157___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__SLM_XLNA_ODD_157___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__SLM_XLNA_ODD_157___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__BQ_GAIN_ODD_157___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__BQ_GAIN_ODD_157___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__XLNA_GAIN_EVEN_157___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__XLNA_GAIN_EVEN_157___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__LNA_GAIN_EVEN_157___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__LNA_GAIN_EVEN_157___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__GM_GAIN_EVEN_157___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__GM_GAIN_EVEN_157___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__TIA_GAIN_EVEN_157___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__TIA_GAIN_EVEN_157___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__SLM_XLNA_EVEN_157___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__SLM_XLNA_EVEN_157___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__BQ_GAIN_EVEN_157___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157__BQ_GAIN_EVEN_157___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_157___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158 (0x005ED278) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__XLNA_GAIN_ODD_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__LNA_GAIN_ODD_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__GM_GAIN_ODD_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__TIA_GAIN_ODD_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__SLM_XLNA_ODD_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__BQ_GAIN_ODD_158___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__XLNA_GAIN_EVEN_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__LNA_GAIN_EVEN_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__GM_GAIN_EVEN_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__TIA_GAIN_EVEN_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__SLM_XLNA_EVEN_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__BQ_GAIN_EVEN_158___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__XLNA_GAIN_ODD_158___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__XLNA_GAIN_ODD_158___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__LNA_GAIN_ODD_158___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__LNA_GAIN_ODD_158___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__GM_GAIN_ODD_158___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__GM_GAIN_ODD_158___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__TIA_GAIN_ODD_158___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__TIA_GAIN_ODD_158___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__SLM_XLNA_ODD_158___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__SLM_XLNA_ODD_158___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__BQ_GAIN_ODD_158___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__BQ_GAIN_ODD_158___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__XLNA_GAIN_EVEN_158___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__XLNA_GAIN_EVEN_158___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__LNA_GAIN_EVEN_158___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__LNA_GAIN_EVEN_158___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__GM_GAIN_EVEN_158___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__GM_GAIN_EVEN_158___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__TIA_GAIN_EVEN_158___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__TIA_GAIN_EVEN_158___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__SLM_XLNA_EVEN_158___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__SLM_XLNA_EVEN_158___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__BQ_GAIN_EVEN_158___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158__BQ_GAIN_EVEN_158___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_158___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159 (0x005ED27C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__XLNA_GAIN_ODD_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__LNA_GAIN_ODD_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__GM_GAIN_ODD_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__TIA_GAIN_ODD_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__SLM_XLNA_ODD_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__BQ_GAIN_ODD_159___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__XLNA_GAIN_EVEN_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__LNA_GAIN_EVEN_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__GM_GAIN_EVEN_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__TIA_GAIN_EVEN_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__SLM_XLNA_EVEN_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__BQ_GAIN_EVEN_159___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__XLNA_GAIN_ODD_159___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__XLNA_GAIN_ODD_159___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__LNA_GAIN_ODD_159___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__LNA_GAIN_ODD_159___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__GM_GAIN_ODD_159___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__GM_GAIN_ODD_159___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__TIA_GAIN_ODD_159___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__TIA_GAIN_ODD_159___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__SLM_XLNA_ODD_159___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__SLM_XLNA_ODD_159___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__BQ_GAIN_ODD_159___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__BQ_GAIN_ODD_159___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__XLNA_GAIN_EVEN_159___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__XLNA_GAIN_EVEN_159___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__LNA_GAIN_EVEN_159___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__LNA_GAIN_EVEN_159___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__GM_GAIN_EVEN_159___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__GM_GAIN_EVEN_159___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__TIA_GAIN_EVEN_159___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__TIA_GAIN_EVEN_159___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__SLM_XLNA_EVEN_159___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__SLM_XLNA_EVEN_159___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__BQ_GAIN_EVEN_159___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159__BQ_GAIN_EVEN_159___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_159___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160 (0x005ED280) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__XLNA_GAIN_ODD_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__LNA_GAIN_ODD_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__GM_GAIN_ODD_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__TIA_GAIN_ODD_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__SLM_XLNA_ODD_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__BQ_GAIN_ODD_160___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__XLNA_GAIN_EVEN_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__LNA_GAIN_EVEN_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__GM_GAIN_EVEN_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__TIA_GAIN_EVEN_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__SLM_XLNA_EVEN_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__BQ_GAIN_EVEN_160___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__XLNA_GAIN_ODD_160___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__XLNA_GAIN_ODD_160___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__LNA_GAIN_ODD_160___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__LNA_GAIN_ODD_160___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__GM_GAIN_ODD_160___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__GM_GAIN_ODD_160___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__TIA_GAIN_ODD_160___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__TIA_GAIN_ODD_160___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__SLM_XLNA_ODD_160___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__SLM_XLNA_ODD_160___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__BQ_GAIN_ODD_160___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__BQ_GAIN_ODD_160___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__XLNA_GAIN_EVEN_160___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__XLNA_GAIN_EVEN_160___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__LNA_GAIN_EVEN_160___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__LNA_GAIN_EVEN_160___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__GM_GAIN_EVEN_160___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__GM_GAIN_EVEN_160___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__TIA_GAIN_EVEN_160___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__TIA_GAIN_EVEN_160___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__SLM_XLNA_EVEN_160___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__SLM_XLNA_EVEN_160___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__BQ_GAIN_EVEN_160___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160__BQ_GAIN_EVEN_160___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_160___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161 (0x005ED284) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__XLNA_GAIN_ODD_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__LNA_GAIN_ODD_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__GM_GAIN_ODD_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__TIA_GAIN_ODD_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__SLM_XLNA_ODD_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__BQ_GAIN_ODD_161___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__XLNA_GAIN_EVEN_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__LNA_GAIN_EVEN_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__GM_GAIN_EVEN_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__TIA_GAIN_EVEN_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__SLM_XLNA_EVEN_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__BQ_GAIN_EVEN_161___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__XLNA_GAIN_ODD_161___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__XLNA_GAIN_ODD_161___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__LNA_GAIN_ODD_161___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__LNA_GAIN_ODD_161___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__GM_GAIN_ODD_161___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__GM_GAIN_ODD_161___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__TIA_GAIN_ODD_161___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__TIA_GAIN_ODD_161___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__SLM_XLNA_ODD_161___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__SLM_XLNA_ODD_161___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__BQ_GAIN_ODD_161___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__BQ_GAIN_ODD_161___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__XLNA_GAIN_EVEN_161___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__XLNA_GAIN_EVEN_161___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__LNA_GAIN_EVEN_161___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__LNA_GAIN_EVEN_161___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__GM_GAIN_EVEN_161___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__GM_GAIN_EVEN_161___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__TIA_GAIN_EVEN_161___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__TIA_GAIN_EVEN_161___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__SLM_XLNA_EVEN_161___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__SLM_XLNA_EVEN_161___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__BQ_GAIN_EVEN_161___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161__BQ_GAIN_EVEN_161___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_161___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162 (0x005ED288) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__XLNA_GAIN_ODD_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__LNA_GAIN_ODD_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__GM_GAIN_ODD_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__TIA_GAIN_ODD_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__SLM_XLNA_ODD_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__BQ_GAIN_ODD_162___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__XLNA_GAIN_EVEN_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__LNA_GAIN_EVEN_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__GM_GAIN_EVEN_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__TIA_GAIN_EVEN_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__SLM_XLNA_EVEN_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__BQ_GAIN_EVEN_162___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__XLNA_GAIN_ODD_162___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__XLNA_GAIN_ODD_162___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__LNA_GAIN_ODD_162___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__LNA_GAIN_ODD_162___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__GM_GAIN_ODD_162___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__GM_GAIN_ODD_162___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__TIA_GAIN_ODD_162___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__TIA_GAIN_ODD_162___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__SLM_XLNA_ODD_162___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__SLM_XLNA_ODD_162___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__BQ_GAIN_ODD_162___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__BQ_GAIN_ODD_162___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__XLNA_GAIN_EVEN_162___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__XLNA_GAIN_EVEN_162___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__LNA_GAIN_EVEN_162___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__LNA_GAIN_EVEN_162___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__GM_GAIN_EVEN_162___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__GM_GAIN_EVEN_162___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__TIA_GAIN_EVEN_162___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__TIA_GAIN_EVEN_162___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__SLM_XLNA_EVEN_162___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__SLM_XLNA_EVEN_162___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__BQ_GAIN_EVEN_162___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162__BQ_GAIN_EVEN_162___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_162___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163 (0x005ED28C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__XLNA_GAIN_ODD_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__LNA_GAIN_ODD_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__GM_GAIN_ODD_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__TIA_GAIN_ODD_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__SLM_XLNA_ODD_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__BQ_GAIN_ODD_163___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__XLNA_GAIN_EVEN_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__LNA_GAIN_EVEN_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__GM_GAIN_EVEN_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__TIA_GAIN_EVEN_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__SLM_XLNA_EVEN_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__BQ_GAIN_EVEN_163___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__XLNA_GAIN_ODD_163___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__XLNA_GAIN_ODD_163___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__LNA_GAIN_ODD_163___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__LNA_GAIN_ODD_163___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__GM_GAIN_ODD_163___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__GM_GAIN_ODD_163___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__TIA_GAIN_ODD_163___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__TIA_GAIN_ODD_163___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__SLM_XLNA_ODD_163___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__SLM_XLNA_ODD_163___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__BQ_GAIN_ODD_163___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__BQ_GAIN_ODD_163___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__XLNA_GAIN_EVEN_163___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__XLNA_GAIN_EVEN_163___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__LNA_GAIN_EVEN_163___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__LNA_GAIN_EVEN_163___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__GM_GAIN_EVEN_163___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__GM_GAIN_EVEN_163___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__TIA_GAIN_EVEN_163___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__TIA_GAIN_EVEN_163___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__SLM_XLNA_EVEN_163___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__SLM_XLNA_EVEN_163___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__BQ_GAIN_EVEN_163___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163__BQ_GAIN_EVEN_163___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_163___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164 (0x005ED290) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__XLNA_GAIN_ODD_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__LNA_GAIN_ODD_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__GM_GAIN_ODD_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__TIA_GAIN_ODD_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__SLM_XLNA_ODD_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__BQ_GAIN_ODD_164___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__XLNA_GAIN_EVEN_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__LNA_GAIN_EVEN_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__GM_GAIN_EVEN_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__TIA_GAIN_EVEN_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__SLM_XLNA_EVEN_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__BQ_GAIN_EVEN_164___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__XLNA_GAIN_ODD_164___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__XLNA_GAIN_ODD_164___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__LNA_GAIN_ODD_164___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__LNA_GAIN_ODD_164___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__GM_GAIN_ODD_164___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__GM_GAIN_ODD_164___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__TIA_GAIN_ODD_164___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__TIA_GAIN_ODD_164___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__SLM_XLNA_ODD_164___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__SLM_XLNA_ODD_164___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__BQ_GAIN_ODD_164___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__BQ_GAIN_ODD_164___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__XLNA_GAIN_EVEN_164___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__XLNA_GAIN_EVEN_164___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__LNA_GAIN_EVEN_164___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__LNA_GAIN_EVEN_164___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__GM_GAIN_EVEN_164___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__GM_GAIN_EVEN_164___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__TIA_GAIN_EVEN_164___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__TIA_GAIN_EVEN_164___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__SLM_XLNA_EVEN_164___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__SLM_XLNA_EVEN_164___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__BQ_GAIN_EVEN_164___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164__BQ_GAIN_EVEN_164___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_164___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165 (0x005ED294) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__XLNA_GAIN_ODD_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__LNA_GAIN_ODD_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__GM_GAIN_ODD_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__TIA_GAIN_ODD_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__SLM_XLNA_ODD_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__BQ_GAIN_ODD_165___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__XLNA_GAIN_EVEN_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__LNA_GAIN_EVEN_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__GM_GAIN_EVEN_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__TIA_GAIN_EVEN_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__SLM_XLNA_EVEN_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__BQ_GAIN_EVEN_165___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__XLNA_GAIN_ODD_165___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__XLNA_GAIN_ODD_165___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__LNA_GAIN_ODD_165___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__LNA_GAIN_ODD_165___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__GM_GAIN_ODD_165___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__GM_GAIN_ODD_165___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__TIA_GAIN_ODD_165___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__TIA_GAIN_ODD_165___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__SLM_XLNA_ODD_165___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__SLM_XLNA_ODD_165___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__BQ_GAIN_ODD_165___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__BQ_GAIN_ODD_165___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__XLNA_GAIN_EVEN_165___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__XLNA_GAIN_EVEN_165___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__LNA_GAIN_EVEN_165___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__LNA_GAIN_EVEN_165___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__GM_GAIN_EVEN_165___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__GM_GAIN_EVEN_165___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__TIA_GAIN_EVEN_165___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__TIA_GAIN_EVEN_165___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__SLM_XLNA_EVEN_165___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__SLM_XLNA_EVEN_165___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__BQ_GAIN_EVEN_165___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165__BQ_GAIN_EVEN_165___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_165___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166 (0x005ED298) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__XLNA_GAIN_ODD_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__LNA_GAIN_ODD_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__GM_GAIN_ODD_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__TIA_GAIN_ODD_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__SLM_XLNA_ODD_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__BQ_GAIN_ODD_166___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__XLNA_GAIN_EVEN_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__LNA_GAIN_EVEN_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__GM_GAIN_EVEN_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__TIA_GAIN_EVEN_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__SLM_XLNA_EVEN_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__BQ_GAIN_EVEN_166___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__XLNA_GAIN_ODD_166___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__XLNA_GAIN_ODD_166___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__LNA_GAIN_ODD_166___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__LNA_GAIN_ODD_166___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__GM_GAIN_ODD_166___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__GM_GAIN_ODD_166___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__TIA_GAIN_ODD_166___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__TIA_GAIN_ODD_166___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__SLM_XLNA_ODD_166___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__SLM_XLNA_ODD_166___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__BQ_GAIN_ODD_166___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__BQ_GAIN_ODD_166___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__XLNA_GAIN_EVEN_166___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__XLNA_GAIN_EVEN_166___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__LNA_GAIN_EVEN_166___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__LNA_GAIN_EVEN_166___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__GM_GAIN_EVEN_166___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__GM_GAIN_EVEN_166___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__TIA_GAIN_EVEN_166___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__TIA_GAIN_EVEN_166___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__SLM_XLNA_EVEN_166___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__SLM_XLNA_EVEN_166___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__BQ_GAIN_EVEN_166___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166__BQ_GAIN_EVEN_166___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_166___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167 (0x005ED29C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__XLNA_GAIN_ODD_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__LNA_GAIN_ODD_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__GM_GAIN_ODD_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__TIA_GAIN_ODD_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__SLM_XLNA_ODD_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__BQ_GAIN_ODD_167___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__XLNA_GAIN_EVEN_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__LNA_GAIN_EVEN_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__GM_GAIN_EVEN_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__TIA_GAIN_EVEN_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__SLM_XLNA_EVEN_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__BQ_GAIN_EVEN_167___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__XLNA_GAIN_ODD_167___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__XLNA_GAIN_ODD_167___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__LNA_GAIN_ODD_167___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__LNA_GAIN_ODD_167___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__GM_GAIN_ODD_167___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__GM_GAIN_ODD_167___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__TIA_GAIN_ODD_167___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__TIA_GAIN_ODD_167___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__SLM_XLNA_ODD_167___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__SLM_XLNA_ODD_167___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__BQ_GAIN_ODD_167___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__BQ_GAIN_ODD_167___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__XLNA_GAIN_EVEN_167___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__XLNA_GAIN_EVEN_167___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__LNA_GAIN_EVEN_167___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__LNA_GAIN_EVEN_167___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__GM_GAIN_EVEN_167___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__GM_GAIN_EVEN_167___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__TIA_GAIN_EVEN_167___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__TIA_GAIN_EVEN_167___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__SLM_XLNA_EVEN_167___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__SLM_XLNA_EVEN_167___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__BQ_GAIN_EVEN_167___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167__BQ_GAIN_EVEN_167___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_167___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168 (0x005ED2A0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__XLNA_GAIN_ODD_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__LNA_GAIN_ODD_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__GM_GAIN_ODD_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__TIA_GAIN_ODD_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__SLM_XLNA_ODD_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__BQ_GAIN_ODD_168___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__XLNA_GAIN_EVEN_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__LNA_GAIN_EVEN_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__GM_GAIN_EVEN_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__TIA_GAIN_EVEN_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__SLM_XLNA_EVEN_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__BQ_GAIN_EVEN_168___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__XLNA_GAIN_ODD_168___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__XLNA_GAIN_ODD_168___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__LNA_GAIN_ODD_168___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__LNA_GAIN_ODD_168___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__GM_GAIN_ODD_168___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__GM_GAIN_ODD_168___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__TIA_GAIN_ODD_168___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__TIA_GAIN_ODD_168___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__SLM_XLNA_ODD_168___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__SLM_XLNA_ODD_168___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__BQ_GAIN_ODD_168___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__BQ_GAIN_ODD_168___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__XLNA_GAIN_EVEN_168___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__XLNA_GAIN_EVEN_168___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__LNA_GAIN_EVEN_168___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__LNA_GAIN_EVEN_168___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__GM_GAIN_EVEN_168___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__GM_GAIN_EVEN_168___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__TIA_GAIN_EVEN_168___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__TIA_GAIN_EVEN_168___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__SLM_XLNA_EVEN_168___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__SLM_XLNA_EVEN_168___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__BQ_GAIN_EVEN_168___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168__BQ_GAIN_EVEN_168___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_168___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169 (0x005ED2A4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__XLNA_GAIN_ODD_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__LNA_GAIN_ODD_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__GM_GAIN_ODD_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__TIA_GAIN_ODD_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__SLM_XLNA_ODD_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__BQ_GAIN_ODD_169___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__XLNA_GAIN_EVEN_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__LNA_GAIN_EVEN_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__GM_GAIN_EVEN_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__TIA_GAIN_EVEN_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__SLM_XLNA_EVEN_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__BQ_GAIN_EVEN_169___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__XLNA_GAIN_ODD_169___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__XLNA_GAIN_ODD_169___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__LNA_GAIN_ODD_169___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__LNA_GAIN_ODD_169___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__GM_GAIN_ODD_169___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__GM_GAIN_ODD_169___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__TIA_GAIN_ODD_169___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__TIA_GAIN_ODD_169___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__SLM_XLNA_ODD_169___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__SLM_XLNA_ODD_169___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__BQ_GAIN_ODD_169___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__BQ_GAIN_ODD_169___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__XLNA_GAIN_EVEN_169___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__XLNA_GAIN_EVEN_169___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__LNA_GAIN_EVEN_169___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__LNA_GAIN_EVEN_169___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__GM_GAIN_EVEN_169___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__GM_GAIN_EVEN_169___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__TIA_GAIN_EVEN_169___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__TIA_GAIN_EVEN_169___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__SLM_XLNA_EVEN_169___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__SLM_XLNA_EVEN_169___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__BQ_GAIN_EVEN_169___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169__BQ_GAIN_EVEN_169___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_169___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170 (0x005ED2A8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__XLNA_GAIN_ODD_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__LNA_GAIN_ODD_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__GM_GAIN_ODD_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__TIA_GAIN_ODD_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__SLM_XLNA_ODD_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__BQ_GAIN_ODD_170___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__XLNA_GAIN_EVEN_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__LNA_GAIN_EVEN_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__GM_GAIN_EVEN_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__TIA_GAIN_EVEN_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__SLM_XLNA_EVEN_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__BQ_GAIN_EVEN_170___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__XLNA_GAIN_ODD_170___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__XLNA_GAIN_ODD_170___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__LNA_GAIN_ODD_170___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__LNA_GAIN_ODD_170___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__GM_GAIN_ODD_170___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__GM_GAIN_ODD_170___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__TIA_GAIN_ODD_170___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__TIA_GAIN_ODD_170___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__SLM_XLNA_ODD_170___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__SLM_XLNA_ODD_170___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__BQ_GAIN_ODD_170___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__BQ_GAIN_ODD_170___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__XLNA_GAIN_EVEN_170___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__XLNA_GAIN_EVEN_170___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__LNA_GAIN_EVEN_170___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__LNA_GAIN_EVEN_170___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__GM_GAIN_EVEN_170___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__GM_GAIN_EVEN_170___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__TIA_GAIN_EVEN_170___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__TIA_GAIN_EVEN_170___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__SLM_XLNA_EVEN_170___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__SLM_XLNA_EVEN_170___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__BQ_GAIN_EVEN_170___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170__BQ_GAIN_EVEN_170___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_170___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171 (0x005ED2AC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__XLNA_GAIN_ODD_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__LNA_GAIN_ODD_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__GM_GAIN_ODD_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__TIA_GAIN_ODD_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__SLM_XLNA_ODD_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__BQ_GAIN_ODD_171___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__XLNA_GAIN_EVEN_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__LNA_GAIN_EVEN_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__GM_GAIN_EVEN_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__TIA_GAIN_EVEN_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__SLM_XLNA_EVEN_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__BQ_GAIN_EVEN_171___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__XLNA_GAIN_ODD_171___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__XLNA_GAIN_ODD_171___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__LNA_GAIN_ODD_171___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__LNA_GAIN_ODD_171___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__GM_GAIN_ODD_171___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__GM_GAIN_ODD_171___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__TIA_GAIN_ODD_171___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__TIA_GAIN_ODD_171___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__SLM_XLNA_ODD_171___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__SLM_XLNA_ODD_171___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__BQ_GAIN_ODD_171___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__BQ_GAIN_ODD_171___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__XLNA_GAIN_EVEN_171___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__XLNA_GAIN_EVEN_171___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__LNA_GAIN_EVEN_171___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__LNA_GAIN_EVEN_171___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__GM_GAIN_EVEN_171___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__GM_GAIN_EVEN_171___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__TIA_GAIN_EVEN_171___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__TIA_GAIN_EVEN_171___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__SLM_XLNA_EVEN_171___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__SLM_XLNA_EVEN_171___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__BQ_GAIN_EVEN_171___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171__BQ_GAIN_EVEN_171___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_171___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172 (0x005ED2B0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__XLNA_GAIN_ODD_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__LNA_GAIN_ODD_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__GM_GAIN_ODD_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__TIA_GAIN_ODD_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__SLM_XLNA_ODD_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__BQ_GAIN_ODD_172___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__XLNA_GAIN_EVEN_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__LNA_GAIN_EVEN_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__GM_GAIN_EVEN_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__TIA_GAIN_EVEN_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__SLM_XLNA_EVEN_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__BQ_GAIN_EVEN_172___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__XLNA_GAIN_ODD_172___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__XLNA_GAIN_ODD_172___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__LNA_GAIN_ODD_172___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__LNA_GAIN_ODD_172___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__GM_GAIN_ODD_172___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__GM_GAIN_ODD_172___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__TIA_GAIN_ODD_172___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__TIA_GAIN_ODD_172___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__SLM_XLNA_ODD_172___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__SLM_XLNA_ODD_172___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__BQ_GAIN_ODD_172___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__BQ_GAIN_ODD_172___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__XLNA_GAIN_EVEN_172___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__XLNA_GAIN_EVEN_172___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__LNA_GAIN_EVEN_172___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__LNA_GAIN_EVEN_172___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__GM_GAIN_EVEN_172___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__GM_GAIN_EVEN_172___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__TIA_GAIN_EVEN_172___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__TIA_GAIN_EVEN_172___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__SLM_XLNA_EVEN_172___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__SLM_XLNA_EVEN_172___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__BQ_GAIN_EVEN_172___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172__BQ_GAIN_EVEN_172___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_172___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173 (0x005ED2B4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__XLNA_GAIN_ODD_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__LNA_GAIN_ODD_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__GM_GAIN_ODD_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__TIA_GAIN_ODD_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__SLM_XLNA_ODD_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__BQ_GAIN_ODD_173___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__XLNA_GAIN_EVEN_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__LNA_GAIN_EVEN_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__GM_GAIN_EVEN_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__TIA_GAIN_EVEN_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__SLM_XLNA_EVEN_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__BQ_GAIN_EVEN_173___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__XLNA_GAIN_ODD_173___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__XLNA_GAIN_ODD_173___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__LNA_GAIN_ODD_173___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__LNA_GAIN_ODD_173___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__GM_GAIN_ODD_173___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__GM_GAIN_ODD_173___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__TIA_GAIN_ODD_173___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__TIA_GAIN_ODD_173___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__SLM_XLNA_ODD_173___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__SLM_XLNA_ODD_173___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__BQ_GAIN_ODD_173___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__BQ_GAIN_ODD_173___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__XLNA_GAIN_EVEN_173___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__XLNA_GAIN_EVEN_173___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__LNA_GAIN_EVEN_173___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__LNA_GAIN_EVEN_173___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__GM_GAIN_EVEN_173___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__GM_GAIN_EVEN_173___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__TIA_GAIN_EVEN_173___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__TIA_GAIN_EVEN_173___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__SLM_XLNA_EVEN_173___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__SLM_XLNA_EVEN_173___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__BQ_GAIN_EVEN_173___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173__BQ_GAIN_EVEN_173___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_173___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174 (0x005ED2B8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__XLNA_GAIN_ODD_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__LNA_GAIN_ODD_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__GM_GAIN_ODD_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__TIA_GAIN_ODD_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__SLM_XLNA_ODD_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__BQ_GAIN_ODD_174___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__XLNA_GAIN_EVEN_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__LNA_GAIN_EVEN_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__GM_GAIN_EVEN_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__TIA_GAIN_EVEN_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__SLM_XLNA_EVEN_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__BQ_GAIN_EVEN_174___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__XLNA_GAIN_ODD_174___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__XLNA_GAIN_ODD_174___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__LNA_GAIN_ODD_174___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__LNA_GAIN_ODD_174___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__GM_GAIN_ODD_174___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__GM_GAIN_ODD_174___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__TIA_GAIN_ODD_174___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__TIA_GAIN_ODD_174___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__SLM_XLNA_ODD_174___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__SLM_XLNA_ODD_174___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__BQ_GAIN_ODD_174___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__BQ_GAIN_ODD_174___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__XLNA_GAIN_EVEN_174___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__XLNA_GAIN_EVEN_174___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__LNA_GAIN_EVEN_174___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__LNA_GAIN_EVEN_174___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__GM_GAIN_EVEN_174___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__GM_GAIN_EVEN_174___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__TIA_GAIN_EVEN_174___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__TIA_GAIN_EVEN_174___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__SLM_XLNA_EVEN_174___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__SLM_XLNA_EVEN_174___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__BQ_GAIN_EVEN_174___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174__BQ_GAIN_EVEN_174___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_174___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175 (0x005ED2BC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__XLNA_GAIN_ODD_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__LNA_GAIN_ODD_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__GM_GAIN_ODD_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__TIA_GAIN_ODD_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__SLM_XLNA_ODD_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__BQ_GAIN_ODD_175___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__XLNA_GAIN_EVEN_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__LNA_GAIN_EVEN_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__GM_GAIN_EVEN_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__TIA_GAIN_EVEN_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__SLM_XLNA_EVEN_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__BQ_GAIN_EVEN_175___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__XLNA_GAIN_ODD_175___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__XLNA_GAIN_ODD_175___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__LNA_GAIN_ODD_175___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__LNA_GAIN_ODD_175___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__GM_GAIN_ODD_175___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__GM_GAIN_ODD_175___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__TIA_GAIN_ODD_175___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__TIA_GAIN_ODD_175___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__SLM_XLNA_ODD_175___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__SLM_XLNA_ODD_175___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__BQ_GAIN_ODD_175___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__BQ_GAIN_ODD_175___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__XLNA_GAIN_EVEN_175___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__XLNA_GAIN_EVEN_175___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__LNA_GAIN_EVEN_175___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__LNA_GAIN_EVEN_175___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__GM_GAIN_EVEN_175___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__GM_GAIN_EVEN_175___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__TIA_GAIN_EVEN_175___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__TIA_GAIN_EVEN_175___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__SLM_XLNA_EVEN_175___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__SLM_XLNA_EVEN_175___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__BQ_GAIN_EVEN_175___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175__BQ_GAIN_EVEN_175___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_175___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176 (0x005ED2C0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__XLNA_GAIN_ODD_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__LNA_GAIN_ODD_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__GM_GAIN_ODD_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__TIA_GAIN_ODD_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__SLM_XLNA_ODD_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__BQ_GAIN_ODD_176___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__XLNA_GAIN_EVEN_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__LNA_GAIN_EVEN_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__GM_GAIN_EVEN_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__TIA_GAIN_EVEN_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__SLM_XLNA_EVEN_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__BQ_GAIN_EVEN_176___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__XLNA_GAIN_ODD_176___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__XLNA_GAIN_ODD_176___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__LNA_GAIN_ODD_176___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__LNA_GAIN_ODD_176___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__GM_GAIN_ODD_176___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__GM_GAIN_ODD_176___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__TIA_GAIN_ODD_176___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__TIA_GAIN_ODD_176___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__SLM_XLNA_ODD_176___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__SLM_XLNA_ODD_176___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__BQ_GAIN_ODD_176___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__BQ_GAIN_ODD_176___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__XLNA_GAIN_EVEN_176___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__XLNA_GAIN_EVEN_176___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__LNA_GAIN_EVEN_176___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__LNA_GAIN_EVEN_176___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__GM_GAIN_EVEN_176___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__GM_GAIN_EVEN_176___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__TIA_GAIN_EVEN_176___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__TIA_GAIN_EVEN_176___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__SLM_XLNA_EVEN_176___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__SLM_XLNA_EVEN_176___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__BQ_GAIN_EVEN_176___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176__BQ_GAIN_EVEN_176___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_176___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177 (0x005ED2C4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__XLNA_GAIN_ODD_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__LNA_GAIN_ODD_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__GM_GAIN_ODD_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__TIA_GAIN_ODD_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__SLM_XLNA_ODD_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__BQ_GAIN_ODD_177___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__XLNA_GAIN_EVEN_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__LNA_GAIN_EVEN_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__GM_GAIN_EVEN_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__TIA_GAIN_EVEN_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__SLM_XLNA_EVEN_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__BQ_GAIN_EVEN_177___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__XLNA_GAIN_ODD_177___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__XLNA_GAIN_ODD_177___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__LNA_GAIN_ODD_177___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__LNA_GAIN_ODD_177___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__GM_GAIN_ODD_177___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__GM_GAIN_ODD_177___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__TIA_GAIN_ODD_177___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__TIA_GAIN_ODD_177___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__SLM_XLNA_ODD_177___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__SLM_XLNA_ODD_177___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__BQ_GAIN_ODD_177___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__BQ_GAIN_ODD_177___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__XLNA_GAIN_EVEN_177___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__XLNA_GAIN_EVEN_177___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__LNA_GAIN_EVEN_177___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__LNA_GAIN_EVEN_177___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__GM_GAIN_EVEN_177___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__GM_GAIN_EVEN_177___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__TIA_GAIN_EVEN_177___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__TIA_GAIN_EVEN_177___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__SLM_XLNA_EVEN_177___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__SLM_XLNA_EVEN_177___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__BQ_GAIN_EVEN_177___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177__BQ_GAIN_EVEN_177___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_177___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178 (0x005ED2C8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__XLNA_GAIN_ODD_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__LNA_GAIN_ODD_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__GM_GAIN_ODD_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__TIA_GAIN_ODD_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__SLM_XLNA_ODD_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__BQ_GAIN_ODD_178___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__XLNA_GAIN_EVEN_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__LNA_GAIN_EVEN_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__GM_GAIN_EVEN_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__TIA_GAIN_EVEN_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__SLM_XLNA_EVEN_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__BQ_GAIN_EVEN_178___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__XLNA_GAIN_ODD_178___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__XLNA_GAIN_ODD_178___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__LNA_GAIN_ODD_178___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__LNA_GAIN_ODD_178___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__GM_GAIN_ODD_178___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__GM_GAIN_ODD_178___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__TIA_GAIN_ODD_178___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__TIA_GAIN_ODD_178___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__SLM_XLNA_ODD_178___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__SLM_XLNA_ODD_178___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__BQ_GAIN_ODD_178___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__BQ_GAIN_ODD_178___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__XLNA_GAIN_EVEN_178___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__XLNA_GAIN_EVEN_178___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__LNA_GAIN_EVEN_178___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__LNA_GAIN_EVEN_178___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__GM_GAIN_EVEN_178___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__GM_GAIN_EVEN_178___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__TIA_GAIN_EVEN_178___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__TIA_GAIN_EVEN_178___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__SLM_XLNA_EVEN_178___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__SLM_XLNA_EVEN_178___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__BQ_GAIN_EVEN_178___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178__BQ_GAIN_EVEN_178___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_178___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179 (0x005ED2CC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__XLNA_GAIN_ODD_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__LNA_GAIN_ODD_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__GM_GAIN_ODD_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__TIA_GAIN_ODD_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__SLM_XLNA_ODD_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__BQ_GAIN_ODD_179___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__XLNA_GAIN_EVEN_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__LNA_GAIN_EVEN_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__GM_GAIN_EVEN_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__TIA_GAIN_EVEN_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__SLM_XLNA_EVEN_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__BQ_GAIN_EVEN_179___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__XLNA_GAIN_ODD_179___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__XLNA_GAIN_ODD_179___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__LNA_GAIN_ODD_179___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__LNA_GAIN_ODD_179___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__GM_GAIN_ODD_179___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__GM_GAIN_ODD_179___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__TIA_GAIN_ODD_179___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__TIA_GAIN_ODD_179___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__SLM_XLNA_ODD_179___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__SLM_XLNA_ODD_179___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__BQ_GAIN_ODD_179___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__BQ_GAIN_ODD_179___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__XLNA_GAIN_EVEN_179___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__XLNA_GAIN_EVEN_179___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__LNA_GAIN_EVEN_179___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__LNA_GAIN_EVEN_179___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__GM_GAIN_EVEN_179___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__GM_GAIN_EVEN_179___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__TIA_GAIN_EVEN_179___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__TIA_GAIN_EVEN_179___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__SLM_XLNA_EVEN_179___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__SLM_XLNA_EVEN_179___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__BQ_GAIN_EVEN_179___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179__BQ_GAIN_EVEN_179___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_179___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180 (0x005ED2D0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__XLNA_GAIN_ODD_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__LNA_GAIN_ODD_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__GM_GAIN_ODD_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__TIA_GAIN_ODD_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__SLM_XLNA_ODD_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__BQ_GAIN_ODD_180___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__XLNA_GAIN_EVEN_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__LNA_GAIN_EVEN_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__GM_GAIN_EVEN_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__TIA_GAIN_EVEN_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__SLM_XLNA_EVEN_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__BQ_GAIN_EVEN_180___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__XLNA_GAIN_ODD_180___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__XLNA_GAIN_ODD_180___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__LNA_GAIN_ODD_180___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__LNA_GAIN_ODD_180___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__GM_GAIN_ODD_180___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__GM_GAIN_ODD_180___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__TIA_GAIN_ODD_180___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__TIA_GAIN_ODD_180___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__SLM_XLNA_ODD_180___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__SLM_XLNA_ODD_180___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__BQ_GAIN_ODD_180___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__BQ_GAIN_ODD_180___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__XLNA_GAIN_EVEN_180___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__XLNA_GAIN_EVEN_180___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__LNA_GAIN_EVEN_180___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__LNA_GAIN_EVEN_180___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__GM_GAIN_EVEN_180___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__GM_GAIN_EVEN_180___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__TIA_GAIN_EVEN_180___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__TIA_GAIN_EVEN_180___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__SLM_XLNA_EVEN_180___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__SLM_XLNA_EVEN_180___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__BQ_GAIN_EVEN_180___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180__BQ_GAIN_EVEN_180___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_180___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181 (0x005ED2D4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__XLNA_GAIN_ODD_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__LNA_GAIN_ODD_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__GM_GAIN_ODD_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__TIA_GAIN_ODD_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__SLM_XLNA_ODD_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__BQ_GAIN_ODD_181___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__XLNA_GAIN_EVEN_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__LNA_GAIN_EVEN_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__GM_GAIN_EVEN_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__TIA_GAIN_EVEN_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__SLM_XLNA_EVEN_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__BQ_GAIN_EVEN_181___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__XLNA_GAIN_ODD_181___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__XLNA_GAIN_ODD_181___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__LNA_GAIN_ODD_181___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__LNA_GAIN_ODD_181___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__GM_GAIN_ODD_181___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__GM_GAIN_ODD_181___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__TIA_GAIN_ODD_181___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__TIA_GAIN_ODD_181___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__SLM_XLNA_ODD_181___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__SLM_XLNA_ODD_181___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__BQ_GAIN_ODD_181___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__BQ_GAIN_ODD_181___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__XLNA_GAIN_EVEN_181___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__XLNA_GAIN_EVEN_181___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__LNA_GAIN_EVEN_181___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__LNA_GAIN_EVEN_181___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__GM_GAIN_EVEN_181___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__GM_GAIN_EVEN_181___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__TIA_GAIN_EVEN_181___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__TIA_GAIN_EVEN_181___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__SLM_XLNA_EVEN_181___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__SLM_XLNA_EVEN_181___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__BQ_GAIN_EVEN_181___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181__BQ_GAIN_EVEN_181___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_181___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182 (0x005ED2D8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__XLNA_GAIN_ODD_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__LNA_GAIN_ODD_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__GM_GAIN_ODD_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__TIA_GAIN_ODD_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__SLM_XLNA_ODD_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__BQ_GAIN_ODD_182___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__XLNA_GAIN_EVEN_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__LNA_GAIN_EVEN_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__GM_GAIN_EVEN_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__TIA_GAIN_EVEN_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__SLM_XLNA_EVEN_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__BQ_GAIN_EVEN_182___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__XLNA_GAIN_ODD_182___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__XLNA_GAIN_ODD_182___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__LNA_GAIN_ODD_182___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__LNA_GAIN_ODD_182___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__GM_GAIN_ODD_182___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__GM_GAIN_ODD_182___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__TIA_GAIN_ODD_182___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__TIA_GAIN_ODD_182___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__SLM_XLNA_ODD_182___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__SLM_XLNA_ODD_182___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__BQ_GAIN_ODD_182___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__BQ_GAIN_ODD_182___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__XLNA_GAIN_EVEN_182___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__XLNA_GAIN_EVEN_182___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__LNA_GAIN_EVEN_182___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__LNA_GAIN_EVEN_182___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__GM_GAIN_EVEN_182___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__GM_GAIN_EVEN_182___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__TIA_GAIN_EVEN_182___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__TIA_GAIN_EVEN_182___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__SLM_XLNA_EVEN_182___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__SLM_XLNA_EVEN_182___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__BQ_GAIN_EVEN_182___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182__BQ_GAIN_EVEN_182___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_182___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183 (0x005ED2DC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__XLNA_GAIN_ODD_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__LNA_GAIN_ODD_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__GM_GAIN_ODD_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__TIA_GAIN_ODD_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__SLM_XLNA_ODD_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__BQ_GAIN_ODD_183___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__XLNA_GAIN_EVEN_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__LNA_GAIN_EVEN_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__GM_GAIN_EVEN_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__TIA_GAIN_EVEN_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__SLM_XLNA_EVEN_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__BQ_GAIN_EVEN_183___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__XLNA_GAIN_ODD_183___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__XLNA_GAIN_ODD_183___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__LNA_GAIN_ODD_183___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__LNA_GAIN_ODD_183___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__GM_GAIN_ODD_183___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__GM_GAIN_ODD_183___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__TIA_GAIN_ODD_183___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__TIA_GAIN_ODD_183___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__SLM_XLNA_ODD_183___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__SLM_XLNA_ODD_183___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__BQ_GAIN_ODD_183___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__BQ_GAIN_ODD_183___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__XLNA_GAIN_EVEN_183___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__XLNA_GAIN_EVEN_183___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__LNA_GAIN_EVEN_183___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__LNA_GAIN_EVEN_183___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__GM_GAIN_EVEN_183___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__GM_GAIN_EVEN_183___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__TIA_GAIN_EVEN_183___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__TIA_GAIN_EVEN_183___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__SLM_XLNA_EVEN_183___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__SLM_XLNA_EVEN_183___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__BQ_GAIN_EVEN_183___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183__BQ_GAIN_EVEN_183___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_183___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184 (0x005ED2E0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__XLNA_GAIN_ODD_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__LNA_GAIN_ODD_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__GM_GAIN_ODD_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__TIA_GAIN_ODD_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__SLM_XLNA_ODD_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__BQ_GAIN_ODD_184___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__XLNA_GAIN_EVEN_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__LNA_GAIN_EVEN_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__GM_GAIN_EVEN_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__TIA_GAIN_EVEN_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__SLM_XLNA_EVEN_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__BQ_GAIN_EVEN_184___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__XLNA_GAIN_ODD_184___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__XLNA_GAIN_ODD_184___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__LNA_GAIN_ODD_184___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__LNA_GAIN_ODD_184___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__GM_GAIN_ODD_184___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__GM_GAIN_ODD_184___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__TIA_GAIN_ODD_184___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__TIA_GAIN_ODD_184___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__SLM_XLNA_ODD_184___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__SLM_XLNA_ODD_184___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__BQ_GAIN_ODD_184___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__BQ_GAIN_ODD_184___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__XLNA_GAIN_EVEN_184___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__XLNA_GAIN_EVEN_184___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__LNA_GAIN_EVEN_184___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__LNA_GAIN_EVEN_184___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__GM_GAIN_EVEN_184___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__GM_GAIN_EVEN_184___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__TIA_GAIN_EVEN_184___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__TIA_GAIN_EVEN_184___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__SLM_XLNA_EVEN_184___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__SLM_XLNA_EVEN_184___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__BQ_GAIN_EVEN_184___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184__BQ_GAIN_EVEN_184___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_184___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185 (0x005ED2E4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__XLNA_GAIN_ODD_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__LNA_GAIN_ODD_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__GM_GAIN_ODD_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__TIA_GAIN_ODD_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__SLM_XLNA_ODD_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__BQ_GAIN_ODD_185___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__XLNA_GAIN_EVEN_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__LNA_GAIN_EVEN_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__GM_GAIN_EVEN_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__TIA_GAIN_EVEN_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__SLM_XLNA_EVEN_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__BQ_GAIN_EVEN_185___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__XLNA_GAIN_ODD_185___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__XLNA_GAIN_ODD_185___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__LNA_GAIN_ODD_185___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__LNA_GAIN_ODD_185___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__GM_GAIN_ODD_185___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__GM_GAIN_ODD_185___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__TIA_GAIN_ODD_185___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__TIA_GAIN_ODD_185___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__SLM_XLNA_ODD_185___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__SLM_XLNA_ODD_185___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__BQ_GAIN_ODD_185___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__BQ_GAIN_ODD_185___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__XLNA_GAIN_EVEN_185___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__XLNA_GAIN_EVEN_185___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__LNA_GAIN_EVEN_185___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__LNA_GAIN_EVEN_185___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__GM_GAIN_EVEN_185___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__GM_GAIN_EVEN_185___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__TIA_GAIN_EVEN_185___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__TIA_GAIN_EVEN_185___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__SLM_XLNA_EVEN_185___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__SLM_XLNA_EVEN_185___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__BQ_GAIN_EVEN_185___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185__BQ_GAIN_EVEN_185___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_185___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186 (0x005ED2E8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__XLNA_GAIN_ODD_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__LNA_GAIN_ODD_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__GM_GAIN_ODD_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__TIA_GAIN_ODD_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__SLM_XLNA_ODD_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__BQ_GAIN_ODD_186___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__XLNA_GAIN_EVEN_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__LNA_GAIN_EVEN_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__GM_GAIN_EVEN_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__TIA_GAIN_EVEN_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__SLM_XLNA_EVEN_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__BQ_GAIN_EVEN_186___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__XLNA_GAIN_ODD_186___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__XLNA_GAIN_ODD_186___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__LNA_GAIN_ODD_186___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__LNA_GAIN_ODD_186___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__GM_GAIN_ODD_186___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__GM_GAIN_ODD_186___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__TIA_GAIN_ODD_186___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__TIA_GAIN_ODD_186___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__SLM_XLNA_ODD_186___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__SLM_XLNA_ODD_186___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__BQ_GAIN_ODD_186___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__BQ_GAIN_ODD_186___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__XLNA_GAIN_EVEN_186___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__XLNA_GAIN_EVEN_186___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__LNA_GAIN_EVEN_186___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__LNA_GAIN_EVEN_186___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__GM_GAIN_EVEN_186___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__GM_GAIN_EVEN_186___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__TIA_GAIN_EVEN_186___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__TIA_GAIN_EVEN_186___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__SLM_XLNA_EVEN_186___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__SLM_XLNA_EVEN_186___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__BQ_GAIN_EVEN_186___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186__BQ_GAIN_EVEN_186___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_186___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187 (0x005ED2EC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__XLNA_GAIN_ODD_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__LNA_GAIN_ODD_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__GM_GAIN_ODD_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__TIA_GAIN_ODD_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__SLM_XLNA_ODD_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__BQ_GAIN_ODD_187___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__XLNA_GAIN_EVEN_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__LNA_GAIN_EVEN_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__GM_GAIN_EVEN_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__TIA_GAIN_EVEN_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__SLM_XLNA_EVEN_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__BQ_GAIN_EVEN_187___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__XLNA_GAIN_ODD_187___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__XLNA_GAIN_ODD_187___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__LNA_GAIN_ODD_187___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__LNA_GAIN_ODD_187___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__GM_GAIN_ODD_187___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__GM_GAIN_ODD_187___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__TIA_GAIN_ODD_187___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__TIA_GAIN_ODD_187___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__SLM_XLNA_ODD_187___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__SLM_XLNA_ODD_187___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__BQ_GAIN_ODD_187___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__BQ_GAIN_ODD_187___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__XLNA_GAIN_EVEN_187___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__XLNA_GAIN_EVEN_187___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__LNA_GAIN_EVEN_187___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__LNA_GAIN_EVEN_187___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__GM_GAIN_EVEN_187___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__GM_GAIN_EVEN_187___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__TIA_GAIN_EVEN_187___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__TIA_GAIN_EVEN_187___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__SLM_XLNA_EVEN_187___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__SLM_XLNA_EVEN_187___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__BQ_GAIN_EVEN_187___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187__BQ_GAIN_EVEN_187___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_187___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188 (0x005ED2F0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__XLNA_GAIN_ODD_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__LNA_GAIN_ODD_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__GM_GAIN_ODD_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__TIA_GAIN_ODD_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__SLM_XLNA_ODD_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__BQ_GAIN_ODD_188___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__XLNA_GAIN_EVEN_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__LNA_GAIN_EVEN_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__GM_GAIN_EVEN_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__TIA_GAIN_EVEN_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__SLM_XLNA_EVEN_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__BQ_GAIN_EVEN_188___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__XLNA_GAIN_ODD_188___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__XLNA_GAIN_ODD_188___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__LNA_GAIN_ODD_188___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__LNA_GAIN_ODD_188___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__GM_GAIN_ODD_188___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__GM_GAIN_ODD_188___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__TIA_GAIN_ODD_188___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__TIA_GAIN_ODD_188___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__SLM_XLNA_ODD_188___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__SLM_XLNA_ODD_188___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__BQ_GAIN_ODD_188___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__BQ_GAIN_ODD_188___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__XLNA_GAIN_EVEN_188___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__XLNA_GAIN_EVEN_188___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__LNA_GAIN_EVEN_188___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__LNA_GAIN_EVEN_188___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__GM_GAIN_EVEN_188___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__GM_GAIN_EVEN_188___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__TIA_GAIN_EVEN_188___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__TIA_GAIN_EVEN_188___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__SLM_XLNA_EVEN_188___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__SLM_XLNA_EVEN_188___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__BQ_GAIN_EVEN_188___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188__BQ_GAIN_EVEN_188___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_188___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189 (0x005ED2F4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__XLNA_GAIN_ODD_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__LNA_GAIN_ODD_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__GM_GAIN_ODD_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__TIA_GAIN_ODD_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__SLM_XLNA_ODD_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__BQ_GAIN_ODD_189___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__XLNA_GAIN_EVEN_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__LNA_GAIN_EVEN_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__GM_GAIN_EVEN_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__TIA_GAIN_EVEN_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__SLM_XLNA_EVEN_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__BQ_GAIN_EVEN_189___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__XLNA_GAIN_ODD_189___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__XLNA_GAIN_ODD_189___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__LNA_GAIN_ODD_189___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__LNA_GAIN_ODD_189___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__GM_GAIN_ODD_189___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__GM_GAIN_ODD_189___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__TIA_GAIN_ODD_189___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__TIA_GAIN_ODD_189___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__SLM_XLNA_ODD_189___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__SLM_XLNA_ODD_189___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__BQ_GAIN_ODD_189___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__BQ_GAIN_ODD_189___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__XLNA_GAIN_EVEN_189___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__XLNA_GAIN_EVEN_189___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__LNA_GAIN_EVEN_189___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__LNA_GAIN_EVEN_189___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__GM_GAIN_EVEN_189___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__GM_GAIN_EVEN_189___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__TIA_GAIN_EVEN_189___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__TIA_GAIN_EVEN_189___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__SLM_XLNA_EVEN_189___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__SLM_XLNA_EVEN_189___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__BQ_GAIN_EVEN_189___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189__BQ_GAIN_EVEN_189___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_189___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190 (0x005ED2F8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__XLNA_GAIN_ODD_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__LNA_GAIN_ODD_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__GM_GAIN_ODD_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__TIA_GAIN_ODD_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__SLM_XLNA_ODD_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__BQ_GAIN_ODD_190___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__XLNA_GAIN_EVEN_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__LNA_GAIN_EVEN_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__GM_GAIN_EVEN_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__TIA_GAIN_EVEN_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__SLM_XLNA_EVEN_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__BQ_GAIN_EVEN_190___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__XLNA_GAIN_ODD_190___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__XLNA_GAIN_ODD_190___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__LNA_GAIN_ODD_190___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__LNA_GAIN_ODD_190___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__GM_GAIN_ODD_190___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__GM_GAIN_ODD_190___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__TIA_GAIN_ODD_190___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__TIA_GAIN_ODD_190___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__SLM_XLNA_ODD_190___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__SLM_XLNA_ODD_190___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__BQ_GAIN_ODD_190___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__BQ_GAIN_ODD_190___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__XLNA_GAIN_EVEN_190___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__XLNA_GAIN_EVEN_190___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__LNA_GAIN_EVEN_190___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__LNA_GAIN_EVEN_190___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__GM_GAIN_EVEN_190___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__GM_GAIN_EVEN_190___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__TIA_GAIN_EVEN_190___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__TIA_GAIN_EVEN_190___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__SLM_XLNA_EVEN_190___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__SLM_XLNA_EVEN_190___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__BQ_GAIN_EVEN_190___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190__BQ_GAIN_EVEN_190___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_190___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191 (0x005ED2FC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__XLNA_GAIN_ODD_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__LNA_GAIN_ODD_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__GM_GAIN_ODD_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__TIA_GAIN_ODD_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__SLM_XLNA_ODD_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__BQ_GAIN_ODD_191___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__XLNA_GAIN_EVEN_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__LNA_GAIN_EVEN_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__GM_GAIN_EVEN_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__TIA_GAIN_EVEN_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__SLM_XLNA_EVEN_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__BQ_GAIN_EVEN_191___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__XLNA_GAIN_ODD_191___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__XLNA_GAIN_ODD_191___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__LNA_GAIN_ODD_191___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__LNA_GAIN_ODD_191___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__GM_GAIN_ODD_191___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__GM_GAIN_ODD_191___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__TIA_GAIN_ODD_191___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__TIA_GAIN_ODD_191___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__SLM_XLNA_ODD_191___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__SLM_XLNA_ODD_191___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__BQ_GAIN_ODD_191___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__BQ_GAIN_ODD_191___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__XLNA_GAIN_EVEN_191___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__XLNA_GAIN_EVEN_191___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__LNA_GAIN_EVEN_191___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__LNA_GAIN_EVEN_191___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__GM_GAIN_EVEN_191___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__GM_GAIN_EVEN_191___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__TIA_GAIN_EVEN_191___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__TIA_GAIN_EVEN_191___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__SLM_XLNA_EVEN_191___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__SLM_XLNA_EVEN_191___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__BQ_GAIN_EVEN_191___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191__BQ_GAIN_EVEN_191___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_191___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192 (0x005ED300) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__XLNA_GAIN_ODD_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__LNA_GAIN_ODD_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__GM_GAIN_ODD_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__TIA_GAIN_ODD_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__SLM_XLNA_ODD_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__BQ_GAIN_ODD_192___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__XLNA_GAIN_EVEN_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__LNA_GAIN_EVEN_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__GM_GAIN_EVEN_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__TIA_GAIN_EVEN_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__SLM_XLNA_EVEN_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__BQ_GAIN_EVEN_192___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__XLNA_GAIN_ODD_192___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__XLNA_GAIN_ODD_192___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__LNA_GAIN_ODD_192___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__LNA_GAIN_ODD_192___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__GM_GAIN_ODD_192___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__GM_GAIN_ODD_192___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__TIA_GAIN_ODD_192___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__TIA_GAIN_ODD_192___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__SLM_XLNA_ODD_192___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__SLM_XLNA_ODD_192___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__BQ_GAIN_ODD_192___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__BQ_GAIN_ODD_192___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__XLNA_GAIN_EVEN_192___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__XLNA_GAIN_EVEN_192___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__LNA_GAIN_EVEN_192___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__LNA_GAIN_EVEN_192___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__GM_GAIN_EVEN_192___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__GM_GAIN_EVEN_192___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__TIA_GAIN_EVEN_192___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__TIA_GAIN_EVEN_192___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__SLM_XLNA_EVEN_192___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__SLM_XLNA_EVEN_192___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__BQ_GAIN_EVEN_192___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192__BQ_GAIN_EVEN_192___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_192___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193 (0x005ED304) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__XLNA_GAIN_ODD_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__LNA_GAIN_ODD_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__GM_GAIN_ODD_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__TIA_GAIN_ODD_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__SLM_XLNA_ODD_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__BQ_GAIN_ODD_193___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__XLNA_GAIN_EVEN_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__LNA_GAIN_EVEN_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__GM_GAIN_EVEN_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__TIA_GAIN_EVEN_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__SLM_XLNA_EVEN_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__BQ_GAIN_EVEN_193___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__XLNA_GAIN_ODD_193___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__XLNA_GAIN_ODD_193___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__LNA_GAIN_ODD_193___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__LNA_GAIN_ODD_193___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__GM_GAIN_ODD_193___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__GM_GAIN_ODD_193___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__TIA_GAIN_ODD_193___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__TIA_GAIN_ODD_193___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__SLM_XLNA_ODD_193___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__SLM_XLNA_ODD_193___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__BQ_GAIN_ODD_193___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__BQ_GAIN_ODD_193___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__XLNA_GAIN_EVEN_193___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__XLNA_GAIN_EVEN_193___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__LNA_GAIN_EVEN_193___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__LNA_GAIN_EVEN_193___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__GM_GAIN_EVEN_193___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__GM_GAIN_EVEN_193___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__TIA_GAIN_EVEN_193___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__TIA_GAIN_EVEN_193___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__SLM_XLNA_EVEN_193___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__SLM_XLNA_EVEN_193___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__BQ_GAIN_EVEN_193___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193__BQ_GAIN_EVEN_193___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_193___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194 (0x005ED308) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__XLNA_GAIN_ODD_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__LNA_GAIN_ODD_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__GM_GAIN_ODD_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__TIA_GAIN_ODD_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__SLM_XLNA_ODD_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__BQ_GAIN_ODD_194___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__XLNA_GAIN_EVEN_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__LNA_GAIN_EVEN_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__GM_GAIN_EVEN_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__TIA_GAIN_EVEN_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__SLM_XLNA_EVEN_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__BQ_GAIN_EVEN_194___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__XLNA_GAIN_ODD_194___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__XLNA_GAIN_ODD_194___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__LNA_GAIN_ODD_194___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__LNA_GAIN_ODD_194___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__GM_GAIN_ODD_194___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__GM_GAIN_ODD_194___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__TIA_GAIN_ODD_194___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__TIA_GAIN_ODD_194___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__SLM_XLNA_ODD_194___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__SLM_XLNA_ODD_194___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__BQ_GAIN_ODD_194___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__BQ_GAIN_ODD_194___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__XLNA_GAIN_EVEN_194___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__XLNA_GAIN_EVEN_194___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__LNA_GAIN_EVEN_194___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__LNA_GAIN_EVEN_194___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__GM_GAIN_EVEN_194___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__GM_GAIN_EVEN_194___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__TIA_GAIN_EVEN_194___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__TIA_GAIN_EVEN_194___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__SLM_XLNA_EVEN_194___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__SLM_XLNA_EVEN_194___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__BQ_GAIN_EVEN_194___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194__BQ_GAIN_EVEN_194___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_194___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195 (0x005ED30C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__XLNA_GAIN_ODD_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__LNA_GAIN_ODD_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__GM_GAIN_ODD_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__TIA_GAIN_ODD_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__SLM_XLNA_ODD_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__BQ_GAIN_ODD_195___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__XLNA_GAIN_EVEN_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__LNA_GAIN_EVEN_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__GM_GAIN_EVEN_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__TIA_GAIN_EVEN_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__SLM_XLNA_EVEN_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__BQ_GAIN_EVEN_195___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__XLNA_GAIN_ODD_195___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__XLNA_GAIN_ODD_195___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__LNA_GAIN_ODD_195___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__LNA_GAIN_ODD_195___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__GM_GAIN_ODD_195___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__GM_GAIN_ODD_195___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__TIA_GAIN_ODD_195___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__TIA_GAIN_ODD_195___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__SLM_XLNA_ODD_195___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__SLM_XLNA_ODD_195___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__BQ_GAIN_ODD_195___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__BQ_GAIN_ODD_195___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__XLNA_GAIN_EVEN_195___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__XLNA_GAIN_EVEN_195___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__LNA_GAIN_EVEN_195___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__LNA_GAIN_EVEN_195___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__GM_GAIN_EVEN_195___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__GM_GAIN_EVEN_195___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__TIA_GAIN_EVEN_195___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__TIA_GAIN_EVEN_195___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__SLM_XLNA_EVEN_195___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__SLM_XLNA_EVEN_195___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__BQ_GAIN_EVEN_195___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195__BQ_GAIN_EVEN_195___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_195___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196 (0x005ED310) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__XLNA_GAIN_ODD_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__LNA_GAIN_ODD_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__GM_GAIN_ODD_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__TIA_GAIN_ODD_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__SLM_XLNA_ODD_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__BQ_GAIN_ODD_196___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__XLNA_GAIN_EVEN_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__LNA_GAIN_EVEN_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__GM_GAIN_EVEN_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__TIA_GAIN_EVEN_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__SLM_XLNA_EVEN_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__BQ_GAIN_EVEN_196___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__XLNA_GAIN_ODD_196___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__XLNA_GAIN_ODD_196___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__LNA_GAIN_ODD_196___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__LNA_GAIN_ODD_196___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__GM_GAIN_ODD_196___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__GM_GAIN_ODD_196___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__TIA_GAIN_ODD_196___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__TIA_GAIN_ODD_196___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__SLM_XLNA_ODD_196___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__SLM_XLNA_ODD_196___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__BQ_GAIN_ODD_196___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__BQ_GAIN_ODD_196___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__XLNA_GAIN_EVEN_196___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__XLNA_GAIN_EVEN_196___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__LNA_GAIN_EVEN_196___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__LNA_GAIN_EVEN_196___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__GM_GAIN_EVEN_196___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__GM_GAIN_EVEN_196___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__TIA_GAIN_EVEN_196___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__TIA_GAIN_EVEN_196___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__SLM_XLNA_EVEN_196___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__SLM_XLNA_EVEN_196___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__BQ_GAIN_EVEN_196___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196__BQ_GAIN_EVEN_196___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_196___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197 (0x005ED314) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__XLNA_GAIN_ODD_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__LNA_GAIN_ODD_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__GM_GAIN_ODD_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__TIA_GAIN_ODD_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__SLM_XLNA_ODD_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__BQ_GAIN_ODD_197___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__XLNA_GAIN_EVEN_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__LNA_GAIN_EVEN_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__GM_GAIN_EVEN_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__TIA_GAIN_EVEN_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__SLM_XLNA_EVEN_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__BQ_GAIN_EVEN_197___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__XLNA_GAIN_ODD_197___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__XLNA_GAIN_ODD_197___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__LNA_GAIN_ODD_197___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__LNA_GAIN_ODD_197___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__GM_GAIN_ODD_197___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__GM_GAIN_ODD_197___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__TIA_GAIN_ODD_197___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__TIA_GAIN_ODD_197___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__SLM_XLNA_ODD_197___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__SLM_XLNA_ODD_197___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__BQ_GAIN_ODD_197___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__BQ_GAIN_ODD_197___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__XLNA_GAIN_EVEN_197___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__XLNA_GAIN_EVEN_197___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__LNA_GAIN_EVEN_197___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__LNA_GAIN_EVEN_197___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__GM_GAIN_EVEN_197___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__GM_GAIN_EVEN_197___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__TIA_GAIN_EVEN_197___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__TIA_GAIN_EVEN_197___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__SLM_XLNA_EVEN_197___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__SLM_XLNA_EVEN_197___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__BQ_GAIN_EVEN_197___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197__BQ_GAIN_EVEN_197___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_197___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198 (0x005ED318) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__XLNA_GAIN_ODD_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__LNA_GAIN_ODD_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__GM_GAIN_ODD_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__TIA_GAIN_ODD_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__SLM_XLNA_ODD_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__BQ_GAIN_ODD_198___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__XLNA_GAIN_EVEN_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__LNA_GAIN_EVEN_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__GM_GAIN_EVEN_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__TIA_GAIN_EVEN_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__SLM_XLNA_EVEN_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__BQ_GAIN_EVEN_198___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__XLNA_GAIN_ODD_198___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__XLNA_GAIN_ODD_198___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__LNA_GAIN_ODD_198___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__LNA_GAIN_ODD_198___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__GM_GAIN_ODD_198___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__GM_GAIN_ODD_198___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__TIA_GAIN_ODD_198___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__TIA_GAIN_ODD_198___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__SLM_XLNA_ODD_198___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__SLM_XLNA_ODD_198___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__BQ_GAIN_ODD_198___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__BQ_GAIN_ODD_198___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__XLNA_GAIN_EVEN_198___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__XLNA_GAIN_EVEN_198___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__LNA_GAIN_EVEN_198___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__LNA_GAIN_EVEN_198___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__GM_GAIN_EVEN_198___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__GM_GAIN_EVEN_198___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__TIA_GAIN_EVEN_198___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__TIA_GAIN_EVEN_198___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__SLM_XLNA_EVEN_198___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__SLM_XLNA_EVEN_198___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__BQ_GAIN_EVEN_198___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198__BQ_GAIN_EVEN_198___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_198___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199 (0x005ED31C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__XLNA_GAIN_ODD_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__LNA_GAIN_ODD_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__GM_GAIN_ODD_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__TIA_GAIN_ODD_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__SLM_XLNA_ODD_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__BQ_GAIN_ODD_199___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__XLNA_GAIN_EVEN_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__LNA_GAIN_EVEN_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__GM_GAIN_EVEN_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__TIA_GAIN_EVEN_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__SLM_XLNA_EVEN_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__BQ_GAIN_EVEN_199___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__XLNA_GAIN_ODD_199___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__XLNA_GAIN_ODD_199___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__LNA_GAIN_ODD_199___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__LNA_GAIN_ODD_199___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__GM_GAIN_ODD_199___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__GM_GAIN_ODD_199___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__TIA_GAIN_ODD_199___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__TIA_GAIN_ODD_199___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__SLM_XLNA_ODD_199___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__SLM_XLNA_ODD_199___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__BQ_GAIN_ODD_199___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__BQ_GAIN_ODD_199___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__XLNA_GAIN_EVEN_199___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__XLNA_GAIN_EVEN_199___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__LNA_GAIN_EVEN_199___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__LNA_GAIN_EVEN_199___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__GM_GAIN_EVEN_199___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__GM_GAIN_EVEN_199___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__TIA_GAIN_EVEN_199___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__TIA_GAIN_EVEN_199___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__SLM_XLNA_EVEN_199___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__SLM_XLNA_EVEN_199___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__BQ_GAIN_EVEN_199___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199__BQ_GAIN_EVEN_199___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_199___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200 (0x005ED320) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__XLNA_GAIN_ODD_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__LNA_GAIN_ODD_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__GM_GAIN_ODD_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__TIA_GAIN_ODD_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__SLM_XLNA_ODD_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__BQ_GAIN_ODD_200___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__XLNA_GAIN_EVEN_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__LNA_GAIN_EVEN_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__GM_GAIN_EVEN_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__TIA_GAIN_EVEN_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__SLM_XLNA_EVEN_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__BQ_GAIN_EVEN_200___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__XLNA_GAIN_ODD_200___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__XLNA_GAIN_ODD_200___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__LNA_GAIN_ODD_200___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__LNA_GAIN_ODD_200___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__GM_GAIN_ODD_200___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__GM_GAIN_ODD_200___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__TIA_GAIN_ODD_200___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__TIA_GAIN_ODD_200___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__SLM_XLNA_ODD_200___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__SLM_XLNA_ODD_200___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__BQ_GAIN_ODD_200___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__BQ_GAIN_ODD_200___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__XLNA_GAIN_EVEN_200___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__XLNA_GAIN_EVEN_200___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__LNA_GAIN_EVEN_200___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__LNA_GAIN_EVEN_200___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__GM_GAIN_EVEN_200___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__GM_GAIN_EVEN_200___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__TIA_GAIN_EVEN_200___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__TIA_GAIN_EVEN_200___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__SLM_XLNA_EVEN_200___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__SLM_XLNA_EVEN_200___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__BQ_GAIN_EVEN_200___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200__BQ_GAIN_EVEN_200___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_200___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201 (0x005ED324) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__XLNA_GAIN_ODD_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__LNA_GAIN_ODD_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__GM_GAIN_ODD_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__TIA_GAIN_ODD_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__SLM_XLNA_ODD_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__BQ_GAIN_ODD_201___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__XLNA_GAIN_EVEN_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__LNA_GAIN_EVEN_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__GM_GAIN_EVEN_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__TIA_GAIN_EVEN_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__SLM_XLNA_EVEN_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__BQ_GAIN_EVEN_201___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__XLNA_GAIN_ODD_201___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__XLNA_GAIN_ODD_201___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__LNA_GAIN_ODD_201___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__LNA_GAIN_ODD_201___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__GM_GAIN_ODD_201___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__GM_GAIN_ODD_201___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__TIA_GAIN_ODD_201___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__TIA_GAIN_ODD_201___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__SLM_XLNA_ODD_201___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__SLM_XLNA_ODD_201___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__BQ_GAIN_ODD_201___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__BQ_GAIN_ODD_201___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__XLNA_GAIN_EVEN_201___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__XLNA_GAIN_EVEN_201___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__LNA_GAIN_EVEN_201___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__LNA_GAIN_EVEN_201___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__GM_GAIN_EVEN_201___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__GM_GAIN_EVEN_201___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__TIA_GAIN_EVEN_201___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__TIA_GAIN_EVEN_201___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__SLM_XLNA_EVEN_201___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__SLM_XLNA_EVEN_201___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__BQ_GAIN_EVEN_201___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201__BQ_GAIN_EVEN_201___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_201___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202 (0x005ED328) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__XLNA_GAIN_ODD_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__LNA_GAIN_ODD_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__GM_GAIN_ODD_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__TIA_GAIN_ODD_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__SLM_XLNA_ODD_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__BQ_GAIN_ODD_202___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__XLNA_GAIN_EVEN_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__LNA_GAIN_EVEN_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__GM_GAIN_EVEN_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__TIA_GAIN_EVEN_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__SLM_XLNA_EVEN_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__BQ_GAIN_EVEN_202___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__XLNA_GAIN_ODD_202___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__XLNA_GAIN_ODD_202___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__LNA_GAIN_ODD_202___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__LNA_GAIN_ODD_202___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__GM_GAIN_ODD_202___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__GM_GAIN_ODD_202___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__TIA_GAIN_ODD_202___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__TIA_GAIN_ODD_202___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__SLM_XLNA_ODD_202___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__SLM_XLNA_ODD_202___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__BQ_GAIN_ODD_202___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__BQ_GAIN_ODD_202___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__XLNA_GAIN_EVEN_202___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__XLNA_GAIN_EVEN_202___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__LNA_GAIN_EVEN_202___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__LNA_GAIN_EVEN_202___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__GM_GAIN_EVEN_202___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__GM_GAIN_EVEN_202___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__TIA_GAIN_EVEN_202___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__TIA_GAIN_EVEN_202___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__SLM_XLNA_EVEN_202___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__SLM_XLNA_EVEN_202___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__BQ_GAIN_EVEN_202___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202__BQ_GAIN_EVEN_202___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_202___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203 (0x005ED32C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__XLNA_GAIN_ODD_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__LNA_GAIN_ODD_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__GM_GAIN_ODD_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__TIA_GAIN_ODD_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__SLM_XLNA_ODD_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__BQ_GAIN_ODD_203___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__XLNA_GAIN_EVEN_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__LNA_GAIN_EVEN_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__GM_GAIN_EVEN_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__TIA_GAIN_EVEN_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__SLM_XLNA_EVEN_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__BQ_GAIN_EVEN_203___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__XLNA_GAIN_ODD_203___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__XLNA_GAIN_ODD_203___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__LNA_GAIN_ODD_203___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__LNA_GAIN_ODD_203___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__GM_GAIN_ODD_203___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__GM_GAIN_ODD_203___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__TIA_GAIN_ODD_203___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__TIA_GAIN_ODD_203___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__SLM_XLNA_ODD_203___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__SLM_XLNA_ODD_203___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__BQ_GAIN_ODD_203___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__BQ_GAIN_ODD_203___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__XLNA_GAIN_EVEN_203___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__XLNA_GAIN_EVEN_203___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__LNA_GAIN_EVEN_203___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__LNA_GAIN_EVEN_203___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__GM_GAIN_EVEN_203___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__GM_GAIN_EVEN_203___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__TIA_GAIN_EVEN_203___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__TIA_GAIN_EVEN_203___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__SLM_XLNA_EVEN_203___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__SLM_XLNA_EVEN_203___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__BQ_GAIN_EVEN_203___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203__BQ_GAIN_EVEN_203___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_203___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204 (0x005ED330) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__XLNA_GAIN_ODD_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__LNA_GAIN_ODD_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__GM_GAIN_ODD_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__TIA_GAIN_ODD_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__SLM_XLNA_ODD_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__BQ_GAIN_ODD_204___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__XLNA_GAIN_EVEN_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__LNA_GAIN_EVEN_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__GM_GAIN_EVEN_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__TIA_GAIN_EVEN_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__SLM_XLNA_EVEN_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__BQ_GAIN_EVEN_204___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__XLNA_GAIN_ODD_204___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__XLNA_GAIN_ODD_204___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__LNA_GAIN_ODD_204___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__LNA_GAIN_ODD_204___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__GM_GAIN_ODD_204___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__GM_GAIN_ODD_204___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__TIA_GAIN_ODD_204___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__TIA_GAIN_ODD_204___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__SLM_XLNA_ODD_204___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__SLM_XLNA_ODD_204___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__BQ_GAIN_ODD_204___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__BQ_GAIN_ODD_204___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__XLNA_GAIN_EVEN_204___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__XLNA_GAIN_EVEN_204___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__LNA_GAIN_EVEN_204___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__LNA_GAIN_EVEN_204___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__GM_GAIN_EVEN_204___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__GM_GAIN_EVEN_204___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__TIA_GAIN_EVEN_204___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__TIA_GAIN_EVEN_204___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__SLM_XLNA_EVEN_204___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__SLM_XLNA_EVEN_204___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__BQ_GAIN_EVEN_204___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204__BQ_GAIN_EVEN_204___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_204___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205 (0x005ED334) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__XLNA_GAIN_ODD_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__LNA_GAIN_ODD_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__GM_GAIN_ODD_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__TIA_GAIN_ODD_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__SLM_XLNA_ODD_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__BQ_GAIN_ODD_205___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__XLNA_GAIN_EVEN_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__LNA_GAIN_EVEN_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__GM_GAIN_EVEN_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__TIA_GAIN_EVEN_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__SLM_XLNA_EVEN_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__BQ_GAIN_EVEN_205___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__XLNA_GAIN_ODD_205___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__XLNA_GAIN_ODD_205___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__LNA_GAIN_ODD_205___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__LNA_GAIN_ODD_205___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__GM_GAIN_ODD_205___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__GM_GAIN_ODD_205___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__TIA_GAIN_ODD_205___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__TIA_GAIN_ODD_205___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__SLM_XLNA_ODD_205___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__SLM_XLNA_ODD_205___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__BQ_GAIN_ODD_205___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__BQ_GAIN_ODD_205___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__XLNA_GAIN_EVEN_205___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__XLNA_GAIN_EVEN_205___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__LNA_GAIN_EVEN_205___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__LNA_GAIN_EVEN_205___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__GM_GAIN_EVEN_205___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__GM_GAIN_EVEN_205___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__TIA_GAIN_EVEN_205___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__TIA_GAIN_EVEN_205___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__SLM_XLNA_EVEN_205___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__SLM_XLNA_EVEN_205___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__BQ_GAIN_EVEN_205___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205__BQ_GAIN_EVEN_205___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_205___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206 (0x005ED338) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__XLNA_GAIN_ODD_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__LNA_GAIN_ODD_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__GM_GAIN_ODD_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__TIA_GAIN_ODD_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__SLM_XLNA_ODD_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__BQ_GAIN_ODD_206___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__XLNA_GAIN_EVEN_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__LNA_GAIN_EVEN_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__GM_GAIN_EVEN_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__TIA_GAIN_EVEN_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__SLM_XLNA_EVEN_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__BQ_GAIN_EVEN_206___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__XLNA_GAIN_ODD_206___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__XLNA_GAIN_ODD_206___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__LNA_GAIN_ODD_206___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__LNA_GAIN_ODD_206___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__GM_GAIN_ODD_206___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__GM_GAIN_ODD_206___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__TIA_GAIN_ODD_206___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__TIA_GAIN_ODD_206___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__SLM_XLNA_ODD_206___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__SLM_XLNA_ODD_206___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__BQ_GAIN_ODD_206___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__BQ_GAIN_ODD_206___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__XLNA_GAIN_EVEN_206___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__XLNA_GAIN_EVEN_206___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__LNA_GAIN_EVEN_206___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__LNA_GAIN_EVEN_206___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__GM_GAIN_EVEN_206___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__GM_GAIN_EVEN_206___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__TIA_GAIN_EVEN_206___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__TIA_GAIN_EVEN_206___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__SLM_XLNA_EVEN_206___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__SLM_XLNA_EVEN_206___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__BQ_GAIN_EVEN_206___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206__BQ_GAIN_EVEN_206___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_206___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207 (0x005ED33C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__XLNA_GAIN_ODD_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__LNA_GAIN_ODD_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__GM_GAIN_ODD_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__TIA_GAIN_ODD_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__SLM_XLNA_ODD_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__BQ_GAIN_ODD_207___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__XLNA_GAIN_EVEN_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__LNA_GAIN_EVEN_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__GM_GAIN_EVEN_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__TIA_GAIN_EVEN_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__SLM_XLNA_EVEN_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__BQ_GAIN_EVEN_207___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__XLNA_GAIN_ODD_207___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__XLNA_GAIN_ODD_207___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__LNA_GAIN_ODD_207___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__LNA_GAIN_ODD_207___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__GM_GAIN_ODD_207___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__GM_GAIN_ODD_207___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__TIA_GAIN_ODD_207___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__TIA_GAIN_ODD_207___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__SLM_XLNA_ODD_207___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__SLM_XLNA_ODD_207___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__BQ_GAIN_ODD_207___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__BQ_GAIN_ODD_207___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__XLNA_GAIN_EVEN_207___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__XLNA_GAIN_EVEN_207___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__LNA_GAIN_EVEN_207___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__LNA_GAIN_EVEN_207___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__GM_GAIN_EVEN_207___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__GM_GAIN_EVEN_207___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__TIA_GAIN_EVEN_207___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__TIA_GAIN_EVEN_207___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__SLM_XLNA_EVEN_207___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__SLM_XLNA_EVEN_207___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__BQ_GAIN_EVEN_207___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207__BQ_GAIN_EVEN_207___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_207___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208 (0x005ED340) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__XLNA_GAIN_ODD_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__LNA_GAIN_ODD_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__GM_GAIN_ODD_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__TIA_GAIN_ODD_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__SLM_XLNA_ODD_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__BQ_GAIN_ODD_208___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__XLNA_GAIN_EVEN_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__LNA_GAIN_EVEN_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__GM_GAIN_EVEN_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__TIA_GAIN_EVEN_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__SLM_XLNA_EVEN_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__BQ_GAIN_EVEN_208___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__XLNA_GAIN_ODD_208___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__XLNA_GAIN_ODD_208___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__LNA_GAIN_ODD_208___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__LNA_GAIN_ODD_208___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__GM_GAIN_ODD_208___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__GM_GAIN_ODD_208___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__TIA_GAIN_ODD_208___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__TIA_GAIN_ODD_208___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__SLM_XLNA_ODD_208___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__SLM_XLNA_ODD_208___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__BQ_GAIN_ODD_208___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__BQ_GAIN_ODD_208___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__XLNA_GAIN_EVEN_208___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__XLNA_GAIN_EVEN_208___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__LNA_GAIN_EVEN_208___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__LNA_GAIN_EVEN_208___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__GM_GAIN_EVEN_208___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__GM_GAIN_EVEN_208___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__TIA_GAIN_EVEN_208___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__TIA_GAIN_EVEN_208___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__SLM_XLNA_EVEN_208___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__SLM_XLNA_EVEN_208___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__BQ_GAIN_EVEN_208___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208__BQ_GAIN_EVEN_208___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_208___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209 (0x005ED344) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__XLNA_GAIN_ODD_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__LNA_GAIN_ODD_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__GM_GAIN_ODD_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__TIA_GAIN_ODD_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__SLM_XLNA_ODD_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__BQ_GAIN_ODD_209___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__XLNA_GAIN_EVEN_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__LNA_GAIN_EVEN_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__GM_GAIN_EVEN_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__TIA_GAIN_EVEN_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__SLM_XLNA_EVEN_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__BQ_GAIN_EVEN_209___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__XLNA_GAIN_ODD_209___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__XLNA_GAIN_ODD_209___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__LNA_GAIN_ODD_209___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__LNA_GAIN_ODD_209___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__GM_GAIN_ODD_209___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__GM_GAIN_ODD_209___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__TIA_GAIN_ODD_209___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__TIA_GAIN_ODD_209___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__SLM_XLNA_ODD_209___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__SLM_XLNA_ODD_209___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__BQ_GAIN_ODD_209___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__BQ_GAIN_ODD_209___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__XLNA_GAIN_EVEN_209___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__XLNA_GAIN_EVEN_209___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__LNA_GAIN_EVEN_209___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__LNA_GAIN_EVEN_209___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__GM_GAIN_EVEN_209___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__GM_GAIN_EVEN_209___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__TIA_GAIN_EVEN_209___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__TIA_GAIN_EVEN_209___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__SLM_XLNA_EVEN_209___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__SLM_XLNA_EVEN_209___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__BQ_GAIN_EVEN_209___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209__BQ_GAIN_EVEN_209___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_209___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210 (0x005ED348) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__XLNA_GAIN_ODD_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__LNA_GAIN_ODD_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__GM_GAIN_ODD_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__TIA_GAIN_ODD_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__SLM_XLNA_ODD_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__BQ_GAIN_ODD_210___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__XLNA_GAIN_EVEN_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__LNA_GAIN_EVEN_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__GM_GAIN_EVEN_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__TIA_GAIN_EVEN_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__SLM_XLNA_EVEN_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__BQ_GAIN_EVEN_210___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__XLNA_GAIN_ODD_210___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__XLNA_GAIN_ODD_210___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__LNA_GAIN_ODD_210___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__LNA_GAIN_ODD_210___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__GM_GAIN_ODD_210___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__GM_GAIN_ODD_210___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__TIA_GAIN_ODD_210___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__TIA_GAIN_ODD_210___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__SLM_XLNA_ODD_210___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__SLM_XLNA_ODD_210___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__BQ_GAIN_ODD_210___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__BQ_GAIN_ODD_210___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__XLNA_GAIN_EVEN_210___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__XLNA_GAIN_EVEN_210___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__LNA_GAIN_EVEN_210___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__LNA_GAIN_EVEN_210___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__GM_GAIN_EVEN_210___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__GM_GAIN_EVEN_210___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__TIA_GAIN_EVEN_210___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__TIA_GAIN_EVEN_210___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__SLM_XLNA_EVEN_210___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__SLM_XLNA_EVEN_210___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__BQ_GAIN_EVEN_210___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210__BQ_GAIN_EVEN_210___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_210___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211 (0x005ED34C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__XLNA_GAIN_ODD_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__LNA_GAIN_ODD_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__GM_GAIN_ODD_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__TIA_GAIN_ODD_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__SLM_XLNA_ODD_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__BQ_GAIN_ODD_211___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__XLNA_GAIN_EVEN_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__LNA_GAIN_EVEN_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__GM_GAIN_EVEN_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__TIA_GAIN_EVEN_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__SLM_XLNA_EVEN_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__BQ_GAIN_EVEN_211___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__XLNA_GAIN_ODD_211___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__XLNA_GAIN_ODD_211___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__LNA_GAIN_ODD_211___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__LNA_GAIN_ODD_211___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__GM_GAIN_ODD_211___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__GM_GAIN_ODD_211___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__TIA_GAIN_ODD_211___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__TIA_GAIN_ODD_211___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__SLM_XLNA_ODD_211___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__SLM_XLNA_ODD_211___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__BQ_GAIN_ODD_211___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__BQ_GAIN_ODD_211___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__XLNA_GAIN_EVEN_211___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__XLNA_GAIN_EVEN_211___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__LNA_GAIN_EVEN_211___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__LNA_GAIN_EVEN_211___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__GM_GAIN_EVEN_211___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__GM_GAIN_EVEN_211___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__TIA_GAIN_EVEN_211___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__TIA_GAIN_EVEN_211___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__SLM_XLNA_EVEN_211___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__SLM_XLNA_EVEN_211___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__BQ_GAIN_EVEN_211___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211__BQ_GAIN_EVEN_211___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_211___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212 (0x005ED350) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__XLNA_GAIN_ODD_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__LNA_GAIN_ODD_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__GM_GAIN_ODD_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__TIA_GAIN_ODD_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__SLM_XLNA_ODD_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__BQ_GAIN_ODD_212___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__XLNA_GAIN_EVEN_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__LNA_GAIN_EVEN_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__GM_GAIN_EVEN_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__TIA_GAIN_EVEN_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__SLM_XLNA_EVEN_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__BQ_GAIN_EVEN_212___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__XLNA_GAIN_ODD_212___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__XLNA_GAIN_ODD_212___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__LNA_GAIN_ODD_212___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__LNA_GAIN_ODD_212___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__GM_GAIN_ODD_212___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__GM_GAIN_ODD_212___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__TIA_GAIN_ODD_212___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__TIA_GAIN_ODD_212___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__SLM_XLNA_ODD_212___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__SLM_XLNA_ODD_212___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__BQ_GAIN_ODD_212___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__BQ_GAIN_ODD_212___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__XLNA_GAIN_EVEN_212___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__XLNA_GAIN_EVEN_212___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__LNA_GAIN_EVEN_212___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__LNA_GAIN_EVEN_212___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__GM_GAIN_EVEN_212___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__GM_GAIN_EVEN_212___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__TIA_GAIN_EVEN_212___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__TIA_GAIN_EVEN_212___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__SLM_XLNA_EVEN_212___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__SLM_XLNA_EVEN_212___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__BQ_GAIN_EVEN_212___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212__BQ_GAIN_EVEN_212___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_212___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213 (0x005ED354) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__XLNA_GAIN_ODD_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__LNA_GAIN_ODD_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__GM_GAIN_ODD_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__TIA_GAIN_ODD_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__SLM_XLNA_ODD_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__BQ_GAIN_ODD_213___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__XLNA_GAIN_EVEN_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__LNA_GAIN_EVEN_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__GM_GAIN_EVEN_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__TIA_GAIN_EVEN_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__SLM_XLNA_EVEN_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__BQ_GAIN_EVEN_213___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__XLNA_GAIN_ODD_213___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__XLNA_GAIN_ODD_213___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__LNA_GAIN_ODD_213___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__LNA_GAIN_ODD_213___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__GM_GAIN_ODD_213___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__GM_GAIN_ODD_213___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__TIA_GAIN_ODD_213___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__TIA_GAIN_ODD_213___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__SLM_XLNA_ODD_213___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__SLM_XLNA_ODD_213___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__BQ_GAIN_ODD_213___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__BQ_GAIN_ODD_213___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__XLNA_GAIN_EVEN_213___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__XLNA_GAIN_EVEN_213___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__LNA_GAIN_EVEN_213___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__LNA_GAIN_EVEN_213___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__GM_GAIN_EVEN_213___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__GM_GAIN_EVEN_213___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__TIA_GAIN_EVEN_213___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__TIA_GAIN_EVEN_213___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__SLM_XLNA_EVEN_213___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__SLM_XLNA_EVEN_213___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__BQ_GAIN_EVEN_213___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213__BQ_GAIN_EVEN_213___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_213___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214 (0x005ED358) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__XLNA_GAIN_ODD_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__LNA_GAIN_ODD_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__GM_GAIN_ODD_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__TIA_GAIN_ODD_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__SLM_XLNA_ODD_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__BQ_GAIN_ODD_214___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__XLNA_GAIN_EVEN_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__LNA_GAIN_EVEN_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__GM_GAIN_EVEN_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__TIA_GAIN_EVEN_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__SLM_XLNA_EVEN_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__BQ_GAIN_EVEN_214___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__XLNA_GAIN_ODD_214___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__XLNA_GAIN_ODD_214___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__LNA_GAIN_ODD_214___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__LNA_GAIN_ODD_214___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__GM_GAIN_ODD_214___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__GM_GAIN_ODD_214___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__TIA_GAIN_ODD_214___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__TIA_GAIN_ODD_214___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__SLM_XLNA_ODD_214___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__SLM_XLNA_ODD_214___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__BQ_GAIN_ODD_214___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__BQ_GAIN_ODD_214___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__XLNA_GAIN_EVEN_214___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__XLNA_GAIN_EVEN_214___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__LNA_GAIN_EVEN_214___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__LNA_GAIN_EVEN_214___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__GM_GAIN_EVEN_214___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__GM_GAIN_EVEN_214___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__TIA_GAIN_EVEN_214___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__TIA_GAIN_EVEN_214___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__SLM_XLNA_EVEN_214___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__SLM_XLNA_EVEN_214___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__BQ_GAIN_EVEN_214___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214__BQ_GAIN_EVEN_214___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_214___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215 (0x005ED35C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__XLNA_GAIN_ODD_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__LNA_GAIN_ODD_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__GM_GAIN_ODD_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__TIA_GAIN_ODD_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__SLM_XLNA_ODD_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__BQ_GAIN_ODD_215___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__XLNA_GAIN_EVEN_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__LNA_GAIN_EVEN_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__GM_GAIN_EVEN_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__TIA_GAIN_EVEN_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__SLM_XLNA_EVEN_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__BQ_GAIN_EVEN_215___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__XLNA_GAIN_ODD_215___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__XLNA_GAIN_ODD_215___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__LNA_GAIN_ODD_215___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__LNA_GAIN_ODD_215___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__GM_GAIN_ODD_215___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__GM_GAIN_ODD_215___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__TIA_GAIN_ODD_215___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__TIA_GAIN_ODD_215___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__SLM_XLNA_ODD_215___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__SLM_XLNA_ODD_215___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__BQ_GAIN_ODD_215___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__BQ_GAIN_ODD_215___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__XLNA_GAIN_EVEN_215___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__XLNA_GAIN_EVEN_215___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__LNA_GAIN_EVEN_215___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__LNA_GAIN_EVEN_215___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__GM_GAIN_EVEN_215___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__GM_GAIN_EVEN_215___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__TIA_GAIN_EVEN_215___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__TIA_GAIN_EVEN_215___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__SLM_XLNA_EVEN_215___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__SLM_XLNA_EVEN_215___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__BQ_GAIN_EVEN_215___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215__BQ_GAIN_EVEN_215___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_215___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216 (0x005ED360) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__XLNA_GAIN_ODD_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__LNA_GAIN_ODD_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__GM_GAIN_ODD_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__TIA_GAIN_ODD_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__SLM_XLNA_ODD_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__BQ_GAIN_ODD_216___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__XLNA_GAIN_EVEN_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__LNA_GAIN_EVEN_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__GM_GAIN_EVEN_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__TIA_GAIN_EVEN_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__SLM_XLNA_EVEN_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__BQ_GAIN_EVEN_216___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__XLNA_GAIN_ODD_216___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__XLNA_GAIN_ODD_216___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__LNA_GAIN_ODD_216___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__LNA_GAIN_ODD_216___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__GM_GAIN_ODD_216___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__GM_GAIN_ODD_216___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__TIA_GAIN_ODD_216___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__TIA_GAIN_ODD_216___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__SLM_XLNA_ODD_216___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__SLM_XLNA_ODD_216___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__BQ_GAIN_ODD_216___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__BQ_GAIN_ODD_216___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__XLNA_GAIN_EVEN_216___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__XLNA_GAIN_EVEN_216___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__LNA_GAIN_EVEN_216___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__LNA_GAIN_EVEN_216___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__GM_GAIN_EVEN_216___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__GM_GAIN_EVEN_216___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__TIA_GAIN_EVEN_216___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__TIA_GAIN_EVEN_216___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__SLM_XLNA_EVEN_216___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__SLM_XLNA_EVEN_216___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__BQ_GAIN_EVEN_216___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216__BQ_GAIN_EVEN_216___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_216___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217 (0x005ED364) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__XLNA_GAIN_ODD_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__LNA_GAIN_ODD_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__GM_GAIN_ODD_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__TIA_GAIN_ODD_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__SLM_XLNA_ODD_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__BQ_GAIN_ODD_217___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__XLNA_GAIN_EVEN_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__LNA_GAIN_EVEN_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__GM_GAIN_EVEN_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__TIA_GAIN_EVEN_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__SLM_XLNA_EVEN_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__BQ_GAIN_EVEN_217___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__XLNA_GAIN_ODD_217___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__XLNA_GAIN_ODD_217___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__LNA_GAIN_ODD_217___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__LNA_GAIN_ODD_217___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__GM_GAIN_ODD_217___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__GM_GAIN_ODD_217___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__TIA_GAIN_ODD_217___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__TIA_GAIN_ODD_217___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__SLM_XLNA_ODD_217___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__SLM_XLNA_ODD_217___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__BQ_GAIN_ODD_217___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__BQ_GAIN_ODD_217___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__XLNA_GAIN_EVEN_217___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__XLNA_GAIN_EVEN_217___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__LNA_GAIN_EVEN_217___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__LNA_GAIN_EVEN_217___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__GM_GAIN_EVEN_217___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__GM_GAIN_EVEN_217___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__TIA_GAIN_EVEN_217___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__TIA_GAIN_EVEN_217___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__SLM_XLNA_EVEN_217___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__SLM_XLNA_EVEN_217___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__BQ_GAIN_EVEN_217___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217__BQ_GAIN_EVEN_217___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_217___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218 (0x005ED368) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__XLNA_GAIN_ODD_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__LNA_GAIN_ODD_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__GM_GAIN_ODD_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__TIA_GAIN_ODD_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__SLM_XLNA_ODD_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__BQ_GAIN_ODD_218___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__XLNA_GAIN_EVEN_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__LNA_GAIN_EVEN_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__GM_GAIN_EVEN_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__TIA_GAIN_EVEN_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__SLM_XLNA_EVEN_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__BQ_GAIN_EVEN_218___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__XLNA_GAIN_ODD_218___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__XLNA_GAIN_ODD_218___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__LNA_GAIN_ODD_218___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__LNA_GAIN_ODD_218___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__GM_GAIN_ODD_218___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__GM_GAIN_ODD_218___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__TIA_GAIN_ODD_218___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__TIA_GAIN_ODD_218___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__SLM_XLNA_ODD_218___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__SLM_XLNA_ODD_218___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__BQ_GAIN_ODD_218___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__BQ_GAIN_ODD_218___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__XLNA_GAIN_EVEN_218___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__XLNA_GAIN_EVEN_218___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__LNA_GAIN_EVEN_218___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__LNA_GAIN_EVEN_218___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__GM_GAIN_EVEN_218___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__GM_GAIN_EVEN_218___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__TIA_GAIN_EVEN_218___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__TIA_GAIN_EVEN_218___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__SLM_XLNA_EVEN_218___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__SLM_XLNA_EVEN_218___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__BQ_GAIN_EVEN_218___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218__BQ_GAIN_EVEN_218___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_218___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219 (0x005ED36C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__XLNA_GAIN_ODD_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__LNA_GAIN_ODD_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__GM_GAIN_ODD_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__TIA_GAIN_ODD_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__SLM_XLNA_ODD_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__BQ_GAIN_ODD_219___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__XLNA_GAIN_EVEN_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__LNA_GAIN_EVEN_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__GM_GAIN_EVEN_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__TIA_GAIN_EVEN_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__SLM_XLNA_EVEN_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__BQ_GAIN_EVEN_219___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__XLNA_GAIN_ODD_219___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__XLNA_GAIN_ODD_219___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__LNA_GAIN_ODD_219___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__LNA_GAIN_ODD_219___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__GM_GAIN_ODD_219___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__GM_GAIN_ODD_219___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__TIA_GAIN_ODD_219___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__TIA_GAIN_ODD_219___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__SLM_XLNA_ODD_219___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__SLM_XLNA_ODD_219___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__BQ_GAIN_ODD_219___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__BQ_GAIN_ODD_219___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__XLNA_GAIN_EVEN_219___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__XLNA_GAIN_EVEN_219___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__LNA_GAIN_EVEN_219___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__LNA_GAIN_EVEN_219___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__GM_GAIN_EVEN_219___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__GM_GAIN_EVEN_219___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__TIA_GAIN_EVEN_219___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__TIA_GAIN_EVEN_219___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__SLM_XLNA_EVEN_219___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__SLM_XLNA_EVEN_219___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__BQ_GAIN_EVEN_219___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219__BQ_GAIN_EVEN_219___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_219___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220 (0x005ED370) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__XLNA_GAIN_ODD_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__LNA_GAIN_ODD_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__GM_GAIN_ODD_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__TIA_GAIN_ODD_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__SLM_XLNA_ODD_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__BQ_GAIN_ODD_220___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__XLNA_GAIN_EVEN_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__LNA_GAIN_EVEN_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__GM_GAIN_EVEN_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__TIA_GAIN_EVEN_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__SLM_XLNA_EVEN_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__BQ_GAIN_EVEN_220___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__XLNA_GAIN_ODD_220___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__XLNA_GAIN_ODD_220___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__LNA_GAIN_ODD_220___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__LNA_GAIN_ODD_220___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__GM_GAIN_ODD_220___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__GM_GAIN_ODD_220___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__TIA_GAIN_ODD_220___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__TIA_GAIN_ODD_220___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__SLM_XLNA_ODD_220___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__SLM_XLNA_ODD_220___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__BQ_GAIN_ODD_220___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__BQ_GAIN_ODD_220___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__XLNA_GAIN_EVEN_220___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__XLNA_GAIN_EVEN_220___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__LNA_GAIN_EVEN_220___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__LNA_GAIN_EVEN_220___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__GM_GAIN_EVEN_220___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__GM_GAIN_EVEN_220___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__TIA_GAIN_EVEN_220___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__TIA_GAIN_EVEN_220___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__SLM_XLNA_EVEN_220___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__SLM_XLNA_EVEN_220___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__BQ_GAIN_EVEN_220___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220__BQ_GAIN_EVEN_220___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_220___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221 (0x005ED374) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__XLNA_GAIN_ODD_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__LNA_GAIN_ODD_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__GM_GAIN_ODD_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__TIA_GAIN_ODD_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__SLM_XLNA_ODD_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__BQ_GAIN_ODD_221___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__XLNA_GAIN_EVEN_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__LNA_GAIN_EVEN_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__GM_GAIN_EVEN_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__TIA_GAIN_EVEN_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__SLM_XLNA_EVEN_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__BQ_GAIN_EVEN_221___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__XLNA_GAIN_ODD_221___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__XLNA_GAIN_ODD_221___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__LNA_GAIN_ODD_221___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__LNA_GAIN_ODD_221___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__GM_GAIN_ODD_221___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__GM_GAIN_ODD_221___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__TIA_GAIN_ODD_221___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__TIA_GAIN_ODD_221___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__SLM_XLNA_ODD_221___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__SLM_XLNA_ODD_221___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__BQ_GAIN_ODD_221___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__BQ_GAIN_ODD_221___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__XLNA_GAIN_EVEN_221___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__XLNA_GAIN_EVEN_221___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__LNA_GAIN_EVEN_221___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__LNA_GAIN_EVEN_221___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__GM_GAIN_EVEN_221___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__GM_GAIN_EVEN_221___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__TIA_GAIN_EVEN_221___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__TIA_GAIN_EVEN_221___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__SLM_XLNA_EVEN_221___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__SLM_XLNA_EVEN_221___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__BQ_GAIN_EVEN_221___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221__BQ_GAIN_EVEN_221___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_221___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222 (0x005ED378) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__XLNA_GAIN_ODD_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__LNA_GAIN_ODD_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__GM_GAIN_ODD_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__TIA_GAIN_ODD_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__SLM_XLNA_ODD_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__BQ_GAIN_ODD_222___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__XLNA_GAIN_EVEN_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__LNA_GAIN_EVEN_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__GM_GAIN_EVEN_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__TIA_GAIN_EVEN_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__SLM_XLNA_EVEN_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__BQ_GAIN_EVEN_222___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__XLNA_GAIN_ODD_222___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__XLNA_GAIN_ODD_222___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__LNA_GAIN_ODD_222___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__LNA_GAIN_ODD_222___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__GM_GAIN_ODD_222___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__GM_GAIN_ODD_222___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__TIA_GAIN_ODD_222___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__TIA_GAIN_ODD_222___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__SLM_XLNA_ODD_222___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__SLM_XLNA_ODD_222___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__BQ_GAIN_ODD_222___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__BQ_GAIN_ODD_222___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__XLNA_GAIN_EVEN_222___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__XLNA_GAIN_EVEN_222___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__LNA_GAIN_EVEN_222___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__LNA_GAIN_EVEN_222___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__GM_GAIN_EVEN_222___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__GM_GAIN_EVEN_222___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__TIA_GAIN_EVEN_222___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__TIA_GAIN_EVEN_222___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__SLM_XLNA_EVEN_222___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__SLM_XLNA_EVEN_222___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__BQ_GAIN_EVEN_222___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222__BQ_GAIN_EVEN_222___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_222___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223 (0x005ED37C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__XLNA_GAIN_ODD_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__LNA_GAIN_ODD_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__GM_GAIN_ODD_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__TIA_GAIN_ODD_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__SLM_XLNA_ODD_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__BQ_GAIN_ODD_223___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__XLNA_GAIN_EVEN_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__LNA_GAIN_EVEN_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__GM_GAIN_EVEN_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__TIA_GAIN_EVEN_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__SLM_XLNA_EVEN_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__BQ_GAIN_EVEN_223___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__XLNA_GAIN_ODD_223___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__XLNA_GAIN_ODD_223___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__LNA_GAIN_ODD_223___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__LNA_GAIN_ODD_223___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__GM_GAIN_ODD_223___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__GM_GAIN_ODD_223___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__TIA_GAIN_ODD_223___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__TIA_GAIN_ODD_223___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__SLM_XLNA_ODD_223___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__SLM_XLNA_ODD_223___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__BQ_GAIN_ODD_223___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__BQ_GAIN_ODD_223___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__XLNA_GAIN_EVEN_223___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__XLNA_GAIN_EVEN_223___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__LNA_GAIN_EVEN_223___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__LNA_GAIN_EVEN_223___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__GM_GAIN_EVEN_223___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__GM_GAIN_EVEN_223___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__TIA_GAIN_EVEN_223___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__TIA_GAIN_EVEN_223___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__SLM_XLNA_EVEN_223___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__SLM_XLNA_EVEN_223___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__BQ_GAIN_EVEN_223___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223__BQ_GAIN_EVEN_223___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_223___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224 (0x005ED380) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__XLNA_GAIN_ODD_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__LNA_GAIN_ODD_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__GM_GAIN_ODD_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__TIA_GAIN_ODD_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__SLM_XLNA_ODD_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__BQ_GAIN_ODD_224___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__XLNA_GAIN_EVEN_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__LNA_GAIN_EVEN_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__GM_GAIN_EVEN_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__TIA_GAIN_EVEN_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__SLM_XLNA_EVEN_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__BQ_GAIN_EVEN_224___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__XLNA_GAIN_ODD_224___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__XLNA_GAIN_ODD_224___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__LNA_GAIN_ODD_224___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__LNA_GAIN_ODD_224___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__GM_GAIN_ODD_224___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__GM_GAIN_ODD_224___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__TIA_GAIN_ODD_224___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__TIA_GAIN_ODD_224___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__SLM_XLNA_ODD_224___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__SLM_XLNA_ODD_224___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__BQ_GAIN_ODD_224___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__BQ_GAIN_ODD_224___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__XLNA_GAIN_EVEN_224___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__XLNA_GAIN_EVEN_224___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__LNA_GAIN_EVEN_224___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__LNA_GAIN_EVEN_224___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__GM_GAIN_EVEN_224___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__GM_GAIN_EVEN_224___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__TIA_GAIN_EVEN_224___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__TIA_GAIN_EVEN_224___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__SLM_XLNA_EVEN_224___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__SLM_XLNA_EVEN_224___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__BQ_GAIN_EVEN_224___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224__BQ_GAIN_EVEN_224___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_224___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225 (0x005ED384) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__XLNA_GAIN_ODD_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__LNA_GAIN_ODD_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__GM_GAIN_ODD_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__TIA_GAIN_ODD_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__SLM_XLNA_ODD_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__BQ_GAIN_ODD_225___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__XLNA_GAIN_EVEN_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__LNA_GAIN_EVEN_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__GM_GAIN_EVEN_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__TIA_GAIN_EVEN_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__SLM_XLNA_EVEN_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__BQ_GAIN_EVEN_225___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__XLNA_GAIN_ODD_225___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__XLNA_GAIN_ODD_225___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__LNA_GAIN_ODD_225___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__LNA_GAIN_ODD_225___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__GM_GAIN_ODD_225___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__GM_GAIN_ODD_225___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__TIA_GAIN_ODD_225___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__TIA_GAIN_ODD_225___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__SLM_XLNA_ODD_225___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__SLM_XLNA_ODD_225___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__BQ_GAIN_ODD_225___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__BQ_GAIN_ODD_225___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__XLNA_GAIN_EVEN_225___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__XLNA_GAIN_EVEN_225___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__LNA_GAIN_EVEN_225___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__LNA_GAIN_EVEN_225___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__GM_GAIN_EVEN_225___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__GM_GAIN_EVEN_225___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__TIA_GAIN_EVEN_225___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__TIA_GAIN_EVEN_225___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__SLM_XLNA_EVEN_225___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__SLM_XLNA_EVEN_225___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__BQ_GAIN_EVEN_225___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225__BQ_GAIN_EVEN_225___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_225___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226 (0x005ED388) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__XLNA_GAIN_ODD_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__LNA_GAIN_ODD_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__GM_GAIN_ODD_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__TIA_GAIN_ODD_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__SLM_XLNA_ODD_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__BQ_GAIN_ODD_226___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__XLNA_GAIN_EVEN_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__LNA_GAIN_EVEN_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__GM_GAIN_EVEN_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__TIA_GAIN_EVEN_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__SLM_XLNA_EVEN_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__BQ_GAIN_EVEN_226___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__XLNA_GAIN_ODD_226___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__XLNA_GAIN_ODD_226___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__LNA_GAIN_ODD_226___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__LNA_GAIN_ODD_226___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__GM_GAIN_ODD_226___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__GM_GAIN_ODD_226___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__TIA_GAIN_ODD_226___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__TIA_GAIN_ODD_226___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__SLM_XLNA_ODD_226___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__SLM_XLNA_ODD_226___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__BQ_GAIN_ODD_226___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__BQ_GAIN_ODD_226___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__XLNA_GAIN_EVEN_226___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__XLNA_GAIN_EVEN_226___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__LNA_GAIN_EVEN_226___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__LNA_GAIN_EVEN_226___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__GM_GAIN_EVEN_226___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__GM_GAIN_EVEN_226___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__TIA_GAIN_EVEN_226___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__TIA_GAIN_EVEN_226___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__SLM_XLNA_EVEN_226___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__SLM_XLNA_EVEN_226___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__BQ_GAIN_EVEN_226___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226__BQ_GAIN_EVEN_226___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_226___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227 (0x005ED38C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__XLNA_GAIN_ODD_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__LNA_GAIN_ODD_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__GM_GAIN_ODD_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__TIA_GAIN_ODD_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__SLM_XLNA_ODD_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__BQ_GAIN_ODD_227___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__XLNA_GAIN_EVEN_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__LNA_GAIN_EVEN_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__GM_GAIN_EVEN_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__TIA_GAIN_EVEN_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__SLM_XLNA_EVEN_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__BQ_GAIN_EVEN_227___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__XLNA_GAIN_ODD_227___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__XLNA_GAIN_ODD_227___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__LNA_GAIN_ODD_227___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__LNA_GAIN_ODD_227___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__GM_GAIN_ODD_227___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__GM_GAIN_ODD_227___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__TIA_GAIN_ODD_227___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__TIA_GAIN_ODD_227___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__SLM_XLNA_ODD_227___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__SLM_XLNA_ODD_227___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__BQ_GAIN_ODD_227___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__BQ_GAIN_ODD_227___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__XLNA_GAIN_EVEN_227___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__XLNA_GAIN_EVEN_227___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__LNA_GAIN_EVEN_227___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__LNA_GAIN_EVEN_227___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__GM_GAIN_EVEN_227___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__GM_GAIN_EVEN_227___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__TIA_GAIN_EVEN_227___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__TIA_GAIN_EVEN_227___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__SLM_XLNA_EVEN_227___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__SLM_XLNA_EVEN_227___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__BQ_GAIN_EVEN_227___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227__BQ_GAIN_EVEN_227___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_227___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228 (0x005ED390) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__XLNA_GAIN_ODD_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__LNA_GAIN_ODD_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__GM_GAIN_ODD_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__TIA_GAIN_ODD_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__SLM_XLNA_ODD_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__BQ_GAIN_ODD_228___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__XLNA_GAIN_EVEN_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__LNA_GAIN_EVEN_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__GM_GAIN_EVEN_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__TIA_GAIN_EVEN_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__SLM_XLNA_EVEN_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__BQ_GAIN_EVEN_228___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__XLNA_GAIN_ODD_228___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__XLNA_GAIN_ODD_228___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__LNA_GAIN_ODD_228___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__LNA_GAIN_ODD_228___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__GM_GAIN_ODD_228___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__GM_GAIN_ODD_228___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__TIA_GAIN_ODD_228___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__TIA_GAIN_ODD_228___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__SLM_XLNA_ODD_228___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__SLM_XLNA_ODD_228___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__BQ_GAIN_ODD_228___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__BQ_GAIN_ODD_228___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__XLNA_GAIN_EVEN_228___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__XLNA_GAIN_EVEN_228___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__LNA_GAIN_EVEN_228___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__LNA_GAIN_EVEN_228___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__GM_GAIN_EVEN_228___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__GM_GAIN_EVEN_228___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__TIA_GAIN_EVEN_228___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__TIA_GAIN_EVEN_228___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__SLM_XLNA_EVEN_228___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__SLM_XLNA_EVEN_228___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__BQ_GAIN_EVEN_228___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228__BQ_GAIN_EVEN_228___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_228___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229 (0x005ED394) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__XLNA_GAIN_ODD_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__LNA_GAIN_ODD_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__GM_GAIN_ODD_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__TIA_GAIN_ODD_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__SLM_XLNA_ODD_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__BQ_GAIN_ODD_229___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__XLNA_GAIN_EVEN_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__LNA_GAIN_EVEN_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__GM_GAIN_EVEN_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__TIA_GAIN_EVEN_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__SLM_XLNA_EVEN_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__BQ_GAIN_EVEN_229___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__XLNA_GAIN_ODD_229___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__XLNA_GAIN_ODD_229___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__LNA_GAIN_ODD_229___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__LNA_GAIN_ODD_229___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__GM_GAIN_ODD_229___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__GM_GAIN_ODD_229___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__TIA_GAIN_ODD_229___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__TIA_GAIN_ODD_229___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__SLM_XLNA_ODD_229___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__SLM_XLNA_ODD_229___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__BQ_GAIN_ODD_229___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__BQ_GAIN_ODD_229___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__XLNA_GAIN_EVEN_229___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__XLNA_GAIN_EVEN_229___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__LNA_GAIN_EVEN_229___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__LNA_GAIN_EVEN_229___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__GM_GAIN_EVEN_229___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__GM_GAIN_EVEN_229___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__TIA_GAIN_EVEN_229___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__TIA_GAIN_EVEN_229___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__SLM_XLNA_EVEN_229___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__SLM_XLNA_EVEN_229___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__BQ_GAIN_EVEN_229___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229__BQ_GAIN_EVEN_229___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_229___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230 (0x005ED398) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__XLNA_GAIN_ODD_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__LNA_GAIN_ODD_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__GM_GAIN_ODD_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__TIA_GAIN_ODD_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__SLM_XLNA_ODD_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__BQ_GAIN_ODD_230___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__XLNA_GAIN_EVEN_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__LNA_GAIN_EVEN_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__GM_GAIN_EVEN_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__TIA_GAIN_EVEN_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__SLM_XLNA_EVEN_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__BQ_GAIN_EVEN_230___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__XLNA_GAIN_ODD_230___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__XLNA_GAIN_ODD_230___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__LNA_GAIN_ODD_230___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__LNA_GAIN_ODD_230___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__GM_GAIN_ODD_230___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__GM_GAIN_ODD_230___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__TIA_GAIN_ODD_230___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__TIA_GAIN_ODD_230___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__SLM_XLNA_ODD_230___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__SLM_XLNA_ODD_230___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__BQ_GAIN_ODD_230___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__BQ_GAIN_ODD_230___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__XLNA_GAIN_EVEN_230___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__XLNA_GAIN_EVEN_230___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__LNA_GAIN_EVEN_230___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__LNA_GAIN_EVEN_230___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__GM_GAIN_EVEN_230___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__GM_GAIN_EVEN_230___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__TIA_GAIN_EVEN_230___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__TIA_GAIN_EVEN_230___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__SLM_XLNA_EVEN_230___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__SLM_XLNA_EVEN_230___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__BQ_GAIN_EVEN_230___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230__BQ_GAIN_EVEN_230___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_230___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231 (0x005ED39C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__XLNA_GAIN_ODD_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__LNA_GAIN_ODD_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__GM_GAIN_ODD_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__TIA_GAIN_ODD_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__SLM_XLNA_ODD_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__BQ_GAIN_ODD_231___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__XLNA_GAIN_EVEN_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__LNA_GAIN_EVEN_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__GM_GAIN_EVEN_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__TIA_GAIN_EVEN_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__SLM_XLNA_EVEN_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__BQ_GAIN_EVEN_231___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__XLNA_GAIN_ODD_231___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__XLNA_GAIN_ODD_231___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__LNA_GAIN_ODD_231___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__LNA_GAIN_ODD_231___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__GM_GAIN_ODD_231___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__GM_GAIN_ODD_231___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__TIA_GAIN_ODD_231___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__TIA_GAIN_ODD_231___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__SLM_XLNA_ODD_231___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__SLM_XLNA_ODD_231___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__BQ_GAIN_ODD_231___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__BQ_GAIN_ODD_231___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__XLNA_GAIN_EVEN_231___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__XLNA_GAIN_EVEN_231___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__LNA_GAIN_EVEN_231___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__LNA_GAIN_EVEN_231___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__GM_GAIN_EVEN_231___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__GM_GAIN_EVEN_231___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__TIA_GAIN_EVEN_231___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__TIA_GAIN_EVEN_231___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__SLM_XLNA_EVEN_231___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__SLM_XLNA_EVEN_231___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__BQ_GAIN_EVEN_231___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231__BQ_GAIN_EVEN_231___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_231___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232 (0x005ED3A0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__XLNA_GAIN_ODD_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__LNA_GAIN_ODD_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__GM_GAIN_ODD_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__TIA_GAIN_ODD_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__SLM_XLNA_ODD_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__BQ_GAIN_ODD_232___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__XLNA_GAIN_EVEN_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__LNA_GAIN_EVEN_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__GM_GAIN_EVEN_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__TIA_GAIN_EVEN_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__SLM_XLNA_EVEN_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__BQ_GAIN_EVEN_232___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__XLNA_GAIN_ODD_232___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__XLNA_GAIN_ODD_232___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__LNA_GAIN_ODD_232___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__LNA_GAIN_ODD_232___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__GM_GAIN_ODD_232___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__GM_GAIN_ODD_232___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__TIA_GAIN_ODD_232___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__TIA_GAIN_ODD_232___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__SLM_XLNA_ODD_232___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__SLM_XLNA_ODD_232___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__BQ_GAIN_ODD_232___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__BQ_GAIN_ODD_232___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__XLNA_GAIN_EVEN_232___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__XLNA_GAIN_EVEN_232___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__LNA_GAIN_EVEN_232___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__LNA_GAIN_EVEN_232___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__GM_GAIN_EVEN_232___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__GM_GAIN_EVEN_232___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__TIA_GAIN_EVEN_232___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__TIA_GAIN_EVEN_232___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__SLM_XLNA_EVEN_232___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__SLM_XLNA_EVEN_232___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__BQ_GAIN_EVEN_232___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232__BQ_GAIN_EVEN_232___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_232___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233 (0x005ED3A4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__XLNA_GAIN_ODD_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__LNA_GAIN_ODD_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__GM_GAIN_ODD_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__TIA_GAIN_ODD_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__SLM_XLNA_ODD_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__BQ_GAIN_ODD_233___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__XLNA_GAIN_EVEN_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__LNA_GAIN_EVEN_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__GM_GAIN_EVEN_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__TIA_GAIN_EVEN_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__SLM_XLNA_EVEN_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__BQ_GAIN_EVEN_233___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__XLNA_GAIN_ODD_233___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__XLNA_GAIN_ODD_233___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__LNA_GAIN_ODD_233___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__LNA_GAIN_ODD_233___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__GM_GAIN_ODD_233___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__GM_GAIN_ODD_233___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__TIA_GAIN_ODD_233___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__TIA_GAIN_ODD_233___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__SLM_XLNA_ODD_233___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__SLM_XLNA_ODD_233___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__BQ_GAIN_ODD_233___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__BQ_GAIN_ODD_233___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__XLNA_GAIN_EVEN_233___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__XLNA_GAIN_EVEN_233___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__LNA_GAIN_EVEN_233___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__LNA_GAIN_EVEN_233___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__GM_GAIN_EVEN_233___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__GM_GAIN_EVEN_233___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__TIA_GAIN_EVEN_233___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__TIA_GAIN_EVEN_233___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__SLM_XLNA_EVEN_233___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__SLM_XLNA_EVEN_233___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__BQ_GAIN_EVEN_233___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233__BQ_GAIN_EVEN_233___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_233___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234 (0x005ED3A8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__XLNA_GAIN_ODD_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__LNA_GAIN_ODD_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__GM_GAIN_ODD_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__TIA_GAIN_ODD_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__SLM_XLNA_ODD_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__BQ_GAIN_ODD_234___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__XLNA_GAIN_EVEN_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__LNA_GAIN_EVEN_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__GM_GAIN_EVEN_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__TIA_GAIN_EVEN_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__SLM_XLNA_EVEN_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__BQ_GAIN_EVEN_234___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__XLNA_GAIN_ODD_234___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__XLNA_GAIN_ODD_234___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__LNA_GAIN_ODD_234___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__LNA_GAIN_ODD_234___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__GM_GAIN_ODD_234___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__GM_GAIN_ODD_234___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__TIA_GAIN_ODD_234___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__TIA_GAIN_ODD_234___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__SLM_XLNA_ODD_234___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__SLM_XLNA_ODD_234___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__BQ_GAIN_ODD_234___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__BQ_GAIN_ODD_234___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__XLNA_GAIN_EVEN_234___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__XLNA_GAIN_EVEN_234___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__LNA_GAIN_EVEN_234___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__LNA_GAIN_EVEN_234___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__GM_GAIN_EVEN_234___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__GM_GAIN_EVEN_234___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__TIA_GAIN_EVEN_234___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__TIA_GAIN_EVEN_234___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__SLM_XLNA_EVEN_234___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__SLM_XLNA_EVEN_234___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__BQ_GAIN_EVEN_234___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234__BQ_GAIN_EVEN_234___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_234___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235 (0x005ED3AC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__XLNA_GAIN_ODD_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__LNA_GAIN_ODD_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__GM_GAIN_ODD_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__TIA_GAIN_ODD_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__SLM_XLNA_ODD_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__BQ_GAIN_ODD_235___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__XLNA_GAIN_EVEN_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__LNA_GAIN_EVEN_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__GM_GAIN_EVEN_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__TIA_GAIN_EVEN_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__SLM_XLNA_EVEN_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__BQ_GAIN_EVEN_235___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__XLNA_GAIN_ODD_235___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__XLNA_GAIN_ODD_235___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__LNA_GAIN_ODD_235___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__LNA_GAIN_ODD_235___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__GM_GAIN_ODD_235___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__GM_GAIN_ODD_235___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__TIA_GAIN_ODD_235___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__TIA_GAIN_ODD_235___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__SLM_XLNA_ODD_235___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__SLM_XLNA_ODD_235___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__BQ_GAIN_ODD_235___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__BQ_GAIN_ODD_235___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__XLNA_GAIN_EVEN_235___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__XLNA_GAIN_EVEN_235___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__LNA_GAIN_EVEN_235___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__LNA_GAIN_EVEN_235___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__GM_GAIN_EVEN_235___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__GM_GAIN_EVEN_235___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__TIA_GAIN_EVEN_235___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__TIA_GAIN_EVEN_235___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__SLM_XLNA_EVEN_235___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__SLM_XLNA_EVEN_235___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__BQ_GAIN_EVEN_235___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235__BQ_GAIN_EVEN_235___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_235___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236 (0x005ED3B0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__XLNA_GAIN_ODD_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__LNA_GAIN_ODD_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__GM_GAIN_ODD_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__TIA_GAIN_ODD_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__SLM_XLNA_ODD_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__BQ_GAIN_ODD_236___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__XLNA_GAIN_EVEN_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__LNA_GAIN_EVEN_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__GM_GAIN_EVEN_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__TIA_GAIN_EVEN_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__SLM_XLNA_EVEN_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__BQ_GAIN_EVEN_236___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__XLNA_GAIN_ODD_236___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__XLNA_GAIN_ODD_236___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__LNA_GAIN_ODD_236___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__LNA_GAIN_ODD_236___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__GM_GAIN_ODD_236___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__GM_GAIN_ODD_236___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__TIA_GAIN_ODD_236___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__TIA_GAIN_ODD_236___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__SLM_XLNA_ODD_236___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__SLM_XLNA_ODD_236___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__BQ_GAIN_ODD_236___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__BQ_GAIN_ODD_236___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__XLNA_GAIN_EVEN_236___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__XLNA_GAIN_EVEN_236___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__LNA_GAIN_EVEN_236___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__LNA_GAIN_EVEN_236___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__GM_GAIN_EVEN_236___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__GM_GAIN_EVEN_236___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__TIA_GAIN_EVEN_236___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__TIA_GAIN_EVEN_236___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__SLM_XLNA_EVEN_236___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__SLM_XLNA_EVEN_236___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__BQ_GAIN_EVEN_236___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236__BQ_GAIN_EVEN_236___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_236___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237 (0x005ED3B4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__XLNA_GAIN_ODD_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__LNA_GAIN_ODD_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__GM_GAIN_ODD_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__TIA_GAIN_ODD_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__SLM_XLNA_ODD_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__BQ_GAIN_ODD_237___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__XLNA_GAIN_EVEN_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__LNA_GAIN_EVEN_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__GM_GAIN_EVEN_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__TIA_GAIN_EVEN_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__SLM_XLNA_EVEN_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__BQ_GAIN_EVEN_237___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__XLNA_GAIN_ODD_237___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__XLNA_GAIN_ODD_237___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__LNA_GAIN_ODD_237___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__LNA_GAIN_ODD_237___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__GM_GAIN_ODD_237___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__GM_GAIN_ODD_237___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__TIA_GAIN_ODD_237___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__TIA_GAIN_ODD_237___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__SLM_XLNA_ODD_237___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__SLM_XLNA_ODD_237___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__BQ_GAIN_ODD_237___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__BQ_GAIN_ODD_237___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__XLNA_GAIN_EVEN_237___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__XLNA_GAIN_EVEN_237___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__LNA_GAIN_EVEN_237___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__LNA_GAIN_EVEN_237___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__GM_GAIN_EVEN_237___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__GM_GAIN_EVEN_237___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__TIA_GAIN_EVEN_237___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__TIA_GAIN_EVEN_237___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__SLM_XLNA_EVEN_237___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__SLM_XLNA_EVEN_237___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__BQ_GAIN_EVEN_237___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237__BQ_GAIN_EVEN_237___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_237___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238 (0x005ED3B8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__XLNA_GAIN_ODD_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__LNA_GAIN_ODD_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__GM_GAIN_ODD_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__TIA_GAIN_ODD_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__SLM_XLNA_ODD_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__BQ_GAIN_ODD_238___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__XLNA_GAIN_EVEN_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__LNA_GAIN_EVEN_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__GM_GAIN_EVEN_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__TIA_GAIN_EVEN_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__SLM_XLNA_EVEN_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__BQ_GAIN_EVEN_238___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__XLNA_GAIN_ODD_238___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__XLNA_GAIN_ODD_238___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__LNA_GAIN_ODD_238___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__LNA_GAIN_ODD_238___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__GM_GAIN_ODD_238___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__GM_GAIN_ODD_238___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__TIA_GAIN_ODD_238___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__TIA_GAIN_ODD_238___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__SLM_XLNA_ODD_238___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__SLM_XLNA_ODD_238___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__BQ_GAIN_ODD_238___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__BQ_GAIN_ODD_238___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__XLNA_GAIN_EVEN_238___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__XLNA_GAIN_EVEN_238___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__LNA_GAIN_EVEN_238___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__LNA_GAIN_EVEN_238___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__GM_GAIN_EVEN_238___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__GM_GAIN_EVEN_238___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__TIA_GAIN_EVEN_238___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__TIA_GAIN_EVEN_238___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__SLM_XLNA_EVEN_238___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__SLM_XLNA_EVEN_238___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__BQ_GAIN_EVEN_238___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238__BQ_GAIN_EVEN_238___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_238___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239 (0x005ED3BC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__XLNA_GAIN_ODD_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__LNA_GAIN_ODD_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__GM_GAIN_ODD_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__TIA_GAIN_ODD_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__SLM_XLNA_ODD_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__BQ_GAIN_ODD_239___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__XLNA_GAIN_EVEN_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__LNA_GAIN_EVEN_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__GM_GAIN_EVEN_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__TIA_GAIN_EVEN_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__SLM_XLNA_EVEN_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__BQ_GAIN_EVEN_239___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__XLNA_GAIN_ODD_239___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__XLNA_GAIN_ODD_239___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__LNA_GAIN_ODD_239___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__LNA_GAIN_ODD_239___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__GM_GAIN_ODD_239___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__GM_GAIN_ODD_239___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__TIA_GAIN_ODD_239___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__TIA_GAIN_ODD_239___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__SLM_XLNA_ODD_239___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__SLM_XLNA_ODD_239___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__BQ_GAIN_ODD_239___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__BQ_GAIN_ODD_239___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__XLNA_GAIN_EVEN_239___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__XLNA_GAIN_EVEN_239___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__LNA_GAIN_EVEN_239___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__LNA_GAIN_EVEN_239___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__GM_GAIN_EVEN_239___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__GM_GAIN_EVEN_239___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__TIA_GAIN_EVEN_239___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__TIA_GAIN_EVEN_239___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__SLM_XLNA_EVEN_239___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__SLM_XLNA_EVEN_239___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__BQ_GAIN_EVEN_239___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239__BQ_GAIN_EVEN_239___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_239___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240 (0x005ED3C0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__XLNA_GAIN_ODD_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__LNA_GAIN_ODD_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__GM_GAIN_ODD_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__TIA_GAIN_ODD_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__SLM_XLNA_ODD_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__BQ_GAIN_ODD_240___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__XLNA_GAIN_EVEN_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__LNA_GAIN_EVEN_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__GM_GAIN_EVEN_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__TIA_GAIN_EVEN_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__SLM_XLNA_EVEN_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__BQ_GAIN_EVEN_240___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__XLNA_GAIN_ODD_240___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__XLNA_GAIN_ODD_240___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__LNA_GAIN_ODD_240___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__LNA_GAIN_ODD_240___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__GM_GAIN_ODD_240___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__GM_GAIN_ODD_240___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__TIA_GAIN_ODD_240___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__TIA_GAIN_ODD_240___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__SLM_XLNA_ODD_240___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__SLM_XLNA_ODD_240___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__BQ_GAIN_ODD_240___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__BQ_GAIN_ODD_240___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__XLNA_GAIN_EVEN_240___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__XLNA_GAIN_EVEN_240___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__LNA_GAIN_EVEN_240___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__LNA_GAIN_EVEN_240___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__GM_GAIN_EVEN_240___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__GM_GAIN_EVEN_240___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__TIA_GAIN_EVEN_240___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__TIA_GAIN_EVEN_240___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__SLM_XLNA_EVEN_240___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__SLM_XLNA_EVEN_240___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__BQ_GAIN_EVEN_240___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240__BQ_GAIN_EVEN_240___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_240___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241 (0x005ED3C4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__XLNA_GAIN_ODD_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__LNA_GAIN_ODD_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__GM_GAIN_ODD_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__TIA_GAIN_ODD_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__SLM_XLNA_ODD_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__BQ_GAIN_ODD_241___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__XLNA_GAIN_EVEN_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__LNA_GAIN_EVEN_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__GM_GAIN_EVEN_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__TIA_GAIN_EVEN_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__SLM_XLNA_EVEN_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__BQ_GAIN_EVEN_241___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__XLNA_GAIN_ODD_241___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__XLNA_GAIN_ODD_241___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__LNA_GAIN_ODD_241___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__LNA_GAIN_ODD_241___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__GM_GAIN_ODD_241___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__GM_GAIN_ODD_241___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__TIA_GAIN_ODD_241___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__TIA_GAIN_ODD_241___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__SLM_XLNA_ODD_241___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__SLM_XLNA_ODD_241___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__BQ_GAIN_ODD_241___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__BQ_GAIN_ODD_241___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__XLNA_GAIN_EVEN_241___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__XLNA_GAIN_EVEN_241___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__LNA_GAIN_EVEN_241___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__LNA_GAIN_EVEN_241___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__GM_GAIN_EVEN_241___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__GM_GAIN_EVEN_241___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__TIA_GAIN_EVEN_241___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__TIA_GAIN_EVEN_241___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__SLM_XLNA_EVEN_241___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__SLM_XLNA_EVEN_241___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__BQ_GAIN_EVEN_241___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241__BQ_GAIN_EVEN_241___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_241___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242 (0x005ED3C8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__XLNA_GAIN_ODD_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__LNA_GAIN_ODD_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__GM_GAIN_ODD_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__TIA_GAIN_ODD_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__SLM_XLNA_ODD_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__BQ_GAIN_ODD_242___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__XLNA_GAIN_EVEN_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__LNA_GAIN_EVEN_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__GM_GAIN_EVEN_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__TIA_GAIN_EVEN_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__SLM_XLNA_EVEN_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__BQ_GAIN_EVEN_242___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__XLNA_GAIN_ODD_242___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__XLNA_GAIN_ODD_242___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__LNA_GAIN_ODD_242___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__LNA_GAIN_ODD_242___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__GM_GAIN_ODD_242___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__GM_GAIN_ODD_242___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__TIA_GAIN_ODD_242___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__TIA_GAIN_ODD_242___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__SLM_XLNA_ODD_242___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__SLM_XLNA_ODD_242___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__BQ_GAIN_ODD_242___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__BQ_GAIN_ODD_242___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__XLNA_GAIN_EVEN_242___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__XLNA_GAIN_EVEN_242___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__LNA_GAIN_EVEN_242___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__LNA_GAIN_EVEN_242___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__GM_GAIN_EVEN_242___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__GM_GAIN_EVEN_242___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__TIA_GAIN_EVEN_242___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__TIA_GAIN_EVEN_242___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__SLM_XLNA_EVEN_242___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__SLM_XLNA_EVEN_242___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__BQ_GAIN_EVEN_242___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242__BQ_GAIN_EVEN_242___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_242___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243 (0x005ED3CC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__XLNA_GAIN_ODD_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__LNA_GAIN_ODD_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__GM_GAIN_ODD_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__TIA_GAIN_ODD_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__SLM_XLNA_ODD_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__BQ_GAIN_ODD_243___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__XLNA_GAIN_EVEN_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__LNA_GAIN_EVEN_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__GM_GAIN_EVEN_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__TIA_GAIN_EVEN_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__SLM_XLNA_EVEN_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__BQ_GAIN_EVEN_243___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__XLNA_GAIN_ODD_243___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__XLNA_GAIN_ODD_243___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__LNA_GAIN_ODD_243___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__LNA_GAIN_ODD_243___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__GM_GAIN_ODD_243___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__GM_GAIN_ODD_243___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__TIA_GAIN_ODD_243___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__TIA_GAIN_ODD_243___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__SLM_XLNA_ODD_243___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__SLM_XLNA_ODD_243___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__BQ_GAIN_ODD_243___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__BQ_GAIN_ODD_243___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__XLNA_GAIN_EVEN_243___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__XLNA_GAIN_EVEN_243___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__LNA_GAIN_EVEN_243___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__LNA_GAIN_EVEN_243___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__GM_GAIN_EVEN_243___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__GM_GAIN_EVEN_243___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__TIA_GAIN_EVEN_243___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__TIA_GAIN_EVEN_243___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__SLM_XLNA_EVEN_243___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__SLM_XLNA_EVEN_243___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__BQ_GAIN_EVEN_243___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243__BQ_GAIN_EVEN_243___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_243___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244 (0x005ED3D0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__XLNA_GAIN_ODD_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__LNA_GAIN_ODD_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__GM_GAIN_ODD_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__TIA_GAIN_ODD_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__SLM_XLNA_ODD_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__BQ_GAIN_ODD_244___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__XLNA_GAIN_EVEN_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__LNA_GAIN_EVEN_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__GM_GAIN_EVEN_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__TIA_GAIN_EVEN_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__SLM_XLNA_EVEN_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__BQ_GAIN_EVEN_244___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__XLNA_GAIN_ODD_244___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__XLNA_GAIN_ODD_244___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__LNA_GAIN_ODD_244___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__LNA_GAIN_ODD_244___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__GM_GAIN_ODD_244___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__GM_GAIN_ODD_244___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__TIA_GAIN_ODD_244___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__TIA_GAIN_ODD_244___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__SLM_XLNA_ODD_244___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__SLM_XLNA_ODD_244___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__BQ_GAIN_ODD_244___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__BQ_GAIN_ODD_244___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__XLNA_GAIN_EVEN_244___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__XLNA_GAIN_EVEN_244___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__LNA_GAIN_EVEN_244___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__LNA_GAIN_EVEN_244___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__GM_GAIN_EVEN_244___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__GM_GAIN_EVEN_244___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__TIA_GAIN_EVEN_244___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__TIA_GAIN_EVEN_244___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__SLM_XLNA_EVEN_244___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__SLM_XLNA_EVEN_244___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__BQ_GAIN_EVEN_244___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244__BQ_GAIN_EVEN_244___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_244___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245 (0x005ED3D4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__XLNA_GAIN_ODD_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__LNA_GAIN_ODD_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__GM_GAIN_ODD_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__TIA_GAIN_ODD_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__SLM_XLNA_ODD_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__BQ_GAIN_ODD_245___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__XLNA_GAIN_EVEN_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__LNA_GAIN_EVEN_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__GM_GAIN_EVEN_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__TIA_GAIN_EVEN_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__SLM_XLNA_EVEN_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__BQ_GAIN_EVEN_245___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__XLNA_GAIN_ODD_245___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__XLNA_GAIN_ODD_245___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__LNA_GAIN_ODD_245___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__LNA_GAIN_ODD_245___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__GM_GAIN_ODD_245___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__GM_GAIN_ODD_245___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__TIA_GAIN_ODD_245___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__TIA_GAIN_ODD_245___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__SLM_XLNA_ODD_245___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__SLM_XLNA_ODD_245___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__BQ_GAIN_ODD_245___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__BQ_GAIN_ODD_245___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__XLNA_GAIN_EVEN_245___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__XLNA_GAIN_EVEN_245___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__LNA_GAIN_EVEN_245___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__LNA_GAIN_EVEN_245___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__GM_GAIN_EVEN_245___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__GM_GAIN_EVEN_245___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__TIA_GAIN_EVEN_245___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__TIA_GAIN_EVEN_245___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__SLM_XLNA_EVEN_245___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__SLM_XLNA_EVEN_245___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__BQ_GAIN_EVEN_245___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245__BQ_GAIN_EVEN_245___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_245___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246 (0x005ED3D8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__XLNA_GAIN_ODD_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__LNA_GAIN_ODD_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__GM_GAIN_ODD_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__TIA_GAIN_ODD_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__SLM_XLNA_ODD_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__BQ_GAIN_ODD_246___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__XLNA_GAIN_EVEN_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__LNA_GAIN_EVEN_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__GM_GAIN_EVEN_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__TIA_GAIN_EVEN_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__SLM_XLNA_EVEN_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__BQ_GAIN_EVEN_246___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__XLNA_GAIN_ODD_246___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__XLNA_GAIN_ODD_246___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__LNA_GAIN_ODD_246___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__LNA_GAIN_ODD_246___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__GM_GAIN_ODD_246___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__GM_GAIN_ODD_246___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__TIA_GAIN_ODD_246___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__TIA_GAIN_ODD_246___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__SLM_XLNA_ODD_246___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__SLM_XLNA_ODD_246___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__BQ_GAIN_ODD_246___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__BQ_GAIN_ODD_246___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__XLNA_GAIN_EVEN_246___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__XLNA_GAIN_EVEN_246___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__LNA_GAIN_EVEN_246___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__LNA_GAIN_EVEN_246___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__GM_GAIN_EVEN_246___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__GM_GAIN_EVEN_246___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__TIA_GAIN_EVEN_246___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__TIA_GAIN_EVEN_246___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__SLM_XLNA_EVEN_246___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__SLM_XLNA_EVEN_246___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__BQ_GAIN_EVEN_246___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246__BQ_GAIN_EVEN_246___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_246___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247 (0x005ED3DC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__XLNA_GAIN_ODD_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__LNA_GAIN_ODD_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__GM_GAIN_ODD_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__TIA_GAIN_ODD_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__SLM_XLNA_ODD_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__BQ_GAIN_ODD_247___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__XLNA_GAIN_EVEN_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__LNA_GAIN_EVEN_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__GM_GAIN_EVEN_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__TIA_GAIN_EVEN_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__SLM_XLNA_EVEN_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__BQ_GAIN_EVEN_247___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__XLNA_GAIN_ODD_247___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__XLNA_GAIN_ODD_247___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__LNA_GAIN_ODD_247___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__LNA_GAIN_ODD_247___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__GM_GAIN_ODD_247___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__GM_GAIN_ODD_247___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__TIA_GAIN_ODD_247___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__TIA_GAIN_ODD_247___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__SLM_XLNA_ODD_247___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__SLM_XLNA_ODD_247___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__BQ_GAIN_ODD_247___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__BQ_GAIN_ODD_247___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__XLNA_GAIN_EVEN_247___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__XLNA_GAIN_EVEN_247___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__LNA_GAIN_EVEN_247___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__LNA_GAIN_EVEN_247___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__GM_GAIN_EVEN_247___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__GM_GAIN_EVEN_247___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__TIA_GAIN_EVEN_247___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__TIA_GAIN_EVEN_247___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__SLM_XLNA_EVEN_247___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__SLM_XLNA_EVEN_247___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__BQ_GAIN_EVEN_247___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247__BQ_GAIN_EVEN_247___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_247___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248 (0x005ED3E0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__XLNA_GAIN_ODD_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__LNA_GAIN_ODD_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__GM_GAIN_ODD_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__TIA_GAIN_ODD_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__SLM_XLNA_ODD_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__BQ_GAIN_ODD_248___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__XLNA_GAIN_EVEN_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__LNA_GAIN_EVEN_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__GM_GAIN_EVEN_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__TIA_GAIN_EVEN_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__SLM_XLNA_EVEN_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__BQ_GAIN_EVEN_248___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__XLNA_GAIN_ODD_248___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__XLNA_GAIN_ODD_248___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__LNA_GAIN_ODD_248___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__LNA_GAIN_ODD_248___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__GM_GAIN_ODD_248___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__GM_GAIN_ODD_248___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__TIA_GAIN_ODD_248___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__TIA_GAIN_ODD_248___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__SLM_XLNA_ODD_248___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__SLM_XLNA_ODD_248___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__BQ_GAIN_ODD_248___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__BQ_GAIN_ODD_248___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__XLNA_GAIN_EVEN_248___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__XLNA_GAIN_EVEN_248___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__LNA_GAIN_EVEN_248___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__LNA_GAIN_EVEN_248___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__GM_GAIN_EVEN_248___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__GM_GAIN_EVEN_248___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__TIA_GAIN_EVEN_248___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__TIA_GAIN_EVEN_248___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__SLM_XLNA_EVEN_248___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__SLM_XLNA_EVEN_248___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__BQ_GAIN_EVEN_248___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248__BQ_GAIN_EVEN_248___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_248___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249 (0x005ED3E4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__XLNA_GAIN_ODD_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__LNA_GAIN_ODD_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__GM_GAIN_ODD_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__TIA_GAIN_ODD_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__SLM_XLNA_ODD_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__BQ_GAIN_ODD_249___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__XLNA_GAIN_EVEN_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__LNA_GAIN_EVEN_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__GM_GAIN_EVEN_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__TIA_GAIN_EVEN_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__SLM_XLNA_EVEN_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__BQ_GAIN_EVEN_249___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__XLNA_GAIN_ODD_249___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__XLNA_GAIN_ODD_249___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__LNA_GAIN_ODD_249___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__LNA_GAIN_ODD_249___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__GM_GAIN_ODD_249___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__GM_GAIN_ODD_249___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__TIA_GAIN_ODD_249___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__TIA_GAIN_ODD_249___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__SLM_XLNA_ODD_249___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__SLM_XLNA_ODD_249___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__BQ_GAIN_ODD_249___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__BQ_GAIN_ODD_249___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__XLNA_GAIN_EVEN_249___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__XLNA_GAIN_EVEN_249___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__LNA_GAIN_EVEN_249___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__LNA_GAIN_EVEN_249___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__GM_GAIN_EVEN_249___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__GM_GAIN_EVEN_249___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__TIA_GAIN_EVEN_249___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__TIA_GAIN_EVEN_249___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__SLM_XLNA_EVEN_249___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__SLM_XLNA_EVEN_249___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__BQ_GAIN_EVEN_249___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249__BQ_GAIN_EVEN_249___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_249___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250 (0x005ED3E8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__XLNA_GAIN_ODD_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__LNA_GAIN_ODD_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__GM_GAIN_ODD_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__TIA_GAIN_ODD_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__SLM_XLNA_ODD_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__BQ_GAIN_ODD_250___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__XLNA_GAIN_EVEN_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__LNA_GAIN_EVEN_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__GM_GAIN_EVEN_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__TIA_GAIN_EVEN_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__SLM_XLNA_EVEN_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__BQ_GAIN_EVEN_250___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__XLNA_GAIN_ODD_250___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__XLNA_GAIN_ODD_250___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__LNA_GAIN_ODD_250___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__LNA_GAIN_ODD_250___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__GM_GAIN_ODD_250___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__GM_GAIN_ODD_250___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__TIA_GAIN_ODD_250___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__TIA_GAIN_ODD_250___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__SLM_XLNA_ODD_250___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__SLM_XLNA_ODD_250___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__BQ_GAIN_ODD_250___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__BQ_GAIN_ODD_250___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__XLNA_GAIN_EVEN_250___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__XLNA_GAIN_EVEN_250___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__LNA_GAIN_EVEN_250___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__LNA_GAIN_EVEN_250___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__GM_GAIN_EVEN_250___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__GM_GAIN_EVEN_250___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__TIA_GAIN_EVEN_250___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__TIA_GAIN_EVEN_250___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__SLM_XLNA_EVEN_250___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__SLM_XLNA_EVEN_250___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__BQ_GAIN_EVEN_250___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250__BQ_GAIN_EVEN_250___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_250___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251 (0x005ED3EC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__XLNA_GAIN_ODD_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__LNA_GAIN_ODD_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__GM_GAIN_ODD_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__TIA_GAIN_ODD_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__SLM_XLNA_ODD_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__BQ_GAIN_ODD_251___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__XLNA_GAIN_EVEN_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__LNA_GAIN_EVEN_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__GM_GAIN_EVEN_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__TIA_GAIN_EVEN_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__SLM_XLNA_EVEN_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__BQ_GAIN_EVEN_251___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__XLNA_GAIN_ODD_251___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__XLNA_GAIN_ODD_251___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__LNA_GAIN_ODD_251___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__LNA_GAIN_ODD_251___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__GM_GAIN_ODD_251___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__GM_GAIN_ODD_251___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__TIA_GAIN_ODD_251___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__TIA_GAIN_ODD_251___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__SLM_XLNA_ODD_251___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__SLM_XLNA_ODD_251___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__BQ_GAIN_ODD_251___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__BQ_GAIN_ODD_251___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__XLNA_GAIN_EVEN_251___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__XLNA_GAIN_EVEN_251___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__LNA_GAIN_EVEN_251___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__LNA_GAIN_EVEN_251___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__GM_GAIN_EVEN_251___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__GM_GAIN_EVEN_251___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__TIA_GAIN_EVEN_251___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__TIA_GAIN_EVEN_251___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__SLM_XLNA_EVEN_251___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__SLM_XLNA_EVEN_251___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__BQ_GAIN_EVEN_251___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251__BQ_GAIN_EVEN_251___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_251___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252 (0x005ED3F0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__XLNA_GAIN_ODD_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__LNA_GAIN_ODD_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__GM_GAIN_ODD_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__TIA_GAIN_ODD_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__SLM_XLNA_ODD_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__BQ_GAIN_ODD_252___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__XLNA_GAIN_EVEN_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__LNA_GAIN_EVEN_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__GM_GAIN_EVEN_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__TIA_GAIN_EVEN_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__SLM_XLNA_EVEN_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__BQ_GAIN_EVEN_252___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__XLNA_GAIN_ODD_252___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__XLNA_GAIN_ODD_252___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__LNA_GAIN_ODD_252___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__LNA_GAIN_ODD_252___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__GM_GAIN_ODD_252___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__GM_GAIN_ODD_252___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__TIA_GAIN_ODD_252___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__TIA_GAIN_ODD_252___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__SLM_XLNA_ODD_252___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__SLM_XLNA_ODD_252___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__BQ_GAIN_ODD_252___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__BQ_GAIN_ODD_252___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__XLNA_GAIN_EVEN_252___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__XLNA_GAIN_EVEN_252___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__LNA_GAIN_EVEN_252___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__LNA_GAIN_EVEN_252___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__GM_GAIN_EVEN_252___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__GM_GAIN_EVEN_252___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__TIA_GAIN_EVEN_252___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__TIA_GAIN_EVEN_252___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__SLM_XLNA_EVEN_252___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__SLM_XLNA_EVEN_252___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__BQ_GAIN_EVEN_252___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252__BQ_GAIN_EVEN_252___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_252___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253 (0x005ED3F4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__XLNA_GAIN_ODD_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__LNA_GAIN_ODD_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__GM_GAIN_ODD_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__TIA_GAIN_ODD_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__SLM_XLNA_ODD_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__BQ_GAIN_ODD_253___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__XLNA_GAIN_EVEN_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__LNA_GAIN_EVEN_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__GM_GAIN_EVEN_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__TIA_GAIN_EVEN_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__SLM_XLNA_EVEN_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__BQ_GAIN_EVEN_253___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__XLNA_GAIN_ODD_253___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__XLNA_GAIN_ODD_253___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__LNA_GAIN_ODD_253___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__LNA_GAIN_ODD_253___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__GM_GAIN_ODD_253___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__GM_GAIN_ODD_253___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__TIA_GAIN_ODD_253___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__TIA_GAIN_ODD_253___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__SLM_XLNA_ODD_253___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__SLM_XLNA_ODD_253___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__BQ_GAIN_ODD_253___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__BQ_GAIN_ODD_253___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__XLNA_GAIN_EVEN_253___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__XLNA_GAIN_EVEN_253___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__LNA_GAIN_EVEN_253___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__LNA_GAIN_EVEN_253___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__GM_GAIN_EVEN_253___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__GM_GAIN_EVEN_253___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__TIA_GAIN_EVEN_253___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__TIA_GAIN_EVEN_253___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__SLM_XLNA_EVEN_253___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__SLM_XLNA_EVEN_253___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__BQ_GAIN_EVEN_253___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253__BQ_GAIN_EVEN_253___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_253___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254 (0x005ED3F8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__XLNA_GAIN_ODD_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__LNA_GAIN_ODD_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__GM_GAIN_ODD_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__TIA_GAIN_ODD_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__SLM_XLNA_ODD_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__BQ_GAIN_ODD_254___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__XLNA_GAIN_EVEN_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__LNA_GAIN_EVEN_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__GM_GAIN_EVEN_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__TIA_GAIN_EVEN_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__SLM_XLNA_EVEN_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__BQ_GAIN_EVEN_254___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__XLNA_GAIN_ODD_254___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__XLNA_GAIN_ODD_254___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__LNA_GAIN_ODD_254___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__LNA_GAIN_ODD_254___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__GM_GAIN_ODD_254___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__GM_GAIN_ODD_254___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__TIA_GAIN_ODD_254___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__TIA_GAIN_ODD_254___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__SLM_XLNA_ODD_254___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__SLM_XLNA_ODD_254___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__BQ_GAIN_ODD_254___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__BQ_GAIN_ODD_254___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__XLNA_GAIN_EVEN_254___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__XLNA_GAIN_EVEN_254___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__LNA_GAIN_EVEN_254___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__LNA_GAIN_EVEN_254___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__GM_GAIN_EVEN_254___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__GM_GAIN_EVEN_254___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__TIA_GAIN_EVEN_254___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__TIA_GAIN_EVEN_254___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__SLM_XLNA_EVEN_254___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__SLM_XLNA_EVEN_254___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__BQ_GAIN_EVEN_254___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254__BQ_GAIN_EVEN_254___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_254___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255 (0x005ED3FC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__XLNA_GAIN_ODD_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__LNA_GAIN_ODD_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__GM_GAIN_ODD_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__TIA_GAIN_ODD_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__SLM_XLNA_ODD_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__BQ_GAIN_ODD_255___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__XLNA_GAIN_EVEN_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__LNA_GAIN_EVEN_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__GM_GAIN_EVEN_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__TIA_GAIN_EVEN_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__SLM_XLNA_EVEN_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__BQ_GAIN_EVEN_255___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__XLNA_GAIN_ODD_255___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__XLNA_GAIN_ODD_255___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__LNA_GAIN_ODD_255___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__LNA_GAIN_ODD_255___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__GM_GAIN_ODD_255___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__GM_GAIN_ODD_255___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__TIA_GAIN_ODD_255___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__TIA_GAIN_ODD_255___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__SLM_XLNA_ODD_255___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__SLM_XLNA_ODD_255___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__BQ_GAIN_ODD_255___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__BQ_GAIN_ODD_255___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__XLNA_GAIN_EVEN_255___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__XLNA_GAIN_EVEN_255___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__LNA_GAIN_EVEN_255___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__LNA_GAIN_EVEN_255___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__GM_GAIN_EVEN_255___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__GM_GAIN_EVEN_255___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__TIA_GAIN_EVEN_255___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__TIA_GAIN_EVEN_255___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__SLM_XLNA_EVEN_255___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__SLM_XLNA_EVEN_255___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__BQ_GAIN_EVEN_255___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255__BQ_GAIN_EVEN_255___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_RXGAIN_255___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_0 (0x005ED800) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_0__TX_DCOC_RES_I_ODD_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_0__TX_DCOC_RES_Q_ODD_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_0__TX_DCOC_RES_I_EVEN_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_0__TX_DCOC_RES_Q_EVEN_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_0__TX_DCOC_RES_I_ODD_0___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_0__TX_DCOC_RES_I_ODD_0___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_0__TX_DCOC_RES_Q_ODD_0___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_0__TX_DCOC_RES_Q_ODD_0___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_0__TX_DCOC_RES_I_EVEN_0___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_0__TX_DCOC_RES_I_EVEN_0___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_0__TX_DCOC_RES_Q_EVEN_0___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_0__TX_DCOC_RES_Q_EVEN_0___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_0___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_1 (0x005ED804) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_1__TX_DCOC_RES_I_ODD_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_1__TX_DCOC_RES_Q_ODD_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_1__TX_DCOC_RES_I_EVEN_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_1__TX_DCOC_RES_Q_EVEN_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_1__TX_DCOC_RES_I_ODD_1___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_1__TX_DCOC_RES_I_ODD_1___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_1__TX_DCOC_RES_Q_ODD_1___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_1__TX_DCOC_RES_Q_ODD_1___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_1__TX_DCOC_RES_I_EVEN_1___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_1__TX_DCOC_RES_I_EVEN_1___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_1__TX_DCOC_RES_Q_EVEN_1___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_1__TX_DCOC_RES_Q_EVEN_1___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_1___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_2 (0x005ED808) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_2__TX_DCOC_RES_I_ODD_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_2__TX_DCOC_RES_Q_ODD_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_2__TX_DCOC_RES_I_EVEN_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_2__TX_DCOC_RES_Q_EVEN_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_2__TX_DCOC_RES_I_ODD_2___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_2__TX_DCOC_RES_I_ODD_2___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_2__TX_DCOC_RES_Q_ODD_2___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_2__TX_DCOC_RES_Q_ODD_2___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_2__TX_DCOC_RES_I_EVEN_2___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_2__TX_DCOC_RES_I_EVEN_2___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_2__TX_DCOC_RES_Q_EVEN_2___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_2__TX_DCOC_RES_Q_EVEN_2___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_2___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_2___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_3 (0x005ED80C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_3__TX_DCOC_RES_I_ODD_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_3__TX_DCOC_RES_Q_ODD_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_3__TX_DCOC_RES_I_EVEN_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_3__TX_DCOC_RES_Q_EVEN_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_3__TX_DCOC_RES_I_ODD_3___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_3__TX_DCOC_RES_I_ODD_3___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_3__TX_DCOC_RES_Q_ODD_3___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_3__TX_DCOC_RES_Q_ODD_3___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_3__TX_DCOC_RES_I_EVEN_3___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_3__TX_DCOC_RES_I_EVEN_3___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_3__TX_DCOC_RES_Q_EVEN_3___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_3__TX_DCOC_RES_Q_EVEN_3___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_3___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_3___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_4 (0x005ED810) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_4__TX_DCOC_RES_I_ODD_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_4__TX_DCOC_RES_Q_ODD_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_4__TX_DCOC_RES_I_EVEN_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_4__TX_DCOC_RES_Q_EVEN_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_4__TX_DCOC_RES_I_ODD_4___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_4__TX_DCOC_RES_I_ODD_4___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_4__TX_DCOC_RES_Q_ODD_4___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_4__TX_DCOC_RES_Q_ODD_4___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_4__TX_DCOC_RES_I_EVEN_4___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_4__TX_DCOC_RES_I_EVEN_4___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_4__TX_DCOC_RES_Q_EVEN_4___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_4__TX_DCOC_RES_Q_EVEN_4___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_4___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_4___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_5 (0x005ED814) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_5__TX_DCOC_RES_I_ODD_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_5__TX_DCOC_RES_Q_ODD_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_5__TX_DCOC_RES_I_EVEN_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_5__TX_DCOC_RES_Q_EVEN_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_5__TX_DCOC_RES_I_ODD_5___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_5__TX_DCOC_RES_I_ODD_5___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_5__TX_DCOC_RES_Q_ODD_5___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_5__TX_DCOC_RES_Q_ODD_5___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_5__TX_DCOC_RES_I_EVEN_5___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_5__TX_DCOC_RES_I_EVEN_5___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_5__TX_DCOC_RES_Q_EVEN_5___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_5__TX_DCOC_RES_Q_EVEN_5___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_5___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_5___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_6 (0x005ED818) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_6__TX_DCOC_RES_I_ODD_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_6__TX_DCOC_RES_Q_ODD_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_6__TX_DCOC_RES_I_EVEN_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_6__TX_DCOC_RES_Q_EVEN_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_6__TX_DCOC_RES_I_ODD_6___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_6__TX_DCOC_RES_I_ODD_6___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_6__TX_DCOC_RES_Q_ODD_6___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_6__TX_DCOC_RES_Q_ODD_6___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_6__TX_DCOC_RES_I_EVEN_6___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_6__TX_DCOC_RES_I_EVEN_6___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_6__TX_DCOC_RES_Q_EVEN_6___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_6__TX_DCOC_RES_Q_EVEN_6___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_6___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_6___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_7 (0x005ED81C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_7__TX_DCOC_RES_I_ODD_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_7__TX_DCOC_RES_Q_ODD_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_7__TX_DCOC_RES_I_EVEN_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_7__TX_DCOC_RES_Q_EVEN_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_7__TX_DCOC_RES_I_ODD_7___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_7__TX_DCOC_RES_I_ODD_7___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_7__TX_DCOC_RES_Q_ODD_7___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_7__TX_DCOC_RES_Q_ODD_7___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_7__TX_DCOC_RES_I_EVEN_7___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_7__TX_DCOC_RES_I_EVEN_7___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_7__TX_DCOC_RES_Q_EVEN_7___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_7__TX_DCOC_RES_Q_EVEN_7___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_7___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_7___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_8 (0x005ED820) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_8__TX_DCOC_RES_I_ODD_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_8__TX_DCOC_RES_Q_ODD_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_8__TX_DCOC_RES_I_EVEN_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_8__TX_DCOC_RES_Q_EVEN_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_8__TX_DCOC_RES_I_ODD_8___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_8__TX_DCOC_RES_I_ODD_8___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_8__TX_DCOC_RES_Q_ODD_8___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_8__TX_DCOC_RES_Q_ODD_8___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_8__TX_DCOC_RES_I_EVEN_8___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_8__TX_DCOC_RES_I_EVEN_8___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_8__TX_DCOC_RES_Q_EVEN_8___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_8__TX_DCOC_RES_Q_EVEN_8___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_8___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_8___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_9 (0x005ED824) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_9__TX_DCOC_RES_I_ODD_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_9__TX_DCOC_RES_Q_ODD_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_9__TX_DCOC_RES_I_EVEN_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_9__TX_DCOC_RES_Q_EVEN_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_9__TX_DCOC_RES_I_ODD_9___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_9__TX_DCOC_RES_I_ODD_9___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_9__TX_DCOC_RES_Q_ODD_9___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_9__TX_DCOC_RES_Q_ODD_9___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_9__TX_DCOC_RES_I_EVEN_9___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_9__TX_DCOC_RES_I_EVEN_9___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_9__TX_DCOC_RES_Q_EVEN_9___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_9__TX_DCOC_RES_Q_EVEN_9___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_9___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_9___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_10 (0x005ED828) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_10__TX_DCOC_RES_I_ODD_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_10__TX_DCOC_RES_Q_ODD_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_10__TX_DCOC_RES_I_EVEN_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_10__TX_DCOC_RES_Q_EVEN_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_10__TX_DCOC_RES_I_ODD_10___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_10__TX_DCOC_RES_I_ODD_10___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_10__TX_DCOC_RES_Q_ODD_10___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_10__TX_DCOC_RES_Q_ODD_10___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_10__TX_DCOC_RES_I_EVEN_10___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_10__TX_DCOC_RES_I_EVEN_10___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_10__TX_DCOC_RES_Q_EVEN_10___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_10__TX_DCOC_RES_Q_EVEN_10___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_10___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_10___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_11 (0x005ED82C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_11__TX_DCOC_RES_I_ODD_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_11__TX_DCOC_RES_Q_ODD_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_11__TX_DCOC_RES_I_EVEN_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_11__TX_DCOC_RES_Q_EVEN_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_11__TX_DCOC_RES_I_ODD_11___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_11__TX_DCOC_RES_I_ODD_11___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_11__TX_DCOC_RES_Q_ODD_11___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_11__TX_DCOC_RES_Q_ODD_11___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_11__TX_DCOC_RES_I_EVEN_11___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_11__TX_DCOC_RES_I_EVEN_11___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_11__TX_DCOC_RES_Q_EVEN_11___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_11__TX_DCOC_RES_Q_EVEN_11___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_11___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_11___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_12 (0x005ED830) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_12__TX_DCOC_RES_I_ODD_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_12__TX_DCOC_RES_Q_ODD_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_12__TX_DCOC_RES_I_EVEN_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_12__TX_DCOC_RES_Q_EVEN_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_12__TX_DCOC_RES_I_ODD_12___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_12__TX_DCOC_RES_I_ODD_12___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_12__TX_DCOC_RES_Q_ODD_12___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_12__TX_DCOC_RES_Q_ODD_12___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_12__TX_DCOC_RES_I_EVEN_12___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_12__TX_DCOC_RES_I_EVEN_12___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_12__TX_DCOC_RES_Q_EVEN_12___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_12__TX_DCOC_RES_Q_EVEN_12___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_12___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_12___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_13 (0x005ED834) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_13__TX_DCOC_RES_I_ODD_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_13__TX_DCOC_RES_Q_ODD_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_13__TX_DCOC_RES_I_EVEN_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_13__TX_DCOC_RES_Q_EVEN_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_13__TX_DCOC_RES_I_ODD_13___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_13__TX_DCOC_RES_I_ODD_13___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_13__TX_DCOC_RES_Q_ODD_13___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_13__TX_DCOC_RES_Q_ODD_13___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_13__TX_DCOC_RES_I_EVEN_13___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_13__TX_DCOC_RES_I_EVEN_13___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_13__TX_DCOC_RES_Q_EVEN_13___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_13__TX_DCOC_RES_Q_EVEN_13___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_13___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_13___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_14 (0x005ED838) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_14__TX_DCOC_RES_I_ODD_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_14__TX_DCOC_RES_Q_ODD_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_14__TX_DCOC_RES_I_EVEN_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_14__TX_DCOC_RES_Q_EVEN_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_14__TX_DCOC_RES_I_ODD_14___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_14__TX_DCOC_RES_I_ODD_14___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_14__TX_DCOC_RES_Q_ODD_14___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_14__TX_DCOC_RES_Q_ODD_14___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_14__TX_DCOC_RES_I_EVEN_14___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_14__TX_DCOC_RES_I_EVEN_14___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_14__TX_DCOC_RES_Q_EVEN_14___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_14__TX_DCOC_RES_Q_EVEN_14___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_14___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_14___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_15 (0x005ED83C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_15__TX_DCOC_RES_I_ODD_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_15__TX_DCOC_RES_Q_ODD_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_15__TX_DCOC_RES_I_EVEN_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_15__TX_DCOC_RES_Q_EVEN_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_15__TX_DCOC_RES_I_ODD_15___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_15__TX_DCOC_RES_I_ODD_15___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_15__TX_DCOC_RES_Q_ODD_15___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_15__TX_DCOC_RES_Q_ODD_15___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_15__TX_DCOC_RES_I_EVEN_15___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_15__TX_DCOC_RES_I_EVEN_15___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_15__TX_DCOC_RES_Q_EVEN_15___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_15__TX_DCOC_RES_Q_EVEN_15___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_15___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_15___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_16 (0x005ED840) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_16___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_16__TX_DCOC_RES_I_ODD_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_16__TX_DCOC_RES_Q_ODD_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_16__TX_DCOC_RES_I_EVEN_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_16__TX_DCOC_RES_Q_EVEN_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_16__TX_DCOC_RES_I_ODD_16___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_16__TX_DCOC_RES_I_ODD_16___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_16__TX_DCOC_RES_Q_ODD_16___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_16__TX_DCOC_RES_Q_ODD_16___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_16__TX_DCOC_RES_I_EVEN_16___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_16__TX_DCOC_RES_I_EVEN_16___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_16__TX_DCOC_RES_Q_EVEN_16___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_16__TX_DCOC_RES_Q_EVEN_16___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_16___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_16___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_17 (0x005ED844) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_17___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_17__TX_DCOC_RES_I_ODD_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_17__TX_DCOC_RES_Q_ODD_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_17__TX_DCOC_RES_I_EVEN_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_17__TX_DCOC_RES_Q_EVEN_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_17__TX_DCOC_RES_I_ODD_17___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_17__TX_DCOC_RES_I_ODD_17___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_17__TX_DCOC_RES_Q_ODD_17___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_17__TX_DCOC_RES_Q_ODD_17___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_17__TX_DCOC_RES_I_EVEN_17___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_17__TX_DCOC_RES_I_EVEN_17___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_17__TX_DCOC_RES_Q_EVEN_17___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_17__TX_DCOC_RES_Q_EVEN_17___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_17___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_17___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_18 (0x005ED848) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_18___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_18__TX_DCOC_RES_I_ODD_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_18__TX_DCOC_RES_Q_ODD_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_18__TX_DCOC_RES_I_EVEN_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_18__TX_DCOC_RES_Q_EVEN_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_18__TX_DCOC_RES_I_ODD_18___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_18__TX_DCOC_RES_I_ODD_18___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_18__TX_DCOC_RES_Q_ODD_18___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_18__TX_DCOC_RES_Q_ODD_18___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_18__TX_DCOC_RES_I_EVEN_18___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_18__TX_DCOC_RES_I_EVEN_18___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_18__TX_DCOC_RES_Q_EVEN_18___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_18__TX_DCOC_RES_Q_EVEN_18___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_18___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_18___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_19 (0x005ED84C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_19___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_19__TX_DCOC_RES_I_ODD_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_19__TX_DCOC_RES_Q_ODD_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_19__TX_DCOC_RES_I_EVEN_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_19__TX_DCOC_RES_Q_EVEN_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_19__TX_DCOC_RES_I_ODD_19___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_19__TX_DCOC_RES_I_ODD_19___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_19__TX_DCOC_RES_Q_ODD_19___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_19__TX_DCOC_RES_Q_ODD_19___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_19__TX_DCOC_RES_I_EVEN_19___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_19__TX_DCOC_RES_I_EVEN_19___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_19__TX_DCOC_RES_Q_EVEN_19___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_19__TX_DCOC_RES_Q_EVEN_19___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_19___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_19___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_20 (0x005ED850) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_20___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_20__TX_DCOC_RES_I_ODD_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_20__TX_DCOC_RES_Q_ODD_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_20__TX_DCOC_RES_I_EVEN_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_20__TX_DCOC_RES_Q_EVEN_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_20__TX_DCOC_RES_I_ODD_20___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_20__TX_DCOC_RES_I_ODD_20___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_20__TX_DCOC_RES_Q_ODD_20___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_20__TX_DCOC_RES_Q_ODD_20___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_20__TX_DCOC_RES_I_EVEN_20___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_20__TX_DCOC_RES_I_EVEN_20___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_20__TX_DCOC_RES_Q_EVEN_20___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_20__TX_DCOC_RES_Q_EVEN_20___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_20___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_20___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_21 (0x005ED854) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_21___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_21__TX_DCOC_RES_I_ODD_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_21__TX_DCOC_RES_Q_ODD_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_21__TX_DCOC_RES_I_EVEN_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_21__TX_DCOC_RES_Q_EVEN_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_21__TX_DCOC_RES_I_ODD_21___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_21__TX_DCOC_RES_I_ODD_21___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_21__TX_DCOC_RES_Q_ODD_21___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_21__TX_DCOC_RES_Q_ODD_21___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_21__TX_DCOC_RES_I_EVEN_21___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_21__TX_DCOC_RES_I_EVEN_21___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_21__TX_DCOC_RES_Q_EVEN_21___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_21__TX_DCOC_RES_Q_EVEN_21___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_21___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_21___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_22 (0x005ED858) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_22___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_22__TX_DCOC_RES_I_ODD_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_22__TX_DCOC_RES_Q_ODD_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_22__TX_DCOC_RES_I_EVEN_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_22__TX_DCOC_RES_Q_EVEN_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_22__TX_DCOC_RES_I_ODD_22___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_22__TX_DCOC_RES_I_ODD_22___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_22__TX_DCOC_RES_Q_ODD_22___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_22__TX_DCOC_RES_Q_ODD_22___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_22__TX_DCOC_RES_I_EVEN_22___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_22__TX_DCOC_RES_I_EVEN_22___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_22__TX_DCOC_RES_Q_EVEN_22___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_22__TX_DCOC_RES_Q_EVEN_22___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_22___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_22___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_23 (0x005ED85C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_23___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_23__TX_DCOC_RES_I_ODD_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_23__TX_DCOC_RES_Q_ODD_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_23__TX_DCOC_RES_I_EVEN_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_23__TX_DCOC_RES_Q_EVEN_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_23__TX_DCOC_RES_I_ODD_23___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_23__TX_DCOC_RES_I_ODD_23___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_23__TX_DCOC_RES_Q_ODD_23___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_23__TX_DCOC_RES_Q_ODD_23___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_23__TX_DCOC_RES_I_EVEN_23___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_23__TX_DCOC_RES_I_EVEN_23___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_23__TX_DCOC_RES_Q_EVEN_23___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_23__TX_DCOC_RES_Q_EVEN_23___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_23___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_23___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_24 (0x005ED860) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_24___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_24__TX_DCOC_RES_I_ODD_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_24__TX_DCOC_RES_Q_ODD_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_24__TX_DCOC_RES_I_EVEN_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_24__TX_DCOC_RES_Q_EVEN_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_24__TX_DCOC_RES_I_ODD_24___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_24__TX_DCOC_RES_I_ODD_24___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_24__TX_DCOC_RES_Q_ODD_24___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_24__TX_DCOC_RES_Q_ODD_24___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_24__TX_DCOC_RES_I_EVEN_24___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_24__TX_DCOC_RES_I_EVEN_24___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_24__TX_DCOC_RES_Q_EVEN_24___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_24__TX_DCOC_RES_Q_EVEN_24___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_24___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_24___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_25 (0x005ED864) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_25___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_25__TX_DCOC_RES_I_ODD_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_25__TX_DCOC_RES_Q_ODD_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_25__TX_DCOC_RES_I_EVEN_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_25__TX_DCOC_RES_Q_EVEN_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_25__TX_DCOC_RES_I_ODD_25___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_25__TX_DCOC_RES_I_ODD_25___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_25__TX_DCOC_RES_Q_ODD_25___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_25__TX_DCOC_RES_Q_ODD_25___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_25__TX_DCOC_RES_I_EVEN_25___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_25__TX_DCOC_RES_I_EVEN_25___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_25__TX_DCOC_RES_Q_EVEN_25___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_25__TX_DCOC_RES_Q_EVEN_25___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_25___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_25___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_26 (0x005ED868) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_26___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_26__TX_DCOC_RES_I_ODD_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_26__TX_DCOC_RES_Q_ODD_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_26__TX_DCOC_RES_I_EVEN_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_26__TX_DCOC_RES_Q_EVEN_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_26__TX_DCOC_RES_I_ODD_26___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_26__TX_DCOC_RES_I_ODD_26___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_26__TX_DCOC_RES_Q_ODD_26___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_26__TX_DCOC_RES_Q_ODD_26___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_26__TX_DCOC_RES_I_EVEN_26___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_26__TX_DCOC_RES_I_EVEN_26___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_26__TX_DCOC_RES_Q_EVEN_26___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_26__TX_DCOC_RES_Q_EVEN_26___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_26___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_26___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_27 (0x005ED86C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_27___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_27__TX_DCOC_RES_I_ODD_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_27__TX_DCOC_RES_Q_ODD_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_27__TX_DCOC_RES_I_EVEN_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_27__TX_DCOC_RES_Q_EVEN_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_27__TX_DCOC_RES_I_ODD_27___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_27__TX_DCOC_RES_I_ODD_27___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_27__TX_DCOC_RES_Q_ODD_27___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_27__TX_DCOC_RES_Q_ODD_27___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_27__TX_DCOC_RES_I_EVEN_27___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_27__TX_DCOC_RES_I_EVEN_27___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_27__TX_DCOC_RES_Q_EVEN_27___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_27__TX_DCOC_RES_Q_EVEN_27___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_27___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_27___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_28 (0x005ED870) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_28___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_28__TX_DCOC_RES_I_ODD_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_28__TX_DCOC_RES_Q_ODD_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_28__TX_DCOC_RES_I_EVEN_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_28__TX_DCOC_RES_Q_EVEN_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_28__TX_DCOC_RES_I_ODD_28___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_28__TX_DCOC_RES_I_ODD_28___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_28__TX_DCOC_RES_Q_ODD_28___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_28__TX_DCOC_RES_Q_ODD_28___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_28__TX_DCOC_RES_I_EVEN_28___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_28__TX_DCOC_RES_I_EVEN_28___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_28__TX_DCOC_RES_Q_EVEN_28___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_28__TX_DCOC_RES_Q_EVEN_28___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_28___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_28___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_29 (0x005ED874) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_29___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_29__TX_DCOC_RES_I_ODD_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_29__TX_DCOC_RES_Q_ODD_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_29__TX_DCOC_RES_I_EVEN_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_29__TX_DCOC_RES_Q_EVEN_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_29__TX_DCOC_RES_I_ODD_29___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_29__TX_DCOC_RES_I_ODD_29___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_29__TX_DCOC_RES_Q_ODD_29___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_29__TX_DCOC_RES_Q_ODD_29___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_29__TX_DCOC_RES_I_EVEN_29___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_29__TX_DCOC_RES_I_EVEN_29___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_29__TX_DCOC_RES_Q_EVEN_29___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_29__TX_DCOC_RES_Q_EVEN_29___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_29___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_29___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_30 (0x005ED878) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_30___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_30__TX_DCOC_RES_I_ODD_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_30__TX_DCOC_RES_Q_ODD_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_30__TX_DCOC_RES_I_EVEN_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_30__TX_DCOC_RES_Q_EVEN_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_30__TX_DCOC_RES_I_ODD_30___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_30__TX_DCOC_RES_I_ODD_30___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_30__TX_DCOC_RES_Q_ODD_30___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_30__TX_DCOC_RES_Q_ODD_30___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_30__TX_DCOC_RES_I_EVEN_30___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_30__TX_DCOC_RES_I_EVEN_30___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_30__TX_DCOC_RES_Q_EVEN_30___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_30__TX_DCOC_RES_Q_EVEN_30___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_30___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_30___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_31 (0x005ED87C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_31___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_31__TX_DCOC_RES_I_ODD_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_31__TX_DCOC_RES_Q_ODD_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_31__TX_DCOC_RES_I_EVEN_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_31__TX_DCOC_RES_Q_EVEN_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_31__TX_DCOC_RES_I_ODD_31___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_31__TX_DCOC_RES_I_ODD_31___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_31__TX_DCOC_RES_Q_ODD_31___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_31__TX_DCOC_RES_Q_ODD_31___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_31__TX_DCOC_RES_I_EVEN_31___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_31__TX_DCOC_RES_I_EVEN_31___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_31__TX_DCOC_RES_Q_EVEN_31___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_31__TX_DCOC_RES_Q_EVEN_31___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_31___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_31___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_32 (0x005ED880) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_32___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_32___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_32__TX_DCOC_RES_I_ODD_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_32__TX_DCOC_RES_Q_ODD_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_32__TX_DCOC_RES_I_EVEN_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_32__TX_DCOC_RES_Q_EVEN_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_32__TX_DCOC_RES_I_ODD_32___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_32__TX_DCOC_RES_I_ODD_32___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_32__TX_DCOC_RES_Q_ODD_32___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_32__TX_DCOC_RES_Q_ODD_32___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_32__TX_DCOC_RES_I_EVEN_32___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_32__TX_DCOC_RES_I_EVEN_32___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_32__TX_DCOC_RES_Q_EVEN_32___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_32__TX_DCOC_RES_Q_EVEN_32___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_32___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_32___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_33 (0x005ED884) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_33___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_33___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_33__TX_DCOC_RES_I_ODD_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_33__TX_DCOC_RES_Q_ODD_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_33__TX_DCOC_RES_I_EVEN_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_33__TX_DCOC_RES_Q_EVEN_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_33__TX_DCOC_RES_I_ODD_33___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_33__TX_DCOC_RES_I_ODD_33___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_33__TX_DCOC_RES_Q_ODD_33___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_33__TX_DCOC_RES_Q_ODD_33___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_33__TX_DCOC_RES_I_EVEN_33___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_33__TX_DCOC_RES_I_EVEN_33___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_33__TX_DCOC_RES_Q_EVEN_33___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_33__TX_DCOC_RES_Q_EVEN_33___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_33___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_33___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_34 (0x005ED888) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_34___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_34___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_34__TX_DCOC_RES_I_ODD_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_34__TX_DCOC_RES_Q_ODD_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_34__TX_DCOC_RES_I_EVEN_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_34__TX_DCOC_RES_Q_EVEN_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_34__TX_DCOC_RES_I_ODD_34___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_34__TX_DCOC_RES_I_ODD_34___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_34__TX_DCOC_RES_Q_ODD_34___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_34__TX_DCOC_RES_Q_ODD_34___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_34__TX_DCOC_RES_I_EVEN_34___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_34__TX_DCOC_RES_I_EVEN_34___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_34__TX_DCOC_RES_Q_EVEN_34___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_34__TX_DCOC_RES_Q_EVEN_34___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_34___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_34___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_35 (0x005ED88C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_35___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_35___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_35__TX_DCOC_RES_I_ODD_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_35__TX_DCOC_RES_Q_ODD_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_35__TX_DCOC_RES_I_EVEN_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_35__TX_DCOC_RES_Q_EVEN_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_35__TX_DCOC_RES_I_ODD_35___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_35__TX_DCOC_RES_I_ODD_35___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_35__TX_DCOC_RES_Q_ODD_35___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_35__TX_DCOC_RES_Q_ODD_35___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_35__TX_DCOC_RES_I_EVEN_35___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_35__TX_DCOC_RES_I_EVEN_35___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_35__TX_DCOC_RES_Q_EVEN_35___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_35__TX_DCOC_RES_Q_EVEN_35___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_35___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_35___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_36 (0x005ED890) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_36___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_36___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_36__TX_DCOC_RES_I_ODD_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_36__TX_DCOC_RES_Q_ODD_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_36__TX_DCOC_RES_I_EVEN_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_36__TX_DCOC_RES_Q_EVEN_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_36__TX_DCOC_RES_I_ODD_36___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_36__TX_DCOC_RES_I_ODD_36___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_36__TX_DCOC_RES_Q_ODD_36___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_36__TX_DCOC_RES_Q_ODD_36___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_36__TX_DCOC_RES_I_EVEN_36___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_36__TX_DCOC_RES_I_EVEN_36___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_36__TX_DCOC_RES_Q_EVEN_36___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_36__TX_DCOC_RES_Q_EVEN_36___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_36___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_36___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_37 (0x005ED894) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_37___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_37___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_37__TX_DCOC_RES_I_ODD_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_37__TX_DCOC_RES_Q_ODD_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_37__TX_DCOC_RES_I_EVEN_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_37__TX_DCOC_RES_Q_EVEN_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_37__TX_DCOC_RES_I_ODD_37___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_37__TX_DCOC_RES_I_ODD_37___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_37__TX_DCOC_RES_Q_ODD_37___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_37__TX_DCOC_RES_Q_ODD_37___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_37__TX_DCOC_RES_I_EVEN_37___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_37__TX_DCOC_RES_I_EVEN_37___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_37__TX_DCOC_RES_Q_EVEN_37___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_37__TX_DCOC_RES_Q_EVEN_37___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_37___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_37___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_38 (0x005ED898) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_38___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_38___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_38__TX_DCOC_RES_I_ODD_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_38__TX_DCOC_RES_Q_ODD_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_38__TX_DCOC_RES_I_EVEN_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_38__TX_DCOC_RES_Q_EVEN_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_38__TX_DCOC_RES_I_ODD_38___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_38__TX_DCOC_RES_I_ODD_38___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_38__TX_DCOC_RES_Q_ODD_38___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_38__TX_DCOC_RES_Q_ODD_38___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_38__TX_DCOC_RES_I_EVEN_38___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_38__TX_DCOC_RES_I_EVEN_38___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_38__TX_DCOC_RES_Q_EVEN_38___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_38__TX_DCOC_RES_Q_EVEN_38___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_38___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_38___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_39 (0x005ED89C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_39___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_39___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_39__TX_DCOC_RES_I_ODD_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_39__TX_DCOC_RES_Q_ODD_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_39__TX_DCOC_RES_I_EVEN_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_39__TX_DCOC_RES_Q_EVEN_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_39__TX_DCOC_RES_I_ODD_39___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_39__TX_DCOC_RES_I_ODD_39___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_39__TX_DCOC_RES_Q_ODD_39___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_39__TX_DCOC_RES_Q_ODD_39___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_39__TX_DCOC_RES_I_EVEN_39___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_39__TX_DCOC_RES_I_EVEN_39___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_39__TX_DCOC_RES_Q_EVEN_39___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_39__TX_DCOC_RES_Q_EVEN_39___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_39___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_39___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_40 (0x005ED8A0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_40___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_40___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_40__TX_DCOC_RES_I_ODD_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_40__TX_DCOC_RES_Q_ODD_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_40__TX_DCOC_RES_I_EVEN_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_40__TX_DCOC_RES_Q_EVEN_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_40__TX_DCOC_RES_I_ODD_40___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_40__TX_DCOC_RES_I_ODD_40___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_40__TX_DCOC_RES_Q_ODD_40___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_40__TX_DCOC_RES_Q_ODD_40___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_40__TX_DCOC_RES_I_EVEN_40___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_40__TX_DCOC_RES_I_EVEN_40___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_40__TX_DCOC_RES_Q_EVEN_40___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_40__TX_DCOC_RES_Q_EVEN_40___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_40___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_40___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_41 (0x005ED8A4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_41___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_41___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_41__TX_DCOC_RES_I_ODD_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_41__TX_DCOC_RES_Q_ODD_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_41__TX_DCOC_RES_I_EVEN_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_41__TX_DCOC_RES_Q_EVEN_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_41__TX_DCOC_RES_I_ODD_41___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_41__TX_DCOC_RES_I_ODD_41___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_41__TX_DCOC_RES_Q_ODD_41___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_41__TX_DCOC_RES_Q_ODD_41___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_41__TX_DCOC_RES_I_EVEN_41___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_41__TX_DCOC_RES_I_EVEN_41___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_41__TX_DCOC_RES_Q_EVEN_41___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_41__TX_DCOC_RES_Q_EVEN_41___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_41___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_41___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_42 (0x005ED8A8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_42___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_42___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_42__TX_DCOC_RES_I_ODD_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_42__TX_DCOC_RES_Q_ODD_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_42__TX_DCOC_RES_I_EVEN_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_42__TX_DCOC_RES_Q_EVEN_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_42__TX_DCOC_RES_I_ODD_42___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_42__TX_DCOC_RES_I_ODD_42___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_42__TX_DCOC_RES_Q_ODD_42___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_42__TX_DCOC_RES_Q_ODD_42___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_42__TX_DCOC_RES_I_EVEN_42___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_42__TX_DCOC_RES_I_EVEN_42___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_42__TX_DCOC_RES_Q_EVEN_42___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_42__TX_DCOC_RES_Q_EVEN_42___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_42___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_42___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_43 (0x005ED8AC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_43___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_43___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_43__TX_DCOC_RES_I_ODD_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_43__TX_DCOC_RES_Q_ODD_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_43__TX_DCOC_RES_I_EVEN_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_43__TX_DCOC_RES_Q_EVEN_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_43__TX_DCOC_RES_I_ODD_43___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_43__TX_DCOC_RES_I_ODD_43___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_43__TX_DCOC_RES_Q_ODD_43___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_43__TX_DCOC_RES_Q_ODD_43___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_43__TX_DCOC_RES_I_EVEN_43___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_43__TX_DCOC_RES_I_EVEN_43___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_43__TX_DCOC_RES_Q_EVEN_43___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_43__TX_DCOC_RES_Q_EVEN_43___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_43___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_43___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_44 (0x005ED8B0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_44___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_44___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_44__TX_DCOC_RES_I_ODD_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_44__TX_DCOC_RES_Q_ODD_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_44__TX_DCOC_RES_I_EVEN_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_44__TX_DCOC_RES_Q_EVEN_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_44__TX_DCOC_RES_I_ODD_44___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_44__TX_DCOC_RES_I_ODD_44___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_44__TX_DCOC_RES_Q_ODD_44___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_44__TX_DCOC_RES_Q_ODD_44___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_44__TX_DCOC_RES_I_EVEN_44___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_44__TX_DCOC_RES_I_EVEN_44___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_44__TX_DCOC_RES_Q_EVEN_44___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_44__TX_DCOC_RES_Q_EVEN_44___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_44___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_44___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_45 (0x005ED8B4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_45___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_45___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_45__TX_DCOC_RES_I_ODD_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_45__TX_DCOC_RES_Q_ODD_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_45__TX_DCOC_RES_I_EVEN_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_45__TX_DCOC_RES_Q_EVEN_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_45__TX_DCOC_RES_I_ODD_45___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_45__TX_DCOC_RES_I_ODD_45___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_45__TX_DCOC_RES_Q_ODD_45___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_45__TX_DCOC_RES_Q_ODD_45___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_45__TX_DCOC_RES_I_EVEN_45___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_45__TX_DCOC_RES_I_EVEN_45___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_45__TX_DCOC_RES_Q_EVEN_45___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_45__TX_DCOC_RES_Q_EVEN_45___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_45___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_45___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_46 (0x005ED8B8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_46___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_46___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_46__TX_DCOC_RES_I_ODD_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_46__TX_DCOC_RES_Q_ODD_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_46__TX_DCOC_RES_I_EVEN_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_46__TX_DCOC_RES_Q_EVEN_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_46__TX_DCOC_RES_I_ODD_46___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_46__TX_DCOC_RES_I_ODD_46___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_46__TX_DCOC_RES_Q_ODD_46___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_46__TX_DCOC_RES_Q_ODD_46___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_46__TX_DCOC_RES_I_EVEN_46___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_46__TX_DCOC_RES_I_EVEN_46___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_46__TX_DCOC_RES_Q_EVEN_46___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_46__TX_DCOC_RES_Q_EVEN_46___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_46___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_46___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_47 (0x005ED8BC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_47___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_47___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_47__TX_DCOC_RES_I_ODD_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_47__TX_DCOC_RES_Q_ODD_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_47__TX_DCOC_RES_I_EVEN_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_47__TX_DCOC_RES_Q_EVEN_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_47__TX_DCOC_RES_I_ODD_47___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_47__TX_DCOC_RES_I_ODD_47___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_47__TX_DCOC_RES_Q_ODD_47___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_47__TX_DCOC_RES_Q_ODD_47___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_47__TX_DCOC_RES_I_EVEN_47___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_47__TX_DCOC_RES_I_EVEN_47___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_47__TX_DCOC_RES_Q_EVEN_47___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_47__TX_DCOC_RES_Q_EVEN_47___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_47___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_47___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_48 (0x005ED8C0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_48___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_48___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_48__TX_DCOC_RES_I_ODD_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_48__TX_DCOC_RES_Q_ODD_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_48__TX_DCOC_RES_I_EVEN_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_48__TX_DCOC_RES_Q_EVEN_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_48__TX_DCOC_RES_I_ODD_48___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_48__TX_DCOC_RES_I_ODD_48___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_48__TX_DCOC_RES_Q_ODD_48___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_48__TX_DCOC_RES_Q_ODD_48___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_48__TX_DCOC_RES_I_EVEN_48___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_48__TX_DCOC_RES_I_EVEN_48___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_48__TX_DCOC_RES_Q_EVEN_48___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_48__TX_DCOC_RES_Q_EVEN_48___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_48___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_48___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_49 (0x005ED8C4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_49___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_49___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_49__TX_DCOC_RES_I_ODD_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_49__TX_DCOC_RES_Q_ODD_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_49__TX_DCOC_RES_I_EVEN_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_49__TX_DCOC_RES_Q_EVEN_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_49__TX_DCOC_RES_I_ODD_49___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_49__TX_DCOC_RES_I_ODD_49___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_49__TX_DCOC_RES_Q_ODD_49___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_49__TX_DCOC_RES_Q_ODD_49___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_49__TX_DCOC_RES_I_EVEN_49___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_49__TX_DCOC_RES_I_EVEN_49___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_49__TX_DCOC_RES_Q_EVEN_49___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_49__TX_DCOC_RES_Q_EVEN_49___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_49___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_49___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_50 (0x005ED8C8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_50___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_50___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_50__TX_DCOC_RES_I_ODD_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_50__TX_DCOC_RES_Q_ODD_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_50__TX_DCOC_RES_I_EVEN_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_50__TX_DCOC_RES_Q_EVEN_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_50__TX_DCOC_RES_I_ODD_50___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_50__TX_DCOC_RES_I_ODD_50___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_50__TX_DCOC_RES_Q_ODD_50___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_50__TX_DCOC_RES_Q_ODD_50___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_50__TX_DCOC_RES_I_EVEN_50___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_50__TX_DCOC_RES_I_EVEN_50___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_50__TX_DCOC_RES_Q_EVEN_50___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_50__TX_DCOC_RES_Q_EVEN_50___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_50___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_50___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_51 (0x005ED8CC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_51___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_51___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_51__TX_DCOC_RES_I_ODD_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_51__TX_DCOC_RES_Q_ODD_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_51__TX_DCOC_RES_I_EVEN_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_51__TX_DCOC_RES_Q_EVEN_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_51__TX_DCOC_RES_I_ODD_51___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_51__TX_DCOC_RES_I_ODD_51___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_51__TX_DCOC_RES_Q_ODD_51___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_51__TX_DCOC_RES_Q_ODD_51___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_51__TX_DCOC_RES_I_EVEN_51___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_51__TX_DCOC_RES_I_EVEN_51___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_51__TX_DCOC_RES_Q_EVEN_51___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_51__TX_DCOC_RES_Q_EVEN_51___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_51___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_51___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_52 (0x005ED8D0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_52___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_52___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_52__TX_DCOC_RES_I_ODD_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_52__TX_DCOC_RES_Q_ODD_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_52__TX_DCOC_RES_I_EVEN_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_52__TX_DCOC_RES_Q_EVEN_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_52__TX_DCOC_RES_I_ODD_52___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_52__TX_DCOC_RES_I_ODD_52___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_52__TX_DCOC_RES_Q_ODD_52___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_52__TX_DCOC_RES_Q_ODD_52___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_52__TX_DCOC_RES_I_EVEN_52___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_52__TX_DCOC_RES_I_EVEN_52___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_52__TX_DCOC_RES_Q_EVEN_52___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_52__TX_DCOC_RES_Q_EVEN_52___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_52___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_52___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_53 (0x005ED8D4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_53___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_53___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_53__TX_DCOC_RES_I_ODD_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_53__TX_DCOC_RES_Q_ODD_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_53__TX_DCOC_RES_I_EVEN_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_53__TX_DCOC_RES_Q_EVEN_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_53__TX_DCOC_RES_I_ODD_53___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_53__TX_DCOC_RES_I_ODD_53___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_53__TX_DCOC_RES_Q_ODD_53___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_53__TX_DCOC_RES_Q_ODD_53___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_53__TX_DCOC_RES_I_EVEN_53___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_53__TX_DCOC_RES_I_EVEN_53___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_53__TX_DCOC_RES_Q_EVEN_53___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_53__TX_DCOC_RES_Q_EVEN_53___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_53___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_53___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_54 (0x005ED8D8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_54___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_54___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_54__TX_DCOC_RES_I_ODD_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_54__TX_DCOC_RES_Q_ODD_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_54__TX_DCOC_RES_I_EVEN_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_54__TX_DCOC_RES_Q_EVEN_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_54__TX_DCOC_RES_I_ODD_54___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_54__TX_DCOC_RES_I_ODD_54___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_54__TX_DCOC_RES_Q_ODD_54___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_54__TX_DCOC_RES_Q_ODD_54___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_54__TX_DCOC_RES_I_EVEN_54___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_54__TX_DCOC_RES_I_EVEN_54___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_54__TX_DCOC_RES_Q_EVEN_54___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_54__TX_DCOC_RES_Q_EVEN_54___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_54___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_54___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_55 (0x005ED8DC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_55___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_55___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_55__TX_DCOC_RES_I_ODD_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_55__TX_DCOC_RES_Q_ODD_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_55__TX_DCOC_RES_I_EVEN_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_55__TX_DCOC_RES_Q_EVEN_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_55__TX_DCOC_RES_I_ODD_55___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_55__TX_DCOC_RES_I_ODD_55___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_55__TX_DCOC_RES_Q_ODD_55___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_55__TX_DCOC_RES_Q_ODD_55___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_55__TX_DCOC_RES_I_EVEN_55___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_55__TX_DCOC_RES_I_EVEN_55___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_55__TX_DCOC_RES_Q_EVEN_55___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_55__TX_DCOC_RES_Q_EVEN_55___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_55___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_55___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_56 (0x005ED8E0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_56___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_56___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_56__TX_DCOC_RES_I_ODD_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_56__TX_DCOC_RES_Q_ODD_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_56__TX_DCOC_RES_I_EVEN_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_56__TX_DCOC_RES_Q_EVEN_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_56__TX_DCOC_RES_I_ODD_56___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_56__TX_DCOC_RES_I_ODD_56___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_56__TX_DCOC_RES_Q_ODD_56___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_56__TX_DCOC_RES_Q_ODD_56___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_56__TX_DCOC_RES_I_EVEN_56___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_56__TX_DCOC_RES_I_EVEN_56___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_56__TX_DCOC_RES_Q_EVEN_56___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_56__TX_DCOC_RES_Q_EVEN_56___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_56___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_56___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_57 (0x005ED8E4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_57___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_57___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_57__TX_DCOC_RES_I_ODD_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_57__TX_DCOC_RES_Q_ODD_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_57__TX_DCOC_RES_I_EVEN_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_57__TX_DCOC_RES_Q_EVEN_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_57__TX_DCOC_RES_I_ODD_57___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_57__TX_DCOC_RES_I_ODD_57___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_57__TX_DCOC_RES_Q_ODD_57___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_57__TX_DCOC_RES_Q_ODD_57___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_57__TX_DCOC_RES_I_EVEN_57___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_57__TX_DCOC_RES_I_EVEN_57___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_57__TX_DCOC_RES_Q_EVEN_57___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_57__TX_DCOC_RES_Q_EVEN_57___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_57___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_57___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_58 (0x005ED8E8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_58___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_58___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_58__TX_DCOC_RES_I_ODD_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_58__TX_DCOC_RES_Q_ODD_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_58__TX_DCOC_RES_I_EVEN_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_58__TX_DCOC_RES_Q_EVEN_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_58__TX_DCOC_RES_I_ODD_58___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_58__TX_DCOC_RES_I_ODD_58___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_58__TX_DCOC_RES_Q_ODD_58___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_58__TX_DCOC_RES_Q_ODD_58___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_58__TX_DCOC_RES_I_EVEN_58___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_58__TX_DCOC_RES_I_EVEN_58___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_58__TX_DCOC_RES_Q_EVEN_58___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_58__TX_DCOC_RES_Q_EVEN_58___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_58___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_58___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_59 (0x005ED8EC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_59___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_59___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_59__TX_DCOC_RES_I_ODD_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_59__TX_DCOC_RES_Q_ODD_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_59__TX_DCOC_RES_I_EVEN_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_59__TX_DCOC_RES_Q_EVEN_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_59__TX_DCOC_RES_I_ODD_59___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_59__TX_DCOC_RES_I_ODD_59___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_59__TX_DCOC_RES_Q_ODD_59___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_59__TX_DCOC_RES_Q_ODD_59___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_59__TX_DCOC_RES_I_EVEN_59___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_59__TX_DCOC_RES_I_EVEN_59___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_59__TX_DCOC_RES_Q_EVEN_59___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_59__TX_DCOC_RES_Q_EVEN_59___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_59___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_59___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_60 (0x005ED8F0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_60___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_60___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_60__TX_DCOC_RES_I_ODD_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_60__TX_DCOC_RES_Q_ODD_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_60__TX_DCOC_RES_I_EVEN_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_60__TX_DCOC_RES_Q_EVEN_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_60__TX_DCOC_RES_I_ODD_60___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_60__TX_DCOC_RES_I_ODD_60___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_60__TX_DCOC_RES_Q_ODD_60___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_60__TX_DCOC_RES_Q_ODD_60___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_60__TX_DCOC_RES_I_EVEN_60___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_60__TX_DCOC_RES_I_EVEN_60___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_60__TX_DCOC_RES_Q_EVEN_60___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_60__TX_DCOC_RES_Q_EVEN_60___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_60___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_60___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_61 (0x005ED8F4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_61___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_61___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_61__TX_DCOC_RES_I_ODD_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_61__TX_DCOC_RES_Q_ODD_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_61__TX_DCOC_RES_I_EVEN_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_61__TX_DCOC_RES_Q_EVEN_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_61__TX_DCOC_RES_I_ODD_61___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_61__TX_DCOC_RES_I_ODD_61___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_61__TX_DCOC_RES_Q_ODD_61___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_61__TX_DCOC_RES_Q_ODD_61___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_61__TX_DCOC_RES_I_EVEN_61___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_61__TX_DCOC_RES_I_EVEN_61___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_61__TX_DCOC_RES_Q_EVEN_61___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_61__TX_DCOC_RES_Q_EVEN_61___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_61___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_61___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_62 (0x005ED8F8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_62___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_62___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_62__TX_DCOC_RES_I_ODD_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_62__TX_DCOC_RES_Q_ODD_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_62__TX_DCOC_RES_I_EVEN_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_62__TX_DCOC_RES_Q_EVEN_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_62__TX_DCOC_RES_I_ODD_62___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_62__TX_DCOC_RES_I_ODD_62___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_62__TX_DCOC_RES_Q_ODD_62___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_62__TX_DCOC_RES_Q_ODD_62___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_62__TX_DCOC_RES_I_EVEN_62___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_62__TX_DCOC_RES_I_EVEN_62___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_62__TX_DCOC_RES_Q_EVEN_62___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_62__TX_DCOC_RES_Q_EVEN_62___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_62___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_62___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_63 (0x005ED8FC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_63___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_63___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_63__TX_DCOC_RES_I_ODD_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_63__TX_DCOC_RES_Q_ODD_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_63__TX_DCOC_RES_I_EVEN_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_63__TX_DCOC_RES_Q_EVEN_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_63__TX_DCOC_RES_I_ODD_63___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_63__TX_DCOC_RES_I_ODD_63___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_63__TX_DCOC_RES_Q_ODD_63___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_63__TX_DCOC_RES_Q_ODD_63___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_63__TX_DCOC_RES_I_EVEN_63___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_63__TX_DCOC_RES_I_EVEN_63___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_63__TX_DCOC_RES_Q_EVEN_63___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_63__TX_DCOC_RES_Q_EVEN_63___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_63___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_63___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_64 (0x005ED900) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_64___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_64___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_64__TX_DCOC_RES_I_ODD_64___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_64__TX_DCOC_RES_Q_ODD_64___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_64__TX_DCOC_RES_I_EVEN_64___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_64__TX_DCOC_RES_Q_EVEN_64___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_64__TX_DCOC_RES_I_ODD_64___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_64__TX_DCOC_RES_I_ODD_64___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_64__TX_DCOC_RES_Q_ODD_64___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_64__TX_DCOC_RES_Q_ODD_64___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_64__TX_DCOC_RES_I_EVEN_64___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_64__TX_DCOC_RES_I_EVEN_64___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_64__TX_DCOC_RES_Q_EVEN_64___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_64__TX_DCOC_RES_Q_EVEN_64___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_64___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_64___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_65 (0x005ED904) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_65___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_65___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_65__TX_DCOC_RES_I_ODD_65___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_65__TX_DCOC_RES_Q_ODD_65___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_65__TX_DCOC_RES_I_EVEN_65___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_65__TX_DCOC_RES_Q_EVEN_65___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_65__TX_DCOC_RES_I_ODD_65___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_65__TX_DCOC_RES_I_ODD_65___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_65__TX_DCOC_RES_Q_ODD_65___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_65__TX_DCOC_RES_Q_ODD_65___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_65__TX_DCOC_RES_I_EVEN_65___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_65__TX_DCOC_RES_I_EVEN_65___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_65__TX_DCOC_RES_Q_EVEN_65___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_65__TX_DCOC_RES_Q_EVEN_65___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_65___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_65___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_66 (0x005ED908) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_66___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_66___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_66__TX_DCOC_RES_I_ODD_66___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_66__TX_DCOC_RES_Q_ODD_66___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_66__TX_DCOC_RES_I_EVEN_66___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_66__TX_DCOC_RES_Q_EVEN_66___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_66__TX_DCOC_RES_I_ODD_66___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_66__TX_DCOC_RES_I_ODD_66___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_66__TX_DCOC_RES_Q_ODD_66___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_66__TX_DCOC_RES_Q_ODD_66___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_66__TX_DCOC_RES_I_EVEN_66___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_66__TX_DCOC_RES_I_EVEN_66___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_66__TX_DCOC_RES_Q_EVEN_66___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_66__TX_DCOC_RES_Q_EVEN_66___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_66___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_66___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_67 (0x005ED90C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_67___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_67___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_67__TX_DCOC_RES_I_ODD_67___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_67__TX_DCOC_RES_Q_ODD_67___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_67__TX_DCOC_RES_I_EVEN_67___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_67__TX_DCOC_RES_Q_EVEN_67___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_67__TX_DCOC_RES_I_ODD_67___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_67__TX_DCOC_RES_I_ODD_67___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_67__TX_DCOC_RES_Q_ODD_67___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_67__TX_DCOC_RES_Q_ODD_67___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_67__TX_DCOC_RES_I_EVEN_67___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_67__TX_DCOC_RES_I_EVEN_67___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_67__TX_DCOC_RES_Q_EVEN_67___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_67__TX_DCOC_RES_Q_EVEN_67___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_67___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_67___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_68 (0x005ED910) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_68___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_68___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_68__TX_DCOC_RES_I_ODD_68___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_68__TX_DCOC_RES_Q_ODD_68___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_68__TX_DCOC_RES_I_EVEN_68___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_68__TX_DCOC_RES_Q_EVEN_68___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_68__TX_DCOC_RES_I_ODD_68___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_68__TX_DCOC_RES_I_ODD_68___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_68__TX_DCOC_RES_Q_ODD_68___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_68__TX_DCOC_RES_Q_ODD_68___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_68__TX_DCOC_RES_I_EVEN_68___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_68__TX_DCOC_RES_I_EVEN_68___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_68__TX_DCOC_RES_Q_EVEN_68___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_68__TX_DCOC_RES_Q_EVEN_68___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_68___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_68___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_69 (0x005ED914) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_69___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_69___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_69__TX_DCOC_RES_I_ODD_69___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_69__TX_DCOC_RES_Q_ODD_69___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_69__TX_DCOC_RES_I_EVEN_69___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_69__TX_DCOC_RES_Q_EVEN_69___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_69__TX_DCOC_RES_I_ODD_69___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_69__TX_DCOC_RES_I_ODD_69___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_69__TX_DCOC_RES_Q_ODD_69___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_69__TX_DCOC_RES_Q_ODD_69___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_69__TX_DCOC_RES_I_EVEN_69___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_69__TX_DCOC_RES_I_EVEN_69___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_69__TX_DCOC_RES_Q_EVEN_69___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_69__TX_DCOC_RES_Q_EVEN_69___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_69___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_69___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_70 (0x005ED918) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_70___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_70___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_70__TX_DCOC_RES_I_ODD_70___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_70__TX_DCOC_RES_Q_ODD_70___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_70__TX_DCOC_RES_I_EVEN_70___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_70__TX_DCOC_RES_Q_EVEN_70___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_70__TX_DCOC_RES_I_ODD_70___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_70__TX_DCOC_RES_I_ODD_70___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_70__TX_DCOC_RES_Q_ODD_70___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_70__TX_DCOC_RES_Q_ODD_70___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_70__TX_DCOC_RES_I_EVEN_70___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_70__TX_DCOC_RES_I_EVEN_70___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_70__TX_DCOC_RES_Q_EVEN_70___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_70__TX_DCOC_RES_Q_EVEN_70___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_70___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_70___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_71 (0x005ED91C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_71___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_71___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_71__TX_DCOC_RES_I_ODD_71___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_71__TX_DCOC_RES_Q_ODD_71___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_71__TX_DCOC_RES_I_EVEN_71___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_71__TX_DCOC_RES_Q_EVEN_71___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_71__TX_DCOC_RES_I_ODD_71___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_71__TX_DCOC_RES_I_ODD_71___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_71__TX_DCOC_RES_Q_ODD_71___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_71__TX_DCOC_RES_Q_ODD_71___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_71__TX_DCOC_RES_I_EVEN_71___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_71__TX_DCOC_RES_I_EVEN_71___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_71__TX_DCOC_RES_Q_EVEN_71___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_71__TX_DCOC_RES_Q_EVEN_71___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_71___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_71___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_72 (0x005ED920) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_72___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_72___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_72__TX_DCOC_RES_I_ODD_72___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_72__TX_DCOC_RES_Q_ODD_72___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_72__TX_DCOC_RES_I_EVEN_72___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_72__TX_DCOC_RES_Q_EVEN_72___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_72__TX_DCOC_RES_I_ODD_72___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_72__TX_DCOC_RES_I_ODD_72___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_72__TX_DCOC_RES_Q_ODD_72___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_72__TX_DCOC_RES_Q_ODD_72___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_72__TX_DCOC_RES_I_EVEN_72___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_72__TX_DCOC_RES_I_EVEN_72___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_72__TX_DCOC_RES_Q_EVEN_72___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_72__TX_DCOC_RES_Q_EVEN_72___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_72___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_72___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_73 (0x005ED924) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_73___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_73___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_73__TX_DCOC_RES_I_ODD_73___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_73__TX_DCOC_RES_Q_ODD_73___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_73__TX_DCOC_RES_I_EVEN_73___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_73__TX_DCOC_RES_Q_EVEN_73___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_73__TX_DCOC_RES_I_ODD_73___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_73__TX_DCOC_RES_I_ODD_73___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_73__TX_DCOC_RES_Q_ODD_73___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_73__TX_DCOC_RES_Q_ODD_73___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_73__TX_DCOC_RES_I_EVEN_73___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_73__TX_DCOC_RES_I_EVEN_73___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_73__TX_DCOC_RES_Q_EVEN_73___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_73__TX_DCOC_RES_Q_EVEN_73___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_73___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_73___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_74 (0x005ED928) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_74___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_74___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_74__TX_DCOC_RES_I_ODD_74___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_74__TX_DCOC_RES_Q_ODD_74___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_74__TX_DCOC_RES_I_EVEN_74___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_74__TX_DCOC_RES_Q_EVEN_74___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_74__TX_DCOC_RES_I_ODD_74___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_74__TX_DCOC_RES_I_ODD_74___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_74__TX_DCOC_RES_Q_ODD_74___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_74__TX_DCOC_RES_Q_ODD_74___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_74__TX_DCOC_RES_I_EVEN_74___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_74__TX_DCOC_RES_I_EVEN_74___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_74__TX_DCOC_RES_Q_EVEN_74___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_74__TX_DCOC_RES_Q_EVEN_74___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_74___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_74___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_75 (0x005ED92C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_75___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_75___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_75__TX_DCOC_RES_I_ODD_75___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_75__TX_DCOC_RES_Q_ODD_75___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_75__TX_DCOC_RES_I_EVEN_75___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_75__TX_DCOC_RES_Q_EVEN_75___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_75__TX_DCOC_RES_I_ODD_75___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_75__TX_DCOC_RES_I_ODD_75___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_75__TX_DCOC_RES_Q_ODD_75___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_75__TX_DCOC_RES_Q_ODD_75___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_75__TX_DCOC_RES_I_EVEN_75___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_75__TX_DCOC_RES_I_EVEN_75___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_75__TX_DCOC_RES_Q_EVEN_75___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_75__TX_DCOC_RES_Q_EVEN_75___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_75___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_75___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_76 (0x005ED930) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_76___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_76___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_76__TX_DCOC_RES_I_ODD_76___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_76__TX_DCOC_RES_Q_ODD_76___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_76__TX_DCOC_RES_I_EVEN_76___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_76__TX_DCOC_RES_Q_EVEN_76___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_76__TX_DCOC_RES_I_ODD_76___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_76__TX_DCOC_RES_I_ODD_76___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_76__TX_DCOC_RES_Q_ODD_76___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_76__TX_DCOC_RES_Q_ODD_76___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_76__TX_DCOC_RES_I_EVEN_76___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_76__TX_DCOC_RES_I_EVEN_76___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_76__TX_DCOC_RES_Q_EVEN_76___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_76__TX_DCOC_RES_Q_EVEN_76___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_76___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_76___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_77 (0x005ED934) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_77___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_77___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_77__TX_DCOC_RES_I_ODD_77___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_77__TX_DCOC_RES_Q_ODD_77___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_77__TX_DCOC_RES_I_EVEN_77___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_77__TX_DCOC_RES_Q_EVEN_77___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_77__TX_DCOC_RES_I_ODD_77___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_77__TX_DCOC_RES_I_ODD_77___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_77__TX_DCOC_RES_Q_ODD_77___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_77__TX_DCOC_RES_Q_ODD_77___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_77__TX_DCOC_RES_I_EVEN_77___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_77__TX_DCOC_RES_I_EVEN_77___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_77__TX_DCOC_RES_Q_EVEN_77___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_77__TX_DCOC_RES_Q_EVEN_77___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_77___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_77___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_78 (0x005ED938) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_78___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_78___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_78__TX_DCOC_RES_I_ODD_78___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_78__TX_DCOC_RES_Q_ODD_78___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_78__TX_DCOC_RES_I_EVEN_78___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_78__TX_DCOC_RES_Q_EVEN_78___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_78__TX_DCOC_RES_I_ODD_78___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_78__TX_DCOC_RES_I_ODD_78___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_78__TX_DCOC_RES_Q_ODD_78___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_78__TX_DCOC_RES_Q_ODD_78___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_78__TX_DCOC_RES_I_EVEN_78___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_78__TX_DCOC_RES_I_EVEN_78___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_78__TX_DCOC_RES_Q_EVEN_78___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_78__TX_DCOC_RES_Q_EVEN_78___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_78___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_78___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_79 (0x005ED93C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_79___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_79___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_79__TX_DCOC_RES_I_ODD_79___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_79__TX_DCOC_RES_Q_ODD_79___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_79__TX_DCOC_RES_I_EVEN_79___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_79__TX_DCOC_RES_Q_EVEN_79___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_79__TX_DCOC_RES_I_ODD_79___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_79__TX_DCOC_RES_I_ODD_79___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_79__TX_DCOC_RES_Q_ODD_79___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_79__TX_DCOC_RES_Q_ODD_79___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_79__TX_DCOC_RES_I_EVEN_79___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_79__TX_DCOC_RES_I_EVEN_79___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_79__TX_DCOC_RES_Q_EVEN_79___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_79__TX_DCOC_RES_Q_EVEN_79___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_79___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_79___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_80 (0x005ED940) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_80___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_80___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_80__TX_DCOC_RES_I_ODD_80___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_80__TX_DCOC_RES_Q_ODD_80___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_80__TX_DCOC_RES_I_EVEN_80___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_80__TX_DCOC_RES_Q_EVEN_80___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_80__TX_DCOC_RES_I_ODD_80___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_80__TX_DCOC_RES_I_ODD_80___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_80__TX_DCOC_RES_Q_ODD_80___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_80__TX_DCOC_RES_Q_ODD_80___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_80__TX_DCOC_RES_I_EVEN_80___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_80__TX_DCOC_RES_I_EVEN_80___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_80__TX_DCOC_RES_Q_EVEN_80___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_80__TX_DCOC_RES_Q_EVEN_80___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_80___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_80___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_81 (0x005ED944) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_81___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_81___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_81__TX_DCOC_RES_I_ODD_81___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_81__TX_DCOC_RES_Q_ODD_81___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_81__TX_DCOC_RES_I_EVEN_81___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_81__TX_DCOC_RES_Q_EVEN_81___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_81__TX_DCOC_RES_I_ODD_81___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_81__TX_DCOC_RES_I_ODD_81___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_81__TX_DCOC_RES_Q_ODD_81___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_81__TX_DCOC_RES_Q_ODD_81___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_81__TX_DCOC_RES_I_EVEN_81___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_81__TX_DCOC_RES_I_EVEN_81___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_81__TX_DCOC_RES_Q_EVEN_81___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_81__TX_DCOC_RES_Q_EVEN_81___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_81___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_81___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_82 (0x005ED948) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_82___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_82___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_82__TX_DCOC_RES_I_ODD_82___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_82__TX_DCOC_RES_Q_ODD_82___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_82__TX_DCOC_RES_I_EVEN_82___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_82__TX_DCOC_RES_Q_EVEN_82___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_82__TX_DCOC_RES_I_ODD_82___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_82__TX_DCOC_RES_I_ODD_82___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_82__TX_DCOC_RES_Q_ODD_82___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_82__TX_DCOC_RES_Q_ODD_82___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_82__TX_DCOC_RES_I_EVEN_82___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_82__TX_DCOC_RES_I_EVEN_82___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_82__TX_DCOC_RES_Q_EVEN_82___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_82__TX_DCOC_RES_Q_EVEN_82___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_82___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_82___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_83 (0x005ED94C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_83___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_83___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_83__TX_DCOC_RES_I_ODD_83___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_83__TX_DCOC_RES_Q_ODD_83___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_83__TX_DCOC_RES_I_EVEN_83___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_83__TX_DCOC_RES_Q_EVEN_83___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_83__TX_DCOC_RES_I_ODD_83___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_83__TX_DCOC_RES_I_ODD_83___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_83__TX_DCOC_RES_Q_ODD_83___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_83__TX_DCOC_RES_Q_ODD_83___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_83__TX_DCOC_RES_I_EVEN_83___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_83__TX_DCOC_RES_I_EVEN_83___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_83__TX_DCOC_RES_Q_EVEN_83___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_83__TX_DCOC_RES_Q_EVEN_83___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_83___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_83___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_84 (0x005ED950) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_84___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_84___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_84__TX_DCOC_RES_I_ODD_84___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_84__TX_DCOC_RES_Q_ODD_84___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_84__TX_DCOC_RES_I_EVEN_84___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_84__TX_DCOC_RES_Q_EVEN_84___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_84__TX_DCOC_RES_I_ODD_84___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_84__TX_DCOC_RES_I_ODD_84___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_84__TX_DCOC_RES_Q_ODD_84___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_84__TX_DCOC_RES_Q_ODD_84___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_84__TX_DCOC_RES_I_EVEN_84___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_84__TX_DCOC_RES_I_EVEN_84___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_84__TX_DCOC_RES_Q_EVEN_84___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_84__TX_DCOC_RES_Q_EVEN_84___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_84___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_84___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_85 (0x005ED954) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_85___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_85___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_85__TX_DCOC_RES_I_ODD_85___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_85__TX_DCOC_RES_Q_ODD_85___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_85__TX_DCOC_RES_I_EVEN_85___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_85__TX_DCOC_RES_Q_EVEN_85___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_85__TX_DCOC_RES_I_ODD_85___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_85__TX_DCOC_RES_I_ODD_85___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_85__TX_DCOC_RES_Q_ODD_85___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_85__TX_DCOC_RES_Q_ODD_85___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_85__TX_DCOC_RES_I_EVEN_85___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_85__TX_DCOC_RES_I_EVEN_85___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_85__TX_DCOC_RES_Q_EVEN_85___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_85__TX_DCOC_RES_Q_EVEN_85___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_85___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_85___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_86 (0x005ED958) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_86___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_86___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_86__TX_DCOC_RES_I_ODD_86___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_86__TX_DCOC_RES_Q_ODD_86___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_86__TX_DCOC_RES_I_EVEN_86___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_86__TX_DCOC_RES_Q_EVEN_86___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_86__TX_DCOC_RES_I_ODD_86___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_86__TX_DCOC_RES_I_ODD_86___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_86__TX_DCOC_RES_Q_ODD_86___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_86__TX_DCOC_RES_Q_ODD_86___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_86__TX_DCOC_RES_I_EVEN_86___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_86__TX_DCOC_RES_I_EVEN_86___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_86__TX_DCOC_RES_Q_EVEN_86___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_86__TX_DCOC_RES_Q_EVEN_86___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_86___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_86___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_87 (0x005ED95C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_87___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_87___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_87__TX_DCOC_RES_I_ODD_87___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_87__TX_DCOC_RES_Q_ODD_87___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_87__TX_DCOC_RES_I_EVEN_87___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_87__TX_DCOC_RES_Q_EVEN_87___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_87__TX_DCOC_RES_I_ODD_87___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_87__TX_DCOC_RES_I_ODD_87___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_87__TX_DCOC_RES_Q_ODD_87___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_87__TX_DCOC_RES_Q_ODD_87___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_87__TX_DCOC_RES_I_EVEN_87___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_87__TX_DCOC_RES_I_EVEN_87___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_87__TX_DCOC_RES_Q_EVEN_87___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_87__TX_DCOC_RES_Q_EVEN_87___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_87___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_87___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_88 (0x005ED960) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_88___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_88___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_88__TX_DCOC_RES_I_ODD_88___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_88__TX_DCOC_RES_Q_ODD_88___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_88__TX_DCOC_RES_I_EVEN_88___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_88__TX_DCOC_RES_Q_EVEN_88___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_88__TX_DCOC_RES_I_ODD_88___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_88__TX_DCOC_RES_I_ODD_88___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_88__TX_DCOC_RES_Q_ODD_88___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_88__TX_DCOC_RES_Q_ODD_88___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_88__TX_DCOC_RES_I_EVEN_88___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_88__TX_DCOC_RES_I_EVEN_88___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_88__TX_DCOC_RES_Q_EVEN_88___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_88__TX_DCOC_RES_Q_EVEN_88___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_88___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_88___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_89 (0x005ED964) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_89___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_89___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_89__TX_DCOC_RES_I_ODD_89___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_89__TX_DCOC_RES_Q_ODD_89___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_89__TX_DCOC_RES_I_EVEN_89___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_89__TX_DCOC_RES_Q_EVEN_89___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_89__TX_DCOC_RES_I_ODD_89___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_89__TX_DCOC_RES_I_ODD_89___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_89__TX_DCOC_RES_Q_ODD_89___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_89__TX_DCOC_RES_Q_ODD_89___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_89__TX_DCOC_RES_I_EVEN_89___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_89__TX_DCOC_RES_I_EVEN_89___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_89__TX_DCOC_RES_Q_EVEN_89___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_89__TX_DCOC_RES_Q_EVEN_89___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_89___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_89___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_90 (0x005ED968) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_90___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_90___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_90__TX_DCOC_RES_I_ODD_90___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_90__TX_DCOC_RES_Q_ODD_90___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_90__TX_DCOC_RES_I_EVEN_90___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_90__TX_DCOC_RES_Q_EVEN_90___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_90__TX_DCOC_RES_I_ODD_90___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_90__TX_DCOC_RES_I_ODD_90___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_90__TX_DCOC_RES_Q_ODD_90___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_90__TX_DCOC_RES_Q_ODD_90___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_90__TX_DCOC_RES_I_EVEN_90___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_90__TX_DCOC_RES_I_EVEN_90___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_90__TX_DCOC_RES_Q_EVEN_90___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_90__TX_DCOC_RES_Q_EVEN_90___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_90___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_90___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_91 (0x005ED96C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_91___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_91___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_91__TX_DCOC_RES_I_ODD_91___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_91__TX_DCOC_RES_Q_ODD_91___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_91__TX_DCOC_RES_I_EVEN_91___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_91__TX_DCOC_RES_Q_EVEN_91___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_91__TX_DCOC_RES_I_ODD_91___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_91__TX_DCOC_RES_I_ODD_91___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_91__TX_DCOC_RES_Q_ODD_91___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_91__TX_DCOC_RES_Q_ODD_91___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_91__TX_DCOC_RES_I_EVEN_91___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_91__TX_DCOC_RES_I_EVEN_91___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_91__TX_DCOC_RES_Q_EVEN_91___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_91__TX_DCOC_RES_Q_EVEN_91___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_91___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_91___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_92 (0x005ED970) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_92___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_92___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_92__TX_DCOC_RES_I_ODD_92___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_92__TX_DCOC_RES_Q_ODD_92___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_92__TX_DCOC_RES_I_EVEN_92___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_92__TX_DCOC_RES_Q_EVEN_92___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_92__TX_DCOC_RES_I_ODD_92___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_92__TX_DCOC_RES_I_ODD_92___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_92__TX_DCOC_RES_Q_ODD_92___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_92__TX_DCOC_RES_Q_ODD_92___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_92__TX_DCOC_RES_I_EVEN_92___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_92__TX_DCOC_RES_I_EVEN_92___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_92__TX_DCOC_RES_Q_EVEN_92___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_92__TX_DCOC_RES_Q_EVEN_92___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_92___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_92___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_93 (0x005ED974) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_93___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_93___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_93__TX_DCOC_RES_I_ODD_93___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_93__TX_DCOC_RES_Q_ODD_93___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_93__TX_DCOC_RES_I_EVEN_93___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_93__TX_DCOC_RES_Q_EVEN_93___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_93__TX_DCOC_RES_I_ODD_93___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_93__TX_DCOC_RES_I_ODD_93___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_93__TX_DCOC_RES_Q_ODD_93___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_93__TX_DCOC_RES_Q_ODD_93___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_93__TX_DCOC_RES_I_EVEN_93___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_93__TX_DCOC_RES_I_EVEN_93___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_93__TX_DCOC_RES_Q_EVEN_93___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_93__TX_DCOC_RES_Q_EVEN_93___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_93___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_93___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_94 (0x005ED978) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_94___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_94___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_94__TX_DCOC_RES_I_ODD_94___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_94__TX_DCOC_RES_Q_ODD_94___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_94__TX_DCOC_RES_I_EVEN_94___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_94__TX_DCOC_RES_Q_EVEN_94___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_94__TX_DCOC_RES_I_ODD_94___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_94__TX_DCOC_RES_I_ODD_94___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_94__TX_DCOC_RES_Q_ODD_94___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_94__TX_DCOC_RES_Q_ODD_94___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_94__TX_DCOC_RES_I_EVEN_94___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_94__TX_DCOC_RES_I_EVEN_94___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_94__TX_DCOC_RES_Q_EVEN_94___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_94__TX_DCOC_RES_Q_EVEN_94___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_94___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_94___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_95 (0x005ED97C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_95___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_95___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_95__TX_DCOC_RES_I_ODD_95___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_95__TX_DCOC_RES_Q_ODD_95___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_95__TX_DCOC_RES_I_EVEN_95___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_95__TX_DCOC_RES_Q_EVEN_95___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_95__TX_DCOC_RES_I_ODD_95___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_95__TX_DCOC_RES_I_ODD_95___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_95__TX_DCOC_RES_Q_ODD_95___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_95__TX_DCOC_RES_Q_ODD_95___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_95__TX_DCOC_RES_I_EVEN_95___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_95__TX_DCOC_RES_I_EVEN_95___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_95__TX_DCOC_RES_Q_EVEN_95___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_95__TX_DCOC_RES_Q_EVEN_95___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_95___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_95___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_96 (0x005ED980) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_96___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_96___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_96__TX_DCOC_RES_I_ODD_96___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_96__TX_DCOC_RES_Q_ODD_96___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_96__TX_DCOC_RES_I_EVEN_96___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_96__TX_DCOC_RES_Q_EVEN_96___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_96__TX_DCOC_RES_I_ODD_96___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_96__TX_DCOC_RES_I_ODD_96___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_96__TX_DCOC_RES_Q_ODD_96___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_96__TX_DCOC_RES_Q_ODD_96___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_96__TX_DCOC_RES_I_EVEN_96___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_96__TX_DCOC_RES_I_EVEN_96___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_96__TX_DCOC_RES_Q_EVEN_96___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_96__TX_DCOC_RES_Q_EVEN_96___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_96___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_96___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_97 (0x005ED984) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_97___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_97___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_97__TX_DCOC_RES_I_ODD_97___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_97__TX_DCOC_RES_Q_ODD_97___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_97__TX_DCOC_RES_I_EVEN_97___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_97__TX_DCOC_RES_Q_EVEN_97___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_97__TX_DCOC_RES_I_ODD_97___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_97__TX_DCOC_RES_I_ODD_97___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_97__TX_DCOC_RES_Q_ODD_97___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_97__TX_DCOC_RES_Q_ODD_97___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_97__TX_DCOC_RES_I_EVEN_97___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_97__TX_DCOC_RES_I_EVEN_97___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_97__TX_DCOC_RES_Q_EVEN_97___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_97__TX_DCOC_RES_Q_EVEN_97___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_97___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_97___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_98 (0x005ED988) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_98___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_98___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_98__TX_DCOC_RES_I_ODD_98___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_98__TX_DCOC_RES_Q_ODD_98___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_98__TX_DCOC_RES_I_EVEN_98___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_98__TX_DCOC_RES_Q_EVEN_98___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_98__TX_DCOC_RES_I_ODD_98___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_98__TX_DCOC_RES_I_ODD_98___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_98__TX_DCOC_RES_Q_ODD_98___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_98__TX_DCOC_RES_Q_ODD_98___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_98__TX_DCOC_RES_I_EVEN_98___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_98__TX_DCOC_RES_I_EVEN_98___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_98__TX_DCOC_RES_Q_EVEN_98___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_98__TX_DCOC_RES_Q_EVEN_98___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_98___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_98___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_99 (0x005ED98C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_99___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_99___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_99__TX_DCOC_RES_I_ODD_99___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_99__TX_DCOC_RES_Q_ODD_99___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_99__TX_DCOC_RES_I_EVEN_99___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_99__TX_DCOC_RES_Q_EVEN_99___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_99__TX_DCOC_RES_I_ODD_99___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_99__TX_DCOC_RES_I_ODD_99___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_99__TX_DCOC_RES_Q_ODD_99___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_99__TX_DCOC_RES_Q_ODD_99___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_99__TX_DCOC_RES_I_EVEN_99___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_99__TX_DCOC_RES_I_EVEN_99___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_99__TX_DCOC_RES_Q_EVEN_99___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_99__TX_DCOC_RES_Q_EVEN_99___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_99___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_99___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_100 (0x005ED990) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_100___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_100___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_100__TX_DCOC_RES_I_ODD_100___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_100__TX_DCOC_RES_Q_ODD_100___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_100__TX_DCOC_RES_I_EVEN_100___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_100__TX_DCOC_RES_Q_EVEN_100___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_100__TX_DCOC_RES_I_ODD_100___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_100__TX_DCOC_RES_I_ODD_100___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_100__TX_DCOC_RES_Q_ODD_100___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_100__TX_DCOC_RES_Q_ODD_100___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_100__TX_DCOC_RES_I_EVEN_100___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_100__TX_DCOC_RES_I_EVEN_100___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_100__TX_DCOC_RES_Q_EVEN_100___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_100__TX_DCOC_RES_Q_EVEN_100___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_100___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_100___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_101 (0x005ED994) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_101___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_101___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_101__TX_DCOC_RES_I_ODD_101___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_101__TX_DCOC_RES_Q_ODD_101___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_101__TX_DCOC_RES_I_EVEN_101___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_101__TX_DCOC_RES_Q_EVEN_101___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_101__TX_DCOC_RES_I_ODD_101___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_101__TX_DCOC_RES_I_ODD_101___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_101__TX_DCOC_RES_Q_ODD_101___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_101__TX_DCOC_RES_Q_ODD_101___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_101__TX_DCOC_RES_I_EVEN_101___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_101__TX_DCOC_RES_I_EVEN_101___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_101__TX_DCOC_RES_Q_EVEN_101___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_101__TX_DCOC_RES_Q_EVEN_101___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_101___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_101___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_102 (0x005ED998) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_102___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_102___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_102__TX_DCOC_RES_I_ODD_102___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_102__TX_DCOC_RES_Q_ODD_102___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_102__TX_DCOC_RES_I_EVEN_102___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_102__TX_DCOC_RES_Q_EVEN_102___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_102__TX_DCOC_RES_I_ODD_102___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_102__TX_DCOC_RES_I_ODD_102___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_102__TX_DCOC_RES_Q_ODD_102___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_102__TX_DCOC_RES_Q_ODD_102___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_102__TX_DCOC_RES_I_EVEN_102___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_102__TX_DCOC_RES_I_EVEN_102___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_102__TX_DCOC_RES_Q_EVEN_102___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_102__TX_DCOC_RES_Q_EVEN_102___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_102___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_102___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_103 (0x005ED99C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_103___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_103___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_103__TX_DCOC_RES_I_ODD_103___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_103__TX_DCOC_RES_Q_ODD_103___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_103__TX_DCOC_RES_I_EVEN_103___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_103__TX_DCOC_RES_Q_EVEN_103___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_103__TX_DCOC_RES_I_ODD_103___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_103__TX_DCOC_RES_I_ODD_103___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_103__TX_DCOC_RES_Q_ODD_103___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_103__TX_DCOC_RES_Q_ODD_103___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_103__TX_DCOC_RES_I_EVEN_103___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_103__TX_DCOC_RES_I_EVEN_103___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_103__TX_DCOC_RES_Q_EVEN_103___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_103__TX_DCOC_RES_Q_EVEN_103___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_103___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_103___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_104 (0x005ED9A0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_104___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_104___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_104__TX_DCOC_RES_I_ODD_104___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_104__TX_DCOC_RES_Q_ODD_104___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_104__TX_DCOC_RES_I_EVEN_104___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_104__TX_DCOC_RES_Q_EVEN_104___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_104__TX_DCOC_RES_I_ODD_104___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_104__TX_DCOC_RES_I_ODD_104___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_104__TX_DCOC_RES_Q_ODD_104___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_104__TX_DCOC_RES_Q_ODD_104___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_104__TX_DCOC_RES_I_EVEN_104___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_104__TX_DCOC_RES_I_EVEN_104___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_104__TX_DCOC_RES_Q_EVEN_104___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_104__TX_DCOC_RES_Q_EVEN_104___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_104___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_104___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_105 (0x005ED9A4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_105___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_105___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_105__TX_DCOC_RES_I_ODD_105___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_105__TX_DCOC_RES_Q_ODD_105___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_105__TX_DCOC_RES_I_EVEN_105___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_105__TX_DCOC_RES_Q_EVEN_105___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_105__TX_DCOC_RES_I_ODD_105___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_105__TX_DCOC_RES_I_ODD_105___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_105__TX_DCOC_RES_Q_ODD_105___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_105__TX_DCOC_RES_Q_ODD_105___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_105__TX_DCOC_RES_I_EVEN_105___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_105__TX_DCOC_RES_I_EVEN_105___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_105__TX_DCOC_RES_Q_EVEN_105___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_105__TX_DCOC_RES_Q_EVEN_105___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_105___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_105___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_106 (0x005ED9A8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_106___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_106___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_106__TX_DCOC_RES_I_ODD_106___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_106__TX_DCOC_RES_Q_ODD_106___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_106__TX_DCOC_RES_I_EVEN_106___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_106__TX_DCOC_RES_Q_EVEN_106___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_106__TX_DCOC_RES_I_ODD_106___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_106__TX_DCOC_RES_I_ODD_106___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_106__TX_DCOC_RES_Q_ODD_106___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_106__TX_DCOC_RES_Q_ODD_106___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_106__TX_DCOC_RES_I_EVEN_106___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_106__TX_DCOC_RES_I_EVEN_106___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_106__TX_DCOC_RES_Q_EVEN_106___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_106__TX_DCOC_RES_Q_EVEN_106___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_106___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_106___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_107 (0x005ED9AC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_107___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_107___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_107__TX_DCOC_RES_I_ODD_107___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_107__TX_DCOC_RES_Q_ODD_107___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_107__TX_DCOC_RES_I_EVEN_107___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_107__TX_DCOC_RES_Q_EVEN_107___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_107__TX_DCOC_RES_I_ODD_107___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_107__TX_DCOC_RES_I_ODD_107___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_107__TX_DCOC_RES_Q_ODD_107___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_107__TX_DCOC_RES_Q_ODD_107___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_107__TX_DCOC_RES_I_EVEN_107___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_107__TX_DCOC_RES_I_EVEN_107___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_107__TX_DCOC_RES_Q_EVEN_107___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_107__TX_DCOC_RES_Q_EVEN_107___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_107___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_107___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_108 (0x005ED9B0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_108___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_108___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_108__TX_DCOC_RES_I_ODD_108___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_108__TX_DCOC_RES_Q_ODD_108___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_108__TX_DCOC_RES_I_EVEN_108___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_108__TX_DCOC_RES_Q_EVEN_108___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_108__TX_DCOC_RES_I_ODD_108___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_108__TX_DCOC_RES_I_ODD_108___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_108__TX_DCOC_RES_Q_ODD_108___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_108__TX_DCOC_RES_Q_ODD_108___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_108__TX_DCOC_RES_I_EVEN_108___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_108__TX_DCOC_RES_I_EVEN_108___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_108__TX_DCOC_RES_Q_EVEN_108___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_108__TX_DCOC_RES_Q_EVEN_108___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_108___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_108___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_109 (0x005ED9B4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_109___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_109___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_109__TX_DCOC_RES_I_ODD_109___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_109__TX_DCOC_RES_Q_ODD_109___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_109__TX_DCOC_RES_I_EVEN_109___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_109__TX_DCOC_RES_Q_EVEN_109___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_109__TX_DCOC_RES_I_ODD_109___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_109__TX_DCOC_RES_I_ODD_109___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_109__TX_DCOC_RES_Q_ODD_109___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_109__TX_DCOC_RES_Q_ODD_109___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_109__TX_DCOC_RES_I_EVEN_109___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_109__TX_DCOC_RES_I_EVEN_109___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_109__TX_DCOC_RES_Q_EVEN_109___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_109__TX_DCOC_RES_Q_EVEN_109___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_109___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_109___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_110 (0x005ED9B8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_110___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_110___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_110__TX_DCOC_RES_I_ODD_110___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_110__TX_DCOC_RES_Q_ODD_110___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_110__TX_DCOC_RES_I_EVEN_110___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_110__TX_DCOC_RES_Q_EVEN_110___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_110__TX_DCOC_RES_I_ODD_110___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_110__TX_DCOC_RES_I_ODD_110___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_110__TX_DCOC_RES_Q_ODD_110___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_110__TX_DCOC_RES_Q_ODD_110___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_110__TX_DCOC_RES_I_EVEN_110___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_110__TX_DCOC_RES_I_EVEN_110___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_110__TX_DCOC_RES_Q_EVEN_110___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_110__TX_DCOC_RES_Q_EVEN_110___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_110___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_110___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_111 (0x005ED9BC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_111___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_111___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_111__TX_DCOC_RES_I_ODD_111___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_111__TX_DCOC_RES_Q_ODD_111___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_111__TX_DCOC_RES_I_EVEN_111___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_111__TX_DCOC_RES_Q_EVEN_111___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_111__TX_DCOC_RES_I_ODD_111___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_111__TX_DCOC_RES_I_ODD_111___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_111__TX_DCOC_RES_Q_ODD_111___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_111__TX_DCOC_RES_Q_ODD_111___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_111__TX_DCOC_RES_I_EVEN_111___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_111__TX_DCOC_RES_I_EVEN_111___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_111__TX_DCOC_RES_Q_EVEN_111___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_111__TX_DCOC_RES_Q_EVEN_111___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_111___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_111___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_112 (0x005ED9C0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_112___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_112___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_112__TX_DCOC_RES_I_ODD_112___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_112__TX_DCOC_RES_Q_ODD_112___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_112__TX_DCOC_RES_I_EVEN_112___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_112__TX_DCOC_RES_Q_EVEN_112___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_112__TX_DCOC_RES_I_ODD_112___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_112__TX_DCOC_RES_I_ODD_112___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_112__TX_DCOC_RES_Q_ODD_112___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_112__TX_DCOC_RES_Q_ODD_112___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_112__TX_DCOC_RES_I_EVEN_112___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_112__TX_DCOC_RES_I_EVEN_112___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_112__TX_DCOC_RES_Q_EVEN_112___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_112__TX_DCOC_RES_Q_EVEN_112___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_112___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_112___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_113 (0x005ED9C4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_113___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_113___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_113__TX_DCOC_RES_I_ODD_113___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_113__TX_DCOC_RES_Q_ODD_113___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_113__TX_DCOC_RES_I_EVEN_113___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_113__TX_DCOC_RES_Q_EVEN_113___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_113__TX_DCOC_RES_I_ODD_113___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_113__TX_DCOC_RES_I_ODD_113___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_113__TX_DCOC_RES_Q_ODD_113___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_113__TX_DCOC_RES_Q_ODD_113___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_113__TX_DCOC_RES_I_EVEN_113___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_113__TX_DCOC_RES_I_EVEN_113___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_113__TX_DCOC_RES_Q_EVEN_113___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_113__TX_DCOC_RES_Q_EVEN_113___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_113___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_113___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_114 (0x005ED9C8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_114___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_114___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_114__TX_DCOC_RES_I_ODD_114___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_114__TX_DCOC_RES_Q_ODD_114___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_114__TX_DCOC_RES_I_EVEN_114___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_114__TX_DCOC_RES_Q_EVEN_114___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_114__TX_DCOC_RES_I_ODD_114___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_114__TX_DCOC_RES_I_ODD_114___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_114__TX_DCOC_RES_Q_ODD_114___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_114__TX_DCOC_RES_Q_ODD_114___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_114__TX_DCOC_RES_I_EVEN_114___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_114__TX_DCOC_RES_I_EVEN_114___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_114__TX_DCOC_RES_Q_EVEN_114___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_114__TX_DCOC_RES_Q_EVEN_114___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_114___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_114___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_115 (0x005ED9CC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_115___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_115___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_115__TX_DCOC_RES_I_ODD_115___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_115__TX_DCOC_RES_Q_ODD_115___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_115__TX_DCOC_RES_I_EVEN_115___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_115__TX_DCOC_RES_Q_EVEN_115___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_115__TX_DCOC_RES_I_ODD_115___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_115__TX_DCOC_RES_I_ODD_115___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_115__TX_DCOC_RES_Q_ODD_115___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_115__TX_DCOC_RES_Q_ODD_115___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_115__TX_DCOC_RES_I_EVEN_115___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_115__TX_DCOC_RES_I_EVEN_115___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_115__TX_DCOC_RES_Q_EVEN_115___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_115__TX_DCOC_RES_Q_EVEN_115___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_115___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_115___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_116 (0x005ED9D0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_116___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_116___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_116__TX_DCOC_RES_I_ODD_116___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_116__TX_DCOC_RES_Q_ODD_116___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_116__TX_DCOC_RES_I_EVEN_116___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_116__TX_DCOC_RES_Q_EVEN_116___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_116__TX_DCOC_RES_I_ODD_116___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_116__TX_DCOC_RES_I_ODD_116___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_116__TX_DCOC_RES_Q_ODD_116___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_116__TX_DCOC_RES_Q_ODD_116___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_116__TX_DCOC_RES_I_EVEN_116___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_116__TX_DCOC_RES_I_EVEN_116___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_116__TX_DCOC_RES_Q_EVEN_116___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_116__TX_DCOC_RES_Q_EVEN_116___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_116___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_116___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_117 (0x005ED9D4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_117___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_117___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_117__TX_DCOC_RES_I_ODD_117___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_117__TX_DCOC_RES_Q_ODD_117___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_117__TX_DCOC_RES_I_EVEN_117___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_117__TX_DCOC_RES_Q_EVEN_117___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_117__TX_DCOC_RES_I_ODD_117___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_117__TX_DCOC_RES_I_ODD_117___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_117__TX_DCOC_RES_Q_ODD_117___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_117__TX_DCOC_RES_Q_ODD_117___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_117__TX_DCOC_RES_I_EVEN_117___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_117__TX_DCOC_RES_I_EVEN_117___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_117__TX_DCOC_RES_Q_EVEN_117___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_117__TX_DCOC_RES_Q_EVEN_117___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_117___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_117___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_118 (0x005ED9D8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_118___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_118___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_118__TX_DCOC_RES_I_ODD_118___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_118__TX_DCOC_RES_Q_ODD_118___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_118__TX_DCOC_RES_I_EVEN_118___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_118__TX_DCOC_RES_Q_EVEN_118___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_118__TX_DCOC_RES_I_ODD_118___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_118__TX_DCOC_RES_I_ODD_118___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_118__TX_DCOC_RES_Q_ODD_118___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_118__TX_DCOC_RES_Q_ODD_118___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_118__TX_DCOC_RES_I_EVEN_118___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_118__TX_DCOC_RES_I_EVEN_118___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_118__TX_DCOC_RES_Q_EVEN_118___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_118__TX_DCOC_RES_Q_EVEN_118___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_118___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_118___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_119 (0x005ED9DC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_119___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_119___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_119__TX_DCOC_RES_I_ODD_119___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_119__TX_DCOC_RES_Q_ODD_119___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_119__TX_DCOC_RES_I_EVEN_119___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_119__TX_DCOC_RES_Q_EVEN_119___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_119__TX_DCOC_RES_I_ODD_119___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_119__TX_DCOC_RES_I_ODD_119___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_119__TX_DCOC_RES_Q_ODD_119___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_119__TX_DCOC_RES_Q_ODD_119___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_119__TX_DCOC_RES_I_EVEN_119___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_119__TX_DCOC_RES_I_EVEN_119___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_119__TX_DCOC_RES_Q_EVEN_119___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_119__TX_DCOC_RES_Q_EVEN_119___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_119___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_119___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_120 (0x005ED9E0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_120___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_120___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_120__TX_DCOC_RES_I_ODD_120___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_120__TX_DCOC_RES_Q_ODD_120___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_120__TX_DCOC_RES_I_EVEN_120___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_120__TX_DCOC_RES_Q_EVEN_120___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_120__TX_DCOC_RES_I_ODD_120___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_120__TX_DCOC_RES_I_ODD_120___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_120__TX_DCOC_RES_Q_ODD_120___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_120__TX_DCOC_RES_Q_ODD_120___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_120__TX_DCOC_RES_I_EVEN_120___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_120__TX_DCOC_RES_I_EVEN_120___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_120__TX_DCOC_RES_Q_EVEN_120___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_120__TX_DCOC_RES_Q_EVEN_120___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_120___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_120___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_121 (0x005ED9E4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_121___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_121___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_121__TX_DCOC_RES_I_ODD_121___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_121__TX_DCOC_RES_Q_ODD_121___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_121__TX_DCOC_RES_I_EVEN_121___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_121__TX_DCOC_RES_Q_EVEN_121___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_121__TX_DCOC_RES_I_ODD_121___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_121__TX_DCOC_RES_I_ODD_121___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_121__TX_DCOC_RES_Q_ODD_121___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_121__TX_DCOC_RES_Q_ODD_121___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_121__TX_DCOC_RES_I_EVEN_121___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_121__TX_DCOC_RES_I_EVEN_121___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_121__TX_DCOC_RES_Q_EVEN_121___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_121__TX_DCOC_RES_Q_EVEN_121___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_121___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_121___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_122 (0x005ED9E8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_122___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_122___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_122__TX_DCOC_RES_I_ODD_122___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_122__TX_DCOC_RES_Q_ODD_122___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_122__TX_DCOC_RES_I_EVEN_122___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_122__TX_DCOC_RES_Q_EVEN_122___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_122__TX_DCOC_RES_I_ODD_122___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_122__TX_DCOC_RES_I_ODD_122___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_122__TX_DCOC_RES_Q_ODD_122___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_122__TX_DCOC_RES_Q_ODD_122___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_122__TX_DCOC_RES_I_EVEN_122___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_122__TX_DCOC_RES_I_EVEN_122___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_122__TX_DCOC_RES_Q_EVEN_122___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_122__TX_DCOC_RES_Q_EVEN_122___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_122___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_122___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_123 (0x005ED9EC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_123___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_123___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_123__TX_DCOC_RES_I_ODD_123___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_123__TX_DCOC_RES_Q_ODD_123___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_123__TX_DCOC_RES_I_EVEN_123___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_123__TX_DCOC_RES_Q_EVEN_123___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_123__TX_DCOC_RES_I_ODD_123___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_123__TX_DCOC_RES_I_ODD_123___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_123__TX_DCOC_RES_Q_ODD_123___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_123__TX_DCOC_RES_Q_ODD_123___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_123__TX_DCOC_RES_I_EVEN_123___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_123__TX_DCOC_RES_I_EVEN_123___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_123__TX_DCOC_RES_Q_EVEN_123___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_123__TX_DCOC_RES_Q_EVEN_123___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_123___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_123___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_124 (0x005ED9F0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_124___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_124___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_124__TX_DCOC_RES_I_ODD_124___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_124__TX_DCOC_RES_Q_ODD_124___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_124__TX_DCOC_RES_I_EVEN_124___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_124__TX_DCOC_RES_Q_EVEN_124___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_124__TX_DCOC_RES_I_ODD_124___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_124__TX_DCOC_RES_I_ODD_124___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_124__TX_DCOC_RES_Q_ODD_124___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_124__TX_DCOC_RES_Q_ODD_124___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_124__TX_DCOC_RES_I_EVEN_124___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_124__TX_DCOC_RES_I_EVEN_124___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_124__TX_DCOC_RES_Q_EVEN_124___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_124__TX_DCOC_RES_Q_EVEN_124___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_124___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_124___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_125 (0x005ED9F4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_125___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_125___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_125__TX_DCOC_RES_I_ODD_125___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_125__TX_DCOC_RES_Q_ODD_125___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_125__TX_DCOC_RES_I_EVEN_125___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_125__TX_DCOC_RES_Q_EVEN_125___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_125__TX_DCOC_RES_I_ODD_125___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_125__TX_DCOC_RES_I_ODD_125___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_125__TX_DCOC_RES_Q_ODD_125___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_125__TX_DCOC_RES_Q_ODD_125___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_125__TX_DCOC_RES_I_EVEN_125___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_125__TX_DCOC_RES_I_EVEN_125___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_125__TX_DCOC_RES_Q_EVEN_125___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_125__TX_DCOC_RES_Q_EVEN_125___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_125___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_125___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_126 (0x005ED9F8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_126___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_126___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_126__TX_DCOC_RES_I_ODD_126___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_126__TX_DCOC_RES_Q_ODD_126___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_126__TX_DCOC_RES_I_EVEN_126___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_126__TX_DCOC_RES_Q_EVEN_126___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_126__TX_DCOC_RES_I_ODD_126___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_126__TX_DCOC_RES_I_ODD_126___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_126__TX_DCOC_RES_Q_ODD_126___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_126__TX_DCOC_RES_Q_ODD_126___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_126__TX_DCOC_RES_I_EVEN_126___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_126__TX_DCOC_RES_I_EVEN_126___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_126__TX_DCOC_RES_Q_EVEN_126___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_126__TX_DCOC_RES_Q_EVEN_126___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_126___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_126___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_127 (0x005ED9FC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_127___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_127___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_127__TX_DCOC_RES_I_ODD_127___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_127__TX_DCOC_RES_Q_ODD_127___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_127__TX_DCOC_RES_I_EVEN_127___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_127__TX_DCOC_RES_Q_EVEN_127___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_127__TX_DCOC_RES_I_ODD_127___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_127__TX_DCOC_RES_I_ODD_127___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_127__TX_DCOC_RES_Q_ODD_127___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_127__TX_DCOC_RES_Q_ODD_127___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_127__TX_DCOC_RES_I_EVEN_127___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_127__TX_DCOC_RES_I_EVEN_127___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_127__TX_DCOC_RES_Q_EVEN_127___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_127__TX_DCOC_RES_Q_EVEN_127___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_127___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXDCOC_127___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0 (0x005EDC00) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__IPA_GAIN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__DAC_GAIN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__TX_PWR_LV_LAA_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__TX_PWR_LV_N79_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__BBF_GAIN_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__UPC_GAIN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__DA_GAIN_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__XPA_GAIN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__IPA_GAIN_0___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__IPA_GAIN_0___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__DAC_GAIN_0___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__DAC_GAIN_0___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__TX_PWR_LV_LAA_0___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__TX_PWR_LV_LAA_0___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__TX_PWR_LV_N79_0___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__TX_PWR_LV_N79_0___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__BBF_GAIN_0___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__BBF_GAIN_0___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__UPC_GAIN_0___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__UPC_GAIN_0___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__DA_GAIN_0___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__DA_GAIN_0___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__XPA_GAIN_0___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0__XPA_GAIN_0___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1 (0x005EDC04) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__IPA_GAIN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__DAC_GAIN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__TX_PWR_LV_LAA_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__TX_PWR_LV_N79_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__BBF_GAIN_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__UPC_GAIN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__DA_GAIN_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__XPA_GAIN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__IPA_GAIN_1___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__IPA_GAIN_1___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__DAC_GAIN_1___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__DAC_GAIN_1___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__TX_PWR_LV_LAA_1___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__TX_PWR_LV_LAA_1___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__TX_PWR_LV_N79_1___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__TX_PWR_LV_N79_1___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__BBF_GAIN_1___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__BBF_GAIN_1___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__UPC_GAIN_1___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__UPC_GAIN_1___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__DA_GAIN_1___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__DA_GAIN_1___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__XPA_GAIN_1___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1__XPA_GAIN_1___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2 (0x005EDC08) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__IPA_GAIN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__DAC_GAIN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__TX_PWR_LV_LAA_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__TX_PWR_LV_N79_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__BBF_GAIN_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__UPC_GAIN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__DA_GAIN_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__XPA_GAIN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__IPA_GAIN_2___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__IPA_GAIN_2___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__DAC_GAIN_2___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__DAC_GAIN_2___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__TX_PWR_LV_LAA_2___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__TX_PWR_LV_LAA_2___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__TX_PWR_LV_N79_2___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__TX_PWR_LV_N79_2___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__BBF_GAIN_2___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__BBF_GAIN_2___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__UPC_GAIN_2___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__UPC_GAIN_2___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__DA_GAIN_2___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__DA_GAIN_2___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__XPA_GAIN_2___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2__XPA_GAIN_2___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_2___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3 (0x005EDC0C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__IPA_GAIN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__DAC_GAIN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__TX_PWR_LV_LAA_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__TX_PWR_LV_N79_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__BBF_GAIN_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__UPC_GAIN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__DA_GAIN_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__XPA_GAIN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__IPA_GAIN_3___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__IPA_GAIN_3___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__DAC_GAIN_3___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__DAC_GAIN_3___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__TX_PWR_LV_LAA_3___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__TX_PWR_LV_LAA_3___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__TX_PWR_LV_N79_3___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__TX_PWR_LV_N79_3___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__BBF_GAIN_3___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__BBF_GAIN_3___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__UPC_GAIN_3___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__UPC_GAIN_3___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__DA_GAIN_3___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__DA_GAIN_3___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__XPA_GAIN_3___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3__XPA_GAIN_3___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_3___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4 (0x005EDC10) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__IPA_GAIN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__DAC_GAIN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__TX_PWR_LV_LAA_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__TX_PWR_LV_N79_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__BBF_GAIN_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__UPC_GAIN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__DA_GAIN_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__XPA_GAIN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__IPA_GAIN_4___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__IPA_GAIN_4___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__DAC_GAIN_4___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__DAC_GAIN_4___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__TX_PWR_LV_LAA_4___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__TX_PWR_LV_LAA_4___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__TX_PWR_LV_N79_4___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__TX_PWR_LV_N79_4___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__BBF_GAIN_4___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__BBF_GAIN_4___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__UPC_GAIN_4___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__UPC_GAIN_4___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__DA_GAIN_4___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__DA_GAIN_4___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__XPA_GAIN_4___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4__XPA_GAIN_4___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_4___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5 (0x005EDC14) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__IPA_GAIN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__DAC_GAIN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__TX_PWR_LV_LAA_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__TX_PWR_LV_N79_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__BBF_GAIN_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__UPC_GAIN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__DA_GAIN_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__XPA_GAIN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__IPA_GAIN_5___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__IPA_GAIN_5___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__DAC_GAIN_5___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__DAC_GAIN_5___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__TX_PWR_LV_LAA_5___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__TX_PWR_LV_LAA_5___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__TX_PWR_LV_N79_5___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__TX_PWR_LV_N79_5___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__BBF_GAIN_5___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__BBF_GAIN_5___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__UPC_GAIN_5___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__UPC_GAIN_5___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__DA_GAIN_5___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__DA_GAIN_5___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__XPA_GAIN_5___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5__XPA_GAIN_5___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_5___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6 (0x005EDC18) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__IPA_GAIN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__DAC_GAIN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__TX_PWR_LV_LAA_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__TX_PWR_LV_N79_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__BBF_GAIN_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__UPC_GAIN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__DA_GAIN_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__XPA_GAIN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__IPA_GAIN_6___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__IPA_GAIN_6___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__DAC_GAIN_6___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__DAC_GAIN_6___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__TX_PWR_LV_LAA_6___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__TX_PWR_LV_LAA_6___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__TX_PWR_LV_N79_6___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__TX_PWR_LV_N79_6___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__BBF_GAIN_6___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__BBF_GAIN_6___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__UPC_GAIN_6___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__UPC_GAIN_6___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__DA_GAIN_6___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__DA_GAIN_6___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__XPA_GAIN_6___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6__XPA_GAIN_6___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_6___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7 (0x005EDC1C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__IPA_GAIN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__DAC_GAIN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__TX_PWR_LV_LAA_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__TX_PWR_LV_N79_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__BBF_GAIN_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__UPC_GAIN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__DA_GAIN_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__XPA_GAIN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__IPA_GAIN_7___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__IPA_GAIN_7___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__DAC_GAIN_7___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__DAC_GAIN_7___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__TX_PWR_LV_LAA_7___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__TX_PWR_LV_LAA_7___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__TX_PWR_LV_N79_7___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__TX_PWR_LV_N79_7___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__BBF_GAIN_7___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__BBF_GAIN_7___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__UPC_GAIN_7___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__UPC_GAIN_7___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__DA_GAIN_7___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__DA_GAIN_7___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__XPA_GAIN_7___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7__XPA_GAIN_7___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_7___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8 (0x005EDC20) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__IPA_GAIN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__DAC_GAIN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__TX_PWR_LV_LAA_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__TX_PWR_LV_N79_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__BBF_GAIN_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__UPC_GAIN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__DA_GAIN_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__XPA_GAIN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__IPA_GAIN_8___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__IPA_GAIN_8___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__DAC_GAIN_8___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__DAC_GAIN_8___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__TX_PWR_LV_LAA_8___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__TX_PWR_LV_LAA_8___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__TX_PWR_LV_N79_8___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__TX_PWR_LV_N79_8___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__BBF_GAIN_8___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__BBF_GAIN_8___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__UPC_GAIN_8___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__UPC_GAIN_8___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__DA_GAIN_8___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__DA_GAIN_8___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__XPA_GAIN_8___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8__XPA_GAIN_8___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_8___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9 (0x005EDC24) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__IPA_GAIN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__DAC_GAIN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__TX_PWR_LV_LAA_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__TX_PWR_LV_N79_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__BBF_GAIN_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__UPC_GAIN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__DA_GAIN_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__XPA_GAIN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__IPA_GAIN_9___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__IPA_GAIN_9___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__DAC_GAIN_9___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__DAC_GAIN_9___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__TX_PWR_LV_LAA_9___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__TX_PWR_LV_LAA_9___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__TX_PWR_LV_N79_9___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__TX_PWR_LV_N79_9___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__BBF_GAIN_9___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__BBF_GAIN_9___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__UPC_GAIN_9___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__UPC_GAIN_9___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__DA_GAIN_9___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__DA_GAIN_9___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__XPA_GAIN_9___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9__XPA_GAIN_9___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_9___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10 (0x005EDC28) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__IPA_GAIN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__DAC_GAIN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__TX_PWR_LV_LAA_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__TX_PWR_LV_N79_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__BBF_GAIN_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__UPC_GAIN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__DA_GAIN_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__XPA_GAIN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__IPA_GAIN_10___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__IPA_GAIN_10___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__DAC_GAIN_10___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__DAC_GAIN_10___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__TX_PWR_LV_LAA_10___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__TX_PWR_LV_LAA_10___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__TX_PWR_LV_N79_10___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__TX_PWR_LV_N79_10___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__BBF_GAIN_10___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__BBF_GAIN_10___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__UPC_GAIN_10___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__UPC_GAIN_10___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__DA_GAIN_10___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__DA_GAIN_10___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__XPA_GAIN_10___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10__XPA_GAIN_10___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_10___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11 (0x005EDC2C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__IPA_GAIN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__DAC_GAIN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__TX_PWR_LV_LAA_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__TX_PWR_LV_N79_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__BBF_GAIN_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__UPC_GAIN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__DA_GAIN_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__XPA_GAIN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__IPA_GAIN_11___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__IPA_GAIN_11___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__DAC_GAIN_11___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__DAC_GAIN_11___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__TX_PWR_LV_LAA_11___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__TX_PWR_LV_LAA_11___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__TX_PWR_LV_N79_11___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__TX_PWR_LV_N79_11___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__BBF_GAIN_11___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__BBF_GAIN_11___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__UPC_GAIN_11___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__UPC_GAIN_11___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__DA_GAIN_11___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__DA_GAIN_11___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__XPA_GAIN_11___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11__XPA_GAIN_11___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_11___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12 (0x005EDC30) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__IPA_GAIN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__DAC_GAIN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__TX_PWR_LV_LAA_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__TX_PWR_LV_N79_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__BBF_GAIN_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__UPC_GAIN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__DA_GAIN_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__XPA_GAIN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__IPA_GAIN_12___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__IPA_GAIN_12___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__DAC_GAIN_12___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__DAC_GAIN_12___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__TX_PWR_LV_LAA_12___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__TX_PWR_LV_LAA_12___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__TX_PWR_LV_N79_12___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__TX_PWR_LV_N79_12___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__BBF_GAIN_12___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__BBF_GAIN_12___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__UPC_GAIN_12___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__UPC_GAIN_12___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__DA_GAIN_12___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__DA_GAIN_12___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__XPA_GAIN_12___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12__XPA_GAIN_12___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_12___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13 (0x005EDC34) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__IPA_GAIN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__DAC_GAIN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__TX_PWR_LV_LAA_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__TX_PWR_LV_N79_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__BBF_GAIN_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__UPC_GAIN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__DA_GAIN_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__XPA_GAIN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__IPA_GAIN_13___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__IPA_GAIN_13___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__DAC_GAIN_13___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__DAC_GAIN_13___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__TX_PWR_LV_LAA_13___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__TX_PWR_LV_LAA_13___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__TX_PWR_LV_N79_13___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__TX_PWR_LV_N79_13___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__BBF_GAIN_13___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__BBF_GAIN_13___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__UPC_GAIN_13___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__UPC_GAIN_13___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__DA_GAIN_13___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__DA_GAIN_13___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__XPA_GAIN_13___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13__XPA_GAIN_13___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_13___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14 (0x005EDC38) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__IPA_GAIN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__DAC_GAIN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__TX_PWR_LV_LAA_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__TX_PWR_LV_N79_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__BBF_GAIN_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__UPC_GAIN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__DA_GAIN_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__XPA_GAIN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__IPA_GAIN_14___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__IPA_GAIN_14___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__DAC_GAIN_14___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__DAC_GAIN_14___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__TX_PWR_LV_LAA_14___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__TX_PWR_LV_LAA_14___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__TX_PWR_LV_N79_14___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__TX_PWR_LV_N79_14___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__BBF_GAIN_14___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__BBF_GAIN_14___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__UPC_GAIN_14___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__UPC_GAIN_14___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__DA_GAIN_14___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__DA_GAIN_14___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__XPA_GAIN_14___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14__XPA_GAIN_14___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_14___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15 (0x005EDC3C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__IPA_GAIN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__DAC_GAIN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__TX_PWR_LV_LAA_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__TX_PWR_LV_N79_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__BBF_GAIN_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__UPC_GAIN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__DA_GAIN_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__XPA_GAIN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__IPA_GAIN_15___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__IPA_GAIN_15___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__DAC_GAIN_15___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__DAC_GAIN_15___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__TX_PWR_LV_LAA_15___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__TX_PWR_LV_LAA_15___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__TX_PWR_LV_N79_15___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__TX_PWR_LV_N79_15___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__BBF_GAIN_15___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__BBF_GAIN_15___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__UPC_GAIN_15___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__UPC_GAIN_15___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__DA_GAIN_15___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__DA_GAIN_15___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__XPA_GAIN_15___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15__XPA_GAIN_15___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_15___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16 (0x005EDC40) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__IPA_GAIN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__DAC_GAIN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__TX_PWR_LV_LAA_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__TX_PWR_LV_N79_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__BBF_GAIN_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__UPC_GAIN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__DA_GAIN_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__XPA_GAIN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__IPA_GAIN_16___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__IPA_GAIN_16___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__DAC_GAIN_16___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__DAC_GAIN_16___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__TX_PWR_LV_LAA_16___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__TX_PWR_LV_LAA_16___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__TX_PWR_LV_N79_16___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__TX_PWR_LV_N79_16___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__BBF_GAIN_16___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__BBF_GAIN_16___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__UPC_GAIN_16___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__UPC_GAIN_16___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__DA_GAIN_16___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__DA_GAIN_16___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__XPA_GAIN_16___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16__XPA_GAIN_16___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_16___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17 (0x005EDC44) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__IPA_GAIN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__DAC_GAIN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__TX_PWR_LV_LAA_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__TX_PWR_LV_N79_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__BBF_GAIN_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__UPC_GAIN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__DA_GAIN_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__XPA_GAIN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__IPA_GAIN_17___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__IPA_GAIN_17___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__DAC_GAIN_17___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__DAC_GAIN_17___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__TX_PWR_LV_LAA_17___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__TX_PWR_LV_LAA_17___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__TX_PWR_LV_N79_17___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__TX_PWR_LV_N79_17___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__BBF_GAIN_17___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__BBF_GAIN_17___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__UPC_GAIN_17___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__UPC_GAIN_17___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__DA_GAIN_17___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__DA_GAIN_17___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__XPA_GAIN_17___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17__XPA_GAIN_17___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_17___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18 (0x005EDC48) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__IPA_GAIN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__DAC_GAIN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__TX_PWR_LV_LAA_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__TX_PWR_LV_N79_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__BBF_GAIN_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__UPC_GAIN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__DA_GAIN_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__XPA_GAIN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__IPA_GAIN_18___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__IPA_GAIN_18___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__DAC_GAIN_18___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__DAC_GAIN_18___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__TX_PWR_LV_LAA_18___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__TX_PWR_LV_LAA_18___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__TX_PWR_LV_N79_18___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__TX_PWR_LV_N79_18___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__BBF_GAIN_18___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__BBF_GAIN_18___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__UPC_GAIN_18___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__UPC_GAIN_18___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__DA_GAIN_18___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__DA_GAIN_18___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__XPA_GAIN_18___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18__XPA_GAIN_18___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_18___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19 (0x005EDC4C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__IPA_GAIN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__DAC_GAIN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__TX_PWR_LV_LAA_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__TX_PWR_LV_N79_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__BBF_GAIN_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__UPC_GAIN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__DA_GAIN_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__XPA_GAIN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__IPA_GAIN_19___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__IPA_GAIN_19___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__DAC_GAIN_19___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__DAC_GAIN_19___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__TX_PWR_LV_LAA_19___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__TX_PWR_LV_LAA_19___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__TX_PWR_LV_N79_19___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__TX_PWR_LV_N79_19___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__BBF_GAIN_19___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__BBF_GAIN_19___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__UPC_GAIN_19___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__UPC_GAIN_19___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__DA_GAIN_19___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__DA_GAIN_19___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__XPA_GAIN_19___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19__XPA_GAIN_19___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_19___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20 (0x005EDC50) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__IPA_GAIN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__DAC_GAIN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__TX_PWR_LV_LAA_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__TX_PWR_LV_N79_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__BBF_GAIN_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__UPC_GAIN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__DA_GAIN_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__XPA_GAIN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__IPA_GAIN_20___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__IPA_GAIN_20___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__DAC_GAIN_20___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__DAC_GAIN_20___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__TX_PWR_LV_LAA_20___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__TX_PWR_LV_LAA_20___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__TX_PWR_LV_N79_20___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__TX_PWR_LV_N79_20___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__BBF_GAIN_20___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__BBF_GAIN_20___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__UPC_GAIN_20___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__UPC_GAIN_20___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__DA_GAIN_20___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__DA_GAIN_20___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__XPA_GAIN_20___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20__XPA_GAIN_20___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_20___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21 (0x005EDC54) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__IPA_GAIN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__DAC_GAIN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__TX_PWR_LV_LAA_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__TX_PWR_LV_N79_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__BBF_GAIN_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__UPC_GAIN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__DA_GAIN_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__XPA_GAIN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__IPA_GAIN_21___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__IPA_GAIN_21___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__DAC_GAIN_21___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__DAC_GAIN_21___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__TX_PWR_LV_LAA_21___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__TX_PWR_LV_LAA_21___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__TX_PWR_LV_N79_21___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__TX_PWR_LV_N79_21___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__BBF_GAIN_21___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__BBF_GAIN_21___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__UPC_GAIN_21___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__UPC_GAIN_21___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__DA_GAIN_21___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__DA_GAIN_21___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__XPA_GAIN_21___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21__XPA_GAIN_21___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_21___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22 (0x005EDC58) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__IPA_GAIN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__DAC_GAIN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__TX_PWR_LV_LAA_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__TX_PWR_LV_N79_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__BBF_GAIN_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__UPC_GAIN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__DA_GAIN_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__XPA_GAIN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__IPA_GAIN_22___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__IPA_GAIN_22___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__DAC_GAIN_22___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__DAC_GAIN_22___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__TX_PWR_LV_LAA_22___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__TX_PWR_LV_LAA_22___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__TX_PWR_LV_N79_22___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__TX_PWR_LV_N79_22___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__BBF_GAIN_22___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__BBF_GAIN_22___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__UPC_GAIN_22___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__UPC_GAIN_22___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__DA_GAIN_22___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__DA_GAIN_22___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__XPA_GAIN_22___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22__XPA_GAIN_22___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_22___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23 (0x005EDC5C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__IPA_GAIN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__DAC_GAIN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__TX_PWR_LV_LAA_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__TX_PWR_LV_N79_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__BBF_GAIN_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__UPC_GAIN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__DA_GAIN_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__XPA_GAIN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__IPA_GAIN_23___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__IPA_GAIN_23___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__DAC_GAIN_23___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__DAC_GAIN_23___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__TX_PWR_LV_LAA_23___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__TX_PWR_LV_LAA_23___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__TX_PWR_LV_N79_23___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__TX_PWR_LV_N79_23___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__BBF_GAIN_23___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__BBF_GAIN_23___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__UPC_GAIN_23___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__UPC_GAIN_23___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__DA_GAIN_23___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__DA_GAIN_23___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__XPA_GAIN_23___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23__XPA_GAIN_23___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_23___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24 (0x005EDC60) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__IPA_GAIN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__DAC_GAIN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__TX_PWR_LV_LAA_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__TX_PWR_LV_N79_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__BBF_GAIN_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__UPC_GAIN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__DA_GAIN_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__XPA_GAIN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__IPA_GAIN_24___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__IPA_GAIN_24___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__DAC_GAIN_24___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__DAC_GAIN_24___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__TX_PWR_LV_LAA_24___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__TX_PWR_LV_LAA_24___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__TX_PWR_LV_N79_24___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__TX_PWR_LV_N79_24___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__BBF_GAIN_24___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__BBF_GAIN_24___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__UPC_GAIN_24___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__UPC_GAIN_24___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__DA_GAIN_24___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__DA_GAIN_24___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__XPA_GAIN_24___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24__XPA_GAIN_24___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_24___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25 (0x005EDC64) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__IPA_GAIN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__DAC_GAIN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__TX_PWR_LV_LAA_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__TX_PWR_LV_N79_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__BBF_GAIN_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__UPC_GAIN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__DA_GAIN_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__XPA_GAIN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__IPA_GAIN_25___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__IPA_GAIN_25___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__DAC_GAIN_25___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__DAC_GAIN_25___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__TX_PWR_LV_LAA_25___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__TX_PWR_LV_LAA_25___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__TX_PWR_LV_N79_25___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__TX_PWR_LV_N79_25___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__BBF_GAIN_25___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__BBF_GAIN_25___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__UPC_GAIN_25___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__UPC_GAIN_25___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__DA_GAIN_25___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__DA_GAIN_25___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__XPA_GAIN_25___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25__XPA_GAIN_25___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_25___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26 (0x005EDC68) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__IPA_GAIN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__DAC_GAIN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__TX_PWR_LV_LAA_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__TX_PWR_LV_N79_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__BBF_GAIN_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__UPC_GAIN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__DA_GAIN_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__XPA_GAIN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__IPA_GAIN_26___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__IPA_GAIN_26___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__DAC_GAIN_26___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__DAC_GAIN_26___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__TX_PWR_LV_LAA_26___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__TX_PWR_LV_LAA_26___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__TX_PWR_LV_N79_26___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__TX_PWR_LV_N79_26___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__BBF_GAIN_26___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__BBF_GAIN_26___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__UPC_GAIN_26___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__UPC_GAIN_26___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__DA_GAIN_26___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__DA_GAIN_26___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__XPA_GAIN_26___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26__XPA_GAIN_26___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_26___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27 (0x005EDC6C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__IPA_GAIN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__DAC_GAIN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__TX_PWR_LV_LAA_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__TX_PWR_LV_N79_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__BBF_GAIN_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__UPC_GAIN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__DA_GAIN_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__XPA_GAIN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__IPA_GAIN_27___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__IPA_GAIN_27___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__DAC_GAIN_27___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__DAC_GAIN_27___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__TX_PWR_LV_LAA_27___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__TX_PWR_LV_LAA_27___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__TX_PWR_LV_N79_27___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__TX_PWR_LV_N79_27___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__BBF_GAIN_27___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__BBF_GAIN_27___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__UPC_GAIN_27___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__UPC_GAIN_27___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__DA_GAIN_27___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__DA_GAIN_27___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__XPA_GAIN_27___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27__XPA_GAIN_27___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_27___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28 (0x005EDC70) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__IPA_GAIN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__DAC_GAIN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__TX_PWR_LV_LAA_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__TX_PWR_LV_N79_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__BBF_GAIN_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__UPC_GAIN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__DA_GAIN_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__XPA_GAIN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__IPA_GAIN_28___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__IPA_GAIN_28___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__DAC_GAIN_28___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__DAC_GAIN_28___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__TX_PWR_LV_LAA_28___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__TX_PWR_LV_LAA_28___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__TX_PWR_LV_N79_28___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__TX_PWR_LV_N79_28___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__BBF_GAIN_28___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__BBF_GAIN_28___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__UPC_GAIN_28___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__UPC_GAIN_28___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__DA_GAIN_28___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__DA_GAIN_28___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__XPA_GAIN_28___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28__XPA_GAIN_28___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_28___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29 (0x005EDC74) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__IPA_GAIN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__DAC_GAIN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__TX_PWR_LV_LAA_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__TX_PWR_LV_N79_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__BBF_GAIN_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__UPC_GAIN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__DA_GAIN_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__XPA_GAIN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__IPA_GAIN_29___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__IPA_GAIN_29___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__DAC_GAIN_29___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__DAC_GAIN_29___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__TX_PWR_LV_LAA_29___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__TX_PWR_LV_LAA_29___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__TX_PWR_LV_N79_29___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__TX_PWR_LV_N79_29___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__BBF_GAIN_29___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__BBF_GAIN_29___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__UPC_GAIN_29___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__UPC_GAIN_29___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__DA_GAIN_29___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__DA_GAIN_29___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__XPA_GAIN_29___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29__XPA_GAIN_29___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_29___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30 (0x005EDC78) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__IPA_GAIN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__DAC_GAIN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__TX_PWR_LV_LAA_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__TX_PWR_LV_N79_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__BBF_GAIN_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__UPC_GAIN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__DA_GAIN_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__XPA_GAIN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__IPA_GAIN_30___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__IPA_GAIN_30___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__DAC_GAIN_30___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__DAC_GAIN_30___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__TX_PWR_LV_LAA_30___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__TX_PWR_LV_LAA_30___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__TX_PWR_LV_N79_30___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__TX_PWR_LV_N79_30___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__BBF_GAIN_30___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__BBF_GAIN_30___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__UPC_GAIN_30___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__UPC_GAIN_30___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__DA_GAIN_30___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__DA_GAIN_30___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__XPA_GAIN_30___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30__XPA_GAIN_30___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_30___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31 (0x005EDC7C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__IPA_GAIN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__DAC_GAIN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__TX_PWR_LV_LAA_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__TX_PWR_LV_N79_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__BBF_GAIN_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__UPC_GAIN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__DA_GAIN_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__XPA_GAIN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__IPA_GAIN_31___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__IPA_GAIN_31___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__DAC_GAIN_31___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__DAC_GAIN_31___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__TX_PWR_LV_LAA_31___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__TX_PWR_LV_LAA_31___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__TX_PWR_LV_N79_31___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__TX_PWR_LV_N79_31___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__BBF_GAIN_31___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__BBF_GAIN_31___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__UPC_GAIN_31___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__UPC_GAIN_31___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__DA_GAIN_31___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__DA_GAIN_31___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__XPA_GAIN_31___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31__XPA_GAIN_31___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_31___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32 (0x005EDC80) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__IPA_GAIN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__DAC_GAIN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__TX_PWR_LV_LAA_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__TX_PWR_LV_N79_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__BBF_GAIN_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__UPC_GAIN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__DA_GAIN_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__XPA_GAIN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__IPA_GAIN_32___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__IPA_GAIN_32___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__DAC_GAIN_32___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__DAC_GAIN_32___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__TX_PWR_LV_LAA_32___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__TX_PWR_LV_LAA_32___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__TX_PWR_LV_N79_32___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__TX_PWR_LV_N79_32___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__BBF_GAIN_32___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__BBF_GAIN_32___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__UPC_GAIN_32___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__UPC_GAIN_32___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__DA_GAIN_32___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__DA_GAIN_32___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__XPA_GAIN_32___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32__XPA_GAIN_32___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_32___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33 (0x005EDC84) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__IPA_GAIN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__DAC_GAIN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__TX_PWR_LV_LAA_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__TX_PWR_LV_N79_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__BBF_GAIN_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__UPC_GAIN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__DA_GAIN_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__XPA_GAIN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__IPA_GAIN_33___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__IPA_GAIN_33___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__DAC_GAIN_33___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__DAC_GAIN_33___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__TX_PWR_LV_LAA_33___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__TX_PWR_LV_LAA_33___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__TX_PWR_LV_N79_33___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__TX_PWR_LV_N79_33___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__BBF_GAIN_33___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__BBF_GAIN_33___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__UPC_GAIN_33___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__UPC_GAIN_33___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__DA_GAIN_33___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__DA_GAIN_33___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__XPA_GAIN_33___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33__XPA_GAIN_33___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_33___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34 (0x005EDC88) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__IPA_GAIN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__DAC_GAIN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__TX_PWR_LV_LAA_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__TX_PWR_LV_N79_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__BBF_GAIN_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__UPC_GAIN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__DA_GAIN_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__XPA_GAIN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__IPA_GAIN_34___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__IPA_GAIN_34___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__DAC_GAIN_34___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__DAC_GAIN_34___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__TX_PWR_LV_LAA_34___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__TX_PWR_LV_LAA_34___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__TX_PWR_LV_N79_34___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__TX_PWR_LV_N79_34___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__BBF_GAIN_34___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__BBF_GAIN_34___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__UPC_GAIN_34___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__UPC_GAIN_34___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__DA_GAIN_34___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__DA_GAIN_34___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__XPA_GAIN_34___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34__XPA_GAIN_34___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_34___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35 (0x005EDC8C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__IPA_GAIN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__DAC_GAIN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__TX_PWR_LV_LAA_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__TX_PWR_LV_N79_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__BBF_GAIN_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__UPC_GAIN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__DA_GAIN_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__XPA_GAIN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__IPA_GAIN_35___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__IPA_GAIN_35___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__DAC_GAIN_35___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__DAC_GAIN_35___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__TX_PWR_LV_LAA_35___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__TX_PWR_LV_LAA_35___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__TX_PWR_LV_N79_35___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__TX_PWR_LV_N79_35___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__BBF_GAIN_35___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__BBF_GAIN_35___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__UPC_GAIN_35___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__UPC_GAIN_35___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__DA_GAIN_35___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__DA_GAIN_35___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__XPA_GAIN_35___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35__XPA_GAIN_35___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_35___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36 (0x005EDC90) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__IPA_GAIN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__DAC_GAIN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__TX_PWR_LV_LAA_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__TX_PWR_LV_N79_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__BBF_GAIN_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__UPC_GAIN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__DA_GAIN_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__XPA_GAIN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__IPA_GAIN_36___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__IPA_GAIN_36___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__DAC_GAIN_36___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__DAC_GAIN_36___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__TX_PWR_LV_LAA_36___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__TX_PWR_LV_LAA_36___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__TX_PWR_LV_N79_36___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__TX_PWR_LV_N79_36___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__BBF_GAIN_36___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__BBF_GAIN_36___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__UPC_GAIN_36___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__UPC_GAIN_36___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__DA_GAIN_36___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__DA_GAIN_36___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__XPA_GAIN_36___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36__XPA_GAIN_36___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_36___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37 (0x005EDC94) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__IPA_GAIN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__DAC_GAIN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__TX_PWR_LV_LAA_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__TX_PWR_LV_N79_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__BBF_GAIN_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__UPC_GAIN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__DA_GAIN_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__XPA_GAIN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__IPA_GAIN_37___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__IPA_GAIN_37___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__DAC_GAIN_37___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__DAC_GAIN_37___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__TX_PWR_LV_LAA_37___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__TX_PWR_LV_LAA_37___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__TX_PWR_LV_N79_37___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__TX_PWR_LV_N79_37___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__BBF_GAIN_37___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__BBF_GAIN_37___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__UPC_GAIN_37___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__UPC_GAIN_37___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__DA_GAIN_37___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__DA_GAIN_37___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__XPA_GAIN_37___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37__XPA_GAIN_37___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_37___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38 (0x005EDC98) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__IPA_GAIN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__DAC_GAIN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__TX_PWR_LV_LAA_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__TX_PWR_LV_N79_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__BBF_GAIN_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__UPC_GAIN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__DA_GAIN_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__XPA_GAIN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__IPA_GAIN_38___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__IPA_GAIN_38___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__DAC_GAIN_38___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__DAC_GAIN_38___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__TX_PWR_LV_LAA_38___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__TX_PWR_LV_LAA_38___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__TX_PWR_LV_N79_38___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__TX_PWR_LV_N79_38___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__BBF_GAIN_38___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__BBF_GAIN_38___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__UPC_GAIN_38___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__UPC_GAIN_38___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__DA_GAIN_38___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__DA_GAIN_38___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__XPA_GAIN_38___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38__XPA_GAIN_38___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_38___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39 (0x005EDC9C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__IPA_GAIN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__DAC_GAIN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__TX_PWR_LV_LAA_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__TX_PWR_LV_N79_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__BBF_GAIN_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__UPC_GAIN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__DA_GAIN_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__XPA_GAIN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__IPA_GAIN_39___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__IPA_GAIN_39___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__DAC_GAIN_39___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__DAC_GAIN_39___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__TX_PWR_LV_LAA_39___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__TX_PWR_LV_LAA_39___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__TX_PWR_LV_N79_39___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__TX_PWR_LV_N79_39___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__BBF_GAIN_39___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__BBF_GAIN_39___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__UPC_GAIN_39___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__UPC_GAIN_39___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__DA_GAIN_39___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__DA_GAIN_39___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__XPA_GAIN_39___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39__XPA_GAIN_39___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_39___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40 (0x005EDCA0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__IPA_GAIN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__DAC_GAIN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__TX_PWR_LV_LAA_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__TX_PWR_LV_N79_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__BBF_GAIN_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__UPC_GAIN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__DA_GAIN_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__XPA_GAIN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__IPA_GAIN_40___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__IPA_GAIN_40___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__DAC_GAIN_40___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__DAC_GAIN_40___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__TX_PWR_LV_LAA_40___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__TX_PWR_LV_LAA_40___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__TX_PWR_LV_N79_40___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__TX_PWR_LV_N79_40___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__BBF_GAIN_40___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__BBF_GAIN_40___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__UPC_GAIN_40___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__UPC_GAIN_40___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__DA_GAIN_40___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__DA_GAIN_40___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__XPA_GAIN_40___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40__XPA_GAIN_40___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_40___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41 (0x005EDCA4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__IPA_GAIN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__DAC_GAIN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__TX_PWR_LV_LAA_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__TX_PWR_LV_N79_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__BBF_GAIN_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__UPC_GAIN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__DA_GAIN_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__XPA_GAIN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__IPA_GAIN_41___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__IPA_GAIN_41___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__DAC_GAIN_41___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__DAC_GAIN_41___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__TX_PWR_LV_LAA_41___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__TX_PWR_LV_LAA_41___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__TX_PWR_LV_N79_41___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__TX_PWR_LV_N79_41___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__BBF_GAIN_41___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__BBF_GAIN_41___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__UPC_GAIN_41___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__UPC_GAIN_41___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__DA_GAIN_41___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__DA_GAIN_41___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__XPA_GAIN_41___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41__XPA_GAIN_41___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_41___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42 (0x005EDCA8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__IPA_GAIN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__DAC_GAIN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__TX_PWR_LV_LAA_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__TX_PWR_LV_N79_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__BBF_GAIN_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__UPC_GAIN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__DA_GAIN_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__XPA_GAIN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__IPA_GAIN_42___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__IPA_GAIN_42___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__DAC_GAIN_42___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__DAC_GAIN_42___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__TX_PWR_LV_LAA_42___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__TX_PWR_LV_LAA_42___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__TX_PWR_LV_N79_42___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__TX_PWR_LV_N79_42___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__BBF_GAIN_42___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__BBF_GAIN_42___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__UPC_GAIN_42___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__UPC_GAIN_42___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__DA_GAIN_42___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__DA_GAIN_42___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__XPA_GAIN_42___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42__XPA_GAIN_42___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_42___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43 (0x005EDCAC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__IPA_GAIN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__DAC_GAIN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__TX_PWR_LV_LAA_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__TX_PWR_LV_N79_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__BBF_GAIN_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__UPC_GAIN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__DA_GAIN_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__XPA_GAIN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__IPA_GAIN_43___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__IPA_GAIN_43___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__DAC_GAIN_43___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__DAC_GAIN_43___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__TX_PWR_LV_LAA_43___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__TX_PWR_LV_LAA_43___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__TX_PWR_LV_N79_43___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__TX_PWR_LV_N79_43___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__BBF_GAIN_43___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__BBF_GAIN_43___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__UPC_GAIN_43___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__UPC_GAIN_43___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__DA_GAIN_43___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__DA_GAIN_43___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__XPA_GAIN_43___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43__XPA_GAIN_43___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_43___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44 (0x005EDCB0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__IPA_GAIN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__DAC_GAIN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__TX_PWR_LV_LAA_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__TX_PWR_LV_N79_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__BBF_GAIN_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__UPC_GAIN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__DA_GAIN_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__XPA_GAIN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__IPA_GAIN_44___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__IPA_GAIN_44___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__DAC_GAIN_44___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__DAC_GAIN_44___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__TX_PWR_LV_LAA_44___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__TX_PWR_LV_LAA_44___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__TX_PWR_LV_N79_44___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__TX_PWR_LV_N79_44___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__BBF_GAIN_44___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__BBF_GAIN_44___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__UPC_GAIN_44___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__UPC_GAIN_44___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__DA_GAIN_44___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__DA_GAIN_44___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__XPA_GAIN_44___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44__XPA_GAIN_44___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_44___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45 (0x005EDCB4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__IPA_GAIN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__DAC_GAIN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__TX_PWR_LV_LAA_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__TX_PWR_LV_N79_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__BBF_GAIN_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__UPC_GAIN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__DA_GAIN_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__XPA_GAIN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__IPA_GAIN_45___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__IPA_GAIN_45___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__DAC_GAIN_45___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__DAC_GAIN_45___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__TX_PWR_LV_LAA_45___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__TX_PWR_LV_LAA_45___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__TX_PWR_LV_N79_45___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__TX_PWR_LV_N79_45___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__BBF_GAIN_45___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__BBF_GAIN_45___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__UPC_GAIN_45___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__UPC_GAIN_45___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__DA_GAIN_45___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__DA_GAIN_45___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__XPA_GAIN_45___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45__XPA_GAIN_45___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_45___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46 (0x005EDCB8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__IPA_GAIN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__DAC_GAIN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__TX_PWR_LV_LAA_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__TX_PWR_LV_N79_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__BBF_GAIN_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__UPC_GAIN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__DA_GAIN_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__XPA_GAIN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__IPA_GAIN_46___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__IPA_GAIN_46___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__DAC_GAIN_46___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__DAC_GAIN_46___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__TX_PWR_LV_LAA_46___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__TX_PWR_LV_LAA_46___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__TX_PWR_LV_N79_46___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__TX_PWR_LV_N79_46___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__BBF_GAIN_46___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__BBF_GAIN_46___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__UPC_GAIN_46___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__UPC_GAIN_46___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__DA_GAIN_46___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__DA_GAIN_46___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__XPA_GAIN_46___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46__XPA_GAIN_46___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_46___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47 (0x005EDCBC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__IPA_GAIN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__DAC_GAIN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__TX_PWR_LV_LAA_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__TX_PWR_LV_N79_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__BBF_GAIN_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__UPC_GAIN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__DA_GAIN_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__XPA_GAIN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__IPA_GAIN_47___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__IPA_GAIN_47___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__DAC_GAIN_47___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__DAC_GAIN_47___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__TX_PWR_LV_LAA_47___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__TX_PWR_LV_LAA_47___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__TX_PWR_LV_N79_47___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__TX_PWR_LV_N79_47___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__BBF_GAIN_47___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__BBF_GAIN_47___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__UPC_GAIN_47___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__UPC_GAIN_47___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__DA_GAIN_47___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__DA_GAIN_47___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__XPA_GAIN_47___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47__XPA_GAIN_47___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_47___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48 (0x005EDCC0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__IPA_GAIN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__DAC_GAIN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__TX_PWR_LV_LAA_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__TX_PWR_LV_N79_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__BBF_GAIN_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__UPC_GAIN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__DA_GAIN_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__XPA_GAIN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__IPA_GAIN_48___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__IPA_GAIN_48___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__DAC_GAIN_48___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__DAC_GAIN_48___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__TX_PWR_LV_LAA_48___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__TX_PWR_LV_LAA_48___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__TX_PWR_LV_N79_48___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__TX_PWR_LV_N79_48___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__BBF_GAIN_48___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__BBF_GAIN_48___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__UPC_GAIN_48___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__UPC_GAIN_48___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__DA_GAIN_48___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__DA_GAIN_48___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__XPA_GAIN_48___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48__XPA_GAIN_48___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_48___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49 (0x005EDCC4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__IPA_GAIN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__DAC_GAIN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__TX_PWR_LV_LAA_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__TX_PWR_LV_N79_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__BBF_GAIN_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__UPC_GAIN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__DA_GAIN_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__XPA_GAIN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__IPA_GAIN_49___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__IPA_GAIN_49___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__DAC_GAIN_49___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__DAC_GAIN_49___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__TX_PWR_LV_LAA_49___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__TX_PWR_LV_LAA_49___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__TX_PWR_LV_N79_49___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__TX_PWR_LV_N79_49___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__BBF_GAIN_49___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__BBF_GAIN_49___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__UPC_GAIN_49___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__UPC_GAIN_49___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__DA_GAIN_49___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__DA_GAIN_49___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__XPA_GAIN_49___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49__XPA_GAIN_49___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_49___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50 (0x005EDCC8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__IPA_GAIN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__DAC_GAIN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__TX_PWR_LV_LAA_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__TX_PWR_LV_N79_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__BBF_GAIN_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__UPC_GAIN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__DA_GAIN_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__XPA_GAIN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__IPA_GAIN_50___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__IPA_GAIN_50___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__DAC_GAIN_50___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__DAC_GAIN_50___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__TX_PWR_LV_LAA_50___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__TX_PWR_LV_LAA_50___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__TX_PWR_LV_N79_50___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__TX_PWR_LV_N79_50___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__BBF_GAIN_50___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__BBF_GAIN_50___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__UPC_GAIN_50___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__UPC_GAIN_50___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__DA_GAIN_50___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__DA_GAIN_50___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__XPA_GAIN_50___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50__XPA_GAIN_50___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_50___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51 (0x005EDCCC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__IPA_GAIN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__DAC_GAIN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__TX_PWR_LV_LAA_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__TX_PWR_LV_N79_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__BBF_GAIN_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__UPC_GAIN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__DA_GAIN_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__XPA_GAIN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__IPA_GAIN_51___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__IPA_GAIN_51___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__DAC_GAIN_51___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__DAC_GAIN_51___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__TX_PWR_LV_LAA_51___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__TX_PWR_LV_LAA_51___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__TX_PWR_LV_N79_51___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__TX_PWR_LV_N79_51___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__BBF_GAIN_51___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__BBF_GAIN_51___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__UPC_GAIN_51___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__UPC_GAIN_51___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__DA_GAIN_51___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__DA_GAIN_51___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__XPA_GAIN_51___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51__XPA_GAIN_51___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_51___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52 (0x005EDCD0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__IPA_GAIN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__DAC_GAIN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__TX_PWR_LV_LAA_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__TX_PWR_LV_N79_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__BBF_GAIN_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__UPC_GAIN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__DA_GAIN_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__XPA_GAIN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__IPA_GAIN_52___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__IPA_GAIN_52___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__DAC_GAIN_52___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__DAC_GAIN_52___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__TX_PWR_LV_LAA_52___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__TX_PWR_LV_LAA_52___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__TX_PWR_LV_N79_52___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__TX_PWR_LV_N79_52___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__BBF_GAIN_52___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__BBF_GAIN_52___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__UPC_GAIN_52___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__UPC_GAIN_52___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__DA_GAIN_52___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__DA_GAIN_52___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__XPA_GAIN_52___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52__XPA_GAIN_52___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_52___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53 (0x005EDCD4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__IPA_GAIN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__DAC_GAIN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__TX_PWR_LV_LAA_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__TX_PWR_LV_N79_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__BBF_GAIN_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__UPC_GAIN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__DA_GAIN_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__XPA_GAIN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__IPA_GAIN_53___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__IPA_GAIN_53___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__DAC_GAIN_53___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__DAC_GAIN_53___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__TX_PWR_LV_LAA_53___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__TX_PWR_LV_LAA_53___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__TX_PWR_LV_N79_53___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__TX_PWR_LV_N79_53___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__BBF_GAIN_53___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__BBF_GAIN_53___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__UPC_GAIN_53___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__UPC_GAIN_53___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__DA_GAIN_53___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__DA_GAIN_53___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__XPA_GAIN_53___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53__XPA_GAIN_53___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_53___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54 (0x005EDCD8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__IPA_GAIN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__DAC_GAIN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__TX_PWR_LV_LAA_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__TX_PWR_LV_N79_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__BBF_GAIN_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__UPC_GAIN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__DA_GAIN_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__XPA_GAIN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__IPA_GAIN_54___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__IPA_GAIN_54___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__DAC_GAIN_54___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__DAC_GAIN_54___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__TX_PWR_LV_LAA_54___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__TX_PWR_LV_LAA_54___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__TX_PWR_LV_N79_54___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__TX_PWR_LV_N79_54___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__BBF_GAIN_54___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__BBF_GAIN_54___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__UPC_GAIN_54___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__UPC_GAIN_54___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__DA_GAIN_54___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__DA_GAIN_54___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__XPA_GAIN_54___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54__XPA_GAIN_54___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_54___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55 (0x005EDCDC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__IPA_GAIN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__DAC_GAIN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__TX_PWR_LV_LAA_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__TX_PWR_LV_N79_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__BBF_GAIN_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__UPC_GAIN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__DA_GAIN_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__XPA_GAIN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__IPA_GAIN_55___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__IPA_GAIN_55___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__DAC_GAIN_55___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__DAC_GAIN_55___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__TX_PWR_LV_LAA_55___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__TX_PWR_LV_LAA_55___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__TX_PWR_LV_N79_55___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__TX_PWR_LV_N79_55___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__BBF_GAIN_55___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__BBF_GAIN_55___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__UPC_GAIN_55___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__UPC_GAIN_55___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__DA_GAIN_55___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__DA_GAIN_55___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__XPA_GAIN_55___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55__XPA_GAIN_55___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_55___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56 (0x005EDCE0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__IPA_GAIN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__DAC_GAIN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__TX_PWR_LV_LAA_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__TX_PWR_LV_N79_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__BBF_GAIN_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__UPC_GAIN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__DA_GAIN_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__XPA_GAIN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__IPA_GAIN_56___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__IPA_GAIN_56___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__DAC_GAIN_56___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__DAC_GAIN_56___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__TX_PWR_LV_LAA_56___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__TX_PWR_LV_LAA_56___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__TX_PWR_LV_N79_56___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__TX_PWR_LV_N79_56___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__BBF_GAIN_56___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__BBF_GAIN_56___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__UPC_GAIN_56___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__UPC_GAIN_56___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__DA_GAIN_56___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__DA_GAIN_56___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__XPA_GAIN_56___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56__XPA_GAIN_56___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_56___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57 (0x005EDCE4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__IPA_GAIN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__DAC_GAIN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__TX_PWR_LV_LAA_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__TX_PWR_LV_N79_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__BBF_GAIN_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__UPC_GAIN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__DA_GAIN_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__XPA_GAIN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__IPA_GAIN_57___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__IPA_GAIN_57___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__DAC_GAIN_57___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__DAC_GAIN_57___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__TX_PWR_LV_LAA_57___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__TX_PWR_LV_LAA_57___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__TX_PWR_LV_N79_57___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__TX_PWR_LV_N79_57___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__BBF_GAIN_57___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__BBF_GAIN_57___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__UPC_GAIN_57___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__UPC_GAIN_57___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__DA_GAIN_57___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__DA_GAIN_57___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__XPA_GAIN_57___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57__XPA_GAIN_57___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_57___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58 (0x005EDCE8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__IPA_GAIN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__DAC_GAIN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__TX_PWR_LV_LAA_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__TX_PWR_LV_N79_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__BBF_GAIN_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__UPC_GAIN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__DA_GAIN_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__XPA_GAIN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__IPA_GAIN_58___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__IPA_GAIN_58___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__DAC_GAIN_58___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__DAC_GAIN_58___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__TX_PWR_LV_LAA_58___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__TX_PWR_LV_LAA_58___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__TX_PWR_LV_N79_58___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__TX_PWR_LV_N79_58___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__BBF_GAIN_58___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__BBF_GAIN_58___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__UPC_GAIN_58___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__UPC_GAIN_58___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__DA_GAIN_58___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__DA_GAIN_58___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__XPA_GAIN_58___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58__XPA_GAIN_58___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_58___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59 (0x005EDCEC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__IPA_GAIN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__DAC_GAIN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__TX_PWR_LV_LAA_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__TX_PWR_LV_N79_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__BBF_GAIN_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__UPC_GAIN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__DA_GAIN_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__XPA_GAIN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__IPA_GAIN_59___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__IPA_GAIN_59___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__DAC_GAIN_59___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__DAC_GAIN_59___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__TX_PWR_LV_LAA_59___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__TX_PWR_LV_LAA_59___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__TX_PWR_LV_N79_59___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__TX_PWR_LV_N79_59___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__BBF_GAIN_59___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__BBF_GAIN_59___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__UPC_GAIN_59___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__UPC_GAIN_59___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__DA_GAIN_59___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__DA_GAIN_59___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__XPA_GAIN_59___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59__XPA_GAIN_59___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_59___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60 (0x005EDCF0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__IPA_GAIN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__DAC_GAIN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__TX_PWR_LV_LAA_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__TX_PWR_LV_N79_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__BBF_GAIN_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__UPC_GAIN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__DA_GAIN_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__XPA_GAIN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__IPA_GAIN_60___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__IPA_GAIN_60___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__DAC_GAIN_60___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__DAC_GAIN_60___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__TX_PWR_LV_LAA_60___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__TX_PWR_LV_LAA_60___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__TX_PWR_LV_N79_60___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__TX_PWR_LV_N79_60___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__BBF_GAIN_60___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__BBF_GAIN_60___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__UPC_GAIN_60___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__UPC_GAIN_60___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__DA_GAIN_60___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__DA_GAIN_60___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__XPA_GAIN_60___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60__XPA_GAIN_60___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_60___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61 (0x005EDCF4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__IPA_GAIN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__DAC_GAIN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__TX_PWR_LV_LAA_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__TX_PWR_LV_N79_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__BBF_GAIN_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__UPC_GAIN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__DA_GAIN_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__XPA_GAIN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__IPA_GAIN_61___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__IPA_GAIN_61___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__DAC_GAIN_61___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__DAC_GAIN_61___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__TX_PWR_LV_LAA_61___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__TX_PWR_LV_LAA_61___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__TX_PWR_LV_N79_61___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__TX_PWR_LV_N79_61___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__BBF_GAIN_61___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__BBF_GAIN_61___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__UPC_GAIN_61___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__UPC_GAIN_61___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__DA_GAIN_61___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__DA_GAIN_61___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__XPA_GAIN_61___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61__XPA_GAIN_61___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_61___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62 (0x005EDCF8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__IPA_GAIN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__DAC_GAIN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__TX_PWR_LV_LAA_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__TX_PWR_LV_N79_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__BBF_GAIN_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__UPC_GAIN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__DA_GAIN_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__XPA_GAIN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__IPA_GAIN_62___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__IPA_GAIN_62___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__DAC_GAIN_62___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__DAC_GAIN_62___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__TX_PWR_LV_LAA_62___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__TX_PWR_LV_LAA_62___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__TX_PWR_LV_N79_62___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__TX_PWR_LV_N79_62___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__BBF_GAIN_62___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__BBF_GAIN_62___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__UPC_GAIN_62___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__UPC_GAIN_62___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__DA_GAIN_62___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__DA_GAIN_62___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__XPA_GAIN_62___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62__XPA_GAIN_62___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_62___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63 (0x005EDCFC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__IPA_GAIN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__DAC_GAIN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__TX_PWR_LV_LAA_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__TX_PWR_LV_N79_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__BBF_GAIN_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__UPC_GAIN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__DA_GAIN_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__XPA_GAIN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__IPA_GAIN_63___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__IPA_GAIN_63___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__DAC_GAIN_63___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__DAC_GAIN_63___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__TX_PWR_LV_LAA_63___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__TX_PWR_LV_LAA_63___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__TX_PWR_LV_N79_63___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__TX_PWR_LV_N79_63___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__BBF_GAIN_63___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__BBF_GAIN_63___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__UPC_GAIN_63___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__UPC_GAIN_63___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__DA_GAIN_63___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__DA_GAIN_63___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__XPA_GAIN_63___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63__XPA_GAIN_63___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_63___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64 (0x005EDD00) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__IPA_GAIN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__DAC_GAIN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__TX_PWR_LV_LAA_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__TX_PWR_LV_N79_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__BBF_GAIN_64___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__UPC_GAIN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__DA_GAIN_64___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__XPA_GAIN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__IPA_GAIN_64___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__IPA_GAIN_64___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__DAC_GAIN_64___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__DAC_GAIN_64___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__TX_PWR_LV_LAA_64___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__TX_PWR_LV_LAA_64___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__TX_PWR_LV_N79_64___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__TX_PWR_LV_N79_64___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__BBF_GAIN_64___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__BBF_GAIN_64___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__UPC_GAIN_64___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__UPC_GAIN_64___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__DA_GAIN_64___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__DA_GAIN_64___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__XPA_GAIN_64___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64__XPA_GAIN_64___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_64___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65 (0x005EDD04) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__IPA_GAIN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__DAC_GAIN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__TX_PWR_LV_LAA_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__TX_PWR_LV_N79_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__BBF_GAIN_65___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__UPC_GAIN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__DA_GAIN_65___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__XPA_GAIN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__IPA_GAIN_65___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__IPA_GAIN_65___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__DAC_GAIN_65___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__DAC_GAIN_65___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__TX_PWR_LV_LAA_65___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__TX_PWR_LV_LAA_65___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__TX_PWR_LV_N79_65___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__TX_PWR_LV_N79_65___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__BBF_GAIN_65___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__BBF_GAIN_65___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__UPC_GAIN_65___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__UPC_GAIN_65___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__DA_GAIN_65___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__DA_GAIN_65___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__XPA_GAIN_65___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65__XPA_GAIN_65___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_65___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66 (0x005EDD08) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__IPA_GAIN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__DAC_GAIN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__TX_PWR_LV_LAA_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__TX_PWR_LV_N79_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__BBF_GAIN_66___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__UPC_GAIN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__DA_GAIN_66___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__XPA_GAIN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__IPA_GAIN_66___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__IPA_GAIN_66___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__DAC_GAIN_66___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__DAC_GAIN_66___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__TX_PWR_LV_LAA_66___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__TX_PWR_LV_LAA_66___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__TX_PWR_LV_N79_66___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__TX_PWR_LV_N79_66___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__BBF_GAIN_66___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__BBF_GAIN_66___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__UPC_GAIN_66___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__UPC_GAIN_66___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__DA_GAIN_66___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__DA_GAIN_66___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__XPA_GAIN_66___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66__XPA_GAIN_66___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_66___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67 (0x005EDD0C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__IPA_GAIN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__DAC_GAIN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__TX_PWR_LV_LAA_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__TX_PWR_LV_N79_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__BBF_GAIN_67___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__UPC_GAIN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__DA_GAIN_67___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__XPA_GAIN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__IPA_GAIN_67___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__IPA_GAIN_67___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__DAC_GAIN_67___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__DAC_GAIN_67___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__TX_PWR_LV_LAA_67___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__TX_PWR_LV_LAA_67___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__TX_PWR_LV_N79_67___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__TX_PWR_LV_N79_67___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__BBF_GAIN_67___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__BBF_GAIN_67___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__UPC_GAIN_67___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__UPC_GAIN_67___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__DA_GAIN_67___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__DA_GAIN_67___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__XPA_GAIN_67___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67__XPA_GAIN_67___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_67___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68 (0x005EDD10) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__IPA_GAIN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__DAC_GAIN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__TX_PWR_LV_LAA_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__TX_PWR_LV_N79_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__BBF_GAIN_68___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__UPC_GAIN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__DA_GAIN_68___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__XPA_GAIN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__IPA_GAIN_68___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__IPA_GAIN_68___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__DAC_GAIN_68___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__DAC_GAIN_68___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__TX_PWR_LV_LAA_68___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__TX_PWR_LV_LAA_68___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__TX_PWR_LV_N79_68___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__TX_PWR_LV_N79_68___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__BBF_GAIN_68___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__BBF_GAIN_68___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__UPC_GAIN_68___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__UPC_GAIN_68___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__DA_GAIN_68___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__DA_GAIN_68___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__XPA_GAIN_68___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68__XPA_GAIN_68___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_68___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69 (0x005EDD14) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__IPA_GAIN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__DAC_GAIN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__TX_PWR_LV_LAA_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__TX_PWR_LV_N79_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__BBF_GAIN_69___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__UPC_GAIN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__DA_GAIN_69___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__XPA_GAIN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__IPA_GAIN_69___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__IPA_GAIN_69___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__DAC_GAIN_69___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__DAC_GAIN_69___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__TX_PWR_LV_LAA_69___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__TX_PWR_LV_LAA_69___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__TX_PWR_LV_N79_69___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__TX_PWR_LV_N79_69___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__BBF_GAIN_69___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__BBF_GAIN_69___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__UPC_GAIN_69___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__UPC_GAIN_69___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__DA_GAIN_69___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__DA_GAIN_69___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__XPA_GAIN_69___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69__XPA_GAIN_69___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_69___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70 (0x005EDD18) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__IPA_GAIN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__DAC_GAIN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__TX_PWR_LV_LAA_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__TX_PWR_LV_N79_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__BBF_GAIN_70___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__UPC_GAIN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__DA_GAIN_70___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__XPA_GAIN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__IPA_GAIN_70___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__IPA_GAIN_70___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__DAC_GAIN_70___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__DAC_GAIN_70___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__TX_PWR_LV_LAA_70___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__TX_PWR_LV_LAA_70___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__TX_PWR_LV_N79_70___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__TX_PWR_LV_N79_70___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__BBF_GAIN_70___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__BBF_GAIN_70___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__UPC_GAIN_70___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__UPC_GAIN_70___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__DA_GAIN_70___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__DA_GAIN_70___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__XPA_GAIN_70___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70__XPA_GAIN_70___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_70___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71 (0x005EDD1C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__IPA_GAIN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__DAC_GAIN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__TX_PWR_LV_LAA_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__TX_PWR_LV_N79_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__BBF_GAIN_71___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__UPC_GAIN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__DA_GAIN_71___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__XPA_GAIN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__IPA_GAIN_71___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__IPA_GAIN_71___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__DAC_GAIN_71___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__DAC_GAIN_71___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__TX_PWR_LV_LAA_71___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__TX_PWR_LV_LAA_71___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__TX_PWR_LV_N79_71___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__TX_PWR_LV_N79_71___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__BBF_GAIN_71___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__BBF_GAIN_71___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__UPC_GAIN_71___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__UPC_GAIN_71___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__DA_GAIN_71___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__DA_GAIN_71___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__XPA_GAIN_71___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71__XPA_GAIN_71___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_71___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72 (0x005EDD20) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__IPA_GAIN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__DAC_GAIN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__TX_PWR_LV_LAA_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__TX_PWR_LV_N79_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__BBF_GAIN_72___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__UPC_GAIN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__DA_GAIN_72___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__XPA_GAIN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__IPA_GAIN_72___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__IPA_GAIN_72___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__DAC_GAIN_72___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__DAC_GAIN_72___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__TX_PWR_LV_LAA_72___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__TX_PWR_LV_LAA_72___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__TX_PWR_LV_N79_72___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__TX_PWR_LV_N79_72___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__BBF_GAIN_72___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__BBF_GAIN_72___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__UPC_GAIN_72___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__UPC_GAIN_72___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__DA_GAIN_72___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__DA_GAIN_72___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__XPA_GAIN_72___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72__XPA_GAIN_72___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_72___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73 (0x005EDD24) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__IPA_GAIN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__DAC_GAIN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__TX_PWR_LV_LAA_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__TX_PWR_LV_N79_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__BBF_GAIN_73___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__UPC_GAIN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__DA_GAIN_73___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__XPA_GAIN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__IPA_GAIN_73___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__IPA_GAIN_73___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__DAC_GAIN_73___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__DAC_GAIN_73___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__TX_PWR_LV_LAA_73___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__TX_PWR_LV_LAA_73___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__TX_PWR_LV_N79_73___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__TX_PWR_LV_N79_73___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__BBF_GAIN_73___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__BBF_GAIN_73___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__UPC_GAIN_73___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__UPC_GAIN_73___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__DA_GAIN_73___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__DA_GAIN_73___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__XPA_GAIN_73___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73__XPA_GAIN_73___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_73___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74 (0x005EDD28) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__IPA_GAIN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__DAC_GAIN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__TX_PWR_LV_LAA_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__TX_PWR_LV_N79_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__BBF_GAIN_74___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__UPC_GAIN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__DA_GAIN_74___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__XPA_GAIN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__IPA_GAIN_74___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__IPA_GAIN_74___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__DAC_GAIN_74___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__DAC_GAIN_74___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__TX_PWR_LV_LAA_74___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__TX_PWR_LV_LAA_74___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__TX_PWR_LV_N79_74___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__TX_PWR_LV_N79_74___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__BBF_GAIN_74___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__BBF_GAIN_74___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__UPC_GAIN_74___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__UPC_GAIN_74___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__DA_GAIN_74___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__DA_GAIN_74___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__XPA_GAIN_74___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74__XPA_GAIN_74___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_74___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75 (0x005EDD2C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__IPA_GAIN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__DAC_GAIN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__TX_PWR_LV_LAA_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__TX_PWR_LV_N79_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__BBF_GAIN_75___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__UPC_GAIN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__DA_GAIN_75___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__XPA_GAIN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__IPA_GAIN_75___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__IPA_GAIN_75___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__DAC_GAIN_75___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__DAC_GAIN_75___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__TX_PWR_LV_LAA_75___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__TX_PWR_LV_LAA_75___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__TX_PWR_LV_N79_75___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__TX_PWR_LV_N79_75___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__BBF_GAIN_75___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__BBF_GAIN_75___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__UPC_GAIN_75___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__UPC_GAIN_75___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__DA_GAIN_75___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__DA_GAIN_75___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__XPA_GAIN_75___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75__XPA_GAIN_75___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_75___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76 (0x005EDD30) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__IPA_GAIN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__DAC_GAIN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__TX_PWR_LV_LAA_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__TX_PWR_LV_N79_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__BBF_GAIN_76___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__UPC_GAIN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__DA_GAIN_76___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__XPA_GAIN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__IPA_GAIN_76___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__IPA_GAIN_76___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__DAC_GAIN_76___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__DAC_GAIN_76___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__TX_PWR_LV_LAA_76___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__TX_PWR_LV_LAA_76___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__TX_PWR_LV_N79_76___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__TX_PWR_LV_N79_76___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__BBF_GAIN_76___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__BBF_GAIN_76___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__UPC_GAIN_76___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__UPC_GAIN_76___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__DA_GAIN_76___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__DA_GAIN_76___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__XPA_GAIN_76___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76__XPA_GAIN_76___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_76___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77 (0x005EDD34) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__IPA_GAIN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__DAC_GAIN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__TX_PWR_LV_LAA_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__TX_PWR_LV_N79_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__BBF_GAIN_77___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__UPC_GAIN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__DA_GAIN_77___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__XPA_GAIN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__IPA_GAIN_77___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__IPA_GAIN_77___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__DAC_GAIN_77___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__DAC_GAIN_77___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__TX_PWR_LV_LAA_77___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__TX_PWR_LV_LAA_77___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__TX_PWR_LV_N79_77___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__TX_PWR_LV_N79_77___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__BBF_GAIN_77___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__BBF_GAIN_77___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__UPC_GAIN_77___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__UPC_GAIN_77___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__DA_GAIN_77___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__DA_GAIN_77___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__XPA_GAIN_77___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77__XPA_GAIN_77___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_77___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78 (0x005EDD38) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__IPA_GAIN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__DAC_GAIN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__TX_PWR_LV_LAA_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__TX_PWR_LV_N79_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__BBF_GAIN_78___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__UPC_GAIN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__DA_GAIN_78___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__XPA_GAIN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__IPA_GAIN_78___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__IPA_GAIN_78___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__DAC_GAIN_78___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__DAC_GAIN_78___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__TX_PWR_LV_LAA_78___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__TX_PWR_LV_LAA_78___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__TX_PWR_LV_N79_78___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__TX_PWR_LV_N79_78___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__BBF_GAIN_78___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__BBF_GAIN_78___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__UPC_GAIN_78___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__UPC_GAIN_78___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__DA_GAIN_78___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__DA_GAIN_78___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__XPA_GAIN_78___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78__XPA_GAIN_78___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_78___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79 (0x005EDD3C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__IPA_GAIN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__DAC_GAIN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__TX_PWR_LV_LAA_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__TX_PWR_LV_N79_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__BBF_GAIN_79___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__UPC_GAIN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__DA_GAIN_79___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__XPA_GAIN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__IPA_GAIN_79___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__IPA_GAIN_79___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__DAC_GAIN_79___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__DAC_GAIN_79___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__TX_PWR_LV_LAA_79___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__TX_PWR_LV_LAA_79___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__TX_PWR_LV_N79_79___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__TX_PWR_LV_N79_79___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__BBF_GAIN_79___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__BBF_GAIN_79___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__UPC_GAIN_79___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__UPC_GAIN_79___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__DA_GAIN_79___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__DA_GAIN_79___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__XPA_GAIN_79___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79__XPA_GAIN_79___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_79___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80 (0x005EDD40) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__IPA_GAIN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__DAC_GAIN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__TX_PWR_LV_LAA_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__TX_PWR_LV_N79_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__BBF_GAIN_80___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__UPC_GAIN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__DA_GAIN_80___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__XPA_GAIN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__IPA_GAIN_80___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__IPA_GAIN_80___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__DAC_GAIN_80___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__DAC_GAIN_80___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__TX_PWR_LV_LAA_80___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__TX_PWR_LV_LAA_80___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__TX_PWR_LV_N79_80___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__TX_PWR_LV_N79_80___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__BBF_GAIN_80___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__BBF_GAIN_80___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__UPC_GAIN_80___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__UPC_GAIN_80___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__DA_GAIN_80___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__DA_GAIN_80___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__XPA_GAIN_80___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80__XPA_GAIN_80___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_80___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81 (0x005EDD44) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__IPA_GAIN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__DAC_GAIN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__TX_PWR_LV_LAA_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__TX_PWR_LV_N79_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__BBF_GAIN_81___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__UPC_GAIN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__DA_GAIN_81___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__XPA_GAIN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__IPA_GAIN_81___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__IPA_GAIN_81___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__DAC_GAIN_81___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__DAC_GAIN_81___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__TX_PWR_LV_LAA_81___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__TX_PWR_LV_LAA_81___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__TX_PWR_LV_N79_81___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__TX_PWR_LV_N79_81___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__BBF_GAIN_81___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__BBF_GAIN_81___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__UPC_GAIN_81___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__UPC_GAIN_81___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__DA_GAIN_81___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__DA_GAIN_81___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__XPA_GAIN_81___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81__XPA_GAIN_81___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_81___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82 (0x005EDD48) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__IPA_GAIN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__DAC_GAIN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__TX_PWR_LV_LAA_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__TX_PWR_LV_N79_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__BBF_GAIN_82___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__UPC_GAIN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__DA_GAIN_82___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__XPA_GAIN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__IPA_GAIN_82___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__IPA_GAIN_82___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__DAC_GAIN_82___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__DAC_GAIN_82___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__TX_PWR_LV_LAA_82___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__TX_PWR_LV_LAA_82___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__TX_PWR_LV_N79_82___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__TX_PWR_LV_N79_82___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__BBF_GAIN_82___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__BBF_GAIN_82___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__UPC_GAIN_82___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__UPC_GAIN_82___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__DA_GAIN_82___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__DA_GAIN_82___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__XPA_GAIN_82___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82__XPA_GAIN_82___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_82___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83 (0x005EDD4C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__IPA_GAIN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__DAC_GAIN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__TX_PWR_LV_LAA_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__TX_PWR_LV_N79_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__BBF_GAIN_83___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__UPC_GAIN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__DA_GAIN_83___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__XPA_GAIN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__IPA_GAIN_83___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__IPA_GAIN_83___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__DAC_GAIN_83___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__DAC_GAIN_83___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__TX_PWR_LV_LAA_83___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__TX_PWR_LV_LAA_83___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__TX_PWR_LV_N79_83___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__TX_PWR_LV_N79_83___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__BBF_GAIN_83___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__BBF_GAIN_83___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__UPC_GAIN_83___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__UPC_GAIN_83___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__DA_GAIN_83___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__DA_GAIN_83___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__XPA_GAIN_83___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83__XPA_GAIN_83___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_83___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84 (0x005EDD50) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__IPA_GAIN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__DAC_GAIN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__TX_PWR_LV_LAA_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__TX_PWR_LV_N79_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__BBF_GAIN_84___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__UPC_GAIN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__DA_GAIN_84___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__XPA_GAIN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__IPA_GAIN_84___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__IPA_GAIN_84___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__DAC_GAIN_84___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__DAC_GAIN_84___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__TX_PWR_LV_LAA_84___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__TX_PWR_LV_LAA_84___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__TX_PWR_LV_N79_84___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__TX_PWR_LV_N79_84___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__BBF_GAIN_84___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__BBF_GAIN_84___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__UPC_GAIN_84___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__UPC_GAIN_84___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__DA_GAIN_84___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__DA_GAIN_84___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__XPA_GAIN_84___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84__XPA_GAIN_84___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_84___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85 (0x005EDD54) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__IPA_GAIN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__DAC_GAIN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__TX_PWR_LV_LAA_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__TX_PWR_LV_N79_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__BBF_GAIN_85___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__UPC_GAIN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__DA_GAIN_85___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__XPA_GAIN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__IPA_GAIN_85___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__IPA_GAIN_85___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__DAC_GAIN_85___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__DAC_GAIN_85___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__TX_PWR_LV_LAA_85___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__TX_PWR_LV_LAA_85___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__TX_PWR_LV_N79_85___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__TX_PWR_LV_N79_85___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__BBF_GAIN_85___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__BBF_GAIN_85___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__UPC_GAIN_85___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__UPC_GAIN_85___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__DA_GAIN_85___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__DA_GAIN_85___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__XPA_GAIN_85___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85__XPA_GAIN_85___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_85___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86 (0x005EDD58) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__IPA_GAIN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__DAC_GAIN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__TX_PWR_LV_LAA_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__TX_PWR_LV_N79_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__BBF_GAIN_86___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__UPC_GAIN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__DA_GAIN_86___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__XPA_GAIN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__IPA_GAIN_86___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__IPA_GAIN_86___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__DAC_GAIN_86___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__DAC_GAIN_86___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__TX_PWR_LV_LAA_86___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__TX_PWR_LV_LAA_86___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__TX_PWR_LV_N79_86___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__TX_PWR_LV_N79_86___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__BBF_GAIN_86___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__BBF_GAIN_86___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__UPC_GAIN_86___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__UPC_GAIN_86___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__DA_GAIN_86___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__DA_GAIN_86___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__XPA_GAIN_86___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86__XPA_GAIN_86___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_86___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87 (0x005EDD5C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__IPA_GAIN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__DAC_GAIN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__TX_PWR_LV_LAA_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__TX_PWR_LV_N79_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__BBF_GAIN_87___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__UPC_GAIN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__DA_GAIN_87___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__XPA_GAIN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__IPA_GAIN_87___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__IPA_GAIN_87___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__DAC_GAIN_87___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__DAC_GAIN_87___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__TX_PWR_LV_LAA_87___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__TX_PWR_LV_LAA_87___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__TX_PWR_LV_N79_87___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__TX_PWR_LV_N79_87___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__BBF_GAIN_87___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__BBF_GAIN_87___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__UPC_GAIN_87___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__UPC_GAIN_87___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__DA_GAIN_87___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__DA_GAIN_87___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__XPA_GAIN_87___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87__XPA_GAIN_87___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_87___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88 (0x005EDD60) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__IPA_GAIN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__DAC_GAIN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__TX_PWR_LV_LAA_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__TX_PWR_LV_N79_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__BBF_GAIN_88___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__UPC_GAIN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__DA_GAIN_88___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__XPA_GAIN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__IPA_GAIN_88___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__IPA_GAIN_88___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__DAC_GAIN_88___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__DAC_GAIN_88___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__TX_PWR_LV_LAA_88___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__TX_PWR_LV_LAA_88___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__TX_PWR_LV_N79_88___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__TX_PWR_LV_N79_88___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__BBF_GAIN_88___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__BBF_GAIN_88___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__UPC_GAIN_88___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__UPC_GAIN_88___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__DA_GAIN_88___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__DA_GAIN_88___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__XPA_GAIN_88___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88__XPA_GAIN_88___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_88___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89 (0x005EDD64) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__IPA_GAIN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__DAC_GAIN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__TX_PWR_LV_LAA_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__TX_PWR_LV_N79_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__BBF_GAIN_89___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__UPC_GAIN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__DA_GAIN_89___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__XPA_GAIN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__IPA_GAIN_89___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__IPA_GAIN_89___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__DAC_GAIN_89___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__DAC_GAIN_89___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__TX_PWR_LV_LAA_89___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__TX_PWR_LV_LAA_89___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__TX_PWR_LV_N79_89___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__TX_PWR_LV_N79_89___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__BBF_GAIN_89___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__BBF_GAIN_89___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__UPC_GAIN_89___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__UPC_GAIN_89___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__DA_GAIN_89___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__DA_GAIN_89___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__XPA_GAIN_89___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89__XPA_GAIN_89___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_89___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90 (0x005EDD68) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__IPA_GAIN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__DAC_GAIN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__TX_PWR_LV_LAA_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__TX_PWR_LV_N79_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__BBF_GAIN_90___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__UPC_GAIN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__DA_GAIN_90___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__XPA_GAIN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__IPA_GAIN_90___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__IPA_GAIN_90___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__DAC_GAIN_90___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__DAC_GAIN_90___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__TX_PWR_LV_LAA_90___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__TX_PWR_LV_LAA_90___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__TX_PWR_LV_N79_90___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__TX_PWR_LV_N79_90___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__BBF_GAIN_90___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__BBF_GAIN_90___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__UPC_GAIN_90___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__UPC_GAIN_90___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__DA_GAIN_90___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__DA_GAIN_90___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__XPA_GAIN_90___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90__XPA_GAIN_90___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_90___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91 (0x005EDD6C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__IPA_GAIN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__DAC_GAIN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__TX_PWR_LV_LAA_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__TX_PWR_LV_N79_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__BBF_GAIN_91___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__UPC_GAIN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__DA_GAIN_91___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__XPA_GAIN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__IPA_GAIN_91___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__IPA_GAIN_91___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__DAC_GAIN_91___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__DAC_GAIN_91___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__TX_PWR_LV_LAA_91___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__TX_PWR_LV_LAA_91___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__TX_PWR_LV_N79_91___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__TX_PWR_LV_N79_91___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__BBF_GAIN_91___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__BBF_GAIN_91___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__UPC_GAIN_91___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__UPC_GAIN_91___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__DA_GAIN_91___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__DA_GAIN_91___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__XPA_GAIN_91___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91__XPA_GAIN_91___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_91___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92 (0x005EDD70) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__IPA_GAIN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__DAC_GAIN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__TX_PWR_LV_LAA_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__TX_PWR_LV_N79_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__BBF_GAIN_92___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__UPC_GAIN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__DA_GAIN_92___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__XPA_GAIN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__IPA_GAIN_92___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__IPA_GAIN_92___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__DAC_GAIN_92___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__DAC_GAIN_92___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__TX_PWR_LV_LAA_92___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__TX_PWR_LV_LAA_92___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__TX_PWR_LV_N79_92___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__TX_PWR_LV_N79_92___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__BBF_GAIN_92___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__BBF_GAIN_92___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__UPC_GAIN_92___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__UPC_GAIN_92___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__DA_GAIN_92___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__DA_GAIN_92___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__XPA_GAIN_92___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92__XPA_GAIN_92___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_92___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93 (0x005EDD74) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__IPA_GAIN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__DAC_GAIN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__TX_PWR_LV_LAA_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__TX_PWR_LV_N79_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__BBF_GAIN_93___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__UPC_GAIN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__DA_GAIN_93___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__XPA_GAIN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__IPA_GAIN_93___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__IPA_GAIN_93___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__DAC_GAIN_93___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__DAC_GAIN_93___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__TX_PWR_LV_LAA_93___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__TX_PWR_LV_LAA_93___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__TX_PWR_LV_N79_93___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__TX_PWR_LV_N79_93___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__BBF_GAIN_93___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__BBF_GAIN_93___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__UPC_GAIN_93___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__UPC_GAIN_93___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__DA_GAIN_93___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__DA_GAIN_93___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__XPA_GAIN_93___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93__XPA_GAIN_93___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_93___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94 (0x005EDD78) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__IPA_GAIN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__DAC_GAIN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__TX_PWR_LV_LAA_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__TX_PWR_LV_N79_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__BBF_GAIN_94___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__UPC_GAIN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__DA_GAIN_94___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__XPA_GAIN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__IPA_GAIN_94___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__IPA_GAIN_94___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__DAC_GAIN_94___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__DAC_GAIN_94___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__TX_PWR_LV_LAA_94___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__TX_PWR_LV_LAA_94___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__TX_PWR_LV_N79_94___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__TX_PWR_LV_N79_94___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__BBF_GAIN_94___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__BBF_GAIN_94___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__UPC_GAIN_94___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__UPC_GAIN_94___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__DA_GAIN_94___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__DA_GAIN_94___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__XPA_GAIN_94___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94__XPA_GAIN_94___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_94___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95 (0x005EDD7C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__IPA_GAIN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__DAC_GAIN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__TX_PWR_LV_LAA_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__TX_PWR_LV_N79_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__BBF_GAIN_95___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__UPC_GAIN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__DA_GAIN_95___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__XPA_GAIN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__IPA_GAIN_95___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__IPA_GAIN_95___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__DAC_GAIN_95___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__DAC_GAIN_95___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__TX_PWR_LV_LAA_95___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__TX_PWR_LV_LAA_95___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__TX_PWR_LV_N79_95___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__TX_PWR_LV_N79_95___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__BBF_GAIN_95___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__BBF_GAIN_95___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__UPC_GAIN_95___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__UPC_GAIN_95___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__DA_GAIN_95___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__DA_GAIN_95___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__XPA_GAIN_95___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95__XPA_GAIN_95___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_95___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96 (0x005EDD80) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__IPA_GAIN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__DAC_GAIN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__TX_PWR_LV_LAA_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__TX_PWR_LV_N79_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__BBF_GAIN_96___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__UPC_GAIN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__DA_GAIN_96___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__XPA_GAIN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__IPA_GAIN_96___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__IPA_GAIN_96___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__DAC_GAIN_96___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__DAC_GAIN_96___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__TX_PWR_LV_LAA_96___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__TX_PWR_LV_LAA_96___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__TX_PWR_LV_N79_96___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__TX_PWR_LV_N79_96___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__BBF_GAIN_96___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__BBF_GAIN_96___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__UPC_GAIN_96___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__UPC_GAIN_96___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__DA_GAIN_96___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__DA_GAIN_96___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__XPA_GAIN_96___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96__XPA_GAIN_96___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_96___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97 (0x005EDD84) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__IPA_GAIN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__DAC_GAIN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__TX_PWR_LV_LAA_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__TX_PWR_LV_N79_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__BBF_GAIN_97___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__UPC_GAIN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__DA_GAIN_97___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__XPA_GAIN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__IPA_GAIN_97___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__IPA_GAIN_97___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__DAC_GAIN_97___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__DAC_GAIN_97___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__TX_PWR_LV_LAA_97___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__TX_PWR_LV_LAA_97___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__TX_PWR_LV_N79_97___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__TX_PWR_LV_N79_97___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__BBF_GAIN_97___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__BBF_GAIN_97___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__UPC_GAIN_97___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__UPC_GAIN_97___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__DA_GAIN_97___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__DA_GAIN_97___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__XPA_GAIN_97___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97__XPA_GAIN_97___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_97___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98 (0x005EDD88) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__IPA_GAIN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__DAC_GAIN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__TX_PWR_LV_LAA_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__TX_PWR_LV_N79_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__BBF_GAIN_98___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__UPC_GAIN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__DA_GAIN_98___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__XPA_GAIN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__IPA_GAIN_98___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__IPA_GAIN_98___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__DAC_GAIN_98___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__DAC_GAIN_98___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__TX_PWR_LV_LAA_98___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__TX_PWR_LV_LAA_98___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__TX_PWR_LV_N79_98___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__TX_PWR_LV_N79_98___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__BBF_GAIN_98___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__BBF_GAIN_98___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__UPC_GAIN_98___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__UPC_GAIN_98___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__DA_GAIN_98___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__DA_GAIN_98___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__XPA_GAIN_98___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98__XPA_GAIN_98___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_98___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99 (0x005EDD8C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__IPA_GAIN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__DAC_GAIN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__TX_PWR_LV_LAA_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__TX_PWR_LV_N79_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__BBF_GAIN_99___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__UPC_GAIN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__DA_GAIN_99___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__XPA_GAIN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__IPA_GAIN_99___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__IPA_GAIN_99___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__DAC_GAIN_99___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__DAC_GAIN_99___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__TX_PWR_LV_LAA_99___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__TX_PWR_LV_LAA_99___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__TX_PWR_LV_N79_99___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__TX_PWR_LV_N79_99___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__BBF_GAIN_99___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__BBF_GAIN_99___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__UPC_GAIN_99___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__UPC_GAIN_99___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__DA_GAIN_99___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__DA_GAIN_99___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__XPA_GAIN_99___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99__XPA_GAIN_99___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_99___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100 (0x005EDD90) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__IPA_GAIN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__DAC_GAIN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__TX_PWR_LV_LAA_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__TX_PWR_LV_N79_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__BBF_GAIN_100___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__UPC_GAIN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__DA_GAIN_100___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__XPA_GAIN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__IPA_GAIN_100___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__IPA_GAIN_100___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__DAC_GAIN_100___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__DAC_GAIN_100___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__TX_PWR_LV_LAA_100___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__TX_PWR_LV_LAA_100___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__TX_PWR_LV_N79_100___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__TX_PWR_LV_N79_100___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__BBF_GAIN_100___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__BBF_GAIN_100___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__UPC_GAIN_100___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__UPC_GAIN_100___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__DA_GAIN_100___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__DA_GAIN_100___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__XPA_GAIN_100___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100__XPA_GAIN_100___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_100___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101 (0x005EDD94) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__IPA_GAIN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__DAC_GAIN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__TX_PWR_LV_LAA_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__TX_PWR_LV_N79_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__BBF_GAIN_101___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__UPC_GAIN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__DA_GAIN_101___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__XPA_GAIN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__IPA_GAIN_101___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__IPA_GAIN_101___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__DAC_GAIN_101___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__DAC_GAIN_101___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__TX_PWR_LV_LAA_101___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__TX_PWR_LV_LAA_101___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__TX_PWR_LV_N79_101___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__TX_PWR_LV_N79_101___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__BBF_GAIN_101___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__BBF_GAIN_101___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__UPC_GAIN_101___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__UPC_GAIN_101___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__DA_GAIN_101___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__DA_GAIN_101___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__XPA_GAIN_101___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101__XPA_GAIN_101___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_101___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102 (0x005EDD98) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__IPA_GAIN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__DAC_GAIN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__TX_PWR_LV_LAA_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__TX_PWR_LV_N79_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__BBF_GAIN_102___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__UPC_GAIN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__DA_GAIN_102___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__XPA_GAIN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__IPA_GAIN_102___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__IPA_GAIN_102___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__DAC_GAIN_102___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__DAC_GAIN_102___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__TX_PWR_LV_LAA_102___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__TX_PWR_LV_LAA_102___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__TX_PWR_LV_N79_102___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__TX_PWR_LV_N79_102___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__BBF_GAIN_102___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__BBF_GAIN_102___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__UPC_GAIN_102___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__UPC_GAIN_102___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__DA_GAIN_102___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__DA_GAIN_102___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__XPA_GAIN_102___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102__XPA_GAIN_102___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_102___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103 (0x005EDD9C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__IPA_GAIN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__DAC_GAIN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__TX_PWR_LV_LAA_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__TX_PWR_LV_N79_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__BBF_GAIN_103___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__UPC_GAIN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__DA_GAIN_103___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__XPA_GAIN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__IPA_GAIN_103___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__IPA_GAIN_103___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__DAC_GAIN_103___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__DAC_GAIN_103___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__TX_PWR_LV_LAA_103___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__TX_PWR_LV_LAA_103___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__TX_PWR_LV_N79_103___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__TX_PWR_LV_N79_103___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__BBF_GAIN_103___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__BBF_GAIN_103___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__UPC_GAIN_103___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__UPC_GAIN_103___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__DA_GAIN_103___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__DA_GAIN_103___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__XPA_GAIN_103___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103__XPA_GAIN_103___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_103___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104 (0x005EDDA0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__IPA_GAIN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__DAC_GAIN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__TX_PWR_LV_LAA_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__TX_PWR_LV_N79_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__BBF_GAIN_104___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__UPC_GAIN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__DA_GAIN_104___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__XPA_GAIN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__IPA_GAIN_104___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__IPA_GAIN_104___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__DAC_GAIN_104___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__DAC_GAIN_104___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__TX_PWR_LV_LAA_104___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__TX_PWR_LV_LAA_104___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__TX_PWR_LV_N79_104___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__TX_PWR_LV_N79_104___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__BBF_GAIN_104___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__BBF_GAIN_104___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__UPC_GAIN_104___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__UPC_GAIN_104___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__DA_GAIN_104___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__DA_GAIN_104___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__XPA_GAIN_104___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104__XPA_GAIN_104___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_104___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105 (0x005EDDA4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__IPA_GAIN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__DAC_GAIN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__TX_PWR_LV_LAA_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__TX_PWR_LV_N79_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__BBF_GAIN_105___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__UPC_GAIN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__DA_GAIN_105___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__XPA_GAIN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__IPA_GAIN_105___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__IPA_GAIN_105___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__DAC_GAIN_105___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__DAC_GAIN_105___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__TX_PWR_LV_LAA_105___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__TX_PWR_LV_LAA_105___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__TX_PWR_LV_N79_105___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__TX_PWR_LV_N79_105___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__BBF_GAIN_105___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__BBF_GAIN_105___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__UPC_GAIN_105___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__UPC_GAIN_105___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__DA_GAIN_105___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__DA_GAIN_105___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__XPA_GAIN_105___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105__XPA_GAIN_105___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_105___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106 (0x005EDDA8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__IPA_GAIN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__DAC_GAIN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__TX_PWR_LV_LAA_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__TX_PWR_LV_N79_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__BBF_GAIN_106___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__UPC_GAIN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__DA_GAIN_106___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__XPA_GAIN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__IPA_GAIN_106___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__IPA_GAIN_106___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__DAC_GAIN_106___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__DAC_GAIN_106___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__TX_PWR_LV_LAA_106___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__TX_PWR_LV_LAA_106___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__TX_PWR_LV_N79_106___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__TX_PWR_LV_N79_106___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__BBF_GAIN_106___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__BBF_GAIN_106___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__UPC_GAIN_106___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__UPC_GAIN_106___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__DA_GAIN_106___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__DA_GAIN_106___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__XPA_GAIN_106___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106__XPA_GAIN_106___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_106___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107 (0x005EDDAC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__IPA_GAIN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__DAC_GAIN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__TX_PWR_LV_LAA_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__TX_PWR_LV_N79_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__BBF_GAIN_107___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__UPC_GAIN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__DA_GAIN_107___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__XPA_GAIN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__IPA_GAIN_107___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__IPA_GAIN_107___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__DAC_GAIN_107___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__DAC_GAIN_107___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__TX_PWR_LV_LAA_107___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__TX_PWR_LV_LAA_107___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__TX_PWR_LV_N79_107___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__TX_PWR_LV_N79_107___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__BBF_GAIN_107___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__BBF_GAIN_107___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__UPC_GAIN_107___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__UPC_GAIN_107___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__DA_GAIN_107___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__DA_GAIN_107___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__XPA_GAIN_107___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107__XPA_GAIN_107___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_107___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108 (0x005EDDB0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__IPA_GAIN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__DAC_GAIN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__TX_PWR_LV_LAA_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__TX_PWR_LV_N79_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__BBF_GAIN_108___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__UPC_GAIN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__DA_GAIN_108___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__XPA_GAIN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__IPA_GAIN_108___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__IPA_GAIN_108___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__DAC_GAIN_108___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__DAC_GAIN_108___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__TX_PWR_LV_LAA_108___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__TX_PWR_LV_LAA_108___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__TX_PWR_LV_N79_108___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__TX_PWR_LV_N79_108___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__BBF_GAIN_108___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__BBF_GAIN_108___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__UPC_GAIN_108___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__UPC_GAIN_108___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__DA_GAIN_108___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__DA_GAIN_108___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__XPA_GAIN_108___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108__XPA_GAIN_108___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_108___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109 (0x005EDDB4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__IPA_GAIN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__DAC_GAIN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__TX_PWR_LV_LAA_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__TX_PWR_LV_N79_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__BBF_GAIN_109___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__UPC_GAIN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__DA_GAIN_109___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__XPA_GAIN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__IPA_GAIN_109___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__IPA_GAIN_109___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__DAC_GAIN_109___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__DAC_GAIN_109___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__TX_PWR_LV_LAA_109___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__TX_PWR_LV_LAA_109___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__TX_PWR_LV_N79_109___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__TX_PWR_LV_N79_109___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__BBF_GAIN_109___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__BBF_GAIN_109___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__UPC_GAIN_109___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__UPC_GAIN_109___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__DA_GAIN_109___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__DA_GAIN_109___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__XPA_GAIN_109___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109__XPA_GAIN_109___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_109___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110 (0x005EDDB8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__IPA_GAIN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__DAC_GAIN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__TX_PWR_LV_LAA_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__TX_PWR_LV_N79_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__BBF_GAIN_110___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__UPC_GAIN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__DA_GAIN_110___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__XPA_GAIN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__IPA_GAIN_110___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__IPA_GAIN_110___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__DAC_GAIN_110___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__DAC_GAIN_110___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__TX_PWR_LV_LAA_110___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__TX_PWR_LV_LAA_110___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__TX_PWR_LV_N79_110___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__TX_PWR_LV_N79_110___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__BBF_GAIN_110___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__BBF_GAIN_110___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__UPC_GAIN_110___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__UPC_GAIN_110___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__DA_GAIN_110___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__DA_GAIN_110___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__XPA_GAIN_110___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110__XPA_GAIN_110___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_110___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111 (0x005EDDBC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__IPA_GAIN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__DAC_GAIN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__TX_PWR_LV_LAA_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__TX_PWR_LV_N79_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__BBF_GAIN_111___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__UPC_GAIN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__DA_GAIN_111___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__XPA_GAIN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__IPA_GAIN_111___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__IPA_GAIN_111___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__DAC_GAIN_111___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__DAC_GAIN_111___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__TX_PWR_LV_LAA_111___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__TX_PWR_LV_LAA_111___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__TX_PWR_LV_N79_111___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__TX_PWR_LV_N79_111___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__BBF_GAIN_111___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__BBF_GAIN_111___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__UPC_GAIN_111___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__UPC_GAIN_111___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__DA_GAIN_111___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__DA_GAIN_111___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__XPA_GAIN_111___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111__XPA_GAIN_111___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_111___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112 (0x005EDDC0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__IPA_GAIN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__DAC_GAIN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__TX_PWR_LV_LAA_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__TX_PWR_LV_N79_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__BBF_GAIN_112___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__UPC_GAIN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__DA_GAIN_112___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__XPA_GAIN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__IPA_GAIN_112___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__IPA_GAIN_112___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__DAC_GAIN_112___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__DAC_GAIN_112___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__TX_PWR_LV_LAA_112___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__TX_PWR_LV_LAA_112___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__TX_PWR_LV_N79_112___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__TX_PWR_LV_N79_112___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__BBF_GAIN_112___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__BBF_GAIN_112___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__UPC_GAIN_112___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__UPC_GAIN_112___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__DA_GAIN_112___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__DA_GAIN_112___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__XPA_GAIN_112___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112__XPA_GAIN_112___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_112___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113 (0x005EDDC4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__IPA_GAIN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__DAC_GAIN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__TX_PWR_LV_LAA_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__TX_PWR_LV_N79_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__BBF_GAIN_113___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__UPC_GAIN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__DA_GAIN_113___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__XPA_GAIN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__IPA_GAIN_113___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__IPA_GAIN_113___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__DAC_GAIN_113___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__DAC_GAIN_113___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__TX_PWR_LV_LAA_113___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__TX_PWR_LV_LAA_113___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__TX_PWR_LV_N79_113___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__TX_PWR_LV_N79_113___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__BBF_GAIN_113___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__BBF_GAIN_113___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__UPC_GAIN_113___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__UPC_GAIN_113___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__DA_GAIN_113___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__DA_GAIN_113___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__XPA_GAIN_113___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113__XPA_GAIN_113___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_113___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114 (0x005EDDC8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__IPA_GAIN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__DAC_GAIN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__TX_PWR_LV_LAA_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__TX_PWR_LV_N79_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__BBF_GAIN_114___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__UPC_GAIN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__DA_GAIN_114___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__XPA_GAIN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__IPA_GAIN_114___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__IPA_GAIN_114___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__DAC_GAIN_114___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__DAC_GAIN_114___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__TX_PWR_LV_LAA_114___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__TX_PWR_LV_LAA_114___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__TX_PWR_LV_N79_114___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__TX_PWR_LV_N79_114___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__BBF_GAIN_114___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__BBF_GAIN_114___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__UPC_GAIN_114___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__UPC_GAIN_114___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__DA_GAIN_114___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__DA_GAIN_114___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__XPA_GAIN_114___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114__XPA_GAIN_114___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_114___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115 (0x005EDDCC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__IPA_GAIN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__DAC_GAIN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__TX_PWR_LV_LAA_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__TX_PWR_LV_N79_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__BBF_GAIN_115___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__UPC_GAIN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__DA_GAIN_115___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__XPA_GAIN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__IPA_GAIN_115___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__IPA_GAIN_115___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__DAC_GAIN_115___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__DAC_GAIN_115___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__TX_PWR_LV_LAA_115___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__TX_PWR_LV_LAA_115___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__TX_PWR_LV_N79_115___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__TX_PWR_LV_N79_115___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__BBF_GAIN_115___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__BBF_GAIN_115___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__UPC_GAIN_115___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__UPC_GAIN_115___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__DA_GAIN_115___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__DA_GAIN_115___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__XPA_GAIN_115___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115__XPA_GAIN_115___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_115___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116 (0x005EDDD0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__IPA_GAIN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__DAC_GAIN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__TX_PWR_LV_LAA_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__TX_PWR_LV_N79_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__BBF_GAIN_116___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__UPC_GAIN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__DA_GAIN_116___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__XPA_GAIN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__IPA_GAIN_116___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__IPA_GAIN_116___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__DAC_GAIN_116___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__DAC_GAIN_116___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__TX_PWR_LV_LAA_116___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__TX_PWR_LV_LAA_116___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__TX_PWR_LV_N79_116___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__TX_PWR_LV_N79_116___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__BBF_GAIN_116___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__BBF_GAIN_116___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__UPC_GAIN_116___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__UPC_GAIN_116___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__DA_GAIN_116___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__DA_GAIN_116___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__XPA_GAIN_116___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116__XPA_GAIN_116___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_116___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117 (0x005EDDD4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__IPA_GAIN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__DAC_GAIN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__TX_PWR_LV_LAA_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__TX_PWR_LV_N79_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__BBF_GAIN_117___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__UPC_GAIN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__DA_GAIN_117___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__XPA_GAIN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__IPA_GAIN_117___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__IPA_GAIN_117___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__DAC_GAIN_117___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__DAC_GAIN_117___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__TX_PWR_LV_LAA_117___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__TX_PWR_LV_LAA_117___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__TX_PWR_LV_N79_117___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__TX_PWR_LV_N79_117___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__BBF_GAIN_117___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__BBF_GAIN_117___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__UPC_GAIN_117___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__UPC_GAIN_117___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__DA_GAIN_117___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__DA_GAIN_117___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__XPA_GAIN_117___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117__XPA_GAIN_117___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_117___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118 (0x005EDDD8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__IPA_GAIN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__DAC_GAIN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__TX_PWR_LV_LAA_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__TX_PWR_LV_N79_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__BBF_GAIN_118___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__UPC_GAIN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__DA_GAIN_118___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__XPA_GAIN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__IPA_GAIN_118___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__IPA_GAIN_118___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__DAC_GAIN_118___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__DAC_GAIN_118___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__TX_PWR_LV_LAA_118___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__TX_PWR_LV_LAA_118___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__TX_PWR_LV_N79_118___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__TX_PWR_LV_N79_118___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__BBF_GAIN_118___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__BBF_GAIN_118___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__UPC_GAIN_118___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__UPC_GAIN_118___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__DA_GAIN_118___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__DA_GAIN_118___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__XPA_GAIN_118___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118__XPA_GAIN_118___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_118___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119 (0x005EDDDC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__IPA_GAIN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__DAC_GAIN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__TX_PWR_LV_LAA_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__TX_PWR_LV_N79_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__BBF_GAIN_119___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__UPC_GAIN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__DA_GAIN_119___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__XPA_GAIN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__IPA_GAIN_119___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__IPA_GAIN_119___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__DAC_GAIN_119___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__DAC_GAIN_119___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__TX_PWR_LV_LAA_119___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__TX_PWR_LV_LAA_119___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__TX_PWR_LV_N79_119___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__TX_PWR_LV_N79_119___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__BBF_GAIN_119___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__BBF_GAIN_119___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__UPC_GAIN_119___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__UPC_GAIN_119___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__DA_GAIN_119___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__DA_GAIN_119___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__XPA_GAIN_119___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119__XPA_GAIN_119___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_119___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120 (0x005EDDE0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__IPA_GAIN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__DAC_GAIN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__TX_PWR_LV_LAA_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__TX_PWR_LV_N79_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__BBF_GAIN_120___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__UPC_GAIN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__DA_GAIN_120___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__XPA_GAIN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__IPA_GAIN_120___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__IPA_GAIN_120___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__DAC_GAIN_120___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__DAC_GAIN_120___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__TX_PWR_LV_LAA_120___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__TX_PWR_LV_LAA_120___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__TX_PWR_LV_N79_120___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__TX_PWR_LV_N79_120___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__BBF_GAIN_120___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__BBF_GAIN_120___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__UPC_GAIN_120___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__UPC_GAIN_120___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__DA_GAIN_120___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__DA_GAIN_120___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__XPA_GAIN_120___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120__XPA_GAIN_120___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_120___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121 (0x005EDDE4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__IPA_GAIN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__DAC_GAIN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__TX_PWR_LV_LAA_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__TX_PWR_LV_N79_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__BBF_GAIN_121___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__UPC_GAIN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__DA_GAIN_121___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__XPA_GAIN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__IPA_GAIN_121___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__IPA_GAIN_121___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__DAC_GAIN_121___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__DAC_GAIN_121___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__TX_PWR_LV_LAA_121___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__TX_PWR_LV_LAA_121___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__TX_PWR_LV_N79_121___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__TX_PWR_LV_N79_121___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__BBF_GAIN_121___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__BBF_GAIN_121___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__UPC_GAIN_121___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__UPC_GAIN_121___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__DA_GAIN_121___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__DA_GAIN_121___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__XPA_GAIN_121___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121__XPA_GAIN_121___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_121___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122 (0x005EDDE8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__IPA_GAIN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__DAC_GAIN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__TX_PWR_LV_LAA_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__TX_PWR_LV_N79_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__BBF_GAIN_122___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__UPC_GAIN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__DA_GAIN_122___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__XPA_GAIN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__IPA_GAIN_122___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__IPA_GAIN_122___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__DAC_GAIN_122___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__DAC_GAIN_122___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__TX_PWR_LV_LAA_122___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__TX_PWR_LV_LAA_122___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__TX_PWR_LV_N79_122___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__TX_PWR_LV_N79_122___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__BBF_GAIN_122___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__BBF_GAIN_122___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__UPC_GAIN_122___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__UPC_GAIN_122___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__DA_GAIN_122___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__DA_GAIN_122___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__XPA_GAIN_122___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122__XPA_GAIN_122___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_122___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123 (0x005EDDEC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__IPA_GAIN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__DAC_GAIN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__TX_PWR_LV_LAA_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__TX_PWR_LV_N79_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__BBF_GAIN_123___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__UPC_GAIN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__DA_GAIN_123___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__XPA_GAIN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__IPA_GAIN_123___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__IPA_GAIN_123___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__DAC_GAIN_123___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__DAC_GAIN_123___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__TX_PWR_LV_LAA_123___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__TX_PWR_LV_LAA_123___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__TX_PWR_LV_N79_123___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__TX_PWR_LV_N79_123___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__BBF_GAIN_123___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__BBF_GAIN_123___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__UPC_GAIN_123___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__UPC_GAIN_123___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__DA_GAIN_123___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__DA_GAIN_123___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__XPA_GAIN_123___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123__XPA_GAIN_123___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_123___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124 (0x005EDDF0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__IPA_GAIN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__DAC_GAIN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__TX_PWR_LV_LAA_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__TX_PWR_LV_N79_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__BBF_GAIN_124___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__UPC_GAIN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__DA_GAIN_124___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__XPA_GAIN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__IPA_GAIN_124___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__IPA_GAIN_124___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__DAC_GAIN_124___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__DAC_GAIN_124___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__TX_PWR_LV_LAA_124___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__TX_PWR_LV_LAA_124___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__TX_PWR_LV_N79_124___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__TX_PWR_LV_N79_124___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__BBF_GAIN_124___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__BBF_GAIN_124___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__UPC_GAIN_124___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__UPC_GAIN_124___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__DA_GAIN_124___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__DA_GAIN_124___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__XPA_GAIN_124___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124__XPA_GAIN_124___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_124___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125 (0x005EDDF4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__IPA_GAIN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__DAC_GAIN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__TX_PWR_LV_LAA_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__TX_PWR_LV_N79_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__BBF_GAIN_125___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__UPC_GAIN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__DA_GAIN_125___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__XPA_GAIN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__IPA_GAIN_125___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__IPA_GAIN_125___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__DAC_GAIN_125___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__DAC_GAIN_125___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__TX_PWR_LV_LAA_125___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__TX_PWR_LV_LAA_125___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__TX_PWR_LV_N79_125___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__TX_PWR_LV_N79_125___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__BBF_GAIN_125___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__BBF_GAIN_125___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__UPC_GAIN_125___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__UPC_GAIN_125___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__DA_GAIN_125___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__DA_GAIN_125___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__XPA_GAIN_125___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125__XPA_GAIN_125___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_125___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126 (0x005EDDF8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__IPA_GAIN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__DAC_GAIN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__TX_PWR_LV_LAA_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__TX_PWR_LV_N79_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__BBF_GAIN_126___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__UPC_GAIN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__DA_GAIN_126___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__XPA_GAIN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__IPA_GAIN_126___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__IPA_GAIN_126___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__DAC_GAIN_126___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__DAC_GAIN_126___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__TX_PWR_LV_LAA_126___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__TX_PWR_LV_LAA_126___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__TX_PWR_LV_N79_126___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__TX_PWR_LV_N79_126___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__BBF_GAIN_126___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__BBF_GAIN_126___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__UPC_GAIN_126___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__UPC_GAIN_126___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__DA_GAIN_126___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__DA_GAIN_126___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__XPA_GAIN_126___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126__XPA_GAIN_126___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_126___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127 (0x005EDDFC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__IPA_GAIN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__DAC_GAIN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__TX_PWR_LV_LAA_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__TX_PWR_LV_N79_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__BBF_GAIN_127___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__UPC_GAIN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__DA_GAIN_127___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__XPA_GAIN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__IPA_GAIN_127___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__IPA_GAIN_127___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__DAC_GAIN_127___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__DAC_GAIN_127___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__TX_PWR_LV_LAA_127___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__TX_PWR_LV_LAA_127___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__TX_PWR_LV_N79_127___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__TX_PWR_LV_N79_127___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__BBF_GAIN_127___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__BBF_GAIN_127___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__UPC_GAIN_127___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__UPC_GAIN_127___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__DA_GAIN_127___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__DA_GAIN_127___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__XPA_GAIN_127___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127__XPA_GAIN_127___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH0_TXGAIN_127___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_TESTREG (0x005F0000) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_TESTREG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_TESTREG___POR 0x0000AB80 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_TESTREG__TESTREG___POR 0x0000AB80 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_TESTREG__TESTREG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_TESTREG__TESTREG___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_TESTREG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_TESTREG___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_0 (0x005F0004) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_0__SYN_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_0__SYN_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_0__SYN_EN___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_0___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1 (0x005F0008) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__XPA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__IPA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__INJECT_TXLO_I_OFFSET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__LPBK_TX_CHAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__TX_RESIDUE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__RF_LPBK_PHASE_SHIFT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__CAL_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__XPA_EN_OVS___M 0x00001800 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__XPA_EN_OVS___S 11 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__IPA_EN_OVS___M 0x00000600 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__IPA_EN_OVS___S 9 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__INJECT_TXLO_I_OFFSET___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__INJECT_TXLO_I_OFFSET___S 7 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__LPBK_TX_CHAIN___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__LPBK_TX_CHAIN___S 6 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__TX_RESIDUE___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__TX_RESIDUE___S 5 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__RF_LPBK_PHASE_SHIFT___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__RF_LPBK_PHASE_SHIFT___S 4 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__CAL_MODE___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1__CAL_MODE___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_0 (0x005F000C) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_0___POR 0x00000010 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_0__TRSW_EN_RXGAIN_CAL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_0__TRSW_EN_DPD___POR 0x1 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_0__CAL_SUB_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_0__TRSW_EN_RXGAIN_CAL___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_0__TRSW_EN_RXGAIN_CAL___S 5 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_0__TRSW_EN_DPD___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_0__TRSW_EN_DPD___S 4 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_0__CAL_SUB_MODE___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_0__CAL_SUB_MODE___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_0___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_1 (0x005F0010) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_1___POR 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_1__FCS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_1__LP_RX_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_1__CLPC_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_1__FCS___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_1__FCS___S 2 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_1__LP_RX_EN___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_1__LP_RX_EN___S 1 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_1__CLPC_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_1__CLPC_EN___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_1___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2 (0x005F0014) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2___POR 0x0000C001 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__PMM_SYN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_CORE_RX_GAIN_ON___POR 0x1 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_CORE_RX_DCOC_ON___POR 0x1 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_CORE_TX_GAIN_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_CORE_TX_DCOC_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_PERIPH_RX_GAIN_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_PERIPH_RX_DCOC_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_PERIPH_TX_GAIN_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_PERIPH_TX_DCOC_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__RXIQ_CROSS_CHAIN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__PMM_SYN_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__PMM_SYN_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_CORE_RX_GAIN_ON___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_CORE_RX_GAIN_ON___S 15 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_CORE_RX_DCOC_ON___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_CORE_RX_DCOC_ON___S 14 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_CORE_TX_GAIN_ON___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_CORE_TX_GAIN_ON___S 13 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_CORE_TX_DCOC_ON___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_CORE_TX_DCOC_ON___S 12 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_PERIPH_RX_GAIN_ON___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_PERIPH_RX_GAIN_ON___S 11 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_PERIPH_RX_DCOC_ON___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_PERIPH_RX_DCOC_ON___S 10 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_PERIPH_TX_GAIN_ON___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_PERIPH_TX_GAIN_ON___S 9 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_PERIPH_TX_DCOC_ON___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__FORCE_PERIPH_TX_DCOC_ON___S 8 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__RXIQ_CROSS_CHAIN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2__RXIQ_CROSS_CHAIN___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2___M 0xC000FF01 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MODE_SEL_2___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_BBSAT_0 (0x005F0018) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_BBSAT_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_BBSAT_0___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_BBSAT_0__AGC_BBSAT_RESET_PERIOD___POR 0x14 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_BBSAT_0__AGC_BBSAT_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_BBSAT_0__AGC_BBSAT_FLAG_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_BBSAT_0__RX_SATDET_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_BBSAT_0__AGC_BBSAT_RESET_PERIOD___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_BBSAT_0__AGC_BBSAT_RESET_PERIOD___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_BBSAT_0__AGC_BBSAT_MODE___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_BBSAT_0__AGC_BBSAT_MODE___S 25 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_BBSAT_0__AGC_BBSAT_FLAG_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_BBSAT_0__AGC_BBSAT_FLAG_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_BBSAT_0__RX_SATDET_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_BBSAT_0__RX_SATDET_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_BBSAT_0___M 0xFECC0000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_BBSAT_0___S 18 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0 (0x005F001C) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0__AGC_PKDET_RESET_PERIOD___POR 0x14 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0__AGC_PKDET_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0__AGC_PKDET_FLAG_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0__AGC_EN_BY_RX_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0__AGC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0__AGC_PKDET_RESET_PERIOD___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0__AGC_PKDET_RESET_PERIOD___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0__AGC_PKDET_MODE___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0__AGC_PKDET_MODE___S 25 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0__AGC_PKDET_FLAG_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0__AGC_PKDET_FLAG_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0__AGC_EN_BY_RX_EN___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0__AGC_EN_BY_RX_EN___S 20 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0__AGC_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0__AGC_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0___M 0xFEDC0000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PKDET_0___S 18 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_PKDET (0x005F0020) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_PKDET___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_PKDET___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_PKDET__RO_AGC_PKDET_FLAG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_PKDET__RO_AGC_BBSAT_FLAG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_PKDET__RO_AGC_PKDET_FLAG___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_PKDET__RO_AGC_PKDET_FLAG___S 1 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_PKDET__RO_AGC_BBSAT_FLAG___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_PKDET__RO_AGC_BBSAT_FLAG___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_PKDET___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_PKDET___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0 (0x005F0024) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0___POR 0x06769292 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T0_START_PRD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T0_END_PRD___POR 0x6 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T1_START_PRD___POR 0x7 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T1_END_PRD___POR 0x6 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T2_START_PRD___POR 0x9 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T2_END_PRD___POR 0x2 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T3_START_PRD___POR 0x9 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T3_END_PRD___POR 0x2 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T0_START_PRD___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T0_START_PRD___S 28 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T0_END_PRD___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T0_END_PRD___S 24 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T1_START_PRD___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T1_START_PRD___S 20 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T1_END_PRD___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T1_END_PRD___S 16 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T2_START_PRD___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T2_START_PRD___S 12 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T2_END_PRD___M 0x00000F00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T2_END_PRD___S 8 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T3_START_PRD___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T3_START_PRD___S 4 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T3_END_PRD___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0__TX_T3_END_PRD___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_STAGGER_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0 (0x005F0028) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0___POR 0x00004142 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T0_START_PRD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T0_END_PRD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T1_START_PRD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T1_END_PRD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T2_START_PRD___POR 0x4 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T2_END_PRD___POR 0x1 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T3_START_PRD___POR 0x4 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T3_END_PRD___POR 0x2 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T0_START_PRD___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T0_START_PRD___S 28 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T0_END_PRD___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T0_END_PRD___S 24 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T1_START_PRD___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T1_START_PRD___S 20 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T1_END_PRD___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T1_END_PRD___S 16 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T2_START_PRD___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T2_START_PRD___S 12 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T2_END_PRD___M 0x00000F00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T2_END_PRD___S 8 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T3_START_PRD___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T3_START_PRD___S 4 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T3_END_PRD___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0__RX_T3_END_PRD___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_STAGGER_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_TIMER_0 (0x005F002C) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_TIMER_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_TIMER_0___POR 0x20000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_TIMER_0__LNA_FC_PRD___POR 0x1 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_TIMER_0__LNA_FC_PRD___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_TIMER_0__LNA_FC_PRD___S 29 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_TIMER_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_TIMER_0___S 29 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_XFEM_0 (0x005F0030) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_XFEM_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_XFEM_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_XFEM_0__ZZZ_SPARE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_XFEM_0__ZZZ_SPARE___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_XFEM_0__ZZZ_SPARE___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_XFEM_0___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_XFEM_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_SPARE_0 (0x005F0034) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_SPARE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_SPARE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_SPARE_0__D_CHAIN_SPARE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_SPARE_0__D_CHAIN_SPARE_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_SPARE_0__D_CHAIN_SPARE_0___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_SPARE_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_SPARE_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_SPARE_1 (0x005F0038) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_SPARE_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_SPARE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_SPARE_1__D_CHAIN_SPARE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_SPARE_1__D_CHAIN_SPARE_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_SPARE_1__D_CHAIN_SPARE_1___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_SPARE_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_SPARE_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_COEX_GAIN_CFG (0x005F003C) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_COEX_GAIN_CFG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_COEX_GAIN_CFG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_COEX_GAIN_CFG__COEX_LNA_GAIN_FREEZE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_COEX_GAIN_CFG__COEX_LNA_GAIN_FREEZE___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_COEX_GAIN_CFG__COEX_LNA_GAIN_FREEZE___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_COEX_GAIN_CFG___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_COEX_GAIN_CFG___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_2 (0x005F0040) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_2__COEX_XLNA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_2__COEX_LNA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_2__COEX_XLNA_GAIN___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_2__COEX_XLNA_GAIN___S 3 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_2__COEX_LNA_GAIN___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_2__COEX_LNA_GAIN___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_2___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_PHY_2___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0 (0x005F0044) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0___POR 0x09200000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__WL_ISEL_IC___POR 0x4 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__WL_ISEL_IR___POR 0x4 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__WL_ISEL_ICPT___POR 0x4 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__D_IC_25U_TEST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__D_IR_25U_TEST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__D_ICPT_25U_TEST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__WL_ISEL_IC___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__WL_ISEL_IC___S 25 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__WL_ISEL_IR___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__WL_ISEL_IR___S 22 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__WL_ISEL_ICPT___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__WL_ISEL_ICPT___S 19 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__D_IC_25U_TEST_EN___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__D_IC_25U_TEST_EN___S 2 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__D_IR_25U_TEST_EN___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__D_IR_25U_TEST_EN___S 1 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__D_ICPT_25U_TEST_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0__D_ICPT_25U_TEST_EN___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0___M 0x0FF80007 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_MC_ISEL_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_ADC_ATEST (0x005F0048) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_ADC_ATEST___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_ADC_ATEST___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_ADC_ATEST__D_ATEST_EN_ADC_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_ADC_ATEST__D_ATEST_EN_ADC_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_ADC_ATEST__D_ATEST_EN_ADC_I___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_ADC_ATEST__D_ATEST_EN_ADC_I___S 1 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_ADC_ATEST__D_ATEST_EN_ADC_Q___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_ADC_ATEST__D_ATEST_EN_ADC_Q___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_ADC_ATEST___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_ADC_ATEST___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_0 (0x005F0080) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_0___POR 0x005078A0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_REGULAR___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_LG___POR 0x50 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_VLG___POR 0x78 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_COEX___POR 0xA0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_REGULAR___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_REGULAR___S 24 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_LG___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_LG___S 16 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_VLG___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_VLG___S 8 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_COEX___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_COEX___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1 (0x005F0084) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1___POR 0xC8F00000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_DPD___POR 0xC8 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_RXDCCAL___POR 0xF0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_SEL_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__TX_GAIN_LUT_SEL_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_DPD___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_DPD___S 24 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_RXDCCAL___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_RXDCCAL___S 16 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_SEL_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_SEL_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OV___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OV___S 7 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OVD___M 0x00000060 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OVD___S 5 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__TX_GAIN_LUT_SEL_OVS___M 0x00000018 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__TX_GAIN_LUT_SEL_OVS___S 3 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OV___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OV___S 2 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OVD___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1___M 0xFFFF03FF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RXGC_BASE_ADDR_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_GC_RAM_CONTROL (0x005F0088) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_GC_RAM_CONTROL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_GC_RAM_CONTROL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_GC_RAM_CONTROL__GC_MEM_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_GC_RAM_CONTROL__RXDCCAL_GAIN_TBL_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_GC_RAM_CONTROL__GC_MEM_SEL___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_GC_RAM_CONTROL__GC_MEM_SEL___S 15 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_GC_RAM_CONTROL__RXDCCAL_GAIN_TBL_SEL___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_GC_RAM_CONTROL__RXDCCAL_GAIN_TBL_SEL___S 14 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_GC_RAM_CONTROL___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_GC_RAM_CONTROL___S 14 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0 (0x005F008C) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__SLM_XLNA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__XLNA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__LNA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__GM_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__TIA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__BQ_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__SLM_XLNA_GAIN_OV___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__SLM_XLNA_GAIN_OV___S 5 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__XLNA_GAIN_OV___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__XLNA_GAIN_OV___S 4 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__LNA_GAIN_OV___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__LNA_GAIN_OV___S 3 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__GM_GAIN_OV___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__GM_GAIN_OV___S 2 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__TIA_GAIN_OV___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__TIA_GAIN_OV___S 1 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__BQ_GAIN_OV___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0__BQ_GAIN_OV___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1 (0x005F0090) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__XLNA_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__LNA_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__GM_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__TIA_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__SLM_XLNA_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__BQ_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__XLNA_GAIN_OVD___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__XLNA_GAIN_OVD___S 15 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__LNA_GAIN_OVD___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__LNA_GAIN_OVD___S 12 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__GM_GAIN_OVD___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__GM_GAIN_OVD___S 9 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__TIA_GAIN_OVD___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__TIA_GAIN_OVD___S 7 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__SLM_XLNA_GAIN_OVD___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__SLM_XLNA_GAIN_OVD___S 5 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__BQ_GAIN_OVD___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1__BQ_GAIN_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1___M 0x0000FFBF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_GAIN_OV_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0 (0x005F0094) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_I_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_Q_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_I_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_Q_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OV___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OV___S 25 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OV___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OV___S 24 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_I_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_I_OV___S 23 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_Q_OV___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_Q_OV___S 22 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OVD___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OVD___S 20 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OVD___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OVD___S 18 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_I_OVD___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_I_OVD___S 9 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_Q_OVD___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_Q_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RX_DCOC_OV_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0 (0x005F0098) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__IPA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__DAC_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__TX_PWR_LV_LAA_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__TX_PWR_LV_N79_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__BBF_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__UPC_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__DA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__XPA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__IPA_GAIN_OV___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__IPA_GAIN_OV___S 7 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__DAC_GAIN_OV___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__DAC_GAIN_OV___S 6 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__TX_PWR_LV_LAA_OV___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__TX_PWR_LV_LAA_OV___S 5 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__TX_PWR_LV_N79_OV___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__TX_PWR_LV_N79_OV___S 4 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__BBF_GAIN_OV___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__BBF_GAIN_OV___S 3 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__UPC_GAIN_OV___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__UPC_GAIN_OV___S 2 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__DA_GAIN_OV___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__DA_GAIN_OV___S 1 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__XPA_GAIN_OV___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0__XPA_GAIN_OV___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1 (0x005F009C) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__IPA_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__DAC_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__TX_PWR_LV_LAA_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__TX_PWR_LV_N79_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__BBF_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__UPC_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__DA_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__XPA_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__IPA_GAIN_OVD___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__IPA_GAIN_OVD___S 23 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__DAC_GAIN_OVD___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__DAC_GAIN_OVD___S 20 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__TX_PWR_LV_LAA_OVD___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__TX_PWR_LV_LAA_OVD___S 19 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__TX_PWR_LV_N79_OVD___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__TX_PWR_LV_N79_OVD___S 18 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__BBF_GAIN_OVD___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__BBF_GAIN_OVD___S 12 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__UPC_GAIN_OVD___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__UPC_GAIN_OVD___S 9 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__DA_GAIN_OVD___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__DA_GAIN_OVD___S 4 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__XPA_GAIN_OVD___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1__XPA_GAIN_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_GAIN_OV_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0 (0x005F00A0) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_I_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_Q_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_I_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_Q_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_I_OV___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_I_OV___S 19 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_Q_OV___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_Q_OV___S 18 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_I_OVD___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_I_OVD___S 7 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_Q_OVD___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_Q_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0___M 0x000C3FFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_TX_DCOC_OV_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_IM2_0 (0x005F00A4) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_IM2_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_IM2_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_IM2_0__IM2_EN_MC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_IM2_0__IM2_EN_MC_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_IM2_0__IM2_EN_MC_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_IM2_0___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_IM2_0___S 30 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC (0x005F00A8) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC__RO_RX_DCOC_ADDR___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC__RO_RX_DCOC_RANGE_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC__RO_RX_DCOC_RANGE_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC__RO_RX_DCOC_RES_I___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC__RO_RX_DCOC_RES_Q___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC__RO_RX_DCOC_ADDR___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC__RO_RX_DCOC_ADDR___S 22 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC__RO_RX_DCOC_RANGE_I___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC__RO_RX_DCOC_RANGE_I___S 20 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC__RO_RX_DCOC_RANGE_Q___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC__RO_RX_DCOC_RANGE_Q___S 18 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC__RO_RX_DCOC_RES_I___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC__RO_RX_DCOC_RES_I___S 9 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC__RO_RX_DCOC_RES_Q___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC__RO_RX_DCOC_RES_Q___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_DCOC___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_DCOC (0x005F00AC) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_DCOC___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_DCOC___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_DCOC__RO_TX_DCOC_ADDR___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_DCOC__RO_TX_DCOC_RES_I___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_DCOC__RO_TX_DCOC_RES_Q___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_DCOC__RO_TX_DCOC_ADDR___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_DCOC__RO_TX_DCOC_ADDR___S 16 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_DCOC__RO_TX_DCOC_RES_I___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_DCOC__RO_TX_DCOC_RES_I___S 7 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_DCOC__RO_TX_DCOC_RES_Q___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_DCOC__RO_TX_DCOC_RES_Q___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_DCOC___M 0x007F3FFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_DCOC___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN (0x005F00B0) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_RX_GAIN_ADDR___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_XLNA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_LNA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_GM_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_TIA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_SLM_XLNA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_BQ_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_RX_GAIN_ADDR___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_RX_GAIN_ADDR___S 16 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_XLNA_GAIN___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_XLNA_GAIN___S 15 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_LNA_GAIN___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_LNA_GAIN___S 12 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_GM_GAIN___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_GM_GAIN___S 9 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_TIA_GAIN___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_TIA_GAIN___S 7 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_SLM_XLNA_GAIN___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_SLM_XLNA_GAIN___S 5 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_BQ_GAIN___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN__RO_BQ_GAIN___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN___M 0x00FFFFBF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_RX_GAIN___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0 (0x005F00B4) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_IPA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_DAC_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_TX_PWR_LV_LAA___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_TX_PWR_LV_N79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_BBF_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_UPC_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_DA_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_XPA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_IPA_GAIN___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_IPA_GAIN___S 23 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_DAC_GAIN___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_DAC_GAIN___S 20 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_TX_PWR_LV_LAA___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_TX_PWR_LV_LAA___S 19 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_TX_PWR_LV_N79___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_TX_PWR_LV_N79___S 18 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_BBF_GAIN___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_BBF_GAIN___S 12 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_UPC_GAIN___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_UPC_GAIN___S 9 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_DA_GAIN___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_DA_GAIN___S 4 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_XPA_GAIN___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0__RO_XPA_GAIN___S 0 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_1 (0x005F00B8) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_1__RO_TX_GAIN_ADDR___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_1__RO_RX_IDX___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_1__RO_TX_IDX___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_1__RO_TX_GAIN_ADDR___M 0x7F000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_1__RO_TX_GAIN_ADDR___S 24 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_1__RO_RX_IDX___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_1__RO_RX_IDX___S 16 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_1__RO_TX_IDX___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_1__RO_TX_IDX___S 8 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_1___M 0x7FFF3F00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_RO_TX_GAIN_1___S 8 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_0 (0x005F00C0) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_0__TX_DCOC_CAL_OFFSET_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_0__TX_DCOC_CAL_OFFSET_0___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_0__TX_DCOC_CAL_OFFSET_0___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_0___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_0___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_1 (0x005F00C4) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_1__TX_DCOC_CAL_OFFSET_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_1__TX_DCOC_CAL_OFFSET_1___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_1__TX_DCOC_CAL_OFFSET_1___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_1___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_1___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_2 (0x005F00C8) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_2__TX_DCOC_CAL_OFFSET_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_2__TX_DCOC_CAL_OFFSET_2___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_2__TX_DCOC_CAL_OFFSET_2___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_2___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_2___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_3 (0x005F00CC) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_3__TX_DCOC_CAL_OFFSET_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_3__TX_DCOC_CAL_OFFSET_3___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_3__TX_DCOC_CAL_OFFSET_3___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_3___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_3___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_4 (0x005F00D0) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_4__TX_DCOC_CAL_OFFSET_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_4__TX_DCOC_CAL_OFFSET_4___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_4__TX_DCOC_CAL_OFFSET_4___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_4___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_4___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_5 (0x005F00D4) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_5__TX_DCOC_CAL_OFFSET_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_5__TX_DCOC_CAL_OFFSET_5___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_5__TX_DCOC_CAL_OFFSET_5___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_5___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_5___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_6 (0x005F00D8) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_6__TX_DCOC_CAL_OFFSET_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_6__TX_DCOC_CAL_OFFSET_6___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_6__TX_DCOC_CAL_OFFSET_6___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_6___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_6___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_7 (0x005F00DC) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_7__TX_DCOC_CAL_OFFSET_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_7__TX_DCOC_CAL_OFFSET_7___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_7__TX_DCOC_CAL_OFFSET_7___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_7___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_7___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_8 (0x005F00E0) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_8__TX_DCOC_CAL_OFFSET_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_8__TX_DCOC_CAL_OFFSET_8___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_8__TX_DCOC_CAL_OFFSET_8___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_8___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_8___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_9 (0x005F00E4) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_9__TX_DCOC_CAL_OFFSET_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_9__TX_DCOC_CAL_OFFSET_9___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_9__TX_DCOC_CAL_OFFSET_9___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_9___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_9___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_10 (0x005F00E8) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_10__TX_DCOC_CAL_OFFSET_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_10__TX_DCOC_CAL_OFFSET_10___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_10__TX_DCOC_CAL_OFFSET_10___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_10___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_10___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_11 (0x005F00EC) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_11__TX_DCOC_CAL_OFFSET_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_11__TX_DCOC_CAL_OFFSET_11___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_11__TX_DCOC_CAL_OFFSET_11___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_11___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_11___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_12 (0x005F00F0) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_12__TX_DCOC_CAL_OFFSET_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_12__TX_DCOC_CAL_OFFSET_12___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_12__TX_DCOC_CAL_OFFSET_12___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_12___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_12___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_13 (0x005F00F4) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_13__TX_DCOC_CAL_OFFSET_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_13__TX_DCOC_CAL_OFFSET_13___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_13__TX_DCOC_CAL_OFFSET_13___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_13___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_13___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_14 (0x005F00F8) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_14__TX_DCOC_CAL_OFFSET_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_14__TX_DCOC_CAL_OFFSET_14___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_14__TX_DCOC_CAL_OFFSET_14___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_14___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_14___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_15 (0x005F00FC) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_15__TX_DCOC_CAL_OFFSET_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_15__TX_DCOC_CAL_OFFSET_15___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_15__TX_DCOC_CAL_OFFSET_15___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_15___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_15___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_16 (0x005F0100) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_16___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_16__TX_DCOC_CAL_OFFSET_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_16__TX_DCOC_CAL_OFFSET_16___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_16__TX_DCOC_CAL_OFFSET_16___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_16___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_16___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_17 (0x005F0104) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_17___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_17__TX_DCOC_CAL_OFFSET_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_17__TX_DCOC_CAL_OFFSET_17___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_17__TX_DCOC_CAL_OFFSET_17___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_17___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_17___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_18 (0x005F0108) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_18___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_18__TX_DCOC_CAL_OFFSET_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_18__TX_DCOC_CAL_OFFSET_18___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_18__TX_DCOC_CAL_OFFSET_18___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_18___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_18___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_19 (0x005F010C) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_19___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_19__TX_DCOC_CAL_OFFSET_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_19__TX_DCOC_CAL_OFFSET_19___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_19__TX_DCOC_CAL_OFFSET_19___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_19___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_19___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_20 (0x005F0110) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_20___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_20__TX_DCOC_CAL_OFFSET_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_20__TX_DCOC_CAL_OFFSET_20___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_20__TX_DCOC_CAL_OFFSET_20___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_20___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_20___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_21 (0x005F0114) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_21___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_21__TX_DCOC_CAL_OFFSET_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_21__TX_DCOC_CAL_OFFSET_21___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_21__TX_DCOC_CAL_OFFSET_21___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_21___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_21___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_22 (0x005F0118) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_22___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_22__TX_DCOC_CAL_OFFSET_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_22__TX_DCOC_CAL_OFFSET_22___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_22__TX_DCOC_CAL_OFFSET_22___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_22___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_22___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_23 (0x005F011C) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_23___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_23__TX_DCOC_CAL_OFFSET_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_23__TX_DCOC_CAL_OFFSET_23___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_23__TX_DCOC_CAL_OFFSET_23___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_23___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_23___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_24 (0x005F0120) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_24___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_24__TX_DCOC_CAL_OFFSET_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_24__TX_DCOC_CAL_OFFSET_24___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_24__TX_DCOC_CAL_OFFSET_24___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_24___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_24___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_25 (0x005F0124) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_25___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_25__TX_DCOC_CAL_OFFSET_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_25__TX_DCOC_CAL_OFFSET_25___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_25__TX_DCOC_CAL_OFFSET_25___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_25___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_25___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_26 (0x005F0128) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_26___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_26__TX_DCOC_CAL_OFFSET_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_26__TX_DCOC_CAL_OFFSET_26___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_26__TX_DCOC_CAL_OFFSET_26___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_26___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_26___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_27 (0x005F012C) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_27___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_27__TX_DCOC_CAL_OFFSET_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_27__TX_DCOC_CAL_OFFSET_27___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_27__TX_DCOC_CAL_OFFSET_27___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_27___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_27___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_28 (0x005F0130) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_28___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_28__TX_DCOC_CAL_OFFSET_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_28__TX_DCOC_CAL_OFFSET_28___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_28__TX_DCOC_CAL_OFFSET_28___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_28___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_28___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_29 (0x005F0134) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_29___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_29__TX_DCOC_CAL_OFFSET_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_29__TX_DCOC_CAL_OFFSET_29___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_29__TX_DCOC_CAL_OFFSET_29___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_29___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_29___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_30 (0x005F0138) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_30___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_30__TX_DCOC_CAL_OFFSET_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_30__TX_DCOC_CAL_OFFSET_30___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_30__TX_DCOC_CAL_OFFSET_30___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_30___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_30___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_31 (0x005F013C) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_31___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_31__TX_DCOC_CAL_OFFSET_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_31__TX_DCOC_CAL_OFFSET_31___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_31__TX_DCOC_CAL_OFFSET_31___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_31___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_31___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_32 (0x005F0140) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_32___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_32___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_32__TX_DCOC_CAL_OFFSET_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_32__TX_DCOC_CAL_OFFSET_32___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_32__TX_DCOC_CAL_OFFSET_32___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_32___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_32___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_33 (0x005F0144) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_33___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_33___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_33__TX_DCOC_CAL_OFFSET_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_33__TX_DCOC_CAL_OFFSET_33___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_33__TX_DCOC_CAL_OFFSET_33___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_33___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_33___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_34 (0x005F0148) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_34___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_34___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_34__TX_DCOC_CAL_OFFSET_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_34__TX_DCOC_CAL_OFFSET_34___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_34__TX_DCOC_CAL_OFFSET_34___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_34___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_34___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_35 (0x005F014C) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_35___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_35___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_35__TX_DCOC_CAL_OFFSET_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_35__TX_DCOC_CAL_OFFSET_35___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_35__TX_DCOC_CAL_OFFSET_35___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_35___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_35___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_36 (0x005F0150) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_36___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_36___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_36__TX_DCOC_CAL_OFFSET_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_36__TX_DCOC_CAL_OFFSET_36___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_36__TX_DCOC_CAL_OFFSET_36___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_36___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_36___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_37 (0x005F0154) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_37___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_37___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_37__TX_DCOC_CAL_OFFSET_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_37__TX_DCOC_CAL_OFFSET_37___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_37__TX_DCOC_CAL_OFFSET_37___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_37___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_37___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_38 (0x005F0158) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_38___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_38___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_38__TX_DCOC_CAL_OFFSET_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_38__TX_DCOC_CAL_OFFSET_38___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_38__TX_DCOC_CAL_OFFSET_38___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_38___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_38___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_39 (0x005F015C) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_39___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_39___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_39__TX_DCOC_CAL_OFFSET_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_39__TX_DCOC_CAL_OFFSET_39___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_39__TX_DCOC_CAL_OFFSET_39___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_39___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_39___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_40 (0x005F0160) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_40___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_40___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_40__TX_DCOC_CAL_OFFSET_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_40__TX_DCOC_CAL_OFFSET_40___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_40__TX_DCOC_CAL_OFFSET_40___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_40___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_40___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_41 (0x005F0164) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_41___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_41___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_41__TX_DCOC_CAL_OFFSET_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_41__TX_DCOC_CAL_OFFSET_41___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_41__TX_DCOC_CAL_OFFSET_41___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_41___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_41___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_42 (0x005F0168) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_42___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_42___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_42__TX_DCOC_CAL_OFFSET_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_42__TX_DCOC_CAL_OFFSET_42___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_42__TX_DCOC_CAL_OFFSET_42___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_42___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_42___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_43 (0x005F016C) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_43___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_43___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_43__TX_DCOC_CAL_OFFSET_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_43__TX_DCOC_CAL_OFFSET_43___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_43__TX_DCOC_CAL_OFFSET_43___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_43___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_43___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_44 (0x005F0170) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_44___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_44___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_44__TX_DCOC_CAL_OFFSET_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_44__TX_DCOC_CAL_OFFSET_44___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_44__TX_DCOC_CAL_OFFSET_44___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_44___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_44___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_45 (0x005F0174) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_45___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_45___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_45__TX_DCOC_CAL_OFFSET_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_45__TX_DCOC_CAL_OFFSET_45___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_45__TX_DCOC_CAL_OFFSET_45___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_45___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_45___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_46 (0x005F0178) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_46___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_46___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_46__TX_DCOC_CAL_OFFSET_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_46__TX_DCOC_CAL_OFFSET_46___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_46__TX_DCOC_CAL_OFFSET_46___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_46___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_46___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_47 (0x005F017C) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_47___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_47___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_47__TX_DCOC_CAL_OFFSET_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_47__TX_DCOC_CAL_OFFSET_47___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_47__TX_DCOC_CAL_OFFSET_47___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_47___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_47___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_48 (0x005F0180) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_48___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_48___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_48__TX_DCOC_CAL_OFFSET_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_48__TX_DCOC_CAL_OFFSET_48___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_48__TX_DCOC_CAL_OFFSET_48___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_48___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_48___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_49 (0x005F0184) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_49___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_49___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_49__TX_DCOC_CAL_OFFSET_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_49__TX_DCOC_CAL_OFFSET_49___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_49__TX_DCOC_CAL_OFFSET_49___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_49___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_49___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_50 (0x005F0188) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_50___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_50___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_50__TX_DCOC_CAL_OFFSET_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_50__TX_DCOC_CAL_OFFSET_50___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_50__TX_DCOC_CAL_OFFSET_50___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_50___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_50___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_51 (0x005F018C) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_51___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_51___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_51__TX_DCOC_CAL_OFFSET_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_51__TX_DCOC_CAL_OFFSET_51___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_51__TX_DCOC_CAL_OFFSET_51___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_51___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_51___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_52 (0x005F0190) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_52___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_52___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_52__TX_DCOC_CAL_OFFSET_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_52__TX_DCOC_CAL_OFFSET_52___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_52__TX_DCOC_CAL_OFFSET_52___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_52___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_52___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_53 (0x005F0194) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_53___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_53___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_53__TX_DCOC_CAL_OFFSET_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_53__TX_DCOC_CAL_OFFSET_53___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_53__TX_DCOC_CAL_OFFSET_53___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_53___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_53___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_54 (0x005F0198) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_54___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_54___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_54__TX_DCOC_CAL_OFFSET_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_54__TX_DCOC_CAL_OFFSET_54___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_54__TX_DCOC_CAL_OFFSET_54___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_54___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_54___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_55 (0x005F019C) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_55___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_55___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_55__TX_DCOC_CAL_OFFSET_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_55__TX_DCOC_CAL_OFFSET_55___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_55__TX_DCOC_CAL_OFFSET_55___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_55___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_55___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_56 (0x005F01A0) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_56___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_56___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_56__TX_DCOC_CAL_OFFSET_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_56__TX_DCOC_CAL_OFFSET_56___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_56__TX_DCOC_CAL_OFFSET_56___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_56___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_56___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_57 (0x005F01A4) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_57___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_57___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_57__TX_DCOC_CAL_OFFSET_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_57__TX_DCOC_CAL_OFFSET_57___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_57__TX_DCOC_CAL_OFFSET_57___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_57___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_57___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_58 (0x005F01A8) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_58___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_58___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_58__TX_DCOC_CAL_OFFSET_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_58__TX_DCOC_CAL_OFFSET_58___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_58__TX_DCOC_CAL_OFFSET_58___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_58___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_58___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_59 (0x005F01AC) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_59___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_59___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_59__TX_DCOC_CAL_OFFSET_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_59__TX_DCOC_CAL_OFFSET_59___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_59__TX_DCOC_CAL_OFFSET_59___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_59___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_59___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_60 (0x005F01B0) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_60___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_60___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_60__TX_DCOC_CAL_OFFSET_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_60__TX_DCOC_CAL_OFFSET_60___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_60__TX_DCOC_CAL_OFFSET_60___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_60___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_60___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_61 (0x005F01B4) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_61___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_61___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_61__TX_DCOC_CAL_OFFSET_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_61__TX_DCOC_CAL_OFFSET_61___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_61__TX_DCOC_CAL_OFFSET_61___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_61___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_61___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_62 (0x005F01B8) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_62___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_62___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_62__TX_DCOC_CAL_OFFSET_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_62__TX_DCOC_CAL_OFFSET_62___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_62__TX_DCOC_CAL_OFFSET_62___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_62___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_62___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_63 (0x005F01BC) +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_63___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_63___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_63__TX_DCOC_CAL_OFFSET_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_63__TX_DCOC_CAL_OFFSET_63___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_63__TX_DCOC_CAL_OFFSET_63___S 26 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_63___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_2G_CH1_LUT_63___S 26 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_TESTREG (0x005F1000) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_TESTREG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_TESTREG___POR 0x44FE2111 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_TESTREG__TESTREG___POR 0x44FE2111 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_TESTREG__TESTREG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_TESTREG__TESTREG___S 0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_TESTREG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_TESTREG___S 0 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL (0x005F1004) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL__FCS_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OV___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OVD___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OVD___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OV___S 27 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OVD___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OVD___S 24 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL__FCS_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL__FCS_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LUT_IDX_SEL___S 22 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_1_0 (0x005F1008) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_1_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_1_0___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_1_0__LNA_LOAD_C_0___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_1_0__LNA_LOAD_C_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_1_0__LNA_LOAD_C_0___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_1_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_1_0___S 29 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_1_1 (0x005F100C) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_1_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_1_1___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_1_1__LNA_LOAD_C_1___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_1_1__LNA_LOAD_C_1___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_1_1__LNA_LOAD_C_1___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_1_1___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_1_1___S 29 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0 (0x005F1010) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0___POR 0x60A25480 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_RMATCH_0___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_GAINA_0___POR 0x5 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_LOAD_R_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_OTA_EN_0___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_BIAS_0___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_AUX_CAP_0___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__BYPS_HG_0___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_MAINI_VREF_EN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_MAIN_EN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_AUX_EN_0___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_SH_GAIN_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_RMATCH_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_RMATCH_0___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_GAINA_0___M 0x01E00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_GAINA_0___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_LOAD_R_0___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_LOAD_R_0___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_OTA_EN_0___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_OTA_EN_0___S 17 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_BIAS_0___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_BIAS_0___S 13 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_AUX_CAP_0___M 0x00001800 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_AUX_CAP_0___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__BYPS_HG_0___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__BYPS_HG_0___S 10 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_MAINI_VREF_EN_0___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_MAINI_VREF_EN_0___S 9 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_MAIN_EN_0___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_MAIN_EN_0___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_AUX_EN_0___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_AUX_EN_0___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_SH_GAIN_0___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0__LNA_SH_GAIN_0___S 0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_0___S 0 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1 (0x005F1014) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1___POR 0x60E24480 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_RMATCH_1___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_GAINA_1___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_LOAD_R_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_OTA_EN_1___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_BIAS_1___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_AUX_CAP_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__BYPS_HG_1___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_MAINI_VREF_EN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_MAIN_EN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_AUX_EN_1___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_SH_GAIN_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_RMATCH_1___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_RMATCH_1___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_GAINA_1___M 0x01E00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_GAINA_1___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_LOAD_R_1___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_LOAD_R_1___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_OTA_EN_1___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_OTA_EN_1___S 17 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_BIAS_1___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_BIAS_1___S 13 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_AUX_CAP_1___M 0x00001800 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_AUX_CAP_1___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__BYPS_HG_1___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__BYPS_HG_1___S 10 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_MAINI_VREF_EN_1___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_MAINI_VREF_EN_1___S 9 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_MAIN_EN_1___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_MAIN_EN_1___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_AUX_EN_1___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_AUX_EN_1___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_SH_GAIN_1___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1__LNA_SH_GAIN_1___S 0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_1___S 0 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2 (0x005F1018) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2___POR 0x601E030A +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_RMATCH_2___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_GAINA_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_LOAD_R_2___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_OTA_EN_2___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_BIAS_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_AUX_CAP_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__BYPS_HG_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_MAINI_VREF_EN_2___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_MAIN_EN_2___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_AUX_EN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_SH_GAIN_2___POR 0x0A +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_RMATCH_2___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_RMATCH_2___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_GAINA_2___M 0x01E00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_GAINA_2___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_LOAD_R_2___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_LOAD_R_2___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_OTA_EN_2___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_OTA_EN_2___S 17 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_BIAS_2___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_BIAS_2___S 13 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_AUX_CAP_2___M 0x00001800 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_AUX_CAP_2___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__BYPS_HG_2___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__BYPS_HG_2___S 10 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_MAINI_VREF_EN_2___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_MAINI_VREF_EN_2___S 9 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_MAIN_EN_2___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_MAIN_EN_2___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_AUX_EN_2___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_AUX_EN_2___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_SH_GAIN_2___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2__LNA_SH_GAIN_2___S 0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_2___S 0 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3 (0x005F101C) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3___POR 0x60022304 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_RMATCH_3___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_GAINA_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_LOAD_R_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_OTA_EN_3___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_BIAS_3___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_AUX_CAP_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__BYPS_HG_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_MAINI_VREF_EN_3___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_MAIN_EN_3___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_AUX_EN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_SH_GAIN_3___POR 0x04 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_RMATCH_3___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_RMATCH_3___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_GAINA_3___M 0x01E00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_GAINA_3___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_LOAD_R_3___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_LOAD_R_3___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_OTA_EN_3___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_OTA_EN_3___S 17 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_BIAS_3___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_BIAS_3___S 13 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_AUX_CAP_3___M 0x00001800 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_AUX_CAP_3___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__BYPS_HG_3___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__BYPS_HG_3___S 10 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_MAINI_VREF_EN_3___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_MAINI_VREF_EN_3___S 9 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_MAIN_EN_3___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_MAIN_EN_3___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_AUX_EN_3___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_AUX_EN_3___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_SH_GAIN_3___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3__LNA_SH_GAIN_3___S 0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_3___S 0 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4 (0x005F1020) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4___POR 0x60022309 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_RMATCH_4___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_GAINA_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_LOAD_R_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_OTA_EN_4___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_BIAS_4___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_AUX_CAP_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__BYPS_HG_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_MAINI_VREF_EN_4___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_MAIN_EN_4___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_AUX_EN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_SH_GAIN_4___POR 0x09 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_RMATCH_4___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_RMATCH_4___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_GAINA_4___M 0x01E00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_GAINA_4___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_LOAD_R_4___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_LOAD_R_4___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_OTA_EN_4___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_OTA_EN_4___S 17 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_BIAS_4___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_BIAS_4___S 13 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_AUX_CAP_4___M 0x00001800 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_AUX_CAP_4___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__BYPS_HG_4___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__BYPS_HG_4___S 10 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_MAINI_VREF_EN_4___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_MAINI_VREF_EN_4___S 9 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_MAIN_EN_4___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_MAIN_EN_4___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_AUX_EN_4___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_AUX_EN_4___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_SH_GAIN_4___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4__LNA_SH_GAIN_4___S 0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_4___S 0 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5 (0x005F1024) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5___POR 0x60022312 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_RMATCH_5___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_GAINA_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_LOAD_R_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_OTA_EN_5___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_BIAS_5___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_AUX_CAP_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__BYPS_HG_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_MAINI_VREF_EN_5___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_MAIN_EN_5___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_AUX_EN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_SH_GAIN_5___POR 0x12 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_RMATCH_5___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_RMATCH_5___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_GAINA_5___M 0x01E00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_GAINA_5___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_LOAD_R_5___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_LOAD_R_5___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_OTA_EN_5___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_OTA_EN_5___S 17 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_BIAS_5___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_BIAS_5___S 13 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_AUX_CAP_5___M 0x00001800 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_AUX_CAP_5___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__BYPS_HG_5___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__BYPS_HG_5___S 10 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_MAINI_VREF_EN_5___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_MAINI_VREF_EN_5___S 9 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_MAIN_EN_5___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_MAIN_EN_5___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_AUX_EN_5___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_AUX_EN_5___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_SH_GAIN_5___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5__LNA_SH_GAIN_5___S 0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_5___S 0 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6 (0x005F1028) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6___POR 0x4002231C +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_RMATCH_6___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_GAINA_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_LOAD_R_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_OTA_EN_6___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_BIAS_6___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_AUX_CAP_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__BYPS_HG_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_MAINI_VREF_EN_6___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_MAIN_EN_6___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_AUX_EN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_SH_GAIN_6___POR 0x1C +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_RMATCH_6___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_RMATCH_6___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_GAINA_6___M 0x01E00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_GAINA_6___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_LOAD_R_6___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_LOAD_R_6___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_OTA_EN_6___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_OTA_EN_6___S 17 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_BIAS_6___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_BIAS_6___S 13 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_AUX_CAP_6___M 0x00001800 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_AUX_CAP_6___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__BYPS_HG_6___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__BYPS_HG_6___S 10 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_MAINI_VREF_EN_6___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_MAINI_VREF_EN_6___S 9 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_MAIN_EN_6___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_MAIN_EN_6___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_AUX_EN_6___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_AUX_EN_6___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_SH_GAIN_6___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6__LNA_SH_GAIN_6___S 0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_6___S 0 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7 (0x005F102C) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7___POR 0x00026339 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_RMATCH_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_GAINA_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_LOAD_R_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_OTA_EN_7___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_BIAS_7___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_AUX_CAP_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__BYPS_HG_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_MAINI_VREF_EN_7___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_MAIN_EN_7___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_AUX_EN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_SH_GAIN_7___POR 0x39 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_RMATCH_7___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_RMATCH_7___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_GAINA_7___M 0x01E00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_GAINA_7___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_LOAD_R_7___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_LOAD_R_7___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_OTA_EN_7___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_OTA_EN_7___S 17 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_BIAS_7___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_BIAS_7___S 13 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_AUX_CAP_7___M 0x00001800 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_AUX_CAP_7___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__BYPS_HG_7___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__BYPS_HG_7___S 10 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_MAINI_VREF_EN_7___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_MAINI_VREF_EN_7___S 9 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_MAIN_EN_7___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_MAIN_EN_7___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_AUX_EN_7___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_AUX_EN_7___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_SH_GAIN_7___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7__LNA_SH_GAIN_7___S 0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_LNA_0_7___S 0 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0 (0x005F1030) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0___POR 0x0A320000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0__WL_GM_BYP_EN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0__WL_GM_SH_GAIN_0___POR 0x05 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0__WL_GMP_GAIN_0___POR 0x06 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0__WL_GM_IBIAS_CTRL_0___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0__WL_GM_BYP_EN_0___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0__WL_GM_BYP_EN_0___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0__WL_GM_SH_GAIN_0___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0__WL_GM_SH_GAIN_0___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0__WL_GMP_GAIN_0___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0__WL_GMP_GAIN_0___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0__WL_GM_IBIAS_CTRL_0___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0__WL_GM_IBIAS_CTRL_0___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_0___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_1 (0x005F1034) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_1___POR 0x0A320000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_1__WL_GM_BYP_EN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_1__WL_GM_SH_GAIN_1___POR 0x05 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_1__WL_GMP_GAIN_1___POR 0x06 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_1__WL_GM_IBIAS_CTRL_1___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_1__WL_GM_BYP_EN_1___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_1__WL_GM_BYP_EN_1___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_1__WL_GM_SH_GAIN_1___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_1__WL_GM_SH_GAIN_1___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_1__WL_GMP_GAIN_1___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_1__WL_GMP_GAIN_1___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_1__WL_GM_IBIAS_CTRL_1___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_1__WL_GM_IBIAS_CTRL_1___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_1___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_1___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_2 (0x005F1038) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_2___POR 0x14520000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_2__WL_GM_BYP_EN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_2__WL_GM_SH_GAIN_2___POR 0x0A +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_2__WL_GMP_GAIN_2___POR 0x0A +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_2__WL_GM_IBIAS_CTRL_2___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_2__WL_GM_BYP_EN_2___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_2__WL_GM_BYP_EN_2___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_2__WL_GM_SH_GAIN_2___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_2__WL_GM_SH_GAIN_2___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_2__WL_GMP_GAIN_2___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_2__WL_GMP_GAIN_2___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_2__WL_GM_IBIAS_CTRL_2___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_2__WL_GM_IBIAS_CTRL_2___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_2___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_2___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_3 (0x005F103C) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_3___POR 0x1E7A0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_3__WL_GM_BYP_EN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_3__WL_GM_SH_GAIN_3___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_3__WL_GMP_GAIN_3___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_3__WL_GM_IBIAS_CTRL_3___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_3__WL_GM_BYP_EN_3___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_3__WL_GM_BYP_EN_3___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_3__WL_GM_SH_GAIN_3___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_3__WL_GM_SH_GAIN_3___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_3__WL_GMP_GAIN_3___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_3__WL_GMP_GAIN_3___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_3__WL_GM_IBIAS_CTRL_3___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_3__WL_GM_IBIAS_CTRL_3___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_3___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_3___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_4 (0x005F1040) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_4___POR 0x28930000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_4__WL_GM_BYP_EN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_4__WL_GM_SH_GAIN_4___POR 0x14 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_4__WL_GMP_GAIN_4___POR 0x12 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_4__WL_GM_IBIAS_CTRL_4___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_4__WL_GM_BYP_EN_4___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_4__WL_GM_BYP_EN_4___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_4__WL_GM_SH_GAIN_4___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_4__WL_GM_SH_GAIN_4___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_4__WL_GMP_GAIN_4___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_4__WL_GMP_GAIN_4___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_4__WL_GM_IBIAS_CTRL_4___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_4__WL_GM_IBIAS_CTRL_4___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_4___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_4___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_5 (0x005F1044) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_5___POR 0x3CC20000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_5__WL_GM_BYP_EN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_5__WL_GM_SH_GAIN_5___POR 0x1E +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_5__WL_GMP_GAIN_5___POR 0x18 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_5__WL_GM_IBIAS_CTRL_5___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_5__WL_GM_BYP_EN_5___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_5__WL_GM_BYP_EN_5___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_5__WL_GM_SH_GAIN_5___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_5__WL_GM_SH_GAIN_5___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_5__WL_GMP_GAIN_5___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_5__WL_GMP_GAIN_5___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_5__WL_GM_IBIAS_CTRL_5___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_5__WL_GM_IBIAS_CTRL_5___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_5___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_5___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_6 (0x005F1048) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_6___POR 0x65A90000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_6__WL_GM_BYP_EN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_6__WL_GM_SH_GAIN_6___POR 0x32 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_6__WL_GMP_GAIN_6___POR 0x35 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_6__WL_GM_IBIAS_CTRL_6___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_6__WL_GM_BYP_EN_6___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_6__WL_GM_BYP_EN_6___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_6__WL_GM_SH_GAIN_6___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_6__WL_GM_SH_GAIN_6___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_6__WL_GMP_GAIN_6___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_6__WL_GMP_GAIN_6___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_6__WL_GM_IBIAS_CTRL_6___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_6__WL_GM_IBIAS_CTRL_6___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_6___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_6___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_7 (0x005F104C) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_7___POR 0x65A90000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_7__WL_GM_BYP_EN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_7__WL_GM_SH_GAIN_7___POR 0x32 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_7__WL_GMP_GAIN_7___POR 0x35 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_7__WL_GM_IBIAS_CTRL_7___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_7__WL_GM_BYP_EN_7___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_7__WL_GM_BYP_EN_7___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_7__WL_GM_SH_GAIN_7___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_7__WL_GM_SH_GAIN_7___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_7__WL_GMP_GAIN_7___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_7__WL_GMP_GAIN_7___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_7__WL_GM_IBIAS_CTRL_7___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_7__WL_GM_IBIAS_CTRL_7___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_7___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_GM_0_7___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0 (0x005F1080) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_RMATCH_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_RMATCH_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_GAINA_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_GAINA_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_LOAD_R_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_LOAD_R_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_OTA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_BIAS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_BIAS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_AUX_CAP_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_AUX_CAP_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__BYPS_HG_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_MAINI_VREF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_RMATCH_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_RMATCH_OV___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_RMATCH_OVD___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_RMATCH_OVD___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_GAINA_OV___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_GAINA_OV___S 22 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_GAINA_OVD___M 0x003C0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_GAINA_OVD___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_LOAD_R_OV___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_LOAD_R_OV___S 17 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_LOAD_R_OVD___M 0x0001C000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_LOAD_R_OVD___S 14 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_OTA_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_OTA_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_BIAS_OV___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_BIAS_OV___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_BIAS_OVD___M 0x00000780 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_BIAS_OVD___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_AUX_CAP_OV___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_AUX_CAP_OV___S 6 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_AUX_CAP_OVD___M 0x00000030 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_AUX_CAP_OVD___S 4 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__BYPS_HG_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__BYPS_HG_OVS___S 2 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_MAINI_VREF_EN_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0__LNA_MAINI_VREF_EN_OVS___S 0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0___M 0xF07FFFFF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0___S 0 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT (0x005F1084) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_MAIN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_AUX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_SH_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_SH_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_MAIN_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_MAIN_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_AUX_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_AUX_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_SH_GAIN_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_SH_GAIN_OV___S 27 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_SH_GAIN_OVD___M 0x07E00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT__LNA_SH_GAIN_OVD___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV0_EXT___S 21 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1 (0x005F1088) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GM_BYP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GM_SH_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GM_SH_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GMP_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GMP_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GM_IBIAS_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GM_IBIAS_CTRL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GM_BYP_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GM_BYP_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GM_SH_GAIN_OV___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GM_SH_GAIN_OV___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GM_SH_GAIN_OVD___M 0x1F800000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GM_SH_GAIN_OVD___S 23 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GMP_GAIN_OV___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GMP_GAIN_OV___S 22 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GMP_GAIN_OVD___M 0x003F0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GMP_GAIN_OVD___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GM_IBIAS_CTRL_OV___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GM_IBIAS_CTRL_OV___S 15 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GM_IBIAS_CTRL_OVD___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1__WL_GM_IBIAS_CTRL_OVD___S 12 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV1___S 12 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV2 (0x005F108C) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV2__LNA_LOAD_C_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV2__LNA_LOAD_C_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV2__LNA_LOAD_C_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV2__LNA_LOAD_C_OV___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV2__LNA_LOAD_C_OVD___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV2__LNA_LOAD_C_OVD___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV2___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_LUT_OV2___S 28 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0 (0x005F1090) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__LNA_FASTCH_BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__CALRTX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__DPD_IPA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_GM_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_MIX_EN_I_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_MIX_EN_Q_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_RXLO_INBUF25DC1ST_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_RXLO_INBUF25DC2ND_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_RXLO_OBUF25DC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__LNA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_LPMIX_EN_I_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_LPMIX_EN_Q_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__LNA_FASTCH_BIAS_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__LNA_FASTCH_BIAS_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__CALRTX_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__CALRTX_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__DPD_IPA_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__DPD_IPA_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_GM_EN_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_GM_EN_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_MIX_EN_I_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_MIX_EN_I_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_MIX_EN_Q_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_MIX_EN_Q_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_RXLO_INBUF25DC1ST_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_RXLO_INBUF25DC1ST_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_RXLO_INBUF25DC2ND_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_RXLO_INBUF25DC2ND_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_RXLO_OBUF25DC_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_RXLO_OBUF25DC_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__LNA_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__LNA_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_LPMIX_EN_I_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_LPMIX_EN_I_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_LPMIX_EN_Q_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0__WL_LPMIX_EN_Q_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0___M 0xFFFFFF00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV0___S 8 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1 (0x005F1094) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__AGC_PKDET_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__WL_AGC_PKDET_COMP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__AGC_PKDET_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__AGC_PKDET_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__WL_AGC_PKDET_COMP_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__WL_AGC_PKDET_COMP_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OV___S 27 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OVD___M 0x07F00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OVD___S 20 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1___M 0xFFF00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_OV1___S 20 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_RXFE_LUT_IDX_SEL (0x005F1098) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_RXFE_LUT_IDX_SEL___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_RXFE_LUT_IDX_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_RXFE_LUT_IDX_SEL__RO_FCS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN___S 26 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_RXFE_LUT_IDX_SEL__RO_FCS___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_RXFE_LUT_IDX_SEL__RO_FCS___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_RXFE_LUT_IDX_SEL___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_RXFE_LUT_IDX_SEL___S 25 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0 (0x005F109C) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_RMATCH___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_GAINA___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_LOAD_R___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_OTA_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_BIAS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_AUX_CAP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_BYPS_HG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_MAINI_VREF_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_MAIN_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_AUX_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_SH_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_RMATCH___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_RMATCH___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_GAINA___M 0x01E00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_GAINA___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_LOAD_R___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_LOAD_R___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_OTA_EN___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_OTA_EN___S 17 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_BIAS___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_BIAS___S 13 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_AUX_CAP___M 0x00001800 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_AUX_CAP___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_BYPS_HG___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_BYPS_HG___S 10 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_MAINI_VREF_EN___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_MAINI_VREF_EN___S 9 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_MAIN_EN___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_MAIN_EN___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_AUX_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_AUX_EN___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_SH_GAIN___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0__RO_LNA_SH_GAIN___S 0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0___M 0xE1FFFFBF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT0___S 0 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1 (0x005F10A0) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_WL_GM_BYP_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_WL_GM_SH_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_WL_GMP_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_WL_GM_IBIAS_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_WL_GM_BYP_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_WL_GM_BYP_EN___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_WL_GM_SH_GAIN___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_WL_GM_SH_GAIN___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_WL_GMP_GAIN___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_WL_GMP_GAIN___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_WL_GM_IBIAS_CTRL___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1__RO_WL_GM_IBIAS_CTRL___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT1___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT2 (0x005F10A4) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT2__RO_LNA_LOAD_C___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT2__RO_LNA_LOAD_C___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT2__RO_LNA_LOAD_C___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT2___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_WL_RXFE_LUT2___S 29 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0 (0x005F10A8) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0___POR 0xA201E000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__IWL_AGC_PKDET_GAIN___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__D_WL_AGC_PKDET_BW___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__D_WL_AGC_PKDET_DCOC_RANGE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__D_WL_AGC_PKDET_THRES___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__AGC_PKDET_DCOC_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__AGC_PKDET_DCOC_SETT___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__IWL_AGC_PKDET_DCOC_RANGE___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__IWL_AGC_PKDET_GAIN___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__IWL_AGC_PKDET_GAIN___S 30 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__D_WL_AGC_PKDET_BW___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__D_WL_AGC_PKDET_BW___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__D_WL_AGC_PKDET_DCOC_RANGE___M 0x06000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__D_WL_AGC_PKDET_DCOC_RANGE___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__D_WL_AGC_PKDET_THRES___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__D_WL_AGC_PKDET_THRES___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__AGC_PKDET_DCOC_EN___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__AGC_PKDET_DCOC_EN___S 17 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__AGC_PKDET_DCOC_SETT___M 0x0001C000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__AGC_PKDET_DCOC_SETT___S 14 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__IWL_AGC_PKDET_DCOC_RANGE___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0__IWL_AGC_PKDET_DCOC_RANGE___S 12 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0___M 0xE7FFF000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_AGC_CAL_0___S 12 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_AGC_CAL (0x005F10AC) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_AGC_CAL___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_AGC_CAL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_VALID___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_SAT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES_EFFECT___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_VALID___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_VALID___S 15 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_SAT___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_SAT___S 14 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES_EFFECT___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES_EFFECT___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES___S 0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_AGC_CAL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_RO_AGC_CAL___S 0 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0 (0x005F10B0) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0___POR 0x7011C800 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__WL_LNA_IC_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__WL_LNA_IRTT_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__WL_LNA_OTA_BIAS_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__WL_LNA_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__WL_LNA_BIAS_OTA_SHORTR___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__IWL_SEL_2GNOTCH_TUNE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IC_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IPT_CTRL___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IOFFSET_CTRL___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__WL_LNA_IC_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__WL_LNA_IC_EN___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__WL_LNA_IRTT_EN___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__WL_LNA_IRTT_EN___S 30 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__WL_LNA_OTA_BIAS_CTRL___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__WL_LNA_OTA_BIAS_CTRL___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__WL_LNA_ATB_SEL___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__WL_LNA_ATB_SEL___S 27 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__WL_LNA_BIAS_OTA_SHORTR___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__WL_LNA_BIAS_OTA_SHORTR___S 22 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__IWL_SEL_2GNOTCH_TUNE___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__IWL_SEL_2GNOTCH_TUNE___S 20 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IC_CTRL___M 0x000E0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IC_CTRL___S 17 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IPT_CTRL___M 0x0001C000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IPT_CTRL___S 14 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IOFFSET_CTRL___M 0x00003800 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0__IWL_WLRXFE2_RTT_IOFFSET_CTRL___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0___M 0xF87FF800 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_CONTROL0___S 11 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1 (0x005F10B4) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1___POR 0x52000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_GM_IC_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_GM_IRTT_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_GM_CM_IBIAS_CTRL___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_GM_VCM___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_GM_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_AGC_PKDET_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_GM_IC_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_GM_IC_EN___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_GM_IRTT_EN___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_GM_IRTT_EN___S 30 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_GM_CM_IBIAS_CTRL___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_GM_CM_IBIAS_CTRL___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_GM_VCM___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_GM_VCM___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_GM_ATB_SEL___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_GM_ATB_SEL___S 22 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_AGC_PKDET_ATB_SEL___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1__D_WL_AGC_PKDET_ATB_SEL___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL1___S 21 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2 (0x005F10B8) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2___POR 0xFF000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_LSB_I___POR 0xF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_LSB_Q___POR 0xF +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_MSB_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_MSB_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_WL_RXLO_ATB_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__WL_CONC_TX_GRANT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_AGC_PKDET_OUT_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_RFPKDET_VREFRNG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_LSB_I___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_LSB_I___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_LSB_Q___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_LSB_Q___S 24 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_MSB_I___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_MSB_I___S 20 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_MSB_Q___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_WL_RXLO_DUTYCODE_MSB_Q___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_WL_RXLO_ATB_SEL___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_WL_RXLO_ATB_SEL___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__WL_CONC_TX_GRANT___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__WL_CONC_TX_GRANT___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_AGC_PKDET_OUT_ATB_SEL___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_AGC_PKDET_OUT_ATB_SEL___S 5 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_RFPKDET_VREFRNG___M 0x00000018 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2__D_RFPKDET_VREFRNG___S 3 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2___M 0xFFFFFFB8 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_W_RXFE_CONTROL2___S 3 + +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_SPARE (0x005F10BC) +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_SPARE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_SPARE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_SPARE__D_BT_RXFE_SPARE___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_SPARE__D_WL_RXFE_SPARE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_SPARE__D_BT_RXFE_SPARE___M 0x0003FF00 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_SPARE__D_BT_RXFE_SPARE___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_SPARE__D_WL_RXFE_SPARE___M 0x000000FE +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_SPARE__D_WL_RXFE_SPARE___S 1 +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_SPARE___M 0x0003FFFE +#define PHYA_IRON2G_RFA_WL_RXFE_2G_CH1_WL_RXFE_SPARE___S 1 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_TESTREG (0x005F1300) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_TESTREG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_TESTREG___POR 0x33FE2111 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_TESTREG__TESTREG___POR 0x33FE2111 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_TESTREG__TESTREG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_TESTREG__TESTREG___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_TESTREG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_TESTREG___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL (0x005F1304) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__FCS_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OV___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__FCS_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__FCS_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___M 0x00078000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL___M 0xFFFF8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LUT_IDX_SEL___S 15 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_0 (0x005F1308) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_0___POR 0x14500000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE3FLO_0___POR 0x05 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE1FLO_0___POR 0x05 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_0__DA_CTUNE_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE3FLO_0___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE3FLO_0___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE1FLO_0___M 0x03F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE1FLO_0___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_0__DA_CTUNE_0___M 0x0001F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_0__DA_CTUNE_0___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_0___M 0xFFF1F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_0___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_1 (0x005F130C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_1___POR 0x14500000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE3FLO_1___POR 0x05 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE1FLO_1___POR 0x05 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_1__DA_CTUNE_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE3FLO_1___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE3FLO_1___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE1FLO_1___M 0x03F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE1FLO_1___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_1__DA_CTUNE_1___M 0x0001F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_1__DA_CTUNE_1___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_1___M 0xFFF1F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CTUNE_LUT_1___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_0 (0x005F1310) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_0__DA_CELL_EN_0___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_0__DA_CELL_AUX_EN_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_0__DA_CASOFF_BIAS_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_0__DA_HS_CTRL_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_0__DA_CELL_EN_0___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_0__DA_CELL_EN_0___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_0__DA_CELL_AUX_EN_0___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_0__DA_CELL_AUX_EN_0___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_0__DA_CASOFF_BIAS_0___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_0__DA_CASOFF_BIAS_0___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_0__DA_HS_CTRL_0___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_0__DA_HS_CTRL_0___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_0___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_0___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_1 (0x005F1314) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_1__DA_CELL_EN_1___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_1__DA_CELL_AUX_EN_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_1__DA_CASOFF_BIAS_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_1__DA_HS_CTRL_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_1__DA_CELL_EN_1___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_1__DA_CELL_EN_1___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_1__DA_CELL_AUX_EN_1___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_1__DA_CELL_AUX_EN_1___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_1__DA_CASOFF_BIAS_1___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_1__DA_CASOFF_BIAS_1___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_1__DA_HS_CTRL_1___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_1__DA_HS_CTRL_1___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_1___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_1___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_2 (0x005F1318) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_2__DA_CELL_EN_2___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_2__DA_CELL_AUX_EN_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_2__DA_CASOFF_BIAS_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_2__DA_HS_CTRL_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_2__DA_CELL_EN_2___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_2__DA_CELL_EN_2___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_2__DA_CELL_AUX_EN_2___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_2__DA_CELL_AUX_EN_2___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_2__DA_CASOFF_BIAS_2___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_2__DA_CASOFF_BIAS_2___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_2__DA_HS_CTRL_2___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_2__DA_HS_CTRL_2___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_2___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_2___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_3 (0x005F131C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_3__DA_CELL_EN_3___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_3__DA_CELL_AUX_EN_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_3__DA_CASOFF_BIAS_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_3__DA_HS_CTRL_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_3__DA_CELL_EN_3___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_3__DA_CELL_EN_3___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_3__DA_CELL_AUX_EN_3___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_3__DA_CELL_AUX_EN_3___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_3__DA_CASOFF_BIAS_3___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_3__DA_CASOFF_BIAS_3___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_3__DA_HS_CTRL_3___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_3__DA_HS_CTRL_3___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_3___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_3___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_4 (0x005F1320) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_4__DA_CELL_EN_4___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_4__DA_CELL_AUX_EN_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_4__DA_CASOFF_BIAS_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_4__DA_HS_CTRL_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_4__DA_CELL_EN_4___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_4__DA_CELL_EN_4___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_4__DA_CELL_AUX_EN_4___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_4__DA_CELL_AUX_EN_4___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_4__DA_CASOFF_BIAS_4___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_4__DA_CASOFF_BIAS_4___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_4__DA_HS_CTRL_4___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_4__DA_HS_CTRL_4___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_4___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_4___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_5 (0x005F1324) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_5__DA_CELL_EN_5___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_5__DA_CELL_AUX_EN_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_5__DA_CASOFF_BIAS_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_5__DA_HS_CTRL_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_5__DA_CELL_EN_5___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_5__DA_CELL_EN_5___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_5__DA_CELL_AUX_EN_5___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_5__DA_CELL_AUX_EN_5___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_5__DA_CASOFF_BIAS_5___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_5__DA_CASOFF_BIAS_5___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_5__DA_HS_CTRL_5___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_5__DA_HS_CTRL_5___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_5___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_5___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_6 (0x005F1328) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_6___POR 0x04811000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_6__DA_CELL_EN_6___POR 0x009 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_6__DA_CELL_AUX_EN_6___POR 0x02 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_6__DA_CASOFF_BIAS_6___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_6__DA_HS_CTRL_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_6__DA_CELL_EN_6___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_6__DA_CELL_EN_6___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_6__DA_CELL_AUX_EN_6___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_6__DA_CELL_AUX_EN_6___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_6__DA_CASOFF_BIAS_6___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_6__DA_CASOFF_BIAS_6___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_6__DA_HS_CTRL_6___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_6__DA_HS_CTRL_6___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_6___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_6___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_7 (0x005F132C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_7___POR 0x05811000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_7__DA_CELL_EN_7___POR 0x00B +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_7__DA_CELL_AUX_EN_7___POR 0x02 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_7__DA_CASOFF_BIAS_7___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_7__DA_HS_CTRL_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_7__DA_CELL_EN_7___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_7__DA_CELL_EN_7___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_7__DA_CELL_AUX_EN_7___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_7__DA_CELL_AUX_EN_7___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_7__DA_CASOFF_BIAS_7___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_7__DA_CASOFF_BIAS_7___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_7__DA_HS_CTRL_7___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_7__DA_HS_CTRL_7___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_7___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_7___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_8 (0x005F1330) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_8___POR 0x06011000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_8__DA_CELL_EN_8___POR 0x00C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_8__DA_CELL_AUX_EN_8___POR 0x02 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_8__DA_CASOFF_BIAS_8___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_8__DA_HS_CTRL_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_8__DA_CELL_EN_8___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_8__DA_CELL_EN_8___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_8__DA_CELL_AUX_EN_8___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_8__DA_CELL_AUX_EN_8___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_8__DA_CASOFF_BIAS_8___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_8__DA_CASOFF_BIAS_8___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_8__DA_HS_CTRL_8___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_8__DA_HS_CTRL_8___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_8___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_8___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_9 (0x005F1334) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_9___POR 0x09011000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_9__DA_CELL_EN_9___POR 0x012 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_9__DA_CELL_AUX_EN_9___POR 0x02 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_9__DA_CASOFF_BIAS_9___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_9__DA_HS_CTRL_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_9__DA_CELL_EN_9___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_9__DA_CELL_EN_9___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_9__DA_CELL_AUX_EN_9___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_9__DA_CELL_AUX_EN_9___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_9__DA_CASOFF_BIAS_9___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_9__DA_CASOFF_BIAS_9___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_9__DA_HS_CTRL_9___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_9__DA_HS_CTRL_9___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_9___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_9___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_10 (0x005F1338) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_10___POR 0x0A011000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_10__DA_CELL_EN_10___POR 0x014 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_10__DA_CELL_AUX_EN_10___POR 0x02 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_10__DA_CASOFF_BIAS_10___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_10__DA_HS_CTRL_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_10__DA_CELL_EN_10___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_10__DA_CELL_EN_10___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_10__DA_CELL_AUX_EN_10___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_10__DA_CELL_AUX_EN_10___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_10__DA_CASOFF_BIAS_10___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_10__DA_CASOFF_BIAS_10___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_10__DA_HS_CTRL_10___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_10__DA_HS_CTRL_10___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_10___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_10___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_11 (0x005F133C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_11___POR 0x0B019000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_11__DA_CELL_EN_11___POR 0x016 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_11__DA_CELL_AUX_EN_11___POR 0x03 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_11__DA_CASOFF_BIAS_11___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_11__DA_HS_CTRL_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_11__DA_CELL_EN_11___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_11__DA_CELL_EN_11___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_11__DA_CELL_AUX_EN_11___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_11__DA_CELL_AUX_EN_11___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_11__DA_CASOFF_BIAS_11___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_11__DA_CASOFF_BIAS_11___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_11__DA_HS_CTRL_11___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_11__DA_HS_CTRL_11___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_11___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_11___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_12 (0x005F1340) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_12___POR 0x0C019000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_12__DA_CELL_EN_12___POR 0x018 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_12__DA_CELL_AUX_EN_12___POR 0x03 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_12__DA_CASOFF_BIAS_12___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_12__DA_HS_CTRL_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_12__DA_CELL_EN_12___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_12__DA_CELL_EN_12___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_12__DA_CELL_AUX_EN_12___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_12__DA_CELL_AUX_EN_12___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_12__DA_CASOFF_BIAS_12___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_12__DA_CASOFF_BIAS_12___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_12__DA_HS_CTRL_12___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_12__DA_HS_CTRL_12___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_12___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_12___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_13 (0x005F1344) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_13___POR 0x0D019000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_13__DA_CELL_EN_13___POR 0x01A +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_13__DA_CELL_AUX_EN_13___POR 0x03 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_13__DA_CASOFF_BIAS_13___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_13__DA_HS_CTRL_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_13__DA_CELL_EN_13___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_13__DA_CELL_EN_13___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_13__DA_CELL_AUX_EN_13___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_13__DA_CELL_AUX_EN_13___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_13__DA_CASOFF_BIAS_13___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_13__DA_CASOFF_BIAS_13___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_13__DA_HS_CTRL_13___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_13__DA_HS_CTRL_13___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_13___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_13___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_14 (0x005F1348) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_14___POR 0x13019000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_14__DA_CELL_EN_14___POR 0x026 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_14__DA_CELL_AUX_EN_14___POR 0x03 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_14__DA_CASOFF_BIAS_14___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_14__DA_HS_CTRL_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_14__DA_CELL_EN_14___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_14__DA_CELL_EN_14___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_14__DA_CELL_AUX_EN_14___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_14__DA_CELL_AUX_EN_14___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_14__DA_CASOFF_BIAS_14___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_14__DA_CASOFF_BIAS_14___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_14__DA_HS_CTRL_14___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_14__DA_HS_CTRL_14___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_14___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_14___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_15 (0x005F134C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_15___POR 0x14021000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_15__DA_CELL_EN_15___POR 0x028 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_15__DA_CELL_AUX_EN_15___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_15__DA_CASOFF_BIAS_15___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_15__DA_HS_CTRL_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_15__DA_CELL_EN_15___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_15__DA_CELL_EN_15___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_15__DA_CELL_AUX_EN_15___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_15__DA_CELL_AUX_EN_15___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_15__DA_CASOFF_BIAS_15___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_15__DA_CASOFF_BIAS_15___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_15__DA_HS_CTRL_15___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_15__DA_HS_CTRL_15___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_15___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_15___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_16 (0x005F1350) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_16___POR 0x15031000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_16__DA_CELL_EN_16___POR 0x02A +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_16__DA_CELL_AUX_EN_16___POR 0x06 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_16__DA_CASOFF_BIAS_16___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_16__DA_HS_CTRL_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_16__DA_CELL_EN_16___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_16__DA_CELL_EN_16___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_16__DA_CELL_AUX_EN_16___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_16__DA_CELL_AUX_EN_16___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_16__DA_CASOFF_BIAS_16___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_16__DA_CASOFF_BIAS_16___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_16__DA_HS_CTRL_16___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_16__DA_HS_CTRL_16___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_16___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_16___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_17 (0x005F1354) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_17___POR 0x19051000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_17__DA_CELL_EN_17___POR 0x032 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_17__DA_CELL_AUX_EN_17___POR 0x0A +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_17__DA_CASOFF_BIAS_17___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_17__DA_HS_CTRL_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_17__DA_CELL_EN_17___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_17__DA_CELL_EN_17___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_17__DA_CELL_AUX_EN_17___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_17__DA_CELL_AUX_EN_17___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_17__DA_CASOFF_BIAS_17___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_17__DA_CASOFF_BIAS_17___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_17__DA_HS_CTRL_17___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_17__DA_HS_CTRL_17___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_17___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_17___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_18 (0x005F1358) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_18___POR 0x1B061000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_18__DA_CELL_EN_18___POR 0x036 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_18__DA_CELL_AUX_EN_18___POR 0x0C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_18__DA_CASOFF_BIAS_18___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_18__DA_HS_CTRL_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_18__DA_CELL_EN_18___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_18__DA_CELL_EN_18___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_18__DA_CELL_AUX_EN_18___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_18__DA_CELL_AUX_EN_18___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_18__DA_CASOFF_BIAS_18___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_18__DA_CASOFF_BIAS_18___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_18__DA_HS_CTRL_18___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_18__DA_HS_CTRL_18___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_18___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_18___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_19 (0x005F135C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_19___POR 0x1D861000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_19__DA_CELL_EN_19___POR 0x03B +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_19__DA_CELL_AUX_EN_19___POR 0x0C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_19__DA_CASOFF_BIAS_19___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_19__DA_HS_CTRL_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_19__DA_CELL_EN_19___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_19__DA_CELL_EN_19___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_19__DA_CELL_AUX_EN_19___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_19__DA_CELL_AUX_EN_19___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_19__DA_CASOFF_BIAS_19___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_19__DA_CASOFF_BIAS_19___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_19__DA_HS_CTRL_19___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_19__DA_HS_CTRL_19___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_19___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_19___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_20 (0x005F1360) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_20___POR 0x25071000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_20__DA_CELL_EN_20___POR 0x04A +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_20__DA_CELL_AUX_EN_20___POR 0x0E +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_20__DA_CASOFF_BIAS_20___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_20__DA_HS_CTRL_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_20__DA_CELL_EN_20___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_20__DA_CELL_EN_20___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_20__DA_CELL_AUX_EN_20___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_20__DA_CELL_AUX_EN_20___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_20__DA_CASOFF_BIAS_20___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_20__DA_CASOFF_BIAS_20___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_20__DA_HS_CTRL_20___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_20__DA_HS_CTRL_20___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_20___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_20___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_21 (0x005F1364) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_21___POR 0x2A079000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_21__DA_CELL_EN_21___POR 0x054 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_21__DA_CELL_AUX_EN_21___POR 0x0F +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_21__DA_CASOFF_BIAS_21___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_21__DA_HS_CTRL_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_21__DA_CELL_EN_21___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_21__DA_CELL_EN_21___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_21__DA_CELL_AUX_EN_21___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_21__DA_CELL_AUX_EN_21___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_21__DA_CASOFF_BIAS_21___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_21__DA_CASOFF_BIAS_21___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_21__DA_HS_CTRL_21___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_21__DA_HS_CTRL_21___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_21___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_21___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_22 (0x005F1368) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_22___POR 0x2D091000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_22__DA_CELL_EN_22___POR 0x05A +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_22__DA_CELL_AUX_EN_22___POR 0x12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_22__DA_CASOFF_BIAS_22___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_22__DA_HS_CTRL_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_22__DA_CELL_EN_22___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_22__DA_CELL_EN_22___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_22__DA_CELL_AUX_EN_22___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_22__DA_CELL_AUX_EN_22___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_22__DA_CASOFF_BIAS_22___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_22__DA_CASOFF_BIAS_22___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_22__DA_HS_CTRL_22___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_22__DA_HS_CTRL_22___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_22___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_22___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_23 (0x005F136C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_23___POR 0x358C1000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_23__DA_CELL_EN_23___POR 0x06B +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_23__DA_CELL_AUX_EN_23___POR 0x18 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_23__DA_CASOFF_BIAS_23___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_23__DA_HS_CTRL_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_23__DA_CELL_EN_23___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_23__DA_CELL_EN_23___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_23__DA_CELL_AUX_EN_23___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_23__DA_CELL_AUX_EN_23___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_23__DA_CASOFF_BIAS_23___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_23__DA_CASOFF_BIAS_23___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_23__DA_HS_CTRL_23___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_23__DA_HS_CTRL_23___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_23___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_23___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_24 (0x005F1370) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_24___POR 0x3C0F9000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_24__DA_CELL_EN_24___POR 0x078 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_24__DA_CELL_AUX_EN_24___POR 0x1F +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_24__DA_CASOFF_BIAS_24___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_24__DA_HS_CTRL_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_24__DA_CELL_EN_24___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_24__DA_CELL_EN_24___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_24__DA_CELL_AUX_EN_24___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_24__DA_CELL_AUX_EN_24___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_24__DA_CASOFF_BIAS_24___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_24__DA_CASOFF_BIAS_24___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_24__DA_HS_CTRL_24___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_24__DA_HS_CTRL_24___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_24___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_24___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_25 (0x005F1374) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_25___POR 0x44951000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_25__DA_CELL_EN_25___POR 0x089 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_25__DA_CELL_AUX_EN_25___POR 0x2A +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_25__DA_CASOFF_BIAS_25___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_25__DA_HS_CTRL_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_25__DA_CELL_EN_25___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_25__DA_CELL_EN_25___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_25__DA_CELL_AUX_EN_25___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_25__DA_CELL_AUX_EN_25___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_25__DA_CASOFF_BIAS_25___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_25__DA_CASOFF_BIAS_25___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_25__DA_HS_CTRL_25___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_25__DA_HS_CTRL_25___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_25___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_25___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_26 (0x005F1378) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_26___POR 0x50199000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_26__DA_CELL_EN_26___POR 0x0A0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_26__DA_CELL_AUX_EN_26___POR 0x33 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_26__DA_CASOFF_BIAS_26___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_26__DA_HS_CTRL_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_26__DA_CELL_EN_26___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_26__DA_CELL_EN_26___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_26__DA_CELL_AUX_EN_26___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_26__DA_CELL_AUX_EN_26___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_26__DA_CASOFF_BIAS_26___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_26__DA_CASOFF_BIAS_26___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_26__DA_HS_CTRL_26___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_26__DA_HS_CTRL_26___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_26___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_26___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_27 (0x005F137C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_27___POR 0x569F9000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_27__DA_CELL_EN_27___POR 0x0AD +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_27__DA_CELL_AUX_EN_27___POR 0x3F +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_27__DA_CASOFF_BIAS_27___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_27__DA_HS_CTRL_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_27__DA_CELL_EN_27___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_27__DA_CELL_EN_27___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_27__DA_CELL_AUX_EN_27___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_27__DA_CELL_AUX_EN_27___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_27__DA_CASOFF_BIAS_27___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_27__DA_CASOFF_BIAS_27___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_27__DA_HS_CTRL_27___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_27__DA_HS_CTRL_27___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_27___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_27___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_28 (0x005F1380) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_28___POR 0x641F9000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_28__DA_CELL_EN_28___POR 0x0C8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_28__DA_CELL_AUX_EN_28___POR 0x3F +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_28__DA_CASOFF_BIAS_28___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_28__DA_HS_CTRL_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_28__DA_CELL_EN_28___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_28__DA_CELL_EN_28___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_28__DA_CELL_AUX_EN_28___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_28__DA_CELL_AUX_EN_28___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_28__DA_CASOFF_BIAS_28___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_28__DA_CASOFF_BIAS_28___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_28__DA_HS_CTRL_28___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_28__DA_HS_CTRL_28___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_28___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_28___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_29 (0x005F1384) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_29___POR 0x6E1F9000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_29__DA_CELL_EN_29___POR 0x0DC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_29__DA_CELL_AUX_EN_29___POR 0x3F +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_29__DA_CASOFF_BIAS_29___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_29__DA_HS_CTRL_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_29__DA_CELL_EN_29___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_29__DA_CELL_EN_29___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_29__DA_CELL_AUX_EN_29___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_29__DA_CELL_AUX_EN_29___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_29__DA_CASOFF_BIAS_29___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_29__DA_CASOFF_BIAS_29___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_29__DA_HS_CTRL_29___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_29__DA_HS_CTRL_29___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_29___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_29___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_30 (0x005F1388) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_30___POR 0x7D9F9000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_30__DA_CELL_EN_30___POR 0x0FB +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_30__DA_CELL_AUX_EN_30___POR 0x3F +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_30__DA_CASOFF_BIAS_30___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_30__DA_HS_CTRL_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_30__DA_CELL_EN_30___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_30__DA_CELL_EN_30___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_30__DA_CELL_AUX_EN_30___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_30__DA_CELL_AUX_EN_30___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_30__DA_CASOFF_BIAS_30___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_30__DA_CASOFF_BIAS_30___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_30__DA_HS_CTRL_30___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_30__DA_HS_CTRL_30___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_30___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_30___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_31 (0x005F138C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_31___POR 0xFE9F9000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_31__DA_CELL_EN_31___POR 0x1FD +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_31__DA_CELL_AUX_EN_31___POR 0x3F +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_31__DA_CASOFF_BIAS_31___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_31__DA_HS_CTRL_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_31__DA_CELL_EN_31___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_31__DA_CELL_EN_31___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_31__DA_CELL_AUX_EN_31___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_31__DA_CELL_AUX_EN_31___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_31__DA_CASOFF_BIAS_31___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_31__DA_CASOFF_BIAS_31___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_31__DA_HS_CTRL_31___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_31__DA_HS_CTRL_31___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_31___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA_LUT0_31___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_0 (0x005F1390) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_0__UPC_RGAIN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_0__UPC_RGAIN_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_0__UPC_RGAIN_0___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_0___S 29 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_1 (0x005F1394) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_1__UPC_RGAIN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_1__UPC_RGAIN_1___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_1__UPC_RGAIN_1___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_1___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_1___S 29 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_2 (0x005F1398) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_2__UPC_RGAIN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_2__UPC_RGAIN_2___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_2__UPC_RGAIN_2___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_2___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_2___S 29 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_3 (0x005F139C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_3__UPC_RGAIN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_3__UPC_RGAIN_3___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_3__UPC_RGAIN_3___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_3___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_3___S 29 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_4 (0x005F13A0) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_4__UPC_RGAIN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_4__UPC_RGAIN_4___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_4__UPC_RGAIN_4___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_4___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_4___S 29 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_5 (0x005F13A4) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_5__UPC_RGAIN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_5__UPC_RGAIN_5___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_5__UPC_RGAIN_5___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_5___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_5___S 29 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_6 (0x005F13A8) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_6__UPC_RGAIN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_6__UPC_RGAIN_6___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_6__UPC_RGAIN_6___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_6___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_6___S 29 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_7 (0x005F13AC) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_7__UPC_RGAIN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_7__UPC_RGAIN_7___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_7__UPC_RGAIN_7___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_7___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC_LUT_7___S 29 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0 (0x005F13B0) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0___POR 0x302E4000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_ILEVEL_0___POR 0x06 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_ILEVEL_B2_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX1_0___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX0_0___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_0___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_CASOFF_BIAS_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_ILEVEL_0___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_ILEVEL_0___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_ILEVEL_B2_0___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_ILEVEL_B2_0___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX1_0___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX1_0___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX0_0___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX0_0___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_0___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_0___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_CASOFF_BIAS_0___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0__PA_CASOFF_BIAS_0___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_0___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1 (0x005F13B4) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1___POR 0x302E4000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_ILEVEL_1___POR 0x06 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_ILEVEL_B2_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX1_1___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX0_1___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_1___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_CASOFF_BIAS_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_ILEVEL_1___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_ILEVEL_1___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_ILEVEL_B2_1___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_ILEVEL_B2_1___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX1_1___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX1_1___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX0_1___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX0_1___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_1___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_1___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_CASOFF_BIAS_1___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1__PA_CASOFF_BIAS_1___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_1___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2 (0x005F13B8) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2___POR 0x302E4000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_ILEVEL_2___POR 0x06 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_ILEVEL_B2_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX1_2___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX0_2___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_2___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_CASOFF_BIAS_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_ILEVEL_2___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_ILEVEL_2___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_ILEVEL_B2_2___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_ILEVEL_B2_2___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX1_2___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX1_2___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX0_2___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX0_2___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_2___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_2___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_CASOFF_BIAS_2___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2__PA_CASOFF_BIAS_2___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_2___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3 (0x005F13BC) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3___POR 0x302E4000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_ILEVEL_3___POR 0x06 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_ILEVEL_B2_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX1_3___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX0_3___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_3___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_CASOFF_BIAS_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_ILEVEL_3___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_ILEVEL_3___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_ILEVEL_B2_3___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_ILEVEL_B2_3___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX1_3___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX1_3___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX0_3___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX0_3___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_3___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_3___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_CASOFF_BIAS_3___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3__PA_CASOFF_BIAS_3___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_3___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4 (0x005F13C0) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4___POR 0x302E4000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_ILEVEL_4___POR 0x06 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_ILEVEL_B2_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX1_4___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX0_4___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_4___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_CASOFF_BIAS_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_ILEVEL_4___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_ILEVEL_4___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_ILEVEL_B2_4___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_ILEVEL_B2_4___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX1_4___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX1_4___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX0_4___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX0_4___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_4___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_4___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_CASOFF_BIAS_4___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4__PA_CASOFF_BIAS_4___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_4___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5 (0x005F13C4) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5___POR 0x302E4000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_ILEVEL_5___POR 0x06 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_ILEVEL_B2_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX1_5___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX0_5___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_5___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_CASOFF_BIAS_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_ILEVEL_5___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_ILEVEL_5___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_ILEVEL_B2_5___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_ILEVEL_B2_5___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX1_5___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX1_5___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX0_5___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX0_5___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_5___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_5___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_CASOFF_BIAS_5___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5__PA_CASOFF_BIAS_5___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_5___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6 (0x005F13C8) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6___POR 0x302E4000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_ILEVEL_6___POR 0x06 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_ILEVEL_B2_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_AUX1_6___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_AUX0_6___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_6___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_CASOFF_BIAS_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_ILEVEL_6___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_ILEVEL_6___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_ILEVEL_B2_6___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_ILEVEL_B2_6___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_AUX1_6___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_AUX1_6___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_AUX0_6___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_AUX0_6___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_6___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_CAS_BIAS_6___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_CASOFF_BIAS_6___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6__PA_CASOFF_BIAS_6___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_6___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7 (0x005F13CC) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7___POR 0x302E4000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_ILEVEL_7___POR 0x06 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_ILEVEL_B2_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_AUX1_7___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_AUX0_7___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_7___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_CASOFF_BIAS_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_ILEVEL_7___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_ILEVEL_7___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_ILEVEL_B2_7___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_ILEVEL_B2_7___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_AUX1_7___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_AUX1_7___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_AUX0_7___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_AUX0_7___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_7___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_CAS_BIAS_7___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_CASOFF_BIAS_7___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7__PA_CASOFF_BIAS_7___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_7___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8 (0x005F13D0) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8___POR 0x282EB000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_ILEVEL_8___POR 0x05 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_ILEVEL_B2_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_AUX1_8___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_AUX0_8___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_8___POR 0xB +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_CASOFF_BIAS_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_ILEVEL_8___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_ILEVEL_8___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_ILEVEL_B2_8___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_ILEVEL_B2_8___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_AUX1_8___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_AUX1_8___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_AUX0_8___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_AUX0_8___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_8___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_CAS_BIAS_8___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_CASOFF_BIAS_8___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8__PA_CASOFF_BIAS_8___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_8___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9 (0x005F13D4) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9___POR 0x282EB000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_ILEVEL_9___POR 0x05 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_ILEVEL_B2_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_AUX1_9___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_AUX0_9___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_9___POR 0xB +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_CASOFF_BIAS_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_ILEVEL_9___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_ILEVEL_9___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_ILEVEL_B2_9___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_ILEVEL_B2_9___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_AUX1_9___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_AUX1_9___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_AUX0_9___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_AUX0_9___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_9___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_CAS_BIAS_9___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_CASOFF_BIAS_9___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9__PA_CASOFF_BIAS_9___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_9___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10 (0x005F13D8) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10___POR 0x282EB000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_ILEVEL_10___POR 0x05 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_ILEVEL_B2_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_AUX1_10___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_AUX0_10___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_10___POR 0xB +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_CASOFF_BIAS_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_ILEVEL_10___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_ILEVEL_10___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_ILEVEL_B2_10___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_ILEVEL_B2_10___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_AUX1_10___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_AUX1_10___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_AUX0_10___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_AUX0_10___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_10___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_CAS_BIAS_10___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_CASOFF_BIAS_10___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10__PA_CASOFF_BIAS_10___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_10___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11 (0x005F13DC) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11___POR 0x282EB000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_ILEVEL_11___POR 0x05 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_ILEVEL_B2_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_AUX1_11___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_AUX0_11___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_11___POR 0xB +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_CASOFF_BIAS_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_ILEVEL_11___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_ILEVEL_11___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_ILEVEL_B2_11___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_ILEVEL_B2_11___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_AUX1_11___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_AUX1_11___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_AUX0_11___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_AUX0_11___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_11___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_CAS_BIAS_11___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_CASOFF_BIAS_11___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11__PA_CASOFF_BIAS_11___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_11___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12 (0x005F13E0) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12___POR 0x282EB000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_ILEVEL_12___POR 0x05 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_ILEVEL_B2_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_AUX1_12___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_AUX0_12___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_12___POR 0xB +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_CASOFF_BIAS_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_ILEVEL_12___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_ILEVEL_12___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_ILEVEL_B2_12___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_ILEVEL_B2_12___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_AUX1_12___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_AUX1_12___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_AUX0_12___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_AUX0_12___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_12___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_CAS_BIAS_12___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_CASOFF_BIAS_12___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12__PA_CASOFF_BIAS_12___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_12___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13 (0x005F13E4) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13___POR 0x282EB000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_ILEVEL_13___POR 0x05 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_ILEVEL_B2_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_AUX1_13___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_AUX0_13___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_13___POR 0xB +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_CASOFF_BIAS_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_ILEVEL_13___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_ILEVEL_13___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_ILEVEL_B2_13___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_ILEVEL_B2_13___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_AUX1_13___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_AUX1_13___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_AUX0_13___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_AUX0_13___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_13___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_CAS_BIAS_13___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_CASOFF_BIAS_13___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13__PA_CASOFF_BIAS_13___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_13___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14 (0x005F13E8) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14___POR 0x282EB000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_ILEVEL_14___POR 0x05 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_ILEVEL_B2_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_AUX1_14___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_AUX0_14___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_14___POR 0xB +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_CASOFF_BIAS_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_ILEVEL_14___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_ILEVEL_14___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_ILEVEL_B2_14___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_ILEVEL_B2_14___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_AUX1_14___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_AUX1_14___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_AUX0_14___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_AUX0_14___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_14___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_CAS_BIAS_14___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_CASOFF_BIAS_14___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14__PA_CASOFF_BIAS_14___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_14___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15 (0x005F13EC) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15___POR 0x282EB000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_ILEVEL_15___POR 0x05 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_ILEVEL_B2_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_AUX1_15___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_AUX0_15___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_15___POR 0xB +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_CASOFF_BIAS_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_ILEVEL_15___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_ILEVEL_15___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_ILEVEL_B2_15___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_ILEVEL_B2_15___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_AUX1_15___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_AUX1_15___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_AUX0_15___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_AUX0_15___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_15___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_CAS_BIAS_15___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_CASOFF_BIAS_15___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15__PA_CASOFF_BIAS_15___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT0_15___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0 (0x005F13F0) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0___POR 0xC0300500 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0__PA_CELL_EN1_0___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0__PA_CELL_EN0_0___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0__PA_IBIAS_MODE_0___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0__PA_LP_HS_CTRL_0___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0__PA_LP_CORE_XFRM_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0__PA_CELL_EN1_0___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0__PA_CELL_EN1_0___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0__PA_CELL_EN0_0___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0__PA_CELL_EN0_0___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0__PA_IBIAS_MODE_0___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0__PA_IBIAS_MODE_0___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0__PA_LP_HS_CTRL_0___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0__PA_LP_HS_CTRL_0___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0__PA_LP_CORE_XFRM_0___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0__PA_LP_CORE_XFRM_0___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0___M 0xFFFFFF80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_0___S 7 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1 (0x005F13F4) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1___POR 0xC0300500 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1__PA_CELL_EN1_1___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1__PA_CELL_EN0_1___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1__PA_IBIAS_MODE_1___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1__PA_LP_HS_CTRL_1___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1__PA_LP_CORE_XFRM_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1__PA_CELL_EN1_1___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1__PA_CELL_EN1_1___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1__PA_CELL_EN0_1___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1__PA_CELL_EN0_1___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1__PA_IBIAS_MODE_1___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1__PA_IBIAS_MODE_1___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1__PA_LP_HS_CTRL_1___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1__PA_LP_HS_CTRL_1___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1__PA_LP_CORE_XFRM_1___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1__PA_LP_CORE_XFRM_1___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1___M 0xFFFFFF80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_1___S 7 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2 (0x005F13F8) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2___POR 0xC0300500 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2__PA_CELL_EN1_2___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2__PA_CELL_EN0_2___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2__PA_IBIAS_MODE_2___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2__PA_LP_HS_CTRL_2___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2__PA_LP_CORE_XFRM_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2__PA_CELL_EN1_2___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2__PA_CELL_EN1_2___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2__PA_CELL_EN0_2___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2__PA_CELL_EN0_2___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2__PA_IBIAS_MODE_2___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2__PA_IBIAS_MODE_2___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2__PA_LP_HS_CTRL_2___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2__PA_LP_HS_CTRL_2___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2__PA_LP_CORE_XFRM_2___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2__PA_LP_CORE_XFRM_2___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2___M 0xFFFFFF80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_2___S 7 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3 (0x005F13FC) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3___POR 0xC0300500 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3__PA_CELL_EN1_3___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3__PA_CELL_EN0_3___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3__PA_IBIAS_MODE_3___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3__PA_LP_HS_CTRL_3___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3__PA_LP_CORE_XFRM_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3__PA_CELL_EN1_3___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3__PA_CELL_EN1_3___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3__PA_CELL_EN0_3___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3__PA_CELL_EN0_3___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3__PA_IBIAS_MODE_3___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3__PA_IBIAS_MODE_3___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3__PA_LP_HS_CTRL_3___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3__PA_LP_HS_CTRL_3___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3__PA_LP_CORE_XFRM_3___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3__PA_LP_CORE_XFRM_3___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3___M 0xFFFFFF80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_3___S 7 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4 (0x005F1400) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4___POR 0xC0300500 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4__PA_CELL_EN1_4___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4__PA_CELL_EN0_4___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4__PA_IBIAS_MODE_4___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4__PA_LP_HS_CTRL_4___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4__PA_LP_CORE_XFRM_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4__PA_CELL_EN1_4___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4__PA_CELL_EN1_4___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4__PA_CELL_EN0_4___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4__PA_CELL_EN0_4___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4__PA_IBIAS_MODE_4___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4__PA_IBIAS_MODE_4___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4__PA_LP_HS_CTRL_4___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4__PA_LP_HS_CTRL_4___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4__PA_LP_CORE_XFRM_4___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4__PA_LP_CORE_XFRM_4___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4___M 0xFFFFFF80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_4___S 7 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5 (0x005F1404) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5___POR 0xC0300500 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5__PA_CELL_EN1_5___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5__PA_CELL_EN0_5___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5__PA_IBIAS_MODE_5___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5__PA_LP_HS_CTRL_5___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5__PA_LP_CORE_XFRM_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5__PA_CELL_EN1_5___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5__PA_CELL_EN1_5___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5__PA_CELL_EN0_5___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5__PA_CELL_EN0_5___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5__PA_IBIAS_MODE_5___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5__PA_IBIAS_MODE_5___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5__PA_LP_HS_CTRL_5___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5__PA_LP_HS_CTRL_5___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5__PA_LP_CORE_XFRM_5___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5__PA_LP_CORE_XFRM_5___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5___M 0xFFFFFF80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_5___S 7 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6 (0x005F1408) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6___POR 0xC0300500 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6__PA_CELL_EN1_6___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6__PA_CELL_EN0_6___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6__PA_IBIAS_MODE_6___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6__PA_LP_HS_CTRL_6___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6__PA_LP_CORE_XFRM_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6__PA_CELL_EN1_6___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6__PA_CELL_EN1_6___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6__PA_CELL_EN0_6___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6__PA_CELL_EN0_6___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6__PA_IBIAS_MODE_6___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6__PA_IBIAS_MODE_6___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6__PA_LP_HS_CTRL_6___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6__PA_LP_HS_CTRL_6___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6__PA_LP_CORE_XFRM_6___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6__PA_LP_CORE_XFRM_6___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6___M 0xFFFFFF80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_6___S 7 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7 (0x005F140C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7___POR 0xC0300500 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7__PA_CELL_EN1_7___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7__PA_CELL_EN0_7___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7__PA_IBIAS_MODE_7___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7__PA_LP_HS_CTRL_7___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7__PA_LP_CORE_XFRM_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7__PA_CELL_EN1_7___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7__PA_CELL_EN1_7___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7__PA_CELL_EN0_7___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7__PA_CELL_EN0_7___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7__PA_IBIAS_MODE_7___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7__PA_IBIAS_MODE_7___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7__PA_LP_HS_CTRL_7___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7__PA_LP_HS_CTRL_7___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7__PA_LP_CORE_XFRM_7___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7__PA_LP_CORE_XFRM_7___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7___M 0xFFFFFF80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_7___S 7 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8 (0x005F1410) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8___POR 0x3FCFFD80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8__PA_CELL_EN1_8___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8__PA_CELL_EN0_8___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8__PA_IBIAS_MODE_8___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8__PA_LP_HS_CTRL_8___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8__PA_LP_CORE_XFRM_8___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8__PA_CELL_EN1_8___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8__PA_CELL_EN1_8___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8__PA_CELL_EN0_8___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8__PA_CELL_EN0_8___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8__PA_IBIAS_MODE_8___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8__PA_IBIAS_MODE_8___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8__PA_LP_HS_CTRL_8___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8__PA_LP_HS_CTRL_8___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8__PA_LP_CORE_XFRM_8___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8__PA_LP_CORE_XFRM_8___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8___M 0xFFFFFF80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_8___S 7 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9 (0x005F1414) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9___POR 0x3FCFFD80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9__PA_CELL_EN1_9___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9__PA_CELL_EN0_9___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9__PA_IBIAS_MODE_9___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9__PA_LP_HS_CTRL_9___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9__PA_LP_CORE_XFRM_9___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9__PA_CELL_EN1_9___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9__PA_CELL_EN1_9___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9__PA_CELL_EN0_9___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9__PA_CELL_EN0_9___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9__PA_IBIAS_MODE_9___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9__PA_IBIAS_MODE_9___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9__PA_LP_HS_CTRL_9___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9__PA_LP_HS_CTRL_9___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9__PA_LP_CORE_XFRM_9___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9__PA_LP_CORE_XFRM_9___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9___M 0xFFFFFF80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_9___S 7 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10 (0x005F1418) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10___POR 0x3FCFFD80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10__PA_CELL_EN1_10___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10__PA_CELL_EN0_10___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10__PA_IBIAS_MODE_10___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10__PA_LP_HS_CTRL_10___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10__PA_LP_CORE_XFRM_10___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10__PA_CELL_EN1_10___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10__PA_CELL_EN1_10___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10__PA_CELL_EN0_10___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10__PA_CELL_EN0_10___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10__PA_IBIAS_MODE_10___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10__PA_IBIAS_MODE_10___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10__PA_LP_HS_CTRL_10___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10__PA_LP_HS_CTRL_10___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10__PA_LP_CORE_XFRM_10___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10__PA_LP_CORE_XFRM_10___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10___M 0xFFFFFF80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_10___S 7 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11 (0x005F141C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11___POR 0x3FCFFD80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11__PA_CELL_EN1_11___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11__PA_CELL_EN0_11___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11__PA_IBIAS_MODE_11___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11__PA_LP_HS_CTRL_11___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11__PA_LP_CORE_XFRM_11___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11__PA_CELL_EN1_11___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11__PA_CELL_EN1_11___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11__PA_CELL_EN0_11___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11__PA_CELL_EN0_11___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11__PA_IBIAS_MODE_11___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11__PA_IBIAS_MODE_11___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11__PA_LP_HS_CTRL_11___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11__PA_LP_HS_CTRL_11___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11__PA_LP_CORE_XFRM_11___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11__PA_LP_CORE_XFRM_11___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11___M 0xFFFFFF80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_11___S 7 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12 (0x005F1420) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12___POR 0x3FCFFD80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12__PA_CELL_EN1_12___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12__PA_CELL_EN0_12___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12__PA_IBIAS_MODE_12___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12__PA_LP_HS_CTRL_12___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12__PA_LP_CORE_XFRM_12___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12__PA_CELL_EN1_12___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12__PA_CELL_EN1_12___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12__PA_CELL_EN0_12___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12__PA_CELL_EN0_12___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12__PA_IBIAS_MODE_12___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12__PA_IBIAS_MODE_12___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12__PA_LP_HS_CTRL_12___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12__PA_LP_HS_CTRL_12___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12__PA_LP_CORE_XFRM_12___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12__PA_LP_CORE_XFRM_12___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12___M 0xFFFFFF80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_12___S 7 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13 (0x005F1424) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13___POR 0x3FCFFD80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13__PA_CELL_EN1_13___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13__PA_CELL_EN0_13___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13__PA_IBIAS_MODE_13___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13__PA_LP_HS_CTRL_13___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13__PA_LP_CORE_XFRM_13___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13__PA_CELL_EN1_13___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13__PA_CELL_EN1_13___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13__PA_CELL_EN0_13___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13__PA_CELL_EN0_13___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13__PA_IBIAS_MODE_13___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13__PA_IBIAS_MODE_13___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13__PA_LP_HS_CTRL_13___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13__PA_LP_HS_CTRL_13___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13__PA_LP_CORE_XFRM_13___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13__PA_LP_CORE_XFRM_13___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13___M 0xFFFFFF80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_13___S 7 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14 (0x005F1428) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14___POR 0x3FCFFD80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14__PA_CELL_EN1_14___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14__PA_CELL_EN0_14___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14__PA_IBIAS_MODE_14___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14__PA_LP_HS_CTRL_14___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14__PA_LP_CORE_XFRM_14___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14__PA_CELL_EN1_14___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14__PA_CELL_EN1_14___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14__PA_CELL_EN0_14___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14__PA_CELL_EN0_14___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14__PA_IBIAS_MODE_14___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14__PA_IBIAS_MODE_14___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14__PA_LP_HS_CTRL_14___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14__PA_LP_HS_CTRL_14___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14__PA_LP_CORE_XFRM_14___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14__PA_LP_CORE_XFRM_14___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14___M 0xFFFFFF80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_14___S 7 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15 (0x005F142C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15___POR 0x3FCFFD80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15__PA_CELL_EN1_15___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15__PA_CELL_EN0_15___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15__PA_IBIAS_MODE_15___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15__PA_LP_HS_CTRL_15___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15__PA_LP_CORE_XFRM_15___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15__PA_CELL_EN1_15___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15__PA_CELL_EN1_15___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15__PA_CELL_EN0_15___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15__PA_CELL_EN0_15___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15__PA_IBIAS_MODE_15___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15__PA_IBIAS_MODE_15___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15__PA_LP_HS_CTRL_15___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15__PA_LP_HS_CTRL_15___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15__PA_LP_CORE_XFRM_15___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15__PA_LP_CORE_XFRM_15___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15___M 0xFFFFFF80 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT1_15___S 7 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0 (0x005F1430) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__FE_RFIO_CAP_EN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__PA_CELL_FB_0___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__FE_RFIO_CAP_EN_0___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__FE_RFIO_CAP_EN_0___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__PA_CELL_FB_0___M 0x7FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0__PA_CELL_FB_0___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_0___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1 (0x005F1434) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__FE_RFIO_CAP_EN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__PA_CELL_FB_1___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__FE_RFIO_CAP_EN_1___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__FE_RFIO_CAP_EN_1___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__PA_CELL_FB_1___M 0x7FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1__PA_CELL_FB_1___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_1___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2 (0x005F1438) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__FE_RFIO_CAP_EN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__PA_CELL_FB_2___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__FE_RFIO_CAP_EN_2___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__FE_RFIO_CAP_EN_2___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__PA_CELL_FB_2___M 0x7FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2__PA_CELL_FB_2___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_2___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3 (0x005F143C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__FE_RFIO_CAP_EN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__PA_CELL_FB_3___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__FE_RFIO_CAP_EN_3___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__FE_RFIO_CAP_EN_3___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__PA_CELL_FB_3___M 0x7FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3__PA_CELL_FB_3___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_3___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4 (0x005F1440) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__FE_RFIO_CAP_EN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__PA_CELL_FB_4___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__FE_RFIO_CAP_EN_4___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__FE_RFIO_CAP_EN_4___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__PA_CELL_FB_4___M 0x7FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4__PA_CELL_FB_4___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_4___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5 (0x005F1444) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__FE_RFIO_CAP_EN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__PA_CELL_FB_5___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__FE_RFIO_CAP_EN_5___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__FE_RFIO_CAP_EN_5___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__PA_CELL_FB_5___M 0x7FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5__PA_CELL_FB_5___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_5___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6 (0x005F1448) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__FE_RFIO_CAP_EN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__PA_CELL_FB_6___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__FE_RFIO_CAP_EN_6___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__FE_RFIO_CAP_EN_6___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__PA_CELL_FB_6___M 0x7FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6__PA_CELL_FB_6___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_6___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7 (0x005F144C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__FE_RFIO_CAP_EN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__PA_CELL_FB_7___POR 0x300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__FE_RFIO_CAP_EN_7___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__FE_RFIO_CAP_EN_7___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__PA_CELL_FB_7___M 0x7FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7__PA_CELL_FB_7___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_7___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8 (0x005F1450) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8___POR 0x1FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__FE_RFIO_CAP_EN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__PA_CELL_FB_8___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__FE_RFIO_CAP_EN_8___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__FE_RFIO_CAP_EN_8___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__PA_CELL_FB_8___M 0x7FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8__PA_CELL_FB_8___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_8___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9 (0x005F1454) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9___POR 0x1FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__FE_RFIO_CAP_EN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__PA_CELL_FB_9___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__FE_RFIO_CAP_EN_9___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__FE_RFIO_CAP_EN_9___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__PA_CELL_FB_9___M 0x7FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9__PA_CELL_FB_9___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_9___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10 (0x005F1458) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10___POR 0x1FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__FE_RFIO_CAP_EN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__PA_CELL_FB_10___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__FE_RFIO_CAP_EN_10___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__FE_RFIO_CAP_EN_10___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__PA_CELL_FB_10___M 0x7FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10__PA_CELL_FB_10___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_10___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11 (0x005F145C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11___POR 0x1FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__FE_RFIO_CAP_EN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__PA_CELL_FB_11___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__FE_RFIO_CAP_EN_11___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__FE_RFIO_CAP_EN_11___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__PA_CELL_FB_11___M 0x7FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11__PA_CELL_FB_11___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_11___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12 (0x005F1460) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12___POR 0x1FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__FE_RFIO_CAP_EN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__PA_CELL_FB_12___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__FE_RFIO_CAP_EN_12___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__FE_RFIO_CAP_EN_12___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__PA_CELL_FB_12___M 0x7FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12__PA_CELL_FB_12___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_12___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13 (0x005F1464) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13___POR 0x1FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__FE_RFIO_CAP_EN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__PA_CELL_FB_13___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__FE_RFIO_CAP_EN_13___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__FE_RFIO_CAP_EN_13___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__PA_CELL_FB_13___M 0x7FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13__PA_CELL_FB_13___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_13___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14 (0x005F1468) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14___POR 0x1FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__FE_RFIO_CAP_EN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__PA_CELL_FB_14___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__FE_RFIO_CAP_EN_14___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__FE_RFIO_CAP_EN_14___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__PA_CELL_FB_14___M 0x7FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14__PA_CELL_FB_14___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_14___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15 (0x005F146C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15___POR 0x1FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__FE_RFIO_CAP_EN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__PA_CELL_FB_15___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__FE_RFIO_CAP_EN_15___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__FE_RFIO_CAP_EN_15___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__PA_CELL_FB_15___M 0x7FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15__PA_CELL_FB_15___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA_LUT2_15___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0 (0x005F1470) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_CTUNE3FLO_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_CTUNE3FLO_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_CTUNE1FLO_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_CTUNE1FLO_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__DA_CTUNE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__DA_CTUNE_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_RGAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_RGAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_CTUNE3FLO_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_CTUNE3FLO_OV___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_CTUNE3FLO_OVD___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_CTUNE3FLO_OVD___S 25 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_CTUNE1FLO_OV___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_CTUNE1FLO_OV___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_CTUNE1FLO_OVD___M 0x00FC0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_CTUNE1FLO_OVD___S 18 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__DA_CTUNE_OV___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__DA_CTUNE_OV___S 17 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__DA_CTUNE_OVD___M 0x0001F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__DA_CTUNE_OVD___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_RGAIN_OV___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_RGAIN_OV___S 11 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_RGAIN_OVD___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0__UPC_RGAIN_OVD___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0___M 0xFFFFFF00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV0___S 8 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1 (0x005F1474) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CELL_EN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CELL_EN_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CELL_AUX_EN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CELL_AUX_EN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CASOFF_BIAS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CASOFF_BIAS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_HS_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_HS_CTRL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CELL_EN_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CELL_EN_OV___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CELL_EN_OVD___M 0x7FC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CELL_EN_OVD___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CELL_AUX_EN_OV___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CELL_AUX_EN_OV___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CELL_AUX_EN_OVD___M 0x001FE000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CELL_AUX_EN_OVD___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CASOFF_BIAS_OV___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CASOFF_BIAS_OV___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CASOFF_BIAS_OVD___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_CASOFF_BIAS_OVD___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_HS_CTRL_OV___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_HS_CTRL_OV___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_HS_CTRL_OVD___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1__DA_HS_CTRL_OVD___S 6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1___M 0xFFFFFFC0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV1___S 6 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4 (0x005F1478) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_ILEVEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_ILEVEL_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_ILEVEL_B2_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_ILEVEL_B2_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_AUX1_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_AUX1_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_AUX0_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_AUX0_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CASOFF_BIAS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CASOFF_BIAS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_ILEVEL_OV___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_ILEVEL_OV___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_ILEVEL_OVD___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_ILEVEL_OVD___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_ILEVEL_B2_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_ILEVEL_B2_OV___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_ILEVEL_B2_OVD___M 0x007C0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_ILEVEL_B2_OVD___S 18 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_AUX1_OV___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_AUX1_OV___S 17 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_AUX1_OVD___M 0x0001C000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_AUX1_OVD___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_AUX0_OV___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_AUX0_OV___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_AUX0_OVD___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_AUX0_OVD___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_OV___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_OV___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_OVD___M 0x000001E0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CAS_BIAS_OVD___S 5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CASOFF_BIAS_OV___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CASOFF_BIAS_OV___S 4 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CASOFF_BIAS_OVD___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4__PA_CASOFF_BIAS_OVD___S 1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4___M 0x3FFFFFFE +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV4___S 1 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5 (0x005F147C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_CELL_EN1_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_CELL_EN1_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_CELL_EN0_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_CELL_EN0_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_IBIAS_MODE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_IBIAS_MODE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_LP_HS_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_LP_HS_CTRL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_LP_CORE_XFRM_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_CELL_EN1_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_CELL_EN1_OV___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_CELL_EN1_OVD___M 0x7FE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_CELL_EN1_OVD___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_CELL_EN0_OV___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_CELL_EN0_OV___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_CELL_EN0_OVD___M 0x000FFC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_CELL_EN0_OVD___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_IBIAS_MODE_OV___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_IBIAS_MODE_OV___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_IBIAS_MODE_OVD___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_IBIAS_MODE_OVD___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_LP_HS_CTRL_OV___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_LP_HS_CTRL_OV___S 6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_LP_HS_CTRL_OVD___M 0x00000030 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_LP_HS_CTRL_OVD___S 4 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_LP_CORE_XFRM_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5__PA_LP_CORE_XFRM_OVS___S 2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV5___S 2 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6 (0x005F1480) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__FE_RFIO_CAP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_CELL_FB_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_CELL_FB_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__FE_RFIO_CAP_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__FE_RFIO_CAP_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_CELL_FB_OV___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_CELL_FB_OV___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_CELL_FB_OVD___M 0x1FF80000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6__PA_CELL_FB_OVD___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_LUT_OV6___S 19 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV0 (0x005F1484) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV0___POR 0x000C0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV0__TX_SINGLE_RU_OVS___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV0__TX_LO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV0__TX_LO_LP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV0__TX_SINGLE_RU_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV0__TX_SINGLE_RU_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV0__TX_LO_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV0__TX_LO_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV0__TX_LO_LP_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV0__TX_LO_LP_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV0___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV0___S 14 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1 (0x005F1488) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__CALRTX_ATTN_GM_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__CALRTX_PHASESHIFT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__DA_BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__TXLO_INBUF25DC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__TXLO_LP_INBUF25DC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_AUX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_LO_EN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_LO_EN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_EN_NMX_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_EN_NMX_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_EN_PMX_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_EN_PMX_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__CALRTX_ATTN_GM_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__CALRTX_ATTN_GM_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__CALRTX_PHASESHIFT_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__CALRTX_PHASESHIFT_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__DA_BIAS_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__DA_BIAS_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__TXLO_INBUF25DC_EN_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__TXLO_INBUF25DC_EN_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__TXLO_LP_INBUF25DC_EN_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__TXLO_LP_INBUF25DC_EN_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_AUX_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_AUX_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_LO_EN_OV___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_LO_EN_OV___S 18 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_LO_EN_OVD___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_LO_EN_OVD___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_EN_NMX_OV___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_EN_NMX_OV___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_EN_NMX_OVD___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_EN_NMX_OVD___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_EN_PMX_OV___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_EN_PMX_OV___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_EN_PMX_OVD___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1__UPC_EN_PMX_OVD___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1___M 0xFFF7FC00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV1___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2 (0x005F148C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_BUFTLINE1ST_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_BUFTLINE2ND_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_LP_BUFTLINE1ST_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_LP_BUFTLINE2ND_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_OBUF25DC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_LP_OBUF25DC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__PA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_IPA_SW_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_IPA_CALTXSHIFT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_IPA_GM_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__PA_EN_SW_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_ATTN_HP_SW_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_ATTN_MP_SW_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_BUFTLINE1ST_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_BUFTLINE1ST_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_BUFTLINE2ND_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_BUFTLINE2ND_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_LP_BUFTLINE1ST_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_LP_BUFTLINE1ST_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_LP_BUFTLINE2ND_EN_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_LP_BUFTLINE2ND_EN_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_OBUF25DC_EN_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_OBUF25DC_EN_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_LP_OBUF25DC_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__TXLO_LP_OBUF25DC_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__PA_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__PA_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_IPA_SW_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_IPA_SW_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_IPA_CALTXSHIFT_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_IPA_CALTXSHIFT_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_IPA_GM_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_IPA_GM_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__PA_EN_SW_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__PA_EN_SW_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_ATTN_HP_SW_EN_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_ATTN_HP_SW_EN_OVS___S 6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_ATTN_MP_SW_EN_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2__WL_DPD2_ATTN_MP_SW_EN_OVS___S 4 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2___M 0xFFF3FFF0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_OV2___S 4 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0 (0x005F1490) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_UPC_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_DA_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_FCS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_DA_CTUNE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_TX_SINGLE_RU___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_IPA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_DA_CASOFF_BIAS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_DA_HS_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_UPC_GAIN___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_UPC_GAIN___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_DA_GAIN___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_DA_GAIN___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_FCS___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_FCS___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_DA_CTUNE___M 0x007C0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_DA_CTUNE___S 18 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_TX_SINGLE_RU___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_TX_SINGLE_RU___S 17 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_IPA_GAIN___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_IPA_GAIN___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_DA_CASOFF_BIAS___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_DA_CASOFF_BIAS___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_DA_HS_CTRL___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0__RO_DA_HS_CTRL___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0___M 0xFFFFFF00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT0___S 8 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1 (0x005F1494) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1__RO_DA_CELL_EN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1__RO_DA_CELL_AUX_EN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1__RO_UPC_RGAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1__RO_UPC_CTUNE3FLO___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1__RO_UPC_CTUNE1FLO___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1__RO_DA_CELL_EN___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1__RO_DA_CELL_EN___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1__RO_DA_CELL_AUX_EN___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1__RO_DA_CELL_AUX_EN___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1__RO_UPC_RGAIN___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1__RO_UPC_RGAIN___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1__RO_UPC_CTUNE3FLO___M 0x00000FC0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1__RO_UPC_CTUNE3FLO___S 6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1__RO_UPC_CTUNE1FLO___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1__RO_UPC_CTUNE1FLO___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT1___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3 (0x005F1498) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3__RO_PA_ILEVEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3__RO_PA_ILEVEL_B2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3__RO_PA_ILEVEL___M 0x000007C0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3__RO_PA_ILEVEL___S 6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3__RO_PA_ILEVEL_B2___M 0x0000003E +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3__RO_PA_ILEVEL_B2___S 1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3___M 0x000007FE +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT3___S 1 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4 (0x005F149C) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CASOFF_BIAS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CELL_EN1___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX1___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX1___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX0___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX0___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CASOFF_BIAS___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CASOFF_BIAS___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CELL_EN1___M 0x0007FE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4__RO_PA_CELL_EN1___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT4___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5 (0x005F14A0) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_CELL_EN0___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_LP_HS_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_LP_CORE_XFRM___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_IBIAS_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_FE_RFIO_CAP_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_CELL_FB___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_CELL_EN0___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_CELL_EN0___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_LP_HS_CTRL___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_LP_HS_CTRL___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_LP_CORE_XFRM___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_LP_CORE_XFRM___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_IBIAS_MODE___M 0x00060000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_IBIAS_MODE___S 17 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_FE_RFIO_CAP_EN___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_FE_RFIO_CAP_EN___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_CELL_FB___M 0x0000FFC0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5__RO_PA_CELL_FB___S 6 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5___M 0xFFFFFFC0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LUT5___S 6 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0 (0x005F14A4) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_PA_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_SW_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_CALTXSHIFT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_GM_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_PA_EN_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_ATTN_HP_SW_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_ATTN_MP_SW_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_PA_EN___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_PA_EN___S 30 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_SW_EN___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_SW_EN___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_CALTXSHIFT___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_CALTXSHIFT___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_GM_EN___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_IPA_GM_EN___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_PA_EN_SW___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_PA_EN_SW___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_ATTN_HP_SW_EN___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_ATTN_HP_SW_EN___S 25 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_ATTN_MP_SW_EN___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD2_ATTN_MP_SW_EN___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0___M 0x7F000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_RO_WL_TXFE_LOGIC0___S 24 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0 (0x005F14C0) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0___POR 0x26920D00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_IBIAS_LOWER_LIM_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_IBIAS_LOWER_LIM___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_ISLOPE___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_CAS_BIAS___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_CAS_BIAS_AUX___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_ILEVEL_COARSE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_ILEVEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_BIAS_NOISE_CNCL_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_BIAS_NOISE_CNCL_RES___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_IBIAS_LOWER_LIM_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_IBIAS_LOWER_LIM_EN___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_IBIAS_LOWER_LIM___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_IBIAS_LOWER_LIM___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_ISLOPE___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_ISLOPE___S 25 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_CAS_BIAS___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_CAS_BIAS___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_CAS_BIAS_AUX___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_CAS_BIAS_AUX___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_ILEVEL_COARSE___M 0x00060000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_ILEVEL_COARSE___S 17 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_ILEVEL___M 0x00018000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_ILEVEL___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_ATB_SEL___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_ATB_SEL___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_BIAS_NOISE_CNCL_EN___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_BIAS_NOISE_CNCL_EN___S 11 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_BIAS_NOISE_CNCL_RES___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0__WL_DA_BIAS_NOISE_CNCL_RES___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0___M 0xFFFFFF00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DA0___S 8 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC0 (0x005F14C4) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC0___POR 0xBC000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC0__D_UPC_RSHIFTN___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC0__D_UPC_RSHIFTP___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC0__D_UPC_RMXFILT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC0__D_UPC_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC0__D_UPC_RSHIFTN___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC0__D_UPC_RSHIFTN___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC0__D_UPC_RSHIFTP___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC0__D_UPC_RSHIFTP___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC0__D_UPC_RMXFILT___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC0__D_UPC_RMXFILT___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC0__D_UPC_ATB_SEL___M 0x00600000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC0__D_UPC_ATB_SEL___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC0___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_UPC0___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0 (0x005F14C8) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0___POR 0x00FF00FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_IP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_QP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_IP___POR 0xF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_QP___POR 0xF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_IP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_QP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_IP___POR 0xF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_QP___POR 0xF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_IP___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_IP___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_QP___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_QP___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_IP___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_IP___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_QP___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_QP___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_IP___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_IP___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_QP___M 0x00000F00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_QP___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_IP___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_IP___S 4 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_QP___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_QP___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO0___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1 (0x005F14CC) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1___POR 0x00FF00FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_IN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_QN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_IN___POR 0xF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_QN___POR 0xF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_IN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_QN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_IN___POR 0xF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_QN___POR 0xF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_IN___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_IN___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_QN___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_QN___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_IN___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_IN___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_QN___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_QN___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_IN___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_IN___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_QN___M 0x00000F00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_QN___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_IN___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_IN___S 4 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_QN___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_QN___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_LO1___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL (0x005F14D0) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL___POR 0x04000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL__WL_CALRTX_GC___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL__WL_CALRTX_SW_FLP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL__WL_CALRTX_RES_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL__WL_CALRTX_IBIAS___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL__WL_CALRTX_GC___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL__WL_CALRTX_GC___S 30 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL__WL_CALRTX_SW_FLP___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL__WL_CALRTX_SW_FLP___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL__WL_CALRTX_RES_CTRL___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL__WL_CALRTX_RES_CTRL___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL__WL_CALRTX_IBIAS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL__WL_CALRTX_IBIAS___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL___S 26 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_SPARE (0x005F14D4) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_SPARE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_SPARE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_SPARE__D_TXFE_SPARE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_SPARE__D_TXFE_SPARE___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_SPARE__D_TXFE_SPARE___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_SPARE___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_SPARE___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PPA0 (0x005F14D8) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PPA0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PPA0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PPA0__WL_PPA_INPUT_SW_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PPA0__WL_PPA_INPUT_SW_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PPA0__WL_PPA_INPUT_SW_EN___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PPA0___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PPA0___S 31 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0 (0x005F14DC) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0___POR 0xAA000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_IBIAS_LOWER_LIM_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_IBIAS_LOWER_LIM___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_ISLOPE___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX0_PD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX1_PD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_IBIAS_BOOST___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_IBIAS_LOWER_LIM_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_IBIAS_LOWER_LIM_EN___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_IBIAS_LOWER_LIM___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_IBIAS_LOWER_LIM___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_ISLOPE___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_ISLOPE___S 25 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_ATB_SEL___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_ATB_SEL___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX0_PD___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX0_PD___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX1_PD___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_CAS_BIAS_AUX1_PD___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_IBIAS_BOOST___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0__WL_PA_IBIAS_BOOST___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_PA0___S 19 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY (0x005F14E0) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY__WL_DTOP_CAL_DUMMY1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY__WL_DTOP_CAL_DUMMY0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY__WL_DTOP_DUMMY1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY__WL_DTOP_DUMMY0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY__WL_DTOP_CAL_DUMMY1___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY__WL_DTOP_CAL_DUMMY1___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY__WL_DTOP_CAL_DUMMY0___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY__WL_DTOP_CAL_DUMMY0___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY__WL_DTOP_DUMMY1___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY__WL_DTOP_DUMMY1___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY__WL_DTOP_DUMMY0___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY__WL_DTOP_DUMMY0___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_CAL_DUMMY___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD (0x005F14E4) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD___POR 0x08B80000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_NOTCH_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_CALTXSHIFT_RES_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_TAIL_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_IBIAS_CTRL___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_DEGEN_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_VCAS_CTRL___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_ATTN_CTRL___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_NOTCH_CTRL___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_NOTCH_CTRL___S 30 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_CALTXSHIFT_RES_CTRL___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_CALTXSHIFT_RES_CTRL___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_TAIL_SW___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_TAIL_SW___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_IBIAS_CTRL___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_IBIAS_CTRL___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_DEGEN_CTRL___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_DEGEN_CTRL___S 25 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_VCAS_CTRL___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_GM_VCAS_CTRL___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_ATTN_CTRL___M 0x00780000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD__D_WL_DPD2_IPA_ATTN_CTRL___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_DPD___S 19 + +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR (0x005F1500) +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR___POR 0x6C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR__D_TS_REF_RTUNE___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR__D_TS_RTUNE___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR__D_TS_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR__TS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR__TS_SRC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR__D_TS_REF_RTUNE___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR__D_TS_REF_RTUNE___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR__D_TS_RTUNE___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR__D_TS_RTUNE___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR__D_TS_ATB_SEL___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR__D_TS_ATB_SEL___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR__TS_EN_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR__TS_EN_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR__TS_SRC_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR__TS_SRC_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR___M 0xFDF00000 +#define PHYA_IRON2G_RFA_WL_TXFE_2G_CH1_WL_TXFE_TSENSOR___S 20 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CTRL_0 (0x005F2000) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CTRL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CTRL_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CTRL_0__TPC_STOP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CTRL_0__TPC_STOP___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CTRL_0__TPC_STOP___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CTRL_0___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CTRL_0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT (0x005F2004) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_TEMP_VALID___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_FULLPKT_PWR_VALID___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_PREAMBLE_PWR_VALID___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_TEMP___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_FULLPKT_PWR___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_PREAMBLE_PWR___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_TEMP_VALID___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_TEMP_VALID___S 26 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_FULLPKT_PWR_VALID___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_FULLPKT_PWR_VALID___S 25 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_PREAMBLE_PWR_VALID___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_PREAMBLE_PWR_VALID___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_TEMP___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_TEMP___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_FULLPKT_PWR___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_FULLPKT_PWR___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_PREAMBLE_PWR___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT__RO_PREAMBLE_PWR___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT___M 0x07FFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_RESULT___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0 (0x005F2040) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0___POR 0x000A0026 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__PDADC_CLK_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__PDADC_TEST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_HI_IN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_MID_IN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_LO_IN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_BIAS_COMP_IN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_BIAS_REFBUFF_IN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_PRECHARGEC_IN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ATEST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ATEST_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_SPARE___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_FSMODE_IN___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__PDADC_CLK_SEL___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__PDADC_CLK_SEL___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__PDADC_TEST_EN___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__PDADC_TEST_EN___S 30 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_HI_IN___M 0x38000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_HI_IN___S 27 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_MID_IN___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_MID_IN___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_LO_IN___M 0x00E00000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_LO_IN___S 21 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_BIAS_COMP_IN___M 0x00180000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_BIAS_COMP_IN___S 19 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_BIAS_REFBUFF_IN___M 0x00060000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_BIAS_REFBUFF_IN___S 17 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_PRECHARGEC_IN___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_PRECHARGEC_IN___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ATEST_EN___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ATEST_EN___S 15 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ATEST_SEL___M 0x00007800 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_ATEST_SEL___S 11 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_SPARE___M 0x000007F8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_SPARE___S 3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_FSMODE_IN___M 0x00000006 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0__D_ADC_FSMODE_IN___S 1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_0___S 1 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_1 (0x005F2044) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_1___POR 0x00004020 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_1__PDADC_CLK_POL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_1__ADC_DATA_COMP_REF_HI_GAIN___POR 0x020 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_1__ADC_DATA_COMP_REF_LO_GAIN___POR 0x020 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_1__PDADC_CLK_POL___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_1__PDADC_CLK_POL___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_1__ADC_DATA_COMP_REF_HI_GAIN___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_1__ADC_DATA_COMP_REF_HI_GAIN___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_1__ADC_DATA_COMP_REF_LO_GAIN___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_1__ADC_DATA_COMP_REF_LO_GAIN___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_1___M 0x0007FFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_PDADC_CTRL_1___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_PDADC_DATA (0x005F2048) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_PDADC_DATA___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_PDADC_DATA___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_PDADC_DATA__RO_D_PDADC_DATA___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_PDADC_DATA__RO_D_PDADC_DATA___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_PDADC_DATA__RO_D_PDADC_DATA___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_PDADC_DATA___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_PDADC_DATA___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0 (0x005F2080) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0___POR 0x0200E8B6 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_RESET_L___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CLK_CFG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_PATH_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_DAC_EN___POR 0xE +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_POL___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_BIN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_SETT___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_SMPL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__DC_OFFSET_MODE_MAX_ATTN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_RESET_L___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_RESET_L___S 25 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CLK_CFG___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CLK_CFG___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_PATH_SEL___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_PATH_SEL___S 22 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_EN___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_EN___S 17 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_DAC_EN___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_DAC_EN___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_POL___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_POL___S 10 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_BIN___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_BIN___S 7 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_SETT___M 0x00000070 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_SETT___S 4 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_SMPL___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__TPC_CAL_SMPL___S 1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__DC_OFFSET_MODE_MAX_ATTN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0__DC_OFFSET_MODE_MAX_ATTN___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0___M 0x03C2FCFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1 (0x005F2084) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1___POR 0x00F80204 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_LG___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_PGA_GAIN_CTRL_HG___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___POR 0x10 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG___S 22 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_LG___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__FE_SQ_GAIN_LG___S 20 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_PGA_GAIN_CTRL_HG___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_PGA_GAIN_CTRL_HG___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___M 0x000003E0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___S 5 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1___M 0x00FF03FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2 (0x005F2088) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2___POR 0xECA86420 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_7___POR 0xE +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_6___POR 0xC +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_5___POR 0xA +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_4___POR 0x8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_3___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_2___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_1___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_7___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_7___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_6___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_6___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_5___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_5___S 20 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_4___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_4___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_3___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_3___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_2___M 0x00000F00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_2___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_1___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_1___S 4 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_0___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2__WL_PWR_IDX_0___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_2___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_3 (0x005F208C) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT___S 4 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT_EN___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_3___M 0x000000F1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_CFG_3___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0 (0x005F2090) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_HI___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_HI_CAL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_HI_CAL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_LO___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_LO_CAL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_LO_CAL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_HI___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_HI___S 30 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_HI_CAL___M 0x0FE00000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_HI_CAL___S 21 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_HI_CAL___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_HI_CAL___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_LO___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_LO___S 14 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_LO_CAL___M 0x00000FE0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_LO_CAL___S 5 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_LO_CAL___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_LO_CAL___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0___M 0x4FFF4FFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_BE_CAL_RESULT_0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0 (0x005F2094) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__BE_INT_PDET_PATH_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__FE_SQ_XPA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__FE_SQ_IPA_IS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__FE_SQ_IPA_PO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__FE_VDET_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__PDADC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__BE_TIA_SQBIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__ADC_VREF_IN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__BE_INT_PDET_PATH_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__BE_INT_PDET_PATH_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__FE_SQ_XPA_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__FE_SQ_XPA_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__FE_SQ_IPA_IS_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__FE_SQ_IPA_IS_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__FE_SQ_IPA_PO_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__FE_SQ_IPA_PO_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__FE_VDET_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__FE_VDET_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__PDADC_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__PDADC_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__BE_TIA_SQBIAS_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__BE_TIA_SQBIAS_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__ADC_VREF_IN_EN_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0__ADC_VREF_IN_EN_OVS___S 4 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0___M 0xC03FFC30 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_0___S 4 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1 (0x005F2098) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__PDET_GAIN_IDX_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_SQ_XPA_DUMMY_CURRENT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_SQ_IPA_IS_DUMMY_CURRENT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_SQ_IPA_PO_DUMMY_CURRENT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_XPA_RF_DISCONNECT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_IPA_IS_RF_DISCONNECT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_IPA_PO_RF_DISCONNECT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__PDET_GAIN_IDX_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__PDET_GAIN_IDX_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_SQ_XPA_DUMMY_CURRENT_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_SQ_XPA_DUMMY_CURRENT_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_SQ_IPA_IS_DUMMY_CURRENT_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_SQ_IPA_IS_DUMMY_CURRENT_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_SQ_IPA_PO_DUMMY_CURRENT_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_SQ_IPA_PO_DUMMY_CURRENT_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_XPA_RF_DISCONNECT_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_XPA_RF_DISCONNECT_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_IPA_IS_RF_DISCONNECT_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_IPA_IS_RF_DISCONNECT_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_IPA_PO_RF_DISCONNECT_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1__FE_IPA_PO_RF_DISCONNECT_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1___M 0x0CFFF000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_1___S 12 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2 (0x005F209C) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2___POR 0x000C1010 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__FE_R50_ADJ_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__FE_R50_ADJ_OVD___POR 0x30 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OVD___POR 0x10 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OVD___POR 0x10 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__FE_R50_ADJ_OV___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__FE_R50_ADJ_OV___S 20 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__FE_R50_ADJ_OVD___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__FE_R50_ADJ_OVD___S 14 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OV___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OV___S 13 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OVD___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OVD___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OV___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OV___S 5 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OVD___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2___M 0x001FFF3F +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_2___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3 (0x005F20A0) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3___POR 0x0000B880 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__FE_SQ_IPA_PO_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__FE_SQ_IPA_IS_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__FE_SQ_XPA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_TIA_GAIN_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_PGA_GAIN_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC2_OFFSET_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__TPC_SQR_IC_N_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__TPC_SQR_IC_P_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__TPC_SQR_IPTS_N_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__TPC_SQR_IPTS_P_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OV___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OVD___POR 0x38 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OV___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__FE_SQ_IPA_PO_GAIN_OV___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__FE_SQ_IPA_PO_GAIN_OV___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__FE_SQ_IPA_IS_GAIN_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__FE_SQ_IPA_IS_GAIN_OV___S 27 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__FE_SQ_XPA_GAIN_OV___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__FE_SQ_XPA_GAIN_OV___S 26 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_TIA_GAIN_CTRL_OV___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_TIA_GAIN_CTRL_OV___S 25 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_PGA_GAIN_CTRL_OV___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_PGA_GAIN_CTRL_OV___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_OV___S 23 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC2_OFFSET_OV___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC2_OFFSET_OV___S 22 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__TPC_SQR_IC_N_CTRL_OV___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__TPC_SQR_IC_N_CTRL_OV___S 21 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__TPC_SQR_IC_P_CTRL_OV___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__TPC_SQR_IC_P_CTRL_OV___S 20 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__TPC_SQR_IPTS_N_CTRL_OV___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__TPC_SQR_IPTS_N_CTRL_OV___S 19 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__TPC_SQR_IPTS_P_CTRL_OV___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__TPC_SQR_IPTS_P_CTRL_OV___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OV___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OV___S 15 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OVD___M 0x00007F00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OVD___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OV___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OV___S 7 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OVD___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3___M 0x1FFCFFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_3___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4 (0x005F20A4) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4___POR 0x01010840 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_R50_ADJ_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OVD___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OVD___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OVD___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OVD___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_R50_ADJ_CTRL_OV___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_R50_ADJ_CTRL_OV___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OV___S 27 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OVD___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OVD___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OV___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OV___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OVD___M 0x0003C000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OVD___S 14 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OV___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OV___S 13 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OVD___M 0x00001E00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OVD___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OV___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OV___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OVD___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OVD___S 4 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4___M 0x1B07FFF0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OVERRIDE_4___S 4 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0 (0x005F20A8) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0___POR 0x1D186008 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_FORCE_EN_2P5_CURRENT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_TIA_FB_LOWER_IR_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_TIA_FB_LOWER_IC_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_TIA_FB_TOP_IR_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_TIA_FB_TOP_IC_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_VREF_SET___POR 0x8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__FE_R50_ADJ_HG___POR 0x30 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__FE_R50_ADJ_LG___POR 0x30 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_BW_SEL___POR 0x8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_FORCE_EN_2P5_CURRENT___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_FORCE_EN_2P5_CURRENT___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_TIA_FB_LOWER_IR_EN___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_TIA_FB_LOWER_IR_EN___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_TIA_FB_LOWER_IC_EN___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_TIA_FB_LOWER_IC_EN___S 27 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_TIA_FB_TOP_IR_EN___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_TIA_FB_TOP_IR_EN___S 26 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_TIA_FB_TOP_IC_EN___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_TIA_FB_TOP_IC_EN___S 25 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_VREF_SET___M 0x01E00000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_VREF_SET___S 21 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__FE_R50_ADJ_HG___M 0x001F8000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__FE_R50_ADJ_HG___S 15 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__FE_R50_ADJ_LG___M 0x00007E00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__FE_R50_ADJ_LG___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_BW_SEL___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0__D_BE_BW_SEL___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0___M 0x9FFFFE0F +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_1 (0x005F20AC) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_1___POR 0x00000840 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_1__D_BE_ATB_MUX_SEL___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_1__D_BE_S2DOFFSET_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_1__D_BE_VREF_DEC_SEL___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_1__D_BE_ATB_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_1__D_BE_ATB_MUX_SEL___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_1__D_BE_ATB_MUX_SEL___S 10 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_1__D_BE_S2DOFFSET_SEL___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_1__D_BE_S2DOFFSET_SEL___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_1__D_BE_VREF_DEC_SEL___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_1__D_BE_VREF_DEC_SEL___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_1__D_BE_ATB_SEL___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_1__D_BE_ATB_SEL___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_1___M 0x00000DFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_1___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0 (0x005F20B0) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0___POR 0x036E36DC +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_ATB_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASN_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASP_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_IDAC_CTRL___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_IC_LPF_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_REFGEN_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_IC_VCMOUTGEN_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_TIA_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_VDAC_CTRL___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_ATB_CTRL___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_ATB_CTRL___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASN_CTRL___M 0x00E00000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASN_CTRL___S 21 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASP_CTRL___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASP_CTRL___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_IDAC_CTRL___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_IDAC_CTRL___S 15 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_IC_LPF_CTRL___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_IC_LPF_CTRL___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_REFGEN_CTRL___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_REFGEN_CTRL___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_IC_VCMOUTGEN_CTRL___M 0x000001C0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_IC_VCMOUTGEN_CTRL___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_TIA_CTRL___M 0x00000038 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_TIA_CTRL___S 3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_VDAC_CTRL___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_VDAC_CTRL___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0___M 0x07FFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1 (0x005F20B4) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1___POR 0x0001B6DA +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_IC_PDBUFFER_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IC_PDBUFFER_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_IC_SPARE_0_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_IC_SPARE_1_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IR_ATB_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IR_REFGEN_CTRL___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_IC_PDBUFFER_CTRL___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_IC_PDBUFFER_CTRL___S 15 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IC_PDBUFFER_CTRL___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IC_PDBUFFER_CTRL___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_IC_SPARE_0_CTRL___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_IC_SPARE_0_CTRL___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_IC_SPARE_1_CTRL___M 0x000001C0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_IC_SPARE_1_CTRL___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IR_ATB_CTRL___M 0x00000038 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IR_ATB_CTRL___S 3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IR_REFGEN_CTRL___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IR_REFGEN_CTRL___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1___M 0x0003FFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_1___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2 (0x005F20B8) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2___POR 0x0001B6DC +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_VCMOUTGEN_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_IR_SPARE_0_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_IR_SPARE_1_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_IC_TIA_FB_BIAS___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_OFFSET_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_TIA_FB_BIAS___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_VCMOUTGEN_CTRL___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_VCMOUTGEN_CTRL___S 15 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_IR_SPARE_0_CTRL___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_IR_SPARE_0_CTRL___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_IR_SPARE_1_CTRL___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_IR_SPARE_1_CTRL___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_IC_TIA_FB_BIAS___M 0x000001C0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_IC_TIA_FB_BIAS___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_OFFSET_CTRL___M 0x00000038 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_OFFSET_CTRL___S 3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_TIA_FB_BIAS___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_TIA_FB_BIAS___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2___M 0x0003FFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_IC_IR_BIAS_CTRL_2___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2 (0x005F20BC) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2___POR 0x68000104 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__D_VDET_VREF___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__D_VDET_ROUT_SEL___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__D_VDET_RFIN_DISCONNECT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__D_TPCDPD_SPARE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__D_BE_IR_SQR_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__TPC_SQR_IC_N_CTRL_HG___POR 0x02 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__TPC_SQR_IC_N_CTRL_LG___POR 0x02 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__D_VDET_VREF___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__D_VDET_VREF___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__D_VDET_ROUT_SEL___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__D_VDET_ROUT_SEL___S 25 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__D_VDET_RFIN_DISCONNECT___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__D_VDET_RFIN_DISCONNECT___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__D_TPCDPD_SPARE___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__D_TPCDPD_SPARE___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__D_BE_IR_SQR_CTRL___M 0x0000E000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__D_BE_IR_SQR_CTRL___S 13 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__TPC_SQR_IC_N_CTRL_HG___M 0x00001F80 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__TPC_SQR_IC_N_CTRL_HG___S 7 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__TPC_SQR_IC_N_CTRL_LG___M 0x0000007E +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2__TPC_SQR_IC_N_CTRL_LG___S 1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_2___S 1 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3 (0x005F20C0) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3___POR 0x000C5000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__TPC_SQR_IC_P_CTRL_HG___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__TPC_SQR_IC_P_CTRL_LG___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__D_WL_DPD_GC___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__D_WL_DPD_IBIAS_INV___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__D_WL_DPD_IBIAS_GM___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__D_WL_DPD_RES_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__WL_DPD_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__WL_DPD_CALSHIFT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__TPC_SQR_IC_P_CTRL_HG___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__TPC_SQR_IC_P_CTRL_HG___S 26 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__TPC_SQR_IC_P_CTRL_LG___M 0x03F00000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__TPC_SQR_IC_P_CTRL_LG___S 20 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__D_WL_DPD_GC___M 0x000E0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__D_WL_DPD_GC___S 17 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__D_WL_DPD_IBIAS_INV___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__D_WL_DPD_IBIAS_INV___S 13 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__D_WL_DPD_IBIAS_GM___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__D_WL_DPD_IBIAS_GM___S 10 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__D_WL_DPD_RES_CTRL___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__D_WL_DPD_RES_CTRL___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__WL_DPD_EN_OVS___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__WL_DPD_EN_OVS___S 7 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__WL_DPD_CALSHIFT_OVS___M 0x00000060 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3__WL_DPD_CALSHIFT_OVS___S 5 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3___M 0xFFFE7FE0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_3___S 5 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_4 (0x005F20C4) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_4___POR 0x00000492 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_HG___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_LG___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_HG___POR 0x12 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_LG___POR 0x12 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_HG___M 0x00FC0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_HG___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_LG___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_LG___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_HG___M 0x00000FC0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_HG___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_LG___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_LG___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_4___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_AC_4___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OV_5 (0x005F20C8) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OV_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OV_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OV_5__TPC_BE_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OV_5__VDET_VREF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OV_5__TPC_BE_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OV_5__TPC_BE_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OV_5__VDET_VREF_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OV_5__VDET_VREF_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OV_5___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_OV_5___S 28 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST (0x005F20CC) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST__RBIST_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST__RBIST_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST__RBIST_OV___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST___S 31 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST_OV (0x005F20D0) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST_OV___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST_OV___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST_OV__RBIST_CLPC_PKT_TYPE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST_OV__RBIST_TPC_PDET_GAIN_IDX_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST_OV__RBIST_TPC_ATTEN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST_OV__RBIST_CLPC_PKT_TYPE_OVD___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST_OV__RBIST_CLPC_PKT_TYPE_OVD___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST_OV__RBIST_TPC_PDET_GAIN_IDX_OVD___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST_OV__RBIST_TPC_PDET_GAIN_IDX_OVD___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST_OV__RBIST_TPC_ATTEN_OVD___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST_OV__RBIST_TPC_ATTEN_OVD___S 4 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST_OV___M 0x000003F0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_RBIST_OV___S 4 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0 (0x005F2100) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0___POR 0x1B000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_BIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_POL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_SETT___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_SMPL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_REF___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_BIN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_BIN___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_POL___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_POL___S 30 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_SETT___M 0x38000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_SETT___S 27 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_SMPL___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_SMPL___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_EN___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_EN___S 23 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_REF___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0__LDO_CAL_REF___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0___M 0xFF8001FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_LDO_CAL_0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_LDO_CAL_0 (0x005F2104) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_LDO_CAL_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_LDO_CAL_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_PDADC_DATA___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_RESULT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_PDADC_DATA___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_PDADC_DATA___S 23 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_DONE___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_DONE___S 4 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_RESULT___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_RESULT___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_LDO_CAL_0___M 0xFF80001F +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_LDO_CAL_0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_MEASURE_0 (0x005F2140) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_MEASURE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_MEASURE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_MEASURE_0__SW_MEASURE_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_MEASURE_0__SW_MEASURE_TMR_SETTING___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_MEASURE_0__SW_MEASURE_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_MEASURE_0__SW_MEASURE_EN___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_MEASURE_0__SW_MEASURE_TMR_SETTING___M 0x60000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_MEASURE_0__SW_MEASURE_TMR_SETTING___S 29 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_MEASURE_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_MEASURE_0___S 29 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_MEASURE_0 (0x005F2144) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_MEASURE_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_MEASURE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_MEASURE_0__RO_SW_MEASURE_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_MEASURE_0__RO_SW_MEASURE_RESULT___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_MEASURE_0__RO_SW_MEASURE_DONE___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_MEASURE_0__RO_SW_MEASURE_DONE___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_MEASURE_0__RO_SW_MEASURE_RESULT___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_MEASURE_0__RO_SW_MEASURE_RESULT___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_MEASURE_0___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_MEASURE_0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_AVG_0 (0x005F2148) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_AVG_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_AVG_0___POR 0x08000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_AVG_0__SW_AVG_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_AVG_0__SW_AVG_CFG___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_AVG_0__SW_AVG_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_AVG_0__SW_AVG_EN___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_AVG_0__SW_AVG_CFG___M 0x78000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_AVG_0__SW_AVG_CFG___S 27 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_AVG_0___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_SW_AVG_0___S 27 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_AVG_0 (0x005F214C) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_AVG_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_AVG_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_AVG_0__RO_SW_AVG_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_AVG_0__RO_SW_AVG_RESULT___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_AVG_0__RO_SW_AVG_DONE___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_AVG_0__RO_SW_AVG_DONE___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_AVG_0__RO_SW_AVG_RESULT___M 0x7FC00000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_AVG_0__RO_SW_AVG_RESULT___S 22 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_AVG_0___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_SW_AVG_0___S 22 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1 (0x005F2180) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1___POR 0x073D11C0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PDADC_STROBE_INV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PWR_MEAS_TRIG_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PDACC_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__ATB_MEAS_DUR___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__THERM_MEAS_DUR___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__VOLT_MEAS_DUR___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PD_ACC_WINDOW_CCK___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PD_ACC_WINDOW_OFDM___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PD_DC_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PD_DC_WIN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PD_DC_START___POR 0xC0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PDADC_STROBE_INV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PDADC_STROBE_INV___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS___S 30 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET___S 29 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PWR_MEAS_TRIG_SW___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PWR_MEAS_TRIG_SW___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PDACC_MODE___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PDACC_MODE___S 27 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__ATB_MEAS_DUR___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__ATB_MEAS_DUR___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__THERM_MEAS_DUR___M 0x00E00000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__THERM_MEAS_DUR___S 21 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__VOLT_MEAS_DUR___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__VOLT_MEAS_DUR___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PD_ACC_WINDOW_CCK___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PD_ACC_WINDOW_CCK___S 15 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PD_ACC_WINDOW_OFDM___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PD_ACC_WINDOW_OFDM___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PD_DC_SEL___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PD_DC_SEL___S 11 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PD_DC_WIN___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PD_DC_WIN___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PD_DC_START___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1__PD_DC_START___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_1___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_2 (0x005F2184) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_2___POR 0x00900090 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_2__CLPC_START_OFDM___POR 0x0090 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_2__CLPC_START_CCK___POR 0x0090 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_2__CLPC_START_OFDM___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_2__CLPC_START_OFDM___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_2__CLPC_START_CCK___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_2__CLPC_START_CCK___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_2___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_3_STAT_B0 (0x005F2188) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_3_STAT_B0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_3_STAT_B0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_4_CNT_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_3_CNT_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_2_CNT_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_1_CNT_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_4_CNT_0___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_4_CNT_0___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_3_CNT_0___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_3_CNT_0___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_2_CNT_0___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_2_CNT_0___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_1_CNT_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_1_CNT_0___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_3_STAT_B0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_3_STAT_B0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4 (0x005F218C) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4___POR 0x22685349 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__OLPC_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__FULL_PKT_PWR_ACC_SYM_CNT___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__FULL_PKT_PWR_MEAS_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_PWR_INIT_DUR___POR 0x4D +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_DC_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_ACC_DC_WIN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_DC_INIT_DUR___POR 0x4D +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_ACC_WIN_CCK___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_ACC_WIN_OFDM___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__OLPC_MODE___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__OLPC_MODE___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__FULL_PKT_PWR_ACC_SYM_CNT___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__FULL_PKT_PWR_ACC_SYM_CNT___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__FULL_PKT_PWR_MEAS_EN___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__FULL_PKT_PWR_MEAS_EN___S 27 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_PWR_INIT_DUR___M 0x07F80000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_PWR_INIT_DUR___S 19 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_DC_SEL___M 0x00060000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_DC_SEL___S 17 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_ACC_DC_WIN___M 0x0001C000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_ACC_DC_WIN___S 14 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_DC_INIT_DUR___M 0x00003FC0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_DC_INIT_DUR___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_ACC_WIN_CCK___M 0x00000038 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_ACC_WIN_CCK___S 3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_ACC_WIN_OFDM___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4__PSYM_ACC_WIN_OFDM___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_4___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_5 (0x005F2190) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_5___POR 0x004D4D4D +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_5__FULL_PKT_PWR_INIT_DUR___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_5__ATB_INI_DUR___POR 0x4D +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_5__THERM_INI_DUR___POR 0x4D +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_5__VOLT_INI_DUR___POR 0x4D +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_5__FULL_PKT_PWR_INIT_DUR___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_5__FULL_PKT_PWR_INIT_DUR___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_5__ATB_INI_DUR___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_5__ATB_INI_DUR___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_5__THERM_INI_DUR___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_5__THERM_INI_DUR___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_5__VOLT_INI_DUR___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_5__VOLT_INI_DUR___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_5___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_5___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6 (0x005F2194) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6___POR 0x079E79E7 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__PDADC_STROBE_DLY_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__FULL_PKT_PWR_VALID_THR___POR 0x07 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__ATB_MEAS_DUR_MULTIPLIER___POR 0x27 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__THERM_MEAS_DUR_MULTIPLIER___POR 0x27 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__VOLT_MEAS_DUR_MULTIPLIER___POR 0x27 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__PD_DC_WIN_MULTIPLIER___POR 0x27 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__PDADC_STROBE_DLY_SEL___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__PDADC_STROBE_DLY_SEL___S 30 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__FULL_PKT_PWR_VALID_THR___M 0x3F000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__FULL_PKT_PWR_VALID_THR___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__ATB_MEAS_DUR_MULTIPLIER___M 0x00FC0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__ATB_MEAS_DUR_MULTIPLIER___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__THERM_MEAS_DUR_MULTIPLIER___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__THERM_MEAS_DUR_MULTIPLIER___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__VOLT_MEAS_DUR_MULTIPLIER___M 0x00000FC0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__VOLT_MEAS_DUR_MULTIPLIER___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__PD_DC_WIN_MULTIPLIER___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6__PD_DC_WIN_MULTIPLIER___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_6___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7 (0x005F2198) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7___POR 0x27C27C27 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7__PSYM_ACC_DC_WIN_MULTIPLIER___POR 0x27 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7__PSYM_ACC_WIN_CCK_MULTIPLIER___POR 0x30 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7__PSYM_ACC_WIN_OFDM_MULTIPLIER___POR 0x27 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7__PD_ACC_WINDOW_CCK_MULTIPLIER___POR 0x30 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7__PD_ACC_WINDOW_OFDM_MULTIPLIER___POR 0x27 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7__PSYM_ACC_DC_WIN_MULTIPLIER___M 0x3F000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7__PSYM_ACC_DC_WIN_MULTIPLIER___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7__PSYM_ACC_WIN_CCK_MULTIPLIER___M 0x00FC0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7__PSYM_ACC_WIN_CCK_MULTIPLIER___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7__PSYM_ACC_WIN_OFDM_MULTIPLIER___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7__PSYM_ACC_WIN_OFDM_MULTIPLIER___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7__PD_ACC_WINDOW_CCK_MULTIPLIER___M 0x00000FC0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7__PD_ACC_WINDOW_CCK_MULTIPLIER___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7__PD_ACC_WINDOW_OFDM_MULTIPLIER___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7__PD_ACC_WINDOW_OFDM_MULTIPLIER___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7___M 0x3FFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_7___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_8_B0 (0x005F219C) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_8_B0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_8_B0___POR 0x00008399 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_8_B0__PDADC_BIAS___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_8_B0__INIT_ATB_SETTING_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_8_B0__INIT_VOLT_SETTING_0___POR 0x83 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_8_B0__INIT_THERM_SETTING_0___POR 0x99 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_8_B0__PDADC_BIAS___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_8_B0__PDADC_BIAS___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_8_B0__INIT_ATB_SETTING_0___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_8_B0__INIT_ATB_SETTING_0___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_8_B0__INIT_VOLT_SETTING_0___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_8_B0__INIT_VOLT_SETTING_0___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_8_B0__INIT_THERM_SETTING_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_8_B0__INIT_THERM_SETTING_0___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_8_B0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_8_B0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_9 (0x005F21A0) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_9___POR 0x000001FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_9__PDADC_CLIP_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_9__PDADC_CLIP_THRES___POR 0x1FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_9__PDADC_CLIP_EN___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_9__PDADC_CLIP_EN___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_9__PDADC_CLIP_THRES___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_9__PDADC_CLIP_THRES___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_9___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_9___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_10_B0 (0x005F21A4) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_10_B0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_10_B0___POR 0x01010000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_10_B0__THERM_RESOLUTION_OFFSET___POR 0x80 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_10_B0__THERM_ADC_SCALED_GAIN_0___POR 0x100 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_10_B0__THERM_ADC_OFFSET_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_10_B0__THERM_RESOLUTION_OFFSET___M 0x01FE0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_10_B0__THERM_RESOLUTION_OFFSET___S 17 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_10_B0__THERM_ADC_SCALED_GAIN_0___M 0x0001FF00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_10_B0__THERM_ADC_SCALED_GAIN_0___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_10_B0__THERM_ADC_OFFSET_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_10_B0__THERM_ADC_OFFSET_0___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_10_B0___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_10_B0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_11_STAT_B0 (0x005F21A8) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_11_STAT_B0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_11_STAT_B0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_ATB_VALUE_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_VOLT_VALUE_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_THERM_VALUE_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_ATB_VALUE_0___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_ATB_VALUE_0___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_VOLT_VALUE_0___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_VOLT_VALUE_0___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_THERM_VALUE_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_THERM_VALUE_0___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_11_STAT_B0___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_11_STAT_B0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_12_STAT_B0 (0x005F21AC) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_12_STAT_B0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_12_STAT_B0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_12_STAT_B0__RO_FULL_PKT_AVG_OUT_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_12_STAT_B0__RO_LATEST_DC_VALUE_0___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_12_STAT_B0__RO_PDACC_AVG_OUT_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_12_STAT_B0__RO_FULL_PKT_AVG_OUT_0___M 0x01FE0000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_12_STAT_B0__RO_FULL_PKT_AVG_OUT_0___S 17 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_12_STAT_B0__RO_LATEST_DC_VALUE_0___M 0x0001FF00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_12_STAT_B0__RO_LATEST_DC_VALUE_0___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_12_STAT_B0__RO_PDACC_AVG_OUT_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_12_STAT_B0__RO_PDACC_AVG_OUT_0___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_12_STAT_B0___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_12_STAT_B0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_13 (0x005F21B0) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_13___POR 0x00000001 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_13__TEMP_MEAS_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_13__TPCRB_DELAY___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_13__TEMP_MEAS_SEL___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_13__TEMP_MEAS_SEL___S 3 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_13__TPCRB_DELAY___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_13__TPCRB_DELAY___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_13___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_TPC_FB_13___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14 (0x005F21B4) +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_GNT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_CS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_FB_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_VALID___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_PKT_PWR_MEAS_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_PKT_PWR_MEAS_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_ATB_MEAS_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_THERM_MEAS_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_VOLT_MEAS_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_FB_ABORT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_ACC_NXT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_FB_CS___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_GNT___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_GNT___S 19 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_REQ___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_REQ___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_CS___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_CS___S 15 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_FB_ON___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_FB_ON___S 14 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_VALID___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_VALID___S 13 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_EN___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_EN___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_PKT_PWR_MEAS_DONE___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_PKT_PWR_MEAS_DONE___S 11 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_PKT_PWR_MEAS_ON___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_PKT_PWR_MEAS_ON___S 10 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_ATB_MEAS_ON___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_ATB_MEAS_ON___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_THERM_MEAS_ON___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_THERM_MEAS_ON___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_VOLT_MEAS_ON___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_VOLT_MEAS_ON___S 7 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_FB_ABORT___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_FB_ABORT___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_ACC_NXT___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_ACC_NXT___S 5 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_FB_CS___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14__RO_FB_CS___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_TPC_2G_CH1_RO_TPC_FB_14___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_0 (0x005F4000) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_0__RX_DCOC_RANGE_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_0__RX_DCOC_RES_I_0___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_0__RX_DCOC_RES_Q_0___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_0__RX_DCOC_RANGE_0___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_0__RX_DCOC_RANGE_0___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_0__RX_DCOC_RES_I_0___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_0__RX_DCOC_RES_I_0___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_0__RX_DCOC_RES_Q_0___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_0__RX_DCOC_RES_Q_0___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_0___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1 (0x005F4004) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1__RX_DCOC_RANGE_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1__RX_DCOC_RES_I_1___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1__RX_DCOC_RES_Q_1___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1__RX_DCOC_RANGE_1___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1__RX_DCOC_RANGE_1___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1__RX_DCOC_RES_I_1___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1__RX_DCOC_RES_I_1___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1__RX_DCOC_RES_Q_1___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1__RX_DCOC_RES_Q_1___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_2 (0x005F4008) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_2__RX_DCOC_RANGE_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_2__RX_DCOC_RES_I_2___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_2__RX_DCOC_RES_Q_2___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_2__RX_DCOC_RANGE_2___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_2__RX_DCOC_RANGE_2___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_2__RX_DCOC_RES_I_2___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_2__RX_DCOC_RES_I_2___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_2__RX_DCOC_RES_Q_2___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_2__RX_DCOC_RES_Q_2___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_2___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_2___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_3 (0x005F400C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_3__RX_DCOC_RANGE_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_3__RX_DCOC_RES_I_3___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_3__RX_DCOC_RES_Q_3___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_3__RX_DCOC_RANGE_3___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_3__RX_DCOC_RANGE_3___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_3__RX_DCOC_RES_I_3___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_3__RX_DCOC_RES_I_3___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_3__RX_DCOC_RES_Q_3___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_3__RX_DCOC_RES_Q_3___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_3___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_3___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_4 (0x005F4010) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_4__RX_DCOC_RANGE_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_4__RX_DCOC_RES_I_4___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_4__RX_DCOC_RES_Q_4___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_4__RX_DCOC_RANGE_4___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_4__RX_DCOC_RANGE_4___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_4__RX_DCOC_RES_I_4___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_4__RX_DCOC_RES_I_4___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_4__RX_DCOC_RES_Q_4___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_4__RX_DCOC_RES_Q_4___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_4___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_4___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_5 (0x005F4014) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_5__RX_DCOC_RANGE_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_5__RX_DCOC_RES_I_5___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_5__RX_DCOC_RES_Q_5___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_5__RX_DCOC_RANGE_5___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_5__RX_DCOC_RANGE_5___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_5__RX_DCOC_RES_I_5___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_5__RX_DCOC_RES_I_5___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_5__RX_DCOC_RES_Q_5___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_5__RX_DCOC_RES_Q_5___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_5___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_5___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_6 (0x005F4018) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_6__RX_DCOC_RANGE_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_6__RX_DCOC_RES_I_6___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_6__RX_DCOC_RES_Q_6___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_6__RX_DCOC_RANGE_6___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_6__RX_DCOC_RANGE_6___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_6__RX_DCOC_RES_I_6___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_6__RX_DCOC_RES_I_6___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_6__RX_DCOC_RES_Q_6___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_6__RX_DCOC_RES_Q_6___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_6___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_6___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_7 (0x005F401C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_7__RX_DCOC_RANGE_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_7__RX_DCOC_RES_I_7___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_7__RX_DCOC_RES_Q_7___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_7__RX_DCOC_RANGE_7___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_7__RX_DCOC_RANGE_7___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_7__RX_DCOC_RES_I_7___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_7__RX_DCOC_RES_I_7___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_7__RX_DCOC_RES_Q_7___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_7__RX_DCOC_RES_Q_7___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_7___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_7___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_8 (0x005F4020) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_8__RX_DCOC_RANGE_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_8__RX_DCOC_RES_I_8___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_8__RX_DCOC_RES_Q_8___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_8__RX_DCOC_RANGE_8___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_8__RX_DCOC_RANGE_8___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_8__RX_DCOC_RES_I_8___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_8__RX_DCOC_RES_I_8___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_8__RX_DCOC_RES_Q_8___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_8__RX_DCOC_RES_Q_8___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_8___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_8___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_9 (0x005F4024) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_9__RX_DCOC_RANGE_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_9__RX_DCOC_RES_I_9___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_9__RX_DCOC_RES_Q_9___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_9__RX_DCOC_RANGE_9___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_9__RX_DCOC_RANGE_9___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_9__RX_DCOC_RES_I_9___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_9__RX_DCOC_RES_I_9___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_9__RX_DCOC_RES_Q_9___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_9__RX_DCOC_RES_Q_9___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_9___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_9___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_10 (0x005F4028) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_10__RX_DCOC_RANGE_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_10__RX_DCOC_RES_I_10___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_10__RX_DCOC_RES_Q_10___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_10__RX_DCOC_RANGE_10___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_10__RX_DCOC_RANGE_10___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_10__RX_DCOC_RES_I_10___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_10__RX_DCOC_RES_I_10___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_10__RX_DCOC_RES_Q_10___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_10__RX_DCOC_RES_Q_10___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_10___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_10___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_11 (0x005F402C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_11__RX_DCOC_RANGE_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_11__RX_DCOC_RES_I_11___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_11__RX_DCOC_RES_Q_11___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_11__RX_DCOC_RANGE_11___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_11__RX_DCOC_RANGE_11___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_11__RX_DCOC_RES_I_11___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_11__RX_DCOC_RES_I_11___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_11__RX_DCOC_RES_Q_11___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_11__RX_DCOC_RES_Q_11___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_11___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_11___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_12 (0x005F4030) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_12__RX_DCOC_RANGE_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_12__RX_DCOC_RES_I_12___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_12__RX_DCOC_RES_Q_12___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_12__RX_DCOC_RANGE_12___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_12__RX_DCOC_RANGE_12___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_12__RX_DCOC_RES_I_12___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_12__RX_DCOC_RES_I_12___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_12__RX_DCOC_RES_Q_12___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_12__RX_DCOC_RES_Q_12___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_12___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_12___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_13 (0x005F4034) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_13__RX_DCOC_RANGE_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_13__RX_DCOC_RES_I_13___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_13__RX_DCOC_RES_Q_13___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_13__RX_DCOC_RANGE_13___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_13__RX_DCOC_RANGE_13___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_13__RX_DCOC_RES_I_13___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_13__RX_DCOC_RES_I_13___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_13__RX_DCOC_RES_Q_13___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_13__RX_DCOC_RES_Q_13___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_13___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_13___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_14 (0x005F4038) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_14__RX_DCOC_RANGE_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_14__RX_DCOC_RES_I_14___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_14__RX_DCOC_RES_Q_14___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_14__RX_DCOC_RANGE_14___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_14__RX_DCOC_RANGE_14___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_14__RX_DCOC_RES_I_14___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_14__RX_DCOC_RES_I_14___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_14__RX_DCOC_RES_Q_14___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_14__RX_DCOC_RES_Q_14___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_14___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_14___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_15 (0x005F403C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_15__RX_DCOC_RANGE_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_15__RX_DCOC_RES_I_15___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_15__RX_DCOC_RES_Q_15___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_15__RX_DCOC_RANGE_15___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_15__RX_DCOC_RANGE_15___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_15__RX_DCOC_RES_I_15___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_15__RX_DCOC_RES_I_15___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_15__RX_DCOC_RES_Q_15___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_15__RX_DCOC_RES_Q_15___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_15___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_15___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_16 (0x005F4040) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_16___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_16__RX_DCOC_RANGE_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_16__RX_DCOC_RES_I_16___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_16__RX_DCOC_RES_Q_16___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_16__RX_DCOC_RANGE_16___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_16__RX_DCOC_RANGE_16___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_16__RX_DCOC_RES_I_16___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_16__RX_DCOC_RES_I_16___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_16__RX_DCOC_RES_Q_16___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_16__RX_DCOC_RES_Q_16___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_16___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_16___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_17 (0x005F4044) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_17___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_17__RX_DCOC_RANGE_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_17__RX_DCOC_RES_I_17___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_17__RX_DCOC_RES_Q_17___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_17__RX_DCOC_RANGE_17___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_17__RX_DCOC_RANGE_17___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_17__RX_DCOC_RES_I_17___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_17__RX_DCOC_RES_I_17___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_17__RX_DCOC_RES_Q_17___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_17__RX_DCOC_RES_Q_17___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_17___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_17___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_18 (0x005F4048) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_18___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_18__RX_DCOC_RANGE_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_18__RX_DCOC_RES_I_18___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_18__RX_DCOC_RES_Q_18___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_18__RX_DCOC_RANGE_18___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_18__RX_DCOC_RANGE_18___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_18__RX_DCOC_RES_I_18___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_18__RX_DCOC_RES_I_18___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_18__RX_DCOC_RES_Q_18___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_18__RX_DCOC_RES_Q_18___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_18___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_18___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_19 (0x005F404C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_19___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_19__RX_DCOC_RANGE_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_19__RX_DCOC_RES_I_19___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_19__RX_DCOC_RES_Q_19___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_19__RX_DCOC_RANGE_19___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_19__RX_DCOC_RANGE_19___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_19__RX_DCOC_RES_I_19___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_19__RX_DCOC_RES_I_19___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_19__RX_DCOC_RES_Q_19___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_19__RX_DCOC_RES_Q_19___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_19___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_19___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_20 (0x005F4050) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_20___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_20__RX_DCOC_RANGE_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_20__RX_DCOC_RES_I_20___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_20__RX_DCOC_RES_Q_20___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_20__RX_DCOC_RANGE_20___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_20__RX_DCOC_RANGE_20___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_20__RX_DCOC_RES_I_20___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_20__RX_DCOC_RES_I_20___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_20__RX_DCOC_RES_Q_20___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_20__RX_DCOC_RES_Q_20___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_20___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_20___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_21 (0x005F4054) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_21___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_21__RX_DCOC_RANGE_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_21__RX_DCOC_RES_I_21___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_21__RX_DCOC_RES_Q_21___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_21__RX_DCOC_RANGE_21___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_21__RX_DCOC_RANGE_21___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_21__RX_DCOC_RES_I_21___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_21__RX_DCOC_RES_I_21___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_21__RX_DCOC_RES_Q_21___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_21__RX_DCOC_RES_Q_21___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_21___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_21___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_22 (0x005F4058) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_22___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_22__RX_DCOC_RANGE_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_22__RX_DCOC_RES_I_22___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_22__RX_DCOC_RES_Q_22___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_22__RX_DCOC_RANGE_22___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_22__RX_DCOC_RANGE_22___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_22__RX_DCOC_RES_I_22___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_22__RX_DCOC_RES_I_22___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_22__RX_DCOC_RES_Q_22___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_22__RX_DCOC_RES_Q_22___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_22___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_22___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_23 (0x005F405C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_23___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_23__RX_DCOC_RANGE_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_23__RX_DCOC_RES_I_23___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_23__RX_DCOC_RES_Q_23___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_23__RX_DCOC_RANGE_23___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_23__RX_DCOC_RANGE_23___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_23__RX_DCOC_RES_I_23___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_23__RX_DCOC_RES_I_23___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_23__RX_DCOC_RES_Q_23___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_23__RX_DCOC_RES_Q_23___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_23___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_23___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_24 (0x005F4060) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_24___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_24__RX_DCOC_RANGE_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_24__RX_DCOC_RES_I_24___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_24__RX_DCOC_RES_Q_24___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_24__RX_DCOC_RANGE_24___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_24__RX_DCOC_RANGE_24___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_24__RX_DCOC_RES_I_24___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_24__RX_DCOC_RES_I_24___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_24__RX_DCOC_RES_Q_24___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_24__RX_DCOC_RES_Q_24___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_24___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_24___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_25 (0x005F4064) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_25___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_25__RX_DCOC_RANGE_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_25__RX_DCOC_RES_I_25___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_25__RX_DCOC_RES_Q_25___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_25__RX_DCOC_RANGE_25___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_25__RX_DCOC_RANGE_25___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_25__RX_DCOC_RES_I_25___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_25__RX_DCOC_RES_I_25___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_25__RX_DCOC_RES_Q_25___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_25__RX_DCOC_RES_Q_25___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_25___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_25___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_26 (0x005F4068) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_26___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_26__RX_DCOC_RANGE_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_26__RX_DCOC_RES_I_26___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_26__RX_DCOC_RES_Q_26___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_26__RX_DCOC_RANGE_26___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_26__RX_DCOC_RANGE_26___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_26__RX_DCOC_RES_I_26___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_26__RX_DCOC_RES_I_26___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_26__RX_DCOC_RES_Q_26___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_26__RX_DCOC_RES_Q_26___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_26___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_26___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_27 (0x005F406C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_27___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_27__RX_DCOC_RANGE_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_27__RX_DCOC_RES_I_27___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_27__RX_DCOC_RES_Q_27___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_27__RX_DCOC_RANGE_27___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_27__RX_DCOC_RANGE_27___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_27__RX_DCOC_RES_I_27___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_27__RX_DCOC_RES_I_27___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_27__RX_DCOC_RES_Q_27___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_27__RX_DCOC_RES_Q_27___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_27___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_27___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_28 (0x005F4070) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_28___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_28__RX_DCOC_RANGE_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_28__RX_DCOC_RES_I_28___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_28__RX_DCOC_RES_Q_28___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_28__RX_DCOC_RANGE_28___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_28__RX_DCOC_RANGE_28___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_28__RX_DCOC_RES_I_28___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_28__RX_DCOC_RES_I_28___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_28__RX_DCOC_RES_Q_28___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_28__RX_DCOC_RES_Q_28___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_28___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_28___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_29 (0x005F4074) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_29___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_29__RX_DCOC_RANGE_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_29__RX_DCOC_RES_I_29___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_29__RX_DCOC_RES_Q_29___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_29__RX_DCOC_RANGE_29___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_29__RX_DCOC_RANGE_29___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_29__RX_DCOC_RES_I_29___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_29__RX_DCOC_RES_I_29___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_29__RX_DCOC_RES_Q_29___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_29__RX_DCOC_RES_Q_29___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_29___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_29___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_30 (0x005F4078) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_30___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_30__RX_DCOC_RANGE_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_30__RX_DCOC_RES_I_30___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_30__RX_DCOC_RES_Q_30___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_30__RX_DCOC_RANGE_30___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_30__RX_DCOC_RANGE_30___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_30__RX_DCOC_RES_I_30___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_30__RX_DCOC_RES_I_30___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_30__RX_DCOC_RES_Q_30___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_30__RX_DCOC_RES_Q_30___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_30___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_30___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_31 (0x005F407C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_31___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_31__RX_DCOC_RANGE_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_31__RX_DCOC_RES_I_31___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_31__RX_DCOC_RES_Q_31___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_31__RX_DCOC_RANGE_31___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_31__RX_DCOC_RANGE_31___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_31__RX_DCOC_RES_I_31___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_31__RX_DCOC_RES_I_31___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_31__RX_DCOC_RES_Q_31___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_31__RX_DCOC_RES_Q_31___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_31___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_31___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_32 (0x005F4080) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_32___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_32___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_32__RX_DCOC_RANGE_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_32__RX_DCOC_RES_I_32___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_32__RX_DCOC_RES_Q_32___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_32__RX_DCOC_RANGE_32___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_32__RX_DCOC_RANGE_32___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_32__RX_DCOC_RES_I_32___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_32__RX_DCOC_RES_I_32___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_32__RX_DCOC_RES_Q_32___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_32__RX_DCOC_RES_Q_32___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_32___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_32___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_33 (0x005F4084) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_33___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_33___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_33__RX_DCOC_RANGE_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_33__RX_DCOC_RES_I_33___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_33__RX_DCOC_RES_Q_33___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_33__RX_DCOC_RANGE_33___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_33__RX_DCOC_RANGE_33___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_33__RX_DCOC_RES_I_33___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_33__RX_DCOC_RES_I_33___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_33__RX_DCOC_RES_Q_33___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_33__RX_DCOC_RES_Q_33___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_33___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_33___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_34 (0x005F4088) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_34___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_34___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_34__RX_DCOC_RANGE_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_34__RX_DCOC_RES_I_34___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_34__RX_DCOC_RES_Q_34___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_34__RX_DCOC_RANGE_34___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_34__RX_DCOC_RANGE_34___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_34__RX_DCOC_RES_I_34___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_34__RX_DCOC_RES_I_34___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_34__RX_DCOC_RES_Q_34___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_34__RX_DCOC_RES_Q_34___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_34___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_34___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_35 (0x005F408C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_35___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_35___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_35__RX_DCOC_RANGE_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_35__RX_DCOC_RES_I_35___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_35__RX_DCOC_RES_Q_35___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_35__RX_DCOC_RANGE_35___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_35__RX_DCOC_RANGE_35___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_35__RX_DCOC_RES_I_35___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_35__RX_DCOC_RES_I_35___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_35__RX_DCOC_RES_Q_35___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_35__RX_DCOC_RES_Q_35___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_35___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_35___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_36 (0x005F4090) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_36___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_36___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_36__RX_DCOC_RANGE_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_36__RX_DCOC_RES_I_36___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_36__RX_DCOC_RES_Q_36___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_36__RX_DCOC_RANGE_36___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_36__RX_DCOC_RANGE_36___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_36__RX_DCOC_RES_I_36___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_36__RX_DCOC_RES_I_36___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_36__RX_DCOC_RES_Q_36___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_36__RX_DCOC_RES_Q_36___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_36___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_36___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_37 (0x005F4094) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_37___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_37___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_37__RX_DCOC_RANGE_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_37__RX_DCOC_RES_I_37___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_37__RX_DCOC_RES_Q_37___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_37__RX_DCOC_RANGE_37___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_37__RX_DCOC_RANGE_37___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_37__RX_DCOC_RES_I_37___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_37__RX_DCOC_RES_I_37___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_37__RX_DCOC_RES_Q_37___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_37__RX_DCOC_RES_Q_37___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_37___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_37___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_38 (0x005F4098) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_38___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_38___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_38__RX_DCOC_RANGE_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_38__RX_DCOC_RES_I_38___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_38__RX_DCOC_RES_Q_38___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_38__RX_DCOC_RANGE_38___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_38__RX_DCOC_RANGE_38___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_38__RX_DCOC_RES_I_38___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_38__RX_DCOC_RES_I_38___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_38__RX_DCOC_RES_Q_38___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_38__RX_DCOC_RES_Q_38___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_38___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_38___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_39 (0x005F409C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_39___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_39___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_39__RX_DCOC_RANGE_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_39__RX_DCOC_RES_I_39___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_39__RX_DCOC_RES_Q_39___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_39__RX_DCOC_RANGE_39___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_39__RX_DCOC_RANGE_39___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_39__RX_DCOC_RES_I_39___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_39__RX_DCOC_RES_I_39___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_39__RX_DCOC_RES_Q_39___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_39__RX_DCOC_RES_Q_39___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_39___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_39___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_40 (0x005F40A0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_40___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_40___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_40__RX_DCOC_RANGE_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_40__RX_DCOC_RES_I_40___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_40__RX_DCOC_RES_Q_40___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_40__RX_DCOC_RANGE_40___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_40__RX_DCOC_RANGE_40___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_40__RX_DCOC_RES_I_40___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_40__RX_DCOC_RES_I_40___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_40__RX_DCOC_RES_Q_40___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_40__RX_DCOC_RES_Q_40___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_40___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_40___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_41 (0x005F40A4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_41___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_41___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_41__RX_DCOC_RANGE_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_41__RX_DCOC_RES_I_41___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_41__RX_DCOC_RES_Q_41___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_41__RX_DCOC_RANGE_41___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_41__RX_DCOC_RANGE_41___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_41__RX_DCOC_RES_I_41___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_41__RX_DCOC_RES_I_41___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_41__RX_DCOC_RES_Q_41___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_41__RX_DCOC_RES_Q_41___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_41___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_41___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_42 (0x005F40A8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_42___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_42___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_42__RX_DCOC_RANGE_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_42__RX_DCOC_RES_I_42___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_42__RX_DCOC_RES_Q_42___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_42__RX_DCOC_RANGE_42___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_42__RX_DCOC_RANGE_42___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_42__RX_DCOC_RES_I_42___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_42__RX_DCOC_RES_I_42___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_42__RX_DCOC_RES_Q_42___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_42__RX_DCOC_RES_Q_42___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_42___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_42___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_43 (0x005F40AC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_43___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_43___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_43__RX_DCOC_RANGE_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_43__RX_DCOC_RES_I_43___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_43__RX_DCOC_RES_Q_43___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_43__RX_DCOC_RANGE_43___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_43__RX_DCOC_RANGE_43___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_43__RX_DCOC_RES_I_43___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_43__RX_DCOC_RES_I_43___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_43__RX_DCOC_RES_Q_43___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_43__RX_DCOC_RES_Q_43___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_43___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_43___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_44 (0x005F40B0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_44___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_44___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_44__RX_DCOC_RANGE_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_44__RX_DCOC_RES_I_44___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_44__RX_DCOC_RES_Q_44___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_44__RX_DCOC_RANGE_44___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_44__RX_DCOC_RANGE_44___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_44__RX_DCOC_RES_I_44___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_44__RX_DCOC_RES_I_44___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_44__RX_DCOC_RES_Q_44___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_44__RX_DCOC_RES_Q_44___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_44___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_44___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_45 (0x005F40B4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_45___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_45___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_45__RX_DCOC_RANGE_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_45__RX_DCOC_RES_I_45___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_45__RX_DCOC_RES_Q_45___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_45__RX_DCOC_RANGE_45___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_45__RX_DCOC_RANGE_45___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_45__RX_DCOC_RES_I_45___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_45__RX_DCOC_RES_I_45___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_45__RX_DCOC_RES_Q_45___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_45__RX_DCOC_RES_Q_45___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_45___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_45___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_46 (0x005F40B8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_46___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_46___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_46__RX_DCOC_RANGE_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_46__RX_DCOC_RES_I_46___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_46__RX_DCOC_RES_Q_46___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_46__RX_DCOC_RANGE_46___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_46__RX_DCOC_RANGE_46___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_46__RX_DCOC_RES_I_46___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_46__RX_DCOC_RES_I_46___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_46__RX_DCOC_RES_Q_46___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_46__RX_DCOC_RES_Q_46___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_46___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_46___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_47 (0x005F40BC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_47___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_47___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_47__RX_DCOC_RANGE_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_47__RX_DCOC_RES_I_47___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_47__RX_DCOC_RES_Q_47___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_47__RX_DCOC_RANGE_47___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_47__RX_DCOC_RANGE_47___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_47__RX_DCOC_RES_I_47___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_47__RX_DCOC_RES_I_47___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_47__RX_DCOC_RES_Q_47___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_47__RX_DCOC_RES_Q_47___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_47___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_47___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_48 (0x005F40C0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_48___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_48___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_48__RX_DCOC_RANGE_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_48__RX_DCOC_RES_I_48___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_48__RX_DCOC_RES_Q_48___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_48__RX_DCOC_RANGE_48___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_48__RX_DCOC_RANGE_48___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_48__RX_DCOC_RES_I_48___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_48__RX_DCOC_RES_I_48___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_48__RX_DCOC_RES_Q_48___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_48__RX_DCOC_RES_Q_48___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_48___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_48___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_49 (0x005F40C4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_49___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_49___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_49__RX_DCOC_RANGE_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_49__RX_DCOC_RES_I_49___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_49__RX_DCOC_RES_Q_49___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_49__RX_DCOC_RANGE_49___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_49__RX_DCOC_RANGE_49___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_49__RX_DCOC_RES_I_49___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_49__RX_DCOC_RES_I_49___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_49__RX_DCOC_RES_Q_49___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_49__RX_DCOC_RES_Q_49___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_49___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_49___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_50 (0x005F40C8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_50___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_50___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_50__RX_DCOC_RANGE_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_50__RX_DCOC_RES_I_50___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_50__RX_DCOC_RES_Q_50___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_50__RX_DCOC_RANGE_50___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_50__RX_DCOC_RANGE_50___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_50__RX_DCOC_RES_I_50___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_50__RX_DCOC_RES_I_50___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_50__RX_DCOC_RES_Q_50___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_50__RX_DCOC_RES_Q_50___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_50___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_50___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_51 (0x005F40CC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_51___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_51___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_51__RX_DCOC_RANGE_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_51__RX_DCOC_RES_I_51___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_51__RX_DCOC_RES_Q_51___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_51__RX_DCOC_RANGE_51___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_51__RX_DCOC_RANGE_51___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_51__RX_DCOC_RES_I_51___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_51__RX_DCOC_RES_I_51___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_51__RX_DCOC_RES_Q_51___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_51__RX_DCOC_RES_Q_51___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_51___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_51___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_52 (0x005F40D0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_52___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_52___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_52__RX_DCOC_RANGE_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_52__RX_DCOC_RES_I_52___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_52__RX_DCOC_RES_Q_52___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_52__RX_DCOC_RANGE_52___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_52__RX_DCOC_RANGE_52___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_52__RX_DCOC_RES_I_52___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_52__RX_DCOC_RES_I_52___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_52__RX_DCOC_RES_Q_52___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_52__RX_DCOC_RES_Q_52___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_52___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_52___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_53 (0x005F40D4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_53___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_53___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_53__RX_DCOC_RANGE_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_53__RX_DCOC_RES_I_53___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_53__RX_DCOC_RES_Q_53___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_53__RX_DCOC_RANGE_53___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_53__RX_DCOC_RANGE_53___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_53__RX_DCOC_RES_I_53___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_53__RX_DCOC_RES_I_53___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_53__RX_DCOC_RES_Q_53___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_53__RX_DCOC_RES_Q_53___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_53___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_53___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_54 (0x005F40D8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_54___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_54___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_54__RX_DCOC_RANGE_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_54__RX_DCOC_RES_I_54___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_54__RX_DCOC_RES_Q_54___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_54__RX_DCOC_RANGE_54___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_54__RX_DCOC_RANGE_54___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_54__RX_DCOC_RES_I_54___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_54__RX_DCOC_RES_I_54___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_54__RX_DCOC_RES_Q_54___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_54__RX_DCOC_RES_Q_54___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_54___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_54___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_55 (0x005F40DC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_55___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_55___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_55__RX_DCOC_RANGE_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_55__RX_DCOC_RES_I_55___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_55__RX_DCOC_RES_Q_55___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_55__RX_DCOC_RANGE_55___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_55__RX_DCOC_RANGE_55___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_55__RX_DCOC_RES_I_55___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_55__RX_DCOC_RES_I_55___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_55__RX_DCOC_RES_Q_55___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_55__RX_DCOC_RES_Q_55___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_55___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_55___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_56 (0x005F40E0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_56___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_56___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_56__RX_DCOC_RANGE_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_56__RX_DCOC_RES_I_56___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_56__RX_DCOC_RES_Q_56___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_56__RX_DCOC_RANGE_56___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_56__RX_DCOC_RANGE_56___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_56__RX_DCOC_RES_I_56___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_56__RX_DCOC_RES_I_56___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_56__RX_DCOC_RES_Q_56___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_56__RX_DCOC_RES_Q_56___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_56___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_56___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_57 (0x005F40E4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_57___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_57___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_57__RX_DCOC_RANGE_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_57__RX_DCOC_RES_I_57___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_57__RX_DCOC_RES_Q_57___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_57__RX_DCOC_RANGE_57___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_57__RX_DCOC_RANGE_57___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_57__RX_DCOC_RES_I_57___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_57__RX_DCOC_RES_I_57___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_57__RX_DCOC_RES_Q_57___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_57__RX_DCOC_RES_Q_57___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_57___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_57___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_58 (0x005F40E8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_58___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_58___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_58__RX_DCOC_RANGE_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_58__RX_DCOC_RES_I_58___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_58__RX_DCOC_RES_Q_58___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_58__RX_DCOC_RANGE_58___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_58__RX_DCOC_RANGE_58___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_58__RX_DCOC_RES_I_58___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_58__RX_DCOC_RES_I_58___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_58__RX_DCOC_RES_Q_58___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_58__RX_DCOC_RES_Q_58___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_58___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_58___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_59 (0x005F40EC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_59___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_59___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_59__RX_DCOC_RANGE_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_59__RX_DCOC_RES_I_59___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_59__RX_DCOC_RES_Q_59___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_59__RX_DCOC_RANGE_59___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_59__RX_DCOC_RANGE_59___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_59__RX_DCOC_RES_I_59___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_59__RX_DCOC_RES_I_59___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_59__RX_DCOC_RES_Q_59___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_59__RX_DCOC_RES_Q_59___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_59___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_59___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_60 (0x005F40F0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_60___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_60___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_60__RX_DCOC_RANGE_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_60__RX_DCOC_RES_I_60___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_60__RX_DCOC_RES_Q_60___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_60__RX_DCOC_RANGE_60___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_60__RX_DCOC_RANGE_60___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_60__RX_DCOC_RES_I_60___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_60__RX_DCOC_RES_I_60___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_60__RX_DCOC_RES_Q_60___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_60__RX_DCOC_RES_Q_60___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_60___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_60___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_61 (0x005F40F4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_61___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_61___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_61__RX_DCOC_RANGE_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_61__RX_DCOC_RES_I_61___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_61__RX_DCOC_RES_Q_61___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_61__RX_DCOC_RANGE_61___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_61__RX_DCOC_RANGE_61___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_61__RX_DCOC_RES_I_61___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_61__RX_DCOC_RES_I_61___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_61__RX_DCOC_RES_Q_61___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_61__RX_DCOC_RES_Q_61___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_61___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_61___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_62 (0x005F40F8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_62___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_62___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_62__RX_DCOC_RANGE_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_62__RX_DCOC_RES_I_62___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_62__RX_DCOC_RES_Q_62___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_62__RX_DCOC_RANGE_62___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_62__RX_DCOC_RANGE_62___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_62__RX_DCOC_RES_I_62___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_62__RX_DCOC_RES_I_62___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_62__RX_DCOC_RES_Q_62___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_62__RX_DCOC_RES_Q_62___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_62___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_62___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_63 (0x005F40FC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_63___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_63___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_63__RX_DCOC_RANGE_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_63__RX_DCOC_RES_I_63___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_63__RX_DCOC_RES_Q_63___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_63__RX_DCOC_RANGE_63___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_63__RX_DCOC_RANGE_63___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_63__RX_DCOC_RES_I_63___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_63__RX_DCOC_RES_I_63___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_63__RX_DCOC_RES_Q_63___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_63__RX_DCOC_RES_Q_63___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_63___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_63___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_64 (0x005F4100) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_64___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_64___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_64__RX_DCOC_RANGE_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_64__RX_DCOC_RES_I_64___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_64__RX_DCOC_RES_Q_64___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_64__RX_DCOC_RANGE_64___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_64__RX_DCOC_RANGE_64___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_64__RX_DCOC_RES_I_64___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_64__RX_DCOC_RES_I_64___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_64__RX_DCOC_RES_Q_64___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_64__RX_DCOC_RES_Q_64___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_64___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_64___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_65 (0x005F4104) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_65___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_65___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_65__RX_DCOC_RANGE_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_65__RX_DCOC_RES_I_65___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_65__RX_DCOC_RES_Q_65___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_65__RX_DCOC_RANGE_65___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_65__RX_DCOC_RANGE_65___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_65__RX_DCOC_RES_I_65___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_65__RX_DCOC_RES_I_65___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_65__RX_DCOC_RES_Q_65___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_65__RX_DCOC_RES_Q_65___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_65___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_65___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_66 (0x005F4108) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_66___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_66___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_66__RX_DCOC_RANGE_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_66__RX_DCOC_RES_I_66___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_66__RX_DCOC_RES_Q_66___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_66__RX_DCOC_RANGE_66___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_66__RX_DCOC_RANGE_66___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_66__RX_DCOC_RES_I_66___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_66__RX_DCOC_RES_I_66___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_66__RX_DCOC_RES_Q_66___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_66__RX_DCOC_RES_Q_66___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_66___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_66___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_67 (0x005F410C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_67___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_67___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_67__RX_DCOC_RANGE_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_67__RX_DCOC_RES_I_67___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_67__RX_DCOC_RES_Q_67___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_67__RX_DCOC_RANGE_67___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_67__RX_DCOC_RANGE_67___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_67__RX_DCOC_RES_I_67___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_67__RX_DCOC_RES_I_67___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_67__RX_DCOC_RES_Q_67___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_67__RX_DCOC_RES_Q_67___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_67___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_67___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_68 (0x005F4110) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_68___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_68___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_68__RX_DCOC_RANGE_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_68__RX_DCOC_RES_I_68___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_68__RX_DCOC_RES_Q_68___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_68__RX_DCOC_RANGE_68___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_68__RX_DCOC_RANGE_68___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_68__RX_DCOC_RES_I_68___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_68__RX_DCOC_RES_I_68___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_68__RX_DCOC_RES_Q_68___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_68__RX_DCOC_RES_Q_68___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_68___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_68___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_69 (0x005F4114) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_69___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_69___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_69__RX_DCOC_RANGE_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_69__RX_DCOC_RES_I_69___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_69__RX_DCOC_RES_Q_69___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_69__RX_DCOC_RANGE_69___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_69__RX_DCOC_RANGE_69___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_69__RX_DCOC_RES_I_69___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_69__RX_DCOC_RES_I_69___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_69__RX_DCOC_RES_Q_69___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_69__RX_DCOC_RES_Q_69___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_69___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_69___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_70 (0x005F4118) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_70___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_70___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_70__RX_DCOC_RANGE_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_70__RX_DCOC_RES_I_70___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_70__RX_DCOC_RES_Q_70___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_70__RX_DCOC_RANGE_70___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_70__RX_DCOC_RANGE_70___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_70__RX_DCOC_RES_I_70___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_70__RX_DCOC_RES_I_70___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_70__RX_DCOC_RES_Q_70___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_70__RX_DCOC_RES_Q_70___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_70___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_70___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_71 (0x005F411C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_71___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_71___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_71__RX_DCOC_RANGE_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_71__RX_DCOC_RES_I_71___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_71__RX_DCOC_RES_Q_71___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_71__RX_DCOC_RANGE_71___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_71__RX_DCOC_RANGE_71___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_71__RX_DCOC_RES_I_71___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_71__RX_DCOC_RES_I_71___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_71__RX_DCOC_RES_Q_71___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_71__RX_DCOC_RES_Q_71___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_71___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_71___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_72 (0x005F4120) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_72___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_72___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_72__RX_DCOC_RANGE_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_72__RX_DCOC_RES_I_72___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_72__RX_DCOC_RES_Q_72___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_72__RX_DCOC_RANGE_72___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_72__RX_DCOC_RANGE_72___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_72__RX_DCOC_RES_I_72___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_72__RX_DCOC_RES_I_72___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_72__RX_DCOC_RES_Q_72___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_72__RX_DCOC_RES_Q_72___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_72___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_72___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_73 (0x005F4124) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_73___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_73___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_73__RX_DCOC_RANGE_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_73__RX_DCOC_RES_I_73___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_73__RX_DCOC_RES_Q_73___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_73__RX_DCOC_RANGE_73___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_73__RX_DCOC_RANGE_73___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_73__RX_DCOC_RES_I_73___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_73__RX_DCOC_RES_I_73___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_73__RX_DCOC_RES_Q_73___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_73__RX_DCOC_RES_Q_73___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_73___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_73___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_74 (0x005F4128) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_74___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_74___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_74__RX_DCOC_RANGE_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_74__RX_DCOC_RES_I_74___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_74__RX_DCOC_RES_Q_74___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_74__RX_DCOC_RANGE_74___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_74__RX_DCOC_RANGE_74___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_74__RX_DCOC_RES_I_74___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_74__RX_DCOC_RES_I_74___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_74__RX_DCOC_RES_Q_74___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_74__RX_DCOC_RES_Q_74___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_74___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_74___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_75 (0x005F412C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_75___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_75___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_75__RX_DCOC_RANGE_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_75__RX_DCOC_RES_I_75___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_75__RX_DCOC_RES_Q_75___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_75__RX_DCOC_RANGE_75___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_75__RX_DCOC_RANGE_75___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_75__RX_DCOC_RES_I_75___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_75__RX_DCOC_RES_I_75___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_75__RX_DCOC_RES_Q_75___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_75__RX_DCOC_RES_Q_75___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_75___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_75___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_76 (0x005F4130) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_76___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_76___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_76__RX_DCOC_RANGE_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_76__RX_DCOC_RES_I_76___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_76__RX_DCOC_RES_Q_76___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_76__RX_DCOC_RANGE_76___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_76__RX_DCOC_RANGE_76___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_76__RX_DCOC_RES_I_76___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_76__RX_DCOC_RES_I_76___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_76__RX_DCOC_RES_Q_76___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_76__RX_DCOC_RES_Q_76___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_76___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_76___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_77 (0x005F4134) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_77___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_77___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_77__RX_DCOC_RANGE_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_77__RX_DCOC_RES_I_77___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_77__RX_DCOC_RES_Q_77___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_77__RX_DCOC_RANGE_77___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_77__RX_DCOC_RANGE_77___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_77__RX_DCOC_RES_I_77___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_77__RX_DCOC_RES_I_77___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_77__RX_DCOC_RES_Q_77___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_77__RX_DCOC_RES_Q_77___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_77___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_77___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_78 (0x005F4138) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_78___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_78___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_78__RX_DCOC_RANGE_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_78__RX_DCOC_RES_I_78___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_78__RX_DCOC_RES_Q_78___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_78__RX_DCOC_RANGE_78___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_78__RX_DCOC_RANGE_78___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_78__RX_DCOC_RES_I_78___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_78__RX_DCOC_RES_I_78___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_78__RX_DCOC_RES_Q_78___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_78__RX_DCOC_RES_Q_78___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_78___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_78___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_79 (0x005F413C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_79___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_79___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_79__RX_DCOC_RANGE_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_79__RX_DCOC_RES_I_79___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_79__RX_DCOC_RES_Q_79___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_79__RX_DCOC_RANGE_79___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_79__RX_DCOC_RANGE_79___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_79__RX_DCOC_RES_I_79___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_79__RX_DCOC_RES_I_79___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_79__RX_DCOC_RES_Q_79___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_79__RX_DCOC_RES_Q_79___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_79___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_79___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_80 (0x005F4140) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_80___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_80___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_80__RX_DCOC_RANGE_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_80__RX_DCOC_RES_I_80___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_80__RX_DCOC_RES_Q_80___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_80__RX_DCOC_RANGE_80___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_80__RX_DCOC_RANGE_80___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_80__RX_DCOC_RES_I_80___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_80__RX_DCOC_RES_I_80___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_80__RX_DCOC_RES_Q_80___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_80__RX_DCOC_RES_Q_80___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_80___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_80___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_81 (0x005F4144) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_81___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_81___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_81__RX_DCOC_RANGE_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_81__RX_DCOC_RES_I_81___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_81__RX_DCOC_RES_Q_81___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_81__RX_DCOC_RANGE_81___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_81__RX_DCOC_RANGE_81___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_81__RX_DCOC_RES_I_81___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_81__RX_DCOC_RES_I_81___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_81__RX_DCOC_RES_Q_81___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_81__RX_DCOC_RES_Q_81___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_81___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_81___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_82 (0x005F4148) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_82___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_82___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_82__RX_DCOC_RANGE_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_82__RX_DCOC_RES_I_82___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_82__RX_DCOC_RES_Q_82___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_82__RX_DCOC_RANGE_82___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_82__RX_DCOC_RANGE_82___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_82__RX_DCOC_RES_I_82___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_82__RX_DCOC_RES_I_82___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_82__RX_DCOC_RES_Q_82___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_82__RX_DCOC_RES_Q_82___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_82___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_82___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_83 (0x005F414C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_83___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_83___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_83__RX_DCOC_RANGE_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_83__RX_DCOC_RES_I_83___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_83__RX_DCOC_RES_Q_83___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_83__RX_DCOC_RANGE_83___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_83__RX_DCOC_RANGE_83___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_83__RX_DCOC_RES_I_83___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_83__RX_DCOC_RES_I_83___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_83__RX_DCOC_RES_Q_83___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_83__RX_DCOC_RES_Q_83___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_83___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_83___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_84 (0x005F4150) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_84___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_84___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_84__RX_DCOC_RANGE_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_84__RX_DCOC_RES_I_84___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_84__RX_DCOC_RES_Q_84___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_84__RX_DCOC_RANGE_84___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_84__RX_DCOC_RANGE_84___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_84__RX_DCOC_RES_I_84___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_84__RX_DCOC_RES_I_84___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_84__RX_DCOC_RES_Q_84___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_84__RX_DCOC_RES_Q_84___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_84___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_84___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_85 (0x005F4154) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_85___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_85___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_85__RX_DCOC_RANGE_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_85__RX_DCOC_RES_I_85___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_85__RX_DCOC_RES_Q_85___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_85__RX_DCOC_RANGE_85___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_85__RX_DCOC_RANGE_85___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_85__RX_DCOC_RES_I_85___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_85__RX_DCOC_RES_I_85___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_85__RX_DCOC_RES_Q_85___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_85__RX_DCOC_RES_Q_85___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_85___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_85___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_86 (0x005F4158) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_86___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_86___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_86__RX_DCOC_RANGE_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_86__RX_DCOC_RES_I_86___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_86__RX_DCOC_RES_Q_86___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_86__RX_DCOC_RANGE_86___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_86__RX_DCOC_RANGE_86___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_86__RX_DCOC_RES_I_86___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_86__RX_DCOC_RES_I_86___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_86__RX_DCOC_RES_Q_86___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_86__RX_DCOC_RES_Q_86___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_86___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_86___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_87 (0x005F415C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_87___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_87___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_87__RX_DCOC_RANGE_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_87__RX_DCOC_RES_I_87___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_87__RX_DCOC_RES_Q_87___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_87__RX_DCOC_RANGE_87___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_87__RX_DCOC_RANGE_87___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_87__RX_DCOC_RES_I_87___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_87__RX_DCOC_RES_I_87___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_87__RX_DCOC_RES_Q_87___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_87__RX_DCOC_RES_Q_87___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_87___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_87___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_88 (0x005F4160) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_88___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_88___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_88__RX_DCOC_RANGE_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_88__RX_DCOC_RES_I_88___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_88__RX_DCOC_RES_Q_88___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_88__RX_DCOC_RANGE_88___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_88__RX_DCOC_RANGE_88___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_88__RX_DCOC_RES_I_88___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_88__RX_DCOC_RES_I_88___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_88__RX_DCOC_RES_Q_88___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_88__RX_DCOC_RES_Q_88___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_88___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_88___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_89 (0x005F4164) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_89___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_89___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_89__RX_DCOC_RANGE_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_89__RX_DCOC_RES_I_89___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_89__RX_DCOC_RES_Q_89___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_89__RX_DCOC_RANGE_89___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_89__RX_DCOC_RANGE_89___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_89__RX_DCOC_RES_I_89___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_89__RX_DCOC_RES_I_89___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_89__RX_DCOC_RES_Q_89___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_89__RX_DCOC_RES_Q_89___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_89___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_89___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_90 (0x005F4168) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_90___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_90___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_90__RX_DCOC_RANGE_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_90__RX_DCOC_RES_I_90___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_90__RX_DCOC_RES_Q_90___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_90__RX_DCOC_RANGE_90___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_90__RX_DCOC_RANGE_90___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_90__RX_DCOC_RES_I_90___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_90__RX_DCOC_RES_I_90___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_90__RX_DCOC_RES_Q_90___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_90__RX_DCOC_RES_Q_90___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_90___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_90___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_91 (0x005F416C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_91___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_91___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_91__RX_DCOC_RANGE_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_91__RX_DCOC_RES_I_91___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_91__RX_DCOC_RES_Q_91___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_91__RX_DCOC_RANGE_91___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_91__RX_DCOC_RANGE_91___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_91__RX_DCOC_RES_I_91___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_91__RX_DCOC_RES_I_91___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_91__RX_DCOC_RES_Q_91___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_91__RX_DCOC_RES_Q_91___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_91___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_91___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_92 (0x005F4170) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_92___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_92___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_92__RX_DCOC_RANGE_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_92__RX_DCOC_RES_I_92___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_92__RX_DCOC_RES_Q_92___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_92__RX_DCOC_RANGE_92___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_92__RX_DCOC_RANGE_92___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_92__RX_DCOC_RES_I_92___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_92__RX_DCOC_RES_I_92___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_92__RX_DCOC_RES_Q_92___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_92__RX_DCOC_RES_Q_92___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_92___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_92___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_93 (0x005F4174) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_93___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_93___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_93__RX_DCOC_RANGE_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_93__RX_DCOC_RES_I_93___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_93__RX_DCOC_RES_Q_93___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_93__RX_DCOC_RANGE_93___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_93__RX_DCOC_RANGE_93___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_93__RX_DCOC_RES_I_93___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_93__RX_DCOC_RES_I_93___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_93__RX_DCOC_RES_Q_93___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_93__RX_DCOC_RES_Q_93___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_93___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_93___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_94 (0x005F4178) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_94___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_94___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_94__RX_DCOC_RANGE_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_94__RX_DCOC_RES_I_94___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_94__RX_DCOC_RES_Q_94___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_94__RX_DCOC_RANGE_94___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_94__RX_DCOC_RANGE_94___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_94__RX_DCOC_RES_I_94___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_94__RX_DCOC_RES_I_94___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_94__RX_DCOC_RES_Q_94___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_94__RX_DCOC_RES_Q_94___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_94___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_94___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_95 (0x005F417C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_95___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_95___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_95__RX_DCOC_RANGE_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_95__RX_DCOC_RES_I_95___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_95__RX_DCOC_RES_Q_95___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_95__RX_DCOC_RANGE_95___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_95__RX_DCOC_RANGE_95___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_95__RX_DCOC_RES_I_95___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_95__RX_DCOC_RES_I_95___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_95__RX_DCOC_RES_Q_95___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_95__RX_DCOC_RES_Q_95___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_95___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_95___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_96 (0x005F4180) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_96___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_96___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_96__RX_DCOC_RANGE_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_96__RX_DCOC_RES_I_96___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_96__RX_DCOC_RES_Q_96___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_96__RX_DCOC_RANGE_96___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_96__RX_DCOC_RANGE_96___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_96__RX_DCOC_RES_I_96___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_96__RX_DCOC_RES_I_96___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_96__RX_DCOC_RES_Q_96___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_96__RX_DCOC_RES_Q_96___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_96___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_96___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_97 (0x005F4184) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_97___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_97___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_97__RX_DCOC_RANGE_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_97__RX_DCOC_RES_I_97___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_97__RX_DCOC_RES_Q_97___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_97__RX_DCOC_RANGE_97___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_97__RX_DCOC_RANGE_97___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_97__RX_DCOC_RES_I_97___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_97__RX_DCOC_RES_I_97___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_97__RX_DCOC_RES_Q_97___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_97__RX_DCOC_RES_Q_97___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_97___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_97___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_98 (0x005F4188) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_98___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_98___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_98__RX_DCOC_RANGE_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_98__RX_DCOC_RES_I_98___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_98__RX_DCOC_RES_Q_98___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_98__RX_DCOC_RANGE_98___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_98__RX_DCOC_RANGE_98___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_98__RX_DCOC_RES_I_98___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_98__RX_DCOC_RES_I_98___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_98__RX_DCOC_RES_Q_98___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_98__RX_DCOC_RES_Q_98___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_98___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_98___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_99 (0x005F418C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_99___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_99___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_99__RX_DCOC_RANGE_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_99__RX_DCOC_RES_I_99___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_99__RX_DCOC_RES_Q_99___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_99__RX_DCOC_RANGE_99___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_99__RX_DCOC_RANGE_99___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_99__RX_DCOC_RES_I_99___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_99__RX_DCOC_RES_I_99___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_99__RX_DCOC_RES_Q_99___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_99__RX_DCOC_RES_Q_99___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_99___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_99___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_100 (0x005F4190) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_100___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_100___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_100__RX_DCOC_RANGE_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_100__RX_DCOC_RES_I_100___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_100__RX_DCOC_RES_Q_100___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_100__RX_DCOC_RANGE_100___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_100__RX_DCOC_RANGE_100___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_100__RX_DCOC_RES_I_100___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_100__RX_DCOC_RES_I_100___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_100__RX_DCOC_RES_Q_100___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_100__RX_DCOC_RES_Q_100___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_100___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_100___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_101 (0x005F4194) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_101___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_101___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_101__RX_DCOC_RANGE_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_101__RX_DCOC_RES_I_101___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_101__RX_DCOC_RES_Q_101___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_101__RX_DCOC_RANGE_101___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_101__RX_DCOC_RANGE_101___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_101__RX_DCOC_RES_I_101___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_101__RX_DCOC_RES_I_101___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_101__RX_DCOC_RES_Q_101___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_101__RX_DCOC_RES_Q_101___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_101___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_101___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_102 (0x005F4198) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_102___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_102___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_102__RX_DCOC_RANGE_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_102__RX_DCOC_RES_I_102___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_102__RX_DCOC_RES_Q_102___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_102__RX_DCOC_RANGE_102___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_102__RX_DCOC_RANGE_102___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_102__RX_DCOC_RES_I_102___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_102__RX_DCOC_RES_I_102___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_102__RX_DCOC_RES_Q_102___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_102__RX_DCOC_RES_Q_102___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_102___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_102___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_103 (0x005F419C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_103___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_103___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_103__RX_DCOC_RANGE_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_103__RX_DCOC_RES_I_103___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_103__RX_DCOC_RES_Q_103___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_103__RX_DCOC_RANGE_103___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_103__RX_DCOC_RANGE_103___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_103__RX_DCOC_RES_I_103___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_103__RX_DCOC_RES_I_103___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_103__RX_DCOC_RES_Q_103___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_103__RX_DCOC_RES_Q_103___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_103___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_103___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_104 (0x005F41A0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_104___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_104___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_104__RX_DCOC_RANGE_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_104__RX_DCOC_RES_I_104___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_104__RX_DCOC_RES_Q_104___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_104__RX_DCOC_RANGE_104___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_104__RX_DCOC_RANGE_104___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_104__RX_DCOC_RES_I_104___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_104__RX_DCOC_RES_I_104___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_104__RX_DCOC_RES_Q_104___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_104__RX_DCOC_RES_Q_104___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_104___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_104___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_105 (0x005F41A4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_105___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_105___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_105__RX_DCOC_RANGE_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_105__RX_DCOC_RES_I_105___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_105__RX_DCOC_RES_Q_105___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_105__RX_DCOC_RANGE_105___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_105__RX_DCOC_RANGE_105___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_105__RX_DCOC_RES_I_105___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_105__RX_DCOC_RES_I_105___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_105__RX_DCOC_RES_Q_105___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_105__RX_DCOC_RES_Q_105___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_105___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_105___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_106 (0x005F41A8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_106___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_106___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_106__RX_DCOC_RANGE_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_106__RX_DCOC_RES_I_106___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_106__RX_DCOC_RES_Q_106___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_106__RX_DCOC_RANGE_106___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_106__RX_DCOC_RANGE_106___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_106__RX_DCOC_RES_I_106___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_106__RX_DCOC_RES_I_106___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_106__RX_DCOC_RES_Q_106___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_106__RX_DCOC_RES_Q_106___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_106___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_106___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_107 (0x005F41AC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_107___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_107___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_107__RX_DCOC_RANGE_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_107__RX_DCOC_RES_I_107___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_107__RX_DCOC_RES_Q_107___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_107__RX_DCOC_RANGE_107___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_107__RX_DCOC_RANGE_107___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_107__RX_DCOC_RES_I_107___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_107__RX_DCOC_RES_I_107___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_107__RX_DCOC_RES_Q_107___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_107__RX_DCOC_RES_Q_107___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_107___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_107___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_108 (0x005F41B0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_108___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_108___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_108__RX_DCOC_RANGE_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_108__RX_DCOC_RES_I_108___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_108__RX_DCOC_RES_Q_108___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_108__RX_DCOC_RANGE_108___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_108__RX_DCOC_RANGE_108___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_108__RX_DCOC_RES_I_108___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_108__RX_DCOC_RES_I_108___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_108__RX_DCOC_RES_Q_108___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_108__RX_DCOC_RES_Q_108___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_108___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_108___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_109 (0x005F41B4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_109___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_109___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_109__RX_DCOC_RANGE_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_109__RX_DCOC_RES_I_109___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_109__RX_DCOC_RES_Q_109___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_109__RX_DCOC_RANGE_109___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_109__RX_DCOC_RANGE_109___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_109__RX_DCOC_RES_I_109___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_109__RX_DCOC_RES_I_109___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_109__RX_DCOC_RES_Q_109___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_109__RX_DCOC_RES_Q_109___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_109___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_109___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_110 (0x005F41B8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_110___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_110___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_110__RX_DCOC_RANGE_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_110__RX_DCOC_RES_I_110___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_110__RX_DCOC_RES_Q_110___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_110__RX_DCOC_RANGE_110___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_110__RX_DCOC_RANGE_110___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_110__RX_DCOC_RES_I_110___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_110__RX_DCOC_RES_I_110___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_110__RX_DCOC_RES_Q_110___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_110__RX_DCOC_RES_Q_110___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_110___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_110___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_111 (0x005F41BC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_111___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_111___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_111__RX_DCOC_RANGE_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_111__RX_DCOC_RES_I_111___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_111__RX_DCOC_RES_Q_111___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_111__RX_DCOC_RANGE_111___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_111__RX_DCOC_RANGE_111___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_111__RX_DCOC_RES_I_111___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_111__RX_DCOC_RES_I_111___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_111__RX_DCOC_RES_Q_111___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_111__RX_DCOC_RES_Q_111___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_111___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_111___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_112 (0x005F41C0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_112___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_112___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_112__RX_DCOC_RANGE_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_112__RX_DCOC_RES_I_112___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_112__RX_DCOC_RES_Q_112___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_112__RX_DCOC_RANGE_112___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_112__RX_DCOC_RANGE_112___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_112__RX_DCOC_RES_I_112___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_112__RX_DCOC_RES_I_112___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_112__RX_DCOC_RES_Q_112___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_112__RX_DCOC_RES_Q_112___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_112___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_112___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_113 (0x005F41C4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_113___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_113___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_113__RX_DCOC_RANGE_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_113__RX_DCOC_RES_I_113___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_113__RX_DCOC_RES_Q_113___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_113__RX_DCOC_RANGE_113___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_113__RX_DCOC_RANGE_113___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_113__RX_DCOC_RES_I_113___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_113__RX_DCOC_RES_I_113___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_113__RX_DCOC_RES_Q_113___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_113__RX_DCOC_RES_Q_113___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_113___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_113___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_114 (0x005F41C8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_114___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_114___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_114__RX_DCOC_RANGE_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_114__RX_DCOC_RES_I_114___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_114__RX_DCOC_RES_Q_114___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_114__RX_DCOC_RANGE_114___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_114__RX_DCOC_RANGE_114___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_114__RX_DCOC_RES_I_114___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_114__RX_DCOC_RES_I_114___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_114__RX_DCOC_RES_Q_114___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_114__RX_DCOC_RES_Q_114___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_114___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_114___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_115 (0x005F41CC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_115___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_115___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_115__RX_DCOC_RANGE_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_115__RX_DCOC_RES_I_115___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_115__RX_DCOC_RES_Q_115___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_115__RX_DCOC_RANGE_115___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_115__RX_DCOC_RANGE_115___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_115__RX_DCOC_RES_I_115___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_115__RX_DCOC_RES_I_115___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_115__RX_DCOC_RES_Q_115___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_115__RX_DCOC_RES_Q_115___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_115___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_115___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_116 (0x005F41D0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_116___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_116___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_116__RX_DCOC_RANGE_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_116__RX_DCOC_RES_I_116___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_116__RX_DCOC_RES_Q_116___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_116__RX_DCOC_RANGE_116___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_116__RX_DCOC_RANGE_116___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_116__RX_DCOC_RES_I_116___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_116__RX_DCOC_RES_I_116___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_116__RX_DCOC_RES_Q_116___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_116__RX_DCOC_RES_Q_116___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_116___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_116___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_117 (0x005F41D4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_117___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_117___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_117__RX_DCOC_RANGE_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_117__RX_DCOC_RES_I_117___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_117__RX_DCOC_RES_Q_117___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_117__RX_DCOC_RANGE_117___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_117__RX_DCOC_RANGE_117___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_117__RX_DCOC_RES_I_117___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_117__RX_DCOC_RES_I_117___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_117__RX_DCOC_RES_Q_117___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_117__RX_DCOC_RES_Q_117___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_117___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_117___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_118 (0x005F41D8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_118___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_118___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_118__RX_DCOC_RANGE_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_118__RX_DCOC_RES_I_118___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_118__RX_DCOC_RES_Q_118___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_118__RX_DCOC_RANGE_118___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_118__RX_DCOC_RANGE_118___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_118__RX_DCOC_RES_I_118___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_118__RX_DCOC_RES_I_118___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_118__RX_DCOC_RES_Q_118___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_118__RX_DCOC_RES_Q_118___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_118___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_118___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_119 (0x005F41DC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_119___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_119___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_119__RX_DCOC_RANGE_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_119__RX_DCOC_RES_I_119___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_119__RX_DCOC_RES_Q_119___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_119__RX_DCOC_RANGE_119___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_119__RX_DCOC_RANGE_119___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_119__RX_DCOC_RES_I_119___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_119__RX_DCOC_RES_I_119___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_119__RX_DCOC_RES_Q_119___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_119__RX_DCOC_RES_Q_119___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_119___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_119___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_120 (0x005F41E0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_120___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_120___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_120__RX_DCOC_RANGE_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_120__RX_DCOC_RES_I_120___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_120__RX_DCOC_RES_Q_120___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_120__RX_DCOC_RANGE_120___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_120__RX_DCOC_RANGE_120___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_120__RX_DCOC_RES_I_120___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_120__RX_DCOC_RES_I_120___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_120__RX_DCOC_RES_Q_120___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_120__RX_DCOC_RES_Q_120___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_120___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_120___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_121 (0x005F41E4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_121___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_121___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_121__RX_DCOC_RANGE_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_121__RX_DCOC_RES_I_121___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_121__RX_DCOC_RES_Q_121___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_121__RX_DCOC_RANGE_121___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_121__RX_DCOC_RANGE_121___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_121__RX_DCOC_RES_I_121___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_121__RX_DCOC_RES_I_121___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_121__RX_DCOC_RES_Q_121___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_121__RX_DCOC_RES_Q_121___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_121___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_121___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_122 (0x005F41E8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_122___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_122___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_122__RX_DCOC_RANGE_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_122__RX_DCOC_RES_I_122___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_122__RX_DCOC_RES_Q_122___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_122__RX_DCOC_RANGE_122___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_122__RX_DCOC_RANGE_122___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_122__RX_DCOC_RES_I_122___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_122__RX_DCOC_RES_I_122___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_122__RX_DCOC_RES_Q_122___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_122__RX_DCOC_RES_Q_122___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_122___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_122___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_123 (0x005F41EC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_123___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_123___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_123__RX_DCOC_RANGE_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_123__RX_DCOC_RES_I_123___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_123__RX_DCOC_RES_Q_123___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_123__RX_DCOC_RANGE_123___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_123__RX_DCOC_RANGE_123___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_123__RX_DCOC_RES_I_123___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_123__RX_DCOC_RES_I_123___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_123__RX_DCOC_RES_Q_123___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_123__RX_DCOC_RES_Q_123___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_123___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_123___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_124 (0x005F41F0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_124___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_124___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_124__RX_DCOC_RANGE_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_124__RX_DCOC_RES_I_124___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_124__RX_DCOC_RES_Q_124___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_124__RX_DCOC_RANGE_124___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_124__RX_DCOC_RANGE_124___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_124__RX_DCOC_RES_I_124___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_124__RX_DCOC_RES_I_124___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_124__RX_DCOC_RES_Q_124___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_124__RX_DCOC_RES_Q_124___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_124___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_124___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_125 (0x005F41F4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_125___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_125___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_125__RX_DCOC_RANGE_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_125__RX_DCOC_RES_I_125___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_125__RX_DCOC_RES_Q_125___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_125__RX_DCOC_RANGE_125___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_125__RX_DCOC_RANGE_125___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_125__RX_DCOC_RES_I_125___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_125__RX_DCOC_RES_I_125___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_125__RX_DCOC_RES_Q_125___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_125__RX_DCOC_RES_Q_125___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_125___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_125___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_126 (0x005F41F8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_126___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_126___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_126__RX_DCOC_RANGE_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_126__RX_DCOC_RES_I_126___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_126__RX_DCOC_RES_Q_126___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_126__RX_DCOC_RANGE_126___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_126__RX_DCOC_RANGE_126___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_126__RX_DCOC_RES_I_126___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_126__RX_DCOC_RES_I_126___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_126__RX_DCOC_RES_Q_126___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_126__RX_DCOC_RES_Q_126___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_126___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_126___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_127 (0x005F41FC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_127___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_127___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_127__RX_DCOC_RANGE_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_127__RX_DCOC_RES_I_127___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_127__RX_DCOC_RES_Q_127___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_127__RX_DCOC_RANGE_127___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_127__RX_DCOC_RANGE_127___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_127__RX_DCOC_RES_I_127___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_127__RX_DCOC_RES_I_127___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_127__RX_DCOC_RES_Q_127___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_127__RX_DCOC_RES_Q_127___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_127___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_127___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_128 (0x005F4200) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_128___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_128___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_128__RX_DCOC_RANGE_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_128__RX_DCOC_RES_I_128___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_128__RX_DCOC_RES_Q_128___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_128__RX_DCOC_RANGE_128___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_128__RX_DCOC_RANGE_128___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_128__RX_DCOC_RES_I_128___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_128__RX_DCOC_RES_I_128___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_128__RX_DCOC_RES_Q_128___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_128__RX_DCOC_RES_Q_128___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_128___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_128___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_129 (0x005F4204) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_129___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_129___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_129__RX_DCOC_RANGE_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_129__RX_DCOC_RES_I_129___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_129__RX_DCOC_RES_Q_129___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_129__RX_DCOC_RANGE_129___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_129__RX_DCOC_RANGE_129___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_129__RX_DCOC_RES_I_129___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_129__RX_DCOC_RES_I_129___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_129__RX_DCOC_RES_Q_129___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_129__RX_DCOC_RES_Q_129___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_129___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_129___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_130 (0x005F4208) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_130___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_130___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_130__RX_DCOC_RANGE_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_130__RX_DCOC_RES_I_130___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_130__RX_DCOC_RES_Q_130___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_130__RX_DCOC_RANGE_130___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_130__RX_DCOC_RANGE_130___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_130__RX_DCOC_RES_I_130___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_130__RX_DCOC_RES_I_130___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_130__RX_DCOC_RES_Q_130___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_130__RX_DCOC_RES_Q_130___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_130___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_130___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_131 (0x005F420C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_131___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_131___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_131__RX_DCOC_RANGE_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_131__RX_DCOC_RES_I_131___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_131__RX_DCOC_RES_Q_131___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_131__RX_DCOC_RANGE_131___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_131__RX_DCOC_RANGE_131___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_131__RX_DCOC_RES_I_131___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_131__RX_DCOC_RES_I_131___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_131__RX_DCOC_RES_Q_131___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_131__RX_DCOC_RES_Q_131___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_131___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_131___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_132 (0x005F4210) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_132___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_132___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_132__RX_DCOC_RANGE_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_132__RX_DCOC_RES_I_132___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_132__RX_DCOC_RES_Q_132___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_132__RX_DCOC_RANGE_132___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_132__RX_DCOC_RANGE_132___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_132__RX_DCOC_RES_I_132___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_132__RX_DCOC_RES_I_132___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_132__RX_DCOC_RES_Q_132___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_132__RX_DCOC_RES_Q_132___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_132___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_132___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_133 (0x005F4214) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_133___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_133___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_133__RX_DCOC_RANGE_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_133__RX_DCOC_RES_I_133___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_133__RX_DCOC_RES_Q_133___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_133__RX_DCOC_RANGE_133___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_133__RX_DCOC_RANGE_133___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_133__RX_DCOC_RES_I_133___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_133__RX_DCOC_RES_I_133___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_133__RX_DCOC_RES_Q_133___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_133__RX_DCOC_RES_Q_133___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_133___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_133___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_134 (0x005F4218) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_134___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_134___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_134__RX_DCOC_RANGE_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_134__RX_DCOC_RES_I_134___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_134__RX_DCOC_RES_Q_134___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_134__RX_DCOC_RANGE_134___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_134__RX_DCOC_RANGE_134___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_134__RX_DCOC_RES_I_134___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_134__RX_DCOC_RES_I_134___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_134__RX_DCOC_RES_Q_134___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_134__RX_DCOC_RES_Q_134___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_134___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_134___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_135 (0x005F421C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_135___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_135___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_135__RX_DCOC_RANGE_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_135__RX_DCOC_RES_I_135___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_135__RX_DCOC_RES_Q_135___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_135__RX_DCOC_RANGE_135___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_135__RX_DCOC_RANGE_135___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_135__RX_DCOC_RES_I_135___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_135__RX_DCOC_RES_I_135___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_135__RX_DCOC_RES_Q_135___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_135__RX_DCOC_RES_Q_135___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_135___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_135___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_136 (0x005F4220) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_136___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_136___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_136__RX_DCOC_RANGE_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_136__RX_DCOC_RES_I_136___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_136__RX_DCOC_RES_Q_136___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_136__RX_DCOC_RANGE_136___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_136__RX_DCOC_RANGE_136___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_136__RX_DCOC_RES_I_136___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_136__RX_DCOC_RES_I_136___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_136__RX_DCOC_RES_Q_136___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_136__RX_DCOC_RES_Q_136___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_136___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_136___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_137 (0x005F4224) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_137___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_137___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_137__RX_DCOC_RANGE_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_137__RX_DCOC_RES_I_137___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_137__RX_DCOC_RES_Q_137___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_137__RX_DCOC_RANGE_137___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_137__RX_DCOC_RANGE_137___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_137__RX_DCOC_RES_I_137___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_137__RX_DCOC_RES_I_137___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_137__RX_DCOC_RES_Q_137___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_137__RX_DCOC_RES_Q_137___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_137___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_137___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_138 (0x005F4228) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_138___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_138___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_138__RX_DCOC_RANGE_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_138__RX_DCOC_RES_I_138___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_138__RX_DCOC_RES_Q_138___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_138__RX_DCOC_RANGE_138___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_138__RX_DCOC_RANGE_138___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_138__RX_DCOC_RES_I_138___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_138__RX_DCOC_RES_I_138___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_138__RX_DCOC_RES_Q_138___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_138__RX_DCOC_RES_Q_138___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_138___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_138___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_139 (0x005F422C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_139___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_139___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_139__RX_DCOC_RANGE_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_139__RX_DCOC_RES_I_139___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_139__RX_DCOC_RES_Q_139___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_139__RX_DCOC_RANGE_139___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_139__RX_DCOC_RANGE_139___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_139__RX_DCOC_RES_I_139___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_139__RX_DCOC_RES_I_139___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_139__RX_DCOC_RES_Q_139___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_139__RX_DCOC_RES_Q_139___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_139___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_139___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_140 (0x005F4230) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_140___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_140___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_140__RX_DCOC_RANGE_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_140__RX_DCOC_RES_I_140___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_140__RX_DCOC_RES_Q_140___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_140__RX_DCOC_RANGE_140___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_140__RX_DCOC_RANGE_140___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_140__RX_DCOC_RES_I_140___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_140__RX_DCOC_RES_I_140___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_140__RX_DCOC_RES_Q_140___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_140__RX_DCOC_RES_Q_140___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_140___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_140___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_141 (0x005F4234) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_141___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_141___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_141__RX_DCOC_RANGE_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_141__RX_DCOC_RES_I_141___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_141__RX_DCOC_RES_Q_141___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_141__RX_DCOC_RANGE_141___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_141__RX_DCOC_RANGE_141___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_141__RX_DCOC_RES_I_141___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_141__RX_DCOC_RES_I_141___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_141__RX_DCOC_RES_Q_141___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_141__RX_DCOC_RES_Q_141___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_141___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_141___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_142 (0x005F4238) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_142___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_142___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_142__RX_DCOC_RANGE_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_142__RX_DCOC_RES_I_142___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_142__RX_DCOC_RES_Q_142___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_142__RX_DCOC_RANGE_142___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_142__RX_DCOC_RANGE_142___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_142__RX_DCOC_RES_I_142___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_142__RX_DCOC_RES_I_142___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_142__RX_DCOC_RES_Q_142___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_142__RX_DCOC_RES_Q_142___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_142___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_142___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_143 (0x005F423C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_143___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_143___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_143__RX_DCOC_RANGE_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_143__RX_DCOC_RES_I_143___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_143__RX_DCOC_RES_Q_143___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_143__RX_DCOC_RANGE_143___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_143__RX_DCOC_RANGE_143___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_143__RX_DCOC_RES_I_143___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_143__RX_DCOC_RES_I_143___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_143__RX_DCOC_RES_Q_143___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_143__RX_DCOC_RES_Q_143___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_143___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_143___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_144 (0x005F4240) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_144___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_144___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_144__RX_DCOC_RANGE_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_144__RX_DCOC_RES_I_144___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_144__RX_DCOC_RES_Q_144___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_144__RX_DCOC_RANGE_144___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_144__RX_DCOC_RANGE_144___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_144__RX_DCOC_RES_I_144___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_144__RX_DCOC_RES_I_144___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_144__RX_DCOC_RES_Q_144___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_144__RX_DCOC_RES_Q_144___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_144___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_144___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_145 (0x005F4244) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_145___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_145___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_145__RX_DCOC_RANGE_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_145__RX_DCOC_RES_I_145___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_145__RX_DCOC_RES_Q_145___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_145__RX_DCOC_RANGE_145___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_145__RX_DCOC_RANGE_145___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_145__RX_DCOC_RES_I_145___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_145__RX_DCOC_RES_I_145___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_145__RX_DCOC_RES_Q_145___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_145__RX_DCOC_RES_Q_145___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_145___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_145___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_146 (0x005F4248) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_146___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_146___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_146__RX_DCOC_RANGE_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_146__RX_DCOC_RES_I_146___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_146__RX_DCOC_RES_Q_146___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_146__RX_DCOC_RANGE_146___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_146__RX_DCOC_RANGE_146___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_146__RX_DCOC_RES_I_146___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_146__RX_DCOC_RES_I_146___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_146__RX_DCOC_RES_Q_146___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_146__RX_DCOC_RES_Q_146___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_146___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_146___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_147 (0x005F424C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_147___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_147___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_147__RX_DCOC_RANGE_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_147__RX_DCOC_RES_I_147___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_147__RX_DCOC_RES_Q_147___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_147__RX_DCOC_RANGE_147___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_147__RX_DCOC_RANGE_147___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_147__RX_DCOC_RES_I_147___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_147__RX_DCOC_RES_I_147___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_147__RX_DCOC_RES_Q_147___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_147__RX_DCOC_RES_Q_147___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_147___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_147___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_148 (0x005F4250) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_148___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_148___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_148__RX_DCOC_RANGE_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_148__RX_DCOC_RES_I_148___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_148__RX_DCOC_RES_Q_148___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_148__RX_DCOC_RANGE_148___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_148__RX_DCOC_RANGE_148___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_148__RX_DCOC_RES_I_148___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_148__RX_DCOC_RES_I_148___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_148__RX_DCOC_RES_Q_148___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_148__RX_DCOC_RES_Q_148___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_148___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_148___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_149 (0x005F4254) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_149___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_149___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_149__RX_DCOC_RANGE_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_149__RX_DCOC_RES_I_149___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_149__RX_DCOC_RES_Q_149___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_149__RX_DCOC_RANGE_149___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_149__RX_DCOC_RANGE_149___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_149__RX_DCOC_RES_I_149___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_149__RX_DCOC_RES_I_149___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_149__RX_DCOC_RES_Q_149___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_149__RX_DCOC_RES_Q_149___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_149___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_149___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_150 (0x005F4258) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_150___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_150___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_150__RX_DCOC_RANGE_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_150__RX_DCOC_RES_I_150___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_150__RX_DCOC_RES_Q_150___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_150__RX_DCOC_RANGE_150___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_150__RX_DCOC_RANGE_150___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_150__RX_DCOC_RES_I_150___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_150__RX_DCOC_RES_I_150___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_150__RX_DCOC_RES_Q_150___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_150__RX_DCOC_RES_Q_150___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_150___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_150___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_151 (0x005F425C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_151___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_151___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_151__RX_DCOC_RANGE_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_151__RX_DCOC_RES_I_151___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_151__RX_DCOC_RES_Q_151___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_151__RX_DCOC_RANGE_151___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_151__RX_DCOC_RANGE_151___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_151__RX_DCOC_RES_I_151___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_151__RX_DCOC_RES_I_151___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_151__RX_DCOC_RES_Q_151___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_151__RX_DCOC_RES_Q_151___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_151___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_151___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_152 (0x005F4260) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_152___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_152___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_152__RX_DCOC_RANGE_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_152__RX_DCOC_RES_I_152___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_152__RX_DCOC_RES_Q_152___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_152__RX_DCOC_RANGE_152___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_152__RX_DCOC_RANGE_152___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_152__RX_DCOC_RES_I_152___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_152__RX_DCOC_RES_I_152___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_152__RX_DCOC_RES_Q_152___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_152__RX_DCOC_RES_Q_152___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_152___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_152___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_153 (0x005F4264) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_153___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_153___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_153__RX_DCOC_RANGE_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_153__RX_DCOC_RES_I_153___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_153__RX_DCOC_RES_Q_153___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_153__RX_DCOC_RANGE_153___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_153__RX_DCOC_RANGE_153___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_153__RX_DCOC_RES_I_153___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_153__RX_DCOC_RES_I_153___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_153__RX_DCOC_RES_Q_153___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_153__RX_DCOC_RES_Q_153___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_153___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_153___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_154 (0x005F4268) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_154___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_154___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_154__RX_DCOC_RANGE_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_154__RX_DCOC_RES_I_154___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_154__RX_DCOC_RES_Q_154___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_154__RX_DCOC_RANGE_154___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_154__RX_DCOC_RANGE_154___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_154__RX_DCOC_RES_I_154___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_154__RX_DCOC_RES_I_154___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_154__RX_DCOC_RES_Q_154___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_154__RX_DCOC_RES_Q_154___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_154___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_154___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_155 (0x005F426C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_155___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_155___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_155__RX_DCOC_RANGE_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_155__RX_DCOC_RES_I_155___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_155__RX_DCOC_RES_Q_155___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_155__RX_DCOC_RANGE_155___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_155__RX_DCOC_RANGE_155___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_155__RX_DCOC_RES_I_155___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_155__RX_DCOC_RES_I_155___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_155__RX_DCOC_RES_Q_155___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_155__RX_DCOC_RES_Q_155___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_155___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_155___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_156 (0x005F4270) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_156___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_156___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_156__RX_DCOC_RANGE_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_156__RX_DCOC_RES_I_156___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_156__RX_DCOC_RES_Q_156___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_156__RX_DCOC_RANGE_156___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_156__RX_DCOC_RANGE_156___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_156__RX_DCOC_RES_I_156___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_156__RX_DCOC_RES_I_156___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_156__RX_DCOC_RES_Q_156___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_156__RX_DCOC_RES_Q_156___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_156___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_156___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_157 (0x005F4274) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_157___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_157___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_157__RX_DCOC_RANGE_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_157__RX_DCOC_RES_I_157___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_157__RX_DCOC_RES_Q_157___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_157__RX_DCOC_RANGE_157___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_157__RX_DCOC_RANGE_157___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_157__RX_DCOC_RES_I_157___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_157__RX_DCOC_RES_I_157___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_157__RX_DCOC_RES_Q_157___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_157__RX_DCOC_RES_Q_157___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_157___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_157___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_158 (0x005F4278) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_158___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_158___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_158__RX_DCOC_RANGE_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_158__RX_DCOC_RES_I_158___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_158__RX_DCOC_RES_Q_158___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_158__RX_DCOC_RANGE_158___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_158__RX_DCOC_RANGE_158___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_158__RX_DCOC_RES_I_158___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_158__RX_DCOC_RES_I_158___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_158__RX_DCOC_RES_Q_158___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_158__RX_DCOC_RES_Q_158___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_158___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_158___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_159 (0x005F427C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_159___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_159___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_159__RX_DCOC_RANGE_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_159__RX_DCOC_RES_I_159___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_159__RX_DCOC_RES_Q_159___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_159__RX_DCOC_RANGE_159___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_159__RX_DCOC_RANGE_159___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_159__RX_DCOC_RES_I_159___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_159__RX_DCOC_RES_I_159___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_159__RX_DCOC_RES_Q_159___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_159__RX_DCOC_RES_Q_159___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_159___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_159___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_160 (0x005F4280) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_160___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_160___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_160__RX_DCOC_RANGE_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_160__RX_DCOC_RES_I_160___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_160__RX_DCOC_RES_Q_160___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_160__RX_DCOC_RANGE_160___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_160__RX_DCOC_RANGE_160___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_160__RX_DCOC_RES_I_160___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_160__RX_DCOC_RES_I_160___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_160__RX_DCOC_RES_Q_160___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_160__RX_DCOC_RES_Q_160___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_160___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_160___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_161 (0x005F4284) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_161___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_161___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_161__RX_DCOC_RANGE_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_161__RX_DCOC_RES_I_161___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_161__RX_DCOC_RES_Q_161___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_161__RX_DCOC_RANGE_161___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_161__RX_DCOC_RANGE_161___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_161__RX_DCOC_RES_I_161___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_161__RX_DCOC_RES_I_161___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_161__RX_DCOC_RES_Q_161___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_161__RX_DCOC_RES_Q_161___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_161___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_161___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_162 (0x005F4288) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_162___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_162___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_162__RX_DCOC_RANGE_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_162__RX_DCOC_RES_I_162___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_162__RX_DCOC_RES_Q_162___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_162__RX_DCOC_RANGE_162___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_162__RX_DCOC_RANGE_162___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_162__RX_DCOC_RES_I_162___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_162__RX_DCOC_RES_I_162___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_162__RX_DCOC_RES_Q_162___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_162__RX_DCOC_RES_Q_162___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_162___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_162___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_163 (0x005F428C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_163___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_163___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_163__RX_DCOC_RANGE_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_163__RX_DCOC_RES_I_163___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_163__RX_DCOC_RES_Q_163___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_163__RX_DCOC_RANGE_163___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_163__RX_DCOC_RANGE_163___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_163__RX_DCOC_RES_I_163___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_163__RX_DCOC_RES_I_163___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_163__RX_DCOC_RES_Q_163___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_163__RX_DCOC_RES_Q_163___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_163___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_163___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_164 (0x005F4290) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_164___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_164___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_164__RX_DCOC_RANGE_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_164__RX_DCOC_RES_I_164___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_164__RX_DCOC_RES_Q_164___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_164__RX_DCOC_RANGE_164___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_164__RX_DCOC_RANGE_164___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_164__RX_DCOC_RES_I_164___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_164__RX_DCOC_RES_I_164___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_164__RX_DCOC_RES_Q_164___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_164__RX_DCOC_RES_Q_164___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_164___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_164___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_165 (0x005F4294) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_165___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_165___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_165__RX_DCOC_RANGE_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_165__RX_DCOC_RES_I_165___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_165__RX_DCOC_RES_Q_165___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_165__RX_DCOC_RANGE_165___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_165__RX_DCOC_RANGE_165___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_165__RX_DCOC_RES_I_165___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_165__RX_DCOC_RES_I_165___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_165__RX_DCOC_RES_Q_165___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_165__RX_DCOC_RES_Q_165___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_165___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_165___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_166 (0x005F4298) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_166___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_166___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_166__RX_DCOC_RANGE_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_166__RX_DCOC_RES_I_166___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_166__RX_DCOC_RES_Q_166___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_166__RX_DCOC_RANGE_166___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_166__RX_DCOC_RANGE_166___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_166__RX_DCOC_RES_I_166___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_166__RX_DCOC_RES_I_166___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_166__RX_DCOC_RES_Q_166___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_166__RX_DCOC_RES_Q_166___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_166___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_166___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_167 (0x005F429C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_167___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_167___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_167__RX_DCOC_RANGE_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_167__RX_DCOC_RES_I_167___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_167__RX_DCOC_RES_Q_167___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_167__RX_DCOC_RANGE_167___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_167__RX_DCOC_RANGE_167___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_167__RX_DCOC_RES_I_167___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_167__RX_DCOC_RES_I_167___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_167__RX_DCOC_RES_Q_167___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_167__RX_DCOC_RES_Q_167___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_167___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_167___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_168 (0x005F42A0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_168___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_168___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_168__RX_DCOC_RANGE_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_168__RX_DCOC_RES_I_168___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_168__RX_DCOC_RES_Q_168___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_168__RX_DCOC_RANGE_168___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_168__RX_DCOC_RANGE_168___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_168__RX_DCOC_RES_I_168___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_168__RX_DCOC_RES_I_168___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_168__RX_DCOC_RES_Q_168___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_168__RX_DCOC_RES_Q_168___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_168___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_168___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_169 (0x005F42A4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_169___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_169___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_169__RX_DCOC_RANGE_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_169__RX_DCOC_RES_I_169___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_169__RX_DCOC_RES_Q_169___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_169__RX_DCOC_RANGE_169___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_169__RX_DCOC_RANGE_169___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_169__RX_DCOC_RES_I_169___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_169__RX_DCOC_RES_I_169___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_169__RX_DCOC_RES_Q_169___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_169__RX_DCOC_RES_Q_169___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_169___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_169___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_170 (0x005F42A8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_170___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_170___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_170__RX_DCOC_RANGE_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_170__RX_DCOC_RES_I_170___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_170__RX_DCOC_RES_Q_170___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_170__RX_DCOC_RANGE_170___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_170__RX_DCOC_RANGE_170___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_170__RX_DCOC_RES_I_170___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_170__RX_DCOC_RES_I_170___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_170__RX_DCOC_RES_Q_170___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_170__RX_DCOC_RES_Q_170___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_170___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_170___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_171 (0x005F42AC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_171___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_171___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_171__RX_DCOC_RANGE_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_171__RX_DCOC_RES_I_171___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_171__RX_DCOC_RES_Q_171___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_171__RX_DCOC_RANGE_171___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_171__RX_DCOC_RANGE_171___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_171__RX_DCOC_RES_I_171___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_171__RX_DCOC_RES_I_171___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_171__RX_DCOC_RES_Q_171___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_171__RX_DCOC_RES_Q_171___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_171___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_171___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_172 (0x005F42B0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_172___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_172___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_172__RX_DCOC_RANGE_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_172__RX_DCOC_RES_I_172___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_172__RX_DCOC_RES_Q_172___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_172__RX_DCOC_RANGE_172___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_172__RX_DCOC_RANGE_172___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_172__RX_DCOC_RES_I_172___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_172__RX_DCOC_RES_I_172___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_172__RX_DCOC_RES_Q_172___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_172__RX_DCOC_RES_Q_172___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_172___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_172___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_173 (0x005F42B4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_173___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_173___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_173__RX_DCOC_RANGE_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_173__RX_DCOC_RES_I_173___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_173__RX_DCOC_RES_Q_173___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_173__RX_DCOC_RANGE_173___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_173__RX_DCOC_RANGE_173___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_173__RX_DCOC_RES_I_173___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_173__RX_DCOC_RES_I_173___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_173__RX_DCOC_RES_Q_173___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_173__RX_DCOC_RES_Q_173___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_173___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_173___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_174 (0x005F42B8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_174___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_174___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_174__RX_DCOC_RANGE_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_174__RX_DCOC_RES_I_174___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_174__RX_DCOC_RES_Q_174___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_174__RX_DCOC_RANGE_174___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_174__RX_DCOC_RANGE_174___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_174__RX_DCOC_RES_I_174___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_174__RX_DCOC_RES_I_174___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_174__RX_DCOC_RES_Q_174___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_174__RX_DCOC_RES_Q_174___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_174___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_174___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_175 (0x005F42BC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_175___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_175___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_175__RX_DCOC_RANGE_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_175__RX_DCOC_RES_I_175___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_175__RX_DCOC_RES_Q_175___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_175__RX_DCOC_RANGE_175___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_175__RX_DCOC_RANGE_175___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_175__RX_DCOC_RES_I_175___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_175__RX_DCOC_RES_I_175___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_175__RX_DCOC_RES_Q_175___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_175__RX_DCOC_RES_Q_175___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_175___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_175___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_176 (0x005F42C0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_176___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_176___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_176__RX_DCOC_RANGE_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_176__RX_DCOC_RES_I_176___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_176__RX_DCOC_RES_Q_176___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_176__RX_DCOC_RANGE_176___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_176__RX_DCOC_RANGE_176___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_176__RX_DCOC_RES_I_176___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_176__RX_DCOC_RES_I_176___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_176__RX_DCOC_RES_Q_176___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_176__RX_DCOC_RES_Q_176___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_176___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_176___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_177 (0x005F42C4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_177___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_177___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_177__RX_DCOC_RANGE_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_177__RX_DCOC_RES_I_177___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_177__RX_DCOC_RES_Q_177___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_177__RX_DCOC_RANGE_177___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_177__RX_DCOC_RANGE_177___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_177__RX_DCOC_RES_I_177___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_177__RX_DCOC_RES_I_177___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_177__RX_DCOC_RES_Q_177___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_177__RX_DCOC_RES_Q_177___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_177___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_177___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_178 (0x005F42C8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_178___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_178___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_178__RX_DCOC_RANGE_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_178__RX_DCOC_RES_I_178___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_178__RX_DCOC_RES_Q_178___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_178__RX_DCOC_RANGE_178___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_178__RX_DCOC_RANGE_178___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_178__RX_DCOC_RES_I_178___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_178__RX_DCOC_RES_I_178___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_178__RX_DCOC_RES_Q_178___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_178__RX_DCOC_RES_Q_178___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_178___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_178___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_179 (0x005F42CC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_179___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_179___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_179__RX_DCOC_RANGE_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_179__RX_DCOC_RES_I_179___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_179__RX_DCOC_RES_Q_179___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_179__RX_DCOC_RANGE_179___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_179__RX_DCOC_RANGE_179___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_179__RX_DCOC_RES_I_179___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_179__RX_DCOC_RES_I_179___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_179__RX_DCOC_RES_Q_179___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_179__RX_DCOC_RES_Q_179___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_179___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_179___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_180 (0x005F42D0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_180___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_180___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_180__RX_DCOC_RANGE_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_180__RX_DCOC_RES_I_180___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_180__RX_DCOC_RES_Q_180___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_180__RX_DCOC_RANGE_180___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_180__RX_DCOC_RANGE_180___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_180__RX_DCOC_RES_I_180___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_180__RX_DCOC_RES_I_180___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_180__RX_DCOC_RES_Q_180___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_180__RX_DCOC_RES_Q_180___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_180___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_180___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_181 (0x005F42D4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_181___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_181___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_181__RX_DCOC_RANGE_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_181__RX_DCOC_RES_I_181___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_181__RX_DCOC_RES_Q_181___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_181__RX_DCOC_RANGE_181___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_181__RX_DCOC_RANGE_181___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_181__RX_DCOC_RES_I_181___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_181__RX_DCOC_RES_I_181___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_181__RX_DCOC_RES_Q_181___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_181__RX_DCOC_RES_Q_181___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_181___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_181___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_182 (0x005F42D8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_182___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_182___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_182__RX_DCOC_RANGE_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_182__RX_DCOC_RES_I_182___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_182__RX_DCOC_RES_Q_182___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_182__RX_DCOC_RANGE_182___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_182__RX_DCOC_RANGE_182___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_182__RX_DCOC_RES_I_182___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_182__RX_DCOC_RES_I_182___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_182__RX_DCOC_RES_Q_182___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_182__RX_DCOC_RES_Q_182___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_182___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_182___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_183 (0x005F42DC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_183___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_183___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_183__RX_DCOC_RANGE_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_183__RX_DCOC_RES_I_183___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_183__RX_DCOC_RES_Q_183___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_183__RX_DCOC_RANGE_183___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_183__RX_DCOC_RANGE_183___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_183__RX_DCOC_RES_I_183___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_183__RX_DCOC_RES_I_183___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_183__RX_DCOC_RES_Q_183___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_183__RX_DCOC_RES_Q_183___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_183___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_183___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_184 (0x005F42E0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_184___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_184___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_184__RX_DCOC_RANGE_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_184__RX_DCOC_RES_I_184___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_184__RX_DCOC_RES_Q_184___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_184__RX_DCOC_RANGE_184___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_184__RX_DCOC_RANGE_184___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_184__RX_DCOC_RES_I_184___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_184__RX_DCOC_RES_I_184___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_184__RX_DCOC_RES_Q_184___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_184__RX_DCOC_RES_Q_184___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_184___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_184___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_185 (0x005F42E4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_185___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_185___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_185__RX_DCOC_RANGE_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_185__RX_DCOC_RES_I_185___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_185__RX_DCOC_RES_Q_185___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_185__RX_DCOC_RANGE_185___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_185__RX_DCOC_RANGE_185___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_185__RX_DCOC_RES_I_185___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_185__RX_DCOC_RES_I_185___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_185__RX_DCOC_RES_Q_185___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_185__RX_DCOC_RES_Q_185___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_185___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_185___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_186 (0x005F42E8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_186___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_186___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_186__RX_DCOC_RANGE_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_186__RX_DCOC_RES_I_186___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_186__RX_DCOC_RES_Q_186___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_186__RX_DCOC_RANGE_186___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_186__RX_DCOC_RANGE_186___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_186__RX_DCOC_RES_I_186___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_186__RX_DCOC_RES_I_186___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_186__RX_DCOC_RES_Q_186___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_186__RX_DCOC_RES_Q_186___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_186___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_186___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_187 (0x005F42EC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_187___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_187___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_187__RX_DCOC_RANGE_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_187__RX_DCOC_RES_I_187___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_187__RX_DCOC_RES_Q_187___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_187__RX_DCOC_RANGE_187___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_187__RX_DCOC_RANGE_187___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_187__RX_DCOC_RES_I_187___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_187__RX_DCOC_RES_I_187___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_187__RX_DCOC_RES_Q_187___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_187__RX_DCOC_RES_Q_187___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_187___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_187___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_188 (0x005F42F0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_188___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_188___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_188__RX_DCOC_RANGE_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_188__RX_DCOC_RES_I_188___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_188__RX_DCOC_RES_Q_188___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_188__RX_DCOC_RANGE_188___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_188__RX_DCOC_RANGE_188___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_188__RX_DCOC_RES_I_188___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_188__RX_DCOC_RES_I_188___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_188__RX_DCOC_RES_Q_188___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_188__RX_DCOC_RES_Q_188___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_188___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_188___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_189 (0x005F42F4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_189___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_189___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_189__RX_DCOC_RANGE_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_189__RX_DCOC_RES_I_189___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_189__RX_DCOC_RES_Q_189___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_189__RX_DCOC_RANGE_189___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_189__RX_DCOC_RANGE_189___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_189__RX_DCOC_RES_I_189___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_189__RX_DCOC_RES_I_189___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_189__RX_DCOC_RES_Q_189___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_189__RX_DCOC_RES_Q_189___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_189___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_189___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_190 (0x005F42F8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_190___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_190___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_190__RX_DCOC_RANGE_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_190__RX_DCOC_RES_I_190___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_190__RX_DCOC_RES_Q_190___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_190__RX_DCOC_RANGE_190___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_190__RX_DCOC_RANGE_190___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_190__RX_DCOC_RES_I_190___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_190__RX_DCOC_RES_I_190___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_190__RX_DCOC_RES_Q_190___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_190__RX_DCOC_RES_Q_190___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_190___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_190___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_191 (0x005F42FC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_191___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_191___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_191__RX_DCOC_RANGE_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_191__RX_DCOC_RES_I_191___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_191__RX_DCOC_RES_Q_191___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_191__RX_DCOC_RANGE_191___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_191__RX_DCOC_RANGE_191___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_191__RX_DCOC_RES_I_191___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_191__RX_DCOC_RES_I_191___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_191__RX_DCOC_RES_Q_191___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_191__RX_DCOC_RES_Q_191___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_191___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_191___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_192 (0x005F4300) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_192___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_192___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_192__RX_DCOC_RANGE_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_192__RX_DCOC_RES_I_192___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_192__RX_DCOC_RES_Q_192___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_192__RX_DCOC_RANGE_192___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_192__RX_DCOC_RANGE_192___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_192__RX_DCOC_RES_I_192___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_192__RX_DCOC_RES_I_192___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_192__RX_DCOC_RES_Q_192___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_192__RX_DCOC_RES_Q_192___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_192___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_192___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_193 (0x005F4304) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_193___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_193___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_193__RX_DCOC_RANGE_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_193__RX_DCOC_RES_I_193___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_193__RX_DCOC_RES_Q_193___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_193__RX_DCOC_RANGE_193___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_193__RX_DCOC_RANGE_193___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_193__RX_DCOC_RES_I_193___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_193__RX_DCOC_RES_I_193___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_193__RX_DCOC_RES_Q_193___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_193__RX_DCOC_RES_Q_193___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_193___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_193___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_194 (0x005F4308) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_194___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_194___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_194__RX_DCOC_RANGE_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_194__RX_DCOC_RES_I_194___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_194__RX_DCOC_RES_Q_194___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_194__RX_DCOC_RANGE_194___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_194__RX_DCOC_RANGE_194___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_194__RX_DCOC_RES_I_194___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_194__RX_DCOC_RES_I_194___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_194__RX_DCOC_RES_Q_194___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_194__RX_DCOC_RES_Q_194___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_194___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_194___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_195 (0x005F430C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_195___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_195___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_195__RX_DCOC_RANGE_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_195__RX_DCOC_RES_I_195___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_195__RX_DCOC_RES_Q_195___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_195__RX_DCOC_RANGE_195___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_195__RX_DCOC_RANGE_195___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_195__RX_DCOC_RES_I_195___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_195__RX_DCOC_RES_I_195___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_195__RX_DCOC_RES_Q_195___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_195__RX_DCOC_RES_Q_195___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_195___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_195___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_196 (0x005F4310) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_196___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_196___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_196__RX_DCOC_RANGE_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_196__RX_DCOC_RES_I_196___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_196__RX_DCOC_RES_Q_196___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_196__RX_DCOC_RANGE_196___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_196__RX_DCOC_RANGE_196___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_196__RX_DCOC_RES_I_196___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_196__RX_DCOC_RES_I_196___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_196__RX_DCOC_RES_Q_196___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_196__RX_DCOC_RES_Q_196___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_196___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_196___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_197 (0x005F4314) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_197___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_197___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_197__RX_DCOC_RANGE_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_197__RX_DCOC_RES_I_197___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_197__RX_DCOC_RES_Q_197___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_197__RX_DCOC_RANGE_197___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_197__RX_DCOC_RANGE_197___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_197__RX_DCOC_RES_I_197___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_197__RX_DCOC_RES_I_197___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_197__RX_DCOC_RES_Q_197___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_197__RX_DCOC_RES_Q_197___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_197___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_197___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_198 (0x005F4318) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_198___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_198___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_198__RX_DCOC_RANGE_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_198__RX_DCOC_RES_I_198___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_198__RX_DCOC_RES_Q_198___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_198__RX_DCOC_RANGE_198___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_198__RX_DCOC_RANGE_198___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_198__RX_DCOC_RES_I_198___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_198__RX_DCOC_RES_I_198___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_198__RX_DCOC_RES_Q_198___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_198__RX_DCOC_RES_Q_198___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_198___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_198___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_199 (0x005F431C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_199___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_199___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_199__RX_DCOC_RANGE_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_199__RX_DCOC_RES_I_199___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_199__RX_DCOC_RES_Q_199___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_199__RX_DCOC_RANGE_199___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_199__RX_DCOC_RANGE_199___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_199__RX_DCOC_RES_I_199___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_199__RX_DCOC_RES_I_199___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_199__RX_DCOC_RES_Q_199___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_199__RX_DCOC_RES_Q_199___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_199___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_199___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_200 (0x005F4320) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_200___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_200___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_200__RX_DCOC_RANGE_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_200__RX_DCOC_RES_I_200___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_200__RX_DCOC_RES_Q_200___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_200__RX_DCOC_RANGE_200___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_200__RX_DCOC_RANGE_200___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_200__RX_DCOC_RES_I_200___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_200__RX_DCOC_RES_I_200___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_200__RX_DCOC_RES_Q_200___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_200__RX_DCOC_RES_Q_200___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_200___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_200___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_201 (0x005F4324) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_201___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_201___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_201__RX_DCOC_RANGE_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_201__RX_DCOC_RES_I_201___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_201__RX_DCOC_RES_Q_201___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_201__RX_DCOC_RANGE_201___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_201__RX_DCOC_RANGE_201___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_201__RX_DCOC_RES_I_201___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_201__RX_DCOC_RES_I_201___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_201__RX_DCOC_RES_Q_201___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_201__RX_DCOC_RES_Q_201___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_201___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_201___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_202 (0x005F4328) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_202___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_202___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_202__RX_DCOC_RANGE_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_202__RX_DCOC_RES_I_202___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_202__RX_DCOC_RES_Q_202___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_202__RX_DCOC_RANGE_202___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_202__RX_DCOC_RANGE_202___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_202__RX_DCOC_RES_I_202___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_202__RX_DCOC_RES_I_202___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_202__RX_DCOC_RES_Q_202___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_202__RX_DCOC_RES_Q_202___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_202___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_202___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_203 (0x005F432C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_203___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_203___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_203__RX_DCOC_RANGE_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_203__RX_DCOC_RES_I_203___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_203__RX_DCOC_RES_Q_203___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_203__RX_DCOC_RANGE_203___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_203__RX_DCOC_RANGE_203___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_203__RX_DCOC_RES_I_203___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_203__RX_DCOC_RES_I_203___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_203__RX_DCOC_RES_Q_203___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_203__RX_DCOC_RES_Q_203___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_203___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_203___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_204 (0x005F4330) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_204___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_204___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_204__RX_DCOC_RANGE_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_204__RX_DCOC_RES_I_204___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_204__RX_DCOC_RES_Q_204___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_204__RX_DCOC_RANGE_204___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_204__RX_DCOC_RANGE_204___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_204__RX_DCOC_RES_I_204___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_204__RX_DCOC_RES_I_204___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_204__RX_DCOC_RES_Q_204___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_204__RX_DCOC_RES_Q_204___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_204___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_204___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_205 (0x005F4334) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_205___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_205___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_205__RX_DCOC_RANGE_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_205__RX_DCOC_RES_I_205___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_205__RX_DCOC_RES_Q_205___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_205__RX_DCOC_RANGE_205___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_205__RX_DCOC_RANGE_205___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_205__RX_DCOC_RES_I_205___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_205__RX_DCOC_RES_I_205___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_205__RX_DCOC_RES_Q_205___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_205__RX_DCOC_RES_Q_205___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_205___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_205___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_206 (0x005F4338) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_206___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_206___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_206__RX_DCOC_RANGE_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_206__RX_DCOC_RES_I_206___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_206__RX_DCOC_RES_Q_206___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_206__RX_DCOC_RANGE_206___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_206__RX_DCOC_RANGE_206___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_206__RX_DCOC_RES_I_206___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_206__RX_DCOC_RES_I_206___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_206__RX_DCOC_RES_Q_206___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_206__RX_DCOC_RES_Q_206___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_206___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_206___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_207 (0x005F433C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_207___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_207___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_207__RX_DCOC_RANGE_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_207__RX_DCOC_RES_I_207___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_207__RX_DCOC_RES_Q_207___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_207__RX_DCOC_RANGE_207___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_207__RX_DCOC_RANGE_207___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_207__RX_DCOC_RES_I_207___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_207__RX_DCOC_RES_I_207___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_207__RX_DCOC_RES_Q_207___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_207__RX_DCOC_RES_Q_207___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_207___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_207___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_208 (0x005F4340) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_208___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_208___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_208__RX_DCOC_RANGE_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_208__RX_DCOC_RES_I_208___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_208__RX_DCOC_RES_Q_208___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_208__RX_DCOC_RANGE_208___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_208__RX_DCOC_RANGE_208___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_208__RX_DCOC_RES_I_208___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_208__RX_DCOC_RES_I_208___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_208__RX_DCOC_RES_Q_208___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_208__RX_DCOC_RES_Q_208___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_208___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_208___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_209 (0x005F4344) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_209___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_209___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_209__RX_DCOC_RANGE_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_209__RX_DCOC_RES_I_209___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_209__RX_DCOC_RES_Q_209___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_209__RX_DCOC_RANGE_209___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_209__RX_DCOC_RANGE_209___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_209__RX_DCOC_RES_I_209___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_209__RX_DCOC_RES_I_209___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_209__RX_DCOC_RES_Q_209___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_209__RX_DCOC_RES_Q_209___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_209___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_209___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_210 (0x005F4348) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_210___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_210___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_210__RX_DCOC_RANGE_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_210__RX_DCOC_RES_I_210___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_210__RX_DCOC_RES_Q_210___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_210__RX_DCOC_RANGE_210___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_210__RX_DCOC_RANGE_210___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_210__RX_DCOC_RES_I_210___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_210__RX_DCOC_RES_I_210___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_210__RX_DCOC_RES_Q_210___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_210__RX_DCOC_RES_Q_210___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_210___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_210___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_211 (0x005F434C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_211___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_211___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_211__RX_DCOC_RANGE_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_211__RX_DCOC_RES_I_211___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_211__RX_DCOC_RES_Q_211___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_211__RX_DCOC_RANGE_211___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_211__RX_DCOC_RANGE_211___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_211__RX_DCOC_RES_I_211___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_211__RX_DCOC_RES_I_211___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_211__RX_DCOC_RES_Q_211___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_211__RX_DCOC_RES_Q_211___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_211___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_211___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_212 (0x005F4350) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_212___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_212___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_212__RX_DCOC_RANGE_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_212__RX_DCOC_RES_I_212___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_212__RX_DCOC_RES_Q_212___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_212__RX_DCOC_RANGE_212___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_212__RX_DCOC_RANGE_212___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_212__RX_DCOC_RES_I_212___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_212__RX_DCOC_RES_I_212___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_212__RX_DCOC_RES_Q_212___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_212__RX_DCOC_RES_Q_212___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_212___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_212___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_213 (0x005F4354) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_213___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_213___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_213__RX_DCOC_RANGE_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_213__RX_DCOC_RES_I_213___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_213__RX_DCOC_RES_Q_213___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_213__RX_DCOC_RANGE_213___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_213__RX_DCOC_RANGE_213___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_213__RX_DCOC_RES_I_213___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_213__RX_DCOC_RES_I_213___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_213__RX_DCOC_RES_Q_213___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_213__RX_DCOC_RES_Q_213___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_213___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_213___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_214 (0x005F4358) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_214___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_214___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_214__RX_DCOC_RANGE_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_214__RX_DCOC_RES_I_214___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_214__RX_DCOC_RES_Q_214___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_214__RX_DCOC_RANGE_214___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_214__RX_DCOC_RANGE_214___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_214__RX_DCOC_RES_I_214___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_214__RX_DCOC_RES_I_214___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_214__RX_DCOC_RES_Q_214___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_214__RX_DCOC_RES_Q_214___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_214___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_214___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_215 (0x005F435C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_215___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_215___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_215__RX_DCOC_RANGE_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_215__RX_DCOC_RES_I_215___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_215__RX_DCOC_RES_Q_215___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_215__RX_DCOC_RANGE_215___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_215__RX_DCOC_RANGE_215___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_215__RX_DCOC_RES_I_215___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_215__RX_DCOC_RES_I_215___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_215__RX_DCOC_RES_Q_215___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_215__RX_DCOC_RES_Q_215___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_215___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_215___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_216 (0x005F4360) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_216___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_216___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_216__RX_DCOC_RANGE_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_216__RX_DCOC_RES_I_216___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_216__RX_DCOC_RES_Q_216___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_216__RX_DCOC_RANGE_216___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_216__RX_DCOC_RANGE_216___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_216__RX_DCOC_RES_I_216___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_216__RX_DCOC_RES_I_216___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_216__RX_DCOC_RES_Q_216___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_216__RX_DCOC_RES_Q_216___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_216___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_216___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_217 (0x005F4364) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_217___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_217___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_217__RX_DCOC_RANGE_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_217__RX_DCOC_RES_I_217___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_217__RX_DCOC_RES_Q_217___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_217__RX_DCOC_RANGE_217___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_217__RX_DCOC_RANGE_217___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_217__RX_DCOC_RES_I_217___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_217__RX_DCOC_RES_I_217___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_217__RX_DCOC_RES_Q_217___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_217__RX_DCOC_RES_Q_217___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_217___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_217___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_218 (0x005F4368) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_218___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_218___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_218__RX_DCOC_RANGE_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_218__RX_DCOC_RES_I_218___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_218__RX_DCOC_RES_Q_218___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_218__RX_DCOC_RANGE_218___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_218__RX_DCOC_RANGE_218___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_218__RX_DCOC_RES_I_218___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_218__RX_DCOC_RES_I_218___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_218__RX_DCOC_RES_Q_218___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_218__RX_DCOC_RES_Q_218___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_218___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_218___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_219 (0x005F436C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_219___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_219___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_219__RX_DCOC_RANGE_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_219__RX_DCOC_RES_I_219___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_219__RX_DCOC_RES_Q_219___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_219__RX_DCOC_RANGE_219___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_219__RX_DCOC_RANGE_219___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_219__RX_DCOC_RES_I_219___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_219__RX_DCOC_RES_I_219___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_219__RX_DCOC_RES_Q_219___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_219__RX_DCOC_RES_Q_219___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_219___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_219___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_220 (0x005F4370) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_220___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_220___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_220__RX_DCOC_RANGE_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_220__RX_DCOC_RES_I_220___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_220__RX_DCOC_RES_Q_220___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_220__RX_DCOC_RANGE_220___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_220__RX_DCOC_RANGE_220___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_220__RX_DCOC_RES_I_220___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_220__RX_DCOC_RES_I_220___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_220__RX_DCOC_RES_Q_220___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_220__RX_DCOC_RES_Q_220___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_220___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_220___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_221 (0x005F4374) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_221___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_221___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_221__RX_DCOC_RANGE_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_221__RX_DCOC_RES_I_221___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_221__RX_DCOC_RES_Q_221___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_221__RX_DCOC_RANGE_221___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_221__RX_DCOC_RANGE_221___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_221__RX_DCOC_RES_I_221___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_221__RX_DCOC_RES_I_221___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_221__RX_DCOC_RES_Q_221___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_221__RX_DCOC_RES_Q_221___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_221___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_221___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_222 (0x005F4378) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_222___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_222___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_222__RX_DCOC_RANGE_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_222__RX_DCOC_RES_I_222___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_222__RX_DCOC_RES_Q_222___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_222__RX_DCOC_RANGE_222___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_222__RX_DCOC_RANGE_222___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_222__RX_DCOC_RES_I_222___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_222__RX_DCOC_RES_I_222___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_222__RX_DCOC_RES_Q_222___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_222__RX_DCOC_RES_Q_222___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_222___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_222___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_223 (0x005F437C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_223___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_223___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_223__RX_DCOC_RANGE_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_223__RX_DCOC_RES_I_223___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_223__RX_DCOC_RES_Q_223___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_223__RX_DCOC_RANGE_223___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_223__RX_DCOC_RANGE_223___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_223__RX_DCOC_RES_I_223___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_223__RX_DCOC_RES_I_223___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_223__RX_DCOC_RES_Q_223___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_223__RX_DCOC_RES_Q_223___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_223___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_223___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_224 (0x005F4380) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_224___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_224___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_224__RX_DCOC_RANGE_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_224__RX_DCOC_RES_I_224___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_224__RX_DCOC_RES_Q_224___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_224__RX_DCOC_RANGE_224___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_224__RX_DCOC_RANGE_224___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_224__RX_DCOC_RES_I_224___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_224__RX_DCOC_RES_I_224___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_224__RX_DCOC_RES_Q_224___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_224__RX_DCOC_RES_Q_224___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_224___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_224___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_225 (0x005F4384) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_225___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_225___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_225__RX_DCOC_RANGE_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_225__RX_DCOC_RES_I_225___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_225__RX_DCOC_RES_Q_225___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_225__RX_DCOC_RANGE_225___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_225__RX_DCOC_RANGE_225___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_225__RX_DCOC_RES_I_225___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_225__RX_DCOC_RES_I_225___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_225__RX_DCOC_RES_Q_225___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_225__RX_DCOC_RES_Q_225___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_225___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_225___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_226 (0x005F4388) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_226___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_226___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_226__RX_DCOC_RANGE_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_226__RX_DCOC_RES_I_226___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_226__RX_DCOC_RES_Q_226___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_226__RX_DCOC_RANGE_226___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_226__RX_DCOC_RANGE_226___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_226__RX_DCOC_RES_I_226___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_226__RX_DCOC_RES_I_226___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_226__RX_DCOC_RES_Q_226___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_226__RX_DCOC_RES_Q_226___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_226___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_226___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_227 (0x005F438C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_227___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_227___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_227__RX_DCOC_RANGE_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_227__RX_DCOC_RES_I_227___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_227__RX_DCOC_RES_Q_227___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_227__RX_DCOC_RANGE_227___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_227__RX_DCOC_RANGE_227___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_227__RX_DCOC_RES_I_227___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_227__RX_DCOC_RES_I_227___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_227__RX_DCOC_RES_Q_227___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_227__RX_DCOC_RES_Q_227___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_227___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_227___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_228 (0x005F4390) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_228___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_228___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_228__RX_DCOC_RANGE_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_228__RX_DCOC_RES_I_228___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_228__RX_DCOC_RES_Q_228___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_228__RX_DCOC_RANGE_228___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_228__RX_DCOC_RANGE_228___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_228__RX_DCOC_RES_I_228___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_228__RX_DCOC_RES_I_228___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_228__RX_DCOC_RES_Q_228___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_228__RX_DCOC_RES_Q_228___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_228___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_228___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_229 (0x005F4394) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_229___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_229___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_229__RX_DCOC_RANGE_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_229__RX_DCOC_RES_I_229___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_229__RX_DCOC_RES_Q_229___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_229__RX_DCOC_RANGE_229___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_229__RX_DCOC_RANGE_229___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_229__RX_DCOC_RES_I_229___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_229__RX_DCOC_RES_I_229___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_229__RX_DCOC_RES_Q_229___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_229__RX_DCOC_RES_Q_229___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_229___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_229___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_230 (0x005F4398) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_230___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_230___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_230__RX_DCOC_RANGE_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_230__RX_DCOC_RES_I_230___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_230__RX_DCOC_RES_Q_230___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_230__RX_DCOC_RANGE_230___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_230__RX_DCOC_RANGE_230___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_230__RX_DCOC_RES_I_230___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_230__RX_DCOC_RES_I_230___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_230__RX_DCOC_RES_Q_230___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_230__RX_DCOC_RES_Q_230___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_230___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_230___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_231 (0x005F439C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_231___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_231___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_231__RX_DCOC_RANGE_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_231__RX_DCOC_RES_I_231___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_231__RX_DCOC_RES_Q_231___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_231__RX_DCOC_RANGE_231___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_231__RX_DCOC_RANGE_231___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_231__RX_DCOC_RES_I_231___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_231__RX_DCOC_RES_I_231___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_231__RX_DCOC_RES_Q_231___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_231__RX_DCOC_RES_Q_231___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_231___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_231___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_232 (0x005F43A0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_232___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_232___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_232__RX_DCOC_RANGE_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_232__RX_DCOC_RES_I_232___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_232__RX_DCOC_RES_Q_232___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_232__RX_DCOC_RANGE_232___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_232__RX_DCOC_RANGE_232___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_232__RX_DCOC_RES_I_232___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_232__RX_DCOC_RES_I_232___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_232__RX_DCOC_RES_Q_232___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_232__RX_DCOC_RES_Q_232___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_232___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_232___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_233 (0x005F43A4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_233___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_233___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_233__RX_DCOC_RANGE_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_233__RX_DCOC_RES_I_233___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_233__RX_DCOC_RES_Q_233___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_233__RX_DCOC_RANGE_233___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_233__RX_DCOC_RANGE_233___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_233__RX_DCOC_RES_I_233___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_233__RX_DCOC_RES_I_233___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_233__RX_DCOC_RES_Q_233___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_233__RX_DCOC_RES_Q_233___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_233___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_233___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_234 (0x005F43A8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_234___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_234___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_234__RX_DCOC_RANGE_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_234__RX_DCOC_RES_I_234___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_234__RX_DCOC_RES_Q_234___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_234__RX_DCOC_RANGE_234___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_234__RX_DCOC_RANGE_234___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_234__RX_DCOC_RES_I_234___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_234__RX_DCOC_RES_I_234___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_234__RX_DCOC_RES_Q_234___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_234__RX_DCOC_RES_Q_234___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_234___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_234___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_235 (0x005F43AC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_235___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_235___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_235__RX_DCOC_RANGE_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_235__RX_DCOC_RES_I_235___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_235__RX_DCOC_RES_Q_235___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_235__RX_DCOC_RANGE_235___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_235__RX_DCOC_RANGE_235___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_235__RX_DCOC_RES_I_235___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_235__RX_DCOC_RES_I_235___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_235__RX_DCOC_RES_Q_235___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_235__RX_DCOC_RES_Q_235___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_235___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_235___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_236 (0x005F43B0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_236___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_236___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_236__RX_DCOC_RANGE_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_236__RX_DCOC_RES_I_236___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_236__RX_DCOC_RES_Q_236___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_236__RX_DCOC_RANGE_236___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_236__RX_DCOC_RANGE_236___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_236__RX_DCOC_RES_I_236___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_236__RX_DCOC_RES_I_236___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_236__RX_DCOC_RES_Q_236___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_236__RX_DCOC_RES_Q_236___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_236___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_236___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_237 (0x005F43B4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_237___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_237___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_237__RX_DCOC_RANGE_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_237__RX_DCOC_RES_I_237___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_237__RX_DCOC_RES_Q_237___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_237__RX_DCOC_RANGE_237___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_237__RX_DCOC_RANGE_237___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_237__RX_DCOC_RES_I_237___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_237__RX_DCOC_RES_I_237___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_237__RX_DCOC_RES_Q_237___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_237__RX_DCOC_RES_Q_237___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_237___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_237___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_238 (0x005F43B8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_238___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_238___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_238__RX_DCOC_RANGE_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_238__RX_DCOC_RES_I_238___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_238__RX_DCOC_RES_Q_238___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_238__RX_DCOC_RANGE_238___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_238__RX_DCOC_RANGE_238___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_238__RX_DCOC_RES_I_238___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_238__RX_DCOC_RES_I_238___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_238__RX_DCOC_RES_Q_238___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_238__RX_DCOC_RES_Q_238___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_238___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_238___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_239 (0x005F43BC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_239___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_239___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_239__RX_DCOC_RANGE_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_239__RX_DCOC_RES_I_239___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_239__RX_DCOC_RES_Q_239___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_239__RX_DCOC_RANGE_239___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_239__RX_DCOC_RANGE_239___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_239__RX_DCOC_RES_I_239___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_239__RX_DCOC_RES_I_239___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_239__RX_DCOC_RES_Q_239___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_239__RX_DCOC_RES_Q_239___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_239___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_239___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_240 (0x005F43C0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_240___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_240___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_240__RX_DCOC_RANGE_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_240__RX_DCOC_RES_I_240___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_240__RX_DCOC_RES_Q_240___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_240__RX_DCOC_RANGE_240___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_240__RX_DCOC_RANGE_240___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_240__RX_DCOC_RES_I_240___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_240__RX_DCOC_RES_I_240___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_240__RX_DCOC_RES_Q_240___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_240__RX_DCOC_RES_Q_240___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_240___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_240___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_241 (0x005F43C4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_241___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_241___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_241__RX_DCOC_RANGE_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_241__RX_DCOC_RES_I_241___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_241__RX_DCOC_RES_Q_241___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_241__RX_DCOC_RANGE_241___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_241__RX_DCOC_RANGE_241___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_241__RX_DCOC_RES_I_241___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_241__RX_DCOC_RES_I_241___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_241__RX_DCOC_RES_Q_241___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_241__RX_DCOC_RES_Q_241___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_241___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_241___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_242 (0x005F43C8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_242___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_242___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_242__RX_DCOC_RANGE_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_242__RX_DCOC_RES_I_242___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_242__RX_DCOC_RES_Q_242___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_242__RX_DCOC_RANGE_242___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_242__RX_DCOC_RANGE_242___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_242__RX_DCOC_RES_I_242___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_242__RX_DCOC_RES_I_242___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_242__RX_DCOC_RES_Q_242___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_242__RX_DCOC_RES_Q_242___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_242___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_242___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_243 (0x005F43CC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_243___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_243___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_243__RX_DCOC_RANGE_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_243__RX_DCOC_RES_I_243___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_243__RX_DCOC_RES_Q_243___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_243__RX_DCOC_RANGE_243___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_243__RX_DCOC_RANGE_243___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_243__RX_DCOC_RES_I_243___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_243__RX_DCOC_RES_I_243___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_243__RX_DCOC_RES_Q_243___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_243__RX_DCOC_RES_Q_243___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_243___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_243___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_244 (0x005F43D0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_244___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_244___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_244__RX_DCOC_RANGE_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_244__RX_DCOC_RES_I_244___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_244__RX_DCOC_RES_Q_244___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_244__RX_DCOC_RANGE_244___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_244__RX_DCOC_RANGE_244___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_244__RX_DCOC_RES_I_244___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_244__RX_DCOC_RES_I_244___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_244__RX_DCOC_RES_Q_244___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_244__RX_DCOC_RES_Q_244___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_244___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_244___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_245 (0x005F43D4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_245___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_245___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_245__RX_DCOC_RANGE_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_245__RX_DCOC_RES_I_245___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_245__RX_DCOC_RES_Q_245___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_245__RX_DCOC_RANGE_245___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_245__RX_DCOC_RANGE_245___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_245__RX_DCOC_RES_I_245___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_245__RX_DCOC_RES_I_245___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_245__RX_DCOC_RES_Q_245___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_245__RX_DCOC_RES_Q_245___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_245___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_245___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_246 (0x005F43D8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_246___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_246___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_246__RX_DCOC_RANGE_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_246__RX_DCOC_RES_I_246___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_246__RX_DCOC_RES_Q_246___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_246__RX_DCOC_RANGE_246___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_246__RX_DCOC_RANGE_246___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_246__RX_DCOC_RES_I_246___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_246__RX_DCOC_RES_I_246___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_246__RX_DCOC_RES_Q_246___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_246__RX_DCOC_RES_Q_246___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_246___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_246___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_247 (0x005F43DC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_247___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_247___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_247__RX_DCOC_RANGE_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_247__RX_DCOC_RES_I_247___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_247__RX_DCOC_RES_Q_247___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_247__RX_DCOC_RANGE_247___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_247__RX_DCOC_RANGE_247___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_247__RX_DCOC_RES_I_247___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_247__RX_DCOC_RES_I_247___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_247__RX_DCOC_RES_Q_247___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_247__RX_DCOC_RES_Q_247___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_247___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_247___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_248 (0x005F43E0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_248___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_248___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_248__RX_DCOC_RANGE_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_248__RX_DCOC_RES_I_248___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_248__RX_DCOC_RES_Q_248___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_248__RX_DCOC_RANGE_248___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_248__RX_DCOC_RANGE_248___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_248__RX_DCOC_RES_I_248___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_248__RX_DCOC_RES_I_248___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_248__RX_DCOC_RES_Q_248___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_248__RX_DCOC_RES_Q_248___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_248___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_248___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_249 (0x005F43E4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_249___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_249___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_249__RX_DCOC_RANGE_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_249__RX_DCOC_RES_I_249___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_249__RX_DCOC_RES_Q_249___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_249__RX_DCOC_RANGE_249___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_249__RX_DCOC_RANGE_249___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_249__RX_DCOC_RES_I_249___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_249__RX_DCOC_RES_I_249___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_249__RX_DCOC_RES_Q_249___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_249__RX_DCOC_RES_Q_249___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_249___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_249___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_250 (0x005F43E8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_250___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_250___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_250__RX_DCOC_RANGE_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_250__RX_DCOC_RES_I_250___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_250__RX_DCOC_RES_Q_250___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_250__RX_DCOC_RANGE_250___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_250__RX_DCOC_RANGE_250___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_250__RX_DCOC_RES_I_250___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_250__RX_DCOC_RES_I_250___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_250__RX_DCOC_RES_Q_250___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_250__RX_DCOC_RES_Q_250___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_250___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_250___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_251 (0x005F43EC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_251___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_251___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_251__RX_DCOC_RANGE_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_251__RX_DCOC_RES_I_251___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_251__RX_DCOC_RES_Q_251___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_251__RX_DCOC_RANGE_251___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_251__RX_DCOC_RANGE_251___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_251__RX_DCOC_RES_I_251___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_251__RX_DCOC_RES_I_251___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_251__RX_DCOC_RES_Q_251___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_251__RX_DCOC_RES_Q_251___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_251___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_251___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_252 (0x005F43F0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_252___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_252___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_252__RX_DCOC_RANGE_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_252__RX_DCOC_RES_I_252___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_252__RX_DCOC_RES_Q_252___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_252__RX_DCOC_RANGE_252___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_252__RX_DCOC_RANGE_252___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_252__RX_DCOC_RES_I_252___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_252__RX_DCOC_RES_I_252___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_252__RX_DCOC_RES_Q_252___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_252__RX_DCOC_RES_Q_252___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_252___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_252___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_253 (0x005F43F4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_253___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_253___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_253__RX_DCOC_RANGE_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_253__RX_DCOC_RES_I_253___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_253__RX_DCOC_RES_Q_253___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_253__RX_DCOC_RANGE_253___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_253__RX_DCOC_RANGE_253___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_253__RX_DCOC_RES_I_253___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_253__RX_DCOC_RES_I_253___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_253__RX_DCOC_RES_Q_253___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_253__RX_DCOC_RES_Q_253___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_253___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_253___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_254 (0x005F43F8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_254___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_254___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_254__RX_DCOC_RANGE_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_254__RX_DCOC_RES_I_254___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_254__RX_DCOC_RES_Q_254___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_254__RX_DCOC_RANGE_254___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_254__RX_DCOC_RANGE_254___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_254__RX_DCOC_RES_I_254___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_254__RX_DCOC_RES_I_254___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_254__RX_DCOC_RES_Q_254___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_254__RX_DCOC_RES_Q_254___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_254___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_254___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_255 (0x005F43FC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_255___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_255___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_255__RX_DCOC_RANGE_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_255__RX_DCOC_RES_I_255___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_255__RX_DCOC_RES_Q_255___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_255__RX_DCOC_RANGE_255___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_255__RX_DCOC_RANGE_255___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_255__RX_DCOC_RES_I_255___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_255__RX_DCOC_RES_I_255___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_255__RX_DCOC_RES_Q_255___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_255__RX_DCOC_RES_Q_255___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_255___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_255___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_256 (0x005F4400) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_256___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_256___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_256__RX_DCOC_RANGE_256___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_256__RX_DCOC_RES_I_256___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_256__RX_DCOC_RES_Q_256___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_256__RX_DCOC_RANGE_256___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_256__RX_DCOC_RANGE_256___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_256__RX_DCOC_RES_I_256___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_256__RX_DCOC_RES_I_256___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_256__RX_DCOC_RES_Q_256___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_256__RX_DCOC_RES_Q_256___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_256___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_256___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_257 (0x005F4404) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_257___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_257___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_257__RX_DCOC_RANGE_257___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_257__RX_DCOC_RES_I_257___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_257__RX_DCOC_RES_Q_257___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_257__RX_DCOC_RANGE_257___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_257__RX_DCOC_RANGE_257___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_257__RX_DCOC_RES_I_257___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_257__RX_DCOC_RES_I_257___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_257__RX_DCOC_RES_Q_257___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_257__RX_DCOC_RES_Q_257___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_257___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_257___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_258 (0x005F4408) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_258___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_258___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_258__RX_DCOC_RANGE_258___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_258__RX_DCOC_RES_I_258___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_258__RX_DCOC_RES_Q_258___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_258__RX_DCOC_RANGE_258___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_258__RX_DCOC_RANGE_258___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_258__RX_DCOC_RES_I_258___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_258__RX_DCOC_RES_I_258___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_258__RX_DCOC_RES_Q_258___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_258__RX_DCOC_RES_Q_258___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_258___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_258___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_259 (0x005F440C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_259___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_259___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_259__RX_DCOC_RANGE_259___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_259__RX_DCOC_RES_I_259___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_259__RX_DCOC_RES_Q_259___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_259__RX_DCOC_RANGE_259___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_259__RX_DCOC_RANGE_259___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_259__RX_DCOC_RES_I_259___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_259__RX_DCOC_RES_I_259___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_259__RX_DCOC_RES_Q_259___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_259__RX_DCOC_RES_Q_259___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_259___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_259___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_260 (0x005F4410) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_260___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_260___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_260__RX_DCOC_RANGE_260___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_260__RX_DCOC_RES_I_260___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_260__RX_DCOC_RES_Q_260___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_260__RX_DCOC_RANGE_260___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_260__RX_DCOC_RANGE_260___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_260__RX_DCOC_RES_I_260___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_260__RX_DCOC_RES_I_260___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_260__RX_DCOC_RES_Q_260___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_260__RX_DCOC_RES_Q_260___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_260___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_260___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_261 (0x005F4414) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_261___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_261___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_261__RX_DCOC_RANGE_261___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_261__RX_DCOC_RES_I_261___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_261__RX_DCOC_RES_Q_261___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_261__RX_DCOC_RANGE_261___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_261__RX_DCOC_RANGE_261___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_261__RX_DCOC_RES_I_261___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_261__RX_DCOC_RES_I_261___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_261__RX_DCOC_RES_Q_261___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_261__RX_DCOC_RES_Q_261___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_261___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_261___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_262 (0x005F4418) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_262___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_262___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_262__RX_DCOC_RANGE_262___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_262__RX_DCOC_RES_I_262___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_262__RX_DCOC_RES_Q_262___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_262__RX_DCOC_RANGE_262___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_262__RX_DCOC_RANGE_262___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_262__RX_DCOC_RES_I_262___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_262__RX_DCOC_RES_I_262___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_262__RX_DCOC_RES_Q_262___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_262__RX_DCOC_RES_Q_262___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_262___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_262___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_263 (0x005F441C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_263___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_263___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_263__RX_DCOC_RANGE_263___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_263__RX_DCOC_RES_I_263___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_263__RX_DCOC_RES_Q_263___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_263__RX_DCOC_RANGE_263___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_263__RX_DCOC_RANGE_263___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_263__RX_DCOC_RES_I_263___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_263__RX_DCOC_RES_I_263___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_263__RX_DCOC_RES_Q_263___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_263__RX_DCOC_RES_Q_263___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_263___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_263___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_264 (0x005F4420) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_264___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_264___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_264__RX_DCOC_RANGE_264___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_264__RX_DCOC_RES_I_264___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_264__RX_DCOC_RES_Q_264___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_264__RX_DCOC_RANGE_264___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_264__RX_DCOC_RANGE_264___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_264__RX_DCOC_RES_I_264___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_264__RX_DCOC_RES_I_264___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_264__RX_DCOC_RES_Q_264___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_264__RX_DCOC_RES_Q_264___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_264___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_264___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_265 (0x005F4424) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_265___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_265___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_265__RX_DCOC_RANGE_265___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_265__RX_DCOC_RES_I_265___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_265__RX_DCOC_RES_Q_265___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_265__RX_DCOC_RANGE_265___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_265__RX_DCOC_RANGE_265___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_265__RX_DCOC_RES_I_265___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_265__RX_DCOC_RES_I_265___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_265__RX_DCOC_RES_Q_265___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_265__RX_DCOC_RES_Q_265___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_265___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_265___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_266 (0x005F4428) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_266___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_266___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_266__RX_DCOC_RANGE_266___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_266__RX_DCOC_RES_I_266___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_266__RX_DCOC_RES_Q_266___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_266__RX_DCOC_RANGE_266___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_266__RX_DCOC_RANGE_266___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_266__RX_DCOC_RES_I_266___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_266__RX_DCOC_RES_I_266___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_266__RX_DCOC_RES_Q_266___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_266__RX_DCOC_RES_Q_266___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_266___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_266___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_267 (0x005F442C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_267___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_267___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_267__RX_DCOC_RANGE_267___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_267__RX_DCOC_RES_I_267___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_267__RX_DCOC_RES_Q_267___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_267__RX_DCOC_RANGE_267___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_267__RX_DCOC_RANGE_267___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_267__RX_DCOC_RES_I_267___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_267__RX_DCOC_RES_I_267___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_267__RX_DCOC_RES_Q_267___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_267__RX_DCOC_RES_Q_267___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_267___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_267___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_268 (0x005F4430) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_268___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_268___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_268__RX_DCOC_RANGE_268___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_268__RX_DCOC_RES_I_268___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_268__RX_DCOC_RES_Q_268___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_268__RX_DCOC_RANGE_268___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_268__RX_DCOC_RANGE_268___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_268__RX_DCOC_RES_I_268___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_268__RX_DCOC_RES_I_268___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_268__RX_DCOC_RES_Q_268___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_268__RX_DCOC_RES_Q_268___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_268___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_268___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_269 (0x005F4434) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_269___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_269___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_269__RX_DCOC_RANGE_269___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_269__RX_DCOC_RES_I_269___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_269__RX_DCOC_RES_Q_269___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_269__RX_DCOC_RANGE_269___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_269__RX_DCOC_RANGE_269___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_269__RX_DCOC_RES_I_269___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_269__RX_DCOC_RES_I_269___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_269__RX_DCOC_RES_Q_269___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_269__RX_DCOC_RES_Q_269___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_269___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_269___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_270 (0x005F4438) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_270___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_270___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_270__RX_DCOC_RANGE_270___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_270__RX_DCOC_RES_I_270___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_270__RX_DCOC_RES_Q_270___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_270__RX_DCOC_RANGE_270___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_270__RX_DCOC_RANGE_270___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_270__RX_DCOC_RES_I_270___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_270__RX_DCOC_RES_I_270___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_270__RX_DCOC_RES_Q_270___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_270__RX_DCOC_RES_Q_270___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_270___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_270___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_271 (0x005F443C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_271___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_271___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_271__RX_DCOC_RANGE_271___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_271__RX_DCOC_RES_I_271___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_271__RX_DCOC_RES_Q_271___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_271__RX_DCOC_RANGE_271___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_271__RX_DCOC_RANGE_271___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_271__RX_DCOC_RES_I_271___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_271__RX_DCOC_RES_I_271___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_271__RX_DCOC_RES_Q_271___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_271__RX_DCOC_RES_Q_271___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_271___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_271___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_272 (0x005F4440) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_272___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_272___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_272__RX_DCOC_RANGE_272___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_272__RX_DCOC_RES_I_272___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_272__RX_DCOC_RES_Q_272___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_272__RX_DCOC_RANGE_272___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_272__RX_DCOC_RANGE_272___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_272__RX_DCOC_RES_I_272___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_272__RX_DCOC_RES_I_272___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_272__RX_DCOC_RES_Q_272___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_272__RX_DCOC_RES_Q_272___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_272___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_272___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_273 (0x005F4444) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_273___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_273___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_273__RX_DCOC_RANGE_273___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_273__RX_DCOC_RES_I_273___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_273__RX_DCOC_RES_Q_273___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_273__RX_DCOC_RANGE_273___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_273__RX_DCOC_RANGE_273___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_273__RX_DCOC_RES_I_273___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_273__RX_DCOC_RES_I_273___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_273__RX_DCOC_RES_Q_273___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_273__RX_DCOC_RES_Q_273___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_273___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_273___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_274 (0x005F4448) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_274___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_274___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_274__RX_DCOC_RANGE_274___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_274__RX_DCOC_RES_I_274___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_274__RX_DCOC_RES_Q_274___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_274__RX_DCOC_RANGE_274___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_274__RX_DCOC_RANGE_274___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_274__RX_DCOC_RES_I_274___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_274__RX_DCOC_RES_I_274___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_274__RX_DCOC_RES_Q_274___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_274__RX_DCOC_RES_Q_274___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_274___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_274___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_275 (0x005F444C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_275___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_275___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_275__RX_DCOC_RANGE_275___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_275__RX_DCOC_RES_I_275___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_275__RX_DCOC_RES_Q_275___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_275__RX_DCOC_RANGE_275___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_275__RX_DCOC_RANGE_275___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_275__RX_DCOC_RES_I_275___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_275__RX_DCOC_RES_I_275___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_275__RX_DCOC_RES_Q_275___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_275__RX_DCOC_RES_Q_275___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_275___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_275___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_276 (0x005F4450) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_276___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_276___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_276__RX_DCOC_RANGE_276___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_276__RX_DCOC_RES_I_276___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_276__RX_DCOC_RES_Q_276___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_276__RX_DCOC_RANGE_276___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_276__RX_DCOC_RANGE_276___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_276__RX_DCOC_RES_I_276___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_276__RX_DCOC_RES_I_276___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_276__RX_DCOC_RES_Q_276___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_276__RX_DCOC_RES_Q_276___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_276___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_276___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_277 (0x005F4454) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_277___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_277___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_277__RX_DCOC_RANGE_277___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_277__RX_DCOC_RES_I_277___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_277__RX_DCOC_RES_Q_277___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_277__RX_DCOC_RANGE_277___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_277__RX_DCOC_RANGE_277___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_277__RX_DCOC_RES_I_277___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_277__RX_DCOC_RES_I_277___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_277__RX_DCOC_RES_Q_277___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_277__RX_DCOC_RES_Q_277___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_277___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_277___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_278 (0x005F4458) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_278___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_278___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_278__RX_DCOC_RANGE_278___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_278__RX_DCOC_RES_I_278___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_278__RX_DCOC_RES_Q_278___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_278__RX_DCOC_RANGE_278___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_278__RX_DCOC_RANGE_278___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_278__RX_DCOC_RES_I_278___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_278__RX_DCOC_RES_I_278___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_278__RX_DCOC_RES_Q_278___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_278__RX_DCOC_RES_Q_278___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_278___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_278___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_279 (0x005F445C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_279___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_279___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_279__RX_DCOC_RANGE_279___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_279__RX_DCOC_RES_I_279___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_279__RX_DCOC_RES_Q_279___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_279__RX_DCOC_RANGE_279___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_279__RX_DCOC_RANGE_279___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_279__RX_DCOC_RES_I_279___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_279__RX_DCOC_RES_I_279___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_279__RX_DCOC_RES_Q_279___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_279__RX_DCOC_RES_Q_279___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_279___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_279___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_280 (0x005F4460) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_280___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_280___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_280__RX_DCOC_RANGE_280___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_280__RX_DCOC_RES_I_280___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_280__RX_DCOC_RES_Q_280___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_280__RX_DCOC_RANGE_280___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_280__RX_DCOC_RANGE_280___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_280__RX_DCOC_RES_I_280___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_280__RX_DCOC_RES_I_280___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_280__RX_DCOC_RES_Q_280___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_280__RX_DCOC_RES_Q_280___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_280___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_280___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_281 (0x005F4464) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_281___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_281___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_281__RX_DCOC_RANGE_281___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_281__RX_DCOC_RES_I_281___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_281__RX_DCOC_RES_Q_281___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_281__RX_DCOC_RANGE_281___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_281__RX_DCOC_RANGE_281___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_281__RX_DCOC_RES_I_281___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_281__RX_DCOC_RES_I_281___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_281__RX_DCOC_RES_Q_281___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_281__RX_DCOC_RES_Q_281___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_281___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_281___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_282 (0x005F4468) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_282___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_282___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_282__RX_DCOC_RANGE_282___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_282__RX_DCOC_RES_I_282___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_282__RX_DCOC_RES_Q_282___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_282__RX_DCOC_RANGE_282___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_282__RX_DCOC_RANGE_282___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_282__RX_DCOC_RES_I_282___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_282__RX_DCOC_RES_I_282___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_282__RX_DCOC_RES_Q_282___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_282__RX_DCOC_RES_Q_282___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_282___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_282___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_283 (0x005F446C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_283___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_283___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_283__RX_DCOC_RANGE_283___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_283__RX_DCOC_RES_I_283___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_283__RX_DCOC_RES_Q_283___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_283__RX_DCOC_RANGE_283___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_283__RX_DCOC_RANGE_283___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_283__RX_DCOC_RES_I_283___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_283__RX_DCOC_RES_I_283___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_283__RX_DCOC_RES_Q_283___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_283__RX_DCOC_RES_Q_283___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_283___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_283___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_284 (0x005F4470) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_284___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_284___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_284__RX_DCOC_RANGE_284___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_284__RX_DCOC_RES_I_284___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_284__RX_DCOC_RES_Q_284___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_284__RX_DCOC_RANGE_284___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_284__RX_DCOC_RANGE_284___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_284__RX_DCOC_RES_I_284___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_284__RX_DCOC_RES_I_284___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_284__RX_DCOC_RES_Q_284___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_284__RX_DCOC_RES_Q_284___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_284___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_284___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_285 (0x005F4474) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_285___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_285___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_285__RX_DCOC_RANGE_285___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_285__RX_DCOC_RES_I_285___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_285__RX_DCOC_RES_Q_285___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_285__RX_DCOC_RANGE_285___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_285__RX_DCOC_RANGE_285___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_285__RX_DCOC_RES_I_285___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_285__RX_DCOC_RES_I_285___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_285__RX_DCOC_RES_Q_285___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_285__RX_DCOC_RES_Q_285___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_285___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_285___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_286 (0x005F4478) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_286___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_286___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_286__RX_DCOC_RANGE_286___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_286__RX_DCOC_RES_I_286___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_286__RX_DCOC_RES_Q_286___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_286__RX_DCOC_RANGE_286___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_286__RX_DCOC_RANGE_286___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_286__RX_DCOC_RES_I_286___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_286__RX_DCOC_RES_I_286___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_286__RX_DCOC_RES_Q_286___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_286__RX_DCOC_RES_Q_286___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_286___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_286___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_287 (0x005F447C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_287___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_287___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_287__RX_DCOC_RANGE_287___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_287__RX_DCOC_RES_I_287___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_287__RX_DCOC_RES_Q_287___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_287__RX_DCOC_RANGE_287___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_287__RX_DCOC_RANGE_287___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_287__RX_DCOC_RES_I_287___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_287__RX_DCOC_RES_I_287___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_287__RX_DCOC_RES_Q_287___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_287__RX_DCOC_RES_Q_287___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_287___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_287___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_288 (0x005F4480) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_288___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_288___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_288__RX_DCOC_RANGE_288___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_288__RX_DCOC_RES_I_288___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_288__RX_DCOC_RES_Q_288___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_288__RX_DCOC_RANGE_288___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_288__RX_DCOC_RANGE_288___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_288__RX_DCOC_RES_I_288___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_288__RX_DCOC_RES_I_288___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_288__RX_DCOC_RES_Q_288___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_288__RX_DCOC_RES_Q_288___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_288___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_288___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_289 (0x005F4484) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_289___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_289___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_289__RX_DCOC_RANGE_289___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_289__RX_DCOC_RES_I_289___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_289__RX_DCOC_RES_Q_289___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_289__RX_DCOC_RANGE_289___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_289__RX_DCOC_RANGE_289___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_289__RX_DCOC_RES_I_289___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_289__RX_DCOC_RES_I_289___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_289__RX_DCOC_RES_Q_289___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_289__RX_DCOC_RES_Q_289___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_289___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_289___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_290 (0x005F4488) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_290___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_290___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_290__RX_DCOC_RANGE_290___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_290__RX_DCOC_RES_I_290___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_290__RX_DCOC_RES_Q_290___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_290__RX_DCOC_RANGE_290___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_290__RX_DCOC_RANGE_290___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_290__RX_DCOC_RES_I_290___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_290__RX_DCOC_RES_I_290___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_290__RX_DCOC_RES_Q_290___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_290__RX_DCOC_RES_Q_290___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_290___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_290___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_291 (0x005F448C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_291___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_291___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_291__RX_DCOC_RANGE_291___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_291__RX_DCOC_RES_I_291___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_291__RX_DCOC_RES_Q_291___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_291__RX_DCOC_RANGE_291___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_291__RX_DCOC_RANGE_291___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_291__RX_DCOC_RES_I_291___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_291__RX_DCOC_RES_I_291___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_291__RX_DCOC_RES_Q_291___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_291__RX_DCOC_RES_Q_291___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_291___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_291___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_292 (0x005F4490) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_292___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_292___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_292__RX_DCOC_RANGE_292___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_292__RX_DCOC_RES_I_292___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_292__RX_DCOC_RES_Q_292___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_292__RX_DCOC_RANGE_292___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_292__RX_DCOC_RANGE_292___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_292__RX_DCOC_RES_I_292___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_292__RX_DCOC_RES_I_292___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_292__RX_DCOC_RES_Q_292___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_292__RX_DCOC_RES_Q_292___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_292___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_292___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_293 (0x005F4494) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_293___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_293___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_293__RX_DCOC_RANGE_293___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_293__RX_DCOC_RES_I_293___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_293__RX_DCOC_RES_Q_293___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_293__RX_DCOC_RANGE_293___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_293__RX_DCOC_RANGE_293___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_293__RX_DCOC_RES_I_293___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_293__RX_DCOC_RES_I_293___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_293__RX_DCOC_RES_Q_293___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_293__RX_DCOC_RES_Q_293___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_293___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_293___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_294 (0x005F4498) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_294___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_294___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_294__RX_DCOC_RANGE_294___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_294__RX_DCOC_RES_I_294___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_294__RX_DCOC_RES_Q_294___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_294__RX_DCOC_RANGE_294___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_294__RX_DCOC_RANGE_294___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_294__RX_DCOC_RES_I_294___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_294__RX_DCOC_RES_I_294___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_294__RX_DCOC_RES_Q_294___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_294__RX_DCOC_RES_Q_294___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_294___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_294___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_295 (0x005F449C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_295___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_295___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_295__RX_DCOC_RANGE_295___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_295__RX_DCOC_RES_I_295___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_295__RX_DCOC_RES_Q_295___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_295__RX_DCOC_RANGE_295___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_295__RX_DCOC_RANGE_295___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_295__RX_DCOC_RES_I_295___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_295__RX_DCOC_RES_I_295___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_295__RX_DCOC_RES_Q_295___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_295__RX_DCOC_RES_Q_295___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_295___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_295___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_296 (0x005F44A0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_296___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_296___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_296__RX_DCOC_RANGE_296___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_296__RX_DCOC_RES_I_296___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_296__RX_DCOC_RES_Q_296___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_296__RX_DCOC_RANGE_296___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_296__RX_DCOC_RANGE_296___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_296__RX_DCOC_RES_I_296___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_296__RX_DCOC_RES_I_296___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_296__RX_DCOC_RES_Q_296___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_296__RX_DCOC_RES_Q_296___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_296___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_296___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_297 (0x005F44A4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_297___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_297___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_297__RX_DCOC_RANGE_297___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_297__RX_DCOC_RES_I_297___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_297__RX_DCOC_RES_Q_297___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_297__RX_DCOC_RANGE_297___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_297__RX_DCOC_RANGE_297___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_297__RX_DCOC_RES_I_297___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_297__RX_DCOC_RES_I_297___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_297__RX_DCOC_RES_Q_297___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_297__RX_DCOC_RES_Q_297___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_297___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_297___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_298 (0x005F44A8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_298___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_298___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_298__RX_DCOC_RANGE_298___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_298__RX_DCOC_RES_I_298___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_298__RX_DCOC_RES_Q_298___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_298__RX_DCOC_RANGE_298___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_298__RX_DCOC_RANGE_298___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_298__RX_DCOC_RES_I_298___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_298__RX_DCOC_RES_I_298___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_298__RX_DCOC_RES_Q_298___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_298__RX_DCOC_RES_Q_298___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_298___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_298___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_299 (0x005F44AC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_299___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_299___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_299__RX_DCOC_RANGE_299___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_299__RX_DCOC_RES_I_299___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_299__RX_DCOC_RES_Q_299___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_299__RX_DCOC_RANGE_299___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_299__RX_DCOC_RANGE_299___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_299__RX_DCOC_RES_I_299___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_299__RX_DCOC_RES_I_299___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_299__RX_DCOC_RES_Q_299___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_299__RX_DCOC_RES_Q_299___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_299___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_299___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_300 (0x005F44B0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_300___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_300___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_300__RX_DCOC_RANGE_300___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_300__RX_DCOC_RES_I_300___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_300__RX_DCOC_RES_Q_300___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_300__RX_DCOC_RANGE_300___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_300__RX_DCOC_RANGE_300___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_300__RX_DCOC_RES_I_300___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_300__RX_DCOC_RES_I_300___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_300__RX_DCOC_RES_Q_300___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_300__RX_DCOC_RES_Q_300___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_300___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_300___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_301 (0x005F44B4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_301___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_301___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_301__RX_DCOC_RANGE_301___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_301__RX_DCOC_RES_I_301___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_301__RX_DCOC_RES_Q_301___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_301__RX_DCOC_RANGE_301___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_301__RX_DCOC_RANGE_301___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_301__RX_DCOC_RES_I_301___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_301__RX_DCOC_RES_I_301___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_301__RX_DCOC_RES_Q_301___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_301__RX_DCOC_RES_Q_301___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_301___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_301___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_302 (0x005F44B8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_302___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_302___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_302__RX_DCOC_RANGE_302___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_302__RX_DCOC_RES_I_302___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_302__RX_DCOC_RES_Q_302___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_302__RX_DCOC_RANGE_302___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_302__RX_DCOC_RANGE_302___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_302__RX_DCOC_RES_I_302___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_302__RX_DCOC_RES_I_302___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_302__RX_DCOC_RES_Q_302___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_302__RX_DCOC_RES_Q_302___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_302___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_302___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_303 (0x005F44BC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_303___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_303___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_303__RX_DCOC_RANGE_303___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_303__RX_DCOC_RES_I_303___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_303__RX_DCOC_RES_Q_303___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_303__RX_DCOC_RANGE_303___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_303__RX_DCOC_RANGE_303___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_303__RX_DCOC_RES_I_303___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_303__RX_DCOC_RES_I_303___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_303__RX_DCOC_RES_Q_303___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_303__RX_DCOC_RES_Q_303___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_303___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_303___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_304 (0x005F44C0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_304___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_304___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_304__RX_DCOC_RANGE_304___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_304__RX_DCOC_RES_I_304___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_304__RX_DCOC_RES_Q_304___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_304__RX_DCOC_RANGE_304___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_304__RX_DCOC_RANGE_304___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_304__RX_DCOC_RES_I_304___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_304__RX_DCOC_RES_I_304___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_304__RX_DCOC_RES_Q_304___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_304__RX_DCOC_RES_Q_304___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_304___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_304___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_305 (0x005F44C4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_305___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_305___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_305__RX_DCOC_RANGE_305___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_305__RX_DCOC_RES_I_305___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_305__RX_DCOC_RES_Q_305___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_305__RX_DCOC_RANGE_305___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_305__RX_DCOC_RANGE_305___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_305__RX_DCOC_RES_I_305___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_305__RX_DCOC_RES_I_305___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_305__RX_DCOC_RES_Q_305___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_305__RX_DCOC_RES_Q_305___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_305___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_305___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_306 (0x005F44C8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_306___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_306___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_306__RX_DCOC_RANGE_306___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_306__RX_DCOC_RES_I_306___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_306__RX_DCOC_RES_Q_306___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_306__RX_DCOC_RANGE_306___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_306__RX_DCOC_RANGE_306___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_306__RX_DCOC_RES_I_306___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_306__RX_DCOC_RES_I_306___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_306__RX_DCOC_RES_Q_306___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_306__RX_DCOC_RES_Q_306___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_306___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_306___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_307 (0x005F44CC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_307___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_307___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_307__RX_DCOC_RANGE_307___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_307__RX_DCOC_RES_I_307___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_307__RX_DCOC_RES_Q_307___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_307__RX_DCOC_RANGE_307___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_307__RX_DCOC_RANGE_307___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_307__RX_DCOC_RES_I_307___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_307__RX_DCOC_RES_I_307___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_307__RX_DCOC_RES_Q_307___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_307__RX_DCOC_RES_Q_307___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_307___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_307___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_308 (0x005F44D0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_308___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_308___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_308__RX_DCOC_RANGE_308___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_308__RX_DCOC_RES_I_308___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_308__RX_DCOC_RES_Q_308___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_308__RX_DCOC_RANGE_308___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_308__RX_DCOC_RANGE_308___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_308__RX_DCOC_RES_I_308___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_308__RX_DCOC_RES_I_308___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_308__RX_DCOC_RES_Q_308___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_308__RX_DCOC_RES_Q_308___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_308___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_308___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_309 (0x005F44D4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_309___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_309___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_309__RX_DCOC_RANGE_309___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_309__RX_DCOC_RES_I_309___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_309__RX_DCOC_RES_Q_309___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_309__RX_DCOC_RANGE_309___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_309__RX_DCOC_RANGE_309___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_309__RX_DCOC_RES_I_309___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_309__RX_DCOC_RES_I_309___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_309__RX_DCOC_RES_Q_309___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_309__RX_DCOC_RES_Q_309___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_309___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_309___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_310 (0x005F44D8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_310___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_310___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_310__RX_DCOC_RANGE_310___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_310__RX_DCOC_RES_I_310___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_310__RX_DCOC_RES_Q_310___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_310__RX_DCOC_RANGE_310___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_310__RX_DCOC_RANGE_310___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_310__RX_DCOC_RES_I_310___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_310__RX_DCOC_RES_I_310___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_310__RX_DCOC_RES_Q_310___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_310__RX_DCOC_RES_Q_310___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_310___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_310___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_311 (0x005F44DC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_311___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_311___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_311__RX_DCOC_RANGE_311___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_311__RX_DCOC_RES_I_311___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_311__RX_DCOC_RES_Q_311___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_311__RX_DCOC_RANGE_311___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_311__RX_DCOC_RANGE_311___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_311__RX_DCOC_RES_I_311___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_311__RX_DCOC_RES_I_311___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_311__RX_DCOC_RES_Q_311___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_311__RX_DCOC_RES_Q_311___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_311___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_311___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_312 (0x005F44E0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_312___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_312___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_312__RX_DCOC_RANGE_312___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_312__RX_DCOC_RES_I_312___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_312__RX_DCOC_RES_Q_312___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_312__RX_DCOC_RANGE_312___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_312__RX_DCOC_RANGE_312___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_312__RX_DCOC_RES_I_312___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_312__RX_DCOC_RES_I_312___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_312__RX_DCOC_RES_Q_312___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_312__RX_DCOC_RES_Q_312___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_312___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_312___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_313 (0x005F44E4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_313___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_313___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_313__RX_DCOC_RANGE_313___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_313__RX_DCOC_RES_I_313___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_313__RX_DCOC_RES_Q_313___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_313__RX_DCOC_RANGE_313___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_313__RX_DCOC_RANGE_313___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_313__RX_DCOC_RES_I_313___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_313__RX_DCOC_RES_I_313___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_313__RX_DCOC_RES_Q_313___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_313__RX_DCOC_RES_Q_313___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_313___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_313___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_314 (0x005F44E8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_314___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_314___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_314__RX_DCOC_RANGE_314___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_314__RX_DCOC_RES_I_314___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_314__RX_DCOC_RES_Q_314___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_314__RX_DCOC_RANGE_314___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_314__RX_DCOC_RANGE_314___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_314__RX_DCOC_RES_I_314___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_314__RX_DCOC_RES_I_314___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_314__RX_DCOC_RES_Q_314___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_314__RX_DCOC_RES_Q_314___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_314___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_314___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_315 (0x005F44EC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_315___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_315___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_315__RX_DCOC_RANGE_315___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_315__RX_DCOC_RES_I_315___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_315__RX_DCOC_RES_Q_315___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_315__RX_DCOC_RANGE_315___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_315__RX_DCOC_RANGE_315___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_315__RX_DCOC_RES_I_315___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_315__RX_DCOC_RES_I_315___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_315__RX_DCOC_RES_Q_315___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_315__RX_DCOC_RES_Q_315___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_315___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_315___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_316 (0x005F44F0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_316___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_316___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_316__RX_DCOC_RANGE_316___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_316__RX_DCOC_RES_I_316___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_316__RX_DCOC_RES_Q_316___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_316__RX_DCOC_RANGE_316___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_316__RX_DCOC_RANGE_316___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_316__RX_DCOC_RES_I_316___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_316__RX_DCOC_RES_I_316___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_316__RX_DCOC_RES_Q_316___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_316__RX_DCOC_RES_Q_316___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_316___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_316___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_317 (0x005F44F4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_317___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_317___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_317__RX_DCOC_RANGE_317___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_317__RX_DCOC_RES_I_317___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_317__RX_DCOC_RES_Q_317___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_317__RX_DCOC_RANGE_317___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_317__RX_DCOC_RANGE_317___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_317__RX_DCOC_RES_I_317___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_317__RX_DCOC_RES_I_317___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_317__RX_DCOC_RES_Q_317___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_317__RX_DCOC_RES_Q_317___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_317___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_317___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_318 (0x005F44F8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_318___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_318___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_318__RX_DCOC_RANGE_318___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_318__RX_DCOC_RES_I_318___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_318__RX_DCOC_RES_Q_318___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_318__RX_DCOC_RANGE_318___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_318__RX_DCOC_RANGE_318___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_318__RX_DCOC_RES_I_318___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_318__RX_DCOC_RES_I_318___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_318__RX_DCOC_RES_Q_318___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_318__RX_DCOC_RES_Q_318___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_318___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_318___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_319 (0x005F44FC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_319___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_319___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_319__RX_DCOC_RANGE_319___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_319__RX_DCOC_RES_I_319___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_319__RX_DCOC_RES_Q_319___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_319__RX_DCOC_RANGE_319___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_319__RX_DCOC_RANGE_319___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_319__RX_DCOC_RES_I_319___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_319__RX_DCOC_RES_I_319___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_319__RX_DCOC_RES_Q_319___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_319__RX_DCOC_RES_Q_319___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_319___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_319___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_320 (0x005F4500) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_320___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_320___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_320__RX_DCOC_RANGE_320___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_320__RX_DCOC_RES_I_320___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_320__RX_DCOC_RES_Q_320___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_320__RX_DCOC_RANGE_320___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_320__RX_DCOC_RANGE_320___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_320__RX_DCOC_RES_I_320___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_320__RX_DCOC_RES_I_320___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_320__RX_DCOC_RES_Q_320___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_320__RX_DCOC_RES_Q_320___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_320___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_320___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_321 (0x005F4504) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_321___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_321___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_321__RX_DCOC_RANGE_321___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_321__RX_DCOC_RES_I_321___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_321__RX_DCOC_RES_Q_321___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_321__RX_DCOC_RANGE_321___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_321__RX_DCOC_RANGE_321___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_321__RX_DCOC_RES_I_321___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_321__RX_DCOC_RES_I_321___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_321__RX_DCOC_RES_Q_321___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_321__RX_DCOC_RES_Q_321___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_321___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_321___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_322 (0x005F4508) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_322___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_322___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_322__RX_DCOC_RANGE_322___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_322__RX_DCOC_RES_I_322___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_322__RX_DCOC_RES_Q_322___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_322__RX_DCOC_RANGE_322___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_322__RX_DCOC_RANGE_322___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_322__RX_DCOC_RES_I_322___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_322__RX_DCOC_RES_I_322___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_322__RX_DCOC_RES_Q_322___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_322__RX_DCOC_RES_Q_322___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_322___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_322___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_323 (0x005F450C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_323___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_323___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_323__RX_DCOC_RANGE_323___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_323__RX_DCOC_RES_I_323___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_323__RX_DCOC_RES_Q_323___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_323__RX_DCOC_RANGE_323___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_323__RX_DCOC_RANGE_323___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_323__RX_DCOC_RES_I_323___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_323__RX_DCOC_RES_I_323___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_323__RX_DCOC_RES_Q_323___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_323__RX_DCOC_RES_Q_323___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_323___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_323___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_324 (0x005F4510) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_324___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_324___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_324__RX_DCOC_RANGE_324___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_324__RX_DCOC_RES_I_324___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_324__RX_DCOC_RES_Q_324___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_324__RX_DCOC_RANGE_324___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_324__RX_DCOC_RANGE_324___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_324__RX_DCOC_RES_I_324___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_324__RX_DCOC_RES_I_324___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_324__RX_DCOC_RES_Q_324___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_324__RX_DCOC_RES_Q_324___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_324___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_324___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_325 (0x005F4514) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_325___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_325___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_325__RX_DCOC_RANGE_325___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_325__RX_DCOC_RES_I_325___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_325__RX_DCOC_RES_Q_325___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_325__RX_DCOC_RANGE_325___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_325__RX_DCOC_RANGE_325___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_325__RX_DCOC_RES_I_325___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_325__RX_DCOC_RES_I_325___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_325__RX_DCOC_RES_Q_325___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_325__RX_DCOC_RES_Q_325___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_325___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_325___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_326 (0x005F4518) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_326___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_326___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_326__RX_DCOC_RANGE_326___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_326__RX_DCOC_RES_I_326___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_326__RX_DCOC_RES_Q_326___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_326__RX_DCOC_RANGE_326___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_326__RX_DCOC_RANGE_326___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_326__RX_DCOC_RES_I_326___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_326__RX_DCOC_RES_I_326___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_326__RX_DCOC_RES_Q_326___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_326__RX_DCOC_RES_Q_326___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_326___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_326___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_327 (0x005F451C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_327___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_327___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_327__RX_DCOC_RANGE_327___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_327__RX_DCOC_RES_I_327___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_327__RX_DCOC_RES_Q_327___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_327__RX_DCOC_RANGE_327___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_327__RX_DCOC_RANGE_327___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_327__RX_DCOC_RES_I_327___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_327__RX_DCOC_RES_I_327___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_327__RX_DCOC_RES_Q_327___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_327__RX_DCOC_RES_Q_327___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_327___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_327___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_328 (0x005F4520) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_328___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_328___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_328__RX_DCOC_RANGE_328___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_328__RX_DCOC_RES_I_328___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_328__RX_DCOC_RES_Q_328___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_328__RX_DCOC_RANGE_328___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_328__RX_DCOC_RANGE_328___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_328__RX_DCOC_RES_I_328___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_328__RX_DCOC_RES_I_328___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_328__RX_DCOC_RES_Q_328___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_328__RX_DCOC_RES_Q_328___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_328___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_328___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_329 (0x005F4524) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_329___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_329___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_329__RX_DCOC_RANGE_329___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_329__RX_DCOC_RES_I_329___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_329__RX_DCOC_RES_Q_329___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_329__RX_DCOC_RANGE_329___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_329__RX_DCOC_RANGE_329___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_329__RX_DCOC_RES_I_329___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_329__RX_DCOC_RES_I_329___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_329__RX_DCOC_RES_Q_329___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_329__RX_DCOC_RES_Q_329___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_329___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_329___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_330 (0x005F4528) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_330___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_330___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_330__RX_DCOC_RANGE_330___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_330__RX_DCOC_RES_I_330___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_330__RX_DCOC_RES_Q_330___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_330__RX_DCOC_RANGE_330___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_330__RX_DCOC_RANGE_330___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_330__RX_DCOC_RES_I_330___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_330__RX_DCOC_RES_I_330___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_330__RX_DCOC_RES_Q_330___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_330__RX_DCOC_RES_Q_330___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_330___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_330___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_331 (0x005F452C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_331___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_331___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_331__RX_DCOC_RANGE_331___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_331__RX_DCOC_RES_I_331___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_331__RX_DCOC_RES_Q_331___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_331__RX_DCOC_RANGE_331___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_331__RX_DCOC_RANGE_331___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_331__RX_DCOC_RES_I_331___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_331__RX_DCOC_RES_I_331___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_331__RX_DCOC_RES_Q_331___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_331__RX_DCOC_RES_Q_331___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_331___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_331___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_332 (0x005F4530) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_332___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_332___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_332__RX_DCOC_RANGE_332___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_332__RX_DCOC_RES_I_332___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_332__RX_DCOC_RES_Q_332___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_332__RX_DCOC_RANGE_332___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_332__RX_DCOC_RANGE_332___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_332__RX_DCOC_RES_I_332___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_332__RX_DCOC_RES_I_332___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_332__RX_DCOC_RES_Q_332___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_332__RX_DCOC_RES_Q_332___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_332___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_332___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_333 (0x005F4534) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_333___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_333___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_333__RX_DCOC_RANGE_333___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_333__RX_DCOC_RES_I_333___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_333__RX_DCOC_RES_Q_333___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_333__RX_DCOC_RANGE_333___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_333__RX_DCOC_RANGE_333___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_333__RX_DCOC_RES_I_333___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_333__RX_DCOC_RES_I_333___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_333__RX_DCOC_RES_Q_333___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_333__RX_DCOC_RES_Q_333___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_333___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_333___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_334 (0x005F4538) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_334___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_334___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_334__RX_DCOC_RANGE_334___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_334__RX_DCOC_RES_I_334___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_334__RX_DCOC_RES_Q_334___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_334__RX_DCOC_RANGE_334___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_334__RX_DCOC_RANGE_334___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_334__RX_DCOC_RES_I_334___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_334__RX_DCOC_RES_I_334___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_334__RX_DCOC_RES_Q_334___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_334__RX_DCOC_RES_Q_334___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_334___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_334___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_335 (0x005F453C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_335___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_335___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_335__RX_DCOC_RANGE_335___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_335__RX_DCOC_RES_I_335___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_335__RX_DCOC_RES_Q_335___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_335__RX_DCOC_RANGE_335___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_335__RX_DCOC_RANGE_335___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_335__RX_DCOC_RES_I_335___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_335__RX_DCOC_RES_I_335___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_335__RX_DCOC_RES_Q_335___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_335__RX_DCOC_RES_Q_335___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_335___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_335___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_336 (0x005F4540) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_336___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_336___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_336__RX_DCOC_RANGE_336___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_336__RX_DCOC_RES_I_336___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_336__RX_DCOC_RES_Q_336___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_336__RX_DCOC_RANGE_336___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_336__RX_DCOC_RANGE_336___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_336__RX_DCOC_RES_I_336___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_336__RX_DCOC_RES_I_336___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_336__RX_DCOC_RES_Q_336___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_336__RX_DCOC_RES_Q_336___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_336___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_336___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_337 (0x005F4544) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_337___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_337___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_337__RX_DCOC_RANGE_337___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_337__RX_DCOC_RES_I_337___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_337__RX_DCOC_RES_Q_337___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_337__RX_DCOC_RANGE_337___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_337__RX_DCOC_RANGE_337___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_337__RX_DCOC_RES_I_337___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_337__RX_DCOC_RES_I_337___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_337__RX_DCOC_RES_Q_337___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_337__RX_DCOC_RES_Q_337___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_337___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_337___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_338 (0x005F4548) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_338___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_338___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_338__RX_DCOC_RANGE_338___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_338__RX_DCOC_RES_I_338___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_338__RX_DCOC_RES_Q_338___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_338__RX_DCOC_RANGE_338___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_338__RX_DCOC_RANGE_338___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_338__RX_DCOC_RES_I_338___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_338__RX_DCOC_RES_I_338___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_338__RX_DCOC_RES_Q_338___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_338__RX_DCOC_RES_Q_338___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_338___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_338___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_339 (0x005F454C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_339___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_339___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_339__RX_DCOC_RANGE_339___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_339__RX_DCOC_RES_I_339___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_339__RX_DCOC_RES_Q_339___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_339__RX_DCOC_RANGE_339___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_339__RX_DCOC_RANGE_339___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_339__RX_DCOC_RES_I_339___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_339__RX_DCOC_RES_I_339___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_339__RX_DCOC_RES_Q_339___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_339__RX_DCOC_RES_Q_339___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_339___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_339___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_340 (0x005F4550) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_340___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_340___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_340__RX_DCOC_RANGE_340___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_340__RX_DCOC_RES_I_340___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_340__RX_DCOC_RES_Q_340___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_340__RX_DCOC_RANGE_340___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_340__RX_DCOC_RANGE_340___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_340__RX_DCOC_RES_I_340___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_340__RX_DCOC_RES_I_340___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_340__RX_DCOC_RES_Q_340___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_340__RX_DCOC_RES_Q_340___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_340___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_340___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_341 (0x005F4554) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_341___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_341___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_341__RX_DCOC_RANGE_341___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_341__RX_DCOC_RES_I_341___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_341__RX_DCOC_RES_Q_341___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_341__RX_DCOC_RANGE_341___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_341__RX_DCOC_RANGE_341___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_341__RX_DCOC_RES_I_341___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_341__RX_DCOC_RES_I_341___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_341__RX_DCOC_RES_Q_341___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_341__RX_DCOC_RES_Q_341___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_341___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_341___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_342 (0x005F4558) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_342___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_342___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_342__RX_DCOC_RANGE_342___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_342__RX_DCOC_RES_I_342___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_342__RX_DCOC_RES_Q_342___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_342__RX_DCOC_RANGE_342___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_342__RX_DCOC_RANGE_342___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_342__RX_DCOC_RES_I_342___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_342__RX_DCOC_RES_I_342___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_342__RX_DCOC_RES_Q_342___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_342__RX_DCOC_RES_Q_342___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_342___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_342___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_343 (0x005F455C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_343___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_343___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_343__RX_DCOC_RANGE_343___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_343__RX_DCOC_RES_I_343___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_343__RX_DCOC_RES_Q_343___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_343__RX_DCOC_RANGE_343___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_343__RX_DCOC_RANGE_343___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_343__RX_DCOC_RES_I_343___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_343__RX_DCOC_RES_I_343___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_343__RX_DCOC_RES_Q_343___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_343__RX_DCOC_RES_Q_343___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_343___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_343___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_344 (0x005F4560) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_344___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_344___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_344__RX_DCOC_RANGE_344___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_344__RX_DCOC_RES_I_344___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_344__RX_DCOC_RES_Q_344___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_344__RX_DCOC_RANGE_344___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_344__RX_DCOC_RANGE_344___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_344__RX_DCOC_RES_I_344___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_344__RX_DCOC_RES_I_344___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_344__RX_DCOC_RES_Q_344___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_344__RX_DCOC_RES_Q_344___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_344___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_344___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_345 (0x005F4564) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_345___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_345___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_345__RX_DCOC_RANGE_345___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_345__RX_DCOC_RES_I_345___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_345__RX_DCOC_RES_Q_345___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_345__RX_DCOC_RANGE_345___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_345__RX_DCOC_RANGE_345___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_345__RX_DCOC_RES_I_345___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_345__RX_DCOC_RES_I_345___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_345__RX_DCOC_RES_Q_345___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_345__RX_DCOC_RES_Q_345___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_345___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_345___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_346 (0x005F4568) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_346___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_346___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_346__RX_DCOC_RANGE_346___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_346__RX_DCOC_RES_I_346___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_346__RX_DCOC_RES_Q_346___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_346__RX_DCOC_RANGE_346___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_346__RX_DCOC_RANGE_346___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_346__RX_DCOC_RES_I_346___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_346__RX_DCOC_RES_I_346___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_346__RX_DCOC_RES_Q_346___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_346__RX_DCOC_RES_Q_346___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_346___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_346___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_347 (0x005F456C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_347___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_347___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_347__RX_DCOC_RANGE_347___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_347__RX_DCOC_RES_I_347___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_347__RX_DCOC_RES_Q_347___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_347__RX_DCOC_RANGE_347___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_347__RX_DCOC_RANGE_347___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_347__RX_DCOC_RES_I_347___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_347__RX_DCOC_RES_I_347___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_347__RX_DCOC_RES_Q_347___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_347__RX_DCOC_RES_Q_347___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_347___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_347___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_348 (0x005F4570) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_348___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_348___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_348__RX_DCOC_RANGE_348___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_348__RX_DCOC_RES_I_348___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_348__RX_DCOC_RES_Q_348___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_348__RX_DCOC_RANGE_348___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_348__RX_DCOC_RANGE_348___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_348__RX_DCOC_RES_I_348___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_348__RX_DCOC_RES_I_348___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_348__RX_DCOC_RES_Q_348___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_348__RX_DCOC_RES_Q_348___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_348___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_348___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_349 (0x005F4574) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_349___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_349___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_349__RX_DCOC_RANGE_349___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_349__RX_DCOC_RES_I_349___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_349__RX_DCOC_RES_Q_349___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_349__RX_DCOC_RANGE_349___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_349__RX_DCOC_RANGE_349___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_349__RX_DCOC_RES_I_349___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_349__RX_DCOC_RES_I_349___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_349__RX_DCOC_RES_Q_349___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_349__RX_DCOC_RES_Q_349___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_349___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_349___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_350 (0x005F4578) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_350___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_350___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_350__RX_DCOC_RANGE_350___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_350__RX_DCOC_RES_I_350___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_350__RX_DCOC_RES_Q_350___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_350__RX_DCOC_RANGE_350___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_350__RX_DCOC_RANGE_350___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_350__RX_DCOC_RES_I_350___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_350__RX_DCOC_RES_I_350___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_350__RX_DCOC_RES_Q_350___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_350__RX_DCOC_RES_Q_350___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_350___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_350___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_351 (0x005F457C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_351___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_351___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_351__RX_DCOC_RANGE_351___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_351__RX_DCOC_RES_I_351___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_351__RX_DCOC_RES_Q_351___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_351__RX_DCOC_RANGE_351___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_351__RX_DCOC_RANGE_351___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_351__RX_DCOC_RES_I_351___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_351__RX_DCOC_RES_I_351___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_351__RX_DCOC_RES_Q_351___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_351__RX_DCOC_RES_Q_351___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_351___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_351___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_352 (0x005F4580) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_352___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_352___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_352__RX_DCOC_RANGE_352___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_352__RX_DCOC_RES_I_352___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_352__RX_DCOC_RES_Q_352___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_352__RX_DCOC_RANGE_352___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_352__RX_DCOC_RANGE_352___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_352__RX_DCOC_RES_I_352___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_352__RX_DCOC_RES_I_352___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_352__RX_DCOC_RES_Q_352___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_352__RX_DCOC_RES_Q_352___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_352___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_352___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_353 (0x005F4584) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_353___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_353___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_353__RX_DCOC_RANGE_353___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_353__RX_DCOC_RES_I_353___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_353__RX_DCOC_RES_Q_353___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_353__RX_DCOC_RANGE_353___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_353__RX_DCOC_RANGE_353___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_353__RX_DCOC_RES_I_353___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_353__RX_DCOC_RES_I_353___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_353__RX_DCOC_RES_Q_353___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_353__RX_DCOC_RES_Q_353___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_353___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_353___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_354 (0x005F4588) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_354___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_354___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_354__RX_DCOC_RANGE_354___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_354__RX_DCOC_RES_I_354___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_354__RX_DCOC_RES_Q_354___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_354__RX_DCOC_RANGE_354___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_354__RX_DCOC_RANGE_354___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_354__RX_DCOC_RES_I_354___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_354__RX_DCOC_RES_I_354___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_354__RX_DCOC_RES_Q_354___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_354__RX_DCOC_RES_Q_354___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_354___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_354___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_355 (0x005F458C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_355___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_355___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_355__RX_DCOC_RANGE_355___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_355__RX_DCOC_RES_I_355___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_355__RX_DCOC_RES_Q_355___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_355__RX_DCOC_RANGE_355___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_355__RX_DCOC_RANGE_355___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_355__RX_DCOC_RES_I_355___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_355__RX_DCOC_RES_I_355___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_355__RX_DCOC_RES_Q_355___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_355__RX_DCOC_RES_Q_355___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_355___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_355___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_356 (0x005F4590) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_356___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_356___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_356__RX_DCOC_RANGE_356___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_356__RX_DCOC_RES_I_356___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_356__RX_DCOC_RES_Q_356___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_356__RX_DCOC_RANGE_356___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_356__RX_DCOC_RANGE_356___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_356__RX_DCOC_RES_I_356___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_356__RX_DCOC_RES_I_356___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_356__RX_DCOC_RES_Q_356___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_356__RX_DCOC_RES_Q_356___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_356___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_356___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_357 (0x005F4594) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_357___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_357___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_357__RX_DCOC_RANGE_357___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_357__RX_DCOC_RES_I_357___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_357__RX_DCOC_RES_Q_357___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_357__RX_DCOC_RANGE_357___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_357__RX_DCOC_RANGE_357___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_357__RX_DCOC_RES_I_357___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_357__RX_DCOC_RES_I_357___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_357__RX_DCOC_RES_Q_357___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_357__RX_DCOC_RES_Q_357___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_357___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_357___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_358 (0x005F4598) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_358___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_358___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_358__RX_DCOC_RANGE_358___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_358__RX_DCOC_RES_I_358___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_358__RX_DCOC_RES_Q_358___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_358__RX_DCOC_RANGE_358___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_358__RX_DCOC_RANGE_358___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_358__RX_DCOC_RES_I_358___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_358__RX_DCOC_RES_I_358___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_358__RX_DCOC_RES_Q_358___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_358__RX_DCOC_RES_Q_358___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_358___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_358___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_359 (0x005F459C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_359___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_359___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_359__RX_DCOC_RANGE_359___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_359__RX_DCOC_RES_I_359___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_359__RX_DCOC_RES_Q_359___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_359__RX_DCOC_RANGE_359___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_359__RX_DCOC_RANGE_359___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_359__RX_DCOC_RES_I_359___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_359__RX_DCOC_RES_I_359___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_359__RX_DCOC_RES_Q_359___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_359__RX_DCOC_RES_Q_359___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_359___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_359___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_360 (0x005F45A0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_360___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_360___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_360__RX_DCOC_RANGE_360___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_360__RX_DCOC_RES_I_360___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_360__RX_DCOC_RES_Q_360___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_360__RX_DCOC_RANGE_360___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_360__RX_DCOC_RANGE_360___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_360__RX_DCOC_RES_I_360___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_360__RX_DCOC_RES_I_360___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_360__RX_DCOC_RES_Q_360___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_360__RX_DCOC_RES_Q_360___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_360___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_360___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_361 (0x005F45A4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_361___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_361___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_361__RX_DCOC_RANGE_361___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_361__RX_DCOC_RES_I_361___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_361__RX_DCOC_RES_Q_361___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_361__RX_DCOC_RANGE_361___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_361__RX_DCOC_RANGE_361___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_361__RX_DCOC_RES_I_361___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_361__RX_DCOC_RES_I_361___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_361__RX_DCOC_RES_Q_361___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_361__RX_DCOC_RES_Q_361___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_361___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_361___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_362 (0x005F45A8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_362___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_362___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_362__RX_DCOC_RANGE_362___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_362__RX_DCOC_RES_I_362___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_362__RX_DCOC_RES_Q_362___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_362__RX_DCOC_RANGE_362___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_362__RX_DCOC_RANGE_362___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_362__RX_DCOC_RES_I_362___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_362__RX_DCOC_RES_I_362___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_362__RX_DCOC_RES_Q_362___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_362__RX_DCOC_RES_Q_362___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_362___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_362___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_363 (0x005F45AC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_363___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_363___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_363__RX_DCOC_RANGE_363___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_363__RX_DCOC_RES_I_363___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_363__RX_DCOC_RES_Q_363___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_363__RX_DCOC_RANGE_363___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_363__RX_DCOC_RANGE_363___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_363__RX_DCOC_RES_I_363___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_363__RX_DCOC_RES_I_363___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_363__RX_DCOC_RES_Q_363___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_363__RX_DCOC_RES_Q_363___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_363___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_363___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_364 (0x005F45B0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_364___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_364___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_364__RX_DCOC_RANGE_364___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_364__RX_DCOC_RES_I_364___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_364__RX_DCOC_RES_Q_364___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_364__RX_DCOC_RANGE_364___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_364__RX_DCOC_RANGE_364___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_364__RX_DCOC_RES_I_364___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_364__RX_DCOC_RES_I_364___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_364__RX_DCOC_RES_Q_364___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_364__RX_DCOC_RES_Q_364___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_364___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_364___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_365 (0x005F45B4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_365___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_365___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_365__RX_DCOC_RANGE_365___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_365__RX_DCOC_RES_I_365___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_365__RX_DCOC_RES_Q_365___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_365__RX_DCOC_RANGE_365___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_365__RX_DCOC_RANGE_365___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_365__RX_DCOC_RES_I_365___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_365__RX_DCOC_RES_I_365___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_365__RX_DCOC_RES_Q_365___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_365__RX_DCOC_RES_Q_365___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_365___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_365___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_366 (0x005F45B8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_366___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_366___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_366__RX_DCOC_RANGE_366___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_366__RX_DCOC_RES_I_366___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_366__RX_DCOC_RES_Q_366___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_366__RX_DCOC_RANGE_366___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_366__RX_DCOC_RANGE_366___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_366__RX_DCOC_RES_I_366___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_366__RX_DCOC_RES_I_366___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_366__RX_DCOC_RES_Q_366___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_366__RX_DCOC_RES_Q_366___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_366___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_366___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_367 (0x005F45BC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_367___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_367___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_367__RX_DCOC_RANGE_367___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_367__RX_DCOC_RES_I_367___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_367__RX_DCOC_RES_Q_367___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_367__RX_DCOC_RANGE_367___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_367__RX_DCOC_RANGE_367___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_367__RX_DCOC_RES_I_367___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_367__RX_DCOC_RES_I_367___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_367__RX_DCOC_RES_Q_367___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_367__RX_DCOC_RES_Q_367___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_367___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_367___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_368 (0x005F45C0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_368___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_368___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_368__RX_DCOC_RANGE_368___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_368__RX_DCOC_RES_I_368___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_368__RX_DCOC_RES_Q_368___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_368__RX_DCOC_RANGE_368___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_368__RX_DCOC_RANGE_368___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_368__RX_DCOC_RES_I_368___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_368__RX_DCOC_RES_I_368___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_368__RX_DCOC_RES_Q_368___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_368__RX_DCOC_RES_Q_368___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_368___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_368___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_369 (0x005F45C4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_369___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_369___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_369__RX_DCOC_RANGE_369___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_369__RX_DCOC_RES_I_369___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_369__RX_DCOC_RES_Q_369___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_369__RX_DCOC_RANGE_369___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_369__RX_DCOC_RANGE_369___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_369__RX_DCOC_RES_I_369___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_369__RX_DCOC_RES_I_369___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_369__RX_DCOC_RES_Q_369___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_369__RX_DCOC_RES_Q_369___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_369___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_369___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_370 (0x005F45C8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_370___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_370___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_370__RX_DCOC_RANGE_370___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_370__RX_DCOC_RES_I_370___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_370__RX_DCOC_RES_Q_370___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_370__RX_DCOC_RANGE_370___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_370__RX_DCOC_RANGE_370___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_370__RX_DCOC_RES_I_370___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_370__RX_DCOC_RES_I_370___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_370__RX_DCOC_RES_Q_370___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_370__RX_DCOC_RES_Q_370___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_370___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_370___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_371 (0x005F45CC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_371___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_371___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_371__RX_DCOC_RANGE_371___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_371__RX_DCOC_RES_I_371___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_371__RX_DCOC_RES_Q_371___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_371__RX_DCOC_RANGE_371___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_371__RX_DCOC_RANGE_371___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_371__RX_DCOC_RES_I_371___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_371__RX_DCOC_RES_I_371___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_371__RX_DCOC_RES_Q_371___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_371__RX_DCOC_RES_Q_371___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_371___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_371___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_372 (0x005F45D0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_372___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_372___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_372__RX_DCOC_RANGE_372___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_372__RX_DCOC_RES_I_372___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_372__RX_DCOC_RES_Q_372___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_372__RX_DCOC_RANGE_372___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_372__RX_DCOC_RANGE_372___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_372__RX_DCOC_RES_I_372___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_372__RX_DCOC_RES_I_372___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_372__RX_DCOC_RES_Q_372___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_372__RX_DCOC_RES_Q_372___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_372___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_372___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_373 (0x005F45D4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_373___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_373___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_373__RX_DCOC_RANGE_373___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_373__RX_DCOC_RES_I_373___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_373__RX_DCOC_RES_Q_373___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_373__RX_DCOC_RANGE_373___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_373__RX_DCOC_RANGE_373___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_373__RX_DCOC_RES_I_373___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_373__RX_DCOC_RES_I_373___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_373__RX_DCOC_RES_Q_373___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_373__RX_DCOC_RES_Q_373___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_373___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_373___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_374 (0x005F45D8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_374___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_374___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_374__RX_DCOC_RANGE_374___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_374__RX_DCOC_RES_I_374___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_374__RX_DCOC_RES_Q_374___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_374__RX_DCOC_RANGE_374___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_374__RX_DCOC_RANGE_374___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_374__RX_DCOC_RES_I_374___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_374__RX_DCOC_RES_I_374___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_374__RX_DCOC_RES_Q_374___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_374__RX_DCOC_RES_Q_374___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_374___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_374___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_375 (0x005F45DC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_375___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_375___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_375__RX_DCOC_RANGE_375___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_375__RX_DCOC_RES_I_375___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_375__RX_DCOC_RES_Q_375___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_375__RX_DCOC_RANGE_375___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_375__RX_DCOC_RANGE_375___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_375__RX_DCOC_RES_I_375___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_375__RX_DCOC_RES_I_375___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_375__RX_DCOC_RES_Q_375___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_375__RX_DCOC_RES_Q_375___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_375___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_375___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_376 (0x005F45E0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_376___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_376___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_376__RX_DCOC_RANGE_376___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_376__RX_DCOC_RES_I_376___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_376__RX_DCOC_RES_Q_376___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_376__RX_DCOC_RANGE_376___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_376__RX_DCOC_RANGE_376___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_376__RX_DCOC_RES_I_376___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_376__RX_DCOC_RES_I_376___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_376__RX_DCOC_RES_Q_376___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_376__RX_DCOC_RES_Q_376___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_376___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_376___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_377 (0x005F45E4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_377___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_377___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_377__RX_DCOC_RANGE_377___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_377__RX_DCOC_RES_I_377___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_377__RX_DCOC_RES_Q_377___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_377__RX_DCOC_RANGE_377___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_377__RX_DCOC_RANGE_377___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_377__RX_DCOC_RES_I_377___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_377__RX_DCOC_RES_I_377___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_377__RX_DCOC_RES_Q_377___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_377__RX_DCOC_RES_Q_377___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_377___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_377___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_378 (0x005F45E8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_378___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_378___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_378__RX_DCOC_RANGE_378___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_378__RX_DCOC_RES_I_378___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_378__RX_DCOC_RES_Q_378___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_378__RX_DCOC_RANGE_378___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_378__RX_DCOC_RANGE_378___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_378__RX_DCOC_RES_I_378___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_378__RX_DCOC_RES_I_378___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_378__RX_DCOC_RES_Q_378___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_378__RX_DCOC_RES_Q_378___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_378___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_378___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_379 (0x005F45EC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_379___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_379___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_379__RX_DCOC_RANGE_379___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_379__RX_DCOC_RES_I_379___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_379__RX_DCOC_RES_Q_379___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_379__RX_DCOC_RANGE_379___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_379__RX_DCOC_RANGE_379___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_379__RX_DCOC_RES_I_379___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_379__RX_DCOC_RES_I_379___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_379__RX_DCOC_RES_Q_379___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_379__RX_DCOC_RES_Q_379___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_379___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_379___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_380 (0x005F45F0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_380___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_380___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_380__RX_DCOC_RANGE_380___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_380__RX_DCOC_RES_I_380___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_380__RX_DCOC_RES_Q_380___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_380__RX_DCOC_RANGE_380___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_380__RX_DCOC_RANGE_380___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_380__RX_DCOC_RES_I_380___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_380__RX_DCOC_RES_I_380___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_380__RX_DCOC_RES_Q_380___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_380__RX_DCOC_RES_Q_380___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_380___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_380___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_381 (0x005F45F4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_381___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_381___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_381__RX_DCOC_RANGE_381___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_381__RX_DCOC_RES_I_381___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_381__RX_DCOC_RES_Q_381___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_381__RX_DCOC_RANGE_381___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_381__RX_DCOC_RANGE_381___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_381__RX_DCOC_RES_I_381___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_381__RX_DCOC_RES_I_381___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_381__RX_DCOC_RES_Q_381___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_381__RX_DCOC_RES_Q_381___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_381___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_381___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_382 (0x005F45F8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_382___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_382___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_382__RX_DCOC_RANGE_382___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_382__RX_DCOC_RES_I_382___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_382__RX_DCOC_RES_Q_382___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_382__RX_DCOC_RANGE_382___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_382__RX_DCOC_RANGE_382___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_382__RX_DCOC_RES_I_382___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_382__RX_DCOC_RES_I_382___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_382__RX_DCOC_RES_Q_382___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_382__RX_DCOC_RES_Q_382___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_382___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_382___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_383 (0x005F45FC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_383___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_383___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_383__RX_DCOC_RANGE_383___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_383__RX_DCOC_RES_I_383___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_383__RX_DCOC_RES_Q_383___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_383__RX_DCOC_RANGE_383___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_383__RX_DCOC_RANGE_383___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_383__RX_DCOC_RES_I_383___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_383__RX_DCOC_RES_I_383___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_383__RX_DCOC_RES_Q_383___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_383__RX_DCOC_RES_Q_383___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_383___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_383___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_384 (0x005F4600) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_384___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_384___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_384__RX_DCOC_RANGE_384___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_384__RX_DCOC_RES_I_384___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_384__RX_DCOC_RES_Q_384___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_384__RX_DCOC_RANGE_384___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_384__RX_DCOC_RANGE_384___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_384__RX_DCOC_RES_I_384___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_384__RX_DCOC_RES_I_384___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_384__RX_DCOC_RES_Q_384___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_384__RX_DCOC_RES_Q_384___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_384___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_384___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_385 (0x005F4604) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_385___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_385___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_385__RX_DCOC_RANGE_385___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_385__RX_DCOC_RES_I_385___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_385__RX_DCOC_RES_Q_385___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_385__RX_DCOC_RANGE_385___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_385__RX_DCOC_RANGE_385___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_385__RX_DCOC_RES_I_385___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_385__RX_DCOC_RES_I_385___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_385__RX_DCOC_RES_Q_385___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_385__RX_DCOC_RES_Q_385___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_385___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_385___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_386 (0x005F4608) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_386___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_386___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_386__RX_DCOC_RANGE_386___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_386__RX_DCOC_RES_I_386___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_386__RX_DCOC_RES_Q_386___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_386__RX_DCOC_RANGE_386___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_386__RX_DCOC_RANGE_386___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_386__RX_DCOC_RES_I_386___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_386__RX_DCOC_RES_I_386___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_386__RX_DCOC_RES_Q_386___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_386__RX_DCOC_RES_Q_386___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_386___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_386___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_387 (0x005F460C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_387___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_387___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_387__RX_DCOC_RANGE_387___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_387__RX_DCOC_RES_I_387___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_387__RX_DCOC_RES_Q_387___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_387__RX_DCOC_RANGE_387___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_387__RX_DCOC_RANGE_387___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_387__RX_DCOC_RES_I_387___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_387__RX_DCOC_RES_I_387___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_387__RX_DCOC_RES_Q_387___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_387__RX_DCOC_RES_Q_387___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_387___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_387___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_388 (0x005F4610) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_388___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_388___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_388__RX_DCOC_RANGE_388___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_388__RX_DCOC_RES_I_388___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_388__RX_DCOC_RES_Q_388___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_388__RX_DCOC_RANGE_388___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_388__RX_DCOC_RANGE_388___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_388__RX_DCOC_RES_I_388___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_388__RX_DCOC_RES_I_388___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_388__RX_DCOC_RES_Q_388___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_388__RX_DCOC_RES_Q_388___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_388___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_388___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_389 (0x005F4614) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_389___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_389___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_389__RX_DCOC_RANGE_389___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_389__RX_DCOC_RES_I_389___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_389__RX_DCOC_RES_Q_389___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_389__RX_DCOC_RANGE_389___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_389__RX_DCOC_RANGE_389___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_389__RX_DCOC_RES_I_389___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_389__RX_DCOC_RES_I_389___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_389__RX_DCOC_RES_Q_389___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_389__RX_DCOC_RES_Q_389___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_389___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_389___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_390 (0x005F4618) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_390___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_390___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_390__RX_DCOC_RANGE_390___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_390__RX_DCOC_RES_I_390___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_390__RX_DCOC_RES_Q_390___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_390__RX_DCOC_RANGE_390___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_390__RX_DCOC_RANGE_390___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_390__RX_DCOC_RES_I_390___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_390__RX_DCOC_RES_I_390___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_390__RX_DCOC_RES_Q_390___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_390__RX_DCOC_RES_Q_390___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_390___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_390___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_391 (0x005F461C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_391___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_391___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_391__RX_DCOC_RANGE_391___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_391__RX_DCOC_RES_I_391___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_391__RX_DCOC_RES_Q_391___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_391__RX_DCOC_RANGE_391___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_391__RX_DCOC_RANGE_391___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_391__RX_DCOC_RES_I_391___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_391__RX_DCOC_RES_I_391___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_391__RX_DCOC_RES_Q_391___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_391__RX_DCOC_RES_Q_391___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_391___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_391___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_392 (0x005F4620) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_392___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_392___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_392__RX_DCOC_RANGE_392___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_392__RX_DCOC_RES_I_392___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_392__RX_DCOC_RES_Q_392___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_392__RX_DCOC_RANGE_392___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_392__RX_DCOC_RANGE_392___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_392__RX_DCOC_RES_I_392___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_392__RX_DCOC_RES_I_392___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_392__RX_DCOC_RES_Q_392___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_392__RX_DCOC_RES_Q_392___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_392___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_392___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_393 (0x005F4624) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_393___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_393___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_393__RX_DCOC_RANGE_393___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_393__RX_DCOC_RES_I_393___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_393__RX_DCOC_RES_Q_393___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_393__RX_DCOC_RANGE_393___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_393__RX_DCOC_RANGE_393___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_393__RX_DCOC_RES_I_393___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_393__RX_DCOC_RES_I_393___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_393__RX_DCOC_RES_Q_393___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_393__RX_DCOC_RES_Q_393___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_393___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_393___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_394 (0x005F4628) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_394___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_394___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_394__RX_DCOC_RANGE_394___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_394__RX_DCOC_RES_I_394___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_394__RX_DCOC_RES_Q_394___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_394__RX_DCOC_RANGE_394___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_394__RX_DCOC_RANGE_394___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_394__RX_DCOC_RES_I_394___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_394__RX_DCOC_RES_I_394___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_394__RX_DCOC_RES_Q_394___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_394__RX_DCOC_RES_Q_394___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_394___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_394___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_395 (0x005F462C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_395___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_395___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_395__RX_DCOC_RANGE_395___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_395__RX_DCOC_RES_I_395___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_395__RX_DCOC_RES_Q_395___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_395__RX_DCOC_RANGE_395___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_395__RX_DCOC_RANGE_395___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_395__RX_DCOC_RES_I_395___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_395__RX_DCOC_RES_I_395___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_395__RX_DCOC_RES_Q_395___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_395__RX_DCOC_RES_Q_395___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_395___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_395___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_396 (0x005F4630) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_396___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_396___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_396__RX_DCOC_RANGE_396___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_396__RX_DCOC_RES_I_396___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_396__RX_DCOC_RES_Q_396___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_396__RX_DCOC_RANGE_396___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_396__RX_DCOC_RANGE_396___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_396__RX_DCOC_RES_I_396___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_396__RX_DCOC_RES_I_396___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_396__RX_DCOC_RES_Q_396___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_396__RX_DCOC_RES_Q_396___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_396___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_396___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_397 (0x005F4634) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_397___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_397___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_397__RX_DCOC_RANGE_397___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_397__RX_DCOC_RES_I_397___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_397__RX_DCOC_RES_Q_397___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_397__RX_DCOC_RANGE_397___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_397__RX_DCOC_RANGE_397___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_397__RX_DCOC_RES_I_397___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_397__RX_DCOC_RES_I_397___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_397__RX_DCOC_RES_Q_397___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_397__RX_DCOC_RES_Q_397___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_397___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_397___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_398 (0x005F4638) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_398___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_398___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_398__RX_DCOC_RANGE_398___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_398__RX_DCOC_RES_I_398___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_398__RX_DCOC_RES_Q_398___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_398__RX_DCOC_RANGE_398___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_398__RX_DCOC_RANGE_398___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_398__RX_DCOC_RES_I_398___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_398__RX_DCOC_RES_I_398___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_398__RX_DCOC_RES_Q_398___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_398__RX_DCOC_RES_Q_398___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_398___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_398___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_399 (0x005F463C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_399___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_399___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_399__RX_DCOC_RANGE_399___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_399__RX_DCOC_RES_I_399___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_399__RX_DCOC_RES_Q_399___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_399__RX_DCOC_RANGE_399___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_399__RX_DCOC_RANGE_399___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_399__RX_DCOC_RES_I_399___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_399__RX_DCOC_RES_I_399___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_399__RX_DCOC_RES_Q_399___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_399__RX_DCOC_RES_Q_399___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_399___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_399___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_400 (0x005F4640) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_400___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_400___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_400__RX_DCOC_RANGE_400___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_400__RX_DCOC_RES_I_400___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_400__RX_DCOC_RES_Q_400___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_400__RX_DCOC_RANGE_400___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_400__RX_DCOC_RANGE_400___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_400__RX_DCOC_RES_I_400___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_400__RX_DCOC_RES_I_400___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_400__RX_DCOC_RES_Q_400___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_400__RX_DCOC_RES_Q_400___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_400___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_400___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_401 (0x005F4644) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_401___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_401___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_401__RX_DCOC_RANGE_401___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_401__RX_DCOC_RES_I_401___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_401__RX_DCOC_RES_Q_401___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_401__RX_DCOC_RANGE_401___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_401__RX_DCOC_RANGE_401___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_401__RX_DCOC_RES_I_401___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_401__RX_DCOC_RES_I_401___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_401__RX_DCOC_RES_Q_401___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_401__RX_DCOC_RES_Q_401___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_401___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_401___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_402 (0x005F4648) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_402___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_402___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_402__RX_DCOC_RANGE_402___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_402__RX_DCOC_RES_I_402___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_402__RX_DCOC_RES_Q_402___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_402__RX_DCOC_RANGE_402___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_402__RX_DCOC_RANGE_402___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_402__RX_DCOC_RES_I_402___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_402__RX_DCOC_RES_I_402___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_402__RX_DCOC_RES_Q_402___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_402__RX_DCOC_RES_Q_402___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_402___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_402___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_403 (0x005F464C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_403___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_403___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_403__RX_DCOC_RANGE_403___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_403__RX_DCOC_RES_I_403___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_403__RX_DCOC_RES_Q_403___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_403__RX_DCOC_RANGE_403___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_403__RX_DCOC_RANGE_403___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_403__RX_DCOC_RES_I_403___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_403__RX_DCOC_RES_I_403___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_403__RX_DCOC_RES_Q_403___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_403__RX_DCOC_RES_Q_403___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_403___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_403___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_404 (0x005F4650) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_404___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_404___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_404__RX_DCOC_RANGE_404___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_404__RX_DCOC_RES_I_404___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_404__RX_DCOC_RES_Q_404___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_404__RX_DCOC_RANGE_404___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_404__RX_DCOC_RANGE_404___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_404__RX_DCOC_RES_I_404___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_404__RX_DCOC_RES_I_404___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_404__RX_DCOC_RES_Q_404___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_404__RX_DCOC_RES_Q_404___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_404___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_404___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_405 (0x005F4654) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_405___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_405___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_405__RX_DCOC_RANGE_405___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_405__RX_DCOC_RES_I_405___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_405__RX_DCOC_RES_Q_405___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_405__RX_DCOC_RANGE_405___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_405__RX_DCOC_RANGE_405___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_405__RX_DCOC_RES_I_405___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_405__RX_DCOC_RES_I_405___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_405__RX_DCOC_RES_Q_405___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_405__RX_DCOC_RES_Q_405___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_405___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_405___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_406 (0x005F4658) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_406___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_406___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_406__RX_DCOC_RANGE_406___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_406__RX_DCOC_RES_I_406___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_406__RX_DCOC_RES_Q_406___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_406__RX_DCOC_RANGE_406___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_406__RX_DCOC_RANGE_406___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_406__RX_DCOC_RES_I_406___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_406__RX_DCOC_RES_I_406___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_406__RX_DCOC_RES_Q_406___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_406__RX_DCOC_RES_Q_406___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_406___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_406___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_407 (0x005F465C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_407___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_407___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_407__RX_DCOC_RANGE_407___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_407__RX_DCOC_RES_I_407___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_407__RX_DCOC_RES_Q_407___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_407__RX_DCOC_RANGE_407___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_407__RX_DCOC_RANGE_407___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_407__RX_DCOC_RES_I_407___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_407__RX_DCOC_RES_I_407___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_407__RX_DCOC_RES_Q_407___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_407__RX_DCOC_RES_Q_407___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_407___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_407___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_408 (0x005F4660) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_408___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_408___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_408__RX_DCOC_RANGE_408___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_408__RX_DCOC_RES_I_408___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_408__RX_DCOC_RES_Q_408___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_408__RX_DCOC_RANGE_408___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_408__RX_DCOC_RANGE_408___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_408__RX_DCOC_RES_I_408___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_408__RX_DCOC_RES_I_408___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_408__RX_DCOC_RES_Q_408___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_408__RX_DCOC_RES_Q_408___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_408___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_408___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_409 (0x005F4664) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_409___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_409___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_409__RX_DCOC_RANGE_409___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_409__RX_DCOC_RES_I_409___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_409__RX_DCOC_RES_Q_409___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_409__RX_DCOC_RANGE_409___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_409__RX_DCOC_RANGE_409___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_409__RX_DCOC_RES_I_409___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_409__RX_DCOC_RES_I_409___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_409__RX_DCOC_RES_Q_409___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_409__RX_DCOC_RES_Q_409___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_409___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_409___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_410 (0x005F4668) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_410___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_410___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_410__RX_DCOC_RANGE_410___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_410__RX_DCOC_RES_I_410___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_410__RX_DCOC_RES_Q_410___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_410__RX_DCOC_RANGE_410___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_410__RX_DCOC_RANGE_410___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_410__RX_DCOC_RES_I_410___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_410__RX_DCOC_RES_I_410___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_410__RX_DCOC_RES_Q_410___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_410__RX_DCOC_RES_Q_410___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_410___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_410___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_411 (0x005F466C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_411___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_411___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_411__RX_DCOC_RANGE_411___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_411__RX_DCOC_RES_I_411___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_411__RX_DCOC_RES_Q_411___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_411__RX_DCOC_RANGE_411___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_411__RX_DCOC_RANGE_411___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_411__RX_DCOC_RES_I_411___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_411__RX_DCOC_RES_I_411___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_411__RX_DCOC_RES_Q_411___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_411__RX_DCOC_RES_Q_411___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_411___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_411___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_412 (0x005F4670) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_412___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_412___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_412__RX_DCOC_RANGE_412___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_412__RX_DCOC_RES_I_412___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_412__RX_DCOC_RES_Q_412___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_412__RX_DCOC_RANGE_412___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_412__RX_DCOC_RANGE_412___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_412__RX_DCOC_RES_I_412___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_412__RX_DCOC_RES_I_412___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_412__RX_DCOC_RES_Q_412___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_412__RX_DCOC_RES_Q_412___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_412___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_412___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_413 (0x005F4674) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_413___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_413___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_413__RX_DCOC_RANGE_413___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_413__RX_DCOC_RES_I_413___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_413__RX_DCOC_RES_Q_413___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_413__RX_DCOC_RANGE_413___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_413__RX_DCOC_RANGE_413___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_413__RX_DCOC_RES_I_413___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_413__RX_DCOC_RES_I_413___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_413__RX_DCOC_RES_Q_413___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_413__RX_DCOC_RES_Q_413___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_413___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_413___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_414 (0x005F4678) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_414___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_414___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_414__RX_DCOC_RANGE_414___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_414__RX_DCOC_RES_I_414___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_414__RX_DCOC_RES_Q_414___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_414__RX_DCOC_RANGE_414___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_414__RX_DCOC_RANGE_414___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_414__RX_DCOC_RES_I_414___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_414__RX_DCOC_RES_I_414___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_414__RX_DCOC_RES_Q_414___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_414__RX_DCOC_RES_Q_414___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_414___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_414___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_415 (0x005F467C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_415___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_415___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_415__RX_DCOC_RANGE_415___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_415__RX_DCOC_RES_I_415___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_415__RX_DCOC_RES_Q_415___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_415__RX_DCOC_RANGE_415___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_415__RX_DCOC_RANGE_415___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_415__RX_DCOC_RES_I_415___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_415__RX_DCOC_RES_I_415___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_415__RX_DCOC_RES_Q_415___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_415__RX_DCOC_RES_Q_415___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_415___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_415___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_416 (0x005F4680) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_416___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_416___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_416__RX_DCOC_RANGE_416___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_416__RX_DCOC_RES_I_416___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_416__RX_DCOC_RES_Q_416___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_416__RX_DCOC_RANGE_416___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_416__RX_DCOC_RANGE_416___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_416__RX_DCOC_RES_I_416___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_416__RX_DCOC_RES_I_416___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_416__RX_DCOC_RES_Q_416___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_416__RX_DCOC_RES_Q_416___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_416___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_416___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_417 (0x005F4684) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_417___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_417___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_417__RX_DCOC_RANGE_417___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_417__RX_DCOC_RES_I_417___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_417__RX_DCOC_RES_Q_417___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_417__RX_DCOC_RANGE_417___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_417__RX_DCOC_RANGE_417___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_417__RX_DCOC_RES_I_417___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_417__RX_DCOC_RES_I_417___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_417__RX_DCOC_RES_Q_417___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_417__RX_DCOC_RES_Q_417___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_417___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_417___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_418 (0x005F4688) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_418___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_418___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_418__RX_DCOC_RANGE_418___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_418__RX_DCOC_RES_I_418___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_418__RX_DCOC_RES_Q_418___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_418__RX_DCOC_RANGE_418___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_418__RX_DCOC_RANGE_418___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_418__RX_DCOC_RES_I_418___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_418__RX_DCOC_RES_I_418___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_418__RX_DCOC_RES_Q_418___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_418__RX_DCOC_RES_Q_418___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_418___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_418___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_419 (0x005F468C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_419___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_419___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_419__RX_DCOC_RANGE_419___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_419__RX_DCOC_RES_I_419___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_419__RX_DCOC_RES_Q_419___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_419__RX_DCOC_RANGE_419___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_419__RX_DCOC_RANGE_419___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_419__RX_DCOC_RES_I_419___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_419__RX_DCOC_RES_I_419___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_419__RX_DCOC_RES_Q_419___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_419__RX_DCOC_RES_Q_419___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_419___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_419___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_420 (0x005F4690) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_420___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_420___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_420__RX_DCOC_RANGE_420___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_420__RX_DCOC_RES_I_420___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_420__RX_DCOC_RES_Q_420___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_420__RX_DCOC_RANGE_420___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_420__RX_DCOC_RANGE_420___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_420__RX_DCOC_RES_I_420___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_420__RX_DCOC_RES_I_420___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_420__RX_DCOC_RES_Q_420___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_420__RX_DCOC_RES_Q_420___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_420___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_420___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_421 (0x005F4694) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_421___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_421___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_421__RX_DCOC_RANGE_421___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_421__RX_DCOC_RES_I_421___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_421__RX_DCOC_RES_Q_421___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_421__RX_DCOC_RANGE_421___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_421__RX_DCOC_RANGE_421___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_421__RX_DCOC_RES_I_421___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_421__RX_DCOC_RES_I_421___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_421__RX_DCOC_RES_Q_421___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_421__RX_DCOC_RES_Q_421___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_421___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_421___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_422 (0x005F4698) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_422___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_422___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_422__RX_DCOC_RANGE_422___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_422__RX_DCOC_RES_I_422___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_422__RX_DCOC_RES_Q_422___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_422__RX_DCOC_RANGE_422___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_422__RX_DCOC_RANGE_422___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_422__RX_DCOC_RES_I_422___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_422__RX_DCOC_RES_I_422___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_422__RX_DCOC_RES_Q_422___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_422__RX_DCOC_RES_Q_422___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_422___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_422___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_423 (0x005F469C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_423___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_423___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_423__RX_DCOC_RANGE_423___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_423__RX_DCOC_RES_I_423___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_423__RX_DCOC_RES_Q_423___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_423__RX_DCOC_RANGE_423___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_423__RX_DCOC_RANGE_423___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_423__RX_DCOC_RES_I_423___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_423__RX_DCOC_RES_I_423___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_423__RX_DCOC_RES_Q_423___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_423__RX_DCOC_RES_Q_423___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_423___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_423___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_424 (0x005F46A0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_424___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_424___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_424__RX_DCOC_RANGE_424___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_424__RX_DCOC_RES_I_424___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_424__RX_DCOC_RES_Q_424___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_424__RX_DCOC_RANGE_424___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_424__RX_DCOC_RANGE_424___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_424__RX_DCOC_RES_I_424___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_424__RX_DCOC_RES_I_424___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_424__RX_DCOC_RES_Q_424___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_424__RX_DCOC_RES_Q_424___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_424___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_424___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_425 (0x005F46A4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_425___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_425___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_425__RX_DCOC_RANGE_425___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_425__RX_DCOC_RES_I_425___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_425__RX_DCOC_RES_Q_425___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_425__RX_DCOC_RANGE_425___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_425__RX_DCOC_RANGE_425___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_425__RX_DCOC_RES_I_425___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_425__RX_DCOC_RES_I_425___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_425__RX_DCOC_RES_Q_425___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_425__RX_DCOC_RES_Q_425___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_425___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_425___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_426 (0x005F46A8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_426___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_426___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_426__RX_DCOC_RANGE_426___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_426__RX_DCOC_RES_I_426___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_426__RX_DCOC_RES_Q_426___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_426__RX_DCOC_RANGE_426___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_426__RX_DCOC_RANGE_426___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_426__RX_DCOC_RES_I_426___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_426__RX_DCOC_RES_I_426___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_426__RX_DCOC_RES_Q_426___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_426__RX_DCOC_RES_Q_426___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_426___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_426___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_427 (0x005F46AC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_427___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_427___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_427__RX_DCOC_RANGE_427___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_427__RX_DCOC_RES_I_427___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_427__RX_DCOC_RES_Q_427___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_427__RX_DCOC_RANGE_427___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_427__RX_DCOC_RANGE_427___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_427__RX_DCOC_RES_I_427___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_427__RX_DCOC_RES_I_427___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_427__RX_DCOC_RES_Q_427___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_427__RX_DCOC_RES_Q_427___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_427___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_427___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_428 (0x005F46B0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_428___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_428___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_428__RX_DCOC_RANGE_428___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_428__RX_DCOC_RES_I_428___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_428__RX_DCOC_RES_Q_428___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_428__RX_DCOC_RANGE_428___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_428__RX_DCOC_RANGE_428___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_428__RX_DCOC_RES_I_428___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_428__RX_DCOC_RES_I_428___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_428__RX_DCOC_RES_Q_428___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_428__RX_DCOC_RES_Q_428___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_428___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_428___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_429 (0x005F46B4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_429___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_429___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_429__RX_DCOC_RANGE_429___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_429__RX_DCOC_RES_I_429___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_429__RX_DCOC_RES_Q_429___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_429__RX_DCOC_RANGE_429___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_429__RX_DCOC_RANGE_429___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_429__RX_DCOC_RES_I_429___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_429__RX_DCOC_RES_I_429___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_429__RX_DCOC_RES_Q_429___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_429__RX_DCOC_RES_Q_429___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_429___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_429___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_430 (0x005F46B8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_430___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_430___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_430__RX_DCOC_RANGE_430___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_430__RX_DCOC_RES_I_430___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_430__RX_DCOC_RES_Q_430___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_430__RX_DCOC_RANGE_430___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_430__RX_DCOC_RANGE_430___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_430__RX_DCOC_RES_I_430___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_430__RX_DCOC_RES_I_430___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_430__RX_DCOC_RES_Q_430___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_430__RX_DCOC_RES_Q_430___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_430___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_430___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_431 (0x005F46BC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_431___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_431___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_431__RX_DCOC_RANGE_431___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_431__RX_DCOC_RES_I_431___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_431__RX_DCOC_RES_Q_431___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_431__RX_DCOC_RANGE_431___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_431__RX_DCOC_RANGE_431___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_431__RX_DCOC_RES_I_431___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_431__RX_DCOC_RES_I_431___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_431__RX_DCOC_RES_Q_431___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_431__RX_DCOC_RES_Q_431___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_431___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_431___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_432 (0x005F46C0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_432___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_432___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_432__RX_DCOC_RANGE_432___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_432__RX_DCOC_RES_I_432___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_432__RX_DCOC_RES_Q_432___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_432__RX_DCOC_RANGE_432___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_432__RX_DCOC_RANGE_432___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_432__RX_DCOC_RES_I_432___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_432__RX_DCOC_RES_I_432___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_432__RX_DCOC_RES_Q_432___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_432__RX_DCOC_RES_Q_432___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_432___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_432___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_433 (0x005F46C4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_433___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_433___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_433__RX_DCOC_RANGE_433___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_433__RX_DCOC_RES_I_433___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_433__RX_DCOC_RES_Q_433___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_433__RX_DCOC_RANGE_433___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_433__RX_DCOC_RANGE_433___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_433__RX_DCOC_RES_I_433___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_433__RX_DCOC_RES_I_433___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_433__RX_DCOC_RES_Q_433___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_433__RX_DCOC_RES_Q_433___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_433___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_433___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_434 (0x005F46C8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_434___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_434___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_434__RX_DCOC_RANGE_434___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_434__RX_DCOC_RES_I_434___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_434__RX_DCOC_RES_Q_434___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_434__RX_DCOC_RANGE_434___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_434__RX_DCOC_RANGE_434___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_434__RX_DCOC_RES_I_434___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_434__RX_DCOC_RES_I_434___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_434__RX_DCOC_RES_Q_434___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_434__RX_DCOC_RES_Q_434___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_434___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_434___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_435 (0x005F46CC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_435___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_435___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_435__RX_DCOC_RANGE_435___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_435__RX_DCOC_RES_I_435___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_435__RX_DCOC_RES_Q_435___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_435__RX_DCOC_RANGE_435___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_435__RX_DCOC_RANGE_435___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_435__RX_DCOC_RES_I_435___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_435__RX_DCOC_RES_I_435___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_435__RX_DCOC_RES_Q_435___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_435__RX_DCOC_RES_Q_435___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_435___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_435___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_436 (0x005F46D0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_436___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_436___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_436__RX_DCOC_RANGE_436___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_436__RX_DCOC_RES_I_436___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_436__RX_DCOC_RES_Q_436___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_436__RX_DCOC_RANGE_436___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_436__RX_DCOC_RANGE_436___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_436__RX_DCOC_RES_I_436___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_436__RX_DCOC_RES_I_436___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_436__RX_DCOC_RES_Q_436___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_436__RX_DCOC_RES_Q_436___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_436___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_436___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_437 (0x005F46D4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_437___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_437___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_437__RX_DCOC_RANGE_437___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_437__RX_DCOC_RES_I_437___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_437__RX_DCOC_RES_Q_437___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_437__RX_DCOC_RANGE_437___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_437__RX_DCOC_RANGE_437___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_437__RX_DCOC_RES_I_437___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_437__RX_DCOC_RES_I_437___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_437__RX_DCOC_RES_Q_437___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_437__RX_DCOC_RES_Q_437___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_437___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_437___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_438 (0x005F46D8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_438___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_438___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_438__RX_DCOC_RANGE_438___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_438__RX_DCOC_RES_I_438___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_438__RX_DCOC_RES_Q_438___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_438__RX_DCOC_RANGE_438___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_438__RX_DCOC_RANGE_438___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_438__RX_DCOC_RES_I_438___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_438__RX_DCOC_RES_I_438___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_438__RX_DCOC_RES_Q_438___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_438__RX_DCOC_RES_Q_438___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_438___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_438___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_439 (0x005F46DC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_439___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_439___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_439__RX_DCOC_RANGE_439___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_439__RX_DCOC_RES_I_439___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_439__RX_DCOC_RES_Q_439___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_439__RX_DCOC_RANGE_439___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_439__RX_DCOC_RANGE_439___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_439__RX_DCOC_RES_I_439___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_439__RX_DCOC_RES_I_439___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_439__RX_DCOC_RES_Q_439___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_439__RX_DCOC_RES_Q_439___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_439___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_439___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_440 (0x005F46E0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_440___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_440___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_440__RX_DCOC_RANGE_440___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_440__RX_DCOC_RES_I_440___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_440__RX_DCOC_RES_Q_440___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_440__RX_DCOC_RANGE_440___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_440__RX_DCOC_RANGE_440___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_440__RX_DCOC_RES_I_440___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_440__RX_DCOC_RES_I_440___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_440__RX_DCOC_RES_Q_440___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_440__RX_DCOC_RES_Q_440___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_440___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_440___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_441 (0x005F46E4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_441___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_441___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_441__RX_DCOC_RANGE_441___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_441__RX_DCOC_RES_I_441___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_441__RX_DCOC_RES_Q_441___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_441__RX_DCOC_RANGE_441___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_441__RX_DCOC_RANGE_441___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_441__RX_DCOC_RES_I_441___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_441__RX_DCOC_RES_I_441___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_441__RX_DCOC_RES_Q_441___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_441__RX_DCOC_RES_Q_441___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_441___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_441___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_442 (0x005F46E8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_442___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_442___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_442__RX_DCOC_RANGE_442___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_442__RX_DCOC_RES_I_442___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_442__RX_DCOC_RES_Q_442___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_442__RX_DCOC_RANGE_442___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_442__RX_DCOC_RANGE_442___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_442__RX_DCOC_RES_I_442___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_442__RX_DCOC_RES_I_442___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_442__RX_DCOC_RES_Q_442___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_442__RX_DCOC_RES_Q_442___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_442___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_442___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_443 (0x005F46EC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_443___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_443___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_443__RX_DCOC_RANGE_443___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_443__RX_DCOC_RES_I_443___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_443__RX_DCOC_RES_Q_443___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_443__RX_DCOC_RANGE_443___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_443__RX_DCOC_RANGE_443___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_443__RX_DCOC_RES_I_443___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_443__RX_DCOC_RES_I_443___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_443__RX_DCOC_RES_Q_443___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_443__RX_DCOC_RES_Q_443___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_443___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_443___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_444 (0x005F46F0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_444___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_444___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_444__RX_DCOC_RANGE_444___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_444__RX_DCOC_RES_I_444___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_444__RX_DCOC_RES_Q_444___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_444__RX_DCOC_RANGE_444___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_444__RX_DCOC_RANGE_444___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_444__RX_DCOC_RES_I_444___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_444__RX_DCOC_RES_I_444___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_444__RX_DCOC_RES_Q_444___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_444__RX_DCOC_RES_Q_444___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_444___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_444___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_445 (0x005F46F4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_445___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_445___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_445__RX_DCOC_RANGE_445___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_445__RX_DCOC_RES_I_445___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_445__RX_DCOC_RES_Q_445___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_445__RX_DCOC_RANGE_445___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_445__RX_DCOC_RANGE_445___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_445__RX_DCOC_RES_I_445___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_445__RX_DCOC_RES_I_445___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_445__RX_DCOC_RES_Q_445___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_445__RX_DCOC_RES_Q_445___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_445___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_445___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_446 (0x005F46F8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_446___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_446___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_446__RX_DCOC_RANGE_446___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_446__RX_DCOC_RES_I_446___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_446__RX_DCOC_RES_Q_446___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_446__RX_DCOC_RANGE_446___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_446__RX_DCOC_RANGE_446___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_446__RX_DCOC_RES_I_446___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_446__RX_DCOC_RES_I_446___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_446__RX_DCOC_RES_Q_446___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_446__RX_DCOC_RES_Q_446___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_446___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_446___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_447 (0x005F46FC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_447___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_447___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_447__RX_DCOC_RANGE_447___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_447__RX_DCOC_RES_I_447___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_447__RX_DCOC_RES_Q_447___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_447__RX_DCOC_RANGE_447___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_447__RX_DCOC_RANGE_447___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_447__RX_DCOC_RES_I_447___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_447__RX_DCOC_RES_I_447___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_447__RX_DCOC_RES_Q_447___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_447__RX_DCOC_RES_Q_447___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_447___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_447___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_448 (0x005F4700) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_448___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_448___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_448__RX_DCOC_RANGE_448___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_448__RX_DCOC_RES_I_448___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_448__RX_DCOC_RES_Q_448___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_448__RX_DCOC_RANGE_448___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_448__RX_DCOC_RANGE_448___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_448__RX_DCOC_RES_I_448___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_448__RX_DCOC_RES_I_448___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_448__RX_DCOC_RES_Q_448___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_448__RX_DCOC_RES_Q_448___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_448___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_448___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_449 (0x005F4704) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_449___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_449___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_449__RX_DCOC_RANGE_449___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_449__RX_DCOC_RES_I_449___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_449__RX_DCOC_RES_Q_449___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_449__RX_DCOC_RANGE_449___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_449__RX_DCOC_RANGE_449___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_449__RX_DCOC_RES_I_449___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_449__RX_DCOC_RES_I_449___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_449__RX_DCOC_RES_Q_449___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_449__RX_DCOC_RES_Q_449___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_449___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_449___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_450 (0x005F4708) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_450___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_450___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_450__RX_DCOC_RANGE_450___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_450__RX_DCOC_RES_I_450___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_450__RX_DCOC_RES_Q_450___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_450__RX_DCOC_RANGE_450___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_450__RX_DCOC_RANGE_450___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_450__RX_DCOC_RES_I_450___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_450__RX_DCOC_RES_I_450___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_450__RX_DCOC_RES_Q_450___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_450__RX_DCOC_RES_Q_450___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_450___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_450___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_451 (0x005F470C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_451___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_451___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_451__RX_DCOC_RANGE_451___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_451__RX_DCOC_RES_I_451___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_451__RX_DCOC_RES_Q_451___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_451__RX_DCOC_RANGE_451___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_451__RX_DCOC_RANGE_451___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_451__RX_DCOC_RES_I_451___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_451__RX_DCOC_RES_I_451___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_451__RX_DCOC_RES_Q_451___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_451__RX_DCOC_RES_Q_451___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_451___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_451___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_452 (0x005F4710) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_452___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_452___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_452__RX_DCOC_RANGE_452___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_452__RX_DCOC_RES_I_452___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_452__RX_DCOC_RES_Q_452___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_452__RX_DCOC_RANGE_452___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_452__RX_DCOC_RANGE_452___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_452__RX_DCOC_RES_I_452___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_452__RX_DCOC_RES_I_452___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_452__RX_DCOC_RES_Q_452___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_452__RX_DCOC_RES_Q_452___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_452___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_452___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_453 (0x005F4714) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_453___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_453___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_453__RX_DCOC_RANGE_453___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_453__RX_DCOC_RES_I_453___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_453__RX_DCOC_RES_Q_453___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_453__RX_DCOC_RANGE_453___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_453__RX_DCOC_RANGE_453___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_453__RX_DCOC_RES_I_453___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_453__RX_DCOC_RES_I_453___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_453__RX_DCOC_RES_Q_453___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_453__RX_DCOC_RES_Q_453___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_453___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_453___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_454 (0x005F4718) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_454___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_454___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_454__RX_DCOC_RANGE_454___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_454__RX_DCOC_RES_I_454___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_454__RX_DCOC_RES_Q_454___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_454__RX_DCOC_RANGE_454___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_454__RX_DCOC_RANGE_454___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_454__RX_DCOC_RES_I_454___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_454__RX_DCOC_RES_I_454___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_454__RX_DCOC_RES_Q_454___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_454__RX_DCOC_RES_Q_454___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_454___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_454___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_455 (0x005F471C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_455___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_455___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_455__RX_DCOC_RANGE_455___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_455__RX_DCOC_RES_I_455___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_455__RX_DCOC_RES_Q_455___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_455__RX_DCOC_RANGE_455___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_455__RX_DCOC_RANGE_455___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_455__RX_DCOC_RES_I_455___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_455__RX_DCOC_RES_I_455___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_455__RX_DCOC_RES_Q_455___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_455__RX_DCOC_RES_Q_455___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_455___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_455___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_456 (0x005F4720) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_456___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_456___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_456__RX_DCOC_RANGE_456___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_456__RX_DCOC_RES_I_456___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_456__RX_DCOC_RES_Q_456___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_456__RX_DCOC_RANGE_456___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_456__RX_DCOC_RANGE_456___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_456__RX_DCOC_RES_I_456___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_456__RX_DCOC_RES_I_456___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_456__RX_DCOC_RES_Q_456___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_456__RX_DCOC_RES_Q_456___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_456___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_456___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_457 (0x005F4724) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_457___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_457___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_457__RX_DCOC_RANGE_457___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_457__RX_DCOC_RES_I_457___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_457__RX_DCOC_RES_Q_457___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_457__RX_DCOC_RANGE_457___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_457__RX_DCOC_RANGE_457___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_457__RX_DCOC_RES_I_457___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_457__RX_DCOC_RES_I_457___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_457__RX_DCOC_RES_Q_457___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_457__RX_DCOC_RES_Q_457___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_457___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_457___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_458 (0x005F4728) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_458___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_458___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_458__RX_DCOC_RANGE_458___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_458__RX_DCOC_RES_I_458___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_458__RX_DCOC_RES_Q_458___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_458__RX_DCOC_RANGE_458___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_458__RX_DCOC_RANGE_458___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_458__RX_DCOC_RES_I_458___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_458__RX_DCOC_RES_I_458___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_458__RX_DCOC_RES_Q_458___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_458__RX_DCOC_RES_Q_458___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_458___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_458___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_459 (0x005F472C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_459___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_459___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_459__RX_DCOC_RANGE_459___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_459__RX_DCOC_RES_I_459___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_459__RX_DCOC_RES_Q_459___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_459__RX_DCOC_RANGE_459___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_459__RX_DCOC_RANGE_459___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_459__RX_DCOC_RES_I_459___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_459__RX_DCOC_RES_I_459___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_459__RX_DCOC_RES_Q_459___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_459__RX_DCOC_RES_Q_459___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_459___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_459___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_460 (0x005F4730) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_460___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_460___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_460__RX_DCOC_RANGE_460___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_460__RX_DCOC_RES_I_460___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_460__RX_DCOC_RES_Q_460___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_460__RX_DCOC_RANGE_460___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_460__RX_DCOC_RANGE_460___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_460__RX_DCOC_RES_I_460___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_460__RX_DCOC_RES_I_460___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_460__RX_DCOC_RES_Q_460___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_460__RX_DCOC_RES_Q_460___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_460___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_460___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_461 (0x005F4734) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_461___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_461___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_461__RX_DCOC_RANGE_461___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_461__RX_DCOC_RES_I_461___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_461__RX_DCOC_RES_Q_461___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_461__RX_DCOC_RANGE_461___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_461__RX_DCOC_RANGE_461___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_461__RX_DCOC_RES_I_461___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_461__RX_DCOC_RES_I_461___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_461__RX_DCOC_RES_Q_461___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_461__RX_DCOC_RES_Q_461___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_461___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_461___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_462 (0x005F4738) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_462___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_462___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_462__RX_DCOC_RANGE_462___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_462__RX_DCOC_RES_I_462___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_462__RX_DCOC_RES_Q_462___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_462__RX_DCOC_RANGE_462___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_462__RX_DCOC_RANGE_462___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_462__RX_DCOC_RES_I_462___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_462__RX_DCOC_RES_I_462___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_462__RX_DCOC_RES_Q_462___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_462__RX_DCOC_RES_Q_462___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_462___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_462___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_463 (0x005F473C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_463___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_463___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_463__RX_DCOC_RANGE_463___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_463__RX_DCOC_RES_I_463___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_463__RX_DCOC_RES_Q_463___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_463__RX_DCOC_RANGE_463___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_463__RX_DCOC_RANGE_463___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_463__RX_DCOC_RES_I_463___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_463__RX_DCOC_RES_I_463___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_463__RX_DCOC_RES_Q_463___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_463__RX_DCOC_RES_Q_463___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_463___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_463___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_464 (0x005F4740) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_464___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_464___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_464__RX_DCOC_RANGE_464___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_464__RX_DCOC_RES_I_464___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_464__RX_DCOC_RES_Q_464___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_464__RX_DCOC_RANGE_464___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_464__RX_DCOC_RANGE_464___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_464__RX_DCOC_RES_I_464___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_464__RX_DCOC_RES_I_464___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_464__RX_DCOC_RES_Q_464___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_464__RX_DCOC_RES_Q_464___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_464___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_464___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_465 (0x005F4744) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_465___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_465___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_465__RX_DCOC_RANGE_465___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_465__RX_DCOC_RES_I_465___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_465__RX_DCOC_RES_Q_465___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_465__RX_DCOC_RANGE_465___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_465__RX_DCOC_RANGE_465___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_465__RX_DCOC_RES_I_465___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_465__RX_DCOC_RES_I_465___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_465__RX_DCOC_RES_Q_465___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_465__RX_DCOC_RES_Q_465___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_465___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_465___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_466 (0x005F4748) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_466___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_466___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_466__RX_DCOC_RANGE_466___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_466__RX_DCOC_RES_I_466___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_466__RX_DCOC_RES_Q_466___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_466__RX_DCOC_RANGE_466___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_466__RX_DCOC_RANGE_466___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_466__RX_DCOC_RES_I_466___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_466__RX_DCOC_RES_I_466___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_466__RX_DCOC_RES_Q_466___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_466__RX_DCOC_RES_Q_466___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_466___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_466___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_467 (0x005F474C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_467___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_467___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_467__RX_DCOC_RANGE_467___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_467__RX_DCOC_RES_I_467___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_467__RX_DCOC_RES_Q_467___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_467__RX_DCOC_RANGE_467___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_467__RX_DCOC_RANGE_467___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_467__RX_DCOC_RES_I_467___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_467__RX_DCOC_RES_I_467___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_467__RX_DCOC_RES_Q_467___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_467__RX_DCOC_RES_Q_467___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_467___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_467___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_468 (0x005F4750) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_468___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_468___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_468__RX_DCOC_RANGE_468___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_468__RX_DCOC_RES_I_468___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_468__RX_DCOC_RES_Q_468___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_468__RX_DCOC_RANGE_468___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_468__RX_DCOC_RANGE_468___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_468__RX_DCOC_RES_I_468___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_468__RX_DCOC_RES_I_468___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_468__RX_DCOC_RES_Q_468___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_468__RX_DCOC_RES_Q_468___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_468___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_468___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_469 (0x005F4754) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_469___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_469___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_469__RX_DCOC_RANGE_469___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_469__RX_DCOC_RES_I_469___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_469__RX_DCOC_RES_Q_469___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_469__RX_DCOC_RANGE_469___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_469__RX_DCOC_RANGE_469___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_469__RX_DCOC_RES_I_469___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_469__RX_DCOC_RES_I_469___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_469__RX_DCOC_RES_Q_469___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_469__RX_DCOC_RES_Q_469___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_469___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_469___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_470 (0x005F4758) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_470___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_470___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_470__RX_DCOC_RANGE_470___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_470__RX_DCOC_RES_I_470___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_470__RX_DCOC_RES_Q_470___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_470__RX_DCOC_RANGE_470___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_470__RX_DCOC_RANGE_470___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_470__RX_DCOC_RES_I_470___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_470__RX_DCOC_RES_I_470___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_470__RX_DCOC_RES_Q_470___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_470__RX_DCOC_RES_Q_470___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_470___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_470___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_471 (0x005F475C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_471___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_471___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_471__RX_DCOC_RANGE_471___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_471__RX_DCOC_RES_I_471___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_471__RX_DCOC_RES_Q_471___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_471__RX_DCOC_RANGE_471___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_471__RX_DCOC_RANGE_471___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_471__RX_DCOC_RES_I_471___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_471__RX_DCOC_RES_I_471___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_471__RX_DCOC_RES_Q_471___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_471__RX_DCOC_RES_Q_471___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_471___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_471___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_472 (0x005F4760) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_472___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_472___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_472__RX_DCOC_RANGE_472___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_472__RX_DCOC_RES_I_472___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_472__RX_DCOC_RES_Q_472___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_472__RX_DCOC_RANGE_472___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_472__RX_DCOC_RANGE_472___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_472__RX_DCOC_RES_I_472___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_472__RX_DCOC_RES_I_472___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_472__RX_DCOC_RES_Q_472___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_472__RX_DCOC_RES_Q_472___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_472___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_472___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_473 (0x005F4764) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_473___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_473___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_473__RX_DCOC_RANGE_473___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_473__RX_DCOC_RES_I_473___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_473__RX_DCOC_RES_Q_473___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_473__RX_DCOC_RANGE_473___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_473__RX_DCOC_RANGE_473___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_473__RX_DCOC_RES_I_473___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_473__RX_DCOC_RES_I_473___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_473__RX_DCOC_RES_Q_473___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_473__RX_DCOC_RES_Q_473___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_473___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_473___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_474 (0x005F4768) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_474___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_474___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_474__RX_DCOC_RANGE_474___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_474__RX_DCOC_RES_I_474___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_474__RX_DCOC_RES_Q_474___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_474__RX_DCOC_RANGE_474___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_474__RX_DCOC_RANGE_474___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_474__RX_DCOC_RES_I_474___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_474__RX_DCOC_RES_I_474___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_474__RX_DCOC_RES_Q_474___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_474__RX_DCOC_RES_Q_474___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_474___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_474___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_475 (0x005F476C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_475___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_475___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_475__RX_DCOC_RANGE_475___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_475__RX_DCOC_RES_I_475___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_475__RX_DCOC_RES_Q_475___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_475__RX_DCOC_RANGE_475___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_475__RX_DCOC_RANGE_475___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_475__RX_DCOC_RES_I_475___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_475__RX_DCOC_RES_I_475___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_475__RX_DCOC_RES_Q_475___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_475__RX_DCOC_RES_Q_475___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_475___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_475___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_476 (0x005F4770) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_476___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_476___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_476__RX_DCOC_RANGE_476___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_476__RX_DCOC_RES_I_476___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_476__RX_DCOC_RES_Q_476___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_476__RX_DCOC_RANGE_476___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_476__RX_DCOC_RANGE_476___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_476__RX_DCOC_RES_I_476___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_476__RX_DCOC_RES_I_476___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_476__RX_DCOC_RES_Q_476___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_476__RX_DCOC_RES_Q_476___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_476___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_476___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_477 (0x005F4774) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_477___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_477___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_477__RX_DCOC_RANGE_477___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_477__RX_DCOC_RES_I_477___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_477__RX_DCOC_RES_Q_477___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_477__RX_DCOC_RANGE_477___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_477__RX_DCOC_RANGE_477___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_477__RX_DCOC_RES_I_477___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_477__RX_DCOC_RES_I_477___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_477__RX_DCOC_RES_Q_477___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_477__RX_DCOC_RES_Q_477___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_477___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_477___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_478 (0x005F4778) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_478___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_478___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_478__RX_DCOC_RANGE_478___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_478__RX_DCOC_RES_I_478___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_478__RX_DCOC_RES_Q_478___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_478__RX_DCOC_RANGE_478___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_478__RX_DCOC_RANGE_478___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_478__RX_DCOC_RES_I_478___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_478__RX_DCOC_RES_I_478___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_478__RX_DCOC_RES_Q_478___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_478__RX_DCOC_RES_Q_478___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_478___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_478___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_479 (0x005F477C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_479___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_479___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_479__RX_DCOC_RANGE_479___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_479__RX_DCOC_RES_I_479___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_479__RX_DCOC_RES_Q_479___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_479__RX_DCOC_RANGE_479___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_479__RX_DCOC_RANGE_479___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_479__RX_DCOC_RES_I_479___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_479__RX_DCOC_RES_I_479___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_479__RX_DCOC_RES_Q_479___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_479__RX_DCOC_RES_Q_479___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_479___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_479___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_480 (0x005F4780) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_480___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_480___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_480__RX_DCOC_RANGE_480___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_480__RX_DCOC_RES_I_480___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_480__RX_DCOC_RES_Q_480___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_480__RX_DCOC_RANGE_480___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_480__RX_DCOC_RANGE_480___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_480__RX_DCOC_RES_I_480___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_480__RX_DCOC_RES_I_480___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_480__RX_DCOC_RES_Q_480___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_480__RX_DCOC_RES_Q_480___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_480___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_480___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_481 (0x005F4784) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_481___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_481___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_481__RX_DCOC_RANGE_481___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_481__RX_DCOC_RES_I_481___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_481__RX_DCOC_RES_Q_481___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_481__RX_DCOC_RANGE_481___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_481__RX_DCOC_RANGE_481___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_481__RX_DCOC_RES_I_481___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_481__RX_DCOC_RES_I_481___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_481__RX_DCOC_RES_Q_481___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_481__RX_DCOC_RES_Q_481___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_481___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_481___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_482 (0x005F4788) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_482___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_482___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_482__RX_DCOC_RANGE_482___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_482__RX_DCOC_RES_I_482___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_482__RX_DCOC_RES_Q_482___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_482__RX_DCOC_RANGE_482___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_482__RX_DCOC_RANGE_482___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_482__RX_DCOC_RES_I_482___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_482__RX_DCOC_RES_I_482___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_482__RX_DCOC_RES_Q_482___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_482__RX_DCOC_RES_Q_482___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_482___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_482___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_483 (0x005F478C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_483___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_483___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_483__RX_DCOC_RANGE_483___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_483__RX_DCOC_RES_I_483___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_483__RX_DCOC_RES_Q_483___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_483__RX_DCOC_RANGE_483___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_483__RX_DCOC_RANGE_483___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_483__RX_DCOC_RES_I_483___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_483__RX_DCOC_RES_I_483___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_483__RX_DCOC_RES_Q_483___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_483__RX_DCOC_RES_Q_483___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_483___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_483___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_484 (0x005F4790) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_484___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_484___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_484__RX_DCOC_RANGE_484___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_484__RX_DCOC_RES_I_484___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_484__RX_DCOC_RES_Q_484___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_484__RX_DCOC_RANGE_484___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_484__RX_DCOC_RANGE_484___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_484__RX_DCOC_RES_I_484___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_484__RX_DCOC_RES_I_484___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_484__RX_DCOC_RES_Q_484___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_484__RX_DCOC_RES_Q_484___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_484___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_484___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_485 (0x005F4794) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_485___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_485___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_485__RX_DCOC_RANGE_485___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_485__RX_DCOC_RES_I_485___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_485__RX_DCOC_RES_Q_485___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_485__RX_DCOC_RANGE_485___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_485__RX_DCOC_RANGE_485___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_485__RX_DCOC_RES_I_485___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_485__RX_DCOC_RES_I_485___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_485__RX_DCOC_RES_Q_485___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_485__RX_DCOC_RES_Q_485___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_485___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_485___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_486 (0x005F4798) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_486___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_486___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_486__RX_DCOC_RANGE_486___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_486__RX_DCOC_RES_I_486___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_486__RX_DCOC_RES_Q_486___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_486__RX_DCOC_RANGE_486___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_486__RX_DCOC_RANGE_486___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_486__RX_DCOC_RES_I_486___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_486__RX_DCOC_RES_I_486___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_486__RX_DCOC_RES_Q_486___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_486__RX_DCOC_RES_Q_486___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_486___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_486___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_487 (0x005F479C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_487___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_487___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_487__RX_DCOC_RANGE_487___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_487__RX_DCOC_RES_I_487___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_487__RX_DCOC_RES_Q_487___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_487__RX_DCOC_RANGE_487___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_487__RX_DCOC_RANGE_487___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_487__RX_DCOC_RES_I_487___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_487__RX_DCOC_RES_I_487___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_487__RX_DCOC_RES_Q_487___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_487__RX_DCOC_RES_Q_487___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_487___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_487___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_488 (0x005F47A0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_488___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_488___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_488__RX_DCOC_RANGE_488___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_488__RX_DCOC_RES_I_488___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_488__RX_DCOC_RES_Q_488___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_488__RX_DCOC_RANGE_488___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_488__RX_DCOC_RANGE_488___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_488__RX_DCOC_RES_I_488___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_488__RX_DCOC_RES_I_488___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_488__RX_DCOC_RES_Q_488___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_488__RX_DCOC_RES_Q_488___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_488___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_488___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_489 (0x005F47A4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_489___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_489___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_489__RX_DCOC_RANGE_489___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_489__RX_DCOC_RES_I_489___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_489__RX_DCOC_RES_Q_489___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_489__RX_DCOC_RANGE_489___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_489__RX_DCOC_RANGE_489___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_489__RX_DCOC_RES_I_489___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_489__RX_DCOC_RES_I_489___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_489__RX_DCOC_RES_Q_489___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_489__RX_DCOC_RES_Q_489___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_489___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_489___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_490 (0x005F47A8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_490___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_490___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_490__RX_DCOC_RANGE_490___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_490__RX_DCOC_RES_I_490___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_490__RX_DCOC_RES_Q_490___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_490__RX_DCOC_RANGE_490___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_490__RX_DCOC_RANGE_490___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_490__RX_DCOC_RES_I_490___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_490__RX_DCOC_RES_I_490___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_490__RX_DCOC_RES_Q_490___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_490__RX_DCOC_RES_Q_490___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_490___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_490___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_491 (0x005F47AC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_491___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_491___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_491__RX_DCOC_RANGE_491___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_491__RX_DCOC_RES_I_491___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_491__RX_DCOC_RES_Q_491___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_491__RX_DCOC_RANGE_491___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_491__RX_DCOC_RANGE_491___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_491__RX_DCOC_RES_I_491___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_491__RX_DCOC_RES_I_491___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_491__RX_DCOC_RES_Q_491___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_491__RX_DCOC_RES_Q_491___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_491___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_491___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_492 (0x005F47B0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_492___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_492___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_492__RX_DCOC_RANGE_492___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_492__RX_DCOC_RES_I_492___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_492__RX_DCOC_RES_Q_492___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_492__RX_DCOC_RANGE_492___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_492__RX_DCOC_RANGE_492___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_492__RX_DCOC_RES_I_492___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_492__RX_DCOC_RES_I_492___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_492__RX_DCOC_RES_Q_492___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_492__RX_DCOC_RES_Q_492___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_492___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_492___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_493 (0x005F47B4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_493___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_493___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_493__RX_DCOC_RANGE_493___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_493__RX_DCOC_RES_I_493___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_493__RX_DCOC_RES_Q_493___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_493__RX_DCOC_RANGE_493___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_493__RX_DCOC_RANGE_493___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_493__RX_DCOC_RES_I_493___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_493__RX_DCOC_RES_I_493___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_493__RX_DCOC_RES_Q_493___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_493__RX_DCOC_RES_Q_493___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_493___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_493___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_494 (0x005F47B8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_494___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_494___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_494__RX_DCOC_RANGE_494___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_494__RX_DCOC_RES_I_494___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_494__RX_DCOC_RES_Q_494___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_494__RX_DCOC_RANGE_494___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_494__RX_DCOC_RANGE_494___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_494__RX_DCOC_RES_I_494___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_494__RX_DCOC_RES_I_494___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_494__RX_DCOC_RES_Q_494___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_494__RX_DCOC_RES_Q_494___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_494___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_494___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_495 (0x005F47BC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_495___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_495___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_495__RX_DCOC_RANGE_495___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_495__RX_DCOC_RES_I_495___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_495__RX_DCOC_RES_Q_495___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_495__RX_DCOC_RANGE_495___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_495__RX_DCOC_RANGE_495___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_495__RX_DCOC_RES_I_495___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_495__RX_DCOC_RES_I_495___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_495__RX_DCOC_RES_Q_495___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_495__RX_DCOC_RES_Q_495___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_495___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_495___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_496 (0x005F47C0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_496___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_496___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_496__RX_DCOC_RANGE_496___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_496__RX_DCOC_RES_I_496___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_496__RX_DCOC_RES_Q_496___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_496__RX_DCOC_RANGE_496___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_496__RX_DCOC_RANGE_496___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_496__RX_DCOC_RES_I_496___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_496__RX_DCOC_RES_I_496___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_496__RX_DCOC_RES_Q_496___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_496__RX_DCOC_RES_Q_496___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_496___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_496___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_497 (0x005F47C4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_497___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_497___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_497__RX_DCOC_RANGE_497___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_497__RX_DCOC_RES_I_497___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_497__RX_DCOC_RES_Q_497___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_497__RX_DCOC_RANGE_497___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_497__RX_DCOC_RANGE_497___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_497__RX_DCOC_RES_I_497___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_497__RX_DCOC_RES_I_497___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_497__RX_DCOC_RES_Q_497___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_497__RX_DCOC_RES_Q_497___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_497___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_497___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_498 (0x005F47C8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_498___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_498___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_498__RX_DCOC_RANGE_498___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_498__RX_DCOC_RES_I_498___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_498__RX_DCOC_RES_Q_498___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_498__RX_DCOC_RANGE_498___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_498__RX_DCOC_RANGE_498___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_498__RX_DCOC_RES_I_498___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_498__RX_DCOC_RES_I_498___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_498__RX_DCOC_RES_Q_498___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_498__RX_DCOC_RES_Q_498___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_498___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_498___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_499 (0x005F47CC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_499___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_499___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_499__RX_DCOC_RANGE_499___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_499__RX_DCOC_RES_I_499___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_499__RX_DCOC_RES_Q_499___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_499__RX_DCOC_RANGE_499___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_499__RX_DCOC_RANGE_499___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_499__RX_DCOC_RES_I_499___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_499__RX_DCOC_RES_I_499___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_499__RX_DCOC_RES_Q_499___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_499__RX_DCOC_RES_Q_499___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_499___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_499___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_500 (0x005F47D0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_500___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_500___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_500__RX_DCOC_RANGE_500___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_500__RX_DCOC_RES_I_500___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_500__RX_DCOC_RES_Q_500___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_500__RX_DCOC_RANGE_500___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_500__RX_DCOC_RANGE_500___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_500__RX_DCOC_RES_I_500___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_500__RX_DCOC_RES_I_500___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_500__RX_DCOC_RES_Q_500___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_500__RX_DCOC_RES_Q_500___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_500___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_500___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_501 (0x005F47D4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_501___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_501___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_501__RX_DCOC_RANGE_501___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_501__RX_DCOC_RES_I_501___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_501__RX_DCOC_RES_Q_501___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_501__RX_DCOC_RANGE_501___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_501__RX_DCOC_RANGE_501___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_501__RX_DCOC_RES_I_501___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_501__RX_DCOC_RES_I_501___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_501__RX_DCOC_RES_Q_501___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_501__RX_DCOC_RES_Q_501___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_501___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_501___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_502 (0x005F47D8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_502___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_502___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_502__RX_DCOC_RANGE_502___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_502__RX_DCOC_RES_I_502___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_502__RX_DCOC_RES_Q_502___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_502__RX_DCOC_RANGE_502___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_502__RX_DCOC_RANGE_502___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_502__RX_DCOC_RES_I_502___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_502__RX_DCOC_RES_I_502___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_502__RX_DCOC_RES_Q_502___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_502__RX_DCOC_RES_Q_502___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_502___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_502___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_503 (0x005F47DC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_503___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_503___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_503__RX_DCOC_RANGE_503___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_503__RX_DCOC_RES_I_503___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_503__RX_DCOC_RES_Q_503___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_503__RX_DCOC_RANGE_503___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_503__RX_DCOC_RANGE_503___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_503__RX_DCOC_RES_I_503___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_503__RX_DCOC_RES_I_503___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_503__RX_DCOC_RES_Q_503___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_503__RX_DCOC_RES_Q_503___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_503___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_503___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_504 (0x005F47E0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_504___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_504___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_504__RX_DCOC_RANGE_504___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_504__RX_DCOC_RES_I_504___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_504__RX_DCOC_RES_Q_504___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_504__RX_DCOC_RANGE_504___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_504__RX_DCOC_RANGE_504___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_504__RX_DCOC_RES_I_504___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_504__RX_DCOC_RES_I_504___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_504__RX_DCOC_RES_Q_504___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_504__RX_DCOC_RES_Q_504___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_504___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_504___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_505 (0x005F47E4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_505___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_505___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_505__RX_DCOC_RANGE_505___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_505__RX_DCOC_RES_I_505___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_505__RX_DCOC_RES_Q_505___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_505__RX_DCOC_RANGE_505___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_505__RX_DCOC_RANGE_505___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_505__RX_DCOC_RES_I_505___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_505__RX_DCOC_RES_I_505___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_505__RX_DCOC_RES_Q_505___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_505__RX_DCOC_RES_Q_505___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_505___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_505___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_506 (0x005F47E8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_506___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_506___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_506__RX_DCOC_RANGE_506___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_506__RX_DCOC_RES_I_506___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_506__RX_DCOC_RES_Q_506___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_506__RX_DCOC_RANGE_506___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_506__RX_DCOC_RANGE_506___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_506__RX_DCOC_RES_I_506___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_506__RX_DCOC_RES_I_506___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_506__RX_DCOC_RES_Q_506___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_506__RX_DCOC_RES_Q_506___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_506___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_506___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_507 (0x005F47EC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_507___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_507___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_507__RX_DCOC_RANGE_507___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_507__RX_DCOC_RES_I_507___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_507__RX_DCOC_RES_Q_507___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_507__RX_DCOC_RANGE_507___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_507__RX_DCOC_RANGE_507___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_507__RX_DCOC_RES_I_507___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_507__RX_DCOC_RES_I_507___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_507__RX_DCOC_RES_Q_507___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_507__RX_DCOC_RES_Q_507___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_507___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_507___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_508 (0x005F47F0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_508___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_508___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_508__RX_DCOC_RANGE_508___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_508__RX_DCOC_RES_I_508___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_508__RX_DCOC_RES_Q_508___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_508__RX_DCOC_RANGE_508___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_508__RX_DCOC_RANGE_508___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_508__RX_DCOC_RES_I_508___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_508__RX_DCOC_RES_I_508___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_508__RX_DCOC_RES_Q_508___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_508__RX_DCOC_RES_Q_508___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_508___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_508___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_509 (0x005F47F4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_509___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_509___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_509__RX_DCOC_RANGE_509___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_509__RX_DCOC_RES_I_509___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_509__RX_DCOC_RES_Q_509___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_509__RX_DCOC_RANGE_509___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_509__RX_DCOC_RANGE_509___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_509__RX_DCOC_RES_I_509___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_509__RX_DCOC_RES_I_509___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_509__RX_DCOC_RES_Q_509___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_509__RX_DCOC_RES_Q_509___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_509___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_509___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_510 (0x005F47F8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_510___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_510___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_510__RX_DCOC_RANGE_510___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_510__RX_DCOC_RES_I_510___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_510__RX_DCOC_RES_Q_510___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_510__RX_DCOC_RANGE_510___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_510__RX_DCOC_RANGE_510___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_510__RX_DCOC_RES_I_510___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_510__RX_DCOC_RES_I_510___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_510__RX_DCOC_RES_Q_510___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_510__RX_DCOC_RES_Q_510___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_510___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_510___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_511 (0x005F47FC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_511___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_511___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_511__RX_DCOC_RANGE_511___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_511__RX_DCOC_RES_I_511___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_511__RX_DCOC_RES_Q_511___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_511__RX_DCOC_RANGE_511___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_511__RX_DCOC_RANGE_511___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_511__RX_DCOC_RES_I_511___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_511__RX_DCOC_RES_I_511___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_511__RX_DCOC_RES_Q_511___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_511__RX_DCOC_RES_Q_511___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_511___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_511___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_512 (0x005F4800) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_512___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_512___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_512__RX_DCOC_RANGE_512___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_512__RX_DCOC_RES_I_512___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_512__RX_DCOC_RES_Q_512___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_512__RX_DCOC_RANGE_512___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_512__RX_DCOC_RANGE_512___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_512__RX_DCOC_RES_I_512___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_512__RX_DCOC_RES_I_512___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_512__RX_DCOC_RES_Q_512___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_512__RX_DCOC_RES_Q_512___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_512___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_512___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_513 (0x005F4804) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_513___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_513___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_513__RX_DCOC_RANGE_513___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_513__RX_DCOC_RES_I_513___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_513__RX_DCOC_RES_Q_513___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_513__RX_DCOC_RANGE_513___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_513__RX_DCOC_RANGE_513___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_513__RX_DCOC_RES_I_513___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_513__RX_DCOC_RES_I_513___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_513__RX_DCOC_RES_Q_513___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_513__RX_DCOC_RES_Q_513___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_513___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_513___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_514 (0x005F4808) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_514___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_514___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_514__RX_DCOC_RANGE_514___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_514__RX_DCOC_RES_I_514___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_514__RX_DCOC_RES_Q_514___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_514__RX_DCOC_RANGE_514___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_514__RX_DCOC_RANGE_514___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_514__RX_DCOC_RES_I_514___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_514__RX_DCOC_RES_I_514___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_514__RX_DCOC_RES_Q_514___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_514__RX_DCOC_RES_Q_514___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_514___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_514___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_515 (0x005F480C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_515___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_515___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_515__RX_DCOC_RANGE_515___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_515__RX_DCOC_RES_I_515___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_515__RX_DCOC_RES_Q_515___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_515__RX_DCOC_RANGE_515___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_515__RX_DCOC_RANGE_515___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_515__RX_DCOC_RES_I_515___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_515__RX_DCOC_RES_I_515___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_515__RX_DCOC_RES_Q_515___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_515__RX_DCOC_RES_Q_515___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_515___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_515___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_516 (0x005F4810) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_516___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_516___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_516__RX_DCOC_RANGE_516___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_516__RX_DCOC_RES_I_516___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_516__RX_DCOC_RES_Q_516___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_516__RX_DCOC_RANGE_516___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_516__RX_DCOC_RANGE_516___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_516__RX_DCOC_RES_I_516___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_516__RX_DCOC_RES_I_516___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_516__RX_DCOC_RES_Q_516___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_516__RX_DCOC_RES_Q_516___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_516___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_516___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_517 (0x005F4814) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_517___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_517___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_517__RX_DCOC_RANGE_517___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_517__RX_DCOC_RES_I_517___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_517__RX_DCOC_RES_Q_517___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_517__RX_DCOC_RANGE_517___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_517__RX_DCOC_RANGE_517___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_517__RX_DCOC_RES_I_517___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_517__RX_DCOC_RES_I_517___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_517__RX_DCOC_RES_Q_517___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_517__RX_DCOC_RES_Q_517___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_517___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_517___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_518 (0x005F4818) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_518___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_518___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_518__RX_DCOC_RANGE_518___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_518__RX_DCOC_RES_I_518___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_518__RX_DCOC_RES_Q_518___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_518__RX_DCOC_RANGE_518___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_518__RX_DCOC_RANGE_518___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_518__RX_DCOC_RES_I_518___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_518__RX_DCOC_RES_I_518___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_518__RX_DCOC_RES_Q_518___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_518__RX_DCOC_RES_Q_518___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_518___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_518___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_519 (0x005F481C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_519___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_519___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_519__RX_DCOC_RANGE_519___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_519__RX_DCOC_RES_I_519___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_519__RX_DCOC_RES_Q_519___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_519__RX_DCOC_RANGE_519___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_519__RX_DCOC_RANGE_519___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_519__RX_DCOC_RES_I_519___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_519__RX_DCOC_RES_I_519___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_519__RX_DCOC_RES_Q_519___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_519__RX_DCOC_RES_Q_519___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_519___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_519___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_520 (0x005F4820) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_520___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_520___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_520__RX_DCOC_RANGE_520___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_520__RX_DCOC_RES_I_520___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_520__RX_DCOC_RES_Q_520___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_520__RX_DCOC_RANGE_520___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_520__RX_DCOC_RANGE_520___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_520__RX_DCOC_RES_I_520___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_520__RX_DCOC_RES_I_520___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_520__RX_DCOC_RES_Q_520___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_520__RX_DCOC_RES_Q_520___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_520___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_520___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_521 (0x005F4824) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_521___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_521___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_521__RX_DCOC_RANGE_521___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_521__RX_DCOC_RES_I_521___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_521__RX_DCOC_RES_Q_521___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_521__RX_DCOC_RANGE_521___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_521__RX_DCOC_RANGE_521___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_521__RX_DCOC_RES_I_521___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_521__RX_DCOC_RES_I_521___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_521__RX_DCOC_RES_Q_521___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_521__RX_DCOC_RES_Q_521___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_521___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_521___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_522 (0x005F4828) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_522___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_522___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_522__RX_DCOC_RANGE_522___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_522__RX_DCOC_RES_I_522___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_522__RX_DCOC_RES_Q_522___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_522__RX_DCOC_RANGE_522___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_522__RX_DCOC_RANGE_522___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_522__RX_DCOC_RES_I_522___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_522__RX_DCOC_RES_I_522___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_522__RX_DCOC_RES_Q_522___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_522__RX_DCOC_RES_Q_522___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_522___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_522___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_523 (0x005F482C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_523___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_523___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_523__RX_DCOC_RANGE_523___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_523__RX_DCOC_RES_I_523___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_523__RX_DCOC_RES_Q_523___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_523__RX_DCOC_RANGE_523___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_523__RX_DCOC_RANGE_523___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_523__RX_DCOC_RES_I_523___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_523__RX_DCOC_RES_I_523___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_523__RX_DCOC_RES_Q_523___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_523__RX_DCOC_RES_Q_523___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_523___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_523___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_524 (0x005F4830) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_524___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_524___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_524__RX_DCOC_RANGE_524___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_524__RX_DCOC_RES_I_524___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_524__RX_DCOC_RES_Q_524___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_524__RX_DCOC_RANGE_524___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_524__RX_DCOC_RANGE_524___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_524__RX_DCOC_RES_I_524___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_524__RX_DCOC_RES_I_524___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_524__RX_DCOC_RES_Q_524___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_524__RX_DCOC_RES_Q_524___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_524___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_524___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_525 (0x005F4834) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_525___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_525___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_525__RX_DCOC_RANGE_525___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_525__RX_DCOC_RES_I_525___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_525__RX_DCOC_RES_Q_525___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_525__RX_DCOC_RANGE_525___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_525__RX_DCOC_RANGE_525___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_525__RX_DCOC_RES_I_525___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_525__RX_DCOC_RES_I_525___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_525__RX_DCOC_RES_Q_525___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_525__RX_DCOC_RES_Q_525___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_525___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_525___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_526 (0x005F4838) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_526___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_526___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_526__RX_DCOC_RANGE_526___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_526__RX_DCOC_RES_I_526___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_526__RX_DCOC_RES_Q_526___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_526__RX_DCOC_RANGE_526___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_526__RX_DCOC_RANGE_526___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_526__RX_DCOC_RES_I_526___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_526__RX_DCOC_RES_I_526___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_526__RX_DCOC_RES_Q_526___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_526__RX_DCOC_RES_Q_526___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_526___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_526___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_527 (0x005F483C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_527___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_527___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_527__RX_DCOC_RANGE_527___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_527__RX_DCOC_RES_I_527___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_527__RX_DCOC_RES_Q_527___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_527__RX_DCOC_RANGE_527___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_527__RX_DCOC_RANGE_527___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_527__RX_DCOC_RES_I_527___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_527__RX_DCOC_RES_I_527___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_527__RX_DCOC_RES_Q_527___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_527__RX_DCOC_RES_Q_527___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_527___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_527___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_528 (0x005F4840) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_528___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_528___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_528__RX_DCOC_RANGE_528___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_528__RX_DCOC_RES_I_528___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_528__RX_DCOC_RES_Q_528___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_528__RX_DCOC_RANGE_528___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_528__RX_DCOC_RANGE_528___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_528__RX_DCOC_RES_I_528___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_528__RX_DCOC_RES_I_528___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_528__RX_DCOC_RES_Q_528___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_528__RX_DCOC_RES_Q_528___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_528___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_528___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_529 (0x005F4844) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_529___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_529___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_529__RX_DCOC_RANGE_529___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_529__RX_DCOC_RES_I_529___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_529__RX_DCOC_RES_Q_529___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_529__RX_DCOC_RANGE_529___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_529__RX_DCOC_RANGE_529___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_529__RX_DCOC_RES_I_529___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_529__RX_DCOC_RES_I_529___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_529__RX_DCOC_RES_Q_529___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_529__RX_DCOC_RES_Q_529___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_529___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_529___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_530 (0x005F4848) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_530___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_530___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_530__RX_DCOC_RANGE_530___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_530__RX_DCOC_RES_I_530___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_530__RX_DCOC_RES_Q_530___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_530__RX_DCOC_RANGE_530___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_530__RX_DCOC_RANGE_530___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_530__RX_DCOC_RES_I_530___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_530__RX_DCOC_RES_I_530___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_530__RX_DCOC_RES_Q_530___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_530__RX_DCOC_RES_Q_530___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_530___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_530___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_531 (0x005F484C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_531___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_531___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_531__RX_DCOC_RANGE_531___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_531__RX_DCOC_RES_I_531___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_531__RX_DCOC_RES_Q_531___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_531__RX_DCOC_RANGE_531___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_531__RX_DCOC_RANGE_531___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_531__RX_DCOC_RES_I_531___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_531__RX_DCOC_RES_I_531___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_531__RX_DCOC_RES_Q_531___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_531__RX_DCOC_RES_Q_531___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_531___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_531___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_532 (0x005F4850) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_532___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_532___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_532__RX_DCOC_RANGE_532___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_532__RX_DCOC_RES_I_532___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_532__RX_DCOC_RES_Q_532___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_532__RX_DCOC_RANGE_532___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_532__RX_DCOC_RANGE_532___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_532__RX_DCOC_RES_I_532___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_532__RX_DCOC_RES_I_532___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_532__RX_DCOC_RES_Q_532___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_532__RX_DCOC_RES_Q_532___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_532___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_532___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_533 (0x005F4854) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_533___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_533___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_533__RX_DCOC_RANGE_533___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_533__RX_DCOC_RES_I_533___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_533__RX_DCOC_RES_Q_533___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_533__RX_DCOC_RANGE_533___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_533__RX_DCOC_RANGE_533___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_533__RX_DCOC_RES_I_533___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_533__RX_DCOC_RES_I_533___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_533__RX_DCOC_RES_Q_533___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_533__RX_DCOC_RES_Q_533___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_533___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_533___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_534 (0x005F4858) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_534___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_534___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_534__RX_DCOC_RANGE_534___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_534__RX_DCOC_RES_I_534___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_534__RX_DCOC_RES_Q_534___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_534__RX_DCOC_RANGE_534___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_534__RX_DCOC_RANGE_534___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_534__RX_DCOC_RES_I_534___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_534__RX_DCOC_RES_I_534___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_534__RX_DCOC_RES_Q_534___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_534__RX_DCOC_RES_Q_534___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_534___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_534___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_535 (0x005F485C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_535___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_535___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_535__RX_DCOC_RANGE_535___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_535__RX_DCOC_RES_I_535___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_535__RX_DCOC_RES_Q_535___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_535__RX_DCOC_RANGE_535___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_535__RX_DCOC_RANGE_535___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_535__RX_DCOC_RES_I_535___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_535__RX_DCOC_RES_I_535___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_535__RX_DCOC_RES_Q_535___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_535__RX_DCOC_RES_Q_535___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_535___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_535___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_536 (0x005F4860) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_536___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_536___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_536__RX_DCOC_RANGE_536___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_536__RX_DCOC_RES_I_536___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_536__RX_DCOC_RES_Q_536___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_536__RX_DCOC_RANGE_536___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_536__RX_DCOC_RANGE_536___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_536__RX_DCOC_RES_I_536___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_536__RX_DCOC_RES_I_536___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_536__RX_DCOC_RES_Q_536___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_536__RX_DCOC_RES_Q_536___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_536___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_536___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_537 (0x005F4864) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_537___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_537___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_537__RX_DCOC_RANGE_537___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_537__RX_DCOC_RES_I_537___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_537__RX_DCOC_RES_Q_537___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_537__RX_DCOC_RANGE_537___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_537__RX_DCOC_RANGE_537___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_537__RX_DCOC_RES_I_537___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_537__RX_DCOC_RES_I_537___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_537__RX_DCOC_RES_Q_537___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_537__RX_DCOC_RES_Q_537___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_537___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_537___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_538 (0x005F4868) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_538___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_538___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_538__RX_DCOC_RANGE_538___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_538__RX_DCOC_RES_I_538___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_538__RX_DCOC_RES_Q_538___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_538__RX_DCOC_RANGE_538___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_538__RX_DCOC_RANGE_538___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_538__RX_DCOC_RES_I_538___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_538__RX_DCOC_RES_I_538___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_538__RX_DCOC_RES_Q_538___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_538__RX_DCOC_RES_Q_538___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_538___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_538___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_539 (0x005F486C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_539___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_539___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_539__RX_DCOC_RANGE_539___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_539__RX_DCOC_RES_I_539___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_539__RX_DCOC_RES_Q_539___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_539__RX_DCOC_RANGE_539___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_539__RX_DCOC_RANGE_539___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_539__RX_DCOC_RES_I_539___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_539__RX_DCOC_RES_I_539___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_539__RX_DCOC_RES_Q_539___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_539__RX_DCOC_RES_Q_539___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_539___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_539___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_540 (0x005F4870) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_540___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_540___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_540__RX_DCOC_RANGE_540___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_540__RX_DCOC_RES_I_540___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_540__RX_DCOC_RES_Q_540___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_540__RX_DCOC_RANGE_540___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_540__RX_DCOC_RANGE_540___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_540__RX_DCOC_RES_I_540___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_540__RX_DCOC_RES_I_540___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_540__RX_DCOC_RES_Q_540___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_540__RX_DCOC_RES_Q_540___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_540___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_540___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_541 (0x005F4874) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_541___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_541___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_541__RX_DCOC_RANGE_541___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_541__RX_DCOC_RES_I_541___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_541__RX_DCOC_RES_Q_541___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_541__RX_DCOC_RANGE_541___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_541__RX_DCOC_RANGE_541___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_541__RX_DCOC_RES_I_541___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_541__RX_DCOC_RES_I_541___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_541__RX_DCOC_RES_Q_541___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_541__RX_DCOC_RES_Q_541___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_541___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_541___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_542 (0x005F4878) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_542___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_542___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_542__RX_DCOC_RANGE_542___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_542__RX_DCOC_RES_I_542___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_542__RX_DCOC_RES_Q_542___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_542__RX_DCOC_RANGE_542___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_542__RX_DCOC_RANGE_542___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_542__RX_DCOC_RES_I_542___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_542__RX_DCOC_RES_I_542___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_542__RX_DCOC_RES_Q_542___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_542__RX_DCOC_RES_Q_542___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_542___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_542___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_543 (0x005F487C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_543___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_543___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_543__RX_DCOC_RANGE_543___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_543__RX_DCOC_RES_I_543___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_543__RX_DCOC_RES_Q_543___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_543__RX_DCOC_RANGE_543___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_543__RX_DCOC_RANGE_543___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_543__RX_DCOC_RES_I_543___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_543__RX_DCOC_RES_I_543___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_543__RX_DCOC_RES_Q_543___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_543__RX_DCOC_RES_Q_543___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_543___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_543___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_544 (0x005F4880) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_544___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_544___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_544__RX_DCOC_RANGE_544___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_544__RX_DCOC_RES_I_544___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_544__RX_DCOC_RES_Q_544___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_544__RX_DCOC_RANGE_544___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_544__RX_DCOC_RANGE_544___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_544__RX_DCOC_RES_I_544___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_544__RX_DCOC_RES_I_544___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_544__RX_DCOC_RES_Q_544___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_544__RX_DCOC_RES_Q_544___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_544___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_544___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_545 (0x005F4884) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_545___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_545___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_545__RX_DCOC_RANGE_545___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_545__RX_DCOC_RES_I_545___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_545__RX_DCOC_RES_Q_545___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_545__RX_DCOC_RANGE_545___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_545__RX_DCOC_RANGE_545___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_545__RX_DCOC_RES_I_545___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_545__RX_DCOC_RES_I_545___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_545__RX_DCOC_RES_Q_545___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_545__RX_DCOC_RES_Q_545___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_545___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_545___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_546 (0x005F4888) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_546___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_546___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_546__RX_DCOC_RANGE_546___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_546__RX_DCOC_RES_I_546___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_546__RX_DCOC_RES_Q_546___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_546__RX_DCOC_RANGE_546___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_546__RX_DCOC_RANGE_546___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_546__RX_DCOC_RES_I_546___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_546__RX_DCOC_RES_I_546___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_546__RX_DCOC_RES_Q_546___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_546__RX_DCOC_RES_Q_546___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_546___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_546___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_547 (0x005F488C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_547___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_547___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_547__RX_DCOC_RANGE_547___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_547__RX_DCOC_RES_I_547___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_547__RX_DCOC_RES_Q_547___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_547__RX_DCOC_RANGE_547___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_547__RX_DCOC_RANGE_547___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_547__RX_DCOC_RES_I_547___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_547__RX_DCOC_RES_I_547___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_547__RX_DCOC_RES_Q_547___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_547__RX_DCOC_RES_Q_547___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_547___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_547___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_548 (0x005F4890) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_548___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_548___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_548__RX_DCOC_RANGE_548___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_548__RX_DCOC_RES_I_548___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_548__RX_DCOC_RES_Q_548___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_548__RX_DCOC_RANGE_548___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_548__RX_DCOC_RANGE_548___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_548__RX_DCOC_RES_I_548___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_548__RX_DCOC_RES_I_548___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_548__RX_DCOC_RES_Q_548___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_548__RX_DCOC_RES_Q_548___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_548___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_548___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_549 (0x005F4894) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_549___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_549___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_549__RX_DCOC_RANGE_549___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_549__RX_DCOC_RES_I_549___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_549__RX_DCOC_RES_Q_549___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_549__RX_DCOC_RANGE_549___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_549__RX_DCOC_RANGE_549___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_549__RX_DCOC_RES_I_549___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_549__RX_DCOC_RES_I_549___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_549__RX_DCOC_RES_Q_549___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_549__RX_DCOC_RES_Q_549___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_549___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_549___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_550 (0x005F4898) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_550___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_550___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_550__RX_DCOC_RANGE_550___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_550__RX_DCOC_RES_I_550___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_550__RX_DCOC_RES_Q_550___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_550__RX_DCOC_RANGE_550___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_550__RX_DCOC_RANGE_550___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_550__RX_DCOC_RES_I_550___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_550__RX_DCOC_RES_I_550___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_550__RX_DCOC_RES_Q_550___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_550__RX_DCOC_RES_Q_550___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_550___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_550___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_551 (0x005F489C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_551___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_551___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_551__RX_DCOC_RANGE_551___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_551__RX_DCOC_RES_I_551___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_551__RX_DCOC_RES_Q_551___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_551__RX_DCOC_RANGE_551___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_551__RX_DCOC_RANGE_551___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_551__RX_DCOC_RES_I_551___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_551__RX_DCOC_RES_I_551___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_551__RX_DCOC_RES_Q_551___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_551__RX_DCOC_RES_Q_551___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_551___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_551___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_552 (0x005F48A0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_552___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_552___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_552__RX_DCOC_RANGE_552___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_552__RX_DCOC_RES_I_552___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_552__RX_DCOC_RES_Q_552___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_552__RX_DCOC_RANGE_552___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_552__RX_DCOC_RANGE_552___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_552__RX_DCOC_RES_I_552___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_552__RX_DCOC_RES_I_552___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_552__RX_DCOC_RES_Q_552___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_552__RX_DCOC_RES_Q_552___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_552___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_552___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_553 (0x005F48A4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_553___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_553___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_553__RX_DCOC_RANGE_553___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_553__RX_DCOC_RES_I_553___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_553__RX_DCOC_RES_Q_553___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_553__RX_DCOC_RANGE_553___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_553__RX_DCOC_RANGE_553___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_553__RX_DCOC_RES_I_553___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_553__RX_DCOC_RES_I_553___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_553__RX_DCOC_RES_Q_553___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_553__RX_DCOC_RES_Q_553___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_553___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_553___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_554 (0x005F48A8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_554___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_554___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_554__RX_DCOC_RANGE_554___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_554__RX_DCOC_RES_I_554___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_554__RX_DCOC_RES_Q_554___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_554__RX_DCOC_RANGE_554___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_554__RX_DCOC_RANGE_554___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_554__RX_DCOC_RES_I_554___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_554__RX_DCOC_RES_I_554___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_554__RX_DCOC_RES_Q_554___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_554__RX_DCOC_RES_Q_554___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_554___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_554___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_555 (0x005F48AC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_555___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_555___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_555__RX_DCOC_RANGE_555___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_555__RX_DCOC_RES_I_555___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_555__RX_DCOC_RES_Q_555___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_555__RX_DCOC_RANGE_555___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_555__RX_DCOC_RANGE_555___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_555__RX_DCOC_RES_I_555___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_555__RX_DCOC_RES_I_555___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_555__RX_DCOC_RES_Q_555___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_555__RX_DCOC_RES_Q_555___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_555___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_555___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_556 (0x005F48B0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_556___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_556___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_556__RX_DCOC_RANGE_556___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_556__RX_DCOC_RES_I_556___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_556__RX_DCOC_RES_Q_556___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_556__RX_DCOC_RANGE_556___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_556__RX_DCOC_RANGE_556___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_556__RX_DCOC_RES_I_556___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_556__RX_DCOC_RES_I_556___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_556__RX_DCOC_RES_Q_556___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_556__RX_DCOC_RES_Q_556___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_556___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_556___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_557 (0x005F48B4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_557___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_557___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_557__RX_DCOC_RANGE_557___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_557__RX_DCOC_RES_I_557___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_557__RX_DCOC_RES_Q_557___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_557__RX_DCOC_RANGE_557___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_557__RX_DCOC_RANGE_557___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_557__RX_DCOC_RES_I_557___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_557__RX_DCOC_RES_I_557___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_557__RX_DCOC_RES_Q_557___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_557__RX_DCOC_RES_Q_557___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_557___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_557___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_558 (0x005F48B8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_558___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_558___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_558__RX_DCOC_RANGE_558___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_558__RX_DCOC_RES_I_558___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_558__RX_DCOC_RES_Q_558___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_558__RX_DCOC_RANGE_558___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_558__RX_DCOC_RANGE_558___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_558__RX_DCOC_RES_I_558___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_558__RX_DCOC_RES_I_558___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_558__RX_DCOC_RES_Q_558___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_558__RX_DCOC_RES_Q_558___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_558___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_558___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_559 (0x005F48BC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_559___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_559___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_559__RX_DCOC_RANGE_559___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_559__RX_DCOC_RES_I_559___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_559__RX_DCOC_RES_Q_559___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_559__RX_DCOC_RANGE_559___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_559__RX_DCOC_RANGE_559___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_559__RX_DCOC_RES_I_559___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_559__RX_DCOC_RES_I_559___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_559__RX_DCOC_RES_Q_559___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_559__RX_DCOC_RES_Q_559___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_559___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_559___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_560 (0x005F48C0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_560___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_560___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_560__RX_DCOC_RANGE_560___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_560__RX_DCOC_RES_I_560___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_560__RX_DCOC_RES_Q_560___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_560__RX_DCOC_RANGE_560___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_560__RX_DCOC_RANGE_560___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_560__RX_DCOC_RES_I_560___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_560__RX_DCOC_RES_I_560___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_560__RX_DCOC_RES_Q_560___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_560__RX_DCOC_RES_Q_560___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_560___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_560___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_561 (0x005F48C4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_561___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_561___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_561__RX_DCOC_RANGE_561___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_561__RX_DCOC_RES_I_561___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_561__RX_DCOC_RES_Q_561___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_561__RX_DCOC_RANGE_561___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_561__RX_DCOC_RANGE_561___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_561__RX_DCOC_RES_I_561___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_561__RX_DCOC_RES_I_561___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_561__RX_DCOC_RES_Q_561___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_561__RX_DCOC_RES_Q_561___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_561___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_561___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_562 (0x005F48C8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_562___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_562___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_562__RX_DCOC_RANGE_562___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_562__RX_DCOC_RES_I_562___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_562__RX_DCOC_RES_Q_562___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_562__RX_DCOC_RANGE_562___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_562__RX_DCOC_RANGE_562___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_562__RX_DCOC_RES_I_562___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_562__RX_DCOC_RES_I_562___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_562__RX_DCOC_RES_Q_562___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_562__RX_DCOC_RES_Q_562___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_562___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_562___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_563 (0x005F48CC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_563___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_563___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_563__RX_DCOC_RANGE_563___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_563__RX_DCOC_RES_I_563___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_563__RX_DCOC_RES_Q_563___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_563__RX_DCOC_RANGE_563___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_563__RX_DCOC_RANGE_563___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_563__RX_DCOC_RES_I_563___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_563__RX_DCOC_RES_I_563___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_563__RX_DCOC_RES_Q_563___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_563__RX_DCOC_RES_Q_563___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_563___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_563___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_564 (0x005F48D0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_564___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_564___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_564__RX_DCOC_RANGE_564___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_564__RX_DCOC_RES_I_564___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_564__RX_DCOC_RES_Q_564___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_564__RX_DCOC_RANGE_564___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_564__RX_DCOC_RANGE_564___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_564__RX_DCOC_RES_I_564___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_564__RX_DCOC_RES_I_564___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_564__RX_DCOC_RES_Q_564___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_564__RX_DCOC_RES_Q_564___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_564___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_564___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_565 (0x005F48D4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_565___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_565___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_565__RX_DCOC_RANGE_565___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_565__RX_DCOC_RES_I_565___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_565__RX_DCOC_RES_Q_565___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_565__RX_DCOC_RANGE_565___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_565__RX_DCOC_RANGE_565___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_565__RX_DCOC_RES_I_565___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_565__RX_DCOC_RES_I_565___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_565__RX_DCOC_RES_Q_565___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_565__RX_DCOC_RES_Q_565___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_565___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_565___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_566 (0x005F48D8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_566___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_566___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_566__RX_DCOC_RANGE_566___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_566__RX_DCOC_RES_I_566___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_566__RX_DCOC_RES_Q_566___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_566__RX_DCOC_RANGE_566___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_566__RX_DCOC_RANGE_566___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_566__RX_DCOC_RES_I_566___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_566__RX_DCOC_RES_I_566___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_566__RX_DCOC_RES_Q_566___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_566__RX_DCOC_RES_Q_566___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_566___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_566___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_567 (0x005F48DC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_567___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_567___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_567__RX_DCOC_RANGE_567___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_567__RX_DCOC_RES_I_567___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_567__RX_DCOC_RES_Q_567___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_567__RX_DCOC_RANGE_567___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_567__RX_DCOC_RANGE_567___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_567__RX_DCOC_RES_I_567___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_567__RX_DCOC_RES_I_567___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_567__RX_DCOC_RES_Q_567___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_567__RX_DCOC_RES_Q_567___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_567___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_567___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_568 (0x005F48E0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_568___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_568___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_568__RX_DCOC_RANGE_568___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_568__RX_DCOC_RES_I_568___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_568__RX_DCOC_RES_Q_568___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_568__RX_DCOC_RANGE_568___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_568__RX_DCOC_RANGE_568___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_568__RX_DCOC_RES_I_568___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_568__RX_DCOC_RES_I_568___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_568__RX_DCOC_RES_Q_568___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_568__RX_DCOC_RES_Q_568___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_568___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_568___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_569 (0x005F48E4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_569___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_569___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_569__RX_DCOC_RANGE_569___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_569__RX_DCOC_RES_I_569___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_569__RX_DCOC_RES_Q_569___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_569__RX_DCOC_RANGE_569___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_569__RX_DCOC_RANGE_569___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_569__RX_DCOC_RES_I_569___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_569__RX_DCOC_RES_I_569___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_569__RX_DCOC_RES_Q_569___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_569__RX_DCOC_RES_Q_569___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_569___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_569___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_570 (0x005F48E8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_570___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_570___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_570__RX_DCOC_RANGE_570___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_570__RX_DCOC_RES_I_570___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_570__RX_DCOC_RES_Q_570___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_570__RX_DCOC_RANGE_570___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_570__RX_DCOC_RANGE_570___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_570__RX_DCOC_RES_I_570___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_570__RX_DCOC_RES_I_570___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_570__RX_DCOC_RES_Q_570___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_570__RX_DCOC_RES_Q_570___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_570___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_570___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_571 (0x005F48EC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_571___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_571___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_571__RX_DCOC_RANGE_571___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_571__RX_DCOC_RES_I_571___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_571__RX_DCOC_RES_Q_571___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_571__RX_DCOC_RANGE_571___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_571__RX_DCOC_RANGE_571___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_571__RX_DCOC_RES_I_571___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_571__RX_DCOC_RES_I_571___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_571__RX_DCOC_RES_Q_571___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_571__RX_DCOC_RES_Q_571___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_571___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_571___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_572 (0x005F48F0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_572___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_572___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_572__RX_DCOC_RANGE_572___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_572__RX_DCOC_RES_I_572___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_572__RX_DCOC_RES_Q_572___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_572__RX_DCOC_RANGE_572___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_572__RX_DCOC_RANGE_572___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_572__RX_DCOC_RES_I_572___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_572__RX_DCOC_RES_I_572___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_572__RX_DCOC_RES_Q_572___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_572__RX_DCOC_RES_Q_572___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_572___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_572___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_573 (0x005F48F4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_573___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_573___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_573__RX_DCOC_RANGE_573___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_573__RX_DCOC_RES_I_573___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_573__RX_DCOC_RES_Q_573___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_573__RX_DCOC_RANGE_573___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_573__RX_DCOC_RANGE_573___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_573__RX_DCOC_RES_I_573___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_573__RX_DCOC_RES_I_573___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_573__RX_DCOC_RES_Q_573___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_573__RX_DCOC_RES_Q_573___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_573___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_573___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_574 (0x005F48F8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_574___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_574___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_574__RX_DCOC_RANGE_574___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_574__RX_DCOC_RES_I_574___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_574__RX_DCOC_RES_Q_574___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_574__RX_DCOC_RANGE_574___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_574__RX_DCOC_RANGE_574___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_574__RX_DCOC_RES_I_574___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_574__RX_DCOC_RES_I_574___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_574__RX_DCOC_RES_Q_574___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_574__RX_DCOC_RES_Q_574___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_574___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_574___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_575 (0x005F48FC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_575___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_575___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_575__RX_DCOC_RANGE_575___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_575__RX_DCOC_RES_I_575___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_575__RX_DCOC_RES_Q_575___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_575__RX_DCOC_RANGE_575___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_575__RX_DCOC_RANGE_575___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_575__RX_DCOC_RES_I_575___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_575__RX_DCOC_RES_I_575___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_575__RX_DCOC_RES_Q_575___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_575__RX_DCOC_RES_Q_575___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_575___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_575___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_576 (0x005F4900) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_576___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_576___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_576__RX_DCOC_RANGE_576___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_576__RX_DCOC_RES_I_576___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_576__RX_DCOC_RES_Q_576___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_576__RX_DCOC_RANGE_576___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_576__RX_DCOC_RANGE_576___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_576__RX_DCOC_RES_I_576___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_576__RX_DCOC_RES_I_576___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_576__RX_DCOC_RES_Q_576___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_576__RX_DCOC_RES_Q_576___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_576___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_576___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_577 (0x005F4904) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_577___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_577___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_577__RX_DCOC_RANGE_577___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_577__RX_DCOC_RES_I_577___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_577__RX_DCOC_RES_Q_577___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_577__RX_DCOC_RANGE_577___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_577__RX_DCOC_RANGE_577___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_577__RX_DCOC_RES_I_577___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_577__RX_DCOC_RES_I_577___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_577__RX_DCOC_RES_Q_577___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_577__RX_DCOC_RES_Q_577___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_577___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_577___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_578 (0x005F4908) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_578___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_578___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_578__RX_DCOC_RANGE_578___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_578__RX_DCOC_RES_I_578___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_578__RX_DCOC_RES_Q_578___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_578__RX_DCOC_RANGE_578___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_578__RX_DCOC_RANGE_578___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_578__RX_DCOC_RES_I_578___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_578__RX_DCOC_RES_I_578___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_578__RX_DCOC_RES_Q_578___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_578__RX_DCOC_RES_Q_578___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_578___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_578___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_579 (0x005F490C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_579___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_579___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_579__RX_DCOC_RANGE_579___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_579__RX_DCOC_RES_I_579___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_579__RX_DCOC_RES_Q_579___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_579__RX_DCOC_RANGE_579___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_579__RX_DCOC_RANGE_579___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_579__RX_DCOC_RES_I_579___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_579__RX_DCOC_RES_I_579___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_579__RX_DCOC_RES_Q_579___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_579__RX_DCOC_RES_Q_579___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_579___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_579___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_580 (0x005F4910) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_580___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_580___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_580__RX_DCOC_RANGE_580___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_580__RX_DCOC_RES_I_580___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_580__RX_DCOC_RES_Q_580___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_580__RX_DCOC_RANGE_580___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_580__RX_DCOC_RANGE_580___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_580__RX_DCOC_RES_I_580___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_580__RX_DCOC_RES_I_580___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_580__RX_DCOC_RES_Q_580___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_580__RX_DCOC_RES_Q_580___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_580___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_580___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_581 (0x005F4914) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_581___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_581___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_581__RX_DCOC_RANGE_581___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_581__RX_DCOC_RES_I_581___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_581__RX_DCOC_RES_Q_581___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_581__RX_DCOC_RANGE_581___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_581__RX_DCOC_RANGE_581___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_581__RX_DCOC_RES_I_581___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_581__RX_DCOC_RES_I_581___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_581__RX_DCOC_RES_Q_581___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_581__RX_DCOC_RES_Q_581___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_581___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_581___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_582 (0x005F4918) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_582___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_582___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_582__RX_DCOC_RANGE_582___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_582__RX_DCOC_RES_I_582___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_582__RX_DCOC_RES_Q_582___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_582__RX_DCOC_RANGE_582___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_582__RX_DCOC_RANGE_582___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_582__RX_DCOC_RES_I_582___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_582__RX_DCOC_RES_I_582___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_582__RX_DCOC_RES_Q_582___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_582__RX_DCOC_RES_Q_582___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_582___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_582___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_583 (0x005F491C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_583___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_583___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_583__RX_DCOC_RANGE_583___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_583__RX_DCOC_RES_I_583___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_583__RX_DCOC_RES_Q_583___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_583__RX_DCOC_RANGE_583___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_583__RX_DCOC_RANGE_583___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_583__RX_DCOC_RES_I_583___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_583__RX_DCOC_RES_I_583___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_583__RX_DCOC_RES_Q_583___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_583__RX_DCOC_RES_Q_583___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_583___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_583___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_584 (0x005F4920) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_584___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_584___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_584__RX_DCOC_RANGE_584___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_584__RX_DCOC_RES_I_584___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_584__RX_DCOC_RES_Q_584___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_584__RX_DCOC_RANGE_584___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_584__RX_DCOC_RANGE_584___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_584__RX_DCOC_RES_I_584___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_584__RX_DCOC_RES_I_584___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_584__RX_DCOC_RES_Q_584___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_584__RX_DCOC_RES_Q_584___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_584___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_584___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_585 (0x005F4924) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_585___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_585___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_585__RX_DCOC_RANGE_585___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_585__RX_DCOC_RES_I_585___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_585__RX_DCOC_RES_Q_585___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_585__RX_DCOC_RANGE_585___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_585__RX_DCOC_RANGE_585___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_585__RX_DCOC_RES_I_585___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_585__RX_DCOC_RES_I_585___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_585__RX_DCOC_RES_Q_585___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_585__RX_DCOC_RES_Q_585___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_585___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_585___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_586 (0x005F4928) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_586___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_586___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_586__RX_DCOC_RANGE_586___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_586__RX_DCOC_RES_I_586___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_586__RX_DCOC_RES_Q_586___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_586__RX_DCOC_RANGE_586___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_586__RX_DCOC_RANGE_586___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_586__RX_DCOC_RES_I_586___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_586__RX_DCOC_RES_I_586___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_586__RX_DCOC_RES_Q_586___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_586__RX_DCOC_RES_Q_586___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_586___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_586___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_587 (0x005F492C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_587___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_587___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_587__RX_DCOC_RANGE_587___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_587__RX_DCOC_RES_I_587___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_587__RX_DCOC_RES_Q_587___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_587__RX_DCOC_RANGE_587___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_587__RX_DCOC_RANGE_587___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_587__RX_DCOC_RES_I_587___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_587__RX_DCOC_RES_I_587___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_587__RX_DCOC_RES_Q_587___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_587__RX_DCOC_RES_Q_587___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_587___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_587___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_588 (0x005F4930) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_588___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_588___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_588__RX_DCOC_RANGE_588___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_588__RX_DCOC_RES_I_588___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_588__RX_DCOC_RES_Q_588___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_588__RX_DCOC_RANGE_588___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_588__RX_DCOC_RANGE_588___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_588__RX_DCOC_RES_I_588___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_588__RX_DCOC_RES_I_588___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_588__RX_DCOC_RES_Q_588___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_588__RX_DCOC_RES_Q_588___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_588___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_588___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_589 (0x005F4934) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_589___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_589___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_589__RX_DCOC_RANGE_589___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_589__RX_DCOC_RES_I_589___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_589__RX_DCOC_RES_Q_589___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_589__RX_DCOC_RANGE_589___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_589__RX_DCOC_RANGE_589___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_589__RX_DCOC_RES_I_589___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_589__RX_DCOC_RES_I_589___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_589__RX_DCOC_RES_Q_589___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_589__RX_DCOC_RES_Q_589___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_589___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_589___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_590 (0x005F4938) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_590___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_590___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_590__RX_DCOC_RANGE_590___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_590__RX_DCOC_RES_I_590___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_590__RX_DCOC_RES_Q_590___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_590__RX_DCOC_RANGE_590___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_590__RX_DCOC_RANGE_590___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_590__RX_DCOC_RES_I_590___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_590__RX_DCOC_RES_I_590___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_590__RX_DCOC_RES_Q_590___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_590__RX_DCOC_RES_Q_590___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_590___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_590___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_591 (0x005F493C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_591___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_591___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_591__RX_DCOC_RANGE_591___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_591__RX_DCOC_RES_I_591___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_591__RX_DCOC_RES_Q_591___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_591__RX_DCOC_RANGE_591___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_591__RX_DCOC_RANGE_591___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_591__RX_DCOC_RES_I_591___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_591__RX_DCOC_RES_I_591___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_591__RX_DCOC_RES_Q_591___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_591__RX_DCOC_RES_Q_591___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_591___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_591___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_592 (0x005F4940) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_592___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_592___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_592__RX_DCOC_RANGE_592___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_592__RX_DCOC_RES_I_592___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_592__RX_DCOC_RES_Q_592___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_592__RX_DCOC_RANGE_592___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_592__RX_DCOC_RANGE_592___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_592__RX_DCOC_RES_I_592___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_592__RX_DCOC_RES_I_592___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_592__RX_DCOC_RES_Q_592___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_592__RX_DCOC_RES_Q_592___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_592___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_592___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_593 (0x005F4944) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_593___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_593___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_593__RX_DCOC_RANGE_593___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_593__RX_DCOC_RES_I_593___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_593__RX_DCOC_RES_Q_593___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_593__RX_DCOC_RANGE_593___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_593__RX_DCOC_RANGE_593___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_593__RX_DCOC_RES_I_593___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_593__RX_DCOC_RES_I_593___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_593__RX_DCOC_RES_Q_593___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_593__RX_DCOC_RES_Q_593___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_593___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_593___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_594 (0x005F4948) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_594___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_594___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_594__RX_DCOC_RANGE_594___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_594__RX_DCOC_RES_I_594___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_594__RX_DCOC_RES_Q_594___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_594__RX_DCOC_RANGE_594___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_594__RX_DCOC_RANGE_594___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_594__RX_DCOC_RES_I_594___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_594__RX_DCOC_RES_I_594___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_594__RX_DCOC_RES_Q_594___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_594__RX_DCOC_RES_Q_594___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_594___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_594___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_595 (0x005F494C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_595___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_595___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_595__RX_DCOC_RANGE_595___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_595__RX_DCOC_RES_I_595___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_595__RX_DCOC_RES_Q_595___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_595__RX_DCOC_RANGE_595___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_595__RX_DCOC_RANGE_595___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_595__RX_DCOC_RES_I_595___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_595__RX_DCOC_RES_I_595___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_595__RX_DCOC_RES_Q_595___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_595__RX_DCOC_RES_Q_595___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_595___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_595___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_596 (0x005F4950) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_596___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_596___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_596__RX_DCOC_RANGE_596___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_596__RX_DCOC_RES_I_596___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_596__RX_DCOC_RES_Q_596___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_596__RX_DCOC_RANGE_596___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_596__RX_DCOC_RANGE_596___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_596__RX_DCOC_RES_I_596___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_596__RX_DCOC_RES_I_596___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_596__RX_DCOC_RES_Q_596___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_596__RX_DCOC_RES_Q_596___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_596___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_596___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_597 (0x005F4954) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_597___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_597___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_597__RX_DCOC_RANGE_597___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_597__RX_DCOC_RES_I_597___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_597__RX_DCOC_RES_Q_597___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_597__RX_DCOC_RANGE_597___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_597__RX_DCOC_RANGE_597___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_597__RX_DCOC_RES_I_597___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_597__RX_DCOC_RES_I_597___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_597__RX_DCOC_RES_Q_597___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_597__RX_DCOC_RES_Q_597___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_597___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_597___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_598 (0x005F4958) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_598___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_598___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_598__RX_DCOC_RANGE_598___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_598__RX_DCOC_RES_I_598___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_598__RX_DCOC_RES_Q_598___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_598__RX_DCOC_RANGE_598___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_598__RX_DCOC_RANGE_598___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_598__RX_DCOC_RES_I_598___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_598__RX_DCOC_RES_I_598___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_598__RX_DCOC_RES_Q_598___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_598__RX_DCOC_RES_Q_598___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_598___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_598___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_599 (0x005F495C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_599___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_599___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_599__RX_DCOC_RANGE_599___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_599__RX_DCOC_RES_I_599___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_599__RX_DCOC_RES_Q_599___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_599__RX_DCOC_RANGE_599___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_599__RX_DCOC_RANGE_599___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_599__RX_DCOC_RES_I_599___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_599__RX_DCOC_RES_I_599___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_599__RX_DCOC_RES_Q_599___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_599__RX_DCOC_RES_Q_599___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_599___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_599___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_600 (0x005F4960) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_600___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_600___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_600__RX_DCOC_RANGE_600___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_600__RX_DCOC_RES_I_600___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_600__RX_DCOC_RES_Q_600___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_600__RX_DCOC_RANGE_600___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_600__RX_DCOC_RANGE_600___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_600__RX_DCOC_RES_I_600___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_600__RX_DCOC_RES_I_600___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_600__RX_DCOC_RES_Q_600___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_600__RX_DCOC_RES_Q_600___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_600___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_600___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_601 (0x005F4964) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_601___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_601___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_601__RX_DCOC_RANGE_601___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_601__RX_DCOC_RES_I_601___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_601__RX_DCOC_RES_Q_601___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_601__RX_DCOC_RANGE_601___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_601__RX_DCOC_RANGE_601___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_601__RX_DCOC_RES_I_601___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_601__RX_DCOC_RES_I_601___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_601__RX_DCOC_RES_Q_601___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_601__RX_DCOC_RES_Q_601___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_601___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_601___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_602 (0x005F4968) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_602___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_602___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_602__RX_DCOC_RANGE_602___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_602__RX_DCOC_RES_I_602___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_602__RX_DCOC_RES_Q_602___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_602__RX_DCOC_RANGE_602___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_602__RX_DCOC_RANGE_602___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_602__RX_DCOC_RES_I_602___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_602__RX_DCOC_RES_I_602___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_602__RX_DCOC_RES_Q_602___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_602__RX_DCOC_RES_Q_602___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_602___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_602___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_603 (0x005F496C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_603___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_603___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_603__RX_DCOC_RANGE_603___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_603__RX_DCOC_RES_I_603___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_603__RX_DCOC_RES_Q_603___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_603__RX_DCOC_RANGE_603___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_603__RX_DCOC_RANGE_603___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_603__RX_DCOC_RES_I_603___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_603__RX_DCOC_RES_I_603___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_603__RX_DCOC_RES_Q_603___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_603__RX_DCOC_RES_Q_603___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_603___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_603___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_604 (0x005F4970) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_604___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_604___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_604__RX_DCOC_RANGE_604___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_604__RX_DCOC_RES_I_604___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_604__RX_DCOC_RES_Q_604___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_604__RX_DCOC_RANGE_604___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_604__RX_DCOC_RANGE_604___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_604__RX_DCOC_RES_I_604___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_604__RX_DCOC_RES_I_604___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_604__RX_DCOC_RES_Q_604___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_604__RX_DCOC_RES_Q_604___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_604___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_604___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_605 (0x005F4974) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_605___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_605___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_605__RX_DCOC_RANGE_605___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_605__RX_DCOC_RES_I_605___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_605__RX_DCOC_RES_Q_605___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_605__RX_DCOC_RANGE_605___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_605__RX_DCOC_RANGE_605___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_605__RX_DCOC_RES_I_605___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_605__RX_DCOC_RES_I_605___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_605__RX_DCOC_RES_Q_605___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_605__RX_DCOC_RES_Q_605___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_605___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_605___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_606 (0x005F4978) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_606___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_606___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_606__RX_DCOC_RANGE_606___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_606__RX_DCOC_RES_I_606___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_606__RX_DCOC_RES_Q_606___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_606__RX_DCOC_RANGE_606___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_606__RX_DCOC_RANGE_606___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_606__RX_DCOC_RES_I_606___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_606__RX_DCOC_RES_I_606___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_606__RX_DCOC_RES_Q_606___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_606__RX_DCOC_RES_Q_606___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_606___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_606___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_607 (0x005F497C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_607___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_607___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_607__RX_DCOC_RANGE_607___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_607__RX_DCOC_RES_I_607___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_607__RX_DCOC_RES_Q_607___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_607__RX_DCOC_RANGE_607___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_607__RX_DCOC_RANGE_607___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_607__RX_DCOC_RES_I_607___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_607__RX_DCOC_RES_I_607___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_607__RX_DCOC_RES_Q_607___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_607__RX_DCOC_RES_Q_607___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_607___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_607___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_608 (0x005F4980) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_608___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_608___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_608__RX_DCOC_RANGE_608___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_608__RX_DCOC_RES_I_608___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_608__RX_DCOC_RES_Q_608___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_608__RX_DCOC_RANGE_608___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_608__RX_DCOC_RANGE_608___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_608__RX_DCOC_RES_I_608___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_608__RX_DCOC_RES_I_608___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_608__RX_DCOC_RES_Q_608___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_608__RX_DCOC_RES_Q_608___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_608___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_608___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_609 (0x005F4984) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_609___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_609___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_609__RX_DCOC_RANGE_609___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_609__RX_DCOC_RES_I_609___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_609__RX_DCOC_RES_Q_609___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_609__RX_DCOC_RANGE_609___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_609__RX_DCOC_RANGE_609___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_609__RX_DCOC_RES_I_609___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_609__RX_DCOC_RES_I_609___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_609__RX_DCOC_RES_Q_609___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_609__RX_DCOC_RES_Q_609___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_609___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_609___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_610 (0x005F4988) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_610___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_610___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_610__RX_DCOC_RANGE_610___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_610__RX_DCOC_RES_I_610___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_610__RX_DCOC_RES_Q_610___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_610__RX_DCOC_RANGE_610___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_610__RX_DCOC_RANGE_610___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_610__RX_DCOC_RES_I_610___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_610__RX_DCOC_RES_I_610___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_610__RX_DCOC_RES_Q_610___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_610__RX_DCOC_RES_Q_610___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_610___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_610___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_611 (0x005F498C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_611___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_611___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_611__RX_DCOC_RANGE_611___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_611__RX_DCOC_RES_I_611___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_611__RX_DCOC_RES_Q_611___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_611__RX_DCOC_RANGE_611___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_611__RX_DCOC_RANGE_611___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_611__RX_DCOC_RES_I_611___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_611__RX_DCOC_RES_I_611___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_611__RX_DCOC_RES_Q_611___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_611__RX_DCOC_RES_Q_611___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_611___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_611___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_612 (0x005F4990) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_612___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_612___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_612__RX_DCOC_RANGE_612___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_612__RX_DCOC_RES_I_612___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_612__RX_DCOC_RES_Q_612___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_612__RX_DCOC_RANGE_612___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_612__RX_DCOC_RANGE_612___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_612__RX_DCOC_RES_I_612___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_612__RX_DCOC_RES_I_612___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_612__RX_DCOC_RES_Q_612___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_612__RX_DCOC_RES_Q_612___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_612___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_612___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_613 (0x005F4994) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_613___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_613___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_613__RX_DCOC_RANGE_613___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_613__RX_DCOC_RES_I_613___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_613__RX_DCOC_RES_Q_613___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_613__RX_DCOC_RANGE_613___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_613__RX_DCOC_RANGE_613___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_613__RX_DCOC_RES_I_613___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_613__RX_DCOC_RES_I_613___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_613__RX_DCOC_RES_Q_613___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_613__RX_DCOC_RES_Q_613___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_613___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_613___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_614 (0x005F4998) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_614___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_614___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_614__RX_DCOC_RANGE_614___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_614__RX_DCOC_RES_I_614___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_614__RX_DCOC_RES_Q_614___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_614__RX_DCOC_RANGE_614___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_614__RX_DCOC_RANGE_614___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_614__RX_DCOC_RES_I_614___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_614__RX_DCOC_RES_I_614___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_614__RX_DCOC_RES_Q_614___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_614__RX_DCOC_RES_Q_614___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_614___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_614___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_615 (0x005F499C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_615___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_615___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_615__RX_DCOC_RANGE_615___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_615__RX_DCOC_RES_I_615___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_615__RX_DCOC_RES_Q_615___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_615__RX_DCOC_RANGE_615___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_615__RX_DCOC_RANGE_615___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_615__RX_DCOC_RES_I_615___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_615__RX_DCOC_RES_I_615___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_615__RX_DCOC_RES_Q_615___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_615__RX_DCOC_RES_Q_615___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_615___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_615___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_616 (0x005F49A0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_616___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_616___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_616__RX_DCOC_RANGE_616___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_616__RX_DCOC_RES_I_616___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_616__RX_DCOC_RES_Q_616___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_616__RX_DCOC_RANGE_616___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_616__RX_DCOC_RANGE_616___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_616__RX_DCOC_RES_I_616___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_616__RX_DCOC_RES_I_616___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_616__RX_DCOC_RES_Q_616___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_616__RX_DCOC_RES_Q_616___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_616___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_616___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_617 (0x005F49A4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_617___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_617___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_617__RX_DCOC_RANGE_617___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_617__RX_DCOC_RES_I_617___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_617__RX_DCOC_RES_Q_617___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_617__RX_DCOC_RANGE_617___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_617__RX_DCOC_RANGE_617___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_617__RX_DCOC_RES_I_617___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_617__RX_DCOC_RES_I_617___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_617__RX_DCOC_RES_Q_617___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_617__RX_DCOC_RES_Q_617___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_617___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_617___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_618 (0x005F49A8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_618___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_618___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_618__RX_DCOC_RANGE_618___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_618__RX_DCOC_RES_I_618___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_618__RX_DCOC_RES_Q_618___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_618__RX_DCOC_RANGE_618___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_618__RX_DCOC_RANGE_618___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_618__RX_DCOC_RES_I_618___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_618__RX_DCOC_RES_I_618___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_618__RX_DCOC_RES_Q_618___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_618__RX_DCOC_RES_Q_618___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_618___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_618___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_619 (0x005F49AC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_619___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_619___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_619__RX_DCOC_RANGE_619___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_619__RX_DCOC_RES_I_619___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_619__RX_DCOC_RES_Q_619___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_619__RX_DCOC_RANGE_619___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_619__RX_DCOC_RANGE_619___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_619__RX_DCOC_RES_I_619___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_619__RX_DCOC_RES_I_619___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_619__RX_DCOC_RES_Q_619___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_619__RX_DCOC_RES_Q_619___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_619___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_619___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_620 (0x005F49B0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_620___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_620___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_620__RX_DCOC_RANGE_620___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_620__RX_DCOC_RES_I_620___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_620__RX_DCOC_RES_Q_620___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_620__RX_DCOC_RANGE_620___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_620__RX_DCOC_RANGE_620___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_620__RX_DCOC_RES_I_620___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_620__RX_DCOC_RES_I_620___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_620__RX_DCOC_RES_Q_620___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_620__RX_DCOC_RES_Q_620___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_620___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_620___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_621 (0x005F49B4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_621___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_621___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_621__RX_DCOC_RANGE_621___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_621__RX_DCOC_RES_I_621___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_621__RX_DCOC_RES_Q_621___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_621__RX_DCOC_RANGE_621___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_621__RX_DCOC_RANGE_621___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_621__RX_DCOC_RES_I_621___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_621__RX_DCOC_RES_I_621___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_621__RX_DCOC_RES_Q_621___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_621__RX_DCOC_RES_Q_621___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_621___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_621___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_622 (0x005F49B8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_622___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_622___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_622__RX_DCOC_RANGE_622___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_622__RX_DCOC_RES_I_622___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_622__RX_DCOC_RES_Q_622___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_622__RX_DCOC_RANGE_622___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_622__RX_DCOC_RANGE_622___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_622__RX_DCOC_RES_I_622___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_622__RX_DCOC_RES_I_622___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_622__RX_DCOC_RES_Q_622___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_622__RX_DCOC_RES_Q_622___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_622___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_622___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_623 (0x005F49BC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_623___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_623___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_623__RX_DCOC_RANGE_623___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_623__RX_DCOC_RES_I_623___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_623__RX_DCOC_RES_Q_623___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_623__RX_DCOC_RANGE_623___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_623__RX_DCOC_RANGE_623___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_623__RX_DCOC_RES_I_623___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_623__RX_DCOC_RES_I_623___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_623__RX_DCOC_RES_Q_623___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_623__RX_DCOC_RES_Q_623___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_623___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_623___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_624 (0x005F49C0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_624___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_624___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_624__RX_DCOC_RANGE_624___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_624__RX_DCOC_RES_I_624___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_624__RX_DCOC_RES_Q_624___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_624__RX_DCOC_RANGE_624___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_624__RX_DCOC_RANGE_624___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_624__RX_DCOC_RES_I_624___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_624__RX_DCOC_RES_I_624___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_624__RX_DCOC_RES_Q_624___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_624__RX_DCOC_RES_Q_624___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_624___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_624___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_625 (0x005F49C4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_625___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_625___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_625__RX_DCOC_RANGE_625___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_625__RX_DCOC_RES_I_625___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_625__RX_DCOC_RES_Q_625___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_625__RX_DCOC_RANGE_625___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_625__RX_DCOC_RANGE_625___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_625__RX_DCOC_RES_I_625___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_625__RX_DCOC_RES_I_625___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_625__RX_DCOC_RES_Q_625___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_625__RX_DCOC_RES_Q_625___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_625___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_625___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_626 (0x005F49C8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_626___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_626___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_626__RX_DCOC_RANGE_626___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_626__RX_DCOC_RES_I_626___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_626__RX_DCOC_RES_Q_626___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_626__RX_DCOC_RANGE_626___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_626__RX_DCOC_RANGE_626___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_626__RX_DCOC_RES_I_626___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_626__RX_DCOC_RES_I_626___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_626__RX_DCOC_RES_Q_626___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_626__RX_DCOC_RES_Q_626___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_626___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_626___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_627 (0x005F49CC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_627___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_627___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_627__RX_DCOC_RANGE_627___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_627__RX_DCOC_RES_I_627___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_627__RX_DCOC_RES_Q_627___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_627__RX_DCOC_RANGE_627___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_627__RX_DCOC_RANGE_627___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_627__RX_DCOC_RES_I_627___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_627__RX_DCOC_RES_I_627___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_627__RX_DCOC_RES_Q_627___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_627__RX_DCOC_RES_Q_627___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_627___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_627___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_628 (0x005F49D0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_628___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_628___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_628__RX_DCOC_RANGE_628___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_628__RX_DCOC_RES_I_628___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_628__RX_DCOC_RES_Q_628___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_628__RX_DCOC_RANGE_628___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_628__RX_DCOC_RANGE_628___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_628__RX_DCOC_RES_I_628___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_628__RX_DCOC_RES_I_628___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_628__RX_DCOC_RES_Q_628___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_628__RX_DCOC_RES_Q_628___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_628___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_628___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_629 (0x005F49D4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_629___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_629___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_629__RX_DCOC_RANGE_629___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_629__RX_DCOC_RES_I_629___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_629__RX_DCOC_RES_Q_629___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_629__RX_DCOC_RANGE_629___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_629__RX_DCOC_RANGE_629___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_629__RX_DCOC_RES_I_629___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_629__RX_DCOC_RES_I_629___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_629__RX_DCOC_RES_Q_629___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_629__RX_DCOC_RES_Q_629___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_629___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_629___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_630 (0x005F49D8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_630___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_630___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_630__RX_DCOC_RANGE_630___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_630__RX_DCOC_RES_I_630___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_630__RX_DCOC_RES_Q_630___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_630__RX_DCOC_RANGE_630___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_630__RX_DCOC_RANGE_630___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_630__RX_DCOC_RES_I_630___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_630__RX_DCOC_RES_I_630___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_630__RX_DCOC_RES_Q_630___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_630__RX_DCOC_RES_Q_630___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_630___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_630___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_631 (0x005F49DC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_631___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_631___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_631__RX_DCOC_RANGE_631___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_631__RX_DCOC_RES_I_631___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_631__RX_DCOC_RES_Q_631___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_631__RX_DCOC_RANGE_631___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_631__RX_DCOC_RANGE_631___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_631__RX_DCOC_RES_I_631___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_631__RX_DCOC_RES_I_631___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_631__RX_DCOC_RES_Q_631___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_631__RX_DCOC_RES_Q_631___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_631___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_631___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_632 (0x005F49E0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_632___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_632___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_632__RX_DCOC_RANGE_632___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_632__RX_DCOC_RES_I_632___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_632__RX_DCOC_RES_Q_632___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_632__RX_DCOC_RANGE_632___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_632__RX_DCOC_RANGE_632___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_632__RX_DCOC_RES_I_632___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_632__RX_DCOC_RES_I_632___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_632__RX_DCOC_RES_Q_632___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_632__RX_DCOC_RES_Q_632___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_632___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_632___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_633 (0x005F49E4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_633___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_633___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_633__RX_DCOC_RANGE_633___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_633__RX_DCOC_RES_I_633___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_633__RX_DCOC_RES_Q_633___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_633__RX_DCOC_RANGE_633___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_633__RX_DCOC_RANGE_633___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_633__RX_DCOC_RES_I_633___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_633__RX_DCOC_RES_I_633___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_633__RX_DCOC_RES_Q_633___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_633__RX_DCOC_RES_Q_633___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_633___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_633___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_634 (0x005F49E8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_634___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_634___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_634__RX_DCOC_RANGE_634___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_634__RX_DCOC_RES_I_634___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_634__RX_DCOC_RES_Q_634___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_634__RX_DCOC_RANGE_634___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_634__RX_DCOC_RANGE_634___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_634__RX_DCOC_RES_I_634___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_634__RX_DCOC_RES_I_634___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_634__RX_DCOC_RES_Q_634___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_634__RX_DCOC_RES_Q_634___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_634___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_634___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_635 (0x005F49EC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_635___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_635___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_635__RX_DCOC_RANGE_635___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_635__RX_DCOC_RES_I_635___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_635__RX_DCOC_RES_Q_635___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_635__RX_DCOC_RANGE_635___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_635__RX_DCOC_RANGE_635___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_635__RX_DCOC_RES_I_635___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_635__RX_DCOC_RES_I_635___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_635__RX_DCOC_RES_Q_635___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_635__RX_DCOC_RES_Q_635___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_635___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_635___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_636 (0x005F49F0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_636___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_636___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_636__RX_DCOC_RANGE_636___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_636__RX_DCOC_RES_I_636___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_636__RX_DCOC_RES_Q_636___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_636__RX_DCOC_RANGE_636___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_636__RX_DCOC_RANGE_636___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_636__RX_DCOC_RES_I_636___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_636__RX_DCOC_RES_I_636___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_636__RX_DCOC_RES_Q_636___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_636__RX_DCOC_RES_Q_636___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_636___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_636___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_637 (0x005F49F4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_637___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_637___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_637__RX_DCOC_RANGE_637___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_637__RX_DCOC_RES_I_637___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_637__RX_DCOC_RES_Q_637___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_637__RX_DCOC_RANGE_637___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_637__RX_DCOC_RANGE_637___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_637__RX_DCOC_RES_I_637___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_637__RX_DCOC_RES_I_637___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_637__RX_DCOC_RES_Q_637___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_637__RX_DCOC_RES_Q_637___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_637___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_637___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_638 (0x005F49F8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_638___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_638___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_638__RX_DCOC_RANGE_638___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_638__RX_DCOC_RES_I_638___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_638__RX_DCOC_RES_Q_638___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_638__RX_DCOC_RANGE_638___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_638__RX_DCOC_RANGE_638___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_638__RX_DCOC_RES_I_638___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_638__RX_DCOC_RES_I_638___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_638__RX_DCOC_RES_Q_638___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_638__RX_DCOC_RES_Q_638___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_638___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_638___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_639 (0x005F49FC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_639___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_639___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_639__RX_DCOC_RANGE_639___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_639__RX_DCOC_RES_I_639___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_639__RX_DCOC_RES_Q_639___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_639__RX_DCOC_RANGE_639___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_639__RX_DCOC_RANGE_639___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_639__RX_DCOC_RES_I_639___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_639__RX_DCOC_RES_I_639___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_639__RX_DCOC_RES_Q_639___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_639__RX_DCOC_RES_Q_639___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_639___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_639___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_640 (0x005F4A00) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_640___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_640___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_640__RX_DCOC_RANGE_640___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_640__RX_DCOC_RES_I_640___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_640__RX_DCOC_RES_Q_640___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_640__RX_DCOC_RANGE_640___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_640__RX_DCOC_RANGE_640___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_640__RX_DCOC_RES_I_640___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_640__RX_DCOC_RES_I_640___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_640__RX_DCOC_RES_Q_640___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_640__RX_DCOC_RES_Q_640___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_640___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_640___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_641 (0x005F4A04) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_641___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_641___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_641__RX_DCOC_RANGE_641___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_641__RX_DCOC_RES_I_641___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_641__RX_DCOC_RES_Q_641___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_641__RX_DCOC_RANGE_641___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_641__RX_DCOC_RANGE_641___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_641__RX_DCOC_RES_I_641___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_641__RX_DCOC_RES_I_641___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_641__RX_DCOC_RES_Q_641___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_641__RX_DCOC_RES_Q_641___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_641___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_641___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_642 (0x005F4A08) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_642___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_642___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_642__RX_DCOC_RANGE_642___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_642__RX_DCOC_RES_I_642___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_642__RX_DCOC_RES_Q_642___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_642__RX_DCOC_RANGE_642___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_642__RX_DCOC_RANGE_642___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_642__RX_DCOC_RES_I_642___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_642__RX_DCOC_RES_I_642___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_642__RX_DCOC_RES_Q_642___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_642__RX_DCOC_RES_Q_642___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_642___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_642___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_643 (0x005F4A0C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_643___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_643___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_643__RX_DCOC_RANGE_643___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_643__RX_DCOC_RES_I_643___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_643__RX_DCOC_RES_Q_643___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_643__RX_DCOC_RANGE_643___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_643__RX_DCOC_RANGE_643___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_643__RX_DCOC_RES_I_643___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_643__RX_DCOC_RES_I_643___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_643__RX_DCOC_RES_Q_643___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_643__RX_DCOC_RES_Q_643___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_643___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_643___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_644 (0x005F4A10) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_644___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_644___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_644__RX_DCOC_RANGE_644___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_644__RX_DCOC_RES_I_644___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_644__RX_DCOC_RES_Q_644___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_644__RX_DCOC_RANGE_644___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_644__RX_DCOC_RANGE_644___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_644__RX_DCOC_RES_I_644___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_644__RX_DCOC_RES_I_644___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_644__RX_DCOC_RES_Q_644___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_644__RX_DCOC_RES_Q_644___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_644___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_644___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_645 (0x005F4A14) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_645___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_645___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_645__RX_DCOC_RANGE_645___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_645__RX_DCOC_RES_I_645___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_645__RX_DCOC_RES_Q_645___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_645__RX_DCOC_RANGE_645___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_645__RX_DCOC_RANGE_645___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_645__RX_DCOC_RES_I_645___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_645__RX_DCOC_RES_I_645___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_645__RX_DCOC_RES_Q_645___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_645__RX_DCOC_RES_Q_645___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_645___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_645___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_646 (0x005F4A18) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_646___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_646___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_646__RX_DCOC_RANGE_646___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_646__RX_DCOC_RES_I_646___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_646__RX_DCOC_RES_Q_646___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_646__RX_DCOC_RANGE_646___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_646__RX_DCOC_RANGE_646___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_646__RX_DCOC_RES_I_646___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_646__RX_DCOC_RES_I_646___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_646__RX_DCOC_RES_Q_646___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_646__RX_DCOC_RES_Q_646___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_646___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_646___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_647 (0x005F4A1C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_647___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_647___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_647__RX_DCOC_RANGE_647___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_647__RX_DCOC_RES_I_647___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_647__RX_DCOC_RES_Q_647___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_647__RX_DCOC_RANGE_647___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_647__RX_DCOC_RANGE_647___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_647__RX_DCOC_RES_I_647___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_647__RX_DCOC_RES_I_647___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_647__RX_DCOC_RES_Q_647___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_647__RX_DCOC_RES_Q_647___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_647___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_647___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_648 (0x005F4A20) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_648___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_648___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_648__RX_DCOC_RANGE_648___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_648__RX_DCOC_RES_I_648___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_648__RX_DCOC_RES_Q_648___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_648__RX_DCOC_RANGE_648___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_648__RX_DCOC_RANGE_648___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_648__RX_DCOC_RES_I_648___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_648__RX_DCOC_RES_I_648___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_648__RX_DCOC_RES_Q_648___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_648__RX_DCOC_RES_Q_648___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_648___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_648___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_649 (0x005F4A24) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_649___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_649___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_649__RX_DCOC_RANGE_649___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_649__RX_DCOC_RES_I_649___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_649__RX_DCOC_RES_Q_649___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_649__RX_DCOC_RANGE_649___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_649__RX_DCOC_RANGE_649___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_649__RX_DCOC_RES_I_649___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_649__RX_DCOC_RES_I_649___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_649__RX_DCOC_RES_Q_649___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_649__RX_DCOC_RES_Q_649___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_649___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_649___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_650 (0x005F4A28) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_650___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_650___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_650__RX_DCOC_RANGE_650___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_650__RX_DCOC_RES_I_650___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_650__RX_DCOC_RES_Q_650___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_650__RX_DCOC_RANGE_650___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_650__RX_DCOC_RANGE_650___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_650__RX_DCOC_RES_I_650___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_650__RX_DCOC_RES_I_650___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_650__RX_DCOC_RES_Q_650___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_650__RX_DCOC_RES_Q_650___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_650___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_650___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_651 (0x005F4A2C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_651___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_651___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_651__RX_DCOC_RANGE_651___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_651__RX_DCOC_RES_I_651___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_651__RX_DCOC_RES_Q_651___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_651__RX_DCOC_RANGE_651___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_651__RX_DCOC_RANGE_651___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_651__RX_DCOC_RES_I_651___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_651__RX_DCOC_RES_I_651___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_651__RX_DCOC_RES_Q_651___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_651__RX_DCOC_RES_Q_651___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_651___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_651___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_652 (0x005F4A30) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_652___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_652___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_652__RX_DCOC_RANGE_652___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_652__RX_DCOC_RES_I_652___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_652__RX_DCOC_RES_Q_652___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_652__RX_DCOC_RANGE_652___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_652__RX_DCOC_RANGE_652___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_652__RX_DCOC_RES_I_652___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_652__RX_DCOC_RES_I_652___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_652__RX_DCOC_RES_Q_652___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_652__RX_DCOC_RES_Q_652___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_652___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_652___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_653 (0x005F4A34) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_653___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_653___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_653__RX_DCOC_RANGE_653___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_653__RX_DCOC_RES_I_653___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_653__RX_DCOC_RES_Q_653___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_653__RX_DCOC_RANGE_653___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_653__RX_DCOC_RANGE_653___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_653__RX_DCOC_RES_I_653___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_653__RX_DCOC_RES_I_653___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_653__RX_DCOC_RES_Q_653___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_653__RX_DCOC_RES_Q_653___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_653___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_653___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_654 (0x005F4A38) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_654___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_654___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_654__RX_DCOC_RANGE_654___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_654__RX_DCOC_RES_I_654___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_654__RX_DCOC_RES_Q_654___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_654__RX_DCOC_RANGE_654___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_654__RX_DCOC_RANGE_654___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_654__RX_DCOC_RES_I_654___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_654__RX_DCOC_RES_I_654___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_654__RX_DCOC_RES_Q_654___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_654__RX_DCOC_RES_Q_654___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_654___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_654___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_655 (0x005F4A3C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_655___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_655___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_655__RX_DCOC_RANGE_655___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_655__RX_DCOC_RES_I_655___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_655__RX_DCOC_RES_Q_655___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_655__RX_DCOC_RANGE_655___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_655__RX_DCOC_RANGE_655___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_655__RX_DCOC_RES_I_655___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_655__RX_DCOC_RES_I_655___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_655__RX_DCOC_RES_Q_655___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_655__RX_DCOC_RES_Q_655___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_655___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_655___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_656 (0x005F4A40) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_656___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_656___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_656__RX_DCOC_RANGE_656___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_656__RX_DCOC_RES_I_656___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_656__RX_DCOC_RES_Q_656___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_656__RX_DCOC_RANGE_656___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_656__RX_DCOC_RANGE_656___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_656__RX_DCOC_RES_I_656___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_656__RX_DCOC_RES_I_656___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_656__RX_DCOC_RES_Q_656___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_656__RX_DCOC_RES_Q_656___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_656___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_656___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_657 (0x005F4A44) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_657___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_657___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_657__RX_DCOC_RANGE_657___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_657__RX_DCOC_RES_I_657___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_657__RX_DCOC_RES_Q_657___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_657__RX_DCOC_RANGE_657___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_657__RX_DCOC_RANGE_657___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_657__RX_DCOC_RES_I_657___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_657__RX_DCOC_RES_I_657___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_657__RX_DCOC_RES_Q_657___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_657__RX_DCOC_RES_Q_657___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_657___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_657___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_658 (0x005F4A48) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_658___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_658___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_658__RX_DCOC_RANGE_658___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_658__RX_DCOC_RES_I_658___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_658__RX_DCOC_RES_Q_658___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_658__RX_DCOC_RANGE_658___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_658__RX_DCOC_RANGE_658___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_658__RX_DCOC_RES_I_658___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_658__RX_DCOC_RES_I_658___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_658__RX_DCOC_RES_Q_658___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_658__RX_DCOC_RES_Q_658___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_658___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_658___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_659 (0x005F4A4C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_659___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_659___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_659__RX_DCOC_RANGE_659___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_659__RX_DCOC_RES_I_659___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_659__RX_DCOC_RES_Q_659___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_659__RX_DCOC_RANGE_659___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_659__RX_DCOC_RANGE_659___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_659__RX_DCOC_RES_I_659___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_659__RX_DCOC_RES_I_659___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_659__RX_DCOC_RES_Q_659___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_659__RX_DCOC_RES_Q_659___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_659___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_659___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_660 (0x005F4A50) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_660___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_660___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_660__RX_DCOC_RANGE_660___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_660__RX_DCOC_RES_I_660___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_660__RX_DCOC_RES_Q_660___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_660__RX_DCOC_RANGE_660___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_660__RX_DCOC_RANGE_660___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_660__RX_DCOC_RES_I_660___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_660__RX_DCOC_RES_I_660___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_660__RX_DCOC_RES_Q_660___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_660__RX_DCOC_RES_Q_660___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_660___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_660___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_661 (0x005F4A54) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_661___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_661___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_661__RX_DCOC_RANGE_661___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_661__RX_DCOC_RES_I_661___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_661__RX_DCOC_RES_Q_661___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_661__RX_DCOC_RANGE_661___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_661__RX_DCOC_RANGE_661___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_661__RX_DCOC_RES_I_661___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_661__RX_DCOC_RES_I_661___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_661__RX_DCOC_RES_Q_661___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_661__RX_DCOC_RES_Q_661___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_661___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_661___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_662 (0x005F4A58) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_662___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_662___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_662__RX_DCOC_RANGE_662___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_662__RX_DCOC_RES_I_662___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_662__RX_DCOC_RES_Q_662___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_662__RX_DCOC_RANGE_662___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_662__RX_DCOC_RANGE_662___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_662__RX_DCOC_RES_I_662___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_662__RX_DCOC_RES_I_662___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_662__RX_DCOC_RES_Q_662___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_662__RX_DCOC_RES_Q_662___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_662___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_662___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_663 (0x005F4A5C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_663___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_663___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_663__RX_DCOC_RANGE_663___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_663__RX_DCOC_RES_I_663___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_663__RX_DCOC_RES_Q_663___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_663__RX_DCOC_RANGE_663___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_663__RX_DCOC_RANGE_663___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_663__RX_DCOC_RES_I_663___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_663__RX_DCOC_RES_I_663___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_663__RX_DCOC_RES_Q_663___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_663__RX_DCOC_RES_Q_663___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_663___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_663___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_664 (0x005F4A60) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_664___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_664___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_664__RX_DCOC_RANGE_664___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_664__RX_DCOC_RES_I_664___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_664__RX_DCOC_RES_Q_664___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_664__RX_DCOC_RANGE_664___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_664__RX_DCOC_RANGE_664___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_664__RX_DCOC_RES_I_664___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_664__RX_DCOC_RES_I_664___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_664__RX_DCOC_RES_Q_664___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_664__RX_DCOC_RES_Q_664___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_664___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_664___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_665 (0x005F4A64) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_665___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_665___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_665__RX_DCOC_RANGE_665___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_665__RX_DCOC_RES_I_665___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_665__RX_DCOC_RES_Q_665___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_665__RX_DCOC_RANGE_665___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_665__RX_DCOC_RANGE_665___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_665__RX_DCOC_RES_I_665___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_665__RX_DCOC_RES_I_665___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_665__RX_DCOC_RES_Q_665___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_665__RX_DCOC_RES_Q_665___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_665___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_665___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_666 (0x005F4A68) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_666___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_666___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_666__RX_DCOC_RANGE_666___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_666__RX_DCOC_RES_I_666___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_666__RX_DCOC_RES_Q_666___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_666__RX_DCOC_RANGE_666___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_666__RX_DCOC_RANGE_666___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_666__RX_DCOC_RES_I_666___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_666__RX_DCOC_RES_I_666___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_666__RX_DCOC_RES_Q_666___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_666__RX_DCOC_RES_Q_666___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_666___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_666___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_667 (0x005F4A6C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_667___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_667___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_667__RX_DCOC_RANGE_667___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_667__RX_DCOC_RES_I_667___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_667__RX_DCOC_RES_Q_667___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_667__RX_DCOC_RANGE_667___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_667__RX_DCOC_RANGE_667___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_667__RX_DCOC_RES_I_667___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_667__RX_DCOC_RES_I_667___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_667__RX_DCOC_RES_Q_667___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_667__RX_DCOC_RES_Q_667___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_667___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_667___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_668 (0x005F4A70) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_668___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_668___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_668__RX_DCOC_RANGE_668___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_668__RX_DCOC_RES_I_668___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_668__RX_DCOC_RES_Q_668___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_668__RX_DCOC_RANGE_668___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_668__RX_DCOC_RANGE_668___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_668__RX_DCOC_RES_I_668___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_668__RX_DCOC_RES_I_668___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_668__RX_DCOC_RES_Q_668___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_668__RX_DCOC_RES_Q_668___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_668___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_668___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_669 (0x005F4A74) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_669___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_669___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_669__RX_DCOC_RANGE_669___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_669__RX_DCOC_RES_I_669___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_669__RX_DCOC_RES_Q_669___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_669__RX_DCOC_RANGE_669___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_669__RX_DCOC_RANGE_669___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_669__RX_DCOC_RES_I_669___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_669__RX_DCOC_RES_I_669___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_669__RX_DCOC_RES_Q_669___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_669__RX_DCOC_RES_Q_669___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_669___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_669___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_670 (0x005F4A78) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_670___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_670___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_670__RX_DCOC_RANGE_670___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_670__RX_DCOC_RES_I_670___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_670__RX_DCOC_RES_Q_670___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_670__RX_DCOC_RANGE_670___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_670__RX_DCOC_RANGE_670___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_670__RX_DCOC_RES_I_670___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_670__RX_DCOC_RES_I_670___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_670__RX_DCOC_RES_Q_670___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_670__RX_DCOC_RES_Q_670___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_670___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_670___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_671 (0x005F4A7C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_671___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_671___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_671__RX_DCOC_RANGE_671___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_671__RX_DCOC_RES_I_671___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_671__RX_DCOC_RES_Q_671___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_671__RX_DCOC_RANGE_671___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_671__RX_DCOC_RANGE_671___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_671__RX_DCOC_RES_I_671___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_671__RX_DCOC_RES_I_671___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_671__RX_DCOC_RES_Q_671___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_671__RX_DCOC_RES_Q_671___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_671___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_671___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_672 (0x005F4A80) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_672___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_672___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_672__RX_DCOC_RANGE_672___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_672__RX_DCOC_RES_I_672___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_672__RX_DCOC_RES_Q_672___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_672__RX_DCOC_RANGE_672___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_672__RX_DCOC_RANGE_672___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_672__RX_DCOC_RES_I_672___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_672__RX_DCOC_RES_I_672___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_672__RX_DCOC_RES_Q_672___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_672__RX_DCOC_RES_Q_672___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_672___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_672___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_673 (0x005F4A84) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_673___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_673___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_673__RX_DCOC_RANGE_673___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_673__RX_DCOC_RES_I_673___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_673__RX_DCOC_RES_Q_673___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_673__RX_DCOC_RANGE_673___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_673__RX_DCOC_RANGE_673___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_673__RX_DCOC_RES_I_673___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_673__RX_DCOC_RES_I_673___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_673__RX_DCOC_RES_Q_673___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_673__RX_DCOC_RES_Q_673___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_673___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_673___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_674 (0x005F4A88) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_674___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_674___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_674__RX_DCOC_RANGE_674___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_674__RX_DCOC_RES_I_674___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_674__RX_DCOC_RES_Q_674___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_674__RX_DCOC_RANGE_674___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_674__RX_DCOC_RANGE_674___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_674__RX_DCOC_RES_I_674___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_674__RX_DCOC_RES_I_674___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_674__RX_DCOC_RES_Q_674___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_674__RX_DCOC_RES_Q_674___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_674___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_674___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_675 (0x005F4A8C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_675___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_675___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_675__RX_DCOC_RANGE_675___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_675__RX_DCOC_RES_I_675___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_675__RX_DCOC_RES_Q_675___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_675__RX_DCOC_RANGE_675___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_675__RX_DCOC_RANGE_675___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_675__RX_DCOC_RES_I_675___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_675__RX_DCOC_RES_I_675___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_675__RX_DCOC_RES_Q_675___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_675__RX_DCOC_RES_Q_675___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_675___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_675___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_676 (0x005F4A90) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_676___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_676___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_676__RX_DCOC_RANGE_676___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_676__RX_DCOC_RES_I_676___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_676__RX_DCOC_RES_Q_676___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_676__RX_DCOC_RANGE_676___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_676__RX_DCOC_RANGE_676___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_676__RX_DCOC_RES_I_676___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_676__RX_DCOC_RES_I_676___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_676__RX_DCOC_RES_Q_676___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_676__RX_DCOC_RES_Q_676___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_676___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_676___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_677 (0x005F4A94) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_677___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_677___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_677__RX_DCOC_RANGE_677___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_677__RX_DCOC_RES_I_677___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_677__RX_DCOC_RES_Q_677___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_677__RX_DCOC_RANGE_677___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_677__RX_DCOC_RANGE_677___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_677__RX_DCOC_RES_I_677___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_677__RX_DCOC_RES_I_677___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_677__RX_DCOC_RES_Q_677___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_677__RX_DCOC_RES_Q_677___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_677___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_677___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_678 (0x005F4A98) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_678___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_678___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_678__RX_DCOC_RANGE_678___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_678__RX_DCOC_RES_I_678___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_678__RX_DCOC_RES_Q_678___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_678__RX_DCOC_RANGE_678___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_678__RX_DCOC_RANGE_678___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_678__RX_DCOC_RES_I_678___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_678__RX_DCOC_RES_I_678___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_678__RX_DCOC_RES_Q_678___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_678__RX_DCOC_RES_Q_678___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_678___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_678___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_679 (0x005F4A9C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_679___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_679___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_679__RX_DCOC_RANGE_679___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_679__RX_DCOC_RES_I_679___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_679__RX_DCOC_RES_Q_679___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_679__RX_DCOC_RANGE_679___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_679__RX_DCOC_RANGE_679___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_679__RX_DCOC_RES_I_679___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_679__RX_DCOC_RES_I_679___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_679__RX_DCOC_RES_Q_679___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_679__RX_DCOC_RES_Q_679___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_679___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_679___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_680 (0x005F4AA0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_680___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_680___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_680__RX_DCOC_RANGE_680___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_680__RX_DCOC_RES_I_680___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_680__RX_DCOC_RES_Q_680___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_680__RX_DCOC_RANGE_680___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_680__RX_DCOC_RANGE_680___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_680__RX_DCOC_RES_I_680___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_680__RX_DCOC_RES_I_680___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_680__RX_DCOC_RES_Q_680___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_680__RX_DCOC_RES_Q_680___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_680___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_680___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_681 (0x005F4AA4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_681___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_681___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_681__RX_DCOC_RANGE_681___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_681__RX_DCOC_RES_I_681___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_681__RX_DCOC_RES_Q_681___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_681__RX_DCOC_RANGE_681___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_681__RX_DCOC_RANGE_681___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_681__RX_DCOC_RES_I_681___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_681__RX_DCOC_RES_I_681___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_681__RX_DCOC_RES_Q_681___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_681__RX_DCOC_RES_Q_681___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_681___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_681___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_682 (0x005F4AA8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_682___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_682___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_682__RX_DCOC_RANGE_682___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_682__RX_DCOC_RES_I_682___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_682__RX_DCOC_RES_Q_682___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_682__RX_DCOC_RANGE_682___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_682__RX_DCOC_RANGE_682___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_682__RX_DCOC_RES_I_682___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_682__RX_DCOC_RES_I_682___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_682__RX_DCOC_RES_Q_682___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_682__RX_DCOC_RES_Q_682___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_682___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_682___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_683 (0x005F4AAC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_683___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_683___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_683__RX_DCOC_RANGE_683___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_683__RX_DCOC_RES_I_683___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_683__RX_DCOC_RES_Q_683___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_683__RX_DCOC_RANGE_683___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_683__RX_DCOC_RANGE_683___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_683__RX_DCOC_RES_I_683___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_683__RX_DCOC_RES_I_683___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_683__RX_DCOC_RES_Q_683___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_683__RX_DCOC_RES_Q_683___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_683___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_683___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_684 (0x005F4AB0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_684___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_684___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_684__RX_DCOC_RANGE_684___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_684__RX_DCOC_RES_I_684___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_684__RX_DCOC_RES_Q_684___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_684__RX_DCOC_RANGE_684___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_684__RX_DCOC_RANGE_684___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_684__RX_DCOC_RES_I_684___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_684__RX_DCOC_RES_I_684___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_684__RX_DCOC_RES_Q_684___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_684__RX_DCOC_RES_Q_684___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_684___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_684___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_685 (0x005F4AB4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_685___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_685___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_685__RX_DCOC_RANGE_685___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_685__RX_DCOC_RES_I_685___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_685__RX_DCOC_RES_Q_685___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_685__RX_DCOC_RANGE_685___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_685__RX_DCOC_RANGE_685___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_685__RX_DCOC_RES_I_685___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_685__RX_DCOC_RES_I_685___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_685__RX_DCOC_RES_Q_685___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_685__RX_DCOC_RES_Q_685___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_685___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_685___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_686 (0x005F4AB8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_686___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_686___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_686__RX_DCOC_RANGE_686___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_686__RX_DCOC_RES_I_686___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_686__RX_DCOC_RES_Q_686___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_686__RX_DCOC_RANGE_686___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_686__RX_DCOC_RANGE_686___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_686__RX_DCOC_RES_I_686___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_686__RX_DCOC_RES_I_686___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_686__RX_DCOC_RES_Q_686___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_686__RX_DCOC_RES_Q_686___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_686___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_686___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_687 (0x005F4ABC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_687___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_687___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_687__RX_DCOC_RANGE_687___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_687__RX_DCOC_RES_I_687___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_687__RX_DCOC_RES_Q_687___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_687__RX_DCOC_RANGE_687___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_687__RX_DCOC_RANGE_687___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_687__RX_DCOC_RES_I_687___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_687__RX_DCOC_RES_I_687___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_687__RX_DCOC_RES_Q_687___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_687__RX_DCOC_RES_Q_687___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_687___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_687___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_688 (0x005F4AC0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_688___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_688___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_688__RX_DCOC_RANGE_688___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_688__RX_DCOC_RES_I_688___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_688__RX_DCOC_RES_Q_688___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_688__RX_DCOC_RANGE_688___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_688__RX_DCOC_RANGE_688___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_688__RX_DCOC_RES_I_688___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_688__RX_DCOC_RES_I_688___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_688__RX_DCOC_RES_Q_688___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_688__RX_DCOC_RES_Q_688___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_688___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_688___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_689 (0x005F4AC4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_689___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_689___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_689__RX_DCOC_RANGE_689___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_689__RX_DCOC_RES_I_689___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_689__RX_DCOC_RES_Q_689___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_689__RX_DCOC_RANGE_689___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_689__RX_DCOC_RANGE_689___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_689__RX_DCOC_RES_I_689___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_689__RX_DCOC_RES_I_689___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_689__RX_DCOC_RES_Q_689___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_689__RX_DCOC_RES_Q_689___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_689___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_689___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_690 (0x005F4AC8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_690___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_690___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_690__RX_DCOC_RANGE_690___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_690__RX_DCOC_RES_I_690___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_690__RX_DCOC_RES_Q_690___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_690__RX_DCOC_RANGE_690___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_690__RX_DCOC_RANGE_690___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_690__RX_DCOC_RES_I_690___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_690__RX_DCOC_RES_I_690___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_690__RX_DCOC_RES_Q_690___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_690__RX_DCOC_RES_Q_690___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_690___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_690___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_691 (0x005F4ACC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_691___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_691___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_691__RX_DCOC_RANGE_691___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_691__RX_DCOC_RES_I_691___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_691__RX_DCOC_RES_Q_691___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_691__RX_DCOC_RANGE_691___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_691__RX_DCOC_RANGE_691___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_691__RX_DCOC_RES_I_691___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_691__RX_DCOC_RES_I_691___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_691__RX_DCOC_RES_Q_691___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_691__RX_DCOC_RES_Q_691___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_691___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_691___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_692 (0x005F4AD0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_692___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_692___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_692__RX_DCOC_RANGE_692___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_692__RX_DCOC_RES_I_692___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_692__RX_DCOC_RES_Q_692___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_692__RX_DCOC_RANGE_692___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_692__RX_DCOC_RANGE_692___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_692__RX_DCOC_RES_I_692___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_692__RX_DCOC_RES_I_692___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_692__RX_DCOC_RES_Q_692___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_692__RX_DCOC_RES_Q_692___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_692___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_692___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_693 (0x005F4AD4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_693___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_693___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_693__RX_DCOC_RANGE_693___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_693__RX_DCOC_RES_I_693___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_693__RX_DCOC_RES_Q_693___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_693__RX_DCOC_RANGE_693___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_693__RX_DCOC_RANGE_693___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_693__RX_DCOC_RES_I_693___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_693__RX_DCOC_RES_I_693___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_693__RX_DCOC_RES_Q_693___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_693__RX_DCOC_RES_Q_693___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_693___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_693___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_694 (0x005F4AD8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_694___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_694___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_694__RX_DCOC_RANGE_694___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_694__RX_DCOC_RES_I_694___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_694__RX_DCOC_RES_Q_694___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_694__RX_DCOC_RANGE_694___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_694__RX_DCOC_RANGE_694___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_694__RX_DCOC_RES_I_694___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_694__RX_DCOC_RES_I_694___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_694__RX_DCOC_RES_Q_694___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_694__RX_DCOC_RES_Q_694___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_694___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_694___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_695 (0x005F4ADC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_695___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_695___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_695__RX_DCOC_RANGE_695___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_695__RX_DCOC_RES_I_695___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_695__RX_DCOC_RES_Q_695___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_695__RX_DCOC_RANGE_695___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_695__RX_DCOC_RANGE_695___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_695__RX_DCOC_RES_I_695___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_695__RX_DCOC_RES_I_695___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_695__RX_DCOC_RES_Q_695___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_695__RX_DCOC_RES_Q_695___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_695___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_695___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_696 (0x005F4AE0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_696___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_696___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_696__RX_DCOC_RANGE_696___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_696__RX_DCOC_RES_I_696___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_696__RX_DCOC_RES_Q_696___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_696__RX_DCOC_RANGE_696___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_696__RX_DCOC_RANGE_696___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_696__RX_DCOC_RES_I_696___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_696__RX_DCOC_RES_I_696___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_696__RX_DCOC_RES_Q_696___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_696__RX_DCOC_RES_Q_696___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_696___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_696___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_697 (0x005F4AE4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_697___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_697___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_697__RX_DCOC_RANGE_697___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_697__RX_DCOC_RES_I_697___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_697__RX_DCOC_RES_Q_697___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_697__RX_DCOC_RANGE_697___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_697__RX_DCOC_RANGE_697___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_697__RX_DCOC_RES_I_697___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_697__RX_DCOC_RES_I_697___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_697__RX_DCOC_RES_Q_697___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_697__RX_DCOC_RES_Q_697___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_697___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_697___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_698 (0x005F4AE8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_698___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_698___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_698__RX_DCOC_RANGE_698___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_698__RX_DCOC_RES_I_698___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_698__RX_DCOC_RES_Q_698___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_698__RX_DCOC_RANGE_698___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_698__RX_DCOC_RANGE_698___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_698__RX_DCOC_RES_I_698___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_698__RX_DCOC_RES_I_698___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_698__RX_DCOC_RES_Q_698___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_698__RX_DCOC_RES_Q_698___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_698___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_698___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_699 (0x005F4AEC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_699___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_699___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_699__RX_DCOC_RANGE_699___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_699__RX_DCOC_RES_I_699___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_699__RX_DCOC_RES_Q_699___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_699__RX_DCOC_RANGE_699___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_699__RX_DCOC_RANGE_699___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_699__RX_DCOC_RES_I_699___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_699__RX_DCOC_RES_I_699___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_699__RX_DCOC_RES_Q_699___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_699__RX_DCOC_RES_Q_699___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_699___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_699___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_700 (0x005F4AF0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_700___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_700___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_700__RX_DCOC_RANGE_700___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_700__RX_DCOC_RES_I_700___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_700__RX_DCOC_RES_Q_700___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_700__RX_DCOC_RANGE_700___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_700__RX_DCOC_RANGE_700___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_700__RX_DCOC_RES_I_700___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_700__RX_DCOC_RES_I_700___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_700__RX_DCOC_RES_Q_700___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_700__RX_DCOC_RES_Q_700___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_700___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_700___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_701 (0x005F4AF4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_701___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_701___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_701__RX_DCOC_RANGE_701___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_701__RX_DCOC_RES_I_701___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_701__RX_DCOC_RES_Q_701___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_701__RX_DCOC_RANGE_701___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_701__RX_DCOC_RANGE_701___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_701__RX_DCOC_RES_I_701___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_701__RX_DCOC_RES_I_701___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_701__RX_DCOC_RES_Q_701___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_701__RX_DCOC_RES_Q_701___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_701___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_701___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_702 (0x005F4AF8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_702___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_702___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_702__RX_DCOC_RANGE_702___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_702__RX_DCOC_RES_I_702___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_702__RX_DCOC_RES_Q_702___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_702__RX_DCOC_RANGE_702___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_702__RX_DCOC_RANGE_702___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_702__RX_DCOC_RES_I_702___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_702__RX_DCOC_RES_I_702___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_702__RX_DCOC_RES_Q_702___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_702__RX_DCOC_RES_Q_702___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_702___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_702___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_703 (0x005F4AFC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_703___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_703___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_703__RX_DCOC_RANGE_703___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_703__RX_DCOC_RES_I_703___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_703__RX_DCOC_RES_Q_703___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_703__RX_DCOC_RANGE_703___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_703__RX_DCOC_RANGE_703___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_703__RX_DCOC_RES_I_703___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_703__RX_DCOC_RES_I_703___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_703__RX_DCOC_RES_Q_703___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_703__RX_DCOC_RES_Q_703___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_703___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_703___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_704 (0x005F4B00) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_704___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_704___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_704__RX_DCOC_RANGE_704___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_704__RX_DCOC_RES_I_704___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_704__RX_DCOC_RES_Q_704___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_704__RX_DCOC_RANGE_704___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_704__RX_DCOC_RANGE_704___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_704__RX_DCOC_RES_I_704___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_704__RX_DCOC_RES_I_704___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_704__RX_DCOC_RES_Q_704___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_704__RX_DCOC_RES_Q_704___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_704___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_704___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_705 (0x005F4B04) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_705___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_705___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_705__RX_DCOC_RANGE_705___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_705__RX_DCOC_RES_I_705___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_705__RX_DCOC_RES_Q_705___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_705__RX_DCOC_RANGE_705___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_705__RX_DCOC_RANGE_705___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_705__RX_DCOC_RES_I_705___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_705__RX_DCOC_RES_I_705___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_705__RX_DCOC_RES_Q_705___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_705__RX_DCOC_RES_Q_705___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_705___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_705___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_706 (0x005F4B08) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_706___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_706___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_706__RX_DCOC_RANGE_706___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_706__RX_DCOC_RES_I_706___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_706__RX_DCOC_RES_Q_706___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_706__RX_DCOC_RANGE_706___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_706__RX_DCOC_RANGE_706___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_706__RX_DCOC_RES_I_706___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_706__RX_DCOC_RES_I_706___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_706__RX_DCOC_RES_Q_706___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_706__RX_DCOC_RES_Q_706___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_706___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_706___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_707 (0x005F4B0C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_707___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_707___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_707__RX_DCOC_RANGE_707___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_707__RX_DCOC_RES_I_707___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_707__RX_DCOC_RES_Q_707___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_707__RX_DCOC_RANGE_707___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_707__RX_DCOC_RANGE_707___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_707__RX_DCOC_RES_I_707___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_707__RX_DCOC_RES_I_707___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_707__RX_DCOC_RES_Q_707___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_707__RX_DCOC_RES_Q_707___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_707___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_707___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_708 (0x005F4B10) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_708___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_708___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_708__RX_DCOC_RANGE_708___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_708__RX_DCOC_RES_I_708___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_708__RX_DCOC_RES_Q_708___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_708__RX_DCOC_RANGE_708___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_708__RX_DCOC_RANGE_708___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_708__RX_DCOC_RES_I_708___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_708__RX_DCOC_RES_I_708___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_708__RX_DCOC_RES_Q_708___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_708__RX_DCOC_RES_Q_708___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_708___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_708___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_709 (0x005F4B14) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_709___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_709___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_709__RX_DCOC_RANGE_709___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_709__RX_DCOC_RES_I_709___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_709__RX_DCOC_RES_Q_709___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_709__RX_DCOC_RANGE_709___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_709__RX_DCOC_RANGE_709___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_709__RX_DCOC_RES_I_709___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_709__RX_DCOC_RES_I_709___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_709__RX_DCOC_RES_Q_709___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_709__RX_DCOC_RES_Q_709___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_709___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_709___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_710 (0x005F4B18) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_710___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_710___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_710__RX_DCOC_RANGE_710___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_710__RX_DCOC_RES_I_710___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_710__RX_DCOC_RES_Q_710___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_710__RX_DCOC_RANGE_710___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_710__RX_DCOC_RANGE_710___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_710__RX_DCOC_RES_I_710___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_710__RX_DCOC_RES_I_710___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_710__RX_DCOC_RES_Q_710___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_710__RX_DCOC_RES_Q_710___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_710___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_710___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_711 (0x005F4B1C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_711___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_711___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_711__RX_DCOC_RANGE_711___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_711__RX_DCOC_RES_I_711___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_711__RX_DCOC_RES_Q_711___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_711__RX_DCOC_RANGE_711___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_711__RX_DCOC_RANGE_711___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_711__RX_DCOC_RES_I_711___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_711__RX_DCOC_RES_I_711___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_711__RX_DCOC_RES_Q_711___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_711__RX_DCOC_RES_Q_711___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_711___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_711___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_712 (0x005F4B20) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_712___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_712___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_712__RX_DCOC_RANGE_712___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_712__RX_DCOC_RES_I_712___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_712__RX_DCOC_RES_Q_712___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_712__RX_DCOC_RANGE_712___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_712__RX_DCOC_RANGE_712___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_712__RX_DCOC_RES_I_712___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_712__RX_DCOC_RES_I_712___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_712__RX_DCOC_RES_Q_712___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_712__RX_DCOC_RES_Q_712___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_712___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_712___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_713 (0x005F4B24) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_713___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_713___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_713__RX_DCOC_RANGE_713___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_713__RX_DCOC_RES_I_713___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_713__RX_DCOC_RES_Q_713___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_713__RX_DCOC_RANGE_713___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_713__RX_DCOC_RANGE_713___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_713__RX_DCOC_RES_I_713___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_713__RX_DCOC_RES_I_713___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_713__RX_DCOC_RES_Q_713___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_713__RX_DCOC_RES_Q_713___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_713___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_713___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_714 (0x005F4B28) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_714___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_714___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_714__RX_DCOC_RANGE_714___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_714__RX_DCOC_RES_I_714___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_714__RX_DCOC_RES_Q_714___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_714__RX_DCOC_RANGE_714___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_714__RX_DCOC_RANGE_714___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_714__RX_DCOC_RES_I_714___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_714__RX_DCOC_RES_I_714___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_714__RX_DCOC_RES_Q_714___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_714__RX_DCOC_RES_Q_714___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_714___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_714___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_715 (0x005F4B2C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_715___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_715___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_715__RX_DCOC_RANGE_715___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_715__RX_DCOC_RES_I_715___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_715__RX_DCOC_RES_Q_715___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_715__RX_DCOC_RANGE_715___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_715__RX_DCOC_RANGE_715___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_715__RX_DCOC_RES_I_715___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_715__RX_DCOC_RES_I_715___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_715__RX_DCOC_RES_Q_715___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_715__RX_DCOC_RES_Q_715___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_715___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_715___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_716 (0x005F4B30) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_716___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_716___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_716__RX_DCOC_RANGE_716___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_716__RX_DCOC_RES_I_716___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_716__RX_DCOC_RES_Q_716___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_716__RX_DCOC_RANGE_716___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_716__RX_DCOC_RANGE_716___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_716__RX_DCOC_RES_I_716___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_716__RX_DCOC_RES_I_716___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_716__RX_DCOC_RES_Q_716___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_716__RX_DCOC_RES_Q_716___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_716___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_716___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_717 (0x005F4B34) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_717___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_717___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_717__RX_DCOC_RANGE_717___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_717__RX_DCOC_RES_I_717___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_717__RX_DCOC_RES_Q_717___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_717__RX_DCOC_RANGE_717___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_717__RX_DCOC_RANGE_717___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_717__RX_DCOC_RES_I_717___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_717__RX_DCOC_RES_I_717___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_717__RX_DCOC_RES_Q_717___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_717__RX_DCOC_RES_Q_717___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_717___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_717___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_718 (0x005F4B38) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_718___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_718___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_718__RX_DCOC_RANGE_718___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_718__RX_DCOC_RES_I_718___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_718__RX_DCOC_RES_Q_718___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_718__RX_DCOC_RANGE_718___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_718__RX_DCOC_RANGE_718___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_718__RX_DCOC_RES_I_718___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_718__RX_DCOC_RES_I_718___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_718__RX_DCOC_RES_Q_718___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_718__RX_DCOC_RES_Q_718___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_718___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_718___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_719 (0x005F4B3C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_719___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_719___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_719__RX_DCOC_RANGE_719___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_719__RX_DCOC_RES_I_719___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_719__RX_DCOC_RES_Q_719___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_719__RX_DCOC_RANGE_719___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_719__RX_DCOC_RANGE_719___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_719__RX_DCOC_RES_I_719___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_719__RX_DCOC_RES_I_719___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_719__RX_DCOC_RES_Q_719___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_719__RX_DCOC_RES_Q_719___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_719___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_719___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_720 (0x005F4B40) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_720___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_720___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_720__RX_DCOC_RANGE_720___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_720__RX_DCOC_RES_I_720___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_720__RX_DCOC_RES_Q_720___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_720__RX_DCOC_RANGE_720___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_720__RX_DCOC_RANGE_720___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_720__RX_DCOC_RES_I_720___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_720__RX_DCOC_RES_I_720___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_720__RX_DCOC_RES_Q_720___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_720__RX_DCOC_RES_Q_720___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_720___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_720___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_721 (0x005F4B44) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_721___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_721___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_721__RX_DCOC_RANGE_721___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_721__RX_DCOC_RES_I_721___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_721__RX_DCOC_RES_Q_721___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_721__RX_DCOC_RANGE_721___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_721__RX_DCOC_RANGE_721___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_721__RX_DCOC_RES_I_721___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_721__RX_DCOC_RES_I_721___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_721__RX_DCOC_RES_Q_721___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_721__RX_DCOC_RES_Q_721___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_721___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_721___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_722 (0x005F4B48) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_722___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_722___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_722__RX_DCOC_RANGE_722___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_722__RX_DCOC_RES_I_722___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_722__RX_DCOC_RES_Q_722___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_722__RX_DCOC_RANGE_722___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_722__RX_DCOC_RANGE_722___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_722__RX_DCOC_RES_I_722___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_722__RX_DCOC_RES_I_722___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_722__RX_DCOC_RES_Q_722___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_722__RX_DCOC_RES_Q_722___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_722___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_722___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_723 (0x005F4B4C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_723___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_723___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_723__RX_DCOC_RANGE_723___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_723__RX_DCOC_RES_I_723___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_723__RX_DCOC_RES_Q_723___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_723__RX_DCOC_RANGE_723___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_723__RX_DCOC_RANGE_723___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_723__RX_DCOC_RES_I_723___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_723__RX_DCOC_RES_I_723___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_723__RX_DCOC_RES_Q_723___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_723__RX_DCOC_RES_Q_723___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_723___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_723___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_724 (0x005F4B50) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_724___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_724___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_724__RX_DCOC_RANGE_724___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_724__RX_DCOC_RES_I_724___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_724__RX_DCOC_RES_Q_724___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_724__RX_DCOC_RANGE_724___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_724__RX_DCOC_RANGE_724___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_724__RX_DCOC_RES_I_724___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_724__RX_DCOC_RES_I_724___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_724__RX_DCOC_RES_Q_724___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_724__RX_DCOC_RES_Q_724___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_724___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_724___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_725 (0x005F4B54) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_725___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_725___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_725__RX_DCOC_RANGE_725___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_725__RX_DCOC_RES_I_725___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_725__RX_DCOC_RES_Q_725___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_725__RX_DCOC_RANGE_725___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_725__RX_DCOC_RANGE_725___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_725__RX_DCOC_RES_I_725___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_725__RX_DCOC_RES_I_725___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_725__RX_DCOC_RES_Q_725___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_725__RX_DCOC_RES_Q_725___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_725___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_725___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_726 (0x005F4B58) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_726___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_726___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_726__RX_DCOC_RANGE_726___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_726__RX_DCOC_RES_I_726___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_726__RX_DCOC_RES_Q_726___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_726__RX_DCOC_RANGE_726___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_726__RX_DCOC_RANGE_726___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_726__RX_DCOC_RES_I_726___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_726__RX_DCOC_RES_I_726___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_726__RX_DCOC_RES_Q_726___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_726__RX_DCOC_RES_Q_726___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_726___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_726___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_727 (0x005F4B5C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_727___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_727___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_727__RX_DCOC_RANGE_727___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_727__RX_DCOC_RES_I_727___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_727__RX_DCOC_RES_Q_727___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_727__RX_DCOC_RANGE_727___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_727__RX_DCOC_RANGE_727___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_727__RX_DCOC_RES_I_727___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_727__RX_DCOC_RES_I_727___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_727__RX_DCOC_RES_Q_727___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_727__RX_DCOC_RES_Q_727___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_727___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_727___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_728 (0x005F4B60) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_728___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_728___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_728__RX_DCOC_RANGE_728___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_728__RX_DCOC_RES_I_728___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_728__RX_DCOC_RES_Q_728___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_728__RX_DCOC_RANGE_728___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_728__RX_DCOC_RANGE_728___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_728__RX_DCOC_RES_I_728___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_728__RX_DCOC_RES_I_728___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_728__RX_DCOC_RES_Q_728___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_728__RX_DCOC_RES_Q_728___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_728___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_728___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_729 (0x005F4B64) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_729___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_729___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_729__RX_DCOC_RANGE_729___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_729__RX_DCOC_RES_I_729___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_729__RX_DCOC_RES_Q_729___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_729__RX_DCOC_RANGE_729___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_729__RX_DCOC_RANGE_729___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_729__RX_DCOC_RES_I_729___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_729__RX_DCOC_RES_I_729___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_729__RX_DCOC_RES_Q_729___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_729__RX_DCOC_RES_Q_729___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_729___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_729___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_730 (0x005F4B68) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_730___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_730___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_730__RX_DCOC_RANGE_730___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_730__RX_DCOC_RES_I_730___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_730__RX_DCOC_RES_Q_730___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_730__RX_DCOC_RANGE_730___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_730__RX_DCOC_RANGE_730___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_730__RX_DCOC_RES_I_730___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_730__RX_DCOC_RES_I_730___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_730__RX_DCOC_RES_Q_730___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_730__RX_DCOC_RES_Q_730___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_730___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_730___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_731 (0x005F4B6C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_731___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_731___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_731__RX_DCOC_RANGE_731___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_731__RX_DCOC_RES_I_731___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_731__RX_DCOC_RES_Q_731___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_731__RX_DCOC_RANGE_731___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_731__RX_DCOC_RANGE_731___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_731__RX_DCOC_RES_I_731___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_731__RX_DCOC_RES_I_731___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_731__RX_DCOC_RES_Q_731___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_731__RX_DCOC_RES_Q_731___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_731___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_731___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_732 (0x005F4B70) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_732___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_732___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_732__RX_DCOC_RANGE_732___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_732__RX_DCOC_RES_I_732___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_732__RX_DCOC_RES_Q_732___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_732__RX_DCOC_RANGE_732___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_732__RX_DCOC_RANGE_732___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_732__RX_DCOC_RES_I_732___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_732__RX_DCOC_RES_I_732___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_732__RX_DCOC_RES_Q_732___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_732__RX_DCOC_RES_Q_732___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_732___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_732___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_733 (0x005F4B74) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_733___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_733___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_733__RX_DCOC_RANGE_733___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_733__RX_DCOC_RES_I_733___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_733__RX_DCOC_RES_Q_733___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_733__RX_DCOC_RANGE_733___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_733__RX_DCOC_RANGE_733___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_733__RX_DCOC_RES_I_733___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_733__RX_DCOC_RES_I_733___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_733__RX_DCOC_RES_Q_733___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_733__RX_DCOC_RES_Q_733___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_733___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_733___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_734 (0x005F4B78) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_734___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_734___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_734__RX_DCOC_RANGE_734___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_734__RX_DCOC_RES_I_734___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_734__RX_DCOC_RES_Q_734___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_734__RX_DCOC_RANGE_734___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_734__RX_DCOC_RANGE_734___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_734__RX_DCOC_RES_I_734___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_734__RX_DCOC_RES_I_734___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_734__RX_DCOC_RES_Q_734___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_734__RX_DCOC_RES_Q_734___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_734___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_734___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_735 (0x005F4B7C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_735___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_735___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_735__RX_DCOC_RANGE_735___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_735__RX_DCOC_RES_I_735___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_735__RX_DCOC_RES_Q_735___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_735__RX_DCOC_RANGE_735___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_735__RX_DCOC_RANGE_735___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_735__RX_DCOC_RES_I_735___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_735__RX_DCOC_RES_I_735___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_735__RX_DCOC_RES_Q_735___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_735__RX_DCOC_RES_Q_735___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_735___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_735___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_736 (0x005F4B80) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_736___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_736___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_736__RX_DCOC_RANGE_736___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_736__RX_DCOC_RES_I_736___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_736__RX_DCOC_RES_Q_736___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_736__RX_DCOC_RANGE_736___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_736__RX_DCOC_RANGE_736___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_736__RX_DCOC_RES_I_736___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_736__RX_DCOC_RES_I_736___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_736__RX_DCOC_RES_Q_736___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_736__RX_DCOC_RES_Q_736___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_736___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_736___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_737 (0x005F4B84) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_737___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_737___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_737__RX_DCOC_RANGE_737___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_737__RX_DCOC_RES_I_737___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_737__RX_DCOC_RES_Q_737___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_737__RX_DCOC_RANGE_737___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_737__RX_DCOC_RANGE_737___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_737__RX_DCOC_RES_I_737___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_737__RX_DCOC_RES_I_737___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_737__RX_DCOC_RES_Q_737___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_737__RX_DCOC_RES_Q_737___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_737___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_737___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_738 (0x005F4B88) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_738___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_738___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_738__RX_DCOC_RANGE_738___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_738__RX_DCOC_RES_I_738___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_738__RX_DCOC_RES_Q_738___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_738__RX_DCOC_RANGE_738___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_738__RX_DCOC_RANGE_738___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_738__RX_DCOC_RES_I_738___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_738__RX_DCOC_RES_I_738___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_738__RX_DCOC_RES_Q_738___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_738__RX_DCOC_RES_Q_738___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_738___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_738___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_739 (0x005F4B8C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_739___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_739___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_739__RX_DCOC_RANGE_739___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_739__RX_DCOC_RES_I_739___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_739__RX_DCOC_RES_Q_739___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_739__RX_DCOC_RANGE_739___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_739__RX_DCOC_RANGE_739___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_739__RX_DCOC_RES_I_739___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_739__RX_DCOC_RES_I_739___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_739__RX_DCOC_RES_Q_739___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_739__RX_DCOC_RES_Q_739___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_739___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_739___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_740 (0x005F4B90) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_740___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_740___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_740__RX_DCOC_RANGE_740___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_740__RX_DCOC_RES_I_740___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_740__RX_DCOC_RES_Q_740___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_740__RX_DCOC_RANGE_740___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_740__RX_DCOC_RANGE_740___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_740__RX_DCOC_RES_I_740___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_740__RX_DCOC_RES_I_740___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_740__RX_DCOC_RES_Q_740___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_740__RX_DCOC_RES_Q_740___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_740___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_740___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_741 (0x005F4B94) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_741___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_741___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_741__RX_DCOC_RANGE_741___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_741__RX_DCOC_RES_I_741___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_741__RX_DCOC_RES_Q_741___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_741__RX_DCOC_RANGE_741___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_741__RX_DCOC_RANGE_741___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_741__RX_DCOC_RES_I_741___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_741__RX_DCOC_RES_I_741___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_741__RX_DCOC_RES_Q_741___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_741__RX_DCOC_RES_Q_741___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_741___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_741___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_742 (0x005F4B98) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_742___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_742___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_742__RX_DCOC_RANGE_742___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_742__RX_DCOC_RES_I_742___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_742__RX_DCOC_RES_Q_742___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_742__RX_DCOC_RANGE_742___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_742__RX_DCOC_RANGE_742___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_742__RX_DCOC_RES_I_742___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_742__RX_DCOC_RES_I_742___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_742__RX_DCOC_RES_Q_742___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_742__RX_DCOC_RES_Q_742___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_742___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_742___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_743 (0x005F4B9C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_743___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_743___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_743__RX_DCOC_RANGE_743___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_743__RX_DCOC_RES_I_743___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_743__RX_DCOC_RES_Q_743___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_743__RX_DCOC_RANGE_743___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_743__RX_DCOC_RANGE_743___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_743__RX_DCOC_RES_I_743___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_743__RX_DCOC_RES_I_743___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_743__RX_DCOC_RES_Q_743___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_743__RX_DCOC_RES_Q_743___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_743___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_743___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_744 (0x005F4BA0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_744___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_744___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_744__RX_DCOC_RANGE_744___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_744__RX_DCOC_RES_I_744___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_744__RX_DCOC_RES_Q_744___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_744__RX_DCOC_RANGE_744___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_744__RX_DCOC_RANGE_744___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_744__RX_DCOC_RES_I_744___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_744__RX_DCOC_RES_I_744___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_744__RX_DCOC_RES_Q_744___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_744__RX_DCOC_RES_Q_744___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_744___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_744___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_745 (0x005F4BA4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_745___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_745___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_745__RX_DCOC_RANGE_745___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_745__RX_DCOC_RES_I_745___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_745__RX_DCOC_RES_Q_745___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_745__RX_DCOC_RANGE_745___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_745__RX_DCOC_RANGE_745___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_745__RX_DCOC_RES_I_745___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_745__RX_DCOC_RES_I_745___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_745__RX_DCOC_RES_Q_745___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_745__RX_DCOC_RES_Q_745___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_745___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_745___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_746 (0x005F4BA8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_746___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_746___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_746__RX_DCOC_RANGE_746___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_746__RX_DCOC_RES_I_746___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_746__RX_DCOC_RES_Q_746___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_746__RX_DCOC_RANGE_746___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_746__RX_DCOC_RANGE_746___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_746__RX_DCOC_RES_I_746___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_746__RX_DCOC_RES_I_746___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_746__RX_DCOC_RES_Q_746___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_746__RX_DCOC_RES_Q_746___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_746___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_746___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_747 (0x005F4BAC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_747___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_747___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_747__RX_DCOC_RANGE_747___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_747__RX_DCOC_RES_I_747___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_747__RX_DCOC_RES_Q_747___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_747__RX_DCOC_RANGE_747___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_747__RX_DCOC_RANGE_747___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_747__RX_DCOC_RES_I_747___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_747__RX_DCOC_RES_I_747___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_747__RX_DCOC_RES_Q_747___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_747__RX_DCOC_RES_Q_747___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_747___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_747___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_748 (0x005F4BB0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_748___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_748___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_748__RX_DCOC_RANGE_748___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_748__RX_DCOC_RES_I_748___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_748__RX_DCOC_RES_Q_748___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_748__RX_DCOC_RANGE_748___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_748__RX_DCOC_RANGE_748___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_748__RX_DCOC_RES_I_748___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_748__RX_DCOC_RES_I_748___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_748__RX_DCOC_RES_Q_748___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_748__RX_DCOC_RES_Q_748___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_748___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_748___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_749 (0x005F4BB4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_749___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_749___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_749__RX_DCOC_RANGE_749___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_749__RX_DCOC_RES_I_749___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_749__RX_DCOC_RES_Q_749___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_749__RX_DCOC_RANGE_749___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_749__RX_DCOC_RANGE_749___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_749__RX_DCOC_RES_I_749___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_749__RX_DCOC_RES_I_749___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_749__RX_DCOC_RES_Q_749___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_749__RX_DCOC_RES_Q_749___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_749___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_749___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_750 (0x005F4BB8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_750___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_750___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_750__RX_DCOC_RANGE_750___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_750__RX_DCOC_RES_I_750___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_750__RX_DCOC_RES_Q_750___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_750__RX_DCOC_RANGE_750___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_750__RX_DCOC_RANGE_750___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_750__RX_DCOC_RES_I_750___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_750__RX_DCOC_RES_I_750___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_750__RX_DCOC_RES_Q_750___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_750__RX_DCOC_RES_Q_750___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_750___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_750___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_751 (0x005F4BBC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_751___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_751___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_751__RX_DCOC_RANGE_751___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_751__RX_DCOC_RES_I_751___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_751__RX_DCOC_RES_Q_751___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_751__RX_DCOC_RANGE_751___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_751__RX_DCOC_RANGE_751___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_751__RX_DCOC_RES_I_751___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_751__RX_DCOC_RES_I_751___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_751__RX_DCOC_RES_Q_751___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_751__RX_DCOC_RES_Q_751___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_751___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_751___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_752 (0x005F4BC0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_752___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_752___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_752__RX_DCOC_RANGE_752___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_752__RX_DCOC_RES_I_752___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_752__RX_DCOC_RES_Q_752___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_752__RX_DCOC_RANGE_752___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_752__RX_DCOC_RANGE_752___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_752__RX_DCOC_RES_I_752___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_752__RX_DCOC_RES_I_752___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_752__RX_DCOC_RES_Q_752___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_752__RX_DCOC_RES_Q_752___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_752___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_752___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_753 (0x005F4BC4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_753___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_753___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_753__RX_DCOC_RANGE_753___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_753__RX_DCOC_RES_I_753___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_753__RX_DCOC_RES_Q_753___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_753__RX_DCOC_RANGE_753___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_753__RX_DCOC_RANGE_753___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_753__RX_DCOC_RES_I_753___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_753__RX_DCOC_RES_I_753___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_753__RX_DCOC_RES_Q_753___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_753__RX_DCOC_RES_Q_753___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_753___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_753___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_754 (0x005F4BC8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_754___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_754___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_754__RX_DCOC_RANGE_754___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_754__RX_DCOC_RES_I_754___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_754__RX_DCOC_RES_Q_754___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_754__RX_DCOC_RANGE_754___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_754__RX_DCOC_RANGE_754___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_754__RX_DCOC_RES_I_754___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_754__RX_DCOC_RES_I_754___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_754__RX_DCOC_RES_Q_754___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_754__RX_DCOC_RES_Q_754___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_754___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_754___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_755 (0x005F4BCC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_755___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_755___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_755__RX_DCOC_RANGE_755___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_755__RX_DCOC_RES_I_755___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_755__RX_DCOC_RES_Q_755___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_755__RX_DCOC_RANGE_755___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_755__RX_DCOC_RANGE_755___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_755__RX_DCOC_RES_I_755___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_755__RX_DCOC_RES_I_755___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_755__RX_DCOC_RES_Q_755___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_755__RX_DCOC_RES_Q_755___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_755___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_755___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_756 (0x005F4BD0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_756___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_756___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_756__RX_DCOC_RANGE_756___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_756__RX_DCOC_RES_I_756___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_756__RX_DCOC_RES_Q_756___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_756__RX_DCOC_RANGE_756___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_756__RX_DCOC_RANGE_756___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_756__RX_DCOC_RES_I_756___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_756__RX_DCOC_RES_I_756___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_756__RX_DCOC_RES_Q_756___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_756__RX_DCOC_RES_Q_756___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_756___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_756___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_757 (0x005F4BD4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_757___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_757___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_757__RX_DCOC_RANGE_757___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_757__RX_DCOC_RES_I_757___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_757__RX_DCOC_RES_Q_757___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_757__RX_DCOC_RANGE_757___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_757__RX_DCOC_RANGE_757___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_757__RX_DCOC_RES_I_757___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_757__RX_DCOC_RES_I_757___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_757__RX_DCOC_RES_Q_757___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_757__RX_DCOC_RES_Q_757___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_757___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_757___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_758 (0x005F4BD8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_758___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_758___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_758__RX_DCOC_RANGE_758___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_758__RX_DCOC_RES_I_758___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_758__RX_DCOC_RES_Q_758___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_758__RX_DCOC_RANGE_758___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_758__RX_DCOC_RANGE_758___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_758__RX_DCOC_RES_I_758___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_758__RX_DCOC_RES_I_758___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_758__RX_DCOC_RES_Q_758___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_758__RX_DCOC_RES_Q_758___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_758___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_758___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_759 (0x005F4BDC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_759___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_759___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_759__RX_DCOC_RANGE_759___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_759__RX_DCOC_RES_I_759___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_759__RX_DCOC_RES_Q_759___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_759__RX_DCOC_RANGE_759___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_759__RX_DCOC_RANGE_759___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_759__RX_DCOC_RES_I_759___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_759__RX_DCOC_RES_I_759___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_759__RX_DCOC_RES_Q_759___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_759__RX_DCOC_RES_Q_759___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_759___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_759___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_760 (0x005F4BE0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_760___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_760___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_760__RX_DCOC_RANGE_760___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_760__RX_DCOC_RES_I_760___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_760__RX_DCOC_RES_Q_760___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_760__RX_DCOC_RANGE_760___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_760__RX_DCOC_RANGE_760___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_760__RX_DCOC_RES_I_760___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_760__RX_DCOC_RES_I_760___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_760__RX_DCOC_RES_Q_760___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_760__RX_DCOC_RES_Q_760___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_760___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_760___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_761 (0x005F4BE4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_761___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_761___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_761__RX_DCOC_RANGE_761___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_761__RX_DCOC_RES_I_761___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_761__RX_DCOC_RES_Q_761___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_761__RX_DCOC_RANGE_761___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_761__RX_DCOC_RANGE_761___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_761__RX_DCOC_RES_I_761___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_761__RX_DCOC_RES_I_761___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_761__RX_DCOC_RES_Q_761___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_761__RX_DCOC_RES_Q_761___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_761___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_761___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_762 (0x005F4BE8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_762___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_762___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_762__RX_DCOC_RANGE_762___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_762__RX_DCOC_RES_I_762___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_762__RX_DCOC_RES_Q_762___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_762__RX_DCOC_RANGE_762___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_762__RX_DCOC_RANGE_762___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_762__RX_DCOC_RES_I_762___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_762__RX_DCOC_RES_I_762___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_762__RX_DCOC_RES_Q_762___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_762__RX_DCOC_RES_Q_762___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_762___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_762___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_763 (0x005F4BEC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_763___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_763___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_763__RX_DCOC_RANGE_763___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_763__RX_DCOC_RES_I_763___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_763__RX_DCOC_RES_Q_763___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_763__RX_DCOC_RANGE_763___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_763__RX_DCOC_RANGE_763___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_763__RX_DCOC_RES_I_763___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_763__RX_DCOC_RES_I_763___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_763__RX_DCOC_RES_Q_763___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_763__RX_DCOC_RES_Q_763___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_763___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_763___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_764 (0x005F4BF0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_764___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_764___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_764__RX_DCOC_RANGE_764___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_764__RX_DCOC_RES_I_764___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_764__RX_DCOC_RES_Q_764___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_764__RX_DCOC_RANGE_764___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_764__RX_DCOC_RANGE_764___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_764__RX_DCOC_RES_I_764___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_764__RX_DCOC_RES_I_764___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_764__RX_DCOC_RES_Q_764___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_764__RX_DCOC_RES_Q_764___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_764___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_764___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_765 (0x005F4BF4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_765___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_765___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_765__RX_DCOC_RANGE_765___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_765__RX_DCOC_RES_I_765___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_765__RX_DCOC_RES_Q_765___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_765__RX_DCOC_RANGE_765___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_765__RX_DCOC_RANGE_765___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_765__RX_DCOC_RES_I_765___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_765__RX_DCOC_RES_I_765___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_765__RX_DCOC_RES_Q_765___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_765__RX_DCOC_RES_Q_765___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_765___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_765___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_766 (0x005F4BF8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_766___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_766___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_766__RX_DCOC_RANGE_766___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_766__RX_DCOC_RES_I_766___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_766__RX_DCOC_RES_Q_766___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_766__RX_DCOC_RANGE_766___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_766__RX_DCOC_RANGE_766___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_766__RX_DCOC_RES_I_766___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_766__RX_DCOC_RES_I_766___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_766__RX_DCOC_RES_Q_766___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_766__RX_DCOC_RES_Q_766___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_766___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_766___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_767 (0x005F4BFC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_767___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_767___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_767__RX_DCOC_RANGE_767___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_767__RX_DCOC_RES_I_767___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_767__RX_DCOC_RES_Q_767___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_767__RX_DCOC_RANGE_767___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_767__RX_DCOC_RANGE_767___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_767__RX_DCOC_RES_I_767___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_767__RX_DCOC_RES_I_767___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_767__RX_DCOC_RES_Q_767___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_767__RX_DCOC_RES_Q_767___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_767___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_767___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_768 (0x005F4C00) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_768___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_768___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_768__RX_DCOC_RANGE_768___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_768__RX_DCOC_RES_I_768___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_768__RX_DCOC_RES_Q_768___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_768__RX_DCOC_RANGE_768___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_768__RX_DCOC_RANGE_768___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_768__RX_DCOC_RES_I_768___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_768__RX_DCOC_RES_I_768___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_768__RX_DCOC_RES_Q_768___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_768__RX_DCOC_RES_Q_768___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_768___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_768___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_769 (0x005F4C04) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_769___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_769___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_769__RX_DCOC_RANGE_769___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_769__RX_DCOC_RES_I_769___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_769__RX_DCOC_RES_Q_769___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_769__RX_DCOC_RANGE_769___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_769__RX_DCOC_RANGE_769___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_769__RX_DCOC_RES_I_769___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_769__RX_DCOC_RES_I_769___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_769__RX_DCOC_RES_Q_769___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_769__RX_DCOC_RES_Q_769___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_769___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_769___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_770 (0x005F4C08) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_770___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_770___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_770__RX_DCOC_RANGE_770___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_770__RX_DCOC_RES_I_770___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_770__RX_DCOC_RES_Q_770___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_770__RX_DCOC_RANGE_770___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_770__RX_DCOC_RANGE_770___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_770__RX_DCOC_RES_I_770___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_770__RX_DCOC_RES_I_770___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_770__RX_DCOC_RES_Q_770___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_770__RX_DCOC_RES_Q_770___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_770___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_770___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_771 (0x005F4C0C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_771___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_771___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_771__RX_DCOC_RANGE_771___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_771__RX_DCOC_RES_I_771___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_771__RX_DCOC_RES_Q_771___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_771__RX_DCOC_RANGE_771___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_771__RX_DCOC_RANGE_771___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_771__RX_DCOC_RES_I_771___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_771__RX_DCOC_RES_I_771___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_771__RX_DCOC_RES_Q_771___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_771__RX_DCOC_RES_Q_771___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_771___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_771___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_772 (0x005F4C10) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_772___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_772___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_772__RX_DCOC_RANGE_772___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_772__RX_DCOC_RES_I_772___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_772__RX_DCOC_RES_Q_772___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_772__RX_DCOC_RANGE_772___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_772__RX_DCOC_RANGE_772___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_772__RX_DCOC_RES_I_772___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_772__RX_DCOC_RES_I_772___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_772__RX_DCOC_RES_Q_772___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_772__RX_DCOC_RES_Q_772___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_772___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_772___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_773 (0x005F4C14) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_773___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_773___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_773__RX_DCOC_RANGE_773___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_773__RX_DCOC_RES_I_773___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_773__RX_DCOC_RES_Q_773___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_773__RX_DCOC_RANGE_773___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_773__RX_DCOC_RANGE_773___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_773__RX_DCOC_RES_I_773___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_773__RX_DCOC_RES_I_773___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_773__RX_DCOC_RES_Q_773___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_773__RX_DCOC_RES_Q_773___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_773___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_773___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_774 (0x005F4C18) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_774___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_774___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_774__RX_DCOC_RANGE_774___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_774__RX_DCOC_RES_I_774___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_774__RX_DCOC_RES_Q_774___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_774__RX_DCOC_RANGE_774___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_774__RX_DCOC_RANGE_774___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_774__RX_DCOC_RES_I_774___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_774__RX_DCOC_RES_I_774___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_774__RX_DCOC_RES_Q_774___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_774__RX_DCOC_RES_Q_774___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_774___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_774___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_775 (0x005F4C1C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_775___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_775___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_775__RX_DCOC_RANGE_775___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_775__RX_DCOC_RES_I_775___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_775__RX_DCOC_RES_Q_775___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_775__RX_DCOC_RANGE_775___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_775__RX_DCOC_RANGE_775___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_775__RX_DCOC_RES_I_775___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_775__RX_DCOC_RES_I_775___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_775__RX_DCOC_RES_Q_775___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_775__RX_DCOC_RES_Q_775___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_775___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_775___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_776 (0x005F4C20) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_776___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_776___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_776__RX_DCOC_RANGE_776___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_776__RX_DCOC_RES_I_776___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_776__RX_DCOC_RES_Q_776___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_776__RX_DCOC_RANGE_776___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_776__RX_DCOC_RANGE_776___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_776__RX_DCOC_RES_I_776___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_776__RX_DCOC_RES_I_776___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_776__RX_DCOC_RES_Q_776___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_776__RX_DCOC_RES_Q_776___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_776___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_776___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_777 (0x005F4C24) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_777___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_777___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_777__RX_DCOC_RANGE_777___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_777__RX_DCOC_RES_I_777___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_777__RX_DCOC_RES_Q_777___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_777__RX_DCOC_RANGE_777___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_777__RX_DCOC_RANGE_777___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_777__RX_DCOC_RES_I_777___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_777__RX_DCOC_RES_I_777___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_777__RX_DCOC_RES_Q_777___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_777__RX_DCOC_RES_Q_777___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_777___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_777___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_778 (0x005F4C28) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_778___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_778___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_778__RX_DCOC_RANGE_778___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_778__RX_DCOC_RES_I_778___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_778__RX_DCOC_RES_Q_778___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_778__RX_DCOC_RANGE_778___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_778__RX_DCOC_RANGE_778___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_778__RX_DCOC_RES_I_778___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_778__RX_DCOC_RES_I_778___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_778__RX_DCOC_RES_Q_778___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_778__RX_DCOC_RES_Q_778___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_778___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_778___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_779 (0x005F4C2C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_779___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_779___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_779__RX_DCOC_RANGE_779___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_779__RX_DCOC_RES_I_779___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_779__RX_DCOC_RES_Q_779___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_779__RX_DCOC_RANGE_779___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_779__RX_DCOC_RANGE_779___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_779__RX_DCOC_RES_I_779___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_779__RX_DCOC_RES_I_779___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_779__RX_DCOC_RES_Q_779___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_779__RX_DCOC_RES_Q_779___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_779___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_779___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_780 (0x005F4C30) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_780___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_780___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_780__RX_DCOC_RANGE_780___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_780__RX_DCOC_RES_I_780___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_780__RX_DCOC_RES_Q_780___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_780__RX_DCOC_RANGE_780___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_780__RX_DCOC_RANGE_780___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_780__RX_DCOC_RES_I_780___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_780__RX_DCOC_RES_I_780___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_780__RX_DCOC_RES_Q_780___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_780__RX_DCOC_RES_Q_780___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_780___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_780___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_781 (0x005F4C34) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_781___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_781___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_781__RX_DCOC_RANGE_781___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_781__RX_DCOC_RES_I_781___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_781__RX_DCOC_RES_Q_781___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_781__RX_DCOC_RANGE_781___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_781__RX_DCOC_RANGE_781___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_781__RX_DCOC_RES_I_781___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_781__RX_DCOC_RES_I_781___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_781__RX_DCOC_RES_Q_781___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_781__RX_DCOC_RES_Q_781___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_781___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_781___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_782 (0x005F4C38) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_782___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_782___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_782__RX_DCOC_RANGE_782___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_782__RX_DCOC_RES_I_782___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_782__RX_DCOC_RES_Q_782___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_782__RX_DCOC_RANGE_782___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_782__RX_DCOC_RANGE_782___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_782__RX_DCOC_RES_I_782___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_782__RX_DCOC_RES_I_782___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_782__RX_DCOC_RES_Q_782___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_782__RX_DCOC_RES_Q_782___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_782___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_782___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_783 (0x005F4C3C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_783___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_783___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_783__RX_DCOC_RANGE_783___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_783__RX_DCOC_RES_I_783___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_783__RX_DCOC_RES_Q_783___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_783__RX_DCOC_RANGE_783___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_783__RX_DCOC_RANGE_783___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_783__RX_DCOC_RES_I_783___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_783__RX_DCOC_RES_I_783___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_783__RX_DCOC_RES_Q_783___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_783__RX_DCOC_RES_Q_783___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_783___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_783___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_784 (0x005F4C40) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_784___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_784___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_784__RX_DCOC_RANGE_784___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_784__RX_DCOC_RES_I_784___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_784__RX_DCOC_RES_Q_784___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_784__RX_DCOC_RANGE_784___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_784__RX_DCOC_RANGE_784___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_784__RX_DCOC_RES_I_784___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_784__RX_DCOC_RES_I_784___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_784__RX_DCOC_RES_Q_784___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_784__RX_DCOC_RES_Q_784___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_784___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_784___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_785 (0x005F4C44) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_785___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_785___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_785__RX_DCOC_RANGE_785___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_785__RX_DCOC_RES_I_785___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_785__RX_DCOC_RES_Q_785___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_785__RX_DCOC_RANGE_785___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_785__RX_DCOC_RANGE_785___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_785__RX_DCOC_RES_I_785___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_785__RX_DCOC_RES_I_785___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_785__RX_DCOC_RES_Q_785___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_785__RX_DCOC_RES_Q_785___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_785___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_785___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_786 (0x005F4C48) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_786___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_786___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_786__RX_DCOC_RANGE_786___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_786__RX_DCOC_RES_I_786___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_786__RX_DCOC_RES_Q_786___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_786__RX_DCOC_RANGE_786___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_786__RX_DCOC_RANGE_786___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_786__RX_DCOC_RES_I_786___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_786__RX_DCOC_RES_I_786___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_786__RX_DCOC_RES_Q_786___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_786__RX_DCOC_RES_Q_786___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_786___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_786___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_787 (0x005F4C4C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_787___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_787___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_787__RX_DCOC_RANGE_787___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_787__RX_DCOC_RES_I_787___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_787__RX_DCOC_RES_Q_787___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_787__RX_DCOC_RANGE_787___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_787__RX_DCOC_RANGE_787___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_787__RX_DCOC_RES_I_787___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_787__RX_DCOC_RES_I_787___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_787__RX_DCOC_RES_Q_787___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_787__RX_DCOC_RES_Q_787___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_787___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_787___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_788 (0x005F4C50) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_788___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_788___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_788__RX_DCOC_RANGE_788___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_788__RX_DCOC_RES_I_788___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_788__RX_DCOC_RES_Q_788___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_788__RX_DCOC_RANGE_788___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_788__RX_DCOC_RANGE_788___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_788__RX_DCOC_RES_I_788___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_788__RX_DCOC_RES_I_788___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_788__RX_DCOC_RES_Q_788___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_788__RX_DCOC_RES_Q_788___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_788___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_788___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_789 (0x005F4C54) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_789___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_789___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_789__RX_DCOC_RANGE_789___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_789__RX_DCOC_RES_I_789___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_789__RX_DCOC_RES_Q_789___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_789__RX_DCOC_RANGE_789___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_789__RX_DCOC_RANGE_789___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_789__RX_DCOC_RES_I_789___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_789__RX_DCOC_RES_I_789___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_789__RX_DCOC_RES_Q_789___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_789__RX_DCOC_RES_Q_789___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_789___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_789___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_790 (0x005F4C58) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_790___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_790___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_790__RX_DCOC_RANGE_790___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_790__RX_DCOC_RES_I_790___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_790__RX_DCOC_RES_Q_790___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_790__RX_DCOC_RANGE_790___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_790__RX_DCOC_RANGE_790___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_790__RX_DCOC_RES_I_790___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_790__RX_DCOC_RES_I_790___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_790__RX_DCOC_RES_Q_790___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_790__RX_DCOC_RES_Q_790___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_790___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_790___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_791 (0x005F4C5C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_791___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_791___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_791__RX_DCOC_RANGE_791___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_791__RX_DCOC_RES_I_791___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_791__RX_DCOC_RES_Q_791___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_791__RX_DCOC_RANGE_791___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_791__RX_DCOC_RANGE_791___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_791__RX_DCOC_RES_I_791___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_791__RX_DCOC_RES_I_791___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_791__RX_DCOC_RES_Q_791___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_791__RX_DCOC_RES_Q_791___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_791___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_791___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_792 (0x005F4C60) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_792___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_792___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_792__RX_DCOC_RANGE_792___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_792__RX_DCOC_RES_I_792___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_792__RX_DCOC_RES_Q_792___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_792__RX_DCOC_RANGE_792___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_792__RX_DCOC_RANGE_792___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_792__RX_DCOC_RES_I_792___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_792__RX_DCOC_RES_I_792___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_792__RX_DCOC_RES_Q_792___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_792__RX_DCOC_RES_Q_792___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_792___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_792___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_793 (0x005F4C64) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_793___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_793___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_793__RX_DCOC_RANGE_793___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_793__RX_DCOC_RES_I_793___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_793__RX_DCOC_RES_Q_793___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_793__RX_DCOC_RANGE_793___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_793__RX_DCOC_RANGE_793___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_793__RX_DCOC_RES_I_793___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_793__RX_DCOC_RES_I_793___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_793__RX_DCOC_RES_Q_793___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_793__RX_DCOC_RES_Q_793___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_793___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_793___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_794 (0x005F4C68) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_794___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_794___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_794__RX_DCOC_RANGE_794___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_794__RX_DCOC_RES_I_794___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_794__RX_DCOC_RES_Q_794___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_794__RX_DCOC_RANGE_794___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_794__RX_DCOC_RANGE_794___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_794__RX_DCOC_RES_I_794___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_794__RX_DCOC_RES_I_794___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_794__RX_DCOC_RES_Q_794___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_794__RX_DCOC_RES_Q_794___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_794___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_794___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_795 (0x005F4C6C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_795___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_795___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_795__RX_DCOC_RANGE_795___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_795__RX_DCOC_RES_I_795___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_795__RX_DCOC_RES_Q_795___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_795__RX_DCOC_RANGE_795___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_795__RX_DCOC_RANGE_795___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_795__RX_DCOC_RES_I_795___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_795__RX_DCOC_RES_I_795___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_795__RX_DCOC_RES_Q_795___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_795__RX_DCOC_RES_Q_795___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_795___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_795___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_796 (0x005F4C70) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_796___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_796___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_796__RX_DCOC_RANGE_796___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_796__RX_DCOC_RES_I_796___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_796__RX_DCOC_RES_Q_796___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_796__RX_DCOC_RANGE_796___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_796__RX_DCOC_RANGE_796___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_796__RX_DCOC_RES_I_796___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_796__RX_DCOC_RES_I_796___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_796__RX_DCOC_RES_Q_796___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_796__RX_DCOC_RES_Q_796___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_796___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_796___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_797 (0x005F4C74) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_797___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_797___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_797__RX_DCOC_RANGE_797___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_797__RX_DCOC_RES_I_797___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_797__RX_DCOC_RES_Q_797___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_797__RX_DCOC_RANGE_797___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_797__RX_DCOC_RANGE_797___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_797__RX_DCOC_RES_I_797___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_797__RX_DCOC_RES_I_797___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_797__RX_DCOC_RES_Q_797___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_797__RX_DCOC_RES_Q_797___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_797___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_797___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_798 (0x005F4C78) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_798___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_798___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_798__RX_DCOC_RANGE_798___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_798__RX_DCOC_RES_I_798___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_798__RX_DCOC_RES_Q_798___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_798__RX_DCOC_RANGE_798___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_798__RX_DCOC_RANGE_798___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_798__RX_DCOC_RES_I_798___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_798__RX_DCOC_RES_I_798___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_798__RX_DCOC_RES_Q_798___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_798__RX_DCOC_RES_Q_798___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_798___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_798___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_799 (0x005F4C7C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_799___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_799___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_799__RX_DCOC_RANGE_799___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_799__RX_DCOC_RES_I_799___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_799__RX_DCOC_RES_Q_799___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_799__RX_DCOC_RANGE_799___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_799__RX_DCOC_RANGE_799___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_799__RX_DCOC_RES_I_799___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_799__RX_DCOC_RES_I_799___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_799__RX_DCOC_RES_Q_799___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_799__RX_DCOC_RES_Q_799___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_799___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_799___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_800 (0x005F4C80) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_800___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_800___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_800__RX_DCOC_RANGE_800___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_800__RX_DCOC_RES_I_800___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_800__RX_DCOC_RES_Q_800___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_800__RX_DCOC_RANGE_800___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_800__RX_DCOC_RANGE_800___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_800__RX_DCOC_RES_I_800___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_800__RX_DCOC_RES_I_800___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_800__RX_DCOC_RES_Q_800___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_800__RX_DCOC_RES_Q_800___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_800___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_800___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_801 (0x005F4C84) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_801___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_801___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_801__RX_DCOC_RANGE_801___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_801__RX_DCOC_RES_I_801___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_801__RX_DCOC_RES_Q_801___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_801__RX_DCOC_RANGE_801___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_801__RX_DCOC_RANGE_801___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_801__RX_DCOC_RES_I_801___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_801__RX_DCOC_RES_I_801___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_801__RX_DCOC_RES_Q_801___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_801__RX_DCOC_RES_Q_801___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_801___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_801___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_802 (0x005F4C88) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_802___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_802___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_802__RX_DCOC_RANGE_802___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_802__RX_DCOC_RES_I_802___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_802__RX_DCOC_RES_Q_802___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_802__RX_DCOC_RANGE_802___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_802__RX_DCOC_RANGE_802___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_802__RX_DCOC_RES_I_802___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_802__RX_DCOC_RES_I_802___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_802__RX_DCOC_RES_Q_802___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_802__RX_DCOC_RES_Q_802___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_802___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_802___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_803 (0x005F4C8C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_803___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_803___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_803__RX_DCOC_RANGE_803___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_803__RX_DCOC_RES_I_803___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_803__RX_DCOC_RES_Q_803___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_803__RX_DCOC_RANGE_803___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_803__RX_DCOC_RANGE_803___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_803__RX_DCOC_RES_I_803___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_803__RX_DCOC_RES_I_803___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_803__RX_DCOC_RES_Q_803___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_803__RX_DCOC_RES_Q_803___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_803___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_803___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_804 (0x005F4C90) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_804___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_804___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_804__RX_DCOC_RANGE_804___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_804__RX_DCOC_RES_I_804___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_804__RX_DCOC_RES_Q_804___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_804__RX_DCOC_RANGE_804___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_804__RX_DCOC_RANGE_804___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_804__RX_DCOC_RES_I_804___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_804__RX_DCOC_RES_I_804___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_804__RX_DCOC_RES_Q_804___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_804__RX_DCOC_RES_Q_804___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_804___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_804___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_805 (0x005F4C94) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_805___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_805___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_805__RX_DCOC_RANGE_805___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_805__RX_DCOC_RES_I_805___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_805__RX_DCOC_RES_Q_805___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_805__RX_DCOC_RANGE_805___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_805__RX_DCOC_RANGE_805___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_805__RX_DCOC_RES_I_805___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_805__RX_DCOC_RES_I_805___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_805__RX_DCOC_RES_Q_805___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_805__RX_DCOC_RES_Q_805___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_805___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_805___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_806 (0x005F4C98) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_806___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_806___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_806__RX_DCOC_RANGE_806___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_806__RX_DCOC_RES_I_806___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_806__RX_DCOC_RES_Q_806___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_806__RX_DCOC_RANGE_806___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_806__RX_DCOC_RANGE_806___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_806__RX_DCOC_RES_I_806___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_806__RX_DCOC_RES_I_806___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_806__RX_DCOC_RES_Q_806___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_806__RX_DCOC_RES_Q_806___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_806___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_806___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_807 (0x005F4C9C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_807___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_807___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_807__RX_DCOC_RANGE_807___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_807__RX_DCOC_RES_I_807___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_807__RX_DCOC_RES_Q_807___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_807__RX_DCOC_RANGE_807___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_807__RX_DCOC_RANGE_807___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_807__RX_DCOC_RES_I_807___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_807__RX_DCOC_RES_I_807___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_807__RX_DCOC_RES_Q_807___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_807__RX_DCOC_RES_Q_807___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_807___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_807___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_808 (0x005F4CA0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_808___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_808___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_808__RX_DCOC_RANGE_808___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_808__RX_DCOC_RES_I_808___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_808__RX_DCOC_RES_Q_808___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_808__RX_DCOC_RANGE_808___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_808__RX_DCOC_RANGE_808___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_808__RX_DCOC_RES_I_808___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_808__RX_DCOC_RES_I_808___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_808__RX_DCOC_RES_Q_808___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_808__RX_DCOC_RES_Q_808___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_808___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_808___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_809 (0x005F4CA4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_809___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_809___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_809__RX_DCOC_RANGE_809___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_809__RX_DCOC_RES_I_809___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_809__RX_DCOC_RES_Q_809___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_809__RX_DCOC_RANGE_809___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_809__RX_DCOC_RANGE_809___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_809__RX_DCOC_RES_I_809___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_809__RX_DCOC_RES_I_809___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_809__RX_DCOC_RES_Q_809___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_809__RX_DCOC_RES_Q_809___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_809___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_809___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_810 (0x005F4CA8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_810___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_810___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_810__RX_DCOC_RANGE_810___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_810__RX_DCOC_RES_I_810___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_810__RX_DCOC_RES_Q_810___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_810__RX_DCOC_RANGE_810___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_810__RX_DCOC_RANGE_810___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_810__RX_DCOC_RES_I_810___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_810__RX_DCOC_RES_I_810___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_810__RX_DCOC_RES_Q_810___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_810__RX_DCOC_RES_Q_810___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_810___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_810___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_811 (0x005F4CAC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_811___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_811___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_811__RX_DCOC_RANGE_811___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_811__RX_DCOC_RES_I_811___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_811__RX_DCOC_RES_Q_811___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_811__RX_DCOC_RANGE_811___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_811__RX_DCOC_RANGE_811___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_811__RX_DCOC_RES_I_811___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_811__RX_DCOC_RES_I_811___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_811__RX_DCOC_RES_Q_811___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_811__RX_DCOC_RES_Q_811___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_811___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_811___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_812 (0x005F4CB0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_812___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_812___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_812__RX_DCOC_RANGE_812___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_812__RX_DCOC_RES_I_812___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_812__RX_DCOC_RES_Q_812___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_812__RX_DCOC_RANGE_812___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_812__RX_DCOC_RANGE_812___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_812__RX_DCOC_RES_I_812___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_812__RX_DCOC_RES_I_812___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_812__RX_DCOC_RES_Q_812___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_812__RX_DCOC_RES_Q_812___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_812___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_812___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_813 (0x005F4CB4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_813___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_813___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_813__RX_DCOC_RANGE_813___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_813__RX_DCOC_RES_I_813___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_813__RX_DCOC_RES_Q_813___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_813__RX_DCOC_RANGE_813___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_813__RX_DCOC_RANGE_813___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_813__RX_DCOC_RES_I_813___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_813__RX_DCOC_RES_I_813___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_813__RX_DCOC_RES_Q_813___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_813__RX_DCOC_RES_Q_813___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_813___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_813___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_814 (0x005F4CB8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_814___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_814___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_814__RX_DCOC_RANGE_814___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_814__RX_DCOC_RES_I_814___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_814__RX_DCOC_RES_Q_814___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_814__RX_DCOC_RANGE_814___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_814__RX_DCOC_RANGE_814___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_814__RX_DCOC_RES_I_814___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_814__RX_DCOC_RES_I_814___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_814__RX_DCOC_RES_Q_814___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_814__RX_DCOC_RES_Q_814___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_814___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_814___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_815 (0x005F4CBC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_815___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_815___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_815__RX_DCOC_RANGE_815___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_815__RX_DCOC_RES_I_815___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_815__RX_DCOC_RES_Q_815___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_815__RX_DCOC_RANGE_815___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_815__RX_DCOC_RANGE_815___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_815__RX_DCOC_RES_I_815___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_815__RX_DCOC_RES_I_815___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_815__RX_DCOC_RES_Q_815___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_815__RX_DCOC_RES_Q_815___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_815___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_815___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_816 (0x005F4CC0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_816___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_816___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_816__RX_DCOC_RANGE_816___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_816__RX_DCOC_RES_I_816___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_816__RX_DCOC_RES_Q_816___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_816__RX_DCOC_RANGE_816___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_816__RX_DCOC_RANGE_816___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_816__RX_DCOC_RES_I_816___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_816__RX_DCOC_RES_I_816___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_816__RX_DCOC_RES_Q_816___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_816__RX_DCOC_RES_Q_816___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_816___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_816___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_817 (0x005F4CC4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_817___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_817___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_817__RX_DCOC_RANGE_817___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_817__RX_DCOC_RES_I_817___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_817__RX_DCOC_RES_Q_817___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_817__RX_DCOC_RANGE_817___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_817__RX_DCOC_RANGE_817___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_817__RX_DCOC_RES_I_817___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_817__RX_DCOC_RES_I_817___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_817__RX_DCOC_RES_Q_817___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_817__RX_DCOC_RES_Q_817___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_817___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_817___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_818 (0x005F4CC8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_818___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_818___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_818__RX_DCOC_RANGE_818___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_818__RX_DCOC_RES_I_818___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_818__RX_DCOC_RES_Q_818___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_818__RX_DCOC_RANGE_818___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_818__RX_DCOC_RANGE_818___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_818__RX_DCOC_RES_I_818___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_818__RX_DCOC_RES_I_818___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_818__RX_DCOC_RES_Q_818___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_818__RX_DCOC_RES_Q_818___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_818___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_818___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_819 (0x005F4CCC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_819___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_819___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_819__RX_DCOC_RANGE_819___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_819__RX_DCOC_RES_I_819___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_819__RX_DCOC_RES_Q_819___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_819__RX_DCOC_RANGE_819___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_819__RX_DCOC_RANGE_819___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_819__RX_DCOC_RES_I_819___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_819__RX_DCOC_RES_I_819___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_819__RX_DCOC_RES_Q_819___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_819__RX_DCOC_RES_Q_819___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_819___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_819___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_820 (0x005F4CD0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_820___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_820___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_820__RX_DCOC_RANGE_820___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_820__RX_DCOC_RES_I_820___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_820__RX_DCOC_RES_Q_820___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_820__RX_DCOC_RANGE_820___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_820__RX_DCOC_RANGE_820___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_820__RX_DCOC_RES_I_820___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_820__RX_DCOC_RES_I_820___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_820__RX_DCOC_RES_Q_820___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_820__RX_DCOC_RES_Q_820___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_820___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_820___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_821 (0x005F4CD4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_821___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_821___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_821__RX_DCOC_RANGE_821___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_821__RX_DCOC_RES_I_821___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_821__RX_DCOC_RES_Q_821___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_821__RX_DCOC_RANGE_821___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_821__RX_DCOC_RANGE_821___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_821__RX_DCOC_RES_I_821___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_821__RX_DCOC_RES_I_821___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_821__RX_DCOC_RES_Q_821___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_821__RX_DCOC_RES_Q_821___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_821___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_821___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_822 (0x005F4CD8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_822___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_822___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_822__RX_DCOC_RANGE_822___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_822__RX_DCOC_RES_I_822___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_822__RX_DCOC_RES_Q_822___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_822__RX_DCOC_RANGE_822___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_822__RX_DCOC_RANGE_822___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_822__RX_DCOC_RES_I_822___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_822__RX_DCOC_RES_I_822___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_822__RX_DCOC_RES_Q_822___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_822__RX_DCOC_RES_Q_822___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_822___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_822___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_823 (0x005F4CDC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_823___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_823___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_823__RX_DCOC_RANGE_823___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_823__RX_DCOC_RES_I_823___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_823__RX_DCOC_RES_Q_823___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_823__RX_DCOC_RANGE_823___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_823__RX_DCOC_RANGE_823___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_823__RX_DCOC_RES_I_823___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_823__RX_DCOC_RES_I_823___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_823__RX_DCOC_RES_Q_823___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_823__RX_DCOC_RES_Q_823___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_823___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_823___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_824 (0x005F4CE0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_824___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_824___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_824__RX_DCOC_RANGE_824___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_824__RX_DCOC_RES_I_824___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_824__RX_DCOC_RES_Q_824___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_824__RX_DCOC_RANGE_824___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_824__RX_DCOC_RANGE_824___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_824__RX_DCOC_RES_I_824___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_824__RX_DCOC_RES_I_824___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_824__RX_DCOC_RES_Q_824___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_824__RX_DCOC_RES_Q_824___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_824___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_824___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_825 (0x005F4CE4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_825___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_825___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_825__RX_DCOC_RANGE_825___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_825__RX_DCOC_RES_I_825___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_825__RX_DCOC_RES_Q_825___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_825__RX_DCOC_RANGE_825___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_825__RX_DCOC_RANGE_825___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_825__RX_DCOC_RES_I_825___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_825__RX_DCOC_RES_I_825___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_825__RX_DCOC_RES_Q_825___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_825__RX_DCOC_RES_Q_825___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_825___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_825___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_826 (0x005F4CE8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_826___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_826___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_826__RX_DCOC_RANGE_826___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_826__RX_DCOC_RES_I_826___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_826__RX_DCOC_RES_Q_826___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_826__RX_DCOC_RANGE_826___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_826__RX_DCOC_RANGE_826___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_826__RX_DCOC_RES_I_826___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_826__RX_DCOC_RES_I_826___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_826__RX_DCOC_RES_Q_826___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_826__RX_DCOC_RES_Q_826___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_826___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_826___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_827 (0x005F4CEC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_827___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_827___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_827__RX_DCOC_RANGE_827___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_827__RX_DCOC_RES_I_827___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_827__RX_DCOC_RES_Q_827___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_827__RX_DCOC_RANGE_827___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_827__RX_DCOC_RANGE_827___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_827__RX_DCOC_RES_I_827___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_827__RX_DCOC_RES_I_827___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_827__RX_DCOC_RES_Q_827___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_827__RX_DCOC_RES_Q_827___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_827___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_827___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_828 (0x005F4CF0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_828___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_828___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_828__RX_DCOC_RANGE_828___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_828__RX_DCOC_RES_I_828___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_828__RX_DCOC_RES_Q_828___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_828__RX_DCOC_RANGE_828___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_828__RX_DCOC_RANGE_828___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_828__RX_DCOC_RES_I_828___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_828__RX_DCOC_RES_I_828___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_828__RX_DCOC_RES_Q_828___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_828__RX_DCOC_RES_Q_828___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_828___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_828___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_829 (0x005F4CF4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_829___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_829___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_829__RX_DCOC_RANGE_829___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_829__RX_DCOC_RES_I_829___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_829__RX_DCOC_RES_Q_829___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_829__RX_DCOC_RANGE_829___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_829__RX_DCOC_RANGE_829___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_829__RX_DCOC_RES_I_829___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_829__RX_DCOC_RES_I_829___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_829__RX_DCOC_RES_Q_829___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_829__RX_DCOC_RES_Q_829___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_829___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_829___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_830 (0x005F4CF8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_830___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_830___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_830__RX_DCOC_RANGE_830___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_830__RX_DCOC_RES_I_830___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_830__RX_DCOC_RES_Q_830___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_830__RX_DCOC_RANGE_830___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_830__RX_DCOC_RANGE_830___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_830__RX_DCOC_RES_I_830___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_830__RX_DCOC_RES_I_830___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_830__RX_DCOC_RES_Q_830___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_830__RX_DCOC_RES_Q_830___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_830___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_830___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_831 (0x005F4CFC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_831___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_831___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_831__RX_DCOC_RANGE_831___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_831__RX_DCOC_RES_I_831___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_831__RX_DCOC_RES_Q_831___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_831__RX_DCOC_RANGE_831___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_831__RX_DCOC_RANGE_831___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_831__RX_DCOC_RES_I_831___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_831__RX_DCOC_RES_I_831___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_831__RX_DCOC_RES_Q_831___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_831__RX_DCOC_RES_Q_831___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_831___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_831___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_832 (0x005F4D00) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_832___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_832___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_832__RX_DCOC_RANGE_832___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_832__RX_DCOC_RES_I_832___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_832__RX_DCOC_RES_Q_832___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_832__RX_DCOC_RANGE_832___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_832__RX_DCOC_RANGE_832___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_832__RX_DCOC_RES_I_832___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_832__RX_DCOC_RES_I_832___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_832__RX_DCOC_RES_Q_832___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_832__RX_DCOC_RES_Q_832___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_832___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_832___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_833 (0x005F4D04) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_833___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_833___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_833__RX_DCOC_RANGE_833___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_833__RX_DCOC_RES_I_833___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_833__RX_DCOC_RES_Q_833___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_833__RX_DCOC_RANGE_833___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_833__RX_DCOC_RANGE_833___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_833__RX_DCOC_RES_I_833___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_833__RX_DCOC_RES_I_833___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_833__RX_DCOC_RES_Q_833___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_833__RX_DCOC_RES_Q_833___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_833___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_833___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_834 (0x005F4D08) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_834___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_834___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_834__RX_DCOC_RANGE_834___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_834__RX_DCOC_RES_I_834___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_834__RX_DCOC_RES_Q_834___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_834__RX_DCOC_RANGE_834___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_834__RX_DCOC_RANGE_834___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_834__RX_DCOC_RES_I_834___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_834__RX_DCOC_RES_I_834___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_834__RX_DCOC_RES_Q_834___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_834__RX_DCOC_RES_Q_834___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_834___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_834___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_835 (0x005F4D0C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_835___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_835___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_835__RX_DCOC_RANGE_835___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_835__RX_DCOC_RES_I_835___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_835__RX_DCOC_RES_Q_835___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_835__RX_DCOC_RANGE_835___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_835__RX_DCOC_RANGE_835___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_835__RX_DCOC_RES_I_835___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_835__RX_DCOC_RES_I_835___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_835__RX_DCOC_RES_Q_835___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_835__RX_DCOC_RES_Q_835___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_835___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_835___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_836 (0x005F4D10) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_836___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_836___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_836__RX_DCOC_RANGE_836___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_836__RX_DCOC_RES_I_836___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_836__RX_DCOC_RES_Q_836___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_836__RX_DCOC_RANGE_836___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_836__RX_DCOC_RANGE_836___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_836__RX_DCOC_RES_I_836___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_836__RX_DCOC_RES_I_836___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_836__RX_DCOC_RES_Q_836___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_836__RX_DCOC_RES_Q_836___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_836___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_836___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_837 (0x005F4D14) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_837___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_837___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_837__RX_DCOC_RANGE_837___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_837__RX_DCOC_RES_I_837___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_837__RX_DCOC_RES_Q_837___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_837__RX_DCOC_RANGE_837___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_837__RX_DCOC_RANGE_837___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_837__RX_DCOC_RES_I_837___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_837__RX_DCOC_RES_I_837___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_837__RX_DCOC_RES_Q_837___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_837__RX_DCOC_RES_Q_837___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_837___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_837___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_838 (0x005F4D18) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_838___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_838___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_838__RX_DCOC_RANGE_838___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_838__RX_DCOC_RES_I_838___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_838__RX_DCOC_RES_Q_838___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_838__RX_DCOC_RANGE_838___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_838__RX_DCOC_RANGE_838___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_838__RX_DCOC_RES_I_838___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_838__RX_DCOC_RES_I_838___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_838__RX_DCOC_RES_Q_838___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_838__RX_DCOC_RES_Q_838___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_838___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_838___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_839 (0x005F4D1C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_839___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_839___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_839__RX_DCOC_RANGE_839___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_839__RX_DCOC_RES_I_839___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_839__RX_DCOC_RES_Q_839___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_839__RX_DCOC_RANGE_839___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_839__RX_DCOC_RANGE_839___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_839__RX_DCOC_RES_I_839___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_839__RX_DCOC_RES_I_839___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_839__RX_DCOC_RES_Q_839___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_839__RX_DCOC_RES_Q_839___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_839___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_839___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_840 (0x005F4D20) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_840___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_840___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_840__RX_DCOC_RANGE_840___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_840__RX_DCOC_RES_I_840___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_840__RX_DCOC_RES_Q_840___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_840__RX_DCOC_RANGE_840___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_840__RX_DCOC_RANGE_840___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_840__RX_DCOC_RES_I_840___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_840__RX_DCOC_RES_I_840___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_840__RX_DCOC_RES_Q_840___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_840__RX_DCOC_RES_Q_840___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_840___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_840___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_841 (0x005F4D24) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_841___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_841___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_841__RX_DCOC_RANGE_841___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_841__RX_DCOC_RES_I_841___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_841__RX_DCOC_RES_Q_841___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_841__RX_DCOC_RANGE_841___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_841__RX_DCOC_RANGE_841___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_841__RX_DCOC_RES_I_841___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_841__RX_DCOC_RES_I_841___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_841__RX_DCOC_RES_Q_841___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_841__RX_DCOC_RES_Q_841___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_841___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_841___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_842 (0x005F4D28) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_842___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_842___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_842__RX_DCOC_RANGE_842___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_842__RX_DCOC_RES_I_842___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_842__RX_DCOC_RES_Q_842___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_842__RX_DCOC_RANGE_842___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_842__RX_DCOC_RANGE_842___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_842__RX_DCOC_RES_I_842___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_842__RX_DCOC_RES_I_842___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_842__RX_DCOC_RES_Q_842___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_842__RX_DCOC_RES_Q_842___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_842___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_842___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_843 (0x005F4D2C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_843___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_843___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_843__RX_DCOC_RANGE_843___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_843__RX_DCOC_RES_I_843___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_843__RX_DCOC_RES_Q_843___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_843__RX_DCOC_RANGE_843___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_843__RX_DCOC_RANGE_843___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_843__RX_DCOC_RES_I_843___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_843__RX_DCOC_RES_I_843___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_843__RX_DCOC_RES_Q_843___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_843__RX_DCOC_RES_Q_843___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_843___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_843___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_844 (0x005F4D30) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_844___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_844___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_844__RX_DCOC_RANGE_844___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_844__RX_DCOC_RES_I_844___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_844__RX_DCOC_RES_Q_844___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_844__RX_DCOC_RANGE_844___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_844__RX_DCOC_RANGE_844___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_844__RX_DCOC_RES_I_844___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_844__RX_DCOC_RES_I_844___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_844__RX_DCOC_RES_Q_844___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_844__RX_DCOC_RES_Q_844___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_844___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_844___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_845 (0x005F4D34) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_845___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_845___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_845__RX_DCOC_RANGE_845___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_845__RX_DCOC_RES_I_845___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_845__RX_DCOC_RES_Q_845___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_845__RX_DCOC_RANGE_845___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_845__RX_DCOC_RANGE_845___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_845__RX_DCOC_RES_I_845___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_845__RX_DCOC_RES_I_845___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_845__RX_DCOC_RES_Q_845___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_845__RX_DCOC_RES_Q_845___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_845___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_845___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_846 (0x005F4D38) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_846___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_846___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_846__RX_DCOC_RANGE_846___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_846__RX_DCOC_RES_I_846___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_846__RX_DCOC_RES_Q_846___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_846__RX_DCOC_RANGE_846___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_846__RX_DCOC_RANGE_846___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_846__RX_DCOC_RES_I_846___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_846__RX_DCOC_RES_I_846___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_846__RX_DCOC_RES_Q_846___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_846__RX_DCOC_RES_Q_846___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_846___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_846___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_847 (0x005F4D3C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_847___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_847___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_847__RX_DCOC_RANGE_847___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_847__RX_DCOC_RES_I_847___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_847__RX_DCOC_RES_Q_847___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_847__RX_DCOC_RANGE_847___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_847__RX_DCOC_RANGE_847___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_847__RX_DCOC_RES_I_847___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_847__RX_DCOC_RES_I_847___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_847__RX_DCOC_RES_Q_847___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_847__RX_DCOC_RES_Q_847___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_847___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_847___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_848 (0x005F4D40) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_848___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_848___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_848__RX_DCOC_RANGE_848___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_848__RX_DCOC_RES_I_848___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_848__RX_DCOC_RES_Q_848___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_848__RX_DCOC_RANGE_848___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_848__RX_DCOC_RANGE_848___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_848__RX_DCOC_RES_I_848___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_848__RX_DCOC_RES_I_848___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_848__RX_DCOC_RES_Q_848___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_848__RX_DCOC_RES_Q_848___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_848___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_848___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_849 (0x005F4D44) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_849___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_849___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_849__RX_DCOC_RANGE_849___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_849__RX_DCOC_RES_I_849___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_849__RX_DCOC_RES_Q_849___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_849__RX_DCOC_RANGE_849___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_849__RX_DCOC_RANGE_849___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_849__RX_DCOC_RES_I_849___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_849__RX_DCOC_RES_I_849___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_849__RX_DCOC_RES_Q_849___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_849__RX_DCOC_RES_Q_849___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_849___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_849___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_850 (0x005F4D48) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_850___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_850___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_850__RX_DCOC_RANGE_850___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_850__RX_DCOC_RES_I_850___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_850__RX_DCOC_RES_Q_850___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_850__RX_DCOC_RANGE_850___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_850__RX_DCOC_RANGE_850___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_850__RX_DCOC_RES_I_850___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_850__RX_DCOC_RES_I_850___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_850__RX_DCOC_RES_Q_850___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_850__RX_DCOC_RES_Q_850___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_850___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_850___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_851 (0x005F4D4C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_851___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_851___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_851__RX_DCOC_RANGE_851___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_851__RX_DCOC_RES_I_851___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_851__RX_DCOC_RES_Q_851___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_851__RX_DCOC_RANGE_851___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_851__RX_DCOC_RANGE_851___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_851__RX_DCOC_RES_I_851___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_851__RX_DCOC_RES_I_851___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_851__RX_DCOC_RES_Q_851___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_851__RX_DCOC_RES_Q_851___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_851___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_851___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_852 (0x005F4D50) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_852___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_852___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_852__RX_DCOC_RANGE_852___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_852__RX_DCOC_RES_I_852___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_852__RX_DCOC_RES_Q_852___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_852__RX_DCOC_RANGE_852___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_852__RX_DCOC_RANGE_852___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_852__RX_DCOC_RES_I_852___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_852__RX_DCOC_RES_I_852___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_852__RX_DCOC_RES_Q_852___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_852__RX_DCOC_RES_Q_852___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_852___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_852___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_853 (0x005F4D54) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_853___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_853___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_853__RX_DCOC_RANGE_853___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_853__RX_DCOC_RES_I_853___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_853__RX_DCOC_RES_Q_853___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_853__RX_DCOC_RANGE_853___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_853__RX_DCOC_RANGE_853___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_853__RX_DCOC_RES_I_853___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_853__RX_DCOC_RES_I_853___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_853__RX_DCOC_RES_Q_853___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_853__RX_DCOC_RES_Q_853___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_853___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_853___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_854 (0x005F4D58) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_854___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_854___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_854__RX_DCOC_RANGE_854___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_854__RX_DCOC_RES_I_854___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_854__RX_DCOC_RES_Q_854___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_854__RX_DCOC_RANGE_854___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_854__RX_DCOC_RANGE_854___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_854__RX_DCOC_RES_I_854___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_854__RX_DCOC_RES_I_854___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_854__RX_DCOC_RES_Q_854___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_854__RX_DCOC_RES_Q_854___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_854___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_854___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_855 (0x005F4D5C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_855___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_855___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_855__RX_DCOC_RANGE_855___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_855__RX_DCOC_RES_I_855___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_855__RX_DCOC_RES_Q_855___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_855__RX_DCOC_RANGE_855___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_855__RX_DCOC_RANGE_855___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_855__RX_DCOC_RES_I_855___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_855__RX_DCOC_RES_I_855___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_855__RX_DCOC_RES_Q_855___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_855__RX_DCOC_RES_Q_855___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_855___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_855___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_856 (0x005F4D60) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_856___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_856___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_856__RX_DCOC_RANGE_856___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_856__RX_DCOC_RES_I_856___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_856__RX_DCOC_RES_Q_856___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_856__RX_DCOC_RANGE_856___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_856__RX_DCOC_RANGE_856___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_856__RX_DCOC_RES_I_856___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_856__RX_DCOC_RES_I_856___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_856__RX_DCOC_RES_Q_856___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_856__RX_DCOC_RES_Q_856___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_856___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_856___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_857 (0x005F4D64) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_857___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_857___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_857__RX_DCOC_RANGE_857___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_857__RX_DCOC_RES_I_857___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_857__RX_DCOC_RES_Q_857___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_857__RX_DCOC_RANGE_857___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_857__RX_DCOC_RANGE_857___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_857__RX_DCOC_RES_I_857___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_857__RX_DCOC_RES_I_857___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_857__RX_DCOC_RES_Q_857___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_857__RX_DCOC_RES_Q_857___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_857___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_857___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_858 (0x005F4D68) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_858___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_858___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_858__RX_DCOC_RANGE_858___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_858__RX_DCOC_RES_I_858___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_858__RX_DCOC_RES_Q_858___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_858__RX_DCOC_RANGE_858___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_858__RX_DCOC_RANGE_858___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_858__RX_DCOC_RES_I_858___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_858__RX_DCOC_RES_I_858___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_858__RX_DCOC_RES_Q_858___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_858__RX_DCOC_RES_Q_858___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_858___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_858___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_859 (0x005F4D6C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_859___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_859___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_859__RX_DCOC_RANGE_859___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_859__RX_DCOC_RES_I_859___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_859__RX_DCOC_RES_Q_859___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_859__RX_DCOC_RANGE_859___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_859__RX_DCOC_RANGE_859___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_859__RX_DCOC_RES_I_859___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_859__RX_DCOC_RES_I_859___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_859__RX_DCOC_RES_Q_859___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_859__RX_DCOC_RES_Q_859___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_859___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_859___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_860 (0x005F4D70) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_860___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_860___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_860__RX_DCOC_RANGE_860___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_860__RX_DCOC_RES_I_860___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_860__RX_DCOC_RES_Q_860___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_860__RX_DCOC_RANGE_860___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_860__RX_DCOC_RANGE_860___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_860__RX_DCOC_RES_I_860___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_860__RX_DCOC_RES_I_860___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_860__RX_DCOC_RES_Q_860___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_860__RX_DCOC_RES_Q_860___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_860___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_860___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_861 (0x005F4D74) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_861___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_861___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_861__RX_DCOC_RANGE_861___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_861__RX_DCOC_RES_I_861___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_861__RX_DCOC_RES_Q_861___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_861__RX_DCOC_RANGE_861___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_861__RX_DCOC_RANGE_861___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_861__RX_DCOC_RES_I_861___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_861__RX_DCOC_RES_I_861___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_861__RX_DCOC_RES_Q_861___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_861__RX_DCOC_RES_Q_861___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_861___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_861___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_862 (0x005F4D78) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_862___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_862___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_862__RX_DCOC_RANGE_862___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_862__RX_DCOC_RES_I_862___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_862__RX_DCOC_RES_Q_862___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_862__RX_DCOC_RANGE_862___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_862__RX_DCOC_RANGE_862___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_862__RX_DCOC_RES_I_862___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_862__RX_DCOC_RES_I_862___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_862__RX_DCOC_RES_Q_862___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_862__RX_DCOC_RES_Q_862___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_862___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_862___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_863 (0x005F4D7C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_863___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_863___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_863__RX_DCOC_RANGE_863___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_863__RX_DCOC_RES_I_863___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_863__RX_DCOC_RES_Q_863___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_863__RX_DCOC_RANGE_863___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_863__RX_DCOC_RANGE_863___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_863__RX_DCOC_RES_I_863___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_863__RX_DCOC_RES_I_863___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_863__RX_DCOC_RES_Q_863___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_863__RX_DCOC_RES_Q_863___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_863___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_863___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_864 (0x005F4D80) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_864___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_864___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_864__RX_DCOC_RANGE_864___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_864__RX_DCOC_RES_I_864___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_864__RX_DCOC_RES_Q_864___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_864__RX_DCOC_RANGE_864___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_864__RX_DCOC_RANGE_864___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_864__RX_DCOC_RES_I_864___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_864__RX_DCOC_RES_I_864___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_864__RX_DCOC_RES_Q_864___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_864__RX_DCOC_RES_Q_864___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_864___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_864___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_865 (0x005F4D84) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_865___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_865___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_865__RX_DCOC_RANGE_865___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_865__RX_DCOC_RES_I_865___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_865__RX_DCOC_RES_Q_865___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_865__RX_DCOC_RANGE_865___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_865__RX_DCOC_RANGE_865___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_865__RX_DCOC_RES_I_865___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_865__RX_DCOC_RES_I_865___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_865__RX_DCOC_RES_Q_865___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_865__RX_DCOC_RES_Q_865___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_865___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_865___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_866 (0x005F4D88) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_866___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_866___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_866__RX_DCOC_RANGE_866___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_866__RX_DCOC_RES_I_866___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_866__RX_DCOC_RES_Q_866___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_866__RX_DCOC_RANGE_866___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_866__RX_DCOC_RANGE_866___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_866__RX_DCOC_RES_I_866___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_866__RX_DCOC_RES_I_866___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_866__RX_DCOC_RES_Q_866___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_866__RX_DCOC_RES_Q_866___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_866___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_866___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_867 (0x005F4D8C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_867___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_867___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_867__RX_DCOC_RANGE_867___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_867__RX_DCOC_RES_I_867___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_867__RX_DCOC_RES_Q_867___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_867__RX_DCOC_RANGE_867___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_867__RX_DCOC_RANGE_867___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_867__RX_DCOC_RES_I_867___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_867__RX_DCOC_RES_I_867___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_867__RX_DCOC_RES_Q_867___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_867__RX_DCOC_RES_Q_867___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_867___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_867___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_868 (0x005F4D90) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_868___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_868___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_868__RX_DCOC_RANGE_868___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_868__RX_DCOC_RES_I_868___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_868__RX_DCOC_RES_Q_868___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_868__RX_DCOC_RANGE_868___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_868__RX_DCOC_RANGE_868___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_868__RX_DCOC_RES_I_868___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_868__RX_DCOC_RES_I_868___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_868__RX_DCOC_RES_Q_868___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_868__RX_DCOC_RES_Q_868___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_868___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_868___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_869 (0x005F4D94) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_869___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_869___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_869__RX_DCOC_RANGE_869___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_869__RX_DCOC_RES_I_869___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_869__RX_DCOC_RES_Q_869___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_869__RX_DCOC_RANGE_869___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_869__RX_DCOC_RANGE_869___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_869__RX_DCOC_RES_I_869___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_869__RX_DCOC_RES_I_869___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_869__RX_DCOC_RES_Q_869___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_869__RX_DCOC_RES_Q_869___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_869___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_869___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_870 (0x005F4D98) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_870___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_870___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_870__RX_DCOC_RANGE_870___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_870__RX_DCOC_RES_I_870___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_870__RX_DCOC_RES_Q_870___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_870__RX_DCOC_RANGE_870___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_870__RX_DCOC_RANGE_870___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_870__RX_DCOC_RES_I_870___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_870__RX_DCOC_RES_I_870___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_870__RX_DCOC_RES_Q_870___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_870__RX_DCOC_RES_Q_870___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_870___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_870___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_871 (0x005F4D9C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_871___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_871___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_871__RX_DCOC_RANGE_871___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_871__RX_DCOC_RES_I_871___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_871__RX_DCOC_RES_Q_871___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_871__RX_DCOC_RANGE_871___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_871__RX_DCOC_RANGE_871___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_871__RX_DCOC_RES_I_871___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_871__RX_DCOC_RES_I_871___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_871__RX_DCOC_RES_Q_871___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_871__RX_DCOC_RES_Q_871___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_871___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_871___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_872 (0x005F4DA0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_872___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_872___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_872__RX_DCOC_RANGE_872___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_872__RX_DCOC_RES_I_872___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_872__RX_DCOC_RES_Q_872___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_872__RX_DCOC_RANGE_872___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_872__RX_DCOC_RANGE_872___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_872__RX_DCOC_RES_I_872___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_872__RX_DCOC_RES_I_872___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_872__RX_DCOC_RES_Q_872___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_872__RX_DCOC_RES_Q_872___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_872___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_872___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_873 (0x005F4DA4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_873___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_873___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_873__RX_DCOC_RANGE_873___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_873__RX_DCOC_RES_I_873___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_873__RX_DCOC_RES_Q_873___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_873__RX_DCOC_RANGE_873___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_873__RX_DCOC_RANGE_873___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_873__RX_DCOC_RES_I_873___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_873__RX_DCOC_RES_I_873___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_873__RX_DCOC_RES_Q_873___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_873__RX_DCOC_RES_Q_873___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_873___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_873___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_874 (0x005F4DA8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_874___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_874___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_874__RX_DCOC_RANGE_874___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_874__RX_DCOC_RES_I_874___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_874__RX_DCOC_RES_Q_874___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_874__RX_DCOC_RANGE_874___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_874__RX_DCOC_RANGE_874___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_874__RX_DCOC_RES_I_874___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_874__RX_DCOC_RES_I_874___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_874__RX_DCOC_RES_Q_874___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_874__RX_DCOC_RES_Q_874___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_874___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_874___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_875 (0x005F4DAC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_875___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_875___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_875__RX_DCOC_RANGE_875___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_875__RX_DCOC_RES_I_875___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_875__RX_DCOC_RES_Q_875___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_875__RX_DCOC_RANGE_875___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_875__RX_DCOC_RANGE_875___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_875__RX_DCOC_RES_I_875___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_875__RX_DCOC_RES_I_875___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_875__RX_DCOC_RES_Q_875___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_875__RX_DCOC_RES_Q_875___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_875___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_875___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_876 (0x005F4DB0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_876___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_876___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_876__RX_DCOC_RANGE_876___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_876__RX_DCOC_RES_I_876___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_876__RX_DCOC_RES_Q_876___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_876__RX_DCOC_RANGE_876___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_876__RX_DCOC_RANGE_876___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_876__RX_DCOC_RES_I_876___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_876__RX_DCOC_RES_I_876___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_876__RX_DCOC_RES_Q_876___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_876__RX_DCOC_RES_Q_876___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_876___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_876___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_877 (0x005F4DB4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_877___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_877___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_877__RX_DCOC_RANGE_877___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_877__RX_DCOC_RES_I_877___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_877__RX_DCOC_RES_Q_877___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_877__RX_DCOC_RANGE_877___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_877__RX_DCOC_RANGE_877___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_877__RX_DCOC_RES_I_877___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_877__RX_DCOC_RES_I_877___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_877__RX_DCOC_RES_Q_877___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_877__RX_DCOC_RES_Q_877___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_877___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_877___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_878 (0x005F4DB8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_878___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_878___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_878__RX_DCOC_RANGE_878___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_878__RX_DCOC_RES_I_878___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_878__RX_DCOC_RES_Q_878___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_878__RX_DCOC_RANGE_878___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_878__RX_DCOC_RANGE_878___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_878__RX_DCOC_RES_I_878___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_878__RX_DCOC_RES_I_878___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_878__RX_DCOC_RES_Q_878___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_878__RX_DCOC_RES_Q_878___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_878___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_878___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_879 (0x005F4DBC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_879___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_879___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_879__RX_DCOC_RANGE_879___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_879__RX_DCOC_RES_I_879___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_879__RX_DCOC_RES_Q_879___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_879__RX_DCOC_RANGE_879___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_879__RX_DCOC_RANGE_879___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_879__RX_DCOC_RES_I_879___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_879__RX_DCOC_RES_I_879___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_879__RX_DCOC_RES_Q_879___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_879__RX_DCOC_RES_Q_879___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_879___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_879___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_880 (0x005F4DC0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_880___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_880___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_880__RX_DCOC_RANGE_880___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_880__RX_DCOC_RES_I_880___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_880__RX_DCOC_RES_Q_880___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_880__RX_DCOC_RANGE_880___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_880__RX_DCOC_RANGE_880___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_880__RX_DCOC_RES_I_880___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_880__RX_DCOC_RES_I_880___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_880__RX_DCOC_RES_Q_880___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_880__RX_DCOC_RES_Q_880___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_880___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_880___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_881 (0x005F4DC4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_881___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_881___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_881__RX_DCOC_RANGE_881___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_881__RX_DCOC_RES_I_881___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_881__RX_DCOC_RES_Q_881___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_881__RX_DCOC_RANGE_881___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_881__RX_DCOC_RANGE_881___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_881__RX_DCOC_RES_I_881___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_881__RX_DCOC_RES_I_881___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_881__RX_DCOC_RES_Q_881___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_881__RX_DCOC_RES_Q_881___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_881___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_881___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_882 (0x005F4DC8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_882___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_882___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_882__RX_DCOC_RANGE_882___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_882__RX_DCOC_RES_I_882___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_882__RX_DCOC_RES_Q_882___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_882__RX_DCOC_RANGE_882___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_882__RX_DCOC_RANGE_882___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_882__RX_DCOC_RES_I_882___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_882__RX_DCOC_RES_I_882___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_882__RX_DCOC_RES_Q_882___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_882__RX_DCOC_RES_Q_882___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_882___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_882___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_883 (0x005F4DCC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_883___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_883___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_883__RX_DCOC_RANGE_883___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_883__RX_DCOC_RES_I_883___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_883__RX_DCOC_RES_Q_883___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_883__RX_DCOC_RANGE_883___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_883__RX_DCOC_RANGE_883___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_883__RX_DCOC_RES_I_883___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_883__RX_DCOC_RES_I_883___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_883__RX_DCOC_RES_Q_883___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_883__RX_DCOC_RES_Q_883___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_883___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_883___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_884 (0x005F4DD0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_884___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_884___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_884__RX_DCOC_RANGE_884___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_884__RX_DCOC_RES_I_884___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_884__RX_DCOC_RES_Q_884___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_884__RX_DCOC_RANGE_884___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_884__RX_DCOC_RANGE_884___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_884__RX_DCOC_RES_I_884___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_884__RX_DCOC_RES_I_884___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_884__RX_DCOC_RES_Q_884___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_884__RX_DCOC_RES_Q_884___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_884___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_884___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_885 (0x005F4DD4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_885___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_885___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_885__RX_DCOC_RANGE_885___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_885__RX_DCOC_RES_I_885___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_885__RX_DCOC_RES_Q_885___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_885__RX_DCOC_RANGE_885___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_885__RX_DCOC_RANGE_885___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_885__RX_DCOC_RES_I_885___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_885__RX_DCOC_RES_I_885___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_885__RX_DCOC_RES_Q_885___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_885__RX_DCOC_RES_Q_885___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_885___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_885___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_886 (0x005F4DD8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_886___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_886___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_886__RX_DCOC_RANGE_886___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_886__RX_DCOC_RES_I_886___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_886__RX_DCOC_RES_Q_886___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_886__RX_DCOC_RANGE_886___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_886__RX_DCOC_RANGE_886___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_886__RX_DCOC_RES_I_886___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_886__RX_DCOC_RES_I_886___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_886__RX_DCOC_RES_Q_886___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_886__RX_DCOC_RES_Q_886___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_886___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_886___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_887 (0x005F4DDC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_887___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_887___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_887__RX_DCOC_RANGE_887___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_887__RX_DCOC_RES_I_887___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_887__RX_DCOC_RES_Q_887___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_887__RX_DCOC_RANGE_887___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_887__RX_DCOC_RANGE_887___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_887__RX_DCOC_RES_I_887___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_887__RX_DCOC_RES_I_887___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_887__RX_DCOC_RES_Q_887___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_887__RX_DCOC_RES_Q_887___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_887___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_887___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_888 (0x005F4DE0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_888___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_888___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_888__RX_DCOC_RANGE_888___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_888__RX_DCOC_RES_I_888___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_888__RX_DCOC_RES_Q_888___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_888__RX_DCOC_RANGE_888___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_888__RX_DCOC_RANGE_888___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_888__RX_DCOC_RES_I_888___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_888__RX_DCOC_RES_I_888___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_888__RX_DCOC_RES_Q_888___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_888__RX_DCOC_RES_Q_888___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_888___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_888___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_889 (0x005F4DE4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_889___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_889___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_889__RX_DCOC_RANGE_889___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_889__RX_DCOC_RES_I_889___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_889__RX_DCOC_RES_Q_889___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_889__RX_DCOC_RANGE_889___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_889__RX_DCOC_RANGE_889___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_889__RX_DCOC_RES_I_889___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_889__RX_DCOC_RES_I_889___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_889__RX_DCOC_RES_Q_889___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_889__RX_DCOC_RES_Q_889___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_889___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_889___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_890 (0x005F4DE8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_890___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_890___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_890__RX_DCOC_RANGE_890___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_890__RX_DCOC_RES_I_890___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_890__RX_DCOC_RES_Q_890___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_890__RX_DCOC_RANGE_890___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_890__RX_DCOC_RANGE_890___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_890__RX_DCOC_RES_I_890___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_890__RX_DCOC_RES_I_890___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_890__RX_DCOC_RES_Q_890___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_890__RX_DCOC_RES_Q_890___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_890___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_890___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_891 (0x005F4DEC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_891___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_891___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_891__RX_DCOC_RANGE_891___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_891__RX_DCOC_RES_I_891___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_891__RX_DCOC_RES_Q_891___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_891__RX_DCOC_RANGE_891___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_891__RX_DCOC_RANGE_891___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_891__RX_DCOC_RES_I_891___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_891__RX_DCOC_RES_I_891___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_891__RX_DCOC_RES_Q_891___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_891__RX_DCOC_RES_Q_891___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_891___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_891___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_892 (0x005F4DF0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_892___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_892___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_892__RX_DCOC_RANGE_892___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_892__RX_DCOC_RES_I_892___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_892__RX_DCOC_RES_Q_892___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_892__RX_DCOC_RANGE_892___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_892__RX_DCOC_RANGE_892___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_892__RX_DCOC_RES_I_892___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_892__RX_DCOC_RES_I_892___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_892__RX_DCOC_RES_Q_892___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_892__RX_DCOC_RES_Q_892___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_892___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_892___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_893 (0x005F4DF4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_893___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_893___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_893__RX_DCOC_RANGE_893___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_893__RX_DCOC_RES_I_893___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_893__RX_DCOC_RES_Q_893___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_893__RX_DCOC_RANGE_893___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_893__RX_DCOC_RANGE_893___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_893__RX_DCOC_RES_I_893___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_893__RX_DCOC_RES_I_893___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_893__RX_DCOC_RES_Q_893___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_893__RX_DCOC_RES_Q_893___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_893___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_893___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_894 (0x005F4DF8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_894___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_894___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_894__RX_DCOC_RANGE_894___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_894__RX_DCOC_RES_I_894___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_894__RX_DCOC_RES_Q_894___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_894__RX_DCOC_RANGE_894___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_894__RX_DCOC_RANGE_894___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_894__RX_DCOC_RES_I_894___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_894__RX_DCOC_RES_I_894___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_894__RX_DCOC_RES_Q_894___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_894__RX_DCOC_RES_Q_894___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_894___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_894___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_895 (0x005F4DFC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_895___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_895___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_895__RX_DCOC_RANGE_895___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_895__RX_DCOC_RES_I_895___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_895__RX_DCOC_RES_Q_895___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_895__RX_DCOC_RANGE_895___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_895__RX_DCOC_RANGE_895___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_895__RX_DCOC_RES_I_895___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_895__RX_DCOC_RES_I_895___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_895__RX_DCOC_RES_Q_895___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_895__RX_DCOC_RES_Q_895___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_895___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_895___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_896 (0x005F4E00) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_896___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_896___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_896__RX_DCOC_RANGE_896___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_896__RX_DCOC_RES_I_896___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_896__RX_DCOC_RES_Q_896___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_896__RX_DCOC_RANGE_896___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_896__RX_DCOC_RANGE_896___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_896__RX_DCOC_RES_I_896___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_896__RX_DCOC_RES_I_896___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_896__RX_DCOC_RES_Q_896___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_896__RX_DCOC_RES_Q_896___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_896___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_896___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_897 (0x005F4E04) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_897___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_897___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_897__RX_DCOC_RANGE_897___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_897__RX_DCOC_RES_I_897___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_897__RX_DCOC_RES_Q_897___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_897__RX_DCOC_RANGE_897___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_897__RX_DCOC_RANGE_897___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_897__RX_DCOC_RES_I_897___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_897__RX_DCOC_RES_I_897___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_897__RX_DCOC_RES_Q_897___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_897__RX_DCOC_RES_Q_897___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_897___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_897___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_898 (0x005F4E08) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_898___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_898___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_898__RX_DCOC_RANGE_898___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_898__RX_DCOC_RES_I_898___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_898__RX_DCOC_RES_Q_898___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_898__RX_DCOC_RANGE_898___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_898__RX_DCOC_RANGE_898___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_898__RX_DCOC_RES_I_898___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_898__RX_DCOC_RES_I_898___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_898__RX_DCOC_RES_Q_898___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_898__RX_DCOC_RES_Q_898___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_898___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_898___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_899 (0x005F4E0C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_899___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_899___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_899__RX_DCOC_RANGE_899___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_899__RX_DCOC_RES_I_899___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_899__RX_DCOC_RES_Q_899___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_899__RX_DCOC_RANGE_899___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_899__RX_DCOC_RANGE_899___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_899__RX_DCOC_RES_I_899___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_899__RX_DCOC_RES_I_899___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_899__RX_DCOC_RES_Q_899___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_899__RX_DCOC_RES_Q_899___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_899___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_899___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_900 (0x005F4E10) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_900___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_900___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_900__RX_DCOC_RANGE_900___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_900__RX_DCOC_RES_I_900___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_900__RX_DCOC_RES_Q_900___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_900__RX_DCOC_RANGE_900___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_900__RX_DCOC_RANGE_900___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_900__RX_DCOC_RES_I_900___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_900__RX_DCOC_RES_I_900___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_900__RX_DCOC_RES_Q_900___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_900__RX_DCOC_RES_Q_900___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_900___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_900___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_901 (0x005F4E14) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_901___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_901___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_901__RX_DCOC_RANGE_901___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_901__RX_DCOC_RES_I_901___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_901__RX_DCOC_RES_Q_901___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_901__RX_DCOC_RANGE_901___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_901__RX_DCOC_RANGE_901___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_901__RX_DCOC_RES_I_901___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_901__RX_DCOC_RES_I_901___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_901__RX_DCOC_RES_Q_901___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_901__RX_DCOC_RES_Q_901___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_901___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_901___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_902 (0x005F4E18) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_902___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_902___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_902__RX_DCOC_RANGE_902___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_902__RX_DCOC_RES_I_902___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_902__RX_DCOC_RES_Q_902___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_902__RX_DCOC_RANGE_902___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_902__RX_DCOC_RANGE_902___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_902__RX_DCOC_RES_I_902___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_902__RX_DCOC_RES_I_902___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_902__RX_DCOC_RES_Q_902___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_902__RX_DCOC_RES_Q_902___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_902___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_902___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_903 (0x005F4E1C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_903___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_903___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_903__RX_DCOC_RANGE_903___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_903__RX_DCOC_RES_I_903___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_903__RX_DCOC_RES_Q_903___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_903__RX_DCOC_RANGE_903___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_903__RX_DCOC_RANGE_903___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_903__RX_DCOC_RES_I_903___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_903__RX_DCOC_RES_I_903___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_903__RX_DCOC_RES_Q_903___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_903__RX_DCOC_RES_Q_903___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_903___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_903___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_904 (0x005F4E20) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_904___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_904___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_904__RX_DCOC_RANGE_904___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_904__RX_DCOC_RES_I_904___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_904__RX_DCOC_RES_Q_904___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_904__RX_DCOC_RANGE_904___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_904__RX_DCOC_RANGE_904___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_904__RX_DCOC_RES_I_904___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_904__RX_DCOC_RES_I_904___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_904__RX_DCOC_RES_Q_904___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_904__RX_DCOC_RES_Q_904___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_904___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_904___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_905 (0x005F4E24) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_905___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_905___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_905__RX_DCOC_RANGE_905___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_905__RX_DCOC_RES_I_905___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_905__RX_DCOC_RES_Q_905___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_905__RX_DCOC_RANGE_905___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_905__RX_DCOC_RANGE_905___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_905__RX_DCOC_RES_I_905___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_905__RX_DCOC_RES_I_905___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_905__RX_DCOC_RES_Q_905___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_905__RX_DCOC_RES_Q_905___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_905___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_905___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_906 (0x005F4E28) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_906___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_906___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_906__RX_DCOC_RANGE_906___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_906__RX_DCOC_RES_I_906___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_906__RX_DCOC_RES_Q_906___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_906__RX_DCOC_RANGE_906___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_906__RX_DCOC_RANGE_906___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_906__RX_DCOC_RES_I_906___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_906__RX_DCOC_RES_I_906___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_906__RX_DCOC_RES_Q_906___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_906__RX_DCOC_RES_Q_906___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_906___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_906___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_907 (0x005F4E2C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_907___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_907___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_907__RX_DCOC_RANGE_907___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_907__RX_DCOC_RES_I_907___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_907__RX_DCOC_RES_Q_907___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_907__RX_DCOC_RANGE_907___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_907__RX_DCOC_RANGE_907___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_907__RX_DCOC_RES_I_907___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_907__RX_DCOC_RES_I_907___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_907__RX_DCOC_RES_Q_907___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_907__RX_DCOC_RES_Q_907___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_907___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_907___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_908 (0x005F4E30) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_908___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_908___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_908__RX_DCOC_RANGE_908___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_908__RX_DCOC_RES_I_908___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_908__RX_DCOC_RES_Q_908___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_908__RX_DCOC_RANGE_908___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_908__RX_DCOC_RANGE_908___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_908__RX_DCOC_RES_I_908___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_908__RX_DCOC_RES_I_908___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_908__RX_DCOC_RES_Q_908___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_908__RX_DCOC_RES_Q_908___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_908___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_908___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_909 (0x005F4E34) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_909___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_909___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_909__RX_DCOC_RANGE_909___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_909__RX_DCOC_RES_I_909___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_909__RX_DCOC_RES_Q_909___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_909__RX_DCOC_RANGE_909___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_909__RX_DCOC_RANGE_909___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_909__RX_DCOC_RES_I_909___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_909__RX_DCOC_RES_I_909___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_909__RX_DCOC_RES_Q_909___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_909__RX_DCOC_RES_Q_909___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_909___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_909___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_910 (0x005F4E38) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_910___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_910___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_910__RX_DCOC_RANGE_910___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_910__RX_DCOC_RES_I_910___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_910__RX_DCOC_RES_Q_910___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_910__RX_DCOC_RANGE_910___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_910__RX_DCOC_RANGE_910___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_910__RX_DCOC_RES_I_910___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_910__RX_DCOC_RES_I_910___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_910__RX_DCOC_RES_Q_910___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_910__RX_DCOC_RES_Q_910___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_910___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_910___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_911 (0x005F4E3C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_911___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_911___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_911__RX_DCOC_RANGE_911___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_911__RX_DCOC_RES_I_911___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_911__RX_DCOC_RES_Q_911___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_911__RX_DCOC_RANGE_911___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_911__RX_DCOC_RANGE_911___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_911__RX_DCOC_RES_I_911___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_911__RX_DCOC_RES_I_911___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_911__RX_DCOC_RES_Q_911___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_911__RX_DCOC_RES_Q_911___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_911___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_911___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_912 (0x005F4E40) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_912___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_912___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_912__RX_DCOC_RANGE_912___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_912__RX_DCOC_RES_I_912___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_912__RX_DCOC_RES_Q_912___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_912__RX_DCOC_RANGE_912___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_912__RX_DCOC_RANGE_912___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_912__RX_DCOC_RES_I_912___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_912__RX_DCOC_RES_I_912___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_912__RX_DCOC_RES_Q_912___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_912__RX_DCOC_RES_Q_912___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_912___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_912___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_913 (0x005F4E44) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_913___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_913___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_913__RX_DCOC_RANGE_913___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_913__RX_DCOC_RES_I_913___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_913__RX_DCOC_RES_Q_913___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_913__RX_DCOC_RANGE_913___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_913__RX_DCOC_RANGE_913___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_913__RX_DCOC_RES_I_913___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_913__RX_DCOC_RES_I_913___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_913__RX_DCOC_RES_Q_913___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_913__RX_DCOC_RES_Q_913___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_913___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_913___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_914 (0x005F4E48) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_914___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_914___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_914__RX_DCOC_RANGE_914___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_914__RX_DCOC_RES_I_914___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_914__RX_DCOC_RES_Q_914___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_914__RX_DCOC_RANGE_914___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_914__RX_DCOC_RANGE_914___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_914__RX_DCOC_RES_I_914___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_914__RX_DCOC_RES_I_914___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_914__RX_DCOC_RES_Q_914___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_914__RX_DCOC_RES_Q_914___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_914___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_914___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_915 (0x005F4E4C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_915___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_915___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_915__RX_DCOC_RANGE_915___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_915__RX_DCOC_RES_I_915___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_915__RX_DCOC_RES_Q_915___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_915__RX_DCOC_RANGE_915___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_915__RX_DCOC_RANGE_915___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_915__RX_DCOC_RES_I_915___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_915__RX_DCOC_RES_I_915___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_915__RX_DCOC_RES_Q_915___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_915__RX_DCOC_RES_Q_915___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_915___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_915___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_916 (0x005F4E50) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_916___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_916___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_916__RX_DCOC_RANGE_916___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_916__RX_DCOC_RES_I_916___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_916__RX_DCOC_RES_Q_916___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_916__RX_DCOC_RANGE_916___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_916__RX_DCOC_RANGE_916___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_916__RX_DCOC_RES_I_916___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_916__RX_DCOC_RES_I_916___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_916__RX_DCOC_RES_Q_916___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_916__RX_DCOC_RES_Q_916___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_916___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_916___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_917 (0x005F4E54) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_917___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_917___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_917__RX_DCOC_RANGE_917___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_917__RX_DCOC_RES_I_917___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_917__RX_DCOC_RES_Q_917___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_917__RX_DCOC_RANGE_917___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_917__RX_DCOC_RANGE_917___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_917__RX_DCOC_RES_I_917___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_917__RX_DCOC_RES_I_917___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_917__RX_DCOC_RES_Q_917___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_917__RX_DCOC_RES_Q_917___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_917___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_917___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_918 (0x005F4E58) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_918___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_918___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_918__RX_DCOC_RANGE_918___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_918__RX_DCOC_RES_I_918___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_918__RX_DCOC_RES_Q_918___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_918__RX_DCOC_RANGE_918___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_918__RX_DCOC_RANGE_918___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_918__RX_DCOC_RES_I_918___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_918__RX_DCOC_RES_I_918___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_918__RX_DCOC_RES_Q_918___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_918__RX_DCOC_RES_Q_918___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_918___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_918___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_919 (0x005F4E5C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_919___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_919___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_919__RX_DCOC_RANGE_919___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_919__RX_DCOC_RES_I_919___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_919__RX_DCOC_RES_Q_919___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_919__RX_DCOC_RANGE_919___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_919__RX_DCOC_RANGE_919___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_919__RX_DCOC_RES_I_919___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_919__RX_DCOC_RES_I_919___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_919__RX_DCOC_RES_Q_919___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_919__RX_DCOC_RES_Q_919___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_919___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_919___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_920 (0x005F4E60) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_920___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_920___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_920__RX_DCOC_RANGE_920___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_920__RX_DCOC_RES_I_920___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_920__RX_DCOC_RES_Q_920___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_920__RX_DCOC_RANGE_920___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_920__RX_DCOC_RANGE_920___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_920__RX_DCOC_RES_I_920___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_920__RX_DCOC_RES_I_920___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_920__RX_DCOC_RES_Q_920___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_920__RX_DCOC_RES_Q_920___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_920___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_920___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_921 (0x005F4E64) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_921___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_921___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_921__RX_DCOC_RANGE_921___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_921__RX_DCOC_RES_I_921___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_921__RX_DCOC_RES_Q_921___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_921__RX_DCOC_RANGE_921___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_921__RX_DCOC_RANGE_921___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_921__RX_DCOC_RES_I_921___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_921__RX_DCOC_RES_I_921___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_921__RX_DCOC_RES_Q_921___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_921__RX_DCOC_RES_Q_921___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_921___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_921___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_922 (0x005F4E68) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_922___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_922___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_922__RX_DCOC_RANGE_922___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_922__RX_DCOC_RES_I_922___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_922__RX_DCOC_RES_Q_922___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_922__RX_DCOC_RANGE_922___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_922__RX_DCOC_RANGE_922___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_922__RX_DCOC_RES_I_922___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_922__RX_DCOC_RES_I_922___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_922__RX_DCOC_RES_Q_922___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_922__RX_DCOC_RES_Q_922___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_922___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_922___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_923 (0x005F4E6C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_923___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_923___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_923__RX_DCOC_RANGE_923___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_923__RX_DCOC_RES_I_923___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_923__RX_DCOC_RES_Q_923___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_923__RX_DCOC_RANGE_923___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_923__RX_DCOC_RANGE_923___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_923__RX_DCOC_RES_I_923___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_923__RX_DCOC_RES_I_923___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_923__RX_DCOC_RES_Q_923___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_923__RX_DCOC_RES_Q_923___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_923___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_923___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_924 (0x005F4E70) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_924___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_924___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_924__RX_DCOC_RANGE_924___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_924__RX_DCOC_RES_I_924___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_924__RX_DCOC_RES_Q_924___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_924__RX_DCOC_RANGE_924___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_924__RX_DCOC_RANGE_924___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_924__RX_DCOC_RES_I_924___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_924__RX_DCOC_RES_I_924___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_924__RX_DCOC_RES_Q_924___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_924__RX_DCOC_RES_Q_924___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_924___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_924___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_925 (0x005F4E74) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_925___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_925___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_925__RX_DCOC_RANGE_925___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_925__RX_DCOC_RES_I_925___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_925__RX_DCOC_RES_Q_925___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_925__RX_DCOC_RANGE_925___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_925__RX_DCOC_RANGE_925___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_925__RX_DCOC_RES_I_925___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_925__RX_DCOC_RES_I_925___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_925__RX_DCOC_RES_Q_925___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_925__RX_DCOC_RES_Q_925___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_925___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_925___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_926 (0x005F4E78) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_926___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_926___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_926__RX_DCOC_RANGE_926___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_926__RX_DCOC_RES_I_926___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_926__RX_DCOC_RES_Q_926___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_926__RX_DCOC_RANGE_926___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_926__RX_DCOC_RANGE_926___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_926__RX_DCOC_RES_I_926___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_926__RX_DCOC_RES_I_926___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_926__RX_DCOC_RES_Q_926___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_926__RX_DCOC_RES_Q_926___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_926___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_926___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_927 (0x005F4E7C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_927___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_927___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_927__RX_DCOC_RANGE_927___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_927__RX_DCOC_RES_I_927___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_927__RX_DCOC_RES_Q_927___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_927__RX_DCOC_RANGE_927___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_927__RX_DCOC_RANGE_927___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_927__RX_DCOC_RES_I_927___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_927__RX_DCOC_RES_I_927___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_927__RX_DCOC_RES_Q_927___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_927__RX_DCOC_RES_Q_927___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_927___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_927___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_928 (0x005F4E80) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_928___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_928___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_928__RX_DCOC_RANGE_928___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_928__RX_DCOC_RES_I_928___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_928__RX_DCOC_RES_Q_928___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_928__RX_DCOC_RANGE_928___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_928__RX_DCOC_RANGE_928___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_928__RX_DCOC_RES_I_928___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_928__RX_DCOC_RES_I_928___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_928__RX_DCOC_RES_Q_928___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_928__RX_DCOC_RES_Q_928___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_928___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_928___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_929 (0x005F4E84) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_929___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_929___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_929__RX_DCOC_RANGE_929___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_929__RX_DCOC_RES_I_929___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_929__RX_DCOC_RES_Q_929___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_929__RX_DCOC_RANGE_929___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_929__RX_DCOC_RANGE_929___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_929__RX_DCOC_RES_I_929___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_929__RX_DCOC_RES_I_929___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_929__RX_DCOC_RES_Q_929___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_929__RX_DCOC_RES_Q_929___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_929___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_929___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_930 (0x005F4E88) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_930___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_930___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_930__RX_DCOC_RANGE_930___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_930__RX_DCOC_RES_I_930___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_930__RX_DCOC_RES_Q_930___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_930__RX_DCOC_RANGE_930___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_930__RX_DCOC_RANGE_930___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_930__RX_DCOC_RES_I_930___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_930__RX_DCOC_RES_I_930___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_930__RX_DCOC_RES_Q_930___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_930__RX_DCOC_RES_Q_930___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_930___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_930___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_931 (0x005F4E8C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_931___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_931___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_931__RX_DCOC_RANGE_931___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_931__RX_DCOC_RES_I_931___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_931__RX_DCOC_RES_Q_931___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_931__RX_DCOC_RANGE_931___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_931__RX_DCOC_RANGE_931___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_931__RX_DCOC_RES_I_931___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_931__RX_DCOC_RES_I_931___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_931__RX_DCOC_RES_Q_931___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_931__RX_DCOC_RES_Q_931___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_931___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_931___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_932 (0x005F4E90) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_932___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_932___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_932__RX_DCOC_RANGE_932___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_932__RX_DCOC_RES_I_932___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_932__RX_DCOC_RES_Q_932___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_932__RX_DCOC_RANGE_932___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_932__RX_DCOC_RANGE_932___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_932__RX_DCOC_RES_I_932___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_932__RX_DCOC_RES_I_932___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_932__RX_DCOC_RES_Q_932___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_932__RX_DCOC_RES_Q_932___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_932___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_932___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_933 (0x005F4E94) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_933___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_933___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_933__RX_DCOC_RANGE_933___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_933__RX_DCOC_RES_I_933___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_933__RX_DCOC_RES_Q_933___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_933__RX_DCOC_RANGE_933___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_933__RX_DCOC_RANGE_933___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_933__RX_DCOC_RES_I_933___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_933__RX_DCOC_RES_I_933___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_933__RX_DCOC_RES_Q_933___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_933__RX_DCOC_RES_Q_933___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_933___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_933___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_934 (0x005F4E98) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_934___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_934___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_934__RX_DCOC_RANGE_934___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_934__RX_DCOC_RES_I_934___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_934__RX_DCOC_RES_Q_934___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_934__RX_DCOC_RANGE_934___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_934__RX_DCOC_RANGE_934___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_934__RX_DCOC_RES_I_934___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_934__RX_DCOC_RES_I_934___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_934__RX_DCOC_RES_Q_934___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_934__RX_DCOC_RES_Q_934___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_934___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_934___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_935 (0x005F4E9C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_935___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_935___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_935__RX_DCOC_RANGE_935___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_935__RX_DCOC_RES_I_935___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_935__RX_DCOC_RES_Q_935___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_935__RX_DCOC_RANGE_935___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_935__RX_DCOC_RANGE_935___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_935__RX_DCOC_RES_I_935___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_935__RX_DCOC_RES_I_935___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_935__RX_DCOC_RES_Q_935___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_935__RX_DCOC_RES_Q_935___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_935___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_935___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_936 (0x005F4EA0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_936___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_936___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_936__RX_DCOC_RANGE_936___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_936__RX_DCOC_RES_I_936___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_936__RX_DCOC_RES_Q_936___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_936__RX_DCOC_RANGE_936___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_936__RX_DCOC_RANGE_936___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_936__RX_DCOC_RES_I_936___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_936__RX_DCOC_RES_I_936___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_936__RX_DCOC_RES_Q_936___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_936__RX_DCOC_RES_Q_936___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_936___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_936___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_937 (0x005F4EA4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_937___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_937___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_937__RX_DCOC_RANGE_937___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_937__RX_DCOC_RES_I_937___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_937__RX_DCOC_RES_Q_937___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_937__RX_DCOC_RANGE_937___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_937__RX_DCOC_RANGE_937___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_937__RX_DCOC_RES_I_937___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_937__RX_DCOC_RES_I_937___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_937__RX_DCOC_RES_Q_937___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_937__RX_DCOC_RES_Q_937___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_937___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_937___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_938 (0x005F4EA8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_938___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_938___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_938__RX_DCOC_RANGE_938___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_938__RX_DCOC_RES_I_938___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_938__RX_DCOC_RES_Q_938___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_938__RX_DCOC_RANGE_938___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_938__RX_DCOC_RANGE_938___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_938__RX_DCOC_RES_I_938___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_938__RX_DCOC_RES_I_938___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_938__RX_DCOC_RES_Q_938___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_938__RX_DCOC_RES_Q_938___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_938___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_938___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_939 (0x005F4EAC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_939___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_939___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_939__RX_DCOC_RANGE_939___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_939__RX_DCOC_RES_I_939___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_939__RX_DCOC_RES_Q_939___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_939__RX_DCOC_RANGE_939___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_939__RX_DCOC_RANGE_939___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_939__RX_DCOC_RES_I_939___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_939__RX_DCOC_RES_I_939___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_939__RX_DCOC_RES_Q_939___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_939__RX_DCOC_RES_Q_939___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_939___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_939___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_940 (0x005F4EB0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_940___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_940___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_940__RX_DCOC_RANGE_940___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_940__RX_DCOC_RES_I_940___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_940__RX_DCOC_RES_Q_940___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_940__RX_DCOC_RANGE_940___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_940__RX_DCOC_RANGE_940___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_940__RX_DCOC_RES_I_940___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_940__RX_DCOC_RES_I_940___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_940__RX_DCOC_RES_Q_940___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_940__RX_DCOC_RES_Q_940___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_940___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_940___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_941 (0x005F4EB4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_941___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_941___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_941__RX_DCOC_RANGE_941___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_941__RX_DCOC_RES_I_941___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_941__RX_DCOC_RES_Q_941___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_941__RX_DCOC_RANGE_941___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_941__RX_DCOC_RANGE_941___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_941__RX_DCOC_RES_I_941___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_941__RX_DCOC_RES_I_941___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_941__RX_DCOC_RES_Q_941___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_941__RX_DCOC_RES_Q_941___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_941___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_941___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_942 (0x005F4EB8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_942___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_942___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_942__RX_DCOC_RANGE_942___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_942__RX_DCOC_RES_I_942___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_942__RX_DCOC_RES_Q_942___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_942__RX_DCOC_RANGE_942___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_942__RX_DCOC_RANGE_942___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_942__RX_DCOC_RES_I_942___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_942__RX_DCOC_RES_I_942___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_942__RX_DCOC_RES_Q_942___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_942__RX_DCOC_RES_Q_942___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_942___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_942___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_943 (0x005F4EBC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_943___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_943___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_943__RX_DCOC_RANGE_943___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_943__RX_DCOC_RES_I_943___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_943__RX_DCOC_RES_Q_943___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_943__RX_DCOC_RANGE_943___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_943__RX_DCOC_RANGE_943___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_943__RX_DCOC_RES_I_943___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_943__RX_DCOC_RES_I_943___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_943__RX_DCOC_RES_Q_943___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_943__RX_DCOC_RES_Q_943___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_943___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_943___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_944 (0x005F4EC0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_944___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_944___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_944__RX_DCOC_RANGE_944___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_944__RX_DCOC_RES_I_944___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_944__RX_DCOC_RES_Q_944___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_944__RX_DCOC_RANGE_944___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_944__RX_DCOC_RANGE_944___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_944__RX_DCOC_RES_I_944___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_944__RX_DCOC_RES_I_944___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_944__RX_DCOC_RES_Q_944___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_944__RX_DCOC_RES_Q_944___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_944___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_944___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_945 (0x005F4EC4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_945___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_945___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_945__RX_DCOC_RANGE_945___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_945__RX_DCOC_RES_I_945___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_945__RX_DCOC_RES_Q_945___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_945__RX_DCOC_RANGE_945___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_945__RX_DCOC_RANGE_945___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_945__RX_DCOC_RES_I_945___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_945__RX_DCOC_RES_I_945___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_945__RX_DCOC_RES_Q_945___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_945__RX_DCOC_RES_Q_945___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_945___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_945___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_946 (0x005F4EC8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_946___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_946___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_946__RX_DCOC_RANGE_946___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_946__RX_DCOC_RES_I_946___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_946__RX_DCOC_RES_Q_946___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_946__RX_DCOC_RANGE_946___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_946__RX_DCOC_RANGE_946___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_946__RX_DCOC_RES_I_946___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_946__RX_DCOC_RES_I_946___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_946__RX_DCOC_RES_Q_946___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_946__RX_DCOC_RES_Q_946___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_946___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_946___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_947 (0x005F4ECC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_947___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_947___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_947__RX_DCOC_RANGE_947___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_947__RX_DCOC_RES_I_947___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_947__RX_DCOC_RES_Q_947___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_947__RX_DCOC_RANGE_947___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_947__RX_DCOC_RANGE_947___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_947__RX_DCOC_RES_I_947___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_947__RX_DCOC_RES_I_947___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_947__RX_DCOC_RES_Q_947___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_947__RX_DCOC_RES_Q_947___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_947___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_947___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_948 (0x005F4ED0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_948___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_948___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_948__RX_DCOC_RANGE_948___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_948__RX_DCOC_RES_I_948___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_948__RX_DCOC_RES_Q_948___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_948__RX_DCOC_RANGE_948___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_948__RX_DCOC_RANGE_948___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_948__RX_DCOC_RES_I_948___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_948__RX_DCOC_RES_I_948___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_948__RX_DCOC_RES_Q_948___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_948__RX_DCOC_RES_Q_948___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_948___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_948___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_949 (0x005F4ED4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_949___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_949___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_949__RX_DCOC_RANGE_949___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_949__RX_DCOC_RES_I_949___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_949__RX_DCOC_RES_Q_949___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_949__RX_DCOC_RANGE_949___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_949__RX_DCOC_RANGE_949___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_949__RX_DCOC_RES_I_949___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_949__RX_DCOC_RES_I_949___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_949__RX_DCOC_RES_Q_949___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_949__RX_DCOC_RES_Q_949___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_949___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_949___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_950 (0x005F4ED8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_950___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_950___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_950__RX_DCOC_RANGE_950___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_950__RX_DCOC_RES_I_950___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_950__RX_DCOC_RES_Q_950___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_950__RX_DCOC_RANGE_950___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_950__RX_DCOC_RANGE_950___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_950__RX_DCOC_RES_I_950___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_950__RX_DCOC_RES_I_950___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_950__RX_DCOC_RES_Q_950___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_950__RX_DCOC_RES_Q_950___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_950___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_950___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_951 (0x005F4EDC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_951___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_951___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_951__RX_DCOC_RANGE_951___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_951__RX_DCOC_RES_I_951___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_951__RX_DCOC_RES_Q_951___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_951__RX_DCOC_RANGE_951___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_951__RX_DCOC_RANGE_951___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_951__RX_DCOC_RES_I_951___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_951__RX_DCOC_RES_I_951___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_951__RX_DCOC_RES_Q_951___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_951__RX_DCOC_RES_Q_951___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_951___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_951___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_952 (0x005F4EE0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_952___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_952___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_952__RX_DCOC_RANGE_952___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_952__RX_DCOC_RES_I_952___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_952__RX_DCOC_RES_Q_952___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_952__RX_DCOC_RANGE_952___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_952__RX_DCOC_RANGE_952___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_952__RX_DCOC_RES_I_952___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_952__RX_DCOC_RES_I_952___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_952__RX_DCOC_RES_Q_952___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_952__RX_DCOC_RES_Q_952___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_952___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_952___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_953 (0x005F4EE4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_953___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_953___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_953__RX_DCOC_RANGE_953___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_953__RX_DCOC_RES_I_953___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_953__RX_DCOC_RES_Q_953___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_953__RX_DCOC_RANGE_953___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_953__RX_DCOC_RANGE_953___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_953__RX_DCOC_RES_I_953___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_953__RX_DCOC_RES_I_953___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_953__RX_DCOC_RES_Q_953___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_953__RX_DCOC_RES_Q_953___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_953___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_953___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_954 (0x005F4EE8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_954___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_954___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_954__RX_DCOC_RANGE_954___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_954__RX_DCOC_RES_I_954___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_954__RX_DCOC_RES_Q_954___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_954__RX_DCOC_RANGE_954___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_954__RX_DCOC_RANGE_954___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_954__RX_DCOC_RES_I_954___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_954__RX_DCOC_RES_I_954___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_954__RX_DCOC_RES_Q_954___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_954__RX_DCOC_RES_Q_954___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_954___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_954___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_955 (0x005F4EEC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_955___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_955___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_955__RX_DCOC_RANGE_955___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_955__RX_DCOC_RES_I_955___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_955__RX_DCOC_RES_Q_955___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_955__RX_DCOC_RANGE_955___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_955__RX_DCOC_RANGE_955___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_955__RX_DCOC_RES_I_955___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_955__RX_DCOC_RES_I_955___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_955__RX_DCOC_RES_Q_955___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_955__RX_DCOC_RES_Q_955___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_955___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_955___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_956 (0x005F4EF0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_956___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_956___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_956__RX_DCOC_RANGE_956___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_956__RX_DCOC_RES_I_956___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_956__RX_DCOC_RES_Q_956___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_956__RX_DCOC_RANGE_956___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_956__RX_DCOC_RANGE_956___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_956__RX_DCOC_RES_I_956___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_956__RX_DCOC_RES_I_956___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_956__RX_DCOC_RES_Q_956___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_956__RX_DCOC_RES_Q_956___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_956___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_956___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_957 (0x005F4EF4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_957___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_957___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_957__RX_DCOC_RANGE_957___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_957__RX_DCOC_RES_I_957___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_957__RX_DCOC_RES_Q_957___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_957__RX_DCOC_RANGE_957___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_957__RX_DCOC_RANGE_957___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_957__RX_DCOC_RES_I_957___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_957__RX_DCOC_RES_I_957___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_957__RX_DCOC_RES_Q_957___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_957__RX_DCOC_RES_Q_957___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_957___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_957___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_958 (0x005F4EF8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_958___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_958___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_958__RX_DCOC_RANGE_958___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_958__RX_DCOC_RES_I_958___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_958__RX_DCOC_RES_Q_958___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_958__RX_DCOC_RANGE_958___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_958__RX_DCOC_RANGE_958___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_958__RX_DCOC_RES_I_958___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_958__RX_DCOC_RES_I_958___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_958__RX_DCOC_RES_Q_958___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_958__RX_DCOC_RES_Q_958___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_958___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_958___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_959 (0x005F4EFC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_959___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_959___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_959__RX_DCOC_RANGE_959___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_959__RX_DCOC_RES_I_959___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_959__RX_DCOC_RES_Q_959___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_959__RX_DCOC_RANGE_959___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_959__RX_DCOC_RANGE_959___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_959__RX_DCOC_RES_I_959___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_959__RX_DCOC_RES_I_959___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_959__RX_DCOC_RES_Q_959___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_959__RX_DCOC_RES_Q_959___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_959___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_959___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_960 (0x005F4F00) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_960___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_960___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_960__RX_DCOC_RANGE_960___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_960__RX_DCOC_RES_I_960___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_960__RX_DCOC_RES_Q_960___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_960__RX_DCOC_RANGE_960___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_960__RX_DCOC_RANGE_960___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_960__RX_DCOC_RES_I_960___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_960__RX_DCOC_RES_I_960___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_960__RX_DCOC_RES_Q_960___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_960__RX_DCOC_RES_Q_960___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_960___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_960___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_961 (0x005F4F04) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_961___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_961___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_961__RX_DCOC_RANGE_961___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_961__RX_DCOC_RES_I_961___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_961__RX_DCOC_RES_Q_961___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_961__RX_DCOC_RANGE_961___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_961__RX_DCOC_RANGE_961___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_961__RX_DCOC_RES_I_961___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_961__RX_DCOC_RES_I_961___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_961__RX_DCOC_RES_Q_961___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_961__RX_DCOC_RES_Q_961___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_961___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_961___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_962 (0x005F4F08) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_962___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_962___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_962__RX_DCOC_RANGE_962___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_962__RX_DCOC_RES_I_962___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_962__RX_DCOC_RES_Q_962___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_962__RX_DCOC_RANGE_962___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_962__RX_DCOC_RANGE_962___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_962__RX_DCOC_RES_I_962___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_962__RX_DCOC_RES_I_962___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_962__RX_DCOC_RES_Q_962___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_962__RX_DCOC_RES_Q_962___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_962___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_962___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_963 (0x005F4F0C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_963___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_963___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_963__RX_DCOC_RANGE_963___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_963__RX_DCOC_RES_I_963___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_963__RX_DCOC_RES_Q_963___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_963__RX_DCOC_RANGE_963___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_963__RX_DCOC_RANGE_963___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_963__RX_DCOC_RES_I_963___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_963__RX_DCOC_RES_I_963___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_963__RX_DCOC_RES_Q_963___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_963__RX_DCOC_RES_Q_963___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_963___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_963___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_964 (0x005F4F10) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_964___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_964___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_964__RX_DCOC_RANGE_964___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_964__RX_DCOC_RES_I_964___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_964__RX_DCOC_RES_Q_964___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_964__RX_DCOC_RANGE_964___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_964__RX_DCOC_RANGE_964___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_964__RX_DCOC_RES_I_964___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_964__RX_DCOC_RES_I_964___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_964__RX_DCOC_RES_Q_964___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_964__RX_DCOC_RES_Q_964___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_964___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_964___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_965 (0x005F4F14) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_965___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_965___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_965__RX_DCOC_RANGE_965___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_965__RX_DCOC_RES_I_965___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_965__RX_DCOC_RES_Q_965___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_965__RX_DCOC_RANGE_965___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_965__RX_DCOC_RANGE_965___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_965__RX_DCOC_RES_I_965___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_965__RX_DCOC_RES_I_965___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_965__RX_DCOC_RES_Q_965___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_965__RX_DCOC_RES_Q_965___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_965___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_965___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_966 (0x005F4F18) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_966___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_966___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_966__RX_DCOC_RANGE_966___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_966__RX_DCOC_RES_I_966___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_966__RX_DCOC_RES_Q_966___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_966__RX_DCOC_RANGE_966___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_966__RX_DCOC_RANGE_966___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_966__RX_DCOC_RES_I_966___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_966__RX_DCOC_RES_I_966___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_966__RX_DCOC_RES_Q_966___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_966__RX_DCOC_RES_Q_966___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_966___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_966___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_967 (0x005F4F1C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_967___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_967___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_967__RX_DCOC_RANGE_967___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_967__RX_DCOC_RES_I_967___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_967__RX_DCOC_RES_Q_967___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_967__RX_DCOC_RANGE_967___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_967__RX_DCOC_RANGE_967___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_967__RX_DCOC_RES_I_967___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_967__RX_DCOC_RES_I_967___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_967__RX_DCOC_RES_Q_967___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_967__RX_DCOC_RES_Q_967___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_967___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_967___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_968 (0x005F4F20) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_968___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_968___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_968__RX_DCOC_RANGE_968___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_968__RX_DCOC_RES_I_968___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_968__RX_DCOC_RES_Q_968___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_968__RX_DCOC_RANGE_968___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_968__RX_DCOC_RANGE_968___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_968__RX_DCOC_RES_I_968___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_968__RX_DCOC_RES_I_968___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_968__RX_DCOC_RES_Q_968___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_968__RX_DCOC_RES_Q_968___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_968___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_968___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_969 (0x005F4F24) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_969___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_969___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_969__RX_DCOC_RANGE_969___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_969__RX_DCOC_RES_I_969___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_969__RX_DCOC_RES_Q_969___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_969__RX_DCOC_RANGE_969___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_969__RX_DCOC_RANGE_969___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_969__RX_DCOC_RES_I_969___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_969__RX_DCOC_RES_I_969___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_969__RX_DCOC_RES_Q_969___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_969__RX_DCOC_RES_Q_969___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_969___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_969___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_970 (0x005F4F28) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_970___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_970___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_970__RX_DCOC_RANGE_970___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_970__RX_DCOC_RES_I_970___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_970__RX_DCOC_RES_Q_970___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_970__RX_DCOC_RANGE_970___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_970__RX_DCOC_RANGE_970___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_970__RX_DCOC_RES_I_970___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_970__RX_DCOC_RES_I_970___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_970__RX_DCOC_RES_Q_970___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_970__RX_DCOC_RES_Q_970___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_970___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_970___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_971 (0x005F4F2C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_971___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_971___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_971__RX_DCOC_RANGE_971___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_971__RX_DCOC_RES_I_971___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_971__RX_DCOC_RES_Q_971___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_971__RX_DCOC_RANGE_971___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_971__RX_DCOC_RANGE_971___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_971__RX_DCOC_RES_I_971___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_971__RX_DCOC_RES_I_971___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_971__RX_DCOC_RES_Q_971___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_971__RX_DCOC_RES_Q_971___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_971___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_971___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_972 (0x005F4F30) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_972___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_972___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_972__RX_DCOC_RANGE_972___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_972__RX_DCOC_RES_I_972___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_972__RX_DCOC_RES_Q_972___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_972__RX_DCOC_RANGE_972___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_972__RX_DCOC_RANGE_972___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_972__RX_DCOC_RES_I_972___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_972__RX_DCOC_RES_I_972___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_972__RX_DCOC_RES_Q_972___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_972__RX_DCOC_RES_Q_972___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_972___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_972___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_973 (0x005F4F34) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_973___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_973___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_973__RX_DCOC_RANGE_973___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_973__RX_DCOC_RES_I_973___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_973__RX_DCOC_RES_Q_973___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_973__RX_DCOC_RANGE_973___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_973__RX_DCOC_RANGE_973___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_973__RX_DCOC_RES_I_973___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_973__RX_DCOC_RES_I_973___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_973__RX_DCOC_RES_Q_973___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_973__RX_DCOC_RES_Q_973___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_973___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_973___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_974 (0x005F4F38) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_974___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_974___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_974__RX_DCOC_RANGE_974___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_974__RX_DCOC_RES_I_974___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_974__RX_DCOC_RES_Q_974___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_974__RX_DCOC_RANGE_974___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_974__RX_DCOC_RANGE_974___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_974__RX_DCOC_RES_I_974___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_974__RX_DCOC_RES_I_974___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_974__RX_DCOC_RES_Q_974___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_974__RX_DCOC_RES_Q_974___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_974___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_974___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_975 (0x005F4F3C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_975___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_975___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_975__RX_DCOC_RANGE_975___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_975__RX_DCOC_RES_I_975___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_975__RX_DCOC_RES_Q_975___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_975__RX_DCOC_RANGE_975___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_975__RX_DCOC_RANGE_975___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_975__RX_DCOC_RES_I_975___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_975__RX_DCOC_RES_I_975___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_975__RX_DCOC_RES_Q_975___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_975__RX_DCOC_RES_Q_975___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_975___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_975___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_976 (0x005F4F40) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_976___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_976___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_976__RX_DCOC_RANGE_976___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_976__RX_DCOC_RES_I_976___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_976__RX_DCOC_RES_Q_976___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_976__RX_DCOC_RANGE_976___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_976__RX_DCOC_RANGE_976___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_976__RX_DCOC_RES_I_976___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_976__RX_DCOC_RES_I_976___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_976__RX_DCOC_RES_Q_976___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_976__RX_DCOC_RES_Q_976___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_976___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_976___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_977 (0x005F4F44) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_977___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_977___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_977__RX_DCOC_RANGE_977___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_977__RX_DCOC_RES_I_977___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_977__RX_DCOC_RES_Q_977___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_977__RX_DCOC_RANGE_977___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_977__RX_DCOC_RANGE_977___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_977__RX_DCOC_RES_I_977___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_977__RX_DCOC_RES_I_977___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_977__RX_DCOC_RES_Q_977___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_977__RX_DCOC_RES_Q_977___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_977___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_977___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_978 (0x005F4F48) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_978___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_978___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_978__RX_DCOC_RANGE_978___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_978__RX_DCOC_RES_I_978___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_978__RX_DCOC_RES_Q_978___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_978__RX_DCOC_RANGE_978___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_978__RX_DCOC_RANGE_978___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_978__RX_DCOC_RES_I_978___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_978__RX_DCOC_RES_I_978___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_978__RX_DCOC_RES_Q_978___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_978__RX_DCOC_RES_Q_978___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_978___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_978___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_979 (0x005F4F4C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_979___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_979___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_979__RX_DCOC_RANGE_979___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_979__RX_DCOC_RES_I_979___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_979__RX_DCOC_RES_Q_979___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_979__RX_DCOC_RANGE_979___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_979__RX_DCOC_RANGE_979___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_979__RX_DCOC_RES_I_979___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_979__RX_DCOC_RES_I_979___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_979__RX_DCOC_RES_Q_979___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_979__RX_DCOC_RES_Q_979___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_979___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_979___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_980 (0x005F4F50) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_980___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_980___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_980__RX_DCOC_RANGE_980___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_980__RX_DCOC_RES_I_980___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_980__RX_DCOC_RES_Q_980___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_980__RX_DCOC_RANGE_980___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_980__RX_DCOC_RANGE_980___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_980__RX_DCOC_RES_I_980___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_980__RX_DCOC_RES_I_980___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_980__RX_DCOC_RES_Q_980___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_980__RX_DCOC_RES_Q_980___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_980___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_980___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_981 (0x005F4F54) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_981___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_981___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_981__RX_DCOC_RANGE_981___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_981__RX_DCOC_RES_I_981___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_981__RX_DCOC_RES_Q_981___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_981__RX_DCOC_RANGE_981___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_981__RX_DCOC_RANGE_981___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_981__RX_DCOC_RES_I_981___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_981__RX_DCOC_RES_I_981___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_981__RX_DCOC_RES_Q_981___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_981__RX_DCOC_RES_Q_981___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_981___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_981___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_982 (0x005F4F58) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_982___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_982___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_982__RX_DCOC_RANGE_982___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_982__RX_DCOC_RES_I_982___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_982__RX_DCOC_RES_Q_982___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_982__RX_DCOC_RANGE_982___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_982__RX_DCOC_RANGE_982___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_982__RX_DCOC_RES_I_982___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_982__RX_DCOC_RES_I_982___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_982__RX_DCOC_RES_Q_982___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_982__RX_DCOC_RES_Q_982___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_982___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_982___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_983 (0x005F4F5C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_983___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_983___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_983__RX_DCOC_RANGE_983___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_983__RX_DCOC_RES_I_983___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_983__RX_DCOC_RES_Q_983___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_983__RX_DCOC_RANGE_983___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_983__RX_DCOC_RANGE_983___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_983__RX_DCOC_RES_I_983___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_983__RX_DCOC_RES_I_983___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_983__RX_DCOC_RES_Q_983___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_983__RX_DCOC_RES_Q_983___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_983___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_983___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_984 (0x005F4F60) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_984___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_984___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_984__RX_DCOC_RANGE_984___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_984__RX_DCOC_RES_I_984___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_984__RX_DCOC_RES_Q_984___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_984__RX_DCOC_RANGE_984___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_984__RX_DCOC_RANGE_984___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_984__RX_DCOC_RES_I_984___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_984__RX_DCOC_RES_I_984___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_984__RX_DCOC_RES_Q_984___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_984__RX_DCOC_RES_Q_984___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_984___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_984___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_985 (0x005F4F64) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_985___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_985___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_985__RX_DCOC_RANGE_985___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_985__RX_DCOC_RES_I_985___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_985__RX_DCOC_RES_Q_985___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_985__RX_DCOC_RANGE_985___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_985__RX_DCOC_RANGE_985___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_985__RX_DCOC_RES_I_985___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_985__RX_DCOC_RES_I_985___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_985__RX_DCOC_RES_Q_985___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_985__RX_DCOC_RES_Q_985___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_985___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_985___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_986 (0x005F4F68) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_986___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_986___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_986__RX_DCOC_RANGE_986___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_986__RX_DCOC_RES_I_986___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_986__RX_DCOC_RES_Q_986___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_986__RX_DCOC_RANGE_986___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_986__RX_DCOC_RANGE_986___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_986__RX_DCOC_RES_I_986___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_986__RX_DCOC_RES_I_986___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_986__RX_DCOC_RES_Q_986___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_986__RX_DCOC_RES_Q_986___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_986___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_986___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_987 (0x005F4F6C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_987___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_987___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_987__RX_DCOC_RANGE_987___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_987__RX_DCOC_RES_I_987___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_987__RX_DCOC_RES_Q_987___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_987__RX_DCOC_RANGE_987___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_987__RX_DCOC_RANGE_987___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_987__RX_DCOC_RES_I_987___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_987__RX_DCOC_RES_I_987___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_987__RX_DCOC_RES_Q_987___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_987__RX_DCOC_RES_Q_987___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_987___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_987___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_988 (0x005F4F70) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_988___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_988___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_988__RX_DCOC_RANGE_988___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_988__RX_DCOC_RES_I_988___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_988__RX_DCOC_RES_Q_988___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_988__RX_DCOC_RANGE_988___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_988__RX_DCOC_RANGE_988___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_988__RX_DCOC_RES_I_988___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_988__RX_DCOC_RES_I_988___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_988__RX_DCOC_RES_Q_988___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_988__RX_DCOC_RES_Q_988___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_988___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_988___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_989 (0x005F4F74) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_989___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_989___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_989__RX_DCOC_RANGE_989___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_989__RX_DCOC_RES_I_989___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_989__RX_DCOC_RES_Q_989___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_989__RX_DCOC_RANGE_989___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_989__RX_DCOC_RANGE_989___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_989__RX_DCOC_RES_I_989___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_989__RX_DCOC_RES_I_989___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_989__RX_DCOC_RES_Q_989___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_989__RX_DCOC_RES_Q_989___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_989___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_989___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_990 (0x005F4F78) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_990___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_990___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_990__RX_DCOC_RANGE_990___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_990__RX_DCOC_RES_I_990___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_990__RX_DCOC_RES_Q_990___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_990__RX_DCOC_RANGE_990___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_990__RX_DCOC_RANGE_990___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_990__RX_DCOC_RES_I_990___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_990__RX_DCOC_RES_I_990___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_990__RX_DCOC_RES_Q_990___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_990__RX_DCOC_RES_Q_990___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_990___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_990___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_991 (0x005F4F7C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_991___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_991___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_991__RX_DCOC_RANGE_991___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_991__RX_DCOC_RES_I_991___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_991__RX_DCOC_RES_Q_991___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_991__RX_DCOC_RANGE_991___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_991__RX_DCOC_RANGE_991___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_991__RX_DCOC_RES_I_991___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_991__RX_DCOC_RES_I_991___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_991__RX_DCOC_RES_Q_991___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_991__RX_DCOC_RES_Q_991___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_991___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_991___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_992 (0x005F4F80) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_992___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_992___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_992__RX_DCOC_RANGE_992___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_992__RX_DCOC_RES_I_992___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_992__RX_DCOC_RES_Q_992___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_992__RX_DCOC_RANGE_992___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_992__RX_DCOC_RANGE_992___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_992__RX_DCOC_RES_I_992___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_992__RX_DCOC_RES_I_992___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_992__RX_DCOC_RES_Q_992___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_992__RX_DCOC_RES_Q_992___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_992___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_992___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_993 (0x005F4F84) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_993___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_993___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_993__RX_DCOC_RANGE_993___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_993__RX_DCOC_RES_I_993___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_993__RX_DCOC_RES_Q_993___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_993__RX_DCOC_RANGE_993___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_993__RX_DCOC_RANGE_993___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_993__RX_DCOC_RES_I_993___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_993__RX_DCOC_RES_I_993___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_993__RX_DCOC_RES_Q_993___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_993__RX_DCOC_RES_Q_993___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_993___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_993___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_994 (0x005F4F88) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_994___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_994___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_994__RX_DCOC_RANGE_994___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_994__RX_DCOC_RES_I_994___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_994__RX_DCOC_RES_Q_994___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_994__RX_DCOC_RANGE_994___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_994__RX_DCOC_RANGE_994___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_994__RX_DCOC_RES_I_994___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_994__RX_DCOC_RES_I_994___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_994__RX_DCOC_RES_Q_994___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_994__RX_DCOC_RES_Q_994___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_994___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_994___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_995 (0x005F4F8C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_995___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_995___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_995__RX_DCOC_RANGE_995___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_995__RX_DCOC_RES_I_995___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_995__RX_DCOC_RES_Q_995___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_995__RX_DCOC_RANGE_995___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_995__RX_DCOC_RANGE_995___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_995__RX_DCOC_RES_I_995___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_995__RX_DCOC_RES_I_995___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_995__RX_DCOC_RES_Q_995___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_995__RX_DCOC_RES_Q_995___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_995___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_995___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_996 (0x005F4F90) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_996___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_996___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_996__RX_DCOC_RANGE_996___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_996__RX_DCOC_RES_I_996___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_996__RX_DCOC_RES_Q_996___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_996__RX_DCOC_RANGE_996___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_996__RX_DCOC_RANGE_996___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_996__RX_DCOC_RES_I_996___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_996__RX_DCOC_RES_I_996___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_996__RX_DCOC_RES_Q_996___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_996__RX_DCOC_RES_Q_996___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_996___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_996___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_997 (0x005F4F94) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_997___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_997___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_997__RX_DCOC_RANGE_997___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_997__RX_DCOC_RES_I_997___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_997__RX_DCOC_RES_Q_997___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_997__RX_DCOC_RANGE_997___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_997__RX_DCOC_RANGE_997___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_997__RX_DCOC_RES_I_997___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_997__RX_DCOC_RES_I_997___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_997__RX_DCOC_RES_Q_997___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_997__RX_DCOC_RES_Q_997___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_997___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_997___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_998 (0x005F4F98) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_998___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_998___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_998__RX_DCOC_RANGE_998___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_998__RX_DCOC_RES_I_998___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_998__RX_DCOC_RES_Q_998___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_998__RX_DCOC_RANGE_998___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_998__RX_DCOC_RANGE_998___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_998__RX_DCOC_RES_I_998___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_998__RX_DCOC_RES_I_998___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_998__RX_DCOC_RES_Q_998___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_998__RX_DCOC_RES_Q_998___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_998___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_998___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_999 (0x005F4F9C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_999___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_999___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_999__RX_DCOC_RANGE_999___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_999__RX_DCOC_RES_I_999___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_999__RX_DCOC_RES_Q_999___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_999__RX_DCOC_RANGE_999___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_999__RX_DCOC_RANGE_999___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_999__RX_DCOC_RES_I_999___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_999__RX_DCOC_RES_I_999___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_999__RX_DCOC_RES_Q_999___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_999__RX_DCOC_RES_Q_999___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_999___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_999___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1000 (0x005F4FA0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1000___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1000___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1000__RX_DCOC_RANGE_1000___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1000__RX_DCOC_RES_I_1000___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1000__RX_DCOC_RES_Q_1000___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1000__RX_DCOC_RANGE_1000___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1000__RX_DCOC_RANGE_1000___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1000__RX_DCOC_RES_I_1000___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1000__RX_DCOC_RES_I_1000___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1000__RX_DCOC_RES_Q_1000___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1000__RX_DCOC_RES_Q_1000___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1000___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1000___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1001 (0x005F4FA4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1001___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1001___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1001__RX_DCOC_RANGE_1001___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1001__RX_DCOC_RES_I_1001___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1001__RX_DCOC_RES_Q_1001___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1001__RX_DCOC_RANGE_1001___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1001__RX_DCOC_RANGE_1001___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1001__RX_DCOC_RES_I_1001___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1001__RX_DCOC_RES_I_1001___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1001__RX_DCOC_RES_Q_1001___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1001__RX_DCOC_RES_Q_1001___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1001___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1001___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1002 (0x005F4FA8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1002___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1002___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1002__RX_DCOC_RANGE_1002___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1002__RX_DCOC_RES_I_1002___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1002__RX_DCOC_RES_Q_1002___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1002__RX_DCOC_RANGE_1002___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1002__RX_DCOC_RANGE_1002___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1002__RX_DCOC_RES_I_1002___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1002__RX_DCOC_RES_I_1002___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1002__RX_DCOC_RES_Q_1002___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1002__RX_DCOC_RES_Q_1002___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1002___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1002___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1003 (0x005F4FAC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1003___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1003___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1003__RX_DCOC_RANGE_1003___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1003__RX_DCOC_RES_I_1003___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1003__RX_DCOC_RES_Q_1003___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1003__RX_DCOC_RANGE_1003___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1003__RX_DCOC_RANGE_1003___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1003__RX_DCOC_RES_I_1003___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1003__RX_DCOC_RES_I_1003___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1003__RX_DCOC_RES_Q_1003___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1003__RX_DCOC_RES_Q_1003___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1003___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1003___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1004 (0x005F4FB0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1004___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1004___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1004__RX_DCOC_RANGE_1004___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1004__RX_DCOC_RES_I_1004___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1004__RX_DCOC_RES_Q_1004___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1004__RX_DCOC_RANGE_1004___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1004__RX_DCOC_RANGE_1004___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1004__RX_DCOC_RES_I_1004___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1004__RX_DCOC_RES_I_1004___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1004__RX_DCOC_RES_Q_1004___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1004__RX_DCOC_RES_Q_1004___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1004___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1004___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1005 (0x005F4FB4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1005___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1005___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1005__RX_DCOC_RANGE_1005___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1005__RX_DCOC_RES_I_1005___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1005__RX_DCOC_RES_Q_1005___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1005__RX_DCOC_RANGE_1005___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1005__RX_DCOC_RANGE_1005___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1005__RX_DCOC_RES_I_1005___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1005__RX_DCOC_RES_I_1005___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1005__RX_DCOC_RES_Q_1005___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1005__RX_DCOC_RES_Q_1005___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1005___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1005___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1006 (0x005F4FB8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1006___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1006___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1006__RX_DCOC_RANGE_1006___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1006__RX_DCOC_RES_I_1006___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1006__RX_DCOC_RES_Q_1006___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1006__RX_DCOC_RANGE_1006___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1006__RX_DCOC_RANGE_1006___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1006__RX_DCOC_RES_I_1006___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1006__RX_DCOC_RES_I_1006___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1006__RX_DCOC_RES_Q_1006___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1006__RX_DCOC_RES_Q_1006___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1006___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1006___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1007 (0x005F4FBC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1007___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1007___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1007__RX_DCOC_RANGE_1007___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1007__RX_DCOC_RES_I_1007___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1007__RX_DCOC_RES_Q_1007___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1007__RX_DCOC_RANGE_1007___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1007__RX_DCOC_RANGE_1007___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1007__RX_DCOC_RES_I_1007___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1007__RX_DCOC_RES_I_1007___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1007__RX_DCOC_RES_Q_1007___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1007__RX_DCOC_RES_Q_1007___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1007___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1007___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1008 (0x005F4FC0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1008___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1008___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1008__RX_DCOC_RANGE_1008___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1008__RX_DCOC_RES_I_1008___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1008__RX_DCOC_RES_Q_1008___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1008__RX_DCOC_RANGE_1008___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1008__RX_DCOC_RANGE_1008___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1008__RX_DCOC_RES_I_1008___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1008__RX_DCOC_RES_I_1008___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1008__RX_DCOC_RES_Q_1008___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1008__RX_DCOC_RES_Q_1008___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1008___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1008___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1009 (0x005F4FC4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1009___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1009___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1009__RX_DCOC_RANGE_1009___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1009__RX_DCOC_RES_I_1009___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1009__RX_DCOC_RES_Q_1009___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1009__RX_DCOC_RANGE_1009___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1009__RX_DCOC_RANGE_1009___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1009__RX_DCOC_RES_I_1009___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1009__RX_DCOC_RES_I_1009___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1009__RX_DCOC_RES_Q_1009___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1009__RX_DCOC_RES_Q_1009___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1009___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1009___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1010 (0x005F4FC8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1010___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1010___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1010__RX_DCOC_RANGE_1010___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1010__RX_DCOC_RES_I_1010___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1010__RX_DCOC_RES_Q_1010___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1010__RX_DCOC_RANGE_1010___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1010__RX_DCOC_RANGE_1010___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1010__RX_DCOC_RES_I_1010___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1010__RX_DCOC_RES_I_1010___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1010__RX_DCOC_RES_Q_1010___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1010__RX_DCOC_RES_Q_1010___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1010___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1010___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1011 (0x005F4FCC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1011___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1011___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1011__RX_DCOC_RANGE_1011___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1011__RX_DCOC_RES_I_1011___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1011__RX_DCOC_RES_Q_1011___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1011__RX_DCOC_RANGE_1011___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1011__RX_DCOC_RANGE_1011___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1011__RX_DCOC_RES_I_1011___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1011__RX_DCOC_RES_I_1011___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1011__RX_DCOC_RES_Q_1011___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1011__RX_DCOC_RES_Q_1011___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1011___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1011___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1012 (0x005F4FD0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1012___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1012___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1012__RX_DCOC_RANGE_1012___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1012__RX_DCOC_RES_I_1012___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1012__RX_DCOC_RES_Q_1012___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1012__RX_DCOC_RANGE_1012___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1012__RX_DCOC_RANGE_1012___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1012__RX_DCOC_RES_I_1012___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1012__RX_DCOC_RES_I_1012___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1012__RX_DCOC_RES_Q_1012___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1012__RX_DCOC_RES_Q_1012___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1012___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1012___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1013 (0x005F4FD4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1013___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1013___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1013__RX_DCOC_RANGE_1013___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1013__RX_DCOC_RES_I_1013___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1013__RX_DCOC_RES_Q_1013___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1013__RX_DCOC_RANGE_1013___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1013__RX_DCOC_RANGE_1013___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1013__RX_DCOC_RES_I_1013___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1013__RX_DCOC_RES_I_1013___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1013__RX_DCOC_RES_Q_1013___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1013__RX_DCOC_RES_Q_1013___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1013___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1013___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1014 (0x005F4FD8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1014___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1014___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1014__RX_DCOC_RANGE_1014___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1014__RX_DCOC_RES_I_1014___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1014__RX_DCOC_RES_Q_1014___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1014__RX_DCOC_RANGE_1014___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1014__RX_DCOC_RANGE_1014___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1014__RX_DCOC_RES_I_1014___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1014__RX_DCOC_RES_I_1014___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1014__RX_DCOC_RES_Q_1014___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1014__RX_DCOC_RES_Q_1014___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1014___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1014___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1015 (0x005F4FDC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1015___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1015___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1015__RX_DCOC_RANGE_1015___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1015__RX_DCOC_RES_I_1015___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1015__RX_DCOC_RES_Q_1015___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1015__RX_DCOC_RANGE_1015___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1015__RX_DCOC_RANGE_1015___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1015__RX_DCOC_RES_I_1015___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1015__RX_DCOC_RES_I_1015___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1015__RX_DCOC_RES_Q_1015___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1015__RX_DCOC_RES_Q_1015___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1015___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1015___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1016 (0x005F4FE0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1016___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1016___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1016__RX_DCOC_RANGE_1016___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1016__RX_DCOC_RES_I_1016___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1016__RX_DCOC_RES_Q_1016___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1016__RX_DCOC_RANGE_1016___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1016__RX_DCOC_RANGE_1016___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1016__RX_DCOC_RES_I_1016___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1016__RX_DCOC_RES_I_1016___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1016__RX_DCOC_RES_Q_1016___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1016__RX_DCOC_RES_Q_1016___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1016___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1016___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1017 (0x005F4FE4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1017___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1017___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1017__RX_DCOC_RANGE_1017___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1017__RX_DCOC_RES_I_1017___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1017__RX_DCOC_RES_Q_1017___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1017__RX_DCOC_RANGE_1017___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1017__RX_DCOC_RANGE_1017___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1017__RX_DCOC_RES_I_1017___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1017__RX_DCOC_RES_I_1017___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1017__RX_DCOC_RES_Q_1017___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1017__RX_DCOC_RES_Q_1017___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1017___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1017___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1018 (0x005F4FE8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1018___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1018___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1018__RX_DCOC_RANGE_1018___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1018__RX_DCOC_RES_I_1018___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1018__RX_DCOC_RES_Q_1018___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1018__RX_DCOC_RANGE_1018___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1018__RX_DCOC_RANGE_1018___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1018__RX_DCOC_RES_I_1018___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1018__RX_DCOC_RES_I_1018___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1018__RX_DCOC_RES_Q_1018___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1018__RX_DCOC_RES_Q_1018___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1018___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1018___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1019 (0x005F4FEC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1019___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1019___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1019__RX_DCOC_RANGE_1019___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1019__RX_DCOC_RES_I_1019___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1019__RX_DCOC_RES_Q_1019___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1019__RX_DCOC_RANGE_1019___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1019__RX_DCOC_RANGE_1019___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1019__RX_DCOC_RES_I_1019___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1019__RX_DCOC_RES_I_1019___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1019__RX_DCOC_RES_Q_1019___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1019__RX_DCOC_RES_Q_1019___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1019___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1019___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1020 (0x005F4FF0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1020___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1020___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1020__RX_DCOC_RANGE_1020___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1020__RX_DCOC_RES_I_1020___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1020__RX_DCOC_RES_Q_1020___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1020__RX_DCOC_RANGE_1020___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1020__RX_DCOC_RANGE_1020___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1020__RX_DCOC_RES_I_1020___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1020__RX_DCOC_RES_I_1020___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1020__RX_DCOC_RES_Q_1020___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1020__RX_DCOC_RES_Q_1020___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1020___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1020___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1021 (0x005F4FF4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1021___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1021___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1021__RX_DCOC_RANGE_1021___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1021__RX_DCOC_RES_I_1021___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1021__RX_DCOC_RES_Q_1021___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1021__RX_DCOC_RANGE_1021___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1021__RX_DCOC_RANGE_1021___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1021__RX_DCOC_RES_I_1021___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1021__RX_DCOC_RES_I_1021___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1021__RX_DCOC_RES_Q_1021___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1021__RX_DCOC_RES_Q_1021___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1021___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1021___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1022 (0x005F4FF8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1022___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1022___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1022__RX_DCOC_RANGE_1022___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1022__RX_DCOC_RES_I_1022___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1022__RX_DCOC_RES_Q_1022___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1022__RX_DCOC_RANGE_1022___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1022__RX_DCOC_RANGE_1022___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1022__RX_DCOC_RES_I_1022___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1022__RX_DCOC_RES_I_1022___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1022__RX_DCOC_RES_Q_1022___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1022__RX_DCOC_RES_Q_1022___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1022___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1022___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1023 (0x005F4FFC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1023___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1023___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1023__RX_DCOC_RANGE_1023___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1023__RX_DCOC_RES_I_1023___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1023__RX_DCOC_RES_Q_1023___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1023__RX_DCOC_RANGE_1023___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1023__RX_DCOC_RANGE_1023___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1023__RX_DCOC_RES_I_1023___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1023__RX_DCOC_RES_I_1023___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1023__RX_DCOC_RES_Q_1023___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1023__RX_DCOC_RES_Q_1023___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1023___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXDCOC_1023___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0 (0x005F5000) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__XLNA_GAIN_ODD_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__LNA_GAIN_ODD_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__GM_GAIN_ODD_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__TIA_GAIN_ODD_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__SLM_XLNA_ODD_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__BQ_GAIN_ODD_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__XLNA_GAIN_EVEN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__LNA_GAIN_EVEN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__GM_GAIN_EVEN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__TIA_GAIN_EVEN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__SLM_XLNA_EVEN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__BQ_GAIN_EVEN_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__XLNA_GAIN_ODD_0___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__XLNA_GAIN_ODD_0___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__LNA_GAIN_ODD_0___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__LNA_GAIN_ODD_0___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__GM_GAIN_ODD_0___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__GM_GAIN_ODD_0___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__TIA_GAIN_ODD_0___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__TIA_GAIN_ODD_0___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__SLM_XLNA_ODD_0___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__SLM_XLNA_ODD_0___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__BQ_GAIN_ODD_0___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__BQ_GAIN_ODD_0___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__XLNA_GAIN_EVEN_0___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__XLNA_GAIN_EVEN_0___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__LNA_GAIN_EVEN_0___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__LNA_GAIN_EVEN_0___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__GM_GAIN_EVEN_0___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__GM_GAIN_EVEN_0___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__TIA_GAIN_EVEN_0___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__TIA_GAIN_EVEN_0___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__SLM_XLNA_EVEN_0___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__SLM_XLNA_EVEN_0___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__BQ_GAIN_EVEN_0___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0__BQ_GAIN_EVEN_0___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1 (0x005F5004) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__XLNA_GAIN_ODD_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__LNA_GAIN_ODD_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__GM_GAIN_ODD_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__TIA_GAIN_ODD_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__SLM_XLNA_ODD_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__BQ_GAIN_ODD_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__XLNA_GAIN_EVEN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__LNA_GAIN_EVEN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__GM_GAIN_EVEN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__TIA_GAIN_EVEN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__SLM_XLNA_EVEN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__BQ_GAIN_EVEN_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__XLNA_GAIN_ODD_1___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__XLNA_GAIN_ODD_1___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__LNA_GAIN_ODD_1___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__LNA_GAIN_ODD_1___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__GM_GAIN_ODD_1___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__GM_GAIN_ODD_1___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__TIA_GAIN_ODD_1___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__TIA_GAIN_ODD_1___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__SLM_XLNA_ODD_1___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__SLM_XLNA_ODD_1___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__BQ_GAIN_ODD_1___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__BQ_GAIN_ODD_1___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__XLNA_GAIN_EVEN_1___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__XLNA_GAIN_EVEN_1___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__LNA_GAIN_EVEN_1___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__LNA_GAIN_EVEN_1___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__GM_GAIN_EVEN_1___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__GM_GAIN_EVEN_1___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__TIA_GAIN_EVEN_1___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__TIA_GAIN_EVEN_1___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__SLM_XLNA_EVEN_1___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__SLM_XLNA_EVEN_1___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__BQ_GAIN_EVEN_1___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1__BQ_GAIN_EVEN_1___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2 (0x005F5008) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__XLNA_GAIN_ODD_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__LNA_GAIN_ODD_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__GM_GAIN_ODD_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__TIA_GAIN_ODD_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__SLM_XLNA_ODD_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__BQ_GAIN_ODD_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__XLNA_GAIN_EVEN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__LNA_GAIN_EVEN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__GM_GAIN_EVEN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__TIA_GAIN_EVEN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__SLM_XLNA_EVEN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__BQ_GAIN_EVEN_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__XLNA_GAIN_ODD_2___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__XLNA_GAIN_ODD_2___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__LNA_GAIN_ODD_2___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__LNA_GAIN_ODD_2___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__GM_GAIN_ODD_2___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__GM_GAIN_ODD_2___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__TIA_GAIN_ODD_2___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__TIA_GAIN_ODD_2___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__SLM_XLNA_ODD_2___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__SLM_XLNA_ODD_2___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__BQ_GAIN_ODD_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__BQ_GAIN_ODD_2___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__XLNA_GAIN_EVEN_2___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__XLNA_GAIN_EVEN_2___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__LNA_GAIN_EVEN_2___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__LNA_GAIN_EVEN_2___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__GM_GAIN_EVEN_2___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__GM_GAIN_EVEN_2___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__TIA_GAIN_EVEN_2___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__TIA_GAIN_EVEN_2___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__SLM_XLNA_EVEN_2___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__SLM_XLNA_EVEN_2___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__BQ_GAIN_EVEN_2___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2__BQ_GAIN_EVEN_2___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_2___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3 (0x005F500C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__XLNA_GAIN_ODD_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__LNA_GAIN_ODD_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__GM_GAIN_ODD_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__TIA_GAIN_ODD_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__SLM_XLNA_ODD_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__BQ_GAIN_ODD_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__XLNA_GAIN_EVEN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__LNA_GAIN_EVEN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__GM_GAIN_EVEN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__TIA_GAIN_EVEN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__SLM_XLNA_EVEN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__BQ_GAIN_EVEN_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__XLNA_GAIN_ODD_3___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__XLNA_GAIN_ODD_3___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__LNA_GAIN_ODD_3___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__LNA_GAIN_ODD_3___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__GM_GAIN_ODD_3___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__GM_GAIN_ODD_3___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__TIA_GAIN_ODD_3___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__TIA_GAIN_ODD_3___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__SLM_XLNA_ODD_3___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__SLM_XLNA_ODD_3___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__BQ_GAIN_ODD_3___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__BQ_GAIN_ODD_3___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__XLNA_GAIN_EVEN_3___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__XLNA_GAIN_EVEN_3___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__LNA_GAIN_EVEN_3___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__LNA_GAIN_EVEN_3___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__GM_GAIN_EVEN_3___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__GM_GAIN_EVEN_3___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__TIA_GAIN_EVEN_3___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__TIA_GAIN_EVEN_3___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__SLM_XLNA_EVEN_3___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__SLM_XLNA_EVEN_3___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__BQ_GAIN_EVEN_3___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3__BQ_GAIN_EVEN_3___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_3___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4 (0x005F5010) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__XLNA_GAIN_ODD_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__LNA_GAIN_ODD_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__GM_GAIN_ODD_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__TIA_GAIN_ODD_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__SLM_XLNA_ODD_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__BQ_GAIN_ODD_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__XLNA_GAIN_EVEN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__LNA_GAIN_EVEN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__GM_GAIN_EVEN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__TIA_GAIN_EVEN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__SLM_XLNA_EVEN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__BQ_GAIN_EVEN_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__XLNA_GAIN_ODD_4___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__XLNA_GAIN_ODD_4___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__LNA_GAIN_ODD_4___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__LNA_GAIN_ODD_4___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__GM_GAIN_ODD_4___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__GM_GAIN_ODD_4___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__TIA_GAIN_ODD_4___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__TIA_GAIN_ODD_4___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__SLM_XLNA_ODD_4___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__SLM_XLNA_ODD_4___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__BQ_GAIN_ODD_4___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__BQ_GAIN_ODD_4___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__XLNA_GAIN_EVEN_4___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__XLNA_GAIN_EVEN_4___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__LNA_GAIN_EVEN_4___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__LNA_GAIN_EVEN_4___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__GM_GAIN_EVEN_4___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__GM_GAIN_EVEN_4___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__TIA_GAIN_EVEN_4___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__TIA_GAIN_EVEN_4___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__SLM_XLNA_EVEN_4___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__SLM_XLNA_EVEN_4___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__BQ_GAIN_EVEN_4___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4__BQ_GAIN_EVEN_4___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_4___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5 (0x005F5014) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__XLNA_GAIN_ODD_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__LNA_GAIN_ODD_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__GM_GAIN_ODD_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__TIA_GAIN_ODD_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__SLM_XLNA_ODD_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__BQ_GAIN_ODD_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__XLNA_GAIN_EVEN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__LNA_GAIN_EVEN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__GM_GAIN_EVEN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__TIA_GAIN_EVEN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__SLM_XLNA_EVEN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__BQ_GAIN_EVEN_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__XLNA_GAIN_ODD_5___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__XLNA_GAIN_ODD_5___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__LNA_GAIN_ODD_5___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__LNA_GAIN_ODD_5___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__GM_GAIN_ODD_5___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__GM_GAIN_ODD_5___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__TIA_GAIN_ODD_5___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__TIA_GAIN_ODD_5___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__SLM_XLNA_ODD_5___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__SLM_XLNA_ODD_5___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__BQ_GAIN_ODD_5___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__BQ_GAIN_ODD_5___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__XLNA_GAIN_EVEN_5___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__XLNA_GAIN_EVEN_5___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__LNA_GAIN_EVEN_5___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__LNA_GAIN_EVEN_5___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__GM_GAIN_EVEN_5___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__GM_GAIN_EVEN_5___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__TIA_GAIN_EVEN_5___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__TIA_GAIN_EVEN_5___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__SLM_XLNA_EVEN_5___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__SLM_XLNA_EVEN_5___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__BQ_GAIN_EVEN_5___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5__BQ_GAIN_EVEN_5___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_5___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6 (0x005F5018) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__XLNA_GAIN_ODD_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__LNA_GAIN_ODD_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__GM_GAIN_ODD_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__TIA_GAIN_ODD_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__SLM_XLNA_ODD_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__BQ_GAIN_ODD_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__XLNA_GAIN_EVEN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__LNA_GAIN_EVEN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__GM_GAIN_EVEN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__TIA_GAIN_EVEN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__SLM_XLNA_EVEN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__BQ_GAIN_EVEN_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__XLNA_GAIN_ODD_6___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__XLNA_GAIN_ODD_6___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__LNA_GAIN_ODD_6___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__LNA_GAIN_ODD_6___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__GM_GAIN_ODD_6___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__GM_GAIN_ODD_6___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__TIA_GAIN_ODD_6___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__TIA_GAIN_ODD_6___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__SLM_XLNA_ODD_6___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__SLM_XLNA_ODD_6___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__BQ_GAIN_ODD_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__BQ_GAIN_ODD_6___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__XLNA_GAIN_EVEN_6___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__XLNA_GAIN_EVEN_6___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__LNA_GAIN_EVEN_6___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__LNA_GAIN_EVEN_6___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__GM_GAIN_EVEN_6___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__GM_GAIN_EVEN_6___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__TIA_GAIN_EVEN_6___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__TIA_GAIN_EVEN_6___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__SLM_XLNA_EVEN_6___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__SLM_XLNA_EVEN_6___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__BQ_GAIN_EVEN_6___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6__BQ_GAIN_EVEN_6___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_6___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7 (0x005F501C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__XLNA_GAIN_ODD_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__LNA_GAIN_ODD_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__GM_GAIN_ODD_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__TIA_GAIN_ODD_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__SLM_XLNA_ODD_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__BQ_GAIN_ODD_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__XLNA_GAIN_EVEN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__LNA_GAIN_EVEN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__GM_GAIN_EVEN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__TIA_GAIN_EVEN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__SLM_XLNA_EVEN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__BQ_GAIN_EVEN_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__XLNA_GAIN_ODD_7___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__XLNA_GAIN_ODD_7___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__LNA_GAIN_ODD_7___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__LNA_GAIN_ODD_7___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__GM_GAIN_ODD_7___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__GM_GAIN_ODD_7___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__TIA_GAIN_ODD_7___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__TIA_GAIN_ODD_7___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__SLM_XLNA_ODD_7___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__SLM_XLNA_ODD_7___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__BQ_GAIN_ODD_7___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__BQ_GAIN_ODD_7___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__XLNA_GAIN_EVEN_7___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__XLNA_GAIN_EVEN_7___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__LNA_GAIN_EVEN_7___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__LNA_GAIN_EVEN_7___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__GM_GAIN_EVEN_7___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__GM_GAIN_EVEN_7___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__TIA_GAIN_EVEN_7___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__TIA_GAIN_EVEN_7___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__SLM_XLNA_EVEN_7___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__SLM_XLNA_EVEN_7___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__BQ_GAIN_EVEN_7___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7__BQ_GAIN_EVEN_7___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_7___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8 (0x005F5020) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__XLNA_GAIN_ODD_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__LNA_GAIN_ODD_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__GM_GAIN_ODD_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__TIA_GAIN_ODD_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__SLM_XLNA_ODD_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__BQ_GAIN_ODD_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__XLNA_GAIN_EVEN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__LNA_GAIN_EVEN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__GM_GAIN_EVEN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__TIA_GAIN_EVEN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__SLM_XLNA_EVEN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__BQ_GAIN_EVEN_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__XLNA_GAIN_ODD_8___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__XLNA_GAIN_ODD_8___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__LNA_GAIN_ODD_8___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__LNA_GAIN_ODD_8___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__GM_GAIN_ODD_8___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__GM_GAIN_ODD_8___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__TIA_GAIN_ODD_8___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__TIA_GAIN_ODD_8___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__SLM_XLNA_ODD_8___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__SLM_XLNA_ODD_8___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__BQ_GAIN_ODD_8___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__BQ_GAIN_ODD_8___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__XLNA_GAIN_EVEN_8___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__XLNA_GAIN_EVEN_8___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__LNA_GAIN_EVEN_8___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__LNA_GAIN_EVEN_8___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__GM_GAIN_EVEN_8___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__GM_GAIN_EVEN_8___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__TIA_GAIN_EVEN_8___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__TIA_GAIN_EVEN_8___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__SLM_XLNA_EVEN_8___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__SLM_XLNA_EVEN_8___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__BQ_GAIN_EVEN_8___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8__BQ_GAIN_EVEN_8___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_8___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9 (0x005F5024) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__XLNA_GAIN_ODD_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__LNA_GAIN_ODD_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__GM_GAIN_ODD_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__TIA_GAIN_ODD_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__SLM_XLNA_ODD_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__BQ_GAIN_ODD_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__XLNA_GAIN_EVEN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__LNA_GAIN_EVEN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__GM_GAIN_EVEN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__TIA_GAIN_EVEN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__SLM_XLNA_EVEN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__BQ_GAIN_EVEN_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__XLNA_GAIN_ODD_9___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__XLNA_GAIN_ODD_9___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__LNA_GAIN_ODD_9___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__LNA_GAIN_ODD_9___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__GM_GAIN_ODD_9___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__GM_GAIN_ODD_9___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__TIA_GAIN_ODD_9___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__TIA_GAIN_ODD_9___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__SLM_XLNA_ODD_9___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__SLM_XLNA_ODD_9___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__BQ_GAIN_ODD_9___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__BQ_GAIN_ODD_9___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__XLNA_GAIN_EVEN_9___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__XLNA_GAIN_EVEN_9___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__LNA_GAIN_EVEN_9___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__LNA_GAIN_EVEN_9___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__GM_GAIN_EVEN_9___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__GM_GAIN_EVEN_9___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__TIA_GAIN_EVEN_9___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__TIA_GAIN_EVEN_9___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__SLM_XLNA_EVEN_9___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__SLM_XLNA_EVEN_9___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__BQ_GAIN_EVEN_9___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9__BQ_GAIN_EVEN_9___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_9___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10 (0x005F5028) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__XLNA_GAIN_ODD_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__LNA_GAIN_ODD_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__GM_GAIN_ODD_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__TIA_GAIN_ODD_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__SLM_XLNA_ODD_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__BQ_GAIN_ODD_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__XLNA_GAIN_EVEN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__LNA_GAIN_EVEN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__GM_GAIN_EVEN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__TIA_GAIN_EVEN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__SLM_XLNA_EVEN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__BQ_GAIN_EVEN_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__XLNA_GAIN_ODD_10___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__XLNA_GAIN_ODD_10___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__LNA_GAIN_ODD_10___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__LNA_GAIN_ODD_10___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__GM_GAIN_ODD_10___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__GM_GAIN_ODD_10___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__TIA_GAIN_ODD_10___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__TIA_GAIN_ODD_10___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__SLM_XLNA_ODD_10___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__SLM_XLNA_ODD_10___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__BQ_GAIN_ODD_10___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__BQ_GAIN_ODD_10___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__XLNA_GAIN_EVEN_10___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__XLNA_GAIN_EVEN_10___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__LNA_GAIN_EVEN_10___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__LNA_GAIN_EVEN_10___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__GM_GAIN_EVEN_10___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__GM_GAIN_EVEN_10___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__TIA_GAIN_EVEN_10___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__TIA_GAIN_EVEN_10___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__SLM_XLNA_EVEN_10___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__SLM_XLNA_EVEN_10___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__BQ_GAIN_EVEN_10___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10__BQ_GAIN_EVEN_10___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_10___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11 (0x005F502C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__XLNA_GAIN_ODD_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__LNA_GAIN_ODD_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__GM_GAIN_ODD_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__TIA_GAIN_ODD_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__SLM_XLNA_ODD_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__BQ_GAIN_ODD_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__XLNA_GAIN_EVEN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__LNA_GAIN_EVEN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__GM_GAIN_EVEN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__TIA_GAIN_EVEN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__SLM_XLNA_EVEN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__BQ_GAIN_EVEN_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__XLNA_GAIN_ODD_11___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__XLNA_GAIN_ODD_11___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__LNA_GAIN_ODD_11___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__LNA_GAIN_ODD_11___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__GM_GAIN_ODD_11___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__GM_GAIN_ODD_11___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__TIA_GAIN_ODD_11___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__TIA_GAIN_ODD_11___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__SLM_XLNA_ODD_11___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__SLM_XLNA_ODD_11___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__BQ_GAIN_ODD_11___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__BQ_GAIN_ODD_11___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__XLNA_GAIN_EVEN_11___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__XLNA_GAIN_EVEN_11___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__LNA_GAIN_EVEN_11___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__LNA_GAIN_EVEN_11___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__GM_GAIN_EVEN_11___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__GM_GAIN_EVEN_11___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__TIA_GAIN_EVEN_11___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__TIA_GAIN_EVEN_11___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__SLM_XLNA_EVEN_11___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__SLM_XLNA_EVEN_11___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__BQ_GAIN_EVEN_11___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11__BQ_GAIN_EVEN_11___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_11___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12 (0x005F5030) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__XLNA_GAIN_ODD_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__LNA_GAIN_ODD_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__GM_GAIN_ODD_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__TIA_GAIN_ODD_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__SLM_XLNA_ODD_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__BQ_GAIN_ODD_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__XLNA_GAIN_EVEN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__LNA_GAIN_EVEN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__GM_GAIN_EVEN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__TIA_GAIN_EVEN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__SLM_XLNA_EVEN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__BQ_GAIN_EVEN_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__XLNA_GAIN_ODD_12___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__XLNA_GAIN_ODD_12___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__LNA_GAIN_ODD_12___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__LNA_GAIN_ODD_12___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__GM_GAIN_ODD_12___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__GM_GAIN_ODD_12___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__TIA_GAIN_ODD_12___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__TIA_GAIN_ODD_12___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__SLM_XLNA_ODD_12___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__SLM_XLNA_ODD_12___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__BQ_GAIN_ODD_12___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__BQ_GAIN_ODD_12___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__XLNA_GAIN_EVEN_12___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__XLNA_GAIN_EVEN_12___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__LNA_GAIN_EVEN_12___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__LNA_GAIN_EVEN_12___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__GM_GAIN_EVEN_12___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__GM_GAIN_EVEN_12___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__TIA_GAIN_EVEN_12___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__TIA_GAIN_EVEN_12___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__SLM_XLNA_EVEN_12___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__SLM_XLNA_EVEN_12___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__BQ_GAIN_EVEN_12___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12__BQ_GAIN_EVEN_12___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_12___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13 (0x005F5034) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__XLNA_GAIN_ODD_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__LNA_GAIN_ODD_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__GM_GAIN_ODD_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__TIA_GAIN_ODD_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__SLM_XLNA_ODD_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__BQ_GAIN_ODD_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__XLNA_GAIN_EVEN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__LNA_GAIN_EVEN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__GM_GAIN_EVEN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__TIA_GAIN_EVEN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__SLM_XLNA_EVEN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__BQ_GAIN_EVEN_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__XLNA_GAIN_ODD_13___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__XLNA_GAIN_ODD_13___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__LNA_GAIN_ODD_13___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__LNA_GAIN_ODD_13___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__GM_GAIN_ODD_13___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__GM_GAIN_ODD_13___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__TIA_GAIN_ODD_13___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__TIA_GAIN_ODD_13___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__SLM_XLNA_ODD_13___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__SLM_XLNA_ODD_13___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__BQ_GAIN_ODD_13___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__BQ_GAIN_ODD_13___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__XLNA_GAIN_EVEN_13___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__XLNA_GAIN_EVEN_13___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__LNA_GAIN_EVEN_13___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__LNA_GAIN_EVEN_13___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__GM_GAIN_EVEN_13___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__GM_GAIN_EVEN_13___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__TIA_GAIN_EVEN_13___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__TIA_GAIN_EVEN_13___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__SLM_XLNA_EVEN_13___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__SLM_XLNA_EVEN_13___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__BQ_GAIN_EVEN_13___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13__BQ_GAIN_EVEN_13___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_13___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14 (0x005F5038) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__XLNA_GAIN_ODD_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__LNA_GAIN_ODD_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__GM_GAIN_ODD_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__TIA_GAIN_ODD_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__SLM_XLNA_ODD_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__BQ_GAIN_ODD_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__XLNA_GAIN_EVEN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__LNA_GAIN_EVEN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__GM_GAIN_EVEN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__TIA_GAIN_EVEN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__SLM_XLNA_EVEN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__BQ_GAIN_EVEN_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__XLNA_GAIN_ODD_14___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__XLNA_GAIN_ODD_14___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__LNA_GAIN_ODD_14___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__LNA_GAIN_ODD_14___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__GM_GAIN_ODD_14___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__GM_GAIN_ODD_14___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__TIA_GAIN_ODD_14___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__TIA_GAIN_ODD_14___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__SLM_XLNA_ODD_14___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__SLM_XLNA_ODD_14___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__BQ_GAIN_ODD_14___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__BQ_GAIN_ODD_14___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__XLNA_GAIN_EVEN_14___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__XLNA_GAIN_EVEN_14___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__LNA_GAIN_EVEN_14___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__LNA_GAIN_EVEN_14___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__GM_GAIN_EVEN_14___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__GM_GAIN_EVEN_14___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__TIA_GAIN_EVEN_14___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__TIA_GAIN_EVEN_14___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__SLM_XLNA_EVEN_14___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__SLM_XLNA_EVEN_14___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__BQ_GAIN_EVEN_14___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14__BQ_GAIN_EVEN_14___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_14___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15 (0x005F503C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__XLNA_GAIN_ODD_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__LNA_GAIN_ODD_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__GM_GAIN_ODD_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__TIA_GAIN_ODD_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__SLM_XLNA_ODD_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__BQ_GAIN_ODD_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__XLNA_GAIN_EVEN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__LNA_GAIN_EVEN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__GM_GAIN_EVEN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__TIA_GAIN_EVEN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__SLM_XLNA_EVEN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__BQ_GAIN_EVEN_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__XLNA_GAIN_ODD_15___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__XLNA_GAIN_ODD_15___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__LNA_GAIN_ODD_15___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__LNA_GAIN_ODD_15___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__GM_GAIN_ODD_15___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__GM_GAIN_ODD_15___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__TIA_GAIN_ODD_15___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__TIA_GAIN_ODD_15___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__SLM_XLNA_ODD_15___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__SLM_XLNA_ODD_15___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__BQ_GAIN_ODD_15___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__BQ_GAIN_ODD_15___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__XLNA_GAIN_EVEN_15___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__XLNA_GAIN_EVEN_15___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__LNA_GAIN_EVEN_15___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__LNA_GAIN_EVEN_15___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__GM_GAIN_EVEN_15___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__GM_GAIN_EVEN_15___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__TIA_GAIN_EVEN_15___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__TIA_GAIN_EVEN_15___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__SLM_XLNA_EVEN_15___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__SLM_XLNA_EVEN_15___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__BQ_GAIN_EVEN_15___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15__BQ_GAIN_EVEN_15___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_15___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16 (0x005F5040) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__XLNA_GAIN_ODD_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__LNA_GAIN_ODD_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__GM_GAIN_ODD_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__TIA_GAIN_ODD_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__SLM_XLNA_ODD_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__BQ_GAIN_ODD_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__XLNA_GAIN_EVEN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__LNA_GAIN_EVEN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__GM_GAIN_EVEN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__TIA_GAIN_EVEN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__SLM_XLNA_EVEN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__BQ_GAIN_EVEN_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__XLNA_GAIN_ODD_16___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__XLNA_GAIN_ODD_16___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__LNA_GAIN_ODD_16___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__LNA_GAIN_ODD_16___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__GM_GAIN_ODD_16___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__GM_GAIN_ODD_16___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__TIA_GAIN_ODD_16___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__TIA_GAIN_ODD_16___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__SLM_XLNA_ODD_16___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__SLM_XLNA_ODD_16___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__BQ_GAIN_ODD_16___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__BQ_GAIN_ODD_16___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__XLNA_GAIN_EVEN_16___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__XLNA_GAIN_EVEN_16___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__LNA_GAIN_EVEN_16___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__LNA_GAIN_EVEN_16___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__GM_GAIN_EVEN_16___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__GM_GAIN_EVEN_16___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__TIA_GAIN_EVEN_16___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__TIA_GAIN_EVEN_16___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__SLM_XLNA_EVEN_16___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__SLM_XLNA_EVEN_16___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__BQ_GAIN_EVEN_16___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16__BQ_GAIN_EVEN_16___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_16___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17 (0x005F5044) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__XLNA_GAIN_ODD_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__LNA_GAIN_ODD_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__GM_GAIN_ODD_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__TIA_GAIN_ODD_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__SLM_XLNA_ODD_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__BQ_GAIN_ODD_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__XLNA_GAIN_EVEN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__LNA_GAIN_EVEN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__GM_GAIN_EVEN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__TIA_GAIN_EVEN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__SLM_XLNA_EVEN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__BQ_GAIN_EVEN_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__XLNA_GAIN_ODD_17___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__XLNA_GAIN_ODD_17___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__LNA_GAIN_ODD_17___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__LNA_GAIN_ODD_17___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__GM_GAIN_ODD_17___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__GM_GAIN_ODD_17___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__TIA_GAIN_ODD_17___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__TIA_GAIN_ODD_17___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__SLM_XLNA_ODD_17___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__SLM_XLNA_ODD_17___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__BQ_GAIN_ODD_17___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__BQ_GAIN_ODD_17___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__XLNA_GAIN_EVEN_17___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__XLNA_GAIN_EVEN_17___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__LNA_GAIN_EVEN_17___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__LNA_GAIN_EVEN_17___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__GM_GAIN_EVEN_17___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__GM_GAIN_EVEN_17___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__TIA_GAIN_EVEN_17___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__TIA_GAIN_EVEN_17___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__SLM_XLNA_EVEN_17___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__SLM_XLNA_EVEN_17___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__BQ_GAIN_EVEN_17___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17__BQ_GAIN_EVEN_17___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_17___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18 (0x005F5048) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__XLNA_GAIN_ODD_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__LNA_GAIN_ODD_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__GM_GAIN_ODD_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__TIA_GAIN_ODD_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__SLM_XLNA_ODD_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__BQ_GAIN_ODD_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__XLNA_GAIN_EVEN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__LNA_GAIN_EVEN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__GM_GAIN_EVEN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__TIA_GAIN_EVEN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__SLM_XLNA_EVEN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__BQ_GAIN_EVEN_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__XLNA_GAIN_ODD_18___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__XLNA_GAIN_ODD_18___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__LNA_GAIN_ODD_18___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__LNA_GAIN_ODD_18___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__GM_GAIN_ODD_18___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__GM_GAIN_ODD_18___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__TIA_GAIN_ODD_18___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__TIA_GAIN_ODD_18___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__SLM_XLNA_ODD_18___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__SLM_XLNA_ODD_18___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__BQ_GAIN_ODD_18___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__BQ_GAIN_ODD_18___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__XLNA_GAIN_EVEN_18___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__XLNA_GAIN_EVEN_18___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__LNA_GAIN_EVEN_18___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__LNA_GAIN_EVEN_18___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__GM_GAIN_EVEN_18___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__GM_GAIN_EVEN_18___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__TIA_GAIN_EVEN_18___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__TIA_GAIN_EVEN_18___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__SLM_XLNA_EVEN_18___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__SLM_XLNA_EVEN_18___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__BQ_GAIN_EVEN_18___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18__BQ_GAIN_EVEN_18___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_18___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19 (0x005F504C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__XLNA_GAIN_ODD_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__LNA_GAIN_ODD_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__GM_GAIN_ODD_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__TIA_GAIN_ODD_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__SLM_XLNA_ODD_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__BQ_GAIN_ODD_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__XLNA_GAIN_EVEN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__LNA_GAIN_EVEN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__GM_GAIN_EVEN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__TIA_GAIN_EVEN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__SLM_XLNA_EVEN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__BQ_GAIN_EVEN_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__XLNA_GAIN_ODD_19___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__XLNA_GAIN_ODD_19___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__LNA_GAIN_ODD_19___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__LNA_GAIN_ODD_19___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__GM_GAIN_ODD_19___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__GM_GAIN_ODD_19___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__TIA_GAIN_ODD_19___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__TIA_GAIN_ODD_19___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__SLM_XLNA_ODD_19___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__SLM_XLNA_ODD_19___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__BQ_GAIN_ODD_19___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__BQ_GAIN_ODD_19___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__XLNA_GAIN_EVEN_19___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__XLNA_GAIN_EVEN_19___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__LNA_GAIN_EVEN_19___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__LNA_GAIN_EVEN_19___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__GM_GAIN_EVEN_19___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__GM_GAIN_EVEN_19___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__TIA_GAIN_EVEN_19___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__TIA_GAIN_EVEN_19___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__SLM_XLNA_EVEN_19___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__SLM_XLNA_EVEN_19___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__BQ_GAIN_EVEN_19___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19__BQ_GAIN_EVEN_19___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_19___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20 (0x005F5050) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__XLNA_GAIN_ODD_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__LNA_GAIN_ODD_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__GM_GAIN_ODD_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__TIA_GAIN_ODD_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__SLM_XLNA_ODD_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__BQ_GAIN_ODD_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__XLNA_GAIN_EVEN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__LNA_GAIN_EVEN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__GM_GAIN_EVEN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__TIA_GAIN_EVEN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__SLM_XLNA_EVEN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__BQ_GAIN_EVEN_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__XLNA_GAIN_ODD_20___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__XLNA_GAIN_ODD_20___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__LNA_GAIN_ODD_20___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__LNA_GAIN_ODD_20___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__GM_GAIN_ODD_20___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__GM_GAIN_ODD_20___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__TIA_GAIN_ODD_20___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__TIA_GAIN_ODD_20___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__SLM_XLNA_ODD_20___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__SLM_XLNA_ODD_20___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__BQ_GAIN_ODD_20___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__BQ_GAIN_ODD_20___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__XLNA_GAIN_EVEN_20___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__XLNA_GAIN_EVEN_20___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__LNA_GAIN_EVEN_20___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__LNA_GAIN_EVEN_20___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__GM_GAIN_EVEN_20___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__GM_GAIN_EVEN_20___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__TIA_GAIN_EVEN_20___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__TIA_GAIN_EVEN_20___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__SLM_XLNA_EVEN_20___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__SLM_XLNA_EVEN_20___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__BQ_GAIN_EVEN_20___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20__BQ_GAIN_EVEN_20___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_20___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21 (0x005F5054) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__XLNA_GAIN_ODD_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__LNA_GAIN_ODD_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__GM_GAIN_ODD_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__TIA_GAIN_ODD_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__SLM_XLNA_ODD_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__BQ_GAIN_ODD_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__XLNA_GAIN_EVEN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__LNA_GAIN_EVEN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__GM_GAIN_EVEN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__TIA_GAIN_EVEN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__SLM_XLNA_EVEN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__BQ_GAIN_EVEN_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__XLNA_GAIN_ODD_21___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__XLNA_GAIN_ODD_21___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__LNA_GAIN_ODD_21___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__LNA_GAIN_ODD_21___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__GM_GAIN_ODD_21___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__GM_GAIN_ODD_21___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__TIA_GAIN_ODD_21___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__TIA_GAIN_ODD_21___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__SLM_XLNA_ODD_21___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__SLM_XLNA_ODD_21___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__BQ_GAIN_ODD_21___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__BQ_GAIN_ODD_21___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__XLNA_GAIN_EVEN_21___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__XLNA_GAIN_EVEN_21___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__LNA_GAIN_EVEN_21___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__LNA_GAIN_EVEN_21___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__GM_GAIN_EVEN_21___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__GM_GAIN_EVEN_21___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__TIA_GAIN_EVEN_21___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__TIA_GAIN_EVEN_21___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__SLM_XLNA_EVEN_21___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__SLM_XLNA_EVEN_21___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__BQ_GAIN_EVEN_21___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21__BQ_GAIN_EVEN_21___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_21___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22 (0x005F5058) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__XLNA_GAIN_ODD_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__LNA_GAIN_ODD_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__GM_GAIN_ODD_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__TIA_GAIN_ODD_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__SLM_XLNA_ODD_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__BQ_GAIN_ODD_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__XLNA_GAIN_EVEN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__LNA_GAIN_EVEN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__GM_GAIN_EVEN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__TIA_GAIN_EVEN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__SLM_XLNA_EVEN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__BQ_GAIN_EVEN_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__XLNA_GAIN_ODD_22___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__XLNA_GAIN_ODD_22___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__LNA_GAIN_ODD_22___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__LNA_GAIN_ODD_22___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__GM_GAIN_ODD_22___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__GM_GAIN_ODD_22___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__TIA_GAIN_ODD_22___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__TIA_GAIN_ODD_22___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__SLM_XLNA_ODD_22___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__SLM_XLNA_ODD_22___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__BQ_GAIN_ODD_22___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__BQ_GAIN_ODD_22___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__XLNA_GAIN_EVEN_22___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__XLNA_GAIN_EVEN_22___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__LNA_GAIN_EVEN_22___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__LNA_GAIN_EVEN_22___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__GM_GAIN_EVEN_22___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__GM_GAIN_EVEN_22___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__TIA_GAIN_EVEN_22___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__TIA_GAIN_EVEN_22___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__SLM_XLNA_EVEN_22___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__SLM_XLNA_EVEN_22___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__BQ_GAIN_EVEN_22___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22__BQ_GAIN_EVEN_22___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_22___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23 (0x005F505C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__XLNA_GAIN_ODD_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__LNA_GAIN_ODD_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__GM_GAIN_ODD_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__TIA_GAIN_ODD_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__SLM_XLNA_ODD_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__BQ_GAIN_ODD_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__XLNA_GAIN_EVEN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__LNA_GAIN_EVEN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__GM_GAIN_EVEN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__TIA_GAIN_EVEN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__SLM_XLNA_EVEN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__BQ_GAIN_EVEN_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__XLNA_GAIN_ODD_23___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__XLNA_GAIN_ODD_23___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__LNA_GAIN_ODD_23___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__LNA_GAIN_ODD_23___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__GM_GAIN_ODD_23___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__GM_GAIN_ODD_23___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__TIA_GAIN_ODD_23___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__TIA_GAIN_ODD_23___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__SLM_XLNA_ODD_23___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__SLM_XLNA_ODD_23___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__BQ_GAIN_ODD_23___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__BQ_GAIN_ODD_23___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__XLNA_GAIN_EVEN_23___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__XLNA_GAIN_EVEN_23___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__LNA_GAIN_EVEN_23___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__LNA_GAIN_EVEN_23___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__GM_GAIN_EVEN_23___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__GM_GAIN_EVEN_23___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__TIA_GAIN_EVEN_23___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__TIA_GAIN_EVEN_23___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__SLM_XLNA_EVEN_23___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__SLM_XLNA_EVEN_23___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__BQ_GAIN_EVEN_23___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23__BQ_GAIN_EVEN_23___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_23___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24 (0x005F5060) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__XLNA_GAIN_ODD_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__LNA_GAIN_ODD_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__GM_GAIN_ODD_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__TIA_GAIN_ODD_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__SLM_XLNA_ODD_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__BQ_GAIN_ODD_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__XLNA_GAIN_EVEN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__LNA_GAIN_EVEN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__GM_GAIN_EVEN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__TIA_GAIN_EVEN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__SLM_XLNA_EVEN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__BQ_GAIN_EVEN_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__XLNA_GAIN_ODD_24___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__XLNA_GAIN_ODD_24___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__LNA_GAIN_ODD_24___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__LNA_GAIN_ODD_24___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__GM_GAIN_ODD_24___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__GM_GAIN_ODD_24___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__TIA_GAIN_ODD_24___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__TIA_GAIN_ODD_24___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__SLM_XLNA_ODD_24___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__SLM_XLNA_ODD_24___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__BQ_GAIN_ODD_24___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__BQ_GAIN_ODD_24___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__XLNA_GAIN_EVEN_24___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__XLNA_GAIN_EVEN_24___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__LNA_GAIN_EVEN_24___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__LNA_GAIN_EVEN_24___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__GM_GAIN_EVEN_24___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__GM_GAIN_EVEN_24___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__TIA_GAIN_EVEN_24___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__TIA_GAIN_EVEN_24___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__SLM_XLNA_EVEN_24___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__SLM_XLNA_EVEN_24___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__BQ_GAIN_EVEN_24___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24__BQ_GAIN_EVEN_24___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_24___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25 (0x005F5064) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__XLNA_GAIN_ODD_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__LNA_GAIN_ODD_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__GM_GAIN_ODD_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__TIA_GAIN_ODD_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__SLM_XLNA_ODD_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__BQ_GAIN_ODD_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__XLNA_GAIN_EVEN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__LNA_GAIN_EVEN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__GM_GAIN_EVEN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__TIA_GAIN_EVEN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__SLM_XLNA_EVEN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__BQ_GAIN_EVEN_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__XLNA_GAIN_ODD_25___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__XLNA_GAIN_ODD_25___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__LNA_GAIN_ODD_25___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__LNA_GAIN_ODD_25___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__GM_GAIN_ODD_25___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__GM_GAIN_ODD_25___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__TIA_GAIN_ODD_25___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__TIA_GAIN_ODD_25___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__SLM_XLNA_ODD_25___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__SLM_XLNA_ODD_25___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__BQ_GAIN_ODD_25___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__BQ_GAIN_ODD_25___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__XLNA_GAIN_EVEN_25___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__XLNA_GAIN_EVEN_25___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__LNA_GAIN_EVEN_25___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__LNA_GAIN_EVEN_25___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__GM_GAIN_EVEN_25___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__GM_GAIN_EVEN_25___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__TIA_GAIN_EVEN_25___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__TIA_GAIN_EVEN_25___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__SLM_XLNA_EVEN_25___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__SLM_XLNA_EVEN_25___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__BQ_GAIN_EVEN_25___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25__BQ_GAIN_EVEN_25___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_25___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26 (0x005F5068) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__XLNA_GAIN_ODD_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__LNA_GAIN_ODD_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__GM_GAIN_ODD_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__TIA_GAIN_ODD_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__SLM_XLNA_ODD_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__BQ_GAIN_ODD_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__XLNA_GAIN_EVEN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__LNA_GAIN_EVEN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__GM_GAIN_EVEN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__TIA_GAIN_EVEN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__SLM_XLNA_EVEN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__BQ_GAIN_EVEN_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__XLNA_GAIN_ODD_26___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__XLNA_GAIN_ODD_26___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__LNA_GAIN_ODD_26___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__LNA_GAIN_ODD_26___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__GM_GAIN_ODD_26___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__GM_GAIN_ODD_26___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__TIA_GAIN_ODD_26___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__TIA_GAIN_ODD_26___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__SLM_XLNA_ODD_26___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__SLM_XLNA_ODD_26___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__BQ_GAIN_ODD_26___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__BQ_GAIN_ODD_26___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__XLNA_GAIN_EVEN_26___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__XLNA_GAIN_EVEN_26___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__LNA_GAIN_EVEN_26___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__LNA_GAIN_EVEN_26___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__GM_GAIN_EVEN_26___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__GM_GAIN_EVEN_26___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__TIA_GAIN_EVEN_26___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__TIA_GAIN_EVEN_26___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__SLM_XLNA_EVEN_26___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__SLM_XLNA_EVEN_26___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__BQ_GAIN_EVEN_26___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26__BQ_GAIN_EVEN_26___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_26___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27 (0x005F506C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__XLNA_GAIN_ODD_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__LNA_GAIN_ODD_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__GM_GAIN_ODD_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__TIA_GAIN_ODD_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__SLM_XLNA_ODD_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__BQ_GAIN_ODD_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__XLNA_GAIN_EVEN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__LNA_GAIN_EVEN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__GM_GAIN_EVEN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__TIA_GAIN_EVEN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__SLM_XLNA_EVEN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__BQ_GAIN_EVEN_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__XLNA_GAIN_ODD_27___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__XLNA_GAIN_ODD_27___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__LNA_GAIN_ODD_27___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__LNA_GAIN_ODD_27___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__GM_GAIN_ODD_27___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__GM_GAIN_ODD_27___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__TIA_GAIN_ODD_27___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__TIA_GAIN_ODD_27___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__SLM_XLNA_ODD_27___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__SLM_XLNA_ODD_27___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__BQ_GAIN_ODD_27___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__BQ_GAIN_ODD_27___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__XLNA_GAIN_EVEN_27___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__XLNA_GAIN_EVEN_27___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__LNA_GAIN_EVEN_27___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__LNA_GAIN_EVEN_27___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__GM_GAIN_EVEN_27___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__GM_GAIN_EVEN_27___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__TIA_GAIN_EVEN_27___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__TIA_GAIN_EVEN_27___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__SLM_XLNA_EVEN_27___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__SLM_XLNA_EVEN_27___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__BQ_GAIN_EVEN_27___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27__BQ_GAIN_EVEN_27___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_27___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28 (0x005F5070) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__XLNA_GAIN_ODD_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__LNA_GAIN_ODD_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__GM_GAIN_ODD_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__TIA_GAIN_ODD_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__SLM_XLNA_ODD_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__BQ_GAIN_ODD_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__XLNA_GAIN_EVEN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__LNA_GAIN_EVEN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__GM_GAIN_EVEN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__TIA_GAIN_EVEN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__SLM_XLNA_EVEN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__BQ_GAIN_EVEN_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__XLNA_GAIN_ODD_28___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__XLNA_GAIN_ODD_28___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__LNA_GAIN_ODD_28___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__LNA_GAIN_ODD_28___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__GM_GAIN_ODD_28___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__GM_GAIN_ODD_28___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__TIA_GAIN_ODD_28___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__TIA_GAIN_ODD_28___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__SLM_XLNA_ODD_28___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__SLM_XLNA_ODD_28___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__BQ_GAIN_ODD_28___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__BQ_GAIN_ODD_28___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__XLNA_GAIN_EVEN_28___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__XLNA_GAIN_EVEN_28___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__LNA_GAIN_EVEN_28___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__LNA_GAIN_EVEN_28___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__GM_GAIN_EVEN_28___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__GM_GAIN_EVEN_28___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__TIA_GAIN_EVEN_28___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__TIA_GAIN_EVEN_28___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__SLM_XLNA_EVEN_28___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__SLM_XLNA_EVEN_28___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__BQ_GAIN_EVEN_28___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28__BQ_GAIN_EVEN_28___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_28___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29 (0x005F5074) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__XLNA_GAIN_ODD_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__LNA_GAIN_ODD_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__GM_GAIN_ODD_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__TIA_GAIN_ODD_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__SLM_XLNA_ODD_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__BQ_GAIN_ODD_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__XLNA_GAIN_EVEN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__LNA_GAIN_EVEN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__GM_GAIN_EVEN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__TIA_GAIN_EVEN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__SLM_XLNA_EVEN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__BQ_GAIN_EVEN_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__XLNA_GAIN_ODD_29___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__XLNA_GAIN_ODD_29___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__LNA_GAIN_ODD_29___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__LNA_GAIN_ODD_29___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__GM_GAIN_ODD_29___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__GM_GAIN_ODD_29___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__TIA_GAIN_ODD_29___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__TIA_GAIN_ODD_29___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__SLM_XLNA_ODD_29___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__SLM_XLNA_ODD_29___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__BQ_GAIN_ODD_29___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__BQ_GAIN_ODD_29___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__XLNA_GAIN_EVEN_29___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__XLNA_GAIN_EVEN_29___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__LNA_GAIN_EVEN_29___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__LNA_GAIN_EVEN_29___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__GM_GAIN_EVEN_29___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__GM_GAIN_EVEN_29___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__TIA_GAIN_EVEN_29___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__TIA_GAIN_EVEN_29___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__SLM_XLNA_EVEN_29___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__SLM_XLNA_EVEN_29___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__BQ_GAIN_EVEN_29___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29__BQ_GAIN_EVEN_29___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_29___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30 (0x005F5078) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__XLNA_GAIN_ODD_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__LNA_GAIN_ODD_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__GM_GAIN_ODD_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__TIA_GAIN_ODD_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__SLM_XLNA_ODD_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__BQ_GAIN_ODD_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__XLNA_GAIN_EVEN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__LNA_GAIN_EVEN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__GM_GAIN_EVEN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__TIA_GAIN_EVEN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__SLM_XLNA_EVEN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__BQ_GAIN_EVEN_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__XLNA_GAIN_ODD_30___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__XLNA_GAIN_ODD_30___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__LNA_GAIN_ODD_30___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__LNA_GAIN_ODD_30___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__GM_GAIN_ODD_30___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__GM_GAIN_ODD_30___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__TIA_GAIN_ODD_30___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__TIA_GAIN_ODD_30___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__SLM_XLNA_ODD_30___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__SLM_XLNA_ODD_30___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__BQ_GAIN_ODD_30___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__BQ_GAIN_ODD_30___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__XLNA_GAIN_EVEN_30___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__XLNA_GAIN_EVEN_30___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__LNA_GAIN_EVEN_30___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__LNA_GAIN_EVEN_30___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__GM_GAIN_EVEN_30___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__GM_GAIN_EVEN_30___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__TIA_GAIN_EVEN_30___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__TIA_GAIN_EVEN_30___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__SLM_XLNA_EVEN_30___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__SLM_XLNA_EVEN_30___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__BQ_GAIN_EVEN_30___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30__BQ_GAIN_EVEN_30___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_30___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31 (0x005F507C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__XLNA_GAIN_ODD_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__LNA_GAIN_ODD_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__GM_GAIN_ODD_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__TIA_GAIN_ODD_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__SLM_XLNA_ODD_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__BQ_GAIN_ODD_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__XLNA_GAIN_EVEN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__LNA_GAIN_EVEN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__GM_GAIN_EVEN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__TIA_GAIN_EVEN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__SLM_XLNA_EVEN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__BQ_GAIN_EVEN_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__XLNA_GAIN_ODD_31___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__XLNA_GAIN_ODD_31___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__LNA_GAIN_ODD_31___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__LNA_GAIN_ODD_31___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__GM_GAIN_ODD_31___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__GM_GAIN_ODD_31___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__TIA_GAIN_ODD_31___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__TIA_GAIN_ODD_31___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__SLM_XLNA_ODD_31___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__SLM_XLNA_ODD_31___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__BQ_GAIN_ODD_31___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__BQ_GAIN_ODD_31___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__XLNA_GAIN_EVEN_31___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__XLNA_GAIN_EVEN_31___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__LNA_GAIN_EVEN_31___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__LNA_GAIN_EVEN_31___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__GM_GAIN_EVEN_31___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__GM_GAIN_EVEN_31___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__TIA_GAIN_EVEN_31___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__TIA_GAIN_EVEN_31___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__SLM_XLNA_EVEN_31___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__SLM_XLNA_EVEN_31___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__BQ_GAIN_EVEN_31___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31__BQ_GAIN_EVEN_31___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_31___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32 (0x005F5080) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__XLNA_GAIN_ODD_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__LNA_GAIN_ODD_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__GM_GAIN_ODD_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__TIA_GAIN_ODD_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__SLM_XLNA_ODD_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__BQ_GAIN_ODD_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__XLNA_GAIN_EVEN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__LNA_GAIN_EVEN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__GM_GAIN_EVEN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__TIA_GAIN_EVEN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__SLM_XLNA_EVEN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__BQ_GAIN_EVEN_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__XLNA_GAIN_ODD_32___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__XLNA_GAIN_ODD_32___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__LNA_GAIN_ODD_32___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__LNA_GAIN_ODD_32___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__GM_GAIN_ODD_32___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__GM_GAIN_ODD_32___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__TIA_GAIN_ODD_32___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__TIA_GAIN_ODD_32___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__SLM_XLNA_ODD_32___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__SLM_XLNA_ODD_32___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__BQ_GAIN_ODD_32___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__BQ_GAIN_ODD_32___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__XLNA_GAIN_EVEN_32___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__XLNA_GAIN_EVEN_32___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__LNA_GAIN_EVEN_32___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__LNA_GAIN_EVEN_32___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__GM_GAIN_EVEN_32___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__GM_GAIN_EVEN_32___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__TIA_GAIN_EVEN_32___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__TIA_GAIN_EVEN_32___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__SLM_XLNA_EVEN_32___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__SLM_XLNA_EVEN_32___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__BQ_GAIN_EVEN_32___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32__BQ_GAIN_EVEN_32___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_32___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33 (0x005F5084) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__XLNA_GAIN_ODD_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__LNA_GAIN_ODD_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__GM_GAIN_ODD_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__TIA_GAIN_ODD_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__SLM_XLNA_ODD_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__BQ_GAIN_ODD_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__XLNA_GAIN_EVEN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__LNA_GAIN_EVEN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__GM_GAIN_EVEN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__TIA_GAIN_EVEN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__SLM_XLNA_EVEN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__BQ_GAIN_EVEN_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__XLNA_GAIN_ODD_33___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__XLNA_GAIN_ODD_33___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__LNA_GAIN_ODD_33___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__LNA_GAIN_ODD_33___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__GM_GAIN_ODD_33___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__GM_GAIN_ODD_33___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__TIA_GAIN_ODD_33___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__TIA_GAIN_ODD_33___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__SLM_XLNA_ODD_33___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__SLM_XLNA_ODD_33___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__BQ_GAIN_ODD_33___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__BQ_GAIN_ODD_33___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__XLNA_GAIN_EVEN_33___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__XLNA_GAIN_EVEN_33___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__LNA_GAIN_EVEN_33___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__LNA_GAIN_EVEN_33___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__GM_GAIN_EVEN_33___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__GM_GAIN_EVEN_33___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__TIA_GAIN_EVEN_33___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__TIA_GAIN_EVEN_33___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__SLM_XLNA_EVEN_33___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__SLM_XLNA_EVEN_33___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__BQ_GAIN_EVEN_33___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33__BQ_GAIN_EVEN_33___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_33___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34 (0x005F5088) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__XLNA_GAIN_ODD_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__LNA_GAIN_ODD_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__GM_GAIN_ODD_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__TIA_GAIN_ODD_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__SLM_XLNA_ODD_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__BQ_GAIN_ODD_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__XLNA_GAIN_EVEN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__LNA_GAIN_EVEN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__GM_GAIN_EVEN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__TIA_GAIN_EVEN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__SLM_XLNA_EVEN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__BQ_GAIN_EVEN_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__XLNA_GAIN_ODD_34___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__XLNA_GAIN_ODD_34___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__LNA_GAIN_ODD_34___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__LNA_GAIN_ODD_34___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__GM_GAIN_ODD_34___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__GM_GAIN_ODD_34___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__TIA_GAIN_ODD_34___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__TIA_GAIN_ODD_34___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__SLM_XLNA_ODD_34___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__SLM_XLNA_ODD_34___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__BQ_GAIN_ODD_34___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__BQ_GAIN_ODD_34___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__XLNA_GAIN_EVEN_34___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__XLNA_GAIN_EVEN_34___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__LNA_GAIN_EVEN_34___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__LNA_GAIN_EVEN_34___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__GM_GAIN_EVEN_34___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__GM_GAIN_EVEN_34___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__TIA_GAIN_EVEN_34___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__TIA_GAIN_EVEN_34___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__SLM_XLNA_EVEN_34___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__SLM_XLNA_EVEN_34___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__BQ_GAIN_EVEN_34___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34__BQ_GAIN_EVEN_34___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_34___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35 (0x005F508C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__XLNA_GAIN_ODD_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__LNA_GAIN_ODD_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__GM_GAIN_ODD_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__TIA_GAIN_ODD_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__SLM_XLNA_ODD_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__BQ_GAIN_ODD_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__XLNA_GAIN_EVEN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__LNA_GAIN_EVEN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__GM_GAIN_EVEN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__TIA_GAIN_EVEN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__SLM_XLNA_EVEN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__BQ_GAIN_EVEN_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__XLNA_GAIN_ODD_35___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__XLNA_GAIN_ODD_35___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__LNA_GAIN_ODD_35___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__LNA_GAIN_ODD_35___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__GM_GAIN_ODD_35___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__GM_GAIN_ODD_35___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__TIA_GAIN_ODD_35___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__TIA_GAIN_ODD_35___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__SLM_XLNA_ODD_35___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__SLM_XLNA_ODD_35___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__BQ_GAIN_ODD_35___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__BQ_GAIN_ODD_35___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__XLNA_GAIN_EVEN_35___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__XLNA_GAIN_EVEN_35___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__LNA_GAIN_EVEN_35___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__LNA_GAIN_EVEN_35___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__GM_GAIN_EVEN_35___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__GM_GAIN_EVEN_35___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__TIA_GAIN_EVEN_35___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__TIA_GAIN_EVEN_35___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__SLM_XLNA_EVEN_35___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__SLM_XLNA_EVEN_35___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__BQ_GAIN_EVEN_35___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35__BQ_GAIN_EVEN_35___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_35___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36 (0x005F5090) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__XLNA_GAIN_ODD_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__LNA_GAIN_ODD_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__GM_GAIN_ODD_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__TIA_GAIN_ODD_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__SLM_XLNA_ODD_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__BQ_GAIN_ODD_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__XLNA_GAIN_EVEN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__LNA_GAIN_EVEN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__GM_GAIN_EVEN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__TIA_GAIN_EVEN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__SLM_XLNA_EVEN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__BQ_GAIN_EVEN_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__XLNA_GAIN_ODD_36___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__XLNA_GAIN_ODD_36___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__LNA_GAIN_ODD_36___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__LNA_GAIN_ODD_36___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__GM_GAIN_ODD_36___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__GM_GAIN_ODD_36___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__TIA_GAIN_ODD_36___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__TIA_GAIN_ODD_36___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__SLM_XLNA_ODD_36___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__SLM_XLNA_ODD_36___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__BQ_GAIN_ODD_36___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__BQ_GAIN_ODD_36___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__XLNA_GAIN_EVEN_36___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__XLNA_GAIN_EVEN_36___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__LNA_GAIN_EVEN_36___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__LNA_GAIN_EVEN_36___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__GM_GAIN_EVEN_36___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__GM_GAIN_EVEN_36___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__TIA_GAIN_EVEN_36___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__TIA_GAIN_EVEN_36___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__SLM_XLNA_EVEN_36___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__SLM_XLNA_EVEN_36___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__BQ_GAIN_EVEN_36___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36__BQ_GAIN_EVEN_36___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_36___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37 (0x005F5094) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__XLNA_GAIN_ODD_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__LNA_GAIN_ODD_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__GM_GAIN_ODD_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__TIA_GAIN_ODD_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__SLM_XLNA_ODD_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__BQ_GAIN_ODD_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__XLNA_GAIN_EVEN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__LNA_GAIN_EVEN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__GM_GAIN_EVEN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__TIA_GAIN_EVEN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__SLM_XLNA_EVEN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__BQ_GAIN_EVEN_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__XLNA_GAIN_ODD_37___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__XLNA_GAIN_ODD_37___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__LNA_GAIN_ODD_37___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__LNA_GAIN_ODD_37___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__GM_GAIN_ODD_37___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__GM_GAIN_ODD_37___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__TIA_GAIN_ODD_37___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__TIA_GAIN_ODD_37___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__SLM_XLNA_ODD_37___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__SLM_XLNA_ODD_37___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__BQ_GAIN_ODD_37___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__BQ_GAIN_ODD_37___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__XLNA_GAIN_EVEN_37___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__XLNA_GAIN_EVEN_37___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__LNA_GAIN_EVEN_37___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__LNA_GAIN_EVEN_37___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__GM_GAIN_EVEN_37___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__GM_GAIN_EVEN_37___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__TIA_GAIN_EVEN_37___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__TIA_GAIN_EVEN_37___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__SLM_XLNA_EVEN_37___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__SLM_XLNA_EVEN_37___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__BQ_GAIN_EVEN_37___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37__BQ_GAIN_EVEN_37___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_37___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38 (0x005F5098) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__XLNA_GAIN_ODD_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__LNA_GAIN_ODD_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__GM_GAIN_ODD_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__TIA_GAIN_ODD_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__SLM_XLNA_ODD_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__BQ_GAIN_ODD_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__XLNA_GAIN_EVEN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__LNA_GAIN_EVEN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__GM_GAIN_EVEN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__TIA_GAIN_EVEN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__SLM_XLNA_EVEN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__BQ_GAIN_EVEN_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__XLNA_GAIN_ODD_38___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__XLNA_GAIN_ODD_38___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__LNA_GAIN_ODD_38___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__LNA_GAIN_ODD_38___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__GM_GAIN_ODD_38___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__GM_GAIN_ODD_38___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__TIA_GAIN_ODD_38___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__TIA_GAIN_ODD_38___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__SLM_XLNA_ODD_38___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__SLM_XLNA_ODD_38___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__BQ_GAIN_ODD_38___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__BQ_GAIN_ODD_38___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__XLNA_GAIN_EVEN_38___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__XLNA_GAIN_EVEN_38___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__LNA_GAIN_EVEN_38___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__LNA_GAIN_EVEN_38___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__GM_GAIN_EVEN_38___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__GM_GAIN_EVEN_38___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__TIA_GAIN_EVEN_38___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__TIA_GAIN_EVEN_38___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__SLM_XLNA_EVEN_38___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__SLM_XLNA_EVEN_38___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__BQ_GAIN_EVEN_38___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38__BQ_GAIN_EVEN_38___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_38___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39 (0x005F509C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__XLNA_GAIN_ODD_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__LNA_GAIN_ODD_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__GM_GAIN_ODD_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__TIA_GAIN_ODD_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__SLM_XLNA_ODD_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__BQ_GAIN_ODD_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__XLNA_GAIN_EVEN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__LNA_GAIN_EVEN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__GM_GAIN_EVEN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__TIA_GAIN_EVEN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__SLM_XLNA_EVEN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__BQ_GAIN_EVEN_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__XLNA_GAIN_ODD_39___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__XLNA_GAIN_ODD_39___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__LNA_GAIN_ODD_39___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__LNA_GAIN_ODD_39___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__GM_GAIN_ODD_39___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__GM_GAIN_ODD_39___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__TIA_GAIN_ODD_39___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__TIA_GAIN_ODD_39___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__SLM_XLNA_ODD_39___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__SLM_XLNA_ODD_39___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__BQ_GAIN_ODD_39___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__BQ_GAIN_ODD_39___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__XLNA_GAIN_EVEN_39___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__XLNA_GAIN_EVEN_39___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__LNA_GAIN_EVEN_39___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__LNA_GAIN_EVEN_39___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__GM_GAIN_EVEN_39___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__GM_GAIN_EVEN_39___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__TIA_GAIN_EVEN_39___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__TIA_GAIN_EVEN_39___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__SLM_XLNA_EVEN_39___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__SLM_XLNA_EVEN_39___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__BQ_GAIN_EVEN_39___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39__BQ_GAIN_EVEN_39___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_39___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40 (0x005F50A0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__XLNA_GAIN_ODD_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__LNA_GAIN_ODD_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__GM_GAIN_ODD_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__TIA_GAIN_ODD_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__SLM_XLNA_ODD_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__BQ_GAIN_ODD_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__XLNA_GAIN_EVEN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__LNA_GAIN_EVEN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__GM_GAIN_EVEN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__TIA_GAIN_EVEN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__SLM_XLNA_EVEN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__BQ_GAIN_EVEN_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__XLNA_GAIN_ODD_40___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__XLNA_GAIN_ODD_40___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__LNA_GAIN_ODD_40___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__LNA_GAIN_ODD_40___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__GM_GAIN_ODD_40___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__GM_GAIN_ODD_40___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__TIA_GAIN_ODD_40___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__TIA_GAIN_ODD_40___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__SLM_XLNA_ODD_40___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__SLM_XLNA_ODD_40___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__BQ_GAIN_ODD_40___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__BQ_GAIN_ODD_40___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__XLNA_GAIN_EVEN_40___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__XLNA_GAIN_EVEN_40___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__LNA_GAIN_EVEN_40___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__LNA_GAIN_EVEN_40___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__GM_GAIN_EVEN_40___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__GM_GAIN_EVEN_40___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__TIA_GAIN_EVEN_40___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__TIA_GAIN_EVEN_40___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__SLM_XLNA_EVEN_40___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__SLM_XLNA_EVEN_40___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__BQ_GAIN_EVEN_40___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40__BQ_GAIN_EVEN_40___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_40___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41 (0x005F50A4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__XLNA_GAIN_ODD_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__LNA_GAIN_ODD_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__GM_GAIN_ODD_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__TIA_GAIN_ODD_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__SLM_XLNA_ODD_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__BQ_GAIN_ODD_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__XLNA_GAIN_EVEN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__LNA_GAIN_EVEN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__GM_GAIN_EVEN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__TIA_GAIN_EVEN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__SLM_XLNA_EVEN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__BQ_GAIN_EVEN_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__XLNA_GAIN_ODD_41___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__XLNA_GAIN_ODD_41___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__LNA_GAIN_ODD_41___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__LNA_GAIN_ODD_41___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__GM_GAIN_ODD_41___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__GM_GAIN_ODD_41___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__TIA_GAIN_ODD_41___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__TIA_GAIN_ODD_41___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__SLM_XLNA_ODD_41___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__SLM_XLNA_ODD_41___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__BQ_GAIN_ODD_41___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__BQ_GAIN_ODD_41___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__XLNA_GAIN_EVEN_41___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__XLNA_GAIN_EVEN_41___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__LNA_GAIN_EVEN_41___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__LNA_GAIN_EVEN_41___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__GM_GAIN_EVEN_41___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__GM_GAIN_EVEN_41___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__TIA_GAIN_EVEN_41___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__TIA_GAIN_EVEN_41___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__SLM_XLNA_EVEN_41___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__SLM_XLNA_EVEN_41___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__BQ_GAIN_EVEN_41___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41__BQ_GAIN_EVEN_41___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_41___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42 (0x005F50A8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__XLNA_GAIN_ODD_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__LNA_GAIN_ODD_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__GM_GAIN_ODD_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__TIA_GAIN_ODD_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__SLM_XLNA_ODD_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__BQ_GAIN_ODD_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__XLNA_GAIN_EVEN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__LNA_GAIN_EVEN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__GM_GAIN_EVEN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__TIA_GAIN_EVEN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__SLM_XLNA_EVEN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__BQ_GAIN_EVEN_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__XLNA_GAIN_ODD_42___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__XLNA_GAIN_ODD_42___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__LNA_GAIN_ODD_42___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__LNA_GAIN_ODD_42___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__GM_GAIN_ODD_42___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__GM_GAIN_ODD_42___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__TIA_GAIN_ODD_42___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__TIA_GAIN_ODD_42___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__SLM_XLNA_ODD_42___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__SLM_XLNA_ODD_42___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__BQ_GAIN_ODD_42___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__BQ_GAIN_ODD_42___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__XLNA_GAIN_EVEN_42___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__XLNA_GAIN_EVEN_42___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__LNA_GAIN_EVEN_42___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__LNA_GAIN_EVEN_42___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__GM_GAIN_EVEN_42___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__GM_GAIN_EVEN_42___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__TIA_GAIN_EVEN_42___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__TIA_GAIN_EVEN_42___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__SLM_XLNA_EVEN_42___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__SLM_XLNA_EVEN_42___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__BQ_GAIN_EVEN_42___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42__BQ_GAIN_EVEN_42___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_42___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43 (0x005F50AC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__XLNA_GAIN_ODD_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__LNA_GAIN_ODD_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__GM_GAIN_ODD_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__TIA_GAIN_ODD_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__SLM_XLNA_ODD_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__BQ_GAIN_ODD_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__XLNA_GAIN_EVEN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__LNA_GAIN_EVEN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__GM_GAIN_EVEN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__TIA_GAIN_EVEN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__SLM_XLNA_EVEN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__BQ_GAIN_EVEN_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__XLNA_GAIN_ODD_43___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__XLNA_GAIN_ODD_43___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__LNA_GAIN_ODD_43___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__LNA_GAIN_ODD_43___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__GM_GAIN_ODD_43___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__GM_GAIN_ODD_43___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__TIA_GAIN_ODD_43___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__TIA_GAIN_ODD_43___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__SLM_XLNA_ODD_43___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__SLM_XLNA_ODD_43___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__BQ_GAIN_ODD_43___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__BQ_GAIN_ODD_43___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__XLNA_GAIN_EVEN_43___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__XLNA_GAIN_EVEN_43___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__LNA_GAIN_EVEN_43___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__LNA_GAIN_EVEN_43___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__GM_GAIN_EVEN_43___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__GM_GAIN_EVEN_43___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__TIA_GAIN_EVEN_43___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__TIA_GAIN_EVEN_43___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__SLM_XLNA_EVEN_43___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__SLM_XLNA_EVEN_43___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__BQ_GAIN_EVEN_43___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43__BQ_GAIN_EVEN_43___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_43___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44 (0x005F50B0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__XLNA_GAIN_ODD_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__LNA_GAIN_ODD_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__GM_GAIN_ODD_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__TIA_GAIN_ODD_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__SLM_XLNA_ODD_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__BQ_GAIN_ODD_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__XLNA_GAIN_EVEN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__LNA_GAIN_EVEN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__GM_GAIN_EVEN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__TIA_GAIN_EVEN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__SLM_XLNA_EVEN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__BQ_GAIN_EVEN_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__XLNA_GAIN_ODD_44___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__XLNA_GAIN_ODD_44___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__LNA_GAIN_ODD_44___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__LNA_GAIN_ODD_44___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__GM_GAIN_ODD_44___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__GM_GAIN_ODD_44___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__TIA_GAIN_ODD_44___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__TIA_GAIN_ODD_44___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__SLM_XLNA_ODD_44___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__SLM_XLNA_ODD_44___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__BQ_GAIN_ODD_44___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__BQ_GAIN_ODD_44___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__XLNA_GAIN_EVEN_44___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__XLNA_GAIN_EVEN_44___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__LNA_GAIN_EVEN_44___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__LNA_GAIN_EVEN_44___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__GM_GAIN_EVEN_44___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__GM_GAIN_EVEN_44___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__TIA_GAIN_EVEN_44___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__TIA_GAIN_EVEN_44___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__SLM_XLNA_EVEN_44___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__SLM_XLNA_EVEN_44___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__BQ_GAIN_EVEN_44___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44__BQ_GAIN_EVEN_44___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_44___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45 (0x005F50B4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__XLNA_GAIN_ODD_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__LNA_GAIN_ODD_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__GM_GAIN_ODD_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__TIA_GAIN_ODD_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__SLM_XLNA_ODD_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__BQ_GAIN_ODD_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__XLNA_GAIN_EVEN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__LNA_GAIN_EVEN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__GM_GAIN_EVEN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__TIA_GAIN_EVEN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__SLM_XLNA_EVEN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__BQ_GAIN_EVEN_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__XLNA_GAIN_ODD_45___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__XLNA_GAIN_ODD_45___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__LNA_GAIN_ODD_45___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__LNA_GAIN_ODD_45___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__GM_GAIN_ODD_45___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__GM_GAIN_ODD_45___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__TIA_GAIN_ODD_45___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__TIA_GAIN_ODD_45___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__SLM_XLNA_ODD_45___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__SLM_XLNA_ODD_45___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__BQ_GAIN_ODD_45___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__BQ_GAIN_ODD_45___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__XLNA_GAIN_EVEN_45___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__XLNA_GAIN_EVEN_45___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__LNA_GAIN_EVEN_45___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__LNA_GAIN_EVEN_45___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__GM_GAIN_EVEN_45___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__GM_GAIN_EVEN_45___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__TIA_GAIN_EVEN_45___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__TIA_GAIN_EVEN_45___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__SLM_XLNA_EVEN_45___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__SLM_XLNA_EVEN_45___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__BQ_GAIN_EVEN_45___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45__BQ_GAIN_EVEN_45___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_45___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46 (0x005F50B8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__XLNA_GAIN_ODD_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__LNA_GAIN_ODD_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__GM_GAIN_ODD_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__TIA_GAIN_ODD_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__SLM_XLNA_ODD_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__BQ_GAIN_ODD_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__XLNA_GAIN_EVEN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__LNA_GAIN_EVEN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__GM_GAIN_EVEN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__TIA_GAIN_EVEN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__SLM_XLNA_EVEN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__BQ_GAIN_EVEN_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__XLNA_GAIN_ODD_46___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__XLNA_GAIN_ODD_46___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__LNA_GAIN_ODD_46___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__LNA_GAIN_ODD_46___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__GM_GAIN_ODD_46___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__GM_GAIN_ODD_46___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__TIA_GAIN_ODD_46___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__TIA_GAIN_ODD_46___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__SLM_XLNA_ODD_46___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__SLM_XLNA_ODD_46___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__BQ_GAIN_ODD_46___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__BQ_GAIN_ODD_46___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__XLNA_GAIN_EVEN_46___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__XLNA_GAIN_EVEN_46___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__LNA_GAIN_EVEN_46___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__LNA_GAIN_EVEN_46___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__GM_GAIN_EVEN_46___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__GM_GAIN_EVEN_46___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__TIA_GAIN_EVEN_46___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__TIA_GAIN_EVEN_46___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__SLM_XLNA_EVEN_46___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__SLM_XLNA_EVEN_46___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__BQ_GAIN_EVEN_46___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46__BQ_GAIN_EVEN_46___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_46___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47 (0x005F50BC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__XLNA_GAIN_ODD_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__LNA_GAIN_ODD_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__GM_GAIN_ODD_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__TIA_GAIN_ODD_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__SLM_XLNA_ODD_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__BQ_GAIN_ODD_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__XLNA_GAIN_EVEN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__LNA_GAIN_EVEN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__GM_GAIN_EVEN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__TIA_GAIN_EVEN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__SLM_XLNA_EVEN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__BQ_GAIN_EVEN_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__XLNA_GAIN_ODD_47___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__XLNA_GAIN_ODD_47___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__LNA_GAIN_ODD_47___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__LNA_GAIN_ODD_47___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__GM_GAIN_ODD_47___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__GM_GAIN_ODD_47___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__TIA_GAIN_ODD_47___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__TIA_GAIN_ODD_47___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__SLM_XLNA_ODD_47___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__SLM_XLNA_ODD_47___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__BQ_GAIN_ODD_47___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__BQ_GAIN_ODD_47___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__XLNA_GAIN_EVEN_47___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__XLNA_GAIN_EVEN_47___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__LNA_GAIN_EVEN_47___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__LNA_GAIN_EVEN_47___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__GM_GAIN_EVEN_47___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__GM_GAIN_EVEN_47___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__TIA_GAIN_EVEN_47___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__TIA_GAIN_EVEN_47___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__SLM_XLNA_EVEN_47___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__SLM_XLNA_EVEN_47___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__BQ_GAIN_EVEN_47___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47__BQ_GAIN_EVEN_47___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_47___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48 (0x005F50C0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__XLNA_GAIN_ODD_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__LNA_GAIN_ODD_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__GM_GAIN_ODD_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__TIA_GAIN_ODD_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__SLM_XLNA_ODD_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__BQ_GAIN_ODD_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__XLNA_GAIN_EVEN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__LNA_GAIN_EVEN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__GM_GAIN_EVEN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__TIA_GAIN_EVEN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__SLM_XLNA_EVEN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__BQ_GAIN_EVEN_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__XLNA_GAIN_ODD_48___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__XLNA_GAIN_ODD_48___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__LNA_GAIN_ODD_48___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__LNA_GAIN_ODD_48___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__GM_GAIN_ODD_48___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__GM_GAIN_ODD_48___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__TIA_GAIN_ODD_48___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__TIA_GAIN_ODD_48___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__SLM_XLNA_ODD_48___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__SLM_XLNA_ODD_48___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__BQ_GAIN_ODD_48___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__BQ_GAIN_ODD_48___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__XLNA_GAIN_EVEN_48___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__XLNA_GAIN_EVEN_48___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__LNA_GAIN_EVEN_48___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__LNA_GAIN_EVEN_48___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__GM_GAIN_EVEN_48___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__GM_GAIN_EVEN_48___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__TIA_GAIN_EVEN_48___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__TIA_GAIN_EVEN_48___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__SLM_XLNA_EVEN_48___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__SLM_XLNA_EVEN_48___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__BQ_GAIN_EVEN_48___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48__BQ_GAIN_EVEN_48___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_48___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49 (0x005F50C4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__XLNA_GAIN_ODD_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__LNA_GAIN_ODD_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__GM_GAIN_ODD_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__TIA_GAIN_ODD_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__SLM_XLNA_ODD_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__BQ_GAIN_ODD_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__XLNA_GAIN_EVEN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__LNA_GAIN_EVEN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__GM_GAIN_EVEN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__TIA_GAIN_EVEN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__SLM_XLNA_EVEN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__BQ_GAIN_EVEN_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__XLNA_GAIN_ODD_49___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__XLNA_GAIN_ODD_49___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__LNA_GAIN_ODD_49___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__LNA_GAIN_ODD_49___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__GM_GAIN_ODD_49___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__GM_GAIN_ODD_49___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__TIA_GAIN_ODD_49___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__TIA_GAIN_ODD_49___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__SLM_XLNA_ODD_49___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__SLM_XLNA_ODD_49___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__BQ_GAIN_ODD_49___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__BQ_GAIN_ODD_49___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__XLNA_GAIN_EVEN_49___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__XLNA_GAIN_EVEN_49___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__LNA_GAIN_EVEN_49___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__LNA_GAIN_EVEN_49___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__GM_GAIN_EVEN_49___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__GM_GAIN_EVEN_49___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__TIA_GAIN_EVEN_49___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__TIA_GAIN_EVEN_49___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__SLM_XLNA_EVEN_49___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__SLM_XLNA_EVEN_49___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__BQ_GAIN_EVEN_49___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49__BQ_GAIN_EVEN_49___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_49___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50 (0x005F50C8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__XLNA_GAIN_ODD_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__LNA_GAIN_ODD_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__GM_GAIN_ODD_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__TIA_GAIN_ODD_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__SLM_XLNA_ODD_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__BQ_GAIN_ODD_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__XLNA_GAIN_EVEN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__LNA_GAIN_EVEN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__GM_GAIN_EVEN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__TIA_GAIN_EVEN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__SLM_XLNA_EVEN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__BQ_GAIN_EVEN_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__XLNA_GAIN_ODD_50___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__XLNA_GAIN_ODD_50___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__LNA_GAIN_ODD_50___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__LNA_GAIN_ODD_50___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__GM_GAIN_ODD_50___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__GM_GAIN_ODD_50___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__TIA_GAIN_ODD_50___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__TIA_GAIN_ODD_50___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__SLM_XLNA_ODD_50___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__SLM_XLNA_ODD_50___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__BQ_GAIN_ODD_50___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__BQ_GAIN_ODD_50___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__XLNA_GAIN_EVEN_50___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__XLNA_GAIN_EVEN_50___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__LNA_GAIN_EVEN_50___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__LNA_GAIN_EVEN_50___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__GM_GAIN_EVEN_50___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__GM_GAIN_EVEN_50___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__TIA_GAIN_EVEN_50___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__TIA_GAIN_EVEN_50___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__SLM_XLNA_EVEN_50___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__SLM_XLNA_EVEN_50___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__BQ_GAIN_EVEN_50___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50__BQ_GAIN_EVEN_50___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_50___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51 (0x005F50CC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__XLNA_GAIN_ODD_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__LNA_GAIN_ODD_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__GM_GAIN_ODD_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__TIA_GAIN_ODD_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__SLM_XLNA_ODD_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__BQ_GAIN_ODD_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__XLNA_GAIN_EVEN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__LNA_GAIN_EVEN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__GM_GAIN_EVEN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__TIA_GAIN_EVEN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__SLM_XLNA_EVEN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__BQ_GAIN_EVEN_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__XLNA_GAIN_ODD_51___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__XLNA_GAIN_ODD_51___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__LNA_GAIN_ODD_51___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__LNA_GAIN_ODD_51___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__GM_GAIN_ODD_51___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__GM_GAIN_ODD_51___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__TIA_GAIN_ODD_51___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__TIA_GAIN_ODD_51___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__SLM_XLNA_ODD_51___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__SLM_XLNA_ODD_51___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__BQ_GAIN_ODD_51___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__BQ_GAIN_ODD_51___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__XLNA_GAIN_EVEN_51___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__XLNA_GAIN_EVEN_51___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__LNA_GAIN_EVEN_51___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__LNA_GAIN_EVEN_51___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__GM_GAIN_EVEN_51___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__GM_GAIN_EVEN_51___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__TIA_GAIN_EVEN_51___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__TIA_GAIN_EVEN_51___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__SLM_XLNA_EVEN_51___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__SLM_XLNA_EVEN_51___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__BQ_GAIN_EVEN_51___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51__BQ_GAIN_EVEN_51___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_51___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52 (0x005F50D0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__XLNA_GAIN_ODD_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__LNA_GAIN_ODD_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__GM_GAIN_ODD_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__TIA_GAIN_ODD_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__SLM_XLNA_ODD_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__BQ_GAIN_ODD_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__XLNA_GAIN_EVEN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__LNA_GAIN_EVEN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__GM_GAIN_EVEN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__TIA_GAIN_EVEN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__SLM_XLNA_EVEN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__BQ_GAIN_EVEN_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__XLNA_GAIN_ODD_52___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__XLNA_GAIN_ODD_52___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__LNA_GAIN_ODD_52___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__LNA_GAIN_ODD_52___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__GM_GAIN_ODD_52___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__GM_GAIN_ODD_52___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__TIA_GAIN_ODD_52___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__TIA_GAIN_ODD_52___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__SLM_XLNA_ODD_52___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__SLM_XLNA_ODD_52___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__BQ_GAIN_ODD_52___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__BQ_GAIN_ODD_52___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__XLNA_GAIN_EVEN_52___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__XLNA_GAIN_EVEN_52___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__LNA_GAIN_EVEN_52___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__LNA_GAIN_EVEN_52___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__GM_GAIN_EVEN_52___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__GM_GAIN_EVEN_52___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__TIA_GAIN_EVEN_52___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__TIA_GAIN_EVEN_52___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__SLM_XLNA_EVEN_52___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__SLM_XLNA_EVEN_52___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__BQ_GAIN_EVEN_52___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52__BQ_GAIN_EVEN_52___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_52___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53 (0x005F50D4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__XLNA_GAIN_ODD_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__LNA_GAIN_ODD_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__GM_GAIN_ODD_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__TIA_GAIN_ODD_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__SLM_XLNA_ODD_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__BQ_GAIN_ODD_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__XLNA_GAIN_EVEN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__LNA_GAIN_EVEN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__GM_GAIN_EVEN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__TIA_GAIN_EVEN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__SLM_XLNA_EVEN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__BQ_GAIN_EVEN_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__XLNA_GAIN_ODD_53___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__XLNA_GAIN_ODD_53___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__LNA_GAIN_ODD_53___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__LNA_GAIN_ODD_53___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__GM_GAIN_ODD_53___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__GM_GAIN_ODD_53___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__TIA_GAIN_ODD_53___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__TIA_GAIN_ODD_53___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__SLM_XLNA_ODD_53___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__SLM_XLNA_ODD_53___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__BQ_GAIN_ODD_53___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__BQ_GAIN_ODD_53___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__XLNA_GAIN_EVEN_53___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__XLNA_GAIN_EVEN_53___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__LNA_GAIN_EVEN_53___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__LNA_GAIN_EVEN_53___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__GM_GAIN_EVEN_53___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__GM_GAIN_EVEN_53___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__TIA_GAIN_EVEN_53___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__TIA_GAIN_EVEN_53___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__SLM_XLNA_EVEN_53___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__SLM_XLNA_EVEN_53___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__BQ_GAIN_EVEN_53___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53__BQ_GAIN_EVEN_53___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_53___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54 (0x005F50D8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__XLNA_GAIN_ODD_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__LNA_GAIN_ODD_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__GM_GAIN_ODD_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__TIA_GAIN_ODD_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__SLM_XLNA_ODD_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__BQ_GAIN_ODD_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__XLNA_GAIN_EVEN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__LNA_GAIN_EVEN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__GM_GAIN_EVEN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__TIA_GAIN_EVEN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__SLM_XLNA_EVEN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__BQ_GAIN_EVEN_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__XLNA_GAIN_ODD_54___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__XLNA_GAIN_ODD_54___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__LNA_GAIN_ODD_54___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__LNA_GAIN_ODD_54___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__GM_GAIN_ODD_54___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__GM_GAIN_ODD_54___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__TIA_GAIN_ODD_54___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__TIA_GAIN_ODD_54___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__SLM_XLNA_ODD_54___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__SLM_XLNA_ODD_54___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__BQ_GAIN_ODD_54___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__BQ_GAIN_ODD_54___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__XLNA_GAIN_EVEN_54___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__XLNA_GAIN_EVEN_54___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__LNA_GAIN_EVEN_54___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__LNA_GAIN_EVEN_54___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__GM_GAIN_EVEN_54___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__GM_GAIN_EVEN_54___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__TIA_GAIN_EVEN_54___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__TIA_GAIN_EVEN_54___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__SLM_XLNA_EVEN_54___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__SLM_XLNA_EVEN_54___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__BQ_GAIN_EVEN_54___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54__BQ_GAIN_EVEN_54___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_54___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55 (0x005F50DC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__XLNA_GAIN_ODD_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__LNA_GAIN_ODD_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__GM_GAIN_ODD_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__TIA_GAIN_ODD_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__SLM_XLNA_ODD_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__BQ_GAIN_ODD_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__XLNA_GAIN_EVEN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__LNA_GAIN_EVEN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__GM_GAIN_EVEN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__TIA_GAIN_EVEN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__SLM_XLNA_EVEN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__BQ_GAIN_EVEN_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__XLNA_GAIN_ODD_55___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__XLNA_GAIN_ODD_55___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__LNA_GAIN_ODD_55___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__LNA_GAIN_ODD_55___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__GM_GAIN_ODD_55___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__GM_GAIN_ODD_55___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__TIA_GAIN_ODD_55___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__TIA_GAIN_ODD_55___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__SLM_XLNA_ODD_55___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__SLM_XLNA_ODD_55___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__BQ_GAIN_ODD_55___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__BQ_GAIN_ODD_55___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__XLNA_GAIN_EVEN_55___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__XLNA_GAIN_EVEN_55___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__LNA_GAIN_EVEN_55___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__LNA_GAIN_EVEN_55___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__GM_GAIN_EVEN_55___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__GM_GAIN_EVEN_55___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__TIA_GAIN_EVEN_55___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__TIA_GAIN_EVEN_55___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__SLM_XLNA_EVEN_55___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__SLM_XLNA_EVEN_55___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__BQ_GAIN_EVEN_55___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55__BQ_GAIN_EVEN_55___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_55___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56 (0x005F50E0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__XLNA_GAIN_ODD_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__LNA_GAIN_ODD_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__GM_GAIN_ODD_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__TIA_GAIN_ODD_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__SLM_XLNA_ODD_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__BQ_GAIN_ODD_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__XLNA_GAIN_EVEN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__LNA_GAIN_EVEN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__GM_GAIN_EVEN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__TIA_GAIN_EVEN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__SLM_XLNA_EVEN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__BQ_GAIN_EVEN_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__XLNA_GAIN_ODD_56___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__XLNA_GAIN_ODD_56___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__LNA_GAIN_ODD_56___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__LNA_GAIN_ODD_56___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__GM_GAIN_ODD_56___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__GM_GAIN_ODD_56___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__TIA_GAIN_ODD_56___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__TIA_GAIN_ODD_56___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__SLM_XLNA_ODD_56___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__SLM_XLNA_ODD_56___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__BQ_GAIN_ODD_56___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__BQ_GAIN_ODD_56___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__XLNA_GAIN_EVEN_56___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__XLNA_GAIN_EVEN_56___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__LNA_GAIN_EVEN_56___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__LNA_GAIN_EVEN_56___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__GM_GAIN_EVEN_56___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__GM_GAIN_EVEN_56___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__TIA_GAIN_EVEN_56___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__TIA_GAIN_EVEN_56___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__SLM_XLNA_EVEN_56___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__SLM_XLNA_EVEN_56___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__BQ_GAIN_EVEN_56___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56__BQ_GAIN_EVEN_56___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_56___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57 (0x005F50E4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__XLNA_GAIN_ODD_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__LNA_GAIN_ODD_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__GM_GAIN_ODD_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__TIA_GAIN_ODD_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__SLM_XLNA_ODD_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__BQ_GAIN_ODD_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__XLNA_GAIN_EVEN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__LNA_GAIN_EVEN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__GM_GAIN_EVEN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__TIA_GAIN_EVEN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__SLM_XLNA_EVEN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__BQ_GAIN_EVEN_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__XLNA_GAIN_ODD_57___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__XLNA_GAIN_ODD_57___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__LNA_GAIN_ODD_57___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__LNA_GAIN_ODD_57___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__GM_GAIN_ODD_57___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__GM_GAIN_ODD_57___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__TIA_GAIN_ODD_57___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__TIA_GAIN_ODD_57___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__SLM_XLNA_ODD_57___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__SLM_XLNA_ODD_57___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__BQ_GAIN_ODD_57___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__BQ_GAIN_ODD_57___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__XLNA_GAIN_EVEN_57___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__XLNA_GAIN_EVEN_57___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__LNA_GAIN_EVEN_57___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__LNA_GAIN_EVEN_57___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__GM_GAIN_EVEN_57___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__GM_GAIN_EVEN_57___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__TIA_GAIN_EVEN_57___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__TIA_GAIN_EVEN_57___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__SLM_XLNA_EVEN_57___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__SLM_XLNA_EVEN_57___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__BQ_GAIN_EVEN_57___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57__BQ_GAIN_EVEN_57___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_57___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58 (0x005F50E8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__XLNA_GAIN_ODD_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__LNA_GAIN_ODD_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__GM_GAIN_ODD_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__TIA_GAIN_ODD_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__SLM_XLNA_ODD_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__BQ_GAIN_ODD_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__XLNA_GAIN_EVEN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__LNA_GAIN_EVEN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__GM_GAIN_EVEN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__TIA_GAIN_EVEN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__SLM_XLNA_EVEN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__BQ_GAIN_EVEN_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__XLNA_GAIN_ODD_58___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__XLNA_GAIN_ODD_58___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__LNA_GAIN_ODD_58___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__LNA_GAIN_ODD_58___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__GM_GAIN_ODD_58___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__GM_GAIN_ODD_58___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__TIA_GAIN_ODD_58___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__TIA_GAIN_ODD_58___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__SLM_XLNA_ODD_58___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__SLM_XLNA_ODD_58___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__BQ_GAIN_ODD_58___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__BQ_GAIN_ODD_58___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__XLNA_GAIN_EVEN_58___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__XLNA_GAIN_EVEN_58___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__LNA_GAIN_EVEN_58___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__LNA_GAIN_EVEN_58___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__GM_GAIN_EVEN_58___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__GM_GAIN_EVEN_58___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__TIA_GAIN_EVEN_58___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__TIA_GAIN_EVEN_58___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__SLM_XLNA_EVEN_58___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__SLM_XLNA_EVEN_58___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__BQ_GAIN_EVEN_58___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58__BQ_GAIN_EVEN_58___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_58___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59 (0x005F50EC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__XLNA_GAIN_ODD_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__LNA_GAIN_ODD_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__GM_GAIN_ODD_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__TIA_GAIN_ODD_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__SLM_XLNA_ODD_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__BQ_GAIN_ODD_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__XLNA_GAIN_EVEN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__LNA_GAIN_EVEN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__GM_GAIN_EVEN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__TIA_GAIN_EVEN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__SLM_XLNA_EVEN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__BQ_GAIN_EVEN_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__XLNA_GAIN_ODD_59___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__XLNA_GAIN_ODD_59___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__LNA_GAIN_ODD_59___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__LNA_GAIN_ODD_59___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__GM_GAIN_ODD_59___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__GM_GAIN_ODD_59___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__TIA_GAIN_ODD_59___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__TIA_GAIN_ODD_59___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__SLM_XLNA_ODD_59___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__SLM_XLNA_ODD_59___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__BQ_GAIN_ODD_59___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__BQ_GAIN_ODD_59___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__XLNA_GAIN_EVEN_59___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__XLNA_GAIN_EVEN_59___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__LNA_GAIN_EVEN_59___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__LNA_GAIN_EVEN_59___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__GM_GAIN_EVEN_59___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__GM_GAIN_EVEN_59___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__TIA_GAIN_EVEN_59___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__TIA_GAIN_EVEN_59___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__SLM_XLNA_EVEN_59___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__SLM_XLNA_EVEN_59___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__BQ_GAIN_EVEN_59___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59__BQ_GAIN_EVEN_59___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_59___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60 (0x005F50F0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__XLNA_GAIN_ODD_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__LNA_GAIN_ODD_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__GM_GAIN_ODD_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__TIA_GAIN_ODD_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__SLM_XLNA_ODD_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__BQ_GAIN_ODD_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__XLNA_GAIN_EVEN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__LNA_GAIN_EVEN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__GM_GAIN_EVEN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__TIA_GAIN_EVEN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__SLM_XLNA_EVEN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__BQ_GAIN_EVEN_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__XLNA_GAIN_ODD_60___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__XLNA_GAIN_ODD_60___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__LNA_GAIN_ODD_60___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__LNA_GAIN_ODD_60___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__GM_GAIN_ODD_60___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__GM_GAIN_ODD_60___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__TIA_GAIN_ODD_60___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__TIA_GAIN_ODD_60___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__SLM_XLNA_ODD_60___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__SLM_XLNA_ODD_60___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__BQ_GAIN_ODD_60___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__BQ_GAIN_ODD_60___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__XLNA_GAIN_EVEN_60___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__XLNA_GAIN_EVEN_60___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__LNA_GAIN_EVEN_60___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__LNA_GAIN_EVEN_60___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__GM_GAIN_EVEN_60___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__GM_GAIN_EVEN_60___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__TIA_GAIN_EVEN_60___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__TIA_GAIN_EVEN_60___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__SLM_XLNA_EVEN_60___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__SLM_XLNA_EVEN_60___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__BQ_GAIN_EVEN_60___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60__BQ_GAIN_EVEN_60___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_60___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61 (0x005F50F4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__XLNA_GAIN_ODD_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__LNA_GAIN_ODD_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__GM_GAIN_ODD_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__TIA_GAIN_ODD_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__SLM_XLNA_ODD_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__BQ_GAIN_ODD_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__XLNA_GAIN_EVEN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__LNA_GAIN_EVEN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__GM_GAIN_EVEN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__TIA_GAIN_EVEN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__SLM_XLNA_EVEN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__BQ_GAIN_EVEN_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__XLNA_GAIN_ODD_61___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__XLNA_GAIN_ODD_61___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__LNA_GAIN_ODD_61___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__LNA_GAIN_ODD_61___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__GM_GAIN_ODD_61___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__GM_GAIN_ODD_61___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__TIA_GAIN_ODD_61___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__TIA_GAIN_ODD_61___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__SLM_XLNA_ODD_61___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__SLM_XLNA_ODD_61___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__BQ_GAIN_ODD_61___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__BQ_GAIN_ODD_61___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__XLNA_GAIN_EVEN_61___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__XLNA_GAIN_EVEN_61___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__LNA_GAIN_EVEN_61___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__LNA_GAIN_EVEN_61___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__GM_GAIN_EVEN_61___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__GM_GAIN_EVEN_61___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__TIA_GAIN_EVEN_61___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__TIA_GAIN_EVEN_61___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__SLM_XLNA_EVEN_61___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__SLM_XLNA_EVEN_61___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__BQ_GAIN_EVEN_61___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61__BQ_GAIN_EVEN_61___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_61___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62 (0x005F50F8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__XLNA_GAIN_ODD_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__LNA_GAIN_ODD_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__GM_GAIN_ODD_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__TIA_GAIN_ODD_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__SLM_XLNA_ODD_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__BQ_GAIN_ODD_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__XLNA_GAIN_EVEN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__LNA_GAIN_EVEN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__GM_GAIN_EVEN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__TIA_GAIN_EVEN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__SLM_XLNA_EVEN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__BQ_GAIN_EVEN_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__XLNA_GAIN_ODD_62___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__XLNA_GAIN_ODD_62___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__LNA_GAIN_ODD_62___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__LNA_GAIN_ODD_62___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__GM_GAIN_ODD_62___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__GM_GAIN_ODD_62___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__TIA_GAIN_ODD_62___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__TIA_GAIN_ODD_62___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__SLM_XLNA_ODD_62___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__SLM_XLNA_ODD_62___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__BQ_GAIN_ODD_62___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__BQ_GAIN_ODD_62___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__XLNA_GAIN_EVEN_62___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__XLNA_GAIN_EVEN_62___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__LNA_GAIN_EVEN_62___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__LNA_GAIN_EVEN_62___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__GM_GAIN_EVEN_62___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__GM_GAIN_EVEN_62___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__TIA_GAIN_EVEN_62___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__TIA_GAIN_EVEN_62___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__SLM_XLNA_EVEN_62___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__SLM_XLNA_EVEN_62___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__BQ_GAIN_EVEN_62___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62__BQ_GAIN_EVEN_62___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_62___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63 (0x005F50FC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__XLNA_GAIN_ODD_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__LNA_GAIN_ODD_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__GM_GAIN_ODD_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__TIA_GAIN_ODD_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__SLM_XLNA_ODD_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__BQ_GAIN_ODD_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__XLNA_GAIN_EVEN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__LNA_GAIN_EVEN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__GM_GAIN_EVEN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__TIA_GAIN_EVEN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__SLM_XLNA_EVEN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__BQ_GAIN_EVEN_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__XLNA_GAIN_ODD_63___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__XLNA_GAIN_ODD_63___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__LNA_GAIN_ODD_63___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__LNA_GAIN_ODD_63___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__GM_GAIN_ODD_63___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__GM_GAIN_ODD_63___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__TIA_GAIN_ODD_63___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__TIA_GAIN_ODD_63___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__SLM_XLNA_ODD_63___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__SLM_XLNA_ODD_63___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__BQ_GAIN_ODD_63___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__BQ_GAIN_ODD_63___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__XLNA_GAIN_EVEN_63___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__XLNA_GAIN_EVEN_63___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__LNA_GAIN_EVEN_63___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__LNA_GAIN_EVEN_63___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__GM_GAIN_EVEN_63___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__GM_GAIN_EVEN_63___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__TIA_GAIN_EVEN_63___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__TIA_GAIN_EVEN_63___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__SLM_XLNA_EVEN_63___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__SLM_XLNA_EVEN_63___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__BQ_GAIN_EVEN_63___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63__BQ_GAIN_EVEN_63___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_63___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64 (0x005F5100) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__XLNA_GAIN_ODD_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__LNA_GAIN_ODD_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__GM_GAIN_ODD_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__TIA_GAIN_ODD_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__SLM_XLNA_ODD_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__BQ_GAIN_ODD_64___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__XLNA_GAIN_EVEN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__LNA_GAIN_EVEN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__GM_GAIN_EVEN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__TIA_GAIN_EVEN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__SLM_XLNA_EVEN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__BQ_GAIN_EVEN_64___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__XLNA_GAIN_ODD_64___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__XLNA_GAIN_ODD_64___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__LNA_GAIN_ODD_64___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__LNA_GAIN_ODD_64___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__GM_GAIN_ODD_64___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__GM_GAIN_ODD_64___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__TIA_GAIN_ODD_64___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__TIA_GAIN_ODD_64___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__SLM_XLNA_ODD_64___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__SLM_XLNA_ODD_64___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__BQ_GAIN_ODD_64___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__BQ_GAIN_ODD_64___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__XLNA_GAIN_EVEN_64___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__XLNA_GAIN_EVEN_64___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__LNA_GAIN_EVEN_64___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__LNA_GAIN_EVEN_64___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__GM_GAIN_EVEN_64___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__GM_GAIN_EVEN_64___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__TIA_GAIN_EVEN_64___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__TIA_GAIN_EVEN_64___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__SLM_XLNA_EVEN_64___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__SLM_XLNA_EVEN_64___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__BQ_GAIN_EVEN_64___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64__BQ_GAIN_EVEN_64___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_64___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65 (0x005F5104) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__XLNA_GAIN_ODD_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__LNA_GAIN_ODD_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__GM_GAIN_ODD_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__TIA_GAIN_ODD_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__SLM_XLNA_ODD_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__BQ_GAIN_ODD_65___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__XLNA_GAIN_EVEN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__LNA_GAIN_EVEN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__GM_GAIN_EVEN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__TIA_GAIN_EVEN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__SLM_XLNA_EVEN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__BQ_GAIN_EVEN_65___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__XLNA_GAIN_ODD_65___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__XLNA_GAIN_ODD_65___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__LNA_GAIN_ODD_65___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__LNA_GAIN_ODD_65___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__GM_GAIN_ODD_65___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__GM_GAIN_ODD_65___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__TIA_GAIN_ODD_65___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__TIA_GAIN_ODD_65___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__SLM_XLNA_ODD_65___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__SLM_XLNA_ODD_65___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__BQ_GAIN_ODD_65___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__BQ_GAIN_ODD_65___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__XLNA_GAIN_EVEN_65___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__XLNA_GAIN_EVEN_65___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__LNA_GAIN_EVEN_65___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__LNA_GAIN_EVEN_65___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__GM_GAIN_EVEN_65___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__GM_GAIN_EVEN_65___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__TIA_GAIN_EVEN_65___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__TIA_GAIN_EVEN_65___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__SLM_XLNA_EVEN_65___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__SLM_XLNA_EVEN_65___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__BQ_GAIN_EVEN_65___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65__BQ_GAIN_EVEN_65___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_65___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66 (0x005F5108) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__XLNA_GAIN_ODD_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__LNA_GAIN_ODD_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__GM_GAIN_ODD_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__TIA_GAIN_ODD_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__SLM_XLNA_ODD_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__BQ_GAIN_ODD_66___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__XLNA_GAIN_EVEN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__LNA_GAIN_EVEN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__GM_GAIN_EVEN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__TIA_GAIN_EVEN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__SLM_XLNA_EVEN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__BQ_GAIN_EVEN_66___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__XLNA_GAIN_ODD_66___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__XLNA_GAIN_ODD_66___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__LNA_GAIN_ODD_66___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__LNA_GAIN_ODD_66___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__GM_GAIN_ODD_66___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__GM_GAIN_ODD_66___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__TIA_GAIN_ODD_66___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__TIA_GAIN_ODD_66___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__SLM_XLNA_ODD_66___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__SLM_XLNA_ODD_66___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__BQ_GAIN_ODD_66___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__BQ_GAIN_ODD_66___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__XLNA_GAIN_EVEN_66___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__XLNA_GAIN_EVEN_66___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__LNA_GAIN_EVEN_66___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__LNA_GAIN_EVEN_66___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__GM_GAIN_EVEN_66___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__GM_GAIN_EVEN_66___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__TIA_GAIN_EVEN_66___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__TIA_GAIN_EVEN_66___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__SLM_XLNA_EVEN_66___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__SLM_XLNA_EVEN_66___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__BQ_GAIN_EVEN_66___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66__BQ_GAIN_EVEN_66___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_66___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67 (0x005F510C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__XLNA_GAIN_ODD_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__LNA_GAIN_ODD_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__GM_GAIN_ODD_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__TIA_GAIN_ODD_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__SLM_XLNA_ODD_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__BQ_GAIN_ODD_67___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__XLNA_GAIN_EVEN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__LNA_GAIN_EVEN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__GM_GAIN_EVEN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__TIA_GAIN_EVEN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__SLM_XLNA_EVEN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__BQ_GAIN_EVEN_67___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__XLNA_GAIN_ODD_67___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__XLNA_GAIN_ODD_67___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__LNA_GAIN_ODD_67___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__LNA_GAIN_ODD_67___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__GM_GAIN_ODD_67___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__GM_GAIN_ODD_67___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__TIA_GAIN_ODD_67___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__TIA_GAIN_ODD_67___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__SLM_XLNA_ODD_67___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__SLM_XLNA_ODD_67___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__BQ_GAIN_ODD_67___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__BQ_GAIN_ODD_67___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__XLNA_GAIN_EVEN_67___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__XLNA_GAIN_EVEN_67___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__LNA_GAIN_EVEN_67___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__LNA_GAIN_EVEN_67___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__GM_GAIN_EVEN_67___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__GM_GAIN_EVEN_67___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__TIA_GAIN_EVEN_67___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__TIA_GAIN_EVEN_67___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__SLM_XLNA_EVEN_67___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__SLM_XLNA_EVEN_67___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__BQ_GAIN_EVEN_67___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67__BQ_GAIN_EVEN_67___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_67___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68 (0x005F5110) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__XLNA_GAIN_ODD_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__LNA_GAIN_ODD_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__GM_GAIN_ODD_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__TIA_GAIN_ODD_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__SLM_XLNA_ODD_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__BQ_GAIN_ODD_68___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__XLNA_GAIN_EVEN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__LNA_GAIN_EVEN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__GM_GAIN_EVEN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__TIA_GAIN_EVEN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__SLM_XLNA_EVEN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__BQ_GAIN_EVEN_68___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__XLNA_GAIN_ODD_68___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__XLNA_GAIN_ODD_68___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__LNA_GAIN_ODD_68___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__LNA_GAIN_ODD_68___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__GM_GAIN_ODD_68___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__GM_GAIN_ODD_68___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__TIA_GAIN_ODD_68___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__TIA_GAIN_ODD_68___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__SLM_XLNA_ODD_68___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__SLM_XLNA_ODD_68___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__BQ_GAIN_ODD_68___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__BQ_GAIN_ODD_68___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__XLNA_GAIN_EVEN_68___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__XLNA_GAIN_EVEN_68___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__LNA_GAIN_EVEN_68___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__LNA_GAIN_EVEN_68___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__GM_GAIN_EVEN_68___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__GM_GAIN_EVEN_68___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__TIA_GAIN_EVEN_68___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__TIA_GAIN_EVEN_68___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__SLM_XLNA_EVEN_68___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__SLM_XLNA_EVEN_68___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__BQ_GAIN_EVEN_68___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68__BQ_GAIN_EVEN_68___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_68___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69 (0x005F5114) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__XLNA_GAIN_ODD_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__LNA_GAIN_ODD_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__GM_GAIN_ODD_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__TIA_GAIN_ODD_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__SLM_XLNA_ODD_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__BQ_GAIN_ODD_69___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__XLNA_GAIN_EVEN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__LNA_GAIN_EVEN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__GM_GAIN_EVEN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__TIA_GAIN_EVEN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__SLM_XLNA_EVEN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__BQ_GAIN_EVEN_69___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__XLNA_GAIN_ODD_69___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__XLNA_GAIN_ODD_69___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__LNA_GAIN_ODD_69___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__LNA_GAIN_ODD_69___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__GM_GAIN_ODD_69___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__GM_GAIN_ODD_69___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__TIA_GAIN_ODD_69___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__TIA_GAIN_ODD_69___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__SLM_XLNA_ODD_69___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__SLM_XLNA_ODD_69___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__BQ_GAIN_ODD_69___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__BQ_GAIN_ODD_69___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__XLNA_GAIN_EVEN_69___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__XLNA_GAIN_EVEN_69___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__LNA_GAIN_EVEN_69___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__LNA_GAIN_EVEN_69___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__GM_GAIN_EVEN_69___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__GM_GAIN_EVEN_69___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__TIA_GAIN_EVEN_69___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__TIA_GAIN_EVEN_69___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__SLM_XLNA_EVEN_69___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__SLM_XLNA_EVEN_69___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__BQ_GAIN_EVEN_69___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69__BQ_GAIN_EVEN_69___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_69___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70 (0x005F5118) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__XLNA_GAIN_ODD_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__LNA_GAIN_ODD_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__GM_GAIN_ODD_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__TIA_GAIN_ODD_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__SLM_XLNA_ODD_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__BQ_GAIN_ODD_70___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__XLNA_GAIN_EVEN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__LNA_GAIN_EVEN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__GM_GAIN_EVEN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__TIA_GAIN_EVEN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__SLM_XLNA_EVEN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__BQ_GAIN_EVEN_70___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__XLNA_GAIN_ODD_70___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__XLNA_GAIN_ODD_70___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__LNA_GAIN_ODD_70___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__LNA_GAIN_ODD_70___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__GM_GAIN_ODD_70___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__GM_GAIN_ODD_70___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__TIA_GAIN_ODD_70___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__TIA_GAIN_ODD_70___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__SLM_XLNA_ODD_70___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__SLM_XLNA_ODD_70___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__BQ_GAIN_ODD_70___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__BQ_GAIN_ODD_70___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__XLNA_GAIN_EVEN_70___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__XLNA_GAIN_EVEN_70___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__LNA_GAIN_EVEN_70___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__LNA_GAIN_EVEN_70___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__GM_GAIN_EVEN_70___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__GM_GAIN_EVEN_70___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__TIA_GAIN_EVEN_70___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__TIA_GAIN_EVEN_70___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__SLM_XLNA_EVEN_70___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__SLM_XLNA_EVEN_70___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__BQ_GAIN_EVEN_70___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70__BQ_GAIN_EVEN_70___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_70___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71 (0x005F511C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__XLNA_GAIN_ODD_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__LNA_GAIN_ODD_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__GM_GAIN_ODD_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__TIA_GAIN_ODD_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__SLM_XLNA_ODD_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__BQ_GAIN_ODD_71___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__XLNA_GAIN_EVEN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__LNA_GAIN_EVEN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__GM_GAIN_EVEN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__TIA_GAIN_EVEN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__SLM_XLNA_EVEN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__BQ_GAIN_EVEN_71___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__XLNA_GAIN_ODD_71___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__XLNA_GAIN_ODD_71___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__LNA_GAIN_ODD_71___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__LNA_GAIN_ODD_71___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__GM_GAIN_ODD_71___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__GM_GAIN_ODD_71___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__TIA_GAIN_ODD_71___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__TIA_GAIN_ODD_71___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__SLM_XLNA_ODD_71___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__SLM_XLNA_ODD_71___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__BQ_GAIN_ODD_71___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__BQ_GAIN_ODD_71___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__XLNA_GAIN_EVEN_71___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__XLNA_GAIN_EVEN_71___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__LNA_GAIN_EVEN_71___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__LNA_GAIN_EVEN_71___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__GM_GAIN_EVEN_71___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__GM_GAIN_EVEN_71___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__TIA_GAIN_EVEN_71___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__TIA_GAIN_EVEN_71___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__SLM_XLNA_EVEN_71___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__SLM_XLNA_EVEN_71___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__BQ_GAIN_EVEN_71___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71__BQ_GAIN_EVEN_71___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_71___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72 (0x005F5120) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__XLNA_GAIN_ODD_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__LNA_GAIN_ODD_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__GM_GAIN_ODD_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__TIA_GAIN_ODD_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__SLM_XLNA_ODD_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__BQ_GAIN_ODD_72___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__XLNA_GAIN_EVEN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__LNA_GAIN_EVEN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__GM_GAIN_EVEN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__TIA_GAIN_EVEN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__SLM_XLNA_EVEN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__BQ_GAIN_EVEN_72___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__XLNA_GAIN_ODD_72___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__XLNA_GAIN_ODD_72___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__LNA_GAIN_ODD_72___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__LNA_GAIN_ODD_72___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__GM_GAIN_ODD_72___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__GM_GAIN_ODD_72___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__TIA_GAIN_ODD_72___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__TIA_GAIN_ODD_72___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__SLM_XLNA_ODD_72___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__SLM_XLNA_ODD_72___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__BQ_GAIN_ODD_72___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__BQ_GAIN_ODD_72___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__XLNA_GAIN_EVEN_72___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__XLNA_GAIN_EVEN_72___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__LNA_GAIN_EVEN_72___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__LNA_GAIN_EVEN_72___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__GM_GAIN_EVEN_72___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__GM_GAIN_EVEN_72___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__TIA_GAIN_EVEN_72___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__TIA_GAIN_EVEN_72___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__SLM_XLNA_EVEN_72___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__SLM_XLNA_EVEN_72___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__BQ_GAIN_EVEN_72___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72__BQ_GAIN_EVEN_72___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_72___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73 (0x005F5124) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__XLNA_GAIN_ODD_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__LNA_GAIN_ODD_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__GM_GAIN_ODD_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__TIA_GAIN_ODD_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__SLM_XLNA_ODD_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__BQ_GAIN_ODD_73___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__XLNA_GAIN_EVEN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__LNA_GAIN_EVEN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__GM_GAIN_EVEN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__TIA_GAIN_EVEN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__SLM_XLNA_EVEN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__BQ_GAIN_EVEN_73___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__XLNA_GAIN_ODD_73___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__XLNA_GAIN_ODD_73___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__LNA_GAIN_ODD_73___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__LNA_GAIN_ODD_73___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__GM_GAIN_ODD_73___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__GM_GAIN_ODD_73___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__TIA_GAIN_ODD_73___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__TIA_GAIN_ODD_73___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__SLM_XLNA_ODD_73___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__SLM_XLNA_ODD_73___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__BQ_GAIN_ODD_73___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__BQ_GAIN_ODD_73___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__XLNA_GAIN_EVEN_73___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__XLNA_GAIN_EVEN_73___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__LNA_GAIN_EVEN_73___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__LNA_GAIN_EVEN_73___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__GM_GAIN_EVEN_73___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__GM_GAIN_EVEN_73___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__TIA_GAIN_EVEN_73___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__TIA_GAIN_EVEN_73___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__SLM_XLNA_EVEN_73___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__SLM_XLNA_EVEN_73___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__BQ_GAIN_EVEN_73___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73__BQ_GAIN_EVEN_73___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_73___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74 (0x005F5128) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__XLNA_GAIN_ODD_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__LNA_GAIN_ODD_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__GM_GAIN_ODD_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__TIA_GAIN_ODD_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__SLM_XLNA_ODD_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__BQ_GAIN_ODD_74___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__XLNA_GAIN_EVEN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__LNA_GAIN_EVEN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__GM_GAIN_EVEN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__TIA_GAIN_EVEN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__SLM_XLNA_EVEN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__BQ_GAIN_EVEN_74___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__XLNA_GAIN_ODD_74___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__XLNA_GAIN_ODD_74___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__LNA_GAIN_ODD_74___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__LNA_GAIN_ODD_74___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__GM_GAIN_ODD_74___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__GM_GAIN_ODD_74___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__TIA_GAIN_ODD_74___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__TIA_GAIN_ODD_74___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__SLM_XLNA_ODD_74___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__SLM_XLNA_ODD_74___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__BQ_GAIN_ODD_74___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__BQ_GAIN_ODD_74___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__XLNA_GAIN_EVEN_74___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__XLNA_GAIN_EVEN_74___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__LNA_GAIN_EVEN_74___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__LNA_GAIN_EVEN_74___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__GM_GAIN_EVEN_74___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__GM_GAIN_EVEN_74___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__TIA_GAIN_EVEN_74___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__TIA_GAIN_EVEN_74___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__SLM_XLNA_EVEN_74___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__SLM_XLNA_EVEN_74___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__BQ_GAIN_EVEN_74___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74__BQ_GAIN_EVEN_74___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_74___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75 (0x005F512C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__XLNA_GAIN_ODD_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__LNA_GAIN_ODD_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__GM_GAIN_ODD_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__TIA_GAIN_ODD_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__SLM_XLNA_ODD_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__BQ_GAIN_ODD_75___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__XLNA_GAIN_EVEN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__LNA_GAIN_EVEN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__GM_GAIN_EVEN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__TIA_GAIN_EVEN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__SLM_XLNA_EVEN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__BQ_GAIN_EVEN_75___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__XLNA_GAIN_ODD_75___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__XLNA_GAIN_ODD_75___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__LNA_GAIN_ODD_75___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__LNA_GAIN_ODD_75___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__GM_GAIN_ODD_75___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__GM_GAIN_ODD_75___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__TIA_GAIN_ODD_75___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__TIA_GAIN_ODD_75___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__SLM_XLNA_ODD_75___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__SLM_XLNA_ODD_75___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__BQ_GAIN_ODD_75___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__BQ_GAIN_ODD_75___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__XLNA_GAIN_EVEN_75___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__XLNA_GAIN_EVEN_75___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__LNA_GAIN_EVEN_75___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__LNA_GAIN_EVEN_75___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__GM_GAIN_EVEN_75___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__GM_GAIN_EVEN_75___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__TIA_GAIN_EVEN_75___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__TIA_GAIN_EVEN_75___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__SLM_XLNA_EVEN_75___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__SLM_XLNA_EVEN_75___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__BQ_GAIN_EVEN_75___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75__BQ_GAIN_EVEN_75___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_75___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76 (0x005F5130) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__XLNA_GAIN_ODD_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__LNA_GAIN_ODD_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__GM_GAIN_ODD_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__TIA_GAIN_ODD_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__SLM_XLNA_ODD_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__BQ_GAIN_ODD_76___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__XLNA_GAIN_EVEN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__LNA_GAIN_EVEN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__GM_GAIN_EVEN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__TIA_GAIN_EVEN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__SLM_XLNA_EVEN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__BQ_GAIN_EVEN_76___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__XLNA_GAIN_ODD_76___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__XLNA_GAIN_ODD_76___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__LNA_GAIN_ODD_76___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__LNA_GAIN_ODD_76___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__GM_GAIN_ODD_76___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__GM_GAIN_ODD_76___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__TIA_GAIN_ODD_76___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__TIA_GAIN_ODD_76___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__SLM_XLNA_ODD_76___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__SLM_XLNA_ODD_76___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__BQ_GAIN_ODD_76___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__BQ_GAIN_ODD_76___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__XLNA_GAIN_EVEN_76___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__XLNA_GAIN_EVEN_76___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__LNA_GAIN_EVEN_76___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__LNA_GAIN_EVEN_76___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__GM_GAIN_EVEN_76___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__GM_GAIN_EVEN_76___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__TIA_GAIN_EVEN_76___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__TIA_GAIN_EVEN_76___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__SLM_XLNA_EVEN_76___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__SLM_XLNA_EVEN_76___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__BQ_GAIN_EVEN_76___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76__BQ_GAIN_EVEN_76___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_76___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77 (0x005F5134) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__XLNA_GAIN_ODD_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__LNA_GAIN_ODD_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__GM_GAIN_ODD_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__TIA_GAIN_ODD_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__SLM_XLNA_ODD_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__BQ_GAIN_ODD_77___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__XLNA_GAIN_EVEN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__LNA_GAIN_EVEN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__GM_GAIN_EVEN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__TIA_GAIN_EVEN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__SLM_XLNA_EVEN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__BQ_GAIN_EVEN_77___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__XLNA_GAIN_ODD_77___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__XLNA_GAIN_ODD_77___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__LNA_GAIN_ODD_77___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__LNA_GAIN_ODD_77___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__GM_GAIN_ODD_77___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__GM_GAIN_ODD_77___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__TIA_GAIN_ODD_77___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__TIA_GAIN_ODD_77___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__SLM_XLNA_ODD_77___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__SLM_XLNA_ODD_77___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__BQ_GAIN_ODD_77___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__BQ_GAIN_ODD_77___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__XLNA_GAIN_EVEN_77___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__XLNA_GAIN_EVEN_77___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__LNA_GAIN_EVEN_77___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__LNA_GAIN_EVEN_77___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__GM_GAIN_EVEN_77___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__GM_GAIN_EVEN_77___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__TIA_GAIN_EVEN_77___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__TIA_GAIN_EVEN_77___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__SLM_XLNA_EVEN_77___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__SLM_XLNA_EVEN_77___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__BQ_GAIN_EVEN_77___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77__BQ_GAIN_EVEN_77___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_77___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78 (0x005F5138) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__XLNA_GAIN_ODD_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__LNA_GAIN_ODD_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__GM_GAIN_ODD_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__TIA_GAIN_ODD_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__SLM_XLNA_ODD_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__BQ_GAIN_ODD_78___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__XLNA_GAIN_EVEN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__LNA_GAIN_EVEN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__GM_GAIN_EVEN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__TIA_GAIN_EVEN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__SLM_XLNA_EVEN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__BQ_GAIN_EVEN_78___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__XLNA_GAIN_ODD_78___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__XLNA_GAIN_ODD_78___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__LNA_GAIN_ODD_78___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__LNA_GAIN_ODD_78___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__GM_GAIN_ODD_78___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__GM_GAIN_ODD_78___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__TIA_GAIN_ODD_78___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__TIA_GAIN_ODD_78___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__SLM_XLNA_ODD_78___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__SLM_XLNA_ODD_78___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__BQ_GAIN_ODD_78___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__BQ_GAIN_ODD_78___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__XLNA_GAIN_EVEN_78___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__XLNA_GAIN_EVEN_78___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__LNA_GAIN_EVEN_78___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__LNA_GAIN_EVEN_78___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__GM_GAIN_EVEN_78___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__GM_GAIN_EVEN_78___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__TIA_GAIN_EVEN_78___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__TIA_GAIN_EVEN_78___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__SLM_XLNA_EVEN_78___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__SLM_XLNA_EVEN_78___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__BQ_GAIN_EVEN_78___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78__BQ_GAIN_EVEN_78___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_78___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79 (0x005F513C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__XLNA_GAIN_ODD_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__LNA_GAIN_ODD_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__GM_GAIN_ODD_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__TIA_GAIN_ODD_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__SLM_XLNA_ODD_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__BQ_GAIN_ODD_79___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__XLNA_GAIN_EVEN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__LNA_GAIN_EVEN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__GM_GAIN_EVEN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__TIA_GAIN_EVEN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__SLM_XLNA_EVEN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__BQ_GAIN_EVEN_79___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__XLNA_GAIN_ODD_79___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__XLNA_GAIN_ODD_79___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__LNA_GAIN_ODD_79___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__LNA_GAIN_ODD_79___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__GM_GAIN_ODD_79___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__GM_GAIN_ODD_79___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__TIA_GAIN_ODD_79___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__TIA_GAIN_ODD_79___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__SLM_XLNA_ODD_79___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__SLM_XLNA_ODD_79___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__BQ_GAIN_ODD_79___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__BQ_GAIN_ODD_79___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__XLNA_GAIN_EVEN_79___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__XLNA_GAIN_EVEN_79___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__LNA_GAIN_EVEN_79___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__LNA_GAIN_EVEN_79___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__GM_GAIN_EVEN_79___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__GM_GAIN_EVEN_79___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__TIA_GAIN_EVEN_79___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__TIA_GAIN_EVEN_79___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__SLM_XLNA_EVEN_79___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__SLM_XLNA_EVEN_79___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__BQ_GAIN_EVEN_79___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79__BQ_GAIN_EVEN_79___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_79___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80 (0x005F5140) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__XLNA_GAIN_ODD_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__LNA_GAIN_ODD_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__GM_GAIN_ODD_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__TIA_GAIN_ODD_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__SLM_XLNA_ODD_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__BQ_GAIN_ODD_80___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__XLNA_GAIN_EVEN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__LNA_GAIN_EVEN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__GM_GAIN_EVEN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__TIA_GAIN_EVEN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__SLM_XLNA_EVEN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__BQ_GAIN_EVEN_80___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__XLNA_GAIN_ODD_80___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__XLNA_GAIN_ODD_80___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__LNA_GAIN_ODD_80___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__LNA_GAIN_ODD_80___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__GM_GAIN_ODD_80___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__GM_GAIN_ODD_80___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__TIA_GAIN_ODD_80___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__TIA_GAIN_ODD_80___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__SLM_XLNA_ODD_80___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__SLM_XLNA_ODD_80___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__BQ_GAIN_ODD_80___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__BQ_GAIN_ODD_80___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__XLNA_GAIN_EVEN_80___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__XLNA_GAIN_EVEN_80___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__LNA_GAIN_EVEN_80___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__LNA_GAIN_EVEN_80___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__GM_GAIN_EVEN_80___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__GM_GAIN_EVEN_80___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__TIA_GAIN_EVEN_80___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__TIA_GAIN_EVEN_80___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__SLM_XLNA_EVEN_80___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__SLM_XLNA_EVEN_80___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__BQ_GAIN_EVEN_80___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80__BQ_GAIN_EVEN_80___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_80___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81 (0x005F5144) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__XLNA_GAIN_ODD_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__LNA_GAIN_ODD_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__GM_GAIN_ODD_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__TIA_GAIN_ODD_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__SLM_XLNA_ODD_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__BQ_GAIN_ODD_81___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__XLNA_GAIN_EVEN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__LNA_GAIN_EVEN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__GM_GAIN_EVEN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__TIA_GAIN_EVEN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__SLM_XLNA_EVEN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__BQ_GAIN_EVEN_81___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__XLNA_GAIN_ODD_81___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__XLNA_GAIN_ODD_81___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__LNA_GAIN_ODD_81___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__LNA_GAIN_ODD_81___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__GM_GAIN_ODD_81___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__GM_GAIN_ODD_81___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__TIA_GAIN_ODD_81___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__TIA_GAIN_ODD_81___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__SLM_XLNA_ODD_81___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__SLM_XLNA_ODD_81___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__BQ_GAIN_ODD_81___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__BQ_GAIN_ODD_81___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__XLNA_GAIN_EVEN_81___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__XLNA_GAIN_EVEN_81___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__LNA_GAIN_EVEN_81___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__LNA_GAIN_EVEN_81___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__GM_GAIN_EVEN_81___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__GM_GAIN_EVEN_81___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__TIA_GAIN_EVEN_81___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__TIA_GAIN_EVEN_81___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__SLM_XLNA_EVEN_81___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__SLM_XLNA_EVEN_81___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__BQ_GAIN_EVEN_81___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81__BQ_GAIN_EVEN_81___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_81___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82 (0x005F5148) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__XLNA_GAIN_ODD_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__LNA_GAIN_ODD_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__GM_GAIN_ODD_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__TIA_GAIN_ODD_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__SLM_XLNA_ODD_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__BQ_GAIN_ODD_82___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__XLNA_GAIN_EVEN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__LNA_GAIN_EVEN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__GM_GAIN_EVEN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__TIA_GAIN_EVEN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__SLM_XLNA_EVEN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__BQ_GAIN_EVEN_82___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__XLNA_GAIN_ODD_82___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__XLNA_GAIN_ODD_82___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__LNA_GAIN_ODD_82___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__LNA_GAIN_ODD_82___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__GM_GAIN_ODD_82___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__GM_GAIN_ODD_82___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__TIA_GAIN_ODD_82___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__TIA_GAIN_ODD_82___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__SLM_XLNA_ODD_82___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__SLM_XLNA_ODD_82___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__BQ_GAIN_ODD_82___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__BQ_GAIN_ODD_82___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__XLNA_GAIN_EVEN_82___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__XLNA_GAIN_EVEN_82___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__LNA_GAIN_EVEN_82___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__LNA_GAIN_EVEN_82___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__GM_GAIN_EVEN_82___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__GM_GAIN_EVEN_82___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__TIA_GAIN_EVEN_82___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__TIA_GAIN_EVEN_82___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__SLM_XLNA_EVEN_82___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__SLM_XLNA_EVEN_82___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__BQ_GAIN_EVEN_82___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82__BQ_GAIN_EVEN_82___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_82___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83 (0x005F514C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__XLNA_GAIN_ODD_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__LNA_GAIN_ODD_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__GM_GAIN_ODD_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__TIA_GAIN_ODD_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__SLM_XLNA_ODD_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__BQ_GAIN_ODD_83___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__XLNA_GAIN_EVEN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__LNA_GAIN_EVEN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__GM_GAIN_EVEN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__TIA_GAIN_EVEN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__SLM_XLNA_EVEN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__BQ_GAIN_EVEN_83___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__XLNA_GAIN_ODD_83___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__XLNA_GAIN_ODD_83___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__LNA_GAIN_ODD_83___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__LNA_GAIN_ODD_83___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__GM_GAIN_ODD_83___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__GM_GAIN_ODD_83___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__TIA_GAIN_ODD_83___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__TIA_GAIN_ODD_83___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__SLM_XLNA_ODD_83___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__SLM_XLNA_ODD_83___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__BQ_GAIN_ODD_83___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__BQ_GAIN_ODD_83___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__XLNA_GAIN_EVEN_83___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__XLNA_GAIN_EVEN_83___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__LNA_GAIN_EVEN_83___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__LNA_GAIN_EVEN_83___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__GM_GAIN_EVEN_83___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__GM_GAIN_EVEN_83___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__TIA_GAIN_EVEN_83___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__TIA_GAIN_EVEN_83___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__SLM_XLNA_EVEN_83___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__SLM_XLNA_EVEN_83___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__BQ_GAIN_EVEN_83___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83__BQ_GAIN_EVEN_83___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_83___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84 (0x005F5150) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__XLNA_GAIN_ODD_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__LNA_GAIN_ODD_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__GM_GAIN_ODD_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__TIA_GAIN_ODD_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__SLM_XLNA_ODD_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__BQ_GAIN_ODD_84___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__XLNA_GAIN_EVEN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__LNA_GAIN_EVEN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__GM_GAIN_EVEN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__TIA_GAIN_EVEN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__SLM_XLNA_EVEN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__BQ_GAIN_EVEN_84___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__XLNA_GAIN_ODD_84___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__XLNA_GAIN_ODD_84___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__LNA_GAIN_ODD_84___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__LNA_GAIN_ODD_84___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__GM_GAIN_ODD_84___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__GM_GAIN_ODD_84___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__TIA_GAIN_ODD_84___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__TIA_GAIN_ODD_84___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__SLM_XLNA_ODD_84___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__SLM_XLNA_ODD_84___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__BQ_GAIN_ODD_84___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__BQ_GAIN_ODD_84___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__XLNA_GAIN_EVEN_84___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__XLNA_GAIN_EVEN_84___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__LNA_GAIN_EVEN_84___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__LNA_GAIN_EVEN_84___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__GM_GAIN_EVEN_84___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__GM_GAIN_EVEN_84___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__TIA_GAIN_EVEN_84___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__TIA_GAIN_EVEN_84___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__SLM_XLNA_EVEN_84___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__SLM_XLNA_EVEN_84___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__BQ_GAIN_EVEN_84___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84__BQ_GAIN_EVEN_84___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_84___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85 (0x005F5154) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__XLNA_GAIN_ODD_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__LNA_GAIN_ODD_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__GM_GAIN_ODD_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__TIA_GAIN_ODD_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__SLM_XLNA_ODD_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__BQ_GAIN_ODD_85___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__XLNA_GAIN_EVEN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__LNA_GAIN_EVEN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__GM_GAIN_EVEN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__TIA_GAIN_EVEN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__SLM_XLNA_EVEN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__BQ_GAIN_EVEN_85___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__XLNA_GAIN_ODD_85___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__XLNA_GAIN_ODD_85___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__LNA_GAIN_ODD_85___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__LNA_GAIN_ODD_85___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__GM_GAIN_ODD_85___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__GM_GAIN_ODD_85___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__TIA_GAIN_ODD_85___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__TIA_GAIN_ODD_85___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__SLM_XLNA_ODD_85___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__SLM_XLNA_ODD_85___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__BQ_GAIN_ODD_85___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__BQ_GAIN_ODD_85___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__XLNA_GAIN_EVEN_85___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__XLNA_GAIN_EVEN_85___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__LNA_GAIN_EVEN_85___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__LNA_GAIN_EVEN_85___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__GM_GAIN_EVEN_85___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__GM_GAIN_EVEN_85___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__TIA_GAIN_EVEN_85___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__TIA_GAIN_EVEN_85___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__SLM_XLNA_EVEN_85___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__SLM_XLNA_EVEN_85___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__BQ_GAIN_EVEN_85___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85__BQ_GAIN_EVEN_85___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_85___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86 (0x005F5158) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__XLNA_GAIN_ODD_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__LNA_GAIN_ODD_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__GM_GAIN_ODD_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__TIA_GAIN_ODD_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__SLM_XLNA_ODD_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__BQ_GAIN_ODD_86___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__XLNA_GAIN_EVEN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__LNA_GAIN_EVEN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__GM_GAIN_EVEN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__TIA_GAIN_EVEN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__SLM_XLNA_EVEN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__BQ_GAIN_EVEN_86___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__XLNA_GAIN_ODD_86___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__XLNA_GAIN_ODD_86___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__LNA_GAIN_ODD_86___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__LNA_GAIN_ODD_86___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__GM_GAIN_ODD_86___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__GM_GAIN_ODD_86___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__TIA_GAIN_ODD_86___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__TIA_GAIN_ODD_86___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__SLM_XLNA_ODD_86___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__SLM_XLNA_ODD_86___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__BQ_GAIN_ODD_86___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__BQ_GAIN_ODD_86___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__XLNA_GAIN_EVEN_86___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__XLNA_GAIN_EVEN_86___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__LNA_GAIN_EVEN_86___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__LNA_GAIN_EVEN_86___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__GM_GAIN_EVEN_86___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__GM_GAIN_EVEN_86___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__TIA_GAIN_EVEN_86___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__TIA_GAIN_EVEN_86___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__SLM_XLNA_EVEN_86___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__SLM_XLNA_EVEN_86___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__BQ_GAIN_EVEN_86___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86__BQ_GAIN_EVEN_86___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_86___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87 (0x005F515C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__XLNA_GAIN_ODD_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__LNA_GAIN_ODD_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__GM_GAIN_ODD_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__TIA_GAIN_ODD_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__SLM_XLNA_ODD_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__BQ_GAIN_ODD_87___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__XLNA_GAIN_EVEN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__LNA_GAIN_EVEN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__GM_GAIN_EVEN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__TIA_GAIN_EVEN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__SLM_XLNA_EVEN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__BQ_GAIN_EVEN_87___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__XLNA_GAIN_ODD_87___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__XLNA_GAIN_ODD_87___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__LNA_GAIN_ODD_87___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__LNA_GAIN_ODD_87___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__GM_GAIN_ODD_87___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__GM_GAIN_ODD_87___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__TIA_GAIN_ODD_87___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__TIA_GAIN_ODD_87___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__SLM_XLNA_ODD_87___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__SLM_XLNA_ODD_87___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__BQ_GAIN_ODD_87___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__BQ_GAIN_ODD_87___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__XLNA_GAIN_EVEN_87___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__XLNA_GAIN_EVEN_87___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__LNA_GAIN_EVEN_87___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__LNA_GAIN_EVEN_87___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__GM_GAIN_EVEN_87___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__GM_GAIN_EVEN_87___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__TIA_GAIN_EVEN_87___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__TIA_GAIN_EVEN_87___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__SLM_XLNA_EVEN_87___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__SLM_XLNA_EVEN_87___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__BQ_GAIN_EVEN_87___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87__BQ_GAIN_EVEN_87___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_87___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88 (0x005F5160) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__XLNA_GAIN_ODD_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__LNA_GAIN_ODD_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__GM_GAIN_ODD_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__TIA_GAIN_ODD_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__SLM_XLNA_ODD_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__BQ_GAIN_ODD_88___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__XLNA_GAIN_EVEN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__LNA_GAIN_EVEN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__GM_GAIN_EVEN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__TIA_GAIN_EVEN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__SLM_XLNA_EVEN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__BQ_GAIN_EVEN_88___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__XLNA_GAIN_ODD_88___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__XLNA_GAIN_ODD_88___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__LNA_GAIN_ODD_88___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__LNA_GAIN_ODD_88___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__GM_GAIN_ODD_88___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__GM_GAIN_ODD_88___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__TIA_GAIN_ODD_88___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__TIA_GAIN_ODD_88___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__SLM_XLNA_ODD_88___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__SLM_XLNA_ODD_88___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__BQ_GAIN_ODD_88___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__BQ_GAIN_ODD_88___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__XLNA_GAIN_EVEN_88___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__XLNA_GAIN_EVEN_88___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__LNA_GAIN_EVEN_88___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__LNA_GAIN_EVEN_88___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__GM_GAIN_EVEN_88___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__GM_GAIN_EVEN_88___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__TIA_GAIN_EVEN_88___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__TIA_GAIN_EVEN_88___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__SLM_XLNA_EVEN_88___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__SLM_XLNA_EVEN_88___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__BQ_GAIN_EVEN_88___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88__BQ_GAIN_EVEN_88___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_88___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89 (0x005F5164) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__XLNA_GAIN_ODD_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__LNA_GAIN_ODD_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__GM_GAIN_ODD_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__TIA_GAIN_ODD_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__SLM_XLNA_ODD_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__BQ_GAIN_ODD_89___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__XLNA_GAIN_EVEN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__LNA_GAIN_EVEN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__GM_GAIN_EVEN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__TIA_GAIN_EVEN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__SLM_XLNA_EVEN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__BQ_GAIN_EVEN_89___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__XLNA_GAIN_ODD_89___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__XLNA_GAIN_ODD_89___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__LNA_GAIN_ODD_89___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__LNA_GAIN_ODD_89___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__GM_GAIN_ODD_89___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__GM_GAIN_ODD_89___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__TIA_GAIN_ODD_89___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__TIA_GAIN_ODD_89___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__SLM_XLNA_ODD_89___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__SLM_XLNA_ODD_89___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__BQ_GAIN_ODD_89___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__BQ_GAIN_ODD_89___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__XLNA_GAIN_EVEN_89___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__XLNA_GAIN_EVEN_89___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__LNA_GAIN_EVEN_89___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__LNA_GAIN_EVEN_89___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__GM_GAIN_EVEN_89___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__GM_GAIN_EVEN_89___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__TIA_GAIN_EVEN_89___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__TIA_GAIN_EVEN_89___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__SLM_XLNA_EVEN_89___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__SLM_XLNA_EVEN_89___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__BQ_GAIN_EVEN_89___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89__BQ_GAIN_EVEN_89___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_89___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90 (0x005F5168) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__XLNA_GAIN_ODD_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__LNA_GAIN_ODD_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__GM_GAIN_ODD_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__TIA_GAIN_ODD_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__SLM_XLNA_ODD_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__BQ_GAIN_ODD_90___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__XLNA_GAIN_EVEN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__LNA_GAIN_EVEN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__GM_GAIN_EVEN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__TIA_GAIN_EVEN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__SLM_XLNA_EVEN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__BQ_GAIN_EVEN_90___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__XLNA_GAIN_ODD_90___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__XLNA_GAIN_ODD_90___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__LNA_GAIN_ODD_90___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__LNA_GAIN_ODD_90___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__GM_GAIN_ODD_90___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__GM_GAIN_ODD_90___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__TIA_GAIN_ODD_90___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__TIA_GAIN_ODD_90___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__SLM_XLNA_ODD_90___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__SLM_XLNA_ODD_90___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__BQ_GAIN_ODD_90___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__BQ_GAIN_ODD_90___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__XLNA_GAIN_EVEN_90___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__XLNA_GAIN_EVEN_90___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__LNA_GAIN_EVEN_90___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__LNA_GAIN_EVEN_90___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__GM_GAIN_EVEN_90___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__GM_GAIN_EVEN_90___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__TIA_GAIN_EVEN_90___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__TIA_GAIN_EVEN_90___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__SLM_XLNA_EVEN_90___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__SLM_XLNA_EVEN_90___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__BQ_GAIN_EVEN_90___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90__BQ_GAIN_EVEN_90___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_90___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91 (0x005F516C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__XLNA_GAIN_ODD_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__LNA_GAIN_ODD_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__GM_GAIN_ODD_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__TIA_GAIN_ODD_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__SLM_XLNA_ODD_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__BQ_GAIN_ODD_91___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__XLNA_GAIN_EVEN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__LNA_GAIN_EVEN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__GM_GAIN_EVEN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__TIA_GAIN_EVEN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__SLM_XLNA_EVEN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__BQ_GAIN_EVEN_91___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__XLNA_GAIN_ODD_91___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__XLNA_GAIN_ODD_91___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__LNA_GAIN_ODD_91___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__LNA_GAIN_ODD_91___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__GM_GAIN_ODD_91___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__GM_GAIN_ODD_91___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__TIA_GAIN_ODD_91___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__TIA_GAIN_ODD_91___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__SLM_XLNA_ODD_91___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__SLM_XLNA_ODD_91___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__BQ_GAIN_ODD_91___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__BQ_GAIN_ODD_91___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__XLNA_GAIN_EVEN_91___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__XLNA_GAIN_EVEN_91___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__LNA_GAIN_EVEN_91___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__LNA_GAIN_EVEN_91___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__GM_GAIN_EVEN_91___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__GM_GAIN_EVEN_91___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__TIA_GAIN_EVEN_91___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__TIA_GAIN_EVEN_91___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__SLM_XLNA_EVEN_91___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__SLM_XLNA_EVEN_91___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__BQ_GAIN_EVEN_91___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91__BQ_GAIN_EVEN_91___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_91___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92 (0x005F5170) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__XLNA_GAIN_ODD_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__LNA_GAIN_ODD_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__GM_GAIN_ODD_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__TIA_GAIN_ODD_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__SLM_XLNA_ODD_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__BQ_GAIN_ODD_92___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__XLNA_GAIN_EVEN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__LNA_GAIN_EVEN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__GM_GAIN_EVEN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__TIA_GAIN_EVEN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__SLM_XLNA_EVEN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__BQ_GAIN_EVEN_92___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__XLNA_GAIN_ODD_92___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__XLNA_GAIN_ODD_92___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__LNA_GAIN_ODD_92___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__LNA_GAIN_ODD_92___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__GM_GAIN_ODD_92___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__GM_GAIN_ODD_92___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__TIA_GAIN_ODD_92___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__TIA_GAIN_ODD_92___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__SLM_XLNA_ODD_92___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__SLM_XLNA_ODD_92___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__BQ_GAIN_ODD_92___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__BQ_GAIN_ODD_92___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__XLNA_GAIN_EVEN_92___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__XLNA_GAIN_EVEN_92___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__LNA_GAIN_EVEN_92___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__LNA_GAIN_EVEN_92___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__GM_GAIN_EVEN_92___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__GM_GAIN_EVEN_92___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__TIA_GAIN_EVEN_92___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__TIA_GAIN_EVEN_92___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__SLM_XLNA_EVEN_92___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__SLM_XLNA_EVEN_92___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__BQ_GAIN_EVEN_92___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92__BQ_GAIN_EVEN_92___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_92___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93 (0x005F5174) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__XLNA_GAIN_ODD_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__LNA_GAIN_ODD_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__GM_GAIN_ODD_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__TIA_GAIN_ODD_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__SLM_XLNA_ODD_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__BQ_GAIN_ODD_93___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__XLNA_GAIN_EVEN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__LNA_GAIN_EVEN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__GM_GAIN_EVEN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__TIA_GAIN_EVEN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__SLM_XLNA_EVEN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__BQ_GAIN_EVEN_93___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__XLNA_GAIN_ODD_93___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__XLNA_GAIN_ODD_93___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__LNA_GAIN_ODD_93___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__LNA_GAIN_ODD_93___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__GM_GAIN_ODD_93___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__GM_GAIN_ODD_93___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__TIA_GAIN_ODD_93___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__TIA_GAIN_ODD_93___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__SLM_XLNA_ODD_93___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__SLM_XLNA_ODD_93___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__BQ_GAIN_ODD_93___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__BQ_GAIN_ODD_93___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__XLNA_GAIN_EVEN_93___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__XLNA_GAIN_EVEN_93___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__LNA_GAIN_EVEN_93___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__LNA_GAIN_EVEN_93___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__GM_GAIN_EVEN_93___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__GM_GAIN_EVEN_93___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__TIA_GAIN_EVEN_93___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__TIA_GAIN_EVEN_93___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__SLM_XLNA_EVEN_93___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__SLM_XLNA_EVEN_93___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__BQ_GAIN_EVEN_93___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93__BQ_GAIN_EVEN_93___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_93___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94 (0x005F5178) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__XLNA_GAIN_ODD_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__LNA_GAIN_ODD_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__GM_GAIN_ODD_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__TIA_GAIN_ODD_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__SLM_XLNA_ODD_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__BQ_GAIN_ODD_94___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__XLNA_GAIN_EVEN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__LNA_GAIN_EVEN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__GM_GAIN_EVEN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__TIA_GAIN_EVEN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__SLM_XLNA_EVEN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__BQ_GAIN_EVEN_94___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__XLNA_GAIN_ODD_94___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__XLNA_GAIN_ODD_94___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__LNA_GAIN_ODD_94___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__LNA_GAIN_ODD_94___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__GM_GAIN_ODD_94___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__GM_GAIN_ODD_94___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__TIA_GAIN_ODD_94___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__TIA_GAIN_ODD_94___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__SLM_XLNA_ODD_94___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__SLM_XLNA_ODD_94___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__BQ_GAIN_ODD_94___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__BQ_GAIN_ODD_94___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__XLNA_GAIN_EVEN_94___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__XLNA_GAIN_EVEN_94___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__LNA_GAIN_EVEN_94___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__LNA_GAIN_EVEN_94___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__GM_GAIN_EVEN_94___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__GM_GAIN_EVEN_94___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__TIA_GAIN_EVEN_94___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__TIA_GAIN_EVEN_94___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__SLM_XLNA_EVEN_94___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__SLM_XLNA_EVEN_94___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__BQ_GAIN_EVEN_94___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94__BQ_GAIN_EVEN_94___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_94___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95 (0x005F517C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__XLNA_GAIN_ODD_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__LNA_GAIN_ODD_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__GM_GAIN_ODD_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__TIA_GAIN_ODD_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__SLM_XLNA_ODD_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__BQ_GAIN_ODD_95___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__XLNA_GAIN_EVEN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__LNA_GAIN_EVEN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__GM_GAIN_EVEN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__TIA_GAIN_EVEN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__SLM_XLNA_EVEN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__BQ_GAIN_EVEN_95___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__XLNA_GAIN_ODD_95___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__XLNA_GAIN_ODD_95___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__LNA_GAIN_ODD_95___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__LNA_GAIN_ODD_95___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__GM_GAIN_ODD_95___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__GM_GAIN_ODD_95___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__TIA_GAIN_ODD_95___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__TIA_GAIN_ODD_95___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__SLM_XLNA_ODD_95___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__SLM_XLNA_ODD_95___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__BQ_GAIN_ODD_95___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__BQ_GAIN_ODD_95___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__XLNA_GAIN_EVEN_95___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__XLNA_GAIN_EVEN_95___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__LNA_GAIN_EVEN_95___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__LNA_GAIN_EVEN_95___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__GM_GAIN_EVEN_95___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__GM_GAIN_EVEN_95___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__TIA_GAIN_EVEN_95___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__TIA_GAIN_EVEN_95___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__SLM_XLNA_EVEN_95___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__SLM_XLNA_EVEN_95___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__BQ_GAIN_EVEN_95___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95__BQ_GAIN_EVEN_95___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_95___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96 (0x005F5180) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__XLNA_GAIN_ODD_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__LNA_GAIN_ODD_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__GM_GAIN_ODD_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__TIA_GAIN_ODD_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__SLM_XLNA_ODD_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__BQ_GAIN_ODD_96___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__XLNA_GAIN_EVEN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__LNA_GAIN_EVEN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__GM_GAIN_EVEN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__TIA_GAIN_EVEN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__SLM_XLNA_EVEN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__BQ_GAIN_EVEN_96___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__XLNA_GAIN_ODD_96___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__XLNA_GAIN_ODD_96___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__LNA_GAIN_ODD_96___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__LNA_GAIN_ODD_96___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__GM_GAIN_ODD_96___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__GM_GAIN_ODD_96___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__TIA_GAIN_ODD_96___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__TIA_GAIN_ODD_96___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__SLM_XLNA_ODD_96___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__SLM_XLNA_ODD_96___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__BQ_GAIN_ODD_96___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__BQ_GAIN_ODD_96___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__XLNA_GAIN_EVEN_96___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__XLNA_GAIN_EVEN_96___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__LNA_GAIN_EVEN_96___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__LNA_GAIN_EVEN_96___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__GM_GAIN_EVEN_96___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__GM_GAIN_EVEN_96___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__TIA_GAIN_EVEN_96___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__TIA_GAIN_EVEN_96___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__SLM_XLNA_EVEN_96___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__SLM_XLNA_EVEN_96___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__BQ_GAIN_EVEN_96___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96__BQ_GAIN_EVEN_96___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_96___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97 (0x005F5184) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__XLNA_GAIN_ODD_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__LNA_GAIN_ODD_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__GM_GAIN_ODD_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__TIA_GAIN_ODD_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__SLM_XLNA_ODD_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__BQ_GAIN_ODD_97___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__XLNA_GAIN_EVEN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__LNA_GAIN_EVEN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__GM_GAIN_EVEN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__TIA_GAIN_EVEN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__SLM_XLNA_EVEN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__BQ_GAIN_EVEN_97___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__XLNA_GAIN_ODD_97___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__XLNA_GAIN_ODD_97___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__LNA_GAIN_ODD_97___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__LNA_GAIN_ODD_97___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__GM_GAIN_ODD_97___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__GM_GAIN_ODD_97___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__TIA_GAIN_ODD_97___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__TIA_GAIN_ODD_97___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__SLM_XLNA_ODD_97___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__SLM_XLNA_ODD_97___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__BQ_GAIN_ODD_97___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__BQ_GAIN_ODD_97___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__XLNA_GAIN_EVEN_97___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__XLNA_GAIN_EVEN_97___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__LNA_GAIN_EVEN_97___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__LNA_GAIN_EVEN_97___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__GM_GAIN_EVEN_97___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__GM_GAIN_EVEN_97___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__TIA_GAIN_EVEN_97___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__TIA_GAIN_EVEN_97___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__SLM_XLNA_EVEN_97___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__SLM_XLNA_EVEN_97___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__BQ_GAIN_EVEN_97___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97__BQ_GAIN_EVEN_97___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_97___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98 (0x005F5188) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__XLNA_GAIN_ODD_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__LNA_GAIN_ODD_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__GM_GAIN_ODD_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__TIA_GAIN_ODD_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__SLM_XLNA_ODD_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__BQ_GAIN_ODD_98___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__XLNA_GAIN_EVEN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__LNA_GAIN_EVEN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__GM_GAIN_EVEN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__TIA_GAIN_EVEN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__SLM_XLNA_EVEN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__BQ_GAIN_EVEN_98___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__XLNA_GAIN_ODD_98___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__XLNA_GAIN_ODD_98___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__LNA_GAIN_ODD_98___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__LNA_GAIN_ODD_98___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__GM_GAIN_ODD_98___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__GM_GAIN_ODD_98___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__TIA_GAIN_ODD_98___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__TIA_GAIN_ODD_98___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__SLM_XLNA_ODD_98___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__SLM_XLNA_ODD_98___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__BQ_GAIN_ODD_98___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__BQ_GAIN_ODD_98___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__XLNA_GAIN_EVEN_98___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__XLNA_GAIN_EVEN_98___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__LNA_GAIN_EVEN_98___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__LNA_GAIN_EVEN_98___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__GM_GAIN_EVEN_98___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__GM_GAIN_EVEN_98___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__TIA_GAIN_EVEN_98___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__TIA_GAIN_EVEN_98___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__SLM_XLNA_EVEN_98___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__SLM_XLNA_EVEN_98___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__BQ_GAIN_EVEN_98___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98__BQ_GAIN_EVEN_98___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_98___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99 (0x005F518C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__XLNA_GAIN_ODD_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__LNA_GAIN_ODD_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__GM_GAIN_ODD_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__TIA_GAIN_ODD_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__SLM_XLNA_ODD_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__BQ_GAIN_ODD_99___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__XLNA_GAIN_EVEN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__LNA_GAIN_EVEN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__GM_GAIN_EVEN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__TIA_GAIN_EVEN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__SLM_XLNA_EVEN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__BQ_GAIN_EVEN_99___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__XLNA_GAIN_ODD_99___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__XLNA_GAIN_ODD_99___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__LNA_GAIN_ODD_99___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__LNA_GAIN_ODD_99___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__GM_GAIN_ODD_99___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__GM_GAIN_ODD_99___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__TIA_GAIN_ODD_99___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__TIA_GAIN_ODD_99___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__SLM_XLNA_ODD_99___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__SLM_XLNA_ODD_99___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__BQ_GAIN_ODD_99___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__BQ_GAIN_ODD_99___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__XLNA_GAIN_EVEN_99___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__XLNA_GAIN_EVEN_99___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__LNA_GAIN_EVEN_99___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__LNA_GAIN_EVEN_99___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__GM_GAIN_EVEN_99___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__GM_GAIN_EVEN_99___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__TIA_GAIN_EVEN_99___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__TIA_GAIN_EVEN_99___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__SLM_XLNA_EVEN_99___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__SLM_XLNA_EVEN_99___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__BQ_GAIN_EVEN_99___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99__BQ_GAIN_EVEN_99___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_99___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100 (0x005F5190) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__XLNA_GAIN_ODD_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__LNA_GAIN_ODD_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__GM_GAIN_ODD_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__TIA_GAIN_ODD_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__SLM_XLNA_ODD_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__BQ_GAIN_ODD_100___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__XLNA_GAIN_EVEN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__LNA_GAIN_EVEN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__GM_GAIN_EVEN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__TIA_GAIN_EVEN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__SLM_XLNA_EVEN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__BQ_GAIN_EVEN_100___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__XLNA_GAIN_ODD_100___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__XLNA_GAIN_ODD_100___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__LNA_GAIN_ODD_100___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__LNA_GAIN_ODD_100___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__GM_GAIN_ODD_100___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__GM_GAIN_ODD_100___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__TIA_GAIN_ODD_100___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__TIA_GAIN_ODD_100___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__SLM_XLNA_ODD_100___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__SLM_XLNA_ODD_100___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__BQ_GAIN_ODD_100___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__BQ_GAIN_ODD_100___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__XLNA_GAIN_EVEN_100___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__XLNA_GAIN_EVEN_100___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__LNA_GAIN_EVEN_100___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__LNA_GAIN_EVEN_100___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__GM_GAIN_EVEN_100___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__GM_GAIN_EVEN_100___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__TIA_GAIN_EVEN_100___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__TIA_GAIN_EVEN_100___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__SLM_XLNA_EVEN_100___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__SLM_XLNA_EVEN_100___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__BQ_GAIN_EVEN_100___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100__BQ_GAIN_EVEN_100___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_100___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101 (0x005F5194) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__XLNA_GAIN_ODD_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__LNA_GAIN_ODD_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__GM_GAIN_ODD_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__TIA_GAIN_ODD_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__SLM_XLNA_ODD_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__BQ_GAIN_ODD_101___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__XLNA_GAIN_EVEN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__LNA_GAIN_EVEN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__GM_GAIN_EVEN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__TIA_GAIN_EVEN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__SLM_XLNA_EVEN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__BQ_GAIN_EVEN_101___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__XLNA_GAIN_ODD_101___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__XLNA_GAIN_ODD_101___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__LNA_GAIN_ODD_101___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__LNA_GAIN_ODD_101___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__GM_GAIN_ODD_101___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__GM_GAIN_ODD_101___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__TIA_GAIN_ODD_101___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__TIA_GAIN_ODD_101___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__SLM_XLNA_ODD_101___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__SLM_XLNA_ODD_101___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__BQ_GAIN_ODD_101___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__BQ_GAIN_ODD_101___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__XLNA_GAIN_EVEN_101___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__XLNA_GAIN_EVEN_101___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__LNA_GAIN_EVEN_101___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__LNA_GAIN_EVEN_101___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__GM_GAIN_EVEN_101___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__GM_GAIN_EVEN_101___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__TIA_GAIN_EVEN_101___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__TIA_GAIN_EVEN_101___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__SLM_XLNA_EVEN_101___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__SLM_XLNA_EVEN_101___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__BQ_GAIN_EVEN_101___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101__BQ_GAIN_EVEN_101___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_101___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102 (0x005F5198) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__XLNA_GAIN_ODD_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__LNA_GAIN_ODD_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__GM_GAIN_ODD_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__TIA_GAIN_ODD_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__SLM_XLNA_ODD_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__BQ_GAIN_ODD_102___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__XLNA_GAIN_EVEN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__LNA_GAIN_EVEN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__GM_GAIN_EVEN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__TIA_GAIN_EVEN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__SLM_XLNA_EVEN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__BQ_GAIN_EVEN_102___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__XLNA_GAIN_ODD_102___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__XLNA_GAIN_ODD_102___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__LNA_GAIN_ODD_102___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__LNA_GAIN_ODD_102___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__GM_GAIN_ODD_102___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__GM_GAIN_ODD_102___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__TIA_GAIN_ODD_102___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__TIA_GAIN_ODD_102___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__SLM_XLNA_ODD_102___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__SLM_XLNA_ODD_102___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__BQ_GAIN_ODD_102___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__BQ_GAIN_ODD_102___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__XLNA_GAIN_EVEN_102___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__XLNA_GAIN_EVEN_102___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__LNA_GAIN_EVEN_102___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__LNA_GAIN_EVEN_102___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__GM_GAIN_EVEN_102___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__GM_GAIN_EVEN_102___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__TIA_GAIN_EVEN_102___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__TIA_GAIN_EVEN_102___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__SLM_XLNA_EVEN_102___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__SLM_XLNA_EVEN_102___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__BQ_GAIN_EVEN_102___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102__BQ_GAIN_EVEN_102___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_102___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103 (0x005F519C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__XLNA_GAIN_ODD_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__LNA_GAIN_ODD_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__GM_GAIN_ODD_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__TIA_GAIN_ODD_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__SLM_XLNA_ODD_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__BQ_GAIN_ODD_103___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__XLNA_GAIN_EVEN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__LNA_GAIN_EVEN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__GM_GAIN_EVEN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__TIA_GAIN_EVEN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__SLM_XLNA_EVEN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__BQ_GAIN_EVEN_103___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__XLNA_GAIN_ODD_103___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__XLNA_GAIN_ODD_103___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__LNA_GAIN_ODD_103___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__LNA_GAIN_ODD_103___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__GM_GAIN_ODD_103___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__GM_GAIN_ODD_103___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__TIA_GAIN_ODD_103___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__TIA_GAIN_ODD_103___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__SLM_XLNA_ODD_103___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__SLM_XLNA_ODD_103___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__BQ_GAIN_ODD_103___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__BQ_GAIN_ODD_103___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__XLNA_GAIN_EVEN_103___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__XLNA_GAIN_EVEN_103___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__LNA_GAIN_EVEN_103___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__LNA_GAIN_EVEN_103___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__GM_GAIN_EVEN_103___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__GM_GAIN_EVEN_103___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__TIA_GAIN_EVEN_103___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__TIA_GAIN_EVEN_103___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__SLM_XLNA_EVEN_103___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__SLM_XLNA_EVEN_103___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__BQ_GAIN_EVEN_103___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103__BQ_GAIN_EVEN_103___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_103___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104 (0x005F51A0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__XLNA_GAIN_ODD_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__LNA_GAIN_ODD_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__GM_GAIN_ODD_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__TIA_GAIN_ODD_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__SLM_XLNA_ODD_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__BQ_GAIN_ODD_104___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__XLNA_GAIN_EVEN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__LNA_GAIN_EVEN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__GM_GAIN_EVEN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__TIA_GAIN_EVEN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__SLM_XLNA_EVEN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__BQ_GAIN_EVEN_104___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__XLNA_GAIN_ODD_104___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__XLNA_GAIN_ODD_104___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__LNA_GAIN_ODD_104___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__LNA_GAIN_ODD_104___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__GM_GAIN_ODD_104___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__GM_GAIN_ODD_104___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__TIA_GAIN_ODD_104___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__TIA_GAIN_ODD_104___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__SLM_XLNA_ODD_104___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__SLM_XLNA_ODD_104___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__BQ_GAIN_ODD_104___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__BQ_GAIN_ODD_104___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__XLNA_GAIN_EVEN_104___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__XLNA_GAIN_EVEN_104___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__LNA_GAIN_EVEN_104___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__LNA_GAIN_EVEN_104___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__GM_GAIN_EVEN_104___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__GM_GAIN_EVEN_104___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__TIA_GAIN_EVEN_104___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__TIA_GAIN_EVEN_104___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__SLM_XLNA_EVEN_104___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__SLM_XLNA_EVEN_104___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__BQ_GAIN_EVEN_104___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104__BQ_GAIN_EVEN_104___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_104___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105 (0x005F51A4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__XLNA_GAIN_ODD_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__LNA_GAIN_ODD_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__GM_GAIN_ODD_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__TIA_GAIN_ODD_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__SLM_XLNA_ODD_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__BQ_GAIN_ODD_105___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__XLNA_GAIN_EVEN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__LNA_GAIN_EVEN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__GM_GAIN_EVEN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__TIA_GAIN_EVEN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__SLM_XLNA_EVEN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__BQ_GAIN_EVEN_105___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__XLNA_GAIN_ODD_105___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__XLNA_GAIN_ODD_105___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__LNA_GAIN_ODD_105___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__LNA_GAIN_ODD_105___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__GM_GAIN_ODD_105___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__GM_GAIN_ODD_105___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__TIA_GAIN_ODD_105___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__TIA_GAIN_ODD_105___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__SLM_XLNA_ODD_105___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__SLM_XLNA_ODD_105___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__BQ_GAIN_ODD_105___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__BQ_GAIN_ODD_105___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__XLNA_GAIN_EVEN_105___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__XLNA_GAIN_EVEN_105___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__LNA_GAIN_EVEN_105___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__LNA_GAIN_EVEN_105___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__GM_GAIN_EVEN_105___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__GM_GAIN_EVEN_105___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__TIA_GAIN_EVEN_105___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__TIA_GAIN_EVEN_105___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__SLM_XLNA_EVEN_105___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__SLM_XLNA_EVEN_105___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__BQ_GAIN_EVEN_105___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105__BQ_GAIN_EVEN_105___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_105___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106 (0x005F51A8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__XLNA_GAIN_ODD_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__LNA_GAIN_ODD_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__GM_GAIN_ODD_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__TIA_GAIN_ODD_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__SLM_XLNA_ODD_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__BQ_GAIN_ODD_106___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__XLNA_GAIN_EVEN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__LNA_GAIN_EVEN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__GM_GAIN_EVEN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__TIA_GAIN_EVEN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__SLM_XLNA_EVEN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__BQ_GAIN_EVEN_106___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__XLNA_GAIN_ODD_106___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__XLNA_GAIN_ODD_106___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__LNA_GAIN_ODD_106___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__LNA_GAIN_ODD_106___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__GM_GAIN_ODD_106___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__GM_GAIN_ODD_106___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__TIA_GAIN_ODD_106___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__TIA_GAIN_ODD_106___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__SLM_XLNA_ODD_106___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__SLM_XLNA_ODD_106___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__BQ_GAIN_ODD_106___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__BQ_GAIN_ODD_106___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__XLNA_GAIN_EVEN_106___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__XLNA_GAIN_EVEN_106___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__LNA_GAIN_EVEN_106___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__LNA_GAIN_EVEN_106___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__GM_GAIN_EVEN_106___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__GM_GAIN_EVEN_106___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__TIA_GAIN_EVEN_106___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__TIA_GAIN_EVEN_106___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__SLM_XLNA_EVEN_106___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__SLM_XLNA_EVEN_106___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__BQ_GAIN_EVEN_106___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106__BQ_GAIN_EVEN_106___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_106___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107 (0x005F51AC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__XLNA_GAIN_ODD_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__LNA_GAIN_ODD_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__GM_GAIN_ODD_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__TIA_GAIN_ODD_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__SLM_XLNA_ODD_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__BQ_GAIN_ODD_107___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__XLNA_GAIN_EVEN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__LNA_GAIN_EVEN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__GM_GAIN_EVEN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__TIA_GAIN_EVEN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__SLM_XLNA_EVEN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__BQ_GAIN_EVEN_107___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__XLNA_GAIN_ODD_107___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__XLNA_GAIN_ODD_107___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__LNA_GAIN_ODD_107___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__LNA_GAIN_ODD_107___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__GM_GAIN_ODD_107___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__GM_GAIN_ODD_107___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__TIA_GAIN_ODD_107___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__TIA_GAIN_ODD_107___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__SLM_XLNA_ODD_107___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__SLM_XLNA_ODD_107___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__BQ_GAIN_ODD_107___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__BQ_GAIN_ODD_107___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__XLNA_GAIN_EVEN_107___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__XLNA_GAIN_EVEN_107___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__LNA_GAIN_EVEN_107___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__LNA_GAIN_EVEN_107___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__GM_GAIN_EVEN_107___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__GM_GAIN_EVEN_107___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__TIA_GAIN_EVEN_107___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__TIA_GAIN_EVEN_107___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__SLM_XLNA_EVEN_107___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__SLM_XLNA_EVEN_107___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__BQ_GAIN_EVEN_107___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107__BQ_GAIN_EVEN_107___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_107___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108 (0x005F51B0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__XLNA_GAIN_ODD_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__LNA_GAIN_ODD_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__GM_GAIN_ODD_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__TIA_GAIN_ODD_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__SLM_XLNA_ODD_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__BQ_GAIN_ODD_108___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__XLNA_GAIN_EVEN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__LNA_GAIN_EVEN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__GM_GAIN_EVEN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__TIA_GAIN_EVEN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__SLM_XLNA_EVEN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__BQ_GAIN_EVEN_108___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__XLNA_GAIN_ODD_108___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__XLNA_GAIN_ODD_108___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__LNA_GAIN_ODD_108___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__LNA_GAIN_ODD_108___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__GM_GAIN_ODD_108___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__GM_GAIN_ODD_108___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__TIA_GAIN_ODD_108___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__TIA_GAIN_ODD_108___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__SLM_XLNA_ODD_108___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__SLM_XLNA_ODD_108___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__BQ_GAIN_ODD_108___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__BQ_GAIN_ODD_108___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__XLNA_GAIN_EVEN_108___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__XLNA_GAIN_EVEN_108___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__LNA_GAIN_EVEN_108___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__LNA_GAIN_EVEN_108___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__GM_GAIN_EVEN_108___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__GM_GAIN_EVEN_108___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__TIA_GAIN_EVEN_108___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__TIA_GAIN_EVEN_108___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__SLM_XLNA_EVEN_108___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__SLM_XLNA_EVEN_108___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__BQ_GAIN_EVEN_108___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108__BQ_GAIN_EVEN_108___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_108___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109 (0x005F51B4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__XLNA_GAIN_ODD_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__LNA_GAIN_ODD_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__GM_GAIN_ODD_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__TIA_GAIN_ODD_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__SLM_XLNA_ODD_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__BQ_GAIN_ODD_109___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__XLNA_GAIN_EVEN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__LNA_GAIN_EVEN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__GM_GAIN_EVEN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__TIA_GAIN_EVEN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__SLM_XLNA_EVEN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__BQ_GAIN_EVEN_109___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__XLNA_GAIN_ODD_109___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__XLNA_GAIN_ODD_109___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__LNA_GAIN_ODD_109___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__LNA_GAIN_ODD_109___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__GM_GAIN_ODD_109___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__GM_GAIN_ODD_109___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__TIA_GAIN_ODD_109___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__TIA_GAIN_ODD_109___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__SLM_XLNA_ODD_109___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__SLM_XLNA_ODD_109___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__BQ_GAIN_ODD_109___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__BQ_GAIN_ODD_109___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__XLNA_GAIN_EVEN_109___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__XLNA_GAIN_EVEN_109___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__LNA_GAIN_EVEN_109___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__LNA_GAIN_EVEN_109___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__GM_GAIN_EVEN_109___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__GM_GAIN_EVEN_109___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__TIA_GAIN_EVEN_109___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__TIA_GAIN_EVEN_109___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__SLM_XLNA_EVEN_109___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__SLM_XLNA_EVEN_109___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__BQ_GAIN_EVEN_109___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109__BQ_GAIN_EVEN_109___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_109___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110 (0x005F51B8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__XLNA_GAIN_ODD_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__LNA_GAIN_ODD_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__GM_GAIN_ODD_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__TIA_GAIN_ODD_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__SLM_XLNA_ODD_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__BQ_GAIN_ODD_110___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__XLNA_GAIN_EVEN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__LNA_GAIN_EVEN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__GM_GAIN_EVEN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__TIA_GAIN_EVEN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__SLM_XLNA_EVEN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__BQ_GAIN_EVEN_110___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__XLNA_GAIN_ODD_110___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__XLNA_GAIN_ODD_110___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__LNA_GAIN_ODD_110___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__LNA_GAIN_ODD_110___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__GM_GAIN_ODD_110___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__GM_GAIN_ODD_110___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__TIA_GAIN_ODD_110___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__TIA_GAIN_ODD_110___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__SLM_XLNA_ODD_110___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__SLM_XLNA_ODD_110___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__BQ_GAIN_ODD_110___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__BQ_GAIN_ODD_110___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__XLNA_GAIN_EVEN_110___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__XLNA_GAIN_EVEN_110___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__LNA_GAIN_EVEN_110___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__LNA_GAIN_EVEN_110___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__GM_GAIN_EVEN_110___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__GM_GAIN_EVEN_110___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__TIA_GAIN_EVEN_110___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__TIA_GAIN_EVEN_110___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__SLM_XLNA_EVEN_110___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__SLM_XLNA_EVEN_110___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__BQ_GAIN_EVEN_110___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110__BQ_GAIN_EVEN_110___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_110___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111 (0x005F51BC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__XLNA_GAIN_ODD_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__LNA_GAIN_ODD_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__GM_GAIN_ODD_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__TIA_GAIN_ODD_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__SLM_XLNA_ODD_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__BQ_GAIN_ODD_111___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__XLNA_GAIN_EVEN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__LNA_GAIN_EVEN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__GM_GAIN_EVEN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__TIA_GAIN_EVEN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__SLM_XLNA_EVEN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__BQ_GAIN_EVEN_111___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__XLNA_GAIN_ODD_111___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__XLNA_GAIN_ODD_111___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__LNA_GAIN_ODD_111___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__LNA_GAIN_ODD_111___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__GM_GAIN_ODD_111___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__GM_GAIN_ODD_111___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__TIA_GAIN_ODD_111___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__TIA_GAIN_ODD_111___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__SLM_XLNA_ODD_111___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__SLM_XLNA_ODD_111___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__BQ_GAIN_ODD_111___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__BQ_GAIN_ODD_111___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__XLNA_GAIN_EVEN_111___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__XLNA_GAIN_EVEN_111___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__LNA_GAIN_EVEN_111___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__LNA_GAIN_EVEN_111___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__GM_GAIN_EVEN_111___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__GM_GAIN_EVEN_111___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__TIA_GAIN_EVEN_111___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__TIA_GAIN_EVEN_111___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__SLM_XLNA_EVEN_111___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__SLM_XLNA_EVEN_111___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__BQ_GAIN_EVEN_111___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111__BQ_GAIN_EVEN_111___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_111___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112 (0x005F51C0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__XLNA_GAIN_ODD_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__LNA_GAIN_ODD_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__GM_GAIN_ODD_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__TIA_GAIN_ODD_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__SLM_XLNA_ODD_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__BQ_GAIN_ODD_112___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__XLNA_GAIN_EVEN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__LNA_GAIN_EVEN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__GM_GAIN_EVEN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__TIA_GAIN_EVEN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__SLM_XLNA_EVEN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__BQ_GAIN_EVEN_112___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__XLNA_GAIN_ODD_112___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__XLNA_GAIN_ODD_112___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__LNA_GAIN_ODD_112___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__LNA_GAIN_ODD_112___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__GM_GAIN_ODD_112___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__GM_GAIN_ODD_112___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__TIA_GAIN_ODD_112___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__TIA_GAIN_ODD_112___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__SLM_XLNA_ODD_112___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__SLM_XLNA_ODD_112___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__BQ_GAIN_ODD_112___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__BQ_GAIN_ODD_112___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__XLNA_GAIN_EVEN_112___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__XLNA_GAIN_EVEN_112___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__LNA_GAIN_EVEN_112___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__LNA_GAIN_EVEN_112___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__GM_GAIN_EVEN_112___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__GM_GAIN_EVEN_112___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__TIA_GAIN_EVEN_112___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__TIA_GAIN_EVEN_112___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__SLM_XLNA_EVEN_112___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__SLM_XLNA_EVEN_112___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__BQ_GAIN_EVEN_112___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112__BQ_GAIN_EVEN_112___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_112___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113 (0x005F51C4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__XLNA_GAIN_ODD_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__LNA_GAIN_ODD_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__GM_GAIN_ODD_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__TIA_GAIN_ODD_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__SLM_XLNA_ODD_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__BQ_GAIN_ODD_113___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__XLNA_GAIN_EVEN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__LNA_GAIN_EVEN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__GM_GAIN_EVEN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__TIA_GAIN_EVEN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__SLM_XLNA_EVEN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__BQ_GAIN_EVEN_113___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__XLNA_GAIN_ODD_113___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__XLNA_GAIN_ODD_113___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__LNA_GAIN_ODD_113___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__LNA_GAIN_ODD_113___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__GM_GAIN_ODD_113___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__GM_GAIN_ODD_113___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__TIA_GAIN_ODD_113___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__TIA_GAIN_ODD_113___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__SLM_XLNA_ODD_113___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__SLM_XLNA_ODD_113___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__BQ_GAIN_ODD_113___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__BQ_GAIN_ODD_113___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__XLNA_GAIN_EVEN_113___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__XLNA_GAIN_EVEN_113___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__LNA_GAIN_EVEN_113___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__LNA_GAIN_EVEN_113___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__GM_GAIN_EVEN_113___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__GM_GAIN_EVEN_113___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__TIA_GAIN_EVEN_113___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__TIA_GAIN_EVEN_113___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__SLM_XLNA_EVEN_113___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__SLM_XLNA_EVEN_113___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__BQ_GAIN_EVEN_113___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113__BQ_GAIN_EVEN_113___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_113___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114 (0x005F51C8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__XLNA_GAIN_ODD_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__LNA_GAIN_ODD_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__GM_GAIN_ODD_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__TIA_GAIN_ODD_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__SLM_XLNA_ODD_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__BQ_GAIN_ODD_114___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__XLNA_GAIN_EVEN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__LNA_GAIN_EVEN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__GM_GAIN_EVEN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__TIA_GAIN_EVEN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__SLM_XLNA_EVEN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__BQ_GAIN_EVEN_114___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__XLNA_GAIN_ODD_114___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__XLNA_GAIN_ODD_114___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__LNA_GAIN_ODD_114___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__LNA_GAIN_ODD_114___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__GM_GAIN_ODD_114___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__GM_GAIN_ODD_114___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__TIA_GAIN_ODD_114___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__TIA_GAIN_ODD_114___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__SLM_XLNA_ODD_114___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__SLM_XLNA_ODD_114___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__BQ_GAIN_ODD_114___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__BQ_GAIN_ODD_114___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__XLNA_GAIN_EVEN_114___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__XLNA_GAIN_EVEN_114___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__LNA_GAIN_EVEN_114___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__LNA_GAIN_EVEN_114___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__GM_GAIN_EVEN_114___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__GM_GAIN_EVEN_114___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__TIA_GAIN_EVEN_114___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__TIA_GAIN_EVEN_114___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__SLM_XLNA_EVEN_114___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__SLM_XLNA_EVEN_114___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__BQ_GAIN_EVEN_114___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114__BQ_GAIN_EVEN_114___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_114___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115 (0x005F51CC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__XLNA_GAIN_ODD_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__LNA_GAIN_ODD_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__GM_GAIN_ODD_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__TIA_GAIN_ODD_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__SLM_XLNA_ODD_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__BQ_GAIN_ODD_115___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__XLNA_GAIN_EVEN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__LNA_GAIN_EVEN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__GM_GAIN_EVEN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__TIA_GAIN_EVEN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__SLM_XLNA_EVEN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__BQ_GAIN_EVEN_115___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__XLNA_GAIN_ODD_115___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__XLNA_GAIN_ODD_115___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__LNA_GAIN_ODD_115___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__LNA_GAIN_ODD_115___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__GM_GAIN_ODD_115___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__GM_GAIN_ODD_115___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__TIA_GAIN_ODD_115___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__TIA_GAIN_ODD_115___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__SLM_XLNA_ODD_115___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__SLM_XLNA_ODD_115___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__BQ_GAIN_ODD_115___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__BQ_GAIN_ODD_115___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__XLNA_GAIN_EVEN_115___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__XLNA_GAIN_EVEN_115___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__LNA_GAIN_EVEN_115___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__LNA_GAIN_EVEN_115___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__GM_GAIN_EVEN_115___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__GM_GAIN_EVEN_115___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__TIA_GAIN_EVEN_115___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__TIA_GAIN_EVEN_115___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__SLM_XLNA_EVEN_115___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__SLM_XLNA_EVEN_115___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__BQ_GAIN_EVEN_115___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115__BQ_GAIN_EVEN_115___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_115___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116 (0x005F51D0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__XLNA_GAIN_ODD_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__LNA_GAIN_ODD_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__GM_GAIN_ODD_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__TIA_GAIN_ODD_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__SLM_XLNA_ODD_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__BQ_GAIN_ODD_116___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__XLNA_GAIN_EVEN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__LNA_GAIN_EVEN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__GM_GAIN_EVEN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__TIA_GAIN_EVEN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__SLM_XLNA_EVEN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__BQ_GAIN_EVEN_116___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__XLNA_GAIN_ODD_116___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__XLNA_GAIN_ODD_116___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__LNA_GAIN_ODD_116___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__LNA_GAIN_ODD_116___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__GM_GAIN_ODD_116___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__GM_GAIN_ODD_116___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__TIA_GAIN_ODD_116___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__TIA_GAIN_ODD_116___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__SLM_XLNA_ODD_116___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__SLM_XLNA_ODD_116___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__BQ_GAIN_ODD_116___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__BQ_GAIN_ODD_116___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__XLNA_GAIN_EVEN_116___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__XLNA_GAIN_EVEN_116___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__LNA_GAIN_EVEN_116___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__LNA_GAIN_EVEN_116___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__GM_GAIN_EVEN_116___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__GM_GAIN_EVEN_116___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__TIA_GAIN_EVEN_116___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__TIA_GAIN_EVEN_116___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__SLM_XLNA_EVEN_116___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__SLM_XLNA_EVEN_116___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__BQ_GAIN_EVEN_116___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116__BQ_GAIN_EVEN_116___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_116___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117 (0x005F51D4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__XLNA_GAIN_ODD_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__LNA_GAIN_ODD_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__GM_GAIN_ODD_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__TIA_GAIN_ODD_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__SLM_XLNA_ODD_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__BQ_GAIN_ODD_117___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__XLNA_GAIN_EVEN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__LNA_GAIN_EVEN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__GM_GAIN_EVEN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__TIA_GAIN_EVEN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__SLM_XLNA_EVEN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__BQ_GAIN_EVEN_117___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__XLNA_GAIN_ODD_117___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__XLNA_GAIN_ODD_117___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__LNA_GAIN_ODD_117___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__LNA_GAIN_ODD_117___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__GM_GAIN_ODD_117___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__GM_GAIN_ODD_117___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__TIA_GAIN_ODD_117___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__TIA_GAIN_ODD_117___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__SLM_XLNA_ODD_117___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__SLM_XLNA_ODD_117___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__BQ_GAIN_ODD_117___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__BQ_GAIN_ODD_117___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__XLNA_GAIN_EVEN_117___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__XLNA_GAIN_EVEN_117___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__LNA_GAIN_EVEN_117___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__LNA_GAIN_EVEN_117___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__GM_GAIN_EVEN_117___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__GM_GAIN_EVEN_117___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__TIA_GAIN_EVEN_117___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__TIA_GAIN_EVEN_117___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__SLM_XLNA_EVEN_117___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__SLM_XLNA_EVEN_117___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__BQ_GAIN_EVEN_117___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117__BQ_GAIN_EVEN_117___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_117___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118 (0x005F51D8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__XLNA_GAIN_ODD_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__LNA_GAIN_ODD_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__GM_GAIN_ODD_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__TIA_GAIN_ODD_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__SLM_XLNA_ODD_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__BQ_GAIN_ODD_118___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__XLNA_GAIN_EVEN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__LNA_GAIN_EVEN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__GM_GAIN_EVEN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__TIA_GAIN_EVEN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__SLM_XLNA_EVEN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__BQ_GAIN_EVEN_118___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__XLNA_GAIN_ODD_118___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__XLNA_GAIN_ODD_118___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__LNA_GAIN_ODD_118___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__LNA_GAIN_ODD_118___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__GM_GAIN_ODD_118___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__GM_GAIN_ODD_118___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__TIA_GAIN_ODD_118___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__TIA_GAIN_ODD_118___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__SLM_XLNA_ODD_118___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__SLM_XLNA_ODD_118___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__BQ_GAIN_ODD_118___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__BQ_GAIN_ODD_118___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__XLNA_GAIN_EVEN_118___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__XLNA_GAIN_EVEN_118___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__LNA_GAIN_EVEN_118___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__LNA_GAIN_EVEN_118___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__GM_GAIN_EVEN_118___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__GM_GAIN_EVEN_118___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__TIA_GAIN_EVEN_118___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__TIA_GAIN_EVEN_118___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__SLM_XLNA_EVEN_118___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__SLM_XLNA_EVEN_118___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__BQ_GAIN_EVEN_118___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118__BQ_GAIN_EVEN_118___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_118___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119 (0x005F51DC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__XLNA_GAIN_ODD_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__LNA_GAIN_ODD_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__GM_GAIN_ODD_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__TIA_GAIN_ODD_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__SLM_XLNA_ODD_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__BQ_GAIN_ODD_119___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__XLNA_GAIN_EVEN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__LNA_GAIN_EVEN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__GM_GAIN_EVEN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__TIA_GAIN_EVEN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__SLM_XLNA_EVEN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__BQ_GAIN_EVEN_119___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__XLNA_GAIN_ODD_119___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__XLNA_GAIN_ODD_119___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__LNA_GAIN_ODD_119___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__LNA_GAIN_ODD_119___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__GM_GAIN_ODD_119___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__GM_GAIN_ODD_119___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__TIA_GAIN_ODD_119___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__TIA_GAIN_ODD_119___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__SLM_XLNA_ODD_119___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__SLM_XLNA_ODD_119___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__BQ_GAIN_ODD_119___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__BQ_GAIN_ODD_119___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__XLNA_GAIN_EVEN_119___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__XLNA_GAIN_EVEN_119___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__LNA_GAIN_EVEN_119___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__LNA_GAIN_EVEN_119___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__GM_GAIN_EVEN_119___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__GM_GAIN_EVEN_119___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__TIA_GAIN_EVEN_119___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__TIA_GAIN_EVEN_119___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__SLM_XLNA_EVEN_119___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__SLM_XLNA_EVEN_119___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__BQ_GAIN_EVEN_119___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119__BQ_GAIN_EVEN_119___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_119___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120 (0x005F51E0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__XLNA_GAIN_ODD_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__LNA_GAIN_ODD_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__GM_GAIN_ODD_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__TIA_GAIN_ODD_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__SLM_XLNA_ODD_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__BQ_GAIN_ODD_120___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__XLNA_GAIN_EVEN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__LNA_GAIN_EVEN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__GM_GAIN_EVEN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__TIA_GAIN_EVEN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__SLM_XLNA_EVEN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__BQ_GAIN_EVEN_120___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__XLNA_GAIN_ODD_120___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__XLNA_GAIN_ODD_120___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__LNA_GAIN_ODD_120___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__LNA_GAIN_ODD_120___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__GM_GAIN_ODD_120___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__GM_GAIN_ODD_120___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__TIA_GAIN_ODD_120___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__TIA_GAIN_ODD_120___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__SLM_XLNA_ODD_120___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__SLM_XLNA_ODD_120___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__BQ_GAIN_ODD_120___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__BQ_GAIN_ODD_120___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__XLNA_GAIN_EVEN_120___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__XLNA_GAIN_EVEN_120___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__LNA_GAIN_EVEN_120___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__LNA_GAIN_EVEN_120___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__GM_GAIN_EVEN_120___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__GM_GAIN_EVEN_120___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__TIA_GAIN_EVEN_120___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__TIA_GAIN_EVEN_120___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__SLM_XLNA_EVEN_120___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__SLM_XLNA_EVEN_120___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__BQ_GAIN_EVEN_120___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120__BQ_GAIN_EVEN_120___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_120___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121 (0x005F51E4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__XLNA_GAIN_ODD_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__LNA_GAIN_ODD_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__GM_GAIN_ODD_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__TIA_GAIN_ODD_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__SLM_XLNA_ODD_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__BQ_GAIN_ODD_121___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__XLNA_GAIN_EVEN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__LNA_GAIN_EVEN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__GM_GAIN_EVEN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__TIA_GAIN_EVEN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__SLM_XLNA_EVEN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__BQ_GAIN_EVEN_121___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__XLNA_GAIN_ODD_121___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__XLNA_GAIN_ODD_121___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__LNA_GAIN_ODD_121___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__LNA_GAIN_ODD_121___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__GM_GAIN_ODD_121___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__GM_GAIN_ODD_121___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__TIA_GAIN_ODD_121___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__TIA_GAIN_ODD_121___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__SLM_XLNA_ODD_121___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__SLM_XLNA_ODD_121___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__BQ_GAIN_ODD_121___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__BQ_GAIN_ODD_121___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__XLNA_GAIN_EVEN_121___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__XLNA_GAIN_EVEN_121___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__LNA_GAIN_EVEN_121___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__LNA_GAIN_EVEN_121___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__GM_GAIN_EVEN_121___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__GM_GAIN_EVEN_121___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__TIA_GAIN_EVEN_121___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__TIA_GAIN_EVEN_121___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__SLM_XLNA_EVEN_121___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__SLM_XLNA_EVEN_121___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__BQ_GAIN_EVEN_121___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121__BQ_GAIN_EVEN_121___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_121___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122 (0x005F51E8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__XLNA_GAIN_ODD_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__LNA_GAIN_ODD_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__GM_GAIN_ODD_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__TIA_GAIN_ODD_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__SLM_XLNA_ODD_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__BQ_GAIN_ODD_122___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__XLNA_GAIN_EVEN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__LNA_GAIN_EVEN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__GM_GAIN_EVEN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__TIA_GAIN_EVEN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__SLM_XLNA_EVEN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__BQ_GAIN_EVEN_122___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__XLNA_GAIN_ODD_122___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__XLNA_GAIN_ODD_122___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__LNA_GAIN_ODD_122___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__LNA_GAIN_ODD_122___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__GM_GAIN_ODD_122___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__GM_GAIN_ODD_122___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__TIA_GAIN_ODD_122___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__TIA_GAIN_ODD_122___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__SLM_XLNA_ODD_122___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__SLM_XLNA_ODD_122___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__BQ_GAIN_ODD_122___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__BQ_GAIN_ODD_122___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__XLNA_GAIN_EVEN_122___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__XLNA_GAIN_EVEN_122___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__LNA_GAIN_EVEN_122___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__LNA_GAIN_EVEN_122___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__GM_GAIN_EVEN_122___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__GM_GAIN_EVEN_122___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__TIA_GAIN_EVEN_122___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__TIA_GAIN_EVEN_122___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__SLM_XLNA_EVEN_122___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__SLM_XLNA_EVEN_122___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__BQ_GAIN_EVEN_122___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122__BQ_GAIN_EVEN_122___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_122___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123 (0x005F51EC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__XLNA_GAIN_ODD_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__LNA_GAIN_ODD_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__GM_GAIN_ODD_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__TIA_GAIN_ODD_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__SLM_XLNA_ODD_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__BQ_GAIN_ODD_123___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__XLNA_GAIN_EVEN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__LNA_GAIN_EVEN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__GM_GAIN_EVEN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__TIA_GAIN_EVEN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__SLM_XLNA_EVEN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__BQ_GAIN_EVEN_123___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__XLNA_GAIN_ODD_123___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__XLNA_GAIN_ODD_123___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__LNA_GAIN_ODD_123___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__LNA_GAIN_ODD_123___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__GM_GAIN_ODD_123___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__GM_GAIN_ODD_123___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__TIA_GAIN_ODD_123___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__TIA_GAIN_ODD_123___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__SLM_XLNA_ODD_123___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__SLM_XLNA_ODD_123___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__BQ_GAIN_ODD_123___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__BQ_GAIN_ODD_123___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__XLNA_GAIN_EVEN_123___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__XLNA_GAIN_EVEN_123___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__LNA_GAIN_EVEN_123___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__LNA_GAIN_EVEN_123___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__GM_GAIN_EVEN_123___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__GM_GAIN_EVEN_123___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__TIA_GAIN_EVEN_123___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__TIA_GAIN_EVEN_123___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__SLM_XLNA_EVEN_123___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__SLM_XLNA_EVEN_123___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__BQ_GAIN_EVEN_123___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123__BQ_GAIN_EVEN_123___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_123___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124 (0x005F51F0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__XLNA_GAIN_ODD_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__LNA_GAIN_ODD_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__GM_GAIN_ODD_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__TIA_GAIN_ODD_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__SLM_XLNA_ODD_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__BQ_GAIN_ODD_124___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__XLNA_GAIN_EVEN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__LNA_GAIN_EVEN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__GM_GAIN_EVEN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__TIA_GAIN_EVEN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__SLM_XLNA_EVEN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__BQ_GAIN_EVEN_124___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__XLNA_GAIN_ODD_124___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__XLNA_GAIN_ODD_124___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__LNA_GAIN_ODD_124___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__LNA_GAIN_ODD_124___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__GM_GAIN_ODD_124___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__GM_GAIN_ODD_124___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__TIA_GAIN_ODD_124___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__TIA_GAIN_ODD_124___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__SLM_XLNA_ODD_124___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__SLM_XLNA_ODD_124___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__BQ_GAIN_ODD_124___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__BQ_GAIN_ODD_124___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__XLNA_GAIN_EVEN_124___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__XLNA_GAIN_EVEN_124___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__LNA_GAIN_EVEN_124___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__LNA_GAIN_EVEN_124___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__GM_GAIN_EVEN_124___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__GM_GAIN_EVEN_124___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__TIA_GAIN_EVEN_124___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__TIA_GAIN_EVEN_124___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__SLM_XLNA_EVEN_124___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__SLM_XLNA_EVEN_124___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__BQ_GAIN_EVEN_124___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124__BQ_GAIN_EVEN_124___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_124___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125 (0x005F51F4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__XLNA_GAIN_ODD_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__LNA_GAIN_ODD_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__GM_GAIN_ODD_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__TIA_GAIN_ODD_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__SLM_XLNA_ODD_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__BQ_GAIN_ODD_125___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__XLNA_GAIN_EVEN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__LNA_GAIN_EVEN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__GM_GAIN_EVEN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__TIA_GAIN_EVEN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__SLM_XLNA_EVEN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__BQ_GAIN_EVEN_125___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__XLNA_GAIN_ODD_125___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__XLNA_GAIN_ODD_125___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__LNA_GAIN_ODD_125___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__LNA_GAIN_ODD_125___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__GM_GAIN_ODD_125___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__GM_GAIN_ODD_125___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__TIA_GAIN_ODD_125___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__TIA_GAIN_ODD_125___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__SLM_XLNA_ODD_125___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__SLM_XLNA_ODD_125___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__BQ_GAIN_ODD_125___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__BQ_GAIN_ODD_125___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__XLNA_GAIN_EVEN_125___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__XLNA_GAIN_EVEN_125___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__LNA_GAIN_EVEN_125___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__LNA_GAIN_EVEN_125___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__GM_GAIN_EVEN_125___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__GM_GAIN_EVEN_125___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__TIA_GAIN_EVEN_125___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__TIA_GAIN_EVEN_125___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__SLM_XLNA_EVEN_125___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__SLM_XLNA_EVEN_125___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__BQ_GAIN_EVEN_125___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125__BQ_GAIN_EVEN_125___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_125___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126 (0x005F51F8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__XLNA_GAIN_ODD_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__LNA_GAIN_ODD_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__GM_GAIN_ODD_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__TIA_GAIN_ODD_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__SLM_XLNA_ODD_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__BQ_GAIN_ODD_126___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__XLNA_GAIN_EVEN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__LNA_GAIN_EVEN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__GM_GAIN_EVEN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__TIA_GAIN_EVEN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__SLM_XLNA_EVEN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__BQ_GAIN_EVEN_126___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__XLNA_GAIN_ODD_126___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__XLNA_GAIN_ODD_126___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__LNA_GAIN_ODD_126___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__LNA_GAIN_ODD_126___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__GM_GAIN_ODD_126___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__GM_GAIN_ODD_126___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__TIA_GAIN_ODD_126___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__TIA_GAIN_ODD_126___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__SLM_XLNA_ODD_126___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__SLM_XLNA_ODD_126___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__BQ_GAIN_ODD_126___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__BQ_GAIN_ODD_126___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__XLNA_GAIN_EVEN_126___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__XLNA_GAIN_EVEN_126___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__LNA_GAIN_EVEN_126___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__LNA_GAIN_EVEN_126___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__GM_GAIN_EVEN_126___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__GM_GAIN_EVEN_126___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__TIA_GAIN_EVEN_126___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__TIA_GAIN_EVEN_126___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__SLM_XLNA_EVEN_126___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__SLM_XLNA_EVEN_126___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__BQ_GAIN_EVEN_126___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126__BQ_GAIN_EVEN_126___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_126___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127 (0x005F51FC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__XLNA_GAIN_ODD_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__LNA_GAIN_ODD_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__GM_GAIN_ODD_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__TIA_GAIN_ODD_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__SLM_XLNA_ODD_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__BQ_GAIN_ODD_127___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__XLNA_GAIN_EVEN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__LNA_GAIN_EVEN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__GM_GAIN_EVEN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__TIA_GAIN_EVEN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__SLM_XLNA_EVEN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__BQ_GAIN_EVEN_127___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__XLNA_GAIN_ODD_127___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__XLNA_GAIN_ODD_127___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__LNA_GAIN_ODD_127___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__LNA_GAIN_ODD_127___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__GM_GAIN_ODD_127___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__GM_GAIN_ODD_127___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__TIA_GAIN_ODD_127___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__TIA_GAIN_ODD_127___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__SLM_XLNA_ODD_127___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__SLM_XLNA_ODD_127___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__BQ_GAIN_ODD_127___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__BQ_GAIN_ODD_127___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__XLNA_GAIN_EVEN_127___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__XLNA_GAIN_EVEN_127___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__LNA_GAIN_EVEN_127___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__LNA_GAIN_EVEN_127___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__GM_GAIN_EVEN_127___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__GM_GAIN_EVEN_127___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__TIA_GAIN_EVEN_127___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__TIA_GAIN_EVEN_127___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__SLM_XLNA_EVEN_127___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__SLM_XLNA_EVEN_127___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__BQ_GAIN_EVEN_127___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127__BQ_GAIN_EVEN_127___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_127___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128 (0x005F5200) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__XLNA_GAIN_ODD_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__LNA_GAIN_ODD_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__GM_GAIN_ODD_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__TIA_GAIN_ODD_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__SLM_XLNA_ODD_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__BQ_GAIN_ODD_128___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__XLNA_GAIN_EVEN_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__LNA_GAIN_EVEN_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__GM_GAIN_EVEN_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__TIA_GAIN_EVEN_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__SLM_XLNA_EVEN_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__BQ_GAIN_EVEN_128___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__XLNA_GAIN_ODD_128___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__XLNA_GAIN_ODD_128___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__LNA_GAIN_ODD_128___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__LNA_GAIN_ODD_128___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__GM_GAIN_ODD_128___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__GM_GAIN_ODD_128___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__TIA_GAIN_ODD_128___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__TIA_GAIN_ODD_128___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__SLM_XLNA_ODD_128___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__SLM_XLNA_ODD_128___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__BQ_GAIN_ODD_128___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__BQ_GAIN_ODD_128___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__XLNA_GAIN_EVEN_128___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__XLNA_GAIN_EVEN_128___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__LNA_GAIN_EVEN_128___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__LNA_GAIN_EVEN_128___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__GM_GAIN_EVEN_128___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__GM_GAIN_EVEN_128___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__TIA_GAIN_EVEN_128___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__TIA_GAIN_EVEN_128___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__SLM_XLNA_EVEN_128___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__SLM_XLNA_EVEN_128___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__BQ_GAIN_EVEN_128___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128__BQ_GAIN_EVEN_128___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_128___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129 (0x005F5204) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__XLNA_GAIN_ODD_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__LNA_GAIN_ODD_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__GM_GAIN_ODD_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__TIA_GAIN_ODD_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__SLM_XLNA_ODD_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__BQ_GAIN_ODD_129___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__XLNA_GAIN_EVEN_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__LNA_GAIN_EVEN_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__GM_GAIN_EVEN_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__TIA_GAIN_EVEN_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__SLM_XLNA_EVEN_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__BQ_GAIN_EVEN_129___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__XLNA_GAIN_ODD_129___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__XLNA_GAIN_ODD_129___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__LNA_GAIN_ODD_129___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__LNA_GAIN_ODD_129___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__GM_GAIN_ODD_129___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__GM_GAIN_ODD_129___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__TIA_GAIN_ODD_129___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__TIA_GAIN_ODD_129___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__SLM_XLNA_ODD_129___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__SLM_XLNA_ODD_129___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__BQ_GAIN_ODD_129___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__BQ_GAIN_ODD_129___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__XLNA_GAIN_EVEN_129___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__XLNA_GAIN_EVEN_129___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__LNA_GAIN_EVEN_129___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__LNA_GAIN_EVEN_129___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__GM_GAIN_EVEN_129___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__GM_GAIN_EVEN_129___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__TIA_GAIN_EVEN_129___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__TIA_GAIN_EVEN_129___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__SLM_XLNA_EVEN_129___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__SLM_XLNA_EVEN_129___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__BQ_GAIN_EVEN_129___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129__BQ_GAIN_EVEN_129___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_129___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130 (0x005F5208) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__XLNA_GAIN_ODD_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__LNA_GAIN_ODD_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__GM_GAIN_ODD_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__TIA_GAIN_ODD_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__SLM_XLNA_ODD_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__BQ_GAIN_ODD_130___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__XLNA_GAIN_EVEN_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__LNA_GAIN_EVEN_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__GM_GAIN_EVEN_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__TIA_GAIN_EVEN_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__SLM_XLNA_EVEN_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__BQ_GAIN_EVEN_130___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__XLNA_GAIN_ODD_130___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__XLNA_GAIN_ODD_130___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__LNA_GAIN_ODD_130___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__LNA_GAIN_ODD_130___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__GM_GAIN_ODD_130___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__GM_GAIN_ODD_130___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__TIA_GAIN_ODD_130___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__TIA_GAIN_ODD_130___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__SLM_XLNA_ODD_130___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__SLM_XLNA_ODD_130___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__BQ_GAIN_ODD_130___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__BQ_GAIN_ODD_130___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__XLNA_GAIN_EVEN_130___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__XLNA_GAIN_EVEN_130___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__LNA_GAIN_EVEN_130___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__LNA_GAIN_EVEN_130___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__GM_GAIN_EVEN_130___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__GM_GAIN_EVEN_130___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__TIA_GAIN_EVEN_130___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__TIA_GAIN_EVEN_130___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__SLM_XLNA_EVEN_130___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__SLM_XLNA_EVEN_130___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__BQ_GAIN_EVEN_130___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130__BQ_GAIN_EVEN_130___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_130___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131 (0x005F520C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__XLNA_GAIN_ODD_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__LNA_GAIN_ODD_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__GM_GAIN_ODD_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__TIA_GAIN_ODD_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__SLM_XLNA_ODD_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__BQ_GAIN_ODD_131___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__XLNA_GAIN_EVEN_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__LNA_GAIN_EVEN_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__GM_GAIN_EVEN_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__TIA_GAIN_EVEN_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__SLM_XLNA_EVEN_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__BQ_GAIN_EVEN_131___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__XLNA_GAIN_ODD_131___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__XLNA_GAIN_ODD_131___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__LNA_GAIN_ODD_131___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__LNA_GAIN_ODD_131___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__GM_GAIN_ODD_131___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__GM_GAIN_ODD_131___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__TIA_GAIN_ODD_131___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__TIA_GAIN_ODD_131___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__SLM_XLNA_ODD_131___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__SLM_XLNA_ODD_131___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__BQ_GAIN_ODD_131___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__BQ_GAIN_ODD_131___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__XLNA_GAIN_EVEN_131___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__XLNA_GAIN_EVEN_131___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__LNA_GAIN_EVEN_131___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__LNA_GAIN_EVEN_131___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__GM_GAIN_EVEN_131___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__GM_GAIN_EVEN_131___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__TIA_GAIN_EVEN_131___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__TIA_GAIN_EVEN_131___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__SLM_XLNA_EVEN_131___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__SLM_XLNA_EVEN_131___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__BQ_GAIN_EVEN_131___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131__BQ_GAIN_EVEN_131___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_131___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132 (0x005F5210) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__XLNA_GAIN_ODD_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__LNA_GAIN_ODD_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__GM_GAIN_ODD_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__TIA_GAIN_ODD_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__SLM_XLNA_ODD_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__BQ_GAIN_ODD_132___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__XLNA_GAIN_EVEN_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__LNA_GAIN_EVEN_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__GM_GAIN_EVEN_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__TIA_GAIN_EVEN_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__SLM_XLNA_EVEN_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__BQ_GAIN_EVEN_132___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__XLNA_GAIN_ODD_132___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__XLNA_GAIN_ODD_132___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__LNA_GAIN_ODD_132___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__LNA_GAIN_ODD_132___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__GM_GAIN_ODD_132___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__GM_GAIN_ODD_132___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__TIA_GAIN_ODD_132___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__TIA_GAIN_ODD_132___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__SLM_XLNA_ODD_132___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__SLM_XLNA_ODD_132___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__BQ_GAIN_ODD_132___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__BQ_GAIN_ODD_132___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__XLNA_GAIN_EVEN_132___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__XLNA_GAIN_EVEN_132___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__LNA_GAIN_EVEN_132___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__LNA_GAIN_EVEN_132___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__GM_GAIN_EVEN_132___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__GM_GAIN_EVEN_132___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__TIA_GAIN_EVEN_132___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__TIA_GAIN_EVEN_132___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__SLM_XLNA_EVEN_132___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__SLM_XLNA_EVEN_132___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__BQ_GAIN_EVEN_132___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132__BQ_GAIN_EVEN_132___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_132___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133 (0x005F5214) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__XLNA_GAIN_ODD_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__LNA_GAIN_ODD_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__GM_GAIN_ODD_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__TIA_GAIN_ODD_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__SLM_XLNA_ODD_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__BQ_GAIN_ODD_133___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__XLNA_GAIN_EVEN_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__LNA_GAIN_EVEN_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__GM_GAIN_EVEN_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__TIA_GAIN_EVEN_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__SLM_XLNA_EVEN_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__BQ_GAIN_EVEN_133___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__XLNA_GAIN_ODD_133___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__XLNA_GAIN_ODD_133___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__LNA_GAIN_ODD_133___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__LNA_GAIN_ODD_133___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__GM_GAIN_ODD_133___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__GM_GAIN_ODD_133___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__TIA_GAIN_ODD_133___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__TIA_GAIN_ODD_133___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__SLM_XLNA_ODD_133___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__SLM_XLNA_ODD_133___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__BQ_GAIN_ODD_133___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__BQ_GAIN_ODD_133___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__XLNA_GAIN_EVEN_133___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__XLNA_GAIN_EVEN_133___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__LNA_GAIN_EVEN_133___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__LNA_GAIN_EVEN_133___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__GM_GAIN_EVEN_133___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__GM_GAIN_EVEN_133___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__TIA_GAIN_EVEN_133___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__TIA_GAIN_EVEN_133___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__SLM_XLNA_EVEN_133___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__SLM_XLNA_EVEN_133___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__BQ_GAIN_EVEN_133___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133__BQ_GAIN_EVEN_133___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_133___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134 (0x005F5218) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__XLNA_GAIN_ODD_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__LNA_GAIN_ODD_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__GM_GAIN_ODD_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__TIA_GAIN_ODD_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__SLM_XLNA_ODD_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__BQ_GAIN_ODD_134___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__XLNA_GAIN_EVEN_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__LNA_GAIN_EVEN_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__GM_GAIN_EVEN_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__TIA_GAIN_EVEN_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__SLM_XLNA_EVEN_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__BQ_GAIN_EVEN_134___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__XLNA_GAIN_ODD_134___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__XLNA_GAIN_ODD_134___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__LNA_GAIN_ODD_134___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__LNA_GAIN_ODD_134___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__GM_GAIN_ODD_134___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__GM_GAIN_ODD_134___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__TIA_GAIN_ODD_134___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__TIA_GAIN_ODD_134___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__SLM_XLNA_ODD_134___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__SLM_XLNA_ODD_134___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__BQ_GAIN_ODD_134___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__BQ_GAIN_ODD_134___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__XLNA_GAIN_EVEN_134___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__XLNA_GAIN_EVEN_134___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__LNA_GAIN_EVEN_134___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__LNA_GAIN_EVEN_134___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__GM_GAIN_EVEN_134___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__GM_GAIN_EVEN_134___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__TIA_GAIN_EVEN_134___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__TIA_GAIN_EVEN_134___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__SLM_XLNA_EVEN_134___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__SLM_XLNA_EVEN_134___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__BQ_GAIN_EVEN_134___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134__BQ_GAIN_EVEN_134___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_134___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135 (0x005F521C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__XLNA_GAIN_ODD_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__LNA_GAIN_ODD_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__GM_GAIN_ODD_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__TIA_GAIN_ODD_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__SLM_XLNA_ODD_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__BQ_GAIN_ODD_135___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__XLNA_GAIN_EVEN_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__LNA_GAIN_EVEN_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__GM_GAIN_EVEN_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__TIA_GAIN_EVEN_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__SLM_XLNA_EVEN_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__BQ_GAIN_EVEN_135___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__XLNA_GAIN_ODD_135___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__XLNA_GAIN_ODD_135___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__LNA_GAIN_ODD_135___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__LNA_GAIN_ODD_135___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__GM_GAIN_ODD_135___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__GM_GAIN_ODD_135___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__TIA_GAIN_ODD_135___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__TIA_GAIN_ODD_135___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__SLM_XLNA_ODD_135___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__SLM_XLNA_ODD_135___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__BQ_GAIN_ODD_135___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__BQ_GAIN_ODD_135___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__XLNA_GAIN_EVEN_135___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__XLNA_GAIN_EVEN_135___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__LNA_GAIN_EVEN_135___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__LNA_GAIN_EVEN_135___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__GM_GAIN_EVEN_135___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__GM_GAIN_EVEN_135___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__TIA_GAIN_EVEN_135___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__TIA_GAIN_EVEN_135___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__SLM_XLNA_EVEN_135___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__SLM_XLNA_EVEN_135___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__BQ_GAIN_EVEN_135___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135__BQ_GAIN_EVEN_135___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_135___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136 (0x005F5220) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__XLNA_GAIN_ODD_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__LNA_GAIN_ODD_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__GM_GAIN_ODD_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__TIA_GAIN_ODD_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__SLM_XLNA_ODD_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__BQ_GAIN_ODD_136___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__XLNA_GAIN_EVEN_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__LNA_GAIN_EVEN_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__GM_GAIN_EVEN_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__TIA_GAIN_EVEN_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__SLM_XLNA_EVEN_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__BQ_GAIN_EVEN_136___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__XLNA_GAIN_ODD_136___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__XLNA_GAIN_ODD_136___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__LNA_GAIN_ODD_136___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__LNA_GAIN_ODD_136___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__GM_GAIN_ODD_136___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__GM_GAIN_ODD_136___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__TIA_GAIN_ODD_136___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__TIA_GAIN_ODD_136___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__SLM_XLNA_ODD_136___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__SLM_XLNA_ODD_136___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__BQ_GAIN_ODD_136___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__BQ_GAIN_ODD_136___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__XLNA_GAIN_EVEN_136___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__XLNA_GAIN_EVEN_136___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__LNA_GAIN_EVEN_136___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__LNA_GAIN_EVEN_136___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__GM_GAIN_EVEN_136___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__GM_GAIN_EVEN_136___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__TIA_GAIN_EVEN_136___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__TIA_GAIN_EVEN_136___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__SLM_XLNA_EVEN_136___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__SLM_XLNA_EVEN_136___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__BQ_GAIN_EVEN_136___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136__BQ_GAIN_EVEN_136___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_136___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137 (0x005F5224) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__XLNA_GAIN_ODD_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__LNA_GAIN_ODD_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__GM_GAIN_ODD_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__TIA_GAIN_ODD_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__SLM_XLNA_ODD_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__BQ_GAIN_ODD_137___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__XLNA_GAIN_EVEN_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__LNA_GAIN_EVEN_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__GM_GAIN_EVEN_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__TIA_GAIN_EVEN_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__SLM_XLNA_EVEN_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__BQ_GAIN_EVEN_137___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__XLNA_GAIN_ODD_137___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__XLNA_GAIN_ODD_137___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__LNA_GAIN_ODD_137___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__LNA_GAIN_ODD_137___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__GM_GAIN_ODD_137___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__GM_GAIN_ODD_137___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__TIA_GAIN_ODD_137___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__TIA_GAIN_ODD_137___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__SLM_XLNA_ODD_137___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__SLM_XLNA_ODD_137___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__BQ_GAIN_ODD_137___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__BQ_GAIN_ODD_137___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__XLNA_GAIN_EVEN_137___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__XLNA_GAIN_EVEN_137___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__LNA_GAIN_EVEN_137___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__LNA_GAIN_EVEN_137___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__GM_GAIN_EVEN_137___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__GM_GAIN_EVEN_137___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__TIA_GAIN_EVEN_137___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__TIA_GAIN_EVEN_137___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__SLM_XLNA_EVEN_137___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__SLM_XLNA_EVEN_137___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__BQ_GAIN_EVEN_137___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137__BQ_GAIN_EVEN_137___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_137___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138 (0x005F5228) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__XLNA_GAIN_ODD_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__LNA_GAIN_ODD_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__GM_GAIN_ODD_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__TIA_GAIN_ODD_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__SLM_XLNA_ODD_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__BQ_GAIN_ODD_138___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__XLNA_GAIN_EVEN_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__LNA_GAIN_EVEN_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__GM_GAIN_EVEN_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__TIA_GAIN_EVEN_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__SLM_XLNA_EVEN_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__BQ_GAIN_EVEN_138___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__XLNA_GAIN_ODD_138___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__XLNA_GAIN_ODD_138___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__LNA_GAIN_ODD_138___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__LNA_GAIN_ODD_138___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__GM_GAIN_ODD_138___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__GM_GAIN_ODD_138___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__TIA_GAIN_ODD_138___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__TIA_GAIN_ODD_138___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__SLM_XLNA_ODD_138___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__SLM_XLNA_ODD_138___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__BQ_GAIN_ODD_138___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__BQ_GAIN_ODD_138___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__XLNA_GAIN_EVEN_138___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__XLNA_GAIN_EVEN_138___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__LNA_GAIN_EVEN_138___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__LNA_GAIN_EVEN_138___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__GM_GAIN_EVEN_138___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__GM_GAIN_EVEN_138___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__TIA_GAIN_EVEN_138___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__TIA_GAIN_EVEN_138___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__SLM_XLNA_EVEN_138___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__SLM_XLNA_EVEN_138___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__BQ_GAIN_EVEN_138___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138__BQ_GAIN_EVEN_138___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_138___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139 (0x005F522C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__XLNA_GAIN_ODD_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__LNA_GAIN_ODD_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__GM_GAIN_ODD_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__TIA_GAIN_ODD_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__SLM_XLNA_ODD_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__BQ_GAIN_ODD_139___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__XLNA_GAIN_EVEN_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__LNA_GAIN_EVEN_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__GM_GAIN_EVEN_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__TIA_GAIN_EVEN_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__SLM_XLNA_EVEN_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__BQ_GAIN_EVEN_139___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__XLNA_GAIN_ODD_139___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__XLNA_GAIN_ODD_139___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__LNA_GAIN_ODD_139___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__LNA_GAIN_ODD_139___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__GM_GAIN_ODD_139___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__GM_GAIN_ODD_139___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__TIA_GAIN_ODD_139___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__TIA_GAIN_ODD_139___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__SLM_XLNA_ODD_139___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__SLM_XLNA_ODD_139___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__BQ_GAIN_ODD_139___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__BQ_GAIN_ODD_139___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__XLNA_GAIN_EVEN_139___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__XLNA_GAIN_EVEN_139___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__LNA_GAIN_EVEN_139___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__LNA_GAIN_EVEN_139___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__GM_GAIN_EVEN_139___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__GM_GAIN_EVEN_139___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__TIA_GAIN_EVEN_139___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__TIA_GAIN_EVEN_139___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__SLM_XLNA_EVEN_139___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__SLM_XLNA_EVEN_139___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__BQ_GAIN_EVEN_139___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139__BQ_GAIN_EVEN_139___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_139___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140 (0x005F5230) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__XLNA_GAIN_ODD_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__LNA_GAIN_ODD_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__GM_GAIN_ODD_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__TIA_GAIN_ODD_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__SLM_XLNA_ODD_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__BQ_GAIN_ODD_140___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__XLNA_GAIN_EVEN_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__LNA_GAIN_EVEN_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__GM_GAIN_EVEN_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__TIA_GAIN_EVEN_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__SLM_XLNA_EVEN_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__BQ_GAIN_EVEN_140___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__XLNA_GAIN_ODD_140___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__XLNA_GAIN_ODD_140___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__LNA_GAIN_ODD_140___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__LNA_GAIN_ODD_140___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__GM_GAIN_ODD_140___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__GM_GAIN_ODD_140___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__TIA_GAIN_ODD_140___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__TIA_GAIN_ODD_140___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__SLM_XLNA_ODD_140___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__SLM_XLNA_ODD_140___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__BQ_GAIN_ODD_140___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__BQ_GAIN_ODD_140___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__XLNA_GAIN_EVEN_140___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__XLNA_GAIN_EVEN_140___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__LNA_GAIN_EVEN_140___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__LNA_GAIN_EVEN_140___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__GM_GAIN_EVEN_140___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__GM_GAIN_EVEN_140___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__TIA_GAIN_EVEN_140___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__TIA_GAIN_EVEN_140___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__SLM_XLNA_EVEN_140___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__SLM_XLNA_EVEN_140___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__BQ_GAIN_EVEN_140___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140__BQ_GAIN_EVEN_140___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_140___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141 (0x005F5234) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__XLNA_GAIN_ODD_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__LNA_GAIN_ODD_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__GM_GAIN_ODD_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__TIA_GAIN_ODD_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__SLM_XLNA_ODD_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__BQ_GAIN_ODD_141___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__XLNA_GAIN_EVEN_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__LNA_GAIN_EVEN_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__GM_GAIN_EVEN_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__TIA_GAIN_EVEN_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__SLM_XLNA_EVEN_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__BQ_GAIN_EVEN_141___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__XLNA_GAIN_ODD_141___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__XLNA_GAIN_ODD_141___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__LNA_GAIN_ODD_141___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__LNA_GAIN_ODD_141___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__GM_GAIN_ODD_141___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__GM_GAIN_ODD_141___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__TIA_GAIN_ODD_141___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__TIA_GAIN_ODD_141___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__SLM_XLNA_ODD_141___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__SLM_XLNA_ODD_141___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__BQ_GAIN_ODD_141___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__BQ_GAIN_ODD_141___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__XLNA_GAIN_EVEN_141___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__XLNA_GAIN_EVEN_141___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__LNA_GAIN_EVEN_141___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__LNA_GAIN_EVEN_141___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__GM_GAIN_EVEN_141___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__GM_GAIN_EVEN_141___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__TIA_GAIN_EVEN_141___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__TIA_GAIN_EVEN_141___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__SLM_XLNA_EVEN_141___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__SLM_XLNA_EVEN_141___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__BQ_GAIN_EVEN_141___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141__BQ_GAIN_EVEN_141___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_141___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142 (0x005F5238) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__XLNA_GAIN_ODD_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__LNA_GAIN_ODD_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__GM_GAIN_ODD_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__TIA_GAIN_ODD_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__SLM_XLNA_ODD_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__BQ_GAIN_ODD_142___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__XLNA_GAIN_EVEN_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__LNA_GAIN_EVEN_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__GM_GAIN_EVEN_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__TIA_GAIN_EVEN_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__SLM_XLNA_EVEN_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__BQ_GAIN_EVEN_142___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__XLNA_GAIN_ODD_142___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__XLNA_GAIN_ODD_142___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__LNA_GAIN_ODD_142___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__LNA_GAIN_ODD_142___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__GM_GAIN_ODD_142___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__GM_GAIN_ODD_142___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__TIA_GAIN_ODD_142___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__TIA_GAIN_ODD_142___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__SLM_XLNA_ODD_142___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__SLM_XLNA_ODD_142___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__BQ_GAIN_ODD_142___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__BQ_GAIN_ODD_142___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__XLNA_GAIN_EVEN_142___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__XLNA_GAIN_EVEN_142___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__LNA_GAIN_EVEN_142___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__LNA_GAIN_EVEN_142___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__GM_GAIN_EVEN_142___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__GM_GAIN_EVEN_142___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__TIA_GAIN_EVEN_142___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__TIA_GAIN_EVEN_142___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__SLM_XLNA_EVEN_142___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__SLM_XLNA_EVEN_142___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__BQ_GAIN_EVEN_142___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142__BQ_GAIN_EVEN_142___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_142___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143 (0x005F523C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__XLNA_GAIN_ODD_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__LNA_GAIN_ODD_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__GM_GAIN_ODD_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__TIA_GAIN_ODD_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__SLM_XLNA_ODD_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__BQ_GAIN_ODD_143___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__XLNA_GAIN_EVEN_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__LNA_GAIN_EVEN_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__GM_GAIN_EVEN_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__TIA_GAIN_EVEN_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__SLM_XLNA_EVEN_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__BQ_GAIN_EVEN_143___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__XLNA_GAIN_ODD_143___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__XLNA_GAIN_ODD_143___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__LNA_GAIN_ODD_143___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__LNA_GAIN_ODD_143___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__GM_GAIN_ODD_143___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__GM_GAIN_ODD_143___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__TIA_GAIN_ODD_143___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__TIA_GAIN_ODD_143___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__SLM_XLNA_ODD_143___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__SLM_XLNA_ODD_143___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__BQ_GAIN_ODD_143___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__BQ_GAIN_ODD_143___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__XLNA_GAIN_EVEN_143___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__XLNA_GAIN_EVEN_143___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__LNA_GAIN_EVEN_143___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__LNA_GAIN_EVEN_143___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__GM_GAIN_EVEN_143___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__GM_GAIN_EVEN_143___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__TIA_GAIN_EVEN_143___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__TIA_GAIN_EVEN_143___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__SLM_XLNA_EVEN_143___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__SLM_XLNA_EVEN_143___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__BQ_GAIN_EVEN_143___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143__BQ_GAIN_EVEN_143___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_143___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144 (0x005F5240) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__XLNA_GAIN_ODD_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__LNA_GAIN_ODD_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__GM_GAIN_ODD_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__TIA_GAIN_ODD_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__SLM_XLNA_ODD_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__BQ_GAIN_ODD_144___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__XLNA_GAIN_EVEN_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__LNA_GAIN_EVEN_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__GM_GAIN_EVEN_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__TIA_GAIN_EVEN_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__SLM_XLNA_EVEN_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__BQ_GAIN_EVEN_144___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__XLNA_GAIN_ODD_144___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__XLNA_GAIN_ODD_144___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__LNA_GAIN_ODD_144___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__LNA_GAIN_ODD_144___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__GM_GAIN_ODD_144___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__GM_GAIN_ODD_144___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__TIA_GAIN_ODD_144___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__TIA_GAIN_ODD_144___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__SLM_XLNA_ODD_144___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__SLM_XLNA_ODD_144___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__BQ_GAIN_ODD_144___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__BQ_GAIN_ODD_144___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__XLNA_GAIN_EVEN_144___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__XLNA_GAIN_EVEN_144___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__LNA_GAIN_EVEN_144___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__LNA_GAIN_EVEN_144___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__GM_GAIN_EVEN_144___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__GM_GAIN_EVEN_144___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__TIA_GAIN_EVEN_144___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__TIA_GAIN_EVEN_144___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__SLM_XLNA_EVEN_144___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__SLM_XLNA_EVEN_144___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__BQ_GAIN_EVEN_144___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144__BQ_GAIN_EVEN_144___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_144___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145 (0x005F5244) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__XLNA_GAIN_ODD_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__LNA_GAIN_ODD_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__GM_GAIN_ODD_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__TIA_GAIN_ODD_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__SLM_XLNA_ODD_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__BQ_GAIN_ODD_145___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__XLNA_GAIN_EVEN_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__LNA_GAIN_EVEN_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__GM_GAIN_EVEN_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__TIA_GAIN_EVEN_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__SLM_XLNA_EVEN_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__BQ_GAIN_EVEN_145___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__XLNA_GAIN_ODD_145___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__XLNA_GAIN_ODD_145___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__LNA_GAIN_ODD_145___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__LNA_GAIN_ODD_145___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__GM_GAIN_ODD_145___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__GM_GAIN_ODD_145___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__TIA_GAIN_ODD_145___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__TIA_GAIN_ODD_145___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__SLM_XLNA_ODD_145___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__SLM_XLNA_ODD_145___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__BQ_GAIN_ODD_145___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__BQ_GAIN_ODD_145___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__XLNA_GAIN_EVEN_145___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__XLNA_GAIN_EVEN_145___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__LNA_GAIN_EVEN_145___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__LNA_GAIN_EVEN_145___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__GM_GAIN_EVEN_145___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__GM_GAIN_EVEN_145___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__TIA_GAIN_EVEN_145___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__TIA_GAIN_EVEN_145___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__SLM_XLNA_EVEN_145___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__SLM_XLNA_EVEN_145___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__BQ_GAIN_EVEN_145___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145__BQ_GAIN_EVEN_145___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_145___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146 (0x005F5248) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__XLNA_GAIN_ODD_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__LNA_GAIN_ODD_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__GM_GAIN_ODD_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__TIA_GAIN_ODD_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__SLM_XLNA_ODD_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__BQ_GAIN_ODD_146___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__XLNA_GAIN_EVEN_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__LNA_GAIN_EVEN_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__GM_GAIN_EVEN_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__TIA_GAIN_EVEN_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__SLM_XLNA_EVEN_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__BQ_GAIN_EVEN_146___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__XLNA_GAIN_ODD_146___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__XLNA_GAIN_ODD_146___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__LNA_GAIN_ODD_146___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__LNA_GAIN_ODD_146___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__GM_GAIN_ODD_146___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__GM_GAIN_ODD_146___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__TIA_GAIN_ODD_146___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__TIA_GAIN_ODD_146___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__SLM_XLNA_ODD_146___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__SLM_XLNA_ODD_146___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__BQ_GAIN_ODD_146___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__BQ_GAIN_ODD_146___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__XLNA_GAIN_EVEN_146___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__XLNA_GAIN_EVEN_146___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__LNA_GAIN_EVEN_146___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__LNA_GAIN_EVEN_146___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__GM_GAIN_EVEN_146___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__GM_GAIN_EVEN_146___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__TIA_GAIN_EVEN_146___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__TIA_GAIN_EVEN_146___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__SLM_XLNA_EVEN_146___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__SLM_XLNA_EVEN_146___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__BQ_GAIN_EVEN_146___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146__BQ_GAIN_EVEN_146___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_146___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147 (0x005F524C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__XLNA_GAIN_ODD_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__LNA_GAIN_ODD_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__GM_GAIN_ODD_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__TIA_GAIN_ODD_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__SLM_XLNA_ODD_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__BQ_GAIN_ODD_147___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__XLNA_GAIN_EVEN_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__LNA_GAIN_EVEN_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__GM_GAIN_EVEN_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__TIA_GAIN_EVEN_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__SLM_XLNA_EVEN_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__BQ_GAIN_EVEN_147___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__XLNA_GAIN_ODD_147___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__XLNA_GAIN_ODD_147___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__LNA_GAIN_ODD_147___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__LNA_GAIN_ODD_147___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__GM_GAIN_ODD_147___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__GM_GAIN_ODD_147___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__TIA_GAIN_ODD_147___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__TIA_GAIN_ODD_147___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__SLM_XLNA_ODD_147___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__SLM_XLNA_ODD_147___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__BQ_GAIN_ODD_147___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__BQ_GAIN_ODD_147___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__XLNA_GAIN_EVEN_147___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__XLNA_GAIN_EVEN_147___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__LNA_GAIN_EVEN_147___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__LNA_GAIN_EVEN_147___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__GM_GAIN_EVEN_147___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__GM_GAIN_EVEN_147___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__TIA_GAIN_EVEN_147___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__TIA_GAIN_EVEN_147___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__SLM_XLNA_EVEN_147___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__SLM_XLNA_EVEN_147___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__BQ_GAIN_EVEN_147___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147__BQ_GAIN_EVEN_147___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_147___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148 (0x005F5250) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__XLNA_GAIN_ODD_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__LNA_GAIN_ODD_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__GM_GAIN_ODD_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__TIA_GAIN_ODD_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__SLM_XLNA_ODD_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__BQ_GAIN_ODD_148___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__XLNA_GAIN_EVEN_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__LNA_GAIN_EVEN_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__GM_GAIN_EVEN_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__TIA_GAIN_EVEN_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__SLM_XLNA_EVEN_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__BQ_GAIN_EVEN_148___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__XLNA_GAIN_ODD_148___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__XLNA_GAIN_ODD_148___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__LNA_GAIN_ODD_148___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__LNA_GAIN_ODD_148___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__GM_GAIN_ODD_148___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__GM_GAIN_ODD_148___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__TIA_GAIN_ODD_148___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__TIA_GAIN_ODD_148___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__SLM_XLNA_ODD_148___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__SLM_XLNA_ODD_148___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__BQ_GAIN_ODD_148___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__BQ_GAIN_ODD_148___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__XLNA_GAIN_EVEN_148___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__XLNA_GAIN_EVEN_148___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__LNA_GAIN_EVEN_148___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__LNA_GAIN_EVEN_148___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__GM_GAIN_EVEN_148___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__GM_GAIN_EVEN_148___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__TIA_GAIN_EVEN_148___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__TIA_GAIN_EVEN_148___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__SLM_XLNA_EVEN_148___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__SLM_XLNA_EVEN_148___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__BQ_GAIN_EVEN_148___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148__BQ_GAIN_EVEN_148___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_148___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149 (0x005F5254) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__XLNA_GAIN_ODD_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__LNA_GAIN_ODD_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__GM_GAIN_ODD_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__TIA_GAIN_ODD_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__SLM_XLNA_ODD_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__BQ_GAIN_ODD_149___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__XLNA_GAIN_EVEN_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__LNA_GAIN_EVEN_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__GM_GAIN_EVEN_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__TIA_GAIN_EVEN_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__SLM_XLNA_EVEN_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__BQ_GAIN_EVEN_149___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__XLNA_GAIN_ODD_149___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__XLNA_GAIN_ODD_149___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__LNA_GAIN_ODD_149___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__LNA_GAIN_ODD_149___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__GM_GAIN_ODD_149___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__GM_GAIN_ODD_149___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__TIA_GAIN_ODD_149___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__TIA_GAIN_ODD_149___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__SLM_XLNA_ODD_149___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__SLM_XLNA_ODD_149___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__BQ_GAIN_ODD_149___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__BQ_GAIN_ODD_149___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__XLNA_GAIN_EVEN_149___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__XLNA_GAIN_EVEN_149___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__LNA_GAIN_EVEN_149___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__LNA_GAIN_EVEN_149___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__GM_GAIN_EVEN_149___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__GM_GAIN_EVEN_149___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__TIA_GAIN_EVEN_149___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__TIA_GAIN_EVEN_149___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__SLM_XLNA_EVEN_149___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__SLM_XLNA_EVEN_149___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__BQ_GAIN_EVEN_149___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149__BQ_GAIN_EVEN_149___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_149___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150 (0x005F5258) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__XLNA_GAIN_ODD_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__LNA_GAIN_ODD_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__GM_GAIN_ODD_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__TIA_GAIN_ODD_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__SLM_XLNA_ODD_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__BQ_GAIN_ODD_150___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__XLNA_GAIN_EVEN_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__LNA_GAIN_EVEN_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__GM_GAIN_EVEN_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__TIA_GAIN_EVEN_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__SLM_XLNA_EVEN_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__BQ_GAIN_EVEN_150___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__XLNA_GAIN_ODD_150___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__XLNA_GAIN_ODD_150___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__LNA_GAIN_ODD_150___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__LNA_GAIN_ODD_150___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__GM_GAIN_ODD_150___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__GM_GAIN_ODD_150___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__TIA_GAIN_ODD_150___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__TIA_GAIN_ODD_150___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__SLM_XLNA_ODD_150___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__SLM_XLNA_ODD_150___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__BQ_GAIN_ODD_150___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__BQ_GAIN_ODD_150___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__XLNA_GAIN_EVEN_150___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__XLNA_GAIN_EVEN_150___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__LNA_GAIN_EVEN_150___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__LNA_GAIN_EVEN_150___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__GM_GAIN_EVEN_150___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__GM_GAIN_EVEN_150___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__TIA_GAIN_EVEN_150___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__TIA_GAIN_EVEN_150___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__SLM_XLNA_EVEN_150___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__SLM_XLNA_EVEN_150___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__BQ_GAIN_EVEN_150___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150__BQ_GAIN_EVEN_150___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_150___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151 (0x005F525C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__XLNA_GAIN_ODD_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__LNA_GAIN_ODD_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__GM_GAIN_ODD_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__TIA_GAIN_ODD_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__SLM_XLNA_ODD_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__BQ_GAIN_ODD_151___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__XLNA_GAIN_EVEN_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__LNA_GAIN_EVEN_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__GM_GAIN_EVEN_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__TIA_GAIN_EVEN_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__SLM_XLNA_EVEN_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__BQ_GAIN_EVEN_151___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__XLNA_GAIN_ODD_151___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__XLNA_GAIN_ODD_151___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__LNA_GAIN_ODD_151___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__LNA_GAIN_ODD_151___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__GM_GAIN_ODD_151___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__GM_GAIN_ODD_151___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__TIA_GAIN_ODD_151___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__TIA_GAIN_ODD_151___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__SLM_XLNA_ODD_151___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__SLM_XLNA_ODD_151___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__BQ_GAIN_ODD_151___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__BQ_GAIN_ODD_151___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__XLNA_GAIN_EVEN_151___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__XLNA_GAIN_EVEN_151___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__LNA_GAIN_EVEN_151___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__LNA_GAIN_EVEN_151___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__GM_GAIN_EVEN_151___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__GM_GAIN_EVEN_151___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__TIA_GAIN_EVEN_151___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__TIA_GAIN_EVEN_151___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__SLM_XLNA_EVEN_151___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__SLM_XLNA_EVEN_151___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__BQ_GAIN_EVEN_151___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151__BQ_GAIN_EVEN_151___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_151___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152 (0x005F5260) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__XLNA_GAIN_ODD_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__LNA_GAIN_ODD_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__GM_GAIN_ODD_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__TIA_GAIN_ODD_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__SLM_XLNA_ODD_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__BQ_GAIN_ODD_152___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__XLNA_GAIN_EVEN_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__LNA_GAIN_EVEN_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__GM_GAIN_EVEN_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__TIA_GAIN_EVEN_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__SLM_XLNA_EVEN_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__BQ_GAIN_EVEN_152___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__XLNA_GAIN_ODD_152___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__XLNA_GAIN_ODD_152___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__LNA_GAIN_ODD_152___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__LNA_GAIN_ODD_152___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__GM_GAIN_ODD_152___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__GM_GAIN_ODD_152___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__TIA_GAIN_ODD_152___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__TIA_GAIN_ODD_152___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__SLM_XLNA_ODD_152___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__SLM_XLNA_ODD_152___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__BQ_GAIN_ODD_152___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__BQ_GAIN_ODD_152___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__XLNA_GAIN_EVEN_152___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__XLNA_GAIN_EVEN_152___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__LNA_GAIN_EVEN_152___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__LNA_GAIN_EVEN_152___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__GM_GAIN_EVEN_152___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__GM_GAIN_EVEN_152___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__TIA_GAIN_EVEN_152___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__TIA_GAIN_EVEN_152___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__SLM_XLNA_EVEN_152___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__SLM_XLNA_EVEN_152___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__BQ_GAIN_EVEN_152___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152__BQ_GAIN_EVEN_152___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_152___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153 (0x005F5264) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__XLNA_GAIN_ODD_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__LNA_GAIN_ODD_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__GM_GAIN_ODD_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__TIA_GAIN_ODD_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__SLM_XLNA_ODD_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__BQ_GAIN_ODD_153___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__XLNA_GAIN_EVEN_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__LNA_GAIN_EVEN_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__GM_GAIN_EVEN_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__TIA_GAIN_EVEN_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__SLM_XLNA_EVEN_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__BQ_GAIN_EVEN_153___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__XLNA_GAIN_ODD_153___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__XLNA_GAIN_ODD_153___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__LNA_GAIN_ODD_153___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__LNA_GAIN_ODD_153___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__GM_GAIN_ODD_153___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__GM_GAIN_ODD_153___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__TIA_GAIN_ODD_153___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__TIA_GAIN_ODD_153___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__SLM_XLNA_ODD_153___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__SLM_XLNA_ODD_153___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__BQ_GAIN_ODD_153___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__BQ_GAIN_ODD_153___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__XLNA_GAIN_EVEN_153___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__XLNA_GAIN_EVEN_153___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__LNA_GAIN_EVEN_153___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__LNA_GAIN_EVEN_153___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__GM_GAIN_EVEN_153___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__GM_GAIN_EVEN_153___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__TIA_GAIN_EVEN_153___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__TIA_GAIN_EVEN_153___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__SLM_XLNA_EVEN_153___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__SLM_XLNA_EVEN_153___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__BQ_GAIN_EVEN_153___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153__BQ_GAIN_EVEN_153___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_153___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154 (0x005F5268) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__XLNA_GAIN_ODD_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__LNA_GAIN_ODD_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__GM_GAIN_ODD_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__TIA_GAIN_ODD_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__SLM_XLNA_ODD_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__BQ_GAIN_ODD_154___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__XLNA_GAIN_EVEN_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__LNA_GAIN_EVEN_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__GM_GAIN_EVEN_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__TIA_GAIN_EVEN_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__SLM_XLNA_EVEN_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__BQ_GAIN_EVEN_154___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__XLNA_GAIN_ODD_154___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__XLNA_GAIN_ODD_154___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__LNA_GAIN_ODD_154___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__LNA_GAIN_ODD_154___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__GM_GAIN_ODD_154___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__GM_GAIN_ODD_154___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__TIA_GAIN_ODD_154___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__TIA_GAIN_ODD_154___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__SLM_XLNA_ODD_154___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__SLM_XLNA_ODD_154___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__BQ_GAIN_ODD_154___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__BQ_GAIN_ODD_154___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__XLNA_GAIN_EVEN_154___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__XLNA_GAIN_EVEN_154___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__LNA_GAIN_EVEN_154___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__LNA_GAIN_EVEN_154___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__GM_GAIN_EVEN_154___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__GM_GAIN_EVEN_154___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__TIA_GAIN_EVEN_154___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__TIA_GAIN_EVEN_154___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__SLM_XLNA_EVEN_154___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__SLM_XLNA_EVEN_154___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__BQ_GAIN_EVEN_154___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154__BQ_GAIN_EVEN_154___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_154___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155 (0x005F526C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__XLNA_GAIN_ODD_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__LNA_GAIN_ODD_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__GM_GAIN_ODD_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__TIA_GAIN_ODD_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__SLM_XLNA_ODD_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__BQ_GAIN_ODD_155___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__XLNA_GAIN_EVEN_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__LNA_GAIN_EVEN_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__GM_GAIN_EVEN_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__TIA_GAIN_EVEN_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__SLM_XLNA_EVEN_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__BQ_GAIN_EVEN_155___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__XLNA_GAIN_ODD_155___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__XLNA_GAIN_ODD_155___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__LNA_GAIN_ODD_155___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__LNA_GAIN_ODD_155___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__GM_GAIN_ODD_155___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__GM_GAIN_ODD_155___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__TIA_GAIN_ODD_155___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__TIA_GAIN_ODD_155___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__SLM_XLNA_ODD_155___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__SLM_XLNA_ODD_155___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__BQ_GAIN_ODD_155___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__BQ_GAIN_ODD_155___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__XLNA_GAIN_EVEN_155___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__XLNA_GAIN_EVEN_155___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__LNA_GAIN_EVEN_155___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__LNA_GAIN_EVEN_155___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__GM_GAIN_EVEN_155___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__GM_GAIN_EVEN_155___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__TIA_GAIN_EVEN_155___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__TIA_GAIN_EVEN_155___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__SLM_XLNA_EVEN_155___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__SLM_XLNA_EVEN_155___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__BQ_GAIN_EVEN_155___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155__BQ_GAIN_EVEN_155___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_155___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156 (0x005F5270) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__XLNA_GAIN_ODD_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__LNA_GAIN_ODD_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__GM_GAIN_ODD_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__TIA_GAIN_ODD_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__SLM_XLNA_ODD_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__BQ_GAIN_ODD_156___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__XLNA_GAIN_EVEN_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__LNA_GAIN_EVEN_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__GM_GAIN_EVEN_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__TIA_GAIN_EVEN_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__SLM_XLNA_EVEN_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__BQ_GAIN_EVEN_156___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__XLNA_GAIN_ODD_156___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__XLNA_GAIN_ODD_156___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__LNA_GAIN_ODD_156___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__LNA_GAIN_ODD_156___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__GM_GAIN_ODD_156___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__GM_GAIN_ODD_156___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__TIA_GAIN_ODD_156___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__TIA_GAIN_ODD_156___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__SLM_XLNA_ODD_156___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__SLM_XLNA_ODD_156___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__BQ_GAIN_ODD_156___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__BQ_GAIN_ODD_156___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__XLNA_GAIN_EVEN_156___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__XLNA_GAIN_EVEN_156___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__LNA_GAIN_EVEN_156___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__LNA_GAIN_EVEN_156___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__GM_GAIN_EVEN_156___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__GM_GAIN_EVEN_156___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__TIA_GAIN_EVEN_156___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__TIA_GAIN_EVEN_156___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__SLM_XLNA_EVEN_156___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__SLM_XLNA_EVEN_156___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__BQ_GAIN_EVEN_156___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156__BQ_GAIN_EVEN_156___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_156___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157 (0x005F5274) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__XLNA_GAIN_ODD_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__LNA_GAIN_ODD_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__GM_GAIN_ODD_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__TIA_GAIN_ODD_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__SLM_XLNA_ODD_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__BQ_GAIN_ODD_157___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__XLNA_GAIN_EVEN_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__LNA_GAIN_EVEN_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__GM_GAIN_EVEN_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__TIA_GAIN_EVEN_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__SLM_XLNA_EVEN_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__BQ_GAIN_EVEN_157___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__XLNA_GAIN_ODD_157___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__XLNA_GAIN_ODD_157___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__LNA_GAIN_ODD_157___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__LNA_GAIN_ODD_157___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__GM_GAIN_ODD_157___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__GM_GAIN_ODD_157___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__TIA_GAIN_ODD_157___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__TIA_GAIN_ODD_157___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__SLM_XLNA_ODD_157___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__SLM_XLNA_ODD_157___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__BQ_GAIN_ODD_157___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__BQ_GAIN_ODD_157___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__XLNA_GAIN_EVEN_157___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__XLNA_GAIN_EVEN_157___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__LNA_GAIN_EVEN_157___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__LNA_GAIN_EVEN_157___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__GM_GAIN_EVEN_157___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__GM_GAIN_EVEN_157___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__TIA_GAIN_EVEN_157___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__TIA_GAIN_EVEN_157___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__SLM_XLNA_EVEN_157___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__SLM_XLNA_EVEN_157___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__BQ_GAIN_EVEN_157___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157__BQ_GAIN_EVEN_157___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_157___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158 (0x005F5278) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__XLNA_GAIN_ODD_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__LNA_GAIN_ODD_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__GM_GAIN_ODD_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__TIA_GAIN_ODD_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__SLM_XLNA_ODD_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__BQ_GAIN_ODD_158___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__XLNA_GAIN_EVEN_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__LNA_GAIN_EVEN_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__GM_GAIN_EVEN_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__TIA_GAIN_EVEN_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__SLM_XLNA_EVEN_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__BQ_GAIN_EVEN_158___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__XLNA_GAIN_ODD_158___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__XLNA_GAIN_ODD_158___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__LNA_GAIN_ODD_158___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__LNA_GAIN_ODD_158___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__GM_GAIN_ODD_158___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__GM_GAIN_ODD_158___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__TIA_GAIN_ODD_158___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__TIA_GAIN_ODD_158___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__SLM_XLNA_ODD_158___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__SLM_XLNA_ODD_158___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__BQ_GAIN_ODD_158___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__BQ_GAIN_ODD_158___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__XLNA_GAIN_EVEN_158___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__XLNA_GAIN_EVEN_158___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__LNA_GAIN_EVEN_158___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__LNA_GAIN_EVEN_158___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__GM_GAIN_EVEN_158___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__GM_GAIN_EVEN_158___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__TIA_GAIN_EVEN_158___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__TIA_GAIN_EVEN_158___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__SLM_XLNA_EVEN_158___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__SLM_XLNA_EVEN_158___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__BQ_GAIN_EVEN_158___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158__BQ_GAIN_EVEN_158___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_158___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159 (0x005F527C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__XLNA_GAIN_ODD_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__LNA_GAIN_ODD_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__GM_GAIN_ODD_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__TIA_GAIN_ODD_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__SLM_XLNA_ODD_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__BQ_GAIN_ODD_159___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__XLNA_GAIN_EVEN_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__LNA_GAIN_EVEN_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__GM_GAIN_EVEN_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__TIA_GAIN_EVEN_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__SLM_XLNA_EVEN_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__BQ_GAIN_EVEN_159___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__XLNA_GAIN_ODD_159___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__XLNA_GAIN_ODD_159___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__LNA_GAIN_ODD_159___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__LNA_GAIN_ODD_159___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__GM_GAIN_ODD_159___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__GM_GAIN_ODD_159___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__TIA_GAIN_ODD_159___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__TIA_GAIN_ODD_159___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__SLM_XLNA_ODD_159___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__SLM_XLNA_ODD_159___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__BQ_GAIN_ODD_159___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__BQ_GAIN_ODD_159___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__XLNA_GAIN_EVEN_159___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__XLNA_GAIN_EVEN_159___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__LNA_GAIN_EVEN_159___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__LNA_GAIN_EVEN_159___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__GM_GAIN_EVEN_159___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__GM_GAIN_EVEN_159___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__TIA_GAIN_EVEN_159___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__TIA_GAIN_EVEN_159___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__SLM_XLNA_EVEN_159___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__SLM_XLNA_EVEN_159___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__BQ_GAIN_EVEN_159___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159__BQ_GAIN_EVEN_159___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_159___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160 (0x005F5280) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__XLNA_GAIN_ODD_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__LNA_GAIN_ODD_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__GM_GAIN_ODD_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__TIA_GAIN_ODD_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__SLM_XLNA_ODD_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__BQ_GAIN_ODD_160___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__XLNA_GAIN_EVEN_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__LNA_GAIN_EVEN_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__GM_GAIN_EVEN_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__TIA_GAIN_EVEN_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__SLM_XLNA_EVEN_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__BQ_GAIN_EVEN_160___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__XLNA_GAIN_ODD_160___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__XLNA_GAIN_ODD_160___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__LNA_GAIN_ODD_160___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__LNA_GAIN_ODD_160___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__GM_GAIN_ODD_160___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__GM_GAIN_ODD_160___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__TIA_GAIN_ODD_160___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__TIA_GAIN_ODD_160___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__SLM_XLNA_ODD_160___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__SLM_XLNA_ODD_160___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__BQ_GAIN_ODD_160___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__BQ_GAIN_ODD_160___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__XLNA_GAIN_EVEN_160___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__XLNA_GAIN_EVEN_160___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__LNA_GAIN_EVEN_160___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__LNA_GAIN_EVEN_160___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__GM_GAIN_EVEN_160___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__GM_GAIN_EVEN_160___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__TIA_GAIN_EVEN_160___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__TIA_GAIN_EVEN_160___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__SLM_XLNA_EVEN_160___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__SLM_XLNA_EVEN_160___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__BQ_GAIN_EVEN_160___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160__BQ_GAIN_EVEN_160___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_160___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161 (0x005F5284) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__XLNA_GAIN_ODD_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__LNA_GAIN_ODD_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__GM_GAIN_ODD_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__TIA_GAIN_ODD_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__SLM_XLNA_ODD_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__BQ_GAIN_ODD_161___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__XLNA_GAIN_EVEN_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__LNA_GAIN_EVEN_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__GM_GAIN_EVEN_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__TIA_GAIN_EVEN_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__SLM_XLNA_EVEN_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__BQ_GAIN_EVEN_161___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__XLNA_GAIN_ODD_161___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__XLNA_GAIN_ODD_161___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__LNA_GAIN_ODD_161___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__LNA_GAIN_ODD_161___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__GM_GAIN_ODD_161___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__GM_GAIN_ODD_161___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__TIA_GAIN_ODD_161___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__TIA_GAIN_ODD_161___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__SLM_XLNA_ODD_161___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__SLM_XLNA_ODD_161___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__BQ_GAIN_ODD_161___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__BQ_GAIN_ODD_161___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__XLNA_GAIN_EVEN_161___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__XLNA_GAIN_EVEN_161___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__LNA_GAIN_EVEN_161___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__LNA_GAIN_EVEN_161___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__GM_GAIN_EVEN_161___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__GM_GAIN_EVEN_161___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__TIA_GAIN_EVEN_161___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__TIA_GAIN_EVEN_161___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__SLM_XLNA_EVEN_161___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__SLM_XLNA_EVEN_161___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__BQ_GAIN_EVEN_161___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161__BQ_GAIN_EVEN_161___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_161___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162 (0x005F5288) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__XLNA_GAIN_ODD_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__LNA_GAIN_ODD_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__GM_GAIN_ODD_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__TIA_GAIN_ODD_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__SLM_XLNA_ODD_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__BQ_GAIN_ODD_162___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__XLNA_GAIN_EVEN_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__LNA_GAIN_EVEN_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__GM_GAIN_EVEN_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__TIA_GAIN_EVEN_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__SLM_XLNA_EVEN_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__BQ_GAIN_EVEN_162___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__XLNA_GAIN_ODD_162___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__XLNA_GAIN_ODD_162___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__LNA_GAIN_ODD_162___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__LNA_GAIN_ODD_162___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__GM_GAIN_ODD_162___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__GM_GAIN_ODD_162___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__TIA_GAIN_ODD_162___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__TIA_GAIN_ODD_162___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__SLM_XLNA_ODD_162___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__SLM_XLNA_ODD_162___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__BQ_GAIN_ODD_162___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__BQ_GAIN_ODD_162___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__XLNA_GAIN_EVEN_162___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__XLNA_GAIN_EVEN_162___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__LNA_GAIN_EVEN_162___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__LNA_GAIN_EVEN_162___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__GM_GAIN_EVEN_162___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__GM_GAIN_EVEN_162___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__TIA_GAIN_EVEN_162___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__TIA_GAIN_EVEN_162___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__SLM_XLNA_EVEN_162___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__SLM_XLNA_EVEN_162___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__BQ_GAIN_EVEN_162___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162__BQ_GAIN_EVEN_162___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_162___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163 (0x005F528C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__XLNA_GAIN_ODD_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__LNA_GAIN_ODD_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__GM_GAIN_ODD_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__TIA_GAIN_ODD_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__SLM_XLNA_ODD_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__BQ_GAIN_ODD_163___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__XLNA_GAIN_EVEN_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__LNA_GAIN_EVEN_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__GM_GAIN_EVEN_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__TIA_GAIN_EVEN_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__SLM_XLNA_EVEN_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__BQ_GAIN_EVEN_163___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__XLNA_GAIN_ODD_163___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__XLNA_GAIN_ODD_163___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__LNA_GAIN_ODD_163___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__LNA_GAIN_ODD_163___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__GM_GAIN_ODD_163___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__GM_GAIN_ODD_163___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__TIA_GAIN_ODD_163___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__TIA_GAIN_ODD_163___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__SLM_XLNA_ODD_163___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__SLM_XLNA_ODD_163___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__BQ_GAIN_ODD_163___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__BQ_GAIN_ODD_163___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__XLNA_GAIN_EVEN_163___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__XLNA_GAIN_EVEN_163___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__LNA_GAIN_EVEN_163___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__LNA_GAIN_EVEN_163___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__GM_GAIN_EVEN_163___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__GM_GAIN_EVEN_163___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__TIA_GAIN_EVEN_163___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__TIA_GAIN_EVEN_163___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__SLM_XLNA_EVEN_163___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__SLM_XLNA_EVEN_163___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__BQ_GAIN_EVEN_163___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163__BQ_GAIN_EVEN_163___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_163___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164 (0x005F5290) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__XLNA_GAIN_ODD_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__LNA_GAIN_ODD_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__GM_GAIN_ODD_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__TIA_GAIN_ODD_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__SLM_XLNA_ODD_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__BQ_GAIN_ODD_164___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__XLNA_GAIN_EVEN_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__LNA_GAIN_EVEN_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__GM_GAIN_EVEN_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__TIA_GAIN_EVEN_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__SLM_XLNA_EVEN_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__BQ_GAIN_EVEN_164___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__XLNA_GAIN_ODD_164___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__XLNA_GAIN_ODD_164___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__LNA_GAIN_ODD_164___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__LNA_GAIN_ODD_164___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__GM_GAIN_ODD_164___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__GM_GAIN_ODD_164___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__TIA_GAIN_ODD_164___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__TIA_GAIN_ODD_164___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__SLM_XLNA_ODD_164___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__SLM_XLNA_ODD_164___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__BQ_GAIN_ODD_164___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__BQ_GAIN_ODD_164___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__XLNA_GAIN_EVEN_164___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__XLNA_GAIN_EVEN_164___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__LNA_GAIN_EVEN_164___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__LNA_GAIN_EVEN_164___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__GM_GAIN_EVEN_164___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__GM_GAIN_EVEN_164___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__TIA_GAIN_EVEN_164___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__TIA_GAIN_EVEN_164___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__SLM_XLNA_EVEN_164___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__SLM_XLNA_EVEN_164___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__BQ_GAIN_EVEN_164___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164__BQ_GAIN_EVEN_164___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_164___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165 (0x005F5294) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__XLNA_GAIN_ODD_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__LNA_GAIN_ODD_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__GM_GAIN_ODD_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__TIA_GAIN_ODD_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__SLM_XLNA_ODD_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__BQ_GAIN_ODD_165___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__XLNA_GAIN_EVEN_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__LNA_GAIN_EVEN_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__GM_GAIN_EVEN_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__TIA_GAIN_EVEN_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__SLM_XLNA_EVEN_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__BQ_GAIN_EVEN_165___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__XLNA_GAIN_ODD_165___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__XLNA_GAIN_ODD_165___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__LNA_GAIN_ODD_165___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__LNA_GAIN_ODD_165___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__GM_GAIN_ODD_165___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__GM_GAIN_ODD_165___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__TIA_GAIN_ODD_165___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__TIA_GAIN_ODD_165___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__SLM_XLNA_ODD_165___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__SLM_XLNA_ODD_165___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__BQ_GAIN_ODD_165___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__BQ_GAIN_ODD_165___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__XLNA_GAIN_EVEN_165___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__XLNA_GAIN_EVEN_165___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__LNA_GAIN_EVEN_165___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__LNA_GAIN_EVEN_165___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__GM_GAIN_EVEN_165___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__GM_GAIN_EVEN_165___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__TIA_GAIN_EVEN_165___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__TIA_GAIN_EVEN_165___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__SLM_XLNA_EVEN_165___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__SLM_XLNA_EVEN_165___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__BQ_GAIN_EVEN_165___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165__BQ_GAIN_EVEN_165___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_165___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166 (0x005F5298) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__XLNA_GAIN_ODD_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__LNA_GAIN_ODD_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__GM_GAIN_ODD_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__TIA_GAIN_ODD_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__SLM_XLNA_ODD_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__BQ_GAIN_ODD_166___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__XLNA_GAIN_EVEN_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__LNA_GAIN_EVEN_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__GM_GAIN_EVEN_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__TIA_GAIN_EVEN_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__SLM_XLNA_EVEN_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__BQ_GAIN_EVEN_166___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__XLNA_GAIN_ODD_166___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__XLNA_GAIN_ODD_166___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__LNA_GAIN_ODD_166___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__LNA_GAIN_ODD_166___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__GM_GAIN_ODD_166___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__GM_GAIN_ODD_166___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__TIA_GAIN_ODD_166___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__TIA_GAIN_ODD_166___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__SLM_XLNA_ODD_166___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__SLM_XLNA_ODD_166___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__BQ_GAIN_ODD_166___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__BQ_GAIN_ODD_166___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__XLNA_GAIN_EVEN_166___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__XLNA_GAIN_EVEN_166___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__LNA_GAIN_EVEN_166___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__LNA_GAIN_EVEN_166___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__GM_GAIN_EVEN_166___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__GM_GAIN_EVEN_166___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__TIA_GAIN_EVEN_166___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__TIA_GAIN_EVEN_166___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__SLM_XLNA_EVEN_166___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__SLM_XLNA_EVEN_166___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__BQ_GAIN_EVEN_166___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166__BQ_GAIN_EVEN_166___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_166___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167 (0x005F529C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__XLNA_GAIN_ODD_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__LNA_GAIN_ODD_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__GM_GAIN_ODD_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__TIA_GAIN_ODD_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__SLM_XLNA_ODD_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__BQ_GAIN_ODD_167___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__XLNA_GAIN_EVEN_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__LNA_GAIN_EVEN_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__GM_GAIN_EVEN_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__TIA_GAIN_EVEN_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__SLM_XLNA_EVEN_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__BQ_GAIN_EVEN_167___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__XLNA_GAIN_ODD_167___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__XLNA_GAIN_ODD_167___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__LNA_GAIN_ODD_167___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__LNA_GAIN_ODD_167___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__GM_GAIN_ODD_167___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__GM_GAIN_ODD_167___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__TIA_GAIN_ODD_167___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__TIA_GAIN_ODD_167___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__SLM_XLNA_ODD_167___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__SLM_XLNA_ODD_167___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__BQ_GAIN_ODD_167___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__BQ_GAIN_ODD_167___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__XLNA_GAIN_EVEN_167___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__XLNA_GAIN_EVEN_167___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__LNA_GAIN_EVEN_167___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__LNA_GAIN_EVEN_167___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__GM_GAIN_EVEN_167___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__GM_GAIN_EVEN_167___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__TIA_GAIN_EVEN_167___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__TIA_GAIN_EVEN_167___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__SLM_XLNA_EVEN_167___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__SLM_XLNA_EVEN_167___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__BQ_GAIN_EVEN_167___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167__BQ_GAIN_EVEN_167___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_167___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168 (0x005F52A0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__XLNA_GAIN_ODD_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__LNA_GAIN_ODD_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__GM_GAIN_ODD_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__TIA_GAIN_ODD_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__SLM_XLNA_ODD_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__BQ_GAIN_ODD_168___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__XLNA_GAIN_EVEN_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__LNA_GAIN_EVEN_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__GM_GAIN_EVEN_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__TIA_GAIN_EVEN_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__SLM_XLNA_EVEN_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__BQ_GAIN_EVEN_168___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__XLNA_GAIN_ODD_168___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__XLNA_GAIN_ODD_168___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__LNA_GAIN_ODD_168___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__LNA_GAIN_ODD_168___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__GM_GAIN_ODD_168___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__GM_GAIN_ODD_168___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__TIA_GAIN_ODD_168___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__TIA_GAIN_ODD_168___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__SLM_XLNA_ODD_168___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__SLM_XLNA_ODD_168___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__BQ_GAIN_ODD_168___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__BQ_GAIN_ODD_168___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__XLNA_GAIN_EVEN_168___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__XLNA_GAIN_EVEN_168___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__LNA_GAIN_EVEN_168___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__LNA_GAIN_EVEN_168___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__GM_GAIN_EVEN_168___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__GM_GAIN_EVEN_168___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__TIA_GAIN_EVEN_168___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__TIA_GAIN_EVEN_168___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__SLM_XLNA_EVEN_168___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__SLM_XLNA_EVEN_168___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__BQ_GAIN_EVEN_168___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168__BQ_GAIN_EVEN_168___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_168___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169 (0x005F52A4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__XLNA_GAIN_ODD_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__LNA_GAIN_ODD_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__GM_GAIN_ODD_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__TIA_GAIN_ODD_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__SLM_XLNA_ODD_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__BQ_GAIN_ODD_169___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__XLNA_GAIN_EVEN_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__LNA_GAIN_EVEN_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__GM_GAIN_EVEN_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__TIA_GAIN_EVEN_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__SLM_XLNA_EVEN_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__BQ_GAIN_EVEN_169___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__XLNA_GAIN_ODD_169___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__XLNA_GAIN_ODD_169___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__LNA_GAIN_ODD_169___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__LNA_GAIN_ODD_169___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__GM_GAIN_ODD_169___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__GM_GAIN_ODD_169___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__TIA_GAIN_ODD_169___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__TIA_GAIN_ODD_169___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__SLM_XLNA_ODD_169___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__SLM_XLNA_ODD_169___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__BQ_GAIN_ODD_169___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__BQ_GAIN_ODD_169___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__XLNA_GAIN_EVEN_169___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__XLNA_GAIN_EVEN_169___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__LNA_GAIN_EVEN_169___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__LNA_GAIN_EVEN_169___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__GM_GAIN_EVEN_169___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__GM_GAIN_EVEN_169___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__TIA_GAIN_EVEN_169___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__TIA_GAIN_EVEN_169___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__SLM_XLNA_EVEN_169___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__SLM_XLNA_EVEN_169___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__BQ_GAIN_EVEN_169___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169__BQ_GAIN_EVEN_169___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_169___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170 (0x005F52A8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__XLNA_GAIN_ODD_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__LNA_GAIN_ODD_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__GM_GAIN_ODD_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__TIA_GAIN_ODD_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__SLM_XLNA_ODD_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__BQ_GAIN_ODD_170___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__XLNA_GAIN_EVEN_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__LNA_GAIN_EVEN_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__GM_GAIN_EVEN_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__TIA_GAIN_EVEN_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__SLM_XLNA_EVEN_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__BQ_GAIN_EVEN_170___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__XLNA_GAIN_ODD_170___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__XLNA_GAIN_ODD_170___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__LNA_GAIN_ODD_170___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__LNA_GAIN_ODD_170___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__GM_GAIN_ODD_170___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__GM_GAIN_ODD_170___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__TIA_GAIN_ODD_170___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__TIA_GAIN_ODD_170___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__SLM_XLNA_ODD_170___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__SLM_XLNA_ODD_170___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__BQ_GAIN_ODD_170___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__BQ_GAIN_ODD_170___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__XLNA_GAIN_EVEN_170___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__XLNA_GAIN_EVEN_170___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__LNA_GAIN_EVEN_170___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__LNA_GAIN_EVEN_170___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__GM_GAIN_EVEN_170___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__GM_GAIN_EVEN_170___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__TIA_GAIN_EVEN_170___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__TIA_GAIN_EVEN_170___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__SLM_XLNA_EVEN_170___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__SLM_XLNA_EVEN_170___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__BQ_GAIN_EVEN_170___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170__BQ_GAIN_EVEN_170___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_170___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171 (0x005F52AC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__XLNA_GAIN_ODD_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__LNA_GAIN_ODD_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__GM_GAIN_ODD_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__TIA_GAIN_ODD_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__SLM_XLNA_ODD_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__BQ_GAIN_ODD_171___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__XLNA_GAIN_EVEN_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__LNA_GAIN_EVEN_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__GM_GAIN_EVEN_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__TIA_GAIN_EVEN_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__SLM_XLNA_EVEN_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__BQ_GAIN_EVEN_171___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__XLNA_GAIN_ODD_171___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__XLNA_GAIN_ODD_171___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__LNA_GAIN_ODD_171___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__LNA_GAIN_ODD_171___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__GM_GAIN_ODD_171___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__GM_GAIN_ODD_171___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__TIA_GAIN_ODD_171___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__TIA_GAIN_ODD_171___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__SLM_XLNA_ODD_171___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__SLM_XLNA_ODD_171___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__BQ_GAIN_ODD_171___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__BQ_GAIN_ODD_171___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__XLNA_GAIN_EVEN_171___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__XLNA_GAIN_EVEN_171___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__LNA_GAIN_EVEN_171___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__LNA_GAIN_EVEN_171___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__GM_GAIN_EVEN_171___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__GM_GAIN_EVEN_171___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__TIA_GAIN_EVEN_171___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__TIA_GAIN_EVEN_171___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__SLM_XLNA_EVEN_171___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__SLM_XLNA_EVEN_171___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__BQ_GAIN_EVEN_171___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171__BQ_GAIN_EVEN_171___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_171___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172 (0x005F52B0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__XLNA_GAIN_ODD_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__LNA_GAIN_ODD_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__GM_GAIN_ODD_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__TIA_GAIN_ODD_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__SLM_XLNA_ODD_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__BQ_GAIN_ODD_172___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__XLNA_GAIN_EVEN_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__LNA_GAIN_EVEN_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__GM_GAIN_EVEN_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__TIA_GAIN_EVEN_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__SLM_XLNA_EVEN_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__BQ_GAIN_EVEN_172___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__XLNA_GAIN_ODD_172___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__XLNA_GAIN_ODD_172___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__LNA_GAIN_ODD_172___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__LNA_GAIN_ODD_172___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__GM_GAIN_ODD_172___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__GM_GAIN_ODD_172___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__TIA_GAIN_ODD_172___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__TIA_GAIN_ODD_172___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__SLM_XLNA_ODD_172___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__SLM_XLNA_ODD_172___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__BQ_GAIN_ODD_172___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__BQ_GAIN_ODD_172___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__XLNA_GAIN_EVEN_172___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__XLNA_GAIN_EVEN_172___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__LNA_GAIN_EVEN_172___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__LNA_GAIN_EVEN_172___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__GM_GAIN_EVEN_172___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__GM_GAIN_EVEN_172___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__TIA_GAIN_EVEN_172___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__TIA_GAIN_EVEN_172___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__SLM_XLNA_EVEN_172___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__SLM_XLNA_EVEN_172___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__BQ_GAIN_EVEN_172___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172__BQ_GAIN_EVEN_172___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_172___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173 (0x005F52B4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__XLNA_GAIN_ODD_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__LNA_GAIN_ODD_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__GM_GAIN_ODD_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__TIA_GAIN_ODD_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__SLM_XLNA_ODD_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__BQ_GAIN_ODD_173___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__XLNA_GAIN_EVEN_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__LNA_GAIN_EVEN_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__GM_GAIN_EVEN_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__TIA_GAIN_EVEN_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__SLM_XLNA_EVEN_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__BQ_GAIN_EVEN_173___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__XLNA_GAIN_ODD_173___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__XLNA_GAIN_ODD_173___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__LNA_GAIN_ODD_173___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__LNA_GAIN_ODD_173___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__GM_GAIN_ODD_173___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__GM_GAIN_ODD_173___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__TIA_GAIN_ODD_173___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__TIA_GAIN_ODD_173___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__SLM_XLNA_ODD_173___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__SLM_XLNA_ODD_173___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__BQ_GAIN_ODD_173___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__BQ_GAIN_ODD_173___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__XLNA_GAIN_EVEN_173___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__XLNA_GAIN_EVEN_173___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__LNA_GAIN_EVEN_173___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__LNA_GAIN_EVEN_173___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__GM_GAIN_EVEN_173___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__GM_GAIN_EVEN_173___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__TIA_GAIN_EVEN_173___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__TIA_GAIN_EVEN_173___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__SLM_XLNA_EVEN_173___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__SLM_XLNA_EVEN_173___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__BQ_GAIN_EVEN_173___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173__BQ_GAIN_EVEN_173___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_173___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174 (0x005F52B8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__XLNA_GAIN_ODD_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__LNA_GAIN_ODD_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__GM_GAIN_ODD_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__TIA_GAIN_ODD_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__SLM_XLNA_ODD_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__BQ_GAIN_ODD_174___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__XLNA_GAIN_EVEN_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__LNA_GAIN_EVEN_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__GM_GAIN_EVEN_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__TIA_GAIN_EVEN_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__SLM_XLNA_EVEN_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__BQ_GAIN_EVEN_174___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__XLNA_GAIN_ODD_174___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__XLNA_GAIN_ODD_174___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__LNA_GAIN_ODD_174___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__LNA_GAIN_ODD_174___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__GM_GAIN_ODD_174___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__GM_GAIN_ODD_174___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__TIA_GAIN_ODD_174___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__TIA_GAIN_ODD_174___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__SLM_XLNA_ODD_174___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__SLM_XLNA_ODD_174___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__BQ_GAIN_ODD_174___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__BQ_GAIN_ODD_174___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__XLNA_GAIN_EVEN_174___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__XLNA_GAIN_EVEN_174___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__LNA_GAIN_EVEN_174___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__LNA_GAIN_EVEN_174___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__GM_GAIN_EVEN_174___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__GM_GAIN_EVEN_174___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__TIA_GAIN_EVEN_174___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__TIA_GAIN_EVEN_174___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__SLM_XLNA_EVEN_174___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__SLM_XLNA_EVEN_174___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__BQ_GAIN_EVEN_174___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174__BQ_GAIN_EVEN_174___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_174___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175 (0x005F52BC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__XLNA_GAIN_ODD_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__LNA_GAIN_ODD_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__GM_GAIN_ODD_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__TIA_GAIN_ODD_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__SLM_XLNA_ODD_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__BQ_GAIN_ODD_175___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__XLNA_GAIN_EVEN_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__LNA_GAIN_EVEN_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__GM_GAIN_EVEN_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__TIA_GAIN_EVEN_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__SLM_XLNA_EVEN_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__BQ_GAIN_EVEN_175___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__XLNA_GAIN_ODD_175___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__XLNA_GAIN_ODD_175___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__LNA_GAIN_ODD_175___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__LNA_GAIN_ODD_175___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__GM_GAIN_ODD_175___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__GM_GAIN_ODD_175___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__TIA_GAIN_ODD_175___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__TIA_GAIN_ODD_175___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__SLM_XLNA_ODD_175___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__SLM_XLNA_ODD_175___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__BQ_GAIN_ODD_175___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__BQ_GAIN_ODD_175___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__XLNA_GAIN_EVEN_175___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__XLNA_GAIN_EVEN_175___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__LNA_GAIN_EVEN_175___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__LNA_GAIN_EVEN_175___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__GM_GAIN_EVEN_175___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__GM_GAIN_EVEN_175___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__TIA_GAIN_EVEN_175___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__TIA_GAIN_EVEN_175___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__SLM_XLNA_EVEN_175___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__SLM_XLNA_EVEN_175___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__BQ_GAIN_EVEN_175___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175__BQ_GAIN_EVEN_175___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_175___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176 (0x005F52C0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__XLNA_GAIN_ODD_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__LNA_GAIN_ODD_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__GM_GAIN_ODD_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__TIA_GAIN_ODD_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__SLM_XLNA_ODD_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__BQ_GAIN_ODD_176___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__XLNA_GAIN_EVEN_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__LNA_GAIN_EVEN_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__GM_GAIN_EVEN_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__TIA_GAIN_EVEN_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__SLM_XLNA_EVEN_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__BQ_GAIN_EVEN_176___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__XLNA_GAIN_ODD_176___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__XLNA_GAIN_ODD_176___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__LNA_GAIN_ODD_176___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__LNA_GAIN_ODD_176___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__GM_GAIN_ODD_176___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__GM_GAIN_ODD_176___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__TIA_GAIN_ODD_176___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__TIA_GAIN_ODD_176___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__SLM_XLNA_ODD_176___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__SLM_XLNA_ODD_176___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__BQ_GAIN_ODD_176___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__BQ_GAIN_ODD_176___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__XLNA_GAIN_EVEN_176___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__XLNA_GAIN_EVEN_176___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__LNA_GAIN_EVEN_176___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__LNA_GAIN_EVEN_176___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__GM_GAIN_EVEN_176___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__GM_GAIN_EVEN_176___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__TIA_GAIN_EVEN_176___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__TIA_GAIN_EVEN_176___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__SLM_XLNA_EVEN_176___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__SLM_XLNA_EVEN_176___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__BQ_GAIN_EVEN_176___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176__BQ_GAIN_EVEN_176___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_176___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177 (0x005F52C4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__XLNA_GAIN_ODD_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__LNA_GAIN_ODD_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__GM_GAIN_ODD_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__TIA_GAIN_ODD_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__SLM_XLNA_ODD_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__BQ_GAIN_ODD_177___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__XLNA_GAIN_EVEN_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__LNA_GAIN_EVEN_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__GM_GAIN_EVEN_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__TIA_GAIN_EVEN_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__SLM_XLNA_EVEN_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__BQ_GAIN_EVEN_177___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__XLNA_GAIN_ODD_177___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__XLNA_GAIN_ODD_177___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__LNA_GAIN_ODD_177___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__LNA_GAIN_ODD_177___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__GM_GAIN_ODD_177___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__GM_GAIN_ODD_177___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__TIA_GAIN_ODD_177___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__TIA_GAIN_ODD_177___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__SLM_XLNA_ODD_177___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__SLM_XLNA_ODD_177___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__BQ_GAIN_ODD_177___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__BQ_GAIN_ODD_177___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__XLNA_GAIN_EVEN_177___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__XLNA_GAIN_EVEN_177___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__LNA_GAIN_EVEN_177___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__LNA_GAIN_EVEN_177___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__GM_GAIN_EVEN_177___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__GM_GAIN_EVEN_177___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__TIA_GAIN_EVEN_177___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__TIA_GAIN_EVEN_177___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__SLM_XLNA_EVEN_177___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__SLM_XLNA_EVEN_177___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__BQ_GAIN_EVEN_177___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177__BQ_GAIN_EVEN_177___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_177___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178 (0x005F52C8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__XLNA_GAIN_ODD_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__LNA_GAIN_ODD_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__GM_GAIN_ODD_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__TIA_GAIN_ODD_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__SLM_XLNA_ODD_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__BQ_GAIN_ODD_178___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__XLNA_GAIN_EVEN_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__LNA_GAIN_EVEN_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__GM_GAIN_EVEN_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__TIA_GAIN_EVEN_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__SLM_XLNA_EVEN_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__BQ_GAIN_EVEN_178___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__XLNA_GAIN_ODD_178___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__XLNA_GAIN_ODD_178___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__LNA_GAIN_ODD_178___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__LNA_GAIN_ODD_178___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__GM_GAIN_ODD_178___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__GM_GAIN_ODD_178___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__TIA_GAIN_ODD_178___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__TIA_GAIN_ODD_178___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__SLM_XLNA_ODD_178___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__SLM_XLNA_ODD_178___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__BQ_GAIN_ODD_178___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__BQ_GAIN_ODD_178___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__XLNA_GAIN_EVEN_178___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__XLNA_GAIN_EVEN_178___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__LNA_GAIN_EVEN_178___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__LNA_GAIN_EVEN_178___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__GM_GAIN_EVEN_178___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__GM_GAIN_EVEN_178___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__TIA_GAIN_EVEN_178___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__TIA_GAIN_EVEN_178___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__SLM_XLNA_EVEN_178___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__SLM_XLNA_EVEN_178___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__BQ_GAIN_EVEN_178___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178__BQ_GAIN_EVEN_178___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_178___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179 (0x005F52CC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__XLNA_GAIN_ODD_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__LNA_GAIN_ODD_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__GM_GAIN_ODD_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__TIA_GAIN_ODD_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__SLM_XLNA_ODD_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__BQ_GAIN_ODD_179___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__XLNA_GAIN_EVEN_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__LNA_GAIN_EVEN_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__GM_GAIN_EVEN_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__TIA_GAIN_EVEN_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__SLM_XLNA_EVEN_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__BQ_GAIN_EVEN_179___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__XLNA_GAIN_ODD_179___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__XLNA_GAIN_ODD_179___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__LNA_GAIN_ODD_179___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__LNA_GAIN_ODD_179___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__GM_GAIN_ODD_179___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__GM_GAIN_ODD_179___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__TIA_GAIN_ODD_179___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__TIA_GAIN_ODD_179___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__SLM_XLNA_ODD_179___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__SLM_XLNA_ODD_179___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__BQ_GAIN_ODD_179___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__BQ_GAIN_ODD_179___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__XLNA_GAIN_EVEN_179___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__XLNA_GAIN_EVEN_179___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__LNA_GAIN_EVEN_179___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__LNA_GAIN_EVEN_179___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__GM_GAIN_EVEN_179___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__GM_GAIN_EVEN_179___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__TIA_GAIN_EVEN_179___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__TIA_GAIN_EVEN_179___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__SLM_XLNA_EVEN_179___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__SLM_XLNA_EVEN_179___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__BQ_GAIN_EVEN_179___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179__BQ_GAIN_EVEN_179___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_179___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180 (0x005F52D0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__XLNA_GAIN_ODD_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__LNA_GAIN_ODD_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__GM_GAIN_ODD_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__TIA_GAIN_ODD_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__SLM_XLNA_ODD_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__BQ_GAIN_ODD_180___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__XLNA_GAIN_EVEN_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__LNA_GAIN_EVEN_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__GM_GAIN_EVEN_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__TIA_GAIN_EVEN_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__SLM_XLNA_EVEN_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__BQ_GAIN_EVEN_180___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__XLNA_GAIN_ODD_180___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__XLNA_GAIN_ODD_180___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__LNA_GAIN_ODD_180___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__LNA_GAIN_ODD_180___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__GM_GAIN_ODD_180___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__GM_GAIN_ODD_180___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__TIA_GAIN_ODD_180___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__TIA_GAIN_ODD_180___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__SLM_XLNA_ODD_180___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__SLM_XLNA_ODD_180___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__BQ_GAIN_ODD_180___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__BQ_GAIN_ODD_180___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__XLNA_GAIN_EVEN_180___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__XLNA_GAIN_EVEN_180___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__LNA_GAIN_EVEN_180___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__LNA_GAIN_EVEN_180___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__GM_GAIN_EVEN_180___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__GM_GAIN_EVEN_180___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__TIA_GAIN_EVEN_180___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__TIA_GAIN_EVEN_180___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__SLM_XLNA_EVEN_180___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__SLM_XLNA_EVEN_180___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__BQ_GAIN_EVEN_180___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180__BQ_GAIN_EVEN_180___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_180___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181 (0x005F52D4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__XLNA_GAIN_ODD_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__LNA_GAIN_ODD_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__GM_GAIN_ODD_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__TIA_GAIN_ODD_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__SLM_XLNA_ODD_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__BQ_GAIN_ODD_181___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__XLNA_GAIN_EVEN_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__LNA_GAIN_EVEN_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__GM_GAIN_EVEN_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__TIA_GAIN_EVEN_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__SLM_XLNA_EVEN_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__BQ_GAIN_EVEN_181___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__XLNA_GAIN_ODD_181___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__XLNA_GAIN_ODD_181___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__LNA_GAIN_ODD_181___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__LNA_GAIN_ODD_181___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__GM_GAIN_ODD_181___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__GM_GAIN_ODD_181___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__TIA_GAIN_ODD_181___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__TIA_GAIN_ODD_181___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__SLM_XLNA_ODD_181___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__SLM_XLNA_ODD_181___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__BQ_GAIN_ODD_181___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__BQ_GAIN_ODD_181___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__XLNA_GAIN_EVEN_181___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__XLNA_GAIN_EVEN_181___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__LNA_GAIN_EVEN_181___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__LNA_GAIN_EVEN_181___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__GM_GAIN_EVEN_181___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__GM_GAIN_EVEN_181___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__TIA_GAIN_EVEN_181___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__TIA_GAIN_EVEN_181___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__SLM_XLNA_EVEN_181___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__SLM_XLNA_EVEN_181___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__BQ_GAIN_EVEN_181___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181__BQ_GAIN_EVEN_181___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_181___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182 (0x005F52D8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__XLNA_GAIN_ODD_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__LNA_GAIN_ODD_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__GM_GAIN_ODD_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__TIA_GAIN_ODD_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__SLM_XLNA_ODD_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__BQ_GAIN_ODD_182___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__XLNA_GAIN_EVEN_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__LNA_GAIN_EVEN_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__GM_GAIN_EVEN_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__TIA_GAIN_EVEN_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__SLM_XLNA_EVEN_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__BQ_GAIN_EVEN_182___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__XLNA_GAIN_ODD_182___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__XLNA_GAIN_ODD_182___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__LNA_GAIN_ODD_182___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__LNA_GAIN_ODD_182___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__GM_GAIN_ODD_182___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__GM_GAIN_ODD_182___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__TIA_GAIN_ODD_182___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__TIA_GAIN_ODD_182___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__SLM_XLNA_ODD_182___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__SLM_XLNA_ODD_182___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__BQ_GAIN_ODD_182___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__BQ_GAIN_ODD_182___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__XLNA_GAIN_EVEN_182___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__XLNA_GAIN_EVEN_182___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__LNA_GAIN_EVEN_182___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__LNA_GAIN_EVEN_182___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__GM_GAIN_EVEN_182___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__GM_GAIN_EVEN_182___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__TIA_GAIN_EVEN_182___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__TIA_GAIN_EVEN_182___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__SLM_XLNA_EVEN_182___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__SLM_XLNA_EVEN_182___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__BQ_GAIN_EVEN_182___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182__BQ_GAIN_EVEN_182___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_182___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183 (0x005F52DC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__XLNA_GAIN_ODD_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__LNA_GAIN_ODD_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__GM_GAIN_ODD_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__TIA_GAIN_ODD_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__SLM_XLNA_ODD_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__BQ_GAIN_ODD_183___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__XLNA_GAIN_EVEN_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__LNA_GAIN_EVEN_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__GM_GAIN_EVEN_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__TIA_GAIN_EVEN_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__SLM_XLNA_EVEN_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__BQ_GAIN_EVEN_183___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__XLNA_GAIN_ODD_183___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__XLNA_GAIN_ODD_183___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__LNA_GAIN_ODD_183___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__LNA_GAIN_ODD_183___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__GM_GAIN_ODD_183___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__GM_GAIN_ODD_183___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__TIA_GAIN_ODD_183___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__TIA_GAIN_ODD_183___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__SLM_XLNA_ODD_183___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__SLM_XLNA_ODD_183___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__BQ_GAIN_ODD_183___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__BQ_GAIN_ODD_183___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__XLNA_GAIN_EVEN_183___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__XLNA_GAIN_EVEN_183___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__LNA_GAIN_EVEN_183___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__LNA_GAIN_EVEN_183___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__GM_GAIN_EVEN_183___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__GM_GAIN_EVEN_183___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__TIA_GAIN_EVEN_183___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__TIA_GAIN_EVEN_183___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__SLM_XLNA_EVEN_183___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__SLM_XLNA_EVEN_183___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__BQ_GAIN_EVEN_183___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183__BQ_GAIN_EVEN_183___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_183___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184 (0x005F52E0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__XLNA_GAIN_ODD_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__LNA_GAIN_ODD_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__GM_GAIN_ODD_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__TIA_GAIN_ODD_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__SLM_XLNA_ODD_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__BQ_GAIN_ODD_184___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__XLNA_GAIN_EVEN_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__LNA_GAIN_EVEN_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__GM_GAIN_EVEN_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__TIA_GAIN_EVEN_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__SLM_XLNA_EVEN_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__BQ_GAIN_EVEN_184___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__XLNA_GAIN_ODD_184___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__XLNA_GAIN_ODD_184___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__LNA_GAIN_ODD_184___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__LNA_GAIN_ODD_184___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__GM_GAIN_ODD_184___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__GM_GAIN_ODD_184___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__TIA_GAIN_ODD_184___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__TIA_GAIN_ODD_184___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__SLM_XLNA_ODD_184___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__SLM_XLNA_ODD_184___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__BQ_GAIN_ODD_184___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__BQ_GAIN_ODD_184___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__XLNA_GAIN_EVEN_184___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__XLNA_GAIN_EVEN_184___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__LNA_GAIN_EVEN_184___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__LNA_GAIN_EVEN_184___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__GM_GAIN_EVEN_184___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__GM_GAIN_EVEN_184___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__TIA_GAIN_EVEN_184___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__TIA_GAIN_EVEN_184___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__SLM_XLNA_EVEN_184___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__SLM_XLNA_EVEN_184___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__BQ_GAIN_EVEN_184___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184__BQ_GAIN_EVEN_184___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_184___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185 (0x005F52E4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__XLNA_GAIN_ODD_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__LNA_GAIN_ODD_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__GM_GAIN_ODD_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__TIA_GAIN_ODD_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__SLM_XLNA_ODD_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__BQ_GAIN_ODD_185___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__XLNA_GAIN_EVEN_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__LNA_GAIN_EVEN_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__GM_GAIN_EVEN_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__TIA_GAIN_EVEN_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__SLM_XLNA_EVEN_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__BQ_GAIN_EVEN_185___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__XLNA_GAIN_ODD_185___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__XLNA_GAIN_ODD_185___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__LNA_GAIN_ODD_185___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__LNA_GAIN_ODD_185___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__GM_GAIN_ODD_185___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__GM_GAIN_ODD_185___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__TIA_GAIN_ODD_185___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__TIA_GAIN_ODD_185___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__SLM_XLNA_ODD_185___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__SLM_XLNA_ODD_185___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__BQ_GAIN_ODD_185___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__BQ_GAIN_ODD_185___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__XLNA_GAIN_EVEN_185___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__XLNA_GAIN_EVEN_185___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__LNA_GAIN_EVEN_185___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__LNA_GAIN_EVEN_185___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__GM_GAIN_EVEN_185___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__GM_GAIN_EVEN_185___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__TIA_GAIN_EVEN_185___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__TIA_GAIN_EVEN_185___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__SLM_XLNA_EVEN_185___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__SLM_XLNA_EVEN_185___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__BQ_GAIN_EVEN_185___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185__BQ_GAIN_EVEN_185___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_185___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186 (0x005F52E8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__XLNA_GAIN_ODD_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__LNA_GAIN_ODD_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__GM_GAIN_ODD_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__TIA_GAIN_ODD_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__SLM_XLNA_ODD_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__BQ_GAIN_ODD_186___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__XLNA_GAIN_EVEN_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__LNA_GAIN_EVEN_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__GM_GAIN_EVEN_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__TIA_GAIN_EVEN_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__SLM_XLNA_EVEN_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__BQ_GAIN_EVEN_186___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__XLNA_GAIN_ODD_186___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__XLNA_GAIN_ODD_186___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__LNA_GAIN_ODD_186___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__LNA_GAIN_ODD_186___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__GM_GAIN_ODD_186___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__GM_GAIN_ODD_186___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__TIA_GAIN_ODD_186___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__TIA_GAIN_ODD_186___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__SLM_XLNA_ODD_186___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__SLM_XLNA_ODD_186___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__BQ_GAIN_ODD_186___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__BQ_GAIN_ODD_186___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__XLNA_GAIN_EVEN_186___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__XLNA_GAIN_EVEN_186___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__LNA_GAIN_EVEN_186___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__LNA_GAIN_EVEN_186___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__GM_GAIN_EVEN_186___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__GM_GAIN_EVEN_186___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__TIA_GAIN_EVEN_186___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__TIA_GAIN_EVEN_186___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__SLM_XLNA_EVEN_186___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__SLM_XLNA_EVEN_186___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__BQ_GAIN_EVEN_186___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186__BQ_GAIN_EVEN_186___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_186___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187 (0x005F52EC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__XLNA_GAIN_ODD_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__LNA_GAIN_ODD_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__GM_GAIN_ODD_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__TIA_GAIN_ODD_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__SLM_XLNA_ODD_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__BQ_GAIN_ODD_187___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__XLNA_GAIN_EVEN_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__LNA_GAIN_EVEN_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__GM_GAIN_EVEN_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__TIA_GAIN_EVEN_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__SLM_XLNA_EVEN_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__BQ_GAIN_EVEN_187___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__XLNA_GAIN_ODD_187___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__XLNA_GAIN_ODD_187___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__LNA_GAIN_ODD_187___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__LNA_GAIN_ODD_187___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__GM_GAIN_ODD_187___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__GM_GAIN_ODD_187___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__TIA_GAIN_ODD_187___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__TIA_GAIN_ODD_187___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__SLM_XLNA_ODD_187___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__SLM_XLNA_ODD_187___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__BQ_GAIN_ODD_187___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__BQ_GAIN_ODD_187___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__XLNA_GAIN_EVEN_187___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__XLNA_GAIN_EVEN_187___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__LNA_GAIN_EVEN_187___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__LNA_GAIN_EVEN_187___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__GM_GAIN_EVEN_187___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__GM_GAIN_EVEN_187___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__TIA_GAIN_EVEN_187___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__TIA_GAIN_EVEN_187___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__SLM_XLNA_EVEN_187___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__SLM_XLNA_EVEN_187___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__BQ_GAIN_EVEN_187___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187__BQ_GAIN_EVEN_187___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_187___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188 (0x005F52F0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__XLNA_GAIN_ODD_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__LNA_GAIN_ODD_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__GM_GAIN_ODD_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__TIA_GAIN_ODD_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__SLM_XLNA_ODD_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__BQ_GAIN_ODD_188___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__XLNA_GAIN_EVEN_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__LNA_GAIN_EVEN_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__GM_GAIN_EVEN_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__TIA_GAIN_EVEN_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__SLM_XLNA_EVEN_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__BQ_GAIN_EVEN_188___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__XLNA_GAIN_ODD_188___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__XLNA_GAIN_ODD_188___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__LNA_GAIN_ODD_188___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__LNA_GAIN_ODD_188___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__GM_GAIN_ODD_188___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__GM_GAIN_ODD_188___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__TIA_GAIN_ODD_188___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__TIA_GAIN_ODD_188___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__SLM_XLNA_ODD_188___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__SLM_XLNA_ODD_188___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__BQ_GAIN_ODD_188___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__BQ_GAIN_ODD_188___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__XLNA_GAIN_EVEN_188___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__XLNA_GAIN_EVEN_188___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__LNA_GAIN_EVEN_188___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__LNA_GAIN_EVEN_188___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__GM_GAIN_EVEN_188___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__GM_GAIN_EVEN_188___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__TIA_GAIN_EVEN_188___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__TIA_GAIN_EVEN_188___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__SLM_XLNA_EVEN_188___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__SLM_XLNA_EVEN_188___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__BQ_GAIN_EVEN_188___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188__BQ_GAIN_EVEN_188___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_188___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189 (0x005F52F4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__XLNA_GAIN_ODD_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__LNA_GAIN_ODD_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__GM_GAIN_ODD_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__TIA_GAIN_ODD_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__SLM_XLNA_ODD_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__BQ_GAIN_ODD_189___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__XLNA_GAIN_EVEN_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__LNA_GAIN_EVEN_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__GM_GAIN_EVEN_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__TIA_GAIN_EVEN_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__SLM_XLNA_EVEN_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__BQ_GAIN_EVEN_189___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__XLNA_GAIN_ODD_189___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__XLNA_GAIN_ODD_189___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__LNA_GAIN_ODD_189___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__LNA_GAIN_ODD_189___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__GM_GAIN_ODD_189___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__GM_GAIN_ODD_189___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__TIA_GAIN_ODD_189___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__TIA_GAIN_ODD_189___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__SLM_XLNA_ODD_189___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__SLM_XLNA_ODD_189___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__BQ_GAIN_ODD_189___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__BQ_GAIN_ODD_189___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__XLNA_GAIN_EVEN_189___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__XLNA_GAIN_EVEN_189___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__LNA_GAIN_EVEN_189___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__LNA_GAIN_EVEN_189___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__GM_GAIN_EVEN_189___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__GM_GAIN_EVEN_189___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__TIA_GAIN_EVEN_189___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__TIA_GAIN_EVEN_189___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__SLM_XLNA_EVEN_189___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__SLM_XLNA_EVEN_189___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__BQ_GAIN_EVEN_189___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189__BQ_GAIN_EVEN_189___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_189___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190 (0x005F52F8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__XLNA_GAIN_ODD_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__LNA_GAIN_ODD_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__GM_GAIN_ODD_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__TIA_GAIN_ODD_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__SLM_XLNA_ODD_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__BQ_GAIN_ODD_190___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__XLNA_GAIN_EVEN_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__LNA_GAIN_EVEN_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__GM_GAIN_EVEN_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__TIA_GAIN_EVEN_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__SLM_XLNA_EVEN_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__BQ_GAIN_EVEN_190___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__XLNA_GAIN_ODD_190___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__XLNA_GAIN_ODD_190___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__LNA_GAIN_ODD_190___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__LNA_GAIN_ODD_190___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__GM_GAIN_ODD_190___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__GM_GAIN_ODD_190___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__TIA_GAIN_ODD_190___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__TIA_GAIN_ODD_190___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__SLM_XLNA_ODD_190___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__SLM_XLNA_ODD_190___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__BQ_GAIN_ODD_190___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__BQ_GAIN_ODD_190___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__XLNA_GAIN_EVEN_190___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__XLNA_GAIN_EVEN_190___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__LNA_GAIN_EVEN_190___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__LNA_GAIN_EVEN_190___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__GM_GAIN_EVEN_190___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__GM_GAIN_EVEN_190___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__TIA_GAIN_EVEN_190___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__TIA_GAIN_EVEN_190___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__SLM_XLNA_EVEN_190___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__SLM_XLNA_EVEN_190___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__BQ_GAIN_EVEN_190___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190__BQ_GAIN_EVEN_190___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_190___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191 (0x005F52FC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__XLNA_GAIN_ODD_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__LNA_GAIN_ODD_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__GM_GAIN_ODD_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__TIA_GAIN_ODD_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__SLM_XLNA_ODD_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__BQ_GAIN_ODD_191___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__XLNA_GAIN_EVEN_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__LNA_GAIN_EVEN_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__GM_GAIN_EVEN_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__TIA_GAIN_EVEN_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__SLM_XLNA_EVEN_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__BQ_GAIN_EVEN_191___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__XLNA_GAIN_ODD_191___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__XLNA_GAIN_ODD_191___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__LNA_GAIN_ODD_191___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__LNA_GAIN_ODD_191___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__GM_GAIN_ODD_191___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__GM_GAIN_ODD_191___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__TIA_GAIN_ODD_191___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__TIA_GAIN_ODD_191___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__SLM_XLNA_ODD_191___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__SLM_XLNA_ODD_191___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__BQ_GAIN_ODD_191___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__BQ_GAIN_ODD_191___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__XLNA_GAIN_EVEN_191___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__XLNA_GAIN_EVEN_191___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__LNA_GAIN_EVEN_191___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__LNA_GAIN_EVEN_191___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__GM_GAIN_EVEN_191___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__GM_GAIN_EVEN_191___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__TIA_GAIN_EVEN_191___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__TIA_GAIN_EVEN_191___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__SLM_XLNA_EVEN_191___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__SLM_XLNA_EVEN_191___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__BQ_GAIN_EVEN_191___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191__BQ_GAIN_EVEN_191___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_191___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192 (0x005F5300) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__XLNA_GAIN_ODD_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__LNA_GAIN_ODD_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__GM_GAIN_ODD_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__TIA_GAIN_ODD_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__SLM_XLNA_ODD_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__BQ_GAIN_ODD_192___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__XLNA_GAIN_EVEN_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__LNA_GAIN_EVEN_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__GM_GAIN_EVEN_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__TIA_GAIN_EVEN_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__SLM_XLNA_EVEN_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__BQ_GAIN_EVEN_192___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__XLNA_GAIN_ODD_192___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__XLNA_GAIN_ODD_192___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__LNA_GAIN_ODD_192___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__LNA_GAIN_ODD_192___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__GM_GAIN_ODD_192___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__GM_GAIN_ODD_192___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__TIA_GAIN_ODD_192___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__TIA_GAIN_ODD_192___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__SLM_XLNA_ODD_192___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__SLM_XLNA_ODD_192___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__BQ_GAIN_ODD_192___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__BQ_GAIN_ODD_192___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__XLNA_GAIN_EVEN_192___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__XLNA_GAIN_EVEN_192___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__LNA_GAIN_EVEN_192___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__LNA_GAIN_EVEN_192___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__GM_GAIN_EVEN_192___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__GM_GAIN_EVEN_192___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__TIA_GAIN_EVEN_192___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__TIA_GAIN_EVEN_192___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__SLM_XLNA_EVEN_192___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__SLM_XLNA_EVEN_192___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__BQ_GAIN_EVEN_192___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192__BQ_GAIN_EVEN_192___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_192___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193 (0x005F5304) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__XLNA_GAIN_ODD_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__LNA_GAIN_ODD_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__GM_GAIN_ODD_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__TIA_GAIN_ODD_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__SLM_XLNA_ODD_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__BQ_GAIN_ODD_193___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__XLNA_GAIN_EVEN_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__LNA_GAIN_EVEN_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__GM_GAIN_EVEN_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__TIA_GAIN_EVEN_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__SLM_XLNA_EVEN_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__BQ_GAIN_EVEN_193___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__XLNA_GAIN_ODD_193___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__XLNA_GAIN_ODD_193___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__LNA_GAIN_ODD_193___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__LNA_GAIN_ODD_193___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__GM_GAIN_ODD_193___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__GM_GAIN_ODD_193___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__TIA_GAIN_ODD_193___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__TIA_GAIN_ODD_193___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__SLM_XLNA_ODD_193___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__SLM_XLNA_ODD_193___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__BQ_GAIN_ODD_193___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__BQ_GAIN_ODD_193___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__XLNA_GAIN_EVEN_193___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__XLNA_GAIN_EVEN_193___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__LNA_GAIN_EVEN_193___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__LNA_GAIN_EVEN_193___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__GM_GAIN_EVEN_193___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__GM_GAIN_EVEN_193___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__TIA_GAIN_EVEN_193___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__TIA_GAIN_EVEN_193___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__SLM_XLNA_EVEN_193___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__SLM_XLNA_EVEN_193___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__BQ_GAIN_EVEN_193___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193__BQ_GAIN_EVEN_193___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_193___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194 (0x005F5308) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__XLNA_GAIN_ODD_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__LNA_GAIN_ODD_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__GM_GAIN_ODD_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__TIA_GAIN_ODD_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__SLM_XLNA_ODD_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__BQ_GAIN_ODD_194___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__XLNA_GAIN_EVEN_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__LNA_GAIN_EVEN_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__GM_GAIN_EVEN_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__TIA_GAIN_EVEN_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__SLM_XLNA_EVEN_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__BQ_GAIN_EVEN_194___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__XLNA_GAIN_ODD_194___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__XLNA_GAIN_ODD_194___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__LNA_GAIN_ODD_194___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__LNA_GAIN_ODD_194___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__GM_GAIN_ODD_194___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__GM_GAIN_ODD_194___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__TIA_GAIN_ODD_194___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__TIA_GAIN_ODD_194___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__SLM_XLNA_ODD_194___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__SLM_XLNA_ODD_194___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__BQ_GAIN_ODD_194___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__BQ_GAIN_ODD_194___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__XLNA_GAIN_EVEN_194___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__XLNA_GAIN_EVEN_194___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__LNA_GAIN_EVEN_194___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__LNA_GAIN_EVEN_194___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__GM_GAIN_EVEN_194___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__GM_GAIN_EVEN_194___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__TIA_GAIN_EVEN_194___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__TIA_GAIN_EVEN_194___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__SLM_XLNA_EVEN_194___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__SLM_XLNA_EVEN_194___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__BQ_GAIN_EVEN_194___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194__BQ_GAIN_EVEN_194___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_194___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195 (0x005F530C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__XLNA_GAIN_ODD_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__LNA_GAIN_ODD_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__GM_GAIN_ODD_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__TIA_GAIN_ODD_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__SLM_XLNA_ODD_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__BQ_GAIN_ODD_195___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__XLNA_GAIN_EVEN_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__LNA_GAIN_EVEN_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__GM_GAIN_EVEN_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__TIA_GAIN_EVEN_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__SLM_XLNA_EVEN_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__BQ_GAIN_EVEN_195___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__XLNA_GAIN_ODD_195___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__XLNA_GAIN_ODD_195___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__LNA_GAIN_ODD_195___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__LNA_GAIN_ODD_195___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__GM_GAIN_ODD_195___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__GM_GAIN_ODD_195___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__TIA_GAIN_ODD_195___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__TIA_GAIN_ODD_195___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__SLM_XLNA_ODD_195___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__SLM_XLNA_ODD_195___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__BQ_GAIN_ODD_195___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__BQ_GAIN_ODD_195___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__XLNA_GAIN_EVEN_195___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__XLNA_GAIN_EVEN_195___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__LNA_GAIN_EVEN_195___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__LNA_GAIN_EVEN_195___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__GM_GAIN_EVEN_195___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__GM_GAIN_EVEN_195___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__TIA_GAIN_EVEN_195___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__TIA_GAIN_EVEN_195___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__SLM_XLNA_EVEN_195___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__SLM_XLNA_EVEN_195___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__BQ_GAIN_EVEN_195___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195__BQ_GAIN_EVEN_195___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_195___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196 (0x005F5310) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__XLNA_GAIN_ODD_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__LNA_GAIN_ODD_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__GM_GAIN_ODD_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__TIA_GAIN_ODD_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__SLM_XLNA_ODD_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__BQ_GAIN_ODD_196___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__XLNA_GAIN_EVEN_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__LNA_GAIN_EVEN_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__GM_GAIN_EVEN_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__TIA_GAIN_EVEN_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__SLM_XLNA_EVEN_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__BQ_GAIN_EVEN_196___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__XLNA_GAIN_ODD_196___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__XLNA_GAIN_ODD_196___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__LNA_GAIN_ODD_196___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__LNA_GAIN_ODD_196___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__GM_GAIN_ODD_196___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__GM_GAIN_ODD_196___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__TIA_GAIN_ODD_196___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__TIA_GAIN_ODD_196___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__SLM_XLNA_ODD_196___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__SLM_XLNA_ODD_196___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__BQ_GAIN_ODD_196___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__BQ_GAIN_ODD_196___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__XLNA_GAIN_EVEN_196___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__XLNA_GAIN_EVEN_196___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__LNA_GAIN_EVEN_196___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__LNA_GAIN_EVEN_196___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__GM_GAIN_EVEN_196___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__GM_GAIN_EVEN_196___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__TIA_GAIN_EVEN_196___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__TIA_GAIN_EVEN_196___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__SLM_XLNA_EVEN_196___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__SLM_XLNA_EVEN_196___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__BQ_GAIN_EVEN_196___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196__BQ_GAIN_EVEN_196___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_196___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197 (0x005F5314) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__XLNA_GAIN_ODD_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__LNA_GAIN_ODD_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__GM_GAIN_ODD_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__TIA_GAIN_ODD_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__SLM_XLNA_ODD_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__BQ_GAIN_ODD_197___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__XLNA_GAIN_EVEN_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__LNA_GAIN_EVEN_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__GM_GAIN_EVEN_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__TIA_GAIN_EVEN_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__SLM_XLNA_EVEN_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__BQ_GAIN_EVEN_197___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__XLNA_GAIN_ODD_197___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__XLNA_GAIN_ODD_197___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__LNA_GAIN_ODD_197___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__LNA_GAIN_ODD_197___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__GM_GAIN_ODD_197___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__GM_GAIN_ODD_197___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__TIA_GAIN_ODD_197___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__TIA_GAIN_ODD_197___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__SLM_XLNA_ODD_197___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__SLM_XLNA_ODD_197___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__BQ_GAIN_ODD_197___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__BQ_GAIN_ODD_197___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__XLNA_GAIN_EVEN_197___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__XLNA_GAIN_EVEN_197___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__LNA_GAIN_EVEN_197___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__LNA_GAIN_EVEN_197___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__GM_GAIN_EVEN_197___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__GM_GAIN_EVEN_197___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__TIA_GAIN_EVEN_197___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__TIA_GAIN_EVEN_197___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__SLM_XLNA_EVEN_197___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__SLM_XLNA_EVEN_197___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__BQ_GAIN_EVEN_197___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197__BQ_GAIN_EVEN_197___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_197___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198 (0x005F5318) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__XLNA_GAIN_ODD_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__LNA_GAIN_ODD_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__GM_GAIN_ODD_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__TIA_GAIN_ODD_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__SLM_XLNA_ODD_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__BQ_GAIN_ODD_198___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__XLNA_GAIN_EVEN_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__LNA_GAIN_EVEN_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__GM_GAIN_EVEN_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__TIA_GAIN_EVEN_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__SLM_XLNA_EVEN_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__BQ_GAIN_EVEN_198___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__XLNA_GAIN_ODD_198___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__XLNA_GAIN_ODD_198___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__LNA_GAIN_ODD_198___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__LNA_GAIN_ODD_198___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__GM_GAIN_ODD_198___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__GM_GAIN_ODD_198___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__TIA_GAIN_ODD_198___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__TIA_GAIN_ODD_198___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__SLM_XLNA_ODD_198___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__SLM_XLNA_ODD_198___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__BQ_GAIN_ODD_198___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__BQ_GAIN_ODD_198___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__XLNA_GAIN_EVEN_198___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__XLNA_GAIN_EVEN_198___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__LNA_GAIN_EVEN_198___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__LNA_GAIN_EVEN_198___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__GM_GAIN_EVEN_198___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__GM_GAIN_EVEN_198___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__TIA_GAIN_EVEN_198___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__TIA_GAIN_EVEN_198___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__SLM_XLNA_EVEN_198___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__SLM_XLNA_EVEN_198___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__BQ_GAIN_EVEN_198___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198__BQ_GAIN_EVEN_198___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_198___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199 (0x005F531C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__XLNA_GAIN_ODD_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__LNA_GAIN_ODD_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__GM_GAIN_ODD_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__TIA_GAIN_ODD_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__SLM_XLNA_ODD_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__BQ_GAIN_ODD_199___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__XLNA_GAIN_EVEN_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__LNA_GAIN_EVEN_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__GM_GAIN_EVEN_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__TIA_GAIN_EVEN_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__SLM_XLNA_EVEN_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__BQ_GAIN_EVEN_199___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__XLNA_GAIN_ODD_199___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__XLNA_GAIN_ODD_199___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__LNA_GAIN_ODD_199___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__LNA_GAIN_ODD_199___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__GM_GAIN_ODD_199___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__GM_GAIN_ODD_199___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__TIA_GAIN_ODD_199___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__TIA_GAIN_ODD_199___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__SLM_XLNA_ODD_199___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__SLM_XLNA_ODD_199___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__BQ_GAIN_ODD_199___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__BQ_GAIN_ODD_199___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__XLNA_GAIN_EVEN_199___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__XLNA_GAIN_EVEN_199___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__LNA_GAIN_EVEN_199___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__LNA_GAIN_EVEN_199___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__GM_GAIN_EVEN_199___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__GM_GAIN_EVEN_199___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__TIA_GAIN_EVEN_199___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__TIA_GAIN_EVEN_199___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__SLM_XLNA_EVEN_199___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__SLM_XLNA_EVEN_199___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__BQ_GAIN_EVEN_199___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199__BQ_GAIN_EVEN_199___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_199___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200 (0x005F5320) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__XLNA_GAIN_ODD_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__LNA_GAIN_ODD_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__GM_GAIN_ODD_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__TIA_GAIN_ODD_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__SLM_XLNA_ODD_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__BQ_GAIN_ODD_200___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__XLNA_GAIN_EVEN_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__LNA_GAIN_EVEN_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__GM_GAIN_EVEN_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__TIA_GAIN_EVEN_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__SLM_XLNA_EVEN_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__BQ_GAIN_EVEN_200___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__XLNA_GAIN_ODD_200___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__XLNA_GAIN_ODD_200___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__LNA_GAIN_ODD_200___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__LNA_GAIN_ODD_200___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__GM_GAIN_ODD_200___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__GM_GAIN_ODD_200___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__TIA_GAIN_ODD_200___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__TIA_GAIN_ODD_200___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__SLM_XLNA_ODD_200___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__SLM_XLNA_ODD_200___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__BQ_GAIN_ODD_200___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__BQ_GAIN_ODD_200___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__XLNA_GAIN_EVEN_200___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__XLNA_GAIN_EVEN_200___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__LNA_GAIN_EVEN_200___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__LNA_GAIN_EVEN_200___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__GM_GAIN_EVEN_200___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__GM_GAIN_EVEN_200___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__TIA_GAIN_EVEN_200___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__TIA_GAIN_EVEN_200___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__SLM_XLNA_EVEN_200___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__SLM_XLNA_EVEN_200___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__BQ_GAIN_EVEN_200___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200__BQ_GAIN_EVEN_200___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_200___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201 (0x005F5324) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__XLNA_GAIN_ODD_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__LNA_GAIN_ODD_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__GM_GAIN_ODD_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__TIA_GAIN_ODD_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__SLM_XLNA_ODD_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__BQ_GAIN_ODD_201___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__XLNA_GAIN_EVEN_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__LNA_GAIN_EVEN_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__GM_GAIN_EVEN_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__TIA_GAIN_EVEN_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__SLM_XLNA_EVEN_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__BQ_GAIN_EVEN_201___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__XLNA_GAIN_ODD_201___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__XLNA_GAIN_ODD_201___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__LNA_GAIN_ODD_201___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__LNA_GAIN_ODD_201___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__GM_GAIN_ODD_201___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__GM_GAIN_ODD_201___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__TIA_GAIN_ODD_201___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__TIA_GAIN_ODD_201___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__SLM_XLNA_ODD_201___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__SLM_XLNA_ODD_201___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__BQ_GAIN_ODD_201___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__BQ_GAIN_ODD_201___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__XLNA_GAIN_EVEN_201___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__XLNA_GAIN_EVEN_201___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__LNA_GAIN_EVEN_201___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__LNA_GAIN_EVEN_201___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__GM_GAIN_EVEN_201___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__GM_GAIN_EVEN_201___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__TIA_GAIN_EVEN_201___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__TIA_GAIN_EVEN_201___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__SLM_XLNA_EVEN_201___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__SLM_XLNA_EVEN_201___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__BQ_GAIN_EVEN_201___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201__BQ_GAIN_EVEN_201___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_201___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202 (0x005F5328) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__XLNA_GAIN_ODD_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__LNA_GAIN_ODD_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__GM_GAIN_ODD_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__TIA_GAIN_ODD_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__SLM_XLNA_ODD_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__BQ_GAIN_ODD_202___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__XLNA_GAIN_EVEN_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__LNA_GAIN_EVEN_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__GM_GAIN_EVEN_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__TIA_GAIN_EVEN_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__SLM_XLNA_EVEN_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__BQ_GAIN_EVEN_202___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__XLNA_GAIN_ODD_202___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__XLNA_GAIN_ODD_202___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__LNA_GAIN_ODD_202___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__LNA_GAIN_ODD_202___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__GM_GAIN_ODD_202___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__GM_GAIN_ODD_202___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__TIA_GAIN_ODD_202___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__TIA_GAIN_ODD_202___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__SLM_XLNA_ODD_202___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__SLM_XLNA_ODD_202___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__BQ_GAIN_ODD_202___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__BQ_GAIN_ODD_202___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__XLNA_GAIN_EVEN_202___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__XLNA_GAIN_EVEN_202___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__LNA_GAIN_EVEN_202___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__LNA_GAIN_EVEN_202___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__GM_GAIN_EVEN_202___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__GM_GAIN_EVEN_202___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__TIA_GAIN_EVEN_202___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__TIA_GAIN_EVEN_202___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__SLM_XLNA_EVEN_202___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__SLM_XLNA_EVEN_202___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__BQ_GAIN_EVEN_202___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202__BQ_GAIN_EVEN_202___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_202___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203 (0x005F532C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__XLNA_GAIN_ODD_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__LNA_GAIN_ODD_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__GM_GAIN_ODD_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__TIA_GAIN_ODD_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__SLM_XLNA_ODD_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__BQ_GAIN_ODD_203___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__XLNA_GAIN_EVEN_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__LNA_GAIN_EVEN_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__GM_GAIN_EVEN_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__TIA_GAIN_EVEN_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__SLM_XLNA_EVEN_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__BQ_GAIN_EVEN_203___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__XLNA_GAIN_ODD_203___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__XLNA_GAIN_ODD_203___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__LNA_GAIN_ODD_203___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__LNA_GAIN_ODD_203___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__GM_GAIN_ODD_203___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__GM_GAIN_ODD_203___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__TIA_GAIN_ODD_203___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__TIA_GAIN_ODD_203___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__SLM_XLNA_ODD_203___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__SLM_XLNA_ODD_203___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__BQ_GAIN_ODD_203___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__BQ_GAIN_ODD_203___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__XLNA_GAIN_EVEN_203___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__XLNA_GAIN_EVEN_203___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__LNA_GAIN_EVEN_203___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__LNA_GAIN_EVEN_203___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__GM_GAIN_EVEN_203___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__GM_GAIN_EVEN_203___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__TIA_GAIN_EVEN_203___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__TIA_GAIN_EVEN_203___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__SLM_XLNA_EVEN_203___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__SLM_XLNA_EVEN_203___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__BQ_GAIN_EVEN_203___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203__BQ_GAIN_EVEN_203___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_203___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204 (0x005F5330) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__XLNA_GAIN_ODD_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__LNA_GAIN_ODD_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__GM_GAIN_ODD_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__TIA_GAIN_ODD_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__SLM_XLNA_ODD_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__BQ_GAIN_ODD_204___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__XLNA_GAIN_EVEN_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__LNA_GAIN_EVEN_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__GM_GAIN_EVEN_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__TIA_GAIN_EVEN_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__SLM_XLNA_EVEN_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__BQ_GAIN_EVEN_204___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__XLNA_GAIN_ODD_204___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__XLNA_GAIN_ODD_204___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__LNA_GAIN_ODD_204___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__LNA_GAIN_ODD_204___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__GM_GAIN_ODD_204___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__GM_GAIN_ODD_204___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__TIA_GAIN_ODD_204___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__TIA_GAIN_ODD_204___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__SLM_XLNA_ODD_204___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__SLM_XLNA_ODD_204___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__BQ_GAIN_ODD_204___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__BQ_GAIN_ODD_204___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__XLNA_GAIN_EVEN_204___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__XLNA_GAIN_EVEN_204___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__LNA_GAIN_EVEN_204___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__LNA_GAIN_EVEN_204___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__GM_GAIN_EVEN_204___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__GM_GAIN_EVEN_204___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__TIA_GAIN_EVEN_204___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__TIA_GAIN_EVEN_204___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__SLM_XLNA_EVEN_204___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__SLM_XLNA_EVEN_204___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__BQ_GAIN_EVEN_204___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204__BQ_GAIN_EVEN_204___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_204___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205 (0x005F5334) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__XLNA_GAIN_ODD_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__LNA_GAIN_ODD_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__GM_GAIN_ODD_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__TIA_GAIN_ODD_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__SLM_XLNA_ODD_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__BQ_GAIN_ODD_205___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__XLNA_GAIN_EVEN_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__LNA_GAIN_EVEN_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__GM_GAIN_EVEN_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__TIA_GAIN_EVEN_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__SLM_XLNA_EVEN_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__BQ_GAIN_EVEN_205___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__XLNA_GAIN_ODD_205___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__XLNA_GAIN_ODD_205___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__LNA_GAIN_ODD_205___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__LNA_GAIN_ODD_205___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__GM_GAIN_ODD_205___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__GM_GAIN_ODD_205___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__TIA_GAIN_ODD_205___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__TIA_GAIN_ODD_205___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__SLM_XLNA_ODD_205___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__SLM_XLNA_ODD_205___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__BQ_GAIN_ODD_205___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__BQ_GAIN_ODD_205___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__XLNA_GAIN_EVEN_205___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__XLNA_GAIN_EVEN_205___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__LNA_GAIN_EVEN_205___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__LNA_GAIN_EVEN_205___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__GM_GAIN_EVEN_205___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__GM_GAIN_EVEN_205___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__TIA_GAIN_EVEN_205___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__TIA_GAIN_EVEN_205___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__SLM_XLNA_EVEN_205___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__SLM_XLNA_EVEN_205___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__BQ_GAIN_EVEN_205___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205__BQ_GAIN_EVEN_205___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_205___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206 (0x005F5338) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__XLNA_GAIN_ODD_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__LNA_GAIN_ODD_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__GM_GAIN_ODD_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__TIA_GAIN_ODD_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__SLM_XLNA_ODD_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__BQ_GAIN_ODD_206___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__XLNA_GAIN_EVEN_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__LNA_GAIN_EVEN_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__GM_GAIN_EVEN_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__TIA_GAIN_EVEN_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__SLM_XLNA_EVEN_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__BQ_GAIN_EVEN_206___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__XLNA_GAIN_ODD_206___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__XLNA_GAIN_ODD_206___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__LNA_GAIN_ODD_206___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__LNA_GAIN_ODD_206___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__GM_GAIN_ODD_206___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__GM_GAIN_ODD_206___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__TIA_GAIN_ODD_206___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__TIA_GAIN_ODD_206___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__SLM_XLNA_ODD_206___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__SLM_XLNA_ODD_206___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__BQ_GAIN_ODD_206___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__BQ_GAIN_ODD_206___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__XLNA_GAIN_EVEN_206___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__XLNA_GAIN_EVEN_206___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__LNA_GAIN_EVEN_206___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__LNA_GAIN_EVEN_206___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__GM_GAIN_EVEN_206___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__GM_GAIN_EVEN_206___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__TIA_GAIN_EVEN_206___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__TIA_GAIN_EVEN_206___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__SLM_XLNA_EVEN_206___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__SLM_XLNA_EVEN_206___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__BQ_GAIN_EVEN_206___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206__BQ_GAIN_EVEN_206___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_206___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207 (0x005F533C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__XLNA_GAIN_ODD_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__LNA_GAIN_ODD_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__GM_GAIN_ODD_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__TIA_GAIN_ODD_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__SLM_XLNA_ODD_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__BQ_GAIN_ODD_207___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__XLNA_GAIN_EVEN_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__LNA_GAIN_EVEN_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__GM_GAIN_EVEN_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__TIA_GAIN_EVEN_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__SLM_XLNA_EVEN_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__BQ_GAIN_EVEN_207___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__XLNA_GAIN_ODD_207___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__XLNA_GAIN_ODD_207___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__LNA_GAIN_ODD_207___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__LNA_GAIN_ODD_207___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__GM_GAIN_ODD_207___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__GM_GAIN_ODD_207___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__TIA_GAIN_ODD_207___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__TIA_GAIN_ODD_207___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__SLM_XLNA_ODD_207___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__SLM_XLNA_ODD_207___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__BQ_GAIN_ODD_207___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__BQ_GAIN_ODD_207___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__XLNA_GAIN_EVEN_207___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__XLNA_GAIN_EVEN_207___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__LNA_GAIN_EVEN_207___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__LNA_GAIN_EVEN_207___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__GM_GAIN_EVEN_207___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__GM_GAIN_EVEN_207___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__TIA_GAIN_EVEN_207___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__TIA_GAIN_EVEN_207___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__SLM_XLNA_EVEN_207___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__SLM_XLNA_EVEN_207___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__BQ_GAIN_EVEN_207___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207__BQ_GAIN_EVEN_207___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_207___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208 (0x005F5340) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__XLNA_GAIN_ODD_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__LNA_GAIN_ODD_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__GM_GAIN_ODD_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__TIA_GAIN_ODD_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__SLM_XLNA_ODD_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__BQ_GAIN_ODD_208___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__XLNA_GAIN_EVEN_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__LNA_GAIN_EVEN_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__GM_GAIN_EVEN_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__TIA_GAIN_EVEN_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__SLM_XLNA_EVEN_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__BQ_GAIN_EVEN_208___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__XLNA_GAIN_ODD_208___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__XLNA_GAIN_ODD_208___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__LNA_GAIN_ODD_208___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__LNA_GAIN_ODD_208___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__GM_GAIN_ODD_208___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__GM_GAIN_ODD_208___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__TIA_GAIN_ODD_208___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__TIA_GAIN_ODD_208___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__SLM_XLNA_ODD_208___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__SLM_XLNA_ODD_208___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__BQ_GAIN_ODD_208___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__BQ_GAIN_ODD_208___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__XLNA_GAIN_EVEN_208___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__XLNA_GAIN_EVEN_208___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__LNA_GAIN_EVEN_208___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__LNA_GAIN_EVEN_208___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__GM_GAIN_EVEN_208___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__GM_GAIN_EVEN_208___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__TIA_GAIN_EVEN_208___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__TIA_GAIN_EVEN_208___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__SLM_XLNA_EVEN_208___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__SLM_XLNA_EVEN_208___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__BQ_GAIN_EVEN_208___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208__BQ_GAIN_EVEN_208___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_208___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209 (0x005F5344) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__XLNA_GAIN_ODD_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__LNA_GAIN_ODD_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__GM_GAIN_ODD_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__TIA_GAIN_ODD_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__SLM_XLNA_ODD_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__BQ_GAIN_ODD_209___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__XLNA_GAIN_EVEN_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__LNA_GAIN_EVEN_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__GM_GAIN_EVEN_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__TIA_GAIN_EVEN_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__SLM_XLNA_EVEN_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__BQ_GAIN_EVEN_209___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__XLNA_GAIN_ODD_209___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__XLNA_GAIN_ODD_209___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__LNA_GAIN_ODD_209___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__LNA_GAIN_ODD_209___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__GM_GAIN_ODD_209___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__GM_GAIN_ODD_209___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__TIA_GAIN_ODD_209___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__TIA_GAIN_ODD_209___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__SLM_XLNA_ODD_209___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__SLM_XLNA_ODD_209___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__BQ_GAIN_ODD_209___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__BQ_GAIN_ODD_209___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__XLNA_GAIN_EVEN_209___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__XLNA_GAIN_EVEN_209___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__LNA_GAIN_EVEN_209___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__LNA_GAIN_EVEN_209___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__GM_GAIN_EVEN_209___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__GM_GAIN_EVEN_209___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__TIA_GAIN_EVEN_209___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__TIA_GAIN_EVEN_209___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__SLM_XLNA_EVEN_209___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__SLM_XLNA_EVEN_209___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__BQ_GAIN_EVEN_209___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209__BQ_GAIN_EVEN_209___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_209___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210 (0x005F5348) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__XLNA_GAIN_ODD_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__LNA_GAIN_ODD_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__GM_GAIN_ODD_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__TIA_GAIN_ODD_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__SLM_XLNA_ODD_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__BQ_GAIN_ODD_210___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__XLNA_GAIN_EVEN_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__LNA_GAIN_EVEN_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__GM_GAIN_EVEN_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__TIA_GAIN_EVEN_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__SLM_XLNA_EVEN_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__BQ_GAIN_EVEN_210___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__XLNA_GAIN_ODD_210___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__XLNA_GAIN_ODD_210___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__LNA_GAIN_ODD_210___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__LNA_GAIN_ODD_210___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__GM_GAIN_ODD_210___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__GM_GAIN_ODD_210___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__TIA_GAIN_ODD_210___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__TIA_GAIN_ODD_210___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__SLM_XLNA_ODD_210___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__SLM_XLNA_ODD_210___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__BQ_GAIN_ODD_210___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__BQ_GAIN_ODD_210___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__XLNA_GAIN_EVEN_210___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__XLNA_GAIN_EVEN_210___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__LNA_GAIN_EVEN_210___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__LNA_GAIN_EVEN_210___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__GM_GAIN_EVEN_210___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__GM_GAIN_EVEN_210___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__TIA_GAIN_EVEN_210___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__TIA_GAIN_EVEN_210___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__SLM_XLNA_EVEN_210___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__SLM_XLNA_EVEN_210___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__BQ_GAIN_EVEN_210___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210__BQ_GAIN_EVEN_210___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_210___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211 (0x005F534C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__XLNA_GAIN_ODD_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__LNA_GAIN_ODD_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__GM_GAIN_ODD_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__TIA_GAIN_ODD_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__SLM_XLNA_ODD_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__BQ_GAIN_ODD_211___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__XLNA_GAIN_EVEN_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__LNA_GAIN_EVEN_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__GM_GAIN_EVEN_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__TIA_GAIN_EVEN_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__SLM_XLNA_EVEN_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__BQ_GAIN_EVEN_211___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__XLNA_GAIN_ODD_211___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__XLNA_GAIN_ODD_211___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__LNA_GAIN_ODD_211___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__LNA_GAIN_ODD_211___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__GM_GAIN_ODD_211___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__GM_GAIN_ODD_211___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__TIA_GAIN_ODD_211___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__TIA_GAIN_ODD_211___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__SLM_XLNA_ODD_211___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__SLM_XLNA_ODD_211___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__BQ_GAIN_ODD_211___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__BQ_GAIN_ODD_211___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__XLNA_GAIN_EVEN_211___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__XLNA_GAIN_EVEN_211___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__LNA_GAIN_EVEN_211___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__LNA_GAIN_EVEN_211___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__GM_GAIN_EVEN_211___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__GM_GAIN_EVEN_211___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__TIA_GAIN_EVEN_211___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__TIA_GAIN_EVEN_211___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__SLM_XLNA_EVEN_211___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__SLM_XLNA_EVEN_211___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__BQ_GAIN_EVEN_211___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211__BQ_GAIN_EVEN_211___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_211___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212 (0x005F5350) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__XLNA_GAIN_ODD_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__LNA_GAIN_ODD_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__GM_GAIN_ODD_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__TIA_GAIN_ODD_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__SLM_XLNA_ODD_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__BQ_GAIN_ODD_212___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__XLNA_GAIN_EVEN_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__LNA_GAIN_EVEN_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__GM_GAIN_EVEN_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__TIA_GAIN_EVEN_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__SLM_XLNA_EVEN_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__BQ_GAIN_EVEN_212___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__XLNA_GAIN_ODD_212___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__XLNA_GAIN_ODD_212___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__LNA_GAIN_ODD_212___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__LNA_GAIN_ODD_212___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__GM_GAIN_ODD_212___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__GM_GAIN_ODD_212___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__TIA_GAIN_ODD_212___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__TIA_GAIN_ODD_212___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__SLM_XLNA_ODD_212___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__SLM_XLNA_ODD_212___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__BQ_GAIN_ODD_212___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__BQ_GAIN_ODD_212___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__XLNA_GAIN_EVEN_212___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__XLNA_GAIN_EVEN_212___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__LNA_GAIN_EVEN_212___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__LNA_GAIN_EVEN_212___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__GM_GAIN_EVEN_212___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__GM_GAIN_EVEN_212___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__TIA_GAIN_EVEN_212___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__TIA_GAIN_EVEN_212___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__SLM_XLNA_EVEN_212___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__SLM_XLNA_EVEN_212___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__BQ_GAIN_EVEN_212___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212__BQ_GAIN_EVEN_212___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_212___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213 (0x005F5354) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__XLNA_GAIN_ODD_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__LNA_GAIN_ODD_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__GM_GAIN_ODD_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__TIA_GAIN_ODD_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__SLM_XLNA_ODD_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__BQ_GAIN_ODD_213___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__XLNA_GAIN_EVEN_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__LNA_GAIN_EVEN_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__GM_GAIN_EVEN_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__TIA_GAIN_EVEN_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__SLM_XLNA_EVEN_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__BQ_GAIN_EVEN_213___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__XLNA_GAIN_ODD_213___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__XLNA_GAIN_ODD_213___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__LNA_GAIN_ODD_213___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__LNA_GAIN_ODD_213___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__GM_GAIN_ODD_213___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__GM_GAIN_ODD_213___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__TIA_GAIN_ODD_213___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__TIA_GAIN_ODD_213___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__SLM_XLNA_ODD_213___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__SLM_XLNA_ODD_213___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__BQ_GAIN_ODD_213___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__BQ_GAIN_ODD_213___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__XLNA_GAIN_EVEN_213___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__XLNA_GAIN_EVEN_213___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__LNA_GAIN_EVEN_213___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__LNA_GAIN_EVEN_213___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__GM_GAIN_EVEN_213___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__GM_GAIN_EVEN_213___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__TIA_GAIN_EVEN_213___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__TIA_GAIN_EVEN_213___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__SLM_XLNA_EVEN_213___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__SLM_XLNA_EVEN_213___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__BQ_GAIN_EVEN_213___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213__BQ_GAIN_EVEN_213___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_213___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214 (0x005F5358) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__XLNA_GAIN_ODD_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__LNA_GAIN_ODD_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__GM_GAIN_ODD_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__TIA_GAIN_ODD_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__SLM_XLNA_ODD_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__BQ_GAIN_ODD_214___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__XLNA_GAIN_EVEN_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__LNA_GAIN_EVEN_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__GM_GAIN_EVEN_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__TIA_GAIN_EVEN_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__SLM_XLNA_EVEN_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__BQ_GAIN_EVEN_214___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__XLNA_GAIN_ODD_214___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__XLNA_GAIN_ODD_214___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__LNA_GAIN_ODD_214___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__LNA_GAIN_ODD_214___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__GM_GAIN_ODD_214___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__GM_GAIN_ODD_214___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__TIA_GAIN_ODD_214___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__TIA_GAIN_ODD_214___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__SLM_XLNA_ODD_214___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__SLM_XLNA_ODD_214___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__BQ_GAIN_ODD_214___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__BQ_GAIN_ODD_214___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__XLNA_GAIN_EVEN_214___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__XLNA_GAIN_EVEN_214___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__LNA_GAIN_EVEN_214___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__LNA_GAIN_EVEN_214___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__GM_GAIN_EVEN_214___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__GM_GAIN_EVEN_214___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__TIA_GAIN_EVEN_214___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__TIA_GAIN_EVEN_214___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__SLM_XLNA_EVEN_214___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__SLM_XLNA_EVEN_214___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__BQ_GAIN_EVEN_214___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214__BQ_GAIN_EVEN_214___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_214___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215 (0x005F535C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__XLNA_GAIN_ODD_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__LNA_GAIN_ODD_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__GM_GAIN_ODD_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__TIA_GAIN_ODD_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__SLM_XLNA_ODD_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__BQ_GAIN_ODD_215___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__XLNA_GAIN_EVEN_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__LNA_GAIN_EVEN_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__GM_GAIN_EVEN_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__TIA_GAIN_EVEN_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__SLM_XLNA_EVEN_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__BQ_GAIN_EVEN_215___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__XLNA_GAIN_ODD_215___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__XLNA_GAIN_ODD_215___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__LNA_GAIN_ODD_215___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__LNA_GAIN_ODD_215___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__GM_GAIN_ODD_215___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__GM_GAIN_ODD_215___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__TIA_GAIN_ODD_215___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__TIA_GAIN_ODD_215___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__SLM_XLNA_ODD_215___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__SLM_XLNA_ODD_215___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__BQ_GAIN_ODD_215___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__BQ_GAIN_ODD_215___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__XLNA_GAIN_EVEN_215___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__XLNA_GAIN_EVEN_215___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__LNA_GAIN_EVEN_215___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__LNA_GAIN_EVEN_215___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__GM_GAIN_EVEN_215___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__GM_GAIN_EVEN_215___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__TIA_GAIN_EVEN_215___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__TIA_GAIN_EVEN_215___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__SLM_XLNA_EVEN_215___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__SLM_XLNA_EVEN_215___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__BQ_GAIN_EVEN_215___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215__BQ_GAIN_EVEN_215___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_215___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216 (0x005F5360) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__XLNA_GAIN_ODD_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__LNA_GAIN_ODD_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__GM_GAIN_ODD_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__TIA_GAIN_ODD_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__SLM_XLNA_ODD_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__BQ_GAIN_ODD_216___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__XLNA_GAIN_EVEN_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__LNA_GAIN_EVEN_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__GM_GAIN_EVEN_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__TIA_GAIN_EVEN_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__SLM_XLNA_EVEN_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__BQ_GAIN_EVEN_216___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__XLNA_GAIN_ODD_216___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__XLNA_GAIN_ODD_216___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__LNA_GAIN_ODD_216___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__LNA_GAIN_ODD_216___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__GM_GAIN_ODD_216___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__GM_GAIN_ODD_216___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__TIA_GAIN_ODD_216___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__TIA_GAIN_ODD_216___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__SLM_XLNA_ODD_216___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__SLM_XLNA_ODD_216___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__BQ_GAIN_ODD_216___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__BQ_GAIN_ODD_216___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__XLNA_GAIN_EVEN_216___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__XLNA_GAIN_EVEN_216___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__LNA_GAIN_EVEN_216___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__LNA_GAIN_EVEN_216___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__GM_GAIN_EVEN_216___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__GM_GAIN_EVEN_216___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__TIA_GAIN_EVEN_216___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__TIA_GAIN_EVEN_216___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__SLM_XLNA_EVEN_216___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__SLM_XLNA_EVEN_216___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__BQ_GAIN_EVEN_216___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216__BQ_GAIN_EVEN_216___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_216___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217 (0x005F5364) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__XLNA_GAIN_ODD_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__LNA_GAIN_ODD_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__GM_GAIN_ODD_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__TIA_GAIN_ODD_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__SLM_XLNA_ODD_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__BQ_GAIN_ODD_217___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__XLNA_GAIN_EVEN_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__LNA_GAIN_EVEN_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__GM_GAIN_EVEN_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__TIA_GAIN_EVEN_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__SLM_XLNA_EVEN_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__BQ_GAIN_EVEN_217___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__XLNA_GAIN_ODD_217___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__XLNA_GAIN_ODD_217___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__LNA_GAIN_ODD_217___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__LNA_GAIN_ODD_217___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__GM_GAIN_ODD_217___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__GM_GAIN_ODD_217___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__TIA_GAIN_ODD_217___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__TIA_GAIN_ODD_217___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__SLM_XLNA_ODD_217___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__SLM_XLNA_ODD_217___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__BQ_GAIN_ODD_217___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__BQ_GAIN_ODD_217___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__XLNA_GAIN_EVEN_217___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__XLNA_GAIN_EVEN_217___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__LNA_GAIN_EVEN_217___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__LNA_GAIN_EVEN_217___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__GM_GAIN_EVEN_217___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__GM_GAIN_EVEN_217___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__TIA_GAIN_EVEN_217___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__TIA_GAIN_EVEN_217___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__SLM_XLNA_EVEN_217___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__SLM_XLNA_EVEN_217___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__BQ_GAIN_EVEN_217___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217__BQ_GAIN_EVEN_217___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_217___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218 (0x005F5368) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__XLNA_GAIN_ODD_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__LNA_GAIN_ODD_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__GM_GAIN_ODD_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__TIA_GAIN_ODD_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__SLM_XLNA_ODD_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__BQ_GAIN_ODD_218___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__XLNA_GAIN_EVEN_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__LNA_GAIN_EVEN_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__GM_GAIN_EVEN_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__TIA_GAIN_EVEN_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__SLM_XLNA_EVEN_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__BQ_GAIN_EVEN_218___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__XLNA_GAIN_ODD_218___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__XLNA_GAIN_ODD_218___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__LNA_GAIN_ODD_218___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__LNA_GAIN_ODD_218___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__GM_GAIN_ODD_218___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__GM_GAIN_ODD_218___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__TIA_GAIN_ODD_218___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__TIA_GAIN_ODD_218___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__SLM_XLNA_ODD_218___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__SLM_XLNA_ODD_218___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__BQ_GAIN_ODD_218___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__BQ_GAIN_ODD_218___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__XLNA_GAIN_EVEN_218___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__XLNA_GAIN_EVEN_218___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__LNA_GAIN_EVEN_218___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__LNA_GAIN_EVEN_218___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__GM_GAIN_EVEN_218___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__GM_GAIN_EVEN_218___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__TIA_GAIN_EVEN_218___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__TIA_GAIN_EVEN_218___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__SLM_XLNA_EVEN_218___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__SLM_XLNA_EVEN_218___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__BQ_GAIN_EVEN_218___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218__BQ_GAIN_EVEN_218___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_218___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219 (0x005F536C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__XLNA_GAIN_ODD_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__LNA_GAIN_ODD_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__GM_GAIN_ODD_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__TIA_GAIN_ODD_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__SLM_XLNA_ODD_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__BQ_GAIN_ODD_219___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__XLNA_GAIN_EVEN_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__LNA_GAIN_EVEN_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__GM_GAIN_EVEN_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__TIA_GAIN_EVEN_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__SLM_XLNA_EVEN_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__BQ_GAIN_EVEN_219___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__XLNA_GAIN_ODD_219___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__XLNA_GAIN_ODD_219___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__LNA_GAIN_ODD_219___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__LNA_GAIN_ODD_219___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__GM_GAIN_ODD_219___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__GM_GAIN_ODD_219___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__TIA_GAIN_ODD_219___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__TIA_GAIN_ODD_219___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__SLM_XLNA_ODD_219___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__SLM_XLNA_ODD_219___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__BQ_GAIN_ODD_219___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__BQ_GAIN_ODD_219___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__XLNA_GAIN_EVEN_219___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__XLNA_GAIN_EVEN_219___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__LNA_GAIN_EVEN_219___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__LNA_GAIN_EVEN_219___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__GM_GAIN_EVEN_219___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__GM_GAIN_EVEN_219___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__TIA_GAIN_EVEN_219___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__TIA_GAIN_EVEN_219___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__SLM_XLNA_EVEN_219___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__SLM_XLNA_EVEN_219___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__BQ_GAIN_EVEN_219___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219__BQ_GAIN_EVEN_219___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_219___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220 (0x005F5370) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__XLNA_GAIN_ODD_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__LNA_GAIN_ODD_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__GM_GAIN_ODD_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__TIA_GAIN_ODD_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__SLM_XLNA_ODD_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__BQ_GAIN_ODD_220___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__XLNA_GAIN_EVEN_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__LNA_GAIN_EVEN_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__GM_GAIN_EVEN_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__TIA_GAIN_EVEN_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__SLM_XLNA_EVEN_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__BQ_GAIN_EVEN_220___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__XLNA_GAIN_ODD_220___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__XLNA_GAIN_ODD_220___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__LNA_GAIN_ODD_220___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__LNA_GAIN_ODD_220___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__GM_GAIN_ODD_220___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__GM_GAIN_ODD_220___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__TIA_GAIN_ODD_220___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__TIA_GAIN_ODD_220___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__SLM_XLNA_ODD_220___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__SLM_XLNA_ODD_220___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__BQ_GAIN_ODD_220___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__BQ_GAIN_ODD_220___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__XLNA_GAIN_EVEN_220___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__XLNA_GAIN_EVEN_220___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__LNA_GAIN_EVEN_220___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__LNA_GAIN_EVEN_220___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__GM_GAIN_EVEN_220___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__GM_GAIN_EVEN_220___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__TIA_GAIN_EVEN_220___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__TIA_GAIN_EVEN_220___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__SLM_XLNA_EVEN_220___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__SLM_XLNA_EVEN_220___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__BQ_GAIN_EVEN_220___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220__BQ_GAIN_EVEN_220___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_220___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221 (0x005F5374) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__XLNA_GAIN_ODD_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__LNA_GAIN_ODD_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__GM_GAIN_ODD_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__TIA_GAIN_ODD_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__SLM_XLNA_ODD_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__BQ_GAIN_ODD_221___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__XLNA_GAIN_EVEN_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__LNA_GAIN_EVEN_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__GM_GAIN_EVEN_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__TIA_GAIN_EVEN_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__SLM_XLNA_EVEN_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__BQ_GAIN_EVEN_221___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__XLNA_GAIN_ODD_221___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__XLNA_GAIN_ODD_221___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__LNA_GAIN_ODD_221___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__LNA_GAIN_ODD_221___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__GM_GAIN_ODD_221___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__GM_GAIN_ODD_221___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__TIA_GAIN_ODD_221___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__TIA_GAIN_ODD_221___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__SLM_XLNA_ODD_221___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__SLM_XLNA_ODD_221___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__BQ_GAIN_ODD_221___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__BQ_GAIN_ODD_221___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__XLNA_GAIN_EVEN_221___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__XLNA_GAIN_EVEN_221___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__LNA_GAIN_EVEN_221___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__LNA_GAIN_EVEN_221___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__GM_GAIN_EVEN_221___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__GM_GAIN_EVEN_221___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__TIA_GAIN_EVEN_221___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__TIA_GAIN_EVEN_221___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__SLM_XLNA_EVEN_221___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__SLM_XLNA_EVEN_221___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__BQ_GAIN_EVEN_221___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221__BQ_GAIN_EVEN_221___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_221___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222 (0x005F5378) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__XLNA_GAIN_ODD_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__LNA_GAIN_ODD_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__GM_GAIN_ODD_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__TIA_GAIN_ODD_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__SLM_XLNA_ODD_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__BQ_GAIN_ODD_222___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__XLNA_GAIN_EVEN_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__LNA_GAIN_EVEN_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__GM_GAIN_EVEN_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__TIA_GAIN_EVEN_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__SLM_XLNA_EVEN_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__BQ_GAIN_EVEN_222___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__XLNA_GAIN_ODD_222___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__XLNA_GAIN_ODD_222___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__LNA_GAIN_ODD_222___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__LNA_GAIN_ODD_222___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__GM_GAIN_ODD_222___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__GM_GAIN_ODD_222___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__TIA_GAIN_ODD_222___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__TIA_GAIN_ODD_222___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__SLM_XLNA_ODD_222___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__SLM_XLNA_ODD_222___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__BQ_GAIN_ODD_222___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__BQ_GAIN_ODD_222___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__XLNA_GAIN_EVEN_222___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__XLNA_GAIN_EVEN_222___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__LNA_GAIN_EVEN_222___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__LNA_GAIN_EVEN_222___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__GM_GAIN_EVEN_222___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__GM_GAIN_EVEN_222___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__TIA_GAIN_EVEN_222___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__TIA_GAIN_EVEN_222___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__SLM_XLNA_EVEN_222___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__SLM_XLNA_EVEN_222___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__BQ_GAIN_EVEN_222___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222__BQ_GAIN_EVEN_222___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_222___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223 (0x005F537C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__XLNA_GAIN_ODD_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__LNA_GAIN_ODD_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__GM_GAIN_ODD_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__TIA_GAIN_ODD_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__SLM_XLNA_ODD_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__BQ_GAIN_ODD_223___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__XLNA_GAIN_EVEN_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__LNA_GAIN_EVEN_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__GM_GAIN_EVEN_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__TIA_GAIN_EVEN_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__SLM_XLNA_EVEN_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__BQ_GAIN_EVEN_223___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__XLNA_GAIN_ODD_223___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__XLNA_GAIN_ODD_223___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__LNA_GAIN_ODD_223___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__LNA_GAIN_ODD_223___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__GM_GAIN_ODD_223___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__GM_GAIN_ODD_223___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__TIA_GAIN_ODD_223___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__TIA_GAIN_ODD_223___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__SLM_XLNA_ODD_223___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__SLM_XLNA_ODD_223___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__BQ_GAIN_ODD_223___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__BQ_GAIN_ODD_223___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__XLNA_GAIN_EVEN_223___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__XLNA_GAIN_EVEN_223___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__LNA_GAIN_EVEN_223___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__LNA_GAIN_EVEN_223___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__GM_GAIN_EVEN_223___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__GM_GAIN_EVEN_223___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__TIA_GAIN_EVEN_223___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__TIA_GAIN_EVEN_223___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__SLM_XLNA_EVEN_223___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__SLM_XLNA_EVEN_223___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__BQ_GAIN_EVEN_223___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223__BQ_GAIN_EVEN_223___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_223___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224 (0x005F5380) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__XLNA_GAIN_ODD_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__LNA_GAIN_ODD_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__GM_GAIN_ODD_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__TIA_GAIN_ODD_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__SLM_XLNA_ODD_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__BQ_GAIN_ODD_224___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__XLNA_GAIN_EVEN_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__LNA_GAIN_EVEN_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__GM_GAIN_EVEN_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__TIA_GAIN_EVEN_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__SLM_XLNA_EVEN_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__BQ_GAIN_EVEN_224___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__XLNA_GAIN_ODD_224___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__XLNA_GAIN_ODD_224___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__LNA_GAIN_ODD_224___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__LNA_GAIN_ODD_224___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__GM_GAIN_ODD_224___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__GM_GAIN_ODD_224___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__TIA_GAIN_ODD_224___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__TIA_GAIN_ODD_224___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__SLM_XLNA_ODD_224___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__SLM_XLNA_ODD_224___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__BQ_GAIN_ODD_224___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__BQ_GAIN_ODD_224___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__XLNA_GAIN_EVEN_224___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__XLNA_GAIN_EVEN_224___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__LNA_GAIN_EVEN_224___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__LNA_GAIN_EVEN_224___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__GM_GAIN_EVEN_224___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__GM_GAIN_EVEN_224___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__TIA_GAIN_EVEN_224___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__TIA_GAIN_EVEN_224___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__SLM_XLNA_EVEN_224___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__SLM_XLNA_EVEN_224___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__BQ_GAIN_EVEN_224___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224__BQ_GAIN_EVEN_224___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_224___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225 (0x005F5384) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__XLNA_GAIN_ODD_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__LNA_GAIN_ODD_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__GM_GAIN_ODD_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__TIA_GAIN_ODD_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__SLM_XLNA_ODD_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__BQ_GAIN_ODD_225___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__XLNA_GAIN_EVEN_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__LNA_GAIN_EVEN_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__GM_GAIN_EVEN_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__TIA_GAIN_EVEN_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__SLM_XLNA_EVEN_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__BQ_GAIN_EVEN_225___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__XLNA_GAIN_ODD_225___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__XLNA_GAIN_ODD_225___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__LNA_GAIN_ODD_225___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__LNA_GAIN_ODD_225___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__GM_GAIN_ODD_225___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__GM_GAIN_ODD_225___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__TIA_GAIN_ODD_225___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__TIA_GAIN_ODD_225___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__SLM_XLNA_ODD_225___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__SLM_XLNA_ODD_225___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__BQ_GAIN_ODD_225___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__BQ_GAIN_ODD_225___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__XLNA_GAIN_EVEN_225___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__XLNA_GAIN_EVEN_225___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__LNA_GAIN_EVEN_225___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__LNA_GAIN_EVEN_225___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__GM_GAIN_EVEN_225___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__GM_GAIN_EVEN_225___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__TIA_GAIN_EVEN_225___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__TIA_GAIN_EVEN_225___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__SLM_XLNA_EVEN_225___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__SLM_XLNA_EVEN_225___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__BQ_GAIN_EVEN_225___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225__BQ_GAIN_EVEN_225___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_225___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226 (0x005F5388) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__XLNA_GAIN_ODD_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__LNA_GAIN_ODD_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__GM_GAIN_ODD_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__TIA_GAIN_ODD_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__SLM_XLNA_ODD_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__BQ_GAIN_ODD_226___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__XLNA_GAIN_EVEN_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__LNA_GAIN_EVEN_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__GM_GAIN_EVEN_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__TIA_GAIN_EVEN_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__SLM_XLNA_EVEN_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__BQ_GAIN_EVEN_226___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__XLNA_GAIN_ODD_226___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__XLNA_GAIN_ODD_226___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__LNA_GAIN_ODD_226___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__LNA_GAIN_ODD_226___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__GM_GAIN_ODD_226___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__GM_GAIN_ODD_226___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__TIA_GAIN_ODD_226___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__TIA_GAIN_ODD_226___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__SLM_XLNA_ODD_226___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__SLM_XLNA_ODD_226___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__BQ_GAIN_ODD_226___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__BQ_GAIN_ODD_226___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__XLNA_GAIN_EVEN_226___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__XLNA_GAIN_EVEN_226___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__LNA_GAIN_EVEN_226___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__LNA_GAIN_EVEN_226___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__GM_GAIN_EVEN_226___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__GM_GAIN_EVEN_226___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__TIA_GAIN_EVEN_226___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__TIA_GAIN_EVEN_226___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__SLM_XLNA_EVEN_226___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__SLM_XLNA_EVEN_226___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__BQ_GAIN_EVEN_226___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226__BQ_GAIN_EVEN_226___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_226___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227 (0x005F538C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__XLNA_GAIN_ODD_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__LNA_GAIN_ODD_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__GM_GAIN_ODD_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__TIA_GAIN_ODD_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__SLM_XLNA_ODD_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__BQ_GAIN_ODD_227___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__XLNA_GAIN_EVEN_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__LNA_GAIN_EVEN_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__GM_GAIN_EVEN_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__TIA_GAIN_EVEN_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__SLM_XLNA_EVEN_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__BQ_GAIN_EVEN_227___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__XLNA_GAIN_ODD_227___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__XLNA_GAIN_ODD_227___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__LNA_GAIN_ODD_227___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__LNA_GAIN_ODD_227___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__GM_GAIN_ODD_227___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__GM_GAIN_ODD_227___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__TIA_GAIN_ODD_227___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__TIA_GAIN_ODD_227___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__SLM_XLNA_ODD_227___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__SLM_XLNA_ODD_227___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__BQ_GAIN_ODD_227___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__BQ_GAIN_ODD_227___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__XLNA_GAIN_EVEN_227___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__XLNA_GAIN_EVEN_227___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__LNA_GAIN_EVEN_227___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__LNA_GAIN_EVEN_227___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__GM_GAIN_EVEN_227___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__GM_GAIN_EVEN_227___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__TIA_GAIN_EVEN_227___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__TIA_GAIN_EVEN_227___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__SLM_XLNA_EVEN_227___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__SLM_XLNA_EVEN_227___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__BQ_GAIN_EVEN_227___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227__BQ_GAIN_EVEN_227___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_227___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228 (0x005F5390) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__XLNA_GAIN_ODD_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__LNA_GAIN_ODD_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__GM_GAIN_ODD_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__TIA_GAIN_ODD_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__SLM_XLNA_ODD_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__BQ_GAIN_ODD_228___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__XLNA_GAIN_EVEN_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__LNA_GAIN_EVEN_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__GM_GAIN_EVEN_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__TIA_GAIN_EVEN_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__SLM_XLNA_EVEN_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__BQ_GAIN_EVEN_228___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__XLNA_GAIN_ODD_228___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__XLNA_GAIN_ODD_228___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__LNA_GAIN_ODD_228___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__LNA_GAIN_ODD_228___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__GM_GAIN_ODD_228___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__GM_GAIN_ODD_228___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__TIA_GAIN_ODD_228___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__TIA_GAIN_ODD_228___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__SLM_XLNA_ODD_228___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__SLM_XLNA_ODD_228___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__BQ_GAIN_ODD_228___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__BQ_GAIN_ODD_228___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__XLNA_GAIN_EVEN_228___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__XLNA_GAIN_EVEN_228___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__LNA_GAIN_EVEN_228___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__LNA_GAIN_EVEN_228___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__GM_GAIN_EVEN_228___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__GM_GAIN_EVEN_228___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__TIA_GAIN_EVEN_228___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__TIA_GAIN_EVEN_228___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__SLM_XLNA_EVEN_228___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__SLM_XLNA_EVEN_228___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__BQ_GAIN_EVEN_228___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228__BQ_GAIN_EVEN_228___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_228___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229 (0x005F5394) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__XLNA_GAIN_ODD_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__LNA_GAIN_ODD_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__GM_GAIN_ODD_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__TIA_GAIN_ODD_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__SLM_XLNA_ODD_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__BQ_GAIN_ODD_229___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__XLNA_GAIN_EVEN_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__LNA_GAIN_EVEN_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__GM_GAIN_EVEN_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__TIA_GAIN_EVEN_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__SLM_XLNA_EVEN_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__BQ_GAIN_EVEN_229___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__XLNA_GAIN_ODD_229___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__XLNA_GAIN_ODD_229___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__LNA_GAIN_ODD_229___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__LNA_GAIN_ODD_229___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__GM_GAIN_ODD_229___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__GM_GAIN_ODD_229___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__TIA_GAIN_ODD_229___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__TIA_GAIN_ODD_229___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__SLM_XLNA_ODD_229___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__SLM_XLNA_ODD_229___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__BQ_GAIN_ODD_229___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__BQ_GAIN_ODD_229___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__XLNA_GAIN_EVEN_229___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__XLNA_GAIN_EVEN_229___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__LNA_GAIN_EVEN_229___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__LNA_GAIN_EVEN_229___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__GM_GAIN_EVEN_229___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__GM_GAIN_EVEN_229___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__TIA_GAIN_EVEN_229___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__TIA_GAIN_EVEN_229___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__SLM_XLNA_EVEN_229___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__SLM_XLNA_EVEN_229___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__BQ_GAIN_EVEN_229___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229__BQ_GAIN_EVEN_229___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_229___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230 (0x005F5398) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__XLNA_GAIN_ODD_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__LNA_GAIN_ODD_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__GM_GAIN_ODD_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__TIA_GAIN_ODD_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__SLM_XLNA_ODD_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__BQ_GAIN_ODD_230___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__XLNA_GAIN_EVEN_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__LNA_GAIN_EVEN_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__GM_GAIN_EVEN_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__TIA_GAIN_EVEN_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__SLM_XLNA_EVEN_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__BQ_GAIN_EVEN_230___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__XLNA_GAIN_ODD_230___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__XLNA_GAIN_ODD_230___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__LNA_GAIN_ODD_230___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__LNA_GAIN_ODD_230___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__GM_GAIN_ODD_230___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__GM_GAIN_ODD_230___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__TIA_GAIN_ODD_230___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__TIA_GAIN_ODD_230___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__SLM_XLNA_ODD_230___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__SLM_XLNA_ODD_230___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__BQ_GAIN_ODD_230___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__BQ_GAIN_ODD_230___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__XLNA_GAIN_EVEN_230___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__XLNA_GAIN_EVEN_230___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__LNA_GAIN_EVEN_230___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__LNA_GAIN_EVEN_230___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__GM_GAIN_EVEN_230___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__GM_GAIN_EVEN_230___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__TIA_GAIN_EVEN_230___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__TIA_GAIN_EVEN_230___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__SLM_XLNA_EVEN_230___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__SLM_XLNA_EVEN_230___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__BQ_GAIN_EVEN_230___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230__BQ_GAIN_EVEN_230___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_230___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231 (0x005F539C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__XLNA_GAIN_ODD_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__LNA_GAIN_ODD_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__GM_GAIN_ODD_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__TIA_GAIN_ODD_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__SLM_XLNA_ODD_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__BQ_GAIN_ODD_231___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__XLNA_GAIN_EVEN_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__LNA_GAIN_EVEN_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__GM_GAIN_EVEN_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__TIA_GAIN_EVEN_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__SLM_XLNA_EVEN_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__BQ_GAIN_EVEN_231___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__XLNA_GAIN_ODD_231___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__XLNA_GAIN_ODD_231___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__LNA_GAIN_ODD_231___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__LNA_GAIN_ODD_231___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__GM_GAIN_ODD_231___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__GM_GAIN_ODD_231___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__TIA_GAIN_ODD_231___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__TIA_GAIN_ODD_231___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__SLM_XLNA_ODD_231___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__SLM_XLNA_ODD_231___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__BQ_GAIN_ODD_231___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__BQ_GAIN_ODD_231___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__XLNA_GAIN_EVEN_231___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__XLNA_GAIN_EVEN_231___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__LNA_GAIN_EVEN_231___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__LNA_GAIN_EVEN_231___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__GM_GAIN_EVEN_231___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__GM_GAIN_EVEN_231___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__TIA_GAIN_EVEN_231___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__TIA_GAIN_EVEN_231___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__SLM_XLNA_EVEN_231___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__SLM_XLNA_EVEN_231___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__BQ_GAIN_EVEN_231___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231__BQ_GAIN_EVEN_231___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_231___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232 (0x005F53A0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__XLNA_GAIN_ODD_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__LNA_GAIN_ODD_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__GM_GAIN_ODD_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__TIA_GAIN_ODD_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__SLM_XLNA_ODD_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__BQ_GAIN_ODD_232___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__XLNA_GAIN_EVEN_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__LNA_GAIN_EVEN_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__GM_GAIN_EVEN_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__TIA_GAIN_EVEN_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__SLM_XLNA_EVEN_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__BQ_GAIN_EVEN_232___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__XLNA_GAIN_ODD_232___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__XLNA_GAIN_ODD_232___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__LNA_GAIN_ODD_232___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__LNA_GAIN_ODD_232___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__GM_GAIN_ODD_232___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__GM_GAIN_ODD_232___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__TIA_GAIN_ODD_232___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__TIA_GAIN_ODD_232___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__SLM_XLNA_ODD_232___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__SLM_XLNA_ODD_232___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__BQ_GAIN_ODD_232___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__BQ_GAIN_ODD_232___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__XLNA_GAIN_EVEN_232___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__XLNA_GAIN_EVEN_232___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__LNA_GAIN_EVEN_232___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__LNA_GAIN_EVEN_232___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__GM_GAIN_EVEN_232___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__GM_GAIN_EVEN_232___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__TIA_GAIN_EVEN_232___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__TIA_GAIN_EVEN_232___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__SLM_XLNA_EVEN_232___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__SLM_XLNA_EVEN_232___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__BQ_GAIN_EVEN_232___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232__BQ_GAIN_EVEN_232___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_232___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233 (0x005F53A4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__XLNA_GAIN_ODD_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__LNA_GAIN_ODD_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__GM_GAIN_ODD_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__TIA_GAIN_ODD_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__SLM_XLNA_ODD_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__BQ_GAIN_ODD_233___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__XLNA_GAIN_EVEN_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__LNA_GAIN_EVEN_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__GM_GAIN_EVEN_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__TIA_GAIN_EVEN_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__SLM_XLNA_EVEN_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__BQ_GAIN_EVEN_233___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__XLNA_GAIN_ODD_233___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__XLNA_GAIN_ODD_233___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__LNA_GAIN_ODD_233___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__LNA_GAIN_ODD_233___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__GM_GAIN_ODD_233___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__GM_GAIN_ODD_233___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__TIA_GAIN_ODD_233___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__TIA_GAIN_ODD_233___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__SLM_XLNA_ODD_233___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__SLM_XLNA_ODD_233___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__BQ_GAIN_ODD_233___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__BQ_GAIN_ODD_233___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__XLNA_GAIN_EVEN_233___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__XLNA_GAIN_EVEN_233___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__LNA_GAIN_EVEN_233___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__LNA_GAIN_EVEN_233___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__GM_GAIN_EVEN_233___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__GM_GAIN_EVEN_233___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__TIA_GAIN_EVEN_233___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__TIA_GAIN_EVEN_233___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__SLM_XLNA_EVEN_233___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__SLM_XLNA_EVEN_233___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__BQ_GAIN_EVEN_233___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233__BQ_GAIN_EVEN_233___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_233___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234 (0x005F53A8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__XLNA_GAIN_ODD_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__LNA_GAIN_ODD_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__GM_GAIN_ODD_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__TIA_GAIN_ODD_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__SLM_XLNA_ODD_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__BQ_GAIN_ODD_234___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__XLNA_GAIN_EVEN_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__LNA_GAIN_EVEN_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__GM_GAIN_EVEN_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__TIA_GAIN_EVEN_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__SLM_XLNA_EVEN_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__BQ_GAIN_EVEN_234___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__XLNA_GAIN_ODD_234___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__XLNA_GAIN_ODD_234___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__LNA_GAIN_ODD_234___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__LNA_GAIN_ODD_234___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__GM_GAIN_ODD_234___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__GM_GAIN_ODD_234___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__TIA_GAIN_ODD_234___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__TIA_GAIN_ODD_234___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__SLM_XLNA_ODD_234___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__SLM_XLNA_ODD_234___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__BQ_GAIN_ODD_234___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__BQ_GAIN_ODD_234___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__XLNA_GAIN_EVEN_234___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__XLNA_GAIN_EVEN_234___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__LNA_GAIN_EVEN_234___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__LNA_GAIN_EVEN_234___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__GM_GAIN_EVEN_234___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__GM_GAIN_EVEN_234___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__TIA_GAIN_EVEN_234___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__TIA_GAIN_EVEN_234___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__SLM_XLNA_EVEN_234___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__SLM_XLNA_EVEN_234___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__BQ_GAIN_EVEN_234___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234__BQ_GAIN_EVEN_234___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_234___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235 (0x005F53AC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__XLNA_GAIN_ODD_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__LNA_GAIN_ODD_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__GM_GAIN_ODD_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__TIA_GAIN_ODD_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__SLM_XLNA_ODD_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__BQ_GAIN_ODD_235___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__XLNA_GAIN_EVEN_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__LNA_GAIN_EVEN_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__GM_GAIN_EVEN_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__TIA_GAIN_EVEN_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__SLM_XLNA_EVEN_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__BQ_GAIN_EVEN_235___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__XLNA_GAIN_ODD_235___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__XLNA_GAIN_ODD_235___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__LNA_GAIN_ODD_235___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__LNA_GAIN_ODD_235___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__GM_GAIN_ODD_235___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__GM_GAIN_ODD_235___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__TIA_GAIN_ODD_235___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__TIA_GAIN_ODD_235___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__SLM_XLNA_ODD_235___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__SLM_XLNA_ODD_235___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__BQ_GAIN_ODD_235___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__BQ_GAIN_ODD_235___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__XLNA_GAIN_EVEN_235___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__XLNA_GAIN_EVEN_235___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__LNA_GAIN_EVEN_235___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__LNA_GAIN_EVEN_235___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__GM_GAIN_EVEN_235___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__GM_GAIN_EVEN_235___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__TIA_GAIN_EVEN_235___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__TIA_GAIN_EVEN_235___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__SLM_XLNA_EVEN_235___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__SLM_XLNA_EVEN_235___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__BQ_GAIN_EVEN_235___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235__BQ_GAIN_EVEN_235___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_235___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236 (0x005F53B0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__XLNA_GAIN_ODD_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__LNA_GAIN_ODD_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__GM_GAIN_ODD_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__TIA_GAIN_ODD_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__SLM_XLNA_ODD_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__BQ_GAIN_ODD_236___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__XLNA_GAIN_EVEN_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__LNA_GAIN_EVEN_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__GM_GAIN_EVEN_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__TIA_GAIN_EVEN_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__SLM_XLNA_EVEN_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__BQ_GAIN_EVEN_236___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__XLNA_GAIN_ODD_236___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__XLNA_GAIN_ODD_236___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__LNA_GAIN_ODD_236___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__LNA_GAIN_ODD_236___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__GM_GAIN_ODD_236___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__GM_GAIN_ODD_236___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__TIA_GAIN_ODD_236___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__TIA_GAIN_ODD_236___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__SLM_XLNA_ODD_236___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__SLM_XLNA_ODD_236___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__BQ_GAIN_ODD_236___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__BQ_GAIN_ODD_236___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__XLNA_GAIN_EVEN_236___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__XLNA_GAIN_EVEN_236___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__LNA_GAIN_EVEN_236___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__LNA_GAIN_EVEN_236___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__GM_GAIN_EVEN_236___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__GM_GAIN_EVEN_236___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__TIA_GAIN_EVEN_236___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__TIA_GAIN_EVEN_236___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__SLM_XLNA_EVEN_236___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__SLM_XLNA_EVEN_236___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__BQ_GAIN_EVEN_236___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236__BQ_GAIN_EVEN_236___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_236___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237 (0x005F53B4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__XLNA_GAIN_ODD_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__LNA_GAIN_ODD_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__GM_GAIN_ODD_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__TIA_GAIN_ODD_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__SLM_XLNA_ODD_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__BQ_GAIN_ODD_237___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__XLNA_GAIN_EVEN_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__LNA_GAIN_EVEN_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__GM_GAIN_EVEN_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__TIA_GAIN_EVEN_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__SLM_XLNA_EVEN_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__BQ_GAIN_EVEN_237___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__XLNA_GAIN_ODD_237___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__XLNA_GAIN_ODD_237___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__LNA_GAIN_ODD_237___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__LNA_GAIN_ODD_237___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__GM_GAIN_ODD_237___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__GM_GAIN_ODD_237___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__TIA_GAIN_ODD_237___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__TIA_GAIN_ODD_237___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__SLM_XLNA_ODD_237___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__SLM_XLNA_ODD_237___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__BQ_GAIN_ODD_237___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__BQ_GAIN_ODD_237___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__XLNA_GAIN_EVEN_237___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__XLNA_GAIN_EVEN_237___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__LNA_GAIN_EVEN_237___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__LNA_GAIN_EVEN_237___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__GM_GAIN_EVEN_237___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__GM_GAIN_EVEN_237___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__TIA_GAIN_EVEN_237___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__TIA_GAIN_EVEN_237___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__SLM_XLNA_EVEN_237___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__SLM_XLNA_EVEN_237___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__BQ_GAIN_EVEN_237___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237__BQ_GAIN_EVEN_237___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_237___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238 (0x005F53B8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__XLNA_GAIN_ODD_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__LNA_GAIN_ODD_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__GM_GAIN_ODD_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__TIA_GAIN_ODD_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__SLM_XLNA_ODD_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__BQ_GAIN_ODD_238___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__XLNA_GAIN_EVEN_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__LNA_GAIN_EVEN_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__GM_GAIN_EVEN_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__TIA_GAIN_EVEN_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__SLM_XLNA_EVEN_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__BQ_GAIN_EVEN_238___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__XLNA_GAIN_ODD_238___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__XLNA_GAIN_ODD_238___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__LNA_GAIN_ODD_238___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__LNA_GAIN_ODD_238___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__GM_GAIN_ODD_238___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__GM_GAIN_ODD_238___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__TIA_GAIN_ODD_238___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__TIA_GAIN_ODD_238___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__SLM_XLNA_ODD_238___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__SLM_XLNA_ODD_238___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__BQ_GAIN_ODD_238___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__BQ_GAIN_ODD_238___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__XLNA_GAIN_EVEN_238___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__XLNA_GAIN_EVEN_238___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__LNA_GAIN_EVEN_238___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__LNA_GAIN_EVEN_238___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__GM_GAIN_EVEN_238___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__GM_GAIN_EVEN_238___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__TIA_GAIN_EVEN_238___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__TIA_GAIN_EVEN_238___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__SLM_XLNA_EVEN_238___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__SLM_XLNA_EVEN_238___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__BQ_GAIN_EVEN_238___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238__BQ_GAIN_EVEN_238___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_238___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239 (0x005F53BC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__XLNA_GAIN_ODD_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__LNA_GAIN_ODD_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__GM_GAIN_ODD_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__TIA_GAIN_ODD_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__SLM_XLNA_ODD_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__BQ_GAIN_ODD_239___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__XLNA_GAIN_EVEN_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__LNA_GAIN_EVEN_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__GM_GAIN_EVEN_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__TIA_GAIN_EVEN_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__SLM_XLNA_EVEN_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__BQ_GAIN_EVEN_239___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__XLNA_GAIN_ODD_239___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__XLNA_GAIN_ODD_239___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__LNA_GAIN_ODD_239___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__LNA_GAIN_ODD_239___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__GM_GAIN_ODD_239___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__GM_GAIN_ODD_239___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__TIA_GAIN_ODD_239___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__TIA_GAIN_ODD_239___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__SLM_XLNA_ODD_239___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__SLM_XLNA_ODD_239___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__BQ_GAIN_ODD_239___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__BQ_GAIN_ODD_239___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__XLNA_GAIN_EVEN_239___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__XLNA_GAIN_EVEN_239___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__LNA_GAIN_EVEN_239___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__LNA_GAIN_EVEN_239___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__GM_GAIN_EVEN_239___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__GM_GAIN_EVEN_239___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__TIA_GAIN_EVEN_239___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__TIA_GAIN_EVEN_239___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__SLM_XLNA_EVEN_239___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__SLM_XLNA_EVEN_239___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__BQ_GAIN_EVEN_239___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239__BQ_GAIN_EVEN_239___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_239___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240 (0x005F53C0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__XLNA_GAIN_ODD_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__LNA_GAIN_ODD_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__GM_GAIN_ODD_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__TIA_GAIN_ODD_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__SLM_XLNA_ODD_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__BQ_GAIN_ODD_240___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__XLNA_GAIN_EVEN_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__LNA_GAIN_EVEN_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__GM_GAIN_EVEN_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__TIA_GAIN_EVEN_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__SLM_XLNA_EVEN_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__BQ_GAIN_EVEN_240___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__XLNA_GAIN_ODD_240___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__XLNA_GAIN_ODD_240___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__LNA_GAIN_ODD_240___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__LNA_GAIN_ODD_240___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__GM_GAIN_ODD_240___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__GM_GAIN_ODD_240___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__TIA_GAIN_ODD_240___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__TIA_GAIN_ODD_240___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__SLM_XLNA_ODD_240___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__SLM_XLNA_ODD_240___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__BQ_GAIN_ODD_240___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__BQ_GAIN_ODD_240___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__XLNA_GAIN_EVEN_240___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__XLNA_GAIN_EVEN_240___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__LNA_GAIN_EVEN_240___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__LNA_GAIN_EVEN_240___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__GM_GAIN_EVEN_240___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__GM_GAIN_EVEN_240___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__TIA_GAIN_EVEN_240___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__TIA_GAIN_EVEN_240___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__SLM_XLNA_EVEN_240___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__SLM_XLNA_EVEN_240___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__BQ_GAIN_EVEN_240___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240__BQ_GAIN_EVEN_240___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_240___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241 (0x005F53C4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__XLNA_GAIN_ODD_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__LNA_GAIN_ODD_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__GM_GAIN_ODD_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__TIA_GAIN_ODD_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__SLM_XLNA_ODD_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__BQ_GAIN_ODD_241___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__XLNA_GAIN_EVEN_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__LNA_GAIN_EVEN_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__GM_GAIN_EVEN_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__TIA_GAIN_EVEN_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__SLM_XLNA_EVEN_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__BQ_GAIN_EVEN_241___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__XLNA_GAIN_ODD_241___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__XLNA_GAIN_ODD_241___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__LNA_GAIN_ODD_241___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__LNA_GAIN_ODD_241___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__GM_GAIN_ODD_241___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__GM_GAIN_ODD_241___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__TIA_GAIN_ODD_241___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__TIA_GAIN_ODD_241___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__SLM_XLNA_ODD_241___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__SLM_XLNA_ODD_241___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__BQ_GAIN_ODD_241___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__BQ_GAIN_ODD_241___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__XLNA_GAIN_EVEN_241___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__XLNA_GAIN_EVEN_241___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__LNA_GAIN_EVEN_241___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__LNA_GAIN_EVEN_241___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__GM_GAIN_EVEN_241___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__GM_GAIN_EVEN_241___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__TIA_GAIN_EVEN_241___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__TIA_GAIN_EVEN_241___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__SLM_XLNA_EVEN_241___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__SLM_XLNA_EVEN_241___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__BQ_GAIN_EVEN_241___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241__BQ_GAIN_EVEN_241___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_241___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242 (0x005F53C8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__XLNA_GAIN_ODD_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__LNA_GAIN_ODD_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__GM_GAIN_ODD_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__TIA_GAIN_ODD_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__SLM_XLNA_ODD_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__BQ_GAIN_ODD_242___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__XLNA_GAIN_EVEN_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__LNA_GAIN_EVEN_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__GM_GAIN_EVEN_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__TIA_GAIN_EVEN_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__SLM_XLNA_EVEN_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__BQ_GAIN_EVEN_242___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__XLNA_GAIN_ODD_242___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__XLNA_GAIN_ODD_242___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__LNA_GAIN_ODD_242___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__LNA_GAIN_ODD_242___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__GM_GAIN_ODD_242___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__GM_GAIN_ODD_242___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__TIA_GAIN_ODD_242___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__TIA_GAIN_ODD_242___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__SLM_XLNA_ODD_242___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__SLM_XLNA_ODD_242___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__BQ_GAIN_ODD_242___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__BQ_GAIN_ODD_242___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__XLNA_GAIN_EVEN_242___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__XLNA_GAIN_EVEN_242___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__LNA_GAIN_EVEN_242___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__LNA_GAIN_EVEN_242___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__GM_GAIN_EVEN_242___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__GM_GAIN_EVEN_242___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__TIA_GAIN_EVEN_242___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__TIA_GAIN_EVEN_242___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__SLM_XLNA_EVEN_242___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__SLM_XLNA_EVEN_242___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__BQ_GAIN_EVEN_242___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242__BQ_GAIN_EVEN_242___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_242___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243 (0x005F53CC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__XLNA_GAIN_ODD_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__LNA_GAIN_ODD_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__GM_GAIN_ODD_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__TIA_GAIN_ODD_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__SLM_XLNA_ODD_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__BQ_GAIN_ODD_243___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__XLNA_GAIN_EVEN_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__LNA_GAIN_EVEN_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__GM_GAIN_EVEN_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__TIA_GAIN_EVEN_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__SLM_XLNA_EVEN_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__BQ_GAIN_EVEN_243___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__XLNA_GAIN_ODD_243___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__XLNA_GAIN_ODD_243___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__LNA_GAIN_ODD_243___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__LNA_GAIN_ODD_243___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__GM_GAIN_ODD_243___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__GM_GAIN_ODD_243___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__TIA_GAIN_ODD_243___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__TIA_GAIN_ODD_243___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__SLM_XLNA_ODD_243___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__SLM_XLNA_ODD_243___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__BQ_GAIN_ODD_243___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__BQ_GAIN_ODD_243___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__XLNA_GAIN_EVEN_243___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__XLNA_GAIN_EVEN_243___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__LNA_GAIN_EVEN_243___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__LNA_GAIN_EVEN_243___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__GM_GAIN_EVEN_243___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__GM_GAIN_EVEN_243___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__TIA_GAIN_EVEN_243___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__TIA_GAIN_EVEN_243___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__SLM_XLNA_EVEN_243___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__SLM_XLNA_EVEN_243___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__BQ_GAIN_EVEN_243___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243__BQ_GAIN_EVEN_243___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_243___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244 (0x005F53D0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__XLNA_GAIN_ODD_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__LNA_GAIN_ODD_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__GM_GAIN_ODD_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__TIA_GAIN_ODD_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__SLM_XLNA_ODD_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__BQ_GAIN_ODD_244___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__XLNA_GAIN_EVEN_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__LNA_GAIN_EVEN_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__GM_GAIN_EVEN_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__TIA_GAIN_EVEN_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__SLM_XLNA_EVEN_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__BQ_GAIN_EVEN_244___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__XLNA_GAIN_ODD_244___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__XLNA_GAIN_ODD_244___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__LNA_GAIN_ODD_244___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__LNA_GAIN_ODD_244___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__GM_GAIN_ODD_244___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__GM_GAIN_ODD_244___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__TIA_GAIN_ODD_244___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__TIA_GAIN_ODD_244___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__SLM_XLNA_ODD_244___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__SLM_XLNA_ODD_244___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__BQ_GAIN_ODD_244___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__BQ_GAIN_ODD_244___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__XLNA_GAIN_EVEN_244___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__XLNA_GAIN_EVEN_244___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__LNA_GAIN_EVEN_244___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__LNA_GAIN_EVEN_244___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__GM_GAIN_EVEN_244___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__GM_GAIN_EVEN_244___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__TIA_GAIN_EVEN_244___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__TIA_GAIN_EVEN_244___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__SLM_XLNA_EVEN_244___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__SLM_XLNA_EVEN_244___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__BQ_GAIN_EVEN_244___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244__BQ_GAIN_EVEN_244___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_244___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245 (0x005F53D4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__XLNA_GAIN_ODD_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__LNA_GAIN_ODD_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__GM_GAIN_ODD_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__TIA_GAIN_ODD_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__SLM_XLNA_ODD_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__BQ_GAIN_ODD_245___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__XLNA_GAIN_EVEN_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__LNA_GAIN_EVEN_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__GM_GAIN_EVEN_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__TIA_GAIN_EVEN_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__SLM_XLNA_EVEN_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__BQ_GAIN_EVEN_245___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__XLNA_GAIN_ODD_245___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__XLNA_GAIN_ODD_245___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__LNA_GAIN_ODD_245___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__LNA_GAIN_ODD_245___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__GM_GAIN_ODD_245___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__GM_GAIN_ODD_245___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__TIA_GAIN_ODD_245___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__TIA_GAIN_ODD_245___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__SLM_XLNA_ODD_245___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__SLM_XLNA_ODD_245___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__BQ_GAIN_ODD_245___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__BQ_GAIN_ODD_245___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__XLNA_GAIN_EVEN_245___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__XLNA_GAIN_EVEN_245___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__LNA_GAIN_EVEN_245___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__LNA_GAIN_EVEN_245___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__GM_GAIN_EVEN_245___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__GM_GAIN_EVEN_245___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__TIA_GAIN_EVEN_245___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__TIA_GAIN_EVEN_245___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__SLM_XLNA_EVEN_245___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__SLM_XLNA_EVEN_245___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__BQ_GAIN_EVEN_245___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245__BQ_GAIN_EVEN_245___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_245___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246 (0x005F53D8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__XLNA_GAIN_ODD_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__LNA_GAIN_ODD_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__GM_GAIN_ODD_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__TIA_GAIN_ODD_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__SLM_XLNA_ODD_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__BQ_GAIN_ODD_246___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__XLNA_GAIN_EVEN_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__LNA_GAIN_EVEN_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__GM_GAIN_EVEN_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__TIA_GAIN_EVEN_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__SLM_XLNA_EVEN_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__BQ_GAIN_EVEN_246___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__XLNA_GAIN_ODD_246___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__XLNA_GAIN_ODD_246___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__LNA_GAIN_ODD_246___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__LNA_GAIN_ODD_246___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__GM_GAIN_ODD_246___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__GM_GAIN_ODD_246___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__TIA_GAIN_ODD_246___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__TIA_GAIN_ODD_246___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__SLM_XLNA_ODD_246___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__SLM_XLNA_ODD_246___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__BQ_GAIN_ODD_246___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__BQ_GAIN_ODD_246___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__XLNA_GAIN_EVEN_246___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__XLNA_GAIN_EVEN_246___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__LNA_GAIN_EVEN_246___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__LNA_GAIN_EVEN_246___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__GM_GAIN_EVEN_246___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__GM_GAIN_EVEN_246___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__TIA_GAIN_EVEN_246___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__TIA_GAIN_EVEN_246___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__SLM_XLNA_EVEN_246___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__SLM_XLNA_EVEN_246___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__BQ_GAIN_EVEN_246___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246__BQ_GAIN_EVEN_246___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_246___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247 (0x005F53DC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__XLNA_GAIN_ODD_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__LNA_GAIN_ODD_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__GM_GAIN_ODD_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__TIA_GAIN_ODD_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__SLM_XLNA_ODD_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__BQ_GAIN_ODD_247___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__XLNA_GAIN_EVEN_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__LNA_GAIN_EVEN_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__GM_GAIN_EVEN_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__TIA_GAIN_EVEN_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__SLM_XLNA_EVEN_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__BQ_GAIN_EVEN_247___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__XLNA_GAIN_ODD_247___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__XLNA_GAIN_ODD_247___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__LNA_GAIN_ODD_247___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__LNA_GAIN_ODD_247___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__GM_GAIN_ODD_247___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__GM_GAIN_ODD_247___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__TIA_GAIN_ODD_247___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__TIA_GAIN_ODD_247___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__SLM_XLNA_ODD_247___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__SLM_XLNA_ODD_247___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__BQ_GAIN_ODD_247___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__BQ_GAIN_ODD_247___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__XLNA_GAIN_EVEN_247___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__XLNA_GAIN_EVEN_247___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__LNA_GAIN_EVEN_247___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__LNA_GAIN_EVEN_247___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__GM_GAIN_EVEN_247___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__GM_GAIN_EVEN_247___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__TIA_GAIN_EVEN_247___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__TIA_GAIN_EVEN_247___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__SLM_XLNA_EVEN_247___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__SLM_XLNA_EVEN_247___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__BQ_GAIN_EVEN_247___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247__BQ_GAIN_EVEN_247___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_247___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248 (0x005F53E0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__XLNA_GAIN_ODD_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__LNA_GAIN_ODD_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__GM_GAIN_ODD_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__TIA_GAIN_ODD_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__SLM_XLNA_ODD_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__BQ_GAIN_ODD_248___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__XLNA_GAIN_EVEN_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__LNA_GAIN_EVEN_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__GM_GAIN_EVEN_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__TIA_GAIN_EVEN_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__SLM_XLNA_EVEN_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__BQ_GAIN_EVEN_248___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__XLNA_GAIN_ODD_248___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__XLNA_GAIN_ODD_248___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__LNA_GAIN_ODD_248___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__LNA_GAIN_ODD_248___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__GM_GAIN_ODD_248___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__GM_GAIN_ODD_248___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__TIA_GAIN_ODD_248___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__TIA_GAIN_ODD_248___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__SLM_XLNA_ODD_248___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__SLM_XLNA_ODD_248___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__BQ_GAIN_ODD_248___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__BQ_GAIN_ODD_248___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__XLNA_GAIN_EVEN_248___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__XLNA_GAIN_EVEN_248___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__LNA_GAIN_EVEN_248___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__LNA_GAIN_EVEN_248___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__GM_GAIN_EVEN_248___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__GM_GAIN_EVEN_248___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__TIA_GAIN_EVEN_248___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__TIA_GAIN_EVEN_248___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__SLM_XLNA_EVEN_248___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__SLM_XLNA_EVEN_248___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__BQ_GAIN_EVEN_248___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248__BQ_GAIN_EVEN_248___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_248___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249 (0x005F53E4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__XLNA_GAIN_ODD_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__LNA_GAIN_ODD_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__GM_GAIN_ODD_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__TIA_GAIN_ODD_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__SLM_XLNA_ODD_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__BQ_GAIN_ODD_249___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__XLNA_GAIN_EVEN_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__LNA_GAIN_EVEN_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__GM_GAIN_EVEN_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__TIA_GAIN_EVEN_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__SLM_XLNA_EVEN_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__BQ_GAIN_EVEN_249___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__XLNA_GAIN_ODD_249___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__XLNA_GAIN_ODD_249___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__LNA_GAIN_ODD_249___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__LNA_GAIN_ODD_249___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__GM_GAIN_ODD_249___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__GM_GAIN_ODD_249___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__TIA_GAIN_ODD_249___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__TIA_GAIN_ODD_249___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__SLM_XLNA_ODD_249___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__SLM_XLNA_ODD_249___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__BQ_GAIN_ODD_249___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__BQ_GAIN_ODD_249___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__XLNA_GAIN_EVEN_249___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__XLNA_GAIN_EVEN_249___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__LNA_GAIN_EVEN_249___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__LNA_GAIN_EVEN_249___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__GM_GAIN_EVEN_249___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__GM_GAIN_EVEN_249___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__TIA_GAIN_EVEN_249___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__TIA_GAIN_EVEN_249___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__SLM_XLNA_EVEN_249___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__SLM_XLNA_EVEN_249___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__BQ_GAIN_EVEN_249___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249__BQ_GAIN_EVEN_249___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_249___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250 (0x005F53E8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__XLNA_GAIN_ODD_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__LNA_GAIN_ODD_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__GM_GAIN_ODD_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__TIA_GAIN_ODD_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__SLM_XLNA_ODD_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__BQ_GAIN_ODD_250___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__XLNA_GAIN_EVEN_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__LNA_GAIN_EVEN_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__GM_GAIN_EVEN_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__TIA_GAIN_EVEN_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__SLM_XLNA_EVEN_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__BQ_GAIN_EVEN_250___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__XLNA_GAIN_ODD_250___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__XLNA_GAIN_ODD_250___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__LNA_GAIN_ODD_250___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__LNA_GAIN_ODD_250___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__GM_GAIN_ODD_250___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__GM_GAIN_ODD_250___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__TIA_GAIN_ODD_250___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__TIA_GAIN_ODD_250___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__SLM_XLNA_ODD_250___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__SLM_XLNA_ODD_250___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__BQ_GAIN_ODD_250___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__BQ_GAIN_ODD_250___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__XLNA_GAIN_EVEN_250___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__XLNA_GAIN_EVEN_250___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__LNA_GAIN_EVEN_250___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__LNA_GAIN_EVEN_250___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__GM_GAIN_EVEN_250___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__GM_GAIN_EVEN_250___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__TIA_GAIN_EVEN_250___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__TIA_GAIN_EVEN_250___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__SLM_XLNA_EVEN_250___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__SLM_XLNA_EVEN_250___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__BQ_GAIN_EVEN_250___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250__BQ_GAIN_EVEN_250___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_250___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251 (0x005F53EC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__XLNA_GAIN_ODD_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__LNA_GAIN_ODD_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__GM_GAIN_ODD_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__TIA_GAIN_ODD_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__SLM_XLNA_ODD_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__BQ_GAIN_ODD_251___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__XLNA_GAIN_EVEN_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__LNA_GAIN_EVEN_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__GM_GAIN_EVEN_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__TIA_GAIN_EVEN_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__SLM_XLNA_EVEN_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__BQ_GAIN_EVEN_251___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__XLNA_GAIN_ODD_251___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__XLNA_GAIN_ODD_251___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__LNA_GAIN_ODD_251___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__LNA_GAIN_ODD_251___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__GM_GAIN_ODD_251___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__GM_GAIN_ODD_251___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__TIA_GAIN_ODD_251___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__TIA_GAIN_ODD_251___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__SLM_XLNA_ODD_251___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__SLM_XLNA_ODD_251___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__BQ_GAIN_ODD_251___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__BQ_GAIN_ODD_251___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__XLNA_GAIN_EVEN_251___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__XLNA_GAIN_EVEN_251___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__LNA_GAIN_EVEN_251___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__LNA_GAIN_EVEN_251___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__GM_GAIN_EVEN_251___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__GM_GAIN_EVEN_251___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__TIA_GAIN_EVEN_251___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__TIA_GAIN_EVEN_251___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__SLM_XLNA_EVEN_251___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__SLM_XLNA_EVEN_251___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__BQ_GAIN_EVEN_251___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251__BQ_GAIN_EVEN_251___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_251___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252 (0x005F53F0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__XLNA_GAIN_ODD_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__LNA_GAIN_ODD_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__GM_GAIN_ODD_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__TIA_GAIN_ODD_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__SLM_XLNA_ODD_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__BQ_GAIN_ODD_252___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__XLNA_GAIN_EVEN_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__LNA_GAIN_EVEN_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__GM_GAIN_EVEN_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__TIA_GAIN_EVEN_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__SLM_XLNA_EVEN_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__BQ_GAIN_EVEN_252___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__XLNA_GAIN_ODD_252___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__XLNA_GAIN_ODD_252___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__LNA_GAIN_ODD_252___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__LNA_GAIN_ODD_252___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__GM_GAIN_ODD_252___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__GM_GAIN_ODD_252___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__TIA_GAIN_ODD_252___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__TIA_GAIN_ODD_252___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__SLM_XLNA_ODD_252___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__SLM_XLNA_ODD_252___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__BQ_GAIN_ODD_252___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__BQ_GAIN_ODD_252___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__XLNA_GAIN_EVEN_252___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__XLNA_GAIN_EVEN_252___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__LNA_GAIN_EVEN_252___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__LNA_GAIN_EVEN_252___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__GM_GAIN_EVEN_252___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__GM_GAIN_EVEN_252___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__TIA_GAIN_EVEN_252___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__TIA_GAIN_EVEN_252___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__SLM_XLNA_EVEN_252___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__SLM_XLNA_EVEN_252___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__BQ_GAIN_EVEN_252___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252__BQ_GAIN_EVEN_252___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_252___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253 (0x005F53F4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__XLNA_GAIN_ODD_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__LNA_GAIN_ODD_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__GM_GAIN_ODD_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__TIA_GAIN_ODD_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__SLM_XLNA_ODD_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__BQ_GAIN_ODD_253___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__XLNA_GAIN_EVEN_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__LNA_GAIN_EVEN_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__GM_GAIN_EVEN_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__TIA_GAIN_EVEN_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__SLM_XLNA_EVEN_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__BQ_GAIN_EVEN_253___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__XLNA_GAIN_ODD_253___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__XLNA_GAIN_ODD_253___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__LNA_GAIN_ODD_253___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__LNA_GAIN_ODD_253___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__GM_GAIN_ODD_253___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__GM_GAIN_ODD_253___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__TIA_GAIN_ODD_253___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__TIA_GAIN_ODD_253___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__SLM_XLNA_ODD_253___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__SLM_XLNA_ODD_253___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__BQ_GAIN_ODD_253___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__BQ_GAIN_ODD_253___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__XLNA_GAIN_EVEN_253___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__XLNA_GAIN_EVEN_253___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__LNA_GAIN_EVEN_253___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__LNA_GAIN_EVEN_253___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__GM_GAIN_EVEN_253___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__GM_GAIN_EVEN_253___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__TIA_GAIN_EVEN_253___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__TIA_GAIN_EVEN_253___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__SLM_XLNA_EVEN_253___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__SLM_XLNA_EVEN_253___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__BQ_GAIN_EVEN_253___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253__BQ_GAIN_EVEN_253___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_253___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254 (0x005F53F8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__XLNA_GAIN_ODD_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__LNA_GAIN_ODD_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__GM_GAIN_ODD_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__TIA_GAIN_ODD_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__SLM_XLNA_ODD_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__BQ_GAIN_ODD_254___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__XLNA_GAIN_EVEN_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__LNA_GAIN_EVEN_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__GM_GAIN_EVEN_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__TIA_GAIN_EVEN_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__SLM_XLNA_EVEN_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__BQ_GAIN_EVEN_254___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__XLNA_GAIN_ODD_254___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__XLNA_GAIN_ODD_254___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__LNA_GAIN_ODD_254___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__LNA_GAIN_ODD_254___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__GM_GAIN_ODD_254___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__GM_GAIN_ODD_254___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__TIA_GAIN_ODD_254___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__TIA_GAIN_ODD_254___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__SLM_XLNA_ODD_254___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__SLM_XLNA_ODD_254___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__BQ_GAIN_ODD_254___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__BQ_GAIN_ODD_254___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__XLNA_GAIN_EVEN_254___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__XLNA_GAIN_EVEN_254___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__LNA_GAIN_EVEN_254___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__LNA_GAIN_EVEN_254___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__GM_GAIN_EVEN_254___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__GM_GAIN_EVEN_254___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__TIA_GAIN_EVEN_254___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__TIA_GAIN_EVEN_254___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__SLM_XLNA_EVEN_254___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__SLM_XLNA_EVEN_254___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__BQ_GAIN_EVEN_254___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254__BQ_GAIN_EVEN_254___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_254___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255 (0x005F53FC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__XLNA_GAIN_ODD_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__LNA_GAIN_ODD_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__GM_GAIN_ODD_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__TIA_GAIN_ODD_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__SLM_XLNA_ODD_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__BQ_GAIN_ODD_255___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__XLNA_GAIN_EVEN_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__LNA_GAIN_EVEN_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__GM_GAIN_EVEN_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__TIA_GAIN_EVEN_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__SLM_XLNA_EVEN_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__BQ_GAIN_EVEN_255___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__XLNA_GAIN_ODD_255___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__XLNA_GAIN_ODD_255___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__LNA_GAIN_ODD_255___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__LNA_GAIN_ODD_255___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__GM_GAIN_ODD_255___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__GM_GAIN_ODD_255___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__TIA_GAIN_ODD_255___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__TIA_GAIN_ODD_255___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__SLM_XLNA_ODD_255___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__SLM_XLNA_ODD_255___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__BQ_GAIN_ODD_255___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__BQ_GAIN_ODD_255___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__XLNA_GAIN_EVEN_255___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__XLNA_GAIN_EVEN_255___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__LNA_GAIN_EVEN_255___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__LNA_GAIN_EVEN_255___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__GM_GAIN_EVEN_255___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__GM_GAIN_EVEN_255___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__TIA_GAIN_EVEN_255___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__TIA_GAIN_EVEN_255___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__SLM_XLNA_EVEN_255___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__SLM_XLNA_EVEN_255___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__BQ_GAIN_EVEN_255___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255__BQ_GAIN_EVEN_255___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_RXGAIN_255___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_0 (0x005F5800) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_0__TX_DCOC_RES_I_ODD_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_0__TX_DCOC_RES_Q_ODD_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_0__TX_DCOC_RES_I_EVEN_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_0__TX_DCOC_RES_Q_EVEN_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_0__TX_DCOC_RES_I_ODD_0___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_0__TX_DCOC_RES_I_ODD_0___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_0__TX_DCOC_RES_Q_ODD_0___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_0__TX_DCOC_RES_Q_ODD_0___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_0__TX_DCOC_RES_I_EVEN_0___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_0__TX_DCOC_RES_I_EVEN_0___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_0__TX_DCOC_RES_Q_EVEN_0___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_0__TX_DCOC_RES_Q_EVEN_0___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_0___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_1 (0x005F5804) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_1__TX_DCOC_RES_I_ODD_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_1__TX_DCOC_RES_Q_ODD_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_1__TX_DCOC_RES_I_EVEN_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_1__TX_DCOC_RES_Q_EVEN_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_1__TX_DCOC_RES_I_ODD_1___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_1__TX_DCOC_RES_I_ODD_1___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_1__TX_DCOC_RES_Q_ODD_1___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_1__TX_DCOC_RES_Q_ODD_1___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_1__TX_DCOC_RES_I_EVEN_1___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_1__TX_DCOC_RES_I_EVEN_1___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_1__TX_DCOC_RES_Q_EVEN_1___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_1__TX_DCOC_RES_Q_EVEN_1___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_1___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_2 (0x005F5808) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_2__TX_DCOC_RES_I_ODD_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_2__TX_DCOC_RES_Q_ODD_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_2__TX_DCOC_RES_I_EVEN_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_2__TX_DCOC_RES_Q_EVEN_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_2__TX_DCOC_RES_I_ODD_2___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_2__TX_DCOC_RES_I_ODD_2___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_2__TX_DCOC_RES_Q_ODD_2___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_2__TX_DCOC_RES_Q_ODD_2___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_2__TX_DCOC_RES_I_EVEN_2___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_2__TX_DCOC_RES_I_EVEN_2___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_2__TX_DCOC_RES_Q_EVEN_2___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_2__TX_DCOC_RES_Q_EVEN_2___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_2___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_2___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_3 (0x005F580C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_3__TX_DCOC_RES_I_ODD_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_3__TX_DCOC_RES_Q_ODD_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_3__TX_DCOC_RES_I_EVEN_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_3__TX_DCOC_RES_Q_EVEN_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_3__TX_DCOC_RES_I_ODD_3___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_3__TX_DCOC_RES_I_ODD_3___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_3__TX_DCOC_RES_Q_ODD_3___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_3__TX_DCOC_RES_Q_ODD_3___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_3__TX_DCOC_RES_I_EVEN_3___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_3__TX_DCOC_RES_I_EVEN_3___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_3__TX_DCOC_RES_Q_EVEN_3___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_3__TX_DCOC_RES_Q_EVEN_3___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_3___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_3___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_4 (0x005F5810) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_4__TX_DCOC_RES_I_ODD_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_4__TX_DCOC_RES_Q_ODD_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_4__TX_DCOC_RES_I_EVEN_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_4__TX_DCOC_RES_Q_EVEN_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_4__TX_DCOC_RES_I_ODD_4___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_4__TX_DCOC_RES_I_ODD_4___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_4__TX_DCOC_RES_Q_ODD_4___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_4__TX_DCOC_RES_Q_ODD_4___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_4__TX_DCOC_RES_I_EVEN_4___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_4__TX_DCOC_RES_I_EVEN_4___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_4__TX_DCOC_RES_Q_EVEN_4___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_4__TX_DCOC_RES_Q_EVEN_4___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_4___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_4___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_5 (0x005F5814) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_5__TX_DCOC_RES_I_ODD_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_5__TX_DCOC_RES_Q_ODD_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_5__TX_DCOC_RES_I_EVEN_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_5__TX_DCOC_RES_Q_EVEN_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_5__TX_DCOC_RES_I_ODD_5___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_5__TX_DCOC_RES_I_ODD_5___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_5__TX_DCOC_RES_Q_ODD_5___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_5__TX_DCOC_RES_Q_ODD_5___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_5__TX_DCOC_RES_I_EVEN_5___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_5__TX_DCOC_RES_I_EVEN_5___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_5__TX_DCOC_RES_Q_EVEN_5___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_5__TX_DCOC_RES_Q_EVEN_5___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_5___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_5___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_6 (0x005F5818) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_6__TX_DCOC_RES_I_ODD_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_6__TX_DCOC_RES_Q_ODD_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_6__TX_DCOC_RES_I_EVEN_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_6__TX_DCOC_RES_Q_EVEN_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_6__TX_DCOC_RES_I_ODD_6___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_6__TX_DCOC_RES_I_ODD_6___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_6__TX_DCOC_RES_Q_ODD_6___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_6__TX_DCOC_RES_Q_ODD_6___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_6__TX_DCOC_RES_I_EVEN_6___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_6__TX_DCOC_RES_I_EVEN_6___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_6__TX_DCOC_RES_Q_EVEN_6___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_6__TX_DCOC_RES_Q_EVEN_6___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_6___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_6___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_7 (0x005F581C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_7__TX_DCOC_RES_I_ODD_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_7__TX_DCOC_RES_Q_ODD_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_7__TX_DCOC_RES_I_EVEN_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_7__TX_DCOC_RES_Q_EVEN_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_7__TX_DCOC_RES_I_ODD_7___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_7__TX_DCOC_RES_I_ODD_7___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_7__TX_DCOC_RES_Q_ODD_7___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_7__TX_DCOC_RES_Q_ODD_7___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_7__TX_DCOC_RES_I_EVEN_7___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_7__TX_DCOC_RES_I_EVEN_7___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_7__TX_DCOC_RES_Q_EVEN_7___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_7__TX_DCOC_RES_Q_EVEN_7___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_7___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_7___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_8 (0x005F5820) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_8__TX_DCOC_RES_I_ODD_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_8__TX_DCOC_RES_Q_ODD_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_8__TX_DCOC_RES_I_EVEN_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_8__TX_DCOC_RES_Q_EVEN_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_8__TX_DCOC_RES_I_ODD_8___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_8__TX_DCOC_RES_I_ODD_8___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_8__TX_DCOC_RES_Q_ODD_8___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_8__TX_DCOC_RES_Q_ODD_8___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_8__TX_DCOC_RES_I_EVEN_8___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_8__TX_DCOC_RES_I_EVEN_8___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_8__TX_DCOC_RES_Q_EVEN_8___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_8__TX_DCOC_RES_Q_EVEN_8___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_8___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_8___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_9 (0x005F5824) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_9__TX_DCOC_RES_I_ODD_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_9__TX_DCOC_RES_Q_ODD_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_9__TX_DCOC_RES_I_EVEN_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_9__TX_DCOC_RES_Q_EVEN_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_9__TX_DCOC_RES_I_ODD_9___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_9__TX_DCOC_RES_I_ODD_9___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_9__TX_DCOC_RES_Q_ODD_9___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_9__TX_DCOC_RES_Q_ODD_9___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_9__TX_DCOC_RES_I_EVEN_9___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_9__TX_DCOC_RES_I_EVEN_9___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_9__TX_DCOC_RES_Q_EVEN_9___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_9__TX_DCOC_RES_Q_EVEN_9___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_9___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_9___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_10 (0x005F5828) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_10__TX_DCOC_RES_I_ODD_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_10__TX_DCOC_RES_Q_ODD_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_10__TX_DCOC_RES_I_EVEN_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_10__TX_DCOC_RES_Q_EVEN_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_10__TX_DCOC_RES_I_ODD_10___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_10__TX_DCOC_RES_I_ODD_10___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_10__TX_DCOC_RES_Q_ODD_10___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_10__TX_DCOC_RES_Q_ODD_10___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_10__TX_DCOC_RES_I_EVEN_10___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_10__TX_DCOC_RES_I_EVEN_10___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_10__TX_DCOC_RES_Q_EVEN_10___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_10__TX_DCOC_RES_Q_EVEN_10___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_10___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_10___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_11 (0x005F582C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_11__TX_DCOC_RES_I_ODD_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_11__TX_DCOC_RES_Q_ODD_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_11__TX_DCOC_RES_I_EVEN_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_11__TX_DCOC_RES_Q_EVEN_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_11__TX_DCOC_RES_I_ODD_11___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_11__TX_DCOC_RES_I_ODD_11___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_11__TX_DCOC_RES_Q_ODD_11___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_11__TX_DCOC_RES_Q_ODD_11___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_11__TX_DCOC_RES_I_EVEN_11___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_11__TX_DCOC_RES_I_EVEN_11___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_11__TX_DCOC_RES_Q_EVEN_11___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_11__TX_DCOC_RES_Q_EVEN_11___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_11___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_11___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_12 (0x005F5830) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_12__TX_DCOC_RES_I_ODD_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_12__TX_DCOC_RES_Q_ODD_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_12__TX_DCOC_RES_I_EVEN_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_12__TX_DCOC_RES_Q_EVEN_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_12__TX_DCOC_RES_I_ODD_12___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_12__TX_DCOC_RES_I_ODD_12___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_12__TX_DCOC_RES_Q_ODD_12___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_12__TX_DCOC_RES_Q_ODD_12___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_12__TX_DCOC_RES_I_EVEN_12___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_12__TX_DCOC_RES_I_EVEN_12___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_12__TX_DCOC_RES_Q_EVEN_12___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_12__TX_DCOC_RES_Q_EVEN_12___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_12___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_12___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_13 (0x005F5834) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_13__TX_DCOC_RES_I_ODD_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_13__TX_DCOC_RES_Q_ODD_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_13__TX_DCOC_RES_I_EVEN_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_13__TX_DCOC_RES_Q_EVEN_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_13__TX_DCOC_RES_I_ODD_13___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_13__TX_DCOC_RES_I_ODD_13___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_13__TX_DCOC_RES_Q_ODD_13___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_13__TX_DCOC_RES_Q_ODD_13___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_13__TX_DCOC_RES_I_EVEN_13___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_13__TX_DCOC_RES_I_EVEN_13___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_13__TX_DCOC_RES_Q_EVEN_13___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_13__TX_DCOC_RES_Q_EVEN_13___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_13___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_13___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_14 (0x005F5838) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_14__TX_DCOC_RES_I_ODD_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_14__TX_DCOC_RES_Q_ODD_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_14__TX_DCOC_RES_I_EVEN_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_14__TX_DCOC_RES_Q_EVEN_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_14__TX_DCOC_RES_I_ODD_14___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_14__TX_DCOC_RES_I_ODD_14___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_14__TX_DCOC_RES_Q_ODD_14___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_14__TX_DCOC_RES_Q_ODD_14___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_14__TX_DCOC_RES_I_EVEN_14___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_14__TX_DCOC_RES_I_EVEN_14___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_14__TX_DCOC_RES_Q_EVEN_14___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_14__TX_DCOC_RES_Q_EVEN_14___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_14___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_14___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_15 (0x005F583C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_15__TX_DCOC_RES_I_ODD_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_15__TX_DCOC_RES_Q_ODD_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_15__TX_DCOC_RES_I_EVEN_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_15__TX_DCOC_RES_Q_EVEN_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_15__TX_DCOC_RES_I_ODD_15___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_15__TX_DCOC_RES_I_ODD_15___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_15__TX_DCOC_RES_Q_ODD_15___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_15__TX_DCOC_RES_Q_ODD_15___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_15__TX_DCOC_RES_I_EVEN_15___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_15__TX_DCOC_RES_I_EVEN_15___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_15__TX_DCOC_RES_Q_EVEN_15___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_15__TX_DCOC_RES_Q_EVEN_15___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_15___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_15___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_16 (0x005F5840) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_16___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_16__TX_DCOC_RES_I_ODD_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_16__TX_DCOC_RES_Q_ODD_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_16__TX_DCOC_RES_I_EVEN_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_16__TX_DCOC_RES_Q_EVEN_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_16__TX_DCOC_RES_I_ODD_16___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_16__TX_DCOC_RES_I_ODD_16___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_16__TX_DCOC_RES_Q_ODD_16___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_16__TX_DCOC_RES_Q_ODD_16___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_16__TX_DCOC_RES_I_EVEN_16___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_16__TX_DCOC_RES_I_EVEN_16___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_16__TX_DCOC_RES_Q_EVEN_16___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_16__TX_DCOC_RES_Q_EVEN_16___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_16___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_16___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_17 (0x005F5844) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_17___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_17__TX_DCOC_RES_I_ODD_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_17__TX_DCOC_RES_Q_ODD_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_17__TX_DCOC_RES_I_EVEN_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_17__TX_DCOC_RES_Q_EVEN_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_17__TX_DCOC_RES_I_ODD_17___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_17__TX_DCOC_RES_I_ODD_17___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_17__TX_DCOC_RES_Q_ODD_17___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_17__TX_DCOC_RES_Q_ODD_17___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_17__TX_DCOC_RES_I_EVEN_17___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_17__TX_DCOC_RES_I_EVEN_17___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_17__TX_DCOC_RES_Q_EVEN_17___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_17__TX_DCOC_RES_Q_EVEN_17___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_17___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_17___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_18 (0x005F5848) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_18___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_18__TX_DCOC_RES_I_ODD_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_18__TX_DCOC_RES_Q_ODD_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_18__TX_DCOC_RES_I_EVEN_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_18__TX_DCOC_RES_Q_EVEN_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_18__TX_DCOC_RES_I_ODD_18___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_18__TX_DCOC_RES_I_ODD_18___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_18__TX_DCOC_RES_Q_ODD_18___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_18__TX_DCOC_RES_Q_ODD_18___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_18__TX_DCOC_RES_I_EVEN_18___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_18__TX_DCOC_RES_I_EVEN_18___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_18__TX_DCOC_RES_Q_EVEN_18___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_18__TX_DCOC_RES_Q_EVEN_18___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_18___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_18___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_19 (0x005F584C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_19___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_19__TX_DCOC_RES_I_ODD_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_19__TX_DCOC_RES_Q_ODD_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_19__TX_DCOC_RES_I_EVEN_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_19__TX_DCOC_RES_Q_EVEN_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_19__TX_DCOC_RES_I_ODD_19___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_19__TX_DCOC_RES_I_ODD_19___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_19__TX_DCOC_RES_Q_ODD_19___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_19__TX_DCOC_RES_Q_ODD_19___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_19__TX_DCOC_RES_I_EVEN_19___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_19__TX_DCOC_RES_I_EVEN_19___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_19__TX_DCOC_RES_Q_EVEN_19___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_19__TX_DCOC_RES_Q_EVEN_19___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_19___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_19___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_20 (0x005F5850) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_20___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_20__TX_DCOC_RES_I_ODD_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_20__TX_DCOC_RES_Q_ODD_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_20__TX_DCOC_RES_I_EVEN_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_20__TX_DCOC_RES_Q_EVEN_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_20__TX_DCOC_RES_I_ODD_20___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_20__TX_DCOC_RES_I_ODD_20___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_20__TX_DCOC_RES_Q_ODD_20___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_20__TX_DCOC_RES_Q_ODD_20___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_20__TX_DCOC_RES_I_EVEN_20___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_20__TX_DCOC_RES_I_EVEN_20___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_20__TX_DCOC_RES_Q_EVEN_20___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_20__TX_DCOC_RES_Q_EVEN_20___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_20___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_20___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_21 (0x005F5854) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_21___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_21__TX_DCOC_RES_I_ODD_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_21__TX_DCOC_RES_Q_ODD_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_21__TX_DCOC_RES_I_EVEN_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_21__TX_DCOC_RES_Q_EVEN_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_21__TX_DCOC_RES_I_ODD_21___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_21__TX_DCOC_RES_I_ODD_21___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_21__TX_DCOC_RES_Q_ODD_21___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_21__TX_DCOC_RES_Q_ODD_21___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_21__TX_DCOC_RES_I_EVEN_21___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_21__TX_DCOC_RES_I_EVEN_21___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_21__TX_DCOC_RES_Q_EVEN_21___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_21__TX_DCOC_RES_Q_EVEN_21___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_21___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_21___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_22 (0x005F5858) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_22___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_22__TX_DCOC_RES_I_ODD_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_22__TX_DCOC_RES_Q_ODD_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_22__TX_DCOC_RES_I_EVEN_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_22__TX_DCOC_RES_Q_EVEN_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_22__TX_DCOC_RES_I_ODD_22___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_22__TX_DCOC_RES_I_ODD_22___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_22__TX_DCOC_RES_Q_ODD_22___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_22__TX_DCOC_RES_Q_ODD_22___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_22__TX_DCOC_RES_I_EVEN_22___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_22__TX_DCOC_RES_I_EVEN_22___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_22__TX_DCOC_RES_Q_EVEN_22___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_22__TX_DCOC_RES_Q_EVEN_22___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_22___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_22___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_23 (0x005F585C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_23___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_23__TX_DCOC_RES_I_ODD_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_23__TX_DCOC_RES_Q_ODD_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_23__TX_DCOC_RES_I_EVEN_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_23__TX_DCOC_RES_Q_EVEN_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_23__TX_DCOC_RES_I_ODD_23___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_23__TX_DCOC_RES_I_ODD_23___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_23__TX_DCOC_RES_Q_ODD_23___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_23__TX_DCOC_RES_Q_ODD_23___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_23__TX_DCOC_RES_I_EVEN_23___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_23__TX_DCOC_RES_I_EVEN_23___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_23__TX_DCOC_RES_Q_EVEN_23___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_23__TX_DCOC_RES_Q_EVEN_23___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_23___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_23___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_24 (0x005F5860) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_24___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_24__TX_DCOC_RES_I_ODD_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_24__TX_DCOC_RES_Q_ODD_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_24__TX_DCOC_RES_I_EVEN_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_24__TX_DCOC_RES_Q_EVEN_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_24__TX_DCOC_RES_I_ODD_24___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_24__TX_DCOC_RES_I_ODD_24___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_24__TX_DCOC_RES_Q_ODD_24___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_24__TX_DCOC_RES_Q_ODD_24___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_24__TX_DCOC_RES_I_EVEN_24___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_24__TX_DCOC_RES_I_EVEN_24___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_24__TX_DCOC_RES_Q_EVEN_24___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_24__TX_DCOC_RES_Q_EVEN_24___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_24___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_24___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_25 (0x005F5864) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_25___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_25__TX_DCOC_RES_I_ODD_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_25__TX_DCOC_RES_Q_ODD_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_25__TX_DCOC_RES_I_EVEN_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_25__TX_DCOC_RES_Q_EVEN_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_25__TX_DCOC_RES_I_ODD_25___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_25__TX_DCOC_RES_I_ODD_25___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_25__TX_DCOC_RES_Q_ODD_25___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_25__TX_DCOC_RES_Q_ODD_25___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_25__TX_DCOC_RES_I_EVEN_25___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_25__TX_DCOC_RES_I_EVEN_25___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_25__TX_DCOC_RES_Q_EVEN_25___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_25__TX_DCOC_RES_Q_EVEN_25___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_25___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_25___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_26 (0x005F5868) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_26___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_26__TX_DCOC_RES_I_ODD_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_26__TX_DCOC_RES_Q_ODD_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_26__TX_DCOC_RES_I_EVEN_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_26__TX_DCOC_RES_Q_EVEN_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_26__TX_DCOC_RES_I_ODD_26___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_26__TX_DCOC_RES_I_ODD_26___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_26__TX_DCOC_RES_Q_ODD_26___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_26__TX_DCOC_RES_Q_ODD_26___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_26__TX_DCOC_RES_I_EVEN_26___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_26__TX_DCOC_RES_I_EVEN_26___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_26__TX_DCOC_RES_Q_EVEN_26___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_26__TX_DCOC_RES_Q_EVEN_26___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_26___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_26___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_27 (0x005F586C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_27___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_27__TX_DCOC_RES_I_ODD_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_27__TX_DCOC_RES_Q_ODD_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_27__TX_DCOC_RES_I_EVEN_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_27__TX_DCOC_RES_Q_EVEN_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_27__TX_DCOC_RES_I_ODD_27___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_27__TX_DCOC_RES_I_ODD_27___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_27__TX_DCOC_RES_Q_ODD_27___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_27__TX_DCOC_RES_Q_ODD_27___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_27__TX_DCOC_RES_I_EVEN_27___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_27__TX_DCOC_RES_I_EVEN_27___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_27__TX_DCOC_RES_Q_EVEN_27___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_27__TX_DCOC_RES_Q_EVEN_27___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_27___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_27___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_28 (0x005F5870) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_28___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_28__TX_DCOC_RES_I_ODD_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_28__TX_DCOC_RES_Q_ODD_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_28__TX_DCOC_RES_I_EVEN_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_28__TX_DCOC_RES_Q_EVEN_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_28__TX_DCOC_RES_I_ODD_28___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_28__TX_DCOC_RES_I_ODD_28___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_28__TX_DCOC_RES_Q_ODD_28___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_28__TX_DCOC_RES_Q_ODD_28___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_28__TX_DCOC_RES_I_EVEN_28___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_28__TX_DCOC_RES_I_EVEN_28___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_28__TX_DCOC_RES_Q_EVEN_28___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_28__TX_DCOC_RES_Q_EVEN_28___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_28___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_28___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_29 (0x005F5874) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_29___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_29__TX_DCOC_RES_I_ODD_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_29__TX_DCOC_RES_Q_ODD_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_29__TX_DCOC_RES_I_EVEN_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_29__TX_DCOC_RES_Q_EVEN_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_29__TX_DCOC_RES_I_ODD_29___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_29__TX_DCOC_RES_I_ODD_29___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_29__TX_DCOC_RES_Q_ODD_29___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_29__TX_DCOC_RES_Q_ODD_29___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_29__TX_DCOC_RES_I_EVEN_29___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_29__TX_DCOC_RES_I_EVEN_29___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_29__TX_DCOC_RES_Q_EVEN_29___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_29__TX_DCOC_RES_Q_EVEN_29___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_29___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_29___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_30 (0x005F5878) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_30___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_30__TX_DCOC_RES_I_ODD_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_30__TX_DCOC_RES_Q_ODD_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_30__TX_DCOC_RES_I_EVEN_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_30__TX_DCOC_RES_Q_EVEN_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_30__TX_DCOC_RES_I_ODD_30___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_30__TX_DCOC_RES_I_ODD_30___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_30__TX_DCOC_RES_Q_ODD_30___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_30__TX_DCOC_RES_Q_ODD_30___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_30__TX_DCOC_RES_I_EVEN_30___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_30__TX_DCOC_RES_I_EVEN_30___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_30__TX_DCOC_RES_Q_EVEN_30___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_30__TX_DCOC_RES_Q_EVEN_30___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_30___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_30___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_31 (0x005F587C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_31___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_31__TX_DCOC_RES_I_ODD_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_31__TX_DCOC_RES_Q_ODD_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_31__TX_DCOC_RES_I_EVEN_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_31__TX_DCOC_RES_Q_EVEN_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_31__TX_DCOC_RES_I_ODD_31___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_31__TX_DCOC_RES_I_ODD_31___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_31__TX_DCOC_RES_Q_ODD_31___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_31__TX_DCOC_RES_Q_ODD_31___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_31__TX_DCOC_RES_I_EVEN_31___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_31__TX_DCOC_RES_I_EVEN_31___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_31__TX_DCOC_RES_Q_EVEN_31___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_31__TX_DCOC_RES_Q_EVEN_31___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_31___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_31___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_32 (0x005F5880) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_32___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_32___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_32__TX_DCOC_RES_I_ODD_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_32__TX_DCOC_RES_Q_ODD_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_32__TX_DCOC_RES_I_EVEN_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_32__TX_DCOC_RES_Q_EVEN_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_32__TX_DCOC_RES_I_ODD_32___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_32__TX_DCOC_RES_I_ODD_32___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_32__TX_DCOC_RES_Q_ODD_32___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_32__TX_DCOC_RES_Q_ODD_32___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_32__TX_DCOC_RES_I_EVEN_32___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_32__TX_DCOC_RES_I_EVEN_32___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_32__TX_DCOC_RES_Q_EVEN_32___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_32__TX_DCOC_RES_Q_EVEN_32___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_32___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_32___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_33 (0x005F5884) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_33___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_33___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_33__TX_DCOC_RES_I_ODD_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_33__TX_DCOC_RES_Q_ODD_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_33__TX_DCOC_RES_I_EVEN_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_33__TX_DCOC_RES_Q_EVEN_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_33__TX_DCOC_RES_I_ODD_33___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_33__TX_DCOC_RES_I_ODD_33___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_33__TX_DCOC_RES_Q_ODD_33___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_33__TX_DCOC_RES_Q_ODD_33___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_33__TX_DCOC_RES_I_EVEN_33___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_33__TX_DCOC_RES_I_EVEN_33___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_33__TX_DCOC_RES_Q_EVEN_33___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_33__TX_DCOC_RES_Q_EVEN_33___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_33___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_33___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_34 (0x005F5888) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_34___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_34___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_34__TX_DCOC_RES_I_ODD_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_34__TX_DCOC_RES_Q_ODD_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_34__TX_DCOC_RES_I_EVEN_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_34__TX_DCOC_RES_Q_EVEN_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_34__TX_DCOC_RES_I_ODD_34___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_34__TX_DCOC_RES_I_ODD_34___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_34__TX_DCOC_RES_Q_ODD_34___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_34__TX_DCOC_RES_Q_ODD_34___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_34__TX_DCOC_RES_I_EVEN_34___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_34__TX_DCOC_RES_I_EVEN_34___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_34__TX_DCOC_RES_Q_EVEN_34___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_34__TX_DCOC_RES_Q_EVEN_34___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_34___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_34___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_35 (0x005F588C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_35___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_35___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_35__TX_DCOC_RES_I_ODD_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_35__TX_DCOC_RES_Q_ODD_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_35__TX_DCOC_RES_I_EVEN_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_35__TX_DCOC_RES_Q_EVEN_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_35__TX_DCOC_RES_I_ODD_35___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_35__TX_DCOC_RES_I_ODD_35___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_35__TX_DCOC_RES_Q_ODD_35___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_35__TX_DCOC_RES_Q_ODD_35___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_35__TX_DCOC_RES_I_EVEN_35___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_35__TX_DCOC_RES_I_EVEN_35___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_35__TX_DCOC_RES_Q_EVEN_35___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_35__TX_DCOC_RES_Q_EVEN_35___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_35___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_35___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_36 (0x005F5890) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_36___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_36___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_36__TX_DCOC_RES_I_ODD_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_36__TX_DCOC_RES_Q_ODD_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_36__TX_DCOC_RES_I_EVEN_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_36__TX_DCOC_RES_Q_EVEN_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_36__TX_DCOC_RES_I_ODD_36___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_36__TX_DCOC_RES_I_ODD_36___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_36__TX_DCOC_RES_Q_ODD_36___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_36__TX_DCOC_RES_Q_ODD_36___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_36__TX_DCOC_RES_I_EVEN_36___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_36__TX_DCOC_RES_I_EVEN_36___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_36__TX_DCOC_RES_Q_EVEN_36___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_36__TX_DCOC_RES_Q_EVEN_36___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_36___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_36___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_37 (0x005F5894) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_37___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_37___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_37__TX_DCOC_RES_I_ODD_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_37__TX_DCOC_RES_Q_ODD_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_37__TX_DCOC_RES_I_EVEN_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_37__TX_DCOC_RES_Q_EVEN_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_37__TX_DCOC_RES_I_ODD_37___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_37__TX_DCOC_RES_I_ODD_37___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_37__TX_DCOC_RES_Q_ODD_37___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_37__TX_DCOC_RES_Q_ODD_37___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_37__TX_DCOC_RES_I_EVEN_37___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_37__TX_DCOC_RES_I_EVEN_37___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_37__TX_DCOC_RES_Q_EVEN_37___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_37__TX_DCOC_RES_Q_EVEN_37___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_37___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_37___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_38 (0x005F5898) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_38___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_38___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_38__TX_DCOC_RES_I_ODD_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_38__TX_DCOC_RES_Q_ODD_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_38__TX_DCOC_RES_I_EVEN_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_38__TX_DCOC_RES_Q_EVEN_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_38__TX_DCOC_RES_I_ODD_38___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_38__TX_DCOC_RES_I_ODD_38___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_38__TX_DCOC_RES_Q_ODD_38___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_38__TX_DCOC_RES_Q_ODD_38___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_38__TX_DCOC_RES_I_EVEN_38___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_38__TX_DCOC_RES_I_EVEN_38___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_38__TX_DCOC_RES_Q_EVEN_38___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_38__TX_DCOC_RES_Q_EVEN_38___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_38___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_38___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_39 (0x005F589C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_39___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_39___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_39__TX_DCOC_RES_I_ODD_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_39__TX_DCOC_RES_Q_ODD_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_39__TX_DCOC_RES_I_EVEN_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_39__TX_DCOC_RES_Q_EVEN_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_39__TX_DCOC_RES_I_ODD_39___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_39__TX_DCOC_RES_I_ODD_39___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_39__TX_DCOC_RES_Q_ODD_39___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_39__TX_DCOC_RES_Q_ODD_39___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_39__TX_DCOC_RES_I_EVEN_39___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_39__TX_DCOC_RES_I_EVEN_39___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_39__TX_DCOC_RES_Q_EVEN_39___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_39__TX_DCOC_RES_Q_EVEN_39___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_39___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_39___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_40 (0x005F58A0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_40___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_40___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_40__TX_DCOC_RES_I_ODD_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_40__TX_DCOC_RES_Q_ODD_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_40__TX_DCOC_RES_I_EVEN_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_40__TX_DCOC_RES_Q_EVEN_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_40__TX_DCOC_RES_I_ODD_40___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_40__TX_DCOC_RES_I_ODD_40___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_40__TX_DCOC_RES_Q_ODD_40___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_40__TX_DCOC_RES_Q_ODD_40___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_40__TX_DCOC_RES_I_EVEN_40___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_40__TX_DCOC_RES_I_EVEN_40___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_40__TX_DCOC_RES_Q_EVEN_40___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_40__TX_DCOC_RES_Q_EVEN_40___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_40___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_40___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_41 (0x005F58A4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_41___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_41___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_41__TX_DCOC_RES_I_ODD_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_41__TX_DCOC_RES_Q_ODD_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_41__TX_DCOC_RES_I_EVEN_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_41__TX_DCOC_RES_Q_EVEN_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_41__TX_DCOC_RES_I_ODD_41___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_41__TX_DCOC_RES_I_ODD_41___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_41__TX_DCOC_RES_Q_ODD_41___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_41__TX_DCOC_RES_Q_ODD_41___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_41__TX_DCOC_RES_I_EVEN_41___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_41__TX_DCOC_RES_I_EVEN_41___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_41__TX_DCOC_RES_Q_EVEN_41___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_41__TX_DCOC_RES_Q_EVEN_41___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_41___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_41___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_42 (0x005F58A8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_42___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_42___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_42__TX_DCOC_RES_I_ODD_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_42__TX_DCOC_RES_Q_ODD_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_42__TX_DCOC_RES_I_EVEN_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_42__TX_DCOC_RES_Q_EVEN_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_42__TX_DCOC_RES_I_ODD_42___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_42__TX_DCOC_RES_I_ODD_42___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_42__TX_DCOC_RES_Q_ODD_42___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_42__TX_DCOC_RES_Q_ODD_42___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_42__TX_DCOC_RES_I_EVEN_42___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_42__TX_DCOC_RES_I_EVEN_42___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_42__TX_DCOC_RES_Q_EVEN_42___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_42__TX_DCOC_RES_Q_EVEN_42___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_42___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_42___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_43 (0x005F58AC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_43___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_43___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_43__TX_DCOC_RES_I_ODD_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_43__TX_DCOC_RES_Q_ODD_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_43__TX_DCOC_RES_I_EVEN_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_43__TX_DCOC_RES_Q_EVEN_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_43__TX_DCOC_RES_I_ODD_43___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_43__TX_DCOC_RES_I_ODD_43___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_43__TX_DCOC_RES_Q_ODD_43___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_43__TX_DCOC_RES_Q_ODD_43___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_43__TX_DCOC_RES_I_EVEN_43___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_43__TX_DCOC_RES_I_EVEN_43___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_43__TX_DCOC_RES_Q_EVEN_43___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_43__TX_DCOC_RES_Q_EVEN_43___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_43___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_43___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_44 (0x005F58B0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_44___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_44___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_44__TX_DCOC_RES_I_ODD_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_44__TX_DCOC_RES_Q_ODD_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_44__TX_DCOC_RES_I_EVEN_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_44__TX_DCOC_RES_Q_EVEN_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_44__TX_DCOC_RES_I_ODD_44___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_44__TX_DCOC_RES_I_ODD_44___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_44__TX_DCOC_RES_Q_ODD_44___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_44__TX_DCOC_RES_Q_ODD_44___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_44__TX_DCOC_RES_I_EVEN_44___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_44__TX_DCOC_RES_I_EVEN_44___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_44__TX_DCOC_RES_Q_EVEN_44___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_44__TX_DCOC_RES_Q_EVEN_44___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_44___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_44___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_45 (0x005F58B4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_45___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_45___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_45__TX_DCOC_RES_I_ODD_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_45__TX_DCOC_RES_Q_ODD_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_45__TX_DCOC_RES_I_EVEN_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_45__TX_DCOC_RES_Q_EVEN_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_45__TX_DCOC_RES_I_ODD_45___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_45__TX_DCOC_RES_I_ODD_45___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_45__TX_DCOC_RES_Q_ODD_45___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_45__TX_DCOC_RES_Q_ODD_45___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_45__TX_DCOC_RES_I_EVEN_45___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_45__TX_DCOC_RES_I_EVEN_45___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_45__TX_DCOC_RES_Q_EVEN_45___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_45__TX_DCOC_RES_Q_EVEN_45___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_45___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_45___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_46 (0x005F58B8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_46___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_46___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_46__TX_DCOC_RES_I_ODD_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_46__TX_DCOC_RES_Q_ODD_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_46__TX_DCOC_RES_I_EVEN_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_46__TX_DCOC_RES_Q_EVEN_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_46__TX_DCOC_RES_I_ODD_46___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_46__TX_DCOC_RES_I_ODD_46___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_46__TX_DCOC_RES_Q_ODD_46___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_46__TX_DCOC_RES_Q_ODD_46___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_46__TX_DCOC_RES_I_EVEN_46___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_46__TX_DCOC_RES_I_EVEN_46___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_46__TX_DCOC_RES_Q_EVEN_46___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_46__TX_DCOC_RES_Q_EVEN_46___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_46___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_46___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_47 (0x005F58BC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_47___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_47___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_47__TX_DCOC_RES_I_ODD_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_47__TX_DCOC_RES_Q_ODD_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_47__TX_DCOC_RES_I_EVEN_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_47__TX_DCOC_RES_Q_EVEN_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_47__TX_DCOC_RES_I_ODD_47___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_47__TX_DCOC_RES_I_ODD_47___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_47__TX_DCOC_RES_Q_ODD_47___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_47__TX_DCOC_RES_Q_ODD_47___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_47__TX_DCOC_RES_I_EVEN_47___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_47__TX_DCOC_RES_I_EVEN_47___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_47__TX_DCOC_RES_Q_EVEN_47___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_47__TX_DCOC_RES_Q_EVEN_47___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_47___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_47___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_48 (0x005F58C0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_48___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_48___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_48__TX_DCOC_RES_I_ODD_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_48__TX_DCOC_RES_Q_ODD_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_48__TX_DCOC_RES_I_EVEN_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_48__TX_DCOC_RES_Q_EVEN_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_48__TX_DCOC_RES_I_ODD_48___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_48__TX_DCOC_RES_I_ODD_48___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_48__TX_DCOC_RES_Q_ODD_48___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_48__TX_DCOC_RES_Q_ODD_48___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_48__TX_DCOC_RES_I_EVEN_48___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_48__TX_DCOC_RES_I_EVEN_48___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_48__TX_DCOC_RES_Q_EVEN_48___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_48__TX_DCOC_RES_Q_EVEN_48___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_48___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_48___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_49 (0x005F58C4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_49___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_49___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_49__TX_DCOC_RES_I_ODD_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_49__TX_DCOC_RES_Q_ODD_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_49__TX_DCOC_RES_I_EVEN_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_49__TX_DCOC_RES_Q_EVEN_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_49__TX_DCOC_RES_I_ODD_49___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_49__TX_DCOC_RES_I_ODD_49___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_49__TX_DCOC_RES_Q_ODD_49___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_49__TX_DCOC_RES_Q_ODD_49___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_49__TX_DCOC_RES_I_EVEN_49___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_49__TX_DCOC_RES_I_EVEN_49___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_49__TX_DCOC_RES_Q_EVEN_49___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_49__TX_DCOC_RES_Q_EVEN_49___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_49___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_49___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_50 (0x005F58C8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_50___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_50___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_50__TX_DCOC_RES_I_ODD_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_50__TX_DCOC_RES_Q_ODD_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_50__TX_DCOC_RES_I_EVEN_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_50__TX_DCOC_RES_Q_EVEN_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_50__TX_DCOC_RES_I_ODD_50___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_50__TX_DCOC_RES_I_ODD_50___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_50__TX_DCOC_RES_Q_ODD_50___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_50__TX_DCOC_RES_Q_ODD_50___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_50__TX_DCOC_RES_I_EVEN_50___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_50__TX_DCOC_RES_I_EVEN_50___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_50__TX_DCOC_RES_Q_EVEN_50___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_50__TX_DCOC_RES_Q_EVEN_50___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_50___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_50___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_51 (0x005F58CC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_51___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_51___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_51__TX_DCOC_RES_I_ODD_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_51__TX_DCOC_RES_Q_ODD_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_51__TX_DCOC_RES_I_EVEN_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_51__TX_DCOC_RES_Q_EVEN_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_51__TX_DCOC_RES_I_ODD_51___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_51__TX_DCOC_RES_I_ODD_51___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_51__TX_DCOC_RES_Q_ODD_51___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_51__TX_DCOC_RES_Q_ODD_51___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_51__TX_DCOC_RES_I_EVEN_51___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_51__TX_DCOC_RES_I_EVEN_51___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_51__TX_DCOC_RES_Q_EVEN_51___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_51__TX_DCOC_RES_Q_EVEN_51___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_51___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_51___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_52 (0x005F58D0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_52___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_52___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_52__TX_DCOC_RES_I_ODD_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_52__TX_DCOC_RES_Q_ODD_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_52__TX_DCOC_RES_I_EVEN_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_52__TX_DCOC_RES_Q_EVEN_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_52__TX_DCOC_RES_I_ODD_52___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_52__TX_DCOC_RES_I_ODD_52___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_52__TX_DCOC_RES_Q_ODD_52___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_52__TX_DCOC_RES_Q_ODD_52___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_52__TX_DCOC_RES_I_EVEN_52___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_52__TX_DCOC_RES_I_EVEN_52___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_52__TX_DCOC_RES_Q_EVEN_52___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_52__TX_DCOC_RES_Q_EVEN_52___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_52___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_52___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_53 (0x005F58D4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_53___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_53___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_53__TX_DCOC_RES_I_ODD_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_53__TX_DCOC_RES_Q_ODD_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_53__TX_DCOC_RES_I_EVEN_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_53__TX_DCOC_RES_Q_EVEN_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_53__TX_DCOC_RES_I_ODD_53___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_53__TX_DCOC_RES_I_ODD_53___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_53__TX_DCOC_RES_Q_ODD_53___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_53__TX_DCOC_RES_Q_ODD_53___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_53__TX_DCOC_RES_I_EVEN_53___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_53__TX_DCOC_RES_I_EVEN_53___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_53__TX_DCOC_RES_Q_EVEN_53___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_53__TX_DCOC_RES_Q_EVEN_53___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_53___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_53___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_54 (0x005F58D8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_54___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_54___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_54__TX_DCOC_RES_I_ODD_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_54__TX_DCOC_RES_Q_ODD_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_54__TX_DCOC_RES_I_EVEN_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_54__TX_DCOC_RES_Q_EVEN_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_54__TX_DCOC_RES_I_ODD_54___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_54__TX_DCOC_RES_I_ODD_54___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_54__TX_DCOC_RES_Q_ODD_54___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_54__TX_DCOC_RES_Q_ODD_54___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_54__TX_DCOC_RES_I_EVEN_54___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_54__TX_DCOC_RES_I_EVEN_54___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_54__TX_DCOC_RES_Q_EVEN_54___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_54__TX_DCOC_RES_Q_EVEN_54___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_54___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_54___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_55 (0x005F58DC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_55___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_55___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_55__TX_DCOC_RES_I_ODD_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_55__TX_DCOC_RES_Q_ODD_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_55__TX_DCOC_RES_I_EVEN_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_55__TX_DCOC_RES_Q_EVEN_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_55__TX_DCOC_RES_I_ODD_55___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_55__TX_DCOC_RES_I_ODD_55___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_55__TX_DCOC_RES_Q_ODD_55___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_55__TX_DCOC_RES_Q_ODD_55___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_55__TX_DCOC_RES_I_EVEN_55___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_55__TX_DCOC_RES_I_EVEN_55___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_55__TX_DCOC_RES_Q_EVEN_55___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_55__TX_DCOC_RES_Q_EVEN_55___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_55___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_55___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_56 (0x005F58E0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_56___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_56___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_56__TX_DCOC_RES_I_ODD_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_56__TX_DCOC_RES_Q_ODD_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_56__TX_DCOC_RES_I_EVEN_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_56__TX_DCOC_RES_Q_EVEN_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_56__TX_DCOC_RES_I_ODD_56___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_56__TX_DCOC_RES_I_ODD_56___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_56__TX_DCOC_RES_Q_ODD_56___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_56__TX_DCOC_RES_Q_ODD_56___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_56__TX_DCOC_RES_I_EVEN_56___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_56__TX_DCOC_RES_I_EVEN_56___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_56__TX_DCOC_RES_Q_EVEN_56___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_56__TX_DCOC_RES_Q_EVEN_56___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_56___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_56___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_57 (0x005F58E4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_57___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_57___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_57__TX_DCOC_RES_I_ODD_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_57__TX_DCOC_RES_Q_ODD_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_57__TX_DCOC_RES_I_EVEN_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_57__TX_DCOC_RES_Q_EVEN_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_57__TX_DCOC_RES_I_ODD_57___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_57__TX_DCOC_RES_I_ODD_57___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_57__TX_DCOC_RES_Q_ODD_57___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_57__TX_DCOC_RES_Q_ODD_57___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_57__TX_DCOC_RES_I_EVEN_57___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_57__TX_DCOC_RES_I_EVEN_57___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_57__TX_DCOC_RES_Q_EVEN_57___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_57__TX_DCOC_RES_Q_EVEN_57___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_57___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_57___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_58 (0x005F58E8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_58___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_58___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_58__TX_DCOC_RES_I_ODD_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_58__TX_DCOC_RES_Q_ODD_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_58__TX_DCOC_RES_I_EVEN_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_58__TX_DCOC_RES_Q_EVEN_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_58__TX_DCOC_RES_I_ODD_58___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_58__TX_DCOC_RES_I_ODD_58___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_58__TX_DCOC_RES_Q_ODD_58___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_58__TX_DCOC_RES_Q_ODD_58___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_58__TX_DCOC_RES_I_EVEN_58___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_58__TX_DCOC_RES_I_EVEN_58___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_58__TX_DCOC_RES_Q_EVEN_58___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_58__TX_DCOC_RES_Q_EVEN_58___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_58___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_58___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_59 (0x005F58EC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_59___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_59___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_59__TX_DCOC_RES_I_ODD_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_59__TX_DCOC_RES_Q_ODD_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_59__TX_DCOC_RES_I_EVEN_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_59__TX_DCOC_RES_Q_EVEN_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_59__TX_DCOC_RES_I_ODD_59___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_59__TX_DCOC_RES_I_ODD_59___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_59__TX_DCOC_RES_Q_ODD_59___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_59__TX_DCOC_RES_Q_ODD_59___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_59__TX_DCOC_RES_I_EVEN_59___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_59__TX_DCOC_RES_I_EVEN_59___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_59__TX_DCOC_RES_Q_EVEN_59___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_59__TX_DCOC_RES_Q_EVEN_59___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_59___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_59___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_60 (0x005F58F0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_60___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_60___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_60__TX_DCOC_RES_I_ODD_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_60__TX_DCOC_RES_Q_ODD_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_60__TX_DCOC_RES_I_EVEN_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_60__TX_DCOC_RES_Q_EVEN_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_60__TX_DCOC_RES_I_ODD_60___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_60__TX_DCOC_RES_I_ODD_60___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_60__TX_DCOC_RES_Q_ODD_60___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_60__TX_DCOC_RES_Q_ODD_60___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_60__TX_DCOC_RES_I_EVEN_60___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_60__TX_DCOC_RES_I_EVEN_60___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_60__TX_DCOC_RES_Q_EVEN_60___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_60__TX_DCOC_RES_Q_EVEN_60___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_60___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_60___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_61 (0x005F58F4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_61___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_61___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_61__TX_DCOC_RES_I_ODD_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_61__TX_DCOC_RES_Q_ODD_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_61__TX_DCOC_RES_I_EVEN_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_61__TX_DCOC_RES_Q_EVEN_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_61__TX_DCOC_RES_I_ODD_61___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_61__TX_DCOC_RES_I_ODD_61___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_61__TX_DCOC_RES_Q_ODD_61___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_61__TX_DCOC_RES_Q_ODD_61___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_61__TX_DCOC_RES_I_EVEN_61___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_61__TX_DCOC_RES_I_EVEN_61___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_61__TX_DCOC_RES_Q_EVEN_61___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_61__TX_DCOC_RES_Q_EVEN_61___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_61___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_61___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_62 (0x005F58F8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_62___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_62___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_62__TX_DCOC_RES_I_ODD_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_62__TX_DCOC_RES_Q_ODD_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_62__TX_DCOC_RES_I_EVEN_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_62__TX_DCOC_RES_Q_EVEN_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_62__TX_DCOC_RES_I_ODD_62___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_62__TX_DCOC_RES_I_ODD_62___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_62__TX_DCOC_RES_Q_ODD_62___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_62__TX_DCOC_RES_Q_ODD_62___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_62__TX_DCOC_RES_I_EVEN_62___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_62__TX_DCOC_RES_I_EVEN_62___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_62__TX_DCOC_RES_Q_EVEN_62___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_62__TX_DCOC_RES_Q_EVEN_62___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_62___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_62___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_63 (0x005F58FC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_63___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_63___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_63__TX_DCOC_RES_I_ODD_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_63__TX_DCOC_RES_Q_ODD_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_63__TX_DCOC_RES_I_EVEN_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_63__TX_DCOC_RES_Q_EVEN_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_63__TX_DCOC_RES_I_ODD_63___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_63__TX_DCOC_RES_I_ODD_63___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_63__TX_DCOC_RES_Q_ODD_63___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_63__TX_DCOC_RES_Q_ODD_63___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_63__TX_DCOC_RES_I_EVEN_63___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_63__TX_DCOC_RES_I_EVEN_63___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_63__TX_DCOC_RES_Q_EVEN_63___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_63__TX_DCOC_RES_Q_EVEN_63___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_63___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_63___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_64 (0x005F5900) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_64___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_64___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_64__TX_DCOC_RES_I_ODD_64___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_64__TX_DCOC_RES_Q_ODD_64___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_64__TX_DCOC_RES_I_EVEN_64___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_64__TX_DCOC_RES_Q_EVEN_64___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_64__TX_DCOC_RES_I_ODD_64___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_64__TX_DCOC_RES_I_ODD_64___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_64__TX_DCOC_RES_Q_ODD_64___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_64__TX_DCOC_RES_Q_ODD_64___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_64__TX_DCOC_RES_I_EVEN_64___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_64__TX_DCOC_RES_I_EVEN_64___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_64__TX_DCOC_RES_Q_EVEN_64___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_64__TX_DCOC_RES_Q_EVEN_64___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_64___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_64___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_65 (0x005F5904) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_65___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_65___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_65__TX_DCOC_RES_I_ODD_65___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_65__TX_DCOC_RES_Q_ODD_65___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_65__TX_DCOC_RES_I_EVEN_65___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_65__TX_DCOC_RES_Q_EVEN_65___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_65__TX_DCOC_RES_I_ODD_65___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_65__TX_DCOC_RES_I_ODD_65___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_65__TX_DCOC_RES_Q_ODD_65___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_65__TX_DCOC_RES_Q_ODD_65___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_65__TX_DCOC_RES_I_EVEN_65___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_65__TX_DCOC_RES_I_EVEN_65___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_65__TX_DCOC_RES_Q_EVEN_65___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_65__TX_DCOC_RES_Q_EVEN_65___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_65___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_65___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_66 (0x005F5908) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_66___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_66___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_66__TX_DCOC_RES_I_ODD_66___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_66__TX_DCOC_RES_Q_ODD_66___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_66__TX_DCOC_RES_I_EVEN_66___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_66__TX_DCOC_RES_Q_EVEN_66___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_66__TX_DCOC_RES_I_ODD_66___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_66__TX_DCOC_RES_I_ODD_66___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_66__TX_DCOC_RES_Q_ODD_66___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_66__TX_DCOC_RES_Q_ODD_66___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_66__TX_DCOC_RES_I_EVEN_66___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_66__TX_DCOC_RES_I_EVEN_66___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_66__TX_DCOC_RES_Q_EVEN_66___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_66__TX_DCOC_RES_Q_EVEN_66___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_66___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_66___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_67 (0x005F590C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_67___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_67___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_67__TX_DCOC_RES_I_ODD_67___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_67__TX_DCOC_RES_Q_ODD_67___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_67__TX_DCOC_RES_I_EVEN_67___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_67__TX_DCOC_RES_Q_EVEN_67___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_67__TX_DCOC_RES_I_ODD_67___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_67__TX_DCOC_RES_I_ODD_67___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_67__TX_DCOC_RES_Q_ODD_67___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_67__TX_DCOC_RES_Q_ODD_67___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_67__TX_DCOC_RES_I_EVEN_67___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_67__TX_DCOC_RES_I_EVEN_67___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_67__TX_DCOC_RES_Q_EVEN_67___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_67__TX_DCOC_RES_Q_EVEN_67___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_67___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_67___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_68 (0x005F5910) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_68___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_68___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_68__TX_DCOC_RES_I_ODD_68___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_68__TX_DCOC_RES_Q_ODD_68___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_68__TX_DCOC_RES_I_EVEN_68___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_68__TX_DCOC_RES_Q_EVEN_68___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_68__TX_DCOC_RES_I_ODD_68___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_68__TX_DCOC_RES_I_ODD_68___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_68__TX_DCOC_RES_Q_ODD_68___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_68__TX_DCOC_RES_Q_ODD_68___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_68__TX_DCOC_RES_I_EVEN_68___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_68__TX_DCOC_RES_I_EVEN_68___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_68__TX_DCOC_RES_Q_EVEN_68___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_68__TX_DCOC_RES_Q_EVEN_68___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_68___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_68___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_69 (0x005F5914) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_69___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_69___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_69__TX_DCOC_RES_I_ODD_69___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_69__TX_DCOC_RES_Q_ODD_69___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_69__TX_DCOC_RES_I_EVEN_69___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_69__TX_DCOC_RES_Q_EVEN_69___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_69__TX_DCOC_RES_I_ODD_69___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_69__TX_DCOC_RES_I_ODD_69___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_69__TX_DCOC_RES_Q_ODD_69___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_69__TX_DCOC_RES_Q_ODD_69___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_69__TX_DCOC_RES_I_EVEN_69___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_69__TX_DCOC_RES_I_EVEN_69___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_69__TX_DCOC_RES_Q_EVEN_69___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_69__TX_DCOC_RES_Q_EVEN_69___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_69___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_69___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_70 (0x005F5918) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_70___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_70___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_70__TX_DCOC_RES_I_ODD_70___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_70__TX_DCOC_RES_Q_ODD_70___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_70__TX_DCOC_RES_I_EVEN_70___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_70__TX_DCOC_RES_Q_EVEN_70___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_70__TX_DCOC_RES_I_ODD_70___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_70__TX_DCOC_RES_I_ODD_70___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_70__TX_DCOC_RES_Q_ODD_70___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_70__TX_DCOC_RES_Q_ODD_70___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_70__TX_DCOC_RES_I_EVEN_70___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_70__TX_DCOC_RES_I_EVEN_70___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_70__TX_DCOC_RES_Q_EVEN_70___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_70__TX_DCOC_RES_Q_EVEN_70___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_70___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_70___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_71 (0x005F591C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_71___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_71___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_71__TX_DCOC_RES_I_ODD_71___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_71__TX_DCOC_RES_Q_ODD_71___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_71__TX_DCOC_RES_I_EVEN_71___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_71__TX_DCOC_RES_Q_EVEN_71___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_71__TX_DCOC_RES_I_ODD_71___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_71__TX_DCOC_RES_I_ODD_71___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_71__TX_DCOC_RES_Q_ODD_71___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_71__TX_DCOC_RES_Q_ODD_71___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_71__TX_DCOC_RES_I_EVEN_71___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_71__TX_DCOC_RES_I_EVEN_71___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_71__TX_DCOC_RES_Q_EVEN_71___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_71__TX_DCOC_RES_Q_EVEN_71___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_71___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_71___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_72 (0x005F5920) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_72___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_72___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_72__TX_DCOC_RES_I_ODD_72___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_72__TX_DCOC_RES_Q_ODD_72___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_72__TX_DCOC_RES_I_EVEN_72___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_72__TX_DCOC_RES_Q_EVEN_72___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_72__TX_DCOC_RES_I_ODD_72___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_72__TX_DCOC_RES_I_ODD_72___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_72__TX_DCOC_RES_Q_ODD_72___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_72__TX_DCOC_RES_Q_ODD_72___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_72__TX_DCOC_RES_I_EVEN_72___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_72__TX_DCOC_RES_I_EVEN_72___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_72__TX_DCOC_RES_Q_EVEN_72___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_72__TX_DCOC_RES_Q_EVEN_72___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_72___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_72___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_73 (0x005F5924) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_73___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_73___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_73__TX_DCOC_RES_I_ODD_73___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_73__TX_DCOC_RES_Q_ODD_73___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_73__TX_DCOC_RES_I_EVEN_73___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_73__TX_DCOC_RES_Q_EVEN_73___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_73__TX_DCOC_RES_I_ODD_73___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_73__TX_DCOC_RES_I_ODD_73___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_73__TX_DCOC_RES_Q_ODD_73___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_73__TX_DCOC_RES_Q_ODD_73___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_73__TX_DCOC_RES_I_EVEN_73___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_73__TX_DCOC_RES_I_EVEN_73___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_73__TX_DCOC_RES_Q_EVEN_73___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_73__TX_DCOC_RES_Q_EVEN_73___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_73___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_73___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_74 (0x005F5928) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_74___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_74___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_74__TX_DCOC_RES_I_ODD_74___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_74__TX_DCOC_RES_Q_ODD_74___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_74__TX_DCOC_RES_I_EVEN_74___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_74__TX_DCOC_RES_Q_EVEN_74___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_74__TX_DCOC_RES_I_ODD_74___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_74__TX_DCOC_RES_I_ODD_74___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_74__TX_DCOC_RES_Q_ODD_74___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_74__TX_DCOC_RES_Q_ODD_74___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_74__TX_DCOC_RES_I_EVEN_74___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_74__TX_DCOC_RES_I_EVEN_74___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_74__TX_DCOC_RES_Q_EVEN_74___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_74__TX_DCOC_RES_Q_EVEN_74___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_74___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_74___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_75 (0x005F592C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_75___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_75___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_75__TX_DCOC_RES_I_ODD_75___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_75__TX_DCOC_RES_Q_ODD_75___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_75__TX_DCOC_RES_I_EVEN_75___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_75__TX_DCOC_RES_Q_EVEN_75___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_75__TX_DCOC_RES_I_ODD_75___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_75__TX_DCOC_RES_I_ODD_75___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_75__TX_DCOC_RES_Q_ODD_75___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_75__TX_DCOC_RES_Q_ODD_75___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_75__TX_DCOC_RES_I_EVEN_75___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_75__TX_DCOC_RES_I_EVEN_75___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_75__TX_DCOC_RES_Q_EVEN_75___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_75__TX_DCOC_RES_Q_EVEN_75___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_75___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_75___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_76 (0x005F5930) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_76___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_76___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_76__TX_DCOC_RES_I_ODD_76___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_76__TX_DCOC_RES_Q_ODD_76___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_76__TX_DCOC_RES_I_EVEN_76___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_76__TX_DCOC_RES_Q_EVEN_76___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_76__TX_DCOC_RES_I_ODD_76___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_76__TX_DCOC_RES_I_ODD_76___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_76__TX_DCOC_RES_Q_ODD_76___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_76__TX_DCOC_RES_Q_ODD_76___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_76__TX_DCOC_RES_I_EVEN_76___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_76__TX_DCOC_RES_I_EVEN_76___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_76__TX_DCOC_RES_Q_EVEN_76___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_76__TX_DCOC_RES_Q_EVEN_76___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_76___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_76___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_77 (0x005F5934) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_77___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_77___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_77__TX_DCOC_RES_I_ODD_77___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_77__TX_DCOC_RES_Q_ODD_77___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_77__TX_DCOC_RES_I_EVEN_77___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_77__TX_DCOC_RES_Q_EVEN_77___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_77__TX_DCOC_RES_I_ODD_77___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_77__TX_DCOC_RES_I_ODD_77___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_77__TX_DCOC_RES_Q_ODD_77___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_77__TX_DCOC_RES_Q_ODD_77___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_77__TX_DCOC_RES_I_EVEN_77___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_77__TX_DCOC_RES_I_EVEN_77___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_77__TX_DCOC_RES_Q_EVEN_77___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_77__TX_DCOC_RES_Q_EVEN_77___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_77___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_77___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_78 (0x005F5938) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_78___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_78___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_78__TX_DCOC_RES_I_ODD_78___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_78__TX_DCOC_RES_Q_ODD_78___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_78__TX_DCOC_RES_I_EVEN_78___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_78__TX_DCOC_RES_Q_EVEN_78___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_78__TX_DCOC_RES_I_ODD_78___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_78__TX_DCOC_RES_I_ODD_78___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_78__TX_DCOC_RES_Q_ODD_78___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_78__TX_DCOC_RES_Q_ODD_78___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_78__TX_DCOC_RES_I_EVEN_78___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_78__TX_DCOC_RES_I_EVEN_78___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_78__TX_DCOC_RES_Q_EVEN_78___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_78__TX_DCOC_RES_Q_EVEN_78___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_78___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_78___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_79 (0x005F593C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_79___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_79___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_79__TX_DCOC_RES_I_ODD_79___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_79__TX_DCOC_RES_Q_ODD_79___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_79__TX_DCOC_RES_I_EVEN_79___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_79__TX_DCOC_RES_Q_EVEN_79___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_79__TX_DCOC_RES_I_ODD_79___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_79__TX_DCOC_RES_I_ODD_79___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_79__TX_DCOC_RES_Q_ODD_79___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_79__TX_DCOC_RES_Q_ODD_79___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_79__TX_DCOC_RES_I_EVEN_79___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_79__TX_DCOC_RES_I_EVEN_79___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_79__TX_DCOC_RES_Q_EVEN_79___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_79__TX_DCOC_RES_Q_EVEN_79___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_79___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_79___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_80 (0x005F5940) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_80___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_80___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_80__TX_DCOC_RES_I_ODD_80___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_80__TX_DCOC_RES_Q_ODD_80___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_80__TX_DCOC_RES_I_EVEN_80___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_80__TX_DCOC_RES_Q_EVEN_80___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_80__TX_DCOC_RES_I_ODD_80___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_80__TX_DCOC_RES_I_ODD_80___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_80__TX_DCOC_RES_Q_ODD_80___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_80__TX_DCOC_RES_Q_ODD_80___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_80__TX_DCOC_RES_I_EVEN_80___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_80__TX_DCOC_RES_I_EVEN_80___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_80__TX_DCOC_RES_Q_EVEN_80___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_80__TX_DCOC_RES_Q_EVEN_80___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_80___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_80___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_81 (0x005F5944) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_81___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_81___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_81__TX_DCOC_RES_I_ODD_81___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_81__TX_DCOC_RES_Q_ODD_81___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_81__TX_DCOC_RES_I_EVEN_81___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_81__TX_DCOC_RES_Q_EVEN_81___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_81__TX_DCOC_RES_I_ODD_81___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_81__TX_DCOC_RES_I_ODD_81___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_81__TX_DCOC_RES_Q_ODD_81___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_81__TX_DCOC_RES_Q_ODD_81___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_81__TX_DCOC_RES_I_EVEN_81___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_81__TX_DCOC_RES_I_EVEN_81___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_81__TX_DCOC_RES_Q_EVEN_81___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_81__TX_DCOC_RES_Q_EVEN_81___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_81___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_81___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_82 (0x005F5948) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_82___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_82___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_82__TX_DCOC_RES_I_ODD_82___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_82__TX_DCOC_RES_Q_ODD_82___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_82__TX_DCOC_RES_I_EVEN_82___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_82__TX_DCOC_RES_Q_EVEN_82___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_82__TX_DCOC_RES_I_ODD_82___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_82__TX_DCOC_RES_I_ODD_82___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_82__TX_DCOC_RES_Q_ODD_82___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_82__TX_DCOC_RES_Q_ODD_82___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_82__TX_DCOC_RES_I_EVEN_82___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_82__TX_DCOC_RES_I_EVEN_82___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_82__TX_DCOC_RES_Q_EVEN_82___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_82__TX_DCOC_RES_Q_EVEN_82___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_82___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_82___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_83 (0x005F594C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_83___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_83___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_83__TX_DCOC_RES_I_ODD_83___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_83__TX_DCOC_RES_Q_ODD_83___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_83__TX_DCOC_RES_I_EVEN_83___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_83__TX_DCOC_RES_Q_EVEN_83___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_83__TX_DCOC_RES_I_ODD_83___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_83__TX_DCOC_RES_I_ODD_83___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_83__TX_DCOC_RES_Q_ODD_83___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_83__TX_DCOC_RES_Q_ODD_83___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_83__TX_DCOC_RES_I_EVEN_83___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_83__TX_DCOC_RES_I_EVEN_83___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_83__TX_DCOC_RES_Q_EVEN_83___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_83__TX_DCOC_RES_Q_EVEN_83___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_83___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_83___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_84 (0x005F5950) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_84___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_84___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_84__TX_DCOC_RES_I_ODD_84___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_84__TX_DCOC_RES_Q_ODD_84___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_84__TX_DCOC_RES_I_EVEN_84___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_84__TX_DCOC_RES_Q_EVEN_84___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_84__TX_DCOC_RES_I_ODD_84___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_84__TX_DCOC_RES_I_ODD_84___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_84__TX_DCOC_RES_Q_ODD_84___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_84__TX_DCOC_RES_Q_ODD_84___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_84__TX_DCOC_RES_I_EVEN_84___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_84__TX_DCOC_RES_I_EVEN_84___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_84__TX_DCOC_RES_Q_EVEN_84___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_84__TX_DCOC_RES_Q_EVEN_84___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_84___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_84___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_85 (0x005F5954) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_85___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_85___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_85__TX_DCOC_RES_I_ODD_85___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_85__TX_DCOC_RES_Q_ODD_85___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_85__TX_DCOC_RES_I_EVEN_85___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_85__TX_DCOC_RES_Q_EVEN_85___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_85__TX_DCOC_RES_I_ODD_85___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_85__TX_DCOC_RES_I_ODD_85___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_85__TX_DCOC_RES_Q_ODD_85___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_85__TX_DCOC_RES_Q_ODD_85___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_85__TX_DCOC_RES_I_EVEN_85___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_85__TX_DCOC_RES_I_EVEN_85___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_85__TX_DCOC_RES_Q_EVEN_85___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_85__TX_DCOC_RES_Q_EVEN_85___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_85___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_85___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_86 (0x005F5958) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_86___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_86___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_86__TX_DCOC_RES_I_ODD_86___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_86__TX_DCOC_RES_Q_ODD_86___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_86__TX_DCOC_RES_I_EVEN_86___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_86__TX_DCOC_RES_Q_EVEN_86___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_86__TX_DCOC_RES_I_ODD_86___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_86__TX_DCOC_RES_I_ODD_86___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_86__TX_DCOC_RES_Q_ODD_86___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_86__TX_DCOC_RES_Q_ODD_86___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_86__TX_DCOC_RES_I_EVEN_86___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_86__TX_DCOC_RES_I_EVEN_86___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_86__TX_DCOC_RES_Q_EVEN_86___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_86__TX_DCOC_RES_Q_EVEN_86___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_86___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_86___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_87 (0x005F595C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_87___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_87___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_87__TX_DCOC_RES_I_ODD_87___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_87__TX_DCOC_RES_Q_ODD_87___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_87__TX_DCOC_RES_I_EVEN_87___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_87__TX_DCOC_RES_Q_EVEN_87___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_87__TX_DCOC_RES_I_ODD_87___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_87__TX_DCOC_RES_I_ODD_87___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_87__TX_DCOC_RES_Q_ODD_87___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_87__TX_DCOC_RES_Q_ODD_87___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_87__TX_DCOC_RES_I_EVEN_87___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_87__TX_DCOC_RES_I_EVEN_87___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_87__TX_DCOC_RES_Q_EVEN_87___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_87__TX_DCOC_RES_Q_EVEN_87___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_87___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_87___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_88 (0x005F5960) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_88___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_88___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_88__TX_DCOC_RES_I_ODD_88___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_88__TX_DCOC_RES_Q_ODD_88___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_88__TX_DCOC_RES_I_EVEN_88___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_88__TX_DCOC_RES_Q_EVEN_88___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_88__TX_DCOC_RES_I_ODD_88___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_88__TX_DCOC_RES_I_ODD_88___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_88__TX_DCOC_RES_Q_ODD_88___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_88__TX_DCOC_RES_Q_ODD_88___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_88__TX_DCOC_RES_I_EVEN_88___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_88__TX_DCOC_RES_I_EVEN_88___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_88__TX_DCOC_RES_Q_EVEN_88___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_88__TX_DCOC_RES_Q_EVEN_88___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_88___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_88___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_89 (0x005F5964) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_89___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_89___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_89__TX_DCOC_RES_I_ODD_89___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_89__TX_DCOC_RES_Q_ODD_89___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_89__TX_DCOC_RES_I_EVEN_89___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_89__TX_DCOC_RES_Q_EVEN_89___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_89__TX_DCOC_RES_I_ODD_89___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_89__TX_DCOC_RES_I_ODD_89___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_89__TX_DCOC_RES_Q_ODD_89___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_89__TX_DCOC_RES_Q_ODD_89___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_89__TX_DCOC_RES_I_EVEN_89___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_89__TX_DCOC_RES_I_EVEN_89___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_89__TX_DCOC_RES_Q_EVEN_89___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_89__TX_DCOC_RES_Q_EVEN_89___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_89___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_89___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_90 (0x005F5968) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_90___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_90___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_90__TX_DCOC_RES_I_ODD_90___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_90__TX_DCOC_RES_Q_ODD_90___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_90__TX_DCOC_RES_I_EVEN_90___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_90__TX_DCOC_RES_Q_EVEN_90___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_90__TX_DCOC_RES_I_ODD_90___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_90__TX_DCOC_RES_I_ODD_90___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_90__TX_DCOC_RES_Q_ODD_90___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_90__TX_DCOC_RES_Q_ODD_90___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_90__TX_DCOC_RES_I_EVEN_90___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_90__TX_DCOC_RES_I_EVEN_90___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_90__TX_DCOC_RES_Q_EVEN_90___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_90__TX_DCOC_RES_Q_EVEN_90___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_90___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_90___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_91 (0x005F596C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_91___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_91___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_91__TX_DCOC_RES_I_ODD_91___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_91__TX_DCOC_RES_Q_ODD_91___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_91__TX_DCOC_RES_I_EVEN_91___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_91__TX_DCOC_RES_Q_EVEN_91___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_91__TX_DCOC_RES_I_ODD_91___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_91__TX_DCOC_RES_I_ODD_91___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_91__TX_DCOC_RES_Q_ODD_91___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_91__TX_DCOC_RES_Q_ODD_91___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_91__TX_DCOC_RES_I_EVEN_91___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_91__TX_DCOC_RES_I_EVEN_91___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_91__TX_DCOC_RES_Q_EVEN_91___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_91__TX_DCOC_RES_Q_EVEN_91___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_91___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_91___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_92 (0x005F5970) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_92___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_92___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_92__TX_DCOC_RES_I_ODD_92___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_92__TX_DCOC_RES_Q_ODD_92___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_92__TX_DCOC_RES_I_EVEN_92___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_92__TX_DCOC_RES_Q_EVEN_92___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_92__TX_DCOC_RES_I_ODD_92___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_92__TX_DCOC_RES_I_ODD_92___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_92__TX_DCOC_RES_Q_ODD_92___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_92__TX_DCOC_RES_Q_ODD_92___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_92__TX_DCOC_RES_I_EVEN_92___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_92__TX_DCOC_RES_I_EVEN_92___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_92__TX_DCOC_RES_Q_EVEN_92___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_92__TX_DCOC_RES_Q_EVEN_92___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_92___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_92___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_93 (0x005F5974) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_93___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_93___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_93__TX_DCOC_RES_I_ODD_93___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_93__TX_DCOC_RES_Q_ODD_93___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_93__TX_DCOC_RES_I_EVEN_93___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_93__TX_DCOC_RES_Q_EVEN_93___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_93__TX_DCOC_RES_I_ODD_93___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_93__TX_DCOC_RES_I_ODD_93___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_93__TX_DCOC_RES_Q_ODD_93___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_93__TX_DCOC_RES_Q_ODD_93___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_93__TX_DCOC_RES_I_EVEN_93___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_93__TX_DCOC_RES_I_EVEN_93___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_93__TX_DCOC_RES_Q_EVEN_93___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_93__TX_DCOC_RES_Q_EVEN_93___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_93___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_93___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_94 (0x005F5978) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_94___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_94___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_94__TX_DCOC_RES_I_ODD_94___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_94__TX_DCOC_RES_Q_ODD_94___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_94__TX_DCOC_RES_I_EVEN_94___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_94__TX_DCOC_RES_Q_EVEN_94___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_94__TX_DCOC_RES_I_ODD_94___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_94__TX_DCOC_RES_I_ODD_94___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_94__TX_DCOC_RES_Q_ODD_94___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_94__TX_DCOC_RES_Q_ODD_94___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_94__TX_DCOC_RES_I_EVEN_94___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_94__TX_DCOC_RES_I_EVEN_94___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_94__TX_DCOC_RES_Q_EVEN_94___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_94__TX_DCOC_RES_Q_EVEN_94___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_94___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_94___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_95 (0x005F597C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_95___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_95___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_95__TX_DCOC_RES_I_ODD_95___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_95__TX_DCOC_RES_Q_ODD_95___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_95__TX_DCOC_RES_I_EVEN_95___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_95__TX_DCOC_RES_Q_EVEN_95___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_95__TX_DCOC_RES_I_ODD_95___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_95__TX_DCOC_RES_I_ODD_95___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_95__TX_DCOC_RES_Q_ODD_95___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_95__TX_DCOC_RES_Q_ODD_95___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_95__TX_DCOC_RES_I_EVEN_95___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_95__TX_DCOC_RES_I_EVEN_95___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_95__TX_DCOC_RES_Q_EVEN_95___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_95__TX_DCOC_RES_Q_EVEN_95___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_95___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_95___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_96 (0x005F5980) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_96___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_96___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_96__TX_DCOC_RES_I_ODD_96___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_96__TX_DCOC_RES_Q_ODD_96___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_96__TX_DCOC_RES_I_EVEN_96___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_96__TX_DCOC_RES_Q_EVEN_96___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_96__TX_DCOC_RES_I_ODD_96___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_96__TX_DCOC_RES_I_ODD_96___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_96__TX_DCOC_RES_Q_ODD_96___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_96__TX_DCOC_RES_Q_ODD_96___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_96__TX_DCOC_RES_I_EVEN_96___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_96__TX_DCOC_RES_I_EVEN_96___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_96__TX_DCOC_RES_Q_EVEN_96___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_96__TX_DCOC_RES_Q_EVEN_96___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_96___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_96___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_97 (0x005F5984) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_97___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_97___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_97__TX_DCOC_RES_I_ODD_97___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_97__TX_DCOC_RES_Q_ODD_97___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_97__TX_DCOC_RES_I_EVEN_97___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_97__TX_DCOC_RES_Q_EVEN_97___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_97__TX_DCOC_RES_I_ODD_97___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_97__TX_DCOC_RES_I_ODD_97___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_97__TX_DCOC_RES_Q_ODD_97___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_97__TX_DCOC_RES_Q_ODD_97___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_97__TX_DCOC_RES_I_EVEN_97___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_97__TX_DCOC_RES_I_EVEN_97___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_97__TX_DCOC_RES_Q_EVEN_97___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_97__TX_DCOC_RES_Q_EVEN_97___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_97___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_97___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_98 (0x005F5988) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_98___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_98___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_98__TX_DCOC_RES_I_ODD_98___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_98__TX_DCOC_RES_Q_ODD_98___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_98__TX_DCOC_RES_I_EVEN_98___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_98__TX_DCOC_RES_Q_EVEN_98___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_98__TX_DCOC_RES_I_ODD_98___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_98__TX_DCOC_RES_I_ODD_98___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_98__TX_DCOC_RES_Q_ODD_98___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_98__TX_DCOC_RES_Q_ODD_98___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_98__TX_DCOC_RES_I_EVEN_98___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_98__TX_DCOC_RES_I_EVEN_98___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_98__TX_DCOC_RES_Q_EVEN_98___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_98__TX_DCOC_RES_Q_EVEN_98___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_98___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_98___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_99 (0x005F598C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_99___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_99___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_99__TX_DCOC_RES_I_ODD_99___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_99__TX_DCOC_RES_Q_ODD_99___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_99__TX_DCOC_RES_I_EVEN_99___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_99__TX_DCOC_RES_Q_EVEN_99___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_99__TX_DCOC_RES_I_ODD_99___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_99__TX_DCOC_RES_I_ODD_99___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_99__TX_DCOC_RES_Q_ODD_99___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_99__TX_DCOC_RES_Q_ODD_99___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_99__TX_DCOC_RES_I_EVEN_99___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_99__TX_DCOC_RES_I_EVEN_99___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_99__TX_DCOC_RES_Q_EVEN_99___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_99__TX_DCOC_RES_Q_EVEN_99___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_99___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_99___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_100 (0x005F5990) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_100___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_100___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_100__TX_DCOC_RES_I_ODD_100___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_100__TX_DCOC_RES_Q_ODD_100___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_100__TX_DCOC_RES_I_EVEN_100___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_100__TX_DCOC_RES_Q_EVEN_100___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_100__TX_DCOC_RES_I_ODD_100___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_100__TX_DCOC_RES_I_ODD_100___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_100__TX_DCOC_RES_Q_ODD_100___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_100__TX_DCOC_RES_Q_ODD_100___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_100__TX_DCOC_RES_I_EVEN_100___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_100__TX_DCOC_RES_I_EVEN_100___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_100__TX_DCOC_RES_Q_EVEN_100___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_100__TX_DCOC_RES_Q_EVEN_100___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_100___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_100___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_101 (0x005F5994) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_101___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_101___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_101__TX_DCOC_RES_I_ODD_101___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_101__TX_DCOC_RES_Q_ODD_101___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_101__TX_DCOC_RES_I_EVEN_101___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_101__TX_DCOC_RES_Q_EVEN_101___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_101__TX_DCOC_RES_I_ODD_101___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_101__TX_DCOC_RES_I_ODD_101___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_101__TX_DCOC_RES_Q_ODD_101___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_101__TX_DCOC_RES_Q_ODD_101___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_101__TX_DCOC_RES_I_EVEN_101___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_101__TX_DCOC_RES_I_EVEN_101___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_101__TX_DCOC_RES_Q_EVEN_101___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_101__TX_DCOC_RES_Q_EVEN_101___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_101___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_101___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_102 (0x005F5998) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_102___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_102___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_102__TX_DCOC_RES_I_ODD_102___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_102__TX_DCOC_RES_Q_ODD_102___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_102__TX_DCOC_RES_I_EVEN_102___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_102__TX_DCOC_RES_Q_EVEN_102___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_102__TX_DCOC_RES_I_ODD_102___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_102__TX_DCOC_RES_I_ODD_102___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_102__TX_DCOC_RES_Q_ODD_102___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_102__TX_DCOC_RES_Q_ODD_102___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_102__TX_DCOC_RES_I_EVEN_102___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_102__TX_DCOC_RES_I_EVEN_102___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_102__TX_DCOC_RES_Q_EVEN_102___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_102__TX_DCOC_RES_Q_EVEN_102___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_102___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_102___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_103 (0x005F599C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_103___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_103___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_103__TX_DCOC_RES_I_ODD_103___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_103__TX_DCOC_RES_Q_ODD_103___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_103__TX_DCOC_RES_I_EVEN_103___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_103__TX_DCOC_RES_Q_EVEN_103___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_103__TX_DCOC_RES_I_ODD_103___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_103__TX_DCOC_RES_I_ODD_103___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_103__TX_DCOC_RES_Q_ODD_103___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_103__TX_DCOC_RES_Q_ODD_103___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_103__TX_DCOC_RES_I_EVEN_103___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_103__TX_DCOC_RES_I_EVEN_103___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_103__TX_DCOC_RES_Q_EVEN_103___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_103__TX_DCOC_RES_Q_EVEN_103___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_103___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_103___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_104 (0x005F59A0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_104___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_104___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_104__TX_DCOC_RES_I_ODD_104___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_104__TX_DCOC_RES_Q_ODD_104___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_104__TX_DCOC_RES_I_EVEN_104___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_104__TX_DCOC_RES_Q_EVEN_104___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_104__TX_DCOC_RES_I_ODD_104___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_104__TX_DCOC_RES_I_ODD_104___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_104__TX_DCOC_RES_Q_ODD_104___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_104__TX_DCOC_RES_Q_ODD_104___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_104__TX_DCOC_RES_I_EVEN_104___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_104__TX_DCOC_RES_I_EVEN_104___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_104__TX_DCOC_RES_Q_EVEN_104___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_104__TX_DCOC_RES_Q_EVEN_104___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_104___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_104___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_105 (0x005F59A4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_105___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_105___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_105__TX_DCOC_RES_I_ODD_105___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_105__TX_DCOC_RES_Q_ODD_105___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_105__TX_DCOC_RES_I_EVEN_105___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_105__TX_DCOC_RES_Q_EVEN_105___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_105__TX_DCOC_RES_I_ODD_105___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_105__TX_DCOC_RES_I_ODD_105___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_105__TX_DCOC_RES_Q_ODD_105___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_105__TX_DCOC_RES_Q_ODD_105___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_105__TX_DCOC_RES_I_EVEN_105___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_105__TX_DCOC_RES_I_EVEN_105___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_105__TX_DCOC_RES_Q_EVEN_105___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_105__TX_DCOC_RES_Q_EVEN_105___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_105___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_105___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_106 (0x005F59A8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_106___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_106___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_106__TX_DCOC_RES_I_ODD_106___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_106__TX_DCOC_RES_Q_ODD_106___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_106__TX_DCOC_RES_I_EVEN_106___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_106__TX_DCOC_RES_Q_EVEN_106___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_106__TX_DCOC_RES_I_ODD_106___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_106__TX_DCOC_RES_I_ODD_106___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_106__TX_DCOC_RES_Q_ODD_106___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_106__TX_DCOC_RES_Q_ODD_106___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_106__TX_DCOC_RES_I_EVEN_106___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_106__TX_DCOC_RES_I_EVEN_106___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_106__TX_DCOC_RES_Q_EVEN_106___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_106__TX_DCOC_RES_Q_EVEN_106___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_106___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_106___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_107 (0x005F59AC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_107___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_107___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_107__TX_DCOC_RES_I_ODD_107___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_107__TX_DCOC_RES_Q_ODD_107___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_107__TX_DCOC_RES_I_EVEN_107___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_107__TX_DCOC_RES_Q_EVEN_107___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_107__TX_DCOC_RES_I_ODD_107___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_107__TX_DCOC_RES_I_ODD_107___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_107__TX_DCOC_RES_Q_ODD_107___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_107__TX_DCOC_RES_Q_ODD_107___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_107__TX_DCOC_RES_I_EVEN_107___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_107__TX_DCOC_RES_I_EVEN_107___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_107__TX_DCOC_RES_Q_EVEN_107___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_107__TX_DCOC_RES_Q_EVEN_107___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_107___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_107___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_108 (0x005F59B0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_108___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_108___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_108__TX_DCOC_RES_I_ODD_108___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_108__TX_DCOC_RES_Q_ODD_108___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_108__TX_DCOC_RES_I_EVEN_108___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_108__TX_DCOC_RES_Q_EVEN_108___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_108__TX_DCOC_RES_I_ODD_108___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_108__TX_DCOC_RES_I_ODD_108___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_108__TX_DCOC_RES_Q_ODD_108___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_108__TX_DCOC_RES_Q_ODD_108___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_108__TX_DCOC_RES_I_EVEN_108___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_108__TX_DCOC_RES_I_EVEN_108___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_108__TX_DCOC_RES_Q_EVEN_108___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_108__TX_DCOC_RES_Q_EVEN_108___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_108___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_108___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_109 (0x005F59B4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_109___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_109___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_109__TX_DCOC_RES_I_ODD_109___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_109__TX_DCOC_RES_Q_ODD_109___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_109__TX_DCOC_RES_I_EVEN_109___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_109__TX_DCOC_RES_Q_EVEN_109___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_109__TX_DCOC_RES_I_ODD_109___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_109__TX_DCOC_RES_I_ODD_109___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_109__TX_DCOC_RES_Q_ODD_109___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_109__TX_DCOC_RES_Q_ODD_109___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_109__TX_DCOC_RES_I_EVEN_109___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_109__TX_DCOC_RES_I_EVEN_109___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_109__TX_DCOC_RES_Q_EVEN_109___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_109__TX_DCOC_RES_Q_EVEN_109___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_109___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_109___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_110 (0x005F59B8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_110___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_110___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_110__TX_DCOC_RES_I_ODD_110___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_110__TX_DCOC_RES_Q_ODD_110___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_110__TX_DCOC_RES_I_EVEN_110___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_110__TX_DCOC_RES_Q_EVEN_110___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_110__TX_DCOC_RES_I_ODD_110___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_110__TX_DCOC_RES_I_ODD_110___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_110__TX_DCOC_RES_Q_ODD_110___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_110__TX_DCOC_RES_Q_ODD_110___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_110__TX_DCOC_RES_I_EVEN_110___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_110__TX_DCOC_RES_I_EVEN_110___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_110__TX_DCOC_RES_Q_EVEN_110___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_110__TX_DCOC_RES_Q_EVEN_110___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_110___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_110___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_111 (0x005F59BC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_111___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_111___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_111__TX_DCOC_RES_I_ODD_111___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_111__TX_DCOC_RES_Q_ODD_111___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_111__TX_DCOC_RES_I_EVEN_111___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_111__TX_DCOC_RES_Q_EVEN_111___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_111__TX_DCOC_RES_I_ODD_111___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_111__TX_DCOC_RES_I_ODD_111___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_111__TX_DCOC_RES_Q_ODD_111___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_111__TX_DCOC_RES_Q_ODD_111___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_111__TX_DCOC_RES_I_EVEN_111___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_111__TX_DCOC_RES_I_EVEN_111___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_111__TX_DCOC_RES_Q_EVEN_111___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_111__TX_DCOC_RES_Q_EVEN_111___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_111___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_111___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_112 (0x005F59C0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_112___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_112___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_112__TX_DCOC_RES_I_ODD_112___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_112__TX_DCOC_RES_Q_ODD_112___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_112__TX_DCOC_RES_I_EVEN_112___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_112__TX_DCOC_RES_Q_EVEN_112___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_112__TX_DCOC_RES_I_ODD_112___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_112__TX_DCOC_RES_I_ODD_112___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_112__TX_DCOC_RES_Q_ODD_112___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_112__TX_DCOC_RES_Q_ODD_112___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_112__TX_DCOC_RES_I_EVEN_112___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_112__TX_DCOC_RES_I_EVEN_112___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_112__TX_DCOC_RES_Q_EVEN_112___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_112__TX_DCOC_RES_Q_EVEN_112___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_112___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_112___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_113 (0x005F59C4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_113___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_113___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_113__TX_DCOC_RES_I_ODD_113___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_113__TX_DCOC_RES_Q_ODD_113___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_113__TX_DCOC_RES_I_EVEN_113___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_113__TX_DCOC_RES_Q_EVEN_113___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_113__TX_DCOC_RES_I_ODD_113___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_113__TX_DCOC_RES_I_ODD_113___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_113__TX_DCOC_RES_Q_ODD_113___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_113__TX_DCOC_RES_Q_ODD_113___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_113__TX_DCOC_RES_I_EVEN_113___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_113__TX_DCOC_RES_I_EVEN_113___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_113__TX_DCOC_RES_Q_EVEN_113___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_113__TX_DCOC_RES_Q_EVEN_113___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_113___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_113___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_114 (0x005F59C8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_114___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_114___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_114__TX_DCOC_RES_I_ODD_114___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_114__TX_DCOC_RES_Q_ODD_114___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_114__TX_DCOC_RES_I_EVEN_114___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_114__TX_DCOC_RES_Q_EVEN_114___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_114__TX_DCOC_RES_I_ODD_114___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_114__TX_DCOC_RES_I_ODD_114___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_114__TX_DCOC_RES_Q_ODD_114___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_114__TX_DCOC_RES_Q_ODD_114___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_114__TX_DCOC_RES_I_EVEN_114___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_114__TX_DCOC_RES_I_EVEN_114___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_114__TX_DCOC_RES_Q_EVEN_114___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_114__TX_DCOC_RES_Q_EVEN_114___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_114___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_114___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_115 (0x005F59CC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_115___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_115___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_115__TX_DCOC_RES_I_ODD_115___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_115__TX_DCOC_RES_Q_ODD_115___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_115__TX_DCOC_RES_I_EVEN_115___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_115__TX_DCOC_RES_Q_EVEN_115___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_115__TX_DCOC_RES_I_ODD_115___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_115__TX_DCOC_RES_I_ODD_115___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_115__TX_DCOC_RES_Q_ODD_115___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_115__TX_DCOC_RES_Q_ODD_115___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_115__TX_DCOC_RES_I_EVEN_115___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_115__TX_DCOC_RES_I_EVEN_115___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_115__TX_DCOC_RES_Q_EVEN_115___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_115__TX_DCOC_RES_Q_EVEN_115___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_115___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_115___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_116 (0x005F59D0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_116___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_116___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_116__TX_DCOC_RES_I_ODD_116___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_116__TX_DCOC_RES_Q_ODD_116___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_116__TX_DCOC_RES_I_EVEN_116___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_116__TX_DCOC_RES_Q_EVEN_116___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_116__TX_DCOC_RES_I_ODD_116___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_116__TX_DCOC_RES_I_ODD_116___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_116__TX_DCOC_RES_Q_ODD_116___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_116__TX_DCOC_RES_Q_ODD_116___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_116__TX_DCOC_RES_I_EVEN_116___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_116__TX_DCOC_RES_I_EVEN_116___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_116__TX_DCOC_RES_Q_EVEN_116___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_116__TX_DCOC_RES_Q_EVEN_116___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_116___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_116___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_117 (0x005F59D4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_117___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_117___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_117__TX_DCOC_RES_I_ODD_117___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_117__TX_DCOC_RES_Q_ODD_117___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_117__TX_DCOC_RES_I_EVEN_117___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_117__TX_DCOC_RES_Q_EVEN_117___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_117__TX_DCOC_RES_I_ODD_117___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_117__TX_DCOC_RES_I_ODD_117___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_117__TX_DCOC_RES_Q_ODD_117___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_117__TX_DCOC_RES_Q_ODD_117___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_117__TX_DCOC_RES_I_EVEN_117___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_117__TX_DCOC_RES_I_EVEN_117___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_117__TX_DCOC_RES_Q_EVEN_117___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_117__TX_DCOC_RES_Q_EVEN_117___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_117___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_117___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_118 (0x005F59D8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_118___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_118___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_118__TX_DCOC_RES_I_ODD_118___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_118__TX_DCOC_RES_Q_ODD_118___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_118__TX_DCOC_RES_I_EVEN_118___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_118__TX_DCOC_RES_Q_EVEN_118___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_118__TX_DCOC_RES_I_ODD_118___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_118__TX_DCOC_RES_I_ODD_118___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_118__TX_DCOC_RES_Q_ODD_118___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_118__TX_DCOC_RES_Q_ODD_118___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_118__TX_DCOC_RES_I_EVEN_118___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_118__TX_DCOC_RES_I_EVEN_118___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_118__TX_DCOC_RES_Q_EVEN_118___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_118__TX_DCOC_RES_Q_EVEN_118___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_118___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_118___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_119 (0x005F59DC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_119___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_119___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_119__TX_DCOC_RES_I_ODD_119___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_119__TX_DCOC_RES_Q_ODD_119___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_119__TX_DCOC_RES_I_EVEN_119___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_119__TX_DCOC_RES_Q_EVEN_119___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_119__TX_DCOC_RES_I_ODD_119___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_119__TX_DCOC_RES_I_ODD_119___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_119__TX_DCOC_RES_Q_ODD_119___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_119__TX_DCOC_RES_Q_ODD_119___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_119__TX_DCOC_RES_I_EVEN_119___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_119__TX_DCOC_RES_I_EVEN_119___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_119__TX_DCOC_RES_Q_EVEN_119___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_119__TX_DCOC_RES_Q_EVEN_119___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_119___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_119___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_120 (0x005F59E0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_120___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_120___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_120__TX_DCOC_RES_I_ODD_120___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_120__TX_DCOC_RES_Q_ODD_120___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_120__TX_DCOC_RES_I_EVEN_120___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_120__TX_DCOC_RES_Q_EVEN_120___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_120__TX_DCOC_RES_I_ODD_120___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_120__TX_DCOC_RES_I_ODD_120___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_120__TX_DCOC_RES_Q_ODD_120___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_120__TX_DCOC_RES_Q_ODD_120___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_120__TX_DCOC_RES_I_EVEN_120___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_120__TX_DCOC_RES_I_EVEN_120___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_120__TX_DCOC_RES_Q_EVEN_120___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_120__TX_DCOC_RES_Q_EVEN_120___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_120___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_120___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_121 (0x005F59E4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_121___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_121___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_121__TX_DCOC_RES_I_ODD_121___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_121__TX_DCOC_RES_Q_ODD_121___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_121__TX_DCOC_RES_I_EVEN_121___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_121__TX_DCOC_RES_Q_EVEN_121___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_121__TX_DCOC_RES_I_ODD_121___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_121__TX_DCOC_RES_I_ODD_121___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_121__TX_DCOC_RES_Q_ODD_121___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_121__TX_DCOC_RES_Q_ODD_121___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_121__TX_DCOC_RES_I_EVEN_121___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_121__TX_DCOC_RES_I_EVEN_121___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_121__TX_DCOC_RES_Q_EVEN_121___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_121__TX_DCOC_RES_Q_EVEN_121___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_121___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_121___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_122 (0x005F59E8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_122___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_122___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_122__TX_DCOC_RES_I_ODD_122___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_122__TX_DCOC_RES_Q_ODD_122___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_122__TX_DCOC_RES_I_EVEN_122___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_122__TX_DCOC_RES_Q_EVEN_122___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_122__TX_DCOC_RES_I_ODD_122___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_122__TX_DCOC_RES_I_ODD_122___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_122__TX_DCOC_RES_Q_ODD_122___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_122__TX_DCOC_RES_Q_ODD_122___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_122__TX_DCOC_RES_I_EVEN_122___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_122__TX_DCOC_RES_I_EVEN_122___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_122__TX_DCOC_RES_Q_EVEN_122___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_122__TX_DCOC_RES_Q_EVEN_122___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_122___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_122___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_123 (0x005F59EC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_123___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_123___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_123__TX_DCOC_RES_I_ODD_123___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_123__TX_DCOC_RES_Q_ODD_123___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_123__TX_DCOC_RES_I_EVEN_123___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_123__TX_DCOC_RES_Q_EVEN_123___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_123__TX_DCOC_RES_I_ODD_123___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_123__TX_DCOC_RES_I_ODD_123___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_123__TX_DCOC_RES_Q_ODD_123___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_123__TX_DCOC_RES_Q_ODD_123___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_123__TX_DCOC_RES_I_EVEN_123___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_123__TX_DCOC_RES_I_EVEN_123___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_123__TX_DCOC_RES_Q_EVEN_123___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_123__TX_DCOC_RES_Q_EVEN_123___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_123___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_123___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_124 (0x005F59F0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_124___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_124___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_124__TX_DCOC_RES_I_ODD_124___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_124__TX_DCOC_RES_Q_ODD_124___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_124__TX_DCOC_RES_I_EVEN_124___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_124__TX_DCOC_RES_Q_EVEN_124___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_124__TX_DCOC_RES_I_ODD_124___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_124__TX_DCOC_RES_I_ODD_124___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_124__TX_DCOC_RES_Q_ODD_124___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_124__TX_DCOC_RES_Q_ODD_124___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_124__TX_DCOC_RES_I_EVEN_124___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_124__TX_DCOC_RES_I_EVEN_124___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_124__TX_DCOC_RES_Q_EVEN_124___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_124__TX_DCOC_RES_Q_EVEN_124___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_124___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_124___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_125 (0x005F59F4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_125___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_125___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_125__TX_DCOC_RES_I_ODD_125___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_125__TX_DCOC_RES_Q_ODD_125___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_125__TX_DCOC_RES_I_EVEN_125___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_125__TX_DCOC_RES_Q_EVEN_125___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_125__TX_DCOC_RES_I_ODD_125___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_125__TX_DCOC_RES_I_ODD_125___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_125__TX_DCOC_RES_Q_ODD_125___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_125__TX_DCOC_RES_Q_ODD_125___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_125__TX_DCOC_RES_I_EVEN_125___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_125__TX_DCOC_RES_I_EVEN_125___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_125__TX_DCOC_RES_Q_EVEN_125___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_125__TX_DCOC_RES_Q_EVEN_125___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_125___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_125___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_126 (0x005F59F8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_126___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_126___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_126__TX_DCOC_RES_I_ODD_126___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_126__TX_DCOC_RES_Q_ODD_126___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_126__TX_DCOC_RES_I_EVEN_126___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_126__TX_DCOC_RES_Q_EVEN_126___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_126__TX_DCOC_RES_I_ODD_126___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_126__TX_DCOC_RES_I_ODD_126___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_126__TX_DCOC_RES_Q_ODD_126___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_126__TX_DCOC_RES_Q_ODD_126___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_126__TX_DCOC_RES_I_EVEN_126___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_126__TX_DCOC_RES_I_EVEN_126___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_126__TX_DCOC_RES_Q_EVEN_126___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_126__TX_DCOC_RES_Q_EVEN_126___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_126___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_126___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_127 (0x005F59FC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_127___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_127___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_127__TX_DCOC_RES_I_ODD_127___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_127__TX_DCOC_RES_Q_ODD_127___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_127__TX_DCOC_RES_I_EVEN_127___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_127__TX_DCOC_RES_Q_EVEN_127___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_127__TX_DCOC_RES_I_ODD_127___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_127__TX_DCOC_RES_I_ODD_127___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_127__TX_DCOC_RES_Q_ODD_127___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_127__TX_DCOC_RES_Q_ODD_127___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_127__TX_DCOC_RES_I_EVEN_127___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_127__TX_DCOC_RES_I_EVEN_127___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_127__TX_DCOC_RES_Q_EVEN_127___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_127__TX_DCOC_RES_Q_EVEN_127___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_127___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXDCOC_127___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0 (0x005F5C00) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__IPA_GAIN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__DAC_GAIN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__TX_PWR_LV_LAA_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__TX_PWR_LV_N79_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__BBF_GAIN_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__UPC_GAIN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__DA_GAIN_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__XPA_GAIN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__IPA_GAIN_0___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__IPA_GAIN_0___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__DAC_GAIN_0___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__DAC_GAIN_0___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__TX_PWR_LV_LAA_0___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__TX_PWR_LV_LAA_0___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__TX_PWR_LV_N79_0___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__TX_PWR_LV_N79_0___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__BBF_GAIN_0___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__BBF_GAIN_0___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__UPC_GAIN_0___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__UPC_GAIN_0___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__DA_GAIN_0___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__DA_GAIN_0___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__XPA_GAIN_0___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0__XPA_GAIN_0___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1 (0x005F5C04) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__IPA_GAIN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__DAC_GAIN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__TX_PWR_LV_LAA_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__TX_PWR_LV_N79_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__BBF_GAIN_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__UPC_GAIN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__DA_GAIN_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__XPA_GAIN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__IPA_GAIN_1___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__IPA_GAIN_1___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__DAC_GAIN_1___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__DAC_GAIN_1___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__TX_PWR_LV_LAA_1___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__TX_PWR_LV_LAA_1___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__TX_PWR_LV_N79_1___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__TX_PWR_LV_N79_1___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__BBF_GAIN_1___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__BBF_GAIN_1___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__UPC_GAIN_1___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__UPC_GAIN_1___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__DA_GAIN_1___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__DA_GAIN_1___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__XPA_GAIN_1___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1__XPA_GAIN_1___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2 (0x005F5C08) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__IPA_GAIN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__DAC_GAIN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__TX_PWR_LV_LAA_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__TX_PWR_LV_N79_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__BBF_GAIN_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__UPC_GAIN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__DA_GAIN_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__XPA_GAIN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__IPA_GAIN_2___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__IPA_GAIN_2___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__DAC_GAIN_2___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__DAC_GAIN_2___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__TX_PWR_LV_LAA_2___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__TX_PWR_LV_LAA_2___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__TX_PWR_LV_N79_2___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__TX_PWR_LV_N79_2___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__BBF_GAIN_2___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__BBF_GAIN_2___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__UPC_GAIN_2___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__UPC_GAIN_2___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__DA_GAIN_2___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__DA_GAIN_2___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__XPA_GAIN_2___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2__XPA_GAIN_2___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_2___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3 (0x005F5C0C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__IPA_GAIN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__DAC_GAIN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__TX_PWR_LV_LAA_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__TX_PWR_LV_N79_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__BBF_GAIN_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__UPC_GAIN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__DA_GAIN_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__XPA_GAIN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__IPA_GAIN_3___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__IPA_GAIN_3___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__DAC_GAIN_3___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__DAC_GAIN_3___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__TX_PWR_LV_LAA_3___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__TX_PWR_LV_LAA_3___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__TX_PWR_LV_N79_3___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__TX_PWR_LV_N79_3___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__BBF_GAIN_3___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__BBF_GAIN_3___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__UPC_GAIN_3___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__UPC_GAIN_3___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__DA_GAIN_3___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__DA_GAIN_3___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__XPA_GAIN_3___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3__XPA_GAIN_3___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_3___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4 (0x005F5C10) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__IPA_GAIN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__DAC_GAIN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__TX_PWR_LV_LAA_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__TX_PWR_LV_N79_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__BBF_GAIN_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__UPC_GAIN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__DA_GAIN_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__XPA_GAIN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__IPA_GAIN_4___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__IPA_GAIN_4___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__DAC_GAIN_4___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__DAC_GAIN_4___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__TX_PWR_LV_LAA_4___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__TX_PWR_LV_LAA_4___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__TX_PWR_LV_N79_4___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__TX_PWR_LV_N79_4___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__BBF_GAIN_4___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__BBF_GAIN_4___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__UPC_GAIN_4___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__UPC_GAIN_4___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__DA_GAIN_4___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__DA_GAIN_4___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__XPA_GAIN_4___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4__XPA_GAIN_4___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_4___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5 (0x005F5C14) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__IPA_GAIN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__DAC_GAIN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__TX_PWR_LV_LAA_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__TX_PWR_LV_N79_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__BBF_GAIN_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__UPC_GAIN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__DA_GAIN_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__XPA_GAIN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__IPA_GAIN_5___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__IPA_GAIN_5___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__DAC_GAIN_5___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__DAC_GAIN_5___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__TX_PWR_LV_LAA_5___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__TX_PWR_LV_LAA_5___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__TX_PWR_LV_N79_5___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__TX_PWR_LV_N79_5___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__BBF_GAIN_5___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__BBF_GAIN_5___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__UPC_GAIN_5___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__UPC_GAIN_5___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__DA_GAIN_5___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__DA_GAIN_5___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__XPA_GAIN_5___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5__XPA_GAIN_5___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_5___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6 (0x005F5C18) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__IPA_GAIN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__DAC_GAIN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__TX_PWR_LV_LAA_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__TX_PWR_LV_N79_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__BBF_GAIN_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__UPC_GAIN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__DA_GAIN_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__XPA_GAIN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__IPA_GAIN_6___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__IPA_GAIN_6___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__DAC_GAIN_6___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__DAC_GAIN_6___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__TX_PWR_LV_LAA_6___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__TX_PWR_LV_LAA_6___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__TX_PWR_LV_N79_6___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__TX_PWR_LV_N79_6___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__BBF_GAIN_6___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__BBF_GAIN_6___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__UPC_GAIN_6___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__UPC_GAIN_6___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__DA_GAIN_6___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__DA_GAIN_6___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__XPA_GAIN_6___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6__XPA_GAIN_6___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_6___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7 (0x005F5C1C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__IPA_GAIN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__DAC_GAIN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__TX_PWR_LV_LAA_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__TX_PWR_LV_N79_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__BBF_GAIN_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__UPC_GAIN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__DA_GAIN_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__XPA_GAIN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__IPA_GAIN_7___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__IPA_GAIN_7___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__DAC_GAIN_7___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__DAC_GAIN_7___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__TX_PWR_LV_LAA_7___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__TX_PWR_LV_LAA_7___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__TX_PWR_LV_N79_7___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__TX_PWR_LV_N79_7___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__BBF_GAIN_7___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__BBF_GAIN_7___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__UPC_GAIN_7___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__UPC_GAIN_7___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__DA_GAIN_7___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__DA_GAIN_7___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__XPA_GAIN_7___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7__XPA_GAIN_7___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_7___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8 (0x005F5C20) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__IPA_GAIN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__DAC_GAIN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__TX_PWR_LV_LAA_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__TX_PWR_LV_N79_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__BBF_GAIN_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__UPC_GAIN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__DA_GAIN_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__XPA_GAIN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__IPA_GAIN_8___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__IPA_GAIN_8___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__DAC_GAIN_8___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__DAC_GAIN_8___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__TX_PWR_LV_LAA_8___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__TX_PWR_LV_LAA_8___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__TX_PWR_LV_N79_8___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__TX_PWR_LV_N79_8___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__BBF_GAIN_8___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__BBF_GAIN_8___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__UPC_GAIN_8___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__UPC_GAIN_8___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__DA_GAIN_8___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__DA_GAIN_8___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__XPA_GAIN_8___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8__XPA_GAIN_8___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_8___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9 (0x005F5C24) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__IPA_GAIN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__DAC_GAIN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__TX_PWR_LV_LAA_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__TX_PWR_LV_N79_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__BBF_GAIN_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__UPC_GAIN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__DA_GAIN_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__XPA_GAIN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__IPA_GAIN_9___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__IPA_GAIN_9___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__DAC_GAIN_9___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__DAC_GAIN_9___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__TX_PWR_LV_LAA_9___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__TX_PWR_LV_LAA_9___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__TX_PWR_LV_N79_9___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__TX_PWR_LV_N79_9___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__BBF_GAIN_9___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__BBF_GAIN_9___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__UPC_GAIN_9___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__UPC_GAIN_9___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__DA_GAIN_9___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__DA_GAIN_9___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__XPA_GAIN_9___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9__XPA_GAIN_9___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_9___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10 (0x005F5C28) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__IPA_GAIN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__DAC_GAIN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__TX_PWR_LV_LAA_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__TX_PWR_LV_N79_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__BBF_GAIN_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__UPC_GAIN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__DA_GAIN_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__XPA_GAIN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__IPA_GAIN_10___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__IPA_GAIN_10___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__DAC_GAIN_10___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__DAC_GAIN_10___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__TX_PWR_LV_LAA_10___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__TX_PWR_LV_LAA_10___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__TX_PWR_LV_N79_10___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__TX_PWR_LV_N79_10___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__BBF_GAIN_10___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__BBF_GAIN_10___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__UPC_GAIN_10___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__UPC_GAIN_10___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__DA_GAIN_10___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__DA_GAIN_10___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__XPA_GAIN_10___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10__XPA_GAIN_10___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_10___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11 (0x005F5C2C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__IPA_GAIN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__DAC_GAIN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__TX_PWR_LV_LAA_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__TX_PWR_LV_N79_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__BBF_GAIN_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__UPC_GAIN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__DA_GAIN_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__XPA_GAIN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__IPA_GAIN_11___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__IPA_GAIN_11___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__DAC_GAIN_11___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__DAC_GAIN_11___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__TX_PWR_LV_LAA_11___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__TX_PWR_LV_LAA_11___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__TX_PWR_LV_N79_11___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__TX_PWR_LV_N79_11___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__BBF_GAIN_11___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__BBF_GAIN_11___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__UPC_GAIN_11___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__UPC_GAIN_11___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__DA_GAIN_11___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__DA_GAIN_11___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__XPA_GAIN_11___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11__XPA_GAIN_11___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_11___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12 (0x005F5C30) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__IPA_GAIN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__DAC_GAIN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__TX_PWR_LV_LAA_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__TX_PWR_LV_N79_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__BBF_GAIN_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__UPC_GAIN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__DA_GAIN_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__XPA_GAIN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__IPA_GAIN_12___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__IPA_GAIN_12___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__DAC_GAIN_12___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__DAC_GAIN_12___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__TX_PWR_LV_LAA_12___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__TX_PWR_LV_LAA_12___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__TX_PWR_LV_N79_12___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__TX_PWR_LV_N79_12___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__BBF_GAIN_12___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__BBF_GAIN_12___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__UPC_GAIN_12___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__UPC_GAIN_12___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__DA_GAIN_12___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__DA_GAIN_12___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__XPA_GAIN_12___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12__XPA_GAIN_12___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_12___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13 (0x005F5C34) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__IPA_GAIN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__DAC_GAIN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__TX_PWR_LV_LAA_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__TX_PWR_LV_N79_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__BBF_GAIN_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__UPC_GAIN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__DA_GAIN_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__XPA_GAIN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__IPA_GAIN_13___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__IPA_GAIN_13___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__DAC_GAIN_13___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__DAC_GAIN_13___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__TX_PWR_LV_LAA_13___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__TX_PWR_LV_LAA_13___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__TX_PWR_LV_N79_13___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__TX_PWR_LV_N79_13___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__BBF_GAIN_13___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__BBF_GAIN_13___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__UPC_GAIN_13___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__UPC_GAIN_13___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__DA_GAIN_13___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__DA_GAIN_13___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__XPA_GAIN_13___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13__XPA_GAIN_13___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_13___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14 (0x005F5C38) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__IPA_GAIN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__DAC_GAIN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__TX_PWR_LV_LAA_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__TX_PWR_LV_N79_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__BBF_GAIN_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__UPC_GAIN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__DA_GAIN_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__XPA_GAIN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__IPA_GAIN_14___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__IPA_GAIN_14___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__DAC_GAIN_14___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__DAC_GAIN_14___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__TX_PWR_LV_LAA_14___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__TX_PWR_LV_LAA_14___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__TX_PWR_LV_N79_14___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__TX_PWR_LV_N79_14___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__BBF_GAIN_14___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__BBF_GAIN_14___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__UPC_GAIN_14___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__UPC_GAIN_14___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__DA_GAIN_14___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__DA_GAIN_14___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__XPA_GAIN_14___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14__XPA_GAIN_14___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_14___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15 (0x005F5C3C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__IPA_GAIN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__DAC_GAIN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__TX_PWR_LV_LAA_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__TX_PWR_LV_N79_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__BBF_GAIN_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__UPC_GAIN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__DA_GAIN_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__XPA_GAIN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__IPA_GAIN_15___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__IPA_GAIN_15___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__DAC_GAIN_15___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__DAC_GAIN_15___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__TX_PWR_LV_LAA_15___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__TX_PWR_LV_LAA_15___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__TX_PWR_LV_N79_15___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__TX_PWR_LV_N79_15___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__BBF_GAIN_15___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__BBF_GAIN_15___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__UPC_GAIN_15___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__UPC_GAIN_15___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__DA_GAIN_15___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__DA_GAIN_15___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__XPA_GAIN_15___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15__XPA_GAIN_15___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_15___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16 (0x005F5C40) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__IPA_GAIN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__DAC_GAIN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__TX_PWR_LV_LAA_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__TX_PWR_LV_N79_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__BBF_GAIN_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__UPC_GAIN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__DA_GAIN_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__XPA_GAIN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__IPA_GAIN_16___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__IPA_GAIN_16___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__DAC_GAIN_16___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__DAC_GAIN_16___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__TX_PWR_LV_LAA_16___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__TX_PWR_LV_LAA_16___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__TX_PWR_LV_N79_16___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__TX_PWR_LV_N79_16___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__BBF_GAIN_16___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__BBF_GAIN_16___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__UPC_GAIN_16___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__UPC_GAIN_16___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__DA_GAIN_16___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__DA_GAIN_16___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__XPA_GAIN_16___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16__XPA_GAIN_16___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_16___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17 (0x005F5C44) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__IPA_GAIN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__DAC_GAIN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__TX_PWR_LV_LAA_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__TX_PWR_LV_N79_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__BBF_GAIN_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__UPC_GAIN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__DA_GAIN_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__XPA_GAIN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__IPA_GAIN_17___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__IPA_GAIN_17___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__DAC_GAIN_17___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__DAC_GAIN_17___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__TX_PWR_LV_LAA_17___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__TX_PWR_LV_LAA_17___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__TX_PWR_LV_N79_17___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__TX_PWR_LV_N79_17___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__BBF_GAIN_17___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__BBF_GAIN_17___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__UPC_GAIN_17___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__UPC_GAIN_17___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__DA_GAIN_17___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__DA_GAIN_17___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__XPA_GAIN_17___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17__XPA_GAIN_17___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_17___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18 (0x005F5C48) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__IPA_GAIN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__DAC_GAIN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__TX_PWR_LV_LAA_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__TX_PWR_LV_N79_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__BBF_GAIN_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__UPC_GAIN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__DA_GAIN_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__XPA_GAIN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__IPA_GAIN_18___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__IPA_GAIN_18___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__DAC_GAIN_18___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__DAC_GAIN_18___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__TX_PWR_LV_LAA_18___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__TX_PWR_LV_LAA_18___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__TX_PWR_LV_N79_18___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__TX_PWR_LV_N79_18___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__BBF_GAIN_18___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__BBF_GAIN_18___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__UPC_GAIN_18___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__UPC_GAIN_18___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__DA_GAIN_18___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__DA_GAIN_18___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__XPA_GAIN_18___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18__XPA_GAIN_18___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_18___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19 (0x005F5C4C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__IPA_GAIN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__DAC_GAIN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__TX_PWR_LV_LAA_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__TX_PWR_LV_N79_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__BBF_GAIN_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__UPC_GAIN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__DA_GAIN_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__XPA_GAIN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__IPA_GAIN_19___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__IPA_GAIN_19___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__DAC_GAIN_19___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__DAC_GAIN_19___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__TX_PWR_LV_LAA_19___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__TX_PWR_LV_LAA_19___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__TX_PWR_LV_N79_19___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__TX_PWR_LV_N79_19___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__BBF_GAIN_19___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__BBF_GAIN_19___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__UPC_GAIN_19___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__UPC_GAIN_19___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__DA_GAIN_19___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__DA_GAIN_19___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__XPA_GAIN_19___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19__XPA_GAIN_19___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_19___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20 (0x005F5C50) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__IPA_GAIN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__DAC_GAIN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__TX_PWR_LV_LAA_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__TX_PWR_LV_N79_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__BBF_GAIN_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__UPC_GAIN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__DA_GAIN_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__XPA_GAIN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__IPA_GAIN_20___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__IPA_GAIN_20___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__DAC_GAIN_20___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__DAC_GAIN_20___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__TX_PWR_LV_LAA_20___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__TX_PWR_LV_LAA_20___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__TX_PWR_LV_N79_20___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__TX_PWR_LV_N79_20___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__BBF_GAIN_20___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__BBF_GAIN_20___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__UPC_GAIN_20___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__UPC_GAIN_20___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__DA_GAIN_20___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__DA_GAIN_20___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__XPA_GAIN_20___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20__XPA_GAIN_20___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_20___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21 (0x005F5C54) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__IPA_GAIN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__DAC_GAIN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__TX_PWR_LV_LAA_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__TX_PWR_LV_N79_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__BBF_GAIN_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__UPC_GAIN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__DA_GAIN_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__XPA_GAIN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__IPA_GAIN_21___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__IPA_GAIN_21___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__DAC_GAIN_21___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__DAC_GAIN_21___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__TX_PWR_LV_LAA_21___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__TX_PWR_LV_LAA_21___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__TX_PWR_LV_N79_21___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__TX_PWR_LV_N79_21___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__BBF_GAIN_21___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__BBF_GAIN_21___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__UPC_GAIN_21___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__UPC_GAIN_21___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__DA_GAIN_21___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__DA_GAIN_21___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__XPA_GAIN_21___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21__XPA_GAIN_21___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_21___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22 (0x005F5C58) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__IPA_GAIN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__DAC_GAIN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__TX_PWR_LV_LAA_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__TX_PWR_LV_N79_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__BBF_GAIN_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__UPC_GAIN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__DA_GAIN_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__XPA_GAIN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__IPA_GAIN_22___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__IPA_GAIN_22___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__DAC_GAIN_22___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__DAC_GAIN_22___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__TX_PWR_LV_LAA_22___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__TX_PWR_LV_LAA_22___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__TX_PWR_LV_N79_22___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__TX_PWR_LV_N79_22___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__BBF_GAIN_22___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__BBF_GAIN_22___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__UPC_GAIN_22___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__UPC_GAIN_22___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__DA_GAIN_22___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__DA_GAIN_22___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__XPA_GAIN_22___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22__XPA_GAIN_22___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_22___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23 (0x005F5C5C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__IPA_GAIN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__DAC_GAIN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__TX_PWR_LV_LAA_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__TX_PWR_LV_N79_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__BBF_GAIN_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__UPC_GAIN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__DA_GAIN_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__XPA_GAIN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__IPA_GAIN_23___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__IPA_GAIN_23___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__DAC_GAIN_23___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__DAC_GAIN_23___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__TX_PWR_LV_LAA_23___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__TX_PWR_LV_LAA_23___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__TX_PWR_LV_N79_23___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__TX_PWR_LV_N79_23___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__BBF_GAIN_23___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__BBF_GAIN_23___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__UPC_GAIN_23___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__UPC_GAIN_23___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__DA_GAIN_23___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__DA_GAIN_23___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__XPA_GAIN_23___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23__XPA_GAIN_23___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_23___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24 (0x005F5C60) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__IPA_GAIN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__DAC_GAIN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__TX_PWR_LV_LAA_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__TX_PWR_LV_N79_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__BBF_GAIN_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__UPC_GAIN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__DA_GAIN_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__XPA_GAIN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__IPA_GAIN_24___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__IPA_GAIN_24___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__DAC_GAIN_24___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__DAC_GAIN_24___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__TX_PWR_LV_LAA_24___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__TX_PWR_LV_LAA_24___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__TX_PWR_LV_N79_24___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__TX_PWR_LV_N79_24___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__BBF_GAIN_24___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__BBF_GAIN_24___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__UPC_GAIN_24___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__UPC_GAIN_24___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__DA_GAIN_24___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__DA_GAIN_24___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__XPA_GAIN_24___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24__XPA_GAIN_24___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_24___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25 (0x005F5C64) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__IPA_GAIN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__DAC_GAIN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__TX_PWR_LV_LAA_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__TX_PWR_LV_N79_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__BBF_GAIN_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__UPC_GAIN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__DA_GAIN_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__XPA_GAIN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__IPA_GAIN_25___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__IPA_GAIN_25___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__DAC_GAIN_25___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__DAC_GAIN_25___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__TX_PWR_LV_LAA_25___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__TX_PWR_LV_LAA_25___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__TX_PWR_LV_N79_25___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__TX_PWR_LV_N79_25___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__BBF_GAIN_25___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__BBF_GAIN_25___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__UPC_GAIN_25___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__UPC_GAIN_25___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__DA_GAIN_25___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__DA_GAIN_25___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__XPA_GAIN_25___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25__XPA_GAIN_25___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_25___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26 (0x005F5C68) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__IPA_GAIN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__DAC_GAIN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__TX_PWR_LV_LAA_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__TX_PWR_LV_N79_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__BBF_GAIN_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__UPC_GAIN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__DA_GAIN_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__XPA_GAIN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__IPA_GAIN_26___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__IPA_GAIN_26___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__DAC_GAIN_26___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__DAC_GAIN_26___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__TX_PWR_LV_LAA_26___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__TX_PWR_LV_LAA_26___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__TX_PWR_LV_N79_26___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__TX_PWR_LV_N79_26___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__BBF_GAIN_26___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__BBF_GAIN_26___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__UPC_GAIN_26___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__UPC_GAIN_26___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__DA_GAIN_26___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__DA_GAIN_26___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__XPA_GAIN_26___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26__XPA_GAIN_26___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_26___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27 (0x005F5C6C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__IPA_GAIN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__DAC_GAIN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__TX_PWR_LV_LAA_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__TX_PWR_LV_N79_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__BBF_GAIN_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__UPC_GAIN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__DA_GAIN_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__XPA_GAIN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__IPA_GAIN_27___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__IPA_GAIN_27___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__DAC_GAIN_27___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__DAC_GAIN_27___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__TX_PWR_LV_LAA_27___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__TX_PWR_LV_LAA_27___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__TX_PWR_LV_N79_27___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__TX_PWR_LV_N79_27___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__BBF_GAIN_27___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__BBF_GAIN_27___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__UPC_GAIN_27___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__UPC_GAIN_27___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__DA_GAIN_27___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__DA_GAIN_27___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__XPA_GAIN_27___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27__XPA_GAIN_27___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_27___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28 (0x005F5C70) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__IPA_GAIN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__DAC_GAIN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__TX_PWR_LV_LAA_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__TX_PWR_LV_N79_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__BBF_GAIN_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__UPC_GAIN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__DA_GAIN_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__XPA_GAIN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__IPA_GAIN_28___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__IPA_GAIN_28___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__DAC_GAIN_28___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__DAC_GAIN_28___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__TX_PWR_LV_LAA_28___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__TX_PWR_LV_LAA_28___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__TX_PWR_LV_N79_28___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__TX_PWR_LV_N79_28___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__BBF_GAIN_28___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__BBF_GAIN_28___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__UPC_GAIN_28___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__UPC_GAIN_28___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__DA_GAIN_28___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__DA_GAIN_28___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__XPA_GAIN_28___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28__XPA_GAIN_28___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_28___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29 (0x005F5C74) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__IPA_GAIN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__DAC_GAIN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__TX_PWR_LV_LAA_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__TX_PWR_LV_N79_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__BBF_GAIN_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__UPC_GAIN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__DA_GAIN_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__XPA_GAIN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__IPA_GAIN_29___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__IPA_GAIN_29___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__DAC_GAIN_29___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__DAC_GAIN_29___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__TX_PWR_LV_LAA_29___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__TX_PWR_LV_LAA_29___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__TX_PWR_LV_N79_29___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__TX_PWR_LV_N79_29___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__BBF_GAIN_29___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__BBF_GAIN_29___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__UPC_GAIN_29___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__UPC_GAIN_29___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__DA_GAIN_29___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__DA_GAIN_29___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__XPA_GAIN_29___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29__XPA_GAIN_29___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_29___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30 (0x005F5C78) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__IPA_GAIN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__DAC_GAIN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__TX_PWR_LV_LAA_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__TX_PWR_LV_N79_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__BBF_GAIN_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__UPC_GAIN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__DA_GAIN_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__XPA_GAIN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__IPA_GAIN_30___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__IPA_GAIN_30___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__DAC_GAIN_30___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__DAC_GAIN_30___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__TX_PWR_LV_LAA_30___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__TX_PWR_LV_LAA_30___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__TX_PWR_LV_N79_30___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__TX_PWR_LV_N79_30___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__BBF_GAIN_30___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__BBF_GAIN_30___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__UPC_GAIN_30___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__UPC_GAIN_30___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__DA_GAIN_30___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__DA_GAIN_30___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__XPA_GAIN_30___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30__XPA_GAIN_30___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_30___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31 (0x005F5C7C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__IPA_GAIN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__DAC_GAIN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__TX_PWR_LV_LAA_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__TX_PWR_LV_N79_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__BBF_GAIN_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__UPC_GAIN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__DA_GAIN_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__XPA_GAIN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__IPA_GAIN_31___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__IPA_GAIN_31___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__DAC_GAIN_31___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__DAC_GAIN_31___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__TX_PWR_LV_LAA_31___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__TX_PWR_LV_LAA_31___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__TX_PWR_LV_N79_31___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__TX_PWR_LV_N79_31___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__BBF_GAIN_31___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__BBF_GAIN_31___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__UPC_GAIN_31___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__UPC_GAIN_31___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__DA_GAIN_31___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__DA_GAIN_31___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__XPA_GAIN_31___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31__XPA_GAIN_31___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_31___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32 (0x005F5C80) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__IPA_GAIN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__DAC_GAIN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__TX_PWR_LV_LAA_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__TX_PWR_LV_N79_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__BBF_GAIN_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__UPC_GAIN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__DA_GAIN_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__XPA_GAIN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__IPA_GAIN_32___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__IPA_GAIN_32___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__DAC_GAIN_32___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__DAC_GAIN_32___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__TX_PWR_LV_LAA_32___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__TX_PWR_LV_LAA_32___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__TX_PWR_LV_N79_32___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__TX_PWR_LV_N79_32___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__BBF_GAIN_32___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__BBF_GAIN_32___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__UPC_GAIN_32___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__UPC_GAIN_32___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__DA_GAIN_32___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__DA_GAIN_32___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__XPA_GAIN_32___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32__XPA_GAIN_32___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_32___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33 (0x005F5C84) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__IPA_GAIN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__DAC_GAIN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__TX_PWR_LV_LAA_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__TX_PWR_LV_N79_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__BBF_GAIN_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__UPC_GAIN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__DA_GAIN_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__XPA_GAIN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__IPA_GAIN_33___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__IPA_GAIN_33___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__DAC_GAIN_33___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__DAC_GAIN_33___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__TX_PWR_LV_LAA_33___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__TX_PWR_LV_LAA_33___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__TX_PWR_LV_N79_33___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__TX_PWR_LV_N79_33___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__BBF_GAIN_33___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__BBF_GAIN_33___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__UPC_GAIN_33___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__UPC_GAIN_33___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__DA_GAIN_33___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__DA_GAIN_33___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__XPA_GAIN_33___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33__XPA_GAIN_33___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_33___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34 (0x005F5C88) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__IPA_GAIN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__DAC_GAIN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__TX_PWR_LV_LAA_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__TX_PWR_LV_N79_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__BBF_GAIN_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__UPC_GAIN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__DA_GAIN_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__XPA_GAIN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__IPA_GAIN_34___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__IPA_GAIN_34___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__DAC_GAIN_34___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__DAC_GAIN_34___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__TX_PWR_LV_LAA_34___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__TX_PWR_LV_LAA_34___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__TX_PWR_LV_N79_34___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__TX_PWR_LV_N79_34___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__BBF_GAIN_34___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__BBF_GAIN_34___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__UPC_GAIN_34___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__UPC_GAIN_34___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__DA_GAIN_34___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__DA_GAIN_34___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__XPA_GAIN_34___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34__XPA_GAIN_34___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_34___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35 (0x005F5C8C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__IPA_GAIN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__DAC_GAIN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__TX_PWR_LV_LAA_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__TX_PWR_LV_N79_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__BBF_GAIN_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__UPC_GAIN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__DA_GAIN_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__XPA_GAIN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__IPA_GAIN_35___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__IPA_GAIN_35___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__DAC_GAIN_35___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__DAC_GAIN_35___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__TX_PWR_LV_LAA_35___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__TX_PWR_LV_LAA_35___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__TX_PWR_LV_N79_35___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__TX_PWR_LV_N79_35___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__BBF_GAIN_35___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__BBF_GAIN_35___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__UPC_GAIN_35___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__UPC_GAIN_35___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__DA_GAIN_35___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__DA_GAIN_35___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__XPA_GAIN_35___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35__XPA_GAIN_35___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_35___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36 (0x005F5C90) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__IPA_GAIN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__DAC_GAIN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__TX_PWR_LV_LAA_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__TX_PWR_LV_N79_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__BBF_GAIN_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__UPC_GAIN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__DA_GAIN_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__XPA_GAIN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__IPA_GAIN_36___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__IPA_GAIN_36___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__DAC_GAIN_36___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__DAC_GAIN_36___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__TX_PWR_LV_LAA_36___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__TX_PWR_LV_LAA_36___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__TX_PWR_LV_N79_36___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__TX_PWR_LV_N79_36___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__BBF_GAIN_36___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__BBF_GAIN_36___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__UPC_GAIN_36___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__UPC_GAIN_36___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__DA_GAIN_36___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__DA_GAIN_36___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__XPA_GAIN_36___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36__XPA_GAIN_36___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_36___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37 (0x005F5C94) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__IPA_GAIN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__DAC_GAIN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__TX_PWR_LV_LAA_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__TX_PWR_LV_N79_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__BBF_GAIN_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__UPC_GAIN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__DA_GAIN_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__XPA_GAIN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__IPA_GAIN_37___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__IPA_GAIN_37___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__DAC_GAIN_37___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__DAC_GAIN_37___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__TX_PWR_LV_LAA_37___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__TX_PWR_LV_LAA_37___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__TX_PWR_LV_N79_37___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__TX_PWR_LV_N79_37___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__BBF_GAIN_37___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__BBF_GAIN_37___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__UPC_GAIN_37___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__UPC_GAIN_37___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__DA_GAIN_37___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__DA_GAIN_37___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__XPA_GAIN_37___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37__XPA_GAIN_37___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_37___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38 (0x005F5C98) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__IPA_GAIN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__DAC_GAIN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__TX_PWR_LV_LAA_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__TX_PWR_LV_N79_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__BBF_GAIN_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__UPC_GAIN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__DA_GAIN_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__XPA_GAIN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__IPA_GAIN_38___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__IPA_GAIN_38___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__DAC_GAIN_38___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__DAC_GAIN_38___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__TX_PWR_LV_LAA_38___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__TX_PWR_LV_LAA_38___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__TX_PWR_LV_N79_38___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__TX_PWR_LV_N79_38___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__BBF_GAIN_38___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__BBF_GAIN_38___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__UPC_GAIN_38___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__UPC_GAIN_38___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__DA_GAIN_38___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__DA_GAIN_38___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__XPA_GAIN_38___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38__XPA_GAIN_38___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_38___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39 (0x005F5C9C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__IPA_GAIN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__DAC_GAIN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__TX_PWR_LV_LAA_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__TX_PWR_LV_N79_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__BBF_GAIN_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__UPC_GAIN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__DA_GAIN_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__XPA_GAIN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__IPA_GAIN_39___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__IPA_GAIN_39___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__DAC_GAIN_39___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__DAC_GAIN_39___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__TX_PWR_LV_LAA_39___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__TX_PWR_LV_LAA_39___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__TX_PWR_LV_N79_39___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__TX_PWR_LV_N79_39___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__BBF_GAIN_39___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__BBF_GAIN_39___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__UPC_GAIN_39___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__UPC_GAIN_39___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__DA_GAIN_39___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__DA_GAIN_39___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__XPA_GAIN_39___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39__XPA_GAIN_39___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_39___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40 (0x005F5CA0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__IPA_GAIN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__DAC_GAIN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__TX_PWR_LV_LAA_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__TX_PWR_LV_N79_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__BBF_GAIN_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__UPC_GAIN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__DA_GAIN_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__XPA_GAIN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__IPA_GAIN_40___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__IPA_GAIN_40___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__DAC_GAIN_40___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__DAC_GAIN_40___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__TX_PWR_LV_LAA_40___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__TX_PWR_LV_LAA_40___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__TX_PWR_LV_N79_40___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__TX_PWR_LV_N79_40___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__BBF_GAIN_40___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__BBF_GAIN_40___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__UPC_GAIN_40___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__UPC_GAIN_40___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__DA_GAIN_40___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__DA_GAIN_40___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__XPA_GAIN_40___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40__XPA_GAIN_40___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_40___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41 (0x005F5CA4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__IPA_GAIN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__DAC_GAIN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__TX_PWR_LV_LAA_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__TX_PWR_LV_N79_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__BBF_GAIN_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__UPC_GAIN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__DA_GAIN_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__XPA_GAIN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__IPA_GAIN_41___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__IPA_GAIN_41___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__DAC_GAIN_41___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__DAC_GAIN_41___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__TX_PWR_LV_LAA_41___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__TX_PWR_LV_LAA_41___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__TX_PWR_LV_N79_41___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__TX_PWR_LV_N79_41___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__BBF_GAIN_41___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__BBF_GAIN_41___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__UPC_GAIN_41___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__UPC_GAIN_41___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__DA_GAIN_41___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__DA_GAIN_41___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__XPA_GAIN_41___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41__XPA_GAIN_41___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_41___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42 (0x005F5CA8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__IPA_GAIN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__DAC_GAIN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__TX_PWR_LV_LAA_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__TX_PWR_LV_N79_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__BBF_GAIN_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__UPC_GAIN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__DA_GAIN_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__XPA_GAIN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__IPA_GAIN_42___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__IPA_GAIN_42___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__DAC_GAIN_42___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__DAC_GAIN_42___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__TX_PWR_LV_LAA_42___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__TX_PWR_LV_LAA_42___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__TX_PWR_LV_N79_42___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__TX_PWR_LV_N79_42___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__BBF_GAIN_42___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__BBF_GAIN_42___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__UPC_GAIN_42___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__UPC_GAIN_42___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__DA_GAIN_42___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__DA_GAIN_42___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__XPA_GAIN_42___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42__XPA_GAIN_42___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_42___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43 (0x005F5CAC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__IPA_GAIN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__DAC_GAIN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__TX_PWR_LV_LAA_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__TX_PWR_LV_N79_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__BBF_GAIN_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__UPC_GAIN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__DA_GAIN_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__XPA_GAIN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__IPA_GAIN_43___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__IPA_GAIN_43___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__DAC_GAIN_43___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__DAC_GAIN_43___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__TX_PWR_LV_LAA_43___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__TX_PWR_LV_LAA_43___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__TX_PWR_LV_N79_43___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__TX_PWR_LV_N79_43___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__BBF_GAIN_43___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__BBF_GAIN_43___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__UPC_GAIN_43___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__UPC_GAIN_43___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__DA_GAIN_43___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__DA_GAIN_43___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__XPA_GAIN_43___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43__XPA_GAIN_43___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_43___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44 (0x005F5CB0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__IPA_GAIN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__DAC_GAIN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__TX_PWR_LV_LAA_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__TX_PWR_LV_N79_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__BBF_GAIN_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__UPC_GAIN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__DA_GAIN_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__XPA_GAIN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__IPA_GAIN_44___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__IPA_GAIN_44___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__DAC_GAIN_44___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__DAC_GAIN_44___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__TX_PWR_LV_LAA_44___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__TX_PWR_LV_LAA_44___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__TX_PWR_LV_N79_44___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__TX_PWR_LV_N79_44___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__BBF_GAIN_44___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__BBF_GAIN_44___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__UPC_GAIN_44___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__UPC_GAIN_44___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__DA_GAIN_44___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__DA_GAIN_44___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__XPA_GAIN_44___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44__XPA_GAIN_44___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_44___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45 (0x005F5CB4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__IPA_GAIN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__DAC_GAIN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__TX_PWR_LV_LAA_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__TX_PWR_LV_N79_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__BBF_GAIN_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__UPC_GAIN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__DA_GAIN_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__XPA_GAIN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__IPA_GAIN_45___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__IPA_GAIN_45___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__DAC_GAIN_45___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__DAC_GAIN_45___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__TX_PWR_LV_LAA_45___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__TX_PWR_LV_LAA_45___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__TX_PWR_LV_N79_45___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__TX_PWR_LV_N79_45___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__BBF_GAIN_45___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__BBF_GAIN_45___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__UPC_GAIN_45___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__UPC_GAIN_45___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__DA_GAIN_45___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__DA_GAIN_45___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__XPA_GAIN_45___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45__XPA_GAIN_45___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_45___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46 (0x005F5CB8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__IPA_GAIN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__DAC_GAIN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__TX_PWR_LV_LAA_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__TX_PWR_LV_N79_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__BBF_GAIN_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__UPC_GAIN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__DA_GAIN_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__XPA_GAIN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__IPA_GAIN_46___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__IPA_GAIN_46___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__DAC_GAIN_46___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__DAC_GAIN_46___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__TX_PWR_LV_LAA_46___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__TX_PWR_LV_LAA_46___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__TX_PWR_LV_N79_46___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__TX_PWR_LV_N79_46___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__BBF_GAIN_46___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__BBF_GAIN_46___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__UPC_GAIN_46___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__UPC_GAIN_46___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__DA_GAIN_46___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__DA_GAIN_46___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__XPA_GAIN_46___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46__XPA_GAIN_46___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_46___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47 (0x005F5CBC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__IPA_GAIN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__DAC_GAIN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__TX_PWR_LV_LAA_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__TX_PWR_LV_N79_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__BBF_GAIN_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__UPC_GAIN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__DA_GAIN_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__XPA_GAIN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__IPA_GAIN_47___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__IPA_GAIN_47___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__DAC_GAIN_47___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__DAC_GAIN_47___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__TX_PWR_LV_LAA_47___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__TX_PWR_LV_LAA_47___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__TX_PWR_LV_N79_47___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__TX_PWR_LV_N79_47___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__BBF_GAIN_47___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__BBF_GAIN_47___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__UPC_GAIN_47___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__UPC_GAIN_47___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__DA_GAIN_47___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__DA_GAIN_47___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__XPA_GAIN_47___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47__XPA_GAIN_47___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_47___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48 (0x005F5CC0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__IPA_GAIN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__DAC_GAIN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__TX_PWR_LV_LAA_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__TX_PWR_LV_N79_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__BBF_GAIN_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__UPC_GAIN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__DA_GAIN_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__XPA_GAIN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__IPA_GAIN_48___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__IPA_GAIN_48___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__DAC_GAIN_48___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__DAC_GAIN_48___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__TX_PWR_LV_LAA_48___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__TX_PWR_LV_LAA_48___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__TX_PWR_LV_N79_48___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__TX_PWR_LV_N79_48___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__BBF_GAIN_48___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__BBF_GAIN_48___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__UPC_GAIN_48___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__UPC_GAIN_48___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__DA_GAIN_48___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__DA_GAIN_48___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__XPA_GAIN_48___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48__XPA_GAIN_48___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_48___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49 (0x005F5CC4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__IPA_GAIN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__DAC_GAIN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__TX_PWR_LV_LAA_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__TX_PWR_LV_N79_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__BBF_GAIN_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__UPC_GAIN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__DA_GAIN_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__XPA_GAIN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__IPA_GAIN_49___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__IPA_GAIN_49___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__DAC_GAIN_49___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__DAC_GAIN_49___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__TX_PWR_LV_LAA_49___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__TX_PWR_LV_LAA_49___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__TX_PWR_LV_N79_49___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__TX_PWR_LV_N79_49___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__BBF_GAIN_49___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__BBF_GAIN_49___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__UPC_GAIN_49___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__UPC_GAIN_49___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__DA_GAIN_49___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__DA_GAIN_49___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__XPA_GAIN_49___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49__XPA_GAIN_49___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_49___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50 (0x005F5CC8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__IPA_GAIN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__DAC_GAIN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__TX_PWR_LV_LAA_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__TX_PWR_LV_N79_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__BBF_GAIN_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__UPC_GAIN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__DA_GAIN_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__XPA_GAIN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__IPA_GAIN_50___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__IPA_GAIN_50___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__DAC_GAIN_50___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__DAC_GAIN_50___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__TX_PWR_LV_LAA_50___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__TX_PWR_LV_LAA_50___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__TX_PWR_LV_N79_50___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__TX_PWR_LV_N79_50___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__BBF_GAIN_50___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__BBF_GAIN_50___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__UPC_GAIN_50___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__UPC_GAIN_50___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__DA_GAIN_50___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__DA_GAIN_50___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__XPA_GAIN_50___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50__XPA_GAIN_50___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_50___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51 (0x005F5CCC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__IPA_GAIN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__DAC_GAIN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__TX_PWR_LV_LAA_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__TX_PWR_LV_N79_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__BBF_GAIN_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__UPC_GAIN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__DA_GAIN_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__XPA_GAIN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__IPA_GAIN_51___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__IPA_GAIN_51___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__DAC_GAIN_51___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__DAC_GAIN_51___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__TX_PWR_LV_LAA_51___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__TX_PWR_LV_LAA_51___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__TX_PWR_LV_N79_51___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__TX_PWR_LV_N79_51___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__BBF_GAIN_51___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__BBF_GAIN_51___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__UPC_GAIN_51___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__UPC_GAIN_51___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__DA_GAIN_51___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__DA_GAIN_51___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__XPA_GAIN_51___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51__XPA_GAIN_51___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_51___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52 (0x005F5CD0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__IPA_GAIN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__DAC_GAIN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__TX_PWR_LV_LAA_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__TX_PWR_LV_N79_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__BBF_GAIN_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__UPC_GAIN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__DA_GAIN_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__XPA_GAIN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__IPA_GAIN_52___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__IPA_GAIN_52___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__DAC_GAIN_52___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__DAC_GAIN_52___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__TX_PWR_LV_LAA_52___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__TX_PWR_LV_LAA_52___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__TX_PWR_LV_N79_52___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__TX_PWR_LV_N79_52___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__BBF_GAIN_52___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__BBF_GAIN_52___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__UPC_GAIN_52___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__UPC_GAIN_52___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__DA_GAIN_52___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__DA_GAIN_52___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__XPA_GAIN_52___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52__XPA_GAIN_52___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_52___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53 (0x005F5CD4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__IPA_GAIN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__DAC_GAIN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__TX_PWR_LV_LAA_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__TX_PWR_LV_N79_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__BBF_GAIN_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__UPC_GAIN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__DA_GAIN_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__XPA_GAIN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__IPA_GAIN_53___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__IPA_GAIN_53___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__DAC_GAIN_53___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__DAC_GAIN_53___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__TX_PWR_LV_LAA_53___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__TX_PWR_LV_LAA_53___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__TX_PWR_LV_N79_53___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__TX_PWR_LV_N79_53___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__BBF_GAIN_53___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__BBF_GAIN_53___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__UPC_GAIN_53___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__UPC_GAIN_53___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__DA_GAIN_53___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__DA_GAIN_53___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__XPA_GAIN_53___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53__XPA_GAIN_53___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_53___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54 (0x005F5CD8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__IPA_GAIN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__DAC_GAIN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__TX_PWR_LV_LAA_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__TX_PWR_LV_N79_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__BBF_GAIN_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__UPC_GAIN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__DA_GAIN_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__XPA_GAIN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__IPA_GAIN_54___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__IPA_GAIN_54___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__DAC_GAIN_54___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__DAC_GAIN_54___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__TX_PWR_LV_LAA_54___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__TX_PWR_LV_LAA_54___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__TX_PWR_LV_N79_54___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__TX_PWR_LV_N79_54___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__BBF_GAIN_54___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__BBF_GAIN_54___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__UPC_GAIN_54___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__UPC_GAIN_54___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__DA_GAIN_54___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__DA_GAIN_54___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__XPA_GAIN_54___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54__XPA_GAIN_54___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_54___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55 (0x005F5CDC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__IPA_GAIN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__DAC_GAIN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__TX_PWR_LV_LAA_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__TX_PWR_LV_N79_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__BBF_GAIN_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__UPC_GAIN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__DA_GAIN_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__XPA_GAIN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__IPA_GAIN_55___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__IPA_GAIN_55___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__DAC_GAIN_55___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__DAC_GAIN_55___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__TX_PWR_LV_LAA_55___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__TX_PWR_LV_LAA_55___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__TX_PWR_LV_N79_55___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__TX_PWR_LV_N79_55___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__BBF_GAIN_55___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__BBF_GAIN_55___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__UPC_GAIN_55___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__UPC_GAIN_55___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__DA_GAIN_55___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__DA_GAIN_55___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__XPA_GAIN_55___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55__XPA_GAIN_55___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_55___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56 (0x005F5CE0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__IPA_GAIN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__DAC_GAIN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__TX_PWR_LV_LAA_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__TX_PWR_LV_N79_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__BBF_GAIN_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__UPC_GAIN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__DA_GAIN_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__XPA_GAIN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__IPA_GAIN_56___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__IPA_GAIN_56___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__DAC_GAIN_56___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__DAC_GAIN_56___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__TX_PWR_LV_LAA_56___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__TX_PWR_LV_LAA_56___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__TX_PWR_LV_N79_56___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__TX_PWR_LV_N79_56___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__BBF_GAIN_56___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__BBF_GAIN_56___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__UPC_GAIN_56___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__UPC_GAIN_56___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__DA_GAIN_56___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__DA_GAIN_56___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__XPA_GAIN_56___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56__XPA_GAIN_56___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_56___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57 (0x005F5CE4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__IPA_GAIN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__DAC_GAIN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__TX_PWR_LV_LAA_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__TX_PWR_LV_N79_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__BBF_GAIN_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__UPC_GAIN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__DA_GAIN_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__XPA_GAIN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__IPA_GAIN_57___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__IPA_GAIN_57___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__DAC_GAIN_57___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__DAC_GAIN_57___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__TX_PWR_LV_LAA_57___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__TX_PWR_LV_LAA_57___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__TX_PWR_LV_N79_57___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__TX_PWR_LV_N79_57___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__BBF_GAIN_57___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__BBF_GAIN_57___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__UPC_GAIN_57___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__UPC_GAIN_57___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__DA_GAIN_57___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__DA_GAIN_57___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__XPA_GAIN_57___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57__XPA_GAIN_57___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_57___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58 (0x005F5CE8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__IPA_GAIN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__DAC_GAIN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__TX_PWR_LV_LAA_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__TX_PWR_LV_N79_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__BBF_GAIN_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__UPC_GAIN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__DA_GAIN_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__XPA_GAIN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__IPA_GAIN_58___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__IPA_GAIN_58___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__DAC_GAIN_58___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__DAC_GAIN_58___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__TX_PWR_LV_LAA_58___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__TX_PWR_LV_LAA_58___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__TX_PWR_LV_N79_58___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__TX_PWR_LV_N79_58___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__BBF_GAIN_58___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__BBF_GAIN_58___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__UPC_GAIN_58___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__UPC_GAIN_58___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__DA_GAIN_58___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__DA_GAIN_58___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__XPA_GAIN_58___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58__XPA_GAIN_58___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_58___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59 (0x005F5CEC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__IPA_GAIN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__DAC_GAIN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__TX_PWR_LV_LAA_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__TX_PWR_LV_N79_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__BBF_GAIN_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__UPC_GAIN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__DA_GAIN_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__XPA_GAIN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__IPA_GAIN_59___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__IPA_GAIN_59___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__DAC_GAIN_59___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__DAC_GAIN_59___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__TX_PWR_LV_LAA_59___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__TX_PWR_LV_LAA_59___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__TX_PWR_LV_N79_59___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__TX_PWR_LV_N79_59___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__BBF_GAIN_59___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__BBF_GAIN_59___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__UPC_GAIN_59___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__UPC_GAIN_59___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__DA_GAIN_59___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__DA_GAIN_59___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__XPA_GAIN_59___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59__XPA_GAIN_59___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_59___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60 (0x005F5CF0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__IPA_GAIN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__DAC_GAIN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__TX_PWR_LV_LAA_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__TX_PWR_LV_N79_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__BBF_GAIN_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__UPC_GAIN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__DA_GAIN_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__XPA_GAIN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__IPA_GAIN_60___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__IPA_GAIN_60___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__DAC_GAIN_60___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__DAC_GAIN_60___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__TX_PWR_LV_LAA_60___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__TX_PWR_LV_LAA_60___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__TX_PWR_LV_N79_60___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__TX_PWR_LV_N79_60___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__BBF_GAIN_60___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__BBF_GAIN_60___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__UPC_GAIN_60___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__UPC_GAIN_60___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__DA_GAIN_60___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__DA_GAIN_60___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__XPA_GAIN_60___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60__XPA_GAIN_60___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_60___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61 (0x005F5CF4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__IPA_GAIN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__DAC_GAIN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__TX_PWR_LV_LAA_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__TX_PWR_LV_N79_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__BBF_GAIN_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__UPC_GAIN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__DA_GAIN_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__XPA_GAIN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__IPA_GAIN_61___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__IPA_GAIN_61___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__DAC_GAIN_61___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__DAC_GAIN_61___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__TX_PWR_LV_LAA_61___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__TX_PWR_LV_LAA_61___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__TX_PWR_LV_N79_61___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__TX_PWR_LV_N79_61___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__BBF_GAIN_61___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__BBF_GAIN_61___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__UPC_GAIN_61___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__UPC_GAIN_61___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__DA_GAIN_61___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__DA_GAIN_61___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__XPA_GAIN_61___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61__XPA_GAIN_61___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_61___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62 (0x005F5CF8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__IPA_GAIN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__DAC_GAIN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__TX_PWR_LV_LAA_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__TX_PWR_LV_N79_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__BBF_GAIN_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__UPC_GAIN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__DA_GAIN_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__XPA_GAIN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__IPA_GAIN_62___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__IPA_GAIN_62___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__DAC_GAIN_62___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__DAC_GAIN_62___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__TX_PWR_LV_LAA_62___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__TX_PWR_LV_LAA_62___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__TX_PWR_LV_N79_62___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__TX_PWR_LV_N79_62___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__BBF_GAIN_62___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__BBF_GAIN_62___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__UPC_GAIN_62___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__UPC_GAIN_62___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__DA_GAIN_62___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__DA_GAIN_62___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__XPA_GAIN_62___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62__XPA_GAIN_62___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_62___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63 (0x005F5CFC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__IPA_GAIN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__DAC_GAIN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__TX_PWR_LV_LAA_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__TX_PWR_LV_N79_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__BBF_GAIN_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__UPC_GAIN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__DA_GAIN_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__XPA_GAIN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__IPA_GAIN_63___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__IPA_GAIN_63___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__DAC_GAIN_63___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__DAC_GAIN_63___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__TX_PWR_LV_LAA_63___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__TX_PWR_LV_LAA_63___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__TX_PWR_LV_N79_63___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__TX_PWR_LV_N79_63___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__BBF_GAIN_63___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__BBF_GAIN_63___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__UPC_GAIN_63___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__UPC_GAIN_63___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__DA_GAIN_63___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__DA_GAIN_63___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__XPA_GAIN_63___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63__XPA_GAIN_63___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_63___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64 (0x005F5D00) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__IPA_GAIN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__DAC_GAIN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__TX_PWR_LV_LAA_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__TX_PWR_LV_N79_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__BBF_GAIN_64___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__UPC_GAIN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__DA_GAIN_64___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__XPA_GAIN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__IPA_GAIN_64___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__IPA_GAIN_64___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__DAC_GAIN_64___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__DAC_GAIN_64___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__TX_PWR_LV_LAA_64___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__TX_PWR_LV_LAA_64___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__TX_PWR_LV_N79_64___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__TX_PWR_LV_N79_64___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__BBF_GAIN_64___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__BBF_GAIN_64___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__UPC_GAIN_64___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__UPC_GAIN_64___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__DA_GAIN_64___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__DA_GAIN_64___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__XPA_GAIN_64___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64__XPA_GAIN_64___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_64___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65 (0x005F5D04) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__IPA_GAIN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__DAC_GAIN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__TX_PWR_LV_LAA_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__TX_PWR_LV_N79_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__BBF_GAIN_65___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__UPC_GAIN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__DA_GAIN_65___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__XPA_GAIN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__IPA_GAIN_65___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__IPA_GAIN_65___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__DAC_GAIN_65___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__DAC_GAIN_65___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__TX_PWR_LV_LAA_65___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__TX_PWR_LV_LAA_65___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__TX_PWR_LV_N79_65___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__TX_PWR_LV_N79_65___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__BBF_GAIN_65___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__BBF_GAIN_65___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__UPC_GAIN_65___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__UPC_GAIN_65___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__DA_GAIN_65___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__DA_GAIN_65___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__XPA_GAIN_65___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65__XPA_GAIN_65___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_65___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66 (0x005F5D08) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__IPA_GAIN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__DAC_GAIN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__TX_PWR_LV_LAA_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__TX_PWR_LV_N79_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__BBF_GAIN_66___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__UPC_GAIN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__DA_GAIN_66___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__XPA_GAIN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__IPA_GAIN_66___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__IPA_GAIN_66___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__DAC_GAIN_66___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__DAC_GAIN_66___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__TX_PWR_LV_LAA_66___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__TX_PWR_LV_LAA_66___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__TX_PWR_LV_N79_66___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__TX_PWR_LV_N79_66___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__BBF_GAIN_66___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__BBF_GAIN_66___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__UPC_GAIN_66___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__UPC_GAIN_66___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__DA_GAIN_66___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__DA_GAIN_66___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__XPA_GAIN_66___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66__XPA_GAIN_66___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_66___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67 (0x005F5D0C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__IPA_GAIN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__DAC_GAIN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__TX_PWR_LV_LAA_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__TX_PWR_LV_N79_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__BBF_GAIN_67___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__UPC_GAIN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__DA_GAIN_67___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__XPA_GAIN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__IPA_GAIN_67___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__IPA_GAIN_67___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__DAC_GAIN_67___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__DAC_GAIN_67___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__TX_PWR_LV_LAA_67___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__TX_PWR_LV_LAA_67___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__TX_PWR_LV_N79_67___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__TX_PWR_LV_N79_67___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__BBF_GAIN_67___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__BBF_GAIN_67___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__UPC_GAIN_67___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__UPC_GAIN_67___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__DA_GAIN_67___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__DA_GAIN_67___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__XPA_GAIN_67___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67__XPA_GAIN_67___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_67___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68 (0x005F5D10) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__IPA_GAIN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__DAC_GAIN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__TX_PWR_LV_LAA_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__TX_PWR_LV_N79_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__BBF_GAIN_68___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__UPC_GAIN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__DA_GAIN_68___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__XPA_GAIN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__IPA_GAIN_68___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__IPA_GAIN_68___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__DAC_GAIN_68___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__DAC_GAIN_68___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__TX_PWR_LV_LAA_68___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__TX_PWR_LV_LAA_68___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__TX_PWR_LV_N79_68___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__TX_PWR_LV_N79_68___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__BBF_GAIN_68___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__BBF_GAIN_68___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__UPC_GAIN_68___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__UPC_GAIN_68___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__DA_GAIN_68___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__DA_GAIN_68___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__XPA_GAIN_68___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68__XPA_GAIN_68___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_68___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69 (0x005F5D14) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__IPA_GAIN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__DAC_GAIN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__TX_PWR_LV_LAA_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__TX_PWR_LV_N79_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__BBF_GAIN_69___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__UPC_GAIN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__DA_GAIN_69___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__XPA_GAIN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__IPA_GAIN_69___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__IPA_GAIN_69___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__DAC_GAIN_69___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__DAC_GAIN_69___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__TX_PWR_LV_LAA_69___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__TX_PWR_LV_LAA_69___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__TX_PWR_LV_N79_69___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__TX_PWR_LV_N79_69___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__BBF_GAIN_69___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__BBF_GAIN_69___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__UPC_GAIN_69___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__UPC_GAIN_69___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__DA_GAIN_69___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__DA_GAIN_69___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__XPA_GAIN_69___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69__XPA_GAIN_69___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_69___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70 (0x005F5D18) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__IPA_GAIN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__DAC_GAIN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__TX_PWR_LV_LAA_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__TX_PWR_LV_N79_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__BBF_GAIN_70___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__UPC_GAIN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__DA_GAIN_70___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__XPA_GAIN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__IPA_GAIN_70___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__IPA_GAIN_70___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__DAC_GAIN_70___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__DAC_GAIN_70___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__TX_PWR_LV_LAA_70___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__TX_PWR_LV_LAA_70___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__TX_PWR_LV_N79_70___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__TX_PWR_LV_N79_70___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__BBF_GAIN_70___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__BBF_GAIN_70___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__UPC_GAIN_70___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__UPC_GAIN_70___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__DA_GAIN_70___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__DA_GAIN_70___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__XPA_GAIN_70___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70__XPA_GAIN_70___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_70___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71 (0x005F5D1C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__IPA_GAIN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__DAC_GAIN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__TX_PWR_LV_LAA_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__TX_PWR_LV_N79_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__BBF_GAIN_71___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__UPC_GAIN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__DA_GAIN_71___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__XPA_GAIN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__IPA_GAIN_71___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__IPA_GAIN_71___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__DAC_GAIN_71___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__DAC_GAIN_71___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__TX_PWR_LV_LAA_71___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__TX_PWR_LV_LAA_71___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__TX_PWR_LV_N79_71___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__TX_PWR_LV_N79_71___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__BBF_GAIN_71___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__BBF_GAIN_71___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__UPC_GAIN_71___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__UPC_GAIN_71___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__DA_GAIN_71___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__DA_GAIN_71___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__XPA_GAIN_71___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71__XPA_GAIN_71___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_71___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72 (0x005F5D20) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__IPA_GAIN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__DAC_GAIN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__TX_PWR_LV_LAA_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__TX_PWR_LV_N79_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__BBF_GAIN_72___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__UPC_GAIN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__DA_GAIN_72___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__XPA_GAIN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__IPA_GAIN_72___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__IPA_GAIN_72___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__DAC_GAIN_72___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__DAC_GAIN_72___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__TX_PWR_LV_LAA_72___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__TX_PWR_LV_LAA_72___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__TX_PWR_LV_N79_72___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__TX_PWR_LV_N79_72___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__BBF_GAIN_72___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__BBF_GAIN_72___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__UPC_GAIN_72___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__UPC_GAIN_72___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__DA_GAIN_72___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__DA_GAIN_72___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__XPA_GAIN_72___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72__XPA_GAIN_72___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_72___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73 (0x005F5D24) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__IPA_GAIN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__DAC_GAIN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__TX_PWR_LV_LAA_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__TX_PWR_LV_N79_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__BBF_GAIN_73___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__UPC_GAIN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__DA_GAIN_73___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__XPA_GAIN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__IPA_GAIN_73___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__IPA_GAIN_73___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__DAC_GAIN_73___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__DAC_GAIN_73___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__TX_PWR_LV_LAA_73___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__TX_PWR_LV_LAA_73___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__TX_PWR_LV_N79_73___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__TX_PWR_LV_N79_73___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__BBF_GAIN_73___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__BBF_GAIN_73___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__UPC_GAIN_73___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__UPC_GAIN_73___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__DA_GAIN_73___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__DA_GAIN_73___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__XPA_GAIN_73___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73__XPA_GAIN_73___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_73___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74 (0x005F5D28) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__IPA_GAIN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__DAC_GAIN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__TX_PWR_LV_LAA_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__TX_PWR_LV_N79_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__BBF_GAIN_74___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__UPC_GAIN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__DA_GAIN_74___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__XPA_GAIN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__IPA_GAIN_74___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__IPA_GAIN_74___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__DAC_GAIN_74___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__DAC_GAIN_74___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__TX_PWR_LV_LAA_74___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__TX_PWR_LV_LAA_74___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__TX_PWR_LV_N79_74___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__TX_PWR_LV_N79_74___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__BBF_GAIN_74___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__BBF_GAIN_74___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__UPC_GAIN_74___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__UPC_GAIN_74___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__DA_GAIN_74___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__DA_GAIN_74___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__XPA_GAIN_74___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74__XPA_GAIN_74___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_74___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75 (0x005F5D2C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__IPA_GAIN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__DAC_GAIN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__TX_PWR_LV_LAA_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__TX_PWR_LV_N79_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__BBF_GAIN_75___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__UPC_GAIN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__DA_GAIN_75___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__XPA_GAIN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__IPA_GAIN_75___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__IPA_GAIN_75___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__DAC_GAIN_75___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__DAC_GAIN_75___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__TX_PWR_LV_LAA_75___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__TX_PWR_LV_LAA_75___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__TX_PWR_LV_N79_75___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__TX_PWR_LV_N79_75___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__BBF_GAIN_75___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__BBF_GAIN_75___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__UPC_GAIN_75___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__UPC_GAIN_75___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__DA_GAIN_75___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__DA_GAIN_75___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__XPA_GAIN_75___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75__XPA_GAIN_75___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_75___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76 (0x005F5D30) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__IPA_GAIN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__DAC_GAIN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__TX_PWR_LV_LAA_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__TX_PWR_LV_N79_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__BBF_GAIN_76___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__UPC_GAIN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__DA_GAIN_76___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__XPA_GAIN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__IPA_GAIN_76___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__IPA_GAIN_76___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__DAC_GAIN_76___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__DAC_GAIN_76___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__TX_PWR_LV_LAA_76___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__TX_PWR_LV_LAA_76___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__TX_PWR_LV_N79_76___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__TX_PWR_LV_N79_76___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__BBF_GAIN_76___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__BBF_GAIN_76___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__UPC_GAIN_76___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__UPC_GAIN_76___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__DA_GAIN_76___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__DA_GAIN_76___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__XPA_GAIN_76___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76__XPA_GAIN_76___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_76___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77 (0x005F5D34) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__IPA_GAIN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__DAC_GAIN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__TX_PWR_LV_LAA_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__TX_PWR_LV_N79_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__BBF_GAIN_77___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__UPC_GAIN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__DA_GAIN_77___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__XPA_GAIN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__IPA_GAIN_77___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__IPA_GAIN_77___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__DAC_GAIN_77___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__DAC_GAIN_77___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__TX_PWR_LV_LAA_77___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__TX_PWR_LV_LAA_77___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__TX_PWR_LV_N79_77___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__TX_PWR_LV_N79_77___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__BBF_GAIN_77___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__BBF_GAIN_77___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__UPC_GAIN_77___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__UPC_GAIN_77___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__DA_GAIN_77___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__DA_GAIN_77___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__XPA_GAIN_77___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77__XPA_GAIN_77___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_77___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78 (0x005F5D38) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__IPA_GAIN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__DAC_GAIN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__TX_PWR_LV_LAA_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__TX_PWR_LV_N79_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__BBF_GAIN_78___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__UPC_GAIN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__DA_GAIN_78___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__XPA_GAIN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__IPA_GAIN_78___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__IPA_GAIN_78___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__DAC_GAIN_78___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__DAC_GAIN_78___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__TX_PWR_LV_LAA_78___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__TX_PWR_LV_LAA_78___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__TX_PWR_LV_N79_78___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__TX_PWR_LV_N79_78___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__BBF_GAIN_78___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__BBF_GAIN_78___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__UPC_GAIN_78___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__UPC_GAIN_78___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__DA_GAIN_78___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__DA_GAIN_78___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__XPA_GAIN_78___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78__XPA_GAIN_78___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_78___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79 (0x005F5D3C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__IPA_GAIN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__DAC_GAIN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__TX_PWR_LV_LAA_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__TX_PWR_LV_N79_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__BBF_GAIN_79___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__UPC_GAIN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__DA_GAIN_79___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__XPA_GAIN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__IPA_GAIN_79___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__IPA_GAIN_79___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__DAC_GAIN_79___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__DAC_GAIN_79___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__TX_PWR_LV_LAA_79___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__TX_PWR_LV_LAA_79___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__TX_PWR_LV_N79_79___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__TX_PWR_LV_N79_79___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__BBF_GAIN_79___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__BBF_GAIN_79___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__UPC_GAIN_79___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__UPC_GAIN_79___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__DA_GAIN_79___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__DA_GAIN_79___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__XPA_GAIN_79___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79__XPA_GAIN_79___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_79___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80 (0x005F5D40) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__IPA_GAIN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__DAC_GAIN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__TX_PWR_LV_LAA_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__TX_PWR_LV_N79_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__BBF_GAIN_80___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__UPC_GAIN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__DA_GAIN_80___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__XPA_GAIN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__IPA_GAIN_80___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__IPA_GAIN_80___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__DAC_GAIN_80___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__DAC_GAIN_80___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__TX_PWR_LV_LAA_80___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__TX_PWR_LV_LAA_80___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__TX_PWR_LV_N79_80___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__TX_PWR_LV_N79_80___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__BBF_GAIN_80___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__BBF_GAIN_80___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__UPC_GAIN_80___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__UPC_GAIN_80___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__DA_GAIN_80___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__DA_GAIN_80___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__XPA_GAIN_80___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80__XPA_GAIN_80___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_80___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81 (0x005F5D44) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__IPA_GAIN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__DAC_GAIN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__TX_PWR_LV_LAA_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__TX_PWR_LV_N79_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__BBF_GAIN_81___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__UPC_GAIN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__DA_GAIN_81___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__XPA_GAIN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__IPA_GAIN_81___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__IPA_GAIN_81___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__DAC_GAIN_81___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__DAC_GAIN_81___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__TX_PWR_LV_LAA_81___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__TX_PWR_LV_LAA_81___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__TX_PWR_LV_N79_81___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__TX_PWR_LV_N79_81___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__BBF_GAIN_81___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__BBF_GAIN_81___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__UPC_GAIN_81___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__UPC_GAIN_81___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__DA_GAIN_81___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__DA_GAIN_81___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__XPA_GAIN_81___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81__XPA_GAIN_81___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_81___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82 (0x005F5D48) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__IPA_GAIN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__DAC_GAIN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__TX_PWR_LV_LAA_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__TX_PWR_LV_N79_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__BBF_GAIN_82___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__UPC_GAIN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__DA_GAIN_82___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__XPA_GAIN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__IPA_GAIN_82___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__IPA_GAIN_82___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__DAC_GAIN_82___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__DAC_GAIN_82___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__TX_PWR_LV_LAA_82___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__TX_PWR_LV_LAA_82___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__TX_PWR_LV_N79_82___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__TX_PWR_LV_N79_82___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__BBF_GAIN_82___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__BBF_GAIN_82___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__UPC_GAIN_82___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__UPC_GAIN_82___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__DA_GAIN_82___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__DA_GAIN_82___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__XPA_GAIN_82___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82__XPA_GAIN_82___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_82___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83 (0x005F5D4C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__IPA_GAIN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__DAC_GAIN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__TX_PWR_LV_LAA_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__TX_PWR_LV_N79_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__BBF_GAIN_83___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__UPC_GAIN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__DA_GAIN_83___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__XPA_GAIN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__IPA_GAIN_83___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__IPA_GAIN_83___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__DAC_GAIN_83___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__DAC_GAIN_83___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__TX_PWR_LV_LAA_83___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__TX_PWR_LV_LAA_83___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__TX_PWR_LV_N79_83___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__TX_PWR_LV_N79_83___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__BBF_GAIN_83___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__BBF_GAIN_83___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__UPC_GAIN_83___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__UPC_GAIN_83___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__DA_GAIN_83___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__DA_GAIN_83___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__XPA_GAIN_83___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83__XPA_GAIN_83___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_83___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84 (0x005F5D50) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__IPA_GAIN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__DAC_GAIN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__TX_PWR_LV_LAA_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__TX_PWR_LV_N79_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__BBF_GAIN_84___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__UPC_GAIN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__DA_GAIN_84___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__XPA_GAIN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__IPA_GAIN_84___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__IPA_GAIN_84___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__DAC_GAIN_84___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__DAC_GAIN_84___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__TX_PWR_LV_LAA_84___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__TX_PWR_LV_LAA_84___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__TX_PWR_LV_N79_84___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__TX_PWR_LV_N79_84___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__BBF_GAIN_84___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__BBF_GAIN_84___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__UPC_GAIN_84___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__UPC_GAIN_84___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__DA_GAIN_84___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__DA_GAIN_84___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__XPA_GAIN_84___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84__XPA_GAIN_84___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_84___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85 (0x005F5D54) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__IPA_GAIN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__DAC_GAIN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__TX_PWR_LV_LAA_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__TX_PWR_LV_N79_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__BBF_GAIN_85___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__UPC_GAIN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__DA_GAIN_85___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__XPA_GAIN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__IPA_GAIN_85___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__IPA_GAIN_85___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__DAC_GAIN_85___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__DAC_GAIN_85___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__TX_PWR_LV_LAA_85___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__TX_PWR_LV_LAA_85___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__TX_PWR_LV_N79_85___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__TX_PWR_LV_N79_85___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__BBF_GAIN_85___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__BBF_GAIN_85___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__UPC_GAIN_85___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__UPC_GAIN_85___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__DA_GAIN_85___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__DA_GAIN_85___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__XPA_GAIN_85___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85__XPA_GAIN_85___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_85___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86 (0x005F5D58) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__IPA_GAIN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__DAC_GAIN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__TX_PWR_LV_LAA_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__TX_PWR_LV_N79_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__BBF_GAIN_86___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__UPC_GAIN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__DA_GAIN_86___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__XPA_GAIN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__IPA_GAIN_86___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__IPA_GAIN_86___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__DAC_GAIN_86___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__DAC_GAIN_86___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__TX_PWR_LV_LAA_86___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__TX_PWR_LV_LAA_86___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__TX_PWR_LV_N79_86___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__TX_PWR_LV_N79_86___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__BBF_GAIN_86___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__BBF_GAIN_86___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__UPC_GAIN_86___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__UPC_GAIN_86___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__DA_GAIN_86___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__DA_GAIN_86___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__XPA_GAIN_86___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86__XPA_GAIN_86___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_86___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87 (0x005F5D5C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__IPA_GAIN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__DAC_GAIN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__TX_PWR_LV_LAA_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__TX_PWR_LV_N79_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__BBF_GAIN_87___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__UPC_GAIN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__DA_GAIN_87___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__XPA_GAIN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__IPA_GAIN_87___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__IPA_GAIN_87___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__DAC_GAIN_87___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__DAC_GAIN_87___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__TX_PWR_LV_LAA_87___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__TX_PWR_LV_LAA_87___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__TX_PWR_LV_N79_87___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__TX_PWR_LV_N79_87___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__BBF_GAIN_87___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__BBF_GAIN_87___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__UPC_GAIN_87___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__UPC_GAIN_87___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__DA_GAIN_87___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__DA_GAIN_87___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__XPA_GAIN_87___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87__XPA_GAIN_87___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_87___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88 (0x005F5D60) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__IPA_GAIN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__DAC_GAIN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__TX_PWR_LV_LAA_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__TX_PWR_LV_N79_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__BBF_GAIN_88___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__UPC_GAIN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__DA_GAIN_88___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__XPA_GAIN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__IPA_GAIN_88___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__IPA_GAIN_88___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__DAC_GAIN_88___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__DAC_GAIN_88___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__TX_PWR_LV_LAA_88___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__TX_PWR_LV_LAA_88___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__TX_PWR_LV_N79_88___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__TX_PWR_LV_N79_88___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__BBF_GAIN_88___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__BBF_GAIN_88___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__UPC_GAIN_88___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__UPC_GAIN_88___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__DA_GAIN_88___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__DA_GAIN_88___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__XPA_GAIN_88___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88__XPA_GAIN_88___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_88___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89 (0x005F5D64) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__IPA_GAIN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__DAC_GAIN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__TX_PWR_LV_LAA_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__TX_PWR_LV_N79_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__BBF_GAIN_89___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__UPC_GAIN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__DA_GAIN_89___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__XPA_GAIN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__IPA_GAIN_89___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__IPA_GAIN_89___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__DAC_GAIN_89___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__DAC_GAIN_89___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__TX_PWR_LV_LAA_89___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__TX_PWR_LV_LAA_89___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__TX_PWR_LV_N79_89___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__TX_PWR_LV_N79_89___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__BBF_GAIN_89___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__BBF_GAIN_89___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__UPC_GAIN_89___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__UPC_GAIN_89___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__DA_GAIN_89___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__DA_GAIN_89___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__XPA_GAIN_89___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89__XPA_GAIN_89___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_89___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90 (0x005F5D68) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__IPA_GAIN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__DAC_GAIN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__TX_PWR_LV_LAA_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__TX_PWR_LV_N79_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__BBF_GAIN_90___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__UPC_GAIN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__DA_GAIN_90___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__XPA_GAIN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__IPA_GAIN_90___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__IPA_GAIN_90___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__DAC_GAIN_90___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__DAC_GAIN_90___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__TX_PWR_LV_LAA_90___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__TX_PWR_LV_LAA_90___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__TX_PWR_LV_N79_90___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__TX_PWR_LV_N79_90___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__BBF_GAIN_90___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__BBF_GAIN_90___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__UPC_GAIN_90___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__UPC_GAIN_90___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__DA_GAIN_90___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__DA_GAIN_90___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__XPA_GAIN_90___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90__XPA_GAIN_90___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_90___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91 (0x005F5D6C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__IPA_GAIN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__DAC_GAIN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__TX_PWR_LV_LAA_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__TX_PWR_LV_N79_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__BBF_GAIN_91___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__UPC_GAIN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__DA_GAIN_91___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__XPA_GAIN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__IPA_GAIN_91___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__IPA_GAIN_91___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__DAC_GAIN_91___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__DAC_GAIN_91___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__TX_PWR_LV_LAA_91___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__TX_PWR_LV_LAA_91___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__TX_PWR_LV_N79_91___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__TX_PWR_LV_N79_91___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__BBF_GAIN_91___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__BBF_GAIN_91___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__UPC_GAIN_91___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__UPC_GAIN_91___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__DA_GAIN_91___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__DA_GAIN_91___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__XPA_GAIN_91___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91__XPA_GAIN_91___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_91___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92 (0x005F5D70) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__IPA_GAIN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__DAC_GAIN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__TX_PWR_LV_LAA_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__TX_PWR_LV_N79_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__BBF_GAIN_92___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__UPC_GAIN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__DA_GAIN_92___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__XPA_GAIN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__IPA_GAIN_92___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__IPA_GAIN_92___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__DAC_GAIN_92___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__DAC_GAIN_92___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__TX_PWR_LV_LAA_92___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__TX_PWR_LV_LAA_92___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__TX_PWR_LV_N79_92___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__TX_PWR_LV_N79_92___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__BBF_GAIN_92___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__BBF_GAIN_92___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__UPC_GAIN_92___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__UPC_GAIN_92___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__DA_GAIN_92___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__DA_GAIN_92___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__XPA_GAIN_92___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92__XPA_GAIN_92___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_92___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93 (0x005F5D74) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__IPA_GAIN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__DAC_GAIN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__TX_PWR_LV_LAA_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__TX_PWR_LV_N79_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__BBF_GAIN_93___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__UPC_GAIN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__DA_GAIN_93___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__XPA_GAIN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__IPA_GAIN_93___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__IPA_GAIN_93___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__DAC_GAIN_93___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__DAC_GAIN_93___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__TX_PWR_LV_LAA_93___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__TX_PWR_LV_LAA_93___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__TX_PWR_LV_N79_93___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__TX_PWR_LV_N79_93___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__BBF_GAIN_93___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__BBF_GAIN_93___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__UPC_GAIN_93___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__UPC_GAIN_93___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__DA_GAIN_93___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__DA_GAIN_93___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__XPA_GAIN_93___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93__XPA_GAIN_93___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_93___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94 (0x005F5D78) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__IPA_GAIN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__DAC_GAIN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__TX_PWR_LV_LAA_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__TX_PWR_LV_N79_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__BBF_GAIN_94___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__UPC_GAIN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__DA_GAIN_94___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__XPA_GAIN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__IPA_GAIN_94___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__IPA_GAIN_94___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__DAC_GAIN_94___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__DAC_GAIN_94___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__TX_PWR_LV_LAA_94___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__TX_PWR_LV_LAA_94___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__TX_PWR_LV_N79_94___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__TX_PWR_LV_N79_94___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__BBF_GAIN_94___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__BBF_GAIN_94___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__UPC_GAIN_94___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__UPC_GAIN_94___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__DA_GAIN_94___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__DA_GAIN_94___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__XPA_GAIN_94___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94__XPA_GAIN_94___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_94___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95 (0x005F5D7C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__IPA_GAIN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__DAC_GAIN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__TX_PWR_LV_LAA_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__TX_PWR_LV_N79_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__BBF_GAIN_95___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__UPC_GAIN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__DA_GAIN_95___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__XPA_GAIN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__IPA_GAIN_95___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__IPA_GAIN_95___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__DAC_GAIN_95___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__DAC_GAIN_95___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__TX_PWR_LV_LAA_95___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__TX_PWR_LV_LAA_95___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__TX_PWR_LV_N79_95___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__TX_PWR_LV_N79_95___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__BBF_GAIN_95___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__BBF_GAIN_95___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__UPC_GAIN_95___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__UPC_GAIN_95___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__DA_GAIN_95___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__DA_GAIN_95___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__XPA_GAIN_95___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95__XPA_GAIN_95___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_95___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96 (0x005F5D80) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__IPA_GAIN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__DAC_GAIN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__TX_PWR_LV_LAA_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__TX_PWR_LV_N79_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__BBF_GAIN_96___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__UPC_GAIN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__DA_GAIN_96___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__XPA_GAIN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__IPA_GAIN_96___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__IPA_GAIN_96___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__DAC_GAIN_96___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__DAC_GAIN_96___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__TX_PWR_LV_LAA_96___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__TX_PWR_LV_LAA_96___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__TX_PWR_LV_N79_96___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__TX_PWR_LV_N79_96___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__BBF_GAIN_96___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__BBF_GAIN_96___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__UPC_GAIN_96___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__UPC_GAIN_96___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__DA_GAIN_96___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__DA_GAIN_96___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__XPA_GAIN_96___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96__XPA_GAIN_96___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_96___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97 (0x005F5D84) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__IPA_GAIN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__DAC_GAIN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__TX_PWR_LV_LAA_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__TX_PWR_LV_N79_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__BBF_GAIN_97___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__UPC_GAIN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__DA_GAIN_97___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__XPA_GAIN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__IPA_GAIN_97___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__IPA_GAIN_97___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__DAC_GAIN_97___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__DAC_GAIN_97___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__TX_PWR_LV_LAA_97___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__TX_PWR_LV_LAA_97___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__TX_PWR_LV_N79_97___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__TX_PWR_LV_N79_97___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__BBF_GAIN_97___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__BBF_GAIN_97___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__UPC_GAIN_97___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__UPC_GAIN_97___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__DA_GAIN_97___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__DA_GAIN_97___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__XPA_GAIN_97___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97__XPA_GAIN_97___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_97___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98 (0x005F5D88) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__IPA_GAIN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__DAC_GAIN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__TX_PWR_LV_LAA_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__TX_PWR_LV_N79_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__BBF_GAIN_98___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__UPC_GAIN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__DA_GAIN_98___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__XPA_GAIN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__IPA_GAIN_98___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__IPA_GAIN_98___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__DAC_GAIN_98___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__DAC_GAIN_98___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__TX_PWR_LV_LAA_98___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__TX_PWR_LV_LAA_98___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__TX_PWR_LV_N79_98___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__TX_PWR_LV_N79_98___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__BBF_GAIN_98___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__BBF_GAIN_98___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__UPC_GAIN_98___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__UPC_GAIN_98___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__DA_GAIN_98___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__DA_GAIN_98___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__XPA_GAIN_98___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98__XPA_GAIN_98___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_98___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99 (0x005F5D8C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__IPA_GAIN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__DAC_GAIN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__TX_PWR_LV_LAA_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__TX_PWR_LV_N79_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__BBF_GAIN_99___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__UPC_GAIN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__DA_GAIN_99___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__XPA_GAIN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__IPA_GAIN_99___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__IPA_GAIN_99___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__DAC_GAIN_99___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__DAC_GAIN_99___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__TX_PWR_LV_LAA_99___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__TX_PWR_LV_LAA_99___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__TX_PWR_LV_N79_99___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__TX_PWR_LV_N79_99___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__BBF_GAIN_99___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__BBF_GAIN_99___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__UPC_GAIN_99___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__UPC_GAIN_99___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__DA_GAIN_99___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__DA_GAIN_99___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__XPA_GAIN_99___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99__XPA_GAIN_99___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_99___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100 (0x005F5D90) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__IPA_GAIN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__DAC_GAIN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__TX_PWR_LV_LAA_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__TX_PWR_LV_N79_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__BBF_GAIN_100___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__UPC_GAIN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__DA_GAIN_100___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__XPA_GAIN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__IPA_GAIN_100___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__IPA_GAIN_100___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__DAC_GAIN_100___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__DAC_GAIN_100___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__TX_PWR_LV_LAA_100___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__TX_PWR_LV_LAA_100___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__TX_PWR_LV_N79_100___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__TX_PWR_LV_N79_100___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__BBF_GAIN_100___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__BBF_GAIN_100___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__UPC_GAIN_100___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__UPC_GAIN_100___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__DA_GAIN_100___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__DA_GAIN_100___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__XPA_GAIN_100___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100__XPA_GAIN_100___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_100___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101 (0x005F5D94) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__IPA_GAIN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__DAC_GAIN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__TX_PWR_LV_LAA_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__TX_PWR_LV_N79_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__BBF_GAIN_101___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__UPC_GAIN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__DA_GAIN_101___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__XPA_GAIN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__IPA_GAIN_101___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__IPA_GAIN_101___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__DAC_GAIN_101___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__DAC_GAIN_101___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__TX_PWR_LV_LAA_101___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__TX_PWR_LV_LAA_101___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__TX_PWR_LV_N79_101___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__TX_PWR_LV_N79_101___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__BBF_GAIN_101___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__BBF_GAIN_101___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__UPC_GAIN_101___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__UPC_GAIN_101___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__DA_GAIN_101___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__DA_GAIN_101___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__XPA_GAIN_101___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101__XPA_GAIN_101___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_101___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102 (0x005F5D98) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__IPA_GAIN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__DAC_GAIN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__TX_PWR_LV_LAA_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__TX_PWR_LV_N79_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__BBF_GAIN_102___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__UPC_GAIN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__DA_GAIN_102___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__XPA_GAIN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__IPA_GAIN_102___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__IPA_GAIN_102___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__DAC_GAIN_102___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__DAC_GAIN_102___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__TX_PWR_LV_LAA_102___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__TX_PWR_LV_LAA_102___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__TX_PWR_LV_N79_102___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__TX_PWR_LV_N79_102___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__BBF_GAIN_102___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__BBF_GAIN_102___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__UPC_GAIN_102___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__UPC_GAIN_102___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__DA_GAIN_102___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__DA_GAIN_102___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__XPA_GAIN_102___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102__XPA_GAIN_102___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_102___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103 (0x005F5D9C) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__IPA_GAIN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__DAC_GAIN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__TX_PWR_LV_LAA_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__TX_PWR_LV_N79_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__BBF_GAIN_103___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__UPC_GAIN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__DA_GAIN_103___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__XPA_GAIN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__IPA_GAIN_103___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__IPA_GAIN_103___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__DAC_GAIN_103___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__DAC_GAIN_103___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__TX_PWR_LV_LAA_103___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__TX_PWR_LV_LAA_103___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__TX_PWR_LV_N79_103___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__TX_PWR_LV_N79_103___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__BBF_GAIN_103___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__BBF_GAIN_103___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__UPC_GAIN_103___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__UPC_GAIN_103___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__DA_GAIN_103___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__DA_GAIN_103___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__XPA_GAIN_103___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103__XPA_GAIN_103___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_103___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104 (0x005F5DA0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__IPA_GAIN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__DAC_GAIN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__TX_PWR_LV_LAA_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__TX_PWR_LV_N79_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__BBF_GAIN_104___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__UPC_GAIN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__DA_GAIN_104___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__XPA_GAIN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__IPA_GAIN_104___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__IPA_GAIN_104___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__DAC_GAIN_104___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__DAC_GAIN_104___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__TX_PWR_LV_LAA_104___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__TX_PWR_LV_LAA_104___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__TX_PWR_LV_N79_104___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__TX_PWR_LV_N79_104___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__BBF_GAIN_104___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__BBF_GAIN_104___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__UPC_GAIN_104___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__UPC_GAIN_104___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__DA_GAIN_104___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__DA_GAIN_104___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__XPA_GAIN_104___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104__XPA_GAIN_104___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_104___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105 (0x005F5DA4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__IPA_GAIN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__DAC_GAIN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__TX_PWR_LV_LAA_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__TX_PWR_LV_N79_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__BBF_GAIN_105___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__UPC_GAIN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__DA_GAIN_105___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__XPA_GAIN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__IPA_GAIN_105___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__IPA_GAIN_105___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__DAC_GAIN_105___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__DAC_GAIN_105___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__TX_PWR_LV_LAA_105___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__TX_PWR_LV_LAA_105___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__TX_PWR_LV_N79_105___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__TX_PWR_LV_N79_105___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__BBF_GAIN_105___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__BBF_GAIN_105___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__UPC_GAIN_105___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__UPC_GAIN_105___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__DA_GAIN_105___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__DA_GAIN_105___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__XPA_GAIN_105___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105__XPA_GAIN_105___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_105___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106 (0x005F5DA8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__IPA_GAIN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__DAC_GAIN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__TX_PWR_LV_LAA_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__TX_PWR_LV_N79_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__BBF_GAIN_106___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__UPC_GAIN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__DA_GAIN_106___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__XPA_GAIN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__IPA_GAIN_106___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__IPA_GAIN_106___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__DAC_GAIN_106___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__DAC_GAIN_106___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__TX_PWR_LV_LAA_106___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__TX_PWR_LV_LAA_106___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__TX_PWR_LV_N79_106___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__TX_PWR_LV_N79_106___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__BBF_GAIN_106___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__BBF_GAIN_106___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__UPC_GAIN_106___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__UPC_GAIN_106___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__DA_GAIN_106___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__DA_GAIN_106___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__XPA_GAIN_106___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106__XPA_GAIN_106___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_106___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107 (0x005F5DAC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__IPA_GAIN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__DAC_GAIN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__TX_PWR_LV_LAA_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__TX_PWR_LV_N79_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__BBF_GAIN_107___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__UPC_GAIN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__DA_GAIN_107___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__XPA_GAIN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__IPA_GAIN_107___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__IPA_GAIN_107___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__DAC_GAIN_107___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__DAC_GAIN_107___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__TX_PWR_LV_LAA_107___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__TX_PWR_LV_LAA_107___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__TX_PWR_LV_N79_107___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__TX_PWR_LV_N79_107___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__BBF_GAIN_107___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__BBF_GAIN_107___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__UPC_GAIN_107___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__UPC_GAIN_107___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__DA_GAIN_107___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__DA_GAIN_107___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__XPA_GAIN_107___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107__XPA_GAIN_107___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_107___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108 (0x005F5DB0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__IPA_GAIN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__DAC_GAIN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__TX_PWR_LV_LAA_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__TX_PWR_LV_N79_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__BBF_GAIN_108___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__UPC_GAIN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__DA_GAIN_108___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__XPA_GAIN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__IPA_GAIN_108___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__IPA_GAIN_108___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__DAC_GAIN_108___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__DAC_GAIN_108___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__TX_PWR_LV_LAA_108___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__TX_PWR_LV_LAA_108___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__TX_PWR_LV_N79_108___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__TX_PWR_LV_N79_108___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__BBF_GAIN_108___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__BBF_GAIN_108___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__UPC_GAIN_108___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__UPC_GAIN_108___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__DA_GAIN_108___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__DA_GAIN_108___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__XPA_GAIN_108___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108__XPA_GAIN_108___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_108___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109 (0x005F5DB4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__IPA_GAIN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__DAC_GAIN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__TX_PWR_LV_LAA_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__TX_PWR_LV_N79_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__BBF_GAIN_109___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__UPC_GAIN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__DA_GAIN_109___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__XPA_GAIN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__IPA_GAIN_109___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__IPA_GAIN_109___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__DAC_GAIN_109___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__DAC_GAIN_109___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__TX_PWR_LV_LAA_109___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__TX_PWR_LV_LAA_109___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__TX_PWR_LV_N79_109___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__TX_PWR_LV_N79_109___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__BBF_GAIN_109___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__BBF_GAIN_109___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__UPC_GAIN_109___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__UPC_GAIN_109___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__DA_GAIN_109___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__DA_GAIN_109___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__XPA_GAIN_109___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109__XPA_GAIN_109___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_109___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110 (0x005F5DB8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__IPA_GAIN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__DAC_GAIN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__TX_PWR_LV_LAA_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__TX_PWR_LV_N79_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__BBF_GAIN_110___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__UPC_GAIN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__DA_GAIN_110___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__XPA_GAIN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__IPA_GAIN_110___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__IPA_GAIN_110___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__DAC_GAIN_110___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__DAC_GAIN_110___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__TX_PWR_LV_LAA_110___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__TX_PWR_LV_LAA_110___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__TX_PWR_LV_N79_110___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__TX_PWR_LV_N79_110___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__BBF_GAIN_110___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__BBF_GAIN_110___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__UPC_GAIN_110___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__UPC_GAIN_110___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__DA_GAIN_110___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__DA_GAIN_110___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__XPA_GAIN_110___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110__XPA_GAIN_110___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_110___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111 (0x005F5DBC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__IPA_GAIN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__DAC_GAIN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__TX_PWR_LV_LAA_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__TX_PWR_LV_N79_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__BBF_GAIN_111___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__UPC_GAIN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__DA_GAIN_111___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__XPA_GAIN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__IPA_GAIN_111___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__IPA_GAIN_111___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__DAC_GAIN_111___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__DAC_GAIN_111___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__TX_PWR_LV_LAA_111___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__TX_PWR_LV_LAA_111___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__TX_PWR_LV_N79_111___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__TX_PWR_LV_N79_111___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__BBF_GAIN_111___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__BBF_GAIN_111___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__UPC_GAIN_111___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__UPC_GAIN_111___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__DA_GAIN_111___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__DA_GAIN_111___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__XPA_GAIN_111___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111__XPA_GAIN_111___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_111___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112 (0x005F5DC0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__IPA_GAIN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__DAC_GAIN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__TX_PWR_LV_LAA_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__TX_PWR_LV_N79_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__BBF_GAIN_112___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__UPC_GAIN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__DA_GAIN_112___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__XPA_GAIN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__IPA_GAIN_112___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__IPA_GAIN_112___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__DAC_GAIN_112___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__DAC_GAIN_112___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__TX_PWR_LV_LAA_112___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__TX_PWR_LV_LAA_112___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__TX_PWR_LV_N79_112___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__TX_PWR_LV_N79_112___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__BBF_GAIN_112___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__BBF_GAIN_112___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__UPC_GAIN_112___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__UPC_GAIN_112___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__DA_GAIN_112___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__DA_GAIN_112___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__XPA_GAIN_112___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112__XPA_GAIN_112___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_112___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113 (0x005F5DC4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__IPA_GAIN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__DAC_GAIN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__TX_PWR_LV_LAA_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__TX_PWR_LV_N79_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__BBF_GAIN_113___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__UPC_GAIN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__DA_GAIN_113___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__XPA_GAIN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__IPA_GAIN_113___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__IPA_GAIN_113___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__DAC_GAIN_113___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__DAC_GAIN_113___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__TX_PWR_LV_LAA_113___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__TX_PWR_LV_LAA_113___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__TX_PWR_LV_N79_113___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__TX_PWR_LV_N79_113___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__BBF_GAIN_113___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__BBF_GAIN_113___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__UPC_GAIN_113___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__UPC_GAIN_113___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__DA_GAIN_113___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__DA_GAIN_113___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__XPA_GAIN_113___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113__XPA_GAIN_113___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_113___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114 (0x005F5DC8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__IPA_GAIN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__DAC_GAIN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__TX_PWR_LV_LAA_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__TX_PWR_LV_N79_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__BBF_GAIN_114___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__UPC_GAIN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__DA_GAIN_114___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__XPA_GAIN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__IPA_GAIN_114___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__IPA_GAIN_114___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__DAC_GAIN_114___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__DAC_GAIN_114___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__TX_PWR_LV_LAA_114___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__TX_PWR_LV_LAA_114___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__TX_PWR_LV_N79_114___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__TX_PWR_LV_N79_114___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__BBF_GAIN_114___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__BBF_GAIN_114___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__UPC_GAIN_114___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__UPC_GAIN_114___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__DA_GAIN_114___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__DA_GAIN_114___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__XPA_GAIN_114___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114__XPA_GAIN_114___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_114___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115 (0x005F5DCC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__IPA_GAIN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__DAC_GAIN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__TX_PWR_LV_LAA_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__TX_PWR_LV_N79_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__BBF_GAIN_115___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__UPC_GAIN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__DA_GAIN_115___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__XPA_GAIN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__IPA_GAIN_115___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__IPA_GAIN_115___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__DAC_GAIN_115___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__DAC_GAIN_115___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__TX_PWR_LV_LAA_115___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__TX_PWR_LV_LAA_115___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__TX_PWR_LV_N79_115___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__TX_PWR_LV_N79_115___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__BBF_GAIN_115___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__BBF_GAIN_115___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__UPC_GAIN_115___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__UPC_GAIN_115___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__DA_GAIN_115___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__DA_GAIN_115___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__XPA_GAIN_115___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115__XPA_GAIN_115___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_115___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116 (0x005F5DD0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__IPA_GAIN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__DAC_GAIN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__TX_PWR_LV_LAA_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__TX_PWR_LV_N79_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__BBF_GAIN_116___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__UPC_GAIN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__DA_GAIN_116___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__XPA_GAIN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__IPA_GAIN_116___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__IPA_GAIN_116___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__DAC_GAIN_116___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__DAC_GAIN_116___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__TX_PWR_LV_LAA_116___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__TX_PWR_LV_LAA_116___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__TX_PWR_LV_N79_116___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__TX_PWR_LV_N79_116___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__BBF_GAIN_116___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__BBF_GAIN_116___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__UPC_GAIN_116___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__UPC_GAIN_116___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__DA_GAIN_116___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__DA_GAIN_116___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__XPA_GAIN_116___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116__XPA_GAIN_116___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_116___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117 (0x005F5DD4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__IPA_GAIN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__DAC_GAIN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__TX_PWR_LV_LAA_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__TX_PWR_LV_N79_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__BBF_GAIN_117___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__UPC_GAIN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__DA_GAIN_117___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__XPA_GAIN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__IPA_GAIN_117___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__IPA_GAIN_117___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__DAC_GAIN_117___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__DAC_GAIN_117___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__TX_PWR_LV_LAA_117___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__TX_PWR_LV_LAA_117___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__TX_PWR_LV_N79_117___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__TX_PWR_LV_N79_117___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__BBF_GAIN_117___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__BBF_GAIN_117___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__UPC_GAIN_117___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__UPC_GAIN_117___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__DA_GAIN_117___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__DA_GAIN_117___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__XPA_GAIN_117___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117__XPA_GAIN_117___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_117___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118 (0x005F5DD8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__IPA_GAIN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__DAC_GAIN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__TX_PWR_LV_LAA_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__TX_PWR_LV_N79_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__BBF_GAIN_118___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__UPC_GAIN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__DA_GAIN_118___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__XPA_GAIN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__IPA_GAIN_118___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__IPA_GAIN_118___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__DAC_GAIN_118___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__DAC_GAIN_118___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__TX_PWR_LV_LAA_118___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__TX_PWR_LV_LAA_118___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__TX_PWR_LV_N79_118___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__TX_PWR_LV_N79_118___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__BBF_GAIN_118___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__BBF_GAIN_118___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__UPC_GAIN_118___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__UPC_GAIN_118___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__DA_GAIN_118___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__DA_GAIN_118___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__XPA_GAIN_118___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118__XPA_GAIN_118___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_118___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119 (0x005F5DDC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__IPA_GAIN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__DAC_GAIN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__TX_PWR_LV_LAA_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__TX_PWR_LV_N79_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__BBF_GAIN_119___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__UPC_GAIN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__DA_GAIN_119___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__XPA_GAIN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__IPA_GAIN_119___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__IPA_GAIN_119___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__DAC_GAIN_119___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__DAC_GAIN_119___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__TX_PWR_LV_LAA_119___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__TX_PWR_LV_LAA_119___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__TX_PWR_LV_N79_119___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__TX_PWR_LV_N79_119___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__BBF_GAIN_119___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__BBF_GAIN_119___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__UPC_GAIN_119___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__UPC_GAIN_119___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__DA_GAIN_119___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__DA_GAIN_119___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__XPA_GAIN_119___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119__XPA_GAIN_119___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_119___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120 (0x005F5DE0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__IPA_GAIN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__DAC_GAIN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__TX_PWR_LV_LAA_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__TX_PWR_LV_N79_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__BBF_GAIN_120___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__UPC_GAIN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__DA_GAIN_120___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__XPA_GAIN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__IPA_GAIN_120___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__IPA_GAIN_120___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__DAC_GAIN_120___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__DAC_GAIN_120___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__TX_PWR_LV_LAA_120___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__TX_PWR_LV_LAA_120___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__TX_PWR_LV_N79_120___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__TX_PWR_LV_N79_120___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__BBF_GAIN_120___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__BBF_GAIN_120___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__UPC_GAIN_120___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__UPC_GAIN_120___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__DA_GAIN_120___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__DA_GAIN_120___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__XPA_GAIN_120___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120__XPA_GAIN_120___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_120___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121 (0x005F5DE4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__IPA_GAIN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__DAC_GAIN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__TX_PWR_LV_LAA_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__TX_PWR_LV_N79_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__BBF_GAIN_121___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__UPC_GAIN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__DA_GAIN_121___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__XPA_GAIN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__IPA_GAIN_121___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__IPA_GAIN_121___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__DAC_GAIN_121___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__DAC_GAIN_121___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__TX_PWR_LV_LAA_121___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__TX_PWR_LV_LAA_121___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__TX_PWR_LV_N79_121___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__TX_PWR_LV_N79_121___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__BBF_GAIN_121___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__BBF_GAIN_121___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__UPC_GAIN_121___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__UPC_GAIN_121___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__DA_GAIN_121___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__DA_GAIN_121___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__XPA_GAIN_121___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121__XPA_GAIN_121___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_121___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122 (0x005F5DE8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__IPA_GAIN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__DAC_GAIN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__TX_PWR_LV_LAA_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__TX_PWR_LV_N79_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__BBF_GAIN_122___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__UPC_GAIN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__DA_GAIN_122___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__XPA_GAIN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__IPA_GAIN_122___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__IPA_GAIN_122___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__DAC_GAIN_122___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__DAC_GAIN_122___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__TX_PWR_LV_LAA_122___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__TX_PWR_LV_LAA_122___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__TX_PWR_LV_N79_122___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__TX_PWR_LV_N79_122___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__BBF_GAIN_122___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__BBF_GAIN_122___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__UPC_GAIN_122___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__UPC_GAIN_122___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__DA_GAIN_122___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__DA_GAIN_122___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__XPA_GAIN_122___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122__XPA_GAIN_122___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_122___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123 (0x005F5DEC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__IPA_GAIN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__DAC_GAIN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__TX_PWR_LV_LAA_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__TX_PWR_LV_N79_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__BBF_GAIN_123___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__UPC_GAIN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__DA_GAIN_123___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__XPA_GAIN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__IPA_GAIN_123___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__IPA_GAIN_123___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__DAC_GAIN_123___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__DAC_GAIN_123___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__TX_PWR_LV_LAA_123___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__TX_PWR_LV_LAA_123___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__TX_PWR_LV_N79_123___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__TX_PWR_LV_N79_123___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__BBF_GAIN_123___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__BBF_GAIN_123___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__UPC_GAIN_123___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__UPC_GAIN_123___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__DA_GAIN_123___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__DA_GAIN_123___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__XPA_GAIN_123___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123__XPA_GAIN_123___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_123___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124 (0x005F5DF0) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__IPA_GAIN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__DAC_GAIN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__TX_PWR_LV_LAA_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__TX_PWR_LV_N79_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__BBF_GAIN_124___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__UPC_GAIN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__DA_GAIN_124___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__XPA_GAIN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__IPA_GAIN_124___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__IPA_GAIN_124___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__DAC_GAIN_124___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__DAC_GAIN_124___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__TX_PWR_LV_LAA_124___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__TX_PWR_LV_LAA_124___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__TX_PWR_LV_N79_124___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__TX_PWR_LV_N79_124___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__BBF_GAIN_124___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__BBF_GAIN_124___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__UPC_GAIN_124___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__UPC_GAIN_124___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__DA_GAIN_124___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__DA_GAIN_124___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__XPA_GAIN_124___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124__XPA_GAIN_124___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_124___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125 (0x005F5DF4) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__IPA_GAIN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__DAC_GAIN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__TX_PWR_LV_LAA_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__TX_PWR_LV_N79_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__BBF_GAIN_125___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__UPC_GAIN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__DA_GAIN_125___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__XPA_GAIN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__IPA_GAIN_125___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__IPA_GAIN_125___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__DAC_GAIN_125___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__DAC_GAIN_125___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__TX_PWR_LV_LAA_125___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__TX_PWR_LV_LAA_125___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__TX_PWR_LV_N79_125___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__TX_PWR_LV_N79_125___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__BBF_GAIN_125___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__BBF_GAIN_125___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__UPC_GAIN_125___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__UPC_GAIN_125___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__DA_GAIN_125___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__DA_GAIN_125___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__XPA_GAIN_125___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125__XPA_GAIN_125___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_125___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126 (0x005F5DF8) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__IPA_GAIN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__DAC_GAIN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__TX_PWR_LV_LAA_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__TX_PWR_LV_N79_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__BBF_GAIN_126___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__UPC_GAIN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__DA_GAIN_126___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__XPA_GAIN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__IPA_GAIN_126___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__IPA_GAIN_126___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__DAC_GAIN_126___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__DAC_GAIN_126___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__TX_PWR_LV_LAA_126___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__TX_PWR_LV_LAA_126___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__TX_PWR_LV_N79_126___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__TX_PWR_LV_N79_126___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__BBF_GAIN_126___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__BBF_GAIN_126___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__UPC_GAIN_126___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__UPC_GAIN_126___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__DA_GAIN_126___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__DA_GAIN_126___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__XPA_GAIN_126___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126__XPA_GAIN_126___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_126___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127 (0x005F5DFC) +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__IPA_GAIN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__DAC_GAIN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__TX_PWR_LV_LAA_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__TX_PWR_LV_N79_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__BBF_GAIN_127___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__UPC_GAIN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__DA_GAIN_127___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__XPA_GAIN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__IPA_GAIN_127___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__IPA_GAIN_127___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__DAC_GAIN_127___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__DAC_GAIN_127___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__TX_PWR_LV_LAA_127___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__TX_PWR_LV_LAA_127___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__TX_PWR_LV_N79_127___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__TX_PWR_LV_N79_127___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__BBF_GAIN_127___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__BBF_GAIN_127___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__UPC_GAIN_127___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__UPC_GAIN_127___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__DA_GAIN_127___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__DA_GAIN_127___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__XPA_GAIN_127___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127__XPA_GAIN_127___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_2G_CH1_TXGAIN_127___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_TESTREG (0x005F8000) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_TESTREG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_TESTREG___POR 0x0000AB80 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_TESTREG__TESTREG___POR 0x0000AB80 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_TESTREG__TESTREG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_TESTREG__TESTREG___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_TESTREG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_TESTREG___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_0 (0x005F8004) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_0__SYN_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_0__SYN_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_0__SYN_EN___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_0___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1 (0x005F8008) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__XPA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__IPA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__INJECT_TXLO_I_OFFSET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__LPBK_TX_CHAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__TX_RESIDUE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__RF_LPBK_PHASE_SHIFT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__CAL_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__XPA_EN_OVS___M 0x00001800 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__XPA_EN_OVS___S 11 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__IPA_EN_OVS___M 0x00000600 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__IPA_EN_OVS___S 9 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__INJECT_TXLO_I_OFFSET___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__INJECT_TXLO_I_OFFSET___S 7 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__LPBK_TX_CHAIN___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__LPBK_TX_CHAIN___S 6 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__TX_RESIDUE___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__TX_RESIDUE___S 5 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__RF_LPBK_PHASE_SHIFT___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__RF_LPBK_PHASE_SHIFT___S 4 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__CAL_MODE___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1__CAL_MODE___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_0 (0x005F800C) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_0___POR 0x00000010 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_0__TRSW_EN_RXGAIN_CAL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_0__TRSW_EN_DPD___POR 0x1 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_0__CAL_SUB_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_0__TRSW_EN_RXGAIN_CAL___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_0__TRSW_EN_RXGAIN_CAL___S 5 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_0__TRSW_EN_DPD___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_0__TRSW_EN_DPD___S 4 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_0__CAL_SUB_MODE___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_0__CAL_SUB_MODE___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_0___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_1 (0x005F8010) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_1___POR 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_1__FCS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_1__LP_RX_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_1__CLPC_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_1__FCS___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_1__FCS___S 2 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_1__LP_RX_EN___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_1__LP_RX_EN___S 1 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_1__CLPC_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_1__CLPC_EN___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_1___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2 (0x005F8014) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2___POR 0x0000C001 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__PMM_SYN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_CORE_RX_GAIN_ON___POR 0x1 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_CORE_RX_DCOC_ON___POR 0x1 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_CORE_TX_GAIN_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_CORE_TX_DCOC_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_PERIPH_RX_GAIN_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_PERIPH_RX_DCOC_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_PERIPH_TX_GAIN_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_PERIPH_TX_DCOC_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__RXIQ_CROSS_CHAIN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__PMM_SYN_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__PMM_SYN_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_CORE_RX_GAIN_ON___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_CORE_RX_GAIN_ON___S 15 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_CORE_RX_DCOC_ON___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_CORE_RX_DCOC_ON___S 14 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_CORE_TX_GAIN_ON___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_CORE_TX_GAIN_ON___S 13 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_CORE_TX_DCOC_ON___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_CORE_TX_DCOC_ON___S 12 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_PERIPH_RX_GAIN_ON___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_PERIPH_RX_GAIN_ON___S 11 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_PERIPH_RX_DCOC_ON___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_PERIPH_RX_DCOC_ON___S 10 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_PERIPH_TX_GAIN_ON___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_PERIPH_TX_GAIN_ON___S 9 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_PERIPH_TX_DCOC_ON___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__FORCE_PERIPH_TX_DCOC_ON___S 8 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__RXIQ_CROSS_CHAIN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2__RXIQ_CROSS_CHAIN___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2___M 0xC000FF01 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MODE_SEL_2___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_BBSAT_0 (0x005F8018) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_BBSAT_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_BBSAT_0___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_BBSAT_0__AGC_BBSAT_RESET_PERIOD___POR 0x14 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_BBSAT_0__AGC_BBSAT_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_BBSAT_0__AGC_BBSAT_FLAG_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_BBSAT_0__RX_SATDET_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_BBSAT_0__AGC_BBSAT_RESET_PERIOD___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_BBSAT_0__AGC_BBSAT_RESET_PERIOD___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_BBSAT_0__AGC_BBSAT_MODE___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_BBSAT_0__AGC_BBSAT_MODE___S 25 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_BBSAT_0__AGC_BBSAT_FLAG_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_BBSAT_0__AGC_BBSAT_FLAG_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_BBSAT_0__RX_SATDET_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_BBSAT_0__RX_SATDET_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_BBSAT_0___M 0xFECC0000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_BBSAT_0___S 18 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0 (0x005F801C) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0__AGC_PKDET_RESET_PERIOD___POR 0x14 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0__AGC_PKDET_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0__AGC_PKDET_FLAG_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0__AGC_EN_BY_RX_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0__AGC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0__AGC_PKDET_RESET_PERIOD___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0__AGC_PKDET_RESET_PERIOD___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0__AGC_PKDET_MODE___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0__AGC_PKDET_MODE___S 25 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0__AGC_PKDET_FLAG_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0__AGC_PKDET_FLAG_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0__AGC_EN_BY_RX_EN___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0__AGC_EN_BY_RX_EN___S 20 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0__AGC_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0__AGC_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0___M 0xFEDC0000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PKDET_0___S 18 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_PKDET (0x005F8020) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_PKDET___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_PKDET___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_PKDET__RO_AGC_PKDET_FLAG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_PKDET__RO_AGC_BBSAT_FLAG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_PKDET__RO_AGC_PKDET_FLAG___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_PKDET__RO_AGC_PKDET_FLAG___S 1 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_PKDET__RO_AGC_BBSAT_FLAG___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_PKDET__RO_AGC_BBSAT_FLAG___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_PKDET___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_PKDET___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0 (0x005F8024) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0___POR 0x06769292 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T0_START_PRD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T0_END_PRD___POR 0x6 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T1_START_PRD___POR 0x7 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T1_END_PRD___POR 0x6 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T2_START_PRD___POR 0x9 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T2_END_PRD___POR 0x2 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T3_START_PRD___POR 0x9 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T3_END_PRD___POR 0x2 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T0_START_PRD___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T0_START_PRD___S 28 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T0_END_PRD___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T0_END_PRD___S 24 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T1_START_PRD___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T1_START_PRD___S 20 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T1_END_PRD___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T1_END_PRD___S 16 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T2_START_PRD___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T2_START_PRD___S 12 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T2_END_PRD___M 0x00000F00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T2_END_PRD___S 8 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T3_START_PRD___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T3_START_PRD___S 4 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T3_END_PRD___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0__TX_T3_END_PRD___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_STAGGER_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0 (0x005F8028) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0___POR 0x00004142 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T0_START_PRD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T0_END_PRD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T1_START_PRD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T1_END_PRD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T2_START_PRD___POR 0x4 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T2_END_PRD___POR 0x1 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T3_START_PRD___POR 0x4 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T3_END_PRD___POR 0x2 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T0_START_PRD___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T0_START_PRD___S 28 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T0_END_PRD___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T0_END_PRD___S 24 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T1_START_PRD___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T1_START_PRD___S 20 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T1_END_PRD___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T1_END_PRD___S 16 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T2_START_PRD___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T2_START_PRD___S 12 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T2_END_PRD___M 0x00000F00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T2_END_PRD___S 8 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T3_START_PRD___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T3_START_PRD___S 4 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T3_END_PRD___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0__RX_T3_END_PRD___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_STAGGER_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_TIMER_0 (0x005F802C) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_TIMER_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_TIMER_0___POR 0x20000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_TIMER_0__LNA_FC_PRD___POR 0x1 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_TIMER_0__LNA_FC_PRD___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_TIMER_0__LNA_FC_PRD___S 29 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_TIMER_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_TIMER_0___S 29 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_XFEM_0 (0x005F8030) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_XFEM_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_XFEM_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_XFEM_0__ZZZ_SPARE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_XFEM_0__ZZZ_SPARE___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_XFEM_0__ZZZ_SPARE___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_XFEM_0___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_XFEM_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_SPARE_0 (0x005F8034) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_SPARE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_SPARE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_SPARE_0__D_CHAIN_SPARE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_SPARE_0__D_CHAIN_SPARE_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_SPARE_0__D_CHAIN_SPARE_0___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_SPARE_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_SPARE_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_SPARE_1 (0x005F8038) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_SPARE_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_SPARE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_SPARE_1__D_CHAIN_SPARE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_SPARE_1__D_CHAIN_SPARE_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_SPARE_1__D_CHAIN_SPARE_1___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_SPARE_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_SPARE_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_COEX_GAIN_CFG (0x005F803C) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_COEX_GAIN_CFG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_COEX_GAIN_CFG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_COEX_GAIN_CFG__COEX_LNA_GAIN_FREEZE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_COEX_GAIN_CFG__COEX_LNA_GAIN_FREEZE___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_COEX_GAIN_CFG__COEX_LNA_GAIN_FREEZE___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_COEX_GAIN_CFG___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_COEX_GAIN_CFG___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_2 (0x005F8040) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_2__COEX_XLNA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_2__COEX_LNA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_2__COEX_XLNA_GAIN___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_2__COEX_XLNA_GAIN___S 3 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_2__COEX_LNA_GAIN___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_2__COEX_LNA_GAIN___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_2___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_PHY_2___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0 (0x005F8044) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0___POR 0x09200000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__WL_ISEL_IC___POR 0x4 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__WL_ISEL_IR___POR 0x4 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__WL_ISEL_ICPT___POR 0x4 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__D_IC_25U_TEST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__D_IR_25U_TEST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__D_ICPT_25U_TEST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__WL_ISEL_IC___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__WL_ISEL_IC___S 25 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__WL_ISEL_IR___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__WL_ISEL_IR___S 22 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__WL_ISEL_ICPT___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__WL_ISEL_ICPT___S 19 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__D_IC_25U_TEST_EN___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__D_IC_25U_TEST_EN___S 2 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__D_IR_25U_TEST_EN___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__D_IR_25U_TEST_EN___S 1 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__D_ICPT_25U_TEST_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0__D_ICPT_25U_TEST_EN___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0___M 0x0FF80007 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_MC_ISEL_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_ADC_ATEST (0x005F8048) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_ADC_ATEST___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_ADC_ATEST___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_ADC_ATEST__D_ATEST_EN_ADC_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_ADC_ATEST__D_ATEST_EN_ADC_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_ADC_ATEST__D_ATEST_EN_ADC_I___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_ADC_ATEST__D_ATEST_EN_ADC_I___S 1 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_ADC_ATEST__D_ATEST_EN_ADC_Q___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_ADC_ATEST__D_ATEST_EN_ADC_Q___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_ADC_ATEST___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_ADC_ATEST___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_0 (0x005F8080) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_0___POR 0x005078A0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_REGULAR___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_LG___POR 0x50 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_VLG___POR 0x78 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_COEX___POR 0xA0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_REGULAR___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_REGULAR___S 24 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_LG___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_LG___S 16 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_VLG___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_VLG___S 8 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_COEX___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_0__RX_GAIN_LUT_BASE_COEX___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1 (0x005F8084) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1___POR 0xC8F00000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_DPD___POR 0xC8 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_RXDCCAL___POR 0xF0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_SEL_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__TX_GAIN_LUT_SEL_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_DPD___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_DPD___S 24 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_RXDCCAL___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_BASE_RXDCCAL___S 16 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_SEL_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__RX_GAIN_LUT_SEL_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OV___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OV___S 7 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OVD___M 0x00000060 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__RX_DCOC_LUT_SEL_OVD___S 5 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__TX_GAIN_LUT_SEL_OVS___M 0x00000018 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__TX_GAIN_LUT_SEL_OVS___S 3 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OV___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OV___S 2 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OVD___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1__TX_DCOC_LUT_SEL_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1___M 0xFFFF03FF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RXGC_BASE_ADDR_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_GC_RAM_CONTROL (0x005F8088) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_GC_RAM_CONTROL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_GC_RAM_CONTROL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_GC_RAM_CONTROL__GC_MEM_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_GC_RAM_CONTROL__RXDCCAL_GAIN_TBL_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_GC_RAM_CONTROL__GC_MEM_SEL___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_GC_RAM_CONTROL__GC_MEM_SEL___S 15 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_GC_RAM_CONTROL__RXDCCAL_GAIN_TBL_SEL___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_GC_RAM_CONTROL__RXDCCAL_GAIN_TBL_SEL___S 14 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_GC_RAM_CONTROL___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_GC_RAM_CONTROL___S 14 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0 (0x005F808C) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__SLM_XLNA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__XLNA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__LNA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__GM_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__TIA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__BQ_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__SLM_XLNA_GAIN_OV___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__SLM_XLNA_GAIN_OV___S 5 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__XLNA_GAIN_OV___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__XLNA_GAIN_OV___S 4 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__LNA_GAIN_OV___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__LNA_GAIN_OV___S 3 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__GM_GAIN_OV___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__GM_GAIN_OV___S 2 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__TIA_GAIN_OV___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__TIA_GAIN_OV___S 1 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__BQ_GAIN_OV___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0__BQ_GAIN_OV___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1 (0x005F8090) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__XLNA_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__LNA_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__GM_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__TIA_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__SLM_XLNA_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__BQ_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__XLNA_GAIN_OVD___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__XLNA_GAIN_OVD___S 15 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__LNA_GAIN_OVD___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__LNA_GAIN_OVD___S 12 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__GM_GAIN_OVD___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__GM_GAIN_OVD___S 9 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__TIA_GAIN_OVD___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__TIA_GAIN_OVD___S 7 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__SLM_XLNA_GAIN_OVD___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__SLM_XLNA_GAIN_OVD___S 5 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__BQ_GAIN_OVD___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1__BQ_GAIN_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1___M 0x0000FFBF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_GAIN_OV_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0 (0x005F8094) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_I_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_Q_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_I_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_Q_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OV___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OV___S 25 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OV___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OV___S 24 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_I_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_I_OV___S 23 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_Q_OV___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_Q_OV___S 22 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OVD___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_I_OVD___S 20 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OVD___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RANGE_Q_OVD___S 18 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_I_OVD___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_I_OVD___S 9 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_Q_OVD___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0__RX_DCOC_RES_Q_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RX_DCOC_OV_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0 (0x005F8098) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__IPA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__DAC_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__TX_PWR_LV_LAA_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__TX_PWR_LV_N79_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__BBF_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__UPC_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__DA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__XPA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__IPA_GAIN_OV___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__IPA_GAIN_OV___S 7 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__DAC_GAIN_OV___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__DAC_GAIN_OV___S 6 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__TX_PWR_LV_LAA_OV___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__TX_PWR_LV_LAA_OV___S 5 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__TX_PWR_LV_N79_OV___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__TX_PWR_LV_N79_OV___S 4 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__BBF_GAIN_OV___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__BBF_GAIN_OV___S 3 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__UPC_GAIN_OV___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__UPC_GAIN_OV___S 2 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__DA_GAIN_OV___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__DA_GAIN_OV___S 1 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__XPA_GAIN_OV___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0__XPA_GAIN_OV___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1 (0x005F809C) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__IPA_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__DAC_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__TX_PWR_LV_LAA_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__TX_PWR_LV_N79_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__BBF_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__UPC_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__DA_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__XPA_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__IPA_GAIN_OVD___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__IPA_GAIN_OVD___S 23 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__DAC_GAIN_OVD___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__DAC_GAIN_OVD___S 20 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__TX_PWR_LV_LAA_OVD___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__TX_PWR_LV_LAA_OVD___S 19 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__TX_PWR_LV_N79_OVD___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__TX_PWR_LV_N79_OVD___S 18 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__BBF_GAIN_OVD___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__BBF_GAIN_OVD___S 12 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__UPC_GAIN_OVD___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__UPC_GAIN_OVD___S 9 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__DA_GAIN_OVD___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__DA_GAIN_OVD___S 4 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__XPA_GAIN_OVD___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1__XPA_GAIN_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_GAIN_OV_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0 (0x005F80A0) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_I_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_Q_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_I_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_Q_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_I_OV___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_I_OV___S 19 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_Q_OV___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_Q_OV___S 18 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_I_OVD___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_I_OVD___S 7 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_Q_OVD___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0__TX_DCOC_RES_Q_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0___M 0x000C3FFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_TX_DCOC_OV_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_IM2_0 (0x005F80A4) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_IM2_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_IM2_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_IM2_0__IM2_EN_MC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_IM2_0__IM2_EN_MC_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_IM2_0__IM2_EN_MC_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_IM2_0___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_IM2_0___S 30 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC (0x005F80A8) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC__RO_RX_DCOC_ADDR___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC__RO_RX_DCOC_RANGE_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC__RO_RX_DCOC_RANGE_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC__RO_RX_DCOC_RES_I___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC__RO_RX_DCOC_RES_Q___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC__RO_RX_DCOC_ADDR___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC__RO_RX_DCOC_ADDR___S 22 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC__RO_RX_DCOC_RANGE_I___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC__RO_RX_DCOC_RANGE_I___S 20 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC__RO_RX_DCOC_RANGE_Q___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC__RO_RX_DCOC_RANGE_Q___S 18 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC__RO_RX_DCOC_RES_I___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC__RO_RX_DCOC_RES_I___S 9 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC__RO_RX_DCOC_RES_Q___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC__RO_RX_DCOC_RES_Q___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_DCOC___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_DCOC (0x005F80AC) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_DCOC___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_DCOC___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_DCOC__RO_TX_DCOC_ADDR___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_DCOC__RO_TX_DCOC_RES_I___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_DCOC__RO_TX_DCOC_RES_Q___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_DCOC__RO_TX_DCOC_ADDR___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_DCOC__RO_TX_DCOC_ADDR___S 16 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_DCOC__RO_TX_DCOC_RES_I___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_DCOC__RO_TX_DCOC_RES_I___S 7 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_DCOC__RO_TX_DCOC_RES_Q___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_DCOC__RO_TX_DCOC_RES_Q___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_DCOC___M 0x007F3FFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_DCOC___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN (0x005F80B0) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_RX_GAIN_ADDR___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_XLNA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_LNA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_GM_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_TIA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_SLM_XLNA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_BQ_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_RX_GAIN_ADDR___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_RX_GAIN_ADDR___S 16 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_XLNA_GAIN___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_XLNA_GAIN___S 15 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_LNA_GAIN___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_LNA_GAIN___S 12 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_GM_GAIN___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_GM_GAIN___S 9 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_TIA_GAIN___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_TIA_GAIN___S 7 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_SLM_XLNA_GAIN___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_SLM_XLNA_GAIN___S 5 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_BQ_GAIN___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN__RO_BQ_GAIN___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN___M 0x00FFFFBF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_RX_GAIN___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0 (0x005F80B4) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_IPA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_DAC_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_TX_PWR_LV_LAA___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_TX_PWR_LV_N79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_BBF_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_UPC_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_DA_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_XPA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_IPA_GAIN___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_IPA_GAIN___S 23 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_DAC_GAIN___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_DAC_GAIN___S 20 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_TX_PWR_LV_LAA___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_TX_PWR_LV_LAA___S 19 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_TX_PWR_LV_N79___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_TX_PWR_LV_N79___S 18 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_BBF_GAIN___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_BBF_GAIN___S 12 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_UPC_GAIN___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_UPC_GAIN___S 9 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_DA_GAIN___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_DA_GAIN___S 4 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_XPA_GAIN___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0__RO_XPA_GAIN___S 0 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_1 (0x005F80B8) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_1__RO_TX_GAIN_ADDR___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_1__RO_RX_IDX___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_1__RO_TX_IDX___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_1__RO_TX_GAIN_ADDR___M 0x7F000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_1__RO_TX_GAIN_ADDR___S 24 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_1__RO_RX_IDX___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_1__RO_RX_IDX___S 16 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_1__RO_TX_IDX___M 0x00003F00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_1__RO_TX_IDX___S 8 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_1___M 0x7FFF3F00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_RO_TX_GAIN_1___S 8 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_0 (0x005F80C0) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_0__TX_DCOC_CAL_OFFSET_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_0__TX_DCOC_CAL_OFFSET_0___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_0__TX_DCOC_CAL_OFFSET_0___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_0___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_0___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_1 (0x005F80C4) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_1__TX_DCOC_CAL_OFFSET_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_1__TX_DCOC_CAL_OFFSET_1___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_1__TX_DCOC_CAL_OFFSET_1___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_1___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_1___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_2 (0x005F80C8) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_2__TX_DCOC_CAL_OFFSET_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_2__TX_DCOC_CAL_OFFSET_2___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_2__TX_DCOC_CAL_OFFSET_2___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_2___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_2___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_3 (0x005F80CC) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_3__TX_DCOC_CAL_OFFSET_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_3__TX_DCOC_CAL_OFFSET_3___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_3__TX_DCOC_CAL_OFFSET_3___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_3___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_3___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_4 (0x005F80D0) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_4__TX_DCOC_CAL_OFFSET_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_4__TX_DCOC_CAL_OFFSET_4___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_4__TX_DCOC_CAL_OFFSET_4___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_4___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_4___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_5 (0x005F80D4) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_5__TX_DCOC_CAL_OFFSET_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_5__TX_DCOC_CAL_OFFSET_5___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_5__TX_DCOC_CAL_OFFSET_5___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_5___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_5___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_6 (0x005F80D8) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_6__TX_DCOC_CAL_OFFSET_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_6__TX_DCOC_CAL_OFFSET_6___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_6__TX_DCOC_CAL_OFFSET_6___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_6___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_6___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_7 (0x005F80DC) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_7__TX_DCOC_CAL_OFFSET_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_7__TX_DCOC_CAL_OFFSET_7___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_7__TX_DCOC_CAL_OFFSET_7___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_7___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_7___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_8 (0x005F80E0) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_8__TX_DCOC_CAL_OFFSET_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_8__TX_DCOC_CAL_OFFSET_8___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_8__TX_DCOC_CAL_OFFSET_8___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_8___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_8___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_9 (0x005F80E4) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_9__TX_DCOC_CAL_OFFSET_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_9__TX_DCOC_CAL_OFFSET_9___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_9__TX_DCOC_CAL_OFFSET_9___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_9___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_9___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_10 (0x005F80E8) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_10__TX_DCOC_CAL_OFFSET_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_10__TX_DCOC_CAL_OFFSET_10___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_10__TX_DCOC_CAL_OFFSET_10___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_10___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_10___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_11 (0x005F80EC) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_11__TX_DCOC_CAL_OFFSET_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_11__TX_DCOC_CAL_OFFSET_11___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_11__TX_DCOC_CAL_OFFSET_11___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_11___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_11___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_12 (0x005F80F0) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_12__TX_DCOC_CAL_OFFSET_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_12__TX_DCOC_CAL_OFFSET_12___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_12__TX_DCOC_CAL_OFFSET_12___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_12___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_12___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_13 (0x005F80F4) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_13__TX_DCOC_CAL_OFFSET_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_13__TX_DCOC_CAL_OFFSET_13___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_13__TX_DCOC_CAL_OFFSET_13___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_13___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_13___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_14 (0x005F80F8) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_14__TX_DCOC_CAL_OFFSET_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_14__TX_DCOC_CAL_OFFSET_14___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_14__TX_DCOC_CAL_OFFSET_14___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_14___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_14___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_15 (0x005F80FC) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_15__TX_DCOC_CAL_OFFSET_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_15__TX_DCOC_CAL_OFFSET_15___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_15__TX_DCOC_CAL_OFFSET_15___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_15___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_15___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_16 (0x005F8100) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_16___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_16__TX_DCOC_CAL_OFFSET_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_16__TX_DCOC_CAL_OFFSET_16___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_16__TX_DCOC_CAL_OFFSET_16___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_16___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_16___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_17 (0x005F8104) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_17___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_17__TX_DCOC_CAL_OFFSET_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_17__TX_DCOC_CAL_OFFSET_17___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_17__TX_DCOC_CAL_OFFSET_17___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_17___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_17___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_18 (0x005F8108) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_18___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_18__TX_DCOC_CAL_OFFSET_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_18__TX_DCOC_CAL_OFFSET_18___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_18__TX_DCOC_CAL_OFFSET_18___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_18___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_18___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_19 (0x005F810C) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_19___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_19__TX_DCOC_CAL_OFFSET_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_19__TX_DCOC_CAL_OFFSET_19___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_19__TX_DCOC_CAL_OFFSET_19___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_19___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_19___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_20 (0x005F8110) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_20___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_20__TX_DCOC_CAL_OFFSET_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_20__TX_DCOC_CAL_OFFSET_20___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_20__TX_DCOC_CAL_OFFSET_20___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_20___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_20___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_21 (0x005F8114) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_21___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_21__TX_DCOC_CAL_OFFSET_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_21__TX_DCOC_CAL_OFFSET_21___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_21__TX_DCOC_CAL_OFFSET_21___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_21___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_21___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_22 (0x005F8118) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_22___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_22__TX_DCOC_CAL_OFFSET_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_22__TX_DCOC_CAL_OFFSET_22___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_22__TX_DCOC_CAL_OFFSET_22___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_22___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_22___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_23 (0x005F811C) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_23___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_23__TX_DCOC_CAL_OFFSET_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_23__TX_DCOC_CAL_OFFSET_23___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_23__TX_DCOC_CAL_OFFSET_23___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_23___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_23___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_24 (0x005F8120) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_24___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_24__TX_DCOC_CAL_OFFSET_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_24__TX_DCOC_CAL_OFFSET_24___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_24__TX_DCOC_CAL_OFFSET_24___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_24___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_24___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_25 (0x005F8124) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_25___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_25__TX_DCOC_CAL_OFFSET_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_25__TX_DCOC_CAL_OFFSET_25___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_25__TX_DCOC_CAL_OFFSET_25___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_25___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_25___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_26 (0x005F8128) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_26___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_26__TX_DCOC_CAL_OFFSET_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_26__TX_DCOC_CAL_OFFSET_26___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_26__TX_DCOC_CAL_OFFSET_26___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_26___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_26___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_27 (0x005F812C) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_27___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_27__TX_DCOC_CAL_OFFSET_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_27__TX_DCOC_CAL_OFFSET_27___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_27__TX_DCOC_CAL_OFFSET_27___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_27___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_27___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_28 (0x005F8130) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_28___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_28__TX_DCOC_CAL_OFFSET_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_28__TX_DCOC_CAL_OFFSET_28___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_28__TX_DCOC_CAL_OFFSET_28___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_28___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_28___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_29 (0x005F8134) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_29___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_29__TX_DCOC_CAL_OFFSET_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_29__TX_DCOC_CAL_OFFSET_29___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_29__TX_DCOC_CAL_OFFSET_29___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_29___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_29___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_30 (0x005F8138) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_30___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_30__TX_DCOC_CAL_OFFSET_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_30__TX_DCOC_CAL_OFFSET_30___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_30__TX_DCOC_CAL_OFFSET_30___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_30___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_30___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_31 (0x005F813C) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_31___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_31__TX_DCOC_CAL_OFFSET_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_31__TX_DCOC_CAL_OFFSET_31___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_31__TX_DCOC_CAL_OFFSET_31___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_31___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_31___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_32 (0x005F8140) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_32___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_32___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_32__TX_DCOC_CAL_OFFSET_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_32__TX_DCOC_CAL_OFFSET_32___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_32__TX_DCOC_CAL_OFFSET_32___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_32___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_32___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_33 (0x005F8144) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_33___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_33___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_33__TX_DCOC_CAL_OFFSET_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_33__TX_DCOC_CAL_OFFSET_33___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_33__TX_DCOC_CAL_OFFSET_33___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_33___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_33___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_34 (0x005F8148) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_34___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_34___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_34__TX_DCOC_CAL_OFFSET_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_34__TX_DCOC_CAL_OFFSET_34___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_34__TX_DCOC_CAL_OFFSET_34___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_34___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_34___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_35 (0x005F814C) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_35___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_35___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_35__TX_DCOC_CAL_OFFSET_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_35__TX_DCOC_CAL_OFFSET_35___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_35__TX_DCOC_CAL_OFFSET_35___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_35___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_35___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_36 (0x005F8150) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_36___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_36___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_36__TX_DCOC_CAL_OFFSET_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_36__TX_DCOC_CAL_OFFSET_36___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_36__TX_DCOC_CAL_OFFSET_36___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_36___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_36___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_37 (0x005F8154) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_37___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_37___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_37__TX_DCOC_CAL_OFFSET_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_37__TX_DCOC_CAL_OFFSET_37___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_37__TX_DCOC_CAL_OFFSET_37___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_37___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_37___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_38 (0x005F8158) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_38___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_38___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_38__TX_DCOC_CAL_OFFSET_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_38__TX_DCOC_CAL_OFFSET_38___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_38__TX_DCOC_CAL_OFFSET_38___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_38___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_38___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_39 (0x005F815C) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_39___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_39___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_39__TX_DCOC_CAL_OFFSET_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_39__TX_DCOC_CAL_OFFSET_39___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_39__TX_DCOC_CAL_OFFSET_39___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_39___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_39___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_40 (0x005F8160) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_40___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_40___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_40__TX_DCOC_CAL_OFFSET_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_40__TX_DCOC_CAL_OFFSET_40___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_40__TX_DCOC_CAL_OFFSET_40___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_40___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_40___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_41 (0x005F8164) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_41___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_41___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_41__TX_DCOC_CAL_OFFSET_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_41__TX_DCOC_CAL_OFFSET_41___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_41__TX_DCOC_CAL_OFFSET_41___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_41___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_41___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_42 (0x005F8168) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_42___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_42___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_42__TX_DCOC_CAL_OFFSET_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_42__TX_DCOC_CAL_OFFSET_42___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_42__TX_DCOC_CAL_OFFSET_42___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_42___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_42___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_43 (0x005F816C) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_43___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_43___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_43__TX_DCOC_CAL_OFFSET_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_43__TX_DCOC_CAL_OFFSET_43___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_43__TX_DCOC_CAL_OFFSET_43___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_43___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_43___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_44 (0x005F8170) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_44___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_44___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_44__TX_DCOC_CAL_OFFSET_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_44__TX_DCOC_CAL_OFFSET_44___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_44__TX_DCOC_CAL_OFFSET_44___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_44___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_44___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_45 (0x005F8174) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_45___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_45___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_45__TX_DCOC_CAL_OFFSET_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_45__TX_DCOC_CAL_OFFSET_45___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_45__TX_DCOC_CAL_OFFSET_45___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_45___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_45___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_46 (0x005F8178) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_46___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_46___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_46__TX_DCOC_CAL_OFFSET_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_46__TX_DCOC_CAL_OFFSET_46___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_46__TX_DCOC_CAL_OFFSET_46___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_46___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_46___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_47 (0x005F817C) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_47___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_47___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_47__TX_DCOC_CAL_OFFSET_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_47__TX_DCOC_CAL_OFFSET_47___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_47__TX_DCOC_CAL_OFFSET_47___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_47___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_47___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_48 (0x005F8180) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_48___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_48___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_48__TX_DCOC_CAL_OFFSET_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_48__TX_DCOC_CAL_OFFSET_48___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_48__TX_DCOC_CAL_OFFSET_48___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_48___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_48___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_49 (0x005F8184) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_49___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_49___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_49__TX_DCOC_CAL_OFFSET_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_49__TX_DCOC_CAL_OFFSET_49___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_49__TX_DCOC_CAL_OFFSET_49___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_49___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_49___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_50 (0x005F8188) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_50___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_50___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_50__TX_DCOC_CAL_OFFSET_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_50__TX_DCOC_CAL_OFFSET_50___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_50__TX_DCOC_CAL_OFFSET_50___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_50___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_50___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_51 (0x005F818C) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_51___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_51___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_51__TX_DCOC_CAL_OFFSET_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_51__TX_DCOC_CAL_OFFSET_51___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_51__TX_DCOC_CAL_OFFSET_51___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_51___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_51___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_52 (0x005F8190) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_52___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_52___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_52__TX_DCOC_CAL_OFFSET_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_52__TX_DCOC_CAL_OFFSET_52___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_52__TX_DCOC_CAL_OFFSET_52___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_52___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_52___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_53 (0x005F8194) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_53___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_53___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_53__TX_DCOC_CAL_OFFSET_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_53__TX_DCOC_CAL_OFFSET_53___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_53__TX_DCOC_CAL_OFFSET_53___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_53___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_53___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_54 (0x005F8198) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_54___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_54___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_54__TX_DCOC_CAL_OFFSET_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_54__TX_DCOC_CAL_OFFSET_54___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_54__TX_DCOC_CAL_OFFSET_54___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_54___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_54___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_55 (0x005F819C) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_55___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_55___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_55__TX_DCOC_CAL_OFFSET_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_55__TX_DCOC_CAL_OFFSET_55___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_55__TX_DCOC_CAL_OFFSET_55___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_55___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_55___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_56 (0x005F81A0) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_56___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_56___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_56__TX_DCOC_CAL_OFFSET_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_56__TX_DCOC_CAL_OFFSET_56___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_56__TX_DCOC_CAL_OFFSET_56___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_56___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_56___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_57 (0x005F81A4) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_57___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_57___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_57__TX_DCOC_CAL_OFFSET_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_57__TX_DCOC_CAL_OFFSET_57___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_57__TX_DCOC_CAL_OFFSET_57___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_57___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_57___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_58 (0x005F81A8) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_58___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_58___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_58__TX_DCOC_CAL_OFFSET_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_58__TX_DCOC_CAL_OFFSET_58___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_58__TX_DCOC_CAL_OFFSET_58___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_58___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_58___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_59 (0x005F81AC) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_59___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_59___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_59__TX_DCOC_CAL_OFFSET_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_59__TX_DCOC_CAL_OFFSET_59___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_59__TX_DCOC_CAL_OFFSET_59___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_59___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_59___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_60 (0x005F81B0) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_60___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_60___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_60__TX_DCOC_CAL_OFFSET_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_60__TX_DCOC_CAL_OFFSET_60___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_60__TX_DCOC_CAL_OFFSET_60___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_60___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_60___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_61 (0x005F81B4) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_61___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_61___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_61__TX_DCOC_CAL_OFFSET_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_61__TX_DCOC_CAL_OFFSET_61___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_61__TX_DCOC_CAL_OFFSET_61___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_61___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_61___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_62 (0x005F81B8) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_62___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_62___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_62__TX_DCOC_CAL_OFFSET_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_62__TX_DCOC_CAL_OFFSET_62___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_62__TX_DCOC_CAL_OFFSET_62___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_62___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_62___S 26 + +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_63 (0x005F81BC) +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_63___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_63___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_63__TX_DCOC_CAL_OFFSET_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_63__TX_DCOC_CAL_OFFSET_63___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_63__TX_DCOC_CAL_OFFSET_63___S 26 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_63___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_MC_5G_CH1_LUT_63___S 26 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL (0x005F8400) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL__TIA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL__TIA_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL__BQ_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL__BQ_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL__TIA_GAIN_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL__TIA_GAIN_OV___S 31 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL__TIA_GAIN_OVD___M 0x60000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL__TIA_GAIN_OVD___S 29 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL__BQ_GAIN_OV___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL__BQ_GAIN_OV___S 28 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL__BQ_GAIN_OVD___M 0x0F800000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL__BQ_GAIN_OVD___S 23 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_LUT_IDX_SEL___S 23 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB_CFG (0x005F8404) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB_CFG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB_CFG___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB_CFG__DCOCBB_FORMAT___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB_CFG__DCOCBB_FORMAT___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB_CFG__DCOCBB_FORMAT___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB_CFG___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB_CFG___S 30 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB (0x005F8408) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RANGE_I_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RANGE_Q_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RES_I_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RES_Q_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RANGE_I_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RANGE_Q_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RES_I_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RES_Q_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RANGE_I_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RANGE_I_OV___S 31 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RANGE_Q_OV___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RANGE_Q_OV___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RES_I_OV___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RES_I_OV___S 29 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RES_Q_OV___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RES_Q_OV___S 28 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RANGE_I_OVD___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RANGE_I_OVD___S 26 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RANGE_Q_OVD___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RANGE_Q_OVD___S 24 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RES_I_OVD___M 0x00FF8000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RES_I_OVD___S 15 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RES_Q_OVD___M 0x00007FC0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB__DCOCBB_RES_Q_OVD___S 6 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB___M 0xFFFFFFC0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DCOCBB___S 6 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC (0x005F840C) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC___POR 0x92492400 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_TIA_BW___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_BW___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_CC1ADJ___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_CC2ADJ___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_ZR1___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_ZR2___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_SELQ___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BOOST_BQ___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_TIA_BW___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_TIA_BW___S 29 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_BW___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_BW___S 26 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_CC1ADJ___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_CC1ADJ___S 23 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_CC2ADJ___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_CC2ADJ___S 20 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_ZR1___M 0x000E0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_ZR1___S 17 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_ZR2___M 0x0001C000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_ZR2___S 14 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_SELQ___M 0x00003800 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BQ_SELQ___S 11 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BOOST_BQ___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC__D_BOOST_BQ___S 10 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_CH_BW_AC___S 10 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0 (0x005F8410) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0___POR 0x87CCD234 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_CCADJ0___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_CFBCAL_0___POR 0x03E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_ICQADJ0___POR 0x6 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_VCMINTADJ0___POR 0x6 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_ISEL_IR25_IP0___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_ISEL_IC25_OP0___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_ISEL_OP_OS0___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_ISEL_IPTAT25_OP0___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_CCADJ0___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_CCADJ0___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_CFBCAL_0___M 0x3FE00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_CFBCAL_0___S 21 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_ICQADJ0___M 0x001E0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_ICQADJ0___S 17 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_VCMINTADJ0___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_VCMINTADJ0___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_ISEL_IR25_IP0___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_ISEL_IR25_IP0___S 10 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_ISEL_IC25_OP0___M 0x00000380 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_ISEL_IC25_OP0___S 7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_ISEL_OP_OS0___M 0x00000070 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_ISEL_OP_OS0___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_ISEL_IPTAT25_OP0___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0__TIA_ISEL_IPTAT25_OP0___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_0___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1 (0x005F8414) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1___POR 0x07CCD234 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_CCADJ1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_CFBCAL_1___POR 0x03E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_ICQADJ1___POR 0x6 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_VCMINTADJ1___POR 0x6 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_ISEL_IR25_IP1___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_ISEL_IC25_OP1___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_ISEL_OP_OS1___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_ISEL_IPTAT25_OP1___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_CCADJ1___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_CCADJ1___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_CFBCAL_1___M 0x3FE00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_CFBCAL_1___S 21 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_ICQADJ1___M 0x001E0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_ICQADJ1___S 17 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_VCMINTADJ1___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_VCMINTADJ1___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_ISEL_IR25_IP1___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_ISEL_IR25_IP1___S 10 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_ISEL_IC25_OP1___M 0x00000380 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_ISEL_IC25_OP1___S 7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_ISEL_OP_OS1___M 0x00000070 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_ISEL_OP_OS1___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_ISEL_IPTAT25_OP1___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1__TIA_ISEL_IPTAT25_OP1___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_1___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2 (0x005F8418) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2___POR 0x07CCD234 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_CCADJ2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_CFBCAL_2___POR 0x03E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_ICQADJ2___POR 0x6 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_VCMINTADJ2___POR 0x6 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_ISEL_IR25_IP2___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_ISEL_IC25_OP2___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_ISEL_OP_OS2___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_ISEL_IPTAT25_OP2___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_CCADJ2___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_CCADJ2___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_CFBCAL_2___M 0x3FE00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_CFBCAL_2___S 21 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_ICQADJ2___M 0x001E0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_ICQADJ2___S 17 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_VCMINTADJ2___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_VCMINTADJ2___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_ISEL_IR25_IP2___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_ISEL_IR25_IP2___S 10 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_ISEL_IC25_OP2___M 0x00000380 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_ISEL_IC25_OP2___S 7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_ISEL_OP_OS2___M 0x00000070 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_ISEL_OP_OS2___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_ISEL_IPTAT25_OP2___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2__TIA_ISEL_IPTAT25_OP2___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_2___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3 (0x005F841C) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3___POR 0x07C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_CCADJ3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_CFBCAL_3___POR 0x03E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_ICQADJ3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_VCMINTADJ3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_ISEL_IR25_IP3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_ISEL_IC25_OP3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_ISEL_OP_OS3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_ISEL_IPTAT25_OP3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_CCADJ3___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_CCADJ3___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_CFBCAL_3___M 0x3FE00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_CFBCAL_3___S 21 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_ICQADJ3___M 0x001E0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_ICQADJ3___S 17 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_VCMINTADJ3___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_VCMINTADJ3___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_ISEL_IR25_IP3___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_ISEL_IR25_IP3___S 10 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_ISEL_IC25_OP3___M 0x00000380 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_ISEL_IC25_OP3___S 7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_ISEL_OP_OS3___M 0x00000070 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_ISEL_OP_OS3___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_ISEL_IPTAT25_OP3___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3__TIA_ISEL_IPTAT25_OP3___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_3___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0 (0x005F8420) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0___POR 0x7EC8AF76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_CFBCAL_0___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_ISEL_OP_OS_0___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_CIN_CT_0___POR 0x045 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_ISEL_IC25_IP_0___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_ISEL_IC25_OP_0___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_ISEL_IPTAT25_OP_0___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_CFBCAL_0___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_CFBCAL_0___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_ISEL_OP_OS_0___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_ISEL_OP_OS_0___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_CIN_CT_0___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_CIN_CT_0___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_ISEL_IC25_IP_0___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_ISEL_IC25_IP_0___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_ISEL_IC25_OP_0___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_ISEL_IC25_OP_0___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_ISEL_IPTAT25_OP_0___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0__BQ_ISEL_IPTAT25_OP_0___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_0___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1 (0x005F8424) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1___POR 0x7EC9CF76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_CFBCAL_1___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_ISEL_OP_OS_1___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_CIN_CT_1___POR 0x04E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_ISEL_IC25_IP_1___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_ISEL_IC25_OP_1___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_ISEL_IPTAT25_OP_1___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_CFBCAL_1___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_CFBCAL_1___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_ISEL_OP_OS_1___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_ISEL_OP_OS_1___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_CIN_CT_1___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_CIN_CT_1___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_ISEL_IC25_IP_1___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_ISEL_IC25_IP_1___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_ISEL_IC25_OP_1___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_ISEL_IC25_OP_1___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_ISEL_IPTAT25_OP_1___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1__BQ_ISEL_IPTAT25_OP_1___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_1___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2 (0x005F8428) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2___POR 0x7ECAEF76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_CFBCAL_2___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_ISEL_OP_OS_2___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_CIN_CT_2___POR 0x057 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_ISEL_IC25_IP_2___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_ISEL_IC25_OP_2___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_ISEL_IPTAT25_OP_2___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_CFBCAL_2___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_CFBCAL_2___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_ISEL_OP_OS_2___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_ISEL_OP_OS_2___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_CIN_CT_2___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_CIN_CT_2___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_ISEL_IC25_IP_2___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_ISEL_IC25_IP_2___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_ISEL_IC25_OP_2___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_ISEL_IC25_OP_2___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_ISEL_IPTAT25_OP_2___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2__BQ_ISEL_IPTAT25_OP_2___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_2___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3 (0x005F842C) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3___POR 0x7ECC4F76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_CFBCAL_3___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_ISEL_OP_OS_3___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_CIN_CT_3___POR 0x062 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_ISEL_IC25_IP_3___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_ISEL_IC25_OP_3___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_ISEL_IPTAT25_OP_3___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_CFBCAL_3___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_CFBCAL_3___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_ISEL_OP_OS_3___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_ISEL_OP_OS_3___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_CIN_CT_3___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_CIN_CT_3___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_ISEL_IC25_IP_3___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_ISEL_IC25_IP_3___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_ISEL_IC25_OP_3___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_ISEL_IC25_OP_3___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_ISEL_IPTAT25_OP_3___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3__BQ_ISEL_IPTAT25_OP_3___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_3___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4 (0x005F8430) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4___POR 0x7ECDCF76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_CFBCAL_4___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_ISEL_OP_OS_4___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_CIN_CT_4___POR 0x06E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_ISEL_IC25_IP_4___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_ISEL_IC25_OP_4___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_ISEL_IPTAT25_OP_4___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_CFBCAL_4___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_CFBCAL_4___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_ISEL_OP_OS_4___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_ISEL_OP_OS_4___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_CIN_CT_4___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_CIN_CT_4___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_ISEL_IC25_IP_4___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_ISEL_IC25_IP_4___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_ISEL_IC25_OP_4___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_ISEL_IC25_OP_4___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_ISEL_IPTAT25_OP_4___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4__BQ_ISEL_IPTAT25_OP_4___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_4___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5 (0x005F8434) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5___POR 0x7ECF6F76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_CFBCAL_5___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_ISEL_OP_OS_5___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_CIN_CT_5___POR 0x07B +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_ISEL_IC25_IP_5___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_ISEL_IC25_OP_5___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_ISEL_IPTAT25_OP_5___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_CFBCAL_5___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_CFBCAL_5___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_ISEL_OP_OS_5___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_ISEL_OP_OS_5___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_CIN_CT_5___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_CIN_CT_5___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_ISEL_IC25_IP_5___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_ISEL_IC25_IP_5___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_ISEL_IC25_OP_5___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_ISEL_IC25_OP_5___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_ISEL_IPTAT25_OP_5___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5__BQ_ISEL_IPTAT25_OP_5___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_5___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6 (0x005F8438) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6___POR 0x7ED14F76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_CFBCAL_6___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_ISEL_OP_OS_6___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_CIN_CT_6___POR 0x08A +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_ISEL_IC25_IP_6___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_ISEL_IC25_OP_6___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_ISEL_IPTAT25_OP_6___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_CFBCAL_6___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_CFBCAL_6___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_ISEL_OP_OS_6___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_ISEL_OP_OS_6___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_CIN_CT_6___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_CIN_CT_6___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_ISEL_IC25_IP_6___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_ISEL_IC25_IP_6___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_ISEL_IC25_OP_6___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_ISEL_IC25_OP_6___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_ISEL_IPTAT25_OP_6___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6__BQ_ISEL_IPTAT25_OP_6___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_6___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7 (0x005F843C) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7___POR 0x7ED36F76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_CFBCAL_7___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_ISEL_OP_OS_7___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_CIN_CT_7___POR 0x09B +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_ISEL_IC25_IP_7___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_ISEL_IC25_OP_7___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_ISEL_IPTAT25_OP_7___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_CFBCAL_7___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_CFBCAL_7___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_ISEL_OP_OS_7___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_ISEL_OP_OS_7___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_CIN_CT_7___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_CIN_CT_7___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_ISEL_IC25_IP_7___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_ISEL_IC25_IP_7___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_ISEL_IC25_OP_7___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_ISEL_IC25_OP_7___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_ISEL_IPTAT25_OP_7___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7__BQ_ISEL_IPTAT25_OP_7___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_7___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8 (0x005F8440) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8___POR 0x7ED5CF76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_CFBCAL_8___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_ISEL_OP_OS_8___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_CIN_CT_8___POR 0x0AE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_ISEL_IC25_IP_8___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_ISEL_IC25_OP_8___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_ISEL_IPTAT25_OP_8___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_CFBCAL_8___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_CFBCAL_8___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_ISEL_OP_OS_8___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_ISEL_OP_OS_8___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_CIN_CT_8___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_CIN_CT_8___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_ISEL_IC25_IP_8___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_ISEL_IC25_IP_8___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_ISEL_IC25_OP_8___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_ISEL_IC25_OP_8___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_ISEL_IPTAT25_OP_8___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8__BQ_ISEL_IPTAT25_OP_8___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_8___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9 (0x005F8444) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9___POR 0x7ED5CF76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_CFBCAL_9___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_ISEL_OP_OS_9___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_CIN_CT_9___POR 0x0AE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_ISEL_IC25_IP_9___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_ISEL_IC25_OP_9___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_ISEL_IPTAT25_OP_9___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_CFBCAL_9___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_CFBCAL_9___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_ISEL_OP_OS_9___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_ISEL_OP_OS_9___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_CIN_CT_9___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_CIN_CT_9___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_ISEL_IC25_IP_9___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_ISEL_IC25_IP_9___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_ISEL_IC25_OP_9___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_ISEL_IC25_OP_9___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_ISEL_IPTAT25_OP_9___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9__BQ_ISEL_IPTAT25_OP_9___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_9___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10 (0x005F8448) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10___POR 0x7ED5CF76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_CFBCAL_10___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_ISEL_OP_OS_10___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_CIN_CT_10___POR 0x0AE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_ISEL_IC25_IP_10___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_ISEL_IC25_OP_10___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_ISEL_IPTAT25_OP_10___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_CFBCAL_10___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_CFBCAL_10___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_ISEL_OP_OS_10___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_ISEL_OP_OS_10___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_CIN_CT_10___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_CIN_CT_10___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_ISEL_IC25_IP_10___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_ISEL_IC25_IP_10___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_ISEL_IC25_OP_10___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_ISEL_IC25_OP_10___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_ISEL_IPTAT25_OP_10___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10__BQ_ISEL_IPTAT25_OP_10___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_10___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11 (0x005F844C) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11___POR 0x7ED5CF76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_CFBCAL_11___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_ISEL_OP_OS_11___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_CIN_CT_11___POR 0x0AE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_ISEL_IC25_IP_11___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_ISEL_IC25_OP_11___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_ISEL_IPTAT25_OP_11___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_CFBCAL_11___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_CFBCAL_11___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_ISEL_OP_OS_11___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_ISEL_OP_OS_11___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_CIN_CT_11___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_CIN_CT_11___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_ISEL_IC25_IP_11___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_ISEL_IC25_IP_11___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_ISEL_IC25_OP_11___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_ISEL_IC25_OP_11___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_ISEL_IPTAT25_OP_11___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11__BQ_ISEL_IPTAT25_OP_11___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_11___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12 (0x005F8450) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12___POR 0x7ED5CF76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_CFBCAL_12___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_ISEL_OP_OS_12___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_CIN_CT_12___POR 0x0AE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_ISEL_IC25_IP_12___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_ISEL_IC25_OP_12___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_ISEL_IPTAT25_OP_12___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_CFBCAL_12___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_CFBCAL_12___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_ISEL_OP_OS_12___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_ISEL_OP_OS_12___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_CIN_CT_12___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_CIN_CT_12___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_ISEL_IC25_IP_12___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_ISEL_IC25_IP_12___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_ISEL_IC25_OP_12___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_ISEL_IC25_OP_12___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_ISEL_IPTAT25_OP_12___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12__BQ_ISEL_IPTAT25_OP_12___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_12___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13 (0x005F8454) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13___POR 0x7ED5CF76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_CFBCAL_13___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_ISEL_OP_OS_13___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_CIN_CT_13___POR 0x0AE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_ISEL_IC25_IP_13___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_ISEL_IC25_OP_13___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_ISEL_IPTAT25_OP_13___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_CFBCAL_13___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_CFBCAL_13___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_ISEL_OP_OS_13___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_ISEL_OP_OS_13___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_CIN_CT_13___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_CIN_CT_13___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_ISEL_IC25_IP_13___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_ISEL_IC25_IP_13___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_ISEL_IC25_OP_13___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_ISEL_IC25_OP_13___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_ISEL_IPTAT25_OP_13___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13__BQ_ISEL_IPTAT25_OP_13___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_13___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14 (0x005F8458) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14___POR 0x7ED5CF76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_CFBCAL_14___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_ISEL_OP_OS_14___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_CIN_CT_14___POR 0x0AE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_ISEL_IC25_IP_14___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_ISEL_IC25_OP_14___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_ISEL_IPTAT25_OP_14___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_CFBCAL_14___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_CFBCAL_14___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_ISEL_OP_OS_14___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_ISEL_OP_OS_14___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_CIN_CT_14___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_CIN_CT_14___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_ISEL_IC25_IP_14___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_ISEL_IC25_IP_14___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_ISEL_IC25_OP_14___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_ISEL_IC25_OP_14___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_ISEL_IPTAT25_OP_14___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14__BQ_ISEL_IPTAT25_OP_14___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_14___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15 (0x005F845C) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15___POR 0x7ED5CF76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_CFBCAL_15___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_ISEL_OP_OS_15___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_CIN_CT_15___POR 0x0AE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_ISEL_IC25_IP_15___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_ISEL_IC25_OP_15___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_ISEL_IPTAT25_OP_15___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_CFBCAL_15___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_CFBCAL_15___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_ISEL_OP_OS_15___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_ISEL_OP_OS_15___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_CIN_CT_15___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_CIN_CT_15___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_ISEL_IC25_IP_15___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_ISEL_IC25_IP_15___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_ISEL_IC25_OP_15___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_ISEL_IC25_OP_15___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_ISEL_IPTAT25_OP_15___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15__BQ_ISEL_IPTAT25_OP_15___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_15___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16 (0x005F8460) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16___POR 0x7EC00F76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_CFBCAL_16___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_ISEL_OP_OS_16___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_CIN_CT_16___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_ISEL_IC25_IP_16___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_ISEL_IC25_OP_16___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_ISEL_IPTAT25_OP_16___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_CFBCAL_16___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_CFBCAL_16___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_ISEL_OP_OS_16___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_ISEL_OP_OS_16___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_CIN_CT_16___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_CIN_CT_16___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_ISEL_IC25_IP_16___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_ISEL_IC25_IP_16___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_ISEL_IC25_OP_16___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_ISEL_IC25_OP_16___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_ISEL_IPTAT25_OP_16___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16__BQ_ISEL_IPTAT25_OP_16___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_16___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17 (0x005F8464) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17___POR 0x7EC00F76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_CFBCAL_17___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_ISEL_OP_OS_17___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_CIN_CT_17___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_ISEL_IC25_IP_17___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_ISEL_IC25_OP_17___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_ISEL_IPTAT25_OP_17___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_CFBCAL_17___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_CFBCAL_17___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_ISEL_OP_OS_17___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_ISEL_OP_OS_17___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_CIN_CT_17___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_CIN_CT_17___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_ISEL_IC25_IP_17___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_ISEL_IC25_IP_17___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_ISEL_IC25_OP_17___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_ISEL_IC25_OP_17___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_ISEL_IPTAT25_OP_17___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17__BQ_ISEL_IPTAT25_OP_17___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_17___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18 (0x005F8468) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18___POR 0x7EC00F76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_CFBCAL_18___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_ISEL_OP_OS_18___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_CIN_CT_18___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_ISEL_IC25_IP_18___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_ISEL_IC25_OP_18___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_ISEL_IPTAT25_OP_18___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_CFBCAL_18___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_CFBCAL_18___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_ISEL_OP_OS_18___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_ISEL_OP_OS_18___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_CIN_CT_18___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_CIN_CT_18___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_ISEL_IC25_IP_18___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_ISEL_IC25_IP_18___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_ISEL_IC25_OP_18___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_ISEL_IC25_OP_18___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_ISEL_IPTAT25_OP_18___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18__BQ_ISEL_IPTAT25_OP_18___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_18___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19 (0x005F846C) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19___POR 0x7EC00F76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_CFBCAL_19___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_ISEL_OP_OS_19___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_CIN_CT_19___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_ISEL_IC25_IP_19___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_ISEL_IC25_OP_19___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_ISEL_IPTAT25_OP_19___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_CFBCAL_19___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_CFBCAL_19___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_ISEL_OP_OS_19___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_ISEL_OP_OS_19___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_CIN_CT_19___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_CIN_CT_19___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_ISEL_IC25_IP_19___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_ISEL_IC25_IP_19___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_ISEL_IC25_OP_19___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_ISEL_IC25_OP_19___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_ISEL_IPTAT25_OP_19___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19__BQ_ISEL_IPTAT25_OP_19___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_19___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20 (0x005F8470) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20___POR 0x7EC00F76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_CFBCAL_20___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_ISEL_OP_OS_20___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_CIN_CT_20___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_ISEL_IC25_IP_20___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_ISEL_IC25_OP_20___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_ISEL_IPTAT25_OP_20___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_CFBCAL_20___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_CFBCAL_20___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_ISEL_OP_OS_20___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_ISEL_OP_OS_20___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_CIN_CT_20___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_CIN_CT_20___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_ISEL_IC25_IP_20___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_ISEL_IC25_IP_20___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_ISEL_IC25_OP_20___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_ISEL_IC25_OP_20___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_ISEL_IPTAT25_OP_20___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20__BQ_ISEL_IPTAT25_OP_20___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_20___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21 (0x005F8474) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21___POR 0x7EC00F76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_CFBCAL_21___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_ISEL_OP_OS_21___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_CIN_CT_21___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_ISEL_IC25_IP_21___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_ISEL_IC25_OP_21___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_ISEL_IPTAT25_OP_21___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_CFBCAL_21___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_CFBCAL_21___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_ISEL_OP_OS_21___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_ISEL_OP_OS_21___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_CIN_CT_21___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_CIN_CT_21___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_ISEL_IC25_IP_21___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_ISEL_IC25_IP_21___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_ISEL_IC25_OP_21___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_ISEL_IC25_OP_21___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_ISEL_IPTAT25_OP_21___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21__BQ_ISEL_IPTAT25_OP_21___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_21___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22 (0x005F8478) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22___POR 0x7EC00F76 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_CFBCAL_22___POR 0x3F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_ISEL_OP_OS_22___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_CIN_CT_22___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_ISEL_IC25_IP_22___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_ISEL_IC25_OP_22___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_ISEL_IPTAT25_OP_22___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_CFBCAL_22___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_CFBCAL_22___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_ISEL_OP_OS_22___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_ISEL_OP_OS_22___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_CIN_CT_22___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_CIN_CT_22___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_ISEL_IC25_IP_22___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_ISEL_IC25_IP_22___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_ISEL_IC25_OP_22___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_ISEL_IC25_OP_22___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_ISEL_IPTAT25_OP_22___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22__BQ_ISEL_IPTAT25_OP_22___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_22___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_0 (0x005F847C) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_0__TIA_GAIN_CTRL_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_0__TIA_GAIN_CTRL_0___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_0__TIA_GAIN_CTRL_0___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_0___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_0___S 30 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_1 (0x005F8480) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_1___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_1__TIA_GAIN_CTRL_1___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_1__TIA_GAIN_CTRL_1___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_1__TIA_GAIN_CTRL_1___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_1___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_1___S 30 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_2 (0x005F8484) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_2___POR 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_2__TIA_GAIN_CTRL_2___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_2__TIA_GAIN_CTRL_2___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_2__TIA_GAIN_CTRL_2___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_2___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_2___S 30 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_3 (0x005F8488) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_3__TIA_GAIN_CTRL_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_3__TIA_GAIN_CTRL_3___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_3__TIA_GAIN_CTRL_3___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_3___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT0_3___S 30 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_0 (0x005F848C) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_0__BQ_GAIN_CTRL_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_0__BQ_GAIN_CTRL_0___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_0__BQ_GAIN_CTRL_0___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_0___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_0___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_1 (0x005F8490) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_1___POR 0x08000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_1__BQ_GAIN_CTRL_1___POR 0x01 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_1__BQ_GAIN_CTRL_1___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_1__BQ_GAIN_CTRL_1___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_1___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_1___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_2 (0x005F8494) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_2___POR 0x10000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_2__BQ_GAIN_CTRL_2___POR 0x02 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_2__BQ_GAIN_CTRL_2___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_2__BQ_GAIN_CTRL_2___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_2___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_2___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_3 (0x005F8498) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_3___POR 0x18000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_3__BQ_GAIN_CTRL_3___POR 0x03 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_3__BQ_GAIN_CTRL_3___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_3__BQ_GAIN_CTRL_3___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_3___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_3___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_4 (0x005F849C) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_4___POR 0x20000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_4__BQ_GAIN_CTRL_4___POR 0x04 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_4__BQ_GAIN_CTRL_4___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_4__BQ_GAIN_CTRL_4___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_4___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_4___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_5 (0x005F84A0) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_5___POR 0x28000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_5__BQ_GAIN_CTRL_5___POR 0x05 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_5__BQ_GAIN_CTRL_5___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_5__BQ_GAIN_CTRL_5___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_5___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_5___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_6 (0x005F84A4) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_6___POR 0x30000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_6__BQ_GAIN_CTRL_6___POR 0x06 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_6__BQ_GAIN_CTRL_6___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_6__BQ_GAIN_CTRL_6___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_6___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_6___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_7 (0x005F84A8) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_7___POR 0x38000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_7__BQ_GAIN_CTRL_7___POR 0x07 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_7__BQ_GAIN_CTRL_7___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_7__BQ_GAIN_CTRL_7___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_7___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_7___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_8 (0x005F84AC) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_8___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_8__BQ_GAIN_CTRL_8___POR 0x08 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_8__BQ_GAIN_CTRL_8___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_8__BQ_GAIN_CTRL_8___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_8___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_8___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_9 (0x005F84B0) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_9___POR 0x48000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_9__BQ_GAIN_CTRL_9___POR 0x09 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_9__BQ_GAIN_CTRL_9___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_9__BQ_GAIN_CTRL_9___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_9___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_9___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_10 (0x005F84B4) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_10___POR 0x50000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_10__BQ_GAIN_CTRL_10___POR 0x0A +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_10__BQ_GAIN_CTRL_10___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_10__BQ_GAIN_CTRL_10___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_10___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_10___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_11 (0x005F84B8) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_11___POR 0x58000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_11__BQ_GAIN_CTRL_11___POR 0x0B +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_11__BQ_GAIN_CTRL_11___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_11__BQ_GAIN_CTRL_11___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_11___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_11___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_12 (0x005F84BC) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_12___POR 0x60000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_12__BQ_GAIN_CTRL_12___POR 0x0C +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_12__BQ_GAIN_CTRL_12___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_12__BQ_GAIN_CTRL_12___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_12___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_12___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_13 (0x005F84C0) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_13___POR 0x68000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_13__BQ_GAIN_CTRL_13___POR 0x0D +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_13__BQ_GAIN_CTRL_13___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_13__BQ_GAIN_CTRL_13___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_13___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_13___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_14 (0x005F84C4) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_14___POR 0x70000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_14__BQ_GAIN_CTRL_14___POR 0x0E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_14__BQ_GAIN_CTRL_14___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_14__BQ_GAIN_CTRL_14___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_14___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_14___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_15 (0x005F84C8) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_15___POR 0x78000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_15__BQ_GAIN_CTRL_15___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_15__BQ_GAIN_CTRL_15___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_15__BQ_GAIN_CTRL_15___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_15___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_15___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_16 (0x005F84CC) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_16___POR 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_16__BQ_GAIN_CTRL_16___POR 0x10 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_16__BQ_GAIN_CTRL_16___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_16__BQ_GAIN_CTRL_16___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_16___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_16___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_17 (0x005F84D0) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_17___POR 0x88000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_17__BQ_GAIN_CTRL_17___POR 0x11 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_17__BQ_GAIN_CTRL_17___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_17__BQ_GAIN_CTRL_17___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_17___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_17___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_18 (0x005F84D4) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_18___POR 0x90000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_18__BQ_GAIN_CTRL_18___POR 0x12 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_18__BQ_GAIN_CTRL_18___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_18__BQ_GAIN_CTRL_18___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_18___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_18___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_19 (0x005F84D8) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_19___POR 0x98000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_19__BQ_GAIN_CTRL_19___POR 0x13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_19__BQ_GAIN_CTRL_19___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_19__BQ_GAIN_CTRL_19___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_19___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_19___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_20 (0x005F84DC) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_20___POR 0xA0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_20__BQ_GAIN_CTRL_20___POR 0x14 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_20__BQ_GAIN_CTRL_20___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_20__BQ_GAIN_CTRL_20___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_20___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_20___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_21 (0x005F84E0) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_21___POR 0xA8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_21__BQ_GAIN_CTRL_21___POR 0x15 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_21__BQ_GAIN_CTRL_21___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_21__BQ_GAIN_CTRL_21___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_21___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_21___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_22 (0x005F84E4) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_22___POR 0xB0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_22__BQ_GAIN_CTRL_22___POR 0x16 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_22__BQ_GAIN_CTRL_22___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_22__BQ_GAIN_CTRL_22___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_22___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT0_22___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0 (0x005F84E8) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CCADJ_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CCADJ_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CFBCAL_I_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CFBCAL_I_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CFBCAL_Q_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CFBCAL_Q_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_ICQADJ_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_ICQADJ_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CCADJ_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CCADJ_OV___S 31 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CCADJ_OVD___M 0x60000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CCADJ_OVD___S 29 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CFBCAL_I_OV___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CFBCAL_I_OV___S 28 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CFBCAL_I_OVD___M 0x0FF80000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CFBCAL_I_OVD___S 19 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CFBCAL_Q_OV___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CFBCAL_Q_OV___S 18 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CFBCAL_Q_OVD___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_CFBCAL_Q_OVD___S 9 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_ICQADJ_OV___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_ICQADJ_OV___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_ICQADJ_OVD___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0__TIA_ICQADJ_OVD___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0___M 0xFFFFFFF0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV0___S 4 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1 (0x005F84EC) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_VCMINTADJ_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_VCMINTADJ_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IR25_IP_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IR25_IP_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IC25_OP_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IC25_OP_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_OP_OS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_OP_OS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IPTAT25_OP_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IPTAT25_OP_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_GAIN_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_GAIN_CTRL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_VCMINTADJ_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_VCMINTADJ_OV___S 31 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_VCMINTADJ_OVD___M 0x78000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_VCMINTADJ_OVD___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IR25_IP_OV___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IR25_IP_OV___S 26 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IR25_IP_OVD___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IR25_IP_OVD___S 23 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IC25_OP_OV___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IC25_OP_OV___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IC25_OP_OVD___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IC25_OP_OVD___S 19 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_OP_OS_OV___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_OP_OS_OV___S 18 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_OP_OS_OVD___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_OP_OS_OVD___S 15 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IPTAT25_OP_OV___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IPTAT25_OP_OV___S 14 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IPTAT25_OP_OVD___M 0x00003800 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_ISEL_IPTAT25_OP_OVD___S 11 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_GAIN_CTRL_OV___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_GAIN_CTRL_OV___S 10 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_GAIN_CTRL_OVD___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1__TIA_GAIN_CTRL_OVD___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1___M 0xFFFFFF00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA_LUT_OV1___S 8 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0 (0x005F84F0) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_GAIN_CTRL_PDET_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_GAIN_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_GAIN_CTRL_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_ISEL_OP_OS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_ISEL_OP_OS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_CIN_CT_I_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_CIN_CT_I_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_CIN_CT_Q_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_CIN_CT_Q_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_GAIN_CTRL_PDET_OV___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_GAIN_CTRL_PDET_OV___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_GAIN_CTRL_OV___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_GAIN_CTRL_OV___S 29 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_GAIN_CTRL_OVD___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_GAIN_CTRL_OVD___S 24 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_ISEL_OP_OS_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_ISEL_OP_OS_OV___S 23 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_ISEL_OP_OS_OVD___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_ISEL_OP_OS_OVD___S 20 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_CIN_CT_I_OV___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_CIN_CT_I_OV___S 19 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_CIN_CT_I_OVD___M 0x0007FC00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_CIN_CT_I_OVD___S 10 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_CIN_CT_Q_OV___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_CIN_CT_Q_OV___S 9 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_CIN_CT_Q_OVD___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0__BQ_CIN_CT_Q_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0___M 0x7FFFFFFF +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV0___S 0 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1 (0x005F84F4) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IC25_IP_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IC25_IP_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IC25_OP_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IC25_OP_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IPTAT25_OP_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IPTAT25_OP_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_CFBCAL_I_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_CFBCAL_I_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_CFBCAL_Q_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_CFBCAL_Q_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IC25_IP_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IC25_IP_OV___S 31 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IC25_IP_OVD___M 0x7C000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IC25_IP_OVD___S 26 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IC25_OP_OV___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IC25_OP_OV___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IC25_OP_OVD___M 0x01E00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IC25_OP_OVD___S 21 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IPTAT25_OP_OV___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IPTAT25_OP_OV___S 20 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IPTAT25_OP_OVD___M 0x000E0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_ISEL_IPTAT25_OP_OVD___S 17 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_CFBCAL_I_OV___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_CFBCAL_I_OV___S 16 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_CFBCAL_I_OVD___M 0x0000FE00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_CFBCAL_I_OVD___S 9 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_CFBCAL_Q_OV___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_CFBCAL_Q_OV___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_CFBCAL_Q_OVD___M 0x000000FE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1__BQ_CFBCAL_Q_OVD___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ_LUT_OV1___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT_OV (0x005F84F8) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT_OV___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT_OV___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT_OV__TIA_SATDET_EN_I_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT_OV__TIA_SATDET_EN_Q_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT_OV__TIA_SATDET_EN_I_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT_OV__TIA_SATDET_EN_I_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT_OV__TIA_SATDET_EN_Q_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT_OV__TIA_SATDET_EN_Q_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT_OV___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT_OV___S 28 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0 (0x005F84FC) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__DCOC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__TIA_EN_I_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__TIA_EN_Q_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BQ_EN_I_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BQ_EN_Q_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__IM2_BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__IM2_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__IM2_OTA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BIAS_RTT_TIA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BIAS_RTT_BQ_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__TIA_EN_HSW_I_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__TIA_EN_HSW_Q_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BQ_EN_HSW_I_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BQ_EN_HSW_Q_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__TPC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BIAS_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BIAS_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__DCOC_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__DCOC_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__TIA_EN_I_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__TIA_EN_I_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__TIA_EN_Q_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__TIA_EN_Q_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BQ_EN_I_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BQ_EN_I_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BQ_EN_Q_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BQ_EN_Q_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__IM2_BIAS_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__IM2_BIAS_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__IM2_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__IM2_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__IM2_OTA_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__IM2_OTA_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BIAS_RTT_TIA_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BIAS_RTT_TIA_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BIAS_RTT_BQ_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BIAS_RTT_BQ_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__TIA_EN_HSW_I_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__TIA_EN_HSW_I_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__TIA_EN_HSW_Q_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__TIA_EN_HSW_Q_OVS___S 6 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BQ_EN_HSW_I_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BQ_EN_HSW_I_OVS___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BQ_EN_HSW_Q_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__BQ_EN_HSW_Q_OVS___S 2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__TPC_EN_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0__TPC_EN_OVS___S 0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_EN0___S 0 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_LUT_IDX (0x005F8500) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_LUT_IDX___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_LUT_IDX___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_LUT_IDX__RO_TIA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_LUT_IDX__RO_BQ_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_LUT_IDX__RO_TIA_GAIN___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_LUT_IDX__RO_TIA_GAIN___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_LUT_IDX__RO_BQ_GAIN___M 0x3E000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_LUT_IDX__RO_BQ_GAIN___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_LUT_IDX___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_LUT_IDX___S 25 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT0 (0x005F8504) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT0__RO_TIA_CCADJ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT0__RO_TIA_CFBCAL_I___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT0__RO_TIA_CFBCAL_Q___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT0__RO_TIA_ICQADJ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT0__RO_TIA_CCADJ___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT0__RO_TIA_CCADJ___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT0__RO_TIA_CFBCAL_I___M 0x3FE00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT0__RO_TIA_CFBCAL_I___S 21 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT0__RO_TIA_CFBCAL_Q___M 0x001FF000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT0__RO_TIA_CFBCAL_Q___S 12 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT0__RO_TIA_ICQADJ___M 0x00000F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT0__RO_TIA_ICQADJ___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT0___M 0xFFFFFF00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT0___S 8 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1 (0x005F8508) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_VCMINTADJ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_ISEL_IR25_IP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_ISEL_IC25_OP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_ISEL_OP_OS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_ISEL_IPTAT25_OP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_GAIN_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_VCMINTADJ___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_VCMINTADJ___S 28 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_ISEL_IR25_IP___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_ISEL_IR25_IP___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_ISEL_IC25_OP___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_ISEL_IC25_OP___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_ISEL_OP_OS___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_ISEL_OP_OS___S 19 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_ISEL_IPTAT25_OP___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_ISEL_IPTAT25_OP___S 16 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_GAIN_CTRL___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1__RO_TIA_GAIN_CTRL___S 14 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1___M 0xFFFFC000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_TIA_LUT1___S 14 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT0 (0x005F850C) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT0__RO_BQ_GAIN_CTRL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT0__RO_BQ_ISEL_OP_OS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT0__RO_BQ_CIN_CT_I___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT0__RO_BQ_CIN_CT_Q___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT0__RO_BQ_GAIN_CTRL___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT0__RO_BQ_GAIN_CTRL___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT0__RO_BQ_ISEL_OP_OS___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT0__RO_BQ_ISEL_OP_OS___S 24 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT0__RO_BQ_CIN_CT_I___M 0x00FF8000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT0__RO_BQ_CIN_CT_I___S 15 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT0__RO_BQ_CIN_CT_Q___M 0x00007FC0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT0__RO_BQ_CIN_CT_Q___S 6 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT0___M 0xFFFFFFC0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT0___S 6 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1 (0x005F8510) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1__RO_BQ_ISEL_IC25_IP___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1__RO_BQ_ISEL_IC25_OP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1__RO_BQ_ISEL_IPTAT25_OP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1__RO_BQ_CFBCAL_I___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1__RO_BQ_CFBCAL_Q___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1__RO_BQ_ISEL_IC25_IP___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1__RO_BQ_ISEL_IC25_IP___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1__RO_BQ_ISEL_IC25_OP___M 0x07800000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1__RO_BQ_ISEL_IC25_OP___S 23 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1__RO_BQ_ISEL_IPTAT25_OP___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1__RO_BQ_ISEL_IPTAT25_OP___S 20 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1__RO_BQ_CFBCAL_I___M 0x000FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1__RO_BQ_CFBCAL_I___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1__RO_BQ_CFBCAL_Q___M 0x00001FC0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1__RO_BQ_CFBCAL_Q___S 6 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1___M 0xFFFFFFC0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_BQ_LUT1___S 6 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_DCOCBB (0x005F8514) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_DCOCBB___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_DCOCBB___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_DCOCBB__RO_DCOCBB_RANGE_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_DCOCBB__RO_DCOCBB_RANGE_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_DCOCBB__RO_DCOCBB_RES_I___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_DCOCBB__RO_DCOCBB_RES_Q___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_DCOCBB__RO_DCOCBB_RANGE_I___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_DCOCBB__RO_DCOCBB_RANGE_I___S 20 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_DCOCBB__RO_DCOCBB_RANGE_Q___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_DCOCBB__RO_DCOCBB_RANGE_Q___S 18 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_DCOCBB__RO_DCOCBB_RES_I___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_DCOCBB__RO_DCOCBB_RES_I___S 9 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_DCOCBB__RO_DCOCBB_RES_Q___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_DCOCBB__RO_DCOCBB_RES_Q___S 0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_DCOCBB___M 0x003FFFFF +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RO_DCOCBB___S 0 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT (0x005F8518) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT___POR 0x58000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT__D_TIA_SATDET_LEVEL___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT__D_TIA_SATDET_BOOST_I___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT__D_TIA_SATDET_BOOST_Q___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT__D_TIA_SATDET_LEVEL___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT__D_TIA_SATDET_LEVEL___S 29 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT__D_TIA_SATDET_BOOST_I___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT__D_TIA_SATDET_BOOST_I___S 28 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT__D_TIA_SATDET_BOOST_Q___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT__D_TIA_SATDET_BOOST_Q___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SAT___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA (0x005F851C) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA___POR 0x37000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA__D_TIA_RMCAP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA__D_TIA_RFB_I___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA__D_TIA_RFB_Q___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA__D_TIA_VICMADJ___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA__D_TIA_RMCAP___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA__D_TIA_RMCAP___S 31 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA__D_TIA_RFB_I___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA__D_TIA_RFB_I___S 28 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA__D_TIA_RFB_Q___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA__D_TIA_RFB_Q___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA__D_TIA_VICMADJ___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA__D_TIA_VICMADJ___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TIA___S 22 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ (0x005F8520) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ___POR 0x20000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ__D_BQ_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ__D_BQ_VCM_SEL___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ__D_BQ_BYPASS___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ__D_BQ_BYPASS___S 31 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ__D_BQ_VCM_SEL___M 0x78000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ__D_BQ_VCM_SEL___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_BQ___S 27 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2 (0x005F8524) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_VCAL_DAC_I___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_VCAL_DAC_Q___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_CONT_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_CONT_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_RCTRL_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_RCTRL_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_VGF_MIX___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_TEST___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_VCAL_DAC_I___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_VCAL_DAC_I___S 24 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_VCAL_DAC_Q___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_VCAL_DAC_Q___S 16 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_CONT_I___M 0x0000E000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_CONT_I___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_CONT_Q___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_CONT_Q___S 10 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_RCTRL_I___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_RCTRL_I___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_RCTRL_Q___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_RCTRL_Q___S 6 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_VGF_MIX___M 0x00000030 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_VGF_MIX___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_TEST___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2__D_IM2_TEST___S 3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2___M 0xFFFFFFF8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_IM2___S 3 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0 (0x005F8528) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2A_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2B_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2C_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW4A_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW5_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW6A_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW6B_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW7_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2A_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2B_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2C_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW4A_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW5_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW6A_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW6B_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW7_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2A_I___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2A_I___S 31 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2B_I___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2B_I___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2C_I___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2C_I___S 29 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW4A_I___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW4A_I___S 28 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW5_I___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW5_I___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW6A_I___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW6A_I___S 26 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW6B_I___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW6B_I___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW7_I___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW7_I___S 24 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2A_Q___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2A_Q___S 23 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2B_Q___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2B_Q___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2C_Q___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW2C_Q___S 21 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW4A_Q___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW4A_Q___S 20 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW5_Q___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW5_Q___S 19 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW6A_Q___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW6A_Q___S 18 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW6B_Q___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW6B_Q___S 17 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW7_Q___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0__D_TSTBUF_SW7_Q___S 16 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER0___S 16 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1 (0x005F852C) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1___POR 0x80426300 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_RIN_CTRL___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_RFB_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_CFB_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_IN___POR 0x10 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_OUT___POR 0x9 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_ZR___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_CCADJ___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_OUT_PTAT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_RTT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_EN_HSW_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_EN_HSW_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_RIN_CTRL___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_RIN_CTRL___S 29 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_RFB_CTRL___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_RFB_CTRL___S 26 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_CFB_CTRL___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_CFB_CTRL___S 23 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_IN___M 0x007C0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_IN___S 18 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_OUT___M 0x0003C000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_OUT___S 14 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_ZR___M 0x00003800 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_ZR___S 11 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_CCADJ___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_CCADJ___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_OUT_PTAT___M 0x000000E0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_IBIAS_OUT_PTAT___S 5 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_RTT_EN___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_RTT_EN___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_EN_HSW_I___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_EN_HSW_I___S 3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_EN_HSW_Q___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1__D_TSTBUF_EN_HSW_Q___S 2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_RX_TEST_BUFFER1___S 2 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL (0x005F8530) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_ADC_VCM_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_TPC_PATH_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_TS_PATH_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_LPBKSEL_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_LPBKSEL_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_BLOCK_TEST_SEL_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_BLOCK_TEST_SEL_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_BIAS_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_ATB_CTRL_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_ATB_CTRL_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_ADC_VCM_SEL___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_ADC_VCM_SEL___S 31 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_TPC_PATH_EN___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_TPC_PATH_EN___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_TS_PATH_EN___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_TS_PATH_EN___S 29 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_LPBKSEL_I___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_LPBKSEL_I___S 28 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_LPBKSEL_Q___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_LPBKSEL_Q___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_BLOCK_TEST_SEL_I___M 0x06000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_BLOCK_TEST_SEL_I___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_BLOCK_TEST_SEL_Q___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_BLOCK_TEST_SEL_Q___S 23 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_BIAS_ATB_SEL___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_BIAS_ATB_SEL___S 20 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_ATB_CTRL_I___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_ATB_CTRL_I___S 18 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_ATB_CTRL_Q___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL__D_ATB_CTRL_Q___S 16 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_OTHER_ANALOG_CONTROL___S 16 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SPARE0 (0x005F8534) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SPARE0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SPARE0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SPARE0__D_RXBB_SPARE___POR 0x00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SPARE0__D_RXBB_SPARE___M 0x0003FFFF +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SPARE0__D_RXBB_SPARE___S 0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SPARE0___M 0x0003FFFF +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_SPARE0___S 0 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0 (0x005F8538) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0___POR 0xD8049248 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__TIA_BW_VDET___POR 0x6 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__TIA_BW_PDET___POR 0x6 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_BW_VDET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_BW_PDET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_CC1ADJ_VDET___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_CC1ADJ_PDET___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_CC2ADJ_VDET___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_CC2ADJ_PDET___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_ZR1_VDET___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_ZR1_PDET___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__TIA_BW_VDET___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__TIA_BW_VDET___S 29 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__TIA_BW_PDET___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__TIA_BW_PDET___S 26 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_BW_VDET___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_BW_VDET___S 23 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_BW_PDET___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_BW_PDET___S 20 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_CC1ADJ_VDET___M 0x000E0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_CC1ADJ_VDET___S 17 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_CC1ADJ_PDET___M 0x0001C000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_CC1ADJ_PDET___S 14 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_CC2ADJ_VDET___M 0x00003800 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_CC2ADJ_VDET___S 11 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_CC2ADJ_PDET___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_CC2ADJ_PDET___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_ZR1_VDET___M 0x000000E0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_ZR1_VDET___S 5 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_ZR1_PDET___M 0x0000001C +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0__BQ_ZR1_PDET___S 2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC0___S 2 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1 (0x005F853C) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1___POR 0x4800006C +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BQ_ZR2_VDET___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BQ_ZR2_PDET___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BQ_SELQ_VDET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BQ_SELQ_PDET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BOOST_BQ_VDET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BOOST_BQ_PDET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BQ_GAIN_CTRL_VDET___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__TIA_ISEL_OP_OS_VDET___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__TIA_ISEL_OP_OS_PDET___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BQ_ZR2_VDET___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BQ_ZR2_VDET___S 29 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BQ_ZR2_PDET___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BQ_ZR2_PDET___S 26 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BQ_SELQ_VDET___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BQ_SELQ_VDET___S 23 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BQ_SELQ_PDET___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BQ_SELQ_PDET___S 20 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BOOST_BQ_VDET___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BOOST_BQ_VDET___S 19 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BOOST_BQ_PDET___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BOOST_BQ_PDET___S 18 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BQ_GAIN_CTRL_VDET___M 0x0003E000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__BQ_GAIN_CTRL_VDET___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__TIA_ISEL_OP_OS_VDET___M 0x000000E0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__TIA_ISEL_OP_OS_VDET___S 5 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__TIA_ISEL_OP_OS_PDET___M 0x0000001C +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1__TIA_ISEL_OP_OS_PDET___S 2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1___M 0xFFFFE0FC +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC1___S 2 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2 (0x005F8540) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2___POR 0x1088B000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__BQ_ISEL_IC25_IP_VDET___POR 0x02 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__BQ_ISEL_IC25_IP_PDET___POR 0x02 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__BQ_ISEL_IC25_OP_VDET___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__BQ_ISEL_IC25_OP_PDET___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__TIA_RMCAP_VDET___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__TIA_RMCAP_PDET___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__BQ_ISEL_IC25_IP_VDET___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__BQ_ISEL_IC25_IP_VDET___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__BQ_ISEL_IC25_IP_PDET___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__BQ_ISEL_IC25_IP_PDET___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__BQ_ISEL_IC25_OP_VDET___M 0x003C0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__BQ_ISEL_IC25_OP_VDET___S 18 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__BQ_ISEL_IC25_OP_PDET___M 0x0003C000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__BQ_ISEL_IC25_OP_PDET___S 14 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__TIA_RMCAP_VDET___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__TIA_RMCAP_VDET___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__TIA_RMCAP_PDET___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2__TIA_RMCAP_PDET___S 12 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC2___S 12 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC3 (0x005F8544) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC3___POR 0x00005E2F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC3__BQ_CIN_CT_I_VDET___POR 0x02F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC3__BQ_CIN_CT_I_PDET___POR 0x02F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC3__BQ_CIN_CT_I_VDET___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC3__BQ_CIN_CT_I_VDET___S 9 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC3__BQ_CIN_CT_I_PDET___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC3__BQ_CIN_CT_I_PDET___S 0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC3___M 0x0003FFFF +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC3___S 0 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC4 (0x005F8548) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC4___POR 0x178BDCB9 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC4__BQ_CIN_CT_Q_VDET___POR 0x02F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC4__BQ_CIN_CT_Q_PDET___POR 0x02F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC4__BQ_CFBCAL_I_VDET___POR 0x39 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC4__BQ_CFBCAL_I_PDET___POR 0x39 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC4__BQ_CIN_CT_Q_VDET___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC4__BQ_CIN_CT_Q_VDET___S 23 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC4__BQ_CIN_CT_Q_PDET___M 0x007FC000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC4__BQ_CIN_CT_Q_PDET___S 14 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC4__BQ_CFBCAL_I_VDET___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC4__BQ_CFBCAL_I_VDET___S 7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC4__BQ_CFBCAL_I_PDET___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC4__BQ_CFBCAL_I_PDET___S 0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC4___S 0 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5 (0x005F854C) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5___POR 0x72E49630 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_CFBCAL_Q_VDET___POR 0x39 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_CFBCAL_Q_PDET___POR 0x39 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_ISEL_IPTAT25_OP_VDET___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_ISEL_IPTAT25_OP_PDET___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_GAIN_CTRL_PDET_HG___POR 0x0C +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_GAIN_CTRL_PDET_LG___POR 0x0C +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_CFBCAL_Q_VDET___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_CFBCAL_Q_VDET___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_CFBCAL_Q_PDET___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_CFBCAL_Q_PDET___S 18 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_ISEL_IPTAT25_OP_VDET___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_ISEL_IPTAT25_OP_VDET___S 15 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_ISEL_IPTAT25_OP_PDET___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_ISEL_IPTAT25_OP_PDET___S 12 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_GAIN_CTRL_PDET_HG___M 0x00000F80 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_GAIN_CTRL_PDET_HG___S 7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_GAIN_CTRL_PDET_LG___M 0x0000007C +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5__BQ_GAIN_CTRL_PDET_LG___S 2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_TPC5___S 2 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DET_MODE (0x005F8550) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DET_MODE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DET_MODE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DET_MODE__PDET_MODE_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DET_MODE__PDET_MODE_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DET_MODE__PDET_MODE_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DET_MODE___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DET_MODE___S 30 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC (0x005F8554) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC___POR 0xDADB7400 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_TIA_BW___POR 0x6 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_BW___POR 0x6 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_CC1ADJ___POR 0x5 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_CC2ADJ___POR 0x5 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_ZR1___POR 0x5 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_ZR2___POR 0x5 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_SELQ___POR 0x6 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BOOST_BQ___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_TIA_BW___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_TIA_BW___S 29 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_BW___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_BW___S 26 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_CC1ADJ___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_CC1ADJ___S 23 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_CC2ADJ___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_CC2ADJ___S 20 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_ZR1___M 0x000E0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_ZR1___S 17 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_ZR2___M 0x0001C000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_ZR2___S 14 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_SELQ___M 0x00003800 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BQ_SELQ___S 11 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BOOST_BQ___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC__DPD_BOOST_BQ___S 10 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_CH_BW_AC___S 10 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT (0x005F8558) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT___POR 0x00BFF234 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_CCADJ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_CFBCAL___POR 0x005 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ICQADJ___POR 0xF +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_VCMINTADJ___POR 0xF +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_IR25_IP___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_IC25_OP___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_OP_OS___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_IPTAT25_OP___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_CCADJ___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_CCADJ___S 30 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_CFBCAL___M 0x3FE00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_CFBCAL___S 21 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ICQADJ___M 0x001E0000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ICQADJ___S 17 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_VCMINTADJ___M 0x0001E000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_VCMINTADJ___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_IR25_IP___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_IR25_IP___S 10 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_IC25_OP___M 0x00000380 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_IC25_OP___S 7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_OP_OS___M 0x00000070 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_OP_OS___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_IPTAT25_OP___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT__DPD_TIA_ISEL_IPTAT25_OP___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA_LUT___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT (0x005F855C) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT___POR 0x2AC01776 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_CFBCAL___POR 0x15 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_OP_OS___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_CIN_CT___POR 0x000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_IP___POR 0x17 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_OP___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_IPTAT25_OP___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_CFBCAL___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_CFBCAL___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_OP_OS___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_OP_OS___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_CIN_CT___M 0x003FE000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_CIN_CT___S 13 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_IP___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_IP___S 8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_OP___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_IC25_OP___S 4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_IPTAT25_OP___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT__DPD_BQ_ISEL_IPTAT25_OP___S 1 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ_LUT___S 1 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA (0x005F8560) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA___POR 0x37000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_TIA_RMCAP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_TIA_RFB_I___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_TIA_RFB_Q___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_TIA_VICMADJ___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_TIA_RMCAP___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_TIA_RMCAP___S 31 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_TIA_RFB_I___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_TIA_RFB_I___S 28 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_TIA_RFB_Q___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_TIA_RFB_Q___S 25 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_TIA_VICMADJ___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA__DPD_TIA_VICMADJ___S 22 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_TIA___S 22 + +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ (0x005F8564) +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ___POR 0x40000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_VCM_SEL___POR 0x8 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_BYPASS___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_BYPASS___S 31 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_VCM_SEL___M 0x78000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ__DPD_BQ_VCM_SEL___S 27 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_RXBB_CH1_DPD_BQ___S 27 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_TESTREG (0x005F8800) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_TESTREG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_TESTREG___POR 0x22BB1212 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_TESTREG__TESTREG___POR 0x22BB1212 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_TESTREG__TESTREG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_TESTREG__TESTREG___S 0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_TESTREG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_TESTREG___S 0 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_IDX_SEL (0x005F8804) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_IDX_SEL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_IDX_SEL___POR 0x00000010 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_IDX_SEL__BBF_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_IDX_SEL__BBF_GAIN_OVD___POR 0x10 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_IDX_SEL__BBF_GAIN_OV___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_IDX_SEL__BBF_GAIN_OV___S 6 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_IDX_SEL__BBF_GAIN_OVD___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_IDX_SEL__BBF_GAIN_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_IDX_SEL___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_IDX_SEL___S 0 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC_CFG (0x005F8808) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC_CFG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC_CFG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC_CFG__DCOC_FORMAT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC_CFG__DCOC_FORMAT___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC_CFG__DCOC_FORMAT___S 30 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC_CFG___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC_CFG___S 30 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC (0x005F880C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC__DCOC_RES_I_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC__DCOC_RES_I_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC__DCOC_RES_Q_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC__DCOC_RES_Q_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC__DCOC_RES_I_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC__DCOC_RES_I_OV___S 31 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC__DCOC_RES_I_OVD___M 0x7F000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC__DCOC_RES_I_OVD___S 24 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC__DCOC_RES_Q_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC__DCOC_RES_Q_OV___S 23 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC__DCOC_RES_Q_OVD___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC__DCOC_RES_Q_OVD___S 16 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_DCOC___S 16 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0 (0x005F8810) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0___POR 0x04040434 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0__D_TIA_CTUNE___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0__D_BQ_C1_CTUNE___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0__D_BQ_C2_CTUNE___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0__D_IC25U_TIA_SEL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0__D_IC120U_TIA_SEL___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0__D_TIA_CTUNE___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0__D_TIA_CTUNE___S 24 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0__D_BQ_C1_CTUNE___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0__D_BQ_C1_CTUNE___S 16 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0__D_BQ_C2_CTUNE___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0__D_BQ_C2_CTUNE___S 8 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0__D_IC25U_TIA_SEL___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0__D_IC25U_TIA_SEL___S 4 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0__D_IC120U_TIA_SEL___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0__D_IC120U_TIA_SEL___S 0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC0___S 0 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1 (0x005F8814) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1___POR 0x5268DB71 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_TIA_CCOMP___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_TIA_CFWRD___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_IC25U_BQ_SEL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_IC120U_BQ_SEL___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_BQ_R1_RTUNE___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_BQ_R2_RTUNE___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_BQ_R3_RTUNE___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_IC25U_TIA_SLOPE___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_IC25U_BQ_SLOPE___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_IC25U_DCOC_SEL___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_TIA_CCOMP___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_TIA_CCOMP___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_TIA_CFWRD___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_TIA_CFWRD___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_IC25U_BQ_SEL___M 0x01E00000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_IC25U_BQ_SEL___S 21 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_IC120U_BQ_SEL___M 0x001E0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_IC120U_BQ_SEL___S 17 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_BQ_R1_RTUNE___M 0x0001C000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_BQ_R1_RTUNE___S 14 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_BQ_R2_RTUNE___M 0x00003800 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_BQ_R2_RTUNE___S 11 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_BQ_R3_RTUNE___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_BQ_R3_RTUNE___S 8 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_IC25U_TIA_SLOPE___M 0x000000E0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_IC25U_TIA_SLOPE___S 5 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_IC25U_BQ_SLOPE___M 0x0000001C +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_IC25U_BQ_SLOPE___S 2 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_IC25U_DCOC_SEL___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1__D_IC25U_DCOC_SEL___S 0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC1___S 0 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC2 (0x005F8818) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC2___POR 0x2B000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC2__D_BQ_CMFB_POLE_TUNE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC2__D_BQ_CMFB_ZERO_TUNE___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC2__D_TIA_CMFB_POLE_TUNE___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC2__D_TIA_CMFB_ZERO_TUNE___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC2__D_BQ_CMFB_POLE_TUNE___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC2__D_BQ_CMFB_POLE_TUNE___S 30 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC2__D_BQ_CMFB_ZERO_TUNE___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC2__D_BQ_CMFB_ZERO_TUNE___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC2__D_TIA_CMFB_POLE_TUNE___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC2__D_TIA_CMFB_POLE_TUNE___S 26 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC2__D_TIA_CMFB_ZERO_TUNE___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC2__D_TIA_CMFB_ZERO_TUNE___S 24 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC2___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_CH_BW_AC2___S 24 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_0 (0x005F881C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_0___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_0__BQ_CCOMP0___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_0__BQ_CFWRD0___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_0__BQ_CCOMP0___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_0__BQ_CCOMP0___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_0__BQ_CFWRD0___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_0__BQ_CFWRD0___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_0___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_0___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_1 (0x005F8820) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_1___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_1__BQ_CCOMP1___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_1__BQ_CFWRD1___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_1__BQ_CCOMP1___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_1__BQ_CCOMP1___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_1__BQ_CFWRD1___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_1__BQ_CFWRD1___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_1___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_1___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_2 (0x005F8824) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_2___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_2__BQ_CCOMP2___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_2__BQ_CFWRD2___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_2__BQ_CCOMP2___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_2__BQ_CCOMP2___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_2__BQ_CFWRD2___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_2__BQ_CFWRD2___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_2___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_2___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_3 (0x005F8828) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_3___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_3__BQ_CCOMP3___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_3__BQ_CFWRD3___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_3__BQ_CCOMP3___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_3__BQ_CCOMP3___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_3__BQ_CFWRD3___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_3__BQ_CFWRD3___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_3___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_3___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_4 (0x005F882C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_4___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_4__BQ_CCOMP4___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_4__BQ_CFWRD4___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_4__BQ_CCOMP4___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_4__BQ_CCOMP4___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_4__BQ_CFWRD4___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_4__BQ_CFWRD4___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_4___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_4___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_5 (0x005F8830) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_5___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_5__BQ_CCOMP5___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_5__BQ_CFWRD5___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_5__BQ_CCOMP5___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_5__BQ_CCOMP5___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_5__BQ_CFWRD5___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_5__BQ_CFWRD5___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_5___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_5___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_6 (0x005F8834) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_6___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_6__BQ_CCOMP6___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_6__BQ_CFWRD6___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_6__BQ_CCOMP6___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_6__BQ_CCOMP6___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_6__BQ_CFWRD6___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_6__BQ_CFWRD6___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_6___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_6___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_7 (0x005F8838) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_7___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_7__BQ_CCOMP7___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_7__BQ_CFWRD7___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_7__BQ_CCOMP7___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_7__BQ_CCOMP7___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_7__BQ_CFWRD7___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_7__BQ_CFWRD7___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_7___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_7___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_8 (0x005F883C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_8___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_8__BQ_CCOMP8___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_8__BQ_CFWRD8___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_8__BQ_CCOMP8___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_8__BQ_CCOMP8___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_8__BQ_CFWRD8___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_8__BQ_CFWRD8___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_8___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_8___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_9 (0x005F8840) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_9___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_9__BQ_CCOMP9___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_9__BQ_CFWRD9___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_9__BQ_CCOMP9___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_9__BQ_CCOMP9___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_9__BQ_CFWRD9___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_9__BQ_CFWRD9___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_9___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_9___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_10 (0x005F8844) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_10___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_10__BQ_CCOMP10___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_10__BQ_CFWRD10___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_10__BQ_CCOMP10___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_10__BQ_CCOMP10___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_10__BQ_CFWRD10___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_10__BQ_CFWRD10___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_10___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_10___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_11 (0x005F8848) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_11___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_11__BQ_CCOMP11___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_11__BQ_CFWRD11___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_11__BQ_CCOMP11___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_11__BQ_CCOMP11___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_11__BQ_CFWRD11___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_11__BQ_CFWRD11___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_11___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_11___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_12 (0x005F884C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_12___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_12__BQ_CCOMP12___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_12__BQ_CFWRD12___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_12__BQ_CCOMP12___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_12__BQ_CCOMP12___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_12__BQ_CFWRD12___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_12__BQ_CFWRD12___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_12___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_12___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_13 (0x005F8850) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_13___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_13__BQ_CCOMP13___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_13__BQ_CFWRD13___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_13__BQ_CCOMP13___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_13__BQ_CCOMP13___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_13__BQ_CFWRD13___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_13__BQ_CFWRD13___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_13___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_13___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_14 (0x005F8854) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_14___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_14__BQ_CCOMP14___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_14__BQ_CFWRD14___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_14__BQ_CCOMP14___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_14__BQ_CCOMP14___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_14__BQ_CFWRD14___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_14__BQ_CFWRD14___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_14___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_14___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_15 (0x005F8858) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_15___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_15__BQ_CCOMP15___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_15__BQ_CFWRD15___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_15__BQ_CCOMP15___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_15__BQ_CCOMP15___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_15__BQ_CFWRD15___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_15__BQ_CFWRD15___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_15___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_15___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_16 (0x005F885C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_16___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_16__BQ_CCOMP16___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_16__BQ_CFWRD16___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_16__BQ_CCOMP16___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_16__BQ_CCOMP16___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_16__BQ_CFWRD16___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_16__BQ_CFWRD16___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_16___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_16___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_17 (0x005F8860) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_17___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_17__BQ_CCOMP17___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_17__BQ_CFWRD17___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_17__BQ_CCOMP17___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_17__BQ_CCOMP17___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_17__BQ_CFWRD17___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_17__BQ_CFWRD17___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_17___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_17___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_18 (0x005F8864) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_18___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_18__BQ_CCOMP18___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_18__BQ_CFWRD18___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_18__BQ_CCOMP18___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_18__BQ_CCOMP18___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_18__BQ_CFWRD18___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_18__BQ_CFWRD18___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_18___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_18___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_19 (0x005F8868) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_19___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_19__BQ_CCOMP19___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_19__BQ_CFWRD19___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_19__BQ_CCOMP19___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_19__BQ_CCOMP19___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_19__BQ_CFWRD19___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_19__BQ_CFWRD19___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_19___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_19___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_20 (0x005F886C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_20___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_20__BQ_CCOMP20___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_20__BQ_CFWRD20___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_20__BQ_CCOMP20___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_20__BQ_CCOMP20___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_20__BQ_CFWRD20___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_20__BQ_CFWRD20___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_20___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_20___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_21 (0x005F8870) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_21___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_21__BQ_CCOMP21___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_21__BQ_CFWRD21___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_21__BQ_CCOMP21___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_21__BQ_CCOMP21___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_21__BQ_CFWRD21___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_21__BQ_CFWRD21___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_21___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_21___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_22 (0x005F8874) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_22___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_22__BQ_CCOMP22___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_22__BQ_CFWRD22___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_22__BQ_CCOMP22___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_22__BQ_CCOMP22___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_22__BQ_CFWRD22___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_22__BQ_CFWRD22___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_22___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_22___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_23 (0x005F8878) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_23___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_23__BQ_CCOMP23___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_23__BQ_CFWRD23___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_23__BQ_CCOMP23___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_23__BQ_CCOMP23___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_23__BQ_CFWRD23___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_23__BQ_CFWRD23___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_23___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_23___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_24 (0x005F887C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_24___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_24__BQ_CCOMP24___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_24__BQ_CFWRD24___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_24__BQ_CCOMP24___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_24__BQ_CCOMP24___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_24__BQ_CFWRD24___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_24__BQ_CFWRD24___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_24___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_24___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_25 (0x005F8880) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_25___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_25__BQ_CCOMP25___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_25__BQ_CFWRD25___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_25__BQ_CCOMP25___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_25__BQ_CCOMP25___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_25__BQ_CFWRD25___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_25__BQ_CFWRD25___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_25___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_25___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_26 (0x005F8884) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_26___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_26__BQ_CCOMP26___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_26__BQ_CFWRD26___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_26__BQ_CCOMP26___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_26__BQ_CCOMP26___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_26__BQ_CFWRD26___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_26__BQ_CFWRD26___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_26___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_26___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_27 (0x005F8888) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_27___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_27__BQ_CCOMP27___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_27__BQ_CFWRD27___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_27__BQ_CCOMP27___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_27__BQ_CCOMP27___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_27__BQ_CFWRD27___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_27__BQ_CFWRD27___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_27___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_27___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_28 (0x005F888C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_28___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_28__BQ_CCOMP28___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_28__BQ_CFWRD28___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_28__BQ_CCOMP28___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_28__BQ_CCOMP28___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_28__BQ_CFWRD28___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_28__BQ_CFWRD28___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_28___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_28___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_29 (0x005F8890) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_29___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_29__BQ_CCOMP29___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_29__BQ_CFWRD29___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_29__BQ_CCOMP29___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_29__BQ_CCOMP29___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_29__BQ_CFWRD29___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_29__BQ_CFWRD29___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_29___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_29___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_30 (0x005F8894) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_30___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_30__BQ_CCOMP30___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_30__BQ_CFWRD30___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_30__BQ_CCOMP30___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_30__BQ_CCOMP30___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_30__BQ_CFWRD30___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_30__BQ_CFWRD30___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_30___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_30___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_31 (0x005F8898) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_31___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_31__BQ_CCOMP31___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_31__BQ_CFWRD31___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_31__BQ_CCOMP31___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_31__BQ_CCOMP31___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_31__BQ_CFWRD31___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_31__BQ_CFWRD31___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_31___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_31___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_32 (0x005F889C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_32___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_32___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_32__BQ_CCOMP32___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_32__BQ_CFWRD32___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_32__BQ_CCOMP32___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_32__BQ_CCOMP32___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_32__BQ_CFWRD32___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_32__BQ_CFWRD32___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_32___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_32___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_33 (0x005F88A0) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_33___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_33___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_33__BQ_CCOMP33___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_33__BQ_CFWRD33___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_33__BQ_CCOMP33___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_33__BQ_CCOMP33___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_33__BQ_CFWRD33___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_33__BQ_CFWRD33___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_33___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_33___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_34 (0x005F88A4) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_34___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_34___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_34__BQ_CCOMP34___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_34__BQ_CFWRD34___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_34__BQ_CCOMP34___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_34__BQ_CCOMP34___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_34__BQ_CFWRD34___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_34__BQ_CFWRD34___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_34___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_34___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_35 (0x005F88A8) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_35___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_35___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_35__BQ_CCOMP35___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_35__BQ_CFWRD35___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_35__BQ_CCOMP35___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_35__BQ_CCOMP35___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_35__BQ_CFWRD35___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_35__BQ_CFWRD35___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_35___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_35___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_36 (0x005F88AC) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_36___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_36___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_36__BQ_CCOMP36___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_36__BQ_CFWRD36___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_36__BQ_CCOMP36___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_36__BQ_CCOMP36___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_36__BQ_CFWRD36___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_36__BQ_CFWRD36___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_36___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_36___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_37 (0x005F88B0) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_37___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_37___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_37__BQ_CCOMP37___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_37__BQ_CFWRD37___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_37__BQ_CCOMP37___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_37__BQ_CCOMP37___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_37__BQ_CFWRD37___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_37__BQ_CFWRD37___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_37___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_37___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_38 (0x005F88B4) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_38___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_38___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_38__BQ_CCOMP38___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_38__BQ_CFWRD38___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_38__BQ_CCOMP38___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_38__BQ_CCOMP38___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_38__BQ_CFWRD38___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_38__BQ_CFWRD38___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_38___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_38___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_39 (0x005F88B8) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_39___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_39___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_39__BQ_CCOMP39___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_39__BQ_CFWRD39___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_39__BQ_CCOMP39___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_39__BQ_CCOMP39___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_39__BQ_CFWRD39___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_39__BQ_CFWRD39___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_39___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_39___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_40 (0x005F88BC) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_40___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_40___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_40__BQ_CCOMP40___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_40__BQ_CFWRD40___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_40__BQ_CCOMP40___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_40__BQ_CCOMP40___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_40__BQ_CFWRD40___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_40__BQ_CFWRD40___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_40___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_40___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_41 (0x005F88C0) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_41___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_41___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_41__BQ_CCOMP41___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_41__BQ_CFWRD41___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_41__BQ_CCOMP41___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_41__BQ_CCOMP41___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_41__BQ_CFWRD41___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_41__BQ_CFWRD41___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_41___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_41___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_42 (0x005F88C4) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_42___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_42___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_42__BQ_CCOMP42___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_42__BQ_CFWRD42___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_42__BQ_CCOMP42___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_42__BQ_CCOMP42___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_42__BQ_CFWRD42___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_42__BQ_CFWRD42___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_42___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_42___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_43 (0x005F88C8) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_43___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_43___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_43__BQ_CCOMP43___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_43__BQ_CFWRD43___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_43__BQ_CCOMP43___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_43__BQ_CCOMP43___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_43__BQ_CFWRD43___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_43__BQ_CFWRD43___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_43___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_43___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_44 (0x005F88CC) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_44___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_44___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_44__BQ_CCOMP44___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_44__BQ_CFWRD44___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_44__BQ_CCOMP44___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_44__BQ_CCOMP44___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_44__BQ_CFWRD44___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_44__BQ_CFWRD44___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_44___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_44___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_45 (0x005F88D0) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_45___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_45___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_45__BQ_CCOMP45___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_45__BQ_CFWRD45___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_45__BQ_CCOMP45___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_45__BQ_CCOMP45___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_45__BQ_CFWRD45___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_45__BQ_CFWRD45___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_45___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_45___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_46 (0x005F88D4) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_46___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_46___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_46__BQ_CCOMP46___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_46__BQ_CFWRD46___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_46__BQ_CCOMP46___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_46__BQ_CCOMP46___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_46__BQ_CFWRD46___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_46__BQ_CFWRD46___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_46___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_46___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_47 (0x005F88D8) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_47___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_47___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_47__BQ_CCOMP47___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_47__BQ_CFWRD47___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_47__BQ_CCOMP47___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_47__BQ_CCOMP47___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_47__BQ_CFWRD47___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_47__BQ_CFWRD47___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_47___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_47___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_48 (0x005F88DC) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_48___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_48___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_48__BQ_CCOMP48___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_48__BQ_CFWRD48___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_48__BQ_CCOMP48___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_48__BQ_CCOMP48___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_48__BQ_CFWRD48___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_48__BQ_CFWRD48___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_48___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_48___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_49 (0x005F88E0) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_49___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_49___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_49__BQ_CCOMP49___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_49__BQ_CFWRD49___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_49__BQ_CCOMP49___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_49__BQ_CCOMP49___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_49__BQ_CFWRD49___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_49__BQ_CFWRD49___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_49___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_49___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_50 (0x005F88E4) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_50___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_50___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_50__BQ_CCOMP50___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_50__BQ_CFWRD50___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_50__BQ_CCOMP50___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_50__BQ_CCOMP50___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_50__BQ_CFWRD50___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_50__BQ_CFWRD50___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_50___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_50___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_51 (0x005F88E8) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_51___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_51___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_51__BQ_CCOMP51___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_51__BQ_CFWRD51___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_51__BQ_CCOMP51___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_51__BQ_CCOMP51___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_51__BQ_CFWRD51___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_51__BQ_CFWRD51___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_51___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_51___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_52 (0x005F88EC) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_52___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_52___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_52__BQ_CCOMP52___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_52__BQ_CFWRD52___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_52__BQ_CCOMP52___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_52__BQ_CCOMP52___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_52__BQ_CFWRD52___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_52__BQ_CFWRD52___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_52___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_52___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_53 (0x005F88F0) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_53___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_53___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_53__BQ_CCOMP53___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_53__BQ_CFWRD53___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_53__BQ_CCOMP53___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_53__BQ_CCOMP53___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_53__BQ_CFWRD53___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_53__BQ_CFWRD53___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_53___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_53___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_54 (0x005F88F4) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_54___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_54___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_54__BQ_CCOMP54___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_54__BQ_CFWRD54___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_54__BQ_CCOMP54___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_54__BQ_CCOMP54___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_54__BQ_CFWRD54___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_54__BQ_CFWRD54___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_54___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_54___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_55 (0x005F88F8) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_55___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_55___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_55__BQ_CCOMP55___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_55__BQ_CFWRD55___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_55__BQ_CCOMP55___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_55__BQ_CCOMP55___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_55__BQ_CFWRD55___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_55__BQ_CFWRD55___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_55___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_55___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_56 (0x005F88FC) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_56___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_56___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_56__BQ_CCOMP56___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_56__BQ_CFWRD56___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_56__BQ_CCOMP56___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_56__BQ_CCOMP56___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_56__BQ_CFWRD56___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_56__BQ_CFWRD56___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_56___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_56___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_57 (0x005F8900) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_57___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_57___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_57__BQ_CCOMP57___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_57__BQ_CFWRD57___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_57__BQ_CCOMP57___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_57__BQ_CCOMP57___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_57__BQ_CFWRD57___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_57__BQ_CFWRD57___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_57___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_57___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_58 (0x005F8904) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_58___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_58___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_58__BQ_CCOMP58___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_58__BQ_CFWRD58___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_58__BQ_CCOMP58___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_58__BQ_CCOMP58___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_58__BQ_CFWRD58___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_58__BQ_CFWRD58___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_58___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_58___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_59 (0x005F8908) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_59___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_59___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_59__BQ_CCOMP59___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_59__BQ_CFWRD59___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_59__BQ_CCOMP59___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_59__BQ_CCOMP59___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_59__BQ_CFWRD59___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_59__BQ_CFWRD59___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_59___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_59___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_60 (0x005F890C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_60___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_60___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_60__BQ_CCOMP60___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_60__BQ_CFWRD60___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_60__BQ_CCOMP60___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_60__BQ_CCOMP60___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_60__BQ_CFWRD60___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_60__BQ_CFWRD60___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_60___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_60___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_61 (0x005F8910) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_61___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_61___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_61__BQ_CCOMP61___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_61__BQ_CFWRD61___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_61__BQ_CCOMP61___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_61__BQ_CCOMP61___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_61__BQ_CFWRD61___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_61__BQ_CFWRD61___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_61___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_61___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_62 (0x005F8914) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_62___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_62___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_62__BQ_CCOMP62___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_62__BQ_CFWRD62___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_62__BQ_CCOMP62___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_62__BQ_CCOMP62___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_62__BQ_CFWRD62___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_62__BQ_CFWRD62___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_62___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_62___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_63 (0x005F8918) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_63___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_63___POR 0x76000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_63__BQ_CCOMP63___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_63__BQ_CFWRD63___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_63__BQ_CCOMP63___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_63__BQ_CCOMP63___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_63__BQ_CFWRD63___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_63__BQ_CFWRD63___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_63___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BBF_GAIN_63___S 25 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_0 (0x005F891C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_0__ATTEN_SWA0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_0__ATTEN_SWB0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_0__ATTEN_SWA0___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_0__ATTEN_SWA0___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_0__ATTEN_SWB0___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_0__ATTEN_SWB0___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_0___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_0___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_1 (0x005F8920) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_1__ATTEN_SWA1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_1__ATTEN_SWB1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_1__ATTEN_SWA1___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_1__ATTEN_SWA1___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_1__ATTEN_SWB1___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_1__ATTEN_SWB1___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_1___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_1___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_2 (0x005F8924) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_2__ATTEN_SWA2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_2__ATTEN_SWB2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_2__ATTEN_SWA2___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_2__ATTEN_SWA2___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_2__ATTEN_SWB2___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_2__ATTEN_SWB2___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_2___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_2___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_3 (0x005F8928) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_3__ATTEN_SWA3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_3__ATTEN_SWB3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_3__ATTEN_SWA3___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_3__ATTEN_SWA3___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_3__ATTEN_SWB3___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_3__ATTEN_SWB3___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_3___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_3___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_4 (0x005F892C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_4__ATTEN_SWA4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_4__ATTEN_SWB4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_4__ATTEN_SWA4___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_4__ATTEN_SWA4___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_4__ATTEN_SWB4___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_4__ATTEN_SWB4___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_4___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_4___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_5 (0x005F8930) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_5__ATTEN_SWA5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_5__ATTEN_SWB5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_5__ATTEN_SWA5___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_5__ATTEN_SWA5___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_5__ATTEN_SWB5___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_5__ATTEN_SWB5___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_5___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_5___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_6 (0x005F8934) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_6__ATTEN_SWA6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_6__ATTEN_SWB6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_6__ATTEN_SWA6___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_6__ATTEN_SWA6___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_6__ATTEN_SWB6___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_6__ATTEN_SWB6___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_6___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_6___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_7 (0x005F8938) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_7__ATTEN_SWA7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_7__ATTEN_SWB7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_7__ATTEN_SWA7___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_7__ATTEN_SWA7___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_7__ATTEN_SWB7___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_7__ATTEN_SWB7___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_7___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_7___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_8 (0x005F893C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_8__ATTEN_SWA8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_8__ATTEN_SWB8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_8__ATTEN_SWA8___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_8__ATTEN_SWA8___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_8__ATTEN_SWB8___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_8__ATTEN_SWB8___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_8___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_8___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_9 (0x005F8940) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_9__ATTEN_SWA9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_9__ATTEN_SWB9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_9__ATTEN_SWA9___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_9__ATTEN_SWA9___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_9__ATTEN_SWB9___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_9__ATTEN_SWB9___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_9___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_9___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_10 (0x005F8944) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_10__ATTEN_SWA10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_10__ATTEN_SWB10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_10__ATTEN_SWA10___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_10__ATTEN_SWA10___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_10__ATTEN_SWB10___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_10__ATTEN_SWB10___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_10___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_10___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_11 (0x005F8948) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_11___POR 0x42400000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_11__ATTEN_SWA11___POR 0x21 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_11__ATTEN_SWB11___POR 0x10 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_11__ATTEN_SWA11___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_11__ATTEN_SWA11___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_11__ATTEN_SWB11___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_11__ATTEN_SWB11___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_11___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_11___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_12 (0x005F894C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_12___POR 0x40200000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_12__ATTEN_SWA12___POR 0x20 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_12__ATTEN_SWB12___POR 0x08 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_12__ATTEN_SWA12___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_12__ATTEN_SWA12___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_12__ATTEN_SWB12___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_12__ATTEN_SWB12___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_12___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_12___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_13 (0x005F8950) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_13___POR 0x10080000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_13__ATTEN_SWA13___POR 0x08 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_13__ATTEN_SWB13___POR 0x02 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_13__ATTEN_SWA13___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_13__ATTEN_SWA13___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_13__ATTEN_SWB13___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_13__ATTEN_SWB13___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_13___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_13___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_14 (0x005F8954) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_14___POR 0x08040000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_14__ATTEN_SWA14___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_14__ATTEN_SWB14___POR 0x01 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_14__ATTEN_SWA14___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_14__ATTEN_SWA14___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_14__ATTEN_SWB14___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_14__ATTEN_SWB14___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_14___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_14___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_15 (0x005F8958) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_15___POR 0x04000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_15__ATTEN_SWA15___POR 0x02 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_15__ATTEN_SWB15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_15__ATTEN_SWA15___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_15__ATTEN_SWA15___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_15__ATTEN_SWB15___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_15__ATTEN_SWB15___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_15___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_15___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_16 (0x005F895C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_16___POR 0x40100000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_16__ATTEN_SWA16___POR 0x20 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_16__ATTEN_SWB16___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_16__ATTEN_SWA16___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_16__ATTEN_SWA16___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_16__ATTEN_SWB16___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_16__ATTEN_SWB16___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_16___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_16___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_17 (0x005F8960) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_17___POR 0x20080000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_17__ATTEN_SWA17___POR 0x10 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_17__ATTEN_SWB17___POR 0x02 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_17__ATTEN_SWA17___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_17__ATTEN_SWA17___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_17__ATTEN_SWB17___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_17__ATTEN_SWB17___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_17___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_17___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_18 (0x005F8964) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_18___POR 0x42100000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_18__ATTEN_SWA18___POR 0x21 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_18__ATTEN_SWB18___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_18__ATTEN_SWA18___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_18__ATTEN_SWA18___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_18__ATTEN_SWB18___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_18__ATTEN_SWB18___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_18___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_18___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_19 (0x005F8968) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_19___POR 0x80200000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_19__ATTEN_SWA19___POR 0x40 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_19__ATTEN_SWB19___POR 0x08 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_19__ATTEN_SWA19___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_19__ATTEN_SWA19___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_19__ATTEN_SWB19___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_19__ATTEN_SWB19___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_19___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_19___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_20 (0x005F896C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_20___POR 0x44100000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_20__ATTEN_SWA20___POR 0x22 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_20__ATTEN_SWB20___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_20__ATTEN_SWA20___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_20__ATTEN_SWA20___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_20__ATTEN_SWB20___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_20__ATTEN_SWB20___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_20___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_20___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_21 (0x005F8970) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_21___POR 0x30100000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_21__ATTEN_SWA21___POR 0x18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_21__ATTEN_SWB21___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_21__ATTEN_SWA21___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_21__ATTEN_SWA21___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_21__ATTEN_SWB21___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_21__ATTEN_SWB21___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_21___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_21___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_22 (0x005F8974) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_22___POR 0x50100000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_22__ATTEN_SWA22___POR 0x28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_22__ATTEN_SWB22___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_22__ATTEN_SWA22___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_22__ATTEN_SWA22___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_22__ATTEN_SWB22___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_22__ATTEN_SWB22___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_22___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_22___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_23 (0x005F8978) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_23___POR 0x84100000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_23__ATTEN_SWA23___POR 0x42 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_23__ATTEN_SWB23___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_23__ATTEN_SWA23___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_23__ATTEN_SWA23___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_23__ATTEN_SWB23___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_23__ATTEN_SWB23___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_23___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_23___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_24 (0x005F897C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_24___POR 0x90100000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_24__ATTEN_SWA24___POR 0x48 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_24__ATTEN_SWB24___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_24__ATTEN_SWA24___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_24__ATTEN_SWA24___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_24__ATTEN_SWB24___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_24__ATTEN_SWB24___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_24___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_24___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_25 (0x005F8980) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_25___POR 0x88080000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_25__ATTEN_SWA25___POR 0x44 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_25__ATTEN_SWB25___POR 0x02 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_25__ATTEN_SWA25___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_25__ATTEN_SWA25___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_25__ATTEN_SWB25___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_25__ATTEN_SWB25___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_25___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_25___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_26 (0x005F8984) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_26___POR 0x88040000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_26__ATTEN_SWA26___POR 0x44 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_26__ATTEN_SWB26___POR 0x01 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_26__ATTEN_SWA26___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_26__ATTEN_SWA26___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_26__ATTEN_SWB26___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_26__ATTEN_SWB26___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_26___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_26___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_27 (0x005F8988) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_27___POR 0xA0040000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_27__ATTEN_SWA27___POR 0x50 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_27__ATTEN_SWB27___POR 0x01 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_27__ATTEN_SWA27___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_27__ATTEN_SWA27___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_27__ATTEN_SWB27___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_27__ATTEN_SWB27___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_27___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_27___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_28 (0x005F898C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_28___POR 0xC8040000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_28__ATTEN_SWA28___POR 0x64 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_28__ATTEN_SWB28___POR 0x01 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_28__ATTEN_SWA28___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_28__ATTEN_SWA28___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_28__ATTEN_SWB28___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_28__ATTEN_SWB28___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_28___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_28___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_29 (0x005F8990) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_29___POR 0xD8040000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_29__ATTEN_SWA29___POR 0x6C +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_29__ATTEN_SWB29___POR 0x01 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_29__ATTEN_SWA29___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_29__ATTEN_SWA29___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_29__ATTEN_SWB29___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_29__ATTEN_SWB29___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_29___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_29___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_30 (0x005F8994) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_30___POR 0xF2000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_30__ATTEN_SWA30___POR 0x79 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_30__ATTEN_SWB30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_30__ATTEN_SWA30___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_30__ATTEN_SWA30___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_30__ATTEN_SWB30___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_30__ATTEN_SWB30___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_30___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_30___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_31 (0x005F8998) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_31___POR 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_31__ATTEN_SWA31___POR 0x7F +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_31__ATTEN_SWB31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_31__ATTEN_SWA31___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_31__ATTEN_SWA31___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_31__ATTEN_SWB31___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_31__ATTEN_SWB31___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_31___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_31___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_32 (0x005F899C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_32___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_32___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_32__ATTEN_SWA32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_32__ATTEN_SWB32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_32__ATTEN_SWA32___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_32__ATTEN_SWA32___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_32__ATTEN_SWB32___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_32__ATTEN_SWB32___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_32___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_32___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_33 (0x005F89A0) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_33___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_33___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_33__ATTEN_SWA33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_33__ATTEN_SWB33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_33__ATTEN_SWA33___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_33__ATTEN_SWA33___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_33__ATTEN_SWB33___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_33__ATTEN_SWB33___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_33___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_33___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_34 (0x005F89A4) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_34___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_34___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_34__ATTEN_SWA34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_34__ATTEN_SWB34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_34__ATTEN_SWA34___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_34__ATTEN_SWA34___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_34__ATTEN_SWB34___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_34__ATTEN_SWB34___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_34___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_34___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_35 (0x005F89A8) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_35___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_35___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_35__ATTEN_SWA35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_35__ATTEN_SWB35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_35__ATTEN_SWA35___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_35__ATTEN_SWA35___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_35__ATTEN_SWB35___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_35__ATTEN_SWB35___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_35___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_35___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_36 (0x005F89AC) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_36___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_36___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_36__ATTEN_SWA36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_36__ATTEN_SWB36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_36__ATTEN_SWA36___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_36__ATTEN_SWA36___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_36__ATTEN_SWB36___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_36__ATTEN_SWB36___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_36___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_36___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_37 (0x005F89B0) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_37___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_37___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_37__ATTEN_SWA37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_37__ATTEN_SWB37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_37__ATTEN_SWA37___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_37__ATTEN_SWA37___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_37__ATTEN_SWB37___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_37__ATTEN_SWB37___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_37___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_37___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_38 (0x005F89B4) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_38___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_38___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_38__ATTEN_SWA38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_38__ATTEN_SWB38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_38__ATTEN_SWA38___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_38__ATTEN_SWA38___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_38__ATTEN_SWB38___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_38__ATTEN_SWB38___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_38___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_38___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_39 (0x005F89B8) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_39___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_39___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_39__ATTEN_SWA39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_39__ATTEN_SWB39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_39__ATTEN_SWA39___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_39__ATTEN_SWA39___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_39__ATTEN_SWB39___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_39__ATTEN_SWB39___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_39___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_39___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_40 (0x005F89BC) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_40___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_40___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_40__ATTEN_SWA40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_40__ATTEN_SWB40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_40__ATTEN_SWA40___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_40__ATTEN_SWA40___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_40__ATTEN_SWB40___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_40__ATTEN_SWB40___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_40___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_40___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_41 (0x005F89C0) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_41___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_41___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_41__ATTEN_SWA41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_41__ATTEN_SWB41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_41__ATTEN_SWA41___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_41__ATTEN_SWA41___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_41__ATTEN_SWB41___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_41__ATTEN_SWB41___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_41___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_41___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_42 (0x005F89C4) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_42___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_42___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_42__ATTEN_SWA42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_42__ATTEN_SWB42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_42__ATTEN_SWA42___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_42__ATTEN_SWA42___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_42__ATTEN_SWB42___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_42__ATTEN_SWB42___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_42___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_42___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_43 (0x005F89C8) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_43___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_43___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_43__ATTEN_SWA43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_43__ATTEN_SWB43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_43__ATTEN_SWA43___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_43__ATTEN_SWA43___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_43__ATTEN_SWB43___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_43__ATTEN_SWB43___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_43___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_43___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_44 (0x005F89CC) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_44___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_44___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_44__ATTEN_SWA44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_44__ATTEN_SWB44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_44__ATTEN_SWA44___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_44__ATTEN_SWA44___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_44__ATTEN_SWB44___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_44__ATTEN_SWB44___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_44___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_44___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_45 (0x005F89D0) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_45___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_45___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_45__ATTEN_SWA45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_45__ATTEN_SWB45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_45__ATTEN_SWA45___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_45__ATTEN_SWA45___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_45__ATTEN_SWB45___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_45__ATTEN_SWB45___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_45___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_45___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_46 (0x005F89D4) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_46___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_46___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_46__ATTEN_SWA46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_46__ATTEN_SWB46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_46__ATTEN_SWA46___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_46__ATTEN_SWA46___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_46__ATTEN_SWB46___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_46__ATTEN_SWB46___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_46___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_46___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_47 (0x005F89D8) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_47___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_47___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_47__ATTEN_SWA47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_47__ATTEN_SWB47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_47__ATTEN_SWA47___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_47__ATTEN_SWA47___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_47__ATTEN_SWB47___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_47__ATTEN_SWB47___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_47___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_47___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_48 (0x005F89DC) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_48___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_48___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_48__ATTEN_SWA48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_48__ATTEN_SWB48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_48__ATTEN_SWA48___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_48__ATTEN_SWA48___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_48__ATTEN_SWB48___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_48__ATTEN_SWB48___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_48___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_48___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_49 (0x005F89E0) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_49___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_49___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_49__ATTEN_SWA49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_49__ATTEN_SWB49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_49__ATTEN_SWA49___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_49__ATTEN_SWA49___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_49__ATTEN_SWB49___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_49__ATTEN_SWB49___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_49___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_49___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_50 (0x005F89E4) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_50___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_50___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_50__ATTEN_SWA50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_50__ATTEN_SWB50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_50__ATTEN_SWA50___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_50__ATTEN_SWA50___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_50__ATTEN_SWB50___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_50__ATTEN_SWB50___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_50___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_50___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_51 (0x005F89E8) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_51___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_51___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_51__ATTEN_SWA51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_51__ATTEN_SWB51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_51__ATTEN_SWA51___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_51__ATTEN_SWA51___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_51__ATTEN_SWB51___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_51__ATTEN_SWB51___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_51___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_51___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_52 (0x005F89EC) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_52___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_52___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_52__ATTEN_SWA52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_52__ATTEN_SWB52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_52__ATTEN_SWA52___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_52__ATTEN_SWA52___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_52__ATTEN_SWB52___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_52__ATTEN_SWB52___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_52___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_52___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_53 (0x005F89F0) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_53___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_53___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_53__ATTEN_SWA53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_53__ATTEN_SWB53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_53__ATTEN_SWA53___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_53__ATTEN_SWA53___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_53__ATTEN_SWB53___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_53__ATTEN_SWB53___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_53___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_53___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_54 (0x005F89F4) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_54___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_54___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_54__ATTEN_SWA54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_54__ATTEN_SWB54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_54__ATTEN_SWA54___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_54__ATTEN_SWA54___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_54__ATTEN_SWB54___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_54__ATTEN_SWB54___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_54___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_54___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_55 (0x005F89F8) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_55___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_55___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_55__ATTEN_SWA55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_55__ATTEN_SWB55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_55__ATTEN_SWA55___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_55__ATTEN_SWA55___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_55__ATTEN_SWB55___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_55__ATTEN_SWB55___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_55___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_55___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_56 (0x005F89FC) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_56___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_56___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_56__ATTEN_SWA56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_56__ATTEN_SWB56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_56__ATTEN_SWA56___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_56__ATTEN_SWA56___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_56__ATTEN_SWB56___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_56__ATTEN_SWB56___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_56___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_56___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_57 (0x005F8A00) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_57___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_57___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_57__ATTEN_SWA57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_57__ATTEN_SWB57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_57__ATTEN_SWA57___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_57__ATTEN_SWA57___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_57__ATTEN_SWB57___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_57__ATTEN_SWB57___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_57___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_57___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_58 (0x005F8A04) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_58___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_58___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_58__ATTEN_SWA58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_58__ATTEN_SWB58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_58__ATTEN_SWA58___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_58__ATTEN_SWA58___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_58__ATTEN_SWB58___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_58__ATTEN_SWB58___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_58___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_58___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_59 (0x005F8A08) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_59___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_59___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_59__ATTEN_SWA59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_59__ATTEN_SWB59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_59__ATTEN_SWA59___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_59__ATTEN_SWA59___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_59__ATTEN_SWB59___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_59__ATTEN_SWB59___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_59___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_59___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_60 (0x005F8A0C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_60___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_60___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_60__ATTEN_SWA60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_60__ATTEN_SWB60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_60__ATTEN_SWA60___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_60__ATTEN_SWA60___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_60__ATTEN_SWB60___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_60__ATTEN_SWB60___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_60___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_60___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_61 (0x005F8A10) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_61___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_61___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_61__ATTEN_SWA61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_61__ATTEN_SWB61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_61__ATTEN_SWA61___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_61__ATTEN_SWA61___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_61__ATTEN_SWB61___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_61__ATTEN_SWB61___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_61___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_61___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_62 (0x005F8A14) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_62___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_62___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_62__ATTEN_SWA62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_62__ATTEN_SWB62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_62__ATTEN_SWA62___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_62__ATTEN_SWA62___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_62__ATTEN_SWB62___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_62__ATTEN_SWB62___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_62___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_62___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_63 (0x005F8A18) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_63___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_63___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_63__ATTEN_SWA63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_63__ATTEN_SWB63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_63__ATTEN_SWA63___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_63__ATTEN_SWA63___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_63__ATTEN_SWB63___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_63__ATTEN_SWB63___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_63___M 0xFFFC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATTEN_GAIN_63___S 18 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV0 (0x005F8A1C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV0__BQ_CCOMP_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV0__BQ_CCOMP_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV0__BQ_CFWRD_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV0__BQ_CFWRD_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV0__BQ_CCOMP_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV0__BQ_CCOMP_OV___S 31 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV0__BQ_CCOMP_OVD___M 0x78000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV0__BQ_CCOMP_OVD___S 27 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV0__BQ_CFWRD_OV___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV0__BQ_CFWRD_OV___S 26 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV0__BQ_CFWRD_OVD___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV0__BQ_CFWRD_OVD___S 23 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV0___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV0___S 23 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV1 (0x005F8A20) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV1__ATTEN_SWA_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV1__ATTEN_SWA_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV1__ATTEN_SWB_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV1__ATTEN_SWB_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV1__ATTEN_SWA_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV1__ATTEN_SWA_OV___S 31 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV1__ATTEN_SWA_OVD___M 0x7F000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV1__ATTEN_SWA_OVD___S 24 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV1__ATTEN_SWB_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV1__ATTEN_SWB_OV___S 23 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV1__ATTEN_SWB_OVD___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV1__ATTEN_SWB_OVD___S 16 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV1___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_LUT_OV1___S 16 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0 (0x005F8A24) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__BBF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__BQ_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__PEF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__DCOC_DAC_EN_I_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__DCOC_DAC_EN_Q_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__TIA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__BBF_BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__TIA_HSW_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__BQ_HSW_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__BBF_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__BBF_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__BQ_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__BQ_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__PEF_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__PEF_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__DCOC_DAC_EN_I_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__DCOC_DAC_EN_I_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__DCOC_DAC_EN_Q_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__DCOC_DAC_EN_Q_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__TIA_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__TIA_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__BBF_BIAS_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__BBF_BIAS_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__TIA_HSW_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__TIA_HSW_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__BQ_HSW_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0__BQ_HSW_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0___M 0xFFFFC000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_EN0___S 14 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT (0x005F8A28) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT__RO_BQ_CCOMP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT__RO_BQ_CFWRD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT__RO_ATTEN_SWA___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT__RO_ATTEN_SWB___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT__RO_BBF_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT__RO_BQ_CCOMP___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT__RO_BQ_CCOMP___S 28 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT__RO_BQ_CFWRD___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT__RO_BQ_CFWRD___S 25 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT__RO_ATTEN_SWA___M 0x01FC0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT__RO_ATTEN_SWA___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT__RO_ATTEN_SWB___M 0x0003F800 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT__RO_ATTEN_SWB___S 11 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT__RO_BBF_GAIN___M 0x000007E0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT__RO_BBF_GAIN___S 5 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT___M 0xFFFFFFE0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_RO_LUT___S 5 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0 (0x005F8A30) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0___POR 0x6D55B000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_VINCM_BBF_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_VOUTCM_BBF_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_TIA_R_NBIAS___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_TIA_R_PBIAS___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_BQ_R_NBIAS___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_BQ_R_PBIAS___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_MIDREF_BQ___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_MIDREF_TIA___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_VINCM_BBF_CTRL___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_VINCM_BBF_CTRL___S 29 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_VOUTCM_BBF_CTRL___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_VOUTCM_BBF_CTRL___S 26 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_TIA_R_NBIAS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_TIA_R_NBIAS___S 24 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_TIA_R_PBIAS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_TIA_R_PBIAS___S 22 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_BQ_R_NBIAS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_BQ_R_NBIAS___S 20 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_BQ_R_PBIAS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_BQ_R_PBIAS___S 18 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_MIDREF_BQ___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_MIDREF_BQ___S 15 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_MIDREF_TIA___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0__D_MIDREF_TIA___S 12 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_BIAS0___S 12 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_RTUNE (0x005F8A34) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_RTUNE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_RTUNE___POR 0xB4000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_RTUNE__D_LVL_RTUNE___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_RTUNE__D_TIA_RTUNE___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_RTUNE__D_LVL_RTUNE___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_RTUNE__D_LVL_RTUNE___S 29 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_RTUNE__D_TIA_RTUNE___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_RTUNE__D_TIA_RTUNE___S 26 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_RTUNE___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_RTUNE___S 26 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATB (0x005F8A38) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATB___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATB___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATB__D_TESTBB_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATB__D_TESTBB_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATB__D_BBF_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATB__D_TESTBB_I___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATB__D_TESTBB_I___S 29 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATB__D_TESTBB_Q___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATB__D_TESTBB_Q___S 26 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATB__D_BBF_ATB_SEL___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATB__D_BBF_ATB_SEL___S 23 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATB___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_ATB___S 23 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_SPARE0 (0x005F8A3C) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_SPARE0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_SPARE0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_SPARE0__D_TXBB_SPARE0___POR 0x000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_SPARE0__D_TXBB_SPARE0___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_SPARE0__D_TXBB_SPARE0___S 0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_SPARE0___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_SPARE0___S 0 + +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_SPARE1 (0x005F8A40) +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_SPARE1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_SPARE1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_SPARE1__D_TXBB_SPARE1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_SPARE1__D_TXBB_SPARE1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_SPARE1__D_TXBB_SPARE1___S 0 +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_SPARE1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXBB_CH1_SPARE1___S 0 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_TESTREG (0x005F9000) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_TESTREG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_TESTREG___POR 0x44FE5111 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_TESTREG__TESTREG___POR 0x44FE5111 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_TESTREG__TESTREG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_TESTREG__TESTREG___S 0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_TESTREG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_TESTREG___S 0 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL (0x005F9004) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL__FCS_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OV___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OVD___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL__LNA_GAIN_OVD___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OV___S 27 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OVD___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL__GM_GAIN_OVD___S 24 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL__FCS_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL__FCS_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LUT_IDX_SEL___S 22 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_0 (0x005F9008) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_0___POR 0x8C000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_0__LNA_LOAD_C_0___POR 0x8 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_0__LNA_INP_NOTCH_CTUNE_0___POR 0xC +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_0__LNA_INP_NOTCH_CTUNE_SW_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_0__LNA_INP_SRC_IND_SW_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_0__LNA_LOAD_C_0___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_0__LNA_LOAD_C_0___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_0__LNA_INP_NOTCH_CTUNE_0___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_0__LNA_INP_NOTCH_CTUNE_0___S 24 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_0__LNA_INP_NOTCH_CTUNE_SW_0___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_0__LNA_INP_NOTCH_CTUNE_SW_0___S 20 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_0__LNA_INP_SRC_IND_SW_0___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_0__LNA_INP_SRC_IND_SW_0___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_0___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_0___S 19 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_1 (0x005F900C) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_1___POR 0x30C00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_1__LNA_LOAD_C_1___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_1__LNA_INP_NOTCH_CTUNE_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_1__LNA_INP_NOTCH_CTUNE_SW_1___POR 0xC +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_1__LNA_INP_SRC_IND_SW_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_1__LNA_LOAD_C_1___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_1__LNA_LOAD_C_1___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_1__LNA_INP_NOTCH_CTUNE_1___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_1__LNA_INP_NOTCH_CTUNE_1___S 24 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_1__LNA_INP_NOTCH_CTUNE_SW_1___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_1__LNA_INP_NOTCH_CTUNE_SW_1___S 20 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_1__LNA_INP_SRC_IND_SW_1___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_1__LNA_INP_SRC_IND_SW_1___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_1___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_1_1___S 19 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0 (0x005F9010) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0___POR 0x62409760 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_RMATCH_0___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_GAIN_CTRL_0___POR 0x12 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_LOAD_R_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_OTA_EN_0___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_BIAS_0___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_AUX_CAP_0___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_MAIN_EN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_AUX_EN_0___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__NA_BIAS_OTA_BYPASS_0___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_RMATCH_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_RMATCH_0___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_GAIN_CTRL_0___M 0x1FE00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_GAIN_CTRL_0___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_LOAD_R_0___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_LOAD_R_0___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_OTA_EN_0___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_OTA_EN_0___S 15 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_BIAS_0___M 0x00007800 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_BIAS_0___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_AUX_CAP_0___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_AUX_CAP_0___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_MAIN_EN_0___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_MAIN_EN_0___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_AUX_EN_0___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__LNA_AUX_EN_0___S 6 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__NA_BIAS_OTA_BYPASS_0___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0__NA_BIAS_OTA_BYPASS_0___S 5 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0___M 0xFFFFFFE0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_0___S 5 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1 (0x005F9014) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1___POR 0x63009D60 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_RMATCH_1___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_GAIN_CTRL_1___POR 0x18 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_LOAD_R_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_OTA_EN_1___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_BIAS_1___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_AUX_CAP_1___POR 0x5 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_MAIN_EN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_AUX_EN_1___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__NA_BIAS_OTA_BYPASS_1___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_RMATCH_1___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_RMATCH_1___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_GAIN_CTRL_1___M 0x1FE00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_GAIN_CTRL_1___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_LOAD_R_1___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_LOAD_R_1___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_OTA_EN_1___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_OTA_EN_1___S 15 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_BIAS_1___M 0x00007800 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_BIAS_1___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_AUX_CAP_1___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_AUX_CAP_1___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_MAIN_EN_1___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_MAIN_EN_1___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_AUX_EN_1___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__LNA_AUX_EN_1___S 6 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__NA_BIAS_OTA_BYPASS_1___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1__NA_BIAS_OTA_BYPASS_1___S 5 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1___M 0xFFFFFFE0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_1___S 5 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2 (0x005F9018) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2___POR 0x6360A360 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_RMATCH_2___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_GAIN_CTRL_2___POR 0x1B +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_LOAD_R_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_OTA_EN_2___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_BIAS_2___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_AUX_CAP_2___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_MAIN_EN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_AUX_EN_2___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__NA_BIAS_OTA_BYPASS_2___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_RMATCH_2___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_RMATCH_2___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_GAIN_CTRL_2___M 0x1FE00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_GAIN_CTRL_2___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_LOAD_R_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_LOAD_R_2___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_OTA_EN_2___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_OTA_EN_2___S 15 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_BIAS_2___M 0x00007800 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_BIAS_2___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_AUX_CAP_2___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_AUX_CAP_2___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_MAIN_EN_2___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_MAIN_EN_2___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_AUX_EN_2___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__LNA_AUX_EN_2___S 6 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__NA_BIAS_OTA_BYPASS_2___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2__NA_BIAS_OTA_BYPASS_2___S 5 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2___M 0xFFFFFFE0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_2___S 5 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3 (0x005F901C) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3___POR 0x6380A860 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_RMATCH_3___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_GAIN_CTRL_3___POR 0x1C +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_LOAD_R_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_OTA_EN_3___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_BIAS_3___POR 0x5 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_AUX_CAP_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_MAIN_EN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_AUX_EN_3___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__NA_BIAS_OTA_BYPASS_3___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_RMATCH_3___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_RMATCH_3___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_GAIN_CTRL_3___M 0x1FE00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_GAIN_CTRL_3___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_LOAD_R_3___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_LOAD_R_3___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_OTA_EN_3___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_OTA_EN_3___S 15 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_BIAS_3___M 0x00007800 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_BIAS_3___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_AUX_CAP_3___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_AUX_CAP_3___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_MAIN_EN_3___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_MAIN_EN_3___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_AUX_EN_3___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__LNA_AUX_EN_3___S 6 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__NA_BIAS_OTA_BYPASS_3___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3__NA_BIAS_OTA_BYPASS_3___S 5 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3___M 0xFFFFFFE0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_3___S 5 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4 (0x005F9020) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4___POR 0x628E9080 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_RMATCH_4___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_GAIN_CTRL_4___POR 0x14 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_LOAD_R_4___POR 0x0E +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_OTA_EN_4___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_BIAS_4___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_AUX_CAP_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_MAIN_EN_4___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_AUX_EN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__NA_BIAS_OTA_BYPASS_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_RMATCH_4___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_RMATCH_4___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_GAIN_CTRL_4___M 0x1FE00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_GAIN_CTRL_4___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_LOAD_R_4___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_LOAD_R_4___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_OTA_EN_4___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_OTA_EN_4___S 15 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_BIAS_4___M 0x00007800 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_BIAS_4___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_AUX_CAP_4___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_AUX_CAP_4___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_MAIN_EN_4___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_MAIN_EN_4___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_AUX_EN_4___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__LNA_AUX_EN_4___S 6 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__NA_BIAS_OTA_BYPASS_4___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4__NA_BIAS_OTA_BYPASS_4___S 5 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4___M 0xFFFFFFE0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_4___S 5 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5 (0x005F9024) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5___POR 0x62809080 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_RMATCH_5___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_GAIN_CTRL_5___POR 0x14 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_LOAD_R_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_OTA_EN_5___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_BIAS_5___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_AUX_CAP_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_MAIN_EN_5___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_AUX_EN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__NA_BIAS_OTA_BYPASS_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_RMATCH_5___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_RMATCH_5___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_GAIN_CTRL_5___M 0x1FE00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_GAIN_CTRL_5___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_LOAD_R_5___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_LOAD_R_5___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_OTA_EN_5___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_OTA_EN_5___S 15 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_BIAS_5___M 0x00007800 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_BIAS_5___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_AUX_CAP_5___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_AUX_CAP_5___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_MAIN_EN_5___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_MAIN_EN_5___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_AUX_EN_5___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__LNA_AUX_EN_5___S 6 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__NA_BIAS_OTA_BYPASS_5___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5__NA_BIAS_OTA_BYPASS_5___S 5 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5___M 0xFFFFFFE0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_5___S 5 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6 (0x005F9028) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6___POR 0x03E29880 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_RMATCH_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_GAIN_CTRL_6___POR 0x1F +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_LOAD_R_6___POR 0x02 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_OTA_EN_6___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_BIAS_6___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_AUX_CAP_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_MAIN_EN_6___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_AUX_EN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__NA_BIAS_OTA_BYPASS_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_RMATCH_6___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_RMATCH_6___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_GAIN_CTRL_6___M 0x1FE00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_GAIN_CTRL_6___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_LOAD_R_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_LOAD_R_6___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_OTA_EN_6___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_OTA_EN_6___S 15 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_BIAS_6___M 0x00007800 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_BIAS_6___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_AUX_CAP_6___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_AUX_CAP_6___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_MAIN_EN_6___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_MAIN_EN_6___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_AUX_EN_6___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__LNA_AUX_EN_6___S 6 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__NA_BIAS_OTA_BYPASS_6___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6__NA_BIAS_OTA_BYPASS_6___S 5 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6___M 0xFFFFFFE0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_6___S 5 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7 (0x005F902C) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7___POR 0x06209080 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_RMATCH_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_GAIN_CTRL_7___POR 0x31 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_LOAD_R_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_OTA_EN_7___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_BIAS_7___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_AUX_CAP_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_MAIN_EN_7___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_AUX_EN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__NA_BIAS_OTA_BYPASS_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_RMATCH_7___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_RMATCH_7___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_GAIN_CTRL_7___M 0x1FE00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_GAIN_CTRL_7___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_LOAD_R_7___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_LOAD_R_7___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_OTA_EN_7___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_OTA_EN_7___S 15 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_BIAS_7___M 0x00007800 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_BIAS_7___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_AUX_CAP_7___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_AUX_CAP_7___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_MAIN_EN_7___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_MAIN_EN_7___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_AUX_EN_7___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__LNA_AUX_EN_7___S 6 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__NA_BIAS_OTA_BYPASS_7___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7__NA_BIAS_OTA_BYPASS_7___S 5 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7___M 0xFFFFFFE0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_LNA_0_7___S 5 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_0 (0x005F9030) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_0___POR 0x0A320000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_0__GM_GAIN_BYP_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_0__GM_GAIN_NCTRL_0___POR 0x05 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_0__GM_GAIN_PCTRL_0___POR 0x06 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_0__GM_BIAS_0___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_0__GM_GAIN_BYP_0___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_0__GM_GAIN_BYP_0___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_0__GM_GAIN_NCTRL_0___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_0__GM_GAIN_NCTRL_0___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_0__GM_GAIN_PCTRL_0___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_0__GM_GAIN_PCTRL_0___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_0__GM_BIAS_0___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_0__GM_BIAS_0___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_0___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_0___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_1 (0x005F9034) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_1___POR 0x0A320000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_1__GM_GAIN_BYP_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_1__GM_GAIN_NCTRL_1___POR 0x05 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_1__GM_GAIN_PCTRL_1___POR 0x06 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_1__GM_BIAS_1___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_1__GM_GAIN_BYP_1___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_1__GM_GAIN_BYP_1___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_1__GM_GAIN_NCTRL_1___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_1__GM_GAIN_NCTRL_1___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_1__GM_GAIN_PCTRL_1___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_1__GM_GAIN_PCTRL_1___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_1__GM_BIAS_1___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_1__GM_BIAS_1___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_1___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_1___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_2 (0x005F9038) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_2___POR 0x14520000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_2__GM_GAIN_BYP_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_2__GM_GAIN_NCTRL_2___POR 0x0A +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_2__GM_GAIN_PCTRL_2___POR 0x0A +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_2__GM_BIAS_2___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_2__GM_GAIN_BYP_2___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_2__GM_GAIN_BYP_2___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_2__GM_GAIN_NCTRL_2___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_2__GM_GAIN_NCTRL_2___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_2__GM_GAIN_PCTRL_2___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_2__GM_GAIN_PCTRL_2___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_2__GM_BIAS_2___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_2__GM_BIAS_2___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_2___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_2___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_3 (0x005F903C) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_3___POR 0x1E7A0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_3__GM_GAIN_BYP_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_3__GM_GAIN_NCTRL_3___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_3__GM_GAIN_PCTRL_3___POR 0x0F +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_3__GM_BIAS_3___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_3__GM_GAIN_BYP_3___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_3__GM_GAIN_BYP_3___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_3__GM_GAIN_NCTRL_3___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_3__GM_GAIN_NCTRL_3___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_3__GM_GAIN_PCTRL_3___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_3__GM_GAIN_PCTRL_3___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_3__GM_BIAS_3___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_3__GM_BIAS_3___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_3___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_3___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_4 (0x005F9040) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_4___POR 0x28930000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_4__GM_GAIN_BYP_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_4__GM_GAIN_NCTRL_4___POR 0x14 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_4__GM_GAIN_PCTRL_4___POR 0x12 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_4__GM_BIAS_4___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_4__GM_GAIN_BYP_4___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_4__GM_GAIN_BYP_4___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_4__GM_GAIN_NCTRL_4___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_4__GM_GAIN_NCTRL_4___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_4__GM_GAIN_PCTRL_4___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_4__GM_GAIN_PCTRL_4___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_4__GM_BIAS_4___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_4__GM_BIAS_4___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_4___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_4___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_5 (0x005F9044) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_5___POR 0x3CC20000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_5__GM_GAIN_BYP_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_5__GM_GAIN_NCTRL_5___POR 0x1E +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_5__GM_GAIN_PCTRL_5___POR 0x18 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_5__GM_BIAS_5___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_5__GM_GAIN_BYP_5___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_5__GM_GAIN_BYP_5___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_5__GM_GAIN_NCTRL_5___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_5__GM_GAIN_NCTRL_5___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_5__GM_GAIN_PCTRL_5___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_5__GM_GAIN_PCTRL_5___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_5__GM_BIAS_5___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_5__GM_BIAS_5___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_5___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_5___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_6 (0x005F9048) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_6___POR 0x65A90000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_6__GM_GAIN_BYP_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_6__GM_GAIN_NCTRL_6___POR 0x32 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_6__GM_GAIN_PCTRL_6___POR 0x35 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_6__GM_BIAS_6___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_6__GM_GAIN_BYP_6___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_6__GM_GAIN_BYP_6___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_6__GM_GAIN_NCTRL_6___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_6__GM_GAIN_NCTRL_6___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_6__GM_GAIN_PCTRL_6___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_6__GM_GAIN_PCTRL_6___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_6__GM_BIAS_6___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_6__GM_BIAS_6___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_6___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_6___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_7 (0x005F904C) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_7___POR 0x65A90000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_7__GM_GAIN_BYP_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_7__GM_GAIN_NCTRL_7___POR 0x32 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_7__GM_GAIN_PCTRL_7___POR 0x35 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_7__GM_BIAS_7___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_7__GM_GAIN_BYP_7___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_7__GM_GAIN_BYP_7___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_7__GM_GAIN_NCTRL_7___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_7__GM_GAIN_NCTRL_7___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_7__GM_GAIN_PCTRL_7___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_7__GM_GAIN_PCTRL_7___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_7__GM_BIAS_7___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_7__GM_BIAS_7___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_7___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_GM_0_7___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0 (0x005F9080) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_RMATCH_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_RMATCH_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_GAIN_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_GAIN_CTRL_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_LOAD_R_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_LOAD_R_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_OTA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_BIAS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_BIAS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_AUX_CAP_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_AUX_CAP_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_RMATCH_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_RMATCH_OV___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_RMATCH_OVD___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_RMATCH_OVD___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_GAIN_CTRL_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_GAIN_CTRL_OV___S 27 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_GAIN_CTRL_OVD___M 0x07F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_GAIN_CTRL_OVD___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_LOAD_R_OV___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_LOAD_R_OV___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_LOAD_R_OVD___M 0x0003E000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_LOAD_R_OVD___S 13 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_OTA_EN_OVS___M 0x00001800 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_OTA_EN_OVS___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_BIAS_OV___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_BIAS_OV___S 10 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_BIAS_OVD___M 0x000003C0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_BIAS_OVD___S 6 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_AUX_CAP_OV___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_AUX_CAP_OV___S 5 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_AUX_CAP_OVD___M 0x0000001C +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0__LNA_AUX_CAP_OVD___S 2 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0___M 0xFFFFFFFC +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0___S 2 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0_EXT (0x005F9084) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0_EXT___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0_EXT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0_EXT__LNA_MAIN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0_EXT__LNA_AUX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0_EXT__LNA_BIAS_OTA_BYPASS_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0_EXT__LNA_MAIN_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0_EXT__LNA_MAIN_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0_EXT__LNA_AUX_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0_EXT__LNA_AUX_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0_EXT__LNA_BIAS_OTA_BYPASS_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0_EXT__LNA_BIAS_OTA_BYPASS_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0_EXT___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV0_EXT___S 26 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1 (0x005F9088) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_GAIN_BYP_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_GAIN_NCTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_GAIN_NCTRL_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_GAIN_PCTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_GAIN_PCTRL_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_BIAS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_BIAS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_GAIN_BYP_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_GAIN_BYP_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_GAIN_NCTRL_OV___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_GAIN_NCTRL_OV___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_GAIN_NCTRL_OVD___M 0x1F800000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_GAIN_NCTRL_OVD___S 23 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_GAIN_PCTRL_OV___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_GAIN_PCTRL_OV___S 22 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_GAIN_PCTRL_OVD___M 0x003F0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_GAIN_PCTRL_OVD___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_BIAS_OV___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_BIAS_OV___S 15 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_BIAS_OVD___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1__GM_BIAS_OVD___S 12 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV1___S 12 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2 (0x005F908C) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_LOAD_C_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_LOAD_C_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_INP_NOTCH_CTUNE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_INP_NOTCH_CTUNE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_INP_NOTCH_CTUNE_SW_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_INP_NOTCH_CTUNE_SW_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_INP_SRC_IND_SW_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_LOAD_C_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_LOAD_C_OV___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_LOAD_C_OVD___M 0x78000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_LOAD_C_OVD___S 27 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_INP_NOTCH_CTUNE_OV___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_INP_NOTCH_CTUNE_OV___S 26 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_INP_NOTCH_CTUNE_OVD___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_INP_NOTCH_CTUNE_OVD___S 22 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_INP_NOTCH_CTUNE_SW_OV___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_INP_NOTCH_CTUNE_SW_OV___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_INP_NOTCH_CTUNE_SW_OVD___M 0x001E0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_INP_NOTCH_CTUNE_SW_OVD___S 17 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_INP_SRC_IND_SW_OVS___M 0x00018000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2__LNA_INP_SRC_IND_SW_OVS___S 15 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2___M 0xFFFF8000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_LUT_OV2___S 15 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0 (0x005F9090) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__GM_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__LNA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__LNA_FC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__MIX_EN_I_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__MIX_EN_Q_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__CALRTX_SW_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__DPD_XPA_SW_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__DPD_IPA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_OBUF25DC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_LP_OBUF25DC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_INBUF25DC1ST_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_LP_INBUF25DC1ST_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_INBUF25DC2ND_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_LP_INBUF25DC2ND_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__MIXLP_EN_I_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__MIXLP_EN_Q_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__GM_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__GM_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__LNA_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__LNA_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__LNA_FC_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__LNA_FC_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__MIX_EN_I_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__MIX_EN_I_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__MIX_EN_Q_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__MIX_EN_Q_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__CALRTX_SW_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__CALRTX_SW_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__DPD_XPA_SW_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__DPD_XPA_SW_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__DPD_IPA_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__DPD_IPA_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_OBUF25DC_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_OBUF25DC_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_LP_OBUF25DC_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_LP_OBUF25DC_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_INBUF25DC1ST_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_INBUF25DC1ST_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_LP_INBUF25DC1ST_EN_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_LP_INBUF25DC1ST_EN_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_INBUF25DC2ND_EN_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_INBUF25DC2ND_EN_OVS___S 6 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_LP_INBUF25DC2ND_EN_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__RXLO_LP_INBUF25DC2ND_EN_OVS___S 4 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__MIXLP_EN_I_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__MIXLP_EN_I_OVS___S 2 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__MIXLP_EN_Q_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0__MIXLP_EN_Q_OVS___S 0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV0___S 0 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV1 (0x005F9094) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV1__AGC_PKDET_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV1__AGC_PKDET_COMP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV1__AGC_PKDET_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV1__AGC_PKDET_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV1__AGC_PKDET_COMP_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV1__AGC_PKDET_COMP_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OV___S 27 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OVD___M 0x07F00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV1__AGC_PKDET_DCOC_RES_OVD___S 20 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV1___M 0xFFF00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_OV1___S 20 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_RXFE_LUT_IDX_SEL (0x005F9098) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_RXFE_LUT_IDX_SEL___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_RXFE_LUT_IDX_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_RXFE_LUT_IDX_SEL__RO_FCS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_RXFE_LUT_IDX_SEL__RO_LNA_GAIN___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_RXFE_LUT_IDX_SEL__RO_GM_GAIN___S 26 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_RXFE_LUT_IDX_SEL__RO_FCS___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_RXFE_LUT_IDX_SEL__RO_FCS___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_RXFE_LUT_IDX_SEL___M 0xFE000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_RXFE_LUT_IDX_SEL___S 25 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0 (0x005F909C) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_RMATCH___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_GAIN_CTRL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_LOAD_R___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_OTA_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_BIAS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_AUX_CAP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_MAIN_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_AUX_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_BIAS_OTA_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_RMATCH___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_RMATCH___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_GAIN_CTRL___M 0x1FE00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_GAIN_CTRL___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_LOAD_R___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_LOAD_R___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_OTA_EN___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_OTA_EN___S 15 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_BIAS___M 0x00007800 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_BIAS___S 11 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_AUX_CAP___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_AUX_CAP___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_MAIN_EN___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_MAIN_EN___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_AUX_EN___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_AUX_EN___S 6 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_BIAS_OTA_BYPASS___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0__RO_LNA_BIAS_OTA_BYPASS___S 5 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0___M 0xFFFFFFE0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT0___S 5 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT1 (0x005F90A0) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT1__RO_GM_GAIN_BYP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT1__RO_GM_GAIN_NCTRL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT1__RO_GM_GAIN_PCTRL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT1__RO_GM_BIAS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT1__RO_GM_GAIN_BYP___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT1__RO_GM_GAIN_BYP___S 31 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT1__RO_GM_GAIN_NCTRL___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT1__RO_GM_GAIN_NCTRL___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT1__RO_GM_GAIN_PCTRL___M 0x01F80000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT1__RO_GM_GAIN_PCTRL___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT1__RO_GM_BIAS___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT1__RO_GM_BIAS___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT1___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT1___S 16 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT2 (0x005F90A4) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT2__RO_LNA_LOAD_C___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT2__RO_LNA_INP_NOTCH_CTUNE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT2__RO_LNA_INP_NOTCH_CTUNE_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT2__RO_LNA_INP_SRC_IND_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT2__RO_LNA_LOAD_C___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT2__RO_LNA_LOAD_C___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT2__RO_LNA_INP_NOTCH_CTUNE___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT2__RO_LNA_INP_NOTCH_CTUNE___S 24 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT2__RO_LNA_INP_NOTCH_CTUNE_SW___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT2__RO_LNA_INP_NOTCH_CTUNE_SW___S 20 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT2__RO_LNA_INP_SRC_IND_SW___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT2__RO_LNA_INP_SRC_IND_SW___S 19 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT2___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_WL_RXFE_LUT2___S 19 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0 (0x005F90A8) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0___POR 0x20280E00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__D_AGC_PKDET_BW___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__D_AGC_PKDET_THRES___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__D_AGC_PKDET_DCOC_RANGE___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__D_AGC_PKDET_GAIN___POR 0x2 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__D_AGC_PKDET_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__AGC_PKDET_DCOC_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__AGC_PKDET_DCOC_SETT___POR 0x7 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__D_AGC_PKDET_BW___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__D_AGC_PKDET_BW___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__D_AGC_PKDET_THRES___M 0x1FC00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__D_AGC_PKDET_THRES___S 22 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__D_AGC_PKDET_DCOC_RANGE___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__D_AGC_PKDET_DCOC_RANGE___S 20 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__D_AGC_PKDET_GAIN___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__D_AGC_PKDET_GAIN___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__D_AGC_PKDET_ATB_SEL___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__D_AGC_PKDET_ATB_SEL___S 17 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__AGC_PKDET_DCOC_EN___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__AGC_PKDET_DCOC_EN___S 12 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__AGC_PKDET_DCOC_SETT___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0__AGC_PKDET_DCOC_SETT___S 9 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0___M 0xFFFE1E00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_AGC_CAL_0___S 9 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_AGC_CAL (0x005F90AC) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_AGC_CAL___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_AGC_CAL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_VALID___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_SAT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES_EFFECT___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_VALID___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_VALID___S 15 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_SAT___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_SAT___S 14 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES_EFFECT___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES_EFFECT___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_AGC_CAL__RO_AGC_PKDET_DCOC_RES___S 0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_AGC_CAL___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_RO_AGC_CAL___S 0 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0 (0x005F90B0) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0___POR 0x520103C0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_CM_BIAS___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_IC_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_IRTT_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_VCM___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_RDGEN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_IC_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_IRTT_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_BIAS_SHORTR_OTA___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_CM_BIAS___POR 0x3 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_CASOFF_MAIN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_CASOFF_AUX___POR 0x1 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_CM_BIAS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_CM_BIAS___S 30 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_IC_EN___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_IC_EN___S 29 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_IRTT_EN___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_IRTT_EN___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_VCM___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_VCM___S 25 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_RDGEN___M 0x01E00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_RDGEN___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_ATB_SEL___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_GM_ATB_SEL___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_IC_EN___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_IC_EN___S 17 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_IRTT_EN___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_IRTT_EN___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_BIAS_SHORTR_OTA___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_BIAS_SHORTR_OTA___S 15 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_ATB_SEL___M 0x00003C00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_ATB_SEL___S 10 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_CM_BIAS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_CM_BIAS___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_CASOFF_MAIN___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_CASOFF_MAIN___S 7 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_CASOFF_AUX___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0__D_LNA_CASOFF_AUX___S 6 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0___M 0xFFFFBFC0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_CONTROL0___S 6 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1 (0x005F90B4) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1___POR 0x00FF00FF +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_ATB_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_LSB_I___POR 0xF +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_LSB_Q___POR 0xF +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_MSB_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_MSB_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_LPDUTYCODE_LSB_I___POR 0xF +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_LPDUTYCODE_LSB_Q___POR 0xF +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_ATB_SEL___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_ATB_SEL___S 24 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_LSB_I___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_LSB_I___S 20 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_LSB_Q___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_LSB_Q___S 16 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_MSB_I___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_MSB_I___S 12 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_MSB_Q___M 0x00000F00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_DUTYCODE_MSB_Q___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_LPDUTYCODE_LSB_I___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_LPDUTYCODE_LSB_I___S 4 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_LPDUTYCODE_LSB_Q___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1__D_RXLO_LPDUTYCODE_LSB_Q___S 0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL1___S 0 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2 (0x005F90B8) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2___POR 0x00968000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_RXLO_LPDUTYCODE_MSB_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_RXLO_LPDUTYCODE_MSB_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_BIAS_IC_CTRL___POR 0x4 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_BIAS_IRTT_OFFSET___POR 0x5 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_BIAS_IP_CTRL___POR 0x5 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_AGC_PKDET_OUT_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_AGC_PKDET_VREFRNG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_RXLO_LPDUTYCODE_MSB_I___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_RXLO_LPDUTYCODE_MSB_I___S 28 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_RXLO_LPDUTYCODE_MSB_Q___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_RXLO_LPDUTYCODE_MSB_Q___S 24 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_BIAS_IC_CTRL___M 0x00E00000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_BIAS_IC_CTRL___S 21 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_BIAS_IRTT_OFFSET___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_BIAS_IRTT_OFFSET___S 18 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_BIAS_IP_CTRL___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_BIAS_IP_CTRL___S 15 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_AGC_PKDET_OUT_ATB_SEL___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_AGC_PKDET_OUT_ATB_SEL___S 14 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_AGC_PKDET_VREFRNG___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2__D_AGC_PKDET_VREFRNG___S 12 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_W_RXFE_CONTROL2___S 12 + +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_SPARE (0x005F90BC) +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_SPARE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_SPARE___POR 0x00000200 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_SPARE__D_RXFE_SPARE___POR 0x000002 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_SPARE__D_RXFE_SPARE___M 0xFFFFFF00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_SPARE__D_RXFE_SPARE___S 8 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_SPARE___M 0xFFFFFF00 +#define PHYA_IRON2G_RFA_WL_RXFE_5G_CH1_WL_RXFE_SPARE___S 8 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_TESTREG (0x005F9300) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_TESTREG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_TESTREG___POR 0x33FE5111 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_TESTREG__TESTREG___POR 0x33FE5111 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_TESTREG__TESTREG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_TESTREG__TESTREG___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_TESTREG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_TESTREG___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL (0x005F9304) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__FCS_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OV___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__UPC_GAIN_OVD___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OV___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__DA_GAIN_OVD___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__FCS_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__FCS_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OV___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL__IPA_GAIN_OVD___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LUT_IDX_SEL___S 16 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_0 (0x005F9308) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_0___POR 0x04101800 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE3FLO_0___POR 0x01 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE1FLO_0___POR 0x01 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_0__DA_CTUNE_0___POR 0x01 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_0__UPC_LSW_EN_0___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE3FLO_0___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE3FLO_0___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE1FLO_0___M 0x03F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_0__UPC_CTUNE1FLO_0___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_0__DA_CTUNE_0___M 0x0001F000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_0__DA_CTUNE_0___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_0__UPC_LSW_EN_0___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_0__UPC_LSW_EN_0___S 11 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_0___M 0xFFF1F800 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_0___S 11 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_1 (0x005F930C) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_1___POR 0x04101800 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE3FLO_1___POR 0x01 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE1FLO_1___POR 0x01 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_1__DA_CTUNE_1___POR 0x01 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_1__UPC_LSW_EN_1___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE3FLO_1___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE3FLO_1___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE1FLO_1___M 0x03F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_1__UPC_CTUNE1FLO_1___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_1__DA_CTUNE_1___M 0x0001F000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_1__DA_CTUNE_1___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_1__UPC_LSW_EN_1___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_1__UPC_LSW_EN_1___S 11 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_1___M 0xFFF1F800 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CTUNE_LUT_1___S 11 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_0 (0x005F9310) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_0__DA_CELL_EN_0___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_0__DA_CELL_AUX_EN_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_0__DA_CASOFF_BIAS_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_0__DA_CELL_EN_0___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_0__DA_CELL_EN_0___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_0__DA_CELL_AUX_EN_0___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_0__DA_CELL_AUX_EN_0___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_0__DA_CASOFF_BIAS_0___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_0__DA_CASOFF_BIAS_0___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_0___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_0___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_1 (0x005F9314) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_1__DA_CELL_EN_1___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_1__DA_CELL_AUX_EN_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_1__DA_CASOFF_BIAS_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_1__DA_CELL_EN_1___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_1__DA_CELL_EN_1___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_1__DA_CELL_AUX_EN_1___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_1__DA_CELL_AUX_EN_1___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_1__DA_CASOFF_BIAS_1___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_1__DA_CASOFF_BIAS_1___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_1___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_1___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_2 (0x005F9318) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_2__DA_CELL_EN_2___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_2__DA_CELL_AUX_EN_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_2__DA_CASOFF_BIAS_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_2__DA_CELL_EN_2___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_2__DA_CELL_EN_2___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_2__DA_CELL_AUX_EN_2___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_2__DA_CELL_AUX_EN_2___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_2__DA_CASOFF_BIAS_2___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_2__DA_CASOFF_BIAS_2___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_2___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_2___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_3 (0x005F931C) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_3__DA_CELL_EN_3___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_3__DA_CELL_AUX_EN_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_3__DA_CASOFF_BIAS_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_3__DA_CELL_EN_3___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_3__DA_CELL_EN_3___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_3__DA_CELL_AUX_EN_3___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_3__DA_CELL_AUX_EN_3___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_3__DA_CASOFF_BIAS_3___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_3__DA_CASOFF_BIAS_3___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_3___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_3___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_4 (0x005F9320) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_4__DA_CELL_EN_4___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_4__DA_CELL_AUX_EN_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_4__DA_CASOFF_BIAS_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_4__DA_CELL_EN_4___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_4__DA_CELL_EN_4___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_4__DA_CELL_AUX_EN_4___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_4__DA_CELL_AUX_EN_4___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_4__DA_CASOFF_BIAS_4___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_4__DA_CASOFF_BIAS_4___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_4___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_4___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_5 (0x005F9324) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_5__DA_CELL_EN_5___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_5__DA_CELL_AUX_EN_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_5__DA_CASOFF_BIAS_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_5__DA_CELL_EN_5___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_5__DA_CELL_EN_5___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_5__DA_CELL_AUX_EN_5___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_5__DA_CELL_AUX_EN_5___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_5__DA_CASOFF_BIAS_5___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_5__DA_CASOFF_BIAS_5___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_5___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_5___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_6 (0x005F9328) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_6__DA_CELL_EN_6___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_6__DA_CELL_AUX_EN_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_6__DA_CASOFF_BIAS_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_6__DA_CELL_EN_6___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_6__DA_CELL_EN_6___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_6__DA_CELL_AUX_EN_6___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_6__DA_CELL_AUX_EN_6___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_6__DA_CASOFF_BIAS_6___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_6__DA_CASOFF_BIAS_6___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_6___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_6___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_7 (0x005F932C) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_7__DA_CELL_EN_7___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_7__DA_CELL_AUX_EN_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_7__DA_CASOFF_BIAS_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_7__DA_CELL_EN_7___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_7__DA_CELL_EN_7___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_7__DA_CELL_AUX_EN_7___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_7__DA_CELL_AUX_EN_7___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_7__DA_CASOFF_BIAS_7___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_7__DA_CASOFF_BIAS_7___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_7___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_7___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_8 (0x005F9330) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_8__DA_CELL_EN_8___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_8__DA_CELL_AUX_EN_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_8__DA_CASOFF_BIAS_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_8__DA_CELL_EN_8___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_8__DA_CELL_EN_8___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_8__DA_CELL_AUX_EN_8___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_8__DA_CELL_AUX_EN_8___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_8__DA_CASOFF_BIAS_8___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_8__DA_CASOFF_BIAS_8___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_8___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_8___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_9 (0x005F9334) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_9___POR 0x06009000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_9__DA_CELL_EN_9___POR 0x00C +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_9__DA_CELL_AUX_EN_9___POR 0x01 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_9__DA_CASOFF_BIAS_9___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_9__DA_CELL_EN_9___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_9__DA_CELL_EN_9___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_9__DA_CELL_AUX_EN_9___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_9__DA_CELL_AUX_EN_9___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_9__DA_CASOFF_BIAS_9___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_9__DA_CASOFF_BIAS_9___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_9___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_9___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_10 (0x005F9338) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_10___POR 0x07009000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_10__DA_CELL_EN_10___POR 0x00E +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_10__DA_CELL_AUX_EN_10___POR 0x01 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_10__DA_CASOFF_BIAS_10___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_10__DA_CELL_EN_10___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_10__DA_CELL_EN_10___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_10__DA_CELL_AUX_EN_10___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_10__DA_CELL_AUX_EN_10___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_10__DA_CASOFF_BIAS_10___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_10__DA_CASOFF_BIAS_10___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_10___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_10___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_11 (0x005F933C) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_11___POR 0x07819000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_11__DA_CELL_EN_11___POR 0x00F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_11__DA_CELL_AUX_EN_11___POR 0x03 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_11__DA_CASOFF_BIAS_11___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_11__DA_CELL_EN_11___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_11__DA_CELL_EN_11___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_11__DA_CELL_AUX_EN_11___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_11__DA_CELL_AUX_EN_11___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_11__DA_CASOFF_BIAS_11___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_11__DA_CASOFF_BIAS_11___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_11___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_11___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_12 (0x005F9340) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_12___POR 0x0A821000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_12__DA_CELL_EN_12___POR 0x015 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_12__DA_CELL_AUX_EN_12___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_12__DA_CASOFF_BIAS_12___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_12__DA_CELL_EN_12___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_12__DA_CELL_EN_12___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_12__DA_CELL_AUX_EN_12___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_12__DA_CELL_AUX_EN_12___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_12__DA_CASOFF_BIAS_12___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_12__DA_CASOFF_BIAS_12___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_12___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_12___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_13 (0x005F9344) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_13___POR 0x0B821000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_13__DA_CELL_EN_13___POR 0x017 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_13__DA_CELL_AUX_EN_13___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_13__DA_CASOFF_BIAS_13___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_13__DA_CELL_EN_13___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_13__DA_CELL_EN_13___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_13__DA_CELL_AUX_EN_13___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_13__DA_CELL_AUX_EN_13___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_13__DA_CASOFF_BIAS_13___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_13__DA_CASOFF_BIAS_13___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_13___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_13___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_14 (0x005F9348) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_14___POR 0x10821000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_14__DA_CELL_EN_14___POR 0x021 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_14__DA_CELL_AUX_EN_14___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_14__DA_CASOFF_BIAS_14___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_14__DA_CELL_EN_14___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_14__DA_CELL_EN_14___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_14__DA_CELL_AUX_EN_14___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_14__DA_CELL_AUX_EN_14___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_14__DA_CASOFF_BIAS_14___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_14__DA_CASOFF_BIAS_14___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_14___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_14___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_15 (0x005F934C) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_15___POR 0x11829000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_15__DA_CELL_EN_15___POR 0x023 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_15__DA_CELL_AUX_EN_15___POR 0x05 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_15__DA_CASOFF_BIAS_15___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_15__DA_CELL_EN_15___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_15__DA_CELL_EN_15___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_15__DA_CELL_AUX_EN_15___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_15__DA_CELL_AUX_EN_15___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_15__DA_CASOFF_BIAS_15___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_15__DA_CASOFF_BIAS_15___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_15___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_15___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_16 (0x005F9350) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_16___POR 0x13029000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_16__DA_CELL_EN_16___POR 0x026 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_16__DA_CELL_AUX_EN_16___POR 0x05 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_16__DA_CASOFF_BIAS_16___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_16__DA_CELL_EN_16___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_16__DA_CELL_EN_16___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_16__DA_CELL_AUX_EN_16___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_16__DA_CELL_AUX_EN_16___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_16__DA_CASOFF_BIAS_16___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_16__DA_CASOFF_BIAS_16___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_16___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_16___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_17 (0x005F9354) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_17___POR 0x14831000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_17__DA_CELL_EN_17___POR 0x029 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_17__DA_CELL_AUX_EN_17___POR 0x06 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_17__DA_CASOFF_BIAS_17___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_17__DA_CELL_EN_17___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_17__DA_CELL_EN_17___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_17__DA_CELL_AUX_EN_17___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_17__DA_CELL_AUX_EN_17___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_17__DA_CASOFF_BIAS_17___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_17__DA_CASOFF_BIAS_17___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_17___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_17___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_18 (0x005F9358) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_18___POR 0x18831000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_18__DA_CELL_EN_18___POR 0x031 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_18__DA_CELL_AUX_EN_18___POR 0x06 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_18__DA_CASOFF_BIAS_18___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_18__DA_CELL_EN_18___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_18__DA_CELL_EN_18___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_18__DA_CELL_AUX_EN_18___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_18__DA_CELL_AUX_EN_18___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_18__DA_CASOFF_BIAS_18___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_18__DA_CASOFF_BIAS_18___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_18___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_18___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_19 (0x005F935C) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_19___POR 0x1B031000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_19__DA_CELL_EN_19___POR 0x036 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_19__DA_CELL_AUX_EN_19___POR 0x06 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_19__DA_CASOFF_BIAS_19___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_19__DA_CELL_EN_19___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_19__DA_CELL_EN_19___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_19__DA_CELL_AUX_EN_19___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_19__DA_CELL_AUX_EN_19___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_19__DA_CASOFF_BIAS_19___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_19__DA_CASOFF_BIAS_19___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_19___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_19___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_20 (0x005F9360) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_20___POR 0x1D839000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_20__DA_CELL_EN_20___POR 0x03B +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_20__DA_CELL_AUX_EN_20___POR 0x07 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_20__DA_CASOFF_BIAS_20___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_20__DA_CELL_EN_20___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_20__DA_CELL_EN_20___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_20__DA_CELL_AUX_EN_20___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_20__DA_CELL_AUX_EN_20___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_20__DA_CASOFF_BIAS_20___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_20__DA_CASOFF_BIAS_20___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_20___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_20___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_21 (0x005F9364) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_21___POR 0x24841000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_21__DA_CELL_EN_21___POR 0x049 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_21__DA_CELL_AUX_EN_21___POR 0x08 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_21__DA_CASOFF_BIAS_21___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_21__DA_CELL_EN_21___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_21__DA_CELL_EN_21___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_21__DA_CELL_AUX_EN_21___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_21__DA_CELL_AUX_EN_21___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_21__DA_CASOFF_BIAS_21___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_21__DA_CASOFF_BIAS_21___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_21___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_21___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_22 (0x005F9368) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_22___POR 0x29849000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_22__DA_CELL_EN_22___POR 0x053 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_22__DA_CELL_AUX_EN_22___POR 0x09 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_22__DA_CASOFF_BIAS_22___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_22__DA_CELL_EN_22___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_22__DA_CELL_EN_22___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_22__DA_CELL_AUX_EN_22___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_22__DA_CELL_AUX_EN_22___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_22__DA_CASOFF_BIAS_22___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_22__DA_CASOFF_BIAS_22___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_22___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_22___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_23 (0x005F936C) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_23___POR 0x30861000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_23__DA_CELL_EN_23___POR 0x061 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_23__DA_CELL_AUX_EN_23___POR 0x0C +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_23__DA_CASOFF_BIAS_23___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_23__DA_CELL_EN_23___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_23__DA_CELL_EN_23___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_23__DA_CELL_AUX_EN_23___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_23__DA_CELL_AUX_EN_23___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_23__DA_CASOFF_BIAS_23___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_23__DA_CASOFF_BIAS_23___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_23___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_23___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_24 (0x005F9370) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_24___POR 0x34079000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_24__DA_CELL_EN_24___POR 0x068 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_24__DA_CELL_AUX_EN_24___POR 0x0F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_24__DA_CASOFF_BIAS_24___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_24__DA_CELL_EN_24___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_24__DA_CELL_EN_24___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_24__DA_CELL_AUX_EN_24___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_24__DA_CELL_AUX_EN_24___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_24__DA_CASOFF_BIAS_24___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_24__DA_CASOFF_BIAS_24___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_24___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_24___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_25 (0x005F9374) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_25___POR 0x3A0A1000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_25__DA_CELL_EN_25___POR 0x074 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_25__DA_CELL_AUX_EN_25___POR 0x14 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_25__DA_CASOFF_BIAS_25___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_25__DA_CELL_EN_25___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_25__DA_CELL_EN_25___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_25__DA_CELL_AUX_EN_25___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_25__DA_CELL_AUX_EN_25___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_25__DA_CASOFF_BIAS_25___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_25__DA_CASOFF_BIAS_25___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_25___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_25___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_26 (0x005F9378) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_26___POR 0x3E0C9000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_26__DA_CELL_EN_26___POR 0x07C +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_26__DA_CELL_AUX_EN_26___POR 0x19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_26__DA_CASOFF_BIAS_26___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_26__DA_CELL_EN_26___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_26__DA_CELL_EN_26___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_26__DA_CELL_AUX_EN_26___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_26__DA_CELL_AUX_EN_26___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_26__DA_CASOFF_BIAS_26___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_26__DA_CASOFF_BIAS_26___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_26___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_26___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_27 (0x005F937C) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_27___POR 0x4A0F9000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_27__DA_CELL_EN_27___POR 0x094 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_27__DA_CELL_AUX_EN_27___POR 0x1F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_27__DA_CASOFF_BIAS_27___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_27__DA_CELL_EN_27___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_27__DA_CELL_EN_27___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_27__DA_CELL_AUX_EN_27___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_27__DA_CELL_AUX_EN_27___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_27__DA_CASOFF_BIAS_27___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_27__DA_CASOFF_BIAS_27___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_27___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_27___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_28 (0x005F9380) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_28___POR 0x550F9000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_28__DA_CELL_EN_28___POR 0x0AA +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_28__DA_CELL_AUX_EN_28___POR 0x1F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_28__DA_CASOFF_BIAS_28___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_28__DA_CELL_EN_28___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_28__DA_CELL_EN_28___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_28__DA_CELL_AUX_EN_28___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_28__DA_CELL_AUX_EN_28___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_28__DA_CASOFF_BIAS_28___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_28__DA_CASOFF_BIAS_28___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_28___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_28___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_29 (0x005F9384) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_29___POR 0x5E0F9000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_29__DA_CELL_EN_29___POR 0x0BC +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_29__DA_CELL_AUX_EN_29___POR 0x1F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_29__DA_CASOFF_BIAS_29___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_29__DA_CELL_EN_29___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_29__DA_CELL_EN_29___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_29__DA_CELL_AUX_EN_29___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_29__DA_CELL_AUX_EN_29___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_29__DA_CASOFF_BIAS_29___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_29__DA_CASOFF_BIAS_29___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_29___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_29___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_30 (0x005F9388) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_30___POR 0x6D8F9000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_30__DA_CELL_EN_30___POR 0x0DB +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_30__DA_CELL_AUX_EN_30___POR 0x1F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_30__DA_CASOFF_BIAS_30___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_30__DA_CELL_EN_30___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_30__DA_CELL_EN_30___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_30__DA_CELL_AUX_EN_30___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_30__DA_CELL_AUX_EN_30___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_30__DA_CASOFF_BIAS_30___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_30__DA_CASOFF_BIAS_30___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_30___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_30___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_31 (0x005F938C) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_31___POR 0x7F8F9000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_31__DA_CELL_EN_31___POR 0x0FF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_31__DA_CELL_AUX_EN_31___POR 0x1F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_31__DA_CASOFF_BIAS_31___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_31__DA_CELL_EN_31___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_31__DA_CELL_EN_31___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_31__DA_CELL_AUX_EN_31___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_31__DA_CELL_AUX_EN_31___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_31__DA_CASOFF_BIAS_31___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_31__DA_CASOFF_BIAS_31___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_31___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA_LUT0_31___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_0 (0x005F9390) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_0__UPC_RGAIN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_0__UPC_RGAIN_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_0__UPC_RGAIN_0___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_0___S 29 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_1 (0x005F9394) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_1__UPC_RGAIN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_1__UPC_RGAIN_1___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_1__UPC_RGAIN_1___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_1___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_1___S 29 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_2 (0x005F9398) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_2__UPC_RGAIN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_2__UPC_RGAIN_2___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_2__UPC_RGAIN_2___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_2___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_2___S 29 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_3 (0x005F939C) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_3__UPC_RGAIN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_3__UPC_RGAIN_3___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_3__UPC_RGAIN_3___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_3___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_3___S 29 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_4 (0x005F93A0) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_4__UPC_RGAIN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_4__UPC_RGAIN_4___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_4__UPC_RGAIN_4___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_4___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_4___S 29 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_5 (0x005F93A4) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_5__UPC_RGAIN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_5__UPC_RGAIN_5___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_5__UPC_RGAIN_5___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_5___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_5___S 29 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_6 (0x005F93A8) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_6__UPC_RGAIN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_6__UPC_RGAIN_6___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_6__UPC_RGAIN_6___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_6___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_6___S 29 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_7 (0x005F93AC) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_7__UPC_RGAIN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_7__UPC_RGAIN_7___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_7__UPC_RGAIN_7___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_7___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC_LUT_7___S 29 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0 (0x005F93B0) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0___POR 0xD02EE80E +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_ILEVEL_0___POR 0x1A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_ILEVEL_B2_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_AUX1_0___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_AUX0_0___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_0___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_CASOFF_BIAS_0___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_CELL_EN_0___POR 0x007 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_VDD_SW_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_ILEVEL_0___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_ILEVEL_0___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_ILEVEL_B2_0___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_ILEVEL_B2_0___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_AUX1_0___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_AUX1_0___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_AUX0_0___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_AUX0_0___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_0___M 0x0000E000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_CAS_BIAS_0___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_CASOFF_BIAS_0___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_CASOFF_BIAS_0___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_CELL_EN_0___M 0x000003FE +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_CELL_EN_0___S 1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_VDD_SW_0___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0__PPA_VDD_SW_0___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_0___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1 (0x005F93B4) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1___POR 0xD02EE80E +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_ILEVEL_1___POR 0x1A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_ILEVEL_B2_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_AUX1_1___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_AUX0_1___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_1___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_CASOFF_BIAS_1___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_CELL_EN_1___POR 0x007 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_VDD_SW_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_ILEVEL_1___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_ILEVEL_1___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_ILEVEL_B2_1___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_ILEVEL_B2_1___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_AUX1_1___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_AUX1_1___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_AUX0_1___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_AUX0_1___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_1___M 0x0000E000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_CAS_BIAS_1___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_CASOFF_BIAS_1___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_CASOFF_BIAS_1___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_CELL_EN_1___M 0x000003FE +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_CELL_EN_1___S 1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_VDD_SW_1___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1__PPA_VDD_SW_1___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_1___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2 (0x005F93B8) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2___POR 0xD02EE81E +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_ILEVEL_2___POR 0x1A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_ILEVEL_B2_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_AUX1_2___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_AUX0_2___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_2___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_CASOFF_BIAS_2___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_CELL_EN_2___POR 0x00F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_VDD_SW_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_ILEVEL_2___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_ILEVEL_2___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_ILEVEL_B2_2___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_ILEVEL_B2_2___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_AUX1_2___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_AUX1_2___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_AUX0_2___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_AUX0_2___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_2___M 0x0000E000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_CAS_BIAS_2___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_CASOFF_BIAS_2___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_CASOFF_BIAS_2___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_CELL_EN_2___M 0x000003FE +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_CELL_EN_2___S 1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_VDD_SW_2___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2__PPA_VDD_SW_2___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_2___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3 (0x005F93BC) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3___POR 0xD02EE81E +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_ILEVEL_3___POR 0x1A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_ILEVEL_B2_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_AUX1_3___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_AUX0_3___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_3___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_CASOFF_BIAS_3___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_CELL_EN_3___POR 0x00F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_VDD_SW_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_ILEVEL_3___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_ILEVEL_3___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_ILEVEL_B2_3___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_ILEVEL_B2_3___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_AUX1_3___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_AUX1_3___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_AUX0_3___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_AUX0_3___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_3___M 0x0000E000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_CAS_BIAS_3___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_CASOFF_BIAS_3___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_CASOFF_BIAS_3___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_CELL_EN_3___M 0x000003FE +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_CELL_EN_3___S 1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_VDD_SW_3___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3__PPA_VDD_SW_3___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_3___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4 (0x005F93C0) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4___POR 0xD02EE87E +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_ILEVEL_4___POR 0x1A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_ILEVEL_B2_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_AUX1_4___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_AUX0_4___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_4___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_CASOFF_BIAS_4___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_CELL_EN_4___POR 0x03F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_VDD_SW_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_ILEVEL_4___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_ILEVEL_4___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_ILEVEL_B2_4___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_ILEVEL_B2_4___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_AUX1_4___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_AUX1_4___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_AUX0_4___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_AUX0_4___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_4___M 0x0000E000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_CAS_BIAS_4___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_CASOFF_BIAS_4___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_CASOFF_BIAS_4___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_CELL_EN_4___M 0x000003FE +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_CELL_EN_4___S 1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_VDD_SW_4___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4__PPA_VDD_SW_4___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_4___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5 (0x005F93C4) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5___POR 0xD02EE87E +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_ILEVEL_5___POR 0x1A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_ILEVEL_B2_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_AUX1_5___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_AUX0_5___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_5___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_CASOFF_BIAS_5___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_CELL_EN_5___POR 0x03F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_VDD_SW_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_ILEVEL_5___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_ILEVEL_5___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_ILEVEL_B2_5___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_ILEVEL_B2_5___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_AUX1_5___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_AUX1_5___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_AUX0_5___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_AUX0_5___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_5___M 0x0000E000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_CAS_BIAS_5___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_CASOFF_BIAS_5___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_CASOFF_BIAS_5___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_CELL_EN_5___M 0x000003FE +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_CELL_EN_5___S 1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_VDD_SW_5___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5__PPA_VDD_SW_5___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT0_5___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_0 (0x005F93D0) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_0___POR 0x57000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_0__PPA_CTUNE_0_FCSA___POR 0x0A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_0__PPA_CTUNE_DEQ_0_FCSA___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_0__PPA_RTUNE_0_FCSA___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_0__PPA_XFMR_SW_EN_0_FCSA___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_0__PPA_CTUNE_0_FCSA___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_0__PPA_CTUNE_0_FCSA___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_0__PPA_CTUNE_DEQ_0_FCSA___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_0__PPA_CTUNE_DEQ_0_FCSA___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_0__PPA_RTUNE_0_FCSA___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_0__PPA_RTUNE_0_FCSA___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_0__PPA_XFMR_SW_EN_0_FCSA___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_0__PPA_XFMR_SW_EN_0_FCSA___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_0___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_0___S 19 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_1 (0x005F93D4) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_1___POR 0x57000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_1__PPA_CTUNE_1_FCSA___POR 0x0A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_1__PPA_CTUNE_DEQ_1_FCSA___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_1__PPA_RTUNE_1_FCSA___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_1__PPA_XFMR_SW_EN_1_FCSA___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_1__PPA_CTUNE_1_FCSA___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_1__PPA_CTUNE_1_FCSA___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_1__PPA_CTUNE_DEQ_1_FCSA___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_1__PPA_CTUNE_DEQ_1_FCSA___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_1__PPA_RTUNE_1_FCSA___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_1__PPA_RTUNE_1_FCSA___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_1__PPA_XFMR_SW_EN_1_FCSA___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_1__PPA_XFMR_SW_EN_1_FCSA___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_1___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_1___S 19 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_2 (0x005F93D8) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_2___POR 0x57000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_2__PPA_CTUNE_2_FCSA___POR 0x0A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_2__PPA_CTUNE_DEQ_2_FCSA___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_2__PPA_RTUNE_2_FCSA___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_2__PPA_XFMR_SW_EN_2_FCSA___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_2__PPA_CTUNE_2_FCSA___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_2__PPA_CTUNE_2_FCSA___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_2__PPA_CTUNE_DEQ_2_FCSA___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_2__PPA_CTUNE_DEQ_2_FCSA___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_2__PPA_RTUNE_2_FCSA___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_2__PPA_RTUNE_2_FCSA___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_2__PPA_XFMR_SW_EN_2_FCSA___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_2__PPA_XFMR_SW_EN_2_FCSA___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_2___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_2___S 19 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_3 (0x005F93DC) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_3___POR 0x57000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_3__PPA_CTUNE_3_FCSA___POR 0x0A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_3__PPA_CTUNE_DEQ_3_FCSA___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_3__PPA_RTUNE_3_FCSA___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_3__PPA_XFMR_SW_EN_3_FCSA___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_3__PPA_CTUNE_3_FCSA___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_3__PPA_CTUNE_3_FCSA___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_3__PPA_CTUNE_DEQ_3_FCSA___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_3__PPA_CTUNE_DEQ_3_FCSA___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_3__PPA_RTUNE_3_FCSA___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_3__PPA_RTUNE_3_FCSA___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_3__PPA_XFMR_SW_EN_3_FCSA___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_3__PPA_XFMR_SW_EN_3_FCSA___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_3___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_3___S 19 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_4 (0x005F93E0) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_4___POR 0x57000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_4__PPA_CTUNE_4_FCSA___POR 0x0A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_4__PPA_CTUNE_DEQ_4_FCSA___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_4__PPA_RTUNE_4_FCSA___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_4__PPA_XFMR_SW_EN_4_FCSA___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_4__PPA_CTUNE_4_FCSA___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_4__PPA_CTUNE_4_FCSA___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_4__PPA_CTUNE_DEQ_4_FCSA___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_4__PPA_CTUNE_DEQ_4_FCSA___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_4__PPA_RTUNE_4_FCSA___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_4__PPA_RTUNE_4_FCSA___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_4__PPA_XFMR_SW_EN_4_FCSA___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_4__PPA_XFMR_SW_EN_4_FCSA___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_4___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_4___S 19 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_5 (0x005F93E4) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_5___POR 0x57000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_5__PPA_CTUNE_5_FCSA___POR 0x0A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_5__PPA_CTUNE_DEQ_5_FCSA___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_5__PPA_RTUNE_5_FCSA___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_5__PPA_XFMR_SW_EN_5_FCSA___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_5__PPA_CTUNE_5_FCSA___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_5__PPA_CTUNE_5_FCSA___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_5__PPA_CTUNE_DEQ_5_FCSA___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_5__PPA_CTUNE_DEQ_5_FCSA___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_5__PPA_RTUNE_5_FCSA___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_5__PPA_RTUNE_5_FCSA___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_5__PPA_XFMR_SW_EN_5_FCSA___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_5__PPA_XFMR_SW_EN_5_FCSA___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_5___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT1_5___S 19 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_0 (0x005F93F0) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_0___POR 0x57000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_0__PPA_CTUNE_0_FCSB___POR 0x0A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_0__PPA_CTUNE_DEQ_0_FCSB___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_0__PPA_RTUNE_0_FCSB___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_0__PPA_XFMR_SW_EN_0_FCSB___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_0__PPA_CTUNE_0_FCSB___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_0__PPA_CTUNE_0_FCSB___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_0__PPA_CTUNE_DEQ_0_FCSB___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_0__PPA_CTUNE_DEQ_0_FCSB___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_0__PPA_RTUNE_0_FCSB___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_0__PPA_RTUNE_0_FCSB___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_0__PPA_XFMR_SW_EN_0_FCSB___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_0__PPA_XFMR_SW_EN_0_FCSB___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_0___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_0___S 19 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_1 (0x005F93F4) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_1___POR 0x57000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_1__PPA_CTUNE_1_FCSB___POR 0x0A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_1__PPA_CTUNE_DEQ_1_FCSB___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_1__PPA_RTUNE_1_FCSB___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_1__PPA_XFMR_SW_EN_1_FCSB___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_1__PPA_CTUNE_1_FCSB___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_1__PPA_CTUNE_1_FCSB___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_1__PPA_CTUNE_DEQ_1_FCSB___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_1__PPA_CTUNE_DEQ_1_FCSB___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_1__PPA_RTUNE_1_FCSB___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_1__PPA_RTUNE_1_FCSB___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_1__PPA_XFMR_SW_EN_1_FCSB___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_1__PPA_XFMR_SW_EN_1_FCSB___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_1___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_1___S 19 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_2 (0x005F93F8) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_2___POR 0x57000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_2__PPA_CTUNE_2_FCSB___POR 0x0A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_2__PPA_CTUNE_DEQ_2_FCSB___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_2__PPA_RTUNE_2_FCSB___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_2__PPA_XFMR_SW_EN_2_FCSB___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_2__PPA_CTUNE_2_FCSB___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_2__PPA_CTUNE_2_FCSB___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_2__PPA_CTUNE_DEQ_2_FCSB___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_2__PPA_CTUNE_DEQ_2_FCSB___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_2__PPA_RTUNE_2_FCSB___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_2__PPA_RTUNE_2_FCSB___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_2__PPA_XFMR_SW_EN_2_FCSB___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_2__PPA_XFMR_SW_EN_2_FCSB___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_2___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_2___S 19 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_3 (0x005F93FC) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_3___POR 0x57000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_3__PPA_CTUNE_3_FCSB___POR 0x0A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_3__PPA_CTUNE_DEQ_3_FCSB___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_3__PPA_RTUNE_3_FCSB___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_3__PPA_XFMR_SW_EN_3_FCSB___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_3__PPA_CTUNE_3_FCSB___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_3__PPA_CTUNE_3_FCSB___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_3__PPA_CTUNE_DEQ_3_FCSB___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_3__PPA_CTUNE_DEQ_3_FCSB___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_3__PPA_RTUNE_3_FCSB___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_3__PPA_RTUNE_3_FCSB___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_3__PPA_XFMR_SW_EN_3_FCSB___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_3__PPA_XFMR_SW_EN_3_FCSB___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_3___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_3___S 19 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_4 (0x005F9400) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_4___POR 0x57000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_4__PPA_CTUNE_4_FCSB___POR 0x0A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_4__PPA_CTUNE_DEQ_4_FCSB___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_4__PPA_RTUNE_4_FCSB___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_4__PPA_XFMR_SW_EN_4_FCSB___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_4__PPA_CTUNE_4_FCSB___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_4__PPA_CTUNE_4_FCSB___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_4__PPA_CTUNE_DEQ_4_FCSB___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_4__PPA_CTUNE_DEQ_4_FCSB___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_4__PPA_RTUNE_4_FCSB___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_4__PPA_RTUNE_4_FCSB___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_4__PPA_XFMR_SW_EN_4_FCSB___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_4__PPA_XFMR_SW_EN_4_FCSB___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_4___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_4___S 19 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_5 (0x005F9404) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_5___POR 0x57000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_5__PPA_CTUNE_5_FCSB___POR 0x0A +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_5__PPA_CTUNE_DEQ_5_FCSB___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_5__PPA_RTUNE_5_FCSB___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_5__PPA_XFMR_SW_EN_5_FCSB___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_5__PPA_CTUNE_5_FCSB___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_5__PPA_CTUNE_5_FCSB___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_5__PPA_CTUNE_DEQ_5_FCSB___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_5__PPA_CTUNE_DEQ_5_FCSB___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_5__PPA_RTUNE_5_FCSB___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_5__PPA_RTUNE_5_FCSB___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_5__PPA_XFMR_SW_EN_5_FCSB___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_5__PPA_XFMR_SW_EN_5_FCSB___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_5___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT2_5___S 19 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_0 (0x005F9410) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_0___POR 0x07000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_0__PPA_CELL_AUX_EN_0___POR 0x07 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_0__PPA_CELL_AUX_EN_0___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_0__PPA_CELL_AUX_EN_0___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_0___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_0___S 24 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_1 (0x005F9414) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_1___POR 0x07000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_1__PPA_CELL_AUX_EN_1___POR 0x07 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_1__PPA_CELL_AUX_EN_1___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_1__PPA_CELL_AUX_EN_1___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_1___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_1___S 24 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_2 (0x005F9418) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_2___POR 0x0F000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_2__PPA_CELL_AUX_EN_2___POR 0x0F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_2__PPA_CELL_AUX_EN_2___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_2__PPA_CELL_AUX_EN_2___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_2___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_2___S 24 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_3 (0x005F941C) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_3___POR 0x0F000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_3__PPA_CELL_AUX_EN_3___POR 0x0F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_3__PPA_CELL_AUX_EN_3___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_3__PPA_CELL_AUX_EN_3___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_3___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_3___S 24 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_4 (0x005F9420) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_4___POR 0x3F000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_4__PPA_CELL_AUX_EN_4___POR 0x3F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_4__PPA_CELL_AUX_EN_4___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_4__PPA_CELL_AUX_EN_4___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_4___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_4___S 24 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_5 (0x005F9424) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_5___POR 0x3F000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_5__PPA_CELL_AUX_EN_5___POR 0x3F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_5__PPA_CELL_AUX_EN_5___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_5__PPA_CELL_AUX_EN_5___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_5___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA_LUT3_5___S 24 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0 (0x005F9430) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0___POR 0x882E3400 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_ILEVEL_0___POR 0x11 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_ILEVEL_B2_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX1_0___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX0_0___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_0___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_CASOFF_BIAS_0___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_ILEVEL_0___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_ILEVEL_0___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_ILEVEL_B2_0___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_ILEVEL_B2_0___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX1_0___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX1_0___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX0_0___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_AUX0_0___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_0___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_CAS_BIAS_0___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_CASOFF_BIAS_0___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0__PA_CASOFF_BIAS_0___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_0___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1 (0x005F9434) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1___POR 0x882E3400 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_ILEVEL_1___POR 0x11 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_ILEVEL_B2_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX1_1___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX0_1___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_1___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_CASOFF_BIAS_1___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_ILEVEL_1___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_ILEVEL_1___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_ILEVEL_B2_1___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_ILEVEL_B2_1___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX1_1___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX1_1___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX0_1___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_AUX0_1___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_1___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_CAS_BIAS_1___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_CASOFF_BIAS_1___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1__PA_CASOFF_BIAS_1___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_1___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2 (0x005F9438) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2___POR 0x882E3400 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_ILEVEL_2___POR 0x11 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_ILEVEL_B2_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX1_2___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX0_2___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_2___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_CASOFF_BIAS_2___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_ILEVEL_2___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_ILEVEL_2___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_ILEVEL_B2_2___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_ILEVEL_B2_2___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX1_2___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX1_2___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX0_2___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_AUX0_2___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_2___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_CAS_BIAS_2___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_CASOFF_BIAS_2___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2__PA_CASOFF_BIAS_2___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_2___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3 (0x005F943C) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3___POR 0x882E3400 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_ILEVEL_3___POR 0x11 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_ILEVEL_B2_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX1_3___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX0_3___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_3___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_CASOFF_BIAS_3___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_ILEVEL_3___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_ILEVEL_3___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_ILEVEL_B2_3___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_ILEVEL_B2_3___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX1_3___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX1_3___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX0_3___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_AUX0_3___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_3___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_CAS_BIAS_3___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_CASOFF_BIAS_3___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3__PA_CASOFF_BIAS_3___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_3___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4 (0x005F9440) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4___POR 0x882E3400 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_ILEVEL_4___POR 0x11 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_ILEVEL_B2_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX1_4___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX0_4___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_4___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_CASOFF_BIAS_4___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_ILEVEL_4___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_ILEVEL_4___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_ILEVEL_B2_4___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_ILEVEL_B2_4___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX1_4___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX1_4___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX0_4___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_AUX0_4___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_4___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_CAS_BIAS_4___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_CASOFF_BIAS_4___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4__PA_CASOFF_BIAS_4___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_4___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5 (0x005F9444) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5___POR 0x882E3400 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_ILEVEL_5___POR 0x11 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_ILEVEL_B2_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX1_5___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX0_5___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_5___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_CASOFF_BIAS_5___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_ILEVEL_5___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_ILEVEL_5___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_ILEVEL_B2_5___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_ILEVEL_B2_5___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX1_5___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX1_5___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX0_5___M 0x00070000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_AUX0_5___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_5___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_CAS_BIAS_5___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_CASOFF_BIAS_5___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5__PA_CASOFF_BIAS_5___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT0_5___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_0 (0x005F9450) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_0___POR 0x10040000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_0__PA_CELL_EN1_0___POR 0x040 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_0__PA_CELL_EN0_0___POR 0x040 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_0__PA_CELL_EN1_0___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_0__PA_CELL_EN1_0___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_0__PA_CELL_EN0_0___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_0__PA_CELL_EN0_0___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_0___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_0___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_1 (0x005F9454) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_1___POR 0x18050000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_1__PA_CELL_EN1_1___POR 0x060 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_1__PA_CELL_EN0_1___POR 0x050 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_1__PA_CELL_EN1_1___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_1__PA_CELL_EN1_1___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_1__PA_CELL_EN0_1___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_1__PA_CELL_EN0_1___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_1___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_1___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_2 (0x005F9458) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_2___POR 0x18050000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_2__PA_CELL_EN1_2___POR 0x060 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_2__PA_CELL_EN0_2___POR 0x050 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_2__PA_CELL_EN1_2___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_2__PA_CELL_EN1_2___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_2__PA_CELL_EN0_2___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_2__PA_CELL_EN0_2___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_2___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_2___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_3 (0x005F945C) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_3___POR 0x1B05C000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_3__PA_CELL_EN1_3___POR 0x06C +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_3__PA_CELL_EN0_3___POR 0x05C +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_3__PA_CELL_EN1_3___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_3__PA_CELL_EN1_3___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_3__PA_CELL_EN0_3___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_3__PA_CELL_EN0_3___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_3___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_3___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_4 (0x005F9460) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_4___POR 0x1B05C000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_4__PA_CELL_EN1_4___POR 0x06C +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_4__PA_CELL_EN0_4___POR 0x05C +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_4__PA_CELL_EN1_4___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_4__PA_CELL_EN1_4___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_4__PA_CELL_EN0_4___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_4__PA_CELL_EN0_4___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_4___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_4___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_5 (0x005F9464) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_5___POR 0x1BC5F000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_5__PA_CELL_EN1_5___POR 0x06F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_5__PA_CELL_EN0_5___POR 0x05F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_5__PA_CELL_EN1_5___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_5__PA_CELL_EN1_5___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_5__PA_CELL_EN0_5___M 0x003FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_5__PA_CELL_EN0_5___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_5___M 0xFFFFF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA_LUT1_5___S 12 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0 (0x005F9470) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_CTUNE3FLO_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_CTUNE3FLO_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_CTUNE1FLO_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_CTUNE1FLO_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__DA_CTUNE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__DA_CTUNE_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_RGAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_RGAIN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_LSW_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_CTUNE3FLO_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_CTUNE3FLO_OV___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_CTUNE3FLO_OVD___M 0x7E000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_CTUNE3FLO_OVD___S 25 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_CTUNE1FLO_OV___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_CTUNE1FLO_OV___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_CTUNE1FLO_OVD___M 0x00FC0000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_CTUNE1FLO_OVD___S 18 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__DA_CTUNE_OV___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__DA_CTUNE_OV___S 17 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__DA_CTUNE_OVD___M 0x0001F000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__DA_CTUNE_OVD___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_RGAIN_OV___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_RGAIN_OV___S 11 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_RGAIN_OVD___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_RGAIN_OVD___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_LSW_EN_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0__UPC_LSW_EN_OVS___S 6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0___M 0xFFFFFFC0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV0___S 6 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1 (0x005F9474) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CELL_EN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CELL_EN_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CELL_AUX_EN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CELL_AUX_EN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CASOFF_BIAS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CASOFF_BIAS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CELL_EN_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CELL_EN_OV___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CELL_EN_OVD___M 0x7FC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CELL_EN_OVD___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CELL_AUX_EN_OV___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CELL_AUX_EN_OV___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CELL_AUX_EN_OVD___M 0x001FE000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CELL_AUX_EN_OVD___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CASOFF_BIAS_OV___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CASOFF_BIAS_OV___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CASOFF_BIAS_OVD___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1__DA_CASOFF_BIAS_OVD___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV1___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2 (0x005F9478) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CTUNE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CTUNE_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CTUNE_DEQ_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CTUNE_DEQ_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_RTUNE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_RTUNE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_ILEVEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_ILEVEL_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_ILEVEL_B2_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_ILEVEL_B2_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CAS_BIAS_AUX1_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CAS_BIAS_AUX1_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CTUNE_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CTUNE_OV___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CTUNE_OVD___M 0x7C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CTUNE_OVD___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CTUNE_DEQ_OV___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CTUNE_DEQ_OV___S 25 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CTUNE_DEQ_OVD___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CTUNE_DEQ_OVD___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_RTUNE_OV___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_RTUNE_OV___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_RTUNE_OVD___M 0x001E0000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_RTUNE_OVD___S 17 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_ILEVEL_OV___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_ILEVEL_OV___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_ILEVEL_OVD___M 0x0000F800 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_ILEVEL_OVD___S 11 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_ILEVEL_B2_OV___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_ILEVEL_B2_OV___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_ILEVEL_B2_OVD___M 0x000003E0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_ILEVEL_B2_OVD___S 5 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CAS_BIAS_AUX1_OV___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CAS_BIAS_AUX1_OV___S 4 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CAS_BIAS_AUX1_OVD___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2__PPA_CAS_BIAS_AUX1_OVD___S 1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV2___S 1 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3 (0x005F947C) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CAS_BIAS_AUX0_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CAS_BIAS_AUX0_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CAS_BIAS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CAS_BIAS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CASOFF_BIAS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CASOFF_BIAS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CELL_EN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CELL_EN_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CELL_AUX_EN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CELL_AUX_EN_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CAS_BIAS_AUX0_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CAS_BIAS_AUX0_OV___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CAS_BIAS_AUX0_OVD___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CAS_BIAS_AUX0_OVD___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CAS_BIAS_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CAS_BIAS_OV___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CAS_BIAS_OVD___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CAS_BIAS_OVD___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CASOFF_BIAS_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CASOFF_BIAS_OV___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CASOFF_BIAS_OVD___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CASOFF_BIAS_OVD___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CELL_EN_OV___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CELL_EN_OV___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CELL_EN_OVD___M 0x0007FC00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CELL_EN_OVD___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CELL_AUX_EN_OV___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CELL_AUX_EN_OV___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CELL_AUX_EN_OVD___M 0x000001FE +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3__PPA_CELL_AUX_EN_OVD___S 1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV3___S 1 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4 (0x005F9480) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PPA_XFMR_SW_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PPA_VDD_SW_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_ILEVEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_ILEVEL_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_ILEVEL_B2_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_ILEVEL_B2_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_AUX1_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_AUX1_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_AUX0_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_AUX0_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PPA_XFMR_SW_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PPA_XFMR_SW_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PPA_VDD_SW_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PPA_VDD_SW_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_ILEVEL_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_ILEVEL_OV___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_ILEVEL_OVD___M 0x07C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_ILEVEL_OVD___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_ILEVEL_B2_OV___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_ILEVEL_B2_OV___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_ILEVEL_B2_OVD___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_ILEVEL_B2_OVD___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_AUX1_OV___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_AUX1_OV___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_AUX1_OVD___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_AUX1_OVD___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_AUX0_OV___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_AUX0_OV___S 11 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_AUX0_OVD___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_AUX0_OVD___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_OV___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_OV___S 7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_OVD___M 0x00000078 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4__PA_CAS_BIAS_OVD___S 3 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4___M 0xFFFFFFF8 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV4___S 3 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5 (0x005F9484) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CASOFF_BIAS_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CASOFF_BIAS_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CELL_EN1_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CELL_EN1_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CELL_EN0_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CELL_EN0_OVD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CASOFF_BIAS_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CASOFF_BIAS_OV___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CASOFF_BIAS_OVD___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CASOFF_BIAS_OVD___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CELL_EN1_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CELL_EN1_OV___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CELL_EN1_OVD___M 0x07FE0000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CELL_EN1_OVD___S 17 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CELL_EN0_OV___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CELL_EN0_OV___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CELL_EN0_OVD___M 0x0000FFC0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5__PA_CELL_EN0_OVD___S 6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5___M 0xFFFFFFC0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_LUT_OV5___S 6 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV0 (0x005F9488) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV0___POR 0x000C0000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV0__TX_SINGLE_RU_OVS___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV0__TX_LO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV0__TX_LO_LP_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV0__TX_SINGLE_RU_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV0__TX_SINGLE_RU_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV0__TX_LO_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV0__TX_LO_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV0__TX_LO_LP_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV0__TX_LO_LP_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV0___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV0___S 14 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1 (0x005F948C) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__CALRTX_ATTN_GM_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__CALRTX_PHASESHIFT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__DA_BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__TXLO_INBUF25DC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__TXLO_LP_INBUF25DC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_AUX_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_LO_EN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_LO_EN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_EN_NMX_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_EN_NMX_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_EN_PMX_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_EN_PMX_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__CALRTX_ATTN_GM_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__CALRTX_ATTN_GM_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__CALRTX_PHASESHIFT_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__CALRTX_PHASESHIFT_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__DA_BIAS_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__DA_BIAS_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__TXLO_INBUF25DC_EN_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__TXLO_INBUF25DC_EN_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__TXLO_LP_INBUF25DC_EN_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__TXLO_LP_INBUF25DC_EN_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_AUX_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_AUX_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_LO_EN_OV___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_LO_EN_OV___S 18 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_LO_EN_OVD___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_LO_EN_OVD___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_EN_NMX_OV___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_EN_NMX_OV___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_EN_NMX_OVD___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_EN_NMX_OVD___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_EN_PMX_OV___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_EN_PMX_OV___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_EN_PMX_OVD___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1__UPC_EN_PMX_OVD___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1___M 0xFFF7FC00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV1___S 10 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2 (0x005F9490) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_BUFTLINE1ST_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_BUFTLINE2ND_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_LP_BUFTLINE1ST_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_LP_BUFTLINE2ND_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_OBUF25DC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_LP_OBUF25DC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__PPA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__PA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__WL_DPD5_IPA_SW_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__WL_DPD5_IPA_CALTXSHIFT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__WL_DPD5_IPA_GM_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__DA_IPA_PATH_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_BUFTLINE1ST_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_BUFTLINE1ST_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_BUFTLINE2ND_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_BUFTLINE2ND_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_LP_BUFTLINE1ST_EN_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_LP_BUFTLINE1ST_EN_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_LP_BUFTLINE2ND_EN_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_LP_BUFTLINE2ND_EN_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_OBUF25DC_EN_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_OBUF25DC_EN_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_LP_OBUF25DC_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__TXLO_LP_OBUF25DC_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__PPA_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__PPA_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__PA_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__PA_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__WL_DPD5_IPA_SW_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__WL_DPD5_IPA_SW_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__WL_DPD5_IPA_CALTXSHIFT_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__WL_DPD5_IPA_CALTXSHIFT_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__WL_DPD5_IPA_GM_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__WL_DPD5_IPA_GM_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__DA_IPA_PATH_EN_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2__DA_IPA_PATH_EN_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2___M 0xFFFFFF00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_OV2___S 8 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0 (0x005F9494) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_UPC_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_DA_GAIN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_FCS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_DA_CTUNE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_TX_SINGLE_RU___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_IPA_GAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_DA_CASOFF_BIAS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_UPC_GAIN___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_UPC_GAIN___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_DA_GAIN___M 0x1F000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_DA_GAIN___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_FCS___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_FCS___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_DA_CTUNE___M 0x007C0000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_DA_CTUNE___S 18 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_TX_SINGLE_RU___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_TX_SINGLE_RU___S 17 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_IPA_GAIN___M 0x0001C000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_IPA_GAIN___S 14 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_DA_CASOFF_BIAS___M 0x00003800 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0__RO_DA_CASOFF_BIAS___S 11 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0___M 0xFFFFF800 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT0___S 11 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1 (0x005F9498) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1__RO_DA_CELL_EN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1__RO_DA_CELL_AUX_EN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1__RO_UPC_RGAIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1__RO_UPC_CTUNE3FLO___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1__RO_UPC_CTUNE1FLO___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1__RO_DA_CELL_EN___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1__RO_DA_CELL_EN___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1__RO_DA_CELL_AUX_EN___M 0x007F8000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1__RO_DA_CELL_AUX_EN___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1__RO_UPC_RGAIN___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1__RO_UPC_RGAIN___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1__RO_UPC_CTUNE3FLO___M 0x00000FC0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1__RO_UPC_CTUNE3FLO___S 6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1__RO_UPC_CTUNE1FLO___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1__RO_UPC_CTUNE1FLO___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT1___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2 (0x005F949C) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_UPC_LSW_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_ILEVEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_ILEVEL_B2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_CTUNE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_CTUNE_DEQ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_RTUNE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS_AUX1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS_AUX0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_UPC_LSW_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_UPC_LSW_EN___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_ILEVEL___M 0x7C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_ILEVEL___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_ILEVEL_B2___M 0x03E00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_ILEVEL_B2___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_CTUNE___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_CTUNE___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_CTUNE_DEQ___M 0x0000E000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_CTUNE_DEQ___S 13 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_RTUNE___M 0x00001E00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_RTUNE___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS_AUX1___M 0x000001C0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS_AUX1___S 6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS_AUX0___M 0x00000038 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS_AUX0___S 3 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2__RO_PPA_CAS_BIAS___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT2___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3 (0x005F94A0) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PPA_CASOFF_BIAS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PPA_CELL_EN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PPA_CELL_AUX_EN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PPA_XFMR_SW_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PPA_VDD_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PA_ILEVEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PA_ILEVEL_B2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PPA_CASOFF_BIAS___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PPA_CASOFF_BIAS___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PPA_CELL_EN___M 0x1FF00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PPA_CELL_EN___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PPA_CELL_AUX_EN___M 0x000FF000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PPA_CELL_AUX_EN___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PPA_XFMR_SW_EN___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PPA_XFMR_SW_EN___S 11 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PPA_VDD_SW___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PPA_VDD_SW___S 10 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PA_ILEVEL___M 0x000003E0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PA_ILEVEL___S 5 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PA_ILEVEL_B2___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3__RO_PA_ILEVEL_B2___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT3___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4 (0x005F94A4) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4__RO_PA_CASOFF_BIAS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4__RO_PA_CELL_EN1___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX1___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX1___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX0___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS_AUX0___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS___M 0x03C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4__RO_PA_CAS_BIAS___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4__RO_PA_CASOFF_BIAS___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4__RO_PA_CASOFF_BIAS___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4__RO_PA_CELL_EN1___M 0x0007FE00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4__RO_PA_CELL_EN1___S 9 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT4___S 9 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT5 (0x005F94A8) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT5___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT5__RO_PA_CELL_EN0___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT5__RO_PA_CELL_EN0___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT5__RO_PA_CELL_EN0___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT5___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LUT5___S 22 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0 (0x005F94AC) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0__RO_PPA_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0__RO_PA_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_SW_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_CALTXSHIFT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_GM_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0__RO_PPA_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0__RO_PPA_EN___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0__RO_PA_EN___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0__RO_PA_EN___S 30 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_SW_EN___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_SW_EN___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_CALTXSHIFT___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_CALTXSHIFT___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_GM_EN___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0__RO_WL_DPD5_IPA_GM_EN___S 27 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_RO_WL_TXFE_LOGIC0___S 27 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0 (0x005F94B0) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0___POR 0x118A0E00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_IBIAS_LOWER_LIM_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_IBIAS_LOWER_LIM___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_ISLOPE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_CAS_BIAS___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_CAS_BIAS_AUX___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_ILEVEL_COARSE___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_ILEVEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_BIAS_NOISE_CNCL_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_BIAS_NOISE_CNCL_RES___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_IBIAS_LOWER_LIM_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_IBIAS_LOWER_LIM_EN___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_IBIAS_LOWER_LIM___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_IBIAS_LOWER_LIM___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_ISLOPE___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_ISLOPE___S 25 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_CAS_BIAS___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_CAS_BIAS___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_CAS_BIAS_AUX___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_CAS_BIAS_AUX___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_ILEVEL_COARSE___M 0x00060000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_ILEVEL_COARSE___S 17 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_ILEVEL___M 0x00018000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_ILEVEL___S 15 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_ATB_SEL___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_ATB_SEL___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_BIAS_NOISE_CNCL_EN___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_BIAS_NOISE_CNCL_EN___S 11 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_BIAS_NOISE_CNCL_RES___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0__D_DA_BIAS_NOISE_CNCL_RES___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0___M 0xFFFFFF00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DA0___S 8 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC0 (0x005F94B4) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC0___POR 0x74000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC0__D_UPC_RSHIFTN___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC0__D_UPC_RSHIFTP___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC0__D_UPC_RMXFILT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC0__D_UPC_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC0__D_UPC_RSHIFTN___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC0__D_UPC_RSHIFTN___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC0__D_UPC_RSHIFTP___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC0__D_UPC_RSHIFTP___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC0__D_UPC_RMXFILT___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC0__D_UPC_RMXFILT___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC0__D_UPC_ATB_SEL___M 0x00600000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC0__D_UPC_ATB_SEL___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC0___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_UPC0___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0 (0x005F94B8) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0___POR 0x00FF00FF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_IP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_QP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_IP___POR 0xF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_QP___POR 0xF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_IP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_QP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_IP___POR 0xF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_QP___POR 0xF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_IP___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_IP___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_QP___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_MSB_QP___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_IP___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_IP___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_QP___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_DUTYCODE_LSB_QP___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_IP___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_IP___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_QP___M 0x00000F00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_MSB_QP___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_IP___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_IP___S 4 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_QP___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0__D_TXLO_LPDUTYCODE_LSB_QP___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO0___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1 (0x005F94BC) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1___POR 0x00FF00FF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_IN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_QN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_IN___POR 0xF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_QN___POR 0xF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_IN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_QN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_IN___POR 0xF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_QN___POR 0xF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_IN___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_IN___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_QN___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_MSB_QN___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_IN___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_IN___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_QN___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_DUTYCODE_LSB_QN___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_IN___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_IN___S 12 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_QN___M 0x00000F00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_MSB_QN___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_IN___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_IN___S 4 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_QN___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1__D_TXLO_LPDUTYCODE_LSB_QN___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_LO1___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL (0x005F94C0) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL___POR 0x04000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL__D_CALRTX_GC___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL__D_CALRTX_SW_FLP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL__D_CALRTX_RES_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL__D_CALRTX_IBIAS___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL__D_CALRTX_GC___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL__D_CALRTX_GC___S 30 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL__D_CALRTX_SW_FLP___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL__D_CALRTX_SW_FLP___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL__D_CALRTX_RES_CTRL___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL__D_CALRTX_RES_CTRL___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL__D_CALRTX_IBIAS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL__D_CALRTX_IBIAS___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL___S 26 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_SPARE (0x005F94C4) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_SPARE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_SPARE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_SPARE__D_TXFE_SPARE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_SPARE__D_TXFE_SPARE___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_SPARE__D_TXFE_SPARE___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_SPARE___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_SPARE___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0 (0x005F94C8) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0___POR 0xAE000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0__D_PPA_IBIAS_LOWER_LIM_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0__D_PPA_IBIAS_LOWER_LIM___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0__D_PPA_ISLOPE___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0__D_PPA_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0__D_PPA_INPUT_SW_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0__D_PPA_IBIAS_LOWER_LIM_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0__D_PPA_IBIAS_LOWER_LIM_EN___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0__D_PPA_IBIAS_LOWER_LIM___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0__D_PPA_IBIAS_LOWER_LIM___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0__D_PPA_ISLOPE___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0__D_PPA_ISLOPE___S 25 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0__D_PPA_ATB_SEL___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0__D_PPA_ATB_SEL___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0__D_PPA_INPUT_SW_EN___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0__D_PPA_INPUT_SW_EN___S 21 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0___M 0xFFE00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PPA0___S 21 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA0 (0x005F94CC) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA0___POR 0xAA000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA0__D_PA_IBIAS_LOWER_LIM_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA0__D_PA_IBIAS_LOWER_LIM___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA0__D_PA_ISLOPE___POR 0x5 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA0__D_PA_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA0__D_PA_IBIAS_LOWER_LIM_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA0__D_PA_IBIAS_LOWER_LIM_EN___S 31 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA0__D_PA_IBIAS_LOWER_LIM___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA0__D_PA_IBIAS_LOWER_LIM___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA0__D_PA_ISLOPE___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA0__D_PA_ISLOPE___S 25 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA0__D_PA_ATB_SEL___M 0x01C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA0__D_PA_ATB_SEL___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA0___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_PA0___S 22 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL_DUMMY (0x005F94D0) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL_DUMMY___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL_DUMMY___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL_DUMMY__D_DTOP_CAL_DUMMY1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL_DUMMY__D_DTOP_CAL_DUMMY0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL_DUMMY__D_DTOP_DUMMY1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL_DUMMY__D_DTOP_DUMMY0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL_DUMMY__D_DTOP_CAL_DUMMY1___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL_DUMMY__D_DTOP_CAL_DUMMY1___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL_DUMMY__D_DTOP_CAL_DUMMY0___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL_DUMMY__D_DTOP_CAL_DUMMY0___S 16 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL_DUMMY__D_DTOP_DUMMY1___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL_DUMMY__D_DTOP_DUMMY1___S 8 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL_DUMMY__D_DTOP_DUMMY0___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL_DUMMY__D_DTOP_DUMMY0___S 0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL_DUMMY___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_CAL_DUMMY___S 0 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD (0x005F94D4) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD___POR 0x08B80000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_NOTCH_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_CALTXSHIFT_RES_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_TAIL_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_IBIAS_CTRL___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_DEGEN_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_VCAS_CTRL___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_ATTN_CTRL___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_NOTCH_CTRL___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_NOTCH_CTRL___S 30 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_CALTXSHIFT_RES_CTRL___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_CALTXSHIFT_RES_CTRL___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_TAIL_SW___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_TAIL_SW___S 28 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_IBIAS_CTRL___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_IBIAS_CTRL___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_DEGEN_CTRL___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_DEGEN_CTRL___S 25 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_VCAS_CTRL___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_GM_VCAS_CTRL___S 23 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_ATTN_CTRL___M 0x00780000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD__D_WL_DPD5_IPA_ATTN_CTRL___S 19 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD___M 0xFFF80000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_DPD___S 19 + +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR (0x005F94D8) +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR___POR 0x6C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR__D_TS_REF_RTUNE___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR__D_TS_RTUNE___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR__D_TS_ATB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR__TS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR__TS_SRC_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR__D_TS_REF_RTUNE___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR__D_TS_REF_RTUNE___S 29 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR__D_TS_RTUNE___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR__D_TS_RTUNE___S 26 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR__D_TS_ATB_SEL___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR__D_TS_ATB_SEL___S 24 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR__TS_EN_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR__TS_EN_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR__TS_SRC_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR__TS_SRC_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR___M 0xFDF00000 +#define PHYA_IRON2G_RFA_WL_TXFE_5G_CH1_WL_TXFE_TSENSOR___S 20 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CTRL_0 (0x005FA000) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CTRL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CTRL_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CTRL_0__TPC_STOP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CTRL_0__TPC_STOP___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CTRL_0__TPC_STOP___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CTRL_0___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CTRL_0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT (0x005FA004) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_TEMP_VALID___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_FULLPKT_PWR_VALID___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_PREAMBLE_PWR_VALID___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_TEMP___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_FULLPKT_PWR___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_PREAMBLE_PWR___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_TEMP_VALID___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_TEMP_VALID___S 26 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_FULLPKT_PWR_VALID___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_FULLPKT_PWR_VALID___S 25 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_PREAMBLE_PWR_VALID___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_PREAMBLE_PWR_VALID___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_TEMP___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_TEMP___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_FULLPKT_PWR___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_FULLPKT_PWR___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_PREAMBLE_PWR___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT__RO_PREAMBLE_PWR___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT___M 0x07FFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_RESULT___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0 (0x005FA040) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0___POR 0x000A0026 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__PDADC_CLK_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__PDADC_TEST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_HI_IN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_MID_IN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_LO_IN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_BIAS_COMP_IN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_BIAS_REFBUFF_IN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_PRECHARGEC_IN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ATEST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ATEST_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_SPARE___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_FSMODE_IN___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__PDADC_CLK_SEL___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__PDADC_CLK_SEL___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__PDADC_TEST_EN___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__PDADC_TEST_EN___S 30 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_HI_IN___M 0x38000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_HI_IN___S 27 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_MID_IN___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_MID_IN___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_LO_IN___M 0x00E00000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_LO_IN___S 21 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_BIAS_COMP_IN___M 0x00180000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_BIAS_COMP_IN___S 19 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_BIAS_REFBUFF_IN___M 0x00060000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_BIAS_REFBUFF_IN___S 17 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_PRECHARGEC_IN___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ADJ_VREF_PRECHARGEC_IN___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ATEST_EN___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ATEST_EN___S 15 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ATEST_SEL___M 0x00007800 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_ATEST_SEL___S 11 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_SPARE___M 0x000007F8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_SPARE___S 3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_FSMODE_IN___M 0x00000006 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0__D_ADC_FSMODE_IN___S 1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_0___S 1 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_1 (0x005FA044) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_1___POR 0x00004020 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_1__PDADC_CLK_POL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_1__ADC_DATA_COMP_REF_HI_GAIN___POR 0x020 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_1__ADC_DATA_COMP_REF_LO_GAIN___POR 0x020 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_1__PDADC_CLK_POL___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_1__PDADC_CLK_POL___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_1__ADC_DATA_COMP_REF_HI_GAIN___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_1__ADC_DATA_COMP_REF_HI_GAIN___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_1__ADC_DATA_COMP_REF_LO_GAIN___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_1__ADC_DATA_COMP_REF_LO_GAIN___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_1___M 0x0007FFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_PDADC_CTRL_1___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_PDADC_DATA (0x005FA048) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_PDADC_DATA___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_PDADC_DATA___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_PDADC_DATA__RO_D_PDADC_DATA___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_PDADC_DATA__RO_D_PDADC_DATA___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_PDADC_DATA__RO_D_PDADC_DATA___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_PDADC_DATA___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_PDADC_DATA___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0 (0x005FA080) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0___POR 0x0200E8B6 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_RESET_L___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CLK_CFG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_PATH_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_DAC_EN___POR 0xE +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_POL___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_BIN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_SETT___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_SMPL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__DC_OFFSET_MODE_MAX_ATTN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_RESET_L___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_RESET_L___S 25 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CLK_CFG___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CLK_CFG___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_PATH_SEL___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_PATH_SEL___S 22 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_EN___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_EN___S 17 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_DAC_EN___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_DAC_EN___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_POL___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_POL___S 10 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_BIN___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_BIN___S 7 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_SETT___M 0x00000070 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_SETT___S 4 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_SMPL___M 0x0000000E +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__TPC_CAL_SMPL___S 1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__DC_OFFSET_MODE_MAX_ATTN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0__DC_OFFSET_MODE_MAX_ATTN___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0___M 0x03C2FCFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1 (0x005FA084) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1___POR 0x00F80204 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_LG___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_PGA_GAIN_CTRL_HG___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___POR 0x10 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___POR 0x04 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_HG___S 22 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_LG___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__FE_SQ_GAIN_LG___S 20 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_PGA_GAIN_CTRL_HG___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_PGA_GAIN_CTRL_HG___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_PGA_GAIN_CTRL_LG___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___M 0x000003E0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_HG___S 5 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1__BE_TIA_GAIN_CTRL_LG___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1___M 0x00FF03FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2 (0x005FA088) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2___POR 0xECA86420 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_7___POR 0xE +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_6___POR 0xC +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_5___POR 0xA +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_4___POR 0x8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_3___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_2___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_1___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_7___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_7___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_6___M 0x0F000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_6___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_5___M 0x00F00000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_5___S 20 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_4___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_4___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_3___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_3___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_2___M 0x00000F00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_2___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_1___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_1___S 4 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_0___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2__WL_PWR_IDX_0___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_2___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_3 (0x005FA08C) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT___S 4 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_3__TPC_MIN_POWER_DELTA_WITH_BT_EN___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_3___M 0x000000F1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_CFG_3___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0 (0x005FA090) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_HI___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_HI_CAL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_HI_CAL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_LO___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_LO_CAL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_LO_CAL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_HI___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_HI___S 30 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_HI_CAL___M 0x0FE00000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_HI_CAL___S 21 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_HI_CAL___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_HI_CAL___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_LO___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_TPC_CAL_VALID_LO___S 14 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_LO_CAL___M 0x00000FE0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC1_LO_CAL___S 5 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_LO_CAL___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0__RO_BE_DCOC_DAC2_LO_CAL___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0___M 0x4FFF4FFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_BE_CAL_RESULT_0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0 (0x005FA094) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__BE_INT_PDET_PATH_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__FE_SQ_XPA_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__FE_SQ_IPA_IS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__FE_SQ_IPA_PO_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__FE_VDET_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__PDADC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__BE_TIA_SQBIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__ADC_VREF_IN_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__BE_INT_PDET_PATH_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__BE_INT_PDET_PATH_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__FE_SQ_XPA_EN_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__FE_SQ_XPA_EN_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__FE_SQ_IPA_IS_EN_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__FE_SQ_IPA_IS_EN_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__FE_SQ_IPA_PO_EN_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__FE_SQ_IPA_PO_EN_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__FE_VDET_EN_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__FE_VDET_EN_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__PDADC_EN_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__PDADC_EN_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__BE_TIA_SQBIAS_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__BE_TIA_SQBIAS_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__ADC_VREF_IN_EN_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0__ADC_VREF_IN_EN_OVS___S 4 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0___M 0xC03FFC30 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_0___S 4 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1 (0x005FA098) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__PDET_GAIN_IDX_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_SQ_XPA_DUMMY_CURRENT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_SQ_IPA_IS_DUMMY_CURRENT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_SQ_IPA_PO_DUMMY_CURRENT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_XPA_RF_DISCONNECT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_IPA_IS_RF_DISCONNECT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_IPA_PO_RF_DISCONNECT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__PDET_GAIN_IDX_OVS___M 0x0C000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__PDET_GAIN_IDX_OVS___S 26 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_SQ_XPA_DUMMY_CURRENT_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_SQ_XPA_DUMMY_CURRENT_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_SQ_IPA_IS_DUMMY_CURRENT_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_SQ_IPA_IS_DUMMY_CURRENT_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_SQ_IPA_PO_DUMMY_CURRENT_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_SQ_IPA_PO_DUMMY_CURRENT_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_XPA_RF_DISCONNECT_OVS___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_XPA_RF_DISCONNECT_OVS___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_IPA_IS_RF_DISCONNECT_OVS___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_IPA_IS_RF_DISCONNECT_OVS___S 14 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_IPA_PO_RF_DISCONNECT_OVS___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1__FE_IPA_PO_RF_DISCONNECT_OVS___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1___M 0x0CFFF000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_1___S 12 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2 (0x005FA09C) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2___POR 0x000C1010 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__FE_R50_ADJ_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__FE_R50_ADJ_OVD___POR 0x30 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OVD___POR 0x10 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OVD___POR 0x10 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__FE_R50_ADJ_OV___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__FE_R50_ADJ_OV___S 20 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__FE_R50_ADJ_OVD___M 0x000FC000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__FE_R50_ADJ_OVD___S 14 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OV___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OV___S 13 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OVD___M 0x00001F00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_HG_OVD___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OV___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OV___S 5 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OVD___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2__BE_IDAC2_OFFSET_LG_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2___M 0x001FFF3F +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_2___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3 (0x005FA0A0) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3___POR 0x0000B880 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__FE_SQ_IPA_PO_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__FE_SQ_IPA_IS_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__FE_SQ_XPA_GAIN_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_TIA_GAIN_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_PGA_GAIN_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC2_OFFSET_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__TPC_SQR_IC_N_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__TPC_SQR_IC_P_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__TPC_SQR_IPTS_N_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__TPC_SQR_IPTS_P_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OV___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OVD___POR 0x38 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OV___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__FE_SQ_IPA_PO_GAIN_OV___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__FE_SQ_IPA_PO_GAIN_OV___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__FE_SQ_IPA_IS_GAIN_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__FE_SQ_IPA_IS_GAIN_OV___S 27 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__FE_SQ_XPA_GAIN_OV___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__FE_SQ_XPA_GAIN_OV___S 26 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_TIA_GAIN_CTRL_OV___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_TIA_GAIN_CTRL_OV___S 25 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_PGA_GAIN_CTRL_OV___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_PGA_GAIN_CTRL_OV___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_OV___S 23 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC2_OFFSET_OV___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC2_OFFSET_OV___S 22 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__TPC_SQR_IC_N_CTRL_OV___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__TPC_SQR_IC_N_CTRL_OV___S 21 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__TPC_SQR_IC_P_CTRL_OV___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__TPC_SQR_IC_P_CTRL_OV___S 20 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__TPC_SQR_IPTS_N_CTRL_OV___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__TPC_SQR_IPTS_N_CTRL_OV___S 19 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__TPC_SQR_IPTS_P_CTRL_OV___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__TPC_SQR_IPTS_P_CTRL_OV___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OV___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OV___S 15 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OVD___M 0x00007F00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_HG_OVD___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OV___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OV___S 7 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OVD___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3__BE_IDAC1_OFFSET_LG_OVD___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3___M 0x1FFCFFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_3___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4 (0x005FA0A4) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4___POR 0x01010840 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_R50_ADJ_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OVD___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OVD___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OVD___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OVD___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_R50_ADJ_CTRL_OV___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_R50_ADJ_CTRL_OV___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OV___S 27 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OVD___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__BE_PDMUX_A_SEL_OVD___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OV___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OV___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OVD___M 0x0003C000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_XPA_ATTN_CTRL_OVD___S 14 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OV___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OV___S 13 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OVD___M 0x00001E00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_IPA_IS_ATTN_CTRL_OVD___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OV___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OV___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OVD___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4__FE_IPA_PO_ATTN_CTRL_OVD___S 4 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4___M 0x1B07FFF0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OVERRIDE_4___S 4 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0 (0x005FA0A8) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0___POR 0x1D186008 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_FORCE_EN_2P5_CURRENT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_TIA_FB_LOWER_IR_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_TIA_FB_LOWER_IC_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_TIA_FB_TOP_IR_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_TIA_FB_TOP_IC_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_VREF_SET___POR 0x8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__FE_R50_ADJ_HG___POR 0x30 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__FE_R50_ADJ_LG___POR 0x30 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_BW_SEL___POR 0x8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_FORCE_EN_2P5_CURRENT___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_FORCE_EN_2P5_CURRENT___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_TIA_FB_LOWER_IR_EN___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_TIA_FB_LOWER_IR_EN___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_TIA_FB_LOWER_IC_EN___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_TIA_FB_LOWER_IC_EN___S 27 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_TIA_FB_TOP_IR_EN___M 0x04000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_TIA_FB_TOP_IR_EN___S 26 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_TIA_FB_TOP_IC_EN___M 0x02000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_TIA_FB_TOP_IC_EN___S 25 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_VREF_SET___M 0x01E00000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_VREF_SET___S 21 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__FE_R50_ADJ_HG___M 0x001F8000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__FE_R50_ADJ_HG___S 15 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__FE_R50_ADJ_LG___M 0x00007E00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__FE_R50_ADJ_LG___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_BW_SEL___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0__D_BE_BW_SEL___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0___M 0x9FFFFE0F +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_1 (0x005FA0AC) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_1___POR 0x00000840 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_1__D_BE_ATB_MUX_SEL___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_1__D_BE_S2DOFFSET_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_1__D_BE_VREF_DEC_SEL___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_1__D_BE_ATB_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_1__D_BE_ATB_MUX_SEL___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_1__D_BE_ATB_MUX_SEL___S 10 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_1__D_BE_S2DOFFSET_SEL___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_1__D_BE_S2DOFFSET_SEL___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_1__D_BE_VREF_DEC_SEL___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_1__D_BE_VREF_DEC_SEL___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_1__D_BE_ATB_SEL___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_1__D_BE_ATB_SEL___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_1___M 0x00000DFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_1___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0 (0x005FA0B0) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0___POR 0x036E36DC +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_ATB_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASN_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASP_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_IDAC_CTRL___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_IC_LPF_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_REFGEN_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_IC_VCMOUTGEN_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_TIA_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_VDAC_CTRL___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_ATB_CTRL___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_ATB_CTRL___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASN_CTRL___M 0x00E00000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASN_CTRL___S 21 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASP_CTRL___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_BIASP_CTRL___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_IDAC_CTRL___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_IDAC_CTRL___S 15 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_IC_LPF_CTRL___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_IC_LPF_CTRL___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_REFGEN_CTRL___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_REFGEN_CTRL___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_IC_VCMOUTGEN_CTRL___M 0x000001C0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_IC_VCMOUTGEN_CTRL___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_TIA_CTRL___M 0x00000038 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_TIA_CTRL___S 3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_VDAC_CTRL___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0__D_BE_IC_VDAC_CTRL___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0___M 0x07FFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1 (0x005FA0B4) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1___POR 0x0001B6DA +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_IC_PDBUFFER_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IC_PDBUFFER_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_IC_SPARE_0_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_IC_SPARE_1_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IR_ATB_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IR_REFGEN_CTRL___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_IC_PDBUFFER_CTRL___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_IC_PDBUFFER_CTRL___S 15 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IC_PDBUFFER_CTRL___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IC_PDBUFFER_CTRL___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_IC_SPARE_0_CTRL___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_IC_SPARE_0_CTRL___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_IC_SPARE_1_CTRL___M 0x000001C0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_IC_SPARE_1_CTRL___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IR_ATB_CTRL___M 0x00000038 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IR_ATB_CTRL___S 3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IR_REFGEN_CTRL___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1__D_BE_IR_REFGEN_CTRL___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1___M 0x0003FFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_1___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2 (0x005FA0B8) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2___POR 0x0001B6DC +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_VCMOUTGEN_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_IR_SPARE_0_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_IR_SPARE_1_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_IC_TIA_FB_BIAS___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_OFFSET_CTRL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_TIA_FB_BIAS___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_VCMOUTGEN_CTRL___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_VCMOUTGEN_CTRL___S 15 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_IR_SPARE_0_CTRL___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_IR_SPARE_0_CTRL___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_IR_SPARE_1_CTRL___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_IR_SPARE_1_CTRL___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_IC_TIA_FB_BIAS___M 0x000001C0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_IC_TIA_FB_BIAS___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_OFFSET_CTRL___M 0x00000038 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_OFFSET_CTRL___S 3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_TIA_FB_BIAS___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2__D_BE_IR_TIA_FB_BIAS___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2___M 0x0003FFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_IC_IR_BIAS_CTRL_2___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2 (0x005FA0BC) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2___POR 0x68000104 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__D_VDET_VREF___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__D_VDET_ROUT_SEL___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__D_VDET_RFIN_DISCONNECT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__D_TPCDPD_SPARE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__D_BE_IR_SQR_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__TPC_SQR_IC_N_CTRL_HG___POR 0x02 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__TPC_SQR_IC_N_CTRL_LG___POR 0x02 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__D_VDET_VREF___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__D_VDET_VREF___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__D_VDET_ROUT_SEL___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__D_VDET_ROUT_SEL___S 25 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__D_VDET_RFIN_DISCONNECT___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__D_VDET_RFIN_DISCONNECT___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__D_TPCDPD_SPARE___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__D_TPCDPD_SPARE___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__D_BE_IR_SQR_CTRL___M 0x0000E000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__D_BE_IR_SQR_CTRL___S 13 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__TPC_SQR_IC_N_CTRL_HG___M 0x00001F80 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__TPC_SQR_IC_N_CTRL_HG___S 7 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__TPC_SQR_IC_N_CTRL_LG___M 0x0000007E +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2__TPC_SQR_IC_N_CTRL_LG___S 1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2___M 0xFFFFFFFE +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_2___S 1 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3 (0x005FA0C0) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3___POR 0x000C5000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__TPC_SQR_IC_P_CTRL_HG___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__TPC_SQR_IC_P_CTRL_LG___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__D_WL_DPD_GC___POR 0x6 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__D_WL_DPD_IBIAS_INV___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__D_WL_DPD_IBIAS_GM___POR 0x4 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__D_WL_DPD_RES_CTRL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__WL_DPD_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__WL_DPD_CALSHIFT_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__TPC_SQR_IC_P_CTRL_HG___M 0xFC000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__TPC_SQR_IC_P_CTRL_HG___S 26 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__TPC_SQR_IC_P_CTRL_LG___M 0x03F00000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__TPC_SQR_IC_P_CTRL_LG___S 20 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__D_WL_DPD_GC___M 0x000E0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__D_WL_DPD_GC___S 17 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__D_WL_DPD_IBIAS_INV___M 0x00006000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__D_WL_DPD_IBIAS_INV___S 13 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__D_WL_DPD_IBIAS_GM___M 0x00001C00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__D_WL_DPD_IBIAS_GM___S 10 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__D_WL_DPD_RES_CTRL___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__D_WL_DPD_RES_CTRL___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__WL_DPD_EN_OVS___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__WL_DPD_EN_OVS___S 7 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__WL_DPD_CALSHIFT_OVS___M 0x00000060 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3__WL_DPD_CALSHIFT_OVS___S 5 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3___M 0xFFFE7FE0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_3___S 5 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_4 (0x005FA0C4) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_4___POR 0x00000492 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_HG___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_LG___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_HG___POR 0x12 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_LG___POR 0x12 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_HG___M 0x00FC0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_HG___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_LG___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_4__TPC_SQR_IPTS_N_CTRL_LG___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_HG___M 0x00000FC0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_HG___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_LG___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_4__TPC_SQR_IPTS_P_CTRL_LG___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_4___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_AC_4___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OV_5 (0x005FA0C8) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OV_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OV_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OV_5__TPC_BE_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OV_5__VDET_VREF_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OV_5__TPC_BE_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OV_5__TPC_BE_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OV_5__VDET_VREF_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OV_5__VDET_VREF_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OV_5___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_OV_5___S 28 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST (0x005FA0CC) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST__RBIST_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST__RBIST_OV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST__RBIST_OV___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST___S 31 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST_OV (0x005FA0D0) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST_OV___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST_OV___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST_OV__RBIST_CLPC_PKT_TYPE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST_OV__RBIST_TPC_PDET_GAIN_IDX_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST_OV__RBIST_TPC_ATTEN_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST_OV__RBIST_CLPC_PKT_TYPE_OVD___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST_OV__RBIST_CLPC_PKT_TYPE_OVD___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST_OV__RBIST_TPC_PDET_GAIN_IDX_OVD___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST_OV__RBIST_TPC_PDET_GAIN_IDX_OVD___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST_OV__RBIST_TPC_ATTEN_OVD___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST_OV__RBIST_TPC_ATTEN_OVD___S 4 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST_OV___M 0x000003F0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_RBIST_OV___S 4 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0 (0x005FA100) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0___POR 0x1B000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_BIN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_POL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_SETT___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_SMPL___POR 0x3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_REF___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_BIN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_BIN___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_POL___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_POL___S 30 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_SETT___M 0x38000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_SETT___S 27 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_SMPL___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_SMPL___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_EN___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_EN___S 23 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_REF___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0__LDO_CAL_REF___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0___M 0xFF8001FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_LDO_CAL_0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_LDO_CAL_0 (0x005FA104) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_LDO_CAL_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_LDO_CAL_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_PDADC_DATA___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_RESULT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_PDADC_DATA___M 0xFF800000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_PDADC_DATA___S 23 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_DONE___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_DONE___S 4 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_RESULT___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_LDO_CAL_0__RO_LDO_CAL_RESULT___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_LDO_CAL_0___M 0xFF80001F +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_LDO_CAL_0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_MEASURE_0 (0x005FA140) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_MEASURE_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_MEASURE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_MEASURE_0__SW_MEASURE_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_MEASURE_0__SW_MEASURE_TMR_SETTING___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_MEASURE_0__SW_MEASURE_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_MEASURE_0__SW_MEASURE_EN___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_MEASURE_0__SW_MEASURE_TMR_SETTING___M 0x60000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_MEASURE_0__SW_MEASURE_TMR_SETTING___S 29 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_MEASURE_0___M 0xE0000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_MEASURE_0___S 29 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_MEASURE_0 (0x005FA144) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_MEASURE_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_MEASURE_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_MEASURE_0__RO_SW_MEASURE_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_MEASURE_0__RO_SW_MEASURE_RESULT___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_MEASURE_0__RO_SW_MEASURE_DONE___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_MEASURE_0__RO_SW_MEASURE_DONE___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_MEASURE_0__RO_SW_MEASURE_RESULT___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_MEASURE_0__RO_SW_MEASURE_RESULT___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_MEASURE_0___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_MEASURE_0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_AVG_0 (0x005FA148) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_AVG_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_AVG_0___POR 0x08000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_AVG_0__SW_AVG_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_AVG_0__SW_AVG_CFG___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_AVG_0__SW_AVG_EN___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_AVG_0__SW_AVG_EN___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_AVG_0__SW_AVG_CFG___M 0x78000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_AVG_0__SW_AVG_CFG___S 27 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_AVG_0___M 0xF8000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_SW_AVG_0___S 27 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_AVG_0 (0x005FA14C) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_AVG_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_AVG_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_AVG_0__RO_SW_AVG_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_AVG_0__RO_SW_AVG_RESULT___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_AVG_0__RO_SW_AVG_DONE___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_AVG_0__RO_SW_AVG_DONE___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_AVG_0__RO_SW_AVG_RESULT___M 0x7FC00000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_AVG_0__RO_SW_AVG_RESULT___S 22 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_AVG_0___M 0xFFC00000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_SW_AVG_0___S 22 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1 (0x005FA180) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1___POR 0x073D11C0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PDADC_STROBE_INV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PWR_MEAS_TRIG_SW___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PDACC_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__ATB_MEAS_DUR___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__THERM_MEAS_DUR___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__VOLT_MEAS_DUR___POR 0x7 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PD_ACC_WINDOW_CCK___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PD_ACC_WINDOW_OFDM___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PD_DC_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PD_DC_WIN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PD_DC_START___POR 0xC0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PDADC_STROBE_INV___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PDADC_STROBE_INV___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS___S 30 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET___S 29 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PWR_MEAS_TRIG_SW___M 0x10000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PWR_MEAS_TRIG_SW___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PDACC_MODE___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PDACC_MODE___S 27 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__ATB_MEAS_DUR___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__ATB_MEAS_DUR___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__THERM_MEAS_DUR___M 0x00E00000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__THERM_MEAS_DUR___S 21 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__VOLT_MEAS_DUR___M 0x001C0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__VOLT_MEAS_DUR___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PD_ACC_WINDOW_CCK___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PD_ACC_WINDOW_CCK___S 15 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PD_ACC_WINDOW_OFDM___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PD_ACC_WINDOW_OFDM___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PD_DC_SEL___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PD_DC_SEL___S 11 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PD_DC_WIN___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PD_DC_WIN___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PD_DC_START___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1__PD_DC_START___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_1___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_2 (0x005FA184) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_2___POR 0x00900090 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_2__CLPC_START_OFDM___POR 0x0090 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_2__CLPC_START_CCK___POR 0x0090 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_2__CLPC_START_OFDM___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_2__CLPC_START_OFDM___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_2__CLPC_START_CCK___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_2__CLPC_START_CCK___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_2___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_3_STAT_B0 (0x005FA188) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_3_STAT_B0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_3_STAT_B0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_4_CNT_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_3_CNT_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_2_CNT_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_1_CNT_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_4_CNT_0___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_4_CNT_0___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_3_CNT_0___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_3_CNT_0___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_2_CNT_0___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_2_CNT_0___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_1_CNT_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_3_STAT_B0__RO_PDADC_CLIP_1_CNT_0___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_3_STAT_B0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_3_STAT_B0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4 (0x005FA18C) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4___POR 0x22685349 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__OLPC_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__FULL_PKT_PWR_ACC_SYM_CNT___POR 0x2 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__FULL_PKT_PWR_MEAS_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_PWR_INIT_DUR___POR 0x4D +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_DC_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_ACC_DC_WIN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_DC_INIT_DUR___POR 0x4D +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_ACC_WIN_CCK___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_ACC_WIN_OFDM___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__OLPC_MODE___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__OLPC_MODE___S 31 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__FULL_PKT_PWR_ACC_SYM_CNT___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__FULL_PKT_PWR_ACC_SYM_CNT___S 28 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__FULL_PKT_PWR_MEAS_EN___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__FULL_PKT_PWR_MEAS_EN___S 27 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_PWR_INIT_DUR___M 0x07F80000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_PWR_INIT_DUR___S 19 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_DC_SEL___M 0x00060000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_DC_SEL___S 17 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_ACC_DC_WIN___M 0x0001C000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_ACC_DC_WIN___S 14 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_DC_INIT_DUR___M 0x00003FC0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_DC_INIT_DUR___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_ACC_WIN_CCK___M 0x00000038 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_ACC_WIN_CCK___S 3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_ACC_WIN_OFDM___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4__PSYM_ACC_WIN_OFDM___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_4___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_5 (0x005FA190) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_5___POR 0x004D4D4D +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_5__FULL_PKT_PWR_INIT_DUR___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_5__ATB_INI_DUR___POR 0x4D +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_5__THERM_INI_DUR___POR 0x4D +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_5__VOLT_INI_DUR___POR 0x4D +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_5__FULL_PKT_PWR_INIT_DUR___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_5__FULL_PKT_PWR_INIT_DUR___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_5__ATB_INI_DUR___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_5__ATB_INI_DUR___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_5__THERM_INI_DUR___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_5__THERM_INI_DUR___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_5__VOLT_INI_DUR___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_5__VOLT_INI_DUR___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_5___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_5___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6 (0x005FA194) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6___POR 0x079E79E7 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__PDADC_STROBE_DLY_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__FULL_PKT_PWR_VALID_THR___POR 0x07 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__ATB_MEAS_DUR_MULTIPLIER___POR 0x27 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__THERM_MEAS_DUR_MULTIPLIER___POR 0x27 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__VOLT_MEAS_DUR_MULTIPLIER___POR 0x27 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__PD_DC_WIN_MULTIPLIER___POR 0x27 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__PDADC_STROBE_DLY_SEL___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__PDADC_STROBE_DLY_SEL___S 30 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__FULL_PKT_PWR_VALID_THR___M 0x3F000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__FULL_PKT_PWR_VALID_THR___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__ATB_MEAS_DUR_MULTIPLIER___M 0x00FC0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__ATB_MEAS_DUR_MULTIPLIER___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__THERM_MEAS_DUR_MULTIPLIER___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__THERM_MEAS_DUR_MULTIPLIER___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__VOLT_MEAS_DUR_MULTIPLIER___M 0x00000FC0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__VOLT_MEAS_DUR_MULTIPLIER___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__PD_DC_WIN_MULTIPLIER___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6__PD_DC_WIN_MULTIPLIER___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_6___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7 (0x005FA198) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7___POR 0x27C27C27 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7__PSYM_ACC_DC_WIN_MULTIPLIER___POR 0x27 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7__PSYM_ACC_WIN_CCK_MULTIPLIER___POR 0x30 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7__PSYM_ACC_WIN_OFDM_MULTIPLIER___POR 0x27 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7__PD_ACC_WINDOW_CCK_MULTIPLIER___POR 0x30 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7__PD_ACC_WINDOW_OFDM_MULTIPLIER___POR 0x27 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7__PSYM_ACC_DC_WIN_MULTIPLIER___M 0x3F000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7__PSYM_ACC_DC_WIN_MULTIPLIER___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7__PSYM_ACC_WIN_CCK_MULTIPLIER___M 0x00FC0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7__PSYM_ACC_WIN_CCK_MULTIPLIER___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7__PSYM_ACC_WIN_OFDM_MULTIPLIER___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7__PSYM_ACC_WIN_OFDM_MULTIPLIER___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7__PD_ACC_WINDOW_CCK_MULTIPLIER___M 0x00000FC0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7__PD_ACC_WINDOW_CCK_MULTIPLIER___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7__PD_ACC_WINDOW_OFDM_MULTIPLIER___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7__PD_ACC_WINDOW_OFDM_MULTIPLIER___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7___M 0x3FFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_7___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_8_B0 (0x005FA19C) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_8_B0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_8_B0___POR 0x00008399 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_8_B0__PDADC_BIAS___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_8_B0__INIT_ATB_SETTING_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_8_B0__INIT_VOLT_SETTING_0___POR 0x83 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_8_B0__INIT_THERM_SETTING_0___POR 0x99 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_8_B0__PDADC_BIAS___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_8_B0__PDADC_BIAS___S 24 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_8_B0__INIT_ATB_SETTING_0___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_8_B0__INIT_ATB_SETTING_0___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_8_B0__INIT_VOLT_SETTING_0___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_8_B0__INIT_VOLT_SETTING_0___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_8_B0__INIT_THERM_SETTING_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_8_B0__INIT_THERM_SETTING_0___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_8_B0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_8_B0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_9 (0x005FA1A0) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_9___POR 0x000001FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_9__PDADC_CLIP_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_9__PDADC_CLIP_THRES___POR 0x1FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_9__PDADC_CLIP_EN___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_9__PDADC_CLIP_EN___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_9__PDADC_CLIP_THRES___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_9__PDADC_CLIP_THRES___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_9___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_9___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_10_B0 (0x005FA1A4) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_10_B0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_10_B0___POR 0x01010000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_10_B0__THERM_RESOLUTION_OFFSET___POR 0x80 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_10_B0__THERM_ADC_SCALED_GAIN_0___POR 0x100 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_10_B0__THERM_ADC_OFFSET_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_10_B0__THERM_RESOLUTION_OFFSET___M 0x01FE0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_10_B0__THERM_RESOLUTION_OFFSET___S 17 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_10_B0__THERM_ADC_SCALED_GAIN_0___M 0x0001FF00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_10_B0__THERM_ADC_SCALED_GAIN_0___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_10_B0__THERM_ADC_OFFSET_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_10_B0__THERM_ADC_OFFSET_0___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_10_B0___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_10_B0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_11_STAT_B0 (0x005FA1A8) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_11_STAT_B0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_11_STAT_B0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_ATB_VALUE_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_VOLT_VALUE_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_THERM_VALUE_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_ATB_VALUE_0___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_ATB_VALUE_0___S 16 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_VOLT_VALUE_0___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_VOLT_VALUE_0___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_THERM_VALUE_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_11_STAT_B0__RO_LATEST_THERM_VALUE_0___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_11_STAT_B0___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_11_STAT_B0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_12_STAT_B0 (0x005FA1AC) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_12_STAT_B0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_12_STAT_B0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_12_STAT_B0__RO_FULL_PKT_AVG_OUT_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_12_STAT_B0__RO_LATEST_DC_VALUE_0___POR 0x000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_12_STAT_B0__RO_PDACC_AVG_OUT_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_12_STAT_B0__RO_FULL_PKT_AVG_OUT_0___M 0x01FE0000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_12_STAT_B0__RO_FULL_PKT_AVG_OUT_0___S 17 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_12_STAT_B0__RO_LATEST_DC_VALUE_0___M 0x0001FF00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_12_STAT_B0__RO_LATEST_DC_VALUE_0___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_12_STAT_B0__RO_PDACC_AVG_OUT_0___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_12_STAT_B0__RO_PDACC_AVG_OUT_0___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_12_STAT_B0___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_12_STAT_B0___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_13 (0x005FA1B0) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_13___POR 0x00000001 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_13__TEMP_MEAS_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_13__TPCRB_DELAY___POR 0x1 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_13__TEMP_MEAS_SEL___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_13__TEMP_MEAS_SEL___S 3 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_13__TPCRB_DELAY___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_13__TPCRB_DELAY___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_13___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_TPC_FB_13___S 0 + +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14 (0x005FA1B4) +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_GNT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_REQ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_CS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_FB_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_VALID___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_PKT_PWR_MEAS_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_PKT_PWR_MEAS_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_ATB_MEAS_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_THERM_MEAS_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_VOLT_MEAS_ON___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_FB_ABORT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_ACC_NXT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_FB_CS___POR 0x00 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_GNT___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_GNT___S 19 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_REQ___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_REQ___S 18 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_CS___M 0x00038000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_TPC_CTRL_CS___S 15 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_FB_ON___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_FB_ON___S 14 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_VALID___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_VALID___S 13 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_EN___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_FULL_PKT_PWR_AVG_EN___S 12 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_PKT_PWR_MEAS_DONE___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_PKT_PWR_MEAS_DONE___S 11 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_PKT_PWR_MEAS_ON___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_PKT_PWR_MEAS_ON___S 10 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_ATB_MEAS_ON___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_ATB_MEAS_ON___S 9 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_THERM_MEAS_ON___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_THERM_MEAS_ON___S 8 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_VOLT_MEAS_ON___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_VOLT_MEAS_ON___S 7 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_FB_ABORT___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_FB_ABORT___S 6 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_ACC_NXT___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_ACC_NXT___S 5 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_FB_CS___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14__RO_FB_CS___S 0 +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_TPC_5G_CH1_RO_TPC_FB_14___S 0 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_MSIP_ID_REG (0x005FA400) +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_MSIP_ID_REG___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_MSIP_ID_REG___POR 0x10000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_MSIP_ID_REG__MSIP_ID_MAJOR___POR 0x1 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_MSIP_ID_REG__MSIP_ID_MINOR___POR 0x000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_MSIP_ID_REG__MSIP_ID_STEP___POR 0x0000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_MSIP_ID_REG__MSIP_ID_MAJOR___M 0xF0000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_MSIP_ID_REG__MSIP_ID_MAJOR___S 28 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_MSIP_ID_REG__MSIP_ID_MINOR___M 0x0FFF0000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_MSIP_ID_REG__MSIP_ID_MINOR___S 16 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_MSIP_ID_REG__MSIP_ID_STEP___M 0x0000FFFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_MSIP_ID_REG__MSIP_ID_STEP___S 0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_MSIP_ID_REG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_MSIP_ID_REG___S 0 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TEST_REG_0 (0x005FA404) +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TEST_REG_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TEST_REG_0___POR 0xDAC1DAC0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TEST_REG_0__TEST_RO___POR 0xDAC1DAC0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TEST_REG_0__TEST_RO___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TEST_REG_0__TEST_RO___S 0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TEST_REG_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TEST_REG_0___S 0 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TEST_REG_1 (0x005FA408) +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TEST_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TEST_REG_1___POR 0x1234ABCD +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TEST_REG_1__TEST_RW___POR 0x1234ABCD +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TEST_REG_1__TEST_RW___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TEST_REG_1__TEST_RW___S 0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TEST_REG_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TEST_REG_1___S 0 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_GLOBAL (0x005FA40C) +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_GLOBAL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_GLOBAL___POR 0x00000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_GLOBAL__RBIST_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_GLOBAL__ATE_WFM_START___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_GLOBAL__RBIST_TX_SW_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_GLOBAL__RBIST_SEL___M 0x00000004 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_GLOBAL__RBIST_SEL___S 2 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_GLOBAL__ATE_WFM_START___M 0x00000002 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_GLOBAL__ATE_WFM_START___S 1 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_GLOBAL__RBIST_TX_SW_RESET___M 0x00000001 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_GLOBAL__RBIST_TX_SW_RESET___S 0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_GLOBAL___M 0x00000007 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_GLOBAL___S 0 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_OUT_SCALING (0x005FA410) +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_OUT_SCALING___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_OUT_SCALING___POR 0x00000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_OUT_SCALING__ATE_TONEGEN_SCALING_ENABLE___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_OUT_SCALING__ATE_TONEGEN_SCALING_I___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_OUT_SCALING__ATE_TONEGEN_SCALING_Q___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_OUT_SCALING__ATE_TONEGEN_SCALING_ENABLE___M 0x00000100 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_OUT_SCALING__ATE_TONEGEN_SCALING_ENABLE___S 8 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_OUT_SCALING__ATE_TONEGEN_SCALING_I___M 0x000000F0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_OUT_SCALING__ATE_TONEGEN_SCALING_I___S 4 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_OUT_SCALING__ATE_TONEGEN_SCALING_Q___M 0x0000000F +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_OUT_SCALING__ATE_TONEGEN_SCALING_Q___S 0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_OUT_SCALING___M 0x000001FF +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_OUT_SCALING___S 0 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_DC_OFFSET (0x005FA414) +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_DC_OFFSET___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_DC_OFFSET___POR 0x00000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_DC_OFFSET__ATE_TONEGEN_DC_ENABLE___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_DC_OFFSET__ATE_TONEGEN_DC_I___POR 0x000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_DC_OFFSET__ATE_TONEGEN_DC_Q___POR 0x000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_DC_OFFSET__ATE_TONEGEN_DC_ENABLE___M 0x01000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_DC_OFFSET__ATE_TONEGEN_DC_ENABLE___S 24 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_DC_OFFSET__ATE_TONEGEN_DC_I___M 0x00FFF000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_DC_OFFSET__ATE_TONEGEN_DC_I___S 12 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_DC_OFFSET__ATE_TONEGEN_DC_Q___M 0x00000FFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_DC_OFFSET__ATE_TONEGEN_DC_Q___S 0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_DC_OFFSET___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_DC_OFFSET___S 0 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0 (0x005FA418) +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0___POR 0x00000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0__ATE_TONEGEN_TONE0_ENABLE___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0__ATE_TONEGEN_TONE0_FREQ___POR 0x00 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_6DB___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_1DB___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0__ATE_TONEGEN_TONE0_DELAY___POR 0x00 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0__ATE_TONEGEN_TONE0_ENABLE___M 0x01000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0__ATE_TONEGEN_TONE0_ENABLE___S 24 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0__ATE_TONEGEN_TONE0_FREQ___M 0x00FF0000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0__ATE_TONEGEN_TONE0_FREQ___S 16 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_6DB___M 0x0000F000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_6DB___S 12 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_1DB___M 0x00000700 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0__ATE_TONEGEN_TONE0_BACKOFF_1DB___S 8 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0__ATE_TONEGEN_TONE0_DELAY___M 0x000000FF +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0__ATE_TONEGEN_TONE0_DELAY___S 0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0___M 0x01FFF7FF +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN0___S 0 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1 (0x005FA41C) +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1___POR 0x00000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1__ATE_TONEGEN_TONE1_ENABLE___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1__ATE_TONEGEN_TONE1_FREQ___POR 0x00 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_6DB___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_1DB___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1__ATE_TONEGEN_TONE1_DELAY___POR 0x00 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1__ATE_TONEGEN_TONE1_ENABLE___M 0x01000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1__ATE_TONEGEN_TONE1_ENABLE___S 24 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1__ATE_TONEGEN_TONE1_FREQ___M 0x00FF0000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1__ATE_TONEGEN_TONE1_FREQ___S 16 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_6DB___M 0x0000F000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_6DB___S 12 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_1DB___M 0x00000700 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1__ATE_TONEGEN_TONE1_BACKOFF_1DB___S 8 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1__ATE_TONEGEN_TONE1_DELAY___M 0x000000FF +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1__ATE_TONEGEN_TONE1_DELAY___S 0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1___M 0x01FFF7FF +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_TONEGEN1___S 0 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0 (0x005FA420) +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0___POR 0x00000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_ENABLE___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_FREQ___POR 0x00 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_6DB___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_1DB___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_DELAY___POR 0x00 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_ENABLE___M 0x01000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_ENABLE___S 24 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_FREQ___M 0x00FF0000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_FREQ___S 16 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_6DB___M 0x0000F000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_6DB___S 12 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_1DB___M 0x00000700 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_BACKOFF_1DB___S 8 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_DELAY___M 0x000000FF +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0__ATE_TONEGEN_LFTONE_DELAY___S 0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0___M 0x01FFF7FF +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LFTONEGEN0___S 0 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_I (0x005FA424) +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_I___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_I___POR 0x00000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_ENABLE_I___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_DWELL_I___POR 0x000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_STEP_I___POR 0x00 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_INIT_I___POR 0x000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_ENABLE_I___M 0x10000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_ENABLE_I___S 28 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_DWELL_I___M 0x0FFC0000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_DWELL_I___S 18 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_STEP_I___M 0x0003F000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_STEP_I___S 12 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_INIT_I___M 0x00000FFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_I__ATE_TONEGEN_LINRAMP_INIT_I___S 0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_I___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_I___S 0 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_Q (0x005FA428) +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_Q___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_Q___POR 0x00000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_ENABLE_Q___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_DWELL_Q___POR 0x000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_STEP_Q___POR 0x00 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_INIT_Q___POR 0x000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_ENABLE_Q___M 0x10000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_ENABLE_Q___S 28 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_DWELL_Q___M 0x0FFC0000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_DWELL_Q___S 18 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_STEP_Q___M 0x0003F000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_STEP_Q___S 12 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_INIT_Q___M 0x00000FFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_Q__ATE_TONEGEN_LINRAMP_INIT_Q___S 0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_Q___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_LINEAR_RAMP_Q___S 0 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_MAG (0x005FA42C) +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_MAG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_MAG___POR 0x00000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_I___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_Q___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_I___POR 0x000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_Q___POR 0x000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_I___M 0x00800000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_I___S 23 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_Q___M 0x00400000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_MAG__ATE_TONEGEN_PRBS_ENABLE_Q___S 22 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_I___M 0x003FF800 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_I___S 11 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_Q___M 0x000007FF +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_MAG__ATE_TONEGEN_PRBS_MAGNITUDE_Q___S 0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_MAG___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_MAG___S 0 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_SEED_I (0x005FA430) +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_SEED_I___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_SEED_I___POR 0x00000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_SEED_I__ATE_TONEGEN_PRBS_SEED_I___POR 0x00000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_SEED_I__ATE_TONEGEN_PRBS_SEED_I___M 0x7FFFFFFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_SEED_I__ATE_TONEGEN_PRBS_SEED_I___S 0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_SEED_I___M 0x7FFFFFFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_SEED_I___S 0 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_SEED_Q (0x005FA434) +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_SEED_Q___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_SEED_Q___POR 0x00000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_SEED_Q__ATE_TONEGEN_PRBS_SEED_Q___POR 0x00000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_SEED_Q__ATE_TONEGEN_PRBS_SEED_Q___M 0x7FFFFFFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_SEED_Q__ATE_TONEGEN_PRBS_SEED_Q___S 0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_SEED_Q___M 0x7FFFFFFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PRBS_SEED_Q___S 0 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM (0x005FA438) +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM___POR 0x000003FF +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_ENABLE___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_SCALING_EN___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_MAGNITUDE___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_START___POR 0x000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_STOP___POR 0x3FF +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_ENABLE___M 0x20000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_ENABLE___S 29 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_SCALING_EN___M 0x10000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_SCALING_EN___S 28 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_MAGNITUDE___M 0x0F000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_MAGNITUDE___S 24 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_START___M 0x000FFC00 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_START___S 10 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_STOP___M 0x000003FF +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM__ATE_TONEGEN_PREAMBLE_STOP___S 0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM___M 0x3F0FFFFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_PREAMBLE_ROM___S 0 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_DIG_TEST_OUT_SEL (0x005FA43C) +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_DIG_TEST_OUT_SEL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_DIG_TEST_OUT_SEL___POR 0x00000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_DIG_TEST_OUT_SEL__DIG_TEST_OUT_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_DIG_TEST_OUT_SEL__DIG_TEST_OUT_SEL___M 0x07800000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_DIG_TEST_OUT_SEL__DIG_TEST_OUT_SEL___S 23 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_DIG_TEST_OUT_SEL___M 0x07800000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_DIG_TEST_OUT_SEL___S 23 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0 (0x005FA440) +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ENABLE___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_MAIN_TAB_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_0___POR 0x000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_1___POR 0x000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_2___POR 0x000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ENABLE___M 0x20000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ENABLE___S 29 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_MAIN_TAB_SEL___M 0x18000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_MAIN_TAB_SEL___S 27 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_0___M 0x07FC0000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_0___S 18 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_1___M 0x0003FE00 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_1___S 9 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_2___M 0x000001FF +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0__ATE_TONEGEN_TXIQ_ICORR_2___S 0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0___M 0x3FFFFFFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_0___S 0 + +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_1 (0x005FA444) +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_0___POR 0x000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_1___POR 0x000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_2___POR 0x000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_0___M 0x07FC0000 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_0___S 18 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_1___M 0x0003FE00 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_1___S 9 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_2___M 0x000001FF +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_1__ATE_TONEGEN_TXIQ_QCORR_2___S 0 +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_1___M 0x07FFFFFF +#define PHYA_IRON2G_RFA_RBIST_TX_CH1_TX_FILTER_CTRL_1___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_CH1_MSIP_ID_REG (0x005FA580) +#define PHYA_IRON2G_RFA_WL_DAC_CH1_MSIP_ID_REG___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_DAC_CH1_MSIP_ID_REG___POR 0x10000000 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_MSIP_ID_REG__MSIP_ID_MAJOR___POR 0x1 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_MSIP_ID_REG__MSIP_ID_MINOR___POR 0x000 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_MSIP_ID_REG__MSIP_ID_STEP___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_MSIP_ID_REG__MSIP_ID_MAJOR___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_MSIP_ID_REG__MSIP_ID_MAJOR___S 28 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_MSIP_ID_REG__MSIP_ID_MINOR___M 0x0FFF0000 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_MSIP_ID_REG__MSIP_ID_MINOR___S 16 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_MSIP_ID_REG__MSIP_ID_STEP___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_DAC_CH1_MSIP_ID_REG__MSIP_ID_STEP___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_MSIP_ID_REG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_DAC_CH1_MSIP_ID_REG___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_CH1_CHIP_ID_REG (0x005FA584) +#define PHYA_IRON2G_RFA_WL_DAC_CH1_CHIP_ID_REG___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_DAC_CH1_CHIP_ID_REG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_CHIP_ID_REG__CHIP_ID___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_CHIP_ID_REG__CHIP_ID___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_CH1_CHIP_ID_REG__CHIP_ID___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_CHIP_ID_REG___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_CH1_CHIP_ID_REG___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_CH1_TEST_REG_0 (0x005FA588) +#define PHYA_IRON2G_RFA_WL_DAC_CH1_TEST_REG_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_DAC_CH1_TEST_REG_0___POR 0xDAC1DAC0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_TEST_REG_0__TEST_RO___POR 0xDAC1DAC0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_TEST_REG_0__TEST_RO___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_DAC_CH1_TEST_REG_0__TEST_RO___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_TEST_REG_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_DAC_CH1_TEST_REG_0___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_CH1_TEST_REG_1 (0x005FA58C) +#define PHYA_IRON2G_RFA_WL_DAC_CH1_TEST_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_CH1_TEST_REG_1___POR 0x1234ABCD +#define PHYA_IRON2G_RFA_WL_DAC_CH1_TEST_REG_1__TEST_RW___POR 0x1234ABCD +#define PHYA_IRON2G_RFA_WL_DAC_CH1_TEST_REG_1__TEST_RW___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_DAC_CH1_TEST_REG_1__TEST_RW___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_TEST_REG_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_DAC_CH1_TEST_REG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0 (0x005FA590) +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0___POR 0x000C5000 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__RBIST_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__D_DAC_AMPLITUDE_GAIN_1___POR 0xC +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__D_DAC_AMPLITUDE_GAIN_0___POR 0x5 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__DAC_SEL_PHYA_PHYB___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__DAC_ATE_TMUX_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__CAL_WR_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__DAC_SW_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__DAC_SIGPATH_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__DAC_CLK_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__RBIST_OV___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__RBIST_OV___S 20 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__D_DAC_AMPLITUDE_GAIN_1___M 0x000F0000 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__D_DAC_AMPLITUDE_GAIN_1___S 16 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__D_DAC_AMPLITUDE_GAIN_0___M 0x0000F000 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__D_DAC_AMPLITUDE_GAIN_0___S 12 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__DAC_SEL_PHYA_PHYB___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__DAC_SEL_PHYA_PHYB___S 10 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__DAC_ATE_TMUX_EN___M 0x00000200 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__DAC_ATE_TMUX_EN___S 9 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__CAL_WR_EN___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__CAL_WR_EN___S 7 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__DAC_SW_RESET___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__DAC_SW_RESET___S 6 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__DAC_SIGPATH_EN_OVS___M 0x00000030 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__DAC_SIGPATH_EN_OVS___S 4 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__DAC_CLK_EN_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0__DAC_CLK_EN_OVS___S 2 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0___M 0x001FF7FC +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_0___S 2 + +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1 (0x005FA594) +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1___POR 0x00000010 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_WARMUP_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_BIAS_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__C_DAC_CLKDIVRST_B_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_Q_FORCEFULLSCALE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_I_FORCEFULLSCALE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_DISABLE_R2RBUFFER___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_CAL_DISABLE_OFFSETDAC___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_ATEST_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_Q_FORCEMIDSCALE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_I_FORCEMIDSCALE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_PWRDN_N___POR 0x1 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_DISABLE_SINK___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_WARMUP_OVS___M 0x03000000 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_WARMUP_OVS___S 24 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_BIAS_EN_OVS___M 0x00C00000 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_BIAS_EN_OVS___S 22 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__C_DAC_CLKDIVRST_B_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__C_DAC_CLKDIVRST_B_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_Q_FORCEFULLSCALE___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_Q_FORCEFULLSCALE___S 19 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_I_FORCEFULLSCALE___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_I_FORCEFULLSCALE___S 18 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_DISABLE_R2RBUFFER___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_DISABLE_R2RBUFFER___S 17 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_CAL_DISABLE_OFFSETDAC___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_CAL_DISABLE_OFFSETDAC___S 16 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_ATEST_SEL___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_ATEST_SEL___S 8 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_Q_FORCEMIDSCALE___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_Q_FORCEMIDSCALE___S 6 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_I_FORCEMIDSCALE___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_I_FORCEMIDSCALE___S 5 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_PWRDN_N___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_PWRDN_N___S 4 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_DISABLE_SINK___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1__D_DAC_DISABLE_SINK___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1___M 0x03FFFF71 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_CTRL_1___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG1 (0x005FA598) +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG1__DAC_REG2_SPARE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG1__DAC_REG2_SPARE___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG1__DAC_REG2_SPARE___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG1___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG1___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2 (0x005FA59C) +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2___POR 0x00000030 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2__DAC_CFG_1_SPARE2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2__D_DAC_VREF___POR 0x3 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2__DAC_CFG_1_SPARE1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2__DISABLE_FIR___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2__DAC_CFG_1_SPARE0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2__DAC_CFG_1_SPARE2___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2__DAC_CFG_1_SPARE2___S 8 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2__D_DAC_VREF___M 0x000000F0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2__D_DAC_VREF___S 4 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2__DAC_CFG_1_SPARE1___M 0x0000000C +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2__DAC_CFG_1_SPARE1___S 2 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2__DISABLE_FIR___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2__DISABLE_FIR___S 1 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2__DAC_CFG_1_SPARE0___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2__DAC_CFG_1_SPARE0___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG2___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG3 (0x005FA5A0) +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG3__DAC_REG3_SPARE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG3__DAC_REG3_SPARE___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG3__DAC_REG3_SPARE___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG3___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG3___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG4 (0x005FA5A4) +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG4__DAC_REG4_SPARE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG4__DAC_REG4_SPARE___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG4__DAC_REG4_SPARE___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG4___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG4___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG5 (0x005FA5A8) +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG5__DAC_REG5_SPARE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG5__DAC_REG5_SPARE___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG5__DAC_REG5_SPARE___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG5___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG5___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG6 (0x005FA5AC) +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG6__DAC_REG6_SPARE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG6__DAC_REG6_SPARE___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG6__DAC_REG6_SPARE___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG6___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG6___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG7 (0x005FA5B0) +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG7__DAC_REG7_SPARE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG7__DAC_REG7_SPARE___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG7__DAC_REG7_SPARE___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG7___M 0x0000003F +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG7___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG8 (0x005FA5B4) +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG8___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG8__CAL_SM_WR___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG8__CAL_SM_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG8__CAL_SM_WR___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG8__CAL_SM_WR___S 1 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG8__CAL_SM_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG8__CAL_SM_EN___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG8___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG8___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG9 (0x005FA5B8) +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG9___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG9___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG9__CAL_SAT_ERR___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG9__CAL_BUSY___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG9__CAL_SAT_ERR___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG9__CAL_SAT_ERR___S 1 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG9__CAL_BUSY___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG9__CAL_BUSY___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG9___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_DAC_CH1_DAC_REG9___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I00 (0x005FA5C0) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I00___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I00___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I00__DAC_CAL_S_I00___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I00__DAC_CAL_S_I00___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I00__DAC_CAL_S_I00___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I00___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I00___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I01 (0x005FA5C4) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I01___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I01___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I01__DAC_CAL_S_I01___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I01__DAC_CAL_S_I01___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I01__DAC_CAL_S_I01___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I01___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I01___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I02 (0x005FA5C8) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I02___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I02___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I02__DAC_CAL_S_I02___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I02__DAC_CAL_S_I02___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I02__DAC_CAL_S_I02___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I02___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I02___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I03 (0x005FA5CC) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I03___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I03___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I03__DAC_CAL_S_I03___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I03__DAC_CAL_S_I03___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I03__DAC_CAL_S_I03___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I03___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I03___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I04 (0x005FA5D0) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I04___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I04___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I04__DAC_CAL_S_I04___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I04__DAC_CAL_S_I04___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I04__DAC_CAL_S_I04___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I04___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I04___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I05 (0x005FA5D4) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I05___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I05___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I05__DAC_CAL_S_I05___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I05__DAC_CAL_S_I05___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I05__DAC_CAL_S_I05___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I05___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I05___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I06 (0x005FA5D8) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I06___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I06___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I06__DAC_CAL_S_I06___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I06__DAC_CAL_S_I06___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I06__DAC_CAL_S_I06___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I06___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I06___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I07 (0x005FA5DC) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I07___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I07___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I07__DAC_CAL_S_I07___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I07__DAC_CAL_S_I07___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I07__DAC_CAL_S_I07___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I07___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I07___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I08 (0x005FA5E0) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I08___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I08___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I08__DAC_CAL_S_I08___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I08__DAC_CAL_S_I08___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I08__DAC_CAL_S_I08___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I08___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I08___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I09 (0x005FA5E4) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I09___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I09___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I09__DAC_CAL_S_I09___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I09__DAC_CAL_S_I09___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I09__DAC_CAL_S_I09___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I09___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I09___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I10 (0x005FA5E8) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I10___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I10__DAC_CAL_S_I10___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I10__DAC_CAL_S_I10___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I10__DAC_CAL_S_I10___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I10___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I10___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I11 (0x005FA5EC) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I11___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I11__DAC_CAL_S_I11___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I11__DAC_CAL_S_I11___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I11__DAC_CAL_S_I11___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I11___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I11___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I12 (0x005FA5F0) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I12___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I12__DAC_CAL_S_I12___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I12__DAC_CAL_S_I12___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I12__DAC_CAL_S_I12___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I12___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I12___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I13 (0x005FA5F4) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I13___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I13__DAC_CAL_S_I13___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I13__DAC_CAL_S_I13___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I13__DAC_CAL_S_I13___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I13___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I13___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I14 (0x005FA5F8) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I14___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I14__DAC_CAL_S_I14___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I14__DAC_CAL_S_I14___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I14__DAC_CAL_S_I14___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I14___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I14___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I15 (0x005FA5FC) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I15___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I15__DAC_CAL_S_I15___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I15__DAC_CAL_S_I15___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I15__DAC_CAL_S_I15___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I15___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I15___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I16 (0x005FA600) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I16___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I16__DAC_CAL_S_I16___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I16__DAC_CAL_S_I16___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I16__DAC_CAL_S_I16___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I16___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I16___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I17 (0x005FA604) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I17___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I17__DAC_CAL_S_I17___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I17__DAC_CAL_S_I17___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I17__DAC_CAL_S_I17___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I17___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I17___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I18 (0x005FA608) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I18___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I18__DAC_CAL_S_I18___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I18__DAC_CAL_S_I18___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I18__DAC_CAL_S_I18___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I18___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I18___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I19 (0x005FA60C) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I19___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I19__DAC_CAL_S_I19___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I19__DAC_CAL_S_I19___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I19__DAC_CAL_S_I19___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I19___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I19___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I20 (0x005FA610) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I20___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I20__DAC_CAL_S_I20___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I20__DAC_CAL_S_I20___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I20__DAC_CAL_S_I20___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I20___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I20___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I21 (0x005FA614) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I21___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I21__DAC_CAL_S_I21___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I21__DAC_CAL_S_I21___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I21__DAC_CAL_S_I21___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I21___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I21___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I22 (0x005FA618) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I22___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I22__DAC_CAL_S_I22___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I22__DAC_CAL_S_I22___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I22__DAC_CAL_S_I22___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I22___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I22___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I23 (0x005FA61C) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I23___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I23__DAC_CAL_S_I23___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I23__DAC_CAL_S_I23___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I23__DAC_CAL_S_I23___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I23___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I23___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I24 (0x005FA620) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I24___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I24__DAC_CAL_S_I24___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I24__DAC_CAL_S_I24___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I24__DAC_CAL_S_I24___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I24___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I24___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I25 (0x005FA624) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I25___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I25__DAC_CAL_S_I25___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I25__DAC_CAL_S_I25___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I25__DAC_CAL_S_I25___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I25___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I25___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I26 (0x005FA628) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I26___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I26__DAC_CAL_S_I26___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I26__DAC_CAL_S_I26___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I26__DAC_CAL_S_I26___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I26___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I26___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I27 (0x005FA62C) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I27___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I27__DAC_CAL_S_I27___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I27__DAC_CAL_S_I27___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I27__DAC_CAL_S_I27___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I27___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I27___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I28 (0x005FA630) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I28___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I28__DAC_CAL_S_I28___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I28__DAC_CAL_S_I28___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I28__DAC_CAL_S_I28___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I28___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I28___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I29 (0x005FA634) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I29___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I29__DAC_CAL_S_I29___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I29__DAC_CAL_S_I29___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I29__DAC_CAL_S_I29___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I29___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I29___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I30 (0x005FA638) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I30___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I30__DAC_CAL_S_I30___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I30__DAC_CAL_S_I30___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I30__DAC_CAL_S_I30___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I30___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I30___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I31 (0x005FA63C) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I31___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I31__DAC_CAL_S_I31___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I31__DAC_CAL_S_I31___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I31__DAC_CAL_S_I31___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I31___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_I31___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q00 (0x005FA640) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q00___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q00___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q00__DAC_CAL_S_Q00___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q00__DAC_CAL_S_Q00___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q00__DAC_CAL_S_Q00___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q00___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q00___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q01 (0x005FA644) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q01___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q01___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q01__DAC_CAL_S_Q01___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q01__DAC_CAL_S_Q01___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q01__DAC_CAL_S_Q01___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q01___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q01___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q02 (0x005FA648) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q02___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q02___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q02__DAC_CAL_S_Q02___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q02__DAC_CAL_S_Q02___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q02__DAC_CAL_S_Q02___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q02___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q02___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q03 (0x005FA64C) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q03___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q03___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q03__DAC_CAL_S_Q03___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q03__DAC_CAL_S_Q03___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q03__DAC_CAL_S_Q03___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q03___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q03___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q04 (0x005FA650) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q04___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q04___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q04__DAC_CAL_S_Q04___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q04__DAC_CAL_S_Q04___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q04__DAC_CAL_S_Q04___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q04___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q04___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q05 (0x005FA654) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q05___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q05___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q05__DAC_CAL_S_Q05___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q05__DAC_CAL_S_Q05___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q05__DAC_CAL_S_Q05___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q05___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q05___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q06 (0x005FA658) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q06___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q06___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q06__DAC_CAL_S_Q06___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q06__DAC_CAL_S_Q06___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q06__DAC_CAL_S_Q06___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q06___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q06___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q07 (0x005FA65C) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q07___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q07___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q07__DAC_CAL_S_Q07___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q07__DAC_CAL_S_Q07___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q07__DAC_CAL_S_Q07___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q07___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q07___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q08 (0x005FA660) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q08___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q08___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q08__DAC_CAL_S_Q08___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q08__DAC_CAL_S_Q08___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q08__DAC_CAL_S_Q08___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q08___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q08___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q09 (0x005FA664) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q09___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q09___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q09__DAC_CAL_S_Q09___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q09__DAC_CAL_S_Q09___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q09__DAC_CAL_S_Q09___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q09___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q09___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q10 (0x005FA668) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q10___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q10__DAC_CAL_S_Q10___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q10__DAC_CAL_S_Q10___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q10__DAC_CAL_S_Q10___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q10___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q10___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q11 (0x005FA66C) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q11___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q11__DAC_CAL_S_Q11___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q11__DAC_CAL_S_Q11___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q11__DAC_CAL_S_Q11___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q11___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q11___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q12 (0x005FA670) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q12___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q12__DAC_CAL_S_Q12___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q12__DAC_CAL_S_Q12___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q12__DAC_CAL_S_Q12___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q12___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q12___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q13 (0x005FA674) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q13___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q13__DAC_CAL_S_Q13___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q13__DAC_CAL_S_Q13___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q13__DAC_CAL_S_Q13___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q13___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q13___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q14 (0x005FA678) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q14___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q14__DAC_CAL_S_Q14___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q14__DAC_CAL_S_Q14___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q14__DAC_CAL_S_Q14___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q14___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q14___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q15 (0x005FA67C) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q15___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q15__DAC_CAL_S_Q15___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q15__DAC_CAL_S_Q15___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q15__DAC_CAL_S_Q15___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q15___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q15___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q16 (0x005FA680) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q16___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q16__DAC_CAL_S_Q16___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q16__DAC_CAL_S_Q16___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q16__DAC_CAL_S_Q16___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q16___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q16___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q17 (0x005FA684) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q17___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q17__DAC_CAL_S_Q17___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q17__DAC_CAL_S_Q17___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q17__DAC_CAL_S_Q17___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q17___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q17___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q18 (0x005FA688) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q18___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q18__DAC_CAL_S_Q18___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q18__DAC_CAL_S_Q18___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q18__DAC_CAL_S_Q18___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q18___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q18___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q19 (0x005FA68C) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q19___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q19__DAC_CAL_S_Q19___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q19__DAC_CAL_S_Q19___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q19__DAC_CAL_S_Q19___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q19___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q19___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q20 (0x005FA690) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q20___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q20__DAC_CAL_S_Q20___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q20__DAC_CAL_S_Q20___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q20__DAC_CAL_S_Q20___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q20___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q20___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q21 (0x005FA694) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q21___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q21__DAC_CAL_S_Q21___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q21__DAC_CAL_S_Q21___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q21__DAC_CAL_S_Q21___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q21___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q21___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q22 (0x005FA698) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q22___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q22__DAC_CAL_S_Q22___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q22__DAC_CAL_S_Q22___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q22__DAC_CAL_S_Q22___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q22___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q22___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q23 (0x005FA69C) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q23___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q23__DAC_CAL_S_Q23___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q23__DAC_CAL_S_Q23___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q23__DAC_CAL_S_Q23___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q23___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q23___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q24 (0x005FA6A0) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q24___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q24__DAC_CAL_S_Q24___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q24__DAC_CAL_S_Q24___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q24__DAC_CAL_S_Q24___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q24___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q24___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q25 (0x005FA6A4) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q25___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q25__DAC_CAL_S_Q25___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q25__DAC_CAL_S_Q25___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q25__DAC_CAL_S_Q25___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q25___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q25___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q26 (0x005FA6A8) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q26___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q26__DAC_CAL_S_Q26___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q26__DAC_CAL_S_Q26___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q26__DAC_CAL_S_Q26___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q26___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q26___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q27 (0x005FA6AC) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q27___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q27__DAC_CAL_S_Q27___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q27__DAC_CAL_S_Q27___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q27__DAC_CAL_S_Q27___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q27___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q27___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q28 (0x005FA6B0) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q28___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q28__DAC_CAL_S_Q28___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q28__DAC_CAL_S_Q28___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q28__DAC_CAL_S_Q28___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q28___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q28___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q29 (0x005FA6B4) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q29___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q29__DAC_CAL_S_Q29___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q29__DAC_CAL_S_Q29___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q29__DAC_CAL_S_Q29___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q29___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q29___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q30 (0x005FA6B8) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q30___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q30__DAC_CAL_S_Q30___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q30__DAC_CAL_S_Q30___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q30__DAC_CAL_S_Q30___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q30___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q30___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q31 (0x005FA6BC) +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q31___POR 0x00000020 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q31__DAC_CAL_S_Q31___POR 0x20 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q31__DAC_CAL_S_Q31___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q31__DAC_CAL_S_Q31___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q31___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_DIG_CORRECTION_CH1_DAC_CAL_REG_Q31___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI0 (0x005FA6C0) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI0__DAC_CAL_BIN_I0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI0__DAC_CAL_BIN_I0___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI0__DAC_CAL_BIN_I0___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI0___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI0___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI1 (0x005FA6C4) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI1__DAC_CAL_BIN_I1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI1__DAC_CAL_BIN_I1___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI1__DAC_CAL_BIN_I1___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI1___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI1___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI2 (0x005FA6C8) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI2__DAC_CAL_BIN_I2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI2__DAC_CAL_BIN_I2___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI2__DAC_CAL_BIN_I2___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI2___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI2___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI3 (0x005FA6CC) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI3__DAC_CAL_BIN_I3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI3__DAC_CAL_BIN_I3___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI3__DAC_CAL_BIN_I3___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI3___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI3___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI4 (0x005FA6D0) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI4__DAC_CAL_BIN_I4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI4__DAC_CAL_BIN_I4___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI4__DAC_CAL_BIN_I4___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI4___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI4___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI5 (0x005FA6D4) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI5__DAC_CAL_BIN_I5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI5__DAC_CAL_BIN_I5___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI5__DAC_CAL_BIN_I5___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI5___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI5___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI6 (0x005FA6D8) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI6__DAC_CAL_BIN_I6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI6__DAC_CAL_BIN_I6___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI6__DAC_CAL_BIN_I6___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI6___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI6___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI7 (0x005FA6DC) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI7__DAC_CAL_BIN_I7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI7__DAC_CAL_BIN_I7___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI7__DAC_CAL_BIN_I7___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI7___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI7___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI8 (0x005FA6E0) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI8___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI8__DAC_CAL_BIN_I8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI8__DAC_CAL_BIN_I8___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI8__DAC_CAL_BIN_I8___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI8___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGI8___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ0 (0x005FA6E4) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ0__DAC_CAL_BIN_Q0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ0__DAC_CAL_BIN_Q0___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ0__DAC_CAL_BIN_Q0___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ0___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ0___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ1 (0x005FA6E8) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ1__DAC_CAL_BIN_Q1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ1__DAC_CAL_BIN_Q1___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ1__DAC_CAL_BIN_Q1___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ1___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ1___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ2 (0x005FA6EC) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ2__DAC_CAL_BIN_Q2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ2__DAC_CAL_BIN_Q2___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ2__DAC_CAL_BIN_Q2___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ2___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ2___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ3 (0x005FA6F0) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ3__DAC_CAL_BIN_Q3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ3__DAC_CAL_BIN_Q3___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ3__DAC_CAL_BIN_Q3___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ3___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ3___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ4 (0x005FA6F4) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ4__DAC_CAL_BIN_Q4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ4__DAC_CAL_BIN_Q4___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ4__DAC_CAL_BIN_Q4___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ4___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ4___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ5 (0x005FA6F8) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ5__DAC_CAL_BIN_Q5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ5__DAC_CAL_BIN_Q5___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ5__DAC_CAL_BIN_Q5___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ5___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ5___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ6 (0x005FA6FC) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ6__DAC_CAL_BIN_Q6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ6__DAC_CAL_BIN_Q6___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ6__DAC_CAL_BIN_Q6___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ6___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ6___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ7 (0x005FA700) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ7__DAC_CAL_BIN_Q7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ7__DAC_CAL_BIN_Q7___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ7__DAC_CAL_BIN_Q7___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ7___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ7___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ8 (0x005FA704) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ8___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ8__DAC_CAL_BIN_Q8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ8__DAC_CAL_BIN_Q8___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ8__DAC_CAL_BIN_Q8___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ8___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_BIN_REGQ8___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1 (0x005FA708) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__DAC_DTEST_PLL_TEST_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__DAC_DTEST_DBG_OUT_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__D_DAC_COMP_OFFSET_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__D_DAC_COMP_OFFSET_OVD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__CAL_SA_OUTPUTS_INVERT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__COMP_IN_INVERT_OFFSET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__DBG_CAL_CLK___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__DBG_CAL_CLK_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__COMP_IN_INVERT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__CAL_N_SAMPLES___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__CAL_STROBE_RESAMP_TMR___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__COMP_SETT_TMR___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__CAL_STROBE_TMR___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__CAL_FSM_FREEZE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__DAC_DTEST_PLL_TEST_SEL___M 0x1C000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__DAC_DTEST_PLL_TEST_SEL___S 26 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__DAC_DTEST_DBG_OUT_SEL___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__DAC_DTEST_DBG_OUT_SEL___S 23 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__D_DAC_COMP_OFFSET_OV___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__D_DAC_COMP_OFFSET_OV___S 22 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__D_DAC_COMP_OFFSET_OVD___M 0x003F0000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__D_DAC_COMP_OFFSET_OVD___S 16 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__CAL_SA_OUTPUTS_INVERT___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__CAL_SA_OUTPUTS_INVERT___S 15 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__COMP_IN_INVERT_OFFSET___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__COMP_IN_INVERT_OFFSET___S 14 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__DBG_CAL_CLK___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__DBG_CAL_CLK___S 13 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__DBG_CAL_CLK_EN___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__DBG_CAL_CLK_EN___S 12 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__COMP_IN_INVERT___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__COMP_IN_INVERT___S 11 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__CAL_N_SAMPLES___M 0x00000600 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__CAL_N_SAMPLES___S 9 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__CAL_STROBE_RESAMP_TMR___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__CAL_STROBE_RESAMP_TMR___S 7 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__COMP_SETT_TMR___M 0x00000060 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__COMP_SETT_TMR___S 5 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__CAL_STROBE_TMR___M 0x00000018 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__CAL_STROBE_TMR___S 3 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__CAL_FSM_FREEZE___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1__CAL_FSM_FREEZE___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1___M 0x1FFFFFFF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG1___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2 (0x005FA70C) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DAC_CAL_REG2_SPARE1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_BIN_DATA___POR 0x000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_MSB_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_DATA_CARRY___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DAC_CAL_REG2_SPARE0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_MSB_VAL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_OFFSET___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_COMP_STROBE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_MODE_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_MODE_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_FSM_BYPASS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DAC_CAL_REG2_SPARE1___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DAC_CAL_REG2_SPARE1___S 31 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_BIN_DATA___M 0x7FC00000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_BIN_DATA___S 22 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_MSB_SEL___M 0x003E0000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_MSB_SEL___S 17 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_DATA_CARRY___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_DATA_CARRY___S 16 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DAC_CAL_REG2_SPARE0___M 0x0000F800 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DAC_CAL_REG2_SPARE0___S 11 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_MSB_VAL___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_MSB_VAL___S 10 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_OFFSET___M 0x000003F0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_OFFSET___S 4 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_COMP_STROBE___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_COMP_STROBE___S 3 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_MODE_Q___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_MODE_Q___S 2 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_MODE_I___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_MODE_I___S 1 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_FSM_BYPASS___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2__DBG_CAL_FSM_BYPASS___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG2___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG3 (0x005FA710) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG3___POR 0x000001FF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG3__DAC_CAL_REG3___POR 0x000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG3__D_DAC_CAL_BIN_SEL___POR 0x1FF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG3__DAC_CAL_REG3___M 0xFFFFFE00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG3__DAC_CAL_REG3___S 9 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG3__D_DAC_CAL_BIN_SEL___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG3__D_DAC_CAL_BIN_SEL___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG3___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG4 (0x005FA714) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG4__DAC_CAL_REG4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG4__DAC_CAL_REG4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG4__DAC_CAL_REG4___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_REG4___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1 (0x005FA718) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1__RO_CAL_SI_ACCUM___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1__DAC_CAL_SM_STATUS1_SPARE___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1__RO_CAL_Q_FROZE_AFTER_CI___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_SI___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_CI___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1__RO_CAL_SI_ACCUM___M 0xFFFF0000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1__RO_CAL_SI_ACCUM___S 16 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1__DAC_CAL_SM_STATUS1_SPARE___M 0x0000FFF8 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1__DAC_CAL_SM_STATUS1_SPARE___S 3 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1__RO_CAL_Q_FROZE_AFTER_CI___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1__RO_CAL_Q_FROZE_AFTER_CI___S 2 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_SI___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_SI___S 1 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_CI___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1__RO_CAL_I_FROZE_AFTER_CI___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG1___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG2 (0x005FA71C) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG2__RO_MAX_CLIP_Q___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG2__RO_MIN_CLIP_Q___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG2__RO_MAX_CLIP_I___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG2__RO_MIN_CLIP_I___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG2__RO_MAX_CLIP_Q___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG2__RO_MAX_CLIP_Q___S 24 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG2__RO_MIN_CLIP_Q___M 0x00FF0000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG2__RO_MIN_CLIP_Q___S 16 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG2__RO_MAX_CLIP_I___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG2__RO_MAX_CLIP_I___S 8 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG2__RO_MIN_CLIP_I___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG2__RO_MIN_CLIP_I___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG2___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG2___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3 (0x005FA720) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CAL_BIN_DATA___POR 0x000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CAL_MSB_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CALDATA_CARRY___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_COMP_OFFSET___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CAL_COMP_STROBE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CAL_MODE_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CAL_MODE_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_COMPOUT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE1___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE1___S 31 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CAL_BIN_DATA___M 0x7FC00000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CAL_BIN_DATA___S 22 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CAL_MSB_SEL___M 0x003E0000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CAL_MSB_SEL___S 17 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CALDATA_CARRY___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CALDATA_CARRY___S 16 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE0___M 0x0000FC00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__DAC_CAL_SM_STATUS3_SPARE0___S 10 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_COMP_OFFSET___M 0x000003F0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_COMP_OFFSET___S 4 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CAL_COMP_STROBE___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CAL_COMP_STROBE___S 3 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CAL_MODE_Q___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CAL_MODE_Q___S 2 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CAL_MODE_I___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_CAL_MODE_I___S 1 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_COMPOUT___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3__RO_COMPOUT___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG3___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG4 (0x005FA724) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG4___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG4__DAC_CAL_SM_STATUS4_SPARE___POR 0x000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG4__RO_CAL_DC_VAL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG4__DAC_CAL_SM_STATUS4_SPARE___M 0xFFFFFF00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG4__DAC_CAL_SM_STATUS4_SPARE___S 8 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG4__RO_CAL_DC_VAL___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG4__RO_CAL_DC_VAL___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG4___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_STATUS_REG4___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_CTRL (0x005FA728) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_CTRL___POR 0x00000004 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_CTRL__DAC_DISABLE_CORRECTION___POR 0x1 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_CTRL__DAC_CAL_RANGE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_CTRL__DAC_DISABLE_CORRECTION___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_CTRL__DAC_DISABLE_CORRECTION___S 2 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_CTRL__DAC_CAL_RANGE___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_CTRL__DAC_CAL_RANGE___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_CTRL___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_SM_CTRL___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG (0x005FA72C) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG__MSB_SEL_OFFSET___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG__CAL_MSB_VAL_OV_REG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG__DAC_EN_D_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG__C_CLKDAC1X_INVERT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG__D_DAC_SPARE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG__MSB_SEL_OFFSET___M 0x0001F000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG__MSB_SEL_OFFSET___S 12 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG__CAL_MSB_VAL_OV_REG___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG__CAL_MSB_VAL_OV_REG___S 11 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG__DAC_EN_D_SEL___M 0x00000600 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG__DAC_EN_D_SEL___S 9 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG__C_CLKDAC1X_INVERT___M 0x00000100 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG__C_CLKDAC1X_INVERT___S 8 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG__D_DAC_SPARE___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG__D_DAC_SPARE___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG___M 0x0001FFFF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_MISC_REG___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_RO_SPARE_REG (0x005FA730) +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_RO_SPARE_REG___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_RO_SPARE_REG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_RO_SPARE_REG__D_DAC_RO_SPARE___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_RO_SPARE_REG__D_DAC_RO_SPARE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_RO_SPARE_REG__D_DAC_RO_SPARE___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_RO_SPARE_REG___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_DAC_MISC_CH1_DAC_RO_SPARE_REG___S 0 + +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0 (0x005FA734) +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKDAC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKDAC_FREQ_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKDAC_FREQ_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKDAC_CAL_FREQ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLK60_FREQ0P5X___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLK60_PHASE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKDAC_PHASE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKDAC_EN_OVS___M 0x30000000 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKDAC_EN_OVS___S 28 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKDAC_FREQ_OV___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKDAC_FREQ_OV___S 23 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKDAC_FREQ_OVD___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKDAC_FREQ_OVD___S 20 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKDAC_CAL_FREQ___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKDAC_CAL_FREQ___S 18 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLK60_FREQ0P5X___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLK60_FREQ0P5X___S 17 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLK60_PHASE___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLK60_PHASE___S 12 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKDAC_PHASE___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKDAC_PHASE___S 0 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0___M 0x30B67007 +#define PHYA_IRON2G_RFA_WL_DAC_BBCLKGEN_CH1_BB_CLKGEN_0___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_MSIP_ID_REG (0x005FA740) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_MSIP_ID_REG___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_MSIP_ID_REG___POR 0x10000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_MSIP_ID_REG__RO_MSIP_ID_MAJOR___POR 0x1 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_MSIP_ID_REG__RO_MSIP_ID_MINOR___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_MSIP_ID_REG__RO_MSIP_ID_STEP___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_MSIP_ID_REG__RO_MSIP_ID_MAJOR___M 0xF0000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_MSIP_ID_REG__RO_MSIP_ID_MAJOR___S 28 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_MSIP_ID_REG__RO_MSIP_ID_MINOR___M 0x0FFF0000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_MSIP_ID_REG__RO_MSIP_ID_MINOR___S 16 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_MSIP_ID_REG__RO_MSIP_ID_STEP___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_MSIP_ID_REG__RO_MSIP_ID_STEP___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_MSIP_ID_REG___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_MSIP_ID_REG___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_TEST_REG_0 (0x005FA744) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_TEST_REG_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_TEST_REG_0___POR 0xADC1ADC0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_TEST_REG_0__RO_TEST___POR 0xADC1ADC0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_TEST_REG_0__RO_TEST___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_TEST_REG_0__RO_TEST___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_TEST_REG_0___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_TEST_REG_0___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_TEST_REG_1 (0x005FA748) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_TEST_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH1_TEST_REG_1___POR 0x1234ABCD +#define PHYA_IRON2G_RFA_WL_ADC_CH1_TEST_REG_1__TEST_RW___POR 0x1234ABCD +#define PHYA_IRON2G_RFA_WL_ADC_CH1_TEST_REG_1__TEST_RW___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_TEST_REG_1__TEST_RW___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_TEST_REG_1___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_TEST_REG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL (0x005FA74C) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL___POR 0x00003000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__D_ADC_EN_Q_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__D_ADC_EN_I_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__ADC_DATA_GPIO_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__RBIST_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__SEL_NATIVE_CHAIN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__D_ADC_PWRDN_N___POR 0x1 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__PHY_ADC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__ADC_EN_Q_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__ADC_EN_I_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__CAL_START___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__OUTDISBL_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__OUTDISBL_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__D_TI_MODE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__D_DIGITAL_CLAMP___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__D_ADC_EN_Q_OVS___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__D_ADC_EN_Q_OVS___S 20 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__D_ADC_EN_I_OVS___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__D_ADC_EN_I_OVS___S 18 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__ADC_DATA_GPIO_SEL___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__ADC_DATA_GPIO_SEL___S 16 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__RBIST_OV___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__RBIST_OV___S 14 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__SEL_NATIVE_CHAIN___M 0x00002000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__SEL_NATIVE_CHAIN___S 13 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__D_ADC_PWRDN_N___M 0x00001000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__D_ADC_PWRDN_N___S 12 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__PHY_ADC_EN_OVS___M 0x00000C00 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__PHY_ADC_EN_OVS___S 10 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__ADC_EN_Q_OVS___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__ADC_EN_Q_OVS___S 8 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__ADC_EN_I_OVS___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__ADC_EN_I_OVS___S 6 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__CAL_START___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__CAL_START___S 5 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__OUTDISBL_Q___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__OUTDISBL_Q___S 4 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__OUTDISBL_I___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__OUTDISBL_I___S 3 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__D_TI_MODE___M 0x00000006 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__D_TI_MODE___S 1 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__D_DIGITAL_CLAMP___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL__D_DIGITAL_CLAMP___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL___M 0x003F7FFF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CTRL___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG (0x005FA750) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__D_ADC_TI_MODE_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__D_ADC_TI_MODE_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__USE_ODD_CORE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__ADC_ATE_DEC_RATIO___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__ADC_ATE_RX_PATH_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__ADC_ATE_TMUX_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__ADC_SW_RESET___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__D_ADC_TI_MODE_OV___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__D_ADC_TI_MODE_OV___S 10 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__D_ADC_TI_MODE_OVD___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__D_ADC_TI_MODE_OVD___S 8 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__USE_ODD_CORE___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__USE_ODD_CORE___S 7 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__ADC_ATE_DEC_RATIO___M 0x00000070 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__ADC_ATE_DEC_RATIO___S 4 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__ADC_ATE_RX_PATH_EN___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__ADC_ATE_RX_PATH_EN___S 3 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__ADC_ATE_TMUX_EN___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__ADC_ATE_TMUX_EN___S 2 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__ADC_SW_RESET___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG__ADC_SW_RESET___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG___M 0x000007FD +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CONFIG___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_STATUS (0x005FA754) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_STATUS___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_STATUS___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_STATUS__RO_CAL_ERROR___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_STATUS__RO_CAL_DONE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_STATUS__RO_CAL_ERROR___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_STATUS__RO_CAL_ERROR___S 1 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_STATUS__RO_CAL_DONE___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_STATUS__RO_CAL_DONE___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_STATUS___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_STATUS___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0 (0x005FA758) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_IN_CLAMP_DISABLE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_TP_ANA_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_DTEST_INVERT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_DTEST_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_DTEST_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_ATEST_V_OR_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_ATEST_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_RED_ENB___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_RST_WIDTH_SEL___POR 0x00 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_IN_CLAMP_DISABLE___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_IN_CLAMP_DISABLE___S 31 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_TP_ANA_EN___M 0x40000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_TP_ANA_EN___S 30 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_DTEST_INVERT___M 0x20000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_DTEST_INVERT___S 29 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_DTEST_SEL___M 0x1F800000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_DTEST_SEL___S 23 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_DTEST_EN___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_DTEST_EN___S 22 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_ATEST_V_OR_I___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_ATEST_V_OR_I___S 21 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_ATEST_SEL___M 0x001E0000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_ATEST_SEL___S 17 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_RED_ENB___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_RED_ENB___S 16 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_RST_WIDTH_SEL___M 0x0000FC00 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0__D_RST_WIDTH_SEL___S 10 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0___M 0xFFFFFC00 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG0___S 10 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG1 (0x005FA75C) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG1__D_CMP_VCM_SEL_Q___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG1__D_CMP_VCM_SEL_I___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG1__D_TP_ANA_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG1__D_CMP_VCM_SEL_Q___M 0x03FE0000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG1__D_CMP_VCM_SEL_Q___S 17 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG1__D_CMP_VCM_SEL_I___M 0x00001FF0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG1__D_CMP_VCM_SEL_I___S 4 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG1__D_TP_ANA_SEL___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG1__D_TP_ANA_SEL___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG1___M 0x03FE1FF3 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG1___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG2 (0x005FA760) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG2__D_DTEST_DIV3_INVERT___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG2__D_DTEST_DIV3_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG2__D_CLKGEN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG2__D_AAF_MISC___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG2__D_DTEST_DIV3_INVERT___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG2__D_DTEST_DIV3_INVERT___S 17 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG2__D_DTEST_DIV3_EN___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG2__D_DTEST_DIV3_EN___S 16 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG2__D_CLKGEN___M 0x0000FF00 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG2__D_CLKGEN___S 8 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG2__D_AAF_MISC___M 0x00000007 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG2__D_AAF_MISC___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG2___M 0x0003FF07 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG2___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG3 (0x005FA764) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG3__D_DBG___POR 0x00 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG3__D_SPARE___POR 0x000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG3__D_DBG___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG3__D_DBG___S 24 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG3__D_SPARE___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG3__D_SPARE___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG3___M 0xFFFFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_AC_REG3___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0 (0x005FA768) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0___POR 0x00003000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__TIGEC_FR_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_LSB_CAL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__SW_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__FR_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__REDC_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__SRST_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__D_OS_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__CAL_WR_EN___POR 0x3 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__D_BP_BYPASS_NC___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__CLK_EDGE_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__REDC_POSTP_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_TIGEC_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_SDM_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_CAL_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_TIGEC_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_SDM_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_CAL_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__CAL_ST_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__TIGEC_FR_SEL___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__TIGEC_FR_SEL___S 23 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_LSB_CAL___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_LSB_CAL___S 22 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__SW_SEL___M 0x00300000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__SW_SEL___S 20 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__FR_SEL___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__FR_SEL___S 18 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__REDC_SEL___M 0x00030000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__REDC_SEL___S 16 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__SRST_SEL___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__SRST_SEL___S 15 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__D_OS_SEL___M 0x00004000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__D_OS_SEL___S 14 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__CAL_WR_EN___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__CAL_WR_EN___S 12 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__D_BP_BYPASS_NC___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__D_BP_BYPASS_NC___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__CLK_EDGE_SEL___M 0x00000400 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__CLK_EDGE_SEL___S 10 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__REDC_POSTP_SEL___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__REDC_POSTP_SEL___S 8 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_TIGEC_Q___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_TIGEC_Q___S 7 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_SDM_Q___M 0x00000040 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_SDM_Q___S 6 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_CAL_Q___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_CAL_Q___S 5 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_TIGEC_I___M 0x00000010 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_TIGEC_I___S 4 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_SDM_I___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_SDM_I___S 3 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_CAL_I___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__BYPASS_CAL_I___S 2 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__CAL_ST_SEL___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0__CAL_ST_SEL___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_CAL_REG_0___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG (0x005FA76C) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__CAL_ENGINE_CORE_ENABLE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TEST_ADC_STATE_EN_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TEST_ADC_STATE_EN_I___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TEST_PATTERN_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TEST_PATTERN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TI_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__CHANNEL_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__ENABLE_CAL_READ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TEST_PATTERN_IN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__DIN_DBG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__CLK_DBG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__CAL_HS_DBG_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__CAL_DBG_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__CAL_ENGINE_CORE_ENABLE___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__CAL_ENGINE_CORE_ENABLE___S 25 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TEST_ADC_STATE_EN_Q___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TEST_ADC_STATE_EN_Q___S 24 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TEST_ADC_STATE_EN_I___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TEST_ADC_STATE_EN_I___S 23 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TEST_PATTERN_EN___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TEST_PATTERN_EN___S 22 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TEST_PATTERN___M 0x00380000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TEST_PATTERN___S 19 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TI_SEL___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TI_SEL___S 18 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__CHANNEL_SEL___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__CHANNEL_SEL___S 17 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__ENABLE_CAL_READ___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__ENABLE_CAL_READ___S 16 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TEST_PATTERN_IN___M 0x0000FFF0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__TEST_PATTERN_IN___S 4 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__DIN_DBG___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__DIN_DBG___S 3 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__CLK_DBG___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__CLK_DBG___S 2 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__CAL_HS_DBG_EN___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__CAL_HS_DBG_EN___S 1 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__CAL_DBG_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG__CAL_DBG_EN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG___M 0x0FFFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_DBG_REG___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_0 (0x005FA770) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_0___POR 0x02020410 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_0__W2_I_EVEN___POR 0x80 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_0__W1_I_EVEN___POR 0x40 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_0__W0P5LSB_I_EVEN___POR 0x20 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_0__W0P25LSB_I_EVEN___POR 0x10 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_0__W2_I_EVEN___M 0x03FC0000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_0__W2_I_EVEN___S 18 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_0__W1_I_EVEN___M 0x0003F800 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_0__W1_I_EVEN___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_0__W0P5LSB_I_EVEN___M 0x000007E0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_0__W0P5LSB_I_EVEN___S 5 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_0__W0P25LSB_I_EVEN___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_0__W0P25LSB_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_0___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_0___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_1 (0x005FA774) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_1___POR 0x10040100 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_1__WREDC_I_EVEN___POR 0x200 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_1__W4_I_EVEN___POR 0x200 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_1__W3_I_EVEN___POR 0x100 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_1__WREDC_I_EVEN___M 0x3FF80000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_1__WREDC_I_EVEN___S 19 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_1__W4_I_EVEN___M 0x0007FE00 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_1__W4_I_EVEN___S 9 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_1__W3_I_EVEN___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_1__W3_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_1___M 0x3FFFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_2 (0x005FA778) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_2___POR 0x00000200 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_2__WREDC_POSTP_I_EVEN___POR 0x200 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_2__WREDC_POSTP_I_EVEN___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_2__WREDC_POSTP_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_2___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_EVEN_LSB_WEIGHT_REG_2___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_0 (0x005FA77C) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_0___POR 0x02020410 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_0__W2_I_ODD___POR 0x80 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_0__W1_I_ODD___POR 0x40 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_0__W0P5LSB_I_ODD___POR 0x20 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_0__W0P25LSB_I_ODD___POR 0x10 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_0__W2_I_ODD___M 0x03FC0000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_0__W2_I_ODD___S 18 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_0__W1_I_ODD___M 0x0003F800 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_0__W1_I_ODD___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_0__W0P5LSB_I_ODD___M 0x000007E0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_0__W0P5LSB_I_ODD___S 5 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_0__W0P25LSB_I_ODD___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_0__W0P25LSB_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_0___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_0___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_1 (0x005FA780) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_1___POR 0x10040100 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_1__WREDC_I_ODD___POR 0x200 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_1__W4_I_ODD___POR 0x200 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_1__W3_I_ODD___POR 0x100 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_1__WREDC_I_ODD___M 0x3FF80000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_1__WREDC_I_ODD___S 19 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_1__W4_I_ODD___M 0x0007FE00 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_1__W4_I_ODD___S 9 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_1__W3_I_ODD___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_1__W3_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_1___M 0x3FFFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_2 (0x005FA784) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_2___POR 0x00000200 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_2__WREDC_POSTP_I_ODD___POR 0x200 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_2__WREDC_POSTP_I_ODD___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_2__WREDC_POSTP_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_2___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_I_ODD_LSB_WEIGHT_REG_2___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_0 (0x005FA788) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_0___POR 0x02020410 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W2_Q_EVEN___POR 0x80 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W1_Q_EVEN___POR 0x40 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W0P5LSB_Q_EVEN___POR 0x20 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W0P25LSB_Q_EVEN___POR 0x10 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W2_Q_EVEN___M 0x03FC0000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W2_Q_EVEN___S 18 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W1_Q_EVEN___M 0x0003F800 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W1_Q_EVEN___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W0P5LSB_Q_EVEN___M 0x000007E0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W0P5LSB_Q_EVEN___S 5 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W0P25LSB_Q_EVEN___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_0__W0P25LSB_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_0___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_0___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_1 (0x005FA78C) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_1___POR 0x10040100 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_1__WREDC_Q_EVEN___POR 0x200 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_1__W4_Q_EVEN___POR 0x200 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_1__W3_Q_EVEN___POR 0x100 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_1__WREDC_Q_EVEN___M 0x3FF80000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_1__WREDC_Q_EVEN___S 19 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_1__W4_Q_EVEN___M 0x0007FE00 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_1__W4_Q_EVEN___S 9 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_1__W3_Q_EVEN___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_1__W3_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_1___M 0x3FFFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_2 (0x005FA790) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_2___POR 0x00000200 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_2__WREDC_POSTP_Q_EVEN___POR 0x200 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_2__WREDC_POSTP_Q_EVEN___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_2__WREDC_POSTP_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_2___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_EVEN_LSB_WEIGHT_REG_2___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_0 (0x005FA794) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_0___POR 0x02020410 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_0__W2_Q_ODD___POR 0x80 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_0__W1_Q_ODD___POR 0x40 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_0__W0P5LSB_Q_ODD___POR 0x20 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_0__W0P25LSB_Q_ODD___POR 0x10 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_0__W2_Q_ODD___M 0x03FC0000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_0__W2_Q_ODD___S 18 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_0__W1_Q_ODD___M 0x0003F800 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_0__W1_Q_ODD___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_0__W0P5LSB_Q_ODD___M 0x000007E0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_0__W0P5LSB_Q_ODD___S 5 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_0__W0P25LSB_Q_ODD___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_0__W0P25LSB_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_0___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_0___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_1 (0x005FA798) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_1___POR 0x10040100 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_1__WREDC_Q_ODD___POR 0x200 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_1__W4_Q_ODD___POR 0x200 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_1__W3_Q_ODD___POR 0x100 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_1__WREDC_Q_ODD___M 0x3FF80000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_1__WREDC_Q_ODD___S 19 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_1__W4_Q_ODD___M 0x0007FE00 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_1__W4_Q_ODD___S 9 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_1__W3_Q_ODD___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_1__W3_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_1___M 0x3FFFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_2 (0x005FA79C) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_2___POR 0x00000200 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_2__WREDC_POSTP_Q_ODD___POR 0x200 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_2__WREDC_POSTP_Q_ODD___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_2__WREDC_POSTP_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_2___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_Q_ODD_LSB_WEIGHT_REG_2___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0 (0x005FA7A0) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0___POR 0x00400001 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME___POR 0x00 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_FLIP_EVEN_ODD___POR 0x1 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_IGNORE_LIN_SEARCH___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_IGNORE_BIN_SEARCH___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_Q_ODD_DISABLE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_Q_EVEN_DISABLE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_I_ODD_DISABLE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_I_EVEN_DISABLE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_LIN_STEP_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_BIN_STEP_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME_SEL_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME_SEL_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_SETT_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_ST_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_RETIMED_CLK___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_IGNORE_FLAG___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_EN___POR 0x1 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME___M 0xFF000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME___S 24 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_FLIP_EVEN_ODD___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_FLIP_EVEN_ODD___S 22 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_IGNORE_LIN_SEARCH___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_IGNORE_LIN_SEARCH___S 21 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_IGNORE_BIN_SEARCH___M 0x00100000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_IGNORE_BIN_SEARCH___S 20 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_Q_ODD_DISABLE___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_Q_ODD_DISABLE___S 19 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_Q_EVEN_DISABLE___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_Q_EVEN_DISABLE___S 18 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_I_ODD_DISABLE___M 0x00020000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_I_ODD_DISABLE___S 17 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_I_EVEN_DISABLE___M 0x00010000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_I_EVEN_DISABLE___S 16 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_LIN_STEP_SEL___M 0x0000C000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_LIN_STEP_SEL___S 14 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_BIN_STEP_SEL___M 0x00003000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_BIN_STEP_SEL___S 12 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME_SEL_OV___M 0x00000800 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME_SEL_OV___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME_SEL_OVD___M 0x00000700 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_LOOPBACK_TIME_SEL_OVD___S 8 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_SETT_SEL___M 0x000000C0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_SETT_SEL___S 6 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_ST_SEL___M 0x00000030 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_ST_SEL___S 4 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_RETIMED_CLK___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_RETIMED_CLK___S 2 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_IGNORE_FLAG___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_IGNORE_FLAG___S 1 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_EN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0__VCM_TRACK_EN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0___M 0xFF7FFFF7 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_0___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_1 (0x005FA7A4) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_1__VCM_TRACK_Q_ODD_ADJ_PN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_1__VCM_TRACK_Q_EVEN_ADJ_PN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_1__VCM_TRACK_I_ODD_ADJ_PN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_1__VCM_TRACK_I_EVEN_ADJ_PN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_1__VCM_TRACK_Q_ODD_ADJ_PN___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_1__VCM_TRACK_Q_ODD_ADJ_PN___S 3 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_1__VCM_TRACK_Q_EVEN_ADJ_PN___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_1__VCM_TRACK_Q_EVEN_ADJ_PN___S 2 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_1__VCM_TRACK_I_ODD_ADJ_PN___M 0x00000002 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_1__VCM_TRACK_I_ODD_ADJ_PN___S 1 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_1__VCM_TRACK_I_EVEN_ADJ_PN___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_1__VCM_TRACK_I_EVEN_ADJ_PN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_1___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_REG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0 (0x005FA7A8) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_FAIL_I_EVEN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PN_OVERFLOW_I_EVEN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_I_EVEN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PN_I_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PP_I_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_FAIL_I_EVEN___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_FAIL_I_EVEN___S 24 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PN_OVERFLOW_I_EVEN___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PN_OVERFLOW_I_EVEN___S 23 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_I_EVEN___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_I_EVEN___S 22 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PN_I_EVEN___M 0x003FF800 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PN_I_EVEN___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PP_I_EVEN___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0__RO_VCM_TRACK_PP_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_EVEN_REG_0___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_1 (0x005FA7AC) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_1___POR 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PP_PN_OVERRIDE_I_EVEN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PN_I_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PP_I_EVEN___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PP_PN_OVERRIDE_I_EVEN___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PP_PN_OVERRIDE_I_EVEN___S 22 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PN_I_EVEN___M 0x003FF800 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PN_I_EVEN___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PP_I_EVEN___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_1__VCM_TRACK_PP_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_1___M 0x007FFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_2 (0x005FA7B0) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_2___POR 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_2__VCM_TRACK_PN_I_EVEN_INIT___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_2__VCM_TRACK_PP_I_EVEN_INIT___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_2__VCM_TRACK_PN_I_EVEN_INIT___M 0x003FF800 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_2__VCM_TRACK_PN_I_EVEN_INIT___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_2__VCM_TRACK_PP_I_EVEN_INIT___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_2__VCM_TRACK_PP_I_EVEN_INIT___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_2___M 0x003FFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_EVEN_REG_2___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0 (0x005FA7B4) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_FAIL_I_ODD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PN_OVERFLOW_I_ODD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_I_ODD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PN_I_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PP_I_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_FAIL_I_ODD___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_FAIL_I_ODD___S 24 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PN_OVERFLOW_I_ODD___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PN_OVERFLOW_I_ODD___S 23 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_I_ODD___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_I_ODD___S 22 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PN_I_ODD___M 0x003FF800 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PN_I_ODD___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PP_I_ODD___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0__RO_VCM_TRACK_PP_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_I_ODD_REG_0___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_1 (0x005FA7B8) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_1___POR 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PP_PN_OVERRIDE_I_ODD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PN_I_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PP_I_ODD___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PP_PN_OVERRIDE_I_ODD___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PP_PN_OVERRIDE_I_ODD___S 22 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PN_I_ODD___M 0x003FF800 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PN_I_ODD___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PP_I_ODD___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_1__VCM_TRACK_PP_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_1___M 0x007FFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_2 (0x005FA7BC) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_2___POR 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_2__VCM_TRACK_PN_I_ODD_INIT___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_2__VCM_TRACK_PP_I_ODD_INIT___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_2__VCM_TRACK_PN_I_ODD_INIT___M 0x003FF800 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_2__VCM_TRACK_PN_I_ODD_INIT___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_2__VCM_TRACK_PP_I_ODD_INIT___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_2__VCM_TRACK_PP_I_ODD_INIT___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_2___M 0x003FFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_I_ODD_REG_2___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0 (0x005FA7C0) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_FAIL_Q_EVEN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PN_OVERFLOW_Q_EVEN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_Q_EVEN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PN_Q_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PP_Q_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_FAIL_Q_EVEN___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_FAIL_Q_EVEN___S 24 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PN_OVERFLOW_Q_EVEN___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PN_OVERFLOW_Q_EVEN___S 23 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_Q_EVEN___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_Q_EVEN___S 22 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PN_Q_EVEN___M 0x003FF800 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PN_Q_EVEN___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PP_Q_EVEN___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0__RO_VCM_TRACK_PP_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_EVEN_REG_0___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_1 (0x005FA7C4) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_1___POR 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PP_PN_OVERRIDE_Q_EVEN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PN_Q_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PP_Q_EVEN___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PP_PN_OVERRIDE_Q_EVEN___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PP_PN_OVERRIDE_Q_EVEN___S 22 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PN_Q_EVEN___M 0x003FF800 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PN_Q_EVEN___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PP_Q_EVEN___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_1__VCM_TRACK_PP_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_1___M 0x007FFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_2 (0x005FA7C8) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_2___POR 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_2__VCM_TRACK_PN_Q_EVEN_INIT___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_2__VCM_TRACK_PP_Q_EVEN_INIT___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_2__VCM_TRACK_PN_Q_EVEN_INIT___M 0x003FF800 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_2__VCM_TRACK_PN_Q_EVEN_INIT___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_2__VCM_TRACK_PP_Q_EVEN_INIT___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_2__VCM_TRACK_PP_Q_EVEN_INIT___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_2___M 0x003FFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_EVEN_REG_2___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0 (0x005FA7CC) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_FAIL_Q_ODD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PN_OVERFLOW_Q_ODD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_Q_ODD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PN_Q_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PP_Q_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_FAIL_Q_ODD___M 0x01000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_FAIL_Q_ODD___S 24 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PN_OVERFLOW_Q_ODD___M 0x00800000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PN_OVERFLOW_Q_ODD___S 23 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_Q_ODD___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PP_UNDERFLOW_Q_ODD___S 22 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PN_Q_ODD___M 0x003FF800 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PN_Q_ODD___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PP_Q_ODD___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0__RO_VCM_TRACK_PP_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0___M 0x01FFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_RO_ADC_VCM_TRACK_Q_ODD_REG_0___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_1 (0x005FA7D0) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_1___POR 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PP_PN_OVERRIDE_Q_ODD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PN_Q_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PP_Q_ODD___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PP_PN_OVERRIDE_Q_ODD___M 0x00400000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PP_PN_OVERRIDE_Q_ODD___S 22 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PN_Q_ODD___M 0x003FF800 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PN_Q_ODD___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PP_Q_ODD___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_1__VCM_TRACK_PP_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_1___M 0x007FFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_2 (0x005FA7D4) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_2___POR 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_2__VCM_TRACK_PN_Q_ODD_INIT___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_2__VCM_TRACK_PP_Q_ODD_INIT___POR 0x7FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_2__VCM_TRACK_PN_Q_ODD_INIT___M 0x003FF800 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_2__VCM_TRACK_PN_Q_ODD_INIT___S 11 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_2__VCM_TRACK_PP_Q_ODD_INIT___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_2__VCM_TRACK_PP_Q_ODD_INIT___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_2___M 0x003FFFFF +#define PHYA_IRON2G_RFA_WL_ADC_CH1_ADC_VCM_TRACK_Q_ODD_REG_2___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_CH1_PDADC_CTRL_REG (0x005FA7D8) +#define PHYA_IRON2G_RFA_WL_ADC_CH1_PDADC_CTRL_REG___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_CH1_PDADC_CTRL_REG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_PDADC_CTRL_REG__PDADC_SEL_I_Q___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_PDADC_CTRL_REG__PDADC_STROBE_EN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_PDADC_CTRL_REG__PDADC_SEL_I_Q___M 0x00000008 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_PDADC_CTRL_REG__PDADC_SEL_I_Q___S 3 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_PDADC_CTRL_REG__PDADC_STROBE_EN___M 0x00000004 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_PDADC_CTRL_REG__PDADC_STROBE_EN___S 2 +#define PHYA_IRON2G_RFA_WL_ADC_CH1_PDADC_CTRL_REG___M 0x0000000C +#define PHYA_IRON2G_RFA_WL_ADC_CH1_PDADC_CTRL_REG___S 2 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_1 (0x005FA800) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_1__WOS_C_I_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_1__WOS_C_I_EVEN___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_1__WOS_C_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_1___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_2 (0x005FA804) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_2__WOS_F_I_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_2__WOS_F_I_EVEN___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_2__WOS_F_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_2___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_2___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_3 (0x005FA808) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_3___POR 0x00000400 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_3__W5_I_EVEN___POR 0x400 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_3__W5_I_EVEN___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_3__W5_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_3___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_3___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_4 (0x005FA80C) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_4___POR 0x00000800 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_4__W6_I_EVEN___POR 0x800 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_4__W6_I_EVEN___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_4__W6_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_4___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_4___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_5 (0x005FA810) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_5___POR 0x00001000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_5__W7_I_EVEN___POR 0x1000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_5__W7_I_EVEN___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_5__W7_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_5___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_5___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_6 (0x005FA814) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_6___POR 0x00002000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_6__W8_I_EVEN___POR 0x2000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_6__W8_I_EVEN___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_6__W8_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_6___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_6___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_7 (0x005FA818) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_7___POR 0x00004000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_7__W9_I_EVEN___POR 0x4000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_7__W9_I_EVEN___M 0x00007FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_7__W9_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_7___M 0x00007FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_EVEN_CH1_ADC_POST_PROC_I_EVEN_REG_7___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_1 (0x005FA840) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_1__WOS_C_I_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_1__WOS_C_I_ODD___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_1__WOS_C_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_1___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_2 (0x005FA844) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_2__WOS_F_I_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_2__WOS_F_I_ODD___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_2__WOS_F_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_2___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_2___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_3 (0x005FA848) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_3___POR 0x00000400 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_3__W5_I_ODD___POR 0x400 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_3__W5_I_ODD___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_3__W5_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_3___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_3___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_4 (0x005FA84C) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_4___POR 0x00000800 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_4__W6_I_ODD___POR 0x800 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_4__W6_I_ODD___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_4__W6_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_4___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_4___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_5 (0x005FA850) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_5___POR 0x00001000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_5__W7_I_ODD___POR 0x1000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_5__W7_I_ODD___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_5__W7_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_5___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_5___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_6 (0x005FA854) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_6___POR 0x00002000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_6__W8_I_ODD___POR 0x2000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_6__W8_I_ODD___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_6__W8_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_6___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_6___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_7 (0x005FA858) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_7___POR 0x00004000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_7__W9_I_ODD___POR 0x4000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_7__W9_I_ODD___M 0x00007FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_7__W9_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_7___M 0x00007FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_I_ODD_CH1_ADC_POST_PROC_I_ODD_REG_7___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_1 (0x005FA880) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_1__WOS_C_Q_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_1__WOS_C_Q_EVEN___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_1__WOS_C_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_1___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_2 (0x005FA884) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_2__WOS_F_Q_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_2__WOS_F_Q_EVEN___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_2__WOS_F_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_2___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_2___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_3 (0x005FA888) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_3___POR 0x00000400 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_3__W5_Q_EVEN___POR 0x400 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_3__W5_Q_EVEN___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_3__W5_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_3___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_3___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_4 (0x005FA88C) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_4___POR 0x00000800 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_4__W6_Q_EVEN___POR 0x800 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_4__W6_Q_EVEN___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_4__W6_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_4___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_4___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_5 (0x005FA890) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_5___POR 0x00001000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_5__W7_Q_EVEN___POR 0x1000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_5__W7_Q_EVEN___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_5__W7_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_5___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_5___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_6 (0x005FA894) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_6___POR 0x00002000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_6__W8_Q_EVEN___POR 0x2000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_6__W8_Q_EVEN___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_6__W8_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_6___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_6___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_7 (0x005FA898) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_7___POR 0x00004000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_7__W9_Q_EVEN___POR 0x4000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_7__W9_Q_EVEN___M 0x00007FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_7__W9_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_7___M 0x00007FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_EVEN_CH1_ADC_POST_PROC_Q_EVEN_REG_7___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_1 (0x005FA8C0) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_1__WOS_C_Q_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_1__WOS_C_Q_ODD___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_1__WOS_C_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_1___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_2 (0x005FA8C4) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_2__WOS_F_Q_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_2__WOS_F_Q_ODD___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_2__WOS_F_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_2___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_2___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_3 (0x005FA8C8) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_3___POR 0x00000400 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_3__W5_Q_ODD___POR 0x400 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_3__W5_Q_ODD___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_3__W5_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_3___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_3___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_4 (0x005FA8CC) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_4___POR 0x00000800 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_4__W6_Q_ODD___POR 0x800 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_4__W6_Q_ODD___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_4__W6_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_4___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_4___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_5 (0x005FA8D0) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_5___POR 0x00001000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_5__W7_Q_ODD___POR 0x1000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_5__W7_Q_ODD___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_5__W7_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_5___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_5___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_6 (0x005FA8D4) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_6___POR 0x00002000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_6__W8_Q_ODD___POR 0x2000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_6__W8_Q_ODD___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_6__W8_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_6___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_6___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_7 (0x005FA8D8) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_7___POR 0x00004000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_7__W9_Q_ODD___POR 0x4000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_7__W9_Q_ODD___M 0x00007FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_7__W9_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_7___M 0x00007FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_Q_ODD_CH1_ADC_POST_PROC_Q_ODD_REG_7___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_1 (0x005FA900) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_1___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_1__RO_WOS_C_I_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_1__RO_WOS_C_I_EVEN___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_1__RO_WOS_C_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_1___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_1___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_2 (0x005FA904) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_2___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_2__RO_WOS_F_I_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_2__RO_WOS_F_I_EVEN___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_2__RO_WOS_F_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_2___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_2___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_3 (0x005FA908) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_3___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_3__RO_W5_I_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_3__RO_W5_I_EVEN___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_3__RO_W5_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_3___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_3___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_4 (0x005FA90C) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_4___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_4__RO_W6_I_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_4__RO_W6_I_EVEN___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_4__RO_W6_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_4___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_4___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_5 (0x005FA910) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_5___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_5__RO_W7_I_EVEN___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_5__RO_W7_I_EVEN___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_5__RO_W7_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_5___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_5___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_6 (0x005FA914) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_6___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_6__RO_W8_I_EVEN___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_6__RO_W8_I_EVEN___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_6__RO_W8_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_6___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_6___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_7 (0x005FA918) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_7___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_7__RO_W9_I_EVEN___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_7__RO_W9_I_EVEN___M 0x00007FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_7__RO_W9_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_7___M 0x00007FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_7___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_8 (0x005FA91C) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_8___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_8__RO_CAL_DONE_I_EVEN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_8__RO_WCAL_FLAG_I_EVEN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_8__RO_CAL_DONE_I_EVEN___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_8__RO_CAL_DONE_I_EVEN___S 7 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_8__RO_WCAL_FLAG_I_EVEN___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_8__RO_WCAL_FLAG_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_8___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_8___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_9 (0x005FA920) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_9___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_9__RO_WOS_C_I_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_9__RO_WOS_C_I_ODD___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_9__RO_WOS_C_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_9___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_9___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_10 (0x005FA924) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_10___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_10__RO_WOS_F_I_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_10__RO_WOS_F_I_ODD___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_10__RO_WOS_F_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_10___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_10___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_11 (0x005FA928) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_11___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_11__RO_W5_I_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_11__RO_W5_I_ODD___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_11__RO_W5_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_11___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_11___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_12 (0x005FA92C) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_12___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_12__RO_W6_I_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_12__RO_W6_I_ODD___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_12__RO_W6_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_12___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_12___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_13 (0x005FA930) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_13___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_13__RO_W7_I_ODD___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_13__RO_W7_I_ODD___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_13__RO_W7_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_13___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_13___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_14 (0x005FA934) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_14___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_14__RO_W8_I_ODD___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_14__RO_W8_I_ODD___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_14__RO_W8_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_14___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_14___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_15 (0x005FA938) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_15___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_15__RO_W9_I_ODD___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_15__RO_W9_I_ODD___M 0x00007FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_15__RO_W9_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_15___M 0x00007FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_15___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_16 (0x005FA93C) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_16___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_16___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_16__RO_CAL_DONE_I_ODD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_16__RO_WCAL_FLAG_I_ODD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_16__RO_CAL_DONE_I_ODD___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_16__RO_CAL_DONE_I_ODD___S 7 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_16__RO_WCAL_FLAG_I_ODD___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_16__RO_WCAL_FLAG_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_16___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_16___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_17 (0x005FA940) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_17___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_17___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_17__RO_WOS_C_Q_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_17__RO_WOS_C_Q_EVEN___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_17__RO_WOS_C_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_17___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_17___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_18 (0x005FA944) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_18___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_18___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_18__RO_WOS_F_Q_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_18__RO_WOS_F_Q_EVEN___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_18__RO_WOS_F_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_18___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_18___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_19 (0x005FA948) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_19___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_19___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_19__RO_W5_Q_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_19__RO_W5_Q_EVEN___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_19__RO_W5_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_19___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_19___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_20 (0x005FA94C) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_20___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_20___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_20__RO_W6_Q_EVEN___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_20__RO_W6_Q_EVEN___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_20__RO_W6_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_20___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_20___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_21 (0x005FA950) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_21___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_21___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_21__RO_W7_Q_EVEN___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_21__RO_W7_Q_EVEN___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_21__RO_W7_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_21___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_21___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_22 (0x005FA954) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_22___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_22___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_22__RO_W8_Q_EVEN___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_22__RO_W8_Q_EVEN___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_22__RO_W8_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_22___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_22___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_23 (0x005FA958) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_23___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_23___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_23__RO_W9_Q_EVEN___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_23__RO_W9_Q_EVEN___M 0x00007FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_23__RO_W9_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_23___M 0x00007FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_23___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_24 (0x005FA95C) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_24___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_24___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_24__RO_CAL_DONE_Q_EVEN___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_24__RO_WCAL_FLAG_Q_EVEN___POR 0x00 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_24__RO_CAL_DONE_Q_EVEN___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_24__RO_CAL_DONE_Q_EVEN___S 7 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_24__RO_WCAL_FLAG_Q_EVEN___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_24__RO_WCAL_FLAG_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_24___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_24___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_25 (0x005FA960) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_25___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_25___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_25__RO_WOS_C_Q_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_25__RO_WOS_C_Q_ODD___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_25__RO_WOS_C_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_25___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_25___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_26 (0x005FA964) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_26___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_26___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_26__RO_WOS_F_Q_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_26__RO_WOS_F_Q_ODD___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_26__RO_WOS_F_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_26___M 0x000003FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_26___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_27 (0x005FA968) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_27___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_27___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_27__RO_W5_Q_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_27__RO_W5_Q_ODD___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_27__RO_W5_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_27___M 0x000007FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_27___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_28 (0x005FA96C) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_28___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_28___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_28__RO_W6_Q_ODD___POR 0x000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_28__RO_W6_Q_ODD___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_28__RO_W6_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_28___M 0x00000FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_28___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_29 (0x005FA970) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_29___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_29___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_29__RO_W7_Q_ODD___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_29__RO_W7_Q_ODD___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_29__RO_W7_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_29___M 0x00001FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_29___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_30 (0x005FA974) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_30___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_30___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_30__RO_W8_Q_ODD___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_30__RO_W8_Q_ODD___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_30__RO_W8_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_30___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_30___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_31 (0x005FA978) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_31___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_31___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_31__RO_W9_Q_ODD___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_31__RO_W9_Q_ODD___M 0x00007FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_31__RO_W9_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_31___M 0x00007FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_31___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_32 (0x005FA97C) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_32___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_32___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_32__RO_CAL_DONE_Q_ODD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_32__RO_WCAL_FLAG_Q_ODD___POR 0x00 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_32__RO_CAL_DONE_Q_ODD___M 0x00000080 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_32__RO_CAL_DONE_Q_ODD___S 7 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_32__RO_WCAL_FLAG_Q_ODD___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_32__RO_WCAL_FLAG_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_32___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_32___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_33 (0x005FA980) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_33___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_33___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_33__RO_K_FACTOR_I_EVEN___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_33__RO_K_FACTOR_I_EVEN___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_33__RO_K_FACTOR_I_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_33___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_33___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_34 (0x005FA984) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_34___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_34___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_34__RO_K_FACTOR_I_ODD___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_34__RO_K_FACTOR_I_ODD___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_34__RO_K_FACTOR_I_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_34___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_34___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_35 (0x005FA988) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_35___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_35___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_35__RO_K_FACTOR_Q_EVEN___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_35__RO_K_FACTOR_Q_EVEN___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_35__RO_K_FACTOR_Q_EVEN___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_35___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_35___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_36 (0x005FA98C) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_36___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_36___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_36__RO_K_FACTOR_Q_ODD___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_36__RO_K_FACTOR_Q_ODD___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_36__RO_K_FACTOR_Q_ODD___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_36___M 0x00003FFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_POST_PROC_RO_REG_36___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_WOUT_REG (0x005FA990) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_WOUT_REG___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_WOUT_REG___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_WOUT_REG__RO_WOUT___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_WOUT_REG__RO_WOUT1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_WOUT_REG__RO_WOUT___M 0x00FFFF00 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_WOUT_REG__RO_WOUT___S 8 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_WOUT_REG__RO_WOUT1___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_WOUT_REG__RO_WOUT1___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_WOUT_REG___M 0x00FFFFFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_WOUT_REG___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_ADC_SPARE (0x005FA994) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_ADC_SPARE___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_ADC_SPARE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_ADC_SPARE__D_ADC_SPARE___POR 0x00 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_ADC_SPARE__D_ADC_SPARE___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_ADC_SPARE__D_ADC_SPARE___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_ADC_SPARE___M 0x000000FF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_ADC_SPARE___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_SPARE (0x005FA998) +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_SPARE___RWC QCSR_REG_RO +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_SPARE___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_SPARE__D_ADC_RO_SPARE___POR 0x0000 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_SPARE__D_ADC_RO_SPARE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_SPARE__D_ADC_RO_SPARE___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_SPARE___M 0x0000FFFF +#define PHYA_IRON2G_RFA_WL_ADC_POSTPROC_RO_CH1_RO_ADC_SPARE___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0 (0x005FA99C) +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKADC_EN_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKADC_FREQ_OV___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKADC_FREQ_OVD___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLK60_PHASE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKADC_CAL_FREQ___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKADC_PHASE___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__RXADC_CLK_SEL_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__PDADC_CLK_SEL_OVS___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKADC_EN_OVS___M 0xC0000000 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKADC_EN_OVS___S 30 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKADC_FREQ_OV___M 0x08000000 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKADC_FREQ_OV___S 27 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKADC_FREQ_OVD___M 0x07000000 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKADC_FREQ_OVD___S 24 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLK60_PHASE___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLK60_PHASE___S 12 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKADC_CAL_FREQ___M 0x00000300 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKADC_CAL_FREQ___S 8 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKADC_PHASE___M 0x00000070 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__CLKADC_PHASE___S 4 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__RXADC_CLK_SEL_OVS___M 0x0000000C +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__RXADC_CLK_SEL_OVS___S 2 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__PDADC_CLK_SEL_OVS___M 0x00000003 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0__PDADC_CLK_SEL_OVS___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0___M 0xCF00737F +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_0___S 0 + +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_1 (0x005FA9A0) +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_1__SAMPLED_ADC_EN_EXT_MUX_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_1__D_CLKADC_TEST_SEL___POR 0x0 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_1__SAMPLED_ADC_EN_EXT_MUX_SEL___M 0x0000000C +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_1__SAMPLED_ADC_EN_EXT_MUX_SEL___S 2 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_1__D_CLKADC_TEST_SEL___M 0x00000001 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_1__D_CLKADC_TEST_SEL___S 0 +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_1___M 0x0000000D +#define PHYA_IRON2G_RFA_WL_ADC_BBCLKGEN_CH1_BB_CLKGEN_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_0 (0x005FC000) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_0__RX_DCOC_RANGE_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_0__RX_DCOC_RES_I_0___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_0__RX_DCOC_RES_Q_0___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_0__RX_DCOC_RANGE_0___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_0__RX_DCOC_RANGE_0___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_0__RX_DCOC_RES_I_0___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_0__RX_DCOC_RES_I_0___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_0__RX_DCOC_RES_Q_0___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_0__RX_DCOC_RES_Q_0___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_0___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1 (0x005FC004) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1__RX_DCOC_RANGE_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1__RX_DCOC_RES_I_1___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1__RX_DCOC_RES_Q_1___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1__RX_DCOC_RANGE_1___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1__RX_DCOC_RANGE_1___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1__RX_DCOC_RES_I_1___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1__RX_DCOC_RES_I_1___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1__RX_DCOC_RES_Q_1___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1__RX_DCOC_RES_Q_1___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_2 (0x005FC008) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_2__RX_DCOC_RANGE_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_2__RX_DCOC_RES_I_2___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_2__RX_DCOC_RES_Q_2___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_2__RX_DCOC_RANGE_2___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_2__RX_DCOC_RANGE_2___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_2__RX_DCOC_RES_I_2___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_2__RX_DCOC_RES_I_2___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_2__RX_DCOC_RES_Q_2___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_2__RX_DCOC_RES_Q_2___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_2___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_2___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_3 (0x005FC00C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_3__RX_DCOC_RANGE_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_3__RX_DCOC_RES_I_3___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_3__RX_DCOC_RES_Q_3___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_3__RX_DCOC_RANGE_3___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_3__RX_DCOC_RANGE_3___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_3__RX_DCOC_RES_I_3___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_3__RX_DCOC_RES_I_3___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_3__RX_DCOC_RES_Q_3___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_3__RX_DCOC_RES_Q_3___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_3___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_3___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_4 (0x005FC010) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_4__RX_DCOC_RANGE_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_4__RX_DCOC_RES_I_4___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_4__RX_DCOC_RES_Q_4___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_4__RX_DCOC_RANGE_4___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_4__RX_DCOC_RANGE_4___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_4__RX_DCOC_RES_I_4___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_4__RX_DCOC_RES_I_4___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_4__RX_DCOC_RES_Q_4___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_4__RX_DCOC_RES_Q_4___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_4___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_4___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_5 (0x005FC014) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_5__RX_DCOC_RANGE_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_5__RX_DCOC_RES_I_5___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_5__RX_DCOC_RES_Q_5___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_5__RX_DCOC_RANGE_5___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_5__RX_DCOC_RANGE_5___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_5__RX_DCOC_RES_I_5___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_5__RX_DCOC_RES_I_5___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_5__RX_DCOC_RES_Q_5___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_5__RX_DCOC_RES_Q_5___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_5___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_5___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_6 (0x005FC018) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_6__RX_DCOC_RANGE_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_6__RX_DCOC_RES_I_6___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_6__RX_DCOC_RES_Q_6___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_6__RX_DCOC_RANGE_6___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_6__RX_DCOC_RANGE_6___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_6__RX_DCOC_RES_I_6___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_6__RX_DCOC_RES_I_6___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_6__RX_DCOC_RES_Q_6___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_6__RX_DCOC_RES_Q_6___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_6___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_6___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_7 (0x005FC01C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_7__RX_DCOC_RANGE_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_7__RX_DCOC_RES_I_7___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_7__RX_DCOC_RES_Q_7___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_7__RX_DCOC_RANGE_7___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_7__RX_DCOC_RANGE_7___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_7__RX_DCOC_RES_I_7___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_7__RX_DCOC_RES_I_7___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_7__RX_DCOC_RES_Q_7___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_7__RX_DCOC_RES_Q_7___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_7___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_7___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_8 (0x005FC020) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_8__RX_DCOC_RANGE_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_8__RX_DCOC_RES_I_8___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_8__RX_DCOC_RES_Q_8___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_8__RX_DCOC_RANGE_8___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_8__RX_DCOC_RANGE_8___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_8__RX_DCOC_RES_I_8___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_8__RX_DCOC_RES_I_8___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_8__RX_DCOC_RES_Q_8___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_8__RX_DCOC_RES_Q_8___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_8___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_8___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_9 (0x005FC024) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_9__RX_DCOC_RANGE_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_9__RX_DCOC_RES_I_9___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_9__RX_DCOC_RES_Q_9___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_9__RX_DCOC_RANGE_9___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_9__RX_DCOC_RANGE_9___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_9__RX_DCOC_RES_I_9___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_9__RX_DCOC_RES_I_9___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_9__RX_DCOC_RES_Q_9___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_9__RX_DCOC_RES_Q_9___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_9___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_9___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_10 (0x005FC028) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_10__RX_DCOC_RANGE_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_10__RX_DCOC_RES_I_10___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_10__RX_DCOC_RES_Q_10___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_10__RX_DCOC_RANGE_10___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_10__RX_DCOC_RANGE_10___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_10__RX_DCOC_RES_I_10___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_10__RX_DCOC_RES_I_10___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_10__RX_DCOC_RES_Q_10___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_10__RX_DCOC_RES_Q_10___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_10___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_10___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_11 (0x005FC02C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_11__RX_DCOC_RANGE_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_11__RX_DCOC_RES_I_11___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_11__RX_DCOC_RES_Q_11___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_11__RX_DCOC_RANGE_11___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_11__RX_DCOC_RANGE_11___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_11__RX_DCOC_RES_I_11___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_11__RX_DCOC_RES_I_11___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_11__RX_DCOC_RES_Q_11___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_11__RX_DCOC_RES_Q_11___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_11___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_11___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_12 (0x005FC030) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_12__RX_DCOC_RANGE_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_12__RX_DCOC_RES_I_12___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_12__RX_DCOC_RES_Q_12___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_12__RX_DCOC_RANGE_12___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_12__RX_DCOC_RANGE_12___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_12__RX_DCOC_RES_I_12___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_12__RX_DCOC_RES_I_12___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_12__RX_DCOC_RES_Q_12___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_12__RX_DCOC_RES_Q_12___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_12___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_12___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_13 (0x005FC034) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_13__RX_DCOC_RANGE_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_13__RX_DCOC_RES_I_13___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_13__RX_DCOC_RES_Q_13___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_13__RX_DCOC_RANGE_13___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_13__RX_DCOC_RANGE_13___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_13__RX_DCOC_RES_I_13___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_13__RX_DCOC_RES_I_13___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_13__RX_DCOC_RES_Q_13___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_13__RX_DCOC_RES_Q_13___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_13___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_13___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_14 (0x005FC038) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_14__RX_DCOC_RANGE_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_14__RX_DCOC_RES_I_14___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_14__RX_DCOC_RES_Q_14___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_14__RX_DCOC_RANGE_14___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_14__RX_DCOC_RANGE_14___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_14__RX_DCOC_RES_I_14___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_14__RX_DCOC_RES_I_14___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_14__RX_DCOC_RES_Q_14___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_14__RX_DCOC_RES_Q_14___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_14___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_14___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_15 (0x005FC03C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_15__RX_DCOC_RANGE_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_15__RX_DCOC_RES_I_15___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_15__RX_DCOC_RES_Q_15___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_15__RX_DCOC_RANGE_15___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_15__RX_DCOC_RANGE_15___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_15__RX_DCOC_RES_I_15___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_15__RX_DCOC_RES_I_15___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_15__RX_DCOC_RES_Q_15___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_15__RX_DCOC_RES_Q_15___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_15___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_15___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_16 (0x005FC040) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_16___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_16__RX_DCOC_RANGE_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_16__RX_DCOC_RES_I_16___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_16__RX_DCOC_RES_Q_16___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_16__RX_DCOC_RANGE_16___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_16__RX_DCOC_RANGE_16___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_16__RX_DCOC_RES_I_16___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_16__RX_DCOC_RES_I_16___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_16__RX_DCOC_RES_Q_16___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_16__RX_DCOC_RES_Q_16___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_16___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_16___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_17 (0x005FC044) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_17___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_17__RX_DCOC_RANGE_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_17__RX_DCOC_RES_I_17___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_17__RX_DCOC_RES_Q_17___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_17__RX_DCOC_RANGE_17___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_17__RX_DCOC_RANGE_17___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_17__RX_DCOC_RES_I_17___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_17__RX_DCOC_RES_I_17___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_17__RX_DCOC_RES_Q_17___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_17__RX_DCOC_RES_Q_17___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_17___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_17___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_18 (0x005FC048) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_18___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_18__RX_DCOC_RANGE_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_18__RX_DCOC_RES_I_18___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_18__RX_DCOC_RES_Q_18___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_18__RX_DCOC_RANGE_18___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_18__RX_DCOC_RANGE_18___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_18__RX_DCOC_RES_I_18___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_18__RX_DCOC_RES_I_18___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_18__RX_DCOC_RES_Q_18___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_18__RX_DCOC_RES_Q_18___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_18___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_18___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_19 (0x005FC04C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_19___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_19__RX_DCOC_RANGE_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_19__RX_DCOC_RES_I_19___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_19__RX_DCOC_RES_Q_19___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_19__RX_DCOC_RANGE_19___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_19__RX_DCOC_RANGE_19___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_19__RX_DCOC_RES_I_19___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_19__RX_DCOC_RES_I_19___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_19__RX_DCOC_RES_Q_19___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_19__RX_DCOC_RES_Q_19___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_19___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_19___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_20 (0x005FC050) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_20___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_20__RX_DCOC_RANGE_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_20__RX_DCOC_RES_I_20___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_20__RX_DCOC_RES_Q_20___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_20__RX_DCOC_RANGE_20___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_20__RX_DCOC_RANGE_20___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_20__RX_DCOC_RES_I_20___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_20__RX_DCOC_RES_I_20___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_20__RX_DCOC_RES_Q_20___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_20__RX_DCOC_RES_Q_20___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_20___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_20___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_21 (0x005FC054) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_21___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_21__RX_DCOC_RANGE_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_21__RX_DCOC_RES_I_21___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_21__RX_DCOC_RES_Q_21___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_21__RX_DCOC_RANGE_21___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_21__RX_DCOC_RANGE_21___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_21__RX_DCOC_RES_I_21___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_21__RX_DCOC_RES_I_21___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_21__RX_DCOC_RES_Q_21___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_21__RX_DCOC_RES_Q_21___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_21___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_21___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_22 (0x005FC058) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_22___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_22__RX_DCOC_RANGE_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_22__RX_DCOC_RES_I_22___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_22__RX_DCOC_RES_Q_22___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_22__RX_DCOC_RANGE_22___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_22__RX_DCOC_RANGE_22___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_22__RX_DCOC_RES_I_22___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_22__RX_DCOC_RES_I_22___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_22__RX_DCOC_RES_Q_22___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_22__RX_DCOC_RES_Q_22___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_22___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_22___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_23 (0x005FC05C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_23___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_23__RX_DCOC_RANGE_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_23__RX_DCOC_RES_I_23___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_23__RX_DCOC_RES_Q_23___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_23__RX_DCOC_RANGE_23___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_23__RX_DCOC_RANGE_23___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_23__RX_DCOC_RES_I_23___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_23__RX_DCOC_RES_I_23___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_23__RX_DCOC_RES_Q_23___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_23__RX_DCOC_RES_Q_23___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_23___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_23___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_24 (0x005FC060) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_24___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_24__RX_DCOC_RANGE_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_24__RX_DCOC_RES_I_24___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_24__RX_DCOC_RES_Q_24___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_24__RX_DCOC_RANGE_24___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_24__RX_DCOC_RANGE_24___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_24__RX_DCOC_RES_I_24___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_24__RX_DCOC_RES_I_24___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_24__RX_DCOC_RES_Q_24___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_24__RX_DCOC_RES_Q_24___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_24___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_24___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_25 (0x005FC064) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_25___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_25__RX_DCOC_RANGE_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_25__RX_DCOC_RES_I_25___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_25__RX_DCOC_RES_Q_25___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_25__RX_DCOC_RANGE_25___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_25__RX_DCOC_RANGE_25___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_25__RX_DCOC_RES_I_25___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_25__RX_DCOC_RES_I_25___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_25__RX_DCOC_RES_Q_25___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_25__RX_DCOC_RES_Q_25___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_25___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_25___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_26 (0x005FC068) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_26___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_26__RX_DCOC_RANGE_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_26__RX_DCOC_RES_I_26___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_26__RX_DCOC_RES_Q_26___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_26__RX_DCOC_RANGE_26___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_26__RX_DCOC_RANGE_26___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_26__RX_DCOC_RES_I_26___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_26__RX_DCOC_RES_I_26___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_26__RX_DCOC_RES_Q_26___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_26__RX_DCOC_RES_Q_26___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_26___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_26___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_27 (0x005FC06C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_27___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_27__RX_DCOC_RANGE_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_27__RX_DCOC_RES_I_27___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_27__RX_DCOC_RES_Q_27___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_27__RX_DCOC_RANGE_27___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_27__RX_DCOC_RANGE_27___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_27__RX_DCOC_RES_I_27___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_27__RX_DCOC_RES_I_27___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_27__RX_DCOC_RES_Q_27___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_27__RX_DCOC_RES_Q_27___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_27___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_27___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_28 (0x005FC070) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_28___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_28__RX_DCOC_RANGE_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_28__RX_DCOC_RES_I_28___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_28__RX_DCOC_RES_Q_28___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_28__RX_DCOC_RANGE_28___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_28__RX_DCOC_RANGE_28___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_28__RX_DCOC_RES_I_28___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_28__RX_DCOC_RES_I_28___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_28__RX_DCOC_RES_Q_28___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_28__RX_DCOC_RES_Q_28___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_28___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_28___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_29 (0x005FC074) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_29___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_29__RX_DCOC_RANGE_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_29__RX_DCOC_RES_I_29___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_29__RX_DCOC_RES_Q_29___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_29__RX_DCOC_RANGE_29___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_29__RX_DCOC_RANGE_29___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_29__RX_DCOC_RES_I_29___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_29__RX_DCOC_RES_I_29___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_29__RX_DCOC_RES_Q_29___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_29__RX_DCOC_RES_Q_29___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_29___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_29___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_30 (0x005FC078) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_30___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_30__RX_DCOC_RANGE_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_30__RX_DCOC_RES_I_30___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_30__RX_DCOC_RES_Q_30___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_30__RX_DCOC_RANGE_30___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_30__RX_DCOC_RANGE_30___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_30__RX_DCOC_RES_I_30___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_30__RX_DCOC_RES_I_30___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_30__RX_DCOC_RES_Q_30___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_30__RX_DCOC_RES_Q_30___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_30___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_30___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_31 (0x005FC07C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_31___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_31__RX_DCOC_RANGE_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_31__RX_DCOC_RES_I_31___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_31__RX_DCOC_RES_Q_31___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_31__RX_DCOC_RANGE_31___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_31__RX_DCOC_RANGE_31___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_31__RX_DCOC_RES_I_31___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_31__RX_DCOC_RES_I_31___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_31__RX_DCOC_RES_Q_31___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_31__RX_DCOC_RES_Q_31___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_31___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_31___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_32 (0x005FC080) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_32___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_32___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_32__RX_DCOC_RANGE_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_32__RX_DCOC_RES_I_32___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_32__RX_DCOC_RES_Q_32___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_32__RX_DCOC_RANGE_32___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_32__RX_DCOC_RANGE_32___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_32__RX_DCOC_RES_I_32___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_32__RX_DCOC_RES_I_32___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_32__RX_DCOC_RES_Q_32___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_32__RX_DCOC_RES_Q_32___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_32___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_32___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_33 (0x005FC084) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_33___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_33___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_33__RX_DCOC_RANGE_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_33__RX_DCOC_RES_I_33___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_33__RX_DCOC_RES_Q_33___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_33__RX_DCOC_RANGE_33___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_33__RX_DCOC_RANGE_33___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_33__RX_DCOC_RES_I_33___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_33__RX_DCOC_RES_I_33___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_33__RX_DCOC_RES_Q_33___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_33__RX_DCOC_RES_Q_33___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_33___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_33___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_34 (0x005FC088) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_34___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_34___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_34__RX_DCOC_RANGE_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_34__RX_DCOC_RES_I_34___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_34__RX_DCOC_RES_Q_34___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_34__RX_DCOC_RANGE_34___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_34__RX_DCOC_RANGE_34___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_34__RX_DCOC_RES_I_34___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_34__RX_DCOC_RES_I_34___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_34__RX_DCOC_RES_Q_34___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_34__RX_DCOC_RES_Q_34___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_34___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_34___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_35 (0x005FC08C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_35___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_35___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_35__RX_DCOC_RANGE_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_35__RX_DCOC_RES_I_35___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_35__RX_DCOC_RES_Q_35___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_35__RX_DCOC_RANGE_35___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_35__RX_DCOC_RANGE_35___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_35__RX_DCOC_RES_I_35___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_35__RX_DCOC_RES_I_35___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_35__RX_DCOC_RES_Q_35___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_35__RX_DCOC_RES_Q_35___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_35___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_35___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_36 (0x005FC090) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_36___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_36___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_36__RX_DCOC_RANGE_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_36__RX_DCOC_RES_I_36___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_36__RX_DCOC_RES_Q_36___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_36__RX_DCOC_RANGE_36___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_36__RX_DCOC_RANGE_36___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_36__RX_DCOC_RES_I_36___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_36__RX_DCOC_RES_I_36___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_36__RX_DCOC_RES_Q_36___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_36__RX_DCOC_RES_Q_36___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_36___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_36___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_37 (0x005FC094) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_37___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_37___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_37__RX_DCOC_RANGE_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_37__RX_DCOC_RES_I_37___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_37__RX_DCOC_RES_Q_37___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_37__RX_DCOC_RANGE_37___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_37__RX_DCOC_RANGE_37___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_37__RX_DCOC_RES_I_37___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_37__RX_DCOC_RES_I_37___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_37__RX_DCOC_RES_Q_37___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_37__RX_DCOC_RES_Q_37___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_37___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_37___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_38 (0x005FC098) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_38___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_38___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_38__RX_DCOC_RANGE_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_38__RX_DCOC_RES_I_38___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_38__RX_DCOC_RES_Q_38___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_38__RX_DCOC_RANGE_38___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_38__RX_DCOC_RANGE_38___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_38__RX_DCOC_RES_I_38___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_38__RX_DCOC_RES_I_38___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_38__RX_DCOC_RES_Q_38___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_38__RX_DCOC_RES_Q_38___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_38___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_38___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_39 (0x005FC09C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_39___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_39___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_39__RX_DCOC_RANGE_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_39__RX_DCOC_RES_I_39___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_39__RX_DCOC_RES_Q_39___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_39__RX_DCOC_RANGE_39___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_39__RX_DCOC_RANGE_39___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_39__RX_DCOC_RES_I_39___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_39__RX_DCOC_RES_I_39___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_39__RX_DCOC_RES_Q_39___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_39__RX_DCOC_RES_Q_39___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_39___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_39___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_40 (0x005FC0A0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_40___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_40___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_40__RX_DCOC_RANGE_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_40__RX_DCOC_RES_I_40___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_40__RX_DCOC_RES_Q_40___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_40__RX_DCOC_RANGE_40___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_40__RX_DCOC_RANGE_40___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_40__RX_DCOC_RES_I_40___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_40__RX_DCOC_RES_I_40___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_40__RX_DCOC_RES_Q_40___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_40__RX_DCOC_RES_Q_40___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_40___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_40___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_41 (0x005FC0A4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_41___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_41___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_41__RX_DCOC_RANGE_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_41__RX_DCOC_RES_I_41___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_41__RX_DCOC_RES_Q_41___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_41__RX_DCOC_RANGE_41___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_41__RX_DCOC_RANGE_41___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_41__RX_DCOC_RES_I_41___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_41__RX_DCOC_RES_I_41___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_41__RX_DCOC_RES_Q_41___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_41__RX_DCOC_RES_Q_41___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_41___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_41___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_42 (0x005FC0A8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_42___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_42___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_42__RX_DCOC_RANGE_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_42__RX_DCOC_RES_I_42___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_42__RX_DCOC_RES_Q_42___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_42__RX_DCOC_RANGE_42___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_42__RX_DCOC_RANGE_42___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_42__RX_DCOC_RES_I_42___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_42__RX_DCOC_RES_I_42___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_42__RX_DCOC_RES_Q_42___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_42__RX_DCOC_RES_Q_42___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_42___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_42___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_43 (0x005FC0AC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_43___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_43___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_43__RX_DCOC_RANGE_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_43__RX_DCOC_RES_I_43___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_43__RX_DCOC_RES_Q_43___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_43__RX_DCOC_RANGE_43___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_43__RX_DCOC_RANGE_43___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_43__RX_DCOC_RES_I_43___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_43__RX_DCOC_RES_I_43___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_43__RX_DCOC_RES_Q_43___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_43__RX_DCOC_RES_Q_43___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_43___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_43___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_44 (0x005FC0B0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_44___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_44___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_44__RX_DCOC_RANGE_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_44__RX_DCOC_RES_I_44___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_44__RX_DCOC_RES_Q_44___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_44__RX_DCOC_RANGE_44___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_44__RX_DCOC_RANGE_44___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_44__RX_DCOC_RES_I_44___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_44__RX_DCOC_RES_I_44___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_44__RX_DCOC_RES_Q_44___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_44__RX_DCOC_RES_Q_44___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_44___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_44___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_45 (0x005FC0B4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_45___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_45___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_45__RX_DCOC_RANGE_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_45__RX_DCOC_RES_I_45___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_45__RX_DCOC_RES_Q_45___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_45__RX_DCOC_RANGE_45___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_45__RX_DCOC_RANGE_45___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_45__RX_DCOC_RES_I_45___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_45__RX_DCOC_RES_I_45___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_45__RX_DCOC_RES_Q_45___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_45__RX_DCOC_RES_Q_45___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_45___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_45___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_46 (0x005FC0B8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_46___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_46___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_46__RX_DCOC_RANGE_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_46__RX_DCOC_RES_I_46___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_46__RX_DCOC_RES_Q_46___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_46__RX_DCOC_RANGE_46___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_46__RX_DCOC_RANGE_46___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_46__RX_DCOC_RES_I_46___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_46__RX_DCOC_RES_I_46___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_46__RX_DCOC_RES_Q_46___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_46__RX_DCOC_RES_Q_46___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_46___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_46___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_47 (0x005FC0BC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_47___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_47___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_47__RX_DCOC_RANGE_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_47__RX_DCOC_RES_I_47___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_47__RX_DCOC_RES_Q_47___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_47__RX_DCOC_RANGE_47___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_47__RX_DCOC_RANGE_47___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_47__RX_DCOC_RES_I_47___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_47__RX_DCOC_RES_I_47___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_47__RX_DCOC_RES_Q_47___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_47__RX_DCOC_RES_Q_47___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_47___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_47___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_48 (0x005FC0C0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_48___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_48___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_48__RX_DCOC_RANGE_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_48__RX_DCOC_RES_I_48___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_48__RX_DCOC_RES_Q_48___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_48__RX_DCOC_RANGE_48___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_48__RX_DCOC_RANGE_48___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_48__RX_DCOC_RES_I_48___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_48__RX_DCOC_RES_I_48___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_48__RX_DCOC_RES_Q_48___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_48__RX_DCOC_RES_Q_48___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_48___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_48___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_49 (0x005FC0C4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_49___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_49___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_49__RX_DCOC_RANGE_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_49__RX_DCOC_RES_I_49___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_49__RX_DCOC_RES_Q_49___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_49__RX_DCOC_RANGE_49___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_49__RX_DCOC_RANGE_49___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_49__RX_DCOC_RES_I_49___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_49__RX_DCOC_RES_I_49___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_49__RX_DCOC_RES_Q_49___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_49__RX_DCOC_RES_Q_49___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_49___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_49___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_50 (0x005FC0C8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_50___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_50___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_50__RX_DCOC_RANGE_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_50__RX_DCOC_RES_I_50___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_50__RX_DCOC_RES_Q_50___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_50__RX_DCOC_RANGE_50___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_50__RX_DCOC_RANGE_50___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_50__RX_DCOC_RES_I_50___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_50__RX_DCOC_RES_I_50___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_50__RX_DCOC_RES_Q_50___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_50__RX_DCOC_RES_Q_50___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_50___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_50___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_51 (0x005FC0CC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_51___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_51___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_51__RX_DCOC_RANGE_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_51__RX_DCOC_RES_I_51___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_51__RX_DCOC_RES_Q_51___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_51__RX_DCOC_RANGE_51___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_51__RX_DCOC_RANGE_51___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_51__RX_DCOC_RES_I_51___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_51__RX_DCOC_RES_I_51___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_51__RX_DCOC_RES_Q_51___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_51__RX_DCOC_RES_Q_51___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_51___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_51___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_52 (0x005FC0D0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_52___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_52___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_52__RX_DCOC_RANGE_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_52__RX_DCOC_RES_I_52___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_52__RX_DCOC_RES_Q_52___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_52__RX_DCOC_RANGE_52___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_52__RX_DCOC_RANGE_52___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_52__RX_DCOC_RES_I_52___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_52__RX_DCOC_RES_I_52___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_52__RX_DCOC_RES_Q_52___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_52__RX_DCOC_RES_Q_52___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_52___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_52___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_53 (0x005FC0D4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_53___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_53___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_53__RX_DCOC_RANGE_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_53__RX_DCOC_RES_I_53___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_53__RX_DCOC_RES_Q_53___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_53__RX_DCOC_RANGE_53___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_53__RX_DCOC_RANGE_53___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_53__RX_DCOC_RES_I_53___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_53__RX_DCOC_RES_I_53___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_53__RX_DCOC_RES_Q_53___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_53__RX_DCOC_RES_Q_53___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_53___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_53___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_54 (0x005FC0D8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_54___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_54___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_54__RX_DCOC_RANGE_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_54__RX_DCOC_RES_I_54___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_54__RX_DCOC_RES_Q_54___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_54__RX_DCOC_RANGE_54___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_54__RX_DCOC_RANGE_54___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_54__RX_DCOC_RES_I_54___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_54__RX_DCOC_RES_I_54___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_54__RX_DCOC_RES_Q_54___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_54__RX_DCOC_RES_Q_54___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_54___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_54___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_55 (0x005FC0DC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_55___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_55___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_55__RX_DCOC_RANGE_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_55__RX_DCOC_RES_I_55___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_55__RX_DCOC_RES_Q_55___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_55__RX_DCOC_RANGE_55___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_55__RX_DCOC_RANGE_55___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_55__RX_DCOC_RES_I_55___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_55__RX_DCOC_RES_I_55___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_55__RX_DCOC_RES_Q_55___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_55__RX_DCOC_RES_Q_55___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_55___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_55___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_56 (0x005FC0E0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_56___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_56___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_56__RX_DCOC_RANGE_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_56__RX_DCOC_RES_I_56___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_56__RX_DCOC_RES_Q_56___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_56__RX_DCOC_RANGE_56___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_56__RX_DCOC_RANGE_56___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_56__RX_DCOC_RES_I_56___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_56__RX_DCOC_RES_I_56___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_56__RX_DCOC_RES_Q_56___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_56__RX_DCOC_RES_Q_56___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_56___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_56___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_57 (0x005FC0E4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_57___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_57___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_57__RX_DCOC_RANGE_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_57__RX_DCOC_RES_I_57___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_57__RX_DCOC_RES_Q_57___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_57__RX_DCOC_RANGE_57___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_57__RX_DCOC_RANGE_57___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_57__RX_DCOC_RES_I_57___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_57__RX_DCOC_RES_I_57___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_57__RX_DCOC_RES_Q_57___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_57__RX_DCOC_RES_Q_57___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_57___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_57___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_58 (0x005FC0E8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_58___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_58___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_58__RX_DCOC_RANGE_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_58__RX_DCOC_RES_I_58___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_58__RX_DCOC_RES_Q_58___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_58__RX_DCOC_RANGE_58___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_58__RX_DCOC_RANGE_58___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_58__RX_DCOC_RES_I_58___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_58__RX_DCOC_RES_I_58___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_58__RX_DCOC_RES_Q_58___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_58__RX_DCOC_RES_Q_58___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_58___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_58___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_59 (0x005FC0EC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_59___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_59___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_59__RX_DCOC_RANGE_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_59__RX_DCOC_RES_I_59___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_59__RX_DCOC_RES_Q_59___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_59__RX_DCOC_RANGE_59___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_59__RX_DCOC_RANGE_59___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_59__RX_DCOC_RES_I_59___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_59__RX_DCOC_RES_I_59___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_59__RX_DCOC_RES_Q_59___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_59__RX_DCOC_RES_Q_59___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_59___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_59___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_60 (0x005FC0F0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_60___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_60___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_60__RX_DCOC_RANGE_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_60__RX_DCOC_RES_I_60___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_60__RX_DCOC_RES_Q_60___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_60__RX_DCOC_RANGE_60___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_60__RX_DCOC_RANGE_60___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_60__RX_DCOC_RES_I_60___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_60__RX_DCOC_RES_I_60___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_60__RX_DCOC_RES_Q_60___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_60__RX_DCOC_RES_Q_60___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_60___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_60___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_61 (0x005FC0F4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_61___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_61___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_61__RX_DCOC_RANGE_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_61__RX_DCOC_RES_I_61___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_61__RX_DCOC_RES_Q_61___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_61__RX_DCOC_RANGE_61___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_61__RX_DCOC_RANGE_61___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_61__RX_DCOC_RES_I_61___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_61__RX_DCOC_RES_I_61___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_61__RX_DCOC_RES_Q_61___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_61__RX_DCOC_RES_Q_61___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_61___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_61___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_62 (0x005FC0F8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_62___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_62___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_62__RX_DCOC_RANGE_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_62__RX_DCOC_RES_I_62___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_62__RX_DCOC_RES_Q_62___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_62__RX_DCOC_RANGE_62___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_62__RX_DCOC_RANGE_62___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_62__RX_DCOC_RES_I_62___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_62__RX_DCOC_RES_I_62___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_62__RX_DCOC_RES_Q_62___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_62__RX_DCOC_RES_Q_62___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_62___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_62___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_63 (0x005FC0FC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_63___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_63___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_63__RX_DCOC_RANGE_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_63__RX_DCOC_RES_I_63___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_63__RX_DCOC_RES_Q_63___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_63__RX_DCOC_RANGE_63___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_63__RX_DCOC_RANGE_63___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_63__RX_DCOC_RES_I_63___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_63__RX_DCOC_RES_I_63___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_63__RX_DCOC_RES_Q_63___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_63__RX_DCOC_RES_Q_63___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_63___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_63___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_64 (0x005FC100) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_64___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_64___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_64__RX_DCOC_RANGE_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_64__RX_DCOC_RES_I_64___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_64__RX_DCOC_RES_Q_64___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_64__RX_DCOC_RANGE_64___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_64__RX_DCOC_RANGE_64___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_64__RX_DCOC_RES_I_64___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_64__RX_DCOC_RES_I_64___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_64__RX_DCOC_RES_Q_64___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_64__RX_DCOC_RES_Q_64___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_64___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_64___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_65 (0x005FC104) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_65___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_65___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_65__RX_DCOC_RANGE_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_65__RX_DCOC_RES_I_65___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_65__RX_DCOC_RES_Q_65___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_65__RX_DCOC_RANGE_65___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_65__RX_DCOC_RANGE_65___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_65__RX_DCOC_RES_I_65___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_65__RX_DCOC_RES_I_65___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_65__RX_DCOC_RES_Q_65___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_65__RX_DCOC_RES_Q_65___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_65___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_65___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_66 (0x005FC108) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_66___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_66___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_66__RX_DCOC_RANGE_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_66__RX_DCOC_RES_I_66___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_66__RX_DCOC_RES_Q_66___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_66__RX_DCOC_RANGE_66___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_66__RX_DCOC_RANGE_66___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_66__RX_DCOC_RES_I_66___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_66__RX_DCOC_RES_I_66___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_66__RX_DCOC_RES_Q_66___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_66__RX_DCOC_RES_Q_66___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_66___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_66___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_67 (0x005FC10C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_67___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_67___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_67__RX_DCOC_RANGE_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_67__RX_DCOC_RES_I_67___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_67__RX_DCOC_RES_Q_67___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_67__RX_DCOC_RANGE_67___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_67__RX_DCOC_RANGE_67___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_67__RX_DCOC_RES_I_67___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_67__RX_DCOC_RES_I_67___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_67__RX_DCOC_RES_Q_67___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_67__RX_DCOC_RES_Q_67___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_67___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_67___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_68 (0x005FC110) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_68___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_68___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_68__RX_DCOC_RANGE_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_68__RX_DCOC_RES_I_68___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_68__RX_DCOC_RES_Q_68___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_68__RX_DCOC_RANGE_68___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_68__RX_DCOC_RANGE_68___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_68__RX_DCOC_RES_I_68___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_68__RX_DCOC_RES_I_68___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_68__RX_DCOC_RES_Q_68___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_68__RX_DCOC_RES_Q_68___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_68___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_68___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_69 (0x005FC114) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_69___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_69___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_69__RX_DCOC_RANGE_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_69__RX_DCOC_RES_I_69___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_69__RX_DCOC_RES_Q_69___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_69__RX_DCOC_RANGE_69___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_69__RX_DCOC_RANGE_69___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_69__RX_DCOC_RES_I_69___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_69__RX_DCOC_RES_I_69___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_69__RX_DCOC_RES_Q_69___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_69__RX_DCOC_RES_Q_69___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_69___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_69___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_70 (0x005FC118) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_70___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_70___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_70__RX_DCOC_RANGE_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_70__RX_DCOC_RES_I_70___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_70__RX_DCOC_RES_Q_70___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_70__RX_DCOC_RANGE_70___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_70__RX_DCOC_RANGE_70___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_70__RX_DCOC_RES_I_70___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_70__RX_DCOC_RES_I_70___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_70__RX_DCOC_RES_Q_70___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_70__RX_DCOC_RES_Q_70___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_70___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_70___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_71 (0x005FC11C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_71___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_71___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_71__RX_DCOC_RANGE_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_71__RX_DCOC_RES_I_71___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_71__RX_DCOC_RES_Q_71___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_71__RX_DCOC_RANGE_71___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_71__RX_DCOC_RANGE_71___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_71__RX_DCOC_RES_I_71___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_71__RX_DCOC_RES_I_71___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_71__RX_DCOC_RES_Q_71___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_71__RX_DCOC_RES_Q_71___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_71___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_71___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_72 (0x005FC120) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_72___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_72___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_72__RX_DCOC_RANGE_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_72__RX_DCOC_RES_I_72___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_72__RX_DCOC_RES_Q_72___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_72__RX_DCOC_RANGE_72___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_72__RX_DCOC_RANGE_72___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_72__RX_DCOC_RES_I_72___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_72__RX_DCOC_RES_I_72___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_72__RX_DCOC_RES_Q_72___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_72__RX_DCOC_RES_Q_72___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_72___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_72___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_73 (0x005FC124) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_73___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_73___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_73__RX_DCOC_RANGE_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_73__RX_DCOC_RES_I_73___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_73__RX_DCOC_RES_Q_73___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_73__RX_DCOC_RANGE_73___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_73__RX_DCOC_RANGE_73___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_73__RX_DCOC_RES_I_73___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_73__RX_DCOC_RES_I_73___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_73__RX_DCOC_RES_Q_73___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_73__RX_DCOC_RES_Q_73___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_73___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_73___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_74 (0x005FC128) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_74___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_74___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_74__RX_DCOC_RANGE_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_74__RX_DCOC_RES_I_74___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_74__RX_DCOC_RES_Q_74___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_74__RX_DCOC_RANGE_74___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_74__RX_DCOC_RANGE_74___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_74__RX_DCOC_RES_I_74___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_74__RX_DCOC_RES_I_74___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_74__RX_DCOC_RES_Q_74___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_74__RX_DCOC_RES_Q_74___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_74___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_74___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_75 (0x005FC12C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_75___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_75___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_75__RX_DCOC_RANGE_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_75__RX_DCOC_RES_I_75___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_75__RX_DCOC_RES_Q_75___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_75__RX_DCOC_RANGE_75___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_75__RX_DCOC_RANGE_75___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_75__RX_DCOC_RES_I_75___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_75__RX_DCOC_RES_I_75___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_75__RX_DCOC_RES_Q_75___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_75__RX_DCOC_RES_Q_75___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_75___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_75___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_76 (0x005FC130) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_76___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_76___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_76__RX_DCOC_RANGE_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_76__RX_DCOC_RES_I_76___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_76__RX_DCOC_RES_Q_76___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_76__RX_DCOC_RANGE_76___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_76__RX_DCOC_RANGE_76___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_76__RX_DCOC_RES_I_76___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_76__RX_DCOC_RES_I_76___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_76__RX_DCOC_RES_Q_76___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_76__RX_DCOC_RES_Q_76___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_76___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_76___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_77 (0x005FC134) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_77___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_77___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_77__RX_DCOC_RANGE_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_77__RX_DCOC_RES_I_77___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_77__RX_DCOC_RES_Q_77___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_77__RX_DCOC_RANGE_77___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_77__RX_DCOC_RANGE_77___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_77__RX_DCOC_RES_I_77___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_77__RX_DCOC_RES_I_77___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_77__RX_DCOC_RES_Q_77___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_77__RX_DCOC_RES_Q_77___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_77___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_77___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_78 (0x005FC138) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_78___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_78___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_78__RX_DCOC_RANGE_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_78__RX_DCOC_RES_I_78___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_78__RX_DCOC_RES_Q_78___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_78__RX_DCOC_RANGE_78___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_78__RX_DCOC_RANGE_78___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_78__RX_DCOC_RES_I_78___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_78__RX_DCOC_RES_I_78___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_78__RX_DCOC_RES_Q_78___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_78__RX_DCOC_RES_Q_78___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_78___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_78___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_79 (0x005FC13C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_79___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_79___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_79__RX_DCOC_RANGE_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_79__RX_DCOC_RES_I_79___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_79__RX_DCOC_RES_Q_79___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_79__RX_DCOC_RANGE_79___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_79__RX_DCOC_RANGE_79___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_79__RX_DCOC_RES_I_79___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_79__RX_DCOC_RES_I_79___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_79__RX_DCOC_RES_Q_79___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_79__RX_DCOC_RES_Q_79___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_79___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_79___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_80 (0x005FC140) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_80___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_80___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_80__RX_DCOC_RANGE_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_80__RX_DCOC_RES_I_80___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_80__RX_DCOC_RES_Q_80___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_80__RX_DCOC_RANGE_80___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_80__RX_DCOC_RANGE_80___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_80__RX_DCOC_RES_I_80___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_80__RX_DCOC_RES_I_80___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_80__RX_DCOC_RES_Q_80___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_80__RX_DCOC_RES_Q_80___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_80___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_80___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_81 (0x005FC144) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_81___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_81___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_81__RX_DCOC_RANGE_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_81__RX_DCOC_RES_I_81___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_81__RX_DCOC_RES_Q_81___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_81__RX_DCOC_RANGE_81___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_81__RX_DCOC_RANGE_81___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_81__RX_DCOC_RES_I_81___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_81__RX_DCOC_RES_I_81___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_81__RX_DCOC_RES_Q_81___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_81__RX_DCOC_RES_Q_81___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_81___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_81___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_82 (0x005FC148) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_82___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_82___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_82__RX_DCOC_RANGE_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_82__RX_DCOC_RES_I_82___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_82__RX_DCOC_RES_Q_82___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_82__RX_DCOC_RANGE_82___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_82__RX_DCOC_RANGE_82___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_82__RX_DCOC_RES_I_82___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_82__RX_DCOC_RES_I_82___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_82__RX_DCOC_RES_Q_82___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_82__RX_DCOC_RES_Q_82___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_82___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_82___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_83 (0x005FC14C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_83___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_83___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_83__RX_DCOC_RANGE_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_83__RX_DCOC_RES_I_83___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_83__RX_DCOC_RES_Q_83___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_83__RX_DCOC_RANGE_83___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_83__RX_DCOC_RANGE_83___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_83__RX_DCOC_RES_I_83___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_83__RX_DCOC_RES_I_83___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_83__RX_DCOC_RES_Q_83___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_83__RX_DCOC_RES_Q_83___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_83___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_83___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_84 (0x005FC150) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_84___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_84___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_84__RX_DCOC_RANGE_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_84__RX_DCOC_RES_I_84___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_84__RX_DCOC_RES_Q_84___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_84__RX_DCOC_RANGE_84___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_84__RX_DCOC_RANGE_84___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_84__RX_DCOC_RES_I_84___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_84__RX_DCOC_RES_I_84___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_84__RX_DCOC_RES_Q_84___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_84__RX_DCOC_RES_Q_84___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_84___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_84___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_85 (0x005FC154) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_85___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_85___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_85__RX_DCOC_RANGE_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_85__RX_DCOC_RES_I_85___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_85__RX_DCOC_RES_Q_85___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_85__RX_DCOC_RANGE_85___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_85__RX_DCOC_RANGE_85___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_85__RX_DCOC_RES_I_85___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_85__RX_DCOC_RES_I_85___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_85__RX_DCOC_RES_Q_85___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_85__RX_DCOC_RES_Q_85___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_85___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_85___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_86 (0x005FC158) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_86___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_86___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_86__RX_DCOC_RANGE_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_86__RX_DCOC_RES_I_86___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_86__RX_DCOC_RES_Q_86___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_86__RX_DCOC_RANGE_86___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_86__RX_DCOC_RANGE_86___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_86__RX_DCOC_RES_I_86___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_86__RX_DCOC_RES_I_86___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_86__RX_DCOC_RES_Q_86___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_86__RX_DCOC_RES_Q_86___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_86___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_86___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_87 (0x005FC15C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_87___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_87___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_87__RX_DCOC_RANGE_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_87__RX_DCOC_RES_I_87___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_87__RX_DCOC_RES_Q_87___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_87__RX_DCOC_RANGE_87___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_87__RX_DCOC_RANGE_87___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_87__RX_DCOC_RES_I_87___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_87__RX_DCOC_RES_I_87___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_87__RX_DCOC_RES_Q_87___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_87__RX_DCOC_RES_Q_87___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_87___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_87___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_88 (0x005FC160) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_88___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_88___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_88__RX_DCOC_RANGE_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_88__RX_DCOC_RES_I_88___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_88__RX_DCOC_RES_Q_88___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_88__RX_DCOC_RANGE_88___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_88__RX_DCOC_RANGE_88___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_88__RX_DCOC_RES_I_88___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_88__RX_DCOC_RES_I_88___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_88__RX_DCOC_RES_Q_88___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_88__RX_DCOC_RES_Q_88___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_88___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_88___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_89 (0x005FC164) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_89___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_89___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_89__RX_DCOC_RANGE_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_89__RX_DCOC_RES_I_89___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_89__RX_DCOC_RES_Q_89___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_89__RX_DCOC_RANGE_89___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_89__RX_DCOC_RANGE_89___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_89__RX_DCOC_RES_I_89___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_89__RX_DCOC_RES_I_89___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_89__RX_DCOC_RES_Q_89___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_89__RX_DCOC_RES_Q_89___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_89___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_89___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_90 (0x005FC168) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_90___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_90___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_90__RX_DCOC_RANGE_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_90__RX_DCOC_RES_I_90___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_90__RX_DCOC_RES_Q_90___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_90__RX_DCOC_RANGE_90___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_90__RX_DCOC_RANGE_90___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_90__RX_DCOC_RES_I_90___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_90__RX_DCOC_RES_I_90___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_90__RX_DCOC_RES_Q_90___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_90__RX_DCOC_RES_Q_90___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_90___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_90___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_91 (0x005FC16C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_91___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_91___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_91__RX_DCOC_RANGE_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_91__RX_DCOC_RES_I_91___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_91__RX_DCOC_RES_Q_91___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_91__RX_DCOC_RANGE_91___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_91__RX_DCOC_RANGE_91___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_91__RX_DCOC_RES_I_91___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_91__RX_DCOC_RES_I_91___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_91__RX_DCOC_RES_Q_91___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_91__RX_DCOC_RES_Q_91___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_91___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_91___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_92 (0x005FC170) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_92___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_92___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_92__RX_DCOC_RANGE_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_92__RX_DCOC_RES_I_92___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_92__RX_DCOC_RES_Q_92___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_92__RX_DCOC_RANGE_92___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_92__RX_DCOC_RANGE_92___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_92__RX_DCOC_RES_I_92___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_92__RX_DCOC_RES_I_92___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_92__RX_DCOC_RES_Q_92___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_92__RX_DCOC_RES_Q_92___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_92___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_92___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_93 (0x005FC174) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_93___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_93___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_93__RX_DCOC_RANGE_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_93__RX_DCOC_RES_I_93___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_93__RX_DCOC_RES_Q_93___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_93__RX_DCOC_RANGE_93___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_93__RX_DCOC_RANGE_93___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_93__RX_DCOC_RES_I_93___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_93__RX_DCOC_RES_I_93___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_93__RX_DCOC_RES_Q_93___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_93__RX_DCOC_RES_Q_93___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_93___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_93___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_94 (0x005FC178) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_94___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_94___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_94__RX_DCOC_RANGE_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_94__RX_DCOC_RES_I_94___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_94__RX_DCOC_RES_Q_94___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_94__RX_DCOC_RANGE_94___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_94__RX_DCOC_RANGE_94___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_94__RX_DCOC_RES_I_94___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_94__RX_DCOC_RES_I_94___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_94__RX_DCOC_RES_Q_94___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_94__RX_DCOC_RES_Q_94___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_94___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_94___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_95 (0x005FC17C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_95___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_95___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_95__RX_DCOC_RANGE_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_95__RX_DCOC_RES_I_95___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_95__RX_DCOC_RES_Q_95___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_95__RX_DCOC_RANGE_95___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_95__RX_DCOC_RANGE_95___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_95__RX_DCOC_RES_I_95___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_95__RX_DCOC_RES_I_95___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_95__RX_DCOC_RES_Q_95___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_95__RX_DCOC_RES_Q_95___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_95___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_95___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_96 (0x005FC180) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_96___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_96___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_96__RX_DCOC_RANGE_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_96__RX_DCOC_RES_I_96___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_96__RX_DCOC_RES_Q_96___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_96__RX_DCOC_RANGE_96___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_96__RX_DCOC_RANGE_96___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_96__RX_DCOC_RES_I_96___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_96__RX_DCOC_RES_I_96___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_96__RX_DCOC_RES_Q_96___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_96__RX_DCOC_RES_Q_96___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_96___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_96___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_97 (0x005FC184) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_97___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_97___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_97__RX_DCOC_RANGE_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_97__RX_DCOC_RES_I_97___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_97__RX_DCOC_RES_Q_97___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_97__RX_DCOC_RANGE_97___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_97__RX_DCOC_RANGE_97___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_97__RX_DCOC_RES_I_97___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_97__RX_DCOC_RES_I_97___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_97__RX_DCOC_RES_Q_97___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_97__RX_DCOC_RES_Q_97___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_97___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_97___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_98 (0x005FC188) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_98___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_98___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_98__RX_DCOC_RANGE_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_98__RX_DCOC_RES_I_98___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_98__RX_DCOC_RES_Q_98___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_98__RX_DCOC_RANGE_98___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_98__RX_DCOC_RANGE_98___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_98__RX_DCOC_RES_I_98___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_98__RX_DCOC_RES_I_98___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_98__RX_DCOC_RES_Q_98___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_98__RX_DCOC_RES_Q_98___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_98___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_98___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_99 (0x005FC18C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_99___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_99___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_99__RX_DCOC_RANGE_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_99__RX_DCOC_RES_I_99___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_99__RX_DCOC_RES_Q_99___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_99__RX_DCOC_RANGE_99___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_99__RX_DCOC_RANGE_99___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_99__RX_DCOC_RES_I_99___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_99__RX_DCOC_RES_I_99___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_99__RX_DCOC_RES_Q_99___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_99__RX_DCOC_RES_Q_99___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_99___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_99___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_100 (0x005FC190) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_100___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_100___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_100__RX_DCOC_RANGE_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_100__RX_DCOC_RES_I_100___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_100__RX_DCOC_RES_Q_100___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_100__RX_DCOC_RANGE_100___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_100__RX_DCOC_RANGE_100___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_100__RX_DCOC_RES_I_100___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_100__RX_DCOC_RES_I_100___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_100__RX_DCOC_RES_Q_100___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_100__RX_DCOC_RES_Q_100___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_100___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_100___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_101 (0x005FC194) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_101___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_101___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_101__RX_DCOC_RANGE_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_101__RX_DCOC_RES_I_101___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_101__RX_DCOC_RES_Q_101___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_101__RX_DCOC_RANGE_101___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_101__RX_DCOC_RANGE_101___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_101__RX_DCOC_RES_I_101___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_101__RX_DCOC_RES_I_101___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_101__RX_DCOC_RES_Q_101___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_101__RX_DCOC_RES_Q_101___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_101___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_101___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_102 (0x005FC198) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_102___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_102___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_102__RX_DCOC_RANGE_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_102__RX_DCOC_RES_I_102___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_102__RX_DCOC_RES_Q_102___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_102__RX_DCOC_RANGE_102___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_102__RX_DCOC_RANGE_102___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_102__RX_DCOC_RES_I_102___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_102__RX_DCOC_RES_I_102___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_102__RX_DCOC_RES_Q_102___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_102__RX_DCOC_RES_Q_102___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_102___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_102___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_103 (0x005FC19C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_103___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_103___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_103__RX_DCOC_RANGE_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_103__RX_DCOC_RES_I_103___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_103__RX_DCOC_RES_Q_103___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_103__RX_DCOC_RANGE_103___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_103__RX_DCOC_RANGE_103___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_103__RX_DCOC_RES_I_103___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_103__RX_DCOC_RES_I_103___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_103__RX_DCOC_RES_Q_103___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_103__RX_DCOC_RES_Q_103___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_103___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_103___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_104 (0x005FC1A0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_104___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_104___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_104__RX_DCOC_RANGE_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_104__RX_DCOC_RES_I_104___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_104__RX_DCOC_RES_Q_104___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_104__RX_DCOC_RANGE_104___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_104__RX_DCOC_RANGE_104___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_104__RX_DCOC_RES_I_104___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_104__RX_DCOC_RES_I_104___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_104__RX_DCOC_RES_Q_104___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_104__RX_DCOC_RES_Q_104___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_104___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_104___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_105 (0x005FC1A4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_105___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_105___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_105__RX_DCOC_RANGE_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_105__RX_DCOC_RES_I_105___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_105__RX_DCOC_RES_Q_105___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_105__RX_DCOC_RANGE_105___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_105__RX_DCOC_RANGE_105___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_105__RX_DCOC_RES_I_105___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_105__RX_DCOC_RES_I_105___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_105__RX_DCOC_RES_Q_105___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_105__RX_DCOC_RES_Q_105___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_105___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_105___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_106 (0x005FC1A8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_106___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_106___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_106__RX_DCOC_RANGE_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_106__RX_DCOC_RES_I_106___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_106__RX_DCOC_RES_Q_106___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_106__RX_DCOC_RANGE_106___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_106__RX_DCOC_RANGE_106___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_106__RX_DCOC_RES_I_106___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_106__RX_DCOC_RES_I_106___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_106__RX_DCOC_RES_Q_106___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_106__RX_DCOC_RES_Q_106___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_106___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_106___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_107 (0x005FC1AC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_107___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_107___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_107__RX_DCOC_RANGE_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_107__RX_DCOC_RES_I_107___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_107__RX_DCOC_RES_Q_107___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_107__RX_DCOC_RANGE_107___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_107__RX_DCOC_RANGE_107___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_107__RX_DCOC_RES_I_107___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_107__RX_DCOC_RES_I_107___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_107__RX_DCOC_RES_Q_107___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_107__RX_DCOC_RES_Q_107___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_107___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_107___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_108 (0x005FC1B0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_108___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_108___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_108__RX_DCOC_RANGE_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_108__RX_DCOC_RES_I_108___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_108__RX_DCOC_RES_Q_108___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_108__RX_DCOC_RANGE_108___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_108__RX_DCOC_RANGE_108___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_108__RX_DCOC_RES_I_108___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_108__RX_DCOC_RES_I_108___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_108__RX_DCOC_RES_Q_108___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_108__RX_DCOC_RES_Q_108___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_108___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_108___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_109 (0x005FC1B4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_109___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_109___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_109__RX_DCOC_RANGE_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_109__RX_DCOC_RES_I_109___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_109__RX_DCOC_RES_Q_109___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_109__RX_DCOC_RANGE_109___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_109__RX_DCOC_RANGE_109___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_109__RX_DCOC_RES_I_109___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_109__RX_DCOC_RES_I_109___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_109__RX_DCOC_RES_Q_109___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_109__RX_DCOC_RES_Q_109___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_109___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_109___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_110 (0x005FC1B8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_110___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_110___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_110__RX_DCOC_RANGE_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_110__RX_DCOC_RES_I_110___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_110__RX_DCOC_RES_Q_110___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_110__RX_DCOC_RANGE_110___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_110__RX_DCOC_RANGE_110___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_110__RX_DCOC_RES_I_110___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_110__RX_DCOC_RES_I_110___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_110__RX_DCOC_RES_Q_110___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_110__RX_DCOC_RES_Q_110___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_110___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_110___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_111 (0x005FC1BC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_111___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_111___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_111__RX_DCOC_RANGE_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_111__RX_DCOC_RES_I_111___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_111__RX_DCOC_RES_Q_111___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_111__RX_DCOC_RANGE_111___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_111__RX_DCOC_RANGE_111___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_111__RX_DCOC_RES_I_111___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_111__RX_DCOC_RES_I_111___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_111__RX_DCOC_RES_Q_111___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_111__RX_DCOC_RES_Q_111___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_111___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_111___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_112 (0x005FC1C0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_112___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_112___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_112__RX_DCOC_RANGE_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_112__RX_DCOC_RES_I_112___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_112__RX_DCOC_RES_Q_112___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_112__RX_DCOC_RANGE_112___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_112__RX_DCOC_RANGE_112___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_112__RX_DCOC_RES_I_112___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_112__RX_DCOC_RES_I_112___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_112__RX_DCOC_RES_Q_112___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_112__RX_DCOC_RES_Q_112___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_112___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_112___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_113 (0x005FC1C4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_113___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_113___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_113__RX_DCOC_RANGE_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_113__RX_DCOC_RES_I_113___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_113__RX_DCOC_RES_Q_113___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_113__RX_DCOC_RANGE_113___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_113__RX_DCOC_RANGE_113___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_113__RX_DCOC_RES_I_113___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_113__RX_DCOC_RES_I_113___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_113__RX_DCOC_RES_Q_113___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_113__RX_DCOC_RES_Q_113___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_113___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_113___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_114 (0x005FC1C8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_114___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_114___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_114__RX_DCOC_RANGE_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_114__RX_DCOC_RES_I_114___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_114__RX_DCOC_RES_Q_114___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_114__RX_DCOC_RANGE_114___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_114__RX_DCOC_RANGE_114___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_114__RX_DCOC_RES_I_114___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_114__RX_DCOC_RES_I_114___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_114__RX_DCOC_RES_Q_114___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_114__RX_DCOC_RES_Q_114___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_114___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_114___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_115 (0x005FC1CC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_115___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_115___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_115__RX_DCOC_RANGE_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_115__RX_DCOC_RES_I_115___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_115__RX_DCOC_RES_Q_115___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_115__RX_DCOC_RANGE_115___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_115__RX_DCOC_RANGE_115___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_115__RX_DCOC_RES_I_115___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_115__RX_DCOC_RES_I_115___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_115__RX_DCOC_RES_Q_115___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_115__RX_DCOC_RES_Q_115___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_115___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_115___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_116 (0x005FC1D0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_116___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_116___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_116__RX_DCOC_RANGE_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_116__RX_DCOC_RES_I_116___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_116__RX_DCOC_RES_Q_116___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_116__RX_DCOC_RANGE_116___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_116__RX_DCOC_RANGE_116___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_116__RX_DCOC_RES_I_116___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_116__RX_DCOC_RES_I_116___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_116__RX_DCOC_RES_Q_116___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_116__RX_DCOC_RES_Q_116___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_116___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_116___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_117 (0x005FC1D4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_117___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_117___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_117__RX_DCOC_RANGE_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_117__RX_DCOC_RES_I_117___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_117__RX_DCOC_RES_Q_117___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_117__RX_DCOC_RANGE_117___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_117__RX_DCOC_RANGE_117___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_117__RX_DCOC_RES_I_117___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_117__RX_DCOC_RES_I_117___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_117__RX_DCOC_RES_Q_117___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_117__RX_DCOC_RES_Q_117___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_117___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_117___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_118 (0x005FC1D8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_118___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_118___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_118__RX_DCOC_RANGE_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_118__RX_DCOC_RES_I_118___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_118__RX_DCOC_RES_Q_118___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_118__RX_DCOC_RANGE_118___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_118__RX_DCOC_RANGE_118___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_118__RX_DCOC_RES_I_118___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_118__RX_DCOC_RES_I_118___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_118__RX_DCOC_RES_Q_118___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_118__RX_DCOC_RES_Q_118___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_118___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_118___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_119 (0x005FC1DC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_119___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_119___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_119__RX_DCOC_RANGE_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_119__RX_DCOC_RES_I_119___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_119__RX_DCOC_RES_Q_119___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_119__RX_DCOC_RANGE_119___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_119__RX_DCOC_RANGE_119___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_119__RX_DCOC_RES_I_119___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_119__RX_DCOC_RES_I_119___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_119__RX_DCOC_RES_Q_119___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_119__RX_DCOC_RES_Q_119___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_119___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_119___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_120 (0x005FC1E0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_120___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_120___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_120__RX_DCOC_RANGE_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_120__RX_DCOC_RES_I_120___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_120__RX_DCOC_RES_Q_120___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_120__RX_DCOC_RANGE_120___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_120__RX_DCOC_RANGE_120___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_120__RX_DCOC_RES_I_120___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_120__RX_DCOC_RES_I_120___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_120__RX_DCOC_RES_Q_120___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_120__RX_DCOC_RES_Q_120___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_120___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_120___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_121 (0x005FC1E4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_121___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_121___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_121__RX_DCOC_RANGE_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_121__RX_DCOC_RES_I_121___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_121__RX_DCOC_RES_Q_121___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_121__RX_DCOC_RANGE_121___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_121__RX_DCOC_RANGE_121___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_121__RX_DCOC_RES_I_121___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_121__RX_DCOC_RES_I_121___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_121__RX_DCOC_RES_Q_121___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_121__RX_DCOC_RES_Q_121___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_121___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_121___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_122 (0x005FC1E8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_122___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_122___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_122__RX_DCOC_RANGE_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_122__RX_DCOC_RES_I_122___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_122__RX_DCOC_RES_Q_122___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_122__RX_DCOC_RANGE_122___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_122__RX_DCOC_RANGE_122___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_122__RX_DCOC_RES_I_122___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_122__RX_DCOC_RES_I_122___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_122__RX_DCOC_RES_Q_122___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_122__RX_DCOC_RES_Q_122___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_122___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_122___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_123 (0x005FC1EC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_123___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_123___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_123__RX_DCOC_RANGE_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_123__RX_DCOC_RES_I_123___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_123__RX_DCOC_RES_Q_123___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_123__RX_DCOC_RANGE_123___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_123__RX_DCOC_RANGE_123___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_123__RX_DCOC_RES_I_123___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_123__RX_DCOC_RES_I_123___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_123__RX_DCOC_RES_Q_123___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_123__RX_DCOC_RES_Q_123___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_123___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_123___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_124 (0x005FC1F0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_124___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_124___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_124__RX_DCOC_RANGE_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_124__RX_DCOC_RES_I_124___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_124__RX_DCOC_RES_Q_124___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_124__RX_DCOC_RANGE_124___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_124__RX_DCOC_RANGE_124___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_124__RX_DCOC_RES_I_124___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_124__RX_DCOC_RES_I_124___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_124__RX_DCOC_RES_Q_124___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_124__RX_DCOC_RES_Q_124___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_124___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_124___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_125 (0x005FC1F4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_125___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_125___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_125__RX_DCOC_RANGE_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_125__RX_DCOC_RES_I_125___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_125__RX_DCOC_RES_Q_125___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_125__RX_DCOC_RANGE_125___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_125__RX_DCOC_RANGE_125___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_125__RX_DCOC_RES_I_125___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_125__RX_DCOC_RES_I_125___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_125__RX_DCOC_RES_Q_125___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_125__RX_DCOC_RES_Q_125___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_125___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_125___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_126 (0x005FC1F8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_126___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_126___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_126__RX_DCOC_RANGE_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_126__RX_DCOC_RES_I_126___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_126__RX_DCOC_RES_Q_126___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_126__RX_DCOC_RANGE_126___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_126__RX_DCOC_RANGE_126___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_126__RX_DCOC_RES_I_126___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_126__RX_DCOC_RES_I_126___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_126__RX_DCOC_RES_Q_126___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_126__RX_DCOC_RES_Q_126___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_126___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_126___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_127 (0x005FC1FC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_127___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_127___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_127__RX_DCOC_RANGE_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_127__RX_DCOC_RES_I_127___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_127__RX_DCOC_RES_Q_127___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_127__RX_DCOC_RANGE_127___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_127__RX_DCOC_RANGE_127___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_127__RX_DCOC_RES_I_127___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_127__RX_DCOC_RES_I_127___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_127__RX_DCOC_RES_Q_127___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_127__RX_DCOC_RES_Q_127___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_127___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_127___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_128 (0x005FC200) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_128___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_128___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_128__RX_DCOC_RANGE_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_128__RX_DCOC_RES_I_128___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_128__RX_DCOC_RES_Q_128___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_128__RX_DCOC_RANGE_128___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_128__RX_DCOC_RANGE_128___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_128__RX_DCOC_RES_I_128___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_128__RX_DCOC_RES_I_128___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_128__RX_DCOC_RES_Q_128___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_128__RX_DCOC_RES_Q_128___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_128___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_128___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_129 (0x005FC204) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_129___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_129___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_129__RX_DCOC_RANGE_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_129__RX_DCOC_RES_I_129___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_129__RX_DCOC_RES_Q_129___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_129__RX_DCOC_RANGE_129___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_129__RX_DCOC_RANGE_129___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_129__RX_DCOC_RES_I_129___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_129__RX_DCOC_RES_I_129___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_129__RX_DCOC_RES_Q_129___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_129__RX_DCOC_RES_Q_129___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_129___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_129___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_130 (0x005FC208) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_130___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_130___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_130__RX_DCOC_RANGE_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_130__RX_DCOC_RES_I_130___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_130__RX_DCOC_RES_Q_130___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_130__RX_DCOC_RANGE_130___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_130__RX_DCOC_RANGE_130___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_130__RX_DCOC_RES_I_130___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_130__RX_DCOC_RES_I_130___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_130__RX_DCOC_RES_Q_130___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_130__RX_DCOC_RES_Q_130___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_130___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_130___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_131 (0x005FC20C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_131___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_131___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_131__RX_DCOC_RANGE_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_131__RX_DCOC_RES_I_131___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_131__RX_DCOC_RES_Q_131___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_131__RX_DCOC_RANGE_131___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_131__RX_DCOC_RANGE_131___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_131__RX_DCOC_RES_I_131___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_131__RX_DCOC_RES_I_131___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_131__RX_DCOC_RES_Q_131___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_131__RX_DCOC_RES_Q_131___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_131___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_131___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_132 (0x005FC210) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_132___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_132___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_132__RX_DCOC_RANGE_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_132__RX_DCOC_RES_I_132___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_132__RX_DCOC_RES_Q_132___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_132__RX_DCOC_RANGE_132___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_132__RX_DCOC_RANGE_132___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_132__RX_DCOC_RES_I_132___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_132__RX_DCOC_RES_I_132___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_132__RX_DCOC_RES_Q_132___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_132__RX_DCOC_RES_Q_132___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_132___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_132___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_133 (0x005FC214) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_133___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_133___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_133__RX_DCOC_RANGE_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_133__RX_DCOC_RES_I_133___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_133__RX_DCOC_RES_Q_133___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_133__RX_DCOC_RANGE_133___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_133__RX_DCOC_RANGE_133___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_133__RX_DCOC_RES_I_133___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_133__RX_DCOC_RES_I_133___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_133__RX_DCOC_RES_Q_133___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_133__RX_DCOC_RES_Q_133___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_133___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_133___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_134 (0x005FC218) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_134___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_134___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_134__RX_DCOC_RANGE_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_134__RX_DCOC_RES_I_134___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_134__RX_DCOC_RES_Q_134___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_134__RX_DCOC_RANGE_134___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_134__RX_DCOC_RANGE_134___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_134__RX_DCOC_RES_I_134___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_134__RX_DCOC_RES_I_134___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_134__RX_DCOC_RES_Q_134___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_134__RX_DCOC_RES_Q_134___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_134___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_134___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_135 (0x005FC21C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_135___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_135___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_135__RX_DCOC_RANGE_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_135__RX_DCOC_RES_I_135___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_135__RX_DCOC_RES_Q_135___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_135__RX_DCOC_RANGE_135___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_135__RX_DCOC_RANGE_135___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_135__RX_DCOC_RES_I_135___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_135__RX_DCOC_RES_I_135___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_135__RX_DCOC_RES_Q_135___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_135__RX_DCOC_RES_Q_135___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_135___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_135___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_136 (0x005FC220) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_136___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_136___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_136__RX_DCOC_RANGE_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_136__RX_DCOC_RES_I_136___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_136__RX_DCOC_RES_Q_136___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_136__RX_DCOC_RANGE_136___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_136__RX_DCOC_RANGE_136___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_136__RX_DCOC_RES_I_136___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_136__RX_DCOC_RES_I_136___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_136__RX_DCOC_RES_Q_136___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_136__RX_DCOC_RES_Q_136___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_136___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_136___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_137 (0x005FC224) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_137___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_137___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_137__RX_DCOC_RANGE_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_137__RX_DCOC_RES_I_137___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_137__RX_DCOC_RES_Q_137___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_137__RX_DCOC_RANGE_137___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_137__RX_DCOC_RANGE_137___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_137__RX_DCOC_RES_I_137___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_137__RX_DCOC_RES_I_137___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_137__RX_DCOC_RES_Q_137___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_137__RX_DCOC_RES_Q_137___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_137___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_137___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_138 (0x005FC228) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_138___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_138___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_138__RX_DCOC_RANGE_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_138__RX_DCOC_RES_I_138___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_138__RX_DCOC_RES_Q_138___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_138__RX_DCOC_RANGE_138___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_138__RX_DCOC_RANGE_138___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_138__RX_DCOC_RES_I_138___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_138__RX_DCOC_RES_I_138___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_138__RX_DCOC_RES_Q_138___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_138__RX_DCOC_RES_Q_138___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_138___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_138___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_139 (0x005FC22C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_139___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_139___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_139__RX_DCOC_RANGE_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_139__RX_DCOC_RES_I_139___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_139__RX_DCOC_RES_Q_139___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_139__RX_DCOC_RANGE_139___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_139__RX_DCOC_RANGE_139___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_139__RX_DCOC_RES_I_139___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_139__RX_DCOC_RES_I_139___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_139__RX_DCOC_RES_Q_139___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_139__RX_DCOC_RES_Q_139___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_139___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_139___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_140 (0x005FC230) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_140___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_140___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_140__RX_DCOC_RANGE_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_140__RX_DCOC_RES_I_140___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_140__RX_DCOC_RES_Q_140___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_140__RX_DCOC_RANGE_140___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_140__RX_DCOC_RANGE_140___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_140__RX_DCOC_RES_I_140___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_140__RX_DCOC_RES_I_140___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_140__RX_DCOC_RES_Q_140___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_140__RX_DCOC_RES_Q_140___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_140___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_140___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_141 (0x005FC234) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_141___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_141___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_141__RX_DCOC_RANGE_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_141__RX_DCOC_RES_I_141___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_141__RX_DCOC_RES_Q_141___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_141__RX_DCOC_RANGE_141___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_141__RX_DCOC_RANGE_141___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_141__RX_DCOC_RES_I_141___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_141__RX_DCOC_RES_I_141___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_141__RX_DCOC_RES_Q_141___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_141__RX_DCOC_RES_Q_141___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_141___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_141___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_142 (0x005FC238) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_142___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_142___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_142__RX_DCOC_RANGE_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_142__RX_DCOC_RES_I_142___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_142__RX_DCOC_RES_Q_142___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_142__RX_DCOC_RANGE_142___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_142__RX_DCOC_RANGE_142___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_142__RX_DCOC_RES_I_142___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_142__RX_DCOC_RES_I_142___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_142__RX_DCOC_RES_Q_142___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_142__RX_DCOC_RES_Q_142___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_142___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_142___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_143 (0x005FC23C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_143___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_143___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_143__RX_DCOC_RANGE_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_143__RX_DCOC_RES_I_143___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_143__RX_DCOC_RES_Q_143___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_143__RX_DCOC_RANGE_143___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_143__RX_DCOC_RANGE_143___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_143__RX_DCOC_RES_I_143___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_143__RX_DCOC_RES_I_143___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_143__RX_DCOC_RES_Q_143___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_143__RX_DCOC_RES_Q_143___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_143___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_143___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_144 (0x005FC240) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_144___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_144___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_144__RX_DCOC_RANGE_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_144__RX_DCOC_RES_I_144___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_144__RX_DCOC_RES_Q_144___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_144__RX_DCOC_RANGE_144___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_144__RX_DCOC_RANGE_144___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_144__RX_DCOC_RES_I_144___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_144__RX_DCOC_RES_I_144___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_144__RX_DCOC_RES_Q_144___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_144__RX_DCOC_RES_Q_144___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_144___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_144___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_145 (0x005FC244) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_145___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_145___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_145__RX_DCOC_RANGE_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_145__RX_DCOC_RES_I_145___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_145__RX_DCOC_RES_Q_145___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_145__RX_DCOC_RANGE_145___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_145__RX_DCOC_RANGE_145___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_145__RX_DCOC_RES_I_145___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_145__RX_DCOC_RES_I_145___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_145__RX_DCOC_RES_Q_145___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_145__RX_DCOC_RES_Q_145___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_145___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_145___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_146 (0x005FC248) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_146___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_146___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_146__RX_DCOC_RANGE_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_146__RX_DCOC_RES_I_146___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_146__RX_DCOC_RES_Q_146___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_146__RX_DCOC_RANGE_146___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_146__RX_DCOC_RANGE_146___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_146__RX_DCOC_RES_I_146___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_146__RX_DCOC_RES_I_146___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_146__RX_DCOC_RES_Q_146___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_146__RX_DCOC_RES_Q_146___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_146___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_146___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_147 (0x005FC24C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_147___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_147___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_147__RX_DCOC_RANGE_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_147__RX_DCOC_RES_I_147___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_147__RX_DCOC_RES_Q_147___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_147__RX_DCOC_RANGE_147___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_147__RX_DCOC_RANGE_147___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_147__RX_DCOC_RES_I_147___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_147__RX_DCOC_RES_I_147___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_147__RX_DCOC_RES_Q_147___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_147__RX_DCOC_RES_Q_147___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_147___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_147___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_148 (0x005FC250) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_148___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_148___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_148__RX_DCOC_RANGE_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_148__RX_DCOC_RES_I_148___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_148__RX_DCOC_RES_Q_148___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_148__RX_DCOC_RANGE_148___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_148__RX_DCOC_RANGE_148___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_148__RX_DCOC_RES_I_148___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_148__RX_DCOC_RES_I_148___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_148__RX_DCOC_RES_Q_148___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_148__RX_DCOC_RES_Q_148___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_148___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_148___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_149 (0x005FC254) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_149___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_149___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_149__RX_DCOC_RANGE_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_149__RX_DCOC_RES_I_149___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_149__RX_DCOC_RES_Q_149___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_149__RX_DCOC_RANGE_149___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_149__RX_DCOC_RANGE_149___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_149__RX_DCOC_RES_I_149___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_149__RX_DCOC_RES_I_149___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_149__RX_DCOC_RES_Q_149___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_149__RX_DCOC_RES_Q_149___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_149___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_149___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_150 (0x005FC258) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_150___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_150___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_150__RX_DCOC_RANGE_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_150__RX_DCOC_RES_I_150___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_150__RX_DCOC_RES_Q_150___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_150__RX_DCOC_RANGE_150___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_150__RX_DCOC_RANGE_150___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_150__RX_DCOC_RES_I_150___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_150__RX_DCOC_RES_I_150___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_150__RX_DCOC_RES_Q_150___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_150__RX_DCOC_RES_Q_150___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_150___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_150___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_151 (0x005FC25C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_151___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_151___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_151__RX_DCOC_RANGE_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_151__RX_DCOC_RES_I_151___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_151__RX_DCOC_RES_Q_151___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_151__RX_DCOC_RANGE_151___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_151__RX_DCOC_RANGE_151___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_151__RX_DCOC_RES_I_151___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_151__RX_DCOC_RES_I_151___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_151__RX_DCOC_RES_Q_151___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_151__RX_DCOC_RES_Q_151___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_151___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_151___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_152 (0x005FC260) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_152___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_152___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_152__RX_DCOC_RANGE_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_152__RX_DCOC_RES_I_152___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_152__RX_DCOC_RES_Q_152___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_152__RX_DCOC_RANGE_152___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_152__RX_DCOC_RANGE_152___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_152__RX_DCOC_RES_I_152___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_152__RX_DCOC_RES_I_152___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_152__RX_DCOC_RES_Q_152___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_152__RX_DCOC_RES_Q_152___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_152___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_152___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_153 (0x005FC264) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_153___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_153___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_153__RX_DCOC_RANGE_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_153__RX_DCOC_RES_I_153___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_153__RX_DCOC_RES_Q_153___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_153__RX_DCOC_RANGE_153___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_153__RX_DCOC_RANGE_153___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_153__RX_DCOC_RES_I_153___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_153__RX_DCOC_RES_I_153___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_153__RX_DCOC_RES_Q_153___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_153__RX_DCOC_RES_Q_153___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_153___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_153___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_154 (0x005FC268) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_154___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_154___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_154__RX_DCOC_RANGE_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_154__RX_DCOC_RES_I_154___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_154__RX_DCOC_RES_Q_154___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_154__RX_DCOC_RANGE_154___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_154__RX_DCOC_RANGE_154___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_154__RX_DCOC_RES_I_154___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_154__RX_DCOC_RES_I_154___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_154__RX_DCOC_RES_Q_154___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_154__RX_DCOC_RES_Q_154___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_154___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_154___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_155 (0x005FC26C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_155___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_155___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_155__RX_DCOC_RANGE_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_155__RX_DCOC_RES_I_155___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_155__RX_DCOC_RES_Q_155___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_155__RX_DCOC_RANGE_155___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_155__RX_DCOC_RANGE_155___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_155__RX_DCOC_RES_I_155___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_155__RX_DCOC_RES_I_155___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_155__RX_DCOC_RES_Q_155___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_155__RX_DCOC_RES_Q_155___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_155___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_155___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_156 (0x005FC270) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_156___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_156___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_156__RX_DCOC_RANGE_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_156__RX_DCOC_RES_I_156___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_156__RX_DCOC_RES_Q_156___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_156__RX_DCOC_RANGE_156___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_156__RX_DCOC_RANGE_156___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_156__RX_DCOC_RES_I_156___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_156__RX_DCOC_RES_I_156___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_156__RX_DCOC_RES_Q_156___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_156__RX_DCOC_RES_Q_156___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_156___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_156___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_157 (0x005FC274) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_157___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_157___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_157__RX_DCOC_RANGE_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_157__RX_DCOC_RES_I_157___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_157__RX_DCOC_RES_Q_157___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_157__RX_DCOC_RANGE_157___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_157__RX_DCOC_RANGE_157___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_157__RX_DCOC_RES_I_157___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_157__RX_DCOC_RES_I_157___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_157__RX_DCOC_RES_Q_157___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_157__RX_DCOC_RES_Q_157___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_157___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_157___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_158 (0x005FC278) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_158___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_158___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_158__RX_DCOC_RANGE_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_158__RX_DCOC_RES_I_158___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_158__RX_DCOC_RES_Q_158___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_158__RX_DCOC_RANGE_158___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_158__RX_DCOC_RANGE_158___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_158__RX_DCOC_RES_I_158___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_158__RX_DCOC_RES_I_158___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_158__RX_DCOC_RES_Q_158___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_158__RX_DCOC_RES_Q_158___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_158___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_158___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_159 (0x005FC27C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_159___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_159___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_159__RX_DCOC_RANGE_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_159__RX_DCOC_RES_I_159___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_159__RX_DCOC_RES_Q_159___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_159__RX_DCOC_RANGE_159___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_159__RX_DCOC_RANGE_159___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_159__RX_DCOC_RES_I_159___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_159__RX_DCOC_RES_I_159___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_159__RX_DCOC_RES_Q_159___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_159__RX_DCOC_RES_Q_159___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_159___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_159___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_160 (0x005FC280) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_160___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_160___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_160__RX_DCOC_RANGE_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_160__RX_DCOC_RES_I_160___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_160__RX_DCOC_RES_Q_160___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_160__RX_DCOC_RANGE_160___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_160__RX_DCOC_RANGE_160___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_160__RX_DCOC_RES_I_160___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_160__RX_DCOC_RES_I_160___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_160__RX_DCOC_RES_Q_160___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_160__RX_DCOC_RES_Q_160___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_160___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_160___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_161 (0x005FC284) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_161___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_161___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_161__RX_DCOC_RANGE_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_161__RX_DCOC_RES_I_161___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_161__RX_DCOC_RES_Q_161___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_161__RX_DCOC_RANGE_161___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_161__RX_DCOC_RANGE_161___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_161__RX_DCOC_RES_I_161___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_161__RX_DCOC_RES_I_161___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_161__RX_DCOC_RES_Q_161___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_161__RX_DCOC_RES_Q_161___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_161___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_161___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_162 (0x005FC288) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_162___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_162___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_162__RX_DCOC_RANGE_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_162__RX_DCOC_RES_I_162___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_162__RX_DCOC_RES_Q_162___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_162__RX_DCOC_RANGE_162___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_162__RX_DCOC_RANGE_162___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_162__RX_DCOC_RES_I_162___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_162__RX_DCOC_RES_I_162___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_162__RX_DCOC_RES_Q_162___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_162__RX_DCOC_RES_Q_162___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_162___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_162___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_163 (0x005FC28C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_163___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_163___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_163__RX_DCOC_RANGE_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_163__RX_DCOC_RES_I_163___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_163__RX_DCOC_RES_Q_163___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_163__RX_DCOC_RANGE_163___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_163__RX_DCOC_RANGE_163___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_163__RX_DCOC_RES_I_163___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_163__RX_DCOC_RES_I_163___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_163__RX_DCOC_RES_Q_163___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_163__RX_DCOC_RES_Q_163___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_163___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_163___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_164 (0x005FC290) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_164___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_164___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_164__RX_DCOC_RANGE_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_164__RX_DCOC_RES_I_164___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_164__RX_DCOC_RES_Q_164___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_164__RX_DCOC_RANGE_164___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_164__RX_DCOC_RANGE_164___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_164__RX_DCOC_RES_I_164___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_164__RX_DCOC_RES_I_164___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_164__RX_DCOC_RES_Q_164___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_164__RX_DCOC_RES_Q_164___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_164___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_164___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_165 (0x005FC294) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_165___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_165___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_165__RX_DCOC_RANGE_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_165__RX_DCOC_RES_I_165___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_165__RX_DCOC_RES_Q_165___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_165__RX_DCOC_RANGE_165___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_165__RX_DCOC_RANGE_165___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_165__RX_DCOC_RES_I_165___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_165__RX_DCOC_RES_I_165___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_165__RX_DCOC_RES_Q_165___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_165__RX_DCOC_RES_Q_165___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_165___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_165___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_166 (0x005FC298) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_166___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_166___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_166__RX_DCOC_RANGE_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_166__RX_DCOC_RES_I_166___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_166__RX_DCOC_RES_Q_166___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_166__RX_DCOC_RANGE_166___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_166__RX_DCOC_RANGE_166___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_166__RX_DCOC_RES_I_166___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_166__RX_DCOC_RES_I_166___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_166__RX_DCOC_RES_Q_166___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_166__RX_DCOC_RES_Q_166___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_166___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_166___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_167 (0x005FC29C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_167___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_167___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_167__RX_DCOC_RANGE_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_167__RX_DCOC_RES_I_167___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_167__RX_DCOC_RES_Q_167___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_167__RX_DCOC_RANGE_167___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_167__RX_DCOC_RANGE_167___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_167__RX_DCOC_RES_I_167___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_167__RX_DCOC_RES_I_167___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_167__RX_DCOC_RES_Q_167___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_167__RX_DCOC_RES_Q_167___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_167___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_167___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_168 (0x005FC2A0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_168___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_168___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_168__RX_DCOC_RANGE_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_168__RX_DCOC_RES_I_168___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_168__RX_DCOC_RES_Q_168___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_168__RX_DCOC_RANGE_168___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_168__RX_DCOC_RANGE_168___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_168__RX_DCOC_RES_I_168___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_168__RX_DCOC_RES_I_168___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_168__RX_DCOC_RES_Q_168___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_168__RX_DCOC_RES_Q_168___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_168___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_168___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_169 (0x005FC2A4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_169___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_169___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_169__RX_DCOC_RANGE_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_169__RX_DCOC_RES_I_169___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_169__RX_DCOC_RES_Q_169___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_169__RX_DCOC_RANGE_169___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_169__RX_DCOC_RANGE_169___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_169__RX_DCOC_RES_I_169___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_169__RX_DCOC_RES_I_169___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_169__RX_DCOC_RES_Q_169___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_169__RX_DCOC_RES_Q_169___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_169___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_169___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_170 (0x005FC2A8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_170___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_170___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_170__RX_DCOC_RANGE_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_170__RX_DCOC_RES_I_170___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_170__RX_DCOC_RES_Q_170___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_170__RX_DCOC_RANGE_170___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_170__RX_DCOC_RANGE_170___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_170__RX_DCOC_RES_I_170___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_170__RX_DCOC_RES_I_170___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_170__RX_DCOC_RES_Q_170___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_170__RX_DCOC_RES_Q_170___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_170___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_170___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_171 (0x005FC2AC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_171___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_171___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_171__RX_DCOC_RANGE_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_171__RX_DCOC_RES_I_171___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_171__RX_DCOC_RES_Q_171___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_171__RX_DCOC_RANGE_171___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_171__RX_DCOC_RANGE_171___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_171__RX_DCOC_RES_I_171___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_171__RX_DCOC_RES_I_171___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_171__RX_DCOC_RES_Q_171___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_171__RX_DCOC_RES_Q_171___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_171___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_171___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_172 (0x005FC2B0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_172___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_172___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_172__RX_DCOC_RANGE_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_172__RX_DCOC_RES_I_172___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_172__RX_DCOC_RES_Q_172___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_172__RX_DCOC_RANGE_172___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_172__RX_DCOC_RANGE_172___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_172__RX_DCOC_RES_I_172___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_172__RX_DCOC_RES_I_172___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_172__RX_DCOC_RES_Q_172___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_172__RX_DCOC_RES_Q_172___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_172___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_172___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_173 (0x005FC2B4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_173___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_173___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_173__RX_DCOC_RANGE_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_173__RX_DCOC_RES_I_173___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_173__RX_DCOC_RES_Q_173___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_173__RX_DCOC_RANGE_173___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_173__RX_DCOC_RANGE_173___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_173__RX_DCOC_RES_I_173___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_173__RX_DCOC_RES_I_173___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_173__RX_DCOC_RES_Q_173___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_173__RX_DCOC_RES_Q_173___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_173___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_173___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_174 (0x005FC2B8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_174___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_174___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_174__RX_DCOC_RANGE_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_174__RX_DCOC_RES_I_174___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_174__RX_DCOC_RES_Q_174___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_174__RX_DCOC_RANGE_174___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_174__RX_DCOC_RANGE_174___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_174__RX_DCOC_RES_I_174___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_174__RX_DCOC_RES_I_174___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_174__RX_DCOC_RES_Q_174___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_174__RX_DCOC_RES_Q_174___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_174___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_174___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_175 (0x005FC2BC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_175___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_175___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_175__RX_DCOC_RANGE_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_175__RX_DCOC_RES_I_175___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_175__RX_DCOC_RES_Q_175___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_175__RX_DCOC_RANGE_175___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_175__RX_DCOC_RANGE_175___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_175__RX_DCOC_RES_I_175___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_175__RX_DCOC_RES_I_175___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_175__RX_DCOC_RES_Q_175___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_175__RX_DCOC_RES_Q_175___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_175___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_175___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_176 (0x005FC2C0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_176___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_176___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_176__RX_DCOC_RANGE_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_176__RX_DCOC_RES_I_176___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_176__RX_DCOC_RES_Q_176___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_176__RX_DCOC_RANGE_176___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_176__RX_DCOC_RANGE_176___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_176__RX_DCOC_RES_I_176___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_176__RX_DCOC_RES_I_176___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_176__RX_DCOC_RES_Q_176___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_176__RX_DCOC_RES_Q_176___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_176___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_176___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_177 (0x005FC2C4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_177___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_177___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_177__RX_DCOC_RANGE_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_177__RX_DCOC_RES_I_177___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_177__RX_DCOC_RES_Q_177___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_177__RX_DCOC_RANGE_177___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_177__RX_DCOC_RANGE_177___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_177__RX_DCOC_RES_I_177___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_177__RX_DCOC_RES_I_177___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_177__RX_DCOC_RES_Q_177___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_177__RX_DCOC_RES_Q_177___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_177___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_177___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_178 (0x005FC2C8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_178___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_178___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_178__RX_DCOC_RANGE_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_178__RX_DCOC_RES_I_178___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_178__RX_DCOC_RES_Q_178___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_178__RX_DCOC_RANGE_178___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_178__RX_DCOC_RANGE_178___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_178__RX_DCOC_RES_I_178___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_178__RX_DCOC_RES_I_178___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_178__RX_DCOC_RES_Q_178___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_178__RX_DCOC_RES_Q_178___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_178___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_178___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_179 (0x005FC2CC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_179___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_179___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_179__RX_DCOC_RANGE_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_179__RX_DCOC_RES_I_179___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_179__RX_DCOC_RES_Q_179___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_179__RX_DCOC_RANGE_179___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_179__RX_DCOC_RANGE_179___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_179__RX_DCOC_RES_I_179___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_179__RX_DCOC_RES_I_179___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_179__RX_DCOC_RES_Q_179___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_179__RX_DCOC_RES_Q_179___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_179___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_179___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_180 (0x005FC2D0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_180___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_180___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_180__RX_DCOC_RANGE_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_180__RX_DCOC_RES_I_180___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_180__RX_DCOC_RES_Q_180___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_180__RX_DCOC_RANGE_180___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_180__RX_DCOC_RANGE_180___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_180__RX_DCOC_RES_I_180___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_180__RX_DCOC_RES_I_180___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_180__RX_DCOC_RES_Q_180___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_180__RX_DCOC_RES_Q_180___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_180___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_180___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_181 (0x005FC2D4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_181___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_181___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_181__RX_DCOC_RANGE_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_181__RX_DCOC_RES_I_181___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_181__RX_DCOC_RES_Q_181___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_181__RX_DCOC_RANGE_181___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_181__RX_DCOC_RANGE_181___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_181__RX_DCOC_RES_I_181___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_181__RX_DCOC_RES_I_181___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_181__RX_DCOC_RES_Q_181___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_181__RX_DCOC_RES_Q_181___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_181___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_181___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_182 (0x005FC2D8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_182___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_182___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_182__RX_DCOC_RANGE_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_182__RX_DCOC_RES_I_182___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_182__RX_DCOC_RES_Q_182___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_182__RX_DCOC_RANGE_182___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_182__RX_DCOC_RANGE_182___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_182__RX_DCOC_RES_I_182___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_182__RX_DCOC_RES_I_182___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_182__RX_DCOC_RES_Q_182___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_182__RX_DCOC_RES_Q_182___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_182___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_182___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_183 (0x005FC2DC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_183___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_183___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_183__RX_DCOC_RANGE_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_183__RX_DCOC_RES_I_183___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_183__RX_DCOC_RES_Q_183___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_183__RX_DCOC_RANGE_183___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_183__RX_DCOC_RANGE_183___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_183__RX_DCOC_RES_I_183___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_183__RX_DCOC_RES_I_183___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_183__RX_DCOC_RES_Q_183___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_183__RX_DCOC_RES_Q_183___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_183___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_183___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_184 (0x005FC2E0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_184___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_184___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_184__RX_DCOC_RANGE_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_184__RX_DCOC_RES_I_184___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_184__RX_DCOC_RES_Q_184___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_184__RX_DCOC_RANGE_184___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_184__RX_DCOC_RANGE_184___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_184__RX_DCOC_RES_I_184___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_184__RX_DCOC_RES_I_184___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_184__RX_DCOC_RES_Q_184___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_184__RX_DCOC_RES_Q_184___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_184___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_184___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_185 (0x005FC2E4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_185___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_185___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_185__RX_DCOC_RANGE_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_185__RX_DCOC_RES_I_185___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_185__RX_DCOC_RES_Q_185___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_185__RX_DCOC_RANGE_185___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_185__RX_DCOC_RANGE_185___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_185__RX_DCOC_RES_I_185___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_185__RX_DCOC_RES_I_185___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_185__RX_DCOC_RES_Q_185___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_185__RX_DCOC_RES_Q_185___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_185___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_185___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_186 (0x005FC2E8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_186___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_186___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_186__RX_DCOC_RANGE_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_186__RX_DCOC_RES_I_186___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_186__RX_DCOC_RES_Q_186___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_186__RX_DCOC_RANGE_186___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_186__RX_DCOC_RANGE_186___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_186__RX_DCOC_RES_I_186___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_186__RX_DCOC_RES_I_186___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_186__RX_DCOC_RES_Q_186___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_186__RX_DCOC_RES_Q_186___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_186___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_186___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_187 (0x005FC2EC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_187___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_187___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_187__RX_DCOC_RANGE_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_187__RX_DCOC_RES_I_187___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_187__RX_DCOC_RES_Q_187___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_187__RX_DCOC_RANGE_187___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_187__RX_DCOC_RANGE_187___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_187__RX_DCOC_RES_I_187___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_187__RX_DCOC_RES_I_187___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_187__RX_DCOC_RES_Q_187___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_187__RX_DCOC_RES_Q_187___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_187___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_187___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_188 (0x005FC2F0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_188___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_188___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_188__RX_DCOC_RANGE_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_188__RX_DCOC_RES_I_188___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_188__RX_DCOC_RES_Q_188___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_188__RX_DCOC_RANGE_188___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_188__RX_DCOC_RANGE_188___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_188__RX_DCOC_RES_I_188___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_188__RX_DCOC_RES_I_188___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_188__RX_DCOC_RES_Q_188___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_188__RX_DCOC_RES_Q_188___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_188___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_188___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_189 (0x005FC2F4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_189___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_189___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_189__RX_DCOC_RANGE_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_189__RX_DCOC_RES_I_189___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_189__RX_DCOC_RES_Q_189___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_189__RX_DCOC_RANGE_189___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_189__RX_DCOC_RANGE_189___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_189__RX_DCOC_RES_I_189___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_189__RX_DCOC_RES_I_189___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_189__RX_DCOC_RES_Q_189___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_189__RX_DCOC_RES_Q_189___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_189___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_189___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_190 (0x005FC2F8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_190___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_190___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_190__RX_DCOC_RANGE_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_190__RX_DCOC_RES_I_190___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_190__RX_DCOC_RES_Q_190___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_190__RX_DCOC_RANGE_190___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_190__RX_DCOC_RANGE_190___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_190__RX_DCOC_RES_I_190___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_190__RX_DCOC_RES_I_190___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_190__RX_DCOC_RES_Q_190___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_190__RX_DCOC_RES_Q_190___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_190___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_190___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_191 (0x005FC2FC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_191___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_191___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_191__RX_DCOC_RANGE_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_191__RX_DCOC_RES_I_191___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_191__RX_DCOC_RES_Q_191___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_191__RX_DCOC_RANGE_191___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_191__RX_DCOC_RANGE_191___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_191__RX_DCOC_RES_I_191___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_191__RX_DCOC_RES_I_191___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_191__RX_DCOC_RES_Q_191___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_191__RX_DCOC_RES_Q_191___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_191___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_191___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_192 (0x005FC300) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_192___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_192___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_192__RX_DCOC_RANGE_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_192__RX_DCOC_RES_I_192___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_192__RX_DCOC_RES_Q_192___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_192__RX_DCOC_RANGE_192___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_192__RX_DCOC_RANGE_192___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_192__RX_DCOC_RES_I_192___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_192__RX_DCOC_RES_I_192___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_192__RX_DCOC_RES_Q_192___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_192__RX_DCOC_RES_Q_192___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_192___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_192___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_193 (0x005FC304) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_193___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_193___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_193__RX_DCOC_RANGE_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_193__RX_DCOC_RES_I_193___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_193__RX_DCOC_RES_Q_193___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_193__RX_DCOC_RANGE_193___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_193__RX_DCOC_RANGE_193___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_193__RX_DCOC_RES_I_193___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_193__RX_DCOC_RES_I_193___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_193__RX_DCOC_RES_Q_193___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_193__RX_DCOC_RES_Q_193___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_193___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_193___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_194 (0x005FC308) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_194___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_194___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_194__RX_DCOC_RANGE_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_194__RX_DCOC_RES_I_194___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_194__RX_DCOC_RES_Q_194___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_194__RX_DCOC_RANGE_194___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_194__RX_DCOC_RANGE_194___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_194__RX_DCOC_RES_I_194___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_194__RX_DCOC_RES_I_194___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_194__RX_DCOC_RES_Q_194___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_194__RX_DCOC_RES_Q_194___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_194___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_194___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_195 (0x005FC30C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_195___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_195___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_195__RX_DCOC_RANGE_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_195__RX_DCOC_RES_I_195___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_195__RX_DCOC_RES_Q_195___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_195__RX_DCOC_RANGE_195___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_195__RX_DCOC_RANGE_195___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_195__RX_DCOC_RES_I_195___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_195__RX_DCOC_RES_I_195___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_195__RX_DCOC_RES_Q_195___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_195__RX_DCOC_RES_Q_195___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_195___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_195___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_196 (0x005FC310) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_196___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_196___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_196__RX_DCOC_RANGE_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_196__RX_DCOC_RES_I_196___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_196__RX_DCOC_RES_Q_196___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_196__RX_DCOC_RANGE_196___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_196__RX_DCOC_RANGE_196___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_196__RX_DCOC_RES_I_196___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_196__RX_DCOC_RES_I_196___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_196__RX_DCOC_RES_Q_196___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_196__RX_DCOC_RES_Q_196___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_196___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_196___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_197 (0x005FC314) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_197___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_197___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_197__RX_DCOC_RANGE_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_197__RX_DCOC_RES_I_197___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_197__RX_DCOC_RES_Q_197___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_197__RX_DCOC_RANGE_197___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_197__RX_DCOC_RANGE_197___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_197__RX_DCOC_RES_I_197___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_197__RX_DCOC_RES_I_197___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_197__RX_DCOC_RES_Q_197___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_197__RX_DCOC_RES_Q_197___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_197___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_197___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_198 (0x005FC318) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_198___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_198___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_198__RX_DCOC_RANGE_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_198__RX_DCOC_RES_I_198___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_198__RX_DCOC_RES_Q_198___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_198__RX_DCOC_RANGE_198___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_198__RX_DCOC_RANGE_198___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_198__RX_DCOC_RES_I_198___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_198__RX_DCOC_RES_I_198___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_198__RX_DCOC_RES_Q_198___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_198__RX_DCOC_RES_Q_198___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_198___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_198___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_199 (0x005FC31C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_199___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_199___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_199__RX_DCOC_RANGE_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_199__RX_DCOC_RES_I_199___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_199__RX_DCOC_RES_Q_199___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_199__RX_DCOC_RANGE_199___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_199__RX_DCOC_RANGE_199___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_199__RX_DCOC_RES_I_199___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_199__RX_DCOC_RES_I_199___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_199__RX_DCOC_RES_Q_199___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_199__RX_DCOC_RES_Q_199___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_199___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_199___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_200 (0x005FC320) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_200___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_200___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_200__RX_DCOC_RANGE_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_200__RX_DCOC_RES_I_200___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_200__RX_DCOC_RES_Q_200___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_200__RX_DCOC_RANGE_200___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_200__RX_DCOC_RANGE_200___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_200__RX_DCOC_RES_I_200___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_200__RX_DCOC_RES_I_200___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_200__RX_DCOC_RES_Q_200___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_200__RX_DCOC_RES_Q_200___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_200___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_200___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_201 (0x005FC324) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_201___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_201___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_201__RX_DCOC_RANGE_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_201__RX_DCOC_RES_I_201___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_201__RX_DCOC_RES_Q_201___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_201__RX_DCOC_RANGE_201___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_201__RX_DCOC_RANGE_201___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_201__RX_DCOC_RES_I_201___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_201__RX_DCOC_RES_I_201___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_201__RX_DCOC_RES_Q_201___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_201__RX_DCOC_RES_Q_201___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_201___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_201___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_202 (0x005FC328) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_202___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_202___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_202__RX_DCOC_RANGE_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_202__RX_DCOC_RES_I_202___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_202__RX_DCOC_RES_Q_202___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_202__RX_DCOC_RANGE_202___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_202__RX_DCOC_RANGE_202___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_202__RX_DCOC_RES_I_202___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_202__RX_DCOC_RES_I_202___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_202__RX_DCOC_RES_Q_202___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_202__RX_DCOC_RES_Q_202___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_202___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_202___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_203 (0x005FC32C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_203___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_203___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_203__RX_DCOC_RANGE_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_203__RX_DCOC_RES_I_203___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_203__RX_DCOC_RES_Q_203___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_203__RX_DCOC_RANGE_203___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_203__RX_DCOC_RANGE_203___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_203__RX_DCOC_RES_I_203___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_203__RX_DCOC_RES_I_203___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_203__RX_DCOC_RES_Q_203___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_203__RX_DCOC_RES_Q_203___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_203___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_203___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_204 (0x005FC330) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_204___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_204___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_204__RX_DCOC_RANGE_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_204__RX_DCOC_RES_I_204___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_204__RX_DCOC_RES_Q_204___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_204__RX_DCOC_RANGE_204___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_204__RX_DCOC_RANGE_204___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_204__RX_DCOC_RES_I_204___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_204__RX_DCOC_RES_I_204___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_204__RX_DCOC_RES_Q_204___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_204__RX_DCOC_RES_Q_204___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_204___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_204___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_205 (0x005FC334) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_205___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_205___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_205__RX_DCOC_RANGE_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_205__RX_DCOC_RES_I_205___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_205__RX_DCOC_RES_Q_205___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_205__RX_DCOC_RANGE_205___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_205__RX_DCOC_RANGE_205___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_205__RX_DCOC_RES_I_205___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_205__RX_DCOC_RES_I_205___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_205__RX_DCOC_RES_Q_205___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_205__RX_DCOC_RES_Q_205___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_205___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_205___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_206 (0x005FC338) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_206___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_206___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_206__RX_DCOC_RANGE_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_206__RX_DCOC_RES_I_206___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_206__RX_DCOC_RES_Q_206___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_206__RX_DCOC_RANGE_206___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_206__RX_DCOC_RANGE_206___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_206__RX_DCOC_RES_I_206___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_206__RX_DCOC_RES_I_206___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_206__RX_DCOC_RES_Q_206___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_206__RX_DCOC_RES_Q_206___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_206___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_206___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_207 (0x005FC33C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_207___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_207___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_207__RX_DCOC_RANGE_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_207__RX_DCOC_RES_I_207___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_207__RX_DCOC_RES_Q_207___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_207__RX_DCOC_RANGE_207___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_207__RX_DCOC_RANGE_207___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_207__RX_DCOC_RES_I_207___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_207__RX_DCOC_RES_I_207___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_207__RX_DCOC_RES_Q_207___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_207__RX_DCOC_RES_Q_207___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_207___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_207___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_208 (0x005FC340) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_208___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_208___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_208__RX_DCOC_RANGE_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_208__RX_DCOC_RES_I_208___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_208__RX_DCOC_RES_Q_208___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_208__RX_DCOC_RANGE_208___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_208__RX_DCOC_RANGE_208___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_208__RX_DCOC_RES_I_208___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_208__RX_DCOC_RES_I_208___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_208__RX_DCOC_RES_Q_208___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_208__RX_DCOC_RES_Q_208___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_208___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_208___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_209 (0x005FC344) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_209___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_209___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_209__RX_DCOC_RANGE_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_209__RX_DCOC_RES_I_209___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_209__RX_DCOC_RES_Q_209___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_209__RX_DCOC_RANGE_209___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_209__RX_DCOC_RANGE_209___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_209__RX_DCOC_RES_I_209___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_209__RX_DCOC_RES_I_209___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_209__RX_DCOC_RES_Q_209___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_209__RX_DCOC_RES_Q_209___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_209___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_209___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_210 (0x005FC348) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_210___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_210___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_210__RX_DCOC_RANGE_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_210__RX_DCOC_RES_I_210___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_210__RX_DCOC_RES_Q_210___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_210__RX_DCOC_RANGE_210___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_210__RX_DCOC_RANGE_210___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_210__RX_DCOC_RES_I_210___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_210__RX_DCOC_RES_I_210___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_210__RX_DCOC_RES_Q_210___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_210__RX_DCOC_RES_Q_210___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_210___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_210___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_211 (0x005FC34C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_211___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_211___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_211__RX_DCOC_RANGE_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_211__RX_DCOC_RES_I_211___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_211__RX_DCOC_RES_Q_211___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_211__RX_DCOC_RANGE_211___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_211__RX_DCOC_RANGE_211___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_211__RX_DCOC_RES_I_211___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_211__RX_DCOC_RES_I_211___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_211__RX_DCOC_RES_Q_211___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_211__RX_DCOC_RES_Q_211___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_211___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_211___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_212 (0x005FC350) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_212___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_212___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_212__RX_DCOC_RANGE_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_212__RX_DCOC_RES_I_212___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_212__RX_DCOC_RES_Q_212___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_212__RX_DCOC_RANGE_212___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_212__RX_DCOC_RANGE_212___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_212__RX_DCOC_RES_I_212___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_212__RX_DCOC_RES_I_212___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_212__RX_DCOC_RES_Q_212___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_212__RX_DCOC_RES_Q_212___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_212___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_212___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_213 (0x005FC354) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_213___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_213___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_213__RX_DCOC_RANGE_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_213__RX_DCOC_RES_I_213___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_213__RX_DCOC_RES_Q_213___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_213__RX_DCOC_RANGE_213___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_213__RX_DCOC_RANGE_213___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_213__RX_DCOC_RES_I_213___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_213__RX_DCOC_RES_I_213___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_213__RX_DCOC_RES_Q_213___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_213__RX_DCOC_RES_Q_213___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_213___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_213___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_214 (0x005FC358) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_214___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_214___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_214__RX_DCOC_RANGE_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_214__RX_DCOC_RES_I_214___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_214__RX_DCOC_RES_Q_214___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_214__RX_DCOC_RANGE_214___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_214__RX_DCOC_RANGE_214___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_214__RX_DCOC_RES_I_214___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_214__RX_DCOC_RES_I_214___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_214__RX_DCOC_RES_Q_214___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_214__RX_DCOC_RES_Q_214___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_214___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_214___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_215 (0x005FC35C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_215___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_215___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_215__RX_DCOC_RANGE_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_215__RX_DCOC_RES_I_215___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_215__RX_DCOC_RES_Q_215___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_215__RX_DCOC_RANGE_215___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_215__RX_DCOC_RANGE_215___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_215__RX_DCOC_RES_I_215___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_215__RX_DCOC_RES_I_215___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_215__RX_DCOC_RES_Q_215___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_215__RX_DCOC_RES_Q_215___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_215___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_215___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_216 (0x005FC360) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_216___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_216___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_216__RX_DCOC_RANGE_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_216__RX_DCOC_RES_I_216___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_216__RX_DCOC_RES_Q_216___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_216__RX_DCOC_RANGE_216___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_216__RX_DCOC_RANGE_216___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_216__RX_DCOC_RES_I_216___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_216__RX_DCOC_RES_I_216___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_216__RX_DCOC_RES_Q_216___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_216__RX_DCOC_RES_Q_216___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_216___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_216___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_217 (0x005FC364) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_217___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_217___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_217__RX_DCOC_RANGE_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_217__RX_DCOC_RES_I_217___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_217__RX_DCOC_RES_Q_217___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_217__RX_DCOC_RANGE_217___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_217__RX_DCOC_RANGE_217___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_217__RX_DCOC_RES_I_217___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_217__RX_DCOC_RES_I_217___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_217__RX_DCOC_RES_Q_217___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_217__RX_DCOC_RES_Q_217___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_217___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_217___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_218 (0x005FC368) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_218___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_218___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_218__RX_DCOC_RANGE_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_218__RX_DCOC_RES_I_218___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_218__RX_DCOC_RES_Q_218___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_218__RX_DCOC_RANGE_218___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_218__RX_DCOC_RANGE_218___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_218__RX_DCOC_RES_I_218___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_218__RX_DCOC_RES_I_218___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_218__RX_DCOC_RES_Q_218___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_218__RX_DCOC_RES_Q_218___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_218___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_218___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_219 (0x005FC36C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_219___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_219___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_219__RX_DCOC_RANGE_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_219__RX_DCOC_RES_I_219___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_219__RX_DCOC_RES_Q_219___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_219__RX_DCOC_RANGE_219___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_219__RX_DCOC_RANGE_219___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_219__RX_DCOC_RES_I_219___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_219__RX_DCOC_RES_I_219___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_219__RX_DCOC_RES_Q_219___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_219__RX_DCOC_RES_Q_219___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_219___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_219___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_220 (0x005FC370) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_220___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_220___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_220__RX_DCOC_RANGE_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_220__RX_DCOC_RES_I_220___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_220__RX_DCOC_RES_Q_220___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_220__RX_DCOC_RANGE_220___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_220__RX_DCOC_RANGE_220___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_220__RX_DCOC_RES_I_220___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_220__RX_DCOC_RES_I_220___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_220__RX_DCOC_RES_Q_220___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_220__RX_DCOC_RES_Q_220___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_220___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_220___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_221 (0x005FC374) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_221___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_221___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_221__RX_DCOC_RANGE_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_221__RX_DCOC_RES_I_221___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_221__RX_DCOC_RES_Q_221___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_221__RX_DCOC_RANGE_221___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_221__RX_DCOC_RANGE_221___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_221__RX_DCOC_RES_I_221___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_221__RX_DCOC_RES_I_221___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_221__RX_DCOC_RES_Q_221___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_221__RX_DCOC_RES_Q_221___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_221___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_221___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_222 (0x005FC378) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_222___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_222___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_222__RX_DCOC_RANGE_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_222__RX_DCOC_RES_I_222___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_222__RX_DCOC_RES_Q_222___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_222__RX_DCOC_RANGE_222___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_222__RX_DCOC_RANGE_222___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_222__RX_DCOC_RES_I_222___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_222__RX_DCOC_RES_I_222___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_222__RX_DCOC_RES_Q_222___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_222__RX_DCOC_RES_Q_222___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_222___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_222___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_223 (0x005FC37C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_223___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_223___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_223__RX_DCOC_RANGE_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_223__RX_DCOC_RES_I_223___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_223__RX_DCOC_RES_Q_223___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_223__RX_DCOC_RANGE_223___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_223__RX_DCOC_RANGE_223___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_223__RX_DCOC_RES_I_223___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_223__RX_DCOC_RES_I_223___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_223__RX_DCOC_RES_Q_223___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_223__RX_DCOC_RES_Q_223___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_223___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_223___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_224 (0x005FC380) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_224___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_224___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_224__RX_DCOC_RANGE_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_224__RX_DCOC_RES_I_224___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_224__RX_DCOC_RES_Q_224___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_224__RX_DCOC_RANGE_224___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_224__RX_DCOC_RANGE_224___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_224__RX_DCOC_RES_I_224___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_224__RX_DCOC_RES_I_224___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_224__RX_DCOC_RES_Q_224___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_224__RX_DCOC_RES_Q_224___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_224___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_224___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_225 (0x005FC384) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_225___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_225___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_225__RX_DCOC_RANGE_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_225__RX_DCOC_RES_I_225___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_225__RX_DCOC_RES_Q_225___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_225__RX_DCOC_RANGE_225___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_225__RX_DCOC_RANGE_225___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_225__RX_DCOC_RES_I_225___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_225__RX_DCOC_RES_I_225___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_225__RX_DCOC_RES_Q_225___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_225__RX_DCOC_RES_Q_225___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_225___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_225___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_226 (0x005FC388) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_226___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_226___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_226__RX_DCOC_RANGE_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_226__RX_DCOC_RES_I_226___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_226__RX_DCOC_RES_Q_226___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_226__RX_DCOC_RANGE_226___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_226__RX_DCOC_RANGE_226___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_226__RX_DCOC_RES_I_226___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_226__RX_DCOC_RES_I_226___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_226__RX_DCOC_RES_Q_226___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_226__RX_DCOC_RES_Q_226___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_226___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_226___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_227 (0x005FC38C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_227___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_227___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_227__RX_DCOC_RANGE_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_227__RX_DCOC_RES_I_227___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_227__RX_DCOC_RES_Q_227___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_227__RX_DCOC_RANGE_227___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_227__RX_DCOC_RANGE_227___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_227__RX_DCOC_RES_I_227___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_227__RX_DCOC_RES_I_227___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_227__RX_DCOC_RES_Q_227___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_227__RX_DCOC_RES_Q_227___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_227___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_227___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_228 (0x005FC390) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_228___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_228___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_228__RX_DCOC_RANGE_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_228__RX_DCOC_RES_I_228___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_228__RX_DCOC_RES_Q_228___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_228__RX_DCOC_RANGE_228___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_228__RX_DCOC_RANGE_228___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_228__RX_DCOC_RES_I_228___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_228__RX_DCOC_RES_I_228___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_228__RX_DCOC_RES_Q_228___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_228__RX_DCOC_RES_Q_228___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_228___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_228___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_229 (0x005FC394) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_229___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_229___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_229__RX_DCOC_RANGE_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_229__RX_DCOC_RES_I_229___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_229__RX_DCOC_RES_Q_229___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_229__RX_DCOC_RANGE_229___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_229__RX_DCOC_RANGE_229___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_229__RX_DCOC_RES_I_229___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_229__RX_DCOC_RES_I_229___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_229__RX_DCOC_RES_Q_229___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_229__RX_DCOC_RES_Q_229___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_229___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_229___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_230 (0x005FC398) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_230___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_230___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_230__RX_DCOC_RANGE_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_230__RX_DCOC_RES_I_230___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_230__RX_DCOC_RES_Q_230___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_230__RX_DCOC_RANGE_230___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_230__RX_DCOC_RANGE_230___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_230__RX_DCOC_RES_I_230___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_230__RX_DCOC_RES_I_230___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_230__RX_DCOC_RES_Q_230___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_230__RX_DCOC_RES_Q_230___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_230___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_230___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_231 (0x005FC39C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_231___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_231___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_231__RX_DCOC_RANGE_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_231__RX_DCOC_RES_I_231___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_231__RX_DCOC_RES_Q_231___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_231__RX_DCOC_RANGE_231___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_231__RX_DCOC_RANGE_231___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_231__RX_DCOC_RES_I_231___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_231__RX_DCOC_RES_I_231___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_231__RX_DCOC_RES_Q_231___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_231__RX_DCOC_RES_Q_231___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_231___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_231___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_232 (0x005FC3A0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_232___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_232___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_232__RX_DCOC_RANGE_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_232__RX_DCOC_RES_I_232___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_232__RX_DCOC_RES_Q_232___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_232__RX_DCOC_RANGE_232___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_232__RX_DCOC_RANGE_232___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_232__RX_DCOC_RES_I_232___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_232__RX_DCOC_RES_I_232___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_232__RX_DCOC_RES_Q_232___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_232__RX_DCOC_RES_Q_232___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_232___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_232___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_233 (0x005FC3A4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_233___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_233___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_233__RX_DCOC_RANGE_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_233__RX_DCOC_RES_I_233___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_233__RX_DCOC_RES_Q_233___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_233__RX_DCOC_RANGE_233___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_233__RX_DCOC_RANGE_233___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_233__RX_DCOC_RES_I_233___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_233__RX_DCOC_RES_I_233___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_233__RX_DCOC_RES_Q_233___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_233__RX_DCOC_RES_Q_233___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_233___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_233___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_234 (0x005FC3A8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_234___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_234___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_234__RX_DCOC_RANGE_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_234__RX_DCOC_RES_I_234___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_234__RX_DCOC_RES_Q_234___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_234__RX_DCOC_RANGE_234___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_234__RX_DCOC_RANGE_234___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_234__RX_DCOC_RES_I_234___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_234__RX_DCOC_RES_I_234___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_234__RX_DCOC_RES_Q_234___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_234__RX_DCOC_RES_Q_234___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_234___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_234___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_235 (0x005FC3AC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_235___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_235___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_235__RX_DCOC_RANGE_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_235__RX_DCOC_RES_I_235___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_235__RX_DCOC_RES_Q_235___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_235__RX_DCOC_RANGE_235___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_235__RX_DCOC_RANGE_235___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_235__RX_DCOC_RES_I_235___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_235__RX_DCOC_RES_I_235___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_235__RX_DCOC_RES_Q_235___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_235__RX_DCOC_RES_Q_235___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_235___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_235___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_236 (0x005FC3B0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_236___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_236___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_236__RX_DCOC_RANGE_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_236__RX_DCOC_RES_I_236___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_236__RX_DCOC_RES_Q_236___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_236__RX_DCOC_RANGE_236___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_236__RX_DCOC_RANGE_236___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_236__RX_DCOC_RES_I_236___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_236__RX_DCOC_RES_I_236___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_236__RX_DCOC_RES_Q_236___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_236__RX_DCOC_RES_Q_236___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_236___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_236___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_237 (0x005FC3B4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_237___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_237___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_237__RX_DCOC_RANGE_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_237__RX_DCOC_RES_I_237___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_237__RX_DCOC_RES_Q_237___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_237__RX_DCOC_RANGE_237___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_237__RX_DCOC_RANGE_237___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_237__RX_DCOC_RES_I_237___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_237__RX_DCOC_RES_I_237___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_237__RX_DCOC_RES_Q_237___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_237__RX_DCOC_RES_Q_237___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_237___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_237___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_238 (0x005FC3B8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_238___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_238___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_238__RX_DCOC_RANGE_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_238__RX_DCOC_RES_I_238___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_238__RX_DCOC_RES_Q_238___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_238__RX_DCOC_RANGE_238___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_238__RX_DCOC_RANGE_238___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_238__RX_DCOC_RES_I_238___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_238__RX_DCOC_RES_I_238___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_238__RX_DCOC_RES_Q_238___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_238__RX_DCOC_RES_Q_238___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_238___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_238___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_239 (0x005FC3BC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_239___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_239___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_239__RX_DCOC_RANGE_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_239__RX_DCOC_RES_I_239___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_239__RX_DCOC_RES_Q_239___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_239__RX_DCOC_RANGE_239___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_239__RX_DCOC_RANGE_239___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_239__RX_DCOC_RES_I_239___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_239__RX_DCOC_RES_I_239___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_239__RX_DCOC_RES_Q_239___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_239__RX_DCOC_RES_Q_239___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_239___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_239___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_240 (0x005FC3C0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_240___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_240___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_240__RX_DCOC_RANGE_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_240__RX_DCOC_RES_I_240___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_240__RX_DCOC_RES_Q_240___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_240__RX_DCOC_RANGE_240___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_240__RX_DCOC_RANGE_240___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_240__RX_DCOC_RES_I_240___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_240__RX_DCOC_RES_I_240___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_240__RX_DCOC_RES_Q_240___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_240__RX_DCOC_RES_Q_240___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_240___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_240___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_241 (0x005FC3C4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_241___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_241___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_241__RX_DCOC_RANGE_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_241__RX_DCOC_RES_I_241___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_241__RX_DCOC_RES_Q_241___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_241__RX_DCOC_RANGE_241___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_241__RX_DCOC_RANGE_241___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_241__RX_DCOC_RES_I_241___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_241__RX_DCOC_RES_I_241___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_241__RX_DCOC_RES_Q_241___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_241__RX_DCOC_RES_Q_241___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_241___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_241___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_242 (0x005FC3C8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_242___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_242___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_242__RX_DCOC_RANGE_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_242__RX_DCOC_RES_I_242___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_242__RX_DCOC_RES_Q_242___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_242__RX_DCOC_RANGE_242___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_242__RX_DCOC_RANGE_242___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_242__RX_DCOC_RES_I_242___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_242__RX_DCOC_RES_I_242___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_242__RX_DCOC_RES_Q_242___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_242__RX_DCOC_RES_Q_242___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_242___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_242___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_243 (0x005FC3CC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_243___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_243___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_243__RX_DCOC_RANGE_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_243__RX_DCOC_RES_I_243___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_243__RX_DCOC_RES_Q_243___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_243__RX_DCOC_RANGE_243___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_243__RX_DCOC_RANGE_243___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_243__RX_DCOC_RES_I_243___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_243__RX_DCOC_RES_I_243___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_243__RX_DCOC_RES_Q_243___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_243__RX_DCOC_RES_Q_243___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_243___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_243___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_244 (0x005FC3D0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_244___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_244___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_244__RX_DCOC_RANGE_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_244__RX_DCOC_RES_I_244___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_244__RX_DCOC_RES_Q_244___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_244__RX_DCOC_RANGE_244___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_244__RX_DCOC_RANGE_244___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_244__RX_DCOC_RES_I_244___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_244__RX_DCOC_RES_I_244___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_244__RX_DCOC_RES_Q_244___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_244__RX_DCOC_RES_Q_244___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_244___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_244___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_245 (0x005FC3D4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_245___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_245___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_245__RX_DCOC_RANGE_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_245__RX_DCOC_RES_I_245___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_245__RX_DCOC_RES_Q_245___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_245__RX_DCOC_RANGE_245___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_245__RX_DCOC_RANGE_245___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_245__RX_DCOC_RES_I_245___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_245__RX_DCOC_RES_I_245___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_245__RX_DCOC_RES_Q_245___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_245__RX_DCOC_RES_Q_245___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_245___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_245___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_246 (0x005FC3D8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_246___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_246___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_246__RX_DCOC_RANGE_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_246__RX_DCOC_RES_I_246___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_246__RX_DCOC_RES_Q_246___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_246__RX_DCOC_RANGE_246___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_246__RX_DCOC_RANGE_246___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_246__RX_DCOC_RES_I_246___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_246__RX_DCOC_RES_I_246___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_246__RX_DCOC_RES_Q_246___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_246__RX_DCOC_RES_Q_246___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_246___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_246___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_247 (0x005FC3DC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_247___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_247___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_247__RX_DCOC_RANGE_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_247__RX_DCOC_RES_I_247___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_247__RX_DCOC_RES_Q_247___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_247__RX_DCOC_RANGE_247___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_247__RX_DCOC_RANGE_247___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_247__RX_DCOC_RES_I_247___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_247__RX_DCOC_RES_I_247___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_247__RX_DCOC_RES_Q_247___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_247__RX_DCOC_RES_Q_247___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_247___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_247___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_248 (0x005FC3E0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_248___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_248___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_248__RX_DCOC_RANGE_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_248__RX_DCOC_RES_I_248___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_248__RX_DCOC_RES_Q_248___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_248__RX_DCOC_RANGE_248___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_248__RX_DCOC_RANGE_248___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_248__RX_DCOC_RES_I_248___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_248__RX_DCOC_RES_I_248___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_248__RX_DCOC_RES_Q_248___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_248__RX_DCOC_RES_Q_248___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_248___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_248___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_249 (0x005FC3E4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_249___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_249___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_249__RX_DCOC_RANGE_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_249__RX_DCOC_RES_I_249___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_249__RX_DCOC_RES_Q_249___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_249__RX_DCOC_RANGE_249___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_249__RX_DCOC_RANGE_249___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_249__RX_DCOC_RES_I_249___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_249__RX_DCOC_RES_I_249___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_249__RX_DCOC_RES_Q_249___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_249__RX_DCOC_RES_Q_249___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_249___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_249___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_250 (0x005FC3E8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_250___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_250___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_250__RX_DCOC_RANGE_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_250__RX_DCOC_RES_I_250___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_250__RX_DCOC_RES_Q_250___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_250__RX_DCOC_RANGE_250___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_250__RX_DCOC_RANGE_250___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_250__RX_DCOC_RES_I_250___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_250__RX_DCOC_RES_I_250___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_250__RX_DCOC_RES_Q_250___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_250__RX_DCOC_RES_Q_250___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_250___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_250___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_251 (0x005FC3EC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_251___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_251___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_251__RX_DCOC_RANGE_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_251__RX_DCOC_RES_I_251___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_251__RX_DCOC_RES_Q_251___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_251__RX_DCOC_RANGE_251___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_251__RX_DCOC_RANGE_251___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_251__RX_DCOC_RES_I_251___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_251__RX_DCOC_RES_I_251___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_251__RX_DCOC_RES_Q_251___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_251__RX_DCOC_RES_Q_251___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_251___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_251___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_252 (0x005FC3F0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_252___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_252___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_252__RX_DCOC_RANGE_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_252__RX_DCOC_RES_I_252___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_252__RX_DCOC_RES_Q_252___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_252__RX_DCOC_RANGE_252___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_252__RX_DCOC_RANGE_252___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_252__RX_DCOC_RES_I_252___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_252__RX_DCOC_RES_I_252___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_252__RX_DCOC_RES_Q_252___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_252__RX_DCOC_RES_Q_252___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_252___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_252___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_253 (0x005FC3F4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_253___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_253___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_253__RX_DCOC_RANGE_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_253__RX_DCOC_RES_I_253___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_253__RX_DCOC_RES_Q_253___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_253__RX_DCOC_RANGE_253___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_253__RX_DCOC_RANGE_253___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_253__RX_DCOC_RES_I_253___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_253__RX_DCOC_RES_I_253___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_253__RX_DCOC_RES_Q_253___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_253__RX_DCOC_RES_Q_253___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_253___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_253___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_254 (0x005FC3F8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_254___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_254___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_254__RX_DCOC_RANGE_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_254__RX_DCOC_RES_I_254___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_254__RX_DCOC_RES_Q_254___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_254__RX_DCOC_RANGE_254___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_254__RX_DCOC_RANGE_254___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_254__RX_DCOC_RES_I_254___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_254__RX_DCOC_RES_I_254___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_254__RX_DCOC_RES_Q_254___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_254__RX_DCOC_RES_Q_254___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_254___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_254___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_255 (0x005FC3FC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_255___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_255___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_255__RX_DCOC_RANGE_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_255__RX_DCOC_RES_I_255___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_255__RX_DCOC_RES_Q_255___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_255__RX_DCOC_RANGE_255___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_255__RX_DCOC_RANGE_255___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_255__RX_DCOC_RES_I_255___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_255__RX_DCOC_RES_I_255___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_255__RX_DCOC_RES_Q_255___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_255__RX_DCOC_RES_Q_255___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_255___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_255___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_256 (0x005FC400) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_256___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_256___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_256__RX_DCOC_RANGE_256___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_256__RX_DCOC_RES_I_256___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_256__RX_DCOC_RES_Q_256___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_256__RX_DCOC_RANGE_256___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_256__RX_DCOC_RANGE_256___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_256__RX_DCOC_RES_I_256___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_256__RX_DCOC_RES_I_256___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_256__RX_DCOC_RES_Q_256___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_256__RX_DCOC_RES_Q_256___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_256___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_256___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_257 (0x005FC404) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_257___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_257___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_257__RX_DCOC_RANGE_257___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_257__RX_DCOC_RES_I_257___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_257__RX_DCOC_RES_Q_257___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_257__RX_DCOC_RANGE_257___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_257__RX_DCOC_RANGE_257___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_257__RX_DCOC_RES_I_257___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_257__RX_DCOC_RES_I_257___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_257__RX_DCOC_RES_Q_257___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_257__RX_DCOC_RES_Q_257___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_257___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_257___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_258 (0x005FC408) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_258___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_258___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_258__RX_DCOC_RANGE_258___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_258__RX_DCOC_RES_I_258___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_258__RX_DCOC_RES_Q_258___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_258__RX_DCOC_RANGE_258___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_258__RX_DCOC_RANGE_258___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_258__RX_DCOC_RES_I_258___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_258__RX_DCOC_RES_I_258___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_258__RX_DCOC_RES_Q_258___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_258__RX_DCOC_RES_Q_258___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_258___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_258___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_259 (0x005FC40C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_259___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_259___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_259__RX_DCOC_RANGE_259___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_259__RX_DCOC_RES_I_259___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_259__RX_DCOC_RES_Q_259___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_259__RX_DCOC_RANGE_259___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_259__RX_DCOC_RANGE_259___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_259__RX_DCOC_RES_I_259___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_259__RX_DCOC_RES_I_259___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_259__RX_DCOC_RES_Q_259___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_259__RX_DCOC_RES_Q_259___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_259___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_259___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_260 (0x005FC410) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_260___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_260___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_260__RX_DCOC_RANGE_260___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_260__RX_DCOC_RES_I_260___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_260__RX_DCOC_RES_Q_260___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_260__RX_DCOC_RANGE_260___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_260__RX_DCOC_RANGE_260___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_260__RX_DCOC_RES_I_260___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_260__RX_DCOC_RES_I_260___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_260__RX_DCOC_RES_Q_260___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_260__RX_DCOC_RES_Q_260___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_260___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_260___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_261 (0x005FC414) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_261___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_261___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_261__RX_DCOC_RANGE_261___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_261__RX_DCOC_RES_I_261___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_261__RX_DCOC_RES_Q_261___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_261__RX_DCOC_RANGE_261___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_261__RX_DCOC_RANGE_261___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_261__RX_DCOC_RES_I_261___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_261__RX_DCOC_RES_I_261___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_261__RX_DCOC_RES_Q_261___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_261__RX_DCOC_RES_Q_261___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_261___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_261___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_262 (0x005FC418) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_262___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_262___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_262__RX_DCOC_RANGE_262___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_262__RX_DCOC_RES_I_262___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_262__RX_DCOC_RES_Q_262___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_262__RX_DCOC_RANGE_262___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_262__RX_DCOC_RANGE_262___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_262__RX_DCOC_RES_I_262___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_262__RX_DCOC_RES_I_262___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_262__RX_DCOC_RES_Q_262___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_262__RX_DCOC_RES_Q_262___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_262___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_262___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_263 (0x005FC41C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_263___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_263___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_263__RX_DCOC_RANGE_263___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_263__RX_DCOC_RES_I_263___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_263__RX_DCOC_RES_Q_263___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_263__RX_DCOC_RANGE_263___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_263__RX_DCOC_RANGE_263___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_263__RX_DCOC_RES_I_263___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_263__RX_DCOC_RES_I_263___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_263__RX_DCOC_RES_Q_263___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_263__RX_DCOC_RES_Q_263___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_263___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_263___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_264 (0x005FC420) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_264___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_264___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_264__RX_DCOC_RANGE_264___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_264__RX_DCOC_RES_I_264___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_264__RX_DCOC_RES_Q_264___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_264__RX_DCOC_RANGE_264___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_264__RX_DCOC_RANGE_264___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_264__RX_DCOC_RES_I_264___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_264__RX_DCOC_RES_I_264___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_264__RX_DCOC_RES_Q_264___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_264__RX_DCOC_RES_Q_264___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_264___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_264___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_265 (0x005FC424) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_265___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_265___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_265__RX_DCOC_RANGE_265___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_265__RX_DCOC_RES_I_265___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_265__RX_DCOC_RES_Q_265___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_265__RX_DCOC_RANGE_265___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_265__RX_DCOC_RANGE_265___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_265__RX_DCOC_RES_I_265___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_265__RX_DCOC_RES_I_265___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_265__RX_DCOC_RES_Q_265___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_265__RX_DCOC_RES_Q_265___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_265___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_265___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_266 (0x005FC428) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_266___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_266___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_266__RX_DCOC_RANGE_266___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_266__RX_DCOC_RES_I_266___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_266__RX_DCOC_RES_Q_266___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_266__RX_DCOC_RANGE_266___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_266__RX_DCOC_RANGE_266___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_266__RX_DCOC_RES_I_266___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_266__RX_DCOC_RES_I_266___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_266__RX_DCOC_RES_Q_266___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_266__RX_DCOC_RES_Q_266___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_266___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_266___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_267 (0x005FC42C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_267___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_267___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_267__RX_DCOC_RANGE_267___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_267__RX_DCOC_RES_I_267___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_267__RX_DCOC_RES_Q_267___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_267__RX_DCOC_RANGE_267___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_267__RX_DCOC_RANGE_267___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_267__RX_DCOC_RES_I_267___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_267__RX_DCOC_RES_I_267___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_267__RX_DCOC_RES_Q_267___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_267__RX_DCOC_RES_Q_267___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_267___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_267___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_268 (0x005FC430) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_268___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_268___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_268__RX_DCOC_RANGE_268___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_268__RX_DCOC_RES_I_268___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_268__RX_DCOC_RES_Q_268___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_268__RX_DCOC_RANGE_268___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_268__RX_DCOC_RANGE_268___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_268__RX_DCOC_RES_I_268___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_268__RX_DCOC_RES_I_268___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_268__RX_DCOC_RES_Q_268___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_268__RX_DCOC_RES_Q_268___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_268___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_268___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_269 (0x005FC434) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_269___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_269___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_269__RX_DCOC_RANGE_269___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_269__RX_DCOC_RES_I_269___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_269__RX_DCOC_RES_Q_269___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_269__RX_DCOC_RANGE_269___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_269__RX_DCOC_RANGE_269___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_269__RX_DCOC_RES_I_269___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_269__RX_DCOC_RES_I_269___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_269__RX_DCOC_RES_Q_269___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_269__RX_DCOC_RES_Q_269___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_269___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_269___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_270 (0x005FC438) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_270___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_270___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_270__RX_DCOC_RANGE_270___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_270__RX_DCOC_RES_I_270___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_270__RX_DCOC_RES_Q_270___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_270__RX_DCOC_RANGE_270___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_270__RX_DCOC_RANGE_270___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_270__RX_DCOC_RES_I_270___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_270__RX_DCOC_RES_I_270___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_270__RX_DCOC_RES_Q_270___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_270__RX_DCOC_RES_Q_270___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_270___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_270___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_271 (0x005FC43C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_271___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_271___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_271__RX_DCOC_RANGE_271___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_271__RX_DCOC_RES_I_271___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_271__RX_DCOC_RES_Q_271___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_271__RX_DCOC_RANGE_271___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_271__RX_DCOC_RANGE_271___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_271__RX_DCOC_RES_I_271___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_271__RX_DCOC_RES_I_271___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_271__RX_DCOC_RES_Q_271___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_271__RX_DCOC_RES_Q_271___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_271___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_271___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_272 (0x005FC440) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_272___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_272___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_272__RX_DCOC_RANGE_272___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_272__RX_DCOC_RES_I_272___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_272__RX_DCOC_RES_Q_272___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_272__RX_DCOC_RANGE_272___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_272__RX_DCOC_RANGE_272___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_272__RX_DCOC_RES_I_272___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_272__RX_DCOC_RES_I_272___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_272__RX_DCOC_RES_Q_272___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_272__RX_DCOC_RES_Q_272___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_272___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_272___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_273 (0x005FC444) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_273___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_273___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_273__RX_DCOC_RANGE_273___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_273__RX_DCOC_RES_I_273___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_273__RX_DCOC_RES_Q_273___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_273__RX_DCOC_RANGE_273___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_273__RX_DCOC_RANGE_273___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_273__RX_DCOC_RES_I_273___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_273__RX_DCOC_RES_I_273___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_273__RX_DCOC_RES_Q_273___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_273__RX_DCOC_RES_Q_273___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_273___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_273___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_274 (0x005FC448) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_274___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_274___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_274__RX_DCOC_RANGE_274___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_274__RX_DCOC_RES_I_274___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_274__RX_DCOC_RES_Q_274___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_274__RX_DCOC_RANGE_274___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_274__RX_DCOC_RANGE_274___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_274__RX_DCOC_RES_I_274___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_274__RX_DCOC_RES_I_274___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_274__RX_DCOC_RES_Q_274___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_274__RX_DCOC_RES_Q_274___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_274___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_274___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_275 (0x005FC44C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_275___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_275___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_275__RX_DCOC_RANGE_275___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_275__RX_DCOC_RES_I_275___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_275__RX_DCOC_RES_Q_275___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_275__RX_DCOC_RANGE_275___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_275__RX_DCOC_RANGE_275___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_275__RX_DCOC_RES_I_275___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_275__RX_DCOC_RES_I_275___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_275__RX_DCOC_RES_Q_275___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_275__RX_DCOC_RES_Q_275___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_275___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_275___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_276 (0x005FC450) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_276___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_276___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_276__RX_DCOC_RANGE_276___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_276__RX_DCOC_RES_I_276___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_276__RX_DCOC_RES_Q_276___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_276__RX_DCOC_RANGE_276___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_276__RX_DCOC_RANGE_276___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_276__RX_DCOC_RES_I_276___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_276__RX_DCOC_RES_I_276___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_276__RX_DCOC_RES_Q_276___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_276__RX_DCOC_RES_Q_276___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_276___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_276___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_277 (0x005FC454) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_277___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_277___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_277__RX_DCOC_RANGE_277___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_277__RX_DCOC_RES_I_277___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_277__RX_DCOC_RES_Q_277___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_277__RX_DCOC_RANGE_277___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_277__RX_DCOC_RANGE_277___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_277__RX_DCOC_RES_I_277___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_277__RX_DCOC_RES_I_277___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_277__RX_DCOC_RES_Q_277___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_277__RX_DCOC_RES_Q_277___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_277___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_277___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_278 (0x005FC458) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_278___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_278___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_278__RX_DCOC_RANGE_278___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_278__RX_DCOC_RES_I_278___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_278__RX_DCOC_RES_Q_278___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_278__RX_DCOC_RANGE_278___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_278__RX_DCOC_RANGE_278___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_278__RX_DCOC_RES_I_278___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_278__RX_DCOC_RES_I_278___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_278__RX_DCOC_RES_Q_278___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_278__RX_DCOC_RES_Q_278___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_278___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_278___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_279 (0x005FC45C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_279___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_279___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_279__RX_DCOC_RANGE_279___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_279__RX_DCOC_RES_I_279___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_279__RX_DCOC_RES_Q_279___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_279__RX_DCOC_RANGE_279___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_279__RX_DCOC_RANGE_279___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_279__RX_DCOC_RES_I_279___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_279__RX_DCOC_RES_I_279___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_279__RX_DCOC_RES_Q_279___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_279__RX_DCOC_RES_Q_279___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_279___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_279___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_280 (0x005FC460) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_280___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_280___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_280__RX_DCOC_RANGE_280___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_280__RX_DCOC_RES_I_280___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_280__RX_DCOC_RES_Q_280___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_280__RX_DCOC_RANGE_280___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_280__RX_DCOC_RANGE_280___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_280__RX_DCOC_RES_I_280___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_280__RX_DCOC_RES_I_280___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_280__RX_DCOC_RES_Q_280___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_280__RX_DCOC_RES_Q_280___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_280___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_280___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_281 (0x005FC464) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_281___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_281___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_281__RX_DCOC_RANGE_281___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_281__RX_DCOC_RES_I_281___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_281__RX_DCOC_RES_Q_281___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_281__RX_DCOC_RANGE_281___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_281__RX_DCOC_RANGE_281___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_281__RX_DCOC_RES_I_281___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_281__RX_DCOC_RES_I_281___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_281__RX_DCOC_RES_Q_281___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_281__RX_DCOC_RES_Q_281___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_281___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_281___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_282 (0x005FC468) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_282___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_282___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_282__RX_DCOC_RANGE_282___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_282__RX_DCOC_RES_I_282___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_282__RX_DCOC_RES_Q_282___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_282__RX_DCOC_RANGE_282___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_282__RX_DCOC_RANGE_282___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_282__RX_DCOC_RES_I_282___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_282__RX_DCOC_RES_I_282___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_282__RX_DCOC_RES_Q_282___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_282__RX_DCOC_RES_Q_282___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_282___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_282___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_283 (0x005FC46C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_283___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_283___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_283__RX_DCOC_RANGE_283___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_283__RX_DCOC_RES_I_283___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_283__RX_DCOC_RES_Q_283___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_283__RX_DCOC_RANGE_283___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_283__RX_DCOC_RANGE_283___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_283__RX_DCOC_RES_I_283___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_283__RX_DCOC_RES_I_283___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_283__RX_DCOC_RES_Q_283___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_283__RX_DCOC_RES_Q_283___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_283___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_283___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_284 (0x005FC470) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_284___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_284___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_284__RX_DCOC_RANGE_284___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_284__RX_DCOC_RES_I_284___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_284__RX_DCOC_RES_Q_284___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_284__RX_DCOC_RANGE_284___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_284__RX_DCOC_RANGE_284___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_284__RX_DCOC_RES_I_284___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_284__RX_DCOC_RES_I_284___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_284__RX_DCOC_RES_Q_284___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_284__RX_DCOC_RES_Q_284___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_284___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_284___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_285 (0x005FC474) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_285___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_285___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_285__RX_DCOC_RANGE_285___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_285__RX_DCOC_RES_I_285___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_285__RX_DCOC_RES_Q_285___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_285__RX_DCOC_RANGE_285___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_285__RX_DCOC_RANGE_285___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_285__RX_DCOC_RES_I_285___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_285__RX_DCOC_RES_I_285___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_285__RX_DCOC_RES_Q_285___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_285__RX_DCOC_RES_Q_285___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_285___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_285___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_286 (0x005FC478) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_286___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_286___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_286__RX_DCOC_RANGE_286___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_286__RX_DCOC_RES_I_286___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_286__RX_DCOC_RES_Q_286___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_286__RX_DCOC_RANGE_286___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_286__RX_DCOC_RANGE_286___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_286__RX_DCOC_RES_I_286___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_286__RX_DCOC_RES_I_286___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_286__RX_DCOC_RES_Q_286___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_286__RX_DCOC_RES_Q_286___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_286___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_286___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_287 (0x005FC47C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_287___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_287___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_287__RX_DCOC_RANGE_287___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_287__RX_DCOC_RES_I_287___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_287__RX_DCOC_RES_Q_287___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_287__RX_DCOC_RANGE_287___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_287__RX_DCOC_RANGE_287___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_287__RX_DCOC_RES_I_287___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_287__RX_DCOC_RES_I_287___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_287__RX_DCOC_RES_Q_287___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_287__RX_DCOC_RES_Q_287___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_287___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_287___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_288 (0x005FC480) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_288___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_288___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_288__RX_DCOC_RANGE_288___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_288__RX_DCOC_RES_I_288___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_288__RX_DCOC_RES_Q_288___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_288__RX_DCOC_RANGE_288___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_288__RX_DCOC_RANGE_288___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_288__RX_DCOC_RES_I_288___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_288__RX_DCOC_RES_I_288___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_288__RX_DCOC_RES_Q_288___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_288__RX_DCOC_RES_Q_288___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_288___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_288___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_289 (0x005FC484) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_289___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_289___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_289__RX_DCOC_RANGE_289___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_289__RX_DCOC_RES_I_289___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_289__RX_DCOC_RES_Q_289___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_289__RX_DCOC_RANGE_289___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_289__RX_DCOC_RANGE_289___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_289__RX_DCOC_RES_I_289___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_289__RX_DCOC_RES_I_289___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_289__RX_DCOC_RES_Q_289___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_289__RX_DCOC_RES_Q_289___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_289___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_289___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_290 (0x005FC488) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_290___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_290___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_290__RX_DCOC_RANGE_290___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_290__RX_DCOC_RES_I_290___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_290__RX_DCOC_RES_Q_290___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_290__RX_DCOC_RANGE_290___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_290__RX_DCOC_RANGE_290___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_290__RX_DCOC_RES_I_290___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_290__RX_DCOC_RES_I_290___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_290__RX_DCOC_RES_Q_290___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_290__RX_DCOC_RES_Q_290___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_290___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_290___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_291 (0x005FC48C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_291___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_291___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_291__RX_DCOC_RANGE_291___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_291__RX_DCOC_RES_I_291___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_291__RX_DCOC_RES_Q_291___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_291__RX_DCOC_RANGE_291___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_291__RX_DCOC_RANGE_291___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_291__RX_DCOC_RES_I_291___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_291__RX_DCOC_RES_I_291___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_291__RX_DCOC_RES_Q_291___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_291__RX_DCOC_RES_Q_291___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_291___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_291___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_292 (0x005FC490) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_292___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_292___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_292__RX_DCOC_RANGE_292___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_292__RX_DCOC_RES_I_292___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_292__RX_DCOC_RES_Q_292___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_292__RX_DCOC_RANGE_292___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_292__RX_DCOC_RANGE_292___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_292__RX_DCOC_RES_I_292___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_292__RX_DCOC_RES_I_292___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_292__RX_DCOC_RES_Q_292___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_292__RX_DCOC_RES_Q_292___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_292___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_292___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_293 (0x005FC494) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_293___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_293___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_293__RX_DCOC_RANGE_293___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_293__RX_DCOC_RES_I_293___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_293__RX_DCOC_RES_Q_293___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_293__RX_DCOC_RANGE_293___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_293__RX_DCOC_RANGE_293___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_293__RX_DCOC_RES_I_293___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_293__RX_DCOC_RES_I_293___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_293__RX_DCOC_RES_Q_293___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_293__RX_DCOC_RES_Q_293___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_293___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_293___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_294 (0x005FC498) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_294___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_294___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_294__RX_DCOC_RANGE_294___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_294__RX_DCOC_RES_I_294___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_294__RX_DCOC_RES_Q_294___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_294__RX_DCOC_RANGE_294___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_294__RX_DCOC_RANGE_294___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_294__RX_DCOC_RES_I_294___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_294__RX_DCOC_RES_I_294___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_294__RX_DCOC_RES_Q_294___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_294__RX_DCOC_RES_Q_294___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_294___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_294___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_295 (0x005FC49C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_295___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_295___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_295__RX_DCOC_RANGE_295___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_295__RX_DCOC_RES_I_295___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_295__RX_DCOC_RES_Q_295___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_295__RX_DCOC_RANGE_295___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_295__RX_DCOC_RANGE_295___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_295__RX_DCOC_RES_I_295___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_295__RX_DCOC_RES_I_295___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_295__RX_DCOC_RES_Q_295___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_295__RX_DCOC_RES_Q_295___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_295___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_295___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_296 (0x005FC4A0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_296___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_296___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_296__RX_DCOC_RANGE_296___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_296__RX_DCOC_RES_I_296___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_296__RX_DCOC_RES_Q_296___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_296__RX_DCOC_RANGE_296___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_296__RX_DCOC_RANGE_296___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_296__RX_DCOC_RES_I_296___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_296__RX_DCOC_RES_I_296___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_296__RX_DCOC_RES_Q_296___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_296__RX_DCOC_RES_Q_296___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_296___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_296___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_297 (0x005FC4A4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_297___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_297___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_297__RX_DCOC_RANGE_297___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_297__RX_DCOC_RES_I_297___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_297__RX_DCOC_RES_Q_297___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_297__RX_DCOC_RANGE_297___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_297__RX_DCOC_RANGE_297___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_297__RX_DCOC_RES_I_297___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_297__RX_DCOC_RES_I_297___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_297__RX_DCOC_RES_Q_297___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_297__RX_DCOC_RES_Q_297___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_297___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_297___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_298 (0x005FC4A8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_298___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_298___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_298__RX_DCOC_RANGE_298___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_298__RX_DCOC_RES_I_298___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_298__RX_DCOC_RES_Q_298___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_298__RX_DCOC_RANGE_298___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_298__RX_DCOC_RANGE_298___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_298__RX_DCOC_RES_I_298___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_298__RX_DCOC_RES_I_298___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_298__RX_DCOC_RES_Q_298___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_298__RX_DCOC_RES_Q_298___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_298___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_298___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_299 (0x005FC4AC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_299___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_299___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_299__RX_DCOC_RANGE_299___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_299__RX_DCOC_RES_I_299___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_299__RX_DCOC_RES_Q_299___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_299__RX_DCOC_RANGE_299___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_299__RX_DCOC_RANGE_299___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_299__RX_DCOC_RES_I_299___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_299__RX_DCOC_RES_I_299___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_299__RX_DCOC_RES_Q_299___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_299__RX_DCOC_RES_Q_299___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_299___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_299___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_300 (0x005FC4B0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_300___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_300___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_300__RX_DCOC_RANGE_300___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_300__RX_DCOC_RES_I_300___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_300__RX_DCOC_RES_Q_300___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_300__RX_DCOC_RANGE_300___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_300__RX_DCOC_RANGE_300___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_300__RX_DCOC_RES_I_300___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_300__RX_DCOC_RES_I_300___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_300__RX_DCOC_RES_Q_300___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_300__RX_DCOC_RES_Q_300___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_300___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_300___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_301 (0x005FC4B4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_301___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_301___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_301__RX_DCOC_RANGE_301___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_301__RX_DCOC_RES_I_301___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_301__RX_DCOC_RES_Q_301___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_301__RX_DCOC_RANGE_301___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_301__RX_DCOC_RANGE_301___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_301__RX_DCOC_RES_I_301___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_301__RX_DCOC_RES_I_301___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_301__RX_DCOC_RES_Q_301___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_301__RX_DCOC_RES_Q_301___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_301___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_301___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_302 (0x005FC4B8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_302___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_302___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_302__RX_DCOC_RANGE_302___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_302__RX_DCOC_RES_I_302___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_302__RX_DCOC_RES_Q_302___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_302__RX_DCOC_RANGE_302___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_302__RX_DCOC_RANGE_302___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_302__RX_DCOC_RES_I_302___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_302__RX_DCOC_RES_I_302___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_302__RX_DCOC_RES_Q_302___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_302__RX_DCOC_RES_Q_302___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_302___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_302___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_303 (0x005FC4BC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_303___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_303___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_303__RX_DCOC_RANGE_303___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_303__RX_DCOC_RES_I_303___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_303__RX_DCOC_RES_Q_303___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_303__RX_DCOC_RANGE_303___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_303__RX_DCOC_RANGE_303___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_303__RX_DCOC_RES_I_303___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_303__RX_DCOC_RES_I_303___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_303__RX_DCOC_RES_Q_303___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_303__RX_DCOC_RES_Q_303___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_303___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_303___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_304 (0x005FC4C0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_304___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_304___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_304__RX_DCOC_RANGE_304___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_304__RX_DCOC_RES_I_304___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_304__RX_DCOC_RES_Q_304___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_304__RX_DCOC_RANGE_304___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_304__RX_DCOC_RANGE_304___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_304__RX_DCOC_RES_I_304___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_304__RX_DCOC_RES_I_304___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_304__RX_DCOC_RES_Q_304___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_304__RX_DCOC_RES_Q_304___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_304___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_304___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_305 (0x005FC4C4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_305___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_305___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_305__RX_DCOC_RANGE_305___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_305__RX_DCOC_RES_I_305___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_305__RX_DCOC_RES_Q_305___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_305__RX_DCOC_RANGE_305___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_305__RX_DCOC_RANGE_305___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_305__RX_DCOC_RES_I_305___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_305__RX_DCOC_RES_I_305___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_305__RX_DCOC_RES_Q_305___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_305__RX_DCOC_RES_Q_305___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_305___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_305___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_306 (0x005FC4C8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_306___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_306___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_306__RX_DCOC_RANGE_306___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_306__RX_DCOC_RES_I_306___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_306__RX_DCOC_RES_Q_306___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_306__RX_DCOC_RANGE_306___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_306__RX_DCOC_RANGE_306___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_306__RX_DCOC_RES_I_306___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_306__RX_DCOC_RES_I_306___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_306__RX_DCOC_RES_Q_306___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_306__RX_DCOC_RES_Q_306___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_306___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_306___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_307 (0x005FC4CC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_307___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_307___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_307__RX_DCOC_RANGE_307___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_307__RX_DCOC_RES_I_307___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_307__RX_DCOC_RES_Q_307___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_307__RX_DCOC_RANGE_307___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_307__RX_DCOC_RANGE_307___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_307__RX_DCOC_RES_I_307___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_307__RX_DCOC_RES_I_307___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_307__RX_DCOC_RES_Q_307___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_307__RX_DCOC_RES_Q_307___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_307___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_307___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_308 (0x005FC4D0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_308___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_308___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_308__RX_DCOC_RANGE_308___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_308__RX_DCOC_RES_I_308___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_308__RX_DCOC_RES_Q_308___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_308__RX_DCOC_RANGE_308___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_308__RX_DCOC_RANGE_308___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_308__RX_DCOC_RES_I_308___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_308__RX_DCOC_RES_I_308___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_308__RX_DCOC_RES_Q_308___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_308__RX_DCOC_RES_Q_308___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_308___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_308___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_309 (0x005FC4D4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_309___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_309___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_309__RX_DCOC_RANGE_309___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_309__RX_DCOC_RES_I_309___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_309__RX_DCOC_RES_Q_309___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_309__RX_DCOC_RANGE_309___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_309__RX_DCOC_RANGE_309___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_309__RX_DCOC_RES_I_309___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_309__RX_DCOC_RES_I_309___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_309__RX_DCOC_RES_Q_309___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_309__RX_DCOC_RES_Q_309___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_309___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_309___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_310 (0x005FC4D8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_310___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_310___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_310__RX_DCOC_RANGE_310___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_310__RX_DCOC_RES_I_310___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_310__RX_DCOC_RES_Q_310___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_310__RX_DCOC_RANGE_310___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_310__RX_DCOC_RANGE_310___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_310__RX_DCOC_RES_I_310___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_310__RX_DCOC_RES_I_310___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_310__RX_DCOC_RES_Q_310___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_310__RX_DCOC_RES_Q_310___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_310___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_310___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_311 (0x005FC4DC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_311___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_311___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_311__RX_DCOC_RANGE_311___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_311__RX_DCOC_RES_I_311___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_311__RX_DCOC_RES_Q_311___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_311__RX_DCOC_RANGE_311___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_311__RX_DCOC_RANGE_311___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_311__RX_DCOC_RES_I_311___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_311__RX_DCOC_RES_I_311___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_311__RX_DCOC_RES_Q_311___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_311__RX_DCOC_RES_Q_311___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_311___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_311___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_312 (0x005FC4E0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_312___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_312___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_312__RX_DCOC_RANGE_312___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_312__RX_DCOC_RES_I_312___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_312__RX_DCOC_RES_Q_312___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_312__RX_DCOC_RANGE_312___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_312__RX_DCOC_RANGE_312___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_312__RX_DCOC_RES_I_312___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_312__RX_DCOC_RES_I_312___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_312__RX_DCOC_RES_Q_312___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_312__RX_DCOC_RES_Q_312___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_312___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_312___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_313 (0x005FC4E4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_313___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_313___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_313__RX_DCOC_RANGE_313___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_313__RX_DCOC_RES_I_313___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_313__RX_DCOC_RES_Q_313___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_313__RX_DCOC_RANGE_313___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_313__RX_DCOC_RANGE_313___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_313__RX_DCOC_RES_I_313___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_313__RX_DCOC_RES_I_313___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_313__RX_DCOC_RES_Q_313___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_313__RX_DCOC_RES_Q_313___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_313___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_313___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_314 (0x005FC4E8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_314___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_314___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_314__RX_DCOC_RANGE_314___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_314__RX_DCOC_RES_I_314___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_314__RX_DCOC_RES_Q_314___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_314__RX_DCOC_RANGE_314___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_314__RX_DCOC_RANGE_314___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_314__RX_DCOC_RES_I_314___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_314__RX_DCOC_RES_I_314___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_314__RX_DCOC_RES_Q_314___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_314__RX_DCOC_RES_Q_314___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_314___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_314___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_315 (0x005FC4EC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_315___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_315___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_315__RX_DCOC_RANGE_315___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_315__RX_DCOC_RES_I_315___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_315__RX_DCOC_RES_Q_315___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_315__RX_DCOC_RANGE_315___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_315__RX_DCOC_RANGE_315___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_315__RX_DCOC_RES_I_315___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_315__RX_DCOC_RES_I_315___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_315__RX_DCOC_RES_Q_315___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_315__RX_DCOC_RES_Q_315___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_315___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_315___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_316 (0x005FC4F0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_316___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_316___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_316__RX_DCOC_RANGE_316___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_316__RX_DCOC_RES_I_316___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_316__RX_DCOC_RES_Q_316___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_316__RX_DCOC_RANGE_316___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_316__RX_DCOC_RANGE_316___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_316__RX_DCOC_RES_I_316___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_316__RX_DCOC_RES_I_316___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_316__RX_DCOC_RES_Q_316___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_316__RX_DCOC_RES_Q_316___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_316___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_316___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_317 (0x005FC4F4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_317___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_317___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_317__RX_DCOC_RANGE_317___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_317__RX_DCOC_RES_I_317___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_317__RX_DCOC_RES_Q_317___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_317__RX_DCOC_RANGE_317___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_317__RX_DCOC_RANGE_317___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_317__RX_DCOC_RES_I_317___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_317__RX_DCOC_RES_I_317___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_317__RX_DCOC_RES_Q_317___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_317__RX_DCOC_RES_Q_317___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_317___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_317___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_318 (0x005FC4F8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_318___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_318___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_318__RX_DCOC_RANGE_318___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_318__RX_DCOC_RES_I_318___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_318__RX_DCOC_RES_Q_318___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_318__RX_DCOC_RANGE_318___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_318__RX_DCOC_RANGE_318___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_318__RX_DCOC_RES_I_318___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_318__RX_DCOC_RES_I_318___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_318__RX_DCOC_RES_Q_318___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_318__RX_DCOC_RES_Q_318___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_318___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_318___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_319 (0x005FC4FC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_319___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_319___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_319__RX_DCOC_RANGE_319___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_319__RX_DCOC_RES_I_319___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_319__RX_DCOC_RES_Q_319___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_319__RX_DCOC_RANGE_319___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_319__RX_DCOC_RANGE_319___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_319__RX_DCOC_RES_I_319___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_319__RX_DCOC_RES_I_319___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_319__RX_DCOC_RES_Q_319___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_319__RX_DCOC_RES_Q_319___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_319___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_319___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_320 (0x005FC500) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_320___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_320___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_320__RX_DCOC_RANGE_320___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_320__RX_DCOC_RES_I_320___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_320__RX_DCOC_RES_Q_320___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_320__RX_DCOC_RANGE_320___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_320__RX_DCOC_RANGE_320___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_320__RX_DCOC_RES_I_320___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_320__RX_DCOC_RES_I_320___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_320__RX_DCOC_RES_Q_320___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_320__RX_DCOC_RES_Q_320___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_320___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_320___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_321 (0x005FC504) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_321___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_321___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_321__RX_DCOC_RANGE_321___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_321__RX_DCOC_RES_I_321___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_321__RX_DCOC_RES_Q_321___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_321__RX_DCOC_RANGE_321___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_321__RX_DCOC_RANGE_321___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_321__RX_DCOC_RES_I_321___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_321__RX_DCOC_RES_I_321___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_321__RX_DCOC_RES_Q_321___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_321__RX_DCOC_RES_Q_321___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_321___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_321___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_322 (0x005FC508) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_322___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_322___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_322__RX_DCOC_RANGE_322___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_322__RX_DCOC_RES_I_322___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_322__RX_DCOC_RES_Q_322___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_322__RX_DCOC_RANGE_322___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_322__RX_DCOC_RANGE_322___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_322__RX_DCOC_RES_I_322___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_322__RX_DCOC_RES_I_322___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_322__RX_DCOC_RES_Q_322___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_322__RX_DCOC_RES_Q_322___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_322___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_322___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_323 (0x005FC50C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_323___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_323___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_323__RX_DCOC_RANGE_323___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_323__RX_DCOC_RES_I_323___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_323__RX_DCOC_RES_Q_323___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_323__RX_DCOC_RANGE_323___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_323__RX_DCOC_RANGE_323___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_323__RX_DCOC_RES_I_323___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_323__RX_DCOC_RES_I_323___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_323__RX_DCOC_RES_Q_323___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_323__RX_DCOC_RES_Q_323___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_323___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_323___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_324 (0x005FC510) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_324___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_324___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_324__RX_DCOC_RANGE_324___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_324__RX_DCOC_RES_I_324___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_324__RX_DCOC_RES_Q_324___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_324__RX_DCOC_RANGE_324___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_324__RX_DCOC_RANGE_324___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_324__RX_DCOC_RES_I_324___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_324__RX_DCOC_RES_I_324___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_324__RX_DCOC_RES_Q_324___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_324__RX_DCOC_RES_Q_324___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_324___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_324___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_325 (0x005FC514) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_325___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_325___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_325__RX_DCOC_RANGE_325___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_325__RX_DCOC_RES_I_325___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_325__RX_DCOC_RES_Q_325___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_325__RX_DCOC_RANGE_325___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_325__RX_DCOC_RANGE_325___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_325__RX_DCOC_RES_I_325___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_325__RX_DCOC_RES_I_325___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_325__RX_DCOC_RES_Q_325___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_325__RX_DCOC_RES_Q_325___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_325___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_325___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_326 (0x005FC518) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_326___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_326___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_326__RX_DCOC_RANGE_326___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_326__RX_DCOC_RES_I_326___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_326__RX_DCOC_RES_Q_326___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_326__RX_DCOC_RANGE_326___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_326__RX_DCOC_RANGE_326___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_326__RX_DCOC_RES_I_326___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_326__RX_DCOC_RES_I_326___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_326__RX_DCOC_RES_Q_326___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_326__RX_DCOC_RES_Q_326___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_326___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_326___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_327 (0x005FC51C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_327___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_327___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_327__RX_DCOC_RANGE_327___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_327__RX_DCOC_RES_I_327___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_327__RX_DCOC_RES_Q_327___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_327__RX_DCOC_RANGE_327___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_327__RX_DCOC_RANGE_327___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_327__RX_DCOC_RES_I_327___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_327__RX_DCOC_RES_I_327___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_327__RX_DCOC_RES_Q_327___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_327__RX_DCOC_RES_Q_327___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_327___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_327___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_328 (0x005FC520) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_328___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_328___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_328__RX_DCOC_RANGE_328___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_328__RX_DCOC_RES_I_328___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_328__RX_DCOC_RES_Q_328___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_328__RX_DCOC_RANGE_328___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_328__RX_DCOC_RANGE_328___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_328__RX_DCOC_RES_I_328___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_328__RX_DCOC_RES_I_328___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_328__RX_DCOC_RES_Q_328___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_328__RX_DCOC_RES_Q_328___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_328___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_328___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_329 (0x005FC524) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_329___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_329___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_329__RX_DCOC_RANGE_329___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_329__RX_DCOC_RES_I_329___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_329__RX_DCOC_RES_Q_329___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_329__RX_DCOC_RANGE_329___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_329__RX_DCOC_RANGE_329___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_329__RX_DCOC_RES_I_329___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_329__RX_DCOC_RES_I_329___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_329__RX_DCOC_RES_Q_329___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_329__RX_DCOC_RES_Q_329___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_329___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_329___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_330 (0x005FC528) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_330___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_330___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_330__RX_DCOC_RANGE_330___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_330__RX_DCOC_RES_I_330___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_330__RX_DCOC_RES_Q_330___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_330__RX_DCOC_RANGE_330___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_330__RX_DCOC_RANGE_330___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_330__RX_DCOC_RES_I_330___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_330__RX_DCOC_RES_I_330___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_330__RX_DCOC_RES_Q_330___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_330__RX_DCOC_RES_Q_330___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_330___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_330___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_331 (0x005FC52C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_331___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_331___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_331__RX_DCOC_RANGE_331___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_331__RX_DCOC_RES_I_331___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_331__RX_DCOC_RES_Q_331___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_331__RX_DCOC_RANGE_331___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_331__RX_DCOC_RANGE_331___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_331__RX_DCOC_RES_I_331___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_331__RX_DCOC_RES_I_331___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_331__RX_DCOC_RES_Q_331___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_331__RX_DCOC_RES_Q_331___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_331___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_331___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_332 (0x005FC530) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_332___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_332___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_332__RX_DCOC_RANGE_332___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_332__RX_DCOC_RES_I_332___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_332__RX_DCOC_RES_Q_332___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_332__RX_DCOC_RANGE_332___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_332__RX_DCOC_RANGE_332___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_332__RX_DCOC_RES_I_332___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_332__RX_DCOC_RES_I_332___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_332__RX_DCOC_RES_Q_332___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_332__RX_DCOC_RES_Q_332___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_332___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_332___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_333 (0x005FC534) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_333___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_333___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_333__RX_DCOC_RANGE_333___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_333__RX_DCOC_RES_I_333___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_333__RX_DCOC_RES_Q_333___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_333__RX_DCOC_RANGE_333___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_333__RX_DCOC_RANGE_333___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_333__RX_DCOC_RES_I_333___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_333__RX_DCOC_RES_I_333___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_333__RX_DCOC_RES_Q_333___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_333__RX_DCOC_RES_Q_333___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_333___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_333___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_334 (0x005FC538) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_334___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_334___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_334__RX_DCOC_RANGE_334___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_334__RX_DCOC_RES_I_334___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_334__RX_DCOC_RES_Q_334___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_334__RX_DCOC_RANGE_334___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_334__RX_DCOC_RANGE_334___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_334__RX_DCOC_RES_I_334___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_334__RX_DCOC_RES_I_334___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_334__RX_DCOC_RES_Q_334___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_334__RX_DCOC_RES_Q_334___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_334___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_334___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_335 (0x005FC53C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_335___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_335___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_335__RX_DCOC_RANGE_335___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_335__RX_DCOC_RES_I_335___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_335__RX_DCOC_RES_Q_335___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_335__RX_DCOC_RANGE_335___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_335__RX_DCOC_RANGE_335___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_335__RX_DCOC_RES_I_335___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_335__RX_DCOC_RES_I_335___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_335__RX_DCOC_RES_Q_335___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_335__RX_DCOC_RES_Q_335___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_335___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_335___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_336 (0x005FC540) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_336___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_336___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_336__RX_DCOC_RANGE_336___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_336__RX_DCOC_RES_I_336___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_336__RX_DCOC_RES_Q_336___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_336__RX_DCOC_RANGE_336___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_336__RX_DCOC_RANGE_336___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_336__RX_DCOC_RES_I_336___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_336__RX_DCOC_RES_I_336___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_336__RX_DCOC_RES_Q_336___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_336__RX_DCOC_RES_Q_336___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_336___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_336___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_337 (0x005FC544) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_337___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_337___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_337__RX_DCOC_RANGE_337___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_337__RX_DCOC_RES_I_337___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_337__RX_DCOC_RES_Q_337___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_337__RX_DCOC_RANGE_337___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_337__RX_DCOC_RANGE_337___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_337__RX_DCOC_RES_I_337___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_337__RX_DCOC_RES_I_337___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_337__RX_DCOC_RES_Q_337___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_337__RX_DCOC_RES_Q_337___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_337___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_337___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_338 (0x005FC548) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_338___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_338___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_338__RX_DCOC_RANGE_338___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_338__RX_DCOC_RES_I_338___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_338__RX_DCOC_RES_Q_338___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_338__RX_DCOC_RANGE_338___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_338__RX_DCOC_RANGE_338___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_338__RX_DCOC_RES_I_338___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_338__RX_DCOC_RES_I_338___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_338__RX_DCOC_RES_Q_338___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_338__RX_DCOC_RES_Q_338___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_338___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_338___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_339 (0x005FC54C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_339___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_339___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_339__RX_DCOC_RANGE_339___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_339__RX_DCOC_RES_I_339___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_339__RX_DCOC_RES_Q_339___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_339__RX_DCOC_RANGE_339___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_339__RX_DCOC_RANGE_339___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_339__RX_DCOC_RES_I_339___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_339__RX_DCOC_RES_I_339___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_339__RX_DCOC_RES_Q_339___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_339__RX_DCOC_RES_Q_339___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_339___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_339___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_340 (0x005FC550) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_340___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_340___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_340__RX_DCOC_RANGE_340___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_340__RX_DCOC_RES_I_340___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_340__RX_DCOC_RES_Q_340___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_340__RX_DCOC_RANGE_340___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_340__RX_DCOC_RANGE_340___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_340__RX_DCOC_RES_I_340___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_340__RX_DCOC_RES_I_340___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_340__RX_DCOC_RES_Q_340___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_340__RX_DCOC_RES_Q_340___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_340___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_340___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_341 (0x005FC554) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_341___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_341___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_341__RX_DCOC_RANGE_341___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_341__RX_DCOC_RES_I_341___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_341__RX_DCOC_RES_Q_341___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_341__RX_DCOC_RANGE_341___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_341__RX_DCOC_RANGE_341___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_341__RX_DCOC_RES_I_341___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_341__RX_DCOC_RES_I_341___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_341__RX_DCOC_RES_Q_341___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_341__RX_DCOC_RES_Q_341___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_341___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_341___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_342 (0x005FC558) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_342___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_342___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_342__RX_DCOC_RANGE_342___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_342__RX_DCOC_RES_I_342___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_342__RX_DCOC_RES_Q_342___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_342__RX_DCOC_RANGE_342___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_342__RX_DCOC_RANGE_342___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_342__RX_DCOC_RES_I_342___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_342__RX_DCOC_RES_I_342___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_342__RX_DCOC_RES_Q_342___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_342__RX_DCOC_RES_Q_342___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_342___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_342___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_343 (0x005FC55C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_343___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_343___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_343__RX_DCOC_RANGE_343___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_343__RX_DCOC_RES_I_343___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_343__RX_DCOC_RES_Q_343___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_343__RX_DCOC_RANGE_343___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_343__RX_DCOC_RANGE_343___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_343__RX_DCOC_RES_I_343___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_343__RX_DCOC_RES_I_343___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_343__RX_DCOC_RES_Q_343___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_343__RX_DCOC_RES_Q_343___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_343___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_343___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_344 (0x005FC560) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_344___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_344___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_344__RX_DCOC_RANGE_344___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_344__RX_DCOC_RES_I_344___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_344__RX_DCOC_RES_Q_344___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_344__RX_DCOC_RANGE_344___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_344__RX_DCOC_RANGE_344___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_344__RX_DCOC_RES_I_344___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_344__RX_DCOC_RES_I_344___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_344__RX_DCOC_RES_Q_344___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_344__RX_DCOC_RES_Q_344___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_344___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_344___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_345 (0x005FC564) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_345___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_345___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_345__RX_DCOC_RANGE_345___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_345__RX_DCOC_RES_I_345___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_345__RX_DCOC_RES_Q_345___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_345__RX_DCOC_RANGE_345___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_345__RX_DCOC_RANGE_345___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_345__RX_DCOC_RES_I_345___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_345__RX_DCOC_RES_I_345___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_345__RX_DCOC_RES_Q_345___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_345__RX_DCOC_RES_Q_345___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_345___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_345___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_346 (0x005FC568) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_346___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_346___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_346__RX_DCOC_RANGE_346___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_346__RX_DCOC_RES_I_346___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_346__RX_DCOC_RES_Q_346___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_346__RX_DCOC_RANGE_346___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_346__RX_DCOC_RANGE_346___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_346__RX_DCOC_RES_I_346___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_346__RX_DCOC_RES_I_346___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_346__RX_DCOC_RES_Q_346___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_346__RX_DCOC_RES_Q_346___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_346___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_346___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_347 (0x005FC56C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_347___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_347___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_347__RX_DCOC_RANGE_347___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_347__RX_DCOC_RES_I_347___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_347__RX_DCOC_RES_Q_347___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_347__RX_DCOC_RANGE_347___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_347__RX_DCOC_RANGE_347___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_347__RX_DCOC_RES_I_347___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_347__RX_DCOC_RES_I_347___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_347__RX_DCOC_RES_Q_347___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_347__RX_DCOC_RES_Q_347___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_347___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_347___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_348 (0x005FC570) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_348___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_348___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_348__RX_DCOC_RANGE_348___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_348__RX_DCOC_RES_I_348___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_348__RX_DCOC_RES_Q_348___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_348__RX_DCOC_RANGE_348___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_348__RX_DCOC_RANGE_348___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_348__RX_DCOC_RES_I_348___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_348__RX_DCOC_RES_I_348___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_348__RX_DCOC_RES_Q_348___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_348__RX_DCOC_RES_Q_348___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_348___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_348___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_349 (0x005FC574) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_349___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_349___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_349__RX_DCOC_RANGE_349___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_349__RX_DCOC_RES_I_349___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_349__RX_DCOC_RES_Q_349___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_349__RX_DCOC_RANGE_349___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_349__RX_DCOC_RANGE_349___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_349__RX_DCOC_RES_I_349___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_349__RX_DCOC_RES_I_349___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_349__RX_DCOC_RES_Q_349___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_349__RX_DCOC_RES_Q_349___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_349___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_349___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_350 (0x005FC578) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_350___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_350___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_350__RX_DCOC_RANGE_350___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_350__RX_DCOC_RES_I_350___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_350__RX_DCOC_RES_Q_350___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_350__RX_DCOC_RANGE_350___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_350__RX_DCOC_RANGE_350___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_350__RX_DCOC_RES_I_350___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_350__RX_DCOC_RES_I_350___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_350__RX_DCOC_RES_Q_350___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_350__RX_DCOC_RES_Q_350___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_350___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_350___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_351 (0x005FC57C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_351___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_351___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_351__RX_DCOC_RANGE_351___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_351__RX_DCOC_RES_I_351___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_351__RX_DCOC_RES_Q_351___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_351__RX_DCOC_RANGE_351___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_351__RX_DCOC_RANGE_351___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_351__RX_DCOC_RES_I_351___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_351__RX_DCOC_RES_I_351___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_351__RX_DCOC_RES_Q_351___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_351__RX_DCOC_RES_Q_351___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_351___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_351___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_352 (0x005FC580) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_352___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_352___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_352__RX_DCOC_RANGE_352___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_352__RX_DCOC_RES_I_352___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_352__RX_DCOC_RES_Q_352___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_352__RX_DCOC_RANGE_352___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_352__RX_DCOC_RANGE_352___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_352__RX_DCOC_RES_I_352___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_352__RX_DCOC_RES_I_352___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_352__RX_DCOC_RES_Q_352___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_352__RX_DCOC_RES_Q_352___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_352___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_352___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_353 (0x005FC584) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_353___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_353___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_353__RX_DCOC_RANGE_353___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_353__RX_DCOC_RES_I_353___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_353__RX_DCOC_RES_Q_353___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_353__RX_DCOC_RANGE_353___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_353__RX_DCOC_RANGE_353___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_353__RX_DCOC_RES_I_353___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_353__RX_DCOC_RES_I_353___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_353__RX_DCOC_RES_Q_353___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_353__RX_DCOC_RES_Q_353___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_353___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_353___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_354 (0x005FC588) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_354___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_354___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_354__RX_DCOC_RANGE_354___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_354__RX_DCOC_RES_I_354___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_354__RX_DCOC_RES_Q_354___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_354__RX_DCOC_RANGE_354___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_354__RX_DCOC_RANGE_354___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_354__RX_DCOC_RES_I_354___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_354__RX_DCOC_RES_I_354___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_354__RX_DCOC_RES_Q_354___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_354__RX_DCOC_RES_Q_354___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_354___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_354___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_355 (0x005FC58C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_355___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_355___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_355__RX_DCOC_RANGE_355___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_355__RX_DCOC_RES_I_355___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_355__RX_DCOC_RES_Q_355___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_355__RX_DCOC_RANGE_355___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_355__RX_DCOC_RANGE_355___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_355__RX_DCOC_RES_I_355___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_355__RX_DCOC_RES_I_355___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_355__RX_DCOC_RES_Q_355___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_355__RX_DCOC_RES_Q_355___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_355___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_355___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_356 (0x005FC590) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_356___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_356___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_356__RX_DCOC_RANGE_356___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_356__RX_DCOC_RES_I_356___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_356__RX_DCOC_RES_Q_356___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_356__RX_DCOC_RANGE_356___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_356__RX_DCOC_RANGE_356___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_356__RX_DCOC_RES_I_356___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_356__RX_DCOC_RES_I_356___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_356__RX_DCOC_RES_Q_356___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_356__RX_DCOC_RES_Q_356___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_356___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_356___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_357 (0x005FC594) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_357___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_357___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_357__RX_DCOC_RANGE_357___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_357__RX_DCOC_RES_I_357___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_357__RX_DCOC_RES_Q_357___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_357__RX_DCOC_RANGE_357___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_357__RX_DCOC_RANGE_357___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_357__RX_DCOC_RES_I_357___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_357__RX_DCOC_RES_I_357___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_357__RX_DCOC_RES_Q_357___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_357__RX_DCOC_RES_Q_357___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_357___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_357___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_358 (0x005FC598) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_358___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_358___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_358__RX_DCOC_RANGE_358___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_358__RX_DCOC_RES_I_358___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_358__RX_DCOC_RES_Q_358___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_358__RX_DCOC_RANGE_358___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_358__RX_DCOC_RANGE_358___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_358__RX_DCOC_RES_I_358___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_358__RX_DCOC_RES_I_358___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_358__RX_DCOC_RES_Q_358___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_358__RX_DCOC_RES_Q_358___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_358___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_358___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_359 (0x005FC59C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_359___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_359___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_359__RX_DCOC_RANGE_359___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_359__RX_DCOC_RES_I_359___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_359__RX_DCOC_RES_Q_359___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_359__RX_DCOC_RANGE_359___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_359__RX_DCOC_RANGE_359___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_359__RX_DCOC_RES_I_359___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_359__RX_DCOC_RES_I_359___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_359__RX_DCOC_RES_Q_359___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_359__RX_DCOC_RES_Q_359___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_359___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_359___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_360 (0x005FC5A0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_360___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_360___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_360__RX_DCOC_RANGE_360___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_360__RX_DCOC_RES_I_360___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_360__RX_DCOC_RES_Q_360___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_360__RX_DCOC_RANGE_360___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_360__RX_DCOC_RANGE_360___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_360__RX_DCOC_RES_I_360___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_360__RX_DCOC_RES_I_360___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_360__RX_DCOC_RES_Q_360___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_360__RX_DCOC_RES_Q_360___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_360___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_360___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_361 (0x005FC5A4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_361___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_361___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_361__RX_DCOC_RANGE_361___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_361__RX_DCOC_RES_I_361___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_361__RX_DCOC_RES_Q_361___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_361__RX_DCOC_RANGE_361___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_361__RX_DCOC_RANGE_361___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_361__RX_DCOC_RES_I_361___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_361__RX_DCOC_RES_I_361___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_361__RX_DCOC_RES_Q_361___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_361__RX_DCOC_RES_Q_361___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_361___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_361___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_362 (0x005FC5A8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_362___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_362___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_362__RX_DCOC_RANGE_362___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_362__RX_DCOC_RES_I_362___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_362__RX_DCOC_RES_Q_362___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_362__RX_DCOC_RANGE_362___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_362__RX_DCOC_RANGE_362___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_362__RX_DCOC_RES_I_362___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_362__RX_DCOC_RES_I_362___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_362__RX_DCOC_RES_Q_362___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_362__RX_DCOC_RES_Q_362___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_362___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_362___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_363 (0x005FC5AC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_363___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_363___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_363__RX_DCOC_RANGE_363___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_363__RX_DCOC_RES_I_363___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_363__RX_DCOC_RES_Q_363___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_363__RX_DCOC_RANGE_363___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_363__RX_DCOC_RANGE_363___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_363__RX_DCOC_RES_I_363___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_363__RX_DCOC_RES_I_363___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_363__RX_DCOC_RES_Q_363___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_363__RX_DCOC_RES_Q_363___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_363___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_363___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_364 (0x005FC5B0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_364___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_364___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_364__RX_DCOC_RANGE_364___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_364__RX_DCOC_RES_I_364___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_364__RX_DCOC_RES_Q_364___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_364__RX_DCOC_RANGE_364___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_364__RX_DCOC_RANGE_364___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_364__RX_DCOC_RES_I_364___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_364__RX_DCOC_RES_I_364___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_364__RX_DCOC_RES_Q_364___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_364__RX_DCOC_RES_Q_364___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_364___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_364___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_365 (0x005FC5B4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_365___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_365___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_365__RX_DCOC_RANGE_365___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_365__RX_DCOC_RES_I_365___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_365__RX_DCOC_RES_Q_365___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_365__RX_DCOC_RANGE_365___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_365__RX_DCOC_RANGE_365___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_365__RX_DCOC_RES_I_365___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_365__RX_DCOC_RES_I_365___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_365__RX_DCOC_RES_Q_365___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_365__RX_DCOC_RES_Q_365___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_365___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_365___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_366 (0x005FC5B8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_366___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_366___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_366__RX_DCOC_RANGE_366___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_366__RX_DCOC_RES_I_366___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_366__RX_DCOC_RES_Q_366___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_366__RX_DCOC_RANGE_366___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_366__RX_DCOC_RANGE_366___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_366__RX_DCOC_RES_I_366___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_366__RX_DCOC_RES_I_366___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_366__RX_DCOC_RES_Q_366___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_366__RX_DCOC_RES_Q_366___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_366___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_366___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_367 (0x005FC5BC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_367___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_367___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_367__RX_DCOC_RANGE_367___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_367__RX_DCOC_RES_I_367___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_367__RX_DCOC_RES_Q_367___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_367__RX_DCOC_RANGE_367___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_367__RX_DCOC_RANGE_367___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_367__RX_DCOC_RES_I_367___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_367__RX_DCOC_RES_I_367___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_367__RX_DCOC_RES_Q_367___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_367__RX_DCOC_RES_Q_367___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_367___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_367___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_368 (0x005FC5C0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_368___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_368___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_368__RX_DCOC_RANGE_368___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_368__RX_DCOC_RES_I_368___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_368__RX_DCOC_RES_Q_368___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_368__RX_DCOC_RANGE_368___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_368__RX_DCOC_RANGE_368___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_368__RX_DCOC_RES_I_368___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_368__RX_DCOC_RES_I_368___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_368__RX_DCOC_RES_Q_368___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_368__RX_DCOC_RES_Q_368___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_368___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_368___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_369 (0x005FC5C4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_369___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_369___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_369__RX_DCOC_RANGE_369___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_369__RX_DCOC_RES_I_369___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_369__RX_DCOC_RES_Q_369___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_369__RX_DCOC_RANGE_369___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_369__RX_DCOC_RANGE_369___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_369__RX_DCOC_RES_I_369___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_369__RX_DCOC_RES_I_369___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_369__RX_DCOC_RES_Q_369___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_369__RX_DCOC_RES_Q_369___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_369___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_369___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_370 (0x005FC5C8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_370___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_370___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_370__RX_DCOC_RANGE_370___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_370__RX_DCOC_RES_I_370___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_370__RX_DCOC_RES_Q_370___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_370__RX_DCOC_RANGE_370___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_370__RX_DCOC_RANGE_370___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_370__RX_DCOC_RES_I_370___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_370__RX_DCOC_RES_I_370___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_370__RX_DCOC_RES_Q_370___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_370__RX_DCOC_RES_Q_370___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_370___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_370___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_371 (0x005FC5CC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_371___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_371___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_371__RX_DCOC_RANGE_371___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_371__RX_DCOC_RES_I_371___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_371__RX_DCOC_RES_Q_371___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_371__RX_DCOC_RANGE_371___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_371__RX_DCOC_RANGE_371___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_371__RX_DCOC_RES_I_371___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_371__RX_DCOC_RES_I_371___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_371__RX_DCOC_RES_Q_371___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_371__RX_DCOC_RES_Q_371___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_371___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_371___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_372 (0x005FC5D0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_372___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_372___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_372__RX_DCOC_RANGE_372___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_372__RX_DCOC_RES_I_372___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_372__RX_DCOC_RES_Q_372___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_372__RX_DCOC_RANGE_372___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_372__RX_DCOC_RANGE_372___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_372__RX_DCOC_RES_I_372___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_372__RX_DCOC_RES_I_372___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_372__RX_DCOC_RES_Q_372___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_372__RX_DCOC_RES_Q_372___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_372___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_372___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_373 (0x005FC5D4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_373___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_373___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_373__RX_DCOC_RANGE_373___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_373__RX_DCOC_RES_I_373___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_373__RX_DCOC_RES_Q_373___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_373__RX_DCOC_RANGE_373___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_373__RX_DCOC_RANGE_373___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_373__RX_DCOC_RES_I_373___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_373__RX_DCOC_RES_I_373___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_373__RX_DCOC_RES_Q_373___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_373__RX_DCOC_RES_Q_373___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_373___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_373___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_374 (0x005FC5D8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_374___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_374___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_374__RX_DCOC_RANGE_374___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_374__RX_DCOC_RES_I_374___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_374__RX_DCOC_RES_Q_374___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_374__RX_DCOC_RANGE_374___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_374__RX_DCOC_RANGE_374___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_374__RX_DCOC_RES_I_374___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_374__RX_DCOC_RES_I_374___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_374__RX_DCOC_RES_Q_374___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_374__RX_DCOC_RES_Q_374___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_374___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_374___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_375 (0x005FC5DC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_375___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_375___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_375__RX_DCOC_RANGE_375___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_375__RX_DCOC_RES_I_375___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_375__RX_DCOC_RES_Q_375___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_375__RX_DCOC_RANGE_375___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_375__RX_DCOC_RANGE_375___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_375__RX_DCOC_RES_I_375___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_375__RX_DCOC_RES_I_375___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_375__RX_DCOC_RES_Q_375___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_375__RX_DCOC_RES_Q_375___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_375___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_375___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_376 (0x005FC5E0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_376___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_376___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_376__RX_DCOC_RANGE_376___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_376__RX_DCOC_RES_I_376___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_376__RX_DCOC_RES_Q_376___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_376__RX_DCOC_RANGE_376___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_376__RX_DCOC_RANGE_376___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_376__RX_DCOC_RES_I_376___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_376__RX_DCOC_RES_I_376___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_376__RX_DCOC_RES_Q_376___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_376__RX_DCOC_RES_Q_376___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_376___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_376___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_377 (0x005FC5E4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_377___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_377___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_377__RX_DCOC_RANGE_377___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_377__RX_DCOC_RES_I_377___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_377__RX_DCOC_RES_Q_377___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_377__RX_DCOC_RANGE_377___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_377__RX_DCOC_RANGE_377___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_377__RX_DCOC_RES_I_377___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_377__RX_DCOC_RES_I_377___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_377__RX_DCOC_RES_Q_377___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_377__RX_DCOC_RES_Q_377___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_377___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_377___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_378 (0x005FC5E8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_378___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_378___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_378__RX_DCOC_RANGE_378___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_378__RX_DCOC_RES_I_378___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_378__RX_DCOC_RES_Q_378___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_378__RX_DCOC_RANGE_378___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_378__RX_DCOC_RANGE_378___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_378__RX_DCOC_RES_I_378___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_378__RX_DCOC_RES_I_378___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_378__RX_DCOC_RES_Q_378___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_378__RX_DCOC_RES_Q_378___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_378___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_378___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_379 (0x005FC5EC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_379___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_379___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_379__RX_DCOC_RANGE_379___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_379__RX_DCOC_RES_I_379___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_379__RX_DCOC_RES_Q_379___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_379__RX_DCOC_RANGE_379___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_379__RX_DCOC_RANGE_379___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_379__RX_DCOC_RES_I_379___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_379__RX_DCOC_RES_I_379___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_379__RX_DCOC_RES_Q_379___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_379__RX_DCOC_RES_Q_379___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_379___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_379___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_380 (0x005FC5F0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_380___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_380___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_380__RX_DCOC_RANGE_380___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_380__RX_DCOC_RES_I_380___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_380__RX_DCOC_RES_Q_380___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_380__RX_DCOC_RANGE_380___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_380__RX_DCOC_RANGE_380___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_380__RX_DCOC_RES_I_380___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_380__RX_DCOC_RES_I_380___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_380__RX_DCOC_RES_Q_380___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_380__RX_DCOC_RES_Q_380___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_380___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_380___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_381 (0x005FC5F4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_381___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_381___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_381__RX_DCOC_RANGE_381___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_381__RX_DCOC_RES_I_381___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_381__RX_DCOC_RES_Q_381___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_381__RX_DCOC_RANGE_381___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_381__RX_DCOC_RANGE_381___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_381__RX_DCOC_RES_I_381___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_381__RX_DCOC_RES_I_381___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_381__RX_DCOC_RES_Q_381___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_381__RX_DCOC_RES_Q_381___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_381___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_381___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_382 (0x005FC5F8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_382___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_382___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_382__RX_DCOC_RANGE_382___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_382__RX_DCOC_RES_I_382___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_382__RX_DCOC_RES_Q_382___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_382__RX_DCOC_RANGE_382___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_382__RX_DCOC_RANGE_382___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_382__RX_DCOC_RES_I_382___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_382__RX_DCOC_RES_I_382___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_382__RX_DCOC_RES_Q_382___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_382__RX_DCOC_RES_Q_382___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_382___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_382___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_383 (0x005FC5FC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_383___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_383___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_383__RX_DCOC_RANGE_383___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_383__RX_DCOC_RES_I_383___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_383__RX_DCOC_RES_Q_383___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_383__RX_DCOC_RANGE_383___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_383__RX_DCOC_RANGE_383___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_383__RX_DCOC_RES_I_383___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_383__RX_DCOC_RES_I_383___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_383__RX_DCOC_RES_Q_383___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_383__RX_DCOC_RES_Q_383___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_383___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_383___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_384 (0x005FC600) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_384___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_384___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_384__RX_DCOC_RANGE_384___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_384__RX_DCOC_RES_I_384___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_384__RX_DCOC_RES_Q_384___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_384__RX_DCOC_RANGE_384___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_384__RX_DCOC_RANGE_384___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_384__RX_DCOC_RES_I_384___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_384__RX_DCOC_RES_I_384___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_384__RX_DCOC_RES_Q_384___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_384__RX_DCOC_RES_Q_384___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_384___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_384___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_385 (0x005FC604) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_385___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_385___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_385__RX_DCOC_RANGE_385___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_385__RX_DCOC_RES_I_385___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_385__RX_DCOC_RES_Q_385___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_385__RX_DCOC_RANGE_385___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_385__RX_DCOC_RANGE_385___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_385__RX_DCOC_RES_I_385___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_385__RX_DCOC_RES_I_385___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_385__RX_DCOC_RES_Q_385___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_385__RX_DCOC_RES_Q_385___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_385___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_385___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_386 (0x005FC608) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_386___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_386___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_386__RX_DCOC_RANGE_386___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_386__RX_DCOC_RES_I_386___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_386__RX_DCOC_RES_Q_386___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_386__RX_DCOC_RANGE_386___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_386__RX_DCOC_RANGE_386___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_386__RX_DCOC_RES_I_386___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_386__RX_DCOC_RES_I_386___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_386__RX_DCOC_RES_Q_386___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_386__RX_DCOC_RES_Q_386___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_386___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_386___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_387 (0x005FC60C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_387___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_387___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_387__RX_DCOC_RANGE_387___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_387__RX_DCOC_RES_I_387___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_387__RX_DCOC_RES_Q_387___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_387__RX_DCOC_RANGE_387___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_387__RX_DCOC_RANGE_387___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_387__RX_DCOC_RES_I_387___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_387__RX_DCOC_RES_I_387___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_387__RX_DCOC_RES_Q_387___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_387__RX_DCOC_RES_Q_387___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_387___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_387___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_388 (0x005FC610) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_388___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_388___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_388__RX_DCOC_RANGE_388___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_388__RX_DCOC_RES_I_388___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_388__RX_DCOC_RES_Q_388___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_388__RX_DCOC_RANGE_388___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_388__RX_DCOC_RANGE_388___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_388__RX_DCOC_RES_I_388___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_388__RX_DCOC_RES_I_388___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_388__RX_DCOC_RES_Q_388___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_388__RX_DCOC_RES_Q_388___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_388___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_388___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_389 (0x005FC614) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_389___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_389___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_389__RX_DCOC_RANGE_389___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_389__RX_DCOC_RES_I_389___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_389__RX_DCOC_RES_Q_389___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_389__RX_DCOC_RANGE_389___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_389__RX_DCOC_RANGE_389___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_389__RX_DCOC_RES_I_389___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_389__RX_DCOC_RES_I_389___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_389__RX_DCOC_RES_Q_389___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_389__RX_DCOC_RES_Q_389___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_389___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_389___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_390 (0x005FC618) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_390___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_390___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_390__RX_DCOC_RANGE_390___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_390__RX_DCOC_RES_I_390___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_390__RX_DCOC_RES_Q_390___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_390__RX_DCOC_RANGE_390___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_390__RX_DCOC_RANGE_390___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_390__RX_DCOC_RES_I_390___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_390__RX_DCOC_RES_I_390___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_390__RX_DCOC_RES_Q_390___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_390__RX_DCOC_RES_Q_390___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_390___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_390___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_391 (0x005FC61C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_391___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_391___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_391__RX_DCOC_RANGE_391___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_391__RX_DCOC_RES_I_391___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_391__RX_DCOC_RES_Q_391___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_391__RX_DCOC_RANGE_391___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_391__RX_DCOC_RANGE_391___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_391__RX_DCOC_RES_I_391___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_391__RX_DCOC_RES_I_391___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_391__RX_DCOC_RES_Q_391___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_391__RX_DCOC_RES_Q_391___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_391___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_391___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_392 (0x005FC620) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_392___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_392___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_392__RX_DCOC_RANGE_392___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_392__RX_DCOC_RES_I_392___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_392__RX_DCOC_RES_Q_392___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_392__RX_DCOC_RANGE_392___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_392__RX_DCOC_RANGE_392___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_392__RX_DCOC_RES_I_392___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_392__RX_DCOC_RES_I_392___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_392__RX_DCOC_RES_Q_392___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_392__RX_DCOC_RES_Q_392___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_392___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_392___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_393 (0x005FC624) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_393___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_393___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_393__RX_DCOC_RANGE_393___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_393__RX_DCOC_RES_I_393___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_393__RX_DCOC_RES_Q_393___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_393__RX_DCOC_RANGE_393___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_393__RX_DCOC_RANGE_393___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_393__RX_DCOC_RES_I_393___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_393__RX_DCOC_RES_I_393___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_393__RX_DCOC_RES_Q_393___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_393__RX_DCOC_RES_Q_393___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_393___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_393___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_394 (0x005FC628) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_394___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_394___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_394__RX_DCOC_RANGE_394___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_394__RX_DCOC_RES_I_394___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_394__RX_DCOC_RES_Q_394___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_394__RX_DCOC_RANGE_394___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_394__RX_DCOC_RANGE_394___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_394__RX_DCOC_RES_I_394___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_394__RX_DCOC_RES_I_394___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_394__RX_DCOC_RES_Q_394___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_394__RX_DCOC_RES_Q_394___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_394___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_394___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_395 (0x005FC62C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_395___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_395___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_395__RX_DCOC_RANGE_395___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_395__RX_DCOC_RES_I_395___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_395__RX_DCOC_RES_Q_395___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_395__RX_DCOC_RANGE_395___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_395__RX_DCOC_RANGE_395___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_395__RX_DCOC_RES_I_395___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_395__RX_DCOC_RES_I_395___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_395__RX_DCOC_RES_Q_395___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_395__RX_DCOC_RES_Q_395___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_395___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_395___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_396 (0x005FC630) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_396___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_396___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_396__RX_DCOC_RANGE_396___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_396__RX_DCOC_RES_I_396___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_396__RX_DCOC_RES_Q_396___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_396__RX_DCOC_RANGE_396___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_396__RX_DCOC_RANGE_396___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_396__RX_DCOC_RES_I_396___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_396__RX_DCOC_RES_I_396___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_396__RX_DCOC_RES_Q_396___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_396__RX_DCOC_RES_Q_396___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_396___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_396___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_397 (0x005FC634) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_397___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_397___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_397__RX_DCOC_RANGE_397___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_397__RX_DCOC_RES_I_397___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_397__RX_DCOC_RES_Q_397___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_397__RX_DCOC_RANGE_397___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_397__RX_DCOC_RANGE_397___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_397__RX_DCOC_RES_I_397___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_397__RX_DCOC_RES_I_397___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_397__RX_DCOC_RES_Q_397___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_397__RX_DCOC_RES_Q_397___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_397___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_397___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_398 (0x005FC638) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_398___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_398___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_398__RX_DCOC_RANGE_398___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_398__RX_DCOC_RES_I_398___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_398__RX_DCOC_RES_Q_398___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_398__RX_DCOC_RANGE_398___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_398__RX_DCOC_RANGE_398___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_398__RX_DCOC_RES_I_398___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_398__RX_DCOC_RES_I_398___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_398__RX_DCOC_RES_Q_398___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_398__RX_DCOC_RES_Q_398___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_398___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_398___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_399 (0x005FC63C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_399___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_399___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_399__RX_DCOC_RANGE_399___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_399__RX_DCOC_RES_I_399___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_399__RX_DCOC_RES_Q_399___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_399__RX_DCOC_RANGE_399___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_399__RX_DCOC_RANGE_399___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_399__RX_DCOC_RES_I_399___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_399__RX_DCOC_RES_I_399___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_399__RX_DCOC_RES_Q_399___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_399__RX_DCOC_RES_Q_399___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_399___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_399___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_400 (0x005FC640) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_400___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_400___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_400__RX_DCOC_RANGE_400___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_400__RX_DCOC_RES_I_400___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_400__RX_DCOC_RES_Q_400___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_400__RX_DCOC_RANGE_400___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_400__RX_DCOC_RANGE_400___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_400__RX_DCOC_RES_I_400___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_400__RX_DCOC_RES_I_400___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_400__RX_DCOC_RES_Q_400___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_400__RX_DCOC_RES_Q_400___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_400___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_400___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_401 (0x005FC644) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_401___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_401___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_401__RX_DCOC_RANGE_401___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_401__RX_DCOC_RES_I_401___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_401__RX_DCOC_RES_Q_401___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_401__RX_DCOC_RANGE_401___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_401__RX_DCOC_RANGE_401___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_401__RX_DCOC_RES_I_401___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_401__RX_DCOC_RES_I_401___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_401__RX_DCOC_RES_Q_401___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_401__RX_DCOC_RES_Q_401___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_401___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_401___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_402 (0x005FC648) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_402___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_402___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_402__RX_DCOC_RANGE_402___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_402__RX_DCOC_RES_I_402___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_402__RX_DCOC_RES_Q_402___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_402__RX_DCOC_RANGE_402___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_402__RX_DCOC_RANGE_402___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_402__RX_DCOC_RES_I_402___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_402__RX_DCOC_RES_I_402___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_402__RX_DCOC_RES_Q_402___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_402__RX_DCOC_RES_Q_402___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_402___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_402___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_403 (0x005FC64C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_403___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_403___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_403__RX_DCOC_RANGE_403___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_403__RX_DCOC_RES_I_403___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_403__RX_DCOC_RES_Q_403___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_403__RX_DCOC_RANGE_403___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_403__RX_DCOC_RANGE_403___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_403__RX_DCOC_RES_I_403___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_403__RX_DCOC_RES_I_403___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_403__RX_DCOC_RES_Q_403___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_403__RX_DCOC_RES_Q_403___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_403___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_403___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_404 (0x005FC650) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_404___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_404___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_404__RX_DCOC_RANGE_404___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_404__RX_DCOC_RES_I_404___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_404__RX_DCOC_RES_Q_404___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_404__RX_DCOC_RANGE_404___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_404__RX_DCOC_RANGE_404___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_404__RX_DCOC_RES_I_404___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_404__RX_DCOC_RES_I_404___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_404__RX_DCOC_RES_Q_404___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_404__RX_DCOC_RES_Q_404___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_404___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_404___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_405 (0x005FC654) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_405___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_405___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_405__RX_DCOC_RANGE_405___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_405__RX_DCOC_RES_I_405___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_405__RX_DCOC_RES_Q_405___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_405__RX_DCOC_RANGE_405___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_405__RX_DCOC_RANGE_405___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_405__RX_DCOC_RES_I_405___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_405__RX_DCOC_RES_I_405___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_405__RX_DCOC_RES_Q_405___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_405__RX_DCOC_RES_Q_405___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_405___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_405___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_406 (0x005FC658) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_406___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_406___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_406__RX_DCOC_RANGE_406___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_406__RX_DCOC_RES_I_406___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_406__RX_DCOC_RES_Q_406___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_406__RX_DCOC_RANGE_406___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_406__RX_DCOC_RANGE_406___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_406__RX_DCOC_RES_I_406___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_406__RX_DCOC_RES_I_406___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_406__RX_DCOC_RES_Q_406___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_406__RX_DCOC_RES_Q_406___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_406___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_406___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_407 (0x005FC65C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_407___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_407___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_407__RX_DCOC_RANGE_407___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_407__RX_DCOC_RES_I_407___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_407__RX_DCOC_RES_Q_407___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_407__RX_DCOC_RANGE_407___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_407__RX_DCOC_RANGE_407___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_407__RX_DCOC_RES_I_407___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_407__RX_DCOC_RES_I_407___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_407__RX_DCOC_RES_Q_407___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_407__RX_DCOC_RES_Q_407___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_407___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_407___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_408 (0x005FC660) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_408___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_408___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_408__RX_DCOC_RANGE_408___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_408__RX_DCOC_RES_I_408___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_408__RX_DCOC_RES_Q_408___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_408__RX_DCOC_RANGE_408___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_408__RX_DCOC_RANGE_408___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_408__RX_DCOC_RES_I_408___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_408__RX_DCOC_RES_I_408___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_408__RX_DCOC_RES_Q_408___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_408__RX_DCOC_RES_Q_408___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_408___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_408___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_409 (0x005FC664) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_409___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_409___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_409__RX_DCOC_RANGE_409___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_409__RX_DCOC_RES_I_409___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_409__RX_DCOC_RES_Q_409___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_409__RX_DCOC_RANGE_409___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_409__RX_DCOC_RANGE_409___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_409__RX_DCOC_RES_I_409___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_409__RX_DCOC_RES_I_409___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_409__RX_DCOC_RES_Q_409___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_409__RX_DCOC_RES_Q_409___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_409___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_409___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_410 (0x005FC668) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_410___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_410___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_410__RX_DCOC_RANGE_410___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_410__RX_DCOC_RES_I_410___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_410__RX_DCOC_RES_Q_410___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_410__RX_DCOC_RANGE_410___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_410__RX_DCOC_RANGE_410___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_410__RX_DCOC_RES_I_410___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_410__RX_DCOC_RES_I_410___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_410__RX_DCOC_RES_Q_410___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_410__RX_DCOC_RES_Q_410___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_410___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_410___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_411 (0x005FC66C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_411___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_411___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_411__RX_DCOC_RANGE_411___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_411__RX_DCOC_RES_I_411___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_411__RX_DCOC_RES_Q_411___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_411__RX_DCOC_RANGE_411___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_411__RX_DCOC_RANGE_411___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_411__RX_DCOC_RES_I_411___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_411__RX_DCOC_RES_I_411___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_411__RX_DCOC_RES_Q_411___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_411__RX_DCOC_RES_Q_411___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_411___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_411___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_412 (0x005FC670) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_412___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_412___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_412__RX_DCOC_RANGE_412___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_412__RX_DCOC_RES_I_412___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_412__RX_DCOC_RES_Q_412___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_412__RX_DCOC_RANGE_412___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_412__RX_DCOC_RANGE_412___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_412__RX_DCOC_RES_I_412___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_412__RX_DCOC_RES_I_412___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_412__RX_DCOC_RES_Q_412___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_412__RX_DCOC_RES_Q_412___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_412___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_412___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_413 (0x005FC674) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_413___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_413___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_413__RX_DCOC_RANGE_413___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_413__RX_DCOC_RES_I_413___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_413__RX_DCOC_RES_Q_413___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_413__RX_DCOC_RANGE_413___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_413__RX_DCOC_RANGE_413___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_413__RX_DCOC_RES_I_413___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_413__RX_DCOC_RES_I_413___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_413__RX_DCOC_RES_Q_413___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_413__RX_DCOC_RES_Q_413___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_413___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_413___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_414 (0x005FC678) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_414___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_414___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_414__RX_DCOC_RANGE_414___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_414__RX_DCOC_RES_I_414___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_414__RX_DCOC_RES_Q_414___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_414__RX_DCOC_RANGE_414___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_414__RX_DCOC_RANGE_414___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_414__RX_DCOC_RES_I_414___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_414__RX_DCOC_RES_I_414___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_414__RX_DCOC_RES_Q_414___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_414__RX_DCOC_RES_Q_414___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_414___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_414___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_415 (0x005FC67C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_415___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_415___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_415__RX_DCOC_RANGE_415___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_415__RX_DCOC_RES_I_415___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_415__RX_DCOC_RES_Q_415___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_415__RX_DCOC_RANGE_415___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_415__RX_DCOC_RANGE_415___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_415__RX_DCOC_RES_I_415___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_415__RX_DCOC_RES_I_415___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_415__RX_DCOC_RES_Q_415___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_415__RX_DCOC_RES_Q_415___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_415___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_415___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_416 (0x005FC680) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_416___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_416___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_416__RX_DCOC_RANGE_416___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_416__RX_DCOC_RES_I_416___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_416__RX_DCOC_RES_Q_416___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_416__RX_DCOC_RANGE_416___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_416__RX_DCOC_RANGE_416___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_416__RX_DCOC_RES_I_416___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_416__RX_DCOC_RES_I_416___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_416__RX_DCOC_RES_Q_416___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_416__RX_DCOC_RES_Q_416___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_416___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_416___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_417 (0x005FC684) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_417___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_417___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_417__RX_DCOC_RANGE_417___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_417__RX_DCOC_RES_I_417___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_417__RX_DCOC_RES_Q_417___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_417__RX_DCOC_RANGE_417___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_417__RX_DCOC_RANGE_417___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_417__RX_DCOC_RES_I_417___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_417__RX_DCOC_RES_I_417___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_417__RX_DCOC_RES_Q_417___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_417__RX_DCOC_RES_Q_417___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_417___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_417___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_418 (0x005FC688) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_418___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_418___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_418__RX_DCOC_RANGE_418___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_418__RX_DCOC_RES_I_418___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_418__RX_DCOC_RES_Q_418___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_418__RX_DCOC_RANGE_418___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_418__RX_DCOC_RANGE_418___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_418__RX_DCOC_RES_I_418___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_418__RX_DCOC_RES_I_418___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_418__RX_DCOC_RES_Q_418___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_418__RX_DCOC_RES_Q_418___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_418___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_418___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_419 (0x005FC68C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_419___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_419___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_419__RX_DCOC_RANGE_419___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_419__RX_DCOC_RES_I_419___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_419__RX_DCOC_RES_Q_419___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_419__RX_DCOC_RANGE_419___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_419__RX_DCOC_RANGE_419___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_419__RX_DCOC_RES_I_419___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_419__RX_DCOC_RES_I_419___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_419__RX_DCOC_RES_Q_419___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_419__RX_DCOC_RES_Q_419___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_419___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_419___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_420 (0x005FC690) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_420___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_420___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_420__RX_DCOC_RANGE_420___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_420__RX_DCOC_RES_I_420___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_420__RX_DCOC_RES_Q_420___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_420__RX_DCOC_RANGE_420___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_420__RX_DCOC_RANGE_420___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_420__RX_DCOC_RES_I_420___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_420__RX_DCOC_RES_I_420___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_420__RX_DCOC_RES_Q_420___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_420__RX_DCOC_RES_Q_420___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_420___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_420___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_421 (0x005FC694) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_421___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_421___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_421__RX_DCOC_RANGE_421___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_421__RX_DCOC_RES_I_421___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_421__RX_DCOC_RES_Q_421___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_421__RX_DCOC_RANGE_421___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_421__RX_DCOC_RANGE_421___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_421__RX_DCOC_RES_I_421___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_421__RX_DCOC_RES_I_421___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_421__RX_DCOC_RES_Q_421___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_421__RX_DCOC_RES_Q_421___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_421___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_421___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_422 (0x005FC698) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_422___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_422___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_422__RX_DCOC_RANGE_422___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_422__RX_DCOC_RES_I_422___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_422__RX_DCOC_RES_Q_422___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_422__RX_DCOC_RANGE_422___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_422__RX_DCOC_RANGE_422___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_422__RX_DCOC_RES_I_422___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_422__RX_DCOC_RES_I_422___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_422__RX_DCOC_RES_Q_422___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_422__RX_DCOC_RES_Q_422___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_422___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_422___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_423 (0x005FC69C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_423___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_423___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_423__RX_DCOC_RANGE_423___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_423__RX_DCOC_RES_I_423___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_423__RX_DCOC_RES_Q_423___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_423__RX_DCOC_RANGE_423___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_423__RX_DCOC_RANGE_423___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_423__RX_DCOC_RES_I_423___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_423__RX_DCOC_RES_I_423___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_423__RX_DCOC_RES_Q_423___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_423__RX_DCOC_RES_Q_423___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_423___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_423___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_424 (0x005FC6A0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_424___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_424___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_424__RX_DCOC_RANGE_424___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_424__RX_DCOC_RES_I_424___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_424__RX_DCOC_RES_Q_424___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_424__RX_DCOC_RANGE_424___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_424__RX_DCOC_RANGE_424___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_424__RX_DCOC_RES_I_424___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_424__RX_DCOC_RES_I_424___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_424__RX_DCOC_RES_Q_424___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_424__RX_DCOC_RES_Q_424___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_424___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_424___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_425 (0x005FC6A4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_425___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_425___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_425__RX_DCOC_RANGE_425___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_425__RX_DCOC_RES_I_425___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_425__RX_DCOC_RES_Q_425___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_425__RX_DCOC_RANGE_425___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_425__RX_DCOC_RANGE_425___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_425__RX_DCOC_RES_I_425___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_425__RX_DCOC_RES_I_425___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_425__RX_DCOC_RES_Q_425___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_425__RX_DCOC_RES_Q_425___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_425___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_425___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_426 (0x005FC6A8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_426___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_426___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_426__RX_DCOC_RANGE_426___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_426__RX_DCOC_RES_I_426___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_426__RX_DCOC_RES_Q_426___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_426__RX_DCOC_RANGE_426___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_426__RX_DCOC_RANGE_426___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_426__RX_DCOC_RES_I_426___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_426__RX_DCOC_RES_I_426___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_426__RX_DCOC_RES_Q_426___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_426__RX_DCOC_RES_Q_426___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_426___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_426___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_427 (0x005FC6AC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_427___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_427___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_427__RX_DCOC_RANGE_427___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_427__RX_DCOC_RES_I_427___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_427__RX_DCOC_RES_Q_427___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_427__RX_DCOC_RANGE_427___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_427__RX_DCOC_RANGE_427___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_427__RX_DCOC_RES_I_427___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_427__RX_DCOC_RES_I_427___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_427__RX_DCOC_RES_Q_427___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_427__RX_DCOC_RES_Q_427___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_427___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_427___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_428 (0x005FC6B0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_428___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_428___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_428__RX_DCOC_RANGE_428___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_428__RX_DCOC_RES_I_428___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_428__RX_DCOC_RES_Q_428___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_428__RX_DCOC_RANGE_428___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_428__RX_DCOC_RANGE_428___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_428__RX_DCOC_RES_I_428___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_428__RX_DCOC_RES_I_428___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_428__RX_DCOC_RES_Q_428___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_428__RX_DCOC_RES_Q_428___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_428___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_428___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_429 (0x005FC6B4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_429___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_429___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_429__RX_DCOC_RANGE_429___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_429__RX_DCOC_RES_I_429___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_429__RX_DCOC_RES_Q_429___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_429__RX_DCOC_RANGE_429___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_429__RX_DCOC_RANGE_429___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_429__RX_DCOC_RES_I_429___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_429__RX_DCOC_RES_I_429___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_429__RX_DCOC_RES_Q_429___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_429__RX_DCOC_RES_Q_429___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_429___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_429___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_430 (0x005FC6B8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_430___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_430___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_430__RX_DCOC_RANGE_430___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_430__RX_DCOC_RES_I_430___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_430__RX_DCOC_RES_Q_430___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_430__RX_DCOC_RANGE_430___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_430__RX_DCOC_RANGE_430___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_430__RX_DCOC_RES_I_430___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_430__RX_DCOC_RES_I_430___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_430__RX_DCOC_RES_Q_430___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_430__RX_DCOC_RES_Q_430___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_430___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_430___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_431 (0x005FC6BC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_431___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_431___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_431__RX_DCOC_RANGE_431___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_431__RX_DCOC_RES_I_431___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_431__RX_DCOC_RES_Q_431___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_431__RX_DCOC_RANGE_431___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_431__RX_DCOC_RANGE_431___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_431__RX_DCOC_RES_I_431___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_431__RX_DCOC_RES_I_431___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_431__RX_DCOC_RES_Q_431___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_431__RX_DCOC_RES_Q_431___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_431___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_431___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_432 (0x005FC6C0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_432___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_432___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_432__RX_DCOC_RANGE_432___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_432__RX_DCOC_RES_I_432___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_432__RX_DCOC_RES_Q_432___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_432__RX_DCOC_RANGE_432___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_432__RX_DCOC_RANGE_432___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_432__RX_DCOC_RES_I_432___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_432__RX_DCOC_RES_I_432___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_432__RX_DCOC_RES_Q_432___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_432__RX_DCOC_RES_Q_432___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_432___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_432___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_433 (0x005FC6C4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_433___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_433___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_433__RX_DCOC_RANGE_433___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_433__RX_DCOC_RES_I_433___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_433__RX_DCOC_RES_Q_433___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_433__RX_DCOC_RANGE_433___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_433__RX_DCOC_RANGE_433___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_433__RX_DCOC_RES_I_433___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_433__RX_DCOC_RES_I_433___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_433__RX_DCOC_RES_Q_433___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_433__RX_DCOC_RES_Q_433___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_433___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_433___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_434 (0x005FC6C8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_434___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_434___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_434__RX_DCOC_RANGE_434___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_434__RX_DCOC_RES_I_434___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_434__RX_DCOC_RES_Q_434___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_434__RX_DCOC_RANGE_434___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_434__RX_DCOC_RANGE_434___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_434__RX_DCOC_RES_I_434___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_434__RX_DCOC_RES_I_434___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_434__RX_DCOC_RES_Q_434___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_434__RX_DCOC_RES_Q_434___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_434___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_434___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_435 (0x005FC6CC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_435___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_435___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_435__RX_DCOC_RANGE_435___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_435__RX_DCOC_RES_I_435___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_435__RX_DCOC_RES_Q_435___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_435__RX_DCOC_RANGE_435___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_435__RX_DCOC_RANGE_435___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_435__RX_DCOC_RES_I_435___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_435__RX_DCOC_RES_I_435___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_435__RX_DCOC_RES_Q_435___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_435__RX_DCOC_RES_Q_435___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_435___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_435___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_436 (0x005FC6D0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_436___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_436___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_436__RX_DCOC_RANGE_436___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_436__RX_DCOC_RES_I_436___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_436__RX_DCOC_RES_Q_436___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_436__RX_DCOC_RANGE_436___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_436__RX_DCOC_RANGE_436___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_436__RX_DCOC_RES_I_436___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_436__RX_DCOC_RES_I_436___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_436__RX_DCOC_RES_Q_436___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_436__RX_DCOC_RES_Q_436___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_436___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_436___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_437 (0x005FC6D4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_437___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_437___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_437__RX_DCOC_RANGE_437___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_437__RX_DCOC_RES_I_437___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_437__RX_DCOC_RES_Q_437___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_437__RX_DCOC_RANGE_437___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_437__RX_DCOC_RANGE_437___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_437__RX_DCOC_RES_I_437___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_437__RX_DCOC_RES_I_437___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_437__RX_DCOC_RES_Q_437___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_437__RX_DCOC_RES_Q_437___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_437___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_437___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_438 (0x005FC6D8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_438___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_438___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_438__RX_DCOC_RANGE_438___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_438__RX_DCOC_RES_I_438___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_438__RX_DCOC_RES_Q_438___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_438__RX_DCOC_RANGE_438___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_438__RX_DCOC_RANGE_438___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_438__RX_DCOC_RES_I_438___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_438__RX_DCOC_RES_I_438___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_438__RX_DCOC_RES_Q_438___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_438__RX_DCOC_RES_Q_438___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_438___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_438___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_439 (0x005FC6DC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_439___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_439___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_439__RX_DCOC_RANGE_439___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_439__RX_DCOC_RES_I_439___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_439__RX_DCOC_RES_Q_439___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_439__RX_DCOC_RANGE_439___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_439__RX_DCOC_RANGE_439___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_439__RX_DCOC_RES_I_439___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_439__RX_DCOC_RES_I_439___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_439__RX_DCOC_RES_Q_439___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_439__RX_DCOC_RES_Q_439___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_439___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_439___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_440 (0x005FC6E0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_440___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_440___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_440__RX_DCOC_RANGE_440___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_440__RX_DCOC_RES_I_440___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_440__RX_DCOC_RES_Q_440___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_440__RX_DCOC_RANGE_440___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_440__RX_DCOC_RANGE_440___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_440__RX_DCOC_RES_I_440___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_440__RX_DCOC_RES_I_440___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_440__RX_DCOC_RES_Q_440___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_440__RX_DCOC_RES_Q_440___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_440___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_440___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_441 (0x005FC6E4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_441___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_441___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_441__RX_DCOC_RANGE_441___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_441__RX_DCOC_RES_I_441___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_441__RX_DCOC_RES_Q_441___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_441__RX_DCOC_RANGE_441___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_441__RX_DCOC_RANGE_441___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_441__RX_DCOC_RES_I_441___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_441__RX_DCOC_RES_I_441___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_441__RX_DCOC_RES_Q_441___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_441__RX_DCOC_RES_Q_441___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_441___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_441___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_442 (0x005FC6E8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_442___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_442___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_442__RX_DCOC_RANGE_442___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_442__RX_DCOC_RES_I_442___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_442__RX_DCOC_RES_Q_442___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_442__RX_DCOC_RANGE_442___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_442__RX_DCOC_RANGE_442___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_442__RX_DCOC_RES_I_442___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_442__RX_DCOC_RES_I_442___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_442__RX_DCOC_RES_Q_442___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_442__RX_DCOC_RES_Q_442___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_442___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_442___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_443 (0x005FC6EC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_443___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_443___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_443__RX_DCOC_RANGE_443___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_443__RX_DCOC_RES_I_443___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_443__RX_DCOC_RES_Q_443___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_443__RX_DCOC_RANGE_443___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_443__RX_DCOC_RANGE_443___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_443__RX_DCOC_RES_I_443___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_443__RX_DCOC_RES_I_443___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_443__RX_DCOC_RES_Q_443___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_443__RX_DCOC_RES_Q_443___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_443___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_443___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_444 (0x005FC6F0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_444___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_444___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_444__RX_DCOC_RANGE_444___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_444__RX_DCOC_RES_I_444___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_444__RX_DCOC_RES_Q_444___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_444__RX_DCOC_RANGE_444___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_444__RX_DCOC_RANGE_444___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_444__RX_DCOC_RES_I_444___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_444__RX_DCOC_RES_I_444___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_444__RX_DCOC_RES_Q_444___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_444__RX_DCOC_RES_Q_444___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_444___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_444___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_445 (0x005FC6F4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_445___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_445___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_445__RX_DCOC_RANGE_445___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_445__RX_DCOC_RES_I_445___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_445__RX_DCOC_RES_Q_445___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_445__RX_DCOC_RANGE_445___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_445__RX_DCOC_RANGE_445___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_445__RX_DCOC_RES_I_445___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_445__RX_DCOC_RES_I_445___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_445__RX_DCOC_RES_Q_445___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_445__RX_DCOC_RES_Q_445___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_445___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_445___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_446 (0x005FC6F8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_446___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_446___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_446__RX_DCOC_RANGE_446___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_446__RX_DCOC_RES_I_446___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_446__RX_DCOC_RES_Q_446___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_446__RX_DCOC_RANGE_446___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_446__RX_DCOC_RANGE_446___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_446__RX_DCOC_RES_I_446___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_446__RX_DCOC_RES_I_446___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_446__RX_DCOC_RES_Q_446___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_446__RX_DCOC_RES_Q_446___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_446___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_446___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_447 (0x005FC6FC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_447___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_447___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_447__RX_DCOC_RANGE_447___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_447__RX_DCOC_RES_I_447___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_447__RX_DCOC_RES_Q_447___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_447__RX_DCOC_RANGE_447___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_447__RX_DCOC_RANGE_447___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_447__RX_DCOC_RES_I_447___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_447__RX_DCOC_RES_I_447___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_447__RX_DCOC_RES_Q_447___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_447__RX_DCOC_RES_Q_447___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_447___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_447___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_448 (0x005FC700) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_448___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_448___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_448__RX_DCOC_RANGE_448___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_448__RX_DCOC_RES_I_448___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_448__RX_DCOC_RES_Q_448___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_448__RX_DCOC_RANGE_448___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_448__RX_DCOC_RANGE_448___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_448__RX_DCOC_RES_I_448___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_448__RX_DCOC_RES_I_448___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_448__RX_DCOC_RES_Q_448___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_448__RX_DCOC_RES_Q_448___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_448___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_448___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_449 (0x005FC704) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_449___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_449___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_449__RX_DCOC_RANGE_449___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_449__RX_DCOC_RES_I_449___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_449__RX_DCOC_RES_Q_449___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_449__RX_DCOC_RANGE_449___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_449__RX_DCOC_RANGE_449___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_449__RX_DCOC_RES_I_449___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_449__RX_DCOC_RES_I_449___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_449__RX_DCOC_RES_Q_449___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_449__RX_DCOC_RES_Q_449___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_449___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_449___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_450 (0x005FC708) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_450___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_450___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_450__RX_DCOC_RANGE_450___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_450__RX_DCOC_RES_I_450___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_450__RX_DCOC_RES_Q_450___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_450__RX_DCOC_RANGE_450___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_450__RX_DCOC_RANGE_450___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_450__RX_DCOC_RES_I_450___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_450__RX_DCOC_RES_I_450___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_450__RX_DCOC_RES_Q_450___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_450__RX_DCOC_RES_Q_450___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_450___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_450___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_451 (0x005FC70C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_451___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_451___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_451__RX_DCOC_RANGE_451___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_451__RX_DCOC_RES_I_451___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_451__RX_DCOC_RES_Q_451___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_451__RX_DCOC_RANGE_451___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_451__RX_DCOC_RANGE_451___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_451__RX_DCOC_RES_I_451___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_451__RX_DCOC_RES_I_451___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_451__RX_DCOC_RES_Q_451___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_451__RX_DCOC_RES_Q_451___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_451___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_451___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_452 (0x005FC710) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_452___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_452___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_452__RX_DCOC_RANGE_452___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_452__RX_DCOC_RES_I_452___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_452__RX_DCOC_RES_Q_452___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_452__RX_DCOC_RANGE_452___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_452__RX_DCOC_RANGE_452___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_452__RX_DCOC_RES_I_452___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_452__RX_DCOC_RES_I_452___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_452__RX_DCOC_RES_Q_452___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_452__RX_DCOC_RES_Q_452___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_452___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_452___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_453 (0x005FC714) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_453___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_453___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_453__RX_DCOC_RANGE_453___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_453__RX_DCOC_RES_I_453___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_453__RX_DCOC_RES_Q_453___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_453__RX_DCOC_RANGE_453___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_453__RX_DCOC_RANGE_453___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_453__RX_DCOC_RES_I_453___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_453__RX_DCOC_RES_I_453___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_453__RX_DCOC_RES_Q_453___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_453__RX_DCOC_RES_Q_453___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_453___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_453___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_454 (0x005FC718) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_454___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_454___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_454__RX_DCOC_RANGE_454___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_454__RX_DCOC_RES_I_454___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_454__RX_DCOC_RES_Q_454___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_454__RX_DCOC_RANGE_454___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_454__RX_DCOC_RANGE_454___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_454__RX_DCOC_RES_I_454___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_454__RX_DCOC_RES_I_454___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_454__RX_DCOC_RES_Q_454___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_454__RX_DCOC_RES_Q_454___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_454___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_454___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_455 (0x005FC71C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_455___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_455___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_455__RX_DCOC_RANGE_455___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_455__RX_DCOC_RES_I_455___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_455__RX_DCOC_RES_Q_455___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_455__RX_DCOC_RANGE_455___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_455__RX_DCOC_RANGE_455___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_455__RX_DCOC_RES_I_455___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_455__RX_DCOC_RES_I_455___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_455__RX_DCOC_RES_Q_455___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_455__RX_DCOC_RES_Q_455___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_455___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_455___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_456 (0x005FC720) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_456___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_456___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_456__RX_DCOC_RANGE_456___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_456__RX_DCOC_RES_I_456___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_456__RX_DCOC_RES_Q_456___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_456__RX_DCOC_RANGE_456___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_456__RX_DCOC_RANGE_456___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_456__RX_DCOC_RES_I_456___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_456__RX_DCOC_RES_I_456___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_456__RX_DCOC_RES_Q_456___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_456__RX_DCOC_RES_Q_456___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_456___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_456___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_457 (0x005FC724) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_457___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_457___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_457__RX_DCOC_RANGE_457___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_457__RX_DCOC_RES_I_457___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_457__RX_DCOC_RES_Q_457___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_457__RX_DCOC_RANGE_457___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_457__RX_DCOC_RANGE_457___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_457__RX_DCOC_RES_I_457___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_457__RX_DCOC_RES_I_457___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_457__RX_DCOC_RES_Q_457___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_457__RX_DCOC_RES_Q_457___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_457___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_457___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_458 (0x005FC728) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_458___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_458___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_458__RX_DCOC_RANGE_458___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_458__RX_DCOC_RES_I_458___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_458__RX_DCOC_RES_Q_458___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_458__RX_DCOC_RANGE_458___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_458__RX_DCOC_RANGE_458___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_458__RX_DCOC_RES_I_458___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_458__RX_DCOC_RES_I_458___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_458__RX_DCOC_RES_Q_458___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_458__RX_DCOC_RES_Q_458___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_458___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_458___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_459 (0x005FC72C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_459___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_459___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_459__RX_DCOC_RANGE_459___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_459__RX_DCOC_RES_I_459___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_459__RX_DCOC_RES_Q_459___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_459__RX_DCOC_RANGE_459___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_459__RX_DCOC_RANGE_459___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_459__RX_DCOC_RES_I_459___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_459__RX_DCOC_RES_I_459___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_459__RX_DCOC_RES_Q_459___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_459__RX_DCOC_RES_Q_459___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_459___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_459___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_460 (0x005FC730) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_460___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_460___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_460__RX_DCOC_RANGE_460___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_460__RX_DCOC_RES_I_460___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_460__RX_DCOC_RES_Q_460___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_460__RX_DCOC_RANGE_460___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_460__RX_DCOC_RANGE_460___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_460__RX_DCOC_RES_I_460___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_460__RX_DCOC_RES_I_460___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_460__RX_DCOC_RES_Q_460___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_460__RX_DCOC_RES_Q_460___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_460___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_460___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_461 (0x005FC734) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_461___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_461___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_461__RX_DCOC_RANGE_461___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_461__RX_DCOC_RES_I_461___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_461__RX_DCOC_RES_Q_461___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_461__RX_DCOC_RANGE_461___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_461__RX_DCOC_RANGE_461___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_461__RX_DCOC_RES_I_461___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_461__RX_DCOC_RES_I_461___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_461__RX_DCOC_RES_Q_461___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_461__RX_DCOC_RES_Q_461___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_461___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_461___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_462 (0x005FC738) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_462___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_462___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_462__RX_DCOC_RANGE_462___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_462__RX_DCOC_RES_I_462___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_462__RX_DCOC_RES_Q_462___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_462__RX_DCOC_RANGE_462___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_462__RX_DCOC_RANGE_462___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_462__RX_DCOC_RES_I_462___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_462__RX_DCOC_RES_I_462___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_462__RX_DCOC_RES_Q_462___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_462__RX_DCOC_RES_Q_462___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_462___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_462___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_463 (0x005FC73C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_463___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_463___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_463__RX_DCOC_RANGE_463___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_463__RX_DCOC_RES_I_463___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_463__RX_DCOC_RES_Q_463___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_463__RX_DCOC_RANGE_463___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_463__RX_DCOC_RANGE_463___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_463__RX_DCOC_RES_I_463___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_463__RX_DCOC_RES_I_463___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_463__RX_DCOC_RES_Q_463___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_463__RX_DCOC_RES_Q_463___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_463___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_463___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_464 (0x005FC740) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_464___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_464___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_464__RX_DCOC_RANGE_464___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_464__RX_DCOC_RES_I_464___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_464__RX_DCOC_RES_Q_464___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_464__RX_DCOC_RANGE_464___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_464__RX_DCOC_RANGE_464___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_464__RX_DCOC_RES_I_464___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_464__RX_DCOC_RES_I_464___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_464__RX_DCOC_RES_Q_464___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_464__RX_DCOC_RES_Q_464___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_464___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_464___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_465 (0x005FC744) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_465___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_465___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_465__RX_DCOC_RANGE_465___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_465__RX_DCOC_RES_I_465___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_465__RX_DCOC_RES_Q_465___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_465__RX_DCOC_RANGE_465___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_465__RX_DCOC_RANGE_465___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_465__RX_DCOC_RES_I_465___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_465__RX_DCOC_RES_I_465___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_465__RX_DCOC_RES_Q_465___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_465__RX_DCOC_RES_Q_465___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_465___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_465___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_466 (0x005FC748) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_466___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_466___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_466__RX_DCOC_RANGE_466___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_466__RX_DCOC_RES_I_466___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_466__RX_DCOC_RES_Q_466___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_466__RX_DCOC_RANGE_466___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_466__RX_DCOC_RANGE_466___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_466__RX_DCOC_RES_I_466___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_466__RX_DCOC_RES_I_466___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_466__RX_DCOC_RES_Q_466___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_466__RX_DCOC_RES_Q_466___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_466___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_466___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_467 (0x005FC74C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_467___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_467___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_467__RX_DCOC_RANGE_467___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_467__RX_DCOC_RES_I_467___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_467__RX_DCOC_RES_Q_467___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_467__RX_DCOC_RANGE_467___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_467__RX_DCOC_RANGE_467___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_467__RX_DCOC_RES_I_467___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_467__RX_DCOC_RES_I_467___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_467__RX_DCOC_RES_Q_467___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_467__RX_DCOC_RES_Q_467___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_467___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_467___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_468 (0x005FC750) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_468___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_468___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_468__RX_DCOC_RANGE_468___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_468__RX_DCOC_RES_I_468___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_468__RX_DCOC_RES_Q_468___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_468__RX_DCOC_RANGE_468___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_468__RX_DCOC_RANGE_468___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_468__RX_DCOC_RES_I_468___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_468__RX_DCOC_RES_I_468___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_468__RX_DCOC_RES_Q_468___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_468__RX_DCOC_RES_Q_468___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_468___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_468___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_469 (0x005FC754) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_469___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_469___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_469__RX_DCOC_RANGE_469___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_469__RX_DCOC_RES_I_469___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_469__RX_DCOC_RES_Q_469___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_469__RX_DCOC_RANGE_469___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_469__RX_DCOC_RANGE_469___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_469__RX_DCOC_RES_I_469___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_469__RX_DCOC_RES_I_469___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_469__RX_DCOC_RES_Q_469___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_469__RX_DCOC_RES_Q_469___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_469___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_469___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_470 (0x005FC758) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_470___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_470___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_470__RX_DCOC_RANGE_470___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_470__RX_DCOC_RES_I_470___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_470__RX_DCOC_RES_Q_470___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_470__RX_DCOC_RANGE_470___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_470__RX_DCOC_RANGE_470___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_470__RX_DCOC_RES_I_470___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_470__RX_DCOC_RES_I_470___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_470__RX_DCOC_RES_Q_470___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_470__RX_DCOC_RES_Q_470___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_470___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_470___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_471 (0x005FC75C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_471___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_471___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_471__RX_DCOC_RANGE_471___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_471__RX_DCOC_RES_I_471___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_471__RX_DCOC_RES_Q_471___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_471__RX_DCOC_RANGE_471___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_471__RX_DCOC_RANGE_471___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_471__RX_DCOC_RES_I_471___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_471__RX_DCOC_RES_I_471___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_471__RX_DCOC_RES_Q_471___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_471__RX_DCOC_RES_Q_471___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_471___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_471___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_472 (0x005FC760) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_472___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_472___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_472__RX_DCOC_RANGE_472___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_472__RX_DCOC_RES_I_472___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_472__RX_DCOC_RES_Q_472___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_472__RX_DCOC_RANGE_472___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_472__RX_DCOC_RANGE_472___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_472__RX_DCOC_RES_I_472___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_472__RX_DCOC_RES_I_472___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_472__RX_DCOC_RES_Q_472___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_472__RX_DCOC_RES_Q_472___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_472___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_472___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_473 (0x005FC764) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_473___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_473___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_473__RX_DCOC_RANGE_473___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_473__RX_DCOC_RES_I_473___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_473__RX_DCOC_RES_Q_473___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_473__RX_DCOC_RANGE_473___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_473__RX_DCOC_RANGE_473___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_473__RX_DCOC_RES_I_473___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_473__RX_DCOC_RES_I_473___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_473__RX_DCOC_RES_Q_473___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_473__RX_DCOC_RES_Q_473___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_473___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_473___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_474 (0x005FC768) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_474___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_474___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_474__RX_DCOC_RANGE_474___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_474__RX_DCOC_RES_I_474___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_474__RX_DCOC_RES_Q_474___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_474__RX_DCOC_RANGE_474___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_474__RX_DCOC_RANGE_474___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_474__RX_DCOC_RES_I_474___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_474__RX_DCOC_RES_I_474___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_474__RX_DCOC_RES_Q_474___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_474__RX_DCOC_RES_Q_474___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_474___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_474___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_475 (0x005FC76C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_475___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_475___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_475__RX_DCOC_RANGE_475___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_475__RX_DCOC_RES_I_475___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_475__RX_DCOC_RES_Q_475___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_475__RX_DCOC_RANGE_475___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_475__RX_DCOC_RANGE_475___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_475__RX_DCOC_RES_I_475___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_475__RX_DCOC_RES_I_475___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_475__RX_DCOC_RES_Q_475___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_475__RX_DCOC_RES_Q_475___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_475___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_475___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_476 (0x005FC770) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_476___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_476___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_476__RX_DCOC_RANGE_476___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_476__RX_DCOC_RES_I_476___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_476__RX_DCOC_RES_Q_476___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_476__RX_DCOC_RANGE_476___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_476__RX_DCOC_RANGE_476___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_476__RX_DCOC_RES_I_476___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_476__RX_DCOC_RES_I_476___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_476__RX_DCOC_RES_Q_476___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_476__RX_DCOC_RES_Q_476___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_476___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_476___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_477 (0x005FC774) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_477___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_477___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_477__RX_DCOC_RANGE_477___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_477__RX_DCOC_RES_I_477___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_477__RX_DCOC_RES_Q_477___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_477__RX_DCOC_RANGE_477___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_477__RX_DCOC_RANGE_477___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_477__RX_DCOC_RES_I_477___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_477__RX_DCOC_RES_I_477___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_477__RX_DCOC_RES_Q_477___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_477__RX_DCOC_RES_Q_477___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_477___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_477___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_478 (0x005FC778) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_478___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_478___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_478__RX_DCOC_RANGE_478___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_478__RX_DCOC_RES_I_478___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_478__RX_DCOC_RES_Q_478___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_478__RX_DCOC_RANGE_478___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_478__RX_DCOC_RANGE_478___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_478__RX_DCOC_RES_I_478___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_478__RX_DCOC_RES_I_478___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_478__RX_DCOC_RES_Q_478___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_478__RX_DCOC_RES_Q_478___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_478___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_478___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_479 (0x005FC77C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_479___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_479___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_479__RX_DCOC_RANGE_479___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_479__RX_DCOC_RES_I_479___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_479__RX_DCOC_RES_Q_479___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_479__RX_DCOC_RANGE_479___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_479__RX_DCOC_RANGE_479___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_479__RX_DCOC_RES_I_479___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_479__RX_DCOC_RES_I_479___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_479__RX_DCOC_RES_Q_479___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_479__RX_DCOC_RES_Q_479___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_479___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_479___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_480 (0x005FC780) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_480___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_480___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_480__RX_DCOC_RANGE_480___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_480__RX_DCOC_RES_I_480___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_480__RX_DCOC_RES_Q_480___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_480__RX_DCOC_RANGE_480___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_480__RX_DCOC_RANGE_480___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_480__RX_DCOC_RES_I_480___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_480__RX_DCOC_RES_I_480___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_480__RX_DCOC_RES_Q_480___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_480__RX_DCOC_RES_Q_480___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_480___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_480___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_481 (0x005FC784) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_481___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_481___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_481__RX_DCOC_RANGE_481___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_481__RX_DCOC_RES_I_481___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_481__RX_DCOC_RES_Q_481___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_481__RX_DCOC_RANGE_481___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_481__RX_DCOC_RANGE_481___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_481__RX_DCOC_RES_I_481___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_481__RX_DCOC_RES_I_481___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_481__RX_DCOC_RES_Q_481___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_481__RX_DCOC_RES_Q_481___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_481___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_481___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_482 (0x005FC788) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_482___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_482___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_482__RX_DCOC_RANGE_482___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_482__RX_DCOC_RES_I_482___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_482__RX_DCOC_RES_Q_482___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_482__RX_DCOC_RANGE_482___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_482__RX_DCOC_RANGE_482___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_482__RX_DCOC_RES_I_482___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_482__RX_DCOC_RES_I_482___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_482__RX_DCOC_RES_Q_482___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_482__RX_DCOC_RES_Q_482___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_482___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_482___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_483 (0x005FC78C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_483___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_483___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_483__RX_DCOC_RANGE_483___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_483__RX_DCOC_RES_I_483___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_483__RX_DCOC_RES_Q_483___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_483__RX_DCOC_RANGE_483___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_483__RX_DCOC_RANGE_483___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_483__RX_DCOC_RES_I_483___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_483__RX_DCOC_RES_I_483___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_483__RX_DCOC_RES_Q_483___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_483__RX_DCOC_RES_Q_483___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_483___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_483___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_484 (0x005FC790) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_484___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_484___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_484__RX_DCOC_RANGE_484___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_484__RX_DCOC_RES_I_484___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_484__RX_DCOC_RES_Q_484___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_484__RX_DCOC_RANGE_484___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_484__RX_DCOC_RANGE_484___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_484__RX_DCOC_RES_I_484___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_484__RX_DCOC_RES_I_484___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_484__RX_DCOC_RES_Q_484___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_484__RX_DCOC_RES_Q_484___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_484___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_484___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_485 (0x005FC794) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_485___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_485___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_485__RX_DCOC_RANGE_485___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_485__RX_DCOC_RES_I_485___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_485__RX_DCOC_RES_Q_485___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_485__RX_DCOC_RANGE_485___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_485__RX_DCOC_RANGE_485___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_485__RX_DCOC_RES_I_485___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_485__RX_DCOC_RES_I_485___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_485__RX_DCOC_RES_Q_485___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_485__RX_DCOC_RES_Q_485___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_485___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_485___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_486 (0x005FC798) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_486___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_486___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_486__RX_DCOC_RANGE_486___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_486__RX_DCOC_RES_I_486___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_486__RX_DCOC_RES_Q_486___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_486__RX_DCOC_RANGE_486___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_486__RX_DCOC_RANGE_486___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_486__RX_DCOC_RES_I_486___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_486__RX_DCOC_RES_I_486___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_486__RX_DCOC_RES_Q_486___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_486__RX_DCOC_RES_Q_486___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_486___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_486___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_487 (0x005FC79C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_487___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_487___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_487__RX_DCOC_RANGE_487___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_487__RX_DCOC_RES_I_487___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_487__RX_DCOC_RES_Q_487___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_487__RX_DCOC_RANGE_487___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_487__RX_DCOC_RANGE_487___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_487__RX_DCOC_RES_I_487___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_487__RX_DCOC_RES_I_487___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_487__RX_DCOC_RES_Q_487___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_487__RX_DCOC_RES_Q_487___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_487___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_487___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_488 (0x005FC7A0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_488___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_488___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_488__RX_DCOC_RANGE_488___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_488__RX_DCOC_RES_I_488___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_488__RX_DCOC_RES_Q_488___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_488__RX_DCOC_RANGE_488___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_488__RX_DCOC_RANGE_488___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_488__RX_DCOC_RES_I_488___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_488__RX_DCOC_RES_I_488___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_488__RX_DCOC_RES_Q_488___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_488__RX_DCOC_RES_Q_488___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_488___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_488___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_489 (0x005FC7A4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_489___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_489___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_489__RX_DCOC_RANGE_489___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_489__RX_DCOC_RES_I_489___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_489__RX_DCOC_RES_Q_489___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_489__RX_DCOC_RANGE_489___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_489__RX_DCOC_RANGE_489___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_489__RX_DCOC_RES_I_489___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_489__RX_DCOC_RES_I_489___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_489__RX_DCOC_RES_Q_489___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_489__RX_DCOC_RES_Q_489___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_489___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_489___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_490 (0x005FC7A8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_490___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_490___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_490__RX_DCOC_RANGE_490___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_490__RX_DCOC_RES_I_490___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_490__RX_DCOC_RES_Q_490___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_490__RX_DCOC_RANGE_490___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_490__RX_DCOC_RANGE_490___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_490__RX_DCOC_RES_I_490___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_490__RX_DCOC_RES_I_490___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_490__RX_DCOC_RES_Q_490___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_490__RX_DCOC_RES_Q_490___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_490___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_490___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_491 (0x005FC7AC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_491___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_491___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_491__RX_DCOC_RANGE_491___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_491__RX_DCOC_RES_I_491___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_491__RX_DCOC_RES_Q_491___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_491__RX_DCOC_RANGE_491___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_491__RX_DCOC_RANGE_491___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_491__RX_DCOC_RES_I_491___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_491__RX_DCOC_RES_I_491___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_491__RX_DCOC_RES_Q_491___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_491__RX_DCOC_RES_Q_491___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_491___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_491___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_492 (0x005FC7B0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_492___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_492___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_492__RX_DCOC_RANGE_492___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_492__RX_DCOC_RES_I_492___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_492__RX_DCOC_RES_Q_492___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_492__RX_DCOC_RANGE_492___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_492__RX_DCOC_RANGE_492___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_492__RX_DCOC_RES_I_492___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_492__RX_DCOC_RES_I_492___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_492__RX_DCOC_RES_Q_492___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_492__RX_DCOC_RES_Q_492___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_492___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_492___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_493 (0x005FC7B4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_493___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_493___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_493__RX_DCOC_RANGE_493___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_493__RX_DCOC_RES_I_493___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_493__RX_DCOC_RES_Q_493___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_493__RX_DCOC_RANGE_493___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_493__RX_DCOC_RANGE_493___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_493__RX_DCOC_RES_I_493___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_493__RX_DCOC_RES_I_493___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_493__RX_DCOC_RES_Q_493___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_493__RX_DCOC_RES_Q_493___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_493___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_493___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_494 (0x005FC7B8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_494___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_494___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_494__RX_DCOC_RANGE_494___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_494__RX_DCOC_RES_I_494___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_494__RX_DCOC_RES_Q_494___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_494__RX_DCOC_RANGE_494___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_494__RX_DCOC_RANGE_494___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_494__RX_DCOC_RES_I_494___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_494__RX_DCOC_RES_I_494___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_494__RX_DCOC_RES_Q_494___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_494__RX_DCOC_RES_Q_494___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_494___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_494___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_495 (0x005FC7BC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_495___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_495___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_495__RX_DCOC_RANGE_495___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_495__RX_DCOC_RES_I_495___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_495__RX_DCOC_RES_Q_495___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_495__RX_DCOC_RANGE_495___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_495__RX_DCOC_RANGE_495___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_495__RX_DCOC_RES_I_495___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_495__RX_DCOC_RES_I_495___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_495__RX_DCOC_RES_Q_495___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_495__RX_DCOC_RES_Q_495___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_495___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_495___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_496 (0x005FC7C0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_496___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_496___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_496__RX_DCOC_RANGE_496___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_496__RX_DCOC_RES_I_496___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_496__RX_DCOC_RES_Q_496___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_496__RX_DCOC_RANGE_496___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_496__RX_DCOC_RANGE_496___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_496__RX_DCOC_RES_I_496___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_496__RX_DCOC_RES_I_496___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_496__RX_DCOC_RES_Q_496___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_496__RX_DCOC_RES_Q_496___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_496___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_496___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_497 (0x005FC7C4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_497___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_497___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_497__RX_DCOC_RANGE_497___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_497__RX_DCOC_RES_I_497___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_497__RX_DCOC_RES_Q_497___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_497__RX_DCOC_RANGE_497___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_497__RX_DCOC_RANGE_497___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_497__RX_DCOC_RES_I_497___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_497__RX_DCOC_RES_I_497___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_497__RX_DCOC_RES_Q_497___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_497__RX_DCOC_RES_Q_497___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_497___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_497___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_498 (0x005FC7C8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_498___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_498___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_498__RX_DCOC_RANGE_498___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_498__RX_DCOC_RES_I_498___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_498__RX_DCOC_RES_Q_498___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_498__RX_DCOC_RANGE_498___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_498__RX_DCOC_RANGE_498___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_498__RX_DCOC_RES_I_498___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_498__RX_DCOC_RES_I_498___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_498__RX_DCOC_RES_Q_498___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_498__RX_DCOC_RES_Q_498___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_498___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_498___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_499 (0x005FC7CC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_499___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_499___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_499__RX_DCOC_RANGE_499___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_499__RX_DCOC_RES_I_499___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_499__RX_DCOC_RES_Q_499___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_499__RX_DCOC_RANGE_499___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_499__RX_DCOC_RANGE_499___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_499__RX_DCOC_RES_I_499___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_499__RX_DCOC_RES_I_499___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_499__RX_DCOC_RES_Q_499___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_499__RX_DCOC_RES_Q_499___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_499___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_499___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_500 (0x005FC7D0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_500___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_500___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_500__RX_DCOC_RANGE_500___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_500__RX_DCOC_RES_I_500___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_500__RX_DCOC_RES_Q_500___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_500__RX_DCOC_RANGE_500___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_500__RX_DCOC_RANGE_500___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_500__RX_DCOC_RES_I_500___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_500__RX_DCOC_RES_I_500___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_500__RX_DCOC_RES_Q_500___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_500__RX_DCOC_RES_Q_500___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_500___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_500___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_501 (0x005FC7D4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_501___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_501___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_501__RX_DCOC_RANGE_501___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_501__RX_DCOC_RES_I_501___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_501__RX_DCOC_RES_Q_501___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_501__RX_DCOC_RANGE_501___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_501__RX_DCOC_RANGE_501___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_501__RX_DCOC_RES_I_501___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_501__RX_DCOC_RES_I_501___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_501__RX_DCOC_RES_Q_501___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_501__RX_DCOC_RES_Q_501___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_501___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_501___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_502 (0x005FC7D8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_502___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_502___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_502__RX_DCOC_RANGE_502___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_502__RX_DCOC_RES_I_502___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_502__RX_DCOC_RES_Q_502___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_502__RX_DCOC_RANGE_502___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_502__RX_DCOC_RANGE_502___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_502__RX_DCOC_RES_I_502___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_502__RX_DCOC_RES_I_502___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_502__RX_DCOC_RES_Q_502___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_502__RX_DCOC_RES_Q_502___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_502___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_502___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_503 (0x005FC7DC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_503___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_503___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_503__RX_DCOC_RANGE_503___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_503__RX_DCOC_RES_I_503___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_503__RX_DCOC_RES_Q_503___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_503__RX_DCOC_RANGE_503___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_503__RX_DCOC_RANGE_503___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_503__RX_DCOC_RES_I_503___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_503__RX_DCOC_RES_I_503___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_503__RX_DCOC_RES_Q_503___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_503__RX_DCOC_RES_Q_503___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_503___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_503___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_504 (0x005FC7E0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_504___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_504___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_504__RX_DCOC_RANGE_504___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_504__RX_DCOC_RES_I_504___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_504__RX_DCOC_RES_Q_504___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_504__RX_DCOC_RANGE_504___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_504__RX_DCOC_RANGE_504___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_504__RX_DCOC_RES_I_504___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_504__RX_DCOC_RES_I_504___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_504__RX_DCOC_RES_Q_504___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_504__RX_DCOC_RES_Q_504___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_504___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_504___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_505 (0x005FC7E4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_505___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_505___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_505__RX_DCOC_RANGE_505___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_505__RX_DCOC_RES_I_505___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_505__RX_DCOC_RES_Q_505___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_505__RX_DCOC_RANGE_505___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_505__RX_DCOC_RANGE_505___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_505__RX_DCOC_RES_I_505___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_505__RX_DCOC_RES_I_505___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_505__RX_DCOC_RES_Q_505___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_505__RX_DCOC_RES_Q_505___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_505___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_505___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_506 (0x005FC7E8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_506___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_506___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_506__RX_DCOC_RANGE_506___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_506__RX_DCOC_RES_I_506___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_506__RX_DCOC_RES_Q_506___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_506__RX_DCOC_RANGE_506___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_506__RX_DCOC_RANGE_506___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_506__RX_DCOC_RES_I_506___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_506__RX_DCOC_RES_I_506___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_506__RX_DCOC_RES_Q_506___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_506__RX_DCOC_RES_Q_506___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_506___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_506___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_507 (0x005FC7EC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_507___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_507___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_507__RX_DCOC_RANGE_507___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_507__RX_DCOC_RES_I_507___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_507__RX_DCOC_RES_Q_507___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_507__RX_DCOC_RANGE_507___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_507__RX_DCOC_RANGE_507___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_507__RX_DCOC_RES_I_507___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_507__RX_DCOC_RES_I_507___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_507__RX_DCOC_RES_Q_507___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_507__RX_DCOC_RES_Q_507___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_507___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_507___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_508 (0x005FC7F0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_508___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_508___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_508__RX_DCOC_RANGE_508___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_508__RX_DCOC_RES_I_508___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_508__RX_DCOC_RES_Q_508___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_508__RX_DCOC_RANGE_508___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_508__RX_DCOC_RANGE_508___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_508__RX_DCOC_RES_I_508___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_508__RX_DCOC_RES_I_508___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_508__RX_DCOC_RES_Q_508___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_508__RX_DCOC_RES_Q_508___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_508___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_508___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_509 (0x005FC7F4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_509___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_509___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_509__RX_DCOC_RANGE_509___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_509__RX_DCOC_RES_I_509___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_509__RX_DCOC_RES_Q_509___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_509__RX_DCOC_RANGE_509___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_509__RX_DCOC_RANGE_509___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_509__RX_DCOC_RES_I_509___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_509__RX_DCOC_RES_I_509___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_509__RX_DCOC_RES_Q_509___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_509__RX_DCOC_RES_Q_509___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_509___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_509___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_510 (0x005FC7F8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_510___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_510___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_510__RX_DCOC_RANGE_510___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_510__RX_DCOC_RES_I_510___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_510__RX_DCOC_RES_Q_510___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_510__RX_DCOC_RANGE_510___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_510__RX_DCOC_RANGE_510___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_510__RX_DCOC_RES_I_510___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_510__RX_DCOC_RES_I_510___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_510__RX_DCOC_RES_Q_510___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_510__RX_DCOC_RES_Q_510___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_510___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_510___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_511 (0x005FC7FC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_511___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_511___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_511__RX_DCOC_RANGE_511___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_511__RX_DCOC_RES_I_511___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_511__RX_DCOC_RES_Q_511___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_511__RX_DCOC_RANGE_511___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_511__RX_DCOC_RANGE_511___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_511__RX_DCOC_RES_I_511___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_511__RX_DCOC_RES_I_511___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_511__RX_DCOC_RES_Q_511___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_511__RX_DCOC_RES_Q_511___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_511___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_511___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_512 (0x005FC800) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_512___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_512___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_512__RX_DCOC_RANGE_512___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_512__RX_DCOC_RES_I_512___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_512__RX_DCOC_RES_Q_512___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_512__RX_DCOC_RANGE_512___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_512__RX_DCOC_RANGE_512___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_512__RX_DCOC_RES_I_512___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_512__RX_DCOC_RES_I_512___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_512__RX_DCOC_RES_Q_512___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_512__RX_DCOC_RES_Q_512___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_512___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_512___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_513 (0x005FC804) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_513___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_513___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_513__RX_DCOC_RANGE_513___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_513__RX_DCOC_RES_I_513___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_513__RX_DCOC_RES_Q_513___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_513__RX_DCOC_RANGE_513___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_513__RX_DCOC_RANGE_513___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_513__RX_DCOC_RES_I_513___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_513__RX_DCOC_RES_I_513___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_513__RX_DCOC_RES_Q_513___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_513__RX_DCOC_RES_Q_513___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_513___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_513___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_514 (0x005FC808) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_514___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_514___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_514__RX_DCOC_RANGE_514___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_514__RX_DCOC_RES_I_514___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_514__RX_DCOC_RES_Q_514___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_514__RX_DCOC_RANGE_514___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_514__RX_DCOC_RANGE_514___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_514__RX_DCOC_RES_I_514___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_514__RX_DCOC_RES_I_514___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_514__RX_DCOC_RES_Q_514___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_514__RX_DCOC_RES_Q_514___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_514___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_514___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_515 (0x005FC80C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_515___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_515___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_515__RX_DCOC_RANGE_515___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_515__RX_DCOC_RES_I_515___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_515__RX_DCOC_RES_Q_515___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_515__RX_DCOC_RANGE_515___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_515__RX_DCOC_RANGE_515___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_515__RX_DCOC_RES_I_515___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_515__RX_DCOC_RES_I_515___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_515__RX_DCOC_RES_Q_515___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_515__RX_DCOC_RES_Q_515___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_515___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_515___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_516 (0x005FC810) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_516___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_516___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_516__RX_DCOC_RANGE_516___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_516__RX_DCOC_RES_I_516___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_516__RX_DCOC_RES_Q_516___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_516__RX_DCOC_RANGE_516___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_516__RX_DCOC_RANGE_516___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_516__RX_DCOC_RES_I_516___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_516__RX_DCOC_RES_I_516___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_516__RX_DCOC_RES_Q_516___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_516__RX_DCOC_RES_Q_516___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_516___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_516___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_517 (0x005FC814) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_517___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_517___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_517__RX_DCOC_RANGE_517___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_517__RX_DCOC_RES_I_517___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_517__RX_DCOC_RES_Q_517___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_517__RX_DCOC_RANGE_517___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_517__RX_DCOC_RANGE_517___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_517__RX_DCOC_RES_I_517___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_517__RX_DCOC_RES_I_517___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_517__RX_DCOC_RES_Q_517___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_517__RX_DCOC_RES_Q_517___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_517___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_517___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_518 (0x005FC818) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_518___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_518___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_518__RX_DCOC_RANGE_518___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_518__RX_DCOC_RES_I_518___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_518__RX_DCOC_RES_Q_518___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_518__RX_DCOC_RANGE_518___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_518__RX_DCOC_RANGE_518___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_518__RX_DCOC_RES_I_518___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_518__RX_DCOC_RES_I_518___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_518__RX_DCOC_RES_Q_518___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_518__RX_DCOC_RES_Q_518___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_518___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_518___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_519 (0x005FC81C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_519___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_519___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_519__RX_DCOC_RANGE_519___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_519__RX_DCOC_RES_I_519___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_519__RX_DCOC_RES_Q_519___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_519__RX_DCOC_RANGE_519___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_519__RX_DCOC_RANGE_519___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_519__RX_DCOC_RES_I_519___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_519__RX_DCOC_RES_I_519___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_519__RX_DCOC_RES_Q_519___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_519__RX_DCOC_RES_Q_519___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_519___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_519___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_520 (0x005FC820) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_520___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_520___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_520__RX_DCOC_RANGE_520___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_520__RX_DCOC_RES_I_520___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_520__RX_DCOC_RES_Q_520___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_520__RX_DCOC_RANGE_520___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_520__RX_DCOC_RANGE_520___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_520__RX_DCOC_RES_I_520___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_520__RX_DCOC_RES_I_520___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_520__RX_DCOC_RES_Q_520___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_520__RX_DCOC_RES_Q_520___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_520___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_520___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_521 (0x005FC824) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_521___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_521___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_521__RX_DCOC_RANGE_521___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_521__RX_DCOC_RES_I_521___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_521__RX_DCOC_RES_Q_521___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_521__RX_DCOC_RANGE_521___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_521__RX_DCOC_RANGE_521___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_521__RX_DCOC_RES_I_521___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_521__RX_DCOC_RES_I_521___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_521__RX_DCOC_RES_Q_521___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_521__RX_DCOC_RES_Q_521___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_521___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_521___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_522 (0x005FC828) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_522___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_522___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_522__RX_DCOC_RANGE_522___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_522__RX_DCOC_RES_I_522___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_522__RX_DCOC_RES_Q_522___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_522__RX_DCOC_RANGE_522___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_522__RX_DCOC_RANGE_522___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_522__RX_DCOC_RES_I_522___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_522__RX_DCOC_RES_I_522___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_522__RX_DCOC_RES_Q_522___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_522__RX_DCOC_RES_Q_522___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_522___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_522___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_523 (0x005FC82C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_523___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_523___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_523__RX_DCOC_RANGE_523___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_523__RX_DCOC_RES_I_523___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_523__RX_DCOC_RES_Q_523___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_523__RX_DCOC_RANGE_523___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_523__RX_DCOC_RANGE_523___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_523__RX_DCOC_RES_I_523___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_523__RX_DCOC_RES_I_523___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_523__RX_DCOC_RES_Q_523___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_523__RX_DCOC_RES_Q_523___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_523___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_523___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_524 (0x005FC830) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_524___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_524___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_524__RX_DCOC_RANGE_524___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_524__RX_DCOC_RES_I_524___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_524__RX_DCOC_RES_Q_524___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_524__RX_DCOC_RANGE_524___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_524__RX_DCOC_RANGE_524___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_524__RX_DCOC_RES_I_524___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_524__RX_DCOC_RES_I_524___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_524__RX_DCOC_RES_Q_524___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_524__RX_DCOC_RES_Q_524___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_524___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_524___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_525 (0x005FC834) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_525___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_525___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_525__RX_DCOC_RANGE_525___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_525__RX_DCOC_RES_I_525___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_525__RX_DCOC_RES_Q_525___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_525__RX_DCOC_RANGE_525___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_525__RX_DCOC_RANGE_525___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_525__RX_DCOC_RES_I_525___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_525__RX_DCOC_RES_I_525___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_525__RX_DCOC_RES_Q_525___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_525__RX_DCOC_RES_Q_525___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_525___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_525___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_526 (0x005FC838) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_526___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_526___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_526__RX_DCOC_RANGE_526___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_526__RX_DCOC_RES_I_526___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_526__RX_DCOC_RES_Q_526___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_526__RX_DCOC_RANGE_526___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_526__RX_DCOC_RANGE_526___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_526__RX_DCOC_RES_I_526___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_526__RX_DCOC_RES_I_526___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_526__RX_DCOC_RES_Q_526___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_526__RX_DCOC_RES_Q_526___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_526___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_526___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_527 (0x005FC83C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_527___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_527___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_527__RX_DCOC_RANGE_527___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_527__RX_DCOC_RES_I_527___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_527__RX_DCOC_RES_Q_527___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_527__RX_DCOC_RANGE_527___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_527__RX_DCOC_RANGE_527___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_527__RX_DCOC_RES_I_527___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_527__RX_DCOC_RES_I_527___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_527__RX_DCOC_RES_Q_527___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_527__RX_DCOC_RES_Q_527___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_527___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_527___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_528 (0x005FC840) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_528___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_528___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_528__RX_DCOC_RANGE_528___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_528__RX_DCOC_RES_I_528___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_528__RX_DCOC_RES_Q_528___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_528__RX_DCOC_RANGE_528___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_528__RX_DCOC_RANGE_528___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_528__RX_DCOC_RES_I_528___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_528__RX_DCOC_RES_I_528___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_528__RX_DCOC_RES_Q_528___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_528__RX_DCOC_RES_Q_528___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_528___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_528___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_529 (0x005FC844) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_529___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_529___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_529__RX_DCOC_RANGE_529___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_529__RX_DCOC_RES_I_529___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_529__RX_DCOC_RES_Q_529___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_529__RX_DCOC_RANGE_529___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_529__RX_DCOC_RANGE_529___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_529__RX_DCOC_RES_I_529___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_529__RX_DCOC_RES_I_529___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_529__RX_DCOC_RES_Q_529___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_529__RX_DCOC_RES_Q_529___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_529___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_529___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_530 (0x005FC848) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_530___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_530___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_530__RX_DCOC_RANGE_530___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_530__RX_DCOC_RES_I_530___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_530__RX_DCOC_RES_Q_530___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_530__RX_DCOC_RANGE_530___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_530__RX_DCOC_RANGE_530___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_530__RX_DCOC_RES_I_530___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_530__RX_DCOC_RES_I_530___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_530__RX_DCOC_RES_Q_530___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_530__RX_DCOC_RES_Q_530___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_530___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_530___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_531 (0x005FC84C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_531___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_531___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_531__RX_DCOC_RANGE_531___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_531__RX_DCOC_RES_I_531___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_531__RX_DCOC_RES_Q_531___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_531__RX_DCOC_RANGE_531___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_531__RX_DCOC_RANGE_531___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_531__RX_DCOC_RES_I_531___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_531__RX_DCOC_RES_I_531___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_531__RX_DCOC_RES_Q_531___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_531__RX_DCOC_RES_Q_531___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_531___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_531___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_532 (0x005FC850) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_532___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_532___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_532__RX_DCOC_RANGE_532___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_532__RX_DCOC_RES_I_532___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_532__RX_DCOC_RES_Q_532___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_532__RX_DCOC_RANGE_532___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_532__RX_DCOC_RANGE_532___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_532__RX_DCOC_RES_I_532___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_532__RX_DCOC_RES_I_532___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_532__RX_DCOC_RES_Q_532___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_532__RX_DCOC_RES_Q_532___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_532___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_532___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_533 (0x005FC854) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_533___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_533___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_533__RX_DCOC_RANGE_533___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_533__RX_DCOC_RES_I_533___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_533__RX_DCOC_RES_Q_533___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_533__RX_DCOC_RANGE_533___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_533__RX_DCOC_RANGE_533___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_533__RX_DCOC_RES_I_533___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_533__RX_DCOC_RES_I_533___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_533__RX_DCOC_RES_Q_533___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_533__RX_DCOC_RES_Q_533___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_533___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_533___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_534 (0x005FC858) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_534___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_534___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_534__RX_DCOC_RANGE_534___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_534__RX_DCOC_RES_I_534___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_534__RX_DCOC_RES_Q_534___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_534__RX_DCOC_RANGE_534___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_534__RX_DCOC_RANGE_534___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_534__RX_DCOC_RES_I_534___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_534__RX_DCOC_RES_I_534___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_534__RX_DCOC_RES_Q_534___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_534__RX_DCOC_RES_Q_534___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_534___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_534___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_535 (0x005FC85C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_535___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_535___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_535__RX_DCOC_RANGE_535___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_535__RX_DCOC_RES_I_535___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_535__RX_DCOC_RES_Q_535___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_535__RX_DCOC_RANGE_535___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_535__RX_DCOC_RANGE_535___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_535__RX_DCOC_RES_I_535___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_535__RX_DCOC_RES_I_535___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_535__RX_DCOC_RES_Q_535___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_535__RX_DCOC_RES_Q_535___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_535___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_535___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_536 (0x005FC860) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_536___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_536___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_536__RX_DCOC_RANGE_536___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_536__RX_DCOC_RES_I_536___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_536__RX_DCOC_RES_Q_536___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_536__RX_DCOC_RANGE_536___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_536__RX_DCOC_RANGE_536___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_536__RX_DCOC_RES_I_536___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_536__RX_DCOC_RES_I_536___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_536__RX_DCOC_RES_Q_536___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_536__RX_DCOC_RES_Q_536___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_536___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_536___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_537 (0x005FC864) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_537___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_537___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_537__RX_DCOC_RANGE_537___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_537__RX_DCOC_RES_I_537___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_537__RX_DCOC_RES_Q_537___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_537__RX_DCOC_RANGE_537___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_537__RX_DCOC_RANGE_537___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_537__RX_DCOC_RES_I_537___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_537__RX_DCOC_RES_I_537___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_537__RX_DCOC_RES_Q_537___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_537__RX_DCOC_RES_Q_537___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_537___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_537___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_538 (0x005FC868) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_538___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_538___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_538__RX_DCOC_RANGE_538___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_538__RX_DCOC_RES_I_538___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_538__RX_DCOC_RES_Q_538___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_538__RX_DCOC_RANGE_538___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_538__RX_DCOC_RANGE_538___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_538__RX_DCOC_RES_I_538___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_538__RX_DCOC_RES_I_538___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_538__RX_DCOC_RES_Q_538___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_538__RX_DCOC_RES_Q_538___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_538___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_538___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_539 (0x005FC86C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_539___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_539___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_539__RX_DCOC_RANGE_539___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_539__RX_DCOC_RES_I_539___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_539__RX_DCOC_RES_Q_539___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_539__RX_DCOC_RANGE_539___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_539__RX_DCOC_RANGE_539___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_539__RX_DCOC_RES_I_539___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_539__RX_DCOC_RES_I_539___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_539__RX_DCOC_RES_Q_539___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_539__RX_DCOC_RES_Q_539___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_539___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_539___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_540 (0x005FC870) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_540___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_540___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_540__RX_DCOC_RANGE_540___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_540__RX_DCOC_RES_I_540___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_540__RX_DCOC_RES_Q_540___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_540__RX_DCOC_RANGE_540___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_540__RX_DCOC_RANGE_540___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_540__RX_DCOC_RES_I_540___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_540__RX_DCOC_RES_I_540___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_540__RX_DCOC_RES_Q_540___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_540__RX_DCOC_RES_Q_540___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_540___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_540___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_541 (0x005FC874) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_541___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_541___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_541__RX_DCOC_RANGE_541___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_541__RX_DCOC_RES_I_541___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_541__RX_DCOC_RES_Q_541___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_541__RX_DCOC_RANGE_541___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_541__RX_DCOC_RANGE_541___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_541__RX_DCOC_RES_I_541___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_541__RX_DCOC_RES_I_541___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_541__RX_DCOC_RES_Q_541___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_541__RX_DCOC_RES_Q_541___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_541___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_541___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_542 (0x005FC878) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_542___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_542___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_542__RX_DCOC_RANGE_542___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_542__RX_DCOC_RES_I_542___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_542__RX_DCOC_RES_Q_542___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_542__RX_DCOC_RANGE_542___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_542__RX_DCOC_RANGE_542___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_542__RX_DCOC_RES_I_542___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_542__RX_DCOC_RES_I_542___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_542__RX_DCOC_RES_Q_542___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_542__RX_DCOC_RES_Q_542___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_542___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_542___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_543 (0x005FC87C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_543___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_543___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_543__RX_DCOC_RANGE_543___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_543__RX_DCOC_RES_I_543___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_543__RX_DCOC_RES_Q_543___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_543__RX_DCOC_RANGE_543___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_543__RX_DCOC_RANGE_543___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_543__RX_DCOC_RES_I_543___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_543__RX_DCOC_RES_I_543___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_543__RX_DCOC_RES_Q_543___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_543__RX_DCOC_RES_Q_543___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_543___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_543___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_544 (0x005FC880) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_544___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_544___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_544__RX_DCOC_RANGE_544___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_544__RX_DCOC_RES_I_544___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_544__RX_DCOC_RES_Q_544___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_544__RX_DCOC_RANGE_544___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_544__RX_DCOC_RANGE_544___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_544__RX_DCOC_RES_I_544___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_544__RX_DCOC_RES_I_544___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_544__RX_DCOC_RES_Q_544___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_544__RX_DCOC_RES_Q_544___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_544___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_544___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_545 (0x005FC884) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_545___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_545___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_545__RX_DCOC_RANGE_545___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_545__RX_DCOC_RES_I_545___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_545__RX_DCOC_RES_Q_545___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_545__RX_DCOC_RANGE_545___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_545__RX_DCOC_RANGE_545___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_545__RX_DCOC_RES_I_545___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_545__RX_DCOC_RES_I_545___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_545__RX_DCOC_RES_Q_545___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_545__RX_DCOC_RES_Q_545___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_545___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_545___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_546 (0x005FC888) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_546___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_546___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_546__RX_DCOC_RANGE_546___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_546__RX_DCOC_RES_I_546___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_546__RX_DCOC_RES_Q_546___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_546__RX_DCOC_RANGE_546___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_546__RX_DCOC_RANGE_546___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_546__RX_DCOC_RES_I_546___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_546__RX_DCOC_RES_I_546___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_546__RX_DCOC_RES_Q_546___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_546__RX_DCOC_RES_Q_546___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_546___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_546___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_547 (0x005FC88C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_547___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_547___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_547__RX_DCOC_RANGE_547___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_547__RX_DCOC_RES_I_547___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_547__RX_DCOC_RES_Q_547___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_547__RX_DCOC_RANGE_547___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_547__RX_DCOC_RANGE_547___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_547__RX_DCOC_RES_I_547___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_547__RX_DCOC_RES_I_547___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_547__RX_DCOC_RES_Q_547___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_547__RX_DCOC_RES_Q_547___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_547___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_547___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_548 (0x005FC890) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_548___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_548___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_548__RX_DCOC_RANGE_548___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_548__RX_DCOC_RES_I_548___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_548__RX_DCOC_RES_Q_548___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_548__RX_DCOC_RANGE_548___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_548__RX_DCOC_RANGE_548___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_548__RX_DCOC_RES_I_548___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_548__RX_DCOC_RES_I_548___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_548__RX_DCOC_RES_Q_548___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_548__RX_DCOC_RES_Q_548___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_548___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_548___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_549 (0x005FC894) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_549___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_549___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_549__RX_DCOC_RANGE_549___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_549__RX_DCOC_RES_I_549___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_549__RX_DCOC_RES_Q_549___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_549__RX_DCOC_RANGE_549___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_549__RX_DCOC_RANGE_549___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_549__RX_DCOC_RES_I_549___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_549__RX_DCOC_RES_I_549___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_549__RX_DCOC_RES_Q_549___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_549__RX_DCOC_RES_Q_549___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_549___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_549___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_550 (0x005FC898) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_550___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_550___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_550__RX_DCOC_RANGE_550___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_550__RX_DCOC_RES_I_550___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_550__RX_DCOC_RES_Q_550___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_550__RX_DCOC_RANGE_550___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_550__RX_DCOC_RANGE_550___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_550__RX_DCOC_RES_I_550___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_550__RX_DCOC_RES_I_550___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_550__RX_DCOC_RES_Q_550___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_550__RX_DCOC_RES_Q_550___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_550___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_550___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_551 (0x005FC89C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_551___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_551___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_551__RX_DCOC_RANGE_551___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_551__RX_DCOC_RES_I_551___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_551__RX_DCOC_RES_Q_551___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_551__RX_DCOC_RANGE_551___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_551__RX_DCOC_RANGE_551___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_551__RX_DCOC_RES_I_551___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_551__RX_DCOC_RES_I_551___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_551__RX_DCOC_RES_Q_551___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_551__RX_DCOC_RES_Q_551___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_551___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_551___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_552 (0x005FC8A0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_552___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_552___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_552__RX_DCOC_RANGE_552___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_552__RX_DCOC_RES_I_552___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_552__RX_DCOC_RES_Q_552___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_552__RX_DCOC_RANGE_552___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_552__RX_DCOC_RANGE_552___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_552__RX_DCOC_RES_I_552___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_552__RX_DCOC_RES_I_552___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_552__RX_DCOC_RES_Q_552___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_552__RX_DCOC_RES_Q_552___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_552___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_552___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_553 (0x005FC8A4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_553___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_553___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_553__RX_DCOC_RANGE_553___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_553__RX_DCOC_RES_I_553___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_553__RX_DCOC_RES_Q_553___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_553__RX_DCOC_RANGE_553___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_553__RX_DCOC_RANGE_553___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_553__RX_DCOC_RES_I_553___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_553__RX_DCOC_RES_I_553___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_553__RX_DCOC_RES_Q_553___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_553__RX_DCOC_RES_Q_553___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_553___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_553___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_554 (0x005FC8A8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_554___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_554___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_554__RX_DCOC_RANGE_554___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_554__RX_DCOC_RES_I_554___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_554__RX_DCOC_RES_Q_554___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_554__RX_DCOC_RANGE_554___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_554__RX_DCOC_RANGE_554___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_554__RX_DCOC_RES_I_554___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_554__RX_DCOC_RES_I_554___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_554__RX_DCOC_RES_Q_554___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_554__RX_DCOC_RES_Q_554___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_554___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_554___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_555 (0x005FC8AC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_555___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_555___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_555__RX_DCOC_RANGE_555___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_555__RX_DCOC_RES_I_555___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_555__RX_DCOC_RES_Q_555___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_555__RX_DCOC_RANGE_555___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_555__RX_DCOC_RANGE_555___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_555__RX_DCOC_RES_I_555___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_555__RX_DCOC_RES_I_555___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_555__RX_DCOC_RES_Q_555___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_555__RX_DCOC_RES_Q_555___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_555___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_555___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_556 (0x005FC8B0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_556___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_556___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_556__RX_DCOC_RANGE_556___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_556__RX_DCOC_RES_I_556___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_556__RX_DCOC_RES_Q_556___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_556__RX_DCOC_RANGE_556___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_556__RX_DCOC_RANGE_556___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_556__RX_DCOC_RES_I_556___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_556__RX_DCOC_RES_I_556___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_556__RX_DCOC_RES_Q_556___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_556__RX_DCOC_RES_Q_556___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_556___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_556___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_557 (0x005FC8B4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_557___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_557___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_557__RX_DCOC_RANGE_557___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_557__RX_DCOC_RES_I_557___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_557__RX_DCOC_RES_Q_557___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_557__RX_DCOC_RANGE_557___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_557__RX_DCOC_RANGE_557___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_557__RX_DCOC_RES_I_557___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_557__RX_DCOC_RES_I_557___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_557__RX_DCOC_RES_Q_557___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_557__RX_DCOC_RES_Q_557___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_557___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_557___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_558 (0x005FC8B8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_558___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_558___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_558__RX_DCOC_RANGE_558___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_558__RX_DCOC_RES_I_558___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_558__RX_DCOC_RES_Q_558___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_558__RX_DCOC_RANGE_558___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_558__RX_DCOC_RANGE_558___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_558__RX_DCOC_RES_I_558___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_558__RX_DCOC_RES_I_558___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_558__RX_DCOC_RES_Q_558___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_558__RX_DCOC_RES_Q_558___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_558___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_558___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_559 (0x005FC8BC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_559___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_559___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_559__RX_DCOC_RANGE_559___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_559__RX_DCOC_RES_I_559___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_559__RX_DCOC_RES_Q_559___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_559__RX_DCOC_RANGE_559___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_559__RX_DCOC_RANGE_559___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_559__RX_DCOC_RES_I_559___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_559__RX_DCOC_RES_I_559___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_559__RX_DCOC_RES_Q_559___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_559__RX_DCOC_RES_Q_559___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_559___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_559___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_560 (0x005FC8C0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_560___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_560___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_560__RX_DCOC_RANGE_560___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_560__RX_DCOC_RES_I_560___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_560__RX_DCOC_RES_Q_560___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_560__RX_DCOC_RANGE_560___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_560__RX_DCOC_RANGE_560___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_560__RX_DCOC_RES_I_560___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_560__RX_DCOC_RES_I_560___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_560__RX_DCOC_RES_Q_560___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_560__RX_DCOC_RES_Q_560___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_560___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_560___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_561 (0x005FC8C4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_561___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_561___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_561__RX_DCOC_RANGE_561___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_561__RX_DCOC_RES_I_561___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_561__RX_DCOC_RES_Q_561___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_561__RX_DCOC_RANGE_561___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_561__RX_DCOC_RANGE_561___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_561__RX_DCOC_RES_I_561___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_561__RX_DCOC_RES_I_561___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_561__RX_DCOC_RES_Q_561___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_561__RX_DCOC_RES_Q_561___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_561___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_561___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_562 (0x005FC8C8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_562___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_562___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_562__RX_DCOC_RANGE_562___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_562__RX_DCOC_RES_I_562___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_562__RX_DCOC_RES_Q_562___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_562__RX_DCOC_RANGE_562___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_562__RX_DCOC_RANGE_562___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_562__RX_DCOC_RES_I_562___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_562__RX_DCOC_RES_I_562___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_562__RX_DCOC_RES_Q_562___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_562__RX_DCOC_RES_Q_562___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_562___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_562___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_563 (0x005FC8CC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_563___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_563___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_563__RX_DCOC_RANGE_563___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_563__RX_DCOC_RES_I_563___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_563__RX_DCOC_RES_Q_563___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_563__RX_DCOC_RANGE_563___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_563__RX_DCOC_RANGE_563___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_563__RX_DCOC_RES_I_563___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_563__RX_DCOC_RES_I_563___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_563__RX_DCOC_RES_Q_563___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_563__RX_DCOC_RES_Q_563___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_563___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_563___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_564 (0x005FC8D0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_564___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_564___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_564__RX_DCOC_RANGE_564___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_564__RX_DCOC_RES_I_564___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_564__RX_DCOC_RES_Q_564___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_564__RX_DCOC_RANGE_564___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_564__RX_DCOC_RANGE_564___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_564__RX_DCOC_RES_I_564___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_564__RX_DCOC_RES_I_564___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_564__RX_DCOC_RES_Q_564___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_564__RX_DCOC_RES_Q_564___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_564___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_564___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_565 (0x005FC8D4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_565___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_565___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_565__RX_DCOC_RANGE_565___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_565__RX_DCOC_RES_I_565___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_565__RX_DCOC_RES_Q_565___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_565__RX_DCOC_RANGE_565___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_565__RX_DCOC_RANGE_565___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_565__RX_DCOC_RES_I_565___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_565__RX_DCOC_RES_I_565___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_565__RX_DCOC_RES_Q_565___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_565__RX_DCOC_RES_Q_565___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_565___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_565___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_566 (0x005FC8D8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_566___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_566___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_566__RX_DCOC_RANGE_566___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_566__RX_DCOC_RES_I_566___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_566__RX_DCOC_RES_Q_566___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_566__RX_DCOC_RANGE_566___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_566__RX_DCOC_RANGE_566___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_566__RX_DCOC_RES_I_566___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_566__RX_DCOC_RES_I_566___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_566__RX_DCOC_RES_Q_566___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_566__RX_DCOC_RES_Q_566___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_566___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_566___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_567 (0x005FC8DC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_567___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_567___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_567__RX_DCOC_RANGE_567___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_567__RX_DCOC_RES_I_567___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_567__RX_DCOC_RES_Q_567___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_567__RX_DCOC_RANGE_567___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_567__RX_DCOC_RANGE_567___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_567__RX_DCOC_RES_I_567___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_567__RX_DCOC_RES_I_567___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_567__RX_DCOC_RES_Q_567___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_567__RX_DCOC_RES_Q_567___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_567___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_567___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_568 (0x005FC8E0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_568___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_568___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_568__RX_DCOC_RANGE_568___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_568__RX_DCOC_RES_I_568___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_568__RX_DCOC_RES_Q_568___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_568__RX_DCOC_RANGE_568___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_568__RX_DCOC_RANGE_568___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_568__RX_DCOC_RES_I_568___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_568__RX_DCOC_RES_I_568___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_568__RX_DCOC_RES_Q_568___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_568__RX_DCOC_RES_Q_568___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_568___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_568___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_569 (0x005FC8E4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_569___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_569___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_569__RX_DCOC_RANGE_569___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_569__RX_DCOC_RES_I_569___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_569__RX_DCOC_RES_Q_569___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_569__RX_DCOC_RANGE_569___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_569__RX_DCOC_RANGE_569___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_569__RX_DCOC_RES_I_569___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_569__RX_DCOC_RES_I_569___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_569__RX_DCOC_RES_Q_569___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_569__RX_DCOC_RES_Q_569___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_569___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_569___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_570 (0x005FC8E8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_570___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_570___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_570__RX_DCOC_RANGE_570___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_570__RX_DCOC_RES_I_570___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_570__RX_DCOC_RES_Q_570___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_570__RX_DCOC_RANGE_570___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_570__RX_DCOC_RANGE_570___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_570__RX_DCOC_RES_I_570___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_570__RX_DCOC_RES_I_570___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_570__RX_DCOC_RES_Q_570___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_570__RX_DCOC_RES_Q_570___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_570___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_570___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_571 (0x005FC8EC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_571___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_571___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_571__RX_DCOC_RANGE_571___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_571__RX_DCOC_RES_I_571___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_571__RX_DCOC_RES_Q_571___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_571__RX_DCOC_RANGE_571___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_571__RX_DCOC_RANGE_571___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_571__RX_DCOC_RES_I_571___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_571__RX_DCOC_RES_I_571___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_571__RX_DCOC_RES_Q_571___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_571__RX_DCOC_RES_Q_571___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_571___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_571___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_572 (0x005FC8F0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_572___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_572___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_572__RX_DCOC_RANGE_572___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_572__RX_DCOC_RES_I_572___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_572__RX_DCOC_RES_Q_572___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_572__RX_DCOC_RANGE_572___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_572__RX_DCOC_RANGE_572___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_572__RX_DCOC_RES_I_572___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_572__RX_DCOC_RES_I_572___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_572__RX_DCOC_RES_Q_572___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_572__RX_DCOC_RES_Q_572___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_572___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_572___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_573 (0x005FC8F4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_573___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_573___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_573__RX_DCOC_RANGE_573___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_573__RX_DCOC_RES_I_573___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_573__RX_DCOC_RES_Q_573___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_573__RX_DCOC_RANGE_573___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_573__RX_DCOC_RANGE_573___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_573__RX_DCOC_RES_I_573___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_573__RX_DCOC_RES_I_573___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_573__RX_DCOC_RES_Q_573___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_573__RX_DCOC_RES_Q_573___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_573___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_573___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_574 (0x005FC8F8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_574___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_574___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_574__RX_DCOC_RANGE_574___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_574__RX_DCOC_RES_I_574___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_574__RX_DCOC_RES_Q_574___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_574__RX_DCOC_RANGE_574___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_574__RX_DCOC_RANGE_574___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_574__RX_DCOC_RES_I_574___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_574__RX_DCOC_RES_I_574___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_574__RX_DCOC_RES_Q_574___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_574__RX_DCOC_RES_Q_574___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_574___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_574___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_575 (0x005FC8FC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_575___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_575___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_575__RX_DCOC_RANGE_575___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_575__RX_DCOC_RES_I_575___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_575__RX_DCOC_RES_Q_575___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_575__RX_DCOC_RANGE_575___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_575__RX_DCOC_RANGE_575___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_575__RX_DCOC_RES_I_575___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_575__RX_DCOC_RES_I_575___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_575__RX_DCOC_RES_Q_575___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_575__RX_DCOC_RES_Q_575___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_575___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_575___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_576 (0x005FC900) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_576___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_576___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_576__RX_DCOC_RANGE_576___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_576__RX_DCOC_RES_I_576___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_576__RX_DCOC_RES_Q_576___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_576__RX_DCOC_RANGE_576___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_576__RX_DCOC_RANGE_576___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_576__RX_DCOC_RES_I_576___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_576__RX_DCOC_RES_I_576___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_576__RX_DCOC_RES_Q_576___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_576__RX_DCOC_RES_Q_576___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_576___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_576___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_577 (0x005FC904) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_577___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_577___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_577__RX_DCOC_RANGE_577___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_577__RX_DCOC_RES_I_577___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_577__RX_DCOC_RES_Q_577___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_577__RX_DCOC_RANGE_577___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_577__RX_DCOC_RANGE_577___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_577__RX_DCOC_RES_I_577___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_577__RX_DCOC_RES_I_577___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_577__RX_DCOC_RES_Q_577___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_577__RX_DCOC_RES_Q_577___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_577___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_577___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_578 (0x005FC908) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_578___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_578___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_578__RX_DCOC_RANGE_578___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_578__RX_DCOC_RES_I_578___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_578__RX_DCOC_RES_Q_578___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_578__RX_DCOC_RANGE_578___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_578__RX_DCOC_RANGE_578___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_578__RX_DCOC_RES_I_578___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_578__RX_DCOC_RES_I_578___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_578__RX_DCOC_RES_Q_578___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_578__RX_DCOC_RES_Q_578___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_578___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_578___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_579 (0x005FC90C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_579___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_579___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_579__RX_DCOC_RANGE_579___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_579__RX_DCOC_RES_I_579___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_579__RX_DCOC_RES_Q_579___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_579__RX_DCOC_RANGE_579___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_579__RX_DCOC_RANGE_579___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_579__RX_DCOC_RES_I_579___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_579__RX_DCOC_RES_I_579___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_579__RX_DCOC_RES_Q_579___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_579__RX_DCOC_RES_Q_579___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_579___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_579___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_580 (0x005FC910) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_580___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_580___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_580__RX_DCOC_RANGE_580___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_580__RX_DCOC_RES_I_580___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_580__RX_DCOC_RES_Q_580___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_580__RX_DCOC_RANGE_580___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_580__RX_DCOC_RANGE_580___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_580__RX_DCOC_RES_I_580___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_580__RX_DCOC_RES_I_580___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_580__RX_DCOC_RES_Q_580___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_580__RX_DCOC_RES_Q_580___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_580___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_580___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_581 (0x005FC914) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_581___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_581___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_581__RX_DCOC_RANGE_581___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_581__RX_DCOC_RES_I_581___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_581__RX_DCOC_RES_Q_581___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_581__RX_DCOC_RANGE_581___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_581__RX_DCOC_RANGE_581___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_581__RX_DCOC_RES_I_581___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_581__RX_DCOC_RES_I_581___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_581__RX_DCOC_RES_Q_581___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_581__RX_DCOC_RES_Q_581___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_581___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_581___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_582 (0x005FC918) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_582___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_582___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_582__RX_DCOC_RANGE_582___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_582__RX_DCOC_RES_I_582___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_582__RX_DCOC_RES_Q_582___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_582__RX_DCOC_RANGE_582___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_582__RX_DCOC_RANGE_582___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_582__RX_DCOC_RES_I_582___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_582__RX_DCOC_RES_I_582___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_582__RX_DCOC_RES_Q_582___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_582__RX_DCOC_RES_Q_582___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_582___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_582___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_583 (0x005FC91C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_583___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_583___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_583__RX_DCOC_RANGE_583___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_583__RX_DCOC_RES_I_583___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_583__RX_DCOC_RES_Q_583___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_583__RX_DCOC_RANGE_583___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_583__RX_DCOC_RANGE_583___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_583__RX_DCOC_RES_I_583___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_583__RX_DCOC_RES_I_583___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_583__RX_DCOC_RES_Q_583___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_583__RX_DCOC_RES_Q_583___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_583___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_583___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_584 (0x005FC920) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_584___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_584___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_584__RX_DCOC_RANGE_584___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_584__RX_DCOC_RES_I_584___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_584__RX_DCOC_RES_Q_584___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_584__RX_DCOC_RANGE_584___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_584__RX_DCOC_RANGE_584___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_584__RX_DCOC_RES_I_584___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_584__RX_DCOC_RES_I_584___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_584__RX_DCOC_RES_Q_584___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_584__RX_DCOC_RES_Q_584___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_584___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_584___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_585 (0x005FC924) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_585___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_585___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_585__RX_DCOC_RANGE_585___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_585__RX_DCOC_RES_I_585___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_585__RX_DCOC_RES_Q_585___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_585__RX_DCOC_RANGE_585___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_585__RX_DCOC_RANGE_585___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_585__RX_DCOC_RES_I_585___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_585__RX_DCOC_RES_I_585___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_585__RX_DCOC_RES_Q_585___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_585__RX_DCOC_RES_Q_585___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_585___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_585___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_586 (0x005FC928) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_586___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_586___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_586__RX_DCOC_RANGE_586___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_586__RX_DCOC_RES_I_586___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_586__RX_DCOC_RES_Q_586___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_586__RX_DCOC_RANGE_586___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_586__RX_DCOC_RANGE_586___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_586__RX_DCOC_RES_I_586___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_586__RX_DCOC_RES_I_586___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_586__RX_DCOC_RES_Q_586___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_586__RX_DCOC_RES_Q_586___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_586___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_586___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_587 (0x005FC92C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_587___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_587___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_587__RX_DCOC_RANGE_587___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_587__RX_DCOC_RES_I_587___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_587__RX_DCOC_RES_Q_587___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_587__RX_DCOC_RANGE_587___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_587__RX_DCOC_RANGE_587___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_587__RX_DCOC_RES_I_587___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_587__RX_DCOC_RES_I_587___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_587__RX_DCOC_RES_Q_587___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_587__RX_DCOC_RES_Q_587___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_587___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_587___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_588 (0x005FC930) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_588___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_588___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_588__RX_DCOC_RANGE_588___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_588__RX_DCOC_RES_I_588___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_588__RX_DCOC_RES_Q_588___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_588__RX_DCOC_RANGE_588___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_588__RX_DCOC_RANGE_588___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_588__RX_DCOC_RES_I_588___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_588__RX_DCOC_RES_I_588___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_588__RX_DCOC_RES_Q_588___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_588__RX_DCOC_RES_Q_588___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_588___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_588___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_589 (0x005FC934) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_589___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_589___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_589__RX_DCOC_RANGE_589___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_589__RX_DCOC_RES_I_589___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_589__RX_DCOC_RES_Q_589___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_589__RX_DCOC_RANGE_589___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_589__RX_DCOC_RANGE_589___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_589__RX_DCOC_RES_I_589___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_589__RX_DCOC_RES_I_589___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_589__RX_DCOC_RES_Q_589___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_589__RX_DCOC_RES_Q_589___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_589___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_589___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_590 (0x005FC938) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_590___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_590___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_590__RX_DCOC_RANGE_590___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_590__RX_DCOC_RES_I_590___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_590__RX_DCOC_RES_Q_590___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_590__RX_DCOC_RANGE_590___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_590__RX_DCOC_RANGE_590___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_590__RX_DCOC_RES_I_590___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_590__RX_DCOC_RES_I_590___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_590__RX_DCOC_RES_Q_590___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_590__RX_DCOC_RES_Q_590___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_590___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_590___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_591 (0x005FC93C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_591___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_591___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_591__RX_DCOC_RANGE_591___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_591__RX_DCOC_RES_I_591___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_591__RX_DCOC_RES_Q_591___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_591__RX_DCOC_RANGE_591___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_591__RX_DCOC_RANGE_591___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_591__RX_DCOC_RES_I_591___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_591__RX_DCOC_RES_I_591___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_591__RX_DCOC_RES_Q_591___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_591__RX_DCOC_RES_Q_591___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_591___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_591___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_592 (0x005FC940) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_592___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_592___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_592__RX_DCOC_RANGE_592___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_592__RX_DCOC_RES_I_592___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_592__RX_DCOC_RES_Q_592___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_592__RX_DCOC_RANGE_592___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_592__RX_DCOC_RANGE_592___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_592__RX_DCOC_RES_I_592___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_592__RX_DCOC_RES_I_592___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_592__RX_DCOC_RES_Q_592___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_592__RX_DCOC_RES_Q_592___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_592___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_592___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_593 (0x005FC944) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_593___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_593___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_593__RX_DCOC_RANGE_593___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_593__RX_DCOC_RES_I_593___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_593__RX_DCOC_RES_Q_593___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_593__RX_DCOC_RANGE_593___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_593__RX_DCOC_RANGE_593___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_593__RX_DCOC_RES_I_593___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_593__RX_DCOC_RES_I_593___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_593__RX_DCOC_RES_Q_593___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_593__RX_DCOC_RES_Q_593___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_593___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_593___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_594 (0x005FC948) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_594___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_594___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_594__RX_DCOC_RANGE_594___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_594__RX_DCOC_RES_I_594___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_594__RX_DCOC_RES_Q_594___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_594__RX_DCOC_RANGE_594___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_594__RX_DCOC_RANGE_594___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_594__RX_DCOC_RES_I_594___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_594__RX_DCOC_RES_I_594___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_594__RX_DCOC_RES_Q_594___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_594__RX_DCOC_RES_Q_594___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_594___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_594___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_595 (0x005FC94C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_595___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_595___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_595__RX_DCOC_RANGE_595___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_595__RX_DCOC_RES_I_595___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_595__RX_DCOC_RES_Q_595___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_595__RX_DCOC_RANGE_595___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_595__RX_DCOC_RANGE_595___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_595__RX_DCOC_RES_I_595___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_595__RX_DCOC_RES_I_595___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_595__RX_DCOC_RES_Q_595___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_595__RX_DCOC_RES_Q_595___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_595___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_595___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_596 (0x005FC950) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_596___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_596___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_596__RX_DCOC_RANGE_596___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_596__RX_DCOC_RES_I_596___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_596__RX_DCOC_RES_Q_596___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_596__RX_DCOC_RANGE_596___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_596__RX_DCOC_RANGE_596___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_596__RX_DCOC_RES_I_596___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_596__RX_DCOC_RES_I_596___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_596__RX_DCOC_RES_Q_596___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_596__RX_DCOC_RES_Q_596___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_596___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_596___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_597 (0x005FC954) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_597___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_597___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_597__RX_DCOC_RANGE_597___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_597__RX_DCOC_RES_I_597___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_597__RX_DCOC_RES_Q_597___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_597__RX_DCOC_RANGE_597___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_597__RX_DCOC_RANGE_597___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_597__RX_DCOC_RES_I_597___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_597__RX_DCOC_RES_I_597___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_597__RX_DCOC_RES_Q_597___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_597__RX_DCOC_RES_Q_597___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_597___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_597___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_598 (0x005FC958) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_598___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_598___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_598__RX_DCOC_RANGE_598___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_598__RX_DCOC_RES_I_598___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_598__RX_DCOC_RES_Q_598___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_598__RX_DCOC_RANGE_598___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_598__RX_DCOC_RANGE_598___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_598__RX_DCOC_RES_I_598___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_598__RX_DCOC_RES_I_598___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_598__RX_DCOC_RES_Q_598___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_598__RX_DCOC_RES_Q_598___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_598___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_598___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_599 (0x005FC95C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_599___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_599___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_599__RX_DCOC_RANGE_599___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_599__RX_DCOC_RES_I_599___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_599__RX_DCOC_RES_Q_599___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_599__RX_DCOC_RANGE_599___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_599__RX_DCOC_RANGE_599___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_599__RX_DCOC_RES_I_599___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_599__RX_DCOC_RES_I_599___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_599__RX_DCOC_RES_Q_599___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_599__RX_DCOC_RES_Q_599___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_599___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_599___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_600 (0x005FC960) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_600___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_600___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_600__RX_DCOC_RANGE_600___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_600__RX_DCOC_RES_I_600___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_600__RX_DCOC_RES_Q_600___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_600__RX_DCOC_RANGE_600___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_600__RX_DCOC_RANGE_600___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_600__RX_DCOC_RES_I_600___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_600__RX_DCOC_RES_I_600___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_600__RX_DCOC_RES_Q_600___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_600__RX_DCOC_RES_Q_600___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_600___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_600___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_601 (0x005FC964) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_601___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_601___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_601__RX_DCOC_RANGE_601___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_601__RX_DCOC_RES_I_601___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_601__RX_DCOC_RES_Q_601___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_601__RX_DCOC_RANGE_601___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_601__RX_DCOC_RANGE_601___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_601__RX_DCOC_RES_I_601___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_601__RX_DCOC_RES_I_601___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_601__RX_DCOC_RES_Q_601___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_601__RX_DCOC_RES_Q_601___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_601___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_601___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_602 (0x005FC968) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_602___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_602___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_602__RX_DCOC_RANGE_602___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_602__RX_DCOC_RES_I_602___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_602__RX_DCOC_RES_Q_602___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_602__RX_DCOC_RANGE_602___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_602__RX_DCOC_RANGE_602___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_602__RX_DCOC_RES_I_602___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_602__RX_DCOC_RES_I_602___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_602__RX_DCOC_RES_Q_602___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_602__RX_DCOC_RES_Q_602___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_602___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_602___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_603 (0x005FC96C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_603___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_603___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_603__RX_DCOC_RANGE_603___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_603__RX_DCOC_RES_I_603___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_603__RX_DCOC_RES_Q_603___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_603__RX_DCOC_RANGE_603___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_603__RX_DCOC_RANGE_603___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_603__RX_DCOC_RES_I_603___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_603__RX_DCOC_RES_I_603___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_603__RX_DCOC_RES_Q_603___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_603__RX_DCOC_RES_Q_603___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_603___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_603___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_604 (0x005FC970) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_604___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_604___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_604__RX_DCOC_RANGE_604___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_604__RX_DCOC_RES_I_604___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_604__RX_DCOC_RES_Q_604___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_604__RX_DCOC_RANGE_604___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_604__RX_DCOC_RANGE_604___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_604__RX_DCOC_RES_I_604___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_604__RX_DCOC_RES_I_604___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_604__RX_DCOC_RES_Q_604___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_604__RX_DCOC_RES_Q_604___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_604___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_604___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_605 (0x005FC974) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_605___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_605___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_605__RX_DCOC_RANGE_605___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_605__RX_DCOC_RES_I_605___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_605__RX_DCOC_RES_Q_605___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_605__RX_DCOC_RANGE_605___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_605__RX_DCOC_RANGE_605___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_605__RX_DCOC_RES_I_605___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_605__RX_DCOC_RES_I_605___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_605__RX_DCOC_RES_Q_605___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_605__RX_DCOC_RES_Q_605___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_605___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_605___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_606 (0x005FC978) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_606___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_606___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_606__RX_DCOC_RANGE_606___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_606__RX_DCOC_RES_I_606___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_606__RX_DCOC_RES_Q_606___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_606__RX_DCOC_RANGE_606___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_606__RX_DCOC_RANGE_606___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_606__RX_DCOC_RES_I_606___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_606__RX_DCOC_RES_I_606___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_606__RX_DCOC_RES_Q_606___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_606__RX_DCOC_RES_Q_606___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_606___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_606___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_607 (0x005FC97C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_607___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_607___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_607__RX_DCOC_RANGE_607___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_607__RX_DCOC_RES_I_607___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_607__RX_DCOC_RES_Q_607___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_607__RX_DCOC_RANGE_607___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_607__RX_DCOC_RANGE_607___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_607__RX_DCOC_RES_I_607___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_607__RX_DCOC_RES_I_607___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_607__RX_DCOC_RES_Q_607___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_607__RX_DCOC_RES_Q_607___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_607___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_607___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_608 (0x005FC980) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_608___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_608___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_608__RX_DCOC_RANGE_608___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_608__RX_DCOC_RES_I_608___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_608__RX_DCOC_RES_Q_608___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_608__RX_DCOC_RANGE_608___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_608__RX_DCOC_RANGE_608___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_608__RX_DCOC_RES_I_608___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_608__RX_DCOC_RES_I_608___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_608__RX_DCOC_RES_Q_608___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_608__RX_DCOC_RES_Q_608___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_608___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_608___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_609 (0x005FC984) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_609___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_609___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_609__RX_DCOC_RANGE_609___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_609__RX_DCOC_RES_I_609___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_609__RX_DCOC_RES_Q_609___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_609__RX_DCOC_RANGE_609___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_609__RX_DCOC_RANGE_609___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_609__RX_DCOC_RES_I_609___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_609__RX_DCOC_RES_I_609___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_609__RX_DCOC_RES_Q_609___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_609__RX_DCOC_RES_Q_609___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_609___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_609___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_610 (0x005FC988) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_610___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_610___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_610__RX_DCOC_RANGE_610___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_610__RX_DCOC_RES_I_610___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_610__RX_DCOC_RES_Q_610___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_610__RX_DCOC_RANGE_610___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_610__RX_DCOC_RANGE_610___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_610__RX_DCOC_RES_I_610___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_610__RX_DCOC_RES_I_610___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_610__RX_DCOC_RES_Q_610___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_610__RX_DCOC_RES_Q_610___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_610___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_610___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_611 (0x005FC98C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_611___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_611___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_611__RX_DCOC_RANGE_611___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_611__RX_DCOC_RES_I_611___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_611__RX_DCOC_RES_Q_611___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_611__RX_DCOC_RANGE_611___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_611__RX_DCOC_RANGE_611___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_611__RX_DCOC_RES_I_611___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_611__RX_DCOC_RES_I_611___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_611__RX_DCOC_RES_Q_611___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_611__RX_DCOC_RES_Q_611___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_611___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_611___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_612 (0x005FC990) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_612___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_612___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_612__RX_DCOC_RANGE_612___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_612__RX_DCOC_RES_I_612___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_612__RX_DCOC_RES_Q_612___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_612__RX_DCOC_RANGE_612___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_612__RX_DCOC_RANGE_612___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_612__RX_DCOC_RES_I_612___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_612__RX_DCOC_RES_I_612___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_612__RX_DCOC_RES_Q_612___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_612__RX_DCOC_RES_Q_612___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_612___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_612___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_613 (0x005FC994) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_613___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_613___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_613__RX_DCOC_RANGE_613___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_613__RX_DCOC_RES_I_613___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_613__RX_DCOC_RES_Q_613___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_613__RX_DCOC_RANGE_613___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_613__RX_DCOC_RANGE_613___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_613__RX_DCOC_RES_I_613___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_613__RX_DCOC_RES_I_613___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_613__RX_DCOC_RES_Q_613___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_613__RX_DCOC_RES_Q_613___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_613___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_613___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_614 (0x005FC998) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_614___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_614___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_614__RX_DCOC_RANGE_614___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_614__RX_DCOC_RES_I_614___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_614__RX_DCOC_RES_Q_614___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_614__RX_DCOC_RANGE_614___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_614__RX_DCOC_RANGE_614___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_614__RX_DCOC_RES_I_614___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_614__RX_DCOC_RES_I_614___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_614__RX_DCOC_RES_Q_614___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_614__RX_DCOC_RES_Q_614___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_614___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_614___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_615 (0x005FC99C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_615___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_615___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_615__RX_DCOC_RANGE_615___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_615__RX_DCOC_RES_I_615___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_615__RX_DCOC_RES_Q_615___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_615__RX_DCOC_RANGE_615___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_615__RX_DCOC_RANGE_615___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_615__RX_DCOC_RES_I_615___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_615__RX_DCOC_RES_I_615___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_615__RX_DCOC_RES_Q_615___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_615__RX_DCOC_RES_Q_615___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_615___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_615___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_616 (0x005FC9A0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_616___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_616___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_616__RX_DCOC_RANGE_616___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_616__RX_DCOC_RES_I_616___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_616__RX_DCOC_RES_Q_616___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_616__RX_DCOC_RANGE_616___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_616__RX_DCOC_RANGE_616___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_616__RX_DCOC_RES_I_616___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_616__RX_DCOC_RES_I_616___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_616__RX_DCOC_RES_Q_616___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_616__RX_DCOC_RES_Q_616___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_616___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_616___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_617 (0x005FC9A4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_617___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_617___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_617__RX_DCOC_RANGE_617___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_617__RX_DCOC_RES_I_617___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_617__RX_DCOC_RES_Q_617___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_617__RX_DCOC_RANGE_617___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_617__RX_DCOC_RANGE_617___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_617__RX_DCOC_RES_I_617___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_617__RX_DCOC_RES_I_617___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_617__RX_DCOC_RES_Q_617___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_617__RX_DCOC_RES_Q_617___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_617___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_617___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_618 (0x005FC9A8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_618___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_618___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_618__RX_DCOC_RANGE_618___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_618__RX_DCOC_RES_I_618___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_618__RX_DCOC_RES_Q_618___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_618__RX_DCOC_RANGE_618___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_618__RX_DCOC_RANGE_618___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_618__RX_DCOC_RES_I_618___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_618__RX_DCOC_RES_I_618___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_618__RX_DCOC_RES_Q_618___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_618__RX_DCOC_RES_Q_618___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_618___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_618___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_619 (0x005FC9AC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_619___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_619___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_619__RX_DCOC_RANGE_619___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_619__RX_DCOC_RES_I_619___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_619__RX_DCOC_RES_Q_619___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_619__RX_DCOC_RANGE_619___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_619__RX_DCOC_RANGE_619___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_619__RX_DCOC_RES_I_619___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_619__RX_DCOC_RES_I_619___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_619__RX_DCOC_RES_Q_619___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_619__RX_DCOC_RES_Q_619___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_619___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_619___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_620 (0x005FC9B0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_620___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_620___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_620__RX_DCOC_RANGE_620___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_620__RX_DCOC_RES_I_620___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_620__RX_DCOC_RES_Q_620___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_620__RX_DCOC_RANGE_620___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_620__RX_DCOC_RANGE_620___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_620__RX_DCOC_RES_I_620___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_620__RX_DCOC_RES_I_620___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_620__RX_DCOC_RES_Q_620___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_620__RX_DCOC_RES_Q_620___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_620___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_620___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_621 (0x005FC9B4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_621___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_621___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_621__RX_DCOC_RANGE_621___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_621__RX_DCOC_RES_I_621___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_621__RX_DCOC_RES_Q_621___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_621__RX_DCOC_RANGE_621___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_621__RX_DCOC_RANGE_621___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_621__RX_DCOC_RES_I_621___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_621__RX_DCOC_RES_I_621___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_621__RX_DCOC_RES_Q_621___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_621__RX_DCOC_RES_Q_621___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_621___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_621___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_622 (0x005FC9B8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_622___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_622___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_622__RX_DCOC_RANGE_622___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_622__RX_DCOC_RES_I_622___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_622__RX_DCOC_RES_Q_622___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_622__RX_DCOC_RANGE_622___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_622__RX_DCOC_RANGE_622___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_622__RX_DCOC_RES_I_622___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_622__RX_DCOC_RES_I_622___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_622__RX_DCOC_RES_Q_622___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_622__RX_DCOC_RES_Q_622___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_622___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_622___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_623 (0x005FC9BC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_623___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_623___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_623__RX_DCOC_RANGE_623___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_623__RX_DCOC_RES_I_623___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_623__RX_DCOC_RES_Q_623___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_623__RX_DCOC_RANGE_623___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_623__RX_DCOC_RANGE_623___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_623__RX_DCOC_RES_I_623___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_623__RX_DCOC_RES_I_623___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_623__RX_DCOC_RES_Q_623___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_623__RX_DCOC_RES_Q_623___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_623___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_623___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_624 (0x005FC9C0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_624___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_624___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_624__RX_DCOC_RANGE_624___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_624__RX_DCOC_RES_I_624___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_624__RX_DCOC_RES_Q_624___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_624__RX_DCOC_RANGE_624___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_624__RX_DCOC_RANGE_624___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_624__RX_DCOC_RES_I_624___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_624__RX_DCOC_RES_I_624___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_624__RX_DCOC_RES_Q_624___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_624__RX_DCOC_RES_Q_624___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_624___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_624___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_625 (0x005FC9C4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_625___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_625___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_625__RX_DCOC_RANGE_625___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_625__RX_DCOC_RES_I_625___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_625__RX_DCOC_RES_Q_625___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_625__RX_DCOC_RANGE_625___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_625__RX_DCOC_RANGE_625___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_625__RX_DCOC_RES_I_625___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_625__RX_DCOC_RES_I_625___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_625__RX_DCOC_RES_Q_625___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_625__RX_DCOC_RES_Q_625___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_625___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_625___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_626 (0x005FC9C8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_626___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_626___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_626__RX_DCOC_RANGE_626___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_626__RX_DCOC_RES_I_626___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_626__RX_DCOC_RES_Q_626___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_626__RX_DCOC_RANGE_626___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_626__RX_DCOC_RANGE_626___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_626__RX_DCOC_RES_I_626___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_626__RX_DCOC_RES_I_626___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_626__RX_DCOC_RES_Q_626___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_626__RX_DCOC_RES_Q_626___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_626___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_626___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_627 (0x005FC9CC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_627___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_627___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_627__RX_DCOC_RANGE_627___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_627__RX_DCOC_RES_I_627___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_627__RX_DCOC_RES_Q_627___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_627__RX_DCOC_RANGE_627___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_627__RX_DCOC_RANGE_627___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_627__RX_DCOC_RES_I_627___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_627__RX_DCOC_RES_I_627___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_627__RX_DCOC_RES_Q_627___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_627__RX_DCOC_RES_Q_627___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_627___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_627___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_628 (0x005FC9D0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_628___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_628___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_628__RX_DCOC_RANGE_628___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_628__RX_DCOC_RES_I_628___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_628__RX_DCOC_RES_Q_628___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_628__RX_DCOC_RANGE_628___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_628__RX_DCOC_RANGE_628___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_628__RX_DCOC_RES_I_628___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_628__RX_DCOC_RES_I_628___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_628__RX_DCOC_RES_Q_628___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_628__RX_DCOC_RES_Q_628___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_628___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_628___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_629 (0x005FC9D4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_629___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_629___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_629__RX_DCOC_RANGE_629___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_629__RX_DCOC_RES_I_629___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_629__RX_DCOC_RES_Q_629___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_629__RX_DCOC_RANGE_629___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_629__RX_DCOC_RANGE_629___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_629__RX_DCOC_RES_I_629___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_629__RX_DCOC_RES_I_629___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_629__RX_DCOC_RES_Q_629___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_629__RX_DCOC_RES_Q_629___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_629___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_629___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_630 (0x005FC9D8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_630___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_630___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_630__RX_DCOC_RANGE_630___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_630__RX_DCOC_RES_I_630___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_630__RX_DCOC_RES_Q_630___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_630__RX_DCOC_RANGE_630___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_630__RX_DCOC_RANGE_630___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_630__RX_DCOC_RES_I_630___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_630__RX_DCOC_RES_I_630___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_630__RX_DCOC_RES_Q_630___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_630__RX_DCOC_RES_Q_630___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_630___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_630___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_631 (0x005FC9DC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_631___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_631___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_631__RX_DCOC_RANGE_631___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_631__RX_DCOC_RES_I_631___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_631__RX_DCOC_RES_Q_631___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_631__RX_DCOC_RANGE_631___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_631__RX_DCOC_RANGE_631___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_631__RX_DCOC_RES_I_631___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_631__RX_DCOC_RES_I_631___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_631__RX_DCOC_RES_Q_631___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_631__RX_DCOC_RES_Q_631___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_631___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_631___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_632 (0x005FC9E0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_632___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_632___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_632__RX_DCOC_RANGE_632___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_632__RX_DCOC_RES_I_632___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_632__RX_DCOC_RES_Q_632___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_632__RX_DCOC_RANGE_632___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_632__RX_DCOC_RANGE_632___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_632__RX_DCOC_RES_I_632___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_632__RX_DCOC_RES_I_632___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_632__RX_DCOC_RES_Q_632___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_632__RX_DCOC_RES_Q_632___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_632___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_632___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_633 (0x005FC9E4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_633___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_633___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_633__RX_DCOC_RANGE_633___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_633__RX_DCOC_RES_I_633___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_633__RX_DCOC_RES_Q_633___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_633__RX_DCOC_RANGE_633___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_633__RX_DCOC_RANGE_633___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_633__RX_DCOC_RES_I_633___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_633__RX_DCOC_RES_I_633___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_633__RX_DCOC_RES_Q_633___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_633__RX_DCOC_RES_Q_633___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_633___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_633___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_634 (0x005FC9E8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_634___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_634___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_634__RX_DCOC_RANGE_634___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_634__RX_DCOC_RES_I_634___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_634__RX_DCOC_RES_Q_634___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_634__RX_DCOC_RANGE_634___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_634__RX_DCOC_RANGE_634___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_634__RX_DCOC_RES_I_634___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_634__RX_DCOC_RES_I_634___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_634__RX_DCOC_RES_Q_634___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_634__RX_DCOC_RES_Q_634___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_634___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_634___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_635 (0x005FC9EC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_635___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_635___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_635__RX_DCOC_RANGE_635___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_635__RX_DCOC_RES_I_635___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_635__RX_DCOC_RES_Q_635___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_635__RX_DCOC_RANGE_635___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_635__RX_DCOC_RANGE_635___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_635__RX_DCOC_RES_I_635___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_635__RX_DCOC_RES_I_635___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_635__RX_DCOC_RES_Q_635___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_635__RX_DCOC_RES_Q_635___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_635___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_635___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_636 (0x005FC9F0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_636___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_636___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_636__RX_DCOC_RANGE_636___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_636__RX_DCOC_RES_I_636___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_636__RX_DCOC_RES_Q_636___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_636__RX_DCOC_RANGE_636___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_636__RX_DCOC_RANGE_636___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_636__RX_DCOC_RES_I_636___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_636__RX_DCOC_RES_I_636___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_636__RX_DCOC_RES_Q_636___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_636__RX_DCOC_RES_Q_636___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_636___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_636___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_637 (0x005FC9F4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_637___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_637___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_637__RX_DCOC_RANGE_637___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_637__RX_DCOC_RES_I_637___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_637__RX_DCOC_RES_Q_637___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_637__RX_DCOC_RANGE_637___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_637__RX_DCOC_RANGE_637___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_637__RX_DCOC_RES_I_637___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_637__RX_DCOC_RES_I_637___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_637__RX_DCOC_RES_Q_637___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_637__RX_DCOC_RES_Q_637___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_637___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_637___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_638 (0x005FC9F8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_638___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_638___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_638__RX_DCOC_RANGE_638___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_638__RX_DCOC_RES_I_638___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_638__RX_DCOC_RES_Q_638___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_638__RX_DCOC_RANGE_638___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_638__RX_DCOC_RANGE_638___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_638__RX_DCOC_RES_I_638___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_638__RX_DCOC_RES_I_638___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_638__RX_DCOC_RES_Q_638___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_638__RX_DCOC_RES_Q_638___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_638___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_638___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_639 (0x005FC9FC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_639___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_639___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_639__RX_DCOC_RANGE_639___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_639__RX_DCOC_RES_I_639___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_639__RX_DCOC_RES_Q_639___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_639__RX_DCOC_RANGE_639___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_639__RX_DCOC_RANGE_639___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_639__RX_DCOC_RES_I_639___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_639__RX_DCOC_RES_I_639___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_639__RX_DCOC_RES_Q_639___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_639__RX_DCOC_RES_Q_639___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_639___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_639___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_640 (0x005FCA00) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_640___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_640___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_640__RX_DCOC_RANGE_640___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_640__RX_DCOC_RES_I_640___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_640__RX_DCOC_RES_Q_640___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_640__RX_DCOC_RANGE_640___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_640__RX_DCOC_RANGE_640___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_640__RX_DCOC_RES_I_640___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_640__RX_DCOC_RES_I_640___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_640__RX_DCOC_RES_Q_640___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_640__RX_DCOC_RES_Q_640___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_640___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_640___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_641 (0x005FCA04) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_641___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_641___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_641__RX_DCOC_RANGE_641___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_641__RX_DCOC_RES_I_641___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_641__RX_DCOC_RES_Q_641___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_641__RX_DCOC_RANGE_641___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_641__RX_DCOC_RANGE_641___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_641__RX_DCOC_RES_I_641___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_641__RX_DCOC_RES_I_641___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_641__RX_DCOC_RES_Q_641___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_641__RX_DCOC_RES_Q_641___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_641___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_641___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_642 (0x005FCA08) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_642___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_642___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_642__RX_DCOC_RANGE_642___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_642__RX_DCOC_RES_I_642___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_642__RX_DCOC_RES_Q_642___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_642__RX_DCOC_RANGE_642___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_642__RX_DCOC_RANGE_642___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_642__RX_DCOC_RES_I_642___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_642__RX_DCOC_RES_I_642___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_642__RX_DCOC_RES_Q_642___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_642__RX_DCOC_RES_Q_642___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_642___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_642___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_643 (0x005FCA0C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_643___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_643___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_643__RX_DCOC_RANGE_643___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_643__RX_DCOC_RES_I_643___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_643__RX_DCOC_RES_Q_643___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_643__RX_DCOC_RANGE_643___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_643__RX_DCOC_RANGE_643___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_643__RX_DCOC_RES_I_643___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_643__RX_DCOC_RES_I_643___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_643__RX_DCOC_RES_Q_643___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_643__RX_DCOC_RES_Q_643___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_643___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_643___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_644 (0x005FCA10) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_644___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_644___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_644__RX_DCOC_RANGE_644___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_644__RX_DCOC_RES_I_644___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_644__RX_DCOC_RES_Q_644___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_644__RX_DCOC_RANGE_644___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_644__RX_DCOC_RANGE_644___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_644__RX_DCOC_RES_I_644___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_644__RX_DCOC_RES_I_644___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_644__RX_DCOC_RES_Q_644___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_644__RX_DCOC_RES_Q_644___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_644___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_644___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_645 (0x005FCA14) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_645___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_645___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_645__RX_DCOC_RANGE_645___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_645__RX_DCOC_RES_I_645___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_645__RX_DCOC_RES_Q_645___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_645__RX_DCOC_RANGE_645___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_645__RX_DCOC_RANGE_645___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_645__RX_DCOC_RES_I_645___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_645__RX_DCOC_RES_I_645___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_645__RX_DCOC_RES_Q_645___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_645__RX_DCOC_RES_Q_645___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_645___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_645___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_646 (0x005FCA18) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_646___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_646___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_646__RX_DCOC_RANGE_646___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_646__RX_DCOC_RES_I_646___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_646__RX_DCOC_RES_Q_646___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_646__RX_DCOC_RANGE_646___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_646__RX_DCOC_RANGE_646___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_646__RX_DCOC_RES_I_646___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_646__RX_DCOC_RES_I_646___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_646__RX_DCOC_RES_Q_646___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_646__RX_DCOC_RES_Q_646___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_646___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_646___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_647 (0x005FCA1C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_647___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_647___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_647__RX_DCOC_RANGE_647___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_647__RX_DCOC_RES_I_647___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_647__RX_DCOC_RES_Q_647___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_647__RX_DCOC_RANGE_647___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_647__RX_DCOC_RANGE_647___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_647__RX_DCOC_RES_I_647___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_647__RX_DCOC_RES_I_647___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_647__RX_DCOC_RES_Q_647___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_647__RX_DCOC_RES_Q_647___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_647___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_647___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_648 (0x005FCA20) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_648___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_648___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_648__RX_DCOC_RANGE_648___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_648__RX_DCOC_RES_I_648___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_648__RX_DCOC_RES_Q_648___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_648__RX_DCOC_RANGE_648___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_648__RX_DCOC_RANGE_648___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_648__RX_DCOC_RES_I_648___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_648__RX_DCOC_RES_I_648___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_648__RX_DCOC_RES_Q_648___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_648__RX_DCOC_RES_Q_648___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_648___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_648___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_649 (0x005FCA24) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_649___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_649___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_649__RX_DCOC_RANGE_649___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_649__RX_DCOC_RES_I_649___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_649__RX_DCOC_RES_Q_649___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_649__RX_DCOC_RANGE_649___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_649__RX_DCOC_RANGE_649___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_649__RX_DCOC_RES_I_649___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_649__RX_DCOC_RES_I_649___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_649__RX_DCOC_RES_Q_649___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_649__RX_DCOC_RES_Q_649___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_649___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_649___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_650 (0x005FCA28) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_650___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_650___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_650__RX_DCOC_RANGE_650___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_650__RX_DCOC_RES_I_650___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_650__RX_DCOC_RES_Q_650___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_650__RX_DCOC_RANGE_650___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_650__RX_DCOC_RANGE_650___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_650__RX_DCOC_RES_I_650___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_650__RX_DCOC_RES_I_650___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_650__RX_DCOC_RES_Q_650___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_650__RX_DCOC_RES_Q_650___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_650___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_650___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_651 (0x005FCA2C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_651___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_651___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_651__RX_DCOC_RANGE_651___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_651__RX_DCOC_RES_I_651___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_651__RX_DCOC_RES_Q_651___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_651__RX_DCOC_RANGE_651___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_651__RX_DCOC_RANGE_651___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_651__RX_DCOC_RES_I_651___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_651__RX_DCOC_RES_I_651___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_651__RX_DCOC_RES_Q_651___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_651__RX_DCOC_RES_Q_651___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_651___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_651___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_652 (0x005FCA30) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_652___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_652___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_652__RX_DCOC_RANGE_652___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_652__RX_DCOC_RES_I_652___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_652__RX_DCOC_RES_Q_652___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_652__RX_DCOC_RANGE_652___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_652__RX_DCOC_RANGE_652___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_652__RX_DCOC_RES_I_652___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_652__RX_DCOC_RES_I_652___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_652__RX_DCOC_RES_Q_652___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_652__RX_DCOC_RES_Q_652___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_652___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_652___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_653 (0x005FCA34) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_653___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_653___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_653__RX_DCOC_RANGE_653___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_653__RX_DCOC_RES_I_653___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_653__RX_DCOC_RES_Q_653___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_653__RX_DCOC_RANGE_653___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_653__RX_DCOC_RANGE_653___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_653__RX_DCOC_RES_I_653___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_653__RX_DCOC_RES_I_653___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_653__RX_DCOC_RES_Q_653___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_653__RX_DCOC_RES_Q_653___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_653___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_653___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_654 (0x005FCA38) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_654___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_654___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_654__RX_DCOC_RANGE_654___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_654__RX_DCOC_RES_I_654___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_654__RX_DCOC_RES_Q_654___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_654__RX_DCOC_RANGE_654___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_654__RX_DCOC_RANGE_654___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_654__RX_DCOC_RES_I_654___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_654__RX_DCOC_RES_I_654___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_654__RX_DCOC_RES_Q_654___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_654__RX_DCOC_RES_Q_654___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_654___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_654___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_655 (0x005FCA3C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_655___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_655___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_655__RX_DCOC_RANGE_655___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_655__RX_DCOC_RES_I_655___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_655__RX_DCOC_RES_Q_655___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_655__RX_DCOC_RANGE_655___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_655__RX_DCOC_RANGE_655___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_655__RX_DCOC_RES_I_655___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_655__RX_DCOC_RES_I_655___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_655__RX_DCOC_RES_Q_655___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_655__RX_DCOC_RES_Q_655___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_655___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_655___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_656 (0x005FCA40) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_656___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_656___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_656__RX_DCOC_RANGE_656___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_656__RX_DCOC_RES_I_656___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_656__RX_DCOC_RES_Q_656___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_656__RX_DCOC_RANGE_656___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_656__RX_DCOC_RANGE_656___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_656__RX_DCOC_RES_I_656___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_656__RX_DCOC_RES_I_656___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_656__RX_DCOC_RES_Q_656___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_656__RX_DCOC_RES_Q_656___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_656___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_656___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_657 (0x005FCA44) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_657___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_657___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_657__RX_DCOC_RANGE_657___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_657__RX_DCOC_RES_I_657___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_657__RX_DCOC_RES_Q_657___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_657__RX_DCOC_RANGE_657___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_657__RX_DCOC_RANGE_657___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_657__RX_DCOC_RES_I_657___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_657__RX_DCOC_RES_I_657___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_657__RX_DCOC_RES_Q_657___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_657__RX_DCOC_RES_Q_657___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_657___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_657___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_658 (0x005FCA48) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_658___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_658___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_658__RX_DCOC_RANGE_658___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_658__RX_DCOC_RES_I_658___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_658__RX_DCOC_RES_Q_658___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_658__RX_DCOC_RANGE_658___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_658__RX_DCOC_RANGE_658___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_658__RX_DCOC_RES_I_658___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_658__RX_DCOC_RES_I_658___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_658__RX_DCOC_RES_Q_658___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_658__RX_DCOC_RES_Q_658___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_658___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_658___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_659 (0x005FCA4C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_659___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_659___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_659__RX_DCOC_RANGE_659___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_659__RX_DCOC_RES_I_659___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_659__RX_DCOC_RES_Q_659___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_659__RX_DCOC_RANGE_659___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_659__RX_DCOC_RANGE_659___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_659__RX_DCOC_RES_I_659___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_659__RX_DCOC_RES_I_659___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_659__RX_DCOC_RES_Q_659___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_659__RX_DCOC_RES_Q_659___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_659___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_659___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_660 (0x005FCA50) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_660___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_660___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_660__RX_DCOC_RANGE_660___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_660__RX_DCOC_RES_I_660___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_660__RX_DCOC_RES_Q_660___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_660__RX_DCOC_RANGE_660___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_660__RX_DCOC_RANGE_660___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_660__RX_DCOC_RES_I_660___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_660__RX_DCOC_RES_I_660___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_660__RX_DCOC_RES_Q_660___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_660__RX_DCOC_RES_Q_660___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_660___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_660___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_661 (0x005FCA54) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_661___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_661___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_661__RX_DCOC_RANGE_661___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_661__RX_DCOC_RES_I_661___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_661__RX_DCOC_RES_Q_661___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_661__RX_DCOC_RANGE_661___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_661__RX_DCOC_RANGE_661___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_661__RX_DCOC_RES_I_661___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_661__RX_DCOC_RES_I_661___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_661__RX_DCOC_RES_Q_661___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_661__RX_DCOC_RES_Q_661___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_661___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_661___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_662 (0x005FCA58) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_662___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_662___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_662__RX_DCOC_RANGE_662___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_662__RX_DCOC_RES_I_662___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_662__RX_DCOC_RES_Q_662___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_662__RX_DCOC_RANGE_662___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_662__RX_DCOC_RANGE_662___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_662__RX_DCOC_RES_I_662___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_662__RX_DCOC_RES_I_662___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_662__RX_DCOC_RES_Q_662___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_662__RX_DCOC_RES_Q_662___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_662___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_662___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_663 (0x005FCA5C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_663___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_663___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_663__RX_DCOC_RANGE_663___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_663__RX_DCOC_RES_I_663___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_663__RX_DCOC_RES_Q_663___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_663__RX_DCOC_RANGE_663___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_663__RX_DCOC_RANGE_663___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_663__RX_DCOC_RES_I_663___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_663__RX_DCOC_RES_I_663___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_663__RX_DCOC_RES_Q_663___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_663__RX_DCOC_RES_Q_663___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_663___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_663___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_664 (0x005FCA60) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_664___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_664___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_664__RX_DCOC_RANGE_664___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_664__RX_DCOC_RES_I_664___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_664__RX_DCOC_RES_Q_664___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_664__RX_DCOC_RANGE_664___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_664__RX_DCOC_RANGE_664___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_664__RX_DCOC_RES_I_664___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_664__RX_DCOC_RES_I_664___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_664__RX_DCOC_RES_Q_664___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_664__RX_DCOC_RES_Q_664___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_664___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_664___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_665 (0x005FCA64) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_665___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_665___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_665__RX_DCOC_RANGE_665___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_665__RX_DCOC_RES_I_665___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_665__RX_DCOC_RES_Q_665___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_665__RX_DCOC_RANGE_665___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_665__RX_DCOC_RANGE_665___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_665__RX_DCOC_RES_I_665___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_665__RX_DCOC_RES_I_665___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_665__RX_DCOC_RES_Q_665___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_665__RX_DCOC_RES_Q_665___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_665___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_665___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_666 (0x005FCA68) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_666___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_666___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_666__RX_DCOC_RANGE_666___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_666__RX_DCOC_RES_I_666___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_666__RX_DCOC_RES_Q_666___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_666__RX_DCOC_RANGE_666___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_666__RX_DCOC_RANGE_666___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_666__RX_DCOC_RES_I_666___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_666__RX_DCOC_RES_I_666___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_666__RX_DCOC_RES_Q_666___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_666__RX_DCOC_RES_Q_666___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_666___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_666___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_667 (0x005FCA6C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_667___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_667___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_667__RX_DCOC_RANGE_667___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_667__RX_DCOC_RES_I_667___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_667__RX_DCOC_RES_Q_667___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_667__RX_DCOC_RANGE_667___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_667__RX_DCOC_RANGE_667___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_667__RX_DCOC_RES_I_667___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_667__RX_DCOC_RES_I_667___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_667__RX_DCOC_RES_Q_667___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_667__RX_DCOC_RES_Q_667___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_667___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_667___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_668 (0x005FCA70) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_668___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_668___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_668__RX_DCOC_RANGE_668___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_668__RX_DCOC_RES_I_668___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_668__RX_DCOC_RES_Q_668___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_668__RX_DCOC_RANGE_668___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_668__RX_DCOC_RANGE_668___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_668__RX_DCOC_RES_I_668___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_668__RX_DCOC_RES_I_668___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_668__RX_DCOC_RES_Q_668___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_668__RX_DCOC_RES_Q_668___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_668___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_668___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_669 (0x005FCA74) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_669___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_669___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_669__RX_DCOC_RANGE_669___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_669__RX_DCOC_RES_I_669___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_669__RX_DCOC_RES_Q_669___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_669__RX_DCOC_RANGE_669___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_669__RX_DCOC_RANGE_669___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_669__RX_DCOC_RES_I_669___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_669__RX_DCOC_RES_I_669___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_669__RX_DCOC_RES_Q_669___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_669__RX_DCOC_RES_Q_669___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_669___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_669___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_670 (0x005FCA78) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_670___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_670___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_670__RX_DCOC_RANGE_670___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_670__RX_DCOC_RES_I_670___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_670__RX_DCOC_RES_Q_670___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_670__RX_DCOC_RANGE_670___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_670__RX_DCOC_RANGE_670___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_670__RX_DCOC_RES_I_670___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_670__RX_DCOC_RES_I_670___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_670__RX_DCOC_RES_Q_670___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_670__RX_DCOC_RES_Q_670___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_670___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_670___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_671 (0x005FCA7C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_671___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_671___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_671__RX_DCOC_RANGE_671___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_671__RX_DCOC_RES_I_671___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_671__RX_DCOC_RES_Q_671___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_671__RX_DCOC_RANGE_671___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_671__RX_DCOC_RANGE_671___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_671__RX_DCOC_RES_I_671___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_671__RX_DCOC_RES_I_671___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_671__RX_DCOC_RES_Q_671___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_671__RX_DCOC_RES_Q_671___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_671___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_671___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_672 (0x005FCA80) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_672___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_672___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_672__RX_DCOC_RANGE_672___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_672__RX_DCOC_RES_I_672___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_672__RX_DCOC_RES_Q_672___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_672__RX_DCOC_RANGE_672___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_672__RX_DCOC_RANGE_672___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_672__RX_DCOC_RES_I_672___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_672__RX_DCOC_RES_I_672___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_672__RX_DCOC_RES_Q_672___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_672__RX_DCOC_RES_Q_672___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_672___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_672___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_673 (0x005FCA84) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_673___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_673___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_673__RX_DCOC_RANGE_673___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_673__RX_DCOC_RES_I_673___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_673__RX_DCOC_RES_Q_673___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_673__RX_DCOC_RANGE_673___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_673__RX_DCOC_RANGE_673___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_673__RX_DCOC_RES_I_673___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_673__RX_DCOC_RES_I_673___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_673__RX_DCOC_RES_Q_673___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_673__RX_DCOC_RES_Q_673___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_673___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_673___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_674 (0x005FCA88) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_674___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_674___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_674__RX_DCOC_RANGE_674___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_674__RX_DCOC_RES_I_674___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_674__RX_DCOC_RES_Q_674___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_674__RX_DCOC_RANGE_674___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_674__RX_DCOC_RANGE_674___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_674__RX_DCOC_RES_I_674___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_674__RX_DCOC_RES_I_674___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_674__RX_DCOC_RES_Q_674___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_674__RX_DCOC_RES_Q_674___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_674___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_674___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_675 (0x005FCA8C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_675___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_675___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_675__RX_DCOC_RANGE_675___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_675__RX_DCOC_RES_I_675___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_675__RX_DCOC_RES_Q_675___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_675__RX_DCOC_RANGE_675___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_675__RX_DCOC_RANGE_675___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_675__RX_DCOC_RES_I_675___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_675__RX_DCOC_RES_I_675___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_675__RX_DCOC_RES_Q_675___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_675__RX_DCOC_RES_Q_675___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_675___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_675___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_676 (0x005FCA90) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_676___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_676___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_676__RX_DCOC_RANGE_676___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_676__RX_DCOC_RES_I_676___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_676__RX_DCOC_RES_Q_676___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_676__RX_DCOC_RANGE_676___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_676__RX_DCOC_RANGE_676___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_676__RX_DCOC_RES_I_676___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_676__RX_DCOC_RES_I_676___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_676__RX_DCOC_RES_Q_676___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_676__RX_DCOC_RES_Q_676___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_676___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_676___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_677 (0x005FCA94) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_677___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_677___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_677__RX_DCOC_RANGE_677___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_677__RX_DCOC_RES_I_677___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_677__RX_DCOC_RES_Q_677___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_677__RX_DCOC_RANGE_677___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_677__RX_DCOC_RANGE_677___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_677__RX_DCOC_RES_I_677___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_677__RX_DCOC_RES_I_677___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_677__RX_DCOC_RES_Q_677___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_677__RX_DCOC_RES_Q_677___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_677___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_677___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_678 (0x005FCA98) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_678___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_678___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_678__RX_DCOC_RANGE_678___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_678__RX_DCOC_RES_I_678___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_678__RX_DCOC_RES_Q_678___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_678__RX_DCOC_RANGE_678___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_678__RX_DCOC_RANGE_678___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_678__RX_DCOC_RES_I_678___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_678__RX_DCOC_RES_I_678___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_678__RX_DCOC_RES_Q_678___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_678__RX_DCOC_RES_Q_678___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_678___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_678___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_679 (0x005FCA9C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_679___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_679___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_679__RX_DCOC_RANGE_679___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_679__RX_DCOC_RES_I_679___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_679__RX_DCOC_RES_Q_679___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_679__RX_DCOC_RANGE_679___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_679__RX_DCOC_RANGE_679___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_679__RX_DCOC_RES_I_679___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_679__RX_DCOC_RES_I_679___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_679__RX_DCOC_RES_Q_679___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_679__RX_DCOC_RES_Q_679___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_679___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_679___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_680 (0x005FCAA0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_680___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_680___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_680__RX_DCOC_RANGE_680___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_680__RX_DCOC_RES_I_680___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_680__RX_DCOC_RES_Q_680___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_680__RX_DCOC_RANGE_680___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_680__RX_DCOC_RANGE_680___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_680__RX_DCOC_RES_I_680___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_680__RX_DCOC_RES_I_680___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_680__RX_DCOC_RES_Q_680___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_680__RX_DCOC_RES_Q_680___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_680___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_680___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_681 (0x005FCAA4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_681___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_681___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_681__RX_DCOC_RANGE_681___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_681__RX_DCOC_RES_I_681___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_681__RX_DCOC_RES_Q_681___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_681__RX_DCOC_RANGE_681___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_681__RX_DCOC_RANGE_681___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_681__RX_DCOC_RES_I_681___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_681__RX_DCOC_RES_I_681___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_681__RX_DCOC_RES_Q_681___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_681__RX_DCOC_RES_Q_681___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_681___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_681___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_682 (0x005FCAA8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_682___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_682___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_682__RX_DCOC_RANGE_682___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_682__RX_DCOC_RES_I_682___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_682__RX_DCOC_RES_Q_682___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_682__RX_DCOC_RANGE_682___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_682__RX_DCOC_RANGE_682___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_682__RX_DCOC_RES_I_682___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_682__RX_DCOC_RES_I_682___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_682__RX_DCOC_RES_Q_682___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_682__RX_DCOC_RES_Q_682___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_682___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_682___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_683 (0x005FCAAC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_683___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_683___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_683__RX_DCOC_RANGE_683___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_683__RX_DCOC_RES_I_683___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_683__RX_DCOC_RES_Q_683___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_683__RX_DCOC_RANGE_683___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_683__RX_DCOC_RANGE_683___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_683__RX_DCOC_RES_I_683___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_683__RX_DCOC_RES_I_683___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_683__RX_DCOC_RES_Q_683___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_683__RX_DCOC_RES_Q_683___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_683___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_683___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_684 (0x005FCAB0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_684___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_684___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_684__RX_DCOC_RANGE_684___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_684__RX_DCOC_RES_I_684___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_684__RX_DCOC_RES_Q_684___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_684__RX_DCOC_RANGE_684___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_684__RX_DCOC_RANGE_684___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_684__RX_DCOC_RES_I_684___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_684__RX_DCOC_RES_I_684___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_684__RX_DCOC_RES_Q_684___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_684__RX_DCOC_RES_Q_684___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_684___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_684___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_685 (0x005FCAB4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_685___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_685___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_685__RX_DCOC_RANGE_685___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_685__RX_DCOC_RES_I_685___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_685__RX_DCOC_RES_Q_685___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_685__RX_DCOC_RANGE_685___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_685__RX_DCOC_RANGE_685___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_685__RX_DCOC_RES_I_685___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_685__RX_DCOC_RES_I_685___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_685__RX_DCOC_RES_Q_685___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_685__RX_DCOC_RES_Q_685___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_685___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_685___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_686 (0x005FCAB8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_686___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_686___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_686__RX_DCOC_RANGE_686___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_686__RX_DCOC_RES_I_686___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_686__RX_DCOC_RES_Q_686___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_686__RX_DCOC_RANGE_686___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_686__RX_DCOC_RANGE_686___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_686__RX_DCOC_RES_I_686___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_686__RX_DCOC_RES_I_686___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_686__RX_DCOC_RES_Q_686___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_686__RX_DCOC_RES_Q_686___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_686___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_686___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_687 (0x005FCABC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_687___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_687___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_687__RX_DCOC_RANGE_687___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_687__RX_DCOC_RES_I_687___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_687__RX_DCOC_RES_Q_687___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_687__RX_DCOC_RANGE_687___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_687__RX_DCOC_RANGE_687___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_687__RX_DCOC_RES_I_687___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_687__RX_DCOC_RES_I_687___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_687__RX_DCOC_RES_Q_687___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_687__RX_DCOC_RES_Q_687___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_687___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_687___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_688 (0x005FCAC0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_688___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_688___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_688__RX_DCOC_RANGE_688___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_688__RX_DCOC_RES_I_688___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_688__RX_DCOC_RES_Q_688___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_688__RX_DCOC_RANGE_688___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_688__RX_DCOC_RANGE_688___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_688__RX_DCOC_RES_I_688___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_688__RX_DCOC_RES_I_688___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_688__RX_DCOC_RES_Q_688___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_688__RX_DCOC_RES_Q_688___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_688___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_688___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_689 (0x005FCAC4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_689___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_689___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_689__RX_DCOC_RANGE_689___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_689__RX_DCOC_RES_I_689___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_689__RX_DCOC_RES_Q_689___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_689__RX_DCOC_RANGE_689___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_689__RX_DCOC_RANGE_689___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_689__RX_DCOC_RES_I_689___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_689__RX_DCOC_RES_I_689___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_689__RX_DCOC_RES_Q_689___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_689__RX_DCOC_RES_Q_689___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_689___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_689___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_690 (0x005FCAC8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_690___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_690___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_690__RX_DCOC_RANGE_690___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_690__RX_DCOC_RES_I_690___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_690__RX_DCOC_RES_Q_690___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_690__RX_DCOC_RANGE_690___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_690__RX_DCOC_RANGE_690___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_690__RX_DCOC_RES_I_690___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_690__RX_DCOC_RES_I_690___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_690__RX_DCOC_RES_Q_690___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_690__RX_DCOC_RES_Q_690___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_690___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_690___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_691 (0x005FCACC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_691___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_691___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_691__RX_DCOC_RANGE_691___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_691__RX_DCOC_RES_I_691___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_691__RX_DCOC_RES_Q_691___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_691__RX_DCOC_RANGE_691___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_691__RX_DCOC_RANGE_691___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_691__RX_DCOC_RES_I_691___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_691__RX_DCOC_RES_I_691___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_691__RX_DCOC_RES_Q_691___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_691__RX_DCOC_RES_Q_691___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_691___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_691___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_692 (0x005FCAD0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_692___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_692___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_692__RX_DCOC_RANGE_692___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_692__RX_DCOC_RES_I_692___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_692__RX_DCOC_RES_Q_692___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_692__RX_DCOC_RANGE_692___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_692__RX_DCOC_RANGE_692___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_692__RX_DCOC_RES_I_692___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_692__RX_DCOC_RES_I_692___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_692__RX_DCOC_RES_Q_692___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_692__RX_DCOC_RES_Q_692___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_692___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_692___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_693 (0x005FCAD4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_693___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_693___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_693__RX_DCOC_RANGE_693___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_693__RX_DCOC_RES_I_693___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_693__RX_DCOC_RES_Q_693___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_693__RX_DCOC_RANGE_693___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_693__RX_DCOC_RANGE_693___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_693__RX_DCOC_RES_I_693___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_693__RX_DCOC_RES_I_693___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_693__RX_DCOC_RES_Q_693___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_693__RX_DCOC_RES_Q_693___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_693___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_693___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_694 (0x005FCAD8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_694___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_694___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_694__RX_DCOC_RANGE_694___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_694__RX_DCOC_RES_I_694___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_694__RX_DCOC_RES_Q_694___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_694__RX_DCOC_RANGE_694___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_694__RX_DCOC_RANGE_694___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_694__RX_DCOC_RES_I_694___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_694__RX_DCOC_RES_I_694___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_694__RX_DCOC_RES_Q_694___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_694__RX_DCOC_RES_Q_694___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_694___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_694___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_695 (0x005FCADC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_695___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_695___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_695__RX_DCOC_RANGE_695___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_695__RX_DCOC_RES_I_695___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_695__RX_DCOC_RES_Q_695___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_695__RX_DCOC_RANGE_695___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_695__RX_DCOC_RANGE_695___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_695__RX_DCOC_RES_I_695___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_695__RX_DCOC_RES_I_695___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_695__RX_DCOC_RES_Q_695___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_695__RX_DCOC_RES_Q_695___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_695___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_695___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_696 (0x005FCAE0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_696___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_696___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_696__RX_DCOC_RANGE_696___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_696__RX_DCOC_RES_I_696___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_696__RX_DCOC_RES_Q_696___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_696__RX_DCOC_RANGE_696___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_696__RX_DCOC_RANGE_696___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_696__RX_DCOC_RES_I_696___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_696__RX_DCOC_RES_I_696___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_696__RX_DCOC_RES_Q_696___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_696__RX_DCOC_RES_Q_696___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_696___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_696___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_697 (0x005FCAE4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_697___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_697___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_697__RX_DCOC_RANGE_697___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_697__RX_DCOC_RES_I_697___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_697__RX_DCOC_RES_Q_697___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_697__RX_DCOC_RANGE_697___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_697__RX_DCOC_RANGE_697___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_697__RX_DCOC_RES_I_697___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_697__RX_DCOC_RES_I_697___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_697__RX_DCOC_RES_Q_697___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_697__RX_DCOC_RES_Q_697___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_697___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_697___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_698 (0x005FCAE8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_698___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_698___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_698__RX_DCOC_RANGE_698___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_698__RX_DCOC_RES_I_698___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_698__RX_DCOC_RES_Q_698___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_698__RX_DCOC_RANGE_698___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_698__RX_DCOC_RANGE_698___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_698__RX_DCOC_RES_I_698___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_698__RX_DCOC_RES_I_698___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_698__RX_DCOC_RES_Q_698___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_698__RX_DCOC_RES_Q_698___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_698___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_698___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_699 (0x005FCAEC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_699___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_699___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_699__RX_DCOC_RANGE_699___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_699__RX_DCOC_RES_I_699___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_699__RX_DCOC_RES_Q_699___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_699__RX_DCOC_RANGE_699___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_699__RX_DCOC_RANGE_699___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_699__RX_DCOC_RES_I_699___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_699__RX_DCOC_RES_I_699___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_699__RX_DCOC_RES_Q_699___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_699__RX_DCOC_RES_Q_699___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_699___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_699___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_700 (0x005FCAF0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_700___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_700___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_700__RX_DCOC_RANGE_700___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_700__RX_DCOC_RES_I_700___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_700__RX_DCOC_RES_Q_700___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_700__RX_DCOC_RANGE_700___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_700__RX_DCOC_RANGE_700___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_700__RX_DCOC_RES_I_700___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_700__RX_DCOC_RES_I_700___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_700__RX_DCOC_RES_Q_700___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_700__RX_DCOC_RES_Q_700___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_700___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_700___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_701 (0x005FCAF4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_701___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_701___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_701__RX_DCOC_RANGE_701___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_701__RX_DCOC_RES_I_701___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_701__RX_DCOC_RES_Q_701___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_701__RX_DCOC_RANGE_701___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_701__RX_DCOC_RANGE_701___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_701__RX_DCOC_RES_I_701___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_701__RX_DCOC_RES_I_701___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_701__RX_DCOC_RES_Q_701___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_701__RX_DCOC_RES_Q_701___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_701___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_701___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_702 (0x005FCAF8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_702___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_702___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_702__RX_DCOC_RANGE_702___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_702__RX_DCOC_RES_I_702___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_702__RX_DCOC_RES_Q_702___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_702__RX_DCOC_RANGE_702___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_702__RX_DCOC_RANGE_702___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_702__RX_DCOC_RES_I_702___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_702__RX_DCOC_RES_I_702___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_702__RX_DCOC_RES_Q_702___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_702__RX_DCOC_RES_Q_702___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_702___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_702___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_703 (0x005FCAFC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_703___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_703___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_703__RX_DCOC_RANGE_703___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_703__RX_DCOC_RES_I_703___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_703__RX_DCOC_RES_Q_703___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_703__RX_DCOC_RANGE_703___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_703__RX_DCOC_RANGE_703___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_703__RX_DCOC_RES_I_703___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_703__RX_DCOC_RES_I_703___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_703__RX_DCOC_RES_Q_703___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_703__RX_DCOC_RES_Q_703___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_703___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_703___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_704 (0x005FCB00) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_704___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_704___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_704__RX_DCOC_RANGE_704___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_704__RX_DCOC_RES_I_704___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_704__RX_DCOC_RES_Q_704___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_704__RX_DCOC_RANGE_704___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_704__RX_DCOC_RANGE_704___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_704__RX_DCOC_RES_I_704___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_704__RX_DCOC_RES_I_704___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_704__RX_DCOC_RES_Q_704___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_704__RX_DCOC_RES_Q_704___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_704___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_704___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_705 (0x005FCB04) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_705___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_705___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_705__RX_DCOC_RANGE_705___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_705__RX_DCOC_RES_I_705___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_705__RX_DCOC_RES_Q_705___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_705__RX_DCOC_RANGE_705___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_705__RX_DCOC_RANGE_705___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_705__RX_DCOC_RES_I_705___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_705__RX_DCOC_RES_I_705___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_705__RX_DCOC_RES_Q_705___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_705__RX_DCOC_RES_Q_705___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_705___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_705___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_706 (0x005FCB08) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_706___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_706___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_706__RX_DCOC_RANGE_706___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_706__RX_DCOC_RES_I_706___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_706__RX_DCOC_RES_Q_706___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_706__RX_DCOC_RANGE_706___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_706__RX_DCOC_RANGE_706___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_706__RX_DCOC_RES_I_706___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_706__RX_DCOC_RES_I_706___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_706__RX_DCOC_RES_Q_706___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_706__RX_DCOC_RES_Q_706___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_706___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_706___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_707 (0x005FCB0C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_707___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_707___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_707__RX_DCOC_RANGE_707___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_707__RX_DCOC_RES_I_707___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_707__RX_DCOC_RES_Q_707___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_707__RX_DCOC_RANGE_707___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_707__RX_DCOC_RANGE_707___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_707__RX_DCOC_RES_I_707___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_707__RX_DCOC_RES_I_707___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_707__RX_DCOC_RES_Q_707___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_707__RX_DCOC_RES_Q_707___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_707___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_707___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_708 (0x005FCB10) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_708___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_708___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_708__RX_DCOC_RANGE_708___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_708__RX_DCOC_RES_I_708___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_708__RX_DCOC_RES_Q_708___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_708__RX_DCOC_RANGE_708___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_708__RX_DCOC_RANGE_708___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_708__RX_DCOC_RES_I_708___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_708__RX_DCOC_RES_I_708___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_708__RX_DCOC_RES_Q_708___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_708__RX_DCOC_RES_Q_708___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_708___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_708___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_709 (0x005FCB14) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_709___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_709___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_709__RX_DCOC_RANGE_709___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_709__RX_DCOC_RES_I_709___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_709__RX_DCOC_RES_Q_709___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_709__RX_DCOC_RANGE_709___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_709__RX_DCOC_RANGE_709___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_709__RX_DCOC_RES_I_709___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_709__RX_DCOC_RES_I_709___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_709__RX_DCOC_RES_Q_709___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_709__RX_DCOC_RES_Q_709___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_709___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_709___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_710 (0x005FCB18) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_710___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_710___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_710__RX_DCOC_RANGE_710___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_710__RX_DCOC_RES_I_710___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_710__RX_DCOC_RES_Q_710___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_710__RX_DCOC_RANGE_710___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_710__RX_DCOC_RANGE_710___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_710__RX_DCOC_RES_I_710___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_710__RX_DCOC_RES_I_710___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_710__RX_DCOC_RES_Q_710___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_710__RX_DCOC_RES_Q_710___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_710___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_710___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_711 (0x005FCB1C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_711___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_711___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_711__RX_DCOC_RANGE_711___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_711__RX_DCOC_RES_I_711___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_711__RX_DCOC_RES_Q_711___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_711__RX_DCOC_RANGE_711___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_711__RX_DCOC_RANGE_711___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_711__RX_DCOC_RES_I_711___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_711__RX_DCOC_RES_I_711___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_711__RX_DCOC_RES_Q_711___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_711__RX_DCOC_RES_Q_711___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_711___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_711___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_712 (0x005FCB20) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_712___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_712___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_712__RX_DCOC_RANGE_712___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_712__RX_DCOC_RES_I_712___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_712__RX_DCOC_RES_Q_712___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_712__RX_DCOC_RANGE_712___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_712__RX_DCOC_RANGE_712___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_712__RX_DCOC_RES_I_712___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_712__RX_DCOC_RES_I_712___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_712__RX_DCOC_RES_Q_712___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_712__RX_DCOC_RES_Q_712___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_712___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_712___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_713 (0x005FCB24) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_713___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_713___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_713__RX_DCOC_RANGE_713___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_713__RX_DCOC_RES_I_713___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_713__RX_DCOC_RES_Q_713___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_713__RX_DCOC_RANGE_713___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_713__RX_DCOC_RANGE_713___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_713__RX_DCOC_RES_I_713___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_713__RX_DCOC_RES_I_713___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_713__RX_DCOC_RES_Q_713___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_713__RX_DCOC_RES_Q_713___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_713___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_713___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_714 (0x005FCB28) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_714___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_714___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_714__RX_DCOC_RANGE_714___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_714__RX_DCOC_RES_I_714___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_714__RX_DCOC_RES_Q_714___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_714__RX_DCOC_RANGE_714___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_714__RX_DCOC_RANGE_714___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_714__RX_DCOC_RES_I_714___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_714__RX_DCOC_RES_I_714___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_714__RX_DCOC_RES_Q_714___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_714__RX_DCOC_RES_Q_714___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_714___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_714___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_715 (0x005FCB2C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_715___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_715___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_715__RX_DCOC_RANGE_715___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_715__RX_DCOC_RES_I_715___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_715__RX_DCOC_RES_Q_715___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_715__RX_DCOC_RANGE_715___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_715__RX_DCOC_RANGE_715___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_715__RX_DCOC_RES_I_715___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_715__RX_DCOC_RES_I_715___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_715__RX_DCOC_RES_Q_715___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_715__RX_DCOC_RES_Q_715___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_715___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_715___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_716 (0x005FCB30) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_716___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_716___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_716__RX_DCOC_RANGE_716___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_716__RX_DCOC_RES_I_716___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_716__RX_DCOC_RES_Q_716___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_716__RX_DCOC_RANGE_716___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_716__RX_DCOC_RANGE_716___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_716__RX_DCOC_RES_I_716___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_716__RX_DCOC_RES_I_716___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_716__RX_DCOC_RES_Q_716___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_716__RX_DCOC_RES_Q_716___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_716___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_716___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_717 (0x005FCB34) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_717___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_717___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_717__RX_DCOC_RANGE_717___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_717__RX_DCOC_RES_I_717___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_717__RX_DCOC_RES_Q_717___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_717__RX_DCOC_RANGE_717___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_717__RX_DCOC_RANGE_717___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_717__RX_DCOC_RES_I_717___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_717__RX_DCOC_RES_I_717___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_717__RX_DCOC_RES_Q_717___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_717__RX_DCOC_RES_Q_717___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_717___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_717___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_718 (0x005FCB38) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_718___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_718___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_718__RX_DCOC_RANGE_718___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_718__RX_DCOC_RES_I_718___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_718__RX_DCOC_RES_Q_718___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_718__RX_DCOC_RANGE_718___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_718__RX_DCOC_RANGE_718___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_718__RX_DCOC_RES_I_718___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_718__RX_DCOC_RES_I_718___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_718__RX_DCOC_RES_Q_718___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_718__RX_DCOC_RES_Q_718___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_718___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_718___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_719 (0x005FCB3C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_719___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_719___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_719__RX_DCOC_RANGE_719___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_719__RX_DCOC_RES_I_719___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_719__RX_DCOC_RES_Q_719___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_719__RX_DCOC_RANGE_719___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_719__RX_DCOC_RANGE_719___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_719__RX_DCOC_RES_I_719___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_719__RX_DCOC_RES_I_719___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_719__RX_DCOC_RES_Q_719___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_719__RX_DCOC_RES_Q_719___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_719___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_719___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_720 (0x005FCB40) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_720___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_720___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_720__RX_DCOC_RANGE_720___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_720__RX_DCOC_RES_I_720___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_720__RX_DCOC_RES_Q_720___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_720__RX_DCOC_RANGE_720___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_720__RX_DCOC_RANGE_720___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_720__RX_DCOC_RES_I_720___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_720__RX_DCOC_RES_I_720___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_720__RX_DCOC_RES_Q_720___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_720__RX_DCOC_RES_Q_720___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_720___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_720___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_721 (0x005FCB44) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_721___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_721___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_721__RX_DCOC_RANGE_721___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_721__RX_DCOC_RES_I_721___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_721__RX_DCOC_RES_Q_721___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_721__RX_DCOC_RANGE_721___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_721__RX_DCOC_RANGE_721___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_721__RX_DCOC_RES_I_721___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_721__RX_DCOC_RES_I_721___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_721__RX_DCOC_RES_Q_721___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_721__RX_DCOC_RES_Q_721___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_721___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_721___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_722 (0x005FCB48) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_722___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_722___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_722__RX_DCOC_RANGE_722___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_722__RX_DCOC_RES_I_722___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_722__RX_DCOC_RES_Q_722___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_722__RX_DCOC_RANGE_722___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_722__RX_DCOC_RANGE_722___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_722__RX_DCOC_RES_I_722___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_722__RX_DCOC_RES_I_722___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_722__RX_DCOC_RES_Q_722___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_722__RX_DCOC_RES_Q_722___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_722___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_722___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_723 (0x005FCB4C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_723___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_723___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_723__RX_DCOC_RANGE_723___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_723__RX_DCOC_RES_I_723___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_723__RX_DCOC_RES_Q_723___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_723__RX_DCOC_RANGE_723___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_723__RX_DCOC_RANGE_723___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_723__RX_DCOC_RES_I_723___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_723__RX_DCOC_RES_I_723___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_723__RX_DCOC_RES_Q_723___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_723__RX_DCOC_RES_Q_723___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_723___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_723___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_724 (0x005FCB50) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_724___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_724___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_724__RX_DCOC_RANGE_724___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_724__RX_DCOC_RES_I_724___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_724__RX_DCOC_RES_Q_724___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_724__RX_DCOC_RANGE_724___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_724__RX_DCOC_RANGE_724___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_724__RX_DCOC_RES_I_724___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_724__RX_DCOC_RES_I_724___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_724__RX_DCOC_RES_Q_724___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_724__RX_DCOC_RES_Q_724___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_724___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_724___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_725 (0x005FCB54) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_725___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_725___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_725__RX_DCOC_RANGE_725___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_725__RX_DCOC_RES_I_725___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_725__RX_DCOC_RES_Q_725___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_725__RX_DCOC_RANGE_725___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_725__RX_DCOC_RANGE_725___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_725__RX_DCOC_RES_I_725___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_725__RX_DCOC_RES_I_725___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_725__RX_DCOC_RES_Q_725___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_725__RX_DCOC_RES_Q_725___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_725___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_725___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_726 (0x005FCB58) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_726___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_726___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_726__RX_DCOC_RANGE_726___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_726__RX_DCOC_RES_I_726___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_726__RX_DCOC_RES_Q_726___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_726__RX_DCOC_RANGE_726___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_726__RX_DCOC_RANGE_726___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_726__RX_DCOC_RES_I_726___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_726__RX_DCOC_RES_I_726___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_726__RX_DCOC_RES_Q_726___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_726__RX_DCOC_RES_Q_726___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_726___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_726___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_727 (0x005FCB5C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_727___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_727___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_727__RX_DCOC_RANGE_727___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_727__RX_DCOC_RES_I_727___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_727__RX_DCOC_RES_Q_727___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_727__RX_DCOC_RANGE_727___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_727__RX_DCOC_RANGE_727___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_727__RX_DCOC_RES_I_727___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_727__RX_DCOC_RES_I_727___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_727__RX_DCOC_RES_Q_727___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_727__RX_DCOC_RES_Q_727___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_727___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_727___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_728 (0x005FCB60) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_728___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_728___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_728__RX_DCOC_RANGE_728___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_728__RX_DCOC_RES_I_728___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_728__RX_DCOC_RES_Q_728___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_728__RX_DCOC_RANGE_728___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_728__RX_DCOC_RANGE_728___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_728__RX_DCOC_RES_I_728___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_728__RX_DCOC_RES_I_728___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_728__RX_DCOC_RES_Q_728___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_728__RX_DCOC_RES_Q_728___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_728___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_728___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_729 (0x005FCB64) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_729___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_729___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_729__RX_DCOC_RANGE_729___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_729__RX_DCOC_RES_I_729___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_729__RX_DCOC_RES_Q_729___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_729__RX_DCOC_RANGE_729___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_729__RX_DCOC_RANGE_729___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_729__RX_DCOC_RES_I_729___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_729__RX_DCOC_RES_I_729___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_729__RX_DCOC_RES_Q_729___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_729__RX_DCOC_RES_Q_729___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_729___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_729___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_730 (0x005FCB68) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_730___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_730___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_730__RX_DCOC_RANGE_730___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_730__RX_DCOC_RES_I_730___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_730__RX_DCOC_RES_Q_730___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_730__RX_DCOC_RANGE_730___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_730__RX_DCOC_RANGE_730___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_730__RX_DCOC_RES_I_730___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_730__RX_DCOC_RES_I_730___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_730__RX_DCOC_RES_Q_730___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_730__RX_DCOC_RES_Q_730___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_730___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_730___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_731 (0x005FCB6C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_731___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_731___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_731__RX_DCOC_RANGE_731___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_731__RX_DCOC_RES_I_731___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_731__RX_DCOC_RES_Q_731___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_731__RX_DCOC_RANGE_731___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_731__RX_DCOC_RANGE_731___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_731__RX_DCOC_RES_I_731___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_731__RX_DCOC_RES_I_731___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_731__RX_DCOC_RES_Q_731___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_731__RX_DCOC_RES_Q_731___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_731___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_731___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_732 (0x005FCB70) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_732___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_732___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_732__RX_DCOC_RANGE_732___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_732__RX_DCOC_RES_I_732___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_732__RX_DCOC_RES_Q_732___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_732__RX_DCOC_RANGE_732___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_732__RX_DCOC_RANGE_732___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_732__RX_DCOC_RES_I_732___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_732__RX_DCOC_RES_I_732___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_732__RX_DCOC_RES_Q_732___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_732__RX_DCOC_RES_Q_732___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_732___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_732___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_733 (0x005FCB74) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_733___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_733___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_733__RX_DCOC_RANGE_733___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_733__RX_DCOC_RES_I_733___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_733__RX_DCOC_RES_Q_733___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_733__RX_DCOC_RANGE_733___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_733__RX_DCOC_RANGE_733___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_733__RX_DCOC_RES_I_733___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_733__RX_DCOC_RES_I_733___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_733__RX_DCOC_RES_Q_733___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_733__RX_DCOC_RES_Q_733___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_733___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_733___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_734 (0x005FCB78) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_734___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_734___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_734__RX_DCOC_RANGE_734___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_734__RX_DCOC_RES_I_734___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_734__RX_DCOC_RES_Q_734___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_734__RX_DCOC_RANGE_734___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_734__RX_DCOC_RANGE_734___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_734__RX_DCOC_RES_I_734___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_734__RX_DCOC_RES_I_734___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_734__RX_DCOC_RES_Q_734___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_734__RX_DCOC_RES_Q_734___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_734___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_734___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_735 (0x005FCB7C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_735___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_735___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_735__RX_DCOC_RANGE_735___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_735__RX_DCOC_RES_I_735___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_735__RX_DCOC_RES_Q_735___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_735__RX_DCOC_RANGE_735___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_735__RX_DCOC_RANGE_735___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_735__RX_DCOC_RES_I_735___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_735__RX_DCOC_RES_I_735___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_735__RX_DCOC_RES_Q_735___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_735__RX_DCOC_RES_Q_735___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_735___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_735___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_736 (0x005FCB80) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_736___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_736___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_736__RX_DCOC_RANGE_736___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_736__RX_DCOC_RES_I_736___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_736__RX_DCOC_RES_Q_736___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_736__RX_DCOC_RANGE_736___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_736__RX_DCOC_RANGE_736___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_736__RX_DCOC_RES_I_736___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_736__RX_DCOC_RES_I_736___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_736__RX_DCOC_RES_Q_736___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_736__RX_DCOC_RES_Q_736___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_736___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_736___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_737 (0x005FCB84) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_737___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_737___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_737__RX_DCOC_RANGE_737___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_737__RX_DCOC_RES_I_737___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_737__RX_DCOC_RES_Q_737___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_737__RX_DCOC_RANGE_737___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_737__RX_DCOC_RANGE_737___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_737__RX_DCOC_RES_I_737___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_737__RX_DCOC_RES_I_737___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_737__RX_DCOC_RES_Q_737___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_737__RX_DCOC_RES_Q_737___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_737___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_737___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_738 (0x005FCB88) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_738___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_738___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_738__RX_DCOC_RANGE_738___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_738__RX_DCOC_RES_I_738___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_738__RX_DCOC_RES_Q_738___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_738__RX_DCOC_RANGE_738___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_738__RX_DCOC_RANGE_738___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_738__RX_DCOC_RES_I_738___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_738__RX_DCOC_RES_I_738___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_738__RX_DCOC_RES_Q_738___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_738__RX_DCOC_RES_Q_738___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_738___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_738___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_739 (0x005FCB8C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_739___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_739___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_739__RX_DCOC_RANGE_739___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_739__RX_DCOC_RES_I_739___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_739__RX_DCOC_RES_Q_739___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_739__RX_DCOC_RANGE_739___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_739__RX_DCOC_RANGE_739___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_739__RX_DCOC_RES_I_739___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_739__RX_DCOC_RES_I_739___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_739__RX_DCOC_RES_Q_739___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_739__RX_DCOC_RES_Q_739___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_739___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_739___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_740 (0x005FCB90) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_740___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_740___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_740__RX_DCOC_RANGE_740___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_740__RX_DCOC_RES_I_740___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_740__RX_DCOC_RES_Q_740___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_740__RX_DCOC_RANGE_740___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_740__RX_DCOC_RANGE_740___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_740__RX_DCOC_RES_I_740___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_740__RX_DCOC_RES_I_740___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_740__RX_DCOC_RES_Q_740___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_740__RX_DCOC_RES_Q_740___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_740___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_740___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_741 (0x005FCB94) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_741___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_741___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_741__RX_DCOC_RANGE_741___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_741__RX_DCOC_RES_I_741___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_741__RX_DCOC_RES_Q_741___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_741__RX_DCOC_RANGE_741___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_741__RX_DCOC_RANGE_741___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_741__RX_DCOC_RES_I_741___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_741__RX_DCOC_RES_I_741___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_741__RX_DCOC_RES_Q_741___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_741__RX_DCOC_RES_Q_741___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_741___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_741___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_742 (0x005FCB98) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_742___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_742___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_742__RX_DCOC_RANGE_742___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_742__RX_DCOC_RES_I_742___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_742__RX_DCOC_RES_Q_742___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_742__RX_DCOC_RANGE_742___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_742__RX_DCOC_RANGE_742___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_742__RX_DCOC_RES_I_742___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_742__RX_DCOC_RES_I_742___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_742__RX_DCOC_RES_Q_742___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_742__RX_DCOC_RES_Q_742___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_742___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_742___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_743 (0x005FCB9C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_743___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_743___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_743__RX_DCOC_RANGE_743___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_743__RX_DCOC_RES_I_743___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_743__RX_DCOC_RES_Q_743___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_743__RX_DCOC_RANGE_743___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_743__RX_DCOC_RANGE_743___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_743__RX_DCOC_RES_I_743___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_743__RX_DCOC_RES_I_743___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_743__RX_DCOC_RES_Q_743___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_743__RX_DCOC_RES_Q_743___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_743___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_743___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_744 (0x005FCBA0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_744___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_744___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_744__RX_DCOC_RANGE_744___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_744__RX_DCOC_RES_I_744___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_744__RX_DCOC_RES_Q_744___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_744__RX_DCOC_RANGE_744___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_744__RX_DCOC_RANGE_744___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_744__RX_DCOC_RES_I_744___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_744__RX_DCOC_RES_I_744___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_744__RX_DCOC_RES_Q_744___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_744__RX_DCOC_RES_Q_744___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_744___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_744___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_745 (0x005FCBA4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_745___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_745___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_745__RX_DCOC_RANGE_745___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_745__RX_DCOC_RES_I_745___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_745__RX_DCOC_RES_Q_745___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_745__RX_DCOC_RANGE_745___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_745__RX_DCOC_RANGE_745___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_745__RX_DCOC_RES_I_745___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_745__RX_DCOC_RES_I_745___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_745__RX_DCOC_RES_Q_745___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_745__RX_DCOC_RES_Q_745___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_745___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_745___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_746 (0x005FCBA8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_746___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_746___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_746__RX_DCOC_RANGE_746___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_746__RX_DCOC_RES_I_746___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_746__RX_DCOC_RES_Q_746___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_746__RX_DCOC_RANGE_746___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_746__RX_DCOC_RANGE_746___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_746__RX_DCOC_RES_I_746___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_746__RX_DCOC_RES_I_746___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_746__RX_DCOC_RES_Q_746___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_746__RX_DCOC_RES_Q_746___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_746___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_746___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_747 (0x005FCBAC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_747___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_747___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_747__RX_DCOC_RANGE_747___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_747__RX_DCOC_RES_I_747___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_747__RX_DCOC_RES_Q_747___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_747__RX_DCOC_RANGE_747___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_747__RX_DCOC_RANGE_747___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_747__RX_DCOC_RES_I_747___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_747__RX_DCOC_RES_I_747___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_747__RX_DCOC_RES_Q_747___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_747__RX_DCOC_RES_Q_747___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_747___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_747___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_748 (0x005FCBB0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_748___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_748___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_748__RX_DCOC_RANGE_748___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_748__RX_DCOC_RES_I_748___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_748__RX_DCOC_RES_Q_748___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_748__RX_DCOC_RANGE_748___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_748__RX_DCOC_RANGE_748___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_748__RX_DCOC_RES_I_748___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_748__RX_DCOC_RES_I_748___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_748__RX_DCOC_RES_Q_748___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_748__RX_DCOC_RES_Q_748___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_748___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_748___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_749 (0x005FCBB4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_749___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_749___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_749__RX_DCOC_RANGE_749___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_749__RX_DCOC_RES_I_749___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_749__RX_DCOC_RES_Q_749___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_749__RX_DCOC_RANGE_749___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_749__RX_DCOC_RANGE_749___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_749__RX_DCOC_RES_I_749___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_749__RX_DCOC_RES_I_749___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_749__RX_DCOC_RES_Q_749___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_749__RX_DCOC_RES_Q_749___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_749___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_749___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_750 (0x005FCBB8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_750___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_750___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_750__RX_DCOC_RANGE_750___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_750__RX_DCOC_RES_I_750___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_750__RX_DCOC_RES_Q_750___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_750__RX_DCOC_RANGE_750___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_750__RX_DCOC_RANGE_750___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_750__RX_DCOC_RES_I_750___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_750__RX_DCOC_RES_I_750___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_750__RX_DCOC_RES_Q_750___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_750__RX_DCOC_RES_Q_750___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_750___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_750___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_751 (0x005FCBBC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_751___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_751___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_751__RX_DCOC_RANGE_751___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_751__RX_DCOC_RES_I_751___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_751__RX_DCOC_RES_Q_751___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_751__RX_DCOC_RANGE_751___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_751__RX_DCOC_RANGE_751___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_751__RX_DCOC_RES_I_751___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_751__RX_DCOC_RES_I_751___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_751__RX_DCOC_RES_Q_751___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_751__RX_DCOC_RES_Q_751___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_751___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_751___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_752 (0x005FCBC0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_752___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_752___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_752__RX_DCOC_RANGE_752___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_752__RX_DCOC_RES_I_752___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_752__RX_DCOC_RES_Q_752___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_752__RX_DCOC_RANGE_752___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_752__RX_DCOC_RANGE_752___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_752__RX_DCOC_RES_I_752___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_752__RX_DCOC_RES_I_752___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_752__RX_DCOC_RES_Q_752___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_752__RX_DCOC_RES_Q_752___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_752___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_752___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_753 (0x005FCBC4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_753___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_753___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_753__RX_DCOC_RANGE_753___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_753__RX_DCOC_RES_I_753___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_753__RX_DCOC_RES_Q_753___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_753__RX_DCOC_RANGE_753___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_753__RX_DCOC_RANGE_753___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_753__RX_DCOC_RES_I_753___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_753__RX_DCOC_RES_I_753___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_753__RX_DCOC_RES_Q_753___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_753__RX_DCOC_RES_Q_753___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_753___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_753___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_754 (0x005FCBC8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_754___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_754___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_754__RX_DCOC_RANGE_754___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_754__RX_DCOC_RES_I_754___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_754__RX_DCOC_RES_Q_754___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_754__RX_DCOC_RANGE_754___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_754__RX_DCOC_RANGE_754___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_754__RX_DCOC_RES_I_754___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_754__RX_DCOC_RES_I_754___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_754__RX_DCOC_RES_Q_754___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_754__RX_DCOC_RES_Q_754___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_754___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_754___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_755 (0x005FCBCC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_755___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_755___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_755__RX_DCOC_RANGE_755___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_755__RX_DCOC_RES_I_755___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_755__RX_DCOC_RES_Q_755___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_755__RX_DCOC_RANGE_755___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_755__RX_DCOC_RANGE_755___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_755__RX_DCOC_RES_I_755___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_755__RX_DCOC_RES_I_755___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_755__RX_DCOC_RES_Q_755___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_755__RX_DCOC_RES_Q_755___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_755___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_755___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_756 (0x005FCBD0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_756___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_756___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_756__RX_DCOC_RANGE_756___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_756__RX_DCOC_RES_I_756___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_756__RX_DCOC_RES_Q_756___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_756__RX_DCOC_RANGE_756___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_756__RX_DCOC_RANGE_756___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_756__RX_DCOC_RES_I_756___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_756__RX_DCOC_RES_I_756___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_756__RX_DCOC_RES_Q_756___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_756__RX_DCOC_RES_Q_756___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_756___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_756___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_757 (0x005FCBD4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_757___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_757___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_757__RX_DCOC_RANGE_757___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_757__RX_DCOC_RES_I_757___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_757__RX_DCOC_RES_Q_757___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_757__RX_DCOC_RANGE_757___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_757__RX_DCOC_RANGE_757___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_757__RX_DCOC_RES_I_757___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_757__RX_DCOC_RES_I_757___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_757__RX_DCOC_RES_Q_757___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_757__RX_DCOC_RES_Q_757___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_757___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_757___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_758 (0x005FCBD8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_758___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_758___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_758__RX_DCOC_RANGE_758___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_758__RX_DCOC_RES_I_758___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_758__RX_DCOC_RES_Q_758___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_758__RX_DCOC_RANGE_758___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_758__RX_DCOC_RANGE_758___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_758__RX_DCOC_RES_I_758___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_758__RX_DCOC_RES_I_758___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_758__RX_DCOC_RES_Q_758___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_758__RX_DCOC_RES_Q_758___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_758___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_758___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_759 (0x005FCBDC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_759___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_759___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_759__RX_DCOC_RANGE_759___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_759__RX_DCOC_RES_I_759___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_759__RX_DCOC_RES_Q_759___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_759__RX_DCOC_RANGE_759___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_759__RX_DCOC_RANGE_759___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_759__RX_DCOC_RES_I_759___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_759__RX_DCOC_RES_I_759___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_759__RX_DCOC_RES_Q_759___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_759__RX_DCOC_RES_Q_759___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_759___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_759___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_760 (0x005FCBE0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_760___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_760___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_760__RX_DCOC_RANGE_760___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_760__RX_DCOC_RES_I_760___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_760__RX_DCOC_RES_Q_760___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_760__RX_DCOC_RANGE_760___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_760__RX_DCOC_RANGE_760___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_760__RX_DCOC_RES_I_760___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_760__RX_DCOC_RES_I_760___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_760__RX_DCOC_RES_Q_760___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_760__RX_DCOC_RES_Q_760___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_760___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_760___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_761 (0x005FCBE4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_761___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_761___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_761__RX_DCOC_RANGE_761___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_761__RX_DCOC_RES_I_761___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_761__RX_DCOC_RES_Q_761___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_761__RX_DCOC_RANGE_761___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_761__RX_DCOC_RANGE_761___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_761__RX_DCOC_RES_I_761___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_761__RX_DCOC_RES_I_761___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_761__RX_DCOC_RES_Q_761___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_761__RX_DCOC_RES_Q_761___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_761___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_761___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_762 (0x005FCBE8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_762___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_762___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_762__RX_DCOC_RANGE_762___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_762__RX_DCOC_RES_I_762___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_762__RX_DCOC_RES_Q_762___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_762__RX_DCOC_RANGE_762___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_762__RX_DCOC_RANGE_762___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_762__RX_DCOC_RES_I_762___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_762__RX_DCOC_RES_I_762___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_762__RX_DCOC_RES_Q_762___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_762__RX_DCOC_RES_Q_762___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_762___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_762___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_763 (0x005FCBEC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_763___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_763___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_763__RX_DCOC_RANGE_763___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_763__RX_DCOC_RES_I_763___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_763__RX_DCOC_RES_Q_763___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_763__RX_DCOC_RANGE_763___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_763__RX_DCOC_RANGE_763___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_763__RX_DCOC_RES_I_763___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_763__RX_DCOC_RES_I_763___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_763__RX_DCOC_RES_Q_763___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_763__RX_DCOC_RES_Q_763___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_763___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_763___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_764 (0x005FCBF0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_764___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_764___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_764__RX_DCOC_RANGE_764___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_764__RX_DCOC_RES_I_764___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_764__RX_DCOC_RES_Q_764___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_764__RX_DCOC_RANGE_764___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_764__RX_DCOC_RANGE_764___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_764__RX_DCOC_RES_I_764___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_764__RX_DCOC_RES_I_764___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_764__RX_DCOC_RES_Q_764___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_764__RX_DCOC_RES_Q_764___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_764___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_764___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_765 (0x005FCBF4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_765___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_765___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_765__RX_DCOC_RANGE_765___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_765__RX_DCOC_RES_I_765___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_765__RX_DCOC_RES_Q_765___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_765__RX_DCOC_RANGE_765___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_765__RX_DCOC_RANGE_765___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_765__RX_DCOC_RES_I_765___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_765__RX_DCOC_RES_I_765___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_765__RX_DCOC_RES_Q_765___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_765__RX_DCOC_RES_Q_765___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_765___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_765___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_766 (0x005FCBF8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_766___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_766___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_766__RX_DCOC_RANGE_766___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_766__RX_DCOC_RES_I_766___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_766__RX_DCOC_RES_Q_766___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_766__RX_DCOC_RANGE_766___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_766__RX_DCOC_RANGE_766___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_766__RX_DCOC_RES_I_766___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_766__RX_DCOC_RES_I_766___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_766__RX_DCOC_RES_Q_766___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_766__RX_DCOC_RES_Q_766___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_766___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_766___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_767 (0x005FCBFC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_767___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_767___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_767__RX_DCOC_RANGE_767___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_767__RX_DCOC_RES_I_767___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_767__RX_DCOC_RES_Q_767___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_767__RX_DCOC_RANGE_767___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_767__RX_DCOC_RANGE_767___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_767__RX_DCOC_RES_I_767___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_767__RX_DCOC_RES_I_767___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_767__RX_DCOC_RES_Q_767___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_767__RX_DCOC_RES_Q_767___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_767___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_767___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_768 (0x005FCC00) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_768___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_768___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_768__RX_DCOC_RANGE_768___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_768__RX_DCOC_RES_I_768___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_768__RX_DCOC_RES_Q_768___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_768__RX_DCOC_RANGE_768___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_768__RX_DCOC_RANGE_768___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_768__RX_DCOC_RES_I_768___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_768__RX_DCOC_RES_I_768___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_768__RX_DCOC_RES_Q_768___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_768__RX_DCOC_RES_Q_768___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_768___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_768___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_769 (0x005FCC04) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_769___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_769___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_769__RX_DCOC_RANGE_769___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_769__RX_DCOC_RES_I_769___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_769__RX_DCOC_RES_Q_769___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_769__RX_DCOC_RANGE_769___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_769__RX_DCOC_RANGE_769___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_769__RX_DCOC_RES_I_769___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_769__RX_DCOC_RES_I_769___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_769__RX_DCOC_RES_Q_769___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_769__RX_DCOC_RES_Q_769___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_769___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_769___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_770 (0x005FCC08) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_770___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_770___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_770__RX_DCOC_RANGE_770___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_770__RX_DCOC_RES_I_770___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_770__RX_DCOC_RES_Q_770___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_770__RX_DCOC_RANGE_770___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_770__RX_DCOC_RANGE_770___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_770__RX_DCOC_RES_I_770___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_770__RX_DCOC_RES_I_770___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_770__RX_DCOC_RES_Q_770___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_770__RX_DCOC_RES_Q_770___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_770___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_770___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_771 (0x005FCC0C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_771___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_771___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_771__RX_DCOC_RANGE_771___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_771__RX_DCOC_RES_I_771___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_771__RX_DCOC_RES_Q_771___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_771__RX_DCOC_RANGE_771___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_771__RX_DCOC_RANGE_771___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_771__RX_DCOC_RES_I_771___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_771__RX_DCOC_RES_I_771___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_771__RX_DCOC_RES_Q_771___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_771__RX_DCOC_RES_Q_771___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_771___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_771___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_772 (0x005FCC10) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_772___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_772___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_772__RX_DCOC_RANGE_772___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_772__RX_DCOC_RES_I_772___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_772__RX_DCOC_RES_Q_772___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_772__RX_DCOC_RANGE_772___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_772__RX_DCOC_RANGE_772___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_772__RX_DCOC_RES_I_772___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_772__RX_DCOC_RES_I_772___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_772__RX_DCOC_RES_Q_772___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_772__RX_DCOC_RES_Q_772___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_772___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_772___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_773 (0x005FCC14) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_773___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_773___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_773__RX_DCOC_RANGE_773___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_773__RX_DCOC_RES_I_773___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_773__RX_DCOC_RES_Q_773___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_773__RX_DCOC_RANGE_773___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_773__RX_DCOC_RANGE_773___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_773__RX_DCOC_RES_I_773___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_773__RX_DCOC_RES_I_773___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_773__RX_DCOC_RES_Q_773___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_773__RX_DCOC_RES_Q_773___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_773___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_773___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_774 (0x005FCC18) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_774___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_774___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_774__RX_DCOC_RANGE_774___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_774__RX_DCOC_RES_I_774___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_774__RX_DCOC_RES_Q_774___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_774__RX_DCOC_RANGE_774___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_774__RX_DCOC_RANGE_774___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_774__RX_DCOC_RES_I_774___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_774__RX_DCOC_RES_I_774___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_774__RX_DCOC_RES_Q_774___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_774__RX_DCOC_RES_Q_774___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_774___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_774___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_775 (0x005FCC1C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_775___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_775___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_775__RX_DCOC_RANGE_775___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_775__RX_DCOC_RES_I_775___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_775__RX_DCOC_RES_Q_775___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_775__RX_DCOC_RANGE_775___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_775__RX_DCOC_RANGE_775___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_775__RX_DCOC_RES_I_775___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_775__RX_DCOC_RES_I_775___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_775__RX_DCOC_RES_Q_775___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_775__RX_DCOC_RES_Q_775___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_775___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_775___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_776 (0x005FCC20) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_776___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_776___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_776__RX_DCOC_RANGE_776___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_776__RX_DCOC_RES_I_776___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_776__RX_DCOC_RES_Q_776___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_776__RX_DCOC_RANGE_776___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_776__RX_DCOC_RANGE_776___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_776__RX_DCOC_RES_I_776___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_776__RX_DCOC_RES_I_776___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_776__RX_DCOC_RES_Q_776___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_776__RX_DCOC_RES_Q_776___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_776___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_776___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_777 (0x005FCC24) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_777___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_777___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_777__RX_DCOC_RANGE_777___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_777__RX_DCOC_RES_I_777___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_777__RX_DCOC_RES_Q_777___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_777__RX_DCOC_RANGE_777___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_777__RX_DCOC_RANGE_777___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_777__RX_DCOC_RES_I_777___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_777__RX_DCOC_RES_I_777___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_777__RX_DCOC_RES_Q_777___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_777__RX_DCOC_RES_Q_777___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_777___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_777___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_778 (0x005FCC28) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_778___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_778___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_778__RX_DCOC_RANGE_778___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_778__RX_DCOC_RES_I_778___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_778__RX_DCOC_RES_Q_778___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_778__RX_DCOC_RANGE_778___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_778__RX_DCOC_RANGE_778___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_778__RX_DCOC_RES_I_778___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_778__RX_DCOC_RES_I_778___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_778__RX_DCOC_RES_Q_778___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_778__RX_DCOC_RES_Q_778___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_778___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_778___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_779 (0x005FCC2C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_779___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_779___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_779__RX_DCOC_RANGE_779___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_779__RX_DCOC_RES_I_779___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_779__RX_DCOC_RES_Q_779___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_779__RX_DCOC_RANGE_779___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_779__RX_DCOC_RANGE_779___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_779__RX_DCOC_RES_I_779___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_779__RX_DCOC_RES_I_779___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_779__RX_DCOC_RES_Q_779___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_779__RX_DCOC_RES_Q_779___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_779___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_779___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_780 (0x005FCC30) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_780___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_780___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_780__RX_DCOC_RANGE_780___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_780__RX_DCOC_RES_I_780___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_780__RX_DCOC_RES_Q_780___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_780__RX_DCOC_RANGE_780___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_780__RX_DCOC_RANGE_780___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_780__RX_DCOC_RES_I_780___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_780__RX_DCOC_RES_I_780___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_780__RX_DCOC_RES_Q_780___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_780__RX_DCOC_RES_Q_780___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_780___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_780___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_781 (0x005FCC34) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_781___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_781___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_781__RX_DCOC_RANGE_781___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_781__RX_DCOC_RES_I_781___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_781__RX_DCOC_RES_Q_781___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_781__RX_DCOC_RANGE_781___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_781__RX_DCOC_RANGE_781___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_781__RX_DCOC_RES_I_781___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_781__RX_DCOC_RES_I_781___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_781__RX_DCOC_RES_Q_781___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_781__RX_DCOC_RES_Q_781___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_781___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_781___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_782 (0x005FCC38) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_782___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_782___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_782__RX_DCOC_RANGE_782___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_782__RX_DCOC_RES_I_782___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_782__RX_DCOC_RES_Q_782___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_782__RX_DCOC_RANGE_782___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_782__RX_DCOC_RANGE_782___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_782__RX_DCOC_RES_I_782___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_782__RX_DCOC_RES_I_782___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_782__RX_DCOC_RES_Q_782___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_782__RX_DCOC_RES_Q_782___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_782___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_782___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_783 (0x005FCC3C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_783___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_783___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_783__RX_DCOC_RANGE_783___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_783__RX_DCOC_RES_I_783___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_783__RX_DCOC_RES_Q_783___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_783__RX_DCOC_RANGE_783___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_783__RX_DCOC_RANGE_783___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_783__RX_DCOC_RES_I_783___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_783__RX_DCOC_RES_I_783___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_783__RX_DCOC_RES_Q_783___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_783__RX_DCOC_RES_Q_783___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_783___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_783___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_784 (0x005FCC40) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_784___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_784___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_784__RX_DCOC_RANGE_784___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_784__RX_DCOC_RES_I_784___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_784__RX_DCOC_RES_Q_784___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_784__RX_DCOC_RANGE_784___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_784__RX_DCOC_RANGE_784___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_784__RX_DCOC_RES_I_784___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_784__RX_DCOC_RES_I_784___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_784__RX_DCOC_RES_Q_784___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_784__RX_DCOC_RES_Q_784___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_784___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_784___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_785 (0x005FCC44) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_785___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_785___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_785__RX_DCOC_RANGE_785___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_785__RX_DCOC_RES_I_785___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_785__RX_DCOC_RES_Q_785___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_785__RX_DCOC_RANGE_785___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_785__RX_DCOC_RANGE_785___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_785__RX_DCOC_RES_I_785___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_785__RX_DCOC_RES_I_785___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_785__RX_DCOC_RES_Q_785___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_785__RX_DCOC_RES_Q_785___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_785___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_785___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_786 (0x005FCC48) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_786___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_786___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_786__RX_DCOC_RANGE_786___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_786__RX_DCOC_RES_I_786___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_786__RX_DCOC_RES_Q_786___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_786__RX_DCOC_RANGE_786___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_786__RX_DCOC_RANGE_786___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_786__RX_DCOC_RES_I_786___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_786__RX_DCOC_RES_I_786___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_786__RX_DCOC_RES_Q_786___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_786__RX_DCOC_RES_Q_786___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_786___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_786___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_787 (0x005FCC4C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_787___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_787___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_787__RX_DCOC_RANGE_787___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_787__RX_DCOC_RES_I_787___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_787__RX_DCOC_RES_Q_787___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_787__RX_DCOC_RANGE_787___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_787__RX_DCOC_RANGE_787___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_787__RX_DCOC_RES_I_787___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_787__RX_DCOC_RES_I_787___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_787__RX_DCOC_RES_Q_787___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_787__RX_DCOC_RES_Q_787___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_787___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_787___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_788 (0x005FCC50) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_788___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_788___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_788__RX_DCOC_RANGE_788___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_788__RX_DCOC_RES_I_788___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_788__RX_DCOC_RES_Q_788___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_788__RX_DCOC_RANGE_788___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_788__RX_DCOC_RANGE_788___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_788__RX_DCOC_RES_I_788___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_788__RX_DCOC_RES_I_788___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_788__RX_DCOC_RES_Q_788___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_788__RX_DCOC_RES_Q_788___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_788___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_788___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_789 (0x005FCC54) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_789___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_789___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_789__RX_DCOC_RANGE_789___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_789__RX_DCOC_RES_I_789___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_789__RX_DCOC_RES_Q_789___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_789__RX_DCOC_RANGE_789___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_789__RX_DCOC_RANGE_789___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_789__RX_DCOC_RES_I_789___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_789__RX_DCOC_RES_I_789___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_789__RX_DCOC_RES_Q_789___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_789__RX_DCOC_RES_Q_789___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_789___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_789___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_790 (0x005FCC58) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_790___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_790___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_790__RX_DCOC_RANGE_790___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_790__RX_DCOC_RES_I_790___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_790__RX_DCOC_RES_Q_790___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_790__RX_DCOC_RANGE_790___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_790__RX_DCOC_RANGE_790___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_790__RX_DCOC_RES_I_790___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_790__RX_DCOC_RES_I_790___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_790__RX_DCOC_RES_Q_790___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_790__RX_DCOC_RES_Q_790___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_790___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_790___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_791 (0x005FCC5C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_791___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_791___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_791__RX_DCOC_RANGE_791___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_791__RX_DCOC_RES_I_791___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_791__RX_DCOC_RES_Q_791___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_791__RX_DCOC_RANGE_791___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_791__RX_DCOC_RANGE_791___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_791__RX_DCOC_RES_I_791___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_791__RX_DCOC_RES_I_791___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_791__RX_DCOC_RES_Q_791___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_791__RX_DCOC_RES_Q_791___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_791___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_791___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_792 (0x005FCC60) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_792___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_792___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_792__RX_DCOC_RANGE_792___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_792__RX_DCOC_RES_I_792___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_792__RX_DCOC_RES_Q_792___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_792__RX_DCOC_RANGE_792___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_792__RX_DCOC_RANGE_792___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_792__RX_DCOC_RES_I_792___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_792__RX_DCOC_RES_I_792___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_792__RX_DCOC_RES_Q_792___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_792__RX_DCOC_RES_Q_792___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_792___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_792___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_793 (0x005FCC64) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_793___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_793___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_793__RX_DCOC_RANGE_793___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_793__RX_DCOC_RES_I_793___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_793__RX_DCOC_RES_Q_793___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_793__RX_DCOC_RANGE_793___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_793__RX_DCOC_RANGE_793___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_793__RX_DCOC_RES_I_793___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_793__RX_DCOC_RES_I_793___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_793__RX_DCOC_RES_Q_793___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_793__RX_DCOC_RES_Q_793___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_793___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_793___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_794 (0x005FCC68) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_794___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_794___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_794__RX_DCOC_RANGE_794___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_794__RX_DCOC_RES_I_794___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_794__RX_DCOC_RES_Q_794___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_794__RX_DCOC_RANGE_794___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_794__RX_DCOC_RANGE_794___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_794__RX_DCOC_RES_I_794___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_794__RX_DCOC_RES_I_794___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_794__RX_DCOC_RES_Q_794___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_794__RX_DCOC_RES_Q_794___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_794___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_794___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_795 (0x005FCC6C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_795___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_795___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_795__RX_DCOC_RANGE_795___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_795__RX_DCOC_RES_I_795___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_795__RX_DCOC_RES_Q_795___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_795__RX_DCOC_RANGE_795___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_795__RX_DCOC_RANGE_795___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_795__RX_DCOC_RES_I_795___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_795__RX_DCOC_RES_I_795___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_795__RX_DCOC_RES_Q_795___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_795__RX_DCOC_RES_Q_795___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_795___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_795___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_796 (0x005FCC70) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_796___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_796___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_796__RX_DCOC_RANGE_796___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_796__RX_DCOC_RES_I_796___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_796__RX_DCOC_RES_Q_796___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_796__RX_DCOC_RANGE_796___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_796__RX_DCOC_RANGE_796___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_796__RX_DCOC_RES_I_796___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_796__RX_DCOC_RES_I_796___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_796__RX_DCOC_RES_Q_796___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_796__RX_DCOC_RES_Q_796___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_796___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_796___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_797 (0x005FCC74) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_797___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_797___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_797__RX_DCOC_RANGE_797___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_797__RX_DCOC_RES_I_797___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_797__RX_DCOC_RES_Q_797___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_797__RX_DCOC_RANGE_797___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_797__RX_DCOC_RANGE_797___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_797__RX_DCOC_RES_I_797___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_797__RX_DCOC_RES_I_797___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_797__RX_DCOC_RES_Q_797___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_797__RX_DCOC_RES_Q_797___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_797___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_797___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_798 (0x005FCC78) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_798___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_798___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_798__RX_DCOC_RANGE_798___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_798__RX_DCOC_RES_I_798___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_798__RX_DCOC_RES_Q_798___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_798__RX_DCOC_RANGE_798___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_798__RX_DCOC_RANGE_798___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_798__RX_DCOC_RES_I_798___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_798__RX_DCOC_RES_I_798___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_798__RX_DCOC_RES_Q_798___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_798__RX_DCOC_RES_Q_798___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_798___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_798___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_799 (0x005FCC7C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_799___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_799___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_799__RX_DCOC_RANGE_799___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_799__RX_DCOC_RES_I_799___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_799__RX_DCOC_RES_Q_799___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_799__RX_DCOC_RANGE_799___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_799__RX_DCOC_RANGE_799___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_799__RX_DCOC_RES_I_799___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_799__RX_DCOC_RES_I_799___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_799__RX_DCOC_RES_Q_799___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_799__RX_DCOC_RES_Q_799___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_799___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_799___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_800 (0x005FCC80) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_800___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_800___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_800__RX_DCOC_RANGE_800___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_800__RX_DCOC_RES_I_800___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_800__RX_DCOC_RES_Q_800___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_800__RX_DCOC_RANGE_800___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_800__RX_DCOC_RANGE_800___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_800__RX_DCOC_RES_I_800___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_800__RX_DCOC_RES_I_800___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_800__RX_DCOC_RES_Q_800___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_800__RX_DCOC_RES_Q_800___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_800___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_800___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_801 (0x005FCC84) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_801___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_801___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_801__RX_DCOC_RANGE_801___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_801__RX_DCOC_RES_I_801___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_801__RX_DCOC_RES_Q_801___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_801__RX_DCOC_RANGE_801___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_801__RX_DCOC_RANGE_801___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_801__RX_DCOC_RES_I_801___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_801__RX_DCOC_RES_I_801___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_801__RX_DCOC_RES_Q_801___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_801__RX_DCOC_RES_Q_801___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_801___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_801___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_802 (0x005FCC88) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_802___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_802___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_802__RX_DCOC_RANGE_802___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_802__RX_DCOC_RES_I_802___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_802__RX_DCOC_RES_Q_802___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_802__RX_DCOC_RANGE_802___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_802__RX_DCOC_RANGE_802___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_802__RX_DCOC_RES_I_802___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_802__RX_DCOC_RES_I_802___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_802__RX_DCOC_RES_Q_802___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_802__RX_DCOC_RES_Q_802___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_802___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_802___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_803 (0x005FCC8C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_803___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_803___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_803__RX_DCOC_RANGE_803___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_803__RX_DCOC_RES_I_803___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_803__RX_DCOC_RES_Q_803___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_803__RX_DCOC_RANGE_803___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_803__RX_DCOC_RANGE_803___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_803__RX_DCOC_RES_I_803___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_803__RX_DCOC_RES_I_803___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_803__RX_DCOC_RES_Q_803___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_803__RX_DCOC_RES_Q_803___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_803___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_803___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_804 (0x005FCC90) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_804___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_804___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_804__RX_DCOC_RANGE_804___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_804__RX_DCOC_RES_I_804___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_804__RX_DCOC_RES_Q_804___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_804__RX_DCOC_RANGE_804___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_804__RX_DCOC_RANGE_804___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_804__RX_DCOC_RES_I_804___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_804__RX_DCOC_RES_I_804___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_804__RX_DCOC_RES_Q_804___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_804__RX_DCOC_RES_Q_804___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_804___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_804___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_805 (0x005FCC94) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_805___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_805___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_805__RX_DCOC_RANGE_805___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_805__RX_DCOC_RES_I_805___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_805__RX_DCOC_RES_Q_805___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_805__RX_DCOC_RANGE_805___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_805__RX_DCOC_RANGE_805___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_805__RX_DCOC_RES_I_805___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_805__RX_DCOC_RES_I_805___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_805__RX_DCOC_RES_Q_805___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_805__RX_DCOC_RES_Q_805___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_805___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_805___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_806 (0x005FCC98) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_806___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_806___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_806__RX_DCOC_RANGE_806___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_806__RX_DCOC_RES_I_806___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_806__RX_DCOC_RES_Q_806___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_806__RX_DCOC_RANGE_806___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_806__RX_DCOC_RANGE_806___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_806__RX_DCOC_RES_I_806___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_806__RX_DCOC_RES_I_806___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_806__RX_DCOC_RES_Q_806___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_806__RX_DCOC_RES_Q_806___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_806___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_806___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_807 (0x005FCC9C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_807___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_807___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_807__RX_DCOC_RANGE_807___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_807__RX_DCOC_RES_I_807___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_807__RX_DCOC_RES_Q_807___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_807__RX_DCOC_RANGE_807___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_807__RX_DCOC_RANGE_807___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_807__RX_DCOC_RES_I_807___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_807__RX_DCOC_RES_I_807___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_807__RX_DCOC_RES_Q_807___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_807__RX_DCOC_RES_Q_807___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_807___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_807___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_808 (0x005FCCA0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_808___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_808___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_808__RX_DCOC_RANGE_808___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_808__RX_DCOC_RES_I_808___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_808__RX_DCOC_RES_Q_808___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_808__RX_DCOC_RANGE_808___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_808__RX_DCOC_RANGE_808___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_808__RX_DCOC_RES_I_808___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_808__RX_DCOC_RES_I_808___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_808__RX_DCOC_RES_Q_808___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_808__RX_DCOC_RES_Q_808___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_808___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_808___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_809 (0x005FCCA4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_809___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_809___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_809__RX_DCOC_RANGE_809___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_809__RX_DCOC_RES_I_809___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_809__RX_DCOC_RES_Q_809___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_809__RX_DCOC_RANGE_809___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_809__RX_DCOC_RANGE_809___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_809__RX_DCOC_RES_I_809___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_809__RX_DCOC_RES_I_809___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_809__RX_DCOC_RES_Q_809___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_809__RX_DCOC_RES_Q_809___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_809___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_809___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_810 (0x005FCCA8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_810___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_810___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_810__RX_DCOC_RANGE_810___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_810__RX_DCOC_RES_I_810___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_810__RX_DCOC_RES_Q_810___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_810__RX_DCOC_RANGE_810___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_810__RX_DCOC_RANGE_810___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_810__RX_DCOC_RES_I_810___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_810__RX_DCOC_RES_I_810___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_810__RX_DCOC_RES_Q_810___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_810__RX_DCOC_RES_Q_810___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_810___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_810___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_811 (0x005FCCAC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_811___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_811___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_811__RX_DCOC_RANGE_811___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_811__RX_DCOC_RES_I_811___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_811__RX_DCOC_RES_Q_811___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_811__RX_DCOC_RANGE_811___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_811__RX_DCOC_RANGE_811___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_811__RX_DCOC_RES_I_811___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_811__RX_DCOC_RES_I_811___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_811__RX_DCOC_RES_Q_811___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_811__RX_DCOC_RES_Q_811___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_811___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_811___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_812 (0x005FCCB0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_812___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_812___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_812__RX_DCOC_RANGE_812___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_812__RX_DCOC_RES_I_812___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_812__RX_DCOC_RES_Q_812___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_812__RX_DCOC_RANGE_812___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_812__RX_DCOC_RANGE_812___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_812__RX_DCOC_RES_I_812___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_812__RX_DCOC_RES_I_812___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_812__RX_DCOC_RES_Q_812___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_812__RX_DCOC_RES_Q_812___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_812___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_812___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_813 (0x005FCCB4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_813___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_813___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_813__RX_DCOC_RANGE_813___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_813__RX_DCOC_RES_I_813___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_813__RX_DCOC_RES_Q_813___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_813__RX_DCOC_RANGE_813___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_813__RX_DCOC_RANGE_813___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_813__RX_DCOC_RES_I_813___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_813__RX_DCOC_RES_I_813___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_813__RX_DCOC_RES_Q_813___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_813__RX_DCOC_RES_Q_813___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_813___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_813___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_814 (0x005FCCB8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_814___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_814___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_814__RX_DCOC_RANGE_814___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_814__RX_DCOC_RES_I_814___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_814__RX_DCOC_RES_Q_814___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_814__RX_DCOC_RANGE_814___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_814__RX_DCOC_RANGE_814___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_814__RX_DCOC_RES_I_814___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_814__RX_DCOC_RES_I_814___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_814__RX_DCOC_RES_Q_814___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_814__RX_DCOC_RES_Q_814___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_814___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_814___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_815 (0x005FCCBC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_815___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_815___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_815__RX_DCOC_RANGE_815___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_815__RX_DCOC_RES_I_815___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_815__RX_DCOC_RES_Q_815___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_815__RX_DCOC_RANGE_815___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_815__RX_DCOC_RANGE_815___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_815__RX_DCOC_RES_I_815___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_815__RX_DCOC_RES_I_815___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_815__RX_DCOC_RES_Q_815___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_815__RX_DCOC_RES_Q_815___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_815___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_815___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_816 (0x005FCCC0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_816___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_816___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_816__RX_DCOC_RANGE_816___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_816__RX_DCOC_RES_I_816___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_816__RX_DCOC_RES_Q_816___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_816__RX_DCOC_RANGE_816___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_816__RX_DCOC_RANGE_816___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_816__RX_DCOC_RES_I_816___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_816__RX_DCOC_RES_I_816___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_816__RX_DCOC_RES_Q_816___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_816__RX_DCOC_RES_Q_816___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_816___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_816___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_817 (0x005FCCC4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_817___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_817___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_817__RX_DCOC_RANGE_817___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_817__RX_DCOC_RES_I_817___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_817__RX_DCOC_RES_Q_817___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_817__RX_DCOC_RANGE_817___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_817__RX_DCOC_RANGE_817___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_817__RX_DCOC_RES_I_817___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_817__RX_DCOC_RES_I_817___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_817__RX_DCOC_RES_Q_817___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_817__RX_DCOC_RES_Q_817___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_817___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_817___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_818 (0x005FCCC8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_818___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_818___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_818__RX_DCOC_RANGE_818___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_818__RX_DCOC_RES_I_818___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_818__RX_DCOC_RES_Q_818___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_818__RX_DCOC_RANGE_818___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_818__RX_DCOC_RANGE_818___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_818__RX_DCOC_RES_I_818___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_818__RX_DCOC_RES_I_818___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_818__RX_DCOC_RES_Q_818___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_818__RX_DCOC_RES_Q_818___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_818___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_818___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_819 (0x005FCCCC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_819___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_819___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_819__RX_DCOC_RANGE_819___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_819__RX_DCOC_RES_I_819___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_819__RX_DCOC_RES_Q_819___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_819__RX_DCOC_RANGE_819___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_819__RX_DCOC_RANGE_819___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_819__RX_DCOC_RES_I_819___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_819__RX_DCOC_RES_I_819___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_819__RX_DCOC_RES_Q_819___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_819__RX_DCOC_RES_Q_819___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_819___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_819___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_820 (0x005FCCD0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_820___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_820___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_820__RX_DCOC_RANGE_820___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_820__RX_DCOC_RES_I_820___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_820__RX_DCOC_RES_Q_820___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_820__RX_DCOC_RANGE_820___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_820__RX_DCOC_RANGE_820___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_820__RX_DCOC_RES_I_820___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_820__RX_DCOC_RES_I_820___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_820__RX_DCOC_RES_Q_820___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_820__RX_DCOC_RES_Q_820___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_820___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_820___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_821 (0x005FCCD4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_821___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_821___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_821__RX_DCOC_RANGE_821___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_821__RX_DCOC_RES_I_821___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_821__RX_DCOC_RES_Q_821___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_821__RX_DCOC_RANGE_821___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_821__RX_DCOC_RANGE_821___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_821__RX_DCOC_RES_I_821___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_821__RX_DCOC_RES_I_821___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_821__RX_DCOC_RES_Q_821___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_821__RX_DCOC_RES_Q_821___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_821___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_821___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_822 (0x005FCCD8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_822___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_822___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_822__RX_DCOC_RANGE_822___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_822__RX_DCOC_RES_I_822___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_822__RX_DCOC_RES_Q_822___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_822__RX_DCOC_RANGE_822___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_822__RX_DCOC_RANGE_822___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_822__RX_DCOC_RES_I_822___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_822__RX_DCOC_RES_I_822___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_822__RX_DCOC_RES_Q_822___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_822__RX_DCOC_RES_Q_822___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_822___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_822___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_823 (0x005FCCDC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_823___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_823___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_823__RX_DCOC_RANGE_823___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_823__RX_DCOC_RES_I_823___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_823__RX_DCOC_RES_Q_823___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_823__RX_DCOC_RANGE_823___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_823__RX_DCOC_RANGE_823___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_823__RX_DCOC_RES_I_823___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_823__RX_DCOC_RES_I_823___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_823__RX_DCOC_RES_Q_823___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_823__RX_DCOC_RES_Q_823___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_823___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_823___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_824 (0x005FCCE0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_824___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_824___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_824__RX_DCOC_RANGE_824___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_824__RX_DCOC_RES_I_824___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_824__RX_DCOC_RES_Q_824___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_824__RX_DCOC_RANGE_824___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_824__RX_DCOC_RANGE_824___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_824__RX_DCOC_RES_I_824___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_824__RX_DCOC_RES_I_824___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_824__RX_DCOC_RES_Q_824___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_824__RX_DCOC_RES_Q_824___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_824___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_824___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_825 (0x005FCCE4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_825___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_825___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_825__RX_DCOC_RANGE_825___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_825__RX_DCOC_RES_I_825___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_825__RX_DCOC_RES_Q_825___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_825__RX_DCOC_RANGE_825___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_825__RX_DCOC_RANGE_825___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_825__RX_DCOC_RES_I_825___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_825__RX_DCOC_RES_I_825___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_825__RX_DCOC_RES_Q_825___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_825__RX_DCOC_RES_Q_825___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_825___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_825___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_826 (0x005FCCE8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_826___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_826___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_826__RX_DCOC_RANGE_826___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_826__RX_DCOC_RES_I_826___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_826__RX_DCOC_RES_Q_826___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_826__RX_DCOC_RANGE_826___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_826__RX_DCOC_RANGE_826___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_826__RX_DCOC_RES_I_826___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_826__RX_DCOC_RES_I_826___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_826__RX_DCOC_RES_Q_826___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_826__RX_DCOC_RES_Q_826___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_826___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_826___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_827 (0x005FCCEC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_827___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_827___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_827__RX_DCOC_RANGE_827___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_827__RX_DCOC_RES_I_827___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_827__RX_DCOC_RES_Q_827___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_827__RX_DCOC_RANGE_827___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_827__RX_DCOC_RANGE_827___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_827__RX_DCOC_RES_I_827___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_827__RX_DCOC_RES_I_827___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_827__RX_DCOC_RES_Q_827___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_827__RX_DCOC_RES_Q_827___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_827___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_827___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_828 (0x005FCCF0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_828___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_828___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_828__RX_DCOC_RANGE_828___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_828__RX_DCOC_RES_I_828___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_828__RX_DCOC_RES_Q_828___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_828__RX_DCOC_RANGE_828___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_828__RX_DCOC_RANGE_828___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_828__RX_DCOC_RES_I_828___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_828__RX_DCOC_RES_I_828___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_828__RX_DCOC_RES_Q_828___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_828__RX_DCOC_RES_Q_828___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_828___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_828___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_829 (0x005FCCF4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_829___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_829___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_829__RX_DCOC_RANGE_829___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_829__RX_DCOC_RES_I_829___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_829__RX_DCOC_RES_Q_829___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_829__RX_DCOC_RANGE_829___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_829__RX_DCOC_RANGE_829___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_829__RX_DCOC_RES_I_829___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_829__RX_DCOC_RES_I_829___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_829__RX_DCOC_RES_Q_829___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_829__RX_DCOC_RES_Q_829___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_829___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_829___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_830 (0x005FCCF8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_830___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_830___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_830__RX_DCOC_RANGE_830___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_830__RX_DCOC_RES_I_830___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_830__RX_DCOC_RES_Q_830___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_830__RX_DCOC_RANGE_830___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_830__RX_DCOC_RANGE_830___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_830__RX_DCOC_RES_I_830___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_830__RX_DCOC_RES_I_830___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_830__RX_DCOC_RES_Q_830___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_830__RX_DCOC_RES_Q_830___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_830___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_830___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_831 (0x005FCCFC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_831___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_831___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_831__RX_DCOC_RANGE_831___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_831__RX_DCOC_RES_I_831___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_831__RX_DCOC_RES_Q_831___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_831__RX_DCOC_RANGE_831___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_831__RX_DCOC_RANGE_831___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_831__RX_DCOC_RES_I_831___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_831__RX_DCOC_RES_I_831___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_831__RX_DCOC_RES_Q_831___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_831__RX_DCOC_RES_Q_831___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_831___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_831___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_832 (0x005FCD00) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_832___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_832___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_832__RX_DCOC_RANGE_832___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_832__RX_DCOC_RES_I_832___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_832__RX_DCOC_RES_Q_832___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_832__RX_DCOC_RANGE_832___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_832__RX_DCOC_RANGE_832___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_832__RX_DCOC_RES_I_832___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_832__RX_DCOC_RES_I_832___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_832__RX_DCOC_RES_Q_832___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_832__RX_DCOC_RES_Q_832___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_832___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_832___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_833 (0x005FCD04) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_833___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_833___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_833__RX_DCOC_RANGE_833___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_833__RX_DCOC_RES_I_833___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_833__RX_DCOC_RES_Q_833___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_833__RX_DCOC_RANGE_833___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_833__RX_DCOC_RANGE_833___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_833__RX_DCOC_RES_I_833___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_833__RX_DCOC_RES_I_833___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_833__RX_DCOC_RES_Q_833___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_833__RX_DCOC_RES_Q_833___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_833___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_833___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_834 (0x005FCD08) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_834___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_834___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_834__RX_DCOC_RANGE_834___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_834__RX_DCOC_RES_I_834___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_834__RX_DCOC_RES_Q_834___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_834__RX_DCOC_RANGE_834___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_834__RX_DCOC_RANGE_834___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_834__RX_DCOC_RES_I_834___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_834__RX_DCOC_RES_I_834___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_834__RX_DCOC_RES_Q_834___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_834__RX_DCOC_RES_Q_834___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_834___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_834___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_835 (0x005FCD0C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_835___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_835___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_835__RX_DCOC_RANGE_835___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_835__RX_DCOC_RES_I_835___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_835__RX_DCOC_RES_Q_835___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_835__RX_DCOC_RANGE_835___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_835__RX_DCOC_RANGE_835___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_835__RX_DCOC_RES_I_835___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_835__RX_DCOC_RES_I_835___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_835__RX_DCOC_RES_Q_835___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_835__RX_DCOC_RES_Q_835___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_835___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_835___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_836 (0x005FCD10) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_836___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_836___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_836__RX_DCOC_RANGE_836___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_836__RX_DCOC_RES_I_836___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_836__RX_DCOC_RES_Q_836___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_836__RX_DCOC_RANGE_836___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_836__RX_DCOC_RANGE_836___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_836__RX_DCOC_RES_I_836___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_836__RX_DCOC_RES_I_836___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_836__RX_DCOC_RES_Q_836___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_836__RX_DCOC_RES_Q_836___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_836___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_836___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_837 (0x005FCD14) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_837___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_837___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_837__RX_DCOC_RANGE_837___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_837__RX_DCOC_RES_I_837___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_837__RX_DCOC_RES_Q_837___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_837__RX_DCOC_RANGE_837___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_837__RX_DCOC_RANGE_837___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_837__RX_DCOC_RES_I_837___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_837__RX_DCOC_RES_I_837___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_837__RX_DCOC_RES_Q_837___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_837__RX_DCOC_RES_Q_837___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_837___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_837___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_838 (0x005FCD18) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_838___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_838___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_838__RX_DCOC_RANGE_838___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_838__RX_DCOC_RES_I_838___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_838__RX_DCOC_RES_Q_838___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_838__RX_DCOC_RANGE_838___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_838__RX_DCOC_RANGE_838___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_838__RX_DCOC_RES_I_838___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_838__RX_DCOC_RES_I_838___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_838__RX_DCOC_RES_Q_838___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_838__RX_DCOC_RES_Q_838___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_838___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_838___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_839 (0x005FCD1C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_839___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_839___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_839__RX_DCOC_RANGE_839___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_839__RX_DCOC_RES_I_839___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_839__RX_DCOC_RES_Q_839___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_839__RX_DCOC_RANGE_839___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_839__RX_DCOC_RANGE_839___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_839__RX_DCOC_RES_I_839___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_839__RX_DCOC_RES_I_839___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_839__RX_DCOC_RES_Q_839___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_839__RX_DCOC_RES_Q_839___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_839___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_839___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_840 (0x005FCD20) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_840___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_840___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_840__RX_DCOC_RANGE_840___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_840__RX_DCOC_RES_I_840___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_840__RX_DCOC_RES_Q_840___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_840__RX_DCOC_RANGE_840___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_840__RX_DCOC_RANGE_840___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_840__RX_DCOC_RES_I_840___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_840__RX_DCOC_RES_I_840___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_840__RX_DCOC_RES_Q_840___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_840__RX_DCOC_RES_Q_840___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_840___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_840___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_841 (0x005FCD24) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_841___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_841___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_841__RX_DCOC_RANGE_841___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_841__RX_DCOC_RES_I_841___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_841__RX_DCOC_RES_Q_841___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_841__RX_DCOC_RANGE_841___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_841__RX_DCOC_RANGE_841___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_841__RX_DCOC_RES_I_841___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_841__RX_DCOC_RES_I_841___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_841__RX_DCOC_RES_Q_841___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_841__RX_DCOC_RES_Q_841___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_841___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_841___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_842 (0x005FCD28) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_842___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_842___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_842__RX_DCOC_RANGE_842___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_842__RX_DCOC_RES_I_842___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_842__RX_DCOC_RES_Q_842___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_842__RX_DCOC_RANGE_842___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_842__RX_DCOC_RANGE_842___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_842__RX_DCOC_RES_I_842___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_842__RX_DCOC_RES_I_842___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_842__RX_DCOC_RES_Q_842___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_842__RX_DCOC_RES_Q_842___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_842___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_842___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_843 (0x005FCD2C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_843___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_843___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_843__RX_DCOC_RANGE_843___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_843__RX_DCOC_RES_I_843___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_843__RX_DCOC_RES_Q_843___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_843__RX_DCOC_RANGE_843___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_843__RX_DCOC_RANGE_843___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_843__RX_DCOC_RES_I_843___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_843__RX_DCOC_RES_I_843___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_843__RX_DCOC_RES_Q_843___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_843__RX_DCOC_RES_Q_843___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_843___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_843___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_844 (0x005FCD30) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_844___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_844___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_844__RX_DCOC_RANGE_844___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_844__RX_DCOC_RES_I_844___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_844__RX_DCOC_RES_Q_844___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_844__RX_DCOC_RANGE_844___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_844__RX_DCOC_RANGE_844___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_844__RX_DCOC_RES_I_844___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_844__RX_DCOC_RES_I_844___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_844__RX_DCOC_RES_Q_844___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_844__RX_DCOC_RES_Q_844___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_844___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_844___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_845 (0x005FCD34) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_845___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_845___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_845__RX_DCOC_RANGE_845___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_845__RX_DCOC_RES_I_845___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_845__RX_DCOC_RES_Q_845___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_845__RX_DCOC_RANGE_845___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_845__RX_DCOC_RANGE_845___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_845__RX_DCOC_RES_I_845___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_845__RX_DCOC_RES_I_845___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_845__RX_DCOC_RES_Q_845___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_845__RX_DCOC_RES_Q_845___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_845___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_845___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_846 (0x005FCD38) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_846___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_846___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_846__RX_DCOC_RANGE_846___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_846__RX_DCOC_RES_I_846___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_846__RX_DCOC_RES_Q_846___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_846__RX_DCOC_RANGE_846___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_846__RX_DCOC_RANGE_846___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_846__RX_DCOC_RES_I_846___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_846__RX_DCOC_RES_I_846___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_846__RX_DCOC_RES_Q_846___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_846__RX_DCOC_RES_Q_846___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_846___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_846___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_847 (0x005FCD3C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_847___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_847___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_847__RX_DCOC_RANGE_847___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_847__RX_DCOC_RES_I_847___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_847__RX_DCOC_RES_Q_847___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_847__RX_DCOC_RANGE_847___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_847__RX_DCOC_RANGE_847___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_847__RX_DCOC_RES_I_847___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_847__RX_DCOC_RES_I_847___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_847__RX_DCOC_RES_Q_847___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_847__RX_DCOC_RES_Q_847___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_847___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_847___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_848 (0x005FCD40) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_848___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_848___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_848__RX_DCOC_RANGE_848___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_848__RX_DCOC_RES_I_848___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_848__RX_DCOC_RES_Q_848___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_848__RX_DCOC_RANGE_848___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_848__RX_DCOC_RANGE_848___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_848__RX_DCOC_RES_I_848___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_848__RX_DCOC_RES_I_848___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_848__RX_DCOC_RES_Q_848___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_848__RX_DCOC_RES_Q_848___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_848___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_848___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_849 (0x005FCD44) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_849___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_849___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_849__RX_DCOC_RANGE_849___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_849__RX_DCOC_RES_I_849___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_849__RX_DCOC_RES_Q_849___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_849__RX_DCOC_RANGE_849___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_849__RX_DCOC_RANGE_849___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_849__RX_DCOC_RES_I_849___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_849__RX_DCOC_RES_I_849___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_849__RX_DCOC_RES_Q_849___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_849__RX_DCOC_RES_Q_849___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_849___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_849___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_850 (0x005FCD48) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_850___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_850___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_850__RX_DCOC_RANGE_850___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_850__RX_DCOC_RES_I_850___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_850__RX_DCOC_RES_Q_850___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_850__RX_DCOC_RANGE_850___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_850__RX_DCOC_RANGE_850___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_850__RX_DCOC_RES_I_850___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_850__RX_DCOC_RES_I_850___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_850__RX_DCOC_RES_Q_850___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_850__RX_DCOC_RES_Q_850___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_850___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_850___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_851 (0x005FCD4C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_851___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_851___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_851__RX_DCOC_RANGE_851___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_851__RX_DCOC_RES_I_851___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_851__RX_DCOC_RES_Q_851___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_851__RX_DCOC_RANGE_851___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_851__RX_DCOC_RANGE_851___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_851__RX_DCOC_RES_I_851___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_851__RX_DCOC_RES_I_851___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_851__RX_DCOC_RES_Q_851___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_851__RX_DCOC_RES_Q_851___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_851___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_851___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_852 (0x005FCD50) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_852___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_852___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_852__RX_DCOC_RANGE_852___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_852__RX_DCOC_RES_I_852___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_852__RX_DCOC_RES_Q_852___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_852__RX_DCOC_RANGE_852___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_852__RX_DCOC_RANGE_852___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_852__RX_DCOC_RES_I_852___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_852__RX_DCOC_RES_I_852___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_852__RX_DCOC_RES_Q_852___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_852__RX_DCOC_RES_Q_852___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_852___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_852___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_853 (0x005FCD54) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_853___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_853___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_853__RX_DCOC_RANGE_853___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_853__RX_DCOC_RES_I_853___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_853__RX_DCOC_RES_Q_853___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_853__RX_DCOC_RANGE_853___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_853__RX_DCOC_RANGE_853___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_853__RX_DCOC_RES_I_853___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_853__RX_DCOC_RES_I_853___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_853__RX_DCOC_RES_Q_853___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_853__RX_DCOC_RES_Q_853___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_853___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_853___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_854 (0x005FCD58) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_854___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_854___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_854__RX_DCOC_RANGE_854___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_854__RX_DCOC_RES_I_854___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_854__RX_DCOC_RES_Q_854___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_854__RX_DCOC_RANGE_854___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_854__RX_DCOC_RANGE_854___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_854__RX_DCOC_RES_I_854___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_854__RX_DCOC_RES_I_854___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_854__RX_DCOC_RES_Q_854___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_854__RX_DCOC_RES_Q_854___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_854___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_854___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_855 (0x005FCD5C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_855___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_855___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_855__RX_DCOC_RANGE_855___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_855__RX_DCOC_RES_I_855___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_855__RX_DCOC_RES_Q_855___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_855__RX_DCOC_RANGE_855___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_855__RX_DCOC_RANGE_855___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_855__RX_DCOC_RES_I_855___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_855__RX_DCOC_RES_I_855___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_855__RX_DCOC_RES_Q_855___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_855__RX_DCOC_RES_Q_855___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_855___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_855___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_856 (0x005FCD60) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_856___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_856___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_856__RX_DCOC_RANGE_856___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_856__RX_DCOC_RES_I_856___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_856__RX_DCOC_RES_Q_856___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_856__RX_DCOC_RANGE_856___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_856__RX_DCOC_RANGE_856___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_856__RX_DCOC_RES_I_856___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_856__RX_DCOC_RES_I_856___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_856__RX_DCOC_RES_Q_856___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_856__RX_DCOC_RES_Q_856___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_856___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_856___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_857 (0x005FCD64) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_857___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_857___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_857__RX_DCOC_RANGE_857___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_857__RX_DCOC_RES_I_857___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_857__RX_DCOC_RES_Q_857___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_857__RX_DCOC_RANGE_857___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_857__RX_DCOC_RANGE_857___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_857__RX_DCOC_RES_I_857___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_857__RX_DCOC_RES_I_857___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_857__RX_DCOC_RES_Q_857___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_857__RX_DCOC_RES_Q_857___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_857___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_857___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_858 (0x005FCD68) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_858___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_858___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_858__RX_DCOC_RANGE_858___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_858__RX_DCOC_RES_I_858___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_858__RX_DCOC_RES_Q_858___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_858__RX_DCOC_RANGE_858___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_858__RX_DCOC_RANGE_858___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_858__RX_DCOC_RES_I_858___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_858__RX_DCOC_RES_I_858___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_858__RX_DCOC_RES_Q_858___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_858__RX_DCOC_RES_Q_858___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_858___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_858___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_859 (0x005FCD6C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_859___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_859___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_859__RX_DCOC_RANGE_859___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_859__RX_DCOC_RES_I_859___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_859__RX_DCOC_RES_Q_859___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_859__RX_DCOC_RANGE_859___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_859__RX_DCOC_RANGE_859___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_859__RX_DCOC_RES_I_859___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_859__RX_DCOC_RES_I_859___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_859__RX_DCOC_RES_Q_859___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_859__RX_DCOC_RES_Q_859___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_859___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_859___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_860 (0x005FCD70) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_860___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_860___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_860__RX_DCOC_RANGE_860___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_860__RX_DCOC_RES_I_860___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_860__RX_DCOC_RES_Q_860___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_860__RX_DCOC_RANGE_860___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_860__RX_DCOC_RANGE_860___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_860__RX_DCOC_RES_I_860___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_860__RX_DCOC_RES_I_860___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_860__RX_DCOC_RES_Q_860___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_860__RX_DCOC_RES_Q_860___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_860___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_860___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_861 (0x005FCD74) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_861___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_861___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_861__RX_DCOC_RANGE_861___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_861__RX_DCOC_RES_I_861___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_861__RX_DCOC_RES_Q_861___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_861__RX_DCOC_RANGE_861___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_861__RX_DCOC_RANGE_861___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_861__RX_DCOC_RES_I_861___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_861__RX_DCOC_RES_I_861___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_861__RX_DCOC_RES_Q_861___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_861__RX_DCOC_RES_Q_861___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_861___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_861___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_862 (0x005FCD78) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_862___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_862___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_862__RX_DCOC_RANGE_862___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_862__RX_DCOC_RES_I_862___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_862__RX_DCOC_RES_Q_862___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_862__RX_DCOC_RANGE_862___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_862__RX_DCOC_RANGE_862___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_862__RX_DCOC_RES_I_862___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_862__RX_DCOC_RES_I_862___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_862__RX_DCOC_RES_Q_862___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_862__RX_DCOC_RES_Q_862___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_862___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_862___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_863 (0x005FCD7C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_863___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_863___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_863__RX_DCOC_RANGE_863___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_863__RX_DCOC_RES_I_863___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_863__RX_DCOC_RES_Q_863___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_863__RX_DCOC_RANGE_863___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_863__RX_DCOC_RANGE_863___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_863__RX_DCOC_RES_I_863___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_863__RX_DCOC_RES_I_863___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_863__RX_DCOC_RES_Q_863___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_863__RX_DCOC_RES_Q_863___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_863___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_863___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_864 (0x005FCD80) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_864___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_864___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_864__RX_DCOC_RANGE_864___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_864__RX_DCOC_RES_I_864___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_864__RX_DCOC_RES_Q_864___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_864__RX_DCOC_RANGE_864___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_864__RX_DCOC_RANGE_864___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_864__RX_DCOC_RES_I_864___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_864__RX_DCOC_RES_I_864___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_864__RX_DCOC_RES_Q_864___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_864__RX_DCOC_RES_Q_864___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_864___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_864___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_865 (0x005FCD84) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_865___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_865___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_865__RX_DCOC_RANGE_865___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_865__RX_DCOC_RES_I_865___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_865__RX_DCOC_RES_Q_865___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_865__RX_DCOC_RANGE_865___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_865__RX_DCOC_RANGE_865___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_865__RX_DCOC_RES_I_865___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_865__RX_DCOC_RES_I_865___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_865__RX_DCOC_RES_Q_865___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_865__RX_DCOC_RES_Q_865___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_865___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_865___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_866 (0x005FCD88) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_866___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_866___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_866__RX_DCOC_RANGE_866___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_866__RX_DCOC_RES_I_866___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_866__RX_DCOC_RES_Q_866___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_866__RX_DCOC_RANGE_866___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_866__RX_DCOC_RANGE_866___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_866__RX_DCOC_RES_I_866___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_866__RX_DCOC_RES_I_866___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_866__RX_DCOC_RES_Q_866___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_866__RX_DCOC_RES_Q_866___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_866___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_866___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_867 (0x005FCD8C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_867___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_867___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_867__RX_DCOC_RANGE_867___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_867__RX_DCOC_RES_I_867___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_867__RX_DCOC_RES_Q_867___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_867__RX_DCOC_RANGE_867___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_867__RX_DCOC_RANGE_867___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_867__RX_DCOC_RES_I_867___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_867__RX_DCOC_RES_I_867___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_867__RX_DCOC_RES_Q_867___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_867__RX_DCOC_RES_Q_867___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_867___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_867___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_868 (0x005FCD90) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_868___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_868___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_868__RX_DCOC_RANGE_868___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_868__RX_DCOC_RES_I_868___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_868__RX_DCOC_RES_Q_868___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_868__RX_DCOC_RANGE_868___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_868__RX_DCOC_RANGE_868___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_868__RX_DCOC_RES_I_868___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_868__RX_DCOC_RES_I_868___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_868__RX_DCOC_RES_Q_868___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_868__RX_DCOC_RES_Q_868___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_868___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_868___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_869 (0x005FCD94) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_869___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_869___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_869__RX_DCOC_RANGE_869___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_869__RX_DCOC_RES_I_869___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_869__RX_DCOC_RES_Q_869___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_869__RX_DCOC_RANGE_869___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_869__RX_DCOC_RANGE_869___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_869__RX_DCOC_RES_I_869___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_869__RX_DCOC_RES_I_869___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_869__RX_DCOC_RES_Q_869___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_869__RX_DCOC_RES_Q_869___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_869___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_869___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_870 (0x005FCD98) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_870___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_870___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_870__RX_DCOC_RANGE_870___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_870__RX_DCOC_RES_I_870___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_870__RX_DCOC_RES_Q_870___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_870__RX_DCOC_RANGE_870___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_870__RX_DCOC_RANGE_870___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_870__RX_DCOC_RES_I_870___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_870__RX_DCOC_RES_I_870___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_870__RX_DCOC_RES_Q_870___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_870__RX_DCOC_RES_Q_870___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_870___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_870___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_871 (0x005FCD9C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_871___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_871___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_871__RX_DCOC_RANGE_871___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_871__RX_DCOC_RES_I_871___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_871__RX_DCOC_RES_Q_871___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_871__RX_DCOC_RANGE_871___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_871__RX_DCOC_RANGE_871___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_871__RX_DCOC_RES_I_871___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_871__RX_DCOC_RES_I_871___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_871__RX_DCOC_RES_Q_871___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_871__RX_DCOC_RES_Q_871___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_871___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_871___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_872 (0x005FCDA0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_872___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_872___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_872__RX_DCOC_RANGE_872___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_872__RX_DCOC_RES_I_872___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_872__RX_DCOC_RES_Q_872___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_872__RX_DCOC_RANGE_872___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_872__RX_DCOC_RANGE_872___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_872__RX_DCOC_RES_I_872___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_872__RX_DCOC_RES_I_872___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_872__RX_DCOC_RES_Q_872___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_872__RX_DCOC_RES_Q_872___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_872___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_872___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_873 (0x005FCDA4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_873___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_873___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_873__RX_DCOC_RANGE_873___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_873__RX_DCOC_RES_I_873___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_873__RX_DCOC_RES_Q_873___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_873__RX_DCOC_RANGE_873___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_873__RX_DCOC_RANGE_873___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_873__RX_DCOC_RES_I_873___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_873__RX_DCOC_RES_I_873___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_873__RX_DCOC_RES_Q_873___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_873__RX_DCOC_RES_Q_873___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_873___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_873___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_874 (0x005FCDA8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_874___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_874___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_874__RX_DCOC_RANGE_874___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_874__RX_DCOC_RES_I_874___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_874__RX_DCOC_RES_Q_874___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_874__RX_DCOC_RANGE_874___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_874__RX_DCOC_RANGE_874___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_874__RX_DCOC_RES_I_874___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_874__RX_DCOC_RES_I_874___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_874__RX_DCOC_RES_Q_874___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_874__RX_DCOC_RES_Q_874___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_874___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_874___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_875 (0x005FCDAC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_875___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_875___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_875__RX_DCOC_RANGE_875___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_875__RX_DCOC_RES_I_875___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_875__RX_DCOC_RES_Q_875___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_875__RX_DCOC_RANGE_875___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_875__RX_DCOC_RANGE_875___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_875__RX_DCOC_RES_I_875___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_875__RX_DCOC_RES_I_875___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_875__RX_DCOC_RES_Q_875___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_875__RX_DCOC_RES_Q_875___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_875___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_875___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_876 (0x005FCDB0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_876___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_876___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_876__RX_DCOC_RANGE_876___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_876__RX_DCOC_RES_I_876___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_876__RX_DCOC_RES_Q_876___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_876__RX_DCOC_RANGE_876___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_876__RX_DCOC_RANGE_876___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_876__RX_DCOC_RES_I_876___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_876__RX_DCOC_RES_I_876___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_876__RX_DCOC_RES_Q_876___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_876__RX_DCOC_RES_Q_876___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_876___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_876___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_877 (0x005FCDB4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_877___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_877___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_877__RX_DCOC_RANGE_877___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_877__RX_DCOC_RES_I_877___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_877__RX_DCOC_RES_Q_877___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_877__RX_DCOC_RANGE_877___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_877__RX_DCOC_RANGE_877___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_877__RX_DCOC_RES_I_877___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_877__RX_DCOC_RES_I_877___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_877__RX_DCOC_RES_Q_877___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_877__RX_DCOC_RES_Q_877___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_877___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_877___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_878 (0x005FCDB8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_878___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_878___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_878__RX_DCOC_RANGE_878___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_878__RX_DCOC_RES_I_878___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_878__RX_DCOC_RES_Q_878___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_878__RX_DCOC_RANGE_878___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_878__RX_DCOC_RANGE_878___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_878__RX_DCOC_RES_I_878___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_878__RX_DCOC_RES_I_878___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_878__RX_DCOC_RES_Q_878___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_878__RX_DCOC_RES_Q_878___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_878___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_878___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_879 (0x005FCDBC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_879___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_879___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_879__RX_DCOC_RANGE_879___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_879__RX_DCOC_RES_I_879___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_879__RX_DCOC_RES_Q_879___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_879__RX_DCOC_RANGE_879___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_879__RX_DCOC_RANGE_879___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_879__RX_DCOC_RES_I_879___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_879__RX_DCOC_RES_I_879___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_879__RX_DCOC_RES_Q_879___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_879__RX_DCOC_RES_Q_879___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_879___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_879___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_880 (0x005FCDC0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_880___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_880___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_880__RX_DCOC_RANGE_880___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_880__RX_DCOC_RES_I_880___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_880__RX_DCOC_RES_Q_880___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_880__RX_DCOC_RANGE_880___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_880__RX_DCOC_RANGE_880___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_880__RX_DCOC_RES_I_880___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_880__RX_DCOC_RES_I_880___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_880__RX_DCOC_RES_Q_880___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_880__RX_DCOC_RES_Q_880___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_880___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_880___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_881 (0x005FCDC4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_881___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_881___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_881__RX_DCOC_RANGE_881___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_881__RX_DCOC_RES_I_881___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_881__RX_DCOC_RES_Q_881___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_881__RX_DCOC_RANGE_881___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_881__RX_DCOC_RANGE_881___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_881__RX_DCOC_RES_I_881___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_881__RX_DCOC_RES_I_881___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_881__RX_DCOC_RES_Q_881___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_881__RX_DCOC_RES_Q_881___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_881___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_881___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_882 (0x005FCDC8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_882___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_882___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_882__RX_DCOC_RANGE_882___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_882__RX_DCOC_RES_I_882___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_882__RX_DCOC_RES_Q_882___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_882__RX_DCOC_RANGE_882___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_882__RX_DCOC_RANGE_882___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_882__RX_DCOC_RES_I_882___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_882__RX_DCOC_RES_I_882___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_882__RX_DCOC_RES_Q_882___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_882__RX_DCOC_RES_Q_882___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_882___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_882___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_883 (0x005FCDCC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_883___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_883___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_883__RX_DCOC_RANGE_883___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_883__RX_DCOC_RES_I_883___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_883__RX_DCOC_RES_Q_883___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_883__RX_DCOC_RANGE_883___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_883__RX_DCOC_RANGE_883___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_883__RX_DCOC_RES_I_883___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_883__RX_DCOC_RES_I_883___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_883__RX_DCOC_RES_Q_883___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_883__RX_DCOC_RES_Q_883___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_883___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_883___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_884 (0x005FCDD0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_884___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_884___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_884__RX_DCOC_RANGE_884___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_884__RX_DCOC_RES_I_884___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_884__RX_DCOC_RES_Q_884___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_884__RX_DCOC_RANGE_884___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_884__RX_DCOC_RANGE_884___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_884__RX_DCOC_RES_I_884___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_884__RX_DCOC_RES_I_884___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_884__RX_DCOC_RES_Q_884___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_884__RX_DCOC_RES_Q_884___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_884___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_884___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_885 (0x005FCDD4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_885___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_885___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_885__RX_DCOC_RANGE_885___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_885__RX_DCOC_RES_I_885___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_885__RX_DCOC_RES_Q_885___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_885__RX_DCOC_RANGE_885___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_885__RX_DCOC_RANGE_885___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_885__RX_DCOC_RES_I_885___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_885__RX_DCOC_RES_I_885___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_885__RX_DCOC_RES_Q_885___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_885__RX_DCOC_RES_Q_885___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_885___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_885___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_886 (0x005FCDD8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_886___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_886___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_886__RX_DCOC_RANGE_886___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_886__RX_DCOC_RES_I_886___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_886__RX_DCOC_RES_Q_886___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_886__RX_DCOC_RANGE_886___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_886__RX_DCOC_RANGE_886___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_886__RX_DCOC_RES_I_886___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_886__RX_DCOC_RES_I_886___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_886__RX_DCOC_RES_Q_886___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_886__RX_DCOC_RES_Q_886___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_886___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_886___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_887 (0x005FCDDC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_887___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_887___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_887__RX_DCOC_RANGE_887___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_887__RX_DCOC_RES_I_887___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_887__RX_DCOC_RES_Q_887___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_887__RX_DCOC_RANGE_887___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_887__RX_DCOC_RANGE_887___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_887__RX_DCOC_RES_I_887___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_887__RX_DCOC_RES_I_887___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_887__RX_DCOC_RES_Q_887___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_887__RX_DCOC_RES_Q_887___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_887___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_887___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_888 (0x005FCDE0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_888___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_888___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_888__RX_DCOC_RANGE_888___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_888__RX_DCOC_RES_I_888___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_888__RX_DCOC_RES_Q_888___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_888__RX_DCOC_RANGE_888___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_888__RX_DCOC_RANGE_888___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_888__RX_DCOC_RES_I_888___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_888__RX_DCOC_RES_I_888___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_888__RX_DCOC_RES_Q_888___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_888__RX_DCOC_RES_Q_888___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_888___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_888___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_889 (0x005FCDE4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_889___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_889___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_889__RX_DCOC_RANGE_889___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_889__RX_DCOC_RES_I_889___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_889__RX_DCOC_RES_Q_889___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_889__RX_DCOC_RANGE_889___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_889__RX_DCOC_RANGE_889___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_889__RX_DCOC_RES_I_889___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_889__RX_DCOC_RES_I_889___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_889__RX_DCOC_RES_Q_889___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_889__RX_DCOC_RES_Q_889___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_889___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_889___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_890 (0x005FCDE8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_890___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_890___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_890__RX_DCOC_RANGE_890___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_890__RX_DCOC_RES_I_890___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_890__RX_DCOC_RES_Q_890___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_890__RX_DCOC_RANGE_890___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_890__RX_DCOC_RANGE_890___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_890__RX_DCOC_RES_I_890___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_890__RX_DCOC_RES_I_890___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_890__RX_DCOC_RES_Q_890___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_890__RX_DCOC_RES_Q_890___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_890___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_890___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_891 (0x005FCDEC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_891___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_891___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_891__RX_DCOC_RANGE_891___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_891__RX_DCOC_RES_I_891___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_891__RX_DCOC_RES_Q_891___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_891__RX_DCOC_RANGE_891___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_891__RX_DCOC_RANGE_891___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_891__RX_DCOC_RES_I_891___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_891__RX_DCOC_RES_I_891___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_891__RX_DCOC_RES_Q_891___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_891__RX_DCOC_RES_Q_891___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_891___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_891___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_892 (0x005FCDF0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_892___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_892___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_892__RX_DCOC_RANGE_892___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_892__RX_DCOC_RES_I_892___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_892__RX_DCOC_RES_Q_892___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_892__RX_DCOC_RANGE_892___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_892__RX_DCOC_RANGE_892___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_892__RX_DCOC_RES_I_892___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_892__RX_DCOC_RES_I_892___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_892__RX_DCOC_RES_Q_892___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_892__RX_DCOC_RES_Q_892___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_892___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_892___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_893 (0x005FCDF4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_893___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_893___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_893__RX_DCOC_RANGE_893___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_893__RX_DCOC_RES_I_893___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_893__RX_DCOC_RES_Q_893___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_893__RX_DCOC_RANGE_893___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_893__RX_DCOC_RANGE_893___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_893__RX_DCOC_RES_I_893___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_893__RX_DCOC_RES_I_893___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_893__RX_DCOC_RES_Q_893___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_893__RX_DCOC_RES_Q_893___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_893___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_893___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_894 (0x005FCDF8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_894___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_894___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_894__RX_DCOC_RANGE_894___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_894__RX_DCOC_RES_I_894___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_894__RX_DCOC_RES_Q_894___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_894__RX_DCOC_RANGE_894___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_894__RX_DCOC_RANGE_894___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_894__RX_DCOC_RES_I_894___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_894__RX_DCOC_RES_I_894___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_894__RX_DCOC_RES_Q_894___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_894__RX_DCOC_RES_Q_894___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_894___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_894___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_895 (0x005FCDFC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_895___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_895___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_895__RX_DCOC_RANGE_895___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_895__RX_DCOC_RES_I_895___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_895__RX_DCOC_RES_Q_895___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_895__RX_DCOC_RANGE_895___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_895__RX_DCOC_RANGE_895___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_895__RX_DCOC_RES_I_895___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_895__RX_DCOC_RES_I_895___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_895__RX_DCOC_RES_Q_895___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_895__RX_DCOC_RES_Q_895___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_895___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_895___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_896 (0x005FCE00) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_896___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_896___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_896__RX_DCOC_RANGE_896___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_896__RX_DCOC_RES_I_896___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_896__RX_DCOC_RES_Q_896___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_896__RX_DCOC_RANGE_896___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_896__RX_DCOC_RANGE_896___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_896__RX_DCOC_RES_I_896___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_896__RX_DCOC_RES_I_896___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_896__RX_DCOC_RES_Q_896___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_896__RX_DCOC_RES_Q_896___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_896___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_896___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_897 (0x005FCE04) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_897___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_897___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_897__RX_DCOC_RANGE_897___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_897__RX_DCOC_RES_I_897___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_897__RX_DCOC_RES_Q_897___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_897__RX_DCOC_RANGE_897___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_897__RX_DCOC_RANGE_897___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_897__RX_DCOC_RES_I_897___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_897__RX_DCOC_RES_I_897___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_897__RX_DCOC_RES_Q_897___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_897__RX_DCOC_RES_Q_897___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_897___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_897___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_898 (0x005FCE08) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_898___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_898___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_898__RX_DCOC_RANGE_898___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_898__RX_DCOC_RES_I_898___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_898__RX_DCOC_RES_Q_898___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_898__RX_DCOC_RANGE_898___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_898__RX_DCOC_RANGE_898___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_898__RX_DCOC_RES_I_898___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_898__RX_DCOC_RES_I_898___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_898__RX_DCOC_RES_Q_898___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_898__RX_DCOC_RES_Q_898___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_898___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_898___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_899 (0x005FCE0C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_899___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_899___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_899__RX_DCOC_RANGE_899___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_899__RX_DCOC_RES_I_899___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_899__RX_DCOC_RES_Q_899___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_899__RX_DCOC_RANGE_899___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_899__RX_DCOC_RANGE_899___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_899__RX_DCOC_RES_I_899___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_899__RX_DCOC_RES_I_899___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_899__RX_DCOC_RES_Q_899___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_899__RX_DCOC_RES_Q_899___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_899___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_899___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_900 (0x005FCE10) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_900___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_900___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_900__RX_DCOC_RANGE_900___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_900__RX_DCOC_RES_I_900___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_900__RX_DCOC_RES_Q_900___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_900__RX_DCOC_RANGE_900___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_900__RX_DCOC_RANGE_900___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_900__RX_DCOC_RES_I_900___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_900__RX_DCOC_RES_I_900___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_900__RX_DCOC_RES_Q_900___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_900__RX_DCOC_RES_Q_900___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_900___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_900___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_901 (0x005FCE14) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_901___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_901___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_901__RX_DCOC_RANGE_901___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_901__RX_DCOC_RES_I_901___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_901__RX_DCOC_RES_Q_901___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_901__RX_DCOC_RANGE_901___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_901__RX_DCOC_RANGE_901___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_901__RX_DCOC_RES_I_901___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_901__RX_DCOC_RES_I_901___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_901__RX_DCOC_RES_Q_901___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_901__RX_DCOC_RES_Q_901___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_901___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_901___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_902 (0x005FCE18) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_902___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_902___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_902__RX_DCOC_RANGE_902___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_902__RX_DCOC_RES_I_902___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_902__RX_DCOC_RES_Q_902___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_902__RX_DCOC_RANGE_902___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_902__RX_DCOC_RANGE_902___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_902__RX_DCOC_RES_I_902___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_902__RX_DCOC_RES_I_902___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_902__RX_DCOC_RES_Q_902___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_902__RX_DCOC_RES_Q_902___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_902___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_902___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_903 (0x005FCE1C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_903___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_903___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_903__RX_DCOC_RANGE_903___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_903__RX_DCOC_RES_I_903___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_903__RX_DCOC_RES_Q_903___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_903__RX_DCOC_RANGE_903___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_903__RX_DCOC_RANGE_903___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_903__RX_DCOC_RES_I_903___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_903__RX_DCOC_RES_I_903___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_903__RX_DCOC_RES_Q_903___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_903__RX_DCOC_RES_Q_903___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_903___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_903___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_904 (0x005FCE20) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_904___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_904___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_904__RX_DCOC_RANGE_904___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_904__RX_DCOC_RES_I_904___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_904__RX_DCOC_RES_Q_904___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_904__RX_DCOC_RANGE_904___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_904__RX_DCOC_RANGE_904___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_904__RX_DCOC_RES_I_904___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_904__RX_DCOC_RES_I_904___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_904__RX_DCOC_RES_Q_904___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_904__RX_DCOC_RES_Q_904___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_904___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_904___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_905 (0x005FCE24) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_905___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_905___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_905__RX_DCOC_RANGE_905___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_905__RX_DCOC_RES_I_905___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_905__RX_DCOC_RES_Q_905___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_905__RX_DCOC_RANGE_905___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_905__RX_DCOC_RANGE_905___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_905__RX_DCOC_RES_I_905___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_905__RX_DCOC_RES_I_905___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_905__RX_DCOC_RES_Q_905___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_905__RX_DCOC_RES_Q_905___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_905___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_905___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_906 (0x005FCE28) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_906___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_906___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_906__RX_DCOC_RANGE_906___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_906__RX_DCOC_RES_I_906___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_906__RX_DCOC_RES_Q_906___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_906__RX_DCOC_RANGE_906___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_906__RX_DCOC_RANGE_906___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_906__RX_DCOC_RES_I_906___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_906__RX_DCOC_RES_I_906___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_906__RX_DCOC_RES_Q_906___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_906__RX_DCOC_RES_Q_906___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_906___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_906___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_907 (0x005FCE2C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_907___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_907___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_907__RX_DCOC_RANGE_907___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_907__RX_DCOC_RES_I_907___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_907__RX_DCOC_RES_Q_907___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_907__RX_DCOC_RANGE_907___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_907__RX_DCOC_RANGE_907___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_907__RX_DCOC_RES_I_907___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_907__RX_DCOC_RES_I_907___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_907__RX_DCOC_RES_Q_907___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_907__RX_DCOC_RES_Q_907___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_907___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_907___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_908 (0x005FCE30) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_908___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_908___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_908__RX_DCOC_RANGE_908___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_908__RX_DCOC_RES_I_908___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_908__RX_DCOC_RES_Q_908___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_908__RX_DCOC_RANGE_908___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_908__RX_DCOC_RANGE_908___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_908__RX_DCOC_RES_I_908___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_908__RX_DCOC_RES_I_908___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_908__RX_DCOC_RES_Q_908___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_908__RX_DCOC_RES_Q_908___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_908___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_908___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_909 (0x005FCE34) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_909___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_909___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_909__RX_DCOC_RANGE_909___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_909__RX_DCOC_RES_I_909___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_909__RX_DCOC_RES_Q_909___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_909__RX_DCOC_RANGE_909___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_909__RX_DCOC_RANGE_909___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_909__RX_DCOC_RES_I_909___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_909__RX_DCOC_RES_I_909___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_909__RX_DCOC_RES_Q_909___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_909__RX_DCOC_RES_Q_909___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_909___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_909___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_910 (0x005FCE38) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_910___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_910___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_910__RX_DCOC_RANGE_910___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_910__RX_DCOC_RES_I_910___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_910__RX_DCOC_RES_Q_910___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_910__RX_DCOC_RANGE_910___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_910__RX_DCOC_RANGE_910___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_910__RX_DCOC_RES_I_910___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_910__RX_DCOC_RES_I_910___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_910__RX_DCOC_RES_Q_910___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_910__RX_DCOC_RES_Q_910___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_910___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_910___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_911 (0x005FCE3C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_911___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_911___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_911__RX_DCOC_RANGE_911___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_911__RX_DCOC_RES_I_911___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_911__RX_DCOC_RES_Q_911___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_911__RX_DCOC_RANGE_911___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_911__RX_DCOC_RANGE_911___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_911__RX_DCOC_RES_I_911___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_911__RX_DCOC_RES_I_911___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_911__RX_DCOC_RES_Q_911___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_911__RX_DCOC_RES_Q_911___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_911___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_911___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_912 (0x005FCE40) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_912___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_912___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_912__RX_DCOC_RANGE_912___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_912__RX_DCOC_RES_I_912___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_912__RX_DCOC_RES_Q_912___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_912__RX_DCOC_RANGE_912___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_912__RX_DCOC_RANGE_912___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_912__RX_DCOC_RES_I_912___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_912__RX_DCOC_RES_I_912___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_912__RX_DCOC_RES_Q_912___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_912__RX_DCOC_RES_Q_912___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_912___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_912___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_913 (0x005FCE44) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_913___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_913___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_913__RX_DCOC_RANGE_913___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_913__RX_DCOC_RES_I_913___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_913__RX_DCOC_RES_Q_913___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_913__RX_DCOC_RANGE_913___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_913__RX_DCOC_RANGE_913___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_913__RX_DCOC_RES_I_913___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_913__RX_DCOC_RES_I_913___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_913__RX_DCOC_RES_Q_913___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_913__RX_DCOC_RES_Q_913___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_913___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_913___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_914 (0x005FCE48) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_914___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_914___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_914__RX_DCOC_RANGE_914___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_914__RX_DCOC_RES_I_914___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_914__RX_DCOC_RES_Q_914___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_914__RX_DCOC_RANGE_914___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_914__RX_DCOC_RANGE_914___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_914__RX_DCOC_RES_I_914___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_914__RX_DCOC_RES_I_914___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_914__RX_DCOC_RES_Q_914___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_914__RX_DCOC_RES_Q_914___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_914___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_914___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_915 (0x005FCE4C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_915___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_915___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_915__RX_DCOC_RANGE_915___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_915__RX_DCOC_RES_I_915___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_915__RX_DCOC_RES_Q_915___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_915__RX_DCOC_RANGE_915___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_915__RX_DCOC_RANGE_915___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_915__RX_DCOC_RES_I_915___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_915__RX_DCOC_RES_I_915___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_915__RX_DCOC_RES_Q_915___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_915__RX_DCOC_RES_Q_915___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_915___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_915___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_916 (0x005FCE50) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_916___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_916___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_916__RX_DCOC_RANGE_916___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_916__RX_DCOC_RES_I_916___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_916__RX_DCOC_RES_Q_916___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_916__RX_DCOC_RANGE_916___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_916__RX_DCOC_RANGE_916___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_916__RX_DCOC_RES_I_916___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_916__RX_DCOC_RES_I_916___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_916__RX_DCOC_RES_Q_916___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_916__RX_DCOC_RES_Q_916___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_916___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_916___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_917 (0x005FCE54) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_917___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_917___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_917__RX_DCOC_RANGE_917___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_917__RX_DCOC_RES_I_917___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_917__RX_DCOC_RES_Q_917___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_917__RX_DCOC_RANGE_917___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_917__RX_DCOC_RANGE_917___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_917__RX_DCOC_RES_I_917___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_917__RX_DCOC_RES_I_917___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_917__RX_DCOC_RES_Q_917___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_917__RX_DCOC_RES_Q_917___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_917___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_917___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_918 (0x005FCE58) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_918___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_918___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_918__RX_DCOC_RANGE_918___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_918__RX_DCOC_RES_I_918___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_918__RX_DCOC_RES_Q_918___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_918__RX_DCOC_RANGE_918___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_918__RX_DCOC_RANGE_918___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_918__RX_DCOC_RES_I_918___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_918__RX_DCOC_RES_I_918___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_918__RX_DCOC_RES_Q_918___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_918__RX_DCOC_RES_Q_918___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_918___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_918___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_919 (0x005FCE5C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_919___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_919___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_919__RX_DCOC_RANGE_919___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_919__RX_DCOC_RES_I_919___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_919__RX_DCOC_RES_Q_919___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_919__RX_DCOC_RANGE_919___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_919__RX_DCOC_RANGE_919___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_919__RX_DCOC_RES_I_919___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_919__RX_DCOC_RES_I_919___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_919__RX_DCOC_RES_Q_919___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_919__RX_DCOC_RES_Q_919___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_919___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_919___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_920 (0x005FCE60) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_920___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_920___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_920__RX_DCOC_RANGE_920___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_920__RX_DCOC_RES_I_920___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_920__RX_DCOC_RES_Q_920___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_920__RX_DCOC_RANGE_920___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_920__RX_DCOC_RANGE_920___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_920__RX_DCOC_RES_I_920___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_920__RX_DCOC_RES_I_920___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_920__RX_DCOC_RES_Q_920___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_920__RX_DCOC_RES_Q_920___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_920___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_920___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_921 (0x005FCE64) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_921___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_921___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_921__RX_DCOC_RANGE_921___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_921__RX_DCOC_RES_I_921___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_921__RX_DCOC_RES_Q_921___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_921__RX_DCOC_RANGE_921___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_921__RX_DCOC_RANGE_921___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_921__RX_DCOC_RES_I_921___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_921__RX_DCOC_RES_I_921___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_921__RX_DCOC_RES_Q_921___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_921__RX_DCOC_RES_Q_921___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_921___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_921___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_922 (0x005FCE68) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_922___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_922___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_922__RX_DCOC_RANGE_922___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_922__RX_DCOC_RES_I_922___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_922__RX_DCOC_RES_Q_922___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_922__RX_DCOC_RANGE_922___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_922__RX_DCOC_RANGE_922___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_922__RX_DCOC_RES_I_922___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_922__RX_DCOC_RES_I_922___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_922__RX_DCOC_RES_Q_922___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_922__RX_DCOC_RES_Q_922___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_922___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_922___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_923 (0x005FCE6C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_923___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_923___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_923__RX_DCOC_RANGE_923___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_923__RX_DCOC_RES_I_923___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_923__RX_DCOC_RES_Q_923___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_923__RX_DCOC_RANGE_923___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_923__RX_DCOC_RANGE_923___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_923__RX_DCOC_RES_I_923___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_923__RX_DCOC_RES_I_923___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_923__RX_DCOC_RES_Q_923___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_923__RX_DCOC_RES_Q_923___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_923___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_923___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_924 (0x005FCE70) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_924___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_924___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_924__RX_DCOC_RANGE_924___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_924__RX_DCOC_RES_I_924___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_924__RX_DCOC_RES_Q_924___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_924__RX_DCOC_RANGE_924___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_924__RX_DCOC_RANGE_924___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_924__RX_DCOC_RES_I_924___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_924__RX_DCOC_RES_I_924___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_924__RX_DCOC_RES_Q_924___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_924__RX_DCOC_RES_Q_924___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_924___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_924___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_925 (0x005FCE74) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_925___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_925___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_925__RX_DCOC_RANGE_925___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_925__RX_DCOC_RES_I_925___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_925__RX_DCOC_RES_Q_925___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_925__RX_DCOC_RANGE_925___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_925__RX_DCOC_RANGE_925___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_925__RX_DCOC_RES_I_925___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_925__RX_DCOC_RES_I_925___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_925__RX_DCOC_RES_Q_925___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_925__RX_DCOC_RES_Q_925___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_925___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_925___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_926 (0x005FCE78) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_926___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_926___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_926__RX_DCOC_RANGE_926___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_926__RX_DCOC_RES_I_926___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_926__RX_DCOC_RES_Q_926___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_926__RX_DCOC_RANGE_926___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_926__RX_DCOC_RANGE_926___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_926__RX_DCOC_RES_I_926___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_926__RX_DCOC_RES_I_926___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_926__RX_DCOC_RES_Q_926___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_926__RX_DCOC_RES_Q_926___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_926___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_926___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_927 (0x005FCE7C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_927___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_927___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_927__RX_DCOC_RANGE_927___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_927__RX_DCOC_RES_I_927___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_927__RX_DCOC_RES_Q_927___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_927__RX_DCOC_RANGE_927___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_927__RX_DCOC_RANGE_927___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_927__RX_DCOC_RES_I_927___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_927__RX_DCOC_RES_I_927___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_927__RX_DCOC_RES_Q_927___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_927__RX_DCOC_RES_Q_927___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_927___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_927___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_928 (0x005FCE80) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_928___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_928___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_928__RX_DCOC_RANGE_928___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_928__RX_DCOC_RES_I_928___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_928__RX_DCOC_RES_Q_928___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_928__RX_DCOC_RANGE_928___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_928__RX_DCOC_RANGE_928___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_928__RX_DCOC_RES_I_928___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_928__RX_DCOC_RES_I_928___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_928__RX_DCOC_RES_Q_928___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_928__RX_DCOC_RES_Q_928___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_928___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_928___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_929 (0x005FCE84) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_929___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_929___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_929__RX_DCOC_RANGE_929___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_929__RX_DCOC_RES_I_929___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_929__RX_DCOC_RES_Q_929___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_929__RX_DCOC_RANGE_929___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_929__RX_DCOC_RANGE_929___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_929__RX_DCOC_RES_I_929___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_929__RX_DCOC_RES_I_929___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_929__RX_DCOC_RES_Q_929___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_929__RX_DCOC_RES_Q_929___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_929___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_929___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_930 (0x005FCE88) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_930___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_930___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_930__RX_DCOC_RANGE_930___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_930__RX_DCOC_RES_I_930___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_930__RX_DCOC_RES_Q_930___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_930__RX_DCOC_RANGE_930___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_930__RX_DCOC_RANGE_930___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_930__RX_DCOC_RES_I_930___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_930__RX_DCOC_RES_I_930___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_930__RX_DCOC_RES_Q_930___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_930__RX_DCOC_RES_Q_930___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_930___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_930___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_931 (0x005FCE8C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_931___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_931___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_931__RX_DCOC_RANGE_931___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_931__RX_DCOC_RES_I_931___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_931__RX_DCOC_RES_Q_931___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_931__RX_DCOC_RANGE_931___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_931__RX_DCOC_RANGE_931___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_931__RX_DCOC_RES_I_931___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_931__RX_DCOC_RES_I_931___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_931__RX_DCOC_RES_Q_931___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_931__RX_DCOC_RES_Q_931___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_931___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_931___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_932 (0x005FCE90) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_932___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_932___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_932__RX_DCOC_RANGE_932___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_932__RX_DCOC_RES_I_932___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_932__RX_DCOC_RES_Q_932___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_932__RX_DCOC_RANGE_932___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_932__RX_DCOC_RANGE_932___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_932__RX_DCOC_RES_I_932___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_932__RX_DCOC_RES_I_932___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_932__RX_DCOC_RES_Q_932___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_932__RX_DCOC_RES_Q_932___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_932___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_932___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_933 (0x005FCE94) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_933___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_933___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_933__RX_DCOC_RANGE_933___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_933__RX_DCOC_RES_I_933___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_933__RX_DCOC_RES_Q_933___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_933__RX_DCOC_RANGE_933___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_933__RX_DCOC_RANGE_933___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_933__RX_DCOC_RES_I_933___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_933__RX_DCOC_RES_I_933___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_933__RX_DCOC_RES_Q_933___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_933__RX_DCOC_RES_Q_933___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_933___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_933___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_934 (0x005FCE98) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_934___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_934___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_934__RX_DCOC_RANGE_934___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_934__RX_DCOC_RES_I_934___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_934__RX_DCOC_RES_Q_934___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_934__RX_DCOC_RANGE_934___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_934__RX_DCOC_RANGE_934___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_934__RX_DCOC_RES_I_934___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_934__RX_DCOC_RES_I_934___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_934__RX_DCOC_RES_Q_934___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_934__RX_DCOC_RES_Q_934___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_934___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_934___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_935 (0x005FCE9C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_935___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_935___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_935__RX_DCOC_RANGE_935___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_935__RX_DCOC_RES_I_935___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_935__RX_DCOC_RES_Q_935___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_935__RX_DCOC_RANGE_935___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_935__RX_DCOC_RANGE_935___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_935__RX_DCOC_RES_I_935___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_935__RX_DCOC_RES_I_935___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_935__RX_DCOC_RES_Q_935___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_935__RX_DCOC_RES_Q_935___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_935___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_935___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_936 (0x005FCEA0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_936___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_936___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_936__RX_DCOC_RANGE_936___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_936__RX_DCOC_RES_I_936___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_936__RX_DCOC_RES_Q_936___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_936__RX_DCOC_RANGE_936___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_936__RX_DCOC_RANGE_936___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_936__RX_DCOC_RES_I_936___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_936__RX_DCOC_RES_I_936___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_936__RX_DCOC_RES_Q_936___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_936__RX_DCOC_RES_Q_936___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_936___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_936___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_937 (0x005FCEA4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_937___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_937___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_937__RX_DCOC_RANGE_937___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_937__RX_DCOC_RES_I_937___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_937__RX_DCOC_RES_Q_937___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_937__RX_DCOC_RANGE_937___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_937__RX_DCOC_RANGE_937___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_937__RX_DCOC_RES_I_937___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_937__RX_DCOC_RES_I_937___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_937__RX_DCOC_RES_Q_937___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_937__RX_DCOC_RES_Q_937___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_937___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_937___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_938 (0x005FCEA8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_938___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_938___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_938__RX_DCOC_RANGE_938___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_938__RX_DCOC_RES_I_938___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_938__RX_DCOC_RES_Q_938___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_938__RX_DCOC_RANGE_938___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_938__RX_DCOC_RANGE_938___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_938__RX_DCOC_RES_I_938___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_938__RX_DCOC_RES_I_938___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_938__RX_DCOC_RES_Q_938___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_938__RX_DCOC_RES_Q_938___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_938___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_938___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_939 (0x005FCEAC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_939___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_939___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_939__RX_DCOC_RANGE_939___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_939__RX_DCOC_RES_I_939___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_939__RX_DCOC_RES_Q_939___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_939__RX_DCOC_RANGE_939___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_939__RX_DCOC_RANGE_939___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_939__RX_DCOC_RES_I_939___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_939__RX_DCOC_RES_I_939___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_939__RX_DCOC_RES_Q_939___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_939__RX_DCOC_RES_Q_939___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_939___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_939___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_940 (0x005FCEB0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_940___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_940___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_940__RX_DCOC_RANGE_940___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_940__RX_DCOC_RES_I_940___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_940__RX_DCOC_RES_Q_940___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_940__RX_DCOC_RANGE_940___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_940__RX_DCOC_RANGE_940___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_940__RX_DCOC_RES_I_940___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_940__RX_DCOC_RES_I_940___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_940__RX_DCOC_RES_Q_940___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_940__RX_DCOC_RES_Q_940___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_940___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_940___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_941 (0x005FCEB4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_941___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_941___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_941__RX_DCOC_RANGE_941___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_941__RX_DCOC_RES_I_941___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_941__RX_DCOC_RES_Q_941___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_941__RX_DCOC_RANGE_941___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_941__RX_DCOC_RANGE_941___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_941__RX_DCOC_RES_I_941___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_941__RX_DCOC_RES_I_941___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_941__RX_DCOC_RES_Q_941___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_941__RX_DCOC_RES_Q_941___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_941___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_941___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_942 (0x005FCEB8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_942___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_942___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_942__RX_DCOC_RANGE_942___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_942__RX_DCOC_RES_I_942___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_942__RX_DCOC_RES_Q_942___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_942__RX_DCOC_RANGE_942___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_942__RX_DCOC_RANGE_942___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_942__RX_DCOC_RES_I_942___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_942__RX_DCOC_RES_I_942___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_942__RX_DCOC_RES_Q_942___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_942__RX_DCOC_RES_Q_942___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_942___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_942___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_943 (0x005FCEBC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_943___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_943___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_943__RX_DCOC_RANGE_943___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_943__RX_DCOC_RES_I_943___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_943__RX_DCOC_RES_Q_943___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_943__RX_DCOC_RANGE_943___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_943__RX_DCOC_RANGE_943___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_943__RX_DCOC_RES_I_943___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_943__RX_DCOC_RES_I_943___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_943__RX_DCOC_RES_Q_943___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_943__RX_DCOC_RES_Q_943___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_943___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_943___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_944 (0x005FCEC0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_944___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_944___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_944__RX_DCOC_RANGE_944___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_944__RX_DCOC_RES_I_944___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_944__RX_DCOC_RES_Q_944___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_944__RX_DCOC_RANGE_944___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_944__RX_DCOC_RANGE_944___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_944__RX_DCOC_RES_I_944___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_944__RX_DCOC_RES_I_944___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_944__RX_DCOC_RES_Q_944___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_944__RX_DCOC_RES_Q_944___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_944___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_944___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_945 (0x005FCEC4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_945___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_945___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_945__RX_DCOC_RANGE_945___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_945__RX_DCOC_RES_I_945___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_945__RX_DCOC_RES_Q_945___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_945__RX_DCOC_RANGE_945___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_945__RX_DCOC_RANGE_945___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_945__RX_DCOC_RES_I_945___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_945__RX_DCOC_RES_I_945___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_945__RX_DCOC_RES_Q_945___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_945__RX_DCOC_RES_Q_945___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_945___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_945___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_946 (0x005FCEC8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_946___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_946___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_946__RX_DCOC_RANGE_946___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_946__RX_DCOC_RES_I_946___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_946__RX_DCOC_RES_Q_946___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_946__RX_DCOC_RANGE_946___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_946__RX_DCOC_RANGE_946___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_946__RX_DCOC_RES_I_946___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_946__RX_DCOC_RES_I_946___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_946__RX_DCOC_RES_Q_946___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_946__RX_DCOC_RES_Q_946___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_946___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_946___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_947 (0x005FCECC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_947___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_947___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_947__RX_DCOC_RANGE_947___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_947__RX_DCOC_RES_I_947___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_947__RX_DCOC_RES_Q_947___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_947__RX_DCOC_RANGE_947___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_947__RX_DCOC_RANGE_947___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_947__RX_DCOC_RES_I_947___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_947__RX_DCOC_RES_I_947___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_947__RX_DCOC_RES_Q_947___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_947__RX_DCOC_RES_Q_947___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_947___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_947___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_948 (0x005FCED0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_948___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_948___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_948__RX_DCOC_RANGE_948___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_948__RX_DCOC_RES_I_948___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_948__RX_DCOC_RES_Q_948___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_948__RX_DCOC_RANGE_948___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_948__RX_DCOC_RANGE_948___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_948__RX_DCOC_RES_I_948___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_948__RX_DCOC_RES_I_948___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_948__RX_DCOC_RES_Q_948___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_948__RX_DCOC_RES_Q_948___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_948___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_948___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_949 (0x005FCED4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_949___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_949___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_949__RX_DCOC_RANGE_949___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_949__RX_DCOC_RES_I_949___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_949__RX_DCOC_RES_Q_949___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_949__RX_DCOC_RANGE_949___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_949__RX_DCOC_RANGE_949___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_949__RX_DCOC_RES_I_949___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_949__RX_DCOC_RES_I_949___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_949__RX_DCOC_RES_Q_949___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_949__RX_DCOC_RES_Q_949___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_949___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_949___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_950 (0x005FCED8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_950___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_950___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_950__RX_DCOC_RANGE_950___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_950__RX_DCOC_RES_I_950___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_950__RX_DCOC_RES_Q_950___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_950__RX_DCOC_RANGE_950___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_950__RX_DCOC_RANGE_950___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_950__RX_DCOC_RES_I_950___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_950__RX_DCOC_RES_I_950___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_950__RX_DCOC_RES_Q_950___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_950__RX_DCOC_RES_Q_950___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_950___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_950___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_951 (0x005FCEDC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_951___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_951___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_951__RX_DCOC_RANGE_951___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_951__RX_DCOC_RES_I_951___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_951__RX_DCOC_RES_Q_951___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_951__RX_DCOC_RANGE_951___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_951__RX_DCOC_RANGE_951___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_951__RX_DCOC_RES_I_951___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_951__RX_DCOC_RES_I_951___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_951__RX_DCOC_RES_Q_951___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_951__RX_DCOC_RES_Q_951___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_951___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_951___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_952 (0x005FCEE0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_952___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_952___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_952__RX_DCOC_RANGE_952___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_952__RX_DCOC_RES_I_952___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_952__RX_DCOC_RES_Q_952___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_952__RX_DCOC_RANGE_952___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_952__RX_DCOC_RANGE_952___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_952__RX_DCOC_RES_I_952___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_952__RX_DCOC_RES_I_952___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_952__RX_DCOC_RES_Q_952___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_952__RX_DCOC_RES_Q_952___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_952___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_952___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_953 (0x005FCEE4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_953___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_953___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_953__RX_DCOC_RANGE_953___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_953__RX_DCOC_RES_I_953___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_953__RX_DCOC_RES_Q_953___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_953__RX_DCOC_RANGE_953___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_953__RX_DCOC_RANGE_953___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_953__RX_DCOC_RES_I_953___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_953__RX_DCOC_RES_I_953___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_953__RX_DCOC_RES_Q_953___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_953__RX_DCOC_RES_Q_953___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_953___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_953___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_954 (0x005FCEE8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_954___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_954___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_954__RX_DCOC_RANGE_954___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_954__RX_DCOC_RES_I_954___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_954__RX_DCOC_RES_Q_954___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_954__RX_DCOC_RANGE_954___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_954__RX_DCOC_RANGE_954___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_954__RX_DCOC_RES_I_954___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_954__RX_DCOC_RES_I_954___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_954__RX_DCOC_RES_Q_954___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_954__RX_DCOC_RES_Q_954___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_954___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_954___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_955 (0x005FCEEC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_955___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_955___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_955__RX_DCOC_RANGE_955___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_955__RX_DCOC_RES_I_955___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_955__RX_DCOC_RES_Q_955___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_955__RX_DCOC_RANGE_955___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_955__RX_DCOC_RANGE_955___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_955__RX_DCOC_RES_I_955___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_955__RX_DCOC_RES_I_955___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_955__RX_DCOC_RES_Q_955___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_955__RX_DCOC_RES_Q_955___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_955___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_955___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_956 (0x005FCEF0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_956___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_956___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_956__RX_DCOC_RANGE_956___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_956__RX_DCOC_RES_I_956___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_956__RX_DCOC_RES_Q_956___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_956__RX_DCOC_RANGE_956___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_956__RX_DCOC_RANGE_956___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_956__RX_DCOC_RES_I_956___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_956__RX_DCOC_RES_I_956___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_956__RX_DCOC_RES_Q_956___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_956__RX_DCOC_RES_Q_956___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_956___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_956___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_957 (0x005FCEF4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_957___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_957___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_957__RX_DCOC_RANGE_957___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_957__RX_DCOC_RES_I_957___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_957__RX_DCOC_RES_Q_957___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_957__RX_DCOC_RANGE_957___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_957__RX_DCOC_RANGE_957___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_957__RX_DCOC_RES_I_957___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_957__RX_DCOC_RES_I_957___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_957__RX_DCOC_RES_Q_957___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_957__RX_DCOC_RES_Q_957___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_957___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_957___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_958 (0x005FCEF8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_958___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_958___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_958__RX_DCOC_RANGE_958___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_958__RX_DCOC_RES_I_958___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_958__RX_DCOC_RES_Q_958___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_958__RX_DCOC_RANGE_958___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_958__RX_DCOC_RANGE_958___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_958__RX_DCOC_RES_I_958___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_958__RX_DCOC_RES_I_958___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_958__RX_DCOC_RES_Q_958___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_958__RX_DCOC_RES_Q_958___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_958___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_958___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_959 (0x005FCEFC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_959___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_959___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_959__RX_DCOC_RANGE_959___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_959__RX_DCOC_RES_I_959___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_959__RX_DCOC_RES_Q_959___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_959__RX_DCOC_RANGE_959___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_959__RX_DCOC_RANGE_959___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_959__RX_DCOC_RES_I_959___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_959__RX_DCOC_RES_I_959___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_959__RX_DCOC_RES_Q_959___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_959__RX_DCOC_RES_Q_959___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_959___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_959___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_960 (0x005FCF00) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_960___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_960___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_960__RX_DCOC_RANGE_960___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_960__RX_DCOC_RES_I_960___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_960__RX_DCOC_RES_Q_960___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_960__RX_DCOC_RANGE_960___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_960__RX_DCOC_RANGE_960___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_960__RX_DCOC_RES_I_960___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_960__RX_DCOC_RES_I_960___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_960__RX_DCOC_RES_Q_960___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_960__RX_DCOC_RES_Q_960___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_960___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_960___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_961 (0x005FCF04) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_961___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_961___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_961__RX_DCOC_RANGE_961___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_961__RX_DCOC_RES_I_961___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_961__RX_DCOC_RES_Q_961___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_961__RX_DCOC_RANGE_961___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_961__RX_DCOC_RANGE_961___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_961__RX_DCOC_RES_I_961___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_961__RX_DCOC_RES_I_961___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_961__RX_DCOC_RES_Q_961___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_961__RX_DCOC_RES_Q_961___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_961___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_961___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_962 (0x005FCF08) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_962___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_962___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_962__RX_DCOC_RANGE_962___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_962__RX_DCOC_RES_I_962___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_962__RX_DCOC_RES_Q_962___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_962__RX_DCOC_RANGE_962___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_962__RX_DCOC_RANGE_962___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_962__RX_DCOC_RES_I_962___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_962__RX_DCOC_RES_I_962___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_962__RX_DCOC_RES_Q_962___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_962__RX_DCOC_RES_Q_962___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_962___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_962___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_963 (0x005FCF0C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_963___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_963___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_963__RX_DCOC_RANGE_963___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_963__RX_DCOC_RES_I_963___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_963__RX_DCOC_RES_Q_963___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_963__RX_DCOC_RANGE_963___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_963__RX_DCOC_RANGE_963___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_963__RX_DCOC_RES_I_963___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_963__RX_DCOC_RES_I_963___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_963__RX_DCOC_RES_Q_963___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_963__RX_DCOC_RES_Q_963___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_963___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_963___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_964 (0x005FCF10) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_964___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_964___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_964__RX_DCOC_RANGE_964___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_964__RX_DCOC_RES_I_964___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_964__RX_DCOC_RES_Q_964___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_964__RX_DCOC_RANGE_964___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_964__RX_DCOC_RANGE_964___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_964__RX_DCOC_RES_I_964___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_964__RX_DCOC_RES_I_964___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_964__RX_DCOC_RES_Q_964___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_964__RX_DCOC_RES_Q_964___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_964___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_964___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_965 (0x005FCF14) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_965___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_965___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_965__RX_DCOC_RANGE_965___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_965__RX_DCOC_RES_I_965___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_965__RX_DCOC_RES_Q_965___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_965__RX_DCOC_RANGE_965___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_965__RX_DCOC_RANGE_965___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_965__RX_DCOC_RES_I_965___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_965__RX_DCOC_RES_I_965___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_965__RX_DCOC_RES_Q_965___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_965__RX_DCOC_RES_Q_965___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_965___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_965___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_966 (0x005FCF18) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_966___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_966___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_966__RX_DCOC_RANGE_966___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_966__RX_DCOC_RES_I_966___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_966__RX_DCOC_RES_Q_966___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_966__RX_DCOC_RANGE_966___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_966__RX_DCOC_RANGE_966___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_966__RX_DCOC_RES_I_966___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_966__RX_DCOC_RES_I_966___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_966__RX_DCOC_RES_Q_966___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_966__RX_DCOC_RES_Q_966___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_966___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_966___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_967 (0x005FCF1C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_967___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_967___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_967__RX_DCOC_RANGE_967___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_967__RX_DCOC_RES_I_967___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_967__RX_DCOC_RES_Q_967___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_967__RX_DCOC_RANGE_967___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_967__RX_DCOC_RANGE_967___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_967__RX_DCOC_RES_I_967___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_967__RX_DCOC_RES_I_967___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_967__RX_DCOC_RES_Q_967___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_967__RX_DCOC_RES_Q_967___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_967___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_967___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_968 (0x005FCF20) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_968___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_968___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_968__RX_DCOC_RANGE_968___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_968__RX_DCOC_RES_I_968___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_968__RX_DCOC_RES_Q_968___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_968__RX_DCOC_RANGE_968___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_968__RX_DCOC_RANGE_968___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_968__RX_DCOC_RES_I_968___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_968__RX_DCOC_RES_I_968___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_968__RX_DCOC_RES_Q_968___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_968__RX_DCOC_RES_Q_968___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_968___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_968___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_969 (0x005FCF24) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_969___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_969___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_969__RX_DCOC_RANGE_969___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_969__RX_DCOC_RES_I_969___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_969__RX_DCOC_RES_Q_969___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_969__RX_DCOC_RANGE_969___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_969__RX_DCOC_RANGE_969___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_969__RX_DCOC_RES_I_969___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_969__RX_DCOC_RES_I_969___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_969__RX_DCOC_RES_Q_969___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_969__RX_DCOC_RES_Q_969___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_969___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_969___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_970 (0x005FCF28) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_970___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_970___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_970__RX_DCOC_RANGE_970___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_970__RX_DCOC_RES_I_970___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_970__RX_DCOC_RES_Q_970___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_970__RX_DCOC_RANGE_970___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_970__RX_DCOC_RANGE_970___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_970__RX_DCOC_RES_I_970___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_970__RX_DCOC_RES_I_970___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_970__RX_DCOC_RES_Q_970___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_970__RX_DCOC_RES_Q_970___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_970___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_970___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_971 (0x005FCF2C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_971___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_971___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_971__RX_DCOC_RANGE_971___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_971__RX_DCOC_RES_I_971___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_971__RX_DCOC_RES_Q_971___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_971__RX_DCOC_RANGE_971___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_971__RX_DCOC_RANGE_971___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_971__RX_DCOC_RES_I_971___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_971__RX_DCOC_RES_I_971___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_971__RX_DCOC_RES_Q_971___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_971__RX_DCOC_RES_Q_971___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_971___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_971___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_972 (0x005FCF30) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_972___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_972___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_972__RX_DCOC_RANGE_972___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_972__RX_DCOC_RES_I_972___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_972__RX_DCOC_RES_Q_972___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_972__RX_DCOC_RANGE_972___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_972__RX_DCOC_RANGE_972___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_972__RX_DCOC_RES_I_972___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_972__RX_DCOC_RES_I_972___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_972__RX_DCOC_RES_Q_972___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_972__RX_DCOC_RES_Q_972___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_972___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_972___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_973 (0x005FCF34) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_973___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_973___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_973__RX_DCOC_RANGE_973___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_973__RX_DCOC_RES_I_973___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_973__RX_DCOC_RES_Q_973___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_973__RX_DCOC_RANGE_973___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_973__RX_DCOC_RANGE_973___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_973__RX_DCOC_RES_I_973___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_973__RX_DCOC_RES_I_973___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_973__RX_DCOC_RES_Q_973___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_973__RX_DCOC_RES_Q_973___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_973___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_973___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_974 (0x005FCF38) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_974___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_974___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_974__RX_DCOC_RANGE_974___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_974__RX_DCOC_RES_I_974___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_974__RX_DCOC_RES_Q_974___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_974__RX_DCOC_RANGE_974___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_974__RX_DCOC_RANGE_974___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_974__RX_DCOC_RES_I_974___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_974__RX_DCOC_RES_I_974___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_974__RX_DCOC_RES_Q_974___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_974__RX_DCOC_RES_Q_974___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_974___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_974___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_975 (0x005FCF3C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_975___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_975___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_975__RX_DCOC_RANGE_975___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_975__RX_DCOC_RES_I_975___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_975__RX_DCOC_RES_Q_975___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_975__RX_DCOC_RANGE_975___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_975__RX_DCOC_RANGE_975___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_975__RX_DCOC_RES_I_975___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_975__RX_DCOC_RES_I_975___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_975__RX_DCOC_RES_Q_975___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_975__RX_DCOC_RES_Q_975___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_975___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_975___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_976 (0x005FCF40) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_976___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_976___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_976__RX_DCOC_RANGE_976___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_976__RX_DCOC_RES_I_976___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_976__RX_DCOC_RES_Q_976___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_976__RX_DCOC_RANGE_976___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_976__RX_DCOC_RANGE_976___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_976__RX_DCOC_RES_I_976___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_976__RX_DCOC_RES_I_976___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_976__RX_DCOC_RES_Q_976___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_976__RX_DCOC_RES_Q_976___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_976___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_976___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_977 (0x005FCF44) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_977___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_977___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_977__RX_DCOC_RANGE_977___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_977__RX_DCOC_RES_I_977___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_977__RX_DCOC_RES_Q_977___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_977__RX_DCOC_RANGE_977___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_977__RX_DCOC_RANGE_977___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_977__RX_DCOC_RES_I_977___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_977__RX_DCOC_RES_I_977___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_977__RX_DCOC_RES_Q_977___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_977__RX_DCOC_RES_Q_977___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_977___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_977___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_978 (0x005FCF48) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_978___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_978___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_978__RX_DCOC_RANGE_978___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_978__RX_DCOC_RES_I_978___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_978__RX_DCOC_RES_Q_978___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_978__RX_DCOC_RANGE_978___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_978__RX_DCOC_RANGE_978___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_978__RX_DCOC_RES_I_978___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_978__RX_DCOC_RES_I_978___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_978__RX_DCOC_RES_Q_978___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_978__RX_DCOC_RES_Q_978___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_978___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_978___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_979 (0x005FCF4C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_979___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_979___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_979__RX_DCOC_RANGE_979___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_979__RX_DCOC_RES_I_979___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_979__RX_DCOC_RES_Q_979___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_979__RX_DCOC_RANGE_979___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_979__RX_DCOC_RANGE_979___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_979__RX_DCOC_RES_I_979___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_979__RX_DCOC_RES_I_979___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_979__RX_DCOC_RES_Q_979___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_979__RX_DCOC_RES_Q_979___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_979___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_979___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_980 (0x005FCF50) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_980___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_980___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_980__RX_DCOC_RANGE_980___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_980__RX_DCOC_RES_I_980___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_980__RX_DCOC_RES_Q_980___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_980__RX_DCOC_RANGE_980___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_980__RX_DCOC_RANGE_980___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_980__RX_DCOC_RES_I_980___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_980__RX_DCOC_RES_I_980___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_980__RX_DCOC_RES_Q_980___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_980__RX_DCOC_RES_Q_980___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_980___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_980___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_981 (0x005FCF54) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_981___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_981___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_981__RX_DCOC_RANGE_981___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_981__RX_DCOC_RES_I_981___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_981__RX_DCOC_RES_Q_981___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_981__RX_DCOC_RANGE_981___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_981__RX_DCOC_RANGE_981___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_981__RX_DCOC_RES_I_981___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_981__RX_DCOC_RES_I_981___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_981__RX_DCOC_RES_Q_981___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_981__RX_DCOC_RES_Q_981___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_981___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_981___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_982 (0x005FCF58) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_982___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_982___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_982__RX_DCOC_RANGE_982___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_982__RX_DCOC_RES_I_982___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_982__RX_DCOC_RES_Q_982___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_982__RX_DCOC_RANGE_982___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_982__RX_DCOC_RANGE_982___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_982__RX_DCOC_RES_I_982___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_982__RX_DCOC_RES_I_982___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_982__RX_DCOC_RES_Q_982___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_982__RX_DCOC_RES_Q_982___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_982___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_982___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_983 (0x005FCF5C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_983___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_983___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_983__RX_DCOC_RANGE_983___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_983__RX_DCOC_RES_I_983___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_983__RX_DCOC_RES_Q_983___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_983__RX_DCOC_RANGE_983___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_983__RX_DCOC_RANGE_983___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_983__RX_DCOC_RES_I_983___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_983__RX_DCOC_RES_I_983___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_983__RX_DCOC_RES_Q_983___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_983__RX_DCOC_RES_Q_983___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_983___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_983___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_984 (0x005FCF60) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_984___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_984___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_984__RX_DCOC_RANGE_984___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_984__RX_DCOC_RES_I_984___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_984__RX_DCOC_RES_Q_984___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_984__RX_DCOC_RANGE_984___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_984__RX_DCOC_RANGE_984___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_984__RX_DCOC_RES_I_984___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_984__RX_DCOC_RES_I_984___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_984__RX_DCOC_RES_Q_984___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_984__RX_DCOC_RES_Q_984___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_984___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_984___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_985 (0x005FCF64) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_985___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_985___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_985__RX_DCOC_RANGE_985___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_985__RX_DCOC_RES_I_985___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_985__RX_DCOC_RES_Q_985___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_985__RX_DCOC_RANGE_985___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_985__RX_DCOC_RANGE_985___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_985__RX_DCOC_RES_I_985___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_985__RX_DCOC_RES_I_985___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_985__RX_DCOC_RES_Q_985___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_985__RX_DCOC_RES_Q_985___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_985___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_985___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_986 (0x005FCF68) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_986___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_986___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_986__RX_DCOC_RANGE_986___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_986__RX_DCOC_RES_I_986___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_986__RX_DCOC_RES_Q_986___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_986__RX_DCOC_RANGE_986___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_986__RX_DCOC_RANGE_986___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_986__RX_DCOC_RES_I_986___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_986__RX_DCOC_RES_I_986___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_986__RX_DCOC_RES_Q_986___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_986__RX_DCOC_RES_Q_986___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_986___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_986___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_987 (0x005FCF6C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_987___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_987___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_987__RX_DCOC_RANGE_987___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_987__RX_DCOC_RES_I_987___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_987__RX_DCOC_RES_Q_987___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_987__RX_DCOC_RANGE_987___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_987__RX_DCOC_RANGE_987___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_987__RX_DCOC_RES_I_987___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_987__RX_DCOC_RES_I_987___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_987__RX_DCOC_RES_Q_987___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_987__RX_DCOC_RES_Q_987___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_987___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_987___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_988 (0x005FCF70) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_988___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_988___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_988__RX_DCOC_RANGE_988___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_988__RX_DCOC_RES_I_988___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_988__RX_DCOC_RES_Q_988___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_988__RX_DCOC_RANGE_988___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_988__RX_DCOC_RANGE_988___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_988__RX_DCOC_RES_I_988___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_988__RX_DCOC_RES_I_988___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_988__RX_DCOC_RES_Q_988___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_988__RX_DCOC_RES_Q_988___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_988___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_988___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_989 (0x005FCF74) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_989___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_989___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_989__RX_DCOC_RANGE_989___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_989__RX_DCOC_RES_I_989___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_989__RX_DCOC_RES_Q_989___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_989__RX_DCOC_RANGE_989___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_989__RX_DCOC_RANGE_989___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_989__RX_DCOC_RES_I_989___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_989__RX_DCOC_RES_I_989___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_989__RX_DCOC_RES_Q_989___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_989__RX_DCOC_RES_Q_989___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_989___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_989___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_990 (0x005FCF78) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_990___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_990___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_990__RX_DCOC_RANGE_990___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_990__RX_DCOC_RES_I_990___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_990__RX_DCOC_RES_Q_990___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_990__RX_DCOC_RANGE_990___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_990__RX_DCOC_RANGE_990___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_990__RX_DCOC_RES_I_990___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_990__RX_DCOC_RES_I_990___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_990__RX_DCOC_RES_Q_990___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_990__RX_DCOC_RES_Q_990___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_990___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_990___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_991 (0x005FCF7C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_991___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_991___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_991__RX_DCOC_RANGE_991___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_991__RX_DCOC_RES_I_991___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_991__RX_DCOC_RES_Q_991___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_991__RX_DCOC_RANGE_991___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_991__RX_DCOC_RANGE_991___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_991__RX_DCOC_RES_I_991___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_991__RX_DCOC_RES_I_991___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_991__RX_DCOC_RES_Q_991___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_991__RX_DCOC_RES_Q_991___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_991___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_991___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_992 (0x005FCF80) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_992___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_992___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_992__RX_DCOC_RANGE_992___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_992__RX_DCOC_RES_I_992___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_992__RX_DCOC_RES_Q_992___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_992__RX_DCOC_RANGE_992___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_992__RX_DCOC_RANGE_992___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_992__RX_DCOC_RES_I_992___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_992__RX_DCOC_RES_I_992___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_992__RX_DCOC_RES_Q_992___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_992__RX_DCOC_RES_Q_992___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_992___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_992___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_993 (0x005FCF84) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_993___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_993___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_993__RX_DCOC_RANGE_993___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_993__RX_DCOC_RES_I_993___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_993__RX_DCOC_RES_Q_993___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_993__RX_DCOC_RANGE_993___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_993__RX_DCOC_RANGE_993___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_993__RX_DCOC_RES_I_993___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_993__RX_DCOC_RES_I_993___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_993__RX_DCOC_RES_Q_993___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_993__RX_DCOC_RES_Q_993___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_993___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_993___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_994 (0x005FCF88) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_994___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_994___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_994__RX_DCOC_RANGE_994___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_994__RX_DCOC_RES_I_994___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_994__RX_DCOC_RES_Q_994___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_994__RX_DCOC_RANGE_994___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_994__RX_DCOC_RANGE_994___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_994__RX_DCOC_RES_I_994___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_994__RX_DCOC_RES_I_994___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_994__RX_DCOC_RES_Q_994___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_994__RX_DCOC_RES_Q_994___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_994___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_994___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_995 (0x005FCF8C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_995___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_995___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_995__RX_DCOC_RANGE_995___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_995__RX_DCOC_RES_I_995___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_995__RX_DCOC_RES_Q_995___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_995__RX_DCOC_RANGE_995___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_995__RX_DCOC_RANGE_995___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_995__RX_DCOC_RES_I_995___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_995__RX_DCOC_RES_I_995___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_995__RX_DCOC_RES_Q_995___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_995__RX_DCOC_RES_Q_995___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_995___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_995___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_996 (0x005FCF90) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_996___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_996___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_996__RX_DCOC_RANGE_996___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_996__RX_DCOC_RES_I_996___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_996__RX_DCOC_RES_Q_996___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_996__RX_DCOC_RANGE_996___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_996__RX_DCOC_RANGE_996___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_996__RX_DCOC_RES_I_996___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_996__RX_DCOC_RES_I_996___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_996__RX_DCOC_RES_Q_996___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_996__RX_DCOC_RES_Q_996___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_996___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_996___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_997 (0x005FCF94) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_997___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_997___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_997__RX_DCOC_RANGE_997___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_997__RX_DCOC_RES_I_997___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_997__RX_DCOC_RES_Q_997___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_997__RX_DCOC_RANGE_997___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_997__RX_DCOC_RANGE_997___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_997__RX_DCOC_RES_I_997___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_997__RX_DCOC_RES_I_997___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_997__RX_DCOC_RES_Q_997___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_997__RX_DCOC_RES_Q_997___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_997___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_997___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_998 (0x005FCF98) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_998___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_998___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_998__RX_DCOC_RANGE_998___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_998__RX_DCOC_RES_I_998___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_998__RX_DCOC_RES_Q_998___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_998__RX_DCOC_RANGE_998___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_998__RX_DCOC_RANGE_998___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_998__RX_DCOC_RES_I_998___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_998__RX_DCOC_RES_I_998___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_998__RX_DCOC_RES_Q_998___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_998__RX_DCOC_RES_Q_998___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_998___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_998___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_999 (0x005FCF9C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_999___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_999___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_999__RX_DCOC_RANGE_999___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_999__RX_DCOC_RES_I_999___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_999__RX_DCOC_RES_Q_999___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_999__RX_DCOC_RANGE_999___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_999__RX_DCOC_RANGE_999___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_999__RX_DCOC_RES_I_999___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_999__RX_DCOC_RES_I_999___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_999__RX_DCOC_RES_Q_999___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_999__RX_DCOC_RES_Q_999___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_999___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_999___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1000 (0x005FCFA0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1000___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1000___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1000__RX_DCOC_RANGE_1000___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1000__RX_DCOC_RES_I_1000___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1000__RX_DCOC_RES_Q_1000___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1000__RX_DCOC_RANGE_1000___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1000__RX_DCOC_RANGE_1000___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1000__RX_DCOC_RES_I_1000___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1000__RX_DCOC_RES_I_1000___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1000__RX_DCOC_RES_Q_1000___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1000__RX_DCOC_RES_Q_1000___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1000___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1000___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1001 (0x005FCFA4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1001___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1001___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1001__RX_DCOC_RANGE_1001___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1001__RX_DCOC_RES_I_1001___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1001__RX_DCOC_RES_Q_1001___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1001__RX_DCOC_RANGE_1001___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1001__RX_DCOC_RANGE_1001___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1001__RX_DCOC_RES_I_1001___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1001__RX_DCOC_RES_I_1001___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1001__RX_DCOC_RES_Q_1001___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1001__RX_DCOC_RES_Q_1001___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1001___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1001___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1002 (0x005FCFA8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1002___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1002___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1002__RX_DCOC_RANGE_1002___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1002__RX_DCOC_RES_I_1002___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1002__RX_DCOC_RES_Q_1002___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1002__RX_DCOC_RANGE_1002___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1002__RX_DCOC_RANGE_1002___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1002__RX_DCOC_RES_I_1002___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1002__RX_DCOC_RES_I_1002___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1002__RX_DCOC_RES_Q_1002___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1002__RX_DCOC_RES_Q_1002___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1002___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1002___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1003 (0x005FCFAC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1003___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1003___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1003__RX_DCOC_RANGE_1003___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1003__RX_DCOC_RES_I_1003___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1003__RX_DCOC_RES_Q_1003___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1003__RX_DCOC_RANGE_1003___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1003__RX_DCOC_RANGE_1003___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1003__RX_DCOC_RES_I_1003___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1003__RX_DCOC_RES_I_1003___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1003__RX_DCOC_RES_Q_1003___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1003__RX_DCOC_RES_Q_1003___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1003___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1003___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1004 (0x005FCFB0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1004___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1004___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1004__RX_DCOC_RANGE_1004___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1004__RX_DCOC_RES_I_1004___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1004__RX_DCOC_RES_Q_1004___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1004__RX_DCOC_RANGE_1004___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1004__RX_DCOC_RANGE_1004___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1004__RX_DCOC_RES_I_1004___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1004__RX_DCOC_RES_I_1004___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1004__RX_DCOC_RES_Q_1004___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1004__RX_DCOC_RES_Q_1004___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1004___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1004___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1005 (0x005FCFB4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1005___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1005___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1005__RX_DCOC_RANGE_1005___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1005__RX_DCOC_RES_I_1005___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1005__RX_DCOC_RES_Q_1005___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1005__RX_DCOC_RANGE_1005___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1005__RX_DCOC_RANGE_1005___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1005__RX_DCOC_RES_I_1005___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1005__RX_DCOC_RES_I_1005___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1005__RX_DCOC_RES_Q_1005___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1005__RX_DCOC_RES_Q_1005___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1005___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1005___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1006 (0x005FCFB8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1006___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1006___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1006__RX_DCOC_RANGE_1006___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1006__RX_DCOC_RES_I_1006___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1006__RX_DCOC_RES_Q_1006___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1006__RX_DCOC_RANGE_1006___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1006__RX_DCOC_RANGE_1006___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1006__RX_DCOC_RES_I_1006___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1006__RX_DCOC_RES_I_1006___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1006__RX_DCOC_RES_Q_1006___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1006__RX_DCOC_RES_Q_1006___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1006___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1006___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1007 (0x005FCFBC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1007___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1007___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1007__RX_DCOC_RANGE_1007___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1007__RX_DCOC_RES_I_1007___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1007__RX_DCOC_RES_Q_1007___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1007__RX_DCOC_RANGE_1007___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1007__RX_DCOC_RANGE_1007___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1007__RX_DCOC_RES_I_1007___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1007__RX_DCOC_RES_I_1007___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1007__RX_DCOC_RES_Q_1007___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1007__RX_DCOC_RES_Q_1007___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1007___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1007___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1008 (0x005FCFC0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1008___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1008___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1008__RX_DCOC_RANGE_1008___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1008__RX_DCOC_RES_I_1008___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1008__RX_DCOC_RES_Q_1008___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1008__RX_DCOC_RANGE_1008___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1008__RX_DCOC_RANGE_1008___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1008__RX_DCOC_RES_I_1008___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1008__RX_DCOC_RES_I_1008___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1008__RX_DCOC_RES_Q_1008___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1008__RX_DCOC_RES_Q_1008___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1008___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1008___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1009 (0x005FCFC4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1009___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1009___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1009__RX_DCOC_RANGE_1009___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1009__RX_DCOC_RES_I_1009___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1009__RX_DCOC_RES_Q_1009___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1009__RX_DCOC_RANGE_1009___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1009__RX_DCOC_RANGE_1009___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1009__RX_DCOC_RES_I_1009___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1009__RX_DCOC_RES_I_1009___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1009__RX_DCOC_RES_Q_1009___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1009__RX_DCOC_RES_Q_1009___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1009___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1009___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1010 (0x005FCFC8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1010___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1010___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1010__RX_DCOC_RANGE_1010___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1010__RX_DCOC_RES_I_1010___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1010__RX_DCOC_RES_Q_1010___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1010__RX_DCOC_RANGE_1010___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1010__RX_DCOC_RANGE_1010___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1010__RX_DCOC_RES_I_1010___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1010__RX_DCOC_RES_I_1010___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1010__RX_DCOC_RES_Q_1010___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1010__RX_DCOC_RES_Q_1010___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1010___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1010___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1011 (0x005FCFCC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1011___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1011___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1011__RX_DCOC_RANGE_1011___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1011__RX_DCOC_RES_I_1011___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1011__RX_DCOC_RES_Q_1011___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1011__RX_DCOC_RANGE_1011___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1011__RX_DCOC_RANGE_1011___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1011__RX_DCOC_RES_I_1011___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1011__RX_DCOC_RES_I_1011___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1011__RX_DCOC_RES_Q_1011___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1011__RX_DCOC_RES_Q_1011___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1011___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1011___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1012 (0x005FCFD0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1012___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1012___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1012__RX_DCOC_RANGE_1012___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1012__RX_DCOC_RES_I_1012___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1012__RX_DCOC_RES_Q_1012___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1012__RX_DCOC_RANGE_1012___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1012__RX_DCOC_RANGE_1012___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1012__RX_DCOC_RES_I_1012___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1012__RX_DCOC_RES_I_1012___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1012__RX_DCOC_RES_Q_1012___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1012__RX_DCOC_RES_Q_1012___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1012___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1012___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1013 (0x005FCFD4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1013___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1013___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1013__RX_DCOC_RANGE_1013___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1013__RX_DCOC_RES_I_1013___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1013__RX_DCOC_RES_Q_1013___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1013__RX_DCOC_RANGE_1013___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1013__RX_DCOC_RANGE_1013___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1013__RX_DCOC_RES_I_1013___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1013__RX_DCOC_RES_I_1013___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1013__RX_DCOC_RES_Q_1013___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1013__RX_DCOC_RES_Q_1013___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1013___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1013___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1014 (0x005FCFD8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1014___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1014___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1014__RX_DCOC_RANGE_1014___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1014__RX_DCOC_RES_I_1014___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1014__RX_DCOC_RES_Q_1014___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1014__RX_DCOC_RANGE_1014___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1014__RX_DCOC_RANGE_1014___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1014__RX_DCOC_RES_I_1014___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1014__RX_DCOC_RES_I_1014___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1014__RX_DCOC_RES_Q_1014___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1014__RX_DCOC_RES_Q_1014___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1014___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1014___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1015 (0x005FCFDC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1015___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1015___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1015__RX_DCOC_RANGE_1015___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1015__RX_DCOC_RES_I_1015___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1015__RX_DCOC_RES_Q_1015___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1015__RX_DCOC_RANGE_1015___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1015__RX_DCOC_RANGE_1015___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1015__RX_DCOC_RES_I_1015___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1015__RX_DCOC_RES_I_1015___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1015__RX_DCOC_RES_Q_1015___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1015__RX_DCOC_RES_Q_1015___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1015___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1015___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1016 (0x005FCFE0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1016___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1016___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1016__RX_DCOC_RANGE_1016___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1016__RX_DCOC_RES_I_1016___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1016__RX_DCOC_RES_Q_1016___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1016__RX_DCOC_RANGE_1016___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1016__RX_DCOC_RANGE_1016___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1016__RX_DCOC_RES_I_1016___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1016__RX_DCOC_RES_I_1016___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1016__RX_DCOC_RES_Q_1016___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1016__RX_DCOC_RES_Q_1016___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1016___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1016___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1017 (0x005FCFE4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1017___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1017___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1017__RX_DCOC_RANGE_1017___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1017__RX_DCOC_RES_I_1017___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1017__RX_DCOC_RES_Q_1017___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1017__RX_DCOC_RANGE_1017___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1017__RX_DCOC_RANGE_1017___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1017__RX_DCOC_RES_I_1017___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1017__RX_DCOC_RES_I_1017___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1017__RX_DCOC_RES_Q_1017___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1017__RX_DCOC_RES_Q_1017___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1017___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1017___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1018 (0x005FCFE8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1018___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1018___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1018__RX_DCOC_RANGE_1018___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1018__RX_DCOC_RES_I_1018___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1018__RX_DCOC_RES_Q_1018___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1018__RX_DCOC_RANGE_1018___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1018__RX_DCOC_RANGE_1018___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1018__RX_DCOC_RES_I_1018___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1018__RX_DCOC_RES_I_1018___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1018__RX_DCOC_RES_Q_1018___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1018__RX_DCOC_RES_Q_1018___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1018___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1018___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1019 (0x005FCFEC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1019___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1019___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1019__RX_DCOC_RANGE_1019___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1019__RX_DCOC_RES_I_1019___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1019__RX_DCOC_RES_Q_1019___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1019__RX_DCOC_RANGE_1019___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1019__RX_DCOC_RANGE_1019___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1019__RX_DCOC_RES_I_1019___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1019__RX_DCOC_RES_I_1019___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1019__RX_DCOC_RES_Q_1019___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1019__RX_DCOC_RES_Q_1019___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1019___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1019___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1020 (0x005FCFF0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1020___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1020___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1020__RX_DCOC_RANGE_1020___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1020__RX_DCOC_RES_I_1020___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1020__RX_DCOC_RES_Q_1020___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1020__RX_DCOC_RANGE_1020___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1020__RX_DCOC_RANGE_1020___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1020__RX_DCOC_RES_I_1020___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1020__RX_DCOC_RES_I_1020___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1020__RX_DCOC_RES_Q_1020___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1020__RX_DCOC_RES_Q_1020___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1020___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1020___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1021 (0x005FCFF4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1021___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1021___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1021__RX_DCOC_RANGE_1021___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1021__RX_DCOC_RES_I_1021___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1021__RX_DCOC_RES_Q_1021___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1021__RX_DCOC_RANGE_1021___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1021__RX_DCOC_RANGE_1021___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1021__RX_DCOC_RES_I_1021___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1021__RX_DCOC_RES_I_1021___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1021__RX_DCOC_RES_Q_1021___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1021__RX_DCOC_RES_Q_1021___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1021___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1021___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1022 (0x005FCFF8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1022___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1022___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1022__RX_DCOC_RANGE_1022___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1022__RX_DCOC_RES_I_1022___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1022__RX_DCOC_RES_Q_1022___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1022__RX_DCOC_RANGE_1022___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1022__RX_DCOC_RANGE_1022___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1022__RX_DCOC_RES_I_1022___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1022__RX_DCOC_RES_I_1022___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1022__RX_DCOC_RES_Q_1022___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1022__RX_DCOC_RES_Q_1022___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1022___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1022___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1023 (0x005FCFFC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1023___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1023___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1023__RX_DCOC_RANGE_1023___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1023__RX_DCOC_RES_I_1023___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1023__RX_DCOC_RES_Q_1023___POR 0x000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1023__RX_DCOC_RANGE_1023___M 0x000C0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1023__RX_DCOC_RANGE_1023___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1023__RX_DCOC_RES_I_1023___M 0x0003FE00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1023__RX_DCOC_RES_I_1023___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1023__RX_DCOC_RES_Q_1023___M 0x000001FF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1023__RX_DCOC_RES_Q_1023___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1023___M 0x000FFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXDCOC_1023___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0 (0x005FD000) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__XLNA_GAIN_ODD_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__LNA_GAIN_ODD_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__GM_GAIN_ODD_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__TIA_GAIN_ODD_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__SLM_XLNA_ODD_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__BQ_GAIN_ODD_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__XLNA_GAIN_EVEN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__LNA_GAIN_EVEN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__GM_GAIN_EVEN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__TIA_GAIN_EVEN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__SLM_XLNA_EVEN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__BQ_GAIN_EVEN_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__XLNA_GAIN_ODD_0___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__XLNA_GAIN_ODD_0___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__LNA_GAIN_ODD_0___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__LNA_GAIN_ODD_0___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__GM_GAIN_ODD_0___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__GM_GAIN_ODD_0___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__TIA_GAIN_ODD_0___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__TIA_GAIN_ODD_0___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__SLM_XLNA_ODD_0___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__SLM_XLNA_ODD_0___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__BQ_GAIN_ODD_0___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__BQ_GAIN_ODD_0___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__XLNA_GAIN_EVEN_0___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__XLNA_GAIN_EVEN_0___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__LNA_GAIN_EVEN_0___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__LNA_GAIN_EVEN_0___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__GM_GAIN_EVEN_0___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__GM_GAIN_EVEN_0___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__TIA_GAIN_EVEN_0___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__TIA_GAIN_EVEN_0___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__SLM_XLNA_EVEN_0___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__SLM_XLNA_EVEN_0___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__BQ_GAIN_EVEN_0___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0__BQ_GAIN_EVEN_0___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1 (0x005FD004) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__XLNA_GAIN_ODD_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__LNA_GAIN_ODD_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__GM_GAIN_ODD_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__TIA_GAIN_ODD_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__SLM_XLNA_ODD_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__BQ_GAIN_ODD_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__XLNA_GAIN_EVEN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__LNA_GAIN_EVEN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__GM_GAIN_EVEN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__TIA_GAIN_EVEN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__SLM_XLNA_EVEN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__BQ_GAIN_EVEN_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__XLNA_GAIN_ODD_1___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__XLNA_GAIN_ODD_1___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__LNA_GAIN_ODD_1___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__LNA_GAIN_ODD_1___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__GM_GAIN_ODD_1___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__GM_GAIN_ODD_1___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__TIA_GAIN_ODD_1___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__TIA_GAIN_ODD_1___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__SLM_XLNA_ODD_1___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__SLM_XLNA_ODD_1___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__BQ_GAIN_ODD_1___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__BQ_GAIN_ODD_1___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__XLNA_GAIN_EVEN_1___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__XLNA_GAIN_EVEN_1___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__LNA_GAIN_EVEN_1___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__LNA_GAIN_EVEN_1___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__GM_GAIN_EVEN_1___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__GM_GAIN_EVEN_1___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__TIA_GAIN_EVEN_1___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__TIA_GAIN_EVEN_1___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__SLM_XLNA_EVEN_1___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__SLM_XLNA_EVEN_1___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__BQ_GAIN_EVEN_1___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1__BQ_GAIN_EVEN_1___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2 (0x005FD008) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__XLNA_GAIN_ODD_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__LNA_GAIN_ODD_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__GM_GAIN_ODD_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__TIA_GAIN_ODD_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__SLM_XLNA_ODD_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__BQ_GAIN_ODD_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__XLNA_GAIN_EVEN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__LNA_GAIN_EVEN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__GM_GAIN_EVEN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__TIA_GAIN_EVEN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__SLM_XLNA_EVEN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__BQ_GAIN_EVEN_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__XLNA_GAIN_ODD_2___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__XLNA_GAIN_ODD_2___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__LNA_GAIN_ODD_2___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__LNA_GAIN_ODD_2___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__GM_GAIN_ODD_2___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__GM_GAIN_ODD_2___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__TIA_GAIN_ODD_2___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__TIA_GAIN_ODD_2___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__SLM_XLNA_ODD_2___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__SLM_XLNA_ODD_2___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__BQ_GAIN_ODD_2___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__BQ_GAIN_ODD_2___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__XLNA_GAIN_EVEN_2___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__XLNA_GAIN_EVEN_2___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__LNA_GAIN_EVEN_2___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__LNA_GAIN_EVEN_2___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__GM_GAIN_EVEN_2___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__GM_GAIN_EVEN_2___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__TIA_GAIN_EVEN_2___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__TIA_GAIN_EVEN_2___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__SLM_XLNA_EVEN_2___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__SLM_XLNA_EVEN_2___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__BQ_GAIN_EVEN_2___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2__BQ_GAIN_EVEN_2___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_2___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3 (0x005FD00C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__XLNA_GAIN_ODD_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__LNA_GAIN_ODD_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__GM_GAIN_ODD_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__TIA_GAIN_ODD_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__SLM_XLNA_ODD_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__BQ_GAIN_ODD_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__XLNA_GAIN_EVEN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__LNA_GAIN_EVEN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__GM_GAIN_EVEN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__TIA_GAIN_EVEN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__SLM_XLNA_EVEN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__BQ_GAIN_EVEN_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__XLNA_GAIN_ODD_3___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__XLNA_GAIN_ODD_3___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__LNA_GAIN_ODD_3___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__LNA_GAIN_ODD_3___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__GM_GAIN_ODD_3___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__GM_GAIN_ODD_3___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__TIA_GAIN_ODD_3___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__TIA_GAIN_ODD_3___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__SLM_XLNA_ODD_3___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__SLM_XLNA_ODD_3___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__BQ_GAIN_ODD_3___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__BQ_GAIN_ODD_3___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__XLNA_GAIN_EVEN_3___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__XLNA_GAIN_EVEN_3___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__LNA_GAIN_EVEN_3___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__LNA_GAIN_EVEN_3___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__GM_GAIN_EVEN_3___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__GM_GAIN_EVEN_3___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__TIA_GAIN_EVEN_3___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__TIA_GAIN_EVEN_3___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__SLM_XLNA_EVEN_3___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__SLM_XLNA_EVEN_3___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__BQ_GAIN_EVEN_3___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3__BQ_GAIN_EVEN_3___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_3___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4 (0x005FD010) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__XLNA_GAIN_ODD_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__LNA_GAIN_ODD_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__GM_GAIN_ODD_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__TIA_GAIN_ODD_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__SLM_XLNA_ODD_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__BQ_GAIN_ODD_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__XLNA_GAIN_EVEN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__LNA_GAIN_EVEN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__GM_GAIN_EVEN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__TIA_GAIN_EVEN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__SLM_XLNA_EVEN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__BQ_GAIN_EVEN_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__XLNA_GAIN_ODD_4___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__XLNA_GAIN_ODD_4___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__LNA_GAIN_ODD_4___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__LNA_GAIN_ODD_4___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__GM_GAIN_ODD_4___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__GM_GAIN_ODD_4___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__TIA_GAIN_ODD_4___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__TIA_GAIN_ODD_4___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__SLM_XLNA_ODD_4___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__SLM_XLNA_ODD_4___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__BQ_GAIN_ODD_4___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__BQ_GAIN_ODD_4___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__XLNA_GAIN_EVEN_4___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__XLNA_GAIN_EVEN_4___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__LNA_GAIN_EVEN_4___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__LNA_GAIN_EVEN_4___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__GM_GAIN_EVEN_4___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__GM_GAIN_EVEN_4___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__TIA_GAIN_EVEN_4___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__TIA_GAIN_EVEN_4___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__SLM_XLNA_EVEN_4___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__SLM_XLNA_EVEN_4___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__BQ_GAIN_EVEN_4___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4__BQ_GAIN_EVEN_4___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_4___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5 (0x005FD014) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__XLNA_GAIN_ODD_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__LNA_GAIN_ODD_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__GM_GAIN_ODD_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__TIA_GAIN_ODD_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__SLM_XLNA_ODD_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__BQ_GAIN_ODD_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__XLNA_GAIN_EVEN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__LNA_GAIN_EVEN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__GM_GAIN_EVEN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__TIA_GAIN_EVEN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__SLM_XLNA_EVEN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__BQ_GAIN_EVEN_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__XLNA_GAIN_ODD_5___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__XLNA_GAIN_ODD_5___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__LNA_GAIN_ODD_5___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__LNA_GAIN_ODD_5___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__GM_GAIN_ODD_5___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__GM_GAIN_ODD_5___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__TIA_GAIN_ODD_5___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__TIA_GAIN_ODD_5___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__SLM_XLNA_ODD_5___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__SLM_XLNA_ODD_5___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__BQ_GAIN_ODD_5___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__BQ_GAIN_ODD_5___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__XLNA_GAIN_EVEN_5___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__XLNA_GAIN_EVEN_5___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__LNA_GAIN_EVEN_5___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__LNA_GAIN_EVEN_5___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__GM_GAIN_EVEN_5___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__GM_GAIN_EVEN_5___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__TIA_GAIN_EVEN_5___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__TIA_GAIN_EVEN_5___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__SLM_XLNA_EVEN_5___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__SLM_XLNA_EVEN_5___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__BQ_GAIN_EVEN_5___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5__BQ_GAIN_EVEN_5___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_5___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6 (0x005FD018) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__XLNA_GAIN_ODD_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__LNA_GAIN_ODD_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__GM_GAIN_ODD_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__TIA_GAIN_ODD_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__SLM_XLNA_ODD_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__BQ_GAIN_ODD_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__XLNA_GAIN_EVEN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__LNA_GAIN_EVEN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__GM_GAIN_EVEN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__TIA_GAIN_EVEN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__SLM_XLNA_EVEN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__BQ_GAIN_EVEN_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__XLNA_GAIN_ODD_6___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__XLNA_GAIN_ODD_6___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__LNA_GAIN_ODD_6___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__LNA_GAIN_ODD_6___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__GM_GAIN_ODD_6___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__GM_GAIN_ODD_6___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__TIA_GAIN_ODD_6___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__TIA_GAIN_ODD_6___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__SLM_XLNA_ODD_6___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__SLM_XLNA_ODD_6___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__BQ_GAIN_ODD_6___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__BQ_GAIN_ODD_6___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__XLNA_GAIN_EVEN_6___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__XLNA_GAIN_EVEN_6___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__LNA_GAIN_EVEN_6___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__LNA_GAIN_EVEN_6___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__GM_GAIN_EVEN_6___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__GM_GAIN_EVEN_6___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__TIA_GAIN_EVEN_6___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__TIA_GAIN_EVEN_6___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__SLM_XLNA_EVEN_6___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__SLM_XLNA_EVEN_6___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__BQ_GAIN_EVEN_6___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6__BQ_GAIN_EVEN_6___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_6___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7 (0x005FD01C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__XLNA_GAIN_ODD_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__LNA_GAIN_ODD_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__GM_GAIN_ODD_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__TIA_GAIN_ODD_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__SLM_XLNA_ODD_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__BQ_GAIN_ODD_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__XLNA_GAIN_EVEN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__LNA_GAIN_EVEN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__GM_GAIN_EVEN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__TIA_GAIN_EVEN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__SLM_XLNA_EVEN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__BQ_GAIN_EVEN_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__XLNA_GAIN_ODD_7___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__XLNA_GAIN_ODD_7___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__LNA_GAIN_ODD_7___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__LNA_GAIN_ODD_7___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__GM_GAIN_ODD_7___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__GM_GAIN_ODD_7___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__TIA_GAIN_ODD_7___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__TIA_GAIN_ODD_7___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__SLM_XLNA_ODD_7___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__SLM_XLNA_ODD_7___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__BQ_GAIN_ODD_7___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__BQ_GAIN_ODD_7___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__XLNA_GAIN_EVEN_7___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__XLNA_GAIN_EVEN_7___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__LNA_GAIN_EVEN_7___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__LNA_GAIN_EVEN_7___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__GM_GAIN_EVEN_7___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__GM_GAIN_EVEN_7___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__TIA_GAIN_EVEN_7___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__TIA_GAIN_EVEN_7___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__SLM_XLNA_EVEN_7___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__SLM_XLNA_EVEN_7___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__BQ_GAIN_EVEN_7___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7__BQ_GAIN_EVEN_7___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_7___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8 (0x005FD020) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__XLNA_GAIN_ODD_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__LNA_GAIN_ODD_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__GM_GAIN_ODD_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__TIA_GAIN_ODD_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__SLM_XLNA_ODD_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__BQ_GAIN_ODD_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__XLNA_GAIN_EVEN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__LNA_GAIN_EVEN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__GM_GAIN_EVEN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__TIA_GAIN_EVEN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__SLM_XLNA_EVEN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__BQ_GAIN_EVEN_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__XLNA_GAIN_ODD_8___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__XLNA_GAIN_ODD_8___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__LNA_GAIN_ODD_8___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__LNA_GAIN_ODD_8___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__GM_GAIN_ODD_8___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__GM_GAIN_ODD_8___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__TIA_GAIN_ODD_8___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__TIA_GAIN_ODD_8___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__SLM_XLNA_ODD_8___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__SLM_XLNA_ODD_8___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__BQ_GAIN_ODD_8___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__BQ_GAIN_ODD_8___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__XLNA_GAIN_EVEN_8___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__XLNA_GAIN_EVEN_8___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__LNA_GAIN_EVEN_8___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__LNA_GAIN_EVEN_8___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__GM_GAIN_EVEN_8___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__GM_GAIN_EVEN_8___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__TIA_GAIN_EVEN_8___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__TIA_GAIN_EVEN_8___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__SLM_XLNA_EVEN_8___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__SLM_XLNA_EVEN_8___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__BQ_GAIN_EVEN_8___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8__BQ_GAIN_EVEN_8___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_8___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9 (0x005FD024) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__XLNA_GAIN_ODD_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__LNA_GAIN_ODD_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__GM_GAIN_ODD_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__TIA_GAIN_ODD_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__SLM_XLNA_ODD_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__BQ_GAIN_ODD_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__XLNA_GAIN_EVEN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__LNA_GAIN_EVEN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__GM_GAIN_EVEN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__TIA_GAIN_EVEN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__SLM_XLNA_EVEN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__BQ_GAIN_EVEN_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__XLNA_GAIN_ODD_9___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__XLNA_GAIN_ODD_9___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__LNA_GAIN_ODD_9___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__LNA_GAIN_ODD_9___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__GM_GAIN_ODD_9___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__GM_GAIN_ODD_9___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__TIA_GAIN_ODD_9___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__TIA_GAIN_ODD_9___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__SLM_XLNA_ODD_9___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__SLM_XLNA_ODD_9___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__BQ_GAIN_ODD_9___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__BQ_GAIN_ODD_9___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__XLNA_GAIN_EVEN_9___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__XLNA_GAIN_EVEN_9___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__LNA_GAIN_EVEN_9___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__LNA_GAIN_EVEN_9___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__GM_GAIN_EVEN_9___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__GM_GAIN_EVEN_9___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__TIA_GAIN_EVEN_9___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__TIA_GAIN_EVEN_9___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__SLM_XLNA_EVEN_9___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__SLM_XLNA_EVEN_9___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__BQ_GAIN_EVEN_9___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9__BQ_GAIN_EVEN_9___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_9___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10 (0x005FD028) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__XLNA_GAIN_ODD_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__LNA_GAIN_ODD_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__GM_GAIN_ODD_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__TIA_GAIN_ODD_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__SLM_XLNA_ODD_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__BQ_GAIN_ODD_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__XLNA_GAIN_EVEN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__LNA_GAIN_EVEN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__GM_GAIN_EVEN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__TIA_GAIN_EVEN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__SLM_XLNA_EVEN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__BQ_GAIN_EVEN_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__XLNA_GAIN_ODD_10___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__XLNA_GAIN_ODD_10___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__LNA_GAIN_ODD_10___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__LNA_GAIN_ODD_10___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__GM_GAIN_ODD_10___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__GM_GAIN_ODD_10___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__TIA_GAIN_ODD_10___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__TIA_GAIN_ODD_10___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__SLM_XLNA_ODD_10___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__SLM_XLNA_ODD_10___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__BQ_GAIN_ODD_10___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__BQ_GAIN_ODD_10___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__XLNA_GAIN_EVEN_10___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__XLNA_GAIN_EVEN_10___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__LNA_GAIN_EVEN_10___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__LNA_GAIN_EVEN_10___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__GM_GAIN_EVEN_10___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__GM_GAIN_EVEN_10___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__TIA_GAIN_EVEN_10___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__TIA_GAIN_EVEN_10___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__SLM_XLNA_EVEN_10___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__SLM_XLNA_EVEN_10___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__BQ_GAIN_EVEN_10___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10__BQ_GAIN_EVEN_10___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_10___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11 (0x005FD02C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__XLNA_GAIN_ODD_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__LNA_GAIN_ODD_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__GM_GAIN_ODD_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__TIA_GAIN_ODD_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__SLM_XLNA_ODD_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__BQ_GAIN_ODD_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__XLNA_GAIN_EVEN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__LNA_GAIN_EVEN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__GM_GAIN_EVEN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__TIA_GAIN_EVEN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__SLM_XLNA_EVEN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__BQ_GAIN_EVEN_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__XLNA_GAIN_ODD_11___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__XLNA_GAIN_ODD_11___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__LNA_GAIN_ODD_11___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__LNA_GAIN_ODD_11___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__GM_GAIN_ODD_11___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__GM_GAIN_ODD_11___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__TIA_GAIN_ODD_11___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__TIA_GAIN_ODD_11___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__SLM_XLNA_ODD_11___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__SLM_XLNA_ODD_11___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__BQ_GAIN_ODD_11___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__BQ_GAIN_ODD_11___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__XLNA_GAIN_EVEN_11___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__XLNA_GAIN_EVEN_11___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__LNA_GAIN_EVEN_11___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__LNA_GAIN_EVEN_11___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__GM_GAIN_EVEN_11___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__GM_GAIN_EVEN_11___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__TIA_GAIN_EVEN_11___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__TIA_GAIN_EVEN_11___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__SLM_XLNA_EVEN_11___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__SLM_XLNA_EVEN_11___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__BQ_GAIN_EVEN_11___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11__BQ_GAIN_EVEN_11___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_11___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12 (0x005FD030) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__XLNA_GAIN_ODD_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__LNA_GAIN_ODD_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__GM_GAIN_ODD_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__TIA_GAIN_ODD_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__SLM_XLNA_ODD_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__BQ_GAIN_ODD_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__XLNA_GAIN_EVEN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__LNA_GAIN_EVEN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__GM_GAIN_EVEN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__TIA_GAIN_EVEN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__SLM_XLNA_EVEN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__BQ_GAIN_EVEN_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__XLNA_GAIN_ODD_12___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__XLNA_GAIN_ODD_12___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__LNA_GAIN_ODD_12___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__LNA_GAIN_ODD_12___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__GM_GAIN_ODD_12___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__GM_GAIN_ODD_12___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__TIA_GAIN_ODD_12___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__TIA_GAIN_ODD_12___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__SLM_XLNA_ODD_12___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__SLM_XLNA_ODD_12___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__BQ_GAIN_ODD_12___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__BQ_GAIN_ODD_12___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__XLNA_GAIN_EVEN_12___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__XLNA_GAIN_EVEN_12___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__LNA_GAIN_EVEN_12___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__LNA_GAIN_EVEN_12___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__GM_GAIN_EVEN_12___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__GM_GAIN_EVEN_12___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__TIA_GAIN_EVEN_12___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__TIA_GAIN_EVEN_12___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__SLM_XLNA_EVEN_12___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__SLM_XLNA_EVEN_12___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__BQ_GAIN_EVEN_12___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12__BQ_GAIN_EVEN_12___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_12___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13 (0x005FD034) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__XLNA_GAIN_ODD_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__LNA_GAIN_ODD_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__GM_GAIN_ODD_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__TIA_GAIN_ODD_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__SLM_XLNA_ODD_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__BQ_GAIN_ODD_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__XLNA_GAIN_EVEN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__LNA_GAIN_EVEN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__GM_GAIN_EVEN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__TIA_GAIN_EVEN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__SLM_XLNA_EVEN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__BQ_GAIN_EVEN_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__XLNA_GAIN_ODD_13___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__XLNA_GAIN_ODD_13___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__LNA_GAIN_ODD_13___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__LNA_GAIN_ODD_13___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__GM_GAIN_ODD_13___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__GM_GAIN_ODD_13___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__TIA_GAIN_ODD_13___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__TIA_GAIN_ODD_13___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__SLM_XLNA_ODD_13___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__SLM_XLNA_ODD_13___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__BQ_GAIN_ODD_13___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__BQ_GAIN_ODD_13___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__XLNA_GAIN_EVEN_13___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__XLNA_GAIN_EVEN_13___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__LNA_GAIN_EVEN_13___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__LNA_GAIN_EVEN_13___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__GM_GAIN_EVEN_13___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__GM_GAIN_EVEN_13___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__TIA_GAIN_EVEN_13___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__TIA_GAIN_EVEN_13___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__SLM_XLNA_EVEN_13___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__SLM_XLNA_EVEN_13___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__BQ_GAIN_EVEN_13___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13__BQ_GAIN_EVEN_13___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_13___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14 (0x005FD038) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__XLNA_GAIN_ODD_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__LNA_GAIN_ODD_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__GM_GAIN_ODD_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__TIA_GAIN_ODD_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__SLM_XLNA_ODD_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__BQ_GAIN_ODD_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__XLNA_GAIN_EVEN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__LNA_GAIN_EVEN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__GM_GAIN_EVEN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__TIA_GAIN_EVEN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__SLM_XLNA_EVEN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__BQ_GAIN_EVEN_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__XLNA_GAIN_ODD_14___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__XLNA_GAIN_ODD_14___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__LNA_GAIN_ODD_14___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__LNA_GAIN_ODD_14___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__GM_GAIN_ODD_14___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__GM_GAIN_ODD_14___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__TIA_GAIN_ODD_14___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__TIA_GAIN_ODD_14___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__SLM_XLNA_ODD_14___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__SLM_XLNA_ODD_14___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__BQ_GAIN_ODD_14___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__BQ_GAIN_ODD_14___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__XLNA_GAIN_EVEN_14___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__XLNA_GAIN_EVEN_14___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__LNA_GAIN_EVEN_14___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__LNA_GAIN_EVEN_14___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__GM_GAIN_EVEN_14___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__GM_GAIN_EVEN_14___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__TIA_GAIN_EVEN_14___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__TIA_GAIN_EVEN_14___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__SLM_XLNA_EVEN_14___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__SLM_XLNA_EVEN_14___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__BQ_GAIN_EVEN_14___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14__BQ_GAIN_EVEN_14___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_14___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15 (0x005FD03C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__XLNA_GAIN_ODD_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__LNA_GAIN_ODD_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__GM_GAIN_ODD_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__TIA_GAIN_ODD_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__SLM_XLNA_ODD_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__BQ_GAIN_ODD_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__XLNA_GAIN_EVEN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__LNA_GAIN_EVEN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__GM_GAIN_EVEN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__TIA_GAIN_EVEN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__SLM_XLNA_EVEN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__BQ_GAIN_EVEN_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__XLNA_GAIN_ODD_15___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__XLNA_GAIN_ODD_15___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__LNA_GAIN_ODD_15___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__LNA_GAIN_ODD_15___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__GM_GAIN_ODD_15___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__GM_GAIN_ODD_15___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__TIA_GAIN_ODD_15___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__TIA_GAIN_ODD_15___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__SLM_XLNA_ODD_15___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__SLM_XLNA_ODD_15___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__BQ_GAIN_ODD_15___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__BQ_GAIN_ODD_15___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__XLNA_GAIN_EVEN_15___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__XLNA_GAIN_EVEN_15___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__LNA_GAIN_EVEN_15___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__LNA_GAIN_EVEN_15___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__GM_GAIN_EVEN_15___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__GM_GAIN_EVEN_15___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__TIA_GAIN_EVEN_15___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__TIA_GAIN_EVEN_15___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__SLM_XLNA_EVEN_15___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__SLM_XLNA_EVEN_15___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__BQ_GAIN_EVEN_15___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15__BQ_GAIN_EVEN_15___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_15___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16 (0x005FD040) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__XLNA_GAIN_ODD_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__LNA_GAIN_ODD_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__GM_GAIN_ODD_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__TIA_GAIN_ODD_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__SLM_XLNA_ODD_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__BQ_GAIN_ODD_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__XLNA_GAIN_EVEN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__LNA_GAIN_EVEN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__GM_GAIN_EVEN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__TIA_GAIN_EVEN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__SLM_XLNA_EVEN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__BQ_GAIN_EVEN_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__XLNA_GAIN_ODD_16___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__XLNA_GAIN_ODD_16___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__LNA_GAIN_ODD_16___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__LNA_GAIN_ODD_16___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__GM_GAIN_ODD_16___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__GM_GAIN_ODD_16___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__TIA_GAIN_ODD_16___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__TIA_GAIN_ODD_16___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__SLM_XLNA_ODD_16___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__SLM_XLNA_ODD_16___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__BQ_GAIN_ODD_16___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__BQ_GAIN_ODD_16___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__XLNA_GAIN_EVEN_16___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__XLNA_GAIN_EVEN_16___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__LNA_GAIN_EVEN_16___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__LNA_GAIN_EVEN_16___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__GM_GAIN_EVEN_16___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__GM_GAIN_EVEN_16___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__TIA_GAIN_EVEN_16___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__TIA_GAIN_EVEN_16___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__SLM_XLNA_EVEN_16___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__SLM_XLNA_EVEN_16___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__BQ_GAIN_EVEN_16___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16__BQ_GAIN_EVEN_16___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_16___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17 (0x005FD044) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__XLNA_GAIN_ODD_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__LNA_GAIN_ODD_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__GM_GAIN_ODD_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__TIA_GAIN_ODD_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__SLM_XLNA_ODD_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__BQ_GAIN_ODD_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__XLNA_GAIN_EVEN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__LNA_GAIN_EVEN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__GM_GAIN_EVEN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__TIA_GAIN_EVEN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__SLM_XLNA_EVEN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__BQ_GAIN_EVEN_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__XLNA_GAIN_ODD_17___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__XLNA_GAIN_ODD_17___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__LNA_GAIN_ODD_17___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__LNA_GAIN_ODD_17___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__GM_GAIN_ODD_17___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__GM_GAIN_ODD_17___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__TIA_GAIN_ODD_17___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__TIA_GAIN_ODD_17___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__SLM_XLNA_ODD_17___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__SLM_XLNA_ODD_17___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__BQ_GAIN_ODD_17___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__BQ_GAIN_ODD_17___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__XLNA_GAIN_EVEN_17___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__XLNA_GAIN_EVEN_17___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__LNA_GAIN_EVEN_17___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__LNA_GAIN_EVEN_17___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__GM_GAIN_EVEN_17___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__GM_GAIN_EVEN_17___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__TIA_GAIN_EVEN_17___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__TIA_GAIN_EVEN_17___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__SLM_XLNA_EVEN_17___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__SLM_XLNA_EVEN_17___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__BQ_GAIN_EVEN_17___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17__BQ_GAIN_EVEN_17___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_17___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18 (0x005FD048) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__XLNA_GAIN_ODD_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__LNA_GAIN_ODD_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__GM_GAIN_ODD_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__TIA_GAIN_ODD_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__SLM_XLNA_ODD_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__BQ_GAIN_ODD_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__XLNA_GAIN_EVEN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__LNA_GAIN_EVEN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__GM_GAIN_EVEN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__TIA_GAIN_EVEN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__SLM_XLNA_EVEN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__BQ_GAIN_EVEN_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__XLNA_GAIN_ODD_18___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__XLNA_GAIN_ODD_18___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__LNA_GAIN_ODD_18___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__LNA_GAIN_ODD_18___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__GM_GAIN_ODD_18___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__GM_GAIN_ODD_18___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__TIA_GAIN_ODD_18___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__TIA_GAIN_ODD_18___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__SLM_XLNA_ODD_18___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__SLM_XLNA_ODD_18___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__BQ_GAIN_ODD_18___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__BQ_GAIN_ODD_18___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__XLNA_GAIN_EVEN_18___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__XLNA_GAIN_EVEN_18___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__LNA_GAIN_EVEN_18___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__LNA_GAIN_EVEN_18___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__GM_GAIN_EVEN_18___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__GM_GAIN_EVEN_18___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__TIA_GAIN_EVEN_18___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__TIA_GAIN_EVEN_18___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__SLM_XLNA_EVEN_18___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__SLM_XLNA_EVEN_18___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__BQ_GAIN_EVEN_18___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18__BQ_GAIN_EVEN_18___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_18___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19 (0x005FD04C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__XLNA_GAIN_ODD_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__LNA_GAIN_ODD_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__GM_GAIN_ODD_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__TIA_GAIN_ODD_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__SLM_XLNA_ODD_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__BQ_GAIN_ODD_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__XLNA_GAIN_EVEN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__LNA_GAIN_EVEN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__GM_GAIN_EVEN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__TIA_GAIN_EVEN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__SLM_XLNA_EVEN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__BQ_GAIN_EVEN_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__XLNA_GAIN_ODD_19___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__XLNA_GAIN_ODD_19___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__LNA_GAIN_ODD_19___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__LNA_GAIN_ODD_19___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__GM_GAIN_ODD_19___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__GM_GAIN_ODD_19___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__TIA_GAIN_ODD_19___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__TIA_GAIN_ODD_19___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__SLM_XLNA_ODD_19___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__SLM_XLNA_ODD_19___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__BQ_GAIN_ODD_19___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__BQ_GAIN_ODD_19___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__XLNA_GAIN_EVEN_19___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__XLNA_GAIN_EVEN_19___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__LNA_GAIN_EVEN_19___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__LNA_GAIN_EVEN_19___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__GM_GAIN_EVEN_19___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__GM_GAIN_EVEN_19___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__TIA_GAIN_EVEN_19___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__TIA_GAIN_EVEN_19___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__SLM_XLNA_EVEN_19___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__SLM_XLNA_EVEN_19___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__BQ_GAIN_EVEN_19___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19__BQ_GAIN_EVEN_19___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_19___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20 (0x005FD050) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__XLNA_GAIN_ODD_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__LNA_GAIN_ODD_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__GM_GAIN_ODD_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__TIA_GAIN_ODD_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__SLM_XLNA_ODD_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__BQ_GAIN_ODD_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__XLNA_GAIN_EVEN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__LNA_GAIN_EVEN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__GM_GAIN_EVEN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__TIA_GAIN_EVEN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__SLM_XLNA_EVEN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__BQ_GAIN_EVEN_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__XLNA_GAIN_ODD_20___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__XLNA_GAIN_ODD_20___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__LNA_GAIN_ODD_20___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__LNA_GAIN_ODD_20___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__GM_GAIN_ODD_20___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__GM_GAIN_ODD_20___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__TIA_GAIN_ODD_20___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__TIA_GAIN_ODD_20___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__SLM_XLNA_ODD_20___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__SLM_XLNA_ODD_20___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__BQ_GAIN_ODD_20___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__BQ_GAIN_ODD_20___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__XLNA_GAIN_EVEN_20___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__XLNA_GAIN_EVEN_20___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__LNA_GAIN_EVEN_20___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__LNA_GAIN_EVEN_20___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__GM_GAIN_EVEN_20___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__GM_GAIN_EVEN_20___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__TIA_GAIN_EVEN_20___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__TIA_GAIN_EVEN_20___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__SLM_XLNA_EVEN_20___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__SLM_XLNA_EVEN_20___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__BQ_GAIN_EVEN_20___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20__BQ_GAIN_EVEN_20___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_20___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21 (0x005FD054) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__XLNA_GAIN_ODD_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__LNA_GAIN_ODD_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__GM_GAIN_ODD_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__TIA_GAIN_ODD_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__SLM_XLNA_ODD_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__BQ_GAIN_ODD_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__XLNA_GAIN_EVEN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__LNA_GAIN_EVEN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__GM_GAIN_EVEN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__TIA_GAIN_EVEN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__SLM_XLNA_EVEN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__BQ_GAIN_EVEN_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__XLNA_GAIN_ODD_21___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__XLNA_GAIN_ODD_21___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__LNA_GAIN_ODD_21___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__LNA_GAIN_ODD_21___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__GM_GAIN_ODD_21___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__GM_GAIN_ODD_21___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__TIA_GAIN_ODD_21___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__TIA_GAIN_ODD_21___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__SLM_XLNA_ODD_21___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__SLM_XLNA_ODD_21___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__BQ_GAIN_ODD_21___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__BQ_GAIN_ODD_21___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__XLNA_GAIN_EVEN_21___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__XLNA_GAIN_EVEN_21___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__LNA_GAIN_EVEN_21___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__LNA_GAIN_EVEN_21___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__GM_GAIN_EVEN_21___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__GM_GAIN_EVEN_21___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__TIA_GAIN_EVEN_21___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__TIA_GAIN_EVEN_21___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__SLM_XLNA_EVEN_21___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__SLM_XLNA_EVEN_21___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__BQ_GAIN_EVEN_21___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21__BQ_GAIN_EVEN_21___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_21___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22 (0x005FD058) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__XLNA_GAIN_ODD_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__LNA_GAIN_ODD_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__GM_GAIN_ODD_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__TIA_GAIN_ODD_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__SLM_XLNA_ODD_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__BQ_GAIN_ODD_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__XLNA_GAIN_EVEN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__LNA_GAIN_EVEN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__GM_GAIN_EVEN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__TIA_GAIN_EVEN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__SLM_XLNA_EVEN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__BQ_GAIN_EVEN_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__XLNA_GAIN_ODD_22___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__XLNA_GAIN_ODD_22___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__LNA_GAIN_ODD_22___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__LNA_GAIN_ODD_22___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__GM_GAIN_ODD_22___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__GM_GAIN_ODD_22___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__TIA_GAIN_ODD_22___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__TIA_GAIN_ODD_22___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__SLM_XLNA_ODD_22___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__SLM_XLNA_ODD_22___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__BQ_GAIN_ODD_22___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__BQ_GAIN_ODD_22___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__XLNA_GAIN_EVEN_22___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__XLNA_GAIN_EVEN_22___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__LNA_GAIN_EVEN_22___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__LNA_GAIN_EVEN_22___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__GM_GAIN_EVEN_22___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__GM_GAIN_EVEN_22___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__TIA_GAIN_EVEN_22___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__TIA_GAIN_EVEN_22___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__SLM_XLNA_EVEN_22___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__SLM_XLNA_EVEN_22___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__BQ_GAIN_EVEN_22___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22__BQ_GAIN_EVEN_22___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_22___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23 (0x005FD05C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__XLNA_GAIN_ODD_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__LNA_GAIN_ODD_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__GM_GAIN_ODD_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__TIA_GAIN_ODD_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__SLM_XLNA_ODD_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__BQ_GAIN_ODD_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__XLNA_GAIN_EVEN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__LNA_GAIN_EVEN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__GM_GAIN_EVEN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__TIA_GAIN_EVEN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__SLM_XLNA_EVEN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__BQ_GAIN_EVEN_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__XLNA_GAIN_ODD_23___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__XLNA_GAIN_ODD_23___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__LNA_GAIN_ODD_23___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__LNA_GAIN_ODD_23___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__GM_GAIN_ODD_23___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__GM_GAIN_ODD_23___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__TIA_GAIN_ODD_23___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__TIA_GAIN_ODD_23___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__SLM_XLNA_ODD_23___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__SLM_XLNA_ODD_23___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__BQ_GAIN_ODD_23___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__BQ_GAIN_ODD_23___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__XLNA_GAIN_EVEN_23___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__XLNA_GAIN_EVEN_23___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__LNA_GAIN_EVEN_23___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__LNA_GAIN_EVEN_23___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__GM_GAIN_EVEN_23___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__GM_GAIN_EVEN_23___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__TIA_GAIN_EVEN_23___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__TIA_GAIN_EVEN_23___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__SLM_XLNA_EVEN_23___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__SLM_XLNA_EVEN_23___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__BQ_GAIN_EVEN_23___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23__BQ_GAIN_EVEN_23___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_23___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24 (0x005FD060) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__XLNA_GAIN_ODD_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__LNA_GAIN_ODD_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__GM_GAIN_ODD_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__TIA_GAIN_ODD_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__SLM_XLNA_ODD_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__BQ_GAIN_ODD_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__XLNA_GAIN_EVEN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__LNA_GAIN_EVEN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__GM_GAIN_EVEN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__TIA_GAIN_EVEN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__SLM_XLNA_EVEN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__BQ_GAIN_EVEN_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__XLNA_GAIN_ODD_24___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__XLNA_GAIN_ODD_24___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__LNA_GAIN_ODD_24___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__LNA_GAIN_ODD_24___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__GM_GAIN_ODD_24___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__GM_GAIN_ODD_24___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__TIA_GAIN_ODD_24___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__TIA_GAIN_ODD_24___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__SLM_XLNA_ODD_24___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__SLM_XLNA_ODD_24___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__BQ_GAIN_ODD_24___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__BQ_GAIN_ODD_24___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__XLNA_GAIN_EVEN_24___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__XLNA_GAIN_EVEN_24___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__LNA_GAIN_EVEN_24___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__LNA_GAIN_EVEN_24___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__GM_GAIN_EVEN_24___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__GM_GAIN_EVEN_24___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__TIA_GAIN_EVEN_24___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__TIA_GAIN_EVEN_24___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__SLM_XLNA_EVEN_24___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__SLM_XLNA_EVEN_24___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__BQ_GAIN_EVEN_24___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24__BQ_GAIN_EVEN_24___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_24___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25 (0x005FD064) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__XLNA_GAIN_ODD_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__LNA_GAIN_ODD_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__GM_GAIN_ODD_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__TIA_GAIN_ODD_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__SLM_XLNA_ODD_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__BQ_GAIN_ODD_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__XLNA_GAIN_EVEN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__LNA_GAIN_EVEN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__GM_GAIN_EVEN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__TIA_GAIN_EVEN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__SLM_XLNA_EVEN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__BQ_GAIN_EVEN_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__XLNA_GAIN_ODD_25___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__XLNA_GAIN_ODD_25___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__LNA_GAIN_ODD_25___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__LNA_GAIN_ODD_25___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__GM_GAIN_ODD_25___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__GM_GAIN_ODD_25___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__TIA_GAIN_ODD_25___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__TIA_GAIN_ODD_25___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__SLM_XLNA_ODD_25___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__SLM_XLNA_ODD_25___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__BQ_GAIN_ODD_25___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__BQ_GAIN_ODD_25___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__XLNA_GAIN_EVEN_25___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__XLNA_GAIN_EVEN_25___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__LNA_GAIN_EVEN_25___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__LNA_GAIN_EVEN_25___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__GM_GAIN_EVEN_25___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__GM_GAIN_EVEN_25___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__TIA_GAIN_EVEN_25___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__TIA_GAIN_EVEN_25___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__SLM_XLNA_EVEN_25___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__SLM_XLNA_EVEN_25___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__BQ_GAIN_EVEN_25___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25__BQ_GAIN_EVEN_25___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_25___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26 (0x005FD068) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__XLNA_GAIN_ODD_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__LNA_GAIN_ODD_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__GM_GAIN_ODD_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__TIA_GAIN_ODD_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__SLM_XLNA_ODD_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__BQ_GAIN_ODD_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__XLNA_GAIN_EVEN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__LNA_GAIN_EVEN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__GM_GAIN_EVEN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__TIA_GAIN_EVEN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__SLM_XLNA_EVEN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__BQ_GAIN_EVEN_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__XLNA_GAIN_ODD_26___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__XLNA_GAIN_ODD_26___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__LNA_GAIN_ODD_26___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__LNA_GAIN_ODD_26___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__GM_GAIN_ODD_26___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__GM_GAIN_ODD_26___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__TIA_GAIN_ODD_26___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__TIA_GAIN_ODD_26___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__SLM_XLNA_ODD_26___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__SLM_XLNA_ODD_26___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__BQ_GAIN_ODD_26___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__BQ_GAIN_ODD_26___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__XLNA_GAIN_EVEN_26___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__XLNA_GAIN_EVEN_26___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__LNA_GAIN_EVEN_26___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__LNA_GAIN_EVEN_26___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__GM_GAIN_EVEN_26___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__GM_GAIN_EVEN_26___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__TIA_GAIN_EVEN_26___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__TIA_GAIN_EVEN_26___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__SLM_XLNA_EVEN_26___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__SLM_XLNA_EVEN_26___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__BQ_GAIN_EVEN_26___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26__BQ_GAIN_EVEN_26___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_26___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27 (0x005FD06C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__XLNA_GAIN_ODD_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__LNA_GAIN_ODD_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__GM_GAIN_ODD_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__TIA_GAIN_ODD_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__SLM_XLNA_ODD_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__BQ_GAIN_ODD_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__XLNA_GAIN_EVEN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__LNA_GAIN_EVEN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__GM_GAIN_EVEN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__TIA_GAIN_EVEN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__SLM_XLNA_EVEN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__BQ_GAIN_EVEN_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__XLNA_GAIN_ODD_27___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__XLNA_GAIN_ODD_27___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__LNA_GAIN_ODD_27___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__LNA_GAIN_ODD_27___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__GM_GAIN_ODD_27___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__GM_GAIN_ODD_27___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__TIA_GAIN_ODD_27___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__TIA_GAIN_ODD_27___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__SLM_XLNA_ODD_27___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__SLM_XLNA_ODD_27___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__BQ_GAIN_ODD_27___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__BQ_GAIN_ODD_27___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__XLNA_GAIN_EVEN_27___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__XLNA_GAIN_EVEN_27___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__LNA_GAIN_EVEN_27___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__LNA_GAIN_EVEN_27___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__GM_GAIN_EVEN_27___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__GM_GAIN_EVEN_27___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__TIA_GAIN_EVEN_27___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__TIA_GAIN_EVEN_27___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__SLM_XLNA_EVEN_27___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__SLM_XLNA_EVEN_27___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__BQ_GAIN_EVEN_27___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27__BQ_GAIN_EVEN_27___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_27___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28 (0x005FD070) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__XLNA_GAIN_ODD_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__LNA_GAIN_ODD_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__GM_GAIN_ODD_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__TIA_GAIN_ODD_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__SLM_XLNA_ODD_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__BQ_GAIN_ODD_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__XLNA_GAIN_EVEN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__LNA_GAIN_EVEN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__GM_GAIN_EVEN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__TIA_GAIN_EVEN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__SLM_XLNA_EVEN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__BQ_GAIN_EVEN_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__XLNA_GAIN_ODD_28___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__XLNA_GAIN_ODD_28___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__LNA_GAIN_ODD_28___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__LNA_GAIN_ODD_28___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__GM_GAIN_ODD_28___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__GM_GAIN_ODD_28___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__TIA_GAIN_ODD_28___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__TIA_GAIN_ODD_28___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__SLM_XLNA_ODD_28___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__SLM_XLNA_ODD_28___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__BQ_GAIN_ODD_28___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__BQ_GAIN_ODD_28___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__XLNA_GAIN_EVEN_28___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__XLNA_GAIN_EVEN_28___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__LNA_GAIN_EVEN_28___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__LNA_GAIN_EVEN_28___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__GM_GAIN_EVEN_28___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__GM_GAIN_EVEN_28___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__TIA_GAIN_EVEN_28___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__TIA_GAIN_EVEN_28___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__SLM_XLNA_EVEN_28___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__SLM_XLNA_EVEN_28___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__BQ_GAIN_EVEN_28___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28__BQ_GAIN_EVEN_28___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_28___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29 (0x005FD074) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__XLNA_GAIN_ODD_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__LNA_GAIN_ODD_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__GM_GAIN_ODD_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__TIA_GAIN_ODD_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__SLM_XLNA_ODD_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__BQ_GAIN_ODD_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__XLNA_GAIN_EVEN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__LNA_GAIN_EVEN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__GM_GAIN_EVEN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__TIA_GAIN_EVEN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__SLM_XLNA_EVEN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__BQ_GAIN_EVEN_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__XLNA_GAIN_ODD_29___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__XLNA_GAIN_ODD_29___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__LNA_GAIN_ODD_29___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__LNA_GAIN_ODD_29___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__GM_GAIN_ODD_29___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__GM_GAIN_ODD_29___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__TIA_GAIN_ODD_29___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__TIA_GAIN_ODD_29___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__SLM_XLNA_ODD_29___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__SLM_XLNA_ODD_29___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__BQ_GAIN_ODD_29___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__BQ_GAIN_ODD_29___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__XLNA_GAIN_EVEN_29___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__XLNA_GAIN_EVEN_29___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__LNA_GAIN_EVEN_29___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__LNA_GAIN_EVEN_29___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__GM_GAIN_EVEN_29___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__GM_GAIN_EVEN_29___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__TIA_GAIN_EVEN_29___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__TIA_GAIN_EVEN_29___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__SLM_XLNA_EVEN_29___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__SLM_XLNA_EVEN_29___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__BQ_GAIN_EVEN_29___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29__BQ_GAIN_EVEN_29___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_29___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30 (0x005FD078) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__XLNA_GAIN_ODD_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__LNA_GAIN_ODD_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__GM_GAIN_ODD_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__TIA_GAIN_ODD_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__SLM_XLNA_ODD_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__BQ_GAIN_ODD_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__XLNA_GAIN_EVEN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__LNA_GAIN_EVEN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__GM_GAIN_EVEN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__TIA_GAIN_EVEN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__SLM_XLNA_EVEN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__BQ_GAIN_EVEN_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__XLNA_GAIN_ODD_30___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__XLNA_GAIN_ODD_30___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__LNA_GAIN_ODD_30___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__LNA_GAIN_ODD_30___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__GM_GAIN_ODD_30___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__GM_GAIN_ODD_30___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__TIA_GAIN_ODD_30___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__TIA_GAIN_ODD_30___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__SLM_XLNA_ODD_30___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__SLM_XLNA_ODD_30___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__BQ_GAIN_ODD_30___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__BQ_GAIN_ODD_30___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__XLNA_GAIN_EVEN_30___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__XLNA_GAIN_EVEN_30___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__LNA_GAIN_EVEN_30___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__LNA_GAIN_EVEN_30___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__GM_GAIN_EVEN_30___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__GM_GAIN_EVEN_30___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__TIA_GAIN_EVEN_30___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__TIA_GAIN_EVEN_30___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__SLM_XLNA_EVEN_30___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__SLM_XLNA_EVEN_30___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__BQ_GAIN_EVEN_30___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30__BQ_GAIN_EVEN_30___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_30___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31 (0x005FD07C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__XLNA_GAIN_ODD_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__LNA_GAIN_ODD_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__GM_GAIN_ODD_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__TIA_GAIN_ODD_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__SLM_XLNA_ODD_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__BQ_GAIN_ODD_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__XLNA_GAIN_EVEN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__LNA_GAIN_EVEN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__GM_GAIN_EVEN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__TIA_GAIN_EVEN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__SLM_XLNA_EVEN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__BQ_GAIN_EVEN_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__XLNA_GAIN_ODD_31___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__XLNA_GAIN_ODD_31___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__LNA_GAIN_ODD_31___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__LNA_GAIN_ODD_31___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__GM_GAIN_ODD_31___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__GM_GAIN_ODD_31___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__TIA_GAIN_ODD_31___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__TIA_GAIN_ODD_31___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__SLM_XLNA_ODD_31___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__SLM_XLNA_ODD_31___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__BQ_GAIN_ODD_31___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__BQ_GAIN_ODD_31___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__XLNA_GAIN_EVEN_31___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__XLNA_GAIN_EVEN_31___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__LNA_GAIN_EVEN_31___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__LNA_GAIN_EVEN_31___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__GM_GAIN_EVEN_31___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__GM_GAIN_EVEN_31___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__TIA_GAIN_EVEN_31___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__TIA_GAIN_EVEN_31___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__SLM_XLNA_EVEN_31___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__SLM_XLNA_EVEN_31___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__BQ_GAIN_EVEN_31___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31__BQ_GAIN_EVEN_31___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_31___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32 (0x005FD080) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__XLNA_GAIN_ODD_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__LNA_GAIN_ODD_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__GM_GAIN_ODD_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__TIA_GAIN_ODD_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__SLM_XLNA_ODD_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__BQ_GAIN_ODD_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__XLNA_GAIN_EVEN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__LNA_GAIN_EVEN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__GM_GAIN_EVEN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__TIA_GAIN_EVEN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__SLM_XLNA_EVEN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__BQ_GAIN_EVEN_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__XLNA_GAIN_ODD_32___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__XLNA_GAIN_ODD_32___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__LNA_GAIN_ODD_32___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__LNA_GAIN_ODD_32___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__GM_GAIN_ODD_32___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__GM_GAIN_ODD_32___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__TIA_GAIN_ODD_32___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__TIA_GAIN_ODD_32___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__SLM_XLNA_ODD_32___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__SLM_XLNA_ODD_32___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__BQ_GAIN_ODD_32___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__BQ_GAIN_ODD_32___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__XLNA_GAIN_EVEN_32___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__XLNA_GAIN_EVEN_32___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__LNA_GAIN_EVEN_32___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__LNA_GAIN_EVEN_32___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__GM_GAIN_EVEN_32___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__GM_GAIN_EVEN_32___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__TIA_GAIN_EVEN_32___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__TIA_GAIN_EVEN_32___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__SLM_XLNA_EVEN_32___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__SLM_XLNA_EVEN_32___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__BQ_GAIN_EVEN_32___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32__BQ_GAIN_EVEN_32___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_32___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33 (0x005FD084) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__XLNA_GAIN_ODD_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__LNA_GAIN_ODD_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__GM_GAIN_ODD_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__TIA_GAIN_ODD_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__SLM_XLNA_ODD_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__BQ_GAIN_ODD_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__XLNA_GAIN_EVEN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__LNA_GAIN_EVEN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__GM_GAIN_EVEN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__TIA_GAIN_EVEN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__SLM_XLNA_EVEN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__BQ_GAIN_EVEN_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__XLNA_GAIN_ODD_33___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__XLNA_GAIN_ODD_33___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__LNA_GAIN_ODD_33___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__LNA_GAIN_ODD_33___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__GM_GAIN_ODD_33___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__GM_GAIN_ODD_33___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__TIA_GAIN_ODD_33___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__TIA_GAIN_ODD_33___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__SLM_XLNA_ODD_33___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__SLM_XLNA_ODD_33___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__BQ_GAIN_ODD_33___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__BQ_GAIN_ODD_33___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__XLNA_GAIN_EVEN_33___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__XLNA_GAIN_EVEN_33___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__LNA_GAIN_EVEN_33___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__LNA_GAIN_EVEN_33___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__GM_GAIN_EVEN_33___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__GM_GAIN_EVEN_33___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__TIA_GAIN_EVEN_33___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__TIA_GAIN_EVEN_33___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__SLM_XLNA_EVEN_33___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__SLM_XLNA_EVEN_33___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__BQ_GAIN_EVEN_33___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33__BQ_GAIN_EVEN_33___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_33___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34 (0x005FD088) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__XLNA_GAIN_ODD_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__LNA_GAIN_ODD_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__GM_GAIN_ODD_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__TIA_GAIN_ODD_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__SLM_XLNA_ODD_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__BQ_GAIN_ODD_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__XLNA_GAIN_EVEN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__LNA_GAIN_EVEN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__GM_GAIN_EVEN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__TIA_GAIN_EVEN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__SLM_XLNA_EVEN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__BQ_GAIN_EVEN_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__XLNA_GAIN_ODD_34___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__XLNA_GAIN_ODD_34___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__LNA_GAIN_ODD_34___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__LNA_GAIN_ODD_34___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__GM_GAIN_ODD_34___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__GM_GAIN_ODD_34___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__TIA_GAIN_ODD_34___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__TIA_GAIN_ODD_34___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__SLM_XLNA_ODD_34___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__SLM_XLNA_ODD_34___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__BQ_GAIN_ODD_34___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__BQ_GAIN_ODD_34___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__XLNA_GAIN_EVEN_34___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__XLNA_GAIN_EVEN_34___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__LNA_GAIN_EVEN_34___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__LNA_GAIN_EVEN_34___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__GM_GAIN_EVEN_34___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__GM_GAIN_EVEN_34___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__TIA_GAIN_EVEN_34___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__TIA_GAIN_EVEN_34___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__SLM_XLNA_EVEN_34___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__SLM_XLNA_EVEN_34___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__BQ_GAIN_EVEN_34___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34__BQ_GAIN_EVEN_34___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_34___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35 (0x005FD08C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__XLNA_GAIN_ODD_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__LNA_GAIN_ODD_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__GM_GAIN_ODD_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__TIA_GAIN_ODD_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__SLM_XLNA_ODD_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__BQ_GAIN_ODD_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__XLNA_GAIN_EVEN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__LNA_GAIN_EVEN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__GM_GAIN_EVEN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__TIA_GAIN_EVEN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__SLM_XLNA_EVEN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__BQ_GAIN_EVEN_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__XLNA_GAIN_ODD_35___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__XLNA_GAIN_ODD_35___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__LNA_GAIN_ODD_35___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__LNA_GAIN_ODD_35___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__GM_GAIN_ODD_35___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__GM_GAIN_ODD_35___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__TIA_GAIN_ODD_35___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__TIA_GAIN_ODD_35___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__SLM_XLNA_ODD_35___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__SLM_XLNA_ODD_35___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__BQ_GAIN_ODD_35___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__BQ_GAIN_ODD_35___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__XLNA_GAIN_EVEN_35___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__XLNA_GAIN_EVEN_35___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__LNA_GAIN_EVEN_35___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__LNA_GAIN_EVEN_35___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__GM_GAIN_EVEN_35___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__GM_GAIN_EVEN_35___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__TIA_GAIN_EVEN_35___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__TIA_GAIN_EVEN_35___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__SLM_XLNA_EVEN_35___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__SLM_XLNA_EVEN_35___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__BQ_GAIN_EVEN_35___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35__BQ_GAIN_EVEN_35___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_35___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36 (0x005FD090) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__XLNA_GAIN_ODD_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__LNA_GAIN_ODD_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__GM_GAIN_ODD_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__TIA_GAIN_ODD_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__SLM_XLNA_ODD_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__BQ_GAIN_ODD_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__XLNA_GAIN_EVEN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__LNA_GAIN_EVEN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__GM_GAIN_EVEN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__TIA_GAIN_EVEN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__SLM_XLNA_EVEN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__BQ_GAIN_EVEN_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__XLNA_GAIN_ODD_36___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__XLNA_GAIN_ODD_36___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__LNA_GAIN_ODD_36___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__LNA_GAIN_ODD_36___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__GM_GAIN_ODD_36___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__GM_GAIN_ODD_36___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__TIA_GAIN_ODD_36___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__TIA_GAIN_ODD_36___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__SLM_XLNA_ODD_36___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__SLM_XLNA_ODD_36___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__BQ_GAIN_ODD_36___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__BQ_GAIN_ODD_36___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__XLNA_GAIN_EVEN_36___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__XLNA_GAIN_EVEN_36___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__LNA_GAIN_EVEN_36___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__LNA_GAIN_EVEN_36___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__GM_GAIN_EVEN_36___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__GM_GAIN_EVEN_36___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__TIA_GAIN_EVEN_36___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__TIA_GAIN_EVEN_36___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__SLM_XLNA_EVEN_36___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__SLM_XLNA_EVEN_36___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__BQ_GAIN_EVEN_36___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36__BQ_GAIN_EVEN_36___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_36___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37 (0x005FD094) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__XLNA_GAIN_ODD_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__LNA_GAIN_ODD_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__GM_GAIN_ODD_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__TIA_GAIN_ODD_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__SLM_XLNA_ODD_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__BQ_GAIN_ODD_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__XLNA_GAIN_EVEN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__LNA_GAIN_EVEN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__GM_GAIN_EVEN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__TIA_GAIN_EVEN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__SLM_XLNA_EVEN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__BQ_GAIN_EVEN_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__XLNA_GAIN_ODD_37___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__XLNA_GAIN_ODD_37___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__LNA_GAIN_ODD_37___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__LNA_GAIN_ODD_37___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__GM_GAIN_ODD_37___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__GM_GAIN_ODD_37___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__TIA_GAIN_ODD_37___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__TIA_GAIN_ODD_37___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__SLM_XLNA_ODD_37___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__SLM_XLNA_ODD_37___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__BQ_GAIN_ODD_37___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__BQ_GAIN_ODD_37___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__XLNA_GAIN_EVEN_37___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__XLNA_GAIN_EVEN_37___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__LNA_GAIN_EVEN_37___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__LNA_GAIN_EVEN_37___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__GM_GAIN_EVEN_37___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__GM_GAIN_EVEN_37___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__TIA_GAIN_EVEN_37___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__TIA_GAIN_EVEN_37___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__SLM_XLNA_EVEN_37___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__SLM_XLNA_EVEN_37___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__BQ_GAIN_EVEN_37___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37__BQ_GAIN_EVEN_37___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_37___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38 (0x005FD098) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__XLNA_GAIN_ODD_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__LNA_GAIN_ODD_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__GM_GAIN_ODD_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__TIA_GAIN_ODD_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__SLM_XLNA_ODD_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__BQ_GAIN_ODD_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__XLNA_GAIN_EVEN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__LNA_GAIN_EVEN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__GM_GAIN_EVEN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__TIA_GAIN_EVEN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__SLM_XLNA_EVEN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__BQ_GAIN_EVEN_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__XLNA_GAIN_ODD_38___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__XLNA_GAIN_ODD_38___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__LNA_GAIN_ODD_38___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__LNA_GAIN_ODD_38___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__GM_GAIN_ODD_38___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__GM_GAIN_ODD_38___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__TIA_GAIN_ODD_38___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__TIA_GAIN_ODD_38___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__SLM_XLNA_ODD_38___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__SLM_XLNA_ODD_38___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__BQ_GAIN_ODD_38___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__BQ_GAIN_ODD_38___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__XLNA_GAIN_EVEN_38___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__XLNA_GAIN_EVEN_38___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__LNA_GAIN_EVEN_38___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__LNA_GAIN_EVEN_38___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__GM_GAIN_EVEN_38___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__GM_GAIN_EVEN_38___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__TIA_GAIN_EVEN_38___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__TIA_GAIN_EVEN_38___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__SLM_XLNA_EVEN_38___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__SLM_XLNA_EVEN_38___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__BQ_GAIN_EVEN_38___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38__BQ_GAIN_EVEN_38___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_38___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39 (0x005FD09C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__XLNA_GAIN_ODD_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__LNA_GAIN_ODD_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__GM_GAIN_ODD_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__TIA_GAIN_ODD_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__SLM_XLNA_ODD_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__BQ_GAIN_ODD_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__XLNA_GAIN_EVEN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__LNA_GAIN_EVEN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__GM_GAIN_EVEN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__TIA_GAIN_EVEN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__SLM_XLNA_EVEN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__BQ_GAIN_EVEN_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__XLNA_GAIN_ODD_39___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__XLNA_GAIN_ODD_39___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__LNA_GAIN_ODD_39___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__LNA_GAIN_ODD_39___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__GM_GAIN_ODD_39___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__GM_GAIN_ODD_39___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__TIA_GAIN_ODD_39___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__TIA_GAIN_ODD_39___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__SLM_XLNA_ODD_39___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__SLM_XLNA_ODD_39___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__BQ_GAIN_ODD_39___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__BQ_GAIN_ODD_39___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__XLNA_GAIN_EVEN_39___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__XLNA_GAIN_EVEN_39___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__LNA_GAIN_EVEN_39___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__LNA_GAIN_EVEN_39___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__GM_GAIN_EVEN_39___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__GM_GAIN_EVEN_39___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__TIA_GAIN_EVEN_39___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__TIA_GAIN_EVEN_39___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__SLM_XLNA_EVEN_39___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__SLM_XLNA_EVEN_39___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__BQ_GAIN_EVEN_39___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39__BQ_GAIN_EVEN_39___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_39___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40 (0x005FD0A0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__XLNA_GAIN_ODD_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__LNA_GAIN_ODD_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__GM_GAIN_ODD_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__TIA_GAIN_ODD_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__SLM_XLNA_ODD_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__BQ_GAIN_ODD_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__XLNA_GAIN_EVEN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__LNA_GAIN_EVEN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__GM_GAIN_EVEN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__TIA_GAIN_EVEN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__SLM_XLNA_EVEN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__BQ_GAIN_EVEN_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__XLNA_GAIN_ODD_40___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__XLNA_GAIN_ODD_40___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__LNA_GAIN_ODD_40___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__LNA_GAIN_ODD_40___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__GM_GAIN_ODD_40___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__GM_GAIN_ODD_40___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__TIA_GAIN_ODD_40___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__TIA_GAIN_ODD_40___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__SLM_XLNA_ODD_40___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__SLM_XLNA_ODD_40___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__BQ_GAIN_ODD_40___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__BQ_GAIN_ODD_40___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__XLNA_GAIN_EVEN_40___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__XLNA_GAIN_EVEN_40___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__LNA_GAIN_EVEN_40___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__LNA_GAIN_EVEN_40___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__GM_GAIN_EVEN_40___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__GM_GAIN_EVEN_40___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__TIA_GAIN_EVEN_40___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__TIA_GAIN_EVEN_40___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__SLM_XLNA_EVEN_40___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__SLM_XLNA_EVEN_40___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__BQ_GAIN_EVEN_40___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40__BQ_GAIN_EVEN_40___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_40___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41 (0x005FD0A4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__XLNA_GAIN_ODD_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__LNA_GAIN_ODD_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__GM_GAIN_ODD_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__TIA_GAIN_ODD_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__SLM_XLNA_ODD_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__BQ_GAIN_ODD_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__XLNA_GAIN_EVEN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__LNA_GAIN_EVEN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__GM_GAIN_EVEN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__TIA_GAIN_EVEN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__SLM_XLNA_EVEN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__BQ_GAIN_EVEN_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__XLNA_GAIN_ODD_41___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__XLNA_GAIN_ODD_41___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__LNA_GAIN_ODD_41___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__LNA_GAIN_ODD_41___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__GM_GAIN_ODD_41___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__GM_GAIN_ODD_41___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__TIA_GAIN_ODD_41___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__TIA_GAIN_ODD_41___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__SLM_XLNA_ODD_41___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__SLM_XLNA_ODD_41___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__BQ_GAIN_ODD_41___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__BQ_GAIN_ODD_41___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__XLNA_GAIN_EVEN_41___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__XLNA_GAIN_EVEN_41___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__LNA_GAIN_EVEN_41___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__LNA_GAIN_EVEN_41___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__GM_GAIN_EVEN_41___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__GM_GAIN_EVEN_41___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__TIA_GAIN_EVEN_41___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__TIA_GAIN_EVEN_41___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__SLM_XLNA_EVEN_41___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__SLM_XLNA_EVEN_41___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__BQ_GAIN_EVEN_41___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41__BQ_GAIN_EVEN_41___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_41___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42 (0x005FD0A8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__XLNA_GAIN_ODD_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__LNA_GAIN_ODD_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__GM_GAIN_ODD_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__TIA_GAIN_ODD_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__SLM_XLNA_ODD_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__BQ_GAIN_ODD_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__XLNA_GAIN_EVEN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__LNA_GAIN_EVEN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__GM_GAIN_EVEN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__TIA_GAIN_EVEN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__SLM_XLNA_EVEN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__BQ_GAIN_EVEN_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__XLNA_GAIN_ODD_42___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__XLNA_GAIN_ODD_42___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__LNA_GAIN_ODD_42___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__LNA_GAIN_ODD_42___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__GM_GAIN_ODD_42___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__GM_GAIN_ODD_42___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__TIA_GAIN_ODD_42___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__TIA_GAIN_ODD_42___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__SLM_XLNA_ODD_42___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__SLM_XLNA_ODD_42___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__BQ_GAIN_ODD_42___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__BQ_GAIN_ODD_42___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__XLNA_GAIN_EVEN_42___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__XLNA_GAIN_EVEN_42___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__LNA_GAIN_EVEN_42___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__LNA_GAIN_EVEN_42___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__GM_GAIN_EVEN_42___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__GM_GAIN_EVEN_42___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__TIA_GAIN_EVEN_42___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__TIA_GAIN_EVEN_42___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__SLM_XLNA_EVEN_42___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__SLM_XLNA_EVEN_42___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__BQ_GAIN_EVEN_42___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42__BQ_GAIN_EVEN_42___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_42___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43 (0x005FD0AC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__XLNA_GAIN_ODD_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__LNA_GAIN_ODD_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__GM_GAIN_ODD_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__TIA_GAIN_ODD_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__SLM_XLNA_ODD_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__BQ_GAIN_ODD_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__XLNA_GAIN_EVEN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__LNA_GAIN_EVEN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__GM_GAIN_EVEN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__TIA_GAIN_EVEN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__SLM_XLNA_EVEN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__BQ_GAIN_EVEN_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__XLNA_GAIN_ODD_43___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__XLNA_GAIN_ODD_43___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__LNA_GAIN_ODD_43___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__LNA_GAIN_ODD_43___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__GM_GAIN_ODD_43___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__GM_GAIN_ODD_43___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__TIA_GAIN_ODD_43___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__TIA_GAIN_ODD_43___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__SLM_XLNA_ODD_43___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__SLM_XLNA_ODD_43___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__BQ_GAIN_ODD_43___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__BQ_GAIN_ODD_43___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__XLNA_GAIN_EVEN_43___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__XLNA_GAIN_EVEN_43___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__LNA_GAIN_EVEN_43___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__LNA_GAIN_EVEN_43___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__GM_GAIN_EVEN_43___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__GM_GAIN_EVEN_43___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__TIA_GAIN_EVEN_43___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__TIA_GAIN_EVEN_43___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__SLM_XLNA_EVEN_43___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__SLM_XLNA_EVEN_43___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__BQ_GAIN_EVEN_43___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43__BQ_GAIN_EVEN_43___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_43___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44 (0x005FD0B0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__XLNA_GAIN_ODD_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__LNA_GAIN_ODD_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__GM_GAIN_ODD_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__TIA_GAIN_ODD_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__SLM_XLNA_ODD_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__BQ_GAIN_ODD_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__XLNA_GAIN_EVEN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__LNA_GAIN_EVEN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__GM_GAIN_EVEN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__TIA_GAIN_EVEN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__SLM_XLNA_EVEN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__BQ_GAIN_EVEN_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__XLNA_GAIN_ODD_44___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__XLNA_GAIN_ODD_44___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__LNA_GAIN_ODD_44___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__LNA_GAIN_ODD_44___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__GM_GAIN_ODD_44___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__GM_GAIN_ODD_44___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__TIA_GAIN_ODD_44___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__TIA_GAIN_ODD_44___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__SLM_XLNA_ODD_44___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__SLM_XLNA_ODD_44___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__BQ_GAIN_ODD_44___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__BQ_GAIN_ODD_44___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__XLNA_GAIN_EVEN_44___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__XLNA_GAIN_EVEN_44___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__LNA_GAIN_EVEN_44___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__LNA_GAIN_EVEN_44___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__GM_GAIN_EVEN_44___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__GM_GAIN_EVEN_44___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__TIA_GAIN_EVEN_44___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__TIA_GAIN_EVEN_44___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__SLM_XLNA_EVEN_44___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__SLM_XLNA_EVEN_44___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__BQ_GAIN_EVEN_44___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44__BQ_GAIN_EVEN_44___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_44___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45 (0x005FD0B4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__XLNA_GAIN_ODD_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__LNA_GAIN_ODD_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__GM_GAIN_ODD_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__TIA_GAIN_ODD_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__SLM_XLNA_ODD_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__BQ_GAIN_ODD_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__XLNA_GAIN_EVEN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__LNA_GAIN_EVEN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__GM_GAIN_EVEN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__TIA_GAIN_EVEN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__SLM_XLNA_EVEN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__BQ_GAIN_EVEN_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__XLNA_GAIN_ODD_45___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__XLNA_GAIN_ODD_45___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__LNA_GAIN_ODD_45___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__LNA_GAIN_ODD_45___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__GM_GAIN_ODD_45___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__GM_GAIN_ODD_45___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__TIA_GAIN_ODD_45___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__TIA_GAIN_ODD_45___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__SLM_XLNA_ODD_45___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__SLM_XLNA_ODD_45___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__BQ_GAIN_ODD_45___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__BQ_GAIN_ODD_45___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__XLNA_GAIN_EVEN_45___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__XLNA_GAIN_EVEN_45___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__LNA_GAIN_EVEN_45___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__LNA_GAIN_EVEN_45___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__GM_GAIN_EVEN_45___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__GM_GAIN_EVEN_45___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__TIA_GAIN_EVEN_45___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__TIA_GAIN_EVEN_45___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__SLM_XLNA_EVEN_45___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__SLM_XLNA_EVEN_45___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__BQ_GAIN_EVEN_45___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45__BQ_GAIN_EVEN_45___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_45___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46 (0x005FD0B8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__XLNA_GAIN_ODD_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__LNA_GAIN_ODD_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__GM_GAIN_ODD_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__TIA_GAIN_ODD_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__SLM_XLNA_ODD_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__BQ_GAIN_ODD_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__XLNA_GAIN_EVEN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__LNA_GAIN_EVEN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__GM_GAIN_EVEN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__TIA_GAIN_EVEN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__SLM_XLNA_EVEN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__BQ_GAIN_EVEN_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__XLNA_GAIN_ODD_46___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__XLNA_GAIN_ODD_46___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__LNA_GAIN_ODD_46___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__LNA_GAIN_ODD_46___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__GM_GAIN_ODD_46___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__GM_GAIN_ODD_46___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__TIA_GAIN_ODD_46___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__TIA_GAIN_ODD_46___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__SLM_XLNA_ODD_46___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__SLM_XLNA_ODD_46___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__BQ_GAIN_ODD_46___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__BQ_GAIN_ODD_46___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__XLNA_GAIN_EVEN_46___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__XLNA_GAIN_EVEN_46___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__LNA_GAIN_EVEN_46___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__LNA_GAIN_EVEN_46___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__GM_GAIN_EVEN_46___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__GM_GAIN_EVEN_46___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__TIA_GAIN_EVEN_46___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__TIA_GAIN_EVEN_46___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__SLM_XLNA_EVEN_46___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__SLM_XLNA_EVEN_46___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__BQ_GAIN_EVEN_46___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46__BQ_GAIN_EVEN_46___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_46___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47 (0x005FD0BC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__XLNA_GAIN_ODD_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__LNA_GAIN_ODD_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__GM_GAIN_ODD_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__TIA_GAIN_ODD_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__SLM_XLNA_ODD_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__BQ_GAIN_ODD_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__XLNA_GAIN_EVEN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__LNA_GAIN_EVEN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__GM_GAIN_EVEN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__TIA_GAIN_EVEN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__SLM_XLNA_EVEN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__BQ_GAIN_EVEN_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__XLNA_GAIN_ODD_47___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__XLNA_GAIN_ODD_47___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__LNA_GAIN_ODD_47___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__LNA_GAIN_ODD_47___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__GM_GAIN_ODD_47___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__GM_GAIN_ODD_47___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__TIA_GAIN_ODD_47___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__TIA_GAIN_ODD_47___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__SLM_XLNA_ODD_47___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__SLM_XLNA_ODD_47___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__BQ_GAIN_ODD_47___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__BQ_GAIN_ODD_47___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__XLNA_GAIN_EVEN_47___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__XLNA_GAIN_EVEN_47___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__LNA_GAIN_EVEN_47___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__LNA_GAIN_EVEN_47___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__GM_GAIN_EVEN_47___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__GM_GAIN_EVEN_47___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__TIA_GAIN_EVEN_47___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__TIA_GAIN_EVEN_47___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__SLM_XLNA_EVEN_47___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__SLM_XLNA_EVEN_47___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__BQ_GAIN_EVEN_47___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47__BQ_GAIN_EVEN_47___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_47___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48 (0x005FD0C0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__XLNA_GAIN_ODD_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__LNA_GAIN_ODD_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__GM_GAIN_ODD_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__TIA_GAIN_ODD_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__SLM_XLNA_ODD_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__BQ_GAIN_ODD_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__XLNA_GAIN_EVEN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__LNA_GAIN_EVEN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__GM_GAIN_EVEN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__TIA_GAIN_EVEN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__SLM_XLNA_EVEN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__BQ_GAIN_EVEN_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__XLNA_GAIN_ODD_48___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__XLNA_GAIN_ODD_48___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__LNA_GAIN_ODD_48___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__LNA_GAIN_ODD_48___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__GM_GAIN_ODD_48___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__GM_GAIN_ODD_48___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__TIA_GAIN_ODD_48___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__TIA_GAIN_ODD_48___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__SLM_XLNA_ODD_48___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__SLM_XLNA_ODD_48___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__BQ_GAIN_ODD_48___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__BQ_GAIN_ODD_48___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__XLNA_GAIN_EVEN_48___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__XLNA_GAIN_EVEN_48___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__LNA_GAIN_EVEN_48___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__LNA_GAIN_EVEN_48___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__GM_GAIN_EVEN_48___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__GM_GAIN_EVEN_48___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__TIA_GAIN_EVEN_48___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__TIA_GAIN_EVEN_48___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__SLM_XLNA_EVEN_48___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__SLM_XLNA_EVEN_48___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__BQ_GAIN_EVEN_48___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48__BQ_GAIN_EVEN_48___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_48___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49 (0x005FD0C4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__XLNA_GAIN_ODD_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__LNA_GAIN_ODD_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__GM_GAIN_ODD_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__TIA_GAIN_ODD_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__SLM_XLNA_ODD_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__BQ_GAIN_ODD_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__XLNA_GAIN_EVEN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__LNA_GAIN_EVEN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__GM_GAIN_EVEN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__TIA_GAIN_EVEN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__SLM_XLNA_EVEN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__BQ_GAIN_EVEN_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__XLNA_GAIN_ODD_49___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__XLNA_GAIN_ODD_49___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__LNA_GAIN_ODD_49___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__LNA_GAIN_ODD_49___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__GM_GAIN_ODD_49___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__GM_GAIN_ODD_49___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__TIA_GAIN_ODD_49___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__TIA_GAIN_ODD_49___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__SLM_XLNA_ODD_49___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__SLM_XLNA_ODD_49___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__BQ_GAIN_ODD_49___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__BQ_GAIN_ODD_49___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__XLNA_GAIN_EVEN_49___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__XLNA_GAIN_EVEN_49___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__LNA_GAIN_EVEN_49___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__LNA_GAIN_EVEN_49___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__GM_GAIN_EVEN_49___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__GM_GAIN_EVEN_49___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__TIA_GAIN_EVEN_49___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__TIA_GAIN_EVEN_49___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__SLM_XLNA_EVEN_49___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__SLM_XLNA_EVEN_49___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__BQ_GAIN_EVEN_49___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49__BQ_GAIN_EVEN_49___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_49___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50 (0x005FD0C8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__XLNA_GAIN_ODD_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__LNA_GAIN_ODD_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__GM_GAIN_ODD_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__TIA_GAIN_ODD_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__SLM_XLNA_ODD_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__BQ_GAIN_ODD_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__XLNA_GAIN_EVEN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__LNA_GAIN_EVEN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__GM_GAIN_EVEN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__TIA_GAIN_EVEN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__SLM_XLNA_EVEN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__BQ_GAIN_EVEN_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__XLNA_GAIN_ODD_50___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__XLNA_GAIN_ODD_50___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__LNA_GAIN_ODD_50___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__LNA_GAIN_ODD_50___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__GM_GAIN_ODD_50___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__GM_GAIN_ODD_50___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__TIA_GAIN_ODD_50___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__TIA_GAIN_ODD_50___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__SLM_XLNA_ODD_50___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__SLM_XLNA_ODD_50___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__BQ_GAIN_ODD_50___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__BQ_GAIN_ODD_50___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__XLNA_GAIN_EVEN_50___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__XLNA_GAIN_EVEN_50___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__LNA_GAIN_EVEN_50___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__LNA_GAIN_EVEN_50___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__GM_GAIN_EVEN_50___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__GM_GAIN_EVEN_50___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__TIA_GAIN_EVEN_50___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__TIA_GAIN_EVEN_50___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__SLM_XLNA_EVEN_50___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__SLM_XLNA_EVEN_50___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__BQ_GAIN_EVEN_50___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50__BQ_GAIN_EVEN_50___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_50___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51 (0x005FD0CC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__XLNA_GAIN_ODD_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__LNA_GAIN_ODD_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__GM_GAIN_ODD_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__TIA_GAIN_ODD_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__SLM_XLNA_ODD_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__BQ_GAIN_ODD_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__XLNA_GAIN_EVEN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__LNA_GAIN_EVEN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__GM_GAIN_EVEN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__TIA_GAIN_EVEN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__SLM_XLNA_EVEN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__BQ_GAIN_EVEN_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__XLNA_GAIN_ODD_51___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__XLNA_GAIN_ODD_51___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__LNA_GAIN_ODD_51___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__LNA_GAIN_ODD_51___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__GM_GAIN_ODD_51___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__GM_GAIN_ODD_51___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__TIA_GAIN_ODD_51___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__TIA_GAIN_ODD_51___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__SLM_XLNA_ODD_51___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__SLM_XLNA_ODD_51___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__BQ_GAIN_ODD_51___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__BQ_GAIN_ODD_51___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__XLNA_GAIN_EVEN_51___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__XLNA_GAIN_EVEN_51___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__LNA_GAIN_EVEN_51___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__LNA_GAIN_EVEN_51___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__GM_GAIN_EVEN_51___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__GM_GAIN_EVEN_51___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__TIA_GAIN_EVEN_51___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__TIA_GAIN_EVEN_51___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__SLM_XLNA_EVEN_51___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__SLM_XLNA_EVEN_51___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__BQ_GAIN_EVEN_51___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51__BQ_GAIN_EVEN_51___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_51___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52 (0x005FD0D0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__XLNA_GAIN_ODD_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__LNA_GAIN_ODD_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__GM_GAIN_ODD_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__TIA_GAIN_ODD_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__SLM_XLNA_ODD_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__BQ_GAIN_ODD_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__XLNA_GAIN_EVEN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__LNA_GAIN_EVEN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__GM_GAIN_EVEN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__TIA_GAIN_EVEN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__SLM_XLNA_EVEN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__BQ_GAIN_EVEN_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__XLNA_GAIN_ODD_52___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__XLNA_GAIN_ODD_52___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__LNA_GAIN_ODD_52___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__LNA_GAIN_ODD_52___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__GM_GAIN_ODD_52___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__GM_GAIN_ODD_52___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__TIA_GAIN_ODD_52___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__TIA_GAIN_ODD_52___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__SLM_XLNA_ODD_52___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__SLM_XLNA_ODD_52___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__BQ_GAIN_ODD_52___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__BQ_GAIN_ODD_52___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__XLNA_GAIN_EVEN_52___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__XLNA_GAIN_EVEN_52___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__LNA_GAIN_EVEN_52___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__LNA_GAIN_EVEN_52___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__GM_GAIN_EVEN_52___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__GM_GAIN_EVEN_52___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__TIA_GAIN_EVEN_52___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__TIA_GAIN_EVEN_52___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__SLM_XLNA_EVEN_52___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__SLM_XLNA_EVEN_52___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__BQ_GAIN_EVEN_52___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52__BQ_GAIN_EVEN_52___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_52___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53 (0x005FD0D4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__XLNA_GAIN_ODD_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__LNA_GAIN_ODD_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__GM_GAIN_ODD_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__TIA_GAIN_ODD_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__SLM_XLNA_ODD_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__BQ_GAIN_ODD_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__XLNA_GAIN_EVEN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__LNA_GAIN_EVEN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__GM_GAIN_EVEN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__TIA_GAIN_EVEN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__SLM_XLNA_EVEN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__BQ_GAIN_EVEN_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__XLNA_GAIN_ODD_53___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__XLNA_GAIN_ODD_53___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__LNA_GAIN_ODD_53___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__LNA_GAIN_ODD_53___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__GM_GAIN_ODD_53___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__GM_GAIN_ODD_53___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__TIA_GAIN_ODD_53___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__TIA_GAIN_ODD_53___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__SLM_XLNA_ODD_53___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__SLM_XLNA_ODD_53___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__BQ_GAIN_ODD_53___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__BQ_GAIN_ODD_53___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__XLNA_GAIN_EVEN_53___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__XLNA_GAIN_EVEN_53___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__LNA_GAIN_EVEN_53___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__LNA_GAIN_EVEN_53___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__GM_GAIN_EVEN_53___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__GM_GAIN_EVEN_53___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__TIA_GAIN_EVEN_53___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__TIA_GAIN_EVEN_53___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__SLM_XLNA_EVEN_53___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__SLM_XLNA_EVEN_53___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__BQ_GAIN_EVEN_53___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53__BQ_GAIN_EVEN_53___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_53___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54 (0x005FD0D8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__XLNA_GAIN_ODD_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__LNA_GAIN_ODD_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__GM_GAIN_ODD_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__TIA_GAIN_ODD_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__SLM_XLNA_ODD_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__BQ_GAIN_ODD_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__XLNA_GAIN_EVEN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__LNA_GAIN_EVEN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__GM_GAIN_EVEN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__TIA_GAIN_EVEN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__SLM_XLNA_EVEN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__BQ_GAIN_EVEN_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__XLNA_GAIN_ODD_54___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__XLNA_GAIN_ODD_54___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__LNA_GAIN_ODD_54___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__LNA_GAIN_ODD_54___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__GM_GAIN_ODD_54___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__GM_GAIN_ODD_54___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__TIA_GAIN_ODD_54___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__TIA_GAIN_ODD_54___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__SLM_XLNA_ODD_54___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__SLM_XLNA_ODD_54___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__BQ_GAIN_ODD_54___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__BQ_GAIN_ODD_54___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__XLNA_GAIN_EVEN_54___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__XLNA_GAIN_EVEN_54___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__LNA_GAIN_EVEN_54___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__LNA_GAIN_EVEN_54___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__GM_GAIN_EVEN_54___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__GM_GAIN_EVEN_54___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__TIA_GAIN_EVEN_54___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__TIA_GAIN_EVEN_54___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__SLM_XLNA_EVEN_54___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__SLM_XLNA_EVEN_54___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__BQ_GAIN_EVEN_54___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54__BQ_GAIN_EVEN_54___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_54___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55 (0x005FD0DC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__XLNA_GAIN_ODD_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__LNA_GAIN_ODD_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__GM_GAIN_ODD_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__TIA_GAIN_ODD_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__SLM_XLNA_ODD_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__BQ_GAIN_ODD_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__XLNA_GAIN_EVEN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__LNA_GAIN_EVEN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__GM_GAIN_EVEN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__TIA_GAIN_EVEN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__SLM_XLNA_EVEN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__BQ_GAIN_EVEN_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__XLNA_GAIN_ODD_55___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__XLNA_GAIN_ODD_55___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__LNA_GAIN_ODD_55___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__LNA_GAIN_ODD_55___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__GM_GAIN_ODD_55___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__GM_GAIN_ODD_55___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__TIA_GAIN_ODD_55___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__TIA_GAIN_ODD_55___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__SLM_XLNA_ODD_55___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__SLM_XLNA_ODD_55___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__BQ_GAIN_ODD_55___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__BQ_GAIN_ODD_55___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__XLNA_GAIN_EVEN_55___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__XLNA_GAIN_EVEN_55___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__LNA_GAIN_EVEN_55___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__LNA_GAIN_EVEN_55___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__GM_GAIN_EVEN_55___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__GM_GAIN_EVEN_55___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__TIA_GAIN_EVEN_55___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__TIA_GAIN_EVEN_55___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__SLM_XLNA_EVEN_55___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__SLM_XLNA_EVEN_55___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__BQ_GAIN_EVEN_55___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55__BQ_GAIN_EVEN_55___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_55___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56 (0x005FD0E0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__XLNA_GAIN_ODD_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__LNA_GAIN_ODD_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__GM_GAIN_ODD_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__TIA_GAIN_ODD_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__SLM_XLNA_ODD_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__BQ_GAIN_ODD_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__XLNA_GAIN_EVEN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__LNA_GAIN_EVEN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__GM_GAIN_EVEN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__TIA_GAIN_EVEN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__SLM_XLNA_EVEN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__BQ_GAIN_EVEN_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__XLNA_GAIN_ODD_56___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__XLNA_GAIN_ODD_56___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__LNA_GAIN_ODD_56___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__LNA_GAIN_ODD_56___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__GM_GAIN_ODD_56___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__GM_GAIN_ODD_56___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__TIA_GAIN_ODD_56___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__TIA_GAIN_ODD_56___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__SLM_XLNA_ODD_56___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__SLM_XLNA_ODD_56___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__BQ_GAIN_ODD_56___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__BQ_GAIN_ODD_56___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__XLNA_GAIN_EVEN_56___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__XLNA_GAIN_EVEN_56___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__LNA_GAIN_EVEN_56___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__LNA_GAIN_EVEN_56___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__GM_GAIN_EVEN_56___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__GM_GAIN_EVEN_56___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__TIA_GAIN_EVEN_56___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__TIA_GAIN_EVEN_56___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__SLM_XLNA_EVEN_56___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__SLM_XLNA_EVEN_56___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__BQ_GAIN_EVEN_56___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56__BQ_GAIN_EVEN_56___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_56___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57 (0x005FD0E4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__XLNA_GAIN_ODD_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__LNA_GAIN_ODD_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__GM_GAIN_ODD_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__TIA_GAIN_ODD_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__SLM_XLNA_ODD_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__BQ_GAIN_ODD_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__XLNA_GAIN_EVEN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__LNA_GAIN_EVEN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__GM_GAIN_EVEN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__TIA_GAIN_EVEN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__SLM_XLNA_EVEN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__BQ_GAIN_EVEN_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__XLNA_GAIN_ODD_57___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__XLNA_GAIN_ODD_57___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__LNA_GAIN_ODD_57___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__LNA_GAIN_ODD_57___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__GM_GAIN_ODD_57___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__GM_GAIN_ODD_57___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__TIA_GAIN_ODD_57___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__TIA_GAIN_ODD_57___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__SLM_XLNA_ODD_57___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__SLM_XLNA_ODD_57___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__BQ_GAIN_ODD_57___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__BQ_GAIN_ODD_57___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__XLNA_GAIN_EVEN_57___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__XLNA_GAIN_EVEN_57___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__LNA_GAIN_EVEN_57___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__LNA_GAIN_EVEN_57___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__GM_GAIN_EVEN_57___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__GM_GAIN_EVEN_57___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__TIA_GAIN_EVEN_57___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__TIA_GAIN_EVEN_57___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__SLM_XLNA_EVEN_57___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__SLM_XLNA_EVEN_57___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__BQ_GAIN_EVEN_57___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57__BQ_GAIN_EVEN_57___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_57___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58 (0x005FD0E8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__XLNA_GAIN_ODD_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__LNA_GAIN_ODD_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__GM_GAIN_ODD_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__TIA_GAIN_ODD_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__SLM_XLNA_ODD_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__BQ_GAIN_ODD_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__XLNA_GAIN_EVEN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__LNA_GAIN_EVEN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__GM_GAIN_EVEN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__TIA_GAIN_EVEN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__SLM_XLNA_EVEN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__BQ_GAIN_EVEN_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__XLNA_GAIN_ODD_58___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__XLNA_GAIN_ODD_58___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__LNA_GAIN_ODD_58___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__LNA_GAIN_ODD_58___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__GM_GAIN_ODD_58___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__GM_GAIN_ODD_58___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__TIA_GAIN_ODD_58___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__TIA_GAIN_ODD_58___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__SLM_XLNA_ODD_58___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__SLM_XLNA_ODD_58___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__BQ_GAIN_ODD_58___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__BQ_GAIN_ODD_58___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__XLNA_GAIN_EVEN_58___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__XLNA_GAIN_EVEN_58___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__LNA_GAIN_EVEN_58___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__LNA_GAIN_EVEN_58___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__GM_GAIN_EVEN_58___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__GM_GAIN_EVEN_58___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__TIA_GAIN_EVEN_58___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__TIA_GAIN_EVEN_58___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__SLM_XLNA_EVEN_58___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__SLM_XLNA_EVEN_58___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__BQ_GAIN_EVEN_58___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58__BQ_GAIN_EVEN_58___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_58___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59 (0x005FD0EC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__XLNA_GAIN_ODD_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__LNA_GAIN_ODD_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__GM_GAIN_ODD_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__TIA_GAIN_ODD_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__SLM_XLNA_ODD_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__BQ_GAIN_ODD_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__XLNA_GAIN_EVEN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__LNA_GAIN_EVEN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__GM_GAIN_EVEN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__TIA_GAIN_EVEN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__SLM_XLNA_EVEN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__BQ_GAIN_EVEN_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__XLNA_GAIN_ODD_59___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__XLNA_GAIN_ODD_59___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__LNA_GAIN_ODD_59___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__LNA_GAIN_ODD_59___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__GM_GAIN_ODD_59___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__GM_GAIN_ODD_59___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__TIA_GAIN_ODD_59___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__TIA_GAIN_ODD_59___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__SLM_XLNA_ODD_59___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__SLM_XLNA_ODD_59___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__BQ_GAIN_ODD_59___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__BQ_GAIN_ODD_59___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__XLNA_GAIN_EVEN_59___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__XLNA_GAIN_EVEN_59___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__LNA_GAIN_EVEN_59___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__LNA_GAIN_EVEN_59___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__GM_GAIN_EVEN_59___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__GM_GAIN_EVEN_59___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__TIA_GAIN_EVEN_59___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__TIA_GAIN_EVEN_59___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__SLM_XLNA_EVEN_59___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__SLM_XLNA_EVEN_59___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__BQ_GAIN_EVEN_59___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59__BQ_GAIN_EVEN_59___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_59___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60 (0x005FD0F0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__XLNA_GAIN_ODD_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__LNA_GAIN_ODD_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__GM_GAIN_ODD_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__TIA_GAIN_ODD_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__SLM_XLNA_ODD_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__BQ_GAIN_ODD_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__XLNA_GAIN_EVEN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__LNA_GAIN_EVEN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__GM_GAIN_EVEN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__TIA_GAIN_EVEN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__SLM_XLNA_EVEN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__BQ_GAIN_EVEN_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__XLNA_GAIN_ODD_60___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__XLNA_GAIN_ODD_60___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__LNA_GAIN_ODD_60___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__LNA_GAIN_ODD_60___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__GM_GAIN_ODD_60___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__GM_GAIN_ODD_60___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__TIA_GAIN_ODD_60___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__TIA_GAIN_ODD_60___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__SLM_XLNA_ODD_60___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__SLM_XLNA_ODD_60___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__BQ_GAIN_ODD_60___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__BQ_GAIN_ODD_60___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__XLNA_GAIN_EVEN_60___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__XLNA_GAIN_EVEN_60___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__LNA_GAIN_EVEN_60___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__LNA_GAIN_EVEN_60___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__GM_GAIN_EVEN_60___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__GM_GAIN_EVEN_60___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__TIA_GAIN_EVEN_60___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__TIA_GAIN_EVEN_60___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__SLM_XLNA_EVEN_60___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__SLM_XLNA_EVEN_60___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__BQ_GAIN_EVEN_60___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60__BQ_GAIN_EVEN_60___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_60___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61 (0x005FD0F4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__XLNA_GAIN_ODD_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__LNA_GAIN_ODD_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__GM_GAIN_ODD_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__TIA_GAIN_ODD_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__SLM_XLNA_ODD_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__BQ_GAIN_ODD_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__XLNA_GAIN_EVEN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__LNA_GAIN_EVEN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__GM_GAIN_EVEN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__TIA_GAIN_EVEN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__SLM_XLNA_EVEN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__BQ_GAIN_EVEN_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__XLNA_GAIN_ODD_61___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__XLNA_GAIN_ODD_61___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__LNA_GAIN_ODD_61___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__LNA_GAIN_ODD_61___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__GM_GAIN_ODD_61___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__GM_GAIN_ODD_61___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__TIA_GAIN_ODD_61___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__TIA_GAIN_ODD_61___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__SLM_XLNA_ODD_61___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__SLM_XLNA_ODD_61___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__BQ_GAIN_ODD_61___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__BQ_GAIN_ODD_61___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__XLNA_GAIN_EVEN_61___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__XLNA_GAIN_EVEN_61___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__LNA_GAIN_EVEN_61___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__LNA_GAIN_EVEN_61___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__GM_GAIN_EVEN_61___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__GM_GAIN_EVEN_61___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__TIA_GAIN_EVEN_61___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__TIA_GAIN_EVEN_61___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__SLM_XLNA_EVEN_61___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__SLM_XLNA_EVEN_61___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__BQ_GAIN_EVEN_61___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61__BQ_GAIN_EVEN_61___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_61___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62 (0x005FD0F8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__XLNA_GAIN_ODD_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__LNA_GAIN_ODD_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__GM_GAIN_ODD_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__TIA_GAIN_ODD_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__SLM_XLNA_ODD_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__BQ_GAIN_ODD_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__XLNA_GAIN_EVEN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__LNA_GAIN_EVEN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__GM_GAIN_EVEN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__TIA_GAIN_EVEN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__SLM_XLNA_EVEN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__BQ_GAIN_EVEN_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__XLNA_GAIN_ODD_62___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__XLNA_GAIN_ODD_62___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__LNA_GAIN_ODD_62___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__LNA_GAIN_ODD_62___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__GM_GAIN_ODD_62___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__GM_GAIN_ODD_62___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__TIA_GAIN_ODD_62___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__TIA_GAIN_ODD_62___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__SLM_XLNA_ODD_62___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__SLM_XLNA_ODD_62___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__BQ_GAIN_ODD_62___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__BQ_GAIN_ODD_62___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__XLNA_GAIN_EVEN_62___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__XLNA_GAIN_EVEN_62___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__LNA_GAIN_EVEN_62___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__LNA_GAIN_EVEN_62___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__GM_GAIN_EVEN_62___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__GM_GAIN_EVEN_62___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__TIA_GAIN_EVEN_62___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__TIA_GAIN_EVEN_62___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__SLM_XLNA_EVEN_62___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__SLM_XLNA_EVEN_62___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__BQ_GAIN_EVEN_62___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62__BQ_GAIN_EVEN_62___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_62___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63 (0x005FD0FC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__XLNA_GAIN_ODD_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__LNA_GAIN_ODD_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__GM_GAIN_ODD_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__TIA_GAIN_ODD_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__SLM_XLNA_ODD_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__BQ_GAIN_ODD_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__XLNA_GAIN_EVEN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__LNA_GAIN_EVEN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__GM_GAIN_EVEN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__TIA_GAIN_EVEN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__SLM_XLNA_EVEN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__BQ_GAIN_EVEN_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__XLNA_GAIN_ODD_63___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__XLNA_GAIN_ODD_63___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__LNA_GAIN_ODD_63___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__LNA_GAIN_ODD_63___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__GM_GAIN_ODD_63___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__GM_GAIN_ODD_63___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__TIA_GAIN_ODD_63___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__TIA_GAIN_ODD_63___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__SLM_XLNA_ODD_63___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__SLM_XLNA_ODD_63___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__BQ_GAIN_ODD_63___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__BQ_GAIN_ODD_63___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__XLNA_GAIN_EVEN_63___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__XLNA_GAIN_EVEN_63___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__LNA_GAIN_EVEN_63___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__LNA_GAIN_EVEN_63___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__GM_GAIN_EVEN_63___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__GM_GAIN_EVEN_63___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__TIA_GAIN_EVEN_63___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__TIA_GAIN_EVEN_63___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__SLM_XLNA_EVEN_63___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__SLM_XLNA_EVEN_63___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__BQ_GAIN_EVEN_63___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63__BQ_GAIN_EVEN_63___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_63___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64 (0x005FD100) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__XLNA_GAIN_ODD_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__LNA_GAIN_ODD_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__GM_GAIN_ODD_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__TIA_GAIN_ODD_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__SLM_XLNA_ODD_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__BQ_GAIN_ODD_64___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__XLNA_GAIN_EVEN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__LNA_GAIN_EVEN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__GM_GAIN_EVEN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__TIA_GAIN_EVEN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__SLM_XLNA_EVEN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__BQ_GAIN_EVEN_64___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__XLNA_GAIN_ODD_64___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__XLNA_GAIN_ODD_64___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__LNA_GAIN_ODD_64___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__LNA_GAIN_ODD_64___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__GM_GAIN_ODD_64___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__GM_GAIN_ODD_64___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__TIA_GAIN_ODD_64___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__TIA_GAIN_ODD_64___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__SLM_XLNA_ODD_64___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__SLM_XLNA_ODD_64___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__BQ_GAIN_ODD_64___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__BQ_GAIN_ODD_64___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__XLNA_GAIN_EVEN_64___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__XLNA_GAIN_EVEN_64___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__LNA_GAIN_EVEN_64___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__LNA_GAIN_EVEN_64___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__GM_GAIN_EVEN_64___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__GM_GAIN_EVEN_64___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__TIA_GAIN_EVEN_64___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__TIA_GAIN_EVEN_64___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__SLM_XLNA_EVEN_64___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__SLM_XLNA_EVEN_64___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__BQ_GAIN_EVEN_64___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64__BQ_GAIN_EVEN_64___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_64___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65 (0x005FD104) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__XLNA_GAIN_ODD_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__LNA_GAIN_ODD_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__GM_GAIN_ODD_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__TIA_GAIN_ODD_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__SLM_XLNA_ODD_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__BQ_GAIN_ODD_65___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__XLNA_GAIN_EVEN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__LNA_GAIN_EVEN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__GM_GAIN_EVEN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__TIA_GAIN_EVEN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__SLM_XLNA_EVEN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__BQ_GAIN_EVEN_65___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__XLNA_GAIN_ODD_65___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__XLNA_GAIN_ODD_65___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__LNA_GAIN_ODD_65___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__LNA_GAIN_ODD_65___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__GM_GAIN_ODD_65___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__GM_GAIN_ODD_65___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__TIA_GAIN_ODD_65___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__TIA_GAIN_ODD_65___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__SLM_XLNA_ODD_65___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__SLM_XLNA_ODD_65___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__BQ_GAIN_ODD_65___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__BQ_GAIN_ODD_65___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__XLNA_GAIN_EVEN_65___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__XLNA_GAIN_EVEN_65___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__LNA_GAIN_EVEN_65___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__LNA_GAIN_EVEN_65___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__GM_GAIN_EVEN_65___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__GM_GAIN_EVEN_65___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__TIA_GAIN_EVEN_65___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__TIA_GAIN_EVEN_65___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__SLM_XLNA_EVEN_65___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__SLM_XLNA_EVEN_65___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__BQ_GAIN_EVEN_65___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65__BQ_GAIN_EVEN_65___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_65___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66 (0x005FD108) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__XLNA_GAIN_ODD_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__LNA_GAIN_ODD_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__GM_GAIN_ODD_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__TIA_GAIN_ODD_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__SLM_XLNA_ODD_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__BQ_GAIN_ODD_66___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__XLNA_GAIN_EVEN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__LNA_GAIN_EVEN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__GM_GAIN_EVEN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__TIA_GAIN_EVEN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__SLM_XLNA_EVEN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__BQ_GAIN_EVEN_66___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__XLNA_GAIN_ODD_66___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__XLNA_GAIN_ODD_66___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__LNA_GAIN_ODD_66___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__LNA_GAIN_ODD_66___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__GM_GAIN_ODD_66___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__GM_GAIN_ODD_66___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__TIA_GAIN_ODD_66___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__TIA_GAIN_ODD_66___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__SLM_XLNA_ODD_66___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__SLM_XLNA_ODD_66___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__BQ_GAIN_ODD_66___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__BQ_GAIN_ODD_66___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__XLNA_GAIN_EVEN_66___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__XLNA_GAIN_EVEN_66___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__LNA_GAIN_EVEN_66___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__LNA_GAIN_EVEN_66___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__GM_GAIN_EVEN_66___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__GM_GAIN_EVEN_66___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__TIA_GAIN_EVEN_66___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__TIA_GAIN_EVEN_66___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__SLM_XLNA_EVEN_66___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__SLM_XLNA_EVEN_66___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__BQ_GAIN_EVEN_66___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66__BQ_GAIN_EVEN_66___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_66___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67 (0x005FD10C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__XLNA_GAIN_ODD_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__LNA_GAIN_ODD_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__GM_GAIN_ODD_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__TIA_GAIN_ODD_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__SLM_XLNA_ODD_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__BQ_GAIN_ODD_67___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__XLNA_GAIN_EVEN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__LNA_GAIN_EVEN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__GM_GAIN_EVEN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__TIA_GAIN_EVEN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__SLM_XLNA_EVEN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__BQ_GAIN_EVEN_67___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__XLNA_GAIN_ODD_67___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__XLNA_GAIN_ODD_67___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__LNA_GAIN_ODD_67___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__LNA_GAIN_ODD_67___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__GM_GAIN_ODD_67___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__GM_GAIN_ODD_67___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__TIA_GAIN_ODD_67___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__TIA_GAIN_ODD_67___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__SLM_XLNA_ODD_67___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__SLM_XLNA_ODD_67___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__BQ_GAIN_ODD_67___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__BQ_GAIN_ODD_67___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__XLNA_GAIN_EVEN_67___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__XLNA_GAIN_EVEN_67___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__LNA_GAIN_EVEN_67___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__LNA_GAIN_EVEN_67___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__GM_GAIN_EVEN_67___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__GM_GAIN_EVEN_67___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__TIA_GAIN_EVEN_67___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__TIA_GAIN_EVEN_67___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__SLM_XLNA_EVEN_67___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__SLM_XLNA_EVEN_67___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__BQ_GAIN_EVEN_67___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67__BQ_GAIN_EVEN_67___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_67___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68 (0x005FD110) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__XLNA_GAIN_ODD_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__LNA_GAIN_ODD_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__GM_GAIN_ODD_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__TIA_GAIN_ODD_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__SLM_XLNA_ODD_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__BQ_GAIN_ODD_68___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__XLNA_GAIN_EVEN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__LNA_GAIN_EVEN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__GM_GAIN_EVEN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__TIA_GAIN_EVEN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__SLM_XLNA_EVEN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__BQ_GAIN_EVEN_68___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__XLNA_GAIN_ODD_68___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__XLNA_GAIN_ODD_68___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__LNA_GAIN_ODD_68___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__LNA_GAIN_ODD_68___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__GM_GAIN_ODD_68___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__GM_GAIN_ODD_68___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__TIA_GAIN_ODD_68___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__TIA_GAIN_ODD_68___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__SLM_XLNA_ODD_68___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__SLM_XLNA_ODD_68___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__BQ_GAIN_ODD_68___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__BQ_GAIN_ODD_68___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__XLNA_GAIN_EVEN_68___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__XLNA_GAIN_EVEN_68___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__LNA_GAIN_EVEN_68___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__LNA_GAIN_EVEN_68___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__GM_GAIN_EVEN_68___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__GM_GAIN_EVEN_68___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__TIA_GAIN_EVEN_68___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__TIA_GAIN_EVEN_68___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__SLM_XLNA_EVEN_68___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__SLM_XLNA_EVEN_68___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__BQ_GAIN_EVEN_68___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68__BQ_GAIN_EVEN_68___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_68___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69 (0x005FD114) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__XLNA_GAIN_ODD_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__LNA_GAIN_ODD_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__GM_GAIN_ODD_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__TIA_GAIN_ODD_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__SLM_XLNA_ODD_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__BQ_GAIN_ODD_69___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__XLNA_GAIN_EVEN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__LNA_GAIN_EVEN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__GM_GAIN_EVEN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__TIA_GAIN_EVEN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__SLM_XLNA_EVEN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__BQ_GAIN_EVEN_69___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__XLNA_GAIN_ODD_69___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__XLNA_GAIN_ODD_69___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__LNA_GAIN_ODD_69___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__LNA_GAIN_ODD_69___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__GM_GAIN_ODD_69___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__GM_GAIN_ODD_69___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__TIA_GAIN_ODD_69___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__TIA_GAIN_ODD_69___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__SLM_XLNA_ODD_69___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__SLM_XLNA_ODD_69___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__BQ_GAIN_ODD_69___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__BQ_GAIN_ODD_69___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__XLNA_GAIN_EVEN_69___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__XLNA_GAIN_EVEN_69___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__LNA_GAIN_EVEN_69___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__LNA_GAIN_EVEN_69___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__GM_GAIN_EVEN_69___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__GM_GAIN_EVEN_69___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__TIA_GAIN_EVEN_69___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__TIA_GAIN_EVEN_69___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__SLM_XLNA_EVEN_69___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__SLM_XLNA_EVEN_69___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__BQ_GAIN_EVEN_69___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69__BQ_GAIN_EVEN_69___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_69___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70 (0x005FD118) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__XLNA_GAIN_ODD_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__LNA_GAIN_ODD_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__GM_GAIN_ODD_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__TIA_GAIN_ODD_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__SLM_XLNA_ODD_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__BQ_GAIN_ODD_70___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__XLNA_GAIN_EVEN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__LNA_GAIN_EVEN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__GM_GAIN_EVEN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__TIA_GAIN_EVEN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__SLM_XLNA_EVEN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__BQ_GAIN_EVEN_70___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__XLNA_GAIN_ODD_70___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__XLNA_GAIN_ODD_70___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__LNA_GAIN_ODD_70___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__LNA_GAIN_ODD_70___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__GM_GAIN_ODD_70___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__GM_GAIN_ODD_70___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__TIA_GAIN_ODD_70___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__TIA_GAIN_ODD_70___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__SLM_XLNA_ODD_70___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__SLM_XLNA_ODD_70___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__BQ_GAIN_ODD_70___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__BQ_GAIN_ODD_70___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__XLNA_GAIN_EVEN_70___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__XLNA_GAIN_EVEN_70___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__LNA_GAIN_EVEN_70___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__LNA_GAIN_EVEN_70___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__GM_GAIN_EVEN_70___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__GM_GAIN_EVEN_70___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__TIA_GAIN_EVEN_70___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__TIA_GAIN_EVEN_70___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__SLM_XLNA_EVEN_70___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__SLM_XLNA_EVEN_70___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__BQ_GAIN_EVEN_70___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70__BQ_GAIN_EVEN_70___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_70___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71 (0x005FD11C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__XLNA_GAIN_ODD_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__LNA_GAIN_ODD_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__GM_GAIN_ODD_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__TIA_GAIN_ODD_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__SLM_XLNA_ODD_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__BQ_GAIN_ODD_71___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__XLNA_GAIN_EVEN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__LNA_GAIN_EVEN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__GM_GAIN_EVEN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__TIA_GAIN_EVEN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__SLM_XLNA_EVEN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__BQ_GAIN_EVEN_71___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__XLNA_GAIN_ODD_71___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__XLNA_GAIN_ODD_71___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__LNA_GAIN_ODD_71___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__LNA_GAIN_ODD_71___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__GM_GAIN_ODD_71___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__GM_GAIN_ODD_71___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__TIA_GAIN_ODD_71___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__TIA_GAIN_ODD_71___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__SLM_XLNA_ODD_71___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__SLM_XLNA_ODD_71___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__BQ_GAIN_ODD_71___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__BQ_GAIN_ODD_71___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__XLNA_GAIN_EVEN_71___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__XLNA_GAIN_EVEN_71___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__LNA_GAIN_EVEN_71___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__LNA_GAIN_EVEN_71___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__GM_GAIN_EVEN_71___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__GM_GAIN_EVEN_71___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__TIA_GAIN_EVEN_71___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__TIA_GAIN_EVEN_71___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__SLM_XLNA_EVEN_71___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__SLM_XLNA_EVEN_71___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__BQ_GAIN_EVEN_71___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71__BQ_GAIN_EVEN_71___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_71___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72 (0x005FD120) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__XLNA_GAIN_ODD_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__LNA_GAIN_ODD_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__GM_GAIN_ODD_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__TIA_GAIN_ODD_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__SLM_XLNA_ODD_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__BQ_GAIN_ODD_72___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__XLNA_GAIN_EVEN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__LNA_GAIN_EVEN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__GM_GAIN_EVEN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__TIA_GAIN_EVEN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__SLM_XLNA_EVEN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__BQ_GAIN_EVEN_72___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__XLNA_GAIN_ODD_72___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__XLNA_GAIN_ODD_72___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__LNA_GAIN_ODD_72___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__LNA_GAIN_ODD_72___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__GM_GAIN_ODD_72___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__GM_GAIN_ODD_72___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__TIA_GAIN_ODD_72___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__TIA_GAIN_ODD_72___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__SLM_XLNA_ODD_72___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__SLM_XLNA_ODD_72___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__BQ_GAIN_ODD_72___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__BQ_GAIN_ODD_72___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__XLNA_GAIN_EVEN_72___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__XLNA_GAIN_EVEN_72___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__LNA_GAIN_EVEN_72___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__LNA_GAIN_EVEN_72___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__GM_GAIN_EVEN_72___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__GM_GAIN_EVEN_72___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__TIA_GAIN_EVEN_72___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__TIA_GAIN_EVEN_72___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__SLM_XLNA_EVEN_72___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__SLM_XLNA_EVEN_72___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__BQ_GAIN_EVEN_72___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72__BQ_GAIN_EVEN_72___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_72___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73 (0x005FD124) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__XLNA_GAIN_ODD_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__LNA_GAIN_ODD_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__GM_GAIN_ODD_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__TIA_GAIN_ODD_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__SLM_XLNA_ODD_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__BQ_GAIN_ODD_73___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__XLNA_GAIN_EVEN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__LNA_GAIN_EVEN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__GM_GAIN_EVEN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__TIA_GAIN_EVEN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__SLM_XLNA_EVEN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__BQ_GAIN_EVEN_73___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__XLNA_GAIN_ODD_73___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__XLNA_GAIN_ODD_73___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__LNA_GAIN_ODD_73___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__LNA_GAIN_ODD_73___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__GM_GAIN_ODD_73___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__GM_GAIN_ODD_73___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__TIA_GAIN_ODD_73___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__TIA_GAIN_ODD_73___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__SLM_XLNA_ODD_73___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__SLM_XLNA_ODD_73___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__BQ_GAIN_ODD_73___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__BQ_GAIN_ODD_73___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__XLNA_GAIN_EVEN_73___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__XLNA_GAIN_EVEN_73___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__LNA_GAIN_EVEN_73___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__LNA_GAIN_EVEN_73___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__GM_GAIN_EVEN_73___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__GM_GAIN_EVEN_73___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__TIA_GAIN_EVEN_73___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__TIA_GAIN_EVEN_73___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__SLM_XLNA_EVEN_73___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__SLM_XLNA_EVEN_73___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__BQ_GAIN_EVEN_73___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73__BQ_GAIN_EVEN_73___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_73___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74 (0x005FD128) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__XLNA_GAIN_ODD_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__LNA_GAIN_ODD_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__GM_GAIN_ODD_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__TIA_GAIN_ODD_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__SLM_XLNA_ODD_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__BQ_GAIN_ODD_74___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__XLNA_GAIN_EVEN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__LNA_GAIN_EVEN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__GM_GAIN_EVEN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__TIA_GAIN_EVEN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__SLM_XLNA_EVEN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__BQ_GAIN_EVEN_74___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__XLNA_GAIN_ODD_74___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__XLNA_GAIN_ODD_74___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__LNA_GAIN_ODD_74___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__LNA_GAIN_ODD_74___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__GM_GAIN_ODD_74___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__GM_GAIN_ODD_74___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__TIA_GAIN_ODD_74___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__TIA_GAIN_ODD_74___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__SLM_XLNA_ODD_74___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__SLM_XLNA_ODD_74___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__BQ_GAIN_ODD_74___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__BQ_GAIN_ODD_74___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__XLNA_GAIN_EVEN_74___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__XLNA_GAIN_EVEN_74___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__LNA_GAIN_EVEN_74___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__LNA_GAIN_EVEN_74___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__GM_GAIN_EVEN_74___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__GM_GAIN_EVEN_74___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__TIA_GAIN_EVEN_74___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__TIA_GAIN_EVEN_74___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__SLM_XLNA_EVEN_74___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__SLM_XLNA_EVEN_74___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__BQ_GAIN_EVEN_74___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74__BQ_GAIN_EVEN_74___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_74___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75 (0x005FD12C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__XLNA_GAIN_ODD_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__LNA_GAIN_ODD_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__GM_GAIN_ODD_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__TIA_GAIN_ODD_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__SLM_XLNA_ODD_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__BQ_GAIN_ODD_75___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__XLNA_GAIN_EVEN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__LNA_GAIN_EVEN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__GM_GAIN_EVEN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__TIA_GAIN_EVEN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__SLM_XLNA_EVEN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__BQ_GAIN_EVEN_75___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__XLNA_GAIN_ODD_75___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__XLNA_GAIN_ODD_75___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__LNA_GAIN_ODD_75___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__LNA_GAIN_ODD_75___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__GM_GAIN_ODD_75___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__GM_GAIN_ODD_75___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__TIA_GAIN_ODD_75___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__TIA_GAIN_ODD_75___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__SLM_XLNA_ODD_75___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__SLM_XLNA_ODD_75___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__BQ_GAIN_ODD_75___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__BQ_GAIN_ODD_75___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__XLNA_GAIN_EVEN_75___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__XLNA_GAIN_EVEN_75___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__LNA_GAIN_EVEN_75___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__LNA_GAIN_EVEN_75___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__GM_GAIN_EVEN_75___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__GM_GAIN_EVEN_75___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__TIA_GAIN_EVEN_75___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__TIA_GAIN_EVEN_75___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__SLM_XLNA_EVEN_75___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__SLM_XLNA_EVEN_75___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__BQ_GAIN_EVEN_75___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75__BQ_GAIN_EVEN_75___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_75___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76 (0x005FD130) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__XLNA_GAIN_ODD_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__LNA_GAIN_ODD_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__GM_GAIN_ODD_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__TIA_GAIN_ODD_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__SLM_XLNA_ODD_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__BQ_GAIN_ODD_76___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__XLNA_GAIN_EVEN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__LNA_GAIN_EVEN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__GM_GAIN_EVEN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__TIA_GAIN_EVEN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__SLM_XLNA_EVEN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__BQ_GAIN_EVEN_76___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__XLNA_GAIN_ODD_76___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__XLNA_GAIN_ODD_76___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__LNA_GAIN_ODD_76___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__LNA_GAIN_ODD_76___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__GM_GAIN_ODD_76___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__GM_GAIN_ODD_76___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__TIA_GAIN_ODD_76___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__TIA_GAIN_ODD_76___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__SLM_XLNA_ODD_76___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__SLM_XLNA_ODD_76___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__BQ_GAIN_ODD_76___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__BQ_GAIN_ODD_76___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__XLNA_GAIN_EVEN_76___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__XLNA_GAIN_EVEN_76___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__LNA_GAIN_EVEN_76___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__LNA_GAIN_EVEN_76___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__GM_GAIN_EVEN_76___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__GM_GAIN_EVEN_76___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__TIA_GAIN_EVEN_76___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__TIA_GAIN_EVEN_76___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__SLM_XLNA_EVEN_76___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__SLM_XLNA_EVEN_76___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__BQ_GAIN_EVEN_76___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76__BQ_GAIN_EVEN_76___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_76___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77 (0x005FD134) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__XLNA_GAIN_ODD_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__LNA_GAIN_ODD_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__GM_GAIN_ODD_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__TIA_GAIN_ODD_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__SLM_XLNA_ODD_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__BQ_GAIN_ODD_77___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__XLNA_GAIN_EVEN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__LNA_GAIN_EVEN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__GM_GAIN_EVEN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__TIA_GAIN_EVEN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__SLM_XLNA_EVEN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__BQ_GAIN_EVEN_77___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__XLNA_GAIN_ODD_77___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__XLNA_GAIN_ODD_77___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__LNA_GAIN_ODD_77___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__LNA_GAIN_ODD_77___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__GM_GAIN_ODD_77___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__GM_GAIN_ODD_77___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__TIA_GAIN_ODD_77___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__TIA_GAIN_ODD_77___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__SLM_XLNA_ODD_77___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__SLM_XLNA_ODD_77___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__BQ_GAIN_ODD_77___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__BQ_GAIN_ODD_77___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__XLNA_GAIN_EVEN_77___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__XLNA_GAIN_EVEN_77___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__LNA_GAIN_EVEN_77___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__LNA_GAIN_EVEN_77___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__GM_GAIN_EVEN_77___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__GM_GAIN_EVEN_77___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__TIA_GAIN_EVEN_77___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__TIA_GAIN_EVEN_77___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__SLM_XLNA_EVEN_77___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__SLM_XLNA_EVEN_77___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__BQ_GAIN_EVEN_77___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77__BQ_GAIN_EVEN_77___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_77___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78 (0x005FD138) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__XLNA_GAIN_ODD_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__LNA_GAIN_ODD_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__GM_GAIN_ODD_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__TIA_GAIN_ODD_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__SLM_XLNA_ODD_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__BQ_GAIN_ODD_78___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__XLNA_GAIN_EVEN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__LNA_GAIN_EVEN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__GM_GAIN_EVEN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__TIA_GAIN_EVEN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__SLM_XLNA_EVEN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__BQ_GAIN_EVEN_78___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__XLNA_GAIN_ODD_78___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__XLNA_GAIN_ODD_78___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__LNA_GAIN_ODD_78___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__LNA_GAIN_ODD_78___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__GM_GAIN_ODD_78___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__GM_GAIN_ODD_78___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__TIA_GAIN_ODD_78___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__TIA_GAIN_ODD_78___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__SLM_XLNA_ODD_78___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__SLM_XLNA_ODD_78___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__BQ_GAIN_ODD_78___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__BQ_GAIN_ODD_78___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__XLNA_GAIN_EVEN_78___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__XLNA_GAIN_EVEN_78___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__LNA_GAIN_EVEN_78___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__LNA_GAIN_EVEN_78___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__GM_GAIN_EVEN_78___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__GM_GAIN_EVEN_78___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__TIA_GAIN_EVEN_78___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__TIA_GAIN_EVEN_78___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__SLM_XLNA_EVEN_78___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__SLM_XLNA_EVEN_78___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__BQ_GAIN_EVEN_78___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78__BQ_GAIN_EVEN_78___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_78___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79 (0x005FD13C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__XLNA_GAIN_ODD_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__LNA_GAIN_ODD_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__GM_GAIN_ODD_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__TIA_GAIN_ODD_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__SLM_XLNA_ODD_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__BQ_GAIN_ODD_79___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__XLNA_GAIN_EVEN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__LNA_GAIN_EVEN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__GM_GAIN_EVEN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__TIA_GAIN_EVEN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__SLM_XLNA_EVEN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__BQ_GAIN_EVEN_79___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__XLNA_GAIN_ODD_79___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__XLNA_GAIN_ODD_79___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__LNA_GAIN_ODD_79___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__LNA_GAIN_ODD_79___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__GM_GAIN_ODD_79___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__GM_GAIN_ODD_79___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__TIA_GAIN_ODD_79___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__TIA_GAIN_ODD_79___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__SLM_XLNA_ODD_79___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__SLM_XLNA_ODD_79___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__BQ_GAIN_ODD_79___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__BQ_GAIN_ODD_79___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__XLNA_GAIN_EVEN_79___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__XLNA_GAIN_EVEN_79___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__LNA_GAIN_EVEN_79___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__LNA_GAIN_EVEN_79___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__GM_GAIN_EVEN_79___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__GM_GAIN_EVEN_79___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__TIA_GAIN_EVEN_79___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__TIA_GAIN_EVEN_79___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__SLM_XLNA_EVEN_79___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__SLM_XLNA_EVEN_79___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__BQ_GAIN_EVEN_79___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79__BQ_GAIN_EVEN_79___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_79___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80 (0x005FD140) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__XLNA_GAIN_ODD_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__LNA_GAIN_ODD_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__GM_GAIN_ODD_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__TIA_GAIN_ODD_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__SLM_XLNA_ODD_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__BQ_GAIN_ODD_80___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__XLNA_GAIN_EVEN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__LNA_GAIN_EVEN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__GM_GAIN_EVEN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__TIA_GAIN_EVEN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__SLM_XLNA_EVEN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__BQ_GAIN_EVEN_80___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__XLNA_GAIN_ODD_80___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__XLNA_GAIN_ODD_80___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__LNA_GAIN_ODD_80___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__LNA_GAIN_ODD_80___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__GM_GAIN_ODD_80___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__GM_GAIN_ODD_80___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__TIA_GAIN_ODD_80___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__TIA_GAIN_ODD_80___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__SLM_XLNA_ODD_80___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__SLM_XLNA_ODD_80___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__BQ_GAIN_ODD_80___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__BQ_GAIN_ODD_80___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__XLNA_GAIN_EVEN_80___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__XLNA_GAIN_EVEN_80___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__LNA_GAIN_EVEN_80___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__LNA_GAIN_EVEN_80___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__GM_GAIN_EVEN_80___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__GM_GAIN_EVEN_80___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__TIA_GAIN_EVEN_80___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__TIA_GAIN_EVEN_80___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__SLM_XLNA_EVEN_80___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__SLM_XLNA_EVEN_80___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__BQ_GAIN_EVEN_80___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80__BQ_GAIN_EVEN_80___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_80___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81 (0x005FD144) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__XLNA_GAIN_ODD_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__LNA_GAIN_ODD_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__GM_GAIN_ODD_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__TIA_GAIN_ODD_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__SLM_XLNA_ODD_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__BQ_GAIN_ODD_81___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__XLNA_GAIN_EVEN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__LNA_GAIN_EVEN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__GM_GAIN_EVEN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__TIA_GAIN_EVEN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__SLM_XLNA_EVEN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__BQ_GAIN_EVEN_81___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__XLNA_GAIN_ODD_81___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__XLNA_GAIN_ODD_81___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__LNA_GAIN_ODD_81___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__LNA_GAIN_ODD_81___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__GM_GAIN_ODD_81___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__GM_GAIN_ODD_81___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__TIA_GAIN_ODD_81___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__TIA_GAIN_ODD_81___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__SLM_XLNA_ODD_81___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__SLM_XLNA_ODD_81___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__BQ_GAIN_ODD_81___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__BQ_GAIN_ODD_81___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__XLNA_GAIN_EVEN_81___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__XLNA_GAIN_EVEN_81___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__LNA_GAIN_EVEN_81___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__LNA_GAIN_EVEN_81___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__GM_GAIN_EVEN_81___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__GM_GAIN_EVEN_81___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__TIA_GAIN_EVEN_81___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__TIA_GAIN_EVEN_81___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__SLM_XLNA_EVEN_81___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__SLM_XLNA_EVEN_81___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__BQ_GAIN_EVEN_81___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81__BQ_GAIN_EVEN_81___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_81___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82 (0x005FD148) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__XLNA_GAIN_ODD_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__LNA_GAIN_ODD_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__GM_GAIN_ODD_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__TIA_GAIN_ODD_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__SLM_XLNA_ODD_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__BQ_GAIN_ODD_82___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__XLNA_GAIN_EVEN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__LNA_GAIN_EVEN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__GM_GAIN_EVEN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__TIA_GAIN_EVEN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__SLM_XLNA_EVEN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__BQ_GAIN_EVEN_82___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__XLNA_GAIN_ODD_82___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__XLNA_GAIN_ODD_82___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__LNA_GAIN_ODD_82___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__LNA_GAIN_ODD_82___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__GM_GAIN_ODD_82___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__GM_GAIN_ODD_82___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__TIA_GAIN_ODD_82___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__TIA_GAIN_ODD_82___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__SLM_XLNA_ODD_82___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__SLM_XLNA_ODD_82___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__BQ_GAIN_ODD_82___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__BQ_GAIN_ODD_82___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__XLNA_GAIN_EVEN_82___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__XLNA_GAIN_EVEN_82___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__LNA_GAIN_EVEN_82___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__LNA_GAIN_EVEN_82___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__GM_GAIN_EVEN_82___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__GM_GAIN_EVEN_82___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__TIA_GAIN_EVEN_82___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__TIA_GAIN_EVEN_82___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__SLM_XLNA_EVEN_82___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__SLM_XLNA_EVEN_82___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__BQ_GAIN_EVEN_82___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82__BQ_GAIN_EVEN_82___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_82___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83 (0x005FD14C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__XLNA_GAIN_ODD_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__LNA_GAIN_ODD_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__GM_GAIN_ODD_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__TIA_GAIN_ODD_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__SLM_XLNA_ODD_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__BQ_GAIN_ODD_83___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__XLNA_GAIN_EVEN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__LNA_GAIN_EVEN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__GM_GAIN_EVEN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__TIA_GAIN_EVEN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__SLM_XLNA_EVEN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__BQ_GAIN_EVEN_83___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__XLNA_GAIN_ODD_83___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__XLNA_GAIN_ODD_83___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__LNA_GAIN_ODD_83___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__LNA_GAIN_ODD_83___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__GM_GAIN_ODD_83___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__GM_GAIN_ODD_83___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__TIA_GAIN_ODD_83___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__TIA_GAIN_ODD_83___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__SLM_XLNA_ODD_83___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__SLM_XLNA_ODD_83___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__BQ_GAIN_ODD_83___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__BQ_GAIN_ODD_83___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__XLNA_GAIN_EVEN_83___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__XLNA_GAIN_EVEN_83___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__LNA_GAIN_EVEN_83___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__LNA_GAIN_EVEN_83___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__GM_GAIN_EVEN_83___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__GM_GAIN_EVEN_83___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__TIA_GAIN_EVEN_83___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__TIA_GAIN_EVEN_83___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__SLM_XLNA_EVEN_83___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__SLM_XLNA_EVEN_83___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__BQ_GAIN_EVEN_83___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83__BQ_GAIN_EVEN_83___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_83___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84 (0x005FD150) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__XLNA_GAIN_ODD_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__LNA_GAIN_ODD_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__GM_GAIN_ODD_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__TIA_GAIN_ODD_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__SLM_XLNA_ODD_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__BQ_GAIN_ODD_84___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__XLNA_GAIN_EVEN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__LNA_GAIN_EVEN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__GM_GAIN_EVEN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__TIA_GAIN_EVEN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__SLM_XLNA_EVEN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__BQ_GAIN_EVEN_84___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__XLNA_GAIN_ODD_84___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__XLNA_GAIN_ODD_84___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__LNA_GAIN_ODD_84___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__LNA_GAIN_ODD_84___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__GM_GAIN_ODD_84___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__GM_GAIN_ODD_84___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__TIA_GAIN_ODD_84___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__TIA_GAIN_ODD_84___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__SLM_XLNA_ODD_84___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__SLM_XLNA_ODD_84___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__BQ_GAIN_ODD_84___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__BQ_GAIN_ODD_84___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__XLNA_GAIN_EVEN_84___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__XLNA_GAIN_EVEN_84___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__LNA_GAIN_EVEN_84___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__LNA_GAIN_EVEN_84___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__GM_GAIN_EVEN_84___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__GM_GAIN_EVEN_84___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__TIA_GAIN_EVEN_84___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__TIA_GAIN_EVEN_84___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__SLM_XLNA_EVEN_84___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__SLM_XLNA_EVEN_84___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__BQ_GAIN_EVEN_84___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84__BQ_GAIN_EVEN_84___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_84___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85 (0x005FD154) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__XLNA_GAIN_ODD_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__LNA_GAIN_ODD_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__GM_GAIN_ODD_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__TIA_GAIN_ODD_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__SLM_XLNA_ODD_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__BQ_GAIN_ODD_85___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__XLNA_GAIN_EVEN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__LNA_GAIN_EVEN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__GM_GAIN_EVEN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__TIA_GAIN_EVEN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__SLM_XLNA_EVEN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__BQ_GAIN_EVEN_85___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__XLNA_GAIN_ODD_85___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__XLNA_GAIN_ODD_85___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__LNA_GAIN_ODD_85___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__LNA_GAIN_ODD_85___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__GM_GAIN_ODD_85___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__GM_GAIN_ODD_85___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__TIA_GAIN_ODD_85___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__TIA_GAIN_ODD_85___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__SLM_XLNA_ODD_85___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__SLM_XLNA_ODD_85___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__BQ_GAIN_ODD_85___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__BQ_GAIN_ODD_85___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__XLNA_GAIN_EVEN_85___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__XLNA_GAIN_EVEN_85___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__LNA_GAIN_EVEN_85___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__LNA_GAIN_EVEN_85___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__GM_GAIN_EVEN_85___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__GM_GAIN_EVEN_85___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__TIA_GAIN_EVEN_85___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__TIA_GAIN_EVEN_85___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__SLM_XLNA_EVEN_85___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__SLM_XLNA_EVEN_85___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__BQ_GAIN_EVEN_85___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85__BQ_GAIN_EVEN_85___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_85___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86 (0x005FD158) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__XLNA_GAIN_ODD_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__LNA_GAIN_ODD_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__GM_GAIN_ODD_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__TIA_GAIN_ODD_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__SLM_XLNA_ODD_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__BQ_GAIN_ODD_86___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__XLNA_GAIN_EVEN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__LNA_GAIN_EVEN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__GM_GAIN_EVEN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__TIA_GAIN_EVEN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__SLM_XLNA_EVEN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__BQ_GAIN_EVEN_86___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__XLNA_GAIN_ODD_86___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__XLNA_GAIN_ODD_86___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__LNA_GAIN_ODD_86___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__LNA_GAIN_ODD_86___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__GM_GAIN_ODD_86___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__GM_GAIN_ODD_86___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__TIA_GAIN_ODD_86___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__TIA_GAIN_ODD_86___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__SLM_XLNA_ODD_86___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__SLM_XLNA_ODD_86___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__BQ_GAIN_ODD_86___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__BQ_GAIN_ODD_86___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__XLNA_GAIN_EVEN_86___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__XLNA_GAIN_EVEN_86___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__LNA_GAIN_EVEN_86___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__LNA_GAIN_EVEN_86___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__GM_GAIN_EVEN_86___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__GM_GAIN_EVEN_86___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__TIA_GAIN_EVEN_86___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__TIA_GAIN_EVEN_86___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__SLM_XLNA_EVEN_86___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__SLM_XLNA_EVEN_86___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__BQ_GAIN_EVEN_86___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86__BQ_GAIN_EVEN_86___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_86___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87 (0x005FD15C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__XLNA_GAIN_ODD_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__LNA_GAIN_ODD_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__GM_GAIN_ODD_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__TIA_GAIN_ODD_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__SLM_XLNA_ODD_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__BQ_GAIN_ODD_87___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__XLNA_GAIN_EVEN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__LNA_GAIN_EVEN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__GM_GAIN_EVEN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__TIA_GAIN_EVEN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__SLM_XLNA_EVEN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__BQ_GAIN_EVEN_87___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__XLNA_GAIN_ODD_87___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__XLNA_GAIN_ODD_87___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__LNA_GAIN_ODD_87___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__LNA_GAIN_ODD_87___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__GM_GAIN_ODD_87___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__GM_GAIN_ODD_87___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__TIA_GAIN_ODD_87___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__TIA_GAIN_ODD_87___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__SLM_XLNA_ODD_87___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__SLM_XLNA_ODD_87___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__BQ_GAIN_ODD_87___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__BQ_GAIN_ODD_87___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__XLNA_GAIN_EVEN_87___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__XLNA_GAIN_EVEN_87___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__LNA_GAIN_EVEN_87___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__LNA_GAIN_EVEN_87___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__GM_GAIN_EVEN_87___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__GM_GAIN_EVEN_87___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__TIA_GAIN_EVEN_87___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__TIA_GAIN_EVEN_87___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__SLM_XLNA_EVEN_87___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__SLM_XLNA_EVEN_87___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__BQ_GAIN_EVEN_87___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87__BQ_GAIN_EVEN_87___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_87___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88 (0x005FD160) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__XLNA_GAIN_ODD_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__LNA_GAIN_ODD_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__GM_GAIN_ODD_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__TIA_GAIN_ODD_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__SLM_XLNA_ODD_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__BQ_GAIN_ODD_88___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__XLNA_GAIN_EVEN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__LNA_GAIN_EVEN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__GM_GAIN_EVEN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__TIA_GAIN_EVEN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__SLM_XLNA_EVEN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__BQ_GAIN_EVEN_88___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__XLNA_GAIN_ODD_88___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__XLNA_GAIN_ODD_88___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__LNA_GAIN_ODD_88___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__LNA_GAIN_ODD_88___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__GM_GAIN_ODD_88___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__GM_GAIN_ODD_88___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__TIA_GAIN_ODD_88___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__TIA_GAIN_ODD_88___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__SLM_XLNA_ODD_88___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__SLM_XLNA_ODD_88___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__BQ_GAIN_ODD_88___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__BQ_GAIN_ODD_88___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__XLNA_GAIN_EVEN_88___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__XLNA_GAIN_EVEN_88___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__LNA_GAIN_EVEN_88___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__LNA_GAIN_EVEN_88___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__GM_GAIN_EVEN_88___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__GM_GAIN_EVEN_88___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__TIA_GAIN_EVEN_88___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__TIA_GAIN_EVEN_88___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__SLM_XLNA_EVEN_88___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__SLM_XLNA_EVEN_88___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__BQ_GAIN_EVEN_88___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88__BQ_GAIN_EVEN_88___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_88___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89 (0x005FD164) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__XLNA_GAIN_ODD_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__LNA_GAIN_ODD_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__GM_GAIN_ODD_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__TIA_GAIN_ODD_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__SLM_XLNA_ODD_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__BQ_GAIN_ODD_89___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__XLNA_GAIN_EVEN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__LNA_GAIN_EVEN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__GM_GAIN_EVEN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__TIA_GAIN_EVEN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__SLM_XLNA_EVEN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__BQ_GAIN_EVEN_89___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__XLNA_GAIN_ODD_89___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__XLNA_GAIN_ODD_89___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__LNA_GAIN_ODD_89___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__LNA_GAIN_ODD_89___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__GM_GAIN_ODD_89___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__GM_GAIN_ODD_89___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__TIA_GAIN_ODD_89___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__TIA_GAIN_ODD_89___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__SLM_XLNA_ODD_89___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__SLM_XLNA_ODD_89___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__BQ_GAIN_ODD_89___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__BQ_GAIN_ODD_89___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__XLNA_GAIN_EVEN_89___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__XLNA_GAIN_EVEN_89___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__LNA_GAIN_EVEN_89___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__LNA_GAIN_EVEN_89___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__GM_GAIN_EVEN_89___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__GM_GAIN_EVEN_89___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__TIA_GAIN_EVEN_89___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__TIA_GAIN_EVEN_89___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__SLM_XLNA_EVEN_89___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__SLM_XLNA_EVEN_89___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__BQ_GAIN_EVEN_89___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89__BQ_GAIN_EVEN_89___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_89___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90 (0x005FD168) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__XLNA_GAIN_ODD_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__LNA_GAIN_ODD_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__GM_GAIN_ODD_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__TIA_GAIN_ODD_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__SLM_XLNA_ODD_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__BQ_GAIN_ODD_90___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__XLNA_GAIN_EVEN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__LNA_GAIN_EVEN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__GM_GAIN_EVEN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__TIA_GAIN_EVEN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__SLM_XLNA_EVEN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__BQ_GAIN_EVEN_90___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__XLNA_GAIN_ODD_90___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__XLNA_GAIN_ODD_90___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__LNA_GAIN_ODD_90___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__LNA_GAIN_ODD_90___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__GM_GAIN_ODD_90___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__GM_GAIN_ODD_90___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__TIA_GAIN_ODD_90___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__TIA_GAIN_ODD_90___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__SLM_XLNA_ODD_90___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__SLM_XLNA_ODD_90___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__BQ_GAIN_ODD_90___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__BQ_GAIN_ODD_90___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__XLNA_GAIN_EVEN_90___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__XLNA_GAIN_EVEN_90___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__LNA_GAIN_EVEN_90___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__LNA_GAIN_EVEN_90___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__GM_GAIN_EVEN_90___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__GM_GAIN_EVEN_90___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__TIA_GAIN_EVEN_90___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__TIA_GAIN_EVEN_90___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__SLM_XLNA_EVEN_90___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__SLM_XLNA_EVEN_90___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__BQ_GAIN_EVEN_90___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90__BQ_GAIN_EVEN_90___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_90___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91 (0x005FD16C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__XLNA_GAIN_ODD_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__LNA_GAIN_ODD_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__GM_GAIN_ODD_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__TIA_GAIN_ODD_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__SLM_XLNA_ODD_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__BQ_GAIN_ODD_91___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__XLNA_GAIN_EVEN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__LNA_GAIN_EVEN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__GM_GAIN_EVEN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__TIA_GAIN_EVEN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__SLM_XLNA_EVEN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__BQ_GAIN_EVEN_91___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__XLNA_GAIN_ODD_91___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__XLNA_GAIN_ODD_91___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__LNA_GAIN_ODD_91___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__LNA_GAIN_ODD_91___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__GM_GAIN_ODD_91___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__GM_GAIN_ODD_91___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__TIA_GAIN_ODD_91___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__TIA_GAIN_ODD_91___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__SLM_XLNA_ODD_91___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__SLM_XLNA_ODD_91___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__BQ_GAIN_ODD_91___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__BQ_GAIN_ODD_91___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__XLNA_GAIN_EVEN_91___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__XLNA_GAIN_EVEN_91___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__LNA_GAIN_EVEN_91___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__LNA_GAIN_EVEN_91___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__GM_GAIN_EVEN_91___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__GM_GAIN_EVEN_91___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__TIA_GAIN_EVEN_91___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__TIA_GAIN_EVEN_91___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__SLM_XLNA_EVEN_91___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__SLM_XLNA_EVEN_91___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__BQ_GAIN_EVEN_91___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91__BQ_GAIN_EVEN_91___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_91___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92 (0x005FD170) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__XLNA_GAIN_ODD_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__LNA_GAIN_ODD_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__GM_GAIN_ODD_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__TIA_GAIN_ODD_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__SLM_XLNA_ODD_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__BQ_GAIN_ODD_92___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__XLNA_GAIN_EVEN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__LNA_GAIN_EVEN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__GM_GAIN_EVEN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__TIA_GAIN_EVEN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__SLM_XLNA_EVEN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__BQ_GAIN_EVEN_92___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__XLNA_GAIN_ODD_92___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__XLNA_GAIN_ODD_92___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__LNA_GAIN_ODD_92___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__LNA_GAIN_ODD_92___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__GM_GAIN_ODD_92___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__GM_GAIN_ODD_92___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__TIA_GAIN_ODD_92___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__TIA_GAIN_ODD_92___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__SLM_XLNA_ODD_92___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__SLM_XLNA_ODD_92___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__BQ_GAIN_ODD_92___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__BQ_GAIN_ODD_92___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__XLNA_GAIN_EVEN_92___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__XLNA_GAIN_EVEN_92___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__LNA_GAIN_EVEN_92___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__LNA_GAIN_EVEN_92___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__GM_GAIN_EVEN_92___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__GM_GAIN_EVEN_92___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__TIA_GAIN_EVEN_92___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__TIA_GAIN_EVEN_92___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__SLM_XLNA_EVEN_92___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__SLM_XLNA_EVEN_92___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__BQ_GAIN_EVEN_92___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92__BQ_GAIN_EVEN_92___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_92___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93 (0x005FD174) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__XLNA_GAIN_ODD_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__LNA_GAIN_ODD_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__GM_GAIN_ODD_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__TIA_GAIN_ODD_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__SLM_XLNA_ODD_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__BQ_GAIN_ODD_93___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__XLNA_GAIN_EVEN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__LNA_GAIN_EVEN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__GM_GAIN_EVEN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__TIA_GAIN_EVEN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__SLM_XLNA_EVEN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__BQ_GAIN_EVEN_93___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__XLNA_GAIN_ODD_93___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__XLNA_GAIN_ODD_93___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__LNA_GAIN_ODD_93___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__LNA_GAIN_ODD_93___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__GM_GAIN_ODD_93___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__GM_GAIN_ODD_93___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__TIA_GAIN_ODD_93___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__TIA_GAIN_ODD_93___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__SLM_XLNA_ODD_93___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__SLM_XLNA_ODD_93___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__BQ_GAIN_ODD_93___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__BQ_GAIN_ODD_93___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__XLNA_GAIN_EVEN_93___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__XLNA_GAIN_EVEN_93___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__LNA_GAIN_EVEN_93___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__LNA_GAIN_EVEN_93___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__GM_GAIN_EVEN_93___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__GM_GAIN_EVEN_93___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__TIA_GAIN_EVEN_93___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__TIA_GAIN_EVEN_93___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__SLM_XLNA_EVEN_93___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__SLM_XLNA_EVEN_93___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__BQ_GAIN_EVEN_93___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93__BQ_GAIN_EVEN_93___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_93___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94 (0x005FD178) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__XLNA_GAIN_ODD_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__LNA_GAIN_ODD_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__GM_GAIN_ODD_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__TIA_GAIN_ODD_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__SLM_XLNA_ODD_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__BQ_GAIN_ODD_94___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__XLNA_GAIN_EVEN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__LNA_GAIN_EVEN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__GM_GAIN_EVEN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__TIA_GAIN_EVEN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__SLM_XLNA_EVEN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__BQ_GAIN_EVEN_94___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__XLNA_GAIN_ODD_94___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__XLNA_GAIN_ODD_94___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__LNA_GAIN_ODD_94___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__LNA_GAIN_ODD_94___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__GM_GAIN_ODD_94___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__GM_GAIN_ODD_94___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__TIA_GAIN_ODD_94___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__TIA_GAIN_ODD_94___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__SLM_XLNA_ODD_94___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__SLM_XLNA_ODD_94___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__BQ_GAIN_ODD_94___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__BQ_GAIN_ODD_94___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__XLNA_GAIN_EVEN_94___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__XLNA_GAIN_EVEN_94___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__LNA_GAIN_EVEN_94___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__LNA_GAIN_EVEN_94___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__GM_GAIN_EVEN_94___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__GM_GAIN_EVEN_94___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__TIA_GAIN_EVEN_94___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__TIA_GAIN_EVEN_94___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__SLM_XLNA_EVEN_94___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__SLM_XLNA_EVEN_94___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__BQ_GAIN_EVEN_94___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94__BQ_GAIN_EVEN_94___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_94___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95 (0x005FD17C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__XLNA_GAIN_ODD_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__LNA_GAIN_ODD_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__GM_GAIN_ODD_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__TIA_GAIN_ODD_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__SLM_XLNA_ODD_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__BQ_GAIN_ODD_95___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__XLNA_GAIN_EVEN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__LNA_GAIN_EVEN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__GM_GAIN_EVEN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__TIA_GAIN_EVEN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__SLM_XLNA_EVEN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__BQ_GAIN_EVEN_95___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__XLNA_GAIN_ODD_95___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__XLNA_GAIN_ODD_95___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__LNA_GAIN_ODD_95___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__LNA_GAIN_ODD_95___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__GM_GAIN_ODD_95___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__GM_GAIN_ODD_95___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__TIA_GAIN_ODD_95___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__TIA_GAIN_ODD_95___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__SLM_XLNA_ODD_95___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__SLM_XLNA_ODD_95___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__BQ_GAIN_ODD_95___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__BQ_GAIN_ODD_95___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__XLNA_GAIN_EVEN_95___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__XLNA_GAIN_EVEN_95___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__LNA_GAIN_EVEN_95___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__LNA_GAIN_EVEN_95___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__GM_GAIN_EVEN_95___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__GM_GAIN_EVEN_95___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__TIA_GAIN_EVEN_95___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__TIA_GAIN_EVEN_95___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__SLM_XLNA_EVEN_95___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__SLM_XLNA_EVEN_95___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__BQ_GAIN_EVEN_95___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95__BQ_GAIN_EVEN_95___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_95___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96 (0x005FD180) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__XLNA_GAIN_ODD_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__LNA_GAIN_ODD_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__GM_GAIN_ODD_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__TIA_GAIN_ODD_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__SLM_XLNA_ODD_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__BQ_GAIN_ODD_96___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__XLNA_GAIN_EVEN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__LNA_GAIN_EVEN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__GM_GAIN_EVEN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__TIA_GAIN_EVEN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__SLM_XLNA_EVEN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__BQ_GAIN_EVEN_96___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__XLNA_GAIN_ODD_96___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__XLNA_GAIN_ODD_96___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__LNA_GAIN_ODD_96___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__LNA_GAIN_ODD_96___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__GM_GAIN_ODD_96___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__GM_GAIN_ODD_96___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__TIA_GAIN_ODD_96___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__TIA_GAIN_ODD_96___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__SLM_XLNA_ODD_96___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__SLM_XLNA_ODD_96___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__BQ_GAIN_ODD_96___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__BQ_GAIN_ODD_96___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__XLNA_GAIN_EVEN_96___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__XLNA_GAIN_EVEN_96___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__LNA_GAIN_EVEN_96___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__LNA_GAIN_EVEN_96___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__GM_GAIN_EVEN_96___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__GM_GAIN_EVEN_96___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__TIA_GAIN_EVEN_96___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__TIA_GAIN_EVEN_96___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__SLM_XLNA_EVEN_96___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__SLM_XLNA_EVEN_96___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__BQ_GAIN_EVEN_96___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96__BQ_GAIN_EVEN_96___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_96___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97 (0x005FD184) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__XLNA_GAIN_ODD_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__LNA_GAIN_ODD_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__GM_GAIN_ODD_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__TIA_GAIN_ODD_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__SLM_XLNA_ODD_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__BQ_GAIN_ODD_97___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__XLNA_GAIN_EVEN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__LNA_GAIN_EVEN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__GM_GAIN_EVEN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__TIA_GAIN_EVEN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__SLM_XLNA_EVEN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__BQ_GAIN_EVEN_97___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__XLNA_GAIN_ODD_97___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__XLNA_GAIN_ODD_97___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__LNA_GAIN_ODD_97___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__LNA_GAIN_ODD_97___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__GM_GAIN_ODD_97___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__GM_GAIN_ODD_97___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__TIA_GAIN_ODD_97___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__TIA_GAIN_ODD_97___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__SLM_XLNA_ODD_97___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__SLM_XLNA_ODD_97___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__BQ_GAIN_ODD_97___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__BQ_GAIN_ODD_97___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__XLNA_GAIN_EVEN_97___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__XLNA_GAIN_EVEN_97___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__LNA_GAIN_EVEN_97___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__LNA_GAIN_EVEN_97___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__GM_GAIN_EVEN_97___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__GM_GAIN_EVEN_97___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__TIA_GAIN_EVEN_97___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__TIA_GAIN_EVEN_97___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__SLM_XLNA_EVEN_97___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__SLM_XLNA_EVEN_97___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__BQ_GAIN_EVEN_97___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97__BQ_GAIN_EVEN_97___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_97___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98 (0x005FD188) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__XLNA_GAIN_ODD_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__LNA_GAIN_ODD_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__GM_GAIN_ODD_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__TIA_GAIN_ODD_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__SLM_XLNA_ODD_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__BQ_GAIN_ODD_98___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__XLNA_GAIN_EVEN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__LNA_GAIN_EVEN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__GM_GAIN_EVEN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__TIA_GAIN_EVEN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__SLM_XLNA_EVEN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__BQ_GAIN_EVEN_98___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__XLNA_GAIN_ODD_98___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__XLNA_GAIN_ODD_98___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__LNA_GAIN_ODD_98___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__LNA_GAIN_ODD_98___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__GM_GAIN_ODD_98___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__GM_GAIN_ODD_98___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__TIA_GAIN_ODD_98___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__TIA_GAIN_ODD_98___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__SLM_XLNA_ODD_98___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__SLM_XLNA_ODD_98___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__BQ_GAIN_ODD_98___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__BQ_GAIN_ODD_98___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__XLNA_GAIN_EVEN_98___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__XLNA_GAIN_EVEN_98___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__LNA_GAIN_EVEN_98___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__LNA_GAIN_EVEN_98___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__GM_GAIN_EVEN_98___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__GM_GAIN_EVEN_98___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__TIA_GAIN_EVEN_98___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__TIA_GAIN_EVEN_98___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__SLM_XLNA_EVEN_98___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__SLM_XLNA_EVEN_98___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__BQ_GAIN_EVEN_98___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98__BQ_GAIN_EVEN_98___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_98___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99 (0x005FD18C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__XLNA_GAIN_ODD_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__LNA_GAIN_ODD_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__GM_GAIN_ODD_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__TIA_GAIN_ODD_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__SLM_XLNA_ODD_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__BQ_GAIN_ODD_99___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__XLNA_GAIN_EVEN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__LNA_GAIN_EVEN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__GM_GAIN_EVEN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__TIA_GAIN_EVEN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__SLM_XLNA_EVEN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__BQ_GAIN_EVEN_99___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__XLNA_GAIN_ODD_99___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__XLNA_GAIN_ODD_99___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__LNA_GAIN_ODD_99___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__LNA_GAIN_ODD_99___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__GM_GAIN_ODD_99___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__GM_GAIN_ODD_99___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__TIA_GAIN_ODD_99___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__TIA_GAIN_ODD_99___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__SLM_XLNA_ODD_99___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__SLM_XLNA_ODD_99___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__BQ_GAIN_ODD_99___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__BQ_GAIN_ODD_99___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__XLNA_GAIN_EVEN_99___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__XLNA_GAIN_EVEN_99___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__LNA_GAIN_EVEN_99___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__LNA_GAIN_EVEN_99___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__GM_GAIN_EVEN_99___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__GM_GAIN_EVEN_99___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__TIA_GAIN_EVEN_99___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__TIA_GAIN_EVEN_99___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__SLM_XLNA_EVEN_99___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__SLM_XLNA_EVEN_99___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__BQ_GAIN_EVEN_99___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99__BQ_GAIN_EVEN_99___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_99___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100 (0x005FD190) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__XLNA_GAIN_ODD_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__LNA_GAIN_ODD_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__GM_GAIN_ODD_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__TIA_GAIN_ODD_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__SLM_XLNA_ODD_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__BQ_GAIN_ODD_100___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__XLNA_GAIN_EVEN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__LNA_GAIN_EVEN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__GM_GAIN_EVEN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__TIA_GAIN_EVEN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__SLM_XLNA_EVEN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__BQ_GAIN_EVEN_100___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__XLNA_GAIN_ODD_100___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__XLNA_GAIN_ODD_100___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__LNA_GAIN_ODD_100___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__LNA_GAIN_ODD_100___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__GM_GAIN_ODD_100___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__GM_GAIN_ODD_100___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__TIA_GAIN_ODD_100___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__TIA_GAIN_ODD_100___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__SLM_XLNA_ODD_100___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__SLM_XLNA_ODD_100___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__BQ_GAIN_ODD_100___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__BQ_GAIN_ODD_100___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__XLNA_GAIN_EVEN_100___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__XLNA_GAIN_EVEN_100___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__LNA_GAIN_EVEN_100___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__LNA_GAIN_EVEN_100___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__GM_GAIN_EVEN_100___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__GM_GAIN_EVEN_100___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__TIA_GAIN_EVEN_100___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__TIA_GAIN_EVEN_100___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__SLM_XLNA_EVEN_100___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__SLM_XLNA_EVEN_100___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__BQ_GAIN_EVEN_100___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100__BQ_GAIN_EVEN_100___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_100___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101 (0x005FD194) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__XLNA_GAIN_ODD_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__LNA_GAIN_ODD_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__GM_GAIN_ODD_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__TIA_GAIN_ODD_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__SLM_XLNA_ODD_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__BQ_GAIN_ODD_101___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__XLNA_GAIN_EVEN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__LNA_GAIN_EVEN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__GM_GAIN_EVEN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__TIA_GAIN_EVEN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__SLM_XLNA_EVEN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__BQ_GAIN_EVEN_101___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__XLNA_GAIN_ODD_101___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__XLNA_GAIN_ODD_101___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__LNA_GAIN_ODD_101___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__LNA_GAIN_ODD_101___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__GM_GAIN_ODD_101___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__GM_GAIN_ODD_101___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__TIA_GAIN_ODD_101___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__TIA_GAIN_ODD_101___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__SLM_XLNA_ODD_101___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__SLM_XLNA_ODD_101___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__BQ_GAIN_ODD_101___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__BQ_GAIN_ODD_101___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__XLNA_GAIN_EVEN_101___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__XLNA_GAIN_EVEN_101___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__LNA_GAIN_EVEN_101___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__LNA_GAIN_EVEN_101___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__GM_GAIN_EVEN_101___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__GM_GAIN_EVEN_101___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__TIA_GAIN_EVEN_101___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__TIA_GAIN_EVEN_101___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__SLM_XLNA_EVEN_101___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__SLM_XLNA_EVEN_101___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__BQ_GAIN_EVEN_101___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101__BQ_GAIN_EVEN_101___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_101___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102 (0x005FD198) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__XLNA_GAIN_ODD_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__LNA_GAIN_ODD_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__GM_GAIN_ODD_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__TIA_GAIN_ODD_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__SLM_XLNA_ODD_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__BQ_GAIN_ODD_102___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__XLNA_GAIN_EVEN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__LNA_GAIN_EVEN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__GM_GAIN_EVEN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__TIA_GAIN_EVEN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__SLM_XLNA_EVEN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__BQ_GAIN_EVEN_102___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__XLNA_GAIN_ODD_102___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__XLNA_GAIN_ODD_102___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__LNA_GAIN_ODD_102___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__LNA_GAIN_ODD_102___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__GM_GAIN_ODD_102___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__GM_GAIN_ODD_102___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__TIA_GAIN_ODD_102___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__TIA_GAIN_ODD_102___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__SLM_XLNA_ODD_102___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__SLM_XLNA_ODD_102___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__BQ_GAIN_ODD_102___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__BQ_GAIN_ODD_102___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__XLNA_GAIN_EVEN_102___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__XLNA_GAIN_EVEN_102___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__LNA_GAIN_EVEN_102___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__LNA_GAIN_EVEN_102___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__GM_GAIN_EVEN_102___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__GM_GAIN_EVEN_102___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__TIA_GAIN_EVEN_102___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__TIA_GAIN_EVEN_102___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__SLM_XLNA_EVEN_102___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__SLM_XLNA_EVEN_102___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__BQ_GAIN_EVEN_102___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102__BQ_GAIN_EVEN_102___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_102___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103 (0x005FD19C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__XLNA_GAIN_ODD_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__LNA_GAIN_ODD_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__GM_GAIN_ODD_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__TIA_GAIN_ODD_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__SLM_XLNA_ODD_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__BQ_GAIN_ODD_103___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__XLNA_GAIN_EVEN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__LNA_GAIN_EVEN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__GM_GAIN_EVEN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__TIA_GAIN_EVEN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__SLM_XLNA_EVEN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__BQ_GAIN_EVEN_103___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__XLNA_GAIN_ODD_103___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__XLNA_GAIN_ODD_103___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__LNA_GAIN_ODD_103___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__LNA_GAIN_ODD_103___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__GM_GAIN_ODD_103___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__GM_GAIN_ODD_103___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__TIA_GAIN_ODD_103___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__TIA_GAIN_ODD_103___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__SLM_XLNA_ODD_103___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__SLM_XLNA_ODD_103___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__BQ_GAIN_ODD_103___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__BQ_GAIN_ODD_103___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__XLNA_GAIN_EVEN_103___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__XLNA_GAIN_EVEN_103___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__LNA_GAIN_EVEN_103___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__LNA_GAIN_EVEN_103___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__GM_GAIN_EVEN_103___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__GM_GAIN_EVEN_103___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__TIA_GAIN_EVEN_103___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__TIA_GAIN_EVEN_103___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__SLM_XLNA_EVEN_103___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__SLM_XLNA_EVEN_103___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__BQ_GAIN_EVEN_103___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103__BQ_GAIN_EVEN_103___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_103___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104 (0x005FD1A0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__XLNA_GAIN_ODD_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__LNA_GAIN_ODD_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__GM_GAIN_ODD_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__TIA_GAIN_ODD_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__SLM_XLNA_ODD_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__BQ_GAIN_ODD_104___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__XLNA_GAIN_EVEN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__LNA_GAIN_EVEN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__GM_GAIN_EVEN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__TIA_GAIN_EVEN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__SLM_XLNA_EVEN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__BQ_GAIN_EVEN_104___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__XLNA_GAIN_ODD_104___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__XLNA_GAIN_ODD_104___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__LNA_GAIN_ODD_104___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__LNA_GAIN_ODD_104___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__GM_GAIN_ODD_104___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__GM_GAIN_ODD_104___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__TIA_GAIN_ODD_104___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__TIA_GAIN_ODD_104___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__SLM_XLNA_ODD_104___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__SLM_XLNA_ODD_104___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__BQ_GAIN_ODD_104___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__BQ_GAIN_ODD_104___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__XLNA_GAIN_EVEN_104___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__XLNA_GAIN_EVEN_104___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__LNA_GAIN_EVEN_104___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__LNA_GAIN_EVEN_104___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__GM_GAIN_EVEN_104___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__GM_GAIN_EVEN_104___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__TIA_GAIN_EVEN_104___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__TIA_GAIN_EVEN_104___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__SLM_XLNA_EVEN_104___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__SLM_XLNA_EVEN_104___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__BQ_GAIN_EVEN_104___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104__BQ_GAIN_EVEN_104___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_104___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105 (0x005FD1A4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__XLNA_GAIN_ODD_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__LNA_GAIN_ODD_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__GM_GAIN_ODD_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__TIA_GAIN_ODD_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__SLM_XLNA_ODD_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__BQ_GAIN_ODD_105___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__XLNA_GAIN_EVEN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__LNA_GAIN_EVEN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__GM_GAIN_EVEN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__TIA_GAIN_EVEN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__SLM_XLNA_EVEN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__BQ_GAIN_EVEN_105___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__XLNA_GAIN_ODD_105___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__XLNA_GAIN_ODD_105___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__LNA_GAIN_ODD_105___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__LNA_GAIN_ODD_105___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__GM_GAIN_ODD_105___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__GM_GAIN_ODD_105___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__TIA_GAIN_ODD_105___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__TIA_GAIN_ODD_105___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__SLM_XLNA_ODD_105___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__SLM_XLNA_ODD_105___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__BQ_GAIN_ODD_105___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__BQ_GAIN_ODD_105___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__XLNA_GAIN_EVEN_105___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__XLNA_GAIN_EVEN_105___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__LNA_GAIN_EVEN_105___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__LNA_GAIN_EVEN_105___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__GM_GAIN_EVEN_105___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__GM_GAIN_EVEN_105___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__TIA_GAIN_EVEN_105___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__TIA_GAIN_EVEN_105___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__SLM_XLNA_EVEN_105___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__SLM_XLNA_EVEN_105___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__BQ_GAIN_EVEN_105___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105__BQ_GAIN_EVEN_105___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_105___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106 (0x005FD1A8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__XLNA_GAIN_ODD_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__LNA_GAIN_ODD_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__GM_GAIN_ODD_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__TIA_GAIN_ODD_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__SLM_XLNA_ODD_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__BQ_GAIN_ODD_106___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__XLNA_GAIN_EVEN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__LNA_GAIN_EVEN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__GM_GAIN_EVEN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__TIA_GAIN_EVEN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__SLM_XLNA_EVEN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__BQ_GAIN_EVEN_106___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__XLNA_GAIN_ODD_106___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__XLNA_GAIN_ODD_106___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__LNA_GAIN_ODD_106___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__LNA_GAIN_ODD_106___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__GM_GAIN_ODD_106___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__GM_GAIN_ODD_106___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__TIA_GAIN_ODD_106___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__TIA_GAIN_ODD_106___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__SLM_XLNA_ODD_106___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__SLM_XLNA_ODD_106___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__BQ_GAIN_ODD_106___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__BQ_GAIN_ODD_106___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__XLNA_GAIN_EVEN_106___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__XLNA_GAIN_EVEN_106___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__LNA_GAIN_EVEN_106___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__LNA_GAIN_EVEN_106___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__GM_GAIN_EVEN_106___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__GM_GAIN_EVEN_106___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__TIA_GAIN_EVEN_106___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__TIA_GAIN_EVEN_106___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__SLM_XLNA_EVEN_106___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__SLM_XLNA_EVEN_106___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__BQ_GAIN_EVEN_106___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106__BQ_GAIN_EVEN_106___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_106___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107 (0x005FD1AC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__XLNA_GAIN_ODD_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__LNA_GAIN_ODD_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__GM_GAIN_ODD_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__TIA_GAIN_ODD_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__SLM_XLNA_ODD_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__BQ_GAIN_ODD_107___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__XLNA_GAIN_EVEN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__LNA_GAIN_EVEN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__GM_GAIN_EVEN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__TIA_GAIN_EVEN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__SLM_XLNA_EVEN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__BQ_GAIN_EVEN_107___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__XLNA_GAIN_ODD_107___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__XLNA_GAIN_ODD_107___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__LNA_GAIN_ODD_107___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__LNA_GAIN_ODD_107___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__GM_GAIN_ODD_107___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__GM_GAIN_ODD_107___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__TIA_GAIN_ODD_107___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__TIA_GAIN_ODD_107___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__SLM_XLNA_ODD_107___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__SLM_XLNA_ODD_107___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__BQ_GAIN_ODD_107___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__BQ_GAIN_ODD_107___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__XLNA_GAIN_EVEN_107___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__XLNA_GAIN_EVEN_107___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__LNA_GAIN_EVEN_107___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__LNA_GAIN_EVEN_107___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__GM_GAIN_EVEN_107___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__GM_GAIN_EVEN_107___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__TIA_GAIN_EVEN_107___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__TIA_GAIN_EVEN_107___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__SLM_XLNA_EVEN_107___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__SLM_XLNA_EVEN_107___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__BQ_GAIN_EVEN_107___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107__BQ_GAIN_EVEN_107___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_107___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108 (0x005FD1B0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__XLNA_GAIN_ODD_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__LNA_GAIN_ODD_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__GM_GAIN_ODD_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__TIA_GAIN_ODD_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__SLM_XLNA_ODD_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__BQ_GAIN_ODD_108___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__XLNA_GAIN_EVEN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__LNA_GAIN_EVEN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__GM_GAIN_EVEN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__TIA_GAIN_EVEN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__SLM_XLNA_EVEN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__BQ_GAIN_EVEN_108___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__XLNA_GAIN_ODD_108___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__XLNA_GAIN_ODD_108___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__LNA_GAIN_ODD_108___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__LNA_GAIN_ODD_108___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__GM_GAIN_ODD_108___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__GM_GAIN_ODD_108___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__TIA_GAIN_ODD_108___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__TIA_GAIN_ODD_108___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__SLM_XLNA_ODD_108___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__SLM_XLNA_ODD_108___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__BQ_GAIN_ODD_108___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__BQ_GAIN_ODD_108___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__XLNA_GAIN_EVEN_108___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__XLNA_GAIN_EVEN_108___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__LNA_GAIN_EVEN_108___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__LNA_GAIN_EVEN_108___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__GM_GAIN_EVEN_108___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__GM_GAIN_EVEN_108___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__TIA_GAIN_EVEN_108___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__TIA_GAIN_EVEN_108___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__SLM_XLNA_EVEN_108___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__SLM_XLNA_EVEN_108___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__BQ_GAIN_EVEN_108___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108__BQ_GAIN_EVEN_108___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_108___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109 (0x005FD1B4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__XLNA_GAIN_ODD_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__LNA_GAIN_ODD_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__GM_GAIN_ODD_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__TIA_GAIN_ODD_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__SLM_XLNA_ODD_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__BQ_GAIN_ODD_109___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__XLNA_GAIN_EVEN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__LNA_GAIN_EVEN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__GM_GAIN_EVEN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__TIA_GAIN_EVEN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__SLM_XLNA_EVEN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__BQ_GAIN_EVEN_109___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__XLNA_GAIN_ODD_109___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__XLNA_GAIN_ODD_109___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__LNA_GAIN_ODD_109___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__LNA_GAIN_ODD_109___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__GM_GAIN_ODD_109___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__GM_GAIN_ODD_109___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__TIA_GAIN_ODD_109___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__TIA_GAIN_ODD_109___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__SLM_XLNA_ODD_109___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__SLM_XLNA_ODD_109___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__BQ_GAIN_ODD_109___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__BQ_GAIN_ODD_109___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__XLNA_GAIN_EVEN_109___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__XLNA_GAIN_EVEN_109___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__LNA_GAIN_EVEN_109___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__LNA_GAIN_EVEN_109___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__GM_GAIN_EVEN_109___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__GM_GAIN_EVEN_109___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__TIA_GAIN_EVEN_109___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__TIA_GAIN_EVEN_109___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__SLM_XLNA_EVEN_109___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__SLM_XLNA_EVEN_109___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__BQ_GAIN_EVEN_109___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109__BQ_GAIN_EVEN_109___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_109___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110 (0x005FD1B8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__XLNA_GAIN_ODD_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__LNA_GAIN_ODD_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__GM_GAIN_ODD_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__TIA_GAIN_ODD_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__SLM_XLNA_ODD_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__BQ_GAIN_ODD_110___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__XLNA_GAIN_EVEN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__LNA_GAIN_EVEN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__GM_GAIN_EVEN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__TIA_GAIN_EVEN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__SLM_XLNA_EVEN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__BQ_GAIN_EVEN_110___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__XLNA_GAIN_ODD_110___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__XLNA_GAIN_ODD_110___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__LNA_GAIN_ODD_110___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__LNA_GAIN_ODD_110___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__GM_GAIN_ODD_110___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__GM_GAIN_ODD_110___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__TIA_GAIN_ODD_110___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__TIA_GAIN_ODD_110___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__SLM_XLNA_ODD_110___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__SLM_XLNA_ODD_110___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__BQ_GAIN_ODD_110___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__BQ_GAIN_ODD_110___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__XLNA_GAIN_EVEN_110___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__XLNA_GAIN_EVEN_110___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__LNA_GAIN_EVEN_110___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__LNA_GAIN_EVEN_110___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__GM_GAIN_EVEN_110___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__GM_GAIN_EVEN_110___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__TIA_GAIN_EVEN_110___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__TIA_GAIN_EVEN_110___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__SLM_XLNA_EVEN_110___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__SLM_XLNA_EVEN_110___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__BQ_GAIN_EVEN_110___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110__BQ_GAIN_EVEN_110___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_110___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111 (0x005FD1BC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__XLNA_GAIN_ODD_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__LNA_GAIN_ODD_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__GM_GAIN_ODD_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__TIA_GAIN_ODD_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__SLM_XLNA_ODD_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__BQ_GAIN_ODD_111___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__XLNA_GAIN_EVEN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__LNA_GAIN_EVEN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__GM_GAIN_EVEN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__TIA_GAIN_EVEN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__SLM_XLNA_EVEN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__BQ_GAIN_EVEN_111___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__XLNA_GAIN_ODD_111___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__XLNA_GAIN_ODD_111___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__LNA_GAIN_ODD_111___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__LNA_GAIN_ODD_111___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__GM_GAIN_ODD_111___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__GM_GAIN_ODD_111___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__TIA_GAIN_ODD_111___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__TIA_GAIN_ODD_111___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__SLM_XLNA_ODD_111___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__SLM_XLNA_ODD_111___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__BQ_GAIN_ODD_111___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__BQ_GAIN_ODD_111___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__XLNA_GAIN_EVEN_111___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__XLNA_GAIN_EVEN_111___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__LNA_GAIN_EVEN_111___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__LNA_GAIN_EVEN_111___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__GM_GAIN_EVEN_111___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__GM_GAIN_EVEN_111___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__TIA_GAIN_EVEN_111___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__TIA_GAIN_EVEN_111___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__SLM_XLNA_EVEN_111___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__SLM_XLNA_EVEN_111___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__BQ_GAIN_EVEN_111___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111__BQ_GAIN_EVEN_111___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_111___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112 (0x005FD1C0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__XLNA_GAIN_ODD_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__LNA_GAIN_ODD_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__GM_GAIN_ODD_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__TIA_GAIN_ODD_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__SLM_XLNA_ODD_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__BQ_GAIN_ODD_112___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__XLNA_GAIN_EVEN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__LNA_GAIN_EVEN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__GM_GAIN_EVEN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__TIA_GAIN_EVEN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__SLM_XLNA_EVEN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__BQ_GAIN_EVEN_112___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__XLNA_GAIN_ODD_112___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__XLNA_GAIN_ODD_112___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__LNA_GAIN_ODD_112___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__LNA_GAIN_ODD_112___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__GM_GAIN_ODD_112___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__GM_GAIN_ODD_112___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__TIA_GAIN_ODD_112___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__TIA_GAIN_ODD_112___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__SLM_XLNA_ODD_112___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__SLM_XLNA_ODD_112___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__BQ_GAIN_ODD_112___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__BQ_GAIN_ODD_112___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__XLNA_GAIN_EVEN_112___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__XLNA_GAIN_EVEN_112___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__LNA_GAIN_EVEN_112___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__LNA_GAIN_EVEN_112___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__GM_GAIN_EVEN_112___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__GM_GAIN_EVEN_112___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__TIA_GAIN_EVEN_112___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__TIA_GAIN_EVEN_112___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__SLM_XLNA_EVEN_112___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__SLM_XLNA_EVEN_112___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__BQ_GAIN_EVEN_112___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112__BQ_GAIN_EVEN_112___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_112___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113 (0x005FD1C4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__XLNA_GAIN_ODD_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__LNA_GAIN_ODD_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__GM_GAIN_ODD_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__TIA_GAIN_ODD_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__SLM_XLNA_ODD_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__BQ_GAIN_ODD_113___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__XLNA_GAIN_EVEN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__LNA_GAIN_EVEN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__GM_GAIN_EVEN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__TIA_GAIN_EVEN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__SLM_XLNA_EVEN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__BQ_GAIN_EVEN_113___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__XLNA_GAIN_ODD_113___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__XLNA_GAIN_ODD_113___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__LNA_GAIN_ODD_113___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__LNA_GAIN_ODD_113___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__GM_GAIN_ODD_113___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__GM_GAIN_ODD_113___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__TIA_GAIN_ODD_113___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__TIA_GAIN_ODD_113___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__SLM_XLNA_ODD_113___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__SLM_XLNA_ODD_113___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__BQ_GAIN_ODD_113___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__BQ_GAIN_ODD_113___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__XLNA_GAIN_EVEN_113___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__XLNA_GAIN_EVEN_113___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__LNA_GAIN_EVEN_113___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__LNA_GAIN_EVEN_113___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__GM_GAIN_EVEN_113___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__GM_GAIN_EVEN_113___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__TIA_GAIN_EVEN_113___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__TIA_GAIN_EVEN_113___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__SLM_XLNA_EVEN_113___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__SLM_XLNA_EVEN_113___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__BQ_GAIN_EVEN_113___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113__BQ_GAIN_EVEN_113___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_113___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114 (0x005FD1C8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__XLNA_GAIN_ODD_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__LNA_GAIN_ODD_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__GM_GAIN_ODD_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__TIA_GAIN_ODD_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__SLM_XLNA_ODD_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__BQ_GAIN_ODD_114___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__XLNA_GAIN_EVEN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__LNA_GAIN_EVEN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__GM_GAIN_EVEN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__TIA_GAIN_EVEN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__SLM_XLNA_EVEN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__BQ_GAIN_EVEN_114___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__XLNA_GAIN_ODD_114___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__XLNA_GAIN_ODD_114___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__LNA_GAIN_ODD_114___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__LNA_GAIN_ODD_114___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__GM_GAIN_ODD_114___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__GM_GAIN_ODD_114___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__TIA_GAIN_ODD_114___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__TIA_GAIN_ODD_114___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__SLM_XLNA_ODD_114___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__SLM_XLNA_ODD_114___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__BQ_GAIN_ODD_114___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__BQ_GAIN_ODD_114___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__XLNA_GAIN_EVEN_114___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__XLNA_GAIN_EVEN_114___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__LNA_GAIN_EVEN_114___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__LNA_GAIN_EVEN_114___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__GM_GAIN_EVEN_114___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__GM_GAIN_EVEN_114___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__TIA_GAIN_EVEN_114___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__TIA_GAIN_EVEN_114___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__SLM_XLNA_EVEN_114___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__SLM_XLNA_EVEN_114___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__BQ_GAIN_EVEN_114___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114__BQ_GAIN_EVEN_114___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_114___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115 (0x005FD1CC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__XLNA_GAIN_ODD_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__LNA_GAIN_ODD_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__GM_GAIN_ODD_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__TIA_GAIN_ODD_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__SLM_XLNA_ODD_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__BQ_GAIN_ODD_115___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__XLNA_GAIN_EVEN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__LNA_GAIN_EVEN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__GM_GAIN_EVEN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__TIA_GAIN_EVEN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__SLM_XLNA_EVEN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__BQ_GAIN_EVEN_115___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__XLNA_GAIN_ODD_115___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__XLNA_GAIN_ODD_115___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__LNA_GAIN_ODD_115___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__LNA_GAIN_ODD_115___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__GM_GAIN_ODD_115___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__GM_GAIN_ODD_115___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__TIA_GAIN_ODD_115___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__TIA_GAIN_ODD_115___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__SLM_XLNA_ODD_115___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__SLM_XLNA_ODD_115___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__BQ_GAIN_ODD_115___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__BQ_GAIN_ODD_115___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__XLNA_GAIN_EVEN_115___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__XLNA_GAIN_EVEN_115___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__LNA_GAIN_EVEN_115___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__LNA_GAIN_EVEN_115___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__GM_GAIN_EVEN_115___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__GM_GAIN_EVEN_115___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__TIA_GAIN_EVEN_115___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__TIA_GAIN_EVEN_115___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__SLM_XLNA_EVEN_115___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__SLM_XLNA_EVEN_115___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__BQ_GAIN_EVEN_115___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115__BQ_GAIN_EVEN_115___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_115___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116 (0x005FD1D0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__XLNA_GAIN_ODD_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__LNA_GAIN_ODD_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__GM_GAIN_ODD_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__TIA_GAIN_ODD_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__SLM_XLNA_ODD_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__BQ_GAIN_ODD_116___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__XLNA_GAIN_EVEN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__LNA_GAIN_EVEN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__GM_GAIN_EVEN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__TIA_GAIN_EVEN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__SLM_XLNA_EVEN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__BQ_GAIN_EVEN_116___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__XLNA_GAIN_ODD_116___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__XLNA_GAIN_ODD_116___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__LNA_GAIN_ODD_116___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__LNA_GAIN_ODD_116___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__GM_GAIN_ODD_116___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__GM_GAIN_ODD_116___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__TIA_GAIN_ODD_116___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__TIA_GAIN_ODD_116___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__SLM_XLNA_ODD_116___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__SLM_XLNA_ODD_116___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__BQ_GAIN_ODD_116___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__BQ_GAIN_ODD_116___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__XLNA_GAIN_EVEN_116___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__XLNA_GAIN_EVEN_116___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__LNA_GAIN_EVEN_116___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__LNA_GAIN_EVEN_116___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__GM_GAIN_EVEN_116___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__GM_GAIN_EVEN_116___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__TIA_GAIN_EVEN_116___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__TIA_GAIN_EVEN_116___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__SLM_XLNA_EVEN_116___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__SLM_XLNA_EVEN_116___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__BQ_GAIN_EVEN_116___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116__BQ_GAIN_EVEN_116___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_116___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117 (0x005FD1D4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__XLNA_GAIN_ODD_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__LNA_GAIN_ODD_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__GM_GAIN_ODD_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__TIA_GAIN_ODD_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__SLM_XLNA_ODD_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__BQ_GAIN_ODD_117___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__XLNA_GAIN_EVEN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__LNA_GAIN_EVEN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__GM_GAIN_EVEN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__TIA_GAIN_EVEN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__SLM_XLNA_EVEN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__BQ_GAIN_EVEN_117___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__XLNA_GAIN_ODD_117___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__XLNA_GAIN_ODD_117___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__LNA_GAIN_ODD_117___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__LNA_GAIN_ODD_117___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__GM_GAIN_ODD_117___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__GM_GAIN_ODD_117___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__TIA_GAIN_ODD_117___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__TIA_GAIN_ODD_117___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__SLM_XLNA_ODD_117___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__SLM_XLNA_ODD_117___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__BQ_GAIN_ODD_117___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__BQ_GAIN_ODD_117___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__XLNA_GAIN_EVEN_117___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__XLNA_GAIN_EVEN_117___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__LNA_GAIN_EVEN_117___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__LNA_GAIN_EVEN_117___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__GM_GAIN_EVEN_117___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__GM_GAIN_EVEN_117___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__TIA_GAIN_EVEN_117___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__TIA_GAIN_EVEN_117___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__SLM_XLNA_EVEN_117___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__SLM_XLNA_EVEN_117___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__BQ_GAIN_EVEN_117___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117__BQ_GAIN_EVEN_117___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_117___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118 (0x005FD1D8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__XLNA_GAIN_ODD_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__LNA_GAIN_ODD_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__GM_GAIN_ODD_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__TIA_GAIN_ODD_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__SLM_XLNA_ODD_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__BQ_GAIN_ODD_118___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__XLNA_GAIN_EVEN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__LNA_GAIN_EVEN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__GM_GAIN_EVEN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__TIA_GAIN_EVEN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__SLM_XLNA_EVEN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__BQ_GAIN_EVEN_118___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__XLNA_GAIN_ODD_118___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__XLNA_GAIN_ODD_118___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__LNA_GAIN_ODD_118___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__LNA_GAIN_ODD_118___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__GM_GAIN_ODD_118___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__GM_GAIN_ODD_118___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__TIA_GAIN_ODD_118___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__TIA_GAIN_ODD_118___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__SLM_XLNA_ODD_118___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__SLM_XLNA_ODD_118___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__BQ_GAIN_ODD_118___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__BQ_GAIN_ODD_118___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__XLNA_GAIN_EVEN_118___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__XLNA_GAIN_EVEN_118___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__LNA_GAIN_EVEN_118___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__LNA_GAIN_EVEN_118___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__GM_GAIN_EVEN_118___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__GM_GAIN_EVEN_118___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__TIA_GAIN_EVEN_118___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__TIA_GAIN_EVEN_118___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__SLM_XLNA_EVEN_118___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__SLM_XLNA_EVEN_118___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__BQ_GAIN_EVEN_118___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118__BQ_GAIN_EVEN_118___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_118___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119 (0x005FD1DC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__XLNA_GAIN_ODD_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__LNA_GAIN_ODD_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__GM_GAIN_ODD_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__TIA_GAIN_ODD_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__SLM_XLNA_ODD_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__BQ_GAIN_ODD_119___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__XLNA_GAIN_EVEN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__LNA_GAIN_EVEN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__GM_GAIN_EVEN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__TIA_GAIN_EVEN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__SLM_XLNA_EVEN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__BQ_GAIN_EVEN_119___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__XLNA_GAIN_ODD_119___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__XLNA_GAIN_ODD_119___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__LNA_GAIN_ODD_119___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__LNA_GAIN_ODD_119___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__GM_GAIN_ODD_119___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__GM_GAIN_ODD_119___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__TIA_GAIN_ODD_119___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__TIA_GAIN_ODD_119___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__SLM_XLNA_ODD_119___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__SLM_XLNA_ODD_119___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__BQ_GAIN_ODD_119___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__BQ_GAIN_ODD_119___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__XLNA_GAIN_EVEN_119___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__XLNA_GAIN_EVEN_119___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__LNA_GAIN_EVEN_119___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__LNA_GAIN_EVEN_119___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__GM_GAIN_EVEN_119___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__GM_GAIN_EVEN_119___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__TIA_GAIN_EVEN_119___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__TIA_GAIN_EVEN_119___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__SLM_XLNA_EVEN_119___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__SLM_XLNA_EVEN_119___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__BQ_GAIN_EVEN_119___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119__BQ_GAIN_EVEN_119___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_119___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120 (0x005FD1E0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__XLNA_GAIN_ODD_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__LNA_GAIN_ODD_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__GM_GAIN_ODD_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__TIA_GAIN_ODD_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__SLM_XLNA_ODD_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__BQ_GAIN_ODD_120___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__XLNA_GAIN_EVEN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__LNA_GAIN_EVEN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__GM_GAIN_EVEN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__TIA_GAIN_EVEN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__SLM_XLNA_EVEN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__BQ_GAIN_EVEN_120___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__XLNA_GAIN_ODD_120___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__XLNA_GAIN_ODD_120___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__LNA_GAIN_ODD_120___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__LNA_GAIN_ODD_120___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__GM_GAIN_ODD_120___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__GM_GAIN_ODD_120___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__TIA_GAIN_ODD_120___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__TIA_GAIN_ODD_120___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__SLM_XLNA_ODD_120___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__SLM_XLNA_ODD_120___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__BQ_GAIN_ODD_120___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__BQ_GAIN_ODD_120___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__XLNA_GAIN_EVEN_120___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__XLNA_GAIN_EVEN_120___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__LNA_GAIN_EVEN_120___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__LNA_GAIN_EVEN_120___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__GM_GAIN_EVEN_120___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__GM_GAIN_EVEN_120___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__TIA_GAIN_EVEN_120___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__TIA_GAIN_EVEN_120___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__SLM_XLNA_EVEN_120___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__SLM_XLNA_EVEN_120___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__BQ_GAIN_EVEN_120___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120__BQ_GAIN_EVEN_120___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_120___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121 (0x005FD1E4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__XLNA_GAIN_ODD_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__LNA_GAIN_ODD_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__GM_GAIN_ODD_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__TIA_GAIN_ODD_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__SLM_XLNA_ODD_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__BQ_GAIN_ODD_121___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__XLNA_GAIN_EVEN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__LNA_GAIN_EVEN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__GM_GAIN_EVEN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__TIA_GAIN_EVEN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__SLM_XLNA_EVEN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__BQ_GAIN_EVEN_121___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__XLNA_GAIN_ODD_121___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__XLNA_GAIN_ODD_121___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__LNA_GAIN_ODD_121___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__LNA_GAIN_ODD_121___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__GM_GAIN_ODD_121___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__GM_GAIN_ODD_121___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__TIA_GAIN_ODD_121___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__TIA_GAIN_ODD_121___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__SLM_XLNA_ODD_121___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__SLM_XLNA_ODD_121___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__BQ_GAIN_ODD_121___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__BQ_GAIN_ODD_121___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__XLNA_GAIN_EVEN_121___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__XLNA_GAIN_EVEN_121___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__LNA_GAIN_EVEN_121___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__LNA_GAIN_EVEN_121___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__GM_GAIN_EVEN_121___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__GM_GAIN_EVEN_121___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__TIA_GAIN_EVEN_121___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__TIA_GAIN_EVEN_121___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__SLM_XLNA_EVEN_121___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__SLM_XLNA_EVEN_121___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__BQ_GAIN_EVEN_121___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121__BQ_GAIN_EVEN_121___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_121___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122 (0x005FD1E8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__XLNA_GAIN_ODD_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__LNA_GAIN_ODD_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__GM_GAIN_ODD_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__TIA_GAIN_ODD_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__SLM_XLNA_ODD_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__BQ_GAIN_ODD_122___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__XLNA_GAIN_EVEN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__LNA_GAIN_EVEN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__GM_GAIN_EVEN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__TIA_GAIN_EVEN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__SLM_XLNA_EVEN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__BQ_GAIN_EVEN_122___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__XLNA_GAIN_ODD_122___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__XLNA_GAIN_ODD_122___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__LNA_GAIN_ODD_122___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__LNA_GAIN_ODD_122___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__GM_GAIN_ODD_122___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__GM_GAIN_ODD_122___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__TIA_GAIN_ODD_122___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__TIA_GAIN_ODD_122___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__SLM_XLNA_ODD_122___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__SLM_XLNA_ODD_122___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__BQ_GAIN_ODD_122___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__BQ_GAIN_ODD_122___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__XLNA_GAIN_EVEN_122___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__XLNA_GAIN_EVEN_122___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__LNA_GAIN_EVEN_122___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__LNA_GAIN_EVEN_122___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__GM_GAIN_EVEN_122___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__GM_GAIN_EVEN_122___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__TIA_GAIN_EVEN_122___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__TIA_GAIN_EVEN_122___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__SLM_XLNA_EVEN_122___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__SLM_XLNA_EVEN_122___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__BQ_GAIN_EVEN_122___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122__BQ_GAIN_EVEN_122___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_122___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123 (0x005FD1EC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__XLNA_GAIN_ODD_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__LNA_GAIN_ODD_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__GM_GAIN_ODD_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__TIA_GAIN_ODD_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__SLM_XLNA_ODD_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__BQ_GAIN_ODD_123___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__XLNA_GAIN_EVEN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__LNA_GAIN_EVEN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__GM_GAIN_EVEN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__TIA_GAIN_EVEN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__SLM_XLNA_EVEN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__BQ_GAIN_EVEN_123___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__XLNA_GAIN_ODD_123___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__XLNA_GAIN_ODD_123___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__LNA_GAIN_ODD_123___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__LNA_GAIN_ODD_123___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__GM_GAIN_ODD_123___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__GM_GAIN_ODD_123___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__TIA_GAIN_ODD_123___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__TIA_GAIN_ODD_123___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__SLM_XLNA_ODD_123___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__SLM_XLNA_ODD_123___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__BQ_GAIN_ODD_123___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__BQ_GAIN_ODD_123___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__XLNA_GAIN_EVEN_123___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__XLNA_GAIN_EVEN_123___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__LNA_GAIN_EVEN_123___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__LNA_GAIN_EVEN_123___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__GM_GAIN_EVEN_123___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__GM_GAIN_EVEN_123___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__TIA_GAIN_EVEN_123___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__TIA_GAIN_EVEN_123___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__SLM_XLNA_EVEN_123___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__SLM_XLNA_EVEN_123___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__BQ_GAIN_EVEN_123___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123__BQ_GAIN_EVEN_123___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_123___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124 (0x005FD1F0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__XLNA_GAIN_ODD_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__LNA_GAIN_ODD_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__GM_GAIN_ODD_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__TIA_GAIN_ODD_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__SLM_XLNA_ODD_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__BQ_GAIN_ODD_124___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__XLNA_GAIN_EVEN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__LNA_GAIN_EVEN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__GM_GAIN_EVEN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__TIA_GAIN_EVEN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__SLM_XLNA_EVEN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__BQ_GAIN_EVEN_124___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__XLNA_GAIN_ODD_124___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__XLNA_GAIN_ODD_124___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__LNA_GAIN_ODD_124___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__LNA_GAIN_ODD_124___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__GM_GAIN_ODD_124___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__GM_GAIN_ODD_124___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__TIA_GAIN_ODD_124___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__TIA_GAIN_ODD_124___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__SLM_XLNA_ODD_124___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__SLM_XLNA_ODD_124___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__BQ_GAIN_ODD_124___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__BQ_GAIN_ODD_124___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__XLNA_GAIN_EVEN_124___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__XLNA_GAIN_EVEN_124___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__LNA_GAIN_EVEN_124___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__LNA_GAIN_EVEN_124___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__GM_GAIN_EVEN_124___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__GM_GAIN_EVEN_124___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__TIA_GAIN_EVEN_124___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__TIA_GAIN_EVEN_124___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__SLM_XLNA_EVEN_124___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__SLM_XLNA_EVEN_124___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__BQ_GAIN_EVEN_124___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124__BQ_GAIN_EVEN_124___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_124___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125 (0x005FD1F4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__XLNA_GAIN_ODD_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__LNA_GAIN_ODD_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__GM_GAIN_ODD_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__TIA_GAIN_ODD_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__SLM_XLNA_ODD_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__BQ_GAIN_ODD_125___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__XLNA_GAIN_EVEN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__LNA_GAIN_EVEN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__GM_GAIN_EVEN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__TIA_GAIN_EVEN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__SLM_XLNA_EVEN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__BQ_GAIN_EVEN_125___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__XLNA_GAIN_ODD_125___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__XLNA_GAIN_ODD_125___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__LNA_GAIN_ODD_125___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__LNA_GAIN_ODD_125___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__GM_GAIN_ODD_125___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__GM_GAIN_ODD_125___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__TIA_GAIN_ODD_125___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__TIA_GAIN_ODD_125___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__SLM_XLNA_ODD_125___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__SLM_XLNA_ODD_125___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__BQ_GAIN_ODD_125___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__BQ_GAIN_ODD_125___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__XLNA_GAIN_EVEN_125___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__XLNA_GAIN_EVEN_125___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__LNA_GAIN_EVEN_125___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__LNA_GAIN_EVEN_125___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__GM_GAIN_EVEN_125___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__GM_GAIN_EVEN_125___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__TIA_GAIN_EVEN_125___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__TIA_GAIN_EVEN_125___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__SLM_XLNA_EVEN_125___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__SLM_XLNA_EVEN_125___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__BQ_GAIN_EVEN_125___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125__BQ_GAIN_EVEN_125___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_125___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126 (0x005FD1F8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__XLNA_GAIN_ODD_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__LNA_GAIN_ODD_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__GM_GAIN_ODD_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__TIA_GAIN_ODD_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__SLM_XLNA_ODD_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__BQ_GAIN_ODD_126___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__XLNA_GAIN_EVEN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__LNA_GAIN_EVEN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__GM_GAIN_EVEN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__TIA_GAIN_EVEN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__SLM_XLNA_EVEN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__BQ_GAIN_EVEN_126___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__XLNA_GAIN_ODD_126___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__XLNA_GAIN_ODD_126___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__LNA_GAIN_ODD_126___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__LNA_GAIN_ODD_126___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__GM_GAIN_ODD_126___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__GM_GAIN_ODD_126___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__TIA_GAIN_ODD_126___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__TIA_GAIN_ODD_126___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__SLM_XLNA_ODD_126___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__SLM_XLNA_ODD_126___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__BQ_GAIN_ODD_126___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__BQ_GAIN_ODD_126___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__XLNA_GAIN_EVEN_126___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__XLNA_GAIN_EVEN_126___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__LNA_GAIN_EVEN_126___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__LNA_GAIN_EVEN_126___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__GM_GAIN_EVEN_126___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__GM_GAIN_EVEN_126___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__TIA_GAIN_EVEN_126___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__TIA_GAIN_EVEN_126___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__SLM_XLNA_EVEN_126___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__SLM_XLNA_EVEN_126___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__BQ_GAIN_EVEN_126___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126__BQ_GAIN_EVEN_126___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_126___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127 (0x005FD1FC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__XLNA_GAIN_ODD_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__LNA_GAIN_ODD_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__GM_GAIN_ODD_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__TIA_GAIN_ODD_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__SLM_XLNA_ODD_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__BQ_GAIN_ODD_127___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__XLNA_GAIN_EVEN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__LNA_GAIN_EVEN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__GM_GAIN_EVEN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__TIA_GAIN_EVEN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__SLM_XLNA_EVEN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__BQ_GAIN_EVEN_127___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__XLNA_GAIN_ODD_127___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__XLNA_GAIN_ODD_127___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__LNA_GAIN_ODD_127___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__LNA_GAIN_ODD_127___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__GM_GAIN_ODD_127___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__GM_GAIN_ODD_127___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__TIA_GAIN_ODD_127___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__TIA_GAIN_ODD_127___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__SLM_XLNA_ODD_127___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__SLM_XLNA_ODD_127___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__BQ_GAIN_ODD_127___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__BQ_GAIN_ODD_127___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__XLNA_GAIN_EVEN_127___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__XLNA_GAIN_EVEN_127___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__LNA_GAIN_EVEN_127___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__LNA_GAIN_EVEN_127___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__GM_GAIN_EVEN_127___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__GM_GAIN_EVEN_127___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__TIA_GAIN_EVEN_127___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__TIA_GAIN_EVEN_127___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__SLM_XLNA_EVEN_127___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__SLM_XLNA_EVEN_127___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__BQ_GAIN_EVEN_127___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127__BQ_GAIN_EVEN_127___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_127___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128 (0x005FD200) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__XLNA_GAIN_ODD_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__LNA_GAIN_ODD_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__GM_GAIN_ODD_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__TIA_GAIN_ODD_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__SLM_XLNA_ODD_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__BQ_GAIN_ODD_128___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__XLNA_GAIN_EVEN_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__LNA_GAIN_EVEN_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__GM_GAIN_EVEN_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__TIA_GAIN_EVEN_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__SLM_XLNA_EVEN_128___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__BQ_GAIN_EVEN_128___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__XLNA_GAIN_ODD_128___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__XLNA_GAIN_ODD_128___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__LNA_GAIN_ODD_128___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__LNA_GAIN_ODD_128___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__GM_GAIN_ODD_128___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__GM_GAIN_ODD_128___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__TIA_GAIN_ODD_128___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__TIA_GAIN_ODD_128___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__SLM_XLNA_ODD_128___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__SLM_XLNA_ODD_128___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__BQ_GAIN_ODD_128___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__BQ_GAIN_ODD_128___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__XLNA_GAIN_EVEN_128___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__XLNA_GAIN_EVEN_128___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__LNA_GAIN_EVEN_128___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__LNA_GAIN_EVEN_128___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__GM_GAIN_EVEN_128___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__GM_GAIN_EVEN_128___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__TIA_GAIN_EVEN_128___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__TIA_GAIN_EVEN_128___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__SLM_XLNA_EVEN_128___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__SLM_XLNA_EVEN_128___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__BQ_GAIN_EVEN_128___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128__BQ_GAIN_EVEN_128___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_128___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129 (0x005FD204) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__XLNA_GAIN_ODD_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__LNA_GAIN_ODD_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__GM_GAIN_ODD_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__TIA_GAIN_ODD_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__SLM_XLNA_ODD_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__BQ_GAIN_ODD_129___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__XLNA_GAIN_EVEN_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__LNA_GAIN_EVEN_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__GM_GAIN_EVEN_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__TIA_GAIN_EVEN_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__SLM_XLNA_EVEN_129___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__BQ_GAIN_EVEN_129___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__XLNA_GAIN_ODD_129___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__XLNA_GAIN_ODD_129___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__LNA_GAIN_ODD_129___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__LNA_GAIN_ODD_129___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__GM_GAIN_ODD_129___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__GM_GAIN_ODD_129___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__TIA_GAIN_ODD_129___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__TIA_GAIN_ODD_129___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__SLM_XLNA_ODD_129___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__SLM_XLNA_ODD_129___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__BQ_GAIN_ODD_129___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__BQ_GAIN_ODD_129___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__XLNA_GAIN_EVEN_129___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__XLNA_GAIN_EVEN_129___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__LNA_GAIN_EVEN_129___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__LNA_GAIN_EVEN_129___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__GM_GAIN_EVEN_129___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__GM_GAIN_EVEN_129___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__TIA_GAIN_EVEN_129___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__TIA_GAIN_EVEN_129___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__SLM_XLNA_EVEN_129___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__SLM_XLNA_EVEN_129___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__BQ_GAIN_EVEN_129___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129__BQ_GAIN_EVEN_129___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_129___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130 (0x005FD208) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__XLNA_GAIN_ODD_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__LNA_GAIN_ODD_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__GM_GAIN_ODD_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__TIA_GAIN_ODD_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__SLM_XLNA_ODD_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__BQ_GAIN_ODD_130___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__XLNA_GAIN_EVEN_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__LNA_GAIN_EVEN_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__GM_GAIN_EVEN_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__TIA_GAIN_EVEN_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__SLM_XLNA_EVEN_130___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__BQ_GAIN_EVEN_130___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__XLNA_GAIN_ODD_130___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__XLNA_GAIN_ODD_130___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__LNA_GAIN_ODD_130___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__LNA_GAIN_ODD_130___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__GM_GAIN_ODD_130___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__GM_GAIN_ODD_130___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__TIA_GAIN_ODD_130___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__TIA_GAIN_ODD_130___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__SLM_XLNA_ODD_130___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__SLM_XLNA_ODD_130___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__BQ_GAIN_ODD_130___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__BQ_GAIN_ODD_130___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__XLNA_GAIN_EVEN_130___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__XLNA_GAIN_EVEN_130___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__LNA_GAIN_EVEN_130___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__LNA_GAIN_EVEN_130___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__GM_GAIN_EVEN_130___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__GM_GAIN_EVEN_130___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__TIA_GAIN_EVEN_130___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__TIA_GAIN_EVEN_130___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__SLM_XLNA_EVEN_130___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__SLM_XLNA_EVEN_130___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__BQ_GAIN_EVEN_130___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130__BQ_GAIN_EVEN_130___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_130___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131 (0x005FD20C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__XLNA_GAIN_ODD_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__LNA_GAIN_ODD_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__GM_GAIN_ODD_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__TIA_GAIN_ODD_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__SLM_XLNA_ODD_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__BQ_GAIN_ODD_131___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__XLNA_GAIN_EVEN_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__LNA_GAIN_EVEN_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__GM_GAIN_EVEN_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__TIA_GAIN_EVEN_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__SLM_XLNA_EVEN_131___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__BQ_GAIN_EVEN_131___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__XLNA_GAIN_ODD_131___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__XLNA_GAIN_ODD_131___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__LNA_GAIN_ODD_131___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__LNA_GAIN_ODD_131___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__GM_GAIN_ODD_131___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__GM_GAIN_ODD_131___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__TIA_GAIN_ODD_131___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__TIA_GAIN_ODD_131___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__SLM_XLNA_ODD_131___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__SLM_XLNA_ODD_131___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__BQ_GAIN_ODD_131___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__BQ_GAIN_ODD_131___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__XLNA_GAIN_EVEN_131___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__XLNA_GAIN_EVEN_131___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__LNA_GAIN_EVEN_131___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__LNA_GAIN_EVEN_131___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__GM_GAIN_EVEN_131___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__GM_GAIN_EVEN_131___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__TIA_GAIN_EVEN_131___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__TIA_GAIN_EVEN_131___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__SLM_XLNA_EVEN_131___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__SLM_XLNA_EVEN_131___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__BQ_GAIN_EVEN_131___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131__BQ_GAIN_EVEN_131___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_131___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132 (0x005FD210) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__XLNA_GAIN_ODD_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__LNA_GAIN_ODD_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__GM_GAIN_ODD_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__TIA_GAIN_ODD_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__SLM_XLNA_ODD_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__BQ_GAIN_ODD_132___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__XLNA_GAIN_EVEN_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__LNA_GAIN_EVEN_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__GM_GAIN_EVEN_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__TIA_GAIN_EVEN_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__SLM_XLNA_EVEN_132___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__BQ_GAIN_EVEN_132___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__XLNA_GAIN_ODD_132___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__XLNA_GAIN_ODD_132___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__LNA_GAIN_ODD_132___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__LNA_GAIN_ODD_132___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__GM_GAIN_ODD_132___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__GM_GAIN_ODD_132___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__TIA_GAIN_ODD_132___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__TIA_GAIN_ODD_132___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__SLM_XLNA_ODD_132___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__SLM_XLNA_ODD_132___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__BQ_GAIN_ODD_132___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__BQ_GAIN_ODD_132___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__XLNA_GAIN_EVEN_132___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__XLNA_GAIN_EVEN_132___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__LNA_GAIN_EVEN_132___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__LNA_GAIN_EVEN_132___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__GM_GAIN_EVEN_132___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__GM_GAIN_EVEN_132___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__TIA_GAIN_EVEN_132___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__TIA_GAIN_EVEN_132___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__SLM_XLNA_EVEN_132___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__SLM_XLNA_EVEN_132___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__BQ_GAIN_EVEN_132___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132__BQ_GAIN_EVEN_132___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_132___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133 (0x005FD214) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__XLNA_GAIN_ODD_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__LNA_GAIN_ODD_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__GM_GAIN_ODD_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__TIA_GAIN_ODD_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__SLM_XLNA_ODD_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__BQ_GAIN_ODD_133___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__XLNA_GAIN_EVEN_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__LNA_GAIN_EVEN_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__GM_GAIN_EVEN_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__TIA_GAIN_EVEN_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__SLM_XLNA_EVEN_133___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__BQ_GAIN_EVEN_133___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__XLNA_GAIN_ODD_133___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__XLNA_GAIN_ODD_133___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__LNA_GAIN_ODD_133___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__LNA_GAIN_ODD_133___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__GM_GAIN_ODD_133___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__GM_GAIN_ODD_133___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__TIA_GAIN_ODD_133___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__TIA_GAIN_ODD_133___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__SLM_XLNA_ODD_133___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__SLM_XLNA_ODD_133___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__BQ_GAIN_ODD_133___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__BQ_GAIN_ODD_133___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__XLNA_GAIN_EVEN_133___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__XLNA_GAIN_EVEN_133___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__LNA_GAIN_EVEN_133___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__LNA_GAIN_EVEN_133___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__GM_GAIN_EVEN_133___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__GM_GAIN_EVEN_133___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__TIA_GAIN_EVEN_133___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__TIA_GAIN_EVEN_133___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__SLM_XLNA_EVEN_133___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__SLM_XLNA_EVEN_133___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__BQ_GAIN_EVEN_133___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133__BQ_GAIN_EVEN_133___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_133___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134 (0x005FD218) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__XLNA_GAIN_ODD_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__LNA_GAIN_ODD_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__GM_GAIN_ODD_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__TIA_GAIN_ODD_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__SLM_XLNA_ODD_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__BQ_GAIN_ODD_134___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__XLNA_GAIN_EVEN_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__LNA_GAIN_EVEN_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__GM_GAIN_EVEN_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__TIA_GAIN_EVEN_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__SLM_XLNA_EVEN_134___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__BQ_GAIN_EVEN_134___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__XLNA_GAIN_ODD_134___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__XLNA_GAIN_ODD_134___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__LNA_GAIN_ODD_134___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__LNA_GAIN_ODD_134___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__GM_GAIN_ODD_134___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__GM_GAIN_ODD_134___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__TIA_GAIN_ODD_134___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__TIA_GAIN_ODD_134___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__SLM_XLNA_ODD_134___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__SLM_XLNA_ODD_134___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__BQ_GAIN_ODD_134___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__BQ_GAIN_ODD_134___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__XLNA_GAIN_EVEN_134___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__XLNA_GAIN_EVEN_134___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__LNA_GAIN_EVEN_134___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__LNA_GAIN_EVEN_134___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__GM_GAIN_EVEN_134___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__GM_GAIN_EVEN_134___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__TIA_GAIN_EVEN_134___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__TIA_GAIN_EVEN_134___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__SLM_XLNA_EVEN_134___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__SLM_XLNA_EVEN_134___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__BQ_GAIN_EVEN_134___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134__BQ_GAIN_EVEN_134___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_134___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135 (0x005FD21C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__XLNA_GAIN_ODD_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__LNA_GAIN_ODD_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__GM_GAIN_ODD_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__TIA_GAIN_ODD_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__SLM_XLNA_ODD_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__BQ_GAIN_ODD_135___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__XLNA_GAIN_EVEN_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__LNA_GAIN_EVEN_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__GM_GAIN_EVEN_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__TIA_GAIN_EVEN_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__SLM_XLNA_EVEN_135___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__BQ_GAIN_EVEN_135___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__XLNA_GAIN_ODD_135___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__XLNA_GAIN_ODD_135___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__LNA_GAIN_ODD_135___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__LNA_GAIN_ODD_135___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__GM_GAIN_ODD_135___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__GM_GAIN_ODD_135___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__TIA_GAIN_ODD_135___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__TIA_GAIN_ODD_135___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__SLM_XLNA_ODD_135___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__SLM_XLNA_ODD_135___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__BQ_GAIN_ODD_135___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__BQ_GAIN_ODD_135___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__XLNA_GAIN_EVEN_135___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__XLNA_GAIN_EVEN_135___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__LNA_GAIN_EVEN_135___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__LNA_GAIN_EVEN_135___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__GM_GAIN_EVEN_135___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__GM_GAIN_EVEN_135___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__TIA_GAIN_EVEN_135___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__TIA_GAIN_EVEN_135___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__SLM_XLNA_EVEN_135___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__SLM_XLNA_EVEN_135___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__BQ_GAIN_EVEN_135___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135__BQ_GAIN_EVEN_135___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_135___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136 (0x005FD220) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__XLNA_GAIN_ODD_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__LNA_GAIN_ODD_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__GM_GAIN_ODD_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__TIA_GAIN_ODD_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__SLM_XLNA_ODD_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__BQ_GAIN_ODD_136___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__XLNA_GAIN_EVEN_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__LNA_GAIN_EVEN_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__GM_GAIN_EVEN_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__TIA_GAIN_EVEN_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__SLM_XLNA_EVEN_136___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__BQ_GAIN_EVEN_136___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__XLNA_GAIN_ODD_136___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__XLNA_GAIN_ODD_136___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__LNA_GAIN_ODD_136___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__LNA_GAIN_ODD_136___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__GM_GAIN_ODD_136___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__GM_GAIN_ODD_136___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__TIA_GAIN_ODD_136___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__TIA_GAIN_ODD_136___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__SLM_XLNA_ODD_136___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__SLM_XLNA_ODD_136___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__BQ_GAIN_ODD_136___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__BQ_GAIN_ODD_136___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__XLNA_GAIN_EVEN_136___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__XLNA_GAIN_EVEN_136___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__LNA_GAIN_EVEN_136___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__LNA_GAIN_EVEN_136___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__GM_GAIN_EVEN_136___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__GM_GAIN_EVEN_136___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__TIA_GAIN_EVEN_136___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__TIA_GAIN_EVEN_136___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__SLM_XLNA_EVEN_136___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__SLM_XLNA_EVEN_136___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__BQ_GAIN_EVEN_136___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136__BQ_GAIN_EVEN_136___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_136___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137 (0x005FD224) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__XLNA_GAIN_ODD_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__LNA_GAIN_ODD_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__GM_GAIN_ODD_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__TIA_GAIN_ODD_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__SLM_XLNA_ODD_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__BQ_GAIN_ODD_137___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__XLNA_GAIN_EVEN_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__LNA_GAIN_EVEN_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__GM_GAIN_EVEN_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__TIA_GAIN_EVEN_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__SLM_XLNA_EVEN_137___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__BQ_GAIN_EVEN_137___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__XLNA_GAIN_ODD_137___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__XLNA_GAIN_ODD_137___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__LNA_GAIN_ODD_137___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__LNA_GAIN_ODD_137___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__GM_GAIN_ODD_137___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__GM_GAIN_ODD_137___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__TIA_GAIN_ODD_137___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__TIA_GAIN_ODD_137___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__SLM_XLNA_ODD_137___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__SLM_XLNA_ODD_137___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__BQ_GAIN_ODD_137___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__BQ_GAIN_ODD_137___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__XLNA_GAIN_EVEN_137___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__XLNA_GAIN_EVEN_137___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__LNA_GAIN_EVEN_137___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__LNA_GAIN_EVEN_137___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__GM_GAIN_EVEN_137___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__GM_GAIN_EVEN_137___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__TIA_GAIN_EVEN_137___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__TIA_GAIN_EVEN_137___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__SLM_XLNA_EVEN_137___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__SLM_XLNA_EVEN_137___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__BQ_GAIN_EVEN_137___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137__BQ_GAIN_EVEN_137___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_137___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138 (0x005FD228) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__XLNA_GAIN_ODD_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__LNA_GAIN_ODD_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__GM_GAIN_ODD_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__TIA_GAIN_ODD_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__SLM_XLNA_ODD_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__BQ_GAIN_ODD_138___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__XLNA_GAIN_EVEN_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__LNA_GAIN_EVEN_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__GM_GAIN_EVEN_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__TIA_GAIN_EVEN_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__SLM_XLNA_EVEN_138___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__BQ_GAIN_EVEN_138___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__XLNA_GAIN_ODD_138___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__XLNA_GAIN_ODD_138___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__LNA_GAIN_ODD_138___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__LNA_GAIN_ODD_138___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__GM_GAIN_ODD_138___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__GM_GAIN_ODD_138___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__TIA_GAIN_ODD_138___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__TIA_GAIN_ODD_138___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__SLM_XLNA_ODD_138___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__SLM_XLNA_ODD_138___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__BQ_GAIN_ODD_138___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__BQ_GAIN_ODD_138___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__XLNA_GAIN_EVEN_138___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__XLNA_GAIN_EVEN_138___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__LNA_GAIN_EVEN_138___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__LNA_GAIN_EVEN_138___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__GM_GAIN_EVEN_138___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__GM_GAIN_EVEN_138___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__TIA_GAIN_EVEN_138___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__TIA_GAIN_EVEN_138___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__SLM_XLNA_EVEN_138___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__SLM_XLNA_EVEN_138___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__BQ_GAIN_EVEN_138___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138__BQ_GAIN_EVEN_138___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_138___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139 (0x005FD22C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__XLNA_GAIN_ODD_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__LNA_GAIN_ODD_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__GM_GAIN_ODD_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__TIA_GAIN_ODD_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__SLM_XLNA_ODD_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__BQ_GAIN_ODD_139___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__XLNA_GAIN_EVEN_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__LNA_GAIN_EVEN_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__GM_GAIN_EVEN_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__TIA_GAIN_EVEN_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__SLM_XLNA_EVEN_139___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__BQ_GAIN_EVEN_139___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__XLNA_GAIN_ODD_139___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__XLNA_GAIN_ODD_139___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__LNA_GAIN_ODD_139___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__LNA_GAIN_ODD_139___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__GM_GAIN_ODD_139___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__GM_GAIN_ODD_139___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__TIA_GAIN_ODD_139___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__TIA_GAIN_ODD_139___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__SLM_XLNA_ODD_139___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__SLM_XLNA_ODD_139___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__BQ_GAIN_ODD_139___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__BQ_GAIN_ODD_139___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__XLNA_GAIN_EVEN_139___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__XLNA_GAIN_EVEN_139___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__LNA_GAIN_EVEN_139___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__LNA_GAIN_EVEN_139___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__GM_GAIN_EVEN_139___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__GM_GAIN_EVEN_139___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__TIA_GAIN_EVEN_139___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__TIA_GAIN_EVEN_139___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__SLM_XLNA_EVEN_139___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__SLM_XLNA_EVEN_139___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__BQ_GAIN_EVEN_139___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139__BQ_GAIN_EVEN_139___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_139___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140 (0x005FD230) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__XLNA_GAIN_ODD_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__LNA_GAIN_ODD_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__GM_GAIN_ODD_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__TIA_GAIN_ODD_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__SLM_XLNA_ODD_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__BQ_GAIN_ODD_140___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__XLNA_GAIN_EVEN_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__LNA_GAIN_EVEN_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__GM_GAIN_EVEN_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__TIA_GAIN_EVEN_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__SLM_XLNA_EVEN_140___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__BQ_GAIN_EVEN_140___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__XLNA_GAIN_ODD_140___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__XLNA_GAIN_ODD_140___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__LNA_GAIN_ODD_140___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__LNA_GAIN_ODD_140___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__GM_GAIN_ODD_140___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__GM_GAIN_ODD_140___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__TIA_GAIN_ODD_140___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__TIA_GAIN_ODD_140___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__SLM_XLNA_ODD_140___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__SLM_XLNA_ODD_140___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__BQ_GAIN_ODD_140___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__BQ_GAIN_ODD_140___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__XLNA_GAIN_EVEN_140___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__XLNA_GAIN_EVEN_140___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__LNA_GAIN_EVEN_140___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__LNA_GAIN_EVEN_140___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__GM_GAIN_EVEN_140___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__GM_GAIN_EVEN_140___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__TIA_GAIN_EVEN_140___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__TIA_GAIN_EVEN_140___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__SLM_XLNA_EVEN_140___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__SLM_XLNA_EVEN_140___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__BQ_GAIN_EVEN_140___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140__BQ_GAIN_EVEN_140___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_140___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141 (0x005FD234) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__XLNA_GAIN_ODD_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__LNA_GAIN_ODD_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__GM_GAIN_ODD_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__TIA_GAIN_ODD_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__SLM_XLNA_ODD_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__BQ_GAIN_ODD_141___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__XLNA_GAIN_EVEN_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__LNA_GAIN_EVEN_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__GM_GAIN_EVEN_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__TIA_GAIN_EVEN_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__SLM_XLNA_EVEN_141___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__BQ_GAIN_EVEN_141___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__XLNA_GAIN_ODD_141___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__XLNA_GAIN_ODD_141___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__LNA_GAIN_ODD_141___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__LNA_GAIN_ODD_141___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__GM_GAIN_ODD_141___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__GM_GAIN_ODD_141___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__TIA_GAIN_ODD_141___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__TIA_GAIN_ODD_141___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__SLM_XLNA_ODD_141___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__SLM_XLNA_ODD_141___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__BQ_GAIN_ODD_141___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__BQ_GAIN_ODD_141___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__XLNA_GAIN_EVEN_141___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__XLNA_GAIN_EVEN_141___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__LNA_GAIN_EVEN_141___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__LNA_GAIN_EVEN_141___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__GM_GAIN_EVEN_141___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__GM_GAIN_EVEN_141___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__TIA_GAIN_EVEN_141___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__TIA_GAIN_EVEN_141___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__SLM_XLNA_EVEN_141___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__SLM_XLNA_EVEN_141___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__BQ_GAIN_EVEN_141___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141__BQ_GAIN_EVEN_141___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_141___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142 (0x005FD238) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__XLNA_GAIN_ODD_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__LNA_GAIN_ODD_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__GM_GAIN_ODD_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__TIA_GAIN_ODD_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__SLM_XLNA_ODD_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__BQ_GAIN_ODD_142___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__XLNA_GAIN_EVEN_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__LNA_GAIN_EVEN_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__GM_GAIN_EVEN_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__TIA_GAIN_EVEN_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__SLM_XLNA_EVEN_142___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__BQ_GAIN_EVEN_142___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__XLNA_GAIN_ODD_142___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__XLNA_GAIN_ODD_142___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__LNA_GAIN_ODD_142___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__LNA_GAIN_ODD_142___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__GM_GAIN_ODD_142___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__GM_GAIN_ODD_142___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__TIA_GAIN_ODD_142___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__TIA_GAIN_ODD_142___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__SLM_XLNA_ODD_142___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__SLM_XLNA_ODD_142___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__BQ_GAIN_ODD_142___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__BQ_GAIN_ODD_142___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__XLNA_GAIN_EVEN_142___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__XLNA_GAIN_EVEN_142___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__LNA_GAIN_EVEN_142___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__LNA_GAIN_EVEN_142___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__GM_GAIN_EVEN_142___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__GM_GAIN_EVEN_142___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__TIA_GAIN_EVEN_142___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__TIA_GAIN_EVEN_142___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__SLM_XLNA_EVEN_142___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__SLM_XLNA_EVEN_142___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__BQ_GAIN_EVEN_142___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142__BQ_GAIN_EVEN_142___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_142___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143 (0x005FD23C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__XLNA_GAIN_ODD_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__LNA_GAIN_ODD_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__GM_GAIN_ODD_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__TIA_GAIN_ODD_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__SLM_XLNA_ODD_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__BQ_GAIN_ODD_143___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__XLNA_GAIN_EVEN_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__LNA_GAIN_EVEN_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__GM_GAIN_EVEN_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__TIA_GAIN_EVEN_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__SLM_XLNA_EVEN_143___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__BQ_GAIN_EVEN_143___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__XLNA_GAIN_ODD_143___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__XLNA_GAIN_ODD_143___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__LNA_GAIN_ODD_143___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__LNA_GAIN_ODD_143___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__GM_GAIN_ODD_143___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__GM_GAIN_ODD_143___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__TIA_GAIN_ODD_143___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__TIA_GAIN_ODD_143___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__SLM_XLNA_ODD_143___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__SLM_XLNA_ODD_143___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__BQ_GAIN_ODD_143___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__BQ_GAIN_ODD_143___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__XLNA_GAIN_EVEN_143___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__XLNA_GAIN_EVEN_143___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__LNA_GAIN_EVEN_143___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__LNA_GAIN_EVEN_143___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__GM_GAIN_EVEN_143___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__GM_GAIN_EVEN_143___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__TIA_GAIN_EVEN_143___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__TIA_GAIN_EVEN_143___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__SLM_XLNA_EVEN_143___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__SLM_XLNA_EVEN_143___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__BQ_GAIN_EVEN_143___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143__BQ_GAIN_EVEN_143___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_143___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144 (0x005FD240) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__XLNA_GAIN_ODD_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__LNA_GAIN_ODD_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__GM_GAIN_ODD_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__TIA_GAIN_ODD_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__SLM_XLNA_ODD_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__BQ_GAIN_ODD_144___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__XLNA_GAIN_EVEN_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__LNA_GAIN_EVEN_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__GM_GAIN_EVEN_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__TIA_GAIN_EVEN_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__SLM_XLNA_EVEN_144___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__BQ_GAIN_EVEN_144___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__XLNA_GAIN_ODD_144___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__XLNA_GAIN_ODD_144___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__LNA_GAIN_ODD_144___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__LNA_GAIN_ODD_144___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__GM_GAIN_ODD_144___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__GM_GAIN_ODD_144___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__TIA_GAIN_ODD_144___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__TIA_GAIN_ODD_144___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__SLM_XLNA_ODD_144___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__SLM_XLNA_ODD_144___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__BQ_GAIN_ODD_144___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__BQ_GAIN_ODD_144___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__XLNA_GAIN_EVEN_144___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__XLNA_GAIN_EVEN_144___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__LNA_GAIN_EVEN_144___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__LNA_GAIN_EVEN_144___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__GM_GAIN_EVEN_144___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__GM_GAIN_EVEN_144___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__TIA_GAIN_EVEN_144___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__TIA_GAIN_EVEN_144___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__SLM_XLNA_EVEN_144___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__SLM_XLNA_EVEN_144___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__BQ_GAIN_EVEN_144___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144__BQ_GAIN_EVEN_144___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_144___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145 (0x005FD244) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__XLNA_GAIN_ODD_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__LNA_GAIN_ODD_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__GM_GAIN_ODD_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__TIA_GAIN_ODD_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__SLM_XLNA_ODD_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__BQ_GAIN_ODD_145___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__XLNA_GAIN_EVEN_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__LNA_GAIN_EVEN_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__GM_GAIN_EVEN_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__TIA_GAIN_EVEN_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__SLM_XLNA_EVEN_145___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__BQ_GAIN_EVEN_145___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__XLNA_GAIN_ODD_145___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__XLNA_GAIN_ODD_145___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__LNA_GAIN_ODD_145___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__LNA_GAIN_ODD_145___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__GM_GAIN_ODD_145___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__GM_GAIN_ODD_145___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__TIA_GAIN_ODD_145___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__TIA_GAIN_ODD_145___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__SLM_XLNA_ODD_145___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__SLM_XLNA_ODD_145___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__BQ_GAIN_ODD_145___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__BQ_GAIN_ODD_145___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__XLNA_GAIN_EVEN_145___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__XLNA_GAIN_EVEN_145___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__LNA_GAIN_EVEN_145___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__LNA_GAIN_EVEN_145___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__GM_GAIN_EVEN_145___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__GM_GAIN_EVEN_145___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__TIA_GAIN_EVEN_145___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__TIA_GAIN_EVEN_145___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__SLM_XLNA_EVEN_145___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__SLM_XLNA_EVEN_145___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__BQ_GAIN_EVEN_145___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145__BQ_GAIN_EVEN_145___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_145___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146 (0x005FD248) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__XLNA_GAIN_ODD_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__LNA_GAIN_ODD_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__GM_GAIN_ODD_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__TIA_GAIN_ODD_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__SLM_XLNA_ODD_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__BQ_GAIN_ODD_146___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__XLNA_GAIN_EVEN_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__LNA_GAIN_EVEN_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__GM_GAIN_EVEN_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__TIA_GAIN_EVEN_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__SLM_XLNA_EVEN_146___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__BQ_GAIN_EVEN_146___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__XLNA_GAIN_ODD_146___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__XLNA_GAIN_ODD_146___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__LNA_GAIN_ODD_146___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__LNA_GAIN_ODD_146___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__GM_GAIN_ODD_146___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__GM_GAIN_ODD_146___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__TIA_GAIN_ODD_146___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__TIA_GAIN_ODD_146___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__SLM_XLNA_ODD_146___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__SLM_XLNA_ODD_146___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__BQ_GAIN_ODD_146___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__BQ_GAIN_ODD_146___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__XLNA_GAIN_EVEN_146___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__XLNA_GAIN_EVEN_146___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__LNA_GAIN_EVEN_146___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__LNA_GAIN_EVEN_146___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__GM_GAIN_EVEN_146___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__GM_GAIN_EVEN_146___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__TIA_GAIN_EVEN_146___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__TIA_GAIN_EVEN_146___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__SLM_XLNA_EVEN_146___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__SLM_XLNA_EVEN_146___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__BQ_GAIN_EVEN_146___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146__BQ_GAIN_EVEN_146___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_146___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147 (0x005FD24C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__XLNA_GAIN_ODD_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__LNA_GAIN_ODD_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__GM_GAIN_ODD_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__TIA_GAIN_ODD_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__SLM_XLNA_ODD_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__BQ_GAIN_ODD_147___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__XLNA_GAIN_EVEN_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__LNA_GAIN_EVEN_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__GM_GAIN_EVEN_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__TIA_GAIN_EVEN_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__SLM_XLNA_EVEN_147___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__BQ_GAIN_EVEN_147___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__XLNA_GAIN_ODD_147___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__XLNA_GAIN_ODD_147___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__LNA_GAIN_ODD_147___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__LNA_GAIN_ODD_147___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__GM_GAIN_ODD_147___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__GM_GAIN_ODD_147___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__TIA_GAIN_ODD_147___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__TIA_GAIN_ODD_147___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__SLM_XLNA_ODD_147___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__SLM_XLNA_ODD_147___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__BQ_GAIN_ODD_147___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__BQ_GAIN_ODD_147___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__XLNA_GAIN_EVEN_147___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__XLNA_GAIN_EVEN_147___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__LNA_GAIN_EVEN_147___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__LNA_GAIN_EVEN_147___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__GM_GAIN_EVEN_147___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__GM_GAIN_EVEN_147___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__TIA_GAIN_EVEN_147___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__TIA_GAIN_EVEN_147___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__SLM_XLNA_EVEN_147___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__SLM_XLNA_EVEN_147___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__BQ_GAIN_EVEN_147___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147__BQ_GAIN_EVEN_147___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_147___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148 (0x005FD250) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__XLNA_GAIN_ODD_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__LNA_GAIN_ODD_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__GM_GAIN_ODD_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__TIA_GAIN_ODD_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__SLM_XLNA_ODD_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__BQ_GAIN_ODD_148___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__XLNA_GAIN_EVEN_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__LNA_GAIN_EVEN_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__GM_GAIN_EVEN_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__TIA_GAIN_EVEN_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__SLM_XLNA_EVEN_148___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__BQ_GAIN_EVEN_148___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__XLNA_GAIN_ODD_148___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__XLNA_GAIN_ODD_148___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__LNA_GAIN_ODD_148___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__LNA_GAIN_ODD_148___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__GM_GAIN_ODD_148___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__GM_GAIN_ODD_148___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__TIA_GAIN_ODD_148___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__TIA_GAIN_ODD_148___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__SLM_XLNA_ODD_148___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__SLM_XLNA_ODD_148___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__BQ_GAIN_ODD_148___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__BQ_GAIN_ODD_148___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__XLNA_GAIN_EVEN_148___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__XLNA_GAIN_EVEN_148___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__LNA_GAIN_EVEN_148___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__LNA_GAIN_EVEN_148___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__GM_GAIN_EVEN_148___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__GM_GAIN_EVEN_148___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__TIA_GAIN_EVEN_148___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__TIA_GAIN_EVEN_148___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__SLM_XLNA_EVEN_148___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__SLM_XLNA_EVEN_148___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__BQ_GAIN_EVEN_148___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148__BQ_GAIN_EVEN_148___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_148___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149 (0x005FD254) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__XLNA_GAIN_ODD_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__LNA_GAIN_ODD_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__GM_GAIN_ODD_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__TIA_GAIN_ODD_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__SLM_XLNA_ODD_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__BQ_GAIN_ODD_149___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__XLNA_GAIN_EVEN_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__LNA_GAIN_EVEN_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__GM_GAIN_EVEN_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__TIA_GAIN_EVEN_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__SLM_XLNA_EVEN_149___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__BQ_GAIN_EVEN_149___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__XLNA_GAIN_ODD_149___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__XLNA_GAIN_ODD_149___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__LNA_GAIN_ODD_149___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__LNA_GAIN_ODD_149___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__GM_GAIN_ODD_149___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__GM_GAIN_ODD_149___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__TIA_GAIN_ODD_149___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__TIA_GAIN_ODD_149___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__SLM_XLNA_ODD_149___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__SLM_XLNA_ODD_149___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__BQ_GAIN_ODD_149___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__BQ_GAIN_ODD_149___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__XLNA_GAIN_EVEN_149___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__XLNA_GAIN_EVEN_149___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__LNA_GAIN_EVEN_149___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__LNA_GAIN_EVEN_149___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__GM_GAIN_EVEN_149___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__GM_GAIN_EVEN_149___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__TIA_GAIN_EVEN_149___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__TIA_GAIN_EVEN_149___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__SLM_XLNA_EVEN_149___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__SLM_XLNA_EVEN_149___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__BQ_GAIN_EVEN_149___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149__BQ_GAIN_EVEN_149___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_149___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150 (0x005FD258) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__XLNA_GAIN_ODD_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__LNA_GAIN_ODD_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__GM_GAIN_ODD_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__TIA_GAIN_ODD_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__SLM_XLNA_ODD_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__BQ_GAIN_ODD_150___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__XLNA_GAIN_EVEN_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__LNA_GAIN_EVEN_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__GM_GAIN_EVEN_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__TIA_GAIN_EVEN_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__SLM_XLNA_EVEN_150___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__BQ_GAIN_EVEN_150___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__XLNA_GAIN_ODD_150___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__XLNA_GAIN_ODD_150___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__LNA_GAIN_ODD_150___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__LNA_GAIN_ODD_150___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__GM_GAIN_ODD_150___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__GM_GAIN_ODD_150___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__TIA_GAIN_ODD_150___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__TIA_GAIN_ODD_150___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__SLM_XLNA_ODD_150___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__SLM_XLNA_ODD_150___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__BQ_GAIN_ODD_150___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__BQ_GAIN_ODD_150___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__XLNA_GAIN_EVEN_150___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__XLNA_GAIN_EVEN_150___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__LNA_GAIN_EVEN_150___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__LNA_GAIN_EVEN_150___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__GM_GAIN_EVEN_150___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__GM_GAIN_EVEN_150___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__TIA_GAIN_EVEN_150___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__TIA_GAIN_EVEN_150___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__SLM_XLNA_EVEN_150___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__SLM_XLNA_EVEN_150___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__BQ_GAIN_EVEN_150___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150__BQ_GAIN_EVEN_150___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_150___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151 (0x005FD25C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__XLNA_GAIN_ODD_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__LNA_GAIN_ODD_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__GM_GAIN_ODD_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__TIA_GAIN_ODD_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__SLM_XLNA_ODD_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__BQ_GAIN_ODD_151___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__XLNA_GAIN_EVEN_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__LNA_GAIN_EVEN_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__GM_GAIN_EVEN_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__TIA_GAIN_EVEN_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__SLM_XLNA_EVEN_151___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__BQ_GAIN_EVEN_151___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__XLNA_GAIN_ODD_151___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__XLNA_GAIN_ODD_151___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__LNA_GAIN_ODD_151___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__LNA_GAIN_ODD_151___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__GM_GAIN_ODD_151___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__GM_GAIN_ODD_151___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__TIA_GAIN_ODD_151___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__TIA_GAIN_ODD_151___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__SLM_XLNA_ODD_151___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__SLM_XLNA_ODD_151___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__BQ_GAIN_ODD_151___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__BQ_GAIN_ODD_151___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__XLNA_GAIN_EVEN_151___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__XLNA_GAIN_EVEN_151___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__LNA_GAIN_EVEN_151___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__LNA_GAIN_EVEN_151___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__GM_GAIN_EVEN_151___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__GM_GAIN_EVEN_151___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__TIA_GAIN_EVEN_151___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__TIA_GAIN_EVEN_151___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__SLM_XLNA_EVEN_151___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__SLM_XLNA_EVEN_151___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__BQ_GAIN_EVEN_151___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151__BQ_GAIN_EVEN_151___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_151___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152 (0x005FD260) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__XLNA_GAIN_ODD_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__LNA_GAIN_ODD_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__GM_GAIN_ODD_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__TIA_GAIN_ODD_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__SLM_XLNA_ODD_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__BQ_GAIN_ODD_152___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__XLNA_GAIN_EVEN_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__LNA_GAIN_EVEN_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__GM_GAIN_EVEN_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__TIA_GAIN_EVEN_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__SLM_XLNA_EVEN_152___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__BQ_GAIN_EVEN_152___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__XLNA_GAIN_ODD_152___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__XLNA_GAIN_ODD_152___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__LNA_GAIN_ODD_152___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__LNA_GAIN_ODD_152___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__GM_GAIN_ODD_152___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__GM_GAIN_ODD_152___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__TIA_GAIN_ODD_152___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__TIA_GAIN_ODD_152___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__SLM_XLNA_ODD_152___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__SLM_XLNA_ODD_152___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__BQ_GAIN_ODD_152___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__BQ_GAIN_ODD_152___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__XLNA_GAIN_EVEN_152___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__XLNA_GAIN_EVEN_152___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__LNA_GAIN_EVEN_152___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__LNA_GAIN_EVEN_152___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__GM_GAIN_EVEN_152___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__GM_GAIN_EVEN_152___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__TIA_GAIN_EVEN_152___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__TIA_GAIN_EVEN_152___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__SLM_XLNA_EVEN_152___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__SLM_XLNA_EVEN_152___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__BQ_GAIN_EVEN_152___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152__BQ_GAIN_EVEN_152___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_152___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153 (0x005FD264) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__XLNA_GAIN_ODD_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__LNA_GAIN_ODD_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__GM_GAIN_ODD_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__TIA_GAIN_ODD_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__SLM_XLNA_ODD_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__BQ_GAIN_ODD_153___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__XLNA_GAIN_EVEN_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__LNA_GAIN_EVEN_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__GM_GAIN_EVEN_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__TIA_GAIN_EVEN_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__SLM_XLNA_EVEN_153___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__BQ_GAIN_EVEN_153___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__XLNA_GAIN_ODD_153___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__XLNA_GAIN_ODD_153___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__LNA_GAIN_ODD_153___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__LNA_GAIN_ODD_153___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__GM_GAIN_ODD_153___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__GM_GAIN_ODD_153___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__TIA_GAIN_ODD_153___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__TIA_GAIN_ODD_153___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__SLM_XLNA_ODD_153___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__SLM_XLNA_ODD_153___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__BQ_GAIN_ODD_153___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__BQ_GAIN_ODD_153___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__XLNA_GAIN_EVEN_153___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__XLNA_GAIN_EVEN_153___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__LNA_GAIN_EVEN_153___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__LNA_GAIN_EVEN_153___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__GM_GAIN_EVEN_153___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__GM_GAIN_EVEN_153___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__TIA_GAIN_EVEN_153___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__TIA_GAIN_EVEN_153___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__SLM_XLNA_EVEN_153___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__SLM_XLNA_EVEN_153___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__BQ_GAIN_EVEN_153___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153__BQ_GAIN_EVEN_153___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_153___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154 (0x005FD268) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__XLNA_GAIN_ODD_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__LNA_GAIN_ODD_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__GM_GAIN_ODD_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__TIA_GAIN_ODD_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__SLM_XLNA_ODD_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__BQ_GAIN_ODD_154___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__XLNA_GAIN_EVEN_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__LNA_GAIN_EVEN_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__GM_GAIN_EVEN_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__TIA_GAIN_EVEN_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__SLM_XLNA_EVEN_154___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__BQ_GAIN_EVEN_154___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__XLNA_GAIN_ODD_154___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__XLNA_GAIN_ODD_154___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__LNA_GAIN_ODD_154___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__LNA_GAIN_ODD_154___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__GM_GAIN_ODD_154___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__GM_GAIN_ODD_154___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__TIA_GAIN_ODD_154___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__TIA_GAIN_ODD_154___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__SLM_XLNA_ODD_154___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__SLM_XLNA_ODD_154___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__BQ_GAIN_ODD_154___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__BQ_GAIN_ODD_154___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__XLNA_GAIN_EVEN_154___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__XLNA_GAIN_EVEN_154___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__LNA_GAIN_EVEN_154___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__LNA_GAIN_EVEN_154___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__GM_GAIN_EVEN_154___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__GM_GAIN_EVEN_154___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__TIA_GAIN_EVEN_154___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__TIA_GAIN_EVEN_154___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__SLM_XLNA_EVEN_154___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__SLM_XLNA_EVEN_154___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__BQ_GAIN_EVEN_154___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154__BQ_GAIN_EVEN_154___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_154___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155 (0x005FD26C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__XLNA_GAIN_ODD_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__LNA_GAIN_ODD_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__GM_GAIN_ODD_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__TIA_GAIN_ODD_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__SLM_XLNA_ODD_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__BQ_GAIN_ODD_155___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__XLNA_GAIN_EVEN_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__LNA_GAIN_EVEN_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__GM_GAIN_EVEN_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__TIA_GAIN_EVEN_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__SLM_XLNA_EVEN_155___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__BQ_GAIN_EVEN_155___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__XLNA_GAIN_ODD_155___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__XLNA_GAIN_ODD_155___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__LNA_GAIN_ODD_155___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__LNA_GAIN_ODD_155___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__GM_GAIN_ODD_155___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__GM_GAIN_ODD_155___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__TIA_GAIN_ODD_155___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__TIA_GAIN_ODD_155___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__SLM_XLNA_ODD_155___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__SLM_XLNA_ODD_155___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__BQ_GAIN_ODD_155___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__BQ_GAIN_ODD_155___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__XLNA_GAIN_EVEN_155___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__XLNA_GAIN_EVEN_155___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__LNA_GAIN_EVEN_155___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__LNA_GAIN_EVEN_155___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__GM_GAIN_EVEN_155___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__GM_GAIN_EVEN_155___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__TIA_GAIN_EVEN_155___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__TIA_GAIN_EVEN_155___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__SLM_XLNA_EVEN_155___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__SLM_XLNA_EVEN_155___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__BQ_GAIN_EVEN_155___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155__BQ_GAIN_EVEN_155___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_155___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156 (0x005FD270) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__XLNA_GAIN_ODD_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__LNA_GAIN_ODD_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__GM_GAIN_ODD_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__TIA_GAIN_ODD_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__SLM_XLNA_ODD_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__BQ_GAIN_ODD_156___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__XLNA_GAIN_EVEN_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__LNA_GAIN_EVEN_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__GM_GAIN_EVEN_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__TIA_GAIN_EVEN_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__SLM_XLNA_EVEN_156___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__BQ_GAIN_EVEN_156___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__XLNA_GAIN_ODD_156___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__XLNA_GAIN_ODD_156___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__LNA_GAIN_ODD_156___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__LNA_GAIN_ODD_156___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__GM_GAIN_ODD_156___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__GM_GAIN_ODD_156___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__TIA_GAIN_ODD_156___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__TIA_GAIN_ODD_156___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__SLM_XLNA_ODD_156___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__SLM_XLNA_ODD_156___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__BQ_GAIN_ODD_156___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__BQ_GAIN_ODD_156___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__XLNA_GAIN_EVEN_156___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__XLNA_GAIN_EVEN_156___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__LNA_GAIN_EVEN_156___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__LNA_GAIN_EVEN_156___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__GM_GAIN_EVEN_156___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__GM_GAIN_EVEN_156___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__TIA_GAIN_EVEN_156___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__TIA_GAIN_EVEN_156___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__SLM_XLNA_EVEN_156___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__SLM_XLNA_EVEN_156___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__BQ_GAIN_EVEN_156___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156__BQ_GAIN_EVEN_156___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_156___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157 (0x005FD274) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__XLNA_GAIN_ODD_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__LNA_GAIN_ODD_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__GM_GAIN_ODD_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__TIA_GAIN_ODD_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__SLM_XLNA_ODD_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__BQ_GAIN_ODD_157___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__XLNA_GAIN_EVEN_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__LNA_GAIN_EVEN_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__GM_GAIN_EVEN_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__TIA_GAIN_EVEN_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__SLM_XLNA_EVEN_157___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__BQ_GAIN_EVEN_157___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__XLNA_GAIN_ODD_157___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__XLNA_GAIN_ODD_157___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__LNA_GAIN_ODD_157___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__LNA_GAIN_ODD_157___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__GM_GAIN_ODD_157___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__GM_GAIN_ODD_157___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__TIA_GAIN_ODD_157___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__TIA_GAIN_ODD_157___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__SLM_XLNA_ODD_157___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__SLM_XLNA_ODD_157___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__BQ_GAIN_ODD_157___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__BQ_GAIN_ODD_157___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__XLNA_GAIN_EVEN_157___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__XLNA_GAIN_EVEN_157___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__LNA_GAIN_EVEN_157___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__LNA_GAIN_EVEN_157___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__GM_GAIN_EVEN_157___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__GM_GAIN_EVEN_157___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__TIA_GAIN_EVEN_157___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__TIA_GAIN_EVEN_157___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__SLM_XLNA_EVEN_157___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__SLM_XLNA_EVEN_157___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__BQ_GAIN_EVEN_157___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157__BQ_GAIN_EVEN_157___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_157___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158 (0x005FD278) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__XLNA_GAIN_ODD_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__LNA_GAIN_ODD_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__GM_GAIN_ODD_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__TIA_GAIN_ODD_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__SLM_XLNA_ODD_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__BQ_GAIN_ODD_158___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__XLNA_GAIN_EVEN_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__LNA_GAIN_EVEN_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__GM_GAIN_EVEN_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__TIA_GAIN_EVEN_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__SLM_XLNA_EVEN_158___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__BQ_GAIN_EVEN_158___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__XLNA_GAIN_ODD_158___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__XLNA_GAIN_ODD_158___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__LNA_GAIN_ODD_158___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__LNA_GAIN_ODD_158___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__GM_GAIN_ODD_158___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__GM_GAIN_ODD_158___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__TIA_GAIN_ODD_158___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__TIA_GAIN_ODD_158___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__SLM_XLNA_ODD_158___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__SLM_XLNA_ODD_158___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__BQ_GAIN_ODD_158___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__BQ_GAIN_ODD_158___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__XLNA_GAIN_EVEN_158___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__XLNA_GAIN_EVEN_158___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__LNA_GAIN_EVEN_158___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__LNA_GAIN_EVEN_158___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__GM_GAIN_EVEN_158___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__GM_GAIN_EVEN_158___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__TIA_GAIN_EVEN_158___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__TIA_GAIN_EVEN_158___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__SLM_XLNA_EVEN_158___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__SLM_XLNA_EVEN_158___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__BQ_GAIN_EVEN_158___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158__BQ_GAIN_EVEN_158___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_158___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159 (0x005FD27C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__XLNA_GAIN_ODD_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__LNA_GAIN_ODD_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__GM_GAIN_ODD_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__TIA_GAIN_ODD_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__SLM_XLNA_ODD_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__BQ_GAIN_ODD_159___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__XLNA_GAIN_EVEN_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__LNA_GAIN_EVEN_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__GM_GAIN_EVEN_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__TIA_GAIN_EVEN_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__SLM_XLNA_EVEN_159___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__BQ_GAIN_EVEN_159___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__XLNA_GAIN_ODD_159___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__XLNA_GAIN_ODD_159___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__LNA_GAIN_ODD_159___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__LNA_GAIN_ODD_159___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__GM_GAIN_ODD_159___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__GM_GAIN_ODD_159___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__TIA_GAIN_ODD_159___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__TIA_GAIN_ODD_159___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__SLM_XLNA_ODD_159___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__SLM_XLNA_ODD_159___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__BQ_GAIN_ODD_159___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__BQ_GAIN_ODD_159___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__XLNA_GAIN_EVEN_159___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__XLNA_GAIN_EVEN_159___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__LNA_GAIN_EVEN_159___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__LNA_GAIN_EVEN_159___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__GM_GAIN_EVEN_159___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__GM_GAIN_EVEN_159___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__TIA_GAIN_EVEN_159___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__TIA_GAIN_EVEN_159___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__SLM_XLNA_EVEN_159___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__SLM_XLNA_EVEN_159___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__BQ_GAIN_EVEN_159___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159__BQ_GAIN_EVEN_159___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_159___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160 (0x005FD280) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__XLNA_GAIN_ODD_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__LNA_GAIN_ODD_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__GM_GAIN_ODD_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__TIA_GAIN_ODD_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__SLM_XLNA_ODD_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__BQ_GAIN_ODD_160___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__XLNA_GAIN_EVEN_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__LNA_GAIN_EVEN_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__GM_GAIN_EVEN_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__TIA_GAIN_EVEN_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__SLM_XLNA_EVEN_160___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__BQ_GAIN_EVEN_160___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__XLNA_GAIN_ODD_160___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__XLNA_GAIN_ODD_160___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__LNA_GAIN_ODD_160___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__LNA_GAIN_ODD_160___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__GM_GAIN_ODD_160___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__GM_GAIN_ODD_160___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__TIA_GAIN_ODD_160___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__TIA_GAIN_ODD_160___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__SLM_XLNA_ODD_160___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__SLM_XLNA_ODD_160___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__BQ_GAIN_ODD_160___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__BQ_GAIN_ODD_160___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__XLNA_GAIN_EVEN_160___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__XLNA_GAIN_EVEN_160___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__LNA_GAIN_EVEN_160___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__LNA_GAIN_EVEN_160___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__GM_GAIN_EVEN_160___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__GM_GAIN_EVEN_160___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__TIA_GAIN_EVEN_160___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__TIA_GAIN_EVEN_160___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__SLM_XLNA_EVEN_160___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__SLM_XLNA_EVEN_160___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__BQ_GAIN_EVEN_160___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160__BQ_GAIN_EVEN_160___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_160___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161 (0x005FD284) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__XLNA_GAIN_ODD_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__LNA_GAIN_ODD_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__GM_GAIN_ODD_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__TIA_GAIN_ODD_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__SLM_XLNA_ODD_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__BQ_GAIN_ODD_161___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__XLNA_GAIN_EVEN_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__LNA_GAIN_EVEN_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__GM_GAIN_EVEN_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__TIA_GAIN_EVEN_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__SLM_XLNA_EVEN_161___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__BQ_GAIN_EVEN_161___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__XLNA_GAIN_ODD_161___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__XLNA_GAIN_ODD_161___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__LNA_GAIN_ODD_161___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__LNA_GAIN_ODD_161___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__GM_GAIN_ODD_161___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__GM_GAIN_ODD_161___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__TIA_GAIN_ODD_161___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__TIA_GAIN_ODD_161___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__SLM_XLNA_ODD_161___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__SLM_XLNA_ODD_161___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__BQ_GAIN_ODD_161___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__BQ_GAIN_ODD_161___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__XLNA_GAIN_EVEN_161___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__XLNA_GAIN_EVEN_161___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__LNA_GAIN_EVEN_161___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__LNA_GAIN_EVEN_161___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__GM_GAIN_EVEN_161___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__GM_GAIN_EVEN_161___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__TIA_GAIN_EVEN_161___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__TIA_GAIN_EVEN_161___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__SLM_XLNA_EVEN_161___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__SLM_XLNA_EVEN_161___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__BQ_GAIN_EVEN_161___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161__BQ_GAIN_EVEN_161___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_161___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162 (0x005FD288) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__XLNA_GAIN_ODD_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__LNA_GAIN_ODD_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__GM_GAIN_ODD_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__TIA_GAIN_ODD_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__SLM_XLNA_ODD_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__BQ_GAIN_ODD_162___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__XLNA_GAIN_EVEN_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__LNA_GAIN_EVEN_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__GM_GAIN_EVEN_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__TIA_GAIN_EVEN_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__SLM_XLNA_EVEN_162___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__BQ_GAIN_EVEN_162___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__XLNA_GAIN_ODD_162___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__XLNA_GAIN_ODD_162___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__LNA_GAIN_ODD_162___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__LNA_GAIN_ODD_162___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__GM_GAIN_ODD_162___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__GM_GAIN_ODD_162___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__TIA_GAIN_ODD_162___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__TIA_GAIN_ODD_162___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__SLM_XLNA_ODD_162___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__SLM_XLNA_ODD_162___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__BQ_GAIN_ODD_162___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__BQ_GAIN_ODD_162___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__XLNA_GAIN_EVEN_162___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__XLNA_GAIN_EVEN_162___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__LNA_GAIN_EVEN_162___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__LNA_GAIN_EVEN_162___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__GM_GAIN_EVEN_162___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__GM_GAIN_EVEN_162___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__TIA_GAIN_EVEN_162___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__TIA_GAIN_EVEN_162___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__SLM_XLNA_EVEN_162___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__SLM_XLNA_EVEN_162___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__BQ_GAIN_EVEN_162___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162__BQ_GAIN_EVEN_162___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_162___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163 (0x005FD28C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__XLNA_GAIN_ODD_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__LNA_GAIN_ODD_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__GM_GAIN_ODD_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__TIA_GAIN_ODD_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__SLM_XLNA_ODD_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__BQ_GAIN_ODD_163___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__XLNA_GAIN_EVEN_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__LNA_GAIN_EVEN_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__GM_GAIN_EVEN_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__TIA_GAIN_EVEN_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__SLM_XLNA_EVEN_163___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__BQ_GAIN_EVEN_163___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__XLNA_GAIN_ODD_163___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__XLNA_GAIN_ODD_163___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__LNA_GAIN_ODD_163___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__LNA_GAIN_ODD_163___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__GM_GAIN_ODD_163___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__GM_GAIN_ODD_163___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__TIA_GAIN_ODD_163___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__TIA_GAIN_ODD_163___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__SLM_XLNA_ODD_163___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__SLM_XLNA_ODD_163___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__BQ_GAIN_ODD_163___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__BQ_GAIN_ODD_163___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__XLNA_GAIN_EVEN_163___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__XLNA_GAIN_EVEN_163___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__LNA_GAIN_EVEN_163___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__LNA_GAIN_EVEN_163___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__GM_GAIN_EVEN_163___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__GM_GAIN_EVEN_163___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__TIA_GAIN_EVEN_163___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__TIA_GAIN_EVEN_163___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__SLM_XLNA_EVEN_163___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__SLM_XLNA_EVEN_163___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__BQ_GAIN_EVEN_163___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163__BQ_GAIN_EVEN_163___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_163___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164 (0x005FD290) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__XLNA_GAIN_ODD_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__LNA_GAIN_ODD_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__GM_GAIN_ODD_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__TIA_GAIN_ODD_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__SLM_XLNA_ODD_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__BQ_GAIN_ODD_164___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__XLNA_GAIN_EVEN_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__LNA_GAIN_EVEN_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__GM_GAIN_EVEN_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__TIA_GAIN_EVEN_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__SLM_XLNA_EVEN_164___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__BQ_GAIN_EVEN_164___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__XLNA_GAIN_ODD_164___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__XLNA_GAIN_ODD_164___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__LNA_GAIN_ODD_164___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__LNA_GAIN_ODD_164___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__GM_GAIN_ODD_164___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__GM_GAIN_ODD_164___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__TIA_GAIN_ODD_164___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__TIA_GAIN_ODD_164___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__SLM_XLNA_ODD_164___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__SLM_XLNA_ODD_164___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__BQ_GAIN_ODD_164___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__BQ_GAIN_ODD_164___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__XLNA_GAIN_EVEN_164___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__XLNA_GAIN_EVEN_164___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__LNA_GAIN_EVEN_164___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__LNA_GAIN_EVEN_164___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__GM_GAIN_EVEN_164___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__GM_GAIN_EVEN_164___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__TIA_GAIN_EVEN_164___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__TIA_GAIN_EVEN_164___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__SLM_XLNA_EVEN_164___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__SLM_XLNA_EVEN_164___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__BQ_GAIN_EVEN_164___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164__BQ_GAIN_EVEN_164___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_164___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165 (0x005FD294) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__XLNA_GAIN_ODD_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__LNA_GAIN_ODD_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__GM_GAIN_ODD_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__TIA_GAIN_ODD_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__SLM_XLNA_ODD_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__BQ_GAIN_ODD_165___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__XLNA_GAIN_EVEN_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__LNA_GAIN_EVEN_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__GM_GAIN_EVEN_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__TIA_GAIN_EVEN_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__SLM_XLNA_EVEN_165___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__BQ_GAIN_EVEN_165___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__XLNA_GAIN_ODD_165___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__XLNA_GAIN_ODD_165___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__LNA_GAIN_ODD_165___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__LNA_GAIN_ODD_165___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__GM_GAIN_ODD_165___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__GM_GAIN_ODD_165___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__TIA_GAIN_ODD_165___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__TIA_GAIN_ODD_165___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__SLM_XLNA_ODD_165___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__SLM_XLNA_ODD_165___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__BQ_GAIN_ODD_165___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__BQ_GAIN_ODD_165___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__XLNA_GAIN_EVEN_165___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__XLNA_GAIN_EVEN_165___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__LNA_GAIN_EVEN_165___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__LNA_GAIN_EVEN_165___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__GM_GAIN_EVEN_165___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__GM_GAIN_EVEN_165___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__TIA_GAIN_EVEN_165___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__TIA_GAIN_EVEN_165___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__SLM_XLNA_EVEN_165___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__SLM_XLNA_EVEN_165___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__BQ_GAIN_EVEN_165___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165__BQ_GAIN_EVEN_165___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_165___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166 (0x005FD298) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__XLNA_GAIN_ODD_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__LNA_GAIN_ODD_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__GM_GAIN_ODD_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__TIA_GAIN_ODD_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__SLM_XLNA_ODD_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__BQ_GAIN_ODD_166___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__XLNA_GAIN_EVEN_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__LNA_GAIN_EVEN_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__GM_GAIN_EVEN_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__TIA_GAIN_EVEN_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__SLM_XLNA_EVEN_166___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__BQ_GAIN_EVEN_166___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__XLNA_GAIN_ODD_166___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__XLNA_GAIN_ODD_166___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__LNA_GAIN_ODD_166___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__LNA_GAIN_ODD_166___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__GM_GAIN_ODD_166___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__GM_GAIN_ODD_166___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__TIA_GAIN_ODD_166___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__TIA_GAIN_ODD_166___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__SLM_XLNA_ODD_166___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__SLM_XLNA_ODD_166___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__BQ_GAIN_ODD_166___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__BQ_GAIN_ODD_166___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__XLNA_GAIN_EVEN_166___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__XLNA_GAIN_EVEN_166___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__LNA_GAIN_EVEN_166___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__LNA_GAIN_EVEN_166___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__GM_GAIN_EVEN_166___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__GM_GAIN_EVEN_166___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__TIA_GAIN_EVEN_166___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__TIA_GAIN_EVEN_166___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__SLM_XLNA_EVEN_166___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__SLM_XLNA_EVEN_166___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__BQ_GAIN_EVEN_166___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166__BQ_GAIN_EVEN_166___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_166___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167 (0x005FD29C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__XLNA_GAIN_ODD_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__LNA_GAIN_ODD_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__GM_GAIN_ODD_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__TIA_GAIN_ODD_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__SLM_XLNA_ODD_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__BQ_GAIN_ODD_167___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__XLNA_GAIN_EVEN_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__LNA_GAIN_EVEN_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__GM_GAIN_EVEN_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__TIA_GAIN_EVEN_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__SLM_XLNA_EVEN_167___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__BQ_GAIN_EVEN_167___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__XLNA_GAIN_ODD_167___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__XLNA_GAIN_ODD_167___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__LNA_GAIN_ODD_167___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__LNA_GAIN_ODD_167___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__GM_GAIN_ODD_167___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__GM_GAIN_ODD_167___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__TIA_GAIN_ODD_167___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__TIA_GAIN_ODD_167___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__SLM_XLNA_ODD_167___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__SLM_XLNA_ODD_167___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__BQ_GAIN_ODD_167___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__BQ_GAIN_ODD_167___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__XLNA_GAIN_EVEN_167___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__XLNA_GAIN_EVEN_167___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__LNA_GAIN_EVEN_167___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__LNA_GAIN_EVEN_167___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__GM_GAIN_EVEN_167___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__GM_GAIN_EVEN_167___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__TIA_GAIN_EVEN_167___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__TIA_GAIN_EVEN_167___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__SLM_XLNA_EVEN_167___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__SLM_XLNA_EVEN_167___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__BQ_GAIN_EVEN_167___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167__BQ_GAIN_EVEN_167___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_167___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168 (0x005FD2A0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__XLNA_GAIN_ODD_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__LNA_GAIN_ODD_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__GM_GAIN_ODD_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__TIA_GAIN_ODD_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__SLM_XLNA_ODD_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__BQ_GAIN_ODD_168___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__XLNA_GAIN_EVEN_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__LNA_GAIN_EVEN_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__GM_GAIN_EVEN_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__TIA_GAIN_EVEN_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__SLM_XLNA_EVEN_168___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__BQ_GAIN_EVEN_168___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__XLNA_GAIN_ODD_168___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__XLNA_GAIN_ODD_168___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__LNA_GAIN_ODD_168___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__LNA_GAIN_ODD_168___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__GM_GAIN_ODD_168___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__GM_GAIN_ODD_168___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__TIA_GAIN_ODD_168___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__TIA_GAIN_ODD_168___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__SLM_XLNA_ODD_168___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__SLM_XLNA_ODD_168___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__BQ_GAIN_ODD_168___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__BQ_GAIN_ODD_168___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__XLNA_GAIN_EVEN_168___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__XLNA_GAIN_EVEN_168___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__LNA_GAIN_EVEN_168___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__LNA_GAIN_EVEN_168___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__GM_GAIN_EVEN_168___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__GM_GAIN_EVEN_168___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__TIA_GAIN_EVEN_168___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__TIA_GAIN_EVEN_168___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__SLM_XLNA_EVEN_168___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__SLM_XLNA_EVEN_168___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__BQ_GAIN_EVEN_168___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168__BQ_GAIN_EVEN_168___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_168___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169 (0x005FD2A4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__XLNA_GAIN_ODD_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__LNA_GAIN_ODD_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__GM_GAIN_ODD_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__TIA_GAIN_ODD_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__SLM_XLNA_ODD_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__BQ_GAIN_ODD_169___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__XLNA_GAIN_EVEN_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__LNA_GAIN_EVEN_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__GM_GAIN_EVEN_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__TIA_GAIN_EVEN_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__SLM_XLNA_EVEN_169___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__BQ_GAIN_EVEN_169___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__XLNA_GAIN_ODD_169___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__XLNA_GAIN_ODD_169___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__LNA_GAIN_ODD_169___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__LNA_GAIN_ODD_169___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__GM_GAIN_ODD_169___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__GM_GAIN_ODD_169___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__TIA_GAIN_ODD_169___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__TIA_GAIN_ODD_169___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__SLM_XLNA_ODD_169___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__SLM_XLNA_ODD_169___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__BQ_GAIN_ODD_169___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__BQ_GAIN_ODD_169___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__XLNA_GAIN_EVEN_169___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__XLNA_GAIN_EVEN_169___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__LNA_GAIN_EVEN_169___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__LNA_GAIN_EVEN_169___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__GM_GAIN_EVEN_169___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__GM_GAIN_EVEN_169___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__TIA_GAIN_EVEN_169___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__TIA_GAIN_EVEN_169___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__SLM_XLNA_EVEN_169___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__SLM_XLNA_EVEN_169___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__BQ_GAIN_EVEN_169___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169__BQ_GAIN_EVEN_169___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_169___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170 (0x005FD2A8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__XLNA_GAIN_ODD_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__LNA_GAIN_ODD_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__GM_GAIN_ODD_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__TIA_GAIN_ODD_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__SLM_XLNA_ODD_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__BQ_GAIN_ODD_170___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__XLNA_GAIN_EVEN_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__LNA_GAIN_EVEN_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__GM_GAIN_EVEN_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__TIA_GAIN_EVEN_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__SLM_XLNA_EVEN_170___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__BQ_GAIN_EVEN_170___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__XLNA_GAIN_ODD_170___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__XLNA_GAIN_ODD_170___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__LNA_GAIN_ODD_170___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__LNA_GAIN_ODD_170___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__GM_GAIN_ODD_170___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__GM_GAIN_ODD_170___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__TIA_GAIN_ODD_170___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__TIA_GAIN_ODD_170___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__SLM_XLNA_ODD_170___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__SLM_XLNA_ODD_170___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__BQ_GAIN_ODD_170___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__BQ_GAIN_ODD_170___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__XLNA_GAIN_EVEN_170___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__XLNA_GAIN_EVEN_170___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__LNA_GAIN_EVEN_170___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__LNA_GAIN_EVEN_170___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__GM_GAIN_EVEN_170___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__GM_GAIN_EVEN_170___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__TIA_GAIN_EVEN_170___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__TIA_GAIN_EVEN_170___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__SLM_XLNA_EVEN_170___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__SLM_XLNA_EVEN_170___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__BQ_GAIN_EVEN_170___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170__BQ_GAIN_EVEN_170___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_170___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171 (0x005FD2AC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__XLNA_GAIN_ODD_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__LNA_GAIN_ODD_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__GM_GAIN_ODD_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__TIA_GAIN_ODD_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__SLM_XLNA_ODD_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__BQ_GAIN_ODD_171___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__XLNA_GAIN_EVEN_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__LNA_GAIN_EVEN_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__GM_GAIN_EVEN_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__TIA_GAIN_EVEN_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__SLM_XLNA_EVEN_171___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__BQ_GAIN_EVEN_171___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__XLNA_GAIN_ODD_171___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__XLNA_GAIN_ODD_171___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__LNA_GAIN_ODD_171___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__LNA_GAIN_ODD_171___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__GM_GAIN_ODD_171___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__GM_GAIN_ODD_171___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__TIA_GAIN_ODD_171___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__TIA_GAIN_ODD_171___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__SLM_XLNA_ODD_171___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__SLM_XLNA_ODD_171___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__BQ_GAIN_ODD_171___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__BQ_GAIN_ODD_171___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__XLNA_GAIN_EVEN_171___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__XLNA_GAIN_EVEN_171___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__LNA_GAIN_EVEN_171___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__LNA_GAIN_EVEN_171___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__GM_GAIN_EVEN_171___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__GM_GAIN_EVEN_171___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__TIA_GAIN_EVEN_171___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__TIA_GAIN_EVEN_171___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__SLM_XLNA_EVEN_171___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__SLM_XLNA_EVEN_171___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__BQ_GAIN_EVEN_171___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171__BQ_GAIN_EVEN_171___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_171___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172 (0x005FD2B0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__XLNA_GAIN_ODD_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__LNA_GAIN_ODD_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__GM_GAIN_ODD_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__TIA_GAIN_ODD_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__SLM_XLNA_ODD_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__BQ_GAIN_ODD_172___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__XLNA_GAIN_EVEN_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__LNA_GAIN_EVEN_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__GM_GAIN_EVEN_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__TIA_GAIN_EVEN_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__SLM_XLNA_EVEN_172___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__BQ_GAIN_EVEN_172___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__XLNA_GAIN_ODD_172___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__XLNA_GAIN_ODD_172___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__LNA_GAIN_ODD_172___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__LNA_GAIN_ODD_172___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__GM_GAIN_ODD_172___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__GM_GAIN_ODD_172___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__TIA_GAIN_ODD_172___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__TIA_GAIN_ODD_172___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__SLM_XLNA_ODD_172___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__SLM_XLNA_ODD_172___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__BQ_GAIN_ODD_172___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__BQ_GAIN_ODD_172___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__XLNA_GAIN_EVEN_172___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__XLNA_GAIN_EVEN_172___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__LNA_GAIN_EVEN_172___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__LNA_GAIN_EVEN_172___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__GM_GAIN_EVEN_172___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__GM_GAIN_EVEN_172___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__TIA_GAIN_EVEN_172___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__TIA_GAIN_EVEN_172___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__SLM_XLNA_EVEN_172___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__SLM_XLNA_EVEN_172___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__BQ_GAIN_EVEN_172___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172__BQ_GAIN_EVEN_172___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_172___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173 (0x005FD2B4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__XLNA_GAIN_ODD_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__LNA_GAIN_ODD_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__GM_GAIN_ODD_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__TIA_GAIN_ODD_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__SLM_XLNA_ODD_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__BQ_GAIN_ODD_173___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__XLNA_GAIN_EVEN_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__LNA_GAIN_EVEN_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__GM_GAIN_EVEN_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__TIA_GAIN_EVEN_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__SLM_XLNA_EVEN_173___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__BQ_GAIN_EVEN_173___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__XLNA_GAIN_ODD_173___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__XLNA_GAIN_ODD_173___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__LNA_GAIN_ODD_173___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__LNA_GAIN_ODD_173___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__GM_GAIN_ODD_173___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__GM_GAIN_ODD_173___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__TIA_GAIN_ODD_173___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__TIA_GAIN_ODD_173___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__SLM_XLNA_ODD_173___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__SLM_XLNA_ODD_173___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__BQ_GAIN_ODD_173___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__BQ_GAIN_ODD_173___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__XLNA_GAIN_EVEN_173___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__XLNA_GAIN_EVEN_173___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__LNA_GAIN_EVEN_173___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__LNA_GAIN_EVEN_173___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__GM_GAIN_EVEN_173___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__GM_GAIN_EVEN_173___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__TIA_GAIN_EVEN_173___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__TIA_GAIN_EVEN_173___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__SLM_XLNA_EVEN_173___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__SLM_XLNA_EVEN_173___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__BQ_GAIN_EVEN_173___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173__BQ_GAIN_EVEN_173___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_173___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174 (0x005FD2B8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__XLNA_GAIN_ODD_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__LNA_GAIN_ODD_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__GM_GAIN_ODD_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__TIA_GAIN_ODD_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__SLM_XLNA_ODD_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__BQ_GAIN_ODD_174___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__XLNA_GAIN_EVEN_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__LNA_GAIN_EVEN_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__GM_GAIN_EVEN_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__TIA_GAIN_EVEN_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__SLM_XLNA_EVEN_174___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__BQ_GAIN_EVEN_174___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__XLNA_GAIN_ODD_174___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__XLNA_GAIN_ODD_174___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__LNA_GAIN_ODD_174___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__LNA_GAIN_ODD_174___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__GM_GAIN_ODD_174___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__GM_GAIN_ODD_174___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__TIA_GAIN_ODD_174___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__TIA_GAIN_ODD_174___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__SLM_XLNA_ODD_174___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__SLM_XLNA_ODD_174___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__BQ_GAIN_ODD_174___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__BQ_GAIN_ODD_174___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__XLNA_GAIN_EVEN_174___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__XLNA_GAIN_EVEN_174___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__LNA_GAIN_EVEN_174___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__LNA_GAIN_EVEN_174___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__GM_GAIN_EVEN_174___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__GM_GAIN_EVEN_174___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__TIA_GAIN_EVEN_174___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__TIA_GAIN_EVEN_174___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__SLM_XLNA_EVEN_174___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__SLM_XLNA_EVEN_174___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__BQ_GAIN_EVEN_174___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174__BQ_GAIN_EVEN_174___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_174___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175 (0x005FD2BC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__XLNA_GAIN_ODD_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__LNA_GAIN_ODD_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__GM_GAIN_ODD_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__TIA_GAIN_ODD_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__SLM_XLNA_ODD_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__BQ_GAIN_ODD_175___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__XLNA_GAIN_EVEN_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__LNA_GAIN_EVEN_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__GM_GAIN_EVEN_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__TIA_GAIN_EVEN_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__SLM_XLNA_EVEN_175___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__BQ_GAIN_EVEN_175___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__XLNA_GAIN_ODD_175___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__XLNA_GAIN_ODD_175___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__LNA_GAIN_ODD_175___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__LNA_GAIN_ODD_175___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__GM_GAIN_ODD_175___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__GM_GAIN_ODD_175___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__TIA_GAIN_ODD_175___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__TIA_GAIN_ODD_175___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__SLM_XLNA_ODD_175___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__SLM_XLNA_ODD_175___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__BQ_GAIN_ODD_175___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__BQ_GAIN_ODD_175___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__XLNA_GAIN_EVEN_175___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__XLNA_GAIN_EVEN_175___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__LNA_GAIN_EVEN_175___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__LNA_GAIN_EVEN_175___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__GM_GAIN_EVEN_175___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__GM_GAIN_EVEN_175___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__TIA_GAIN_EVEN_175___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__TIA_GAIN_EVEN_175___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__SLM_XLNA_EVEN_175___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__SLM_XLNA_EVEN_175___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__BQ_GAIN_EVEN_175___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175__BQ_GAIN_EVEN_175___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_175___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176 (0x005FD2C0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__XLNA_GAIN_ODD_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__LNA_GAIN_ODD_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__GM_GAIN_ODD_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__TIA_GAIN_ODD_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__SLM_XLNA_ODD_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__BQ_GAIN_ODD_176___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__XLNA_GAIN_EVEN_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__LNA_GAIN_EVEN_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__GM_GAIN_EVEN_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__TIA_GAIN_EVEN_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__SLM_XLNA_EVEN_176___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__BQ_GAIN_EVEN_176___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__XLNA_GAIN_ODD_176___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__XLNA_GAIN_ODD_176___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__LNA_GAIN_ODD_176___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__LNA_GAIN_ODD_176___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__GM_GAIN_ODD_176___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__GM_GAIN_ODD_176___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__TIA_GAIN_ODD_176___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__TIA_GAIN_ODD_176___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__SLM_XLNA_ODD_176___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__SLM_XLNA_ODD_176___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__BQ_GAIN_ODD_176___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__BQ_GAIN_ODD_176___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__XLNA_GAIN_EVEN_176___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__XLNA_GAIN_EVEN_176___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__LNA_GAIN_EVEN_176___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__LNA_GAIN_EVEN_176___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__GM_GAIN_EVEN_176___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__GM_GAIN_EVEN_176___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__TIA_GAIN_EVEN_176___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__TIA_GAIN_EVEN_176___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__SLM_XLNA_EVEN_176___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__SLM_XLNA_EVEN_176___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__BQ_GAIN_EVEN_176___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176__BQ_GAIN_EVEN_176___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_176___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177 (0x005FD2C4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__XLNA_GAIN_ODD_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__LNA_GAIN_ODD_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__GM_GAIN_ODD_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__TIA_GAIN_ODD_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__SLM_XLNA_ODD_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__BQ_GAIN_ODD_177___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__XLNA_GAIN_EVEN_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__LNA_GAIN_EVEN_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__GM_GAIN_EVEN_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__TIA_GAIN_EVEN_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__SLM_XLNA_EVEN_177___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__BQ_GAIN_EVEN_177___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__XLNA_GAIN_ODD_177___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__XLNA_GAIN_ODD_177___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__LNA_GAIN_ODD_177___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__LNA_GAIN_ODD_177___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__GM_GAIN_ODD_177___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__GM_GAIN_ODD_177___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__TIA_GAIN_ODD_177___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__TIA_GAIN_ODD_177___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__SLM_XLNA_ODD_177___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__SLM_XLNA_ODD_177___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__BQ_GAIN_ODD_177___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__BQ_GAIN_ODD_177___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__XLNA_GAIN_EVEN_177___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__XLNA_GAIN_EVEN_177___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__LNA_GAIN_EVEN_177___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__LNA_GAIN_EVEN_177___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__GM_GAIN_EVEN_177___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__GM_GAIN_EVEN_177___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__TIA_GAIN_EVEN_177___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__TIA_GAIN_EVEN_177___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__SLM_XLNA_EVEN_177___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__SLM_XLNA_EVEN_177___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__BQ_GAIN_EVEN_177___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177__BQ_GAIN_EVEN_177___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_177___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178 (0x005FD2C8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__XLNA_GAIN_ODD_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__LNA_GAIN_ODD_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__GM_GAIN_ODD_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__TIA_GAIN_ODD_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__SLM_XLNA_ODD_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__BQ_GAIN_ODD_178___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__XLNA_GAIN_EVEN_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__LNA_GAIN_EVEN_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__GM_GAIN_EVEN_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__TIA_GAIN_EVEN_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__SLM_XLNA_EVEN_178___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__BQ_GAIN_EVEN_178___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__XLNA_GAIN_ODD_178___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__XLNA_GAIN_ODD_178___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__LNA_GAIN_ODD_178___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__LNA_GAIN_ODD_178___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__GM_GAIN_ODD_178___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__GM_GAIN_ODD_178___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__TIA_GAIN_ODD_178___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__TIA_GAIN_ODD_178___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__SLM_XLNA_ODD_178___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__SLM_XLNA_ODD_178___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__BQ_GAIN_ODD_178___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__BQ_GAIN_ODD_178___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__XLNA_GAIN_EVEN_178___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__XLNA_GAIN_EVEN_178___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__LNA_GAIN_EVEN_178___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__LNA_GAIN_EVEN_178___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__GM_GAIN_EVEN_178___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__GM_GAIN_EVEN_178___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__TIA_GAIN_EVEN_178___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__TIA_GAIN_EVEN_178___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__SLM_XLNA_EVEN_178___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__SLM_XLNA_EVEN_178___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__BQ_GAIN_EVEN_178___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178__BQ_GAIN_EVEN_178___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_178___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179 (0x005FD2CC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__XLNA_GAIN_ODD_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__LNA_GAIN_ODD_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__GM_GAIN_ODD_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__TIA_GAIN_ODD_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__SLM_XLNA_ODD_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__BQ_GAIN_ODD_179___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__XLNA_GAIN_EVEN_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__LNA_GAIN_EVEN_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__GM_GAIN_EVEN_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__TIA_GAIN_EVEN_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__SLM_XLNA_EVEN_179___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__BQ_GAIN_EVEN_179___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__XLNA_GAIN_ODD_179___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__XLNA_GAIN_ODD_179___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__LNA_GAIN_ODD_179___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__LNA_GAIN_ODD_179___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__GM_GAIN_ODD_179___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__GM_GAIN_ODD_179___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__TIA_GAIN_ODD_179___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__TIA_GAIN_ODD_179___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__SLM_XLNA_ODD_179___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__SLM_XLNA_ODD_179___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__BQ_GAIN_ODD_179___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__BQ_GAIN_ODD_179___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__XLNA_GAIN_EVEN_179___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__XLNA_GAIN_EVEN_179___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__LNA_GAIN_EVEN_179___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__LNA_GAIN_EVEN_179___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__GM_GAIN_EVEN_179___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__GM_GAIN_EVEN_179___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__TIA_GAIN_EVEN_179___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__TIA_GAIN_EVEN_179___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__SLM_XLNA_EVEN_179___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__SLM_XLNA_EVEN_179___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__BQ_GAIN_EVEN_179___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179__BQ_GAIN_EVEN_179___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_179___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180 (0x005FD2D0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__XLNA_GAIN_ODD_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__LNA_GAIN_ODD_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__GM_GAIN_ODD_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__TIA_GAIN_ODD_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__SLM_XLNA_ODD_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__BQ_GAIN_ODD_180___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__XLNA_GAIN_EVEN_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__LNA_GAIN_EVEN_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__GM_GAIN_EVEN_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__TIA_GAIN_EVEN_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__SLM_XLNA_EVEN_180___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__BQ_GAIN_EVEN_180___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__XLNA_GAIN_ODD_180___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__XLNA_GAIN_ODD_180___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__LNA_GAIN_ODD_180___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__LNA_GAIN_ODD_180___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__GM_GAIN_ODD_180___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__GM_GAIN_ODD_180___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__TIA_GAIN_ODD_180___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__TIA_GAIN_ODD_180___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__SLM_XLNA_ODD_180___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__SLM_XLNA_ODD_180___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__BQ_GAIN_ODD_180___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__BQ_GAIN_ODD_180___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__XLNA_GAIN_EVEN_180___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__XLNA_GAIN_EVEN_180___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__LNA_GAIN_EVEN_180___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__LNA_GAIN_EVEN_180___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__GM_GAIN_EVEN_180___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__GM_GAIN_EVEN_180___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__TIA_GAIN_EVEN_180___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__TIA_GAIN_EVEN_180___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__SLM_XLNA_EVEN_180___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__SLM_XLNA_EVEN_180___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__BQ_GAIN_EVEN_180___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180__BQ_GAIN_EVEN_180___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_180___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181 (0x005FD2D4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__XLNA_GAIN_ODD_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__LNA_GAIN_ODD_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__GM_GAIN_ODD_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__TIA_GAIN_ODD_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__SLM_XLNA_ODD_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__BQ_GAIN_ODD_181___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__XLNA_GAIN_EVEN_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__LNA_GAIN_EVEN_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__GM_GAIN_EVEN_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__TIA_GAIN_EVEN_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__SLM_XLNA_EVEN_181___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__BQ_GAIN_EVEN_181___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__XLNA_GAIN_ODD_181___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__XLNA_GAIN_ODD_181___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__LNA_GAIN_ODD_181___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__LNA_GAIN_ODD_181___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__GM_GAIN_ODD_181___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__GM_GAIN_ODD_181___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__TIA_GAIN_ODD_181___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__TIA_GAIN_ODD_181___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__SLM_XLNA_ODD_181___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__SLM_XLNA_ODD_181___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__BQ_GAIN_ODD_181___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__BQ_GAIN_ODD_181___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__XLNA_GAIN_EVEN_181___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__XLNA_GAIN_EVEN_181___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__LNA_GAIN_EVEN_181___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__LNA_GAIN_EVEN_181___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__GM_GAIN_EVEN_181___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__GM_GAIN_EVEN_181___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__TIA_GAIN_EVEN_181___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__TIA_GAIN_EVEN_181___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__SLM_XLNA_EVEN_181___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__SLM_XLNA_EVEN_181___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__BQ_GAIN_EVEN_181___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181__BQ_GAIN_EVEN_181___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_181___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182 (0x005FD2D8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__XLNA_GAIN_ODD_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__LNA_GAIN_ODD_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__GM_GAIN_ODD_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__TIA_GAIN_ODD_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__SLM_XLNA_ODD_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__BQ_GAIN_ODD_182___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__XLNA_GAIN_EVEN_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__LNA_GAIN_EVEN_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__GM_GAIN_EVEN_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__TIA_GAIN_EVEN_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__SLM_XLNA_EVEN_182___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__BQ_GAIN_EVEN_182___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__XLNA_GAIN_ODD_182___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__XLNA_GAIN_ODD_182___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__LNA_GAIN_ODD_182___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__LNA_GAIN_ODD_182___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__GM_GAIN_ODD_182___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__GM_GAIN_ODD_182___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__TIA_GAIN_ODD_182___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__TIA_GAIN_ODD_182___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__SLM_XLNA_ODD_182___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__SLM_XLNA_ODD_182___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__BQ_GAIN_ODD_182___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__BQ_GAIN_ODD_182___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__XLNA_GAIN_EVEN_182___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__XLNA_GAIN_EVEN_182___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__LNA_GAIN_EVEN_182___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__LNA_GAIN_EVEN_182___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__GM_GAIN_EVEN_182___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__GM_GAIN_EVEN_182___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__TIA_GAIN_EVEN_182___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__TIA_GAIN_EVEN_182___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__SLM_XLNA_EVEN_182___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__SLM_XLNA_EVEN_182___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__BQ_GAIN_EVEN_182___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182__BQ_GAIN_EVEN_182___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_182___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183 (0x005FD2DC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__XLNA_GAIN_ODD_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__LNA_GAIN_ODD_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__GM_GAIN_ODD_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__TIA_GAIN_ODD_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__SLM_XLNA_ODD_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__BQ_GAIN_ODD_183___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__XLNA_GAIN_EVEN_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__LNA_GAIN_EVEN_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__GM_GAIN_EVEN_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__TIA_GAIN_EVEN_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__SLM_XLNA_EVEN_183___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__BQ_GAIN_EVEN_183___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__XLNA_GAIN_ODD_183___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__XLNA_GAIN_ODD_183___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__LNA_GAIN_ODD_183___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__LNA_GAIN_ODD_183___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__GM_GAIN_ODD_183___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__GM_GAIN_ODD_183___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__TIA_GAIN_ODD_183___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__TIA_GAIN_ODD_183___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__SLM_XLNA_ODD_183___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__SLM_XLNA_ODD_183___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__BQ_GAIN_ODD_183___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__BQ_GAIN_ODD_183___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__XLNA_GAIN_EVEN_183___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__XLNA_GAIN_EVEN_183___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__LNA_GAIN_EVEN_183___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__LNA_GAIN_EVEN_183___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__GM_GAIN_EVEN_183___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__GM_GAIN_EVEN_183___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__TIA_GAIN_EVEN_183___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__TIA_GAIN_EVEN_183___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__SLM_XLNA_EVEN_183___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__SLM_XLNA_EVEN_183___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__BQ_GAIN_EVEN_183___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183__BQ_GAIN_EVEN_183___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_183___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184 (0x005FD2E0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__XLNA_GAIN_ODD_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__LNA_GAIN_ODD_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__GM_GAIN_ODD_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__TIA_GAIN_ODD_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__SLM_XLNA_ODD_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__BQ_GAIN_ODD_184___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__XLNA_GAIN_EVEN_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__LNA_GAIN_EVEN_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__GM_GAIN_EVEN_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__TIA_GAIN_EVEN_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__SLM_XLNA_EVEN_184___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__BQ_GAIN_EVEN_184___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__XLNA_GAIN_ODD_184___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__XLNA_GAIN_ODD_184___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__LNA_GAIN_ODD_184___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__LNA_GAIN_ODD_184___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__GM_GAIN_ODD_184___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__GM_GAIN_ODD_184___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__TIA_GAIN_ODD_184___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__TIA_GAIN_ODD_184___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__SLM_XLNA_ODD_184___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__SLM_XLNA_ODD_184___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__BQ_GAIN_ODD_184___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__BQ_GAIN_ODD_184___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__XLNA_GAIN_EVEN_184___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__XLNA_GAIN_EVEN_184___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__LNA_GAIN_EVEN_184___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__LNA_GAIN_EVEN_184___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__GM_GAIN_EVEN_184___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__GM_GAIN_EVEN_184___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__TIA_GAIN_EVEN_184___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__TIA_GAIN_EVEN_184___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__SLM_XLNA_EVEN_184___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__SLM_XLNA_EVEN_184___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__BQ_GAIN_EVEN_184___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184__BQ_GAIN_EVEN_184___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_184___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185 (0x005FD2E4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__XLNA_GAIN_ODD_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__LNA_GAIN_ODD_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__GM_GAIN_ODD_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__TIA_GAIN_ODD_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__SLM_XLNA_ODD_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__BQ_GAIN_ODD_185___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__XLNA_GAIN_EVEN_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__LNA_GAIN_EVEN_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__GM_GAIN_EVEN_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__TIA_GAIN_EVEN_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__SLM_XLNA_EVEN_185___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__BQ_GAIN_EVEN_185___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__XLNA_GAIN_ODD_185___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__XLNA_GAIN_ODD_185___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__LNA_GAIN_ODD_185___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__LNA_GAIN_ODD_185___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__GM_GAIN_ODD_185___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__GM_GAIN_ODD_185___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__TIA_GAIN_ODD_185___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__TIA_GAIN_ODD_185___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__SLM_XLNA_ODD_185___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__SLM_XLNA_ODD_185___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__BQ_GAIN_ODD_185___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__BQ_GAIN_ODD_185___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__XLNA_GAIN_EVEN_185___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__XLNA_GAIN_EVEN_185___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__LNA_GAIN_EVEN_185___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__LNA_GAIN_EVEN_185___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__GM_GAIN_EVEN_185___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__GM_GAIN_EVEN_185___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__TIA_GAIN_EVEN_185___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__TIA_GAIN_EVEN_185___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__SLM_XLNA_EVEN_185___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__SLM_XLNA_EVEN_185___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__BQ_GAIN_EVEN_185___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185__BQ_GAIN_EVEN_185___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_185___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186 (0x005FD2E8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__XLNA_GAIN_ODD_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__LNA_GAIN_ODD_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__GM_GAIN_ODD_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__TIA_GAIN_ODD_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__SLM_XLNA_ODD_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__BQ_GAIN_ODD_186___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__XLNA_GAIN_EVEN_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__LNA_GAIN_EVEN_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__GM_GAIN_EVEN_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__TIA_GAIN_EVEN_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__SLM_XLNA_EVEN_186___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__BQ_GAIN_EVEN_186___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__XLNA_GAIN_ODD_186___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__XLNA_GAIN_ODD_186___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__LNA_GAIN_ODD_186___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__LNA_GAIN_ODD_186___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__GM_GAIN_ODD_186___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__GM_GAIN_ODD_186___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__TIA_GAIN_ODD_186___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__TIA_GAIN_ODD_186___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__SLM_XLNA_ODD_186___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__SLM_XLNA_ODD_186___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__BQ_GAIN_ODD_186___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__BQ_GAIN_ODD_186___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__XLNA_GAIN_EVEN_186___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__XLNA_GAIN_EVEN_186___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__LNA_GAIN_EVEN_186___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__LNA_GAIN_EVEN_186___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__GM_GAIN_EVEN_186___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__GM_GAIN_EVEN_186___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__TIA_GAIN_EVEN_186___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__TIA_GAIN_EVEN_186___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__SLM_XLNA_EVEN_186___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__SLM_XLNA_EVEN_186___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__BQ_GAIN_EVEN_186___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186__BQ_GAIN_EVEN_186___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_186___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187 (0x005FD2EC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__XLNA_GAIN_ODD_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__LNA_GAIN_ODD_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__GM_GAIN_ODD_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__TIA_GAIN_ODD_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__SLM_XLNA_ODD_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__BQ_GAIN_ODD_187___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__XLNA_GAIN_EVEN_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__LNA_GAIN_EVEN_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__GM_GAIN_EVEN_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__TIA_GAIN_EVEN_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__SLM_XLNA_EVEN_187___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__BQ_GAIN_EVEN_187___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__XLNA_GAIN_ODD_187___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__XLNA_GAIN_ODD_187___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__LNA_GAIN_ODD_187___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__LNA_GAIN_ODD_187___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__GM_GAIN_ODD_187___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__GM_GAIN_ODD_187___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__TIA_GAIN_ODD_187___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__TIA_GAIN_ODD_187___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__SLM_XLNA_ODD_187___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__SLM_XLNA_ODD_187___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__BQ_GAIN_ODD_187___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__BQ_GAIN_ODD_187___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__XLNA_GAIN_EVEN_187___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__XLNA_GAIN_EVEN_187___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__LNA_GAIN_EVEN_187___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__LNA_GAIN_EVEN_187___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__GM_GAIN_EVEN_187___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__GM_GAIN_EVEN_187___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__TIA_GAIN_EVEN_187___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__TIA_GAIN_EVEN_187___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__SLM_XLNA_EVEN_187___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__SLM_XLNA_EVEN_187___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__BQ_GAIN_EVEN_187___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187__BQ_GAIN_EVEN_187___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_187___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188 (0x005FD2F0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__XLNA_GAIN_ODD_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__LNA_GAIN_ODD_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__GM_GAIN_ODD_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__TIA_GAIN_ODD_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__SLM_XLNA_ODD_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__BQ_GAIN_ODD_188___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__XLNA_GAIN_EVEN_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__LNA_GAIN_EVEN_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__GM_GAIN_EVEN_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__TIA_GAIN_EVEN_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__SLM_XLNA_EVEN_188___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__BQ_GAIN_EVEN_188___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__XLNA_GAIN_ODD_188___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__XLNA_GAIN_ODD_188___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__LNA_GAIN_ODD_188___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__LNA_GAIN_ODD_188___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__GM_GAIN_ODD_188___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__GM_GAIN_ODD_188___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__TIA_GAIN_ODD_188___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__TIA_GAIN_ODD_188___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__SLM_XLNA_ODD_188___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__SLM_XLNA_ODD_188___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__BQ_GAIN_ODD_188___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__BQ_GAIN_ODD_188___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__XLNA_GAIN_EVEN_188___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__XLNA_GAIN_EVEN_188___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__LNA_GAIN_EVEN_188___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__LNA_GAIN_EVEN_188___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__GM_GAIN_EVEN_188___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__GM_GAIN_EVEN_188___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__TIA_GAIN_EVEN_188___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__TIA_GAIN_EVEN_188___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__SLM_XLNA_EVEN_188___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__SLM_XLNA_EVEN_188___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__BQ_GAIN_EVEN_188___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188__BQ_GAIN_EVEN_188___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_188___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189 (0x005FD2F4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__XLNA_GAIN_ODD_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__LNA_GAIN_ODD_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__GM_GAIN_ODD_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__TIA_GAIN_ODD_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__SLM_XLNA_ODD_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__BQ_GAIN_ODD_189___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__XLNA_GAIN_EVEN_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__LNA_GAIN_EVEN_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__GM_GAIN_EVEN_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__TIA_GAIN_EVEN_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__SLM_XLNA_EVEN_189___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__BQ_GAIN_EVEN_189___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__XLNA_GAIN_ODD_189___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__XLNA_GAIN_ODD_189___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__LNA_GAIN_ODD_189___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__LNA_GAIN_ODD_189___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__GM_GAIN_ODD_189___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__GM_GAIN_ODD_189___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__TIA_GAIN_ODD_189___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__TIA_GAIN_ODD_189___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__SLM_XLNA_ODD_189___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__SLM_XLNA_ODD_189___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__BQ_GAIN_ODD_189___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__BQ_GAIN_ODD_189___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__XLNA_GAIN_EVEN_189___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__XLNA_GAIN_EVEN_189___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__LNA_GAIN_EVEN_189___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__LNA_GAIN_EVEN_189___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__GM_GAIN_EVEN_189___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__GM_GAIN_EVEN_189___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__TIA_GAIN_EVEN_189___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__TIA_GAIN_EVEN_189___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__SLM_XLNA_EVEN_189___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__SLM_XLNA_EVEN_189___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__BQ_GAIN_EVEN_189___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189__BQ_GAIN_EVEN_189___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_189___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190 (0x005FD2F8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__XLNA_GAIN_ODD_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__LNA_GAIN_ODD_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__GM_GAIN_ODD_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__TIA_GAIN_ODD_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__SLM_XLNA_ODD_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__BQ_GAIN_ODD_190___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__XLNA_GAIN_EVEN_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__LNA_GAIN_EVEN_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__GM_GAIN_EVEN_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__TIA_GAIN_EVEN_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__SLM_XLNA_EVEN_190___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__BQ_GAIN_EVEN_190___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__XLNA_GAIN_ODD_190___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__XLNA_GAIN_ODD_190___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__LNA_GAIN_ODD_190___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__LNA_GAIN_ODD_190___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__GM_GAIN_ODD_190___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__GM_GAIN_ODD_190___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__TIA_GAIN_ODD_190___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__TIA_GAIN_ODD_190___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__SLM_XLNA_ODD_190___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__SLM_XLNA_ODD_190___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__BQ_GAIN_ODD_190___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__BQ_GAIN_ODD_190___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__XLNA_GAIN_EVEN_190___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__XLNA_GAIN_EVEN_190___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__LNA_GAIN_EVEN_190___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__LNA_GAIN_EVEN_190___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__GM_GAIN_EVEN_190___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__GM_GAIN_EVEN_190___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__TIA_GAIN_EVEN_190___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__TIA_GAIN_EVEN_190___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__SLM_XLNA_EVEN_190___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__SLM_XLNA_EVEN_190___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__BQ_GAIN_EVEN_190___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190__BQ_GAIN_EVEN_190___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_190___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191 (0x005FD2FC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__XLNA_GAIN_ODD_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__LNA_GAIN_ODD_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__GM_GAIN_ODD_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__TIA_GAIN_ODD_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__SLM_XLNA_ODD_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__BQ_GAIN_ODD_191___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__XLNA_GAIN_EVEN_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__LNA_GAIN_EVEN_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__GM_GAIN_EVEN_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__TIA_GAIN_EVEN_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__SLM_XLNA_EVEN_191___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__BQ_GAIN_EVEN_191___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__XLNA_GAIN_ODD_191___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__XLNA_GAIN_ODD_191___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__LNA_GAIN_ODD_191___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__LNA_GAIN_ODD_191___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__GM_GAIN_ODD_191___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__GM_GAIN_ODD_191___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__TIA_GAIN_ODD_191___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__TIA_GAIN_ODD_191___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__SLM_XLNA_ODD_191___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__SLM_XLNA_ODD_191___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__BQ_GAIN_ODD_191___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__BQ_GAIN_ODD_191___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__XLNA_GAIN_EVEN_191___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__XLNA_GAIN_EVEN_191___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__LNA_GAIN_EVEN_191___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__LNA_GAIN_EVEN_191___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__GM_GAIN_EVEN_191___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__GM_GAIN_EVEN_191___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__TIA_GAIN_EVEN_191___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__TIA_GAIN_EVEN_191___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__SLM_XLNA_EVEN_191___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__SLM_XLNA_EVEN_191___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__BQ_GAIN_EVEN_191___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191__BQ_GAIN_EVEN_191___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_191___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192 (0x005FD300) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__XLNA_GAIN_ODD_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__LNA_GAIN_ODD_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__GM_GAIN_ODD_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__TIA_GAIN_ODD_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__SLM_XLNA_ODD_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__BQ_GAIN_ODD_192___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__XLNA_GAIN_EVEN_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__LNA_GAIN_EVEN_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__GM_GAIN_EVEN_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__TIA_GAIN_EVEN_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__SLM_XLNA_EVEN_192___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__BQ_GAIN_EVEN_192___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__XLNA_GAIN_ODD_192___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__XLNA_GAIN_ODD_192___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__LNA_GAIN_ODD_192___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__LNA_GAIN_ODD_192___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__GM_GAIN_ODD_192___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__GM_GAIN_ODD_192___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__TIA_GAIN_ODD_192___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__TIA_GAIN_ODD_192___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__SLM_XLNA_ODD_192___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__SLM_XLNA_ODD_192___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__BQ_GAIN_ODD_192___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__BQ_GAIN_ODD_192___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__XLNA_GAIN_EVEN_192___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__XLNA_GAIN_EVEN_192___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__LNA_GAIN_EVEN_192___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__LNA_GAIN_EVEN_192___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__GM_GAIN_EVEN_192___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__GM_GAIN_EVEN_192___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__TIA_GAIN_EVEN_192___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__TIA_GAIN_EVEN_192___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__SLM_XLNA_EVEN_192___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__SLM_XLNA_EVEN_192___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__BQ_GAIN_EVEN_192___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192__BQ_GAIN_EVEN_192___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_192___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193 (0x005FD304) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__XLNA_GAIN_ODD_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__LNA_GAIN_ODD_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__GM_GAIN_ODD_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__TIA_GAIN_ODD_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__SLM_XLNA_ODD_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__BQ_GAIN_ODD_193___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__XLNA_GAIN_EVEN_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__LNA_GAIN_EVEN_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__GM_GAIN_EVEN_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__TIA_GAIN_EVEN_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__SLM_XLNA_EVEN_193___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__BQ_GAIN_EVEN_193___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__XLNA_GAIN_ODD_193___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__XLNA_GAIN_ODD_193___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__LNA_GAIN_ODD_193___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__LNA_GAIN_ODD_193___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__GM_GAIN_ODD_193___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__GM_GAIN_ODD_193___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__TIA_GAIN_ODD_193___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__TIA_GAIN_ODD_193___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__SLM_XLNA_ODD_193___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__SLM_XLNA_ODD_193___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__BQ_GAIN_ODD_193___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__BQ_GAIN_ODD_193___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__XLNA_GAIN_EVEN_193___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__XLNA_GAIN_EVEN_193___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__LNA_GAIN_EVEN_193___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__LNA_GAIN_EVEN_193___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__GM_GAIN_EVEN_193___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__GM_GAIN_EVEN_193___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__TIA_GAIN_EVEN_193___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__TIA_GAIN_EVEN_193___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__SLM_XLNA_EVEN_193___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__SLM_XLNA_EVEN_193___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__BQ_GAIN_EVEN_193___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193__BQ_GAIN_EVEN_193___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_193___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194 (0x005FD308) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__XLNA_GAIN_ODD_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__LNA_GAIN_ODD_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__GM_GAIN_ODD_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__TIA_GAIN_ODD_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__SLM_XLNA_ODD_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__BQ_GAIN_ODD_194___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__XLNA_GAIN_EVEN_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__LNA_GAIN_EVEN_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__GM_GAIN_EVEN_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__TIA_GAIN_EVEN_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__SLM_XLNA_EVEN_194___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__BQ_GAIN_EVEN_194___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__XLNA_GAIN_ODD_194___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__XLNA_GAIN_ODD_194___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__LNA_GAIN_ODD_194___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__LNA_GAIN_ODD_194___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__GM_GAIN_ODD_194___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__GM_GAIN_ODD_194___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__TIA_GAIN_ODD_194___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__TIA_GAIN_ODD_194___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__SLM_XLNA_ODD_194___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__SLM_XLNA_ODD_194___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__BQ_GAIN_ODD_194___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__BQ_GAIN_ODD_194___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__XLNA_GAIN_EVEN_194___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__XLNA_GAIN_EVEN_194___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__LNA_GAIN_EVEN_194___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__LNA_GAIN_EVEN_194___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__GM_GAIN_EVEN_194___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__GM_GAIN_EVEN_194___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__TIA_GAIN_EVEN_194___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__TIA_GAIN_EVEN_194___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__SLM_XLNA_EVEN_194___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__SLM_XLNA_EVEN_194___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__BQ_GAIN_EVEN_194___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194__BQ_GAIN_EVEN_194___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_194___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195 (0x005FD30C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__XLNA_GAIN_ODD_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__LNA_GAIN_ODD_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__GM_GAIN_ODD_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__TIA_GAIN_ODD_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__SLM_XLNA_ODD_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__BQ_GAIN_ODD_195___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__XLNA_GAIN_EVEN_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__LNA_GAIN_EVEN_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__GM_GAIN_EVEN_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__TIA_GAIN_EVEN_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__SLM_XLNA_EVEN_195___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__BQ_GAIN_EVEN_195___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__XLNA_GAIN_ODD_195___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__XLNA_GAIN_ODD_195___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__LNA_GAIN_ODD_195___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__LNA_GAIN_ODD_195___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__GM_GAIN_ODD_195___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__GM_GAIN_ODD_195___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__TIA_GAIN_ODD_195___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__TIA_GAIN_ODD_195___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__SLM_XLNA_ODD_195___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__SLM_XLNA_ODD_195___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__BQ_GAIN_ODD_195___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__BQ_GAIN_ODD_195___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__XLNA_GAIN_EVEN_195___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__XLNA_GAIN_EVEN_195___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__LNA_GAIN_EVEN_195___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__LNA_GAIN_EVEN_195___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__GM_GAIN_EVEN_195___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__GM_GAIN_EVEN_195___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__TIA_GAIN_EVEN_195___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__TIA_GAIN_EVEN_195___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__SLM_XLNA_EVEN_195___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__SLM_XLNA_EVEN_195___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__BQ_GAIN_EVEN_195___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195__BQ_GAIN_EVEN_195___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_195___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196 (0x005FD310) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__XLNA_GAIN_ODD_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__LNA_GAIN_ODD_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__GM_GAIN_ODD_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__TIA_GAIN_ODD_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__SLM_XLNA_ODD_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__BQ_GAIN_ODD_196___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__XLNA_GAIN_EVEN_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__LNA_GAIN_EVEN_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__GM_GAIN_EVEN_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__TIA_GAIN_EVEN_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__SLM_XLNA_EVEN_196___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__BQ_GAIN_EVEN_196___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__XLNA_GAIN_ODD_196___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__XLNA_GAIN_ODD_196___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__LNA_GAIN_ODD_196___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__LNA_GAIN_ODD_196___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__GM_GAIN_ODD_196___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__GM_GAIN_ODD_196___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__TIA_GAIN_ODD_196___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__TIA_GAIN_ODD_196___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__SLM_XLNA_ODD_196___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__SLM_XLNA_ODD_196___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__BQ_GAIN_ODD_196___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__BQ_GAIN_ODD_196___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__XLNA_GAIN_EVEN_196___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__XLNA_GAIN_EVEN_196___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__LNA_GAIN_EVEN_196___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__LNA_GAIN_EVEN_196___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__GM_GAIN_EVEN_196___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__GM_GAIN_EVEN_196___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__TIA_GAIN_EVEN_196___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__TIA_GAIN_EVEN_196___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__SLM_XLNA_EVEN_196___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__SLM_XLNA_EVEN_196___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__BQ_GAIN_EVEN_196___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196__BQ_GAIN_EVEN_196___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_196___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197 (0x005FD314) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__XLNA_GAIN_ODD_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__LNA_GAIN_ODD_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__GM_GAIN_ODD_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__TIA_GAIN_ODD_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__SLM_XLNA_ODD_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__BQ_GAIN_ODD_197___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__XLNA_GAIN_EVEN_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__LNA_GAIN_EVEN_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__GM_GAIN_EVEN_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__TIA_GAIN_EVEN_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__SLM_XLNA_EVEN_197___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__BQ_GAIN_EVEN_197___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__XLNA_GAIN_ODD_197___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__XLNA_GAIN_ODD_197___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__LNA_GAIN_ODD_197___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__LNA_GAIN_ODD_197___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__GM_GAIN_ODD_197___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__GM_GAIN_ODD_197___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__TIA_GAIN_ODD_197___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__TIA_GAIN_ODD_197___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__SLM_XLNA_ODD_197___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__SLM_XLNA_ODD_197___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__BQ_GAIN_ODD_197___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__BQ_GAIN_ODD_197___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__XLNA_GAIN_EVEN_197___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__XLNA_GAIN_EVEN_197___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__LNA_GAIN_EVEN_197___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__LNA_GAIN_EVEN_197___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__GM_GAIN_EVEN_197___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__GM_GAIN_EVEN_197___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__TIA_GAIN_EVEN_197___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__TIA_GAIN_EVEN_197___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__SLM_XLNA_EVEN_197___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__SLM_XLNA_EVEN_197___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__BQ_GAIN_EVEN_197___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197__BQ_GAIN_EVEN_197___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_197___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198 (0x005FD318) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__XLNA_GAIN_ODD_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__LNA_GAIN_ODD_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__GM_GAIN_ODD_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__TIA_GAIN_ODD_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__SLM_XLNA_ODD_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__BQ_GAIN_ODD_198___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__XLNA_GAIN_EVEN_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__LNA_GAIN_EVEN_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__GM_GAIN_EVEN_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__TIA_GAIN_EVEN_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__SLM_XLNA_EVEN_198___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__BQ_GAIN_EVEN_198___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__XLNA_GAIN_ODD_198___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__XLNA_GAIN_ODD_198___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__LNA_GAIN_ODD_198___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__LNA_GAIN_ODD_198___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__GM_GAIN_ODD_198___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__GM_GAIN_ODD_198___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__TIA_GAIN_ODD_198___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__TIA_GAIN_ODD_198___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__SLM_XLNA_ODD_198___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__SLM_XLNA_ODD_198___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__BQ_GAIN_ODD_198___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__BQ_GAIN_ODD_198___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__XLNA_GAIN_EVEN_198___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__XLNA_GAIN_EVEN_198___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__LNA_GAIN_EVEN_198___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__LNA_GAIN_EVEN_198___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__GM_GAIN_EVEN_198___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__GM_GAIN_EVEN_198___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__TIA_GAIN_EVEN_198___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__TIA_GAIN_EVEN_198___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__SLM_XLNA_EVEN_198___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__SLM_XLNA_EVEN_198___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__BQ_GAIN_EVEN_198___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198__BQ_GAIN_EVEN_198___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_198___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199 (0x005FD31C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__XLNA_GAIN_ODD_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__LNA_GAIN_ODD_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__GM_GAIN_ODD_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__TIA_GAIN_ODD_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__SLM_XLNA_ODD_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__BQ_GAIN_ODD_199___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__XLNA_GAIN_EVEN_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__LNA_GAIN_EVEN_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__GM_GAIN_EVEN_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__TIA_GAIN_EVEN_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__SLM_XLNA_EVEN_199___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__BQ_GAIN_EVEN_199___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__XLNA_GAIN_ODD_199___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__XLNA_GAIN_ODD_199___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__LNA_GAIN_ODD_199___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__LNA_GAIN_ODD_199___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__GM_GAIN_ODD_199___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__GM_GAIN_ODD_199___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__TIA_GAIN_ODD_199___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__TIA_GAIN_ODD_199___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__SLM_XLNA_ODD_199___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__SLM_XLNA_ODD_199___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__BQ_GAIN_ODD_199___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__BQ_GAIN_ODD_199___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__XLNA_GAIN_EVEN_199___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__XLNA_GAIN_EVEN_199___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__LNA_GAIN_EVEN_199___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__LNA_GAIN_EVEN_199___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__GM_GAIN_EVEN_199___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__GM_GAIN_EVEN_199___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__TIA_GAIN_EVEN_199___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__TIA_GAIN_EVEN_199___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__SLM_XLNA_EVEN_199___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__SLM_XLNA_EVEN_199___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__BQ_GAIN_EVEN_199___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199__BQ_GAIN_EVEN_199___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_199___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200 (0x005FD320) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__XLNA_GAIN_ODD_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__LNA_GAIN_ODD_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__GM_GAIN_ODD_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__TIA_GAIN_ODD_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__SLM_XLNA_ODD_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__BQ_GAIN_ODD_200___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__XLNA_GAIN_EVEN_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__LNA_GAIN_EVEN_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__GM_GAIN_EVEN_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__TIA_GAIN_EVEN_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__SLM_XLNA_EVEN_200___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__BQ_GAIN_EVEN_200___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__XLNA_GAIN_ODD_200___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__XLNA_GAIN_ODD_200___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__LNA_GAIN_ODD_200___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__LNA_GAIN_ODD_200___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__GM_GAIN_ODD_200___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__GM_GAIN_ODD_200___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__TIA_GAIN_ODD_200___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__TIA_GAIN_ODD_200___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__SLM_XLNA_ODD_200___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__SLM_XLNA_ODD_200___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__BQ_GAIN_ODD_200___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__BQ_GAIN_ODD_200___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__XLNA_GAIN_EVEN_200___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__XLNA_GAIN_EVEN_200___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__LNA_GAIN_EVEN_200___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__LNA_GAIN_EVEN_200___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__GM_GAIN_EVEN_200___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__GM_GAIN_EVEN_200___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__TIA_GAIN_EVEN_200___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__TIA_GAIN_EVEN_200___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__SLM_XLNA_EVEN_200___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__SLM_XLNA_EVEN_200___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__BQ_GAIN_EVEN_200___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200__BQ_GAIN_EVEN_200___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_200___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201 (0x005FD324) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__XLNA_GAIN_ODD_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__LNA_GAIN_ODD_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__GM_GAIN_ODD_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__TIA_GAIN_ODD_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__SLM_XLNA_ODD_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__BQ_GAIN_ODD_201___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__XLNA_GAIN_EVEN_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__LNA_GAIN_EVEN_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__GM_GAIN_EVEN_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__TIA_GAIN_EVEN_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__SLM_XLNA_EVEN_201___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__BQ_GAIN_EVEN_201___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__XLNA_GAIN_ODD_201___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__XLNA_GAIN_ODD_201___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__LNA_GAIN_ODD_201___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__LNA_GAIN_ODD_201___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__GM_GAIN_ODD_201___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__GM_GAIN_ODD_201___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__TIA_GAIN_ODD_201___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__TIA_GAIN_ODD_201___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__SLM_XLNA_ODD_201___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__SLM_XLNA_ODD_201___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__BQ_GAIN_ODD_201___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__BQ_GAIN_ODD_201___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__XLNA_GAIN_EVEN_201___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__XLNA_GAIN_EVEN_201___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__LNA_GAIN_EVEN_201___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__LNA_GAIN_EVEN_201___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__GM_GAIN_EVEN_201___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__GM_GAIN_EVEN_201___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__TIA_GAIN_EVEN_201___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__TIA_GAIN_EVEN_201___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__SLM_XLNA_EVEN_201___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__SLM_XLNA_EVEN_201___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__BQ_GAIN_EVEN_201___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201__BQ_GAIN_EVEN_201___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_201___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202 (0x005FD328) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__XLNA_GAIN_ODD_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__LNA_GAIN_ODD_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__GM_GAIN_ODD_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__TIA_GAIN_ODD_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__SLM_XLNA_ODD_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__BQ_GAIN_ODD_202___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__XLNA_GAIN_EVEN_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__LNA_GAIN_EVEN_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__GM_GAIN_EVEN_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__TIA_GAIN_EVEN_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__SLM_XLNA_EVEN_202___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__BQ_GAIN_EVEN_202___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__XLNA_GAIN_ODD_202___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__XLNA_GAIN_ODD_202___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__LNA_GAIN_ODD_202___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__LNA_GAIN_ODD_202___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__GM_GAIN_ODD_202___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__GM_GAIN_ODD_202___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__TIA_GAIN_ODD_202___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__TIA_GAIN_ODD_202___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__SLM_XLNA_ODD_202___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__SLM_XLNA_ODD_202___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__BQ_GAIN_ODD_202___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__BQ_GAIN_ODD_202___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__XLNA_GAIN_EVEN_202___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__XLNA_GAIN_EVEN_202___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__LNA_GAIN_EVEN_202___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__LNA_GAIN_EVEN_202___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__GM_GAIN_EVEN_202___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__GM_GAIN_EVEN_202___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__TIA_GAIN_EVEN_202___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__TIA_GAIN_EVEN_202___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__SLM_XLNA_EVEN_202___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__SLM_XLNA_EVEN_202___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__BQ_GAIN_EVEN_202___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202__BQ_GAIN_EVEN_202___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_202___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203 (0x005FD32C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__XLNA_GAIN_ODD_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__LNA_GAIN_ODD_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__GM_GAIN_ODD_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__TIA_GAIN_ODD_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__SLM_XLNA_ODD_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__BQ_GAIN_ODD_203___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__XLNA_GAIN_EVEN_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__LNA_GAIN_EVEN_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__GM_GAIN_EVEN_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__TIA_GAIN_EVEN_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__SLM_XLNA_EVEN_203___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__BQ_GAIN_EVEN_203___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__XLNA_GAIN_ODD_203___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__XLNA_GAIN_ODD_203___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__LNA_GAIN_ODD_203___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__LNA_GAIN_ODD_203___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__GM_GAIN_ODD_203___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__GM_GAIN_ODD_203___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__TIA_GAIN_ODD_203___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__TIA_GAIN_ODD_203___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__SLM_XLNA_ODD_203___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__SLM_XLNA_ODD_203___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__BQ_GAIN_ODD_203___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__BQ_GAIN_ODD_203___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__XLNA_GAIN_EVEN_203___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__XLNA_GAIN_EVEN_203___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__LNA_GAIN_EVEN_203___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__LNA_GAIN_EVEN_203___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__GM_GAIN_EVEN_203___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__GM_GAIN_EVEN_203___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__TIA_GAIN_EVEN_203___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__TIA_GAIN_EVEN_203___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__SLM_XLNA_EVEN_203___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__SLM_XLNA_EVEN_203___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__BQ_GAIN_EVEN_203___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203__BQ_GAIN_EVEN_203___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_203___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204 (0x005FD330) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__XLNA_GAIN_ODD_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__LNA_GAIN_ODD_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__GM_GAIN_ODD_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__TIA_GAIN_ODD_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__SLM_XLNA_ODD_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__BQ_GAIN_ODD_204___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__XLNA_GAIN_EVEN_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__LNA_GAIN_EVEN_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__GM_GAIN_EVEN_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__TIA_GAIN_EVEN_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__SLM_XLNA_EVEN_204___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__BQ_GAIN_EVEN_204___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__XLNA_GAIN_ODD_204___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__XLNA_GAIN_ODD_204___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__LNA_GAIN_ODD_204___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__LNA_GAIN_ODD_204___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__GM_GAIN_ODD_204___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__GM_GAIN_ODD_204___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__TIA_GAIN_ODD_204___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__TIA_GAIN_ODD_204___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__SLM_XLNA_ODD_204___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__SLM_XLNA_ODD_204___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__BQ_GAIN_ODD_204___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__BQ_GAIN_ODD_204___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__XLNA_GAIN_EVEN_204___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__XLNA_GAIN_EVEN_204___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__LNA_GAIN_EVEN_204___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__LNA_GAIN_EVEN_204___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__GM_GAIN_EVEN_204___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__GM_GAIN_EVEN_204___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__TIA_GAIN_EVEN_204___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__TIA_GAIN_EVEN_204___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__SLM_XLNA_EVEN_204___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__SLM_XLNA_EVEN_204___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__BQ_GAIN_EVEN_204___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204__BQ_GAIN_EVEN_204___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_204___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205 (0x005FD334) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__XLNA_GAIN_ODD_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__LNA_GAIN_ODD_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__GM_GAIN_ODD_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__TIA_GAIN_ODD_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__SLM_XLNA_ODD_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__BQ_GAIN_ODD_205___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__XLNA_GAIN_EVEN_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__LNA_GAIN_EVEN_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__GM_GAIN_EVEN_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__TIA_GAIN_EVEN_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__SLM_XLNA_EVEN_205___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__BQ_GAIN_EVEN_205___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__XLNA_GAIN_ODD_205___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__XLNA_GAIN_ODD_205___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__LNA_GAIN_ODD_205___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__LNA_GAIN_ODD_205___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__GM_GAIN_ODD_205___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__GM_GAIN_ODD_205___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__TIA_GAIN_ODD_205___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__TIA_GAIN_ODD_205___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__SLM_XLNA_ODD_205___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__SLM_XLNA_ODD_205___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__BQ_GAIN_ODD_205___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__BQ_GAIN_ODD_205___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__XLNA_GAIN_EVEN_205___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__XLNA_GAIN_EVEN_205___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__LNA_GAIN_EVEN_205___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__LNA_GAIN_EVEN_205___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__GM_GAIN_EVEN_205___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__GM_GAIN_EVEN_205___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__TIA_GAIN_EVEN_205___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__TIA_GAIN_EVEN_205___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__SLM_XLNA_EVEN_205___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__SLM_XLNA_EVEN_205___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__BQ_GAIN_EVEN_205___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205__BQ_GAIN_EVEN_205___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_205___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206 (0x005FD338) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__XLNA_GAIN_ODD_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__LNA_GAIN_ODD_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__GM_GAIN_ODD_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__TIA_GAIN_ODD_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__SLM_XLNA_ODD_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__BQ_GAIN_ODD_206___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__XLNA_GAIN_EVEN_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__LNA_GAIN_EVEN_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__GM_GAIN_EVEN_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__TIA_GAIN_EVEN_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__SLM_XLNA_EVEN_206___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__BQ_GAIN_EVEN_206___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__XLNA_GAIN_ODD_206___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__XLNA_GAIN_ODD_206___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__LNA_GAIN_ODD_206___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__LNA_GAIN_ODD_206___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__GM_GAIN_ODD_206___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__GM_GAIN_ODD_206___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__TIA_GAIN_ODD_206___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__TIA_GAIN_ODD_206___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__SLM_XLNA_ODD_206___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__SLM_XLNA_ODD_206___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__BQ_GAIN_ODD_206___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__BQ_GAIN_ODD_206___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__XLNA_GAIN_EVEN_206___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__XLNA_GAIN_EVEN_206___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__LNA_GAIN_EVEN_206___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__LNA_GAIN_EVEN_206___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__GM_GAIN_EVEN_206___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__GM_GAIN_EVEN_206___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__TIA_GAIN_EVEN_206___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__TIA_GAIN_EVEN_206___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__SLM_XLNA_EVEN_206___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__SLM_XLNA_EVEN_206___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__BQ_GAIN_EVEN_206___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206__BQ_GAIN_EVEN_206___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_206___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207 (0x005FD33C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__XLNA_GAIN_ODD_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__LNA_GAIN_ODD_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__GM_GAIN_ODD_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__TIA_GAIN_ODD_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__SLM_XLNA_ODD_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__BQ_GAIN_ODD_207___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__XLNA_GAIN_EVEN_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__LNA_GAIN_EVEN_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__GM_GAIN_EVEN_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__TIA_GAIN_EVEN_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__SLM_XLNA_EVEN_207___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__BQ_GAIN_EVEN_207___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__XLNA_GAIN_ODD_207___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__XLNA_GAIN_ODD_207___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__LNA_GAIN_ODD_207___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__LNA_GAIN_ODD_207___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__GM_GAIN_ODD_207___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__GM_GAIN_ODD_207___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__TIA_GAIN_ODD_207___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__TIA_GAIN_ODD_207___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__SLM_XLNA_ODD_207___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__SLM_XLNA_ODD_207___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__BQ_GAIN_ODD_207___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__BQ_GAIN_ODD_207___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__XLNA_GAIN_EVEN_207___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__XLNA_GAIN_EVEN_207___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__LNA_GAIN_EVEN_207___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__LNA_GAIN_EVEN_207___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__GM_GAIN_EVEN_207___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__GM_GAIN_EVEN_207___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__TIA_GAIN_EVEN_207___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__TIA_GAIN_EVEN_207___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__SLM_XLNA_EVEN_207___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__SLM_XLNA_EVEN_207___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__BQ_GAIN_EVEN_207___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207__BQ_GAIN_EVEN_207___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_207___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208 (0x005FD340) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__XLNA_GAIN_ODD_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__LNA_GAIN_ODD_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__GM_GAIN_ODD_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__TIA_GAIN_ODD_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__SLM_XLNA_ODD_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__BQ_GAIN_ODD_208___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__XLNA_GAIN_EVEN_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__LNA_GAIN_EVEN_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__GM_GAIN_EVEN_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__TIA_GAIN_EVEN_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__SLM_XLNA_EVEN_208___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__BQ_GAIN_EVEN_208___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__XLNA_GAIN_ODD_208___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__XLNA_GAIN_ODD_208___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__LNA_GAIN_ODD_208___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__LNA_GAIN_ODD_208___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__GM_GAIN_ODD_208___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__GM_GAIN_ODD_208___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__TIA_GAIN_ODD_208___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__TIA_GAIN_ODD_208___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__SLM_XLNA_ODD_208___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__SLM_XLNA_ODD_208___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__BQ_GAIN_ODD_208___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__BQ_GAIN_ODD_208___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__XLNA_GAIN_EVEN_208___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__XLNA_GAIN_EVEN_208___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__LNA_GAIN_EVEN_208___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__LNA_GAIN_EVEN_208___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__GM_GAIN_EVEN_208___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__GM_GAIN_EVEN_208___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__TIA_GAIN_EVEN_208___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__TIA_GAIN_EVEN_208___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__SLM_XLNA_EVEN_208___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__SLM_XLNA_EVEN_208___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__BQ_GAIN_EVEN_208___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208__BQ_GAIN_EVEN_208___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_208___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209 (0x005FD344) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__XLNA_GAIN_ODD_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__LNA_GAIN_ODD_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__GM_GAIN_ODD_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__TIA_GAIN_ODD_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__SLM_XLNA_ODD_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__BQ_GAIN_ODD_209___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__XLNA_GAIN_EVEN_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__LNA_GAIN_EVEN_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__GM_GAIN_EVEN_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__TIA_GAIN_EVEN_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__SLM_XLNA_EVEN_209___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__BQ_GAIN_EVEN_209___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__XLNA_GAIN_ODD_209___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__XLNA_GAIN_ODD_209___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__LNA_GAIN_ODD_209___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__LNA_GAIN_ODD_209___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__GM_GAIN_ODD_209___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__GM_GAIN_ODD_209___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__TIA_GAIN_ODD_209___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__TIA_GAIN_ODD_209___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__SLM_XLNA_ODD_209___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__SLM_XLNA_ODD_209___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__BQ_GAIN_ODD_209___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__BQ_GAIN_ODD_209___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__XLNA_GAIN_EVEN_209___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__XLNA_GAIN_EVEN_209___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__LNA_GAIN_EVEN_209___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__LNA_GAIN_EVEN_209___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__GM_GAIN_EVEN_209___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__GM_GAIN_EVEN_209___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__TIA_GAIN_EVEN_209___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__TIA_GAIN_EVEN_209___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__SLM_XLNA_EVEN_209___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__SLM_XLNA_EVEN_209___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__BQ_GAIN_EVEN_209___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209__BQ_GAIN_EVEN_209___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_209___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210 (0x005FD348) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__XLNA_GAIN_ODD_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__LNA_GAIN_ODD_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__GM_GAIN_ODD_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__TIA_GAIN_ODD_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__SLM_XLNA_ODD_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__BQ_GAIN_ODD_210___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__XLNA_GAIN_EVEN_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__LNA_GAIN_EVEN_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__GM_GAIN_EVEN_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__TIA_GAIN_EVEN_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__SLM_XLNA_EVEN_210___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__BQ_GAIN_EVEN_210___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__XLNA_GAIN_ODD_210___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__XLNA_GAIN_ODD_210___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__LNA_GAIN_ODD_210___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__LNA_GAIN_ODD_210___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__GM_GAIN_ODD_210___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__GM_GAIN_ODD_210___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__TIA_GAIN_ODD_210___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__TIA_GAIN_ODD_210___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__SLM_XLNA_ODD_210___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__SLM_XLNA_ODD_210___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__BQ_GAIN_ODD_210___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__BQ_GAIN_ODD_210___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__XLNA_GAIN_EVEN_210___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__XLNA_GAIN_EVEN_210___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__LNA_GAIN_EVEN_210___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__LNA_GAIN_EVEN_210___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__GM_GAIN_EVEN_210___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__GM_GAIN_EVEN_210___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__TIA_GAIN_EVEN_210___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__TIA_GAIN_EVEN_210___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__SLM_XLNA_EVEN_210___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__SLM_XLNA_EVEN_210___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__BQ_GAIN_EVEN_210___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210__BQ_GAIN_EVEN_210___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_210___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211 (0x005FD34C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__XLNA_GAIN_ODD_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__LNA_GAIN_ODD_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__GM_GAIN_ODD_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__TIA_GAIN_ODD_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__SLM_XLNA_ODD_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__BQ_GAIN_ODD_211___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__XLNA_GAIN_EVEN_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__LNA_GAIN_EVEN_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__GM_GAIN_EVEN_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__TIA_GAIN_EVEN_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__SLM_XLNA_EVEN_211___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__BQ_GAIN_EVEN_211___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__XLNA_GAIN_ODD_211___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__XLNA_GAIN_ODD_211___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__LNA_GAIN_ODD_211___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__LNA_GAIN_ODD_211___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__GM_GAIN_ODD_211___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__GM_GAIN_ODD_211___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__TIA_GAIN_ODD_211___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__TIA_GAIN_ODD_211___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__SLM_XLNA_ODD_211___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__SLM_XLNA_ODD_211___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__BQ_GAIN_ODD_211___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__BQ_GAIN_ODD_211___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__XLNA_GAIN_EVEN_211___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__XLNA_GAIN_EVEN_211___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__LNA_GAIN_EVEN_211___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__LNA_GAIN_EVEN_211___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__GM_GAIN_EVEN_211___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__GM_GAIN_EVEN_211___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__TIA_GAIN_EVEN_211___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__TIA_GAIN_EVEN_211___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__SLM_XLNA_EVEN_211___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__SLM_XLNA_EVEN_211___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__BQ_GAIN_EVEN_211___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211__BQ_GAIN_EVEN_211___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_211___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212 (0x005FD350) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__XLNA_GAIN_ODD_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__LNA_GAIN_ODD_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__GM_GAIN_ODD_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__TIA_GAIN_ODD_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__SLM_XLNA_ODD_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__BQ_GAIN_ODD_212___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__XLNA_GAIN_EVEN_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__LNA_GAIN_EVEN_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__GM_GAIN_EVEN_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__TIA_GAIN_EVEN_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__SLM_XLNA_EVEN_212___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__BQ_GAIN_EVEN_212___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__XLNA_GAIN_ODD_212___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__XLNA_GAIN_ODD_212___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__LNA_GAIN_ODD_212___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__LNA_GAIN_ODD_212___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__GM_GAIN_ODD_212___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__GM_GAIN_ODD_212___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__TIA_GAIN_ODD_212___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__TIA_GAIN_ODD_212___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__SLM_XLNA_ODD_212___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__SLM_XLNA_ODD_212___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__BQ_GAIN_ODD_212___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__BQ_GAIN_ODD_212___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__XLNA_GAIN_EVEN_212___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__XLNA_GAIN_EVEN_212___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__LNA_GAIN_EVEN_212___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__LNA_GAIN_EVEN_212___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__GM_GAIN_EVEN_212___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__GM_GAIN_EVEN_212___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__TIA_GAIN_EVEN_212___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__TIA_GAIN_EVEN_212___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__SLM_XLNA_EVEN_212___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__SLM_XLNA_EVEN_212___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__BQ_GAIN_EVEN_212___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212__BQ_GAIN_EVEN_212___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_212___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213 (0x005FD354) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__XLNA_GAIN_ODD_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__LNA_GAIN_ODD_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__GM_GAIN_ODD_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__TIA_GAIN_ODD_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__SLM_XLNA_ODD_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__BQ_GAIN_ODD_213___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__XLNA_GAIN_EVEN_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__LNA_GAIN_EVEN_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__GM_GAIN_EVEN_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__TIA_GAIN_EVEN_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__SLM_XLNA_EVEN_213___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__BQ_GAIN_EVEN_213___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__XLNA_GAIN_ODD_213___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__XLNA_GAIN_ODD_213___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__LNA_GAIN_ODD_213___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__LNA_GAIN_ODD_213___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__GM_GAIN_ODD_213___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__GM_GAIN_ODD_213___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__TIA_GAIN_ODD_213___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__TIA_GAIN_ODD_213___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__SLM_XLNA_ODD_213___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__SLM_XLNA_ODD_213___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__BQ_GAIN_ODD_213___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__BQ_GAIN_ODD_213___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__XLNA_GAIN_EVEN_213___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__XLNA_GAIN_EVEN_213___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__LNA_GAIN_EVEN_213___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__LNA_GAIN_EVEN_213___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__GM_GAIN_EVEN_213___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__GM_GAIN_EVEN_213___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__TIA_GAIN_EVEN_213___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__TIA_GAIN_EVEN_213___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__SLM_XLNA_EVEN_213___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__SLM_XLNA_EVEN_213___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__BQ_GAIN_EVEN_213___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213__BQ_GAIN_EVEN_213___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_213___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214 (0x005FD358) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__XLNA_GAIN_ODD_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__LNA_GAIN_ODD_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__GM_GAIN_ODD_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__TIA_GAIN_ODD_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__SLM_XLNA_ODD_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__BQ_GAIN_ODD_214___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__XLNA_GAIN_EVEN_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__LNA_GAIN_EVEN_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__GM_GAIN_EVEN_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__TIA_GAIN_EVEN_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__SLM_XLNA_EVEN_214___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__BQ_GAIN_EVEN_214___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__XLNA_GAIN_ODD_214___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__XLNA_GAIN_ODD_214___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__LNA_GAIN_ODD_214___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__LNA_GAIN_ODD_214___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__GM_GAIN_ODD_214___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__GM_GAIN_ODD_214___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__TIA_GAIN_ODD_214___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__TIA_GAIN_ODD_214___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__SLM_XLNA_ODD_214___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__SLM_XLNA_ODD_214___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__BQ_GAIN_ODD_214___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__BQ_GAIN_ODD_214___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__XLNA_GAIN_EVEN_214___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__XLNA_GAIN_EVEN_214___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__LNA_GAIN_EVEN_214___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__LNA_GAIN_EVEN_214___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__GM_GAIN_EVEN_214___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__GM_GAIN_EVEN_214___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__TIA_GAIN_EVEN_214___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__TIA_GAIN_EVEN_214___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__SLM_XLNA_EVEN_214___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__SLM_XLNA_EVEN_214___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__BQ_GAIN_EVEN_214___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214__BQ_GAIN_EVEN_214___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_214___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215 (0x005FD35C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__XLNA_GAIN_ODD_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__LNA_GAIN_ODD_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__GM_GAIN_ODD_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__TIA_GAIN_ODD_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__SLM_XLNA_ODD_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__BQ_GAIN_ODD_215___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__XLNA_GAIN_EVEN_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__LNA_GAIN_EVEN_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__GM_GAIN_EVEN_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__TIA_GAIN_EVEN_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__SLM_XLNA_EVEN_215___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__BQ_GAIN_EVEN_215___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__XLNA_GAIN_ODD_215___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__XLNA_GAIN_ODD_215___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__LNA_GAIN_ODD_215___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__LNA_GAIN_ODD_215___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__GM_GAIN_ODD_215___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__GM_GAIN_ODD_215___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__TIA_GAIN_ODD_215___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__TIA_GAIN_ODD_215___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__SLM_XLNA_ODD_215___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__SLM_XLNA_ODD_215___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__BQ_GAIN_ODD_215___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__BQ_GAIN_ODD_215___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__XLNA_GAIN_EVEN_215___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__XLNA_GAIN_EVEN_215___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__LNA_GAIN_EVEN_215___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__LNA_GAIN_EVEN_215___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__GM_GAIN_EVEN_215___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__GM_GAIN_EVEN_215___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__TIA_GAIN_EVEN_215___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__TIA_GAIN_EVEN_215___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__SLM_XLNA_EVEN_215___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__SLM_XLNA_EVEN_215___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__BQ_GAIN_EVEN_215___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215__BQ_GAIN_EVEN_215___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_215___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216 (0x005FD360) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__XLNA_GAIN_ODD_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__LNA_GAIN_ODD_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__GM_GAIN_ODD_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__TIA_GAIN_ODD_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__SLM_XLNA_ODD_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__BQ_GAIN_ODD_216___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__XLNA_GAIN_EVEN_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__LNA_GAIN_EVEN_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__GM_GAIN_EVEN_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__TIA_GAIN_EVEN_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__SLM_XLNA_EVEN_216___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__BQ_GAIN_EVEN_216___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__XLNA_GAIN_ODD_216___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__XLNA_GAIN_ODD_216___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__LNA_GAIN_ODD_216___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__LNA_GAIN_ODD_216___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__GM_GAIN_ODD_216___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__GM_GAIN_ODD_216___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__TIA_GAIN_ODD_216___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__TIA_GAIN_ODD_216___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__SLM_XLNA_ODD_216___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__SLM_XLNA_ODD_216___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__BQ_GAIN_ODD_216___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__BQ_GAIN_ODD_216___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__XLNA_GAIN_EVEN_216___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__XLNA_GAIN_EVEN_216___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__LNA_GAIN_EVEN_216___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__LNA_GAIN_EVEN_216___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__GM_GAIN_EVEN_216___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__GM_GAIN_EVEN_216___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__TIA_GAIN_EVEN_216___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__TIA_GAIN_EVEN_216___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__SLM_XLNA_EVEN_216___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__SLM_XLNA_EVEN_216___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__BQ_GAIN_EVEN_216___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216__BQ_GAIN_EVEN_216___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_216___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217 (0x005FD364) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__XLNA_GAIN_ODD_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__LNA_GAIN_ODD_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__GM_GAIN_ODD_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__TIA_GAIN_ODD_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__SLM_XLNA_ODD_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__BQ_GAIN_ODD_217___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__XLNA_GAIN_EVEN_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__LNA_GAIN_EVEN_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__GM_GAIN_EVEN_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__TIA_GAIN_EVEN_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__SLM_XLNA_EVEN_217___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__BQ_GAIN_EVEN_217___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__XLNA_GAIN_ODD_217___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__XLNA_GAIN_ODD_217___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__LNA_GAIN_ODD_217___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__LNA_GAIN_ODD_217___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__GM_GAIN_ODD_217___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__GM_GAIN_ODD_217___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__TIA_GAIN_ODD_217___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__TIA_GAIN_ODD_217___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__SLM_XLNA_ODD_217___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__SLM_XLNA_ODD_217___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__BQ_GAIN_ODD_217___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__BQ_GAIN_ODD_217___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__XLNA_GAIN_EVEN_217___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__XLNA_GAIN_EVEN_217___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__LNA_GAIN_EVEN_217___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__LNA_GAIN_EVEN_217___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__GM_GAIN_EVEN_217___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__GM_GAIN_EVEN_217___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__TIA_GAIN_EVEN_217___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__TIA_GAIN_EVEN_217___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__SLM_XLNA_EVEN_217___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__SLM_XLNA_EVEN_217___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__BQ_GAIN_EVEN_217___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217__BQ_GAIN_EVEN_217___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_217___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218 (0x005FD368) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__XLNA_GAIN_ODD_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__LNA_GAIN_ODD_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__GM_GAIN_ODD_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__TIA_GAIN_ODD_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__SLM_XLNA_ODD_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__BQ_GAIN_ODD_218___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__XLNA_GAIN_EVEN_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__LNA_GAIN_EVEN_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__GM_GAIN_EVEN_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__TIA_GAIN_EVEN_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__SLM_XLNA_EVEN_218___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__BQ_GAIN_EVEN_218___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__XLNA_GAIN_ODD_218___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__XLNA_GAIN_ODD_218___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__LNA_GAIN_ODD_218___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__LNA_GAIN_ODD_218___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__GM_GAIN_ODD_218___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__GM_GAIN_ODD_218___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__TIA_GAIN_ODD_218___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__TIA_GAIN_ODD_218___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__SLM_XLNA_ODD_218___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__SLM_XLNA_ODD_218___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__BQ_GAIN_ODD_218___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__BQ_GAIN_ODD_218___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__XLNA_GAIN_EVEN_218___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__XLNA_GAIN_EVEN_218___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__LNA_GAIN_EVEN_218___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__LNA_GAIN_EVEN_218___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__GM_GAIN_EVEN_218___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__GM_GAIN_EVEN_218___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__TIA_GAIN_EVEN_218___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__TIA_GAIN_EVEN_218___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__SLM_XLNA_EVEN_218___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__SLM_XLNA_EVEN_218___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__BQ_GAIN_EVEN_218___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218__BQ_GAIN_EVEN_218___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_218___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219 (0x005FD36C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__XLNA_GAIN_ODD_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__LNA_GAIN_ODD_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__GM_GAIN_ODD_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__TIA_GAIN_ODD_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__SLM_XLNA_ODD_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__BQ_GAIN_ODD_219___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__XLNA_GAIN_EVEN_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__LNA_GAIN_EVEN_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__GM_GAIN_EVEN_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__TIA_GAIN_EVEN_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__SLM_XLNA_EVEN_219___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__BQ_GAIN_EVEN_219___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__XLNA_GAIN_ODD_219___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__XLNA_GAIN_ODD_219___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__LNA_GAIN_ODD_219___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__LNA_GAIN_ODD_219___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__GM_GAIN_ODD_219___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__GM_GAIN_ODD_219___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__TIA_GAIN_ODD_219___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__TIA_GAIN_ODD_219___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__SLM_XLNA_ODD_219___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__SLM_XLNA_ODD_219___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__BQ_GAIN_ODD_219___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__BQ_GAIN_ODD_219___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__XLNA_GAIN_EVEN_219___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__XLNA_GAIN_EVEN_219___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__LNA_GAIN_EVEN_219___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__LNA_GAIN_EVEN_219___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__GM_GAIN_EVEN_219___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__GM_GAIN_EVEN_219___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__TIA_GAIN_EVEN_219___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__TIA_GAIN_EVEN_219___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__SLM_XLNA_EVEN_219___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__SLM_XLNA_EVEN_219___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__BQ_GAIN_EVEN_219___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219__BQ_GAIN_EVEN_219___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_219___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220 (0x005FD370) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__XLNA_GAIN_ODD_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__LNA_GAIN_ODD_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__GM_GAIN_ODD_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__TIA_GAIN_ODD_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__SLM_XLNA_ODD_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__BQ_GAIN_ODD_220___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__XLNA_GAIN_EVEN_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__LNA_GAIN_EVEN_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__GM_GAIN_EVEN_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__TIA_GAIN_EVEN_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__SLM_XLNA_EVEN_220___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__BQ_GAIN_EVEN_220___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__XLNA_GAIN_ODD_220___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__XLNA_GAIN_ODD_220___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__LNA_GAIN_ODD_220___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__LNA_GAIN_ODD_220___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__GM_GAIN_ODD_220___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__GM_GAIN_ODD_220___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__TIA_GAIN_ODD_220___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__TIA_GAIN_ODD_220___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__SLM_XLNA_ODD_220___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__SLM_XLNA_ODD_220___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__BQ_GAIN_ODD_220___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__BQ_GAIN_ODD_220___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__XLNA_GAIN_EVEN_220___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__XLNA_GAIN_EVEN_220___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__LNA_GAIN_EVEN_220___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__LNA_GAIN_EVEN_220___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__GM_GAIN_EVEN_220___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__GM_GAIN_EVEN_220___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__TIA_GAIN_EVEN_220___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__TIA_GAIN_EVEN_220___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__SLM_XLNA_EVEN_220___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__SLM_XLNA_EVEN_220___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__BQ_GAIN_EVEN_220___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220__BQ_GAIN_EVEN_220___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_220___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221 (0x005FD374) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__XLNA_GAIN_ODD_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__LNA_GAIN_ODD_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__GM_GAIN_ODD_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__TIA_GAIN_ODD_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__SLM_XLNA_ODD_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__BQ_GAIN_ODD_221___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__XLNA_GAIN_EVEN_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__LNA_GAIN_EVEN_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__GM_GAIN_EVEN_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__TIA_GAIN_EVEN_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__SLM_XLNA_EVEN_221___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__BQ_GAIN_EVEN_221___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__XLNA_GAIN_ODD_221___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__XLNA_GAIN_ODD_221___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__LNA_GAIN_ODD_221___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__LNA_GAIN_ODD_221___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__GM_GAIN_ODD_221___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__GM_GAIN_ODD_221___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__TIA_GAIN_ODD_221___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__TIA_GAIN_ODD_221___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__SLM_XLNA_ODD_221___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__SLM_XLNA_ODD_221___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__BQ_GAIN_ODD_221___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__BQ_GAIN_ODD_221___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__XLNA_GAIN_EVEN_221___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__XLNA_GAIN_EVEN_221___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__LNA_GAIN_EVEN_221___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__LNA_GAIN_EVEN_221___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__GM_GAIN_EVEN_221___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__GM_GAIN_EVEN_221___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__TIA_GAIN_EVEN_221___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__TIA_GAIN_EVEN_221___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__SLM_XLNA_EVEN_221___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__SLM_XLNA_EVEN_221___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__BQ_GAIN_EVEN_221___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221__BQ_GAIN_EVEN_221___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_221___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222 (0x005FD378) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__XLNA_GAIN_ODD_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__LNA_GAIN_ODD_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__GM_GAIN_ODD_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__TIA_GAIN_ODD_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__SLM_XLNA_ODD_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__BQ_GAIN_ODD_222___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__XLNA_GAIN_EVEN_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__LNA_GAIN_EVEN_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__GM_GAIN_EVEN_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__TIA_GAIN_EVEN_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__SLM_XLNA_EVEN_222___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__BQ_GAIN_EVEN_222___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__XLNA_GAIN_ODD_222___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__XLNA_GAIN_ODD_222___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__LNA_GAIN_ODD_222___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__LNA_GAIN_ODD_222___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__GM_GAIN_ODD_222___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__GM_GAIN_ODD_222___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__TIA_GAIN_ODD_222___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__TIA_GAIN_ODD_222___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__SLM_XLNA_ODD_222___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__SLM_XLNA_ODD_222___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__BQ_GAIN_ODD_222___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__BQ_GAIN_ODD_222___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__XLNA_GAIN_EVEN_222___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__XLNA_GAIN_EVEN_222___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__LNA_GAIN_EVEN_222___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__LNA_GAIN_EVEN_222___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__GM_GAIN_EVEN_222___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__GM_GAIN_EVEN_222___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__TIA_GAIN_EVEN_222___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__TIA_GAIN_EVEN_222___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__SLM_XLNA_EVEN_222___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__SLM_XLNA_EVEN_222___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__BQ_GAIN_EVEN_222___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222__BQ_GAIN_EVEN_222___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_222___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223 (0x005FD37C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__XLNA_GAIN_ODD_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__LNA_GAIN_ODD_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__GM_GAIN_ODD_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__TIA_GAIN_ODD_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__SLM_XLNA_ODD_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__BQ_GAIN_ODD_223___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__XLNA_GAIN_EVEN_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__LNA_GAIN_EVEN_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__GM_GAIN_EVEN_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__TIA_GAIN_EVEN_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__SLM_XLNA_EVEN_223___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__BQ_GAIN_EVEN_223___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__XLNA_GAIN_ODD_223___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__XLNA_GAIN_ODD_223___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__LNA_GAIN_ODD_223___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__LNA_GAIN_ODD_223___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__GM_GAIN_ODD_223___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__GM_GAIN_ODD_223___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__TIA_GAIN_ODD_223___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__TIA_GAIN_ODD_223___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__SLM_XLNA_ODD_223___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__SLM_XLNA_ODD_223___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__BQ_GAIN_ODD_223___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__BQ_GAIN_ODD_223___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__XLNA_GAIN_EVEN_223___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__XLNA_GAIN_EVEN_223___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__LNA_GAIN_EVEN_223___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__LNA_GAIN_EVEN_223___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__GM_GAIN_EVEN_223___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__GM_GAIN_EVEN_223___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__TIA_GAIN_EVEN_223___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__TIA_GAIN_EVEN_223___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__SLM_XLNA_EVEN_223___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__SLM_XLNA_EVEN_223___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__BQ_GAIN_EVEN_223___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223__BQ_GAIN_EVEN_223___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_223___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224 (0x005FD380) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__XLNA_GAIN_ODD_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__LNA_GAIN_ODD_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__GM_GAIN_ODD_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__TIA_GAIN_ODD_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__SLM_XLNA_ODD_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__BQ_GAIN_ODD_224___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__XLNA_GAIN_EVEN_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__LNA_GAIN_EVEN_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__GM_GAIN_EVEN_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__TIA_GAIN_EVEN_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__SLM_XLNA_EVEN_224___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__BQ_GAIN_EVEN_224___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__XLNA_GAIN_ODD_224___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__XLNA_GAIN_ODD_224___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__LNA_GAIN_ODD_224___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__LNA_GAIN_ODD_224___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__GM_GAIN_ODD_224___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__GM_GAIN_ODD_224___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__TIA_GAIN_ODD_224___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__TIA_GAIN_ODD_224___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__SLM_XLNA_ODD_224___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__SLM_XLNA_ODD_224___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__BQ_GAIN_ODD_224___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__BQ_GAIN_ODD_224___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__XLNA_GAIN_EVEN_224___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__XLNA_GAIN_EVEN_224___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__LNA_GAIN_EVEN_224___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__LNA_GAIN_EVEN_224___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__GM_GAIN_EVEN_224___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__GM_GAIN_EVEN_224___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__TIA_GAIN_EVEN_224___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__TIA_GAIN_EVEN_224___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__SLM_XLNA_EVEN_224___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__SLM_XLNA_EVEN_224___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__BQ_GAIN_EVEN_224___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224__BQ_GAIN_EVEN_224___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_224___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225 (0x005FD384) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__XLNA_GAIN_ODD_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__LNA_GAIN_ODD_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__GM_GAIN_ODD_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__TIA_GAIN_ODD_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__SLM_XLNA_ODD_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__BQ_GAIN_ODD_225___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__XLNA_GAIN_EVEN_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__LNA_GAIN_EVEN_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__GM_GAIN_EVEN_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__TIA_GAIN_EVEN_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__SLM_XLNA_EVEN_225___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__BQ_GAIN_EVEN_225___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__XLNA_GAIN_ODD_225___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__XLNA_GAIN_ODD_225___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__LNA_GAIN_ODD_225___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__LNA_GAIN_ODD_225___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__GM_GAIN_ODD_225___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__GM_GAIN_ODD_225___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__TIA_GAIN_ODD_225___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__TIA_GAIN_ODD_225___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__SLM_XLNA_ODD_225___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__SLM_XLNA_ODD_225___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__BQ_GAIN_ODD_225___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__BQ_GAIN_ODD_225___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__XLNA_GAIN_EVEN_225___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__XLNA_GAIN_EVEN_225___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__LNA_GAIN_EVEN_225___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__LNA_GAIN_EVEN_225___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__GM_GAIN_EVEN_225___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__GM_GAIN_EVEN_225___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__TIA_GAIN_EVEN_225___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__TIA_GAIN_EVEN_225___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__SLM_XLNA_EVEN_225___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__SLM_XLNA_EVEN_225___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__BQ_GAIN_EVEN_225___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225__BQ_GAIN_EVEN_225___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_225___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226 (0x005FD388) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__XLNA_GAIN_ODD_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__LNA_GAIN_ODD_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__GM_GAIN_ODD_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__TIA_GAIN_ODD_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__SLM_XLNA_ODD_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__BQ_GAIN_ODD_226___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__XLNA_GAIN_EVEN_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__LNA_GAIN_EVEN_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__GM_GAIN_EVEN_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__TIA_GAIN_EVEN_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__SLM_XLNA_EVEN_226___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__BQ_GAIN_EVEN_226___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__XLNA_GAIN_ODD_226___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__XLNA_GAIN_ODD_226___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__LNA_GAIN_ODD_226___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__LNA_GAIN_ODD_226___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__GM_GAIN_ODD_226___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__GM_GAIN_ODD_226___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__TIA_GAIN_ODD_226___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__TIA_GAIN_ODD_226___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__SLM_XLNA_ODD_226___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__SLM_XLNA_ODD_226___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__BQ_GAIN_ODD_226___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__BQ_GAIN_ODD_226___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__XLNA_GAIN_EVEN_226___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__XLNA_GAIN_EVEN_226___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__LNA_GAIN_EVEN_226___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__LNA_GAIN_EVEN_226___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__GM_GAIN_EVEN_226___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__GM_GAIN_EVEN_226___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__TIA_GAIN_EVEN_226___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__TIA_GAIN_EVEN_226___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__SLM_XLNA_EVEN_226___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__SLM_XLNA_EVEN_226___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__BQ_GAIN_EVEN_226___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226__BQ_GAIN_EVEN_226___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_226___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227 (0x005FD38C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__XLNA_GAIN_ODD_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__LNA_GAIN_ODD_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__GM_GAIN_ODD_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__TIA_GAIN_ODD_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__SLM_XLNA_ODD_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__BQ_GAIN_ODD_227___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__XLNA_GAIN_EVEN_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__LNA_GAIN_EVEN_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__GM_GAIN_EVEN_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__TIA_GAIN_EVEN_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__SLM_XLNA_EVEN_227___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__BQ_GAIN_EVEN_227___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__XLNA_GAIN_ODD_227___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__XLNA_GAIN_ODD_227___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__LNA_GAIN_ODD_227___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__LNA_GAIN_ODD_227___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__GM_GAIN_ODD_227___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__GM_GAIN_ODD_227___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__TIA_GAIN_ODD_227___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__TIA_GAIN_ODD_227___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__SLM_XLNA_ODD_227___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__SLM_XLNA_ODD_227___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__BQ_GAIN_ODD_227___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__BQ_GAIN_ODD_227___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__XLNA_GAIN_EVEN_227___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__XLNA_GAIN_EVEN_227___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__LNA_GAIN_EVEN_227___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__LNA_GAIN_EVEN_227___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__GM_GAIN_EVEN_227___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__GM_GAIN_EVEN_227___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__TIA_GAIN_EVEN_227___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__TIA_GAIN_EVEN_227___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__SLM_XLNA_EVEN_227___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__SLM_XLNA_EVEN_227___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__BQ_GAIN_EVEN_227___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227__BQ_GAIN_EVEN_227___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_227___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228 (0x005FD390) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__XLNA_GAIN_ODD_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__LNA_GAIN_ODD_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__GM_GAIN_ODD_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__TIA_GAIN_ODD_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__SLM_XLNA_ODD_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__BQ_GAIN_ODD_228___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__XLNA_GAIN_EVEN_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__LNA_GAIN_EVEN_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__GM_GAIN_EVEN_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__TIA_GAIN_EVEN_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__SLM_XLNA_EVEN_228___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__BQ_GAIN_EVEN_228___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__XLNA_GAIN_ODD_228___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__XLNA_GAIN_ODD_228___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__LNA_GAIN_ODD_228___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__LNA_GAIN_ODD_228___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__GM_GAIN_ODD_228___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__GM_GAIN_ODD_228___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__TIA_GAIN_ODD_228___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__TIA_GAIN_ODD_228___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__SLM_XLNA_ODD_228___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__SLM_XLNA_ODD_228___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__BQ_GAIN_ODD_228___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__BQ_GAIN_ODD_228___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__XLNA_GAIN_EVEN_228___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__XLNA_GAIN_EVEN_228___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__LNA_GAIN_EVEN_228___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__LNA_GAIN_EVEN_228___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__GM_GAIN_EVEN_228___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__GM_GAIN_EVEN_228___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__TIA_GAIN_EVEN_228___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__TIA_GAIN_EVEN_228___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__SLM_XLNA_EVEN_228___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__SLM_XLNA_EVEN_228___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__BQ_GAIN_EVEN_228___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228__BQ_GAIN_EVEN_228___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_228___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229 (0x005FD394) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__XLNA_GAIN_ODD_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__LNA_GAIN_ODD_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__GM_GAIN_ODD_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__TIA_GAIN_ODD_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__SLM_XLNA_ODD_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__BQ_GAIN_ODD_229___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__XLNA_GAIN_EVEN_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__LNA_GAIN_EVEN_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__GM_GAIN_EVEN_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__TIA_GAIN_EVEN_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__SLM_XLNA_EVEN_229___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__BQ_GAIN_EVEN_229___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__XLNA_GAIN_ODD_229___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__XLNA_GAIN_ODD_229___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__LNA_GAIN_ODD_229___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__LNA_GAIN_ODD_229___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__GM_GAIN_ODD_229___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__GM_GAIN_ODD_229___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__TIA_GAIN_ODD_229___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__TIA_GAIN_ODD_229___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__SLM_XLNA_ODD_229___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__SLM_XLNA_ODD_229___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__BQ_GAIN_ODD_229___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__BQ_GAIN_ODD_229___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__XLNA_GAIN_EVEN_229___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__XLNA_GAIN_EVEN_229___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__LNA_GAIN_EVEN_229___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__LNA_GAIN_EVEN_229___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__GM_GAIN_EVEN_229___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__GM_GAIN_EVEN_229___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__TIA_GAIN_EVEN_229___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__TIA_GAIN_EVEN_229___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__SLM_XLNA_EVEN_229___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__SLM_XLNA_EVEN_229___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__BQ_GAIN_EVEN_229___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229__BQ_GAIN_EVEN_229___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_229___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230 (0x005FD398) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__XLNA_GAIN_ODD_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__LNA_GAIN_ODD_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__GM_GAIN_ODD_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__TIA_GAIN_ODD_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__SLM_XLNA_ODD_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__BQ_GAIN_ODD_230___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__XLNA_GAIN_EVEN_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__LNA_GAIN_EVEN_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__GM_GAIN_EVEN_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__TIA_GAIN_EVEN_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__SLM_XLNA_EVEN_230___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__BQ_GAIN_EVEN_230___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__XLNA_GAIN_ODD_230___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__XLNA_GAIN_ODD_230___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__LNA_GAIN_ODD_230___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__LNA_GAIN_ODD_230___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__GM_GAIN_ODD_230___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__GM_GAIN_ODD_230___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__TIA_GAIN_ODD_230___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__TIA_GAIN_ODD_230___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__SLM_XLNA_ODD_230___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__SLM_XLNA_ODD_230___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__BQ_GAIN_ODD_230___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__BQ_GAIN_ODD_230___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__XLNA_GAIN_EVEN_230___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__XLNA_GAIN_EVEN_230___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__LNA_GAIN_EVEN_230___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__LNA_GAIN_EVEN_230___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__GM_GAIN_EVEN_230___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__GM_GAIN_EVEN_230___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__TIA_GAIN_EVEN_230___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__TIA_GAIN_EVEN_230___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__SLM_XLNA_EVEN_230___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__SLM_XLNA_EVEN_230___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__BQ_GAIN_EVEN_230___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230__BQ_GAIN_EVEN_230___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_230___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231 (0x005FD39C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__XLNA_GAIN_ODD_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__LNA_GAIN_ODD_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__GM_GAIN_ODD_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__TIA_GAIN_ODD_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__SLM_XLNA_ODD_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__BQ_GAIN_ODD_231___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__XLNA_GAIN_EVEN_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__LNA_GAIN_EVEN_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__GM_GAIN_EVEN_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__TIA_GAIN_EVEN_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__SLM_XLNA_EVEN_231___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__BQ_GAIN_EVEN_231___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__XLNA_GAIN_ODD_231___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__XLNA_GAIN_ODD_231___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__LNA_GAIN_ODD_231___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__LNA_GAIN_ODD_231___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__GM_GAIN_ODD_231___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__GM_GAIN_ODD_231___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__TIA_GAIN_ODD_231___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__TIA_GAIN_ODD_231___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__SLM_XLNA_ODD_231___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__SLM_XLNA_ODD_231___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__BQ_GAIN_ODD_231___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__BQ_GAIN_ODD_231___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__XLNA_GAIN_EVEN_231___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__XLNA_GAIN_EVEN_231___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__LNA_GAIN_EVEN_231___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__LNA_GAIN_EVEN_231___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__GM_GAIN_EVEN_231___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__GM_GAIN_EVEN_231___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__TIA_GAIN_EVEN_231___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__TIA_GAIN_EVEN_231___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__SLM_XLNA_EVEN_231___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__SLM_XLNA_EVEN_231___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__BQ_GAIN_EVEN_231___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231__BQ_GAIN_EVEN_231___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_231___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232 (0x005FD3A0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__XLNA_GAIN_ODD_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__LNA_GAIN_ODD_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__GM_GAIN_ODD_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__TIA_GAIN_ODD_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__SLM_XLNA_ODD_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__BQ_GAIN_ODD_232___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__XLNA_GAIN_EVEN_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__LNA_GAIN_EVEN_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__GM_GAIN_EVEN_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__TIA_GAIN_EVEN_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__SLM_XLNA_EVEN_232___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__BQ_GAIN_EVEN_232___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__XLNA_GAIN_ODD_232___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__XLNA_GAIN_ODD_232___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__LNA_GAIN_ODD_232___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__LNA_GAIN_ODD_232___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__GM_GAIN_ODD_232___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__GM_GAIN_ODD_232___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__TIA_GAIN_ODD_232___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__TIA_GAIN_ODD_232___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__SLM_XLNA_ODD_232___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__SLM_XLNA_ODD_232___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__BQ_GAIN_ODD_232___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__BQ_GAIN_ODD_232___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__XLNA_GAIN_EVEN_232___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__XLNA_GAIN_EVEN_232___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__LNA_GAIN_EVEN_232___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__LNA_GAIN_EVEN_232___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__GM_GAIN_EVEN_232___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__GM_GAIN_EVEN_232___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__TIA_GAIN_EVEN_232___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__TIA_GAIN_EVEN_232___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__SLM_XLNA_EVEN_232___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__SLM_XLNA_EVEN_232___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__BQ_GAIN_EVEN_232___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232__BQ_GAIN_EVEN_232___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_232___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233 (0x005FD3A4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__XLNA_GAIN_ODD_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__LNA_GAIN_ODD_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__GM_GAIN_ODD_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__TIA_GAIN_ODD_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__SLM_XLNA_ODD_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__BQ_GAIN_ODD_233___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__XLNA_GAIN_EVEN_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__LNA_GAIN_EVEN_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__GM_GAIN_EVEN_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__TIA_GAIN_EVEN_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__SLM_XLNA_EVEN_233___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__BQ_GAIN_EVEN_233___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__XLNA_GAIN_ODD_233___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__XLNA_GAIN_ODD_233___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__LNA_GAIN_ODD_233___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__LNA_GAIN_ODD_233___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__GM_GAIN_ODD_233___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__GM_GAIN_ODD_233___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__TIA_GAIN_ODD_233___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__TIA_GAIN_ODD_233___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__SLM_XLNA_ODD_233___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__SLM_XLNA_ODD_233___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__BQ_GAIN_ODD_233___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__BQ_GAIN_ODD_233___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__XLNA_GAIN_EVEN_233___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__XLNA_GAIN_EVEN_233___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__LNA_GAIN_EVEN_233___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__LNA_GAIN_EVEN_233___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__GM_GAIN_EVEN_233___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__GM_GAIN_EVEN_233___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__TIA_GAIN_EVEN_233___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__TIA_GAIN_EVEN_233___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__SLM_XLNA_EVEN_233___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__SLM_XLNA_EVEN_233___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__BQ_GAIN_EVEN_233___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233__BQ_GAIN_EVEN_233___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_233___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234 (0x005FD3A8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__XLNA_GAIN_ODD_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__LNA_GAIN_ODD_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__GM_GAIN_ODD_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__TIA_GAIN_ODD_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__SLM_XLNA_ODD_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__BQ_GAIN_ODD_234___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__XLNA_GAIN_EVEN_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__LNA_GAIN_EVEN_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__GM_GAIN_EVEN_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__TIA_GAIN_EVEN_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__SLM_XLNA_EVEN_234___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__BQ_GAIN_EVEN_234___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__XLNA_GAIN_ODD_234___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__XLNA_GAIN_ODD_234___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__LNA_GAIN_ODD_234___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__LNA_GAIN_ODD_234___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__GM_GAIN_ODD_234___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__GM_GAIN_ODD_234___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__TIA_GAIN_ODD_234___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__TIA_GAIN_ODD_234___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__SLM_XLNA_ODD_234___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__SLM_XLNA_ODD_234___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__BQ_GAIN_ODD_234___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__BQ_GAIN_ODD_234___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__XLNA_GAIN_EVEN_234___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__XLNA_GAIN_EVEN_234___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__LNA_GAIN_EVEN_234___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__LNA_GAIN_EVEN_234___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__GM_GAIN_EVEN_234___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__GM_GAIN_EVEN_234___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__TIA_GAIN_EVEN_234___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__TIA_GAIN_EVEN_234___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__SLM_XLNA_EVEN_234___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__SLM_XLNA_EVEN_234___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__BQ_GAIN_EVEN_234___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234__BQ_GAIN_EVEN_234___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_234___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235 (0x005FD3AC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__XLNA_GAIN_ODD_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__LNA_GAIN_ODD_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__GM_GAIN_ODD_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__TIA_GAIN_ODD_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__SLM_XLNA_ODD_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__BQ_GAIN_ODD_235___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__XLNA_GAIN_EVEN_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__LNA_GAIN_EVEN_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__GM_GAIN_EVEN_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__TIA_GAIN_EVEN_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__SLM_XLNA_EVEN_235___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__BQ_GAIN_EVEN_235___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__XLNA_GAIN_ODD_235___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__XLNA_GAIN_ODD_235___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__LNA_GAIN_ODD_235___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__LNA_GAIN_ODD_235___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__GM_GAIN_ODD_235___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__GM_GAIN_ODD_235___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__TIA_GAIN_ODD_235___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__TIA_GAIN_ODD_235___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__SLM_XLNA_ODD_235___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__SLM_XLNA_ODD_235___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__BQ_GAIN_ODD_235___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__BQ_GAIN_ODD_235___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__XLNA_GAIN_EVEN_235___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__XLNA_GAIN_EVEN_235___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__LNA_GAIN_EVEN_235___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__LNA_GAIN_EVEN_235___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__GM_GAIN_EVEN_235___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__GM_GAIN_EVEN_235___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__TIA_GAIN_EVEN_235___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__TIA_GAIN_EVEN_235___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__SLM_XLNA_EVEN_235___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__SLM_XLNA_EVEN_235___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__BQ_GAIN_EVEN_235___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235__BQ_GAIN_EVEN_235___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_235___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236 (0x005FD3B0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__XLNA_GAIN_ODD_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__LNA_GAIN_ODD_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__GM_GAIN_ODD_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__TIA_GAIN_ODD_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__SLM_XLNA_ODD_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__BQ_GAIN_ODD_236___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__XLNA_GAIN_EVEN_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__LNA_GAIN_EVEN_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__GM_GAIN_EVEN_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__TIA_GAIN_EVEN_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__SLM_XLNA_EVEN_236___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__BQ_GAIN_EVEN_236___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__XLNA_GAIN_ODD_236___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__XLNA_GAIN_ODD_236___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__LNA_GAIN_ODD_236___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__LNA_GAIN_ODD_236___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__GM_GAIN_ODD_236___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__GM_GAIN_ODD_236___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__TIA_GAIN_ODD_236___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__TIA_GAIN_ODD_236___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__SLM_XLNA_ODD_236___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__SLM_XLNA_ODD_236___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__BQ_GAIN_ODD_236___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__BQ_GAIN_ODD_236___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__XLNA_GAIN_EVEN_236___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__XLNA_GAIN_EVEN_236___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__LNA_GAIN_EVEN_236___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__LNA_GAIN_EVEN_236___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__GM_GAIN_EVEN_236___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__GM_GAIN_EVEN_236___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__TIA_GAIN_EVEN_236___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__TIA_GAIN_EVEN_236___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__SLM_XLNA_EVEN_236___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__SLM_XLNA_EVEN_236___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__BQ_GAIN_EVEN_236___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236__BQ_GAIN_EVEN_236___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_236___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237 (0x005FD3B4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__XLNA_GAIN_ODD_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__LNA_GAIN_ODD_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__GM_GAIN_ODD_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__TIA_GAIN_ODD_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__SLM_XLNA_ODD_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__BQ_GAIN_ODD_237___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__XLNA_GAIN_EVEN_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__LNA_GAIN_EVEN_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__GM_GAIN_EVEN_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__TIA_GAIN_EVEN_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__SLM_XLNA_EVEN_237___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__BQ_GAIN_EVEN_237___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__XLNA_GAIN_ODD_237___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__XLNA_GAIN_ODD_237___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__LNA_GAIN_ODD_237___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__LNA_GAIN_ODD_237___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__GM_GAIN_ODD_237___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__GM_GAIN_ODD_237___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__TIA_GAIN_ODD_237___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__TIA_GAIN_ODD_237___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__SLM_XLNA_ODD_237___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__SLM_XLNA_ODD_237___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__BQ_GAIN_ODD_237___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__BQ_GAIN_ODD_237___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__XLNA_GAIN_EVEN_237___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__XLNA_GAIN_EVEN_237___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__LNA_GAIN_EVEN_237___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__LNA_GAIN_EVEN_237___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__GM_GAIN_EVEN_237___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__GM_GAIN_EVEN_237___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__TIA_GAIN_EVEN_237___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__TIA_GAIN_EVEN_237___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__SLM_XLNA_EVEN_237___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__SLM_XLNA_EVEN_237___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__BQ_GAIN_EVEN_237___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237__BQ_GAIN_EVEN_237___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_237___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238 (0x005FD3B8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__XLNA_GAIN_ODD_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__LNA_GAIN_ODD_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__GM_GAIN_ODD_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__TIA_GAIN_ODD_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__SLM_XLNA_ODD_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__BQ_GAIN_ODD_238___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__XLNA_GAIN_EVEN_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__LNA_GAIN_EVEN_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__GM_GAIN_EVEN_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__TIA_GAIN_EVEN_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__SLM_XLNA_EVEN_238___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__BQ_GAIN_EVEN_238___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__XLNA_GAIN_ODD_238___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__XLNA_GAIN_ODD_238___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__LNA_GAIN_ODD_238___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__LNA_GAIN_ODD_238___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__GM_GAIN_ODD_238___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__GM_GAIN_ODD_238___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__TIA_GAIN_ODD_238___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__TIA_GAIN_ODD_238___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__SLM_XLNA_ODD_238___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__SLM_XLNA_ODD_238___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__BQ_GAIN_ODD_238___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__BQ_GAIN_ODD_238___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__XLNA_GAIN_EVEN_238___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__XLNA_GAIN_EVEN_238___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__LNA_GAIN_EVEN_238___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__LNA_GAIN_EVEN_238___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__GM_GAIN_EVEN_238___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__GM_GAIN_EVEN_238___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__TIA_GAIN_EVEN_238___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__TIA_GAIN_EVEN_238___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__SLM_XLNA_EVEN_238___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__SLM_XLNA_EVEN_238___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__BQ_GAIN_EVEN_238___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238__BQ_GAIN_EVEN_238___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_238___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239 (0x005FD3BC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__XLNA_GAIN_ODD_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__LNA_GAIN_ODD_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__GM_GAIN_ODD_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__TIA_GAIN_ODD_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__SLM_XLNA_ODD_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__BQ_GAIN_ODD_239___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__XLNA_GAIN_EVEN_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__LNA_GAIN_EVEN_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__GM_GAIN_EVEN_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__TIA_GAIN_EVEN_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__SLM_XLNA_EVEN_239___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__BQ_GAIN_EVEN_239___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__XLNA_GAIN_ODD_239___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__XLNA_GAIN_ODD_239___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__LNA_GAIN_ODD_239___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__LNA_GAIN_ODD_239___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__GM_GAIN_ODD_239___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__GM_GAIN_ODD_239___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__TIA_GAIN_ODD_239___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__TIA_GAIN_ODD_239___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__SLM_XLNA_ODD_239___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__SLM_XLNA_ODD_239___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__BQ_GAIN_ODD_239___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__BQ_GAIN_ODD_239___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__XLNA_GAIN_EVEN_239___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__XLNA_GAIN_EVEN_239___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__LNA_GAIN_EVEN_239___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__LNA_GAIN_EVEN_239___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__GM_GAIN_EVEN_239___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__GM_GAIN_EVEN_239___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__TIA_GAIN_EVEN_239___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__TIA_GAIN_EVEN_239___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__SLM_XLNA_EVEN_239___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__SLM_XLNA_EVEN_239___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__BQ_GAIN_EVEN_239___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239__BQ_GAIN_EVEN_239___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_239___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240 (0x005FD3C0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__XLNA_GAIN_ODD_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__LNA_GAIN_ODD_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__GM_GAIN_ODD_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__TIA_GAIN_ODD_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__SLM_XLNA_ODD_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__BQ_GAIN_ODD_240___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__XLNA_GAIN_EVEN_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__LNA_GAIN_EVEN_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__GM_GAIN_EVEN_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__TIA_GAIN_EVEN_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__SLM_XLNA_EVEN_240___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__BQ_GAIN_EVEN_240___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__XLNA_GAIN_ODD_240___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__XLNA_GAIN_ODD_240___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__LNA_GAIN_ODD_240___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__LNA_GAIN_ODD_240___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__GM_GAIN_ODD_240___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__GM_GAIN_ODD_240___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__TIA_GAIN_ODD_240___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__TIA_GAIN_ODD_240___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__SLM_XLNA_ODD_240___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__SLM_XLNA_ODD_240___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__BQ_GAIN_ODD_240___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__BQ_GAIN_ODD_240___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__XLNA_GAIN_EVEN_240___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__XLNA_GAIN_EVEN_240___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__LNA_GAIN_EVEN_240___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__LNA_GAIN_EVEN_240___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__GM_GAIN_EVEN_240___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__GM_GAIN_EVEN_240___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__TIA_GAIN_EVEN_240___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__TIA_GAIN_EVEN_240___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__SLM_XLNA_EVEN_240___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__SLM_XLNA_EVEN_240___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__BQ_GAIN_EVEN_240___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240__BQ_GAIN_EVEN_240___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_240___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241 (0x005FD3C4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__XLNA_GAIN_ODD_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__LNA_GAIN_ODD_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__GM_GAIN_ODD_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__TIA_GAIN_ODD_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__SLM_XLNA_ODD_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__BQ_GAIN_ODD_241___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__XLNA_GAIN_EVEN_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__LNA_GAIN_EVEN_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__GM_GAIN_EVEN_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__TIA_GAIN_EVEN_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__SLM_XLNA_EVEN_241___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__BQ_GAIN_EVEN_241___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__XLNA_GAIN_ODD_241___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__XLNA_GAIN_ODD_241___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__LNA_GAIN_ODD_241___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__LNA_GAIN_ODD_241___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__GM_GAIN_ODD_241___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__GM_GAIN_ODD_241___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__TIA_GAIN_ODD_241___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__TIA_GAIN_ODD_241___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__SLM_XLNA_ODD_241___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__SLM_XLNA_ODD_241___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__BQ_GAIN_ODD_241___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__BQ_GAIN_ODD_241___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__XLNA_GAIN_EVEN_241___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__XLNA_GAIN_EVEN_241___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__LNA_GAIN_EVEN_241___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__LNA_GAIN_EVEN_241___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__GM_GAIN_EVEN_241___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__GM_GAIN_EVEN_241___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__TIA_GAIN_EVEN_241___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__TIA_GAIN_EVEN_241___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__SLM_XLNA_EVEN_241___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__SLM_XLNA_EVEN_241___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__BQ_GAIN_EVEN_241___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241__BQ_GAIN_EVEN_241___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_241___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242 (0x005FD3C8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__XLNA_GAIN_ODD_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__LNA_GAIN_ODD_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__GM_GAIN_ODD_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__TIA_GAIN_ODD_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__SLM_XLNA_ODD_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__BQ_GAIN_ODD_242___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__XLNA_GAIN_EVEN_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__LNA_GAIN_EVEN_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__GM_GAIN_EVEN_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__TIA_GAIN_EVEN_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__SLM_XLNA_EVEN_242___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__BQ_GAIN_EVEN_242___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__XLNA_GAIN_ODD_242___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__XLNA_GAIN_ODD_242___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__LNA_GAIN_ODD_242___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__LNA_GAIN_ODD_242___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__GM_GAIN_ODD_242___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__GM_GAIN_ODD_242___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__TIA_GAIN_ODD_242___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__TIA_GAIN_ODD_242___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__SLM_XLNA_ODD_242___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__SLM_XLNA_ODD_242___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__BQ_GAIN_ODD_242___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__BQ_GAIN_ODD_242___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__XLNA_GAIN_EVEN_242___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__XLNA_GAIN_EVEN_242___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__LNA_GAIN_EVEN_242___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__LNA_GAIN_EVEN_242___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__GM_GAIN_EVEN_242___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__GM_GAIN_EVEN_242___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__TIA_GAIN_EVEN_242___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__TIA_GAIN_EVEN_242___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__SLM_XLNA_EVEN_242___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__SLM_XLNA_EVEN_242___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__BQ_GAIN_EVEN_242___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242__BQ_GAIN_EVEN_242___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_242___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243 (0x005FD3CC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__XLNA_GAIN_ODD_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__LNA_GAIN_ODD_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__GM_GAIN_ODD_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__TIA_GAIN_ODD_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__SLM_XLNA_ODD_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__BQ_GAIN_ODD_243___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__XLNA_GAIN_EVEN_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__LNA_GAIN_EVEN_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__GM_GAIN_EVEN_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__TIA_GAIN_EVEN_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__SLM_XLNA_EVEN_243___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__BQ_GAIN_EVEN_243___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__XLNA_GAIN_ODD_243___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__XLNA_GAIN_ODD_243___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__LNA_GAIN_ODD_243___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__LNA_GAIN_ODD_243___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__GM_GAIN_ODD_243___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__GM_GAIN_ODD_243___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__TIA_GAIN_ODD_243___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__TIA_GAIN_ODD_243___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__SLM_XLNA_ODD_243___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__SLM_XLNA_ODD_243___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__BQ_GAIN_ODD_243___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__BQ_GAIN_ODD_243___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__XLNA_GAIN_EVEN_243___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__XLNA_GAIN_EVEN_243___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__LNA_GAIN_EVEN_243___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__LNA_GAIN_EVEN_243___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__GM_GAIN_EVEN_243___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__GM_GAIN_EVEN_243___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__TIA_GAIN_EVEN_243___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__TIA_GAIN_EVEN_243___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__SLM_XLNA_EVEN_243___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__SLM_XLNA_EVEN_243___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__BQ_GAIN_EVEN_243___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243__BQ_GAIN_EVEN_243___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_243___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244 (0x005FD3D0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__XLNA_GAIN_ODD_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__LNA_GAIN_ODD_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__GM_GAIN_ODD_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__TIA_GAIN_ODD_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__SLM_XLNA_ODD_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__BQ_GAIN_ODD_244___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__XLNA_GAIN_EVEN_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__LNA_GAIN_EVEN_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__GM_GAIN_EVEN_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__TIA_GAIN_EVEN_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__SLM_XLNA_EVEN_244___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__BQ_GAIN_EVEN_244___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__XLNA_GAIN_ODD_244___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__XLNA_GAIN_ODD_244___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__LNA_GAIN_ODD_244___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__LNA_GAIN_ODD_244___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__GM_GAIN_ODD_244___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__GM_GAIN_ODD_244___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__TIA_GAIN_ODD_244___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__TIA_GAIN_ODD_244___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__SLM_XLNA_ODD_244___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__SLM_XLNA_ODD_244___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__BQ_GAIN_ODD_244___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__BQ_GAIN_ODD_244___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__XLNA_GAIN_EVEN_244___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__XLNA_GAIN_EVEN_244___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__LNA_GAIN_EVEN_244___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__LNA_GAIN_EVEN_244___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__GM_GAIN_EVEN_244___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__GM_GAIN_EVEN_244___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__TIA_GAIN_EVEN_244___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__TIA_GAIN_EVEN_244___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__SLM_XLNA_EVEN_244___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__SLM_XLNA_EVEN_244___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__BQ_GAIN_EVEN_244___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244__BQ_GAIN_EVEN_244___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_244___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245 (0x005FD3D4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__XLNA_GAIN_ODD_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__LNA_GAIN_ODD_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__GM_GAIN_ODD_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__TIA_GAIN_ODD_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__SLM_XLNA_ODD_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__BQ_GAIN_ODD_245___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__XLNA_GAIN_EVEN_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__LNA_GAIN_EVEN_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__GM_GAIN_EVEN_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__TIA_GAIN_EVEN_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__SLM_XLNA_EVEN_245___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__BQ_GAIN_EVEN_245___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__XLNA_GAIN_ODD_245___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__XLNA_GAIN_ODD_245___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__LNA_GAIN_ODD_245___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__LNA_GAIN_ODD_245___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__GM_GAIN_ODD_245___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__GM_GAIN_ODD_245___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__TIA_GAIN_ODD_245___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__TIA_GAIN_ODD_245___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__SLM_XLNA_ODD_245___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__SLM_XLNA_ODD_245___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__BQ_GAIN_ODD_245___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__BQ_GAIN_ODD_245___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__XLNA_GAIN_EVEN_245___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__XLNA_GAIN_EVEN_245___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__LNA_GAIN_EVEN_245___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__LNA_GAIN_EVEN_245___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__GM_GAIN_EVEN_245___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__GM_GAIN_EVEN_245___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__TIA_GAIN_EVEN_245___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__TIA_GAIN_EVEN_245___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__SLM_XLNA_EVEN_245___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__SLM_XLNA_EVEN_245___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__BQ_GAIN_EVEN_245___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245__BQ_GAIN_EVEN_245___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_245___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246 (0x005FD3D8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__XLNA_GAIN_ODD_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__LNA_GAIN_ODD_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__GM_GAIN_ODD_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__TIA_GAIN_ODD_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__SLM_XLNA_ODD_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__BQ_GAIN_ODD_246___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__XLNA_GAIN_EVEN_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__LNA_GAIN_EVEN_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__GM_GAIN_EVEN_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__TIA_GAIN_EVEN_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__SLM_XLNA_EVEN_246___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__BQ_GAIN_EVEN_246___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__XLNA_GAIN_ODD_246___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__XLNA_GAIN_ODD_246___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__LNA_GAIN_ODD_246___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__LNA_GAIN_ODD_246___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__GM_GAIN_ODD_246___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__GM_GAIN_ODD_246___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__TIA_GAIN_ODD_246___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__TIA_GAIN_ODD_246___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__SLM_XLNA_ODD_246___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__SLM_XLNA_ODD_246___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__BQ_GAIN_ODD_246___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__BQ_GAIN_ODD_246___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__XLNA_GAIN_EVEN_246___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__XLNA_GAIN_EVEN_246___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__LNA_GAIN_EVEN_246___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__LNA_GAIN_EVEN_246___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__GM_GAIN_EVEN_246___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__GM_GAIN_EVEN_246___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__TIA_GAIN_EVEN_246___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__TIA_GAIN_EVEN_246___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__SLM_XLNA_EVEN_246___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__SLM_XLNA_EVEN_246___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__BQ_GAIN_EVEN_246___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246__BQ_GAIN_EVEN_246___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_246___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247 (0x005FD3DC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__XLNA_GAIN_ODD_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__LNA_GAIN_ODD_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__GM_GAIN_ODD_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__TIA_GAIN_ODD_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__SLM_XLNA_ODD_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__BQ_GAIN_ODD_247___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__XLNA_GAIN_EVEN_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__LNA_GAIN_EVEN_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__GM_GAIN_EVEN_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__TIA_GAIN_EVEN_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__SLM_XLNA_EVEN_247___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__BQ_GAIN_EVEN_247___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__XLNA_GAIN_ODD_247___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__XLNA_GAIN_ODD_247___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__LNA_GAIN_ODD_247___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__LNA_GAIN_ODD_247___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__GM_GAIN_ODD_247___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__GM_GAIN_ODD_247___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__TIA_GAIN_ODD_247___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__TIA_GAIN_ODD_247___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__SLM_XLNA_ODD_247___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__SLM_XLNA_ODD_247___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__BQ_GAIN_ODD_247___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__BQ_GAIN_ODD_247___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__XLNA_GAIN_EVEN_247___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__XLNA_GAIN_EVEN_247___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__LNA_GAIN_EVEN_247___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__LNA_GAIN_EVEN_247___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__GM_GAIN_EVEN_247___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__GM_GAIN_EVEN_247___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__TIA_GAIN_EVEN_247___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__TIA_GAIN_EVEN_247___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__SLM_XLNA_EVEN_247___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__SLM_XLNA_EVEN_247___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__BQ_GAIN_EVEN_247___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247__BQ_GAIN_EVEN_247___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_247___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248 (0x005FD3E0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__XLNA_GAIN_ODD_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__LNA_GAIN_ODD_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__GM_GAIN_ODD_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__TIA_GAIN_ODD_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__SLM_XLNA_ODD_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__BQ_GAIN_ODD_248___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__XLNA_GAIN_EVEN_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__LNA_GAIN_EVEN_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__GM_GAIN_EVEN_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__TIA_GAIN_EVEN_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__SLM_XLNA_EVEN_248___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__BQ_GAIN_EVEN_248___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__XLNA_GAIN_ODD_248___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__XLNA_GAIN_ODD_248___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__LNA_GAIN_ODD_248___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__LNA_GAIN_ODD_248___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__GM_GAIN_ODD_248___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__GM_GAIN_ODD_248___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__TIA_GAIN_ODD_248___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__TIA_GAIN_ODD_248___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__SLM_XLNA_ODD_248___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__SLM_XLNA_ODD_248___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__BQ_GAIN_ODD_248___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__BQ_GAIN_ODD_248___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__XLNA_GAIN_EVEN_248___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__XLNA_GAIN_EVEN_248___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__LNA_GAIN_EVEN_248___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__LNA_GAIN_EVEN_248___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__GM_GAIN_EVEN_248___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__GM_GAIN_EVEN_248___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__TIA_GAIN_EVEN_248___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__TIA_GAIN_EVEN_248___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__SLM_XLNA_EVEN_248___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__SLM_XLNA_EVEN_248___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__BQ_GAIN_EVEN_248___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248__BQ_GAIN_EVEN_248___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_248___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249 (0x005FD3E4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__XLNA_GAIN_ODD_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__LNA_GAIN_ODD_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__GM_GAIN_ODD_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__TIA_GAIN_ODD_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__SLM_XLNA_ODD_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__BQ_GAIN_ODD_249___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__XLNA_GAIN_EVEN_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__LNA_GAIN_EVEN_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__GM_GAIN_EVEN_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__TIA_GAIN_EVEN_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__SLM_XLNA_EVEN_249___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__BQ_GAIN_EVEN_249___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__XLNA_GAIN_ODD_249___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__XLNA_GAIN_ODD_249___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__LNA_GAIN_ODD_249___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__LNA_GAIN_ODD_249___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__GM_GAIN_ODD_249___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__GM_GAIN_ODD_249___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__TIA_GAIN_ODD_249___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__TIA_GAIN_ODD_249___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__SLM_XLNA_ODD_249___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__SLM_XLNA_ODD_249___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__BQ_GAIN_ODD_249___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__BQ_GAIN_ODD_249___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__XLNA_GAIN_EVEN_249___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__XLNA_GAIN_EVEN_249___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__LNA_GAIN_EVEN_249___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__LNA_GAIN_EVEN_249___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__GM_GAIN_EVEN_249___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__GM_GAIN_EVEN_249___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__TIA_GAIN_EVEN_249___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__TIA_GAIN_EVEN_249___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__SLM_XLNA_EVEN_249___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__SLM_XLNA_EVEN_249___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__BQ_GAIN_EVEN_249___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249__BQ_GAIN_EVEN_249___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_249___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250 (0x005FD3E8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__XLNA_GAIN_ODD_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__LNA_GAIN_ODD_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__GM_GAIN_ODD_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__TIA_GAIN_ODD_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__SLM_XLNA_ODD_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__BQ_GAIN_ODD_250___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__XLNA_GAIN_EVEN_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__LNA_GAIN_EVEN_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__GM_GAIN_EVEN_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__TIA_GAIN_EVEN_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__SLM_XLNA_EVEN_250___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__BQ_GAIN_EVEN_250___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__XLNA_GAIN_ODD_250___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__XLNA_GAIN_ODD_250___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__LNA_GAIN_ODD_250___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__LNA_GAIN_ODD_250___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__GM_GAIN_ODD_250___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__GM_GAIN_ODD_250___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__TIA_GAIN_ODD_250___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__TIA_GAIN_ODD_250___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__SLM_XLNA_ODD_250___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__SLM_XLNA_ODD_250___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__BQ_GAIN_ODD_250___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__BQ_GAIN_ODD_250___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__XLNA_GAIN_EVEN_250___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__XLNA_GAIN_EVEN_250___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__LNA_GAIN_EVEN_250___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__LNA_GAIN_EVEN_250___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__GM_GAIN_EVEN_250___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__GM_GAIN_EVEN_250___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__TIA_GAIN_EVEN_250___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__TIA_GAIN_EVEN_250___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__SLM_XLNA_EVEN_250___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__SLM_XLNA_EVEN_250___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__BQ_GAIN_EVEN_250___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250__BQ_GAIN_EVEN_250___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_250___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251 (0x005FD3EC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__XLNA_GAIN_ODD_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__LNA_GAIN_ODD_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__GM_GAIN_ODD_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__TIA_GAIN_ODD_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__SLM_XLNA_ODD_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__BQ_GAIN_ODD_251___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__XLNA_GAIN_EVEN_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__LNA_GAIN_EVEN_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__GM_GAIN_EVEN_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__TIA_GAIN_EVEN_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__SLM_XLNA_EVEN_251___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__BQ_GAIN_EVEN_251___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__XLNA_GAIN_ODD_251___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__XLNA_GAIN_ODD_251___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__LNA_GAIN_ODD_251___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__LNA_GAIN_ODD_251___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__GM_GAIN_ODD_251___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__GM_GAIN_ODD_251___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__TIA_GAIN_ODD_251___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__TIA_GAIN_ODD_251___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__SLM_XLNA_ODD_251___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__SLM_XLNA_ODD_251___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__BQ_GAIN_ODD_251___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__BQ_GAIN_ODD_251___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__XLNA_GAIN_EVEN_251___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__XLNA_GAIN_EVEN_251___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__LNA_GAIN_EVEN_251___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__LNA_GAIN_EVEN_251___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__GM_GAIN_EVEN_251___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__GM_GAIN_EVEN_251___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__TIA_GAIN_EVEN_251___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__TIA_GAIN_EVEN_251___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__SLM_XLNA_EVEN_251___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__SLM_XLNA_EVEN_251___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__BQ_GAIN_EVEN_251___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251__BQ_GAIN_EVEN_251___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_251___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252 (0x005FD3F0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__XLNA_GAIN_ODD_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__LNA_GAIN_ODD_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__GM_GAIN_ODD_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__TIA_GAIN_ODD_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__SLM_XLNA_ODD_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__BQ_GAIN_ODD_252___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__XLNA_GAIN_EVEN_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__LNA_GAIN_EVEN_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__GM_GAIN_EVEN_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__TIA_GAIN_EVEN_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__SLM_XLNA_EVEN_252___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__BQ_GAIN_EVEN_252___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__XLNA_GAIN_ODD_252___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__XLNA_GAIN_ODD_252___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__LNA_GAIN_ODD_252___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__LNA_GAIN_ODD_252___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__GM_GAIN_ODD_252___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__GM_GAIN_ODD_252___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__TIA_GAIN_ODD_252___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__TIA_GAIN_ODD_252___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__SLM_XLNA_ODD_252___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__SLM_XLNA_ODD_252___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__BQ_GAIN_ODD_252___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__BQ_GAIN_ODD_252___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__XLNA_GAIN_EVEN_252___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__XLNA_GAIN_EVEN_252___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__LNA_GAIN_EVEN_252___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__LNA_GAIN_EVEN_252___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__GM_GAIN_EVEN_252___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__GM_GAIN_EVEN_252___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__TIA_GAIN_EVEN_252___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__TIA_GAIN_EVEN_252___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__SLM_XLNA_EVEN_252___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__SLM_XLNA_EVEN_252___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__BQ_GAIN_EVEN_252___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252__BQ_GAIN_EVEN_252___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_252___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253 (0x005FD3F4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__XLNA_GAIN_ODD_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__LNA_GAIN_ODD_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__GM_GAIN_ODD_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__TIA_GAIN_ODD_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__SLM_XLNA_ODD_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__BQ_GAIN_ODD_253___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__XLNA_GAIN_EVEN_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__LNA_GAIN_EVEN_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__GM_GAIN_EVEN_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__TIA_GAIN_EVEN_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__SLM_XLNA_EVEN_253___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__BQ_GAIN_EVEN_253___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__XLNA_GAIN_ODD_253___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__XLNA_GAIN_ODD_253___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__LNA_GAIN_ODD_253___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__LNA_GAIN_ODD_253___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__GM_GAIN_ODD_253___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__GM_GAIN_ODD_253___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__TIA_GAIN_ODD_253___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__TIA_GAIN_ODD_253___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__SLM_XLNA_ODD_253___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__SLM_XLNA_ODD_253___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__BQ_GAIN_ODD_253___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__BQ_GAIN_ODD_253___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__XLNA_GAIN_EVEN_253___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__XLNA_GAIN_EVEN_253___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__LNA_GAIN_EVEN_253___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__LNA_GAIN_EVEN_253___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__GM_GAIN_EVEN_253___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__GM_GAIN_EVEN_253___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__TIA_GAIN_EVEN_253___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__TIA_GAIN_EVEN_253___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__SLM_XLNA_EVEN_253___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__SLM_XLNA_EVEN_253___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__BQ_GAIN_EVEN_253___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253__BQ_GAIN_EVEN_253___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_253___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254 (0x005FD3F8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__XLNA_GAIN_ODD_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__LNA_GAIN_ODD_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__GM_GAIN_ODD_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__TIA_GAIN_ODD_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__SLM_XLNA_ODD_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__BQ_GAIN_ODD_254___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__XLNA_GAIN_EVEN_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__LNA_GAIN_EVEN_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__GM_GAIN_EVEN_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__TIA_GAIN_EVEN_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__SLM_XLNA_EVEN_254___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__BQ_GAIN_EVEN_254___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__XLNA_GAIN_ODD_254___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__XLNA_GAIN_ODD_254___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__LNA_GAIN_ODD_254___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__LNA_GAIN_ODD_254___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__GM_GAIN_ODD_254___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__GM_GAIN_ODD_254___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__TIA_GAIN_ODD_254___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__TIA_GAIN_ODD_254___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__SLM_XLNA_ODD_254___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__SLM_XLNA_ODD_254___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__BQ_GAIN_ODD_254___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__BQ_GAIN_ODD_254___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__XLNA_GAIN_EVEN_254___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__XLNA_GAIN_EVEN_254___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__LNA_GAIN_EVEN_254___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__LNA_GAIN_EVEN_254___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__GM_GAIN_EVEN_254___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__GM_GAIN_EVEN_254___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__TIA_GAIN_EVEN_254___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__TIA_GAIN_EVEN_254___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__SLM_XLNA_EVEN_254___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__SLM_XLNA_EVEN_254___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__BQ_GAIN_EVEN_254___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254__BQ_GAIN_EVEN_254___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_254___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255 (0x005FD3FC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__XLNA_GAIN_ODD_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__LNA_GAIN_ODD_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__GM_GAIN_ODD_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__TIA_GAIN_ODD_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__SLM_XLNA_ODD_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__BQ_GAIN_ODD_255___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__XLNA_GAIN_EVEN_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__LNA_GAIN_EVEN_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__GM_GAIN_EVEN_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__TIA_GAIN_EVEN_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__SLM_XLNA_EVEN_255___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__BQ_GAIN_EVEN_255___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__XLNA_GAIN_ODD_255___M 0x80000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__XLNA_GAIN_ODD_255___S 31 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__LNA_GAIN_ODD_255___M 0x70000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__LNA_GAIN_ODD_255___S 28 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__GM_GAIN_ODD_255___M 0x0E000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__GM_GAIN_ODD_255___S 25 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__TIA_GAIN_ODD_255___M 0x01800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__TIA_GAIN_ODD_255___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__SLM_XLNA_ODD_255___M 0x00200000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__SLM_XLNA_ODD_255___S 21 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__BQ_GAIN_ODD_255___M 0x001F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__BQ_GAIN_ODD_255___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__XLNA_GAIN_EVEN_255___M 0x00008000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__XLNA_GAIN_EVEN_255___S 15 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__LNA_GAIN_EVEN_255___M 0x00007000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__LNA_GAIN_EVEN_255___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__GM_GAIN_EVEN_255___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__GM_GAIN_EVEN_255___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__TIA_GAIN_EVEN_255___M 0x00000180 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__TIA_GAIN_EVEN_255___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__SLM_XLNA_EVEN_255___M 0x00000020 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__SLM_XLNA_EVEN_255___S 5 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__BQ_GAIN_EVEN_255___M 0x0000001F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255__BQ_GAIN_EVEN_255___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255___M 0xFFBFFFBF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_RXGAIN_255___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_0 (0x005FD800) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_0__TX_DCOC_RES_I_ODD_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_0__TX_DCOC_RES_Q_ODD_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_0__TX_DCOC_RES_I_EVEN_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_0__TX_DCOC_RES_Q_EVEN_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_0__TX_DCOC_RES_I_ODD_0___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_0__TX_DCOC_RES_I_ODD_0___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_0__TX_DCOC_RES_Q_ODD_0___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_0__TX_DCOC_RES_Q_ODD_0___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_0__TX_DCOC_RES_I_EVEN_0___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_0__TX_DCOC_RES_I_EVEN_0___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_0__TX_DCOC_RES_Q_EVEN_0___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_0__TX_DCOC_RES_Q_EVEN_0___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_0___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_1 (0x005FD804) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_1__TX_DCOC_RES_I_ODD_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_1__TX_DCOC_RES_Q_ODD_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_1__TX_DCOC_RES_I_EVEN_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_1__TX_DCOC_RES_Q_EVEN_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_1__TX_DCOC_RES_I_ODD_1___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_1__TX_DCOC_RES_I_ODD_1___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_1__TX_DCOC_RES_Q_ODD_1___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_1__TX_DCOC_RES_Q_ODD_1___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_1__TX_DCOC_RES_I_EVEN_1___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_1__TX_DCOC_RES_I_EVEN_1___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_1__TX_DCOC_RES_Q_EVEN_1___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_1__TX_DCOC_RES_Q_EVEN_1___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_1___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_2 (0x005FD808) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_2__TX_DCOC_RES_I_ODD_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_2__TX_DCOC_RES_Q_ODD_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_2__TX_DCOC_RES_I_EVEN_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_2__TX_DCOC_RES_Q_EVEN_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_2__TX_DCOC_RES_I_ODD_2___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_2__TX_DCOC_RES_I_ODD_2___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_2__TX_DCOC_RES_Q_ODD_2___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_2__TX_DCOC_RES_Q_ODD_2___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_2__TX_DCOC_RES_I_EVEN_2___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_2__TX_DCOC_RES_I_EVEN_2___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_2__TX_DCOC_RES_Q_EVEN_2___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_2__TX_DCOC_RES_Q_EVEN_2___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_2___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_2___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_3 (0x005FD80C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_3__TX_DCOC_RES_I_ODD_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_3__TX_DCOC_RES_Q_ODD_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_3__TX_DCOC_RES_I_EVEN_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_3__TX_DCOC_RES_Q_EVEN_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_3__TX_DCOC_RES_I_ODD_3___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_3__TX_DCOC_RES_I_ODD_3___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_3__TX_DCOC_RES_Q_ODD_3___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_3__TX_DCOC_RES_Q_ODD_3___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_3__TX_DCOC_RES_I_EVEN_3___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_3__TX_DCOC_RES_I_EVEN_3___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_3__TX_DCOC_RES_Q_EVEN_3___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_3__TX_DCOC_RES_Q_EVEN_3___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_3___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_3___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_4 (0x005FD810) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_4__TX_DCOC_RES_I_ODD_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_4__TX_DCOC_RES_Q_ODD_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_4__TX_DCOC_RES_I_EVEN_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_4__TX_DCOC_RES_Q_EVEN_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_4__TX_DCOC_RES_I_ODD_4___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_4__TX_DCOC_RES_I_ODD_4___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_4__TX_DCOC_RES_Q_ODD_4___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_4__TX_DCOC_RES_Q_ODD_4___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_4__TX_DCOC_RES_I_EVEN_4___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_4__TX_DCOC_RES_I_EVEN_4___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_4__TX_DCOC_RES_Q_EVEN_4___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_4__TX_DCOC_RES_Q_EVEN_4___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_4___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_4___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_5 (0x005FD814) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_5__TX_DCOC_RES_I_ODD_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_5__TX_DCOC_RES_Q_ODD_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_5__TX_DCOC_RES_I_EVEN_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_5__TX_DCOC_RES_Q_EVEN_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_5__TX_DCOC_RES_I_ODD_5___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_5__TX_DCOC_RES_I_ODD_5___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_5__TX_DCOC_RES_Q_ODD_5___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_5__TX_DCOC_RES_Q_ODD_5___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_5__TX_DCOC_RES_I_EVEN_5___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_5__TX_DCOC_RES_I_EVEN_5___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_5__TX_DCOC_RES_Q_EVEN_5___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_5__TX_DCOC_RES_Q_EVEN_5___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_5___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_5___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_6 (0x005FD818) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_6__TX_DCOC_RES_I_ODD_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_6__TX_DCOC_RES_Q_ODD_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_6__TX_DCOC_RES_I_EVEN_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_6__TX_DCOC_RES_Q_EVEN_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_6__TX_DCOC_RES_I_ODD_6___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_6__TX_DCOC_RES_I_ODD_6___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_6__TX_DCOC_RES_Q_ODD_6___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_6__TX_DCOC_RES_Q_ODD_6___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_6__TX_DCOC_RES_I_EVEN_6___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_6__TX_DCOC_RES_I_EVEN_6___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_6__TX_DCOC_RES_Q_EVEN_6___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_6__TX_DCOC_RES_Q_EVEN_6___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_6___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_6___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_7 (0x005FD81C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_7__TX_DCOC_RES_I_ODD_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_7__TX_DCOC_RES_Q_ODD_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_7__TX_DCOC_RES_I_EVEN_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_7__TX_DCOC_RES_Q_EVEN_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_7__TX_DCOC_RES_I_ODD_7___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_7__TX_DCOC_RES_I_ODD_7___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_7__TX_DCOC_RES_Q_ODD_7___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_7__TX_DCOC_RES_Q_ODD_7___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_7__TX_DCOC_RES_I_EVEN_7___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_7__TX_DCOC_RES_I_EVEN_7___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_7__TX_DCOC_RES_Q_EVEN_7___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_7__TX_DCOC_RES_Q_EVEN_7___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_7___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_7___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_8 (0x005FD820) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_8__TX_DCOC_RES_I_ODD_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_8__TX_DCOC_RES_Q_ODD_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_8__TX_DCOC_RES_I_EVEN_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_8__TX_DCOC_RES_Q_EVEN_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_8__TX_DCOC_RES_I_ODD_8___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_8__TX_DCOC_RES_I_ODD_8___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_8__TX_DCOC_RES_Q_ODD_8___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_8__TX_DCOC_RES_Q_ODD_8___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_8__TX_DCOC_RES_I_EVEN_8___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_8__TX_DCOC_RES_I_EVEN_8___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_8__TX_DCOC_RES_Q_EVEN_8___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_8__TX_DCOC_RES_Q_EVEN_8___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_8___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_8___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_9 (0x005FD824) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_9__TX_DCOC_RES_I_ODD_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_9__TX_DCOC_RES_Q_ODD_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_9__TX_DCOC_RES_I_EVEN_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_9__TX_DCOC_RES_Q_EVEN_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_9__TX_DCOC_RES_I_ODD_9___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_9__TX_DCOC_RES_I_ODD_9___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_9__TX_DCOC_RES_Q_ODD_9___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_9__TX_DCOC_RES_Q_ODD_9___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_9__TX_DCOC_RES_I_EVEN_9___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_9__TX_DCOC_RES_I_EVEN_9___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_9__TX_DCOC_RES_Q_EVEN_9___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_9__TX_DCOC_RES_Q_EVEN_9___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_9___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_9___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_10 (0x005FD828) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_10__TX_DCOC_RES_I_ODD_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_10__TX_DCOC_RES_Q_ODD_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_10__TX_DCOC_RES_I_EVEN_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_10__TX_DCOC_RES_Q_EVEN_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_10__TX_DCOC_RES_I_ODD_10___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_10__TX_DCOC_RES_I_ODD_10___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_10__TX_DCOC_RES_Q_ODD_10___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_10__TX_DCOC_RES_Q_ODD_10___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_10__TX_DCOC_RES_I_EVEN_10___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_10__TX_DCOC_RES_I_EVEN_10___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_10__TX_DCOC_RES_Q_EVEN_10___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_10__TX_DCOC_RES_Q_EVEN_10___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_10___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_10___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_11 (0x005FD82C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_11__TX_DCOC_RES_I_ODD_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_11__TX_DCOC_RES_Q_ODD_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_11__TX_DCOC_RES_I_EVEN_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_11__TX_DCOC_RES_Q_EVEN_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_11__TX_DCOC_RES_I_ODD_11___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_11__TX_DCOC_RES_I_ODD_11___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_11__TX_DCOC_RES_Q_ODD_11___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_11__TX_DCOC_RES_Q_ODD_11___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_11__TX_DCOC_RES_I_EVEN_11___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_11__TX_DCOC_RES_I_EVEN_11___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_11__TX_DCOC_RES_Q_EVEN_11___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_11__TX_DCOC_RES_Q_EVEN_11___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_11___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_11___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_12 (0x005FD830) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_12__TX_DCOC_RES_I_ODD_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_12__TX_DCOC_RES_Q_ODD_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_12__TX_DCOC_RES_I_EVEN_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_12__TX_DCOC_RES_Q_EVEN_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_12__TX_DCOC_RES_I_ODD_12___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_12__TX_DCOC_RES_I_ODD_12___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_12__TX_DCOC_RES_Q_ODD_12___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_12__TX_DCOC_RES_Q_ODD_12___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_12__TX_DCOC_RES_I_EVEN_12___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_12__TX_DCOC_RES_I_EVEN_12___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_12__TX_DCOC_RES_Q_EVEN_12___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_12__TX_DCOC_RES_Q_EVEN_12___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_12___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_12___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_13 (0x005FD834) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_13__TX_DCOC_RES_I_ODD_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_13__TX_DCOC_RES_Q_ODD_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_13__TX_DCOC_RES_I_EVEN_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_13__TX_DCOC_RES_Q_EVEN_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_13__TX_DCOC_RES_I_ODD_13___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_13__TX_DCOC_RES_I_ODD_13___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_13__TX_DCOC_RES_Q_ODD_13___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_13__TX_DCOC_RES_Q_ODD_13___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_13__TX_DCOC_RES_I_EVEN_13___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_13__TX_DCOC_RES_I_EVEN_13___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_13__TX_DCOC_RES_Q_EVEN_13___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_13__TX_DCOC_RES_Q_EVEN_13___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_13___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_13___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_14 (0x005FD838) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_14__TX_DCOC_RES_I_ODD_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_14__TX_DCOC_RES_Q_ODD_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_14__TX_DCOC_RES_I_EVEN_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_14__TX_DCOC_RES_Q_EVEN_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_14__TX_DCOC_RES_I_ODD_14___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_14__TX_DCOC_RES_I_ODD_14___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_14__TX_DCOC_RES_Q_ODD_14___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_14__TX_DCOC_RES_Q_ODD_14___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_14__TX_DCOC_RES_I_EVEN_14___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_14__TX_DCOC_RES_I_EVEN_14___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_14__TX_DCOC_RES_Q_EVEN_14___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_14__TX_DCOC_RES_Q_EVEN_14___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_14___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_14___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_15 (0x005FD83C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_15__TX_DCOC_RES_I_ODD_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_15__TX_DCOC_RES_Q_ODD_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_15__TX_DCOC_RES_I_EVEN_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_15__TX_DCOC_RES_Q_EVEN_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_15__TX_DCOC_RES_I_ODD_15___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_15__TX_DCOC_RES_I_ODD_15___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_15__TX_DCOC_RES_Q_ODD_15___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_15__TX_DCOC_RES_Q_ODD_15___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_15__TX_DCOC_RES_I_EVEN_15___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_15__TX_DCOC_RES_I_EVEN_15___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_15__TX_DCOC_RES_Q_EVEN_15___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_15__TX_DCOC_RES_Q_EVEN_15___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_15___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_15___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_16 (0x005FD840) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_16___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_16__TX_DCOC_RES_I_ODD_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_16__TX_DCOC_RES_Q_ODD_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_16__TX_DCOC_RES_I_EVEN_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_16__TX_DCOC_RES_Q_EVEN_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_16__TX_DCOC_RES_I_ODD_16___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_16__TX_DCOC_RES_I_ODD_16___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_16__TX_DCOC_RES_Q_ODD_16___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_16__TX_DCOC_RES_Q_ODD_16___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_16__TX_DCOC_RES_I_EVEN_16___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_16__TX_DCOC_RES_I_EVEN_16___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_16__TX_DCOC_RES_Q_EVEN_16___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_16__TX_DCOC_RES_Q_EVEN_16___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_16___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_16___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_17 (0x005FD844) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_17___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_17__TX_DCOC_RES_I_ODD_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_17__TX_DCOC_RES_Q_ODD_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_17__TX_DCOC_RES_I_EVEN_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_17__TX_DCOC_RES_Q_EVEN_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_17__TX_DCOC_RES_I_ODD_17___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_17__TX_DCOC_RES_I_ODD_17___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_17__TX_DCOC_RES_Q_ODD_17___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_17__TX_DCOC_RES_Q_ODD_17___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_17__TX_DCOC_RES_I_EVEN_17___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_17__TX_DCOC_RES_I_EVEN_17___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_17__TX_DCOC_RES_Q_EVEN_17___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_17__TX_DCOC_RES_Q_EVEN_17___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_17___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_17___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_18 (0x005FD848) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_18___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_18__TX_DCOC_RES_I_ODD_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_18__TX_DCOC_RES_Q_ODD_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_18__TX_DCOC_RES_I_EVEN_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_18__TX_DCOC_RES_Q_EVEN_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_18__TX_DCOC_RES_I_ODD_18___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_18__TX_DCOC_RES_I_ODD_18___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_18__TX_DCOC_RES_Q_ODD_18___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_18__TX_DCOC_RES_Q_ODD_18___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_18__TX_DCOC_RES_I_EVEN_18___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_18__TX_DCOC_RES_I_EVEN_18___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_18__TX_DCOC_RES_Q_EVEN_18___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_18__TX_DCOC_RES_Q_EVEN_18___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_18___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_18___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_19 (0x005FD84C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_19___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_19__TX_DCOC_RES_I_ODD_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_19__TX_DCOC_RES_Q_ODD_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_19__TX_DCOC_RES_I_EVEN_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_19__TX_DCOC_RES_Q_EVEN_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_19__TX_DCOC_RES_I_ODD_19___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_19__TX_DCOC_RES_I_ODD_19___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_19__TX_DCOC_RES_Q_ODD_19___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_19__TX_DCOC_RES_Q_ODD_19___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_19__TX_DCOC_RES_I_EVEN_19___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_19__TX_DCOC_RES_I_EVEN_19___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_19__TX_DCOC_RES_Q_EVEN_19___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_19__TX_DCOC_RES_Q_EVEN_19___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_19___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_19___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_20 (0x005FD850) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_20___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_20__TX_DCOC_RES_I_ODD_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_20__TX_DCOC_RES_Q_ODD_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_20__TX_DCOC_RES_I_EVEN_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_20__TX_DCOC_RES_Q_EVEN_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_20__TX_DCOC_RES_I_ODD_20___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_20__TX_DCOC_RES_I_ODD_20___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_20__TX_DCOC_RES_Q_ODD_20___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_20__TX_DCOC_RES_Q_ODD_20___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_20__TX_DCOC_RES_I_EVEN_20___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_20__TX_DCOC_RES_I_EVEN_20___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_20__TX_DCOC_RES_Q_EVEN_20___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_20__TX_DCOC_RES_Q_EVEN_20___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_20___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_20___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_21 (0x005FD854) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_21___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_21__TX_DCOC_RES_I_ODD_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_21__TX_DCOC_RES_Q_ODD_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_21__TX_DCOC_RES_I_EVEN_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_21__TX_DCOC_RES_Q_EVEN_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_21__TX_DCOC_RES_I_ODD_21___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_21__TX_DCOC_RES_I_ODD_21___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_21__TX_DCOC_RES_Q_ODD_21___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_21__TX_DCOC_RES_Q_ODD_21___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_21__TX_DCOC_RES_I_EVEN_21___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_21__TX_DCOC_RES_I_EVEN_21___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_21__TX_DCOC_RES_Q_EVEN_21___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_21__TX_DCOC_RES_Q_EVEN_21___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_21___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_21___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_22 (0x005FD858) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_22___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_22__TX_DCOC_RES_I_ODD_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_22__TX_DCOC_RES_Q_ODD_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_22__TX_DCOC_RES_I_EVEN_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_22__TX_DCOC_RES_Q_EVEN_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_22__TX_DCOC_RES_I_ODD_22___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_22__TX_DCOC_RES_I_ODD_22___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_22__TX_DCOC_RES_Q_ODD_22___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_22__TX_DCOC_RES_Q_ODD_22___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_22__TX_DCOC_RES_I_EVEN_22___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_22__TX_DCOC_RES_I_EVEN_22___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_22__TX_DCOC_RES_Q_EVEN_22___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_22__TX_DCOC_RES_Q_EVEN_22___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_22___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_22___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_23 (0x005FD85C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_23___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_23__TX_DCOC_RES_I_ODD_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_23__TX_DCOC_RES_Q_ODD_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_23__TX_DCOC_RES_I_EVEN_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_23__TX_DCOC_RES_Q_EVEN_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_23__TX_DCOC_RES_I_ODD_23___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_23__TX_DCOC_RES_I_ODD_23___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_23__TX_DCOC_RES_Q_ODD_23___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_23__TX_DCOC_RES_Q_ODD_23___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_23__TX_DCOC_RES_I_EVEN_23___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_23__TX_DCOC_RES_I_EVEN_23___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_23__TX_DCOC_RES_Q_EVEN_23___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_23__TX_DCOC_RES_Q_EVEN_23___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_23___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_23___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_24 (0x005FD860) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_24___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_24__TX_DCOC_RES_I_ODD_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_24__TX_DCOC_RES_Q_ODD_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_24__TX_DCOC_RES_I_EVEN_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_24__TX_DCOC_RES_Q_EVEN_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_24__TX_DCOC_RES_I_ODD_24___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_24__TX_DCOC_RES_I_ODD_24___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_24__TX_DCOC_RES_Q_ODD_24___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_24__TX_DCOC_RES_Q_ODD_24___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_24__TX_DCOC_RES_I_EVEN_24___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_24__TX_DCOC_RES_I_EVEN_24___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_24__TX_DCOC_RES_Q_EVEN_24___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_24__TX_DCOC_RES_Q_EVEN_24___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_24___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_24___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_25 (0x005FD864) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_25___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_25__TX_DCOC_RES_I_ODD_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_25__TX_DCOC_RES_Q_ODD_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_25__TX_DCOC_RES_I_EVEN_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_25__TX_DCOC_RES_Q_EVEN_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_25__TX_DCOC_RES_I_ODD_25___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_25__TX_DCOC_RES_I_ODD_25___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_25__TX_DCOC_RES_Q_ODD_25___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_25__TX_DCOC_RES_Q_ODD_25___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_25__TX_DCOC_RES_I_EVEN_25___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_25__TX_DCOC_RES_I_EVEN_25___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_25__TX_DCOC_RES_Q_EVEN_25___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_25__TX_DCOC_RES_Q_EVEN_25___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_25___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_25___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_26 (0x005FD868) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_26___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_26__TX_DCOC_RES_I_ODD_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_26__TX_DCOC_RES_Q_ODD_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_26__TX_DCOC_RES_I_EVEN_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_26__TX_DCOC_RES_Q_EVEN_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_26__TX_DCOC_RES_I_ODD_26___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_26__TX_DCOC_RES_I_ODD_26___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_26__TX_DCOC_RES_Q_ODD_26___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_26__TX_DCOC_RES_Q_ODD_26___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_26__TX_DCOC_RES_I_EVEN_26___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_26__TX_DCOC_RES_I_EVEN_26___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_26__TX_DCOC_RES_Q_EVEN_26___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_26__TX_DCOC_RES_Q_EVEN_26___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_26___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_26___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_27 (0x005FD86C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_27___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_27__TX_DCOC_RES_I_ODD_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_27__TX_DCOC_RES_Q_ODD_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_27__TX_DCOC_RES_I_EVEN_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_27__TX_DCOC_RES_Q_EVEN_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_27__TX_DCOC_RES_I_ODD_27___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_27__TX_DCOC_RES_I_ODD_27___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_27__TX_DCOC_RES_Q_ODD_27___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_27__TX_DCOC_RES_Q_ODD_27___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_27__TX_DCOC_RES_I_EVEN_27___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_27__TX_DCOC_RES_I_EVEN_27___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_27__TX_DCOC_RES_Q_EVEN_27___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_27__TX_DCOC_RES_Q_EVEN_27___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_27___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_27___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_28 (0x005FD870) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_28___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_28__TX_DCOC_RES_I_ODD_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_28__TX_DCOC_RES_Q_ODD_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_28__TX_DCOC_RES_I_EVEN_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_28__TX_DCOC_RES_Q_EVEN_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_28__TX_DCOC_RES_I_ODD_28___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_28__TX_DCOC_RES_I_ODD_28___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_28__TX_DCOC_RES_Q_ODD_28___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_28__TX_DCOC_RES_Q_ODD_28___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_28__TX_DCOC_RES_I_EVEN_28___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_28__TX_DCOC_RES_I_EVEN_28___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_28__TX_DCOC_RES_Q_EVEN_28___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_28__TX_DCOC_RES_Q_EVEN_28___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_28___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_28___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_29 (0x005FD874) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_29___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_29__TX_DCOC_RES_I_ODD_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_29__TX_DCOC_RES_Q_ODD_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_29__TX_DCOC_RES_I_EVEN_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_29__TX_DCOC_RES_Q_EVEN_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_29__TX_DCOC_RES_I_ODD_29___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_29__TX_DCOC_RES_I_ODD_29___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_29__TX_DCOC_RES_Q_ODD_29___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_29__TX_DCOC_RES_Q_ODD_29___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_29__TX_DCOC_RES_I_EVEN_29___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_29__TX_DCOC_RES_I_EVEN_29___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_29__TX_DCOC_RES_Q_EVEN_29___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_29__TX_DCOC_RES_Q_EVEN_29___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_29___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_29___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_30 (0x005FD878) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_30___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_30__TX_DCOC_RES_I_ODD_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_30__TX_DCOC_RES_Q_ODD_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_30__TX_DCOC_RES_I_EVEN_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_30__TX_DCOC_RES_Q_EVEN_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_30__TX_DCOC_RES_I_ODD_30___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_30__TX_DCOC_RES_I_ODD_30___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_30__TX_DCOC_RES_Q_ODD_30___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_30__TX_DCOC_RES_Q_ODD_30___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_30__TX_DCOC_RES_I_EVEN_30___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_30__TX_DCOC_RES_I_EVEN_30___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_30__TX_DCOC_RES_Q_EVEN_30___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_30__TX_DCOC_RES_Q_EVEN_30___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_30___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_30___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_31 (0x005FD87C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_31___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_31__TX_DCOC_RES_I_ODD_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_31__TX_DCOC_RES_Q_ODD_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_31__TX_DCOC_RES_I_EVEN_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_31__TX_DCOC_RES_Q_EVEN_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_31__TX_DCOC_RES_I_ODD_31___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_31__TX_DCOC_RES_I_ODD_31___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_31__TX_DCOC_RES_Q_ODD_31___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_31__TX_DCOC_RES_Q_ODD_31___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_31__TX_DCOC_RES_I_EVEN_31___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_31__TX_DCOC_RES_I_EVEN_31___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_31__TX_DCOC_RES_Q_EVEN_31___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_31__TX_DCOC_RES_Q_EVEN_31___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_31___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_31___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_32 (0x005FD880) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_32___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_32___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_32__TX_DCOC_RES_I_ODD_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_32__TX_DCOC_RES_Q_ODD_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_32__TX_DCOC_RES_I_EVEN_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_32__TX_DCOC_RES_Q_EVEN_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_32__TX_DCOC_RES_I_ODD_32___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_32__TX_DCOC_RES_I_ODD_32___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_32__TX_DCOC_RES_Q_ODD_32___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_32__TX_DCOC_RES_Q_ODD_32___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_32__TX_DCOC_RES_I_EVEN_32___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_32__TX_DCOC_RES_I_EVEN_32___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_32__TX_DCOC_RES_Q_EVEN_32___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_32__TX_DCOC_RES_Q_EVEN_32___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_32___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_32___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_33 (0x005FD884) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_33___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_33___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_33__TX_DCOC_RES_I_ODD_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_33__TX_DCOC_RES_Q_ODD_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_33__TX_DCOC_RES_I_EVEN_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_33__TX_DCOC_RES_Q_EVEN_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_33__TX_DCOC_RES_I_ODD_33___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_33__TX_DCOC_RES_I_ODD_33___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_33__TX_DCOC_RES_Q_ODD_33___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_33__TX_DCOC_RES_Q_ODD_33___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_33__TX_DCOC_RES_I_EVEN_33___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_33__TX_DCOC_RES_I_EVEN_33___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_33__TX_DCOC_RES_Q_EVEN_33___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_33__TX_DCOC_RES_Q_EVEN_33___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_33___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_33___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_34 (0x005FD888) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_34___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_34___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_34__TX_DCOC_RES_I_ODD_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_34__TX_DCOC_RES_Q_ODD_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_34__TX_DCOC_RES_I_EVEN_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_34__TX_DCOC_RES_Q_EVEN_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_34__TX_DCOC_RES_I_ODD_34___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_34__TX_DCOC_RES_I_ODD_34___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_34__TX_DCOC_RES_Q_ODD_34___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_34__TX_DCOC_RES_Q_ODD_34___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_34__TX_DCOC_RES_I_EVEN_34___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_34__TX_DCOC_RES_I_EVEN_34___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_34__TX_DCOC_RES_Q_EVEN_34___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_34__TX_DCOC_RES_Q_EVEN_34___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_34___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_34___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_35 (0x005FD88C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_35___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_35___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_35__TX_DCOC_RES_I_ODD_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_35__TX_DCOC_RES_Q_ODD_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_35__TX_DCOC_RES_I_EVEN_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_35__TX_DCOC_RES_Q_EVEN_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_35__TX_DCOC_RES_I_ODD_35___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_35__TX_DCOC_RES_I_ODD_35___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_35__TX_DCOC_RES_Q_ODD_35___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_35__TX_DCOC_RES_Q_ODD_35___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_35__TX_DCOC_RES_I_EVEN_35___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_35__TX_DCOC_RES_I_EVEN_35___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_35__TX_DCOC_RES_Q_EVEN_35___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_35__TX_DCOC_RES_Q_EVEN_35___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_35___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_35___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_36 (0x005FD890) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_36___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_36___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_36__TX_DCOC_RES_I_ODD_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_36__TX_DCOC_RES_Q_ODD_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_36__TX_DCOC_RES_I_EVEN_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_36__TX_DCOC_RES_Q_EVEN_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_36__TX_DCOC_RES_I_ODD_36___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_36__TX_DCOC_RES_I_ODD_36___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_36__TX_DCOC_RES_Q_ODD_36___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_36__TX_DCOC_RES_Q_ODD_36___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_36__TX_DCOC_RES_I_EVEN_36___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_36__TX_DCOC_RES_I_EVEN_36___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_36__TX_DCOC_RES_Q_EVEN_36___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_36__TX_DCOC_RES_Q_EVEN_36___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_36___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_36___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_37 (0x005FD894) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_37___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_37___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_37__TX_DCOC_RES_I_ODD_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_37__TX_DCOC_RES_Q_ODD_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_37__TX_DCOC_RES_I_EVEN_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_37__TX_DCOC_RES_Q_EVEN_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_37__TX_DCOC_RES_I_ODD_37___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_37__TX_DCOC_RES_I_ODD_37___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_37__TX_DCOC_RES_Q_ODD_37___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_37__TX_DCOC_RES_Q_ODD_37___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_37__TX_DCOC_RES_I_EVEN_37___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_37__TX_DCOC_RES_I_EVEN_37___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_37__TX_DCOC_RES_Q_EVEN_37___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_37__TX_DCOC_RES_Q_EVEN_37___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_37___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_37___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_38 (0x005FD898) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_38___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_38___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_38__TX_DCOC_RES_I_ODD_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_38__TX_DCOC_RES_Q_ODD_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_38__TX_DCOC_RES_I_EVEN_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_38__TX_DCOC_RES_Q_EVEN_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_38__TX_DCOC_RES_I_ODD_38___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_38__TX_DCOC_RES_I_ODD_38___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_38__TX_DCOC_RES_Q_ODD_38___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_38__TX_DCOC_RES_Q_ODD_38___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_38__TX_DCOC_RES_I_EVEN_38___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_38__TX_DCOC_RES_I_EVEN_38___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_38__TX_DCOC_RES_Q_EVEN_38___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_38__TX_DCOC_RES_Q_EVEN_38___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_38___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_38___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_39 (0x005FD89C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_39___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_39___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_39__TX_DCOC_RES_I_ODD_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_39__TX_DCOC_RES_Q_ODD_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_39__TX_DCOC_RES_I_EVEN_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_39__TX_DCOC_RES_Q_EVEN_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_39__TX_DCOC_RES_I_ODD_39___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_39__TX_DCOC_RES_I_ODD_39___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_39__TX_DCOC_RES_Q_ODD_39___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_39__TX_DCOC_RES_Q_ODD_39___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_39__TX_DCOC_RES_I_EVEN_39___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_39__TX_DCOC_RES_I_EVEN_39___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_39__TX_DCOC_RES_Q_EVEN_39___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_39__TX_DCOC_RES_Q_EVEN_39___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_39___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_39___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_40 (0x005FD8A0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_40___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_40___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_40__TX_DCOC_RES_I_ODD_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_40__TX_DCOC_RES_Q_ODD_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_40__TX_DCOC_RES_I_EVEN_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_40__TX_DCOC_RES_Q_EVEN_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_40__TX_DCOC_RES_I_ODD_40___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_40__TX_DCOC_RES_I_ODD_40___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_40__TX_DCOC_RES_Q_ODD_40___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_40__TX_DCOC_RES_Q_ODD_40___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_40__TX_DCOC_RES_I_EVEN_40___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_40__TX_DCOC_RES_I_EVEN_40___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_40__TX_DCOC_RES_Q_EVEN_40___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_40__TX_DCOC_RES_Q_EVEN_40___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_40___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_40___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_41 (0x005FD8A4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_41___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_41___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_41__TX_DCOC_RES_I_ODD_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_41__TX_DCOC_RES_Q_ODD_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_41__TX_DCOC_RES_I_EVEN_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_41__TX_DCOC_RES_Q_EVEN_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_41__TX_DCOC_RES_I_ODD_41___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_41__TX_DCOC_RES_I_ODD_41___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_41__TX_DCOC_RES_Q_ODD_41___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_41__TX_DCOC_RES_Q_ODD_41___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_41__TX_DCOC_RES_I_EVEN_41___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_41__TX_DCOC_RES_I_EVEN_41___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_41__TX_DCOC_RES_Q_EVEN_41___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_41__TX_DCOC_RES_Q_EVEN_41___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_41___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_41___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_42 (0x005FD8A8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_42___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_42___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_42__TX_DCOC_RES_I_ODD_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_42__TX_DCOC_RES_Q_ODD_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_42__TX_DCOC_RES_I_EVEN_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_42__TX_DCOC_RES_Q_EVEN_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_42__TX_DCOC_RES_I_ODD_42___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_42__TX_DCOC_RES_I_ODD_42___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_42__TX_DCOC_RES_Q_ODD_42___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_42__TX_DCOC_RES_Q_ODD_42___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_42__TX_DCOC_RES_I_EVEN_42___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_42__TX_DCOC_RES_I_EVEN_42___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_42__TX_DCOC_RES_Q_EVEN_42___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_42__TX_DCOC_RES_Q_EVEN_42___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_42___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_42___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_43 (0x005FD8AC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_43___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_43___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_43__TX_DCOC_RES_I_ODD_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_43__TX_DCOC_RES_Q_ODD_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_43__TX_DCOC_RES_I_EVEN_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_43__TX_DCOC_RES_Q_EVEN_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_43__TX_DCOC_RES_I_ODD_43___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_43__TX_DCOC_RES_I_ODD_43___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_43__TX_DCOC_RES_Q_ODD_43___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_43__TX_DCOC_RES_Q_ODD_43___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_43__TX_DCOC_RES_I_EVEN_43___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_43__TX_DCOC_RES_I_EVEN_43___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_43__TX_DCOC_RES_Q_EVEN_43___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_43__TX_DCOC_RES_Q_EVEN_43___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_43___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_43___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_44 (0x005FD8B0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_44___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_44___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_44__TX_DCOC_RES_I_ODD_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_44__TX_DCOC_RES_Q_ODD_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_44__TX_DCOC_RES_I_EVEN_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_44__TX_DCOC_RES_Q_EVEN_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_44__TX_DCOC_RES_I_ODD_44___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_44__TX_DCOC_RES_I_ODD_44___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_44__TX_DCOC_RES_Q_ODD_44___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_44__TX_DCOC_RES_Q_ODD_44___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_44__TX_DCOC_RES_I_EVEN_44___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_44__TX_DCOC_RES_I_EVEN_44___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_44__TX_DCOC_RES_Q_EVEN_44___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_44__TX_DCOC_RES_Q_EVEN_44___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_44___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_44___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_45 (0x005FD8B4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_45___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_45___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_45__TX_DCOC_RES_I_ODD_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_45__TX_DCOC_RES_Q_ODD_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_45__TX_DCOC_RES_I_EVEN_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_45__TX_DCOC_RES_Q_EVEN_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_45__TX_DCOC_RES_I_ODD_45___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_45__TX_DCOC_RES_I_ODD_45___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_45__TX_DCOC_RES_Q_ODD_45___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_45__TX_DCOC_RES_Q_ODD_45___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_45__TX_DCOC_RES_I_EVEN_45___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_45__TX_DCOC_RES_I_EVEN_45___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_45__TX_DCOC_RES_Q_EVEN_45___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_45__TX_DCOC_RES_Q_EVEN_45___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_45___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_45___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_46 (0x005FD8B8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_46___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_46___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_46__TX_DCOC_RES_I_ODD_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_46__TX_DCOC_RES_Q_ODD_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_46__TX_DCOC_RES_I_EVEN_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_46__TX_DCOC_RES_Q_EVEN_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_46__TX_DCOC_RES_I_ODD_46___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_46__TX_DCOC_RES_I_ODD_46___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_46__TX_DCOC_RES_Q_ODD_46___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_46__TX_DCOC_RES_Q_ODD_46___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_46__TX_DCOC_RES_I_EVEN_46___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_46__TX_DCOC_RES_I_EVEN_46___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_46__TX_DCOC_RES_Q_EVEN_46___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_46__TX_DCOC_RES_Q_EVEN_46___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_46___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_46___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_47 (0x005FD8BC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_47___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_47___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_47__TX_DCOC_RES_I_ODD_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_47__TX_DCOC_RES_Q_ODD_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_47__TX_DCOC_RES_I_EVEN_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_47__TX_DCOC_RES_Q_EVEN_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_47__TX_DCOC_RES_I_ODD_47___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_47__TX_DCOC_RES_I_ODD_47___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_47__TX_DCOC_RES_Q_ODD_47___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_47__TX_DCOC_RES_Q_ODD_47___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_47__TX_DCOC_RES_I_EVEN_47___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_47__TX_DCOC_RES_I_EVEN_47___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_47__TX_DCOC_RES_Q_EVEN_47___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_47__TX_DCOC_RES_Q_EVEN_47___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_47___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_47___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_48 (0x005FD8C0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_48___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_48___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_48__TX_DCOC_RES_I_ODD_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_48__TX_DCOC_RES_Q_ODD_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_48__TX_DCOC_RES_I_EVEN_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_48__TX_DCOC_RES_Q_EVEN_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_48__TX_DCOC_RES_I_ODD_48___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_48__TX_DCOC_RES_I_ODD_48___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_48__TX_DCOC_RES_Q_ODD_48___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_48__TX_DCOC_RES_Q_ODD_48___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_48__TX_DCOC_RES_I_EVEN_48___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_48__TX_DCOC_RES_I_EVEN_48___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_48__TX_DCOC_RES_Q_EVEN_48___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_48__TX_DCOC_RES_Q_EVEN_48___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_48___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_48___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_49 (0x005FD8C4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_49___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_49___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_49__TX_DCOC_RES_I_ODD_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_49__TX_DCOC_RES_Q_ODD_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_49__TX_DCOC_RES_I_EVEN_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_49__TX_DCOC_RES_Q_EVEN_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_49__TX_DCOC_RES_I_ODD_49___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_49__TX_DCOC_RES_I_ODD_49___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_49__TX_DCOC_RES_Q_ODD_49___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_49__TX_DCOC_RES_Q_ODD_49___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_49__TX_DCOC_RES_I_EVEN_49___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_49__TX_DCOC_RES_I_EVEN_49___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_49__TX_DCOC_RES_Q_EVEN_49___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_49__TX_DCOC_RES_Q_EVEN_49___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_49___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_49___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_50 (0x005FD8C8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_50___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_50___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_50__TX_DCOC_RES_I_ODD_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_50__TX_DCOC_RES_Q_ODD_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_50__TX_DCOC_RES_I_EVEN_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_50__TX_DCOC_RES_Q_EVEN_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_50__TX_DCOC_RES_I_ODD_50___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_50__TX_DCOC_RES_I_ODD_50___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_50__TX_DCOC_RES_Q_ODD_50___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_50__TX_DCOC_RES_Q_ODD_50___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_50__TX_DCOC_RES_I_EVEN_50___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_50__TX_DCOC_RES_I_EVEN_50___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_50__TX_DCOC_RES_Q_EVEN_50___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_50__TX_DCOC_RES_Q_EVEN_50___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_50___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_50___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_51 (0x005FD8CC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_51___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_51___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_51__TX_DCOC_RES_I_ODD_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_51__TX_DCOC_RES_Q_ODD_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_51__TX_DCOC_RES_I_EVEN_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_51__TX_DCOC_RES_Q_EVEN_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_51__TX_DCOC_RES_I_ODD_51___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_51__TX_DCOC_RES_I_ODD_51___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_51__TX_DCOC_RES_Q_ODD_51___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_51__TX_DCOC_RES_Q_ODD_51___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_51__TX_DCOC_RES_I_EVEN_51___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_51__TX_DCOC_RES_I_EVEN_51___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_51__TX_DCOC_RES_Q_EVEN_51___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_51__TX_DCOC_RES_Q_EVEN_51___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_51___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_51___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_52 (0x005FD8D0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_52___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_52___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_52__TX_DCOC_RES_I_ODD_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_52__TX_DCOC_RES_Q_ODD_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_52__TX_DCOC_RES_I_EVEN_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_52__TX_DCOC_RES_Q_EVEN_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_52__TX_DCOC_RES_I_ODD_52___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_52__TX_DCOC_RES_I_ODD_52___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_52__TX_DCOC_RES_Q_ODD_52___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_52__TX_DCOC_RES_Q_ODD_52___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_52__TX_DCOC_RES_I_EVEN_52___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_52__TX_DCOC_RES_I_EVEN_52___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_52__TX_DCOC_RES_Q_EVEN_52___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_52__TX_DCOC_RES_Q_EVEN_52___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_52___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_52___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_53 (0x005FD8D4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_53___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_53___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_53__TX_DCOC_RES_I_ODD_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_53__TX_DCOC_RES_Q_ODD_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_53__TX_DCOC_RES_I_EVEN_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_53__TX_DCOC_RES_Q_EVEN_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_53__TX_DCOC_RES_I_ODD_53___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_53__TX_DCOC_RES_I_ODD_53___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_53__TX_DCOC_RES_Q_ODD_53___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_53__TX_DCOC_RES_Q_ODD_53___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_53__TX_DCOC_RES_I_EVEN_53___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_53__TX_DCOC_RES_I_EVEN_53___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_53__TX_DCOC_RES_Q_EVEN_53___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_53__TX_DCOC_RES_Q_EVEN_53___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_53___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_53___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_54 (0x005FD8D8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_54___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_54___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_54__TX_DCOC_RES_I_ODD_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_54__TX_DCOC_RES_Q_ODD_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_54__TX_DCOC_RES_I_EVEN_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_54__TX_DCOC_RES_Q_EVEN_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_54__TX_DCOC_RES_I_ODD_54___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_54__TX_DCOC_RES_I_ODD_54___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_54__TX_DCOC_RES_Q_ODD_54___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_54__TX_DCOC_RES_Q_ODD_54___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_54__TX_DCOC_RES_I_EVEN_54___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_54__TX_DCOC_RES_I_EVEN_54___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_54__TX_DCOC_RES_Q_EVEN_54___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_54__TX_DCOC_RES_Q_EVEN_54___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_54___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_54___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_55 (0x005FD8DC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_55___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_55___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_55__TX_DCOC_RES_I_ODD_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_55__TX_DCOC_RES_Q_ODD_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_55__TX_DCOC_RES_I_EVEN_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_55__TX_DCOC_RES_Q_EVEN_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_55__TX_DCOC_RES_I_ODD_55___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_55__TX_DCOC_RES_I_ODD_55___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_55__TX_DCOC_RES_Q_ODD_55___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_55__TX_DCOC_RES_Q_ODD_55___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_55__TX_DCOC_RES_I_EVEN_55___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_55__TX_DCOC_RES_I_EVEN_55___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_55__TX_DCOC_RES_Q_EVEN_55___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_55__TX_DCOC_RES_Q_EVEN_55___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_55___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_55___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_56 (0x005FD8E0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_56___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_56___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_56__TX_DCOC_RES_I_ODD_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_56__TX_DCOC_RES_Q_ODD_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_56__TX_DCOC_RES_I_EVEN_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_56__TX_DCOC_RES_Q_EVEN_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_56__TX_DCOC_RES_I_ODD_56___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_56__TX_DCOC_RES_I_ODD_56___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_56__TX_DCOC_RES_Q_ODD_56___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_56__TX_DCOC_RES_Q_ODD_56___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_56__TX_DCOC_RES_I_EVEN_56___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_56__TX_DCOC_RES_I_EVEN_56___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_56__TX_DCOC_RES_Q_EVEN_56___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_56__TX_DCOC_RES_Q_EVEN_56___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_56___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_56___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_57 (0x005FD8E4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_57___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_57___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_57__TX_DCOC_RES_I_ODD_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_57__TX_DCOC_RES_Q_ODD_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_57__TX_DCOC_RES_I_EVEN_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_57__TX_DCOC_RES_Q_EVEN_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_57__TX_DCOC_RES_I_ODD_57___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_57__TX_DCOC_RES_I_ODD_57___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_57__TX_DCOC_RES_Q_ODD_57___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_57__TX_DCOC_RES_Q_ODD_57___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_57__TX_DCOC_RES_I_EVEN_57___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_57__TX_DCOC_RES_I_EVEN_57___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_57__TX_DCOC_RES_Q_EVEN_57___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_57__TX_DCOC_RES_Q_EVEN_57___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_57___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_57___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_58 (0x005FD8E8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_58___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_58___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_58__TX_DCOC_RES_I_ODD_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_58__TX_DCOC_RES_Q_ODD_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_58__TX_DCOC_RES_I_EVEN_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_58__TX_DCOC_RES_Q_EVEN_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_58__TX_DCOC_RES_I_ODD_58___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_58__TX_DCOC_RES_I_ODD_58___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_58__TX_DCOC_RES_Q_ODD_58___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_58__TX_DCOC_RES_Q_ODD_58___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_58__TX_DCOC_RES_I_EVEN_58___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_58__TX_DCOC_RES_I_EVEN_58___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_58__TX_DCOC_RES_Q_EVEN_58___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_58__TX_DCOC_RES_Q_EVEN_58___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_58___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_58___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_59 (0x005FD8EC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_59___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_59___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_59__TX_DCOC_RES_I_ODD_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_59__TX_DCOC_RES_Q_ODD_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_59__TX_DCOC_RES_I_EVEN_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_59__TX_DCOC_RES_Q_EVEN_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_59__TX_DCOC_RES_I_ODD_59___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_59__TX_DCOC_RES_I_ODD_59___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_59__TX_DCOC_RES_Q_ODD_59___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_59__TX_DCOC_RES_Q_ODD_59___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_59__TX_DCOC_RES_I_EVEN_59___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_59__TX_DCOC_RES_I_EVEN_59___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_59__TX_DCOC_RES_Q_EVEN_59___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_59__TX_DCOC_RES_Q_EVEN_59___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_59___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_59___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_60 (0x005FD8F0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_60___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_60___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_60__TX_DCOC_RES_I_ODD_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_60__TX_DCOC_RES_Q_ODD_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_60__TX_DCOC_RES_I_EVEN_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_60__TX_DCOC_RES_Q_EVEN_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_60__TX_DCOC_RES_I_ODD_60___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_60__TX_DCOC_RES_I_ODD_60___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_60__TX_DCOC_RES_Q_ODD_60___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_60__TX_DCOC_RES_Q_ODD_60___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_60__TX_DCOC_RES_I_EVEN_60___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_60__TX_DCOC_RES_I_EVEN_60___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_60__TX_DCOC_RES_Q_EVEN_60___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_60__TX_DCOC_RES_Q_EVEN_60___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_60___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_60___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_61 (0x005FD8F4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_61___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_61___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_61__TX_DCOC_RES_I_ODD_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_61__TX_DCOC_RES_Q_ODD_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_61__TX_DCOC_RES_I_EVEN_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_61__TX_DCOC_RES_Q_EVEN_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_61__TX_DCOC_RES_I_ODD_61___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_61__TX_DCOC_RES_I_ODD_61___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_61__TX_DCOC_RES_Q_ODD_61___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_61__TX_DCOC_RES_Q_ODD_61___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_61__TX_DCOC_RES_I_EVEN_61___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_61__TX_DCOC_RES_I_EVEN_61___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_61__TX_DCOC_RES_Q_EVEN_61___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_61__TX_DCOC_RES_Q_EVEN_61___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_61___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_61___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_62 (0x005FD8F8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_62___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_62___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_62__TX_DCOC_RES_I_ODD_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_62__TX_DCOC_RES_Q_ODD_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_62__TX_DCOC_RES_I_EVEN_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_62__TX_DCOC_RES_Q_EVEN_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_62__TX_DCOC_RES_I_ODD_62___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_62__TX_DCOC_RES_I_ODD_62___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_62__TX_DCOC_RES_Q_ODD_62___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_62__TX_DCOC_RES_Q_ODD_62___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_62__TX_DCOC_RES_I_EVEN_62___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_62__TX_DCOC_RES_I_EVEN_62___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_62__TX_DCOC_RES_Q_EVEN_62___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_62__TX_DCOC_RES_Q_EVEN_62___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_62___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_62___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_63 (0x005FD8FC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_63___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_63___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_63__TX_DCOC_RES_I_ODD_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_63__TX_DCOC_RES_Q_ODD_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_63__TX_DCOC_RES_I_EVEN_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_63__TX_DCOC_RES_Q_EVEN_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_63__TX_DCOC_RES_I_ODD_63___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_63__TX_DCOC_RES_I_ODD_63___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_63__TX_DCOC_RES_Q_ODD_63___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_63__TX_DCOC_RES_Q_ODD_63___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_63__TX_DCOC_RES_I_EVEN_63___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_63__TX_DCOC_RES_I_EVEN_63___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_63__TX_DCOC_RES_Q_EVEN_63___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_63__TX_DCOC_RES_Q_EVEN_63___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_63___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_63___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_64 (0x005FD900) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_64___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_64___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_64__TX_DCOC_RES_I_ODD_64___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_64__TX_DCOC_RES_Q_ODD_64___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_64__TX_DCOC_RES_I_EVEN_64___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_64__TX_DCOC_RES_Q_EVEN_64___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_64__TX_DCOC_RES_I_ODD_64___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_64__TX_DCOC_RES_I_ODD_64___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_64__TX_DCOC_RES_Q_ODD_64___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_64__TX_DCOC_RES_Q_ODD_64___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_64__TX_DCOC_RES_I_EVEN_64___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_64__TX_DCOC_RES_I_EVEN_64___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_64__TX_DCOC_RES_Q_EVEN_64___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_64__TX_DCOC_RES_Q_EVEN_64___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_64___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_64___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_65 (0x005FD904) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_65___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_65___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_65__TX_DCOC_RES_I_ODD_65___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_65__TX_DCOC_RES_Q_ODD_65___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_65__TX_DCOC_RES_I_EVEN_65___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_65__TX_DCOC_RES_Q_EVEN_65___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_65__TX_DCOC_RES_I_ODD_65___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_65__TX_DCOC_RES_I_ODD_65___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_65__TX_DCOC_RES_Q_ODD_65___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_65__TX_DCOC_RES_Q_ODD_65___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_65__TX_DCOC_RES_I_EVEN_65___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_65__TX_DCOC_RES_I_EVEN_65___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_65__TX_DCOC_RES_Q_EVEN_65___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_65__TX_DCOC_RES_Q_EVEN_65___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_65___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_65___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_66 (0x005FD908) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_66___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_66___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_66__TX_DCOC_RES_I_ODD_66___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_66__TX_DCOC_RES_Q_ODD_66___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_66__TX_DCOC_RES_I_EVEN_66___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_66__TX_DCOC_RES_Q_EVEN_66___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_66__TX_DCOC_RES_I_ODD_66___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_66__TX_DCOC_RES_I_ODD_66___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_66__TX_DCOC_RES_Q_ODD_66___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_66__TX_DCOC_RES_Q_ODD_66___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_66__TX_DCOC_RES_I_EVEN_66___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_66__TX_DCOC_RES_I_EVEN_66___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_66__TX_DCOC_RES_Q_EVEN_66___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_66__TX_DCOC_RES_Q_EVEN_66___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_66___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_66___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_67 (0x005FD90C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_67___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_67___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_67__TX_DCOC_RES_I_ODD_67___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_67__TX_DCOC_RES_Q_ODD_67___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_67__TX_DCOC_RES_I_EVEN_67___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_67__TX_DCOC_RES_Q_EVEN_67___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_67__TX_DCOC_RES_I_ODD_67___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_67__TX_DCOC_RES_I_ODD_67___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_67__TX_DCOC_RES_Q_ODD_67___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_67__TX_DCOC_RES_Q_ODD_67___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_67__TX_DCOC_RES_I_EVEN_67___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_67__TX_DCOC_RES_I_EVEN_67___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_67__TX_DCOC_RES_Q_EVEN_67___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_67__TX_DCOC_RES_Q_EVEN_67___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_67___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_67___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_68 (0x005FD910) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_68___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_68___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_68__TX_DCOC_RES_I_ODD_68___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_68__TX_DCOC_RES_Q_ODD_68___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_68__TX_DCOC_RES_I_EVEN_68___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_68__TX_DCOC_RES_Q_EVEN_68___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_68__TX_DCOC_RES_I_ODD_68___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_68__TX_DCOC_RES_I_ODD_68___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_68__TX_DCOC_RES_Q_ODD_68___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_68__TX_DCOC_RES_Q_ODD_68___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_68__TX_DCOC_RES_I_EVEN_68___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_68__TX_DCOC_RES_I_EVEN_68___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_68__TX_DCOC_RES_Q_EVEN_68___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_68__TX_DCOC_RES_Q_EVEN_68___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_68___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_68___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_69 (0x005FD914) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_69___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_69___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_69__TX_DCOC_RES_I_ODD_69___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_69__TX_DCOC_RES_Q_ODD_69___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_69__TX_DCOC_RES_I_EVEN_69___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_69__TX_DCOC_RES_Q_EVEN_69___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_69__TX_DCOC_RES_I_ODD_69___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_69__TX_DCOC_RES_I_ODD_69___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_69__TX_DCOC_RES_Q_ODD_69___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_69__TX_DCOC_RES_Q_ODD_69___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_69__TX_DCOC_RES_I_EVEN_69___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_69__TX_DCOC_RES_I_EVEN_69___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_69__TX_DCOC_RES_Q_EVEN_69___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_69__TX_DCOC_RES_Q_EVEN_69___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_69___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_69___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_70 (0x005FD918) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_70___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_70___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_70__TX_DCOC_RES_I_ODD_70___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_70__TX_DCOC_RES_Q_ODD_70___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_70__TX_DCOC_RES_I_EVEN_70___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_70__TX_DCOC_RES_Q_EVEN_70___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_70__TX_DCOC_RES_I_ODD_70___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_70__TX_DCOC_RES_I_ODD_70___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_70__TX_DCOC_RES_Q_ODD_70___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_70__TX_DCOC_RES_Q_ODD_70___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_70__TX_DCOC_RES_I_EVEN_70___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_70__TX_DCOC_RES_I_EVEN_70___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_70__TX_DCOC_RES_Q_EVEN_70___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_70__TX_DCOC_RES_Q_EVEN_70___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_70___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_70___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_71 (0x005FD91C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_71___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_71___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_71__TX_DCOC_RES_I_ODD_71___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_71__TX_DCOC_RES_Q_ODD_71___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_71__TX_DCOC_RES_I_EVEN_71___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_71__TX_DCOC_RES_Q_EVEN_71___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_71__TX_DCOC_RES_I_ODD_71___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_71__TX_DCOC_RES_I_ODD_71___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_71__TX_DCOC_RES_Q_ODD_71___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_71__TX_DCOC_RES_Q_ODD_71___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_71__TX_DCOC_RES_I_EVEN_71___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_71__TX_DCOC_RES_I_EVEN_71___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_71__TX_DCOC_RES_Q_EVEN_71___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_71__TX_DCOC_RES_Q_EVEN_71___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_71___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_71___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_72 (0x005FD920) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_72___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_72___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_72__TX_DCOC_RES_I_ODD_72___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_72__TX_DCOC_RES_Q_ODD_72___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_72__TX_DCOC_RES_I_EVEN_72___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_72__TX_DCOC_RES_Q_EVEN_72___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_72__TX_DCOC_RES_I_ODD_72___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_72__TX_DCOC_RES_I_ODD_72___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_72__TX_DCOC_RES_Q_ODD_72___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_72__TX_DCOC_RES_Q_ODD_72___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_72__TX_DCOC_RES_I_EVEN_72___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_72__TX_DCOC_RES_I_EVEN_72___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_72__TX_DCOC_RES_Q_EVEN_72___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_72__TX_DCOC_RES_Q_EVEN_72___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_72___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_72___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_73 (0x005FD924) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_73___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_73___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_73__TX_DCOC_RES_I_ODD_73___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_73__TX_DCOC_RES_Q_ODD_73___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_73__TX_DCOC_RES_I_EVEN_73___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_73__TX_DCOC_RES_Q_EVEN_73___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_73__TX_DCOC_RES_I_ODD_73___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_73__TX_DCOC_RES_I_ODD_73___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_73__TX_DCOC_RES_Q_ODD_73___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_73__TX_DCOC_RES_Q_ODD_73___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_73__TX_DCOC_RES_I_EVEN_73___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_73__TX_DCOC_RES_I_EVEN_73___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_73__TX_DCOC_RES_Q_EVEN_73___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_73__TX_DCOC_RES_Q_EVEN_73___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_73___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_73___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_74 (0x005FD928) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_74___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_74___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_74__TX_DCOC_RES_I_ODD_74___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_74__TX_DCOC_RES_Q_ODD_74___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_74__TX_DCOC_RES_I_EVEN_74___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_74__TX_DCOC_RES_Q_EVEN_74___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_74__TX_DCOC_RES_I_ODD_74___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_74__TX_DCOC_RES_I_ODD_74___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_74__TX_DCOC_RES_Q_ODD_74___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_74__TX_DCOC_RES_Q_ODD_74___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_74__TX_DCOC_RES_I_EVEN_74___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_74__TX_DCOC_RES_I_EVEN_74___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_74__TX_DCOC_RES_Q_EVEN_74___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_74__TX_DCOC_RES_Q_EVEN_74___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_74___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_74___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_75 (0x005FD92C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_75___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_75___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_75__TX_DCOC_RES_I_ODD_75___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_75__TX_DCOC_RES_Q_ODD_75___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_75__TX_DCOC_RES_I_EVEN_75___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_75__TX_DCOC_RES_Q_EVEN_75___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_75__TX_DCOC_RES_I_ODD_75___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_75__TX_DCOC_RES_I_ODD_75___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_75__TX_DCOC_RES_Q_ODD_75___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_75__TX_DCOC_RES_Q_ODD_75___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_75__TX_DCOC_RES_I_EVEN_75___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_75__TX_DCOC_RES_I_EVEN_75___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_75__TX_DCOC_RES_Q_EVEN_75___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_75__TX_DCOC_RES_Q_EVEN_75___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_75___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_75___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_76 (0x005FD930) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_76___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_76___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_76__TX_DCOC_RES_I_ODD_76___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_76__TX_DCOC_RES_Q_ODD_76___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_76__TX_DCOC_RES_I_EVEN_76___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_76__TX_DCOC_RES_Q_EVEN_76___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_76__TX_DCOC_RES_I_ODD_76___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_76__TX_DCOC_RES_I_ODD_76___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_76__TX_DCOC_RES_Q_ODD_76___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_76__TX_DCOC_RES_Q_ODD_76___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_76__TX_DCOC_RES_I_EVEN_76___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_76__TX_DCOC_RES_I_EVEN_76___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_76__TX_DCOC_RES_Q_EVEN_76___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_76__TX_DCOC_RES_Q_EVEN_76___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_76___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_76___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_77 (0x005FD934) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_77___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_77___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_77__TX_DCOC_RES_I_ODD_77___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_77__TX_DCOC_RES_Q_ODD_77___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_77__TX_DCOC_RES_I_EVEN_77___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_77__TX_DCOC_RES_Q_EVEN_77___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_77__TX_DCOC_RES_I_ODD_77___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_77__TX_DCOC_RES_I_ODD_77___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_77__TX_DCOC_RES_Q_ODD_77___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_77__TX_DCOC_RES_Q_ODD_77___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_77__TX_DCOC_RES_I_EVEN_77___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_77__TX_DCOC_RES_I_EVEN_77___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_77__TX_DCOC_RES_Q_EVEN_77___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_77__TX_DCOC_RES_Q_EVEN_77___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_77___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_77___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_78 (0x005FD938) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_78___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_78___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_78__TX_DCOC_RES_I_ODD_78___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_78__TX_DCOC_RES_Q_ODD_78___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_78__TX_DCOC_RES_I_EVEN_78___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_78__TX_DCOC_RES_Q_EVEN_78___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_78__TX_DCOC_RES_I_ODD_78___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_78__TX_DCOC_RES_I_ODD_78___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_78__TX_DCOC_RES_Q_ODD_78___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_78__TX_DCOC_RES_Q_ODD_78___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_78__TX_DCOC_RES_I_EVEN_78___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_78__TX_DCOC_RES_I_EVEN_78___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_78__TX_DCOC_RES_Q_EVEN_78___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_78__TX_DCOC_RES_Q_EVEN_78___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_78___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_78___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_79 (0x005FD93C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_79___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_79___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_79__TX_DCOC_RES_I_ODD_79___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_79__TX_DCOC_RES_Q_ODD_79___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_79__TX_DCOC_RES_I_EVEN_79___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_79__TX_DCOC_RES_Q_EVEN_79___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_79__TX_DCOC_RES_I_ODD_79___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_79__TX_DCOC_RES_I_ODD_79___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_79__TX_DCOC_RES_Q_ODD_79___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_79__TX_DCOC_RES_Q_ODD_79___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_79__TX_DCOC_RES_I_EVEN_79___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_79__TX_DCOC_RES_I_EVEN_79___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_79__TX_DCOC_RES_Q_EVEN_79___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_79__TX_DCOC_RES_Q_EVEN_79___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_79___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_79___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_80 (0x005FD940) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_80___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_80___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_80__TX_DCOC_RES_I_ODD_80___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_80__TX_DCOC_RES_Q_ODD_80___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_80__TX_DCOC_RES_I_EVEN_80___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_80__TX_DCOC_RES_Q_EVEN_80___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_80__TX_DCOC_RES_I_ODD_80___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_80__TX_DCOC_RES_I_ODD_80___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_80__TX_DCOC_RES_Q_ODD_80___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_80__TX_DCOC_RES_Q_ODD_80___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_80__TX_DCOC_RES_I_EVEN_80___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_80__TX_DCOC_RES_I_EVEN_80___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_80__TX_DCOC_RES_Q_EVEN_80___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_80__TX_DCOC_RES_Q_EVEN_80___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_80___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_80___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_81 (0x005FD944) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_81___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_81___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_81__TX_DCOC_RES_I_ODD_81___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_81__TX_DCOC_RES_Q_ODD_81___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_81__TX_DCOC_RES_I_EVEN_81___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_81__TX_DCOC_RES_Q_EVEN_81___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_81__TX_DCOC_RES_I_ODD_81___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_81__TX_DCOC_RES_I_ODD_81___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_81__TX_DCOC_RES_Q_ODD_81___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_81__TX_DCOC_RES_Q_ODD_81___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_81__TX_DCOC_RES_I_EVEN_81___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_81__TX_DCOC_RES_I_EVEN_81___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_81__TX_DCOC_RES_Q_EVEN_81___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_81__TX_DCOC_RES_Q_EVEN_81___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_81___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_81___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_82 (0x005FD948) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_82___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_82___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_82__TX_DCOC_RES_I_ODD_82___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_82__TX_DCOC_RES_Q_ODD_82___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_82__TX_DCOC_RES_I_EVEN_82___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_82__TX_DCOC_RES_Q_EVEN_82___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_82__TX_DCOC_RES_I_ODD_82___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_82__TX_DCOC_RES_I_ODD_82___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_82__TX_DCOC_RES_Q_ODD_82___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_82__TX_DCOC_RES_Q_ODD_82___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_82__TX_DCOC_RES_I_EVEN_82___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_82__TX_DCOC_RES_I_EVEN_82___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_82__TX_DCOC_RES_Q_EVEN_82___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_82__TX_DCOC_RES_Q_EVEN_82___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_82___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_82___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_83 (0x005FD94C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_83___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_83___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_83__TX_DCOC_RES_I_ODD_83___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_83__TX_DCOC_RES_Q_ODD_83___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_83__TX_DCOC_RES_I_EVEN_83___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_83__TX_DCOC_RES_Q_EVEN_83___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_83__TX_DCOC_RES_I_ODD_83___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_83__TX_DCOC_RES_I_ODD_83___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_83__TX_DCOC_RES_Q_ODD_83___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_83__TX_DCOC_RES_Q_ODD_83___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_83__TX_DCOC_RES_I_EVEN_83___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_83__TX_DCOC_RES_I_EVEN_83___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_83__TX_DCOC_RES_Q_EVEN_83___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_83__TX_DCOC_RES_Q_EVEN_83___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_83___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_83___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_84 (0x005FD950) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_84___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_84___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_84__TX_DCOC_RES_I_ODD_84___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_84__TX_DCOC_RES_Q_ODD_84___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_84__TX_DCOC_RES_I_EVEN_84___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_84__TX_DCOC_RES_Q_EVEN_84___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_84__TX_DCOC_RES_I_ODD_84___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_84__TX_DCOC_RES_I_ODD_84___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_84__TX_DCOC_RES_Q_ODD_84___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_84__TX_DCOC_RES_Q_ODD_84___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_84__TX_DCOC_RES_I_EVEN_84___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_84__TX_DCOC_RES_I_EVEN_84___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_84__TX_DCOC_RES_Q_EVEN_84___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_84__TX_DCOC_RES_Q_EVEN_84___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_84___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_84___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_85 (0x005FD954) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_85___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_85___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_85__TX_DCOC_RES_I_ODD_85___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_85__TX_DCOC_RES_Q_ODD_85___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_85__TX_DCOC_RES_I_EVEN_85___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_85__TX_DCOC_RES_Q_EVEN_85___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_85__TX_DCOC_RES_I_ODD_85___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_85__TX_DCOC_RES_I_ODD_85___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_85__TX_DCOC_RES_Q_ODD_85___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_85__TX_DCOC_RES_Q_ODD_85___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_85__TX_DCOC_RES_I_EVEN_85___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_85__TX_DCOC_RES_I_EVEN_85___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_85__TX_DCOC_RES_Q_EVEN_85___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_85__TX_DCOC_RES_Q_EVEN_85___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_85___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_85___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_86 (0x005FD958) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_86___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_86___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_86__TX_DCOC_RES_I_ODD_86___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_86__TX_DCOC_RES_Q_ODD_86___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_86__TX_DCOC_RES_I_EVEN_86___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_86__TX_DCOC_RES_Q_EVEN_86___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_86__TX_DCOC_RES_I_ODD_86___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_86__TX_DCOC_RES_I_ODD_86___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_86__TX_DCOC_RES_Q_ODD_86___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_86__TX_DCOC_RES_Q_ODD_86___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_86__TX_DCOC_RES_I_EVEN_86___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_86__TX_DCOC_RES_I_EVEN_86___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_86__TX_DCOC_RES_Q_EVEN_86___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_86__TX_DCOC_RES_Q_EVEN_86___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_86___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_86___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_87 (0x005FD95C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_87___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_87___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_87__TX_DCOC_RES_I_ODD_87___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_87__TX_DCOC_RES_Q_ODD_87___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_87__TX_DCOC_RES_I_EVEN_87___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_87__TX_DCOC_RES_Q_EVEN_87___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_87__TX_DCOC_RES_I_ODD_87___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_87__TX_DCOC_RES_I_ODD_87___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_87__TX_DCOC_RES_Q_ODD_87___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_87__TX_DCOC_RES_Q_ODD_87___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_87__TX_DCOC_RES_I_EVEN_87___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_87__TX_DCOC_RES_I_EVEN_87___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_87__TX_DCOC_RES_Q_EVEN_87___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_87__TX_DCOC_RES_Q_EVEN_87___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_87___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_87___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_88 (0x005FD960) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_88___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_88___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_88__TX_DCOC_RES_I_ODD_88___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_88__TX_DCOC_RES_Q_ODD_88___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_88__TX_DCOC_RES_I_EVEN_88___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_88__TX_DCOC_RES_Q_EVEN_88___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_88__TX_DCOC_RES_I_ODD_88___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_88__TX_DCOC_RES_I_ODD_88___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_88__TX_DCOC_RES_Q_ODD_88___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_88__TX_DCOC_RES_Q_ODD_88___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_88__TX_DCOC_RES_I_EVEN_88___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_88__TX_DCOC_RES_I_EVEN_88___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_88__TX_DCOC_RES_Q_EVEN_88___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_88__TX_DCOC_RES_Q_EVEN_88___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_88___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_88___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_89 (0x005FD964) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_89___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_89___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_89__TX_DCOC_RES_I_ODD_89___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_89__TX_DCOC_RES_Q_ODD_89___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_89__TX_DCOC_RES_I_EVEN_89___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_89__TX_DCOC_RES_Q_EVEN_89___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_89__TX_DCOC_RES_I_ODD_89___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_89__TX_DCOC_RES_I_ODD_89___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_89__TX_DCOC_RES_Q_ODD_89___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_89__TX_DCOC_RES_Q_ODD_89___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_89__TX_DCOC_RES_I_EVEN_89___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_89__TX_DCOC_RES_I_EVEN_89___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_89__TX_DCOC_RES_Q_EVEN_89___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_89__TX_DCOC_RES_Q_EVEN_89___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_89___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_89___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_90 (0x005FD968) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_90___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_90___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_90__TX_DCOC_RES_I_ODD_90___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_90__TX_DCOC_RES_Q_ODD_90___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_90__TX_DCOC_RES_I_EVEN_90___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_90__TX_DCOC_RES_Q_EVEN_90___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_90__TX_DCOC_RES_I_ODD_90___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_90__TX_DCOC_RES_I_ODD_90___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_90__TX_DCOC_RES_Q_ODD_90___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_90__TX_DCOC_RES_Q_ODD_90___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_90__TX_DCOC_RES_I_EVEN_90___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_90__TX_DCOC_RES_I_EVEN_90___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_90__TX_DCOC_RES_Q_EVEN_90___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_90__TX_DCOC_RES_Q_EVEN_90___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_90___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_90___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_91 (0x005FD96C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_91___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_91___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_91__TX_DCOC_RES_I_ODD_91___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_91__TX_DCOC_RES_Q_ODD_91___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_91__TX_DCOC_RES_I_EVEN_91___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_91__TX_DCOC_RES_Q_EVEN_91___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_91__TX_DCOC_RES_I_ODD_91___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_91__TX_DCOC_RES_I_ODD_91___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_91__TX_DCOC_RES_Q_ODD_91___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_91__TX_DCOC_RES_Q_ODD_91___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_91__TX_DCOC_RES_I_EVEN_91___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_91__TX_DCOC_RES_I_EVEN_91___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_91__TX_DCOC_RES_Q_EVEN_91___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_91__TX_DCOC_RES_Q_EVEN_91___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_91___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_91___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_92 (0x005FD970) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_92___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_92___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_92__TX_DCOC_RES_I_ODD_92___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_92__TX_DCOC_RES_Q_ODD_92___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_92__TX_DCOC_RES_I_EVEN_92___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_92__TX_DCOC_RES_Q_EVEN_92___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_92__TX_DCOC_RES_I_ODD_92___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_92__TX_DCOC_RES_I_ODD_92___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_92__TX_DCOC_RES_Q_ODD_92___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_92__TX_DCOC_RES_Q_ODD_92___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_92__TX_DCOC_RES_I_EVEN_92___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_92__TX_DCOC_RES_I_EVEN_92___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_92__TX_DCOC_RES_Q_EVEN_92___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_92__TX_DCOC_RES_Q_EVEN_92___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_92___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_92___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_93 (0x005FD974) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_93___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_93___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_93__TX_DCOC_RES_I_ODD_93___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_93__TX_DCOC_RES_Q_ODD_93___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_93__TX_DCOC_RES_I_EVEN_93___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_93__TX_DCOC_RES_Q_EVEN_93___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_93__TX_DCOC_RES_I_ODD_93___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_93__TX_DCOC_RES_I_ODD_93___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_93__TX_DCOC_RES_Q_ODD_93___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_93__TX_DCOC_RES_Q_ODD_93___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_93__TX_DCOC_RES_I_EVEN_93___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_93__TX_DCOC_RES_I_EVEN_93___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_93__TX_DCOC_RES_Q_EVEN_93___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_93__TX_DCOC_RES_Q_EVEN_93___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_93___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_93___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_94 (0x005FD978) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_94___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_94___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_94__TX_DCOC_RES_I_ODD_94___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_94__TX_DCOC_RES_Q_ODD_94___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_94__TX_DCOC_RES_I_EVEN_94___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_94__TX_DCOC_RES_Q_EVEN_94___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_94__TX_DCOC_RES_I_ODD_94___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_94__TX_DCOC_RES_I_ODD_94___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_94__TX_DCOC_RES_Q_ODD_94___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_94__TX_DCOC_RES_Q_ODD_94___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_94__TX_DCOC_RES_I_EVEN_94___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_94__TX_DCOC_RES_I_EVEN_94___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_94__TX_DCOC_RES_Q_EVEN_94___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_94__TX_DCOC_RES_Q_EVEN_94___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_94___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_94___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_95 (0x005FD97C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_95___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_95___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_95__TX_DCOC_RES_I_ODD_95___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_95__TX_DCOC_RES_Q_ODD_95___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_95__TX_DCOC_RES_I_EVEN_95___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_95__TX_DCOC_RES_Q_EVEN_95___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_95__TX_DCOC_RES_I_ODD_95___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_95__TX_DCOC_RES_I_ODD_95___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_95__TX_DCOC_RES_Q_ODD_95___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_95__TX_DCOC_RES_Q_ODD_95___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_95__TX_DCOC_RES_I_EVEN_95___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_95__TX_DCOC_RES_I_EVEN_95___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_95__TX_DCOC_RES_Q_EVEN_95___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_95__TX_DCOC_RES_Q_EVEN_95___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_95___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_95___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_96 (0x005FD980) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_96___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_96___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_96__TX_DCOC_RES_I_ODD_96___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_96__TX_DCOC_RES_Q_ODD_96___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_96__TX_DCOC_RES_I_EVEN_96___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_96__TX_DCOC_RES_Q_EVEN_96___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_96__TX_DCOC_RES_I_ODD_96___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_96__TX_DCOC_RES_I_ODD_96___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_96__TX_DCOC_RES_Q_ODD_96___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_96__TX_DCOC_RES_Q_ODD_96___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_96__TX_DCOC_RES_I_EVEN_96___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_96__TX_DCOC_RES_I_EVEN_96___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_96__TX_DCOC_RES_Q_EVEN_96___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_96__TX_DCOC_RES_Q_EVEN_96___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_96___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_96___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_97 (0x005FD984) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_97___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_97___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_97__TX_DCOC_RES_I_ODD_97___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_97__TX_DCOC_RES_Q_ODD_97___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_97__TX_DCOC_RES_I_EVEN_97___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_97__TX_DCOC_RES_Q_EVEN_97___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_97__TX_DCOC_RES_I_ODD_97___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_97__TX_DCOC_RES_I_ODD_97___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_97__TX_DCOC_RES_Q_ODD_97___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_97__TX_DCOC_RES_Q_ODD_97___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_97__TX_DCOC_RES_I_EVEN_97___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_97__TX_DCOC_RES_I_EVEN_97___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_97__TX_DCOC_RES_Q_EVEN_97___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_97__TX_DCOC_RES_Q_EVEN_97___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_97___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_97___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_98 (0x005FD988) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_98___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_98___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_98__TX_DCOC_RES_I_ODD_98___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_98__TX_DCOC_RES_Q_ODD_98___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_98__TX_DCOC_RES_I_EVEN_98___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_98__TX_DCOC_RES_Q_EVEN_98___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_98__TX_DCOC_RES_I_ODD_98___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_98__TX_DCOC_RES_I_ODD_98___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_98__TX_DCOC_RES_Q_ODD_98___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_98__TX_DCOC_RES_Q_ODD_98___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_98__TX_DCOC_RES_I_EVEN_98___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_98__TX_DCOC_RES_I_EVEN_98___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_98__TX_DCOC_RES_Q_EVEN_98___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_98__TX_DCOC_RES_Q_EVEN_98___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_98___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_98___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_99 (0x005FD98C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_99___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_99___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_99__TX_DCOC_RES_I_ODD_99___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_99__TX_DCOC_RES_Q_ODD_99___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_99__TX_DCOC_RES_I_EVEN_99___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_99__TX_DCOC_RES_Q_EVEN_99___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_99__TX_DCOC_RES_I_ODD_99___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_99__TX_DCOC_RES_I_ODD_99___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_99__TX_DCOC_RES_Q_ODD_99___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_99__TX_DCOC_RES_Q_ODD_99___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_99__TX_DCOC_RES_I_EVEN_99___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_99__TX_DCOC_RES_I_EVEN_99___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_99__TX_DCOC_RES_Q_EVEN_99___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_99__TX_DCOC_RES_Q_EVEN_99___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_99___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_99___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_100 (0x005FD990) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_100___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_100___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_100__TX_DCOC_RES_I_ODD_100___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_100__TX_DCOC_RES_Q_ODD_100___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_100__TX_DCOC_RES_I_EVEN_100___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_100__TX_DCOC_RES_Q_EVEN_100___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_100__TX_DCOC_RES_I_ODD_100___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_100__TX_DCOC_RES_I_ODD_100___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_100__TX_DCOC_RES_Q_ODD_100___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_100__TX_DCOC_RES_Q_ODD_100___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_100__TX_DCOC_RES_I_EVEN_100___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_100__TX_DCOC_RES_I_EVEN_100___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_100__TX_DCOC_RES_Q_EVEN_100___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_100__TX_DCOC_RES_Q_EVEN_100___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_100___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_100___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_101 (0x005FD994) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_101___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_101___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_101__TX_DCOC_RES_I_ODD_101___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_101__TX_DCOC_RES_Q_ODD_101___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_101__TX_DCOC_RES_I_EVEN_101___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_101__TX_DCOC_RES_Q_EVEN_101___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_101__TX_DCOC_RES_I_ODD_101___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_101__TX_DCOC_RES_I_ODD_101___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_101__TX_DCOC_RES_Q_ODD_101___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_101__TX_DCOC_RES_Q_ODD_101___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_101__TX_DCOC_RES_I_EVEN_101___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_101__TX_DCOC_RES_I_EVEN_101___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_101__TX_DCOC_RES_Q_EVEN_101___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_101__TX_DCOC_RES_Q_EVEN_101___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_101___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_101___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_102 (0x005FD998) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_102___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_102___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_102__TX_DCOC_RES_I_ODD_102___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_102__TX_DCOC_RES_Q_ODD_102___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_102__TX_DCOC_RES_I_EVEN_102___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_102__TX_DCOC_RES_Q_EVEN_102___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_102__TX_DCOC_RES_I_ODD_102___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_102__TX_DCOC_RES_I_ODD_102___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_102__TX_DCOC_RES_Q_ODD_102___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_102__TX_DCOC_RES_Q_ODD_102___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_102__TX_DCOC_RES_I_EVEN_102___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_102__TX_DCOC_RES_I_EVEN_102___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_102__TX_DCOC_RES_Q_EVEN_102___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_102__TX_DCOC_RES_Q_EVEN_102___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_102___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_102___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_103 (0x005FD99C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_103___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_103___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_103__TX_DCOC_RES_I_ODD_103___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_103__TX_DCOC_RES_Q_ODD_103___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_103__TX_DCOC_RES_I_EVEN_103___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_103__TX_DCOC_RES_Q_EVEN_103___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_103__TX_DCOC_RES_I_ODD_103___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_103__TX_DCOC_RES_I_ODD_103___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_103__TX_DCOC_RES_Q_ODD_103___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_103__TX_DCOC_RES_Q_ODD_103___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_103__TX_DCOC_RES_I_EVEN_103___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_103__TX_DCOC_RES_I_EVEN_103___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_103__TX_DCOC_RES_Q_EVEN_103___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_103__TX_DCOC_RES_Q_EVEN_103___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_103___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_103___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_104 (0x005FD9A0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_104___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_104___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_104__TX_DCOC_RES_I_ODD_104___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_104__TX_DCOC_RES_Q_ODD_104___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_104__TX_DCOC_RES_I_EVEN_104___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_104__TX_DCOC_RES_Q_EVEN_104___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_104__TX_DCOC_RES_I_ODD_104___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_104__TX_DCOC_RES_I_ODD_104___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_104__TX_DCOC_RES_Q_ODD_104___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_104__TX_DCOC_RES_Q_ODD_104___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_104__TX_DCOC_RES_I_EVEN_104___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_104__TX_DCOC_RES_I_EVEN_104___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_104__TX_DCOC_RES_Q_EVEN_104___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_104__TX_DCOC_RES_Q_EVEN_104___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_104___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_104___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_105 (0x005FD9A4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_105___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_105___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_105__TX_DCOC_RES_I_ODD_105___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_105__TX_DCOC_RES_Q_ODD_105___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_105__TX_DCOC_RES_I_EVEN_105___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_105__TX_DCOC_RES_Q_EVEN_105___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_105__TX_DCOC_RES_I_ODD_105___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_105__TX_DCOC_RES_I_ODD_105___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_105__TX_DCOC_RES_Q_ODD_105___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_105__TX_DCOC_RES_Q_ODD_105___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_105__TX_DCOC_RES_I_EVEN_105___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_105__TX_DCOC_RES_I_EVEN_105___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_105__TX_DCOC_RES_Q_EVEN_105___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_105__TX_DCOC_RES_Q_EVEN_105___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_105___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_105___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_106 (0x005FD9A8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_106___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_106___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_106__TX_DCOC_RES_I_ODD_106___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_106__TX_DCOC_RES_Q_ODD_106___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_106__TX_DCOC_RES_I_EVEN_106___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_106__TX_DCOC_RES_Q_EVEN_106___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_106__TX_DCOC_RES_I_ODD_106___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_106__TX_DCOC_RES_I_ODD_106___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_106__TX_DCOC_RES_Q_ODD_106___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_106__TX_DCOC_RES_Q_ODD_106___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_106__TX_DCOC_RES_I_EVEN_106___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_106__TX_DCOC_RES_I_EVEN_106___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_106__TX_DCOC_RES_Q_EVEN_106___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_106__TX_DCOC_RES_Q_EVEN_106___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_106___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_106___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_107 (0x005FD9AC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_107___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_107___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_107__TX_DCOC_RES_I_ODD_107___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_107__TX_DCOC_RES_Q_ODD_107___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_107__TX_DCOC_RES_I_EVEN_107___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_107__TX_DCOC_RES_Q_EVEN_107___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_107__TX_DCOC_RES_I_ODD_107___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_107__TX_DCOC_RES_I_ODD_107___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_107__TX_DCOC_RES_Q_ODD_107___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_107__TX_DCOC_RES_Q_ODD_107___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_107__TX_DCOC_RES_I_EVEN_107___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_107__TX_DCOC_RES_I_EVEN_107___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_107__TX_DCOC_RES_Q_EVEN_107___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_107__TX_DCOC_RES_Q_EVEN_107___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_107___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_107___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_108 (0x005FD9B0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_108___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_108___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_108__TX_DCOC_RES_I_ODD_108___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_108__TX_DCOC_RES_Q_ODD_108___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_108__TX_DCOC_RES_I_EVEN_108___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_108__TX_DCOC_RES_Q_EVEN_108___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_108__TX_DCOC_RES_I_ODD_108___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_108__TX_DCOC_RES_I_ODD_108___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_108__TX_DCOC_RES_Q_ODD_108___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_108__TX_DCOC_RES_Q_ODD_108___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_108__TX_DCOC_RES_I_EVEN_108___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_108__TX_DCOC_RES_I_EVEN_108___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_108__TX_DCOC_RES_Q_EVEN_108___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_108__TX_DCOC_RES_Q_EVEN_108___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_108___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_108___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_109 (0x005FD9B4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_109___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_109___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_109__TX_DCOC_RES_I_ODD_109___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_109__TX_DCOC_RES_Q_ODD_109___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_109__TX_DCOC_RES_I_EVEN_109___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_109__TX_DCOC_RES_Q_EVEN_109___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_109__TX_DCOC_RES_I_ODD_109___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_109__TX_DCOC_RES_I_ODD_109___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_109__TX_DCOC_RES_Q_ODD_109___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_109__TX_DCOC_RES_Q_ODD_109___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_109__TX_DCOC_RES_I_EVEN_109___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_109__TX_DCOC_RES_I_EVEN_109___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_109__TX_DCOC_RES_Q_EVEN_109___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_109__TX_DCOC_RES_Q_EVEN_109___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_109___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_109___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_110 (0x005FD9B8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_110___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_110___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_110__TX_DCOC_RES_I_ODD_110___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_110__TX_DCOC_RES_Q_ODD_110___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_110__TX_DCOC_RES_I_EVEN_110___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_110__TX_DCOC_RES_Q_EVEN_110___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_110__TX_DCOC_RES_I_ODD_110___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_110__TX_DCOC_RES_I_ODD_110___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_110__TX_DCOC_RES_Q_ODD_110___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_110__TX_DCOC_RES_Q_ODD_110___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_110__TX_DCOC_RES_I_EVEN_110___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_110__TX_DCOC_RES_I_EVEN_110___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_110__TX_DCOC_RES_Q_EVEN_110___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_110__TX_DCOC_RES_Q_EVEN_110___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_110___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_110___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_111 (0x005FD9BC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_111___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_111___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_111__TX_DCOC_RES_I_ODD_111___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_111__TX_DCOC_RES_Q_ODD_111___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_111__TX_DCOC_RES_I_EVEN_111___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_111__TX_DCOC_RES_Q_EVEN_111___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_111__TX_DCOC_RES_I_ODD_111___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_111__TX_DCOC_RES_I_ODD_111___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_111__TX_DCOC_RES_Q_ODD_111___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_111__TX_DCOC_RES_Q_ODD_111___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_111__TX_DCOC_RES_I_EVEN_111___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_111__TX_DCOC_RES_I_EVEN_111___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_111__TX_DCOC_RES_Q_EVEN_111___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_111__TX_DCOC_RES_Q_EVEN_111___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_111___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_111___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_112 (0x005FD9C0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_112___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_112___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_112__TX_DCOC_RES_I_ODD_112___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_112__TX_DCOC_RES_Q_ODD_112___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_112__TX_DCOC_RES_I_EVEN_112___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_112__TX_DCOC_RES_Q_EVEN_112___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_112__TX_DCOC_RES_I_ODD_112___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_112__TX_DCOC_RES_I_ODD_112___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_112__TX_DCOC_RES_Q_ODD_112___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_112__TX_DCOC_RES_Q_ODD_112___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_112__TX_DCOC_RES_I_EVEN_112___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_112__TX_DCOC_RES_I_EVEN_112___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_112__TX_DCOC_RES_Q_EVEN_112___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_112__TX_DCOC_RES_Q_EVEN_112___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_112___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_112___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_113 (0x005FD9C4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_113___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_113___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_113__TX_DCOC_RES_I_ODD_113___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_113__TX_DCOC_RES_Q_ODD_113___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_113__TX_DCOC_RES_I_EVEN_113___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_113__TX_DCOC_RES_Q_EVEN_113___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_113__TX_DCOC_RES_I_ODD_113___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_113__TX_DCOC_RES_I_ODD_113___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_113__TX_DCOC_RES_Q_ODD_113___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_113__TX_DCOC_RES_Q_ODD_113___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_113__TX_DCOC_RES_I_EVEN_113___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_113__TX_DCOC_RES_I_EVEN_113___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_113__TX_DCOC_RES_Q_EVEN_113___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_113__TX_DCOC_RES_Q_EVEN_113___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_113___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_113___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_114 (0x005FD9C8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_114___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_114___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_114__TX_DCOC_RES_I_ODD_114___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_114__TX_DCOC_RES_Q_ODD_114___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_114__TX_DCOC_RES_I_EVEN_114___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_114__TX_DCOC_RES_Q_EVEN_114___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_114__TX_DCOC_RES_I_ODD_114___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_114__TX_DCOC_RES_I_ODD_114___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_114__TX_DCOC_RES_Q_ODD_114___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_114__TX_DCOC_RES_Q_ODD_114___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_114__TX_DCOC_RES_I_EVEN_114___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_114__TX_DCOC_RES_I_EVEN_114___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_114__TX_DCOC_RES_Q_EVEN_114___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_114__TX_DCOC_RES_Q_EVEN_114___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_114___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_114___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_115 (0x005FD9CC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_115___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_115___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_115__TX_DCOC_RES_I_ODD_115___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_115__TX_DCOC_RES_Q_ODD_115___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_115__TX_DCOC_RES_I_EVEN_115___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_115__TX_DCOC_RES_Q_EVEN_115___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_115__TX_DCOC_RES_I_ODD_115___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_115__TX_DCOC_RES_I_ODD_115___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_115__TX_DCOC_RES_Q_ODD_115___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_115__TX_DCOC_RES_Q_ODD_115___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_115__TX_DCOC_RES_I_EVEN_115___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_115__TX_DCOC_RES_I_EVEN_115___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_115__TX_DCOC_RES_Q_EVEN_115___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_115__TX_DCOC_RES_Q_EVEN_115___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_115___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_115___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_116 (0x005FD9D0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_116___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_116___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_116__TX_DCOC_RES_I_ODD_116___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_116__TX_DCOC_RES_Q_ODD_116___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_116__TX_DCOC_RES_I_EVEN_116___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_116__TX_DCOC_RES_Q_EVEN_116___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_116__TX_DCOC_RES_I_ODD_116___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_116__TX_DCOC_RES_I_ODD_116___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_116__TX_DCOC_RES_Q_ODD_116___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_116__TX_DCOC_RES_Q_ODD_116___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_116__TX_DCOC_RES_I_EVEN_116___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_116__TX_DCOC_RES_I_EVEN_116___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_116__TX_DCOC_RES_Q_EVEN_116___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_116__TX_DCOC_RES_Q_EVEN_116___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_116___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_116___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_117 (0x005FD9D4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_117___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_117___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_117__TX_DCOC_RES_I_ODD_117___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_117__TX_DCOC_RES_Q_ODD_117___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_117__TX_DCOC_RES_I_EVEN_117___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_117__TX_DCOC_RES_Q_EVEN_117___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_117__TX_DCOC_RES_I_ODD_117___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_117__TX_DCOC_RES_I_ODD_117___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_117__TX_DCOC_RES_Q_ODD_117___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_117__TX_DCOC_RES_Q_ODD_117___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_117__TX_DCOC_RES_I_EVEN_117___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_117__TX_DCOC_RES_I_EVEN_117___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_117__TX_DCOC_RES_Q_EVEN_117___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_117__TX_DCOC_RES_Q_EVEN_117___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_117___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_117___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_118 (0x005FD9D8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_118___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_118___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_118__TX_DCOC_RES_I_ODD_118___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_118__TX_DCOC_RES_Q_ODD_118___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_118__TX_DCOC_RES_I_EVEN_118___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_118__TX_DCOC_RES_Q_EVEN_118___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_118__TX_DCOC_RES_I_ODD_118___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_118__TX_DCOC_RES_I_ODD_118___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_118__TX_DCOC_RES_Q_ODD_118___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_118__TX_DCOC_RES_Q_ODD_118___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_118__TX_DCOC_RES_I_EVEN_118___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_118__TX_DCOC_RES_I_EVEN_118___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_118__TX_DCOC_RES_Q_EVEN_118___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_118__TX_DCOC_RES_Q_EVEN_118___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_118___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_118___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_119 (0x005FD9DC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_119___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_119___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_119__TX_DCOC_RES_I_ODD_119___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_119__TX_DCOC_RES_Q_ODD_119___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_119__TX_DCOC_RES_I_EVEN_119___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_119__TX_DCOC_RES_Q_EVEN_119___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_119__TX_DCOC_RES_I_ODD_119___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_119__TX_DCOC_RES_I_ODD_119___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_119__TX_DCOC_RES_Q_ODD_119___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_119__TX_DCOC_RES_Q_ODD_119___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_119__TX_DCOC_RES_I_EVEN_119___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_119__TX_DCOC_RES_I_EVEN_119___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_119__TX_DCOC_RES_Q_EVEN_119___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_119__TX_DCOC_RES_Q_EVEN_119___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_119___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_119___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_120 (0x005FD9E0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_120___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_120___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_120__TX_DCOC_RES_I_ODD_120___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_120__TX_DCOC_RES_Q_ODD_120___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_120__TX_DCOC_RES_I_EVEN_120___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_120__TX_DCOC_RES_Q_EVEN_120___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_120__TX_DCOC_RES_I_ODD_120___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_120__TX_DCOC_RES_I_ODD_120___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_120__TX_DCOC_RES_Q_ODD_120___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_120__TX_DCOC_RES_Q_ODD_120___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_120__TX_DCOC_RES_I_EVEN_120___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_120__TX_DCOC_RES_I_EVEN_120___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_120__TX_DCOC_RES_Q_EVEN_120___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_120__TX_DCOC_RES_Q_EVEN_120___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_120___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_120___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_121 (0x005FD9E4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_121___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_121___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_121__TX_DCOC_RES_I_ODD_121___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_121__TX_DCOC_RES_Q_ODD_121___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_121__TX_DCOC_RES_I_EVEN_121___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_121__TX_DCOC_RES_Q_EVEN_121___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_121__TX_DCOC_RES_I_ODD_121___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_121__TX_DCOC_RES_I_ODD_121___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_121__TX_DCOC_RES_Q_ODD_121___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_121__TX_DCOC_RES_Q_ODD_121___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_121__TX_DCOC_RES_I_EVEN_121___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_121__TX_DCOC_RES_I_EVEN_121___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_121__TX_DCOC_RES_Q_EVEN_121___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_121__TX_DCOC_RES_Q_EVEN_121___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_121___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_121___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_122 (0x005FD9E8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_122___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_122___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_122__TX_DCOC_RES_I_ODD_122___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_122__TX_DCOC_RES_Q_ODD_122___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_122__TX_DCOC_RES_I_EVEN_122___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_122__TX_DCOC_RES_Q_EVEN_122___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_122__TX_DCOC_RES_I_ODD_122___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_122__TX_DCOC_RES_I_ODD_122___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_122__TX_DCOC_RES_Q_ODD_122___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_122__TX_DCOC_RES_Q_ODD_122___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_122__TX_DCOC_RES_I_EVEN_122___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_122__TX_DCOC_RES_I_EVEN_122___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_122__TX_DCOC_RES_Q_EVEN_122___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_122__TX_DCOC_RES_Q_EVEN_122___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_122___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_122___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_123 (0x005FD9EC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_123___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_123___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_123__TX_DCOC_RES_I_ODD_123___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_123__TX_DCOC_RES_Q_ODD_123___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_123__TX_DCOC_RES_I_EVEN_123___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_123__TX_DCOC_RES_Q_EVEN_123___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_123__TX_DCOC_RES_I_ODD_123___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_123__TX_DCOC_RES_I_ODD_123___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_123__TX_DCOC_RES_Q_ODD_123___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_123__TX_DCOC_RES_Q_ODD_123___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_123__TX_DCOC_RES_I_EVEN_123___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_123__TX_DCOC_RES_I_EVEN_123___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_123__TX_DCOC_RES_Q_EVEN_123___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_123__TX_DCOC_RES_Q_EVEN_123___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_123___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_123___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_124 (0x005FD9F0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_124___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_124___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_124__TX_DCOC_RES_I_ODD_124___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_124__TX_DCOC_RES_Q_ODD_124___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_124__TX_DCOC_RES_I_EVEN_124___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_124__TX_DCOC_RES_Q_EVEN_124___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_124__TX_DCOC_RES_I_ODD_124___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_124__TX_DCOC_RES_I_ODD_124___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_124__TX_DCOC_RES_Q_ODD_124___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_124__TX_DCOC_RES_Q_ODD_124___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_124__TX_DCOC_RES_I_EVEN_124___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_124__TX_DCOC_RES_I_EVEN_124___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_124__TX_DCOC_RES_Q_EVEN_124___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_124__TX_DCOC_RES_Q_EVEN_124___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_124___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_124___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_125 (0x005FD9F4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_125___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_125___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_125__TX_DCOC_RES_I_ODD_125___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_125__TX_DCOC_RES_Q_ODD_125___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_125__TX_DCOC_RES_I_EVEN_125___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_125__TX_DCOC_RES_Q_EVEN_125___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_125__TX_DCOC_RES_I_ODD_125___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_125__TX_DCOC_RES_I_ODD_125___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_125__TX_DCOC_RES_Q_ODD_125___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_125__TX_DCOC_RES_Q_ODD_125___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_125__TX_DCOC_RES_I_EVEN_125___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_125__TX_DCOC_RES_I_EVEN_125___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_125__TX_DCOC_RES_Q_EVEN_125___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_125__TX_DCOC_RES_Q_EVEN_125___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_125___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_125___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_126 (0x005FD9F8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_126___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_126___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_126__TX_DCOC_RES_I_ODD_126___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_126__TX_DCOC_RES_Q_ODD_126___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_126__TX_DCOC_RES_I_EVEN_126___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_126__TX_DCOC_RES_Q_EVEN_126___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_126__TX_DCOC_RES_I_ODD_126___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_126__TX_DCOC_RES_I_ODD_126___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_126__TX_DCOC_RES_Q_ODD_126___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_126__TX_DCOC_RES_Q_ODD_126___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_126__TX_DCOC_RES_I_EVEN_126___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_126__TX_DCOC_RES_I_EVEN_126___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_126__TX_DCOC_RES_Q_EVEN_126___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_126__TX_DCOC_RES_Q_EVEN_126___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_126___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_126___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_127 (0x005FD9FC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_127___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_127___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_127__TX_DCOC_RES_I_ODD_127___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_127__TX_DCOC_RES_Q_ODD_127___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_127__TX_DCOC_RES_I_EVEN_127___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_127__TX_DCOC_RES_Q_EVEN_127___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_127__TX_DCOC_RES_I_ODD_127___M 0x3F800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_127__TX_DCOC_RES_I_ODD_127___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_127__TX_DCOC_RES_Q_ODD_127___M 0x007F0000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_127__TX_DCOC_RES_Q_ODD_127___S 16 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_127__TX_DCOC_RES_I_EVEN_127___M 0x00003F80 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_127__TX_DCOC_RES_I_EVEN_127___S 7 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_127__TX_DCOC_RES_Q_EVEN_127___M 0x0000007F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_127__TX_DCOC_RES_Q_EVEN_127___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_127___M 0x3FFF3FFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXDCOC_127___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0 (0x005FDC00) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__IPA_GAIN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__DAC_GAIN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__TX_PWR_LV_LAA_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__TX_PWR_LV_N79_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__BBF_GAIN_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__UPC_GAIN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__DA_GAIN_0___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__XPA_GAIN_0___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__IPA_GAIN_0___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__IPA_GAIN_0___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__DAC_GAIN_0___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__DAC_GAIN_0___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__TX_PWR_LV_LAA_0___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__TX_PWR_LV_LAA_0___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__TX_PWR_LV_N79_0___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__TX_PWR_LV_N79_0___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__BBF_GAIN_0___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__BBF_GAIN_0___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__UPC_GAIN_0___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__UPC_GAIN_0___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__DA_GAIN_0___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__DA_GAIN_0___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__XPA_GAIN_0___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0__XPA_GAIN_0___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_0___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1 (0x005FDC04) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__IPA_GAIN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__DAC_GAIN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__TX_PWR_LV_LAA_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__TX_PWR_LV_N79_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__BBF_GAIN_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__UPC_GAIN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__DA_GAIN_1___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__XPA_GAIN_1___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__IPA_GAIN_1___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__IPA_GAIN_1___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__DAC_GAIN_1___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__DAC_GAIN_1___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__TX_PWR_LV_LAA_1___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__TX_PWR_LV_LAA_1___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__TX_PWR_LV_N79_1___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__TX_PWR_LV_N79_1___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__BBF_GAIN_1___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__BBF_GAIN_1___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__UPC_GAIN_1___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__UPC_GAIN_1___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__DA_GAIN_1___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__DA_GAIN_1___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__XPA_GAIN_1___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1__XPA_GAIN_1___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_1___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2 (0x005FDC08) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__IPA_GAIN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__DAC_GAIN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__TX_PWR_LV_LAA_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__TX_PWR_LV_N79_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__BBF_GAIN_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__UPC_GAIN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__DA_GAIN_2___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__XPA_GAIN_2___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__IPA_GAIN_2___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__IPA_GAIN_2___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__DAC_GAIN_2___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__DAC_GAIN_2___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__TX_PWR_LV_LAA_2___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__TX_PWR_LV_LAA_2___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__TX_PWR_LV_N79_2___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__TX_PWR_LV_N79_2___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__BBF_GAIN_2___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__BBF_GAIN_2___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__UPC_GAIN_2___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__UPC_GAIN_2___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__DA_GAIN_2___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__DA_GAIN_2___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__XPA_GAIN_2___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2__XPA_GAIN_2___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_2___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3 (0x005FDC0C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__IPA_GAIN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__DAC_GAIN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__TX_PWR_LV_LAA_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__TX_PWR_LV_N79_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__BBF_GAIN_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__UPC_GAIN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__DA_GAIN_3___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__XPA_GAIN_3___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__IPA_GAIN_3___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__IPA_GAIN_3___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__DAC_GAIN_3___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__DAC_GAIN_3___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__TX_PWR_LV_LAA_3___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__TX_PWR_LV_LAA_3___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__TX_PWR_LV_N79_3___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__TX_PWR_LV_N79_3___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__BBF_GAIN_3___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__BBF_GAIN_3___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__UPC_GAIN_3___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__UPC_GAIN_3___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__DA_GAIN_3___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__DA_GAIN_3___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__XPA_GAIN_3___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3__XPA_GAIN_3___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_3___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4 (0x005FDC10) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__IPA_GAIN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__DAC_GAIN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__TX_PWR_LV_LAA_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__TX_PWR_LV_N79_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__BBF_GAIN_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__UPC_GAIN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__DA_GAIN_4___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__XPA_GAIN_4___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__IPA_GAIN_4___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__IPA_GAIN_4___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__DAC_GAIN_4___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__DAC_GAIN_4___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__TX_PWR_LV_LAA_4___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__TX_PWR_LV_LAA_4___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__TX_PWR_LV_N79_4___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__TX_PWR_LV_N79_4___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__BBF_GAIN_4___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__BBF_GAIN_4___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__UPC_GAIN_4___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__UPC_GAIN_4___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__DA_GAIN_4___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__DA_GAIN_4___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__XPA_GAIN_4___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4__XPA_GAIN_4___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_4___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5 (0x005FDC14) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__IPA_GAIN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__DAC_GAIN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__TX_PWR_LV_LAA_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__TX_PWR_LV_N79_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__BBF_GAIN_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__UPC_GAIN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__DA_GAIN_5___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__XPA_GAIN_5___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__IPA_GAIN_5___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__IPA_GAIN_5___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__DAC_GAIN_5___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__DAC_GAIN_5___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__TX_PWR_LV_LAA_5___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__TX_PWR_LV_LAA_5___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__TX_PWR_LV_N79_5___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__TX_PWR_LV_N79_5___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__BBF_GAIN_5___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__BBF_GAIN_5___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__UPC_GAIN_5___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__UPC_GAIN_5___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__DA_GAIN_5___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__DA_GAIN_5___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__XPA_GAIN_5___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5__XPA_GAIN_5___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_5___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6 (0x005FDC18) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__IPA_GAIN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__DAC_GAIN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__TX_PWR_LV_LAA_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__TX_PWR_LV_N79_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__BBF_GAIN_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__UPC_GAIN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__DA_GAIN_6___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__XPA_GAIN_6___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__IPA_GAIN_6___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__IPA_GAIN_6___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__DAC_GAIN_6___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__DAC_GAIN_6___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__TX_PWR_LV_LAA_6___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__TX_PWR_LV_LAA_6___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__TX_PWR_LV_N79_6___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__TX_PWR_LV_N79_6___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__BBF_GAIN_6___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__BBF_GAIN_6___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__UPC_GAIN_6___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__UPC_GAIN_6___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__DA_GAIN_6___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__DA_GAIN_6___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__XPA_GAIN_6___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6__XPA_GAIN_6___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_6___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7 (0x005FDC1C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__IPA_GAIN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__DAC_GAIN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__TX_PWR_LV_LAA_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__TX_PWR_LV_N79_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__BBF_GAIN_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__UPC_GAIN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__DA_GAIN_7___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__XPA_GAIN_7___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__IPA_GAIN_7___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__IPA_GAIN_7___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__DAC_GAIN_7___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__DAC_GAIN_7___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__TX_PWR_LV_LAA_7___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__TX_PWR_LV_LAA_7___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__TX_PWR_LV_N79_7___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__TX_PWR_LV_N79_7___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__BBF_GAIN_7___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__BBF_GAIN_7___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__UPC_GAIN_7___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__UPC_GAIN_7___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__DA_GAIN_7___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__DA_GAIN_7___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__XPA_GAIN_7___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7__XPA_GAIN_7___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_7___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8 (0x005FDC20) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__IPA_GAIN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__DAC_GAIN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__TX_PWR_LV_LAA_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__TX_PWR_LV_N79_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__BBF_GAIN_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__UPC_GAIN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__DA_GAIN_8___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__XPA_GAIN_8___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__IPA_GAIN_8___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__IPA_GAIN_8___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__DAC_GAIN_8___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__DAC_GAIN_8___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__TX_PWR_LV_LAA_8___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__TX_PWR_LV_LAA_8___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__TX_PWR_LV_N79_8___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__TX_PWR_LV_N79_8___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__BBF_GAIN_8___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__BBF_GAIN_8___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__UPC_GAIN_8___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__UPC_GAIN_8___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__DA_GAIN_8___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__DA_GAIN_8___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__XPA_GAIN_8___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8__XPA_GAIN_8___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_8___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9 (0x005FDC24) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__IPA_GAIN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__DAC_GAIN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__TX_PWR_LV_LAA_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__TX_PWR_LV_N79_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__BBF_GAIN_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__UPC_GAIN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__DA_GAIN_9___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__XPA_GAIN_9___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__IPA_GAIN_9___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__IPA_GAIN_9___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__DAC_GAIN_9___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__DAC_GAIN_9___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__TX_PWR_LV_LAA_9___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__TX_PWR_LV_LAA_9___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__TX_PWR_LV_N79_9___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__TX_PWR_LV_N79_9___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__BBF_GAIN_9___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__BBF_GAIN_9___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__UPC_GAIN_9___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__UPC_GAIN_9___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__DA_GAIN_9___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__DA_GAIN_9___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__XPA_GAIN_9___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9__XPA_GAIN_9___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_9___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10 (0x005FDC28) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__IPA_GAIN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__DAC_GAIN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__TX_PWR_LV_LAA_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__TX_PWR_LV_N79_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__BBF_GAIN_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__UPC_GAIN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__DA_GAIN_10___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__XPA_GAIN_10___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__IPA_GAIN_10___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__IPA_GAIN_10___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__DAC_GAIN_10___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__DAC_GAIN_10___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__TX_PWR_LV_LAA_10___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__TX_PWR_LV_LAA_10___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__TX_PWR_LV_N79_10___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__TX_PWR_LV_N79_10___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__BBF_GAIN_10___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__BBF_GAIN_10___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__UPC_GAIN_10___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__UPC_GAIN_10___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__DA_GAIN_10___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__DA_GAIN_10___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__XPA_GAIN_10___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10__XPA_GAIN_10___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_10___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11 (0x005FDC2C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__IPA_GAIN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__DAC_GAIN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__TX_PWR_LV_LAA_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__TX_PWR_LV_N79_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__BBF_GAIN_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__UPC_GAIN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__DA_GAIN_11___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__XPA_GAIN_11___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__IPA_GAIN_11___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__IPA_GAIN_11___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__DAC_GAIN_11___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__DAC_GAIN_11___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__TX_PWR_LV_LAA_11___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__TX_PWR_LV_LAA_11___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__TX_PWR_LV_N79_11___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__TX_PWR_LV_N79_11___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__BBF_GAIN_11___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__BBF_GAIN_11___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__UPC_GAIN_11___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__UPC_GAIN_11___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__DA_GAIN_11___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__DA_GAIN_11___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__XPA_GAIN_11___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11__XPA_GAIN_11___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_11___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12 (0x005FDC30) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__IPA_GAIN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__DAC_GAIN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__TX_PWR_LV_LAA_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__TX_PWR_LV_N79_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__BBF_GAIN_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__UPC_GAIN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__DA_GAIN_12___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__XPA_GAIN_12___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__IPA_GAIN_12___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__IPA_GAIN_12___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__DAC_GAIN_12___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__DAC_GAIN_12___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__TX_PWR_LV_LAA_12___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__TX_PWR_LV_LAA_12___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__TX_PWR_LV_N79_12___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__TX_PWR_LV_N79_12___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__BBF_GAIN_12___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__BBF_GAIN_12___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__UPC_GAIN_12___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__UPC_GAIN_12___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__DA_GAIN_12___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__DA_GAIN_12___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__XPA_GAIN_12___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12__XPA_GAIN_12___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_12___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13 (0x005FDC34) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__IPA_GAIN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__DAC_GAIN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__TX_PWR_LV_LAA_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__TX_PWR_LV_N79_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__BBF_GAIN_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__UPC_GAIN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__DA_GAIN_13___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__XPA_GAIN_13___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__IPA_GAIN_13___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__IPA_GAIN_13___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__DAC_GAIN_13___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__DAC_GAIN_13___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__TX_PWR_LV_LAA_13___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__TX_PWR_LV_LAA_13___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__TX_PWR_LV_N79_13___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__TX_PWR_LV_N79_13___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__BBF_GAIN_13___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__BBF_GAIN_13___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__UPC_GAIN_13___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__UPC_GAIN_13___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__DA_GAIN_13___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__DA_GAIN_13___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__XPA_GAIN_13___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13__XPA_GAIN_13___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_13___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14 (0x005FDC38) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__IPA_GAIN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__DAC_GAIN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__TX_PWR_LV_LAA_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__TX_PWR_LV_N79_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__BBF_GAIN_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__UPC_GAIN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__DA_GAIN_14___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__XPA_GAIN_14___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__IPA_GAIN_14___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__IPA_GAIN_14___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__DAC_GAIN_14___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__DAC_GAIN_14___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__TX_PWR_LV_LAA_14___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__TX_PWR_LV_LAA_14___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__TX_PWR_LV_N79_14___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__TX_PWR_LV_N79_14___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__BBF_GAIN_14___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__BBF_GAIN_14___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__UPC_GAIN_14___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__UPC_GAIN_14___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__DA_GAIN_14___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__DA_GAIN_14___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__XPA_GAIN_14___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14__XPA_GAIN_14___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_14___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15 (0x005FDC3C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__IPA_GAIN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__DAC_GAIN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__TX_PWR_LV_LAA_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__TX_PWR_LV_N79_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__BBF_GAIN_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__UPC_GAIN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__DA_GAIN_15___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__XPA_GAIN_15___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__IPA_GAIN_15___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__IPA_GAIN_15___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__DAC_GAIN_15___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__DAC_GAIN_15___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__TX_PWR_LV_LAA_15___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__TX_PWR_LV_LAA_15___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__TX_PWR_LV_N79_15___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__TX_PWR_LV_N79_15___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__BBF_GAIN_15___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__BBF_GAIN_15___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__UPC_GAIN_15___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__UPC_GAIN_15___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__DA_GAIN_15___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__DA_GAIN_15___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__XPA_GAIN_15___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15__XPA_GAIN_15___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_15___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16 (0x005FDC40) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__IPA_GAIN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__DAC_GAIN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__TX_PWR_LV_LAA_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__TX_PWR_LV_N79_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__BBF_GAIN_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__UPC_GAIN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__DA_GAIN_16___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__XPA_GAIN_16___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__IPA_GAIN_16___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__IPA_GAIN_16___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__DAC_GAIN_16___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__DAC_GAIN_16___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__TX_PWR_LV_LAA_16___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__TX_PWR_LV_LAA_16___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__TX_PWR_LV_N79_16___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__TX_PWR_LV_N79_16___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__BBF_GAIN_16___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__BBF_GAIN_16___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__UPC_GAIN_16___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__UPC_GAIN_16___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__DA_GAIN_16___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__DA_GAIN_16___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__XPA_GAIN_16___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16__XPA_GAIN_16___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_16___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17 (0x005FDC44) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__IPA_GAIN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__DAC_GAIN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__TX_PWR_LV_LAA_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__TX_PWR_LV_N79_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__BBF_GAIN_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__UPC_GAIN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__DA_GAIN_17___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__XPA_GAIN_17___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__IPA_GAIN_17___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__IPA_GAIN_17___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__DAC_GAIN_17___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__DAC_GAIN_17___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__TX_PWR_LV_LAA_17___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__TX_PWR_LV_LAA_17___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__TX_PWR_LV_N79_17___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__TX_PWR_LV_N79_17___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__BBF_GAIN_17___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__BBF_GAIN_17___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__UPC_GAIN_17___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__UPC_GAIN_17___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__DA_GAIN_17___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__DA_GAIN_17___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__XPA_GAIN_17___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17__XPA_GAIN_17___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_17___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18 (0x005FDC48) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__IPA_GAIN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__DAC_GAIN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__TX_PWR_LV_LAA_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__TX_PWR_LV_N79_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__BBF_GAIN_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__UPC_GAIN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__DA_GAIN_18___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__XPA_GAIN_18___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__IPA_GAIN_18___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__IPA_GAIN_18___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__DAC_GAIN_18___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__DAC_GAIN_18___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__TX_PWR_LV_LAA_18___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__TX_PWR_LV_LAA_18___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__TX_PWR_LV_N79_18___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__TX_PWR_LV_N79_18___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__BBF_GAIN_18___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__BBF_GAIN_18___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__UPC_GAIN_18___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__UPC_GAIN_18___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__DA_GAIN_18___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__DA_GAIN_18___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__XPA_GAIN_18___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18__XPA_GAIN_18___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_18___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19 (0x005FDC4C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__IPA_GAIN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__DAC_GAIN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__TX_PWR_LV_LAA_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__TX_PWR_LV_N79_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__BBF_GAIN_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__UPC_GAIN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__DA_GAIN_19___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__XPA_GAIN_19___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__IPA_GAIN_19___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__IPA_GAIN_19___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__DAC_GAIN_19___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__DAC_GAIN_19___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__TX_PWR_LV_LAA_19___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__TX_PWR_LV_LAA_19___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__TX_PWR_LV_N79_19___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__TX_PWR_LV_N79_19___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__BBF_GAIN_19___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__BBF_GAIN_19___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__UPC_GAIN_19___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__UPC_GAIN_19___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__DA_GAIN_19___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__DA_GAIN_19___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__XPA_GAIN_19___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19__XPA_GAIN_19___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_19___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20 (0x005FDC50) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__IPA_GAIN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__DAC_GAIN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__TX_PWR_LV_LAA_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__TX_PWR_LV_N79_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__BBF_GAIN_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__UPC_GAIN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__DA_GAIN_20___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__XPA_GAIN_20___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__IPA_GAIN_20___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__IPA_GAIN_20___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__DAC_GAIN_20___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__DAC_GAIN_20___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__TX_PWR_LV_LAA_20___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__TX_PWR_LV_LAA_20___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__TX_PWR_LV_N79_20___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__TX_PWR_LV_N79_20___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__BBF_GAIN_20___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__BBF_GAIN_20___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__UPC_GAIN_20___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__UPC_GAIN_20___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__DA_GAIN_20___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__DA_GAIN_20___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__XPA_GAIN_20___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20__XPA_GAIN_20___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_20___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21 (0x005FDC54) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__IPA_GAIN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__DAC_GAIN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__TX_PWR_LV_LAA_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__TX_PWR_LV_N79_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__BBF_GAIN_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__UPC_GAIN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__DA_GAIN_21___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__XPA_GAIN_21___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__IPA_GAIN_21___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__IPA_GAIN_21___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__DAC_GAIN_21___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__DAC_GAIN_21___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__TX_PWR_LV_LAA_21___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__TX_PWR_LV_LAA_21___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__TX_PWR_LV_N79_21___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__TX_PWR_LV_N79_21___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__BBF_GAIN_21___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__BBF_GAIN_21___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__UPC_GAIN_21___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__UPC_GAIN_21___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__DA_GAIN_21___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__DA_GAIN_21___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__XPA_GAIN_21___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21__XPA_GAIN_21___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_21___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22 (0x005FDC58) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__IPA_GAIN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__DAC_GAIN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__TX_PWR_LV_LAA_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__TX_PWR_LV_N79_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__BBF_GAIN_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__UPC_GAIN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__DA_GAIN_22___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__XPA_GAIN_22___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__IPA_GAIN_22___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__IPA_GAIN_22___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__DAC_GAIN_22___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__DAC_GAIN_22___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__TX_PWR_LV_LAA_22___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__TX_PWR_LV_LAA_22___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__TX_PWR_LV_N79_22___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__TX_PWR_LV_N79_22___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__BBF_GAIN_22___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__BBF_GAIN_22___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__UPC_GAIN_22___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__UPC_GAIN_22___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__DA_GAIN_22___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__DA_GAIN_22___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__XPA_GAIN_22___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22__XPA_GAIN_22___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_22___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23 (0x005FDC5C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__IPA_GAIN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__DAC_GAIN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__TX_PWR_LV_LAA_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__TX_PWR_LV_N79_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__BBF_GAIN_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__UPC_GAIN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__DA_GAIN_23___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__XPA_GAIN_23___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__IPA_GAIN_23___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__IPA_GAIN_23___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__DAC_GAIN_23___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__DAC_GAIN_23___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__TX_PWR_LV_LAA_23___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__TX_PWR_LV_LAA_23___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__TX_PWR_LV_N79_23___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__TX_PWR_LV_N79_23___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__BBF_GAIN_23___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__BBF_GAIN_23___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__UPC_GAIN_23___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__UPC_GAIN_23___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__DA_GAIN_23___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__DA_GAIN_23___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__XPA_GAIN_23___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23__XPA_GAIN_23___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_23___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24 (0x005FDC60) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__IPA_GAIN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__DAC_GAIN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__TX_PWR_LV_LAA_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__TX_PWR_LV_N79_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__BBF_GAIN_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__UPC_GAIN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__DA_GAIN_24___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__XPA_GAIN_24___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__IPA_GAIN_24___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__IPA_GAIN_24___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__DAC_GAIN_24___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__DAC_GAIN_24___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__TX_PWR_LV_LAA_24___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__TX_PWR_LV_LAA_24___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__TX_PWR_LV_N79_24___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__TX_PWR_LV_N79_24___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__BBF_GAIN_24___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__BBF_GAIN_24___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__UPC_GAIN_24___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__UPC_GAIN_24___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__DA_GAIN_24___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__DA_GAIN_24___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__XPA_GAIN_24___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24__XPA_GAIN_24___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_24___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25 (0x005FDC64) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__IPA_GAIN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__DAC_GAIN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__TX_PWR_LV_LAA_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__TX_PWR_LV_N79_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__BBF_GAIN_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__UPC_GAIN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__DA_GAIN_25___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__XPA_GAIN_25___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__IPA_GAIN_25___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__IPA_GAIN_25___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__DAC_GAIN_25___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__DAC_GAIN_25___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__TX_PWR_LV_LAA_25___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__TX_PWR_LV_LAA_25___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__TX_PWR_LV_N79_25___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__TX_PWR_LV_N79_25___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__BBF_GAIN_25___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__BBF_GAIN_25___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__UPC_GAIN_25___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__UPC_GAIN_25___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__DA_GAIN_25___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__DA_GAIN_25___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__XPA_GAIN_25___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25__XPA_GAIN_25___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_25___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26 (0x005FDC68) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__IPA_GAIN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__DAC_GAIN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__TX_PWR_LV_LAA_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__TX_PWR_LV_N79_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__BBF_GAIN_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__UPC_GAIN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__DA_GAIN_26___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__XPA_GAIN_26___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__IPA_GAIN_26___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__IPA_GAIN_26___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__DAC_GAIN_26___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__DAC_GAIN_26___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__TX_PWR_LV_LAA_26___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__TX_PWR_LV_LAA_26___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__TX_PWR_LV_N79_26___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__TX_PWR_LV_N79_26___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__BBF_GAIN_26___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__BBF_GAIN_26___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__UPC_GAIN_26___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__UPC_GAIN_26___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__DA_GAIN_26___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__DA_GAIN_26___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__XPA_GAIN_26___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26__XPA_GAIN_26___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_26___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27 (0x005FDC6C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__IPA_GAIN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__DAC_GAIN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__TX_PWR_LV_LAA_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__TX_PWR_LV_N79_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__BBF_GAIN_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__UPC_GAIN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__DA_GAIN_27___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__XPA_GAIN_27___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__IPA_GAIN_27___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__IPA_GAIN_27___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__DAC_GAIN_27___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__DAC_GAIN_27___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__TX_PWR_LV_LAA_27___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__TX_PWR_LV_LAA_27___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__TX_PWR_LV_N79_27___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__TX_PWR_LV_N79_27___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__BBF_GAIN_27___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__BBF_GAIN_27___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__UPC_GAIN_27___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__UPC_GAIN_27___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__DA_GAIN_27___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__DA_GAIN_27___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__XPA_GAIN_27___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27__XPA_GAIN_27___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_27___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28 (0x005FDC70) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__IPA_GAIN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__DAC_GAIN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__TX_PWR_LV_LAA_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__TX_PWR_LV_N79_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__BBF_GAIN_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__UPC_GAIN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__DA_GAIN_28___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__XPA_GAIN_28___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__IPA_GAIN_28___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__IPA_GAIN_28___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__DAC_GAIN_28___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__DAC_GAIN_28___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__TX_PWR_LV_LAA_28___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__TX_PWR_LV_LAA_28___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__TX_PWR_LV_N79_28___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__TX_PWR_LV_N79_28___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__BBF_GAIN_28___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__BBF_GAIN_28___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__UPC_GAIN_28___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__UPC_GAIN_28___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__DA_GAIN_28___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__DA_GAIN_28___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__XPA_GAIN_28___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28__XPA_GAIN_28___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_28___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29 (0x005FDC74) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__IPA_GAIN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__DAC_GAIN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__TX_PWR_LV_LAA_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__TX_PWR_LV_N79_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__BBF_GAIN_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__UPC_GAIN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__DA_GAIN_29___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__XPA_GAIN_29___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__IPA_GAIN_29___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__IPA_GAIN_29___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__DAC_GAIN_29___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__DAC_GAIN_29___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__TX_PWR_LV_LAA_29___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__TX_PWR_LV_LAA_29___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__TX_PWR_LV_N79_29___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__TX_PWR_LV_N79_29___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__BBF_GAIN_29___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__BBF_GAIN_29___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__UPC_GAIN_29___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__UPC_GAIN_29___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__DA_GAIN_29___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__DA_GAIN_29___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__XPA_GAIN_29___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29__XPA_GAIN_29___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_29___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30 (0x005FDC78) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__IPA_GAIN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__DAC_GAIN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__TX_PWR_LV_LAA_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__TX_PWR_LV_N79_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__BBF_GAIN_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__UPC_GAIN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__DA_GAIN_30___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__XPA_GAIN_30___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__IPA_GAIN_30___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__IPA_GAIN_30___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__DAC_GAIN_30___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__DAC_GAIN_30___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__TX_PWR_LV_LAA_30___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__TX_PWR_LV_LAA_30___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__TX_PWR_LV_N79_30___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__TX_PWR_LV_N79_30___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__BBF_GAIN_30___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__BBF_GAIN_30___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__UPC_GAIN_30___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__UPC_GAIN_30___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__DA_GAIN_30___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__DA_GAIN_30___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__XPA_GAIN_30___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30__XPA_GAIN_30___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_30___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31 (0x005FDC7C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__IPA_GAIN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__DAC_GAIN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__TX_PWR_LV_LAA_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__TX_PWR_LV_N79_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__BBF_GAIN_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__UPC_GAIN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__DA_GAIN_31___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__XPA_GAIN_31___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__IPA_GAIN_31___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__IPA_GAIN_31___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__DAC_GAIN_31___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__DAC_GAIN_31___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__TX_PWR_LV_LAA_31___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__TX_PWR_LV_LAA_31___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__TX_PWR_LV_N79_31___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__TX_PWR_LV_N79_31___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__BBF_GAIN_31___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__BBF_GAIN_31___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__UPC_GAIN_31___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__UPC_GAIN_31___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__DA_GAIN_31___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__DA_GAIN_31___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__XPA_GAIN_31___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31__XPA_GAIN_31___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_31___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32 (0x005FDC80) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__IPA_GAIN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__DAC_GAIN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__TX_PWR_LV_LAA_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__TX_PWR_LV_N79_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__BBF_GAIN_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__UPC_GAIN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__DA_GAIN_32___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__XPA_GAIN_32___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__IPA_GAIN_32___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__IPA_GAIN_32___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__DAC_GAIN_32___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__DAC_GAIN_32___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__TX_PWR_LV_LAA_32___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__TX_PWR_LV_LAA_32___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__TX_PWR_LV_N79_32___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__TX_PWR_LV_N79_32___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__BBF_GAIN_32___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__BBF_GAIN_32___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__UPC_GAIN_32___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__UPC_GAIN_32___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__DA_GAIN_32___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__DA_GAIN_32___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__XPA_GAIN_32___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32__XPA_GAIN_32___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_32___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33 (0x005FDC84) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__IPA_GAIN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__DAC_GAIN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__TX_PWR_LV_LAA_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__TX_PWR_LV_N79_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__BBF_GAIN_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__UPC_GAIN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__DA_GAIN_33___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__XPA_GAIN_33___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__IPA_GAIN_33___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__IPA_GAIN_33___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__DAC_GAIN_33___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__DAC_GAIN_33___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__TX_PWR_LV_LAA_33___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__TX_PWR_LV_LAA_33___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__TX_PWR_LV_N79_33___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__TX_PWR_LV_N79_33___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__BBF_GAIN_33___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__BBF_GAIN_33___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__UPC_GAIN_33___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__UPC_GAIN_33___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__DA_GAIN_33___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__DA_GAIN_33___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__XPA_GAIN_33___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33__XPA_GAIN_33___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_33___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34 (0x005FDC88) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__IPA_GAIN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__DAC_GAIN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__TX_PWR_LV_LAA_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__TX_PWR_LV_N79_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__BBF_GAIN_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__UPC_GAIN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__DA_GAIN_34___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__XPA_GAIN_34___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__IPA_GAIN_34___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__IPA_GAIN_34___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__DAC_GAIN_34___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__DAC_GAIN_34___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__TX_PWR_LV_LAA_34___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__TX_PWR_LV_LAA_34___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__TX_PWR_LV_N79_34___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__TX_PWR_LV_N79_34___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__BBF_GAIN_34___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__BBF_GAIN_34___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__UPC_GAIN_34___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__UPC_GAIN_34___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__DA_GAIN_34___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__DA_GAIN_34___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__XPA_GAIN_34___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34__XPA_GAIN_34___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_34___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35 (0x005FDC8C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__IPA_GAIN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__DAC_GAIN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__TX_PWR_LV_LAA_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__TX_PWR_LV_N79_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__BBF_GAIN_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__UPC_GAIN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__DA_GAIN_35___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__XPA_GAIN_35___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__IPA_GAIN_35___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__IPA_GAIN_35___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__DAC_GAIN_35___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__DAC_GAIN_35___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__TX_PWR_LV_LAA_35___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__TX_PWR_LV_LAA_35___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__TX_PWR_LV_N79_35___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__TX_PWR_LV_N79_35___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__BBF_GAIN_35___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__BBF_GAIN_35___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__UPC_GAIN_35___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__UPC_GAIN_35___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__DA_GAIN_35___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__DA_GAIN_35___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__XPA_GAIN_35___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35__XPA_GAIN_35___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_35___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36 (0x005FDC90) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__IPA_GAIN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__DAC_GAIN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__TX_PWR_LV_LAA_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__TX_PWR_LV_N79_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__BBF_GAIN_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__UPC_GAIN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__DA_GAIN_36___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__XPA_GAIN_36___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__IPA_GAIN_36___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__IPA_GAIN_36___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__DAC_GAIN_36___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__DAC_GAIN_36___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__TX_PWR_LV_LAA_36___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__TX_PWR_LV_LAA_36___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__TX_PWR_LV_N79_36___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__TX_PWR_LV_N79_36___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__BBF_GAIN_36___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__BBF_GAIN_36___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__UPC_GAIN_36___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__UPC_GAIN_36___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__DA_GAIN_36___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__DA_GAIN_36___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__XPA_GAIN_36___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36__XPA_GAIN_36___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_36___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37 (0x005FDC94) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__IPA_GAIN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__DAC_GAIN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__TX_PWR_LV_LAA_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__TX_PWR_LV_N79_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__BBF_GAIN_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__UPC_GAIN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__DA_GAIN_37___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__XPA_GAIN_37___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__IPA_GAIN_37___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__IPA_GAIN_37___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__DAC_GAIN_37___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__DAC_GAIN_37___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__TX_PWR_LV_LAA_37___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__TX_PWR_LV_LAA_37___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__TX_PWR_LV_N79_37___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__TX_PWR_LV_N79_37___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__BBF_GAIN_37___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__BBF_GAIN_37___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__UPC_GAIN_37___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__UPC_GAIN_37___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__DA_GAIN_37___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__DA_GAIN_37___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__XPA_GAIN_37___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37__XPA_GAIN_37___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_37___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38 (0x005FDC98) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__IPA_GAIN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__DAC_GAIN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__TX_PWR_LV_LAA_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__TX_PWR_LV_N79_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__BBF_GAIN_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__UPC_GAIN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__DA_GAIN_38___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__XPA_GAIN_38___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__IPA_GAIN_38___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__IPA_GAIN_38___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__DAC_GAIN_38___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__DAC_GAIN_38___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__TX_PWR_LV_LAA_38___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__TX_PWR_LV_LAA_38___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__TX_PWR_LV_N79_38___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__TX_PWR_LV_N79_38___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__BBF_GAIN_38___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__BBF_GAIN_38___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__UPC_GAIN_38___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__UPC_GAIN_38___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__DA_GAIN_38___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__DA_GAIN_38___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__XPA_GAIN_38___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38__XPA_GAIN_38___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_38___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39 (0x005FDC9C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__IPA_GAIN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__DAC_GAIN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__TX_PWR_LV_LAA_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__TX_PWR_LV_N79_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__BBF_GAIN_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__UPC_GAIN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__DA_GAIN_39___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__XPA_GAIN_39___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__IPA_GAIN_39___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__IPA_GAIN_39___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__DAC_GAIN_39___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__DAC_GAIN_39___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__TX_PWR_LV_LAA_39___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__TX_PWR_LV_LAA_39___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__TX_PWR_LV_N79_39___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__TX_PWR_LV_N79_39___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__BBF_GAIN_39___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__BBF_GAIN_39___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__UPC_GAIN_39___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__UPC_GAIN_39___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__DA_GAIN_39___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__DA_GAIN_39___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__XPA_GAIN_39___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39__XPA_GAIN_39___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_39___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40 (0x005FDCA0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__IPA_GAIN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__DAC_GAIN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__TX_PWR_LV_LAA_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__TX_PWR_LV_N79_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__BBF_GAIN_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__UPC_GAIN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__DA_GAIN_40___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__XPA_GAIN_40___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__IPA_GAIN_40___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__IPA_GAIN_40___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__DAC_GAIN_40___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__DAC_GAIN_40___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__TX_PWR_LV_LAA_40___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__TX_PWR_LV_LAA_40___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__TX_PWR_LV_N79_40___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__TX_PWR_LV_N79_40___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__BBF_GAIN_40___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__BBF_GAIN_40___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__UPC_GAIN_40___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__UPC_GAIN_40___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__DA_GAIN_40___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__DA_GAIN_40___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__XPA_GAIN_40___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40__XPA_GAIN_40___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_40___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41 (0x005FDCA4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__IPA_GAIN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__DAC_GAIN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__TX_PWR_LV_LAA_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__TX_PWR_LV_N79_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__BBF_GAIN_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__UPC_GAIN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__DA_GAIN_41___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__XPA_GAIN_41___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__IPA_GAIN_41___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__IPA_GAIN_41___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__DAC_GAIN_41___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__DAC_GAIN_41___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__TX_PWR_LV_LAA_41___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__TX_PWR_LV_LAA_41___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__TX_PWR_LV_N79_41___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__TX_PWR_LV_N79_41___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__BBF_GAIN_41___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__BBF_GAIN_41___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__UPC_GAIN_41___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__UPC_GAIN_41___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__DA_GAIN_41___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__DA_GAIN_41___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__XPA_GAIN_41___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41__XPA_GAIN_41___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_41___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42 (0x005FDCA8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__IPA_GAIN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__DAC_GAIN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__TX_PWR_LV_LAA_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__TX_PWR_LV_N79_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__BBF_GAIN_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__UPC_GAIN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__DA_GAIN_42___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__XPA_GAIN_42___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__IPA_GAIN_42___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__IPA_GAIN_42___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__DAC_GAIN_42___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__DAC_GAIN_42___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__TX_PWR_LV_LAA_42___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__TX_PWR_LV_LAA_42___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__TX_PWR_LV_N79_42___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__TX_PWR_LV_N79_42___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__BBF_GAIN_42___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__BBF_GAIN_42___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__UPC_GAIN_42___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__UPC_GAIN_42___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__DA_GAIN_42___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__DA_GAIN_42___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__XPA_GAIN_42___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42__XPA_GAIN_42___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_42___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43 (0x005FDCAC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__IPA_GAIN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__DAC_GAIN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__TX_PWR_LV_LAA_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__TX_PWR_LV_N79_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__BBF_GAIN_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__UPC_GAIN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__DA_GAIN_43___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__XPA_GAIN_43___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__IPA_GAIN_43___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__IPA_GAIN_43___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__DAC_GAIN_43___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__DAC_GAIN_43___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__TX_PWR_LV_LAA_43___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__TX_PWR_LV_LAA_43___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__TX_PWR_LV_N79_43___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__TX_PWR_LV_N79_43___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__BBF_GAIN_43___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__BBF_GAIN_43___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__UPC_GAIN_43___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__UPC_GAIN_43___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__DA_GAIN_43___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__DA_GAIN_43___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__XPA_GAIN_43___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43__XPA_GAIN_43___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_43___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44 (0x005FDCB0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__IPA_GAIN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__DAC_GAIN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__TX_PWR_LV_LAA_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__TX_PWR_LV_N79_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__BBF_GAIN_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__UPC_GAIN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__DA_GAIN_44___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__XPA_GAIN_44___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__IPA_GAIN_44___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__IPA_GAIN_44___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__DAC_GAIN_44___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__DAC_GAIN_44___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__TX_PWR_LV_LAA_44___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__TX_PWR_LV_LAA_44___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__TX_PWR_LV_N79_44___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__TX_PWR_LV_N79_44___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__BBF_GAIN_44___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__BBF_GAIN_44___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__UPC_GAIN_44___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__UPC_GAIN_44___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__DA_GAIN_44___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__DA_GAIN_44___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__XPA_GAIN_44___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44__XPA_GAIN_44___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_44___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45 (0x005FDCB4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__IPA_GAIN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__DAC_GAIN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__TX_PWR_LV_LAA_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__TX_PWR_LV_N79_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__BBF_GAIN_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__UPC_GAIN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__DA_GAIN_45___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__XPA_GAIN_45___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__IPA_GAIN_45___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__IPA_GAIN_45___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__DAC_GAIN_45___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__DAC_GAIN_45___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__TX_PWR_LV_LAA_45___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__TX_PWR_LV_LAA_45___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__TX_PWR_LV_N79_45___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__TX_PWR_LV_N79_45___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__BBF_GAIN_45___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__BBF_GAIN_45___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__UPC_GAIN_45___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__UPC_GAIN_45___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__DA_GAIN_45___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__DA_GAIN_45___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__XPA_GAIN_45___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45__XPA_GAIN_45___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_45___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46 (0x005FDCB8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__IPA_GAIN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__DAC_GAIN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__TX_PWR_LV_LAA_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__TX_PWR_LV_N79_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__BBF_GAIN_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__UPC_GAIN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__DA_GAIN_46___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__XPA_GAIN_46___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__IPA_GAIN_46___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__IPA_GAIN_46___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__DAC_GAIN_46___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__DAC_GAIN_46___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__TX_PWR_LV_LAA_46___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__TX_PWR_LV_LAA_46___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__TX_PWR_LV_N79_46___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__TX_PWR_LV_N79_46___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__BBF_GAIN_46___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__BBF_GAIN_46___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__UPC_GAIN_46___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__UPC_GAIN_46___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__DA_GAIN_46___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__DA_GAIN_46___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__XPA_GAIN_46___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46__XPA_GAIN_46___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_46___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47 (0x005FDCBC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__IPA_GAIN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__DAC_GAIN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__TX_PWR_LV_LAA_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__TX_PWR_LV_N79_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__BBF_GAIN_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__UPC_GAIN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__DA_GAIN_47___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__XPA_GAIN_47___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__IPA_GAIN_47___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__IPA_GAIN_47___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__DAC_GAIN_47___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__DAC_GAIN_47___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__TX_PWR_LV_LAA_47___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__TX_PWR_LV_LAA_47___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__TX_PWR_LV_N79_47___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__TX_PWR_LV_N79_47___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__BBF_GAIN_47___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__BBF_GAIN_47___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__UPC_GAIN_47___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__UPC_GAIN_47___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__DA_GAIN_47___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__DA_GAIN_47___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__XPA_GAIN_47___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47__XPA_GAIN_47___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_47___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48 (0x005FDCC0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__IPA_GAIN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__DAC_GAIN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__TX_PWR_LV_LAA_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__TX_PWR_LV_N79_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__BBF_GAIN_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__UPC_GAIN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__DA_GAIN_48___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__XPA_GAIN_48___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__IPA_GAIN_48___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__IPA_GAIN_48___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__DAC_GAIN_48___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__DAC_GAIN_48___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__TX_PWR_LV_LAA_48___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__TX_PWR_LV_LAA_48___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__TX_PWR_LV_N79_48___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__TX_PWR_LV_N79_48___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__BBF_GAIN_48___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__BBF_GAIN_48___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__UPC_GAIN_48___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__UPC_GAIN_48___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__DA_GAIN_48___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__DA_GAIN_48___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__XPA_GAIN_48___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48__XPA_GAIN_48___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_48___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49 (0x005FDCC4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__IPA_GAIN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__DAC_GAIN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__TX_PWR_LV_LAA_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__TX_PWR_LV_N79_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__BBF_GAIN_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__UPC_GAIN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__DA_GAIN_49___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__XPA_GAIN_49___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__IPA_GAIN_49___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__IPA_GAIN_49___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__DAC_GAIN_49___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__DAC_GAIN_49___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__TX_PWR_LV_LAA_49___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__TX_PWR_LV_LAA_49___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__TX_PWR_LV_N79_49___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__TX_PWR_LV_N79_49___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__BBF_GAIN_49___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__BBF_GAIN_49___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__UPC_GAIN_49___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__UPC_GAIN_49___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__DA_GAIN_49___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__DA_GAIN_49___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__XPA_GAIN_49___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49__XPA_GAIN_49___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_49___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50 (0x005FDCC8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__IPA_GAIN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__DAC_GAIN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__TX_PWR_LV_LAA_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__TX_PWR_LV_N79_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__BBF_GAIN_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__UPC_GAIN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__DA_GAIN_50___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__XPA_GAIN_50___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__IPA_GAIN_50___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__IPA_GAIN_50___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__DAC_GAIN_50___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__DAC_GAIN_50___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__TX_PWR_LV_LAA_50___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__TX_PWR_LV_LAA_50___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__TX_PWR_LV_N79_50___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__TX_PWR_LV_N79_50___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__BBF_GAIN_50___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__BBF_GAIN_50___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__UPC_GAIN_50___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__UPC_GAIN_50___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__DA_GAIN_50___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__DA_GAIN_50___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__XPA_GAIN_50___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50__XPA_GAIN_50___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_50___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51 (0x005FDCCC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__IPA_GAIN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__DAC_GAIN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__TX_PWR_LV_LAA_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__TX_PWR_LV_N79_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__BBF_GAIN_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__UPC_GAIN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__DA_GAIN_51___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__XPA_GAIN_51___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__IPA_GAIN_51___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__IPA_GAIN_51___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__DAC_GAIN_51___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__DAC_GAIN_51___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__TX_PWR_LV_LAA_51___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__TX_PWR_LV_LAA_51___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__TX_PWR_LV_N79_51___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__TX_PWR_LV_N79_51___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__BBF_GAIN_51___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__BBF_GAIN_51___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__UPC_GAIN_51___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__UPC_GAIN_51___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__DA_GAIN_51___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__DA_GAIN_51___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__XPA_GAIN_51___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51__XPA_GAIN_51___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_51___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52 (0x005FDCD0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__IPA_GAIN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__DAC_GAIN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__TX_PWR_LV_LAA_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__TX_PWR_LV_N79_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__BBF_GAIN_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__UPC_GAIN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__DA_GAIN_52___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__XPA_GAIN_52___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__IPA_GAIN_52___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__IPA_GAIN_52___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__DAC_GAIN_52___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__DAC_GAIN_52___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__TX_PWR_LV_LAA_52___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__TX_PWR_LV_LAA_52___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__TX_PWR_LV_N79_52___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__TX_PWR_LV_N79_52___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__BBF_GAIN_52___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__BBF_GAIN_52___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__UPC_GAIN_52___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__UPC_GAIN_52___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__DA_GAIN_52___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__DA_GAIN_52___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__XPA_GAIN_52___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52__XPA_GAIN_52___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_52___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53 (0x005FDCD4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__IPA_GAIN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__DAC_GAIN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__TX_PWR_LV_LAA_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__TX_PWR_LV_N79_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__BBF_GAIN_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__UPC_GAIN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__DA_GAIN_53___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__XPA_GAIN_53___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__IPA_GAIN_53___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__IPA_GAIN_53___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__DAC_GAIN_53___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__DAC_GAIN_53___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__TX_PWR_LV_LAA_53___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__TX_PWR_LV_LAA_53___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__TX_PWR_LV_N79_53___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__TX_PWR_LV_N79_53___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__BBF_GAIN_53___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__BBF_GAIN_53___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__UPC_GAIN_53___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__UPC_GAIN_53___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__DA_GAIN_53___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__DA_GAIN_53___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__XPA_GAIN_53___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53__XPA_GAIN_53___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_53___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54 (0x005FDCD8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__IPA_GAIN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__DAC_GAIN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__TX_PWR_LV_LAA_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__TX_PWR_LV_N79_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__BBF_GAIN_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__UPC_GAIN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__DA_GAIN_54___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__XPA_GAIN_54___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__IPA_GAIN_54___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__IPA_GAIN_54___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__DAC_GAIN_54___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__DAC_GAIN_54___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__TX_PWR_LV_LAA_54___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__TX_PWR_LV_LAA_54___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__TX_PWR_LV_N79_54___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__TX_PWR_LV_N79_54___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__BBF_GAIN_54___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__BBF_GAIN_54___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__UPC_GAIN_54___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__UPC_GAIN_54___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__DA_GAIN_54___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__DA_GAIN_54___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__XPA_GAIN_54___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54__XPA_GAIN_54___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_54___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55 (0x005FDCDC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__IPA_GAIN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__DAC_GAIN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__TX_PWR_LV_LAA_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__TX_PWR_LV_N79_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__BBF_GAIN_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__UPC_GAIN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__DA_GAIN_55___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__XPA_GAIN_55___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__IPA_GAIN_55___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__IPA_GAIN_55___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__DAC_GAIN_55___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__DAC_GAIN_55___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__TX_PWR_LV_LAA_55___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__TX_PWR_LV_LAA_55___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__TX_PWR_LV_N79_55___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__TX_PWR_LV_N79_55___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__BBF_GAIN_55___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__BBF_GAIN_55___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__UPC_GAIN_55___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__UPC_GAIN_55___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__DA_GAIN_55___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__DA_GAIN_55___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__XPA_GAIN_55___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55__XPA_GAIN_55___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_55___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56 (0x005FDCE0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__IPA_GAIN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__DAC_GAIN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__TX_PWR_LV_LAA_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__TX_PWR_LV_N79_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__BBF_GAIN_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__UPC_GAIN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__DA_GAIN_56___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__XPA_GAIN_56___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__IPA_GAIN_56___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__IPA_GAIN_56___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__DAC_GAIN_56___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__DAC_GAIN_56___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__TX_PWR_LV_LAA_56___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__TX_PWR_LV_LAA_56___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__TX_PWR_LV_N79_56___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__TX_PWR_LV_N79_56___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__BBF_GAIN_56___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__BBF_GAIN_56___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__UPC_GAIN_56___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__UPC_GAIN_56___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__DA_GAIN_56___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__DA_GAIN_56___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__XPA_GAIN_56___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56__XPA_GAIN_56___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_56___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57 (0x005FDCE4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__IPA_GAIN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__DAC_GAIN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__TX_PWR_LV_LAA_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__TX_PWR_LV_N79_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__BBF_GAIN_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__UPC_GAIN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__DA_GAIN_57___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__XPA_GAIN_57___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__IPA_GAIN_57___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__IPA_GAIN_57___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__DAC_GAIN_57___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__DAC_GAIN_57___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__TX_PWR_LV_LAA_57___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__TX_PWR_LV_LAA_57___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__TX_PWR_LV_N79_57___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__TX_PWR_LV_N79_57___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__BBF_GAIN_57___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__BBF_GAIN_57___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__UPC_GAIN_57___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__UPC_GAIN_57___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__DA_GAIN_57___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__DA_GAIN_57___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__XPA_GAIN_57___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57__XPA_GAIN_57___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_57___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58 (0x005FDCE8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__IPA_GAIN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__DAC_GAIN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__TX_PWR_LV_LAA_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__TX_PWR_LV_N79_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__BBF_GAIN_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__UPC_GAIN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__DA_GAIN_58___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__XPA_GAIN_58___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__IPA_GAIN_58___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__IPA_GAIN_58___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__DAC_GAIN_58___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__DAC_GAIN_58___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__TX_PWR_LV_LAA_58___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__TX_PWR_LV_LAA_58___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__TX_PWR_LV_N79_58___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__TX_PWR_LV_N79_58___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__BBF_GAIN_58___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__BBF_GAIN_58___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__UPC_GAIN_58___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__UPC_GAIN_58___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__DA_GAIN_58___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__DA_GAIN_58___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__XPA_GAIN_58___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58__XPA_GAIN_58___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_58___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59 (0x005FDCEC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__IPA_GAIN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__DAC_GAIN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__TX_PWR_LV_LAA_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__TX_PWR_LV_N79_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__BBF_GAIN_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__UPC_GAIN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__DA_GAIN_59___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__XPA_GAIN_59___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__IPA_GAIN_59___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__IPA_GAIN_59___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__DAC_GAIN_59___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__DAC_GAIN_59___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__TX_PWR_LV_LAA_59___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__TX_PWR_LV_LAA_59___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__TX_PWR_LV_N79_59___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__TX_PWR_LV_N79_59___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__BBF_GAIN_59___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__BBF_GAIN_59___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__UPC_GAIN_59___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__UPC_GAIN_59___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__DA_GAIN_59___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__DA_GAIN_59___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__XPA_GAIN_59___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59__XPA_GAIN_59___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_59___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60 (0x005FDCF0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__IPA_GAIN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__DAC_GAIN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__TX_PWR_LV_LAA_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__TX_PWR_LV_N79_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__BBF_GAIN_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__UPC_GAIN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__DA_GAIN_60___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__XPA_GAIN_60___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__IPA_GAIN_60___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__IPA_GAIN_60___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__DAC_GAIN_60___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__DAC_GAIN_60___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__TX_PWR_LV_LAA_60___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__TX_PWR_LV_LAA_60___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__TX_PWR_LV_N79_60___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__TX_PWR_LV_N79_60___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__BBF_GAIN_60___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__BBF_GAIN_60___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__UPC_GAIN_60___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__UPC_GAIN_60___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__DA_GAIN_60___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__DA_GAIN_60___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__XPA_GAIN_60___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60__XPA_GAIN_60___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_60___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61 (0x005FDCF4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__IPA_GAIN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__DAC_GAIN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__TX_PWR_LV_LAA_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__TX_PWR_LV_N79_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__BBF_GAIN_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__UPC_GAIN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__DA_GAIN_61___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__XPA_GAIN_61___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__IPA_GAIN_61___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__IPA_GAIN_61___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__DAC_GAIN_61___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__DAC_GAIN_61___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__TX_PWR_LV_LAA_61___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__TX_PWR_LV_LAA_61___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__TX_PWR_LV_N79_61___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__TX_PWR_LV_N79_61___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__BBF_GAIN_61___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__BBF_GAIN_61___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__UPC_GAIN_61___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__UPC_GAIN_61___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__DA_GAIN_61___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__DA_GAIN_61___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__XPA_GAIN_61___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61__XPA_GAIN_61___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_61___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62 (0x005FDCF8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__IPA_GAIN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__DAC_GAIN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__TX_PWR_LV_LAA_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__TX_PWR_LV_N79_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__BBF_GAIN_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__UPC_GAIN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__DA_GAIN_62___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__XPA_GAIN_62___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__IPA_GAIN_62___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__IPA_GAIN_62___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__DAC_GAIN_62___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__DAC_GAIN_62___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__TX_PWR_LV_LAA_62___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__TX_PWR_LV_LAA_62___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__TX_PWR_LV_N79_62___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__TX_PWR_LV_N79_62___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__BBF_GAIN_62___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__BBF_GAIN_62___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__UPC_GAIN_62___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__UPC_GAIN_62___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__DA_GAIN_62___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__DA_GAIN_62___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__XPA_GAIN_62___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62__XPA_GAIN_62___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_62___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63 (0x005FDCFC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__IPA_GAIN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__DAC_GAIN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__TX_PWR_LV_LAA_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__TX_PWR_LV_N79_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__BBF_GAIN_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__UPC_GAIN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__DA_GAIN_63___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__XPA_GAIN_63___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__IPA_GAIN_63___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__IPA_GAIN_63___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__DAC_GAIN_63___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__DAC_GAIN_63___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__TX_PWR_LV_LAA_63___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__TX_PWR_LV_LAA_63___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__TX_PWR_LV_N79_63___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__TX_PWR_LV_N79_63___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__BBF_GAIN_63___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__BBF_GAIN_63___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__UPC_GAIN_63___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__UPC_GAIN_63___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__DA_GAIN_63___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__DA_GAIN_63___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__XPA_GAIN_63___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63__XPA_GAIN_63___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_63___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64 (0x005FDD00) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__IPA_GAIN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__DAC_GAIN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__TX_PWR_LV_LAA_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__TX_PWR_LV_N79_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__BBF_GAIN_64___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__UPC_GAIN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__DA_GAIN_64___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__XPA_GAIN_64___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__IPA_GAIN_64___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__IPA_GAIN_64___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__DAC_GAIN_64___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__DAC_GAIN_64___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__TX_PWR_LV_LAA_64___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__TX_PWR_LV_LAA_64___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__TX_PWR_LV_N79_64___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__TX_PWR_LV_N79_64___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__BBF_GAIN_64___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__BBF_GAIN_64___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__UPC_GAIN_64___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__UPC_GAIN_64___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__DA_GAIN_64___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__DA_GAIN_64___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__XPA_GAIN_64___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64__XPA_GAIN_64___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_64___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65 (0x005FDD04) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__IPA_GAIN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__DAC_GAIN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__TX_PWR_LV_LAA_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__TX_PWR_LV_N79_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__BBF_GAIN_65___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__UPC_GAIN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__DA_GAIN_65___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__XPA_GAIN_65___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__IPA_GAIN_65___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__IPA_GAIN_65___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__DAC_GAIN_65___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__DAC_GAIN_65___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__TX_PWR_LV_LAA_65___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__TX_PWR_LV_LAA_65___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__TX_PWR_LV_N79_65___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__TX_PWR_LV_N79_65___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__BBF_GAIN_65___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__BBF_GAIN_65___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__UPC_GAIN_65___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__UPC_GAIN_65___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__DA_GAIN_65___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__DA_GAIN_65___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__XPA_GAIN_65___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65__XPA_GAIN_65___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_65___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66 (0x005FDD08) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__IPA_GAIN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__DAC_GAIN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__TX_PWR_LV_LAA_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__TX_PWR_LV_N79_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__BBF_GAIN_66___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__UPC_GAIN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__DA_GAIN_66___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__XPA_GAIN_66___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__IPA_GAIN_66___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__IPA_GAIN_66___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__DAC_GAIN_66___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__DAC_GAIN_66___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__TX_PWR_LV_LAA_66___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__TX_PWR_LV_LAA_66___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__TX_PWR_LV_N79_66___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__TX_PWR_LV_N79_66___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__BBF_GAIN_66___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__BBF_GAIN_66___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__UPC_GAIN_66___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__UPC_GAIN_66___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__DA_GAIN_66___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__DA_GAIN_66___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__XPA_GAIN_66___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66__XPA_GAIN_66___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_66___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67 (0x005FDD0C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__IPA_GAIN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__DAC_GAIN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__TX_PWR_LV_LAA_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__TX_PWR_LV_N79_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__BBF_GAIN_67___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__UPC_GAIN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__DA_GAIN_67___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__XPA_GAIN_67___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__IPA_GAIN_67___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__IPA_GAIN_67___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__DAC_GAIN_67___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__DAC_GAIN_67___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__TX_PWR_LV_LAA_67___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__TX_PWR_LV_LAA_67___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__TX_PWR_LV_N79_67___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__TX_PWR_LV_N79_67___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__BBF_GAIN_67___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__BBF_GAIN_67___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__UPC_GAIN_67___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__UPC_GAIN_67___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__DA_GAIN_67___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__DA_GAIN_67___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__XPA_GAIN_67___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67__XPA_GAIN_67___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_67___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68 (0x005FDD10) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__IPA_GAIN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__DAC_GAIN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__TX_PWR_LV_LAA_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__TX_PWR_LV_N79_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__BBF_GAIN_68___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__UPC_GAIN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__DA_GAIN_68___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__XPA_GAIN_68___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__IPA_GAIN_68___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__IPA_GAIN_68___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__DAC_GAIN_68___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__DAC_GAIN_68___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__TX_PWR_LV_LAA_68___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__TX_PWR_LV_LAA_68___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__TX_PWR_LV_N79_68___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__TX_PWR_LV_N79_68___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__BBF_GAIN_68___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__BBF_GAIN_68___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__UPC_GAIN_68___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__UPC_GAIN_68___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__DA_GAIN_68___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__DA_GAIN_68___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__XPA_GAIN_68___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68__XPA_GAIN_68___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_68___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69 (0x005FDD14) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__IPA_GAIN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__DAC_GAIN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__TX_PWR_LV_LAA_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__TX_PWR_LV_N79_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__BBF_GAIN_69___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__UPC_GAIN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__DA_GAIN_69___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__XPA_GAIN_69___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__IPA_GAIN_69___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__IPA_GAIN_69___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__DAC_GAIN_69___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__DAC_GAIN_69___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__TX_PWR_LV_LAA_69___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__TX_PWR_LV_LAA_69___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__TX_PWR_LV_N79_69___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__TX_PWR_LV_N79_69___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__BBF_GAIN_69___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__BBF_GAIN_69___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__UPC_GAIN_69___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__UPC_GAIN_69___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__DA_GAIN_69___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__DA_GAIN_69___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__XPA_GAIN_69___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69__XPA_GAIN_69___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_69___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70 (0x005FDD18) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__IPA_GAIN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__DAC_GAIN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__TX_PWR_LV_LAA_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__TX_PWR_LV_N79_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__BBF_GAIN_70___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__UPC_GAIN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__DA_GAIN_70___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__XPA_GAIN_70___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__IPA_GAIN_70___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__IPA_GAIN_70___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__DAC_GAIN_70___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__DAC_GAIN_70___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__TX_PWR_LV_LAA_70___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__TX_PWR_LV_LAA_70___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__TX_PWR_LV_N79_70___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__TX_PWR_LV_N79_70___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__BBF_GAIN_70___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__BBF_GAIN_70___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__UPC_GAIN_70___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__UPC_GAIN_70___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__DA_GAIN_70___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__DA_GAIN_70___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__XPA_GAIN_70___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70__XPA_GAIN_70___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_70___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71 (0x005FDD1C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__IPA_GAIN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__DAC_GAIN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__TX_PWR_LV_LAA_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__TX_PWR_LV_N79_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__BBF_GAIN_71___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__UPC_GAIN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__DA_GAIN_71___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__XPA_GAIN_71___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__IPA_GAIN_71___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__IPA_GAIN_71___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__DAC_GAIN_71___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__DAC_GAIN_71___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__TX_PWR_LV_LAA_71___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__TX_PWR_LV_LAA_71___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__TX_PWR_LV_N79_71___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__TX_PWR_LV_N79_71___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__BBF_GAIN_71___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__BBF_GAIN_71___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__UPC_GAIN_71___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__UPC_GAIN_71___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__DA_GAIN_71___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__DA_GAIN_71___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__XPA_GAIN_71___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71__XPA_GAIN_71___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_71___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72 (0x005FDD20) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__IPA_GAIN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__DAC_GAIN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__TX_PWR_LV_LAA_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__TX_PWR_LV_N79_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__BBF_GAIN_72___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__UPC_GAIN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__DA_GAIN_72___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__XPA_GAIN_72___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__IPA_GAIN_72___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__IPA_GAIN_72___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__DAC_GAIN_72___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__DAC_GAIN_72___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__TX_PWR_LV_LAA_72___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__TX_PWR_LV_LAA_72___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__TX_PWR_LV_N79_72___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__TX_PWR_LV_N79_72___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__BBF_GAIN_72___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__BBF_GAIN_72___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__UPC_GAIN_72___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__UPC_GAIN_72___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__DA_GAIN_72___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__DA_GAIN_72___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__XPA_GAIN_72___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72__XPA_GAIN_72___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_72___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73 (0x005FDD24) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__IPA_GAIN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__DAC_GAIN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__TX_PWR_LV_LAA_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__TX_PWR_LV_N79_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__BBF_GAIN_73___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__UPC_GAIN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__DA_GAIN_73___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__XPA_GAIN_73___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__IPA_GAIN_73___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__IPA_GAIN_73___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__DAC_GAIN_73___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__DAC_GAIN_73___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__TX_PWR_LV_LAA_73___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__TX_PWR_LV_LAA_73___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__TX_PWR_LV_N79_73___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__TX_PWR_LV_N79_73___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__BBF_GAIN_73___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__BBF_GAIN_73___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__UPC_GAIN_73___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__UPC_GAIN_73___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__DA_GAIN_73___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__DA_GAIN_73___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__XPA_GAIN_73___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73__XPA_GAIN_73___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_73___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74 (0x005FDD28) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__IPA_GAIN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__DAC_GAIN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__TX_PWR_LV_LAA_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__TX_PWR_LV_N79_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__BBF_GAIN_74___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__UPC_GAIN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__DA_GAIN_74___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__XPA_GAIN_74___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__IPA_GAIN_74___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__IPA_GAIN_74___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__DAC_GAIN_74___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__DAC_GAIN_74___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__TX_PWR_LV_LAA_74___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__TX_PWR_LV_LAA_74___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__TX_PWR_LV_N79_74___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__TX_PWR_LV_N79_74___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__BBF_GAIN_74___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__BBF_GAIN_74___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__UPC_GAIN_74___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__UPC_GAIN_74___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__DA_GAIN_74___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__DA_GAIN_74___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__XPA_GAIN_74___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74__XPA_GAIN_74___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_74___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75 (0x005FDD2C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__IPA_GAIN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__DAC_GAIN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__TX_PWR_LV_LAA_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__TX_PWR_LV_N79_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__BBF_GAIN_75___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__UPC_GAIN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__DA_GAIN_75___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__XPA_GAIN_75___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__IPA_GAIN_75___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__IPA_GAIN_75___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__DAC_GAIN_75___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__DAC_GAIN_75___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__TX_PWR_LV_LAA_75___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__TX_PWR_LV_LAA_75___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__TX_PWR_LV_N79_75___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__TX_PWR_LV_N79_75___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__BBF_GAIN_75___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__BBF_GAIN_75___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__UPC_GAIN_75___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__UPC_GAIN_75___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__DA_GAIN_75___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__DA_GAIN_75___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__XPA_GAIN_75___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75__XPA_GAIN_75___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_75___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76 (0x005FDD30) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__IPA_GAIN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__DAC_GAIN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__TX_PWR_LV_LAA_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__TX_PWR_LV_N79_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__BBF_GAIN_76___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__UPC_GAIN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__DA_GAIN_76___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__XPA_GAIN_76___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__IPA_GAIN_76___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__IPA_GAIN_76___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__DAC_GAIN_76___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__DAC_GAIN_76___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__TX_PWR_LV_LAA_76___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__TX_PWR_LV_LAA_76___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__TX_PWR_LV_N79_76___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__TX_PWR_LV_N79_76___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__BBF_GAIN_76___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__BBF_GAIN_76___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__UPC_GAIN_76___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__UPC_GAIN_76___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__DA_GAIN_76___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__DA_GAIN_76___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__XPA_GAIN_76___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76__XPA_GAIN_76___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_76___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77 (0x005FDD34) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__IPA_GAIN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__DAC_GAIN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__TX_PWR_LV_LAA_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__TX_PWR_LV_N79_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__BBF_GAIN_77___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__UPC_GAIN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__DA_GAIN_77___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__XPA_GAIN_77___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__IPA_GAIN_77___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__IPA_GAIN_77___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__DAC_GAIN_77___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__DAC_GAIN_77___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__TX_PWR_LV_LAA_77___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__TX_PWR_LV_LAA_77___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__TX_PWR_LV_N79_77___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__TX_PWR_LV_N79_77___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__BBF_GAIN_77___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__BBF_GAIN_77___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__UPC_GAIN_77___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__UPC_GAIN_77___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__DA_GAIN_77___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__DA_GAIN_77___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__XPA_GAIN_77___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77__XPA_GAIN_77___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_77___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78 (0x005FDD38) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__IPA_GAIN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__DAC_GAIN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__TX_PWR_LV_LAA_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__TX_PWR_LV_N79_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__BBF_GAIN_78___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__UPC_GAIN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__DA_GAIN_78___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__XPA_GAIN_78___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__IPA_GAIN_78___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__IPA_GAIN_78___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__DAC_GAIN_78___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__DAC_GAIN_78___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__TX_PWR_LV_LAA_78___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__TX_PWR_LV_LAA_78___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__TX_PWR_LV_N79_78___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__TX_PWR_LV_N79_78___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__BBF_GAIN_78___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__BBF_GAIN_78___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__UPC_GAIN_78___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__UPC_GAIN_78___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__DA_GAIN_78___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__DA_GAIN_78___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__XPA_GAIN_78___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78__XPA_GAIN_78___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_78___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79 (0x005FDD3C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__IPA_GAIN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__DAC_GAIN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__TX_PWR_LV_LAA_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__TX_PWR_LV_N79_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__BBF_GAIN_79___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__UPC_GAIN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__DA_GAIN_79___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__XPA_GAIN_79___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__IPA_GAIN_79___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__IPA_GAIN_79___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__DAC_GAIN_79___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__DAC_GAIN_79___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__TX_PWR_LV_LAA_79___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__TX_PWR_LV_LAA_79___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__TX_PWR_LV_N79_79___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__TX_PWR_LV_N79_79___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__BBF_GAIN_79___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__BBF_GAIN_79___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__UPC_GAIN_79___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__UPC_GAIN_79___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__DA_GAIN_79___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__DA_GAIN_79___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__XPA_GAIN_79___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79__XPA_GAIN_79___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_79___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80 (0x005FDD40) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__IPA_GAIN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__DAC_GAIN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__TX_PWR_LV_LAA_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__TX_PWR_LV_N79_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__BBF_GAIN_80___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__UPC_GAIN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__DA_GAIN_80___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__XPA_GAIN_80___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__IPA_GAIN_80___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__IPA_GAIN_80___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__DAC_GAIN_80___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__DAC_GAIN_80___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__TX_PWR_LV_LAA_80___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__TX_PWR_LV_LAA_80___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__TX_PWR_LV_N79_80___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__TX_PWR_LV_N79_80___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__BBF_GAIN_80___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__BBF_GAIN_80___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__UPC_GAIN_80___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__UPC_GAIN_80___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__DA_GAIN_80___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__DA_GAIN_80___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__XPA_GAIN_80___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80__XPA_GAIN_80___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_80___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81 (0x005FDD44) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__IPA_GAIN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__DAC_GAIN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__TX_PWR_LV_LAA_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__TX_PWR_LV_N79_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__BBF_GAIN_81___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__UPC_GAIN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__DA_GAIN_81___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__XPA_GAIN_81___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__IPA_GAIN_81___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__IPA_GAIN_81___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__DAC_GAIN_81___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__DAC_GAIN_81___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__TX_PWR_LV_LAA_81___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__TX_PWR_LV_LAA_81___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__TX_PWR_LV_N79_81___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__TX_PWR_LV_N79_81___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__BBF_GAIN_81___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__BBF_GAIN_81___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__UPC_GAIN_81___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__UPC_GAIN_81___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__DA_GAIN_81___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__DA_GAIN_81___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__XPA_GAIN_81___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81__XPA_GAIN_81___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_81___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82 (0x005FDD48) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__IPA_GAIN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__DAC_GAIN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__TX_PWR_LV_LAA_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__TX_PWR_LV_N79_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__BBF_GAIN_82___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__UPC_GAIN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__DA_GAIN_82___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__XPA_GAIN_82___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__IPA_GAIN_82___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__IPA_GAIN_82___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__DAC_GAIN_82___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__DAC_GAIN_82___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__TX_PWR_LV_LAA_82___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__TX_PWR_LV_LAA_82___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__TX_PWR_LV_N79_82___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__TX_PWR_LV_N79_82___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__BBF_GAIN_82___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__BBF_GAIN_82___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__UPC_GAIN_82___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__UPC_GAIN_82___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__DA_GAIN_82___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__DA_GAIN_82___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__XPA_GAIN_82___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82__XPA_GAIN_82___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_82___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83 (0x005FDD4C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__IPA_GAIN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__DAC_GAIN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__TX_PWR_LV_LAA_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__TX_PWR_LV_N79_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__BBF_GAIN_83___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__UPC_GAIN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__DA_GAIN_83___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__XPA_GAIN_83___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__IPA_GAIN_83___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__IPA_GAIN_83___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__DAC_GAIN_83___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__DAC_GAIN_83___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__TX_PWR_LV_LAA_83___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__TX_PWR_LV_LAA_83___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__TX_PWR_LV_N79_83___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__TX_PWR_LV_N79_83___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__BBF_GAIN_83___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__BBF_GAIN_83___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__UPC_GAIN_83___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__UPC_GAIN_83___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__DA_GAIN_83___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__DA_GAIN_83___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__XPA_GAIN_83___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83__XPA_GAIN_83___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_83___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84 (0x005FDD50) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__IPA_GAIN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__DAC_GAIN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__TX_PWR_LV_LAA_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__TX_PWR_LV_N79_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__BBF_GAIN_84___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__UPC_GAIN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__DA_GAIN_84___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__XPA_GAIN_84___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__IPA_GAIN_84___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__IPA_GAIN_84___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__DAC_GAIN_84___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__DAC_GAIN_84___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__TX_PWR_LV_LAA_84___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__TX_PWR_LV_LAA_84___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__TX_PWR_LV_N79_84___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__TX_PWR_LV_N79_84___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__BBF_GAIN_84___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__BBF_GAIN_84___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__UPC_GAIN_84___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__UPC_GAIN_84___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__DA_GAIN_84___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__DA_GAIN_84___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__XPA_GAIN_84___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84__XPA_GAIN_84___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_84___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85 (0x005FDD54) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__IPA_GAIN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__DAC_GAIN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__TX_PWR_LV_LAA_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__TX_PWR_LV_N79_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__BBF_GAIN_85___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__UPC_GAIN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__DA_GAIN_85___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__XPA_GAIN_85___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__IPA_GAIN_85___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__IPA_GAIN_85___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__DAC_GAIN_85___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__DAC_GAIN_85___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__TX_PWR_LV_LAA_85___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__TX_PWR_LV_LAA_85___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__TX_PWR_LV_N79_85___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__TX_PWR_LV_N79_85___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__BBF_GAIN_85___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__BBF_GAIN_85___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__UPC_GAIN_85___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__UPC_GAIN_85___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__DA_GAIN_85___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__DA_GAIN_85___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__XPA_GAIN_85___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85__XPA_GAIN_85___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_85___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86 (0x005FDD58) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__IPA_GAIN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__DAC_GAIN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__TX_PWR_LV_LAA_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__TX_PWR_LV_N79_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__BBF_GAIN_86___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__UPC_GAIN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__DA_GAIN_86___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__XPA_GAIN_86___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__IPA_GAIN_86___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__IPA_GAIN_86___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__DAC_GAIN_86___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__DAC_GAIN_86___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__TX_PWR_LV_LAA_86___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__TX_PWR_LV_LAA_86___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__TX_PWR_LV_N79_86___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__TX_PWR_LV_N79_86___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__BBF_GAIN_86___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__BBF_GAIN_86___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__UPC_GAIN_86___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__UPC_GAIN_86___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__DA_GAIN_86___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__DA_GAIN_86___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__XPA_GAIN_86___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86__XPA_GAIN_86___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_86___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87 (0x005FDD5C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__IPA_GAIN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__DAC_GAIN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__TX_PWR_LV_LAA_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__TX_PWR_LV_N79_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__BBF_GAIN_87___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__UPC_GAIN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__DA_GAIN_87___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__XPA_GAIN_87___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__IPA_GAIN_87___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__IPA_GAIN_87___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__DAC_GAIN_87___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__DAC_GAIN_87___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__TX_PWR_LV_LAA_87___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__TX_PWR_LV_LAA_87___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__TX_PWR_LV_N79_87___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__TX_PWR_LV_N79_87___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__BBF_GAIN_87___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__BBF_GAIN_87___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__UPC_GAIN_87___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__UPC_GAIN_87___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__DA_GAIN_87___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__DA_GAIN_87___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__XPA_GAIN_87___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87__XPA_GAIN_87___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_87___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88 (0x005FDD60) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__IPA_GAIN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__DAC_GAIN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__TX_PWR_LV_LAA_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__TX_PWR_LV_N79_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__BBF_GAIN_88___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__UPC_GAIN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__DA_GAIN_88___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__XPA_GAIN_88___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__IPA_GAIN_88___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__IPA_GAIN_88___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__DAC_GAIN_88___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__DAC_GAIN_88___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__TX_PWR_LV_LAA_88___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__TX_PWR_LV_LAA_88___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__TX_PWR_LV_N79_88___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__TX_PWR_LV_N79_88___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__BBF_GAIN_88___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__BBF_GAIN_88___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__UPC_GAIN_88___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__UPC_GAIN_88___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__DA_GAIN_88___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__DA_GAIN_88___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__XPA_GAIN_88___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88__XPA_GAIN_88___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_88___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89 (0x005FDD64) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__IPA_GAIN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__DAC_GAIN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__TX_PWR_LV_LAA_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__TX_PWR_LV_N79_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__BBF_GAIN_89___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__UPC_GAIN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__DA_GAIN_89___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__XPA_GAIN_89___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__IPA_GAIN_89___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__IPA_GAIN_89___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__DAC_GAIN_89___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__DAC_GAIN_89___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__TX_PWR_LV_LAA_89___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__TX_PWR_LV_LAA_89___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__TX_PWR_LV_N79_89___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__TX_PWR_LV_N79_89___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__BBF_GAIN_89___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__BBF_GAIN_89___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__UPC_GAIN_89___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__UPC_GAIN_89___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__DA_GAIN_89___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__DA_GAIN_89___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__XPA_GAIN_89___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89__XPA_GAIN_89___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_89___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90 (0x005FDD68) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__IPA_GAIN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__DAC_GAIN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__TX_PWR_LV_LAA_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__TX_PWR_LV_N79_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__BBF_GAIN_90___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__UPC_GAIN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__DA_GAIN_90___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__XPA_GAIN_90___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__IPA_GAIN_90___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__IPA_GAIN_90___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__DAC_GAIN_90___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__DAC_GAIN_90___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__TX_PWR_LV_LAA_90___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__TX_PWR_LV_LAA_90___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__TX_PWR_LV_N79_90___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__TX_PWR_LV_N79_90___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__BBF_GAIN_90___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__BBF_GAIN_90___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__UPC_GAIN_90___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__UPC_GAIN_90___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__DA_GAIN_90___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__DA_GAIN_90___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__XPA_GAIN_90___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90__XPA_GAIN_90___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_90___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91 (0x005FDD6C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__IPA_GAIN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__DAC_GAIN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__TX_PWR_LV_LAA_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__TX_PWR_LV_N79_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__BBF_GAIN_91___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__UPC_GAIN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__DA_GAIN_91___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__XPA_GAIN_91___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__IPA_GAIN_91___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__IPA_GAIN_91___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__DAC_GAIN_91___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__DAC_GAIN_91___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__TX_PWR_LV_LAA_91___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__TX_PWR_LV_LAA_91___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__TX_PWR_LV_N79_91___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__TX_PWR_LV_N79_91___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__BBF_GAIN_91___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__BBF_GAIN_91___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__UPC_GAIN_91___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__UPC_GAIN_91___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__DA_GAIN_91___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__DA_GAIN_91___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__XPA_GAIN_91___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91__XPA_GAIN_91___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_91___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92 (0x005FDD70) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__IPA_GAIN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__DAC_GAIN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__TX_PWR_LV_LAA_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__TX_PWR_LV_N79_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__BBF_GAIN_92___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__UPC_GAIN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__DA_GAIN_92___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__XPA_GAIN_92___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__IPA_GAIN_92___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__IPA_GAIN_92___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__DAC_GAIN_92___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__DAC_GAIN_92___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__TX_PWR_LV_LAA_92___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__TX_PWR_LV_LAA_92___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__TX_PWR_LV_N79_92___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__TX_PWR_LV_N79_92___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__BBF_GAIN_92___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__BBF_GAIN_92___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__UPC_GAIN_92___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__UPC_GAIN_92___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__DA_GAIN_92___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__DA_GAIN_92___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__XPA_GAIN_92___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92__XPA_GAIN_92___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_92___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93 (0x005FDD74) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__IPA_GAIN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__DAC_GAIN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__TX_PWR_LV_LAA_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__TX_PWR_LV_N79_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__BBF_GAIN_93___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__UPC_GAIN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__DA_GAIN_93___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__XPA_GAIN_93___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__IPA_GAIN_93___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__IPA_GAIN_93___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__DAC_GAIN_93___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__DAC_GAIN_93___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__TX_PWR_LV_LAA_93___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__TX_PWR_LV_LAA_93___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__TX_PWR_LV_N79_93___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__TX_PWR_LV_N79_93___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__BBF_GAIN_93___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__BBF_GAIN_93___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__UPC_GAIN_93___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__UPC_GAIN_93___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__DA_GAIN_93___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__DA_GAIN_93___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__XPA_GAIN_93___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93__XPA_GAIN_93___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_93___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94 (0x005FDD78) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__IPA_GAIN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__DAC_GAIN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__TX_PWR_LV_LAA_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__TX_PWR_LV_N79_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__BBF_GAIN_94___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__UPC_GAIN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__DA_GAIN_94___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__XPA_GAIN_94___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__IPA_GAIN_94___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__IPA_GAIN_94___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__DAC_GAIN_94___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__DAC_GAIN_94___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__TX_PWR_LV_LAA_94___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__TX_PWR_LV_LAA_94___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__TX_PWR_LV_N79_94___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__TX_PWR_LV_N79_94___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__BBF_GAIN_94___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__BBF_GAIN_94___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__UPC_GAIN_94___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__UPC_GAIN_94___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__DA_GAIN_94___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__DA_GAIN_94___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__XPA_GAIN_94___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94__XPA_GAIN_94___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_94___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95 (0x005FDD7C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__IPA_GAIN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__DAC_GAIN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__TX_PWR_LV_LAA_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__TX_PWR_LV_N79_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__BBF_GAIN_95___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__UPC_GAIN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__DA_GAIN_95___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__XPA_GAIN_95___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__IPA_GAIN_95___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__IPA_GAIN_95___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__DAC_GAIN_95___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__DAC_GAIN_95___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__TX_PWR_LV_LAA_95___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__TX_PWR_LV_LAA_95___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__TX_PWR_LV_N79_95___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__TX_PWR_LV_N79_95___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__BBF_GAIN_95___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__BBF_GAIN_95___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__UPC_GAIN_95___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__UPC_GAIN_95___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__DA_GAIN_95___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__DA_GAIN_95___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__XPA_GAIN_95___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95__XPA_GAIN_95___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_95___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96 (0x005FDD80) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__IPA_GAIN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__DAC_GAIN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__TX_PWR_LV_LAA_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__TX_PWR_LV_N79_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__BBF_GAIN_96___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__UPC_GAIN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__DA_GAIN_96___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__XPA_GAIN_96___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__IPA_GAIN_96___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__IPA_GAIN_96___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__DAC_GAIN_96___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__DAC_GAIN_96___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__TX_PWR_LV_LAA_96___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__TX_PWR_LV_LAA_96___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__TX_PWR_LV_N79_96___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__TX_PWR_LV_N79_96___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__BBF_GAIN_96___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__BBF_GAIN_96___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__UPC_GAIN_96___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__UPC_GAIN_96___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__DA_GAIN_96___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__DA_GAIN_96___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__XPA_GAIN_96___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96__XPA_GAIN_96___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_96___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97 (0x005FDD84) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__IPA_GAIN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__DAC_GAIN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__TX_PWR_LV_LAA_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__TX_PWR_LV_N79_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__BBF_GAIN_97___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__UPC_GAIN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__DA_GAIN_97___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__XPA_GAIN_97___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__IPA_GAIN_97___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__IPA_GAIN_97___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__DAC_GAIN_97___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__DAC_GAIN_97___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__TX_PWR_LV_LAA_97___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__TX_PWR_LV_LAA_97___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__TX_PWR_LV_N79_97___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__TX_PWR_LV_N79_97___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__BBF_GAIN_97___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__BBF_GAIN_97___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__UPC_GAIN_97___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__UPC_GAIN_97___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__DA_GAIN_97___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__DA_GAIN_97___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__XPA_GAIN_97___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97__XPA_GAIN_97___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_97___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98 (0x005FDD88) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__IPA_GAIN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__DAC_GAIN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__TX_PWR_LV_LAA_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__TX_PWR_LV_N79_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__BBF_GAIN_98___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__UPC_GAIN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__DA_GAIN_98___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__XPA_GAIN_98___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__IPA_GAIN_98___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__IPA_GAIN_98___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__DAC_GAIN_98___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__DAC_GAIN_98___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__TX_PWR_LV_LAA_98___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__TX_PWR_LV_LAA_98___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__TX_PWR_LV_N79_98___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__TX_PWR_LV_N79_98___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__BBF_GAIN_98___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__BBF_GAIN_98___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__UPC_GAIN_98___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__UPC_GAIN_98___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__DA_GAIN_98___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__DA_GAIN_98___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__XPA_GAIN_98___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98__XPA_GAIN_98___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_98___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99 (0x005FDD8C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__IPA_GAIN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__DAC_GAIN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__TX_PWR_LV_LAA_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__TX_PWR_LV_N79_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__BBF_GAIN_99___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__UPC_GAIN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__DA_GAIN_99___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__XPA_GAIN_99___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__IPA_GAIN_99___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__IPA_GAIN_99___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__DAC_GAIN_99___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__DAC_GAIN_99___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__TX_PWR_LV_LAA_99___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__TX_PWR_LV_LAA_99___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__TX_PWR_LV_N79_99___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__TX_PWR_LV_N79_99___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__BBF_GAIN_99___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__BBF_GAIN_99___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__UPC_GAIN_99___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__UPC_GAIN_99___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__DA_GAIN_99___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__DA_GAIN_99___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__XPA_GAIN_99___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99__XPA_GAIN_99___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_99___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100 (0x005FDD90) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__IPA_GAIN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__DAC_GAIN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__TX_PWR_LV_LAA_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__TX_PWR_LV_N79_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__BBF_GAIN_100___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__UPC_GAIN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__DA_GAIN_100___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__XPA_GAIN_100___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__IPA_GAIN_100___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__IPA_GAIN_100___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__DAC_GAIN_100___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__DAC_GAIN_100___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__TX_PWR_LV_LAA_100___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__TX_PWR_LV_LAA_100___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__TX_PWR_LV_N79_100___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__TX_PWR_LV_N79_100___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__BBF_GAIN_100___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__BBF_GAIN_100___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__UPC_GAIN_100___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__UPC_GAIN_100___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__DA_GAIN_100___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__DA_GAIN_100___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__XPA_GAIN_100___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100__XPA_GAIN_100___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_100___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101 (0x005FDD94) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__IPA_GAIN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__DAC_GAIN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__TX_PWR_LV_LAA_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__TX_PWR_LV_N79_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__BBF_GAIN_101___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__UPC_GAIN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__DA_GAIN_101___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__XPA_GAIN_101___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__IPA_GAIN_101___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__IPA_GAIN_101___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__DAC_GAIN_101___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__DAC_GAIN_101___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__TX_PWR_LV_LAA_101___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__TX_PWR_LV_LAA_101___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__TX_PWR_LV_N79_101___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__TX_PWR_LV_N79_101___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__BBF_GAIN_101___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__BBF_GAIN_101___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__UPC_GAIN_101___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__UPC_GAIN_101___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__DA_GAIN_101___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__DA_GAIN_101___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__XPA_GAIN_101___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101__XPA_GAIN_101___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_101___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102 (0x005FDD98) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__IPA_GAIN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__DAC_GAIN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__TX_PWR_LV_LAA_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__TX_PWR_LV_N79_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__BBF_GAIN_102___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__UPC_GAIN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__DA_GAIN_102___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__XPA_GAIN_102___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__IPA_GAIN_102___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__IPA_GAIN_102___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__DAC_GAIN_102___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__DAC_GAIN_102___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__TX_PWR_LV_LAA_102___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__TX_PWR_LV_LAA_102___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__TX_PWR_LV_N79_102___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__TX_PWR_LV_N79_102___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__BBF_GAIN_102___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__BBF_GAIN_102___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__UPC_GAIN_102___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__UPC_GAIN_102___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__DA_GAIN_102___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__DA_GAIN_102___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__XPA_GAIN_102___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102__XPA_GAIN_102___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_102___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103 (0x005FDD9C) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__IPA_GAIN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__DAC_GAIN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__TX_PWR_LV_LAA_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__TX_PWR_LV_N79_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__BBF_GAIN_103___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__UPC_GAIN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__DA_GAIN_103___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__XPA_GAIN_103___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__IPA_GAIN_103___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__IPA_GAIN_103___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__DAC_GAIN_103___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__DAC_GAIN_103___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__TX_PWR_LV_LAA_103___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__TX_PWR_LV_LAA_103___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__TX_PWR_LV_N79_103___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__TX_PWR_LV_N79_103___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__BBF_GAIN_103___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__BBF_GAIN_103___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__UPC_GAIN_103___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__UPC_GAIN_103___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__DA_GAIN_103___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__DA_GAIN_103___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__XPA_GAIN_103___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103__XPA_GAIN_103___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_103___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104 (0x005FDDA0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__IPA_GAIN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__DAC_GAIN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__TX_PWR_LV_LAA_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__TX_PWR_LV_N79_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__BBF_GAIN_104___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__UPC_GAIN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__DA_GAIN_104___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__XPA_GAIN_104___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__IPA_GAIN_104___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__IPA_GAIN_104___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__DAC_GAIN_104___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__DAC_GAIN_104___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__TX_PWR_LV_LAA_104___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__TX_PWR_LV_LAA_104___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__TX_PWR_LV_N79_104___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__TX_PWR_LV_N79_104___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__BBF_GAIN_104___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__BBF_GAIN_104___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__UPC_GAIN_104___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__UPC_GAIN_104___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__DA_GAIN_104___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__DA_GAIN_104___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__XPA_GAIN_104___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104__XPA_GAIN_104___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_104___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105 (0x005FDDA4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__IPA_GAIN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__DAC_GAIN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__TX_PWR_LV_LAA_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__TX_PWR_LV_N79_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__BBF_GAIN_105___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__UPC_GAIN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__DA_GAIN_105___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__XPA_GAIN_105___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__IPA_GAIN_105___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__IPA_GAIN_105___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__DAC_GAIN_105___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__DAC_GAIN_105___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__TX_PWR_LV_LAA_105___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__TX_PWR_LV_LAA_105___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__TX_PWR_LV_N79_105___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__TX_PWR_LV_N79_105___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__BBF_GAIN_105___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__BBF_GAIN_105___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__UPC_GAIN_105___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__UPC_GAIN_105___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__DA_GAIN_105___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__DA_GAIN_105___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__XPA_GAIN_105___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105__XPA_GAIN_105___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_105___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106 (0x005FDDA8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__IPA_GAIN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__DAC_GAIN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__TX_PWR_LV_LAA_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__TX_PWR_LV_N79_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__BBF_GAIN_106___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__UPC_GAIN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__DA_GAIN_106___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__XPA_GAIN_106___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__IPA_GAIN_106___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__IPA_GAIN_106___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__DAC_GAIN_106___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__DAC_GAIN_106___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__TX_PWR_LV_LAA_106___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__TX_PWR_LV_LAA_106___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__TX_PWR_LV_N79_106___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__TX_PWR_LV_N79_106___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__BBF_GAIN_106___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__BBF_GAIN_106___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__UPC_GAIN_106___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__UPC_GAIN_106___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__DA_GAIN_106___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__DA_GAIN_106___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__XPA_GAIN_106___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106__XPA_GAIN_106___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_106___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107 (0x005FDDAC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__IPA_GAIN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__DAC_GAIN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__TX_PWR_LV_LAA_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__TX_PWR_LV_N79_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__BBF_GAIN_107___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__UPC_GAIN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__DA_GAIN_107___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__XPA_GAIN_107___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__IPA_GAIN_107___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__IPA_GAIN_107___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__DAC_GAIN_107___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__DAC_GAIN_107___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__TX_PWR_LV_LAA_107___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__TX_PWR_LV_LAA_107___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__TX_PWR_LV_N79_107___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__TX_PWR_LV_N79_107___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__BBF_GAIN_107___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__BBF_GAIN_107___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__UPC_GAIN_107___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__UPC_GAIN_107___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__DA_GAIN_107___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__DA_GAIN_107___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__XPA_GAIN_107___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107__XPA_GAIN_107___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_107___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108 (0x005FDDB0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__IPA_GAIN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__DAC_GAIN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__TX_PWR_LV_LAA_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__TX_PWR_LV_N79_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__BBF_GAIN_108___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__UPC_GAIN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__DA_GAIN_108___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__XPA_GAIN_108___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__IPA_GAIN_108___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__IPA_GAIN_108___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__DAC_GAIN_108___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__DAC_GAIN_108___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__TX_PWR_LV_LAA_108___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__TX_PWR_LV_LAA_108___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__TX_PWR_LV_N79_108___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__TX_PWR_LV_N79_108___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__BBF_GAIN_108___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__BBF_GAIN_108___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__UPC_GAIN_108___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__UPC_GAIN_108___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__DA_GAIN_108___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__DA_GAIN_108___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__XPA_GAIN_108___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108__XPA_GAIN_108___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_108___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109 (0x005FDDB4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__IPA_GAIN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__DAC_GAIN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__TX_PWR_LV_LAA_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__TX_PWR_LV_N79_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__BBF_GAIN_109___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__UPC_GAIN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__DA_GAIN_109___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__XPA_GAIN_109___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__IPA_GAIN_109___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__IPA_GAIN_109___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__DAC_GAIN_109___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__DAC_GAIN_109___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__TX_PWR_LV_LAA_109___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__TX_PWR_LV_LAA_109___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__TX_PWR_LV_N79_109___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__TX_PWR_LV_N79_109___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__BBF_GAIN_109___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__BBF_GAIN_109___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__UPC_GAIN_109___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__UPC_GAIN_109___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__DA_GAIN_109___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__DA_GAIN_109___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__XPA_GAIN_109___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109__XPA_GAIN_109___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_109___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110 (0x005FDDB8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__IPA_GAIN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__DAC_GAIN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__TX_PWR_LV_LAA_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__TX_PWR_LV_N79_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__BBF_GAIN_110___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__UPC_GAIN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__DA_GAIN_110___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__XPA_GAIN_110___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__IPA_GAIN_110___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__IPA_GAIN_110___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__DAC_GAIN_110___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__DAC_GAIN_110___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__TX_PWR_LV_LAA_110___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__TX_PWR_LV_LAA_110___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__TX_PWR_LV_N79_110___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__TX_PWR_LV_N79_110___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__BBF_GAIN_110___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__BBF_GAIN_110___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__UPC_GAIN_110___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__UPC_GAIN_110___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__DA_GAIN_110___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__DA_GAIN_110___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__XPA_GAIN_110___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110__XPA_GAIN_110___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_110___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111 (0x005FDDBC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__IPA_GAIN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__DAC_GAIN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__TX_PWR_LV_LAA_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__TX_PWR_LV_N79_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__BBF_GAIN_111___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__UPC_GAIN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__DA_GAIN_111___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__XPA_GAIN_111___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__IPA_GAIN_111___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__IPA_GAIN_111___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__DAC_GAIN_111___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__DAC_GAIN_111___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__TX_PWR_LV_LAA_111___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__TX_PWR_LV_LAA_111___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__TX_PWR_LV_N79_111___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__TX_PWR_LV_N79_111___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__BBF_GAIN_111___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__BBF_GAIN_111___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__UPC_GAIN_111___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__UPC_GAIN_111___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__DA_GAIN_111___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__DA_GAIN_111___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__XPA_GAIN_111___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111__XPA_GAIN_111___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_111___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112 (0x005FDDC0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__IPA_GAIN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__DAC_GAIN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__TX_PWR_LV_LAA_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__TX_PWR_LV_N79_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__BBF_GAIN_112___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__UPC_GAIN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__DA_GAIN_112___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__XPA_GAIN_112___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__IPA_GAIN_112___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__IPA_GAIN_112___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__DAC_GAIN_112___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__DAC_GAIN_112___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__TX_PWR_LV_LAA_112___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__TX_PWR_LV_LAA_112___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__TX_PWR_LV_N79_112___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__TX_PWR_LV_N79_112___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__BBF_GAIN_112___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__BBF_GAIN_112___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__UPC_GAIN_112___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__UPC_GAIN_112___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__DA_GAIN_112___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__DA_GAIN_112___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__XPA_GAIN_112___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112__XPA_GAIN_112___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_112___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113 (0x005FDDC4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__IPA_GAIN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__DAC_GAIN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__TX_PWR_LV_LAA_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__TX_PWR_LV_N79_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__BBF_GAIN_113___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__UPC_GAIN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__DA_GAIN_113___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__XPA_GAIN_113___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__IPA_GAIN_113___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__IPA_GAIN_113___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__DAC_GAIN_113___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__DAC_GAIN_113___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__TX_PWR_LV_LAA_113___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__TX_PWR_LV_LAA_113___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__TX_PWR_LV_N79_113___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__TX_PWR_LV_N79_113___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__BBF_GAIN_113___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__BBF_GAIN_113___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__UPC_GAIN_113___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__UPC_GAIN_113___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__DA_GAIN_113___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__DA_GAIN_113___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__XPA_GAIN_113___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113__XPA_GAIN_113___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_113___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114 (0x005FDDC8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__IPA_GAIN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__DAC_GAIN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__TX_PWR_LV_LAA_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__TX_PWR_LV_N79_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__BBF_GAIN_114___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__UPC_GAIN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__DA_GAIN_114___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__XPA_GAIN_114___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__IPA_GAIN_114___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__IPA_GAIN_114___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__DAC_GAIN_114___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__DAC_GAIN_114___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__TX_PWR_LV_LAA_114___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__TX_PWR_LV_LAA_114___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__TX_PWR_LV_N79_114___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__TX_PWR_LV_N79_114___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__BBF_GAIN_114___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__BBF_GAIN_114___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__UPC_GAIN_114___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__UPC_GAIN_114___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__DA_GAIN_114___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__DA_GAIN_114___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__XPA_GAIN_114___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114__XPA_GAIN_114___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_114___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115 (0x005FDDCC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__IPA_GAIN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__DAC_GAIN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__TX_PWR_LV_LAA_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__TX_PWR_LV_N79_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__BBF_GAIN_115___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__UPC_GAIN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__DA_GAIN_115___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__XPA_GAIN_115___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__IPA_GAIN_115___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__IPA_GAIN_115___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__DAC_GAIN_115___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__DAC_GAIN_115___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__TX_PWR_LV_LAA_115___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__TX_PWR_LV_LAA_115___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__TX_PWR_LV_N79_115___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__TX_PWR_LV_N79_115___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__BBF_GAIN_115___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__BBF_GAIN_115___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__UPC_GAIN_115___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__UPC_GAIN_115___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__DA_GAIN_115___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__DA_GAIN_115___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__XPA_GAIN_115___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115__XPA_GAIN_115___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_115___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116 (0x005FDDD0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__IPA_GAIN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__DAC_GAIN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__TX_PWR_LV_LAA_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__TX_PWR_LV_N79_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__BBF_GAIN_116___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__UPC_GAIN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__DA_GAIN_116___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__XPA_GAIN_116___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__IPA_GAIN_116___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__IPA_GAIN_116___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__DAC_GAIN_116___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__DAC_GAIN_116___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__TX_PWR_LV_LAA_116___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__TX_PWR_LV_LAA_116___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__TX_PWR_LV_N79_116___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__TX_PWR_LV_N79_116___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__BBF_GAIN_116___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__BBF_GAIN_116___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__UPC_GAIN_116___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__UPC_GAIN_116___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__DA_GAIN_116___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__DA_GAIN_116___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__XPA_GAIN_116___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116__XPA_GAIN_116___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_116___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117 (0x005FDDD4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__IPA_GAIN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__DAC_GAIN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__TX_PWR_LV_LAA_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__TX_PWR_LV_N79_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__BBF_GAIN_117___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__UPC_GAIN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__DA_GAIN_117___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__XPA_GAIN_117___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__IPA_GAIN_117___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__IPA_GAIN_117___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__DAC_GAIN_117___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__DAC_GAIN_117___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__TX_PWR_LV_LAA_117___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__TX_PWR_LV_LAA_117___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__TX_PWR_LV_N79_117___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__TX_PWR_LV_N79_117___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__BBF_GAIN_117___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__BBF_GAIN_117___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__UPC_GAIN_117___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__UPC_GAIN_117___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__DA_GAIN_117___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__DA_GAIN_117___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__XPA_GAIN_117___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117__XPA_GAIN_117___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_117___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118 (0x005FDDD8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__IPA_GAIN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__DAC_GAIN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__TX_PWR_LV_LAA_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__TX_PWR_LV_N79_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__BBF_GAIN_118___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__UPC_GAIN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__DA_GAIN_118___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__XPA_GAIN_118___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__IPA_GAIN_118___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__IPA_GAIN_118___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__DAC_GAIN_118___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__DAC_GAIN_118___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__TX_PWR_LV_LAA_118___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__TX_PWR_LV_LAA_118___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__TX_PWR_LV_N79_118___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__TX_PWR_LV_N79_118___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__BBF_GAIN_118___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__BBF_GAIN_118___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__UPC_GAIN_118___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__UPC_GAIN_118___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__DA_GAIN_118___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__DA_GAIN_118___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__XPA_GAIN_118___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118__XPA_GAIN_118___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_118___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119 (0x005FDDDC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__IPA_GAIN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__DAC_GAIN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__TX_PWR_LV_LAA_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__TX_PWR_LV_N79_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__BBF_GAIN_119___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__UPC_GAIN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__DA_GAIN_119___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__XPA_GAIN_119___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__IPA_GAIN_119___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__IPA_GAIN_119___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__DAC_GAIN_119___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__DAC_GAIN_119___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__TX_PWR_LV_LAA_119___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__TX_PWR_LV_LAA_119___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__TX_PWR_LV_N79_119___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__TX_PWR_LV_N79_119___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__BBF_GAIN_119___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__BBF_GAIN_119___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__UPC_GAIN_119___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__UPC_GAIN_119___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__DA_GAIN_119___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__DA_GAIN_119___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__XPA_GAIN_119___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119__XPA_GAIN_119___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_119___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120 (0x005FDDE0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__IPA_GAIN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__DAC_GAIN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__TX_PWR_LV_LAA_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__TX_PWR_LV_N79_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__BBF_GAIN_120___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__UPC_GAIN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__DA_GAIN_120___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__XPA_GAIN_120___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__IPA_GAIN_120___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__IPA_GAIN_120___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__DAC_GAIN_120___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__DAC_GAIN_120___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__TX_PWR_LV_LAA_120___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__TX_PWR_LV_LAA_120___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__TX_PWR_LV_N79_120___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__TX_PWR_LV_N79_120___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__BBF_GAIN_120___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__BBF_GAIN_120___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__UPC_GAIN_120___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__UPC_GAIN_120___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__DA_GAIN_120___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__DA_GAIN_120___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__XPA_GAIN_120___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120__XPA_GAIN_120___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_120___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121 (0x005FDDE4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__IPA_GAIN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__DAC_GAIN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__TX_PWR_LV_LAA_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__TX_PWR_LV_N79_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__BBF_GAIN_121___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__UPC_GAIN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__DA_GAIN_121___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__XPA_GAIN_121___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__IPA_GAIN_121___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__IPA_GAIN_121___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__DAC_GAIN_121___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__DAC_GAIN_121___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__TX_PWR_LV_LAA_121___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__TX_PWR_LV_LAA_121___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__TX_PWR_LV_N79_121___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__TX_PWR_LV_N79_121___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__BBF_GAIN_121___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__BBF_GAIN_121___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__UPC_GAIN_121___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__UPC_GAIN_121___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__DA_GAIN_121___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__DA_GAIN_121___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__XPA_GAIN_121___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121__XPA_GAIN_121___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_121___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122 (0x005FDDE8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__IPA_GAIN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__DAC_GAIN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__TX_PWR_LV_LAA_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__TX_PWR_LV_N79_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__BBF_GAIN_122___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__UPC_GAIN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__DA_GAIN_122___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__XPA_GAIN_122___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__IPA_GAIN_122___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__IPA_GAIN_122___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__DAC_GAIN_122___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__DAC_GAIN_122___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__TX_PWR_LV_LAA_122___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__TX_PWR_LV_LAA_122___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__TX_PWR_LV_N79_122___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__TX_PWR_LV_N79_122___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__BBF_GAIN_122___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__BBF_GAIN_122___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__UPC_GAIN_122___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__UPC_GAIN_122___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__DA_GAIN_122___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__DA_GAIN_122___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__XPA_GAIN_122___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122__XPA_GAIN_122___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_122___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123 (0x005FDDEC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__IPA_GAIN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__DAC_GAIN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__TX_PWR_LV_LAA_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__TX_PWR_LV_N79_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__BBF_GAIN_123___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__UPC_GAIN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__DA_GAIN_123___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__XPA_GAIN_123___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__IPA_GAIN_123___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__IPA_GAIN_123___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__DAC_GAIN_123___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__DAC_GAIN_123___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__TX_PWR_LV_LAA_123___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__TX_PWR_LV_LAA_123___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__TX_PWR_LV_N79_123___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__TX_PWR_LV_N79_123___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__BBF_GAIN_123___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__BBF_GAIN_123___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__UPC_GAIN_123___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__UPC_GAIN_123___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__DA_GAIN_123___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__DA_GAIN_123___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__XPA_GAIN_123___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123__XPA_GAIN_123___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_123___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124 (0x005FDDF0) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__IPA_GAIN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__DAC_GAIN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__TX_PWR_LV_LAA_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__TX_PWR_LV_N79_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__BBF_GAIN_124___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__UPC_GAIN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__DA_GAIN_124___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__XPA_GAIN_124___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__IPA_GAIN_124___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__IPA_GAIN_124___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__DAC_GAIN_124___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__DAC_GAIN_124___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__TX_PWR_LV_LAA_124___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__TX_PWR_LV_LAA_124___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__TX_PWR_LV_N79_124___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__TX_PWR_LV_N79_124___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__BBF_GAIN_124___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__BBF_GAIN_124___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__UPC_GAIN_124___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__UPC_GAIN_124___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__DA_GAIN_124___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__DA_GAIN_124___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__XPA_GAIN_124___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124__XPA_GAIN_124___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_124___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125 (0x005FDDF4) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__IPA_GAIN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__DAC_GAIN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__TX_PWR_LV_LAA_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__TX_PWR_LV_N79_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__BBF_GAIN_125___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__UPC_GAIN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__DA_GAIN_125___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__XPA_GAIN_125___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__IPA_GAIN_125___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__IPA_GAIN_125___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__DAC_GAIN_125___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__DAC_GAIN_125___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__TX_PWR_LV_LAA_125___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__TX_PWR_LV_LAA_125___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__TX_PWR_LV_N79_125___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__TX_PWR_LV_N79_125___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__BBF_GAIN_125___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__BBF_GAIN_125___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__UPC_GAIN_125___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__UPC_GAIN_125___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__DA_GAIN_125___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__DA_GAIN_125___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__XPA_GAIN_125___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125__XPA_GAIN_125___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_125___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126 (0x005FDDF8) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__IPA_GAIN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__DAC_GAIN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__TX_PWR_LV_LAA_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__TX_PWR_LV_N79_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__BBF_GAIN_126___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__UPC_GAIN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__DA_GAIN_126___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__XPA_GAIN_126___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__IPA_GAIN_126___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__IPA_GAIN_126___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__DAC_GAIN_126___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__DAC_GAIN_126___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__TX_PWR_LV_LAA_126___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__TX_PWR_LV_LAA_126___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__TX_PWR_LV_N79_126___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__TX_PWR_LV_N79_126___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__BBF_GAIN_126___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__BBF_GAIN_126___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__UPC_GAIN_126___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__UPC_GAIN_126___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__DA_GAIN_126___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__DA_GAIN_126___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__XPA_GAIN_126___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126__XPA_GAIN_126___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_126___S 0 + +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127 (0x005FDDFC) +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127___RWC QCSR_REG_RW +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127___POR 0x00000000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__IPA_GAIN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__DAC_GAIN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__TX_PWR_LV_LAA_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__TX_PWR_LV_N79_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__BBF_GAIN_127___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__UPC_GAIN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__DA_GAIN_127___POR 0x00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__XPA_GAIN_127___POR 0x0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__IPA_GAIN_127___M 0x03800000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__IPA_GAIN_127___S 23 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__DAC_GAIN_127___M 0x00700000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__DAC_GAIN_127___S 20 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__TX_PWR_LV_LAA_127___M 0x00080000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__TX_PWR_LV_LAA_127___S 19 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__TX_PWR_LV_N79_127___M 0x00040000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__TX_PWR_LV_N79_127___S 18 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__BBF_GAIN_127___M 0x0003F000 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__BBF_GAIN_127___S 12 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__UPC_GAIN_127___M 0x00000E00 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__UPC_GAIN_127___S 9 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__DA_GAIN_127___M 0x000001F0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__DA_GAIN_127___S 4 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__XPA_GAIN_127___M 0x0000000F +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127__XPA_GAIN_127___S 0 +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127___M 0x03FFFFFF +#define PHYA_IRON2G_RFA_WL_MEM_5G_CH1_TXGAIN_127___S 0 + + +#define UMAC (0x00A00000) + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL (0x00A20000) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__VALID_BITMAP___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__TAG_MSB___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__HW_SCHD_BUSY___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__NO_OF_ENTRIES___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__READ_ENTRY_ADDR___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__RD_BY_ORDER___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__RW_ADDR___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__VALID_BITMAP___M 0x1C000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__VALID_BITMAP___S 26 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__TAG_MSB___M 0x03000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__TAG_MSB___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__HW_SCHD_BUSY___M 0x00100000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__HW_SCHD_BUSY___S 20 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__NO_OF_ENTRIES___M 0x000FC000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__NO_OF_ENTRIES___S 14 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__READ_ENTRY_ADDR___M 0x00003F00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__READ_ENTRY_ADDR___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__RD_BY_ORDER___M 0x00000080 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__RD_BY_ORDER___S 7 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__RW_ADDR___M 0x0000007E +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__RW_ADDR___S 1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__CLEAR___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL__CLEAR___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL___M 0x1F1FFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_CTL___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D0 (0x00A20004) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D0___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D0___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D0__DATA0___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D0__DATA0___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D0__DATA0___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D0___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D0___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D1 (0x00A20008) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D1___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D1__DATA1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D1__DATA1___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D1__DATA1___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D1___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D2 (0x00A2000C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D2___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D2___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D2__DATA2___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D2__DATA2___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D2__DATA2___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D2___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D2___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D3 (0x00A20010) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D3___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D3___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D3__DATA3___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D3__DATA3___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D3__DATA3___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D3___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_HW_SCHD_TBL_D3___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_0 (0x00A20014) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_0___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_0___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_0__VAL3___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_0__VAL2___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_0__VAL1___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_0__VAL0___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_0__VAL3___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_0__VAL3___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_0__VAL2___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_0__VAL2___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_0__VAL1___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_0__VAL1___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_0__VAL0___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_0__VAL0___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_0___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_0___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_1 (0x00A20018) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_1___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_1__VAL3___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_1__VAL2___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_1__VAL1___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_1__VAL0___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_1__VAL3___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_1__VAL3___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_1__VAL2___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_1__VAL2___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_1__VAL1___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_1__VAL1___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_1__VAL0___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_1__VAL0___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_1___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_2 (0x00A2001C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_2___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_2___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_2__VAL3___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_2__VAL2___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_2__VAL1___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_2__VAL0___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_2__VAL3___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_2__VAL3___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_2__VAL2___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_2__VAL2___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_2__VAL1___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_2__VAL1___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_2__VAL0___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_2__VAL0___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_2___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_2___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_3 (0x00A20020) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_3___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_3___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_3__VAL3___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_3__VAL2___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_3__VAL1___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_3__VAL0___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_3__VAL3___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_3__VAL3___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_3__VAL2___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_3__VAL2___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_3__VAL1___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_3__VAL1___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_3__VAL0___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_3__VAL0___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_3___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI_IX_3___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI (0x00A20024) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI__THRESH_FOR_SCHD___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI__THRESH___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI__THRESH_FOR_SCHD___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI__THRESH_FOR_SCHD___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI__THRESH___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI__THRESH___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_PRI___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_0 (0x00A20028) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_0___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_0___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_0__VALUE3___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_0__VALUE2___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_0__VALUE1___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_0__VALUE0___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_0__VALUE3___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_0__VALUE3___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_0__VALUE2___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_0__VALUE2___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_0__VALUE1___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_0__VALUE1___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_0__VALUE0___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_0__VALUE0___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_0___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_0___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_1 (0x00A2002C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_1___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_1__VALUE3___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_1__VALUE2___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_1__VALUE1___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_1__VALUE0___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_1__VALUE3___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_1__VALUE3___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_1__VALUE2___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_1__VALUE2___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_1__VALUE1___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_1__VALUE1___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_1__VALUE0___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_1__VALUE0___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_1___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_2 (0x00A20030) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_2___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_2___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_2__VALUE3___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_2__VALUE2___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_2__VALUE1___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_2__VALUE0___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_2__VALUE3___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_2__VALUE3___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_2__VALUE2___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_2__VALUE2___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_2__VALUE1___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_2__VALUE1___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_2__VALUE0___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_2__VALUE0___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_2___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_2___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_3 (0x00A20034) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_3___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_3___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_3__VALUE3___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_3__VALUE2___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_3__VALUE1___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_3__VALUE0___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_3__VALUE3___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_3__VALUE3___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_3__VALUE2___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_3__VALUE2___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_3__VALUE1___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_3__VALUE1___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_3__VALUE0___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_3__VALUE0___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_3___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_3___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_4 (0x00A20038) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_4___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_4___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_4__VALUE3___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_4__VALUE2___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_4__VALUE1___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_4__VALUE0___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_4__VALUE3___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_4__VALUE3___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_4__VALUE2___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_4__VALUE2___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_4__VALUE1___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_4__VALUE1___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_4__VALUE0___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_4__VALUE0___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_4___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_4___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_5 (0x00A2003C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_5___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_5___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_5__VALUE3___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_5__VALUE2___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_5__VALUE1___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_5__VALUE0___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_5__VALUE3___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_5__VALUE3___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_5__VALUE2___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_5__VALUE2___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_5__VALUE1___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_5__VALUE1___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_5__VALUE0___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_5__VALUE0___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_5___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_5___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_6 (0x00A20040) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_6___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_6___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_6__VALUE3___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_6__VALUE2___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_6__VALUE1___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_6__VALUE0___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_6__VALUE3___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_6__VALUE3___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_6__VALUE2___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_6__VALUE2___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_6__VALUE1___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_6__VALUE1___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_6__VALUE0___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_6__VALUE0___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_6___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_6___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_7 (0x00A20044) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_7___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_7___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_7__VALUE3___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_7__VALUE2___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_7__VALUE1___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_7__VALUE0___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_7__VALUE3___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_7__VALUE3___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_7__VALUE2___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_7__VALUE2___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_7__VALUE1___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_7__VALUE1___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_7__VALUE0___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_7__VALUE0___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_7___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_7___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_8 (0x00A20048) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_8___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_8___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_8__VALUE3___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_8__VALUE2___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_8__VALUE1___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_8__VALUE0___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_8__VALUE3___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_8__VALUE3___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_8__VALUE2___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_8__VALUE2___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_8__VALUE1___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_8__VALUE1___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_8__VALUE0___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_8__VALUE0___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_8___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_8___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_9 (0x00A2004C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_9___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_9___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_9__VALUE3___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_9__VALUE2___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_9__VALUE1___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_9__VALUE0___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_9__VALUE3___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_9__VALUE3___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_9__VALUE2___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_9__VALUE2___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_9__VALUE1___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_9__VALUE1___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_9__VALUE0___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_9__VALUE0___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_9___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_9___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_10 (0x00A20050) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_10___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_10___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_10__VALUE3___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_10__VALUE2___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_10__VALUE1___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_10__VALUE0___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_10__VALUE3___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_10__VALUE3___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_10__VALUE2___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_10__VALUE2___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_10__VALUE1___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_10__VALUE1___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_10__VALUE0___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_10__VALUE0___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_10___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_WEIGHTS_IX_10___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS (0x00A20054) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS__OTHERS_OFFSET___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS__BA_OFFSET___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS__ACK_OFFSET___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS__CTS_OFFSET___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS__OTHERS_OFFSET___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS__OTHERS_OFFSET___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS__BA_OFFSET___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS__BA_OFFSET___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS__ACK_OFFSET___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS__ACK_OFFSET___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS__CTS_OFFSET___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS__CTS_OFFSET___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL (0x00A20058) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL___POR 0x00000008 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_LNA_SIGNAL_ENABLE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_LTE_CCA_THRESHOLD_ENABLE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_BT_CCA_THRESHOLD_ENABLE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_RX_ANT_MASK___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_USE2X2MODE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_LTE_COEX_OUTPUT_EN___POR 0x1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_MAC_DIS___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_LNA_SIGNAL_ENABLE___M 0x00001000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_LNA_SIGNAL_ENABLE___S 12 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_LTE_CCA_THRESHOLD_ENABLE___M 0x00000800 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_LTE_CCA_THRESHOLD_ENABLE___S 11 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_BT_CCA_THRESHOLD_ENABLE___M 0x00000400 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_BT_CCA_THRESHOLD_ENABLE___S 10 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_RX_ANT_MASK___M 0x00000300 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_RX_ANT_MASK___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_USE2X2MODE___M 0x00000010 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_USE2X2MODE___S 4 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_LTE_COEX_OUTPUT_EN___M 0x00000008 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_LTE_COEX_OUTPUT_EN___S 3 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_MAC_DIS___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL__WMAC1_MAC_DIS___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL___M 0x00001F19 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC1_CTRL___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL (0x00A2005C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL___POR 0x00000008 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_LNA_SIGNAL_ENABLE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_LTE_CCA_THRESHOLD_ENABLE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_BT_CCA_THRESHOLD_ENABLE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_RX_ANT_MASK___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_USE2X2MODE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_LTE_COEX_OUTPUT_EN___POR 0x1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_MAC_DIS___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_LNA_SIGNAL_ENABLE___M 0x00001000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_LNA_SIGNAL_ENABLE___S 12 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_LTE_CCA_THRESHOLD_ENABLE___M 0x00000800 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_LTE_CCA_THRESHOLD_ENABLE___S 11 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_BT_CCA_THRESHOLD_ENABLE___M 0x00000400 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_BT_CCA_THRESHOLD_ENABLE___S 10 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_RX_ANT_MASK___M 0x00000300 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_RX_ANT_MASK___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_USE2X2MODE___M 0x00000010 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_USE2X2MODE___S 4 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_LTE_COEX_OUTPUT_EN___M 0x00000008 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_LTE_COEX_OUTPUT_EN___S 3 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_MAC_DIS___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL__WMAC2_MAC_DIS___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL___M 0x00001F19 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WMAC2_CTRL___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL (0x00A20060) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL___POR 0x12000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__MCI_DIS___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__ARB3_WLAN_IDX___POR 0x2 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__ARB2_WLAN_IDX___POR 0x1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__ARB1_WLAN_IDX___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__WLAN_TX_POWER_THRESH_BT_RX___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__WL_PRIORITY_SW_CTRL___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__BT_AOA_FILTER_MODE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__SWAP___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__CONTINUOUS_EVAL_ENABLE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__BT_RX_PRIORITY_ALLOWS_WLAN_TX_UNSHARED_ANT___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__BT_TX_PRIORITY_ALLOWS_WLAN_TX_SHARED_ANT___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__WLAN_TX_PRIORITY_ALLOWS_BT_RX_SHARED_ANT___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__WLAN_TX_PRIORITY_ALLOWS_BT_TX_SHARED_ANT___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__ONE_STEP_LOOK_AHEAD_ENABLE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__CONCURRENTTX_ENABLE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__MCI_RX_CTRL_DISABLE_TIMESTAMP___POR 0x1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__MCI_DIS___M 0x20000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__MCI_DIS___S 29 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__ARB3_WLAN_IDX___M 0x18000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__ARB3_WLAN_IDX___S 27 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__ARB2_WLAN_IDX___M 0x06000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__ARB2_WLAN_IDX___S 25 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__ARB1_WLAN_IDX___M 0x01800000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__ARB1_WLAN_IDX___S 23 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__WLAN_TX_POWER_THRESH_BT_RX___M 0x007F0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__WLAN_TX_POWER_THRESH_BT_RX___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__WL_PRIORITY_SW_CTRL___M 0x0000F000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__WL_PRIORITY_SW_CTRL___S 12 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__BT_AOA_FILTER_MODE___M 0x00000200 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__BT_AOA_FILTER_MODE___S 9 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__SWAP___M 0x00000100 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__SWAP___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__CONTINUOUS_EVAL_ENABLE___M 0x00000080 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__CONTINUOUS_EVAL_ENABLE___S 7 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__BT_RX_PRIORITY_ALLOWS_WLAN_TX_UNSHARED_ANT___M 0x00000040 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__BT_RX_PRIORITY_ALLOWS_WLAN_TX_UNSHARED_ANT___S 6 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__BT_TX_PRIORITY_ALLOWS_WLAN_TX_SHARED_ANT___M 0x00000020 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__BT_TX_PRIORITY_ALLOWS_WLAN_TX_SHARED_ANT___S 5 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__WLAN_TX_PRIORITY_ALLOWS_BT_RX_SHARED_ANT___M 0x00000010 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__WLAN_TX_PRIORITY_ALLOWS_BT_RX_SHARED_ANT___S 4 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__WLAN_TX_PRIORITY_ALLOWS_BT_TX_SHARED_ANT___M 0x00000008 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__WLAN_TX_PRIORITY_ALLOWS_BT_TX_SHARED_ANT___S 3 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__ONE_STEP_LOOK_AHEAD_ENABLE___M 0x00000004 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__ONE_STEP_LOOK_AHEAD_ENABLE___S 2 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__CONCURRENTTX_ENABLE___M 0x00000002 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__CONCURRENTTX_ENABLE___S 1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__MCI_RX_CTRL_DISABLE_TIMESTAMP___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL__MCI_RX_CTRL_DISABLE_TIMESTAMP___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL___M 0x3FFFF3FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2 (0x00A20064) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2___POR 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WLAN_MAX_TX_PWR_THRESHOLD_DURING_BT_RX_HIGH_PRIORITY___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WLAN3_TX_STATUS_BLANK_ENABLE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WLAN_MAX_TX_PWR_THRESHOLD_DURING_BT_RX_LOW_PRIORITY___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__BT_SHARED_ANT_MASK___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__BT_RX_ALLOW_WL_UNSHARED_CHAIN_TX___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WL_1S_RX_ALLOW_BT_TX___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__DEWEIGHT_RX_ENABLE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__BT_TX_STATUS_BLANK_ENABLE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WLAN2_TX_STATUS_BLANK_ENABLE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WLAN1_TX_STATUS_BLANK_ENABLE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__CONCURRENT_WLAN_WLAN_PWR_BACKOFF_ENABLE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__CONCURRENT_WLAN_WLAN_TX_ENABLE___POR 0x1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WLAN_MAX_TX_PWR_THRESHOLD_DURING_BT_RX_HIGH_PRIORITY___M 0x7F000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WLAN_MAX_TX_PWR_THRESHOLD_DURING_BT_RX_HIGH_PRIORITY___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WLAN3_TX_STATUS_BLANK_ENABLE___M 0x00800000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WLAN3_TX_STATUS_BLANK_ENABLE___S 23 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WLAN_MAX_TX_PWR_THRESHOLD_DURING_BT_RX_LOW_PRIORITY___M 0x007F0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WLAN_MAX_TX_PWR_THRESHOLD_DURING_BT_RX_LOW_PRIORITY___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__BT_SHARED_ANT_MASK___M 0x0000F000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__BT_SHARED_ANT_MASK___S 12 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__BT_RX_ALLOW_WL_UNSHARED_CHAIN_TX___M 0x00000800 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__BT_RX_ALLOW_WL_UNSHARED_CHAIN_TX___S 11 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WL_1S_RX_ALLOW_BT_TX___M 0x00000400 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WL_1S_RX_ALLOW_BT_TX___S 10 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__DEWEIGHT_RX_ENABLE___M 0x00000200 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__DEWEIGHT_RX_ENABLE___S 9 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__BT_TX_STATUS_BLANK_ENABLE___M 0x00000010 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__BT_TX_STATUS_BLANK_ENABLE___S 4 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WLAN2_TX_STATUS_BLANK_ENABLE___M 0x00000008 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WLAN2_TX_STATUS_BLANK_ENABLE___S 3 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WLAN1_TX_STATUS_BLANK_ENABLE___M 0x00000004 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__WLAN1_TX_STATUS_BLANK_ENABLE___S 2 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__CONCURRENT_WLAN_WLAN_PWR_BACKOFF_ENABLE___M 0x00000002 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__CONCURRENT_WLAN_WLAN_PWR_BACKOFF_ENABLE___S 1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__CONCURRENT_WLAN_WLAN_TX_ENABLE___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2__CONCURRENT_WLAN_WLAN_TX_ENABLE___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2___M 0x7FFFFE1F +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL2___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL3 (0x00A20068) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL3___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL3___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL3__DEFAULT_BT_PRIORITY___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL3__JUMPING_OFFSET___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL3__CONT_INFO_TIMEOUT___POR 0x000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL3__DEFAULT_BT_PRIORITY___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL3__DEFAULT_BT_PRIORITY___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL3__JUMPING_OFFSET___M 0x000FF000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL3__JUMPING_OFFSET___S 12 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL3__CONT_INFO_TIMEOUT___M 0x00000FFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL3__CONT_INFO_TIMEOUT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL3___M 0xFF0FFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL3___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4 (0x00A2006C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC3_LTE_BLOCK_SCH_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC3_TXPCU_BLOCK_RESPONSE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC3_SCH_BLOCK_BACKOFF___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC3_FORCE_WAIT_BA___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC2_LTE_BLOCK_SCH_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC2_TXPCU_BLOCK_RESPONSE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC2_SCH_BLOCK_BACKOFF___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC2_FORCE_WAIT_BA___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC1_LTE_BLOCK_SCH_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC1_TXPCU_BLOCK_RESPONSE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC1_SCH_BLOCK_BACKOFF___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC1_FORCE_WAIT_BA___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC3_LTE_BLOCK_SCH_EN___M 0x00008000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC3_LTE_BLOCK_SCH_EN___S 15 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC3_TXPCU_BLOCK_RESPONSE___M 0x00004000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC3_TXPCU_BLOCK_RESPONSE___S 14 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC3_SCH_BLOCK_BACKOFF___M 0x00002000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC3_SCH_BLOCK_BACKOFF___S 13 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC3_FORCE_WAIT_BA___M 0x00001000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC3_FORCE_WAIT_BA___S 12 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC2_LTE_BLOCK_SCH_EN___M 0x00000800 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC2_LTE_BLOCK_SCH_EN___S 11 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC2_TXPCU_BLOCK_RESPONSE___M 0x00000400 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC2_TXPCU_BLOCK_RESPONSE___S 10 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC2_SCH_BLOCK_BACKOFF___M 0x00000200 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC2_SCH_BLOCK_BACKOFF___S 9 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC2_FORCE_WAIT_BA___M 0x00000100 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC2_FORCE_WAIT_BA___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC1_LTE_BLOCK_SCH_EN___M 0x00000008 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC1_LTE_BLOCK_SCH_EN___S 3 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC1_TXPCU_BLOCK_RESPONSE___M 0x00000004 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC1_TXPCU_BLOCK_RESPONSE___S 2 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC1_SCH_BLOCK_BACKOFF___M 0x00000002 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC1_SCH_BLOCK_BACKOFF___S 1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC1_FORCE_WAIT_BA___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4__WMAC1_FORCE_WAIT_BA___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4___M 0x0000FF0F +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL4___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL5 (0x00A20070) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL5___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL5___POR 0xF0789C50 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL5__MAX_BT_OFFSET___POR 0xF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL5__TLV_RESEND_DELAY___POR 0x078 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL5__CONT_INFO_BT_END_TIME___POR 0x271 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL5__MAX_SCH_ITERATION___POR 0x10 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL5__MAX_BT_OFFSET___M 0xF0000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL5__MAX_BT_OFFSET___S 28 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL5__TLV_RESEND_DELAY___M 0x0FFF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL5__TLV_RESEND_DELAY___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL5__CONT_INFO_BT_END_TIME___M 0x0000FFC0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL5__CONT_INFO_BT_END_TIME___S 6 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL5__MAX_SCH_ITERATION___M 0x0000003F +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL5__MAX_SCH_ITERATION___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL5___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL5___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL6 (0x00A20074) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL6___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL6___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL6__JUMPING_OFFSET_TIMEOUT___POR 0x000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL6__BT_PRI_SELECT_BT_END___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL6__JUMPING_OFFSET_TIMEOUT___M 0x0FFF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL6__JUMPING_OFFSET_TIMEOUT___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL6__BT_PRI_SELECT_BT_END___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL6__BT_PRI_SELECT_BT_END___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL6___M 0x0FFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL6___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH1 (0x00A20078) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH1___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH1__BT_TX_PRIORITY_ALT_TX_BASED_SLICE_THRESHOLD___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH1__WLAN_TX_PRIORITY_ALT_TX_BASED_SLICE_THRESHOLD___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH1__BT_TX_PRIORITY_ALT_TX_BASED_SLICE_THRESHOLD___M 0xFFFF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH1__BT_TX_PRIORITY_ALT_TX_BASED_SLICE_THRESHOLD___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH1__WLAN_TX_PRIORITY_ALT_TX_BASED_SLICE_THRESHOLD___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH1__WLAN_TX_PRIORITY_ALT_TX_BASED_SLICE_THRESHOLD___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH1___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH2 (0x00A2007C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH2___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH2___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH2__WLAN_TX_BT_RX_PRIORITY_PWR_BASED_SLICE_THRESHOLD___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH2__WLAN_TX_PRIORITY_BT_RX_PWR_BASED_SLICE_THRESHOLD___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH2__WLAN_TX_BT_RX_PRIORITY_PWR_BASED_SLICE_THRESHOLD___M 0xFFFF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH2__WLAN_TX_BT_RX_PRIORITY_PWR_BASED_SLICE_THRESHOLD___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH2__WLAN_TX_PRIORITY_BT_RX_PWR_BASED_SLICE_THRESHOLD___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH2__WLAN_TX_PRIORITY_BT_RX_PWR_BASED_SLICE_THRESHOLD___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH2___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH2___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH3 (0x00A20080) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH3___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH3___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH3__WLAN_TX_BT_TX_PRIORITY_PWR_BASED_SLICE_THRESHOLD___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH3__WLAN_TX_PRIORITY_BT_TX_PWR_BASED_SLICE_THRESHOLD___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH3__WLAN_TX_BT_TX_PRIORITY_PWR_BASED_SLICE_THRESHOLD___M 0xFFFF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH3__WLAN_TX_BT_TX_PRIORITY_PWR_BASED_SLICE_THRESHOLD___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH3__WLAN_TX_PRIORITY_BT_TX_PWR_BASED_SLICE_THRESHOLD___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH3__WLAN_TX_PRIORITY_BT_TX_PWR_BASED_SLICE_THRESHOLD___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH3___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH3___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH4 (0x00A20084) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH4___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH4___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH4__BT_TX_PRIORITY_WLAN_RX_WINDOW_SIDE_THRESHOLD___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH4__LTE_TX_PRIORITY_WLAN_RX_WINDOW_SIDE_THRESHOLD___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH4__BT_TX_PRIORITY_WLAN_RX_WINDOW_SIDE_THRESHOLD___M 0xFFFF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH4__BT_TX_PRIORITY_WLAN_RX_WINDOW_SIDE_THRESHOLD___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH4__LTE_TX_PRIORITY_WLAN_RX_WINDOW_SIDE_THRESHOLD___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH4__LTE_TX_PRIORITY_WLAN_RX_WINDOW_SIDE_THRESHOLD___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH4___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_THRESH4___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_CTRL1 (0x00A20088) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_CTRL1___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_CTRL1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_CTRL1__MINIMUM_RX_WINDOW_DURATION___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_CTRL1__MINIMUM_RX_WINDOW_DURATION___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_CTRL1__MINIMUM_RX_WINDOW_DURATION___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_CTRL1___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SLICE_CTRL1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT (0x00A2008C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC3_SW_TX_SOFT_ABORT___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC3_SW_TX_HARD_ABORT___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC2_SW_TX_SOFT_ABORT___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC2_SW_TX_HARD_ABORT___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC1_SW_TX_SOFT_ABORT___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC1_SW_TX_HARD_ABORT___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC3_SW_TX_SOFT_ABORT___M 0x00000020 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC3_SW_TX_SOFT_ABORT___S 5 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC3_SW_TX_HARD_ABORT___M 0x00000010 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC3_SW_TX_HARD_ABORT___S 4 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC2_SW_TX_SOFT_ABORT___M 0x00000008 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC2_SW_TX_SOFT_ABORT___S 3 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC2_SW_TX_HARD_ABORT___M 0x00000004 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC2_SW_TX_HARD_ABORT___S 2 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC1_SW_TX_SOFT_ABORT___M 0x00000002 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC1_SW_TX_SOFT_ABORT___S 1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC1_SW_TX_HARD_ABORT___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT__MAC1_SW_TX_HARD_ABORT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT___M 0x0000003F +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SW_TX_ABORT___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_1 (0x00A20090) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_1___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_1__WMAC1_DEFAULT_CCA_THRESHOLD_160___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_1__WMAC1_DEFAULT_CCA_THRESHOLD_80___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_1__WMAC1_DEFAULT_CCA_THRESHOLD_40___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_1__WMAC1_DEFAULT_CCA_THRESHOLD_20___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_1__WMAC1_DEFAULT_CCA_THRESHOLD_160___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_1__WMAC1_DEFAULT_CCA_THRESHOLD_160___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_1__WMAC1_DEFAULT_CCA_THRESHOLD_80___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_1__WMAC1_DEFAULT_CCA_THRESHOLD_80___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_1__WMAC1_DEFAULT_CCA_THRESHOLD_40___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_1__WMAC1_DEFAULT_CCA_THRESHOLD_40___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_1__WMAC1_DEFAULT_CCA_THRESHOLD_20___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_1__WMAC1_DEFAULT_CCA_THRESHOLD_20___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_1___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_2 (0x00A20094) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_2___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_2___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_2__WMAC1_DEFAULT_CCA_THRESHOLD_1___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_2__WMAC1_DEFAULT_CCA_THRESHOLD_1___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_2__WMAC1_DEFAULT_CCA_THRESHOLD_1___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_2___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_2___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_3 (0x00A20098) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_3___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_3___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_3__WMAC2_DEFAULT_CCA_THRESHOLD_160___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_3__WMAC2_DEFAULT_CCA_THRESHOLD_80___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_3__WMAC2_DEFAULT_CCA_THRESHOLD_40___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_3__WMAC2_DEFAULT_CCA_THRESHOLD_20___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_3__WMAC2_DEFAULT_CCA_THRESHOLD_160___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_3__WMAC2_DEFAULT_CCA_THRESHOLD_160___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_3__WMAC2_DEFAULT_CCA_THRESHOLD_80___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_3__WMAC2_DEFAULT_CCA_THRESHOLD_80___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_3__WMAC2_DEFAULT_CCA_THRESHOLD_40___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_3__WMAC2_DEFAULT_CCA_THRESHOLD_40___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_3__WMAC2_DEFAULT_CCA_THRESHOLD_20___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_3__WMAC2_DEFAULT_CCA_THRESHOLD_20___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_3___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_3___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_4 (0x00A2009C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_4___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_4___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_4__WMAC2_DEFAULT_CCA_THRESHOLD_1___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_4__WMAC2_DEFAULT_CCA_THRESHOLD_1___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_4__WMAC2_DEFAULT_CCA_THRESHOLD_1___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_4___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_4___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_5 (0x00A200A0) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_5___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_5___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_5__WMAC1_WAN_TX_CCA_THRESHOLD_160___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_5__WMAC1_WAN_TX_CCA_THRESHOLD_80___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_5__WMAC1_WAN_TX_CCA_THRESHOLD_40___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_5__WMAC1_WAN_TX_CCA_THRESHOLD_20___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_5__WMAC1_WAN_TX_CCA_THRESHOLD_160___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_5__WMAC1_WAN_TX_CCA_THRESHOLD_160___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_5__WMAC1_WAN_TX_CCA_THRESHOLD_80___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_5__WMAC1_WAN_TX_CCA_THRESHOLD_80___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_5__WMAC1_WAN_TX_CCA_THRESHOLD_40___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_5__WMAC1_WAN_TX_CCA_THRESHOLD_40___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_5__WMAC1_WAN_TX_CCA_THRESHOLD_20___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_5__WMAC1_WAN_TX_CCA_THRESHOLD_20___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_5___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_5___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_6 (0x00A200A4) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_6___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_6___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_6__WMAC1_WAN_TX_CCA_THRESHOLD_1___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_6__WMAC1_WAN_TX_CCA_THRESHOLD_1___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_6__WMAC1_WAN_TX_CCA_THRESHOLD_1___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_6___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_6___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_7 (0x00A200A8) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_7___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_7___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_7__WMAC2_WAN_TX_CCA_THRESHOLD_160___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_7__WMAC2_WAN_TX_CCA_THRESHOLD_80___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_7__WMAC2_WAN_TX_CCA_THRESHOLD_40___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_7__WMAC2_WAN_TX_CCA_THRESHOLD_20___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_7__WMAC2_WAN_TX_CCA_THRESHOLD_160___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_7__WMAC2_WAN_TX_CCA_THRESHOLD_160___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_7__WMAC2_WAN_TX_CCA_THRESHOLD_80___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_7__WMAC2_WAN_TX_CCA_THRESHOLD_80___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_7__WMAC2_WAN_TX_CCA_THRESHOLD_40___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_7__WMAC2_WAN_TX_CCA_THRESHOLD_40___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_7__WMAC2_WAN_TX_CCA_THRESHOLD_20___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_7__WMAC2_WAN_TX_CCA_THRESHOLD_20___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_7___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_7___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_8 (0x00A200AC) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_8___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_8___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_8__WMAC2_WAN_TX_CCA_THRESHOLD_1___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_8__WMAC2_WAN_TX_CCA_THRESHOLD_1___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_8__WMAC2_WAN_TX_CCA_THRESHOLD_1___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_8___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_8___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_9 (0x00A200B0) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_9___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_9___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_9__BT_TX_CCA_THRESHOLD_160___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_9__BT_TX_CCA_THRESHOLD_80___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_9__BT_TX_CCA_THRESHOLD_40___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_9__BT_TX_CCA_THRESHOLD_20___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_9__BT_TX_CCA_THRESHOLD_160___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_9__BT_TX_CCA_THRESHOLD_160___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_9__BT_TX_CCA_THRESHOLD_80___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_9__BT_TX_CCA_THRESHOLD_80___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_9__BT_TX_CCA_THRESHOLD_40___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_9__BT_TX_CCA_THRESHOLD_40___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_9__BT_TX_CCA_THRESHOLD_20___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_9__BT_TX_CCA_THRESHOLD_20___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_9___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_9___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_10 (0x00A200B4) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_10___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_10___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_10__BT_TX_CCA_THRESHOLD_1___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_10__BT_TX_CCA_THRESHOLD_1___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_10__BT_TX_CCA_THRESHOLD_1___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_10___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_10___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_11 (0x00A200B8) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_11___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_11___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_11__BT_WAN_TX_CCA_THRESHOLD_160___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_11__BT_WAN_TX_CCA_THRESHOLD_80___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_11__BT_WAN_TX_CCA_THRESHOLD_40___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_11__BT_WAN_TX_CCA_THRESHOLD_20___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_11__BT_WAN_TX_CCA_THRESHOLD_160___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_11__BT_WAN_TX_CCA_THRESHOLD_160___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_11__BT_WAN_TX_CCA_THRESHOLD_80___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_11__BT_WAN_TX_CCA_THRESHOLD_80___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_11__BT_WAN_TX_CCA_THRESHOLD_40___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_11__BT_WAN_TX_CCA_THRESHOLD_40___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_11__BT_WAN_TX_CCA_THRESHOLD_20___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_11__BT_WAN_TX_CCA_THRESHOLD_20___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_11___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_11___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_12 (0x00A200BC) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_12___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_12___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_12__BT_WAN_TX_CCA_THRESHOLD_1___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_12__BT_WAN_TX_CCA_THRESHOLD_1___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_12__BT_WAN_TX_CCA_THRESHOLD_1___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_12___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CCA_THRESHOLD_12___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_POWER_THRESHOLD (0x00A200C0) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_POWER_THRESHOLD___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_POWER_THRESHOLD___POR 0x00000F0F +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_POWER_THRESHOLD__WLAN_WLAN_OTHERANTMAXPWRREFERENCETHRESHOLD___POR 0x0F +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_POWER_THRESHOLD__WLAN_WLAN_SAMEANTMAXPWRREFERENCETHRESHOLD___POR 0x0F +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_POWER_THRESHOLD__WLAN_WLAN_OTHERANTMAXPWRREFERENCETHRESHOLD___M 0x00007F00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_POWER_THRESHOLD__WLAN_WLAN_OTHERANTMAXPWRREFERENCETHRESHOLD___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_POWER_THRESHOLD__WLAN_WLAN_SAMEANTMAXPWRREFERENCETHRESHOLD___M 0x0000007F +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_POWER_THRESHOLD__WLAN_WLAN_SAMEANTMAXPWRREFERENCETHRESHOLD___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_POWER_THRESHOLD___M 0x00007F7F +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_POWER_THRESHOLD___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_0 (0x00A200C4) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_0___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_0___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_0__WLAN_WLAN_SAME_ANT_POWER_ENTRY_3___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_0__WLAN_WLAN_SAME_ANT_POWER_ENTRY_2___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_0__WLAN_WLAN_SAME_ANT_POWER_ENTRY_1___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_0__WLAN_WLAN_SAME_ANT_POWER_ENTRY_0___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_0__WLAN_WLAN_SAME_ANT_POWER_ENTRY_3___M 0x7F000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_0__WLAN_WLAN_SAME_ANT_POWER_ENTRY_3___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_0__WLAN_WLAN_SAME_ANT_POWER_ENTRY_2___M 0x007F0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_0__WLAN_WLAN_SAME_ANT_POWER_ENTRY_2___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_0__WLAN_WLAN_SAME_ANT_POWER_ENTRY_1___M 0x00007F00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_0__WLAN_WLAN_SAME_ANT_POWER_ENTRY_1___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_0__WLAN_WLAN_SAME_ANT_POWER_ENTRY_0___M 0x0000007F +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_0__WLAN_WLAN_SAME_ANT_POWER_ENTRY_0___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_0___M 0x7F7F7F7F +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_0___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_1 (0x00A200C8) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_1___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_1__WLAN_WLAN_SAME_ANT_POWER_ENTRY_7___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_1__WLAN_WLAN_SAME_ANT_POWER_ENTRY_6___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_1__WLAN_WLAN_SAME_ANT_POWER_ENTRY_5___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_1__WLAN_WLAN_SAME_ANT_POWER_ENTRY_4___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_1__WLAN_WLAN_SAME_ANT_POWER_ENTRY_7___M 0x7F000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_1__WLAN_WLAN_SAME_ANT_POWER_ENTRY_7___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_1__WLAN_WLAN_SAME_ANT_POWER_ENTRY_6___M 0x007F0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_1__WLAN_WLAN_SAME_ANT_POWER_ENTRY_6___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_1__WLAN_WLAN_SAME_ANT_POWER_ENTRY_5___M 0x00007F00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_1__WLAN_WLAN_SAME_ANT_POWER_ENTRY_5___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_1__WLAN_WLAN_SAME_ANT_POWER_ENTRY_4___M 0x0000007F +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_1__WLAN_WLAN_SAME_ANT_POWER_ENTRY_4___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_1___M 0x7F7F7F7F +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_2 (0x00A200CC) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_2___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_2___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_2__WLAN_WLAN_SAME_ANT_POWER_ENTRY_11___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_2__WLAN_WLAN_SAME_ANT_POWER_ENTRY_10___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_2__WLAN_WLAN_SAME_ANT_POWER_ENTRY_9___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_2__WLAN_WLAN_SAME_ANT_POWER_ENTRY_8___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_2__WLAN_WLAN_SAME_ANT_POWER_ENTRY_11___M 0x7F000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_2__WLAN_WLAN_SAME_ANT_POWER_ENTRY_11___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_2__WLAN_WLAN_SAME_ANT_POWER_ENTRY_10___M 0x007F0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_2__WLAN_WLAN_SAME_ANT_POWER_ENTRY_10___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_2__WLAN_WLAN_SAME_ANT_POWER_ENTRY_9___M 0x00007F00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_2__WLAN_WLAN_SAME_ANT_POWER_ENTRY_9___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_2__WLAN_WLAN_SAME_ANT_POWER_ENTRY_8___M 0x0000007F +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_2__WLAN_WLAN_SAME_ANT_POWER_ENTRY_8___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_2___M 0x7F7F7F7F +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_2___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_3 (0x00A200D0) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_3___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_3___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_3__WLAN_WLAN_SAME_ANT_POWER_ENTRY_15___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_3__WLAN_WLAN_SAME_ANT_POWER_ENTRY_14___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_3__WLAN_WLAN_SAME_ANT_POWER_ENTRY_13___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_3__WLAN_WLAN_SAME_ANT_POWER_ENTRY_12___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_3__WLAN_WLAN_SAME_ANT_POWER_ENTRY_15___M 0x7F000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_3__WLAN_WLAN_SAME_ANT_POWER_ENTRY_15___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_3__WLAN_WLAN_SAME_ANT_POWER_ENTRY_14___M 0x007F0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_3__WLAN_WLAN_SAME_ANT_POWER_ENTRY_14___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_3__WLAN_WLAN_SAME_ANT_POWER_ENTRY_13___M 0x00007F00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_3__WLAN_WLAN_SAME_ANT_POWER_ENTRY_13___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_3__WLAN_WLAN_SAME_ANT_POWER_ENTRY_12___M 0x0000007F +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_3__WLAN_WLAN_SAME_ANT_POWER_ENTRY_12___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_3___M 0x7F7F7F7F +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_SAME_ANT_POWER_LUT_IX_3___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_0 (0x00A200D4) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_0___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_0___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_0__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_3___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_0__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_2___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_0__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_1___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_0__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_0___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_0__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_3___M 0x7F000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_0__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_3___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_0__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_2___M 0x007F0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_0__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_2___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_0__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_1___M 0x00007F00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_0__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_1___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_0__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_0___M 0x0000007F +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_0__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_0___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_0___M 0x7F7F7F7F +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_0___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_1 (0x00A200D8) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_1___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_1__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_7___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_1__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_6___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_1__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_5___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_1__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_4___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_1__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_7___M 0x7F000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_1__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_7___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_1__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_6___M 0x007F0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_1__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_6___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_1__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_5___M 0x00007F00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_1__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_5___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_1__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_4___M 0x0000007F +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_1__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_4___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_1___M 0x7F7F7F7F +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_2 (0x00A200DC) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_2___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_2___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_2__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_11___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_2__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_10___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_2__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_9___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_2__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_8___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_2__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_11___M 0x7F000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_2__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_11___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_2__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_10___M 0x007F0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_2__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_10___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_2__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_9___M 0x00007F00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_2__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_9___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_2__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_8___M 0x0000007F +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_2__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_8___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_2___M 0x7F7F7F7F +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_2___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_3 (0x00A200E0) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_3___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_3___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_3__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_15___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_3__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_14___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_3__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_13___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_3__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_12___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_3__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_15___M 0x7F000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_3__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_15___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_3__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_14___M 0x007F0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_3__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_14___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_3__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_13___M 0x00007F00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_3__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_13___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_3__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_12___M 0x0000007F +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_3__WLAN_WLAN_OTHER_ANT_POWER_ENTRY_12___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_3___M 0x7F7F7F7F +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_WLAN_OTHER_ANT_POWER_LUT_IX_3___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CONC_TX_POWER_THRESHOLD (0x00A200E4) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CONC_TX_POWER_THRESHOLD___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CONC_TX_POWER_THRESHOLD___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CONC_TX_POWER_THRESHOLD__CONC_BT_POWER_THRESH___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CONC_TX_POWER_THRESHOLD__CONC_BT_POWER_THRESH___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CONC_TX_POWER_THRESHOLD__CONC_BT_POWER_THRESH___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CONC_TX_POWER_THRESHOLD___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CONC_TX_POWER_THRESHOLD___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_1 (0x00A200E8) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_1___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_1__SINGLE_MPDU_ADJUST___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_1__MANAGE_FRAME_ADJUST___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_1__MORE_BIT_ADJUST___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_1__RETRY_BIT_ADJUST___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_1__SINGLE_MPDU_ADJUST___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_1__SINGLE_MPDU_ADJUST___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_1__MANAGE_FRAME_ADJUST___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_1__MANAGE_FRAME_ADJUST___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_1__MORE_BIT_ADJUST___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_1__MORE_BIT_ADJUST___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_1__RETRY_BIT_ADJUST___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_1__RETRY_BIT_ADJUST___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_1___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_2 (0x00A200EC) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_2___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_2___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_2__RX_RATE_ADJUST___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_2__RX_RATE_OFFSET___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_2__RX_RATE_ADJUST___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_2__RX_RATE_ADJUST___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_2__RX_RATE_OFFSET___M 0x0000001F +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_2__RX_RATE_OFFSET___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_2___M 0x0000FF1F +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLRX_PRIORITY_OFFSET_2___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_0 (0x00A200F0) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_0___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_0___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_0__DATA_80MHZ_DATA___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_0__DATA_40MHZ_DATA___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_0__DATA_20MHZ_DATA___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_0__DATA_80MHZ_DATA___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_0__DATA_80MHZ_DATA___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_0__DATA_40MHZ_DATA___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_0__DATA_40MHZ_DATA___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_0__DATA_20MHZ_DATA___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_0__DATA_20MHZ_DATA___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_0___M 0x00FFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_0___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_1 (0x00A200F4) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_1___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_1__DATA_80MHZ_DATA___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_1__DATA_40MHZ_DATA___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_1__DATA_20MHZ_DATA___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_1__DATA_80MHZ_DATA___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_1__DATA_80MHZ_DATA___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_1__DATA_40MHZ_DATA___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_1__DATA_40MHZ_DATA___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_1__DATA_20MHZ_DATA___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_1__DATA_20MHZ_DATA___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_1___M 0x00FFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_2 (0x00A200F8) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_2___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_2___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_2__DATA_80MHZ_DATA___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_2__DATA_40MHZ_DATA___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_2__DATA_20MHZ_DATA___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_2__DATA_80MHZ_DATA___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_2__DATA_80MHZ_DATA___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_2__DATA_40MHZ_DATA___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_2__DATA_40MHZ_DATA___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_2__DATA_20MHZ_DATA___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_2__DATA_20MHZ_DATA___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_2___M 0x00FFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_2___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_3 (0x00A200FC) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_3___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_3___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_3__DATA_80MHZ_DATA___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_3__DATA_40MHZ_DATA___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_3__DATA_20MHZ_DATA___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_3__DATA_80MHZ_DATA___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_3__DATA_80MHZ_DATA___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_3__DATA_40MHZ_DATA___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_3__DATA_40MHZ_DATA___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_3__DATA_20MHZ_DATA___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_3__DATA_20MHZ_DATA___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_3___M 0x00FFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_3___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_4 (0x00A20100) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_4___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_4___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_4__DATA_80MHZ_DATA___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_4__DATA_40MHZ_DATA___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_4__DATA_20MHZ_DATA___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_4__DATA_80MHZ_DATA___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_4__DATA_80MHZ_DATA___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_4__DATA_40MHZ_DATA___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_4__DATA_40MHZ_DATA___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_4__DATA_20MHZ_DATA___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_4__DATA_20MHZ_DATA___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_4___M 0x00FFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_4___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_5 (0x00A20104) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_5___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_5___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_5__DATA_80MHZ_DATA___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_5__DATA_40MHZ_DATA___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_5__DATA_20MHZ_DATA___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_5__DATA_80MHZ_DATA___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_5__DATA_80MHZ_DATA___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_5__DATA_40MHZ_DATA___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_5__DATA_40MHZ_DATA___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_5__DATA_20MHZ_DATA___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_5__DATA_20MHZ_DATA___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_5___M 0x00FFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_5___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_6 (0x00A20108) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_6___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_6___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_6__DATA_80MHZ_DATA___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_6__DATA_40MHZ_DATA___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_6__DATA_20MHZ_DATA___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_6__DATA_80MHZ_DATA___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_6__DATA_80MHZ_DATA___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_6__DATA_40MHZ_DATA___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_6__DATA_40MHZ_DATA___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_6__DATA_20MHZ_DATA___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_6__DATA_20MHZ_DATA___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_6___M 0x00FFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_6___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_7 (0x00A2010C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_7___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_7___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_7__DATA_80MHZ_DATA___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_7__DATA_40MHZ_DATA___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_7__DATA_20MHZ_DATA___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_7__DATA_80MHZ_DATA___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_7__DATA_80MHZ_DATA___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_7__DATA_40MHZ_DATA___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_7__DATA_40MHZ_DATA___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_7__DATA_20MHZ_DATA___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_7__DATA_20MHZ_DATA___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_7___M 0x00FFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_7___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_8 (0x00A20110) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_8___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_8___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_8__DATA_80MHZ_DATA___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_8__DATA_40MHZ_DATA___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_8__DATA_20MHZ_DATA___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_8__DATA_80MHZ_DATA___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_8__DATA_80MHZ_DATA___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_8__DATA_40MHZ_DATA___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_8__DATA_40MHZ_DATA___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_8__DATA_20MHZ_DATA___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_8__DATA_20MHZ_DATA___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_8___M 0x00FFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_8___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_9 (0x00A20114) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_9___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_9___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_9__DATA_80MHZ_DATA___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_9__DATA_40MHZ_DATA___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_9__DATA_20MHZ_DATA___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_9__DATA_80MHZ_DATA___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_9__DATA_80MHZ_DATA___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_9__DATA_40MHZ_DATA___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_9__DATA_40MHZ_DATA___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_9__DATA_20MHZ_DATA___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_9__DATA_20MHZ_DATA___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_9___M 0x00FFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_9___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_10 (0x00A20118) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_10___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_10___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_10__DATA_80MHZ_DATA___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_10__DATA_40MHZ_DATA___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_10__DATA_20MHZ_DATA___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_10__DATA_80MHZ_DATA___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_10__DATA_80MHZ_DATA___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_10__DATA_40MHZ_DATA___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_10__DATA_40MHZ_DATA___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_10__DATA_20MHZ_DATA___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_10__DATA_20MHZ_DATA___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_10___M 0x00FFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAX_TXPWR_IX_10___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_GUARD_PERIOD (0x00A2011C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_GUARD_PERIOD___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_GUARD_PERIOD___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_GUARD_PERIOD__BT_GUARD_PERIOD___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_GUARD_PERIOD__BT_GUARD_PERIOD___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_GUARD_PERIOD__BT_GUARD_PERIOD___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_GUARD_PERIOD___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_GUARD_PERIOD___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_LTE_GUARD_PERIOD (0x00A20120) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_LTE_GUARD_PERIOD___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_LTE_GUARD_PERIOD___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_LTE_GUARD_PERIOD__LTE_GUARD_PERIOD___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_LTE_GUARD_PERIOD__LTE_GUARD_PERIOD___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_LTE_GUARD_PERIOD__LTE_GUARD_PERIOD___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_LTE_GUARD_PERIOD___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_LTE_GUARD_PERIOD___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_20 (0x00A20124) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_20___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_20___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_20__UPPER___POR 0x000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_20__LOWER___POR 0x000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_20__UPPER___M 0x0FFF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_20__UPPER___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_20__LOWER___M 0x00000FFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_20__LOWER___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_20___M 0x0FFF0FFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_20___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_40 (0x00A20128) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_40___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_40___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_40__UPPER___POR 0x000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_40__LOWER___POR 0x000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_40__UPPER___M 0x0FFF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_40__UPPER___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_40__LOWER___M 0x00000FFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_40__LOWER___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_40___M 0x0FFF0FFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_40___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_80 (0x00A2012C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_80___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_80___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_80__UPPER___POR 0x000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_80__LOWER___POR 0x000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_80__UPPER___M 0x0FFF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_80__UPPER___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_80__LOWER___M 0x00000FFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_80__LOWER___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_80___M 0x0FFF0FFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WL_FREQ_80___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_TXRX_CNT_CTRL (0x00A20130) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_TXRX_CNT_CTRL___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_TXRX_CNT_CTRL___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_TXRX_CNT_CTRL__LOW_PRI_LIMIT___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_TXRX_CNT_CTRL__HIGH_PRI_LIMIT___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_TXRX_CNT_CTRL__CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_TXRX_CNT_CTRL__ENABLE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_TXRX_CNT_CTRL__LOW_PRI_LIMIT___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_TXRX_CNT_CTRL__LOW_PRI_LIMIT___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_TXRX_CNT_CTRL__HIGH_PRI_LIMIT___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_TXRX_CNT_CTRL__HIGH_PRI_LIMIT___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_TXRX_CNT_CTRL__CLEAR___M 0x00000002 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_TXRX_CNT_CTRL__CLEAR___S 1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_TXRX_CNT_CTRL__ENABLE___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_TXRX_CNT_CTRL__ENABLE___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_TXRX_CNT_CTRL___M 0x00FFFF03 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_BT_TXRX_CNT_CTRL___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_LCMH_TX_GRANT_ENABLE_MASK (0x00A20134) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_LCMH_TX_GRANT_ENABLE_MASK___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_LCMH_TX_GRANT_ENABLE_MASK___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_LCMH_TX_GRANT_ENABLE_MASK__WMAC2_LCMH_TXRX_ON_ENABLE_MASK___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_LCMH_TX_GRANT_ENABLE_MASK__WMAC2_LCMH_TX_GRANT_ENABLE_MASK___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_LCMH_TX_GRANT_ENABLE_MASK__WMAC1_LCMH_TXRX_ON_ENABLE_MASK___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_LCMH_TX_GRANT_ENABLE_MASK__WMAC1_LCMH_TX_GRANT_ENABLE_MASK___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_LCMH_TX_GRANT_ENABLE_MASK__WMAC2_LCMH_TXRX_ON_ENABLE_MASK___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_LCMH_TX_GRANT_ENABLE_MASK__WMAC2_LCMH_TXRX_ON_ENABLE_MASK___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_LCMH_TX_GRANT_ENABLE_MASK__WMAC2_LCMH_TX_GRANT_ENABLE_MASK___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_LCMH_TX_GRANT_ENABLE_MASK__WMAC2_LCMH_TX_GRANT_ENABLE_MASK___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_LCMH_TX_GRANT_ENABLE_MASK__WMAC1_LCMH_TXRX_ON_ENABLE_MASK___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_LCMH_TX_GRANT_ENABLE_MASK__WMAC1_LCMH_TXRX_ON_ENABLE_MASK___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_LCMH_TX_GRANT_ENABLE_MASK__WMAC1_LCMH_TX_GRANT_ENABLE_MASK___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_LCMH_TX_GRANT_ENABLE_MASK__WMAC1_LCMH_TX_GRANT_ENABLE_MASK___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_LCMH_TX_GRANT_ENABLE_MASK___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_LCMH_TX_GRANT_ENABLE_MASK___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE (0x00A2013C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__PTA2_CLK_GATE_DISABLE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__PTA1_CLK_GATE_DISABLE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__BMH_TOP_CLK_GATE_DISABLE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__SCHD_MGMT_CLK_GATE_DISABLE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__CONFIG_CLK_GATE_DISABLE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__ARB_CLK_GATE_DISABLE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__BMH_CLK_GATE_DISABLE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__PTA2_CLK_GATE_DISABLE___M 0x00000080 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__PTA2_CLK_GATE_DISABLE___S 7 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__PTA1_CLK_GATE_DISABLE___M 0x00000040 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__PTA1_CLK_GATE_DISABLE___S 6 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__BMH_TOP_CLK_GATE_DISABLE___M 0x00000010 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__BMH_TOP_CLK_GATE_DISABLE___S 4 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__SCHD_MGMT_CLK_GATE_DISABLE___M 0x00000008 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__SCHD_MGMT_CLK_GATE_DISABLE___S 3 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__CONFIG_CLK_GATE_DISABLE___M 0x00000004 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__CONFIG_CLK_GATE_DISABLE___S 2 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__ARB_CLK_GATE_DISABLE___M 0x00000002 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__ARB_CLK_GATE_DISABLE___S 1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__BMH_CLK_GATE_DISABLE___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE__BMH_CLK_GATE_DISABLE___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE___M 0x000000DF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CLKGATE_DISABLE___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL (0x00A2018C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL__WLAN_ACTIVE_SEL___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL__WLAN_IN_RX_SEL___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL__WLAN_IN_TX_SEL___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL__TX_RX___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL__PTA_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL__WLAN_ACTIVE_SEL___M 0x000000C0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL__WLAN_ACTIVE_SEL___S 6 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL__WLAN_IN_RX_SEL___M 0x00000030 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL__WLAN_IN_RX_SEL___S 4 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL__WLAN_IN_TX_SEL___M 0x0000000C +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL__WLAN_IN_TX_SEL___S 2 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL__TX_RX___M 0x00000002 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL__TX_RX___S 1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL__PTA_EN___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL__PTA_EN___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MISC_CTRL___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MCI_CONT_INFO_TIMERS (0x00A20190) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MCI_CONT_INFO_TIMERS___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MCI_CONT_INFO_TIMERS___POR 0x00000010 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MCI_CONT_INFO_TIMERS__DELAY_CONT_INFO_TIME___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MCI_CONT_INFO_TIMERS__CONT_RST_TO_INFO_TIME___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MCI_CONT_INFO_TIMERS__CONT_NACK_TIME___POR 0x10 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MCI_CONT_INFO_TIMERS__DELAY_CONT_INFO_TIME___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MCI_CONT_INFO_TIMERS__DELAY_CONT_INFO_TIME___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MCI_CONT_INFO_TIMERS__CONT_RST_TO_INFO_TIME___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MCI_CONT_INFO_TIMERS__CONT_RST_TO_INFO_TIME___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MCI_CONT_INFO_TIMERS__CONT_NACK_TIME___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MCI_CONT_INFO_TIMERS__CONT_NACK_TIME___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MCI_CONT_INFO_TIMERS___M 0x00FFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_MCI_CONT_INFO_TIMERS___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_RX (0x00A20194) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_RX___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_RX___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_RX__CHANNEL___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_RX__RSSI___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_RX__LINK___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_RX__CHANNEL___M 0x007F0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_RX__CHANNEL___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_RX__RSSI___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_RX__RSSI___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_RX__LINK___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_RX__LINK___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_RX___M 0x007FFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_RX___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_TX (0x00A20198) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_TX___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_TX___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_TX__CHANNEL___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_TX__TXPWR___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_TX__LINK___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_TX__CHANNEL___M 0x007F0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_TX__CHANNEL___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_TX__TXPWR___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_TX__TXPWR___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_TX__LINK___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_TX__LINK___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_TX___M 0x007FFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_CONT_INFO_TX___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE (0x00A2019C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE___POR 0x18000C00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE__FIRST_SLOT_TIME___POR 0x18 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE__PRIORITY_TIME___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE__RX_CLEAR_POLARITY___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE__MODE___POR 0x3 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE__FIRST_SLOT_TIME___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE__FIRST_SLOT_TIME___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE__PRIORITY_TIME___M 0x00FC0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE__PRIORITY_TIME___S 18 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE__RX_CLEAR_POLARITY___M 0x00020000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE__RX_CLEAR_POLARITY___S 17 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE__MODE___M 0x00000C00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE__MODE___S 10 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE___M 0xFFFE0C00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE___S 10 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE2 (0x00A201A0) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE2___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE2___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE2__WBCNT_BT_PRIORITY_CTRL___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE2__WBCNT_BT_ACTIVE_CTRL___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE2__WBCNT_BT_PRIORITY_CTRL___M 0x30000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE2__WBCNT_BT_PRIORITY_CTRL___S 28 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE2__WBCNT_BT_ACTIVE_CTRL___M 0x0C000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE2__WBCNT_BT_ACTIVE_CTRL___S 26 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE2___M 0x3C000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE2___S 26 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE3 (0x00A201A4) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE3___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE3___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE3__BT_PRIORITY_EXTEND_THRES___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE3__BT_TX_ON_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE3__DYNAMIC_TOGGLE_WLA_DISABLE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE3__BT_PRIORITY_EXTEND_THRES___M 0xF0000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE3__BT_PRIORITY_EXTEND_THRES___S 28 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE3__BT_TX_ON_EN___M 0x08000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE3__BT_TX_ON_EN___S 27 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE3__DYNAMIC_TOGGLE_WLA_DISABLE___M 0x01000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE3__DYNAMIC_TOGGLE_WLA_DISABLE___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE3___M 0xF9000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE3___S 24 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE4 (0x00A201A8) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE4___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE4___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE4__BT_PRIORITY_EXTEND___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE4__BT_ACTIVE_EXTEND___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE4__BT_PRIORITY_EXTEND___M 0xFFFF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE4__BT_PRIORITY_EXTEND___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE4__BT_ACTIVE_EXTEND___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE4__BT_ACTIVE_EXTEND___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE4___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE4___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE5 (0x00A201AC) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE5___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE5___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE5__TX_ON_SRC___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE5__TX_ON_SRC___M 0x00000008 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE5__TX_ON_SRC___S 3 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE5___M 0x00000008 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BLUETOOTH_MODE5___S 3 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BT_BT (0x00A201B0) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BT_BT___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BT_BT___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BT_BT__WEIGHT___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BT_BT__WEIGHT___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BT_BT__WEIGHT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BT_BT___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PTA_COEX_BT_BT___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7 (0x00A201DC) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7___POR 0x00000434 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__SPARE_FIELD_3___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__SPARE_FIELD_2___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__SPARE_FIELD_1___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__SPARE_FIELD_0___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__BT_STATUS_RESPONSE_FORMAT___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_TLV_NEW_DEBUG_FIELDS_EN___POR 0x1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_BACK_TO_BACK_CONT_INFO_TX_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_WAIT_BEACON_REARB_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_BT_ACTIVE_DECODE_MODE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_STATUS_BROADCAST_NEW_FIELDS_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__PWR_RES_INCR_EN___POR 0x1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__PER_CHAIN_PWR_CTRL_EN___POR 0x1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_MAC_NAP_TLV_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__MODIFIED_MCI_CONT_NACK_EN___POR 0x1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__LTE_RX_WLAN_TX_ALLOWED_WITH_PWR_BKOFF___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__WLAN_POST_PACKET_PRIORITY_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__SPARE_FIELD_3___M 0x80000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__SPARE_FIELD_3___S 31 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__SPARE_FIELD_2___M 0x40000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__SPARE_FIELD_2___S 30 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__SPARE_FIELD_1___M 0x20000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__SPARE_FIELD_1___S 29 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__SPARE_FIELD_0___M 0x10000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__SPARE_FIELD_0___S 28 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__BT_STATUS_RESPONSE_FORMAT___M 0x00000800 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__BT_STATUS_RESPONSE_FORMAT___S 11 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_TLV_NEW_DEBUG_FIELDS_EN___M 0x00000400 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_TLV_NEW_DEBUG_FIELDS_EN___S 10 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_BACK_TO_BACK_CONT_INFO_TX_EN___M 0x00000200 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_BACK_TO_BACK_CONT_INFO_TX_EN___S 9 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_WAIT_BEACON_REARB_EN___M 0x00000100 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_WAIT_BEACON_REARB_EN___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_BT_ACTIVE_DECODE_MODE___M 0x00000080 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_BT_ACTIVE_DECODE_MODE___S 7 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_STATUS_BROADCAST_NEW_FIELDS_EN___M 0x00000040 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_STATUS_BROADCAST_NEW_FIELDS_EN___S 6 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__PWR_RES_INCR_EN___M 0x00000020 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__PWR_RES_INCR_EN___S 5 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__PER_CHAIN_PWR_CTRL_EN___M 0x00000010 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__PER_CHAIN_PWR_CTRL_EN___S 4 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_MAC_NAP_TLV_EN___M 0x00000008 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__COEX_MAC_NAP_TLV_EN___S 3 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__MODIFIED_MCI_CONT_NACK_EN___M 0x00000004 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__MODIFIED_MCI_CONT_NACK_EN___S 2 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__LTE_RX_WLAN_TX_ALLOWED_WITH_PWR_BKOFF___M 0x00000002 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__LTE_RX_WLAN_TX_ALLOWED_WITH_PWR_BKOFF___S 1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__WLAN_POST_PACKET_PRIORITY_EN___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7__WLAN_POST_PACKET_PRIORITY_EN___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7___M 0xF0000FFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_CTRL7___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN1_TX_LTE_RX_PWR_BACKOFF_CFG (0x00A201E0) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN1_TX_LTE_RX_PWR_BACKOFF_CFG___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN1_TX_LTE_RX_PWR_BACKOFF_CFG___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN1_TX_LTE_RX_PWR_BACKOFF_CFG__AUTO_RESP_FRAME_PWR___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN1_TX_LTE_RX_PWR_BACKOFF_CFG__DATA_FRAME_PWR___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN1_TX_LTE_RX_PWR_BACKOFF_CFG__AUTO_RESP_FRAME_PWR___M 0x00007F00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN1_TX_LTE_RX_PWR_BACKOFF_CFG__AUTO_RESP_FRAME_PWR___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN1_TX_LTE_RX_PWR_BACKOFF_CFG__DATA_FRAME_PWR___M 0x0000007F +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN1_TX_LTE_RX_PWR_BACKOFF_CFG__DATA_FRAME_PWR___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN1_TX_LTE_RX_PWR_BACKOFF_CFG___M 0x00007F7F +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN1_TX_LTE_RX_PWR_BACKOFF_CFG___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN2_TX_LTE_RX_PWR_BACKOFF_CFG (0x00A201E4) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN2_TX_LTE_RX_PWR_BACKOFF_CFG___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN2_TX_LTE_RX_PWR_BACKOFF_CFG___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN2_TX_LTE_RX_PWR_BACKOFF_CFG__AUTO_RESP_FRAME_PWR___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN2_TX_LTE_RX_PWR_BACKOFF_CFG__DATA_FRAME_PWR___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN2_TX_LTE_RX_PWR_BACKOFF_CFG__AUTO_RESP_FRAME_PWR___M 0x00007F00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN2_TX_LTE_RX_PWR_BACKOFF_CFG__AUTO_RESP_FRAME_PWR___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN2_TX_LTE_RX_PWR_BACKOFF_CFG__DATA_FRAME_PWR___M 0x0000007F +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN2_TX_LTE_RX_PWR_BACKOFF_CFG__DATA_FRAME_PWR___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN2_TX_LTE_RX_PWR_BACKOFF_CFG___M 0x00007F7F +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN2_TX_LTE_RX_PWR_BACKOFF_CFG___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAC_NAP_THRESHOLD (0x00A201EC) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAC_NAP_THRESHOLD___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAC_NAP_THRESHOLD___POR 0x00000064 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAC_NAP_THRESHOLD__VALUE___POR 0x064 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAC_NAP_THRESHOLD__VALUE___M 0x000003FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAC_NAP_THRESHOLD__VALUE___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAC_NAP_THRESHOLD___M 0x000003FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MAC_NAP_THRESHOLD___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS (0x00A201F0) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS__TRIG_RESP_OTHERS_OFFSET___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS__TRIG_RESP_CTS_OFFSET___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS__TRIG_RESP_BRPOLL_OFFSET___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS__TRIG_RESP_BUF_SIZE_OFFSET___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS__TRIG_RESP_OTHERS_OFFSET___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS__TRIG_RESP_OTHERS_OFFSET___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS__TRIG_RESP_CTS_OFFSET___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS__TRIG_RESP_CTS_OFFSET___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS__TRIG_RESP_BRPOLL_OFFSET___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS__TRIG_RESP_BRPOLL_OFFSET___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS__TRIG_RESP_BUF_SIZE_OFFSET___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS__TRIG_RESP_BUF_SIZE_OFFSET___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_TLV_ASYNC_FIFO_SOFT_RESET (0x00A201F4) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_TLV_ASYNC_FIFO_SOFT_RESET___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_TLV_ASYNC_FIFO_SOFT_RESET___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_TLV_ASYNC_FIFO_SOFT_RESET__WMAC3_RST___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_TLV_ASYNC_FIFO_SOFT_RESET__WMAC2_RST___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_TLV_ASYNC_FIFO_SOFT_RESET__WMAC1_RST___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_TLV_ASYNC_FIFO_SOFT_RESET__WMAC3_RST___M 0x00000004 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_TLV_ASYNC_FIFO_SOFT_RESET__WMAC3_RST___S 2 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_TLV_ASYNC_FIFO_SOFT_RESET__WMAC2_RST___M 0x00000002 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_TLV_ASYNC_FIFO_SOFT_RESET__WMAC2_RST___S 1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_TLV_ASYNC_FIFO_SOFT_RESET__WMAC1_RST___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_TLV_ASYNC_FIFO_SOFT_RESET__WMAC1_RST___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_TLV_ASYNC_FIFO_SOFT_RESET___M 0x00000007 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_TLV_ASYNC_FIFO_SOFT_RESET___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS_1 (0x00A201F8) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS_1___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS_1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS_1__MBA_OFFSET___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS_1__MBA_OFFSET___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS_1__MBA_OFFSET___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS_1___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_OFFSET_WEIGHTS_1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS_1 (0x00A201FC) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS_1___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS_1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS_1__TRIG_RESP_BASIC_OFFSET___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS_1__TRIG_RESP_BASIC_OFFSET___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS_1__TRIG_RESP_BASIC_OFFSET___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS_1___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SELF_GEN_TRIG_RESP_OFFSET_WEIGHTS_1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_COEX_WLAN_BT_ARBITRATION_DISABLE (0x00A20200) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_COEX_WLAN_BT_ARBITRATION_DISABLE___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_COEX_WLAN_BT_ARBITRATION_DISABLE___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_COEX_WLAN_BT_ARBITRATION_DISABLE__DIS_ARBITRATION_FEATURE_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_COEX_WLAN_BT_ARBITRATION_DISABLE__DIS_ARBITRATION___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_COEX_WLAN_BT_ARBITRATION_DISABLE__DIS_ARBITRATION_FEATURE_EN___M 0x00000002 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_COEX_WLAN_BT_ARBITRATION_DISABLE__DIS_ARBITRATION_FEATURE_EN___S 1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_COEX_WLAN_BT_ARBITRATION_DISABLE__DIS_ARBITRATION___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_COEX_WLAN_BT_ARBITRATION_DISABLE__DIS_ARBITRATION___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_COEX_WLAN_BT_ARBITRATION_DISABLE___M 0x00000003 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_COEX_WLAN_BT_ARBITRATION_DISABLE___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1 (0x00A20204) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_SCHD_TBL_FOR_AUTO_RESP_FRAMES_ENABLE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_ALL_AUTO_RESP_FRAMES___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TRIG_RESP_OTHER___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TRIG_RESP_CTS___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TRIG_RESP_BRPOLL___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TRIG_RESP_BUF_SIZE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TRIG_RESP_BASIC___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_MBA___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_CBF_RESPONSE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_RTT_ACK___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_AH_NORMAL_BA___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_AH_NORMAL_ACK___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_AH_NDP_MOD_ACK___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_AH_NDP_BA___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_AH_NDP_ACK___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_AH_NDP_CTS___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_NON_11AH_CTS___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_NON_11AH_BA___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_NON_11AH_ACK___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_SCHD_TBL_FOR_AUTO_RESP_FRAMES_ENABLE___M 0x80000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_SCHD_TBL_FOR_AUTO_RESP_FRAMES_ENABLE___S 31 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_ALL_AUTO_RESP_FRAMES___M 0x40000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_ALL_AUTO_RESP_FRAMES___S 30 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TRIG_RESP_OTHER___M 0x00010000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TRIG_RESP_OTHER___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TRIG_RESP_CTS___M 0x00008000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TRIG_RESP_CTS___S 15 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TRIG_RESP_BRPOLL___M 0x00004000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TRIG_RESP_BRPOLL___S 14 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TRIG_RESP_BUF_SIZE___M 0x00002000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TRIG_RESP_BUF_SIZE___S 13 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TRIG_RESP_BASIC___M 0x00001000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TRIG_RESP_BASIC___S 12 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_MBA___M 0x00000800 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_MBA___S 11 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_CBF_RESPONSE___M 0x00000400 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_CBF_RESPONSE___S 10 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_RTT_ACK___M 0x00000200 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_RTT_ACK___S 9 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_AH_NORMAL_BA___M 0x00000100 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_AH_NORMAL_BA___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_AH_NORMAL_ACK___M 0x00000080 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_AH_NORMAL_ACK___S 7 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_AH_NDP_MOD_ACK___M 0x00000040 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_AH_NDP_MOD_ACK___S 6 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_AH_NDP_BA___M 0x00000020 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_AH_NDP_BA___S 5 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_AH_NDP_ACK___M 0x00000010 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_AH_NDP_ACK___S 4 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_AH_NDP_CTS___M 0x00000008 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_AH_NDP_CTS___S 3 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_NON_11AH_CTS___M 0x00000004 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_NON_11AH_CTS___S 2 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_NON_11AH_BA___M 0x00000002 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_NON_11AH_BA___S 1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_NON_11AH_ACK___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1__DIS_TYP_NON_11AH_ACK___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1___M 0xC001FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2 (0x00A20208) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_SCHD_TBL_FOR_AUTO_RESP_FRAMES_ENABLE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_ALL_AUTO_RESP_FRAMES___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TRIG_RESP_OTHER___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TRIG_RESP_CTS___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TRIG_RESP_BRPOLL___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TRIG_RESP_BUF_SIZE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TRIG_RESP_BASIC___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_MBA___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_CBF_RESPONSE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_RTT_ACK___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_AH_NORMAL_BA___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_AH_NORMAL_ACK___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_AH_NDP_MOD_ACK___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_AH_NDP_BA___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_AH_NDP_ACK___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_AH_NDP_CTS___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_NON_11AH_CTS___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_NON_11AH_BA___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_NON_11AH_ACK___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_SCHD_TBL_FOR_AUTO_RESP_FRAMES_ENABLE___M 0x80000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_SCHD_TBL_FOR_AUTO_RESP_FRAMES_ENABLE___S 31 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_ALL_AUTO_RESP_FRAMES___M 0x40000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_ALL_AUTO_RESP_FRAMES___S 30 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TRIG_RESP_OTHER___M 0x00010000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TRIG_RESP_OTHER___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TRIG_RESP_CTS___M 0x00008000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TRIG_RESP_CTS___S 15 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TRIG_RESP_BRPOLL___M 0x00004000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TRIG_RESP_BRPOLL___S 14 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TRIG_RESP_BUF_SIZE___M 0x00002000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TRIG_RESP_BUF_SIZE___S 13 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TRIG_RESP_BASIC___M 0x00001000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TRIG_RESP_BASIC___S 12 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_MBA___M 0x00000800 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_MBA___S 11 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_CBF_RESPONSE___M 0x00000400 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_CBF_RESPONSE___S 10 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_RTT_ACK___M 0x00000200 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_RTT_ACK___S 9 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_AH_NORMAL_BA___M 0x00000100 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_AH_NORMAL_BA___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_AH_NORMAL_ACK___M 0x00000080 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_AH_NORMAL_ACK___S 7 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_AH_NDP_MOD_ACK___M 0x00000040 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_AH_NDP_MOD_ACK___S 6 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_AH_NDP_BA___M 0x00000020 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_AH_NDP_BA___S 5 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_AH_NDP_ACK___M 0x00000010 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_AH_NDP_ACK___S 4 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_AH_NDP_CTS___M 0x00000008 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_AH_NDP_CTS___S 3 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_NON_11AH_CTS___M 0x00000004 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_NON_11AH_CTS___S 2 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_NON_11AH_BA___M 0x00000002 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_NON_11AH_BA___S 1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_NON_11AH_ACK___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2__DIS_TYP_NON_11AH_ACK___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2___M 0xC001FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_TBL_DIS_FOR_AUTO_RESP_FRAMES_ARB2___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_DIS_TM_WL_BEACON_WEIGHT_FOR_WL_TX (0x00A20210) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_DIS_TM_WL_BEACON_WEIGHT_FOR_WL_TX___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_DIS_TM_WL_BEACON_WEIGHT_FOR_WL_TX___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_DIS_TM_WL_BEACON_WEIGHT_FOR_WL_TX__DIS_WLBEACON_WT_FOR_WLTX_ARB3___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_DIS_TM_WL_BEACON_WEIGHT_FOR_WL_TX__DIS_WLBEACON_WT_FOR_WLTX_ARB2___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_DIS_TM_WL_BEACON_WEIGHT_FOR_WL_TX__DIS_WLBEACON_WT_FOR_WLTX_ARB1___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_DIS_TM_WL_BEACON_WEIGHT_FOR_WL_TX__DIS_WLBEACON_WT_FOR_WLTX_ARB3___M 0x00000004 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_DIS_TM_WL_BEACON_WEIGHT_FOR_WL_TX__DIS_WLBEACON_WT_FOR_WLTX_ARB3___S 2 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_DIS_TM_WL_BEACON_WEIGHT_FOR_WL_TX__DIS_WLBEACON_WT_FOR_WLTX_ARB2___M 0x00000002 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_DIS_TM_WL_BEACON_WEIGHT_FOR_WL_TX__DIS_WLBEACON_WT_FOR_WLTX_ARB2___S 1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_DIS_TM_WL_BEACON_WEIGHT_FOR_WL_TX__DIS_WLBEACON_WT_FOR_WLTX_ARB1___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_DIS_TM_WL_BEACON_WEIGHT_FOR_WL_TX__DIS_WLBEACON_WT_FOR_WLTX_ARB1___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_DIS_TM_WL_BEACON_WEIGHT_FOR_WL_TX___M 0x00000007 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_DIS_TM_WL_BEACON_WEIGHT_FOR_WL_TX___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PASS_BT_INFO_FROM_2GARB_TO_5GARB (0x00A20214) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PASS_BT_INFO_FROM_2GARB_TO_5GARB___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PASS_BT_INFO_FROM_2GARB_TO_5GARB___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PASS_BT_INFO_FROM_2GARB_TO_5GARB__BT_INFO_FROM_2GARB_TO_5GARB_FOR_ARB3___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PASS_BT_INFO_FROM_2GARB_TO_5GARB__BT_INFO_FROM_2GARB_TO_5GARB_FOR_ARB2___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PASS_BT_INFO_FROM_2GARB_TO_5GARB__BT_INFO_FROM_2GARB_TO_5GARB_FOR_ARB3___M 0x00000002 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PASS_BT_INFO_FROM_2GARB_TO_5GARB__BT_INFO_FROM_2GARB_TO_5GARB_FOR_ARB3___S 1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PASS_BT_INFO_FROM_2GARB_TO_5GARB__BT_INFO_FROM_2GARB_TO_5GARB_FOR_ARB2___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PASS_BT_INFO_FROM_2GARB_TO_5GARB__BT_INFO_FROM_2GARB_TO_5GARB_FOR_ARB2___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PASS_BT_INFO_FROM_2GARB_TO_5GARB___M 0x00000003 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_PASS_BT_INFO_FROM_2GARB_TO_5GARB___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX (0x00A20218) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_ONLY_WLTX_AUTORESP_FRAMES_ON_UNSHARED_ANT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_TRIG_RESP_OTHER___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_TRIG_RESP_CTS___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_TRIG_RESP_BRPOLL___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_TRIG_RESP_BUF_SIZE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_TRIG_RESP_BASIC___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_MBA___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_CBF_RESPONSE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_RTT_ACK___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NORMAL_BA___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NORMAL_ACK___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NDP_MOD_ACK___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NDP_BA___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NDP_ACK___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NDP_CTS___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_NON_11AH_CTS___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_NON_11AH_BA___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_NON_11AH_ACK___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_ONLY_WLTX_AUTORESP_FRAMES_ON_UNSHARED_ANT_EN___M 0x80000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_ONLY_WLTX_AUTORESP_FRAMES_ON_UNSHARED_ANT_EN___S 31 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_TRIG_RESP_OTHER___M 0x00010000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_TRIG_RESP_OTHER___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_TRIG_RESP_CTS___M 0x00008000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_TRIG_RESP_CTS___S 15 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_TRIG_RESP_BRPOLL___M 0x00004000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_TRIG_RESP_BRPOLL___S 14 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_TRIG_RESP_BUF_SIZE___M 0x00002000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_TRIG_RESP_BUF_SIZE___S 13 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_TRIG_RESP_BASIC___M 0x00001000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_TRIG_RESP_BASIC___S 12 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_MBA___M 0x00000800 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_MBA___S 11 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_CBF_RESPONSE___M 0x00000400 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_CBF_RESPONSE___S 10 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_RTT_ACK___M 0x00000200 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_RTT_ACK___S 9 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NORMAL_BA___M 0x00000100 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NORMAL_BA___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NORMAL_ACK___M 0x00000080 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NORMAL_ACK___S 7 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NDP_MOD_ACK___M 0x00000040 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NDP_MOD_ACK___S 6 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NDP_BA___M 0x00000020 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NDP_BA___S 5 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NDP_ACK___M 0x00000010 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NDP_ACK___S 4 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NDP_CTS___M 0x00000008 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_AH_NDP_CTS___S 3 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_NON_11AH_CTS___M 0x00000004 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_NON_11AH_CTS___S 2 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_NON_11AH_BA___M 0x00000002 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_NON_11AH_BA___S 1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_NON_11AH_ACK___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX__ALLOW_AUTO_RESP_FRM_TYP_NON_11AH_ACK___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX___M 0x8001FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_ALLOW_AUTORESP_FRAMES_ON_UNSHARED_ANT_WITH_BT_RX___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1 (0x00A2021C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__MCI_WLAN_CONT_RST_RX_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__MCI_WLAN_CONT_RST_TX_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__MCI_WLAN_CONT_INFO_RX_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__MCI_WLAN_CONT_INFO_TX_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__BT_REQ_NACK_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__BT_TX_REQ_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__BT_RX_REQ_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__CONCURRENT_BT_RX_WL_RX_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__CONCURRENT_BT_TX_WL_RX_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__CONCURRENT_BT_RX_WL_TX_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__CONCURRENT_BT_TX_WL_TX_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_NACK_SCHD_BT_REASON_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_NACK_CURRENT_BT_REASON_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_NACK_LCMH_REASON_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__COEX_TX_RESP_ALT_BASED_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__COEX_TX_RESP_DEFAULT_BASED_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_STATUS_RESP_TX_END_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_STATUS_RESP_TX_START_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_STATUS_FES_END_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_STATUS_FES_TX_END_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_STATUS_FES_TX_START_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_FLUSH_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TBTT_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_IN_TX_ABORT_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_AUTO_RESP_REQ_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_ACK_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__MCI_WLAN_CONT_RST_RX_CNT_EN___M 0x10000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__MCI_WLAN_CONT_RST_RX_CNT_EN___S 28 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__MCI_WLAN_CONT_RST_TX_CNT_EN___M 0x08000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__MCI_WLAN_CONT_RST_TX_CNT_EN___S 27 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__MCI_WLAN_CONT_INFO_RX_CNT_EN___M 0x04000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__MCI_WLAN_CONT_INFO_RX_CNT_EN___S 26 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__MCI_WLAN_CONT_INFO_TX_CNT_EN___M 0x02000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__MCI_WLAN_CONT_INFO_TX_CNT_EN___S 25 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__BT_REQ_NACK_CNT_EN___M 0x01000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__BT_REQ_NACK_CNT_EN___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__BT_TX_REQ_CNT_EN___M 0x00800000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__BT_TX_REQ_CNT_EN___S 23 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__BT_RX_REQ_CNT_EN___M 0x00400000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__BT_RX_REQ_CNT_EN___S 22 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__CONCURRENT_BT_RX_WL_RX_CNT_EN___M 0x00200000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__CONCURRENT_BT_RX_WL_RX_CNT_EN___S 21 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__CONCURRENT_BT_TX_WL_RX_CNT_EN___M 0x00100000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__CONCURRENT_BT_TX_WL_RX_CNT_EN___S 20 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__CONCURRENT_BT_RX_WL_TX_CNT_EN___M 0x00080000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__CONCURRENT_BT_RX_WL_TX_CNT_EN___S 19 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__CONCURRENT_BT_TX_WL_TX_CNT_EN___M 0x00040000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__CONCURRENT_BT_TX_WL_TX_CNT_EN___S 18 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_NACK_SCHD_BT_REASON_CNT_EN___M 0x00020000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_NACK_SCHD_BT_REASON_CNT_EN___S 17 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_NACK_CURRENT_BT_REASON_CNT_EN___M 0x00010000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_NACK_CURRENT_BT_REASON_CNT_EN___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT_EN___M 0x00008000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT_EN___S 15 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_NACK_LCMH_REASON_CNT_EN___M 0x00004000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_NACK_LCMH_REASON_CNT_EN___S 14 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT_EN___M 0x00002000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT_EN___S 13 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__COEX_TX_RESP_ALT_BASED_CNT_EN___M 0x00001000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__COEX_TX_RESP_ALT_BASED_CNT_EN___S 12 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__COEX_TX_RESP_DEFAULT_BASED_CNT_EN___M 0x00000800 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__COEX_TX_RESP_DEFAULT_BASED_CNT_EN___S 11 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_STATUS_RESP_TX_END_CNT_EN___M 0x00000400 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_STATUS_RESP_TX_END_CNT_EN___S 10 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_STATUS_RESP_TX_START_CNT_EN___M 0x00000200 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_STATUS_RESP_TX_START_CNT_EN___S 9 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_STATUS_FES_END_CNT_EN___M 0x00000100 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_STATUS_FES_END_CNT_EN___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_STATUS_FES_TX_END_CNT_EN___M 0x00000080 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_STATUS_FES_TX_END_CNT_EN___S 7 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_STATUS_FES_TX_START_CNT_EN___M 0x00000040 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_STATUS_FES_TX_START_CNT_EN___S 6 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_FLUSH_CNT_EN___M 0x00000020 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TX_FLUSH_CNT_EN___S 5 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TBTT_CNT_EN___M 0x00000010 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__TBTT_CNT_EN___S 4 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_IN_TX_ABORT_CNT_EN___M 0x00000008 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_IN_TX_ABORT_CNT_EN___S 3 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_AUTO_RESP_REQ_CNT_EN___M 0x00000004 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_AUTO_RESP_REQ_CNT_EN___S 2 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_ACK_CNT_EN___M 0x00000002 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_ACK_CNT_EN___S 1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_CNT_EN___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1__WL_TX_REQ_CNT_EN___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1___M 0x1FFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2 (0x00A20220) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_TX_REQ_NACK_LCMH_REASON_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__COEX_TX_RESP_ALT_BASED_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__COEX_TX_RESP_DEFAULT_BASED_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_STATUS_RESP_TX_END_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_STATUS_RESP_TX_START_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_STATUS_FES_END_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_STATUS_FES_TX_END_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_STATUS_FES_TX_START_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_FLUSH_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TBTT_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_IN_TX_ABORT_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_TX_AUTO_RESP_REQ_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_TX_REQ_ACK_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_TX_REQ_CNT_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT_EN___M 0x00008000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT_EN___S 15 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_TX_REQ_NACK_LCMH_REASON_CNT_EN___M 0x00004000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_TX_REQ_NACK_LCMH_REASON_CNT_EN___S 14 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT_EN___M 0x00002000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT_EN___S 13 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__COEX_TX_RESP_ALT_BASED_CNT_EN___M 0x00001000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__COEX_TX_RESP_ALT_BASED_CNT_EN___S 12 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__COEX_TX_RESP_DEFAULT_BASED_CNT_EN___M 0x00000800 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__COEX_TX_RESP_DEFAULT_BASED_CNT_EN___S 11 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_STATUS_RESP_TX_END_CNT_EN___M 0x00000400 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_STATUS_RESP_TX_END_CNT_EN___S 10 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_STATUS_RESP_TX_START_CNT_EN___M 0x00000200 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_STATUS_RESP_TX_START_CNT_EN___S 9 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_STATUS_FES_END_CNT_EN___M 0x00000100 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_STATUS_FES_END_CNT_EN___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_STATUS_FES_TX_END_CNT_EN___M 0x00000080 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_STATUS_FES_TX_END_CNT_EN___S 7 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_STATUS_FES_TX_START_CNT_EN___M 0x00000040 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_STATUS_FES_TX_START_CNT_EN___S 6 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_FLUSH_CNT_EN___M 0x00000020 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TX_FLUSH_CNT_EN___S 5 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TBTT_CNT_EN___M 0x00000010 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__TBTT_CNT_EN___S 4 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_IN_TX_ABORT_CNT_EN___M 0x00000008 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_IN_TX_ABORT_CNT_EN___S 3 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_TX_AUTO_RESP_REQ_CNT_EN___M 0x00000004 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_TX_AUTO_RESP_REQ_CNT_EN___S 2 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_TX_REQ_ACK_CNT_EN___M 0x00000002 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_TX_REQ_ACK_CNT_EN___S 1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_TX_REQ_CNT_EN___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2__WL_TX_REQ_CNT_EN___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_EN_CNTRL_ARB2___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1 (0x00A20228) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__MCI_WLAN_CONT_RST_RX_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__MCI_WLAN_CONT_RST_TX_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__MCI_WLAN_CONT_INFO_RX_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__MCI_WLAN_CONT_INFO_TX_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__BT_REQ_NACK_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__BT_TX_REQ_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__BT_RX_REQ_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__CONCURRENT_BT_RX_WL_RX_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__CONCURRENT_BT_TX_WL_RX_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__CONCURRENT_BT_RX_WL_TX_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__CONCURRENT_BT_TX_WL_TX_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_NACK_SCHD_BT_REASON_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_NACK_CURRENT_BT_REASON_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_NACK_LCMH_REASON_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__COEX_TX_RESP_ALT_BASED_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__COEX_TX_RESP_DEFAULT_BASED_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_STATUS_RESP_TX_END_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_STATUS_RESP_TX_START_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_STATUS_FES_END_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_STATUS_FES_TX_END_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_STATUS_FES_TX_START_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_FLUSH_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TBTT_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_IN_TX_ABORT_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_AUTO_RESP_REQ_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_ACK_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__MCI_WLAN_CONT_RST_RX_CNT_CLEAR___M 0x10000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__MCI_WLAN_CONT_RST_RX_CNT_CLEAR___S 28 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__MCI_WLAN_CONT_RST_TX_CNT_CLEAR___M 0x08000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__MCI_WLAN_CONT_RST_TX_CNT_CLEAR___S 27 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__MCI_WLAN_CONT_INFO_RX_CNT_CLEAR___M 0x04000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__MCI_WLAN_CONT_INFO_RX_CNT_CLEAR___S 26 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__MCI_WLAN_CONT_INFO_TX_CNT_CLEAR___M 0x02000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__MCI_WLAN_CONT_INFO_TX_CNT_CLEAR___S 25 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__BT_REQ_NACK_CNT_CLEAR___M 0x01000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__BT_REQ_NACK_CNT_CLEAR___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__BT_TX_REQ_CNT_CLEAR___M 0x00800000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__BT_TX_REQ_CNT_CLEAR___S 23 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__BT_RX_REQ_CNT_CLEAR___M 0x00400000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__BT_RX_REQ_CNT_CLEAR___S 22 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__CONCURRENT_BT_RX_WL_RX_CNT_CLEAR___M 0x00200000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__CONCURRENT_BT_RX_WL_RX_CNT_CLEAR___S 21 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__CONCURRENT_BT_TX_WL_RX_CNT_CLEAR___M 0x00100000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__CONCURRENT_BT_TX_WL_RX_CNT_CLEAR___S 20 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__CONCURRENT_BT_RX_WL_TX_CNT_CLEAR___M 0x00080000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__CONCURRENT_BT_RX_WL_TX_CNT_CLEAR___S 19 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__CONCURRENT_BT_TX_WL_TX_CNT_CLEAR___M 0x00040000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__CONCURRENT_BT_TX_WL_TX_CNT_CLEAR___S 18 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_NACK_SCHD_BT_REASON_CNT_CLEAR___M 0x00020000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_NACK_SCHD_BT_REASON_CNT_CLEAR___S 17 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_NACK_CURRENT_BT_REASON_CNT_CLEAR___M 0x00010000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_NACK_CURRENT_BT_REASON_CNT_CLEAR___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT_CLEAR___M 0x00008000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT_CLEAR___S 15 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_NACK_LCMH_REASON_CNT_CLEAR___M 0x00004000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_NACK_LCMH_REASON_CNT_CLEAR___S 14 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT_CLEAR___M 0x00002000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT_CLEAR___S 13 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__COEX_TX_RESP_ALT_BASED_CNT_CLEAR___M 0x00001000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__COEX_TX_RESP_ALT_BASED_CNT_CLEAR___S 12 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__COEX_TX_RESP_DEFAULT_BASED_CNT_CLEAR___M 0x00000800 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__COEX_TX_RESP_DEFAULT_BASED_CNT_CLEAR___S 11 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_STATUS_RESP_TX_END_CNT_CLEAR___M 0x00000400 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_STATUS_RESP_TX_END_CNT_CLEAR___S 10 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_STATUS_RESP_TX_START_CNT_CLEAR___M 0x00000200 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_STATUS_RESP_TX_START_CNT_CLEAR___S 9 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_STATUS_FES_END_CNT_CLEAR___M 0x00000100 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_STATUS_FES_END_CNT_CLEAR___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_STATUS_FES_TX_END_CNT_CLEAR___M 0x00000080 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_STATUS_FES_TX_END_CNT_CLEAR___S 7 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_STATUS_FES_TX_START_CNT_CLEAR___M 0x00000040 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_STATUS_FES_TX_START_CNT_CLEAR___S 6 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_FLUSH_CNT_CLEAR___M 0x00000020 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TX_FLUSH_CNT_CLEAR___S 5 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TBTT_CNT_CLEAR___M 0x00000010 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__TBTT_CNT_CLEAR___S 4 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_IN_TX_ABORT_CNT_CLEAR___M 0x00000008 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_IN_TX_ABORT_CNT_CLEAR___S 3 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_AUTO_RESP_REQ_CNT_CLEAR___M 0x00000004 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_AUTO_RESP_REQ_CNT_CLEAR___S 2 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_ACK_CNT_CLEAR___M 0x00000002 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_ACK_CNT_CLEAR___S 1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_CNT_CLEAR___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1__WL_TX_REQ_CNT_CLEAR___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1___M 0x1FFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2 (0x00A2022C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_TX_REQ_NACK_LCMH_REASON_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__COEX_TX_RESP_ALT_BASED_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__COEX_TX_RESP_DEFAULT_BASED_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_STATUS_RESP_TX_END_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_STATUS_RESP_TX_START_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_STATUS_FES_END_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_STATUS_FES_TX_END_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_STATUS_FES_TX_START_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_FLUSH_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TBTT_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_IN_TX_ABORT_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_TX_AUTO_RESP_REQ_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_TX_REQ_ACK_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_TX_REQ_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT_CLEAR___M 0x00008000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT_CLEAR___S 15 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_TX_REQ_NACK_LCMH_REASON_CNT_CLEAR___M 0x00004000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_TX_REQ_NACK_LCMH_REASON_CNT_CLEAR___S 14 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT_CLEAR___M 0x00002000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT_CLEAR___S 13 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__COEX_TX_RESP_ALT_BASED_CNT_CLEAR___M 0x00001000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__COEX_TX_RESP_ALT_BASED_CNT_CLEAR___S 12 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__COEX_TX_RESP_DEFAULT_BASED_CNT_CLEAR___M 0x00000800 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__COEX_TX_RESP_DEFAULT_BASED_CNT_CLEAR___S 11 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_STATUS_RESP_TX_END_CNT_CLEAR___M 0x00000400 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_STATUS_RESP_TX_END_CNT_CLEAR___S 10 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_STATUS_RESP_TX_START_CNT_CLEAR___M 0x00000200 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_STATUS_RESP_TX_START_CNT_CLEAR___S 9 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_STATUS_FES_END_CNT_CLEAR___M 0x00000100 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_STATUS_FES_END_CNT_CLEAR___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_STATUS_FES_TX_END_CNT_CLEAR___M 0x00000080 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_STATUS_FES_TX_END_CNT_CLEAR___S 7 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_STATUS_FES_TX_START_CNT_CLEAR___M 0x00000040 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_STATUS_FES_TX_START_CNT_CLEAR___S 6 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_FLUSH_CNT_CLEAR___M 0x00000020 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TX_FLUSH_CNT_CLEAR___S 5 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TBTT_CNT_CLEAR___M 0x00000010 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__TBTT_CNT_CLEAR___S 4 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_IN_TX_ABORT_CNT_CLEAR___M 0x00000008 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_IN_TX_ABORT_CNT_CLEAR___S 3 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_TX_AUTO_RESP_REQ_CNT_CLEAR___M 0x00000004 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_TX_AUTO_RESP_REQ_CNT_CLEAR___S 2 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_TX_REQ_ACK_CNT_CLEAR___M 0x00000002 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_TX_REQ_ACK_CNT_CLEAR___S 1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_TX_REQ_CNT_CLEAR___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2__WL_TX_REQ_CNT_CLEAR___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_WLAN_BT_CNT_CLEAR_CNTRL_ARB2___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MODIFIED_CONT_INFO_EN (0x00A20234) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MODIFIED_CONT_INFO_EN___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MODIFIED_CONT_INFO_EN___POR 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MODIFIED_CONT_INFO_EN__MODIFIED_MCI_CONT_INFO_EN___POR 0x1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MODIFIED_CONT_INFO_EN__MODIFIED_MCI_CONT_INFO_EN___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MODIFIED_CONT_INFO_EN__MODIFIED_MCI_CONT_INFO_EN___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MODIFIED_CONT_INFO_EN___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MODIFIED_CONT_INFO_EN___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB1 (0x00A20238) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB1___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB1___POR 0x00000003 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB1__LTE_EVENT_EXPIRY_FIELD_EN___POR 0x1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB1__BT_EVENT_EXPIRY_FIELD_EN___POR 0x1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB1__LTE_EVENT_EXPIRY_FIELD_EN___M 0x00000002 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB1__LTE_EVENT_EXPIRY_FIELD_EN___S 1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB1__BT_EVENT_EXPIRY_FIELD_EN___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB1__BT_EVENT_EXPIRY_FIELD_EN___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB1___M 0x00000003 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB2 (0x00A2023C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB2___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB2___POR 0x00000002 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB2__LTE_EVENT_EXPIRY_FIELD_EN___POR 0x1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB2__BT_EVENT_EXPIRY_FIELD_EN___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB2__LTE_EVENT_EXPIRY_FIELD_EN___M 0x00000002 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB2__LTE_EVENT_EXPIRY_FIELD_EN___S 1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB2__BT_EVENT_EXPIRY_FIELD_EN___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB2__BT_EVENT_EXPIRY_FIELD_EN___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB2___M 0x00000003 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_SCHD_INFO_EVENT_EXPIRY_FIELD_EN_ARB2___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MCI_WLAN_CONT_MSG_EN (0x00A20244) +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MCI_WLAN_CONT_MSG_EN___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MCI_WLAN_CONT_MSG_EN___POR 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MCI_WLAN_CONT_MSG_EN__MCI_WLAN_CONT_MSG_EN___POR 0x1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MCI_WLAN_CONT_MSG_EN__MCI_WLAN_CONT_MSG_EN___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MCI_WLAN_CONT_MSG_EN__MCI_WLAN_CONT_MSG_EN___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MCI_WLAN_CONT_MSG_EN___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R0_MCI_WLAN_CONT_MSG_EN___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_HDR (0x00A21000) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_HDR___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_HDR___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_HDR__LEN___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_HDR__HDR___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_HDR__LEN___M 0x00001F00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_HDR__LEN___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_HDR__HDR___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_HDR__HDR___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_HDR___M 0x00001FFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_HDR___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_BDY (0x00A21004) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_BDY___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_BDY___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_BDY__BDY___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_BDY__BDY___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_BDY__BDY___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_BDY___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_BDY___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WBTIMER (0x00A21008) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WBTIMER___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WBTIMER___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WBTIMER__VALUE___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WBTIMER__VALUE___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WBTIMER__VALUE___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WBTIMER___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WBTIMER___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW (0x00A2100C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__CONT_INFO_TIMEOUT___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__BT_STOMP___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__BT_FREQ___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__BT_PRI_THRESH___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__BT_PRI___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__RX_MSG___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__WLTXSM_INVALID_SEQ_WMAC2___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__WLTXSM_INVALID_SEQ_WMAC1___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__SCHD_BTTX_INTR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__SCHD_BTRX_INTR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__RX_INVALID_HDR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__ARB_ERROR_WMAC2___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__ARB_ERROR_WMAC1___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__CONT_INFO_TIMEOUT___M 0x80000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__CONT_INFO_TIMEOUT___S 31 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__BT_STOMP___M 0x20000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__BT_STOMP___S 29 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__BT_FREQ___M 0x10000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__BT_FREQ___S 28 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__BT_PRI_THRESH___M 0x08000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__BT_PRI_THRESH___S 27 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__BT_PRI___M 0x07FFF800 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__BT_PRI___S 11 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__RX_MSG___M 0x00000200 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__RX_MSG___S 9 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__WLTXSM_INVALID_SEQ_WMAC2___M 0x00000080 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__WLTXSM_INVALID_SEQ_WMAC2___S 7 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__WLTXSM_INVALID_SEQ_WMAC1___M 0x00000040 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__WLTXSM_INVALID_SEQ_WMAC1___S 6 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__SCHD_BTTX_INTR___M 0x00000020 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__SCHD_BTTX_INTR___S 5 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__SCHD_BTRX_INTR___M 0x00000010 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__SCHD_BTRX_INTR___S 4 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__RX_INVALID_HDR___M 0x00000008 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__RX_INVALID_HDR___S 3 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__ARB_ERROR_WMAC2___M 0x00000002 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__ARB_ERROR_WMAC2___S 1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__ARB_ERROR_WMAC1___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW__ARB_ERROR_WMAC1___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW___M 0xBFFFFAFB +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RAW___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN (0x00A21010) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__CONT_INFO_TIMEOUT___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__BT_STOMP___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__BT_FREQ___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__BT_PRI_THRESH___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__BT_PRI___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__RX_MSG___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__TLV_LENGTH_ERR_WMAC2___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__WLTXSM_INVALID_SEQ_WMAC2___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__WLTXSM_INVALID_SEQ_WMAC1___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__SCHD_BTTX_INTR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__SCHD_BTRX_INTR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__RX_INVALID_HDR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__TLV_LENGTH_ERR_WMAC1___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__ARB_ERROR_WMAC2___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__ARB_ERROR_WMAC1___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__CONT_INFO_TIMEOUT___M 0x80000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__CONT_INFO_TIMEOUT___S 31 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__BT_STOMP___M 0x20000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__BT_STOMP___S 29 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__BT_FREQ___M 0x10000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__BT_FREQ___S 28 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__BT_PRI_THRESH___M 0x08000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__BT_PRI_THRESH___S 27 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__BT_PRI___M 0x07FFF800 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__BT_PRI___S 11 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__RX_MSG___M 0x00000200 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__RX_MSG___S 9 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__TLV_LENGTH_ERR_WMAC2___M 0x00000100 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__TLV_LENGTH_ERR_WMAC2___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__WLTXSM_INVALID_SEQ_WMAC2___M 0x00000080 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__WLTXSM_INVALID_SEQ_WMAC2___S 7 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__WLTXSM_INVALID_SEQ_WMAC1___M 0x00000040 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__WLTXSM_INVALID_SEQ_WMAC1___S 6 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__SCHD_BTTX_INTR___M 0x00000020 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__SCHD_BTTX_INTR___S 5 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__SCHD_BTRX_INTR___M 0x00000010 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__SCHD_BTRX_INTR___S 4 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__RX_INVALID_HDR___M 0x00000008 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__RX_INVALID_HDR___S 3 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__TLV_LENGTH_ERR_WMAC1___M 0x00000004 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__TLV_LENGTH_ERR_WMAC1___S 2 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__ARB_ERROR_WMAC2___M 0x00000002 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__ARB_ERROR_WMAC2___S 1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__ARB_ERROR_WMAC1___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN__ARB_ERROR_WMAC1___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN___M 0xBFFFFBFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_EN___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW (0x00A21014) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__WLAN_CONT_RST_RX___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__WLAN_CONT_RST_TX___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__WLAN_CONT_INFO_RX___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__WLAN_CONT_INFO_TX___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__SCHD_LINKID_INT___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__CONT_LINKID_INT___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__SCHD_INFO___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__CONT_RST___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__CONT_INFO___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__CONT_NACK___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__WLAN_CONT_RST_RX___M 0x00000800 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__WLAN_CONT_RST_RX___S 11 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__WLAN_CONT_RST_TX___M 0x00000400 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__WLAN_CONT_RST_TX___S 10 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__WLAN_CONT_INFO_RX___M 0x00000200 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__WLAN_CONT_INFO_RX___S 9 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__WLAN_CONT_INFO_TX___M 0x00000100 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__WLAN_CONT_INFO_TX___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__SCHD_LINKID_INT___M 0x00000080 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__SCHD_LINKID_INT___S 7 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__CONT_LINKID_INT___M 0x00000040 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__CONT_LINKID_INT___S 6 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__SCHD_INFO___M 0x00000020 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__SCHD_INFO___S 5 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__CONT_RST___M 0x00000010 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__CONT_RST___S 4 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__CONT_INFO___M 0x00000008 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__CONT_INFO___S 3 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__CONT_NACK___M 0x00000004 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW__CONT_NACK___S 2 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW___M 0x00000FFC +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_RAW___S 2 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN (0x00A21018) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__WLAN_CONT_RST_RX___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__WLAN_CONT_RST_TX___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__WLAN_CONT_INFO_RX___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__WLAN_CONT_INFO_TX___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__SCHD_LINKID_INT___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__CONT_LINKID_INT___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__SCHD_INFO___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__CONT_RST___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__CONT_INFO___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__CONT_NACK___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__WLAN_CONT_RST_RX___M 0x00000800 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__WLAN_CONT_RST_RX___S 11 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__WLAN_CONT_RST_TX___M 0x00000400 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__WLAN_CONT_RST_TX___S 10 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__WLAN_CONT_INFO_RX___M 0x00000200 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__WLAN_CONT_INFO_RX___S 9 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__WLAN_CONT_INFO_TX___M 0x00000100 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__WLAN_CONT_INFO_TX___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__SCHD_LINKID_INT___M 0x00000080 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__SCHD_LINKID_INT___S 7 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__CONT_LINKID_INT___M 0x00000040 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__CONT_LINKID_INT___S 6 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__SCHD_INFO___M 0x00000020 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__SCHD_INFO___S 5 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__CONT_RST___M 0x00000010 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__CONT_RST___S 4 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__CONT_INFO___M 0x00000008 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__CONT_INFO___S 3 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__CONT_NACK___M 0x00000004 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN__CONT_NACK___S 2 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN___M 0x00000FFC +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_RX_MSG_EN___S 2 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW (0x00A2101C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH3_TLV_OUT_TIMEOUT_ERROR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH3_WL_TX_RX_ERROR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH3_WL_IN_RX_WATCHDOG_TIMEOUT___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH3_WL_IN_TX_WATCHDOG_TIMEOUT___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH2_TLV_OUT_TIMEOUT_ERROR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH1_TLV_OUT_TIMEOUT_ERROR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH2_WL_TX_RX_ERROR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH1_WL_TX_RX_ERROR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH2_WL_IN_RX_WATCHDOG_TIMEOUT___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH2_WL_IN_TX_WATCHDOG_TIMEOUT___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH1_WL_IN_RX_WATCHDOG_TIMEOUT___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH1_WL_IN_TX_WATCHDOG_TIMEOUT___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH_REGISTER_ACCESS_ERR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BT_SCHD_PRI___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BT_TXRX_CNT_LIMIT___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__INVALID_BT_PWR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH3_TLV_OUT_TIMEOUT_ERROR___M 0x40000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH3_TLV_OUT_TIMEOUT_ERROR___S 30 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH3_WL_TX_RX_ERROR___M 0x20000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH3_WL_TX_RX_ERROR___S 29 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH3_WL_IN_RX_WATCHDOG_TIMEOUT___M 0x10000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH3_WL_IN_RX_WATCHDOG_TIMEOUT___S 28 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH3_WL_IN_TX_WATCHDOG_TIMEOUT___M 0x08000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH3_WL_IN_TX_WATCHDOG_TIMEOUT___S 27 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH2_TLV_OUT_TIMEOUT_ERROR___M 0x04000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH2_TLV_OUT_TIMEOUT_ERROR___S 26 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH1_TLV_OUT_TIMEOUT_ERROR___M 0x02000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH1_TLV_OUT_TIMEOUT_ERROR___S 25 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH2_WL_TX_RX_ERROR___M 0x01000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH2_WL_TX_RX_ERROR___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH1_WL_TX_RX_ERROR___M 0x00800000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH1_WL_TX_RX_ERROR___S 23 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH2_WL_IN_RX_WATCHDOG_TIMEOUT___M 0x00400000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH2_WL_IN_RX_WATCHDOG_TIMEOUT___S 22 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH2_WL_IN_TX_WATCHDOG_TIMEOUT___M 0x00200000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH2_WL_IN_TX_WATCHDOG_TIMEOUT___S 21 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH1_WL_IN_RX_WATCHDOG_TIMEOUT___M 0x00100000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH1_WL_IN_RX_WATCHDOG_TIMEOUT___S 20 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH1_WL_IN_TX_WATCHDOG_TIMEOUT___M 0x00080000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH1_WL_IN_TX_WATCHDOG_TIMEOUT___S 19 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH_REGISTER_ACCESS_ERR___M 0x00040000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BMH_REGISTER_ACCESS_ERR___S 18 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BT_SCHD_PRI___M 0x0003FFFC +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BT_SCHD_PRI___S 2 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BT_TXRX_CNT_LIMIT___M 0x00000002 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__BT_TXRX_CNT_LIMIT___S 1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__INVALID_BT_PWR___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW__INVALID_BT_PWR___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW___M 0x7FFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_RAW___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN (0x00A21020) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH3_TLV_OUT_TIMEOUT_ERROR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH3_WL_TX_RX_ERROR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH3_WL_IN_RX_WATCHDOG_TIMEOUT___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH3_WL_IN_TX_WATCHDOG_TIMEOUT___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH2_TLV_OUT_TIMEOUT_ERROR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH1_TLV_OUT_TIMEOUT_ERROR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH2_WL_TX_RX_ERROR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH1_WL_TX_RX_ERROR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH2_WL_IN_RX_WATCHDOG_TIMEOUT___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH2_WL_IN_TX_WATCHDOG_TIMEOUT___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH1_WL_IN_RX_WATCHDOG_TIMEOUT___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH1_WL_IN_TX_WATCHDOG_TIMEOUT___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH_REGISTER_ACCESS_ERR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BT_SCHD_PRI___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BT_TXRX_CNT_LIMIT___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__INVALID_BT_PWR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH3_TLV_OUT_TIMEOUT_ERROR___M 0x40000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH3_TLV_OUT_TIMEOUT_ERROR___S 30 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH3_WL_TX_RX_ERROR___M 0x20000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH3_WL_TX_RX_ERROR___S 29 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH3_WL_IN_RX_WATCHDOG_TIMEOUT___M 0x10000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH3_WL_IN_RX_WATCHDOG_TIMEOUT___S 28 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH3_WL_IN_TX_WATCHDOG_TIMEOUT___M 0x08000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH3_WL_IN_TX_WATCHDOG_TIMEOUT___S 27 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH2_TLV_OUT_TIMEOUT_ERROR___M 0x04000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH2_TLV_OUT_TIMEOUT_ERROR___S 26 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH1_TLV_OUT_TIMEOUT_ERROR___M 0x02000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH1_TLV_OUT_TIMEOUT_ERROR___S 25 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH2_WL_TX_RX_ERROR___M 0x01000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH2_WL_TX_RX_ERROR___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH1_WL_TX_RX_ERROR___M 0x00800000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH1_WL_TX_RX_ERROR___S 23 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH2_WL_IN_RX_WATCHDOG_TIMEOUT___M 0x00400000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH2_WL_IN_RX_WATCHDOG_TIMEOUT___S 22 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH2_WL_IN_TX_WATCHDOG_TIMEOUT___M 0x00200000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH2_WL_IN_TX_WATCHDOG_TIMEOUT___S 21 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH1_WL_IN_RX_WATCHDOG_TIMEOUT___M 0x00100000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH1_WL_IN_RX_WATCHDOG_TIMEOUT___S 20 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH1_WL_IN_TX_WATCHDOG_TIMEOUT___M 0x00080000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH1_WL_IN_TX_WATCHDOG_TIMEOUT___S 19 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH_REGISTER_ACCESS_ERR___M 0x00040000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BMH_REGISTER_ACCESS_ERR___S 18 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BT_SCHD_PRI___M 0x0003FFFC +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BT_SCHD_PRI___S 2 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BT_TXRX_CNT_LIMIT___M 0x00000002 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__BT_TXRX_CNT_LIMIT___S 1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__INVALID_BT_PWR___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN__INVALID_BT_PWR___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN___M 0x7FFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INTERRUPT_1_EN___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS (0x00A21024) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__OWNER___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__CHANNEL___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__LINKID___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__TX___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__PRIORITY___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__RSSI_POWER___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__OWNER___M 0xF0000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__OWNER___S 28 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__CHANNEL___M 0x0FE00000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__CHANNEL___S 21 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__LINKID___M 0x001E0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__LINKID___S 17 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__TX___M 0x00010000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__TX___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__PRIORITY___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__PRIORITY___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__RSSI_POWER___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS__RSSI_POWER___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_ENABLE (0x00A21028) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_ENABLE___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_ENABLE___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_ENABLE__SCHD_LINKID_ENABLE_BITMAP___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_ENABLE__CONT_LINKID_ENABLE_BITMAP___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_ENABLE__SCHD_LINKID_ENABLE_BITMAP___M 0xFFFF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_ENABLE__SCHD_LINKID_ENABLE_BITMAP___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_ENABLE__CONT_LINKID_ENABLE_BITMAP___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_ENABLE__CONT_LINKID_ENABLE_BITMAP___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_ENABLE___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_ENABLE___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_0 (0x00A2102C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_0___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_0___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_0__VALUE3___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_0__VALUE2___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_0__VALUE1___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_0__VALUE0___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_0__VALUE3___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_0__VALUE3___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_0__VALUE2___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_0__VALUE2___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_0__VALUE1___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_0__VALUE1___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_0__VALUE0___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_0__VALUE0___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_0___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_0___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_1 (0x00A21030) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_1___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_1__VALUE7___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_1__VALUE6___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_1__VALUE5___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_1__VALUE4___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_1__VALUE7___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_1__VALUE7___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_1__VALUE6___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_1__VALUE6___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_1__VALUE5___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_1__VALUE5___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_1__VALUE4___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_1__VALUE4___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_1___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_2 (0x00A21034) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_2___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_2___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_2__VALUE11___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_2__VALUE10___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_2__VALUE9___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_2__VALUE8___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_2__VALUE11___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_2__VALUE11___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_2__VALUE10___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_2__VALUE10___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_2__VALUE9___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_2__VALUE9___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_2__VALUE8___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_2__VALUE8___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_2___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_2___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_3 (0x00A21038) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_3___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_3___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_3__VALUE15___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_3__VALUE14___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_3__VALUE13___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_3__VALUE12___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_3__VALUE15___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_3__VALUE15___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_3__VALUE14___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_3__VALUE14___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_3__VALUE13___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_3__VALUE13___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_3__VALUE12___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_3__VALUE12___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_3___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_LINKID_INT_VALUE_IX_3___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_0 (0x00A2103C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_0___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_0___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_0__VALUE3___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_0__VALUE2___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_0__VALUE1___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_0__VALUE0___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_0__VALUE3___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_0__VALUE3___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_0__VALUE2___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_0__VALUE2___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_0__VALUE1___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_0__VALUE1___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_0__VALUE0___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_0__VALUE0___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_0___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_0___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_1 (0x00A21040) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_1___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_1__VALUE7___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_1__VALUE6___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_1__VALUE5___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_1__VALUE4___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_1__VALUE7___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_1__VALUE7___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_1__VALUE6___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_1__VALUE6___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_1__VALUE5___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_1__VALUE5___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_1__VALUE4___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_1__VALUE4___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_1___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_2 (0x00A21044) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_2___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_2___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_2__VALUE11___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_2__VALUE10___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_2__VALUE9___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_2__VALUE8___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_2__VALUE11___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_2__VALUE11___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_2__VALUE10___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_2__VALUE10___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_2__VALUE9___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_2__VALUE9___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_2__VALUE8___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_2__VALUE8___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_2___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_2___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_3 (0x00A21048) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_3___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_3___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_3__VALUE15___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_3__VALUE14___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_3__VALUE13___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_3__VALUE12___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_3__VALUE15___M 0xFF000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_3__VALUE15___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_3__VALUE14___M 0x00FF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_3__VALUE14___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_3__VALUE13___M 0x0000FF00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_3__VALUE13___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_3__VALUE12___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_3__VALUE12___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_3___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_SCHD_LINKID_INT_VALUE_IX_3___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_CONT_INFO (0x00A2104C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_CONT_INFO___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_CONT_INFO___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_CONT_INFO__MCI_CONT_INFO_WORD___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_CONT_INFO__MCI_CONT_INFO_WORD___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_CONT_INFO__MCI_CONT_INFO_WORD___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_CONT_INFO___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_CONT_INFO___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D0 (0x00A21050) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D0___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D0___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D0__MCI_SCHD_INFO_WORD0___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D0__MCI_SCHD_INFO_WORD0___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D0__MCI_SCHD_INFO_WORD0___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D0___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D0___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D1 (0x00A21054) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D1___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D1__MCI_SCHD_INFO_WORD1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D1__MCI_SCHD_INFO_WORD1___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D1__MCI_SCHD_INFO_WORD1___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D1___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D2 (0x00A21058) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D2___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D2___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D2__MCI_SCHD_INFO_WORD2___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D2__MCI_SCHD_INFO_WORD2___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D2__MCI_SCHD_INFO_WORD2___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D2___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D2___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D3 (0x00A2105C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D3___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D3___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D3__MCI_SCHD_INFO_WORD3___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D3__MCI_SCHD_INFO_WORD3___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D3__MCI_SCHD_INFO_WORD3___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D3___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_SCHD_INFO_D3___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ0 (0x00A21060) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ0___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ0___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ0__MASK___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ0__MASK___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ0__MASK___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ0___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ0___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ1 (0x00A21064) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ1___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ1__MASK___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ1__MASK___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ1__MASK___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ1___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ2 (0x00A21068) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ2___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ2___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ2__MASK___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ2__MASK___M 0x00007FFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ2__MASK___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ2___M 0x00007FFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WL_FREQ2___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INVALID_APB_ACC_ADR (0x00A2106C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INVALID_APB_ACC_ADR___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INVALID_APB_ACC_ADR___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INVALID_APB_ACC_ADR__ERR_TYPE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INVALID_APB_ACC_ADR__ERR_ADDR___POR 0x00000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INVALID_APB_ACC_ADR__ERR_TYPE___M 0x00060000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INVALID_APB_ACC_ADR__ERR_TYPE___S 17 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INVALID_APB_ACC_ADR__ERR_ADDR___M 0x0001FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INVALID_APB_ACC_ADR__ERR_ADDR___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INVALID_APB_ACC_ADR___M 0x0007FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_INVALID_APB_ACC_ADR___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL (0x00A21070) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN3_CCA_BUSY_TIME___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN3_NAV_TIME___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN2_CCA_BUSY_TIME___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN1_CCA_BUSY_TIME___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN2_NAV_TIME___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN1_NAV_TIME___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_BT_RX_TIME___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_BT_TX_TIME___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN3_CCA_BUSY_TIME___M 0x00000100 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN3_CCA_BUSY_TIME___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN3_NAV_TIME___M 0x00000080 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN3_NAV_TIME___S 7 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__CLEAR___M 0x00000040 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__CLEAR___S 6 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN2_CCA_BUSY_TIME___M 0x00000020 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN2_CCA_BUSY_TIME___S 5 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN1_CCA_BUSY_TIME___M 0x00000010 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN1_CCA_BUSY_TIME___S 4 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN2_NAV_TIME___M 0x00000008 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN2_NAV_TIME___S 3 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN1_NAV_TIME___M 0x00000004 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_WLAN1_NAV_TIME___S 2 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_BT_RX_TIME___M 0x00000002 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_BT_RX_TIME___S 1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_BT_TX_TIME___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL__COUNT_BT_TX_TIME___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL___M 0x000001FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_WLAN_USAGE_TRACKING_CTRL___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WMAC1_BT_WLAN_MEDIUM_USAGE_CNT (0x00A21074) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WMAC1_BT_WLAN_MEDIUM_USAGE_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WMAC1_BT_WLAN_MEDIUM_USAGE_CNT___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WMAC1_BT_WLAN_MEDIUM_USAGE_CNT__USAGE_COUNTER___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WMAC1_BT_WLAN_MEDIUM_USAGE_CNT__USAGE_COUNTER___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WMAC1_BT_WLAN_MEDIUM_USAGE_CNT__USAGE_COUNTER___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WMAC1_BT_WLAN_MEDIUM_USAGE_CNT___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WMAC1_BT_WLAN_MEDIUM_USAGE_CNT___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WMAC2_BT_WLAN_MEDIUM_USAGE_CNT (0x00A21078) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WMAC2_BT_WLAN_MEDIUM_USAGE_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WMAC2_BT_WLAN_MEDIUM_USAGE_CNT___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WMAC2_BT_WLAN_MEDIUM_USAGE_CNT__USAGE_COUNTER___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WMAC2_BT_WLAN_MEDIUM_USAGE_CNT__USAGE_COUNTER___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WMAC2_BT_WLAN_MEDIUM_USAGE_CNT__USAGE_COUNTER___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WMAC2_BT_WLAN_MEDIUM_USAGE_CNT___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WMAC2_BT_WLAN_MEDIUM_USAGE_CNT___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DBG_SYNC_CNT (0x00A2107C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DBG_SYNC_CNT___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DBG_SYNC_CNT___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DBG_SYNC_CNT__VALUE___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DBG_SYNC_CNT__VALUE___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DBG_SYNC_CNT__VALUE___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DBG_SYNC_CNT___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DBG_SYNC_CNT___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DBG_OUT_OF_SYNC_CNT (0x00A21080) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DBG_OUT_OF_SYNC_CNT___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DBG_OUT_OF_SYNC_CNT___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DBG_OUT_OF_SYNC_CNT__VALUE___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DBG_OUT_OF_SYNC_CNT__VALUE___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DBG_OUT_OF_SYNC_CNT__VALUE___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DBG_OUT_OF_SYNC_CNT___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DBG_OUT_OF_SYNC_CNT___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT (0x00A21084) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT__VALUE___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT__VALUE___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT__VALUE___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT_CTRL (0x00A21088) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT_CTRL___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT_CTRL___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT_CTRL__CLEAR___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT_CTRL__ENABLE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT_CTRL__CLEAR___M 0x00000002 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT_CTRL__CLEAR___S 1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT_CTRL__ENABLE___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT_CTRL__ENABLE___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT_CTRL___M 0x00000003 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CHANNEL_BUSY_CNT_CTRL___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_TX_CNT (0x00A2108C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_TX_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_TX_CNT___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_TX_CNT__VALUE___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_TX_CNT__VALUE___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_TX_CNT__VALUE___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_TX_CNT___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_TX_CNT___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_RX_CNT (0x00A21090) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_RX_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_RX_CNT___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_RX_CNT__VALUE___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_RX_CNT__VALUE___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_RX_CNT__VALUE___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_RX_CNT___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_RX_CNT___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_TXRX_CNT_LIMIT (0x00A21094) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_TXRX_CNT_LIMIT___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_TXRX_CNT_LIMIT___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_TXRX_CNT_LIMIT__VALUE___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_TXRX_CNT_LIMIT__VALUE___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_TXRX_CNT_LIMIT__VALUE___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_TXRX_CNT_LIMIT___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_TXRX_CNT_LIMIT___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WATCHDOG_TIMEOUT (0x00A21098) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WATCHDOG_TIMEOUT___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WATCHDOG_TIMEOUT___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WATCHDOG_TIMEOUT__TLV_TIMEOUT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WATCHDOG_TIMEOUT__VAL___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WATCHDOG_TIMEOUT__TLV_TIMEOUT___M 0xFFFF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WATCHDOG_TIMEOUT__TLV_TIMEOUT___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WATCHDOG_TIMEOUT__VAL___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WATCHDOG_TIMEOUT__VAL___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WATCHDOG_TIMEOUT___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WATCHDOG_TIMEOUT___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG1 (0x00A2109C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG1___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG1__WMAC2_CURRENT_TX_DURATION___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG1__WMAC1_CURRENT_TX_DURATION___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG1__WMAC2_CURRENT_TX_DURATION___M 0xFFFF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG1__WMAC2_CURRENT_TX_DURATION___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG1__WMAC1_CURRENT_TX_DURATION___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG1__WMAC1_CURRENT_TX_DURATION___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG1___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG2 (0x00A210A0) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG2___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG2___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG2__WMAC2_NEXT_RX_ACTIVE_TIME___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG2__WMAC1_NEXT_RX_ACTIVE_TIME___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG2__WMAC2_NEXT_RX_ACTIVE_TIME___M 0xFFFF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG2__WMAC2_NEXT_RX_ACTIVE_TIME___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG2__WMAC1_NEXT_RX_ACTIVE_TIME___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG2__WMAC1_NEXT_RX_ACTIVE_TIME___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG2___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG2___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG3 (0x00A210A4) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG3___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG3___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG3__WMAC2_REMAINING_FES_TIME___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG3__WMAC1_REMAINING_FES_TIME___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG3__WMAC2_REMAINING_FES_TIME___M 0xFFFF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG3__WMAC2_REMAINING_FES_TIME___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG3__WMAC1_REMAINING_FES_TIME___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG3__WMAC1_REMAINING_FES_TIME___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG3___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG3___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG4 (0x00A210A8) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG4___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG4___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG4__WMAC2_REMAIN_RX_PACKET_TIME___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG4__WMAC1_REMAIN_RX_PACKET_TIME___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG4__WMAC2_REMAIN_RX_PACKET_TIME___M 0xFFFF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG4__WMAC2_REMAIN_RX_PACKET_TIME___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG4__WMAC1_REMAIN_RX_PACKET_TIME___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG4__WMAC1_REMAIN_RX_PACKET_TIME___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG4___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG4___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG5 (0x00A210AC) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG5___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG5___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG5__WMAC2_REMAIN_RX_FES_TIME___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG5__WMAC1_REMAIN_RX_FES_TIME___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG5__WMAC2_REMAIN_RX_FES_TIME___M 0xFFFF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG5__WMAC2_REMAIN_RX_FES_TIME___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG5__WMAC1_REMAIN_RX_FES_TIME___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG5__WMAC1_REMAIN_RX_FES_TIME___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG5___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REMAINING_DURATION_REG5___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DEBUG_STATES_WMAC1 (0x00A210B0) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DEBUG_STATES_WMAC1___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DEBUG_STATES_WMAC1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DEBUG_STATES_WMAC1__STATE_INFO___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DEBUG_STATES_WMAC1__STATE_INFO___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DEBUG_STATES_WMAC1__STATE_INFO___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DEBUG_STATES_WMAC1___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DEBUG_STATES_WMAC1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DEBUG_STATES_WMAC2 (0x00A210B4) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DEBUG_STATES_WMAC2___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DEBUG_STATES_WMAC2___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DEBUG_STATES_WMAC2__STATE_INFO___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DEBUG_STATES_WMAC2__STATE_INFO___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DEBUG_STATES_WMAC2__STATE_INFO___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DEBUG_STATES_WMAC2___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_DEBUG_STATES_WMAC2___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TRC_SELECT_BMH (0x00A210B8) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TRC_SELECT_BMH___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TRC_SELECT_BMH___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TRC_SELECT_BMH__EVENTBUS_SEL___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TRC_SELECT_BMH__TESTBUS_SEL___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TRC_SELECT_BMH__EVENTBUS_SEL___M 0x00001F00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TRC_SELECT_BMH__EVENTBUS_SEL___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TRC_SELECT_BMH__TESTBUS_SEL___M 0x0000003F +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TRC_SELECT_BMH__TESTBUS_SEL___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TRC_SELECT_BMH___M 0x00001F3F +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TRC_SELECT_BMH___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL (0x00A210BC) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL___POR 0x00000100 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_7___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_6___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_5___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_4___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_3___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_2___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_1___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__CLOCK_ENS_EXTEND___POR 0x1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_GPIO___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__DEBUG_MODULE_CLOCKON___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__TESTBUS_SELECT___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_7___M 0x00008000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_7___S 15 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_6___M 0x00004000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_6___S 14 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_5___M 0x00002000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_5___S 13 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_4___M 0x00001000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_4___S 12 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_3___M 0x00000800 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_3___S 11 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_2___M 0x00000400 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_2___S 10 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_1___M 0x00000200 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_1___S 9 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__CLOCK_ENS_EXTEND___M 0x00000100 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__CLOCK_ENS_EXTEND___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_GPIO___M 0x00000080 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__RESERVE_GPIO___S 7 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__DEBUG_MODULE_CLOCKON___M 0x00000040 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__DEBUG_MODULE_CLOCKON___S 6 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__TESTBUS_SELECT___M 0x0000003F +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL__TESTBUS_SELECT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_CTRL___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_LOWER (0x00A210C0) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_LOWER___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_LOWER___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_LOWER__VALUE___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_LOWER__VALUE___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_LOWER__VALUE___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_LOWER___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TESTBUS_LOWER___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_0 (0x00A210C4) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_0___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_0___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_0__MASK___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_0__MASK___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_0__MASK___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_0___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_0___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_1 (0x00A210C8) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_1___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_1__MASK___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_1__MASK___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_1__MASK___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_1___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_2 (0x00A210CC) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_2___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_2___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_2__MASK___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_2__MASK___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_2__MASK___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_2___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_2___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_3 (0x00A210D0) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_3___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_3___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_3__MASK___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_3__MASK___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_3__MASK___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_3___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_EVENTMASK_IX_3___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN (0x00A210F0) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_STOMPED___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__WLAN_STOMPED___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_HIGH_PRI_FALLING___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_HIGH_PRI_RISING___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_LOW_PRI_FALLING___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_LOW_PRI_RISING___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_ACTIVE_FALLING___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_ACTIVE_RISING___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_STOMPED___M 0x00000080 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_STOMPED___S 7 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__WLAN_STOMPED___M 0x00000040 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__WLAN_STOMPED___S 6 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_HIGH_PRI_FALLING___M 0x00000020 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_HIGH_PRI_FALLING___S 5 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_HIGH_PRI_RISING___M 0x00000010 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_HIGH_PRI_RISING___S 4 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_LOW_PRI_FALLING___M 0x00000008 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_LOW_PRI_FALLING___S 3 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_LOW_PRI_RISING___M 0x00000004 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_LOW_PRI_RISING___S 2 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_ACTIVE_FALLING___M 0x00000002 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_ACTIVE_FALLING___S 1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_ACTIVE_RISING___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN__BT_ACTIVE_RISING___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_EN___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR (0x00A210F4) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_STOMPED___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__WLAN_STOMPED___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_HIGH_PRI_FALLING___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_HIGH_PRI_RISING___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_LOW_PRI_FALLING___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_LOW_PRI_RISING___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_ACTIVE_FALLING___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_ACTIVE_RISING___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_STOMPED___M 0x00000080 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_STOMPED___S 7 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__WLAN_STOMPED___M 0x00000040 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__WLAN_STOMPED___S 6 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_HIGH_PRI_FALLING___M 0x00000020 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_HIGH_PRI_FALLING___S 5 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_HIGH_PRI_RISING___M 0x00000010 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_HIGH_PRI_RISING___S 4 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_LOW_PRI_FALLING___M 0x00000008 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_LOW_PRI_FALLING___S 3 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_LOW_PRI_RISING___M 0x00000004 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_LOW_PRI_RISING___S 2 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_ACTIVE_FALLING___M 0x00000002 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_ACTIVE_FALLING___S 1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_ACTIVE_RISING___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR__BT_ACTIVE_RISING___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR___M 0x000000FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_INTR_STAT_CLR___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_BLUETOOTH_WBCNT_BT_ACTIVE (0x00A210F8) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_BLUETOOTH_WBCNT_BT_ACTIVE___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_BLUETOOTH_WBCNT_BT_ACTIVE___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_BLUETOOTH_WBCNT_BT_ACTIVE__VALUE___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_BLUETOOTH_WBCNT_BT_ACTIVE__VALUE___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_BLUETOOTH_WBCNT_BT_ACTIVE__VALUE___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_BLUETOOTH_WBCNT_BT_ACTIVE___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_BLUETOOTH_WBCNT_BT_ACTIVE___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_BLUETOOTH_WBCNT_BT_PRIORITY (0x00A210FC) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_BLUETOOTH_WBCNT_BT_PRIORITY___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_BLUETOOTH_WBCNT_BT_PRIORITY___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_BLUETOOTH_WBCNT_BT_PRIORITY__VALUE___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_BLUETOOTH_WBCNT_BT_PRIORITY__VALUE___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_BLUETOOTH_WBCNT_BT_PRIORITY__VALUE___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_BLUETOOTH_WBCNT_BT_PRIORITY___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_PTA_COEX_BLUETOOTH_WBCNT_BT_PRIORITY___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_NACK_REASON (0x00A21110) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_NACK_REASON___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_NACK_REASON___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_NACK_REASON__VALUE___POR 0x000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_NACK_REASON__VALUE___M 0x00FFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_NACK_REASON__VALUE___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_NACK_REASON___M 0x00FFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_CONT_NACK_REASON___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MAC_NAP_TIME (0x00A21114) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MAC_NAP_TIME___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MAC_NAP_TIME___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MAC_NAP_TIME__VALUE___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MAC_NAP_TIME__VALUE___M 0x00003FFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MAC_NAP_TIME__VALUE___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MAC_NAP_TIME___M 0x00003FFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MAC_NAP_TIME___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MAC_NAP_WBTIMER (0x00A21118) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MAC_NAP_WBTIMER___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MAC_NAP_WBTIMER___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MAC_NAP_WBTIMER__VALUE___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MAC_NAP_WBTIMER__VALUE___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MAC_NAP_WBTIMER__VALUE___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MAC_NAP_WBTIMER___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MAC_NAP_WBTIMER___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0 (0x00A2111C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__SCHD_TABLE_WR_STATE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB3_WLAN_RX_STATE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB3_WLAN_TX_STATE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB2_WLAN_RX_STATE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB2_WLAN_TX_STATE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB1_WLAN_RX_STATE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB1_WLAN_TX_STATE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__SCHD_TABLE_WR_STATE___M 0x07000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__SCHD_TABLE_WR_STATE___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB3_WLAN_RX_STATE___M 0x00700000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB3_WLAN_RX_STATE___S 20 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB3_WLAN_TX_STATE___M 0x00070000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB3_WLAN_TX_STATE___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB2_WLAN_RX_STATE___M 0x00007000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB2_WLAN_RX_STATE___S 12 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB2_WLAN_TX_STATE___M 0x00000700 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB2_WLAN_TX_STATE___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB1_WLAN_RX_STATE___M 0x00000070 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB1_WLAN_RX_STATE___S 4 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB1_WLAN_TX_STATE___M 0x00000007 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0__ARB1_WLAN_TX_STATE___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0___M 0x07777777 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_0___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1 (0x00A21120) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1___POR 0x01101000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__WSI_INFO_STATE___POR 0x1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__MERGE_INFO_STATE___POR 0x1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__WSI_DECODE_STATE___POR 0x01 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__MCI_MERGE_STATE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__PTA2_STATE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__PTA1_STATE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__WSI_INFO_STATE___M 0x0F000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__WSI_INFO_STATE___S 24 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__MERGE_INFO_STATE___M 0x00F00000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__MERGE_INFO_STATE___S 20 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__WSI_DECODE_STATE___M 0x0001F000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__WSI_DECODE_STATE___S 12 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__MCI_MERGE_STATE___M 0x00000F00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__MCI_MERGE_STATE___S 8 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__PTA2_STATE___M 0x000000F0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__PTA2_STATE___S 4 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__PTA1_STATE___M 0x0000000F +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1__PTA1_STATE___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1___M 0x0FF1FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SM_STATES_IX_1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REG_ACCESS_EVENT_GEN_CTRL (0x00A21124) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REG_ACCESS_EVENT_GEN_CTRL___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REG_ACCESS_EVENT_GEN_CTRL___POR 0x7FFE0002 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___POR 0x3FFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___POR 0x1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___M 0xFFFE0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___S 17 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___M 0x0001FFFC +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___S 2 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___M 0x00000002 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___S 1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REG_ACCESS_EVENT_GEN_CTRL___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_REG_ACCESS_EVENT_GEN_CTRL___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL (0x00A21128) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_COEX_STATUS_BROADCAST_LMAC3___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_COEX_STATUS_BROADCAST_LMAC2___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_COEX_STATUS_BROADCAST_LMAC1___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_MACTX_COEX_PHY_CTRL_LMAC3___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_MACTX_COEX_PHY_CTRL_LMAC2___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_MACTX_COEX_PHY_CTRL_LMAC1___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_COEX_STATUS_BROADCAST_LMAC3___M 0x00000020 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_COEX_STATUS_BROADCAST_LMAC3___S 5 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_COEX_STATUS_BROADCAST_LMAC2___M 0x00000010 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_COEX_STATUS_BROADCAST_LMAC2___S 4 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_COEX_STATUS_BROADCAST_LMAC1___M 0x00000008 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_COEX_STATUS_BROADCAST_LMAC1___S 3 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_MACTX_COEX_PHY_CTRL_LMAC3___M 0x00000004 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_MACTX_COEX_PHY_CTRL_LMAC3___S 2 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_MACTX_COEX_PHY_CTRL_LMAC2___M 0x00000002 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_MACTX_COEX_PHY_CTRL_LMAC2___S 1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_MACTX_COEX_PHY_CTRL_LMAC1___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL__SEND_MACTX_COEX_PHY_CTRL_LMAC1___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL___M 0x0000003F +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_STATE_RESEND_CTRL___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB1 (0x00A2112C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB1___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB1__WL_TX_REQ_ACK_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB1__WL_TX_REQ_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB1__WL_TX_REQ_ACK_CNT___M 0xFFFF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB1__WL_TX_REQ_ACK_CNT___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB1__WL_TX_REQ_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB1__WL_TX_REQ_CNT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB1___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB2 (0x00A21130) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB2___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB2___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB2__WL_TX_REQ_ACK_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB2__WL_TX_REQ_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB2__WL_TX_REQ_ACK_CNT___M 0xFFFF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB2__WL_TX_REQ_ACK_CNT___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB2__WL_TX_REQ_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB2__WL_TX_REQ_CNT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB2___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_REQ_CNT_ARB2___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_AUTO_RESP_REQ_CNT_ARB1 (0x00A21138) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_AUTO_RESP_REQ_CNT_ARB1___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_AUTO_RESP_REQ_CNT_ARB1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_AUTO_RESP_REQ_CNT_ARB1__WL_TX_AUTO_RESP_REQ_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_AUTO_RESP_REQ_CNT_ARB1__WL_TX_AUTO_RESP_REQ_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_AUTO_RESP_REQ_CNT_ARB1__WL_TX_AUTO_RESP_REQ_CNT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_AUTO_RESP_REQ_CNT_ARB1___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_AUTO_RESP_REQ_CNT_ARB1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_AUTO_RESP_REQ_CNT_ARB2 (0x00A2113C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_AUTO_RESP_REQ_CNT_ARB2___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_AUTO_RESP_REQ_CNT_ARB2___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_AUTO_RESP_REQ_CNT_ARB2__WL_TX_AUTO_RESP_REQ_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_AUTO_RESP_REQ_CNT_ARB2__WL_TX_AUTO_RESP_REQ_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_AUTO_RESP_REQ_CNT_ARB2__WL_TX_AUTO_RESP_REQ_CNT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_AUTO_RESP_REQ_CNT_ARB2___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_AUTO_RESP_REQ_CNT_ARB2___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_IN_TX_ABORT_CNT_ARB1 (0x00A21144) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_IN_TX_ABORT_CNT_ARB1___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_IN_TX_ABORT_CNT_ARB1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_IN_TX_ABORT_CNT_ARB1__WL_IN_TX_ABORT_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_IN_TX_ABORT_CNT_ARB1__WL_IN_TX_ABORT_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_IN_TX_ABORT_CNT_ARB1__WL_IN_TX_ABORT_CNT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_IN_TX_ABORT_CNT_ARB1___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_IN_TX_ABORT_CNT_ARB1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_IN_TX_ABORT_CNT_ARB2 (0x00A21148) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_IN_TX_ABORT_CNT_ARB2___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_IN_TX_ABORT_CNT_ARB2___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_IN_TX_ABORT_CNT_ARB2__WL_IN_TX_ABORT_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_IN_TX_ABORT_CNT_ARB2__WL_IN_TX_ABORT_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_IN_TX_ABORT_CNT_ARB2__WL_IN_TX_ABORT_CNT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_IN_TX_ABORT_CNT_ARB2___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_IN_TX_ABORT_CNT_ARB2___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_FLUSH_TLV_CNT_ARB1 (0x00A21150) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_FLUSH_TLV_CNT_ARB1___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_FLUSH_TLV_CNT_ARB1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_FLUSH_TLV_CNT_ARB1__TX_FLUSH_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_FLUSH_TLV_CNT_ARB1__TX_FLUSH_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_FLUSH_TLV_CNT_ARB1__TX_FLUSH_CNT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_FLUSH_TLV_CNT_ARB1___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_FLUSH_TLV_CNT_ARB1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_FLUSH_TLV_CNT_ARB2 (0x00A21154) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_FLUSH_TLV_CNT_ARB2___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_FLUSH_TLV_CNT_ARB2___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_FLUSH_TLV_CNT_ARB2__TX_FLUSH_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_FLUSH_TLV_CNT_ARB2__TX_FLUSH_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_FLUSH_TLV_CNT_ARB2__TX_FLUSH_CNT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_FLUSH_TLV_CNT_ARB2___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_FLUSH_TLV_CNT_ARB2___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TBTT_CNT_ARB1 (0x00A2115C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TBTT_CNT_ARB1___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TBTT_CNT_ARB1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TBTT_CNT_ARB1__TBTT_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TBTT_CNT_ARB1__TBTT_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TBTT_CNT_ARB1__TBTT_CNT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TBTT_CNT_ARB1___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TBTT_CNT_ARB1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TBTT_CNT_ARB2 (0x00A21160) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TBTT_CNT_ARB2___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TBTT_CNT_ARB2___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TBTT_CNT_ARB2__TBTT_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TBTT_CNT_ARB2__TBTT_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TBTT_CNT_ARB2__TBTT_CNT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TBTT_CNT_ARB2___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TBTT_CNT_ARB2___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB1 (0x00A21168) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB1___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB1__TX_STATUS_FES_TX_END_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB1__TX_STATUS_FES_TX_START_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB1__TX_STATUS_FES_TX_END_CNT___M 0xFFFF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB1__TX_STATUS_FES_TX_END_CNT___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB1__TX_STATUS_FES_TX_START_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB1__TX_STATUS_FES_TX_START_CNT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB1___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_END_CNT_ARB1 (0x00A2116C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_END_CNT_ARB1___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_END_CNT_ARB1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_END_CNT_ARB1__TX_STATUS_FES_END_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_END_CNT_ARB1__TX_STATUS_FES_END_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_END_CNT_ARB1__TX_STATUS_FES_END_CNT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_END_CNT_ARB1___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_END_CNT_ARB1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB1 (0x00A21170) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB1___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB1__TX_STATUS_RESP_TX_END_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB1__TX_STATUS_RESP_TX_START_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB1__TX_STATUS_RESP_TX_END_CNT___M 0xFFFF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB1__TX_STATUS_RESP_TX_END_CNT___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB1__TX_STATUS_RESP_TX_START_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB1__TX_STATUS_RESP_TX_START_CNT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB1___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB2 (0x00A21174) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB2___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB2___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB2__TX_STATUS_FES_TX_END_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB2__TX_STATUS_FES_TX_START_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB2__TX_STATUS_FES_TX_END_CNT___M 0xFFFF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB2__TX_STATUS_FES_TX_END_CNT___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB2__TX_STATUS_FES_TX_START_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB2__TX_STATUS_FES_TX_START_CNT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB2___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_CNT_ARB2___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_END_CNT_ARB2 (0x00A21178) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_END_CNT_ARB2___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_END_CNT_ARB2___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_END_CNT_ARB2__TX_STATUS_FES_END_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_END_CNT_ARB2__TX_STATUS_FES_END_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_END_CNT_ARB2__TX_STATUS_FES_END_CNT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_END_CNT_ARB2___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_FES_END_CNT_ARB2___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB2 (0x00A2117C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB2___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB2___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB2__TX_STATUS_RESP_TX_END_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB2__TX_STATUS_RESP_TX_START_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB2__TX_STATUS_RESP_TX_END_CNT___M 0xFFFF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB2__TX_STATUS_RESP_TX_END_CNT___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB2__TX_STATUS_RESP_TX_START_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB2__TX_STATUS_RESP_TX_START_CNT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB2___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_TX_STATUS_RESP_TX_CNT_ARB2___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB1 (0x00A2118C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB1___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB1__COEX_TX_RESP_ALT_BASED_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB1__COEX_TX_RESP_DEFAULT_BASED_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB1__COEX_TX_RESP_ALT_BASED_CNT___M 0xFFFF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB1__COEX_TX_RESP_ALT_BASED_CNT___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB1__COEX_TX_RESP_DEFAULT_BASED_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB1__COEX_TX_RESP_DEFAULT_BASED_CNT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB1___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB2 (0x00A21190) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB2___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB2___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB2__COEX_TX_RESP_ALT_BASED_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB2__COEX_TX_RESP_DEFAULT_BASED_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB2__COEX_TX_RESP_ALT_BASED_CNT___M 0xFFFF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB2__COEX_TX_RESP_ALT_BASED_CNT___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB2__COEX_TX_RESP_DEFAULT_BASED_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB2__COEX_TX_RESP_DEFAULT_BASED_CNT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB2___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_RESULT_BASED_CNT_ARB2___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_CONCRNT_WLANTX_CNT_ARB1 (0x00A21198) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_CONCRNT_WLANTX_CNT_ARB1___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_CONCRNT_WLANTX_CNT_ARB1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_CONCRNT_WLANTX_CNT_ARB1__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_CONCRNT_WLANTX_CNT_ARB1__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_CONCRNT_WLANTX_CNT_ARB1__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_CONCRNT_WLANTX_CNT_ARB1___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_CONCRNT_WLANTX_CNT_ARB1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_CONCRNT_WLANTX_CNT_ARB2 (0x00A2119C) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_CONCRNT_WLANTX_CNT_ARB2___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_CONCRNT_WLANTX_CNT_ARB2___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_CONCRNT_WLANTX_CNT_ARB2__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_CONCRNT_WLANTX_CNT_ARB2__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_CONCRNT_WLANTX_CNT_ARB2__COEX_TX_RESP_CONCURRENT_WLAN_TX_CNT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_CONCRNT_WLANTX_CNT_ARB2___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_COEX_TX_RESP_CONCRNT_WLANTX_CNT_ARB2___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB1 (0x00A211A4) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB1___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB1__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB1__WL_TX_REQ_NACK_LCMH_REASON_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB1__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT___M 0xFFFF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB1__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB1__WL_TX_REQ_NACK_LCMH_REASON_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB1__WL_TX_REQ_NACK_LCMH_REASON_CNT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB1___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB2 (0x00A211A8) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB2___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB2___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB2__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB2__WL_TX_REQ_NACK_LCMH_REASON_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB2__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT___M 0xFFFF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB2__WL_TX_REQ_NACK_OTHER_WLAN_TX_REASON_CNT___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB2__WL_TX_REQ_NACK_LCMH_REASON_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB2__WL_TX_REQ_NACK_LCMH_REASON_CNT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB2___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_REASON_CNT_ARB2___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_BT_REASON_CNT_ARB1 (0x00A211B0) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_BT_REASON_CNT_ARB1___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_BT_REASON_CNT_ARB1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_BT_REASON_CNT_ARB1__WL_TX_REQ_NACK_SCHD_BT_REASON_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_BT_REASON_CNT_ARB1__WL_TX_REQ_NACK_CURRENT_BT_REASON_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_BT_REASON_CNT_ARB1__WL_TX_REQ_NACK_SCHD_BT_REASON_CNT___M 0xFFFF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_BT_REASON_CNT_ARB1__WL_TX_REQ_NACK_SCHD_BT_REASON_CNT___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_BT_REASON_CNT_ARB1__WL_TX_REQ_NACK_CURRENT_BT_REASON_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_BT_REASON_CNT_ARB1__WL_TX_REQ_NACK_CURRENT_BT_REASON_CNT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_BT_REASON_CNT_ARB1___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_WLAN_TX_NACK_BT_REASON_CNT_ARB1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_CNT (0x00A211B4) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_CNT___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_CNT__BT_RX_REQ_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_CNT__BT_TX_REQ_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_CNT__BT_RX_REQ_CNT___M 0xFFFF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_CNT__BT_RX_REQ_CNT___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_CNT__BT_TX_REQ_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_CNT__BT_TX_REQ_CNT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_CNT___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_CNT___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_TX_WL_TX_CNT (0x00A211B8) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_TX_WL_TX_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_TX_WL_TX_CNT___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_TX_WL_TX_CNT__CONCURRENT_BT_TX_WL_TX_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_TX_WL_TX_CNT__CONCURRENT_BT_TX_WL_TX_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_TX_WL_TX_CNT__CONCURRENT_BT_TX_WL_TX_CNT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_TX_WL_TX_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_TX_WL_TX_CNT___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_RX_WL_TX_CNT (0x00A211BC) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_RX_WL_TX_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_RX_WL_TX_CNT___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_RX_WL_TX_CNT__CONCURRENT_BT_RX_WL_TX_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_RX_WL_TX_CNT__CONCURRENT_BT_RX_WL_TX_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_RX_WL_TX_CNT__CONCURRENT_BT_RX_WL_TX_CNT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_RX_WL_TX_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_RX_WL_TX_CNT___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_TX_WL_RX_CNT (0x00A211C0) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_TX_WL_RX_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_TX_WL_RX_CNT___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_TX_WL_RX_CNT__CONCURRENT_BT_TX_WL_RX_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_TX_WL_RX_CNT__CONCURRENT_BT_TX_WL_RX_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_TX_WL_RX_CNT__CONCURRENT_BT_TX_WL_RX_CNT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_TX_WL_RX_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_TX_WL_RX_CNT___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_RX_WL_RX_CNT (0x00A211C4) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_RX_WL_RX_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_RX_WL_RX_CNT___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_RX_WL_RX_CNT__CONCURRENT_BT_RX_WL_RX_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_RX_WL_RX_CNT__CONCURRENT_BT_RX_WL_RX_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_RX_WL_RX_CNT__CONCURRENT_BT_RX_WL_RX_CNT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_RX_WL_RX_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONCURRENT_BT_RX_WL_RX_CNT___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_BDY1 (0x00A211C8) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_BDY1___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_BDY1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_BDY1__BDY___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_BDY1__BDY___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_BDY1__BDY___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_BDY1___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_LAST_HW_MSG_BDY1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS_DEBUG_FIELDS (0x00A211CC) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS_DEBUG_FIELDS___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS_DEBUG_FIELDS___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS_DEBUG_FIELDS__BT_CLOCK___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS_DEBUG_FIELDS__PRI_IDX___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS_DEBUG_FIELDS__BT_CLOCK___M 0xFFFF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS_DEBUG_FIELDS__BT_CLOCK___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS_DEBUG_FIELDS__PRI_IDX___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS_DEBUG_FIELDS__PRI_IDX___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS_DEBUG_FIELDS___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CONT_STATUS_DEBUG_FIELDS___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_CONT_INFO_DEBUG_FIELDS (0x00A211D0) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_CONT_INFO_DEBUG_FIELDS___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_CONT_INFO_DEBUG_FIELDS___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_CONT_INFO_DEBUG_FIELDS__MCI_CONT_INFO_DEBUG_FIELDS_WORD___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_CONT_INFO_DEBUG_FIELDS__MCI_CONT_INFO_DEBUG_FIELDS_WORD___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_CONT_INFO_DEBUG_FIELDS__MCI_CONT_INFO_DEBUG_FIELDS_WORD___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_CONT_INFO_DEBUG_FIELDS___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_LINKID_INT_CONT_INFO_DEBUG_FIELDS___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SPARE_CNTRL (0x00A211D4) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SPARE_CNTRL___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SPARE_CNTRL___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SPARE_CNTRL__SPARE_FIELD___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SPARE_CNTRL__SPARE_FIELD___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SPARE_CNTRL__SPARE_FIELD___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SPARE_CNTRL___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_SPARE_CNTRL___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_NACK_CNT (0x00A211D8) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_NACK_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_NACK_CNT___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_NACK_CNT__BT_REQ_NACK_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_NACK_CNT__BT_REQ_NACK_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_NACK_CNT__BT_REQ_NACK_CNT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_NACK_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_BT_REQ_NACK_CNT___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_TX_ARB1 (0x00A211DC) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_TX_ARB1___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_TX_ARB1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_TX_ARB1__MCI_WLAN_CONT_RST_TX_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_TX_ARB1__MCI_WLAN_CONT_INFO_TX_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_TX_ARB1__MCI_WLAN_CONT_RST_TX_CNT___M 0xFFFF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_TX_ARB1__MCI_WLAN_CONT_RST_TX_CNT___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_TX_ARB1__MCI_WLAN_CONT_INFO_TX_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_TX_ARB1__MCI_WLAN_CONT_INFO_TX_CNT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_TX_ARB1___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_TX_ARB1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_RX_ARB1 (0x00A211E0) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_RX_ARB1___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_RX_ARB1___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_RX_ARB1__MCI_WLAN_CONT_RST_RX_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_RX_ARB1__MCI_WLAN_CONT_INFO_RX_CNT___POR 0x0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_RX_ARB1__MCI_WLAN_CONT_RST_RX_CNT___M 0xFFFF0000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_RX_ARB1__MCI_WLAN_CONT_RST_RX_CNT___S 16 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_RX_ARB1__MCI_WLAN_CONT_INFO_RX_CNT___M 0x0000FFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_RX_ARB1__MCI_WLAN_CONT_INFO_RX_CNT___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_RX_ARB1___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_MSG_CNT_RX_ARB1___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_TX_STATUS (0x00A211E4) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_TX_STATUS___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_TX_STATUS___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_TX_STATUS__CHAIN_IN_USE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_TX_STATUS__PRIORITY___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_TX_STATUS__TX___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_TX_STATUS__CHAIN_IN_USE___M 0x00000600 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_TX_STATUS__CHAIN_IN_USE___S 9 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_TX_STATUS__PRIORITY___M 0x000001FE +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_TX_STATUS__PRIORITY___S 1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_TX_STATUS__TX___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_TX_STATUS__TX___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_TX_STATUS___M 0x000007FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_TX_STATUS___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_STATUS (0x00A211E8) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_STATUS___RWC QCSR_REG_RO +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_STATUS___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_STATUS__CHAIN_IN_USE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_STATUS__PRIORITY___POR 0x00 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_STATUS__RX___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_STATUS__CHAIN_IN_USE___M 0x00000600 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_STATUS__CHAIN_IN_USE___S 9 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_STATUS__PRIORITY___M 0x000001FE +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_STATUS__PRIORITY___S 1 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_STATUS__RX___M 0x00000001 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_STATUS__RX___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_STATUS___M 0x000007FF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_STATUS___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_CHAIN_IN_USE (0x00A211EC) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_CHAIN_IN_USE___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_CHAIN_IN_USE___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_CHAIN_IN_USE__CHAIN_IN_USE___POR 0x0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_CHAIN_IN_USE__CHAIN_IN_USE___M 0x00000003 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_CHAIN_IN_USE__CHAIN_IN_USE___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_CHAIN_IN_USE___M 0x00000003 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_MCI_WLAN_CONT_INFO_RX_CHAIN_IN_USE___S 0 + +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CXC_SPARE_REGISTER (0x00A211F4) +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CXC_SPARE_REGISTER___RWC QCSR_REG_RW +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CXC_SPARE_REGISTER___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CXC_SPARE_REGISTER__SPARE_FIELD___POR 0x00000000 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CXC_SPARE_REGISTER__SPARE_FIELD___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CXC_SPARE_REGISTER__SPARE_FIELD___S 0 +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CXC_SPARE_REGISTER___M 0xFFFFFFFF +#define UMAC_CXC_BMH_REG_CXC_BMH_R1_CXC_SPARE_REGISTER___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION (0x00A22000) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION___POR 0x0000004F +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__MAC1_MASK___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__MAC0_MASK___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__WL2_TX_BLANK_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__WL1_TX_BLANK_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__WLAN_TX_ON_SELECT2___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__LCMH_SW_CLKGATE_DISABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__SCHEDULING_MODE_SELECT___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__SCHEDULING_FEATURE_MODE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__SEND_RTSM_AFTER_PWRUP_SEL___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__WLAN_TX_ON_SELECT___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__WRITE_ENABLE_TIMER_COUNTER___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__TYPE0_CLEAR_UPON_WAKEUP___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__ENABLE_TX_FIFO_FLUSH_BEFORE_SLEEP___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__NUM_CLOCKS_PER_MICRO_SEC___POR 0x04F +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__MAC1_MASK___M 0x20000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__MAC1_MASK___S 29 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__MAC0_MASK___M 0x10000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__MAC0_MASK___S 28 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__WL2_TX_BLANK_ENABLE___M 0x08000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__WL2_TX_BLANK_ENABLE___S 27 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__WL1_TX_BLANK_ENABLE___M 0x04000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__WL1_TX_BLANK_ENABLE___S 26 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__WLAN_TX_ON_SELECT2___M 0x03000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__WLAN_TX_ON_SELECT2___S 24 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__LCMH_SW_CLKGATE_DISABLE___M 0x00F00000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__LCMH_SW_CLKGATE_DISABLE___S 20 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__SCHEDULING_MODE_SELECT___M 0x00080000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__SCHEDULING_MODE_SELECT___S 19 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__SCHEDULING_FEATURE_MODE___M 0x00060000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__SCHEDULING_FEATURE_MODE___S 17 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__SEND_RTSM_AFTER_PWRUP_SEL___M 0x00008000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__SEND_RTSM_AFTER_PWRUP_SEL___S 15 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__WLAN_TX_ON_SELECT___M 0x00006000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__WLAN_TX_ON_SELECT___S 13 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__WRITE_ENABLE_TIMER_COUNTER___M 0x00001000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__WRITE_ENABLE_TIMER_COUNTER___S 12 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__TYPE0_CLEAR_UPON_WAKEUP___M 0x00000800 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__TYPE0_CLEAR_UPON_WAKEUP___S 11 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__ENABLE_TX_FIFO_FLUSH_BEFORE_SLEEP___M 0x00000400 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__ENABLE_TX_FIFO_FLUSH_BEFORE_SLEEP___S 10 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__NUM_CLOCKS_PER_MICRO_SEC___M 0x000003FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION__NUM_CLOCKS_PER_MICRO_SEC___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION___M 0x3FFEFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_CONFIGURATION___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER (0x00A22004) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER_UPDATE (0x00A22008) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER_UPDATE___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER_UPDATE___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER_UPDATE__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER_UPDATE__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER_UPDATE__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER_UPDATE___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER_UPDATE___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL (0x00A2200C) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL___POR 0x00000006 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__ENABLE1___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__VALUE1___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__ENABLE2___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__VALUE2___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__OVERWRITE_ENABLE___POR 0x1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__OVERWRITE_VALUE___POR 0x1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__UNUSED___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__ENABLE1___M 0x00000040 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__ENABLE1___S 6 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__VALUE1___M 0x00000020 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__VALUE1___S 5 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__ENABLE2___M 0x00000010 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__ENABLE2___S 4 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__VALUE2___M 0x00000008 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__VALUE2___S 3 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__OVERWRITE_ENABLE___M 0x00000004 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__OVERWRITE_ENABLE___S 2 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__OVERWRITE_VALUE___M 0x00000002 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__OVERWRITE_VALUE___S 1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__UNUSED___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL__UNUSED___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL___M 0x0000007F +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_CONTROL___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_RESULT (0x00A22010) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_RESULT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_RESULT___POR 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_RESULT__VAL___POR 0x1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_RESULT__VAL___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_RESULT__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_RESULT___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_RESULT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_THRESHOLD1 (0x00A22014) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_THRESHOLD1___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_THRESHOLD1___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_THRESHOLD1__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_THRESHOLD1__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_THRESHOLD1__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_THRESHOLD1___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_THRESHOLD1___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_THRESHOLD2 (0x00A22018) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_THRESHOLD2___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_THRESHOLD2___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_THRESHOLD2__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_THRESHOLD2__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_THRESHOLD2__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_THRESHOLD2___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_TX_GRANT_THRESHOLD2___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL (0x00A2201C) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL___POR 0x00000006 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__ENABLE1___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__VALUE1___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__ENABLE2___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__VALUE2___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__OVERWRITE_ENABLE___POR 0x1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__OVERWRITE_VALUE___POR 0x1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__UNUSED___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__ENABLE1___M 0x00000040 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__ENABLE1___S 6 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__VALUE1___M 0x00000020 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__VALUE1___S 5 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__ENABLE2___M 0x00000010 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__ENABLE2___S 4 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__VALUE2___M 0x00000008 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__VALUE2___S 3 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__OVERWRITE_ENABLE___M 0x00000004 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__OVERWRITE_ENABLE___S 2 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__OVERWRITE_VALUE___M 0x00000002 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__OVERWRITE_VALUE___S 1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__UNUSED___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL__UNUSED___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL___M 0x0000007F +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_CONTROL___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_RESULT (0x00A22020) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_RESULT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_RESULT___POR 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_RESULT__VAL___POR 0x1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_RESULT__VAL___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_RESULT__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_RESULT___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_RESULT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_THRESHOLD1 (0x00A22024) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_THRESHOLD1___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_THRESHOLD1___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_THRESHOLD1__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_THRESHOLD1__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_THRESHOLD1__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_THRESHOLD1___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_THRESHOLD1___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_THRESHOLD2 (0x00A22028) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_THRESHOLD2___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_THRESHOLD2___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_THRESHOLD2__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_THRESHOLD2__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_THRESHOLD2__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_THRESHOLD2___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_TX_GRANT_THRESHOLD2___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL (0x00A2202C) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL___POR 0x00000006 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__SELECT_MODE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__SELECT2___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__SELECT___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__ENABLE1___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__VALUE1___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__ENABLE2___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__VALUE2___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__OVERWRITE_ENABLE___POR 0x1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__OVERWRITE_VALUE___POR 0x1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__NOT_USED___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__SELECT_MODE___M 0x00000800 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__SELECT_MODE___S 11 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__SELECT2___M 0x00000600 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__SELECT2___S 9 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__SELECT___M 0x00000180 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__SELECT___S 7 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__ENABLE1___M 0x00000040 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__ENABLE1___S 6 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__VALUE1___M 0x00000020 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__VALUE1___S 5 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__ENABLE2___M 0x00000010 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__ENABLE2___S 4 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__VALUE2___M 0x00000008 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__VALUE2___S 3 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__OVERWRITE_ENABLE___M 0x00000004 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__OVERWRITE_ENABLE___S 2 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__OVERWRITE_VALUE___M 0x00000002 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__OVERWRITE_VALUE___S 1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__NOT_USED___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL__NOT_USED___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL___M 0x00000FFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_CONTROL___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_RESULT (0x00A22030) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_RESULT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_RESULT___POR 0x00000003 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_RESULT__RX_PRI___POR 0x1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_RESULT__RX_PRI_SW___POR 0x1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_RESULT__RX_PRI___M 0x00000002 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_RESULT__RX_PRI___S 1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_RESULT__RX_PRI_SW___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_RESULT__RX_PRI_SW___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_RESULT___M 0x00000003 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_RESULT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_THRESHOLD1 (0x00A22034) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_THRESHOLD1___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_THRESHOLD1___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_THRESHOLD1__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_THRESHOLD1__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_THRESHOLD1__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_THRESHOLD1___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_THRESHOLD1___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_THRESHOLD2 (0x00A22038) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_THRESHOLD2___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_THRESHOLD2___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_THRESHOLD2__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_THRESHOLD2__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_THRESHOLD2__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_THRESHOLD2___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_PRI_THRESHOLD2___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT (0x00A2203C) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT___POR 0x00000606 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI___POR 0x1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_SW___POR 0x1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_SELECT___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__UNUSED_2___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_ENABLE1___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_VALUE1___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_ENABLE2___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_VALUE2___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_OVERWRITE_ENABLE___POR 0x1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_OVERWRITE_VALUE___POR 0x1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__UNUSED_1___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI___M 0x00000400 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI___S 10 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_SW___M 0x00000200 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_SW___S 9 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_SELECT___M 0x00000100 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_SELECT___S 8 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__UNUSED_2___M 0x00000080 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__UNUSED_2___S 7 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_ENABLE1___M 0x00000040 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_ENABLE1___S 6 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_VALUE1___M 0x00000020 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_VALUE1___S 5 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_ENABLE2___M 0x00000010 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_ENABLE2___S 4 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_VALUE2___M 0x00000008 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_VALUE2___S 3 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_OVERWRITE_ENABLE___M 0x00000004 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_OVERWRITE_ENABLE___S 2 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_OVERWRITE_VALUE___M 0x00000002 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__RX_PRI_OVERWRITE_VALUE___S 1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__UNUSED_1___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT__UNUSED_1___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT___M 0x000007FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_CONTROL_RESULT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_THRESHOLD1 (0x00A22040) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_THRESHOLD1___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_THRESHOLD1___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_THRESHOLD1__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_THRESHOLD1__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_THRESHOLD1__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_THRESHOLD1___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_THRESHOLD1___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_THRESHOLD2 (0x00A22044) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_THRESHOLD2___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_THRESHOLD2___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_THRESHOLD2__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_THRESHOLD2__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_THRESHOLD2__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_THRESHOLD2___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN1_RX_PRI_THRESHOLD2___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT (0x00A22048) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT___POR 0x00000606 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI___POR 0x1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_SW___POR 0x1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_SELECT___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__UNUSED_2___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_ENABLE1___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_VALUE1___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_ENABLE2___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_VALUE2___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_OVERWRITE_ENABLE___POR 0x1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_OVERWRITE_VALUE___POR 0x1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__UNUSED_1___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI___M 0x00000400 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI___S 10 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_SW___M 0x00000200 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_SW___S 9 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_SELECT___M 0x00000100 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_SELECT___S 8 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__UNUSED_2___M 0x00000080 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__UNUSED_2___S 7 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_ENABLE1___M 0x00000040 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_ENABLE1___S 6 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_VALUE1___M 0x00000020 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_VALUE1___S 5 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_ENABLE2___M 0x00000010 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_ENABLE2___S 4 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_VALUE2___M 0x00000008 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_VALUE2___S 3 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_OVERWRITE_ENABLE___M 0x00000004 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_OVERWRITE_ENABLE___S 2 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_OVERWRITE_VALUE___M 0x00000002 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__RX_PRI_OVERWRITE_VALUE___S 1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__UNUSED_1___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT__UNUSED_1___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT___M 0x000007FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_CONTROL_RESULT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_THRESHOLD1 (0x00A2204C) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_THRESHOLD1___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_THRESHOLD1___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_THRESHOLD1__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_THRESHOLD1__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_THRESHOLD1__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_THRESHOLD1___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_THRESHOLD1___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_THRESHOLD2 (0x00A22050) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_THRESHOLD2___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_THRESHOLD2___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_THRESHOLD2__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_THRESHOLD2__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_THRESHOLD2__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_THRESHOLD2___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN2_RX_PRI_THRESHOLD2___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_ACCESS (0x00A22054) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_ACCESS___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_ACCESS___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_ACCESS__WCI2_TYPE2_MESSAGE_VALID___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_ACCESS__WCI2_TYPE2_MESSAGE___POR 0x00 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_ACCESS__WCI2_TYPE2_MESSAGE_VALID___M 0x00000100 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_ACCESS__WCI2_TYPE2_MESSAGE_VALID___S 8 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_ACCESS__WCI2_TYPE2_MESSAGE___M 0x000000FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_ACCESS__WCI2_TYPE2_MESSAGE___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_ACCESS___M 0x000001FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_ACCESS___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL (0x00A22058) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL___POR 0x0003D004 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__NUM_ENTRIES_USED___POR 0x000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__TX_FIFO_ALMOST_FULL___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__TX_FIFO_OVERFLOW___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__TX_FIFO_ALMOST_FULL_TRIGGER_LEVEL___POR 0xF4 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__UNUSED___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__TX_FIFO_FLUSH___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__TX_FIFO_ALMOST_EMPTY_TRIGGER_LEVEL___POR 0x04 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__NUM_ENTRIES_USED___M 0x1FF00000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__NUM_ENTRIES_USED___S 20 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__TX_FIFO_ALMOST_FULL___M 0x00080000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__TX_FIFO_ALMOST_FULL___S 19 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__TX_FIFO_OVERFLOW___M 0x00040000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__TX_FIFO_OVERFLOW___S 18 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__TX_FIFO_ALMOST_FULL_TRIGGER_LEVEL___M 0x0003FC00 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__TX_FIFO_ALMOST_FULL_TRIGGER_LEVEL___S 10 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__UNUSED___M 0x00000200 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__UNUSED___S 9 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__TX_FIFO_FLUSH___M 0x00000100 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__TX_FIFO_FLUSH___S 8 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__TX_FIFO_ALMOST_EMPTY_TRIGGER_LEVEL___M 0x000000FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL__TX_FIFO_ALMOST_EMPTY_TRIGGER_LEVEL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL___M 0x1FFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TX_FIFO_CTRL___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS (0x00A2205C) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS__POP_ONCE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS__POP_ON_READ___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS__NUM_ENTRIES_AVAIL___POR 0x000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS__MESSAGE_VALID___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS__WCI2_TYPE2_MESSAGE_DATA___POR 0x00 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS__POP_ONCE___M 0x00080000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS__POP_ONCE___S 19 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS__POP_ON_READ___M 0x00040000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS__POP_ON_READ___S 18 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS__NUM_ENTRIES_AVAIL___M 0x0003FE00 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS__NUM_ENTRIES_AVAIL___S 9 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS__MESSAGE_VALID___M 0x00000100 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS__MESSAGE_VALID___S 8 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS__WCI2_TYPE2_MESSAGE_DATA___M 0x000000FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS__WCI2_TYPE2_MESSAGE_DATA___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS___M 0x000FFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_ACCESS___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS (0x00A22060) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS___POR 0x0003D004 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS__RX_FIFO_UNDERFLOW___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS__RX_FIFO_OVERFLOW___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS__RX_FIFO_ALMOST_FULL_TRIGGER_LEVEL___POR 0xF4 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS__RX_FIFO_FLUSH___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS__RX_FIFO_ALMOST_EMPTY_TRIGGER_LEVEL___POR 0x04 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS__RX_FIFO_UNDERFLOW___M 0x00080000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS__RX_FIFO_UNDERFLOW___S 19 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS__RX_FIFO_OVERFLOW___M 0x00040000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS__RX_FIFO_OVERFLOW___S 18 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS__RX_FIFO_ALMOST_FULL_TRIGGER_LEVEL___M 0x0003FC00 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS__RX_FIFO_ALMOST_FULL_TRIGGER_LEVEL___S 10 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS__RX_FIFO_FLUSH___M 0x00000100 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS__RX_FIFO_FLUSH___S 8 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS__RX_FIFO_ALMOST_EMPTY_TRIGGER_LEVEL___M 0x000000FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS__RX_FIFO_ALMOST_EMPTY_TRIGGER_LEVEL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS___M 0x000FFDFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RX_FIFO_CONTROL_STATUS___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SEND_DIRECT_WCI2_MESSAGE (0x00A22064) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SEND_DIRECT_WCI2_MESSAGE___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SEND_DIRECT_WCI2_MESSAGE___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SEND_DIRECT_WCI2_MESSAGE__TRIGGER___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SEND_DIRECT_WCI2_MESSAGE__CONTENT___POR 0x00 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SEND_DIRECT_WCI2_MESSAGE__TRIGGER___M 0x00000100 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SEND_DIRECT_WCI2_MESSAGE__TRIGGER___S 8 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SEND_DIRECT_WCI2_MESSAGE__CONTENT___M 0x000000FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SEND_DIRECT_WCI2_MESSAGE__CONTENT___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SEND_DIRECT_WCI2_MESSAGE___M 0x000001FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SEND_DIRECT_WCI2_MESSAGE___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SCRATCH_PAD_LTE_COEX_SW (0x00A22068) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SCRATCH_PAD_LTE_COEX_SW___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SCRATCH_PAD_LTE_COEX_SW___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SCRATCH_PAD_LTE_COEX_SW__SCRATCH_PAD___POR 0x00 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SCRATCH_PAD_LTE_COEX_SW__SCRATCH_PAD___M 0x000000FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SCRATCH_PAD_LTE_COEX_SW__SCRATCH_PAD___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SCRATCH_PAD_LTE_COEX_SW___M 0x000000FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_SCRATCH_PAD_LTE_COEX_SW___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION (0x00A2206C) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION___POR 0x00000008 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION__TIMEOUT_VAL___POR 0x00008 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION__TIMEOUT_VAL___M 0x0001FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION__TIMEOUT_VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION___M 0x0001FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION_TIMEOUT_STATUS (0x00A22070) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION_TIMEOUT_STATUS___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION_TIMEOUT_STATUS___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION_TIMEOUT_STATUS__RESPOND_BEFORE_TIMEOUT___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION_TIMEOUT_STATUS__RESPOND_AFTER_TIMEOUT___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION_TIMEOUT_STATUS__RESPOND_BEFORE_TIMEOUT___M 0x00000002 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION_TIMEOUT_STATUS__RESPOND_BEFORE_TIMEOUT___S 1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION_TIMEOUT_STATUS__RESPOND_AFTER_TIMEOUT___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION_TIMEOUT_STATUS__RESPOND_AFTER_TIMEOUT___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION_TIMEOUT_STATUS___M 0x00000003 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE0_RESPONSE_DURATION_TIMEOUT_STATUS___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TXFIFO_MESSAGE_SENDTIME_DELAY (0x00A22074) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TXFIFO_MESSAGE_SENDTIME_DELAY___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TXFIFO_MESSAGE_SENDTIME_DELAY___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TXFIFO_MESSAGE_SENDTIME_DELAY__VAL___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TXFIFO_MESSAGE_SENDTIME_DELAY__VAL___M 0x0000000F +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TXFIFO_MESSAGE_SENDTIME_DELAY__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TXFIFO_MESSAGE_SENDTIME_DELAY___M 0x0000000F +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_TXFIFO_MESSAGE_SENDTIME_DELAY___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_CTRL (0x00A22078) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_CTRL___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_CTRL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_CTRL__CAPTURE_QTIMER_VALUE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_CTRL__SYNC_TO_QTIMER___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_CTRL__CAPTURE_QTIMER_VALUE___M 0x00000002 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_CTRL__CAPTURE_QTIMER_VALUE___S 1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_CTRL__SYNC_TO_QTIMER___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_CTRL__SYNC_TO_QTIMER___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_CTRL___M 0x00000003 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_CTRL___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_LOWER_32_BIT (0x00A2207C) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_LOWER_32_BIT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_LOWER_32_BIT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_LOWER_32_BIT__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_LOWER_32_BIT__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_LOWER_32_BIT__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_LOWER_32_BIT___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_LOWER_32_BIT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_UPPER_24_BIT (0x00A22080) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_UPPER_24_BIT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_UPPER_24_BIT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_UPPER_24_BIT__VAL___POR 0x000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_UPPER_24_BIT__VAL___M 0x00FFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_UPPER_24_BIT__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_UPPER_24_BIT___M 0x00FFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_QTIMER_UPPER_24_BIT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER_CAPTURED (0x00A22084) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER_CAPTURED___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER_CAPTURED___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER_CAPTURED__FREEZE_VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER_CAPTURED__FREEZE_VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER_CAPTURED__FREEZE_VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER_CAPTURED___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WBTIMER_CAPTURED___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RAT_ID_ENABLE (0x00A22088) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RAT_ID_ENABLE___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RAT_ID_ENABLE___POR 0x00000020 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RAT_ID_ENABLE__RAT_ID_MODE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RAT_ID_ENABLE__RAT_ID1___POR 0x01 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RAT_ID_ENABLE__RAT_ID0___POR 0x00 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RAT_ID_ENABLE__RAT_ID_MODE___M 0x40000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RAT_ID_ENABLE__RAT_ID_MODE___S 30 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RAT_ID_ENABLE__RAT_ID1___M 0x000003E0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RAT_ID_ENABLE__RAT_ID1___S 5 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RAT_ID_ENABLE__RAT_ID0___M 0x0000001F +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RAT_ID_ENABLE__RAT_ID0___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RAT_ID_ENABLE___M 0x400003FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RAT_ID_ENABLE___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RESEND_TYPE1_AFTER_TYPE7_MESSAGE_ERROR (0x00A2208C) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RESEND_TYPE1_AFTER_TYPE7_MESSAGE_ERROR___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RESEND_TYPE1_AFTER_TYPE7_MESSAGE_ERROR___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RESEND_TYPE1_AFTER_TYPE7_MESSAGE_ERROR__EN___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RESEND_TYPE1_AFTER_TYPE7_MESSAGE_ERROR__EN___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RESEND_TYPE1_AFTER_TYPE7_MESSAGE_ERROR__EN___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RESEND_TYPE1_AFTER_TYPE7_MESSAGE_ERROR___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_RESEND_TYPE1_AFTER_TYPE7_MESSAGE_ERROR___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RAT_ID_ENABLE (0x00A2209C) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RAT_ID_ENABLE___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RAT_ID_ENABLE___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RAT_ID_ENABLE__WLAN3_RAT_ID___POR 0x00 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RAT_ID_ENABLE__WLAN2_RAT_ID___POR 0x00 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RAT_ID_ENABLE__WLAN1_RAT_ID___POR 0x00 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RAT_ID_ENABLE__WLAN3_RAT_ID___M 0x00007C00 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RAT_ID_ENABLE__WLAN3_RAT_ID___S 10 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RAT_ID_ENABLE__WLAN2_RAT_ID___M 0x000003E0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RAT_ID_ENABLE__WLAN2_RAT_ID___S 5 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RAT_ID_ENABLE__WLAN1_RAT_ID___M 0x0000001F +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RAT_ID_ENABLE__WLAN1_RAT_ID___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RAT_ID_ENABLE___M 0x00007FFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RAT_ID_ENABLE___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE3_MESSAGE_ENABLE (0x00A220A0) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE3_MESSAGE_ENABLE___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE3_MESSAGE_ENABLE___POR 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE3_MESSAGE_ENABLE__VAL___POR 0x1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE3_MESSAGE_ENABLE__VAL___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE3_MESSAGE_ENABLE__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE3_MESSAGE_ENABLE___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TYPE3_MESSAGE_ENABLE___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_RISE_DELAY_OFFSET (0x00A220A4) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_RISE_DELAY_OFFSET___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_RISE_DELAY_OFFSET___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_RISE_DELAY_OFFSET__WLAN2___POR 0x000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_RISE_DELAY_OFFSET__WLAN1___POR 0x000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_RISE_DELAY_OFFSET__WLAN2___M 0x003FF800 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_RISE_DELAY_OFFSET__WLAN2___S 11 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_RISE_DELAY_OFFSET__WLAN1___M 0x000007FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_RISE_DELAY_OFFSET__WLAN1___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_RISE_DELAY_OFFSET___M 0x003FFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_RISE_DELAY_OFFSET___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_FALL_DELAY_OFFSET (0x00A220A8) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_FALL_DELAY_OFFSET___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_FALL_DELAY_OFFSET___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_FALL_DELAY_OFFSET__WLAN2___POR 0x000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_FALL_DELAY_OFFSET__WLAN1___POR 0x000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_FALL_DELAY_OFFSET__WLAN2___M 0x003FF800 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_FALL_DELAY_OFFSET__WLAN2___S 11 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_FALL_DELAY_OFFSET__WLAN1___M 0x000007FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_FALL_DELAY_OFFSET__WLAN1___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_FALL_DELAY_OFFSET___M 0x003FFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_TX_ON_FALL_DELAY_OFFSET___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_RISE_DELAY_OFFSET (0x00A220AC) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_RISE_DELAY_OFFSET___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_RISE_DELAY_OFFSET___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_RISE_DELAY_OFFSET__WLAN2___POR 0x000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_RISE_DELAY_OFFSET__WLAN1___POR 0x000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_RISE_DELAY_OFFSET__WLAN2___M 0x003FF800 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_RISE_DELAY_OFFSET__WLAN2___S 11 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_RISE_DELAY_OFFSET__WLAN1___M 0x000007FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_RISE_DELAY_OFFSET__WLAN1___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_RISE_DELAY_OFFSET___M 0x003FFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_RISE_DELAY_OFFSET___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_FALL_DELAY_OFFSET (0x00A220B0) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_FALL_DELAY_OFFSET___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_FALL_DELAY_OFFSET___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_FALL_DELAY_OFFSET__WLAN2___POR 0x000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_FALL_DELAY_OFFSET__WLAN1___POR 0x000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_FALL_DELAY_OFFSET__WLAN2___M 0x003FF800 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_FALL_DELAY_OFFSET__WLAN2___S 11 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_FALL_DELAY_OFFSET__WLAN1___M 0x000007FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_FALL_DELAY_OFFSET__WLAN1___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_FALL_DELAY_OFFSET___M 0x003FFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN_RX_ON_FALL_DELAY_OFFSET___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RX_RATID_1_0_DELAY (0x00A220B4) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RX_RATID_1_0_DELAY___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RX_RATID_1_0_DELAY___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RX_RATID_1_0_DELAY__RATID1___POR 0x000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RX_RATID_1_0_DELAY__RATID0___POR 0x000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RX_RATID_1_0_DELAY__RATID1___M 0x003FF800 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RX_RATID_1_0_DELAY__RATID1___S 11 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RX_RATID_1_0_DELAY__RATID0___M 0x000007FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RX_RATID_1_0_DELAY__RATID0___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RX_RATID_1_0_DELAY___M 0x003FFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_RX_RATID_1_0_DELAY___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TX_RATID_1_0_DELAY (0x00A220C0) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TX_RATID_1_0_DELAY___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TX_RATID_1_0_DELAY___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TX_RATID_1_0_DELAY__RATID1___POR 0x000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TX_RATID_1_0_DELAY__RATID0___POR 0x000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TX_RATID_1_0_DELAY__RATID1___M 0x003FF800 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TX_RATID_1_0_DELAY__RATID1___S 11 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TX_RATID_1_0_DELAY__RATID0___M 0x000007FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TX_RATID_1_0_DELAY__RATID0___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TX_RATID_1_0_DELAY___M 0x003FFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_LTE_TX_RATID_1_0_DELAY___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL (0x00A220C4) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL___POR 0x00000006 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__ENABLE1___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__VALUE1___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__ENABLE2___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__VALUE2___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__OVERWRITE_ENABLE___POR 0x1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__OVERWRITE_VALUE___POR 0x1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__UNUSED___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__ENABLE1___M 0x00000040 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__ENABLE1___S 6 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__VALUE1___M 0x00000020 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__VALUE1___S 5 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__ENABLE2___M 0x00000010 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__ENABLE2___S 4 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__VALUE2___M 0x00000008 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__VALUE2___S 3 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__OVERWRITE_ENABLE___M 0x00000004 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__OVERWRITE_ENABLE___S 2 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__OVERWRITE_VALUE___M 0x00000002 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__OVERWRITE_VALUE___S 1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__UNUSED___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL__UNUSED___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL___M 0x0000007F +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_WLAN3_TX_GRANT_CONTROL___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL (0x00A220FC) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE7_MESSAGE_RCVD_CNT_EN___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE6_MESSAGE_RCVD_CNT_EN___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE5_MESSAGE_RCVD_CNT_EN___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE4_MESSAGE_RCVD_CNT_EN___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE3_MESSAGE_RCVD_CNT_EN___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE2_MESSAGE_RCVD_CNT_EN___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE2_MSB_NIBBLE_RCVD_CNT_EN___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE2_LSB_NIBBLE_RCVD_CNT_EN___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE1_MESSAGE_RCVD_CNT_EN___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE0_MESSAGE_RCVD_CNT_EN___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE7_MESSAGE_RCVD_CNT_EN___M 0x00000200 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE7_MESSAGE_RCVD_CNT_EN___S 9 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE6_MESSAGE_RCVD_CNT_EN___M 0x00000100 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE6_MESSAGE_RCVD_CNT_EN___S 8 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE5_MESSAGE_RCVD_CNT_EN___M 0x00000080 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE5_MESSAGE_RCVD_CNT_EN___S 7 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE4_MESSAGE_RCVD_CNT_EN___M 0x00000040 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE4_MESSAGE_RCVD_CNT_EN___S 6 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE3_MESSAGE_RCVD_CNT_EN___M 0x00000020 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE3_MESSAGE_RCVD_CNT_EN___S 5 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE2_MESSAGE_RCVD_CNT_EN___M 0x00000010 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE2_MESSAGE_RCVD_CNT_EN___S 4 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE2_MSB_NIBBLE_RCVD_CNT_EN___M 0x00000008 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE2_MSB_NIBBLE_RCVD_CNT_EN___S 3 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE2_LSB_NIBBLE_RCVD_CNT_EN___M 0x00000004 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE2_LSB_NIBBLE_RCVD_CNT_EN___S 2 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE1_MESSAGE_RCVD_CNT_EN___M 0x00000002 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE1_MESSAGE_RCVD_CNT_EN___S 1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE0_MESSAGE_RCVD_CNT_EN___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL__TYPE0_MESSAGE_RCVD_CNT_EN___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL___M 0x000003FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_EN_CTRL___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL (0x00A22100) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE7_MESSAGE_RCVD_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE6_MESSAGE_RCVD_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE5_MESSAGE_RCVD_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE4_MESSAGE_RCVD_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE3_MESSAGE_RCVD_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE2_MESSAGE_RCVD_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE2_MSB_NIBBLE_RCVD_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE2_LSB_NIBBLE_RCVD_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE1_MESSAGE_RCVD_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE0_MESSAGE_RCVD_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE7_MESSAGE_RCVD_CNT_CLEAR___M 0x00000200 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE7_MESSAGE_RCVD_CNT_CLEAR___S 9 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE6_MESSAGE_RCVD_CNT_CLEAR___M 0x00000100 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE6_MESSAGE_RCVD_CNT_CLEAR___S 8 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE5_MESSAGE_RCVD_CNT_CLEAR___M 0x00000080 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE5_MESSAGE_RCVD_CNT_CLEAR___S 7 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE4_MESSAGE_RCVD_CNT_CLEAR___M 0x00000040 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE4_MESSAGE_RCVD_CNT_CLEAR___S 6 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE3_MESSAGE_RCVD_CNT_CLEAR___M 0x00000020 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE3_MESSAGE_RCVD_CNT_CLEAR___S 5 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE2_MESSAGE_RCVD_CNT_CLEAR___M 0x00000010 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE2_MESSAGE_RCVD_CNT_CLEAR___S 4 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE2_MSB_NIBBLE_RCVD_CNT_CLEAR___M 0x00000008 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE2_MSB_NIBBLE_RCVD_CNT_CLEAR___S 3 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE2_LSB_NIBBLE_RCVD_CNT_CLEAR___M 0x00000004 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE2_LSB_NIBBLE_RCVD_CNT_CLEAR___S 2 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE1_MESSAGE_RCVD_CNT_CLEAR___M 0x00000002 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE1_MESSAGE_RCVD_CNT_CLEAR___S 1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE0_MESSAGE_RCVD_CNT_CLEAR___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL__TYPE0_MESSAGE_RCVD_CNT_CLEAR___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL___M 0x000003FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_RCVD_CLEAR_CTRL___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL (0x00A22104) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE7_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE6_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE5_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE4_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE3_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE2_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE1_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE0_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE7_RATID1_MESSAGE_SENT_CNT_EN___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE7_RATID0_MESSAGE_SENT_CNT_EN___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE2_COMPLETE_MESSAGE_SENT_CNT_EN___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE2_MSB_MESSAGE_SENT_CNT_EN___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE2_LSB_MESSAGE_SENT_CNT_EN___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE1_MESSAGE_SENT_CNT_EN___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE0_RATID1_MESSAGE_SENT_CNT_EN___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE0_RATID0_MESSAGE_SENT_CNT_EN___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE0_LEGACY_MESSAGE_SENT_CNT_EN___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE7_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___M 0x00010000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE7_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___S 16 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE6_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___M 0x00008000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE6_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___S 15 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE5_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___M 0x00004000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE5_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___S 14 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE4_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___M 0x00002000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE4_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___S 13 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE3_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___M 0x00001000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE3_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___S 12 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE2_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___M 0x00000800 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE2_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___S 11 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE1_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___M 0x00000400 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE1_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___S 10 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE0_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___M 0x00000200 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE0_DIRECT_WCI2_MESSAGE_SENT_CNT_EN___S 9 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE7_RATID1_MESSAGE_SENT_CNT_EN___M 0x00000100 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE7_RATID1_MESSAGE_SENT_CNT_EN___S 8 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE7_RATID0_MESSAGE_SENT_CNT_EN___M 0x00000080 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE7_RATID0_MESSAGE_SENT_CNT_EN___S 7 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE2_COMPLETE_MESSAGE_SENT_CNT_EN___M 0x00000040 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE2_COMPLETE_MESSAGE_SENT_CNT_EN___S 6 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE2_MSB_MESSAGE_SENT_CNT_EN___M 0x00000020 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE2_MSB_MESSAGE_SENT_CNT_EN___S 5 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE2_LSB_MESSAGE_SENT_CNT_EN___M 0x00000010 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE2_LSB_MESSAGE_SENT_CNT_EN___S 4 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE1_MESSAGE_SENT_CNT_EN___M 0x00000008 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE1_MESSAGE_SENT_CNT_EN___S 3 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE0_RATID1_MESSAGE_SENT_CNT_EN___M 0x00000004 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE0_RATID1_MESSAGE_SENT_CNT_EN___S 2 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE0_RATID0_MESSAGE_SENT_CNT_EN___M 0x00000002 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE0_RATID0_MESSAGE_SENT_CNT_EN___S 1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE0_LEGACY_MESSAGE_SENT_CNT_EN___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL__TYPE0_LEGACY_MESSAGE_SENT_CNT_EN___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL___M 0x0001FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_EN_CTRL___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL (0x00A22108) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE7_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE6_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE5_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE4_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE3_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE2_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE1_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE0_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE7_RATID1_MESSAGE_SENT_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE7_RATID0_MESSAGE_SENT_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE2_COMPLETE_MESSAGE_SENT_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE2_MSB_MESSAGE_SENT_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE2_LSB_MESSAGE_SENT_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE1_MESSAGE_SENT_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE0_RATID1_MESSAGE_SENT_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE0_RATID0_MESSAGE_SENT_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE0_LEGACY_MESSAGE_SENT_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE7_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___M 0x00010000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE7_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___S 16 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE6_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___M 0x00008000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE6_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___S 15 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE5_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___M 0x00004000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE5_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___S 14 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE4_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___M 0x00002000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE4_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___S 13 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE3_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___M 0x00001000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE3_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___S 12 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE2_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___M 0x00000800 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE2_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___S 11 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE1_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___M 0x00000400 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE1_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___S 10 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE0_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___M 0x00000200 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE0_DIRECT_WCI2_MESSAGE_SENT_CNT_CLEAR___S 9 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE7_RATID1_MESSAGE_SENT_CNT_CLEAR___M 0x00000100 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE7_RATID1_MESSAGE_SENT_CNT_CLEAR___S 8 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE7_RATID0_MESSAGE_SENT_CNT_CLEAR___M 0x00000080 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE7_RATID0_MESSAGE_SENT_CNT_CLEAR___S 7 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE2_COMPLETE_MESSAGE_SENT_CNT_CLEAR___M 0x00000040 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE2_COMPLETE_MESSAGE_SENT_CNT_CLEAR___S 6 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE2_MSB_MESSAGE_SENT_CNT_CLEAR___M 0x00000020 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE2_MSB_MESSAGE_SENT_CNT_CLEAR___S 5 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE2_LSB_MESSAGE_SENT_CNT_CLEAR___M 0x00000010 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE2_LSB_MESSAGE_SENT_CNT_CLEAR___S 4 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE1_MESSAGE_SENT_CNT_CLEAR___M 0x00000008 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE1_MESSAGE_SENT_CNT_CLEAR___S 3 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE0_RATID1_MESSAGE_SENT_CNT_CLEAR___M 0x00000004 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE0_RATID1_MESSAGE_SENT_CNT_CLEAR___S 2 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE0_RATID0_MESSAGE_SENT_CNT_CLEAR___M 0x00000002 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE0_RATID0_MESSAGE_SENT_CNT_CLEAR___S 1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE0_LEGACY_MESSAGE_SENT_CNT_CLEAR___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL__TYPE0_LEGACY_MESSAGE_SENT_CNT_CLEAR___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL___M 0x0001FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R0_MSG_SENT_CLEAR_CTRL___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_CTRL (0x00A23000) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_CTRL___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_CTRL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_CTRL__VAL___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_CTRL__VAL___M 0x00000003 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_CTRL__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_CTRL___M 0x00000003 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_CTRL___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_RESET_N (0x00A23004) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_RESET_N___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_RESET_N___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_RESET_N__VAL___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_RESET_N__VAL___M 0x00000003 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_RESET_N__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_RESET_N___M 0x00000003 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_RESET_N___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_ENABLE (0x00A23008) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_ENABLE___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_ENABLE___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_ENABLE__VAL___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_ENABLE__VAL___M 0x00000003 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_ENABLE__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_ENABLE___M 0x00000003 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_ENABLE___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_CLEAR (0x00A2300C) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_CLEAR___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_CLEAR___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_CLEAR__VAL___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_CLEAR__VAL___M 0x00000003 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_CLEAR__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_CLEAR___M 0x00000003 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_CLEAR___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_STATUS (0x00A23010) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_STATUS___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_STATUS___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_STATUS__VAL___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_STATUS__VAL___M 0x00000003 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_STATUS__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_STATUS___M 0x00000003 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE_INTERRUPT_STATUS___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE0_INTERRUPT_PERIODICITY (0x00A23014) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE0_INTERRUPT_PERIODICITY___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE0_INTERRUPT_PERIODICITY___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE0_INTERRUPT_PERIODICITY__VAL___POR 0x000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE0_INTERRUPT_PERIODICITY__VAL___M 0x00FFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE0_INTERRUPT_PERIODICITY__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE0_INTERRUPT_PERIODICITY___M 0x00FFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE0_INTERRUPT_PERIODICITY___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE1_INTERRUPT_PERIODICITY (0x00A23018) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE1_INTERRUPT_PERIODICITY___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE1_INTERRUPT_PERIODICITY___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE1_INTERRUPT_PERIODICITY__VAL___POR 0x000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE1_INTERRUPT_PERIODICITY__VAL___M 0x00FFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE1_INTERRUPT_PERIODICITY__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE1_INTERRUPT_PERIODICITY___M 0x00FFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE1_INTERRUPT_PERIODICITY___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE0_INTERRUPT_START_COUNT (0x00A2301C) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE0_INTERRUPT_START_COUNT___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE0_INTERRUPT_START_COUNT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE0_INTERRUPT_START_COUNT__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE0_INTERRUPT_START_COUNT__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE0_INTERRUPT_START_COUNT__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE0_INTERRUPT_START_COUNT___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE0_INTERRUPT_START_COUNT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE1_INTERRUPT_START_COUNT (0x00A23020) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE1_INTERRUPT_START_COUNT___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE1_INTERRUPT_START_COUNT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE1_INTERRUPT_START_COUNT__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE1_INTERRUPT_START_COUNT__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE1_INTERRUPT_START_COUNT__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE1_INTERRUPT_START_COUNT___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_STROBE1_INTERRUPT_START_COUNT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_CAPTURED_TIMER_VALUE (0x00A23024) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_CAPTURED_TIMER_VALUE___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_CAPTURED_TIMER_VALUE___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_CAPTURED_TIMER_VALUE__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_CAPTURED_TIMER_VALUE__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_CAPTURED_TIMER_VALUE__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_CAPTURED_TIMER_VALUE___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_CAPTURED_TIMER_VALUE___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_TYPE_0_MESSAGE_CONTENT (0x00A23028) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_TYPE_0_MESSAGE_CONTENT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_TYPE_0_MESSAGE_CONTENT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_TYPE_0_MESSAGE_CONTENT__FRAME_SYNC_DELAY_COUNTS_ON_BT___POR 0x00 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_TYPE_0_MESSAGE_CONTENT__LTE_TYPE_0_MESSAGE___POR 0x00 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_TYPE_0_MESSAGE_CONTENT__FRAME_SYNC_DELAY_COUNTS_ON_BT___M 0x0000FF00 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_TYPE_0_MESSAGE_CONTENT__FRAME_SYNC_DELAY_COUNTS_ON_BT___S 8 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_TYPE_0_MESSAGE_CONTENT__LTE_TYPE_0_MESSAGE___M 0x000000FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_TYPE_0_MESSAGE_CONTENT__LTE_TYPE_0_MESSAGE___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_TYPE_0_MESSAGE_CONTENT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_FRAME_SYNC_TYPE_0_MESSAGE_CONTENT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS (0x00A2302C) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_MSB_NIBBLE_ORDER_ERROR_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_LSB_NIBBLE_ORDER_ERROR_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__DIRECT_WCI2_TRIGGER_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_7_MESSAGE_RECEIVED_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_6_MESSAGE_RECEIVED_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_5_MESSAGE_RECEIVED_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_4_MESSAGE_RECEIVED_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_3_MESSAGE_RECEIVED_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_2_MESSAGE_RECEIVED_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_1_MESSAGE_RECEIVED_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_0_MESSAGE_RECEIVED_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_802_TX_ON_FALLING_EDGE_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_802_TX_ON_RISING_EDGE_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_802_RX_PRI_FALLING_EDGE_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_802_RX_PRI_RISING_EDGE_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__MWS_TX_FALLING_EDGE_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__MWS_TX_RISING_EDGE_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__MWS_RX_FALLING_EDGE_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__MWS_RX_RISING_EDGE_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TYPE_0_MESSAGE_WITH_FRAME_SYNC_1_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_ALMOST_FULL_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_ALMOST_EMPTY_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_OVERFLOW_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_UNDERFLOW_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_FIFO_ALMOST_FULL_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_FIFO_ALMOST_EMPTY_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_FIFO_OVERFLOW_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_FIFO_UNDERFLOW_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TYPE0_RESPONSE_AFTER_TIMEOUT_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TYPE0_RESPONSE_BEFORE_TIMEOUT_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__INVALID_SUB_FRAME_VALUE_IN_TYPE_6_MESSAGE_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_0_MESSAGE_TRANSMIT_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_MSB_NIBBLE_ORDER_ERROR_INTR___M 0x80000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_MSB_NIBBLE_ORDER_ERROR_INTR___S 31 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_LSB_NIBBLE_ORDER_ERROR_INTR___M 0x40000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_LSB_NIBBLE_ORDER_ERROR_INTR___S 30 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__DIRECT_WCI2_TRIGGER_INTR___M 0x20000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__DIRECT_WCI2_TRIGGER_INTR___S 29 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_7_MESSAGE_RECEIVED_INTR___M 0x10000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_7_MESSAGE_RECEIVED_INTR___S 28 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_6_MESSAGE_RECEIVED_INTR___M 0x08000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_6_MESSAGE_RECEIVED_INTR___S 27 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_5_MESSAGE_RECEIVED_INTR___M 0x04000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_5_MESSAGE_RECEIVED_INTR___S 26 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_4_MESSAGE_RECEIVED_INTR___M 0x02000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_4_MESSAGE_RECEIVED_INTR___S 25 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_3_MESSAGE_RECEIVED_INTR___M 0x01000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_3_MESSAGE_RECEIVED_INTR___S 24 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_2_MESSAGE_RECEIVED_INTR___M 0x00800000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_2_MESSAGE_RECEIVED_INTR___S 23 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_1_MESSAGE_RECEIVED_INTR___M 0x00400000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_1_MESSAGE_RECEIVED_INTR___S 22 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_0_MESSAGE_RECEIVED_INTR___M 0x00200000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_0_MESSAGE_RECEIVED_INTR___S 21 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_802_TX_ON_FALLING_EDGE_INTR___M 0x00100000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_802_TX_ON_FALLING_EDGE_INTR___S 20 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_802_TX_ON_RISING_EDGE_INTR___M 0x00080000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_802_TX_ON_RISING_EDGE_INTR___S 19 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_802_RX_PRI_FALLING_EDGE_INTR___M 0x00040000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_802_RX_PRI_FALLING_EDGE_INTR___S 18 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_802_RX_PRI_RISING_EDGE_INTR___M 0x00020000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_802_RX_PRI_RISING_EDGE_INTR___S 17 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__MWS_TX_FALLING_EDGE_INTR___M 0x00010000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__MWS_TX_FALLING_EDGE_INTR___S 16 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__MWS_TX_RISING_EDGE_INTR___M 0x00008000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__MWS_TX_RISING_EDGE_INTR___S 15 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__MWS_RX_FALLING_EDGE_INTR___M 0x00004000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__MWS_RX_FALLING_EDGE_INTR___S 14 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__MWS_RX_RISING_EDGE_INTR___M 0x00002000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__MWS_RX_RISING_EDGE_INTR___S 13 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TYPE_0_MESSAGE_WITH_FRAME_SYNC_1_INTR___M 0x00001000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TYPE_0_MESSAGE_WITH_FRAME_SYNC_1_INTR___S 12 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_ALMOST_FULL_INTR___M 0x00000800 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_ALMOST_FULL_INTR___S 11 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_ALMOST_EMPTY_INTR___M 0x00000400 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_ALMOST_EMPTY_INTR___S 10 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_OVERFLOW_INTR___M 0x00000200 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_OVERFLOW_INTR___S 9 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_UNDERFLOW_INTR___M 0x00000100 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__RX_FIFO_UNDERFLOW_INTR___S 8 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_FIFO_ALMOST_FULL_INTR___M 0x00000080 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_FIFO_ALMOST_FULL_INTR___S 7 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_FIFO_ALMOST_EMPTY_INTR___M 0x00000040 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_FIFO_ALMOST_EMPTY_INTR___S 6 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_FIFO_OVERFLOW_INTR___M 0x00000020 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_FIFO_OVERFLOW_INTR___S 5 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_FIFO_UNDERFLOW_INTR___M 0x00000010 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TX_FIFO_UNDERFLOW_INTR___S 4 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TYPE0_RESPONSE_AFTER_TIMEOUT_INTR___M 0x00000008 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TYPE0_RESPONSE_AFTER_TIMEOUT_INTR___S 3 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TYPE0_RESPONSE_BEFORE_TIMEOUT_INTR___M 0x00000004 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__TYPE0_RESPONSE_BEFORE_TIMEOUT_INTR___S 2 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__INVALID_SUB_FRAME_VALUE_IN_TYPE_6_MESSAGE_INTR___M 0x00000002 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__INVALID_SUB_FRAME_VALUE_IN_TYPE_6_MESSAGE_INTR___S 1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_0_MESSAGE_TRANSMIT_INTR___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS__WCI2_TYPE_0_MESSAGE_TRANSMIT_INTR___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR (0x00A23030) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_MSB_NIBBLE_ORDER_ERROR_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_LSB_NIBBLE_ORDER_ERROR_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__DIRECT_WCI2_TRIGGER_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_7_MESSAGE_RECEIVED_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_6_MESSAGE_RECEIVED_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_5_MESSAGE_RECEIVED_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_4_MESSAGE_RECEIVED_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_3_MESSAGE_RECEIVED_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_2_MESSAGE_RECEIVED_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_1_MESSAGE_RECEIVED_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_0_MESSAGE_RECEIVED_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_802_TX_ON_FALLING_EDGE_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_802_TX_ON_RISING_EDGE_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_802_RX_PRI_FALLING_EDGE_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_802_RX_PRI_RISING_EDGE_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__MWS_TX_FALLING_EDGE_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__MWS_TX_RISING_EDGE_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__MWS_RX_FALLING_EDGE_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__MWS_RX_RISING_EDGE_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TYPE_0_MESSAGE_WITH_FRAME_SYNC_1_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_ALMOST_FULL_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_ALMOST_EMPTY_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_OVERFLOW_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_UNDERFLOW_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_FIFO_ALMOST_FULL_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_FIFO_ALMOST_EMPTY_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_FIFO_OVERFLOW_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_FIFO_UNDERFLOW_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TYPE0_RESPONSE_AFTER_TIMEOUT_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TYPE0_RESPONSE_BEFORE_TIMEOUT_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__INVALID_SUB_FRAME_VALUE_IN_TYPE_6_MESSAGE_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_0_MESSAGE_TRANSMIT_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_MSB_NIBBLE_ORDER_ERROR_INTR_CLEAR___M 0x80000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_MSB_NIBBLE_ORDER_ERROR_INTR_CLEAR___S 31 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_LSB_NIBBLE_ORDER_ERROR_INTR_CLEAR___M 0x40000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_LSB_NIBBLE_ORDER_ERROR_INTR_CLEAR___S 30 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__DIRECT_WCI2_TRIGGER_INTR_CLEAR___M 0x20000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__DIRECT_WCI2_TRIGGER_INTR_CLEAR___S 29 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_7_MESSAGE_RECEIVED_INTR_CLEAR___M 0x10000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_7_MESSAGE_RECEIVED_INTR_CLEAR___S 28 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_6_MESSAGE_RECEIVED_INTR_CLEAR___M 0x08000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_6_MESSAGE_RECEIVED_INTR_CLEAR___S 27 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_5_MESSAGE_RECEIVED_INTR_CLEAR___M 0x04000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_5_MESSAGE_RECEIVED_INTR_CLEAR___S 26 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_4_MESSAGE_RECEIVED_INTR_CLEAR___M 0x02000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_4_MESSAGE_RECEIVED_INTR_CLEAR___S 25 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_3_MESSAGE_RECEIVED_INTR_CLEAR___M 0x01000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_3_MESSAGE_RECEIVED_INTR_CLEAR___S 24 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_2_MESSAGE_RECEIVED_INTR_CLEAR___M 0x00800000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_2_MESSAGE_RECEIVED_INTR_CLEAR___S 23 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_1_MESSAGE_RECEIVED_INTR_CLEAR___M 0x00400000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_1_MESSAGE_RECEIVED_INTR_CLEAR___S 22 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_0_MESSAGE_RECEIVED_INTR_CLEAR___M 0x00200000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_0_MESSAGE_RECEIVED_INTR_CLEAR___S 21 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_802_TX_ON_FALLING_EDGE_INTR_CLEAR___M 0x00100000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_802_TX_ON_FALLING_EDGE_INTR_CLEAR___S 20 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_802_TX_ON_RISING_EDGE_INTR_CLEAR___M 0x00080000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_802_TX_ON_RISING_EDGE_INTR_CLEAR___S 19 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_802_RX_PRI_FALLING_EDGE_INTR_CLEAR___M 0x00040000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_802_RX_PRI_FALLING_EDGE_INTR_CLEAR___S 18 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_802_RX_PRI_RISING_EDGE_INTR_CLEAR___M 0x00020000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_802_RX_PRI_RISING_EDGE_INTR_CLEAR___S 17 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__MWS_TX_FALLING_EDGE_INTR_CLEAR___M 0x00010000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__MWS_TX_FALLING_EDGE_INTR_CLEAR___S 16 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__MWS_TX_RISING_EDGE_INTR_CLEAR___M 0x00008000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__MWS_TX_RISING_EDGE_INTR_CLEAR___S 15 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__MWS_RX_FALLING_EDGE_INTR_CLEAR___M 0x00004000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__MWS_RX_FALLING_EDGE_INTR_CLEAR___S 14 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__MWS_RX_RISING_EDGE_INTR_CLEAR___M 0x00002000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__MWS_RX_RISING_EDGE_INTR_CLEAR___S 13 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TYPE_0_MESSAGE_WITH_FRAME_SYNC_1_INTR_CLEAR___M 0x00001000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TYPE_0_MESSAGE_WITH_FRAME_SYNC_1_INTR_CLEAR___S 12 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_ALMOST_FULL_INTR_CLEAR___M 0x00000800 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_ALMOST_FULL_INTR_CLEAR___S 11 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_ALMOST_EMPTY_INTR_CLEAR___M 0x00000400 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_ALMOST_EMPTY_INTR_CLEAR___S 10 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_OVERFLOW_INTR_CLEAR___M 0x00000200 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_OVERFLOW_INTR_CLEAR___S 9 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_UNDERFLOW_INTR_CLEAR___M 0x00000100 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__RX_FIFO_UNDERFLOW_INTR_CLEAR___S 8 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_FIFO_ALMOST_FULL_INTR_CLEAR___M 0x00000080 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_FIFO_ALMOST_FULL_INTR_CLEAR___S 7 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_FIFO_ALMOST_EMPTY_INTR_CLEAR___M 0x00000040 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_FIFO_ALMOST_EMPTY_INTR_CLEAR___S 6 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_FIFO_OVERFLOW_INTR_CLEAR___M 0x00000020 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_FIFO_OVERFLOW_INTR_CLEAR___S 5 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_FIFO_UNDERFLOW_INTR_CLEAR___M 0x00000010 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TX_FIFO_UNDERFLOW_INTR_CLEAR___S 4 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TYPE0_RESPONSE_AFTER_TIMEOUT_INTR_CLEAR___M 0x00000008 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TYPE0_RESPONSE_AFTER_TIMEOUT_INTR_CLEAR___S 3 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TYPE0_RESPONSE_BEFORE_TIMEOUT_INTR_CLEAR___M 0x00000004 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__TYPE0_RESPONSE_BEFORE_TIMEOUT_INTR_CLEAR___S 2 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__INVALID_SUB_FRAME_VALUE_IN_TYPE_6_MESSAGE_INTR_CLEAR___M 0x00000002 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__INVALID_SUB_FRAME_VALUE_IN_TYPE_6_MESSAGE_INTR_CLEAR___S 1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_0_MESSAGE_TRANSMIT_INTR_CLEAR___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR__WCI2_TYPE_0_MESSAGE_TRANSMIT_INTR_CLEAR___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE (0x00A23034) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_MSB_NIBBLE_ORDER_ERROR_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_LSB_NIBBLE_ORDER_ERROR_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__DIRECT_WCI2_TRIGGER_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_7_MESSAGE_RECEIVED_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_6_MESSAGE_RECEIVED_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_5_MESSAGE_RECEIVED_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_4_MESSAGE_RECEIVED_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_3_MESSAGE_RECEIVED_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_2_MESSAGE_RECEIVED_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_1_MESSAGE_RECEIVED_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_0_MESSAGE_RECEIVED_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_802_TX_ON_FALLING_EDGE_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_802_TX_ON_RISING_EDGE_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_802_RX_PRI_FALLING_EDGE_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_802_RX_PRI_RISING_EDGE_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__MWS_TX_FALLING_EDGE_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__MWS_TX_RISING_EDGE_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__MWS_RX_FALLING_EDGE_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__MWS_RX_RISING_EDGE_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TYPE_0_MESSAGE_WITH_FRAME_SYNC_1_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_ALMOST_FULL_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_ALMOST_EMPTY_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_OVERFLOW_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_UNDERFLOW_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_FIFO_ALMOST_FULL_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_FIFO_ALMOST_EMPTY_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_FIFO_OVERFLOW_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_FIFO_UNDERFLOW_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TYPE0_RESPONSE_AFTER_TIMEOUT_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TYPE0_RESPONSE_BEFORE_TIMEOUT_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__INVALID_SUB_FRAME_VALUE_IN_TYPE_6_MESSAGE_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_0_MESSAGE_TRANSMIT_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_MSB_NIBBLE_ORDER_ERROR_INTR_ENABLE___M 0x80000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_MSB_NIBBLE_ORDER_ERROR_INTR_ENABLE___S 31 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_LSB_NIBBLE_ORDER_ERROR_INTR_ENABLE___M 0x40000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_LSB_NIBBLE_ORDER_ERROR_INTR_ENABLE___S 30 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__DIRECT_WCI2_TRIGGER_INTR_ENABLE___M 0x20000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__DIRECT_WCI2_TRIGGER_INTR_ENABLE___S 29 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_7_MESSAGE_RECEIVED_INTR_ENABLE___M 0x10000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_7_MESSAGE_RECEIVED_INTR_ENABLE___S 28 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_6_MESSAGE_RECEIVED_INTR_ENABLE___M 0x08000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_6_MESSAGE_RECEIVED_INTR_ENABLE___S 27 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_5_MESSAGE_RECEIVED_INTR_ENABLE___M 0x04000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_5_MESSAGE_RECEIVED_INTR_ENABLE___S 26 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_4_MESSAGE_RECEIVED_INTR_ENABLE___M 0x02000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_4_MESSAGE_RECEIVED_INTR_ENABLE___S 25 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_3_MESSAGE_RECEIVED_INTR_ENABLE___M 0x01000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_3_MESSAGE_RECEIVED_INTR_ENABLE___S 24 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_2_MESSAGE_RECEIVED_INTR_ENABLE___M 0x00800000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_2_MESSAGE_RECEIVED_INTR_ENABLE___S 23 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_1_MESSAGE_RECEIVED_INTR_ENABLE___M 0x00400000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_1_MESSAGE_RECEIVED_INTR_ENABLE___S 22 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_0_MESSAGE_RECEIVED_INTR_ENABLE___M 0x00200000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_0_MESSAGE_RECEIVED_INTR_ENABLE___S 21 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_802_TX_ON_FALLING_EDGE_INTR_ENABLE___M 0x00100000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_802_TX_ON_FALLING_EDGE_INTR_ENABLE___S 20 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_802_TX_ON_RISING_EDGE_INTR_ENABLE___M 0x00080000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_802_TX_ON_RISING_EDGE_INTR_ENABLE___S 19 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_802_RX_PRI_FALLING_EDGE_INTR_ENABLE___M 0x00040000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_802_RX_PRI_FALLING_EDGE_INTR_ENABLE___S 18 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_802_RX_PRI_RISING_EDGE_INTR_ENABLE___M 0x00020000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_802_RX_PRI_RISING_EDGE_INTR_ENABLE___S 17 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__MWS_TX_FALLING_EDGE_INTR_ENABLE___M 0x00010000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__MWS_TX_FALLING_EDGE_INTR_ENABLE___S 16 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__MWS_TX_RISING_EDGE_INTR_ENABLE___M 0x00008000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__MWS_TX_RISING_EDGE_INTR_ENABLE___S 15 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__MWS_RX_FALLING_EDGE_INTR_ENABLE___M 0x00004000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__MWS_RX_FALLING_EDGE_INTR_ENABLE___S 14 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__MWS_RX_RISING_EDGE_INTR_ENABLE___M 0x00002000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__MWS_RX_RISING_EDGE_INTR_ENABLE___S 13 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TYPE_0_MESSAGE_WITH_FRAME_SYNC_1_INTR_ENABLE___M 0x00001000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TYPE_0_MESSAGE_WITH_FRAME_SYNC_1_INTR_ENABLE___S 12 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_ALMOST_FULL_INTR_ENABLE___M 0x00000800 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_ALMOST_FULL_INTR_ENABLE___S 11 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_ALMOST_EMPTY_INTR_ENABLE___M 0x00000400 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_ALMOST_EMPTY_INTR_ENABLE___S 10 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_OVERFLOW_INTR_ENABLE___M 0x00000200 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_OVERFLOW_INTR_ENABLE___S 9 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_UNDERFLOW_INTR_ENABLE___M 0x00000100 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__RX_FIFO_UNDERFLOW_INTR_ENABLE___S 8 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_FIFO_ALMOST_FULL_INTR_ENABLE___M 0x00000080 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_FIFO_ALMOST_FULL_INTR_ENABLE___S 7 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_FIFO_ALMOST_EMPTY_INTR_ENABLE___M 0x00000040 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_FIFO_ALMOST_EMPTY_INTR_ENABLE___S 6 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_FIFO_OVERFLOW_INTR_ENABLE___M 0x00000020 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_FIFO_OVERFLOW_INTR_ENABLE___S 5 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_FIFO_UNDERFLOW_INTR_ENABLE___M 0x00000010 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TX_FIFO_UNDERFLOW_INTR_ENABLE___S 4 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TYPE0_RESPONSE_AFTER_TIMEOUT_INTR_ENABLE___M 0x00000008 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TYPE0_RESPONSE_AFTER_TIMEOUT_INTR_ENABLE___S 3 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TYPE0_RESPONSE_BEFORE_TIMEOUT_INTR_ENABLE___M 0x00000004 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__TYPE0_RESPONSE_BEFORE_TIMEOUT_INTR_ENABLE___S 2 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__INVALID_SUB_FRAME_VALUE_IN_TYPE_6_MESSAGE_INTR_ENABLE___M 0x00000002 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__INVALID_SUB_FRAME_VALUE_IN_TYPE_6_MESSAGE_INTR_ENABLE___S 1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_0_MESSAGE_TRANSMIT_INTR_ENABLE___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE__WCI2_TYPE_0_MESSAGE_TRANSMIT_INTR_ENABLE___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_MESSAGE_CONTENT (0x00A23038) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_MESSAGE_CONTENT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_MESSAGE_CONTENT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_MESSAGE_CONTENT__FRAME_SYNC_DELAY_COUNTS_ON_RHINO___POR 0x00 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_MESSAGE_CONTENT__LTE_TYPE_0_MESSAGE___POR 0x00 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_MESSAGE_CONTENT__FRAME_SYNC_DELAY_COUNTS_ON_RHINO___M 0x0000FF00 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_MESSAGE_CONTENT__FRAME_SYNC_DELAY_COUNTS_ON_RHINO___S 8 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_MESSAGE_CONTENT__LTE_TYPE_0_MESSAGE___M 0x000000FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_MESSAGE_CONTENT__LTE_TYPE_0_MESSAGE___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_MESSAGE_CONTENT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_MESSAGE_CONTENT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_WBTIMER_VALUE (0x00A2303C) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_WBTIMER_VALUE___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_WBTIMER_VALUE___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_WBTIMER_VALUE__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_WBTIMER_VALUE__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_WBTIMER_VALUE__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_WBTIMER_VALUE___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_WBTIMER_VALUE___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_1_MESSAGE_CONTENT (0x00A23040) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_1_MESSAGE_CONTENT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_1_MESSAGE_CONTENT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_1_MESSAGE_CONTENT__VAL___POR 0x00 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_1_MESSAGE_CONTENT__VAL___M 0x000000FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_1_MESSAGE_CONTENT__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_1_MESSAGE_CONTENT___M 0x000000FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_1_MESSAGE_CONTENT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_1_WBTIMER_VALUE (0x00A23044) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_1_WBTIMER_VALUE___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_1_WBTIMER_VALUE___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_1_WBTIMER_VALUE__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_1_WBTIMER_VALUE__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_1_WBTIMER_VALUE__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_1_WBTIMER_VALUE___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_1_WBTIMER_VALUE___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_2_MESSAGE_CONTENT (0x00A23048) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_2_MESSAGE_CONTENT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_2_MESSAGE_CONTENT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_2_MESSAGE_CONTENT__VAL___POR 0x00 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_2_MESSAGE_CONTENT__VAL___M 0x000000FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_2_MESSAGE_CONTENT__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_2_MESSAGE_CONTENT___M 0x000000FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_2_MESSAGE_CONTENT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_2_WBTIMER_VALUE (0x00A2304C) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_2_WBTIMER_VALUE___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_2_WBTIMER_VALUE___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_2_WBTIMER_VALUE__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_2_WBTIMER_VALUE__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_2_WBTIMER_VALUE__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_2_WBTIMER_VALUE___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_2_WBTIMER_VALUE___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_3_MESSAGE_CONTENT (0x00A23050) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_3_MESSAGE_CONTENT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_3_MESSAGE_CONTENT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_3_MESSAGE_CONTENT__VAL___POR 0x00 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_3_MESSAGE_CONTENT__VAL___M 0x000000FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_3_MESSAGE_CONTENT__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_3_MESSAGE_CONTENT___M 0x000000FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_3_MESSAGE_CONTENT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_3_WBTIMER_VALUE (0x00A23054) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_3_WBTIMER_VALUE___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_3_WBTIMER_VALUE___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_3_WBTIMER_VALUE__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_3_WBTIMER_VALUE__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_3_WBTIMER_VALUE__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_3_WBTIMER_VALUE___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_3_WBTIMER_VALUE___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_4_MESSAGE_CONTENT (0x00A23058) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_4_MESSAGE_CONTENT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_4_MESSAGE_CONTENT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_4_MESSAGE_CONTENT__VAL___POR 0x00 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_4_MESSAGE_CONTENT__VAL___M 0x000000FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_4_MESSAGE_CONTENT__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_4_MESSAGE_CONTENT___M 0x000000FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_4_MESSAGE_CONTENT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_4_WBTIMER_VALUE (0x00A2305C) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_4_WBTIMER_VALUE___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_4_WBTIMER_VALUE___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_4_WBTIMER_VALUE__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_4_WBTIMER_VALUE__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_4_WBTIMER_VALUE__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_4_WBTIMER_VALUE___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_4_WBTIMER_VALUE___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_5_MESSAGE_CONTENT (0x00A23060) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_5_MESSAGE_CONTENT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_5_MESSAGE_CONTENT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_5_MESSAGE_CONTENT__VAL___POR 0x00 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_5_MESSAGE_CONTENT__VAL___M 0x000000FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_5_MESSAGE_CONTENT__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_5_MESSAGE_CONTENT___M 0x000000FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_5_MESSAGE_CONTENT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_5_WBTIMER_VALUE (0x00A23064) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_5_WBTIMER_VALUE___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_5_WBTIMER_VALUE___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_5_WBTIMER_VALUE__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_5_WBTIMER_VALUE__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_5_WBTIMER_VALUE__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_5_WBTIMER_VALUE___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_5_WBTIMER_VALUE___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_MESSAGE_CONTENT (0x00A23068) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_MESSAGE_CONTENT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_MESSAGE_CONTENT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_MESSAGE_CONTENT__VAL___POR 0x00 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_MESSAGE_CONTENT__VAL___M 0x000000FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_MESSAGE_CONTENT__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_MESSAGE_CONTENT___M 0x000000FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_MESSAGE_CONTENT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_WBTIMER_VALUE (0x00A2306C) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_WBTIMER_VALUE___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_WBTIMER_VALUE___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_WBTIMER_VALUE__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_WBTIMER_VALUE__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_WBTIMER_VALUE__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_WBTIMER_VALUE___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_WBTIMER_VALUE___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_7_MESSAGE_CONTENT (0x00A23070) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_7_MESSAGE_CONTENT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_7_MESSAGE_CONTENT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_7_MESSAGE_CONTENT__VAL___POR 0x00 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_7_MESSAGE_CONTENT__VAL___M 0x000000FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_7_MESSAGE_CONTENT__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_7_MESSAGE_CONTENT___M 0x000000FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_7_MESSAGE_CONTENT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_7_WBTIMER_VALUE (0x00A23074) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_7_WBTIMER_VALUE___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_7_WBTIMER_VALUE___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_7_WBTIMER_VALUE__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_7_WBTIMER_VALUE__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_7_WBTIMER_VALUE__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_7_WBTIMER_VALUE___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_7_WBTIMER_VALUE___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_MESSAGE_CONTENT (0x00A23078) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_MESSAGE_CONTENT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_MESSAGE_CONTENT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_MESSAGE_CONTENT__FRAME_SYNC_DELAY_COUNTS_ON_BT___POR 0x00 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_MESSAGE_CONTENT__LTE_TYPE_0_MESSAGE___POR 0x00 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_MESSAGE_CONTENT__FRAME_SYNC_DELAY_COUNTS_ON_BT___M 0x00001FE0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_MESSAGE_CONTENT__FRAME_SYNC_DELAY_COUNTS_ON_BT___S 5 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_MESSAGE_CONTENT__LTE_TYPE_0_MESSAGE___M 0x0000001F +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_MESSAGE_CONTENT__LTE_TYPE_0_MESSAGE___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_MESSAGE_CONTENT___M 0x00001FFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_MESSAGE_CONTENT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_WBTIMER_VALUE (0x00A2307C) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_WBTIMER_VALUE___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_WBTIMER_VALUE___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_WBTIMER_VALUE__VAL___POR 0x0000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_WBTIMER_VALUE__VAL___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_WBTIMER_VALUE__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_WBTIMER_VALUE___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID0_WBTIMER_VALUE___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_MESSAGE_CONTENT (0x00A23080) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_MESSAGE_CONTENT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_MESSAGE_CONTENT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_MESSAGE_CONTENT__FRAME_SYNC_DELAY_COUNTS_ON_BT___POR 0x00 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_MESSAGE_CONTENT__LTE_TYPE_0_MESSAGE___POR 0x00 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_MESSAGE_CONTENT__FRAME_SYNC_DELAY_COUNTS_ON_BT___M 0x00001FE0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_MESSAGE_CONTENT__FRAME_SYNC_DELAY_COUNTS_ON_BT___S 5 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_MESSAGE_CONTENT__LTE_TYPE_0_MESSAGE___M 0x0000001F +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_MESSAGE_CONTENT__LTE_TYPE_0_MESSAGE___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_MESSAGE_CONTENT___M 0x00001FFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_MESSAGE_CONTENT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_WBTIMER_VALUE (0x00A23084) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_WBTIMER_VALUE___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_WBTIMER_VALUE___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_WBTIMER_VALUE__VAL___POR 0x0000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_WBTIMER_VALUE__VAL___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_WBTIMER_VALUE__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_WBTIMER_VALUE___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_0_RAT_ID1_WBTIMER_VALUE___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID0_MESSAGE_CONTENT (0x00A23088) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID0_MESSAGE_CONTENT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID0_MESSAGE_CONTENT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID0_MESSAGE_CONTENT__VAL___POR 0x00 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID0_MESSAGE_CONTENT__VAL___M 0x0000001F +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID0_MESSAGE_CONTENT__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID0_MESSAGE_CONTENT___M 0x0000001F +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID0_MESSAGE_CONTENT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID0_WBTIMER_VALUE (0x00A2308C) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID0_WBTIMER_VALUE___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID0_WBTIMER_VALUE___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID0_WBTIMER_VALUE__VAL___POR 0x0000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID0_WBTIMER_VALUE__VAL___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID0_WBTIMER_VALUE__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID0_WBTIMER_VALUE___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID0_WBTIMER_VALUE___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID1_MESSAGE_CONTENT (0x00A23090) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID1_MESSAGE_CONTENT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID1_MESSAGE_CONTENT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID1_MESSAGE_CONTENT__VAL___POR 0x00 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID1_MESSAGE_CONTENT__VAL___M 0x0000001F +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID1_MESSAGE_CONTENT__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID1_MESSAGE_CONTENT___M 0x0000001F +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID1_MESSAGE_CONTENT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID1_WBTIMER_VALUE (0x00A23094) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID1_WBTIMER_VALUE___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID1_WBTIMER_VALUE___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID1_WBTIMER_VALUE__VAL___POR 0x0000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID1_WBTIMER_VALUE__VAL___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID1_WBTIMER_VALUE__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID1_WBTIMER_VALUE___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE_6_RAT_ID1_WBTIMER_VALUE___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TX_RISINGEDGE_OCCURRED_TIME (0x00A23098) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TX_RISINGEDGE_OCCURRED_TIME___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TX_RISINGEDGE_OCCURRED_TIME___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TX_RISINGEDGE_OCCURRED_TIME__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TX_RISINGEDGE_OCCURRED_TIME__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TX_RISINGEDGE_OCCURRED_TIME__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TX_RISINGEDGE_OCCURRED_TIME___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TX_RISINGEDGE_OCCURRED_TIME___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TX_FALLINGEDGE_OCCURRED_TIME (0x00A2309C) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TX_FALLINGEDGE_OCCURRED_TIME___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TX_FALLINGEDGE_OCCURRED_TIME___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TX_FALLINGEDGE_OCCURRED_TIME__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TX_FALLINGEDGE_OCCURRED_TIME__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TX_FALLINGEDGE_OCCURRED_TIME__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TX_FALLINGEDGE_OCCURRED_TIME___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TX_FALLINGEDGE_OCCURRED_TIME___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RX_RISINGEDGE_OCCURRED_TIME (0x00A230A0) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RX_RISINGEDGE_OCCURRED_TIME___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RX_RISINGEDGE_OCCURRED_TIME___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RX_RISINGEDGE_OCCURRED_TIME__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RX_RISINGEDGE_OCCURRED_TIME__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RX_RISINGEDGE_OCCURRED_TIME__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RX_RISINGEDGE_OCCURRED_TIME___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RX_RISINGEDGE_OCCURRED_TIME___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RX_FALLINGEDGE_OCCURRED_TIME (0x00A230A4) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RX_FALLINGEDGE_OCCURRED_TIME___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RX_FALLINGEDGE_OCCURRED_TIME___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RX_FALLINGEDGE_OCCURRED_TIME__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RX_FALLINGEDGE_OCCURRED_TIME__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RX_FALLINGEDGE_OCCURRED_TIME__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RX_FALLINGEDGE_OCCURRED_TIME___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RX_FALLINGEDGE_OCCURRED_TIME___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WLAN_TYPE_0_TRANSMIT_MESSAGE (0x00A230A8) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WLAN_TYPE_0_TRANSMIT_MESSAGE___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WLAN_TYPE_0_TRANSMIT_MESSAGE___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WLAN_TYPE_0_TRANSMIT_MESSAGE__OVERFLOW___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WLAN_TYPE_0_TRANSMIT_MESSAGE__MSG___POR 0x00 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WLAN_TYPE_0_TRANSMIT_MESSAGE__OVERFLOW___M 0x00000100 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WLAN_TYPE_0_TRANSMIT_MESSAGE__OVERFLOW___S 8 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WLAN_TYPE_0_TRANSMIT_MESSAGE__MSG___M 0x000000FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WLAN_TYPE_0_TRANSMIT_MESSAGE__MSG___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WLAN_TYPE_0_TRANSMIT_MESSAGE___M 0x000001FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WLAN_TYPE_0_TRANSMIT_MESSAGE___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_LOWER (0x00A230AC) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_LOWER___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_LOWER___POR 0x00181110 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_LOWER__VALUE___POR 0x00181110 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_LOWER__VALUE___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_LOWER__VALUE___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_LOWER___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_LOWER___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_REGISTER_ACCESS_ERR (0x00A230B0) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_REGISTER_ACCESS_ERR___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_REGISTER_ACCESS_ERR___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_REGISTER_ACCESS_ERR__ERR_TYPE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_REGISTER_ACCESS_ERR__ERR_ADDR___POR 0x00000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_REGISTER_ACCESS_ERR__ERR_TYPE___M 0x00060000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_REGISTER_ACCESS_ERR__ERR_TYPE___S 17 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_REGISTER_ACCESS_ERR__ERR_ADDR___M 0x0001FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_REGISTER_ACCESS_ERR__ERR_ADDR___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_REGISTER_ACCESS_ERR___M 0x0007FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_REGISTER_ACCESS_ERR___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_CTRL (0x00A230B4) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_CTRL___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_CTRL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_CTRL__EVENTBUS_SEL___POR 0x00 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_CTRL__TESTBUS_SELECT___POR 0x00 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_CTRL__EVENTBUS_SEL___M 0x00000FC0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_CTRL__EVENTBUS_SEL___S 6 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_CTRL__TESTBUS_SELECT___M 0x0000003F +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_CTRL__TESTBUS_SELECT___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_CTRL___M 0x00000FFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TESTBUS_CTRL___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_USAGE_TRACKING_CTRL (0x00A230B8) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_USAGE_TRACKING_CTRL___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_USAGE_TRACKING_CTRL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_USAGE_TRACKING_CTRL__COUNT_LTE_MODEM_RX_TIME___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_USAGE_TRACKING_CTRL__COUNT_LTE_MODEM_TX_TIME___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_USAGE_TRACKING_CTRL__COUNT_LTE_MODEM_RX_TIME___M 0x00000002 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_USAGE_TRACKING_CTRL__COUNT_LTE_MODEM_RX_TIME___S 1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_USAGE_TRACKING_CTRL__COUNT_LTE_MODEM_TX_TIME___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_USAGE_TRACKING_CTRL__COUNT_LTE_MODEM_TX_TIME___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_USAGE_TRACKING_CTRL___M 0x00000003 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_USAGE_TRACKING_CTRL___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_MEDIUM_USAGE_CNT (0x00A230BC) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_MEDIUM_USAGE_CNT___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_MEDIUM_USAGE_CNT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_MEDIUM_USAGE_CNT__MODEM_USAGE_COUNTER___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_MEDIUM_USAGE_CNT__MODEM_USAGE_COUNTER___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_MEDIUM_USAGE_CNT__MODEM_USAGE_COUNTER___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_MEDIUM_USAGE_CNT___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MODEM_MEDIUM_USAGE_CNT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_TIMEOUT_COUNT (0x00A230C0) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_TIMEOUT_COUNT___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_TIMEOUT_COUNT___POR 0x00002EE0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_TIMEOUT_COUNT__VAL___POR 0x2EE0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_TIMEOUT_COUNT__VAL___M 0x00003FFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_TIMEOUT_COUNT__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_TIMEOUT_COUNT___M 0x00003FFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_TIMEOUT_COUNT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_ENABLE (0x00A230C4) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_ENABLE___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_ENABLE___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_ENABLE__NO_RATID_MATCH_ERROR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_ENABLE__TYPE_0_MESSAGE_ERROR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_ENABLE__TYPE_6_MESSAGE_ERROR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_ENABLE__TYPE_7_MESSAGE_ERROR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_ENABLE__NO_RATID_MATCH_ERROR___M 0x00000008 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_ENABLE__NO_RATID_MATCH_ERROR___S 3 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_ENABLE__TYPE_0_MESSAGE_ERROR___M 0x00000004 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_ENABLE__TYPE_0_MESSAGE_ERROR___S 2 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_ENABLE__TYPE_6_MESSAGE_ERROR___M 0x00000002 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_ENABLE__TYPE_6_MESSAGE_ERROR___S 1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_ENABLE__TYPE_7_MESSAGE_ERROR___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_ENABLE__TYPE_7_MESSAGE_ERROR___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_ENABLE___M 0x0000000F +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_ENABLE___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_STATUS (0x00A230C8) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_STATUS___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_STATUS___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_STATUS__NO_RATID_MATCH_ERROR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_STATUS__TYPE_0_MESSAGE_ERROR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_STATUS__TYPE_6_MESSAGE_ERROR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_STATUS__TYPE_7_MESSAGE_ERROR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_STATUS__NO_RATID_MATCH_ERROR___M 0x00000008 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_STATUS__NO_RATID_MATCH_ERROR___S 3 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_STATUS__TYPE_0_MESSAGE_ERROR___M 0x00000004 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_STATUS__TYPE_0_MESSAGE_ERROR___S 2 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_STATUS__TYPE_6_MESSAGE_ERROR___M 0x00000002 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_STATUS__TYPE_6_MESSAGE_ERROR___S 1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_STATUS__TYPE_7_MESSAGE_ERROR___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_STATUS__TYPE_7_MESSAGE_ERROR___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_STATUS___M 0x0000000F +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_STATUS___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_CLEAR (0x00A230CC) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_CLEAR___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_CLEAR___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_CLEAR__NO_RATID_MATCH_ERROR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_CLEAR__TYPE_0_MESSAGE_ERROR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_CLEAR__TYPE_6_MESSAGE_ERROR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_CLEAR__TYPE_7_MESSAGE_ERROR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_CLEAR__NO_RATID_MATCH_ERROR___M 0x00000008 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_CLEAR__NO_RATID_MATCH_ERROR___S 3 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_CLEAR__TYPE_0_MESSAGE_ERROR___M 0x00000004 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_CLEAR__TYPE_0_MESSAGE_ERROR___S 2 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_CLEAR__TYPE_6_MESSAGE_ERROR___M 0x00000002 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_CLEAR__TYPE_6_MESSAGE_ERROR___S 1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_CLEAR__TYPE_7_MESSAGE_ERROR___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_CLEAR__TYPE_7_MESSAGE_ERROR___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_CLEAR___M 0x0000000F +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_TYPE7_MESSAGE_INTERRUPT_CLEAR___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_FRAME_SYNC_CAPTURED_TIMER_COUNT (0x00A230D0) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_FRAME_SYNC_CAPTURED_TIMER_COUNT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_FRAME_SYNC_CAPTURED_TIMER_COUNT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_FRAME_SYNC_CAPTURED_TIMER_COUNT__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_FRAME_SYNC_CAPTURED_TIMER_COUNT__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_FRAME_SYNC_CAPTURED_TIMER_COUNT__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_FRAME_SYNC_CAPTURED_TIMER_COUNT___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_FRAME_SYNC_CAPTURED_TIMER_COUNT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_TX_RISINGEDGE_OCCURRED_TIME (0x00A230D4) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_TX_RISINGEDGE_OCCURRED_TIME___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_TX_RISINGEDGE_OCCURRED_TIME___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_TX_RISINGEDGE_OCCURRED_TIME__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_TX_RISINGEDGE_OCCURRED_TIME__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_TX_RISINGEDGE_OCCURRED_TIME__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_TX_RISINGEDGE_OCCURRED_TIME___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_TX_RISINGEDGE_OCCURRED_TIME___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_TX_FALLINGEDGE_OCCURRED_TIME (0x00A230D8) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_TX_FALLINGEDGE_OCCURRED_TIME___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_TX_FALLINGEDGE_OCCURRED_TIME___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_TX_FALLINGEDGE_OCCURRED_TIME__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_TX_FALLINGEDGE_OCCURRED_TIME__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_TX_FALLINGEDGE_OCCURRED_TIME__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_TX_FALLINGEDGE_OCCURRED_TIME___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_TX_FALLINGEDGE_OCCURRED_TIME___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_RX_RISINGEDGE_OCCURRED_TIME (0x00A230DC) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_RX_RISINGEDGE_OCCURRED_TIME___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_RX_RISINGEDGE_OCCURRED_TIME___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_RX_RISINGEDGE_OCCURRED_TIME__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_RX_RISINGEDGE_OCCURRED_TIME__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_RX_RISINGEDGE_OCCURRED_TIME__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_RX_RISINGEDGE_OCCURRED_TIME___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_RX_RISINGEDGE_OCCURRED_TIME___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_RX_FALLINGEDGE_OCCURRED_TIME (0x00A230E0) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_RX_FALLINGEDGE_OCCURRED_TIME___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_RX_FALLINGEDGE_OCCURRED_TIME___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_RX_FALLINGEDGE_OCCURRED_TIME__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_RX_FALLINGEDGE_OCCURRED_TIME__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_RX_FALLINGEDGE_OCCURRED_TIME__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_RX_FALLINGEDGE_OCCURRED_TIME___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_0_RX_FALLINGEDGE_OCCURRED_TIME___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_TX_RISINGEDGE_OCCURRED_TIME (0x00A230E4) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_TX_RISINGEDGE_OCCURRED_TIME___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_TX_RISINGEDGE_OCCURRED_TIME___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_TX_RISINGEDGE_OCCURRED_TIME__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_TX_RISINGEDGE_OCCURRED_TIME__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_TX_RISINGEDGE_OCCURRED_TIME__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_TX_RISINGEDGE_OCCURRED_TIME___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_TX_RISINGEDGE_OCCURRED_TIME___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_TX_FALLINGEDGE_OCCURRED_TIME (0x00A230E8) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_TX_FALLINGEDGE_OCCURRED_TIME___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_TX_FALLINGEDGE_OCCURRED_TIME___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_TX_FALLINGEDGE_OCCURRED_TIME__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_TX_FALLINGEDGE_OCCURRED_TIME__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_TX_FALLINGEDGE_OCCURRED_TIME__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_TX_FALLINGEDGE_OCCURRED_TIME___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_TX_FALLINGEDGE_OCCURRED_TIME___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_RX_RISINGEDGE_OCCURRED_TIME (0x00A230EC) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_RX_RISINGEDGE_OCCURRED_TIME___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_RX_RISINGEDGE_OCCURRED_TIME___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_RX_RISINGEDGE_OCCURRED_TIME__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_RX_RISINGEDGE_OCCURRED_TIME__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_RX_RISINGEDGE_OCCURRED_TIME__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_RX_RISINGEDGE_OCCURRED_TIME___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_RX_RISINGEDGE_OCCURRED_TIME___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_RX_FALLINGEDGE_OCCURRED_TIME (0x00A230F0) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_RX_FALLINGEDGE_OCCURRED_TIME___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_RX_FALLINGEDGE_OCCURRED_TIME___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_RX_FALLINGEDGE_OCCURRED_TIME__VAL___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_RX_FALLINGEDGE_OCCURRED_TIME__VAL___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_RX_FALLINGEDGE_OCCURRED_TIME__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_RX_FALLINGEDGE_OCCURRED_TIME___M 0xFFFFFFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RATID_1_RX_FALLINGEDGE_OCCURRED_TIME___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MICRO_SECOND_COUNT_IN_MILI_SECOND (0x00A230F4) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MICRO_SECOND_COUNT_IN_MILI_SECOND___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MICRO_SECOND_COUNT_IN_MILI_SECOND___POR 0x000003E8 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MICRO_SECOND_COUNT_IN_MILI_SECOND__VAL___POR 0x3E8 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MICRO_SECOND_COUNT_IN_MILI_SECOND__VAL___M 0x000003FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MICRO_SECOND_COUNT_IN_MILI_SECOND__VAL___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MICRO_SECOND_COUNT_IN_MILI_SECOND___M 0x000003FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_MICRO_SECOND_COUNT_IN_MILI_SECOND___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2 (0x00A23108) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__WCI2_TYPE_6_RATID_1_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__WCI2_TYPE_0_RATID_1_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__WCI2_TYPE_6_RATID_0_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__WCI2_TYPE_0_RATID_0_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__INACTIVITY_TIMEOUT_RATID_1_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__INACTIVITY_TIMEOUT_RATID_0_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__FRAME_SYNC_RCVD_EARLY_RATID_1_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__FRAME_SYNC_RCVD_EARLY_RATID_0_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__INCORRECT_DELAY_RATID_1_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__INCORRECT_DELAY_RATID_0_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__SCHEDULE_COMMAND_RATID_1_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__SCHEDULE_COMMAND_RATID_0_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__REG_ACCESS_ERR_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__WCI2_TYPE_6_RATID_1_INTR___M 0x00001000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__WCI2_TYPE_6_RATID_1_INTR___S 12 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__WCI2_TYPE_0_RATID_1_INTR___M 0x00000800 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__WCI2_TYPE_0_RATID_1_INTR___S 11 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__WCI2_TYPE_6_RATID_0_INTR___M 0x00000400 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__WCI2_TYPE_6_RATID_0_INTR___S 10 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__WCI2_TYPE_0_RATID_0_INTR___M 0x00000200 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__WCI2_TYPE_0_RATID_0_INTR___S 9 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__INACTIVITY_TIMEOUT_RATID_1_INTR___M 0x00000100 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__INACTIVITY_TIMEOUT_RATID_1_INTR___S 8 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__INACTIVITY_TIMEOUT_RATID_0_INTR___M 0x00000080 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__INACTIVITY_TIMEOUT_RATID_0_INTR___S 7 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__FRAME_SYNC_RCVD_EARLY_RATID_1_INTR___M 0x00000040 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__FRAME_SYNC_RCVD_EARLY_RATID_1_INTR___S 6 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__FRAME_SYNC_RCVD_EARLY_RATID_0_INTR___M 0x00000020 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__FRAME_SYNC_RCVD_EARLY_RATID_0_INTR___S 5 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__INCORRECT_DELAY_RATID_1_INTR___M 0x00000010 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__INCORRECT_DELAY_RATID_1_INTR___S 4 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__INCORRECT_DELAY_RATID_0_INTR___M 0x00000008 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__INCORRECT_DELAY_RATID_0_INTR___S 3 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__SCHEDULE_COMMAND_RATID_1_INTR___M 0x00000004 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__SCHEDULE_COMMAND_RATID_1_INTR___S 2 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__SCHEDULE_COMMAND_RATID_0_INTR___M 0x00000002 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__SCHEDULE_COMMAND_RATID_0_INTR___S 1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__REG_ACCESS_ERR_INTR___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2__REG_ACCESS_ERR_INTR___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2___M 0x00001FFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_2___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2 (0x00A2310C) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__WCI2_TYPE_6_RATID_1_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__WCI2_TYPE_0_RATID_1_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__WCI2_TYPE_6_RATID_0_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__WCI2_TYPE_0_RATID_0_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__INACTIVITY_TIMEOUT_RATID_1_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__INACTIVITY_TIMEOUT_RATID_0_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__FRAME_SYNC_RCVD_EARLY_RATID_1_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__FRAME_SYNC_RCVD_EARLY_RATID_0_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__INCORRECT_DELAY_RATID_1_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__INCORRECT_DELAY_RATID_0_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__SCHEDULE_COMMAND_RATID_1_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__SCHEDULE_COMMAND_RATID_0_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__REG_ACCESS_ERR_INTR_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__WCI2_TYPE_6_RATID_1_INTR_ENABLE___M 0x00001000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__WCI2_TYPE_6_RATID_1_INTR_ENABLE___S 12 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__WCI2_TYPE_0_RATID_1_INTR_ENABLE___M 0x00000800 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__WCI2_TYPE_0_RATID_1_INTR_ENABLE___S 11 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__WCI2_TYPE_6_RATID_0_INTR_ENABLE___M 0x00000400 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__WCI2_TYPE_6_RATID_0_INTR_ENABLE___S 10 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__WCI2_TYPE_0_RATID_0_INTR_ENABLE___M 0x00000200 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__WCI2_TYPE_0_RATID_0_INTR_ENABLE___S 9 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__INACTIVITY_TIMEOUT_RATID_1_INTR_ENABLE___M 0x00000100 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__INACTIVITY_TIMEOUT_RATID_1_INTR_ENABLE___S 8 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__INACTIVITY_TIMEOUT_RATID_0_INTR_ENABLE___M 0x00000080 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__INACTIVITY_TIMEOUT_RATID_0_INTR_ENABLE___S 7 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__FRAME_SYNC_RCVD_EARLY_RATID_1_INTR_ENABLE___M 0x00000040 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__FRAME_SYNC_RCVD_EARLY_RATID_1_INTR_ENABLE___S 6 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__FRAME_SYNC_RCVD_EARLY_RATID_0_INTR_ENABLE___M 0x00000020 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__FRAME_SYNC_RCVD_EARLY_RATID_0_INTR_ENABLE___S 5 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__INCORRECT_DELAY_RATID_1_INTR_ENABLE___M 0x00000010 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__INCORRECT_DELAY_RATID_1_INTR_ENABLE___S 4 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__INCORRECT_DELAY_RATID_0_INTR_ENABLE___M 0x00000008 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__INCORRECT_DELAY_RATID_0_INTR_ENABLE___S 3 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__SCHEDULE_COMMAND_RATID_1_INTR_ENABLE___M 0x00000004 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__SCHEDULE_COMMAND_RATID_1_INTR_ENABLE___S 2 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__SCHEDULE_COMMAND_RATID_0_INTR_ENABLE___M 0x00000002 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__SCHEDULE_COMMAND_RATID_0_INTR_ENABLE___S 1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__REG_ACCESS_ERR_INTR_ENABLE___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2__REG_ACCESS_ERR_INTR_ENABLE___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2___M 0x00001FFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_2___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2 (0x00A23110) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__WCI2_TYPE_6_RATID_1_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__WCI2_TYPE_0_RATID_1_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__WCI2_TYPE_6_RATID_0_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__WCI2_TYPE_0_RATID_0_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__FRAME_SYNC_RCVD_EARLY_RATID_1_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__FRAME_SYNC_RCVD_EARLY_RATID_0_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__INCORRECT_DELAY_RATID_1_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__INCORRECT_DELAY_RATID_0_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__SCHEDULE_COMMAND_RATID_1_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__SCHEDULE_COMMAND_RATID_0_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__REG_ACCESS_ERR_INTR_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__WCI2_TYPE_6_RATID_1_INTR_CLEAR___M 0x00001000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__WCI2_TYPE_6_RATID_1_INTR_CLEAR___S 12 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__WCI2_TYPE_0_RATID_1_INTR_CLEAR___M 0x00000800 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__WCI2_TYPE_0_RATID_1_INTR_CLEAR___S 11 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__WCI2_TYPE_6_RATID_0_INTR_CLEAR___M 0x00000400 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__WCI2_TYPE_6_RATID_0_INTR_CLEAR___S 10 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__WCI2_TYPE_0_RATID_0_INTR_CLEAR___M 0x00000200 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__WCI2_TYPE_0_RATID_0_INTR_CLEAR___S 9 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__FRAME_SYNC_RCVD_EARLY_RATID_1_INTR_CLEAR___M 0x00000040 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__FRAME_SYNC_RCVD_EARLY_RATID_1_INTR_CLEAR___S 6 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__FRAME_SYNC_RCVD_EARLY_RATID_0_INTR_CLEAR___M 0x00000020 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__FRAME_SYNC_RCVD_EARLY_RATID_0_INTR_CLEAR___S 5 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__INCORRECT_DELAY_RATID_1_INTR_CLEAR___M 0x00000010 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__INCORRECT_DELAY_RATID_1_INTR_CLEAR___S 4 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__INCORRECT_DELAY_RATID_0_INTR_CLEAR___M 0x00000008 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__INCORRECT_DELAY_RATID_0_INTR_CLEAR___S 3 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__SCHEDULE_COMMAND_RATID_1_INTR_CLEAR___M 0x00000004 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__SCHEDULE_COMMAND_RATID_1_INTR_CLEAR___S 2 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__SCHEDULE_COMMAND_RATID_0_INTR_CLEAR___M 0x00000002 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__SCHEDULE_COMMAND_RATID_0_INTR_CLEAR___S 1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__REG_ACCESS_ERR_INTR_CLEAR___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2__REG_ACCESS_ERR_INTR_CLEAR___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2___M 0x00001E7F +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_2___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3 (0x00A23114) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID1_MWS_RX_FALLING_EDGE_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID1_MWS_RX_RISING_EDGE_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID1_MWS_TX_FALLING_EDGE_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID1_MWS_TX_RISING_EDGE_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID0_MWS_RX_FALLING_EDGE_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID0_MWS_RX_RISING_EDGE_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID0_MWS_TX_FALLING_EDGE_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID0_MWS_TX_RISING_EDGE_INTR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID1_MWS_RX_FALLING_EDGE_INTR___M 0x00000080 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID1_MWS_RX_FALLING_EDGE_INTR___S 7 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID1_MWS_RX_RISING_EDGE_INTR___M 0x00000040 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID1_MWS_RX_RISING_EDGE_INTR___S 6 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID1_MWS_TX_FALLING_EDGE_INTR___M 0x00000020 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID1_MWS_TX_FALLING_EDGE_INTR___S 5 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID1_MWS_TX_RISING_EDGE_INTR___M 0x00000010 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID1_MWS_TX_RISING_EDGE_INTR___S 4 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID0_MWS_RX_FALLING_EDGE_INTR___M 0x00000008 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID0_MWS_RX_FALLING_EDGE_INTR___S 3 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID0_MWS_RX_RISING_EDGE_INTR___M 0x00000004 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID0_MWS_RX_RISING_EDGE_INTR___S 2 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID0_MWS_TX_FALLING_EDGE_INTR___M 0x00000002 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID0_MWS_TX_FALLING_EDGE_INTR___S 1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID0_MWS_TX_RISING_EDGE_INTR___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3__RAT_ID0_MWS_TX_RISING_EDGE_INTR___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3___M 0x000000FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_STATUS_3___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3 (0x00A23118) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID1_MWS_RX_FALLING_EDGE_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID1_MWS_RX_RISING_EDGE_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID1_MWS_TX_FALLING_EDGE_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID1_MWS_TX_RISING_EDGE_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID0_MWS_RX_FALLING_EDGE_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID0_MWS_RX_RISING_EDGE_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID0_MWS_TX_FALLING_EDGE_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID0_MWS_TX_RISING_EDGE_ENABLE___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID1_MWS_RX_FALLING_EDGE_ENABLE___M 0x00000080 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID1_MWS_RX_FALLING_EDGE_ENABLE___S 7 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID1_MWS_RX_RISING_EDGE_ENABLE___M 0x00000040 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID1_MWS_RX_RISING_EDGE_ENABLE___S 6 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID1_MWS_TX_FALLING_EDGE_ENABLE___M 0x00000020 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID1_MWS_TX_FALLING_EDGE_ENABLE___S 5 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID1_MWS_TX_RISING_EDGE_ENABLE___M 0x00000010 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID1_MWS_TX_RISING_EDGE_ENABLE___S 4 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID0_MWS_RX_FALLING_EDGE_ENABLE___M 0x00000008 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID0_MWS_RX_FALLING_EDGE_ENABLE___S 3 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID0_MWS_RX_RISING_EDGE_ENABLE___M 0x00000004 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID0_MWS_RX_RISING_EDGE_ENABLE___S 2 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID0_MWS_TX_FALLING_EDGE_ENABLE___M 0x00000002 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID0_MWS_TX_FALLING_EDGE_ENABLE___S 1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID0_MWS_TX_RISING_EDGE_ENABLE___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3__RAT_ID0_MWS_TX_RISING_EDGE_ENABLE___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3___M 0x000000FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_ENABLE_3___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3 (0x00A2311C) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID1_MWS_RX_FALLING_EDGE_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID1_MWS_RX_RISING_EDGE_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID1_MWS_TX_FALLING_EDGE_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID1_MWS_TX_RISING_EDGE_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID0_MWS_RX_FALLING_EDGE_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID0_MWS_RX_RISING_EDGE_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID0_MWS_TX_FALLING_EDGE_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID0_MWS_TX_RISING_EDGE_CLEAR___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID1_MWS_RX_FALLING_EDGE_CLEAR___M 0x00000080 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID1_MWS_RX_FALLING_EDGE_CLEAR___S 7 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID1_MWS_RX_RISING_EDGE_CLEAR___M 0x00000040 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID1_MWS_RX_RISING_EDGE_CLEAR___S 6 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID1_MWS_TX_FALLING_EDGE_CLEAR___M 0x00000020 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID1_MWS_TX_FALLING_EDGE_CLEAR___S 5 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID1_MWS_TX_RISING_EDGE_CLEAR___M 0x00000010 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID1_MWS_TX_RISING_EDGE_CLEAR___S 4 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID0_MWS_RX_FALLING_EDGE_CLEAR___M 0x00000008 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID0_MWS_RX_FALLING_EDGE_CLEAR___S 3 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID0_MWS_RX_RISING_EDGE_CLEAR___M 0x00000004 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID0_MWS_RX_RISING_EDGE_CLEAR___S 2 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID0_MWS_TX_FALLING_EDGE_CLEAR___M 0x00000002 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID0_MWS_TX_FALLING_EDGE_CLEAR___S 1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID0_MWS_TX_RISING_EDGE_CLEAR___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3__RAT_ID0_MWS_TX_RISING_EDGE_CLEAR___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3___M 0x000000FF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_INTERRUPT_CLEAR_3___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RAT_ID_MODE_TX_RX_STATUS (0x00A23120) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RAT_ID_MODE_TX_RX_STATUS___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RAT_ID_MODE_TX_RX_STATUS___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RAT_ID_MODE_TX_RX_STATUS__RAT_ID1_MWS_RX___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RAT_ID_MODE_TX_RX_STATUS__RAT_ID1_MWS_TX___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RAT_ID_MODE_TX_RX_STATUS__RAT_ID0_MWS_RX___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RAT_ID_MODE_TX_RX_STATUS__RAT_ID0_MWS_TX___POR 0x0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RAT_ID_MODE_TX_RX_STATUS__RAT_ID1_MWS_RX___M 0x00000008 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RAT_ID_MODE_TX_RX_STATUS__RAT_ID1_MWS_RX___S 3 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RAT_ID_MODE_TX_RX_STATUS__RAT_ID1_MWS_TX___M 0x00000004 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RAT_ID_MODE_TX_RX_STATUS__RAT_ID1_MWS_TX___S 2 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RAT_ID_MODE_TX_RX_STATUS__RAT_ID0_MWS_RX___M 0x00000002 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RAT_ID_MODE_TX_RX_STATUS__RAT_ID0_MWS_RX___S 1 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RAT_ID_MODE_TX_RX_STATUS__RAT_ID0_MWS_TX___M 0x00000001 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RAT_ID_MODE_TX_RX_STATUS__RAT_ID0_MWS_TX___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RAT_ID_MODE_TX_RX_STATUS___M 0x0000000F +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_LTE_RAT_ID_MODE_TX_RX_STATUS___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WDOG_TIMEOUT (0x00A23128) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WDOG_TIMEOUT___RWC QCSR_REG_RW +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WDOG_TIMEOUT___POR 0x000007CF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WDOG_TIMEOUT__VALUE___POR 0x7CF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WDOG_TIMEOUT__VALUE___M 0x00000FFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WDOG_TIMEOUT__VALUE___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WDOG_TIMEOUT___M 0x00000FFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_WDOG_TIMEOUT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RCVD_CNT (0x00A23134) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RCVD_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RCVD_CNT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RCVD_CNT__TYPE0_MESSAGE_RCVD_CNT___POR 0x0000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RCVD_CNT__TYPE0_MESSAGE_RCVD_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RCVD_CNT__TYPE0_MESSAGE_RCVD_CNT___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RCVD_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RCVD_CNT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_RCVD_CNT (0x00A23138) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_RCVD_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_RCVD_CNT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_RCVD_CNT__TYPE1_MESSAGE_RCVD_CNT___POR 0x0000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_RCVD_CNT__TYPE1_MESSAGE_RCVD_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_RCVD_CNT__TYPE1_MESSAGE_RCVD_CNT___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_RCVD_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_RCVD_CNT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_RCVD_CNT (0x00A2313C) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_RCVD_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_RCVD_CNT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_RCVD_CNT__TYPE2_MESSAGE_RCVD_CNT___POR 0x0000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_RCVD_CNT__TYPE2_MESSAGE_RCVD_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_RCVD_CNT__TYPE2_MESSAGE_RCVD_CNT___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_RCVD_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_RCVD_CNT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_MSB_NIBBLE_RCVD_CNT (0x00A23140) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_MSB_NIBBLE_RCVD_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_MSB_NIBBLE_RCVD_CNT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_MSB_NIBBLE_RCVD_CNT__TYPE2_MSB_NIBBLE_RCVD_CNT___POR 0x0000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_MSB_NIBBLE_RCVD_CNT__TYPE2_MSB_NIBBLE_RCVD_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_MSB_NIBBLE_RCVD_CNT__TYPE2_MSB_NIBBLE_RCVD_CNT___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_MSB_NIBBLE_RCVD_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_MSB_NIBBLE_RCVD_CNT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_LSB_NIBBLE_RCVD_CNT (0x00A23144) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_LSB_NIBBLE_RCVD_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_LSB_NIBBLE_RCVD_CNT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_LSB_NIBBLE_RCVD_CNT__TYPE2_LSB_NIBBLE_RCVD_CNT___POR 0x0000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_LSB_NIBBLE_RCVD_CNT__TYPE2_LSB_NIBBLE_RCVD_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_LSB_NIBBLE_RCVD_CNT__TYPE2_LSB_NIBBLE_RCVD_CNT___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_LSB_NIBBLE_RCVD_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_LSB_NIBBLE_RCVD_CNT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE3_RCVD_CNT (0x00A23148) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE3_RCVD_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE3_RCVD_CNT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE3_RCVD_CNT__TYPE3_MESSAGE_RCVD_CNT___POR 0x0000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE3_RCVD_CNT__TYPE3_MESSAGE_RCVD_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE3_RCVD_CNT__TYPE3_MESSAGE_RCVD_CNT___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE3_RCVD_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE3_RCVD_CNT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE4_RCVD_CNT (0x00A2314C) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE4_RCVD_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE4_RCVD_CNT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE4_RCVD_CNT__TYPE4_MESSAGE_RCVD_CNT___POR 0x0000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE4_RCVD_CNT__TYPE4_MESSAGE_RCVD_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE4_RCVD_CNT__TYPE4_MESSAGE_RCVD_CNT___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE4_RCVD_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE4_RCVD_CNT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE5_RCVD_CNT (0x00A23150) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE5_RCVD_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE5_RCVD_CNT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE5_RCVD_CNT__TYPE5_MESSAGE_RCVD_CNT___POR 0x0000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE5_RCVD_CNT__TYPE5_MESSAGE_RCVD_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE5_RCVD_CNT__TYPE5_MESSAGE_RCVD_CNT___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE5_RCVD_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE5_RCVD_CNT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE6_RCVD_CNT (0x00A23154) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE6_RCVD_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE6_RCVD_CNT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE6_RCVD_CNT__TYPE6_MESSAGE_RCVD_CNT___POR 0x0000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE6_RCVD_CNT__TYPE6_MESSAGE_RCVD_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE6_RCVD_CNT__TYPE6_MESSAGE_RCVD_CNT___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE6_RCVD_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE6_RCVD_CNT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RCVD_CNT (0x00A23158) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RCVD_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RCVD_CNT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RCVD_CNT__TYPE7_MESSAGE_RCVD_CNT___POR 0x0000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RCVD_CNT__TYPE7_MESSAGE_RCVD_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RCVD_CNT__TYPE7_MESSAGE_RCVD_CNT___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RCVD_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RCVD_CNT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_LEGACY_SENT_CNT (0x00A2315C) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_LEGACY_SENT_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_LEGACY_SENT_CNT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_LEGACY_SENT_CNT__TYPE0_LEGACY_MESSAGE_SENT_CNT___POR 0x0000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_LEGACY_SENT_CNT__TYPE0_LEGACY_MESSAGE_SENT_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_LEGACY_SENT_CNT__TYPE0_LEGACY_MESSAGE_SENT_CNT___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_LEGACY_SENT_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_LEGACY_SENT_CNT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RATID0_SENT_CNT (0x00A23160) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RATID0_SENT_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RATID0_SENT_CNT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RATID0_SENT_CNT__TYPE0_RATID0_MESSAGE_SENT_CNT___POR 0x0000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RATID0_SENT_CNT__TYPE0_RATID0_MESSAGE_SENT_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RATID0_SENT_CNT__TYPE0_RATID0_MESSAGE_SENT_CNT___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RATID0_SENT_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RATID0_SENT_CNT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RATID1_SENT_CNT (0x00A23164) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RATID1_SENT_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RATID1_SENT_CNT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RATID1_SENT_CNT__TYPE0_RATID1_MESSAGE_SENT_CNT___POR 0x0000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RATID1_SENT_CNT__TYPE0_RATID1_MESSAGE_SENT_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RATID1_SENT_CNT__TYPE0_RATID1_MESSAGE_SENT_CNT___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RATID1_SENT_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_RATID1_SENT_CNT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_SENT_CNT (0x00A23168) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_SENT_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_SENT_CNT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_SENT_CNT__TYPE1_MESSAGE_SENT_CNT___POR 0x0000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_SENT_CNT__TYPE1_MESSAGE_SENT_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_SENT_CNT__TYPE1_MESSAGE_SENT_CNT___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_SENT_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_SENT_CNT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_SENT_CNT (0x00A2316C) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_SENT_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_SENT_CNT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_SENT_CNT__TYPE2_COMPLETE_MESSAGE_SENT_CNT___POR 0x0000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_SENT_CNT__TYPE2_COMPLETE_MESSAGE_SENT_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_SENT_CNT__TYPE2_COMPLETE_MESSAGE_SENT_CNT___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_SENT_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_SENT_CNT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_LSB_SENT_CNT (0x00A23170) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_LSB_SENT_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_LSB_SENT_CNT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_LSB_SENT_CNT__TYPE2_LSB_MESSAGE_SENT_CNT___POR 0x0000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_LSB_SENT_CNT__TYPE2_LSB_MESSAGE_SENT_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_LSB_SENT_CNT__TYPE2_LSB_MESSAGE_SENT_CNT___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_LSB_SENT_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_LSB_SENT_CNT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_MSB_SENT_CNT (0x00A23174) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_MSB_SENT_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_MSB_SENT_CNT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_MSB_SENT_CNT__TYPE2_MSB_MESSAGE_SENT_CNT___POR 0x0000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_MSB_SENT_CNT__TYPE2_MSB_MESSAGE_SENT_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_MSB_SENT_CNT__TYPE2_MSB_MESSAGE_SENT_CNT___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_MSB_SENT_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_MSB_SENT_CNT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RATID0_SENT_CNT (0x00A23178) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RATID0_SENT_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RATID0_SENT_CNT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RATID0_SENT_CNT__TYPE7_RATID0_MESSAGE_SENT_CNT___POR 0x0000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RATID0_SENT_CNT__TYPE7_RATID0_MESSAGE_SENT_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RATID0_SENT_CNT__TYPE7_RATID0_MESSAGE_SENT_CNT___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RATID0_SENT_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RATID0_SENT_CNT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RATID1_SENT_CNT (0x00A2317C) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RATID1_SENT_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RATID1_SENT_CNT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RATID1_SENT_CNT__TYPE7_RATID1_MESSAGE_SENT_CNT___POR 0x0000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RATID1_SENT_CNT__TYPE7_RATID1_MESSAGE_SENT_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RATID1_SENT_CNT__TYPE7_RATID1_MESSAGE_SENT_CNT___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RATID1_SENT_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_RATID1_SENT_CNT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_DIRWCI2_SENT_CNT (0x00A23180) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_DIRWCI2_SENT_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_DIRWCI2_SENT_CNT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_DIRWCI2_SENT_CNT__TYPE0_DIRECT_WCI2_MESSAGE_SENT_CNT___POR 0x0000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_DIRWCI2_SENT_CNT__TYPE0_DIRECT_WCI2_MESSAGE_SENT_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_DIRWCI2_SENT_CNT__TYPE0_DIRECT_WCI2_MESSAGE_SENT_CNT___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_DIRWCI2_SENT_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE0_DIRWCI2_SENT_CNT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_DIRWCI2_SENT_CNT (0x00A23184) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_DIRWCI2_SENT_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_DIRWCI2_SENT_CNT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_DIRWCI2_SENT_CNT__TYPE1_DIRECT_WCI2_MESSAGE_SENT_CNT___POR 0x0000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_DIRWCI2_SENT_CNT__TYPE1_DIRECT_WCI2_MESSAGE_SENT_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_DIRWCI2_SENT_CNT__TYPE1_DIRECT_WCI2_MESSAGE_SENT_CNT___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_DIRWCI2_SENT_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE1_DIRWCI2_SENT_CNT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_DIRWCI2_SENT_CNT (0x00A23188) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_DIRWCI2_SENT_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_DIRWCI2_SENT_CNT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_DIRWCI2_SENT_CNT__TYPE2_DIRECT_WCI2_MESSAGE_SENT_CNT___POR 0x0000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_DIRWCI2_SENT_CNT__TYPE2_DIRECT_WCI2_MESSAGE_SENT_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_DIRWCI2_SENT_CNT__TYPE2_DIRECT_WCI2_MESSAGE_SENT_CNT___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_DIRWCI2_SENT_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE2_DIRWCI2_SENT_CNT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE3_DIRWCI2_SENT_CNT (0x00A2318C) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE3_DIRWCI2_SENT_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE3_DIRWCI2_SENT_CNT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE3_DIRWCI2_SENT_CNT__TYPE3_DIRECT_WCI2_MESSAGE_SENT_CNT___POR 0x0000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE3_DIRWCI2_SENT_CNT__TYPE3_DIRECT_WCI2_MESSAGE_SENT_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE3_DIRWCI2_SENT_CNT__TYPE3_DIRECT_WCI2_MESSAGE_SENT_CNT___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE3_DIRWCI2_SENT_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE3_DIRWCI2_SENT_CNT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE4_DIRWCI2_SENT_CNT (0x00A23190) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE4_DIRWCI2_SENT_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE4_DIRWCI2_SENT_CNT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE4_DIRWCI2_SENT_CNT__TYPE4_DIRECT_WCI2_MESSAGE_SENT_CNT___POR 0x0000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE4_DIRWCI2_SENT_CNT__TYPE4_DIRECT_WCI2_MESSAGE_SENT_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE4_DIRWCI2_SENT_CNT__TYPE4_DIRECT_WCI2_MESSAGE_SENT_CNT___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE4_DIRWCI2_SENT_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE4_DIRWCI2_SENT_CNT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE5_DIRWCI2_SENT_CNT (0x00A23194) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE5_DIRWCI2_SENT_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE5_DIRWCI2_SENT_CNT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE5_DIRWCI2_SENT_CNT__TYPE5_DIRECT_WCI2_MESSAGE_SENT_CNT___POR 0x0000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE5_DIRWCI2_SENT_CNT__TYPE5_DIRECT_WCI2_MESSAGE_SENT_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE5_DIRWCI2_SENT_CNT__TYPE5_DIRECT_WCI2_MESSAGE_SENT_CNT___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE5_DIRWCI2_SENT_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE5_DIRWCI2_SENT_CNT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE6_DIRWCI2_SENT_CNT (0x00A23198) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE6_DIRWCI2_SENT_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE6_DIRWCI2_SENT_CNT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE6_DIRWCI2_SENT_CNT__TYPE6_DIRECT_WCI2_MESSAGE_SENT_CNT___POR 0x0000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE6_DIRWCI2_SENT_CNT__TYPE6_DIRECT_WCI2_MESSAGE_SENT_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE6_DIRWCI2_SENT_CNT__TYPE6_DIRECT_WCI2_MESSAGE_SENT_CNT___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE6_DIRWCI2_SENT_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE6_DIRWCI2_SENT_CNT___S 0 + +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_DIRWCI2_SENT_CNT (0x00A2319C) +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_DIRWCI2_SENT_CNT___RWC QCSR_REG_RO +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_DIRWCI2_SENT_CNT___POR 0x00000000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_DIRWCI2_SENT_CNT__TYPE7_DIRECT_WCI2_MESSAGE_SENT_CNT___POR 0x0000 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_DIRWCI2_SENT_CNT__TYPE7_DIRECT_WCI2_MESSAGE_SENT_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_DIRWCI2_SENT_CNT__TYPE7_DIRECT_WCI2_MESSAGE_SENT_CNT___S 0 +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_DIRWCI2_SENT_CNT___M 0x0000FFFF +#define UMAC_CXC_LCMH_REG_CXC_LCMH_R1_TYPE7_DIRWCI2_SENT_CNT___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL (0x00A24000) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL___POR 0x00000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__ASYNC_GP_FIFO_RESET___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__BLOCK_WCI2_FROM_BT___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__BLOCK_WCI2_TO_BT___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__TX_PARITY_CORRUPT___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__RX_PARITY_CORRUPT___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__RX_CHECKSUM_CORRUPT___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__TX_CHECKSUM_CORRUPT___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__MAX_RETRIES___POR 0x00 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__SNOOP___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__INJECT___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__CHECKSUM_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__ARBITRARY_HEADER___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__REDIRECT___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__ASYNC_GP_FIFO_RESET___M 0x00010000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__ASYNC_GP_FIFO_RESET___S 16 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__BLOCK_WCI2_FROM_BT___M 0x00008000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__BLOCK_WCI2_FROM_BT___S 15 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__BLOCK_WCI2_TO_BT___M 0x00004000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__BLOCK_WCI2_TO_BT___S 14 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__TX_PARITY_CORRUPT___M 0x00002000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__TX_PARITY_CORRUPT___S 13 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__RX_PARITY_CORRUPT___M 0x00001000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__RX_PARITY_CORRUPT___S 12 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__RX_CHECKSUM_CORRUPT___M 0x00000800 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__RX_CHECKSUM_CORRUPT___S 11 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__TX_CHECKSUM_CORRUPT___M 0x00000400 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__TX_CHECKSUM_CORRUPT___S 10 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__MAX_RETRIES___M 0x000003E0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__MAX_RETRIES___S 5 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__SNOOP___M 0x00000010 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__SNOOP___S 4 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__INJECT___M 0x00000008 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__INJECT___S 3 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__CHECKSUM_ENABLE___M 0x00000004 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__CHECKSUM_ENABLE___S 2 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__ARBITRARY_HEADER___M 0x00000002 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__ARBITRARY_HEADER___S 1 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__REDIRECT___M 0x00000001 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL__REDIRECT___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL___M 0x0001FFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODE_CTRL___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE (0x00A24004) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE___POR 0x00000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__CFG_EXT_SLV_MST_HOVR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__SL_ASSERT_DLY___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__CMCBUS_MONITOR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__AUTOSYNC___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__EDGE_CONFIG___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__BUS_SYNC_TIMEOUT___POR 0x00 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__IGNORE_ACK___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__BUS_SYNC_DRIVE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__SCRAMBLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__CFG_EXT_SLV_MST_HOVR___M 0x00180000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__CFG_EXT_SLV_MST_HOVR___S 19 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__SL_ASSERT_DLY___M 0x00078000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__SL_ASSERT_DLY___S 15 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__CMCBUS_MONITOR___M 0x00004000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__CMCBUS_MONITOR___S 14 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__AUTOSYNC___M 0x00002000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__AUTOSYNC___S 13 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__EDGE_CONFIG___M 0x00001800 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__EDGE_CONFIG___S 11 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__BUS_SYNC_TIMEOUT___M 0x000007F8 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__BUS_SYNC_TIMEOUT___S 3 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__IGNORE_ACK___M 0x00000004 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__IGNORE_ACK___S 2 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__BUS_SYNC_DRIVE___M 0x00000002 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__BUS_SYNC_DRIVE___S 1 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__SCRAMBLE___M 0x00000001 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE__SCRAMBLE___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE___M 0x001FFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_WSIM_MODE___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SMH_CTRL (0x00A24008) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SMH_CTRL___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SMH_CTRL___POR 0x00000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SMH_CTRL__DONE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SMH_CTRL__FORCE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SMH_CTRL__DONE___M 0x00000002 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SMH_CTRL__DONE___S 1 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SMH_CTRL__FORCE___M 0x00000001 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SMH_CTRL__FORCE___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SMH_CTRL___M 0x00000003 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SMH_CTRL___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_EXTRA_TYPE_MSG (0x00A2400C) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_EXTRA_TYPE_MSG___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_EXTRA_TYPE_MSG___POR 0x00000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_EXTRA_TYPE_MSG__X_VALID___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_EXTRA_TYPE_MSG__X_BODY___POR 0x00 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_EXTRA_TYPE_MSG__X_HEADER___POR 0x00 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_EXTRA_TYPE_MSG__X_VALID___M 0x00010000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_EXTRA_TYPE_MSG__X_VALID___S 16 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_EXTRA_TYPE_MSG__X_BODY___M 0x0000FF00 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_EXTRA_TYPE_MSG__X_BODY___S 8 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_EXTRA_TYPE_MSG__X_HEADER___M 0x000000FF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_EXTRA_TYPE_MSG__X_HEADER___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_EXTRA_TYPE_MSG___M 0x0001FFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_EXTRA_TYPE_MSG___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE (0x00A24010) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE___POR 0x00000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE__MCI_BTSIM_CLK_GATE_DISABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE__MCI_INJ_CLK_GATE_DISABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE__MCI_ERR_CLK_GATE_DISABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE__MCI_SNP_CLK_GATE_DISABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE__MCI_WSI_CLK_GATE_DISABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE__MCI_BTSIM_CLK_GATE_DISABLE___M 0x00000010 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE__MCI_BTSIM_CLK_GATE_DISABLE___S 4 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE__MCI_INJ_CLK_GATE_DISABLE___M 0x00000008 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE__MCI_INJ_CLK_GATE_DISABLE___S 3 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE__MCI_ERR_CLK_GATE_DISABLE___M 0x00000004 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE__MCI_ERR_CLK_GATE_DISABLE___S 2 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE__MCI_SNP_CLK_GATE_DISABLE___M 0x00000002 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE__MCI_SNP_CLK_GATE_DISABLE___S 1 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE__MCI_WSI_CLK_GATE_DISABLE___M 0x00000001 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE__MCI_WSI_CLK_GATE_DISABLE___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE___M 0x0000001F +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CLKGATE_DISABLE___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CTRL (0x00A24014) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CTRL___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CTRL___POR 0x00000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CTRL__BT_SIMULATOR_EN___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CTRL__BT_SIMULATOR_EN___M 0x00000001 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CTRL__BT_SIMULATOR_EN___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CTRL___M 0x00000001 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CTRL___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0 (0x00A24018) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0___POR 0x00001000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__MODIFIED_CONT_INFO_EN___POR 0x1 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__SCHD_INFO_2_EN___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__SCHD_INFO_1_EN___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__TX___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__REPEAT_COUNT___POR 0x00 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__SEQ_GEN_EN___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__MODIFIED_CONT_INFO_EN___M 0x00001000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__MODIFIED_CONT_INFO_EN___S 12 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__SCHD_INFO_2_EN___M 0x00000800 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__SCHD_INFO_2_EN___S 11 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__SCHD_INFO_1_EN___M 0x00000400 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__SCHD_INFO_1_EN___S 10 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__TX___M 0x00000200 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__TX___S 9 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__REPEAT_COUNT___M 0x000001FE +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__REPEAT_COUNT___S 1 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__SEQ_GEN_EN___M 0x00000001 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0__SEQ_GEN_EN___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0___M 0x00001FFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ0___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1 (0x00A2401C) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1___POR 0x00001000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__MODIFIED_CONT_INFO_EN___POR 0x1 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__SCHD_INFO_2_EN___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__SCHD_INFO_1_EN___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__TX___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__REPEAT_COUNT___POR 0x00 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__SEQ_GEN_EN___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__MODIFIED_CONT_INFO_EN___M 0x00001000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__MODIFIED_CONT_INFO_EN___S 12 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__SCHD_INFO_2_EN___M 0x00000800 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__SCHD_INFO_2_EN___S 11 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__SCHD_INFO_1_EN___M 0x00000400 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__SCHD_INFO_1_EN___S 10 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__TX___M 0x00000200 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__TX___S 9 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__REPEAT_COUNT___M 0x000001FE +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__REPEAT_COUNT___S 1 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__SEQ_GEN_EN___M 0x00000001 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1__SEQ_GEN_EN___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1___M 0x00001FFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_MSG_CNTRL_SEQ1___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG1 (0x00A24020) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG1___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG1___POR 0x00001000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG1__DWORD1___POR 0x00001000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG1__DWORD1___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG1__DWORD1___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG1___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG1___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG2 (0x00A24024) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG2___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG2___POR 0x00001800 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG2__DWORD2___POR 0x00001800 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG2__DWORD2___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG2__DWORD2___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG2___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG2___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG3 (0x00A24028) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG3___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG3___POR 0x8C040400 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG3__DWORD3___POR 0x8C040400 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG3__DWORD3___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG3__DWORD3___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG3___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG3___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG4 (0x00A2402C) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG4___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG4___POR 0x00000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG4__DWORD4___POR 0x00000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG4__DWORD4___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG4__DWORD4___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG4___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ0_REG4___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG1 (0x00A24030) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG1___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG1___POR 0x00000800 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG1__DWORD1___POR 0x00000800 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG1__DWORD1___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG1__DWORD1___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG1___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG1___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG2 (0x00A24034) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG2___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG2___POR 0x00001000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG2__DWORD2___POR 0x00001000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG2__DWORD2___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG2__DWORD2___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG2___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG2___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG3 (0x00A24038) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG3___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG3___POR 0x8C040400 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG3__DWORD3___POR 0x8C040400 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG3__DWORD3___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG3__DWORD3___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG3___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG3___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG4 (0x00A2403C) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG4___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG4___POR 0x00000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG4__DWORD4___POR 0x00000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG4__DWORD4___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG4__DWORD4___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG4___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ0_REG4___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG1 (0x00A24040) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG1___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG1___POR 0x00001000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG1__DWORD1___POR 0x00001000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG1__DWORD1___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG1__DWORD1___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG1___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG1___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG2 (0x00A24044) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG2___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG2___POR 0x00001800 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG2__DWORD2___POR 0x00001800 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG2__DWORD2___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG2__DWORD2___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG2___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG2___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG3 (0x00A24048) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG3___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG3___POR 0x84040400 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG3__DWORD3___POR 0x84040400 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG3__DWORD3___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG3__DWORD3___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG3___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG3___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG4 (0x00A2404C) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG4___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG4___POR 0x00000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG4__DWORD4___POR 0x00000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG4__DWORD4___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG4__DWORD4___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG4___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_1_SEQ1_REG4___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG1 (0x00A24050) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG1___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG1___POR 0x00000800 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG1__DWORD1___POR 0x00000800 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG1__DWORD1___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG1__DWORD1___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG1___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG1___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG2 (0x00A24054) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG2___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG2___POR 0x00001000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG2__DWORD2___POR 0x00001000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG2__DWORD2___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG2__DWORD2___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG2___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG2___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG3 (0x00A24058) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG3___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG3___POR 0x84040400 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG3__DWORD3___POR 0x84040400 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG3__DWORD3___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG3__DWORD3___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG3___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG3___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG4 (0x00A2405C) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG4___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG4___POR 0x00000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG4__DWORD4___POR 0x00000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG4__DWORD4___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG4__DWORD4___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG4___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SCHD_INFO_CONTENT_2_SEQ1_REG4___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CONT_INFO_CONTENT_SEQ0 (0x00A24060) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CONT_INFO_CONTENT_SEQ0___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CONT_INFO_CONTENT_SEQ0___POR 0x88800880 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CONT_INFO_CONTENT_SEQ0__DWORD1___POR 0x88800880 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CONT_INFO_CONTENT_SEQ0__DWORD1___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CONT_INFO_CONTENT_SEQ0__DWORD1___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CONT_INFO_CONTENT_SEQ0___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CONT_INFO_CONTENT_SEQ0___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CONT_INFO_CONTENT_SEQ1 (0x00A24064) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CONT_INFO_CONTENT_SEQ1___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CONT_INFO_CONTENT_SEQ1___POR 0x88800080 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CONT_INFO_CONTENT_SEQ1__DWORD1___POR 0x88800080 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CONT_INFO_CONTENT_SEQ1__DWORD1___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CONT_INFO_CONTENT_SEQ1__DWORD1___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CONT_INFO_CONTENT_SEQ1___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_CONT_INFO_CONTENT_SEQ1___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODIFIED_CONT_INFO_CONTENT_SEQ0 (0x00A24068) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODIFIED_CONT_INFO_CONTENT_SEQ0___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODIFIED_CONT_INFO_CONTENT_SEQ0___POR 0x80008000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODIFIED_CONT_INFO_CONTENT_SEQ0__DWORD1___POR 0x80008000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODIFIED_CONT_INFO_CONTENT_SEQ0__DWORD1___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODIFIED_CONT_INFO_CONTENT_SEQ0__DWORD1___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODIFIED_CONT_INFO_CONTENT_SEQ0___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODIFIED_CONT_INFO_CONTENT_SEQ0___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODIFIED_CONT_INFO_CONTENT_SEQ1 (0x00A2406C) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODIFIED_CONT_INFO_CONTENT_SEQ1___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODIFIED_CONT_INFO_CONTENT_SEQ1___POR 0x80008000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODIFIED_CONT_INFO_CONTENT_SEQ1__DWORD1___POR 0x80008000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODIFIED_CONT_INFO_CONTENT_SEQ1__DWORD1___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODIFIED_CONT_INFO_CONTENT_SEQ1__DWORD1___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODIFIED_CONT_INFO_CONTENT_SEQ1___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_MODIFIED_CONT_INFO_CONTENT_SEQ1___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_LNA_LOCK_CONTENT_SEQ0 (0x00A24070) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_LNA_LOCK_CONTENT_SEQ0___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_LNA_LOCK_CONTENT_SEQ0___POR 0x00000008 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_LNA_LOCK_CONTENT_SEQ0__DWORD1___POR 0x08 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_LNA_LOCK_CONTENT_SEQ0__DWORD1___M 0x000000FF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_LNA_LOCK_CONTENT_SEQ0__DWORD1___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_LNA_LOCK_CONTENT_SEQ0___M 0x000000FF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_LNA_LOCK_CONTENT_SEQ0___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_LNA_LOCK_CONTENT_SEQ1 (0x00A24074) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_LNA_LOCK_CONTENT_SEQ1___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_LNA_LOCK_CONTENT_SEQ1___POR 0x00000008 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_LNA_LOCK_CONTENT_SEQ1__DWORD1___POR 0x08 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_LNA_LOCK_CONTENT_SEQ1__DWORD1___M 0x000000FF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_LNA_LOCK_CONTENT_SEQ1__DWORD1___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_LNA_LOCK_CONTENT_SEQ1___M 0x000000FF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_LNA_LOCK_CONTENT_SEQ1___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_ABSOLUTE_WB_TIMER_SCHD_INFO_SEQ0 (0x00A24078) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_ABSOLUTE_WB_TIMER_SCHD_INFO_SEQ0___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_ABSOLUTE_WB_TIMER_SCHD_INFO_SEQ0___POR 0x00001400 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_ABSOLUTE_WB_TIMER_SCHD_INFO_SEQ0__VALUE___POR 0x00001400 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_ABSOLUTE_WB_TIMER_SCHD_INFO_SEQ0__VALUE___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_ABSOLUTE_WB_TIMER_SCHD_INFO_SEQ0__VALUE___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_ABSOLUTE_WB_TIMER_SCHD_INFO_SEQ0___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_ABSOLUTE_WB_TIMER_SCHD_INFO_SEQ0___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_1ST_SCHD_INFO_2ND_SEQ0 (0x00A2407C) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_1ST_SCHD_INFO_2ND_SEQ0___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_1ST_SCHD_INFO_2ND_SEQ0___POR 0x00000800 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_1ST_SCHD_INFO_2ND_SEQ0__VALUE___POR 0x00800 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_1ST_SCHD_INFO_2ND_SEQ0__VALUE___M 0x000FFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_1ST_SCHD_INFO_2ND_SEQ0__VALUE___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_1ST_SCHD_INFO_2ND_SEQ0___M 0x000FFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_1ST_SCHD_INFO_2ND_SEQ0___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_2ND_CONT_INFO_SEQ0 (0x00A24080) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_2ND_CONT_INFO_SEQ0___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_2ND_CONT_INFO_SEQ0___POR 0x00000800 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_2ND_CONT_INFO_SEQ0__VALUE___POR 0x00800 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_2ND_CONT_INFO_SEQ0__VALUE___M 0x000FFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_2ND_CONT_INFO_SEQ0__VALUE___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_2ND_CONT_INFO_SEQ0___M 0x000FFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_2ND_CONT_INFO_SEQ0___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_OR_LNA_LOCK_TO_CONT_RST_SEQ0 (0x00A24084) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_OR_LNA_LOCK_TO_CONT_RST_SEQ0___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_OR_LNA_LOCK_TO_CONT_RST_SEQ0___POR 0x00000800 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_OR_LNA_LOCK_TO_CONT_RST_SEQ0__VALUE___POR 0x00800 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_OR_LNA_LOCK_TO_CONT_RST_SEQ0__VALUE___M 0x000FFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_OR_LNA_LOCK_TO_CONT_RST_SEQ0__VALUE___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_OR_LNA_LOCK_TO_CONT_RST_SEQ0___M 0x000FFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_OR_LNA_LOCK_TO_CONT_RST_SEQ0___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_LNA_LOCK_SEQ0 (0x00A24088) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_LNA_LOCK_SEQ0___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_LNA_LOCK_SEQ0___POR 0x00000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_LNA_LOCK_SEQ0__VALUE___POR 0x00000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_LNA_LOCK_SEQ0__VALUE___M 0x000FFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_LNA_LOCK_SEQ0__VALUE___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_LNA_LOCK_SEQ0___M 0x000FFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_LNA_LOCK_SEQ0___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_NACK_CONT_RST_SEQ0 (0x00A2408C) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_NACK_CONT_RST_SEQ0___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_NACK_CONT_RST_SEQ0___POR 0x00000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_NACK_CONT_RST_SEQ0__VALUE___POR 0x00000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_NACK_CONT_RST_SEQ0__VALUE___M 0x000FFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_NACK_CONT_RST_SEQ0__VALUE___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_NACK_CONT_RST_SEQ0___M 0x000FFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_NACK_CONT_RST_SEQ0___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_NXT_SEQ_SEQ0 (0x00A24090) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_NXT_SEQ_SEQ0___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_NXT_SEQ_SEQ0___POR 0x00003800 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_NXT_SEQ_SEQ0__VALUE___POR 0x03800 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_NXT_SEQ_SEQ0__VALUE___M 0x000FFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_NXT_SEQ_SEQ0__VALUE___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_NXT_SEQ_SEQ0___M 0x000FFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_NXT_SEQ_SEQ0___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_ABSOLUTE_WB_TIMER_SCHD_INFO_SEQ1 (0x00A24094) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_ABSOLUTE_WB_TIMER_SCHD_INFO_SEQ1___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_ABSOLUTE_WB_TIMER_SCHD_INFO_SEQ1___POR 0x00003000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_ABSOLUTE_WB_TIMER_SCHD_INFO_SEQ1__VALUE___POR 0x00003000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_ABSOLUTE_WB_TIMER_SCHD_INFO_SEQ1__VALUE___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_ABSOLUTE_WB_TIMER_SCHD_INFO_SEQ1__VALUE___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_ABSOLUTE_WB_TIMER_SCHD_INFO_SEQ1___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_ABSOLUTE_WB_TIMER_SCHD_INFO_SEQ1___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_1ST_SCHD_INFO_2ND_SEQ1 (0x00A24098) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_1ST_SCHD_INFO_2ND_SEQ1___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_1ST_SCHD_INFO_2ND_SEQ1___POR 0x00000800 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_1ST_SCHD_INFO_2ND_SEQ1__VALUE___POR 0x00800 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_1ST_SCHD_INFO_2ND_SEQ1__VALUE___M 0x000FFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_1ST_SCHD_INFO_2ND_SEQ1__VALUE___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_1ST_SCHD_INFO_2ND_SEQ1___M 0x000FFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_1ST_SCHD_INFO_2ND_SEQ1___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_2ND_CONT_INFO_SEQ1 (0x00A2409C) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_2ND_CONT_INFO_SEQ1___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_2ND_CONT_INFO_SEQ1___POR 0x00000800 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_2ND_CONT_INFO_SEQ1__VALUE___POR 0x00800 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_2ND_CONT_INFO_SEQ1__VALUE___M 0x000FFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_2ND_CONT_INFO_SEQ1__VALUE___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_2ND_CONT_INFO_SEQ1___M 0x000FFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_SCHD_INFO_2ND_CONT_INFO_SEQ1___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_OR_LNA_LOCK_TO_CONT_RST_SEQ1 (0x00A240A0) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_OR_LNA_LOCK_TO_CONT_RST_SEQ1___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_OR_LNA_LOCK_TO_CONT_RST_SEQ1___POR 0x00000400 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_OR_LNA_LOCK_TO_CONT_RST_SEQ1__VALUE___POR 0x00400 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_OR_LNA_LOCK_TO_CONT_RST_SEQ1__VALUE___M 0x000FFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_OR_LNA_LOCK_TO_CONT_RST_SEQ1__VALUE___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_OR_LNA_LOCK_TO_CONT_RST_SEQ1___M 0x000FFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_OR_LNA_LOCK_TO_CONT_RST_SEQ1___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_LNA_LOCK_SEQ1 (0x00A240A4) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_LNA_LOCK_SEQ1___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_LNA_LOCK_SEQ1___POR 0x00000400 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_LNA_LOCK_SEQ1__VALUE___POR 0x00400 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_LNA_LOCK_SEQ1__VALUE___M 0x000FFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_LNA_LOCK_SEQ1__VALUE___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_LNA_LOCK_SEQ1___M 0x000FFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_INFO_LNA_LOCK_SEQ1___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_NACK_CONT_RST_SEQ1 (0x00A240A8) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_NACK_CONT_RST_SEQ1___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_NACK_CONT_RST_SEQ1___POR 0x00000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_NACK_CONT_RST_SEQ1__VALUE___POR 0x00000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_NACK_CONT_RST_SEQ1__VALUE___M 0x000FFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_NACK_CONT_RST_SEQ1__VALUE___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_NACK_CONT_RST_SEQ1___M 0x000FFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_CONT_NACK_CONT_RST_SEQ1___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_NXT_SEQ_SEQ1 (0x00A240AC) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_NXT_SEQ_SEQ1___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_NXT_SEQ_SEQ1___POR 0x00003800 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_NXT_SEQ_SEQ1__VALUE___POR 0x03800 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_NXT_SEQ_SEQ1__VALUE___M 0x000FFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_NXT_SEQ_SEQ1__VALUE___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_NXT_SEQ_SEQ1___M 0x000FFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_TIME_INTERVAL_NXT_SEQ_SEQ1___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_STATUS (0x00A240B0) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_STATUS___RWC QCSR_REG_RO +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_STATUS___POR 0x00000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_STATUS__SEQUENCE_COMPLETION_SEQ0___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_STATUS__SEQUENCE_COMPLETION_SEQ1___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_STATUS__SEQUENCE_ERROR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_STATUS__SEQUENCE_COMPLETION_SEQ0___M 0x00000004 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_STATUS__SEQUENCE_COMPLETION_SEQ0___S 2 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_STATUS__SEQUENCE_COMPLETION_SEQ1___M 0x00000002 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_STATUS__SEQUENCE_COMPLETION_SEQ1___S 1 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_STATUS__SEQUENCE_ERROR___M 0x00000001 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_STATUS__SEQUENCE_ERROR___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_STATUS___M 0x00000007 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_STATUS___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CLEAR_STATUS (0x00A240B4) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CLEAR_STATUS___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CLEAR_STATUS___POR 0x00000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CLEAR_STATUS__CLEAR_SEQUENCE_COMPLETION_SEQ0___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CLEAR_STATUS__CLEAR_SEQUENCE_COMPLETION_SEQ1___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CLEAR_STATUS__CLEAR_SEQUENCE_ERROR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CLEAR_STATUS__CLEAR_SEQUENCE_COMPLETION_SEQ0___M 0x00000004 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CLEAR_STATUS__CLEAR_SEQUENCE_COMPLETION_SEQ0___S 2 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CLEAR_STATUS__CLEAR_SEQUENCE_COMPLETION_SEQ1___M 0x00000002 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CLEAR_STATUS__CLEAR_SEQUENCE_COMPLETION_SEQ1___S 1 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CLEAR_STATUS__CLEAR_SEQUENCE_ERROR___M 0x00000001 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CLEAR_STATUS__CLEAR_SEQUENCE_ERROR___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CLEAR_STATUS___M 0x00000007 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_BT_SIMULATOR_CLEAR_STATUS___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SEQ_ERROR_COUNTER (0x00A240B8) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SEQ_ERROR_COUNTER___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SEQ_ERROR_COUNTER___POR 0x00000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SEQ_ERROR_COUNTER__SEQ_ERROR_CNT_EN___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SEQ_ERROR_COUNTER__SEQ_ERROR_CNT_CLEAR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SEQ_ERROR_COUNTER__SEQ_ERROR_CNT___POR 0x00000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SEQ_ERROR_COUNTER__SEQ_ERROR_CNT_EN___M 0x80000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SEQ_ERROR_COUNTER__SEQ_ERROR_CNT_EN___S 31 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SEQ_ERROR_COUNTER__SEQ_ERROR_CNT_CLEAR___M 0x40000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SEQ_ERROR_COUNTER__SEQ_ERROR_CNT_CLEAR___S 30 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SEQ_ERROR_COUNTER__SEQ_ERROR_CNT___M 0x000FFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SEQ_ERROR_COUNTER__SEQ_ERROR_CNT___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SEQ_ERROR_COUNTER___M 0xC00FFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R0_SEQ_ERROR_COUNTER___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT (0x00A25000) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT___RWC QCSR_REG_RO +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT___POR 0x00000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__INJECTOR_ERROR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__SETUP_TIME_CHECK_ERR_EVENT___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__CCU_ACCESS_ERR_EVENT___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__GETFIFOOVERWRITE_ERROR_EVENT___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__DESTINATION_ERROR_EVENT___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__RX_NAK_ERROR_EVENT___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__TX_NAK_ERROR_EVENT___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__WSI_STAT_ERROR_EVENT___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__BUSSYNC_ERROR_EVENT___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__CHECKSUM_ERROR_EVENT___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__PMU_TYPE2_ERROR_EVENT___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__PMU_TYPE1_ERROR_EVENT___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__LTE_TYPE2_ERROR_EVENT___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__LTE_TYPE1_ERROR_EVENT___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__LNA_TYPE2_ERROR_EVENT___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__LNA_TYPE1_ERROR_EVENT___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__BTC_TYPE2_ERROR_EVENT___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__BTC_TYPE1_ERROR_EVENT___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__SW_TYPE2_ERROR_EVENT___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__SW_TYPE1_ERROR_EVENT___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__INJECTOR_ERROR___M 0x00080000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__INJECTOR_ERROR___S 19 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__SETUP_TIME_CHECK_ERR_EVENT___M 0x00040000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__SETUP_TIME_CHECK_ERR_EVENT___S 18 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__CCU_ACCESS_ERR_EVENT___M 0x00020000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__CCU_ACCESS_ERR_EVENT___S 17 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__GETFIFOOVERWRITE_ERROR_EVENT___M 0x00010000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__GETFIFOOVERWRITE_ERROR_EVENT___S 16 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__DESTINATION_ERROR_EVENT___M 0x00008000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__DESTINATION_ERROR_EVENT___S 15 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__RX_NAK_ERROR_EVENT___M 0x00004000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__RX_NAK_ERROR_EVENT___S 14 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__TX_NAK_ERROR_EVENT___M 0x00002000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__TX_NAK_ERROR_EVENT___S 13 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__WSI_STAT_ERROR_EVENT___M 0x00001000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__WSI_STAT_ERROR_EVENT___S 12 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__BUSSYNC_ERROR_EVENT___M 0x00000800 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__BUSSYNC_ERROR_EVENT___S 11 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__CHECKSUM_ERROR_EVENT___M 0x00000400 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__CHECKSUM_ERROR_EVENT___S 10 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__PMU_TYPE2_ERROR_EVENT___M 0x00000200 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__PMU_TYPE2_ERROR_EVENT___S 9 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__PMU_TYPE1_ERROR_EVENT___M 0x00000100 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__PMU_TYPE1_ERROR_EVENT___S 8 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__LTE_TYPE2_ERROR_EVENT___M 0x00000080 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__LTE_TYPE2_ERROR_EVENT___S 7 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__LTE_TYPE1_ERROR_EVENT___M 0x00000040 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__LTE_TYPE1_ERROR_EVENT___S 6 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__LNA_TYPE2_ERROR_EVENT___M 0x00000020 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__LNA_TYPE2_ERROR_EVENT___S 5 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__LNA_TYPE1_ERROR_EVENT___M 0x00000010 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__LNA_TYPE1_ERROR_EVENT___S 4 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__BTC_TYPE2_ERROR_EVENT___M 0x00000008 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__BTC_TYPE2_ERROR_EVENT___S 3 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__BTC_TYPE1_ERROR_EVENT___M 0x00000004 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__BTC_TYPE1_ERROR_EVENT___S 2 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__SW_TYPE2_ERROR_EVENT___M 0x00000002 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__SW_TYPE2_ERROR_EVENT___S 1 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__SW_TYPE1_ERROR_EVENT___M 0x00000001 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT__SW_TYPE1_ERROR_EVENT___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT___M 0x000FFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_EVENT___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE (0x00A25004) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE___POR 0x00000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__SETUP_TIME_CHECK_ERR_EVENT_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__CCU_ACCESS_ERR_EVENT_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__GETFIFOOVERWRITE_ERROR_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__DESTINATION_ERROR_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__RX_NAK_ERROR_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__TX_NAK_ERROR_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__WSI_STAT_ERROR_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__BUSSYNC_ERROR_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__CHECKSUM_ERROR_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__PMU_TYPE2_ERROR_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__PMU_TYPE1_ERROR_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__LTE_TYPE2_ERROR_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__LTE_TYPE1_ERROR_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__LNA_TYPE2_ERROR_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__LNA_TYPE1_ERROR_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__BTC_TYPE2_ERROR_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__BTC_TYPE1_ERROR_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__SW_TYPE2_ERROR_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__SW_TYPE1_ERROR_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__SETUP_TIME_CHECK_ERR_EVENT_ENABLE___M 0x00040000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__SETUP_TIME_CHECK_ERR_EVENT_ENABLE___S 18 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__CCU_ACCESS_ERR_EVENT_ENABLE___M 0x00020000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__CCU_ACCESS_ERR_EVENT_ENABLE___S 17 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__GETFIFOOVERWRITE_ERROR_ENABLE___M 0x00010000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__GETFIFOOVERWRITE_ERROR_ENABLE___S 16 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__DESTINATION_ERROR_ENABLE___M 0x00008000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__DESTINATION_ERROR_ENABLE___S 15 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__RX_NAK_ERROR_ENABLE___M 0x00004000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__RX_NAK_ERROR_ENABLE___S 14 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__TX_NAK_ERROR_ENABLE___M 0x00002000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__TX_NAK_ERROR_ENABLE___S 13 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__WSI_STAT_ERROR_ENABLE___M 0x00001000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__WSI_STAT_ERROR_ENABLE___S 12 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__BUSSYNC_ERROR_ENABLE___M 0x00000800 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__BUSSYNC_ERROR_ENABLE___S 11 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__CHECKSUM_ERROR_ENABLE___M 0x00000400 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__CHECKSUM_ERROR_ENABLE___S 10 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__PMU_TYPE2_ERROR_ENABLE___M 0x00000200 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__PMU_TYPE2_ERROR_ENABLE___S 9 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__PMU_TYPE1_ERROR_ENABLE___M 0x00000100 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__PMU_TYPE1_ERROR_ENABLE___S 8 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__LTE_TYPE2_ERROR_ENABLE___M 0x00000080 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__LTE_TYPE2_ERROR_ENABLE___S 7 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__LTE_TYPE1_ERROR_ENABLE___M 0x00000040 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__LTE_TYPE1_ERROR_ENABLE___S 6 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__LNA_TYPE2_ERROR_ENABLE___M 0x00000020 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__LNA_TYPE2_ERROR_ENABLE___S 5 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__LNA_TYPE1_ERROR_ENABLE___M 0x00000010 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__LNA_TYPE1_ERROR_ENABLE___S 4 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__BTC_TYPE2_ERROR_ENABLE___M 0x00000008 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__BTC_TYPE2_ERROR_ENABLE___S 3 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__BTC_TYPE1_ERROR_ENABLE___M 0x00000004 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__BTC_TYPE1_ERROR_ENABLE___S 2 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__SW_TYPE2_ERROR_ENABLE___M 0x00000002 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__SW_TYPE2_ERROR_ENABLE___S 1 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__SW_TYPE1_ERROR_ENABLE___M 0x00000001 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE__SW_TYPE1_ERROR_ENABLE___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE___M 0x0007FFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_INTERRUPT_ENABLE___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY (0x00A25008) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY___POR 0x00000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__SETUP_TIME_CHECK_ERR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__CCU_ACCESS_ERR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__GETFIFOOVERWRITE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__DESTINATION___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__RX_NAK___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__TX_NAK___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__WSI_STAT___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__BUSSYNC___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__CHECKSUM___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__PMU_TYPE2_ERROR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__PMU_TYPE1_ERROR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__LTE_TYPE2_ERROR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__LTE_TYPE1_ERROR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__LNA_TYPE2_ERROR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__LNA_TYPE1_ERROR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__BTC_TYPE2_ERROR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__BTC_TYPE1_ERROR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__SW_TYPE2_ERROR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__SW_TYPE1_ERROR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__SETUP_TIME_CHECK_ERR___M 0x00040000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__SETUP_TIME_CHECK_ERR___S 18 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__CCU_ACCESS_ERR___M 0x00020000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__CCU_ACCESS_ERR___S 17 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__GETFIFOOVERWRITE___M 0x00010000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__GETFIFOOVERWRITE___S 16 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__DESTINATION___M 0x00008000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__DESTINATION___S 15 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__RX_NAK___M 0x00004000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__RX_NAK___S 14 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__TX_NAK___M 0x00002000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__TX_NAK___S 13 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__WSI_STAT___M 0x00001000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__WSI_STAT___S 12 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__BUSSYNC___M 0x00000800 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__BUSSYNC___S 11 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__CHECKSUM___M 0x00000400 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__CHECKSUM___S 10 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__PMU_TYPE2_ERROR___M 0x00000200 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__PMU_TYPE2_ERROR___S 9 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__PMU_TYPE1_ERROR___M 0x00000100 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__PMU_TYPE1_ERROR___S 8 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__LTE_TYPE2_ERROR___M 0x00000080 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__LTE_TYPE2_ERROR___S 7 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__LTE_TYPE1_ERROR___M 0x00000040 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__LTE_TYPE1_ERROR___S 6 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__LNA_TYPE2_ERROR___M 0x00000020 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__LNA_TYPE2_ERROR___S 5 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__LNA_TYPE1_ERROR___M 0x00000010 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__LNA_TYPE1_ERROR___S 4 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__BTC_TYPE2_ERROR___M 0x00000008 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__BTC_TYPE2_ERROR___S 3 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__BTC_TYPE1_ERROR___M 0x00000004 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__BTC_TYPE1_ERROR___S 2 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__SW_TYPE2_ERROR___M 0x00000002 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__SW_TYPE2_ERROR___S 1 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__SW_TYPE1_ERROR___M 0x00000001 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY__SW_TYPE1_ERROR___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY___M 0x0007FFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_SEVERITY___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR (0x00A2500C) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR___POR 0x00000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__INJECTOR_ERROR_CLEAR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__SETUP_TIME_CHECK_ERR_CLEAR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__CCU_ACCESS_ERR_CLEAR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__GETFIFOOVERWRITE_CLEAR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__DESTINATION_ERROR_CLEAR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__RX_NAK_ERROR_CLEAR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__TX_NAK_ERROR_CLEAR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__WSI_STAT_ERROR_CLEAR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__BUSSYNC_ERROR_CLEAR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__CHECKSUM_ERROR_CLEAR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__PMU_TYPE2_ERROR_CLEAR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__PMU_TYPE1_ERROR_CLEAR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__LTE_TYPE2_ERROR_CLEAR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__LTE_TYPE1_ERROR_CLEAR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__LNA_TYPE2_ERROR_CLEAR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__LNA_TYPE1_ERROR_CLEAR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__BTC_TYPE2_ERROR_CLEAR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__BTC_TYPE1_ERROR_CLEAR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__SW_TYPE2_ERROR_CLEAR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__SW_TYPE1_ERROR_CLEAR___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__INJECTOR_ERROR_CLEAR___M 0x00080000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__INJECTOR_ERROR_CLEAR___S 19 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__SETUP_TIME_CHECK_ERR_CLEAR___M 0x00040000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__SETUP_TIME_CHECK_ERR_CLEAR___S 18 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__CCU_ACCESS_ERR_CLEAR___M 0x00020000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__CCU_ACCESS_ERR_CLEAR___S 17 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__GETFIFOOVERWRITE_CLEAR___M 0x00010000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__GETFIFOOVERWRITE_CLEAR___S 16 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__DESTINATION_ERROR_CLEAR___M 0x00008000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__DESTINATION_ERROR_CLEAR___S 15 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__RX_NAK_ERROR_CLEAR___M 0x00004000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__RX_NAK_ERROR_CLEAR___S 14 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__TX_NAK_ERROR_CLEAR___M 0x00002000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__TX_NAK_ERROR_CLEAR___S 13 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__WSI_STAT_ERROR_CLEAR___M 0x00001000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__WSI_STAT_ERROR_CLEAR___S 12 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__BUSSYNC_ERROR_CLEAR___M 0x00000800 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__BUSSYNC_ERROR_CLEAR___S 11 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__CHECKSUM_ERROR_CLEAR___M 0x00000400 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__CHECKSUM_ERROR_CLEAR___S 10 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__PMU_TYPE2_ERROR_CLEAR___M 0x00000200 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__PMU_TYPE2_ERROR_CLEAR___S 9 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__PMU_TYPE1_ERROR_CLEAR___M 0x00000100 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__PMU_TYPE1_ERROR_CLEAR___S 8 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__LTE_TYPE2_ERROR_CLEAR___M 0x00000080 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__LTE_TYPE2_ERROR_CLEAR___S 7 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__LTE_TYPE1_ERROR_CLEAR___M 0x00000040 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__LTE_TYPE1_ERROR_CLEAR___S 6 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__LNA_TYPE2_ERROR_CLEAR___M 0x00000020 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__LNA_TYPE2_ERROR_CLEAR___S 5 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__LNA_TYPE1_ERROR_CLEAR___M 0x00000010 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__LNA_TYPE1_ERROR_CLEAR___S 4 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__BTC_TYPE2_ERROR_CLEAR___M 0x00000008 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__BTC_TYPE2_ERROR_CLEAR___S 3 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__BTC_TYPE1_ERROR_CLEAR___M 0x00000004 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__BTC_TYPE1_ERROR_CLEAR___S 2 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__SW_TYPE2_ERROR_CLEAR___M 0x00000002 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__SW_TYPE2_ERROR_CLEAR___S 1 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__SW_TYPE1_ERROR_CLEAR___M 0x00000001 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR__SW_TYPE1_ERROR_CLEAR___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR___M 0x000FFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_ERROR_CLEAR___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INJECT_ADDR (0x00A25010) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INJECT_ADDR___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INJECT_ADDR___POR 0x00000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INJECT_ADDR__FULL___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INJECT_ADDR__TAIL_MARK___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INJECT_ADDR__INJECT_DATA___POR 0x00 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INJECT_ADDR__FULL___M 0x80000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INJECT_ADDR__FULL___S 31 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INJECT_ADDR__TAIL_MARK___M 0x00000100 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INJECT_ADDR__TAIL_MARK___S 8 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INJECT_ADDR__INJECT_DATA___M 0x000000FF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INJECT_ADDR__INJECT_DATA___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INJECT_ADDR___M 0x800001FF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INJECT_ADDR___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_SNOOP_ADDR (0x00A25014) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_SNOOP_ADDR___RWC QCSR_REG_RO +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_SNOOP_ADDR___POR 0x00000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_SNOOP_ADDR__VALID___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_SNOOP_ADDR__HEAD_MARK___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_SNOOP_ADDR__TAIL_MARK___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_SNOOP_ADDR__SNOOP_DATA___POR 0x00 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_SNOOP_ADDR__VALID___M 0x00000400 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_SNOOP_ADDR__VALID___S 10 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_SNOOP_ADDR__HEAD_MARK___M 0x00000200 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_SNOOP_ADDR__HEAD_MARK___S 9 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_SNOOP_ADDR__TAIL_MARK___M 0x00000100 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_SNOOP_ADDR__TAIL_MARK___S 8 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_SNOOP_ADDR__SNOOP_DATA___M 0x000000FF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_SNOOP_ADDR__SNOOP_DATA___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_SNOOP_ADDR___M 0x000007FF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_SNOOP_ADDR___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL (0x00A25018) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL___POR 0x00000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE2___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE3___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE4___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE5___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE6___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__TESTBUS_SELECT___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE___M 0xF0000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE___S 28 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE2___M 0x01000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE2___S 24 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE3___M 0x00800000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE3___S 23 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE4___M 0x00400000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE4___S 22 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE5___M 0x00200000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE5___S 21 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE6___M 0x00100000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__SPARE6___S 20 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__TESTBUS_SELECT___M 0x0000000F +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL__TESTBUS_SELECT___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL___M 0xF1F0000F +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TESTBUS_CTRL___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INVALID_APB_ACC_ADR (0x00A2501C) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INVALID_APB_ACC_ADR___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INVALID_APB_ACC_ADR___POR 0x00000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INVALID_APB_ACC_ADR__ERR_TYPE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INVALID_APB_ACC_ADR__ERR_ADDR___POR 0x00000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INVALID_APB_ACC_ADR__ERR_TYPE___M 0x00060000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INVALID_APB_ACC_ADR__ERR_TYPE___S 17 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INVALID_APB_ACC_ADR__ERR_ADDR___M 0x0001FFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INVALID_APB_ACC_ADR__ERR_ADDR___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INVALID_APB_ACC_ADR___M 0x0007FFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_INVALID_APB_ACC_ADR___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_WSIM_STATES (0x00A25020) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_WSIM_STATES___RWC QCSR_REG_RO +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_WSIM_STATES___POR 0x00000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_WSIM_STATES__MCI_WSIM_STATE___POR 0x000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_WSIM_STATES__WSIM_STATER___POR 0x000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_WSIM_STATES__MCI_WSIM_STATE___M 0xFFE00000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_WSIM_STATES__MCI_WSIM_STATE___S 21 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_WSIM_STATES__WSIM_STATER___M 0x001FFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_WSIM_STATES__WSIM_STATER___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_WSIM_STATES___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_WSIM_STATES___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_STATES (0x00A25024) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_STATES___RWC QCSR_REG_RO +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_STATES___POR 0x00000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_STATES__INJECT_STATE___POR 0x00 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_STATES__SNOOP_STATE___POR 0x00 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_STATES__INJECT_STATE___M 0x00000FC0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_STATES__INJECT_STATE___S 6 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_STATES__SNOOP_STATE___M 0x0000003F +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_STATES__SNOOP_STATE___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_STATES___M 0x00000FFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_DEBUG_STATES___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE (0x00A25028) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE___POR 0x000C0000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__TX_CPU_INT_CTRL___POR 0x1 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__RX_CPU_INT_CTRL___POR 0x1 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__PATTERNMATCH_HIT_EVENT_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__GETFIFOOVERWRITE_EVENT_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__DESTINATION_EVENT_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__RX_NAK_EVENT_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__TX_NAK_EVENT_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__WSI_STAT_EVENT_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__BUSSYNC_EVENT_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__CHECKSUM_EVENT_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__PMU_TYPE2_EVENT_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__PMU_TYPE1_EVENT_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__LTE_TYPE2_EVENT_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__LTE_TYPE1_EVENT_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__LNA_TYPE2_EVENT_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__LNA_TYPE1_EVENT_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__BTC_TYPE2_EVENT_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__BTC_TYPE1_EVENT_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__SW_TYPE2_EVENT_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__SW_TYPE1_EVENT_ENABLE___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__TX_CPU_INT_CTRL___M 0x00080000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__TX_CPU_INT_CTRL___S 19 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__RX_CPU_INT_CTRL___M 0x00040000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__RX_CPU_INT_CTRL___S 18 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__PATTERNMATCH_HIT_EVENT_ENABLE___M 0x00020000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__PATTERNMATCH_HIT_EVENT_ENABLE___S 17 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__GETFIFOOVERWRITE_EVENT_ENABLE___M 0x00010000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__GETFIFOOVERWRITE_EVENT_ENABLE___S 16 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__DESTINATION_EVENT_ENABLE___M 0x00008000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__DESTINATION_EVENT_ENABLE___S 15 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__RX_NAK_EVENT_ENABLE___M 0x00004000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__RX_NAK_EVENT_ENABLE___S 14 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__TX_NAK_EVENT_ENABLE___M 0x00002000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__TX_NAK_EVENT_ENABLE___S 13 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__WSI_STAT_EVENT_ENABLE___M 0x00001000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__WSI_STAT_EVENT_ENABLE___S 12 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__BUSSYNC_EVENT_ENABLE___M 0x00000800 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__BUSSYNC_EVENT_ENABLE___S 11 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__CHECKSUM_EVENT_ENABLE___M 0x00000400 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__CHECKSUM_EVENT_ENABLE___S 10 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__PMU_TYPE2_EVENT_ENABLE___M 0x00000200 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__PMU_TYPE2_EVENT_ENABLE___S 9 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__PMU_TYPE1_EVENT_ENABLE___M 0x00000100 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__PMU_TYPE1_EVENT_ENABLE___S 8 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__LTE_TYPE2_EVENT_ENABLE___M 0x00000080 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__LTE_TYPE2_EVENT_ENABLE___S 7 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__LTE_TYPE1_EVENT_ENABLE___M 0x00000040 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__LTE_TYPE1_EVENT_ENABLE___S 6 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__LNA_TYPE2_EVENT_ENABLE___M 0x00000020 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__LNA_TYPE2_EVENT_ENABLE___S 5 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__LNA_TYPE1_EVENT_ENABLE___M 0x00000010 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__LNA_TYPE1_EVENT_ENABLE___S 4 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__BTC_TYPE2_EVENT_ENABLE___M 0x00000008 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__BTC_TYPE2_EVENT_ENABLE___S 3 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__BTC_TYPE1_EVENT_ENABLE___M 0x00000004 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__BTC_TYPE1_EVENT_ENABLE___S 2 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__SW_TYPE2_EVENT_ENABLE___M 0x00000002 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__SW_TYPE2_EVENT_ENABLE___S 1 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__SW_TYPE1_EVENT_ENABLE___M 0x00000001 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE__SW_TYPE1_EVENT_ENABLE___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE___M 0x000FFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_TRC_CTRL_ENABLE___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_VALUE (0x00A2502C) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_VALUE___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_VALUE___POR 0x00000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_VALUE__PATTERN_BYTE_3___POR 0x00 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_VALUE__PATTERN_BYTE_2___POR 0x00 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_VALUE__PATTERN_BYTE_1___POR 0x00 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_VALUE__PATTERN_BYTE_0___POR 0x00 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_VALUE__PATTERN_BYTE_3___M 0xFF000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_VALUE__PATTERN_BYTE_3___S 24 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_VALUE__PATTERN_BYTE_2___M 0x00FF0000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_VALUE__PATTERN_BYTE_2___S 16 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_VALUE__PATTERN_BYTE_1___M 0x0000FF00 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_VALUE__PATTERN_BYTE_1___S 8 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_VALUE__PATTERN_BYTE_0___M 0x000000FF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_VALUE__PATTERN_BYTE_0___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_VALUE___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_VALUE___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_MASK (0x00A25030) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_MASK___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_MASK___POR 0x00000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_MASK__PATTERN_MASK_BYTE_3___POR 0x00 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_MASK__PATTERN_MASK_BYTE_2___POR 0x00 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_MASK__PATTERN_MASK_BYTE_1___POR 0x00 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_MASK__PATTERN_MASK_BYTE_0___POR 0x00 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_MASK__PATTERN_MASK_BYTE_3___M 0xFF000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_MASK__PATTERN_MASK_BYTE_3___S 24 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_MASK__PATTERN_MASK_BYTE_2___M 0x00FF0000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_MASK__PATTERN_MASK_BYTE_2___S 16 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_MASK__PATTERN_MASK_BYTE_1___M 0x0000FF00 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_MASK__PATTERN_MASK_BYTE_1___S 8 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_MASK__PATTERN_MASK_BYTE_0___M 0x000000FF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_MASK__PATTERN_MASK_BYTE_0___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_MASK___M 0xFFFFFFFF +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_MASK___S 0 + +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_CTRL (0x00A25034) +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_CTRL___RWC QCSR_REG_RW +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_CTRL___POR 0x00000000 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_CTRL__PATTERN_HITS_COUNTER___POR 0x00 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_CTRL__OFFSET_BYTES___POR 0x0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_CTRL__PATTERN_HITS_COUNTER___M 0x0000FF00 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_CTRL__PATTERN_HITS_COUNTER___S 8 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_CTRL__OFFSET_BYTES___M 0x0000000F +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_CTRL__OFFSET_BYTES___S 0 +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_CTRL___M 0x0000FF0F +#define UMAC_CXC_MCIBASIC_REG_CXC_MCIBASIC_R1_EVENT_PATTERN_CTRL___S 0 + +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_TIMEOUT (0x00A26000) +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_TIMEOUT___RWC QCSR_REG_RW +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_TIMEOUT___POR 0x0000000A +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_TIMEOUT__TIMEOUT___POR 0x0A +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_TIMEOUT__TIMEOUT___M 0x000000FF +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_TIMEOUT__TIMEOUT___S 0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_TIMEOUT___M 0x000000FF +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_TIMEOUT___S 0 + +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_LNA_IN_USE_TIMEOUT (0x00A26004) +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_LNA_IN_USE_TIMEOUT___RWC QCSR_REG_RW +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_LNA_IN_USE_TIMEOUT___POR 0x000003E8 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_LNA_IN_USE_TIMEOUT__TIMEOUT___POR 0x03E8 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_LNA_IN_USE_TIMEOUT__TIMEOUT___M 0x00003FFF +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_LNA_IN_USE_TIMEOUT__TIMEOUT___S 0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_LNA_IN_USE_TIMEOUT___M 0x00003FFF +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_LNA_IN_USE_TIMEOUT___S 0 + +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_LNA_LOCKED_TIMEOUT (0x00A26008) +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_LNA_LOCKED_TIMEOUT___RWC QCSR_REG_RW +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_LNA_LOCKED_TIMEOUT___POR 0x000003E8 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_LNA_LOCKED_TIMEOUT__TIMEOUT___POR 0x000003E8 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_LNA_LOCKED_TIMEOUT__TIMEOUT___M 0xFFFFFFFF +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_LNA_LOCKED_TIMEOUT__TIMEOUT___S 0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_LNA_LOCKED_TIMEOUT___M 0xFFFFFFFF +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_LNA_LOCKED_TIMEOUT___S 0 + +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_BT_LOCK_DETAILS (0x00A2600C) +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_BT_LOCK_DETAILS___RWC QCSR_REG_RO +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_BT_LOCK_DETAILS___POR 0x00000000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_BT_LOCK_DETAILS__BT_LNA_GAIN_IDX___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_BT_LOCK_DETAILS__BT_LNA_GAIN_IDX___M 0x000000F0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_BT_LOCK_DETAILS__BT_LNA_GAIN_IDX___S 4 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_BT_LOCK_DETAILS___M 0x000000F0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_BT_LOCK_DETAILS___S 4 + +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_DETAILS (0x00A26010) +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_DETAILS___RWC QCSR_REG_RO +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_DETAILS___POR 0x00000000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_DETAILS__BT_LNA_GAIN_IDX___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_DETAILS__BT_LNA_IN_USE___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_DETAILS__LNA_BT_LOCK___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_DETAILS__BT_LNA_GAIN_IDX___M 0x000000F0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_DETAILS__BT_LNA_GAIN_IDX___S 4 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_DETAILS__BT_LNA_IN_USE___M 0x00000002 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_DETAILS__BT_LNA_IN_USE___S 1 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_DETAILS__LNA_BT_LOCK___M 0x00000001 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_DETAILS__LNA_BT_LOCK___S 0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_DETAILS___M 0x000000F3 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_MCI_LNA_STATE_DETAILS___S 0 + +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_RX_MCI_LNA_BT_LOCK_TIMESTAMP (0x00A26014) +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_RX_MCI_LNA_BT_LOCK_TIMESTAMP___RWC QCSR_REG_RO +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_RX_MCI_LNA_BT_LOCK_TIMESTAMP___POR 0x00000000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_RX_MCI_LNA_BT_LOCK_TIMESTAMP__RX_TIMESTAMP___POR 0x00000000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_RX_MCI_LNA_BT_LOCK_TIMESTAMP__RX_TIMESTAMP___M 0xFFFFFFFF +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_RX_MCI_LNA_BT_LOCK_TIMESTAMP__RX_TIMESTAMP___S 0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_RX_MCI_LNA_BT_LOCK_TIMESTAMP___M 0xFFFFFFFF +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_RX_MCI_LNA_BT_LOCK_TIMESTAMP___S 0 + +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_RX_MCI_LNA_STATE_TIMESTAMP (0x00A26018) +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_RX_MCI_LNA_STATE_TIMESTAMP___RWC QCSR_REG_RO +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_RX_MCI_LNA_STATE_TIMESTAMP___POR 0x00000000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_RX_MCI_LNA_STATE_TIMESTAMP__RX_TIMESTAMP___POR 0x00000000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_RX_MCI_LNA_STATE_TIMESTAMP__RX_TIMESTAMP___M 0xFFFFFFFF +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_RX_MCI_LNA_STATE_TIMESTAMP__RX_TIMESTAMP___S 0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_RX_MCI_LNA_STATE_TIMESTAMP___M 0xFFFFFFFF +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_RX_MCI_LNA_STATE_TIMESTAMP___S 0 + +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_TX_MCI_LNA_TRANS_TIMESTAMP (0x00A2601C) +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_TX_MCI_LNA_TRANS_TIMESTAMP___RWC QCSR_REG_RO +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_TX_MCI_LNA_TRANS_TIMESTAMP___POR 0x00000000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_TX_MCI_LNA_TRANS_TIMESTAMP__TX_TIMESTAMP___POR 0x00000000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_TX_MCI_LNA_TRANS_TIMESTAMP__TX_TIMESTAMP___M 0xFFFFFFFF +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_TX_MCI_LNA_TRANS_TIMESTAMP__TX_TIMESTAMP___S 0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_TX_MCI_LNA_TRANS_TIMESTAMP___M 0xFFFFFFFF +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_TX_MCI_LNA_TRANS_TIMESTAMP___S 0 + +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_TX_MCI_LNA_TAKE_TIMESTAMP (0x00A26020) +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_TX_MCI_LNA_TAKE_TIMESTAMP___RWC QCSR_REG_RO +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_TX_MCI_LNA_TAKE_TIMESTAMP___POR 0x00000000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_TX_MCI_LNA_TAKE_TIMESTAMP__TX_TIMESTAMP___POR 0x00000000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_TX_MCI_LNA_TAKE_TIMESTAMP__TX_TIMESTAMP___M 0xFFFFFFFF +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_TX_MCI_LNA_TAKE_TIMESTAMP__TX_TIMESTAMP___S 0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_TX_MCI_LNA_TAKE_TIMESTAMP___M 0xFFFFFFFF +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_TX_MCI_LNA_TAKE_TIMESTAMP___S 0 + +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE (0x00A26024) +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE___RWC QCSR_REG_RW +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE___POR 0x00400000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LOGIC_0___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_RST___POR 0x1 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_IN_USE___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_LOCKED___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_GAIN_IDX___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LOGIC_00___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_RST_OVERWRITE_EN___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_IN_USE_OVERWRITE_EN___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_LOCKED_OVERWRITE_EN___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_GAIN_IDX_OVERWRITE_EN___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LOGIC_000___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_RST_SW_SETTING___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_IN_USE_SW_SETTING___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_LOCKED_SW_SETTING___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_GAIN_IDX_SW_SETTING___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LOGIC_0___M 0x00800000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LOGIC_0___S 23 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_RST___M 0x00400000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_RST___S 22 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_IN_USE___M 0x00200000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_IN_USE___S 21 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_LOCKED___M 0x00100000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_LOCKED___S 20 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_GAIN_IDX___M 0x000F0000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_GAIN_IDX___S 16 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LOGIC_00___M 0x00008000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LOGIC_00___S 15 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_RST_OVERWRITE_EN___M 0x00004000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_RST_OVERWRITE_EN___S 14 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_IN_USE_OVERWRITE_EN___M 0x00002000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_IN_USE_OVERWRITE_EN___S 13 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_LOCKED_OVERWRITE_EN___M 0x00001000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_LOCKED_OVERWRITE_EN___S 12 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_GAIN_IDX_OVERWRITE_EN___M 0x00000F00 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_GAIN_IDX_OVERWRITE_EN___S 8 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LOGIC_000___M 0x00000080 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LOGIC_000___S 7 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_RST_SW_SETTING___M 0x00000040 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_RST_SW_SETTING___S 6 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_IN_USE_SW_SETTING___M 0x00000020 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_IN_USE_SW_SETTING___S 5 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_LOCKED_SW_SETTING___M 0x00000010 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_LOCKED_SW_SETTING___S 4 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_GAIN_IDX_SW_SETTING___M 0x0000000F +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE__LNA_GAIN_IDX_SW_SETTING___S 0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE___M 0x00FFFFFF +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY1_SIGNAL_OVERWRITE___S 0 + +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE (0x00A26028) +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE___RWC QCSR_REG_RW +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE___POR 0x00400000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LOGIC_0___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_RST___POR 0x1 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_IN_USE___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_LOCKED___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_GAIN_IDX___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LOGIC_00___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_RST_OVERWRITE_EN___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_IN_USE_OVERWRITE_EN___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_LOCKED_OVERWRITE_EN___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_GAIN_IDX_OVERWRITE_EN___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LOGIC_000___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_RST_SW_SETTING___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_IN_USE_SW_SETTING___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_LOCKED_SW_SETTING___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_GAIN_IDX_SW_SETTING___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LOGIC_0___M 0x00800000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LOGIC_0___S 23 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_RST___M 0x00400000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_RST___S 22 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_IN_USE___M 0x00200000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_IN_USE___S 21 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_LOCKED___M 0x00100000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_LOCKED___S 20 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_GAIN_IDX___M 0x000F0000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_GAIN_IDX___S 16 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LOGIC_00___M 0x00008000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LOGIC_00___S 15 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_RST_OVERWRITE_EN___M 0x00004000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_RST_OVERWRITE_EN___S 14 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_IN_USE_OVERWRITE_EN___M 0x00002000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_IN_USE_OVERWRITE_EN___S 13 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_LOCKED_OVERWRITE_EN___M 0x00001000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_LOCKED_OVERWRITE_EN___S 12 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_GAIN_IDX_OVERWRITE_EN___M 0x00000F00 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_GAIN_IDX_OVERWRITE_EN___S 8 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LOGIC_000___M 0x00000080 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LOGIC_000___S 7 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_RST_SW_SETTING___M 0x00000040 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_RST_SW_SETTING___S 6 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_IN_USE_SW_SETTING___M 0x00000020 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_IN_USE_SW_SETTING___S 5 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_LOCKED_SW_SETTING___M 0x00000010 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_LOCKED_SW_SETTING___S 4 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_GAIN_IDX_SW_SETTING___M 0x0000000F +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE__LNA_GAIN_IDX_SW_SETTING___S 0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE___M 0x00FFFFFF +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY2_SIGNAL_OVERWRITE___S 0 + +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_CLKGATE_DISABLE (0x00A2602C) +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_CLKGATE_DISABLE___RWC QCSR_REG_RW +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_CLKGATE_DISABLE___POR 0x00000000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_CLKGATE_DISABLE__VAL___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_CLKGATE_DISABLE__VAL___M 0x00000001 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_CLKGATE_DISABLE__VAL___S 0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_CLKGATE_DISABLE___M 0x00000001 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_CLKGATE_DISABLE___S 0 + +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE (0x00A26030) +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE___RWC QCSR_REG_RW +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE___POR 0x00400000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LOGIC_0___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_RST___POR 0x1 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_IN_USE___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_LOCKED___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_GAIN_IDX___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LOGIC_00___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_RST_OVERWRITE_EN___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_IN_USE_OVERWRITE_EN___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_LOCKED_OVERWRITE_EN___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_GAIN_IDX_OVERWRITE_EN___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LOGIC_000___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_RST_SW_SETTING___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_IN_USE_SW_SETTING___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_LOCKED_SW_SETTING___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_GAIN_IDX_SW_SETTING___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LOGIC_0___M 0x00800000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LOGIC_0___S 23 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_RST___M 0x00400000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_RST___S 22 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_IN_USE___M 0x00200000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_IN_USE___S 21 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_LOCKED___M 0x00100000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_LOCKED___S 20 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_GAIN_IDX___M 0x000F0000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_GAIN_IDX___S 16 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LOGIC_00___M 0x00008000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LOGIC_00___S 15 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_RST_OVERWRITE_EN___M 0x00004000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_RST_OVERWRITE_EN___S 14 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_IN_USE_OVERWRITE_EN___M 0x00002000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_IN_USE_OVERWRITE_EN___S 13 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_LOCKED_OVERWRITE_EN___M 0x00001000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_LOCKED_OVERWRITE_EN___S 12 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_GAIN_IDX_OVERWRITE_EN___M 0x00000F00 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_GAIN_IDX_OVERWRITE_EN___S 8 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LOGIC_000___M 0x00000080 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LOGIC_000___S 7 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_RST_SW_SETTING___M 0x00000040 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_RST_SW_SETTING___S 6 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_IN_USE_SW_SETTING___M 0x00000020 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_IN_USE_SW_SETTING___S 5 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_LOCKED_SW_SETTING___M 0x00000010 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_LOCKED_SW_SETTING___S 4 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_GAIN_IDX_SW_SETTING___M 0x0000000F +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE__LNA_GAIN_IDX_SW_SETTING___S 0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE___M 0x00FFFFFF +#define UMAC_CXC_LMH_REG_CXC_LMH_R0_PHY3_SIGNAL_OVERWRITE___S 0 + +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS (0x00A27000) +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS___POR 0x00000000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__CCU_ACCESS_ERR_INT___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__LNA_LOCKED_TIMEOUT_INT___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__LNA_IN_USE_TIMEOUT_INT___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__LNA_STATE_TIMEOUT_INT___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__BT_LNA_IN_USE_CLR_INT___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__BT_LNA_IN_USE_INT___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__BT_UNLOCKED_INT___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__BT_LOCKED_INT___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__RX_MCI_LNA_BT_LOCK_INT___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__RX_MCI_LNA_STATE_INT___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__CCU_ACCESS_ERR_INT___M 0x00000200 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__CCU_ACCESS_ERR_INT___S 9 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__LNA_LOCKED_TIMEOUT_INT___M 0x00000100 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__LNA_LOCKED_TIMEOUT_INT___S 8 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__LNA_IN_USE_TIMEOUT_INT___M 0x00000080 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__LNA_IN_USE_TIMEOUT_INT___S 7 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__LNA_STATE_TIMEOUT_INT___M 0x00000040 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__LNA_STATE_TIMEOUT_INT___S 6 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__BT_LNA_IN_USE_CLR_INT___M 0x00000020 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__BT_LNA_IN_USE_CLR_INT___S 5 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__BT_LNA_IN_USE_INT___M 0x00000010 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__BT_LNA_IN_USE_INT___S 4 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__BT_UNLOCKED_INT___M 0x00000008 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__BT_UNLOCKED_INT___S 3 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__BT_LOCKED_INT___M 0x00000004 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__BT_LOCKED_INT___S 2 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__RX_MCI_LNA_BT_LOCK_INT___M 0x00000002 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__RX_MCI_LNA_BT_LOCK_INT___S 1 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__RX_MCI_LNA_STATE_INT___M 0x00000001 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS__RX_MCI_LNA_STATE_INT___S 0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS___M 0x000003FF +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_STATUS___S 0 + +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE (0x00A27004) +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE___RWC QCSR_REG_RW +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE___POR 0x00000000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__CCU_ACCESS_ERR_INT_EN___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__LNA_LOCKED_TIMEOUT_INT_EN___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__LNA_IN_USE_TIMEOUT_INT_EN___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__LNA_STATE_TIMEOUT_INT_EN___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__BT_LNA_IN_USE_CLR_INT_EN___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__BT_LNA_IN_USE_INT_EN___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__BT_UNLOCKED_INT_EN___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__BT_LOCKED_INT_EN___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__RX_MCI_LNA_BT_LOCK_INT_EN___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__RX_MCI_LNA_STATE_INT_EN___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__CCU_ACCESS_ERR_INT_EN___M 0x00000200 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__CCU_ACCESS_ERR_INT_EN___S 9 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__LNA_LOCKED_TIMEOUT_INT_EN___M 0x00000100 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__LNA_LOCKED_TIMEOUT_INT_EN___S 8 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__LNA_IN_USE_TIMEOUT_INT_EN___M 0x00000080 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__LNA_IN_USE_TIMEOUT_INT_EN___S 7 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__LNA_STATE_TIMEOUT_INT_EN___M 0x00000040 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__LNA_STATE_TIMEOUT_INT_EN___S 6 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__BT_LNA_IN_USE_CLR_INT_EN___M 0x00000020 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__BT_LNA_IN_USE_CLR_INT_EN___S 5 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__BT_LNA_IN_USE_INT_EN___M 0x00000010 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__BT_LNA_IN_USE_INT_EN___S 4 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__BT_UNLOCKED_INT_EN___M 0x00000008 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__BT_UNLOCKED_INT_EN___S 3 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__BT_LOCKED_INT_EN___M 0x00000004 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__BT_LOCKED_INT_EN___S 2 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__RX_MCI_LNA_BT_LOCK_INT_EN___M 0x00000002 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__RX_MCI_LNA_BT_LOCK_INT_EN___S 1 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__RX_MCI_LNA_STATE_INT_EN___M 0x00000001 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE__RX_MCI_LNA_STATE_INT_EN___S 0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE___M 0x000003FF +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_ENABLE___S 0 + +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR (0x00A27008) +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR___RWC QCSR_REG_RW +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR___POR 0x00000000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__CCU_ACCESS_ERR_INT_CLR___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__LNA_LOCKED_TIMEOUT_INT_CLR___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__LNA_IN_USE_TIMEOUT_INT_CLR___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__LNA_STATE_TIMEOUT_INT_CLR___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__BT_LNA_IN_USE_CLR_INT_CLR___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__BT_LNA_IN_USE_INT_CLR___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__BT_UNLOCKED_INT_CLR___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__BT_LOCKED_INT_CLR___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__RX_MCI_LNA_BT_LOCK_INT_CLR___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__RX_MCI_LNA_STATE_INT_CLR___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__CCU_ACCESS_ERR_INT_CLR___M 0x00000200 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__CCU_ACCESS_ERR_INT_CLR___S 9 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__LNA_LOCKED_TIMEOUT_INT_CLR___M 0x00000100 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__LNA_LOCKED_TIMEOUT_INT_CLR___S 8 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__LNA_IN_USE_TIMEOUT_INT_CLR___M 0x00000080 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__LNA_IN_USE_TIMEOUT_INT_CLR___S 7 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__LNA_STATE_TIMEOUT_INT_CLR___M 0x00000040 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__LNA_STATE_TIMEOUT_INT_CLR___S 6 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__BT_LNA_IN_USE_CLR_INT_CLR___M 0x00000020 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__BT_LNA_IN_USE_CLR_INT_CLR___S 5 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__BT_LNA_IN_USE_INT_CLR___M 0x00000010 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__BT_LNA_IN_USE_INT_CLR___S 4 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__BT_UNLOCKED_INT_CLR___M 0x00000008 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__BT_UNLOCKED_INT_CLR___S 3 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__BT_LOCKED_INT_CLR___M 0x00000004 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__BT_LOCKED_INT_CLR___S 2 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__RX_MCI_LNA_BT_LOCK_INT_CLR___M 0x00000002 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__RX_MCI_LNA_BT_LOCK_INT_CLR___S 1 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__RX_MCI_LNA_STATE_INT_CLR___M 0x00000001 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR__RX_MCI_LNA_STATE_INT_CLR___S 0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR___M 0x000003FF +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INT_CLR___S 0 + +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INVALID_APB_ACC_ADR (0x00A2700C) +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INVALID_APB_ACC_ADR___RWC QCSR_REG_RW +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INVALID_APB_ACC_ADR___POR 0x00000000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INVALID_APB_ACC_ADR__ERR_TYPE___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INVALID_APB_ACC_ADR__ERR_ADDR___POR 0x00000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INVALID_APB_ACC_ADR__ERR_TYPE___M 0x00060000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INVALID_APB_ACC_ADR__ERR_TYPE___S 17 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INVALID_APB_ACC_ADR__ERR_ADDR___M 0x0001FFFF +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INVALID_APB_ACC_ADR__ERR_ADDR___S 0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INVALID_APB_ACC_ADR___M 0x0007FFFF +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_INVALID_APB_ACC_ADR___S 0 + +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_DEBUG_STATES (0x00A27010) +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_DEBUG_STATES___RWC QCSR_REG_RO +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_DEBUG_STATES___POR 0x00000000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_DEBUG_STATES__STATE_INFO___POR 0x00000000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_DEBUG_STATES__STATE_INFO___M 0xFFFFFFFF +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_DEBUG_STATES__STATE_INFO___S 0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_DEBUG_STATES___M 0xFFFFFFFF +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_DEBUG_STATES___S 0 + +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TESTBUS_CTRL (0x00A27014) +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TESTBUS_CTRL___RWC QCSR_REG_RW +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TESTBUS_CTRL___POR 0x00000000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TESTBUS_CTRL__SPARE___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TESTBUS_CTRL__SPARE2___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TESTBUS_CTRL__TESTBUS_SELECT___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TESTBUS_CTRL__SPARE___M 0xF0000000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TESTBUS_CTRL__SPARE___S 28 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TESTBUS_CTRL__SPARE2___M 0x01000000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TESTBUS_CTRL__SPARE2___S 24 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TESTBUS_CTRL__TESTBUS_SELECT___M 0x0000000F +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TESTBUS_CTRL__TESTBUS_SELECT___S 0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TESTBUS_CTRL___M 0xF100000F +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TESTBUS_CTRL___S 0 + +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS (0x00A27018) +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS___RWC QCSR_REG_RO +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS___POR 0x00000000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__CCU_ACCESS_ERR_EVENT___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__LNA_LOCKED_TIMEOUT_EVENT___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__LNA_IN_USE_TIMEOUT_EVENT___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__LNA_STATE_TIMEOUT_EVENT___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__BT_LNA_IN_USE_CLR_EVENT___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__BT_LNA_IN_USE_EVENT___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__BT_UNLOCKED_EVENT___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__BT_LOCKED_EVENT___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__RX_MCI_LNA_BT_LOCK_EVENT___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__RX_MCI_LNA_STATE_EVENT___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__CCU_ACCESS_ERR_EVENT___M 0x00000200 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__CCU_ACCESS_ERR_EVENT___S 9 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__LNA_LOCKED_TIMEOUT_EVENT___M 0x00000100 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__LNA_LOCKED_TIMEOUT_EVENT___S 8 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__LNA_IN_USE_TIMEOUT_EVENT___M 0x00000080 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__LNA_IN_USE_TIMEOUT_EVENT___S 7 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__LNA_STATE_TIMEOUT_EVENT___M 0x00000040 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__LNA_STATE_TIMEOUT_EVENT___S 6 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__BT_LNA_IN_USE_CLR_EVENT___M 0x00000020 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__BT_LNA_IN_USE_CLR_EVENT___S 5 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__BT_LNA_IN_USE_EVENT___M 0x00000010 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__BT_LNA_IN_USE_EVENT___S 4 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__BT_UNLOCKED_EVENT___M 0x00000008 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__BT_UNLOCKED_EVENT___S 3 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__BT_LOCKED_EVENT___M 0x00000004 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__BT_LOCKED_EVENT___S 2 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__RX_MCI_LNA_BT_LOCK_EVENT___M 0x00000002 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__RX_MCI_LNA_BT_LOCK_EVENT___S 1 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__RX_MCI_LNA_STATE_EVENT___M 0x00000001 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS__RX_MCI_LNA_STATE_EVENT___S 0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS___M 0x000003FF +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_STATUS___S 0 + +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE (0x00A2701C) +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE___RWC QCSR_REG_RW +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE___POR 0x00000000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__CCU_ACCESS_ERR_EVENT_EN___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__LNA_LOCKED_TIMEOUT_EVENT_EN___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__LNA_IN_USE_TIMEOUT_EVENT_EN___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__LNA_STATE_TIMEOUT_EVENT_EN___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__BT_LNA_IN_USE_CLR_EVENT_EN___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__BT_LNA_IN_USE_EVENT_EN___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__BT_UNLOCKED_EVENT_EN___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__BT_LOCKED_EVENT_EN___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__RX_MCI_LNA_BT_LOCK_EVENT_EN___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__RX_MCI_LNA_STATE_EVENT_EN___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__CCU_ACCESS_ERR_EVENT_EN___M 0x00000200 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__CCU_ACCESS_ERR_EVENT_EN___S 9 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__LNA_LOCKED_TIMEOUT_EVENT_EN___M 0x00000100 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__LNA_LOCKED_TIMEOUT_EVENT_EN___S 8 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__LNA_IN_USE_TIMEOUT_EVENT_EN___M 0x00000080 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__LNA_IN_USE_TIMEOUT_EVENT_EN___S 7 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__LNA_STATE_TIMEOUT_EVENT_EN___M 0x00000040 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__LNA_STATE_TIMEOUT_EVENT_EN___S 6 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__BT_LNA_IN_USE_CLR_EVENT_EN___M 0x00000020 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__BT_LNA_IN_USE_CLR_EVENT_EN___S 5 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__BT_LNA_IN_USE_EVENT_EN___M 0x00000010 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__BT_LNA_IN_USE_EVENT_EN___S 4 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__BT_UNLOCKED_EVENT_EN___M 0x00000008 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__BT_UNLOCKED_EVENT_EN___S 3 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__BT_LOCKED_EVENT_EN___M 0x00000004 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__BT_LOCKED_EVENT_EN___S 2 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__RX_MCI_LNA_BT_LOCK_EVENT_EN___M 0x00000002 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__RX_MCI_LNA_BT_LOCK_EVENT_EN___S 1 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__RX_MCI_LNA_STATE_EVENT_EN___M 0x00000001 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE__RX_MCI_LNA_STATE_EVENT_EN___S 0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE___M 0x000003FF +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_ENABLE___S 0 + +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR (0x00A27020) +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR___RWC QCSR_REG_RW +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR___POR 0x00000000 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__CCU_ACCESS_ERR_EVENT_CLR___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__LNA_LOCKED_TIMEOUT_EVENT_CLR___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__LNA_IN_USE_TIMEOUT_EVENT_CLR___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__LNA_STATE_TIMEOUT_EVENT_CLR___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__BT_LNA_IN_USE_CLR_EVENT_CLR___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__BT_LNA_IN_USE_EVENT_CLR___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__BT_UNLOCKED_EVENT_CLR___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__BT_LOCKED_EVENT_CLR___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__RX_MCI_LNA_BT_LOCK_EVENT_CLR___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__RX_MCI_LNA_STATE_EVENT_CLR___POR 0x0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__CCU_ACCESS_ERR_EVENT_CLR___M 0x00000200 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__CCU_ACCESS_ERR_EVENT_CLR___S 9 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__LNA_LOCKED_TIMEOUT_EVENT_CLR___M 0x00000100 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__LNA_LOCKED_TIMEOUT_EVENT_CLR___S 8 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__LNA_IN_USE_TIMEOUT_EVENT_CLR___M 0x00000080 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__LNA_IN_USE_TIMEOUT_EVENT_CLR___S 7 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__LNA_STATE_TIMEOUT_EVENT_CLR___M 0x00000040 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__LNA_STATE_TIMEOUT_EVENT_CLR___S 6 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__BT_LNA_IN_USE_CLR_EVENT_CLR___M 0x00000020 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__BT_LNA_IN_USE_CLR_EVENT_CLR___S 5 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__BT_LNA_IN_USE_EVENT_CLR___M 0x00000010 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__BT_LNA_IN_USE_EVENT_CLR___S 4 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__BT_UNLOCKED_EVENT_CLR___M 0x00000008 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__BT_UNLOCKED_EVENT_CLR___S 3 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__BT_LOCKED_EVENT_CLR___M 0x00000004 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__BT_LOCKED_EVENT_CLR___S 2 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__RX_MCI_LNA_BT_LOCK_EVENT_CLR___M 0x00000002 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__RX_MCI_LNA_BT_LOCK_EVENT_CLR___S 1 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__RX_MCI_LNA_STATE_EVENT_CLR___M 0x00000001 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR__RX_MCI_LNA_STATE_EVENT_CLR___S 0 +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR___M 0x000003FF +#define UMAC_CXC_LMH_REG_CXC_LMH_R1_TRC_CTRL_CLR___S 0 + +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_BASE_ADDR (0x00A28000) +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_BASE_ADDR___RWC QCSR_REG_RW +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_BASE_ADDR___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_BASE_ADDR__RX_MCI_GPM_BASE_ADDRESS___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_BASE_ADDR__RX_MCI_GPM_BASE_ADDRESS___M 0xFFFFFFFC +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_BASE_ADDR__RX_MCI_GPM_BASE_ADDRESS___S 2 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_BASE_ADDR___M 0xFFFFFFFC +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_BASE_ADDR___S 2 + +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_BASE_ADDR2 (0x00A28004) +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_BASE_ADDR2___RWC QCSR_REG_RW +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_BASE_ADDR2___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_BASE_ADDR2__RX_MCI_GPM_BASE_ADDRESS___POR 0x00 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_BASE_ADDR2__RX_MCI_GPM_BASE_ADDRESS___M 0x0000001F +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_BASE_ADDR2__RX_MCI_GPM_BASE_ADDRESS___S 0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_BASE_ADDR2___M 0x0000001F +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_BASE_ADDR2___S 0 + +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_ENTRIES (0x00A28008) +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_ENTRIES___RWC QCSR_REG_RW +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_ENTRIES___POR 0x00000015 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_ENTRIES__MAX_NR_OF_RING_ENTRIES___POR 0x15 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_ENTRIES__MAX_NR_OF_RING_ENTRIES___M 0x000000FF +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_ENTRIES__MAX_NR_OF_RING_ENTRIES___S 0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_ENTRIES___M 0x000000FF +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_ENTRIES___S 0 + +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_HEAD_INDEX (0x00A2800C) +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_HEAD_INDEX___RWC QCSR_REG_RW +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_HEAD_INDEX___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_HEAD_INDEX__MCI_RX_CTRL_DISABLE_TIMESTAMP___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_HEAD_INDEX__HEAD_INDEX___POR 0x00 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_HEAD_INDEX__MCI_RX_CTRL_DISABLE_TIMESTAMP___M 0x00000100 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_HEAD_INDEX__MCI_RX_CTRL_DISABLE_TIMESTAMP___S 8 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_HEAD_INDEX__HEAD_INDEX___M 0x000000FF +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_HEAD_INDEX__HEAD_INDEX___S 0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_HEAD_INDEX___M 0x000001FF +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_HEAD_INDEX___S 0 + +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_TAIL_INDEX (0x00A28010) +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_TAIL_INDEX___RWC QCSR_REG_RW +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_TAIL_INDEX___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_TAIL_INDEX__TAIL_INDEX___POR 0x00 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_TAIL_INDEX__TAIL_INDEX___M 0x000000FF +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_TAIL_INDEX__TAIL_INDEX___S 0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_TAIL_INDEX___M 0x000000FF +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_GPM_RING_TAIL_INDEX___S 0 + +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT (0x00A28014) +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT___RWC QCSR_REG_RO +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT__MCI_CPU_INT_BODY___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT__MCI_CPU_INT_BODY___M 0xFFFFFFFF +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT__MCI_CPU_INT_BODY___S 0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT___M 0xFFFFFFFF +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT___S 0 + +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT_EN (0x00A28018) +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT_EN___RWC QCSR_REG_RW +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT_EN___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT_EN__MCI_CPU_INT_EN___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT_EN__MCI_CPU_INT_EN___M 0xFFFFFFFF +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT_EN__MCI_CPU_INT_EN___S 0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT_EN___M 0xFFFFFFFF +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT_EN___S 0 + +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT_CLR (0x00A2801C) +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT_CLR___RWC QCSR_REG_RW +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT_CLR___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT_CLR__MCI_CPU_CLR___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT_CLR__MCI_CPU_CLR___M 0xFFFFFFFF +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT_CLR__MCI_CPU_CLR___S 0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT_CLR___M 0xFFFFFFFF +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_RX_MCI_CPU_INT_CLR___S 0 + +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_BODY (0x00A28020) +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_BODY___RWC QCSR_REG_RW +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_BODY___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_BODY__MCI_CPU_INT_BODY___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_BODY__MCI_CPU_INT_BODY___M 0xFFFFFFFF +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_BODY__MCI_CPU_INT_BODY___S 0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_BODY___M 0xFFFFFFFF +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_BODY___S 0 + +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_CTRL (0x00A28024) +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_CTRL___RWC QCSR_REG_RW +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_CTRL___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_CTRL__TRANSFER_PWRDOWN_ERR___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_CTRL__TX_MCI_CPU_INT___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_CTRL__TRANSFER_PWRDOWN_ERR___M 0x00000002 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_CTRL__TRANSFER_PWRDOWN_ERR___S 1 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_CTRL__TX_MCI_CPU_INT___M 0x00000001 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_CTRL__TX_MCI_CPU_INT___S 0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_CTRL___M 0x00000003 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_CPU_INT_CTRL___S 0 + +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_T1 (0x00A28028) +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_T1___RWC QCSR_REG_RW +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_T1___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_T1__MCI_GPM_T1___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_T1__MCI_GPM_T1___M 0xFFFFFFFF +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_T1__MCI_GPM_T1___S 0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_T1___M 0xFFFFFFFF +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_T1___S 0 + +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_0 (0x00A2802C) +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_0___RWC QCSR_REG_RW +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_0___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_0__MCI_GPM_BODY0_3___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_0__MCI_GPM_BODY0_3___M 0xFFFFFFFF +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_0__MCI_GPM_BODY0_3___S 0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_0___M 0xFFFFFFFF +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_0___S 0 + +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_1 (0x00A28030) +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_1___RWC QCSR_REG_RW +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_1___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_1__MCI_GPM_BODY4_7___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_1__MCI_GPM_BODY4_7___M 0xFFFFFFFF +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_1__MCI_GPM_BODY4_7___S 0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_1___M 0xFFFFFFFF +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_1___S 0 + +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_2 (0x00A28034) +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_2___RWC QCSR_REG_RW +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_2___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_2__MCI_GPM_BODY8_11___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_2__MCI_GPM_BODY8_11___M 0xFFFFFFFF +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_2__MCI_GPM_BODY8_11___S 0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_2___M 0xFFFFFFFF +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_BODY_IX_2___S 0 + +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_CTRL (0x00A28038) +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_CTRL___RWC QCSR_REG_RW +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_CTRL___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_CTRL__MCI_GPM_2_MCI_SCHD_INFO___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_CTRL__MCI_COMMAND0_DISABLE_TIMESTAMP___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_CTRL__TRANSFER_PWRDOWN_ERR___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_CTRL__TX_MCI_GPM___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_CTRL__MCI_GPM_2_MCI_SCHD_INFO___M 0x00000008 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_CTRL__MCI_GPM_2_MCI_SCHD_INFO___S 3 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_CTRL__MCI_COMMAND0_DISABLE_TIMESTAMP___M 0x00000004 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_CTRL__MCI_COMMAND0_DISABLE_TIMESTAMP___S 2 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_CTRL__TRANSFER_PWRDOWN_ERR___M 0x00000002 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_CTRL__TRANSFER_PWRDOWN_ERR___S 1 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_CTRL__TX_MCI_GPM___M 0x00000001 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_CTRL__TX_MCI_GPM___S 0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_CTRL___M 0x0000000F +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_GPM_CTRL___S 0 + +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_REMOTE_RESET_CTRL (0x00A2803C) +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_REMOTE_RESET_CTRL___RWC QCSR_REG_RW +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_REMOTE_RESET_CTRL___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_REMOTE_RESET_CTRL__TRANSFER_PWRDOWN_ERR___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_REMOTE_RESET_CTRL__TX_MCI_REMOTE_RESET___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_REMOTE_RESET_CTRL__TRANSFER_PWRDOWN_ERR___M 0x00000002 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_REMOTE_RESET_CTRL__TRANSFER_PWRDOWN_ERR___S 1 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_REMOTE_RESET_CTRL__TX_MCI_REMOTE_RESET___M 0x00000001 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_REMOTE_RESET_CTRL__TX_MCI_REMOTE_RESET___S 0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_REMOTE_RESET_CTRL___M 0x00000003 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TX_MCI_REMOTE_RESET_CTRL___S 0 + +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TRIGGER_MESSAGE_BODY (0x00A28040) +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TRIGGER_MESSAGE_BODY___RWC QCSR_REG_RW +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TRIGGER_MESSAGE_BODY___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TRIGGER_MESSAGE_BODY__MCI_CPU_INT_BODY___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TRIGGER_MESSAGE_BODY__MCI_CPU_INT_BODY___M 0xFFFFFFFF +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TRIGGER_MESSAGE_BODY__MCI_CPU_INT_BODY___S 0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TRIGGER_MESSAGE_BODY___M 0xFFFFFFFF +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_TRIGGER_MESSAGE_BODY___S 0 + +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_CLKGATE_DISABLE (0x00A28044) +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_CLKGATE_DISABLE___RWC QCSR_REG_RW +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_CLKGATE_DISABLE___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_CLKGATE_DISABLE__VAL___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_CLKGATE_DISABLE__VAL___M 0x00000001 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_CLKGATE_DISABLE__VAL___S 0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_CLKGATE_DISABLE___M 0x00000001 +#define UMAC_CXC_SMH_REG_CXC_SMH_R0_CLKGATE_DISABLE___S 0 + +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS (0x00A29000) +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__GPM_SKIP_ERR_INT___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__CCU_ACCESS_ERR_INT___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__AHB_ERR_INT___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__TX_REMOTE_RESET_DONE_INT___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__TX_MCI_CPU_INT_DONE_INT___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__TX_MCI_GPM_DONE_INT___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__RX_MCI_GPM_FULL_ERR_INT___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__RX_MCI_GPM_INT___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__RX_MCI_RESET_INT___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__RX_MCI_CPU_INT___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__GPM_SKIP_ERR_INT___M 0x00000200 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__GPM_SKIP_ERR_INT___S 9 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__CCU_ACCESS_ERR_INT___M 0x00000100 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__CCU_ACCESS_ERR_INT___S 8 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__AHB_ERR_INT___M 0x00000080 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__AHB_ERR_INT___S 7 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__TX_REMOTE_RESET_DONE_INT___M 0x00000040 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__TX_REMOTE_RESET_DONE_INT___S 6 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__TX_MCI_CPU_INT_DONE_INT___M 0x00000020 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__TX_MCI_CPU_INT_DONE_INT___S 5 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__TX_MCI_GPM_DONE_INT___M 0x00000010 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__TX_MCI_GPM_DONE_INT___S 4 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__RX_MCI_GPM_FULL_ERR_INT___M 0x00000008 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__RX_MCI_GPM_FULL_ERR_INT___S 3 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__RX_MCI_GPM_INT___M 0x00000004 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__RX_MCI_GPM_INT___S 2 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__RX_MCI_RESET_INT___M 0x00000002 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__RX_MCI_RESET_INT___S 1 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__RX_MCI_CPU_INT___M 0x00000001 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS__RX_MCI_CPU_INT___S 0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS___M 0x000003FF +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_STATUS___S 0 + +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE (0x00A29004) +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE___RWC QCSR_REG_RW +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__GPM_SKIP_ERR_INT_EN___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__CCU_ACCESS_ERR_INT_EN___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__AHB_ERR_INT_EN___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__TX_REMOTE_RESET_DONE_INT_EN___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__TX_MCI_CPU_INT_DONE_INT_EN___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__TX_MCI_GPM_DONE_INT_EN___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__RX_MCI_GPM_FULL_ERR_INT_EN___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__RX_MCI_GPM_INT_EN___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__RX_MCI_RESET_INT_EN___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__RX_MCI_CPU_INT_EN___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__GPM_SKIP_ERR_INT_EN___M 0x00000200 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__GPM_SKIP_ERR_INT_EN___S 9 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__CCU_ACCESS_ERR_INT_EN___M 0x00000100 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__CCU_ACCESS_ERR_INT_EN___S 8 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__AHB_ERR_INT_EN___M 0x00000080 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__AHB_ERR_INT_EN___S 7 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__TX_REMOTE_RESET_DONE_INT_EN___M 0x00000040 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__TX_REMOTE_RESET_DONE_INT_EN___S 6 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__TX_MCI_CPU_INT_DONE_INT_EN___M 0x00000020 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__TX_MCI_CPU_INT_DONE_INT_EN___S 5 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__TX_MCI_GPM_DONE_INT_EN___M 0x00000010 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__TX_MCI_GPM_DONE_INT_EN___S 4 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__RX_MCI_GPM_FULL_ERR_INT_EN___M 0x00000008 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__RX_MCI_GPM_FULL_ERR_INT_EN___S 3 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__RX_MCI_GPM_INT_EN___M 0x00000004 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__RX_MCI_GPM_INT_EN___S 2 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__RX_MCI_RESET_INT_EN___M 0x00000002 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__RX_MCI_RESET_INT_EN___S 1 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__RX_MCI_CPU_INT_EN___M 0x00000001 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE__RX_MCI_CPU_INT_EN___S 0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE___M 0x000003FF +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_ENABLE___S 0 + +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR (0x00A29008) +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR___RWC QCSR_REG_RW +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__GPM_SKIP_ER_INT_CLR___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__CCU_ACCESS_ER_INT_CLR___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__AHB_ERR_INT_CLR___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__TX_REMOTE_RESET_DONE_INT_CLR___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__TX_MCI_CPU_INT_DONE_INT_CLR___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__TX_MCI_GPM_DONE_INT_CLR___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__RX_MCI_GPM_FULL_ERR_INT_CLR___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__RX_MCI_GPM_INT_CLR___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__RX_MCI_RESET_INT_CLR___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__RX_MCI_CPU_INT_CLR___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__GPM_SKIP_ER_INT_CLR___M 0x00000200 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__GPM_SKIP_ER_INT_CLR___S 9 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__CCU_ACCESS_ER_INT_CLR___M 0x00000100 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__CCU_ACCESS_ER_INT_CLR___S 8 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__AHB_ERR_INT_CLR___M 0x00000080 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__AHB_ERR_INT_CLR___S 7 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__TX_REMOTE_RESET_DONE_INT_CLR___M 0x00000040 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__TX_REMOTE_RESET_DONE_INT_CLR___S 6 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__TX_MCI_CPU_INT_DONE_INT_CLR___M 0x00000020 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__TX_MCI_CPU_INT_DONE_INT_CLR___S 5 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__TX_MCI_GPM_DONE_INT_CLR___M 0x00000010 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__TX_MCI_GPM_DONE_INT_CLR___S 4 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__RX_MCI_GPM_FULL_ERR_INT_CLR___M 0x00000008 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__RX_MCI_GPM_FULL_ERR_INT_CLR___S 3 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__RX_MCI_GPM_INT_CLR___M 0x00000004 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__RX_MCI_GPM_INT_CLR___S 2 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__RX_MCI_RESET_INT_CLR___M 0x00000002 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__RX_MCI_RESET_INT_CLR___S 1 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__RX_MCI_CPU_INT_CLR___M 0x00000001 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR__RX_MCI_CPU_INT_CLR___S 0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR___M 0x000003FF +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INT_CLEAR___S 0 + +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_GPM_TIMESTAMP (0x00A2900C) +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_GPM_TIMESTAMP___RWC QCSR_REG_RO +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_GPM_TIMESTAMP___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_GPM_TIMESTAMP__MCI_GPM_RX_TIMESTAMP___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_GPM_TIMESTAMP__MCI_GPM_RX_TIMESTAMP___M 0xFFFFFFFF +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_GPM_TIMESTAMP__MCI_GPM_RX_TIMESTAMP___S 0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_GPM_TIMESTAMP___M 0xFFFFFFFF +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_GPM_TIMESTAMP___S 0 + +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_CPU_INT_TIMESTAMP (0x00A29010) +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_CPU_INT_TIMESTAMP___RWC QCSR_REG_RO +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_CPU_INT_TIMESTAMP___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_CPU_INT_TIMESTAMP__MCI_CPU_INT_TIMESTAMP___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_CPU_INT_TIMESTAMP__MCI_CPU_INT_TIMESTAMP___M 0xFFFFFFFF +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_CPU_INT_TIMESTAMP__MCI_CPU_INT_TIMESTAMP___S 0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_CPU_INT_TIMESTAMP___M 0xFFFFFFFF +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_CPU_INT_TIMESTAMP___S 0 + +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_RESET_TIMESTAMP (0x00A29014) +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_RESET_TIMESTAMP___RWC QCSR_REG_RO +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_RESET_TIMESTAMP___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_RESET_TIMESTAMP__MCI_RESET_TIMESTAMP___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_RESET_TIMESTAMP__MCI_RESET_TIMESTAMP___M 0xFFFFFFFF +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_RESET_TIMESTAMP__MCI_RESET_TIMESTAMP___S 0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_RESET_TIMESTAMP___M 0xFFFFFFFF +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_RX_MCI_RESET_TIMESTAMP___S 0 + +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_GAMX_AHB_ERR_ADDR (0x00A29018) +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_GAMX_AHB_ERR_ADDR___RWC QCSR_REG_RO +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_GAMX_AHB_ERR_ADDR___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_GAMX_AHB_ERR_ADDR__AHB_ERR_ADDRESS___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_GAMX_AHB_ERR_ADDR__AHB_ERR_ADDRESS___M 0xFFFFFFFF +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_GAMX_AHB_ERR_ADDR__AHB_ERR_ADDRESS___S 0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_GAMX_AHB_ERR_ADDR___M 0xFFFFFFFF +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_GAMX_AHB_ERR_ADDR___S 0 + +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INVALID_APB_ACC_ADR (0x00A2901C) +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INVALID_APB_ACC_ADR___RWC QCSR_REG_RW +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INVALID_APB_ACC_ADR___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INVALID_APB_ACC_ADR__ERR_TYPE___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INVALID_APB_ACC_ADR__ERR_ADDR___POR 0x00000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INVALID_APB_ACC_ADR__ERR_TYPE___M 0x00060000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INVALID_APB_ACC_ADR__ERR_TYPE___S 17 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INVALID_APB_ACC_ADR__ERR_ADDR___M 0x0001FFFF +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INVALID_APB_ACC_ADR__ERR_ADDR___S 0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INVALID_APB_ACC_ADR___M 0x0007FFFF +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_INVALID_APB_ACC_ADR___S 0 + +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_DEBUG_STATES (0x00A29020) +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_DEBUG_STATES___RWC QCSR_REG_RO +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_DEBUG_STATES___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_DEBUG_STATES__STATE_INFO___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_DEBUG_STATES__STATE_INFO___M 0xFFFFFFFF +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_DEBUG_STATES__STATE_INFO___S 0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_DEBUG_STATES___M 0xFFFFFFFF +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_DEBUG_STATES___S 0 + +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TESTBUS_CTRL (0x00A29024) +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TESTBUS_CTRL___RWC QCSR_REG_RW +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TESTBUS_CTRL___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TESTBUS_CTRL__SPR___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TESTBUS_CTRL__SPR2___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TESTBUS_CTRL__TESTBUS_SELECT___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TESTBUS_CTRL__SPR___M 0xF0000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TESTBUS_CTRL__SPR___S 28 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TESTBUS_CTRL__SPR2___M 0x01000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TESTBUS_CTRL__SPR2___S 24 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TESTBUS_CTRL__TESTBUS_SELECT___M 0x0000000F +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TESTBUS_CTRL__TESTBUS_SELECT___S 0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TESTBUS_CTRL___M 0xF100000F +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TESTBUS_CTRL___S 0 + +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS (0x00A29028) +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS___RWC QCSR_REG_RO +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__GPM_SKIP_ERR_EVENT___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__CCU_ACCESS_ERR_EVENT___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__AHB_ERR_EVENT___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__TX_REMOTE_RESET_DONE_EVENT___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__TX_MCI_CPU_INT_DONE_EVENT___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__TX_MCI_GPM_DONE_EVENT___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__RX_MCI_GPM_FULL_ERR_EVENT___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__RX_MCI_GPM_EVENT___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__RX_MCI_RESET_EVENT___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__RX_MCI_CPU_EVENT___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__GPM_SKIP_ERR_EVENT___M 0x00000200 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__GPM_SKIP_ERR_EVENT___S 9 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__CCU_ACCESS_ERR_EVENT___M 0x00000100 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__CCU_ACCESS_ERR_EVENT___S 8 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__AHB_ERR_EVENT___M 0x00000080 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__AHB_ERR_EVENT___S 7 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__TX_REMOTE_RESET_DONE_EVENT___M 0x00000040 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__TX_REMOTE_RESET_DONE_EVENT___S 6 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__TX_MCI_CPU_INT_DONE_EVENT___M 0x00000020 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__TX_MCI_CPU_INT_DONE_EVENT___S 5 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__TX_MCI_GPM_DONE_EVENT___M 0x00000010 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__TX_MCI_GPM_DONE_EVENT___S 4 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__RX_MCI_GPM_FULL_ERR_EVENT___M 0x00000008 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__RX_MCI_GPM_FULL_ERR_EVENT___S 3 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__RX_MCI_GPM_EVENT___M 0x00000004 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__RX_MCI_GPM_EVENT___S 2 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__RX_MCI_RESET_EVENT___M 0x00000002 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__RX_MCI_RESET_EVENT___S 1 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__RX_MCI_CPU_EVENT___M 0x00000001 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS__RX_MCI_CPU_EVENT___S 0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS___M 0x000003FF +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_STATUS___S 0 + +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE (0x00A2902C) +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE___RWC QCSR_REG_RW +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__GPM_SKIP_ERR_EVENT_EN___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__CCU_ACCESS_ERR_EVENT_EN___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__AHB_ERR_EVENT_EN___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__TX_REMOTE_RESET_DONE_EVENT_EN___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__TX_MCI_CPU_INT_DONE_EVENT_EN___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__TX_MCI_GPM_DONE_EVENT_EN___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__RX_MCI_GPM_FULL_ERR_EVENT_EN___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__RX_MCI_GPM_EVENT_EN___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__RX_MCI_RESET_EVENT_EN___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__RX_MCI_CPU_EVENT_EN___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__GPM_SKIP_ERR_EVENT_EN___M 0x00000200 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__GPM_SKIP_ERR_EVENT_EN___S 9 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__CCU_ACCESS_ERR_EVENT_EN___M 0x00000100 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__CCU_ACCESS_ERR_EVENT_EN___S 8 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__AHB_ERR_EVENT_EN___M 0x00000080 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__AHB_ERR_EVENT_EN___S 7 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__TX_REMOTE_RESET_DONE_EVENT_EN___M 0x00000040 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__TX_REMOTE_RESET_DONE_EVENT_EN___S 6 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__TX_MCI_CPU_INT_DONE_EVENT_EN___M 0x00000020 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__TX_MCI_CPU_INT_DONE_EVENT_EN___S 5 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__TX_MCI_GPM_DONE_EVENT_EN___M 0x00000010 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__TX_MCI_GPM_DONE_EVENT_EN___S 4 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__RX_MCI_GPM_FULL_ERR_EVENT_EN___M 0x00000008 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__RX_MCI_GPM_FULL_ERR_EVENT_EN___S 3 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__RX_MCI_GPM_EVENT_EN___M 0x00000004 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__RX_MCI_GPM_EVENT_EN___S 2 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__RX_MCI_RESET_EVENT_EN___M 0x00000002 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__RX_MCI_RESET_EVENT_EN___S 1 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__RX_MCI_CPU_EVENT_EN___M 0x00000001 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE__RX_MCI_CPU_EVENT_EN___S 0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE___M 0x000003FF +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_ENABLE___S 0 + +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR (0x00A29030) +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR___RWC QCSR_REG_RW +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR___POR 0x00000000 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__GPM_SKIP_ER_EVENT_CLR___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__CCU_ACCESS_ER_EVENT_CLR___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__AHB_ERR_EVENT_CLR___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__TX_REMOTE_RESET_DONE_EVENT_CLR___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__TX_MCI_CPU_INT_DONE_EVENT_CLR___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__TX_MCI_GPM_DONE_EVENT_CLR___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__RX_MCI_GPM_FULL_ERR_EVENT_CLR___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__RX_MCI_GPM_EVENT_CLR___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__RX_MCI_RESET_EVENT_CLR___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__RX_MCI_CPU_EVENT_CLR___POR 0x0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__GPM_SKIP_ER_EVENT_CLR___M 0x00000200 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__GPM_SKIP_ER_EVENT_CLR___S 9 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__CCU_ACCESS_ER_EVENT_CLR___M 0x00000100 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__CCU_ACCESS_ER_EVENT_CLR___S 8 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__AHB_ERR_EVENT_CLR___M 0x00000080 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__AHB_ERR_EVENT_CLR___S 7 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__TX_REMOTE_RESET_DONE_EVENT_CLR___M 0x00000040 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__TX_REMOTE_RESET_DONE_EVENT_CLR___S 6 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__TX_MCI_CPU_INT_DONE_EVENT_CLR___M 0x00000020 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__TX_MCI_CPU_INT_DONE_EVENT_CLR___S 5 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__TX_MCI_GPM_DONE_EVENT_CLR___M 0x00000010 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__TX_MCI_GPM_DONE_EVENT_CLR___S 4 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__RX_MCI_GPM_FULL_ERR_EVENT_CLR___M 0x00000008 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__RX_MCI_GPM_FULL_ERR_EVENT_CLR___S 3 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__RX_MCI_GPM_EVENT_CLR___M 0x00000004 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__RX_MCI_GPM_EVENT_CLR___S 2 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__RX_MCI_RESET_EVENT_CLR___M 0x00000002 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__RX_MCI_RESET_EVENT_CLR___S 1 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__RX_MCI_CPU_EVENT_CLR___M 0x00000001 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR__RX_MCI_CPU_EVENT_CLR___S 0 +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR___M 0x000003FF +#define UMAC_CXC_SMH_REG_CXC_SMH_R1_TRC_CTRL_CLR___S 0 + +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL (0x00A2A000) +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL___RWC QCSR_REG_RW +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL___POR 0x00000000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_RESULT_WLAN2___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_STATUS_WLAN2___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_RESULT_WLAN1___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_STATUS_WLAN1___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__BT_RESPONSE_TIMEOUT_WLAN2___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__BT_RESPONSE_TIMEOUT_WLAN1___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__SW_ACTIVATE_MCIB___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_SMH_WLAN2___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_LTE_WLAN2___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_LNA_WLAN2___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_BT_WLAN2___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_WSI_SYNC_WLAN2___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_POWERUP_SEQUENCE_WLAN2___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_SMH_WLAN1___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_LTE_WLAN1___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_LNA_WLAN1___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_BT_WLAN1___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_WSI_SYNC_WLAN1___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_POWERUP_SEQUENCE_WLAN1___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_RESULT_WLAN2___M 0xE0000000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_RESULT_WLAN2___S 29 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_STATUS_WLAN2___M 0x10000000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_STATUS_WLAN2___S 28 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_RESULT_WLAN1___M 0x0E000000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_RESULT_WLAN1___S 25 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_STATUS_WLAN1___M 0x01000000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_STATUS_WLAN1___S 24 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__BT_RESPONSE_TIMEOUT_WLAN2___M 0x00800000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__BT_RESPONSE_TIMEOUT_WLAN2___S 23 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__BT_RESPONSE_TIMEOUT_WLAN1___M 0x00400000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__BT_RESPONSE_TIMEOUT_WLAN1___S 22 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__SW_ACTIVATE_MCIB___M 0x00001000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__SW_ACTIVATE_MCIB___S 12 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_SMH_WLAN2___M 0x00000800 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_SMH_WLAN2___S 11 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_LTE_WLAN2___M 0x00000400 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_LTE_WLAN2___S 10 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_LNA_WLAN2___M 0x00000200 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_LNA_WLAN2___S 9 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_BT_WLAN2___M 0x00000100 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_BT_WLAN2___S 8 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_WSI_SYNC_WLAN2___M 0x00000080 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_WSI_SYNC_WLAN2___S 7 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_POWERUP_SEQUENCE_WLAN2___M 0x00000040 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_POWERUP_SEQUENCE_WLAN2___S 6 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_SMH_WLAN1___M 0x00000020 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_SMH_WLAN1___S 5 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_LTE_WLAN1___M 0x00000010 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_LTE_WLAN1___S 4 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_LNA_WLAN1___M 0x00000008 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_LNA_WLAN1___S 3 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_BT_WLAN1___M 0x00000004 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_BT_WLAN1___S 2 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_WSI_SYNC_WLAN1___M 0x00000002 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__POWERUP_WITH_WSI_SYNC_WLAN1___S 1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_POWERUP_SEQUENCE_WLAN1___M 0x00000001 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL__INIT_POWERUP_SEQUENCE_WLAN1___S 0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL___M 0xFFC01FFF +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL___S 0 + +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR (0x00A2A004) +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR___RWC QCSR_REG_RW +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR___POR 0x00000026 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__BT_OFF_OVERWRITE_VALUE___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__BT_OFF_OVERWRITE___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__PMH_MCI_BT_OFF___POR 0x1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__BT_POWERED_DOWN_OVERWRITE_VALUE___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__BT_POWERED_DOWN_OVERWRITE___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__PMH_BMH_BT_POWERED_DOWN___POR 0x1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__PMH_SMH_BT_POWERED_DOWN___POR 0x1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__CURRENT_BT_PWR_STATE___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__BT_OFF_OVERWRITE_VALUE___M 0x00000080 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__BT_OFF_OVERWRITE_VALUE___S 7 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__BT_OFF_OVERWRITE___M 0x00000040 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__BT_OFF_OVERWRITE___S 6 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__PMH_MCI_BT_OFF___M 0x00000020 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__PMH_MCI_BT_OFF___S 5 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__BT_POWERED_DOWN_OVERWRITE_VALUE___M 0x00000010 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__BT_POWERED_DOWN_OVERWRITE_VALUE___S 4 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__BT_POWERED_DOWN_OVERWRITE___M 0x00000008 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__BT_POWERED_DOWN_OVERWRITE___S 3 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__PMH_BMH_BT_POWERED_DOWN___M 0x00000004 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__PMH_BMH_BT_POWERED_DOWN___S 2 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__PMH_SMH_BT_POWERED_DOWN___M 0x00000002 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__PMH_SMH_BT_POWERED_DOWN___S 1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__CURRENT_BT_PWR_STATE___M 0x00000001 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR__CURRENT_BT_PWR_STATE___S 0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR___M 0x000000FF +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_PWR_STATE_CTLR___S 0 + +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_RESPONSE_TIMEOUT (0x00A2A008) +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_RESPONSE_TIMEOUT___RWC QCSR_REG_RW +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_RESPONSE_TIMEOUT___POR 0x0000000F +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_RESPONSE_TIMEOUT__MAX_TIMEOUT___POR 0x0F +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_RESPONSE_TIMEOUT__MAX_TIMEOUT___M 0x000000FF +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_RESPONSE_TIMEOUT__MAX_TIMEOUT___S 0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_RESPONSE_TIMEOUT___M 0x000000FF +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_BT_RESPONSE_TIMEOUT___S 0 + +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL (0x00A2A00C) +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL___RWC QCSR_REG_RW +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL___POR 0x040008FC +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__DISABLE_SYS_SLEEPING_PWR_DOWN___POR 0x1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_RESULT_WLAN2___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_WLAN2_DONE___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_STATUS_WLAN2___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__PMU_PWR_DOWN_STATUS_WLAN2___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_RESULT_WLAN1___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_WLAN1_DONE___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_STATUS_WLAN1___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__PMU_PWR_DOWN_STATUS_WLAN1___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__MCIM_SHUTDOWN_DELAY___POR 0x08 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__LCMH_BLOCK_RTSM___POR 0x1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__LCMH_BLOCK_TDM___POR 0x1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__LMH_BLOCK_LNA_TAKE___POR 0x1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SMH_BLOCK_GPM___POR 0x1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__ALLOW_PMU_WLAN2_INITIATED_PWR_DOWN___POR 0x1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__ALLOW_PMU_WLAN1_INITIATED_PWR_DOWN___POR 0x1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__INIT_SW_WLAN2_PWR_DOWN_SEQUENCE___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__INIT_SW_WLAN1_PWR_DOWN_SEQUENCE___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__DISABLE_SYS_SLEEPING_PWR_DOWN___M 0x04000000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__DISABLE_SYS_SLEEPING_PWR_DOWN___S 26 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_RESULT_WLAN2___M 0x03800000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_RESULT_WLAN2___S 23 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_WLAN2_DONE___M 0x00400000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_WLAN2_DONE___S 22 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_STATUS_WLAN2___M 0x00200000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_STATUS_WLAN2___S 21 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__PMU_PWR_DOWN_STATUS_WLAN2___M 0x00100000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__PMU_PWR_DOWN_STATUS_WLAN2___S 20 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_RESULT_WLAN1___M 0x000E0000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_RESULT_WLAN1___S 17 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_WLAN1_DONE___M 0x00010000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_WLAN1_DONE___S 16 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_STATUS_WLAN1___M 0x00008000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SW_PWR_DOWN_STATUS_WLAN1___S 15 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__PMU_PWR_DOWN_STATUS_WLAN1___M 0x00004000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__PMU_PWR_DOWN_STATUS_WLAN1___S 14 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__MCIM_SHUTDOWN_DELAY___M 0x00003F00 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__MCIM_SHUTDOWN_DELAY___S 8 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__LCMH_BLOCK_RTSM___M 0x00000080 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__LCMH_BLOCK_RTSM___S 7 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__LCMH_BLOCK_TDM___M 0x00000040 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__LCMH_BLOCK_TDM___S 6 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__LMH_BLOCK_LNA_TAKE___M 0x00000020 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__LMH_BLOCK_LNA_TAKE___S 5 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SMH_BLOCK_GPM___M 0x00000010 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__SMH_BLOCK_GPM___S 4 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__ALLOW_PMU_WLAN2_INITIATED_PWR_DOWN___M 0x00000008 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__ALLOW_PMU_WLAN2_INITIATED_PWR_DOWN___S 3 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__ALLOW_PMU_WLAN1_INITIATED_PWR_DOWN___M 0x00000004 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__ALLOW_PMU_WLAN1_INITIATED_PWR_DOWN___S 2 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__INIT_SW_WLAN2_PWR_DOWN_SEQUENCE___M 0x00000002 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__INIT_SW_WLAN2_PWR_DOWN_SEQUENCE___S 1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__INIT_SW_WLAN1_PWR_DOWN_SEQUENCE___M 0x00000001 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL__INIT_SW_WLAN1_PWR_DOWN_SEQUENCE___S 0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL___M 0x07FFFFFF +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL___S 0 + +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS (0x00A2A010) +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS___RWC QCSR_REG_RO +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS___POR 0x000003FF +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__SMH_SHUTDOWN_ACK___POR 0x1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__BMH_SHUTDOWN_ACK___POR 0x1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__LMH_SHUTDOWN_ACK___POR 0x1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__LCMH_SHUTDOWN_ACK___POR 0x1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__MCIB_SHUTDOWN_ACK___POR 0x1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__PMH_SMH_SHUTDOWN___POR 0x1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__PMH_BMH_SHUTDOWN___POR 0x1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__PMH_LMH_SHUTDOWN___POR 0x1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__PMH_LCMH_SHUTDOWN___POR 0x1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__PMH_MCIB_SHUTDOWN___POR 0x1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__SMH_SHUTDOWN_ACK___M 0x00000200 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__SMH_SHUTDOWN_ACK___S 9 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__BMH_SHUTDOWN_ACK___M 0x00000100 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__BMH_SHUTDOWN_ACK___S 8 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__LMH_SHUTDOWN_ACK___M 0x00000080 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__LMH_SHUTDOWN_ACK___S 7 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__LCMH_SHUTDOWN_ACK___M 0x00000040 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__LCMH_SHUTDOWN_ACK___S 6 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__MCIB_SHUTDOWN_ACK___M 0x00000020 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__MCIB_SHUTDOWN_ACK___S 5 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__PMH_SMH_SHUTDOWN___M 0x00000010 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__PMH_SMH_SHUTDOWN___S 4 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__PMH_BMH_SHUTDOWN___M 0x00000008 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__PMH_BMH_SHUTDOWN___S 3 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__PMH_LMH_SHUTDOWN___M 0x00000004 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__PMH_LMH_SHUTDOWN___S 2 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__PMH_LCMH_SHUTDOWN___M 0x00000002 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__PMH_LCMH_SHUTDOWN___S 1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__PMH_MCIB_SHUTDOWN___M 0x00000001 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS__PMH_MCIB_SHUTDOWN___S 0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS___M 0x000003FF +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_SHUTDOWN_STATUS___S 0 + +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_TIMEOUT (0x00A2A014) +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_TIMEOUT___RWC QCSR_REG_RW +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_TIMEOUT___POR 0x00000038 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_TIMEOUT__TIMEOUT___POR 0x38 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_TIMEOUT__TIMEOUT___M 0x000000FF +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_TIMEOUT__TIMEOUT___S 0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_TIMEOUT___M 0x000000FF +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_TIMEOUT___S 0 + +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_MCI_CMD_GEN_CTRL (0x00A2A018) +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_MCI_CMD_GEN_CTRL___RWC QCSR_REG_RW +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_MCI_CMD_GEN_CTRL___POR 0x00000000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_MCI_CMD_GEN_CTRL__SEND_MCI_SYS_WAKING_ONGOING___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_MCI_CMD_GEN_CTRL__SEND_MCI_SYS_SLEEPING_ONGOING___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_MCI_CMD_GEN_CTRL__SEND_MCI_SYS_SLEEPING___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_MCI_CMD_GEN_CTRL__SEND_MCI_SYS_WAKING___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_MCI_CMD_GEN_CTRL__SEND_MCI_SYS_WAKING_ONGOING___M 0x80000000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_MCI_CMD_GEN_CTRL__SEND_MCI_SYS_WAKING_ONGOING___S 31 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_MCI_CMD_GEN_CTRL__SEND_MCI_SYS_SLEEPING_ONGOING___M 0x40000000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_MCI_CMD_GEN_CTRL__SEND_MCI_SYS_SLEEPING_ONGOING___S 30 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_MCI_CMD_GEN_CTRL__SEND_MCI_SYS_SLEEPING___M 0x00000002 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_MCI_CMD_GEN_CTRL__SEND_MCI_SYS_SLEEPING___S 1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_MCI_CMD_GEN_CTRL__SEND_MCI_SYS_WAKING___M 0x00000001 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_MCI_CMD_GEN_CTRL__SEND_MCI_SYS_WAKING___S 0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_MCI_CMD_GEN_CTRL___M 0xC0000003 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_MCI_CMD_GEN_CTRL___S 0 + +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS (0x00A2A01C) +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS___RWC QCSR_REG_RO +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS___POR 0x00000000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMU_PMH_WLAN3_SLEEP_ANNOUNCEMENT___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN3_SLEEP_ACK___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN3_SLEEP_ACK_RESULT___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN3_COEX_INIT_RESULT___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN3_COEX_INIT_DONE___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMU_PMH_WLAN1_SLEEP_ANNOUNCEMENT___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN1_SLEEP_ACK___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN1_SLEEP_ACK_RESULT___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMU_PMH_WLAN2_SLEEP_ANNOUNCEMENT___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN2_SLEEP_ACK___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN2_SLEEP_ACK_RESULT___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN1_COEX_INIT_RESULT___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN1_COEX_INIT_DONE___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN2_COEX_INIT_RESULT___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN2_COEX_INIT_DONE___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMU_PMH_WLAN3_SLEEP_ANNOUNCEMENT___M 0x04000000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMU_PMH_WLAN3_SLEEP_ANNOUNCEMENT___S 26 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN3_SLEEP_ACK___M 0x02000000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN3_SLEEP_ACK___S 25 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN3_SLEEP_ACK_RESULT___M 0x01C00000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN3_SLEEP_ACK_RESULT___S 22 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN3_COEX_INIT_RESULT___M 0x00380000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN3_COEX_INIT_RESULT___S 19 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN3_COEX_INIT_DONE___M 0x00040000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN3_COEX_INIT_DONE___S 18 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMU_PMH_WLAN1_SLEEP_ANNOUNCEMENT___M 0x00020000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMU_PMH_WLAN1_SLEEP_ANNOUNCEMENT___S 17 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN1_SLEEP_ACK___M 0x00010000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN1_SLEEP_ACK___S 16 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN1_SLEEP_ACK_RESULT___M 0x0000E000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN1_SLEEP_ACK_RESULT___S 13 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMU_PMH_WLAN2_SLEEP_ANNOUNCEMENT___M 0x00001000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMU_PMH_WLAN2_SLEEP_ANNOUNCEMENT___S 12 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN2_SLEEP_ACK___M 0x00000800 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN2_SLEEP_ACK___S 11 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN2_SLEEP_ACK_RESULT___M 0x00000700 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN2_SLEEP_ACK_RESULT___S 8 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN1_COEX_INIT_RESULT___M 0x000000E0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN1_COEX_INIT_RESULT___S 5 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN1_COEX_INIT_DONE___M 0x00000010 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN1_COEX_INIT_DONE___S 4 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN2_COEX_INIT_RESULT___M 0x0000000E +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN2_COEX_INIT_RESULT___S 1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN2_COEX_INIT_DONE___M 0x00000001 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS__PMH_PMU_WLAN2_COEX_INIT_DONE___S 0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS___M 0x07FFFFFF +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_PMU_PMH_SIGNAL_STATUS___S 0 + +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_CLKGATE_DISABLE (0x00A2A020) +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_CLKGATE_DISABLE___RWC QCSR_REG_RW +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_CLKGATE_DISABLE___POR 0x00000000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_CLKGATE_DISABLE__VAL___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_CLKGATE_DISABLE__VAL___M 0x00000001 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_CLKGATE_DISABLE__VAL___S 0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_CLKGATE_DISABLE___M 0x00000001 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_CLKGATE_DISABLE___S 0 + +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2 (0x00A2A024) +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2___RWC QCSR_REG_RW +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2___POR 0x00000000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__INIT_RESULT_WLAN3___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__INIT_STATUS_WLAN3___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__BT_RESPONSE_TIMEOUT_WLAN3___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__POWERUP_WITH_SMH_WLAN3___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__POWERUP_WITH_LTE_WLAN3___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__POWERUP_WITH_LNA_WLAN3___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__POWERUP_WITH_BT_WLAN3___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__POWERUP_WITH_WSI_SYNC_WLAN3___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__INIT_POWERUP_SEQUENCE_WLAN3___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__INIT_RESULT_WLAN3___M 0x00000700 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__INIT_RESULT_WLAN3___S 8 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__INIT_STATUS_WLAN3___M 0x00000080 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__INIT_STATUS_WLAN3___S 7 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__BT_RESPONSE_TIMEOUT_WLAN3___M 0x00000040 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__BT_RESPONSE_TIMEOUT_WLAN3___S 6 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__POWERUP_WITH_SMH_WLAN3___M 0x00000020 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__POWERUP_WITH_SMH_WLAN3___S 5 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__POWERUP_WITH_LTE_WLAN3___M 0x00000010 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__POWERUP_WITH_LTE_WLAN3___S 4 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__POWERUP_WITH_LNA_WLAN3___M 0x00000008 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__POWERUP_WITH_LNA_WLAN3___S 3 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__POWERUP_WITH_BT_WLAN3___M 0x00000004 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__POWERUP_WITH_BT_WLAN3___S 2 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__POWERUP_WITH_WSI_SYNC_WLAN3___M 0x00000002 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__POWERUP_WITH_WSI_SYNC_WLAN3___S 1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__INIT_POWERUP_SEQUENCE_WLAN3___M 0x00000001 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2__INIT_POWERUP_SEQUENCE_WLAN3___S 0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2___M 0x000007FF +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERUP_CTRL2___S 0 + +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2 (0x00A2A028) +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2___RWC QCSR_REG_RW +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2___POR 0x00000002 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__SW_PWR_DOWN_RESULT_WLAN3___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__SW_PWR_DOWN_WLAN3_DONE___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__SW_PWR_DOWN_STATUS_WLAN3___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__PMU_PWR_DOWN_STATUS_WLAN3___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__ALLOW_PMU_WLAN3_INITIATED_PWR_DOWN___POR 0x1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__INIT_SW_WLAN3_PWR_DOWN_SEQUENCE___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__SW_PWR_DOWN_RESULT_WLAN3___M 0x000000E0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__SW_PWR_DOWN_RESULT_WLAN3___S 5 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__SW_PWR_DOWN_WLAN3_DONE___M 0x00000010 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__SW_PWR_DOWN_WLAN3_DONE___S 4 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__SW_PWR_DOWN_STATUS_WLAN3___M 0x00000008 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__SW_PWR_DOWN_STATUS_WLAN3___S 3 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__PMU_PWR_DOWN_STATUS_WLAN3___M 0x00000004 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__PMU_PWR_DOWN_STATUS_WLAN3___S 2 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__ALLOW_PMU_WLAN3_INITIATED_PWR_DOWN___M 0x00000002 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__ALLOW_PMU_WLAN3_INITIATED_PWR_DOWN___S 1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__INIT_SW_WLAN3_PWR_DOWN_SEQUENCE___M 0x00000001 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2__INIT_SW_WLAN3_PWR_DOWN_SEQUENCE___S 0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2___M 0x000000FF +#define UMAC_CXC_PMH_REG_CXC_PMH_R0_POWERDOWN_CTRL2___S 0 + +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS (0x00A2B000) +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS___POR 0x00000000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__PMU_WLAN3_PWR_DWN_DONE_INT___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__SW_WLAN3_PWR_DWN_DONE_INT___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__CCU_ACCESS_ERR_INT___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__WSI_BUS_SYNC_INT___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__BT_RESPONSE_TIMEOUT_INT___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__PWR_DOWN_TIMEOUT_INT___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__PMU_WLAN2_PWR_DWN_DONE_INT___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__PMU_WLAN1_PWR_DWN_DONE_INT___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__SW_WLAN2_PWR_DWN_DONE_INT___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__SW_WLAN1_PWR_DWN_DONE_INT___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__BT_SYS_SLEEPING_INT___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__BT_SYS_WAKING_INT___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__PMU_WLAN3_PWR_DWN_DONE_INT___M 0x00000800 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__PMU_WLAN3_PWR_DWN_DONE_INT___S 11 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__SW_WLAN3_PWR_DWN_DONE_INT___M 0x00000400 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__SW_WLAN3_PWR_DWN_DONE_INT___S 10 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__CCU_ACCESS_ERR_INT___M 0x00000200 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__CCU_ACCESS_ERR_INT___S 9 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__WSI_BUS_SYNC_INT___M 0x00000100 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__WSI_BUS_SYNC_INT___S 8 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__BT_RESPONSE_TIMEOUT_INT___M 0x00000080 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__BT_RESPONSE_TIMEOUT_INT___S 7 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__PWR_DOWN_TIMEOUT_INT___M 0x00000040 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__PWR_DOWN_TIMEOUT_INT___S 6 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__PMU_WLAN2_PWR_DWN_DONE_INT___M 0x00000020 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__PMU_WLAN2_PWR_DWN_DONE_INT___S 5 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__PMU_WLAN1_PWR_DWN_DONE_INT___M 0x00000010 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__PMU_WLAN1_PWR_DWN_DONE_INT___S 4 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__SW_WLAN2_PWR_DWN_DONE_INT___M 0x00000008 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__SW_WLAN2_PWR_DWN_DONE_INT___S 3 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__SW_WLAN1_PWR_DWN_DONE_INT___M 0x00000004 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__SW_WLAN1_PWR_DWN_DONE_INT___S 2 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__BT_SYS_SLEEPING_INT___M 0x00000002 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__BT_SYS_SLEEPING_INT___S 1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__BT_SYS_WAKING_INT___M 0x00000001 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS__BT_SYS_WAKING_INT___S 0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS___M 0x00000FFF +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_STATUS___S 0 + +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE (0x00A2B004) +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE___RWC QCSR_REG_RW +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE___POR 0x00000000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__PMU_WLAN3_PWR_DWN_DONE_INT_EN___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__SW_WLAN3_PWR_DWN_DONE_INT_EN___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__CCU_ACCESS_ERR_INT_EN___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__WSI_BUS_SYNC_INT_EN___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__BT_RESPONSE_TIMEOUT_INT_EN___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__PWR_DOWN_TIMEOUT_INT_EN___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__PMU_WLAN2_PWR_DWN_DONE_INT_EN___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__PMU_WLAN1_PWR_DWN_DONE_INT_EN___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__SW_WLAN2_PWR_DWN_DONE_INT_EN___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__SW_WLAN1_PWR_DWN_DONE_INT_EN___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__BT_SYS_SLEEPING_INT_EN___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__BT_SYS_WAKING_INT_EN___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__PMU_WLAN3_PWR_DWN_DONE_INT_EN___M 0x00000800 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__PMU_WLAN3_PWR_DWN_DONE_INT_EN___S 11 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__SW_WLAN3_PWR_DWN_DONE_INT_EN___M 0x00000400 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__SW_WLAN3_PWR_DWN_DONE_INT_EN___S 10 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__CCU_ACCESS_ERR_INT_EN___M 0x00000200 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__CCU_ACCESS_ERR_INT_EN___S 9 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__WSI_BUS_SYNC_INT_EN___M 0x00000100 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__WSI_BUS_SYNC_INT_EN___S 8 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__BT_RESPONSE_TIMEOUT_INT_EN___M 0x00000080 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__BT_RESPONSE_TIMEOUT_INT_EN___S 7 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__PWR_DOWN_TIMEOUT_INT_EN___M 0x00000040 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__PWR_DOWN_TIMEOUT_INT_EN___S 6 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__PMU_WLAN2_PWR_DWN_DONE_INT_EN___M 0x00000020 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__PMU_WLAN2_PWR_DWN_DONE_INT_EN___S 5 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__PMU_WLAN1_PWR_DWN_DONE_INT_EN___M 0x00000010 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__PMU_WLAN1_PWR_DWN_DONE_INT_EN___S 4 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__SW_WLAN2_PWR_DWN_DONE_INT_EN___M 0x00000008 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__SW_WLAN2_PWR_DWN_DONE_INT_EN___S 3 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__SW_WLAN1_PWR_DWN_DONE_INT_EN___M 0x00000004 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__SW_WLAN1_PWR_DWN_DONE_INT_EN___S 2 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__BT_SYS_SLEEPING_INT_EN___M 0x00000002 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__BT_SYS_SLEEPING_INT_EN___S 1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__BT_SYS_WAKING_INT_EN___M 0x00000001 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE__BT_SYS_WAKING_INT_EN___S 0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE___M 0x00000FFF +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_ENABLE___S 0 + +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR (0x00A2B008) +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR___RWC QCSR_REG_RW +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR___POR 0x00000000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__PMU_WLAN3_PWR_DWN_DONE_INT_CLR___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__SW_WLAN3_PWR_DWN_DONE_INT_CLR___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__CCU_ACCESS_ERR_INT_CLR___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__WSI_BUS_SYNC_INT_CLR___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__BT_RESPONSE_TIMEOUT_INT_CLR___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__PWR_DOWN_TIMEOUT_INT_CLR___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__PMU_WLAN2_PWR_DWN_DONE_INT_CLR___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__PMU_WLAN1_PWR_DWN_DONE_INT_CLR___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__SW_WLAN2_PWR_DWN_DONE_INT_CLR___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__SW_WLAN1_PWR_DWN_DONE_INT_CLR___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__BT_SYS_SLEEPING_INT_CLR___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__BT_SYS_WAKING_INT_CLR___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__PMU_WLAN3_PWR_DWN_DONE_INT_CLR___M 0x00000800 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__PMU_WLAN3_PWR_DWN_DONE_INT_CLR___S 11 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__SW_WLAN3_PWR_DWN_DONE_INT_CLR___M 0x00000400 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__SW_WLAN3_PWR_DWN_DONE_INT_CLR___S 10 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__CCU_ACCESS_ERR_INT_CLR___M 0x00000200 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__CCU_ACCESS_ERR_INT_CLR___S 9 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__WSI_BUS_SYNC_INT_CLR___M 0x00000100 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__WSI_BUS_SYNC_INT_CLR___S 8 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__BT_RESPONSE_TIMEOUT_INT_CLR___M 0x00000080 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__BT_RESPONSE_TIMEOUT_INT_CLR___S 7 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__PWR_DOWN_TIMEOUT_INT_CLR___M 0x00000040 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__PWR_DOWN_TIMEOUT_INT_CLR___S 6 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__PMU_WLAN2_PWR_DWN_DONE_INT_CLR___M 0x00000020 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__PMU_WLAN2_PWR_DWN_DONE_INT_CLR___S 5 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__PMU_WLAN1_PWR_DWN_DONE_INT_CLR___M 0x00000010 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__PMU_WLAN1_PWR_DWN_DONE_INT_CLR___S 4 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__SW_WLAN2_PWR_DWN_DONE_INT_CLR___M 0x00000008 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__SW_WLAN2_PWR_DWN_DONE_INT_CLR___S 3 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__SW_WLAN1_PWR_DWN_DONE_INT_CLR___M 0x00000004 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__SW_WLAN1_PWR_DWN_DONE_INT_CLR___S 2 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__BT_SYS_SLEEPING_INT_CLR___M 0x00000002 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__BT_SYS_SLEEPING_INT_CLR___S 1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__BT_SYS_WAKING_INT_CLR___M 0x00000001 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR__BT_SYS_WAKING_INT_CLR___S 0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR___M 0x00000FFF +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INT_CLR___S 0 + +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_RX_MCI_SYS_SLEEPING_TIMESTAMP (0x00A2B00C) +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_RX_MCI_SYS_SLEEPING_TIMESTAMP___RWC QCSR_REG_RO +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_RX_MCI_SYS_SLEEPING_TIMESTAMP___POR 0x00000000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_RX_MCI_SYS_SLEEPING_TIMESTAMP__TIMESTAMP___POR 0x00000000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_RX_MCI_SYS_SLEEPING_TIMESTAMP__TIMESTAMP___M 0xFFFFFFFF +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_RX_MCI_SYS_SLEEPING_TIMESTAMP__TIMESTAMP___S 0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_RX_MCI_SYS_SLEEPING_TIMESTAMP___M 0xFFFFFFFF +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_RX_MCI_SYS_SLEEPING_TIMESTAMP___S 0 + +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_RX_MCI_SYS_WAKING_TIMESTAMP (0x00A2B010) +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_RX_MCI_SYS_WAKING_TIMESTAMP___RWC QCSR_REG_RO +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_RX_MCI_SYS_WAKING_TIMESTAMP___POR 0x00000000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_RX_MCI_SYS_WAKING_TIMESTAMP__TIMESTAMP___POR 0x00000000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_RX_MCI_SYS_WAKING_TIMESTAMP__TIMESTAMP___M 0xFFFFFFFF +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_RX_MCI_SYS_WAKING_TIMESTAMP__TIMESTAMP___S 0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_RX_MCI_SYS_WAKING_TIMESTAMP___M 0xFFFFFFFF +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_RX_MCI_SYS_WAKING_TIMESTAMP___S 0 + +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INVALID_APB_ACC_ADR (0x00A2B014) +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INVALID_APB_ACC_ADR___RWC QCSR_REG_RW +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INVALID_APB_ACC_ADR___POR 0x00000000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INVALID_APB_ACC_ADR__ERR_TYPE___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INVALID_APB_ACC_ADR__ERR_ADDR___POR 0x00000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INVALID_APB_ACC_ADR__ERR_TYPE___M 0x00060000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INVALID_APB_ACC_ADR__ERR_TYPE___S 17 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INVALID_APB_ACC_ADR__ERR_ADDR___M 0x0001FFFF +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INVALID_APB_ACC_ADR__ERR_ADDR___S 0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INVALID_APB_ACC_ADR___M 0x0007FFFF +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_INVALID_APB_ACC_ADR___S 0 + +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_DEBUG_STATES (0x00A2B018) +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_DEBUG_STATES___RWC QCSR_REG_RO +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_DEBUG_STATES___POR 0x00000001 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_DEBUG_STATES__WLAN3_PWR_STATE___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_DEBUG_STATES__WLAN2_PWR_STATE___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_DEBUG_STATES__WLAN1_PWR_STATE___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_DEBUG_STATES__PMH_STATE___POR 0x1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_DEBUG_STATES__WLAN3_PWR_STATE___M 0x00000300 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_DEBUG_STATES__WLAN3_PWR_STATE___S 8 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_DEBUG_STATES__WLAN2_PWR_STATE___M 0x000000C0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_DEBUG_STATES__WLAN2_PWR_STATE___S 6 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_DEBUG_STATES__WLAN1_PWR_STATE___M 0x00000030 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_DEBUG_STATES__WLAN1_PWR_STATE___S 4 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_DEBUG_STATES__PMH_STATE___M 0x0000000F +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_DEBUG_STATES__PMH_STATE___S 0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_DEBUG_STATES___M 0x000003FF +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_DEBUG_STATES___S 0 + +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TESTBUS_CTRL (0x00A2B01C) +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TESTBUS_CTRL___RWC QCSR_REG_RW +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TESTBUS_CTRL___POR 0x00000000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TESTBUS_CTRL__SPARE___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TESTBUS_CTRL__SPARE2___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TESTBUS_CTRL__TESTBUS_SELECT___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TESTBUS_CTRL__SPARE___M 0xF0000000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TESTBUS_CTRL__SPARE___S 28 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TESTBUS_CTRL__SPARE2___M 0x01000000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TESTBUS_CTRL__SPARE2___S 24 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TESTBUS_CTRL__TESTBUS_SELECT___M 0x0000000F +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TESTBUS_CTRL__TESTBUS_SELECT___S 0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TESTBUS_CTRL___M 0xF100000F +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TESTBUS_CTRL___S 0 + +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS (0x00A2B020) +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS___RWC QCSR_REG_RO +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS___POR 0x00000000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__PMU_WLAN3_PWR_DWN_DONE_EVENT___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__SW_WLAN3_PWR_DWN_DONE_EVENT___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__CCU_ACCESS_ERR_EVENT___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__WSI_BUS_SYNC_EVENT___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__BT_RESPONSE_TIMEOUT_EVENT___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__PWR_DOWN_TIMEOUT_EVENT___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__PMU_WLAN2_PWR_DWN_DONE_EVENT___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__PMU_WLAN1_PWR_DWN_DONE_EVENT___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__SW_WLAN2_PWR_DWN_DONE_EVENT___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__SW_WLAN1_PWR_DWN_DONE_EVENT___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__BT_SYS_SLEEPING_EVENT___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__BT_SYS_WAKING_EVENT___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__PMU_WLAN3_PWR_DWN_DONE_EVENT___M 0x00000800 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__PMU_WLAN3_PWR_DWN_DONE_EVENT___S 11 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__SW_WLAN3_PWR_DWN_DONE_EVENT___M 0x00000400 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__SW_WLAN3_PWR_DWN_DONE_EVENT___S 10 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__CCU_ACCESS_ERR_EVENT___M 0x00000200 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__CCU_ACCESS_ERR_EVENT___S 9 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__WSI_BUS_SYNC_EVENT___M 0x00000100 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__WSI_BUS_SYNC_EVENT___S 8 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__BT_RESPONSE_TIMEOUT_EVENT___M 0x00000080 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__BT_RESPONSE_TIMEOUT_EVENT___S 7 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__PWR_DOWN_TIMEOUT_EVENT___M 0x00000040 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__PWR_DOWN_TIMEOUT_EVENT___S 6 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__PMU_WLAN2_PWR_DWN_DONE_EVENT___M 0x00000020 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__PMU_WLAN2_PWR_DWN_DONE_EVENT___S 5 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__PMU_WLAN1_PWR_DWN_DONE_EVENT___M 0x00000010 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__PMU_WLAN1_PWR_DWN_DONE_EVENT___S 4 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__SW_WLAN2_PWR_DWN_DONE_EVENT___M 0x00000008 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__SW_WLAN2_PWR_DWN_DONE_EVENT___S 3 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__SW_WLAN1_PWR_DWN_DONE_EVENT___M 0x00000004 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__SW_WLAN1_PWR_DWN_DONE_EVENT___S 2 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__BT_SYS_SLEEPING_EVENT___M 0x00000002 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__BT_SYS_SLEEPING_EVENT___S 1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__BT_SYS_WAKING_EVENT___M 0x00000001 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS__BT_SYS_WAKING_EVENT___S 0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS___M 0x00000FFF +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_STATUS___S 0 + +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE (0x00A2B024) +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE___RWC QCSR_REG_RW +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE___POR 0x00000000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__PMU_WLAN3_PWR_DWN_DONE_EVENT_EN___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__SW_WLAN3_PWR_DWN_DONE_EVENT_EN___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__CCU_ACCESS_ERR_EVENT_EN___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__WSI_BUS_SYNC_EVENT_EN___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__BT_RESPONSE_TIMEOUT_EVENT_EN___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__PWR_DOWN_TIMEOUT_EVENT_EN___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__PMU_WLAN2_PWR_DWN_DONE_EVENT_EN___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__PMU_WLAN1_PWR_DWN_DONE_EVENT_EN___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__SW_WLAN2_PWR_DWN_DONE_EVENT_EN___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__SW_WLAN1_PWR_DWN_DONE_EVENT_EN___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__BT_SYS_SLEEPING_EVENT_EN___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__BT_SYS_WAKING_EVENT_EN___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__PMU_WLAN3_PWR_DWN_DONE_EVENT_EN___M 0x00000800 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__PMU_WLAN3_PWR_DWN_DONE_EVENT_EN___S 11 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__SW_WLAN3_PWR_DWN_DONE_EVENT_EN___M 0x00000400 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__SW_WLAN3_PWR_DWN_DONE_EVENT_EN___S 10 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__CCU_ACCESS_ERR_EVENT_EN___M 0x00000200 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__CCU_ACCESS_ERR_EVENT_EN___S 9 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__WSI_BUS_SYNC_EVENT_EN___M 0x00000100 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__WSI_BUS_SYNC_EVENT_EN___S 8 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__BT_RESPONSE_TIMEOUT_EVENT_EN___M 0x00000080 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__BT_RESPONSE_TIMEOUT_EVENT_EN___S 7 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__PWR_DOWN_TIMEOUT_EVENT_EN___M 0x00000040 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__PWR_DOWN_TIMEOUT_EVENT_EN___S 6 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__PMU_WLAN2_PWR_DWN_DONE_EVENT_EN___M 0x00000020 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__PMU_WLAN2_PWR_DWN_DONE_EVENT_EN___S 5 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__PMU_WLAN1_PWR_DWN_DONE_EVENT_EN___M 0x00000010 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__PMU_WLAN1_PWR_DWN_DONE_EVENT_EN___S 4 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__SW_WLAN2_PWR_DWN_DONE_EVENT_EN___M 0x00000008 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__SW_WLAN2_PWR_DWN_DONE_EVENT_EN___S 3 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__SW_WLAN1_PWR_DWN_DONE_EVENT_EN___M 0x00000004 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__SW_WLAN1_PWR_DWN_DONE_EVENT_EN___S 2 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__BT_SYS_SLEEPING_EVENT_EN___M 0x00000002 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__BT_SYS_SLEEPING_EVENT_EN___S 1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__BT_SYS_WAKING_EVENT_EN___M 0x00000001 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE__BT_SYS_WAKING_EVENT_EN___S 0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE___M 0x00000FFF +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_ENABLE___S 0 + +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR (0x00A2B028) +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR___RWC QCSR_REG_RW +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR___POR 0x00000000 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__PMU_WLAN3_PWR_DWN_DONE_EVENT_CLR___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__SW_WLAN3_PWR_DWN_DONE_EVENT_CLR___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__CCU_ACCESS_ERR_EVENT_CLR___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__WSI_BUS_SYNC_EVENT_CLR___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__BT_RESPONSE_TIMEOUT_EVENT_CLR___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__PWR_DOWN_TIMEOUT_EVENT_CLR___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__PMU_WLAN2_PWR_DWN_DONE_EVENT_CLR___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__PMU_WLAN1_PWR_DWN_DONE_EVENT_CLR___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__SW_WLAN2_PWR_DWN_DONE_EVENT_CLR___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__SW_WLAN1_PWR_DWN_DONE_EVENT_CLR___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__BT_SYS_SLEEPING_EVENT_CLR___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__BT_SYS_WAKING_EVENT_CLR___POR 0x0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__PMU_WLAN3_PWR_DWN_DONE_EVENT_CLR___M 0x00000800 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__PMU_WLAN3_PWR_DWN_DONE_EVENT_CLR___S 11 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__SW_WLAN3_PWR_DWN_DONE_EVENT_CLR___M 0x00000400 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__SW_WLAN3_PWR_DWN_DONE_EVENT_CLR___S 10 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__CCU_ACCESS_ERR_EVENT_CLR___M 0x00000200 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__CCU_ACCESS_ERR_EVENT_CLR___S 9 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__WSI_BUS_SYNC_EVENT_CLR___M 0x00000100 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__WSI_BUS_SYNC_EVENT_CLR___S 8 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__BT_RESPONSE_TIMEOUT_EVENT_CLR___M 0x00000080 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__BT_RESPONSE_TIMEOUT_EVENT_CLR___S 7 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__PWR_DOWN_TIMEOUT_EVENT_CLR___M 0x00000040 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__PWR_DOWN_TIMEOUT_EVENT_CLR___S 6 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__PMU_WLAN2_PWR_DWN_DONE_EVENT_CLR___M 0x00000020 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__PMU_WLAN2_PWR_DWN_DONE_EVENT_CLR___S 5 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__PMU_WLAN1_PWR_DWN_DONE_EVENT_CLR___M 0x00000010 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__PMU_WLAN1_PWR_DWN_DONE_EVENT_CLR___S 4 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__SW_WLAN2_PWR_DWN_DONE_EVENT_CLR___M 0x00000008 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__SW_WLAN2_PWR_DWN_DONE_EVENT_CLR___S 3 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__SW_WLAN1_PWR_DWN_DONE_EVENT_CLR___M 0x00000004 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__SW_WLAN1_PWR_DWN_DONE_EVENT_CLR___S 2 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__BT_SYS_SLEEPING_EVENT_CLR___M 0x00000002 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__BT_SYS_SLEEPING_EVENT_CLR___S 1 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__BT_SYS_WAKING_EVENT_CLR___M 0x00000001 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR__BT_SYS_WAKING_EVENT_CLR___S 0 +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR___M 0x00000FFF +#define UMAC_CXC_PMH_REG_CXC_PMH_R1_TRC_CTRL_CLR___S 0 + +#define UMAC_TRACER_R0_CONTROL (0x00A30000) +#define UMAC_TRACER_R0_CONTROL___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_CONTROL___POR 0x00000000 +#define UMAC_TRACER_R0_CONTROL__CROSS_MEM_MODE___POR 0x0 +#define UMAC_TRACER_R0_CONTROL__CMEM_ACCESS_ENABLE___POR 0x0 +#define UMAC_TRACER_R0_CONTROL__OBS_BUS_SEL___POR 0x0 +#define UMAC_TRACER_R0_CONTROL__MAC_MODULE_SEL___POR 0x0 +#define UMAC_TRACER_R0_CONTROL__CPU_ACCESS_EN_VALUE___POR 0x0 +#define UMAC_TRACER_R0_CONTROL__BUF_CFG_VALUE___POR 0x0 +#define UMAC_TRACER_R0_CONTROL__ENABLE_VALUE___POR 0x0 +#define UMAC_TRACER_R0_CONTROL__CROSS_MEM_MODE___M 0x00002000 +#define UMAC_TRACER_R0_CONTROL__CROSS_MEM_MODE___S 13 +#define UMAC_TRACER_R0_CONTROL__CMEM_ACCESS_ENABLE___M 0x00001000 +#define UMAC_TRACER_R0_CONTROL__CMEM_ACCESS_ENABLE___S 12 +#define UMAC_TRACER_R0_CONTROL__OBS_BUS_SEL___M 0x00000C00 +#define UMAC_TRACER_R0_CONTROL__OBS_BUS_SEL___S 10 +#define UMAC_TRACER_R0_CONTROL__MAC_MODULE_SEL___M 0x00000300 +#define UMAC_TRACER_R0_CONTROL__MAC_MODULE_SEL___S 8 +#define UMAC_TRACER_R0_CONTROL__CPU_ACCESS_EN_VALUE___M 0x00000010 +#define UMAC_TRACER_R0_CONTROL__CPU_ACCESS_EN_VALUE___S 4 +#define UMAC_TRACER_R0_CONTROL__BUF_CFG_VALUE___M 0x00000002 +#define UMAC_TRACER_R0_CONTROL__BUF_CFG_VALUE___S 1 +#define UMAC_TRACER_R0_CONTROL__ENABLE_VALUE___M 0x00000001 +#define UMAC_TRACER_R0_CONTROL__ENABLE_VALUE___S 0 +#define UMAC_TRACER_R0_CONTROL___M 0x00003F13 +#define UMAC_TRACER_R0_CONTROL___S 0 + +#define UMAC_TRACER_R0_BUF_INIT (0x00A30004) +#define UMAC_TRACER_R0_BUF_INIT___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_BUF_INIT___POR 0x00000000 +#define UMAC_TRACER_R0_BUF_INIT__VALUE___POR 0x0 +#define UMAC_TRACER_R0_BUF_INIT__VALUE___M 0x00000001 +#define UMAC_TRACER_R0_BUF_INIT__VALUE___S 0 +#define UMAC_TRACER_R0_BUF_INIT___M 0x00000001 +#define UMAC_TRACER_R0_BUF_INIT___S 0 + +#define UMAC_TRACER_R0_ADDR (0x00A30008) +#define UMAC_TRACER_R0_ADDR___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_ADDR___POR 0x00000000 +#define UMAC_TRACER_R0_ADDR__END_VALUE___POR 0x0000 +#define UMAC_TRACER_R0_ADDR__START_VALUE___POR 0x0000 +#define UMAC_TRACER_R0_ADDR__END_VALUE___M 0x3FFF0000 +#define UMAC_TRACER_R0_ADDR__END_VALUE___S 16 +#define UMAC_TRACER_R0_ADDR__START_VALUE___M 0x00003FFF +#define UMAC_TRACER_R0_ADDR__START_VALUE___S 0 +#define UMAC_TRACER_R0_ADDR___M 0x3FFF3FFF +#define UMAC_TRACER_R0_ADDR___S 0 + +#define UMAC_TRACER_R0_WFT_CAPTURE_CTRL (0x00A3000C) +#define UMAC_TRACER_R0_WFT_CAPTURE_CTRL___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_WFT_CAPTURE_CTRL___POR 0x00000000 +#define UMAC_TRACER_R0_WFT_CAPTURE_CTRL__CAP_MODE___POR 0x0 +#define UMAC_TRACER_R0_WFT_CAPTURE_CTRL__CAP_MASK___POR 0x00000000 +#define UMAC_TRACER_R0_WFT_CAPTURE_CTRL__CAP_MODE___M 0xC0000000 +#define UMAC_TRACER_R0_WFT_CAPTURE_CTRL__CAP_MODE___S 30 +#define UMAC_TRACER_R0_WFT_CAPTURE_CTRL__CAP_MASK___M 0x3FFFFFFF +#define UMAC_TRACER_R0_WFT_CAPTURE_CTRL__CAP_MASK___S 0 +#define UMAC_TRACER_R0_WFT_CAPTURE_CTRL___M 0xFFFFFFFF +#define UMAC_TRACER_R0_WFT_CAPTURE_CTRL___S 0 + +#define UMAC_TRACER_R0_WFT_STATE_CTRL (0x00A30010) +#define UMAC_TRACER_R0_WFT_STATE_CTRL___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_WFT_STATE_CTRL___POR 0x00000000 +#define UMAC_TRACER_R0_WFT_STATE_CTRL__MAX_CAP_CNT___POR 0x0000 +#define UMAC_TRACER_R0_WFT_STATE_CTRL__NXT_TS_EN___POR 0x00 +#define UMAC_TRACER_R0_WFT_STATE_CTRL__MAX_CAP_CNT___M 0xFFFF0000 +#define UMAC_TRACER_R0_WFT_STATE_CTRL__MAX_CAP_CNT___S 16 +#define UMAC_TRACER_R0_WFT_STATE_CTRL__NXT_TS_EN___M 0x0000001F +#define UMAC_TRACER_R0_WFT_STATE_CTRL__NXT_TS_EN___S 0 +#define UMAC_TRACER_R0_WFT_STATE_CTRL___M 0xFFFF001F +#define UMAC_TRACER_R0_WFT_STATE_CTRL___S 0 + +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_0 (0x00A30014) +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_0___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_0___POR 0x00000000 +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_0__CAP_MODE___POR 0x0 +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_0__CAP_MASK___POR 0x00000000 +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_0__CAP_MODE___M 0xC0000000 +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_0__CAP_MODE___S 30 +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_0__CAP_MASK___M 0x3FFFFFFF +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_0__CAP_MASK___S 0 +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_0___M 0xFFFFFFFF +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_0___S 0 + +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_0 (0x00A30018) +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_0___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_0___POR 0x00000000 +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_0__MAX_CAP_CNT___POR 0x0000 +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_0__NXT_TS_EN___POR 0x00 +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_0__MAX_CAP_CNT___M 0xFFFF0000 +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_0__MAX_CAP_CNT___S 16 +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_0__NXT_TS_EN___M 0x0000001F +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_0__NXT_TS_EN___S 0 +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_0___M 0xFFFF001F +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_0___S 0 + +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_0 (0x00A3001C) +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_0___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_0___POR 0x00000000 +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_0__VALUE___POR 0x00000000 +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_0__VALUE___M 0x3FFFFFFF +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_0__VALUE___S 0 +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_0___M 0x3FFFFFFF +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_0___S 0 + +#define UMAC_TRACER_R0_TS_TRIG_IX_0 (0x00A30020) +#define UMAC_TRACER_R0_TS_TRIG_IX_0___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_TS_TRIG_IX_0___POR 0x00000000 +#define UMAC_TRACER_R0_TS_TRIG_IX_0__VALUE___POR 0x00000000 +#define UMAC_TRACER_R0_TS_TRIG_IX_0__VALUE___M 0x3FFFFFFF +#define UMAC_TRACER_R0_TS_TRIG_IX_0__VALUE___S 0 +#define UMAC_TRACER_R0_TS_TRIG_IX_0___M 0x3FFFFFFF +#define UMAC_TRACER_R0_TS_TRIG_IX_0___S 0 + +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_1 (0x00A30024) +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_1___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_1___POR 0x00000000 +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_1__CAP_MODE___POR 0x0 +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_1__CAP_MASK___POR 0x00000000 +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_1__CAP_MODE___M 0xC0000000 +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_1__CAP_MODE___S 30 +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_1__CAP_MASK___M 0x3FFFFFFF +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_1__CAP_MASK___S 0 +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_1___M 0xFFFFFFFF +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_1___S 0 + +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_1 (0x00A30028) +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_1___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_1___POR 0x00000000 +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_1__MAX_CAP_CNT___POR 0x0000 +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_1__NXT_TS_EN___POR 0x00 +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_1__MAX_CAP_CNT___M 0xFFFF0000 +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_1__MAX_CAP_CNT___S 16 +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_1__NXT_TS_EN___M 0x0000001F +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_1__NXT_TS_EN___S 0 +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_1___M 0xFFFF001F +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_1___S 0 + +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_1 (0x00A3002C) +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_1___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_1___POR 0x00000000 +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_1__VALUE___POR 0x00000000 +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_1__VALUE___M 0x3FFFFFFF +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_1__VALUE___S 0 +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_1___M 0x3FFFFFFF +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_1___S 0 + +#define UMAC_TRACER_R0_TS_TRIG_IX_1 (0x00A30030) +#define UMAC_TRACER_R0_TS_TRIG_IX_1___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_TS_TRIG_IX_1___POR 0x00000000 +#define UMAC_TRACER_R0_TS_TRIG_IX_1__VALUE___POR 0x00000000 +#define UMAC_TRACER_R0_TS_TRIG_IX_1__VALUE___M 0x3FFFFFFF +#define UMAC_TRACER_R0_TS_TRIG_IX_1__VALUE___S 0 +#define UMAC_TRACER_R0_TS_TRIG_IX_1___M 0x3FFFFFFF +#define UMAC_TRACER_R0_TS_TRIG_IX_1___S 0 + +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_2 (0x00A30034) +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_2___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_2___POR 0x00000000 +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_2__CAP_MODE___POR 0x0 +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_2__CAP_MASK___POR 0x00000000 +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_2__CAP_MODE___M 0xC0000000 +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_2__CAP_MODE___S 30 +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_2__CAP_MASK___M 0x3FFFFFFF +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_2__CAP_MASK___S 0 +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_2___M 0xFFFFFFFF +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_2___S 0 + +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_2 (0x00A30038) +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_2___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_2___POR 0x00000000 +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_2__MAX_CAP_CNT___POR 0x0000 +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_2__NXT_TS_EN___POR 0x00 +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_2__MAX_CAP_CNT___M 0xFFFF0000 +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_2__MAX_CAP_CNT___S 16 +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_2__NXT_TS_EN___M 0x0000001F +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_2__NXT_TS_EN___S 0 +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_2___M 0xFFFF001F +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_2___S 0 + +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_2 (0x00A3003C) +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_2___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_2___POR 0x00000000 +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_2__VALUE___POR 0x00000000 +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_2__VALUE___M 0x3FFFFFFF +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_2__VALUE___S 0 +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_2___M 0x3FFFFFFF +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_2___S 0 + +#define UMAC_TRACER_R0_TS_TRIG_IX_2 (0x00A30040) +#define UMAC_TRACER_R0_TS_TRIG_IX_2___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_TS_TRIG_IX_2___POR 0x00000000 +#define UMAC_TRACER_R0_TS_TRIG_IX_2__VALUE___POR 0x00000000 +#define UMAC_TRACER_R0_TS_TRIG_IX_2__VALUE___M 0x3FFFFFFF +#define UMAC_TRACER_R0_TS_TRIG_IX_2__VALUE___S 0 +#define UMAC_TRACER_R0_TS_TRIG_IX_2___M 0x3FFFFFFF +#define UMAC_TRACER_R0_TS_TRIG_IX_2___S 0 + +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_3 (0x00A30044) +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_3___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_3___POR 0x00000000 +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_3__CAP_MODE___POR 0x0 +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_3__CAP_MASK___POR 0x00000000 +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_3__CAP_MODE___M 0xC0000000 +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_3__CAP_MODE___S 30 +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_3__CAP_MASK___M 0x3FFFFFFF +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_3__CAP_MASK___S 0 +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_3___M 0xFFFFFFFF +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_3___S 0 + +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_3 (0x00A30048) +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_3___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_3___POR 0x00000000 +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_3__MAX_CAP_CNT___POR 0x0000 +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_3__NXT_TS_EN___POR 0x00 +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_3__MAX_CAP_CNT___M 0xFFFF0000 +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_3__MAX_CAP_CNT___S 16 +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_3__NXT_TS_EN___M 0x0000001F +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_3__NXT_TS_EN___S 0 +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_3___M 0xFFFF001F +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_3___S 0 + +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_3 (0x00A3004C) +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_3___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_3___POR 0x00000000 +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_3__VALUE___POR 0x00000000 +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_3__VALUE___M 0x3FFFFFFF +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_3__VALUE___S 0 +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_3___M 0x3FFFFFFF +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_3___S 0 + +#define UMAC_TRACER_R0_TS_TRIG_IX_3 (0x00A30050) +#define UMAC_TRACER_R0_TS_TRIG_IX_3___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_TS_TRIG_IX_3___POR 0x00000000 +#define UMAC_TRACER_R0_TS_TRIG_IX_3__VALUE___POR 0x00000000 +#define UMAC_TRACER_R0_TS_TRIG_IX_3__VALUE___M 0x3FFFFFFF +#define UMAC_TRACER_R0_TS_TRIG_IX_3__VALUE___S 0 +#define UMAC_TRACER_R0_TS_TRIG_IX_3___M 0x3FFFFFFF +#define UMAC_TRACER_R0_TS_TRIG_IX_3___S 0 + +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_4 (0x00A30054) +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_4___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_4___POR 0x00000000 +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_4__CAP_MODE___POR 0x0 +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_4__CAP_MASK___POR 0x00000000 +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_4__CAP_MODE___M 0xC0000000 +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_4__CAP_MODE___S 30 +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_4__CAP_MASK___M 0x3FFFFFFF +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_4__CAP_MASK___S 0 +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_4___M 0xFFFFFFFF +#define UMAC_TRACER_R0_TS_CAPTURE_CTRL_IX_4___S 0 + +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_4 (0x00A30058) +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_4___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_4___POR 0x00000000 +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_4__MAX_CAP_CNT___POR 0x0000 +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_4__NXT_TS_EN___POR 0x00 +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_4__MAX_CAP_CNT___M 0xFFFF0000 +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_4__MAX_CAP_CNT___S 16 +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_4__NXT_TS_EN___M 0x0000001F +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_4__NXT_TS_EN___S 0 +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_4___M 0xFFFF001F +#define UMAC_TRACER_R0_TS_STATE_CTRL_IX_4___S 0 + +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_4 (0x00A3005C) +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_4___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_4___POR 0x00000000 +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_4__VALUE___POR 0x00000000 +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_4__VALUE___M 0x3FFFFFFF +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_4__VALUE___S 0 +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_4___M 0x3FFFFFFF +#define UMAC_TRACER_R0_TS_TRIG_MASK_IX_4___S 0 + +#define UMAC_TRACER_R0_TS_TRIG_IX_4 (0x00A30060) +#define UMAC_TRACER_R0_TS_TRIG_IX_4___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_TS_TRIG_IX_4___POR 0x00000000 +#define UMAC_TRACER_R0_TS_TRIG_IX_4__VALUE___POR 0x00000000 +#define UMAC_TRACER_R0_TS_TRIG_IX_4__VALUE___M 0x3FFFFFFF +#define UMAC_TRACER_R0_TS_TRIG_IX_4__VALUE___S 0 +#define UMAC_TRACER_R0_TS_TRIG_IX_4___M 0x3FFFFFFF +#define UMAC_TRACER_R0_TS_TRIG_IX_4___S 0 + +#define UMAC_TRACER_R0_CPU_ADDR (0x00A30064) +#define UMAC_TRACER_R0_CPU_ADDR___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_CPU_ADDR___POR 0x00000000 +#define UMAC_TRACER_R0_CPU_ADDR__READ_VALUE___POR 0x00000000 +#define UMAC_TRACER_R0_CPU_ADDR__READ_VALUE___M 0xFFFFFFFF +#define UMAC_TRACER_R0_CPU_ADDR__READ_VALUE___S 0 +#define UMAC_TRACER_R0_CPU_ADDR___M 0xFFFFFFFF +#define UMAC_TRACER_R0_CPU_ADDR___S 0 + +#define UMAC_TRACER_R0_CPU_DATA (0x00A30068) +#define UMAC_TRACER_R0_CPU_DATA___RWC QCSR_REG_RO +#define UMAC_TRACER_R0_CPU_DATA___POR 0x00000000 +#define UMAC_TRACER_R0_CPU_DATA__VALUE___POR 0x00000000 +#define UMAC_TRACER_R0_CPU_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_TRACER_R0_CPU_DATA__VALUE___S 0 +#define UMAC_TRACER_R0_CPU_DATA___M 0xFFFFFFFF +#define UMAC_TRACER_R0_CPU_DATA___S 0 + +#define UMAC_TRACER_R0_STATUS_0 (0x00A3006C) +#define UMAC_TRACER_R0_STATUS_0___RWC QCSR_REG_RO +#define UMAC_TRACER_R0_STATUS_0___POR 0x00000000 +#define UMAC_TRACER_R0_STATUS_0__BUF_INIT_DONE___POR 0x0 +#define UMAC_TRACER_R0_STATUS_0__BUF_FULL___POR 0x0 +#define UMAC_TRACER_R0_STATUS_0__BUF_INIT_DONE___M 0x00000002 +#define UMAC_TRACER_R0_STATUS_0__BUF_INIT_DONE___S 1 +#define UMAC_TRACER_R0_STATUS_0__BUF_FULL___M 0x00000001 +#define UMAC_TRACER_R0_STATUS_0__BUF_FULL___S 0 +#define UMAC_TRACER_R0_STATUS_0___M 0x00000003 +#define UMAC_TRACER_R0_STATUS_0___S 0 + +#define UMAC_TRACER_R0_STATUS_1 (0x00A30070) +#define UMAC_TRACER_R0_STATUS_1___RWC QCSR_REG_RO +#define UMAC_TRACER_R0_STATUS_1___POR 0x00000000 +#define UMAC_TRACER_R0_STATUS_1__BUF_RD_END_ADDR___POR 0x0000 +#define UMAC_TRACER_R0_STATUS_1__BUF_RD_START_ADDR___POR 0x0000 +#define UMAC_TRACER_R0_STATUS_1__BUF_RD_END_ADDR___M 0x3FFF0000 +#define UMAC_TRACER_R0_STATUS_1__BUF_RD_END_ADDR___S 16 +#define UMAC_TRACER_R0_STATUS_1__BUF_RD_START_ADDR___M 0x00003FFF +#define UMAC_TRACER_R0_STATUS_1__BUF_RD_START_ADDR___S 0 +#define UMAC_TRACER_R0_STATUS_1___M 0x3FFF3FFF +#define UMAC_TRACER_R0_STATUS_1___S 0 + +#define UMAC_TRACER_R0_STATUS_2 (0x00A30074) +#define UMAC_TRACER_R0_STATUS_2___RWC QCSR_REG_RO +#define UMAC_TRACER_R0_STATUS_2___POR 0x00000000 +#define UMAC_TRACER_R0_STATUS_2__TRIG_EVENT_FLAGS___POR 0x00 +#define UMAC_TRACER_R0_STATUS_2__MAIN_CTL_STATE___POR 0x0 +#define UMAC_TRACER_R0_STATUS_2__WRCTL_STATE___POR 0x0 +#define UMAC_TRACER_R0_STATUS_2__TRIG_EVENT_FLAGS___M 0x00001F00 +#define UMAC_TRACER_R0_STATUS_2__TRIG_EVENT_FLAGS___S 8 +#define UMAC_TRACER_R0_STATUS_2__MAIN_CTL_STATE___M 0x00000070 +#define UMAC_TRACER_R0_STATUS_2__MAIN_CTL_STATE___S 4 +#define UMAC_TRACER_R0_STATUS_2__WRCTL_STATE___M 0x00000007 +#define UMAC_TRACER_R0_STATUS_2__WRCTL_STATE___S 0 +#define UMAC_TRACER_R0_STATUS_2___M 0x00001F77 +#define UMAC_TRACER_R0_STATUS_2___S 0 + +#define UMAC_TRACER_R0_STATUS_3 (0x00A30078) +#define UMAC_TRACER_R0_STATUS_3___RWC QCSR_REG_RO +#define UMAC_TRACER_R0_STATUS_3___POR 0x00000000 +#define UMAC_TRACER_R0_STATUS_3__TRIG_SAMPLE___POR 0x00000000 +#define UMAC_TRACER_R0_STATUS_3__TRIG_SAMPLE___M 0x3FFFFFFF +#define UMAC_TRACER_R0_STATUS_3__TRIG_SAMPLE___S 0 +#define UMAC_TRACER_R0_STATUS_3___M 0x3FFFFFFF +#define UMAC_TRACER_R0_STATUS_3___S 0 + +#define UMAC_TRACER_R0_MAC_BB_OBS_BUS_SEL (0x00A3007C) +#define UMAC_TRACER_R0_MAC_BB_OBS_BUS_SEL___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_MAC_BB_OBS_BUS_SEL___POR 0x00000000 +#define UMAC_TRACER_R0_MAC_BB_OBS_BUS_SEL__VALUE___POR 0x00000000 +#define UMAC_TRACER_R0_MAC_BB_OBS_BUS_SEL__VALUE___M 0xFFFFFFFF +#define UMAC_TRACER_R0_MAC_BB_OBS_BUS_SEL__VALUE___S 0 +#define UMAC_TRACER_R0_MAC_BB_OBS_BUS_SEL___M 0xFFFFFFFF +#define UMAC_TRACER_R0_MAC_BB_OBS_BUS_SEL___S 0 + +#define UMAC_TRACER_R0_CPU_DATA_READ_DATA_SEL (0x00A30080) +#define UMAC_TRACER_R0_CPU_DATA_READ_DATA_SEL___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_CPU_DATA_READ_DATA_SEL___POR 0x00000000 +#define UMAC_TRACER_R0_CPU_DATA_READ_DATA_SEL__VALUE___POR 0x0 +#define UMAC_TRACER_R0_CPU_DATA_READ_DATA_SEL__VALUE___M 0x00000001 +#define UMAC_TRACER_R0_CPU_DATA_READ_DATA_SEL__VALUE___S 0 +#define UMAC_TRACER_R0_CPU_DATA_READ_DATA_SEL___M 0x00000001 +#define UMAC_TRACER_R0_CPU_DATA_READ_DATA_SEL___S 0 + +#define UMAC_TRACER_R0_LANE_SWAP (0x00A30084) +#define UMAC_TRACER_R0_LANE_SWAP___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_LANE_SWAP___POR 0x0000000F +#define UMAC_TRACER_R0_LANE_SWAP__SEL___POR 0x0F +#define UMAC_TRACER_R0_LANE_SWAP__SEL___M 0x0000001F +#define UMAC_TRACER_R0_LANE_SWAP__SEL___S 0 +#define UMAC_TRACER_R0_LANE_SWAP___M 0x0000001F +#define UMAC_TRACER_R0_LANE_SWAP___S 0 + +#define UMAC_TRACER_R0_CLK_GATE_DISABLE (0x00A30088) +#define UMAC_TRACER_R0_CLK_GATE_DISABLE___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_CLK_GATE_DISABLE___POR 0x00000000 +#define UMAC_TRACER_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND___POR 0x0 +#define UMAC_TRACER_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND_APB___POR 0x0 +#define UMAC_TRACER_R0_CLK_GATE_DISABLE__TBD___POR 0x0000000 +#define UMAC_TRACER_R0_CLK_GATE_DISABLE__APB_VAL___POR 0x0 +#define UMAC_TRACER_R0_CLK_GATE_DISABLE__VAL___POR 0x0 +#define UMAC_TRACER_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND___M 0x80000000 +#define UMAC_TRACER_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND___S 31 +#define UMAC_TRACER_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND_APB___M 0x40000000 +#define UMAC_TRACER_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND_APB___S 30 +#define UMAC_TRACER_R0_CLK_GATE_DISABLE__TBD___M 0x3FFFFFFC +#define UMAC_TRACER_R0_CLK_GATE_DISABLE__TBD___S 2 +#define UMAC_TRACER_R0_CLK_GATE_DISABLE__APB_VAL___M 0x00000002 +#define UMAC_TRACER_R0_CLK_GATE_DISABLE__APB_VAL___S 1 +#define UMAC_TRACER_R0_CLK_GATE_DISABLE__VAL___M 0x00000001 +#define UMAC_TRACER_R0_CLK_GATE_DISABLE__VAL___S 0 +#define UMAC_TRACER_R0_CLK_GATE_DISABLE___M 0xFFFFFFFF +#define UMAC_TRACER_R0_CLK_GATE_DISABLE___S 0 + +#define UMAC_TRACER_R0_TIME_STAMP (0x00A3008C) +#define UMAC_TRACER_R0_TIME_STAMP___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_TIME_STAMP___POR 0x00000000 +#define UMAC_TRACER_R0_TIME_STAMP__SEL___POR 0x0 +#define UMAC_TRACER_R0_TIME_STAMP__SEL___M 0x00000001 +#define UMAC_TRACER_R0_TIME_STAMP__SEL___S 0 +#define UMAC_TRACER_R0_TIME_STAMP___M 0x00000001 +#define UMAC_TRACER_R0_TIME_STAMP___S 0 + +#define UMAC_TRACER_R0_CSS_RTL_VERSION (0x00A30090) +#define UMAC_TRACER_R0_CSS_RTL_VERSION___RWC QCSR_REG_RO +#define UMAC_TRACER_R0_CSS_RTL_VERSION___POR 0x00000000 +#define UMAC_TRACER_R0_CSS_RTL_VERSION__VAL___POR 0x00000000 +#define UMAC_TRACER_R0_CSS_RTL_VERSION__VAL___M 0xFFFFFFFF +#define UMAC_TRACER_R0_CSS_RTL_VERSION__VAL___S 0 +#define UMAC_TRACER_R0_CSS_RTL_VERSION___M 0xFFFFFFFF +#define UMAC_TRACER_R0_CSS_RTL_VERSION___S 0 + +#define UMAC_TRACER_R0_INVALID_APB_ACC_ADDR (0x00A30094) +#define UMAC_TRACER_R0_INVALID_APB_ACC_ADDR___RWC QCSR_REG_RO +#define UMAC_TRACER_R0_INVALID_APB_ACC_ADDR___POR 0x00000000 +#define UMAC_TRACER_R0_INVALID_APB_ACC_ADDR__VALUE___POR 0x000 +#define UMAC_TRACER_R0_INVALID_APB_ACC_ADDR__VALUE___M 0x00000FFF +#define UMAC_TRACER_R0_INVALID_APB_ACC_ADDR__VALUE___S 0 +#define UMAC_TRACER_R0_INVALID_APB_ACC_ADDR___M 0x00000FFF +#define UMAC_TRACER_R0_INVALID_APB_ACC_ADDR___S 0 + +#define UMAC_TRACER_R0_INT_CTRL (0x00A30098) +#define UMAC_TRACER_R0_INT_CTRL___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_INT_CTRL___POR 0x00000000 +#define UMAC_TRACER_R0_INT_CTRL__MODE___POR 0x0 +#define UMAC_TRACER_R0_INT_CTRL__ENABLE___POR 0x0 +#define UMAC_TRACER_R0_INT_CTRL__MODE___M 0x00000002 +#define UMAC_TRACER_R0_INT_CTRL__MODE___S 1 +#define UMAC_TRACER_R0_INT_CTRL__ENABLE___M 0x00000001 +#define UMAC_TRACER_R0_INT_CTRL__ENABLE___S 0 +#define UMAC_TRACER_R0_INT_CTRL___M 0x00000003 +#define UMAC_TRACER_R0_INT_CTRL___S 0 + +#define UMAC_TRACER_R0_INT_TRIG_STATE (0x00A3009C) +#define UMAC_TRACER_R0_INT_TRIG_STATE___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_INT_TRIG_STATE___POR 0x00000001 +#define UMAC_TRACER_R0_INT_TRIG_STATE__TRIGGER_STATE___POR 0x1 +#define UMAC_TRACER_R0_INT_TRIG_STATE__TRIGGER_STATE___M 0x00000007 +#define UMAC_TRACER_R0_INT_TRIG_STATE__TRIGGER_STATE___S 0 +#define UMAC_TRACER_R0_INT_TRIG_STATE___M 0x00000007 +#define UMAC_TRACER_R0_INT_TRIG_STATE___S 0 + +#define UMAC_TRACER_R0_INT_TRIG_PATTERN (0x00A300A0) +#define UMAC_TRACER_R0_INT_TRIG_PATTERN___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_INT_TRIG_PATTERN___POR 0x11111111 +#define UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_6___POR 0x1 +#define UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_5___POR 0x1 +#define UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_4___POR 0x1 +#define UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_3___POR 0x1 +#define UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_2___POR 0x1 +#define UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_1___POR 0x1 +#define UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_0___POR 0x1 +#define UMAC_TRACER_R0_INT_TRIG_PATTERN__NUM_TRANSITIONS___POR 0x1 +#define UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_6___M 0x70000000 +#define UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_6___S 28 +#define UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_5___M 0x07000000 +#define UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_5___S 24 +#define UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_4___M 0x00700000 +#define UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_4___S 20 +#define UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_3___M 0x00070000 +#define UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_3___S 16 +#define UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_2___M 0x00007000 +#define UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_2___S 12 +#define UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_1___M 0x00000700 +#define UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_1___S 8 +#define UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_0___M 0x00000070 +#define UMAC_TRACER_R0_INT_TRIG_PATTERN__STATE_0___S 4 +#define UMAC_TRACER_R0_INT_TRIG_PATTERN__NUM_TRANSITIONS___M 0x00000007 +#define UMAC_TRACER_R0_INT_TRIG_PATTERN__NUM_TRANSITIONS___S 0 +#define UMAC_TRACER_R0_INT_TRIG_PATTERN___M 0x77777777 +#define UMAC_TRACER_R0_INT_TRIG_PATTERN___S 0 + +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK (0x00A300A4) +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK___POR 0x00000000 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_WCMN_MISC_EVENT___POR 0x0 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_CXC_EVENT2___POR 0x0 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_CXC_EVENT1___POR 0x0 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_CXC_TRACEBUS___POR 0x0 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__WCMN_MISC_EVENT___POR 0x0 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CXC_EVENT2___POR 0x0 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CXC_EVENT1___POR 0x0 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CXC_TRACEBUS___POR 0x0 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_PHY2___POR 0x0 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_PHY1___POR 0x0 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_WMAC3___POR 0x0 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_WMAC2___POR 0x0 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_WMAC1___POR 0x0 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__PHY2___POR 0x0 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__PHY1___POR 0x0 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__WMAC3___POR 0x0 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__WMAC2___POR 0x0 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__WMAC1___POR 0x0 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_WCMN_MISC_EVENT___M 0x00020000 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_WCMN_MISC_EVENT___S 17 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_CXC_EVENT2___M 0x00010000 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_CXC_EVENT2___S 16 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_CXC_EVENT1___M 0x00008000 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_CXC_EVENT1___S 15 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_CXC_TRACEBUS___M 0x00004000 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_CXC_TRACEBUS___S 14 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__WCMN_MISC_EVENT___M 0x00002000 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__WCMN_MISC_EVENT___S 13 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CXC_EVENT2___M 0x00001000 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CXC_EVENT2___S 12 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CXC_EVENT1___M 0x00000800 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CXC_EVENT1___S 11 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CXC_TRACEBUS___M 0x00000400 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CXC_TRACEBUS___S 10 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_PHY2___M 0x00000200 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_PHY2___S 9 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_PHY1___M 0x00000100 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_PHY1___S 8 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_WMAC3___M 0x00000080 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_WMAC3___S 7 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_WMAC2___M 0x00000040 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_WMAC2___S 6 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_WMAC1___M 0x00000020 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__CLK_WMAC1___S 5 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__PHY2___M 0x00000010 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__PHY2___S 4 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__PHY1___M 0x00000008 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__PHY1___S 3 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__WMAC3___M 0x00000004 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__WMAC3___S 2 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__WMAC2___M 0x00000002 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__WMAC2___S 1 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__WMAC1___M 0x00000001 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK__WMAC1___S 0 +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK___M 0x0003FFFF +#define UMAC_TRACER_R0_ASYNC_ISYNC_FIFO_SOFTRESET_AND_CLK___S 0 + +#define UMAC_TRACER_R0_INTR_BITMASK (0x00A300A8) +#define UMAC_TRACER_R0_INTR_BITMASK___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_INTR_BITMASK___POR 0x00000000 +#define UMAC_TRACER_R0_INTR_BITMASK__APB_RD_INVALID_ADDR_P_BITMASK___POR 0x0 +#define UMAC_TRACER_R0_INTR_BITMASK__APB_WR_INVALID_ADDR_P_BITMASK___POR 0x0 +#define UMAC_TRACER_R0_INTR_BITMASK__APB_WR_TO_RD_ONLY_ADDR_P_BITMASK___POR 0x0 +#define UMAC_TRACER_R0_INTR_BITMASK__TRC_INTR_P___POR 0x0 +#define UMAC_TRACER_R0_INTR_BITMASK__APB_RD_INVALID_ADDR_P_BITMASK___M 0x00000008 +#define UMAC_TRACER_R0_INTR_BITMASK__APB_RD_INVALID_ADDR_P_BITMASK___S 3 +#define UMAC_TRACER_R0_INTR_BITMASK__APB_WR_INVALID_ADDR_P_BITMASK___M 0x00000004 +#define UMAC_TRACER_R0_INTR_BITMASK__APB_WR_INVALID_ADDR_P_BITMASK___S 2 +#define UMAC_TRACER_R0_INTR_BITMASK__APB_WR_TO_RD_ONLY_ADDR_P_BITMASK___M 0x00000002 +#define UMAC_TRACER_R0_INTR_BITMASK__APB_WR_TO_RD_ONLY_ADDR_P_BITMASK___S 1 +#define UMAC_TRACER_R0_INTR_BITMASK__TRC_INTR_P___M 0x00000001 +#define UMAC_TRACER_R0_INTR_BITMASK__TRC_INTR_P___S 0 +#define UMAC_TRACER_R0_INTR_BITMASK___M 0x0000000F +#define UMAC_TRACER_R0_INTR_BITMASK___S 0 + +#define UMAC_TRACER_R0_VID0 (0x00A300AC) +#define UMAC_TRACER_R0_VID0___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_VID0___POR 0x00000000 +#define UMAC_TRACER_R0_VID0__CXC2___POR 0x0 +#define UMAC_TRACER_R0_VID0__TCL___POR 0x0 +#define UMAC_TRACER_R0_VID0__WBM___POR 0x0 +#define UMAC_TRACER_R0_VID0__TQM___POR 0x0 +#define UMAC_TRACER_R0_VID0__REO___POR 0x0 +#define UMAC_TRACER_R0_VID0__CXC___POR 0x0 +#define UMAC_TRACER_R0_VID0__CE___POR 0x0 +#define UMAC_TRACER_R0_VID0__MODULE_EN___POR 0x0 +#define UMAC_TRACER_R0_VID0__CXC2___M 0xF0000000 +#define UMAC_TRACER_R0_VID0__CXC2___S 28 +#define UMAC_TRACER_R0_VID0__TCL___M 0x0F000000 +#define UMAC_TRACER_R0_VID0__TCL___S 24 +#define UMAC_TRACER_R0_VID0__WBM___M 0x00F00000 +#define UMAC_TRACER_R0_VID0__WBM___S 20 +#define UMAC_TRACER_R0_VID0__TQM___M 0x000F0000 +#define UMAC_TRACER_R0_VID0__TQM___S 16 +#define UMAC_TRACER_R0_VID0__REO___M 0x0000F000 +#define UMAC_TRACER_R0_VID0__REO___S 12 +#define UMAC_TRACER_R0_VID0__CXC___M 0x00000F00 +#define UMAC_TRACER_R0_VID0__CXC___S 8 +#define UMAC_TRACER_R0_VID0__CE___M 0x000000F0 +#define UMAC_TRACER_R0_VID0__CE___S 4 +#define UMAC_TRACER_R0_VID0__MODULE_EN___M 0x00000001 +#define UMAC_TRACER_R0_VID0__MODULE_EN___S 0 +#define UMAC_TRACER_R0_VID0___M 0xFFFFFFF1 +#define UMAC_TRACER_R0_VID0___S 0 + +#define UMAC_TRACER_R0_VID0_EXT (0x00A300B0) +#define UMAC_TRACER_R0_VID0_EXT___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_VID0_EXT___POR 0x00000000 +#define UMAC_TRACER_R0_VID0_EXT__PHY_B___POR 0x0 +#define UMAC_TRACER_R0_VID0_EXT__PHY_A___POR 0x0 +#define UMAC_TRACER_R0_VID0_EXT__TQM2___POR 0x0 +#define UMAC_TRACER_R0_VID0_EXT__REO2___POR 0x0 +#define UMAC_TRACER_R0_VID0_EXT__WBM2___POR 0x0 +#define UMAC_TRACER_R0_VID0_EXT__TCL_1___POR 0x0 +#define UMAC_TRACER_R0_VID0_EXT__PHY_B___M 0x00F00000 +#define UMAC_TRACER_R0_VID0_EXT__PHY_B___S 20 +#define UMAC_TRACER_R0_VID0_EXT__PHY_A___M 0x000F0000 +#define UMAC_TRACER_R0_VID0_EXT__PHY_A___S 16 +#define UMAC_TRACER_R0_VID0_EXT__TQM2___M 0x0000F000 +#define UMAC_TRACER_R0_VID0_EXT__TQM2___S 12 +#define UMAC_TRACER_R0_VID0_EXT__REO2___M 0x00000F00 +#define UMAC_TRACER_R0_VID0_EXT__REO2___S 8 +#define UMAC_TRACER_R0_VID0_EXT__WBM2___M 0x000000F0 +#define UMAC_TRACER_R0_VID0_EXT__WBM2___S 4 +#define UMAC_TRACER_R0_VID0_EXT__TCL_1___M 0x0000000F +#define UMAC_TRACER_R0_VID0_EXT__TCL_1___S 0 +#define UMAC_TRACER_R0_VID0_EXT___M 0x00FFFFFF +#define UMAC_TRACER_R0_VID0_EXT___S 0 + +#define UMAC_TRACER_R0_INTR_STATUS (0x00A300B4) +#define UMAC_TRACER_R0_INTR_STATUS___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_INTR_STATUS___POR 0x00000000 +#define UMAC_TRACER_R0_INTR_STATUS__APB_RD_INVALID_ADDR_P_STATUS___POR 0x0 +#define UMAC_TRACER_R0_INTR_STATUS__APB_WR_INVALID_ADDR_P_STATUS___POR 0x0 +#define UMAC_TRACER_R0_INTR_STATUS__APB_WR_TO_RD_ONLY_ADDR_P_STATUS___POR 0x0 +#define UMAC_TRACER_R0_INTR_STATUS__TRC_INTR_P_STATUS___POR 0x0 +#define UMAC_TRACER_R0_INTR_STATUS__APB_RD_INVALID_ADDR_P_STATUS___M 0x00000008 +#define UMAC_TRACER_R0_INTR_STATUS__APB_RD_INVALID_ADDR_P_STATUS___S 3 +#define UMAC_TRACER_R0_INTR_STATUS__APB_WR_INVALID_ADDR_P_STATUS___M 0x00000004 +#define UMAC_TRACER_R0_INTR_STATUS__APB_WR_INVALID_ADDR_P_STATUS___S 2 +#define UMAC_TRACER_R0_INTR_STATUS__APB_WR_TO_RD_ONLY_ADDR_P_STATUS___M 0x00000002 +#define UMAC_TRACER_R0_INTR_STATUS__APB_WR_TO_RD_ONLY_ADDR_P_STATUS___S 1 +#define UMAC_TRACER_R0_INTR_STATUS__TRC_INTR_P_STATUS___M 0x00000001 +#define UMAC_TRACER_R0_INTR_STATUS__TRC_INTR_P_STATUS___S 0 +#define UMAC_TRACER_R0_INTR_STATUS___M 0x0000000F +#define UMAC_TRACER_R0_INTR_STATUS___S 0 + +#define UMAC_TRACER_R0_STM_EVENTS_SEL (0x00A300B8) +#define UMAC_TRACER_R0_STM_EVENTS_SEL___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_STM_EVENTS_SEL___POR 0x00000000 +#define UMAC_TRACER_R0_STM_EVENTS_SEL__TBD___POR 0x00 +#define UMAC_TRACER_R0_STM_EVENTS_SEL__PCSS_DSB_DATA_SEL___POR 0x0 +#define UMAC_TRACER_R0_STM_EVENTS_SEL__VAL___POR 0x0000000 +#define UMAC_TRACER_R0_STM_EVENTS_SEL__TBD___M 0xFC000000 +#define UMAC_TRACER_R0_STM_EVENTS_SEL__TBD___S 26 +#define UMAC_TRACER_R0_STM_EVENTS_SEL__PCSS_DSB_DATA_SEL___M 0x02000000 +#define UMAC_TRACER_R0_STM_EVENTS_SEL__PCSS_DSB_DATA_SEL___S 25 +#define UMAC_TRACER_R0_STM_EVENTS_SEL__VAL___M 0x01FFFFFF +#define UMAC_TRACER_R0_STM_EVENTS_SEL__VAL___S 0 +#define UMAC_TRACER_R0_STM_EVENTS_SEL___M 0xFFFFFFFF +#define UMAC_TRACER_R0_STM_EVENTS_SEL___S 0 + +#define UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL (0x00A300BC) +#define UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL___POR 0x00000000 +#define UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__TRIGGER_STATUS___POR 0x0 +#define UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__TRIGGER_GEN_ENABLE___POR 0x0 +#define UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__RESV_B___POR 0x0 +#define UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__DESTINATION_STATE___POR 0x0 +#define UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__RESV_A___POR 0x0 +#define UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__SOURCE_STATE___POR 0x0 +#define UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__TRIGGER_STATUS___M 0x00000200 +#define UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__TRIGGER_STATUS___S 9 +#define UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__TRIGGER_GEN_ENABLE___M 0x00000100 +#define UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__TRIGGER_GEN_ENABLE___S 8 +#define UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__RESV_B___M 0x00000080 +#define UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__RESV_B___S 7 +#define UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__DESTINATION_STATE___M 0x00000070 +#define UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__DESTINATION_STATE___S 4 +#define UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__RESV_A___M 0x00000008 +#define UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__RESV_A___S 3 +#define UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__SOURCE_STATE___M 0x00000007 +#define UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL__SOURCE_STATE___S 0 +#define UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL___M 0x000003FF +#define UMAC_TRACER_R0_TRIGGER_TO_SMH_GEN_CONTROL___S 0 + +#define UMAC_TRACER_R0_TRIGGER_TO_QDSS_GEN_CONTROL (0x00A300C0) +#define UMAC_TRACER_R0_TRIGGER_TO_QDSS_GEN_CONTROL___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_TRIGGER_TO_QDSS_GEN_CONTROL___POR 0x00000000 +#define UMAC_TRACER_R0_TRIGGER_TO_QDSS_GEN_CONTROL__QDSS_TRIGGER_ENABLE___POR 0x00 +#define UMAC_TRACER_R0_TRIGGER_TO_QDSS_GEN_CONTROL__QDSS_TRIGGER_ENABLE___M 0x0000001F +#define UMAC_TRACER_R0_TRIGGER_TO_QDSS_GEN_CONTROL__QDSS_TRIGGER_ENABLE___S 0 +#define UMAC_TRACER_R0_TRIGGER_TO_QDSS_GEN_CONTROL___M 0x0000001F +#define UMAC_TRACER_R0_TRIGGER_TO_QDSS_GEN_CONTROL___S 0 + +#define UMAC_TRACER_R0_TRIGGER_TO_WMAC1_RRI_GEN_CONTROL (0x00A300C4) +#define UMAC_TRACER_R0_TRIGGER_TO_WMAC1_RRI_GEN_CONTROL___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_TRIGGER_TO_WMAC1_RRI_GEN_CONTROL___POR 0x00000000 +#define UMAC_TRACER_R0_TRIGGER_TO_WMAC1_RRI_GEN_CONTROL__TRIGGER_SEL___POR 0x0 +#define UMAC_TRACER_R0_TRIGGER_TO_WMAC1_RRI_GEN_CONTROL__TRIGGER_ENABLE___POR 0x0 +#define UMAC_TRACER_R0_TRIGGER_TO_WMAC1_RRI_GEN_CONTROL__TRIGGER_SEL___M 0x0000000E +#define UMAC_TRACER_R0_TRIGGER_TO_WMAC1_RRI_GEN_CONTROL__TRIGGER_SEL___S 1 +#define UMAC_TRACER_R0_TRIGGER_TO_WMAC1_RRI_GEN_CONTROL__TRIGGER_ENABLE___M 0x00000001 +#define UMAC_TRACER_R0_TRIGGER_TO_WMAC1_RRI_GEN_CONTROL__TRIGGER_ENABLE___S 0 +#define UMAC_TRACER_R0_TRIGGER_TO_WMAC1_RRI_GEN_CONTROL___M 0x0000000F +#define UMAC_TRACER_R0_TRIGGER_TO_WMAC1_RRI_GEN_CONTROL___S 0 + +#define UMAC_TRACER_R0_TRIGGER_TO_WMAC2_RRI_GEN_CONTROL (0x00A300C8) +#define UMAC_TRACER_R0_TRIGGER_TO_WMAC2_RRI_GEN_CONTROL___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_TRIGGER_TO_WMAC2_RRI_GEN_CONTROL___POR 0x00000000 +#define UMAC_TRACER_R0_TRIGGER_TO_WMAC2_RRI_GEN_CONTROL__TRIGGER_SEL___POR 0x0 +#define UMAC_TRACER_R0_TRIGGER_TO_WMAC2_RRI_GEN_CONTROL__TRIGGER_ENABLE___POR 0x0 +#define UMAC_TRACER_R0_TRIGGER_TO_WMAC2_RRI_GEN_CONTROL__TRIGGER_SEL___M 0x0000000E +#define UMAC_TRACER_R0_TRIGGER_TO_WMAC2_RRI_GEN_CONTROL__TRIGGER_SEL___S 1 +#define UMAC_TRACER_R0_TRIGGER_TO_WMAC2_RRI_GEN_CONTROL__TRIGGER_ENABLE___M 0x00000001 +#define UMAC_TRACER_R0_TRIGGER_TO_WMAC2_RRI_GEN_CONTROL__TRIGGER_ENABLE___S 0 +#define UMAC_TRACER_R0_TRIGGER_TO_WMAC2_RRI_GEN_CONTROL___M 0x0000000F +#define UMAC_TRACER_R0_TRIGGER_TO_WMAC2_RRI_GEN_CONTROL___S 0 + +#define UMAC_TRACER_R0_TRIGGER_TO_WMAC3_RRI_GEN_CONTROL (0x00A300CC) +#define UMAC_TRACER_R0_TRIGGER_TO_WMAC3_RRI_GEN_CONTROL___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_TRIGGER_TO_WMAC3_RRI_GEN_CONTROL___POR 0x00000000 +#define UMAC_TRACER_R0_TRIGGER_TO_WMAC3_RRI_GEN_CONTROL__TRIGGER_SEL___POR 0x0 +#define UMAC_TRACER_R0_TRIGGER_TO_WMAC3_RRI_GEN_CONTROL__TRIGGER_ENABLE___POR 0x0 +#define UMAC_TRACER_R0_TRIGGER_TO_WMAC3_RRI_GEN_CONTROL__TRIGGER_SEL___M 0x0000000E +#define UMAC_TRACER_R0_TRIGGER_TO_WMAC3_RRI_GEN_CONTROL__TRIGGER_SEL___S 1 +#define UMAC_TRACER_R0_TRIGGER_TO_WMAC3_RRI_GEN_CONTROL__TRIGGER_ENABLE___M 0x00000001 +#define UMAC_TRACER_R0_TRIGGER_TO_WMAC3_RRI_GEN_CONTROL__TRIGGER_ENABLE___S 0 +#define UMAC_TRACER_R0_TRIGGER_TO_WMAC3_RRI_GEN_CONTROL___M 0x0000000F +#define UMAC_TRACER_R0_TRIGGER_TO_WMAC3_RRI_GEN_CONTROL___S 0 + +#define UMAC_TRACER_R0_CLK_TESTBUS_OUT (0x00A300D0) +#define UMAC_TRACER_R0_CLK_TESTBUS_OUT___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_CLK_TESTBUS_OUT___POR 0x00000000 +#define UMAC_TRACER_R0_CLK_TESTBUS_OUT__ENABLE___POR 0x0 +#define UMAC_TRACER_R0_CLK_TESTBUS_OUT__ENABLE___M 0x00000001 +#define UMAC_TRACER_R0_CLK_TESTBUS_OUT__ENABLE___S 0 +#define UMAC_TRACER_R0_CLK_TESTBUS_OUT___M 0x00000001 +#define UMAC_TRACER_R0_CLK_TESTBUS_OUT___S 0 + +#define UMAC_TRACER_R0_SS_ID (0x00A300D4) +#define UMAC_TRACER_R0_SS_ID___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_SS_ID___POR 0x00039E40 +#define UMAC_TRACER_R0_SS_ID__TIMESTAMP_MODE___POR 0x0 +#define UMAC_TRACER_R0_SS_ID__WCMN_MISC___POR 0x0 +#define UMAC_TRACER_R0_SS_ID__UMAC_DBG___POR 0x3 +#define UMAC_TRACER_R0_SS_ID__PHY2___POR 0x2 +#define UMAC_TRACER_R0_SS_ID__PHY1___POR 0x1 +#define UMAC_TRACER_R0_SS_ID__UMAC___POR 0x3 +#define UMAC_TRACER_R0_SS_ID__LMAC3___POR 0x2 +#define UMAC_TRACER_R0_SS_ID__LMAC2___POR 0x1 +#define UMAC_TRACER_R0_SS_ID__LMAC1___POR 0x0 +#define UMAC_TRACER_R0_SS_ID__ENABLE___POR 0x0 +#define UMAC_TRACER_R0_SS_ID__TIMESTAMP_MODE___M 0x00100000 +#define UMAC_TRACER_R0_SS_ID__TIMESTAMP_MODE___S 20 +#define UMAC_TRACER_R0_SS_ID__WCMN_MISC___M 0x000C0000 +#define UMAC_TRACER_R0_SS_ID__WCMN_MISC___S 18 +#define UMAC_TRACER_R0_SS_ID__UMAC_DBG___M 0x00030000 +#define UMAC_TRACER_R0_SS_ID__UMAC_DBG___S 16 +#define UMAC_TRACER_R0_SS_ID__PHY2___M 0x0000C000 +#define UMAC_TRACER_R0_SS_ID__PHY2___S 14 +#define UMAC_TRACER_R0_SS_ID__PHY1___M 0x00003000 +#define UMAC_TRACER_R0_SS_ID__PHY1___S 12 +#define UMAC_TRACER_R0_SS_ID__UMAC___M 0x00000C00 +#define UMAC_TRACER_R0_SS_ID__UMAC___S 10 +#define UMAC_TRACER_R0_SS_ID__LMAC3___M 0x00000300 +#define UMAC_TRACER_R0_SS_ID__LMAC3___S 8 +#define UMAC_TRACER_R0_SS_ID__LMAC2___M 0x000000C0 +#define UMAC_TRACER_R0_SS_ID__LMAC2___S 6 +#define UMAC_TRACER_R0_SS_ID__LMAC1___M 0x00000030 +#define UMAC_TRACER_R0_SS_ID__LMAC1___S 4 +#define UMAC_TRACER_R0_SS_ID__ENABLE___M 0x00000001 +#define UMAC_TRACER_R0_SS_ID__ENABLE___S 0 +#define UMAC_TRACER_R0_SS_ID___M 0x001FFFF1 +#define UMAC_TRACER_R0_SS_ID___S 0 + +#define UMAC_TRACER_R0_SPARE_BIT (0x00A300D8) +#define UMAC_TRACER_R0_SPARE_BIT___RWC QCSR_REG_RW +#define UMAC_TRACER_R0_SPARE_BIT___POR 0x00000000 +#define UMAC_TRACER_R0_SPARE_BIT__ENABLE___POR 0x0000 +#define UMAC_TRACER_R0_SPARE_BIT__ENABLE___M 0x0000FFFF +#define UMAC_TRACER_R0_SPARE_BIT__ENABLE___S 0 +#define UMAC_TRACER_R0_SPARE_BIT___M 0x0000FFFF +#define UMAC_TRACER_R0_SPARE_BIT___S 0 + +#define UMAC_WBM_R0_GENERAL_ENABLE (0x00A34000) +#define UMAC_WBM_R0_GENERAL_ENABLE___RWC QCSR_REG_RW +#define UMAC_WBM_R0_GENERAL_ENABLE___POR 0x00000060 +#define UMAC_WBM_R0_GENERAL_ENABLE__LINK_DESC_CONTENT_CLEAR_ENABLE___POR 0x0 +#define UMAC_WBM_R0_GENERAL_ENABLE__LINK_DESC_BYPASS_DISABLE___POR 0x1 +#define UMAC_WBM_R0_GENERAL_ENABLE__MSDU_BUFFER_BYPASS_DISABLE___POR 0x1 +#define UMAC_WBM_R0_GENERAL_ENABLE__RELEASE_FUNCTION_ENABLE___POR 0x0 +#define UMAC_WBM_R0_GENERAL_ENABLE__LINK_IDLE_LIST_CONSUMER_ENABLE___POR 0x0 +#define UMAC_WBM_R0_GENERAL_ENABLE__LINK_IDLE_LIST_PRODUCER_ENABLE___POR 0x0 +#define UMAC_WBM_R0_GENERAL_ENABLE__BUFFER_IDLE_LIST_CONSUMER_ENABLE___POR 0x0 +#define UMAC_WBM_R0_GENERAL_ENABLE__BUFFER_IDLE_LIST_PRODUCER_ENABLE___POR 0x0 +#define UMAC_WBM_R0_GENERAL_ENABLE__LINK_DESC_CONTENT_CLEAR_ENABLE___M 0x00000080 +#define UMAC_WBM_R0_GENERAL_ENABLE__LINK_DESC_CONTENT_CLEAR_ENABLE___S 7 +#define UMAC_WBM_R0_GENERAL_ENABLE__LINK_DESC_BYPASS_DISABLE___M 0x00000040 +#define UMAC_WBM_R0_GENERAL_ENABLE__LINK_DESC_BYPASS_DISABLE___S 6 +#define UMAC_WBM_R0_GENERAL_ENABLE__MSDU_BUFFER_BYPASS_DISABLE___M 0x00000020 +#define UMAC_WBM_R0_GENERAL_ENABLE__MSDU_BUFFER_BYPASS_DISABLE___S 5 +#define UMAC_WBM_R0_GENERAL_ENABLE__RELEASE_FUNCTION_ENABLE___M 0x00000010 +#define UMAC_WBM_R0_GENERAL_ENABLE__RELEASE_FUNCTION_ENABLE___S 4 +#define UMAC_WBM_R0_GENERAL_ENABLE__LINK_IDLE_LIST_CONSUMER_ENABLE___M 0x00000008 +#define UMAC_WBM_R0_GENERAL_ENABLE__LINK_IDLE_LIST_CONSUMER_ENABLE___S 3 +#define UMAC_WBM_R0_GENERAL_ENABLE__LINK_IDLE_LIST_PRODUCER_ENABLE___M 0x00000004 +#define UMAC_WBM_R0_GENERAL_ENABLE__LINK_IDLE_LIST_PRODUCER_ENABLE___S 2 +#define UMAC_WBM_R0_GENERAL_ENABLE__BUFFER_IDLE_LIST_CONSUMER_ENABLE___M 0x00000002 +#define UMAC_WBM_R0_GENERAL_ENABLE__BUFFER_IDLE_LIST_CONSUMER_ENABLE___S 1 +#define UMAC_WBM_R0_GENERAL_ENABLE__BUFFER_IDLE_LIST_PRODUCER_ENABLE___M 0x00000001 +#define UMAC_WBM_R0_GENERAL_ENABLE__BUFFER_IDLE_LIST_PRODUCER_ENABLE___S 0 +#define UMAC_WBM_R0_GENERAL_ENABLE___M 0x000000FF +#define UMAC_WBM_R0_GENERAL_ENABLE___S 0 + +#define UMAC_WBM_R0_RELEASE_RING_ENABLE (0x00A34004) +#define UMAC_WBM_R0_RELEASE_RING_ENABLE___RWC QCSR_REG_RW +#define UMAC_WBM_R0_RELEASE_RING_ENABLE___POR 0x00000000 +#define UMAC_WBM_R0_RELEASE_RING_ENABLE__RXDMA2_RELEASE_RING_ENABLE___POR 0x0 +#define UMAC_WBM_R0_RELEASE_RING_ENABLE__RXDMA1_RELEASE_RING_ENABLE___POR 0x0 +#define UMAC_WBM_R0_RELEASE_RING_ENABLE__RXDMA0_RELEASE_RING_ENABLE___POR 0x0 +#define UMAC_WBM_R0_RELEASE_RING_ENABLE__FW_RELEASE_RING_ENABLE___POR 0x0 +#define UMAC_WBM_R0_RELEASE_RING_ENABLE__SW_RELEASE_RING_ENABLE___POR 0x0 +#define UMAC_WBM_R0_RELEASE_RING_ENABLE__REO_RELEASE_RING_ENABLE___POR 0x0 +#define UMAC_WBM_R0_RELEASE_RING_ENABLE__TQM_RELEASE_RING_ENABLE___POR 0x0 +#define UMAC_WBM_R0_RELEASE_RING_ENABLE__PPE_RELEASE_RING_ENABLE___POR 0x0 +#define UMAC_WBM_R0_RELEASE_RING_ENABLE__RXDMA2_RELEASE_RING_ENABLE___M 0x00000080 +#define UMAC_WBM_R0_RELEASE_RING_ENABLE__RXDMA2_RELEASE_RING_ENABLE___S 7 +#define UMAC_WBM_R0_RELEASE_RING_ENABLE__RXDMA1_RELEASE_RING_ENABLE___M 0x00000040 +#define UMAC_WBM_R0_RELEASE_RING_ENABLE__RXDMA1_RELEASE_RING_ENABLE___S 6 +#define UMAC_WBM_R0_RELEASE_RING_ENABLE__RXDMA0_RELEASE_RING_ENABLE___M 0x00000020 +#define UMAC_WBM_R0_RELEASE_RING_ENABLE__RXDMA0_RELEASE_RING_ENABLE___S 5 +#define UMAC_WBM_R0_RELEASE_RING_ENABLE__FW_RELEASE_RING_ENABLE___M 0x00000010 +#define UMAC_WBM_R0_RELEASE_RING_ENABLE__FW_RELEASE_RING_ENABLE___S 4 +#define UMAC_WBM_R0_RELEASE_RING_ENABLE__SW_RELEASE_RING_ENABLE___M 0x00000008 +#define UMAC_WBM_R0_RELEASE_RING_ENABLE__SW_RELEASE_RING_ENABLE___S 3 +#define UMAC_WBM_R0_RELEASE_RING_ENABLE__REO_RELEASE_RING_ENABLE___M 0x00000004 +#define UMAC_WBM_R0_RELEASE_RING_ENABLE__REO_RELEASE_RING_ENABLE___S 2 +#define UMAC_WBM_R0_RELEASE_RING_ENABLE__TQM_RELEASE_RING_ENABLE___M 0x00000002 +#define UMAC_WBM_R0_RELEASE_RING_ENABLE__TQM_RELEASE_RING_ENABLE___S 1 +#define UMAC_WBM_R0_RELEASE_RING_ENABLE__PPE_RELEASE_RING_ENABLE___M 0x00000001 +#define UMAC_WBM_R0_RELEASE_RING_ENABLE__PPE_RELEASE_RING_ENABLE___S 0 +#define UMAC_WBM_R0_RELEASE_RING_ENABLE___M 0x000000FF +#define UMAC_WBM_R0_RELEASE_RING_ENABLE___S 0 + +#define UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE (0x00A34008) +#define UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE___RWC QCSR_REG_RW +#define UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE___POR 0x00000000 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2RXDMA2_BUF_RING_ENABLE___POR 0x0 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2RXDMA1_BUF_RING_ENABLE___POR 0x0 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2RXDMA0_BUF_RING_ENABLE___POR 0x0 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2FW_BUF_RING_ENABLE___POR 0x0 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2SW_BUF_RING_ENABLE___POR 0x0 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2PPE_BUF_RING_ENABLE___POR 0x0 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2RXDMA2_BUF_RING_ENABLE___M 0x00000020 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2RXDMA2_BUF_RING_ENABLE___S 5 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2RXDMA1_BUF_RING_ENABLE___M 0x00000010 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2RXDMA1_BUF_RING_ENABLE___S 4 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2RXDMA0_BUF_RING_ENABLE___M 0x00000008 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2RXDMA0_BUF_RING_ENABLE___S 3 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2FW_BUF_RING_ENABLE___M 0x00000004 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2FW_BUF_RING_ENABLE___S 2 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2SW_BUF_RING_ENABLE___M 0x00000002 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2SW_BUF_RING_ENABLE___S 1 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2PPE_BUF_RING_ENABLE___M 0x00000001 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE__WBM2PPE_BUF_RING_ENABLE___S 0 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE___M 0x0000003F +#define UMAC_WBM_R0_MSDU_BUFFER_RING_ENABLE___S 0 + +#define UMAC_WBM_R0_LINK_DESC_RING_ENABLE (0x00A3400C) +#define UMAC_WBM_R0_LINK_DESC_RING_ENABLE___RWC QCSR_REG_RW +#define UMAC_WBM_R0_LINK_DESC_RING_ENABLE___POR 0x00000000 +#define UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2RXDMA2_LINK_RING_ENABLE___POR 0x0 +#define UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2RXDMA1_LINK_RING_ENABLE___POR 0x0 +#define UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2RXDMA0_LINK_RING_ENABLE___POR 0x0 +#define UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2FW_LINK_RING_ENABLE___POR 0x0 +#define UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2SW_LINK_RING_ENABLE___POR 0x0 +#define UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2REO_LINK_RING_ENABLE___POR 0x0 +#define UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2TQM_LINK_RING_ENABLE___POR 0x0 +#define UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2RXDMA2_LINK_RING_ENABLE___M 0x00000040 +#define UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2RXDMA2_LINK_RING_ENABLE___S 6 +#define UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2RXDMA1_LINK_RING_ENABLE___M 0x00000020 +#define UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2RXDMA1_LINK_RING_ENABLE___S 5 +#define UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2RXDMA0_LINK_RING_ENABLE___M 0x00000010 +#define UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2RXDMA0_LINK_RING_ENABLE___S 4 +#define UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2FW_LINK_RING_ENABLE___M 0x00000008 +#define UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2FW_LINK_RING_ENABLE___S 3 +#define UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2SW_LINK_RING_ENABLE___M 0x00000004 +#define UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2SW_LINK_RING_ENABLE___S 2 +#define UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2REO_LINK_RING_ENABLE___M 0x00000002 +#define UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2REO_LINK_RING_ENABLE___S 1 +#define UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2TQM_LINK_RING_ENABLE___M 0x00000001 +#define UMAC_WBM_R0_LINK_DESC_RING_ENABLE__WBM2TQM_LINK_RING_ENABLE___S 0 +#define UMAC_WBM_R0_LINK_DESC_RING_ENABLE___M 0x0000007F +#define UMAC_WBM_R0_LINK_DESC_RING_ENABLE___S 0 + +#define UMAC_WBM_R0_MISC_RING_ENABLE (0x00A34010) +#define UMAC_WBM_R0_MISC_RING_ENABLE___RWC QCSR_REG_RW +#define UMAC_WBM_R0_MISC_RING_ENABLE___POR 0x0000003F +#define UMAC_WBM_R0_MISC_RING_ENABLE__WBM2SW4_RELEASE_RING_ENABLE___POR 0x1 +#define UMAC_WBM_R0_MISC_RING_ENABLE__WBM2SW3_RELEASE_RING_ENABLE___POR 0x1 +#define UMAC_WBM_R0_MISC_RING_ENABLE__WBM2SW2_RELEASE_RING_ENABLE___POR 0x1 +#define UMAC_WBM_R0_MISC_RING_ENABLE__WBM2SW1_RELEASE_RING_ENABLE___POR 0x1 +#define UMAC_WBM_R0_MISC_RING_ENABLE__WBM2SW0_RELEASE_RING_ENABLE___POR 0x1 +#define UMAC_WBM_R0_MISC_RING_ENABLE__WBM2FW_RELEASE_RING_ENABLE___POR 0x1 +#define UMAC_WBM_R0_MISC_RING_ENABLE__WBM2SW4_RELEASE_RING_ENABLE___M 0x00000020 +#define UMAC_WBM_R0_MISC_RING_ENABLE__WBM2SW4_RELEASE_RING_ENABLE___S 5 +#define UMAC_WBM_R0_MISC_RING_ENABLE__WBM2SW3_RELEASE_RING_ENABLE___M 0x00000010 +#define UMAC_WBM_R0_MISC_RING_ENABLE__WBM2SW3_RELEASE_RING_ENABLE___S 4 +#define UMAC_WBM_R0_MISC_RING_ENABLE__WBM2SW2_RELEASE_RING_ENABLE___M 0x00000008 +#define UMAC_WBM_R0_MISC_RING_ENABLE__WBM2SW2_RELEASE_RING_ENABLE___S 3 +#define UMAC_WBM_R0_MISC_RING_ENABLE__WBM2SW1_RELEASE_RING_ENABLE___M 0x00000004 +#define UMAC_WBM_R0_MISC_RING_ENABLE__WBM2SW1_RELEASE_RING_ENABLE___S 2 +#define UMAC_WBM_R0_MISC_RING_ENABLE__WBM2SW0_RELEASE_RING_ENABLE___M 0x00000002 +#define UMAC_WBM_R0_MISC_RING_ENABLE__WBM2SW0_RELEASE_RING_ENABLE___S 1 +#define UMAC_WBM_R0_MISC_RING_ENABLE__WBM2FW_RELEASE_RING_ENABLE___M 0x00000001 +#define UMAC_WBM_R0_MISC_RING_ENABLE__WBM2FW_RELEASE_RING_ENABLE___S 0 +#define UMAC_WBM_R0_MISC_RING_ENABLE___M 0x0000003F +#define UMAC_WBM_R0_MISC_RING_ENABLE___S 0 + +#define UMAC_WBM_R0_RELEASE_RING_STATUS (0x00A34014) +#define UMAC_WBM_R0_RELEASE_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_RELEASE_RING_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_RELEASE_RING_STATUS__RXDMA2_RELEASE_RING_NOT_IDLE___POR 0x0 +#define UMAC_WBM_R0_RELEASE_RING_STATUS__RXDMA1_RELEASE_RING_NOT_IDLE___POR 0x0 +#define UMAC_WBM_R0_RELEASE_RING_STATUS__RXDMA0_RELEASE_RING_NOT_IDLE___POR 0x0 +#define UMAC_WBM_R0_RELEASE_RING_STATUS__FW_RELEASE_RING_NOT_IDLE___POR 0x0 +#define UMAC_WBM_R0_RELEASE_RING_STATUS__SW_RELEASE_RING_NOT_IDLE___POR 0x0 +#define UMAC_WBM_R0_RELEASE_RING_STATUS__REO_RELEASE_RING_NOT_IDLE___POR 0x0 +#define UMAC_WBM_R0_RELEASE_RING_STATUS__TQM_RELEASE_RING_NOT_IDLE___POR 0x0 +#define UMAC_WBM_R0_RELEASE_RING_STATUS__PPE_RELEASE_RING_NOT_IDLE___POR 0x0 +#define UMAC_WBM_R0_RELEASE_RING_STATUS__RXDMA2_RELEASE_RING_NOT_IDLE___M 0x00000080 +#define UMAC_WBM_R0_RELEASE_RING_STATUS__RXDMA2_RELEASE_RING_NOT_IDLE___S 7 +#define UMAC_WBM_R0_RELEASE_RING_STATUS__RXDMA1_RELEASE_RING_NOT_IDLE___M 0x00000040 +#define UMAC_WBM_R0_RELEASE_RING_STATUS__RXDMA1_RELEASE_RING_NOT_IDLE___S 6 +#define UMAC_WBM_R0_RELEASE_RING_STATUS__RXDMA0_RELEASE_RING_NOT_IDLE___M 0x00000020 +#define UMAC_WBM_R0_RELEASE_RING_STATUS__RXDMA0_RELEASE_RING_NOT_IDLE___S 5 +#define UMAC_WBM_R0_RELEASE_RING_STATUS__FW_RELEASE_RING_NOT_IDLE___M 0x00000010 +#define UMAC_WBM_R0_RELEASE_RING_STATUS__FW_RELEASE_RING_NOT_IDLE___S 4 +#define UMAC_WBM_R0_RELEASE_RING_STATUS__SW_RELEASE_RING_NOT_IDLE___M 0x00000008 +#define UMAC_WBM_R0_RELEASE_RING_STATUS__SW_RELEASE_RING_NOT_IDLE___S 3 +#define UMAC_WBM_R0_RELEASE_RING_STATUS__REO_RELEASE_RING_NOT_IDLE___M 0x00000004 +#define UMAC_WBM_R0_RELEASE_RING_STATUS__REO_RELEASE_RING_NOT_IDLE___S 2 +#define UMAC_WBM_R0_RELEASE_RING_STATUS__TQM_RELEASE_RING_NOT_IDLE___M 0x00000002 +#define UMAC_WBM_R0_RELEASE_RING_STATUS__TQM_RELEASE_RING_NOT_IDLE___S 1 +#define UMAC_WBM_R0_RELEASE_RING_STATUS__PPE_RELEASE_RING_NOT_IDLE___M 0x00000001 +#define UMAC_WBM_R0_RELEASE_RING_STATUS__PPE_RELEASE_RING_NOT_IDLE___S 0 +#define UMAC_WBM_R0_RELEASE_RING_STATUS___M 0x000000FF +#define UMAC_WBM_R0_RELEASE_RING_STATUS___S 0 + +#define UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS (0x00A34018) +#define UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2RXDMA2_BUF_RING_NOT_IDLE___POR 0x0 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2RXDMA1_BUF_RING_NOT_IDLE___POR 0x0 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2RXDMA0_BUF_RING_NOT_IDLE___POR 0x0 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2FW_BUF_RING_NOT_IDLE___POR 0x0 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2SW_BUF_RING_NOT_IDLE___POR 0x0 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2PPE_BUF_RING_NOT_IDLE___POR 0x0 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2RXDMA2_BUF_RING_NOT_IDLE___M 0x00000020 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2RXDMA2_BUF_RING_NOT_IDLE___S 5 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2RXDMA1_BUF_RING_NOT_IDLE___M 0x00000010 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2RXDMA1_BUF_RING_NOT_IDLE___S 4 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2RXDMA0_BUF_RING_NOT_IDLE___M 0x00000008 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2RXDMA0_BUF_RING_NOT_IDLE___S 3 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2FW_BUF_RING_NOT_IDLE___M 0x00000004 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2FW_BUF_RING_NOT_IDLE___S 2 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2SW_BUF_RING_NOT_IDLE___M 0x00000002 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2SW_BUF_RING_NOT_IDLE___S 1 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2PPE_BUF_RING_NOT_IDLE___M 0x00000001 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS__WBM2PPE_BUF_RING_NOT_IDLE___S 0 +#define UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS___M 0x0000003F +#define UMAC_WBM_R0_MSDU_BUFFER_RING_STATUS___S 0 + +#define UMAC_WBM_R0_LINK_DESC_RING_STATUS (0x00A3401C) +#define UMAC_WBM_R0_LINK_DESC_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_LINK_DESC_RING_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2RXDMA2_LINK_RING_NOT_IDLE___POR 0x0 +#define UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2RXDMA1_LINK_RING_NOT_IDLE___POR 0x0 +#define UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2RXDMA0_LINK_RING_NOT_IDLE___POR 0x0 +#define UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2FW_LINK_RING_NOT_IDLE___POR 0x0 +#define UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2SW_LINK_RING_NOT_IDLE___POR 0x0 +#define UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2REO_LINK_RING_NOT_IDLE___POR 0x0 +#define UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2TQM_LINK_RING_NOT_IDLE___POR 0x0 +#define UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2RXDMA2_LINK_RING_NOT_IDLE___M 0x00000040 +#define UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2RXDMA2_LINK_RING_NOT_IDLE___S 6 +#define UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2RXDMA1_LINK_RING_NOT_IDLE___M 0x00000020 +#define UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2RXDMA1_LINK_RING_NOT_IDLE___S 5 +#define UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2RXDMA0_LINK_RING_NOT_IDLE___M 0x00000010 +#define UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2RXDMA0_LINK_RING_NOT_IDLE___S 4 +#define UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2FW_LINK_RING_NOT_IDLE___M 0x00000008 +#define UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2FW_LINK_RING_NOT_IDLE___S 3 +#define UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2SW_LINK_RING_NOT_IDLE___M 0x00000004 +#define UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2SW_LINK_RING_NOT_IDLE___S 2 +#define UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2REO_LINK_RING_NOT_IDLE___M 0x00000002 +#define UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2REO_LINK_RING_NOT_IDLE___S 1 +#define UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2TQM_LINK_RING_NOT_IDLE___M 0x00000001 +#define UMAC_WBM_R0_LINK_DESC_RING_STATUS__WBM2TQM_LINK_RING_NOT_IDLE___S 0 +#define UMAC_WBM_R0_LINK_DESC_RING_STATUS___M 0x0000007F +#define UMAC_WBM_R0_LINK_DESC_RING_STATUS___S 0 + +#define UMAC_WBM_R0_MISC_RING_STATUS (0x00A34020) +#define UMAC_WBM_R0_MISC_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_MISC_RING_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_MISC_RING_STATUS__SW4_BUFFER_RING_NOT_IDLE___POR 0x0 +#define UMAC_WBM_R0_MISC_RING_STATUS__SW3_BUFFER_RING_NOT_IDLE___POR 0x0 +#define UMAC_WBM_R0_MISC_RING_STATUS__SW2_BUFFER_RING_NOT_IDLE___POR 0x0 +#define UMAC_WBM_R0_MISC_RING_STATUS__SW1_BUFFER_RING_NOT_IDLE___POR 0x0 +#define UMAC_WBM_R0_MISC_RING_STATUS__SW0_BUFFER_RING_NOT_IDLE___POR 0x0 +#define UMAC_WBM_R0_MISC_RING_STATUS__FW_BUFFER_RING_NOT_IDLE___POR 0x0 +#define UMAC_WBM_R0_MISC_RING_STATUS__LINK_IDLE_LIST_CONSUMER_NOT_IDLE___POR 0x0 +#define UMAC_WBM_R0_MISC_RING_STATUS__LINK_IDLE_LIST_PRODUCER_NOT_IDLE___POR 0x0 +#define UMAC_WBM_R0_MISC_RING_STATUS__BUFFER_IDLE_LIST_CONSUMER_NOT_IDLE___POR 0x0 +#define UMAC_WBM_R0_MISC_RING_STATUS__BUFFER_IDLE_LIST_PRODUCER_NOT_IDLE___POR 0x0 +#define UMAC_WBM_R0_MISC_RING_STATUS__SW4_BUFFER_RING_NOT_IDLE___M 0x00000200 +#define UMAC_WBM_R0_MISC_RING_STATUS__SW4_BUFFER_RING_NOT_IDLE___S 9 +#define UMAC_WBM_R0_MISC_RING_STATUS__SW3_BUFFER_RING_NOT_IDLE___M 0x00000100 +#define UMAC_WBM_R0_MISC_RING_STATUS__SW3_BUFFER_RING_NOT_IDLE___S 8 +#define UMAC_WBM_R0_MISC_RING_STATUS__SW2_BUFFER_RING_NOT_IDLE___M 0x00000080 +#define UMAC_WBM_R0_MISC_RING_STATUS__SW2_BUFFER_RING_NOT_IDLE___S 7 +#define UMAC_WBM_R0_MISC_RING_STATUS__SW1_BUFFER_RING_NOT_IDLE___M 0x00000040 +#define UMAC_WBM_R0_MISC_RING_STATUS__SW1_BUFFER_RING_NOT_IDLE___S 6 +#define UMAC_WBM_R0_MISC_RING_STATUS__SW0_BUFFER_RING_NOT_IDLE___M 0x00000020 +#define UMAC_WBM_R0_MISC_RING_STATUS__SW0_BUFFER_RING_NOT_IDLE___S 5 +#define UMAC_WBM_R0_MISC_RING_STATUS__FW_BUFFER_RING_NOT_IDLE___M 0x00000010 +#define UMAC_WBM_R0_MISC_RING_STATUS__FW_BUFFER_RING_NOT_IDLE___S 4 +#define UMAC_WBM_R0_MISC_RING_STATUS__LINK_IDLE_LIST_CONSUMER_NOT_IDLE___M 0x00000008 +#define UMAC_WBM_R0_MISC_RING_STATUS__LINK_IDLE_LIST_CONSUMER_NOT_IDLE___S 3 +#define UMAC_WBM_R0_MISC_RING_STATUS__LINK_IDLE_LIST_PRODUCER_NOT_IDLE___M 0x00000004 +#define UMAC_WBM_R0_MISC_RING_STATUS__LINK_IDLE_LIST_PRODUCER_NOT_IDLE___S 2 +#define UMAC_WBM_R0_MISC_RING_STATUS__BUFFER_IDLE_LIST_CONSUMER_NOT_IDLE___M 0x00000002 +#define UMAC_WBM_R0_MISC_RING_STATUS__BUFFER_IDLE_LIST_CONSUMER_NOT_IDLE___S 1 +#define UMAC_WBM_R0_MISC_RING_STATUS__BUFFER_IDLE_LIST_PRODUCER_NOT_IDLE___M 0x00000001 +#define UMAC_WBM_R0_MISC_RING_STATUS__BUFFER_IDLE_LIST_PRODUCER_NOT_IDLE___S 0 +#define UMAC_WBM_R0_MISC_RING_STATUS___M 0x000003FF +#define UMAC_WBM_R0_MISC_RING_STATUS___S 0 + +#define UMAC_WBM_R0_RELEASE_RING_FLUSH (0x00A34024) +#define UMAC_WBM_R0_RELEASE_RING_FLUSH___RWC QCSR_REG_RW +#define UMAC_WBM_R0_RELEASE_RING_FLUSH___POR 0x00000000 +#define UMAC_WBM_R0_RELEASE_RING_FLUSH__RELEASE_RING_AGE_IN_FLUSH___POR 0x0 +#define UMAC_WBM_R0_RELEASE_RING_FLUSH__SW_RELEASE_FIFO_FLUSH___POR 0x0 +#define UMAC_WBM_R0_RELEASE_RING_FLUSH__SW_RELEASE_RING_AGE_FLUSH___POR 0x0 +#define UMAC_WBM_R0_RELEASE_RING_FLUSH__RELEASE_RING_AGE_TIMEOUT___POR 0x000 +#define UMAC_WBM_R0_RELEASE_RING_FLUSH__RELEASE_RING_AGE_IN_FLUSH___M 0x00010000 +#define UMAC_WBM_R0_RELEASE_RING_FLUSH__RELEASE_RING_AGE_IN_FLUSH___S 16 +#define UMAC_WBM_R0_RELEASE_RING_FLUSH__SW_RELEASE_FIFO_FLUSH___M 0x00002000 +#define UMAC_WBM_R0_RELEASE_RING_FLUSH__SW_RELEASE_FIFO_FLUSH___S 13 +#define UMAC_WBM_R0_RELEASE_RING_FLUSH__SW_RELEASE_RING_AGE_FLUSH___M 0x00001000 +#define UMAC_WBM_R0_RELEASE_RING_FLUSH__SW_RELEASE_RING_AGE_FLUSH___S 12 +#define UMAC_WBM_R0_RELEASE_RING_FLUSH__RELEASE_RING_AGE_TIMEOUT___M 0x00000FFF +#define UMAC_WBM_R0_RELEASE_RING_FLUSH__RELEASE_RING_AGE_TIMEOUT___S 0 +#define UMAC_WBM_R0_RELEASE_RING_FLUSH___M 0x00013FFF +#define UMAC_WBM_R0_RELEASE_RING_FLUSH___S 0 + +#define UMAC_WBM_R0_IDLE_STATUS (0x00A34028) +#define UMAC_WBM_R0_IDLE_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_IDLE_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_IDLE_STATUS__ALL_IN_IDLE___POR 0x0 +#define UMAC_WBM_R0_IDLE_STATUS__ALL_APPLICATION_LOGIC_IN_IDLE___POR 0x0 +#define UMAC_WBM_R0_IDLE_STATUS__ALL_CONSUMER_RINGS_IN_IDLE___POR 0x0 +#define UMAC_WBM_R0_IDLE_STATUS__ALL_PRODUCER_RINGS_IN_IDLE___POR 0x0 +#define UMAC_WBM_R0_IDLE_STATUS__SW4_BUFFER_PROD_FIFO_IN_IDLE___POR 0x0 +#define UMAC_WBM_R0_IDLE_STATUS__SW3_BUFFER_PROD_FIFO_IN_IDLE___POR 0x0 +#define UMAC_WBM_R0_IDLE_STATUS__SW2_BUFFER_PROD_FIFO_IN_IDLE___POR 0x0 +#define UMAC_WBM_R0_IDLE_STATUS__SW1_BUFFER_PROD_FIFO_IN_IDLE___POR 0x0 +#define UMAC_WBM_R0_IDLE_STATUS__SW0_BUFFER_PROD_FIFO_IN_IDLE___POR 0x0 +#define UMAC_WBM_R0_IDLE_STATUS__FW_BUFFER_PROD_FIFO_IN_IDLE___POR 0x0 +#define UMAC_WBM_R0_IDLE_STATUS__LINK_DESC_ZERO_OUT_FIFO_IN_IDLE___POR 0x0 +#define UMAC_WBM_R0_IDLE_STATUS__LINK_IDLE_LIST_DIST_FIFO_IN_IDLE___POR 0x0 +#define UMAC_WBM_R0_IDLE_STATUS__LINK_IDLE_LIST_PROD_FIFO_IN_IDLE___POR 0x0 +#define UMAC_WBM_R0_IDLE_STATUS__BUFFER_IDLE_LIST_DIST_FIFO_IN_IDLE___POR 0x0 +#define UMAC_WBM_R0_IDLE_STATUS__BUFFER_IDLE_LIST_PROD_FIFO_IN_IDLE___POR 0x0 +#define UMAC_WBM_R0_IDLE_STATUS__RELEASE_PARSER_FIFO_IN_IDLE___POR 0x0 +#define UMAC_WBM_R0_IDLE_STATUS__ALL_IN_IDLE___M 0x00008000 +#define UMAC_WBM_R0_IDLE_STATUS__ALL_IN_IDLE___S 15 +#define UMAC_WBM_R0_IDLE_STATUS__ALL_APPLICATION_LOGIC_IN_IDLE___M 0x00004000 +#define UMAC_WBM_R0_IDLE_STATUS__ALL_APPLICATION_LOGIC_IN_IDLE___S 14 +#define UMAC_WBM_R0_IDLE_STATUS__ALL_CONSUMER_RINGS_IN_IDLE___M 0x00002000 +#define UMAC_WBM_R0_IDLE_STATUS__ALL_CONSUMER_RINGS_IN_IDLE___S 13 +#define UMAC_WBM_R0_IDLE_STATUS__ALL_PRODUCER_RINGS_IN_IDLE___M 0x00001000 +#define UMAC_WBM_R0_IDLE_STATUS__ALL_PRODUCER_RINGS_IN_IDLE___S 12 +#define UMAC_WBM_R0_IDLE_STATUS__SW4_BUFFER_PROD_FIFO_IN_IDLE___M 0x00000800 +#define UMAC_WBM_R0_IDLE_STATUS__SW4_BUFFER_PROD_FIFO_IN_IDLE___S 11 +#define UMAC_WBM_R0_IDLE_STATUS__SW3_BUFFER_PROD_FIFO_IN_IDLE___M 0x00000400 +#define UMAC_WBM_R0_IDLE_STATUS__SW3_BUFFER_PROD_FIFO_IN_IDLE___S 10 +#define UMAC_WBM_R0_IDLE_STATUS__SW2_BUFFER_PROD_FIFO_IN_IDLE___M 0x00000200 +#define UMAC_WBM_R0_IDLE_STATUS__SW2_BUFFER_PROD_FIFO_IN_IDLE___S 9 +#define UMAC_WBM_R0_IDLE_STATUS__SW1_BUFFER_PROD_FIFO_IN_IDLE___M 0x00000100 +#define UMAC_WBM_R0_IDLE_STATUS__SW1_BUFFER_PROD_FIFO_IN_IDLE___S 8 +#define UMAC_WBM_R0_IDLE_STATUS__SW0_BUFFER_PROD_FIFO_IN_IDLE___M 0x00000080 +#define UMAC_WBM_R0_IDLE_STATUS__SW0_BUFFER_PROD_FIFO_IN_IDLE___S 7 +#define UMAC_WBM_R0_IDLE_STATUS__FW_BUFFER_PROD_FIFO_IN_IDLE___M 0x00000040 +#define UMAC_WBM_R0_IDLE_STATUS__FW_BUFFER_PROD_FIFO_IN_IDLE___S 6 +#define UMAC_WBM_R0_IDLE_STATUS__LINK_DESC_ZERO_OUT_FIFO_IN_IDLE___M 0x00000020 +#define UMAC_WBM_R0_IDLE_STATUS__LINK_DESC_ZERO_OUT_FIFO_IN_IDLE___S 5 +#define UMAC_WBM_R0_IDLE_STATUS__LINK_IDLE_LIST_DIST_FIFO_IN_IDLE___M 0x00000010 +#define UMAC_WBM_R0_IDLE_STATUS__LINK_IDLE_LIST_DIST_FIFO_IN_IDLE___S 4 +#define UMAC_WBM_R0_IDLE_STATUS__LINK_IDLE_LIST_PROD_FIFO_IN_IDLE___M 0x00000008 +#define UMAC_WBM_R0_IDLE_STATUS__LINK_IDLE_LIST_PROD_FIFO_IN_IDLE___S 3 +#define UMAC_WBM_R0_IDLE_STATUS__BUFFER_IDLE_LIST_DIST_FIFO_IN_IDLE___M 0x00000004 +#define UMAC_WBM_R0_IDLE_STATUS__BUFFER_IDLE_LIST_DIST_FIFO_IN_IDLE___S 2 +#define UMAC_WBM_R0_IDLE_STATUS__BUFFER_IDLE_LIST_PROD_FIFO_IN_IDLE___M 0x00000002 +#define UMAC_WBM_R0_IDLE_STATUS__BUFFER_IDLE_LIST_PROD_FIFO_IN_IDLE___S 1 +#define UMAC_WBM_R0_IDLE_STATUS__RELEASE_PARSER_FIFO_IN_IDLE___M 0x00000001 +#define UMAC_WBM_R0_IDLE_STATUS__RELEASE_PARSER_FIFO_IN_IDLE___S 0 +#define UMAC_WBM_R0_IDLE_STATUS___M 0x0000FFFF +#define UMAC_WBM_R0_IDLE_STATUS___S 0 + +#define UMAC_WBM_R0_IDLE_SEQUENCE (0x00A3402C) +#define UMAC_WBM_R0_IDLE_SEQUENCE___RWC QCSR_REG_RO +#define UMAC_WBM_R0_IDLE_SEQUENCE___POR 0x00000000 +#define UMAC_WBM_R0_IDLE_SEQUENCE__WBM_RELEASE_RING_NOT_EMPTY___POR 0x0 +#define UMAC_WBM_R0_IDLE_SEQUENCE__WBM_IN_IDLE___POR 0x0 +#define UMAC_WBM_R0_IDLE_SEQUENCE__IDLE_SEQUENCE_STATE___POR 0x0 +#define UMAC_WBM_R0_IDLE_SEQUENCE__WBM_RELEASE_RING_NOT_EMPTY___M 0x00000020 +#define UMAC_WBM_R0_IDLE_SEQUENCE__WBM_RELEASE_RING_NOT_EMPTY___S 5 +#define UMAC_WBM_R0_IDLE_SEQUENCE__WBM_IN_IDLE___M 0x00000010 +#define UMAC_WBM_R0_IDLE_SEQUENCE__WBM_IN_IDLE___S 4 +#define UMAC_WBM_R0_IDLE_SEQUENCE__IDLE_SEQUENCE_STATE___M 0x0000000F +#define UMAC_WBM_R0_IDLE_SEQUENCE__IDLE_SEQUENCE_STATE___S 0 +#define UMAC_WBM_R0_IDLE_SEQUENCE___M 0x0000003F +#define UMAC_WBM_R0_IDLE_SEQUENCE___S 0 + +#define UMAC_WBM_R0_MSDU_PARSER_CONTROL (0x00A34030) +#define UMAC_WBM_R0_MSDU_PARSER_CONTROL___RWC QCSR_REG_RW +#define UMAC_WBM_R0_MSDU_PARSER_CONTROL___POR 0x00000000 +#define UMAC_WBM_R0_MSDU_PARSER_CONTROL__DISABLE_CACHE_2___POR 0x0 +#define UMAC_WBM_R0_MSDU_PARSER_CONTROL__FLUSH_CACHE_2___POR 0x0 +#define UMAC_WBM_R0_MSDU_PARSER_CONTROL__FLUSH_CACHE_1___POR 0x0 +#define UMAC_WBM_R0_MSDU_PARSER_CONTROL__DISABLE_CACHE_2___M 0x00000004 +#define UMAC_WBM_R0_MSDU_PARSER_CONTROL__DISABLE_CACHE_2___S 2 +#define UMAC_WBM_R0_MSDU_PARSER_CONTROL__FLUSH_CACHE_2___M 0x00000002 +#define UMAC_WBM_R0_MSDU_PARSER_CONTROL__FLUSH_CACHE_2___S 1 +#define UMAC_WBM_R0_MSDU_PARSER_CONTROL__FLUSH_CACHE_1___M 0x00000001 +#define UMAC_WBM_R0_MSDU_PARSER_CONTROL__FLUSH_CACHE_1___S 0 +#define UMAC_WBM_R0_MSDU_PARSER_CONTROL___M 0x00000007 +#define UMAC_WBM_R0_MSDU_PARSER_CONTROL___S 0 + +#define UMAC_WBM_R0_MSDU_PARSER_STATUS (0x00A34034) +#define UMAC_WBM_R0_MSDU_PARSER_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_MSDU_PARSER_STATUS___POR 0x00000441 +#define UMAC_WBM_R0_MSDU_PARSER_STATUS__FLUSH_CACHE_1_DONE___POR 0x0 +#define UMAC_WBM_R0_MSDU_PARSER_STATUS__MSDU_PARSER_CMD_FIFO_EMPTY___POR 0x1 +#define UMAC_WBM_R0_MSDU_PARSER_STATUS__MSDU_DELINK_PARSER_STATE___POR 0x1 +#define UMAC_WBM_R0_MSDU_PARSER_STATUS__MSDU_PARSER_CMD_FIFO_IN_IDLE___POR 0x0 +#define UMAC_WBM_R0_MSDU_PARSER_STATUS__CACHE_1_STATE___POR 0x01 +#define UMAC_WBM_R0_MSDU_PARSER_STATUS__FLUSH_CACHE_1_DONE___M 0x00000800 +#define UMAC_WBM_R0_MSDU_PARSER_STATUS__FLUSH_CACHE_1_DONE___S 11 +#define UMAC_WBM_R0_MSDU_PARSER_STATUS__MSDU_PARSER_CMD_FIFO_EMPTY___M 0x00000400 +#define UMAC_WBM_R0_MSDU_PARSER_STATUS__MSDU_PARSER_CMD_FIFO_EMPTY___S 10 +#define UMAC_WBM_R0_MSDU_PARSER_STATUS__MSDU_DELINK_PARSER_STATE___M 0x000003C0 +#define UMAC_WBM_R0_MSDU_PARSER_STATUS__MSDU_DELINK_PARSER_STATE___S 6 +#define UMAC_WBM_R0_MSDU_PARSER_STATUS__MSDU_PARSER_CMD_FIFO_IN_IDLE___M 0x00000020 +#define UMAC_WBM_R0_MSDU_PARSER_STATUS__MSDU_PARSER_CMD_FIFO_IN_IDLE___S 5 +#define UMAC_WBM_R0_MSDU_PARSER_STATUS__CACHE_1_STATE___M 0x0000001F +#define UMAC_WBM_R0_MSDU_PARSER_STATUS__CACHE_1_STATE___S 0 +#define UMAC_WBM_R0_MSDU_PARSER_STATUS___M 0x00000FFF +#define UMAC_WBM_R0_MSDU_PARSER_STATUS___S 0 + +#define UMAC_WBM_R0_MISC_CONTROL (0x00A34038) +#define UMAC_WBM_R0_MISC_CONTROL___RWC QCSR_REG_RW +#define UMAC_WBM_R0_MISC_CONTROL___POR 0x000000C0 +#define UMAC_WBM_R0_MISC_CONTROL__SPARE_CONTROL___POR 0x00000030 +#define UMAC_WBM_R0_MISC_CONTROL__GXI_WRITE_STRUCT_SWAP___POR 0x0 +#define UMAC_WBM_R0_MISC_CONTROL__GXI_READ_STRUCT_SWAP___POR 0x0 +#define UMAC_WBM_R0_MISC_CONTROL__SPARE_CONTROL___M 0xFFFFFFFC +#define UMAC_WBM_R0_MISC_CONTROL__SPARE_CONTROL___S 2 +#define UMAC_WBM_R0_MISC_CONTROL__GXI_WRITE_STRUCT_SWAP___M 0x00000002 +#define UMAC_WBM_R0_MISC_CONTROL__GXI_WRITE_STRUCT_SWAP___S 1 +#define UMAC_WBM_R0_MISC_CONTROL__GXI_READ_STRUCT_SWAP___M 0x00000001 +#define UMAC_WBM_R0_MISC_CONTROL__GXI_READ_STRUCT_SWAP___S 0 +#define UMAC_WBM_R0_MISC_CONTROL___M 0xFFFFFFFF +#define UMAC_WBM_R0_MISC_CONTROL___S 0 + +#define UMAC_WBM_R0_WATCHDOG_TIMEOUT (0x00A3403C) +#define UMAC_WBM_R0_WATCHDOG_TIMEOUT___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WATCHDOG_TIMEOUT___POR 0x00000000 +#define UMAC_WBM_R0_WATCHDOG_TIMEOUT__RESOLUTION_UNITS___POR 0x0 +#define UMAC_WBM_R0_WATCHDOG_TIMEOUT__VALUE___POR 0x000 +#define UMAC_WBM_R0_WATCHDOG_TIMEOUT__RESOLUTION_UNITS___M 0x00003000 +#define UMAC_WBM_R0_WATCHDOG_TIMEOUT__RESOLUTION_UNITS___S 12 +#define UMAC_WBM_R0_WATCHDOG_TIMEOUT__VALUE___M 0x00000FFF +#define UMAC_WBM_R0_WATCHDOG_TIMEOUT__VALUE___S 0 +#define UMAC_WBM_R0_WATCHDOG_TIMEOUT___M 0x00003FFF +#define UMAC_WBM_R0_WATCHDOG_TIMEOUT___S 0 + +#define UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE (0x00A34040) +#define UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE___RWC QCSR_REG_RO +#define UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE___POR 0x00000000 +#define UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__ERROR_OCCURRENCE___POR 0x0 +#define UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__ERROR_SOURCE___POR 0x0 +#define UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__ERROR_TYPE___POR 0x0 +#define UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__SW_BUFFER_COOKIE___POR 0x00000 +#define UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__BM_ACTION___POR 0x0 +#define UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__BUFFER_DESC_TYPE___POR 0x0 +#define UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__RETURN_BUFFER_MANAGER___POR 0x0 +#define UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__ERROR_OCCURRENCE___M 0x80000000 +#define UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__ERROR_OCCURRENCE___S 31 +#define UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__ERROR_SOURCE___M 0x40000000 +#define UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__ERROR_SOURCE___S 30 +#define UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__ERROR_TYPE___M 0x30000000 +#define UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__ERROR_TYPE___S 28 +#define UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__SW_BUFFER_COOKIE___M 0x0FFFFF00 +#define UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__SW_BUFFER_COOKIE___S 8 +#define UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__BM_ACTION___M 0x000000C0 +#define UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__BM_ACTION___S 6 +#define UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__BUFFER_DESC_TYPE___M 0x00000038 +#define UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__BUFFER_DESC_TYPE___S 3 +#define UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__RETURN_BUFFER_MANAGER___M 0x00000007 +#define UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE__RETURN_BUFFER_MANAGER___S 0 +#define UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE___M 0xFFFFFFFF +#define UMAC_WBM_R0_INTERRUPT_DATA_CAPTURE___S 0 + +#define UMAC_WBM_R0_INVALID_APB_ACC_ADDR (0x00A34044) +#define UMAC_WBM_R0_INVALID_APB_ACC_ADDR___RWC QCSR_REG_RO +#define UMAC_WBM_R0_INVALID_APB_ACC_ADDR___POR 0x00000000 +#define UMAC_WBM_R0_INVALID_APB_ACC_ADDR__ERR_TYPE___POR 0x0 +#define UMAC_WBM_R0_INVALID_APB_ACC_ADDR__ERR_ADDR___POR 0x00000 +#define UMAC_WBM_R0_INVALID_APB_ACC_ADDR__ERR_TYPE___M 0x00060000 +#define UMAC_WBM_R0_INVALID_APB_ACC_ADDR__ERR_TYPE___S 17 +#define UMAC_WBM_R0_INVALID_APB_ACC_ADDR__ERR_ADDR___M 0x0001FFFF +#define UMAC_WBM_R0_INVALID_APB_ACC_ADDR__ERR_ADDR___S 0 +#define UMAC_WBM_R0_INVALID_APB_ACC_ADDR___M 0x0007FFFF +#define UMAC_WBM_R0_INVALID_APB_ACC_ADDR___S 0 + +#define UMAC_WBM_R0_IDLE_LIST_CONTROL (0x00A34048) +#define UMAC_WBM_R0_IDLE_LIST_CONTROL___RWC QCSR_REG_RW +#define UMAC_WBM_R0_IDLE_LIST_CONTROL___POR 0x00000010 +#define UMAC_WBM_R0_IDLE_LIST_CONTROL__SCATTER_BUFFER_SIZE___POR 0x004 +#define UMAC_WBM_R0_IDLE_LIST_CONTROL__LINK_DESC_IDLE_LIST_MODE___POR 0x0 +#define UMAC_WBM_R0_IDLE_LIST_CONTROL__BUFFER_IDLE_LIST_MODE___POR 0x0 +#define UMAC_WBM_R0_IDLE_LIST_CONTROL__SCATTER_BUFFER_SIZE___M 0x000007FC +#define UMAC_WBM_R0_IDLE_LIST_CONTROL__SCATTER_BUFFER_SIZE___S 2 +#define UMAC_WBM_R0_IDLE_LIST_CONTROL__LINK_DESC_IDLE_LIST_MODE___M 0x00000002 +#define UMAC_WBM_R0_IDLE_LIST_CONTROL__LINK_DESC_IDLE_LIST_MODE___S 1 +#define UMAC_WBM_R0_IDLE_LIST_CONTROL__BUFFER_IDLE_LIST_MODE___M 0x00000001 +#define UMAC_WBM_R0_IDLE_LIST_CONTROL__BUFFER_IDLE_LIST_MODE___S 0 +#define UMAC_WBM_R0_IDLE_LIST_CONTROL___M 0x000007FF +#define UMAC_WBM_R0_IDLE_LIST_CONTROL___S 0 + +#define UMAC_WBM_R0_IDLE_LIST_SIZE (0x00A3404C) +#define UMAC_WBM_R0_IDLE_LIST_SIZE___RWC QCSR_REG_RW +#define UMAC_WBM_R0_IDLE_LIST_SIZE___POR 0x00020002 +#define UMAC_WBM_R0_IDLE_LIST_SIZE__SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST___POR 0x0002 +#define UMAC_WBM_R0_IDLE_LIST_SIZE__SCATTER_RING_SIZE_OF_IDLE_BUF_LIST___POR 0x0002 +#define UMAC_WBM_R0_IDLE_LIST_SIZE__SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST___M 0xFFFF0000 +#define UMAC_WBM_R0_IDLE_LIST_SIZE__SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST___S 16 +#define UMAC_WBM_R0_IDLE_LIST_SIZE__SCATTER_RING_SIZE_OF_IDLE_BUF_LIST___M 0x0000FFFF +#define UMAC_WBM_R0_IDLE_LIST_SIZE__SCATTER_RING_SIZE_OF_IDLE_BUF_LIST___S 0 +#define UMAC_WBM_R0_IDLE_LIST_SIZE___M 0xFFFFFFFF +#define UMAC_WBM_R0_IDLE_LIST_SIZE___S 0 + +#define UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB (0x00A34050) +#define UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB__BASE_ADDRESS_31_0___POR 0x00000000 +#define UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB__BASE_ADDRESS_31_0___M 0xFFFFFFFF +#define UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB__BASE_ADDRESS_31_0___S 0 +#define UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB___S 0 + +#define UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB (0x00A34054) +#define UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB__ADDRESS_MATCH_TAG___POR 0x000000 +#define UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB__BASE_ADDRESS_39_32___POR 0x00 +#define UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB__ADDRESS_MATCH_TAG___M 0xFFFFFF00 +#define UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB__ADDRESS_MATCH_TAG___S 8 +#define UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB__BASE_ADDRESS_39_32___M 0x000000FF +#define UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB__BASE_ADDRESS_39_32___S 0 +#define UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB___S 0 + +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB (0x00A34058) +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB__BASE_ADDRESS_31_0___POR 0x00000000 +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB__BASE_ADDRESS_31_0___M 0xFFFFFFFF +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB__BASE_ADDRESS_31_0___S 0 +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB___S 0 + +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB (0x00A3405C) +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB__ADDRESS_MATCH_TAG___POR 0x000000 +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB__BASE_ADDRESS_39_32___POR 0x00 +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB__ADDRESS_MATCH_TAG___M 0xFFFFFF00 +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB__ADDRESS_MATCH_TAG___S 8 +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB__BASE_ADDRESS_39_32___M 0x000000FF +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB__BASE_ADDRESS_39_32___S 0 +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB___S 0 + +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0 (0x00A34060) +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0___RWC QCSR_REG_RW +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0___POR 0x00000000 +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0__BUFFER_ADDRESS_31_0___POR 0x00000000 +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0__BUFFER_ADDRESS_31_0___M 0xFFFFFFFF +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0__BUFFER_ADDRESS_31_0___S 0 +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0___M 0xFFFFFFFF +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0___S 0 + +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1 (0x00A34064) +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1___RWC QCSR_REG_RW +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1___POR 0x00000000 +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1__HEAD_POINTER_OFFSET___POR 0x0000 +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1__BUFFER_ADDRESS_39_32___POR 0x00 +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1__HEAD_POINTER_OFFSET___M 0x001FFF00 +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1__HEAD_POINTER_OFFSET___S 8 +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1__BUFFER_ADDRESS_39_32___M 0x000000FF +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1__BUFFER_ADDRESS_39_32___S 0 +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1___M 0x001FFFFF +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1___S 0 + +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0 (0x00A34068) +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0___RWC QCSR_REG_RW +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0___POR 0x00000000 +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0__BUFFER_ADDRESS_31_0___POR 0x00000000 +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0__BUFFER_ADDRESS_31_0___M 0xFFFFFFFF +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0__BUFFER_ADDRESS_31_0___S 0 +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0___M 0xFFFFFFFF +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0___S 0 + +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1 (0x00A3406C) +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1___RWC QCSR_REG_RW +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1___POR 0x00000000 +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1__HEAD_POINTER_OFFSET___POR 0x0000 +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1__BUFFER_ADDRESS_39_32___POR 0x00 +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1__HEAD_POINTER_OFFSET___M 0x001FFF00 +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1__HEAD_POINTER_OFFSET___S 8 +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1__BUFFER_ADDRESS_39_32___M 0x000000FF +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1__BUFFER_ADDRESS_39_32___S 0 +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1___M 0x001FFFFF +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1___S 0 + +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0 (0x00A34070) +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0___RWC QCSR_REG_RW +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0___POR 0x00000000 +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0__BUFFER_ADDRESS_31_0___POR 0x00000000 +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0__BUFFER_ADDRESS_31_0___M 0xFFFFFFFF +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0__BUFFER_ADDRESS_31_0___S 0 +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0___M 0xFFFFFFFF +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0___S 0 + +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1 (0x00A34074) +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1___RWC QCSR_REG_RW +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1___POR 0x00000000 +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1__TAIL_POINTER_OFFSET___POR 0x0000 +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1__BUFFER_ADDRESS_39_32___POR 0x00 +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1__TAIL_POINTER_OFFSET___M 0x001FFF00 +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1__TAIL_POINTER_OFFSET___S 8 +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1__BUFFER_ADDRESS_39_32___M 0x000000FF +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1__BUFFER_ADDRESS_39_32___S 0 +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1___M 0x001FFFFF +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1___S 0 + +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0 (0x00A34078) +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0___RWC QCSR_REG_RW +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0___POR 0x00000000 +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0__BUFFER_ADDRESS_31_0___POR 0x00000000 +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0__BUFFER_ADDRESS_31_0___M 0xFFFFFFFF +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0__BUFFER_ADDRESS_31_0___S 0 +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0___M 0xFFFFFFFF +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0___S 0 + +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1 (0x00A3407C) +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1___RWC QCSR_REG_RW +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1___POR 0x00000000 +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1__TAIL_POINTER_OFFSET___POR 0x0000 +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1__BUFFER_ADDRESS_39_32___POR 0x00 +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1__TAIL_POINTER_OFFSET___M 0x001FFF00 +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1__TAIL_POINTER_OFFSET___S 8 +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1__BUFFER_ADDRESS_39_32___M 0x000000FF +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1__BUFFER_ADDRESS_39_32___S 0 +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1___M 0x001FFFFF +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1___S 0 + +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_HP (0x00A34080) +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_HP___RWC QCSR_REG_RW +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_HP___POR 0x00000000 +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_HP__SCAT_HEAD_PTR___POR 0x00000 +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_HP__SCAT_HEAD_PTR___M 0x000FFFFF +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_HP__SCAT_HEAD_PTR___S 0 +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_HP___M 0x000FFFFF +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_HP___S 0 + +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HP (0x00A34084) +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HP___RWC QCSR_REG_RW +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HP___POR 0x00000000 +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HP__SCAT_HEAD_PTR___POR 0x00000 +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HP__SCAT_HEAD_PTR___M 0x000FFFFF +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HP__SCAT_HEAD_PTR___S 0 +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HP___M 0x000FFFFF +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_HP___S 0 + +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_TP (0x00A34088) +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_TP___RWC QCSR_REG_RW +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_TP___POR 0x00000000 +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_TP__SCAT_TAIL_PTR___POR 0x00000 +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_TP__SCAT_TAIL_PTR___M 0x000FFFFF +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_TP__SCAT_TAIL_PTR___S 0 +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_TP___M 0x000FFFFF +#define UMAC_WBM_R0_SCATTERED_BUF_PTR_TP___S 0 + +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TP (0x00A3408C) +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TP___RWC QCSR_REG_RW +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TP___POR 0x00000000 +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TP__SCAT_TAIL_PTR___POR 0x00000 +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TP__SCAT_TAIL_PTR___M 0x000FFFFF +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TP__SCAT_TAIL_PTR___S 0 +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TP___M 0x000FFFFF +#define UMAC_WBM_R0_SCATTERED_LINK_DESC_PTR_TP___S 0 + +#define UMAC_WBM_R0_CLK_GATE_CTRL (0x00A34090) +#define UMAC_WBM_R0_CLK_GATE_CTRL___RWC QCSR_REG_RW +#define UMAC_WBM_R0_CLK_GATE_CTRL___POR 0x00020000 +#define UMAC_WBM_R0_CLK_GATE_CTRL__CLK_ENS_EXTEND___POR 0x1 +#define UMAC_WBM_R0_CLK_GATE_CTRL__CLK_GATE_DISABLE_APB___POR 0x0 +#define UMAC_WBM_R0_CLK_GATE_CTRL__CLK_GATE_DISABLE___POR 0x0000 +#define UMAC_WBM_R0_CLK_GATE_CTRL__CLK_ENS_EXTEND___M 0x00020000 +#define UMAC_WBM_R0_CLK_GATE_CTRL__CLK_ENS_EXTEND___S 17 +#define UMAC_WBM_R0_CLK_GATE_CTRL__CLK_GATE_DISABLE_APB___M 0x00010000 +#define UMAC_WBM_R0_CLK_GATE_CTRL__CLK_GATE_DISABLE_APB___S 16 +#define UMAC_WBM_R0_CLK_GATE_CTRL__CLK_GATE_DISABLE___M 0x0000FFFF +#define UMAC_WBM_R0_CLK_GATE_CTRL__CLK_GATE_DISABLE___S 0 +#define UMAC_WBM_R0_CLK_GATE_CTRL___M 0x0003FFFF +#define UMAC_WBM_R0_CLK_GATE_CTRL___S 0 + +#define UMAC_WBM_R0_GXI_TESTBUS_LOWER (0x00A34094) +#define UMAC_WBM_R0_GXI_TESTBUS_LOWER___RWC QCSR_REG_RO +#define UMAC_WBM_R0_GXI_TESTBUS_LOWER___POR 0x00000000 +#define UMAC_WBM_R0_GXI_TESTBUS_LOWER__VALUE___POR 0x00000000 +#define UMAC_WBM_R0_GXI_TESTBUS_LOWER__VALUE___M 0xFFFFFFFF +#define UMAC_WBM_R0_GXI_TESTBUS_LOWER__VALUE___S 0 +#define UMAC_WBM_R0_GXI_TESTBUS_LOWER___M 0xFFFFFFFF +#define UMAC_WBM_R0_GXI_TESTBUS_LOWER___S 0 + +#define UMAC_WBM_R0_GXI_TESTBUS_UPPER (0x00A34098) +#define UMAC_WBM_R0_GXI_TESTBUS_UPPER___RWC QCSR_REG_RO +#define UMAC_WBM_R0_GXI_TESTBUS_UPPER___POR 0x00000000 +#define UMAC_WBM_R0_GXI_TESTBUS_UPPER__VALUE___POR 0x00 +#define UMAC_WBM_R0_GXI_TESTBUS_UPPER__VALUE___M 0x000000FF +#define UMAC_WBM_R0_GXI_TESTBUS_UPPER__VALUE___S 0 +#define UMAC_WBM_R0_GXI_TESTBUS_UPPER___M 0x000000FF +#define UMAC_WBM_R0_GXI_TESTBUS_UPPER___S 0 + +#define UMAC_WBM_R0_GXI_SM_STATES_IX_0 (0x00A3409C) +#define UMAC_WBM_R0_GXI_SM_STATES_IX_0___RWC QCSR_REG_RO +#define UMAC_WBM_R0_GXI_SM_STATES_IX_0___POR 0x00000211 +#define UMAC_WBM_R0_GXI_SM_STATES_IX_0__SM_STATE_RD_ADDR___POR 0x1 +#define UMAC_WBM_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_ADDR___POR 0x01 +#define UMAC_WBM_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_DATA___POR 0x1 +#define UMAC_WBM_R0_GXI_SM_STATES_IX_0__SM_STATE_RD_ADDR___M 0x00000E00 +#define UMAC_WBM_R0_GXI_SM_STATES_IX_0__SM_STATE_RD_ADDR___S 9 +#define UMAC_WBM_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_ADDR___M 0x000001F0 +#define UMAC_WBM_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_ADDR___S 4 +#define UMAC_WBM_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_DATA___M 0x0000000F +#define UMAC_WBM_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_DATA___S 0 +#define UMAC_WBM_R0_GXI_SM_STATES_IX_0___M 0x00000FFF +#define UMAC_WBM_R0_GXI_SM_STATES_IX_0___S 0 + +#define UMAC_WBM_R0_GXI_END_OF_TEST_CHECK (0x00A340A0) +#define UMAC_WBM_R0_GXI_END_OF_TEST_CHECK___RWC QCSR_REG_RW +#define UMAC_WBM_R0_GXI_END_OF_TEST_CHECK___POR 0x00000000 +#define UMAC_WBM_R0_GXI_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0 +#define UMAC_WBM_R0_GXI_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001 +#define UMAC_WBM_R0_GXI_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S 0 +#define UMAC_WBM_R0_GXI_END_OF_TEST_CHECK___M 0x00000001 +#define UMAC_WBM_R0_GXI_END_OF_TEST_CHECK___S 0 + +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE (0x00A340A4) +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE___RWC QCSR_REG_RW +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE___POR 0x00000000 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___POR 0x0 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__SPARE___POR 0x0 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WDOG_CTR___POR 0x0 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__RD_FIFO___POR 0x0 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_FIFO___POR 0x0 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_FIFO___POR 0x0 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__RD_AXI_MAS___POR 0x0 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_AXI_MAS___POR 0x0 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_AXI_MAS___POR 0x0 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_CMD___POR 0x0 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_CMD___POR 0x0 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__RD_CMD___POR 0x0 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__CORE___POR 0x0 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___M 0x80000000 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___S 31 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__SPARE___M 0x00000800 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__SPARE___S 11 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WDOG_CTR___M 0x00000400 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WDOG_CTR___S 10 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__RD_FIFO___M 0x00000200 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__RD_FIFO___S 9 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_FIFO___M 0x00000100 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_FIFO___S 8 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_FIFO___M 0x00000080 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_FIFO___S 7 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__RD_AXI_MAS___M 0x00000040 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__RD_AXI_MAS___S 6 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_AXI_MAS___M 0x00000020 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_AXI_MAS___S 5 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_AXI_MAS___M 0x00000010 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_AXI_MAS___S 4 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_CMD___M 0x00000008 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_CMD___S 3 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_CMD___M 0x00000004 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_CMD___S 2 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__RD_CMD___M 0x00000002 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__RD_CMD___S 1 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__CORE___M 0x00000001 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE__CORE___S 0 +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE___M 0x80000FFF +#define UMAC_WBM_R0_GXI_CLOCK_GATE_DISABLE___S 0 + +#define UMAC_WBM_R0_GXI_GXI_ERR_INTS (0x00A340A8) +#define UMAC_WBM_R0_GXI_GXI_ERR_INTS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_GXI_GXI_ERR_INTS___POR 0x00000000 +#define UMAC_WBM_R0_GXI_GXI_ERR_INTS__GXI_WR_LAST_ERR_INT___POR 0x0 +#define UMAC_WBM_R0_GXI_GXI_ERR_INTS__GXI_AXI_WR_ERR_INT___POR 0x0 +#define UMAC_WBM_R0_GXI_GXI_ERR_INTS__GXI_AXI_RD_ERR_INT___POR 0x0 +#define UMAC_WBM_R0_GXI_GXI_ERR_INTS__GXI_WDTIMEOUT_INT___POR 0x0 +#define UMAC_WBM_R0_GXI_GXI_ERR_INTS__GXI_WR_LAST_ERR_INT___M 0x01000000 +#define UMAC_WBM_R0_GXI_GXI_ERR_INTS__GXI_WR_LAST_ERR_INT___S 24 +#define UMAC_WBM_R0_GXI_GXI_ERR_INTS__GXI_AXI_WR_ERR_INT___M 0x00010000 +#define UMAC_WBM_R0_GXI_GXI_ERR_INTS__GXI_AXI_WR_ERR_INT___S 16 +#define UMAC_WBM_R0_GXI_GXI_ERR_INTS__GXI_AXI_RD_ERR_INT___M 0x00000100 +#define UMAC_WBM_R0_GXI_GXI_ERR_INTS__GXI_AXI_RD_ERR_INT___S 8 +#define UMAC_WBM_R0_GXI_GXI_ERR_INTS__GXI_WDTIMEOUT_INT___M 0x00000001 +#define UMAC_WBM_R0_GXI_GXI_ERR_INTS__GXI_WDTIMEOUT_INT___S 0 +#define UMAC_WBM_R0_GXI_GXI_ERR_INTS___M 0x01010101 +#define UMAC_WBM_R0_GXI_GXI_ERR_INTS___S 0 + +#define UMAC_WBM_R0_GXI_GXI_ERR_STATS (0x00A340AC) +#define UMAC_WBM_R0_GXI_GXI_ERR_STATS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_GXI_GXI_ERR_STATS___POR 0x00000000 +#define UMAC_WBM_R0_GXI_GXI_ERR_STATS__AXI_WR_LAST_ERR_PORT___POR 0x00 +#define UMAC_WBM_R0_GXI_GXI_ERR_STATS__AXI_WR_ERR_PORT___POR 0x00 +#define UMAC_WBM_R0_GXI_GXI_ERR_STATS__AXI_RD_ERR_PORT___POR 0x00 +#define UMAC_WBM_R0_GXI_GXI_ERR_STATS__AXI_WR_LAST_ERR_PORT___M 0x003F0000 +#define UMAC_WBM_R0_GXI_GXI_ERR_STATS__AXI_WR_LAST_ERR_PORT___S 16 +#define UMAC_WBM_R0_GXI_GXI_ERR_STATS__AXI_WR_ERR_PORT___M 0x00003F00 +#define UMAC_WBM_R0_GXI_GXI_ERR_STATS__AXI_WR_ERR_PORT___S 8 +#define UMAC_WBM_R0_GXI_GXI_ERR_STATS__AXI_RD_ERR_PORT___M 0x0000003F +#define UMAC_WBM_R0_GXI_GXI_ERR_STATS__AXI_RD_ERR_PORT___S 0 +#define UMAC_WBM_R0_GXI_GXI_ERR_STATS___M 0x003F3F3F +#define UMAC_WBM_R0_GXI_GXI_ERR_STATS___S 0 + +#define UMAC_WBM_R0_GXI_GXI_DEFAULT_CONTROL (0x00A340B0) +#define UMAC_WBM_R0_GXI_GXI_DEFAULT_CONTROL___RWC QCSR_REG_RW +#define UMAC_WBM_R0_GXI_GXI_DEFAULT_CONTROL___POR 0x00000000 +#define UMAC_WBM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READ_DATA___POR 0x00 +#define UMAC_WBM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITE_DATA___POR 0x00 +#define UMAC_WBM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READS___POR 0x00 +#define UMAC_WBM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITES___POR 0x00 +#define UMAC_WBM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READ_DATA___M 0xFF000000 +#define UMAC_WBM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READ_DATA___S 24 +#define UMAC_WBM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITE_DATA___M 0x00FF0000 +#define UMAC_WBM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITE_DATA___S 16 +#define UMAC_WBM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READS___M 0x00003F00 +#define UMAC_WBM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READS___S 8 +#define UMAC_WBM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITES___M 0x0000003F +#define UMAC_WBM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITES___S 0 +#define UMAC_WBM_R0_GXI_GXI_DEFAULT_CONTROL___M 0xFFFF3F3F +#define UMAC_WBM_R0_GXI_GXI_DEFAULT_CONTROL___S 0 + +#define UMAC_WBM_R0_GXI_GXI_REDUCED_CONTROL (0x00A340B4) +#define UMAC_WBM_R0_GXI_GXI_REDUCED_CONTROL___RWC QCSR_REG_RW +#define UMAC_WBM_R0_GXI_GXI_REDUCED_CONTROL___POR 0x00000000 +#define UMAC_WBM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READ_DATA___POR 0x00 +#define UMAC_WBM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITE_DATA___POR 0x00 +#define UMAC_WBM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READS___POR 0x00 +#define UMAC_WBM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITES___POR 0x00 +#define UMAC_WBM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READ_DATA___M 0xFF000000 +#define UMAC_WBM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READ_DATA___S 24 +#define UMAC_WBM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITE_DATA___M 0x00FF0000 +#define UMAC_WBM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITE_DATA___S 16 +#define UMAC_WBM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READS___M 0x00003F00 +#define UMAC_WBM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READS___S 8 +#define UMAC_WBM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITES___M 0x0000003F +#define UMAC_WBM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITES___S 0 +#define UMAC_WBM_R0_GXI_GXI_REDUCED_CONTROL___M 0xFFFF3F3F +#define UMAC_WBM_R0_GXI_GXI_REDUCED_CONTROL___S 0 + +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL (0x00A340B8) +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL___RWC QCSR_REG_RW +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL___POR 0x00240000 +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_RD_FLUSH___POR 0x0 +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_WR_FLUSH___POR 0x0 +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_DISABLE_WR_PREFIL___POR 0x0 +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_WR_BOUNDARY_SPLIT___POR 0x0 +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_RD_BOUNDARY_SPLIT___POR 0x0 +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_BURST_SIZE___POR 0x2 +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_READ_BURST_SIZE___POR 0x2 +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_READ_ISSUE_THRESHOLD___POR 0x00 +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_PREFETCH_THRESHOLD___POR 0x00 +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_CLEAR_STATS___POR 0x0 +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_RD_FLUSH___M 0x08000000 +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_RD_FLUSH___S 27 +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_WR_FLUSH___M 0x04000000 +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_WR_FLUSH___S 26 +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_DISABLE_WR_PREFIL___M 0x02000000 +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_DISABLE_WR_PREFIL___S 25 +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_WR_BOUNDARY_SPLIT___M 0x01000000 +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_WR_BOUNDARY_SPLIT___S 24 +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_RD_BOUNDARY_SPLIT___M 0x00800000 +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_RD_BOUNDARY_SPLIT___S 23 +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_BURST_SIZE___M 0x00700000 +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_BURST_SIZE___S 20 +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_READ_BURST_SIZE___M 0x000E0000 +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_READ_BURST_SIZE___S 17 +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_READ_ISSUE_THRESHOLD___M 0x0001FE00 +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_READ_ISSUE_THRESHOLD___S 9 +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_PREFETCH_THRESHOLD___M 0x000001FE +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_PREFETCH_THRESHOLD___S 1 +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_CLEAR_STATS___M 0x00000001 +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL__GXI_CLEAR_STATS___S 0 +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL___M 0x0FFFFFFF +#define UMAC_WBM_R0_GXI_GXI_MISC_CONTROL___S 0 + +#define UMAC_WBM_R0_GXI_GXI_WDOG_CONTROL (0x00A340BC) +#define UMAC_WBM_R0_GXI_GXI_WDOG_CONTROL___RWC QCSR_REG_RW +#define UMAC_WBM_R0_GXI_GXI_WDOG_CONTROL___POR 0x00FF0000 +#define UMAC_WBM_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_LIMIT___POR 0x00FF +#define UMAC_WBM_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_DISABLE___POR 0x0 +#define UMAC_WBM_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_LIMIT___M 0xFFFF0000 +#define UMAC_WBM_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_LIMIT___S 16 +#define UMAC_WBM_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_DISABLE___M 0x00000001 +#define UMAC_WBM_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_DISABLE___S 0 +#define UMAC_WBM_R0_GXI_GXI_WDOG_CONTROL___M 0xFFFF0001 +#define UMAC_WBM_R0_GXI_GXI_WDOG_CONTROL___S 0 + +#define UMAC_WBM_R0_GXI_GXI_WDOG_STATUS (0x00A340C0) +#define UMAC_WBM_R0_GXI_GXI_WDOG_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_GXI_GXI_WDOG_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_GXI_GXI_WDOG_STATUS__GXI_WDOG_STATUS___POR 0x0000 +#define UMAC_WBM_R0_GXI_GXI_WDOG_STATUS__GXI_WDOG_STATUS___M 0x0000FFFF +#define UMAC_WBM_R0_GXI_GXI_WDOG_STATUS__GXI_WDOG_STATUS___S 0 +#define UMAC_WBM_R0_GXI_GXI_WDOG_STATUS___M 0x0000FFFF +#define UMAC_WBM_R0_GXI_GXI_WDOG_STATUS___S 0 + +#define UMAC_WBM_R0_GXI_GXI_IDLE_COUNTERS (0x00A340C4) +#define UMAC_WBM_R0_GXI_GXI_IDLE_COUNTERS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_GXI_GXI_IDLE_COUNTERS___POR 0x00000000 +#define UMAC_WBM_R0_GXI_GXI_IDLE_COUNTERS__GXI_READ_IDLE_CNT___POR 0x0000 +#define UMAC_WBM_R0_GXI_GXI_IDLE_COUNTERS__GXI_WRITE_IDLE_CNT___POR 0x0000 +#define UMAC_WBM_R0_GXI_GXI_IDLE_COUNTERS__GXI_READ_IDLE_CNT___M 0xFFFF0000 +#define UMAC_WBM_R0_GXI_GXI_IDLE_COUNTERS__GXI_READ_IDLE_CNT___S 16 +#define UMAC_WBM_R0_GXI_GXI_IDLE_COUNTERS__GXI_WRITE_IDLE_CNT___M 0x0000FFFF +#define UMAC_WBM_R0_GXI_GXI_IDLE_COUNTERS__GXI_WRITE_IDLE_CNT___S 0 +#define UMAC_WBM_R0_GXI_GXI_IDLE_COUNTERS___M 0xFFFFFFFF +#define UMAC_WBM_R0_GXI_GXI_IDLE_COUNTERS___S 0 + +#define UMAC_WBM_R0_GXI_GXI_RD_LATENCY_CTRL (0x00A340C8) +#define UMAC_WBM_R0_GXI_GXI_RD_LATENCY_CTRL___RWC QCSR_REG_RW +#define UMAC_WBM_R0_GXI_GXI_RD_LATENCY_CTRL___POR 0x00000000 +#define UMAC_WBM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_RANGE___POR 0x0 +#define UMAC_WBM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_EN___POR 0x0 +#define UMAC_WBM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_MIN___POR 0x0000 +#define UMAC_WBM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_RANGE___M 0x000E0000 +#define UMAC_WBM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_RANGE___S 17 +#define UMAC_WBM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_EN___M 0x00010000 +#define UMAC_WBM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_EN___S 16 +#define UMAC_WBM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_MIN___M 0x0000FFFF +#define UMAC_WBM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_MIN___S 0 +#define UMAC_WBM_R0_GXI_GXI_RD_LATENCY_CTRL___M 0x000FFFFF +#define UMAC_WBM_R0_GXI_GXI_RD_LATENCY_CTRL___S 0 + +#define UMAC_WBM_R0_GXI_GXI_WR_LATENCY_CTRL (0x00A340CC) +#define UMAC_WBM_R0_GXI_GXI_WR_LATENCY_CTRL___RWC QCSR_REG_RW +#define UMAC_WBM_R0_GXI_GXI_WR_LATENCY_CTRL___POR 0x00000000 +#define UMAC_WBM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_RANGE___POR 0x0 +#define UMAC_WBM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_EN___POR 0x0 +#define UMAC_WBM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_MIN___POR 0x0000 +#define UMAC_WBM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_RANGE___M 0x000E0000 +#define UMAC_WBM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_RANGE___S 17 +#define UMAC_WBM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_EN___M 0x00010000 +#define UMAC_WBM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_EN___S 16 +#define UMAC_WBM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_MIN___M 0x0000FFFF +#define UMAC_WBM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_MIN___S 0 +#define UMAC_WBM_R0_GXI_GXI_WR_LATENCY_CTRL___M 0x000FFFFF +#define UMAC_WBM_R0_GXI_GXI_WR_LATENCY_CTRL___S 0 + +#define UMAC_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0 (0x00A340D0) +#define UMAC_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___RWC QCSR_REG_RW +#define UMAC_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___POR 0x00000000 +#define UMAC_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0__VALUE___POR 0x00000000 +#define UMAC_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0__VALUE___M 0xFFFFFFFF +#define UMAC_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0__VALUE___S 0 +#define UMAC_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___M 0xFFFFFFFF +#define UMAC_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___S 0 + +#define UMAC_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1 (0x00A340D4) +#define UMAC_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___RWC QCSR_REG_RW +#define UMAC_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___POR 0x00000000 +#define UMAC_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1__VALUE___POR 0x00000000 +#define UMAC_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1__VALUE___M 0xFFFFFFFF +#define UMAC_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1__VALUE___S 0 +#define UMAC_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___M 0xFFFFFFFF +#define UMAC_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___S 0 + +#define UMAC_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0 (0x00A340D8) +#define UMAC_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___RWC QCSR_REG_RW +#define UMAC_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___POR 0x00000000 +#define UMAC_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0__VALUE___POR 0x00000000 +#define UMAC_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0__VALUE___M 0xFFFFFFFF +#define UMAC_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0__VALUE___S 0 +#define UMAC_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___M 0xFFFFFFFF +#define UMAC_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___S 0 + +#define UMAC_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1 (0x00A340DC) +#define UMAC_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___RWC QCSR_REG_RW +#define UMAC_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___POR 0x00000000 +#define UMAC_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1__VALUE___POR 0x00000000 +#define UMAC_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1__VALUE___M 0xFFFFFFFF +#define UMAC_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1__VALUE___S 0 +#define UMAC_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___M 0xFFFFFFFF +#define UMAC_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___S 0 + +#define UMAC_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL (0x00A340E0) +#define UMAC_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL___RWC QCSR_REG_RW +#define UMAC_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL___POR 0x00000000 +#define UMAC_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_EN___POR 0x0 +#define UMAC_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_CNT___POR 0x00 +#define UMAC_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_EN___POR 0x0 +#define UMAC_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_CNT___POR 0x00 +#define UMAC_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_EN___M 0x00008000 +#define UMAC_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_EN___S 15 +#define UMAC_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_CNT___M 0x00001F00 +#define UMAC_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_CNT___S 8 +#define UMAC_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_EN___M 0x00000080 +#define UMAC_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_EN___S 7 +#define UMAC_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_CNT___M 0x0000001F +#define UMAC_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_CNT___S 0 +#define UMAC_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL___M 0x00009F9F +#define UMAC_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL___S 0 + +#define UMAC_WBM_R0_PPE_RELEASE_RING_BASE_LSB (0x00A340E4) +#define UMAC_WBM_R0_PPE_RELEASE_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_PPE_RELEASE_RING_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_PPE_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_WBM_R0_PPE_RELEASE_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_PPE_RELEASE_RING_BASE_LSB___S 0 + +#define UMAC_WBM_R0_PPE_RELEASE_RING_BASE_MSB (0x00A340E8) +#define UMAC_WBM_R0_PPE_RELEASE_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_PPE_RELEASE_RING_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_PPE_RELEASE_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_WBM_R0_PPE_RELEASE_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_WBM_R0_PPE_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_PPE_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_WBM_R0_PPE_RELEASE_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_WBM_R0_PPE_RELEASE_RING_BASE_MSB___S 0 + +#define UMAC_WBM_R0_PPE_RELEASE_RING_ID (0x00A340EC) +#define UMAC_WBM_R0_PPE_RELEASE_RING_ID___RWC QCSR_REG_RW +#define UMAC_WBM_R0_PPE_RELEASE_RING_ID___POR 0x00000000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_WBM_R0_PPE_RELEASE_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_WBM_R0_PPE_RELEASE_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_WBM_R0_PPE_RELEASE_RING_ID___M 0x000000FF +#define UMAC_WBM_R0_PPE_RELEASE_RING_ID___S 0 + +#define UMAC_WBM_R0_PPE_RELEASE_RING_STATUS (0x00A340F0) +#define UMAC_WBM_R0_PPE_RELEASE_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_PPE_RELEASE_RING_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_WBM_R0_PPE_RELEASE_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_WBM_R0_PPE_RELEASE_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_WBM_R0_PPE_RELEASE_RING_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_PPE_RELEASE_RING_STATUS___S 0 + +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC (0x00A340F4) +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC___RWC QCSR_REG_RW +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC___POR 0x00000080 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC___M 0x003FFFFF +#define UMAC_WBM_R0_PPE_RELEASE_RING_MISC___S 0 + +#define UMAC_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB (0x00A34100) +#define UMAC_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S 0 +#define UMAC_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB___S 0 + +#define UMAC_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB (0x00A34104) +#define UMAC_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB___POR 0x00000000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S 0 +#define UMAC_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB___S 0 + +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0 (0x00A34114) +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S 15 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0___S 0 + +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1 (0x00A34118) +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S 0 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1___S 0 + +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS (0x00A3411C) +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S 15 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS___S 0 + +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER (0x00A34120) +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S 0 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER___S 0 + +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER (0x00A34124) +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___S 0 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER___S 0 + +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS (0x00A34128) +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S 16 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S 0 +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF +#define UMAC_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS___S 0 + +#define UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB (0x00A3412C) +#define UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB (0x00A34130) +#define UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_DATA (0x00A34134) +#define UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_WBM_R0_PPE_RELEASE_RING_MSI1_DATA___S 0 + +#define UMAC_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET (0x00A34138) +#define UMAC_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_WBM_R0_TQM_RELEASE_RING_BASE_LSB (0x00A3413C) +#define UMAC_WBM_R0_TQM_RELEASE_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_TQM_RELEASE_RING_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_TQM_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_WBM_R0_TQM_RELEASE_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_TQM_RELEASE_RING_BASE_LSB___S 0 + +#define UMAC_WBM_R0_TQM_RELEASE_RING_BASE_MSB (0x00A34140) +#define UMAC_WBM_R0_TQM_RELEASE_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_TQM_RELEASE_RING_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_TQM_RELEASE_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_WBM_R0_TQM_RELEASE_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_WBM_R0_TQM_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_TQM_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_WBM_R0_TQM_RELEASE_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_WBM_R0_TQM_RELEASE_RING_BASE_MSB___S 0 + +#define UMAC_WBM_R0_TQM_RELEASE_RING_ID (0x00A34144) +#define UMAC_WBM_R0_TQM_RELEASE_RING_ID___RWC QCSR_REG_RW +#define UMAC_WBM_R0_TQM_RELEASE_RING_ID___POR 0x00000000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_WBM_R0_TQM_RELEASE_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_WBM_R0_TQM_RELEASE_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_WBM_R0_TQM_RELEASE_RING_ID___M 0x000000FF +#define UMAC_WBM_R0_TQM_RELEASE_RING_ID___S 0 + +#define UMAC_WBM_R0_TQM_RELEASE_RING_STATUS (0x00A34148) +#define UMAC_WBM_R0_TQM_RELEASE_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_TQM_RELEASE_RING_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_WBM_R0_TQM_RELEASE_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_WBM_R0_TQM_RELEASE_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_WBM_R0_TQM_RELEASE_RING_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_TQM_RELEASE_RING_STATUS___S 0 + +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC (0x00A3414C) +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC___RWC QCSR_REG_RW +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC___POR 0x00000080 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC___M 0x003FFFFF +#define UMAC_WBM_R0_TQM_RELEASE_RING_MISC___S 0 + +#define UMAC_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB (0x00A34158) +#define UMAC_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S 0 +#define UMAC_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB___S 0 + +#define UMAC_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB (0x00A3415C) +#define UMAC_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB___POR 0x00000000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S 0 +#define UMAC_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB___S 0 + +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0 (0x00A3416C) +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S 15 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0___S 0 + +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1 (0x00A34170) +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S 0 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1___S 0 + +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS (0x00A34174) +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S 15 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS___S 0 + +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER (0x00A34178) +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S 0 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER___S 0 + +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER (0x00A3417C) +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___S 0 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER___S 0 + +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS (0x00A34180) +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S 16 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S 0 +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF +#define UMAC_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS___S 0 + +#define UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB (0x00A34184) +#define UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB (0x00A34188) +#define UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_DATA (0x00A3418C) +#define UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_WBM_R0_TQM_RELEASE_RING_MSI1_DATA___S 0 + +#define UMAC_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET (0x00A34190) +#define UMAC_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_WBM_R0_REO_RELEASE_RING_BASE_LSB (0x00A34194) +#define UMAC_WBM_R0_REO_RELEASE_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_REO_RELEASE_RING_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_REO_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_REO_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_REO_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_WBM_R0_REO_RELEASE_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_REO_RELEASE_RING_BASE_LSB___S 0 + +#define UMAC_WBM_R0_REO_RELEASE_RING_BASE_MSB (0x00A34198) +#define UMAC_WBM_R0_REO_RELEASE_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_REO_RELEASE_RING_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_REO_RELEASE_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_WBM_R0_REO_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_REO_RELEASE_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_WBM_R0_REO_RELEASE_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_WBM_R0_REO_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_REO_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_WBM_R0_REO_RELEASE_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_WBM_R0_REO_RELEASE_RING_BASE_MSB___S 0 + +#define UMAC_WBM_R0_REO_RELEASE_RING_ID (0x00A3419C) +#define UMAC_WBM_R0_REO_RELEASE_RING_ID___RWC QCSR_REG_RW +#define UMAC_WBM_R0_REO_RELEASE_RING_ID___POR 0x00000000 +#define UMAC_WBM_R0_REO_RELEASE_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_WBM_R0_REO_RELEASE_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_WBM_R0_REO_RELEASE_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_WBM_R0_REO_RELEASE_RING_ID___M 0x000000FF +#define UMAC_WBM_R0_REO_RELEASE_RING_ID___S 0 + +#define UMAC_WBM_R0_REO_RELEASE_RING_STATUS (0x00A341A0) +#define UMAC_WBM_R0_REO_RELEASE_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_REO_RELEASE_RING_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_REO_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_WBM_R0_REO_RELEASE_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_WBM_R0_REO_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_WBM_R0_REO_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_WBM_R0_REO_RELEASE_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_WBM_R0_REO_RELEASE_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_WBM_R0_REO_RELEASE_RING_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_REO_RELEASE_RING_STATUS___S 0 + +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC (0x00A341A4) +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC___RWC QCSR_REG_RW +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC___POR 0x00000080 +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC___M 0x003FFFFF +#define UMAC_WBM_R0_REO_RELEASE_RING_MISC___S 0 + +#define UMAC_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB (0x00A341B0) +#define UMAC_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S 0 +#define UMAC_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB___S 0 + +#define UMAC_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB (0x00A341B4) +#define UMAC_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB___POR 0x00000000 +#define UMAC_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S 0 +#define UMAC_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB___S 0 + +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0 (0x00A341C4) +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S 15 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0___S 0 + +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1 (0x00A341C8) +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S 0 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1___S 0 + +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS (0x00A341CC) +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S 15 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS___S 0 + +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER (0x00A341D0) +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S 0 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER___S 0 + +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER (0x00A341D4) +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___S 0 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER___S 0 + +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS (0x00A341D8) +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S 16 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S 0 +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF +#define UMAC_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS___S 0 + +#define UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB (0x00A341DC) +#define UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB (0x00A341E0) +#define UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_WBM_R0_REO_RELEASE_RING_MSI1_DATA (0x00A341E4) +#define UMAC_WBM_R0_REO_RELEASE_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_WBM_R0_REO_RELEASE_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_WBM_R0_REO_RELEASE_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_WBM_R0_REO_RELEASE_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_WBM_R0_REO_RELEASE_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_WBM_R0_REO_RELEASE_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_WBM_R0_REO_RELEASE_RING_MSI1_DATA___S 0 + +#define UMAC_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET (0x00A341E8) +#define UMAC_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_WBM_R0_SW_RELEASE_RING_BASE_LSB (0x00A341EC) +#define UMAC_WBM_R0_SW_RELEASE_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_SW_RELEASE_RING_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_SW_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_SW_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_SW_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_WBM_R0_SW_RELEASE_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_SW_RELEASE_RING_BASE_LSB___S 0 + +#define UMAC_WBM_R0_SW_RELEASE_RING_BASE_MSB (0x00A341F0) +#define UMAC_WBM_R0_SW_RELEASE_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_SW_RELEASE_RING_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_SW_RELEASE_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_WBM_R0_SW_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_SW_RELEASE_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_WBM_R0_SW_RELEASE_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_WBM_R0_SW_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_SW_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_WBM_R0_SW_RELEASE_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_WBM_R0_SW_RELEASE_RING_BASE_MSB___S 0 + +#define UMAC_WBM_R0_SW_RELEASE_RING_ID (0x00A341F4) +#define UMAC_WBM_R0_SW_RELEASE_RING_ID___RWC QCSR_REG_RW +#define UMAC_WBM_R0_SW_RELEASE_RING_ID___POR 0x00000000 +#define UMAC_WBM_R0_SW_RELEASE_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_WBM_R0_SW_RELEASE_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_WBM_R0_SW_RELEASE_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_WBM_R0_SW_RELEASE_RING_ID___M 0x000000FF +#define UMAC_WBM_R0_SW_RELEASE_RING_ID___S 0 + +#define UMAC_WBM_R0_SW_RELEASE_RING_STATUS (0x00A341F8) +#define UMAC_WBM_R0_SW_RELEASE_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_SW_RELEASE_RING_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_SW_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_WBM_R0_SW_RELEASE_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_WBM_R0_SW_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_WBM_R0_SW_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_WBM_R0_SW_RELEASE_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_WBM_R0_SW_RELEASE_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_WBM_R0_SW_RELEASE_RING_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_SW_RELEASE_RING_STATUS___S 0 + +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC (0x00A341FC) +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC___RWC QCSR_REG_RW +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC___POR 0x00000080 +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC___M 0x003FFFFF +#define UMAC_WBM_R0_SW_RELEASE_RING_MISC___S 0 + +#define UMAC_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB (0x00A34208) +#define UMAC_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S 0 +#define UMAC_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB___S 0 + +#define UMAC_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB (0x00A3420C) +#define UMAC_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB___POR 0x00000000 +#define UMAC_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S 0 +#define UMAC_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB___S 0 + +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0 (0x00A3421C) +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S 15 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0___S 0 + +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1 (0x00A34220) +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S 0 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1___S 0 + +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS (0x00A34224) +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S 15 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS___S 0 + +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER (0x00A34228) +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S 0 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER___S 0 + +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER (0x00A3422C) +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___S 0 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER___S 0 + +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS (0x00A34230) +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S 16 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S 0 +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF +#define UMAC_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS___S 0 + +#define UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB (0x00A34234) +#define UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB (0x00A34238) +#define UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_WBM_R0_SW_RELEASE_RING_MSI1_DATA (0x00A3423C) +#define UMAC_WBM_R0_SW_RELEASE_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_WBM_R0_SW_RELEASE_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_WBM_R0_SW_RELEASE_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_WBM_R0_SW_RELEASE_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_WBM_R0_SW_RELEASE_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_WBM_R0_SW_RELEASE_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_WBM_R0_SW_RELEASE_RING_MSI1_DATA___S 0 + +#define UMAC_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET (0x00A34240) +#define UMAC_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_WBM_R0_FW_RELEASE_RING_BASE_LSB (0x00A34244) +#define UMAC_WBM_R0_FW_RELEASE_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_FW_RELEASE_RING_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_FW_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_FW_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_FW_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_WBM_R0_FW_RELEASE_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_FW_RELEASE_RING_BASE_LSB___S 0 + +#define UMAC_WBM_R0_FW_RELEASE_RING_BASE_MSB (0x00A34248) +#define UMAC_WBM_R0_FW_RELEASE_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_FW_RELEASE_RING_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_FW_RELEASE_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_WBM_R0_FW_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_FW_RELEASE_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_WBM_R0_FW_RELEASE_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_WBM_R0_FW_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_FW_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_WBM_R0_FW_RELEASE_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_WBM_R0_FW_RELEASE_RING_BASE_MSB___S 0 + +#define UMAC_WBM_R0_FW_RELEASE_RING_ID (0x00A3424C) +#define UMAC_WBM_R0_FW_RELEASE_RING_ID___RWC QCSR_REG_RW +#define UMAC_WBM_R0_FW_RELEASE_RING_ID___POR 0x00000000 +#define UMAC_WBM_R0_FW_RELEASE_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_WBM_R0_FW_RELEASE_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_WBM_R0_FW_RELEASE_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_WBM_R0_FW_RELEASE_RING_ID___M 0x000000FF +#define UMAC_WBM_R0_FW_RELEASE_RING_ID___S 0 + +#define UMAC_WBM_R0_FW_RELEASE_RING_STATUS (0x00A34250) +#define UMAC_WBM_R0_FW_RELEASE_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_FW_RELEASE_RING_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_FW_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_WBM_R0_FW_RELEASE_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_WBM_R0_FW_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_WBM_R0_FW_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_WBM_R0_FW_RELEASE_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_WBM_R0_FW_RELEASE_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_WBM_R0_FW_RELEASE_RING_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_FW_RELEASE_RING_STATUS___S 0 + +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC (0x00A34254) +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC___RWC QCSR_REG_RW +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC___POR 0x00000080 +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC___M 0x003FFFFF +#define UMAC_WBM_R0_FW_RELEASE_RING_MISC___S 0 + +#define UMAC_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB (0x00A34260) +#define UMAC_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S 0 +#define UMAC_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB___S 0 + +#define UMAC_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB (0x00A34264) +#define UMAC_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB___POR 0x00000000 +#define UMAC_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S 0 +#define UMAC_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB___S 0 + +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0 (0x00A34274) +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S 15 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0___S 0 + +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1 (0x00A34278) +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S 0 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1___S 0 + +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS (0x00A3427C) +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S 15 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS___S 0 + +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER (0x00A34280) +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S 0 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER___S 0 + +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER (0x00A34284) +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___S 0 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER___S 0 + +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS (0x00A34288) +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S 16 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S 0 +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF +#define UMAC_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS___S 0 + +#define UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB (0x00A3428C) +#define UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB (0x00A34290) +#define UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_WBM_R0_FW_RELEASE_RING_MSI1_DATA (0x00A34294) +#define UMAC_WBM_R0_FW_RELEASE_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_WBM_R0_FW_RELEASE_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_WBM_R0_FW_RELEASE_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_WBM_R0_FW_RELEASE_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_WBM_R0_FW_RELEASE_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_WBM_R0_FW_RELEASE_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_WBM_R0_FW_RELEASE_RING_MSI1_DATA___S 0 + +#define UMAC_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET (0x00A34298) +#define UMAC_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB (0x00A3429C) +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB___S 0 + +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB (0x00A342A0) +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB___S 0 + +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_ID (0x00A342A4) +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_ID___RWC QCSR_REG_RW +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_ID___POR 0x00000000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_ID___M 0x000000FF +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_ID___S 0 + +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_STATUS (0x00A342A8) +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_STATUS___S 0 + +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC (0x00A342AC) +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC___RWC QCSR_REG_RW +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC___POR 0x00000080 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC___M 0x003FFFFF +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MISC___S 0 + +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB (0x00A342B8) +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S 0 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB___S 0 + +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB (0x00A342BC) +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB___POR 0x00000000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S 0 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB___S 0 + +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0 (0x00A342CC) +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S 15 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0___S 0 + +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1 (0x00A342D0) +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S 0 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1___S 0 + +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS (0x00A342D4) +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S 15 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS___S 0 + +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER (0x00A342D8) +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S 0 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER___S 0 + +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER (0x00A342DC) +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER__MODE___S 0 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER___S 0 + +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS (0x00A342E0) +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S 16 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S 0 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS___S 0 + +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB (0x00A342E4) +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB (0x00A342E8) +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA (0x00A342EC) +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA___S 0 + +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET (0x00A342F0) +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB (0x00A343A4) +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB___S 0 + +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB (0x00A343A8) +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB___S 0 + +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_ID (0x00A343AC) +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_ID___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_ID___POR 0x00000000 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_ID__RING_ID___POR 0x00 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_ID__RING_ID___M 0x0000FF00 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_ID__RING_ID___S 8 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_ID___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_ID___S 0 + +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_STATUS (0x00A343B0) +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_STATUS___S 0 + +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC (0x00A343B4) +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC___POR 0x00000080 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__LOOP_CNT___POR 0x0 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__LOOP_CNT___M 0x03C00000 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__LOOP_CNT___S 22 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC___M 0x03FFFFFF +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MISC___S 0 + +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB (0x00A343B8) +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB___S 0 + +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB (0x00A343BC) +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB___S 0 + +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP (0x00A343C8) +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP___S 0 + +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS (0x00A343CC) +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS___S 0 + +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER (0x00A343D0) +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER___S 0 + +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB (0x00A343EC) +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB (0x00A343F0) +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA (0x00A343F4) +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA___S 0 + +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET (0x00A343F8) +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_LSB (0x00A343FC) +#define UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_LSB___S 0 + +#define UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_MSB (0x00A34400) +#define UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_WBM_R0_WBM2SW_BUF_RING_BASE_MSB___S 0 + +#define UMAC_WBM_R0_WBM2SW_BUF_RING_ID (0x00A34404) +#define UMAC_WBM_R0_WBM2SW_BUF_RING_ID___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW_BUF_RING_ID___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_ID__RING_ID___POR 0x00 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_ID__RING_ID___M 0x0000FF00 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_ID__RING_ID___S 8 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW_BUF_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_ID___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2SW_BUF_RING_ID___S 0 + +#define UMAC_WBM_R0_WBM2SW_BUF_RING_STATUS (0x00A34408) +#define UMAC_WBM_R0_WBM2SW_BUF_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM2SW_BUF_RING_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2SW_BUF_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW_BUF_RING_STATUS___S 0 + +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC (0x00A3440C) +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC___POR 0x00000080 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__LOOP_CNT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__LOOP_CNT___M 0x03C00000 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__LOOP_CNT___S 22 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC___M 0x03FFFFFF +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MISC___S 0 + +#define UMAC_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB (0x00A34410) +#define UMAC_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB___S 0 + +#define UMAC_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB (0x00A34414) +#define UMAC_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB___S 0 + +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP (0x00A34420) +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP___S 0 + +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS (0x00A34424) +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS___S 0 + +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER (0x00A34428) +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER___S 0 + +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB (0x00A34444) +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB (0x00A34448) +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA (0x00A3444C) +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA___S 0 + +#define UMAC_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET (0x00A34450) +#define UMAC_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_LSB (0x00A34454) +#define UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_LSB___S 0 + +#define UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_MSB (0x00A34458) +#define UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_WBM_R0_WBM2FW_BUF_RING_BASE_MSB___S 0 + +#define UMAC_WBM_R0_WBM2FW_BUF_RING_ID (0x00A3445C) +#define UMAC_WBM_R0_WBM2FW_BUF_RING_ID___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_BUF_RING_ID___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_ID__RING_ID___POR 0x00 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_ID__RING_ID___M 0x0000FF00 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_ID__RING_ID___S 8 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_WBM_R0_WBM2FW_BUF_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_ID___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2FW_BUF_RING_ID___S 0 + +#define UMAC_WBM_R0_WBM2FW_BUF_RING_STATUS (0x00A34460) +#define UMAC_WBM_R0_WBM2FW_BUF_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM2FW_BUF_RING_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2FW_BUF_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2FW_BUF_RING_STATUS___S 0 + +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC (0x00A34464) +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC___POR 0x00000080 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__LOOP_CNT___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__LOOP_CNT___M 0x03C00000 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__LOOP_CNT___S 22 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC___M 0x03FFFFFF +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MISC___S 0 + +#define UMAC_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB (0x00A34468) +#define UMAC_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB___S 0 + +#define UMAC_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB (0x00A3446C) +#define UMAC_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB___S 0 + +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP (0x00A34478) +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP___S 0 + +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS (0x00A3447C) +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS___S 0 + +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER (0x00A34480) +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER___S 0 + +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB (0x00A3449C) +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB (0x00A344A0) +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA (0x00A344A4) +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA___S 0 + +#define UMAC_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET (0x00A344A8) +#define UMAC_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB (0x00A344AC) +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB___S 0 + +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB (0x00A344B0) +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB___S 0 + +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_ID (0x00A344B4) +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_ID___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_ID___POR 0x00000000 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_ID__RING_ID___POR 0x00 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_ID__RING_ID___M 0x0000FF00 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_ID__RING_ID___S 8 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_ID___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_ID___S 0 + +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS (0x00A344B8) +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS___S 0 + +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC (0x00A344BC) +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC___POR 0x00000080 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__LOOP_CNT___POR 0x0 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__LOOP_CNT___M 0x03C00000 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__LOOP_CNT___S 22 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC___M 0x03FFFFFF +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MISC___S 0 + +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB (0x00A344C0) +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB___S 0 + +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB (0x00A344C4) +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB___S 0 + +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP (0x00A344D0) +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP___S 0 + +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS (0x00A344D4) +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS___S 0 + +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER (0x00A344D8) +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER___S 0 + +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB (0x00A344F4) +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB (0x00A344F8) +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA (0x00A344FC) +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA___S 0 + +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET (0x00A34500) +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB (0x00A345B4) +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB___S 0 + +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB (0x00A345B8) +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB___S 0 + +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_ID (0x00A345BC) +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_ID___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_ID___POR 0x00000000 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_ID__RING_ID___POR 0x00 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_ID__RING_ID___M 0x0000FF00 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_ID__RING_ID___S 8 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_ID___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_ID___S 0 + +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_STATUS (0x00A345C0) +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_STATUS___S 0 + +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC (0x00A345C4) +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC___POR 0x00000080 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__LOOP_CNT___POR 0x0 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__LOOP_CNT___M 0x03C00000 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__LOOP_CNT___S 22 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC___M 0x03FFFFFF +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MISC___S 0 + +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB (0x00A345C8) +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB___S 0 + +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB (0x00A345CC) +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB___S 0 + +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP (0x00A345D8) +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP___S 0 + +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS (0x00A345DC) +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS___S 0 + +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER (0x00A345E0) +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER___S 0 + +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB (0x00A345FC) +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB (0x00A34600) +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA (0x00A34604) +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA___S 0 + +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET (0x00A34608) +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_LSB (0x00A3460C) +#define UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_LSB___S 0 + +#define UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_MSB (0x00A34610) +#define UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_WBM_R0_WBM2REO_LINK_RING_BASE_MSB___S 0 + +#define UMAC_WBM_R0_WBM2REO_LINK_RING_ID (0x00A34614) +#define UMAC_WBM_R0_WBM2REO_LINK_RING_ID___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2REO_LINK_RING_ID___POR 0x00000000 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_ID__RING_ID___POR 0x00 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_ID__RING_ID___M 0x0000FF00 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_ID__RING_ID___S 8 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_WBM_R0_WBM2REO_LINK_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_ID___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2REO_LINK_RING_ID___S 0 + +#define UMAC_WBM_R0_WBM2REO_LINK_RING_STATUS (0x00A34618) +#define UMAC_WBM_R0_WBM2REO_LINK_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM2REO_LINK_RING_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2REO_LINK_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2REO_LINK_RING_STATUS___S 0 + +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC (0x00A3461C) +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC___POR 0x00000080 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__LOOP_CNT___POR 0x0 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__LOOP_CNT___M 0x03C00000 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__LOOP_CNT___S 22 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC___M 0x03FFFFFF +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MISC___S 0 + +#define UMAC_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB (0x00A34620) +#define UMAC_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB___S 0 + +#define UMAC_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB (0x00A34624) +#define UMAC_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB___S 0 + +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP (0x00A34630) +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP___S 0 + +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS (0x00A34634) +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS___S 0 + +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER (0x00A34638) +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER___S 0 + +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB (0x00A34654) +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB (0x00A34658) +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA (0x00A3465C) +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA___S 0 + +#define UMAC_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET (0x00A34660) +#define UMAC_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_LSB (0x00A34664) +#define UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_LSB___S 0 + +#define UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_MSB (0x00A34668) +#define UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_WBM_R0_WBM2SW_LINK_RING_BASE_MSB___S 0 + +#define UMAC_WBM_R0_WBM2SW_LINK_RING_ID (0x00A3466C) +#define UMAC_WBM_R0_WBM2SW_LINK_RING_ID___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW_LINK_RING_ID___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_ID__RING_ID___POR 0x00 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_ID__RING_ID___M 0x0000FF00 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_ID__RING_ID___S 8 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW_LINK_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_ID___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2SW_LINK_RING_ID___S 0 + +#define UMAC_WBM_R0_WBM2SW_LINK_RING_STATUS (0x00A34670) +#define UMAC_WBM_R0_WBM2SW_LINK_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM2SW_LINK_RING_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2SW_LINK_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW_LINK_RING_STATUS___S 0 + +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC (0x00A34674) +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC___POR 0x00000080 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__LOOP_CNT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__LOOP_CNT___M 0x03C00000 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__LOOP_CNT___S 22 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC___M 0x03FFFFFF +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MISC___S 0 + +#define UMAC_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB (0x00A34678) +#define UMAC_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB___S 0 + +#define UMAC_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB (0x00A3467C) +#define UMAC_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB___S 0 + +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP (0x00A34688) +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP___S 0 + +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS (0x00A3468C) +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS___S 0 + +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER (0x00A34690) +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER___S 0 + +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB (0x00A346AC) +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB (0x00A346B0) +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA (0x00A346B4) +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA___S 0 + +#define UMAC_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET (0x00A346B8) +#define UMAC_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_LSB (0x00A346BC) +#define UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_LSB___S 0 + +#define UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_MSB (0x00A346C0) +#define UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_WBM_R0_WBM2FW_LINK_RING_BASE_MSB___S 0 + +#define UMAC_WBM_R0_WBM2FW_LINK_RING_ID (0x00A346C4) +#define UMAC_WBM_R0_WBM2FW_LINK_RING_ID___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_LINK_RING_ID___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_ID__RING_ID___POR 0x00 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_ID__RING_ID___M 0x0000FF00 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_ID__RING_ID___S 8 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_WBM_R0_WBM2FW_LINK_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_ID___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2FW_LINK_RING_ID___S 0 + +#define UMAC_WBM_R0_WBM2FW_LINK_RING_STATUS (0x00A346C8) +#define UMAC_WBM_R0_WBM2FW_LINK_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM2FW_LINK_RING_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2FW_LINK_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2FW_LINK_RING_STATUS___S 0 + +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC (0x00A346CC) +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC___POR 0x00000080 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__LOOP_CNT___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__LOOP_CNT___M 0x03C00000 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__LOOP_CNT___S 22 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC___M 0x03FFFFFF +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MISC___S 0 + +#define UMAC_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB (0x00A346D0) +#define UMAC_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB___S 0 + +#define UMAC_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB (0x00A346D4) +#define UMAC_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB___S 0 + +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP (0x00A346E0) +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP___S 0 + +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS (0x00A346E4) +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS___S 0 + +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER (0x00A346E8) +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER___S 0 + +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB (0x00A34704) +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB (0x00A34708) +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA (0x00A3470C) +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA___S 0 + +#define UMAC_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET (0x00A34710) +#define UMAC_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB (0x00A34714) +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB___S 0 + +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB (0x00A34718) +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB___S 0 + +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_ID (0x00A3471C) +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_ID___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_ID___POR 0x00000000 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_ID__RING_ID___POR 0x00 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_ID__RING_ID___M 0x0000FF00 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_ID__RING_ID___S 8 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_ID___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_ID___S 0 + +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS (0x00A34720) +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS___S 0 + +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC (0x00A34724) +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC___POR 0x00000080 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__LOOP_CNT___POR 0x0 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__LOOP_CNT___M 0x03C00000 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__LOOP_CNT___S 22 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC___M 0x03FFFFFF +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MISC___S 0 + +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB (0x00A34728) +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB___S 0 + +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB (0x00A3472C) +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB___S 0 + +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP (0x00A34738) +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP___S 0 + +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS (0x00A3473C) +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS___S 0 + +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER (0x00A34740) +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER___S 0 + +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB (0x00A3475C) +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB (0x00A34760) +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA (0x00A34764) +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA___S 0 + +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET (0x00A34768) +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB (0x00A3481C) +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB (0x00A34820) +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_ID (0x00A34824) +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_ID___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_ID___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_ID__RING_ID___POR 0x00 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_ID__RING_ID___M 0x0000FF00 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_ID__RING_ID___S 8 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_ID___M 0x0000FFFF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_ID___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_STATUS (0x00A34828) +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_STATUS___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC (0x00A3482C) +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC___POR 0x00000080 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__LOOP_CNT___POR 0x0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__LOOP_CNT___M 0x03C00000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__LOOP_CNT___S 22 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC___M 0x03FFFFFF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MISC___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB (0x00A34830) +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB (0x00A34834) +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB (0x00A34838) +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB (0x00A3483C) +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP (0x00A34840) +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS (0x00A34844) +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER (0x00A34848) +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0 (0x00A3484C) +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S 15 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1 (0x00A34850) +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S 0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS (0x00A34854) +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S 15 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER (0x00A34858) +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S 0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER (0x00A3485C) +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER__MODE___S 0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS (0x00A34860) +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S 16 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S 0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB (0x00A34864) +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB (0x00A34868) +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA (0x00A3486C) +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET (0x00A34870) +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB (0x00A34874) +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB (0x00A34878) +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_ID (0x00A3487C) +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_ID___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_ID___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_ID__RING_ID___POR 0x00 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_ID__RING_ID___M 0x0000FF00 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_ID__RING_ID___S 8 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_ID___M 0x0000FFFF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_ID___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_STATUS (0x00A34880) +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_STATUS___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC (0x00A34884) +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC___POR 0x00000080 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__LOOP_CNT___POR 0x0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__LOOP_CNT___M 0x03C00000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__LOOP_CNT___S 22 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC___M 0x03FFFFFF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MISC___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB (0x00A34888) +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB (0x00A3488C) +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB (0x00A34890) +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB (0x00A34894) +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP (0x00A34898) +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS (0x00A3489C) +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER (0x00A348A0) +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0 (0x00A348A4) +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S 15 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1 (0x00A348A8) +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S 0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS (0x00A348AC) +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S 15 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER (0x00A348B0) +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S 0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER (0x00A348B4) +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER__MODE___S 0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS (0x00A348B8) +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S 16 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S 0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB (0x00A348BC) +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB (0x00A348C0) +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA (0x00A348C4) +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA___S 0 + +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET (0x00A348C8) +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB (0x00A348CC) +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB___S 0 + +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB (0x00A348D0) +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB___S 0 + +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_ID (0x00A348D4) +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_ID___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_ID___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_ID__RING_ID___POR 0x00 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_ID__RING_ID___M 0x0000FF00 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_ID__RING_ID___S 8 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_ID___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_ID___S 0 + +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_STATUS (0x00A348D8) +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_STATUS___S 0 + +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC (0x00A348DC) +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC___POR 0x00000080 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__LOOP_CNT___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__LOOP_CNT___M 0x03C00000 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__LOOP_CNT___S 22 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC___M 0x03FFFFFF +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MISC___S 0 + +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB (0x00A348E0) +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB___S 0 + +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB (0x00A348E4) +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB___S 0 + +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP (0x00A348F0) +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP___S 0 + +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS (0x00A348F4) +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS___S 0 + +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER (0x00A348F8) +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER___S 0 + +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB (0x00A34914) +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB (0x00A34918) +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA (0x00A3491C) +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA___S 0 + +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET (0x00A34920) +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB (0x00A34924) +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB___S 0 + +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB (0x00A34928) +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB__RING_SIZE___POR 0x00000 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB__RING_SIZE___M 0x0FFFFF00 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB___M 0x0FFFFFFF +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB___S 0 + +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_ID (0x00A3492C) +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_ID___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_ID___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_ID__RING_ID___POR 0x00 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_ID__RING_ID___M 0x0000FF00 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_ID__RING_ID___S 8 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_ID___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_ID___S 0 + +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_STATUS (0x00A34930) +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_STATUS___S 0 + +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC (0x00A34934) +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC___POR 0x00000080 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__LOOP_CNT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__LOOP_CNT___M 0x03C00000 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__LOOP_CNT___S 22 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC___M 0x03FFFFFF +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MISC___S 0 + +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB (0x00A34938) +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB___S 0 + +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB (0x00A3493C) +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB___S 0 + +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP (0x00A34948) +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP___S 0 + +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS (0x00A3494C) +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS___S 0 + +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER (0x00A34950) +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER___S 0 + +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB (0x00A3496C) +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB (0x00A34970) +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA (0x00A34974) +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA___S 0 + +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET (0x00A34978) +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB (0x00A3497C) +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB___S 0 + +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB (0x00A34980) +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB__RING_SIZE___POR 0x00000 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB__RING_SIZE___M 0x0FFFFF00 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB___M 0x0FFFFFFF +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB___S 0 + +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_ID (0x00A34984) +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_ID___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_ID___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_ID__RING_ID___POR 0x00 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_ID__RING_ID___M 0x0000FF00 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_ID__RING_ID___S 8 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_ID___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_ID___S 0 + +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_STATUS (0x00A34988) +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_STATUS___S 0 + +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC (0x00A3498C) +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC___POR 0x00000080 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__LOOP_CNT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__LOOP_CNT___M 0x03C00000 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__LOOP_CNT___S 22 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC___M 0x03FFFFFF +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MISC___S 0 + +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB (0x00A34990) +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB___S 0 + +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB (0x00A34994) +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB___S 0 + +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP (0x00A349A0) +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP___S 0 + +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS (0x00A349A4) +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS___S 0 + +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER (0x00A349A8) +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER___S 0 + +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB (0x00A349C4) +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB (0x00A349C8) +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA (0x00A349CC) +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA___S 0 + +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET (0x00A349D0) +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB (0x00A349D4) +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB___S 0 + +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB (0x00A349D8) +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB__RING_SIZE___POR 0x00000 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB__RING_SIZE___M 0x0FFFFF00 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB___M 0x0FFFFFFF +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB___S 0 + +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_ID (0x00A349DC) +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_ID___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_ID___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_ID__RING_ID___POR 0x00 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_ID__RING_ID___M 0x0000FF00 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_ID__RING_ID___S 8 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_ID___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_ID___S 0 + +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_STATUS (0x00A349E0) +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_STATUS___S 0 + +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC (0x00A349E4) +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC___POR 0x00000080 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__LOOP_CNT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__LOOP_CNT___M 0x03C00000 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__LOOP_CNT___S 22 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC___M 0x03FFFFFF +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MISC___S 0 + +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB (0x00A349E8) +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB___S 0 + +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB (0x00A349EC) +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB___S 0 + +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP (0x00A349F8) +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP___S 0 + +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS (0x00A349FC) +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS___S 0 + +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER (0x00A34A00) +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER___S 0 + +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB (0x00A34A1C) +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB (0x00A34A20) +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA (0x00A34A24) +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA___S 0 + +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET (0x00A34A28) +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB (0x00A34A2C) +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB___S 0 + +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB (0x00A34A30) +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB__RING_SIZE___POR 0x00000 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB__RING_SIZE___M 0x0FFFFF00 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB___M 0x0FFFFFFF +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB___S 0 + +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_ID (0x00A34A34) +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_ID___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_ID___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_ID__RING_ID___POR 0x00 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_ID__RING_ID___M 0x0000FF00 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_ID__RING_ID___S 8 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_ID___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_ID___S 0 + +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_STATUS (0x00A34A38) +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_STATUS___S 0 + +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC (0x00A34A3C) +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC___POR 0x00000080 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__LOOP_CNT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__LOOP_CNT___M 0x03C00000 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__LOOP_CNT___S 22 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC___M 0x03FFFFFF +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MISC___S 0 + +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB (0x00A34A40) +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB___S 0 + +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB (0x00A34A44) +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB___S 0 + +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP (0x00A34A50) +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP___S 0 + +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS (0x00A34A54) +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS___S 0 + +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER (0x00A34A58) +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER___S 0 + +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB (0x00A34A74) +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB (0x00A34A78) +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA (0x00A34A7C) +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA___S 0 + +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET (0x00A34A80) +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB (0x00A34A84) +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB___S 0 + +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB (0x00A34A88) +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB__RING_SIZE___POR 0x00000 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB__RING_SIZE___M 0x0FFFFF00 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB___M 0x0FFFFFFF +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB___S 0 + +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_ID (0x00A34A8C) +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_ID___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_ID___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_ID__RING_ID___POR 0x00 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_ID__RING_ID___M 0x0000FF00 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_ID__RING_ID___S 8 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_ID___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_ID___S 0 + +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_STATUS (0x00A34A90) +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_STATUS___S 0 + +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC (0x00A34A94) +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC___POR 0x00000080 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__LOOP_CNT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__LOOP_CNT___M 0x03C00000 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__LOOP_CNT___S 22 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC___M 0x03FFFFFF +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MISC___S 0 + +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB (0x00A34A98) +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB___S 0 + +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB (0x00A34A9C) +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB___S 0 + +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP (0x00A34AA8) +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP___S 0 + +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS (0x00A34AAC) +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS___S 0 + +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER (0x00A34AB0) +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER___S 0 + +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB (0x00A34ACC) +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB (0x00A34AD0) +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA (0x00A34AD4) +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA___S 0 + +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET (0x00A34AD8) +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_WBM_R1_END_OF_TEST_CHECK (0x00A36000) +#define UMAC_WBM_R1_END_OF_TEST_CHECK___RWC QCSR_REG_RW +#define UMAC_WBM_R1_END_OF_TEST_CHECK___POR 0x00000000 +#define UMAC_WBM_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0 +#define UMAC_WBM_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001 +#define UMAC_WBM_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S 0 +#define UMAC_WBM_R1_END_OF_TEST_CHECK___M 0x00000001 +#define UMAC_WBM_R1_END_OF_TEST_CHECK___S 0 + +#define UMAC_WBM_R1_TESTBUS_CTRL (0x00A36004) +#define UMAC_WBM_R1_TESTBUS_CTRL___RWC QCSR_REG_RW +#define UMAC_WBM_R1_TESTBUS_CTRL___POR 0x00000000 +#define UMAC_WBM_R1_TESTBUS_CTRL__SELECT_GXI___POR 0x00 +#define UMAC_WBM_R1_TESTBUS_CTRL__SELECT_WBM___POR 0x00 +#define UMAC_WBM_R1_TESTBUS_CTRL__SELECT_GXI___M 0x00001F00 +#define UMAC_WBM_R1_TESTBUS_CTRL__SELECT_GXI___S 8 +#define UMAC_WBM_R1_TESTBUS_CTRL__SELECT_WBM___M 0x0000003F +#define UMAC_WBM_R1_TESTBUS_CTRL__SELECT_WBM___S 0 +#define UMAC_WBM_R1_TESTBUS_CTRL___M 0x00001F3F +#define UMAC_WBM_R1_TESTBUS_CTRL___S 0 + +#define UMAC_WBM_R1_TESTBUS_LOWER (0x00A36008) +#define UMAC_WBM_R1_TESTBUS_LOWER___RWC QCSR_REG_RO +#define UMAC_WBM_R1_TESTBUS_LOWER___POR 0x00000000 +#define UMAC_WBM_R1_TESTBUS_LOWER__VALUE___POR 0x00000000 +#define UMAC_WBM_R1_TESTBUS_LOWER__VALUE___M 0xFFFFFFFF +#define UMAC_WBM_R1_TESTBUS_LOWER__VALUE___S 0 +#define UMAC_WBM_R1_TESTBUS_LOWER___M 0xFFFFFFFF +#define UMAC_WBM_R1_TESTBUS_LOWER___S 0 + +#define UMAC_WBM_R1_TESTBUS_HIGHER (0x00A3600C) +#define UMAC_WBM_R1_TESTBUS_HIGHER___RWC QCSR_REG_RO +#define UMAC_WBM_R1_TESTBUS_HIGHER___POR 0x00000000 +#define UMAC_WBM_R1_TESTBUS_HIGHER__VALUE___POR 0x00 +#define UMAC_WBM_R1_TESTBUS_HIGHER__VALUE___M 0x000000FF +#define UMAC_WBM_R1_TESTBUS_HIGHER__VALUE___S 0 +#define UMAC_WBM_R1_TESTBUS_HIGHER___M 0x000000FF +#define UMAC_WBM_R1_TESTBUS_HIGHER___S 0 + +#define UMAC_WBM_R1_SM_STATES_IX_0 (0x00A36010) +#define UMAC_WBM_R1_SM_STATES_IX_0___RWC QCSR_REG_RO +#define UMAC_WBM_R1_SM_STATES_IX_0___POR 0x00000000 +#define UMAC_WBM_R1_SM_STATES_IX_0__SW2_BUFFER_P_STATE___POR 0x0 +#define UMAC_WBM_R1_SM_STATES_IX_0__SW1_BUFFER_P_STATE___POR 0x0 +#define UMAC_WBM_R1_SM_STATES_IX_0__SW0_BUFFER_P_STATE___POR 0x0 +#define UMAC_WBM_R1_SM_STATES_IX_0__FW_BUFFER_P_STATE___POR 0x0 +#define UMAC_WBM_R1_SM_STATES_IX_0__LINK_DIST_P_STATE___POR 0x0 +#define UMAC_WBM_R1_SM_STATES_IX_0__LINK_DIST_C_STATE___POR 0x0 +#define UMAC_WBM_R1_SM_STATES_IX_0__BUFFER_DIST_P_STATE___POR 0x0 +#define UMAC_WBM_R1_SM_STATES_IX_0__BUFFER_DIST_C_STATE___POR 0x0 +#define UMAC_WBM_R1_SM_STATES_IX_0__LINK_IDLE_LIST_PROD_B_STATE___POR 0x0 +#define UMAC_WBM_R1_SM_STATES_IX_0__LINK_IDLE_LIST_PROD_P_STATE___POR 0x0 +#define UMAC_WBM_R1_SM_STATES_IX_0__BUFFER_IDLE_LIST_PROD_B_STATE___POR 0x0 +#define UMAC_WBM_R1_SM_STATES_IX_0__BUFFER_IDLE_LIST_PROD_P_STATE___POR 0x0 +#define UMAC_WBM_R1_SM_STATES_IX_0__RLS_REQ_PARSE_P_STATE___POR 0x0 +#define UMAC_WBM_R1_SM_STATES_IX_0__RLS_REQ_PARSE_C_STATE___POR 0x0 +#define UMAC_WBM_R1_SM_STATES_IX_0__SW2_BUFFER_P_STATE___M 0x60000000 +#define UMAC_WBM_R1_SM_STATES_IX_0__SW2_BUFFER_P_STATE___S 29 +#define UMAC_WBM_R1_SM_STATES_IX_0__SW1_BUFFER_P_STATE___M 0x18000000 +#define UMAC_WBM_R1_SM_STATES_IX_0__SW1_BUFFER_P_STATE___S 27 +#define UMAC_WBM_R1_SM_STATES_IX_0__SW0_BUFFER_P_STATE___M 0x06000000 +#define UMAC_WBM_R1_SM_STATES_IX_0__SW0_BUFFER_P_STATE___S 25 +#define UMAC_WBM_R1_SM_STATES_IX_0__FW_BUFFER_P_STATE___M 0x01800000 +#define UMAC_WBM_R1_SM_STATES_IX_0__FW_BUFFER_P_STATE___S 23 +#define UMAC_WBM_R1_SM_STATES_IX_0__LINK_DIST_P_STATE___M 0x00600000 +#define UMAC_WBM_R1_SM_STATES_IX_0__LINK_DIST_P_STATE___S 21 +#define UMAC_WBM_R1_SM_STATES_IX_0__LINK_DIST_C_STATE___M 0x00180000 +#define UMAC_WBM_R1_SM_STATES_IX_0__LINK_DIST_C_STATE___S 19 +#define UMAC_WBM_R1_SM_STATES_IX_0__BUFFER_DIST_P_STATE___M 0x00060000 +#define UMAC_WBM_R1_SM_STATES_IX_0__BUFFER_DIST_P_STATE___S 17 +#define UMAC_WBM_R1_SM_STATES_IX_0__BUFFER_DIST_C_STATE___M 0x00018000 +#define UMAC_WBM_R1_SM_STATES_IX_0__BUFFER_DIST_C_STATE___S 15 +#define UMAC_WBM_R1_SM_STATES_IX_0__LINK_IDLE_LIST_PROD_B_STATE___M 0x00007000 +#define UMAC_WBM_R1_SM_STATES_IX_0__LINK_IDLE_LIST_PROD_B_STATE___S 12 +#define UMAC_WBM_R1_SM_STATES_IX_0__LINK_IDLE_LIST_PROD_P_STATE___M 0x00000C00 +#define UMAC_WBM_R1_SM_STATES_IX_0__LINK_IDLE_LIST_PROD_P_STATE___S 10 +#define UMAC_WBM_R1_SM_STATES_IX_0__BUFFER_IDLE_LIST_PROD_B_STATE___M 0x00000380 +#define UMAC_WBM_R1_SM_STATES_IX_0__BUFFER_IDLE_LIST_PROD_B_STATE___S 7 +#define UMAC_WBM_R1_SM_STATES_IX_0__BUFFER_IDLE_LIST_PROD_P_STATE___M 0x00000060 +#define UMAC_WBM_R1_SM_STATES_IX_0__BUFFER_IDLE_LIST_PROD_P_STATE___S 5 +#define UMAC_WBM_R1_SM_STATES_IX_0__RLS_REQ_PARSE_P_STATE___M 0x0000001C +#define UMAC_WBM_R1_SM_STATES_IX_0__RLS_REQ_PARSE_P_STATE___S 2 +#define UMAC_WBM_R1_SM_STATES_IX_0__RLS_REQ_PARSE_C_STATE___M 0x00000003 +#define UMAC_WBM_R1_SM_STATES_IX_0__RLS_REQ_PARSE_C_STATE___S 0 +#define UMAC_WBM_R1_SM_STATES_IX_0___M 0x7FFFFFFF +#define UMAC_WBM_R1_SM_STATES_IX_0___S 0 + +#define UMAC_WBM_R1_SM_STATES_IX_1 (0x00A36014) +#define UMAC_WBM_R1_SM_STATES_IX_1___RWC QCSR_REG_RO +#define UMAC_WBM_R1_SM_STATES_IX_1___POR 0x00000000 +#define UMAC_WBM_R1_SM_STATES_IX_1__SW4_BUFFER_P_STATE___POR 0x0 +#define UMAC_WBM_R1_SM_STATES_IX_1__IDLE_LINK_DIST_NULL_PTR___POR 0x0 +#define UMAC_WBM_R1_SM_STATES_IX_1__IDLE_BUF_DIST_NULL_PTR___POR 0x0 +#define UMAC_WBM_R1_SM_STATES_IX_1__IDLE_LINK_SCAT_SRNG_C_STATE___POR 0x0 +#define UMAC_WBM_R1_SM_STATES_IX_1__IDLE_LINK_SCAT_SRNG_P_STATE___POR 0x0 +#define UMAC_WBM_R1_SM_STATES_IX_1__IDLE_BUF_SCAT_SRNG_C_STATE___POR 0x0 +#define UMAC_WBM_R1_SM_STATES_IX_1__IDLE_BUF_SCAT_SRNG_P_STATE___POR 0x0 +#define UMAC_WBM_R1_SM_STATES_IX_1__IDLE_LINK_SRNG_C_STATE___POR 0x0 +#define UMAC_WBM_R1_SM_STATES_IX_1__IDLE_LINK_SRNG_P_STATE___POR 0x0 +#define UMAC_WBM_R1_SM_STATES_IX_1__IDLE_BUF_SRNG_C_STATE___POR 0x0 +#define UMAC_WBM_R1_SM_STATES_IX_1__IDLE_BUF_SRNG_P_STATE___POR 0x0 +#define UMAC_WBM_R1_SM_STATES_IX_1__LINK_ZERO_OUT_STATE___POR 0x0 +#define UMAC_WBM_R1_SM_STATES_IX_1__SW3_BUFFER_P_STATE___POR 0x0 +#define UMAC_WBM_R1_SM_STATES_IX_1__SW4_BUFFER_P_STATE___M 0xC0000000 +#define UMAC_WBM_R1_SM_STATES_IX_1__SW4_BUFFER_P_STATE___S 30 +#define UMAC_WBM_R1_SM_STATES_IX_1__IDLE_LINK_DIST_NULL_PTR___M 0x20000000 +#define UMAC_WBM_R1_SM_STATES_IX_1__IDLE_LINK_DIST_NULL_PTR___S 29 +#define UMAC_WBM_R1_SM_STATES_IX_1__IDLE_BUF_DIST_NULL_PTR___M 0x10000000 +#define UMAC_WBM_R1_SM_STATES_IX_1__IDLE_BUF_DIST_NULL_PTR___S 28 +#define UMAC_WBM_R1_SM_STATES_IX_1__IDLE_LINK_SCAT_SRNG_C_STATE___M 0x0E000000 +#define UMAC_WBM_R1_SM_STATES_IX_1__IDLE_LINK_SCAT_SRNG_C_STATE___S 25 +#define UMAC_WBM_R1_SM_STATES_IX_1__IDLE_LINK_SCAT_SRNG_P_STATE___M 0x01C00000 +#define UMAC_WBM_R1_SM_STATES_IX_1__IDLE_LINK_SCAT_SRNG_P_STATE___S 22 +#define UMAC_WBM_R1_SM_STATES_IX_1__IDLE_BUF_SCAT_SRNG_C_STATE___M 0x00380000 +#define UMAC_WBM_R1_SM_STATES_IX_1__IDLE_BUF_SCAT_SRNG_C_STATE___S 19 +#define UMAC_WBM_R1_SM_STATES_IX_1__IDLE_BUF_SCAT_SRNG_P_STATE___M 0x00070000 +#define UMAC_WBM_R1_SM_STATES_IX_1__IDLE_BUF_SCAT_SRNG_P_STATE___S 16 +#define UMAC_WBM_R1_SM_STATES_IX_1__IDLE_LINK_SRNG_C_STATE___M 0x0000E000 +#define UMAC_WBM_R1_SM_STATES_IX_1__IDLE_LINK_SRNG_C_STATE___S 13 +#define UMAC_WBM_R1_SM_STATES_IX_1__IDLE_LINK_SRNG_P_STATE___M 0x00001C00 +#define UMAC_WBM_R1_SM_STATES_IX_1__IDLE_LINK_SRNG_P_STATE___S 10 +#define UMAC_WBM_R1_SM_STATES_IX_1__IDLE_BUF_SRNG_C_STATE___M 0x00000380 +#define UMAC_WBM_R1_SM_STATES_IX_1__IDLE_BUF_SRNG_C_STATE___S 7 +#define UMAC_WBM_R1_SM_STATES_IX_1__IDLE_BUF_SRNG_P_STATE___M 0x00000070 +#define UMAC_WBM_R1_SM_STATES_IX_1__IDLE_BUF_SRNG_P_STATE___S 4 +#define UMAC_WBM_R1_SM_STATES_IX_1__LINK_ZERO_OUT_STATE___M 0x0000000C +#define UMAC_WBM_R1_SM_STATES_IX_1__LINK_ZERO_OUT_STATE___S 2 +#define UMAC_WBM_R1_SM_STATES_IX_1__SW3_BUFFER_P_STATE___M 0x00000003 +#define UMAC_WBM_R1_SM_STATES_IX_1__SW3_BUFFER_P_STATE___S 0 +#define UMAC_WBM_R1_SM_STATES_IX_1___M 0xFFFFFFFF +#define UMAC_WBM_R1_SM_STATES_IX_1___S 0 + +#define UMAC_WBM_R1_EVENTMASK_IX_0 (0x00A36018) +#define UMAC_WBM_R1_EVENTMASK_IX_0___RWC QCSR_REG_RW +#define UMAC_WBM_R1_EVENTMASK_IX_0___POR 0xFFFFFFFF +#define UMAC_WBM_R1_EVENTMASK_IX_0__MASK___POR 0xFFFFFFFF +#define UMAC_WBM_R1_EVENTMASK_IX_0__MASK___M 0xFFFFFFFF +#define UMAC_WBM_R1_EVENTMASK_IX_0__MASK___S 0 +#define UMAC_WBM_R1_EVENTMASK_IX_0___M 0xFFFFFFFF +#define UMAC_WBM_R1_EVENTMASK_IX_0___S 0 + +#define UMAC_WBM_R1_EVENTMASK_IX_1 (0x00A3601C) +#define UMAC_WBM_R1_EVENTMASK_IX_1___RWC QCSR_REG_RW +#define UMAC_WBM_R1_EVENTMASK_IX_1___POR 0xFFFFFFFF +#define UMAC_WBM_R1_EVENTMASK_IX_1__MASK___POR 0xFFFFFFFF +#define UMAC_WBM_R1_EVENTMASK_IX_1__MASK___M 0xFFFFFFFF +#define UMAC_WBM_R1_EVENTMASK_IX_1__MASK___S 0 +#define UMAC_WBM_R1_EVENTMASK_IX_1___M 0xFFFFFFFF +#define UMAC_WBM_R1_EVENTMASK_IX_1___S 0 + +#define UMAC_WBM_R1_EVENTMASK_IX_2 (0x00A36020) +#define UMAC_WBM_R1_EVENTMASK_IX_2___RWC QCSR_REG_RW +#define UMAC_WBM_R1_EVENTMASK_IX_2___POR 0xFFFFFFFF +#define UMAC_WBM_R1_EVENTMASK_IX_2__MASK___POR 0xFFFFFFFF +#define UMAC_WBM_R1_EVENTMASK_IX_2__MASK___M 0xFFFFFFFF +#define UMAC_WBM_R1_EVENTMASK_IX_2__MASK___S 0 +#define UMAC_WBM_R1_EVENTMASK_IX_2___M 0xFFFFFFFF +#define UMAC_WBM_R1_EVENTMASK_IX_2___S 0 + +#define UMAC_WBM_R1_EVENTMASK_IX_3 (0x00A36024) +#define UMAC_WBM_R1_EVENTMASK_IX_3___RWC QCSR_REG_RW +#define UMAC_WBM_R1_EVENTMASK_IX_3___POR 0xFFFFFFFF +#define UMAC_WBM_R1_EVENTMASK_IX_3__MASK___POR 0xFFFFFFFF +#define UMAC_WBM_R1_EVENTMASK_IX_3__MASK___M 0xFFFFFFFF +#define UMAC_WBM_R1_EVENTMASK_IX_3__MASK___S 0 +#define UMAC_WBM_R1_EVENTMASK_IX_3___M 0xFFFFFFFF +#define UMAC_WBM_R1_EVENTMASK_IX_3___S 0 + +#define UMAC_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL (0x00A36028) +#define UMAC_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL___RWC QCSR_REG_RW +#define UMAC_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL___POR 0x7FFE0002 +#define UMAC_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___POR 0x3FFF +#define UMAC_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___POR 0x0000 +#define UMAC_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___POR 0x1 +#define UMAC_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___POR 0x0 +#define UMAC_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___M 0xFFFE0000 +#define UMAC_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___S 17 +#define UMAC_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___M 0x0001FFFC +#define UMAC_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___S 2 +#define UMAC_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___M 0x00000002 +#define UMAC_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___S 1 +#define UMAC_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___M 0x00000001 +#define UMAC_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___S 0 +#define UMAC_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL___M 0xFFFFFFFF +#define UMAC_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL___S 0 + +#define UMAC_WBM_R2_PPE_RELEASE_RING_HP (0x00A37000) +#define UMAC_WBM_R2_PPE_RELEASE_RING_HP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_PPE_RELEASE_RING_HP___POR 0x00000000 +#define UMAC_WBM_R2_PPE_RELEASE_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_WBM_R2_PPE_RELEASE_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_PPE_RELEASE_RING_HP__HEAD_PTR___S 0 +#define UMAC_WBM_R2_PPE_RELEASE_RING_HP___M 0x0000FFFF +#define UMAC_WBM_R2_PPE_RELEASE_RING_HP___S 0 + +#define UMAC_WBM_R2_PPE_RELEASE_RING_TP (0x00A37004) +#define UMAC_WBM_R2_PPE_RELEASE_RING_TP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_PPE_RELEASE_RING_TP___POR 0x00000000 +#define UMAC_WBM_R2_PPE_RELEASE_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_WBM_R2_PPE_RELEASE_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_PPE_RELEASE_RING_TP__TAIL_PTR___S 0 +#define UMAC_WBM_R2_PPE_RELEASE_RING_TP___M 0x0000FFFF +#define UMAC_WBM_R2_PPE_RELEASE_RING_TP___S 0 + +#define UMAC_WBM_R2_TQM_RELEASE_RING_HP (0x00A37008) +#define UMAC_WBM_R2_TQM_RELEASE_RING_HP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_TQM_RELEASE_RING_HP___POR 0x00000000 +#define UMAC_WBM_R2_TQM_RELEASE_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_WBM_R2_TQM_RELEASE_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_TQM_RELEASE_RING_HP__HEAD_PTR___S 0 +#define UMAC_WBM_R2_TQM_RELEASE_RING_HP___M 0x0000FFFF +#define UMAC_WBM_R2_TQM_RELEASE_RING_HP___S 0 + +#define UMAC_WBM_R2_TQM_RELEASE_RING_TP (0x00A3700C) +#define UMAC_WBM_R2_TQM_RELEASE_RING_TP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_TQM_RELEASE_RING_TP___POR 0x00000000 +#define UMAC_WBM_R2_TQM_RELEASE_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_WBM_R2_TQM_RELEASE_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_TQM_RELEASE_RING_TP__TAIL_PTR___S 0 +#define UMAC_WBM_R2_TQM_RELEASE_RING_TP___M 0x0000FFFF +#define UMAC_WBM_R2_TQM_RELEASE_RING_TP___S 0 + +#define UMAC_WBM_R2_REO_RELEASE_RING_HP (0x00A37010) +#define UMAC_WBM_R2_REO_RELEASE_RING_HP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_REO_RELEASE_RING_HP___POR 0x00000000 +#define UMAC_WBM_R2_REO_RELEASE_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_WBM_R2_REO_RELEASE_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_REO_RELEASE_RING_HP__HEAD_PTR___S 0 +#define UMAC_WBM_R2_REO_RELEASE_RING_HP___M 0x0000FFFF +#define UMAC_WBM_R2_REO_RELEASE_RING_HP___S 0 + +#define UMAC_WBM_R2_REO_RELEASE_RING_TP (0x00A37014) +#define UMAC_WBM_R2_REO_RELEASE_RING_TP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_REO_RELEASE_RING_TP___POR 0x00000000 +#define UMAC_WBM_R2_REO_RELEASE_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_WBM_R2_REO_RELEASE_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_REO_RELEASE_RING_TP__TAIL_PTR___S 0 +#define UMAC_WBM_R2_REO_RELEASE_RING_TP___M 0x0000FFFF +#define UMAC_WBM_R2_REO_RELEASE_RING_TP___S 0 + +#define UMAC_WBM_R2_SW_RELEASE_RING_HP (0x00A37018) +#define UMAC_WBM_R2_SW_RELEASE_RING_HP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_SW_RELEASE_RING_HP___POR 0x00000000 +#define UMAC_WBM_R2_SW_RELEASE_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_WBM_R2_SW_RELEASE_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_SW_RELEASE_RING_HP__HEAD_PTR___S 0 +#define UMAC_WBM_R2_SW_RELEASE_RING_HP___M 0x0000FFFF +#define UMAC_WBM_R2_SW_RELEASE_RING_HP___S 0 + +#define UMAC_WBM_R2_SW_RELEASE_RING_TP (0x00A3701C) +#define UMAC_WBM_R2_SW_RELEASE_RING_TP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_SW_RELEASE_RING_TP___POR 0x00000000 +#define UMAC_WBM_R2_SW_RELEASE_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_WBM_R2_SW_RELEASE_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_SW_RELEASE_RING_TP__TAIL_PTR___S 0 +#define UMAC_WBM_R2_SW_RELEASE_RING_TP___M 0x0000FFFF +#define UMAC_WBM_R2_SW_RELEASE_RING_TP___S 0 + +#define UMAC_WBM_R2_FW_RELEASE_RING_HP (0x00A37020) +#define UMAC_WBM_R2_FW_RELEASE_RING_HP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_FW_RELEASE_RING_HP___POR 0x00000000 +#define UMAC_WBM_R2_FW_RELEASE_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_WBM_R2_FW_RELEASE_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_FW_RELEASE_RING_HP__HEAD_PTR___S 0 +#define UMAC_WBM_R2_FW_RELEASE_RING_HP___M 0x0000FFFF +#define UMAC_WBM_R2_FW_RELEASE_RING_HP___S 0 + +#define UMAC_WBM_R2_FW_RELEASE_RING_TP (0x00A37024) +#define UMAC_WBM_R2_FW_RELEASE_RING_TP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_FW_RELEASE_RING_TP___POR 0x00000000 +#define UMAC_WBM_R2_FW_RELEASE_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_WBM_R2_FW_RELEASE_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_FW_RELEASE_RING_TP__TAIL_PTR___S 0 +#define UMAC_WBM_R2_FW_RELEASE_RING_TP___M 0x0000FFFF +#define UMAC_WBM_R2_FW_RELEASE_RING_TP___S 0 + +#define UMAC_WBM_R2_RXDMA0_RELEASE_RING_HP (0x00A37028) +#define UMAC_WBM_R2_RXDMA0_RELEASE_RING_HP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_RXDMA0_RELEASE_RING_HP___POR 0x00000000 +#define UMAC_WBM_R2_RXDMA0_RELEASE_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_WBM_R2_RXDMA0_RELEASE_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_RXDMA0_RELEASE_RING_HP__HEAD_PTR___S 0 +#define UMAC_WBM_R2_RXDMA0_RELEASE_RING_HP___M 0x0000FFFF +#define UMAC_WBM_R2_RXDMA0_RELEASE_RING_HP___S 0 + +#define UMAC_WBM_R2_RXDMA0_RELEASE_RING_TP (0x00A3702C) +#define UMAC_WBM_R2_RXDMA0_RELEASE_RING_TP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_RXDMA0_RELEASE_RING_TP___POR 0x00000000 +#define UMAC_WBM_R2_RXDMA0_RELEASE_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_WBM_R2_RXDMA0_RELEASE_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_RXDMA0_RELEASE_RING_TP__TAIL_PTR___S 0 +#define UMAC_WBM_R2_RXDMA0_RELEASE_RING_TP___M 0x0000FFFF +#define UMAC_WBM_R2_RXDMA0_RELEASE_RING_TP___S 0 + +#define UMAC_WBM_R2_WBM2PPE_BUF_RING_HP (0x00A37040) +#define UMAC_WBM_R2_WBM2PPE_BUF_RING_HP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_WBM2PPE_BUF_RING_HP___POR 0x00000000 +#define UMAC_WBM_R2_WBM2PPE_BUF_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_WBM_R2_WBM2PPE_BUF_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2PPE_BUF_RING_HP__HEAD_PTR___S 0 +#define UMAC_WBM_R2_WBM2PPE_BUF_RING_HP___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2PPE_BUF_RING_HP___S 0 + +#define UMAC_WBM_R2_WBM2PPE_BUF_RING_TP (0x00A37044) +#define UMAC_WBM_R2_WBM2PPE_BUF_RING_TP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_WBM2PPE_BUF_RING_TP___POR 0x00000000 +#define UMAC_WBM_R2_WBM2PPE_BUF_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_WBM_R2_WBM2PPE_BUF_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2PPE_BUF_RING_TP__TAIL_PTR___S 0 +#define UMAC_WBM_R2_WBM2PPE_BUF_RING_TP___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2PPE_BUF_RING_TP___S 0 + +#define UMAC_WBM_R2_WBM2SW_BUF_RING_HP (0x00A37048) +#define UMAC_WBM_R2_WBM2SW_BUF_RING_HP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_WBM2SW_BUF_RING_HP___POR 0x00000000 +#define UMAC_WBM_R2_WBM2SW_BUF_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_WBM_R2_WBM2SW_BUF_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2SW_BUF_RING_HP__HEAD_PTR___S 0 +#define UMAC_WBM_R2_WBM2SW_BUF_RING_HP___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2SW_BUF_RING_HP___S 0 + +#define UMAC_WBM_R2_WBM2SW_BUF_RING_TP (0x00A3704C) +#define UMAC_WBM_R2_WBM2SW_BUF_RING_TP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_WBM2SW_BUF_RING_TP___POR 0x00000000 +#define UMAC_WBM_R2_WBM2SW_BUF_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_WBM_R2_WBM2SW_BUF_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2SW_BUF_RING_TP__TAIL_PTR___S 0 +#define UMAC_WBM_R2_WBM2SW_BUF_RING_TP___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2SW_BUF_RING_TP___S 0 + +#define UMAC_WBM_R2_WBM2FW_BUF_RING_HP (0x00A37050) +#define UMAC_WBM_R2_WBM2FW_BUF_RING_HP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_WBM2FW_BUF_RING_HP___POR 0x00000000 +#define UMAC_WBM_R2_WBM2FW_BUF_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_WBM_R2_WBM2FW_BUF_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2FW_BUF_RING_HP__HEAD_PTR___S 0 +#define UMAC_WBM_R2_WBM2FW_BUF_RING_HP___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2FW_BUF_RING_HP___S 0 + +#define UMAC_WBM_R2_WBM2FW_BUF_RING_TP (0x00A37054) +#define UMAC_WBM_R2_WBM2FW_BUF_RING_TP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_WBM2FW_BUF_RING_TP___POR 0x00000000 +#define UMAC_WBM_R2_WBM2FW_BUF_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_WBM_R2_WBM2FW_BUF_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2FW_BUF_RING_TP__TAIL_PTR___S 0 +#define UMAC_WBM_R2_WBM2FW_BUF_RING_TP___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2FW_BUF_RING_TP___S 0 + +#define UMAC_WBM_R2_WBM2RXDMA0_BUF_RING_HP (0x00A37058) +#define UMAC_WBM_R2_WBM2RXDMA0_BUF_RING_HP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_WBM2RXDMA0_BUF_RING_HP___POR 0x00000000 +#define UMAC_WBM_R2_WBM2RXDMA0_BUF_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_WBM_R2_WBM2RXDMA0_BUF_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2RXDMA0_BUF_RING_HP__HEAD_PTR___S 0 +#define UMAC_WBM_R2_WBM2RXDMA0_BUF_RING_HP___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2RXDMA0_BUF_RING_HP___S 0 + +#define UMAC_WBM_R2_WBM2RXDMA0_BUF_RING_TP (0x00A3705C) +#define UMAC_WBM_R2_WBM2RXDMA0_BUF_RING_TP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_WBM2RXDMA0_BUF_RING_TP___POR 0x00000000 +#define UMAC_WBM_R2_WBM2RXDMA0_BUF_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_WBM_R2_WBM2RXDMA0_BUF_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2RXDMA0_BUF_RING_TP__TAIL_PTR___S 0 +#define UMAC_WBM_R2_WBM2RXDMA0_BUF_RING_TP___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2RXDMA0_BUF_RING_TP___S 0 + +#define UMAC_WBM_R2_WBM2TQM_LINK_RING_HP (0x00A37070) +#define UMAC_WBM_R2_WBM2TQM_LINK_RING_HP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_WBM2TQM_LINK_RING_HP___POR 0x00000000 +#define UMAC_WBM_R2_WBM2TQM_LINK_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_WBM_R2_WBM2TQM_LINK_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2TQM_LINK_RING_HP__HEAD_PTR___S 0 +#define UMAC_WBM_R2_WBM2TQM_LINK_RING_HP___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2TQM_LINK_RING_HP___S 0 + +#define UMAC_WBM_R2_WBM2TQM_LINK_RING_TP (0x00A37074) +#define UMAC_WBM_R2_WBM2TQM_LINK_RING_TP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_WBM2TQM_LINK_RING_TP___POR 0x00000000 +#define UMAC_WBM_R2_WBM2TQM_LINK_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_WBM_R2_WBM2TQM_LINK_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2TQM_LINK_RING_TP__TAIL_PTR___S 0 +#define UMAC_WBM_R2_WBM2TQM_LINK_RING_TP___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2TQM_LINK_RING_TP___S 0 + +#define UMAC_WBM_R2_WBM2REO_LINK_RING_HP (0x00A37078) +#define UMAC_WBM_R2_WBM2REO_LINK_RING_HP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_WBM2REO_LINK_RING_HP___POR 0x00000000 +#define UMAC_WBM_R2_WBM2REO_LINK_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_WBM_R2_WBM2REO_LINK_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2REO_LINK_RING_HP__HEAD_PTR___S 0 +#define UMAC_WBM_R2_WBM2REO_LINK_RING_HP___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2REO_LINK_RING_HP___S 0 + +#define UMAC_WBM_R2_WBM2REO_LINK_RING_TP (0x00A3707C) +#define UMAC_WBM_R2_WBM2REO_LINK_RING_TP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_WBM2REO_LINK_RING_TP___POR 0x00000000 +#define UMAC_WBM_R2_WBM2REO_LINK_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_WBM_R2_WBM2REO_LINK_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2REO_LINK_RING_TP__TAIL_PTR___S 0 +#define UMAC_WBM_R2_WBM2REO_LINK_RING_TP___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2REO_LINK_RING_TP___S 0 + +#define UMAC_WBM_R2_WBM2SW_LINK_RING_HP (0x00A37080) +#define UMAC_WBM_R2_WBM2SW_LINK_RING_HP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_WBM2SW_LINK_RING_HP___POR 0x00000000 +#define UMAC_WBM_R2_WBM2SW_LINK_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_WBM_R2_WBM2SW_LINK_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2SW_LINK_RING_HP__HEAD_PTR___S 0 +#define UMAC_WBM_R2_WBM2SW_LINK_RING_HP___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2SW_LINK_RING_HP___S 0 + +#define UMAC_WBM_R2_WBM2SW_LINK_RING_TP (0x00A37084) +#define UMAC_WBM_R2_WBM2SW_LINK_RING_TP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_WBM2SW_LINK_RING_TP___POR 0x00000000 +#define UMAC_WBM_R2_WBM2SW_LINK_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_WBM_R2_WBM2SW_LINK_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2SW_LINK_RING_TP__TAIL_PTR___S 0 +#define UMAC_WBM_R2_WBM2SW_LINK_RING_TP___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2SW_LINK_RING_TP___S 0 + +#define UMAC_WBM_R2_WBM2FW_LINK_RING_HP (0x00A37088) +#define UMAC_WBM_R2_WBM2FW_LINK_RING_HP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_WBM2FW_LINK_RING_HP___POR 0x00000000 +#define UMAC_WBM_R2_WBM2FW_LINK_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_WBM_R2_WBM2FW_LINK_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2FW_LINK_RING_HP__HEAD_PTR___S 0 +#define UMAC_WBM_R2_WBM2FW_LINK_RING_HP___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2FW_LINK_RING_HP___S 0 + +#define UMAC_WBM_R2_WBM2FW_LINK_RING_TP (0x00A3708C) +#define UMAC_WBM_R2_WBM2FW_LINK_RING_TP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_WBM2FW_LINK_RING_TP___POR 0x00000000 +#define UMAC_WBM_R2_WBM2FW_LINK_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_WBM_R2_WBM2FW_LINK_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2FW_LINK_RING_TP__TAIL_PTR___S 0 +#define UMAC_WBM_R2_WBM2FW_LINK_RING_TP___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2FW_LINK_RING_TP___S 0 + +#define UMAC_WBM_R2_WBM2RXDMA0_LINK_RING_HP (0x00A37090) +#define UMAC_WBM_R2_WBM2RXDMA0_LINK_RING_HP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_WBM2RXDMA0_LINK_RING_HP___POR 0x00000000 +#define UMAC_WBM_R2_WBM2RXDMA0_LINK_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_WBM_R2_WBM2RXDMA0_LINK_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2RXDMA0_LINK_RING_HP__HEAD_PTR___S 0 +#define UMAC_WBM_R2_WBM2RXDMA0_LINK_RING_HP___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2RXDMA0_LINK_RING_HP___S 0 + +#define UMAC_WBM_R2_WBM2RXDMA0_LINK_RING_TP (0x00A37094) +#define UMAC_WBM_R2_WBM2RXDMA0_LINK_RING_TP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_WBM2RXDMA0_LINK_RING_TP___POR 0x00000000 +#define UMAC_WBM_R2_WBM2RXDMA0_LINK_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_WBM_R2_WBM2RXDMA0_LINK_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2RXDMA0_LINK_RING_TP__TAIL_PTR___S 0 +#define UMAC_WBM_R2_WBM2RXDMA0_LINK_RING_TP___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2RXDMA0_LINK_RING_TP___S 0 + +#define UMAC_WBM_R2_WBM_IDLE_BUF_RING_HP (0x00A370A8) +#define UMAC_WBM_R2_WBM_IDLE_BUF_RING_HP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_WBM_IDLE_BUF_RING_HP___POR 0x00000000 +#define UMAC_WBM_R2_WBM_IDLE_BUF_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_WBM_R2_WBM_IDLE_BUF_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_WBM_IDLE_BUF_RING_HP__HEAD_PTR___S 0 +#define UMAC_WBM_R2_WBM_IDLE_BUF_RING_HP___M 0x0000FFFF +#define UMAC_WBM_R2_WBM_IDLE_BUF_RING_HP___S 0 + +#define UMAC_WBM_R2_WBM_IDLE_BUF_RING_TP (0x00A370AC) +#define UMAC_WBM_R2_WBM_IDLE_BUF_RING_TP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_WBM_IDLE_BUF_RING_TP___POR 0x00000000 +#define UMAC_WBM_R2_WBM_IDLE_BUF_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_WBM_R2_WBM_IDLE_BUF_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_WBM_IDLE_BUF_RING_TP__TAIL_PTR___S 0 +#define UMAC_WBM_R2_WBM_IDLE_BUF_RING_TP___M 0x0000FFFF +#define UMAC_WBM_R2_WBM_IDLE_BUF_RING_TP___S 0 + +#define UMAC_WBM_R2_WBM_IDLE_LINK_RING_HP (0x00A370B0) +#define UMAC_WBM_R2_WBM_IDLE_LINK_RING_HP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_WBM_IDLE_LINK_RING_HP___POR 0x00000000 +#define UMAC_WBM_R2_WBM_IDLE_LINK_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_WBM_R2_WBM_IDLE_LINK_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_WBM_IDLE_LINK_RING_HP__HEAD_PTR___S 0 +#define UMAC_WBM_R2_WBM_IDLE_LINK_RING_HP___M 0x0000FFFF +#define UMAC_WBM_R2_WBM_IDLE_LINK_RING_HP___S 0 + +#define UMAC_WBM_R2_WBM_IDLE_LINK_RING_TP (0x00A370B4) +#define UMAC_WBM_R2_WBM_IDLE_LINK_RING_TP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_WBM_IDLE_LINK_RING_TP___POR 0x00000000 +#define UMAC_WBM_R2_WBM_IDLE_LINK_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_WBM_R2_WBM_IDLE_LINK_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_WBM_IDLE_LINK_RING_TP__TAIL_PTR___S 0 +#define UMAC_WBM_R2_WBM_IDLE_LINK_RING_TP___M 0x0000FFFF +#define UMAC_WBM_R2_WBM_IDLE_LINK_RING_TP___S 0 + +#define UMAC_WBM_R2_WBM2FW_RELEASE_RING_HP (0x00A370B8) +#define UMAC_WBM_R2_WBM2FW_RELEASE_RING_HP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_WBM2FW_RELEASE_RING_HP___POR 0x00000000 +#define UMAC_WBM_R2_WBM2FW_RELEASE_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_WBM_R2_WBM2FW_RELEASE_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2FW_RELEASE_RING_HP__HEAD_PTR___S 0 +#define UMAC_WBM_R2_WBM2FW_RELEASE_RING_HP___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2FW_RELEASE_RING_HP___S 0 + +#define UMAC_WBM_R2_WBM2FW_RELEASE_RING_TP (0x00A370BC) +#define UMAC_WBM_R2_WBM2FW_RELEASE_RING_TP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_WBM2FW_RELEASE_RING_TP___POR 0x00000000 +#define UMAC_WBM_R2_WBM2FW_RELEASE_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_WBM_R2_WBM2FW_RELEASE_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2FW_RELEASE_RING_TP__TAIL_PTR___S 0 +#define UMAC_WBM_R2_WBM2FW_RELEASE_RING_TP___M 0x0000FFFF +#define UMAC_WBM_R2_WBM2FW_RELEASE_RING_TP___S 0 + +#define UMAC_WBM_R2_WBM2SW0_RELEASE_RING_HP (0x00A370C0) +#define UMAC_WBM_R2_WBM2SW0_RELEASE_RING_HP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_WBM2SW0_RELEASE_RING_HP___POR 0x00000000 +#define UMAC_WBM_R2_WBM2SW0_RELEASE_RING_HP__HEAD_PTR___POR 0x00000 +#define UMAC_WBM_R2_WBM2SW0_RELEASE_RING_HP__HEAD_PTR___M 0x000FFFFF +#define UMAC_WBM_R2_WBM2SW0_RELEASE_RING_HP__HEAD_PTR___S 0 +#define UMAC_WBM_R2_WBM2SW0_RELEASE_RING_HP___M 0x000FFFFF +#define UMAC_WBM_R2_WBM2SW0_RELEASE_RING_HP___S 0 + +#define UMAC_WBM_R2_WBM2SW0_RELEASE_RING_TP (0x00A370C4) +#define UMAC_WBM_R2_WBM2SW0_RELEASE_RING_TP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_WBM2SW0_RELEASE_RING_TP___POR 0x00000000 +#define UMAC_WBM_R2_WBM2SW0_RELEASE_RING_TP__TAIL_PTR___POR 0x00000 +#define UMAC_WBM_R2_WBM2SW0_RELEASE_RING_TP__TAIL_PTR___M 0x000FFFFF +#define UMAC_WBM_R2_WBM2SW0_RELEASE_RING_TP__TAIL_PTR___S 0 +#define UMAC_WBM_R2_WBM2SW0_RELEASE_RING_TP___M 0x000FFFFF +#define UMAC_WBM_R2_WBM2SW0_RELEASE_RING_TP___S 0 + +#define UMAC_WBM_R2_WBM2SW1_RELEASE_RING_HP (0x00A370C8) +#define UMAC_WBM_R2_WBM2SW1_RELEASE_RING_HP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_WBM2SW1_RELEASE_RING_HP___POR 0x00000000 +#define UMAC_WBM_R2_WBM2SW1_RELEASE_RING_HP__HEAD_PTR___POR 0x00000 +#define UMAC_WBM_R2_WBM2SW1_RELEASE_RING_HP__HEAD_PTR___M 0x000FFFFF +#define UMAC_WBM_R2_WBM2SW1_RELEASE_RING_HP__HEAD_PTR___S 0 +#define UMAC_WBM_R2_WBM2SW1_RELEASE_RING_HP___M 0x000FFFFF +#define UMAC_WBM_R2_WBM2SW1_RELEASE_RING_HP___S 0 + +#define UMAC_WBM_R2_WBM2SW1_RELEASE_RING_TP (0x00A370CC) +#define UMAC_WBM_R2_WBM2SW1_RELEASE_RING_TP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_WBM2SW1_RELEASE_RING_TP___POR 0x00000000 +#define UMAC_WBM_R2_WBM2SW1_RELEASE_RING_TP__TAIL_PTR___POR 0x00000 +#define UMAC_WBM_R2_WBM2SW1_RELEASE_RING_TP__TAIL_PTR___M 0x000FFFFF +#define UMAC_WBM_R2_WBM2SW1_RELEASE_RING_TP__TAIL_PTR___S 0 +#define UMAC_WBM_R2_WBM2SW1_RELEASE_RING_TP___M 0x000FFFFF +#define UMAC_WBM_R2_WBM2SW1_RELEASE_RING_TP___S 0 + +#define UMAC_WBM_R2_WBM2SW2_RELEASE_RING_HP (0x00A370D0) +#define UMAC_WBM_R2_WBM2SW2_RELEASE_RING_HP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_WBM2SW2_RELEASE_RING_HP___POR 0x00000000 +#define UMAC_WBM_R2_WBM2SW2_RELEASE_RING_HP__HEAD_PTR___POR 0x00000 +#define UMAC_WBM_R2_WBM2SW2_RELEASE_RING_HP__HEAD_PTR___M 0x000FFFFF +#define UMAC_WBM_R2_WBM2SW2_RELEASE_RING_HP__HEAD_PTR___S 0 +#define UMAC_WBM_R2_WBM2SW2_RELEASE_RING_HP___M 0x000FFFFF +#define UMAC_WBM_R2_WBM2SW2_RELEASE_RING_HP___S 0 + +#define UMAC_WBM_R2_WBM2SW2_RELEASE_RING_TP (0x00A370D4) +#define UMAC_WBM_R2_WBM2SW2_RELEASE_RING_TP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_WBM2SW2_RELEASE_RING_TP___POR 0x00000000 +#define UMAC_WBM_R2_WBM2SW2_RELEASE_RING_TP__TAIL_PTR___POR 0x00000 +#define UMAC_WBM_R2_WBM2SW2_RELEASE_RING_TP__TAIL_PTR___M 0x000FFFFF +#define UMAC_WBM_R2_WBM2SW2_RELEASE_RING_TP__TAIL_PTR___S 0 +#define UMAC_WBM_R2_WBM2SW2_RELEASE_RING_TP___M 0x000FFFFF +#define UMAC_WBM_R2_WBM2SW2_RELEASE_RING_TP___S 0 + +#define UMAC_WBM_R2_WBM2SW3_RELEASE_RING_HP (0x00A370D8) +#define UMAC_WBM_R2_WBM2SW3_RELEASE_RING_HP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_WBM2SW3_RELEASE_RING_HP___POR 0x00000000 +#define UMAC_WBM_R2_WBM2SW3_RELEASE_RING_HP__HEAD_PTR___POR 0x00000 +#define UMAC_WBM_R2_WBM2SW3_RELEASE_RING_HP__HEAD_PTR___M 0x000FFFFF +#define UMAC_WBM_R2_WBM2SW3_RELEASE_RING_HP__HEAD_PTR___S 0 +#define UMAC_WBM_R2_WBM2SW3_RELEASE_RING_HP___M 0x000FFFFF +#define UMAC_WBM_R2_WBM2SW3_RELEASE_RING_HP___S 0 + +#define UMAC_WBM_R2_WBM2SW3_RELEASE_RING_TP (0x00A370DC) +#define UMAC_WBM_R2_WBM2SW3_RELEASE_RING_TP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_WBM2SW3_RELEASE_RING_TP___POR 0x00000000 +#define UMAC_WBM_R2_WBM2SW3_RELEASE_RING_TP__TAIL_PTR___POR 0x00000 +#define UMAC_WBM_R2_WBM2SW3_RELEASE_RING_TP__TAIL_PTR___M 0x000FFFFF +#define UMAC_WBM_R2_WBM2SW3_RELEASE_RING_TP__TAIL_PTR___S 0 +#define UMAC_WBM_R2_WBM2SW3_RELEASE_RING_TP___M 0x000FFFFF +#define UMAC_WBM_R2_WBM2SW3_RELEASE_RING_TP___S 0 + +#define UMAC_WBM_R2_WBM2SW4_RELEASE_RING_HP (0x00A370E0) +#define UMAC_WBM_R2_WBM2SW4_RELEASE_RING_HP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_WBM2SW4_RELEASE_RING_HP___POR 0x00000000 +#define UMAC_WBM_R2_WBM2SW4_RELEASE_RING_HP__HEAD_PTR___POR 0x00000 +#define UMAC_WBM_R2_WBM2SW4_RELEASE_RING_HP__HEAD_PTR___M 0x000FFFFF +#define UMAC_WBM_R2_WBM2SW4_RELEASE_RING_HP__HEAD_PTR___S 0 +#define UMAC_WBM_R2_WBM2SW4_RELEASE_RING_HP___M 0x000FFFFF +#define UMAC_WBM_R2_WBM2SW4_RELEASE_RING_HP___S 0 + +#define UMAC_WBM_R2_WBM2SW4_RELEASE_RING_TP (0x00A370E4) +#define UMAC_WBM_R2_WBM2SW4_RELEASE_RING_TP___RWC QCSR_REG_RW +#define UMAC_WBM_R2_WBM2SW4_RELEASE_RING_TP___POR 0x00000000 +#define UMAC_WBM_R2_WBM2SW4_RELEASE_RING_TP__TAIL_PTR___POR 0x00000 +#define UMAC_WBM_R2_WBM2SW4_RELEASE_RING_TP__TAIL_PTR___M 0x000FFFFF +#define UMAC_WBM_R2_WBM2SW4_RELEASE_RING_TP__TAIL_PTR___S 0 +#define UMAC_WBM_R2_WBM2SW4_RELEASE_RING_TP___M 0x000FFFFF +#define UMAC_WBM_R2_WBM2SW4_RELEASE_RING_TP___S 0 + +#define UMAC_REO_R0_GENERAL_ENABLE (0x00A38000) +#define UMAC_REO_R0_GENERAL_ENABLE___RWC QCSR_REG_RW +#define UMAC_REO_R0_GENERAL_ENABLE___POR 0x03000150 +#define UMAC_REO_R0_GENERAL_ENABLE__SW2REO1_RING_ENABLE___POR 0x0 +#define UMAC_REO_R0_GENERAL_ENABLE__REO2SW6_RING_ENABLE___POR 0x0 +#define UMAC_REO_R0_GENERAL_ENABLE__REO2SW5_RING_ENABLE___POR 0x0 +#define UMAC_REO_R0_GENERAL_ENABLE__INVALIDATE_CACHE_FOR_ZERO_VLD___POR 0x0 +#define UMAC_REO_R0_GENERAL_ENABLE__STRUCT_SWAP_DELINK___POR 0x0 +#define UMAC_REO_R0_GENERAL_ENABLE__SOFT_REORDER_DEST_RING___POR 0x6 +#define UMAC_REO_R0_GENERAL_ENABLE__SW2REO_RING_ENABLE___POR 0x0 +#define UMAC_REO_R0_GENERAL_ENABLE__REO_CMD_RING_ENABLE___POR 0x0 +#define UMAC_REO_R0_GENERAL_ENABLE__REO_STATUS_RING_ENABLE___POR 0x0 +#define UMAC_REO_R0_GENERAL_ENABLE__REO_RELEASE_RING_ENABLE___POR 0x0 +#define UMAC_REO_R0_GENERAL_ENABLE__REO2TCL_RING_ENABLE___POR 0x0 +#define UMAC_REO_R0_GENERAL_ENABLE__REO2FW_RING_ENABLE___POR 0x0 +#define UMAC_REO_R0_GENERAL_ENABLE__REO2SW4_RING_ENABLE___POR 0x0 +#define UMAC_REO_R0_GENERAL_ENABLE__REO2SW3_RING_ENABLE___POR 0x0 +#define UMAC_REO_R0_GENERAL_ENABLE__REO2SW2_RING_ENABLE___POR 0x0 +#define UMAC_REO_R0_GENERAL_ENABLE__REO2SW1_RING_ENABLE___POR 0x0 +#define UMAC_REO_R0_GENERAL_ENABLE__WBM2REO_LINK_RING_ENABLE___POR 0x0 +#define UMAC_REO_R0_GENERAL_ENABLE__RXDMA2REO_RING_ENABLE___POR 0x0 +#define UMAC_REO_R0_GENERAL_ENABLE__GLOBAL_PN_CHK___POR 0x1 +#define UMAC_REO_R0_GENERAL_ENABLE__BAR_DEST_RING___POR 0x5 +#define UMAC_REO_R0_GENERAL_ENABLE__AGING_FLUSH_ENABLE___POR 0x0 +#define UMAC_REO_R0_GENERAL_ENABLE__AGING_LIST_ENABLE___POR 0x0 +#define UMAC_REO_R0_GENERAL_ENABLE__REO_HWREORDER_DISABLE___POR 0x0 +#define UMAC_REO_R0_GENERAL_ENABLE__REO_ENABLE___POR 0x0 +#define UMAC_REO_R0_GENERAL_ENABLE__SW2REO1_RING_ENABLE___M 0x80000000 +#define UMAC_REO_R0_GENERAL_ENABLE__SW2REO1_RING_ENABLE___S 31 +#define UMAC_REO_R0_GENERAL_ENABLE__REO2SW6_RING_ENABLE___M 0x40000000 +#define UMAC_REO_R0_GENERAL_ENABLE__REO2SW6_RING_ENABLE___S 30 +#define UMAC_REO_R0_GENERAL_ENABLE__REO2SW5_RING_ENABLE___M 0x20000000 +#define UMAC_REO_R0_GENERAL_ENABLE__REO2SW5_RING_ENABLE___S 29 +#define UMAC_REO_R0_GENERAL_ENABLE__INVALIDATE_CACHE_FOR_ZERO_VLD___M 0x10000000 +#define UMAC_REO_R0_GENERAL_ENABLE__INVALIDATE_CACHE_FOR_ZERO_VLD___S 28 +#define UMAC_REO_R0_GENERAL_ENABLE__STRUCT_SWAP_DELINK___M 0x08000000 +#define UMAC_REO_R0_GENERAL_ENABLE__STRUCT_SWAP_DELINK___S 27 +#define UMAC_REO_R0_GENERAL_ENABLE__SOFT_REORDER_DEST_RING___M 0x07800000 +#define UMAC_REO_R0_GENERAL_ENABLE__SOFT_REORDER_DEST_RING___S 23 +#define UMAC_REO_R0_GENERAL_ENABLE__SW2REO_RING_ENABLE___M 0x00400000 +#define UMAC_REO_R0_GENERAL_ENABLE__SW2REO_RING_ENABLE___S 22 +#define UMAC_REO_R0_GENERAL_ENABLE__REO_CMD_RING_ENABLE___M 0x00200000 +#define UMAC_REO_R0_GENERAL_ENABLE__REO_CMD_RING_ENABLE___S 21 +#define UMAC_REO_R0_GENERAL_ENABLE__REO_STATUS_RING_ENABLE___M 0x00100000 +#define UMAC_REO_R0_GENERAL_ENABLE__REO_STATUS_RING_ENABLE___S 20 +#define UMAC_REO_R0_GENERAL_ENABLE__REO_RELEASE_RING_ENABLE___M 0x00080000 +#define UMAC_REO_R0_GENERAL_ENABLE__REO_RELEASE_RING_ENABLE___S 19 +#define UMAC_REO_R0_GENERAL_ENABLE__REO2TCL_RING_ENABLE___M 0x00040000 +#define UMAC_REO_R0_GENERAL_ENABLE__REO2TCL_RING_ENABLE___S 18 +#define UMAC_REO_R0_GENERAL_ENABLE__REO2FW_RING_ENABLE___M 0x00020000 +#define UMAC_REO_R0_GENERAL_ENABLE__REO2FW_RING_ENABLE___S 17 +#define UMAC_REO_R0_GENERAL_ENABLE__REO2SW4_RING_ENABLE___M 0x00010000 +#define UMAC_REO_R0_GENERAL_ENABLE__REO2SW4_RING_ENABLE___S 16 +#define UMAC_REO_R0_GENERAL_ENABLE__REO2SW3_RING_ENABLE___M 0x00008000 +#define UMAC_REO_R0_GENERAL_ENABLE__REO2SW3_RING_ENABLE___S 15 +#define UMAC_REO_R0_GENERAL_ENABLE__REO2SW2_RING_ENABLE___M 0x00004000 +#define UMAC_REO_R0_GENERAL_ENABLE__REO2SW2_RING_ENABLE___S 14 +#define UMAC_REO_R0_GENERAL_ENABLE__REO2SW1_RING_ENABLE___M 0x00002000 +#define UMAC_REO_R0_GENERAL_ENABLE__REO2SW1_RING_ENABLE___S 13 +#define UMAC_REO_R0_GENERAL_ENABLE__WBM2REO_LINK_RING_ENABLE___M 0x00001000 +#define UMAC_REO_R0_GENERAL_ENABLE__WBM2REO_LINK_RING_ENABLE___S 12 +#define UMAC_REO_R0_GENERAL_ENABLE__RXDMA2REO_RING_ENABLE___M 0x00000E00 +#define UMAC_REO_R0_GENERAL_ENABLE__RXDMA2REO_RING_ENABLE___S 9 +#define UMAC_REO_R0_GENERAL_ENABLE__GLOBAL_PN_CHK___M 0x00000100 +#define UMAC_REO_R0_GENERAL_ENABLE__GLOBAL_PN_CHK___S 8 +#define UMAC_REO_R0_GENERAL_ENABLE__BAR_DEST_RING___M 0x000000F0 +#define UMAC_REO_R0_GENERAL_ENABLE__BAR_DEST_RING___S 4 +#define UMAC_REO_R0_GENERAL_ENABLE__AGING_FLUSH_ENABLE___M 0x00000008 +#define UMAC_REO_R0_GENERAL_ENABLE__AGING_FLUSH_ENABLE___S 3 +#define UMAC_REO_R0_GENERAL_ENABLE__AGING_LIST_ENABLE___M 0x00000004 +#define UMAC_REO_R0_GENERAL_ENABLE__AGING_LIST_ENABLE___S 2 +#define UMAC_REO_R0_GENERAL_ENABLE__REO_HWREORDER_DISABLE___M 0x00000002 +#define UMAC_REO_R0_GENERAL_ENABLE__REO_HWREORDER_DISABLE___S 1 +#define UMAC_REO_R0_GENERAL_ENABLE__REO_ENABLE___M 0x00000001 +#define UMAC_REO_R0_GENERAL_ENABLE__REO_ENABLE___S 0 +#define UMAC_REO_R0_GENERAL_ENABLE___M 0xFFFFFFFF +#define UMAC_REO_R0_GENERAL_ENABLE___S 0 + +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0 (0x00A38004) +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0___RWC QCSR_REG_RW +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0___POR 0x76543210 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_7___POR 0x7 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_6___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_5___POR 0x5 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_4___POR 0x4 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_3___POR 0x3 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_2___POR 0x2 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_1___POR 0x1 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_0___POR 0x0 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_7___M 0xF0000000 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_7___S 28 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_6___M 0x0F000000 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_6___S 24 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_5___M 0x00F00000 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_5___S 20 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_4___M 0x000F0000 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_4___S 16 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_3___M 0x0000F000 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_3___S 12 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_2___M 0x00000F00 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_2___S 8 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_1___M 0x000000F0 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_1___S 4 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_0___M 0x0000000F +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0__DEST_RING_MAPPING_0___S 0 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0___M 0xFFFFFFFF +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_0___S 0 + +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1 (0x00A38008) +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1___RWC QCSR_REG_RW +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1___POR 0x66666666 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_15___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_14___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_13___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_12___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_11___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_10___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_9___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_8___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_15___M 0xF0000000 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_15___S 28 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_14___M 0x0F000000 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_14___S 24 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_13___M 0x00F00000 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_13___S 20 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_12___M 0x000F0000 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_12___S 16 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_11___M 0x0000F000 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_11___S 12 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_10___M 0x00000F00 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_10___S 8 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_9___M 0x000000F0 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_9___S 4 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_8___M 0x0000000F +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1__DEST_RING_MAPPING_8___S 0 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1___M 0xFFFFFFFF +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_1___S 0 + +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2 (0x00A3800C) +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2___RWC QCSR_REG_RW +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2___POR 0x66666666 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_23___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_22___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_21___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_20___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_19___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_18___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_17___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_16___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_23___M 0xF0000000 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_23___S 28 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_22___M 0x0F000000 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_22___S 24 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_21___M 0x00F00000 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_21___S 20 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_20___M 0x000F0000 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_20___S 16 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_19___M 0x0000F000 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_19___S 12 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_18___M 0x00000F00 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_18___S 8 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_17___M 0x000000F0 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_17___S 4 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_16___M 0x0000000F +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2__DEST_RING_MAPPING_16___S 0 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2___M 0xFFFFFFFF +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_2___S 0 + +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3 (0x00A38010) +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3___RWC QCSR_REG_RW +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3___POR 0x66666666 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_31___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_30___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_29___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_28___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_27___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_26___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_25___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_24___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_31___M 0xF0000000 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_31___S 28 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_30___M 0x0F000000 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_30___S 24 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_29___M 0x00F00000 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_29___S 20 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_28___M 0x000F0000 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_28___S 16 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_27___M 0x0000F000 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_27___S 12 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_26___M 0x00000F00 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_26___S 8 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_25___M 0x000000F0 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_25___S 4 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_24___M 0x0000000F +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3__DEST_RING_MAPPING_24___S 0 +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3___M 0xFFFFFFFF +#define UMAC_REO_R0_DESTINATION_RING_CTRL_IX_3___S 0 + +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0 (0x00A38014) +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0___RWC QCSR_REG_RW +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0___POR 0x76543210 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_7___POR 0x7 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_6___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_5___POR 0x5 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_4___POR 0x4 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_3___POR 0x3 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_2___POR 0x2 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_1___POR 0x1 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_0___POR 0x0 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_7___M 0xF0000000 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_7___S 28 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_6___M 0x0F000000 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_6___S 24 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_5___M 0x00F00000 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_5___S 20 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_4___M 0x000F0000 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_4___S 16 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_3___M 0x0000F000 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_3___S 12 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_2___M 0x00000F00 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_2___S 8 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_1___M 0x000000F0 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_1___S 4 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_0___M 0x0000000F +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0__DEST_RING_ALT_MAPPING_0___S 0 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0___M 0xFFFFFFFF +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0___S 0 + +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1 (0x00A38018) +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1___RWC QCSR_REG_RW +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1___POR 0x66666666 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_15___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_14___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_13___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_12___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_11___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_10___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_9___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_8___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_15___M 0xF0000000 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_15___S 28 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_14___M 0x0F000000 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_14___S 24 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_13___M 0x00F00000 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_13___S 20 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_12___M 0x000F0000 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_12___S 16 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_11___M 0x0000F000 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_11___S 12 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_10___M 0x00000F00 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_10___S 8 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_9___M 0x000000F0 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_9___S 4 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_8___M 0x0000000F +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1__DEST_RING_ALT_MAPPING_8___S 0 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1___M 0xFFFFFFFF +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1___S 0 + +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2 (0x00A3801C) +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2___RWC QCSR_REG_RW +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2___POR 0x66666666 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_23___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_22___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_21___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_20___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_19___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_18___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_17___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_16___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_23___M 0xF0000000 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_23___S 28 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_22___M 0x0F000000 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_22___S 24 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_21___M 0x00F00000 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_21___S 20 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_20___M 0x000F0000 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_20___S 16 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_19___M 0x0000F000 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_19___S 12 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_18___M 0x00000F00 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_18___S 8 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_17___M 0x000000F0 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_17___S 4 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_16___M 0x0000000F +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2__DEST_RING_ALT_MAPPING_16___S 0 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2___M 0xFFFFFFFF +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2___S 0 + +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3 (0x00A38020) +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3___RWC QCSR_REG_RW +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3___POR 0x66666666 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_31___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_30___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_29___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_28___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_27___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_26___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_25___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_24___POR 0x6 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_31___M 0xF0000000 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_31___S 28 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_30___M 0x0F000000 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_30___S 24 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_29___M 0x00F00000 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_29___S 20 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_28___M 0x000F0000 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_28___S 16 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_27___M 0x0000F000 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_27___S 12 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_26___M 0x00000F00 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_26___S 8 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_25___M 0x000000F0 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_25___S 4 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_24___M 0x0000000F +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3__DEST_RING_ALT_MAPPING_24___S 0 +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3___M 0xFFFFFFFF +#define UMAC_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3___S 0 + +#define UMAC_REO_R0_TIMESTAMP (0x00A38024) +#define UMAC_REO_R0_TIMESTAMP___RWC QCSR_REG_RW +#define UMAC_REO_R0_TIMESTAMP___POR 0x00000000 +#define UMAC_REO_R0_TIMESTAMP__TIMESTAMP___POR 0x00000000 +#define UMAC_REO_R0_TIMESTAMP__TIMESTAMP___M 0xFFFFFFFF +#define UMAC_REO_R0_TIMESTAMP__TIMESTAMP___S 0 +#define UMAC_REO_R0_TIMESTAMP___M 0xFFFFFFFF +#define UMAC_REO_R0_TIMESTAMP___S 0 + +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0 (0x00A38028) +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0___RWC QCSR_REG_RW +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0___POR 0x55555555 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_7___POR 0x5 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_6___POR 0x5 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_5___POR 0x5 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_4___POR 0x5 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_3___POR 0x5 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_2___POR 0x5 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_1___POR 0x5 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_0___POR 0x5 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_7___M 0xF0000000 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_7___S 28 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_6___M 0x0F000000 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_6___S 24 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_5___M 0x00F00000 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_5___S 20 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_4___M 0x000F0000 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_4___S 16 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_3___M 0x0000F000 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_3___S 12 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_2___M 0x00000F00 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_2___S 8 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_1___M 0x000000F0 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_1___S 4 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_0___M 0x0000000F +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0__ERROR_DESTINATION_RING_0___S 0 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0___M 0xFFFFFFFF +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_0___S 0 + +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1 (0x00A3802C) +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1___RWC QCSR_REG_RW +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1___POR 0x55555555 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_OTHER___POR 0x5 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_14___POR 0x5 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_13___POR 0x5 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_12___POR 0x5 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_11___POR 0x5 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_10___POR 0x5 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_9___POR 0x5 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_8___POR 0x5 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_OTHER___M 0xF0000000 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_OTHER___S 28 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_14___M 0x0F000000 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_14___S 24 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_13___M 0x00F00000 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_13___S 20 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_12___M 0x000F0000 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_12___S 16 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_11___M 0x0000F000 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_11___S 12 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_10___M 0x00000F00 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_10___S 8 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_9___M 0x000000F0 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_9___S 4 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_8___M 0x0000000F +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1__ERROR_DESTINATION_RING_8___S 0 +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1___M 0xFFFFFFFF +#define UMAC_REO_R0_ERROR_DESTINATION_MAPPING_IX_1___S 0 + +#define UMAC_REO_R0_IDLE_REQ_CTRL (0x00A38030) +#define UMAC_REO_R0_IDLE_REQ_CTRL___RWC QCSR_REG_RW +#define UMAC_REO_R0_IDLE_REQ_CTRL___POR 0x00000003 +#define UMAC_REO_R0_IDLE_REQ_CTRL__IDLE_REQ_FLUSH_CACHE___POR 0x1 +#define UMAC_REO_R0_IDLE_REQ_CTRL__IDLE_REQ_FLUSH_AGE_LIST___POR 0x1 +#define UMAC_REO_R0_IDLE_REQ_CTRL__IDLE_REQ_FLUSH_CACHE___M 0x00000002 +#define UMAC_REO_R0_IDLE_REQ_CTRL__IDLE_REQ_FLUSH_CACHE___S 1 +#define UMAC_REO_R0_IDLE_REQ_CTRL__IDLE_REQ_FLUSH_AGE_LIST___M 0x00000001 +#define UMAC_REO_R0_IDLE_REQ_CTRL__IDLE_REQ_FLUSH_AGE_LIST___S 0 +#define UMAC_REO_R0_IDLE_REQ_CTRL___M 0x00000003 +#define UMAC_REO_R0_IDLE_REQ_CTRL___S 0 + +#define UMAC_REO_R0_RXDMA2REO0_RING_BASE_LSB (0x00A38034) +#define UMAC_REO_R0_RXDMA2REO0_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_RXDMA2REO0_RING_BASE_LSB___POR 0x00000000 +#define UMAC_REO_R0_RXDMA2REO0_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_RXDMA2REO0_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_RXDMA2REO0_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_REO_R0_RXDMA2REO0_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_RXDMA2REO0_RING_BASE_LSB___S 0 + +#define UMAC_REO_R0_RXDMA2REO0_RING_BASE_MSB (0x00A38038) +#define UMAC_REO_R0_RXDMA2REO0_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_RXDMA2REO0_RING_BASE_MSB___POR 0x00000000 +#define UMAC_REO_R0_RXDMA2REO0_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_REO_R0_RXDMA2REO0_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_REO_R0_RXDMA2REO0_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_REO_R0_RXDMA2REO0_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_REO_R0_RXDMA2REO0_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_RXDMA2REO0_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_REO_R0_RXDMA2REO0_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_REO_R0_RXDMA2REO0_RING_BASE_MSB___S 0 + +#define UMAC_REO_R0_RXDMA2REO0_RING_ID (0x00A3803C) +#define UMAC_REO_R0_RXDMA2REO0_RING_ID___RWC QCSR_REG_RW +#define UMAC_REO_R0_RXDMA2REO0_RING_ID___POR 0x00000000 +#define UMAC_REO_R0_RXDMA2REO0_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_REO_R0_RXDMA2REO0_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_REO_R0_RXDMA2REO0_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_REO_R0_RXDMA2REO0_RING_ID___M 0x000000FF +#define UMAC_REO_R0_RXDMA2REO0_RING_ID___S 0 + +#define UMAC_REO_R0_RXDMA2REO0_RING_STATUS (0x00A38040) +#define UMAC_REO_R0_RXDMA2REO0_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_RXDMA2REO0_RING_STATUS___POR 0x00000000 +#define UMAC_REO_R0_RXDMA2REO0_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_REO_R0_RXDMA2REO0_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_REO_R0_RXDMA2REO0_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_REO_R0_RXDMA2REO0_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_REO_R0_RXDMA2REO0_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_REO_R0_RXDMA2REO0_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_REO_R0_RXDMA2REO0_RING_STATUS___M 0xFFFFFFFF +#define UMAC_REO_R0_RXDMA2REO0_RING_STATUS___S 0 + +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC (0x00A38044) +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC___RWC QCSR_REG_RW +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC___POR 0x00000080 +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC___M 0x003FFFFF +#define UMAC_REO_R0_RXDMA2REO0_RING_MISC___S 0 + +#define UMAC_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB (0x00A38050) +#define UMAC_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S 0 +#define UMAC_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB___S 0 + +#define UMAC_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB (0x00A38054) +#define UMAC_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB___POR 0x00000000 +#define UMAC_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S 0 +#define UMAC_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB___S 0 + +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0 (0x00A38064) +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S 15 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0___S 0 + +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1 (0x00A38068) +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S 0 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1___S 0 + +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS (0x00A3806C) +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS___POR 0x00000000 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S 15 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS___S 0 + +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER (0x00A38070) +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S 0 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER___S 0 + +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER (0x00A38074) +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER__MODE___S 0 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER___S 0 + +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS (0x00A38078) +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S 16 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S 0 +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF +#define UMAC_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS___S 0 + +#define UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB (0x00A3807C) +#define UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB (0x00A38080) +#define UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_REO_R0_RXDMA2REO0_RING_MSI1_DATA (0x00A38084) +#define UMAC_REO_R0_RXDMA2REO0_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_REO_R0_RXDMA2REO0_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_REO_R0_RXDMA2REO0_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_REO_R0_RXDMA2REO0_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_REO_R0_RXDMA2REO0_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_REO_R0_RXDMA2REO0_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_REO_R0_RXDMA2REO0_RING_MSI1_DATA___S 0 + +#define UMAC_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET (0x00A38088) +#define UMAC_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_REO_R0_WBM2REO_LINK_RING_BASE_LSB (0x00A3808C) +#define UMAC_REO_R0_WBM2REO_LINK_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_WBM2REO_LINK_RING_BASE_LSB___POR 0x00000000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_WBM2REO_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_REO_R0_WBM2REO_LINK_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_WBM2REO_LINK_RING_BASE_LSB___S 0 + +#define UMAC_REO_R0_WBM2REO_LINK_RING_BASE_MSB (0x00A38090) +#define UMAC_REO_R0_WBM2REO_LINK_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_WBM2REO_LINK_RING_BASE_MSB___POR 0x00000000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_REO_R0_WBM2REO_LINK_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_REO_R0_WBM2REO_LINK_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_REO_R0_WBM2REO_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_WBM2REO_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_REO_R0_WBM2REO_LINK_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_REO_R0_WBM2REO_LINK_RING_BASE_MSB___S 0 + +#define UMAC_REO_R0_WBM2REO_LINK_RING_ID (0x00A38094) +#define UMAC_REO_R0_WBM2REO_LINK_RING_ID___RWC QCSR_REG_RW +#define UMAC_REO_R0_WBM2REO_LINK_RING_ID___POR 0x00000000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_REO_R0_WBM2REO_LINK_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_REO_R0_WBM2REO_LINK_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_REO_R0_WBM2REO_LINK_RING_ID___M 0x000000FF +#define UMAC_REO_R0_WBM2REO_LINK_RING_ID___S 0 + +#define UMAC_REO_R0_WBM2REO_LINK_RING_STATUS (0x00A38098) +#define UMAC_REO_R0_WBM2REO_LINK_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_WBM2REO_LINK_RING_STATUS___POR 0x00000000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_REO_R0_WBM2REO_LINK_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_REO_R0_WBM2REO_LINK_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_REO_R0_WBM2REO_LINK_RING_STATUS___M 0xFFFFFFFF +#define UMAC_REO_R0_WBM2REO_LINK_RING_STATUS___S 0 + +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC (0x00A3809C) +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC___RWC QCSR_REG_RW +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC___POR 0x00000080 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC___M 0x003FFFFF +#define UMAC_REO_R0_WBM2REO_LINK_RING_MISC___S 0 + +#define UMAC_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB (0x00A380A8) +#define UMAC_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S 0 +#define UMAC_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB___S 0 + +#define UMAC_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB (0x00A380AC) +#define UMAC_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB___POR 0x00000000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S 0 +#define UMAC_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB___S 0 + +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0 (0x00A380BC) +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S 15 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0___S 0 + +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1 (0x00A380C0) +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S 0 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1___S 0 + +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS (0x00A380C4) +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS___POR 0x00000000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S 15 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS___S 0 + +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER (0x00A380C8) +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S 0 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER___S 0 + +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER (0x00A380CC) +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER__MODE___S 0 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER___S 0 + +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS (0x00A380D0) +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S 16 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S 0 +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF +#define UMAC_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS___S 0 + +#define UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB (0x00A380D4) +#define UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB (0x00A380D8) +#define UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_DATA (0x00A380DC) +#define UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_REO_R0_WBM2REO_LINK_RING_MSI1_DATA___S 0 + +#define UMAC_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET (0x00A380E0) +#define UMAC_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_REO_R0_REO_CMD_RING_BASE_LSB (0x00A380E4) +#define UMAC_REO_R0_REO_CMD_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_CMD_RING_BASE_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO_CMD_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO_CMD_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO_CMD_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_REO_R0_REO_CMD_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO_CMD_RING_BASE_LSB___S 0 + +#define UMAC_REO_R0_REO_CMD_RING_BASE_MSB (0x00A380E8) +#define UMAC_REO_R0_REO_CMD_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_CMD_RING_BASE_MSB___POR 0x00000000 +#define UMAC_REO_R0_REO_CMD_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_REO_R0_REO_CMD_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_REO_R0_REO_CMD_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_REO_R0_REO_CMD_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_REO_R0_REO_CMD_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_REO_CMD_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_REO_R0_REO_CMD_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_REO_R0_REO_CMD_RING_BASE_MSB___S 0 + +#define UMAC_REO_R0_REO_CMD_RING_ID (0x00A380EC) +#define UMAC_REO_R0_REO_CMD_RING_ID___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_CMD_RING_ID___POR 0x00000000 +#define UMAC_REO_R0_REO_CMD_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_REO_R0_REO_CMD_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_REO_R0_REO_CMD_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_REO_R0_REO_CMD_RING_ID___M 0x000000FF +#define UMAC_REO_R0_REO_CMD_RING_ID___S 0 + +#define UMAC_REO_R0_REO_CMD_RING_STATUS (0x00A380F0) +#define UMAC_REO_R0_REO_CMD_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_REO_CMD_RING_STATUS___POR 0x00000000 +#define UMAC_REO_R0_REO_CMD_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_REO_R0_REO_CMD_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_REO_R0_REO_CMD_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_REO_R0_REO_CMD_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_REO_R0_REO_CMD_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_REO_R0_REO_CMD_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_REO_R0_REO_CMD_RING_STATUS___M 0xFFFFFFFF +#define UMAC_REO_R0_REO_CMD_RING_STATUS___S 0 + +#define UMAC_REO_R0_REO_CMD_RING_MISC (0x00A380F4) +#define UMAC_REO_R0_REO_CMD_RING_MISC___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_CMD_RING_MISC___POR 0x00000080 +#define UMAC_REO_R0_REO_CMD_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_REO_R0_REO_CMD_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_REO_R0_REO_CMD_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_REO_R0_REO_CMD_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_REO_R0_REO_CMD_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_REO_R0_REO_CMD_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_REO_CMD_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_REO_CMD_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_REO_CMD_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_REO_R0_REO_CMD_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_REO_R0_REO_CMD_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_REO_R0_REO_CMD_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_REO_R0_REO_CMD_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_REO_R0_REO_CMD_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_REO_R0_REO_CMD_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_REO_R0_REO_CMD_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_REO_R0_REO_CMD_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_REO_R0_REO_CMD_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_REO_R0_REO_CMD_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_REO_R0_REO_CMD_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_REO_R0_REO_CMD_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_REO_R0_REO_CMD_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_REO_R0_REO_CMD_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_REO_R0_REO_CMD_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_REO_R0_REO_CMD_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_REO_R0_REO_CMD_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_REO_R0_REO_CMD_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_REO_R0_REO_CMD_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_REO_R0_REO_CMD_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_REO_R0_REO_CMD_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_REO_R0_REO_CMD_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_REO_R0_REO_CMD_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_REO_R0_REO_CMD_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_REO_R0_REO_CMD_RING_MISC___M 0x003FFFFF +#define UMAC_REO_R0_REO_CMD_RING_MISC___S 0 + +#define UMAC_REO_R0_REO_CMD_RING_TP_ADDR_LSB (0x00A38100) +#define UMAC_REO_R0_REO_CMD_RING_TP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_CMD_RING_TP_ADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO_CMD_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO_CMD_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO_CMD_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S 0 +#define UMAC_REO_R0_REO_CMD_RING_TP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO_CMD_RING_TP_ADDR_LSB___S 0 + +#define UMAC_REO_R0_REO_CMD_RING_TP_ADDR_MSB (0x00A38104) +#define UMAC_REO_R0_REO_CMD_RING_TP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_CMD_RING_TP_ADDR_MSB___POR 0x00000000 +#define UMAC_REO_R0_REO_CMD_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_REO_R0_REO_CMD_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_REO_CMD_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S 0 +#define UMAC_REO_R0_REO_CMD_RING_TP_ADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_REO_CMD_RING_TP_ADDR_MSB___S 0 + +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0 (0x00A38114) +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S 15 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0___S 0 + +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1 (0x00A38118) +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S 0 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1___S 0 + +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS (0x00A3811C) +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS___POR 0x00000000 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S 15 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS___S 0 + +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER (0x00A38120) +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S 0 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER___S 0 + +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER (0x00A38124) +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER__MODE___S 0 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER___S 0 + +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS (0x00A38128) +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S 16 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S 0 +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF +#define UMAC_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS___S 0 + +#define UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_LSB (0x00A3812C) +#define UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_MSB (0x00A38130) +#define UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_REO_R0_REO_CMD_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_REO_R0_REO_CMD_RING_MSI1_DATA (0x00A38134) +#define UMAC_REO_R0_REO_CMD_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_CMD_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_REO_R0_REO_CMD_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_REO_R0_REO_CMD_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_REO_R0_REO_CMD_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_REO_R0_REO_CMD_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_REO_R0_REO_CMD_RING_MSI1_DATA___S 0 + +#define UMAC_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET (0x00A38138) +#define UMAC_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_REO_R0_SW2REO_RING_BASE_LSB (0x00A3813C) +#define UMAC_REO_R0_SW2REO_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_SW2REO_RING_BASE_LSB___POR 0x00000000 +#define UMAC_REO_R0_SW2REO_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_SW2REO_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_SW2REO_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_REO_R0_SW2REO_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_SW2REO_RING_BASE_LSB___S 0 + +#define UMAC_REO_R0_SW2REO_RING_BASE_MSB (0x00A38140) +#define UMAC_REO_R0_SW2REO_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_SW2REO_RING_BASE_MSB___POR 0x00000000 +#define UMAC_REO_R0_SW2REO_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_REO_R0_SW2REO_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_REO_R0_SW2REO_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_REO_R0_SW2REO_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_REO_R0_SW2REO_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_SW2REO_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_REO_R0_SW2REO_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_REO_R0_SW2REO_RING_BASE_MSB___S 0 + +#define UMAC_REO_R0_SW2REO_RING_ID (0x00A38144) +#define UMAC_REO_R0_SW2REO_RING_ID___RWC QCSR_REG_RW +#define UMAC_REO_R0_SW2REO_RING_ID___POR 0x00000000 +#define UMAC_REO_R0_SW2REO_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_REO_R0_SW2REO_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_REO_R0_SW2REO_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_REO_R0_SW2REO_RING_ID___M 0x000000FF +#define UMAC_REO_R0_SW2REO_RING_ID___S 0 + +#define UMAC_REO_R0_SW2REO_RING_STATUS (0x00A38148) +#define UMAC_REO_R0_SW2REO_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_SW2REO_RING_STATUS___POR 0x00000000 +#define UMAC_REO_R0_SW2REO_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_REO_R0_SW2REO_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_REO_R0_SW2REO_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_REO_R0_SW2REO_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_REO_R0_SW2REO_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_REO_R0_SW2REO_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_REO_R0_SW2REO_RING_STATUS___M 0xFFFFFFFF +#define UMAC_REO_R0_SW2REO_RING_STATUS___S 0 + +#define UMAC_REO_R0_SW2REO_RING_MISC (0x00A3814C) +#define UMAC_REO_R0_SW2REO_RING_MISC___RWC QCSR_REG_RW +#define UMAC_REO_R0_SW2REO_RING_MISC___POR 0x00000080 +#define UMAC_REO_R0_SW2REO_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_REO_R0_SW2REO_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_REO_R0_SW2REO_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_REO_R0_SW2REO_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_REO_R0_SW2REO_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_REO_R0_SW2REO_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_SW2REO_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_SW2REO_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_SW2REO_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_REO_R0_SW2REO_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_REO_R0_SW2REO_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_REO_R0_SW2REO_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_REO_R0_SW2REO_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_REO_R0_SW2REO_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_REO_R0_SW2REO_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_REO_R0_SW2REO_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_REO_R0_SW2REO_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_REO_R0_SW2REO_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_REO_R0_SW2REO_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_REO_R0_SW2REO_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_REO_R0_SW2REO_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_REO_R0_SW2REO_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_REO_R0_SW2REO_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_REO_R0_SW2REO_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_REO_R0_SW2REO_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_REO_R0_SW2REO_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_REO_R0_SW2REO_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_REO_R0_SW2REO_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_REO_R0_SW2REO_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_REO_R0_SW2REO_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_REO_R0_SW2REO_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_REO_R0_SW2REO_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_REO_R0_SW2REO_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_REO_R0_SW2REO_RING_MISC___M 0x003FFFFF +#define UMAC_REO_R0_SW2REO_RING_MISC___S 0 + +#define UMAC_REO_R0_SW2REO_RING_TP_ADDR_LSB (0x00A38158) +#define UMAC_REO_R0_SW2REO_RING_TP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_SW2REO_RING_TP_ADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_SW2REO_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_SW2REO_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_SW2REO_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S 0 +#define UMAC_REO_R0_SW2REO_RING_TP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_SW2REO_RING_TP_ADDR_LSB___S 0 + +#define UMAC_REO_R0_SW2REO_RING_TP_ADDR_MSB (0x00A3815C) +#define UMAC_REO_R0_SW2REO_RING_TP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_SW2REO_RING_TP_ADDR_MSB___POR 0x00000000 +#define UMAC_REO_R0_SW2REO_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_REO_R0_SW2REO_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_SW2REO_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S 0 +#define UMAC_REO_R0_SW2REO_RING_TP_ADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_SW2REO_RING_TP_ADDR_MSB___S 0 + +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0 (0x00A3816C) +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S 15 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0___S 0 + +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1 (0x00A38170) +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S 0 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1___S 0 + +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS (0x00A38174) +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS___POR 0x00000000 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S 15 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS___S 0 + +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER (0x00A38178) +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S 0 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER___S 0 + +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER (0x00A3817C) +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER__MODE___S 0 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER___S 0 + +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS (0x00A38180) +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S 16 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S 0 +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF +#define UMAC_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS___S 0 + +#define UMAC_REO_R0_SW2REO_RING_MSI1_BASE_LSB (0x00A38184) +#define UMAC_REO_R0_SW2REO_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_SW2REO_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_REO_R0_SW2REO_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_REO_R0_SW2REO_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_REO_R0_SW2REO_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_REO_R0_SW2REO_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_SW2REO_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_REO_R0_SW2REO_RING_MSI1_BASE_MSB (0x00A38188) +#define UMAC_REO_R0_SW2REO_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_SW2REO_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_REO_R0_SW2REO_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_REO_R0_SW2REO_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_REO_R0_SW2REO_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_REO_R0_SW2REO_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_REO_R0_SW2REO_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_REO_R0_SW2REO_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_REO_R0_SW2REO_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_REO_R0_SW2REO_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_REO_R0_SW2REO_RING_MSI1_DATA (0x00A3818C) +#define UMAC_REO_R0_SW2REO_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_REO_R0_SW2REO_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_REO_R0_SW2REO_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_REO_R0_SW2REO_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_REO_R0_SW2REO_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_REO_R0_SW2REO_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_REO_R0_SW2REO_RING_MSI1_DATA___S 0 + +#define UMAC_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET (0x00A38190) +#define UMAC_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_REO_R0_SW2REO1_RING_BASE_LSB (0x00A38194) +#define UMAC_REO_R0_SW2REO1_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_SW2REO1_RING_BASE_LSB___POR 0x00000000 +#define UMAC_REO_R0_SW2REO1_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_SW2REO1_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_SW2REO1_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_REO_R0_SW2REO1_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_SW2REO1_RING_BASE_LSB___S 0 + +#define UMAC_REO_R0_SW2REO1_RING_BASE_MSB (0x00A38198) +#define UMAC_REO_R0_SW2REO1_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_SW2REO1_RING_BASE_MSB___POR 0x00000000 +#define UMAC_REO_R0_SW2REO1_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_REO_R0_SW2REO1_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_REO_R0_SW2REO1_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_REO_R0_SW2REO1_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_REO_R0_SW2REO1_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_SW2REO1_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_REO_R0_SW2REO1_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_REO_R0_SW2REO1_RING_BASE_MSB___S 0 + +#define UMAC_REO_R0_SW2REO1_RING_ID (0x00A3819C) +#define UMAC_REO_R0_SW2REO1_RING_ID___RWC QCSR_REG_RW +#define UMAC_REO_R0_SW2REO1_RING_ID___POR 0x00000000 +#define UMAC_REO_R0_SW2REO1_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_REO_R0_SW2REO1_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_REO_R0_SW2REO1_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_REO_R0_SW2REO1_RING_ID___M 0x000000FF +#define UMAC_REO_R0_SW2REO1_RING_ID___S 0 + +#define UMAC_REO_R0_SW2REO1_RING_STATUS (0x00A381A0) +#define UMAC_REO_R0_SW2REO1_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_SW2REO1_RING_STATUS___POR 0x00000000 +#define UMAC_REO_R0_SW2REO1_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_REO_R0_SW2REO1_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_REO_R0_SW2REO1_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_REO_R0_SW2REO1_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_REO_R0_SW2REO1_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_REO_R0_SW2REO1_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_REO_R0_SW2REO1_RING_STATUS___M 0xFFFFFFFF +#define UMAC_REO_R0_SW2REO1_RING_STATUS___S 0 + +#define UMAC_REO_R0_SW2REO1_RING_MISC (0x00A381A4) +#define UMAC_REO_R0_SW2REO1_RING_MISC___RWC QCSR_REG_RW +#define UMAC_REO_R0_SW2REO1_RING_MISC___POR 0x00000080 +#define UMAC_REO_R0_SW2REO1_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_REO_R0_SW2REO1_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_REO_R0_SW2REO1_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_REO_R0_SW2REO1_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_REO_R0_SW2REO1_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_REO_R0_SW2REO1_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_SW2REO1_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_SW2REO1_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_SW2REO1_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_REO_R0_SW2REO1_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_REO_R0_SW2REO1_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_REO_R0_SW2REO1_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_REO_R0_SW2REO1_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_REO_R0_SW2REO1_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_REO_R0_SW2REO1_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_REO_R0_SW2REO1_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_REO_R0_SW2REO1_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_REO_R0_SW2REO1_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_REO_R0_SW2REO1_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_REO_R0_SW2REO1_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_REO_R0_SW2REO1_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_REO_R0_SW2REO1_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_REO_R0_SW2REO1_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_REO_R0_SW2REO1_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_REO_R0_SW2REO1_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_REO_R0_SW2REO1_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_REO_R0_SW2REO1_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_REO_R0_SW2REO1_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_REO_R0_SW2REO1_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_REO_R0_SW2REO1_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_REO_R0_SW2REO1_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_REO_R0_SW2REO1_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_REO_R0_SW2REO1_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_REO_R0_SW2REO1_RING_MISC___M 0x003FFFFF +#define UMAC_REO_R0_SW2REO1_RING_MISC___S 0 + +#define UMAC_REO_R0_SW2REO1_RING_TP_ADDR_LSB (0x00A381B0) +#define UMAC_REO_R0_SW2REO1_RING_TP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_SW2REO1_RING_TP_ADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_SW2REO1_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_SW2REO1_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_SW2REO1_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S 0 +#define UMAC_REO_R0_SW2REO1_RING_TP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_SW2REO1_RING_TP_ADDR_LSB___S 0 + +#define UMAC_REO_R0_SW2REO1_RING_TP_ADDR_MSB (0x00A381B4) +#define UMAC_REO_R0_SW2REO1_RING_TP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_SW2REO1_RING_TP_ADDR_MSB___POR 0x00000000 +#define UMAC_REO_R0_SW2REO1_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_REO_R0_SW2REO1_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_SW2REO1_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S 0 +#define UMAC_REO_R0_SW2REO1_RING_TP_ADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_SW2REO1_RING_TP_ADDR_MSB___S 0 + +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0 (0x00A381C4) +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S 15 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0___S 0 + +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1 (0x00A381C8) +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S 0 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1___S 0 + +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS (0x00A381CC) +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS___POR 0x00000000 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S 15 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS___S 0 + +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER (0x00A381D0) +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S 0 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER___S 0 + +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER (0x00A381D4) +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER__MODE___S 0 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER___S 0 + +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS (0x00A381D8) +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S 16 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S 0 +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF +#define UMAC_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS___S 0 + +#define UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_LSB (0x00A381DC) +#define UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_MSB (0x00A381E0) +#define UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_REO_R0_SW2REO1_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_REO_R0_SW2REO1_RING_MSI1_DATA (0x00A381E4) +#define UMAC_REO_R0_SW2REO1_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_REO_R0_SW2REO1_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_REO_R0_SW2REO1_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_REO_R0_SW2REO1_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_REO_R0_SW2REO1_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_REO_R0_SW2REO1_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_REO_R0_SW2REO1_RING_MSI1_DATA___S 0 + +#define UMAC_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET (0x00A381E8) +#define UMAC_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_REO_R0_REO2SW1_RING_BASE_LSB (0x00A381EC) +#define UMAC_REO_R0_REO2SW1_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW1_RING_BASE_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW1_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW1_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW1_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_REO_R0_REO2SW1_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW1_RING_BASE_LSB___S 0 + +#define UMAC_REO_R0_REO2SW1_RING_BASE_MSB (0x00A381F0) +#define UMAC_REO_R0_REO2SW1_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW1_RING_BASE_MSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW1_RING_BASE_MSB__RING_SIZE___POR 0x00000 +#define UMAC_REO_R0_REO2SW1_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_REO_R0_REO2SW1_RING_BASE_MSB__RING_SIZE___M 0x0FFFFF00 +#define UMAC_REO_R0_REO2SW1_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_REO_R0_REO2SW1_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_REO2SW1_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_REO_R0_REO2SW1_RING_BASE_MSB___M 0x0FFFFFFF +#define UMAC_REO_R0_REO2SW1_RING_BASE_MSB___S 0 + +#define UMAC_REO_R0_REO2SW1_RING_ID (0x00A381F4) +#define UMAC_REO_R0_REO2SW1_RING_ID___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW1_RING_ID___POR 0x00000000 +#define UMAC_REO_R0_REO2SW1_RING_ID__RING_ID___POR 0x00 +#define UMAC_REO_R0_REO2SW1_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_REO_R0_REO2SW1_RING_ID__RING_ID___M 0x0000FF00 +#define UMAC_REO_R0_REO2SW1_RING_ID__RING_ID___S 8 +#define UMAC_REO_R0_REO2SW1_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_REO_R0_REO2SW1_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_REO_R0_REO2SW1_RING_ID___M 0x0000FFFF +#define UMAC_REO_R0_REO2SW1_RING_ID___S 0 + +#define UMAC_REO_R0_REO2SW1_RING_STATUS (0x00A381F8) +#define UMAC_REO_R0_REO2SW1_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_REO2SW1_RING_STATUS___POR 0x00000000 +#define UMAC_REO_R0_REO2SW1_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_REO_R0_REO2SW1_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_REO_R0_REO2SW1_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_REO_R0_REO2SW1_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_REO_R0_REO2SW1_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_REO_R0_REO2SW1_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_REO_R0_REO2SW1_RING_STATUS___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW1_RING_STATUS___S 0 + +#define UMAC_REO_R0_REO2SW1_RING_MISC (0x00A381FC) +#define UMAC_REO_R0_REO2SW1_RING_MISC___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW1_RING_MISC___POR 0x00000080 +#define UMAC_REO_R0_REO2SW1_RING_MISC__LOOP_CNT___POR 0x0 +#define UMAC_REO_R0_REO2SW1_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_REO_R0_REO2SW1_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_REO_R0_REO2SW1_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_REO_R0_REO2SW1_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_REO_R0_REO2SW1_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_REO_R0_REO2SW1_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_REO2SW1_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_REO2SW1_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_REO2SW1_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_REO_R0_REO2SW1_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_REO_R0_REO2SW1_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_REO_R0_REO2SW1_RING_MISC__LOOP_CNT___M 0x03C00000 +#define UMAC_REO_R0_REO2SW1_RING_MISC__LOOP_CNT___S 22 +#define UMAC_REO_R0_REO2SW1_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_REO_R0_REO2SW1_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_REO_R0_REO2SW1_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_REO_R0_REO2SW1_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_REO_R0_REO2SW1_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_REO_R0_REO2SW1_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_REO_R0_REO2SW1_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_REO_R0_REO2SW1_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_REO_R0_REO2SW1_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_REO_R0_REO2SW1_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_REO_R0_REO2SW1_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_REO_R0_REO2SW1_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_REO_R0_REO2SW1_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_REO_R0_REO2SW1_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_REO_R0_REO2SW1_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_REO_R0_REO2SW1_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_REO_R0_REO2SW1_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_REO_R0_REO2SW1_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_REO_R0_REO2SW1_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_REO_R0_REO2SW1_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_REO_R0_REO2SW1_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_REO_R0_REO2SW1_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_REO_R0_REO2SW1_RING_MISC___M 0x03FFFFFF +#define UMAC_REO_R0_REO2SW1_RING_MISC___S 0 + +#define UMAC_REO_R0_REO2SW1_RING_HP_ADDR_LSB (0x00A38200) +#define UMAC_REO_R0_REO2SW1_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW1_RING_HP_ADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW1_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW1_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW1_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define UMAC_REO_R0_REO2SW1_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW1_RING_HP_ADDR_LSB___S 0 + +#define UMAC_REO_R0_REO2SW1_RING_HP_ADDR_MSB (0x00A38204) +#define UMAC_REO_R0_REO2SW1_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW1_RING_HP_ADDR_MSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW1_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_REO_R0_REO2SW1_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_REO2SW1_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define UMAC_REO_R0_REO2SW1_RING_HP_ADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_REO2SW1_RING_HP_ADDR_MSB___S 0 + +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP (0x00A38210) +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP___S 0 + +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS (0x00A38214) +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS___S 0 + +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER (0x00A38218) +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define UMAC_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER___S 0 + +#define UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_LSB (0x00A38234) +#define UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_MSB (0x00A38238) +#define UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_REO_R0_REO2SW1_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_REO_R0_REO2SW1_RING_MSI1_DATA (0x00A3823C) +#define UMAC_REO_R0_REO2SW1_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW1_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_REO_R0_REO2SW1_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_REO_R0_REO2SW1_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW1_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_REO_R0_REO2SW1_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW1_RING_MSI1_DATA___S 0 + +#define UMAC_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET (0x00A38240) +#define UMAC_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_REO_R0_REO2SW2_RING_BASE_LSB (0x00A38244) +#define UMAC_REO_R0_REO2SW2_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW2_RING_BASE_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW2_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW2_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW2_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_REO_R0_REO2SW2_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW2_RING_BASE_LSB___S 0 + +#define UMAC_REO_R0_REO2SW2_RING_BASE_MSB (0x00A38248) +#define UMAC_REO_R0_REO2SW2_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW2_RING_BASE_MSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW2_RING_BASE_MSB__RING_SIZE___POR 0x00000 +#define UMAC_REO_R0_REO2SW2_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_REO_R0_REO2SW2_RING_BASE_MSB__RING_SIZE___M 0x0FFFFF00 +#define UMAC_REO_R0_REO2SW2_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_REO_R0_REO2SW2_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_REO2SW2_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_REO_R0_REO2SW2_RING_BASE_MSB___M 0x0FFFFFFF +#define UMAC_REO_R0_REO2SW2_RING_BASE_MSB___S 0 + +#define UMAC_REO_R0_REO2SW2_RING_ID (0x00A3824C) +#define UMAC_REO_R0_REO2SW2_RING_ID___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW2_RING_ID___POR 0x00000000 +#define UMAC_REO_R0_REO2SW2_RING_ID__RING_ID___POR 0x00 +#define UMAC_REO_R0_REO2SW2_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_REO_R0_REO2SW2_RING_ID__RING_ID___M 0x0000FF00 +#define UMAC_REO_R0_REO2SW2_RING_ID__RING_ID___S 8 +#define UMAC_REO_R0_REO2SW2_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_REO_R0_REO2SW2_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_REO_R0_REO2SW2_RING_ID___M 0x0000FFFF +#define UMAC_REO_R0_REO2SW2_RING_ID___S 0 + +#define UMAC_REO_R0_REO2SW2_RING_STATUS (0x00A38250) +#define UMAC_REO_R0_REO2SW2_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_REO2SW2_RING_STATUS___POR 0x00000000 +#define UMAC_REO_R0_REO2SW2_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_REO_R0_REO2SW2_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_REO_R0_REO2SW2_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_REO_R0_REO2SW2_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_REO_R0_REO2SW2_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_REO_R0_REO2SW2_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_REO_R0_REO2SW2_RING_STATUS___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW2_RING_STATUS___S 0 + +#define UMAC_REO_R0_REO2SW2_RING_MISC (0x00A38254) +#define UMAC_REO_R0_REO2SW2_RING_MISC___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW2_RING_MISC___POR 0x00000080 +#define UMAC_REO_R0_REO2SW2_RING_MISC__LOOP_CNT___POR 0x0 +#define UMAC_REO_R0_REO2SW2_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_REO_R0_REO2SW2_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_REO_R0_REO2SW2_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_REO_R0_REO2SW2_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_REO_R0_REO2SW2_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_REO_R0_REO2SW2_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_REO2SW2_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_REO2SW2_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_REO2SW2_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_REO_R0_REO2SW2_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_REO_R0_REO2SW2_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_REO_R0_REO2SW2_RING_MISC__LOOP_CNT___M 0x03C00000 +#define UMAC_REO_R0_REO2SW2_RING_MISC__LOOP_CNT___S 22 +#define UMAC_REO_R0_REO2SW2_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_REO_R0_REO2SW2_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_REO_R0_REO2SW2_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_REO_R0_REO2SW2_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_REO_R0_REO2SW2_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_REO_R0_REO2SW2_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_REO_R0_REO2SW2_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_REO_R0_REO2SW2_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_REO_R0_REO2SW2_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_REO_R0_REO2SW2_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_REO_R0_REO2SW2_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_REO_R0_REO2SW2_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_REO_R0_REO2SW2_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_REO_R0_REO2SW2_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_REO_R0_REO2SW2_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_REO_R0_REO2SW2_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_REO_R0_REO2SW2_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_REO_R0_REO2SW2_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_REO_R0_REO2SW2_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_REO_R0_REO2SW2_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_REO_R0_REO2SW2_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_REO_R0_REO2SW2_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_REO_R0_REO2SW2_RING_MISC___M 0x03FFFFFF +#define UMAC_REO_R0_REO2SW2_RING_MISC___S 0 + +#define UMAC_REO_R0_REO2SW2_RING_HP_ADDR_LSB (0x00A38258) +#define UMAC_REO_R0_REO2SW2_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW2_RING_HP_ADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW2_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW2_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW2_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define UMAC_REO_R0_REO2SW2_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW2_RING_HP_ADDR_LSB___S 0 + +#define UMAC_REO_R0_REO2SW2_RING_HP_ADDR_MSB (0x00A3825C) +#define UMAC_REO_R0_REO2SW2_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW2_RING_HP_ADDR_MSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW2_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_REO_R0_REO2SW2_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_REO2SW2_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define UMAC_REO_R0_REO2SW2_RING_HP_ADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_REO2SW2_RING_HP_ADDR_MSB___S 0 + +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP (0x00A38268) +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP___S 0 + +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS (0x00A3826C) +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS___S 0 + +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER (0x00A38270) +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define UMAC_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER___S 0 + +#define UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_LSB (0x00A3828C) +#define UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_MSB (0x00A38290) +#define UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_REO_R0_REO2SW2_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_REO_R0_REO2SW2_RING_MSI1_DATA (0x00A38294) +#define UMAC_REO_R0_REO2SW2_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW2_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_REO_R0_REO2SW2_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_REO_R0_REO2SW2_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW2_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_REO_R0_REO2SW2_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW2_RING_MSI1_DATA___S 0 + +#define UMAC_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET (0x00A38298) +#define UMAC_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_REO_R0_REO2SW3_RING_BASE_LSB (0x00A3829C) +#define UMAC_REO_R0_REO2SW3_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW3_RING_BASE_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW3_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW3_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW3_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_REO_R0_REO2SW3_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW3_RING_BASE_LSB___S 0 + +#define UMAC_REO_R0_REO2SW3_RING_BASE_MSB (0x00A382A0) +#define UMAC_REO_R0_REO2SW3_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW3_RING_BASE_MSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW3_RING_BASE_MSB__RING_SIZE___POR 0x00000 +#define UMAC_REO_R0_REO2SW3_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_REO_R0_REO2SW3_RING_BASE_MSB__RING_SIZE___M 0x0FFFFF00 +#define UMAC_REO_R0_REO2SW3_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_REO_R0_REO2SW3_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_REO2SW3_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_REO_R0_REO2SW3_RING_BASE_MSB___M 0x0FFFFFFF +#define UMAC_REO_R0_REO2SW3_RING_BASE_MSB___S 0 + +#define UMAC_REO_R0_REO2SW3_RING_ID (0x00A382A4) +#define UMAC_REO_R0_REO2SW3_RING_ID___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW3_RING_ID___POR 0x00000000 +#define UMAC_REO_R0_REO2SW3_RING_ID__RING_ID___POR 0x00 +#define UMAC_REO_R0_REO2SW3_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_REO_R0_REO2SW3_RING_ID__RING_ID___M 0x0000FF00 +#define UMAC_REO_R0_REO2SW3_RING_ID__RING_ID___S 8 +#define UMAC_REO_R0_REO2SW3_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_REO_R0_REO2SW3_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_REO_R0_REO2SW3_RING_ID___M 0x0000FFFF +#define UMAC_REO_R0_REO2SW3_RING_ID___S 0 + +#define UMAC_REO_R0_REO2SW3_RING_STATUS (0x00A382A8) +#define UMAC_REO_R0_REO2SW3_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_REO2SW3_RING_STATUS___POR 0x00000000 +#define UMAC_REO_R0_REO2SW3_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_REO_R0_REO2SW3_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_REO_R0_REO2SW3_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_REO_R0_REO2SW3_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_REO_R0_REO2SW3_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_REO_R0_REO2SW3_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_REO_R0_REO2SW3_RING_STATUS___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW3_RING_STATUS___S 0 + +#define UMAC_REO_R0_REO2SW3_RING_MISC (0x00A382AC) +#define UMAC_REO_R0_REO2SW3_RING_MISC___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW3_RING_MISC___POR 0x00000080 +#define UMAC_REO_R0_REO2SW3_RING_MISC__LOOP_CNT___POR 0x0 +#define UMAC_REO_R0_REO2SW3_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_REO_R0_REO2SW3_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_REO_R0_REO2SW3_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_REO_R0_REO2SW3_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_REO_R0_REO2SW3_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_REO_R0_REO2SW3_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_REO2SW3_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_REO2SW3_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_REO2SW3_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_REO_R0_REO2SW3_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_REO_R0_REO2SW3_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_REO_R0_REO2SW3_RING_MISC__LOOP_CNT___M 0x03C00000 +#define UMAC_REO_R0_REO2SW3_RING_MISC__LOOP_CNT___S 22 +#define UMAC_REO_R0_REO2SW3_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_REO_R0_REO2SW3_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_REO_R0_REO2SW3_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_REO_R0_REO2SW3_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_REO_R0_REO2SW3_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_REO_R0_REO2SW3_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_REO_R0_REO2SW3_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_REO_R0_REO2SW3_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_REO_R0_REO2SW3_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_REO_R0_REO2SW3_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_REO_R0_REO2SW3_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_REO_R0_REO2SW3_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_REO_R0_REO2SW3_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_REO_R0_REO2SW3_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_REO_R0_REO2SW3_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_REO_R0_REO2SW3_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_REO_R0_REO2SW3_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_REO_R0_REO2SW3_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_REO_R0_REO2SW3_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_REO_R0_REO2SW3_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_REO_R0_REO2SW3_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_REO_R0_REO2SW3_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_REO_R0_REO2SW3_RING_MISC___M 0x03FFFFFF +#define UMAC_REO_R0_REO2SW3_RING_MISC___S 0 + +#define UMAC_REO_R0_REO2SW3_RING_HP_ADDR_LSB (0x00A382B0) +#define UMAC_REO_R0_REO2SW3_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW3_RING_HP_ADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW3_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW3_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW3_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define UMAC_REO_R0_REO2SW3_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW3_RING_HP_ADDR_LSB___S 0 + +#define UMAC_REO_R0_REO2SW3_RING_HP_ADDR_MSB (0x00A382B4) +#define UMAC_REO_R0_REO2SW3_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW3_RING_HP_ADDR_MSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW3_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_REO_R0_REO2SW3_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_REO2SW3_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define UMAC_REO_R0_REO2SW3_RING_HP_ADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_REO2SW3_RING_HP_ADDR_MSB___S 0 + +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP (0x00A382C0) +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP___S 0 + +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS (0x00A382C4) +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS___S 0 + +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER (0x00A382C8) +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define UMAC_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER___S 0 + +#define UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_LSB (0x00A382E4) +#define UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_MSB (0x00A382E8) +#define UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_REO_R0_REO2SW3_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_REO_R0_REO2SW3_RING_MSI1_DATA (0x00A382EC) +#define UMAC_REO_R0_REO2SW3_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW3_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_REO_R0_REO2SW3_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_REO_R0_REO2SW3_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW3_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_REO_R0_REO2SW3_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW3_RING_MSI1_DATA___S 0 + +#define UMAC_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET (0x00A382F0) +#define UMAC_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_REO_R0_REO2SW4_RING_BASE_LSB (0x00A382F4) +#define UMAC_REO_R0_REO2SW4_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW4_RING_BASE_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW4_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW4_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW4_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_REO_R0_REO2SW4_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW4_RING_BASE_LSB___S 0 + +#define UMAC_REO_R0_REO2SW4_RING_BASE_MSB (0x00A382F8) +#define UMAC_REO_R0_REO2SW4_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW4_RING_BASE_MSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW4_RING_BASE_MSB__RING_SIZE___POR 0x00000 +#define UMAC_REO_R0_REO2SW4_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_REO_R0_REO2SW4_RING_BASE_MSB__RING_SIZE___M 0x0FFFFF00 +#define UMAC_REO_R0_REO2SW4_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_REO_R0_REO2SW4_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_REO2SW4_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_REO_R0_REO2SW4_RING_BASE_MSB___M 0x0FFFFFFF +#define UMAC_REO_R0_REO2SW4_RING_BASE_MSB___S 0 + +#define UMAC_REO_R0_REO2SW4_RING_ID (0x00A382FC) +#define UMAC_REO_R0_REO2SW4_RING_ID___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW4_RING_ID___POR 0x00000000 +#define UMAC_REO_R0_REO2SW4_RING_ID__RING_ID___POR 0x00 +#define UMAC_REO_R0_REO2SW4_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_REO_R0_REO2SW4_RING_ID__RING_ID___M 0x0000FF00 +#define UMAC_REO_R0_REO2SW4_RING_ID__RING_ID___S 8 +#define UMAC_REO_R0_REO2SW4_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_REO_R0_REO2SW4_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_REO_R0_REO2SW4_RING_ID___M 0x0000FFFF +#define UMAC_REO_R0_REO2SW4_RING_ID___S 0 + +#define UMAC_REO_R0_REO2SW4_RING_STATUS (0x00A38300) +#define UMAC_REO_R0_REO2SW4_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_REO2SW4_RING_STATUS___POR 0x00000000 +#define UMAC_REO_R0_REO2SW4_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_REO_R0_REO2SW4_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_REO_R0_REO2SW4_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_REO_R0_REO2SW4_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_REO_R0_REO2SW4_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_REO_R0_REO2SW4_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_REO_R0_REO2SW4_RING_STATUS___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW4_RING_STATUS___S 0 + +#define UMAC_REO_R0_REO2SW4_RING_MISC (0x00A38304) +#define UMAC_REO_R0_REO2SW4_RING_MISC___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW4_RING_MISC___POR 0x00000080 +#define UMAC_REO_R0_REO2SW4_RING_MISC__LOOP_CNT___POR 0x0 +#define UMAC_REO_R0_REO2SW4_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_REO_R0_REO2SW4_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_REO_R0_REO2SW4_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_REO_R0_REO2SW4_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_REO_R0_REO2SW4_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_REO_R0_REO2SW4_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_REO2SW4_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_REO2SW4_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_REO2SW4_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_REO_R0_REO2SW4_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_REO_R0_REO2SW4_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_REO_R0_REO2SW4_RING_MISC__LOOP_CNT___M 0x03C00000 +#define UMAC_REO_R0_REO2SW4_RING_MISC__LOOP_CNT___S 22 +#define UMAC_REO_R0_REO2SW4_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_REO_R0_REO2SW4_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_REO_R0_REO2SW4_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_REO_R0_REO2SW4_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_REO_R0_REO2SW4_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_REO_R0_REO2SW4_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_REO_R0_REO2SW4_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_REO_R0_REO2SW4_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_REO_R0_REO2SW4_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_REO_R0_REO2SW4_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_REO_R0_REO2SW4_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_REO_R0_REO2SW4_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_REO_R0_REO2SW4_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_REO_R0_REO2SW4_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_REO_R0_REO2SW4_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_REO_R0_REO2SW4_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_REO_R0_REO2SW4_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_REO_R0_REO2SW4_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_REO_R0_REO2SW4_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_REO_R0_REO2SW4_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_REO_R0_REO2SW4_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_REO_R0_REO2SW4_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_REO_R0_REO2SW4_RING_MISC___M 0x03FFFFFF +#define UMAC_REO_R0_REO2SW4_RING_MISC___S 0 + +#define UMAC_REO_R0_REO2SW4_RING_HP_ADDR_LSB (0x00A38308) +#define UMAC_REO_R0_REO2SW4_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW4_RING_HP_ADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW4_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW4_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW4_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define UMAC_REO_R0_REO2SW4_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW4_RING_HP_ADDR_LSB___S 0 + +#define UMAC_REO_R0_REO2SW4_RING_HP_ADDR_MSB (0x00A3830C) +#define UMAC_REO_R0_REO2SW4_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW4_RING_HP_ADDR_MSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW4_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_REO_R0_REO2SW4_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_REO2SW4_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define UMAC_REO_R0_REO2SW4_RING_HP_ADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_REO2SW4_RING_HP_ADDR_MSB___S 0 + +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP (0x00A38318) +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP___S 0 + +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS (0x00A3831C) +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS___S 0 + +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER (0x00A38320) +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define UMAC_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER___S 0 + +#define UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_LSB (0x00A3833C) +#define UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_MSB (0x00A38340) +#define UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_REO_R0_REO2SW4_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_REO_R0_REO2SW4_RING_MSI1_DATA (0x00A38344) +#define UMAC_REO_R0_REO2SW4_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW4_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_REO_R0_REO2SW4_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_REO_R0_REO2SW4_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW4_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_REO_R0_REO2SW4_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW4_RING_MSI1_DATA___S 0 + +#define UMAC_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET (0x00A38348) +#define UMAC_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_REO_R0_REO2SW5_RING_BASE_LSB (0x00A3834C) +#define UMAC_REO_R0_REO2SW5_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW5_RING_BASE_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW5_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW5_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW5_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_REO_R0_REO2SW5_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW5_RING_BASE_LSB___S 0 + +#define UMAC_REO_R0_REO2SW5_RING_BASE_MSB (0x00A38350) +#define UMAC_REO_R0_REO2SW5_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW5_RING_BASE_MSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW5_RING_BASE_MSB__RING_SIZE___POR 0x00000 +#define UMAC_REO_R0_REO2SW5_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_REO_R0_REO2SW5_RING_BASE_MSB__RING_SIZE___M 0x0FFFFF00 +#define UMAC_REO_R0_REO2SW5_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_REO_R0_REO2SW5_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_REO2SW5_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_REO_R0_REO2SW5_RING_BASE_MSB___M 0x0FFFFFFF +#define UMAC_REO_R0_REO2SW5_RING_BASE_MSB___S 0 + +#define UMAC_REO_R0_REO2SW5_RING_ID (0x00A38354) +#define UMAC_REO_R0_REO2SW5_RING_ID___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW5_RING_ID___POR 0x00000000 +#define UMAC_REO_R0_REO2SW5_RING_ID__RING_ID___POR 0x00 +#define UMAC_REO_R0_REO2SW5_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_REO_R0_REO2SW5_RING_ID__RING_ID___M 0x0000FF00 +#define UMAC_REO_R0_REO2SW5_RING_ID__RING_ID___S 8 +#define UMAC_REO_R0_REO2SW5_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_REO_R0_REO2SW5_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_REO_R0_REO2SW5_RING_ID___M 0x0000FFFF +#define UMAC_REO_R0_REO2SW5_RING_ID___S 0 + +#define UMAC_REO_R0_REO2SW5_RING_STATUS (0x00A38358) +#define UMAC_REO_R0_REO2SW5_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_REO2SW5_RING_STATUS___POR 0x00000000 +#define UMAC_REO_R0_REO2SW5_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_REO_R0_REO2SW5_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_REO_R0_REO2SW5_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_REO_R0_REO2SW5_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_REO_R0_REO2SW5_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_REO_R0_REO2SW5_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_REO_R0_REO2SW5_RING_STATUS___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW5_RING_STATUS___S 0 + +#define UMAC_REO_R0_REO2SW5_RING_MISC (0x00A3835C) +#define UMAC_REO_R0_REO2SW5_RING_MISC___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW5_RING_MISC___POR 0x00000080 +#define UMAC_REO_R0_REO2SW5_RING_MISC__LOOP_CNT___POR 0x0 +#define UMAC_REO_R0_REO2SW5_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_REO_R0_REO2SW5_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_REO_R0_REO2SW5_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_REO_R0_REO2SW5_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_REO_R0_REO2SW5_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_REO_R0_REO2SW5_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_REO2SW5_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_REO2SW5_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_REO2SW5_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_REO_R0_REO2SW5_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_REO_R0_REO2SW5_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_REO_R0_REO2SW5_RING_MISC__LOOP_CNT___M 0x03C00000 +#define UMAC_REO_R0_REO2SW5_RING_MISC__LOOP_CNT___S 22 +#define UMAC_REO_R0_REO2SW5_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_REO_R0_REO2SW5_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_REO_R0_REO2SW5_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_REO_R0_REO2SW5_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_REO_R0_REO2SW5_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_REO_R0_REO2SW5_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_REO_R0_REO2SW5_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_REO_R0_REO2SW5_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_REO_R0_REO2SW5_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_REO_R0_REO2SW5_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_REO_R0_REO2SW5_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_REO_R0_REO2SW5_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_REO_R0_REO2SW5_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_REO_R0_REO2SW5_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_REO_R0_REO2SW5_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_REO_R0_REO2SW5_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_REO_R0_REO2SW5_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_REO_R0_REO2SW5_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_REO_R0_REO2SW5_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_REO_R0_REO2SW5_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_REO_R0_REO2SW5_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_REO_R0_REO2SW5_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_REO_R0_REO2SW5_RING_MISC___M 0x03FFFFFF +#define UMAC_REO_R0_REO2SW5_RING_MISC___S 0 + +#define UMAC_REO_R0_REO2SW5_RING_HP_ADDR_LSB (0x00A38360) +#define UMAC_REO_R0_REO2SW5_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW5_RING_HP_ADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW5_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW5_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW5_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define UMAC_REO_R0_REO2SW5_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW5_RING_HP_ADDR_LSB___S 0 + +#define UMAC_REO_R0_REO2SW5_RING_HP_ADDR_MSB (0x00A38364) +#define UMAC_REO_R0_REO2SW5_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW5_RING_HP_ADDR_MSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW5_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_REO_R0_REO2SW5_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_REO2SW5_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define UMAC_REO_R0_REO2SW5_RING_HP_ADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_REO2SW5_RING_HP_ADDR_MSB___S 0 + +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP (0x00A38370) +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP___S 0 + +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS (0x00A38374) +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS___S 0 + +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER (0x00A38378) +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define UMAC_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER___S 0 + +#define UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_LSB (0x00A38394) +#define UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_MSB (0x00A38398) +#define UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_REO_R0_REO2SW5_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_REO_R0_REO2SW5_RING_MSI1_DATA (0x00A3839C) +#define UMAC_REO_R0_REO2SW5_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW5_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_REO_R0_REO2SW5_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_REO_R0_REO2SW5_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW5_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_REO_R0_REO2SW5_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW5_RING_MSI1_DATA___S 0 + +#define UMAC_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET (0x00A383A0) +#define UMAC_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_REO_R0_REO2SW6_RING_BASE_LSB (0x00A383A4) +#define UMAC_REO_R0_REO2SW6_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW6_RING_BASE_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW6_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW6_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW6_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_REO_R0_REO2SW6_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW6_RING_BASE_LSB___S 0 + +#define UMAC_REO_R0_REO2SW6_RING_BASE_MSB (0x00A383A8) +#define UMAC_REO_R0_REO2SW6_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW6_RING_BASE_MSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW6_RING_BASE_MSB__RING_SIZE___POR 0x00000 +#define UMAC_REO_R0_REO2SW6_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_REO_R0_REO2SW6_RING_BASE_MSB__RING_SIZE___M 0x0FFFFF00 +#define UMAC_REO_R0_REO2SW6_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_REO_R0_REO2SW6_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_REO2SW6_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_REO_R0_REO2SW6_RING_BASE_MSB___M 0x0FFFFFFF +#define UMAC_REO_R0_REO2SW6_RING_BASE_MSB___S 0 + +#define UMAC_REO_R0_REO2SW6_RING_ID (0x00A383AC) +#define UMAC_REO_R0_REO2SW6_RING_ID___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW6_RING_ID___POR 0x00000000 +#define UMAC_REO_R0_REO2SW6_RING_ID__RING_ID___POR 0x00 +#define UMAC_REO_R0_REO2SW6_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_REO_R0_REO2SW6_RING_ID__RING_ID___M 0x0000FF00 +#define UMAC_REO_R0_REO2SW6_RING_ID__RING_ID___S 8 +#define UMAC_REO_R0_REO2SW6_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_REO_R0_REO2SW6_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_REO_R0_REO2SW6_RING_ID___M 0x0000FFFF +#define UMAC_REO_R0_REO2SW6_RING_ID___S 0 + +#define UMAC_REO_R0_REO2SW6_RING_STATUS (0x00A383B0) +#define UMAC_REO_R0_REO2SW6_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_REO2SW6_RING_STATUS___POR 0x00000000 +#define UMAC_REO_R0_REO2SW6_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_REO_R0_REO2SW6_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_REO_R0_REO2SW6_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_REO_R0_REO2SW6_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_REO_R0_REO2SW6_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_REO_R0_REO2SW6_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_REO_R0_REO2SW6_RING_STATUS___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW6_RING_STATUS___S 0 + +#define UMAC_REO_R0_REO2SW6_RING_MISC (0x00A383B4) +#define UMAC_REO_R0_REO2SW6_RING_MISC___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW6_RING_MISC___POR 0x00000080 +#define UMAC_REO_R0_REO2SW6_RING_MISC__LOOP_CNT___POR 0x0 +#define UMAC_REO_R0_REO2SW6_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_REO_R0_REO2SW6_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_REO_R0_REO2SW6_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_REO_R0_REO2SW6_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_REO_R0_REO2SW6_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_REO_R0_REO2SW6_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_REO2SW6_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_REO2SW6_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_REO2SW6_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_REO_R0_REO2SW6_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_REO_R0_REO2SW6_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_REO_R0_REO2SW6_RING_MISC__LOOP_CNT___M 0x03C00000 +#define UMAC_REO_R0_REO2SW6_RING_MISC__LOOP_CNT___S 22 +#define UMAC_REO_R0_REO2SW6_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_REO_R0_REO2SW6_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_REO_R0_REO2SW6_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_REO_R0_REO2SW6_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_REO_R0_REO2SW6_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_REO_R0_REO2SW6_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_REO_R0_REO2SW6_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_REO_R0_REO2SW6_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_REO_R0_REO2SW6_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_REO_R0_REO2SW6_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_REO_R0_REO2SW6_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_REO_R0_REO2SW6_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_REO_R0_REO2SW6_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_REO_R0_REO2SW6_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_REO_R0_REO2SW6_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_REO_R0_REO2SW6_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_REO_R0_REO2SW6_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_REO_R0_REO2SW6_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_REO_R0_REO2SW6_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_REO_R0_REO2SW6_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_REO_R0_REO2SW6_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_REO_R0_REO2SW6_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_REO_R0_REO2SW6_RING_MISC___M 0x03FFFFFF +#define UMAC_REO_R0_REO2SW6_RING_MISC___S 0 + +#define UMAC_REO_R0_REO2SW6_RING_HP_ADDR_LSB (0x00A383B8) +#define UMAC_REO_R0_REO2SW6_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW6_RING_HP_ADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW6_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW6_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW6_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define UMAC_REO_R0_REO2SW6_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW6_RING_HP_ADDR_LSB___S 0 + +#define UMAC_REO_R0_REO2SW6_RING_HP_ADDR_MSB (0x00A383BC) +#define UMAC_REO_R0_REO2SW6_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW6_RING_HP_ADDR_MSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW6_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_REO_R0_REO2SW6_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_REO2SW6_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define UMAC_REO_R0_REO2SW6_RING_HP_ADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_REO2SW6_RING_HP_ADDR_MSB___S 0 + +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP (0x00A383C8) +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP___S 0 + +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS (0x00A383CC) +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS___S 0 + +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER (0x00A383D0) +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define UMAC_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER___S 0 + +#define UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_LSB (0x00A383EC) +#define UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_MSB (0x00A383F0) +#define UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_REO_R0_REO2SW6_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_REO_R0_REO2SW6_RING_MSI1_DATA (0x00A383F4) +#define UMAC_REO_R0_REO2SW6_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW6_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_REO_R0_REO2SW6_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_REO_R0_REO2SW6_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW6_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_REO_R0_REO2SW6_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2SW6_RING_MSI1_DATA___S 0 + +#define UMAC_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET (0x00A383F8) +#define UMAC_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_REO_R0_REO2TCL_RING_BASE_LSB (0x00A383FC) +#define UMAC_REO_R0_REO2TCL_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2TCL_RING_BASE_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2TCL_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2TCL_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2TCL_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_REO_R0_REO2TCL_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2TCL_RING_BASE_LSB___S 0 + +#define UMAC_REO_R0_REO2TCL_RING_BASE_MSB (0x00A38400) +#define UMAC_REO_R0_REO2TCL_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2TCL_RING_BASE_MSB___POR 0x00000000 +#define UMAC_REO_R0_REO2TCL_RING_BASE_MSB__RING_SIZE___POR 0x00000 +#define UMAC_REO_R0_REO2TCL_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_REO_R0_REO2TCL_RING_BASE_MSB__RING_SIZE___M 0x0FFFFF00 +#define UMAC_REO_R0_REO2TCL_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_REO_R0_REO2TCL_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_REO2TCL_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_REO_R0_REO2TCL_RING_BASE_MSB___M 0x0FFFFFFF +#define UMAC_REO_R0_REO2TCL_RING_BASE_MSB___S 0 + +#define UMAC_REO_R0_REO2TCL_RING_ID (0x00A38404) +#define UMAC_REO_R0_REO2TCL_RING_ID___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2TCL_RING_ID___POR 0x00000000 +#define UMAC_REO_R0_REO2TCL_RING_ID__RING_ID___POR 0x00 +#define UMAC_REO_R0_REO2TCL_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_REO_R0_REO2TCL_RING_ID__RING_ID___M 0x0000FF00 +#define UMAC_REO_R0_REO2TCL_RING_ID__RING_ID___S 8 +#define UMAC_REO_R0_REO2TCL_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_REO_R0_REO2TCL_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_REO_R0_REO2TCL_RING_ID___M 0x0000FFFF +#define UMAC_REO_R0_REO2TCL_RING_ID___S 0 + +#define UMAC_REO_R0_REO2TCL_RING_STATUS (0x00A38408) +#define UMAC_REO_R0_REO2TCL_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_REO2TCL_RING_STATUS___POR 0x00000000 +#define UMAC_REO_R0_REO2TCL_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_REO_R0_REO2TCL_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_REO_R0_REO2TCL_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_REO_R0_REO2TCL_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_REO_R0_REO2TCL_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_REO_R0_REO2TCL_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_REO_R0_REO2TCL_RING_STATUS___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2TCL_RING_STATUS___S 0 + +#define UMAC_REO_R0_REO2TCL_RING_MISC (0x00A3840C) +#define UMAC_REO_R0_REO2TCL_RING_MISC___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2TCL_RING_MISC___POR 0x00000080 +#define UMAC_REO_R0_REO2TCL_RING_MISC__LOOP_CNT___POR 0x0 +#define UMAC_REO_R0_REO2TCL_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_REO_R0_REO2TCL_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_REO_R0_REO2TCL_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_REO_R0_REO2TCL_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_REO_R0_REO2TCL_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_REO_R0_REO2TCL_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_REO2TCL_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_REO2TCL_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_REO2TCL_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_REO_R0_REO2TCL_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_REO_R0_REO2TCL_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_REO_R0_REO2TCL_RING_MISC__LOOP_CNT___M 0x03C00000 +#define UMAC_REO_R0_REO2TCL_RING_MISC__LOOP_CNT___S 22 +#define UMAC_REO_R0_REO2TCL_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_REO_R0_REO2TCL_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_REO_R0_REO2TCL_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_REO_R0_REO2TCL_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_REO_R0_REO2TCL_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_REO_R0_REO2TCL_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_REO_R0_REO2TCL_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_REO_R0_REO2TCL_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_REO_R0_REO2TCL_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_REO_R0_REO2TCL_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_REO_R0_REO2TCL_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_REO_R0_REO2TCL_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_REO_R0_REO2TCL_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_REO_R0_REO2TCL_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_REO_R0_REO2TCL_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_REO_R0_REO2TCL_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_REO_R0_REO2TCL_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_REO_R0_REO2TCL_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_REO_R0_REO2TCL_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_REO_R0_REO2TCL_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_REO_R0_REO2TCL_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_REO_R0_REO2TCL_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_REO_R0_REO2TCL_RING_MISC___M 0x03FFFFFF +#define UMAC_REO_R0_REO2TCL_RING_MISC___S 0 + +#define UMAC_REO_R0_REO2TCL_RING_HP_ADDR_LSB (0x00A38410) +#define UMAC_REO_R0_REO2TCL_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2TCL_RING_HP_ADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2TCL_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2TCL_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2TCL_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define UMAC_REO_R0_REO2TCL_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2TCL_RING_HP_ADDR_LSB___S 0 + +#define UMAC_REO_R0_REO2TCL_RING_HP_ADDR_MSB (0x00A38414) +#define UMAC_REO_R0_REO2TCL_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2TCL_RING_HP_ADDR_MSB___POR 0x00000000 +#define UMAC_REO_R0_REO2TCL_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_REO_R0_REO2TCL_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_REO2TCL_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define UMAC_REO_R0_REO2TCL_RING_HP_ADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_REO2TCL_RING_HP_ADDR_MSB___S 0 + +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP (0x00A38420) +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP___S 0 + +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS (0x00A38424) +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS___S 0 + +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER (0x00A38428) +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define UMAC_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER___S 0 + +#define UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_LSB (0x00A38444) +#define UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_MSB (0x00A38448) +#define UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_REO_R0_REO2TCL_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_REO_R0_REO2TCL_RING_MSI1_DATA (0x00A3844C) +#define UMAC_REO_R0_REO2TCL_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2TCL_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_REO_R0_REO2TCL_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_REO_R0_REO2TCL_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2TCL_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_REO_R0_REO2TCL_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2TCL_RING_MSI1_DATA___S 0 + +#define UMAC_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET (0x00A38450) +#define UMAC_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_REO_R0_REO2FW_RING_BASE_LSB (0x00A38454) +#define UMAC_REO_R0_REO2FW_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2FW_RING_BASE_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2FW_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2FW_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2FW_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_REO_R0_REO2FW_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2FW_RING_BASE_LSB___S 0 + +#define UMAC_REO_R0_REO2FW_RING_BASE_MSB (0x00A38458) +#define UMAC_REO_R0_REO2FW_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2FW_RING_BASE_MSB___POR 0x00000000 +#define UMAC_REO_R0_REO2FW_RING_BASE_MSB__RING_SIZE___POR 0x00000 +#define UMAC_REO_R0_REO2FW_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_REO_R0_REO2FW_RING_BASE_MSB__RING_SIZE___M 0x0FFFFF00 +#define UMAC_REO_R0_REO2FW_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_REO_R0_REO2FW_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_REO2FW_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_REO_R0_REO2FW_RING_BASE_MSB___M 0x0FFFFFFF +#define UMAC_REO_R0_REO2FW_RING_BASE_MSB___S 0 + +#define UMAC_REO_R0_REO2FW_RING_ID (0x00A3845C) +#define UMAC_REO_R0_REO2FW_RING_ID___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2FW_RING_ID___POR 0x00000000 +#define UMAC_REO_R0_REO2FW_RING_ID__RING_ID___POR 0x00 +#define UMAC_REO_R0_REO2FW_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_REO_R0_REO2FW_RING_ID__RING_ID___M 0x0000FF00 +#define UMAC_REO_R0_REO2FW_RING_ID__RING_ID___S 8 +#define UMAC_REO_R0_REO2FW_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_REO_R0_REO2FW_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_REO_R0_REO2FW_RING_ID___M 0x0000FFFF +#define UMAC_REO_R0_REO2FW_RING_ID___S 0 + +#define UMAC_REO_R0_REO2FW_RING_STATUS (0x00A38460) +#define UMAC_REO_R0_REO2FW_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_REO2FW_RING_STATUS___POR 0x00000000 +#define UMAC_REO_R0_REO2FW_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_REO_R0_REO2FW_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_REO_R0_REO2FW_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_REO_R0_REO2FW_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_REO_R0_REO2FW_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_REO_R0_REO2FW_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_REO_R0_REO2FW_RING_STATUS___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2FW_RING_STATUS___S 0 + +#define UMAC_REO_R0_REO2FW_RING_MISC (0x00A38464) +#define UMAC_REO_R0_REO2FW_RING_MISC___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2FW_RING_MISC___POR 0x00000080 +#define UMAC_REO_R0_REO2FW_RING_MISC__LOOP_CNT___POR 0x0 +#define UMAC_REO_R0_REO2FW_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_REO_R0_REO2FW_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_REO_R0_REO2FW_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_REO_R0_REO2FW_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_REO_R0_REO2FW_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_REO_R0_REO2FW_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_REO2FW_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_REO2FW_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_REO2FW_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_REO_R0_REO2FW_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_REO_R0_REO2FW_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_REO_R0_REO2FW_RING_MISC__LOOP_CNT___M 0x03C00000 +#define UMAC_REO_R0_REO2FW_RING_MISC__LOOP_CNT___S 22 +#define UMAC_REO_R0_REO2FW_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_REO_R0_REO2FW_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_REO_R0_REO2FW_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_REO_R0_REO2FW_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_REO_R0_REO2FW_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_REO_R0_REO2FW_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_REO_R0_REO2FW_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_REO_R0_REO2FW_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_REO_R0_REO2FW_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_REO_R0_REO2FW_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_REO_R0_REO2FW_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_REO_R0_REO2FW_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_REO_R0_REO2FW_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_REO_R0_REO2FW_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_REO_R0_REO2FW_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_REO_R0_REO2FW_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_REO_R0_REO2FW_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_REO_R0_REO2FW_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_REO_R0_REO2FW_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_REO_R0_REO2FW_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_REO_R0_REO2FW_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_REO_R0_REO2FW_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_REO_R0_REO2FW_RING_MISC___M 0x03FFFFFF +#define UMAC_REO_R0_REO2FW_RING_MISC___S 0 + +#define UMAC_REO_R0_REO2FW_RING_HP_ADDR_LSB (0x00A38468) +#define UMAC_REO_R0_REO2FW_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2FW_RING_HP_ADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2FW_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2FW_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2FW_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define UMAC_REO_R0_REO2FW_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2FW_RING_HP_ADDR_LSB___S 0 + +#define UMAC_REO_R0_REO2FW_RING_HP_ADDR_MSB (0x00A3846C) +#define UMAC_REO_R0_REO2FW_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2FW_RING_HP_ADDR_MSB___POR 0x00000000 +#define UMAC_REO_R0_REO2FW_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_REO_R0_REO2FW_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_REO2FW_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define UMAC_REO_R0_REO2FW_RING_HP_ADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_REO2FW_RING_HP_ADDR_MSB___S 0 + +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP (0x00A38478) +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP___S 0 + +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS (0x00A3847C) +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS___S 0 + +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER (0x00A38480) +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define UMAC_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER___S 0 + +#define UMAC_REO_R0_REO2FW_RING_MSI1_BASE_LSB (0x00A3849C) +#define UMAC_REO_R0_REO2FW_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2FW_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO2FW_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_REO_R0_REO2FW_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2FW_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_REO_R0_REO2FW_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2FW_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_REO_R0_REO2FW_RING_MSI1_BASE_MSB (0x00A384A0) +#define UMAC_REO_R0_REO2FW_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2FW_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_REO_R0_REO2FW_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_REO_R0_REO2FW_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_REO_R0_REO2FW_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_REO_R0_REO2FW_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_REO_R0_REO2FW_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_REO_R0_REO2FW_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_REO_R0_REO2FW_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_REO_R0_REO2FW_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_REO_R0_REO2FW_RING_MSI1_DATA (0x00A384A4) +#define UMAC_REO_R0_REO2FW_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2FW_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_REO_R0_REO2FW_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_REO_R0_REO2FW_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2FW_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_REO_R0_REO2FW_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_REO_R0_REO2FW_RING_MSI1_DATA___S 0 + +#define UMAC_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET (0x00A384A8) +#define UMAC_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_REO_R0_REO_RELEASE_RING_BASE_LSB (0x00A384AC) +#define UMAC_REO_R0_REO_RELEASE_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_RELEASE_RING_BASE_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_REO_R0_REO_RELEASE_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO_RELEASE_RING_BASE_LSB___S 0 + +#define UMAC_REO_R0_REO_RELEASE_RING_BASE_MSB (0x00A384B0) +#define UMAC_REO_R0_REO_RELEASE_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_RELEASE_RING_BASE_MSB___POR 0x00000000 +#define UMAC_REO_R0_REO_RELEASE_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_REO_R0_REO_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_REO_R0_REO_RELEASE_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_REO_R0_REO_RELEASE_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_REO_R0_REO_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_REO_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_REO_R0_REO_RELEASE_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_REO_R0_REO_RELEASE_RING_BASE_MSB___S 0 + +#define UMAC_REO_R0_REO_RELEASE_RING_ID (0x00A384B4) +#define UMAC_REO_R0_REO_RELEASE_RING_ID___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_RELEASE_RING_ID___POR 0x00000000 +#define UMAC_REO_R0_REO_RELEASE_RING_ID__RING_ID___POR 0x00 +#define UMAC_REO_R0_REO_RELEASE_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_REO_R0_REO_RELEASE_RING_ID__RING_ID___M 0x0000FF00 +#define UMAC_REO_R0_REO_RELEASE_RING_ID__RING_ID___S 8 +#define UMAC_REO_R0_REO_RELEASE_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_REO_R0_REO_RELEASE_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_REO_R0_REO_RELEASE_RING_ID___M 0x0000FFFF +#define UMAC_REO_R0_REO_RELEASE_RING_ID___S 0 + +#define UMAC_REO_R0_REO_RELEASE_RING_STATUS (0x00A384B8) +#define UMAC_REO_R0_REO_RELEASE_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_REO_RELEASE_RING_STATUS___POR 0x00000000 +#define UMAC_REO_R0_REO_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_REO_R0_REO_RELEASE_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_REO_R0_REO_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_REO_R0_REO_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_REO_R0_REO_RELEASE_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_REO_R0_REO_RELEASE_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_REO_R0_REO_RELEASE_RING_STATUS___M 0xFFFFFFFF +#define UMAC_REO_R0_REO_RELEASE_RING_STATUS___S 0 + +#define UMAC_REO_R0_REO_RELEASE_RING_MISC (0x00A384BC) +#define UMAC_REO_R0_REO_RELEASE_RING_MISC___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_RELEASE_RING_MISC___POR 0x00000080 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__LOOP_CNT___POR 0x0 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__LOOP_CNT___M 0x03C00000 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__LOOP_CNT___S 22 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_REO_R0_REO_RELEASE_RING_MISC___M 0x03FFFFFF +#define UMAC_REO_R0_REO_RELEASE_RING_MISC___S 0 + +#define UMAC_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB (0x00A384C0) +#define UMAC_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define UMAC_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB___S 0 + +#define UMAC_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB (0x00A384C4) +#define UMAC_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB___POR 0x00000000 +#define UMAC_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define UMAC_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB___S 0 + +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP (0x00A384D0) +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP___S 0 + +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS (0x00A384D4) +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS___S 0 + +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER (0x00A384D8) +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define UMAC_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER___S 0 + +#define UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB (0x00A384F4) +#define UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB (0x00A384F8) +#define UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_REO_R0_REO_RELEASE_RING_MSI1_DATA (0x00A384FC) +#define UMAC_REO_R0_REO_RELEASE_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_RELEASE_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_REO_R0_REO_RELEASE_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_REO_R0_REO_RELEASE_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_REO_R0_REO_RELEASE_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_REO_R0_REO_RELEASE_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_REO_R0_REO_RELEASE_RING_MSI1_DATA___S 0 + +#define UMAC_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET (0x00A38500) +#define UMAC_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_REO_R0_REO_STATUS_RING_BASE_LSB (0x00A38504) +#define UMAC_REO_R0_REO_STATUS_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_STATUS_RING_BASE_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO_STATUS_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO_STATUS_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO_STATUS_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_REO_R0_REO_STATUS_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO_STATUS_RING_BASE_LSB___S 0 + +#define UMAC_REO_R0_REO_STATUS_RING_BASE_MSB (0x00A38508) +#define UMAC_REO_R0_REO_STATUS_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_STATUS_RING_BASE_MSB___POR 0x00000000 +#define UMAC_REO_R0_REO_STATUS_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_REO_R0_REO_STATUS_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_REO_R0_REO_STATUS_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_REO_R0_REO_STATUS_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_REO_R0_REO_STATUS_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_REO_STATUS_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_REO_R0_REO_STATUS_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_REO_R0_REO_STATUS_RING_BASE_MSB___S 0 + +#define UMAC_REO_R0_REO_STATUS_RING_ID (0x00A3850C) +#define UMAC_REO_R0_REO_STATUS_RING_ID___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_STATUS_RING_ID___POR 0x00000000 +#define UMAC_REO_R0_REO_STATUS_RING_ID__RING_ID___POR 0x00 +#define UMAC_REO_R0_REO_STATUS_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_REO_R0_REO_STATUS_RING_ID__RING_ID___M 0x0000FF00 +#define UMAC_REO_R0_REO_STATUS_RING_ID__RING_ID___S 8 +#define UMAC_REO_R0_REO_STATUS_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_REO_R0_REO_STATUS_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_REO_R0_REO_STATUS_RING_ID___M 0x0000FFFF +#define UMAC_REO_R0_REO_STATUS_RING_ID___S 0 + +#define UMAC_REO_R0_REO_STATUS_RING_STATUS (0x00A38510) +#define UMAC_REO_R0_REO_STATUS_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_REO_STATUS_RING_STATUS___POR 0x00000000 +#define UMAC_REO_R0_REO_STATUS_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_REO_R0_REO_STATUS_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_REO_R0_REO_STATUS_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_REO_R0_REO_STATUS_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_REO_R0_REO_STATUS_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_REO_R0_REO_STATUS_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_REO_R0_REO_STATUS_RING_STATUS___M 0xFFFFFFFF +#define UMAC_REO_R0_REO_STATUS_RING_STATUS___S 0 + +#define UMAC_REO_R0_REO_STATUS_RING_MISC (0x00A38514) +#define UMAC_REO_R0_REO_STATUS_RING_MISC___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_STATUS_RING_MISC___POR 0x00000080 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__LOOP_CNT___POR 0x0 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__LOOP_CNT___M 0x03C00000 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__LOOP_CNT___S 22 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_REO_R0_REO_STATUS_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_REO_R0_REO_STATUS_RING_MISC___M 0x03FFFFFF +#define UMAC_REO_R0_REO_STATUS_RING_MISC___S 0 + +#define UMAC_REO_R0_REO_STATUS_RING_HP_ADDR_LSB (0x00A38518) +#define UMAC_REO_R0_REO_STATUS_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_STATUS_RING_HP_ADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO_STATUS_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO_STATUS_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO_STATUS_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define UMAC_REO_R0_REO_STATUS_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO_STATUS_RING_HP_ADDR_LSB___S 0 + +#define UMAC_REO_R0_REO_STATUS_RING_HP_ADDR_MSB (0x00A3851C) +#define UMAC_REO_R0_REO_STATUS_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_STATUS_RING_HP_ADDR_MSB___POR 0x00000000 +#define UMAC_REO_R0_REO_STATUS_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_REO_R0_REO_STATUS_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_REO_STATUS_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define UMAC_REO_R0_REO_STATUS_RING_HP_ADDR_MSB___M 0x000000FF +#define UMAC_REO_R0_REO_STATUS_RING_HP_ADDR_MSB___S 0 + +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP (0x00A38528) +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP___S 0 + +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS (0x00A3852C) +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS___S 0 + +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER (0x00A38530) +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define UMAC_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER___S 0 + +#define UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB (0x00A3854C) +#define UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB (0x00A38550) +#define UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_REO_R0_REO_STATUS_RING_MSI1_DATA (0x00A38554) +#define UMAC_REO_R0_REO_STATUS_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_STATUS_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_REO_R0_REO_STATUS_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_REO_R0_REO_STATUS_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_REO_R0_REO_STATUS_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_REO_R0_REO_STATUS_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_REO_R0_REO_STATUS_RING_MSI1_DATA___S 0 + +#define UMAC_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET (0x00A38558) +#define UMAC_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_REO_R0_WATCHDOG_TIMEOUT (0x00A3855C) +#define UMAC_REO_R0_WATCHDOG_TIMEOUT___RWC QCSR_REG_RW +#define UMAC_REO_R0_WATCHDOG_TIMEOUT___POR 0x00000000 +#define UMAC_REO_R0_WATCHDOG_TIMEOUT__RESOLUTION_UNITS___POR 0x0 +#define UMAC_REO_R0_WATCHDOG_TIMEOUT__SRNG_TIMEOUT___POR 0x000 +#define UMAC_REO_R0_WATCHDOG_TIMEOUT__RESOLUTION_UNITS___M 0x00003000 +#define UMAC_REO_R0_WATCHDOG_TIMEOUT__RESOLUTION_UNITS___S 12 +#define UMAC_REO_R0_WATCHDOG_TIMEOUT__SRNG_TIMEOUT___M 0x00000FFF +#define UMAC_REO_R0_WATCHDOG_TIMEOUT__SRNG_TIMEOUT___S 0 +#define UMAC_REO_R0_WATCHDOG_TIMEOUT___M 0x00003FFF +#define UMAC_REO_R0_WATCHDOG_TIMEOUT___S 0 + +#define UMAC_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0 (0x00A38560) +#define UMAC_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0___RWC QCSR_REG_RO +#define UMAC_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0___POR 0x00000000 +#define UMAC_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0__ERROR_DATA___POR 0x00000000 +#define UMAC_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0__ERROR_DATA___M 0xFFFFFFFF +#define UMAC_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0__ERROR_DATA___S 0 +#define UMAC_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0___M 0xFFFFFFFF +#define UMAC_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0___S 0 + +#define UMAC_REO_R0_AGING_THRESHOLD_IX_0 (0x00A38564) +#define UMAC_REO_R0_AGING_THRESHOLD_IX_0___RWC QCSR_REG_RW +#define UMAC_REO_R0_AGING_THRESHOLD_IX_0___POR 0x000186A0 +#define UMAC_REO_R0_AGING_THRESHOLD_IX_0__AGING_THRESHOLD_AC0___POR 0x000186A0 +#define UMAC_REO_R0_AGING_THRESHOLD_IX_0__AGING_THRESHOLD_AC0___M 0xFFFFFFFF +#define UMAC_REO_R0_AGING_THRESHOLD_IX_0__AGING_THRESHOLD_AC0___S 0 +#define UMAC_REO_R0_AGING_THRESHOLD_IX_0___M 0xFFFFFFFF +#define UMAC_REO_R0_AGING_THRESHOLD_IX_0___S 0 + +#define UMAC_REO_R0_AGING_THRESHOLD_IX_1 (0x00A38568) +#define UMAC_REO_R0_AGING_THRESHOLD_IX_1___RWC QCSR_REG_RW +#define UMAC_REO_R0_AGING_THRESHOLD_IX_1___POR 0x000186A0 +#define UMAC_REO_R0_AGING_THRESHOLD_IX_1__AGING_THRESHOLD_AC1___POR 0x000186A0 +#define UMAC_REO_R0_AGING_THRESHOLD_IX_1__AGING_THRESHOLD_AC1___M 0xFFFFFFFF +#define UMAC_REO_R0_AGING_THRESHOLD_IX_1__AGING_THRESHOLD_AC1___S 0 +#define UMAC_REO_R0_AGING_THRESHOLD_IX_1___M 0xFFFFFFFF +#define UMAC_REO_R0_AGING_THRESHOLD_IX_1___S 0 + +#define UMAC_REO_R0_AGING_THRESHOLD_IX_2 (0x00A3856C) +#define UMAC_REO_R0_AGING_THRESHOLD_IX_2___RWC QCSR_REG_RW +#define UMAC_REO_R0_AGING_THRESHOLD_IX_2___POR 0x00009C40 +#define UMAC_REO_R0_AGING_THRESHOLD_IX_2__AGING_THRESHOLD_AC2___POR 0x00009C40 +#define UMAC_REO_R0_AGING_THRESHOLD_IX_2__AGING_THRESHOLD_AC2___M 0xFFFFFFFF +#define UMAC_REO_R0_AGING_THRESHOLD_IX_2__AGING_THRESHOLD_AC2___S 0 +#define UMAC_REO_R0_AGING_THRESHOLD_IX_2___M 0xFFFFFFFF +#define UMAC_REO_R0_AGING_THRESHOLD_IX_2___S 0 + +#define UMAC_REO_R0_AGING_THRESHOLD_IX_3 (0x00A38570) +#define UMAC_REO_R0_AGING_THRESHOLD_IX_3___RWC QCSR_REG_RW +#define UMAC_REO_R0_AGING_THRESHOLD_IX_3___POR 0x00009C40 +#define UMAC_REO_R0_AGING_THRESHOLD_IX_3__AGING_THRESHOLD_AC3___POR 0x00009C40 +#define UMAC_REO_R0_AGING_THRESHOLD_IX_3__AGING_THRESHOLD_AC3___M 0xFFFFFFFF +#define UMAC_REO_R0_AGING_THRESHOLD_IX_3__AGING_THRESHOLD_AC3___S 0 +#define UMAC_REO_R0_AGING_THRESHOLD_IX_3___M 0xFFFFFFFF +#define UMAC_REO_R0_AGING_THRESHOLD_IX_3___S 0 + +#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_0 (0x00A38574) +#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_0___RWC QCSR_REG_RO +#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_0___POR 0x00000000 +#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_0__AGING_HEADPTR_LO_BITS___POR 0x00000000 +#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_0__AGING_HEADPTR_LO_BITS___M 0xFFFFFFFF +#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_0__AGING_HEADPTR_LO_BITS___S 0 +#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_0___M 0xFFFFFFFF +#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_0___S 0 + +#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_0 (0x00A38578) +#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_0___RWC QCSR_REG_RO +#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_0___POR 0x00000000 +#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_0__AGING_HEADPTR_HI_BITS___POR 0x00 +#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_0__AGING_HEADPTR_HI_BITS___M 0x000000FF +#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_0__AGING_HEADPTR_HI_BITS___S 0 +#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_0___M 0x000000FF +#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_0___S 0 + +#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_0 (0x00A3857C) +#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_0___RWC QCSR_REG_RO +#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_0___POR 0x00000000 +#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_0__AGING_TAILPTR_LO_BITS___POR 0x00000000 +#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_0__AGING_TAILPTR_LO_BITS___M 0xFFFFFFFF +#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_0__AGING_TAILPTR_LO_BITS___S 0 +#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_0___M 0xFFFFFFFF +#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_0___S 0 + +#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_0 (0x00A38580) +#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_0___RWC QCSR_REG_RO +#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_0___POR 0x00000000 +#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_0__AGING_TAILPTR_HI_BITS___POR 0x00 +#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_0__AGING_TAILPTR_HI_BITS___M 0x000000FF +#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_0__AGING_TAILPTR_HI_BITS___S 0 +#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_0___M 0x000000FF +#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_0___S 0 + +#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_1 (0x00A38584) +#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_1___RWC QCSR_REG_RO +#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_1___POR 0x00000000 +#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_1__AGING_HEADPTR_LO_BITS___POR 0x00000000 +#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_1__AGING_HEADPTR_LO_BITS___M 0xFFFFFFFF +#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_1__AGING_HEADPTR_LO_BITS___S 0 +#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_1___M 0xFFFFFFFF +#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_1___S 0 + +#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_1 (0x00A38588) +#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_1___RWC QCSR_REG_RO +#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_1___POR 0x00000000 +#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_1__AGING_HEADPTR_HI_BITS___POR 0x00 +#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_1__AGING_HEADPTR_HI_BITS___M 0x000000FF +#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_1__AGING_HEADPTR_HI_BITS___S 0 +#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_1___M 0x000000FF +#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_1___S 0 + +#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_1 (0x00A3858C) +#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_1___RWC QCSR_REG_RO +#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_1___POR 0x00000000 +#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_1__AGING_TAILPTR_LO_BITS___POR 0x00000000 +#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_1__AGING_TAILPTR_LO_BITS___M 0xFFFFFFFF +#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_1__AGING_TAILPTR_LO_BITS___S 0 +#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_1___M 0xFFFFFFFF +#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_1___S 0 + +#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_1 (0x00A38590) +#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_1___RWC QCSR_REG_RO +#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_1___POR 0x00000000 +#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_1__AGING_TAILPTR_HI_BITS___POR 0x00 +#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_1__AGING_TAILPTR_HI_BITS___M 0x000000FF +#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_1__AGING_TAILPTR_HI_BITS___S 0 +#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_1___M 0x000000FF +#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_1___S 0 + +#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_2 (0x00A38594) +#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_2___RWC QCSR_REG_RO +#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_2___POR 0x00000000 +#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_2__AGING_HEADPTR_LO_BITS___POR 0x00000000 +#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_2__AGING_HEADPTR_LO_BITS___M 0xFFFFFFFF +#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_2__AGING_HEADPTR_LO_BITS___S 0 +#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_2___M 0xFFFFFFFF +#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_2___S 0 + +#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_2 (0x00A38598) +#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_2___RWC QCSR_REG_RO +#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_2___POR 0x00000000 +#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_2__AGING_HEADPTR_HI_BITS___POR 0x00 +#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_2__AGING_HEADPTR_HI_BITS___M 0x000000FF +#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_2__AGING_HEADPTR_HI_BITS___S 0 +#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_2___M 0x000000FF +#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_2___S 0 + +#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_2 (0x00A3859C) +#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_2___RWC QCSR_REG_RO +#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_2___POR 0x00000000 +#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_2__AGING_TAILPTR_LO_BITS___POR 0x00000000 +#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_2__AGING_TAILPTR_LO_BITS___M 0xFFFFFFFF +#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_2__AGING_TAILPTR_LO_BITS___S 0 +#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_2___M 0xFFFFFFFF +#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_2___S 0 + +#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_2 (0x00A385A0) +#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_2___RWC QCSR_REG_RO +#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_2___POR 0x00000000 +#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_2__AGING_TAILPTR_HI_BITS___POR 0x00 +#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_2__AGING_TAILPTR_HI_BITS___M 0x000000FF +#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_2__AGING_TAILPTR_HI_BITS___S 0 +#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_2___M 0x000000FF +#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_2___S 0 + +#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_3 (0x00A385A4) +#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_3___RWC QCSR_REG_RO +#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_3___POR 0x00000000 +#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_3__AGING_HEADPTR_LO_BITS___POR 0x00000000 +#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_3__AGING_HEADPTR_LO_BITS___M 0xFFFFFFFF +#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_3__AGING_HEADPTR_LO_BITS___S 0 +#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_3___M 0xFFFFFFFF +#define UMAC_REO_R0_AGING_LINK_HEADPTR_LO_IX_3___S 0 + +#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_3 (0x00A385A8) +#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_3___RWC QCSR_REG_RO +#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_3___POR 0x00000000 +#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_3__AGING_HEADPTR_HI_BITS___POR 0x00 +#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_3__AGING_HEADPTR_HI_BITS___M 0x000000FF +#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_3__AGING_HEADPTR_HI_BITS___S 0 +#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_3___M 0x000000FF +#define UMAC_REO_R0_AGING_LINK_HEADPTR_HI_IX_3___S 0 + +#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_3 (0x00A385AC) +#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_3___RWC QCSR_REG_RO +#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_3___POR 0x00000000 +#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_3__AGING_TAILPTR_LO_BITS___POR 0x00000000 +#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_3__AGING_TAILPTR_LO_BITS___M 0xFFFFFFFF +#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_3__AGING_TAILPTR_LO_BITS___S 0 +#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_3___M 0xFFFFFFFF +#define UMAC_REO_R0_AGING_LINK_TAILPTR_LO_IX_3___S 0 + +#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_3 (0x00A385B0) +#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_3___RWC QCSR_REG_RO +#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_3___POR 0x00000000 +#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_3__AGING_TAILPTR_HI_BITS___POR 0x00 +#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_3__AGING_TAILPTR_HI_BITS___M 0x000000FF +#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_3__AGING_TAILPTR_HI_BITS___S 0 +#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_3___M 0x000000FF +#define UMAC_REO_R0_AGING_LINK_TAILPTR_HI_IX_3___S 0 + +#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_0 (0x00A385B4) +#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_0___RWC QCSR_REG_RO +#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_0___POR 0x00000000 +#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_0__AGING_NUM_QUEUES_AC0___POR 0x0000 +#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_0__AGING_NUM_QUEUES_AC0___M 0x0000FFFF +#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_0__AGING_NUM_QUEUES_AC0___S 0 +#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_0___M 0x0000FFFF +#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_0___S 0 + +#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_1 (0x00A385B8) +#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_1___RWC QCSR_REG_RO +#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_1___POR 0x00000000 +#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_1__AGING_NUM_QUEUES_AC1___POR 0x0000 +#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_1__AGING_NUM_QUEUES_AC1___M 0x0000FFFF +#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_1__AGING_NUM_QUEUES_AC1___S 0 +#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_1___M 0x0000FFFF +#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_1___S 0 + +#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_2 (0x00A385BC) +#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_2___RWC QCSR_REG_RO +#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_2___POR 0x00000000 +#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_2__AGING_NUM_QUEUES_AC2___POR 0x0000 +#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_2__AGING_NUM_QUEUES_AC2___M 0x0000FFFF +#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_2__AGING_NUM_QUEUES_AC2___S 0 +#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_2___M 0x0000FFFF +#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_2___S 0 + +#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_3 (0x00A385C0) +#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_3___RWC QCSR_REG_RO +#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_3___POR 0x00000000 +#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_3__AGING_NUM_QUEUES_AC3___POR 0x0000 +#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_3__AGING_NUM_QUEUES_AC3___M 0x0000FFFF +#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_3__AGING_NUM_QUEUES_AC3___S 0 +#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_3___M 0x0000FFFF +#define UMAC_REO_R0_AGING_NUM_QUEUES_IX_3___S 0 + +#define UMAC_REO_R0_AGING_TIMESTAMP_IX_0 (0x00A385C4) +#define UMAC_REO_R0_AGING_TIMESTAMP_IX_0___RWC QCSR_REG_RO +#define UMAC_REO_R0_AGING_TIMESTAMP_IX_0___POR 0x00000000 +#define UMAC_REO_R0_AGING_TIMESTAMP_IX_0__AGING_TIMESTAMP_AC0___POR 0x00000000 +#define UMAC_REO_R0_AGING_TIMESTAMP_IX_0__AGING_TIMESTAMP_AC0___M 0xFFFFFFFF +#define UMAC_REO_R0_AGING_TIMESTAMP_IX_0__AGING_TIMESTAMP_AC0___S 0 +#define UMAC_REO_R0_AGING_TIMESTAMP_IX_0___M 0xFFFFFFFF +#define UMAC_REO_R0_AGING_TIMESTAMP_IX_0___S 0 + +#define UMAC_REO_R0_AGING_TIMESTAMP_IX_1 (0x00A385C8) +#define UMAC_REO_R0_AGING_TIMESTAMP_IX_1___RWC QCSR_REG_RO +#define UMAC_REO_R0_AGING_TIMESTAMP_IX_1___POR 0x00000000 +#define UMAC_REO_R0_AGING_TIMESTAMP_IX_1__AGING_TIMESTAMP_AC1___POR 0x00000000 +#define UMAC_REO_R0_AGING_TIMESTAMP_IX_1__AGING_TIMESTAMP_AC1___M 0xFFFFFFFF +#define UMAC_REO_R0_AGING_TIMESTAMP_IX_1__AGING_TIMESTAMP_AC1___S 0 +#define UMAC_REO_R0_AGING_TIMESTAMP_IX_1___M 0xFFFFFFFF +#define UMAC_REO_R0_AGING_TIMESTAMP_IX_1___S 0 + +#define UMAC_REO_R0_AGING_TIMESTAMP_IX_2 (0x00A385CC) +#define UMAC_REO_R0_AGING_TIMESTAMP_IX_2___RWC QCSR_REG_RO +#define UMAC_REO_R0_AGING_TIMESTAMP_IX_2___POR 0x00000000 +#define UMAC_REO_R0_AGING_TIMESTAMP_IX_2__AGING_TIMESTAMP_AC2___POR 0x00000000 +#define UMAC_REO_R0_AGING_TIMESTAMP_IX_2__AGING_TIMESTAMP_AC2___M 0xFFFFFFFF +#define UMAC_REO_R0_AGING_TIMESTAMP_IX_2__AGING_TIMESTAMP_AC2___S 0 +#define UMAC_REO_R0_AGING_TIMESTAMP_IX_2___M 0xFFFFFFFF +#define UMAC_REO_R0_AGING_TIMESTAMP_IX_2___S 0 + +#define UMAC_REO_R0_AGING_TIMESTAMP_IX_3 (0x00A385D0) +#define UMAC_REO_R0_AGING_TIMESTAMP_IX_3___RWC QCSR_REG_RO +#define UMAC_REO_R0_AGING_TIMESTAMP_IX_3___POR 0x00000000 +#define UMAC_REO_R0_AGING_TIMESTAMP_IX_3__AGING_TIMESTAMP_AC3___POR 0x00000000 +#define UMAC_REO_R0_AGING_TIMESTAMP_IX_3__AGING_TIMESTAMP_AC3___M 0xFFFFFFFF +#define UMAC_REO_R0_AGING_TIMESTAMP_IX_3__AGING_TIMESTAMP_AC3___S 0 +#define UMAC_REO_R0_AGING_TIMESTAMP_IX_3___M 0xFFFFFFFF +#define UMAC_REO_R0_AGING_TIMESTAMP_IX_3___S 0 + +#define UMAC_REO_R0_AGING_CONTROL (0x00A385D4) +#define UMAC_REO_R0_AGING_CONTROL___RWC QCSR_REG_RW +#define UMAC_REO_R0_AGING_CONTROL___POR 0x00000000 +#define UMAC_REO_R0_AGING_CONTROL__PERMPDU_UPDATE_THRESHOLD___POR 0x00 +#define UMAC_REO_R0_AGING_CONTROL__PERMPDU_UPDATE_THRESHOLD___M 0x0000001F +#define UMAC_REO_R0_AGING_CONTROL__PERMPDU_UPDATE_THRESHOLD___S 0 +#define UMAC_REO_R0_AGING_CONTROL___M 0x0000001F +#define UMAC_REO_R0_AGING_CONTROL___S 0 + +#define UMAC_REO_R0_MISC_CTL (0x00A385D8) +#define UMAC_REO_R0_MISC_CTL___RWC QCSR_REG_RW +#define UMAC_REO_R0_MISC_CTL___POR 0x000C0000 +#define UMAC_REO_R0_MISC_CTL__FRAGMENT_DEST_RING___POR 0x6 +#define UMAC_REO_R0_MISC_CTL__CACHE_FLUSH_Q_DESC_ONLY___POR 0x0 +#define UMAC_REO_R0_MISC_CTL__MSI_ENABLE_CHK_BIT___POR 0x0 +#define UMAC_REO_R0_MISC_CTL__SPARE_CONTROL___POR 0x0000 +#define UMAC_REO_R0_MISC_CTL__FRAGMENT_DEST_RING___M 0x001E0000 +#define UMAC_REO_R0_MISC_CTL__FRAGMENT_DEST_RING___S 17 +#define UMAC_REO_R0_MISC_CTL__CACHE_FLUSH_Q_DESC_ONLY___M 0x00010000 +#define UMAC_REO_R0_MISC_CTL__CACHE_FLUSH_Q_DESC_ONLY___S 16 +#define UMAC_REO_R0_MISC_CTL__MSI_ENABLE_CHK_BIT___M 0x00008000 +#define UMAC_REO_R0_MISC_CTL__MSI_ENABLE_CHK_BIT___S 15 +#define UMAC_REO_R0_MISC_CTL__SPARE_CONTROL___M 0x00007FFF +#define UMAC_REO_R0_MISC_CTL__SPARE_CONTROL___S 0 +#define UMAC_REO_R0_MISC_CTL___M 0x001FFFFF +#define UMAC_REO_R0_MISC_CTL___S 0 + +#define UMAC_REO_R0_HIGH_MEMORY_THRESHOLD (0x00A385DC) +#define UMAC_REO_R0_HIGH_MEMORY_THRESHOLD___RWC QCSR_REG_RW +#define UMAC_REO_R0_HIGH_MEMORY_THRESHOLD___POR 0xFFFFFFFF +#define UMAC_REO_R0_HIGH_MEMORY_THRESHOLD__HIGH_MEMORY_THRESHOLD___POR 0xFFFFFFFF +#define UMAC_REO_R0_HIGH_MEMORY_THRESHOLD__HIGH_MEMORY_THRESHOLD___M 0xFFFFFFFF +#define UMAC_REO_R0_HIGH_MEMORY_THRESHOLD__HIGH_MEMORY_THRESHOLD___S 0 +#define UMAC_REO_R0_HIGH_MEMORY_THRESHOLD___M 0xFFFFFFFF +#define UMAC_REO_R0_HIGH_MEMORY_THRESHOLD___S 0 + +#define UMAC_REO_R0_AC_BUFFERS_USED_IX_0 (0x00A385E0) +#define UMAC_REO_R0_AC_BUFFERS_USED_IX_0___RWC QCSR_REG_RO +#define UMAC_REO_R0_AC_BUFFERS_USED_IX_0___POR 0x00000000 +#define UMAC_REO_R0_AC_BUFFERS_USED_IX_0__BUFFERS_USED___POR 0x00000000 +#define UMAC_REO_R0_AC_BUFFERS_USED_IX_0__BUFFERS_USED___M 0xFFFFFFFF +#define UMAC_REO_R0_AC_BUFFERS_USED_IX_0__BUFFERS_USED___S 0 +#define UMAC_REO_R0_AC_BUFFERS_USED_IX_0___M 0xFFFFFFFF +#define UMAC_REO_R0_AC_BUFFERS_USED_IX_0___S 0 + +#define UMAC_REO_R0_AC_BUFFERS_USED_IX_1 (0x00A385E4) +#define UMAC_REO_R0_AC_BUFFERS_USED_IX_1___RWC QCSR_REG_RO +#define UMAC_REO_R0_AC_BUFFERS_USED_IX_1___POR 0x00000000 +#define UMAC_REO_R0_AC_BUFFERS_USED_IX_1__BUFFERS_USED___POR 0x00000000 +#define UMAC_REO_R0_AC_BUFFERS_USED_IX_1__BUFFERS_USED___M 0xFFFFFFFF +#define UMAC_REO_R0_AC_BUFFERS_USED_IX_1__BUFFERS_USED___S 0 +#define UMAC_REO_R0_AC_BUFFERS_USED_IX_1___M 0xFFFFFFFF +#define UMAC_REO_R0_AC_BUFFERS_USED_IX_1___S 0 + +#define UMAC_REO_R0_AC_BUFFERS_USED_IX_2 (0x00A385E8) +#define UMAC_REO_R0_AC_BUFFERS_USED_IX_2___RWC QCSR_REG_RO +#define UMAC_REO_R0_AC_BUFFERS_USED_IX_2___POR 0x00000000 +#define UMAC_REO_R0_AC_BUFFERS_USED_IX_2__BUFFERS_USED___POR 0x00000000 +#define UMAC_REO_R0_AC_BUFFERS_USED_IX_2__BUFFERS_USED___M 0xFFFFFFFF +#define UMAC_REO_R0_AC_BUFFERS_USED_IX_2__BUFFERS_USED___S 0 +#define UMAC_REO_R0_AC_BUFFERS_USED_IX_2___M 0xFFFFFFFF +#define UMAC_REO_R0_AC_BUFFERS_USED_IX_2___S 0 + +#define UMAC_REO_R0_AC_BUFFERS_USED_IX_3 (0x00A385EC) +#define UMAC_REO_R0_AC_BUFFERS_USED_IX_3___RWC QCSR_REG_RO +#define UMAC_REO_R0_AC_BUFFERS_USED_IX_3___POR 0x00000000 +#define UMAC_REO_R0_AC_BUFFERS_USED_IX_3__BUFFERS_USED___POR 0x00000000 +#define UMAC_REO_R0_AC_BUFFERS_USED_IX_3__BUFFERS_USED___M 0xFFFFFFFF +#define UMAC_REO_R0_AC_BUFFERS_USED_IX_3__BUFFERS_USED___S 0 +#define UMAC_REO_R0_AC_BUFFERS_USED_IX_3___M 0xFFFFFFFF +#define UMAC_REO_R0_AC_BUFFERS_USED_IX_3___S 0 + +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0 (0x00A385F0) +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0___RWC QCSR_REG_RW +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0___POR 0x00FFFFFF +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0__THRESHOLD___POR 0xFFFFFF +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0__THRESHOLD___M 0x00FFFFFF +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0__THRESHOLD___S 0 +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0___M 0x00FFFFFF +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0___S 0 + +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1 (0x00A385F4) +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1___RWC QCSR_REG_RW +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1___POR 0x00FFFFFF +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1__THRESHOLD___POR 0xFFFFFF +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1__THRESHOLD___M 0x00FFFFFF +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1__THRESHOLD___S 0 +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1___M 0x00FFFFFF +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1___S 0 + +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2 (0x00A385F8) +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2___RWC QCSR_REG_RW +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2___POR 0x00FFFFFF +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2__THRESHOLD___POR 0xFFFFFF +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2__THRESHOLD___M 0x00FFFFFF +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2__THRESHOLD___S 0 +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2___M 0x00FFFFFF +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2___S 0 + +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL (0x00A385FC) +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL___RWC QCSR_REG_RW +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL___POR 0x03FFFFFF +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL__THRESHOLD___POR 0x3FFFFFF +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL__THRESHOLD___M 0x03FFFFFF +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL__THRESHOLD___S 0 +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL___M 0x03FFFFFF +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL___S 0 + +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0 (0x00A38600) +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0___RWC QCSR_REG_RW +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0___POR 0x00000000 +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0__COUNT___POR 0x000000 +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0__COUNT___M 0x00FFFFFF +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0__COUNT___S 0 +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0___M 0x00FFFFFF +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0___S 0 + +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1 (0x00A38604) +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1___RWC QCSR_REG_RW +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1___POR 0x00000000 +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1__COUNT___POR 0x000000 +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1__COUNT___M 0x00FFFFFF +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1__COUNT___S 0 +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1___M 0x00FFFFFF +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1___S 0 + +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2 (0x00A38608) +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2___RWC QCSR_REG_RW +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2___POR 0x00000000 +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2__COUNT___POR 0x000000 +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2__COUNT___M 0x00FFFFFF +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2__COUNT___S 0 +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2___M 0x00FFFFFF +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2___S 0 + +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL (0x00A3860C) +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL___RWC QCSR_REG_RW +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL___POR 0x00000000 +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL__ENABLE_DESC_THRESH_TLV___POR 0x0 +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL__ENABLE_DESC_THRESH_TLV___M 0x00000001 +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL__ENABLE_DESC_THRESH_TLV___S 0 +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL___M 0x00000001 +#define UMAC_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL___S 0 + +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0 (0x00A38610) +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0___RWC QCSR_REG_RO +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0___POR 0x00000000 +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0__ADDRESS_LO_BITS___POR 0x00000000 +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0__ADDRESS_LO_BITS___M 0xFFFFFFFF +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0__ADDRESS_LO_BITS___S 0 +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0___M 0xFFFFFFFF +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0___S 0 + +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0 (0x00A38614) +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0___RWC QCSR_REG_RO +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0___POR 0x00000000 +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0__ADDRESS_HI_BITS___POR 0x00 +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0__ADDRESS_HI_BITS___M 0x000000FF +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0__ADDRESS_HI_BITS___S 0 +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0___M 0x000000FF +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0___S 0 + +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1 (0x00A38618) +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1___RWC QCSR_REG_RO +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1___POR 0x00000000 +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1__ADDRESS_LO_BITS___POR 0x00000000 +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1__ADDRESS_LO_BITS___M 0xFFFFFFFF +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1__ADDRESS_LO_BITS___S 0 +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1___M 0xFFFFFFFF +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1___S 0 + +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1 (0x00A3861C) +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1___RWC QCSR_REG_RO +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1___POR 0x00000000 +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1__ADDRESS_HI_BITS___POR 0x00 +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1__ADDRESS_HI_BITS___M 0x000000FF +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1__ADDRESS_HI_BITS___S 0 +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1___M 0x000000FF +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1___S 0 + +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2 (0x00A38620) +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2___RWC QCSR_REG_RO +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2___POR 0x00000000 +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2__ADDRESS_LO_BITS___POR 0x00000000 +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2__ADDRESS_LO_BITS___M 0xFFFFFFFF +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2__ADDRESS_LO_BITS___S 0 +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2___M 0xFFFFFFFF +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2___S 0 + +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2 (0x00A38624) +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2___RWC QCSR_REG_RO +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2___POR 0x00000000 +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2__ADDRESS_HI_BITS___POR 0x00 +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2__ADDRESS_HI_BITS___M 0x000000FF +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2__ADDRESS_HI_BITS___S 0 +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2___M 0x000000FF +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2___S 0 + +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3 (0x00A38628) +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3___RWC QCSR_REG_RO +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3___POR 0x00000000 +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3__ADDRESS_LO_BITS___POR 0x00000000 +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3__ADDRESS_LO_BITS___M 0xFFFFFFFF +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3__ADDRESS_LO_BITS___S 0 +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3___M 0xFFFFFFFF +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3___S 0 + +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3 (0x00A3862C) +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3___RWC QCSR_REG_RO +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3___POR 0x00000000 +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3__ADDRESS_HI_BITS___POR 0x00 +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3__ADDRESS_HI_BITS___M 0x000000FF +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3__ADDRESS_HI_BITS___S 0 +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3___M 0x000000FF +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3___S 0 + +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_INFO (0x00A38630) +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_INFO___RWC QCSR_REG_RO +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_INFO___POR 0x00000000 +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_INFO__ENTIRE_CACHE_BLOCKED___POR 0x0 +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_INFO__ADDRESS_VALID___POR 0x0 +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_INFO__ENTIRE_CACHE_BLOCKED___M 0x00000010 +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_INFO__ENTIRE_CACHE_BLOCKED___S 4 +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_INFO__ADDRESS_VALID___M 0x0000000F +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_INFO__ADDRESS_VALID___S 0 +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_INFO___M 0x0000001F +#define UMAC_REO_R0_QUEUE_DESC_BLOCK_INFO___S 0 + +#define UMAC_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG (0x00A38634) +#define UMAC_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG___POR 0x00000000 +#define UMAC_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___POR 0x0000 +#define UMAC_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___POR 0x0 +#define UMAC_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___M 0x1FFF0000 +#define UMAC_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___S 16 +#define UMAC_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___M 0x0000000F +#define UMAC_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___S 0 +#define UMAC_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG___M 0x1FFF000F +#define UMAC_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG___S 0 + +#define UMAC_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG (0x00A38638) +#define UMAC_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG___POR 0x00000000 +#define UMAC_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___POR 0x0000 +#define UMAC_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___POR 0x0 +#define UMAC_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___M 0x1FFF0000 +#define UMAC_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___S 16 +#define UMAC_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___M 0x0000000F +#define UMAC_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___S 0 +#define UMAC_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG___M 0x1FFF000F +#define UMAC_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG___S 0 + +#define UMAC_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG (0x00A3863C) +#define UMAC_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG___POR 0x00000000 +#define UMAC_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___POR 0x0000 +#define UMAC_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___POR 0x0 +#define UMAC_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___M 0x1FFF0000 +#define UMAC_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___S 16 +#define UMAC_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___M 0x0000000F +#define UMAC_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___S 0 +#define UMAC_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG___M 0x1FFF000F +#define UMAC_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG___S 0 + +#define UMAC_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG (0x00A38640) +#define UMAC_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG___POR 0x00000000 +#define UMAC_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___POR 0x0000 +#define UMAC_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___POR 0x0 +#define UMAC_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___M 0x1FFF0000 +#define UMAC_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___S 16 +#define UMAC_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___M 0x0000000F +#define UMAC_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___S 0 +#define UMAC_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG___M 0x1FFF000F +#define UMAC_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG___S 0 + +#define UMAC_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG (0x00A38644) +#define UMAC_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG___POR 0x00000000 +#define UMAC_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___POR 0x0000 +#define UMAC_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___POR 0x0 +#define UMAC_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___M 0x1FFF0000 +#define UMAC_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___S 16 +#define UMAC_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___M 0x0000000F +#define UMAC_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___S 0 +#define UMAC_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG___M 0x1FFF000F +#define UMAC_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG___S 0 + +#define UMAC_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG (0x00A38648) +#define UMAC_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG___POR 0x00000000 +#define UMAC_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___POR 0x0000 +#define UMAC_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___POR 0x0 +#define UMAC_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___M 0x1FFF0000 +#define UMAC_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___S 16 +#define UMAC_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___M 0x0000000F +#define UMAC_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___S 0 +#define UMAC_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG___M 0x1FFF000F +#define UMAC_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG___S 0 + +#define UMAC_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG (0x00A3864C) +#define UMAC_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG___POR 0x00000000 +#define UMAC_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___POR 0x0000 +#define UMAC_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___POR 0x0 +#define UMAC_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___M 0x1FFF0000 +#define UMAC_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___S 16 +#define UMAC_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___M 0x0000000F +#define UMAC_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___S 0 +#define UMAC_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG___M 0x1FFF000F +#define UMAC_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG___S 0 + +#define UMAC_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG (0x00A38650) +#define UMAC_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG___RWC QCSR_REG_RW +#define UMAC_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG___POR 0x00000000 +#define UMAC_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___POR 0x0000 +#define UMAC_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___POR 0x0 +#define UMAC_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___M 0x1FFF0000 +#define UMAC_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG__READ_START_OFFSET___S 16 +#define UMAC_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___M 0x0000000F +#define UMAC_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG__CAPTURED_MSDU_DATA_SIZE___S 0 +#define UMAC_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG___M 0x1FFF000F +#define UMAC_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG___S 0 + +#define UMAC_REO_R0_GXI_TESTBUS_LOWER (0x00A38654) +#define UMAC_REO_R0_GXI_TESTBUS_LOWER___RWC QCSR_REG_RO +#define UMAC_REO_R0_GXI_TESTBUS_LOWER___POR 0x00000000 +#define UMAC_REO_R0_GXI_TESTBUS_LOWER__VALUE___POR 0x00000000 +#define UMAC_REO_R0_GXI_TESTBUS_LOWER__VALUE___M 0xFFFFFFFF +#define UMAC_REO_R0_GXI_TESTBUS_LOWER__VALUE___S 0 +#define UMAC_REO_R0_GXI_TESTBUS_LOWER___M 0xFFFFFFFF +#define UMAC_REO_R0_GXI_TESTBUS_LOWER___S 0 + +#define UMAC_REO_R0_GXI_TESTBUS_UPPER (0x00A38658) +#define UMAC_REO_R0_GXI_TESTBUS_UPPER___RWC QCSR_REG_RO +#define UMAC_REO_R0_GXI_TESTBUS_UPPER___POR 0x00000000 +#define UMAC_REO_R0_GXI_TESTBUS_UPPER__VALUE___POR 0x00 +#define UMAC_REO_R0_GXI_TESTBUS_UPPER__VALUE___M 0x000000FF +#define UMAC_REO_R0_GXI_TESTBUS_UPPER__VALUE___S 0 +#define UMAC_REO_R0_GXI_TESTBUS_UPPER___M 0x000000FF +#define UMAC_REO_R0_GXI_TESTBUS_UPPER___S 0 + +#define UMAC_REO_R0_GXI_SM_STATES_IX_0 (0x00A3865C) +#define UMAC_REO_R0_GXI_SM_STATES_IX_0___RWC QCSR_REG_RO +#define UMAC_REO_R0_GXI_SM_STATES_IX_0___POR 0x00000211 +#define UMAC_REO_R0_GXI_SM_STATES_IX_0__SM_STATE_RD_ADDR___POR 0x1 +#define UMAC_REO_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_ADDR___POR 0x01 +#define UMAC_REO_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_DATA___POR 0x1 +#define UMAC_REO_R0_GXI_SM_STATES_IX_0__SM_STATE_RD_ADDR___M 0x00000E00 +#define UMAC_REO_R0_GXI_SM_STATES_IX_0__SM_STATE_RD_ADDR___S 9 +#define UMAC_REO_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_ADDR___M 0x000001F0 +#define UMAC_REO_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_ADDR___S 4 +#define UMAC_REO_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_DATA___M 0x0000000F +#define UMAC_REO_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_DATA___S 0 +#define UMAC_REO_R0_GXI_SM_STATES_IX_0___M 0x00000FFF +#define UMAC_REO_R0_GXI_SM_STATES_IX_0___S 0 + +#define UMAC_REO_R0_GXI_END_OF_TEST_CHECK (0x00A38660) +#define UMAC_REO_R0_GXI_END_OF_TEST_CHECK___RWC QCSR_REG_RW +#define UMAC_REO_R0_GXI_END_OF_TEST_CHECK___POR 0x00000000 +#define UMAC_REO_R0_GXI_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0 +#define UMAC_REO_R0_GXI_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001 +#define UMAC_REO_R0_GXI_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S 0 +#define UMAC_REO_R0_GXI_END_OF_TEST_CHECK___M 0x00000001 +#define UMAC_REO_R0_GXI_END_OF_TEST_CHECK___S 0 + +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE (0x00A38664) +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE___RWC QCSR_REG_RW +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE___POR 0x00000000 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___POR 0x0 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__SPARE___POR 0x0 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WDOG_CTR___POR 0x0 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__RD_FIFO___POR 0x0 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_FIFO___POR 0x0 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_FIFO___POR 0x0 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__RD_AXI_MAS___POR 0x0 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_AXI_MAS___POR 0x0 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_AXI_MAS___POR 0x0 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_CMD___POR 0x0 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_CMD___POR 0x0 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__RD_CMD___POR 0x0 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__CORE___POR 0x0 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___M 0x80000000 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___S 31 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__SPARE___M 0x00000800 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__SPARE___S 11 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WDOG_CTR___M 0x00000400 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WDOG_CTR___S 10 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__RD_FIFO___M 0x00000200 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__RD_FIFO___S 9 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_FIFO___M 0x00000100 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_FIFO___S 8 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_FIFO___M 0x00000080 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_FIFO___S 7 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__RD_AXI_MAS___M 0x00000040 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__RD_AXI_MAS___S 6 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_AXI_MAS___M 0x00000020 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_AXI_MAS___S 5 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_AXI_MAS___M 0x00000010 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_AXI_MAS___S 4 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_CMD___M 0x00000008 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_CMD___S 3 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_CMD___M 0x00000004 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_CMD___S 2 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__RD_CMD___M 0x00000002 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__RD_CMD___S 1 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__CORE___M 0x00000001 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE__CORE___S 0 +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE___M 0x80000FFF +#define UMAC_REO_R0_GXI_CLOCK_GATE_DISABLE___S 0 + +#define UMAC_REO_R0_GXI_GXI_ERR_INTS (0x00A38668) +#define UMAC_REO_R0_GXI_GXI_ERR_INTS___RWC QCSR_REG_RO +#define UMAC_REO_R0_GXI_GXI_ERR_INTS___POR 0x00000000 +#define UMAC_REO_R0_GXI_GXI_ERR_INTS__GXI_WR_LAST_ERR_INT___POR 0x0 +#define UMAC_REO_R0_GXI_GXI_ERR_INTS__GXI_AXI_WR_ERR_INT___POR 0x0 +#define UMAC_REO_R0_GXI_GXI_ERR_INTS__GXI_AXI_RD_ERR_INT___POR 0x0 +#define UMAC_REO_R0_GXI_GXI_ERR_INTS__GXI_WDTIMEOUT_INT___POR 0x0 +#define UMAC_REO_R0_GXI_GXI_ERR_INTS__GXI_WR_LAST_ERR_INT___M 0x01000000 +#define UMAC_REO_R0_GXI_GXI_ERR_INTS__GXI_WR_LAST_ERR_INT___S 24 +#define UMAC_REO_R0_GXI_GXI_ERR_INTS__GXI_AXI_WR_ERR_INT___M 0x00010000 +#define UMAC_REO_R0_GXI_GXI_ERR_INTS__GXI_AXI_WR_ERR_INT___S 16 +#define UMAC_REO_R0_GXI_GXI_ERR_INTS__GXI_AXI_RD_ERR_INT___M 0x00000100 +#define UMAC_REO_R0_GXI_GXI_ERR_INTS__GXI_AXI_RD_ERR_INT___S 8 +#define UMAC_REO_R0_GXI_GXI_ERR_INTS__GXI_WDTIMEOUT_INT___M 0x00000001 +#define UMAC_REO_R0_GXI_GXI_ERR_INTS__GXI_WDTIMEOUT_INT___S 0 +#define UMAC_REO_R0_GXI_GXI_ERR_INTS___M 0x01010101 +#define UMAC_REO_R0_GXI_GXI_ERR_INTS___S 0 + +#define UMAC_REO_R0_GXI_GXI_ERR_STATS (0x00A3866C) +#define UMAC_REO_R0_GXI_GXI_ERR_STATS___RWC QCSR_REG_RO +#define UMAC_REO_R0_GXI_GXI_ERR_STATS___POR 0x00000000 +#define UMAC_REO_R0_GXI_GXI_ERR_STATS__AXI_WR_LAST_ERR_PORT___POR 0x00 +#define UMAC_REO_R0_GXI_GXI_ERR_STATS__AXI_WR_ERR_PORT___POR 0x00 +#define UMAC_REO_R0_GXI_GXI_ERR_STATS__AXI_RD_ERR_PORT___POR 0x00 +#define UMAC_REO_R0_GXI_GXI_ERR_STATS__AXI_WR_LAST_ERR_PORT___M 0x003F0000 +#define UMAC_REO_R0_GXI_GXI_ERR_STATS__AXI_WR_LAST_ERR_PORT___S 16 +#define UMAC_REO_R0_GXI_GXI_ERR_STATS__AXI_WR_ERR_PORT___M 0x00003F00 +#define UMAC_REO_R0_GXI_GXI_ERR_STATS__AXI_WR_ERR_PORT___S 8 +#define UMAC_REO_R0_GXI_GXI_ERR_STATS__AXI_RD_ERR_PORT___M 0x0000003F +#define UMAC_REO_R0_GXI_GXI_ERR_STATS__AXI_RD_ERR_PORT___S 0 +#define UMAC_REO_R0_GXI_GXI_ERR_STATS___M 0x003F3F3F +#define UMAC_REO_R0_GXI_GXI_ERR_STATS___S 0 + +#define UMAC_REO_R0_GXI_GXI_DEFAULT_CONTROL (0x00A38670) +#define UMAC_REO_R0_GXI_GXI_DEFAULT_CONTROL___RWC QCSR_REG_RW +#define UMAC_REO_R0_GXI_GXI_DEFAULT_CONTROL___POR 0x00000000 +#define UMAC_REO_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READ_DATA___POR 0x00 +#define UMAC_REO_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITE_DATA___POR 0x00 +#define UMAC_REO_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READS___POR 0x00 +#define UMAC_REO_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITES___POR 0x00 +#define UMAC_REO_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READ_DATA___M 0xFF000000 +#define UMAC_REO_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READ_DATA___S 24 +#define UMAC_REO_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITE_DATA___M 0x00FF0000 +#define UMAC_REO_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITE_DATA___S 16 +#define UMAC_REO_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READS___M 0x00003F00 +#define UMAC_REO_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READS___S 8 +#define UMAC_REO_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITES___M 0x0000003F +#define UMAC_REO_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITES___S 0 +#define UMAC_REO_R0_GXI_GXI_DEFAULT_CONTROL___M 0xFFFF3F3F +#define UMAC_REO_R0_GXI_GXI_DEFAULT_CONTROL___S 0 + +#define UMAC_REO_R0_GXI_GXI_REDUCED_CONTROL (0x00A38674) +#define UMAC_REO_R0_GXI_GXI_REDUCED_CONTROL___RWC QCSR_REG_RW +#define UMAC_REO_R0_GXI_GXI_REDUCED_CONTROL___POR 0x00000000 +#define UMAC_REO_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READ_DATA___POR 0x00 +#define UMAC_REO_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITE_DATA___POR 0x00 +#define UMAC_REO_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READS___POR 0x00 +#define UMAC_REO_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITES___POR 0x00 +#define UMAC_REO_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READ_DATA___M 0xFF000000 +#define UMAC_REO_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READ_DATA___S 24 +#define UMAC_REO_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITE_DATA___M 0x00FF0000 +#define UMAC_REO_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITE_DATA___S 16 +#define UMAC_REO_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READS___M 0x00003F00 +#define UMAC_REO_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READS___S 8 +#define UMAC_REO_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITES___M 0x0000003F +#define UMAC_REO_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITES___S 0 +#define UMAC_REO_R0_GXI_GXI_REDUCED_CONTROL___M 0xFFFF3F3F +#define UMAC_REO_R0_GXI_GXI_REDUCED_CONTROL___S 0 + +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL (0x00A38678) +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL___RWC QCSR_REG_RW +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL___POR 0x00240000 +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_RD_FLUSH___POR 0x0 +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_WR_FLUSH___POR 0x0 +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_DISABLE_WR_PREFIL___POR 0x0 +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_WR_BOUNDARY_SPLIT___POR 0x0 +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_RD_BOUNDARY_SPLIT___POR 0x0 +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_BURST_SIZE___POR 0x2 +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_READ_BURST_SIZE___POR 0x2 +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_READ_ISSUE_THRESHOLD___POR 0x00 +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_PREFETCH_THRESHOLD___POR 0x00 +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_CLEAR_STATS___POR 0x0 +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_RD_FLUSH___M 0x08000000 +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_RD_FLUSH___S 27 +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_WR_FLUSH___M 0x04000000 +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_WR_FLUSH___S 26 +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_DISABLE_WR_PREFIL___M 0x02000000 +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_DISABLE_WR_PREFIL___S 25 +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_WR_BOUNDARY_SPLIT___M 0x01000000 +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_WR_BOUNDARY_SPLIT___S 24 +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_RD_BOUNDARY_SPLIT___M 0x00800000 +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_RD_BOUNDARY_SPLIT___S 23 +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_BURST_SIZE___M 0x00700000 +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_BURST_SIZE___S 20 +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_READ_BURST_SIZE___M 0x000E0000 +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_READ_BURST_SIZE___S 17 +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_READ_ISSUE_THRESHOLD___M 0x0001FE00 +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_READ_ISSUE_THRESHOLD___S 9 +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_PREFETCH_THRESHOLD___M 0x000001FE +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_PREFETCH_THRESHOLD___S 1 +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_CLEAR_STATS___M 0x00000001 +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL__GXI_CLEAR_STATS___S 0 +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL___M 0x0FFFFFFF +#define UMAC_REO_R0_GXI_GXI_MISC_CONTROL___S 0 + +#define UMAC_REO_R0_GXI_GXI_WDOG_CONTROL (0x00A3867C) +#define UMAC_REO_R0_GXI_GXI_WDOG_CONTROL___RWC QCSR_REG_RW +#define UMAC_REO_R0_GXI_GXI_WDOG_CONTROL___POR 0x00FF0000 +#define UMAC_REO_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_LIMIT___POR 0x00FF +#define UMAC_REO_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_DISABLE___POR 0x0 +#define UMAC_REO_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_LIMIT___M 0xFFFF0000 +#define UMAC_REO_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_LIMIT___S 16 +#define UMAC_REO_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_DISABLE___M 0x00000001 +#define UMAC_REO_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_DISABLE___S 0 +#define UMAC_REO_R0_GXI_GXI_WDOG_CONTROL___M 0xFFFF0001 +#define UMAC_REO_R0_GXI_GXI_WDOG_CONTROL___S 0 + +#define UMAC_REO_R0_GXI_GXI_WDOG_STATUS (0x00A38680) +#define UMAC_REO_R0_GXI_GXI_WDOG_STATUS___RWC QCSR_REG_RO +#define UMAC_REO_R0_GXI_GXI_WDOG_STATUS___POR 0x00000000 +#define UMAC_REO_R0_GXI_GXI_WDOG_STATUS__GXI_WDOG_STATUS___POR 0x0000 +#define UMAC_REO_R0_GXI_GXI_WDOG_STATUS__GXI_WDOG_STATUS___M 0x0000FFFF +#define UMAC_REO_R0_GXI_GXI_WDOG_STATUS__GXI_WDOG_STATUS___S 0 +#define UMAC_REO_R0_GXI_GXI_WDOG_STATUS___M 0x0000FFFF +#define UMAC_REO_R0_GXI_GXI_WDOG_STATUS___S 0 + +#define UMAC_REO_R0_GXI_GXI_IDLE_COUNTERS (0x00A38684) +#define UMAC_REO_R0_GXI_GXI_IDLE_COUNTERS___RWC QCSR_REG_RO +#define UMAC_REO_R0_GXI_GXI_IDLE_COUNTERS___POR 0x00000000 +#define UMAC_REO_R0_GXI_GXI_IDLE_COUNTERS__GXI_READ_IDLE_CNT___POR 0x0000 +#define UMAC_REO_R0_GXI_GXI_IDLE_COUNTERS__GXI_WRITE_IDLE_CNT___POR 0x0000 +#define UMAC_REO_R0_GXI_GXI_IDLE_COUNTERS__GXI_READ_IDLE_CNT___M 0xFFFF0000 +#define UMAC_REO_R0_GXI_GXI_IDLE_COUNTERS__GXI_READ_IDLE_CNT___S 16 +#define UMAC_REO_R0_GXI_GXI_IDLE_COUNTERS__GXI_WRITE_IDLE_CNT___M 0x0000FFFF +#define UMAC_REO_R0_GXI_GXI_IDLE_COUNTERS__GXI_WRITE_IDLE_CNT___S 0 +#define UMAC_REO_R0_GXI_GXI_IDLE_COUNTERS___M 0xFFFFFFFF +#define UMAC_REO_R0_GXI_GXI_IDLE_COUNTERS___S 0 + +#define UMAC_REO_R0_GXI_GXI_RD_LATENCY_CTRL (0x00A38688) +#define UMAC_REO_R0_GXI_GXI_RD_LATENCY_CTRL___RWC QCSR_REG_RW +#define UMAC_REO_R0_GXI_GXI_RD_LATENCY_CTRL___POR 0x00000000 +#define UMAC_REO_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_RANGE___POR 0x0 +#define UMAC_REO_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_EN___POR 0x0 +#define UMAC_REO_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_MIN___POR 0x0000 +#define UMAC_REO_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_RANGE___M 0x000E0000 +#define UMAC_REO_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_RANGE___S 17 +#define UMAC_REO_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_EN___M 0x00010000 +#define UMAC_REO_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_EN___S 16 +#define UMAC_REO_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_MIN___M 0x0000FFFF +#define UMAC_REO_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_MIN___S 0 +#define UMAC_REO_R0_GXI_GXI_RD_LATENCY_CTRL___M 0x000FFFFF +#define UMAC_REO_R0_GXI_GXI_RD_LATENCY_CTRL___S 0 + +#define UMAC_REO_R0_GXI_GXI_WR_LATENCY_CTRL (0x00A3868C) +#define UMAC_REO_R0_GXI_GXI_WR_LATENCY_CTRL___RWC QCSR_REG_RW +#define UMAC_REO_R0_GXI_GXI_WR_LATENCY_CTRL___POR 0x00000000 +#define UMAC_REO_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_RANGE___POR 0x0 +#define UMAC_REO_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_EN___POR 0x0 +#define UMAC_REO_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_MIN___POR 0x0000 +#define UMAC_REO_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_RANGE___M 0x000E0000 +#define UMAC_REO_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_RANGE___S 17 +#define UMAC_REO_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_EN___M 0x00010000 +#define UMAC_REO_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_EN___S 16 +#define UMAC_REO_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_MIN___M 0x0000FFFF +#define UMAC_REO_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_MIN___S 0 +#define UMAC_REO_R0_GXI_GXI_WR_LATENCY_CTRL___M 0x000FFFFF +#define UMAC_REO_R0_GXI_GXI_WR_LATENCY_CTRL___S 0 + +#define UMAC_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0 (0x00A38690) +#define UMAC_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___RWC QCSR_REG_RW +#define UMAC_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___POR 0x00000000 +#define UMAC_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0__VALUE___POR 0x00000000 +#define UMAC_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0__VALUE___M 0xFFFFFFFF +#define UMAC_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0__VALUE___S 0 +#define UMAC_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___M 0xFFFFFFFF +#define UMAC_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___S 0 + +#define UMAC_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1 (0x00A38694) +#define UMAC_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___RWC QCSR_REG_RW +#define UMAC_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___POR 0x00000000 +#define UMAC_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1__VALUE___POR 0x00000000 +#define UMAC_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1__VALUE___M 0xFFFFFFFF +#define UMAC_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1__VALUE___S 0 +#define UMAC_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___M 0xFFFFFFFF +#define UMAC_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___S 0 + +#define UMAC_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0 (0x00A38698) +#define UMAC_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___RWC QCSR_REG_RW +#define UMAC_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___POR 0x00000000 +#define UMAC_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0__VALUE___POR 0x00000000 +#define UMAC_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0__VALUE___M 0xFFFFFFFF +#define UMAC_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0__VALUE___S 0 +#define UMAC_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___M 0xFFFFFFFF +#define UMAC_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___S 0 + +#define UMAC_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1 (0x00A3869C) +#define UMAC_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___RWC QCSR_REG_RW +#define UMAC_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___POR 0x00000000 +#define UMAC_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1__VALUE___POR 0x00000000 +#define UMAC_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1__VALUE___M 0xFFFFFFFF +#define UMAC_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1__VALUE___S 0 +#define UMAC_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___M 0xFFFFFFFF +#define UMAC_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___S 0 + +#define UMAC_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL (0x00A386A0) +#define UMAC_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL___RWC QCSR_REG_RW +#define UMAC_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL___POR 0x00000000 +#define UMAC_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_EN___POR 0x0 +#define UMAC_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_CNT___POR 0x00 +#define UMAC_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_EN___POR 0x0 +#define UMAC_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_CNT___POR 0x00 +#define UMAC_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_EN___M 0x00008000 +#define UMAC_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_EN___S 15 +#define UMAC_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_CNT___M 0x00001F00 +#define UMAC_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_CNT___S 8 +#define UMAC_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_EN___M 0x00000080 +#define UMAC_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_EN___S 7 +#define UMAC_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_CNT___M 0x0000001F +#define UMAC_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_CNT___S 0 +#define UMAC_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL___M 0x00009F9F +#define UMAC_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL___S 0 + +#define UMAC_REO_R0_CACHE_CTL_CONFIG (0x00A386A4) +#define UMAC_REO_R0_CACHE_CTL_CONFIG___RWC QCSR_REG_RW +#define UMAC_REO_R0_CACHE_CTL_CONFIG___POR 0x008608FF +#define UMAC_REO_R0_CACHE_CTL_CONFIG__DESC_TYPE_SWAP___POR 0x00 +#define UMAC_REO_R0_CACHE_CTL_CONFIG__ENABLE_LEGACY_SWAP___POR 0x1 +#define UMAC_REO_R0_CACHE_CTL_CONFIG__WRITE_STRUCT_SWAP___POR 0x0 +#define UMAC_REO_R0_CACHE_CTL_CONFIG__READ_STRUCT_SWAP___POR 0x0 +#define UMAC_REO_R0_CACHE_CTL_CONFIG__WRITE_SECURITY___POR 0x0 +#define UMAC_REO_R0_CACHE_CTL_CONFIG__READ_SECURITY___POR 0x0 +#define UMAC_REO_R0_CACHE_CTL_CONFIG__BG_FLUSH_POST_WRITE___POR 0x1 +#define UMAC_REO_R0_CACHE_CTL_CONFIG__CLIENT_FLUSH_POST_WRITE___POR 0x1 +#define UMAC_REO_R0_CACHE_CTL_CONFIG__CACHE_EMPTY_THRESHOLD___POR 0x04 +#define UMAC_REO_R0_CACHE_CTL_CONFIG__CACHE_LINE_USE_NUM___POR 0x0FF +#define UMAC_REO_R0_CACHE_CTL_CONFIG__DESC_TYPE_SWAP___M 0xFF000000 +#define UMAC_REO_R0_CACHE_CTL_CONFIG__DESC_TYPE_SWAP___S 24 +#define UMAC_REO_R0_CACHE_CTL_CONFIG__ENABLE_LEGACY_SWAP___M 0x00800000 +#define UMAC_REO_R0_CACHE_CTL_CONFIG__ENABLE_LEGACY_SWAP___S 23 +#define UMAC_REO_R0_CACHE_CTL_CONFIG__WRITE_STRUCT_SWAP___M 0x00400000 +#define UMAC_REO_R0_CACHE_CTL_CONFIG__WRITE_STRUCT_SWAP___S 22 +#define UMAC_REO_R0_CACHE_CTL_CONFIG__READ_STRUCT_SWAP___M 0x00200000 +#define UMAC_REO_R0_CACHE_CTL_CONFIG__READ_STRUCT_SWAP___S 21 +#define UMAC_REO_R0_CACHE_CTL_CONFIG__WRITE_SECURITY___M 0x00100000 +#define UMAC_REO_R0_CACHE_CTL_CONFIG__WRITE_SECURITY___S 20 +#define UMAC_REO_R0_CACHE_CTL_CONFIG__READ_SECURITY___M 0x00080000 +#define UMAC_REO_R0_CACHE_CTL_CONFIG__READ_SECURITY___S 19 +#define UMAC_REO_R0_CACHE_CTL_CONFIG__BG_FLUSH_POST_WRITE___M 0x00040000 +#define UMAC_REO_R0_CACHE_CTL_CONFIG__BG_FLUSH_POST_WRITE___S 18 +#define UMAC_REO_R0_CACHE_CTL_CONFIG__CLIENT_FLUSH_POST_WRITE___M 0x00020000 +#define UMAC_REO_R0_CACHE_CTL_CONFIG__CLIENT_FLUSH_POST_WRITE___S 17 +#define UMAC_REO_R0_CACHE_CTL_CONFIG__CACHE_EMPTY_THRESHOLD___M 0x0001FE00 +#define UMAC_REO_R0_CACHE_CTL_CONFIG__CACHE_EMPTY_THRESHOLD___S 9 +#define UMAC_REO_R0_CACHE_CTL_CONFIG__CACHE_LINE_USE_NUM___M 0x000001FF +#define UMAC_REO_R0_CACHE_CTL_CONFIG__CACHE_LINE_USE_NUM___S 0 +#define UMAC_REO_R0_CACHE_CTL_CONFIG___M 0xFFFFFFFF +#define UMAC_REO_R0_CACHE_CTL_CONFIG___S 0 + +#define UMAC_REO_R0_CACHE_CTL_CONTROL (0x00A386A8) +#define UMAC_REO_R0_CACHE_CTL_CONTROL___RWC QCSR_REG_RW +#define UMAC_REO_R0_CACHE_CTL_CONTROL___POR 0x00000000 +#define UMAC_REO_R0_CACHE_CTL_CONTROL__WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH___POR 0x0 +#define UMAC_REO_R0_CACHE_CTL_CONTROL__CACHE_RESET___POR 0x0 +#define UMAC_REO_R0_CACHE_CTL_CONTROL__WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH___M 0x00000002 +#define UMAC_REO_R0_CACHE_CTL_CONTROL__WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH___S 1 +#define UMAC_REO_R0_CACHE_CTL_CONTROL__CACHE_RESET___M 0x00000001 +#define UMAC_REO_R0_CACHE_CTL_CONTROL__CACHE_RESET___S 0 +#define UMAC_REO_R0_CACHE_CTL_CONTROL___M 0x00000003 +#define UMAC_REO_R0_CACHE_CTL_CONTROL___S 0 + +#define UMAC_REO_R0_CACHE_CTL_CONFIG_SET (0x00A386AC) +#define UMAC_REO_R0_CACHE_CTL_CONFIG_SET___RWC QCSR_REG_RW +#define UMAC_REO_R0_CACHE_CTL_CONFIG_SET___POR 0x01F808FF +#define UMAC_REO_R0_CACHE_CTL_CONFIG_SET__DESC_TYPE_BITMAP___POR 0xFC +#define UMAC_REO_R0_CACHE_CTL_CONFIG_SET__CACHE_EMPTY_THRESHOLD_SET2___POR 0x04 +#define UMAC_REO_R0_CACHE_CTL_CONFIG_SET__CACHE_LINE_USE_NUM_SET2___POR 0x0FF +#define UMAC_REO_R0_CACHE_CTL_CONFIG_SET__DESC_TYPE_BITMAP___M 0x01FE0000 +#define UMAC_REO_R0_CACHE_CTL_CONFIG_SET__DESC_TYPE_BITMAP___S 17 +#define UMAC_REO_R0_CACHE_CTL_CONFIG_SET__CACHE_EMPTY_THRESHOLD_SET2___M 0x0001FE00 +#define UMAC_REO_R0_CACHE_CTL_CONFIG_SET__CACHE_EMPTY_THRESHOLD_SET2___S 9 +#define UMAC_REO_R0_CACHE_CTL_CONFIG_SET__CACHE_LINE_USE_NUM_SET2___M 0x000001FF +#define UMAC_REO_R0_CACHE_CTL_CONFIG_SET__CACHE_LINE_USE_NUM_SET2___S 0 +#define UMAC_REO_R0_CACHE_CTL_CONFIG_SET___M 0x01FFFFFF +#define UMAC_REO_R0_CACHE_CTL_CONFIG_SET___S 0 + +#define UMAC_REO_R0_CACHE_CTL_SET_SIZE (0x00A386B0) +#define UMAC_REO_R0_CACHE_CTL_SET_SIZE___RWC QCSR_REG_RW +#define UMAC_REO_R0_CACHE_CTL_SET_SIZE___POR 0x000000F0 +#define UMAC_REO_R0_CACHE_CTL_SET_SIZE__SET1_SIZE___POR 0x0F0 +#define UMAC_REO_R0_CACHE_CTL_SET_SIZE__SET1_SIZE___M 0x000001FF +#define UMAC_REO_R0_CACHE_CTL_SET_SIZE__SET1_SIZE___S 0 +#define UMAC_REO_R0_CACHE_CTL_SET_SIZE___M 0x000001FF +#define UMAC_REO_R0_CACHE_CTL_SET_SIZE___S 0 + +#define UMAC_REO_R0_CLK_GATE_CTRL (0x00A386B4) +#define UMAC_REO_R0_CLK_GATE_CTRL___RWC QCSR_REG_RW +#define UMAC_REO_R0_CLK_GATE_CTRL___POR 0x00000400 +#define UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_7___POR 0x0 +#define UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_6___POR 0x0 +#define UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_5___POR 0x0 +#define UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_4___POR 0x0 +#define UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_3___POR 0x0 +#define UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_2___POR 0x0 +#define UMAC_REO_R0_CLK_GATE_CTRL__REO_CLKGATE_DISABLE_SRNG_P___POR 0x0 +#define UMAC_REO_R0_CLK_GATE_CTRL__REO_CLKGATE_DISABLE_SRNG_C___POR 0x0 +#define UMAC_REO_R0_CLK_GATE_CTRL__CLOCK_ENS_EXTEND___POR 0x1 +#define UMAC_REO_R0_CLK_GATE_CTRL__REO_CLKGATE_DISABLE___POR 0x000 +#define UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_7___M 0x00040000 +#define UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_7___S 18 +#define UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_6___M 0x00020000 +#define UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_6___S 17 +#define UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_5___M 0x00010000 +#define UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_5___S 16 +#define UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_4___M 0x00008000 +#define UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_4___S 15 +#define UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_3___M 0x00004000 +#define UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_3___S 14 +#define UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_2___M 0x00002000 +#define UMAC_REO_R0_CLK_GATE_CTRL__RESERVE_2___S 13 +#define UMAC_REO_R0_CLK_GATE_CTRL__REO_CLKGATE_DISABLE_SRNG_P___M 0x00001000 +#define UMAC_REO_R0_CLK_GATE_CTRL__REO_CLKGATE_DISABLE_SRNG_P___S 12 +#define UMAC_REO_R0_CLK_GATE_CTRL__REO_CLKGATE_DISABLE_SRNG_C___M 0x00000800 +#define UMAC_REO_R0_CLK_GATE_CTRL__REO_CLKGATE_DISABLE_SRNG_C___S 11 +#define UMAC_REO_R0_CLK_GATE_CTRL__CLOCK_ENS_EXTEND___M 0x00000400 +#define UMAC_REO_R0_CLK_GATE_CTRL__CLOCK_ENS_EXTEND___S 10 +#define UMAC_REO_R0_CLK_GATE_CTRL__REO_CLKGATE_DISABLE___M 0x000003FF +#define UMAC_REO_R0_CLK_GATE_CTRL__REO_CLKGATE_DISABLE___S 0 +#define UMAC_REO_R0_CLK_GATE_CTRL___M 0x0007FFFF +#define UMAC_REO_R0_CLK_GATE_CTRL___S 0 + +#define UMAC_REO_R0_EVENTMASK_IX_0 (0x00A386B8) +#define UMAC_REO_R0_EVENTMASK_IX_0___RWC QCSR_REG_RW +#define UMAC_REO_R0_EVENTMASK_IX_0___POR 0x00000000 +#define UMAC_REO_R0_EVENTMASK_IX_0__MASK___POR 0x00000000 +#define UMAC_REO_R0_EVENTMASK_IX_0__MASK___M 0xFFFFFFFF +#define UMAC_REO_R0_EVENTMASK_IX_0__MASK___S 0 +#define UMAC_REO_R0_EVENTMASK_IX_0___M 0xFFFFFFFF +#define UMAC_REO_R0_EVENTMASK_IX_0___S 0 + +#define UMAC_REO_R0_EVENTMASK_IX_1 (0x00A386BC) +#define UMAC_REO_R0_EVENTMASK_IX_1___RWC QCSR_REG_RW +#define UMAC_REO_R0_EVENTMASK_IX_1___POR 0x00000000 +#define UMAC_REO_R0_EVENTMASK_IX_1__MASK___POR 0x00000000 +#define UMAC_REO_R0_EVENTMASK_IX_1__MASK___M 0xFFFFFFFF +#define UMAC_REO_R0_EVENTMASK_IX_1__MASK___S 0 +#define UMAC_REO_R0_EVENTMASK_IX_1___M 0xFFFFFFFF +#define UMAC_REO_R0_EVENTMASK_IX_1___S 0 + +#define UMAC_REO_R0_EVENTMASK_IX_2 (0x00A386C0) +#define UMAC_REO_R0_EVENTMASK_IX_2___RWC QCSR_REG_RW +#define UMAC_REO_R0_EVENTMASK_IX_2___POR 0x00000000 +#define UMAC_REO_R0_EVENTMASK_IX_2__MASK___POR 0x00000000 +#define UMAC_REO_R0_EVENTMASK_IX_2__MASK___M 0xFFFFFFFF +#define UMAC_REO_R0_EVENTMASK_IX_2__MASK___S 0 +#define UMAC_REO_R0_EVENTMASK_IX_2___M 0xFFFFFFFF +#define UMAC_REO_R0_EVENTMASK_IX_2___S 0 + +#define UMAC_REO_R0_EVENTMASK_IX_3 (0x00A386C4) +#define UMAC_REO_R0_EVENTMASK_IX_3___RWC QCSR_REG_RW +#define UMAC_REO_R0_EVENTMASK_IX_3___POR 0x00000000 +#define UMAC_REO_R0_EVENTMASK_IX_3__MASK___POR 0x00000000 +#define UMAC_REO_R0_EVENTMASK_IX_3__MASK___M 0xFFFFFFFF +#define UMAC_REO_R0_EVENTMASK_IX_3__MASK___S 0 +#define UMAC_REO_R0_EVENTMASK_IX_3___M 0xFFFFFFFF +#define UMAC_REO_R0_EVENTMASK_IX_3___S 0 + +#define UMAC_REO_R1_MISC_DEBUG_CTRL (0x00A3A000) +#define UMAC_REO_R1_MISC_DEBUG_CTRL___RWC QCSR_REG_RW +#define UMAC_REO_R1_MISC_DEBUG_CTRL___POR 0x100771F0 +#define UMAC_REO_R1_MISC_DEBUG_CTRL__DISABLE_SW_EXCEPTION___POR 0x0 +#define UMAC_REO_R1_MISC_DEBUG_CTRL__IDLE_REQ___POR 0x0 +#define UMAC_REO_R1_MISC_DEBUG_CTRL__CMD_FIFO_RESUME_THRESH___POR 0x100 +#define UMAC_REO_R1_MISC_DEBUG_CTRL__CMD_FIFO_STOP_THRESH___POR 0x1DC +#define UMAC_REO_R1_MISC_DEBUG_CTRL__CMD_FIFO_START_THRESH___POR 0x1F0 +#define UMAC_REO_R1_MISC_DEBUG_CTRL__DISABLE_SW_EXCEPTION___M 0x80000000 +#define UMAC_REO_R1_MISC_DEBUG_CTRL__DISABLE_SW_EXCEPTION___S 31 +#define UMAC_REO_R1_MISC_DEBUG_CTRL__IDLE_REQ___M 0x40000000 +#define UMAC_REO_R1_MISC_DEBUG_CTRL__IDLE_REQ___S 30 +#define UMAC_REO_R1_MISC_DEBUG_CTRL__CMD_FIFO_RESUME_THRESH___M 0x3FF00000 +#define UMAC_REO_R1_MISC_DEBUG_CTRL__CMD_FIFO_RESUME_THRESH___S 20 +#define UMAC_REO_R1_MISC_DEBUG_CTRL__CMD_FIFO_STOP_THRESH___M 0x000FFC00 +#define UMAC_REO_R1_MISC_DEBUG_CTRL__CMD_FIFO_STOP_THRESH___S 10 +#define UMAC_REO_R1_MISC_DEBUG_CTRL__CMD_FIFO_START_THRESH___M 0x000003FF +#define UMAC_REO_R1_MISC_DEBUG_CTRL__CMD_FIFO_START_THRESH___S 0 +#define UMAC_REO_R1_MISC_DEBUG_CTRL___M 0xFFFFFFFF +#define UMAC_REO_R1_MISC_DEBUG_CTRL___S 0 + +#define UMAC_REO_R1_MISC_PERF_DEBUG_CTRL (0x00A3A004) +#define UMAC_REO_R1_MISC_PERF_DEBUG_CTRL___RWC QCSR_REG_RW +#define UMAC_REO_R1_MISC_PERF_DEBUG_CTRL___POR 0x003FF03F +#define UMAC_REO_R1_MISC_PERF_DEBUG_CTRL__RELEASE_RING_ACCUM_DELAY___POR 0x3FF +#define UMAC_REO_R1_MISC_PERF_DEBUG_CTRL__PROD_RING_ACCUM_DELAY___POR 0x03F +#define UMAC_REO_R1_MISC_PERF_DEBUG_CTRL__RELEASE_RING_ACCUM_DELAY___M 0x00FFF000 +#define UMAC_REO_R1_MISC_PERF_DEBUG_CTRL__RELEASE_RING_ACCUM_DELAY___S 12 +#define UMAC_REO_R1_MISC_PERF_DEBUG_CTRL__PROD_RING_ACCUM_DELAY___M 0x00000FFF +#define UMAC_REO_R1_MISC_PERF_DEBUG_CTRL__PROD_RING_ACCUM_DELAY___S 0 +#define UMAC_REO_R1_MISC_PERF_DEBUG_CTRL___M 0x00FFFFFF +#define UMAC_REO_R1_MISC_PERF_DEBUG_CTRL___S 0 + +#define UMAC_REO_R1_CACHE_CTL_DEBUG_CONTROL (0x00A3A008) +#define UMAC_REO_R1_CACHE_CTL_DEBUG_CONTROL___RWC QCSR_REG_RW +#define UMAC_REO_R1_CACHE_CTL_DEBUG_CONTROL___POR 0x00000800 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_CONTROL__CACHE_CMD_HOLD_ACK___POR 0x1 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_CONTROL__CACHE_CMD_HOLD___POR 0x0 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_CONTROL__TAG_TABLE_UPDATE___POR 0x0 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_CONTROL__TAG_TABLE_SEL___POR 0x000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_CONTROL__CACHE_CMD_HOLD_ACK___M 0x00000800 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_CONTROL__CACHE_CMD_HOLD_ACK___S 11 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_CONTROL__CACHE_CMD_HOLD___M 0x00000400 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_CONTROL__CACHE_CMD_HOLD___S 10 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_CONTROL__TAG_TABLE_UPDATE___M 0x00000200 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_CONTROL__TAG_TABLE_UPDATE___S 9 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_CONTROL__TAG_TABLE_SEL___M 0x000001FF +#define UMAC_REO_R1_CACHE_CTL_DEBUG_CONTROL__TAG_TABLE_SEL___S 0 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_CONTROL___M 0x00000FFF +#define UMAC_REO_R1_CACHE_CTL_DEBUG_CONTROL___S 0 + +#define UMAC_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT (0x00A3A00C) +#define UMAC_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT___RWC QCSR_REG_RW +#define UMAC_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT___POR 0x00000000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT__CACHE_HIT_COUNT___POR 0x00000000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT__CACHE_HIT_COUNT___M 0xFFFFFFFF +#define UMAC_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT__CACHE_HIT_COUNT___S 0 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT___M 0xFFFFFFFF +#define UMAC_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT___S 0 + +#define UMAC_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT (0x00A3A010) +#define UMAC_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT___RWC QCSR_REG_RW +#define UMAC_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT___POR 0x00000000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT__CACHE_MISS_COUNT___POR 0x000000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT__CACHE_MISS_COUNT___M 0x00FFFFFF +#define UMAC_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT__CACHE_MISS_COUNT___S 0 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT___M 0x00FFFFFF +#define UMAC_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT___S 0 + +#define UMAC_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW (0x00A3A014) +#define UMAC_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW___RWC QCSR_REG_RW +#define UMAC_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW___POR 0x00000000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW__OVERWRITE___POR 0x00000000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW__OVERWRITE___M 0xFFFFFFFF +#define UMAC_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW__OVERWRITE___S 0 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW___M 0xFFFFFFFF +#define UMAC_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW___S 0 + +#define UMAC_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH (0x00A3A018) +#define UMAC_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH___RWC QCSR_REG_RW +#define UMAC_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH___POR 0x00000000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH__OVERWRITE___POR 0x00000000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH__OVERWRITE___M 0xFFFFFFFF +#define UMAC_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH__OVERWRITE___S 0 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH___M 0xFFFFFFFF +#define UMAC_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH___S 0 + +#define UMAC_REO_R1_CACHE_CTL_DEBUG_STM (0x00A3A01C) +#define UMAC_REO_R1_CACHE_CTL_DEBUG_STM___RWC QCSR_REG_RO +#define UMAC_REO_R1_CACHE_CTL_DEBUG_STM___POR 0x00000000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_STM__STATE___POR 0x0000000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_STM__STATE___M 0x01FFFFFF +#define UMAC_REO_R1_CACHE_CTL_DEBUG_STM__STATE___S 0 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_STM___M 0x01FFFFFF +#define UMAC_REO_R1_CACHE_CTL_DEBUG_STM___S 0 + +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST (0x00A3A020) +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST___RWC QCSR_REG_RO +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST___POR 0x00000000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST__MRU_FLAG___POR 0x000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST__LRU_FLAG___POR 0x000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST__MRU_FLAG___M 0x0007FC00 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST__MRU_FLAG___S 10 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST__LRU_FLAG___M 0x000003FF +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST__LRU_FLAG___S 0 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST___M 0x0007FFFF +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST___S 0 + +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1 (0x00A3A024) +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1___RWC QCSR_REG_RO +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1___POR 0x00000000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1__HEAD_FLAG___POR 0x000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1__TAIL_FLAG___POR 0x000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1__HEAD_FLAG___M 0x0007FC00 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1__HEAD_FLAG___S 10 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1__TAIL_FLAG___M 0x000003FF +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1__TAIL_FLAG___S 0 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1___M 0x0007FFFF +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1___S 0 + +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2 (0x00A3A028) +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2___RWC QCSR_REG_RO +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2___POR 0x00000000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2__MRU_FLAG_SET2___POR 0x000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2__LRU_FLAG_SET2___POR 0x000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2__MRU_FLAG_SET2___M 0x0007FC00 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2__MRU_FLAG_SET2___S 10 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2__LRU_FLAG_SET2___M 0x000003FF +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2__LRU_FLAG_SET2___S 0 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2___M 0x0007FFFF +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2___S 0 + +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3 (0x00A3A02C) +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3___RWC QCSR_REG_RO +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3___POR 0x00000000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3__HEAD_FLAG_SET2___POR 0x000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3__TAIL_FLAG_SET2___POR 0x000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3__HEAD_FLAG_SET2___M 0x0007FC00 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3__HEAD_FLAG_SET2___S 10 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3__TAIL_FLAG_SET2___M 0x000003FF +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3__TAIL_FLAG_SET2___S 0 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3___M 0x0007FFFF +#define UMAC_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3___S 0 + +#define UMAC_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW (0x00A3A030) +#define UMAC_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW___RWC QCSR_REG_RO +#define UMAC_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW___POR 0x00000000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW__VALUE___POR 0x00000000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW__VALUE___M 0xFFFFFFFF +#define UMAC_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW__VALUE___S 0 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW___M 0xFFFFFFFF +#define UMAC_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW___S 0 + +#define UMAC_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH (0x00A3A034) +#define UMAC_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH___RWC QCSR_REG_RO +#define UMAC_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH___POR 0x00000000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH__VALUE___POR 0x00000000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH__VALUE___M 0xFFFFFFFF +#define UMAC_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH__VALUE___S 0 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH___M 0xFFFFFFFF +#define UMAC_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH___S 0 + +#define UMAC_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER (0x00A3A038) +#define UMAC_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER___RWC QCSR_REG_RO +#define UMAC_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER___POR 0x00000000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER__SET2___POR 0x000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER__SET1___POR 0x000 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER__SET2___M 0x000FFC00 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER__SET2___S 10 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER__SET1___M 0x000003FF +#define UMAC_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER__SET1___S 0 +#define UMAC_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER___M 0x000FFFFF +#define UMAC_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER___S 0 + +#define UMAC_REO_R1_CACHE_CTL_END_OF_TEST_CHECK (0x00A3A03C) +#define UMAC_REO_R1_CACHE_CTL_END_OF_TEST_CHECK___RWC QCSR_REG_RW +#define UMAC_REO_R1_CACHE_CTL_END_OF_TEST_CHECK___POR 0x00000000 +#define UMAC_REO_R1_CACHE_CTL_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0 +#define UMAC_REO_R1_CACHE_CTL_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001 +#define UMAC_REO_R1_CACHE_CTL_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S 0 +#define UMAC_REO_R1_CACHE_CTL_END_OF_TEST_CHECK___M 0x00000001 +#define UMAC_REO_R1_CACHE_CTL_END_OF_TEST_CHECK___S 0 + +#define UMAC_REO_R1_END_OF_TEST_CHECK (0x00A3A040) +#define UMAC_REO_R1_END_OF_TEST_CHECK___RWC QCSR_REG_RW +#define UMAC_REO_R1_END_OF_TEST_CHECK___POR 0x00000000 +#define UMAC_REO_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0 +#define UMAC_REO_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001 +#define UMAC_REO_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S 0 +#define UMAC_REO_R1_END_OF_TEST_CHECK___M 0x00000001 +#define UMAC_REO_R1_END_OF_TEST_CHECK___S 0 + +#define UMAC_REO_R1_SM_ALL_IDLE (0x00A3A044) +#define UMAC_REO_R1_SM_ALL_IDLE___RWC QCSR_REG_RO +#define UMAC_REO_R1_SM_ALL_IDLE___POR 0x00000001 +#define UMAC_REO_R1_SM_ALL_IDLE__REO_ENTRANCE_RINGS_NOT_EMPTY___POR 0x0 +#define UMAC_REO_R1_SM_ALL_IDLE__REO_IN_IDLE___POR 0x0 +#define UMAC_REO_R1_SM_ALL_IDLE__ALL_STATES_IN_IDLE___POR 0x1 +#define UMAC_REO_R1_SM_ALL_IDLE__REO_ENTRANCE_RINGS_NOT_EMPTY___M 0x00000004 +#define UMAC_REO_R1_SM_ALL_IDLE__REO_ENTRANCE_RINGS_NOT_EMPTY___S 2 +#define UMAC_REO_R1_SM_ALL_IDLE__REO_IN_IDLE___M 0x00000002 +#define UMAC_REO_R1_SM_ALL_IDLE__REO_IN_IDLE___S 1 +#define UMAC_REO_R1_SM_ALL_IDLE__ALL_STATES_IN_IDLE___M 0x00000001 +#define UMAC_REO_R1_SM_ALL_IDLE__ALL_STATES_IN_IDLE___S 0 +#define UMAC_REO_R1_SM_ALL_IDLE___M 0x00000007 +#define UMAC_REO_R1_SM_ALL_IDLE___S 0 + +#define UMAC_REO_R1_TESTBUS_CTRL (0x00A3A048) +#define UMAC_REO_R1_TESTBUS_CTRL___RWC QCSR_REG_RW +#define UMAC_REO_R1_TESTBUS_CTRL___POR 0x00000000 +#define UMAC_REO_R1_TESTBUS_CTRL__TESTBUS_SELECT___POR 0x00 +#define UMAC_REO_R1_TESTBUS_CTRL__TESTBUS_SELECT___M 0x0000007F +#define UMAC_REO_R1_TESTBUS_CTRL__TESTBUS_SELECT___S 0 +#define UMAC_REO_R1_TESTBUS_CTRL___M 0x0000007F +#define UMAC_REO_R1_TESTBUS_CTRL___S 0 + +#define UMAC_REO_R1_TESTBUS_LOWER (0x00A3A04C) +#define UMAC_REO_R1_TESTBUS_LOWER___RWC QCSR_REG_RO +#define UMAC_REO_R1_TESTBUS_LOWER___POR 0x00000000 +#define UMAC_REO_R1_TESTBUS_LOWER__VALUE___POR 0x00000000 +#define UMAC_REO_R1_TESTBUS_LOWER__VALUE___M 0xFFFFFFFF +#define UMAC_REO_R1_TESTBUS_LOWER__VALUE___S 0 +#define UMAC_REO_R1_TESTBUS_LOWER___M 0xFFFFFFFF +#define UMAC_REO_R1_TESTBUS_LOWER___S 0 + +#define UMAC_REO_R1_TESTBUS_HIGHER (0x00A3A050) +#define UMAC_REO_R1_TESTBUS_HIGHER___RWC QCSR_REG_RO +#define UMAC_REO_R1_TESTBUS_HIGHER___POR 0x00000000 +#define UMAC_REO_R1_TESTBUS_HIGHER__VALUE___POR 0x00 +#define UMAC_REO_R1_TESTBUS_HIGHER__VALUE___M 0x000000FF +#define UMAC_REO_R1_TESTBUS_HIGHER__VALUE___S 0 +#define UMAC_REO_R1_TESTBUS_HIGHER___M 0x000000FF +#define UMAC_REO_R1_TESTBUS_HIGHER___S 0 + +#define UMAC_REO_R1_SM_STATES_IX_0 (0x00A3A054) +#define UMAC_REO_R1_SM_STATES_IX_0___RWC QCSR_REG_RO +#define UMAC_REO_R1_SM_STATES_IX_0___POR 0x00000000 +#define UMAC_REO_R1_SM_STATES_IX_0__SM_STATE___POR 0x00000000 +#define UMAC_REO_R1_SM_STATES_IX_0__SM_STATE___M 0xFFFFFFFF +#define UMAC_REO_R1_SM_STATES_IX_0__SM_STATE___S 0 +#define UMAC_REO_R1_SM_STATES_IX_0___M 0xFFFFFFFF +#define UMAC_REO_R1_SM_STATES_IX_0___S 0 + +#define UMAC_REO_R1_SM_STATES_IX_1 (0x00A3A058) +#define UMAC_REO_R1_SM_STATES_IX_1___RWC QCSR_REG_RO +#define UMAC_REO_R1_SM_STATES_IX_1___POR 0x00000000 +#define UMAC_REO_R1_SM_STATES_IX_1__SM_STATE___POR 0x00000000 +#define UMAC_REO_R1_SM_STATES_IX_1__SM_STATE___M 0xFFFFFFFF +#define UMAC_REO_R1_SM_STATES_IX_1__SM_STATE___S 0 +#define UMAC_REO_R1_SM_STATES_IX_1___M 0xFFFFFFFF +#define UMAC_REO_R1_SM_STATES_IX_1___S 0 + +#define UMAC_REO_R1_SM_STATES_IX_2 (0x00A3A05C) +#define UMAC_REO_R1_SM_STATES_IX_2___RWC QCSR_REG_RO +#define UMAC_REO_R1_SM_STATES_IX_2___POR 0x00000000 +#define UMAC_REO_R1_SM_STATES_IX_2__SM_STATE___POR 0x00000000 +#define UMAC_REO_R1_SM_STATES_IX_2__SM_STATE___M 0xFFFFFFFF +#define UMAC_REO_R1_SM_STATES_IX_2__SM_STATE___S 0 +#define UMAC_REO_R1_SM_STATES_IX_2___M 0xFFFFFFFF +#define UMAC_REO_R1_SM_STATES_IX_2___S 0 + +#define UMAC_REO_R1_SM_STATES_IX_3 (0x00A3A060) +#define UMAC_REO_R1_SM_STATES_IX_3___RWC QCSR_REG_RO +#define UMAC_REO_R1_SM_STATES_IX_3___POR 0x00000000 +#define UMAC_REO_R1_SM_STATES_IX_3__SM_STATE___POR 0x00000000 +#define UMAC_REO_R1_SM_STATES_IX_3__SM_STATE___M 0xFFFFFFFF +#define UMAC_REO_R1_SM_STATES_IX_3__SM_STATE___S 0 +#define UMAC_REO_R1_SM_STATES_IX_3___M 0xFFFFFFFF +#define UMAC_REO_R1_SM_STATES_IX_3___S 0 + +#define UMAC_REO_R1_SM_STATES_IX_4 (0x00A3A064) +#define UMAC_REO_R1_SM_STATES_IX_4___RWC QCSR_REG_RO +#define UMAC_REO_R1_SM_STATES_IX_4___POR 0x00000000 +#define UMAC_REO_R1_SM_STATES_IX_4__SM_STATE___POR 0x00000000 +#define UMAC_REO_R1_SM_STATES_IX_4__SM_STATE___M 0xFFFFFFFF +#define UMAC_REO_R1_SM_STATES_IX_4__SM_STATE___S 0 +#define UMAC_REO_R1_SM_STATES_IX_4___M 0xFFFFFFFF +#define UMAC_REO_R1_SM_STATES_IX_4___S 0 + +#define UMAC_REO_R1_SM_STATES_IX_5 (0x00A3A068) +#define UMAC_REO_R1_SM_STATES_IX_5___RWC QCSR_REG_RO +#define UMAC_REO_R1_SM_STATES_IX_5___POR 0x00000000 +#define UMAC_REO_R1_SM_STATES_IX_5__SM_STATE___POR 0x00000000 +#define UMAC_REO_R1_SM_STATES_IX_5__SM_STATE___M 0xFFFFFFFF +#define UMAC_REO_R1_SM_STATES_IX_5__SM_STATE___S 0 +#define UMAC_REO_R1_SM_STATES_IX_5___M 0xFFFFFFFF +#define UMAC_REO_R1_SM_STATES_IX_5___S 0 + +#define UMAC_REO_R1_SM_STATES_IX_6 (0x00A3A06C) +#define UMAC_REO_R1_SM_STATES_IX_6___RWC QCSR_REG_RO +#define UMAC_REO_R1_SM_STATES_IX_6___POR 0x00000000 +#define UMAC_REO_R1_SM_STATES_IX_6__SM_STATE___POR 0x00000000 +#define UMAC_REO_R1_SM_STATES_IX_6__SM_STATE___M 0xFFFFFFFF +#define UMAC_REO_R1_SM_STATES_IX_6__SM_STATE___S 0 +#define UMAC_REO_R1_SM_STATES_IX_6___M 0xFFFFFFFF +#define UMAC_REO_R1_SM_STATES_IX_6___S 0 + +#define UMAC_REO_R1_IDLE_STATES_IX_0 (0x00A3A070) +#define UMAC_REO_R1_IDLE_STATES_IX_0___RWC QCSR_REG_RO +#define UMAC_REO_R1_IDLE_STATES_IX_0___POR 0x00000000 +#define UMAC_REO_R1_IDLE_STATES_IX_0__IDLE_STATE___POR 0x00000000 +#define UMAC_REO_R1_IDLE_STATES_IX_0__IDLE_STATE___M 0xFFFFFFFF +#define UMAC_REO_R1_IDLE_STATES_IX_0__IDLE_STATE___S 0 +#define UMAC_REO_R1_IDLE_STATES_IX_0___M 0xFFFFFFFF +#define UMAC_REO_R1_IDLE_STATES_IX_0___S 0 + +#define UMAC_REO_R1_INVALID_APB_ACCESS (0x00A3A074) +#define UMAC_REO_R1_INVALID_APB_ACCESS___RWC QCSR_REG_RW +#define UMAC_REO_R1_INVALID_APB_ACCESS___POR 0x00000000 +#define UMAC_REO_R1_INVALID_APB_ACCESS__ERR_TYPE___POR 0x0 +#define UMAC_REO_R1_INVALID_APB_ACCESS__ERR_ADDR___POR 0x00000 +#define UMAC_REO_R1_INVALID_APB_ACCESS__ERR_TYPE___M 0x00060000 +#define UMAC_REO_R1_INVALID_APB_ACCESS__ERR_TYPE___S 17 +#define UMAC_REO_R1_INVALID_APB_ACCESS__ERR_ADDR___M 0x0001FFFF +#define UMAC_REO_R1_INVALID_APB_ACCESS__ERR_ADDR___S 0 +#define UMAC_REO_R1_INVALID_APB_ACCESS___M 0x0007FFFF +#define UMAC_REO_R1_INVALID_APB_ACCESS___S 0 + +#define UMAC_REO_R2_RXDMA2REO0_RING_HP (0x00A3B000) +#define UMAC_REO_R2_RXDMA2REO0_RING_HP___RWC QCSR_REG_RW +#define UMAC_REO_R2_RXDMA2REO0_RING_HP___POR 0x00000000 +#define UMAC_REO_R2_RXDMA2REO0_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_REO_R2_RXDMA2REO0_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_REO_R2_RXDMA2REO0_RING_HP__HEAD_PTR___S 0 +#define UMAC_REO_R2_RXDMA2REO0_RING_HP___M 0x0000FFFF +#define UMAC_REO_R2_RXDMA2REO0_RING_HP___S 0 + +#define UMAC_REO_R2_RXDMA2REO0_RING_TP (0x00A3B004) +#define UMAC_REO_R2_RXDMA2REO0_RING_TP___RWC QCSR_REG_RW +#define UMAC_REO_R2_RXDMA2REO0_RING_TP___POR 0x00000000 +#define UMAC_REO_R2_RXDMA2REO0_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_REO_R2_RXDMA2REO0_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_REO_R2_RXDMA2REO0_RING_TP__TAIL_PTR___S 0 +#define UMAC_REO_R2_RXDMA2REO0_RING_TP___M 0x0000FFFF +#define UMAC_REO_R2_RXDMA2REO0_RING_TP___S 0 + +#define UMAC_REO_R2_WBM2REO_LINK_RING_HP (0x00A3B008) +#define UMAC_REO_R2_WBM2REO_LINK_RING_HP___RWC QCSR_REG_RW +#define UMAC_REO_R2_WBM2REO_LINK_RING_HP___POR 0x00000000 +#define UMAC_REO_R2_WBM2REO_LINK_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_REO_R2_WBM2REO_LINK_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_REO_R2_WBM2REO_LINK_RING_HP__HEAD_PTR___S 0 +#define UMAC_REO_R2_WBM2REO_LINK_RING_HP___M 0x0000FFFF +#define UMAC_REO_R2_WBM2REO_LINK_RING_HP___S 0 + +#define UMAC_REO_R2_WBM2REO_LINK_RING_TP (0x00A3B00C) +#define UMAC_REO_R2_WBM2REO_LINK_RING_TP___RWC QCSR_REG_RW +#define UMAC_REO_R2_WBM2REO_LINK_RING_TP___POR 0x00000000 +#define UMAC_REO_R2_WBM2REO_LINK_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_REO_R2_WBM2REO_LINK_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_REO_R2_WBM2REO_LINK_RING_TP__TAIL_PTR___S 0 +#define UMAC_REO_R2_WBM2REO_LINK_RING_TP___M 0x0000FFFF +#define UMAC_REO_R2_WBM2REO_LINK_RING_TP___S 0 + +#define UMAC_REO_R2_REO_CMD_RING_HP (0x00A3B010) +#define UMAC_REO_R2_REO_CMD_RING_HP___RWC QCSR_REG_RW +#define UMAC_REO_R2_REO_CMD_RING_HP___POR 0x00000000 +#define UMAC_REO_R2_REO_CMD_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_REO_R2_REO_CMD_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_REO_R2_REO_CMD_RING_HP__HEAD_PTR___S 0 +#define UMAC_REO_R2_REO_CMD_RING_HP___M 0x0000FFFF +#define UMAC_REO_R2_REO_CMD_RING_HP___S 0 + +#define UMAC_REO_R2_REO_CMD_RING_TP (0x00A3B014) +#define UMAC_REO_R2_REO_CMD_RING_TP___RWC QCSR_REG_RW +#define UMAC_REO_R2_REO_CMD_RING_TP___POR 0x00000000 +#define UMAC_REO_R2_REO_CMD_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_REO_R2_REO_CMD_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_REO_R2_REO_CMD_RING_TP__TAIL_PTR___S 0 +#define UMAC_REO_R2_REO_CMD_RING_TP___M 0x0000FFFF +#define UMAC_REO_R2_REO_CMD_RING_TP___S 0 + +#define UMAC_REO_R2_SW2REO_RING_HP (0x00A3B018) +#define UMAC_REO_R2_SW2REO_RING_HP___RWC QCSR_REG_RW +#define UMAC_REO_R2_SW2REO_RING_HP___POR 0x00000000 +#define UMAC_REO_R2_SW2REO_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_REO_R2_SW2REO_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_REO_R2_SW2REO_RING_HP__HEAD_PTR___S 0 +#define UMAC_REO_R2_SW2REO_RING_HP___M 0x0000FFFF +#define UMAC_REO_R2_SW2REO_RING_HP___S 0 + +#define UMAC_REO_R2_SW2REO_RING_TP (0x00A3B01C) +#define UMAC_REO_R2_SW2REO_RING_TP___RWC QCSR_REG_RW +#define UMAC_REO_R2_SW2REO_RING_TP___POR 0x00000000 +#define UMAC_REO_R2_SW2REO_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_REO_R2_SW2REO_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_REO_R2_SW2REO_RING_TP__TAIL_PTR___S 0 +#define UMAC_REO_R2_SW2REO_RING_TP___M 0x0000FFFF +#define UMAC_REO_R2_SW2REO_RING_TP___S 0 + +#define UMAC_REO_R2_SW2REO1_RING_HP (0x00A3B020) +#define UMAC_REO_R2_SW2REO1_RING_HP___RWC QCSR_REG_RW +#define UMAC_REO_R2_SW2REO1_RING_HP___POR 0x00000000 +#define UMAC_REO_R2_SW2REO1_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_REO_R2_SW2REO1_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_REO_R2_SW2REO1_RING_HP__HEAD_PTR___S 0 +#define UMAC_REO_R2_SW2REO1_RING_HP___M 0x0000FFFF +#define UMAC_REO_R2_SW2REO1_RING_HP___S 0 + +#define UMAC_REO_R2_SW2REO1_RING_TP (0x00A3B024) +#define UMAC_REO_R2_SW2REO1_RING_TP___RWC QCSR_REG_RW +#define UMAC_REO_R2_SW2REO1_RING_TP___POR 0x00000000 +#define UMAC_REO_R2_SW2REO1_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_REO_R2_SW2REO1_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_REO_R2_SW2REO1_RING_TP__TAIL_PTR___S 0 +#define UMAC_REO_R2_SW2REO1_RING_TP___M 0x0000FFFF +#define UMAC_REO_R2_SW2REO1_RING_TP___S 0 + +#define UMAC_REO_R2_REO2SW1_RING_HP (0x00A3B028) +#define UMAC_REO_R2_REO2SW1_RING_HP___RWC QCSR_REG_RW +#define UMAC_REO_R2_REO2SW1_RING_HP___POR 0x00000000 +#define UMAC_REO_R2_REO2SW1_RING_HP__HEAD_PTR___POR 0x00000 +#define UMAC_REO_R2_REO2SW1_RING_HP__HEAD_PTR___M 0x000FFFFF +#define UMAC_REO_R2_REO2SW1_RING_HP__HEAD_PTR___S 0 +#define UMAC_REO_R2_REO2SW1_RING_HP___M 0x000FFFFF +#define UMAC_REO_R2_REO2SW1_RING_HP___S 0 + +#define UMAC_REO_R2_REO2SW1_RING_TP (0x00A3B02C) +#define UMAC_REO_R2_REO2SW1_RING_TP___RWC QCSR_REG_RW +#define UMAC_REO_R2_REO2SW1_RING_TP___POR 0x00000000 +#define UMAC_REO_R2_REO2SW1_RING_TP__TAIL_PTR___POR 0x00000 +#define UMAC_REO_R2_REO2SW1_RING_TP__TAIL_PTR___M 0x000FFFFF +#define UMAC_REO_R2_REO2SW1_RING_TP__TAIL_PTR___S 0 +#define UMAC_REO_R2_REO2SW1_RING_TP___M 0x000FFFFF +#define UMAC_REO_R2_REO2SW1_RING_TP___S 0 + +#define UMAC_REO_R2_REO2SW2_RING_HP (0x00A3B030) +#define UMAC_REO_R2_REO2SW2_RING_HP___RWC QCSR_REG_RW +#define UMAC_REO_R2_REO2SW2_RING_HP___POR 0x00000000 +#define UMAC_REO_R2_REO2SW2_RING_HP__HEAD_PTR___POR 0x00000 +#define UMAC_REO_R2_REO2SW2_RING_HP__HEAD_PTR___M 0x000FFFFF +#define UMAC_REO_R2_REO2SW2_RING_HP__HEAD_PTR___S 0 +#define UMAC_REO_R2_REO2SW2_RING_HP___M 0x000FFFFF +#define UMAC_REO_R2_REO2SW2_RING_HP___S 0 + +#define UMAC_REO_R2_REO2SW2_RING_TP (0x00A3B034) +#define UMAC_REO_R2_REO2SW2_RING_TP___RWC QCSR_REG_RW +#define UMAC_REO_R2_REO2SW2_RING_TP___POR 0x00000000 +#define UMAC_REO_R2_REO2SW2_RING_TP__TAIL_PTR___POR 0x00000 +#define UMAC_REO_R2_REO2SW2_RING_TP__TAIL_PTR___M 0x000FFFFF +#define UMAC_REO_R2_REO2SW2_RING_TP__TAIL_PTR___S 0 +#define UMAC_REO_R2_REO2SW2_RING_TP___M 0x000FFFFF +#define UMAC_REO_R2_REO2SW2_RING_TP___S 0 + +#define UMAC_REO_R2_REO2SW3_RING_HP (0x00A3B038) +#define UMAC_REO_R2_REO2SW3_RING_HP___RWC QCSR_REG_RW +#define UMAC_REO_R2_REO2SW3_RING_HP___POR 0x00000000 +#define UMAC_REO_R2_REO2SW3_RING_HP__HEAD_PTR___POR 0x00000 +#define UMAC_REO_R2_REO2SW3_RING_HP__HEAD_PTR___M 0x000FFFFF +#define UMAC_REO_R2_REO2SW3_RING_HP__HEAD_PTR___S 0 +#define UMAC_REO_R2_REO2SW3_RING_HP___M 0x000FFFFF +#define UMAC_REO_R2_REO2SW3_RING_HP___S 0 + +#define UMAC_REO_R2_REO2SW3_RING_TP (0x00A3B03C) +#define UMAC_REO_R2_REO2SW3_RING_TP___RWC QCSR_REG_RW +#define UMAC_REO_R2_REO2SW3_RING_TP___POR 0x00000000 +#define UMAC_REO_R2_REO2SW3_RING_TP__TAIL_PTR___POR 0x00000 +#define UMAC_REO_R2_REO2SW3_RING_TP__TAIL_PTR___M 0x000FFFFF +#define UMAC_REO_R2_REO2SW3_RING_TP__TAIL_PTR___S 0 +#define UMAC_REO_R2_REO2SW3_RING_TP___M 0x000FFFFF +#define UMAC_REO_R2_REO2SW3_RING_TP___S 0 + +#define UMAC_REO_R2_REO2SW4_RING_HP (0x00A3B040) +#define UMAC_REO_R2_REO2SW4_RING_HP___RWC QCSR_REG_RW +#define UMAC_REO_R2_REO2SW4_RING_HP___POR 0x00000000 +#define UMAC_REO_R2_REO2SW4_RING_HP__HEAD_PTR___POR 0x00000 +#define UMAC_REO_R2_REO2SW4_RING_HP__HEAD_PTR___M 0x000FFFFF +#define UMAC_REO_R2_REO2SW4_RING_HP__HEAD_PTR___S 0 +#define UMAC_REO_R2_REO2SW4_RING_HP___M 0x000FFFFF +#define UMAC_REO_R2_REO2SW4_RING_HP___S 0 + +#define UMAC_REO_R2_REO2SW4_RING_TP (0x00A3B044) +#define UMAC_REO_R2_REO2SW4_RING_TP___RWC QCSR_REG_RW +#define UMAC_REO_R2_REO2SW4_RING_TP___POR 0x00000000 +#define UMAC_REO_R2_REO2SW4_RING_TP__TAIL_PTR___POR 0x00000 +#define UMAC_REO_R2_REO2SW4_RING_TP__TAIL_PTR___M 0x000FFFFF +#define UMAC_REO_R2_REO2SW4_RING_TP__TAIL_PTR___S 0 +#define UMAC_REO_R2_REO2SW4_RING_TP___M 0x000FFFFF +#define UMAC_REO_R2_REO2SW4_RING_TP___S 0 + +#define UMAC_REO_R2_REO2SW5_RING_HP (0x00A3B048) +#define UMAC_REO_R2_REO2SW5_RING_HP___RWC QCSR_REG_RW +#define UMAC_REO_R2_REO2SW5_RING_HP___POR 0x00000000 +#define UMAC_REO_R2_REO2SW5_RING_HP__HEAD_PTR___POR 0x00000 +#define UMAC_REO_R2_REO2SW5_RING_HP__HEAD_PTR___M 0x000FFFFF +#define UMAC_REO_R2_REO2SW5_RING_HP__HEAD_PTR___S 0 +#define UMAC_REO_R2_REO2SW5_RING_HP___M 0x000FFFFF +#define UMAC_REO_R2_REO2SW5_RING_HP___S 0 + +#define UMAC_REO_R2_REO2SW5_RING_TP (0x00A3B04C) +#define UMAC_REO_R2_REO2SW5_RING_TP___RWC QCSR_REG_RW +#define UMAC_REO_R2_REO2SW5_RING_TP___POR 0x00000000 +#define UMAC_REO_R2_REO2SW5_RING_TP__TAIL_PTR___POR 0x00000 +#define UMAC_REO_R2_REO2SW5_RING_TP__TAIL_PTR___M 0x000FFFFF +#define UMAC_REO_R2_REO2SW5_RING_TP__TAIL_PTR___S 0 +#define UMAC_REO_R2_REO2SW5_RING_TP___M 0x000FFFFF +#define UMAC_REO_R2_REO2SW5_RING_TP___S 0 + +#define UMAC_REO_R2_REO2SW6_RING_HP (0x00A3B050) +#define UMAC_REO_R2_REO2SW6_RING_HP___RWC QCSR_REG_RW +#define UMAC_REO_R2_REO2SW6_RING_HP___POR 0x00000000 +#define UMAC_REO_R2_REO2SW6_RING_HP__HEAD_PTR___POR 0x00000 +#define UMAC_REO_R2_REO2SW6_RING_HP__HEAD_PTR___M 0x000FFFFF +#define UMAC_REO_R2_REO2SW6_RING_HP__HEAD_PTR___S 0 +#define UMAC_REO_R2_REO2SW6_RING_HP___M 0x000FFFFF +#define UMAC_REO_R2_REO2SW6_RING_HP___S 0 + +#define UMAC_REO_R2_REO2SW6_RING_TP (0x00A3B054) +#define UMAC_REO_R2_REO2SW6_RING_TP___RWC QCSR_REG_RW +#define UMAC_REO_R2_REO2SW6_RING_TP___POR 0x00000000 +#define UMAC_REO_R2_REO2SW6_RING_TP__TAIL_PTR___POR 0x00000 +#define UMAC_REO_R2_REO2SW6_RING_TP__TAIL_PTR___M 0x000FFFFF +#define UMAC_REO_R2_REO2SW6_RING_TP__TAIL_PTR___S 0 +#define UMAC_REO_R2_REO2SW6_RING_TP___M 0x000FFFFF +#define UMAC_REO_R2_REO2SW6_RING_TP___S 0 + +#define UMAC_REO_R2_REO2TCL_RING_HP (0x00A3B058) +#define UMAC_REO_R2_REO2TCL_RING_HP___RWC QCSR_REG_RW +#define UMAC_REO_R2_REO2TCL_RING_HP___POR 0x00000000 +#define UMAC_REO_R2_REO2TCL_RING_HP__HEAD_PTR___POR 0x00000 +#define UMAC_REO_R2_REO2TCL_RING_HP__HEAD_PTR___M 0x000FFFFF +#define UMAC_REO_R2_REO2TCL_RING_HP__HEAD_PTR___S 0 +#define UMAC_REO_R2_REO2TCL_RING_HP___M 0x000FFFFF +#define UMAC_REO_R2_REO2TCL_RING_HP___S 0 + +#define UMAC_REO_R2_REO2TCL_RING_TP (0x00A3B05C) +#define UMAC_REO_R2_REO2TCL_RING_TP___RWC QCSR_REG_RW +#define UMAC_REO_R2_REO2TCL_RING_TP___POR 0x00000000 +#define UMAC_REO_R2_REO2TCL_RING_TP__TAIL_PTR___POR 0x00000 +#define UMAC_REO_R2_REO2TCL_RING_TP__TAIL_PTR___M 0x000FFFFF +#define UMAC_REO_R2_REO2TCL_RING_TP__TAIL_PTR___S 0 +#define UMAC_REO_R2_REO2TCL_RING_TP___M 0x000FFFFF +#define UMAC_REO_R2_REO2TCL_RING_TP___S 0 + +#define UMAC_REO_R2_REO2FW_RING_HP (0x00A3B060) +#define UMAC_REO_R2_REO2FW_RING_HP___RWC QCSR_REG_RW +#define UMAC_REO_R2_REO2FW_RING_HP___POR 0x00000000 +#define UMAC_REO_R2_REO2FW_RING_HP__HEAD_PTR___POR 0x00000 +#define UMAC_REO_R2_REO2FW_RING_HP__HEAD_PTR___M 0x000FFFFF +#define UMAC_REO_R2_REO2FW_RING_HP__HEAD_PTR___S 0 +#define UMAC_REO_R2_REO2FW_RING_HP___M 0x000FFFFF +#define UMAC_REO_R2_REO2FW_RING_HP___S 0 + +#define UMAC_REO_R2_REO2FW_RING_TP (0x00A3B064) +#define UMAC_REO_R2_REO2FW_RING_TP___RWC QCSR_REG_RW +#define UMAC_REO_R2_REO2FW_RING_TP___POR 0x00000000 +#define UMAC_REO_R2_REO2FW_RING_TP__TAIL_PTR___POR 0x00000 +#define UMAC_REO_R2_REO2FW_RING_TP__TAIL_PTR___M 0x000FFFFF +#define UMAC_REO_R2_REO2FW_RING_TP__TAIL_PTR___S 0 +#define UMAC_REO_R2_REO2FW_RING_TP___M 0x000FFFFF +#define UMAC_REO_R2_REO2FW_RING_TP___S 0 + +#define UMAC_REO_R2_REO_RELEASE_RING_HP (0x00A3B068) +#define UMAC_REO_R2_REO_RELEASE_RING_HP___RWC QCSR_REG_RW +#define UMAC_REO_R2_REO_RELEASE_RING_HP___POR 0x00000000 +#define UMAC_REO_R2_REO_RELEASE_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_REO_R2_REO_RELEASE_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_REO_R2_REO_RELEASE_RING_HP__HEAD_PTR___S 0 +#define UMAC_REO_R2_REO_RELEASE_RING_HP___M 0x0000FFFF +#define UMAC_REO_R2_REO_RELEASE_RING_HP___S 0 + +#define UMAC_REO_R2_REO_RELEASE_RING_TP (0x00A3B06C) +#define UMAC_REO_R2_REO_RELEASE_RING_TP___RWC QCSR_REG_RW +#define UMAC_REO_R2_REO_RELEASE_RING_TP___POR 0x00000000 +#define UMAC_REO_R2_REO_RELEASE_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_REO_R2_REO_RELEASE_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_REO_R2_REO_RELEASE_RING_TP__TAIL_PTR___S 0 +#define UMAC_REO_R2_REO_RELEASE_RING_TP___M 0x0000FFFF +#define UMAC_REO_R2_REO_RELEASE_RING_TP___S 0 + +#define UMAC_REO_R2_REO_STATUS_RING_HP (0x00A3B070) +#define UMAC_REO_R2_REO_STATUS_RING_HP___RWC QCSR_REG_RW +#define UMAC_REO_R2_REO_STATUS_RING_HP___POR 0x00000000 +#define UMAC_REO_R2_REO_STATUS_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_REO_R2_REO_STATUS_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_REO_R2_REO_STATUS_RING_HP__HEAD_PTR___S 0 +#define UMAC_REO_R2_REO_STATUS_RING_HP___M 0x0000FFFF +#define UMAC_REO_R2_REO_STATUS_RING_HP___S 0 + +#define UMAC_REO_R2_REO_STATUS_RING_TP (0x00A3B074) +#define UMAC_REO_R2_REO_STATUS_RING_TP___RWC QCSR_REG_RW +#define UMAC_REO_R2_REO_STATUS_RING_TP___POR 0x00000000 +#define UMAC_REO_R2_REO_STATUS_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_REO_R2_REO_STATUS_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_REO_R2_REO_STATUS_RING_TP__TAIL_PTR___S 0 +#define UMAC_REO_R2_REO_STATUS_RING_TP___M 0x0000FFFF +#define UMAC_REO_R2_REO_STATUS_RING_TP___S 0 + +#define UMAC_TQM_R0_CONTROL (0x00A3C000) +#define UMAC_TQM_R0_CONTROL___RWC QCSR_REG_RW +#define UMAC_TQM_R0_CONTROL___POR 0x00000012 +#define UMAC_TQM_R0_CONTROL__INIT_PREFETCH_BUFFER_PTRS___POR 0x1 +#define UMAC_TQM_R0_CONTROL__BLOCK_PREFETCH___POR 0x0 +#define UMAC_TQM_R0_CONTROL__STAT_RING_SEL___POR 0x0 +#define UMAC_TQM_R0_CONTROL__CONCURRENT_PROC___POR 0x1 +#define UMAC_TQM_R0_CONTROL__ENABLE___POR 0x0 +#define UMAC_TQM_R0_CONTROL__INIT_PREFETCH_BUFFER_PTRS___M 0x00000010 +#define UMAC_TQM_R0_CONTROL__INIT_PREFETCH_BUFFER_PTRS___S 4 +#define UMAC_TQM_R0_CONTROL__BLOCK_PREFETCH___M 0x00000008 +#define UMAC_TQM_R0_CONTROL__BLOCK_PREFETCH___S 3 +#define UMAC_TQM_R0_CONTROL__STAT_RING_SEL___M 0x00000004 +#define UMAC_TQM_R0_CONTROL__STAT_RING_SEL___S 2 +#define UMAC_TQM_R0_CONTROL__CONCURRENT_PROC___M 0x00000002 +#define UMAC_TQM_R0_CONTROL__CONCURRENT_PROC___S 1 +#define UMAC_TQM_R0_CONTROL__ENABLE___M 0x00000001 +#define UMAC_TQM_R0_CONTROL__ENABLE___S 0 +#define UMAC_TQM_R0_CONTROL___M 0x0000001F +#define UMAC_TQM_R0_CONTROL___S 0 + +#define UMAC_TQM_R0_PAUSE_CONTROL (0x00A3C004) +#define UMAC_TQM_R0_PAUSE_CONTROL___RWC QCSR_REG_RW +#define UMAC_TQM_R0_PAUSE_CONTROL___POR 0x00000003 +#define UMAC_TQM_R0_PAUSE_CONTROL__ENABLE_HW_ACKED_MPDU___POR 0x0 +#define UMAC_TQM_R0_PAUSE_CONTROL__ENABLE_HWSCH_CMD___POR 0x1 +#define UMAC_TQM_R0_PAUSE_CONTROL__ENABLE_SW_CMD___POR 0x1 +#define UMAC_TQM_R0_PAUSE_CONTROL__ENABLE_HW_ACKED_MPDU___M 0x00000004 +#define UMAC_TQM_R0_PAUSE_CONTROL__ENABLE_HW_ACKED_MPDU___S 2 +#define UMAC_TQM_R0_PAUSE_CONTROL__ENABLE_HWSCH_CMD___M 0x00000002 +#define UMAC_TQM_R0_PAUSE_CONTROL__ENABLE_HWSCH_CMD___S 1 +#define UMAC_TQM_R0_PAUSE_CONTROL__ENABLE_SW_CMD___M 0x00000001 +#define UMAC_TQM_R0_PAUSE_CONTROL__ENABLE_SW_CMD___S 0 +#define UMAC_TQM_R0_PAUSE_CONTROL___M 0x00000007 +#define UMAC_TQM_R0_PAUSE_CONTROL___S 0 + +#define UMAC_TQM_R0_MISC_CONTROL (0x00A3C008) +#define UMAC_TQM_R0_MISC_CONTROL___RWC QCSR_REG_RW +#define UMAC_TQM_R0_MISC_CONTROL___POR 0x00000010 +#define UMAC_TQM_R0_MISC_CONTROL__GEN_ACKED_MPDU_INFO_END___POR 0x0 +#define UMAC_TQM_R0_MISC_CONTROL__RETAIN_CACHE___POR 0x0 +#define UMAC_TQM_R0_MISC_CONTROL__FLUSH_IDLE_COUNT___POR 0x10 +#define UMAC_TQM_R0_MISC_CONTROL__GEN_ACKED_MPDU_INFO_END___M 0x00000200 +#define UMAC_TQM_R0_MISC_CONTROL__GEN_ACKED_MPDU_INFO_END___S 9 +#define UMAC_TQM_R0_MISC_CONTROL__RETAIN_CACHE___M 0x00000100 +#define UMAC_TQM_R0_MISC_CONTROL__RETAIN_CACHE___S 8 +#define UMAC_TQM_R0_MISC_CONTROL__FLUSH_IDLE_COUNT___M 0x000000FF +#define UMAC_TQM_R0_MISC_CONTROL__FLUSH_IDLE_COUNT___S 0 +#define UMAC_TQM_R0_MISC_CONTROL___M 0x000003FF +#define UMAC_TQM_R0_MISC_CONTROL___S 0 + +#define UMAC_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL (0x00A3C00C) +#define UMAC_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL___RWC QCSR_REG_RW +#define UMAC_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL___POR 0x0000020A +#define UMAC_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL__ENABLE_PREFETCH___POR 0x1 +#define UMAC_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL__CMD_EXECUTION_TIME_VALID___POR 0x0 +#define UMAC_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL__MAX_CMD_EXECUTION_TIME___POR 0x0A +#define UMAC_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL__ENABLE_PREFETCH___M 0x00000200 +#define UMAC_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL__ENABLE_PREFETCH___S 9 +#define UMAC_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL__CMD_EXECUTION_TIME_VALID___M 0x00000100 +#define UMAC_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL__CMD_EXECUTION_TIME_VALID___S 8 +#define UMAC_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL__MAX_CMD_EXECUTION_TIME___M 0x000000FF +#define UMAC_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL__MAX_CMD_EXECUTION_TIME___S 0 +#define UMAC_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL___M 0x000003FF +#define UMAC_TQM_R0_UPDATE_TX_MPDU_COUNT_SM_CONTROL___S 0 + +#define UMAC_TQM_R0_TCL2TQM_RING_BASE_LSB (0x00A3C010) +#define UMAC_TQM_R0_TCL2TQM_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TCL2TQM_RING_BASE_LSB___POR 0x00000000 +#define UMAC_TQM_R0_TCL2TQM_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_TQM_R0_TCL2TQM_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_TCL2TQM_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_TQM_R0_TCL2TQM_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_TCL2TQM_RING_BASE_LSB___S 0 + +#define UMAC_TQM_R0_TCL2TQM_RING_BASE_MSB (0x00A3C014) +#define UMAC_TQM_R0_TCL2TQM_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TCL2TQM_RING_BASE_MSB___POR 0x00000000 +#define UMAC_TQM_R0_TCL2TQM_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_TQM_R0_TCL2TQM_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_TQM_R0_TCL2TQM_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_TQM_R0_TCL2TQM_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_TQM_R0_TCL2TQM_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_TQM_R0_TCL2TQM_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_TQM_R0_TCL2TQM_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_TQM_R0_TCL2TQM_RING_BASE_MSB___S 0 + +#define UMAC_TQM_R0_TCL2TQM_RING_ID (0x00A3C018) +#define UMAC_TQM_R0_TCL2TQM_RING_ID___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TCL2TQM_RING_ID___POR 0x00000000 +#define UMAC_TQM_R0_TCL2TQM_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_TQM_R0_TCL2TQM_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_TQM_R0_TCL2TQM_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_TQM_R0_TCL2TQM_RING_ID___M 0x000000FF +#define UMAC_TQM_R0_TCL2TQM_RING_ID___S 0 + +#define UMAC_TQM_R0_TCL2TQM_RING_STATUS (0x00A3C01C) +#define UMAC_TQM_R0_TCL2TQM_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_TCL2TQM_RING_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_TCL2TQM_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_TQM_R0_TCL2TQM_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_TQM_R0_TCL2TQM_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_TQM_R0_TCL2TQM_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_TQM_R0_TCL2TQM_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_TQM_R0_TCL2TQM_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_TQM_R0_TCL2TQM_RING_STATUS___M 0xFFFFFFFF +#define UMAC_TQM_R0_TCL2TQM_RING_STATUS___S 0 + +#define UMAC_TQM_R0_TCL2TQM_RING_MISC (0x00A3C020) +#define UMAC_TQM_R0_TCL2TQM_RING_MISC___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TCL2TQM_RING_MISC___POR 0x00000080 +#define UMAC_TQM_R0_TCL2TQM_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_TQM_R0_TCL2TQM_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_TQM_R0_TCL2TQM_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_TQM_R0_TCL2TQM_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_TQM_R0_TCL2TQM_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_TQM_R0_TCL2TQM_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_TQM_R0_TCL2TQM_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_TQM_R0_TCL2TQM_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_TQM_R0_TCL2TQM_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_TQM_R0_TCL2TQM_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_TQM_R0_TCL2TQM_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_TQM_R0_TCL2TQM_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_TQM_R0_TCL2TQM_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_TQM_R0_TCL2TQM_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_TQM_R0_TCL2TQM_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_TQM_R0_TCL2TQM_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_TQM_R0_TCL2TQM_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_TQM_R0_TCL2TQM_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_TQM_R0_TCL2TQM_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_TQM_R0_TCL2TQM_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_TQM_R0_TCL2TQM_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_TQM_R0_TCL2TQM_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_TQM_R0_TCL2TQM_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_TQM_R0_TCL2TQM_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_TQM_R0_TCL2TQM_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_TQM_R0_TCL2TQM_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_TQM_R0_TCL2TQM_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_TQM_R0_TCL2TQM_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_TQM_R0_TCL2TQM_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_TQM_R0_TCL2TQM_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_TQM_R0_TCL2TQM_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_TQM_R0_TCL2TQM_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_TQM_R0_TCL2TQM_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_TQM_R0_TCL2TQM_RING_MISC___M 0x003FFFFF +#define UMAC_TQM_R0_TCL2TQM_RING_MISC___S 0 + +#define UMAC_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB (0x00A3C02C) +#define UMAC_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB___POR 0x00000000 +#define UMAC_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S 0 +#define UMAC_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_TCL2TQM_RING_TP_ADDR_LSB___S 0 + +#define UMAC_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB (0x00A3C030) +#define UMAC_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB___POR 0x00000000 +#define UMAC_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S 0 +#define UMAC_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB___M 0x000000FF +#define UMAC_TQM_R0_TCL2TQM_RING_TP_ADDR_MSB___S 0 + +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0 (0x00A3C040) +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S 15 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX0___S 0 + +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1 (0x00A3C044) +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S 0 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_SETUP_IX1___S 0 + +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS (0x00A3C048) +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S 15 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_INT_STATUS___S 0 + +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER (0x00A3C04C) +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S 0 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_EMPTY_COUNTER___S 0 + +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER (0x00A3C050) +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER__MODE___S 0 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_TIMER___S 0 + +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS (0x00A3C054) +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S 16 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S 0 +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF +#define UMAC_TQM_R0_TCL2TQM_RING_CONSUMER_PREFETCH_STATUS___S 0 + +#define UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB (0x00A3C058) +#define UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB (0x00A3C05C) +#define UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_TQM_R0_TCL2TQM_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_TQM_R0_TCL2TQM_RING_MSI1_DATA (0x00A3C060) +#define UMAC_TQM_R0_TCL2TQM_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TCL2TQM_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_TQM_R0_TCL2TQM_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_TQM_R0_TCL2TQM_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_TQM_R0_TCL2TQM_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_TQM_R0_TCL2TQM_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_TQM_R0_TCL2TQM_RING_MSI1_DATA___S 0 + +#define UMAC_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET (0x00A3C064) +#define UMAC_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_TQM_R0_TCL2TQM_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_TQM_R0_SW2TQM_RING_BASE_LSB (0x00A3C068) +#define UMAC_TQM_R0_SW2TQM_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW2TQM_RING_BASE_LSB___POR 0x00000000 +#define UMAC_TQM_R0_SW2TQM_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_TQM_R0_SW2TQM_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_SW2TQM_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_TQM_R0_SW2TQM_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_SW2TQM_RING_BASE_LSB___S 0 + +#define UMAC_TQM_R0_SW2TQM_RING_BASE_MSB (0x00A3C06C) +#define UMAC_TQM_R0_SW2TQM_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW2TQM_RING_BASE_MSB___POR 0x00000000 +#define UMAC_TQM_R0_SW2TQM_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_TQM_R0_SW2TQM_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_TQM_R0_SW2TQM_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_TQM_R0_SW2TQM_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_TQM_R0_SW2TQM_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_TQM_R0_SW2TQM_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_TQM_R0_SW2TQM_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_TQM_R0_SW2TQM_RING_BASE_MSB___S 0 + +#define UMAC_TQM_R0_SW2TQM_RING_ID (0x00A3C070) +#define UMAC_TQM_R0_SW2TQM_RING_ID___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW2TQM_RING_ID___POR 0x00000000 +#define UMAC_TQM_R0_SW2TQM_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_TQM_R0_SW2TQM_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_TQM_R0_SW2TQM_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_TQM_R0_SW2TQM_RING_ID___M 0x000000FF +#define UMAC_TQM_R0_SW2TQM_RING_ID___S 0 + +#define UMAC_TQM_R0_SW2TQM_RING_STATUS (0x00A3C074) +#define UMAC_TQM_R0_SW2TQM_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_SW2TQM_RING_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_SW2TQM_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_TQM_R0_SW2TQM_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_TQM_R0_SW2TQM_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_TQM_R0_SW2TQM_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_TQM_R0_SW2TQM_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_TQM_R0_SW2TQM_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_TQM_R0_SW2TQM_RING_STATUS___M 0xFFFFFFFF +#define UMAC_TQM_R0_SW2TQM_RING_STATUS___S 0 + +#define UMAC_TQM_R0_SW2TQM_RING_MISC (0x00A3C078) +#define UMAC_TQM_R0_SW2TQM_RING_MISC___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW2TQM_RING_MISC___POR 0x00000080 +#define UMAC_TQM_R0_SW2TQM_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_TQM_R0_SW2TQM_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_TQM_R0_SW2TQM_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_TQM_R0_SW2TQM_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_TQM_R0_SW2TQM_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_TQM_R0_SW2TQM_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_TQM_R0_SW2TQM_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_TQM_R0_SW2TQM_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_TQM_R0_SW2TQM_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_TQM_R0_SW2TQM_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_TQM_R0_SW2TQM_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_TQM_R0_SW2TQM_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_TQM_R0_SW2TQM_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_TQM_R0_SW2TQM_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_TQM_R0_SW2TQM_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_TQM_R0_SW2TQM_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_TQM_R0_SW2TQM_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_TQM_R0_SW2TQM_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_TQM_R0_SW2TQM_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_TQM_R0_SW2TQM_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_TQM_R0_SW2TQM_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_TQM_R0_SW2TQM_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_TQM_R0_SW2TQM_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_TQM_R0_SW2TQM_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_TQM_R0_SW2TQM_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_TQM_R0_SW2TQM_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_TQM_R0_SW2TQM_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_TQM_R0_SW2TQM_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_TQM_R0_SW2TQM_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_TQM_R0_SW2TQM_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_TQM_R0_SW2TQM_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_TQM_R0_SW2TQM_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_TQM_R0_SW2TQM_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_TQM_R0_SW2TQM_RING_MISC___M 0x003FFFFF +#define UMAC_TQM_R0_SW2TQM_RING_MISC___S 0 + +#define UMAC_TQM_R0_SW2TQM_RING_TP_ADDR_LSB (0x00A3C084) +#define UMAC_TQM_R0_SW2TQM_RING_TP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW2TQM_RING_TP_ADDR_LSB___POR 0x00000000 +#define UMAC_TQM_R0_SW2TQM_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_TQM_R0_SW2TQM_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_SW2TQM_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S 0 +#define UMAC_TQM_R0_SW2TQM_RING_TP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_SW2TQM_RING_TP_ADDR_LSB___S 0 + +#define UMAC_TQM_R0_SW2TQM_RING_TP_ADDR_MSB (0x00A3C088) +#define UMAC_TQM_R0_SW2TQM_RING_TP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW2TQM_RING_TP_ADDR_MSB___POR 0x00000000 +#define UMAC_TQM_R0_SW2TQM_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_TQM_R0_SW2TQM_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_TQM_R0_SW2TQM_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S 0 +#define UMAC_TQM_R0_SW2TQM_RING_TP_ADDR_MSB___M 0x000000FF +#define UMAC_TQM_R0_SW2TQM_RING_TP_ADDR_MSB___S 0 + +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX0 (0x00A3C098) +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S 15 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX0___S 0 + +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX1 (0x00A3C09C) +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S 0 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_SETUP_IX1___S 0 + +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_STATUS (0x00A3C0A0) +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S 15 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_INT_STATUS___S 0 + +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_EMPTY_COUNTER (0x00A3C0A4) +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S 0 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_EMPTY_COUNTER___S 0 + +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_TIMER (0x00A3C0A8) +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_TIMER__MODE___S 0 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_TIMER___S 0 + +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_STATUS (0x00A3C0AC) +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S 16 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S 0 +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF +#define UMAC_TQM_R0_SW2TQM_RING_CONSUMER_PREFETCH_STATUS___S 0 + +#define UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_LSB (0x00A3C0B0) +#define UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_MSB (0x00A3C0B4) +#define UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_TQM_R0_SW2TQM_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_TQM_R0_SW2TQM_RING_MSI1_DATA (0x00A3C0B8) +#define UMAC_TQM_R0_SW2TQM_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW2TQM_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_TQM_R0_SW2TQM_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_TQM_R0_SW2TQM_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_TQM_R0_SW2TQM_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_TQM_R0_SW2TQM_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_TQM_R0_SW2TQM_RING_MSI1_DATA___S 0 + +#define UMAC_TQM_R0_SW2TQM_RING_HP_TP_SW_OFFSET (0x00A3C0BC) +#define UMAC_TQM_R0_SW2TQM_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW2TQM_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_TQM_R0_SW2TQM_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_TQM_R0_SW2TQM_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_TQM_R0_SW2TQM_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_TQM_R0_SW2TQM_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_TQM_R0_SW2TQM_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_TQM_R0_FW2TQM_RING_BASE_LSB (0x00A3C0C0) +#define UMAC_TQM_R0_FW2TQM_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_FW2TQM_RING_BASE_LSB___POR 0x00000000 +#define UMAC_TQM_R0_FW2TQM_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_TQM_R0_FW2TQM_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_FW2TQM_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_TQM_R0_FW2TQM_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_FW2TQM_RING_BASE_LSB___S 0 + +#define UMAC_TQM_R0_FW2TQM_RING_BASE_MSB (0x00A3C0C4) +#define UMAC_TQM_R0_FW2TQM_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_FW2TQM_RING_BASE_MSB___POR 0x00000000 +#define UMAC_TQM_R0_FW2TQM_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_TQM_R0_FW2TQM_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_TQM_R0_FW2TQM_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_TQM_R0_FW2TQM_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_TQM_R0_FW2TQM_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_TQM_R0_FW2TQM_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_TQM_R0_FW2TQM_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_TQM_R0_FW2TQM_RING_BASE_MSB___S 0 + +#define UMAC_TQM_R0_FW2TQM_RING_ID (0x00A3C0C8) +#define UMAC_TQM_R0_FW2TQM_RING_ID___RWC QCSR_REG_RW +#define UMAC_TQM_R0_FW2TQM_RING_ID___POR 0x00000000 +#define UMAC_TQM_R0_FW2TQM_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_TQM_R0_FW2TQM_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_TQM_R0_FW2TQM_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_TQM_R0_FW2TQM_RING_ID___M 0x000000FF +#define UMAC_TQM_R0_FW2TQM_RING_ID___S 0 + +#define UMAC_TQM_R0_FW2TQM_RING_STATUS (0x00A3C0CC) +#define UMAC_TQM_R0_FW2TQM_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_FW2TQM_RING_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_FW2TQM_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_TQM_R0_FW2TQM_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_TQM_R0_FW2TQM_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_TQM_R0_FW2TQM_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_TQM_R0_FW2TQM_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_TQM_R0_FW2TQM_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_TQM_R0_FW2TQM_RING_STATUS___M 0xFFFFFFFF +#define UMAC_TQM_R0_FW2TQM_RING_STATUS___S 0 + +#define UMAC_TQM_R0_FW2TQM_RING_MISC (0x00A3C0D0) +#define UMAC_TQM_R0_FW2TQM_RING_MISC___RWC QCSR_REG_RW +#define UMAC_TQM_R0_FW2TQM_RING_MISC___POR 0x00000080 +#define UMAC_TQM_R0_FW2TQM_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_TQM_R0_FW2TQM_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_TQM_R0_FW2TQM_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_TQM_R0_FW2TQM_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_TQM_R0_FW2TQM_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_TQM_R0_FW2TQM_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_TQM_R0_FW2TQM_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_TQM_R0_FW2TQM_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_TQM_R0_FW2TQM_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_TQM_R0_FW2TQM_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_TQM_R0_FW2TQM_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_TQM_R0_FW2TQM_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_TQM_R0_FW2TQM_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_TQM_R0_FW2TQM_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_TQM_R0_FW2TQM_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_TQM_R0_FW2TQM_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_TQM_R0_FW2TQM_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_TQM_R0_FW2TQM_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_TQM_R0_FW2TQM_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_TQM_R0_FW2TQM_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_TQM_R0_FW2TQM_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_TQM_R0_FW2TQM_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_TQM_R0_FW2TQM_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_TQM_R0_FW2TQM_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_TQM_R0_FW2TQM_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_TQM_R0_FW2TQM_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_TQM_R0_FW2TQM_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_TQM_R0_FW2TQM_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_TQM_R0_FW2TQM_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_TQM_R0_FW2TQM_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_TQM_R0_FW2TQM_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_TQM_R0_FW2TQM_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_TQM_R0_FW2TQM_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_TQM_R0_FW2TQM_RING_MISC___M 0x003FFFFF +#define UMAC_TQM_R0_FW2TQM_RING_MISC___S 0 + +#define UMAC_TQM_R0_FW2TQM_RING_TP_ADDR_LSB (0x00A3C0DC) +#define UMAC_TQM_R0_FW2TQM_RING_TP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_FW2TQM_RING_TP_ADDR_LSB___POR 0x00000000 +#define UMAC_TQM_R0_FW2TQM_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_TQM_R0_FW2TQM_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_FW2TQM_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S 0 +#define UMAC_TQM_R0_FW2TQM_RING_TP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_FW2TQM_RING_TP_ADDR_LSB___S 0 + +#define UMAC_TQM_R0_FW2TQM_RING_TP_ADDR_MSB (0x00A3C0E0) +#define UMAC_TQM_R0_FW2TQM_RING_TP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_FW2TQM_RING_TP_ADDR_MSB___POR 0x00000000 +#define UMAC_TQM_R0_FW2TQM_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_TQM_R0_FW2TQM_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_TQM_R0_FW2TQM_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S 0 +#define UMAC_TQM_R0_FW2TQM_RING_TP_ADDR_MSB___M 0x000000FF +#define UMAC_TQM_R0_FW2TQM_RING_TP_ADDR_MSB___S 0 + +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0 (0x00A3C0F0) +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S 15 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX0___S 0 + +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1 (0x00A3C0F4) +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S 0 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_SETUP_IX1___S 0 + +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS (0x00A3C0F8) +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S 15 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_INT_STATUS___S 0 + +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER (0x00A3C0FC) +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S 0 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_EMPTY_COUNTER___S 0 + +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER (0x00A3C100) +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER__MODE___S 0 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_TIMER___S 0 + +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS (0x00A3C104) +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S 16 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S 0 +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF +#define UMAC_TQM_R0_FW2TQM_RING_CONSUMER_PREFETCH_STATUS___S 0 + +#define UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB (0x00A3C108) +#define UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB (0x00A3C10C) +#define UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_TQM_R0_FW2TQM_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_TQM_R0_FW2TQM_RING_MSI1_DATA (0x00A3C110) +#define UMAC_TQM_R0_FW2TQM_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_TQM_R0_FW2TQM_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_TQM_R0_FW2TQM_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_TQM_R0_FW2TQM_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_TQM_R0_FW2TQM_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_TQM_R0_FW2TQM_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_TQM_R0_FW2TQM_RING_MSI1_DATA___S 0 + +#define UMAC_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET (0x00A3C114) +#define UMAC_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_TQM_R0_FW2TQM_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_TQM_R0_SW_CMD_RING_BASE_LSB (0x00A3C118) +#define UMAC_TQM_R0_SW_CMD_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW_CMD_RING_BASE_LSB___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_SW_CMD_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_TQM_R0_SW_CMD_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_SW_CMD_RING_BASE_LSB___S 0 + +#define UMAC_TQM_R0_SW_CMD_RING_BASE_MSB (0x00A3C11C) +#define UMAC_TQM_R0_SW_CMD_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW_CMD_RING_BASE_MSB___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_TQM_R0_SW_CMD_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_TQM_R0_SW_CMD_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_TQM_R0_SW_CMD_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_TQM_R0_SW_CMD_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_TQM_R0_SW_CMD_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_TQM_R0_SW_CMD_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_TQM_R0_SW_CMD_RING_BASE_MSB___S 0 + +#define UMAC_TQM_R0_SW_CMD_RING_ID (0x00A3C120) +#define UMAC_TQM_R0_SW_CMD_RING_ID___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW_CMD_RING_ID___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_TQM_R0_SW_CMD_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_TQM_R0_SW_CMD_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_TQM_R0_SW_CMD_RING_ID___M 0x000000FF +#define UMAC_TQM_R0_SW_CMD_RING_ID___S 0 + +#define UMAC_TQM_R0_SW_CMD_RING_STATUS (0x00A3C124) +#define UMAC_TQM_R0_SW_CMD_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_SW_CMD_RING_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_TQM_R0_SW_CMD_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_TQM_R0_SW_CMD_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_TQM_R0_SW_CMD_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_TQM_R0_SW_CMD_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_TQM_R0_SW_CMD_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_TQM_R0_SW_CMD_RING_STATUS___M 0xFFFFFFFF +#define UMAC_TQM_R0_SW_CMD_RING_STATUS___S 0 + +#define UMAC_TQM_R0_SW_CMD_RING_MISC (0x00A3C128) +#define UMAC_TQM_R0_SW_CMD_RING_MISC___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW_CMD_RING_MISC___POR 0x00000080 +#define UMAC_TQM_R0_SW_CMD_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_TQM_R0_SW_CMD_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_TQM_R0_SW_CMD_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_TQM_R0_SW_CMD_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_TQM_R0_SW_CMD_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_TQM_R0_SW_CMD_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_TQM_R0_SW_CMD_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_TQM_R0_SW_CMD_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_TQM_R0_SW_CMD_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_TQM_R0_SW_CMD_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_TQM_R0_SW_CMD_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_TQM_R0_SW_CMD_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_TQM_R0_SW_CMD_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_TQM_R0_SW_CMD_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_TQM_R0_SW_CMD_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_TQM_R0_SW_CMD_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_TQM_R0_SW_CMD_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_TQM_R0_SW_CMD_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_TQM_R0_SW_CMD_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_TQM_R0_SW_CMD_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_TQM_R0_SW_CMD_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_TQM_R0_SW_CMD_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_TQM_R0_SW_CMD_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_TQM_R0_SW_CMD_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_TQM_R0_SW_CMD_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_TQM_R0_SW_CMD_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_TQM_R0_SW_CMD_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_TQM_R0_SW_CMD_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_TQM_R0_SW_CMD_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_TQM_R0_SW_CMD_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_TQM_R0_SW_CMD_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_TQM_R0_SW_CMD_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_TQM_R0_SW_CMD_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_TQM_R0_SW_CMD_RING_MISC___M 0x003FFFFF +#define UMAC_TQM_R0_SW_CMD_RING_MISC___S 0 + +#define UMAC_TQM_R0_SW_CMD_RING_TP_ADDR_LSB (0x00A3C134) +#define UMAC_TQM_R0_SW_CMD_RING_TP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW_CMD_RING_TP_ADDR_LSB___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_SW_CMD_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S 0 +#define UMAC_TQM_R0_SW_CMD_RING_TP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_SW_CMD_RING_TP_ADDR_LSB___S 0 + +#define UMAC_TQM_R0_SW_CMD_RING_TP_ADDR_MSB (0x00A3C138) +#define UMAC_TQM_R0_SW_CMD_RING_TP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW_CMD_RING_TP_ADDR_MSB___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_TQM_R0_SW_CMD_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_TQM_R0_SW_CMD_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S 0 +#define UMAC_TQM_R0_SW_CMD_RING_TP_ADDR_MSB___M 0x000000FF +#define UMAC_TQM_R0_SW_CMD_RING_TP_ADDR_MSB___S 0 + +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0 (0x00A3C148) +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S 15 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX0___S 0 + +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1 (0x00A3C14C) +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S 0 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_SETUP_IX1___S 0 + +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS (0x00A3C150) +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S 15 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_INT_STATUS___S 0 + +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER (0x00A3C154) +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S 0 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_EMPTY_COUNTER___S 0 + +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER (0x00A3C158) +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER__MODE___S 0 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_TIMER___S 0 + +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS (0x00A3C15C) +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S 16 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S 0 +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF +#define UMAC_TQM_R0_SW_CMD_RING_CONSUMER_PREFETCH_STATUS___S 0 + +#define UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB (0x00A3C160) +#define UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB (0x00A3C164) +#define UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_TQM_R0_SW_CMD_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_TQM_R0_SW_CMD_RING_MSI1_DATA (0x00A3C168) +#define UMAC_TQM_R0_SW_CMD_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW_CMD_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_TQM_R0_SW_CMD_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_TQM_R0_SW_CMD_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_TQM_R0_SW_CMD_RING_MSI1_DATA___S 0 + +#define UMAC_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET (0x00A3C16C) +#define UMAC_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_TQM_R0_SW_CMD_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_TQM_R0_SW_CMD1_RING_BASE_LSB (0x00A3C170) +#define UMAC_TQM_R0_SW_CMD1_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW_CMD1_RING_BASE_LSB___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD1_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD1_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_SW_CMD1_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_TQM_R0_SW_CMD1_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_SW_CMD1_RING_BASE_LSB___S 0 + +#define UMAC_TQM_R0_SW_CMD1_RING_BASE_MSB (0x00A3C174) +#define UMAC_TQM_R0_SW_CMD1_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW_CMD1_RING_BASE_MSB___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD1_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_TQM_R0_SW_CMD1_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_TQM_R0_SW_CMD1_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_TQM_R0_SW_CMD1_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_TQM_R0_SW_CMD1_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_TQM_R0_SW_CMD1_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_TQM_R0_SW_CMD1_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_TQM_R0_SW_CMD1_RING_BASE_MSB___S 0 + +#define UMAC_TQM_R0_SW_CMD1_RING_ID (0x00A3C178) +#define UMAC_TQM_R0_SW_CMD1_RING_ID___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW_CMD1_RING_ID___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD1_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_TQM_R0_SW_CMD1_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_TQM_R0_SW_CMD1_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_TQM_R0_SW_CMD1_RING_ID___M 0x000000FF +#define UMAC_TQM_R0_SW_CMD1_RING_ID___S 0 + +#define UMAC_TQM_R0_SW_CMD1_RING_STATUS (0x00A3C17C) +#define UMAC_TQM_R0_SW_CMD1_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_SW_CMD1_RING_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD1_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_TQM_R0_SW_CMD1_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_TQM_R0_SW_CMD1_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_TQM_R0_SW_CMD1_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_TQM_R0_SW_CMD1_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_TQM_R0_SW_CMD1_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_TQM_R0_SW_CMD1_RING_STATUS___M 0xFFFFFFFF +#define UMAC_TQM_R0_SW_CMD1_RING_STATUS___S 0 + +#define UMAC_TQM_R0_SW_CMD1_RING_MISC (0x00A3C180) +#define UMAC_TQM_R0_SW_CMD1_RING_MISC___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW_CMD1_RING_MISC___POR 0x00000080 +#define UMAC_TQM_R0_SW_CMD1_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_TQM_R0_SW_CMD1_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_TQM_R0_SW_CMD1_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_TQM_R0_SW_CMD1_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_TQM_R0_SW_CMD1_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_TQM_R0_SW_CMD1_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_TQM_R0_SW_CMD1_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_TQM_R0_SW_CMD1_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_TQM_R0_SW_CMD1_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_TQM_R0_SW_CMD1_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_TQM_R0_SW_CMD1_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_TQM_R0_SW_CMD1_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_TQM_R0_SW_CMD1_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_TQM_R0_SW_CMD1_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_TQM_R0_SW_CMD1_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_TQM_R0_SW_CMD1_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_TQM_R0_SW_CMD1_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_TQM_R0_SW_CMD1_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_TQM_R0_SW_CMD1_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_TQM_R0_SW_CMD1_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_TQM_R0_SW_CMD1_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_TQM_R0_SW_CMD1_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_TQM_R0_SW_CMD1_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_TQM_R0_SW_CMD1_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_TQM_R0_SW_CMD1_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_TQM_R0_SW_CMD1_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_TQM_R0_SW_CMD1_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_TQM_R0_SW_CMD1_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_TQM_R0_SW_CMD1_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_TQM_R0_SW_CMD1_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_TQM_R0_SW_CMD1_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_TQM_R0_SW_CMD1_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_TQM_R0_SW_CMD1_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_TQM_R0_SW_CMD1_RING_MISC___M 0x003FFFFF +#define UMAC_TQM_R0_SW_CMD1_RING_MISC___S 0 + +#define UMAC_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB (0x00A3C18C) +#define UMAC_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S 0 +#define UMAC_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_SW_CMD1_RING_TP_ADDR_LSB___S 0 + +#define UMAC_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB (0x00A3C190) +#define UMAC_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S 0 +#define UMAC_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB___M 0x000000FF +#define UMAC_TQM_R0_SW_CMD1_RING_TP_ADDR_MSB___S 0 + +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0 (0x00A3C1A0) +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S 15 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX0___S 0 + +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1 (0x00A3C1A4) +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S 0 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_SETUP_IX1___S 0 + +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS (0x00A3C1A8) +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S 15 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_INT_STATUS___S 0 + +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER (0x00A3C1AC) +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S 0 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_EMPTY_COUNTER___S 0 + +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER (0x00A3C1B0) +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER__MODE___S 0 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_TIMER___S 0 + +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS (0x00A3C1B4) +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S 16 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S 0 +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF +#define UMAC_TQM_R0_SW_CMD1_RING_CONSUMER_PREFETCH_STATUS___S 0 + +#define UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB (0x00A3C1B8) +#define UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB (0x00A3C1BC) +#define UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_TQM_R0_SW_CMD1_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_TQM_R0_SW_CMD1_RING_MSI1_DATA (0x00A3C1C0) +#define UMAC_TQM_R0_SW_CMD1_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW_CMD1_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD1_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD1_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_TQM_R0_SW_CMD1_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_TQM_R0_SW_CMD1_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_TQM_R0_SW_CMD1_RING_MSI1_DATA___S 0 + +#define UMAC_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET (0x00A3C1C4) +#define UMAC_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_TQM_R0_SW_CMD1_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_TQM_R0_SCH2TQM0_RING_BASE_LSB (0x00A3C1C8) +#define UMAC_TQM_R0_SCH2TQM0_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SCH2TQM0_RING_BASE_LSB___POR 0x00000000 +#define UMAC_TQM_R0_SCH2TQM0_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_TQM_R0_SCH2TQM0_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_SCH2TQM0_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_TQM_R0_SCH2TQM0_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_SCH2TQM0_RING_BASE_LSB___S 0 + +#define UMAC_TQM_R0_SCH2TQM0_RING_BASE_MSB (0x00A3C1CC) +#define UMAC_TQM_R0_SCH2TQM0_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SCH2TQM0_RING_BASE_MSB___POR 0x00000000 +#define UMAC_TQM_R0_SCH2TQM0_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_TQM_R0_SCH2TQM0_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_TQM_R0_SCH2TQM0_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_TQM_R0_SCH2TQM0_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_TQM_R0_SCH2TQM0_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_TQM_R0_SCH2TQM0_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_TQM_R0_SCH2TQM0_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_TQM_R0_SCH2TQM0_RING_BASE_MSB___S 0 + +#define UMAC_TQM_R0_SCH2TQM0_RING_ID (0x00A3C1D0) +#define UMAC_TQM_R0_SCH2TQM0_RING_ID___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SCH2TQM0_RING_ID___POR 0x00000000 +#define UMAC_TQM_R0_SCH2TQM0_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_TQM_R0_SCH2TQM0_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_TQM_R0_SCH2TQM0_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_TQM_R0_SCH2TQM0_RING_ID___M 0x000000FF +#define UMAC_TQM_R0_SCH2TQM0_RING_ID___S 0 + +#define UMAC_TQM_R0_SCH2TQM0_RING_STATUS (0x00A3C1D4) +#define UMAC_TQM_R0_SCH2TQM0_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_SCH2TQM0_RING_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_SCH2TQM0_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_TQM_R0_SCH2TQM0_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_TQM_R0_SCH2TQM0_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_TQM_R0_SCH2TQM0_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_TQM_R0_SCH2TQM0_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_TQM_R0_SCH2TQM0_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_TQM_R0_SCH2TQM0_RING_STATUS___M 0xFFFFFFFF +#define UMAC_TQM_R0_SCH2TQM0_RING_STATUS___S 0 + +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC (0x00A3C1D8) +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC___POR 0x00000080 +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC___M 0x003FFFFF +#define UMAC_TQM_R0_SCH2TQM0_RING_MISC___S 0 + +#define UMAC_TQM_R0_SCH2TQM0_RING_TP_ADDR_LSB (0x00A3C1E4) +#define UMAC_TQM_R0_SCH2TQM0_RING_TP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SCH2TQM0_RING_TP_ADDR_LSB___POR 0x00000000 +#define UMAC_TQM_R0_SCH2TQM0_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_TQM_R0_SCH2TQM0_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_SCH2TQM0_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S 0 +#define UMAC_TQM_R0_SCH2TQM0_RING_TP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_SCH2TQM0_RING_TP_ADDR_LSB___S 0 + +#define UMAC_TQM_R0_SCH2TQM0_RING_TP_ADDR_MSB (0x00A3C1E8) +#define UMAC_TQM_R0_SCH2TQM0_RING_TP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SCH2TQM0_RING_TP_ADDR_MSB___POR 0x00000000 +#define UMAC_TQM_R0_SCH2TQM0_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_TQM_R0_SCH2TQM0_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_TQM_R0_SCH2TQM0_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S 0 +#define UMAC_TQM_R0_SCH2TQM0_RING_TP_ADDR_MSB___M 0x000000FF +#define UMAC_TQM_R0_SCH2TQM0_RING_TP_ADDR_MSB___S 0 + +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX0 (0x00A3C1F8) +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S 15 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX0___S 0 + +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX1 (0x00A3C1FC) +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S 0 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_SETUP_IX1___S 0 + +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_STATUS (0x00A3C200) +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S 15 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_INT_STATUS___S 0 + +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_EMPTY_COUNTER (0x00A3C204) +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S 0 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_EMPTY_COUNTER___S 0 + +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_TIMER (0x00A3C208) +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_TIMER__MODE___S 0 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_TIMER___S 0 + +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_STATUS (0x00A3C20C) +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S 16 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S 0 +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF +#define UMAC_TQM_R0_SCH2TQM0_RING_CONSUMER_PREFETCH_STATUS___S 0 + +#define UMAC_TQM_R0_SCH2TQM0_RING_HP_TP_SW_OFFSET (0x00A3C21C) +#define UMAC_TQM_R0_SCH2TQM0_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SCH2TQM0_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_TQM_R0_SCH2TQM0_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_TQM_R0_SCH2TQM0_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_TQM_R0_SCH2TQM0_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_TQM_R0_SCH2TQM0_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_TQM_R0_SCH2TQM0_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB (0x00A3C2D0) +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB___POR 0x00000000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_LSB___S 0 + +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB (0x00A3C2D4) +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB___POR 0x00000000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_BASE_MSB___S 0 + +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_ID (0x00A3C2D8) +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_ID___RWC QCSR_REG_RW +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_ID___POR 0x00000000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_ID___M 0x000000FF +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_ID___S 0 + +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_STATUS (0x00A3C2DC) +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_STATUS___M 0xFFFFFFFF +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_STATUS___S 0 + +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC (0x00A3C2E0) +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC___RWC QCSR_REG_RW +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC___POR 0x00000080 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC___M 0x003FFFFF +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MISC___S 0 + +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB (0x00A3C2EC) +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB___POR 0x00000000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S 0 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_LSB___S 0 + +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB (0x00A3C2F0) +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB___POR 0x00000000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S 0 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB___M 0x000000FF +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_TP_ADDR_MSB___S 0 + +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0 (0x00A3C300) +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S 15 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX0___S 0 + +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1 (0x00A3C304) +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S 0 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_SETUP_IX1___S 0 + +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS (0x00A3C308) +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S 15 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_INT_STATUS___S 0 + +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER (0x00A3C30C) +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S 0 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_EMPTY_COUNTER___S 0 + +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER (0x00A3C310) +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER__MODE___S 0 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_TIMER___S 0 + +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS (0x00A3C314) +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S 16 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S 0 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_CONSUMER_PREFETCH_STATUS___S 0 + +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB (0x00A3C318) +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB (0x00A3C31C) +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA (0x00A3C320) +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_MSI1_DATA___S 0 + +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET (0x00A3C324) +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_TQM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_TQM_R0_TQM_RELEASE_RING_BASE_LSB (0x00A3C328) +#define UMAC_TQM_R0_TQM_RELEASE_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_RELEASE_RING_BASE_LSB___POR 0x00000000 +#define UMAC_TQM_R0_TQM_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_TQM_R0_TQM_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_TQM_R0_TQM_RELEASE_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_RELEASE_RING_BASE_LSB___S 0 + +#define UMAC_TQM_R0_TQM_RELEASE_RING_BASE_MSB (0x00A3C32C) +#define UMAC_TQM_R0_TQM_RELEASE_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_RELEASE_RING_BASE_MSB___POR 0x00000000 +#define UMAC_TQM_R0_TQM_RELEASE_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_TQM_R0_TQM_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_TQM_R0_TQM_RELEASE_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_TQM_R0_TQM_RELEASE_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_TQM_R0_TQM_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_TQM_R0_TQM_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_TQM_R0_TQM_RELEASE_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_TQM_R0_TQM_RELEASE_RING_BASE_MSB___S 0 + +#define UMAC_TQM_R0_TQM_RELEASE_RING_ID (0x00A3C330) +#define UMAC_TQM_R0_TQM_RELEASE_RING_ID___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_RELEASE_RING_ID___POR 0x00000000 +#define UMAC_TQM_R0_TQM_RELEASE_RING_ID__RING_ID___POR 0x00 +#define UMAC_TQM_R0_TQM_RELEASE_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_TQM_R0_TQM_RELEASE_RING_ID__RING_ID___M 0x0000FF00 +#define UMAC_TQM_R0_TQM_RELEASE_RING_ID__RING_ID___S 8 +#define UMAC_TQM_R0_TQM_RELEASE_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_TQM_R0_TQM_RELEASE_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_TQM_R0_TQM_RELEASE_RING_ID___M 0x0000FFFF +#define UMAC_TQM_R0_TQM_RELEASE_RING_ID___S 0 + +#define UMAC_TQM_R0_TQM_RELEASE_RING_STATUS (0x00A3C334) +#define UMAC_TQM_R0_TQM_RELEASE_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_TQM_RELEASE_RING_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_TQM_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_TQM_R0_TQM_RELEASE_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_TQM_R0_TQM_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_TQM_R0_TQM_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_TQM_R0_TQM_RELEASE_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_TQM_R0_TQM_RELEASE_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_TQM_R0_TQM_RELEASE_RING_STATUS___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_RELEASE_RING_STATUS___S 0 + +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC (0x00A3C338) +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC___POR 0x00000080 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__LOOP_CNT___POR 0x0 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__LOOP_CNT___M 0x03C00000 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__LOOP_CNT___S 22 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC___M 0x03FFFFFF +#define UMAC_TQM_R0_TQM_RELEASE_RING_MISC___S 0 + +#define UMAC_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB (0x00A3C33C) +#define UMAC_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB___POR 0x00000000 +#define UMAC_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define UMAC_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_RELEASE_RING_HP_ADDR_LSB___S 0 + +#define UMAC_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB (0x00A3C340) +#define UMAC_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB___POR 0x00000000 +#define UMAC_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define UMAC_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB___M 0x000000FF +#define UMAC_TQM_R0_TQM_RELEASE_RING_HP_ADDR_MSB___S 0 + +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP (0x00A3C34C) +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_SETUP___S 0 + +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS (0x00A3C350) +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_INT_STATUS___S 0 + +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER (0x00A3C354) +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define UMAC_TQM_R0_TQM_RELEASE_RING_PRODUCER_FULL_COUNTER___S 0 + +#define UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB (0x00A3C370) +#define UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB (0x00A3C374) +#define UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_DATA (0x00A3C378) +#define UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_RELEASE_RING_MSI1_DATA___S 0 + +#define UMAC_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET (0x00A3C37C) +#define UMAC_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_TQM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_TQM_R0_TQM_STATUS_RING_BASE_LSB (0x00A3C380) +#define UMAC_TQM_R0_TQM_STATUS_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_STATUS_RING_BASE_LSB___POR 0x00000000 +#define UMAC_TQM_R0_TQM_STATUS_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_TQM_R0_TQM_STATUS_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_STATUS_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_TQM_R0_TQM_STATUS_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_STATUS_RING_BASE_LSB___S 0 + +#define UMAC_TQM_R0_TQM_STATUS_RING_BASE_MSB (0x00A3C384) +#define UMAC_TQM_R0_TQM_STATUS_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_STATUS_RING_BASE_MSB___POR 0x00000000 +#define UMAC_TQM_R0_TQM_STATUS_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_TQM_R0_TQM_STATUS_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_TQM_R0_TQM_STATUS_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_TQM_R0_TQM_STATUS_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_TQM_R0_TQM_STATUS_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_TQM_R0_TQM_STATUS_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_TQM_R0_TQM_STATUS_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_TQM_R0_TQM_STATUS_RING_BASE_MSB___S 0 + +#define UMAC_TQM_R0_TQM_STATUS_RING_ID (0x00A3C388) +#define UMAC_TQM_R0_TQM_STATUS_RING_ID___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_STATUS_RING_ID___POR 0x00000000 +#define UMAC_TQM_R0_TQM_STATUS_RING_ID__RING_ID___POR 0x00 +#define UMAC_TQM_R0_TQM_STATUS_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_TQM_R0_TQM_STATUS_RING_ID__RING_ID___M 0x0000FF00 +#define UMAC_TQM_R0_TQM_STATUS_RING_ID__RING_ID___S 8 +#define UMAC_TQM_R0_TQM_STATUS_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_TQM_R0_TQM_STATUS_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_TQM_R0_TQM_STATUS_RING_ID___M 0x0000FFFF +#define UMAC_TQM_R0_TQM_STATUS_RING_ID___S 0 + +#define UMAC_TQM_R0_TQM_STATUS_RING_STATUS (0x00A3C38C) +#define UMAC_TQM_R0_TQM_STATUS_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_TQM_STATUS_RING_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_TQM_STATUS_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_TQM_R0_TQM_STATUS_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_TQM_R0_TQM_STATUS_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_TQM_R0_TQM_STATUS_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_TQM_R0_TQM_STATUS_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_TQM_R0_TQM_STATUS_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_TQM_R0_TQM_STATUS_RING_STATUS___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_STATUS_RING_STATUS___S 0 + +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC (0x00A3C390) +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC___POR 0x00000080 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__LOOP_CNT___POR 0x0 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__LOOP_CNT___M 0x03C00000 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__LOOP_CNT___S 22 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC___M 0x03FFFFFF +#define UMAC_TQM_R0_TQM_STATUS_RING_MISC___S 0 + +#define UMAC_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB (0x00A3C394) +#define UMAC_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB___POR 0x00000000 +#define UMAC_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define UMAC_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_STATUS_RING_HP_ADDR_LSB___S 0 + +#define UMAC_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB (0x00A3C398) +#define UMAC_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB___POR 0x00000000 +#define UMAC_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define UMAC_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB___M 0x000000FF +#define UMAC_TQM_R0_TQM_STATUS_RING_HP_ADDR_MSB___S 0 + +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP (0x00A3C3A4) +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_SETUP___S 0 + +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS (0x00A3C3A8) +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_INT_STATUS___S 0 + +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER (0x00A3C3AC) +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define UMAC_TQM_R0_TQM_STATUS_RING_PRODUCER_FULL_COUNTER___S 0 + +#define UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB (0x00A3C3C8) +#define UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB (0x00A3C3CC) +#define UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_TQM_R0_TQM_STATUS_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_TQM_R0_TQM_STATUS_RING_MSI1_DATA (0x00A3C3D0) +#define UMAC_TQM_R0_TQM_STATUS_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_STATUS_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_TQM_R0_TQM_STATUS_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_TQM_R0_TQM_STATUS_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_STATUS_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_TQM_R0_TQM_STATUS_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_STATUS_RING_MSI1_DATA___S 0 + +#define UMAC_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET (0x00A3C3D4) +#define UMAC_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_TQM_R0_TQM_STATUS_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_TQM_R0_TQM_STATUS1_RING_BASE_LSB (0x00A3C3D8) +#define UMAC_TQM_R0_TQM_STATUS1_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_STATUS1_RING_BASE_LSB___POR 0x00000000 +#define UMAC_TQM_R0_TQM_STATUS1_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_TQM_R0_TQM_STATUS1_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_STATUS1_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_TQM_R0_TQM_STATUS1_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_STATUS1_RING_BASE_LSB___S 0 + +#define UMAC_TQM_R0_TQM_STATUS1_RING_BASE_MSB (0x00A3C3DC) +#define UMAC_TQM_R0_TQM_STATUS1_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_STATUS1_RING_BASE_MSB___POR 0x00000000 +#define UMAC_TQM_R0_TQM_STATUS1_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_TQM_R0_TQM_STATUS1_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_TQM_R0_TQM_STATUS1_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_TQM_R0_TQM_STATUS1_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_TQM_R0_TQM_STATUS1_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_TQM_R0_TQM_STATUS1_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_TQM_R0_TQM_STATUS1_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_TQM_R0_TQM_STATUS1_RING_BASE_MSB___S 0 + +#define UMAC_TQM_R0_TQM_STATUS1_RING_ID (0x00A3C3E0) +#define UMAC_TQM_R0_TQM_STATUS1_RING_ID___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_STATUS1_RING_ID___POR 0x00000000 +#define UMAC_TQM_R0_TQM_STATUS1_RING_ID__RING_ID___POR 0x00 +#define UMAC_TQM_R0_TQM_STATUS1_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_TQM_R0_TQM_STATUS1_RING_ID__RING_ID___M 0x0000FF00 +#define UMAC_TQM_R0_TQM_STATUS1_RING_ID__RING_ID___S 8 +#define UMAC_TQM_R0_TQM_STATUS1_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_TQM_R0_TQM_STATUS1_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_TQM_R0_TQM_STATUS1_RING_ID___M 0x0000FFFF +#define UMAC_TQM_R0_TQM_STATUS1_RING_ID___S 0 + +#define UMAC_TQM_R0_TQM_STATUS1_RING_STATUS (0x00A3C3E4) +#define UMAC_TQM_R0_TQM_STATUS1_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_TQM_STATUS1_RING_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_TQM_STATUS1_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_TQM_R0_TQM_STATUS1_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_TQM_R0_TQM_STATUS1_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_TQM_R0_TQM_STATUS1_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_TQM_R0_TQM_STATUS1_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_TQM_R0_TQM_STATUS1_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_TQM_R0_TQM_STATUS1_RING_STATUS___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_STATUS1_RING_STATUS___S 0 + +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC (0x00A3C3E8) +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC___POR 0x00000080 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__LOOP_CNT___POR 0x0 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__LOOP_CNT___M 0x03C00000 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__LOOP_CNT___S 22 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC___M 0x03FFFFFF +#define UMAC_TQM_R0_TQM_STATUS1_RING_MISC___S 0 + +#define UMAC_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB (0x00A3C3EC) +#define UMAC_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB___POR 0x00000000 +#define UMAC_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define UMAC_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_STATUS1_RING_HP_ADDR_LSB___S 0 + +#define UMAC_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB (0x00A3C3F0) +#define UMAC_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB___POR 0x00000000 +#define UMAC_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define UMAC_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB___M 0x000000FF +#define UMAC_TQM_R0_TQM_STATUS1_RING_HP_ADDR_MSB___S 0 + +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP (0x00A3C3FC) +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_SETUP___S 0 + +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS (0x00A3C400) +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_INT_STATUS___S 0 + +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER (0x00A3C404) +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define UMAC_TQM_R0_TQM_STATUS1_RING_PRODUCER_FULL_COUNTER___S 0 + +#define UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB (0x00A3C420) +#define UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB (0x00A3C424) +#define UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_DATA (0x00A3C428) +#define UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_STATUS1_RING_MSI1_DATA___S 0 + +#define UMAC_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET (0x00A3C42C) +#define UMAC_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_TQM_R0_TQM_STATUS1_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_TQM_R0_GXI_TESTBUS_LOWER (0x00A3C430) +#define UMAC_TQM_R0_GXI_TESTBUS_LOWER___RWC QCSR_REG_RO +#define UMAC_TQM_R0_GXI_TESTBUS_LOWER___POR 0x00000000 +#define UMAC_TQM_R0_GXI_TESTBUS_LOWER__VALUE___POR 0x00000000 +#define UMAC_TQM_R0_GXI_TESTBUS_LOWER__VALUE___M 0xFFFFFFFF +#define UMAC_TQM_R0_GXI_TESTBUS_LOWER__VALUE___S 0 +#define UMAC_TQM_R0_GXI_TESTBUS_LOWER___M 0xFFFFFFFF +#define UMAC_TQM_R0_GXI_TESTBUS_LOWER___S 0 + +#define UMAC_TQM_R0_GXI_TESTBUS_UPPER (0x00A3C434) +#define UMAC_TQM_R0_GXI_TESTBUS_UPPER___RWC QCSR_REG_RO +#define UMAC_TQM_R0_GXI_TESTBUS_UPPER___POR 0x00000000 +#define UMAC_TQM_R0_GXI_TESTBUS_UPPER__VALUE___POR 0x00 +#define UMAC_TQM_R0_GXI_TESTBUS_UPPER__VALUE___M 0x000000FF +#define UMAC_TQM_R0_GXI_TESTBUS_UPPER__VALUE___S 0 +#define UMAC_TQM_R0_GXI_TESTBUS_UPPER___M 0x000000FF +#define UMAC_TQM_R0_GXI_TESTBUS_UPPER___S 0 + +#define UMAC_TQM_R0_GXI_SM_STATES_IX_0 (0x00A3C438) +#define UMAC_TQM_R0_GXI_SM_STATES_IX_0___RWC QCSR_REG_RO +#define UMAC_TQM_R0_GXI_SM_STATES_IX_0___POR 0x00000211 +#define UMAC_TQM_R0_GXI_SM_STATES_IX_0__SM_STATE_RD_ADDR___POR 0x1 +#define UMAC_TQM_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_ADDR___POR 0x01 +#define UMAC_TQM_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_DATA___POR 0x1 +#define UMAC_TQM_R0_GXI_SM_STATES_IX_0__SM_STATE_RD_ADDR___M 0x00000E00 +#define UMAC_TQM_R0_GXI_SM_STATES_IX_0__SM_STATE_RD_ADDR___S 9 +#define UMAC_TQM_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_ADDR___M 0x000001F0 +#define UMAC_TQM_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_ADDR___S 4 +#define UMAC_TQM_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_DATA___M 0x0000000F +#define UMAC_TQM_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_DATA___S 0 +#define UMAC_TQM_R0_GXI_SM_STATES_IX_0___M 0x00000FFF +#define UMAC_TQM_R0_GXI_SM_STATES_IX_0___S 0 + +#define UMAC_TQM_R0_GXI_END_OF_TEST_CHECK (0x00A3C43C) +#define UMAC_TQM_R0_GXI_END_OF_TEST_CHECK___RWC QCSR_REG_RW +#define UMAC_TQM_R0_GXI_END_OF_TEST_CHECK___POR 0x00000000 +#define UMAC_TQM_R0_GXI_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0 +#define UMAC_TQM_R0_GXI_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001 +#define UMAC_TQM_R0_GXI_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S 0 +#define UMAC_TQM_R0_GXI_END_OF_TEST_CHECK___M 0x00000001 +#define UMAC_TQM_R0_GXI_END_OF_TEST_CHECK___S 0 + +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE (0x00A3C440) +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE___RWC QCSR_REG_RW +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE___POR 0x00000000 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___POR 0x0 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__SPARE___POR 0x0 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WDOG_CTR___POR 0x0 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__RD_FIFO___POR 0x0 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_FIFO___POR 0x0 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_FIFO___POR 0x0 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__RD_AXI_MAS___POR 0x0 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_AXI_MAS___POR 0x0 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_AXI_MAS___POR 0x0 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_CMD___POR 0x0 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_CMD___POR 0x0 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__RD_CMD___POR 0x0 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__CORE___POR 0x0 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___M 0x80000000 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___S 31 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__SPARE___M 0x00000800 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__SPARE___S 11 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WDOG_CTR___M 0x00000400 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WDOG_CTR___S 10 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__RD_FIFO___M 0x00000200 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__RD_FIFO___S 9 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_FIFO___M 0x00000100 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_FIFO___S 8 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_FIFO___M 0x00000080 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_FIFO___S 7 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__RD_AXI_MAS___M 0x00000040 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__RD_AXI_MAS___S 6 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_AXI_MAS___M 0x00000020 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_AXI_MAS___S 5 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_AXI_MAS___M 0x00000010 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_AXI_MAS___S 4 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_CMD___M 0x00000008 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_CMD___S 3 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_CMD___M 0x00000004 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_CMD___S 2 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__RD_CMD___M 0x00000002 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__RD_CMD___S 1 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__CORE___M 0x00000001 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE__CORE___S 0 +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE___M 0x80000FFF +#define UMAC_TQM_R0_GXI_CLOCK_GATE_DISABLE___S 0 + +#define UMAC_TQM_R0_GXI_GXI_ERR_INTS (0x00A3C444) +#define UMAC_TQM_R0_GXI_GXI_ERR_INTS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_GXI_GXI_ERR_INTS___POR 0x00000000 +#define UMAC_TQM_R0_GXI_GXI_ERR_INTS__GXI_WR_LAST_ERR_INT___POR 0x0 +#define UMAC_TQM_R0_GXI_GXI_ERR_INTS__GXI_AXI_WR_ERR_INT___POR 0x0 +#define UMAC_TQM_R0_GXI_GXI_ERR_INTS__GXI_AXI_RD_ERR_INT___POR 0x0 +#define UMAC_TQM_R0_GXI_GXI_ERR_INTS__GXI_WDTIMEOUT_INT___POR 0x0 +#define UMAC_TQM_R0_GXI_GXI_ERR_INTS__GXI_WR_LAST_ERR_INT___M 0x01000000 +#define UMAC_TQM_R0_GXI_GXI_ERR_INTS__GXI_WR_LAST_ERR_INT___S 24 +#define UMAC_TQM_R0_GXI_GXI_ERR_INTS__GXI_AXI_WR_ERR_INT___M 0x00010000 +#define UMAC_TQM_R0_GXI_GXI_ERR_INTS__GXI_AXI_WR_ERR_INT___S 16 +#define UMAC_TQM_R0_GXI_GXI_ERR_INTS__GXI_AXI_RD_ERR_INT___M 0x00000100 +#define UMAC_TQM_R0_GXI_GXI_ERR_INTS__GXI_AXI_RD_ERR_INT___S 8 +#define UMAC_TQM_R0_GXI_GXI_ERR_INTS__GXI_WDTIMEOUT_INT___M 0x00000001 +#define UMAC_TQM_R0_GXI_GXI_ERR_INTS__GXI_WDTIMEOUT_INT___S 0 +#define UMAC_TQM_R0_GXI_GXI_ERR_INTS___M 0x01010101 +#define UMAC_TQM_R0_GXI_GXI_ERR_INTS___S 0 + +#define UMAC_TQM_R0_GXI_GXI_ERR_STATS (0x00A3C448) +#define UMAC_TQM_R0_GXI_GXI_ERR_STATS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_GXI_GXI_ERR_STATS___POR 0x00000000 +#define UMAC_TQM_R0_GXI_GXI_ERR_STATS__AXI_WR_LAST_ERR_PORT___POR 0x00 +#define UMAC_TQM_R0_GXI_GXI_ERR_STATS__AXI_WR_ERR_PORT___POR 0x00 +#define UMAC_TQM_R0_GXI_GXI_ERR_STATS__AXI_RD_ERR_PORT___POR 0x00 +#define UMAC_TQM_R0_GXI_GXI_ERR_STATS__AXI_WR_LAST_ERR_PORT___M 0x003F0000 +#define UMAC_TQM_R0_GXI_GXI_ERR_STATS__AXI_WR_LAST_ERR_PORT___S 16 +#define UMAC_TQM_R0_GXI_GXI_ERR_STATS__AXI_WR_ERR_PORT___M 0x00003F00 +#define UMAC_TQM_R0_GXI_GXI_ERR_STATS__AXI_WR_ERR_PORT___S 8 +#define UMAC_TQM_R0_GXI_GXI_ERR_STATS__AXI_RD_ERR_PORT___M 0x0000003F +#define UMAC_TQM_R0_GXI_GXI_ERR_STATS__AXI_RD_ERR_PORT___S 0 +#define UMAC_TQM_R0_GXI_GXI_ERR_STATS___M 0x003F3F3F +#define UMAC_TQM_R0_GXI_GXI_ERR_STATS___S 0 + +#define UMAC_TQM_R0_GXI_GXI_DEFAULT_CONTROL (0x00A3C44C) +#define UMAC_TQM_R0_GXI_GXI_DEFAULT_CONTROL___RWC QCSR_REG_RW +#define UMAC_TQM_R0_GXI_GXI_DEFAULT_CONTROL___POR 0x00000000 +#define UMAC_TQM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READ_DATA___POR 0x00 +#define UMAC_TQM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITE_DATA___POR 0x00 +#define UMAC_TQM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READS___POR 0x00 +#define UMAC_TQM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITES___POR 0x00 +#define UMAC_TQM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READ_DATA___M 0xFF000000 +#define UMAC_TQM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READ_DATA___S 24 +#define UMAC_TQM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITE_DATA___M 0x00FF0000 +#define UMAC_TQM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITE_DATA___S 16 +#define UMAC_TQM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READS___M 0x00003F00 +#define UMAC_TQM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READS___S 8 +#define UMAC_TQM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITES___M 0x0000003F +#define UMAC_TQM_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITES___S 0 +#define UMAC_TQM_R0_GXI_GXI_DEFAULT_CONTROL___M 0xFFFF3F3F +#define UMAC_TQM_R0_GXI_GXI_DEFAULT_CONTROL___S 0 + +#define UMAC_TQM_R0_GXI_GXI_REDUCED_CONTROL (0x00A3C450) +#define UMAC_TQM_R0_GXI_GXI_REDUCED_CONTROL___RWC QCSR_REG_RW +#define UMAC_TQM_R0_GXI_GXI_REDUCED_CONTROL___POR 0x00000000 +#define UMAC_TQM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READ_DATA___POR 0x00 +#define UMAC_TQM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITE_DATA___POR 0x00 +#define UMAC_TQM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READS___POR 0x00 +#define UMAC_TQM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITES___POR 0x00 +#define UMAC_TQM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READ_DATA___M 0xFF000000 +#define UMAC_TQM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READ_DATA___S 24 +#define UMAC_TQM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITE_DATA___M 0x00FF0000 +#define UMAC_TQM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITE_DATA___S 16 +#define UMAC_TQM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READS___M 0x00003F00 +#define UMAC_TQM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READS___S 8 +#define UMAC_TQM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITES___M 0x0000003F +#define UMAC_TQM_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITES___S 0 +#define UMAC_TQM_R0_GXI_GXI_REDUCED_CONTROL___M 0xFFFF3F3F +#define UMAC_TQM_R0_GXI_GXI_REDUCED_CONTROL___S 0 + +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL (0x00A3C454) +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL___RWC QCSR_REG_RW +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL___POR 0x00240000 +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_RD_FLUSH___POR 0x0 +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_WR_FLUSH___POR 0x0 +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_DISABLE_WR_PREFIL___POR 0x0 +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_WR_BOUNDARY_SPLIT___POR 0x0 +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_RD_BOUNDARY_SPLIT___POR 0x0 +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_BURST_SIZE___POR 0x2 +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_READ_BURST_SIZE___POR 0x2 +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_READ_ISSUE_THRESHOLD___POR 0x00 +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_PREFETCH_THRESHOLD___POR 0x00 +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_CLEAR_STATS___POR 0x0 +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_RD_FLUSH___M 0x08000000 +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_RD_FLUSH___S 27 +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_WR_FLUSH___M 0x04000000 +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_WR_FLUSH___S 26 +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_DISABLE_WR_PREFIL___M 0x02000000 +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_DISABLE_WR_PREFIL___S 25 +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_WR_BOUNDARY_SPLIT___M 0x01000000 +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_WR_BOUNDARY_SPLIT___S 24 +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_RD_BOUNDARY_SPLIT___M 0x00800000 +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_RD_BOUNDARY_SPLIT___S 23 +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_BURST_SIZE___M 0x00700000 +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_BURST_SIZE___S 20 +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_READ_BURST_SIZE___M 0x000E0000 +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_READ_BURST_SIZE___S 17 +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_READ_ISSUE_THRESHOLD___M 0x0001FE00 +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_READ_ISSUE_THRESHOLD___S 9 +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_PREFETCH_THRESHOLD___M 0x000001FE +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_PREFETCH_THRESHOLD___S 1 +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_CLEAR_STATS___M 0x00000001 +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL__GXI_CLEAR_STATS___S 0 +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL___M 0x0FFFFFFF +#define UMAC_TQM_R0_GXI_GXI_MISC_CONTROL___S 0 + +#define UMAC_TQM_R0_GXI_GXI_WDOG_CONTROL (0x00A3C458) +#define UMAC_TQM_R0_GXI_GXI_WDOG_CONTROL___RWC QCSR_REG_RW +#define UMAC_TQM_R0_GXI_GXI_WDOG_CONTROL___POR 0x00FF0000 +#define UMAC_TQM_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_LIMIT___POR 0x00FF +#define UMAC_TQM_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_DISABLE___POR 0x0 +#define UMAC_TQM_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_LIMIT___M 0xFFFF0000 +#define UMAC_TQM_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_LIMIT___S 16 +#define UMAC_TQM_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_DISABLE___M 0x00000001 +#define UMAC_TQM_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_DISABLE___S 0 +#define UMAC_TQM_R0_GXI_GXI_WDOG_CONTROL___M 0xFFFF0001 +#define UMAC_TQM_R0_GXI_GXI_WDOG_CONTROL___S 0 + +#define UMAC_TQM_R0_GXI_GXI_WDOG_STATUS (0x00A3C45C) +#define UMAC_TQM_R0_GXI_GXI_WDOG_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_GXI_GXI_WDOG_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_GXI_GXI_WDOG_STATUS__GXI_WDOG_STATUS___POR 0x0000 +#define UMAC_TQM_R0_GXI_GXI_WDOG_STATUS__GXI_WDOG_STATUS___M 0x0000FFFF +#define UMAC_TQM_R0_GXI_GXI_WDOG_STATUS__GXI_WDOG_STATUS___S 0 +#define UMAC_TQM_R0_GXI_GXI_WDOG_STATUS___M 0x0000FFFF +#define UMAC_TQM_R0_GXI_GXI_WDOG_STATUS___S 0 + +#define UMAC_TQM_R0_GXI_GXI_IDLE_COUNTERS (0x00A3C460) +#define UMAC_TQM_R0_GXI_GXI_IDLE_COUNTERS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_GXI_GXI_IDLE_COUNTERS___POR 0x00000000 +#define UMAC_TQM_R0_GXI_GXI_IDLE_COUNTERS__GXI_READ_IDLE_CNT___POR 0x0000 +#define UMAC_TQM_R0_GXI_GXI_IDLE_COUNTERS__GXI_WRITE_IDLE_CNT___POR 0x0000 +#define UMAC_TQM_R0_GXI_GXI_IDLE_COUNTERS__GXI_READ_IDLE_CNT___M 0xFFFF0000 +#define UMAC_TQM_R0_GXI_GXI_IDLE_COUNTERS__GXI_READ_IDLE_CNT___S 16 +#define UMAC_TQM_R0_GXI_GXI_IDLE_COUNTERS__GXI_WRITE_IDLE_CNT___M 0x0000FFFF +#define UMAC_TQM_R0_GXI_GXI_IDLE_COUNTERS__GXI_WRITE_IDLE_CNT___S 0 +#define UMAC_TQM_R0_GXI_GXI_IDLE_COUNTERS___M 0xFFFFFFFF +#define UMAC_TQM_R0_GXI_GXI_IDLE_COUNTERS___S 0 + +#define UMAC_TQM_R0_GXI_GXI_RD_LATENCY_CTRL (0x00A3C464) +#define UMAC_TQM_R0_GXI_GXI_RD_LATENCY_CTRL___RWC QCSR_REG_RW +#define UMAC_TQM_R0_GXI_GXI_RD_LATENCY_CTRL___POR 0x00000000 +#define UMAC_TQM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_RANGE___POR 0x0 +#define UMAC_TQM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_EN___POR 0x0 +#define UMAC_TQM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_MIN___POR 0x0000 +#define UMAC_TQM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_RANGE___M 0x000E0000 +#define UMAC_TQM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_RANGE___S 17 +#define UMAC_TQM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_EN___M 0x00010000 +#define UMAC_TQM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_EN___S 16 +#define UMAC_TQM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_MIN___M 0x0000FFFF +#define UMAC_TQM_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_MIN___S 0 +#define UMAC_TQM_R0_GXI_GXI_RD_LATENCY_CTRL___M 0x000FFFFF +#define UMAC_TQM_R0_GXI_GXI_RD_LATENCY_CTRL___S 0 + +#define UMAC_TQM_R0_GXI_GXI_WR_LATENCY_CTRL (0x00A3C468) +#define UMAC_TQM_R0_GXI_GXI_WR_LATENCY_CTRL___RWC QCSR_REG_RW +#define UMAC_TQM_R0_GXI_GXI_WR_LATENCY_CTRL___POR 0x00000000 +#define UMAC_TQM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_RANGE___POR 0x0 +#define UMAC_TQM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_EN___POR 0x0 +#define UMAC_TQM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_MIN___POR 0x0000 +#define UMAC_TQM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_RANGE___M 0x000E0000 +#define UMAC_TQM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_RANGE___S 17 +#define UMAC_TQM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_EN___M 0x00010000 +#define UMAC_TQM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_EN___S 16 +#define UMAC_TQM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_MIN___M 0x0000FFFF +#define UMAC_TQM_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_MIN___S 0 +#define UMAC_TQM_R0_GXI_GXI_WR_LATENCY_CTRL___M 0x000FFFFF +#define UMAC_TQM_R0_GXI_GXI_WR_LATENCY_CTRL___S 0 + +#define UMAC_TQM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0 (0x00A3C46C) +#define UMAC_TQM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___RWC QCSR_REG_RW +#define UMAC_TQM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___POR 0x00000000 +#define UMAC_TQM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0__VALUE___POR 0x00000000 +#define UMAC_TQM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0__VALUE___M 0xFFFFFFFF +#define UMAC_TQM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0__VALUE___S 0 +#define UMAC_TQM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___M 0xFFFFFFFF +#define UMAC_TQM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___S 0 + +#define UMAC_TQM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1 (0x00A3C470) +#define UMAC_TQM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___RWC QCSR_REG_RW +#define UMAC_TQM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___POR 0x00000000 +#define UMAC_TQM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1__VALUE___POR 0x00000000 +#define UMAC_TQM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1__VALUE___M 0xFFFFFFFF +#define UMAC_TQM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1__VALUE___S 0 +#define UMAC_TQM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___M 0xFFFFFFFF +#define UMAC_TQM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___S 0 + +#define UMAC_TQM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0 (0x00A3C474) +#define UMAC_TQM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___RWC QCSR_REG_RW +#define UMAC_TQM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___POR 0x00000000 +#define UMAC_TQM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0__VALUE___POR 0x00000000 +#define UMAC_TQM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0__VALUE___M 0xFFFFFFFF +#define UMAC_TQM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0__VALUE___S 0 +#define UMAC_TQM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___M 0xFFFFFFFF +#define UMAC_TQM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___S 0 + +#define UMAC_TQM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1 (0x00A3C478) +#define UMAC_TQM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___RWC QCSR_REG_RW +#define UMAC_TQM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___POR 0x00000000 +#define UMAC_TQM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1__VALUE___POR 0x00000000 +#define UMAC_TQM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1__VALUE___M 0xFFFFFFFF +#define UMAC_TQM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1__VALUE___S 0 +#define UMAC_TQM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___M 0xFFFFFFFF +#define UMAC_TQM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___S 0 + +#define UMAC_TQM_R0_GXI_GXI_AXI_OUTSANDING_CTL (0x00A3C47C) +#define UMAC_TQM_R0_GXI_GXI_AXI_OUTSANDING_CTL___RWC QCSR_REG_RW +#define UMAC_TQM_R0_GXI_GXI_AXI_OUTSANDING_CTL___POR 0x00000000 +#define UMAC_TQM_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_EN___POR 0x0 +#define UMAC_TQM_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_CNT___POR 0x00 +#define UMAC_TQM_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_EN___POR 0x0 +#define UMAC_TQM_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_CNT___POR 0x00 +#define UMAC_TQM_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_EN___M 0x00008000 +#define UMAC_TQM_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_EN___S 15 +#define UMAC_TQM_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_CNT___M 0x00001F00 +#define UMAC_TQM_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_CNT___S 8 +#define UMAC_TQM_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_EN___M 0x00000080 +#define UMAC_TQM_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_EN___S 7 +#define UMAC_TQM_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_CNT___M 0x0000001F +#define UMAC_TQM_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_CNT___S 0 +#define UMAC_TQM_R0_GXI_GXI_AXI_OUTSANDING_CTL___M 0x00009F9F +#define UMAC_TQM_R0_GXI_GXI_AXI_OUTSANDING_CTL___S 0 + +#define UMAC_TQM_R0_CACHE_CTL_CONFIG (0x00A3C480) +#define UMAC_TQM_R0_CACHE_CTL_CONFIG___RWC QCSR_REG_RW +#define UMAC_TQM_R0_CACHE_CTL_CONFIG___POR 0x008608FF +#define UMAC_TQM_R0_CACHE_CTL_CONFIG__DESC_TYPE_SWAP___POR 0x00 +#define UMAC_TQM_R0_CACHE_CTL_CONFIG__ENABLE_LEGACY_SWAP___POR 0x1 +#define UMAC_TQM_R0_CACHE_CTL_CONFIG__WRITE_STRUCT_SWAP___POR 0x0 +#define UMAC_TQM_R0_CACHE_CTL_CONFIG__READ_STRUCT_SWAP___POR 0x0 +#define UMAC_TQM_R0_CACHE_CTL_CONFIG__WRITE_SECURITY___POR 0x0 +#define UMAC_TQM_R0_CACHE_CTL_CONFIG__READ_SECURITY___POR 0x0 +#define UMAC_TQM_R0_CACHE_CTL_CONFIG__BG_FLUSH_POST_WRITE___POR 0x1 +#define UMAC_TQM_R0_CACHE_CTL_CONFIG__CLIENT_FLUSH_POST_WRITE___POR 0x1 +#define UMAC_TQM_R0_CACHE_CTL_CONFIG__CACHE_EMPTY_THRESHOLD___POR 0x04 +#define UMAC_TQM_R0_CACHE_CTL_CONFIG__CACHE_LINE_USE_NUM___POR 0x0FF +#define UMAC_TQM_R0_CACHE_CTL_CONFIG__DESC_TYPE_SWAP___M 0xFF000000 +#define UMAC_TQM_R0_CACHE_CTL_CONFIG__DESC_TYPE_SWAP___S 24 +#define UMAC_TQM_R0_CACHE_CTL_CONFIG__ENABLE_LEGACY_SWAP___M 0x00800000 +#define UMAC_TQM_R0_CACHE_CTL_CONFIG__ENABLE_LEGACY_SWAP___S 23 +#define UMAC_TQM_R0_CACHE_CTL_CONFIG__WRITE_STRUCT_SWAP___M 0x00400000 +#define UMAC_TQM_R0_CACHE_CTL_CONFIG__WRITE_STRUCT_SWAP___S 22 +#define UMAC_TQM_R0_CACHE_CTL_CONFIG__READ_STRUCT_SWAP___M 0x00200000 +#define UMAC_TQM_R0_CACHE_CTL_CONFIG__READ_STRUCT_SWAP___S 21 +#define UMAC_TQM_R0_CACHE_CTL_CONFIG__WRITE_SECURITY___M 0x00100000 +#define UMAC_TQM_R0_CACHE_CTL_CONFIG__WRITE_SECURITY___S 20 +#define UMAC_TQM_R0_CACHE_CTL_CONFIG__READ_SECURITY___M 0x00080000 +#define UMAC_TQM_R0_CACHE_CTL_CONFIG__READ_SECURITY___S 19 +#define UMAC_TQM_R0_CACHE_CTL_CONFIG__BG_FLUSH_POST_WRITE___M 0x00040000 +#define UMAC_TQM_R0_CACHE_CTL_CONFIG__BG_FLUSH_POST_WRITE___S 18 +#define UMAC_TQM_R0_CACHE_CTL_CONFIG__CLIENT_FLUSH_POST_WRITE___M 0x00020000 +#define UMAC_TQM_R0_CACHE_CTL_CONFIG__CLIENT_FLUSH_POST_WRITE___S 17 +#define UMAC_TQM_R0_CACHE_CTL_CONFIG__CACHE_EMPTY_THRESHOLD___M 0x0001FE00 +#define UMAC_TQM_R0_CACHE_CTL_CONFIG__CACHE_EMPTY_THRESHOLD___S 9 +#define UMAC_TQM_R0_CACHE_CTL_CONFIG__CACHE_LINE_USE_NUM___M 0x000001FF +#define UMAC_TQM_R0_CACHE_CTL_CONFIG__CACHE_LINE_USE_NUM___S 0 +#define UMAC_TQM_R0_CACHE_CTL_CONFIG___M 0xFFFFFFFF +#define UMAC_TQM_R0_CACHE_CTL_CONFIG___S 0 + +#define UMAC_TQM_R0_CACHE_CTL_CONTROL (0x00A3C484) +#define UMAC_TQM_R0_CACHE_CTL_CONTROL___RWC QCSR_REG_RW +#define UMAC_TQM_R0_CACHE_CTL_CONTROL___POR 0x00000000 +#define UMAC_TQM_R0_CACHE_CTL_CONTROL__WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH___POR 0x0 +#define UMAC_TQM_R0_CACHE_CTL_CONTROL__CACHE_RESET___POR 0x0 +#define UMAC_TQM_R0_CACHE_CTL_CONTROL__WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH___M 0x00000002 +#define UMAC_TQM_R0_CACHE_CTL_CONTROL__WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH___S 1 +#define UMAC_TQM_R0_CACHE_CTL_CONTROL__CACHE_RESET___M 0x00000001 +#define UMAC_TQM_R0_CACHE_CTL_CONTROL__CACHE_RESET___S 0 +#define UMAC_TQM_R0_CACHE_CTL_CONTROL___M 0x00000003 +#define UMAC_TQM_R0_CACHE_CTL_CONTROL___S 0 + +#define UMAC_TQM_R0_CACHE_CTL_CONFIG_SET (0x00A3C488) +#define UMAC_TQM_R0_CACHE_CTL_CONFIG_SET___RWC QCSR_REG_RW +#define UMAC_TQM_R0_CACHE_CTL_CONFIG_SET___POR 0x00000000 +#define UMAC_TQM_R0_CACHE_CTL_CONFIG_SET__CONFIG_SET___POR 0x0000000 +#define UMAC_TQM_R0_CACHE_CTL_CONFIG_SET__CONFIG_SET___M 0x01FFFFFF +#define UMAC_TQM_R0_CACHE_CTL_CONFIG_SET__CONFIG_SET___S 0 +#define UMAC_TQM_R0_CACHE_CTL_CONFIG_SET___M 0x01FFFFFF +#define UMAC_TQM_R0_CACHE_CTL_CONFIG_SET___S 0 + +#define UMAC_TQM_R0_CACHE_CTL_SET_SIZE (0x00A3C48C) +#define UMAC_TQM_R0_CACHE_CTL_SET_SIZE___RWC QCSR_REG_RW +#define UMAC_TQM_R0_CACHE_CTL_SET_SIZE___POR 0x000000F0 +#define UMAC_TQM_R0_CACHE_CTL_SET_SIZE__SET1_SIZE___POR 0x0F0 +#define UMAC_TQM_R0_CACHE_CTL_SET_SIZE__SET1_SIZE___M 0x000001FF +#define UMAC_TQM_R0_CACHE_CTL_SET_SIZE__SET1_SIZE___S 0 +#define UMAC_TQM_R0_CACHE_CTL_SET_SIZE___M 0x000001FF +#define UMAC_TQM_R0_CACHE_CTL_SET_SIZE___S 0 + +#define UMAC_TQM_R0_CMD_AND_PTR_PREFETCH (0x00A3C490) +#define UMAC_TQM_R0_CMD_AND_PTR_PREFETCH___RWC QCSR_REG_RW +#define UMAC_TQM_R0_CMD_AND_PTR_PREFETCH___POR 0x10004710 +#define UMAC_TQM_R0_CMD_AND_PTR_PREFETCH__MIN_READ_SIZE___POR 0x10 +#define UMAC_TQM_R0_CMD_AND_PTR_PREFETCH__DESC_THRESHOLD___POR 0x04 +#define UMAC_TQM_R0_CMD_AND_PTR_PREFETCH__CMD_THRESHOLD___POR 0x1C +#define UMAC_TQM_R0_CMD_AND_PTR_PREFETCH__ENTRANCE_THRESHOLD___POR 0x10 +#define UMAC_TQM_R0_CMD_AND_PTR_PREFETCH__MIN_READ_SIZE___M 0x3F000000 +#define UMAC_TQM_R0_CMD_AND_PTR_PREFETCH__MIN_READ_SIZE___S 24 +#define UMAC_TQM_R0_CMD_AND_PTR_PREFETCH__DESC_THRESHOLD___M 0x0003F000 +#define UMAC_TQM_R0_CMD_AND_PTR_PREFETCH__DESC_THRESHOLD___S 12 +#define UMAC_TQM_R0_CMD_AND_PTR_PREFETCH__CMD_THRESHOLD___M 0x00000FC0 +#define UMAC_TQM_R0_CMD_AND_PTR_PREFETCH__CMD_THRESHOLD___S 6 +#define UMAC_TQM_R0_CMD_AND_PTR_PREFETCH__ENTRANCE_THRESHOLD___M 0x0000003F +#define UMAC_TQM_R0_CMD_AND_PTR_PREFETCH__ENTRANCE_THRESHOLD___S 0 +#define UMAC_TQM_R0_CMD_AND_PTR_PREFETCH___M 0x3F03FFFF +#define UMAC_TQM_R0_CMD_AND_PTR_PREFETCH___S 0 + +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_0 (0x00A3C494) +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_0___RWC QCSR_REG_RW +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_0___POR 0x002F0000 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_0__SW_CMD_END_ADDR___POR 0x02F +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_0__SW_CMD_START_ADDR___POR 0x000 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_0__SW_CMD_END_ADDR___M 0x01FF0000 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_0__SW_CMD_END_ADDR___S 16 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_0__SW_CMD_START_ADDR___M 0x000001FF +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_0__SW_CMD_START_ADDR___S 0 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_0___M 0x01FF01FF +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_0___S 0 + +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_1 (0x00A3C498) +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_1___RWC QCSR_REG_RW +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_1___POR 0x005F0030 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_1__HWSCH_CMD1_END_ADDR___POR 0x05F +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_1__HWSCH_CMD1_START_ADDR___POR 0x030 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_1__HWSCH_CMD1_END_ADDR___M 0x01FF0000 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_1__HWSCH_CMD1_END_ADDR___S 16 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_1__HWSCH_CMD1_START_ADDR___M 0x000001FF +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_1__HWSCH_CMD1_START_ADDR___S 0 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_1___M 0x01FF01FF +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_1___S 0 + +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_2 (0x00A3C49C) +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_2___RWC QCSR_REG_RW +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_2___POR 0x008F0060 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_2__MSDU_ENTRANCE1_CMD_END_ADDR___POR 0x08F +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_2__MSDU_ENTRANCE1_CMD_START_ADDR___POR 0x060 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_2__MSDU_ENTRANCE1_CMD_END_ADDR___M 0x01FF0000 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_2__MSDU_ENTRANCE1_CMD_END_ADDR___S 16 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_2__MSDU_ENTRANCE1_CMD_START_ADDR___M 0x000001FF +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_2__MSDU_ENTRANCE1_CMD_START_ADDR___S 0 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_2___M 0x01FF01FF +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_2___S 0 + +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_3 (0x00A3C4A0) +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_3___RWC QCSR_REG_RW +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_3___POR 0x00BF0090 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_3__MSDU_ENTRANCE2_CMD_END_ADDR___POR 0x0BF +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_3__MSDU_ENTRANCE2_CMD_START_ADDR___POR 0x090 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_3__MSDU_ENTRANCE2_CMD_END_ADDR___M 0x01FF0000 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_3__MSDU_ENTRANCE2_CMD_END_ADDR___S 16 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_3__MSDU_ENTRANCE2_CMD_START_ADDR___M 0x000001FF +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_3__MSDU_ENTRANCE2_CMD_START_ADDR___S 0 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_3___M 0x01FF01FF +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_3___S 0 + +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_4 (0x00A3C4A4) +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_4___RWC QCSR_REG_RW +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_4___POR 0x01370120 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_4__DESC_PTRS_END_ADDR___POR 0x137 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_4__DESC_PTRS_START_ADDR___POR 0x120 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_4__DESC_PTRS_END_ADDR___M 0x01FF0000 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_4__DESC_PTRS_END_ADDR___S 16 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_4__DESC_PTRS_START_ADDR___M 0x000001FF +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_4__DESC_PTRS_START_ADDR___S 0 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_4___M 0x01FF01FF +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_4___S 0 + +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_8 (0x00A3C4B0) +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_8___RWC QCSR_REG_RW +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_8___POR 0x00EF00C0 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_8__MSDU_ENTRANCE3_CMD_END_ADDR___POR 0x0EF +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_8__MSDU_ENTRANCE3_CMD_START_ADDR___POR 0x0C0 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_8__MSDU_ENTRANCE3_CMD_END_ADDR___M 0x01FF0000 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_8__MSDU_ENTRANCE3_CMD_END_ADDR___S 16 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_8__MSDU_ENTRANCE3_CMD_START_ADDR___M 0x000001FF +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_8__MSDU_ENTRANCE3_CMD_START_ADDR___S 0 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_8___M 0x01FF01FF +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_8___S 0 + +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_9 (0x00A3C4B4) +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_9___RWC QCSR_REG_RW +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_9___POR 0x011F00F0 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_9__SW_CMD1_END_ADDR___POR 0x11F +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_9__SW_CMD1_START_ADDR___POR 0x0F0 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_9__SW_CMD1_END_ADDR___M 0x01FF0000 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_9__SW_CMD1_END_ADDR___S 16 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_9__SW_CMD1_START_ADDR___M 0x000001FF +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_9__SW_CMD1_START_ADDR___S 0 +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_9___M 0x01FF01FF +#define UMAC_TQM_R0_PREFETCH_MEMORY_PARTITION_9___S 0 + +#define UMAC_TQM_R0_STATUS_BUFFER_PARTITION (0x00A3C4B8) +#define UMAC_TQM_R0_STATUS_BUFFER_PARTITION___RWC QCSR_REG_RW +#define UMAC_TQM_R0_STATUS_BUFFER_PARTITION___POR 0x00001441 +#define UMAC_TQM_R0_STATUS_BUFFER_PARTITION__ISSUE_MULTIPLE___POR 0x1 +#define UMAC_TQM_R0_STATUS_BUFFER_PARTITION__WAIT_THRESHOLD___POR 0x4 +#define UMAC_TQM_R0_STATUS_BUFFER_PARTITION__STATUS0_END_ADDR___POR 0x41 +#define UMAC_TQM_R0_STATUS_BUFFER_PARTITION__ISSUE_MULTIPLE___M 0x00001000 +#define UMAC_TQM_R0_STATUS_BUFFER_PARTITION__ISSUE_MULTIPLE___S 12 +#define UMAC_TQM_R0_STATUS_BUFFER_PARTITION__WAIT_THRESHOLD___M 0x00000F00 +#define UMAC_TQM_R0_STATUS_BUFFER_PARTITION__WAIT_THRESHOLD___S 8 +#define UMAC_TQM_R0_STATUS_BUFFER_PARTITION__STATUS0_END_ADDR___M 0x0000007F +#define UMAC_TQM_R0_STATUS_BUFFER_PARTITION__STATUS0_END_ADDR___S 0 +#define UMAC_TQM_R0_STATUS_BUFFER_PARTITION___M 0x00001F7F +#define UMAC_TQM_R0_STATUS_BUFFER_PARTITION___S 0 + +#define UMAC_TQM_R0_WATCHDOG (0x00A3C4BC) +#define UMAC_TQM_R0_WATCHDOG___RWC QCSR_REG_RW +#define UMAC_TQM_R0_WATCHDOG___POR 0x00002710 +#define UMAC_TQM_R0_WATCHDOG__STATUS___POR 0x0000 +#define UMAC_TQM_R0_WATCHDOG__LIMIT___POR 0x2710 +#define UMAC_TQM_R0_WATCHDOG__STATUS___M 0x7FFF0000 +#define UMAC_TQM_R0_WATCHDOG__STATUS___S 16 +#define UMAC_TQM_R0_WATCHDOG__LIMIT___M 0x0000FFFF +#define UMAC_TQM_R0_WATCHDOG__LIMIT___S 0 +#define UMAC_TQM_R0_WATCHDOG___M 0x7FFFFFFF +#define UMAC_TQM_R0_WATCHDOG___S 0 + +#define UMAC_TQM_R0_TESTBUS_CTRL (0x00A3C4C0) +#define UMAC_TQM_R0_TESTBUS_CTRL___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TESTBUS_CTRL___POR 0x00000000 +#define UMAC_TQM_R0_TESTBUS_CTRL__SELECT_CACHE_CTL___POR 0x0 +#define UMAC_TQM_R0_TESTBUS_CTRL__SELECT_GXI___POR 0x00 +#define UMAC_TQM_R0_TESTBUS_CTRL__SELECT_TQM___POR 0x00 +#define UMAC_TQM_R0_TESTBUS_CTRL__SELECT_CACHE_CTL___M 0x0000E000 +#define UMAC_TQM_R0_TESTBUS_CTRL__SELECT_CACHE_CTL___S 13 +#define UMAC_TQM_R0_TESTBUS_CTRL__SELECT_GXI___M 0x00001F00 +#define UMAC_TQM_R0_TESTBUS_CTRL__SELECT_GXI___S 8 +#define UMAC_TQM_R0_TESTBUS_CTRL__SELECT_TQM___M 0x0000003F +#define UMAC_TQM_R0_TESTBUS_CTRL__SELECT_TQM___S 0 +#define UMAC_TQM_R0_TESTBUS_CTRL___M 0x0000FF3F +#define UMAC_TQM_R0_TESTBUS_CTRL___S 0 + +#define UMAC_TQM_R0_TESTBUS_LOWER (0x00A3C4C4) +#define UMAC_TQM_R0_TESTBUS_LOWER___RWC QCSR_REG_RO +#define UMAC_TQM_R0_TESTBUS_LOWER___POR 0x00000000 +#define UMAC_TQM_R0_TESTBUS_LOWER__VALUE___POR 0x00000000 +#define UMAC_TQM_R0_TESTBUS_LOWER__VALUE___M 0xFFFFFFFF +#define UMAC_TQM_R0_TESTBUS_LOWER__VALUE___S 0 +#define UMAC_TQM_R0_TESTBUS_LOWER___M 0xFFFFFFFF +#define UMAC_TQM_R0_TESTBUS_LOWER___S 0 + +#define UMAC_TQM_R0_TESTBUS_UPPER (0x00A3C4C8) +#define UMAC_TQM_R0_TESTBUS_UPPER___RWC QCSR_REG_RO +#define UMAC_TQM_R0_TESTBUS_UPPER___POR 0x00000000 +#define UMAC_TQM_R0_TESTBUS_UPPER__VALUE___POR 0x00 +#define UMAC_TQM_R0_TESTBUS_UPPER__VALUE___M 0x000000FF +#define UMAC_TQM_R0_TESTBUS_UPPER__VALUE___S 0 +#define UMAC_TQM_R0_TESTBUS_UPPER___M 0x000000FF +#define UMAC_TQM_R0_TESTBUS_UPPER___S 0 + +#define UMAC_TQM_R0_EVENTMASK_IX_0 (0x00A3C4CC) +#define UMAC_TQM_R0_EVENTMASK_IX_0___RWC QCSR_REG_RW +#define UMAC_TQM_R0_EVENTMASK_IX_0___POR 0xFFFFFFFF +#define UMAC_TQM_R0_EVENTMASK_IX_0__MASK___POR 0xFFFFFFFF +#define UMAC_TQM_R0_EVENTMASK_IX_0__MASK___M 0xFFFFFFFF +#define UMAC_TQM_R0_EVENTMASK_IX_0__MASK___S 0 +#define UMAC_TQM_R0_EVENTMASK_IX_0___M 0xFFFFFFFF +#define UMAC_TQM_R0_EVENTMASK_IX_0___S 0 + +#define UMAC_TQM_R0_EVENTMASK_IX_1 (0x00A3C4D0) +#define UMAC_TQM_R0_EVENTMASK_IX_1___RWC QCSR_REG_RW +#define UMAC_TQM_R0_EVENTMASK_IX_1___POR 0xFFFFFFFF +#define UMAC_TQM_R0_EVENTMASK_IX_1__MASK___POR 0xFFFFFFFF +#define UMAC_TQM_R0_EVENTMASK_IX_1__MASK___M 0xFFFFFFFF +#define UMAC_TQM_R0_EVENTMASK_IX_1__MASK___S 0 +#define UMAC_TQM_R0_EVENTMASK_IX_1___M 0xFFFFFFFF +#define UMAC_TQM_R0_EVENTMASK_IX_1___S 0 + +#define UMAC_TQM_R0_EVENTMASK_IX_2 (0x00A3C4D4) +#define UMAC_TQM_R0_EVENTMASK_IX_2___RWC QCSR_REG_RW +#define UMAC_TQM_R0_EVENTMASK_IX_2___POR 0xFFFFFFFF +#define UMAC_TQM_R0_EVENTMASK_IX_2__MASK___POR 0xFFFFFFFF +#define UMAC_TQM_R0_EVENTMASK_IX_2__MASK___M 0xFFFFFFFF +#define UMAC_TQM_R0_EVENTMASK_IX_2__MASK___S 0 +#define UMAC_TQM_R0_EVENTMASK_IX_2___M 0xFFFFFFFF +#define UMAC_TQM_R0_EVENTMASK_IX_2___S 0 + +#define UMAC_TQM_R0_EVENTMASK_IX_3 (0x00A3C4D8) +#define UMAC_TQM_R0_EVENTMASK_IX_3___RWC QCSR_REG_RW +#define UMAC_TQM_R0_EVENTMASK_IX_3___POR 0xFFFFFFFF +#define UMAC_TQM_R0_EVENTMASK_IX_3__MASK___POR 0xFFFFFFFF +#define UMAC_TQM_R0_EVENTMASK_IX_3__MASK___M 0xFFFFFFFF +#define UMAC_TQM_R0_EVENTMASK_IX_3__MASK___S 0 +#define UMAC_TQM_R0_EVENTMASK_IX_3___M 0xFFFFFFFF +#define UMAC_TQM_R0_EVENTMASK_IX_3___S 0 + +#define UMAC_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL (0x00A3C4DC) +#define UMAC_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL___RWC QCSR_REG_RW +#define UMAC_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL___POR 0x7FFE0002 +#define UMAC_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___POR 0x3FFF +#define UMAC_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___POR 0x0000 +#define UMAC_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___POR 0x1 +#define UMAC_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___POR 0x0 +#define UMAC_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___M 0xFFFE0000 +#define UMAC_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___S 17 +#define UMAC_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___M 0x0001FFFC +#define UMAC_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___S 2 +#define UMAC_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___M 0x00000002 +#define UMAC_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___S 1 +#define UMAC_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___M 0x00000001 +#define UMAC_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___S 0 +#define UMAC_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL___M 0xFFFFFFFF +#define UMAC_TQM_R0_REG_ACCESS_EVENT_GEN_CTRL___S 0 + +#define UMAC_TQM_R0_END_OF_TEST_CHECK (0x00A3C4E0) +#define UMAC_TQM_R0_END_OF_TEST_CHECK___RWC QCSR_REG_RW +#define UMAC_TQM_R0_END_OF_TEST_CHECK___POR 0x00000000 +#define UMAC_TQM_R0_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0 +#define UMAC_TQM_R0_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001 +#define UMAC_TQM_R0_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S 0 +#define UMAC_TQM_R0_END_OF_TEST_CHECK___M 0x00000001 +#define UMAC_TQM_R0_END_OF_TEST_CHECK___S 0 + +#define UMAC_TQM_R0_INVALID_APB_ACC_ADDR (0x00A3C4E4) +#define UMAC_TQM_R0_INVALID_APB_ACC_ADDR___RWC QCSR_REG_RO +#define UMAC_TQM_R0_INVALID_APB_ACC_ADDR___POR 0x00000000 +#define UMAC_TQM_R0_INVALID_APB_ACC_ADDR__VALUE___POR 0x00000 +#define UMAC_TQM_R0_INVALID_APB_ACC_ADDR__VALUE___M 0x0001FFFF +#define UMAC_TQM_R0_INVALID_APB_ACC_ADDR__VALUE___S 0 +#define UMAC_TQM_R0_INVALID_APB_ACC_ADDR___M 0x0001FFFF +#define UMAC_TQM_R0_INVALID_APB_ACC_ADDR___S 0 + +#define UMAC_TQM_R0_SM_STATES_IX0 (0x00A3C4E8) +#define UMAC_TQM_R0_SM_STATES_IX0___RWC QCSR_REG_RO +#define UMAC_TQM_R0_SM_STATES_IX0___POR 0x00000000 +#define UMAC_TQM_R0_SM_STATES_IX0__GET_QUEUE_STATS_SM___POR 0x0 +#define UMAC_TQM_R0_SM_STATES_IX0__GET_MPDU_HEAD_INFO_SM___POR 0x0 +#define UMAC_TQM_R0_SM_STATES_IX0__FLUSH_AND_UNBLOCK_CACHE_SM___POR 0x0 +#define UMAC_TQM_R0_SM_STATES_IX0__ADD_MPDU_LINK_SM___POR 0x0 +#define UMAC_TQM_R0_SM_STATES_IX0__CREATE_MPDU_SM___POR 0x00 +#define UMAC_TQM_R0_SM_STATES_IX0__GEN_MPDU_SM___POR 0x00 +#define UMAC_TQM_R0_SM_STATES_IX0__ADD_MSDU_SM___POR 0x00 +#define UMAC_TQM_R0_SM_STATES_IX0__GET_QUEUE_STATS_SM___M 0x1E000000 +#define UMAC_TQM_R0_SM_STATES_IX0__GET_QUEUE_STATS_SM___S 25 +#define UMAC_TQM_R0_SM_STATES_IX0__GET_MPDU_HEAD_INFO_SM___M 0x01E00000 +#define UMAC_TQM_R0_SM_STATES_IX0__GET_MPDU_HEAD_INFO_SM___S 21 +#define UMAC_TQM_R0_SM_STATES_IX0__FLUSH_AND_UNBLOCK_CACHE_SM___M 0x00180000 +#define UMAC_TQM_R0_SM_STATES_IX0__FLUSH_AND_UNBLOCK_CACHE_SM___S 19 +#define UMAC_TQM_R0_SM_STATES_IX0__ADD_MPDU_LINK_SM___M 0x00078000 +#define UMAC_TQM_R0_SM_STATES_IX0__ADD_MPDU_LINK_SM___S 15 +#define UMAC_TQM_R0_SM_STATES_IX0__CREATE_MPDU_SM___M 0x00007C00 +#define UMAC_TQM_R0_SM_STATES_IX0__CREATE_MPDU_SM___S 10 +#define UMAC_TQM_R0_SM_STATES_IX0__GEN_MPDU_SM___M 0x000003E0 +#define UMAC_TQM_R0_SM_STATES_IX0__GEN_MPDU_SM___S 5 +#define UMAC_TQM_R0_SM_STATES_IX0__ADD_MSDU_SM___M 0x0000001F +#define UMAC_TQM_R0_SM_STATES_IX0__ADD_MSDU_SM___S 0 +#define UMAC_TQM_R0_SM_STATES_IX0___M 0x1FFFFFFF +#define UMAC_TQM_R0_SM_STATES_IX0___S 0 + +#define UMAC_TQM_R0_SM_STATES_IX1 (0x00A3C4EC) +#define UMAC_TQM_R0_SM_STATES_IX1___RWC QCSR_REG_RO +#define UMAC_TQM_R0_SM_STATES_IX1___POR 0x00000000 +#define UMAC_TQM_R0_SM_STATES_IX1__ARB_STATUS_BLK1_SM___POR 0x0 +#define UMAC_TQM_R0_SM_STATES_IX1__ARB_STATUS_BLK0_SM___POR 0x0 +#define UMAC_TQM_R0_SM_STATES_IX1__UPDATE_TX_MPDU_COUNT_SM___POR 0x00 +#define UMAC_TQM_R0_SM_STATES_IX1__REM_MSDU_SM___POR 0x00 +#define UMAC_TQM_R0_SM_STATES_IX1__REM_MPDU_SM___POR 0x00 +#define UMAC_TQM_R0_SM_STATES_IX1__WRITE_CMD_SM___POR 0x0 +#define UMAC_TQM_R0_SM_STATES_IX1__LIST_MPDU_MAIN_SM___POR 0x00 +#define UMAC_TQM_R0_SM_STATES_IX1__LIST_TLV_SM___POR 0x0 +#define UMAC_TQM_R0_SM_STATES_IX1__ARB_STATUS_BLK1_SM___M 0xC0000000 +#define UMAC_TQM_R0_SM_STATES_IX1__ARB_STATUS_BLK1_SM___S 30 +#define UMAC_TQM_R0_SM_STATES_IX1__ARB_STATUS_BLK0_SM___M 0x30000000 +#define UMAC_TQM_R0_SM_STATES_IX1__ARB_STATUS_BLK0_SM___S 28 +#define UMAC_TQM_R0_SM_STATES_IX1__UPDATE_TX_MPDU_COUNT_SM___M 0x0F800000 +#define UMAC_TQM_R0_SM_STATES_IX1__UPDATE_TX_MPDU_COUNT_SM___S 23 +#define UMAC_TQM_R0_SM_STATES_IX1__REM_MSDU_SM___M 0x007C0000 +#define UMAC_TQM_R0_SM_STATES_IX1__REM_MSDU_SM___S 18 +#define UMAC_TQM_R0_SM_STATES_IX1__REM_MPDU_SM___M 0x0003F000 +#define UMAC_TQM_R0_SM_STATES_IX1__REM_MPDU_SM___S 12 +#define UMAC_TQM_R0_SM_STATES_IX1__WRITE_CMD_SM___M 0x00000E00 +#define UMAC_TQM_R0_SM_STATES_IX1__WRITE_CMD_SM___S 9 +#define UMAC_TQM_R0_SM_STATES_IX1__LIST_MPDU_MAIN_SM___M 0x000001F0 +#define UMAC_TQM_R0_SM_STATES_IX1__LIST_MPDU_MAIN_SM___S 4 +#define UMAC_TQM_R0_SM_STATES_IX1__LIST_TLV_SM___M 0x0000000F +#define UMAC_TQM_R0_SM_STATES_IX1__LIST_TLV_SM___S 0 +#define UMAC_TQM_R0_SM_STATES_IX1___M 0xFFFFFFFF +#define UMAC_TQM_R0_SM_STATES_IX1___S 0 + +#define UMAC_TQM_R0_SM_STATES_IX2 (0x00A3C4F0) +#define UMAC_TQM_R0_SM_STATES_IX2___RWC QCSR_REG_RO +#define UMAC_TQM_R0_SM_STATES_IX2___POR 0x00000000 +#define UMAC_TQM_R0_SM_STATES_IX2__ARB_ASYNC_SM___POR 0x0 +#define UMAC_TQM_R0_SM_STATES_IX2__ARB_MSDU_ENT_SM___POR 0x0 +#define UMAC_TQM_R0_SM_STATES_IX2__ARB_SW_CMD_SM___POR 0x0 +#define UMAC_TQM_R0_SM_STATES_IX2__ARB_HWSCH_CMD_SM___POR 0x0 +#define UMAC_TQM_R0_SM_STATES_IX2__PREFETCH_READ_SM___POR 0x0 +#define UMAC_TQM_R0_SM_STATES_IX2__PREFETCH_SM___POR 0x00000 +#define UMAC_TQM_R0_SM_STATES_IX2__ARB_ASYNC_SM___M 0x80000000 +#define UMAC_TQM_R0_SM_STATES_IX2__ARB_ASYNC_SM___S 31 +#define UMAC_TQM_R0_SM_STATES_IX2__ARB_MSDU_ENT_SM___M 0x70000000 +#define UMAC_TQM_R0_SM_STATES_IX2__ARB_MSDU_ENT_SM___S 28 +#define UMAC_TQM_R0_SM_STATES_IX2__ARB_SW_CMD_SM___M 0x0F000000 +#define UMAC_TQM_R0_SM_STATES_IX2__ARB_SW_CMD_SM___S 24 +#define UMAC_TQM_R0_SM_STATES_IX2__ARB_HWSCH_CMD_SM___M 0x00F00000 +#define UMAC_TQM_R0_SM_STATES_IX2__ARB_HWSCH_CMD_SM___S 20 +#define UMAC_TQM_R0_SM_STATES_IX2__PREFETCH_READ_SM___M 0x000C0000 +#define UMAC_TQM_R0_SM_STATES_IX2__PREFETCH_READ_SM___S 18 +#define UMAC_TQM_R0_SM_STATES_IX2__PREFETCH_SM___M 0x0003FFFF +#define UMAC_TQM_R0_SM_STATES_IX2__PREFETCH_SM___S 0 +#define UMAC_TQM_R0_SM_STATES_IX2___M 0xFFFFFFFF +#define UMAC_TQM_R0_SM_STATES_IX2___S 0 + +#define UMAC_TQM_R0_SM_STATES_IX3 (0x00A3C4F4) +#define UMAC_TQM_R0_SM_STATES_IX3___RWC QCSR_REG_RO +#define UMAC_TQM_R0_SM_STATES_IX3___POR 0x00000000 +#define UMAC_TQM_R0_SM_STATES_IX3__UPDATE_QUEUE_DESC_SM___POR 0x00 +#define UMAC_TQM_R0_SM_STATES_IX3__AXI_TO_TLV_SM___POR 0x0 +#define UMAC_TQM_R0_SM_STATES_IX3__LIST_TLV_STATE___POR 0x0 +#define UMAC_TQM_R0_SM_STATES_IX3__DATA_ALIGN_SM___POR 0x0 +#define UMAC_TQM_R0_SM_STATES_IX3__UPDATE_QUEUE_DESC_SM___M 0x00000F80 +#define UMAC_TQM_R0_SM_STATES_IX3__UPDATE_QUEUE_DESC_SM___S 7 +#define UMAC_TQM_R0_SM_STATES_IX3__AXI_TO_TLV_SM___M 0x00000060 +#define UMAC_TQM_R0_SM_STATES_IX3__AXI_TO_TLV_SM___S 5 +#define UMAC_TQM_R0_SM_STATES_IX3__LIST_TLV_STATE___M 0x0000001C +#define UMAC_TQM_R0_SM_STATES_IX3__LIST_TLV_STATE___S 2 +#define UMAC_TQM_R0_SM_STATES_IX3__DATA_ALIGN_SM___M 0x00000003 +#define UMAC_TQM_R0_SM_STATES_IX3__DATA_ALIGN_SM___S 0 +#define UMAC_TQM_R0_SM_STATES_IX3___M 0x00000FFF +#define UMAC_TQM_R0_SM_STATES_IX3___S 0 + +#define UMAC_TQM_R0_MISC_CFG (0x00A3C4F8) +#define UMAC_TQM_R0_MISC_CFG___RWC QCSR_REG_RW +#define UMAC_TQM_R0_MISC_CFG___POR 0x00006FE0 +#define UMAC_TQM_R0_MISC_CFG__STATUS1_WRITE_POSTED___POR 0x0 +#define UMAC_TQM_R0_MISC_CFG__STATUS_WRITE_POSTED___POR 0x0 +#define UMAC_TQM_R0_MISC_CFG__UPDATE_FW2TQM_TP_AT_8W_BOUNDARY___POR 0x0 +#define UMAC_TQM_R0_MISC_CFG__UPDATE_SW2TQM_TP_AT_8W_BOUNDARY___POR 0x0 +#define UMAC_TQM_R0_MISC_CFG__UPDATE_TCL2TQM_TP_AT_8W_BOUNDARY___POR 0x0 +#define UMAC_TQM_R0_MISC_CFG__ENABLE_FILTER_GEN_MPDU_EMPTY_STATUS___POR 0x0 +#define UMAC_TQM_R0_MISC_CFG__ENABLE_INVALIDATE_CACHE_FOR_INVALID_DESC___POR 0x0 +#define UMAC_TQM_R0_MISC_CFG__ENABLE_BA_PROC_DURING_FLUSH___POR 0x0 +#define UMAC_TQM_R0_MISC_CFG__WRITE_CMD_SWAP_BIT___POR 0x0 +#define UMAC_TQM_R0_MISC_CFG__WRITE_CMD_POSTED___POR 0x1 +#define UMAC_TQM_R0_MISC_CFG__DESC_PTR_RELEASE_POSTED___POR 0x1 +#define UMAC_TQM_R0_MISC_CFG__ASYNC_CMD_STATUS_NUMBER_SELECT___POR 0x0 +#define UMAC_TQM_R0_MISC_CFG__FW_TX_NOTIFY_REM_MSDU___POR 0x1 +#define UMAC_TQM_R0_MISC_CFG__FW_TX_NOTIFY_LIST_MPDU___POR 0x1 +#define UMAC_TQM_R0_MISC_CFG__FW_TX_NOTIFY_GEN_MPDU___POR 0x1 +#define UMAC_TQM_R0_MISC_CFG__FW_TX_NOTIFY_REM_MPDU___POR 0x1 +#define UMAC_TQM_R0_MISC_CFG__FW_TX_NOTIFY_ACKED_MPDU___POR 0x1 +#define UMAC_TQM_R0_MISC_CFG__FORCE_TO_REPORT_STATUS___POR 0x1 +#define UMAC_TQM_R0_MISC_CFG__LIST_MPDU_POSTED___POR 0x1 +#define UMAC_TQM_R0_MISC_CFG__LIST_MPDU_SWAP_BIT___POR 0x0 +#define UMAC_TQM_R0_MISC_CFG__LIST_MPDU_SECURITY_BIT___POR 0x0 +#define UMAC_TQM_R0_MISC_CFG__GEN_MPDU_POSTED___POR 0x0 +#define UMAC_TQM_R0_MISC_CFG__GEN_MPDU_SWAP_BIT___POR 0x0 +#define UMAC_TQM_R0_MISC_CFG__GEN_MPDU_SECURITY_BIT___POR 0x0 +#define UMAC_TQM_R0_MISC_CFG__STATUS1_WRITE_POSTED___M 0x00800000 +#define UMAC_TQM_R0_MISC_CFG__STATUS1_WRITE_POSTED___S 23 +#define UMAC_TQM_R0_MISC_CFG__STATUS_WRITE_POSTED___M 0x00400000 +#define UMAC_TQM_R0_MISC_CFG__STATUS_WRITE_POSTED___S 22 +#define UMAC_TQM_R0_MISC_CFG__UPDATE_FW2TQM_TP_AT_8W_BOUNDARY___M 0x00200000 +#define UMAC_TQM_R0_MISC_CFG__UPDATE_FW2TQM_TP_AT_8W_BOUNDARY___S 21 +#define UMAC_TQM_R0_MISC_CFG__UPDATE_SW2TQM_TP_AT_8W_BOUNDARY___M 0x00100000 +#define UMAC_TQM_R0_MISC_CFG__UPDATE_SW2TQM_TP_AT_8W_BOUNDARY___S 20 +#define UMAC_TQM_R0_MISC_CFG__UPDATE_TCL2TQM_TP_AT_8W_BOUNDARY___M 0x00080000 +#define UMAC_TQM_R0_MISC_CFG__UPDATE_TCL2TQM_TP_AT_8W_BOUNDARY___S 19 +#define UMAC_TQM_R0_MISC_CFG__ENABLE_FILTER_GEN_MPDU_EMPTY_STATUS___M 0x00040000 +#define UMAC_TQM_R0_MISC_CFG__ENABLE_FILTER_GEN_MPDU_EMPTY_STATUS___S 18 +#define UMAC_TQM_R0_MISC_CFG__ENABLE_INVALIDATE_CACHE_FOR_INVALID_DESC___M 0x00020000 +#define UMAC_TQM_R0_MISC_CFG__ENABLE_INVALIDATE_CACHE_FOR_INVALID_DESC___S 17 +#define UMAC_TQM_R0_MISC_CFG__ENABLE_BA_PROC_DURING_FLUSH___M 0x00010000 +#define UMAC_TQM_R0_MISC_CFG__ENABLE_BA_PROC_DURING_FLUSH___S 16 +#define UMAC_TQM_R0_MISC_CFG__WRITE_CMD_SWAP_BIT___M 0x00008000 +#define UMAC_TQM_R0_MISC_CFG__WRITE_CMD_SWAP_BIT___S 15 +#define UMAC_TQM_R0_MISC_CFG__WRITE_CMD_POSTED___M 0x00004000 +#define UMAC_TQM_R0_MISC_CFG__WRITE_CMD_POSTED___S 14 +#define UMAC_TQM_R0_MISC_CFG__DESC_PTR_RELEASE_POSTED___M 0x00002000 +#define UMAC_TQM_R0_MISC_CFG__DESC_PTR_RELEASE_POSTED___S 13 +#define UMAC_TQM_R0_MISC_CFG__ASYNC_CMD_STATUS_NUMBER_SELECT___M 0x00001000 +#define UMAC_TQM_R0_MISC_CFG__ASYNC_CMD_STATUS_NUMBER_SELECT___S 12 +#define UMAC_TQM_R0_MISC_CFG__FW_TX_NOTIFY_REM_MSDU___M 0x00000800 +#define UMAC_TQM_R0_MISC_CFG__FW_TX_NOTIFY_REM_MSDU___S 11 +#define UMAC_TQM_R0_MISC_CFG__FW_TX_NOTIFY_LIST_MPDU___M 0x00000400 +#define UMAC_TQM_R0_MISC_CFG__FW_TX_NOTIFY_LIST_MPDU___S 10 +#define UMAC_TQM_R0_MISC_CFG__FW_TX_NOTIFY_GEN_MPDU___M 0x00000200 +#define UMAC_TQM_R0_MISC_CFG__FW_TX_NOTIFY_GEN_MPDU___S 9 +#define UMAC_TQM_R0_MISC_CFG__FW_TX_NOTIFY_REM_MPDU___M 0x00000100 +#define UMAC_TQM_R0_MISC_CFG__FW_TX_NOTIFY_REM_MPDU___S 8 +#define UMAC_TQM_R0_MISC_CFG__FW_TX_NOTIFY_ACKED_MPDU___M 0x00000080 +#define UMAC_TQM_R0_MISC_CFG__FW_TX_NOTIFY_ACKED_MPDU___S 7 +#define UMAC_TQM_R0_MISC_CFG__FORCE_TO_REPORT_STATUS___M 0x00000040 +#define UMAC_TQM_R0_MISC_CFG__FORCE_TO_REPORT_STATUS___S 6 +#define UMAC_TQM_R0_MISC_CFG__LIST_MPDU_POSTED___M 0x00000020 +#define UMAC_TQM_R0_MISC_CFG__LIST_MPDU_POSTED___S 5 +#define UMAC_TQM_R0_MISC_CFG__LIST_MPDU_SWAP_BIT___M 0x00000010 +#define UMAC_TQM_R0_MISC_CFG__LIST_MPDU_SWAP_BIT___S 4 +#define UMAC_TQM_R0_MISC_CFG__LIST_MPDU_SECURITY_BIT___M 0x00000008 +#define UMAC_TQM_R0_MISC_CFG__LIST_MPDU_SECURITY_BIT___S 3 +#define UMAC_TQM_R0_MISC_CFG__GEN_MPDU_POSTED___M 0x00000004 +#define UMAC_TQM_R0_MISC_CFG__GEN_MPDU_POSTED___S 2 +#define UMAC_TQM_R0_MISC_CFG__GEN_MPDU_SWAP_BIT___M 0x00000002 +#define UMAC_TQM_R0_MISC_CFG__GEN_MPDU_SWAP_BIT___S 1 +#define UMAC_TQM_R0_MISC_CFG__GEN_MPDU_SECURITY_BIT___M 0x00000001 +#define UMAC_TQM_R0_MISC_CFG__GEN_MPDU_SECURITY_BIT___S 0 +#define UMAC_TQM_R0_MISC_CFG___M 0x00FFFFFF +#define UMAC_TQM_R0_MISC_CFG___S 0 + +#define UMAC_TQM_R0_CLKGATE_CTRL (0x00A3C4FC) +#define UMAC_TQM_R0_CLKGATE_CTRL___RWC QCSR_REG_RW +#define UMAC_TQM_R0_CLKGATE_CTRL___POR 0x80000000 +#define UMAC_TQM_R0_CLKGATE_CTRL__CLOCK_ENS_EXTEND___POR 0x1 +#define UMAC_TQM_R0_CLKGATE_CTRL__CLK_GATE_DISABLE_APB___POR 0x0 +#define UMAC_TQM_R0_CLKGATE_CTRL__UPDATE_QUEUE_DESC_CLK_GATE_DISABLE___POR 0x0 +#define UMAC_TQM_R0_CLKGATE_CTRL__CACHE_MEM_CLK_GATE_DISABLE___POR 0x0 +#define UMAC_TQM_R0_CLKGATE_CTRL__TLV_IF_CLK_GATE_DISABLE___POR 0x0 +#define UMAC_TQM_R0_CLKGATE_CTRL__GXI_IF_CLK_GATE_DISABLE___POR 0x0 +#define UMAC_TQM_R0_CLKGATE_CTRL__AXI_IF_CLK_GATE_DISABLE___POR 0x0 +#define UMAC_TQM_R0_CLKGATE_CTRL__COMMON_LOGIC_CLK_GATE_DISABLE___POR 0x0 +#define UMAC_TQM_R0_CLKGATE_CTRL__FLUSH_UNBLK_CACHE_CLK_GATE_DISABLE___POR 0x0 +#define UMAC_TQM_R0_CLKGATE_CTRL__GET_MPDU_HEAD_INFO_CLK_GATE_DISABLE___POR 0x0 +#define UMAC_TQM_R0_CLKGATE_CTRL__REM_MSDU_CLK_GATE_DISABLE___POR 0x0 +#define UMAC_TQM_R0_CLKGATE_CTRL__REM_MPDU_CLK_GATE_DISABLE___POR 0x0 +#define UMAC_TQM_R0_CLKGATE_CTRL__GET_QUEUE_STATS_CLK_GATE_DISABLE___POR 0x0 +#define UMAC_TQM_R0_CLKGATE_CTRL__TX_MPDU_COUNT_CLK_GATE_DISABLE___POR 0x0 +#define UMAC_TQM_R0_CLKGATE_CTRL__LIST_MPDU_CLK_GATE_DISABLE___POR 0x0 +#define UMAC_TQM_R0_CLKGATE_CTRL__GEN_MPDU_CLK_GATE_DISABLE___POR 0x0 +#define UMAC_TQM_R0_CLKGATE_CTRL__ADD_MSDU_CLK_GATE_DISABLE___POR 0x0 +#define UMAC_TQM_R0_CLKGATE_CTRL__ARBITER_CLK_GATE_DISABLE___POR 0x0 +#define UMAC_TQM_R0_CLKGATE_CTRL__PREFETCH_CLK_GATE_DISABLE___POR 0x0 +#define UMAC_TQM_R0_CLKGATE_CTRL__CACHE_CTL_CLK_GATE_DISABLE___POR 0x0 +#define UMAC_TQM_R0_CLKGATE_CTRL__TOP_CLK_GATE_DISABLE___POR 0x0 +#define UMAC_TQM_R0_CLKGATE_CTRL__CLOCK_ENS_EXTEND___M 0x80000000 +#define UMAC_TQM_R0_CLKGATE_CTRL__CLOCK_ENS_EXTEND___S 31 +#define UMAC_TQM_R0_CLKGATE_CTRL__CLK_GATE_DISABLE_APB___M 0x01000000 +#define UMAC_TQM_R0_CLKGATE_CTRL__CLK_GATE_DISABLE_APB___S 24 +#define UMAC_TQM_R0_CLKGATE_CTRL__UPDATE_QUEUE_DESC_CLK_GATE_DISABLE___M 0x00040000 +#define UMAC_TQM_R0_CLKGATE_CTRL__UPDATE_QUEUE_DESC_CLK_GATE_DISABLE___S 18 +#define UMAC_TQM_R0_CLKGATE_CTRL__CACHE_MEM_CLK_GATE_DISABLE___M 0x00020000 +#define UMAC_TQM_R0_CLKGATE_CTRL__CACHE_MEM_CLK_GATE_DISABLE___S 17 +#define UMAC_TQM_R0_CLKGATE_CTRL__TLV_IF_CLK_GATE_DISABLE___M 0x00010000 +#define UMAC_TQM_R0_CLKGATE_CTRL__TLV_IF_CLK_GATE_DISABLE___S 16 +#define UMAC_TQM_R0_CLKGATE_CTRL__GXI_IF_CLK_GATE_DISABLE___M 0x00008000 +#define UMAC_TQM_R0_CLKGATE_CTRL__GXI_IF_CLK_GATE_DISABLE___S 15 +#define UMAC_TQM_R0_CLKGATE_CTRL__AXI_IF_CLK_GATE_DISABLE___M 0x00004000 +#define UMAC_TQM_R0_CLKGATE_CTRL__AXI_IF_CLK_GATE_DISABLE___S 14 +#define UMAC_TQM_R0_CLKGATE_CTRL__COMMON_LOGIC_CLK_GATE_DISABLE___M 0x00002000 +#define UMAC_TQM_R0_CLKGATE_CTRL__COMMON_LOGIC_CLK_GATE_DISABLE___S 13 +#define UMAC_TQM_R0_CLKGATE_CTRL__FLUSH_UNBLK_CACHE_CLK_GATE_DISABLE___M 0x00001000 +#define UMAC_TQM_R0_CLKGATE_CTRL__FLUSH_UNBLK_CACHE_CLK_GATE_DISABLE___S 12 +#define UMAC_TQM_R0_CLKGATE_CTRL__GET_MPDU_HEAD_INFO_CLK_GATE_DISABLE___M 0x00000800 +#define UMAC_TQM_R0_CLKGATE_CTRL__GET_MPDU_HEAD_INFO_CLK_GATE_DISABLE___S 11 +#define UMAC_TQM_R0_CLKGATE_CTRL__REM_MSDU_CLK_GATE_DISABLE___M 0x00000400 +#define UMAC_TQM_R0_CLKGATE_CTRL__REM_MSDU_CLK_GATE_DISABLE___S 10 +#define UMAC_TQM_R0_CLKGATE_CTRL__REM_MPDU_CLK_GATE_DISABLE___M 0x00000200 +#define UMAC_TQM_R0_CLKGATE_CTRL__REM_MPDU_CLK_GATE_DISABLE___S 9 +#define UMAC_TQM_R0_CLKGATE_CTRL__GET_QUEUE_STATS_CLK_GATE_DISABLE___M 0x00000100 +#define UMAC_TQM_R0_CLKGATE_CTRL__GET_QUEUE_STATS_CLK_GATE_DISABLE___S 8 +#define UMAC_TQM_R0_CLKGATE_CTRL__TX_MPDU_COUNT_CLK_GATE_DISABLE___M 0x00000080 +#define UMAC_TQM_R0_CLKGATE_CTRL__TX_MPDU_COUNT_CLK_GATE_DISABLE___S 7 +#define UMAC_TQM_R0_CLKGATE_CTRL__LIST_MPDU_CLK_GATE_DISABLE___M 0x00000040 +#define UMAC_TQM_R0_CLKGATE_CTRL__LIST_MPDU_CLK_GATE_DISABLE___S 6 +#define UMAC_TQM_R0_CLKGATE_CTRL__GEN_MPDU_CLK_GATE_DISABLE___M 0x00000020 +#define UMAC_TQM_R0_CLKGATE_CTRL__GEN_MPDU_CLK_GATE_DISABLE___S 5 +#define UMAC_TQM_R0_CLKGATE_CTRL__ADD_MSDU_CLK_GATE_DISABLE___M 0x00000010 +#define UMAC_TQM_R0_CLKGATE_CTRL__ADD_MSDU_CLK_GATE_DISABLE___S 4 +#define UMAC_TQM_R0_CLKGATE_CTRL__ARBITER_CLK_GATE_DISABLE___M 0x00000008 +#define UMAC_TQM_R0_CLKGATE_CTRL__ARBITER_CLK_GATE_DISABLE___S 3 +#define UMAC_TQM_R0_CLKGATE_CTRL__PREFETCH_CLK_GATE_DISABLE___M 0x00000004 +#define UMAC_TQM_R0_CLKGATE_CTRL__PREFETCH_CLK_GATE_DISABLE___S 2 +#define UMAC_TQM_R0_CLKGATE_CTRL__CACHE_CTL_CLK_GATE_DISABLE___M 0x00000002 +#define UMAC_TQM_R0_CLKGATE_CTRL__CACHE_CTL_CLK_GATE_DISABLE___S 1 +#define UMAC_TQM_R0_CLKGATE_CTRL__TOP_CLK_GATE_DISABLE___M 0x00000001 +#define UMAC_TQM_R0_CLKGATE_CTRL__TOP_CLK_GATE_DISABLE___S 0 +#define UMAC_TQM_R0_CLKGATE_CTRL___M 0x8107FFFF +#define UMAC_TQM_R0_CLKGATE_CTRL___S 0 + +#define UMAC_TQM_R0_FLUSH_CONTROL_0 (0x00A3C500) +#define UMAC_TQM_R0_FLUSH_CONTROL_0___RWC QCSR_REG_RW +#define UMAC_TQM_R0_FLUSH_CONTROL_0___POR 0x00000000 +#define UMAC_TQM_R0_FLUSH_CONTROL_0__REQUEST___POR 0x0 +#define UMAC_TQM_R0_FLUSH_CONTROL_0__REQUEST___M 0x00000001 +#define UMAC_TQM_R0_FLUSH_CONTROL_0__REQUEST___S 0 +#define UMAC_TQM_R0_FLUSH_CONTROL_0___M 0x00000001 +#define UMAC_TQM_R0_FLUSH_CONTROL_0___S 0 + +#define UMAC_TQM_R0_HWSCH_FLUSH_ACK_ADDRESS_LO_0 (0x00A3C50C) +#define UMAC_TQM_R0_HWSCH_FLUSH_ACK_ADDRESS_LO_0___RWC QCSR_REG_RW +#define UMAC_TQM_R0_HWSCH_FLUSH_ACK_ADDRESS_LO_0___POR 0x00000000 +#define UMAC_TQM_R0_HWSCH_FLUSH_ACK_ADDRESS_LO_0__VALUE___POR 0x00000000 +#define UMAC_TQM_R0_HWSCH_FLUSH_ACK_ADDRESS_LO_0__VALUE___M 0xFFFFFFFF +#define UMAC_TQM_R0_HWSCH_FLUSH_ACK_ADDRESS_LO_0__VALUE___S 0 +#define UMAC_TQM_R0_HWSCH_FLUSH_ACK_ADDRESS_LO_0___M 0xFFFFFFFF +#define UMAC_TQM_R0_HWSCH_FLUSH_ACK_ADDRESS_LO_0___S 0 + +#define UMAC_TQM_R0_HWSCH_FLUSH_ACK_ADDRESS_HI_0 (0x00A3C510) +#define UMAC_TQM_R0_HWSCH_FLUSH_ACK_ADDRESS_HI_0___RWC QCSR_REG_RW +#define UMAC_TQM_R0_HWSCH_FLUSH_ACK_ADDRESS_HI_0___POR 0x00000000 +#define UMAC_TQM_R0_HWSCH_FLUSH_ACK_ADDRESS_HI_0__VALUE___POR 0x00 +#define UMAC_TQM_R0_HWSCH_FLUSH_ACK_ADDRESS_HI_0__VALUE___M 0x000000FF +#define UMAC_TQM_R0_HWSCH_FLUSH_ACK_ADDRESS_HI_0__VALUE___S 0 +#define UMAC_TQM_R0_HWSCH_FLUSH_ACK_ADDRESS_HI_0___M 0x000000FF +#define UMAC_TQM_R0_HWSCH_FLUSH_ACK_ADDRESS_HI_0___S 0 + +#define UMAC_TQM_R0_HWSCH_FLUSH_ACK_DATA_0 (0x00A3C524) +#define UMAC_TQM_R0_HWSCH_FLUSH_ACK_DATA_0___RWC QCSR_REG_RW +#define UMAC_TQM_R0_HWSCH_FLUSH_ACK_DATA_0___POR 0x00000000 +#define UMAC_TQM_R0_HWSCH_FLUSH_ACK_DATA_0__VALUE___POR 0x00000000 +#define UMAC_TQM_R0_HWSCH_FLUSH_ACK_DATA_0__VALUE___M 0xFFFFFFFF +#define UMAC_TQM_R0_HWSCH_FLUSH_ACK_DATA_0__VALUE___S 0 +#define UMAC_TQM_R0_HWSCH_FLUSH_ACK_DATA_0___M 0xFFFFFFFF +#define UMAC_TQM_R0_HWSCH_FLUSH_ACK_DATA_0___S 0 + +#define UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER0 (0x00A3C530) +#define UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER0___RWC QCSR_REG_RW +#define UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER0___POR 0x00000000 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER0__LINK_DESCRIPTOR_COUNTER___POR 0x000000 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER0__LINK_DESCRIPTOR_COUNTER___M 0x00FFFFFF +#define UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER0__LINK_DESCRIPTOR_COUNTER___S 0 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER0___M 0x00FFFFFF +#define UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER0___S 0 + +#define UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER1 (0x00A3C534) +#define UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER1___RWC QCSR_REG_RW +#define UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER1___POR 0x00000000 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER1__LINK_DESCRIPTOR_COUNTER___POR 0x000000 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER1__LINK_DESCRIPTOR_COUNTER___M 0x00FFFFFF +#define UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER1__LINK_DESCRIPTOR_COUNTER___S 0 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER1___M 0x00FFFFFF +#define UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER1___S 0 + +#define UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER2 (0x00A3C538) +#define UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER2___RWC QCSR_REG_RW +#define UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER2___POR 0x00000000 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER2__LINK_DESCRIPTOR_COUNTER___POR 0x000000 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER2__LINK_DESCRIPTOR_COUNTER___M 0x00FFFFFF +#define UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER2__LINK_DESCRIPTOR_COUNTER___S 0 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER2___M 0x00FFFFFF +#define UMAC_TQM_R0_LINK_DESCRIPTOR_COUNTER2___S 0 + +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0 (0x00A3C53C) +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0___RWC QCSR_REG_RW +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0___POR 0x00FFFFFF +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0__MESSAGE_ENABLE___POR 0x0 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0__MESSAGE_GENERATED___POR 0x0 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0__PAUSE_ENABLE___POR 0x0 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0__PAUSE_STATUS___POR 0x0 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0__LINK_DESCRIPTOR_COUNTER0_THRESHOLD___POR 0xFFFFFF +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0__MESSAGE_ENABLE___M 0x80000000 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0__MESSAGE_ENABLE___S 31 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0__MESSAGE_GENERATED___M 0x40000000 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0__MESSAGE_GENERATED___S 30 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0__PAUSE_ENABLE___M 0x20000000 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0__PAUSE_ENABLE___S 29 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0__PAUSE_STATUS___M 0x10000000 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0__PAUSE_STATUS___S 28 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0__LINK_DESCRIPTOR_COUNTER0_THRESHOLD___M 0x00FFFFFF +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0__LINK_DESCRIPTOR_COUNTER0_THRESHOLD___S 0 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0___M 0xF0FFFFFF +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD0___S 0 + +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1 (0x00A3C540) +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1___RWC QCSR_REG_RW +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1___POR 0x00000000 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1__MESSAGE_ENABLE___POR 0x0 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1__MESSAGE_GENERATED___POR 0x0 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1__PAUSE_ENABLE___POR 0x0 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1__PAUSE_STATUS___POR 0x0 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1__LINK_DESCRIPTOR_COUNTER1_THRESHOLD___POR 0x000000 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1__MESSAGE_ENABLE___M 0x80000000 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1__MESSAGE_ENABLE___S 31 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1__MESSAGE_GENERATED___M 0x40000000 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1__MESSAGE_GENERATED___S 30 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1__PAUSE_ENABLE___M 0x20000000 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1__PAUSE_ENABLE___S 29 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1__PAUSE_STATUS___M 0x10000000 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1__PAUSE_STATUS___S 28 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1__LINK_DESCRIPTOR_COUNTER1_THRESHOLD___M 0x00FFFFFF +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1__LINK_DESCRIPTOR_COUNTER1_THRESHOLD___S 0 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1___M 0xF0FFFFFF +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD1___S 0 + +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2 (0x00A3C544) +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2___RWC QCSR_REG_RW +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2___POR 0x00000000 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2__MESSAGE_ENABLE___POR 0x0 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2__MESSAGE_GENERATED___POR 0x0 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2__PAUSE_ENABLE___POR 0x0 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2__PAUSE_STATUS___POR 0x0 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2__LINK_DESCRIPTOR_COUNTER2_THRESHOLD___POR 0x000000 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2__MESSAGE_ENABLE___M 0x80000000 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2__MESSAGE_ENABLE___S 31 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2__MESSAGE_GENERATED___M 0x40000000 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2__MESSAGE_GENERATED___S 30 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2__PAUSE_ENABLE___M 0x20000000 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2__PAUSE_ENABLE___S 29 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2__PAUSE_STATUS___M 0x10000000 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2__PAUSE_STATUS___S 28 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2__LINK_DESCRIPTOR_COUNTER2_THRESHOLD___M 0x00FFFFFF +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2__LINK_DESCRIPTOR_COUNTER2_THRESHOLD___S 0 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2___M 0xF0FFFFFF +#define UMAC_TQM_R0_LINK_DESCRIPTOR_THRESHOLD2___S 0 + +#define UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD (0x00A3C548) +#define UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD___RWC QCSR_REG_RW +#define UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD___POR 0x00000000 +#define UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD__MESSAGE_ENABLE___POR 0x0 +#define UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD__MESSAGE_GENERATED___POR 0x0 +#define UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD__PAUSE_ENABLE___POR 0x0 +#define UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD__PAUSE_STATUS___POR 0x0 +#define UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD__LINK_DESCRIPTOR_COUNTER_SUM_THRESHOLD___POR 0x0000000 +#define UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD__MESSAGE_ENABLE___M 0x80000000 +#define UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD__MESSAGE_ENABLE___S 31 +#define UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD__MESSAGE_GENERATED___M 0x40000000 +#define UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD__MESSAGE_GENERATED___S 30 +#define UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD__PAUSE_ENABLE___M 0x20000000 +#define UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD__PAUSE_ENABLE___S 29 +#define UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD__PAUSE_STATUS___M 0x10000000 +#define UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD__PAUSE_STATUS___S 28 +#define UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD__LINK_DESCRIPTOR_COUNTER_SUM_THRESHOLD___M 0x03FFFFFF +#define UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD__LINK_DESCRIPTOR_COUNTER_SUM_THRESHOLD___S 0 +#define UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD___M 0xF3FFFFFF +#define UMAC_TQM_R0_AGGREGATE_LINK_DESCRIPTOR_THRESHOLD___S 0 + +#define UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL (0x00A3C54C) +#define UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL___RWC QCSR_REG_RW +#define UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL___POR 0x00FF0000 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_STATUS_FW2TQM___POR 0x0 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_STATUS_SW2TQM___POR 0x0 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_STATUS_TCL2TQM___POR 0x0 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__UNPAUSE_LINK_DESC_THRESHOLD___POR 0x0FF +#define UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_FW2TQM___POR 0x0 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_SW2TQM___POR 0x0 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_TCL2TQM___POR 0x0 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__LINK_DESC_THRESHOLD___POR 0x000 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_STATUS_FW2TQM___M 0x80000000 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_STATUS_FW2TQM___S 31 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_STATUS_SW2TQM___M 0x40000000 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_STATUS_SW2TQM___S 30 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_STATUS_TCL2TQM___M 0x20000000 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_STATUS_TCL2TQM___S 29 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__UNPAUSE_LINK_DESC_THRESHOLD___M 0x03FF0000 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__UNPAUSE_LINK_DESC_THRESHOLD___S 16 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_FW2TQM___M 0x00001000 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_FW2TQM___S 12 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_SW2TQM___M 0x00000800 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_SW2TQM___S 11 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_TCL2TQM___M 0x00000400 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__BLOCK_TCL2TQM___S 10 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__LINK_DESC_THRESHOLD___M 0x000003FF +#define UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL__LINK_DESC_THRESHOLD___S 0 +#define UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL___M 0xE3FF1FFF +#define UMAC_TQM_R0_LINK_DESCRIPTOR_PRIORITY_CONTROL___S 0 + +#define UMAC_TQM_R0_DESC_PTR_RELEASE (0x00A3C550) +#define UMAC_TQM_R0_DESC_PTR_RELEASE___RWC QCSR_REG_RW +#define UMAC_TQM_R0_DESC_PTR_RELEASE___POR 0x00001F40 +#define UMAC_TQM_R0_DESC_PTR_RELEASE__THRESH___POR 0x1F +#define UMAC_TQM_R0_DESC_PTR_RELEASE__TIMEOUT___POR 0x40 +#define UMAC_TQM_R0_DESC_PTR_RELEASE__THRESH___M 0x0000FF00 +#define UMAC_TQM_R0_DESC_PTR_RELEASE__THRESH___S 8 +#define UMAC_TQM_R0_DESC_PTR_RELEASE__TIMEOUT___M 0x000000FF +#define UMAC_TQM_R0_DESC_PTR_RELEASE__TIMEOUT___S 0 +#define UMAC_TQM_R0_DESC_PTR_RELEASE___M 0x0000FFFF +#define UMAC_TQM_R0_DESC_PTR_RELEASE___S 0 + +#define UMAC_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS (0x00A3C554) +#define UMAC_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS__LINE_ADDRESS___POR 0x000 +#define UMAC_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS__LOCK_ID___POR 0x0 +#define UMAC_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS__IS_LOCKED___POR 0x0 +#define UMAC_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS__LINE_ADDRESS___M 0x0000FFE0 +#define UMAC_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS__LINE_ADDRESS___S 5 +#define UMAC_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS__LOCK_ID___M 0x0000001E +#define UMAC_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS__LOCK_ID___S 1 +#define UMAC_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS__IS_LOCKED___M 0x00000001 +#define UMAC_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS__IS_LOCKED___S 0 +#define UMAC_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS___M 0x0000FFFF +#define UMAC_TQM_R0_FLOW_QUEUE_DESC_CACHE_LINE_STATUS___S 0 + +#define UMAC_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS (0x00A3C558) +#define UMAC_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS__LINE_ADDRESS___POR 0x0000 +#define UMAC_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS__IS_LOCKED___POR 0x0 +#define UMAC_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS__LINE_ADDRESS___M 0x0000FFFE +#define UMAC_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS__LINE_ADDRESS___S 1 +#define UMAC_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS__IS_LOCKED___M 0x00000001 +#define UMAC_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS__IS_LOCKED___S 0 +#define UMAC_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS___M 0x0000FFFF +#define UMAC_TQM_R0_FLOW_QUEUE_DESC_ADD_MSDU_CACHE_LINE_STATUS___S 0 + +#define UMAC_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS (0x00A3C55C) +#define UMAC_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS__LINE_ADDRESS___POR 0x000 +#define UMAC_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS__LOCK_ID___POR 0x0 +#define UMAC_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS__IS_LOCKED___POR 0x0 +#define UMAC_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS__LINE_ADDRESS___M 0x0000FFE0 +#define UMAC_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS__LINE_ADDRESS___S 5 +#define UMAC_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS__LOCK_ID___M 0x0000001E +#define UMAC_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS__LOCK_ID___S 1 +#define UMAC_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS__IS_LOCKED___M 0x00000001 +#define UMAC_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS__IS_LOCKED___S 0 +#define UMAC_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS___M 0x0000FFFF +#define UMAC_TQM_R0_MPDU_QUEUE_HEAD_DESC_CACHE_LINE_STATUS___S 0 + +#define UMAC_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS (0x00A3C560) +#define UMAC_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS__LINE_ADDRESS___POR 0x000 +#define UMAC_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS__LOCK_ID___POR 0x0 +#define UMAC_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS__IS_LOCKED___POR 0x0 +#define UMAC_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS__LINE_ADDRESS___M 0x0000FFE0 +#define UMAC_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS__LINE_ADDRESS___S 5 +#define UMAC_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS__LOCK_ID___M 0x0000001E +#define UMAC_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS__LOCK_ID___S 1 +#define UMAC_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS__IS_LOCKED___M 0x00000001 +#define UMAC_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS__IS_LOCKED___S 0 +#define UMAC_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS___M 0x0000FFFF +#define UMAC_TQM_R0_MSDU_LINK_DESC_CACHE_LINE_STATUS___S 0 + +#define UMAC_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS (0x00A3C564) +#define UMAC_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS__LINE_ADDRESS___POR 0x000 +#define UMAC_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS__IS_LOCKED___POR 0x0 +#define UMAC_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS__LINE_ADDRESS___M 0x0000FFE0 +#define UMAC_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS__LINE_ADDRESS___S 5 +#define UMAC_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS__IS_LOCKED___M 0x00000001 +#define UMAC_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS__IS_LOCKED___S 0 +#define UMAC_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS___M 0x0000FFE1 +#define UMAC_TQM_R0_MSDU_LINK_DESC_ADD_MSDU_CACHE_LINE_STATUS___S 0 + +#define UMAC_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS (0x00A3C568) +#define UMAC_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS__LINE_ADDRESS___POR 0x000 +#define UMAC_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS__LOCK_ID___POR 0x0 +#define UMAC_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS__IS_LOCKED___POR 0x0 +#define UMAC_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS__LINE_ADDRESS___M 0x0000FFE0 +#define UMAC_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS__LINE_ADDRESS___S 5 +#define UMAC_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS__LOCK_ID___M 0x0000001E +#define UMAC_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS__LOCK_ID___S 1 +#define UMAC_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS__IS_LOCKED___M 0x00000001 +#define UMAC_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS__IS_LOCKED___S 0 +#define UMAC_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS___M 0x0000FFFF +#define UMAC_TQM_R0_MPDU_LINK_DESC_0_DESC_CACHE_LINE_STATUS___S 0 + +#define UMAC_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS (0x00A3C56C) +#define UMAC_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS__LINE_ADDRESS___POR 0x000 +#define UMAC_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS__LOCK_ID___POR 0x0 +#define UMAC_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS__IS_LOCKED___POR 0x0 +#define UMAC_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS__LINE_ADDRESS___M 0x0000FFE0 +#define UMAC_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS__LINE_ADDRESS___S 5 +#define UMAC_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS__LOCK_ID___M 0x0000001E +#define UMAC_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS__LOCK_ID___S 1 +#define UMAC_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS__IS_LOCKED___M 0x00000001 +#define UMAC_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS__IS_LOCKED___S 0 +#define UMAC_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS___M 0x0000FFFF +#define UMAC_TQM_R0_MPDU_LINK_DESC_1_CACHE_LINE_STATUS___S 0 + +#define UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS (0x00A3C570) +#define UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS__LINE_ADDRESS___POR 0x000 +#define UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS__LOCK_ID___POR 0x0 +#define UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS__IS_LOCKED___POR 0x0 +#define UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS__LINE_ADDRESS___M 0x0000FFE0 +#define UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS__LINE_ADDRESS___S 5 +#define UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS__LOCK_ID___M 0x0000001E +#define UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS__LOCK_ID___S 1 +#define UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS__IS_LOCKED___M 0x00000001 +#define UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS__IS_LOCKED___S 0 +#define UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS___M 0x0000FFFF +#define UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_0_CACHE_LINE_STATUS___S 0 + +#define UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS (0x00A3C574) +#define UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS___RWC QCSR_REG_RO +#define UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS___POR 0x00000000 +#define UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS__LINE_ADDRESS___POR 0x000 +#define UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS__LOCK_ID___POR 0x0 +#define UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS__IS_LOCKED___POR 0x0 +#define UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS__LINE_ADDRESS___M 0x0000FFE0 +#define UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS__LINE_ADDRESS___S 5 +#define UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS__LOCK_ID___M 0x0000001E +#define UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS__LOCK_ID___S 1 +#define UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS__IS_LOCKED___M 0x00000001 +#define UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS__IS_LOCKED___S 0 +#define UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS___M 0x0000FFFF +#define UMAC_TQM_R0_MPDU_QUEUE_EXT_DESC_1_CACHE_LINE_STATUS___S 0 + +#define UMAC_TQM_R0_ERROR_STATUS_1 (0x00A3C578) +#define UMAC_TQM_R0_ERROR_STATUS_1___RWC QCSR_REG_RW +#define UMAC_TQM_R0_ERROR_STATUS_1___POR 0x00000000 +#define UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_UPDATE_TX_MPDU_COUNT___POR 0x0 +#define UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_REM_MSDU___POR 0x0 +#define UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_REM_MPDU___POR 0x0 +#define UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_LIST_MPDU___POR 0x0 +#define UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_GET_QUEUE_STATS___POR 0x0 +#define UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_GET_MPDU_HEAD_INFO___POR 0x0 +#define UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_GEN_MPDU___POR 0x0 +#define UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_ADD_MSDU___POR 0x0 +#define UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_UPDATE_TX_MPDU_COUNT___M 0x00000080 +#define UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_UPDATE_TX_MPDU_COUNT___S 7 +#define UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_REM_MSDU___M 0x00000040 +#define UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_REM_MSDU___S 6 +#define UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_REM_MPDU___M 0x00000020 +#define UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_REM_MPDU___S 5 +#define UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_LIST_MPDU___M 0x00000010 +#define UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_LIST_MPDU___S 4 +#define UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_GET_QUEUE_STATS___M 0x00000008 +#define UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_GET_QUEUE_STATS___S 3 +#define UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_GET_MPDU_HEAD_INFO___M 0x00000004 +#define UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_GET_MPDU_HEAD_INFO___S 2 +#define UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_GEN_MPDU___M 0x00000002 +#define UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_GEN_MPDU___S 1 +#define UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_ADD_MSDU___M 0x00000001 +#define UMAC_TQM_R0_ERROR_STATUS_1__SW_PROG_ERROR_ADD_MSDU___S 0 +#define UMAC_TQM_R0_ERROR_STATUS_1___M 0x000000FF +#define UMAC_TQM_R0_ERROR_STATUS_1___S 0 + +#define UMAC_TQM_R0_TLV_IF (0x00A3C57C) +#define UMAC_TQM_R0_TLV_IF___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TLV_IF___POR 0x00000000 +#define UMAC_TQM_R0_TLV_IF__ASYNC_GP_FIFO_2_SYNC_RESET___POR 0x0 +#define UMAC_TQM_R0_TLV_IF__ASYNC_GP_FIFO_1_SYNC_RESET___POR 0x0 +#define UMAC_TQM_R0_TLV_IF__ASYNC_GP_FIFO_0_SYNC_RESET___POR 0x0 +#define UMAC_TQM_R0_TLV_IF__ASYNC_GP_FIFO_2_SYNC_RESET___M 0x00000004 +#define UMAC_TQM_R0_TLV_IF__ASYNC_GP_FIFO_2_SYNC_RESET___S 2 +#define UMAC_TQM_R0_TLV_IF__ASYNC_GP_FIFO_1_SYNC_RESET___M 0x00000002 +#define UMAC_TQM_R0_TLV_IF__ASYNC_GP_FIFO_1_SYNC_RESET___S 1 +#define UMAC_TQM_R0_TLV_IF__ASYNC_GP_FIFO_0_SYNC_RESET___M 0x00000001 +#define UMAC_TQM_R0_TLV_IF__ASYNC_GP_FIFO_0_SYNC_RESET___S 0 +#define UMAC_TQM_R0_TLV_IF___M 0x00000007 +#define UMAC_TQM_R0_TLV_IF___S 0 + +#define UMAC_TQM_R0_TQM_REFERENCE_TIMESTAMP (0x00A3C580) +#define UMAC_TQM_R0_TQM_REFERENCE_TIMESTAMP___RWC QCSR_REG_RO +#define UMAC_TQM_R0_TQM_REFERENCE_TIMESTAMP___POR 0x00000000 +#define UMAC_TQM_R0_TQM_REFERENCE_TIMESTAMP__TQM_REFERENCE_TIMESTAMP___POR 0x00000000 +#define UMAC_TQM_R0_TQM_REFERENCE_TIMESTAMP__TQM_REFERENCE_TIMESTAMP___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_REFERENCE_TIMESTAMP__TQM_REFERENCE_TIMESTAMP___S 0 +#define UMAC_TQM_R0_TQM_REFERENCE_TIMESTAMP___M 0xFFFFFFFF +#define UMAC_TQM_R0_TQM_REFERENCE_TIMESTAMP___S 0 + +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_n(n) (0x00A3C584+0x4*(n)) +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_n_nMIN 0 +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_n_nMAX 2 +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_n_ELEM 3 +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_n___RWC QCSR_REG_RO +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_n___POR 0x00000000 +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_n__MPDU_QUEUE_DEPTH___POR 0x0000 +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_n__SEQUENCE_NUMBER___POR 0x000 +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_n__MPDU_QUEUE_DEPTH___M 0x0FFFF000 +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_n__MPDU_QUEUE_DEPTH___S 12 +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_n__SEQUENCE_NUMBER___M 0x00000FFF +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_n__SEQUENCE_NUMBER___S 0 +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_n___M 0x0FFFFFFF +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_n___S 0 +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_0 (0x00A3C584) +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_0___RWC QCSR_REG_RO +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_0__MPDU_QUEUE_DEPTH___M 0x0FFFF000 +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_0__MPDU_QUEUE_DEPTH___S 12 +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_0__SEQUENCE_NUMBER___M 0x00000FFF +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_0__SEQUENCE_NUMBER___S 0 +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_1 (0x00A3C588) +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_1___RWC QCSR_REG_RO +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_1__MPDU_QUEUE_DEPTH___M 0x0FFFF000 +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_1__MPDU_QUEUE_DEPTH___S 12 +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_1__SEQUENCE_NUMBER___M 0x00000FFF +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_1__SEQUENCE_NUMBER___S 0 +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_2 (0x00A3C58C) +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_2___RWC QCSR_REG_RO +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_2__MPDU_QUEUE_DEPTH___M 0x0FFFF000 +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_2__MPDU_QUEUE_DEPTH___S 12 +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_2__SEQUENCE_NUMBER___M 0x00000FFF +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_DETAILS_MAC0_2__SEQUENCE_NUMBER___S 0 + +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_STATUS_MAC0 (0x00A3C618) +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_STATUS_MAC0___RWC QCSR_REG_RW +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_STATUS_MAC0___POR 0x00000000 +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_STATUS_MAC0__CMD_NUMBER___POR 0x000000 +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_STATUS_MAC0__LAST_USER_NUMBER___POR 0x00 +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_STATUS_MAC0__READ_WRITE_STATUS___POR 0x0 +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_STATUS_MAC0__CMD_NUMBER___M 0x7FFFFF80 +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_STATUS_MAC0__CMD_NUMBER___S 7 +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_STATUS_MAC0__LAST_USER_NUMBER___M 0x0000007E +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_STATUS_MAC0__LAST_USER_NUMBER___S 1 +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_STATUS_MAC0__READ_WRITE_STATUS___M 0x00000001 +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_STATUS_MAC0__READ_WRITE_STATUS___S 0 +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_STATUS_MAC0___M 0x7FFFFFFF +#define UMAC_TQM_R0_TQM_QUEUE_HEAD_STATUS_MAC0___S 0 + +#define UMAC_TQM_R0_SPARE (0x00A3C74C) +#define UMAC_TQM_R0_SPARE___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SPARE___POR 0x00000000 +#define UMAC_TQM_R0_SPARE__SPAREBITS___POR 0x00000000 +#define UMAC_TQM_R0_SPARE__SPAREBITS___M 0xFFFFFFFF +#define UMAC_TQM_R0_SPARE__SPAREBITS___S 0 +#define UMAC_TQM_R0_SPARE___M 0xFFFFFFFF +#define UMAC_TQM_R0_SPARE___S 0 + +#define UMAC_TQM_R0_SPEAR (0x00A3C750) +#define UMAC_TQM_R0_SPEAR___RWC QCSR_REG_RW +#define UMAC_TQM_R0_SPEAR___POR 0x00000000 +#define UMAC_TQM_R0_SPEAR__SPEAR___POR 0x00000000 +#define UMAC_TQM_R0_SPEAR__SPEAR___M 0xFFFFFFFF +#define UMAC_TQM_R0_SPEAR__SPEAR___S 0 +#define UMAC_TQM_R0_SPEAR___M 0xFFFFFFFF +#define UMAC_TQM_R0_SPEAR___S 0 + +#define UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH (0x00A3C754) +#define UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH___RWC QCSR_REG_RW +#define UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH___POR 0x00000001 +#define UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH__FOR_REM_MPDU___POR 0x0 +#define UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH__FOR_REM_MSDU___POR 0x0 +#define UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH__FOR_UPDATE_MSDU_FLOW___POR 0x0 +#define UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH__FOR_UPDATE_MPDU_QUEUE___POR 0x0 +#define UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH__FOR_GEN_MPDUS___POR 0x1 +#define UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH__FOR_REM_MPDU___M 0x00000010 +#define UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH__FOR_REM_MPDU___S 4 +#define UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH__FOR_REM_MSDU___M 0x00000008 +#define UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH__FOR_REM_MSDU___S 3 +#define UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH__FOR_UPDATE_MSDU_FLOW___M 0x00000004 +#define UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH__FOR_UPDATE_MSDU_FLOW___S 2 +#define UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH__FOR_UPDATE_MPDU_QUEUE___M 0x00000002 +#define UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH__FOR_UPDATE_MPDU_QUEUE___S 1 +#define UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH__FOR_GEN_MPDUS___M 0x00000001 +#define UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH__FOR_GEN_MPDUS___S 0 +#define UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH___M 0x0000001F +#define UMAC_TQM_R0_ENABLE_NON_POSTED_FLUSH___S 0 + +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_CONTROL (0x00A3E000) +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_CONTROL___RWC QCSR_REG_RW +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_CONTROL___POR 0x00000800 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_CONTROL__CACHE_CMD_HOLD_ACK___POR 0x1 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_CONTROL__CACHE_CMD_HOLD___POR 0x0 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_CONTROL__TAG_TABLE_UPDATE___POR 0x0 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_CONTROL__TAG_TABLE_SEL___POR 0x000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_CONTROL__CACHE_CMD_HOLD_ACK___M 0x00000800 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_CONTROL__CACHE_CMD_HOLD_ACK___S 11 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_CONTROL__CACHE_CMD_HOLD___M 0x00000400 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_CONTROL__CACHE_CMD_HOLD___S 10 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_CONTROL__TAG_TABLE_UPDATE___M 0x00000200 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_CONTROL__TAG_TABLE_UPDATE___S 9 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_CONTROL__TAG_TABLE_SEL___M 0x000001FF +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_CONTROL__TAG_TABLE_SEL___S 0 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_CONTROL___M 0x00000FFF +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_CONTROL___S 0 + +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT (0x00A3E004) +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT___RWC QCSR_REG_RW +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT___POR 0x00000000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT__CACHE_HIT_COUNT___POR 0x00000000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT__CACHE_HIT_COUNT___M 0xFFFFFFFF +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT__CACHE_HIT_COUNT___S 0 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT___M 0xFFFFFFFF +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_HIT_COUNT___S 0 + +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT (0x00A3E008) +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT___RWC QCSR_REG_RW +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT___POR 0x00000000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT__CACHE_MISS_COUNT___POR 0x000000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT__CACHE_MISS_COUNT___M 0x00FFFFFF +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT__CACHE_MISS_COUNT___S 0 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT___M 0x00FFFFFF +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_MISS_COUNT___S 0 + +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW (0x00A3E00C) +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW___RWC QCSR_REG_RW +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW___POR 0x00000000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW__OVERWRITE___POR 0x00000000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW__OVERWRITE___M 0xFFFFFFFF +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW__OVERWRITE___S 0 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW___M 0xFFFFFFFF +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW___S 0 + +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH (0x00A3E010) +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH___RWC QCSR_REG_RW +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH___POR 0x00000000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH__OVERWRITE___POR 0x00000000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH__OVERWRITE___M 0xFFFFFFFF +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH__OVERWRITE___S 0 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH___M 0xFFFFFFFF +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH___S 0 + +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_STM (0x00A3E014) +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_STM___RWC QCSR_REG_RO +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_STM___POR 0x00000000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_STM__STATE___POR 0x0000000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_STM__STATE___M 0x01FFFFFF +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_STM__STATE___S 0 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_STM___M 0x01FFFFFF +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_STM___S 0 + +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST (0x00A3E018) +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST___RWC QCSR_REG_RO +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST___POR 0x00000000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST__MRU_FLAG___POR 0x000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST__LRU_FLAG___POR 0x000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST__MRU_FLAG___M 0x0007FC00 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST__MRU_FLAG___S 10 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST__LRU_FLAG___M 0x000003FF +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST__LRU_FLAG___S 0 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST___M 0x0007FFFF +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST___S 0 + +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1 (0x00A3E01C) +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1___RWC QCSR_REG_RO +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1___POR 0x00000000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1__HEAD_FLAG___POR 0x000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1__TAIL_FLAG___POR 0x000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1__HEAD_FLAG___M 0x0007FC00 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1__HEAD_FLAG___S 10 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1__TAIL_FLAG___M 0x000003FF +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1__TAIL_FLAG___S 0 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1___M 0x0007FFFF +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST1___S 0 + +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2 (0x00A3E020) +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2___RWC QCSR_REG_RO +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2___POR 0x00000000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2__MRU_FLAG_SET2___POR 0x000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2__LRU_FLAG_SET2___POR 0x000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2__MRU_FLAG_SET2___M 0x0007FC00 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2__MRU_FLAG_SET2___S 10 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2__LRU_FLAG_SET2___M 0x000003FF +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2__LRU_FLAG_SET2___S 0 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2___M 0x0007FFFF +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST2___S 0 + +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3 (0x00A3E024) +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3___RWC QCSR_REG_RO +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3___POR 0x00000000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3__HEAD_FLAG_SET2___POR 0x000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3__TAIL_FLAG_SET2___POR 0x000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3__HEAD_FLAG_SET2___M 0x0007FC00 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3__HEAD_FLAG_SET2___S 10 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3__TAIL_FLAG_SET2___M 0x000003FF +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3__TAIL_FLAG_SET2___S 0 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3___M 0x0007FFFF +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_LINK_LIST3___S 0 + +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW (0x00A3E028) +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW___RWC QCSR_REG_RO +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW___POR 0x00000000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW__VALUE___POR 0x00000000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW__VALUE___M 0xFFFFFFFF +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW__VALUE___S 0 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW___M 0xFFFFFFFF +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW___S 0 + +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH (0x00A3E02C) +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH___RWC QCSR_REG_RO +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH___POR 0x00000000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH__VALUE___POR 0x00000000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH__VALUE___M 0xFFFFFFFF +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH__VALUE___S 0 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH___M 0xFFFFFFFF +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH___S 0 + +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER (0x00A3E030) +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER___RWC QCSR_REG_RO +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER___POR 0x00000000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER__SET2___POR 0x000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER__SET1___POR 0x000 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER__SET2___M 0x000FFC00 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER__SET2___S 10 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER__SET1___M 0x000003FF +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER__SET1___S 0 +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER___M 0x000FFFFF +#define UMAC_TQM_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER___S 0 + +#define UMAC_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK (0x00A3E034) +#define UMAC_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK___RWC QCSR_REG_RW +#define UMAC_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK___POR 0x00000000 +#define UMAC_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0 +#define UMAC_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001 +#define UMAC_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S 0 +#define UMAC_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK___M 0x00000001 +#define UMAC_TQM_R1_CACHE_CTL_END_OF_TEST_CHECK___S 0 + +#define UMAC_TQM_R1_PREFETCH_BUF (0x00A3E038) +#define UMAC_TQM_R1_PREFETCH_BUF___RWC QCSR_REG_RW +#define UMAC_TQM_R1_PREFETCH_BUF___POR 0x00000000 +#define UMAC_TQM_R1_PREFETCH_BUF__ADDR___POR 0x000 +#define UMAC_TQM_R1_PREFETCH_BUF__ADDR___M 0x00000FFC +#define UMAC_TQM_R1_PREFETCH_BUF__ADDR___S 2 +#define UMAC_TQM_R1_PREFETCH_BUF___M 0x00000FFC +#define UMAC_TQM_R1_PREFETCH_BUF___S 2 + +#define UMAC_TQM_R1_PREFETCH_BUF_DATA (0x00A3E03C) +#define UMAC_TQM_R1_PREFETCH_BUF_DATA___RWC QCSR_REG_RO +#define UMAC_TQM_R1_PREFETCH_BUF_DATA___POR 0x00000000 +#define UMAC_TQM_R1_PREFETCH_BUF_DATA__VALUE___POR 0x00000000 +#define UMAC_TQM_R1_PREFETCH_BUF_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_TQM_R1_PREFETCH_BUF_DATA__VALUE___S 0 +#define UMAC_TQM_R1_PREFETCH_BUF_DATA___M 0xFFFFFFFF +#define UMAC_TQM_R1_PREFETCH_BUF_DATA___S 0 + +#define UMAC_TQM_R1_CACHE_BUF (0x00A3E040) +#define UMAC_TQM_R1_CACHE_BUF___RWC QCSR_REG_RW +#define UMAC_TQM_R1_CACHE_BUF___POR 0x00000000 +#define UMAC_TQM_R1_CACHE_BUF__ADDR___POR 0x0000 +#define UMAC_TQM_R1_CACHE_BUF__ADDR___M 0x0000FFFC +#define UMAC_TQM_R1_CACHE_BUF__ADDR___S 2 +#define UMAC_TQM_R1_CACHE_BUF___M 0x0000FFFC +#define UMAC_TQM_R1_CACHE_BUF___S 2 + +#define UMAC_TQM_R1_CACHE_BUF_DATA (0x00A3E044) +#define UMAC_TQM_R1_CACHE_BUF_DATA___RWC QCSR_REG_RO +#define UMAC_TQM_R1_CACHE_BUF_DATA___POR 0x00000000 +#define UMAC_TQM_R1_CACHE_BUF_DATA__VALUE___POR 0x00000000 +#define UMAC_TQM_R1_CACHE_BUF_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_TQM_R1_CACHE_BUF_DATA__VALUE___S 0 +#define UMAC_TQM_R1_CACHE_BUF_DATA___M 0xFFFFFFFF +#define UMAC_TQM_R1_CACHE_BUF_DATA___S 0 + +#define UMAC_TQM_R1_MISC_DEBUG_CTRL (0x00A3E048) +#define UMAC_TQM_R1_MISC_DEBUG_CTRL___RWC QCSR_REG_RW +#define UMAC_TQM_R1_MISC_DEBUG_CTRL___POR 0x00000000 +#define UMAC_TQM_R1_MISC_DEBUG_CTRL__IDLE_REQ___POR 0x0 +#define UMAC_TQM_R1_MISC_DEBUG_CTRL__IDLE_REQ_DONE___POR 0x0 +#define UMAC_TQM_R1_MISC_DEBUG_CTRL__IDLE_REQ___M 0x00000002 +#define UMAC_TQM_R1_MISC_DEBUG_CTRL__IDLE_REQ___S 1 +#define UMAC_TQM_R1_MISC_DEBUG_CTRL__IDLE_REQ_DONE___M 0x00000001 +#define UMAC_TQM_R1_MISC_DEBUG_CTRL__IDLE_REQ_DONE___S 0 +#define UMAC_TQM_R1_MISC_DEBUG_CTRL___M 0x00000003 +#define UMAC_TQM_R1_MISC_DEBUG_CTRL___S 0 + +#define UMAC_TQM_R1_LOG (0x00A3E04C) +#define UMAC_TQM_R1_LOG___RWC QCSR_REG_RO +#define UMAC_TQM_R1_LOG___POR 0x0FFFFFFF +#define UMAC_TQM_R1_LOG__CURR_CMD_IDX___POR 0xF +#define UMAC_TQM_R1_LOG__CURR_CMD_NUM___POR 0xFFFFFF +#define UMAC_TQM_R1_LOG__CURR_CMD_IDX___M 0x0F000000 +#define UMAC_TQM_R1_LOG__CURR_CMD_IDX___S 24 +#define UMAC_TQM_R1_LOG__CURR_CMD_NUM___M 0x00FFFFFF +#define UMAC_TQM_R1_LOG__CURR_CMD_NUM___S 0 +#define UMAC_TQM_R1_LOG___M 0x0FFFFFFF +#define UMAC_TQM_R1_LOG___S 0 + +#define UMAC_TQM_R1_BANK_SM_STATES_IX0 (0x00A3E050) +#define UMAC_TQM_R1_BANK_SM_STATES_IX0___RWC QCSR_REG_RO +#define UMAC_TQM_R1_BANK_SM_STATES_IX0___POR 0x00000000 +#define UMAC_TQM_R1_BANK_SM_STATES_IX0__GET_QUEUE_STATS_SM___POR 0x0 +#define UMAC_TQM_R1_BANK_SM_STATES_IX0__GET_MPDU_HEAD_INFO_SM___POR 0x0 +#define UMAC_TQM_R1_BANK_SM_STATES_IX0__FLUSH_AND_UNBLOCK_CACHE_SM___POR 0x0 +#define UMAC_TQM_R1_BANK_SM_STATES_IX0__ADD_MPDU_LINK_SM___POR 0x0 +#define UMAC_TQM_R1_BANK_SM_STATES_IX0__CREATE_MPDU_SM___POR 0x00 +#define UMAC_TQM_R1_BANK_SM_STATES_IX0__GEN_MPDU_SM___POR 0x00 +#define UMAC_TQM_R1_BANK_SM_STATES_IX0__ADD_MSDU_SM___POR 0x00 +#define UMAC_TQM_R1_BANK_SM_STATES_IX0__GET_QUEUE_STATS_SM___M 0x1E000000 +#define UMAC_TQM_R1_BANK_SM_STATES_IX0__GET_QUEUE_STATS_SM___S 25 +#define UMAC_TQM_R1_BANK_SM_STATES_IX0__GET_MPDU_HEAD_INFO_SM___M 0x01E00000 +#define UMAC_TQM_R1_BANK_SM_STATES_IX0__GET_MPDU_HEAD_INFO_SM___S 21 +#define UMAC_TQM_R1_BANK_SM_STATES_IX0__FLUSH_AND_UNBLOCK_CACHE_SM___M 0x00180000 +#define UMAC_TQM_R1_BANK_SM_STATES_IX0__FLUSH_AND_UNBLOCK_CACHE_SM___S 19 +#define UMAC_TQM_R1_BANK_SM_STATES_IX0__ADD_MPDU_LINK_SM___M 0x00078000 +#define UMAC_TQM_R1_BANK_SM_STATES_IX0__ADD_MPDU_LINK_SM___S 15 +#define UMAC_TQM_R1_BANK_SM_STATES_IX0__CREATE_MPDU_SM___M 0x00007C00 +#define UMAC_TQM_R1_BANK_SM_STATES_IX0__CREATE_MPDU_SM___S 10 +#define UMAC_TQM_R1_BANK_SM_STATES_IX0__GEN_MPDU_SM___M 0x000003E0 +#define UMAC_TQM_R1_BANK_SM_STATES_IX0__GEN_MPDU_SM___S 5 +#define UMAC_TQM_R1_BANK_SM_STATES_IX0__ADD_MSDU_SM___M 0x0000001F +#define UMAC_TQM_R1_BANK_SM_STATES_IX0__ADD_MSDU_SM___S 0 +#define UMAC_TQM_R1_BANK_SM_STATES_IX0___M 0x1FFFFFFF +#define UMAC_TQM_R1_BANK_SM_STATES_IX0___S 0 + +#define UMAC_TQM_R1_BANK_SM_STATES_IX1 (0x00A3E054) +#define UMAC_TQM_R1_BANK_SM_STATES_IX1___RWC QCSR_REG_RO +#define UMAC_TQM_R1_BANK_SM_STATES_IX1___POR 0x00000000 +#define UMAC_TQM_R1_BANK_SM_STATES_IX1__ARB_STATUS_BLK1_SM___POR 0x0 +#define UMAC_TQM_R1_BANK_SM_STATES_IX1__ARB_STATUS_BLK0_SM___POR 0x0 +#define UMAC_TQM_R1_BANK_SM_STATES_IX1__UPDATE_TX_MPDU_COUNT_SM___POR 0x00 +#define UMAC_TQM_R1_BANK_SM_STATES_IX1__REM_MSDU_SM___POR 0x00 +#define UMAC_TQM_R1_BANK_SM_STATES_IX1__REM_MPDU_SM___POR 0x00 +#define UMAC_TQM_R1_BANK_SM_STATES_IX1__WRITE_CMD_SM___POR 0x0 +#define UMAC_TQM_R1_BANK_SM_STATES_IX1__LIST_MPDU_MAIN_SM___POR 0x00 +#define UMAC_TQM_R1_BANK_SM_STATES_IX1__LIST_TLV_SM___POR 0x0 +#define UMAC_TQM_R1_BANK_SM_STATES_IX1__ARB_STATUS_BLK1_SM___M 0xC0000000 +#define UMAC_TQM_R1_BANK_SM_STATES_IX1__ARB_STATUS_BLK1_SM___S 30 +#define UMAC_TQM_R1_BANK_SM_STATES_IX1__ARB_STATUS_BLK0_SM___M 0x30000000 +#define UMAC_TQM_R1_BANK_SM_STATES_IX1__ARB_STATUS_BLK0_SM___S 28 +#define UMAC_TQM_R1_BANK_SM_STATES_IX1__UPDATE_TX_MPDU_COUNT_SM___M 0x0F800000 +#define UMAC_TQM_R1_BANK_SM_STATES_IX1__UPDATE_TX_MPDU_COUNT_SM___S 23 +#define UMAC_TQM_R1_BANK_SM_STATES_IX1__REM_MSDU_SM___M 0x007C0000 +#define UMAC_TQM_R1_BANK_SM_STATES_IX1__REM_MSDU_SM___S 18 +#define UMAC_TQM_R1_BANK_SM_STATES_IX1__REM_MPDU_SM___M 0x0003F000 +#define UMAC_TQM_R1_BANK_SM_STATES_IX1__REM_MPDU_SM___S 12 +#define UMAC_TQM_R1_BANK_SM_STATES_IX1__WRITE_CMD_SM___M 0x00000E00 +#define UMAC_TQM_R1_BANK_SM_STATES_IX1__WRITE_CMD_SM___S 9 +#define UMAC_TQM_R1_BANK_SM_STATES_IX1__LIST_MPDU_MAIN_SM___M 0x000001F0 +#define UMAC_TQM_R1_BANK_SM_STATES_IX1__LIST_MPDU_MAIN_SM___S 4 +#define UMAC_TQM_R1_BANK_SM_STATES_IX1__LIST_TLV_SM___M 0x0000000F +#define UMAC_TQM_R1_BANK_SM_STATES_IX1__LIST_TLV_SM___S 0 +#define UMAC_TQM_R1_BANK_SM_STATES_IX1___M 0xFFFFFFFF +#define UMAC_TQM_R1_BANK_SM_STATES_IX1___S 0 + +#define UMAC_TQM_R1_BANK_SM_STATES_IX2 (0x00A3E058) +#define UMAC_TQM_R1_BANK_SM_STATES_IX2___RWC QCSR_REG_RO +#define UMAC_TQM_R1_BANK_SM_STATES_IX2___POR 0x00000000 +#define UMAC_TQM_R1_BANK_SM_STATES_IX2__ARB_ASYNC_SM___POR 0x0 +#define UMAC_TQM_R1_BANK_SM_STATES_IX2__ARB_MSDU_ENT_SM___POR 0x0 +#define UMAC_TQM_R1_BANK_SM_STATES_IX2__ARB_SW_CMD_SM___POR 0x0 +#define UMAC_TQM_R1_BANK_SM_STATES_IX2__ARB_HWSCH_CMD_SM___POR 0x0 +#define UMAC_TQM_R1_BANK_SM_STATES_IX2__PREFETCH_READ_SM___POR 0x0 +#define UMAC_TQM_R1_BANK_SM_STATES_IX2__PREFETCH_SM___POR 0x00000 +#define UMAC_TQM_R1_BANK_SM_STATES_IX2__ARB_ASYNC_SM___M 0x80000000 +#define UMAC_TQM_R1_BANK_SM_STATES_IX2__ARB_ASYNC_SM___S 31 +#define UMAC_TQM_R1_BANK_SM_STATES_IX2__ARB_MSDU_ENT_SM___M 0x70000000 +#define UMAC_TQM_R1_BANK_SM_STATES_IX2__ARB_MSDU_ENT_SM___S 28 +#define UMAC_TQM_R1_BANK_SM_STATES_IX2__ARB_SW_CMD_SM___M 0x0F000000 +#define UMAC_TQM_R1_BANK_SM_STATES_IX2__ARB_SW_CMD_SM___S 24 +#define UMAC_TQM_R1_BANK_SM_STATES_IX2__ARB_HWSCH_CMD_SM___M 0x00F00000 +#define UMAC_TQM_R1_BANK_SM_STATES_IX2__ARB_HWSCH_CMD_SM___S 20 +#define UMAC_TQM_R1_BANK_SM_STATES_IX2__PREFETCH_READ_SM___M 0x000C0000 +#define UMAC_TQM_R1_BANK_SM_STATES_IX2__PREFETCH_READ_SM___S 18 +#define UMAC_TQM_R1_BANK_SM_STATES_IX2__PREFETCH_SM___M 0x0003FFFF +#define UMAC_TQM_R1_BANK_SM_STATES_IX2__PREFETCH_SM___S 0 +#define UMAC_TQM_R1_BANK_SM_STATES_IX2___M 0xFFFFFFFF +#define UMAC_TQM_R1_BANK_SM_STATES_IX2___S 0 + +#define UMAC_TQM_R1_BANK_SM_STATES_IX3 (0x00A3E05C) +#define UMAC_TQM_R1_BANK_SM_STATES_IX3___RWC QCSR_REG_RO +#define UMAC_TQM_R1_BANK_SM_STATES_IX3___POR 0x00000000 +#define UMAC_TQM_R1_BANK_SM_STATES_IX3__UPDATE_QUEUE_DESC_SM___POR 0x00 +#define UMAC_TQM_R1_BANK_SM_STATES_IX3__AXI_TO_TLV_SM___POR 0x0 +#define UMAC_TQM_R1_BANK_SM_STATES_IX3__LIST_TLV_STATE___POR 0x0 +#define UMAC_TQM_R1_BANK_SM_STATES_IX3__DATA_ALIGN_SM___POR 0x0 +#define UMAC_TQM_R1_BANK_SM_STATES_IX3__UPDATE_QUEUE_DESC_SM___M 0x00000F80 +#define UMAC_TQM_R1_BANK_SM_STATES_IX3__UPDATE_QUEUE_DESC_SM___S 7 +#define UMAC_TQM_R1_BANK_SM_STATES_IX3__AXI_TO_TLV_SM___M 0x00000060 +#define UMAC_TQM_R1_BANK_SM_STATES_IX3__AXI_TO_TLV_SM___S 5 +#define UMAC_TQM_R1_BANK_SM_STATES_IX3__LIST_TLV_STATE___M 0x0000001C +#define UMAC_TQM_R1_BANK_SM_STATES_IX3__LIST_TLV_STATE___S 2 +#define UMAC_TQM_R1_BANK_SM_STATES_IX3__DATA_ALIGN_SM___M 0x00000003 +#define UMAC_TQM_R1_BANK_SM_STATES_IX3__DATA_ALIGN_SM___S 0 +#define UMAC_TQM_R1_BANK_SM_STATES_IX3___M 0x00000FFF +#define UMAC_TQM_R1_BANK_SM_STATES_IX3___S 0 + +#define UMAC_TQM_R1_CCMN_IDLE (0x00A3E060) +#define UMAC_TQM_R1_CCMN_IDLE___RWC QCSR_REG_RO +#define UMAC_TQM_R1_CCMN_IDLE___POR 0x00000000 +#define UMAC_TQM_R1_CCMN_IDLE__SOURCES___POR 0x00000000 +#define UMAC_TQM_R1_CCMN_IDLE__SOURCES___M 0xFFFFFFFF +#define UMAC_TQM_R1_CCMN_IDLE__SOURCES___S 0 +#define UMAC_TQM_R1_CCMN_IDLE___M 0xFFFFFFFF +#define UMAC_TQM_R1_CCMN_IDLE___S 0 + +#define UMAC_TQM_R1_CURRENT_COMMAND (0x00A3E064) +#define UMAC_TQM_R1_CURRENT_COMMAND___RWC QCSR_REG_RO +#define UMAC_TQM_R1_CURRENT_COMMAND___POR 0x00000000 +#define UMAC_TQM_R1_CURRENT_COMMAND__POINTER___POR 0x0 +#define UMAC_TQM_R1_CURRENT_COMMAND__INDEX_6___POR 0x0 +#define UMAC_TQM_R1_CURRENT_COMMAND__INDEX_5___POR 0x0 +#define UMAC_TQM_R1_CURRENT_COMMAND__INDEX_4___POR 0x0 +#define UMAC_TQM_R1_CURRENT_COMMAND__INDEX_3___POR 0x0 +#define UMAC_TQM_R1_CURRENT_COMMAND__INDEX_2___POR 0x0 +#define UMAC_TQM_R1_CURRENT_COMMAND__INDEX_1___POR 0x0 +#define UMAC_TQM_R1_CURRENT_COMMAND__INDEX_0___POR 0x0 +#define UMAC_TQM_R1_CURRENT_COMMAND__POINTER___M 0xF0000000 +#define UMAC_TQM_R1_CURRENT_COMMAND__POINTER___S 28 +#define UMAC_TQM_R1_CURRENT_COMMAND__INDEX_6___M 0x0F000000 +#define UMAC_TQM_R1_CURRENT_COMMAND__INDEX_6___S 24 +#define UMAC_TQM_R1_CURRENT_COMMAND__INDEX_5___M 0x00F00000 +#define UMAC_TQM_R1_CURRENT_COMMAND__INDEX_5___S 20 +#define UMAC_TQM_R1_CURRENT_COMMAND__INDEX_4___M 0x000F0000 +#define UMAC_TQM_R1_CURRENT_COMMAND__INDEX_4___S 16 +#define UMAC_TQM_R1_CURRENT_COMMAND__INDEX_3___M 0x0000F000 +#define UMAC_TQM_R1_CURRENT_COMMAND__INDEX_3___S 12 +#define UMAC_TQM_R1_CURRENT_COMMAND__INDEX_2___M 0x00000F00 +#define UMAC_TQM_R1_CURRENT_COMMAND__INDEX_2___S 8 +#define UMAC_TQM_R1_CURRENT_COMMAND__INDEX_1___M 0x000000F0 +#define UMAC_TQM_R1_CURRENT_COMMAND__INDEX_1___S 4 +#define UMAC_TQM_R1_CURRENT_COMMAND__INDEX_0___M 0x0000000F +#define UMAC_TQM_R1_CURRENT_COMMAND__INDEX_0___S 0 +#define UMAC_TQM_R1_CURRENT_COMMAND___M 0xFFFFFFFF +#define UMAC_TQM_R1_CURRENT_COMMAND___S 0 + +#define UMAC_TQM_R1_LOG_ADD_MSDU (0x00A3E068) +#define UMAC_TQM_R1_LOG_ADD_MSDU___RWC QCSR_REG_RO +#define UMAC_TQM_R1_LOG_ADD_MSDU___POR 0x00FFFFFF +#define UMAC_TQM_R1_LOG_ADD_MSDU__CURR_CMD_NUM___POR 0xFFFFFF +#define UMAC_TQM_R1_LOG_ADD_MSDU__CURR_CMD_NUM___M 0x00FFFFFF +#define UMAC_TQM_R1_LOG_ADD_MSDU__CURR_CMD_NUM___S 0 +#define UMAC_TQM_R1_LOG_ADD_MSDU___M 0x00FFFFFF +#define UMAC_TQM_R1_LOG_ADD_MSDU___S 0 + +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX0 (0x00A3E06C) +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX0___RWC QCSR_REG_RO +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX0___POR 0x00000000 +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX0__INDEX_2___POR 0x000 +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX0__INDEX_1___POR 0x000 +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX0__INDEX_0___POR 0x000 +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX0__INDEX_2___M 0x3FF00000 +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX0__INDEX_2___S 20 +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX0__INDEX_1___M 0x000FFC00 +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX0__INDEX_1___S 10 +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX0__INDEX_0___M 0x000003FF +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX0__INDEX_0___S 0 +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX0___M 0x3FFFFFFF +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX0___S 0 + +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX1 (0x00A3E070) +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX1___RWC QCSR_REG_RO +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX1___POR 0x00000000 +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX1__INDEX_5___POR 0x000 +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX1__INDEX_4___POR 0x000 +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX1__INDEX_3___POR 0x000 +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX1__INDEX_5___M 0x3FF00000 +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX1__INDEX_5___S 20 +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX1__INDEX_4___M 0x000FFC00 +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX1__INDEX_4___S 10 +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX1__INDEX_3___M 0x000003FF +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX1__INDEX_3___S 0 +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX1___M 0x3FFFFFFF +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX1___S 0 + +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX2 (0x00A3E074) +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX2___RWC QCSR_REG_RO +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX2___POR 0x00000000 +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX2__POINTER___POR 0x0 +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX2__INDEX_7___POR 0x000 +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX2__INDEX_6___POR 0x000 +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX2__POINTER___M 0x00700000 +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX2__POINTER___S 20 +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX2__INDEX_7___M 0x000FFC00 +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX2__INDEX_7___S 10 +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX2__INDEX_6___M 0x000003FF +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX2__INDEX_6___S 0 +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX2___M 0x007FFFFF +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX2___S 0 + +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX3 (0x00A3E078) +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX3___RWC QCSR_REG_RO +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX3___POR 0x00000000 +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX3__WATCHDOG_SNAPSHOT___POR 0x000000 +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX3__TIMESTAMP___POR 0x000 +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX3__WATCHDOG_SNAPSHOT___M 0xFFFFFC00 +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX3__WATCHDOG_SNAPSHOT___S 10 +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX3__TIMESTAMP___M 0x000003FF +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX3__TIMESTAMP___S 0 +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX3___M 0xFFFFFFFF +#define UMAC_TQM_R1_LOG_TIMESTAMP_IX3___S 0 + +#define UMAC_TQM_R1_WATCHDOG_STATUS_IX0 (0x00A3E07C) +#define UMAC_TQM_R1_WATCHDOG_STATUS_IX0___RWC QCSR_REG_RO +#define UMAC_TQM_R1_WATCHDOG_STATUS_IX0___POR 0x00000000 +#define UMAC_TQM_R1_WATCHDOG_STATUS_IX0__SW_SM_WATCHDOG___POR 0x0000 +#define UMAC_TQM_R1_WATCHDOG_STATUS_IX0__HW_SM_WATCHDOG___POR 0x0000 +#define UMAC_TQM_R1_WATCHDOG_STATUS_IX0__SW_SM_WATCHDOG___M 0xFFFF0000 +#define UMAC_TQM_R1_WATCHDOG_STATUS_IX0__SW_SM_WATCHDOG___S 16 +#define UMAC_TQM_R1_WATCHDOG_STATUS_IX0__HW_SM_WATCHDOG___M 0x0000FFFF +#define UMAC_TQM_R1_WATCHDOG_STATUS_IX0__HW_SM_WATCHDOG___S 0 +#define UMAC_TQM_R1_WATCHDOG_STATUS_IX0___M 0xFFFFFFFF +#define UMAC_TQM_R1_WATCHDOG_STATUS_IX0___S 0 + +#define UMAC_TQM_R1_WATCHDOG_STATUS_IX1 (0x00A3E080) +#define UMAC_TQM_R1_WATCHDOG_STATUS_IX1___RWC QCSR_REG_RO +#define UMAC_TQM_R1_WATCHDOG_STATUS_IX1___POR 0x00000000 +#define UMAC_TQM_R1_WATCHDOG_STATUS_IX1__ENTRANCE_SM_WATCHDOG___POR 0x0000 +#define UMAC_TQM_R1_WATCHDOG_STATUS_IX1__ENTRANCE_SM_WATCHDOG___M 0x0000FFFF +#define UMAC_TQM_R1_WATCHDOG_STATUS_IX1__ENTRANCE_SM_WATCHDOG___S 0 +#define UMAC_TQM_R1_WATCHDOG_STATUS_IX1___M 0x0000FFFF +#define UMAC_TQM_R1_WATCHDOG_STATUS_IX1___S 0 + +#define UMAC_TQM_R1_LOG_ADD_MSDU_FETCH (0x00A3E084) +#define UMAC_TQM_R1_LOG_ADD_MSDU_FETCH___RWC QCSR_REG_RO +#define UMAC_TQM_R1_LOG_ADD_MSDU_FETCH___POR 0x00000000 +#define UMAC_TQM_R1_LOG_ADD_MSDU_FETCH__ADDRESS___POR 0x00000000 +#define UMAC_TQM_R1_LOG_ADD_MSDU_FETCH__ADDRESS___M 0xFFFFFFFF +#define UMAC_TQM_R1_LOG_ADD_MSDU_FETCH__ADDRESS___S 0 +#define UMAC_TQM_R1_LOG_ADD_MSDU_FETCH___M 0xFFFFFFFF +#define UMAC_TQM_R1_LOG_ADD_MSDU_FETCH___S 0 + +#define UMAC_TQM_R1_LOG_GEN_MPDU_FETCH (0x00A3E088) +#define UMAC_TQM_R1_LOG_GEN_MPDU_FETCH___RWC QCSR_REG_RO +#define UMAC_TQM_R1_LOG_GEN_MPDU_FETCH___POR 0x00000000 +#define UMAC_TQM_R1_LOG_GEN_MPDU_FETCH__ADDRESS___POR 0x00000000 +#define UMAC_TQM_R1_LOG_GEN_MPDU_FETCH__ADDRESS___M 0xFFFFFFFF +#define UMAC_TQM_R1_LOG_GEN_MPDU_FETCH__ADDRESS___S 0 +#define UMAC_TQM_R1_LOG_GEN_MPDU_FETCH___M 0xFFFFFFFF +#define UMAC_TQM_R1_LOG_GEN_MPDU_FETCH___S 0 + +#define UMAC_TQM_R2_TCL2TQM_RING_HP (0x00A3F000) +#define UMAC_TQM_R2_TCL2TQM_RING_HP___RWC QCSR_REG_RW +#define UMAC_TQM_R2_TCL2TQM_RING_HP___POR 0x00000000 +#define UMAC_TQM_R2_TCL2TQM_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_TQM_R2_TCL2TQM_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_TQM_R2_TCL2TQM_RING_HP__HEAD_PTR___S 0 +#define UMAC_TQM_R2_TCL2TQM_RING_HP___M 0x0000FFFF +#define UMAC_TQM_R2_TCL2TQM_RING_HP___S 0 + +#define UMAC_TQM_R2_TCL2TQM_RING_TP (0x00A3F004) +#define UMAC_TQM_R2_TCL2TQM_RING_TP___RWC QCSR_REG_RW +#define UMAC_TQM_R2_TCL2TQM_RING_TP___POR 0x00000000 +#define UMAC_TQM_R2_TCL2TQM_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_TQM_R2_TCL2TQM_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_TQM_R2_TCL2TQM_RING_TP__TAIL_PTR___S 0 +#define UMAC_TQM_R2_TCL2TQM_RING_TP___M 0x0000FFFF +#define UMAC_TQM_R2_TCL2TQM_RING_TP___S 0 + +#define UMAC_TQM_R2_SW2TQM_RING_HP (0x00A3F008) +#define UMAC_TQM_R2_SW2TQM_RING_HP___RWC QCSR_REG_RW +#define UMAC_TQM_R2_SW2TQM_RING_HP___POR 0x00000000 +#define UMAC_TQM_R2_SW2TQM_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_TQM_R2_SW2TQM_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_TQM_R2_SW2TQM_RING_HP__HEAD_PTR___S 0 +#define UMAC_TQM_R2_SW2TQM_RING_HP___M 0x0000FFFF +#define UMAC_TQM_R2_SW2TQM_RING_HP___S 0 + +#define UMAC_TQM_R2_SW2TQM_RING_TP (0x00A3F00C) +#define UMAC_TQM_R2_SW2TQM_RING_TP___RWC QCSR_REG_RW +#define UMAC_TQM_R2_SW2TQM_RING_TP___POR 0x00000000 +#define UMAC_TQM_R2_SW2TQM_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_TQM_R2_SW2TQM_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_TQM_R2_SW2TQM_RING_TP__TAIL_PTR___S 0 +#define UMAC_TQM_R2_SW2TQM_RING_TP___M 0x0000FFFF +#define UMAC_TQM_R2_SW2TQM_RING_TP___S 0 + +#define UMAC_TQM_R2_FW2TQM_RING_HP (0x00A3F010) +#define UMAC_TQM_R2_FW2TQM_RING_HP___RWC QCSR_REG_RW +#define UMAC_TQM_R2_FW2TQM_RING_HP___POR 0x00000000 +#define UMAC_TQM_R2_FW2TQM_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_TQM_R2_FW2TQM_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_TQM_R2_FW2TQM_RING_HP__HEAD_PTR___S 0 +#define UMAC_TQM_R2_FW2TQM_RING_HP___M 0x0000FFFF +#define UMAC_TQM_R2_FW2TQM_RING_HP___S 0 + +#define UMAC_TQM_R2_FW2TQM_RING_TP (0x00A3F014) +#define UMAC_TQM_R2_FW2TQM_RING_TP___RWC QCSR_REG_RW +#define UMAC_TQM_R2_FW2TQM_RING_TP___POR 0x00000000 +#define UMAC_TQM_R2_FW2TQM_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_TQM_R2_FW2TQM_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_TQM_R2_FW2TQM_RING_TP__TAIL_PTR___S 0 +#define UMAC_TQM_R2_FW2TQM_RING_TP___M 0x0000FFFF +#define UMAC_TQM_R2_FW2TQM_RING_TP___S 0 + +#define UMAC_TQM_R2_SW_CMD_RING_HP (0x00A3F018) +#define UMAC_TQM_R2_SW_CMD_RING_HP___RWC QCSR_REG_RW +#define UMAC_TQM_R2_SW_CMD_RING_HP___POR 0x00000000 +#define UMAC_TQM_R2_SW_CMD_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_TQM_R2_SW_CMD_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_TQM_R2_SW_CMD_RING_HP__HEAD_PTR___S 0 +#define UMAC_TQM_R2_SW_CMD_RING_HP___M 0x0000FFFF +#define UMAC_TQM_R2_SW_CMD_RING_HP___S 0 + +#define UMAC_TQM_R2_SW_CMD_RING_TP (0x00A3F01C) +#define UMAC_TQM_R2_SW_CMD_RING_TP___RWC QCSR_REG_RW +#define UMAC_TQM_R2_SW_CMD_RING_TP___POR 0x00000000 +#define UMAC_TQM_R2_SW_CMD_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_TQM_R2_SW_CMD_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_TQM_R2_SW_CMD_RING_TP__TAIL_PTR___S 0 +#define UMAC_TQM_R2_SW_CMD_RING_TP___M 0x0000FFFF +#define UMAC_TQM_R2_SW_CMD_RING_TP___S 0 + +#define UMAC_TQM_R2_SW_CMD1_RING_HP (0x00A3F020) +#define UMAC_TQM_R2_SW_CMD1_RING_HP___RWC QCSR_REG_RW +#define UMAC_TQM_R2_SW_CMD1_RING_HP___POR 0x00000000 +#define UMAC_TQM_R2_SW_CMD1_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_TQM_R2_SW_CMD1_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_TQM_R2_SW_CMD1_RING_HP__HEAD_PTR___S 0 +#define UMAC_TQM_R2_SW_CMD1_RING_HP___M 0x0000FFFF +#define UMAC_TQM_R2_SW_CMD1_RING_HP___S 0 + +#define UMAC_TQM_R2_SW_CMD1_RING_TP (0x00A3F024) +#define UMAC_TQM_R2_SW_CMD1_RING_TP___RWC QCSR_REG_RW +#define UMAC_TQM_R2_SW_CMD1_RING_TP___POR 0x00000000 +#define UMAC_TQM_R2_SW_CMD1_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_TQM_R2_SW_CMD1_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_TQM_R2_SW_CMD1_RING_TP__TAIL_PTR___S 0 +#define UMAC_TQM_R2_SW_CMD1_RING_TP___M 0x0000FFFF +#define UMAC_TQM_R2_SW_CMD1_RING_TP___S 0 + +#define UMAC_TQM_R2_SCH2TQM0_RING_HP (0x00A3F028) +#define UMAC_TQM_R2_SCH2TQM0_RING_HP___RWC QCSR_REG_RW +#define UMAC_TQM_R2_SCH2TQM0_RING_HP___POR 0x00000000 +#define UMAC_TQM_R2_SCH2TQM0_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_TQM_R2_SCH2TQM0_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_TQM_R2_SCH2TQM0_RING_HP__HEAD_PTR___S 0 +#define UMAC_TQM_R2_SCH2TQM0_RING_HP___M 0x0000FFFF +#define UMAC_TQM_R2_SCH2TQM0_RING_HP___S 0 + +#define UMAC_TQM_R2_SCH2TQM0_RING_TP (0x00A3F02C) +#define UMAC_TQM_R2_SCH2TQM0_RING_TP___RWC QCSR_REG_RW +#define UMAC_TQM_R2_SCH2TQM0_RING_TP___POR 0x00000000 +#define UMAC_TQM_R2_SCH2TQM0_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_TQM_R2_SCH2TQM0_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_TQM_R2_SCH2TQM0_RING_TP__TAIL_PTR___S 0 +#define UMAC_TQM_R2_SCH2TQM0_RING_TP___M 0x0000FFFF +#define UMAC_TQM_R2_SCH2TQM0_RING_TP___S 0 + +#define UMAC_TQM_R2_WBM2TQM_LINK_RING_HP (0x00A3F040) +#define UMAC_TQM_R2_WBM2TQM_LINK_RING_HP___RWC QCSR_REG_RW +#define UMAC_TQM_R2_WBM2TQM_LINK_RING_HP___POR 0x00000000 +#define UMAC_TQM_R2_WBM2TQM_LINK_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_TQM_R2_WBM2TQM_LINK_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_TQM_R2_WBM2TQM_LINK_RING_HP__HEAD_PTR___S 0 +#define UMAC_TQM_R2_WBM2TQM_LINK_RING_HP___M 0x0000FFFF +#define UMAC_TQM_R2_WBM2TQM_LINK_RING_HP___S 0 + +#define UMAC_TQM_R2_WBM2TQM_LINK_RING_TP (0x00A3F044) +#define UMAC_TQM_R2_WBM2TQM_LINK_RING_TP___RWC QCSR_REG_RW +#define UMAC_TQM_R2_WBM2TQM_LINK_RING_TP___POR 0x00000000 +#define UMAC_TQM_R2_WBM2TQM_LINK_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_TQM_R2_WBM2TQM_LINK_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_TQM_R2_WBM2TQM_LINK_RING_TP__TAIL_PTR___S 0 +#define UMAC_TQM_R2_WBM2TQM_LINK_RING_TP___M 0x0000FFFF +#define UMAC_TQM_R2_WBM2TQM_LINK_RING_TP___S 0 + +#define UMAC_TQM_R2_TQM_RELEASE_RING_HP (0x00A3F048) +#define UMAC_TQM_R2_TQM_RELEASE_RING_HP___RWC QCSR_REG_RW +#define UMAC_TQM_R2_TQM_RELEASE_RING_HP___POR 0x00000000 +#define UMAC_TQM_R2_TQM_RELEASE_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_TQM_R2_TQM_RELEASE_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_TQM_R2_TQM_RELEASE_RING_HP__HEAD_PTR___S 0 +#define UMAC_TQM_R2_TQM_RELEASE_RING_HP___M 0x0000FFFF +#define UMAC_TQM_R2_TQM_RELEASE_RING_HP___S 0 + +#define UMAC_TQM_R2_TQM_RELEASE_RING_TP (0x00A3F04C) +#define UMAC_TQM_R2_TQM_RELEASE_RING_TP___RWC QCSR_REG_RW +#define UMAC_TQM_R2_TQM_RELEASE_RING_TP___POR 0x00000000 +#define UMAC_TQM_R2_TQM_RELEASE_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_TQM_R2_TQM_RELEASE_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_TQM_R2_TQM_RELEASE_RING_TP__TAIL_PTR___S 0 +#define UMAC_TQM_R2_TQM_RELEASE_RING_TP___M 0x0000FFFF +#define UMAC_TQM_R2_TQM_RELEASE_RING_TP___S 0 + +#define UMAC_TQM_R2_TQM_STATUS_RING_HP (0x00A3F050) +#define UMAC_TQM_R2_TQM_STATUS_RING_HP___RWC QCSR_REG_RW +#define UMAC_TQM_R2_TQM_STATUS_RING_HP___POR 0x00000000 +#define UMAC_TQM_R2_TQM_STATUS_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_TQM_R2_TQM_STATUS_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_TQM_R2_TQM_STATUS_RING_HP__HEAD_PTR___S 0 +#define UMAC_TQM_R2_TQM_STATUS_RING_HP___M 0x0000FFFF +#define UMAC_TQM_R2_TQM_STATUS_RING_HP___S 0 + +#define UMAC_TQM_R2_TQM_STATUS_RING_TP (0x00A3F054) +#define UMAC_TQM_R2_TQM_STATUS_RING_TP___RWC QCSR_REG_RW +#define UMAC_TQM_R2_TQM_STATUS_RING_TP___POR 0x00000000 +#define UMAC_TQM_R2_TQM_STATUS_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_TQM_R2_TQM_STATUS_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_TQM_R2_TQM_STATUS_RING_TP__TAIL_PTR___S 0 +#define UMAC_TQM_R2_TQM_STATUS_RING_TP___M 0x0000FFFF +#define UMAC_TQM_R2_TQM_STATUS_RING_TP___S 0 + +#define UMAC_TQM_R2_TQM_STATUS1_RING_HP (0x00A3F058) +#define UMAC_TQM_R2_TQM_STATUS1_RING_HP___RWC QCSR_REG_RW +#define UMAC_TQM_R2_TQM_STATUS1_RING_HP___POR 0x00000000 +#define UMAC_TQM_R2_TQM_STATUS1_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_TQM_R2_TQM_STATUS1_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_TQM_R2_TQM_STATUS1_RING_HP__HEAD_PTR___S 0 +#define UMAC_TQM_R2_TQM_STATUS1_RING_HP___M 0x0000FFFF +#define UMAC_TQM_R2_TQM_STATUS1_RING_HP___S 0 + +#define UMAC_TQM_R2_TQM_STATUS1_RING_TP (0x00A3F05C) +#define UMAC_TQM_R2_TQM_STATUS1_RING_TP___RWC QCSR_REG_RW +#define UMAC_TQM_R2_TQM_STATUS1_RING_TP___POR 0x00000000 +#define UMAC_TQM_R2_TQM_STATUS1_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_TQM_R2_TQM_STATUS1_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_TQM_R2_TQM_STATUS1_RING_TP__TAIL_PTR___S 0 +#define UMAC_TQM_R2_TQM_STATUS1_RING_TP___M 0x0000FFFF +#define UMAC_TQM_R2_TQM_STATUS1_RING_TP___S 0 + +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN (0x00A40000) +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN___POR 0x002FFFE2 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__UMAC_DBG___POR 0x1 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TRC_APB___POR 0x1 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TRC___POR 0x1 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__WBM_APB___POR 0x1 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__WBM___POR 0x1 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TQM_APB___POR 0x1 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TQM___POR 0x1 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TCL_APB___POR 0x1 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TCL___POR 0x1 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__REO_APB___POR 0x1 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__REO___POR 0x1 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__NOC_DBG___POR 0x1 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CE_APB___POR 0x1 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CE___POR 0x1 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CXC___POR 0x1 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CMEM___POR 0x1 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__NOC___POR 0x1 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__UMAC_DBG___M 0x00200000 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__UMAC_DBG___S 21 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TRC_APB___M 0x00080000 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TRC_APB___S 19 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TRC___M 0x00040000 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TRC___S 18 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__WBM_APB___M 0x00020000 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__WBM_APB___S 17 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__WBM___M 0x00010000 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__WBM___S 16 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TQM_APB___M 0x00008000 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TQM_APB___S 15 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TQM___M 0x00004000 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TQM___S 14 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TCL_APB___M 0x00002000 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TCL_APB___S 13 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TCL___M 0x00001000 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__TCL___S 12 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__REO_APB___M 0x00000800 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__REO_APB___S 11 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__REO___M 0x00000400 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__REO___S 10 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__NOC_DBG___M 0x00000200 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__NOC_DBG___S 9 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CE_APB___M 0x00000100 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CE_APB___S 8 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CE___M 0x00000080 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CE___S 7 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CXC___M 0x00000040 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CXC___S 6 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CMEM___M 0x00000020 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__CMEM___S 5 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__NOC___M 0x00000002 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN__NOC___S 1 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN___M 0x002FFFE2 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKEN___S 1 + +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE (0x00A40004) +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE___POR 0x00000002 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__UMAC_DBG___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TRC_APB___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TRC___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__WBM_APB___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__WBM___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TQM_APB___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TQM___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TCL_APB___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TCL___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__REO_APB___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__REO___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CE_APB___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CE___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CXC___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CMEM___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__NOC___POR 0x1 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__UMAC_DBG___M 0x00200000 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__UMAC_DBG___S 21 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TRC_APB___M 0x00080000 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TRC_APB___S 19 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TRC___M 0x00040000 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TRC___S 18 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__WBM_APB___M 0x00020000 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__WBM_APB___S 17 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__WBM___M 0x00010000 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__WBM___S 16 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TQM_APB___M 0x00008000 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TQM_APB___S 15 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TQM___M 0x00004000 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TQM___S 14 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TCL_APB___M 0x00002000 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TCL_APB___S 13 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TCL___M 0x00001000 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__TCL___S 12 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__REO_APB___M 0x00000800 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__REO_APB___S 11 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__REO___M 0x00000400 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__REO___S 10 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CE_APB___M 0x00000100 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CE_APB___S 8 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CE___M 0x00000080 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CE___S 7 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CXC___M 0x00000040 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CXC___S 6 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CMEM___M 0x00000020 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__CMEM___S 5 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__NOC___M 0x00000002 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE__NOC___S 1 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE___M 0x002FFDE2 +#define UMAC_UMCMN_R0_UMRCM_ROOT_CLKGATE_DISABLE___S 1 + +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET (0x00A40008) +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET___POR 0x00000000 +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET__UMAC_DBG___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET__TRC___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET__WBM___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET__TQM___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET__TCL___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET__REO___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET__CE___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET__CXC___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET__CMEM___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET__NOC___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET__UMAC_DBG___M 0x00000400 +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET__UMAC_DBG___S 10 +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET__TRC___M 0x00000100 +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET__TRC___S 8 +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET__WBM___M 0x00000080 +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET__WBM___S 7 +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET__TQM___M 0x00000040 +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET__TQM___S 6 +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET__TCL___M 0x00000020 +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET__TCL___S 5 +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET__REO___M 0x00000010 +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET__REO___S 4 +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET__CE___M 0x00000008 +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET__CE___S 3 +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET__CXC___M 0x00000004 +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET__CXC___S 2 +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET__CMEM___M 0x00000002 +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET__CMEM___S 1 +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET__NOC___M 0x00000001 +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET__NOC___S 0 +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET___M 0x000005FF +#define UMAC_UMCMN_R0_UMRCM_SOFTRESET___S 0 + +#define UMAC_UMCMN_R0_UMRCM_CONFIGRESET (0x00A4000C) +#define UMAC_UMCMN_R0_UMRCM_CONFIGRESET___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_UMRCM_CONFIGRESET___POR 0x00000000 +#define UMAC_UMCMN_R0_UMRCM_CONFIGRESET__TRC___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_CONFIGRESET__WBM___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_CONFIGRESET__TQM___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_CONFIGRESET__TCL___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_CONFIGRESET__REO___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_CONFIGRESET__CE___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_CONFIGRESET__TRC___M 0x00000020 +#define UMAC_UMCMN_R0_UMRCM_CONFIGRESET__TRC___S 5 +#define UMAC_UMCMN_R0_UMRCM_CONFIGRESET__WBM___M 0x00000010 +#define UMAC_UMCMN_R0_UMRCM_CONFIGRESET__WBM___S 4 +#define UMAC_UMCMN_R0_UMRCM_CONFIGRESET__TQM___M 0x00000008 +#define UMAC_UMCMN_R0_UMRCM_CONFIGRESET__TQM___S 3 +#define UMAC_UMCMN_R0_UMRCM_CONFIGRESET__TCL___M 0x00000004 +#define UMAC_UMCMN_R0_UMRCM_CONFIGRESET__TCL___S 2 +#define UMAC_UMCMN_R0_UMRCM_CONFIGRESET__REO___M 0x00000002 +#define UMAC_UMCMN_R0_UMRCM_CONFIGRESET__REO___S 1 +#define UMAC_UMCMN_R0_UMRCM_CONFIGRESET__CE___M 0x00000001 +#define UMAC_UMCMN_R0_UMRCM_CONFIGRESET__CE___S 0 +#define UMAC_UMCMN_R0_UMRCM_CONFIGRESET___M 0x0000003F +#define UMAC_UMCMN_R0_UMRCM_CONFIGRESET___S 0 + +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE (0x00A40010) +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE___POR 0x00000000 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__UMAC_DBG___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TRC_APB___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TRC___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__WBM_APB___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__WBM___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TQM_APB___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TQM___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TCL_APB___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TCL___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__REO_APB___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__REO___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CE_APB___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CE___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CXC___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CMEM___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__NOC___POR 0x0 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__UMAC_DBG___M 0x00400000 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__UMAC_DBG___S 22 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TRC_APB___M 0x00080000 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TRC_APB___S 19 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TRC___M 0x00040000 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TRC___S 18 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__WBM_APB___M 0x00020000 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__WBM_APB___S 17 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__WBM___M 0x00010000 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__WBM___S 16 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TQM_APB___M 0x00008000 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TQM_APB___S 15 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TQM___M 0x00004000 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TQM___S 14 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TCL_APB___M 0x00002000 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TCL_APB___S 13 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TCL___M 0x00001000 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__TCL___S 12 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__REO_APB___M 0x00000800 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__REO_APB___S 11 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__REO___M 0x00000400 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__REO___S 10 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CE_APB___M 0x00000100 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CE_APB___S 8 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CE___M 0x00000080 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CE___S 7 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CXC___M 0x00000040 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CXC___S 6 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CMEM___M 0x00000020 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__CMEM___S 5 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__NOC___M 0x00000002 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE__NOC___S 1 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE___M 0x004FFDE2 +#define UMAC_UMCMN_R0_UMRCM_CLKGATE_DISABLE___S 1 + +#define UMAC_UMCMN_R0_UMAC_RTL_VERSION (0x00A40014) +#define UMAC_UMCMN_R0_UMAC_RTL_VERSION___RWC QCSR_REG_RO +#define UMAC_UMCMN_R0_UMAC_RTL_VERSION___POR 0x00000000 +#define UMAC_UMCMN_R0_UMAC_RTL_VERSION__VAL___POR 0x00000000 +#define UMAC_UMCMN_R0_UMAC_RTL_VERSION__VAL___M 0xFFFFFFFF +#define UMAC_UMCMN_R0_UMAC_RTL_VERSION__VAL___S 0 +#define UMAC_UMCMN_R0_UMAC_RTL_VERSION___M 0xFFFFFFFF +#define UMAC_UMCMN_R0_UMAC_RTL_VERSION___S 0 + +#define UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET (0x00A40018) +#define UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET___POR 0x00000000 +#define UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET__PHY2___POR 0x0 +#define UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET__PHY1___POR 0x0 +#define UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET__WMAC3___POR 0x0 +#define UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET__WMAC2___POR 0x0 +#define UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET__WMAC1___POR 0x0 +#define UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET__PHY2___M 0x00000010 +#define UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET__PHY2___S 4 +#define UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET__PHY1___M 0x00000008 +#define UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET__PHY1___S 3 +#define UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET__WMAC3___M 0x00000004 +#define UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET__WMAC3___S 2 +#define UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET__WMAC2___M 0x00000002 +#define UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET__WMAC2___S 1 +#define UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET__WMAC1___M 0x00000001 +#define UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET__WMAC1___S 0 +#define UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET___M 0x0000001F +#define UMAC_UMCMN_R0_ASYNC_FIFO_SOFTRESET___S 0 + +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE (0x00A4001C) +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE___POR 0x00000000 +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND___POR 0x0 +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND_APB___POR 0x0 +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__TBD___POR 0x0000000 +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__APB_VAL___POR 0x0 +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__PCIE_LOW_POWER_REQ___POR 0x0 +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__UMAC_IDLE_GENERATE___POR 0x0 +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__UMCMN_TOP___POR 0x0 +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND___M 0x80000000 +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND___S 31 +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND_APB___M 0x40000000 +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND_APB___S 30 +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__TBD___M 0x3FFFFFF0 +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__TBD___S 4 +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__APB_VAL___M 0x00000008 +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__APB_VAL___S 3 +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__PCIE_LOW_POWER_REQ___M 0x00000004 +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__PCIE_LOW_POWER_REQ___S 2 +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__UMAC_IDLE_GENERATE___M 0x00000002 +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__UMAC_IDLE_GENERATE___S 1 +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__UMCMN_TOP___M 0x00000001 +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE__UMCMN_TOP___S 0 +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE___M 0xFFFFFFFF +#define UMAC_UMCMN_R0_CLK_GATE_DISABLE___S 0 + +#define UMAC_UMCMN_R0_NOC_PRGMBL_AXCACHE (0x00A40020) +#define UMAC_UMCMN_R0_NOC_PRGMBL_AXCACHE___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_NOC_PRGMBL_AXCACHE___POR 0x00000001 +#define UMAC_UMCMN_R0_NOC_PRGMBL_AXCACHE__VALUE___POR 0x1 +#define UMAC_UMCMN_R0_NOC_PRGMBL_AXCACHE__VALUE___M 0x0000000F +#define UMAC_UMCMN_R0_NOC_PRGMBL_AXCACHE__VALUE___S 0 +#define UMAC_UMCMN_R0_NOC_PRGMBL_AXCACHE___M 0x0000000F +#define UMAC_UMCMN_R0_NOC_PRGMBL_AXCACHE___S 0 + +#define UMAC_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN (0x00A40024) +#define UMAC_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN___POR 0x00000001 +#define UMAC_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN__VALUE___POR 0x1 +#define UMAC_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN__VALUE___M 0x00000001 +#define UMAC_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN__VALUE___S 0 +#define UMAC_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN___M 0x00000001 +#define UMAC_UMCMN_R0_NOC_PRGMBL_AXCACHE_EN___S 0 + +#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_0 (0x00A40028) +#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_0___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_0___POR 0x00000000 +#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_0__SIZE___POR 0x000 +#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_0__BASE___POR 0x0000 +#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_0__SIZE___M 0x0FFF0000 +#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_0__SIZE___S 16 +#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_0__BASE___M 0x0000FFFF +#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_0__BASE___S 0 +#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_0___M 0x0FFFFFFF +#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_0___S 0 + +#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_1 (0x00A4002C) +#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_1___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_1___POR 0x00000000 +#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_1__SIZE___POR 0x000 +#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_1__BASE___POR 0x0000 +#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_1__SIZE___M 0x0FFF0000 +#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_1__SIZE___S 16 +#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_1__BASE___M 0x0000FFFF +#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_1__BASE___S 0 +#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_1___M 0x0FFFFFFF +#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_1___S 0 + +#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_2 (0x00A40030) +#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_2___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_2___POR 0x00000000 +#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_2__SIZE___POR 0x000 +#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_2__BASE___POR 0x0000 +#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_2__SIZE___M 0x0FFF0000 +#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_2__SIZE___S 16 +#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_2__BASE___M 0x0000FFFF +#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_2__BASE___S 0 +#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_2___M 0x0FFFFFFF +#define UMAC_UMCMN_R0_CMEM_SEC_CTRL_2___S 0 + +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL (0x00A40034) +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL___POR 0x00000000 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK13_EN___POR 0x0 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK12_EN___POR 0x0 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK11_EN___POR 0x0 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK10_EN___POR 0x0 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK9_EN___POR 0x0 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK8_EN___POR 0x0 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK7_EN___POR 0x0 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK6_EN___POR 0x0 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK5_EN___POR 0x0 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK4_EN___POR 0x0 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK3_EN___POR 0x0 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK2_EN___POR 0x0 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK1_EN___POR 0x0 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK0_EN___POR 0x0 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK13_EN___M 0x20000000 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK13_EN___S 29 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK12_EN___M 0x10000000 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK12_EN___S 28 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK11_EN___M 0x08000000 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK11_EN___S 27 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK10_EN___M 0x04000000 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK10_EN___S 26 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK9_EN___M 0x02000000 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK9_EN___S 25 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK8_EN___M 0x01000000 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK8_EN___S 24 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK7_EN___M 0x00800000 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK7_EN___S 23 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK6_EN___M 0x00400000 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK6_EN___S 22 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK5_EN___M 0x00200000 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK5_EN___S 21 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK4_EN___M 0x00100000 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK4_EN___S 20 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK3_EN___M 0x00080000 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK3_EN___S 19 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK2_EN___M 0x00040000 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK2_EN___S 18 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK1_EN___M 0x00020000 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK1_EN___S 17 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK0_EN___M 0x00010000 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL__BANK0_EN___S 16 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL___M 0x3FFF0000 +#define UMAC_UMCMN_R0_CMEM_UPEC_ACCESS_CTRL___S 16 + +#define UMAC_UMCMN_R0_ISR_P (0x00A40038) +#define UMAC_UMCMN_R0_ISR_P___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_ISR_P___POR 0x00000000 +#define UMAC_UMCMN_R0_ISR_P__GXI___POR 0x0 +#define UMAC_UMCMN_R0_ISR_P__TQM2___POR 0x0 +#define UMAC_UMCMN_R0_ISR_P__TQM1___POR 0x0 +#define UMAC_UMCMN_R0_ISR_P__TQM0___POR 0x0 +#define UMAC_UMCMN_R0_ISR_P__TCL1___POR 0x0 +#define UMAC_UMCMN_R0_ISR_P__TCL0___POR 0x0 +#define UMAC_UMCMN_R0_ISR_P__REO4___POR 0x0 +#define UMAC_UMCMN_R0_ISR_P__REO3___POR 0x0 +#define UMAC_UMCMN_R0_ISR_P__REO2___POR 0x0 +#define UMAC_UMCMN_R0_ISR_P__REO1___POR 0x0 +#define UMAC_UMCMN_R0_ISR_P__REO0___POR 0x0 +#define UMAC_UMCMN_R0_ISR_P__WBM2___POR 0x0 +#define UMAC_UMCMN_R0_ISR_P__WBM1___POR 0x0 +#define UMAC_UMCMN_R0_ISR_P__WBM0___POR 0x0 +#define UMAC_UMCMN_R0_ISR_P__MEM___POR 0x0 +#define UMAC_UMCMN_R0_ISR_P__CXC___POR 0x0 +#define UMAC_UMCMN_R0_ISR_P__APB___POR 0x0 +#define UMAC_UMCMN_R0_ISR_P__GXI___M 0x00010000 +#define UMAC_UMCMN_R0_ISR_P__GXI___S 16 +#define UMAC_UMCMN_R0_ISR_P__TQM2___M 0x00008000 +#define UMAC_UMCMN_R0_ISR_P__TQM2___S 15 +#define UMAC_UMCMN_R0_ISR_P__TQM1___M 0x00004000 +#define UMAC_UMCMN_R0_ISR_P__TQM1___S 14 +#define UMAC_UMCMN_R0_ISR_P__TQM0___M 0x00002000 +#define UMAC_UMCMN_R0_ISR_P__TQM0___S 13 +#define UMAC_UMCMN_R0_ISR_P__TCL1___M 0x00001000 +#define UMAC_UMCMN_R0_ISR_P__TCL1___S 12 +#define UMAC_UMCMN_R0_ISR_P__TCL0___M 0x00000800 +#define UMAC_UMCMN_R0_ISR_P__TCL0___S 11 +#define UMAC_UMCMN_R0_ISR_P__REO4___M 0x00000400 +#define UMAC_UMCMN_R0_ISR_P__REO4___S 10 +#define UMAC_UMCMN_R0_ISR_P__REO3___M 0x00000200 +#define UMAC_UMCMN_R0_ISR_P__REO3___S 9 +#define UMAC_UMCMN_R0_ISR_P__REO2___M 0x00000100 +#define UMAC_UMCMN_R0_ISR_P__REO2___S 8 +#define UMAC_UMCMN_R0_ISR_P__REO1___M 0x00000080 +#define UMAC_UMCMN_R0_ISR_P__REO1___S 7 +#define UMAC_UMCMN_R0_ISR_P__REO0___M 0x00000040 +#define UMAC_UMCMN_R0_ISR_P__REO0___S 6 +#define UMAC_UMCMN_R0_ISR_P__WBM2___M 0x00000020 +#define UMAC_UMCMN_R0_ISR_P__WBM2___S 5 +#define UMAC_UMCMN_R0_ISR_P__WBM1___M 0x00000010 +#define UMAC_UMCMN_R0_ISR_P__WBM1___S 4 +#define UMAC_UMCMN_R0_ISR_P__WBM0___M 0x00000008 +#define UMAC_UMCMN_R0_ISR_P__WBM0___S 3 +#define UMAC_UMCMN_R0_ISR_P__MEM___M 0x00000004 +#define UMAC_UMCMN_R0_ISR_P__MEM___S 2 +#define UMAC_UMCMN_R0_ISR_P__CXC___M 0x00000002 +#define UMAC_UMCMN_R0_ISR_P__CXC___S 1 +#define UMAC_UMCMN_R0_ISR_P__APB___M 0x00000001 +#define UMAC_UMCMN_R0_ISR_P__APB___S 0 +#define UMAC_UMCMN_R0_ISR_P___M 0x0001FFFF +#define UMAC_UMCMN_R0_ISR_P___S 0 + +#define UMAC_UMCMN_R0_ISR_S0 (0x00A4003C) +#define UMAC_UMCMN_R0_ISR_S0___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_ISR_S0___POR 0x00000000 +#define UMAC_UMCMN_R0_ISR_S0__CE_APB_RD_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S0__CE_APB_WR_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S0__CE_APB_WR_TO_RD_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S0__UMCMN_APB_RD_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S0__UMCMN_APB_WR_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S0__UMCMN_APB_WR_TO_RD_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S0__TQM_APB_RD_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S0__TQM_APB_WR_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S0__TQM_APB_WR_TO_RD_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S0__CMN_PRSR_APB_RD_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S0__CMN_PRSR_APB_WR_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S0__CMN_PRSR_APB_WR_TO_RD_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S0__CCE_APB_RD_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S0__CCE_APB_WR_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S0__CCE_APB_WR_TO_RD_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S0__WBM_APB_RD_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S0__WBM_APB_WR_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S0__WBM_APB_WR_TO_RD_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S0__TCL_APB_RD_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S0__TCL_APB_WR_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S0__TCL_APB_WR_TO_RD_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S0__REO_APB_RD_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S0__REO_APB_WR_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S0__REO_APB_WR_TO_RD_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S0__CE_APB_RD_INVALID___M 0x00800000 +#define UMAC_UMCMN_R0_ISR_S0__CE_APB_RD_INVALID___S 23 +#define UMAC_UMCMN_R0_ISR_S0__CE_APB_WR_INVALID___M 0x00400000 +#define UMAC_UMCMN_R0_ISR_S0__CE_APB_WR_INVALID___S 22 +#define UMAC_UMCMN_R0_ISR_S0__CE_APB_WR_TO_RD_INVALID___M 0x00200000 +#define UMAC_UMCMN_R0_ISR_S0__CE_APB_WR_TO_RD_INVALID___S 21 +#define UMAC_UMCMN_R0_ISR_S0__UMCMN_APB_RD_INVALID___M 0x00100000 +#define UMAC_UMCMN_R0_ISR_S0__UMCMN_APB_RD_INVALID___S 20 +#define UMAC_UMCMN_R0_ISR_S0__UMCMN_APB_WR_INVALID___M 0x00080000 +#define UMAC_UMCMN_R0_ISR_S0__UMCMN_APB_WR_INVALID___S 19 +#define UMAC_UMCMN_R0_ISR_S0__UMCMN_APB_WR_TO_RD_INVALID___M 0x00040000 +#define UMAC_UMCMN_R0_ISR_S0__UMCMN_APB_WR_TO_RD_INVALID___S 18 +#define UMAC_UMCMN_R0_ISR_S0__TQM_APB_RD_INVALID___M 0x00020000 +#define UMAC_UMCMN_R0_ISR_S0__TQM_APB_RD_INVALID___S 17 +#define UMAC_UMCMN_R0_ISR_S0__TQM_APB_WR_INVALID___M 0x00010000 +#define UMAC_UMCMN_R0_ISR_S0__TQM_APB_WR_INVALID___S 16 +#define UMAC_UMCMN_R0_ISR_S0__TQM_APB_WR_TO_RD_INVALID___M 0x00008000 +#define UMAC_UMCMN_R0_ISR_S0__TQM_APB_WR_TO_RD_INVALID___S 15 +#define UMAC_UMCMN_R0_ISR_S0__CMN_PRSR_APB_RD_INVALID___M 0x00004000 +#define UMAC_UMCMN_R0_ISR_S0__CMN_PRSR_APB_RD_INVALID___S 14 +#define UMAC_UMCMN_R0_ISR_S0__CMN_PRSR_APB_WR_INVALID___M 0x00002000 +#define UMAC_UMCMN_R0_ISR_S0__CMN_PRSR_APB_WR_INVALID___S 13 +#define UMAC_UMCMN_R0_ISR_S0__CMN_PRSR_APB_WR_TO_RD_INVALID___M 0x00001000 +#define UMAC_UMCMN_R0_ISR_S0__CMN_PRSR_APB_WR_TO_RD_INVALID___S 12 +#define UMAC_UMCMN_R0_ISR_S0__CCE_APB_RD_INVALID___M 0x00000800 +#define UMAC_UMCMN_R0_ISR_S0__CCE_APB_RD_INVALID___S 11 +#define UMAC_UMCMN_R0_ISR_S0__CCE_APB_WR_INVALID___M 0x00000400 +#define UMAC_UMCMN_R0_ISR_S0__CCE_APB_WR_INVALID___S 10 +#define UMAC_UMCMN_R0_ISR_S0__CCE_APB_WR_TO_RD_INVALID___M 0x00000200 +#define UMAC_UMCMN_R0_ISR_S0__CCE_APB_WR_TO_RD_INVALID___S 9 +#define UMAC_UMCMN_R0_ISR_S0__WBM_APB_RD_INVALID___M 0x00000100 +#define UMAC_UMCMN_R0_ISR_S0__WBM_APB_RD_INVALID___S 8 +#define UMAC_UMCMN_R0_ISR_S0__WBM_APB_WR_INVALID___M 0x00000080 +#define UMAC_UMCMN_R0_ISR_S0__WBM_APB_WR_INVALID___S 7 +#define UMAC_UMCMN_R0_ISR_S0__WBM_APB_WR_TO_RD_INVALID___M 0x00000040 +#define UMAC_UMCMN_R0_ISR_S0__WBM_APB_WR_TO_RD_INVALID___S 6 +#define UMAC_UMCMN_R0_ISR_S0__TCL_APB_RD_INVALID___M 0x00000020 +#define UMAC_UMCMN_R0_ISR_S0__TCL_APB_RD_INVALID___S 5 +#define UMAC_UMCMN_R0_ISR_S0__TCL_APB_WR_INVALID___M 0x00000010 +#define UMAC_UMCMN_R0_ISR_S0__TCL_APB_WR_INVALID___S 4 +#define UMAC_UMCMN_R0_ISR_S0__TCL_APB_WR_TO_RD_INVALID___M 0x00000008 +#define UMAC_UMCMN_R0_ISR_S0__TCL_APB_WR_TO_RD_INVALID___S 3 +#define UMAC_UMCMN_R0_ISR_S0__REO_APB_RD_INVALID___M 0x00000004 +#define UMAC_UMCMN_R0_ISR_S0__REO_APB_RD_INVALID___S 2 +#define UMAC_UMCMN_R0_ISR_S0__REO_APB_WR_INVALID___M 0x00000002 +#define UMAC_UMCMN_R0_ISR_S0__REO_APB_WR_INVALID___S 1 +#define UMAC_UMCMN_R0_ISR_S0__REO_APB_WR_TO_RD_INVALID___M 0x00000001 +#define UMAC_UMCMN_R0_ISR_S0__REO_APB_WR_TO_RD_INVALID___S 0 +#define UMAC_UMCMN_R0_ISR_S0___M 0x00FFFFFF +#define UMAC_UMCMN_R0_ISR_S0___S 0 + +#define UMAC_UMCMN_R0_ISR_S1 (0x00A40040) +#define UMAC_UMCMN_R0_ISR_S1___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_ISR_S1___POR 0x00000000 +#define UMAC_UMCMN_R0_ISR_S1__CE_WDG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S1__CE_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S1__LCMH_WCI2___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S1__LCMH_STROBE___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S1__MCIM___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S1__SMH___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S1__PMH___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S1__LMH___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S1__BMH___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S1__CE_WDG___M 0x00020000 +#define UMAC_UMCMN_R0_ISR_S1__CE_WDG___S 17 +#define UMAC_UMCMN_R0_ISR_S1__CE_ERR___M 0x00010000 +#define UMAC_UMCMN_R0_ISR_S1__CE_ERR___S 16 +#define UMAC_UMCMN_R0_ISR_S1__LCMH_WCI2___M 0x00000040 +#define UMAC_UMCMN_R0_ISR_S1__LCMH_WCI2___S 6 +#define UMAC_UMCMN_R0_ISR_S1__LCMH_STROBE___M 0x00000020 +#define UMAC_UMCMN_R0_ISR_S1__LCMH_STROBE___S 5 +#define UMAC_UMCMN_R0_ISR_S1__MCIM___M 0x00000010 +#define UMAC_UMCMN_R0_ISR_S1__MCIM___S 4 +#define UMAC_UMCMN_R0_ISR_S1__SMH___M 0x00000008 +#define UMAC_UMCMN_R0_ISR_S1__SMH___S 3 +#define UMAC_UMCMN_R0_ISR_S1__PMH___M 0x00000004 +#define UMAC_UMCMN_R0_ISR_S1__PMH___S 2 +#define UMAC_UMCMN_R0_ISR_S1__LMH___M 0x00000002 +#define UMAC_UMCMN_R0_ISR_S1__LMH___S 1 +#define UMAC_UMCMN_R0_ISR_S1__BMH___M 0x00000001 +#define UMAC_UMCMN_R0_ISR_S1__BMH___S 0 +#define UMAC_UMCMN_R0_ISR_S1___M 0x0003007F +#define UMAC_UMCMN_R0_ISR_S1___S 0 + +#define UMAC_UMCMN_R0_ISR_S2 (0x00A40044) +#define UMAC_UMCMN_R0_ISR_S2___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_ISR_S2___POR 0x00000000 +#define UMAC_UMCMN_R0_ISR_S2__MEM_REMOTE_ACC_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S2__MEM_ACC_RANGE_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S2__MEM_NON_SEC_ACC_ERR2___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S2__MEM_NON_SEC_ACC_ERR1___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S2__MEM_REMOTE_ACC_ERR___M 0x00000008 +#define UMAC_UMCMN_R0_ISR_S2__MEM_REMOTE_ACC_ERR___S 3 +#define UMAC_UMCMN_R0_ISR_S2__MEM_ACC_RANGE_ERR___M 0x00000004 +#define UMAC_UMCMN_R0_ISR_S2__MEM_ACC_RANGE_ERR___S 2 +#define UMAC_UMCMN_R0_ISR_S2__MEM_NON_SEC_ACC_ERR2___M 0x00000002 +#define UMAC_UMCMN_R0_ISR_S2__MEM_NON_SEC_ACC_ERR2___S 1 +#define UMAC_UMCMN_R0_ISR_S2__MEM_NON_SEC_ACC_ERR1___M 0x00000001 +#define UMAC_UMCMN_R0_ISR_S2__MEM_NON_SEC_ACC_ERR1___S 0 +#define UMAC_UMCMN_R0_ISR_S2___M 0x0000000F +#define UMAC_UMCMN_R0_ISR_S2___S 0 + +#define UMAC_UMCMN_R0_ISR_S3 (0x00A40048) +#define UMAC_UMCMN_R0_ISR_S3___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_ISR_S3___POR 0x00000000 +#define UMAC_UMCMN_R0_ISR_S3__WBM_RESERVED___POR 0x00 +#define UMAC_UMCMN_R0_ISR_S3__WBM_MSDU_PARSER_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S3__WBM_LINK_IDLE_LIST_SCAT_SRNG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S3__WBM_LINK_IDLE_LIST_SCAT_SRNG_WDG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S3__WBM_BUF_IDLE_LIST_SCAT_SRNG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S3__WBM_BUF_IDLE_LIST_SCAT_SRNG_WDG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S3__WBM_MSDU_DELINK_PARSE_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S3__WBM_MSDU_DELINK_WDG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S3__WBM_LNK_IDLE_LIST_DIST_C_WDG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S3__WBM_LNK_IDLE_LIST_DIST_P_WDG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S3__WBM_BUF_IDLE_LIST_DIST_C_WDG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S3__WBM_BUF_IDLE_LIST_DIST_P_WDG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S3__WBM_FW_BUF_PROD_WDG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S3__WBM_SW3_BUF_PROD_WDG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S3__WBM_SW2_BUF_PROD_WDG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S3__WBM_SW1_BUF_PROD_WDG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S3__WBM_SW0_BUF_PROD_WDG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S3__WBM_BUF_IDLE_LIST_PROD_WDG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S3__WBM_LNK_IDLE_LIST_PROD_WDG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S3__WBM_REL_REQ_PARSER_C_WDG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S3__WBM_REL_REQ_PARSER_P_WDG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S3__WBM_RESERVED___M 0xFF000000 +#define UMAC_UMCMN_R0_ISR_S3__WBM_RESERVED___S 24 +#define UMAC_UMCMN_R0_ISR_S3__WBM_MSDU_PARSER_ERR___M 0x00380000 +#define UMAC_UMCMN_R0_ISR_S3__WBM_MSDU_PARSER_ERR___S 19 +#define UMAC_UMCMN_R0_ISR_S3__WBM_LINK_IDLE_LIST_SCAT_SRNG_ERR___M 0x00040000 +#define UMAC_UMCMN_R0_ISR_S3__WBM_LINK_IDLE_LIST_SCAT_SRNG_ERR___S 18 +#define UMAC_UMCMN_R0_ISR_S3__WBM_LINK_IDLE_LIST_SCAT_SRNG_WDG___M 0x00020000 +#define UMAC_UMCMN_R0_ISR_S3__WBM_LINK_IDLE_LIST_SCAT_SRNG_WDG___S 17 +#define UMAC_UMCMN_R0_ISR_S3__WBM_BUF_IDLE_LIST_SCAT_SRNG_ERR___M 0x00010000 +#define UMAC_UMCMN_R0_ISR_S3__WBM_BUF_IDLE_LIST_SCAT_SRNG_ERR___S 16 +#define UMAC_UMCMN_R0_ISR_S3__WBM_BUF_IDLE_LIST_SCAT_SRNG_WDG___M 0x00008000 +#define UMAC_UMCMN_R0_ISR_S3__WBM_BUF_IDLE_LIST_SCAT_SRNG_WDG___S 15 +#define UMAC_UMCMN_R0_ISR_S3__WBM_MSDU_DELINK_PARSE_ERR___M 0x00004000 +#define UMAC_UMCMN_R0_ISR_S3__WBM_MSDU_DELINK_PARSE_ERR___S 14 +#define UMAC_UMCMN_R0_ISR_S3__WBM_MSDU_DELINK_WDG___M 0x00002000 +#define UMAC_UMCMN_R0_ISR_S3__WBM_MSDU_DELINK_WDG___S 13 +#define UMAC_UMCMN_R0_ISR_S3__WBM_LNK_IDLE_LIST_DIST_C_WDG___M 0x00001000 +#define UMAC_UMCMN_R0_ISR_S3__WBM_LNK_IDLE_LIST_DIST_C_WDG___S 12 +#define UMAC_UMCMN_R0_ISR_S3__WBM_LNK_IDLE_LIST_DIST_P_WDG___M 0x00000800 +#define UMAC_UMCMN_R0_ISR_S3__WBM_LNK_IDLE_LIST_DIST_P_WDG___S 11 +#define UMAC_UMCMN_R0_ISR_S3__WBM_BUF_IDLE_LIST_DIST_C_WDG___M 0x00000400 +#define UMAC_UMCMN_R0_ISR_S3__WBM_BUF_IDLE_LIST_DIST_C_WDG___S 10 +#define UMAC_UMCMN_R0_ISR_S3__WBM_BUF_IDLE_LIST_DIST_P_WDG___M 0x00000200 +#define UMAC_UMCMN_R0_ISR_S3__WBM_BUF_IDLE_LIST_DIST_P_WDG___S 9 +#define UMAC_UMCMN_R0_ISR_S3__WBM_FW_BUF_PROD_WDG___M 0x00000100 +#define UMAC_UMCMN_R0_ISR_S3__WBM_FW_BUF_PROD_WDG___S 8 +#define UMAC_UMCMN_R0_ISR_S3__WBM_SW3_BUF_PROD_WDG___M 0x00000080 +#define UMAC_UMCMN_R0_ISR_S3__WBM_SW3_BUF_PROD_WDG___S 7 +#define UMAC_UMCMN_R0_ISR_S3__WBM_SW2_BUF_PROD_WDG___M 0x00000040 +#define UMAC_UMCMN_R0_ISR_S3__WBM_SW2_BUF_PROD_WDG___S 6 +#define UMAC_UMCMN_R0_ISR_S3__WBM_SW1_BUF_PROD_WDG___M 0x00000020 +#define UMAC_UMCMN_R0_ISR_S3__WBM_SW1_BUF_PROD_WDG___S 5 +#define UMAC_UMCMN_R0_ISR_S3__WBM_SW0_BUF_PROD_WDG___M 0x00000010 +#define UMAC_UMCMN_R0_ISR_S3__WBM_SW0_BUF_PROD_WDG___S 4 +#define UMAC_UMCMN_R0_ISR_S3__WBM_BUF_IDLE_LIST_PROD_WDG___M 0x00000008 +#define UMAC_UMCMN_R0_ISR_S3__WBM_BUF_IDLE_LIST_PROD_WDG___S 3 +#define UMAC_UMCMN_R0_ISR_S3__WBM_LNK_IDLE_LIST_PROD_WDG___M 0x00000004 +#define UMAC_UMCMN_R0_ISR_S3__WBM_LNK_IDLE_LIST_PROD_WDG___S 2 +#define UMAC_UMCMN_R0_ISR_S3__WBM_REL_REQ_PARSER_C_WDG___M 0x00000002 +#define UMAC_UMCMN_R0_ISR_S3__WBM_REL_REQ_PARSER_C_WDG___S 1 +#define UMAC_UMCMN_R0_ISR_S3__WBM_REL_REQ_PARSER_P_WDG___M 0x00000001 +#define UMAC_UMCMN_R0_ISR_S3__WBM_REL_REQ_PARSER_P_WDG___S 0 +#define UMAC_UMCMN_R0_ISR_S3___M 0xFF3FFFFF +#define UMAC_UMCMN_R0_ISR_S3___S 0 + +#define UMAC_UMCMN_R0_ISR_S4 (0x00A4004C) +#define UMAC_UMCMN_R0_ISR_S4___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_ISR_S4___POR 0x00000000 +#define UMAC_UMCMN_R0_ISR_S4__WBM2SW4_RELEASE_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S4__WBM2SW3_RELEASE_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S4__WBM2SW2_RELEASE_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S4__WBM2SW1_RELEASE_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S4__WBM2SW0_RELEASE_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S4__WBM2FW_RELEASE_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S4__WBM_IDLE_LINK_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S4__WBM_IDLE_BUF_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA2_LINK_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA1_LINK_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA0_LINK_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S4__WBM2FW_LINK_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S4__WBM2SW_LINK_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S4__WBM2REO_LINK_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S4__WBM2TQM_LINK_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA2_BUF_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA1_BUF_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA0_BUF_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S4__WBM2FW_BUF_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S4__WBM2SW_BUF_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S4__WBM2PPE_BUF_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S4__RXDMA2_RELEASE_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S4__RXDMA1_RELEASE_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S4__RXDMA0_RELEASE_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S4__FW_RELEASE_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S4__SW_RELEASE_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S4__REO_RELEASE_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S4__TQM_RELEASE_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S4__PPE_RELEASE_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S4__WBM2SW4_RELEASE_RING_WDG_ERR___M 0x10000000 +#define UMAC_UMCMN_R0_ISR_S4__WBM2SW4_RELEASE_RING_WDG_ERR___S 28 +#define UMAC_UMCMN_R0_ISR_S4__WBM2SW3_RELEASE_RING_WDG_ERR___M 0x08000000 +#define UMAC_UMCMN_R0_ISR_S4__WBM2SW3_RELEASE_RING_WDG_ERR___S 27 +#define UMAC_UMCMN_R0_ISR_S4__WBM2SW2_RELEASE_RING_WDG_ERR___M 0x04000000 +#define UMAC_UMCMN_R0_ISR_S4__WBM2SW2_RELEASE_RING_WDG_ERR___S 26 +#define UMAC_UMCMN_R0_ISR_S4__WBM2SW1_RELEASE_RING_WDG_ERR___M 0x02000000 +#define UMAC_UMCMN_R0_ISR_S4__WBM2SW1_RELEASE_RING_WDG_ERR___S 25 +#define UMAC_UMCMN_R0_ISR_S4__WBM2SW0_RELEASE_RING_WDG_ERR___M 0x01000000 +#define UMAC_UMCMN_R0_ISR_S4__WBM2SW0_RELEASE_RING_WDG_ERR___S 24 +#define UMAC_UMCMN_R0_ISR_S4__WBM2FW_RELEASE_RING_WDG_ERR___M 0x00800000 +#define UMAC_UMCMN_R0_ISR_S4__WBM2FW_RELEASE_RING_WDG_ERR___S 23 +#define UMAC_UMCMN_R0_ISR_S4__WBM_IDLE_LINK_RING_WDG_ERR___M 0x00400000 +#define UMAC_UMCMN_R0_ISR_S4__WBM_IDLE_LINK_RING_WDG_ERR___S 22 +#define UMAC_UMCMN_R0_ISR_S4__WBM_IDLE_BUF_RING_WDG_ERR___M 0x00200000 +#define UMAC_UMCMN_R0_ISR_S4__WBM_IDLE_BUF_RING_WDG_ERR___S 21 +#define UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA2_LINK_RING_WDG_ERR___M 0x00100000 +#define UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA2_LINK_RING_WDG_ERR___S 20 +#define UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA1_LINK_RING_WDG_ERR___M 0x00080000 +#define UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA1_LINK_RING_WDG_ERR___S 19 +#define UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA0_LINK_RING_WDG_ERR___M 0x00040000 +#define UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA0_LINK_RING_WDG_ERR___S 18 +#define UMAC_UMCMN_R0_ISR_S4__WBM2FW_LINK_RING_WDG_ERR___M 0x00020000 +#define UMAC_UMCMN_R0_ISR_S4__WBM2FW_LINK_RING_WDG_ERR___S 17 +#define UMAC_UMCMN_R0_ISR_S4__WBM2SW_LINK_RING_WDG_ERR___M 0x00010000 +#define UMAC_UMCMN_R0_ISR_S4__WBM2SW_LINK_RING_WDG_ERR___S 16 +#define UMAC_UMCMN_R0_ISR_S4__WBM2REO_LINK_RING_WDG_ERR___M 0x00008000 +#define UMAC_UMCMN_R0_ISR_S4__WBM2REO_LINK_RING_WDG_ERR___S 15 +#define UMAC_UMCMN_R0_ISR_S4__WBM2TQM_LINK_RING_WDG_ERR___M 0x00004000 +#define UMAC_UMCMN_R0_ISR_S4__WBM2TQM_LINK_RING_WDG_ERR___S 14 +#define UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA2_BUF_RING_WDG_ERR___M 0x00002000 +#define UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA2_BUF_RING_WDG_ERR___S 13 +#define UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA1_BUF_RING_WDG_ERR___M 0x00001000 +#define UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA1_BUF_RING_WDG_ERR___S 12 +#define UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA0_BUF_RING_WDG_ERR___M 0x00000800 +#define UMAC_UMCMN_R0_ISR_S4__WBM2RXDMA0_BUF_RING_WDG_ERR___S 11 +#define UMAC_UMCMN_R0_ISR_S4__WBM2FW_BUF_RING_WDG_ERR___M 0x00000400 +#define UMAC_UMCMN_R0_ISR_S4__WBM2FW_BUF_RING_WDG_ERR___S 10 +#define UMAC_UMCMN_R0_ISR_S4__WBM2SW_BUF_RING_WDG_ERR___M 0x00000200 +#define UMAC_UMCMN_R0_ISR_S4__WBM2SW_BUF_RING_WDG_ERR___S 9 +#define UMAC_UMCMN_R0_ISR_S4__WBM2PPE_BUF_RING_WDG_ERR___M 0x00000100 +#define UMAC_UMCMN_R0_ISR_S4__WBM2PPE_BUF_RING_WDG_ERR___S 8 +#define UMAC_UMCMN_R0_ISR_S4__RXDMA2_RELEASE_RING_WDG_ERR___M 0x00000080 +#define UMAC_UMCMN_R0_ISR_S4__RXDMA2_RELEASE_RING_WDG_ERR___S 7 +#define UMAC_UMCMN_R0_ISR_S4__RXDMA1_RELEASE_RING_WDG_ERR___M 0x00000040 +#define UMAC_UMCMN_R0_ISR_S4__RXDMA1_RELEASE_RING_WDG_ERR___S 6 +#define UMAC_UMCMN_R0_ISR_S4__RXDMA0_RELEASE_RING_WDG_ERR___M 0x00000020 +#define UMAC_UMCMN_R0_ISR_S4__RXDMA0_RELEASE_RING_WDG_ERR___S 5 +#define UMAC_UMCMN_R0_ISR_S4__FW_RELEASE_RING_WDG_ERR___M 0x00000010 +#define UMAC_UMCMN_R0_ISR_S4__FW_RELEASE_RING_WDG_ERR___S 4 +#define UMAC_UMCMN_R0_ISR_S4__SW_RELEASE_RING_WDG_ERR___M 0x00000008 +#define UMAC_UMCMN_R0_ISR_S4__SW_RELEASE_RING_WDG_ERR___S 3 +#define UMAC_UMCMN_R0_ISR_S4__REO_RELEASE_RING_WDG_ERR___M 0x00000004 +#define UMAC_UMCMN_R0_ISR_S4__REO_RELEASE_RING_WDG_ERR___S 2 +#define UMAC_UMCMN_R0_ISR_S4__TQM_RELEASE_RING_WDG_ERR___M 0x00000002 +#define UMAC_UMCMN_R0_ISR_S4__TQM_RELEASE_RING_WDG_ERR___S 1 +#define UMAC_UMCMN_R0_ISR_S4__PPE_RELEASE_RING_WDG_ERR___M 0x00000001 +#define UMAC_UMCMN_R0_ISR_S4__PPE_RELEASE_RING_WDG_ERR___S 0 +#define UMAC_UMCMN_R0_ISR_S4___M 0x1FFFFFFF +#define UMAC_UMCMN_R0_ISR_S4___S 0 + +#define UMAC_UMCMN_R0_ISR_S5 (0x00A40050) +#define UMAC_UMCMN_R0_ISR_S5___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_ISR_S5___POR 0x00000000 +#define UMAC_UMCMN_R0_ISR_S5__WBM2SW4_RELEASE_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S5__WBM2SW3_RELEASE_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S5__WBM2SW2_RELEASE_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S5__WBM2SW1_RELEASE_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S5__WBM2SW0_RELEASE_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S5__WBM2FW_RELEASE_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S5__WBM_IDLE_LINK_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S5__WBM_IDLE_BUF_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA2_LINK_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA1_LINK_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA0_LINK_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S5__WBM2FW_LINK_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S5__WBM2SW_LINK_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S5__WBM2REO_LINK_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S5__WBM2TQM_LINK_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA2_BUF_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA1_BUF_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA0_BUF_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S5__WBM2FW_BUF_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S5__WBM2SW_BUF_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S5__WBM2PPE_BUF_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S5__RXDMA2_RELEASE_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S5__RXDMA1_RELEASE_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S5__RXDMA0_RELEASE_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S5__FW_RELEASE_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S5__SW_RELEASE_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S5__REO_RELEASE_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S5__TQM_RELEASE_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S5__PPE_RELEASE_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S5__WBM2SW4_RELEASE_RING_REQ_ERR___M 0x10000000 +#define UMAC_UMCMN_R0_ISR_S5__WBM2SW4_RELEASE_RING_REQ_ERR___S 28 +#define UMAC_UMCMN_R0_ISR_S5__WBM2SW3_RELEASE_RING_REQ_ERR___M 0x08000000 +#define UMAC_UMCMN_R0_ISR_S5__WBM2SW3_RELEASE_RING_REQ_ERR___S 27 +#define UMAC_UMCMN_R0_ISR_S5__WBM2SW2_RELEASE_RING_REQ_ERR___M 0x04000000 +#define UMAC_UMCMN_R0_ISR_S5__WBM2SW2_RELEASE_RING_REQ_ERR___S 26 +#define UMAC_UMCMN_R0_ISR_S5__WBM2SW1_RELEASE_RING_REQ_ERR___M 0x02000000 +#define UMAC_UMCMN_R0_ISR_S5__WBM2SW1_RELEASE_RING_REQ_ERR___S 25 +#define UMAC_UMCMN_R0_ISR_S5__WBM2SW0_RELEASE_RING_REQ_ERR___M 0x01000000 +#define UMAC_UMCMN_R0_ISR_S5__WBM2SW0_RELEASE_RING_REQ_ERR___S 24 +#define UMAC_UMCMN_R0_ISR_S5__WBM2FW_RELEASE_RING_REQ_ERR___M 0x00800000 +#define UMAC_UMCMN_R0_ISR_S5__WBM2FW_RELEASE_RING_REQ_ERR___S 23 +#define UMAC_UMCMN_R0_ISR_S5__WBM_IDLE_LINK_RING_REQ_ERR___M 0x00400000 +#define UMAC_UMCMN_R0_ISR_S5__WBM_IDLE_LINK_RING_REQ_ERR___S 22 +#define UMAC_UMCMN_R0_ISR_S5__WBM_IDLE_BUF_RING_REQ_ERR___M 0x00200000 +#define UMAC_UMCMN_R0_ISR_S5__WBM_IDLE_BUF_RING_REQ_ERR___S 21 +#define UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA2_LINK_RING_REQ_ERR___M 0x00100000 +#define UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA2_LINK_RING_REQ_ERR___S 20 +#define UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA1_LINK_RING_REQ_ERR___M 0x00080000 +#define UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA1_LINK_RING_REQ_ERR___S 19 +#define UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA0_LINK_RING_REQ_ERR___M 0x00040000 +#define UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA0_LINK_RING_REQ_ERR___S 18 +#define UMAC_UMCMN_R0_ISR_S5__WBM2FW_LINK_RING_REQ_ERR___M 0x00020000 +#define UMAC_UMCMN_R0_ISR_S5__WBM2FW_LINK_RING_REQ_ERR___S 17 +#define UMAC_UMCMN_R0_ISR_S5__WBM2SW_LINK_RING_REQ_ERR___M 0x00010000 +#define UMAC_UMCMN_R0_ISR_S5__WBM2SW_LINK_RING_REQ_ERR___S 16 +#define UMAC_UMCMN_R0_ISR_S5__WBM2REO_LINK_RING_REQ_ERR___M 0x00008000 +#define UMAC_UMCMN_R0_ISR_S5__WBM2REO_LINK_RING_REQ_ERR___S 15 +#define UMAC_UMCMN_R0_ISR_S5__WBM2TQM_LINK_RING_REQ_ERR___M 0x00004000 +#define UMAC_UMCMN_R0_ISR_S5__WBM2TQM_LINK_RING_REQ_ERR___S 14 +#define UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA2_BUF_RING_REQ_ERR___M 0x00002000 +#define UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA2_BUF_RING_REQ_ERR___S 13 +#define UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA1_BUF_RING_REQ_ERR___M 0x00001000 +#define UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA1_BUF_RING_REQ_ERR___S 12 +#define UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA0_BUF_RING_REQ_ERR___M 0x00000800 +#define UMAC_UMCMN_R0_ISR_S5__WBM2RXDMA0_BUF_RING_REQ_ERR___S 11 +#define UMAC_UMCMN_R0_ISR_S5__WBM2FW_BUF_RING_REQ_ERR___M 0x00000400 +#define UMAC_UMCMN_R0_ISR_S5__WBM2FW_BUF_RING_REQ_ERR___S 10 +#define UMAC_UMCMN_R0_ISR_S5__WBM2SW_BUF_RING_REQ_ERR___M 0x00000200 +#define UMAC_UMCMN_R0_ISR_S5__WBM2SW_BUF_RING_REQ_ERR___S 9 +#define UMAC_UMCMN_R0_ISR_S5__WBM2PPE_BUF_RING_REQ_ERR___M 0x00000100 +#define UMAC_UMCMN_R0_ISR_S5__WBM2PPE_BUF_RING_REQ_ERR___S 8 +#define UMAC_UMCMN_R0_ISR_S5__RXDMA2_RELEASE_RING_REQ_ERR___M 0x00000080 +#define UMAC_UMCMN_R0_ISR_S5__RXDMA2_RELEASE_RING_REQ_ERR___S 7 +#define UMAC_UMCMN_R0_ISR_S5__RXDMA1_RELEASE_RING_REQ_ERR___M 0x00000040 +#define UMAC_UMCMN_R0_ISR_S5__RXDMA1_RELEASE_RING_REQ_ERR___S 6 +#define UMAC_UMCMN_R0_ISR_S5__RXDMA0_RELEASE_RING_REQ_ERR___M 0x00000020 +#define UMAC_UMCMN_R0_ISR_S5__RXDMA0_RELEASE_RING_REQ_ERR___S 5 +#define UMAC_UMCMN_R0_ISR_S5__FW_RELEASE_RING_REQ_ERR___M 0x00000010 +#define UMAC_UMCMN_R0_ISR_S5__FW_RELEASE_RING_REQ_ERR___S 4 +#define UMAC_UMCMN_R0_ISR_S5__SW_RELEASE_RING_REQ_ERR___M 0x00000008 +#define UMAC_UMCMN_R0_ISR_S5__SW_RELEASE_RING_REQ_ERR___S 3 +#define UMAC_UMCMN_R0_ISR_S5__REO_RELEASE_RING_REQ_ERR___M 0x00000004 +#define UMAC_UMCMN_R0_ISR_S5__REO_RELEASE_RING_REQ_ERR___S 2 +#define UMAC_UMCMN_R0_ISR_S5__TQM_RELEASE_RING_REQ_ERR___M 0x00000002 +#define UMAC_UMCMN_R0_ISR_S5__TQM_RELEASE_RING_REQ_ERR___S 1 +#define UMAC_UMCMN_R0_ISR_S5__PPE_RELEASE_RING_REQ_ERR___M 0x00000001 +#define UMAC_UMCMN_R0_ISR_S5__PPE_RELEASE_RING_REQ_ERR___S 0 +#define UMAC_UMCMN_R0_ISR_S5___M 0x1FFFFFFF +#define UMAC_UMCMN_R0_ISR_S5___S 0 + +#define UMAC_UMCMN_R0_ISR_S6 (0x00A40054) +#define UMAC_UMCMN_R0_ISR_S6___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_ISR_S6___POR 0x00000000 +#define UMAC_UMCMN_R0_ISR_S6__REO_STATUS_RING_WDG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S6__REO_RELEASE_RING_WDG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S6__REO2FW_RING_WDG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S6__REO2TCL_RING_WDG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S6__REO2SW6_RING_WDG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S6__REO2SW5_RING_WDG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S6__REO2SW4_RING_WDG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S6__REO2SW3_RING_WDG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S6__REO2SW2_RING_WDG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S6__REO2SW1_RING_WDG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S6__SW2REO_RING_WDG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S6__REO_CMD_RING_WDG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S6__WBM2REO_LINK_RING_WDG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S6__RXDMA2REO2_RING_WDG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S6__RXDMA2REO1_RING_WDG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S6__RXDMA2REO0_RING_WDG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S6__REO_STATUS_RING_WDG___M 0x00008000 +#define UMAC_UMCMN_R0_ISR_S6__REO_STATUS_RING_WDG___S 15 +#define UMAC_UMCMN_R0_ISR_S6__REO_RELEASE_RING_WDG___M 0x00004000 +#define UMAC_UMCMN_R0_ISR_S6__REO_RELEASE_RING_WDG___S 14 +#define UMAC_UMCMN_R0_ISR_S6__REO2FW_RING_WDG___M 0x00002000 +#define UMAC_UMCMN_R0_ISR_S6__REO2FW_RING_WDG___S 13 +#define UMAC_UMCMN_R0_ISR_S6__REO2TCL_RING_WDG___M 0x00001000 +#define UMAC_UMCMN_R0_ISR_S6__REO2TCL_RING_WDG___S 12 +#define UMAC_UMCMN_R0_ISR_S6__REO2SW6_RING_WDG___M 0x00000800 +#define UMAC_UMCMN_R0_ISR_S6__REO2SW6_RING_WDG___S 11 +#define UMAC_UMCMN_R0_ISR_S6__REO2SW5_RING_WDG___M 0x00000400 +#define UMAC_UMCMN_R0_ISR_S6__REO2SW5_RING_WDG___S 10 +#define UMAC_UMCMN_R0_ISR_S6__REO2SW4_RING_WDG___M 0x00000200 +#define UMAC_UMCMN_R0_ISR_S6__REO2SW4_RING_WDG___S 9 +#define UMAC_UMCMN_R0_ISR_S6__REO2SW3_RING_WDG___M 0x00000100 +#define UMAC_UMCMN_R0_ISR_S6__REO2SW3_RING_WDG___S 8 +#define UMAC_UMCMN_R0_ISR_S6__REO2SW2_RING_WDG___M 0x00000080 +#define UMAC_UMCMN_R0_ISR_S6__REO2SW2_RING_WDG___S 7 +#define UMAC_UMCMN_R0_ISR_S6__REO2SW1_RING_WDG___M 0x00000040 +#define UMAC_UMCMN_R0_ISR_S6__REO2SW1_RING_WDG___S 6 +#define UMAC_UMCMN_R0_ISR_S6__SW2REO_RING_WDG___M 0x00000020 +#define UMAC_UMCMN_R0_ISR_S6__SW2REO_RING_WDG___S 5 +#define UMAC_UMCMN_R0_ISR_S6__REO_CMD_RING_WDG___M 0x00000010 +#define UMAC_UMCMN_R0_ISR_S6__REO_CMD_RING_WDG___S 4 +#define UMAC_UMCMN_R0_ISR_S6__WBM2REO_LINK_RING_WDG___M 0x00000008 +#define UMAC_UMCMN_R0_ISR_S6__WBM2REO_LINK_RING_WDG___S 3 +#define UMAC_UMCMN_R0_ISR_S6__RXDMA2REO2_RING_WDG___M 0x00000004 +#define UMAC_UMCMN_R0_ISR_S6__RXDMA2REO2_RING_WDG___S 2 +#define UMAC_UMCMN_R0_ISR_S6__RXDMA2REO1_RING_WDG___M 0x00000002 +#define UMAC_UMCMN_R0_ISR_S6__RXDMA2REO1_RING_WDG___S 1 +#define UMAC_UMCMN_R0_ISR_S6__RXDMA2REO0_RING_WDG___M 0x00000001 +#define UMAC_UMCMN_R0_ISR_S6__RXDMA2REO0_RING_WDG___S 0 +#define UMAC_UMCMN_R0_ISR_S6___M 0x0000FFFF +#define UMAC_UMCMN_R0_ISR_S6___S 0 + +#define UMAC_UMCMN_R0_ISR_S7 (0x00A40058) +#define UMAC_UMCMN_R0_ISR_S7___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_ISR_S7___POR 0x00000000 +#define UMAC_UMCMN_R0_ISR_S7__REO_CACHE_INT___POR 0x0000 +#define UMAC_UMCMN_R0_ISR_S7__REO_AC_BUF_OVER_THRESH___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S7__REO_CACHE_INT___M 0xFFFF0000 +#define UMAC_UMCMN_R0_ISR_S7__REO_CACHE_INT___S 16 +#define UMAC_UMCMN_R0_ISR_S7__REO_AC_BUF_OVER_THRESH___M 0x0000000F +#define UMAC_UMCMN_R0_ISR_S7__REO_AC_BUF_OVER_THRESH___S 0 +#define UMAC_UMCMN_R0_ISR_S7___M 0xFFFF000F +#define UMAC_UMCMN_R0_ISR_S7___S 0 + +#define UMAC_UMCMN_R0_ISR_S8 (0x00A4005C) +#define UMAC_UMCMN_R0_ISR_S8___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_ISR_S8___POR 0x00000000 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_RESERVED___POR 0x000 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_INVALID_TLV_CMD___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_RX_QUEUE_NUM_MISMATCH___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_REORDER_SW_ZERO_DESC___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_REORDER_AGE_ZERO_DESC___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_REORDER_ZERO_MSDU_LINK_PTR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_REORDER_ZERO_MPDU_LINK_PTR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_SEQ_ZERO_MSDU_BUF_PTR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_BA_NON_AMPDU___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_SEQ_PN_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_BAR_SNEQUAL___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_BAR_NONBA___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_OOR_BAR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_OOR_REG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_2K_BAR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_2K_REG___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_BA_DD___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_NONBA_DD___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_AMPDU_NONBA___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_QD_NOTVALID___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_REORDER_QD_ADDR_ZERO___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_RESERVED___M 0xFFF00000 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_RESERVED___S 20 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_INVALID_TLV_CMD___M 0x00080000 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_INVALID_TLV_CMD___S 19 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_RX_QUEUE_NUM_MISMATCH___M 0x00040000 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_RX_QUEUE_NUM_MISMATCH___S 18 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_REORDER_SW_ZERO_DESC___M 0x00020000 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_REORDER_SW_ZERO_DESC___S 17 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_REORDER_AGE_ZERO_DESC___M 0x00010000 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_REORDER_AGE_ZERO_DESC___S 16 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_REORDER_ZERO_MSDU_LINK_PTR___M 0x00008000 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_REORDER_ZERO_MSDU_LINK_PTR___S 15 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_REORDER_ZERO_MPDU_LINK_PTR___M 0x00004000 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_REORDER_ZERO_MPDU_LINK_PTR___S 14 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_SEQ_ZERO_MSDU_BUF_PTR___M 0x00002000 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_SEQ_ZERO_MSDU_BUF_PTR___S 13 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_BA_NON_AMPDU___M 0x00001000 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_BA_NON_AMPDU___S 12 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_SEQ_PN_ERR___M 0x00000800 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_SEQ_PN_ERR___S 11 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_BAR_SNEQUAL___M 0x00000400 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_BAR_SNEQUAL___S 10 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_BAR_NONBA___M 0x00000200 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_BAR_NONBA___S 9 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_OOR_BAR___M 0x00000100 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_OOR_BAR___S 8 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_OOR_REG___M 0x00000080 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_OOR_REG___S 7 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_2K_BAR___M 0x00000040 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_2K_BAR___S 6 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_2K_REG___M 0x00000020 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_2K_REG___S 5 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_BA_DD___M 0x00000010 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_BA_DD___S 4 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_NONBA_DD___M 0x00000008 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_NONBA_DD___S 3 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_AMPDU_NONBA___M 0x00000004 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_AMPDU_NONBA___S 2 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_QD_NOTVALID___M 0x00000002 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_DD_QD_NOTVALID___S 1 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_REORDER_QD_ADDR_ZERO___M 0x00000001 +#define UMAC_UMCMN_R0_ISR_S8__REO_ERR_INTR_REORDER_QD_ADDR_ZERO___S 0 +#define UMAC_UMCMN_R0_ISR_S8___M 0xFFFFFFFF +#define UMAC_UMCMN_R0_ISR_S8___S 0 + +#define UMAC_UMCMN_R0_ISR_S9 (0x00A40060) +#define UMAC_UMCMN_R0_ISR_S9___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_ISR_S9___POR 0x00000000 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR___POR 0x000 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_STATUS_PROD___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_RELEASE_PROD___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_WIFI_PROD___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_TCL_PROD___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_HOST3_PROD___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_HOST2_PROD___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_HOST1_PROD___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_HOST0_PROD___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_SEQUENCER___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_REORDER___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_MPDU_LINK_PREFETCH___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_REO_CMD_TLV___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_REO_CMD_PREFETCH___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_REO_RING_PREFETCH___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_REO_RING_PREFETCH_READ___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR___M 0x00FF8000 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR___S 15 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_STATUS_PROD___M 0x00004000 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_STATUS_PROD___S 14 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_RELEASE_PROD___M 0x00002000 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_RELEASE_PROD___S 13 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_WIFI_PROD___M 0x00001000 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_WIFI_PROD___S 12 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_TCL_PROD___M 0x00000800 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_TCL_PROD___S 11 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_HOST3_PROD___M 0x00000400 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_HOST3_PROD___S 10 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_HOST2_PROD___M 0x00000200 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_HOST2_PROD___S 9 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_HOST1_PROD___M 0x00000100 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_HOST1_PROD___S 8 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_HOST0_PROD___M 0x00000080 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_HOST0_PROD___S 7 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_SEQUENCER___M 0x00000040 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_SEQUENCER___S 6 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_REORDER___M 0x00000020 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_REORDER___S 5 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_MPDU_LINK_PREFETCH___M 0x00000010 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_MPDU_LINK_PREFETCH___S 4 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_REO_CMD_TLV___M 0x00000008 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_REO_CMD_TLV___S 3 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_REO_CMD_PREFETCH___M 0x00000004 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_REO_CMD_PREFETCH___S 2 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_REO_RING_PREFETCH___M 0x00000002 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_REO_RING_PREFETCH___S 1 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_REO_RING_PREFETCH_READ___M 0x00000001 +#define UMAC_UMCMN_R0_ISR_S9__REO_RESERVED_WDG_ERR_REO_RING_PREFETCH_READ___S 0 +#define UMAC_UMCMN_R0_ISR_S9___M 0x00FFFFFF +#define UMAC_UMCMN_R0_ISR_S9___S 0 + +#define UMAC_UMCMN_R0_ISR_S10 (0x00A40064) +#define UMAC_UMCMN_R0_ISR_S10___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_ISR_S10___POR 0x00000000 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG7_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG6_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG5_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG4_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG3_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG2_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG1_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG0_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_REO_CMD_SRNG_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_LINK_DESC_SRNG_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_ENTR_SRNG3_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_ENTR_SRNG2_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_ENTR_SRNG1_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_ENTR_SRNG0_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT___M 0x0000C000 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT___S 14 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG7_REQ_ERR___M 0x00002000 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG7_REQ_ERR___S 13 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG6_REQ_ERR___M 0x00001000 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG6_REQ_ERR___S 12 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG5_REQ_ERR___M 0x00000800 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG5_REQ_ERR___S 11 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG4_REQ_ERR___M 0x00000400 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG4_REQ_ERR___S 10 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG3_REQ_ERR___M 0x00000200 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG3_REQ_ERR___S 9 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG2_REQ_ERR___M 0x00000100 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG2_REQ_ERR___S 8 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG1_REQ_ERR___M 0x00000080 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG1_REQ_ERR___S 7 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG0_REQ_ERR___M 0x00000040 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_HOST_SRNG0_REQ_ERR___S 6 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_REO_CMD_SRNG_REQ_ERR___M 0x00000020 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_REO_CMD_SRNG_REQ_ERR___S 5 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_LINK_DESC_SRNG_REQ_ERR___M 0x00000010 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_LINK_DESC_SRNG_REQ_ERR___S 4 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_ENTR_SRNG3_REQ_ERR___M 0x00000008 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_ENTR_SRNG3_REQ_ERR___S 3 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_ENTR_SRNG2_REQ_ERR___M 0x00000004 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_ENTR_SRNG2_REQ_ERR___S 2 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_ENTR_SRNG1_REQ_ERR___M 0x00000002 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_ENTR_SRNG1_REQ_ERR___S 1 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_ENTR_SRNG0_REQ_ERR___M 0x00000001 +#define UMAC_UMCMN_R0_ISR_S10__REO_RESERVED_INT_ENTR_SRNG0_REQ_ERR___S 0 +#define UMAC_UMCMN_R0_ISR_S10___M 0x0000FFFF +#define UMAC_UMCMN_R0_ISR_S10___S 0 + +#define UMAC_UMCMN_R0_ISR_S11 (0x00A40068) +#define UMAC_UMCMN_R0_ISR_S11___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_ISR_S11___POR 0x00000000 +#define UMAC_UMCMN_R0_ISR_S11__TCL_STATUS2_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S11__TCL_STATUS2_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S11__TCL_STATUS1_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S11__TCL_STATUS1_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S11__TCL_TCL2FW_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S11__TCL_TCL2FW_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S11__TCL_TCL2TQM_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S11__TCL_TCL2TQM_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL_CREDIT_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL_CREDIT_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S11__TCL_FW2TCL1_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S11__TCL_FW2TCL1_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL3_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL3_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL2_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL2_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL1_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL1_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S11__TCL_STATUS2_RING_WDG_ERR___M 0x00020000 +#define UMAC_UMCMN_R0_ISR_S11__TCL_STATUS2_RING_WDG_ERR___S 17 +#define UMAC_UMCMN_R0_ISR_S11__TCL_STATUS2_RING_REQ_ERR___M 0x00010000 +#define UMAC_UMCMN_R0_ISR_S11__TCL_STATUS2_RING_REQ_ERR___S 16 +#define UMAC_UMCMN_R0_ISR_S11__TCL_STATUS1_RING_WDG_ERR___M 0x00008000 +#define UMAC_UMCMN_R0_ISR_S11__TCL_STATUS1_RING_WDG_ERR___S 15 +#define UMAC_UMCMN_R0_ISR_S11__TCL_STATUS1_RING_REQ_ERR___M 0x00004000 +#define UMAC_UMCMN_R0_ISR_S11__TCL_STATUS1_RING_REQ_ERR___S 14 +#define UMAC_UMCMN_R0_ISR_S11__TCL_TCL2FW_RING_WDG_ERR___M 0x00002000 +#define UMAC_UMCMN_R0_ISR_S11__TCL_TCL2FW_RING_WDG_ERR___S 13 +#define UMAC_UMCMN_R0_ISR_S11__TCL_TCL2FW_RING_REQ_ERR___M 0x00001000 +#define UMAC_UMCMN_R0_ISR_S11__TCL_TCL2FW_RING_REQ_ERR___S 12 +#define UMAC_UMCMN_R0_ISR_S11__TCL_TCL2TQM_RING_WDG_ERR___M 0x00000800 +#define UMAC_UMCMN_R0_ISR_S11__TCL_TCL2TQM_RING_WDG_ERR___S 11 +#define UMAC_UMCMN_R0_ISR_S11__TCL_TCL2TQM_RING_REQ_ERR___M 0x00000400 +#define UMAC_UMCMN_R0_ISR_S11__TCL_TCL2TQM_RING_REQ_ERR___S 10 +#define UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL_CREDIT_RING_WDG_ERR___M 0x00000200 +#define UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL_CREDIT_RING_WDG_ERR___S 9 +#define UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL_CREDIT_RING_REQ_ERR___M 0x00000100 +#define UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL_CREDIT_RING_REQ_ERR___S 8 +#define UMAC_UMCMN_R0_ISR_S11__TCL_FW2TCL1_RING_WDG_ERR___M 0x00000080 +#define UMAC_UMCMN_R0_ISR_S11__TCL_FW2TCL1_RING_WDG_ERR___S 7 +#define UMAC_UMCMN_R0_ISR_S11__TCL_FW2TCL1_RING_REQ_ERR___M 0x00000040 +#define UMAC_UMCMN_R0_ISR_S11__TCL_FW2TCL1_RING_REQ_ERR___S 6 +#define UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL3_RING_WDG_ERR___M 0x00000020 +#define UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL3_RING_WDG_ERR___S 5 +#define UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL3_RING_REQ_ERR___M 0x00000010 +#define UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL3_RING_REQ_ERR___S 4 +#define UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL2_RING_WDG_ERR___M 0x00000008 +#define UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL2_RING_WDG_ERR___S 3 +#define UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL2_RING_REQ_ERR___M 0x00000004 +#define UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL2_RING_REQ_ERR___S 2 +#define UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL1_RING_WDG_ERR___M 0x00000002 +#define UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL1_RING_WDG_ERR___S 1 +#define UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL1_RING_REQ_ERR___M 0x00000001 +#define UMAC_UMCMN_R0_ISR_S11__TCL_SW2TCL1_RING_REQ_ERR___S 0 +#define UMAC_UMCMN_R0_ISR_S11___M 0x0003FFFF +#define UMAC_UMCMN_R0_ISR_S11___S 0 + +#define UMAC_UMCMN_R0_ISR_S12 (0x00A4006C) +#define UMAC_UMCMN_R0_ISR_S12___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_ISR_S12___POR 0x00000000 +#define UMAC_UMCMN_R0_ISR_S12__TCL_CCE_ERR_CLASSIFY_DIS___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S12__TCL_CCE_WDG_TO___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_IPV6_JUMBOGRAM___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_IPV6_EXT_HD_BYTES_EXCEED___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_MSDU_LEN_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_ETH_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_WMAC_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_WDG_TO___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S12__TCL_SW2TCL_CREDIT_ZERO_LEN_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S12__TCL_FW2TCL1_ZERO_LEN_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S12__TCL_SW2TCL3_ZERO_LEN_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S12__TCL_SW2TCL2_ZERO_LEN_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S12__TCL_SW2TCL1_ZERO_LEN_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S12__TCL_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S12__TCL_CCE_ERR_CLASSIFY_DIS___M 0x00002000 +#define UMAC_UMCMN_R0_ISR_S12__TCL_CCE_ERR_CLASSIFY_DIS___S 13 +#define UMAC_UMCMN_R0_ISR_S12__TCL_CCE_WDG_TO___M 0x00001000 +#define UMAC_UMCMN_R0_ISR_S12__TCL_CCE_WDG_TO___S 12 +#define UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_IPV6_JUMBOGRAM___M 0x00000800 +#define UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_IPV6_JUMBOGRAM___S 11 +#define UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_IPV6_EXT_HD_BYTES_EXCEED___M 0x00000400 +#define UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_IPV6_EXT_HD_BYTES_EXCEED___S 10 +#define UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_MSDU_LEN_ERR___M 0x00000200 +#define UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_MSDU_LEN_ERR___S 9 +#define UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_ETH_ERR___M 0x00000100 +#define UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_ETH_ERR___S 8 +#define UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_WMAC_ERR___M 0x00000080 +#define UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_WMAC_ERR___S 7 +#define UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_WDG_TO___M 0x00000040 +#define UMAC_UMCMN_R0_ISR_S12__TCL_CMN_PRSR_WDG_TO___S 6 +#define UMAC_UMCMN_R0_ISR_S12__TCL_SW2TCL_CREDIT_ZERO_LEN_ERR___M 0x00000020 +#define UMAC_UMCMN_R0_ISR_S12__TCL_SW2TCL_CREDIT_ZERO_LEN_ERR___S 5 +#define UMAC_UMCMN_R0_ISR_S12__TCL_FW2TCL1_ZERO_LEN_ERR___M 0x00000010 +#define UMAC_UMCMN_R0_ISR_S12__TCL_FW2TCL1_ZERO_LEN_ERR___S 4 +#define UMAC_UMCMN_R0_ISR_S12__TCL_SW2TCL3_ZERO_LEN_ERR___M 0x00000008 +#define UMAC_UMCMN_R0_ISR_S12__TCL_SW2TCL3_ZERO_LEN_ERR___S 3 +#define UMAC_UMCMN_R0_ISR_S12__TCL_SW2TCL2_ZERO_LEN_ERR___M 0x00000004 +#define UMAC_UMCMN_R0_ISR_S12__TCL_SW2TCL2_ZERO_LEN_ERR___S 2 +#define UMAC_UMCMN_R0_ISR_S12__TCL_SW2TCL1_ZERO_LEN_ERR___M 0x00000002 +#define UMAC_UMCMN_R0_ISR_S12__TCL_SW2TCL1_ZERO_LEN_ERR___S 1 +#define UMAC_UMCMN_R0_ISR_S12__TCL_WDG_ERR___M 0x00000001 +#define UMAC_UMCMN_R0_ISR_S12__TCL_WDG_ERR___S 0 +#define UMAC_UMCMN_R0_ISR_S12___M 0x00003FFF +#define UMAC_UMCMN_R0_ISR_S12___S 0 + +#define UMAC_UMCMN_R0_ISR_S13 (0x00A40070) +#define UMAC_UMCMN_R0_ISR_S13___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_ISR_S13___POR 0x00000000 +#define UMAC_UMCMN_R0_ISR_S13__TQM_DESC_PTR_RELEASE_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S13__TQM_DESC_PTR_RELEASE_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S13__TQM_STATUS1_UPDATE_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S13__TQM_STATUS1_UPDATE_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S13__TQM_STATUS_UPDATE_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S13__TQM_STATUS_UPDATE_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S13__TQM_DESC_PTR_FETCH_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S13__TQM_DESC_PTR_FETCH_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD3_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD3_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD2_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD2_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD1_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD1_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S13__TQM_SW_CMD_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S13__TQM_SW_CMD_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT3_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT3_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT2_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT2_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT1_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT1_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S13__TQM_DESC_PTR_RELEASE_RING_REQ_ERR___M 0x00200000 +#define UMAC_UMCMN_R0_ISR_S13__TQM_DESC_PTR_RELEASE_RING_REQ_ERR___S 21 +#define UMAC_UMCMN_R0_ISR_S13__TQM_DESC_PTR_RELEASE_RING_WDG_ERR___M 0x00100000 +#define UMAC_UMCMN_R0_ISR_S13__TQM_DESC_PTR_RELEASE_RING_WDG_ERR___S 20 +#define UMAC_UMCMN_R0_ISR_S13__TQM_STATUS1_UPDATE_RING_REQ_ERR___M 0x00080000 +#define UMAC_UMCMN_R0_ISR_S13__TQM_STATUS1_UPDATE_RING_REQ_ERR___S 19 +#define UMAC_UMCMN_R0_ISR_S13__TQM_STATUS1_UPDATE_RING_WDG_ERR___M 0x00040000 +#define UMAC_UMCMN_R0_ISR_S13__TQM_STATUS1_UPDATE_RING_WDG_ERR___S 18 +#define UMAC_UMCMN_R0_ISR_S13__TQM_STATUS_UPDATE_RING_REQ_ERR___M 0x00020000 +#define UMAC_UMCMN_R0_ISR_S13__TQM_STATUS_UPDATE_RING_REQ_ERR___S 17 +#define UMAC_UMCMN_R0_ISR_S13__TQM_STATUS_UPDATE_RING_WDG_ERR___M 0x00010000 +#define UMAC_UMCMN_R0_ISR_S13__TQM_STATUS_UPDATE_RING_WDG_ERR___S 16 +#define UMAC_UMCMN_R0_ISR_S13__TQM_DESC_PTR_FETCH_RING_REQ_ERR___M 0x00008000 +#define UMAC_UMCMN_R0_ISR_S13__TQM_DESC_PTR_FETCH_RING_REQ_ERR___S 15 +#define UMAC_UMCMN_R0_ISR_S13__TQM_DESC_PTR_FETCH_RING_WDG_ERR___M 0x00004000 +#define UMAC_UMCMN_R0_ISR_S13__TQM_DESC_PTR_FETCH_RING_WDG_ERR___S 14 +#define UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD3_RING_REQ_ERR___M 0x00002000 +#define UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD3_RING_REQ_ERR___S 13 +#define UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD3_RING_WDG_ERR___M 0x00001000 +#define UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD3_RING_WDG_ERR___S 12 +#define UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD2_RING_REQ_ERR___M 0x00000800 +#define UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD2_RING_REQ_ERR___S 11 +#define UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD2_RING_WDG_ERR___M 0x00000400 +#define UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD2_RING_WDG_ERR___S 10 +#define UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD1_RING_REQ_ERR___M 0x00000200 +#define UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD1_RING_REQ_ERR___S 9 +#define UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD1_RING_WDG_ERR___M 0x00000100 +#define UMAC_UMCMN_R0_ISR_S13__TQM_HWSCH_CMD1_RING_WDG_ERR___S 8 +#define UMAC_UMCMN_R0_ISR_S13__TQM_SW_CMD_RING_REQ_ERR___M 0x00000080 +#define UMAC_UMCMN_R0_ISR_S13__TQM_SW_CMD_RING_REQ_ERR___S 7 +#define UMAC_UMCMN_R0_ISR_S13__TQM_SW_CMD_RING_WDG_ERR___M 0x00000040 +#define UMAC_UMCMN_R0_ISR_S13__TQM_SW_CMD_RING_WDG_ERR___S 6 +#define UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT3_RING_REQ_ERR___M 0x00000020 +#define UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT3_RING_REQ_ERR___S 5 +#define UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT3_RING_WDG_ERR___M 0x00000010 +#define UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT3_RING_WDG_ERR___S 4 +#define UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT2_RING_REQ_ERR___M 0x00000008 +#define UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT2_RING_REQ_ERR___S 3 +#define UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT2_RING_WDG_ERR___M 0x00000004 +#define UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT2_RING_WDG_ERR___S 2 +#define UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT1_RING_REQ_ERR___M 0x00000002 +#define UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT1_RING_REQ_ERR___S 1 +#define UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT1_RING_WDG_ERR___M 0x00000001 +#define UMAC_UMCMN_R0_ISR_S13__TQM_MSDU_ENT1_RING_WDG_ERR___S 0 +#define UMAC_UMCMN_R0_ISR_S13___M 0x003FFFFF +#define UMAC_UMCMN_R0_ISR_S13___S 0 + +#define UMAC_UMCMN_R0_ISR_S14 (0x00A40074) +#define UMAC_UMCMN_R0_ISR_S14___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_ISR_S14___POR 0x00000000 +#define UMAC_UMCMN_R0_ISR_S14__TQM_CACHE_CTL_ERR___POR 0x000 +#define UMAC_UMCMN_R0_ISR_S14__TQM_WDG_TIMEOUT___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S14__TQM_SW_PRGM_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S14__TQM_CMD_SM_ERR___POR 0x00 +#define UMAC_UMCMN_R0_ISR_S14__TQM_CACHE_CTL_ERR___M 0x0FFF0000 +#define UMAC_UMCMN_R0_ISR_S14__TQM_CACHE_CTL_ERR___S 16 +#define UMAC_UMCMN_R0_ISR_S14__TQM_WDG_TIMEOUT___M 0x00000800 +#define UMAC_UMCMN_R0_ISR_S14__TQM_WDG_TIMEOUT___S 11 +#define UMAC_UMCMN_R0_ISR_S14__TQM_SW_PRGM_ERR___M 0x00000400 +#define UMAC_UMCMN_R0_ISR_S14__TQM_SW_PRGM_ERR___S 10 +#define UMAC_UMCMN_R0_ISR_S14__TQM_CMD_SM_ERR___M 0x000000FF +#define UMAC_UMCMN_R0_ISR_S14__TQM_CMD_SM_ERR___S 0 +#define UMAC_UMCMN_R0_ISR_S14___M 0x0FFF0CFF +#define UMAC_UMCMN_R0_ISR_S14___S 0 + +#define UMAC_UMCMN_R0_ISR_S15 (0x00A40078) +#define UMAC_UMCMN_R0_ISR_S15___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_ISR_S15___POR 0x00000000 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_QUEUE_HEAD_MAC0___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_UNPAUSE_LINK_DESC_THRESHOLD___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_ILLEGAL_HWSCH_CMD___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_ILLEGAL_SW_CMD___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT2_DEC_EMPTY___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT1_DEC_EMPTY___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT0_DEC_EMPTY___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT2_SATURATE___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT1_SATURATE___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT0_SATURATE___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD2_REACHED___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD1_REACHED___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD0_REACHED___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_AGGR_LINK_DESC_THRESHOLD_REACHED___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_SW_CMD1_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_SW_CMD1_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_SW_CMD1_RING_SW_INT___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_QUEUE_HEAD_MAC0___M 0x00010000 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_QUEUE_HEAD_MAC0___S 16 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_UNPAUSE_LINK_DESC_THRESHOLD___M 0x00008000 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_UNPAUSE_LINK_DESC_THRESHOLD___S 15 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_ILLEGAL_HWSCH_CMD___M 0x00004000 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_ILLEGAL_HWSCH_CMD___S 14 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_ILLEGAL_SW_CMD___M 0x00002000 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_ILLEGAL_SW_CMD___S 13 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT2_DEC_EMPTY___M 0x00001000 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT2_DEC_EMPTY___S 12 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT1_DEC_EMPTY___M 0x00000800 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT1_DEC_EMPTY___S 11 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT0_DEC_EMPTY___M 0x00000400 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT0_DEC_EMPTY___S 10 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT2_SATURATE___M 0x00000200 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT2_SATURATE___S 9 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT1_SATURATE___M 0x00000100 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT1_SATURATE___S 8 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT0_SATURATE___M 0x00000080 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_CNT0_SATURATE___S 7 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD2_REACHED___M 0x00000040 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD2_REACHED___S 6 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD1_REACHED___M 0x00000020 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD1_REACHED___S 5 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD0_REACHED___M 0x00000010 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD0_REACHED___S 4 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_AGGR_LINK_DESC_THRESHOLD_REACHED___M 0x00000008 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_AGGR_LINK_DESC_THRESHOLD_REACHED___S 3 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_SW_CMD1_RING_REQ_ERR___M 0x00000004 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_SW_CMD1_RING_REQ_ERR___S 2 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_SW_CMD1_RING_WDG_ERR___M 0x00000002 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_SW_CMD1_RING_WDG_ERR___S 1 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_SW_CMD1_RING_SW_INT___M 0x00000001 +#define UMAC_UMCMN_R0_ISR_S15__TQM_RESERVED_SW_CMD1_RING_SW_INT___S 0 +#define UMAC_UMCMN_R0_ISR_S15___M 0x0001FFFF +#define UMAC_UMCMN_R0_ISR_S15___S 0 + +#define UMAC_UMCMN_R0_ISR_S16 (0x00A4007C) +#define UMAC_UMCMN_R0_ISR_S16___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_ISR_S16___POR 0x00000000 +#define UMAC_UMCMN_R0_ISR_S16__REO_GXI_INTR___POR 0x0000 +#define UMAC_UMCMN_R0_ISR_S16__CE_GXI_AXI_WR_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S16__CE_GXI_AXI_RD_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S16__CE_GXI_LAST_WR_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S16__CE_GXI_WDTO___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S16__TQM_GXI_AXI_WR_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S16__TQM_GXI_AXI_RD_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S16__TQM_GXI_LAST_WR_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S16__TQM_GXI_WDTO___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S16__TCL_GXI_AXI_WR_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S16__TCL_GXI_AXI_RD_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S16__TCL_GXI_LAST_WR_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S16__TCL_GXI_WDTO___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S16__WBM_GXI_AXI_WR_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S16__WBM_GXI_AXI_RD_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S16__WBM_GXI_LAST_WR_ERR___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S16__WBM_GXI_WDTO___POR 0x0 +#define UMAC_UMCMN_R0_ISR_S16__REO_GXI_INTR___M 0xFFFF0000 +#define UMAC_UMCMN_R0_ISR_S16__REO_GXI_INTR___S 16 +#define UMAC_UMCMN_R0_ISR_S16__CE_GXI_AXI_WR_ERR___M 0x00008000 +#define UMAC_UMCMN_R0_ISR_S16__CE_GXI_AXI_WR_ERR___S 15 +#define UMAC_UMCMN_R0_ISR_S16__CE_GXI_AXI_RD_ERR___M 0x00004000 +#define UMAC_UMCMN_R0_ISR_S16__CE_GXI_AXI_RD_ERR___S 14 +#define UMAC_UMCMN_R0_ISR_S16__CE_GXI_LAST_WR_ERR___M 0x00002000 +#define UMAC_UMCMN_R0_ISR_S16__CE_GXI_LAST_WR_ERR___S 13 +#define UMAC_UMCMN_R0_ISR_S16__CE_GXI_WDTO___M 0x00001000 +#define UMAC_UMCMN_R0_ISR_S16__CE_GXI_WDTO___S 12 +#define UMAC_UMCMN_R0_ISR_S16__TQM_GXI_AXI_WR_ERR___M 0x00000800 +#define UMAC_UMCMN_R0_ISR_S16__TQM_GXI_AXI_WR_ERR___S 11 +#define UMAC_UMCMN_R0_ISR_S16__TQM_GXI_AXI_RD_ERR___M 0x00000400 +#define UMAC_UMCMN_R0_ISR_S16__TQM_GXI_AXI_RD_ERR___S 10 +#define UMAC_UMCMN_R0_ISR_S16__TQM_GXI_LAST_WR_ERR___M 0x00000200 +#define UMAC_UMCMN_R0_ISR_S16__TQM_GXI_LAST_WR_ERR___S 9 +#define UMAC_UMCMN_R0_ISR_S16__TQM_GXI_WDTO___M 0x00000100 +#define UMAC_UMCMN_R0_ISR_S16__TQM_GXI_WDTO___S 8 +#define UMAC_UMCMN_R0_ISR_S16__TCL_GXI_AXI_WR_ERR___M 0x00000080 +#define UMAC_UMCMN_R0_ISR_S16__TCL_GXI_AXI_WR_ERR___S 7 +#define UMAC_UMCMN_R0_ISR_S16__TCL_GXI_AXI_RD_ERR___M 0x00000040 +#define UMAC_UMCMN_R0_ISR_S16__TCL_GXI_AXI_RD_ERR___S 6 +#define UMAC_UMCMN_R0_ISR_S16__TCL_GXI_LAST_WR_ERR___M 0x00000020 +#define UMAC_UMCMN_R0_ISR_S16__TCL_GXI_LAST_WR_ERR___S 5 +#define UMAC_UMCMN_R0_ISR_S16__TCL_GXI_WDTO___M 0x00000010 +#define UMAC_UMCMN_R0_ISR_S16__TCL_GXI_WDTO___S 4 +#define UMAC_UMCMN_R0_ISR_S16__WBM_GXI_AXI_WR_ERR___M 0x00000008 +#define UMAC_UMCMN_R0_ISR_S16__WBM_GXI_AXI_WR_ERR___S 3 +#define UMAC_UMCMN_R0_ISR_S16__WBM_GXI_AXI_RD_ERR___M 0x00000004 +#define UMAC_UMCMN_R0_ISR_S16__WBM_GXI_AXI_RD_ERR___S 2 +#define UMAC_UMCMN_R0_ISR_S16__WBM_GXI_LAST_WR_ERR___M 0x00000002 +#define UMAC_UMCMN_R0_ISR_S16__WBM_GXI_LAST_WR_ERR___S 1 +#define UMAC_UMCMN_R0_ISR_S16__WBM_GXI_WDTO___M 0x00000001 +#define UMAC_UMCMN_R0_ISR_S16__WBM_GXI_WDTO___S 0 +#define UMAC_UMCMN_R0_ISR_S16___M 0xFFFFFFFF +#define UMAC_UMCMN_R0_ISR_S16___S 0 + +#define UMAC_UMCMN_R0_IMR_P (0x00A40080) +#define UMAC_UMCMN_R0_IMR_P___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_IMR_P___POR 0x00000000 +#define UMAC_UMCMN_R0_IMR_P__GXI___POR 0x0 +#define UMAC_UMCMN_R0_IMR_P__TQM2___POR 0x0 +#define UMAC_UMCMN_R0_IMR_P__TQM1___POR 0x0 +#define UMAC_UMCMN_R0_IMR_P__TQM0___POR 0x0 +#define UMAC_UMCMN_R0_IMR_P__TCL1___POR 0x0 +#define UMAC_UMCMN_R0_IMR_P__TCL0___POR 0x0 +#define UMAC_UMCMN_R0_IMR_P__REO4___POR 0x0 +#define UMAC_UMCMN_R0_IMR_P__REO3___POR 0x0 +#define UMAC_UMCMN_R0_IMR_P__REO2___POR 0x0 +#define UMAC_UMCMN_R0_IMR_P__REO1___POR 0x0 +#define UMAC_UMCMN_R0_IMR_P__REO0___POR 0x0 +#define UMAC_UMCMN_R0_IMR_P__WBM2___POR 0x0 +#define UMAC_UMCMN_R0_IMR_P__WBM1___POR 0x0 +#define UMAC_UMCMN_R0_IMR_P__WBM0___POR 0x0 +#define UMAC_UMCMN_R0_IMR_P__MEM___POR 0x0 +#define UMAC_UMCMN_R0_IMR_P__CXC___POR 0x0 +#define UMAC_UMCMN_R0_IMR_P__APB___POR 0x0 +#define UMAC_UMCMN_R0_IMR_P__GXI___M 0x00010000 +#define UMAC_UMCMN_R0_IMR_P__GXI___S 16 +#define UMAC_UMCMN_R0_IMR_P__TQM2___M 0x00008000 +#define UMAC_UMCMN_R0_IMR_P__TQM2___S 15 +#define UMAC_UMCMN_R0_IMR_P__TQM1___M 0x00004000 +#define UMAC_UMCMN_R0_IMR_P__TQM1___S 14 +#define UMAC_UMCMN_R0_IMR_P__TQM0___M 0x00002000 +#define UMAC_UMCMN_R0_IMR_P__TQM0___S 13 +#define UMAC_UMCMN_R0_IMR_P__TCL1___M 0x00001000 +#define UMAC_UMCMN_R0_IMR_P__TCL1___S 12 +#define UMAC_UMCMN_R0_IMR_P__TCL0___M 0x00000800 +#define UMAC_UMCMN_R0_IMR_P__TCL0___S 11 +#define UMAC_UMCMN_R0_IMR_P__REO4___M 0x00000400 +#define UMAC_UMCMN_R0_IMR_P__REO4___S 10 +#define UMAC_UMCMN_R0_IMR_P__REO3___M 0x00000200 +#define UMAC_UMCMN_R0_IMR_P__REO3___S 9 +#define UMAC_UMCMN_R0_IMR_P__REO2___M 0x00000100 +#define UMAC_UMCMN_R0_IMR_P__REO2___S 8 +#define UMAC_UMCMN_R0_IMR_P__REO1___M 0x00000080 +#define UMAC_UMCMN_R0_IMR_P__REO1___S 7 +#define UMAC_UMCMN_R0_IMR_P__REO0___M 0x00000040 +#define UMAC_UMCMN_R0_IMR_P__REO0___S 6 +#define UMAC_UMCMN_R0_IMR_P__WBM2___M 0x00000020 +#define UMAC_UMCMN_R0_IMR_P__WBM2___S 5 +#define UMAC_UMCMN_R0_IMR_P__WBM1___M 0x00000010 +#define UMAC_UMCMN_R0_IMR_P__WBM1___S 4 +#define UMAC_UMCMN_R0_IMR_P__WBM0___M 0x00000008 +#define UMAC_UMCMN_R0_IMR_P__WBM0___S 3 +#define UMAC_UMCMN_R0_IMR_P__MEM___M 0x00000004 +#define UMAC_UMCMN_R0_IMR_P__MEM___S 2 +#define UMAC_UMCMN_R0_IMR_P__CXC___M 0x00000002 +#define UMAC_UMCMN_R0_IMR_P__CXC___S 1 +#define UMAC_UMCMN_R0_IMR_P__APB___M 0x00000001 +#define UMAC_UMCMN_R0_IMR_P__APB___S 0 +#define UMAC_UMCMN_R0_IMR_P___M 0x0001FFFF +#define UMAC_UMCMN_R0_IMR_P___S 0 + +#define UMAC_UMCMN_R0_IMR_S0 (0x00A40084) +#define UMAC_UMCMN_R0_IMR_S0___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_IMR_S0___POR 0x00000000 +#define UMAC_UMCMN_R0_IMR_S0__CE_APB_RD_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S0__CE_APB_WR_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S0__CE_APB_WR_TO_RD_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S0__UMCMN_APB_RD_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S0__UMCMN_APB_WR_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S0__UMCMN_APB_WR_TO_RD_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S0__TQM_APB_RD_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S0__TQM_APB_WR_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S0__TQM_APB_WR_TO_RD_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S0__CMN_PRSR_APB_RD_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S0__CMN_PRSR_APB_WR_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S0__CMN_PRSR_APB_WR_TO_RD_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S0__CCE_APB_RD_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S0__CCE_APB_WR_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S0__CCE_APB_WR_TO_RD_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S0__WBM_APB_RD_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S0__WBM_APB_WR_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S0__WBM_APB_WR_TO_RD_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S0__TCL_APB_RD_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S0__TCL_APB_WR_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S0__TCL_APB_WR_TO_RD_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S0__REO_APB_RD_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S0__REO_APB_WR_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S0__REO_APB_WR_TO_RD_INVALID___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S0__CE_APB_RD_INVALID___M 0x00800000 +#define UMAC_UMCMN_R0_IMR_S0__CE_APB_RD_INVALID___S 23 +#define UMAC_UMCMN_R0_IMR_S0__CE_APB_WR_INVALID___M 0x00400000 +#define UMAC_UMCMN_R0_IMR_S0__CE_APB_WR_INVALID___S 22 +#define UMAC_UMCMN_R0_IMR_S0__CE_APB_WR_TO_RD_INVALID___M 0x00200000 +#define UMAC_UMCMN_R0_IMR_S0__CE_APB_WR_TO_RD_INVALID___S 21 +#define UMAC_UMCMN_R0_IMR_S0__UMCMN_APB_RD_INVALID___M 0x00100000 +#define UMAC_UMCMN_R0_IMR_S0__UMCMN_APB_RD_INVALID___S 20 +#define UMAC_UMCMN_R0_IMR_S0__UMCMN_APB_WR_INVALID___M 0x00080000 +#define UMAC_UMCMN_R0_IMR_S0__UMCMN_APB_WR_INVALID___S 19 +#define UMAC_UMCMN_R0_IMR_S0__UMCMN_APB_WR_TO_RD_INVALID___M 0x00040000 +#define UMAC_UMCMN_R0_IMR_S0__UMCMN_APB_WR_TO_RD_INVALID___S 18 +#define UMAC_UMCMN_R0_IMR_S0__TQM_APB_RD_INVALID___M 0x00020000 +#define UMAC_UMCMN_R0_IMR_S0__TQM_APB_RD_INVALID___S 17 +#define UMAC_UMCMN_R0_IMR_S0__TQM_APB_WR_INVALID___M 0x00010000 +#define UMAC_UMCMN_R0_IMR_S0__TQM_APB_WR_INVALID___S 16 +#define UMAC_UMCMN_R0_IMR_S0__TQM_APB_WR_TO_RD_INVALID___M 0x00008000 +#define UMAC_UMCMN_R0_IMR_S0__TQM_APB_WR_TO_RD_INVALID___S 15 +#define UMAC_UMCMN_R0_IMR_S0__CMN_PRSR_APB_RD_INVALID___M 0x00004000 +#define UMAC_UMCMN_R0_IMR_S0__CMN_PRSR_APB_RD_INVALID___S 14 +#define UMAC_UMCMN_R0_IMR_S0__CMN_PRSR_APB_WR_INVALID___M 0x00002000 +#define UMAC_UMCMN_R0_IMR_S0__CMN_PRSR_APB_WR_INVALID___S 13 +#define UMAC_UMCMN_R0_IMR_S0__CMN_PRSR_APB_WR_TO_RD_INVALID___M 0x00001000 +#define UMAC_UMCMN_R0_IMR_S0__CMN_PRSR_APB_WR_TO_RD_INVALID___S 12 +#define UMAC_UMCMN_R0_IMR_S0__CCE_APB_RD_INVALID___M 0x00000800 +#define UMAC_UMCMN_R0_IMR_S0__CCE_APB_RD_INVALID___S 11 +#define UMAC_UMCMN_R0_IMR_S0__CCE_APB_WR_INVALID___M 0x00000400 +#define UMAC_UMCMN_R0_IMR_S0__CCE_APB_WR_INVALID___S 10 +#define UMAC_UMCMN_R0_IMR_S0__CCE_APB_WR_TO_RD_INVALID___M 0x00000200 +#define UMAC_UMCMN_R0_IMR_S0__CCE_APB_WR_TO_RD_INVALID___S 9 +#define UMAC_UMCMN_R0_IMR_S0__WBM_APB_RD_INVALID___M 0x00000100 +#define UMAC_UMCMN_R0_IMR_S0__WBM_APB_RD_INVALID___S 8 +#define UMAC_UMCMN_R0_IMR_S0__WBM_APB_WR_INVALID___M 0x00000080 +#define UMAC_UMCMN_R0_IMR_S0__WBM_APB_WR_INVALID___S 7 +#define UMAC_UMCMN_R0_IMR_S0__WBM_APB_WR_TO_RD_INVALID___M 0x00000040 +#define UMAC_UMCMN_R0_IMR_S0__WBM_APB_WR_TO_RD_INVALID___S 6 +#define UMAC_UMCMN_R0_IMR_S0__TCL_APB_RD_INVALID___M 0x00000020 +#define UMAC_UMCMN_R0_IMR_S0__TCL_APB_RD_INVALID___S 5 +#define UMAC_UMCMN_R0_IMR_S0__TCL_APB_WR_INVALID___M 0x00000010 +#define UMAC_UMCMN_R0_IMR_S0__TCL_APB_WR_INVALID___S 4 +#define UMAC_UMCMN_R0_IMR_S0__TCL_APB_WR_TO_RD_INVALID___M 0x00000008 +#define UMAC_UMCMN_R0_IMR_S0__TCL_APB_WR_TO_RD_INVALID___S 3 +#define UMAC_UMCMN_R0_IMR_S0__REO_APB_RD_INVALID___M 0x00000004 +#define UMAC_UMCMN_R0_IMR_S0__REO_APB_RD_INVALID___S 2 +#define UMAC_UMCMN_R0_IMR_S0__REO_APB_WR_INVALID___M 0x00000002 +#define UMAC_UMCMN_R0_IMR_S0__REO_APB_WR_INVALID___S 1 +#define UMAC_UMCMN_R0_IMR_S0__REO_APB_WR_TO_RD_INVALID___M 0x00000001 +#define UMAC_UMCMN_R0_IMR_S0__REO_APB_WR_TO_RD_INVALID___S 0 +#define UMAC_UMCMN_R0_IMR_S0___M 0x00FFFFFF +#define UMAC_UMCMN_R0_IMR_S0___S 0 + +#define UMAC_UMCMN_R0_IMR_S1 (0x00A40088) +#define UMAC_UMCMN_R0_IMR_S1___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_IMR_S1___POR 0x00000000 +#define UMAC_UMCMN_R0_IMR_S1__CE_WDG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S1__CE_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S1__LCMH_WCI2___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S1__LCMH_STROBE___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S1__MCIM___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S1__SMH___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S1__PMH___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S1__LMH___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S1__BMH___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S1__CE_WDG___M 0x00020000 +#define UMAC_UMCMN_R0_IMR_S1__CE_WDG___S 17 +#define UMAC_UMCMN_R0_IMR_S1__CE_ERR___M 0x00010000 +#define UMAC_UMCMN_R0_IMR_S1__CE_ERR___S 16 +#define UMAC_UMCMN_R0_IMR_S1__LCMH_WCI2___M 0x00000040 +#define UMAC_UMCMN_R0_IMR_S1__LCMH_WCI2___S 6 +#define UMAC_UMCMN_R0_IMR_S1__LCMH_STROBE___M 0x00000020 +#define UMAC_UMCMN_R0_IMR_S1__LCMH_STROBE___S 5 +#define UMAC_UMCMN_R0_IMR_S1__MCIM___M 0x00000010 +#define UMAC_UMCMN_R0_IMR_S1__MCIM___S 4 +#define UMAC_UMCMN_R0_IMR_S1__SMH___M 0x00000008 +#define UMAC_UMCMN_R0_IMR_S1__SMH___S 3 +#define UMAC_UMCMN_R0_IMR_S1__PMH___M 0x00000004 +#define UMAC_UMCMN_R0_IMR_S1__PMH___S 2 +#define UMAC_UMCMN_R0_IMR_S1__LMH___M 0x00000002 +#define UMAC_UMCMN_R0_IMR_S1__LMH___S 1 +#define UMAC_UMCMN_R0_IMR_S1__BMH___M 0x00000001 +#define UMAC_UMCMN_R0_IMR_S1__BMH___S 0 +#define UMAC_UMCMN_R0_IMR_S1___M 0x0003007F +#define UMAC_UMCMN_R0_IMR_S1___S 0 + +#define UMAC_UMCMN_R0_IMR_S2 (0x00A4008C) +#define UMAC_UMCMN_R0_IMR_S2___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_IMR_S2___POR 0x00000000 +#define UMAC_UMCMN_R0_IMR_S2__MEM_REMOTE_ACC_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S2__MEM_ACC_RANGE_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S2__MEM_NON_SEC_ACC_ERR2___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S2__MEM_NON_SEC_ACC_ERR1___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S2__MEM_REMOTE_ACC_ERR___M 0x00000008 +#define UMAC_UMCMN_R0_IMR_S2__MEM_REMOTE_ACC_ERR___S 3 +#define UMAC_UMCMN_R0_IMR_S2__MEM_ACC_RANGE_ERR___M 0x00000004 +#define UMAC_UMCMN_R0_IMR_S2__MEM_ACC_RANGE_ERR___S 2 +#define UMAC_UMCMN_R0_IMR_S2__MEM_NON_SEC_ACC_ERR2___M 0x00000002 +#define UMAC_UMCMN_R0_IMR_S2__MEM_NON_SEC_ACC_ERR2___S 1 +#define UMAC_UMCMN_R0_IMR_S2__MEM_NON_SEC_ACC_ERR1___M 0x00000001 +#define UMAC_UMCMN_R0_IMR_S2__MEM_NON_SEC_ACC_ERR1___S 0 +#define UMAC_UMCMN_R0_IMR_S2___M 0x0000000F +#define UMAC_UMCMN_R0_IMR_S2___S 0 + +#define UMAC_UMCMN_R0_IMR_S3 (0x00A40090) +#define UMAC_UMCMN_R0_IMR_S3___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_IMR_S3___POR 0x00000000 +#define UMAC_UMCMN_R0_IMR_S3__WBM_RESERVED___POR 0x00 +#define UMAC_UMCMN_R0_IMR_S3__WBM_MSDU_PARSER_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S3__WBM_LINK_IDLE_LIST_SCAT_SRNG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S3__WBM_LINK_IDLE_LIST_SCAT_SRNG_WDG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S3__WBM_BUF_IDLE_LIST_SCAT_SRNG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S3__WBM_BUF_IDLE_LIST_SCAT_SRNG_WDG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S3__WBM_MSDU_DELINK_PARSE_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S3__WBM_MSDU_DELINK_WDG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S3__WBM_LNK_IDLE_LIST_DIST_C_WDG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S3__WBM_LNK_IDLE_LIST_DIST_P_WDG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S3__WBM_BUF_IDLE_LIST_DIST_C_WDG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S3__WBM_BUF_IDLE_LIST_DIST_P_WDG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S3__WBM_FW_BUF_PROD_WDG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S3__WBM_SW3_BUF_PROD_WDG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S3__WBM_SW2_BUF_PROD_WDG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S3__WBM_SW1_BUF_PROD_WDG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S3__WBM_SW0_BUF_PROD_WDG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S3__WBM_BUF_IDLE_LIST_PROD_WDG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S3__WBM_LNK_IDLE_LIST_PROD_WDG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S3__WBM_REL_REQ_PARSER_C_WDG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S3__WBM_REL_REQ_PARSER_P_WDG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S3__WBM_RESERVED___M 0xFF000000 +#define UMAC_UMCMN_R0_IMR_S3__WBM_RESERVED___S 24 +#define UMAC_UMCMN_R0_IMR_S3__WBM_MSDU_PARSER_ERR___M 0x00380000 +#define UMAC_UMCMN_R0_IMR_S3__WBM_MSDU_PARSER_ERR___S 19 +#define UMAC_UMCMN_R0_IMR_S3__WBM_LINK_IDLE_LIST_SCAT_SRNG_ERR___M 0x00040000 +#define UMAC_UMCMN_R0_IMR_S3__WBM_LINK_IDLE_LIST_SCAT_SRNG_ERR___S 18 +#define UMAC_UMCMN_R0_IMR_S3__WBM_LINK_IDLE_LIST_SCAT_SRNG_WDG___M 0x00020000 +#define UMAC_UMCMN_R0_IMR_S3__WBM_LINK_IDLE_LIST_SCAT_SRNG_WDG___S 17 +#define UMAC_UMCMN_R0_IMR_S3__WBM_BUF_IDLE_LIST_SCAT_SRNG_ERR___M 0x00010000 +#define UMAC_UMCMN_R0_IMR_S3__WBM_BUF_IDLE_LIST_SCAT_SRNG_ERR___S 16 +#define UMAC_UMCMN_R0_IMR_S3__WBM_BUF_IDLE_LIST_SCAT_SRNG_WDG___M 0x00008000 +#define UMAC_UMCMN_R0_IMR_S3__WBM_BUF_IDLE_LIST_SCAT_SRNG_WDG___S 15 +#define UMAC_UMCMN_R0_IMR_S3__WBM_MSDU_DELINK_PARSE_ERR___M 0x00004000 +#define UMAC_UMCMN_R0_IMR_S3__WBM_MSDU_DELINK_PARSE_ERR___S 14 +#define UMAC_UMCMN_R0_IMR_S3__WBM_MSDU_DELINK_WDG___M 0x00002000 +#define UMAC_UMCMN_R0_IMR_S3__WBM_MSDU_DELINK_WDG___S 13 +#define UMAC_UMCMN_R0_IMR_S3__WBM_LNK_IDLE_LIST_DIST_C_WDG___M 0x00001000 +#define UMAC_UMCMN_R0_IMR_S3__WBM_LNK_IDLE_LIST_DIST_C_WDG___S 12 +#define UMAC_UMCMN_R0_IMR_S3__WBM_LNK_IDLE_LIST_DIST_P_WDG___M 0x00000800 +#define UMAC_UMCMN_R0_IMR_S3__WBM_LNK_IDLE_LIST_DIST_P_WDG___S 11 +#define UMAC_UMCMN_R0_IMR_S3__WBM_BUF_IDLE_LIST_DIST_C_WDG___M 0x00000400 +#define UMAC_UMCMN_R0_IMR_S3__WBM_BUF_IDLE_LIST_DIST_C_WDG___S 10 +#define UMAC_UMCMN_R0_IMR_S3__WBM_BUF_IDLE_LIST_DIST_P_WDG___M 0x00000200 +#define UMAC_UMCMN_R0_IMR_S3__WBM_BUF_IDLE_LIST_DIST_P_WDG___S 9 +#define UMAC_UMCMN_R0_IMR_S3__WBM_FW_BUF_PROD_WDG___M 0x00000100 +#define UMAC_UMCMN_R0_IMR_S3__WBM_FW_BUF_PROD_WDG___S 8 +#define UMAC_UMCMN_R0_IMR_S3__WBM_SW3_BUF_PROD_WDG___M 0x00000080 +#define UMAC_UMCMN_R0_IMR_S3__WBM_SW3_BUF_PROD_WDG___S 7 +#define UMAC_UMCMN_R0_IMR_S3__WBM_SW2_BUF_PROD_WDG___M 0x00000040 +#define UMAC_UMCMN_R0_IMR_S3__WBM_SW2_BUF_PROD_WDG___S 6 +#define UMAC_UMCMN_R0_IMR_S3__WBM_SW1_BUF_PROD_WDG___M 0x00000020 +#define UMAC_UMCMN_R0_IMR_S3__WBM_SW1_BUF_PROD_WDG___S 5 +#define UMAC_UMCMN_R0_IMR_S3__WBM_SW0_BUF_PROD_WDG___M 0x00000010 +#define UMAC_UMCMN_R0_IMR_S3__WBM_SW0_BUF_PROD_WDG___S 4 +#define UMAC_UMCMN_R0_IMR_S3__WBM_BUF_IDLE_LIST_PROD_WDG___M 0x00000008 +#define UMAC_UMCMN_R0_IMR_S3__WBM_BUF_IDLE_LIST_PROD_WDG___S 3 +#define UMAC_UMCMN_R0_IMR_S3__WBM_LNK_IDLE_LIST_PROD_WDG___M 0x00000004 +#define UMAC_UMCMN_R0_IMR_S3__WBM_LNK_IDLE_LIST_PROD_WDG___S 2 +#define UMAC_UMCMN_R0_IMR_S3__WBM_REL_REQ_PARSER_C_WDG___M 0x00000002 +#define UMAC_UMCMN_R0_IMR_S3__WBM_REL_REQ_PARSER_C_WDG___S 1 +#define UMAC_UMCMN_R0_IMR_S3__WBM_REL_REQ_PARSER_P_WDG___M 0x00000001 +#define UMAC_UMCMN_R0_IMR_S3__WBM_REL_REQ_PARSER_P_WDG___S 0 +#define UMAC_UMCMN_R0_IMR_S3___M 0xFF3FFFFF +#define UMAC_UMCMN_R0_IMR_S3___S 0 + +#define UMAC_UMCMN_R0_IMR_S4 (0x00A40094) +#define UMAC_UMCMN_R0_IMR_S4___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_IMR_S4___POR 0x00000000 +#define UMAC_UMCMN_R0_IMR_S4__WBM2SW4_RELEASE_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S4__WBM2SW3_RELEASE_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S4__WBM2SW2_RELEASE_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S4__WBM2SW1_RELEASE_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S4__WBM2SW0_RELEASE_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S4__WBM2FW_RELEASE_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S4__WBM_IDLE_LINK_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S4__WBM_IDLE_BUF_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA2_LINK_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA1_LINK_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA0_LINK_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S4__WBM2FW_LINK_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S4__WBM2SW_LINK_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S4__WBM2REO_LINK_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S4__WBM2TQM_LINK_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA2_BUF_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA1_BUF_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA0_BUF_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S4__WBM2FW_BUF_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S4__WBM2SW_BUF_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S4__WBM2PPE_BUF_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S4__RXDMA2_RELEASE_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S4__RXDMA1_RELEASE_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S4__RXDMA0_RELEASE_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S4__FW_RELEASE_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S4__SW_RELEASE_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S4__REO_RELEASE_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S4__TQM_RELEASE_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S4__PPE_RELEASE_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S4__WBM2SW4_RELEASE_RING_WDG_ERR___M 0x10000000 +#define UMAC_UMCMN_R0_IMR_S4__WBM2SW4_RELEASE_RING_WDG_ERR___S 28 +#define UMAC_UMCMN_R0_IMR_S4__WBM2SW3_RELEASE_RING_WDG_ERR___M 0x08000000 +#define UMAC_UMCMN_R0_IMR_S4__WBM2SW3_RELEASE_RING_WDG_ERR___S 27 +#define UMAC_UMCMN_R0_IMR_S4__WBM2SW2_RELEASE_RING_WDG_ERR___M 0x04000000 +#define UMAC_UMCMN_R0_IMR_S4__WBM2SW2_RELEASE_RING_WDG_ERR___S 26 +#define UMAC_UMCMN_R0_IMR_S4__WBM2SW1_RELEASE_RING_WDG_ERR___M 0x02000000 +#define UMAC_UMCMN_R0_IMR_S4__WBM2SW1_RELEASE_RING_WDG_ERR___S 25 +#define UMAC_UMCMN_R0_IMR_S4__WBM2SW0_RELEASE_RING_WDG_ERR___M 0x01000000 +#define UMAC_UMCMN_R0_IMR_S4__WBM2SW0_RELEASE_RING_WDG_ERR___S 24 +#define UMAC_UMCMN_R0_IMR_S4__WBM2FW_RELEASE_RING_WDG_ERR___M 0x00800000 +#define UMAC_UMCMN_R0_IMR_S4__WBM2FW_RELEASE_RING_WDG_ERR___S 23 +#define UMAC_UMCMN_R0_IMR_S4__WBM_IDLE_LINK_RING_WDG_ERR___M 0x00400000 +#define UMAC_UMCMN_R0_IMR_S4__WBM_IDLE_LINK_RING_WDG_ERR___S 22 +#define UMAC_UMCMN_R0_IMR_S4__WBM_IDLE_BUF_RING_WDG_ERR___M 0x00200000 +#define UMAC_UMCMN_R0_IMR_S4__WBM_IDLE_BUF_RING_WDG_ERR___S 21 +#define UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA2_LINK_RING_WDG_ERR___M 0x00100000 +#define UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA2_LINK_RING_WDG_ERR___S 20 +#define UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA1_LINK_RING_WDG_ERR___M 0x00080000 +#define UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA1_LINK_RING_WDG_ERR___S 19 +#define UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA0_LINK_RING_WDG_ERR___M 0x00040000 +#define UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA0_LINK_RING_WDG_ERR___S 18 +#define UMAC_UMCMN_R0_IMR_S4__WBM2FW_LINK_RING_WDG_ERR___M 0x00020000 +#define UMAC_UMCMN_R0_IMR_S4__WBM2FW_LINK_RING_WDG_ERR___S 17 +#define UMAC_UMCMN_R0_IMR_S4__WBM2SW_LINK_RING_WDG_ERR___M 0x00010000 +#define UMAC_UMCMN_R0_IMR_S4__WBM2SW_LINK_RING_WDG_ERR___S 16 +#define UMAC_UMCMN_R0_IMR_S4__WBM2REO_LINK_RING_WDG_ERR___M 0x00008000 +#define UMAC_UMCMN_R0_IMR_S4__WBM2REO_LINK_RING_WDG_ERR___S 15 +#define UMAC_UMCMN_R0_IMR_S4__WBM2TQM_LINK_RING_WDG_ERR___M 0x00004000 +#define UMAC_UMCMN_R0_IMR_S4__WBM2TQM_LINK_RING_WDG_ERR___S 14 +#define UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA2_BUF_RING_WDG_ERR___M 0x00002000 +#define UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA2_BUF_RING_WDG_ERR___S 13 +#define UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA1_BUF_RING_WDG_ERR___M 0x00001000 +#define UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA1_BUF_RING_WDG_ERR___S 12 +#define UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA0_BUF_RING_WDG_ERR___M 0x00000800 +#define UMAC_UMCMN_R0_IMR_S4__WBM2RXDMA0_BUF_RING_WDG_ERR___S 11 +#define UMAC_UMCMN_R0_IMR_S4__WBM2FW_BUF_RING_WDG_ERR___M 0x00000400 +#define UMAC_UMCMN_R0_IMR_S4__WBM2FW_BUF_RING_WDG_ERR___S 10 +#define UMAC_UMCMN_R0_IMR_S4__WBM2SW_BUF_RING_WDG_ERR___M 0x00000200 +#define UMAC_UMCMN_R0_IMR_S4__WBM2SW_BUF_RING_WDG_ERR___S 9 +#define UMAC_UMCMN_R0_IMR_S4__WBM2PPE_BUF_RING_WDG_ERR___M 0x00000100 +#define UMAC_UMCMN_R0_IMR_S4__WBM2PPE_BUF_RING_WDG_ERR___S 8 +#define UMAC_UMCMN_R0_IMR_S4__RXDMA2_RELEASE_RING_WDG_ERR___M 0x00000080 +#define UMAC_UMCMN_R0_IMR_S4__RXDMA2_RELEASE_RING_WDG_ERR___S 7 +#define UMAC_UMCMN_R0_IMR_S4__RXDMA1_RELEASE_RING_WDG_ERR___M 0x00000040 +#define UMAC_UMCMN_R0_IMR_S4__RXDMA1_RELEASE_RING_WDG_ERR___S 6 +#define UMAC_UMCMN_R0_IMR_S4__RXDMA0_RELEASE_RING_WDG_ERR___M 0x00000020 +#define UMAC_UMCMN_R0_IMR_S4__RXDMA0_RELEASE_RING_WDG_ERR___S 5 +#define UMAC_UMCMN_R0_IMR_S4__FW_RELEASE_RING_WDG_ERR___M 0x00000010 +#define UMAC_UMCMN_R0_IMR_S4__FW_RELEASE_RING_WDG_ERR___S 4 +#define UMAC_UMCMN_R0_IMR_S4__SW_RELEASE_RING_WDG_ERR___M 0x00000008 +#define UMAC_UMCMN_R0_IMR_S4__SW_RELEASE_RING_WDG_ERR___S 3 +#define UMAC_UMCMN_R0_IMR_S4__REO_RELEASE_RING_WDG_ERR___M 0x00000004 +#define UMAC_UMCMN_R0_IMR_S4__REO_RELEASE_RING_WDG_ERR___S 2 +#define UMAC_UMCMN_R0_IMR_S4__TQM_RELEASE_RING_WDG_ERR___M 0x00000002 +#define UMAC_UMCMN_R0_IMR_S4__TQM_RELEASE_RING_WDG_ERR___S 1 +#define UMAC_UMCMN_R0_IMR_S4__PPE_RELEASE_RING_WDG_ERR___M 0x00000001 +#define UMAC_UMCMN_R0_IMR_S4__PPE_RELEASE_RING_WDG_ERR___S 0 +#define UMAC_UMCMN_R0_IMR_S4___M 0x1FFFFFFF +#define UMAC_UMCMN_R0_IMR_S4___S 0 + +#define UMAC_UMCMN_R0_IMR_S5 (0x00A40098) +#define UMAC_UMCMN_R0_IMR_S5___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_IMR_S5___POR 0x00000000 +#define UMAC_UMCMN_R0_IMR_S5__WBM2SW4_RELEASE_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S5__WBM2SW3_RELEASE_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S5__WBM2SW2_RELEASE_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S5__WBM2SW1_RELEASE_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S5__WBM2SW0_RELEASE_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S5__WBM2FW_RELEASE_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S5__WBM_IDLE_LINK_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S5__WBM_IDLE_BUF_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA2_LINK_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA1_LINK_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA0_LINK_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S5__WBM2FW_LINK_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S5__WBM2SW_LINK_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S5__WBM2REO_LINK_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S5__WBM2TQM_LINK_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA2_BUF_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA1_BUF_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA0_BUF_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S5__WBM2FW_BUF_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S5__WBM2SW_BUF_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S5__WBM2PPE_BUF_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S5__RXDMA2_RELEASE_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S5__RXDMA1_RELEASE_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S5__RXDMA0_RELEASE_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S5__FW_RELEASE_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S5__SW_RELEASE_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S5__REO_RELEASE_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S5__TQM_RELEASE_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S5__PPE_RELEASE_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S5__WBM2SW4_RELEASE_RING_REQ_ERR___M 0x10000000 +#define UMAC_UMCMN_R0_IMR_S5__WBM2SW4_RELEASE_RING_REQ_ERR___S 28 +#define UMAC_UMCMN_R0_IMR_S5__WBM2SW3_RELEASE_RING_REQ_ERR___M 0x08000000 +#define UMAC_UMCMN_R0_IMR_S5__WBM2SW3_RELEASE_RING_REQ_ERR___S 27 +#define UMAC_UMCMN_R0_IMR_S5__WBM2SW2_RELEASE_RING_REQ_ERR___M 0x04000000 +#define UMAC_UMCMN_R0_IMR_S5__WBM2SW2_RELEASE_RING_REQ_ERR___S 26 +#define UMAC_UMCMN_R0_IMR_S5__WBM2SW1_RELEASE_RING_REQ_ERR___M 0x02000000 +#define UMAC_UMCMN_R0_IMR_S5__WBM2SW1_RELEASE_RING_REQ_ERR___S 25 +#define UMAC_UMCMN_R0_IMR_S5__WBM2SW0_RELEASE_RING_REQ_ERR___M 0x01000000 +#define UMAC_UMCMN_R0_IMR_S5__WBM2SW0_RELEASE_RING_REQ_ERR___S 24 +#define UMAC_UMCMN_R0_IMR_S5__WBM2FW_RELEASE_RING_REQ_ERR___M 0x00800000 +#define UMAC_UMCMN_R0_IMR_S5__WBM2FW_RELEASE_RING_REQ_ERR___S 23 +#define UMAC_UMCMN_R0_IMR_S5__WBM_IDLE_LINK_RING_REQ_ERR___M 0x00400000 +#define UMAC_UMCMN_R0_IMR_S5__WBM_IDLE_LINK_RING_REQ_ERR___S 22 +#define UMAC_UMCMN_R0_IMR_S5__WBM_IDLE_BUF_RING_REQ_ERR___M 0x00200000 +#define UMAC_UMCMN_R0_IMR_S5__WBM_IDLE_BUF_RING_REQ_ERR___S 21 +#define UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA2_LINK_RING_REQ_ERR___M 0x00100000 +#define UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA2_LINK_RING_REQ_ERR___S 20 +#define UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA1_LINK_RING_REQ_ERR___M 0x00080000 +#define UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA1_LINK_RING_REQ_ERR___S 19 +#define UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA0_LINK_RING_REQ_ERR___M 0x00040000 +#define UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA0_LINK_RING_REQ_ERR___S 18 +#define UMAC_UMCMN_R0_IMR_S5__WBM2FW_LINK_RING_REQ_ERR___M 0x00020000 +#define UMAC_UMCMN_R0_IMR_S5__WBM2FW_LINK_RING_REQ_ERR___S 17 +#define UMAC_UMCMN_R0_IMR_S5__WBM2SW_LINK_RING_REQ_ERR___M 0x00010000 +#define UMAC_UMCMN_R0_IMR_S5__WBM2SW_LINK_RING_REQ_ERR___S 16 +#define UMAC_UMCMN_R0_IMR_S5__WBM2REO_LINK_RING_REQ_ERR___M 0x00008000 +#define UMAC_UMCMN_R0_IMR_S5__WBM2REO_LINK_RING_REQ_ERR___S 15 +#define UMAC_UMCMN_R0_IMR_S5__WBM2TQM_LINK_RING_REQ_ERR___M 0x00004000 +#define UMAC_UMCMN_R0_IMR_S5__WBM2TQM_LINK_RING_REQ_ERR___S 14 +#define UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA2_BUF_RING_REQ_ERR___M 0x00002000 +#define UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA2_BUF_RING_REQ_ERR___S 13 +#define UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA1_BUF_RING_REQ_ERR___M 0x00001000 +#define UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA1_BUF_RING_REQ_ERR___S 12 +#define UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA0_BUF_RING_REQ_ERR___M 0x00000800 +#define UMAC_UMCMN_R0_IMR_S5__WBM2RXDMA0_BUF_RING_REQ_ERR___S 11 +#define UMAC_UMCMN_R0_IMR_S5__WBM2FW_BUF_RING_REQ_ERR___M 0x00000400 +#define UMAC_UMCMN_R0_IMR_S5__WBM2FW_BUF_RING_REQ_ERR___S 10 +#define UMAC_UMCMN_R0_IMR_S5__WBM2SW_BUF_RING_REQ_ERR___M 0x00000200 +#define UMAC_UMCMN_R0_IMR_S5__WBM2SW_BUF_RING_REQ_ERR___S 9 +#define UMAC_UMCMN_R0_IMR_S5__WBM2PPE_BUF_RING_REQ_ERR___M 0x00000100 +#define UMAC_UMCMN_R0_IMR_S5__WBM2PPE_BUF_RING_REQ_ERR___S 8 +#define UMAC_UMCMN_R0_IMR_S5__RXDMA2_RELEASE_RING_REQ_ERR___M 0x00000080 +#define UMAC_UMCMN_R0_IMR_S5__RXDMA2_RELEASE_RING_REQ_ERR___S 7 +#define UMAC_UMCMN_R0_IMR_S5__RXDMA1_RELEASE_RING_REQ_ERR___M 0x00000040 +#define UMAC_UMCMN_R0_IMR_S5__RXDMA1_RELEASE_RING_REQ_ERR___S 6 +#define UMAC_UMCMN_R0_IMR_S5__RXDMA0_RELEASE_RING_REQ_ERR___M 0x00000020 +#define UMAC_UMCMN_R0_IMR_S5__RXDMA0_RELEASE_RING_REQ_ERR___S 5 +#define UMAC_UMCMN_R0_IMR_S5__FW_RELEASE_RING_REQ_ERR___M 0x00000010 +#define UMAC_UMCMN_R0_IMR_S5__FW_RELEASE_RING_REQ_ERR___S 4 +#define UMAC_UMCMN_R0_IMR_S5__SW_RELEASE_RING_REQ_ERR___M 0x00000008 +#define UMAC_UMCMN_R0_IMR_S5__SW_RELEASE_RING_REQ_ERR___S 3 +#define UMAC_UMCMN_R0_IMR_S5__REO_RELEASE_RING_REQ_ERR___M 0x00000004 +#define UMAC_UMCMN_R0_IMR_S5__REO_RELEASE_RING_REQ_ERR___S 2 +#define UMAC_UMCMN_R0_IMR_S5__TQM_RELEASE_RING_REQ_ERR___M 0x00000002 +#define UMAC_UMCMN_R0_IMR_S5__TQM_RELEASE_RING_REQ_ERR___S 1 +#define UMAC_UMCMN_R0_IMR_S5__PPE_RELEASE_RING_REQ_ERR___M 0x00000001 +#define UMAC_UMCMN_R0_IMR_S5__PPE_RELEASE_RING_REQ_ERR___S 0 +#define UMAC_UMCMN_R0_IMR_S5___M 0x1FFFFFFF +#define UMAC_UMCMN_R0_IMR_S5___S 0 + +#define UMAC_UMCMN_R0_IMR_S6 (0x00A4009C) +#define UMAC_UMCMN_R0_IMR_S6___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_IMR_S6___POR 0x00000000 +#define UMAC_UMCMN_R0_IMR_S6__REO_STATUS_RING_WDG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S6__REO_RELEASE_RING_WDG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S6__REO2FW_RING_WDG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S6__REO2TCL_RING_WDG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S6__REO2SW6_RING_WDG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S6__REO2SW5_RING_WDG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S6__REO2SW4_RING_WDG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S6__REO2SW3_RING_WDG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S6__REO2SW2_RING_WDG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S6__REO2SW1_RING_WDG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S6__SW2REO_RING_WDG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S6__REO_CMD_RING_WDG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S6__WBM2REO_LINK_RING_WDG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S6__RXDMA2REO2_RING_WDG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S6__RXDMA2REO1_RING_WDG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S6__RXDMA2REO0_RING_WDG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S6__REO_STATUS_RING_WDG___M 0x00008000 +#define UMAC_UMCMN_R0_IMR_S6__REO_STATUS_RING_WDG___S 15 +#define UMAC_UMCMN_R0_IMR_S6__REO_RELEASE_RING_WDG___M 0x00004000 +#define UMAC_UMCMN_R0_IMR_S6__REO_RELEASE_RING_WDG___S 14 +#define UMAC_UMCMN_R0_IMR_S6__REO2FW_RING_WDG___M 0x00002000 +#define UMAC_UMCMN_R0_IMR_S6__REO2FW_RING_WDG___S 13 +#define UMAC_UMCMN_R0_IMR_S6__REO2TCL_RING_WDG___M 0x00001000 +#define UMAC_UMCMN_R0_IMR_S6__REO2TCL_RING_WDG___S 12 +#define UMAC_UMCMN_R0_IMR_S6__REO2SW6_RING_WDG___M 0x00000800 +#define UMAC_UMCMN_R0_IMR_S6__REO2SW6_RING_WDG___S 11 +#define UMAC_UMCMN_R0_IMR_S6__REO2SW5_RING_WDG___M 0x00000400 +#define UMAC_UMCMN_R0_IMR_S6__REO2SW5_RING_WDG___S 10 +#define UMAC_UMCMN_R0_IMR_S6__REO2SW4_RING_WDG___M 0x00000200 +#define UMAC_UMCMN_R0_IMR_S6__REO2SW4_RING_WDG___S 9 +#define UMAC_UMCMN_R0_IMR_S6__REO2SW3_RING_WDG___M 0x00000100 +#define UMAC_UMCMN_R0_IMR_S6__REO2SW3_RING_WDG___S 8 +#define UMAC_UMCMN_R0_IMR_S6__REO2SW2_RING_WDG___M 0x00000080 +#define UMAC_UMCMN_R0_IMR_S6__REO2SW2_RING_WDG___S 7 +#define UMAC_UMCMN_R0_IMR_S6__REO2SW1_RING_WDG___M 0x00000040 +#define UMAC_UMCMN_R0_IMR_S6__REO2SW1_RING_WDG___S 6 +#define UMAC_UMCMN_R0_IMR_S6__SW2REO_RING_WDG___M 0x00000020 +#define UMAC_UMCMN_R0_IMR_S6__SW2REO_RING_WDG___S 5 +#define UMAC_UMCMN_R0_IMR_S6__REO_CMD_RING_WDG___M 0x00000010 +#define UMAC_UMCMN_R0_IMR_S6__REO_CMD_RING_WDG___S 4 +#define UMAC_UMCMN_R0_IMR_S6__WBM2REO_LINK_RING_WDG___M 0x00000008 +#define UMAC_UMCMN_R0_IMR_S6__WBM2REO_LINK_RING_WDG___S 3 +#define UMAC_UMCMN_R0_IMR_S6__RXDMA2REO2_RING_WDG___M 0x00000004 +#define UMAC_UMCMN_R0_IMR_S6__RXDMA2REO2_RING_WDG___S 2 +#define UMAC_UMCMN_R0_IMR_S6__RXDMA2REO1_RING_WDG___M 0x00000002 +#define UMAC_UMCMN_R0_IMR_S6__RXDMA2REO1_RING_WDG___S 1 +#define UMAC_UMCMN_R0_IMR_S6__RXDMA2REO0_RING_WDG___M 0x00000001 +#define UMAC_UMCMN_R0_IMR_S6__RXDMA2REO0_RING_WDG___S 0 +#define UMAC_UMCMN_R0_IMR_S6___M 0x0000FFFF +#define UMAC_UMCMN_R0_IMR_S6___S 0 + +#define UMAC_UMCMN_R0_IMR_S7 (0x00A400A0) +#define UMAC_UMCMN_R0_IMR_S7___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_IMR_S7___POR 0x00000000 +#define UMAC_UMCMN_R0_IMR_S7__REO_CACHE_INT___POR 0x0000 +#define UMAC_UMCMN_R0_IMR_S7__REO_AC_BUF_OVER_THRESH___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S7__REO_CACHE_INT___M 0xFFFF0000 +#define UMAC_UMCMN_R0_IMR_S7__REO_CACHE_INT___S 16 +#define UMAC_UMCMN_R0_IMR_S7__REO_AC_BUF_OVER_THRESH___M 0x0000000F +#define UMAC_UMCMN_R0_IMR_S7__REO_AC_BUF_OVER_THRESH___S 0 +#define UMAC_UMCMN_R0_IMR_S7___M 0xFFFF000F +#define UMAC_UMCMN_R0_IMR_S7___S 0 + +#define UMAC_UMCMN_R0_IMR_S8 (0x00A400A4) +#define UMAC_UMCMN_R0_IMR_S8___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_IMR_S8___POR 0x00000000 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_RESERVED___POR 0x000 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_INVALID_TLV_CMD___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_RX_QUEUE_NUM_MISMATCH___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_REORDER_SW_ZERO_DESC___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_REORDER_AGE_ZERO_DESC___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_REORDER_ZERO_MSDU_LINK_PTR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_REORDER_ZERO_MPDU_LINK_PTR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_SEQ_ZERO_MSDU_BUF_PTR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_BA_NON_AMPDU___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_SEQ_PN_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_BAR_SNEQUAL___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_BAR_NONBA___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_OOR_BAR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_OOR_REG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_2K_BAR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_2K_REG___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_BA_DD___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_NONBA_DD___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_AMPDU_NONBA___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_QD_NOTVALID___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_REORDER_QD_ADDR_ZERO___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_RESERVED___M 0xFFF00000 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_RESERVED___S 20 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_INVALID_TLV_CMD___M 0x00080000 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_INVALID_TLV_CMD___S 19 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_RX_QUEUE_NUM_MISMATCH___M 0x00040000 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_RX_QUEUE_NUM_MISMATCH___S 18 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_REORDER_SW_ZERO_DESC___M 0x00020000 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_REORDER_SW_ZERO_DESC___S 17 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_REORDER_AGE_ZERO_DESC___M 0x00010000 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_REORDER_AGE_ZERO_DESC___S 16 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_REORDER_ZERO_MSDU_LINK_PTR___M 0x00008000 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_REORDER_ZERO_MSDU_LINK_PTR___S 15 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_REORDER_ZERO_MPDU_LINK_PTR___M 0x00004000 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_REORDER_ZERO_MPDU_LINK_PTR___S 14 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_SEQ_ZERO_MSDU_BUF_PTR___M 0x00002000 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_SEQ_ZERO_MSDU_BUF_PTR___S 13 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_BA_NON_AMPDU___M 0x00001000 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_BA_NON_AMPDU___S 12 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_SEQ_PN_ERR___M 0x00000800 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_SEQ_PN_ERR___S 11 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_BAR_SNEQUAL___M 0x00000400 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_BAR_SNEQUAL___S 10 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_BAR_NONBA___M 0x00000200 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_BAR_NONBA___S 9 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_OOR_BAR___M 0x00000100 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_OOR_BAR___S 8 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_OOR_REG___M 0x00000080 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_OOR_REG___S 7 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_2K_BAR___M 0x00000040 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_2K_BAR___S 6 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_2K_REG___M 0x00000020 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_2K_REG___S 5 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_BA_DD___M 0x00000010 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_BA_DD___S 4 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_NONBA_DD___M 0x00000008 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_NONBA_DD___S 3 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_AMPDU_NONBA___M 0x00000004 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_AMPDU_NONBA___S 2 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_QD_NOTVALID___M 0x00000002 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_DD_QD_NOTVALID___S 1 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_REORDER_QD_ADDR_ZERO___M 0x00000001 +#define UMAC_UMCMN_R0_IMR_S8__REO_ERR_INTR_REORDER_QD_ADDR_ZERO___S 0 +#define UMAC_UMCMN_R0_IMR_S8___M 0xFFFFFFFF +#define UMAC_UMCMN_R0_IMR_S8___S 0 + +#define UMAC_UMCMN_R0_IMR_S9 (0x00A400A8) +#define UMAC_UMCMN_R0_IMR_S9___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_IMR_S9___POR 0x00000000 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR___POR 0x000 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_STATUS_PROD___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_RELEASE_PROD___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_WIFI_PROD___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_TCL_PROD___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_HOST3_PROD___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_HOST2_PROD___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_HOST1_PROD___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_HOST0_PROD___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_SEQUENCER___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_REORDER___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_MPDU_LINK_PREFETCH___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_REO_CMD_TLV___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_REO_CMD_PREFETCH___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_REO_RING_PREFETCH___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_REO_RING_PREFETCH_READ___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR___M 0x00FF8000 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR___S 15 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_STATUS_PROD___M 0x00004000 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_STATUS_PROD___S 14 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_RELEASE_PROD___M 0x00002000 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_RELEASE_PROD___S 13 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_WIFI_PROD___M 0x00001000 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_WIFI_PROD___S 12 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_TCL_PROD___M 0x00000800 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_TCL_PROD___S 11 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_HOST3_PROD___M 0x00000400 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_HOST3_PROD___S 10 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_HOST2_PROD___M 0x00000200 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_HOST2_PROD___S 9 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_HOST1_PROD___M 0x00000100 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_HOST1_PROD___S 8 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_HOST0_PROD___M 0x00000080 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_HOST0_PROD___S 7 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_SEQUENCER___M 0x00000040 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_SEQUENCER___S 6 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_REORDER___M 0x00000020 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_REORDER___S 5 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_MPDU_LINK_PREFETCH___M 0x00000010 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_MPDU_LINK_PREFETCH___S 4 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_REO_CMD_TLV___M 0x00000008 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_REO_CMD_TLV___S 3 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_REO_CMD_PREFETCH___M 0x00000004 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_REO_CMD_PREFETCH___S 2 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_REO_RING_PREFETCH___M 0x00000002 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_REO_RING_PREFETCH___S 1 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_REO_RING_PREFETCH_READ___M 0x00000001 +#define UMAC_UMCMN_R0_IMR_S9__REO_RESERVED_WDG_ERR_REO_RING_PREFETCH_READ___S 0 +#define UMAC_UMCMN_R0_IMR_S9___M 0x00FFFFFF +#define UMAC_UMCMN_R0_IMR_S9___S 0 + +#define UMAC_UMCMN_R0_IMR_S10 (0x00A400AC) +#define UMAC_UMCMN_R0_IMR_S10___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_IMR_S10___POR 0x00000000 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG7_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG6_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG5_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG4_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG3_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG2_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG1_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG0_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_REO_CMD_SRNG_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_LINK_DESC_SRNG_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_ENTR_SRNG3_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_ENTR_SRNG2_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_ENTR_SRNG1_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_ENTR_SRNG0_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT___M 0x0000C000 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT___S 14 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG7_REQ_ERR___M 0x00002000 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG7_REQ_ERR___S 13 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG6_REQ_ERR___M 0x00001000 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG6_REQ_ERR___S 12 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG5_REQ_ERR___M 0x00000800 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG5_REQ_ERR___S 11 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG4_REQ_ERR___M 0x00000400 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG4_REQ_ERR___S 10 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG3_REQ_ERR___M 0x00000200 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG3_REQ_ERR___S 9 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG2_REQ_ERR___M 0x00000100 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG2_REQ_ERR___S 8 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG1_REQ_ERR___M 0x00000080 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG1_REQ_ERR___S 7 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG0_REQ_ERR___M 0x00000040 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_HOST_SRNG0_REQ_ERR___S 6 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_REO_CMD_SRNG_REQ_ERR___M 0x00000020 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_REO_CMD_SRNG_REQ_ERR___S 5 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_LINK_DESC_SRNG_REQ_ERR___M 0x00000010 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_LINK_DESC_SRNG_REQ_ERR___S 4 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_ENTR_SRNG3_REQ_ERR___M 0x00000008 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_ENTR_SRNG3_REQ_ERR___S 3 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_ENTR_SRNG2_REQ_ERR___M 0x00000004 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_ENTR_SRNG2_REQ_ERR___S 2 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_ENTR_SRNG1_REQ_ERR___M 0x00000002 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_ENTR_SRNG1_REQ_ERR___S 1 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_ENTR_SRNG0_REQ_ERR___M 0x00000001 +#define UMAC_UMCMN_R0_IMR_S10__REO_RESERVED_INT_ENTR_SRNG0_REQ_ERR___S 0 +#define UMAC_UMCMN_R0_IMR_S10___M 0x0000FFFF +#define UMAC_UMCMN_R0_IMR_S10___S 0 + +#define UMAC_UMCMN_R0_IMR_S11 (0x00A400B0) +#define UMAC_UMCMN_R0_IMR_S11___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_IMR_S11___POR 0x00000000 +#define UMAC_UMCMN_R0_IMR_S11__TCL_STATUS2_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S11__TCL_STATUS2_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S11__TCL_STATUS1_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S11__TCL_STATUS1_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S11__TCL_TCL2FW_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S11__TCL_TCL2FW_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S11__TCL_TCL2TQM_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S11__TCL_TCL2TQM_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL_CREDIT_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL_CREDIT_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S11__TCL_FW2TCL1_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S11__TCL_FW2TCL1_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL3_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL3_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL2_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL2_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL1_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL1_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S11__TCL_STATUS2_RING_WDG_ERR___M 0x00020000 +#define UMAC_UMCMN_R0_IMR_S11__TCL_STATUS2_RING_WDG_ERR___S 17 +#define UMAC_UMCMN_R0_IMR_S11__TCL_STATUS2_RING_REQ_ERR___M 0x00010000 +#define UMAC_UMCMN_R0_IMR_S11__TCL_STATUS2_RING_REQ_ERR___S 16 +#define UMAC_UMCMN_R0_IMR_S11__TCL_STATUS1_RING_WDG_ERR___M 0x00008000 +#define UMAC_UMCMN_R0_IMR_S11__TCL_STATUS1_RING_WDG_ERR___S 15 +#define UMAC_UMCMN_R0_IMR_S11__TCL_STATUS1_RING_REQ_ERR___M 0x00004000 +#define UMAC_UMCMN_R0_IMR_S11__TCL_STATUS1_RING_REQ_ERR___S 14 +#define UMAC_UMCMN_R0_IMR_S11__TCL_TCL2FW_RING_WDG_ERR___M 0x00002000 +#define UMAC_UMCMN_R0_IMR_S11__TCL_TCL2FW_RING_WDG_ERR___S 13 +#define UMAC_UMCMN_R0_IMR_S11__TCL_TCL2FW_RING_REQ_ERR___M 0x00001000 +#define UMAC_UMCMN_R0_IMR_S11__TCL_TCL2FW_RING_REQ_ERR___S 12 +#define UMAC_UMCMN_R0_IMR_S11__TCL_TCL2TQM_RING_WDG_ERR___M 0x00000800 +#define UMAC_UMCMN_R0_IMR_S11__TCL_TCL2TQM_RING_WDG_ERR___S 11 +#define UMAC_UMCMN_R0_IMR_S11__TCL_TCL2TQM_RING_REQ_ERR___M 0x00000400 +#define UMAC_UMCMN_R0_IMR_S11__TCL_TCL2TQM_RING_REQ_ERR___S 10 +#define UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL_CREDIT_RING_WDG_ERR___M 0x00000200 +#define UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL_CREDIT_RING_WDG_ERR___S 9 +#define UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL_CREDIT_RING_REQ_ERR___M 0x00000100 +#define UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL_CREDIT_RING_REQ_ERR___S 8 +#define UMAC_UMCMN_R0_IMR_S11__TCL_FW2TCL1_RING_WDG_ERR___M 0x00000080 +#define UMAC_UMCMN_R0_IMR_S11__TCL_FW2TCL1_RING_WDG_ERR___S 7 +#define UMAC_UMCMN_R0_IMR_S11__TCL_FW2TCL1_RING_REQ_ERR___M 0x00000040 +#define UMAC_UMCMN_R0_IMR_S11__TCL_FW2TCL1_RING_REQ_ERR___S 6 +#define UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL3_RING_WDG_ERR___M 0x00000020 +#define UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL3_RING_WDG_ERR___S 5 +#define UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL3_RING_REQ_ERR___M 0x00000010 +#define UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL3_RING_REQ_ERR___S 4 +#define UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL2_RING_WDG_ERR___M 0x00000008 +#define UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL2_RING_WDG_ERR___S 3 +#define UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL2_RING_REQ_ERR___M 0x00000004 +#define UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL2_RING_REQ_ERR___S 2 +#define UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL1_RING_WDG_ERR___M 0x00000002 +#define UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL1_RING_WDG_ERR___S 1 +#define UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL1_RING_REQ_ERR___M 0x00000001 +#define UMAC_UMCMN_R0_IMR_S11__TCL_SW2TCL1_RING_REQ_ERR___S 0 +#define UMAC_UMCMN_R0_IMR_S11___M 0x0003FFFF +#define UMAC_UMCMN_R0_IMR_S11___S 0 + +#define UMAC_UMCMN_R0_IMR_S12 (0x00A400B4) +#define UMAC_UMCMN_R0_IMR_S12___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_IMR_S12___POR 0x00000000 +#define UMAC_UMCMN_R0_IMR_S12__TCL_CCE_ERR_CLASSIFY_DIS___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S12__TCL_CCE_WDG_TO___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_IPV6_JUMBOGRAM___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_IPV6_EXT_HD_BYTES_EXCEED___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_MSDU_LEN_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_ETH_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_WMAC_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_WDG_TO___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S12__TCL_SW2TCL_CREDIT_ZERO_LEN_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S12__TCL_FW2TCL1_ZERO_LEN_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S12__TCL_SW2TCL3_ZERO_LEN_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S12__TCL_SW2TCL2_ZERO_LEN_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S12__TCL_SW2TCL1_ZERO_LEN_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S12__TCL_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S12__TCL_CCE_ERR_CLASSIFY_DIS___M 0x00002000 +#define UMAC_UMCMN_R0_IMR_S12__TCL_CCE_ERR_CLASSIFY_DIS___S 13 +#define UMAC_UMCMN_R0_IMR_S12__TCL_CCE_WDG_TO___M 0x00001000 +#define UMAC_UMCMN_R0_IMR_S12__TCL_CCE_WDG_TO___S 12 +#define UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_IPV6_JUMBOGRAM___M 0x00000800 +#define UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_IPV6_JUMBOGRAM___S 11 +#define UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_IPV6_EXT_HD_BYTES_EXCEED___M 0x00000400 +#define UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_IPV6_EXT_HD_BYTES_EXCEED___S 10 +#define UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_MSDU_LEN_ERR___M 0x00000200 +#define UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_MSDU_LEN_ERR___S 9 +#define UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_ETH_ERR___M 0x00000100 +#define UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_ETH_ERR___S 8 +#define UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_WMAC_ERR___M 0x00000080 +#define UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_WMAC_ERR___S 7 +#define UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_WDG_TO___M 0x00000040 +#define UMAC_UMCMN_R0_IMR_S12__TCL_CMN_PRSR_WDG_TO___S 6 +#define UMAC_UMCMN_R0_IMR_S12__TCL_SW2TCL_CREDIT_ZERO_LEN_ERR___M 0x00000020 +#define UMAC_UMCMN_R0_IMR_S12__TCL_SW2TCL_CREDIT_ZERO_LEN_ERR___S 5 +#define UMAC_UMCMN_R0_IMR_S12__TCL_FW2TCL1_ZERO_LEN_ERR___M 0x00000010 +#define UMAC_UMCMN_R0_IMR_S12__TCL_FW2TCL1_ZERO_LEN_ERR___S 4 +#define UMAC_UMCMN_R0_IMR_S12__TCL_SW2TCL3_ZERO_LEN_ERR___M 0x00000008 +#define UMAC_UMCMN_R0_IMR_S12__TCL_SW2TCL3_ZERO_LEN_ERR___S 3 +#define UMAC_UMCMN_R0_IMR_S12__TCL_SW2TCL2_ZERO_LEN_ERR___M 0x00000004 +#define UMAC_UMCMN_R0_IMR_S12__TCL_SW2TCL2_ZERO_LEN_ERR___S 2 +#define UMAC_UMCMN_R0_IMR_S12__TCL_SW2TCL1_ZERO_LEN_ERR___M 0x00000002 +#define UMAC_UMCMN_R0_IMR_S12__TCL_SW2TCL1_ZERO_LEN_ERR___S 1 +#define UMAC_UMCMN_R0_IMR_S12__TCL_WDG_ERR___M 0x00000001 +#define UMAC_UMCMN_R0_IMR_S12__TCL_WDG_ERR___S 0 +#define UMAC_UMCMN_R0_IMR_S12___M 0x00003FFF +#define UMAC_UMCMN_R0_IMR_S12___S 0 + +#define UMAC_UMCMN_R0_IMR_S13 (0x00A400B8) +#define UMAC_UMCMN_R0_IMR_S13___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_IMR_S13___POR 0x00000000 +#define UMAC_UMCMN_R0_IMR_S13__TQM_DESC_PTR_RELEASE_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S13__TQM_DESC_PTR_RELEASE_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S13__TQM_STATUS1_UPDATE_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S13__TQM_STATUS1_UPDATE_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S13__TQM_STATUS_UPDATE_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S13__TQM_STATUS_UPDATE_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S13__TQM_DESC_PTR_FETCH_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S13__TQM_DESC_PTR_FETCH_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD3_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD3_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD2_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD2_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD1_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD1_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S13__TQM_SW_CMD_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S13__TQM_SW_CMD_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT3_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT3_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT2_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT2_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT1_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT1_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S13__TQM_DESC_PTR_RELEASE_RING_REQ_ERR___M 0x00200000 +#define UMAC_UMCMN_R0_IMR_S13__TQM_DESC_PTR_RELEASE_RING_REQ_ERR___S 21 +#define UMAC_UMCMN_R0_IMR_S13__TQM_DESC_PTR_RELEASE_RING_WDG_ERR___M 0x00100000 +#define UMAC_UMCMN_R0_IMR_S13__TQM_DESC_PTR_RELEASE_RING_WDG_ERR___S 20 +#define UMAC_UMCMN_R0_IMR_S13__TQM_STATUS1_UPDATE_RING_REQ_ERR___M 0x00080000 +#define UMAC_UMCMN_R0_IMR_S13__TQM_STATUS1_UPDATE_RING_REQ_ERR___S 19 +#define UMAC_UMCMN_R0_IMR_S13__TQM_STATUS1_UPDATE_RING_WDG_ERR___M 0x00040000 +#define UMAC_UMCMN_R0_IMR_S13__TQM_STATUS1_UPDATE_RING_WDG_ERR___S 18 +#define UMAC_UMCMN_R0_IMR_S13__TQM_STATUS_UPDATE_RING_REQ_ERR___M 0x00020000 +#define UMAC_UMCMN_R0_IMR_S13__TQM_STATUS_UPDATE_RING_REQ_ERR___S 17 +#define UMAC_UMCMN_R0_IMR_S13__TQM_STATUS_UPDATE_RING_WDG_ERR___M 0x00010000 +#define UMAC_UMCMN_R0_IMR_S13__TQM_STATUS_UPDATE_RING_WDG_ERR___S 16 +#define UMAC_UMCMN_R0_IMR_S13__TQM_DESC_PTR_FETCH_RING_REQ_ERR___M 0x00008000 +#define UMAC_UMCMN_R0_IMR_S13__TQM_DESC_PTR_FETCH_RING_REQ_ERR___S 15 +#define UMAC_UMCMN_R0_IMR_S13__TQM_DESC_PTR_FETCH_RING_WDG_ERR___M 0x00004000 +#define UMAC_UMCMN_R0_IMR_S13__TQM_DESC_PTR_FETCH_RING_WDG_ERR___S 14 +#define UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD3_RING_REQ_ERR___M 0x00002000 +#define UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD3_RING_REQ_ERR___S 13 +#define UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD3_RING_WDG_ERR___M 0x00001000 +#define UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD3_RING_WDG_ERR___S 12 +#define UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD2_RING_REQ_ERR___M 0x00000800 +#define UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD2_RING_REQ_ERR___S 11 +#define UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD2_RING_WDG_ERR___M 0x00000400 +#define UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD2_RING_WDG_ERR___S 10 +#define UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD1_RING_REQ_ERR___M 0x00000200 +#define UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD1_RING_REQ_ERR___S 9 +#define UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD1_RING_WDG_ERR___M 0x00000100 +#define UMAC_UMCMN_R0_IMR_S13__TQM_HWSCH_CMD1_RING_WDG_ERR___S 8 +#define UMAC_UMCMN_R0_IMR_S13__TQM_SW_CMD_RING_REQ_ERR___M 0x00000080 +#define UMAC_UMCMN_R0_IMR_S13__TQM_SW_CMD_RING_REQ_ERR___S 7 +#define UMAC_UMCMN_R0_IMR_S13__TQM_SW_CMD_RING_WDG_ERR___M 0x00000040 +#define UMAC_UMCMN_R0_IMR_S13__TQM_SW_CMD_RING_WDG_ERR___S 6 +#define UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT3_RING_REQ_ERR___M 0x00000020 +#define UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT3_RING_REQ_ERR___S 5 +#define UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT3_RING_WDG_ERR___M 0x00000010 +#define UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT3_RING_WDG_ERR___S 4 +#define UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT2_RING_REQ_ERR___M 0x00000008 +#define UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT2_RING_REQ_ERR___S 3 +#define UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT2_RING_WDG_ERR___M 0x00000004 +#define UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT2_RING_WDG_ERR___S 2 +#define UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT1_RING_REQ_ERR___M 0x00000002 +#define UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT1_RING_REQ_ERR___S 1 +#define UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT1_RING_WDG_ERR___M 0x00000001 +#define UMAC_UMCMN_R0_IMR_S13__TQM_MSDU_ENT1_RING_WDG_ERR___S 0 +#define UMAC_UMCMN_R0_IMR_S13___M 0x003FFFFF +#define UMAC_UMCMN_R0_IMR_S13___S 0 + +#define UMAC_UMCMN_R0_IMR_S14 (0x00A400BC) +#define UMAC_UMCMN_R0_IMR_S14___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_IMR_S14___POR 0x00000000 +#define UMAC_UMCMN_R0_IMR_S14__TQM_CACHE_CTL_ERR___POR 0x000 +#define UMAC_UMCMN_R0_IMR_S14__TQM_WDG_TIMEOUT___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S14__TQM_SW_PRGM_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S14__TQM_CMD_SM_ERR___POR 0x00 +#define UMAC_UMCMN_R0_IMR_S14__TQM_CACHE_CTL_ERR___M 0x0FFF0000 +#define UMAC_UMCMN_R0_IMR_S14__TQM_CACHE_CTL_ERR___S 16 +#define UMAC_UMCMN_R0_IMR_S14__TQM_WDG_TIMEOUT___M 0x00000800 +#define UMAC_UMCMN_R0_IMR_S14__TQM_WDG_TIMEOUT___S 11 +#define UMAC_UMCMN_R0_IMR_S14__TQM_SW_PRGM_ERR___M 0x00000400 +#define UMAC_UMCMN_R0_IMR_S14__TQM_SW_PRGM_ERR___S 10 +#define UMAC_UMCMN_R0_IMR_S14__TQM_CMD_SM_ERR___M 0x000000FF +#define UMAC_UMCMN_R0_IMR_S14__TQM_CMD_SM_ERR___S 0 +#define UMAC_UMCMN_R0_IMR_S14___M 0x0FFF0CFF +#define UMAC_UMCMN_R0_IMR_S14___S 0 + +#define UMAC_UMCMN_R0_IMR_S15 (0x00A400C0) +#define UMAC_UMCMN_R0_IMR_S15___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_IMR_S15___POR 0x00000000 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_QUEUE_HEAD_MAC0___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_UNPAUSE_LINK_DESC_THRESHOLD___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_ILLEGAL_HWSCH_CMD___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_ILLEGAL_SW_CMD___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT2_DEC_EMPTY___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT1_DEC_EMPTY___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT0_DEC_EMPTY___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT2_SATURATE___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT1_SATURATE___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT0_SATURATE___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD2_REACHED___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD1_REACHED___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD0_REACHED___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_AGGR_LINK_DESC_THRESHOLD_REACHED___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_SW_CMD1_RING_REQ_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_SW_CMD1_RING_WDG_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_SW_CMD1_RING_SW_INT___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_QUEUE_HEAD_MAC0___M 0x00010000 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_QUEUE_HEAD_MAC0___S 16 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_UNPAUSE_LINK_DESC_THRESHOLD___M 0x00008000 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_UNPAUSE_LINK_DESC_THRESHOLD___S 15 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_ILLEGAL_HWSCH_CMD___M 0x00004000 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_ILLEGAL_HWSCH_CMD___S 14 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_ILLEGAL_SW_CMD___M 0x00002000 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_ILLEGAL_SW_CMD___S 13 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT2_DEC_EMPTY___M 0x00001000 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT2_DEC_EMPTY___S 12 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT1_DEC_EMPTY___M 0x00000800 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT1_DEC_EMPTY___S 11 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT0_DEC_EMPTY___M 0x00000400 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT0_DEC_EMPTY___S 10 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT2_SATURATE___M 0x00000200 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT2_SATURATE___S 9 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT1_SATURATE___M 0x00000100 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT1_SATURATE___S 8 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT0_SATURATE___M 0x00000080 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_CNT0_SATURATE___S 7 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD2_REACHED___M 0x00000040 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD2_REACHED___S 6 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD1_REACHED___M 0x00000020 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD1_REACHED___S 5 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD0_REACHED___M 0x00000010 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_LINK_DESC_THRESHOLD0_REACHED___S 4 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_AGGR_LINK_DESC_THRESHOLD_REACHED___M 0x00000008 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_AGGR_LINK_DESC_THRESHOLD_REACHED___S 3 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_SW_CMD1_RING_REQ_ERR___M 0x00000004 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_SW_CMD1_RING_REQ_ERR___S 2 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_SW_CMD1_RING_WDG_ERR___M 0x00000002 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_SW_CMD1_RING_WDG_ERR___S 1 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_SW_CMD1_RING_SW_INT___M 0x00000001 +#define UMAC_UMCMN_R0_IMR_S15__TQM_RESERVED_SW_CMD1_RING_SW_INT___S 0 +#define UMAC_UMCMN_R0_IMR_S15___M 0x0001FFFF +#define UMAC_UMCMN_R0_IMR_S15___S 0 + +#define UMAC_UMCMN_R0_IMR_S16 (0x00A400C4) +#define UMAC_UMCMN_R0_IMR_S16___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_IMR_S16___POR 0x00000000 +#define UMAC_UMCMN_R0_IMR_S16__REO_GXI_INTR___POR 0x0000 +#define UMAC_UMCMN_R0_IMR_S16__CE_GXI_AXI_WR_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S16__CE_GXI_AXI_RD_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S16__CE_GXI_LAST_WR_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S16__CE_GXI_WDTO___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S16__TQM_GXI_AXI_WR_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S16__TQM_GXI_AXI_RD_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S16__TQM_GXI_LAST_WR_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S16__TQM_GXI_WDTO___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S16__TCL_GXI_AXI_WR_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S16__TCL_GXI_AXI_RD_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S16__TCL_GXI_LAST_WR_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S16__TCL_GXI_WDTO___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S16__WBM_GXI_AXI_WR_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S16__WBM_GXI_AXI_RD_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S16__WBM_GXI_LAST_WR_ERR___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S16__WBM_GXI_WDTO___POR 0x0 +#define UMAC_UMCMN_R0_IMR_S16__REO_GXI_INTR___M 0xFFFF0000 +#define UMAC_UMCMN_R0_IMR_S16__REO_GXI_INTR___S 16 +#define UMAC_UMCMN_R0_IMR_S16__CE_GXI_AXI_WR_ERR___M 0x00008000 +#define UMAC_UMCMN_R0_IMR_S16__CE_GXI_AXI_WR_ERR___S 15 +#define UMAC_UMCMN_R0_IMR_S16__CE_GXI_AXI_RD_ERR___M 0x00004000 +#define UMAC_UMCMN_R0_IMR_S16__CE_GXI_AXI_RD_ERR___S 14 +#define UMAC_UMCMN_R0_IMR_S16__CE_GXI_LAST_WR_ERR___M 0x00002000 +#define UMAC_UMCMN_R0_IMR_S16__CE_GXI_LAST_WR_ERR___S 13 +#define UMAC_UMCMN_R0_IMR_S16__CE_GXI_WDTO___M 0x00001000 +#define UMAC_UMCMN_R0_IMR_S16__CE_GXI_WDTO___S 12 +#define UMAC_UMCMN_R0_IMR_S16__TQM_GXI_AXI_WR_ERR___M 0x00000800 +#define UMAC_UMCMN_R0_IMR_S16__TQM_GXI_AXI_WR_ERR___S 11 +#define UMAC_UMCMN_R0_IMR_S16__TQM_GXI_AXI_RD_ERR___M 0x00000400 +#define UMAC_UMCMN_R0_IMR_S16__TQM_GXI_AXI_RD_ERR___S 10 +#define UMAC_UMCMN_R0_IMR_S16__TQM_GXI_LAST_WR_ERR___M 0x00000200 +#define UMAC_UMCMN_R0_IMR_S16__TQM_GXI_LAST_WR_ERR___S 9 +#define UMAC_UMCMN_R0_IMR_S16__TQM_GXI_WDTO___M 0x00000100 +#define UMAC_UMCMN_R0_IMR_S16__TQM_GXI_WDTO___S 8 +#define UMAC_UMCMN_R0_IMR_S16__TCL_GXI_AXI_WR_ERR___M 0x00000080 +#define UMAC_UMCMN_R0_IMR_S16__TCL_GXI_AXI_WR_ERR___S 7 +#define UMAC_UMCMN_R0_IMR_S16__TCL_GXI_AXI_RD_ERR___M 0x00000040 +#define UMAC_UMCMN_R0_IMR_S16__TCL_GXI_AXI_RD_ERR___S 6 +#define UMAC_UMCMN_R0_IMR_S16__TCL_GXI_LAST_WR_ERR___M 0x00000020 +#define UMAC_UMCMN_R0_IMR_S16__TCL_GXI_LAST_WR_ERR___S 5 +#define UMAC_UMCMN_R0_IMR_S16__TCL_GXI_WDTO___M 0x00000010 +#define UMAC_UMCMN_R0_IMR_S16__TCL_GXI_WDTO___S 4 +#define UMAC_UMCMN_R0_IMR_S16__WBM_GXI_AXI_WR_ERR___M 0x00000008 +#define UMAC_UMCMN_R0_IMR_S16__WBM_GXI_AXI_WR_ERR___S 3 +#define UMAC_UMCMN_R0_IMR_S16__WBM_GXI_AXI_RD_ERR___M 0x00000004 +#define UMAC_UMCMN_R0_IMR_S16__WBM_GXI_AXI_RD_ERR___S 2 +#define UMAC_UMCMN_R0_IMR_S16__WBM_GXI_LAST_WR_ERR___M 0x00000002 +#define UMAC_UMCMN_R0_IMR_S16__WBM_GXI_LAST_WR_ERR___S 1 +#define UMAC_UMCMN_R0_IMR_S16__WBM_GXI_WDTO___M 0x00000001 +#define UMAC_UMCMN_R0_IMR_S16__WBM_GXI_WDTO___S 0 +#define UMAC_UMCMN_R0_IMR_S16___M 0xFFFFFFFF +#define UMAC_UMCMN_R0_IMR_S16___S 0 + +#define UMAC_UMCMN_R0_WOCLR_ISR_P_EN (0x00A400C8) +#define UMAC_UMCMN_R0_WOCLR_ISR_P_EN___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_WOCLR_ISR_P_EN___POR 0x00000000 +#define UMAC_UMCMN_R0_WOCLR_ISR_P_EN__VAL___POR 0x0 +#define UMAC_UMCMN_R0_WOCLR_ISR_P_EN__VAL___M 0x00000001 +#define UMAC_UMCMN_R0_WOCLR_ISR_P_EN__VAL___S 0 +#define UMAC_UMCMN_R0_WOCLR_ISR_P_EN___M 0x00000001 +#define UMAC_UMCMN_R0_WOCLR_ISR_P_EN___S 0 + +#define UMAC_UMCMN_R0_UMAC_REVISION (0x00A400CC) +#define UMAC_UMCMN_R0_UMAC_REVISION___RWC QCSR_REG_RO +#define UMAC_UMCMN_R0_UMAC_REVISION___POR 0x10080000 +#define UMAC_UMCMN_R0_UMAC_REVISION__MAJOR___POR 0x1 +#define UMAC_UMCMN_R0_UMAC_REVISION__MINOR___POR 0x008 +#define UMAC_UMCMN_R0_UMAC_REVISION__STEP___POR 0x0000 +#define UMAC_UMCMN_R0_UMAC_REVISION__MAJOR___M 0xF0000000 +#define UMAC_UMCMN_R0_UMAC_REVISION__MAJOR___S 28 +#define UMAC_UMCMN_R0_UMAC_REVISION__MINOR___M 0x0FFF0000 +#define UMAC_UMCMN_R0_UMAC_REVISION__MINOR___S 16 +#define UMAC_UMCMN_R0_UMAC_REVISION__STEP___M 0x0000FFFF +#define UMAC_UMCMN_R0_UMAC_REVISION__STEP___S 0 +#define UMAC_UMCMN_R0_UMAC_REVISION___M 0xFFFFFFFF +#define UMAC_UMCMN_R0_UMAC_REVISION___S 0 + +#define UMAC_UMCMN_R0_IDLE_CTRL0 (0x00A400D0) +#define UMAC_UMCMN_R0_IDLE_CTRL0___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_IDLE_CTRL0___POR 0x000007DE +#define UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_NOC_IDLE_REQ___POR 0x0 +#define UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_WBM_IDLE_REQ___POR 0x0 +#define UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_TQM_IDLE_REQ___POR 0x0 +#define UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_CE_IDLE_REQ___POR 0x0 +#define UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_REO_IDLE_REQ___POR 0x0 +#define UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_TCL_IDLE_REQ___POR 0x0 +#define UMAC_UMCMN_R0_IDLE_CTRL0__INTER_STATE_DLY___POR 0x01F +#define UMAC_UMCMN_R0_IDLE_CTRL0__IDLE_INTG_CHK_DLY___POR 0x0F +#define UMAC_UMCMN_R0_IDLE_CTRL0__SW_IDLE_REQ___POR 0x0 +#define UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_NOC_IDLE_REQ___M 0x00200000 +#define UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_NOC_IDLE_REQ___S 21 +#define UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_WBM_IDLE_REQ___M 0x00100000 +#define UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_WBM_IDLE_REQ___S 20 +#define UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_TQM_IDLE_REQ___M 0x00080000 +#define UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_TQM_IDLE_REQ___S 19 +#define UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_CE_IDLE_REQ___M 0x00040000 +#define UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_CE_IDLE_REQ___S 18 +#define UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_REO_IDLE_REQ___M 0x00020000 +#define UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_REO_IDLE_REQ___S 17 +#define UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_TCL_IDLE_REQ___M 0x00010000 +#define UMAC_UMCMN_R0_IDLE_CTRL0__BLOCK_TCL_IDLE_REQ___S 16 +#define UMAC_UMCMN_R0_IDLE_CTRL0__INTER_STATE_DLY___M 0x0000FFC0 +#define UMAC_UMCMN_R0_IDLE_CTRL0__INTER_STATE_DLY___S 6 +#define UMAC_UMCMN_R0_IDLE_CTRL0__IDLE_INTG_CHK_DLY___M 0x0000003E +#define UMAC_UMCMN_R0_IDLE_CTRL0__IDLE_INTG_CHK_DLY___S 1 +#define UMAC_UMCMN_R0_IDLE_CTRL0__SW_IDLE_REQ___M 0x00000001 +#define UMAC_UMCMN_R0_IDLE_CTRL0__SW_IDLE_REQ___S 0 +#define UMAC_UMCMN_R0_IDLE_CTRL0___M 0x003FFFFF +#define UMAC_UMCMN_R0_IDLE_CTRL0___S 0 + +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR (0x00A400D4) +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR___POR 0x00000000 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__NOC_IDLE_REQ_SW_DATA___POR 0x0 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__NOC_IDLE_REQ_SW_OVR___POR 0x0 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__WBM_IDLE_REQ_SW_DATA___POR 0x0 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__WBM_IDLE_REQ_SW_OVR___POR 0x0 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__TQM_IDLE_REQ_SW_DATA___POR 0x0 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__TQM_IDLE_REQ_SW_OVR___POR 0x0 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__CE_IDLE_REQ_SW_DATA___POR 0x0 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__CE_IDLE_REQ_SW_OVR___POR 0x0 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__REO_IDLE_REQ_SW_DATA___POR 0x0 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__REO_IDLE_REQ_SW_OVR___POR 0x0 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__TCL_IDLE_REQ_SW_DATA___POR 0x0 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__TCL_IDLE_REQ_SW_OVR___POR 0x0 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__GLOBAL_SW_OVR___POR 0x0 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__NOC_IDLE_REQ_SW_DATA___M 0x00001000 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__NOC_IDLE_REQ_SW_DATA___S 12 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__NOC_IDLE_REQ_SW_OVR___M 0x00000800 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__NOC_IDLE_REQ_SW_OVR___S 11 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__WBM_IDLE_REQ_SW_DATA___M 0x00000400 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__WBM_IDLE_REQ_SW_DATA___S 10 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__WBM_IDLE_REQ_SW_OVR___M 0x00000200 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__WBM_IDLE_REQ_SW_OVR___S 9 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__TQM_IDLE_REQ_SW_DATA___M 0x00000100 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__TQM_IDLE_REQ_SW_DATA___S 8 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__TQM_IDLE_REQ_SW_OVR___M 0x00000080 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__TQM_IDLE_REQ_SW_OVR___S 7 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__CE_IDLE_REQ_SW_DATA___M 0x00000040 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__CE_IDLE_REQ_SW_DATA___S 6 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__CE_IDLE_REQ_SW_OVR___M 0x00000020 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__CE_IDLE_REQ_SW_OVR___S 5 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__REO_IDLE_REQ_SW_DATA___M 0x00000010 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__REO_IDLE_REQ_SW_DATA___S 4 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__REO_IDLE_REQ_SW_OVR___M 0x00000008 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__REO_IDLE_REQ_SW_OVR___S 3 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__TCL_IDLE_REQ_SW_DATA___M 0x00000004 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__TCL_IDLE_REQ_SW_DATA___S 2 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__TCL_IDLE_REQ_SW_OVR___M 0x00000002 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__TCL_IDLE_REQ_SW_OVR___S 1 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__GLOBAL_SW_OVR___M 0x00000001 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR__GLOBAL_SW_OVR___S 0 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR___M 0x00001FFF +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_SW_OVR___S 0 + +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL (0x00A400D8) +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL___POR 0x00000001 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL__FSM_WAIT_IN_STATE___POR 0x0000 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL__FSM_FORCE_IDLE___POR 0x0 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL__FSM_EN___POR 0x1 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL__FSM_WAIT_IN_STATE___M 0x0003FFFC +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL__FSM_WAIT_IN_STATE___S 2 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL__FSM_FORCE_IDLE___M 0x00000002 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL__FSM_FORCE_IDLE___S 1 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL__FSM_EN___M 0x00000001 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL__FSM_EN___S 0 +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL___M 0x0003FFFF +#define UMAC_UMCMN_R0_UMAC_IDLE_GEN_FSM_CTL___S 0 + +#define UMAC_UMCMN_R0_IDLE_SIGNAL (0x00A400DC) +#define UMAC_UMCMN_R0_IDLE_SIGNAL___RWC QCSR_REG_RO +#define UMAC_UMCMN_R0_IDLE_SIGNAL___POR 0x0000007D +#define UMAC_UMCMN_R0_IDLE_SIGNAL__REO___POR 0x1 +#define UMAC_UMCMN_R0_IDLE_SIGNAL__TCL___POR 0x1 +#define UMAC_UMCMN_R0_IDLE_SIGNAL__WBM___POR 0x1 +#define UMAC_UMCMN_R0_IDLE_SIGNAL__TQM___POR 0x1 +#define UMAC_UMCMN_R0_IDLE_SIGNAL__CXC___POR 0x1 +#define UMAC_UMCMN_R0_IDLE_SIGNAL__CE___POR 0x1 +#define UMAC_UMCMN_R0_IDLE_SIGNAL__REO___M 0x00000040 +#define UMAC_UMCMN_R0_IDLE_SIGNAL__REO___S 6 +#define UMAC_UMCMN_R0_IDLE_SIGNAL__TCL___M 0x00000020 +#define UMAC_UMCMN_R0_IDLE_SIGNAL__TCL___S 5 +#define UMAC_UMCMN_R0_IDLE_SIGNAL__WBM___M 0x00000010 +#define UMAC_UMCMN_R0_IDLE_SIGNAL__WBM___S 4 +#define UMAC_UMCMN_R0_IDLE_SIGNAL__TQM___M 0x00000008 +#define UMAC_UMCMN_R0_IDLE_SIGNAL__TQM___S 3 +#define UMAC_UMCMN_R0_IDLE_SIGNAL__CXC___M 0x00000004 +#define UMAC_UMCMN_R0_IDLE_SIGNAL__CXC___S 2 +#define UMAC_UMCMN_R0_IDLE_SIGNAL__CE___M 0x00000001 +#define UMAC_UMCMN_R0_IDLE_SIGNAL__CE___S 0 +#define UMAC_UMCMN_R0_IDLE_SIGNAL___M 0x0000007D +#define UMAC_UMCMN_R0_IDLE_SIGNAL___S 0 + +#define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS (0x00A400E0) +#define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS___RWC QCSR_REG_RO +#define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS___POR 0x00000000 +#define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__WBM_REL_RING___POR 0x0 +#define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__TQM_CMD_RING___POR 0x0 +#define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__REO_CMD_RING___POR 0x0 +#define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__TCL_CMD_RING___POR 0x0 +#define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__CE_CMD_RING___POR 0x0 +#define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__WBM_REL_RING___M 0x00000010 +#define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__WBM_REL_RING___S 4 +#define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__TQM_CMD_RING___M 0x00000008 +#define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__TQM_CMD_RING___S 3 +#define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__REO_CMD_RING___M 0x00000004 +#define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__REO_CMD_RING___S 2 +#define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__TCL_CMD_RING___M 0x00000002 +#define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__TCL_CMD_RING___S 1 +#define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__CE_CMD_RING___M 0x00000001 +#define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS__CE_CMD_RING___S 0 +#define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS___M 0x0000001F +#define UMAC_UMCMN_R0_RING_NOT_EMPTY_STATUS___S 0 + +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR (0x00A400E4) +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR___POR 0x00000000 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__NOC_IDLE_SWOVR_DATA___POR 0x0 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__NOC_IDLE_SWOVR___POR 0x0 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__WBM_IDLE_SWOVR_DATA___POR 0x0 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__WBM_IDLE_SWOVR___POR 0x0 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__TQM_IDLE_SWOVR_DATA___POR 0x0 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__TQM_IDLE_SWOVR___POR 0x0 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__CE_IDLE_SWOVR_DATA___POR 0x0 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__CE_IDLE_SWOVR___POR 0x0 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__REO_IDLE_SWOVR_DATA___POR 0x0 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__REO_IDLE_SWOVR___POR 0x0 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__TCL_IDLE_SWOVR_DATA___POR 0x0 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__TCL_IDLE_SWOVR___POR 0x0 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__NOC_IDLE_SWOVR_DATA___M 0x00000800 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__NOC_IDLE_SWOVR_DATA___S 11 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__NOC_IDLE_SWOVR___M 0x00000400 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__NOC_IDLE_SWOVR___S 10 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__WBM_IDLE_SWOVR_DATA___M 0x00000200 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__WBM_IDLE_SWOVR_DATA___S 9 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__WBM_IDLE_SWOVR___M 0x00000100 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__WBM_IDLE_SWOVR___S 8 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__TQM_IDLE_SWOVR_DATA___M 0x00000080 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__TQM_IDLE_SWOVR_DATA___S 7 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__TQM_IDLE_SWOVR___M 0x00000040 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__TQM_IDLE_SWOVR___S 6 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__CE_IDLE_SWOVR_DATA___M 0x00000020 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__CE_IDLE_SWOVR_DATA___S 5 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__CE_IDLE_SWOVR___M 0x00000010 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__CE_IDLE_SWOVR___S 4 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__REO_IDLE_SWOVR_DATA___M 0x00000008 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__REO_IDLE_SWOVR_DATA___S 3 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__REO_IDLE_SWOVR___M 0x00000004 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__REO_IDLE_SWOVR___S 2 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__TCL_IDLE_SWOVR_DATA___M 0x00000002 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__TCL_IDLE_SWOVR_DATA___S 1 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__TCL_IDLE_SWOVR___M 0x00000001 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR__TCL_IDLE_SWOVR___S 0 +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR___M 0x00000FFF +#define UMAC_UMCMN_R0_UMAC_IDLE_ACK_AND_RESP_SWOVR___S 0 + +#define UMAC_UMCMN_R0_S_PARE_0 (0x00A400E8) +#define UMAC_UMCMN_R0_S_PARE_0___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_S_PARE_0___POR 0x00000000 +#define UMAC_UMCMN_R0_S_PARE_0__S_PARE_0_BITS___POR 0x00000000 +#define UMAC_UMCMN_R0_S_PARE_0__S_PARE_0_BITS___M 0xFFFFFFFF +#define UMAC_UMCMN_R0_S_PARE_0__S_PARE_0_BITS___S 0 +#define UMAC_UMCMN_R0_S_PARE_0___M 0xFFFFFFFF +#define UMAC_UMCMN_R0_S_PARE_0___S 0 + +#define UMAC_UMCMN_R0_S_PARE_1 (0x00A400EC) +#define UMAC_UMCMN_R0_S_PARE_1___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_S_PARE_1___POR 0x00000000 +#define UMAC_UMCMN_R0_S_PARE_1__S_PARE_1_BITS___POR 0x00000000 +#define UMAC_UMCMN_R0_S_PARE_1__S_PARE_1_BITS___M 0xFFFFFFFF +#define UMAC_UMCMN_R0_S_PARE_1__S_PARE_1_BITS___S 0 +#define UMAC_UMCMN_R0_S_PARE_1___M 0xFFFFFFFF +#define UMAC_UMCMN_R0_S_PARE_1___S 0 + +#define UMAC_UMCMN_R0_S_PARE_2 (0x00A400F0) +#define UMAC_UMCMN_R0_S_PARE_2___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_S_PARE_2___POR 0x00000000 +#define UMAC_UMCMN_R0_S_PARE_2__S_PARE_2_BITS___POR 0x00000000 +#define UMAC_UMCMN_R0_S_PARE_2__S_PARE_2_BITS___M 0xFFFFFFFF +#define UMAC_UMCMN_R0_S_PARE_2__S_PARE_2_BITS___S 0 +#define UMAC_UMCMN_R0_S_PARE_2___M 0xFFFFFFFF +#define UMAC_UMCMN_R0_S_PARE_2___S 0 + +#define UMAC_UMCMN_R0_S_PARE_3 (0x00A400F4) +#define UMAC_UMCMN_R0_S_PARE_3___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_S_PARE_3___POR 0x00000000 +#define UMAC_UMCMN_R0_S_PARE_3__S_PARE_3_BITS___POR 0x00000000 +#define UMAC_UMCMN_R0_S_PARE_3__S_PARE_3_BITS___M 0xFFFFFFFF +#define UMAC_UMCMN_R0_S_PARE_3__S_PARE_3_BITS___S 0 +#define UMAC_UMCMN_R0_S_PARE_3___M 0xFFFFFFFF +#define UMAC_UMCMN_R0_S_PARE_3___S 0 + +#define UMAC_UMCMN_R0_UMAC_IDLE_LENGTH (0x00A400F8) +#define UMAC_UMCMN_R0_UMAC_IDLE_LENGTH___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_UMAC_IDLE_LENGTH___POR 0x00000008 +#define UMAC_UMCMN_R0_UMAC_IDLE_LENGTH__VALUE___POR 0x0008 +#define UMAC_UMCMN_R0_UMAC_IDLE_LENGTH__VALUE___M 0x0000FFFF +#define UMAC_UMCMN_R0_UMAC_IDLE_LENGTH__VALUE___S 0 +#define UMAC_UMCMN_R0_UMAC_IDLE_LENGTH___M 0x0000FFFF +#define UMAC_UMCMN_R0_UMAC_IDLE_LENGTH___S 0 + +#define UMAC_UMCMN_R0_UMAC_NON_IDLE_LENGTH (0x00A400FC) +#define UMAC_UMCMN_R0_UMAC_NON_IDLE_LENGTH___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_UMAC_NON_IDLE_LENGTH___POR 0x0000000A +#define UMAC_UMCMN_R0_UMAC_NON_IDLE_LENGTH__VALUE___POR 0x000A +#define UMAC_UMCMN_R0_UMAC_NON_IDLE_LENGTH__VALUE___M 0x0000FFFF +#define UMAC_UMCMN_R0_UMAC_NON_IDLE_LENGTH__VALUE___S 0 +#define UMAC_UMCMN_R0_UMAC_NON_IDLE_LENGTH___M 0x0000FFFF +#define UMAC_UMCMN_R0_UMAC_NON_IDLE_LENGTH___S 0 + +#define UMAC_UMCMN_R0_UMAC_TRACER_CONTROL (0x00A40100) +#define UMAC_UMCMN_R0_UMAC_TRACER_CONTROL___RWC QCSR_REG_RW +#define UMAC_UMCMN_R0_UMAC_TRACER_CONTROL___POR 0x00000000 +#define UMAC_UMCMN_R0_UMAC_TRACER_CONTROL__SUBSYSTEM_ID___POR 0x0 +#define UMAC_UMCMN_R0_UMAC_TRACER_CONTROL__TESTBUS_VALID_CONTROL___POR 0x0 +#define UMAC_UMCMN_R0_UMAC_TRACER_CONTROL__SUBSYSTEM_ID___M 0x0000000C +#define UMAC_UMCMN_R0_UMAC_TRACER_CONTROL__SUBSYSTEM_ID___S 2 +#define UMAC_UMCMN_R0_UMAC_TRACER_CONTROL__TESTBUS_VALID_CONTROL___M 0x00000003 +#define UMAC_UMCMN_R0_UMAC_TRACER_CONTROL__TESTBUS_VALID_CONTROL___S 0 +#define UMAC_UMCMN_R0_UMAC_TRACER_CONTROL___M 0x0000000F +#define UMAC_UMCMN_R0_UMAC_TRACER_CONTROL___S 0 + +#define UMAC_UMCMN_R1_INVALID_APB_ACC_ADDR (0x00A41000) +#define UMAC_UMCMN_R1_INVALID_APB_ACC_ADDR___RWC QCSR_REG_RO +#define UMAC_UMCMN_R1_INVALID_APB_ACC_ADDR___POR 0x00000000 +#define UMAC_UMCMN_R1_INVALID_APB_ACC_ADDR__VALUE___POR 0x000 +#define UMAC_UMCMN_R1_INVALID_APB_ACC_ADDR__VALUE___M 0x00000FFF +#define UMAC_UMCMN_R1_INVALID_APB_ACC_ADDR__VALUE___S 0 +#define UMAC_UMCMN_R1_INVALID_APB_ACC_ADDR___M 0x00000FFF +#define UMAC_UMCMN_R1_INVALID_APB_ACC_ADDR___S 0 + +#define UMAC_UMCMN_R1_UMAC_IDLE (0x00A41004) +#define UMAC_UMCMN_R1_UMAC_IDLE___RWC QCSR_REG_RO +#define UMAC_UMCMN_R1_UMAC_IDLE___POR 0x00000001 +#define UMAC_UMCMN_R1_UMAC_IDLE__UMAC_IDLE_GEN_MOD_BUSY___POR 0x0 +#define UMAC_UMCMN_R1_UMAC_IDLE__MAIN_SM_CS___POR 0x0001 +#define UMAC_UMCMN_R1_UMAC_IDLE__UMAC_IDLE_GEN_MOD_BUSY___M 0x00010000 +#define UMAC_UMCMN_R1_UMAC_IDLE__UMAC_IDLE_GEN_MOD_BUSY___S 16 +#define UMAC_UMCMN_R1_UMAC_IDLE__MAIN_SM_CS___M 0x0000FFFF +#define UMAC_UMCMN_R1_UMAC_IDLE__MAIN_SM_CS___S 0 +#define UMAC_UMCMN_R1_UMAC_IDLE___M 0x0001FFFF +#define UMAC_UMCMN_R1_UMAC_IDLE___S 0 + +#define UMAC_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS (0x00A41008) +#define UMAC_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS___RWC QCSR_REG_RO +#define UMAC_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS___POR 0x00000000 +#define UMAC_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS__VALUE___POR 0x000000 +#define UMAC_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS__VALUE___M 0x00FFFFFF +#define UMAC_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS__VALUE___S 0 +#define UMAC_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS___M 0x00FFFFFF +#define UMAC_UMCMN_R1_UMAC_IDLE_GEN_INTF_STATUS___S 0 + +#define UMAC_UMCMN_R1_UMAC_IDLE_GEN_ERR (0x00A4100C) +#define UMAC_UMCMN_R1_UMAC_IDLE_GEN_ERR___RWC QCSR_REG_RW +#define UMAC_UMCMN_R1_UMAC_IDLE_GEN_ERR___POR 0x00000000 +#define UMAC_UMCMN_R1_UMAC_IDLE_GEN_ERR__IDLE_ERR_STATUS_SW_WDATA___POR 0x00 +#define UMAC_UMCMN_R1_UMAC_IDLE_GEN_ERR__STATUS___POR 0x00 +#define UMAC_UMCMN_R1_UMAC_IDLE_GEN_ERR__IDLE_ERR_STATUS_SW_WDATA___M 0x00000FC0 +#define UMAC_UMCMN_R1_UMAC_IDLE_GEN_ERR__IDLE_ERR_STATUS_SW_WDATA___S 6 +#define UMAC_UMCMN_R1_UMAC_IDLE_GEN_ERR__STATUS___M 0x0000003F +#define UMAC_UMCMN_R1_UMAC_IDLE_GEN_ERR__STATUS___S 0 +#define UMAC_UMCMN_R1_UMAC_IDLE_GEN_ERR___M 0x00000FFF +#define UMAC_UMCMN_R1_UMAC_IDLE_GEN_ERR___S 0 + +#define UMAC_TCL_R0_SW2TCL1_RING_CTRL (0x00A44000) +#define UMAC_TCL_R0_SW2TCL1_RING_CTRL___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL1_RING_CTRL___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL1_RING_CTRL__TIMEOUT_VAL___POR 0x000 +#define UMAC_TCL_R0_SW2TCL1_RING_CTRL__RNG_PRTY___POR 0x0 +#define UMAC_TCL_R0_SW2TCL1_RING_CTRL__TIMEOUT_VAL___M 0x0003FFC0 +#define UMAC_TCL_R0_SW2TCL1_RING_CTRL__TIMEOUT_VAL___S 6 +#define UMAC_TCL_R0_SW2TCL1_RING_CTRL__RNG_PRTY___M 0x00000020 +#define UMAC_TCL_R0_SW2TCL1_RING_CTRL__RNG_PRTY___S 5 +#define UMAC_TCL_R0_SW2TCL1_RING_CTRL___M 0x0003FFE0 +#define UMAC_TCL_R0_SW2TCL1_RING_CTRL___S 5 + +#define UMAC_TCL_R0_SW2TCL2_RING_CTRL (0x00A44004) +#define UMAC_TCL_R0_SW2TCL2_RING_CTRL___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL2_RING_CTRL___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL2_RING_CTRL__TIMEOUT_VAL___POR 0x000 +#define UMAC_TCL_R0_SW2TCL2_RING_CTRL__RNG_PRTY___POR 0x0 +#define UMAC_TCL_R0_SW2TCL2_RING_CTRL__TIMEOUT_VAL___M 0x0003FFC0 +#define UMAC_TCL_R0_SW2TCL2_RING_CTRL__TIMEOUT_VAL___S 6 +#define UMAC_TCL_R0_SW2TCL2_RING_CTRL__RNG_PRTY___M 0x00000020 +#define UMAC_TCL_R0_SW2TCL2_RING_CTRL__RNG_PRTY___S 5 +#define UMAC_TCL_R0_SW2TCL2_RING_CTRL___M 0x0003FFE0 +#define UMAC_TCL_R0_SW2TCL2_RING_CTRL___S 5 + +#define UMAC_TCL_R0_SW2TCL3_RING_CTRL (0x00A44008) +#define UMAC_TCL_R0_SW2TCL3_RING_CTRL___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL3_RING_CTRL___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL3_RING_CTRL__TIMEOUT_VAL___POR 0x000 +#define UMAC_TCL_R0_SW2TCL3_RING_CTRL__RNG_PRTY___POR 0x0 +#define UMAC_TCL_R0_SW2TCL3_RING_CTRL__TIMEOUT_VAL___M 0x0003FFC0 +#define UMAC_TCL_R0_SW2TCL3_RING_CTRL__TIMEOUT_VAL___S 6 +#define UMAC_TCL_R0_SW2TCL3_RING_CTRL__RNG_PRTY___M 0x00000020 +#define UMAC_TCL_R0_SW2TCL3_RING_CTRL__RNG_PRTY___S 5 +#define UMAC_TCL_R0_SW2TCL3_RING_CTRL___M 0x0003FFE0 +#define UMAC_TCL_R0_SW2TCL3_RING_CTRL___S 5 + +#define UMAC_TCL_R0_FW2TCL1_RING_CTRL (0x00A4400C) +#define UMAC_TCL_R0_FW2TCL1_RING_CTRL___RWC QCSR_REG_RW +#define UMAC_TCL_R0_FW2TCL1_RING_CTRL___POR 0x00000000 +#define UMAC_TCL_R0_FW2TCL1_RING_CTRL__TIMEOUT_VAL___POR 0x000 +#define UMAC_TCL_R0_FW2TCL1_RING_CTRL__RNG_PRTY___POR 0x0 +#define UMAC_TCL_R0_FW2TCL1_RING_CTRL__TIMEOUT_VAL___M 0x0003FFC0 +#define UMAC_TCL_R0_FW2TCL1_RING_CTRL__TIMEOUT_VAL___S 6 +#define UMAC_TCL_R0_FW2TCL1_RING_CTRL__RNG_PRTY___M 0x00000020 +#define UMAC_TCL_R0_FW2TCL1_RING_CTRL__RNG_PRTY___S 5 +#define UMAC_TCL_R0_FW2TCL1_RING_CTRL___M 0x0003FFE0 +#define UMAC_TCL_R0_FW2TCL1_RING_CTRL___S 5 + +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CTRL (0x00A44010) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CTRL___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CTRL___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CTRL__TIMEOUT_VAL___POR 0x000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CTRL__RNG_PRTY___POR 0x0 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CTRL__TIMEOUT_VAL___M 0x0003FFC0 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CTRL__TIMEOUT_VAL___S 6 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CTRL__RNG_PRTY___M 0x00000020 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CTRL__RNG_PRTY___S 5 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CTRL___M 0x0003FFE0 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CTRL___S 5 + +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG (0x00A44014) +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG___RWC QCSR_REG_RW +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG___POR 0x0019C000 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__INSERT_VLAN_EN___POR 0x1 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__STOP_META_RD_AT_8B_BDRY___POR 0x1 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__ENABLE_C9D1___POR 0x0 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__DSCP_TID_MAP_PROGRAM_EN___POR 0x0 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__MSDU_EXTN_NUM_BUF_RD___POR 0x7 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__TCL_IDLE___POR 0x0 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL_CREDIT_RING_HALT_STAT___POR 0x0 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__FW2TCL1_RNG_HALT_STAT___POR 0x0 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL3_RNG_HALT_STAT___POR 0x0 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL2_RNG_HALT_STAT___POR 0x0 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL1_RNG_HALT_STAT___POR 0x0 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL_CREDIT_RING_HALT___POR 0x0 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__FW2TCL1_RNG_HALT___POR 0x0 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL3_RNG_HALT___POR 0x0 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL2_RNG_HALT___POR 0x0 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL1_RNG_HALT___POR 0x0 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__HDR_FWD_EN___POR 0x0 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__MSDU_HDR_LEN_SEL___POR 0x0 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__CLFY_DIS___POR 0x0 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__INSERT_VLAN_EN___M 0x00100000 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__INSERT_VLAN_EN___S 20 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__STOP_META_RD_AT_8B_BDRY___M 0x00080000 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__STOP_META_RD_AT_8B_BDRY___S 19 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__ENABLE_C9D1___M 0x00040000 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__ENABLE_C9D1___S 18 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__DSCP_TID_MAP_PROGRAM_EN___M 0x00020000 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__DSCP_TID_MAP_PROGRAM_EN___S 17 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__MSDU_EXTN_NUM_BUF_RD___M 0x0001C000 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__MSDU_EXTN_NUM_BUF_RD___S 14 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__TCL_IDLE___M 0x00002000 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__TCL_IDLE___S 13 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL_CREDIT_RING_HALT_STAT___M 0x00001000 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL_CREDIT_RING_HALT_STAT___S 12 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__FW2TCL1_RNG_HALT_STAT___M 0x00000800 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__FW2TCL1_RNG_HALT_STAT___S 11 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL3_RNG_HALT_STAT___M 0x00000400 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL3_RNG_HALT_STAT___S 10 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL2_RNG_HALT_STAT___M 0x00000200 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL2_RNG_HALT_STAT___S 9 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL1_RNG_HALT_STAT___M 0x00000100 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL1_RNG_HALT_STAT___S 8 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL_CREDIT_RING_HALT___M 0x00000080 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL_CREDIT_RING_HALT___S 7 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__FW2TCL1_RNG_HALT___M 0x00000040 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__FW2TCL1_RNG_HALT___S 6 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL3_RNG_HALT___M 0x00000020 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL3_RNG_HALT___S 5 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL2_RNG_HALT___M 0x00000010 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL2_RNG_HALT___S 4 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL1_RNG_HALT___M 0x00000008 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__SW2TCL1_RNG_HALT___S 3 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__HDR_FWD_EN___M 0x00000004 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__HDR_FWD_EN___S 2 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__MSDU_HDR_LEN_SEL___M 0x00000002 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__MSDU_HDR_LEN_SEL___S 1 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__CLFY_DIS___M 0x00000001 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG__CLFY_DIS___S 0 +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG___M 0x001FFFFF +#define UMAC_TCL_R0_CONS_RING_CMN_CTRL_REG___S 0 + +#define UMAC_TCL_R0_TCL2TQM_RING_CTRL (0x00A44018) +#define UMAC_TCL_R0_TCL2TQM_RING_CTRL___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL2TQM_RING_CTRL___POR 0x00000000 +#define UMAC_TCL_R0_TCL2TQM_RING_CTRL__DROP_NO_DROP_PRIORITY___POR 0x0 +#define UMAC_TCL_R0_TCL2TQM_RING_CTRL__TQM_STATUS_RING___POR 0x0 +#define UMAC_TCL_R0_TCL2TQM_RING_CTRL__TQM_STATUS_REQUIRED___POR 0x0 +#define UMAC_TCL_R0_TCL2TQM_RING_CTRL__TIMEOUT_VAL___POR 0x000 +#define UMAC_TCL_R0_TCL2TQM_RING_CTRL__DROP_NO_DROP_PRIORITY___M 0x0000C000 +#define UMAC_TCL_R0_TCL2TQM_RING_CTRL__DROP_NO_DROP_PRIORITY___S 14 +#define UMAC_TCL_R0_TCL2TQM_RING_CTRL__TQM_STATUS_RING___M 0x00002000 +#define UMAC_TCL_R0_TCL2TQM_RING_CTRL__TQM_STATUS_RING___S 13 +#define UMAC_TCL_R0_TCL2TQM_RING_CTRL__TQM_STATUS_REQUIRED___M 0x00001000 +#define UMAC_TCL_R0_TCL2TQM_RING_CTRL__TQM_STATUS_REQUIRED___S 12 +#define UMAC_TCL_R0_TCL2TQM_RING_CTRL__TIMEOUT_VAL___M 0x00000FFF +#define UMAC_TCL_R0_TCL2TQM_RING_CTRL__TIMEOUT_VAL___S 0 +#define UMAC_TCL_R0_TCL2TQM_RING_CTRL___M 0x0000FFFF +#define UMAC_TCL_R0_TCL2TQM_RING_CTRL___S 0 + +#define UMAC_TCL_R0_TCL2FW_RING_CTRL (0x00A4401C) +#define UMAC_TCL_R0_TCL2FW_RING_CTRL___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL2FW_RING_CTRL___POR 0x00000000 +#define UMAC_TCL_R0_TCL2FW_RING_CTRL__TIMEOUT_VAL___POR 0x000 +#define UMAC_TCL_R0_TCL2FW_RING_CTRL__TIMEOUT_VAL___M 0x00000FFF +#define UMAC_TCL_R0_TCL2FW_RING_CTRL__TIMEOUT_VAL___S 0 +#define UMAC_TCL_R0_TCL2FW_RING_CTRL___M 0x00000FFF +#define UMAC_TCL_R0_TCL2FW_RING_CTRL___S 0 + +#define UMAC_TCL_R0_TCL_STATUS1_RING_CTRL (0x00A44020) +#define UMAC_TCL_R0_TCL_STATUS1_RING_CTRL___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL_STATUS1_RING_CTRL___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_CTRL__TIMEOUT_VAL___POR 0x000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_CTRL__TIMEOUT_VAL___M 0x00000FFF +#define UMAC_TCL_R0_TCL_STATUS1_RING_CTRL__TIMEOUT_VAL___S 0 +#define UMAC_TCL_R0_TCL_STATUS1_RING_CTRL___M 0x00000FFF +#define UMAC_TCL_R0_TCL_STATUS1_RING_CTRL___S 0 + +#define UMAC_TCL_R0_TCL_STATUS2_RING_CTRL (0x00A44024) +#define UMAC_TCL_R0_TCL_STATUS2_RING_CTRL___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL_STATUS2_RING_CTRL___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_CTRL__TIMEOUT_VAL___POR 0x000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_CTRL__TIMEOUT_VAL___M 0x00000FFF +#define UMAC_TCL_R0_TCL_STATUS2_RING_CTRL__TIMEOUT_VAL___S 0 +#define UMAC_TCL_R0_TCL_STATUS2_RING_CTRL___M 0x00000FFF +#define UMAC_TCL_R0_TCL_STATUS2_RING_CTRL___S 0 + +#define UMAC_TCL_R0_GEN_CTRL (0x00A44028) +#define UMAC_TCL_R0_GEN_CTRL___RWC QCSR_REG_RW +#define UMAC_TCL_R0_GEN_CTRL___POR 0x00000000 +#define UMAC_TCL_R0_GEN_CTRL__WHO_CLASSIFY_INFO_OFFSET___POR 0x0000 +#define UMAC_TCL_R0_GEN_CTRL__PROTOCOL_FROM_AH_OR_L4___POR 0x0 +#define UMAC_TCL_R0_GEN_CTRL__PROTOCOL_FROM_AH_OR_ESP___POR 0x0 +#define UMAC_TCL_R0_GEN_CTRL__FLOW_TOEPLITZ_5_SEL___POR 0x0 +#define UMAC_TCL_R0_GEN_CTRL__CCE_STAT_UP_DIS___POR 0x0 +#define UMAC_TCL_R0_GEN_CTRL__CCE_UPDATE_DIS___POR 0x0 +#define UMAC_TCL_R0_GEN_CTRL__FSE_UPDATE_DIS___POR 0x0 +#define UMAC_TCL_R0_GEN_CTRL__ADDRY_UPDATE_DIS___POR 0x0 +#define UMAC_TCL_R0_GEN_CTRL__ADDRX_UPDATE_DIS___POR 0x0 +#define UMAC_TCL_R0_GEN_CTRL__FSE_EN___POR 0x0 +#define UMAC_TCL_R0_GEN_CTRL__CCE_EN___POR 0x0 +#define UMAC_TCL_R0_GEN_CTRL__TO_FW___POR 0x0 +#define UMAC_TCL_R0_GEN_CTRL__EN_11AH___POR 0x0 +#define UMAC_TCL_R0_GEN_CTRL__WHO_CLASSIFY_INFO_OFFSET___M 0xFFFF0000 +#define UMAC_TCL_R0_GEN_CTRL__WHO_CLASSIFY_INFO_OFFSET___S 16 +#define UMAC_TCL_R0_GEN_CTRL__PROTOCOL_FROM_AH_OR_L4___M 0x00008000 +#define UMAC_TCL_R0_GEN_CTRL__PROTOCOL_FROM_AH_OR_L4___S 15 +#define UMAC_TCL_R0_GEN_CTRL__PROTOCOL_FROM_AH_OR_ESP___M 0x00004000 +#define UMAC_TCL_R0_GEN_CTRL__PROTOCOL_FROM_AH_OR_ESP___S 14 +#define UMAC_TCL_R0_GEN_CTRL__FLOW_TOEPLITZ_5_SEL___M 0x00002000 +#define UMAC_TCL_R0_GEN_CTRL__FLOW_TOEPLITZ_5_SEL___S 13 +#define UMAC_TCL_R0_GEN_CTRL__CCE_STAT_UP_DIS___M 0x00001000 +#define UMAC_TCL_R0_GEN_CTRL__CCE_STAT_UP_DIS___S 12 +#define UMAC_TCL_R0_GEN_CTRL__CCE_UPDATE_DIS___M 0x00000100 +#define UMAC_TCL_R0_GEN_CTRL__CCE_UPDATE_DIS___S 8 +#define UMAC_TCL_R0_GEN_CTRL__FSE_UPDATE_DIS___M 0x00000080 +#define UMAC_TCL_R0_GEN_CTRL__FSE_UPDATE_DIS___S 7 +#define UMAC_TCL_R0_GEN_CTRL__ADDRY_UPDATE_DIS___M 0x00000040 +#define UMAC_TCL_R0_GEN_CTRL__ADDRY_UPDATE_DIS___S 6 +#define UMAC_TCL_R0_GEN_CTRL__ADDRX_UPDATE_DIS___M 0x00000020 +#define UMAC_TCL_R0_GEN_CTRL__ADDRX_UPDATE_DIS___S 5 +#define UMAC_TCL_R0_GEN_CTRL__FSE_EN___M 0x00000010 +#define UMAC_TCL_R0_GEN_CTRL__FSE_EN___S 4 +#define UMAC_TCL_R0_GEN_CTRL__CCE_EN___M 0x00000008 +#define UMAC_TCL_R0_GEN_CTRL__CCE_EN___S 3 +#define UMAC_TCL_R0_GEN_CTRL__TO_FW___M 0x00000002 +#define UMAC_TCL_R0_GEN_CTRL__TO_FW___S 1 +#define UMAC_TCL_R0_GEN_CTRL__EN_11AH___M 0x00000001 +#define UMAC_TCL_R0_GEN_CTRL__EN_11AH___S 0 +#define UMAC_TCL_R0_GEN_CTRL___M 0xFFFFF1FB +#define UMAC_TCL_R0_GEN_CTRL___S 0 + +#define UMAC_TCL_R0_DSCP_TID_MAP_n(n) (0x00A4402C+0x4*(n)) +#define UMAC_TCL_R0_DSCP_TID_MAP_n_nMIN 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_n_nMAX 287 +#define UMAC_TCL_R0_DSCP_TID_MAP_n_ELEM 288 +#define UMAC_TCL_R0_DSCP_TID_MAP_n___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_n___POR 0x00000000 +#define UMAC_TCL_R0_DSCP_TID_MAP_n__VAL___POR 0x00000000 +#define UMAC_TCL_R0_DSCP_TID_MAP_n__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_n__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_n___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_n___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_0 (0x00A4402C) +#define UMAC_TCL_R0_DSCP_TID_MAP_0___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_0__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_0__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_1 (0x00A44030) +#define UMAC_TCL_R0_DSCP_TID_MAP_1___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_1__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_1__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_2 (0x00A44034) +#define UMAC_TCL_R0_DSCP_TID_MAP_2___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_2__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_2__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_3 (0x00A44038) +#define UMAC_TCL_R0_DSCP_TID_MAP_3___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_3__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_3__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_4 (0x00A4403C) +#define UMAC_TCL_R0_DSCP_TID_MAP_4___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_4__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_4__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_5 (0x00A44040) +#define UMAC_TCL_R0_DSCP_TID_MAP_5___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_5__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_5__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_6 (0x00A44044) +#define UMAC_TCL_R0_DSCP_TID_MAP_6___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_6__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_6__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_7 (0x00A44048) +#define UMAC_TCL_R0_DSCP_TID_MAP_7___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_7__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_7__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_8 (0x00A4404C) +#define UMAC_TCL_R0_DSCP_TID_MAP_8___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_8__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_8__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_9 (0x00A44050) +#define UMAC_TCL_R0_DSCP_TID_MAP_9___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_9__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_9__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_10 (0x00A44054) +#define UMAC_TCL_R0_DSCP_TID_MAP_10___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_10__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_10__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_11 (0x00A44058) +#define UMAC_TCL_R0_DSCP_TID_MAP_11___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_11__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_11__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_12 (0x00A4405C) +#define UMAC_TCL_R0_DSCP_TID_MAP_12___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_12__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_12__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_13 (0x00A44060) +#define UMAC_TCL_R0_DSCP_TID_MAP_13___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_13__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_13__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_14 (0x00A44064) +#define UMAC_TCL_R0_DSCP_TID_MAP_14___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_14__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_14__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_15 (0x00A44068) +#define UMAC_TCL_R0_DSCP_TID_MAP_15___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_15__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_15__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_16 (0x00A4406C) +#define UMAC_TCL_R0_DSCP_TID_MAP_16___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_16__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_16__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_17 (0x00A44070) +#define UMAC_TCL_R0_DSCP_TID_MAP_17___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_17__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_17__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_18 (0x00A44074) +#define UMAC_TCL_R0_DSCP_TID_MAP_18___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_18__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_18__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_19 (0x00A44078) +#define UMAC_TCL_R0_DSCP_TID_MAP_19___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_19__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_19__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_20 (0x00A4407C) +#define UMAC_TCL_R0_DSCP_TID_MAP_20___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_20__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_20__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_21 (0x00A44080) +#define UMAC_TCL_R0_DSCP_TID_MAP_21___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_21__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_21__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_22 (0x00A44084) +#define UMAC_TCL_R0_DSCP_TID_MAP_22___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_22__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_22__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_23 (0x00A44088) +#define UMAC_TCL_R0_DSCP_TID_MAP_23___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_23__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_23__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_24 (0x00A4408C) +#define UMAC_TCL_R0_DSCP_TID_MAP_24___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_24__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_24__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_25 (0x00A44090) +#define UMAC_TCL_R0_DSCP_TID_MAP_25___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_25__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_25__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_26 (0x00A44094) +#define UMAC_TCL_R0_DSCP_TID_MAP_26___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_26__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_26__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_27 (0x00A44098) +#define UMAC_TCL_R0_DSCP_TID_MAP_27___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_27__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_27__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_28 (0x00A4409C) +#define UMAC_TCL_R0_DSCP_TID_MAP_28___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_28__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_28__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_29 (0x00A440A0) +#define UMAC_TCL_R0_DSCP_TID_MAP_29___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_29__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_29__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_30 (0x00A440A4) +#define UMAC_TCL_R0_DSCP_TID_MAP_30___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_30__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_30__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_31 (0x00A440A8) +#define UMAC_TCL_R0_DSCP_TID_MAP_31___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_31__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_31__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_32 (0x00A440AC) +#define UMAC_TCL_R0_DSCP_TID_MAP_32___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_32__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_32__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_33 (0x00A440B0) +#define UMAC_TCL_R0_DSCP_TID_MAP_33___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_33__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_33__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_34 (0x00A440B4) +#define UMAC_TCL_R0_DSCP_TID_MAP_34___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_34__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_34__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_35 (0x00A440B8) +#define UMAC_TCL_R0_DSCP_TID_MAP_35___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_35__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_35__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_36 (0x00A440BC) +#define UMAC_TCL_R0_DSCP_TID_MAP_36___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_36__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_36__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_37 (0x00A440C0) +#define UMAC_TCL_R0_DSCP_TID_MAP_37___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_37__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_37__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_38 (0x00A440C4) +#define UMAC_TCL_R0_DSCP_TID_MAP_38___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_38__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_38__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_39 (0x00A440C8) +#define UMAC_TCL_R0_DSCP_TID_MAP_39___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_39__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_39__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_40 (0x00A440CC) +#define UMAC_TCL_R0_DSCP_TID_MAP_40___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_40__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_40__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_41 (0x00A440D0) +#define UMAC_TCL_R0_DSCP_TID_MAP_41___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_41__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_41__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_42 (0x00A440D4) +#define UMAC_TCL_R0_DSCP_TID_MAP_42___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_42__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_42__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_43 (0x00A440D8) +#define UMAC_TCL_R0_DSCP_TID_MAP_43___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_43__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_43__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_44 (0x00A440DC) +#define UMAC_TCL_R0_DSCP_TID_MAP_44___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_44__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_44__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_45 (0x00A440E0) +#define UMAC_TCL_R0_DSCP_TID_MAP_45___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_45__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_45__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_46 (0x00A440E4) +#define UMAC_TCL_R0_DSCP_TID_MAP_46___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_46__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_46__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_47 (0x00A440E8) +#define UMAC_TCL_R0_DSCP_TID_MAP_47___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_47__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_47__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_48 (0x00A440EC) +#define UMAC_TCL_R0_DSCP_TID_MAP_48___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_48__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_48__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_49 (0x00A440F0) +#define UMAC_TCL_R0_DSCP_TID_MAP_49___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_49__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_49__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_50 (0x00A440F4) +#define UMAC_TCL_R0_DSCP_TID_MAP_50___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_50__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_50__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_51 (0x00A440F8) +#define UMAC_TCL_R0_DSCP_TID_MAP_51___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_51__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_51__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_52 (0x00A440FC) +#define UMAC_TCL_R0_DSCP_TID_MAP_52___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_52__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_52__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_53 (0x00A44100) +#define UMAC_TCL_R0_DSCP_TID_MAP_53___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_53__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_53__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_54 (0x00A44104) +#define UMAC_TCL_R0_DSCP_TID_MAP_54___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_54__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_54__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_55 (0x00A44108) +#define UMAC_TCL_R0_DSCP_TID_MAP_55___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_55__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_55__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_56 (0x00A4410C) +#define UMAC_TCL_R0_DSCP_TID_MAP_56___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_56__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_56__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_57 (0x00A44110) +#define UMAC_TCL_R0_DSCP_TID_MAP_57___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_57__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_57__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_58 (0x00A44114) +#define UMAC_TCL_R0_DSCP_TID_MAP_58___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_58__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_58__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_59 (0x00A44118) +#define UMAC_TCL_R0_DSCP_TID_MAP_59___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_59__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_59__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_60 (0x00A4411C) +#define UMAC_TCL_R0_DSCP_TID_MAP_60___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_60__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_60__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_61 (0x00A44120) +#define UMAC_TCL_R0_DSCP_TID_MAP_61___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_61__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_61__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_62 (0x00A44124) +#define UMAC_TCL_R0_DSCP_TID_MAP_62___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_62__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_62__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_63 (0x00A44128) +#define UMAC_TCL_R0_DSCP_TID_MAP_63___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_63__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_63__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_64 (0x00A4412C) +#define UMAC_TCL_R0_DSCP_TID_MAP_64___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_64__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_64__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_65 (0x00A44130) +#define UMAC_TCL_R0_DSCP_TID_MAP_65___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_65__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_65__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_66 (0x00A44134) +#define UMAC_TCL_R0_DSCP_TID_MAP_66___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_66__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_66__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_67 (0x00A44138) +#define UMAC_TCL_R0_DSCP_TID_MAP_67___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_67__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_67__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_68 (0x00A4413C) +#define UMAC_TCL_R0_DSCP_TID_MAP_68___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_68__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_68__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_69 (0x00A44140) +#define UMAC_TCL_R0_DSCP_TID_MAP_69___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_69__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_69__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_70 (0x00A44144) +#define UMAC_TCL_R0_DSCP_TID_MAP_70___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_70__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_70__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_71 (0x00A44148) +#define UMAC_TCL_R0_DSCP_TID_MAP_71___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_71__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_71__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_72 (0x00A4414C) +#define UMAC_TCL_R0_DSCP_TID_MAP_72___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_72__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_72__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_73 (0x00A44150) +#define UMAC_TCL_R0_DSCP_TID_MAP_73___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_73__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_73__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_74 (0x00A44154) +#define UMAC_TCL_R0_DSCP_TID_MAP_74___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_74__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_74__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_75 (0x00A44158) +#define UMAC_TCL_R0_DSCP_TID_MAP_75___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_75__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_75__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_76 (0x00A4415C) +#define UMAC_TCL_R0_DSCP_TID_MAP_76___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_76__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_76__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_77 (0x00A44160) +#define UMAC_TCL_R0_DSCP_TID_MAP_77___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_77__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_77__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_78 (0x00A44164) +#define UMAC_TCL_R0_DSCP_TID_MAP_78___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_78__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_78__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_79 (0x00A44168) +#define UMAC_TCL_R0_DSCP_TID_MAP_79___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_79__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_79__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_80 (0x00A4416C) +#define UMAC_TCL_R0_DSCP_TID_MAP_80___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_80__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_80__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_81 (0x00A44170) +#define UMAC_TCL_R0_DSCP_TID_MAP_81___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_81__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_81__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_82 (0x00A44174) +#define UMAC_TCL_R0_DSCP_TID_MAP_82___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_82__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_82__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_83 (0x00A44178) +#define UMAC_TCL_R0_DSCP_TID_MAP_83___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_83__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_83__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_84 (0x00A4417C) +#define UMAC_TCL_R0_DSCP_TID_MAP_84___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_84__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_84__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_85 (0x00A44180) +#define UMAC_TCL_R0_DSCP_TID_MAP_85___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_85__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_85__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_86 (0x00A44184) +#define UMAC_TCL_R0_DSCP_TID_MAP_86___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_86__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_86__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_87 (0x00A44188) +#define UMAC_TCL_R0_DSCP_TID_MAP_87___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_87__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_87__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_88 (0x00A4418C) +#define UMAC_TCL_R0_DSCP_TID_MAP_88___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_88__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_88__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_89 (0x00A44190) +#define UMAC_TCL_R0_DSCP_TID_MAP_89___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_89__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_89__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_90 (0x00A44194) +#define UMAC_TCL_R0_DSCP_TID_MAP_90___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_90__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_90__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_91 (0x00A44198) +#define UMAC_TCL_R0_DSCP_TID_MAP_91___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_91__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_91__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_92 (0x00A4419C) +#define UMAC_TCL_R0_DSCP_TID_MAP_92___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_92__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_92__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_93 (0x00A441A0) +#define UMAC_TCL_R0_DSCP_TID_MAP_93___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_93__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_93__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_94 (0x00A441A4) +#define UMAC_TCL_R0_DSCP_TID_MAP_94___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_94__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_94__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_95 (0x00A441A8) +#define UMAC_TCL_R0_DSCP_TID_MAP_95___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_95__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_95__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_96 (0x00A441AC) +#define UMAC_TCL_R0_DSCP_TID_MAP_96___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_96__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_96__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_97 (0x00A441B0) +#define UMAC_TCL_R0_DSCP_TID_MAP_97___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_97__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_97__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_98 (0x00A441B4) +#define UMAC_TCL_R0_DSCP_TID_MAP_98___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_98__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_98__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_99 (0x00A441B8) +#define UMAC_TCL_R0_DSCP_TID_MAP_99___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_99__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_99__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_100 (0x00A441BC) +#define UMAC_TCL_R0_DSCP_TID_MAP_100___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_100__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_100__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_101 (0x00A441C0) +#define UMAC_TCL_R0_DSCP_TID_MAP_101___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_101__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_101__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_102 (0x00A441C4) +#define UMAC_TCL_R0_DSCP_TID_MAP_102___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_102__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_102__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_103 (0x00A441C8) +#define UMAC_TCL_R0_DSCP_TID_MAP_103___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_103__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_103__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_104 (0x00A441CC) +#define UMAC_TCL_R0_DSCP_TID_MAP_104___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_104__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_104__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_105 (0x00A441D0) +#define UMAC_TCL_R0_DSCP_TID_MAP_105___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_105__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_105__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_106 (0x00A441D4) +#define UMAC_TCL_R0_DSCP_TID_MAP_106___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_106__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_106__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_107 (0x00A441D8) +#define UMAC_TCL_R0_DSCP_TID_MAP_107___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_107__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_107__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_108 (0x00A441DC) +#define UMAC_TCL_R0_DSCP_TID_MAP_108___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_108__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_108__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_109 (0x00A441E0) +#define UMAC_TCL_R0_DSCP_TID_MAP_109___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_109__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_109__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_110 (0x00A441E4) +#define UMAC_TCL_R0_DSCP_TID_MAP_110___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_110__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_110__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_111 (0x00A441E8) +#define UMAC_TCL_R0_DSCP_TID_MAP_111___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_111__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_111__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_112 (0x00A441EC) +#define UMAC_TCL_R0_DSCP_TID_MAP_112___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_112__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_112__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_113 (0x00A441F0) +#define UMAC_TCL_R0_DSCP_TID_MAP_113___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_113__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_113__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_114 (0x00A441F4) +#define UMAC_TCL_R0_DSCP_TID_MAP_114___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_114__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_114__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_115 (0x00A441F8) +#define UMAC_TCL_R0_DSCP_TID_MAP_115___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_115__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_115__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_116 (0x00A441FC) +#define UMAC_TCL_R0_DSCP_TID_MAP_116___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_116__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_116__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_117 (0x00A44200) +#define UMAC_TCL_R0_DSCP_TID_MAP_117___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_117__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_117__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_118 (0x00A44204) +#define UMAC_TCL_R0_DSCP_TID_MAP_118___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_118__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_118__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_119 (0x00A44208) +#define UMAC_TCL_R0_DSCP_TID_MAP_119___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_119__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_119__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_120 (0x00A4420C) +#define UMAC_TCL_R0_DSCP_TID_MAP_120___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_120__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_120__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_121 (0x00A44210) +#define UMAC_TCL_R0_DSCP_TID_MAP_121___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_121__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_121__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_122 (0x00A44214) +#define UMAC_TCL_R0_DSCP_TID_MAP_122___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_122__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_122__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_123 (0x00A44218) +#define UMAC_TCL_R0_DSCP_TID_MAP_123___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_123__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_123__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_124 (0x00A4421C) +#define UMAC_TCL_R0_DSCP_TID_MAP_124___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_124__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_124__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_125 (0x00A44220) +#define UMAC_TCL_R0_DSCP_TID_MAP_125___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_125__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_125__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_126 (0x00A44224) +#define UMAC_TCL_R0_DSCP_TID_MAP_126___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_126__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_126__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_127 (0x00A44228) +#define UMAC_TCL_R0_DSCP_TID_MAP_127___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_127__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_127__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_128 (0x00A4422C) +#define UMAC_TCL_R0_DSCP_TID_MAP_128___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_128__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_128__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_129 (0x00A44230) +#define UMAC_TCL_R0_DSCP_TID_MAP_129___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_129__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_129__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_130 (0x00A44234) +#define UMAC_TCL_R0_DSCP_TID_MAP_130___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_130__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_130__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_131 (0x00A44238) +#define UMAC_TCL_R0_DSCP_TID_MAP_131___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_131__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_131__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_132 (0x00A4423C) +#define UMAC_TCL_R0_DSCP_TID_MAP_132___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_132__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_132__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_133 (0x00A44240) +#define UMAC_TCL_R0_DSCP_TID_MAP_133___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_133__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_133__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_134 (0x00A44244) +#define UMAC_TCL_R0_DSCP_TID_MAP_134___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_134__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_134__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_135 (0x00A44248) +#define UMAC_TCL_R0_DSCP_TID_MAP_135___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_135__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_135__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_136 (0x00A4424C) +#define UMAC_TCL_R0_DSCP_TID_MAP_136___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_136__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_136__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_137 (0x00A44250) +#define UMAC_TCL_R0_DSCP_TID_MAP_137___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_137__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_137__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_138 (0x00A44254) +#define UMAC_TCL_R0_DSCP_TID_MAP_138___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_138__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_138__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_139 (0x00A44258) +#define UMAC_TCL_R0_DSCP_TID_MAP_139___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_139__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_139__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_140 (0x00A4425C) +#define UMAC_TCL_R0_DSCP_TID_MAP_140___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_140__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_140__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_141 (0x00A44260) +#define UMAC_TCL_R0_DSCP_TID_MAP_141___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_141__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_141__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_142 (0x00A44264) +#define UMAC_TCL_R0_DSCP_TID_MAP_142___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_142__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_142__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_143 (0x00A44268) +#define UMAC_TCL_R0_DSCP_TID_MAP_143___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_143__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_143__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_144 (0x00A4426C) +#define UMAC_TCL_R0_DSCP_TID_MAP_144___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_144__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_144__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_145 (0x00A44270) +#define UMAC_TCL_R0_DSCP_TID_MAP_145___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_145__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_145__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_146 (0x00A44274) +#define UMAC_TCL_R0_DSCP_TID_MAP_146___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_146__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_146__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_147 (0x00A44278) +#define UMAC_TCL_R0_DSCP_TID_MAP_147___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_147__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_147__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_148 (0x00A4427C) +#define UMAC_TCL_R0_DSCP_TID_MAP_148___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_148__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_148__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_149 (0x00A44280) +#define UMAC_TCL_R0_DSCP_TID_MAP_149___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_149__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_149__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_150 (0x00A44284) +#define UMAC_TCL_R0_DSCP_TID_MAP_150___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_150__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_150__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_151 (0x00A44288) +#define UMAC_TCL_R0_DSCP_TID_MAP_151___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_151__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_151__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_152 (0x00A4428C) +#define UMAC_TCL_R0_DSCP_TID_MAP_152___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_152__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_152__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_153 (0x00A44290) +#define UMAC_TCL_R0_DSCP_TID_MAP_153___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_153__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_153__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_154 (0x00A44294) +#define UMAC_TCL_R0_DSCP_TID_MAP_154___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_154__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_154__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_155 (0x00A44298) +#define UMAC_TCL_R0_DSCP_TID_MAP_155___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_155__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_155__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_156 (0x00A4429C) +#define UMAC_TCL_R0_DSCP_TID_MAP_156___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_156__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_156__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_157 (0x00A442A0) +#define UMAC_TCL_R0_DSCP_TID_MAP_157___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_157__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_157__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_158 (0x00A442A4) +#define UMAC_TCL_R0_DSCP_TID_MAP_158___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_158__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_158__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_159 (0x00A442A8) +#define UMAC_TCL_R0_DSCP_TID_MAP_159___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_159__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_159__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_160 (0x00A442AC) +#define UMAC_TCL_R0_DSCP_TID_MAP_160___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_160__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_160__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_161 (0x00A442B0) +#define UMAC_TCL_R0_DSCP_TID_MAP_161___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_161__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_161__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_162 (0x00A442B4) +#define UMAC_TCL_R0_DSCP_TID_MAP_162___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_162__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_162__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_163 (0x00A442B8) +#define UMAC_TCL_R0_DSCP_TID_MAP_163___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_163__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_163__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_164 (0x00A442BC) +#define UMAC_TCL_R0_DSCP_TID_MAP_164___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_164__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_164__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_165 (0x00A442C0) +#define UMAC_TCL_R0_DSCP_TID_MAP_165___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_165__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_165__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_166 (0x00A442C4) +#define UMAC_TCL_R0_DSCP_TID_MAP_166___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_166__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_166__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_167 (0x00A442C8) +#define UMAC_TCL_R0_DSCP_TID_MAP_167___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_167__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_167__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_168 (0x00A442CC) +#define UMAC_TCL_R0_DSCP_TID_MAP_168___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_168__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_168__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_169 (0x00A442D0) +#define UMAC_TCL_R0_DSCP_TID_MAP_169___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_169__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_169__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_170 (0x00A442D4) +#define UMAC_TCL_R0_DSCP_TID_MAP_170___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_170__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_170__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_171 (0x00A442D8) +#define UMAC_TCL_R0_DSCP_TID_MAP_171___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_171__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_171__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_172 (0x00A442DC) +#define UMAC_TCL_R0_DSCP_TID_MAP_172___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_172__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_172__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_173 (0x00A442E0) +#define UMAC_TCL_R0_DSCP_TID_MAP_173___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_173__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_173__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_174 (0x00A442E4) +#define UMAC_TCL_R0_DSCP_TID_MAP_174___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_174__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_174__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_175 (0x00A442E8) +#define UMAC_TCL_R0_DSCP_TID_MAP_175___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_175__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_175__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_176 (0x00A442EC) +#define UMAC_TCL_R0_DSCP_TID_MAP_176___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_176__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_176__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_177 (0x00A442F0) +#define UMAC_TCL_R0_DSCP_TID_MAP_177___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_177__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_177__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_178 (0x00A442F4) +#define UMAC_TCL_R0_DSCP_TID_MAP_178___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_178__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_178__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_179 (0x00A442F8) +#define UMAC_TCL_R0_DSCP_TID_MAP_179___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_179__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_179__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_180 (0x00A442FC) +#define UMAC_TCL_R0_DSCP_TID_MAP_180___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_180__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_180__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_181 (0x00A44300) +#define UMAC_TCL_R0_DSCP_TID_MAP_181___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_181__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_181__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_182 (0x00A44304) +#define UMAC_TCL_R0_DSCP_TID_MAP_182___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_182__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_182__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_183 (0x00A44308) +#define UMAC_TCL_R0_DSCP_TID_MAP_183___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_183__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_183__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_184 (0x00A4430C) +#define UMAC_TCL_R0_DSCP_TID_MAP_184___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_184__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_184__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_185 (0x00A44310) +#define UMAC_TCL_R0_DSCP_TID_MAP_185___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_185__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_185__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_186 (0x00A44314) +#define UMAC_TCL_R0_DSCP_TID_MAP_186___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_186__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_186__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_187 (0x00A44318) +#define UMAC_TCL_R0_DSCP_TID_MAP_187___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_187__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_187__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_188 (0x00A4431C) +#define UMAC_TCL_R0_DSCP_TID_MAP_188___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_188__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_188__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_189 (0x00A44320) +#define UMAC_TCL_R0_DSCP_TID_MAP_189___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_189__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_189__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_190 (0x00A44324) +#define UMAC_TCL_R0_DSCP_TID_MAP_190___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_190__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_190__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_191 (0x00A44328) +#define UMAC_TCL_R0_DSCP_TID_MAP_191___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_191__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_191__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_192 (0x00A4432C) +#define UMAC_TCL_R0_DSCP_TID_MAP_192___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_192__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_192__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_193 (0x00A44330) +#define UMAC_TCL_R0_DSCP_TID_MAP_193___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_193__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_193__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_194 (0x00A44334) +#define UMAC_TCL_R0_DSCP_TID_MAP_194___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_194__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_194__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_195 (0x00A44338) +#define UMAC_TCL_R0_DSCP_TID_MAP_195___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_195__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_195__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_196 (0x00A4433C) +#define UMAC_TCL_R0_DSCP_TID_MAP_196___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_196__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_196__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_197 (0x00A44340) +#define UMAC_TCL_R0_DSCP_TID_MAP_197___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_197__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_197__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_198 (0x00A44344) +#define UMAC_TCL_R0_DSCP_TID_MAP_198___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_198__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_198__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_199 (0x00A44348) +#define UMAC_TCL_R0_DSCP_TID_MAP_199___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_199__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_199__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_200 (0x00A4434C) +#define UMAC_TCL_R0_DSCP_TID_MAP_200___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_200__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_200__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_201 (0x00A44350) +#define UMAC_TCL_R0_DSCP_TID_MAP_201___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_201__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_201__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_202 (0x00A44354) +#define UMAC_TCL_R0_DSCP_TID_MAP_202___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_202__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_202__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_203 (0x00A44358) +#define UMAC_TCL_R0_DSCP_TID_MAP_203___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_203__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_203__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_204 (0x00A4435C) +#define UMAC_TCL_R0_DSCP_TID_MAP_204___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_204__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_204__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_205 (0x00A44360) +#define UMAC_TCL_R0_DSCP_TID_MAP_205___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_205__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_205__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_206 (0x00A44364) +#define UMAC_TCL_R0_DSCP_TID_MAP_206___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_206__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_206__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_207 (0x00A44368) +#define UMAC_TCL_R0_DSCP_TID_MAP_207___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_207__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_207__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_208 (0x00A4436C) +#define UMAC_TCL_R0_DSCP_TID_MAP_208___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_208__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_208__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_209 (0x00A44370) +#define UMAC_TCL_R0_DSCP_TID_MAP_209___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_209__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_209__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_210 (0x00A44374) +#define UMAC_TCL_R0_DSCP_TID_MAP_210___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_210__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_210__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_211 (0x00A44378) +#define UMAC_TCL_R0_DSCP_TID_MAP_211___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_211__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_211__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_212 (0x00A4437C) +#define UMAC_TCL_R0_DSCP_TID_MAP_212___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_212__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_212__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_213 (0x00A44380) +#define UMAC_TCL_R0_DSCP_TID_MAP_213___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_213__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_213__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_214 (0x00A44384) +#define UMAC_TCL_R0_DSCP_TID_MAP_214___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_214__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_214__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_215 (0x00A44388) +#define UMAC_TCL_R0_DSCP_TID_MAP_215___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_215__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_215__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_216 (0x00A4438C) +#define UMAC_TCL_R0_DSCP_TID_MAP_216___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_216__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_216__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_217 (0x00A44390) +#define UMAC_TCL_R0_DSCP_TID_MAP_217___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_217__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_217__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_218 (0x00A44394) +#define UMAC_TCL_R0_DSCP_TID_MAP_218___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_218__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_218__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_219 (0x00A44398) +#define UMAC_TCL_R0_DSCP_TID_MAP_219___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_219__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_219__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_220 (0x00A4439C) +#define UMAC_TCL_R0_DSCP_TID_MAP_220___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_220__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_220__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_221 (0x00A443A0) +#define UMAC_TCL_R0_DSCP_TID_MAP_221___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_221__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_221__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_222 (0x00A443A4) +#define UMAC_TCL_R0_DSCP_TID_MAP_222___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_222__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_222__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_223 (0x00A443A8) +#define UMAC_TCL_R0_DSCP_TID_MAP_223___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_223__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_223__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_224 (0x00A443AC) +#define UMAC_TCL_R0_DSCP_TID_MAP_224___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_224__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_224__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_225 (0x00A443B0) +#define UMAC_TCL_R0_DSCP_TID_MAP_225___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_225__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_225__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_226 (0x00A443B4) +#define UMAC_TCL_R0_DSCP_TID_MAP_226___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_226__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_226__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_227 (0x00A443B8) +#define UMAC_TCL_R0_DSCP_TID_MAP_227___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_227__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_227__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_228 (0x00A443BC) +#define UMAC_TCL_R0_DSCP_TID_MAP_228___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_228__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_228__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_229 (0x00A443C0) +#define UMAC_TCL_R0_DSCP_TID_MAP_229___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_229__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_229__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_230 (0x00A443C4) +#define UMAC_TCL_R0_DSCP_TID_MAP_230___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_230__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_230__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_231 (0x00A443C8) +#define UMAC_TCL_R0_DSCP_TID_MAP_231___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_231__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_231__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_232 (0x00A443CC) +#define UMAC_TCL_R0_DSCP_TID_MAP_232___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_232__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_232__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_233 (0x00A443D0) +#define UMAC_TCL_R0_DSCP_TID_MAP_233___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_233__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_233__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_234 (0x00A443D4) +#define UMAC_TCL_R0_DSCP_TID_MAP_234___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_234__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_234__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_235 (0x00A443D8) +#define UMAC_TCL_R0_DSCP_TID_MAP_235___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_235__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_235__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_236 (0x00A443DC) +#define UMAC_TCL_R0_DSCP_TID_MAP_236___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_236__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_236__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_237 (0x00A443E0) +#define UMAC_TCL_R0_DSCP_TID_MAP_237___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_237__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_237__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_238 (0x00A443E4) +#define UMAC_TCL_R0_DSCP_TID_MAP_238___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_238__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_238__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_239 (0x00A443E8) +#define UMAC_TCL_R0_DSCP_TID_MAP_239___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_239__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_239__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_240 (0x00A443EC) +#define UMAC_TCL_R0_DSCP_TID_MAP_240___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_240__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_240__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_241 (0x00A443F0) +#define UMAC_TCL_R0_DSCP_TID_MAP_241___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_241__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_241__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_242 (0x00A443F4) +#define UMAC_TCL_R0_DSCP_TID_MAP_242___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_242__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_242__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_243 (0x00A443F8) +#define UMAC_TCL_R0_DSCP_TID_MAP_243___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_243__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_243__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_244 (0x00A443FC) +#define UMAC_TCL_R0_DSCP_TID_MAP_244___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_244__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_244__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_245 (0x00A44400) +#define UMAC_TCL_R0_DSCP_TID_MAP_245___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_245__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_245__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_246 (0x00A44404) +#define UMAC_TCL_R0_DSCP_TID_MAP_246___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_246__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_246__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_247 (0x00A44408) +#define UMAC_TCL_R0_DSCP_TID_MAP_247___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_247__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_247__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_248 (0x00A4440C) +#define UMAC_TCL_R0_DSCP_TID_MAP_248___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_248__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_248__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_249 (0x00A44410) +#define UMAC_TCL_R0_DSCP_TID_MAP_249___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_249__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_249__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_250 (0x00A44414) +#define UMAC_TCL_R0_DSCP_TID_MAP_250___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_250__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_250__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_251 (0x00A44418) +#define UMAC_TCL_R0_DSCP_TID_MAP_251___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_251__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_251__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_252 (0x00A4441C) +#define UMAC_TCL_R0_DSCP_TID_MAP_252___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_252__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_252__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_253 (0x00A44420) +#define UMAC_TCL_R0_DSCP_TID_MAP_253___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_253__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_253__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_254 (0x00A44424) +#define UMAC_TCL_R0_DSCP_TID_MAP_254___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_254__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_254__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_255 (0x00A44428) +#define UMAC_TCL_R0_DSCP_TID_MAP_255___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_255__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_255__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_256 (0x00A4442C) +#define UMAC_TCL_R0_DSCP_TID_MAP_256___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_256__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_256__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_257 (0x00A44430) +#define UMAC_TCL_R0_DSCP_TID_MAP_257___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_257__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_257__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_258 (0x00A44434) +#define UMAC_TCL_R0_DSCP_TID_MAP_258___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_258__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_258__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_259 (0x00A44438) +#define UMAC_TCL_R0_DSCP_TID_MAP_259___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_259__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_259__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_260 (0x00A4443C) +#define UMAC_TCL_R0_DSCP_TID_MAP_260___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_260__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_260__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_261 (0x00A44440) +#define UMAC_TCL_R0_DSCP_TID_MAP_261___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_261__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_261__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_262 (0x00A44444) +#define UMAC_TCL_R0_DSCP_TID_MAP_262___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_262__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_262__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_263 (0x00A44448) +#define UMAC_TCL_R0_DSCP_TID_MAP_263___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_263__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_263__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_264 (0x00A4444C) +#define UMAC_TCL_R0_DSCP_TID_MAP_264___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_264__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_264__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_265 (0x00A44450) +#define UMAC_TCL_R0_DSCP_TID_MAP_265___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_265__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_265__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_266 (0x00A44454) +#define UMAC_TCL_R0_DSCP_TID_MAP_266___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_266__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_266__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_267 (0x00A44458) +#define UMAC_TCL_R0_DSCP_TID_MAP_267___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_267__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_267__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_268 (0x00A4445C) +#define UMAC_TCL_R0_DSCP_TID_MAP_268___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_268__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_268__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_269 (0x00A44460) +#define UMAC_TCL_R0_DSCP_TID_MAP_269___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_269__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_269__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_270 (0x00A44464) +#define UMAC_TCL_R0_DSCP_TID_MAP_270___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_270__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_270__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_271 (0x00A44468) +#define UMAC_TCL_R0_DSCP_TID_MAP_271___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_271__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_271__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_272 (0x00A4446C) +#define UMAC_TCL_R0_DSCP_TID_MAP_272___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_272__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_272__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_273 (0x00A44470) +#define UMAC_TCL_R0_DSCP_TID_MAP_273___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_273__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_273__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_274 (0x00A44474) +#define UMAC_TCL_R0_DSCP_TID_MAP_274___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_274__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_274__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_275 (0x00A44478) +#define UMAC_TCL_R0_DSCP_TID_MAP_275___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_275__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_275__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_276 (0x00A4447C) +#define UMAC_TCL_R0_DSCP_TID_MAP_276___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_276__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_276__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_277 (0x00A44480) +#define UMAC_TCL_R0_DSCP_TID_MAP_277___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_277__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_277__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_278 (0x00A44484) +#define UMAC_TCL_R0_DSCP_TID_MAP_278___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_278__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_278__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_279 (0x00A44488) +#define UMAC_TCL_R0_DSCP_TID_MAP_279___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_279__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_279__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_280 (0x00A4448C) +#define UMAC_TCL_R0_DSCP_TID_MAP_280___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_280__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_280__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_281 (0x00A44490) +#define UMAC_TCL_R0_DSCP_TID_MAP_281___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_281__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_281__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_282 (0x00A44494) +#define UMAC_TCL_R0_DSCP_TID_MAP_282___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_282__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_282__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_283 (0x00A44498) +#define UMAC_TCL_R0_DSCP_TID_MAP_283___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_283__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_283__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_284 (0x00A4449C) +#define UMAC_TCL_R0_DSCP_TID_MAP_284___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_284__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_284__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_285 (0x00A444A0) +#define UMAC_TCL_R0_DSCP_TID_MAP_285___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_285__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_285__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_286 (0x00A444A4) +#define UMAC_TCL_R0_DSCP_TID_MAP_286___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_286__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_286__VAL___S 0 +#define UMAC_TCL_R0_DSCP_TID_MAP_287 (0x00A444A8) +#define UMAC_TCL_R0_DSCP_TID_MAP_287___RWC QCSR_REG_RW +#define UMAC_TCL_R0_DSCP_TID_MAP_287__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_DSCP_TID_MAP_287__VAL___S 0 + +#define UMAC_TCL_R0_PCP_TID_MAP (0x00A444AC) +#define UMAC_TCL_R0_PCP_TID_MAP___RWC QCSR_REG_RW +#define UMAC_TCL_R0_PCP_TID_MAP___POR 0x00000000 +#define UMAC_TCL_R0_PCP_TID_MAP__PCP_7___POR 0x0 +#define UMAC_TCL_R0_PCP_TID_MAP__PCP_6___POR 0x0 +#define UMAC_TCL_R0_PCP_TID_MAP__PCP_5___POR 0x0 +#define UMAC_TCL_R0_PCP_TID_MAP__PCP_4___POR 0x0 +#define UMAC_TCL_R0_PCP_TID_MAP__PCP_3___POR 0x0 +#define UMAC_TCL_R0_PCP_TID_MAP__PCP_2___POR 0x0 +#define UMAC_TCL_R0_PCP_TID_MAP__PCP_1___POR 0x0 +#define UMAC_TCL_R0_PCP_TID_MAP__PCP_0___POR 0x0 +#define UMAC_TCL_R0_PCP_TID_MAP__PCP_7___M 0x00E00000 +#define UMAC_TCL_R0_PCP_TID_MAP__PCP_7___S 21 +#define UMAC_TCL_R0_PCP_TID_MAP__PCP_6___M 0x001C0000 +#define UMAC_TCL_R0_PCP_TID_MAP__PCP_6___S 18 +#define UMAC_TCL_R0_PCP_TID_MAP__PCP_5___M 0x00038000 +#define UMAC_TCL_R0_PCP_TID_MAP__PCP_5___S 15 +#define UMAC_TCL_R0_PCP_TID_MAP__PCP_4___M 0x00007000 +#define UMAC_TCL_R0_PCP_TID_MAP__PCP_4___S 12 +#define UMAC_TCL_R0_PCP_TID_MAP__PCP_3___M 0x00000E00 +#define UMAC_TCL_R0_PCP_TID_MAP__PCP_3___S 9 +#define UMAC_TCL_R0_PCP_TID_MAP__PCP_2___M 0x000001C0 +#define UMAC_TCL_R0_PCP_TID_MAP__PCP_2___S 6 +#define UMAC_TCL_R0_PCP_TID_MAP__PCP_1___M 0x00000038 +#define UMAC_TCL_R0_PCP_TID_MAP__PCP_1___S 3 +#define UMAC_TCL_R0_PCP_TID_MAP__PCP_0___M 0x00000007 +#define UMAC_TCL_R0_PCP_TID_MAP__PCP_0___S 0 +#define UMAC_TCL_R0_PCP_TID_MAP___M 0x00FFFFFF +#define UMAC_TCL_R0_PCP_TID_MAP___S 0 + +#define UMAC_TCL_R0_ASE_HASH_KEY_31_0 (0x00A444B0) +#define UMAC_TCL_R0_ASE_HASH_KEY_31_0___RWC QCSR_REG_RW +#define UMAC_TCL_R0_ASE_HASH_KEY_31_0___POR 0x00000000 +#define UMAC_TCL_R0_ASE_HASH_KEY_31_0__VAL___POR 0x00000000 +#define UMAC_TCL_R0_ASE_HASH_KEY_31_0__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_ASE_HASH_KEY_31_0__VAL___S 0 +#define UMAC_TCL_R0_ASE_HASH_KEY_31_0___M 0xFFFFFFFF +#define UMAC_TCL_R0_ASE_HASH_KEY_31_0___S 0 + +#define UMAC_TCL_R0_ASE_HASH_KEY_63_32 (0x00A444B4) +#define UMAC_TCL_R0_ASE_HASH_KEY_63_32___RWC QCSR_REG_RW +#define UMAC_TCL_R0_ASE_HASH_KEY_63_32___POR 0x00000000 +#define UMAC_TCL_R0_ASE_HASH_KEY_63_32__VAL___POR 0x00000000 +#define UMAC_TCL_R0_ASE_HASH_KEY_63_32__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_ASE_HASH_KEY_63_32__VAL___S 0 +#define UMAC_TCL_R0_ASE_HASH_KEY_63_32___M 0xFFFFFFFF +#define UMAC_TCL_R0_ASE_HASH_KEY_63_32___S 0 + +#define UMAC_TCL_R0_ASE_HASH_KEY_64 (0x00A444B8) +#define UMAC_TCL_R0_ASE_HASH_KEY_64___RWC QCSR_REG_RW +#define UMAC_TCL_R0_ASE_HASH_KEY_64___POR 0x00000000 +#define UMAC_TCL_R0_ASE_HASH_KEY_64__VAL___POR 0x0 +#define UMAC_TCL_R0_ASE_HASH_KEY_64__VAL___M 0x00000001 +#define UMAC_TCL_R0_ASE_HASH_KEY_64__VAL___S 0 +#define UMAC_TCL_R0_ASE_HASH_KEY_64___M 0x00000001 +#define UMAC_TCL_R0_ASE_HASH_KEY_64___S 0 + +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE (0x00A444BC) +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE___RWC QCSR_REG_RW +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE___POR 0x00840014 +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__MSDU_LEN_ERR_TO_FW_EN___POR 0x1 +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__FSE_M0_FW_SEL___POR 0x0 +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__ASE_M0_FW_SEL___POR 0x2 +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__CCE_M0_FW_SEL___POR 0x0 +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__CCE_FAIL_DROP___POR 0x0 +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__FSE_FAIL_DROP___POR 0x0 +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__CCE_FAIL_LOOP___POR 0x0 +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__FSE_FAIL_LOOP___POR 0x0 +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__PRIORITY___POR 0x0 +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__CCE_FAIL_HANDLER___POR 0x1 +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__FSE_FAIL_HANDLER___POR 0x1 +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__MSDU_LEN_ERR_TO_FW_EN___M 0x00800000 +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__MSDU_LEN_ERR_TO_FW_EN___S 23 +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__FSE_M0_FW_SEL___M 0x00700000 +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__FSE_M0_FW_SEL___S 20 +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__ASE_M0_FW_SEL___M 0x000E0000 +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__ASE_M0_FW_SEL___S 17 +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__CCE_M0_FW_SEL___M 0x0001C000 +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__CCE_M0_FW_SEL___S 14 +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__CCE_FAIL_DROP___M 0x00002000 +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__CCE_FAIL_DROP___S 13 +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__FSE_FAIL_DROP___M 0x00001000 +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__FSE_FAIL_DROP___S 12 +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__CCE_FAIL_LOOP___M 0x00000800 +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__CCE_FAIL_LOOP___S 11 +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__FSE_FAIL_LOOP___M 0x00000400 +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__FSE_FAIL_LOOP___S 10 +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__PRIORITY___M 0x000001C0 +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__PRIORITY___S 6 +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__CCE_FAIL_HANDLER___M 0x00000030 +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__CCE_FAIL_HANDLER___S 4 +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__FSE_FAIL_HANDLER___M 0x0000000C +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE__FSE_FAIL_HANDLER___S 2 +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE___M 0x00FFFDFC +#define UMAC_TCL_R0_CONFIG_SEARCH_QUEUE___S 2 + +#define UMAC_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW (0x00A444C0) +#define UMAC_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW___RWC QCSR_REG_RW +#define UMAC_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW___POR 0x00000000 +#define UMAC_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW__VAL___POR 0x00000000 +#define UMAC_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW__VAL___S 0 +#define UMAC_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW___M 0xFFFFFFFF +#define UMAC_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW___S 0 + +#define UMAC_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH (0x00A444C4) +#define UMAC_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH___RWC QCSR_REG_RW +#define UMAC_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH___POR 0x00000000 +#define UMAC_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH__VAL___POR 0x00 +#define UMAC_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH__VAL___M 0x000000FF +#define UMAC_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH__VAL___S 0 +#define UMAC_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH___M 0x000000FF +#define UMAC_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH___S 0 + +#define UMAC_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW (0x00A444C8) +#define UMAC_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW___RWC QCSR_REG_RW +#define UMAC_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW___POR 0x00000000 +#define UMAC_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW__VAL___POR 0x00000000 +#define UMAC_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW__VAL___S 0 +#define UMAC_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW___M 0xFFFFFFFF +#define UMAC_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW___S 0 + +#define UMAC_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH (0x00A444CC) +#define UMAC_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH___RWC QCSR_REG_RW +#define UMAC_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH___POR 0x00000000 +#define UMAC_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH__VAL___POR 0x00 +#define UMAC_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH__VAL___M 0x000000FF +#define UMAC_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH__VAL___S 0 +#define UMAC_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH___M 0x000000FF +#define UMAC_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH___S 0 + +#define UMAC_TCL_R0_CONFIG_SEARCH_METADATA (0x00A444D0) +#define UMAC_TCL_R0_CONFIG_SEARCH_METADATA___RWC QCSR_REG_RW +#define UMAC_TCL_R0_CONFIG_SEARCH_METADATA___POR 0x00000000 +#define UMAC_TCL_R0_CONFIG_SEARCH_METADATA__FSE_FAIL_NUM___POR 0x0000 +#define UMAC_TCL_R0_CONFIG_SEARCH_METADATA__CCE_FAIL_NUM___POR 0x0000 +#define UMAC_TCL_R0_CONFIG_SEARCH_METADATA__FSE_FAIL_NUM___M 0xFFFF0000 +#define UMAC_TCL_R0_CONFIG_SEARCH_METADATA__FSE_FAIL_NUM___S 16 +#define UMAC_TCL_R0_CONFIG_SEARCH_METADATA__CCE_FAIL_NUM___M 0x0000FFFF +#define UMAC_TCL_R0_CONFIG_SEARCH_METADATA__CCE_FAIL_NUM___S 0 +#define UMAC_TCL_R0_CONFIG_SEARCH_METADATA___M 0xFFFFFFFF +#define UMAC_TCL_R0_CONFIG_SEARCH_METADATA___S 0 + +#define UMAC_TCL_R0_TID_MAP_PRTY (0x00A444D4) +#define UMAC_TCL_R0_TID_MAP_PRTY___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TID_MAP_PRTY___POR 0x00000000 +#define UMAC_TCL_R0_TID_MAP_PRTY__TID_DEF___POR 0x0 +#define UMAC_TCL_R0_TID_MAP_PRTY__VAL___POR 0x0 +#define UMAC_TCL_R0_TID_MAP_PRTY__TID_DEF___M 0x000000E0 +#define UMAC_TCL_R0_TID_MAP_PRTY__TID_DEF___S 5 +#define UMAC_TCL_R0_TID_MAP_PRTY__VAL___M 0x0000000F +#define UMAC_TCL_R0_TID_MAP_PRTY__VAL___S 0 +#define UMAC_TCL_R0_TID_MAP_PRTY___M 0x000000EF +#define UMAC_TCL_R0_TID_MAP_PRTY___S 0 + +#define UMAC_TCL_R0_INVALID_APB_ACC_ADDR (0x00A444D8) +#define UMAC_TCL_R0_INVALID_APB_ACC_ADDR___RWC QCSR_REG_RO +#define UMAC_TCL_R0_INVALID_APB_ACC_ADDR___POR 0x00000000 +#define UMAC_TCL_R0_INVALID_APB_ACC_ADDR__VAL___POR 0x00000000 +#define UMAC_TCL_R0_INVALID_APB_ACC_ADDR__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_INVALID_APB_ACC_ADDR__VAL___S 0 +#define UMAC_TCL_R0_INVALID_APB_ACC_ADDR___M 0xFFFFFFFF +#define UMAC_TCL_R0_INVALID_APB_ACC_ADDR___S 0 + +#define UMAC_TCL_R0_WATCHDOG (0x00A444DC) +#define UMAC_TCL_R0_WATCHDOG___RWC QCSR_REG_RW +#define UMAC_TCL_R0_WATCHDOG___POR 0x0000FFFF +#define UMAC_TCL_R0_WATCHDOG__STATUS___POR 0x0000 +#define UMAC_TCL_R0_WATCHDOG__LIMIT___POR 0xFFFF +#define UMAC_TCL_R0_WATCHDOG__STATUS___M 0xFFFF0000 +#define UMAC_TCL_R0_WATCHDOG__STATUS___S 16 +#define UMAC_TCL_R0_WATCHDOG__LIMIT___M 0x0000FFFF +#define UMAC_TCL_R0_WATCHDOG__LIMIT___S 0 +#define UMAC_TCL_R0_WATCHDOG___M 0xFFFFFFFF +#define UMAC_TCL_R0_WATCHDOG___S 0 + +#define UMAC_TCL_R0_LCE_RULE_n(n) (0x00A444E0+0x4*(n)) +#define UMAC_TCL_R0_LCE_RULE_n_nMIN 0 +#define UMAC_TCL_R0_LCE_RULE_n_nMAX 25 +#define UMAC_TCL_R0_LCE_RULE_n_ELEM 26 +#define UMAC_TCL_R0_LCE_RULE_n___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_RULE_n___POR 0x00000000 +#define UMAC_TCL_R0_LCE_RULE_n__MATCH_IP_PROT___POR 0x0 +#define UMAC_TCL_R0_LCE_RULE_n__MATCH_DEST_ADDR_BIT_0___POR 0x0 +#define UMAC_TCL_R0_LCE_RULE_n__TCP_OR_UDP___POR 0x0 +#define UMAC_TCL_R0_LCE_RULE_n__MATCH_DEST_PORT___POR 0x0 +#define UMAC_TCL_R0_LCE_RULE_n__MATCH_SRC_PORT___POR 0x0 +#define UMAC_TCL_R0_LCE_RULE_n__MATCH_L3_TYPE___POR 0x0 +#define UMAC_TCL_R0_LCE_RULE_n__MATCH_VAL___POR 0x0000 +#define UMAC_TCL_R0_LCE_RULE_n__MATCH_IP_PROT___M 0x00400000 +#define UMAC_TCL_R0_LCE_RULE_n__MATCH_IP_PROT___S 22 +#define UMAC_TCL_R0_LCE_RULE_n__MATCH_DEST_ADDR_BIT_0___M 0x00200000 +#define UMAC_TCL_R0_LCE_RULE_n__MATCH_DEST_ADDR_BIT_0___S 21 +#define UMAC_TCL_R0_LCE_RULE_n__TCP_OR_UDP___M 0x00180000 +#define UMAC_TCL_R0_LCE_RULE_n__TCP_OR_UDP___S 19 +#define UMAC_TCL_R0_LCE_RULE_n__MATCH_DEST_PORT___M 0x00040000 +#define UMAC_TCL_R0_LCE_RULE_n__MATCH_DEST_PORT___S 18 +#define UMAC_TCL_R0_LCE_RULE_n__MATCH_SRC_PORT___M 0x00020000 +#define UMAC_TCL_R0_LCE_RULE_n__MATCH_SRC_PORT___S 17 +#define UMAC_TCL_R0_LCE_RULE_n__MATCH_L3_TYPE___M 0x00010000 +#define UMAC_TCL_R0_LCE_RULE_n__MATCH_L3_TYPE___S 16 +#define UMAC_TCL_R0_LCE_RULE_n__MATCH_VAL___M 0x0000FFFF +#define UMAC_TCL_R0_LCE_RULE_n__MATCH_VAL___S 0 +#define UMAC_TCL_R0_LCE_RULE_n___M 0x007FFFFF +#define UMAC_TCL_R0_LCE_RULE_n___S 0 +#define UMAC_TCL_R0_LCE_RULE_0 (0x00A444E0) +#define UMAC_TCL_R0_LCE_RULE_0___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_RULE_0__MATCH_IP_PROT___M 0x00400000 +#define UMAC_TCL_R0_LCE_RULE_0__MATCH_IP_PROT___S 22 +#define UMAC_TCL_R0_LCE_RULE_0__MATCH_DEST_ADDR_BIT_0___M 0x00200000 +#define UMAC_TCL_R0_LCE_RULE_0__MATCH_DEST_ADDR_BIT_0___S 21 +#define UMAC_TCL_R0_LCE_RULE_0__TCP_OR_UDP___M 0x00180000 +#define UMAC_TCL_R0_LCE_RULE_0__TCP_OR_UDP___S 19 +#define UMAC_TCL_R0_LCE_RULE_0__MATCH_DEST_PORT___M 0x00040000 +#define UMAC_TCL_R0_LCE_RULE_0__MATCH_DEST_PORT___S 18 +#define UMAC_TCL_R0_LCE_RULE_0__MATCH_SRC_PORT___M 0x00020000 +#define UMAC_TCL_R0_LCE_RULE_0__MATCH_SRC_PORT___S 17 +#define UMAC_TCL_R0_LCE_RULE_0__MATCH_L3_TYPE___M 0x00010000 +#define UMAC_TCL_R0_LCE_RULE_0__MATCH_L3_TYPE___S 16 +#define UMAC_TCL_R0_LCE_RULE_0__MATCH_VAL___M 0x0000FFFF +#define UMAC_TCL_R0_LCE_RULE_0__MATCH_VAL___S 0 +#define UMAC_TCL_R0_LCE_RULE_1 (0x00A444E4) +#define UMAC_TCL_R0_LCE_RULE_1___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_RULE_1__MATCH_IP_PROT___M 0x00400000 +#define UMAC_TCL_R0_LCE_RULE_1__MATCH_IP_PROT___S 22 +#define UMAC_TCL_R0_LCE_RULE_1__MATCH_DEST_ADDR_BIT_0___M 0x00200000 +#define UMAC_TCL_R0_LCE_RULE_1__MATCH_DEST_ADDR_BIT_0___S 21 +#define UMAC_TCL_R0_LCE_RULE_1__TCP_OR_UDP___M 0x00180000 +#define UMAC_TCL_R0_LCE_RULE_1__TCP_OR_UDP___S 19 +#define UMAC_TCL_R0_LCE_RULE_1__MATCH_DEST_PORT___M 0x00040000 +#define UMAC_TCL_R0_LCE_RULE_1__MATCH_DEST_PORT___S 18 +#define UMAC_TCL_R0_LCE_RULE_1__MATCH_SRC_PORT___M 0x00020000 +#define UMAC_TCL_R0_LCE_RULE_1__MATCH_SRC_PORT___S 17 +#define UMAC_TCL_R0_LCE_RULE_1__MATCH_L3_TYPE___M 0x00010000 +#define UMAC_TCL_R0_LCE_RULE_1__MATCH_L3_TYPE___S 16 +#define UMAC_TCL_R0_LCE_RULE_1__MATCH_VAL___M 0x0000FFFF +#define UMAC_TCL_R0_LCE_RULE_1__MATCH_VAL___S 0 +#define UMAC_TCL_R0_LCE_RULE_2 (0x00A444E8) +#define UMAC_TCL_R0_LCE_RULE_2___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_RULE_2__MATCH_IP_PROT___M 0x00400000 +#define UMAC_TCL_R0_LCE_RULE_2__MATCH_IP_PROT___S 22 +#define UMAC_TCL_R0_LCE_RULE_2__MATCH_DEST_ADDR_BIT_0___M 0x00200000 +#define UMAC_TCL_R0_LCE_RULE_2__MATCH_DEST_ADDR_BIT_0___S 21 +#define UMAC_TCL_R0_LCE_RULE_2__TCP_OR_UDP___M 0x00180000 +#define UMAC_TCL_R0_LCE_RULE_2__TCP_OR_UDP___S 19 +#define UMAC_TCL_R0_LCE_RULE_2__MATCH_DEST_PORT___M 0x00040000 +#define UMAC_TCL_R0_LCE_RULE_2__MATCH_DEST_PORT___S 18 +#define UMAC_TCL_R0_LCE_RULE_2__MATCH_SRC_PORT___M 0x00020000 +#define UMAC_TCL_R0_LCE_RULE_2__MATCH_SRC_PORT___S 17 +#define UMAC_TCL_R0_LCE_RULE_2__MATCH_L3_TYPE___M 0x00010000 +#define UMAC_TCL_R0_LCE_RULE_2__MATCH_L3_TYPE___S 16 +#define UMAC_TCL_R0_LCE_RULE_2__MATCH_VAL___M 0x0000FFFF +#define UMAC_TCL_R0_LCE_RULE_2__MATCH_VAL___S 0 +#define UMAC_TCL_R0_LCE_RULE_3 (0x00A444EC) +#define UMAC_TCL_R0_LCE_RULE_3___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_RULE_3__MATCH_IP_PROT___M 0x00400000 +#define UMAC_TCL_R0_LCE_RULE_3__MATCH_IP_PROT___S 22 +#define UMAC_TCL_R0_LCE_RULE_3__MATCH_DEST_ADDR_BIT_0___M 0x00200000 +#define UMAC_TCL_R0_LCE_RULE_3__MATCH_DEST_ADDR_BIT_0___S 21 +#define UMAC_TCL_R0_LCE_RULE_3__TCP_OR_UDP___M 0x00180000 +#define UMAC_TCL_R0_LCE_RULE_3__TCP_OR_UDP___S 19 +#define UMAC_TCL_R0_LCE_RULE_3__MATCH_DEST_PORT___M 0x00040000 +#define UMAC_TCL_R0_LCE_RULE_3__MATCH_DEST_PORT___S 18 +#define UMAC_TCL_R0_LCE_RULE_3__MATCH_SRC_PORT___M 0x00020000 +#define UMAC_TCL_R0_LCE_RULE_3__MATCH_SRC_PORT___S 17 +#define UMAC_TCL_R0_LCE_RULE_3__MATCH_L3_TYPE___M 0x00010000 +#define UMAC_TCL_R0_LCE_RULE_3__MATCH_L3_TYPE___S 16 +#define UMAC_TCL_R0_LCE_RULE_3__MATCH_VAL___M 0x0000FFFF +#define UMAC_TCL_R0_LCE_RULE_3__MATCH_VAL___S 0 +#define UMAC_TCL_R0_LCE_RULE_4 (0x00A444F0) +#define UMAC_TCL_R0_LCE_RULE_4___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_RULE_4__MATCH_IP_PROT___M 0x00400000 +#define UMAC_TCL_R0_LCE_RULE_4__MATCH_IP_PROT___S 22 +#define UMAC_TCL_R0_LCE_RULE_4__MATCH_DEST_ADDR_BIT_0___M 0x00200000 +#define UMAC_TCL_R0_LCE_RULE_4__MATCH_DEST_ADDR_BIT_0___S 21 +#define UMAC_TCL_R0_LCE_RULE_4__TCP_OR_UDP___M 0x00180000 +#define UMAC_TCL_R0_LCE_RULE_4__TCP_OR_UDP___S 19 +#define UMAC_TCL_R0_LCE_RULE_4__MATCH_DEST_PORT___M 0x00040000 +#define UMAC_TCL_R0_LCE_RULE_4__MATCH_DEST_PORT___S 18 +#define UMAC_TCL_R0_LCE_RULE_4__MATCH_SRC_PORT___M 0x00020000 +#define UMAC_TCL_R0_LCE_RULE_4__MATCH_SRC_PORT___S 17 +#define UMAC_TCL_R0_LCE_RULE_4__MATCH_L3_TYPE___M 0x00010000 +#define UMAC_TCL_R0_LCE_RULE_4__MATCH_L3_TYPE___S 16 +#define UMAC_TCL_R0_LCE_RULE_4__MATCH_VAL___M 0x0000FFFF +#define UMAC_TCL_R0_LCE_RULE_4__MATCH_VAL___S 0 +#define UMAC_TCL_R0_LCE_RULE_5 (0x00A444F4) +#define UMAC_TCL_R0_LCE_RULE_5___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_RULE_5__MATCH_IP_PROT___M 0x00400000 +#define UMAC_TCL_R0_LCE_RULE_5__MATCH_IP_PROT___S 22 +#define UMAC_TCL_R0_LCE_RULE_5__MATCH_DEST_ADDR_BIT_0___M 0x00200000 +#define UMAC_TCL_R0_LCE_RULE_5__MATCH_DEST_ADDR_BIT_0___S 21 +#define UMAC_TCL_R0_LCE_RULE_5__TCP_OR_UDP___M 0x00180000 +#define UMAC_TCL_R0_LCE_RULE_5__TCP_OR_UDP___S 19 +#define UMAC_TCL_R0_LCE_RULE_5__MATCH_DEST_PORT___M 0x00040000 +#define UMAC_TCL_R0_LCE_RULE_5__MATCH_DEST_PORT___S 18 +#define UMAC_TCL_R0_LCE_RULE_5__MATCH_SRC_PORT___M 0x00020000 +#define UMAC_TCL_R0_LCE_RULE_5__MATCH_SRC_PORT___S 17 +#define UMAC_TCL_R0_LCE_RULE_5__MATCH_L3_TYPE___M 0x00010000 +#define UMAC_TCL_R0_LCE_RULE_5__MATCH_L3_TYPE___S 16 +#define UMAC_TCL_R0_LCE_RULE_5__MATCH_VAL___M 0x0000FFFF +#define UMAC_TCL_R0_LCE_RULE_5__MATCH_VAL___S 0 +#define UMAC_TCL_R0_LCE_RULE_6 (0x00A444F8) +#define UMAC_TCL_R0_LCE_RULE_6___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_RULE_6__MATCH_IP_PROT___M 0x00400000 +#define UMAC_TCL_R0_LCE_RULE_6__MATCH_IP_PROT___S 22 +#define UMAC_TCL_R0_LCE_RULE_6__MATCH_DEST_ADDR_BIT_0___M 0x00200000 +#define UMAC_TCL_R0_LCE_RULE_6__MATCH_DEST_ADDR_BIT_0___S 21 +#define UMAC_TCL_R0_LCE_RULE_6__TCP_OR_UDP___M 0x00180000 +#define UMAC_TCL_R0_LCE_RULE_6__TCP_OR_UDP___S 19 +#define UMAC_TCL_R0_LCE_RULE_6__MATCH_DEST_PORT___M 0x00040000 +#define UMAC_TCL_R0_LCE_RULE_6__MATCH_DEST_PORT___S 18 +#define UMAC_TCL_R0_LCE_RULE_6__MATCH_SRC_PORT___M 0x00020000 +#define UMAC_TCL_R0_LCE_RULE_6__MATCH_SRC_PORT___S 17 +#define UMAC_TCL_R0_LCE_RULE_6__MATCH_L3_TYPE___M 0x00010000 +#define UMAC_TCL_R0_LCE_RULE_6__MATCH_L3_TYPE___S 16 +#define UMAC_TCL_R0_LCE_RULE_6__MATCH_VAL___M 0x0000FFFF +#define UMAC_TCL_R0_LCE_RULE_6__MATCH_VAL___S 0 +#define UMAC_TCL_R0_LCE_RULE_7 (0x00A444FC) +#define UMAC_TCL_R0_LCE_RULE_7___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_RULE_7__MATCH_IP_PROT___M 0x00400000 +#define UMAC_TCL_R0_LCE_RULE_7__MATCH_IP_PROT___S 22 +#define UMAC_TCL_R0_LCE_RULE_7__MATCH_DEST_ADDR_BIT_0___M 0x00200000 +#define UMAC_TCL_R0_LCE_RULE_7__MATCH_DEST_ADDR_BIT_0___S 21 +#define UMAC_TCL_R0_LCE_RULE_7__TCP_OR_UDP___M 0x00180000 +#define UMAC_TCL_R0_LCE_RULE_7__TCP_OR_UDP___S 19 +#define UMAC_TCL_R0_LCE_RULE_7__MATCH_DEST_PORT___M 0x00040000 +#define UMAC_TCL_R0_LCE_RULE_7__MATCH_DEST_PORT___S 18 +#define UMAC_TCL_R0_LCE_RULE_7__MATCH_SRC_PORT___M 0x00020000 +#define UMAC_TCL_R0_LCE_RULE_7__MATCH_SRC_PORT___S 17 +#define UMAC_TCL_R0_LCE_RULE_7__MATCH_L3_TYPE___M 0x00010000 +#define UMAC_TCL_R0_LCE_RULE_7__MATCH_L3_TYPE___S 16 +#define UMAC_TCL_R0_LCE_RULE_7__MATCH_VAL___M 0x0000FFFF +#define UMAC_TCL_R0_LCE_RULE_7__MATCH_VAL___S 0 +#define UMAC_TCL_R0_LCE_RULE_8 (0x00A44500) +#define UMAC_TCL_R0_LCE_RULE_8___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_RULE_8__MATCH_IP_PROT___M 0x00400000 +#define UMAC_TCL_R0_LCE_RULE_8__MATCH_IP_PROT___S 22 +#define UMAC_TCL_R0_LCE_RULE_8__MATCH_DEST_ADDR_BIT_0___M 0x00200000 +#define UMAC_TCL_R0_LCE_RULE_8__MATCH_DEST_ADDR_BIT_0___S 21 +#define UMAC_TCL_R0_LCE_RULE_8__TCP_OR_UDP___M 0x00180000 +#define UMAC_TCL_R0_LCE_RULE_8__TCP_OR_UDP___S 19 +#define UMAC_TCL_R0_LCE_RULE_8__MATCH_DEST_PORT___M 0x00040000 +#define UMAC_TCL_R0_LCE_RULE_8__MATCH_DEST_PORT___S 18 +#define UMAC_TCL_R0_LCE_RULE_8__MATCH_SRC_PORT___M 0x00020000 +#define UMAC_TCL_R0_LCE_RULE_8__MATCH_SRC_PORT___S 17 +#define UMAC_TCL_R0_LCE_RULE_8__MATCH_L3_TYPE___M 0x00010000 +#define UMAC_TCL_R0_LCE_RULE_8__MATCH_L3_TYPE___S 16 +#define UMAC_TCL_R0_LCE_RULE_8__MATCH_VAL___M 0x0000FFFF +#define UMAC_TCL_R0_LCE_RULE_8__MATCH_VAL___S 0 +#define UMAC_TCL_R0_LCE_RULE_9 (0x00A44504) +#define UMAC_TCL_R0_LCE_RULE_9___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_RULE_9__MATCH_IP_PROT___M 0x00400000 +#define UMAC_TCL_R0_LCE_RULE_9__MATCH_IP_PROT___S 22 +#define UMAC_TCL_R0_LCE_RULE_9__MATCH_DEST_ADDR_BIT_0___M 0x00200000 +#define UMAC_TCL_R0_LCE_RULE_9__MATCH_DEST_ADDR_BIT_0___S 21 +#define UMAC_TCL_R0_LCE_RULE_9__TCP_OR_UDP___M 0x00180000 +#define UMAC_TCL_R0_LCE_RULE_9__TCP_OR_UDP___S 19 +#define UMAC_TCL_R0_LCE_RULE_9__MATCH_DEST_PORT___M 0x00040000 +#define UMAC_TCL_R0_LCE_RULE_9__MATCH_DEST_PORT___S 18 +#define UMAC_TCL_R0_LCE_RULE_9__MATCH_SRC_PORT___M 0x00020000 +#define UMAC_TCL_R0_LCE_RULE_9__MATCH_SRC_PORT___S 17 +#define UMAC_TCL_R0_LCE_RULE_9__MATCH_L3_TYPE___M 0x00010000 +#define UMAC_TCL_R0_LCE_RULE_9__MATCH_L3_TYPE___S 16 +#define UMAC_TCL_R0_LCE_RULE_9__MATCH_VAL___M 0x0000FFFF +#define UMAC_TCL_R0_LCE_RULE_9__MATCH_VAL___S 0 +#define UMAC_TCL_R0_LCE_RULE_10 (0x00A44508) +#define UMAC_TCL_R0_LCE_RULE_10___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_RULE_10__MATCH_IP_PROT___M 0x00400000 +#define UMAC_TCL_R0_LCE_RULE_10__MATCH_IP_PROT___S 22 +#define UMAC_TCL_R0_LCE_RULE_10__MATCH_DEST_ADDR_BIT_0___M 0x00200000 +#define UMAC_TCL_R0_LCE_RULE_10__MATCH_DEST_ADDR_BIT_0___S 21 +#define UMAC_TCL_R0_LCE_RULE_10__TCP_OR_UDP___M 0x00180000 +#define UMAC_TCL_R0_LCE_RULE_10__TCP_OR_UDP___S 19 +#define UMAC_TCL_R0_LCE_RULE_10__MATCH_DEST_PORT___M 0x00040000 +#define UMAC_TCL_R0_LCE_RULE_10__MATCH_DEST_PORT___S 18 +#define UMAC_TCL_R0_LCE_RULE_10__MATCH_SRC_PORT___M 0x00020000 +#define UMAC_TCL_R0_LCE_RULE_10__MATCH_SRC_PORT___S 17 +#define UMAC_TCL_R0_LCE_RULE_10__MATCH_L3_TYPE___M 0x00010000 +#define UMAC_TCL_R0_LCE_RULE_10__MATCH_L3_TYPE___S 16 +#define UMAC_TCL_R0_LCE_RULE_10__MATCH_VAL___M 0x0000FFFF +#define UMAC_TCL_R0_LCE_RULE_10__MATCH_VAL___S 0 +#define UMAC_TCL_R0_LCE_RULE_11 (0x00A4450C) +#define UMAC_TCL_R0_LCE_RULE_11___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_RULE_11__MATCH_IP_PROT___M 0x00400000 +#define UMAC_TCL_R0_LCE_RULE_11__MATCH_IP_PROT___S 22 +#define UMAC_TCL_R0_LCE_RULE_11__MATCH_DEST_ADDR_BIT_0___M 0x00200000 +#define UMAC_TCL_R0_LCE_RULE_11__MATCH_DEST_ADDR_BIT_0___S 21 +#define UMAC_TCL_R0_LCE_RULE_11__TCP_OR_UDP___M 0x00180000 +#define UMAC_TCL_R0_LCE_RULE_11__TCP_OR_UDP___S 19 +#define UMAC_TCL_R0_LCE_RULE_11__MATCH_DEST_PORT___M 0x00040000 +#define UMAC_TCL_R0_LCE_RULE_11__MATCH_DEST_PORT___S 18 +#define UMAC_TCL_R0_LCE_RULE_11__MATCH_SRC_PORT___M 0x00020000 +#define UMAC_TCL_R0_LCE_RULE_11__MATCH_SRC_PORT___S 17 +#define UMAC_TCL_R0_LCE_RULE_11__MATCH_L3_TYPE___M 0x00010000 +#define UMAC_TCL_R0_LCE_RULE_11__MATCH_L3_TYPE___S 16 +#define UMAC_TCL_R0_LCE_RULE_11__MATCH_VAL___M 0x0000FFFF +#define UMAC_TCL_R0_LCE_RULE_11__MATCH_VAL___S 0 +#define UMAC_TCL_R0_LCE_RULE_12 (0x00A44510) +#define UMAC_TCL_R0_LCE_RULE_12___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_RULE_12__MATCH_IP_PROT___M 0x00400000 +#define UMAC_TCL_R0_LCE_RULE_12__MATCH_IP_PROT___S 22 +#define UMAC_TCL_R0_LCE_RULE_12__MATCH_DEST_ADDR_BIT_0___M 0x00200000 +#define UMAC_TCL_R0_LCE_RULE_12__MATCH_DEST_ADDR_BIT_0___S 21 +#define UMAC_TCL_R0_LCE_RULE_12__TCP_OR_UDP___M 0x00180000 +#define UMAC_TCL_R0_LCE_RULE_12__TCP_OR_UDP___S 19 +#define UMAC_TCL_R0_LCE_RULE_12__MATCH_DEST_PORT___M 0x00040000 +#define UMAC_TCL_R0_LCE_RULE_12__MATCH_DEST_PORT___S 18 +#define UMAC_TCL_R0_LCE_RULE_12__MATCH_SRC_PORT___M 0x00020000 +#define UMAC_TCL_R0_LCE_RULE_12__MATCH_SRC_PORT___S 17 +#define UMAC_TCL_R0_LCE_RULE_12__MATCH_L3_TYPE___M 0x00010000 +#define UMAC_TCL_R0_LCE_RULE_12__MATCH_L3_TYPE___S 16 +#define UMAC_TCL_R0_LCE_RULE_12__MATCH_VAL___M 0x0000FFFF +#define UMAC_TCL_R0_LCE_RULE_12__MATCH_VAL___S 0 +#define UMAC_TCL_R0_LCE_RULE_13 (0x00A44514) +#define UMAC_TCL_R0_LCE_RULE_13___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_RULE_13__MATCH_IP_PROT___M 0x00400000 +#define UMAC_TCL_R0_LCE_RULE_13__MATCH_IP_PROT___S 22 +#define UMAC_TCL_R0_LCE_RULE_13__MATCH_DEST_ADDR_BIT_0___M 0x00200000 +#define UMAC_TCL_R0_LCE_RULE_13__MATCH_DEST_ADDR_BIT_0___S 21 +#define UMAC_TCL_R0_LCE_RULE_13__TCP_OR_UDP___M 0x00180000 +#define UMAC_TCL_R0_LCE_RULE_13__TCP_OR_UDP___S 19 +#define UMAC_TCL_R0_LCE_RULE_13__MATCH_DEST_PORT___M 0x00040000 +#define UMAC_TCL_R0_LCE_RULE_13__MATCH_DEST_PORT___S 18 +#define UMAC_TCL_R0_LCE_RULE_13__MATCH_SRC_PORT___M 0x00020000 +#define UMAC_TCL_R0_LCE_RULE_13__MATCH_SRC_PORT___S 17 +#define UMAC_TCL_R0_LCE_RULE_13__MATCH_L3_TYPE___M 0x00010000 +#define UMAC_TCL_R0_LCE_RULE_13__MATCH_L3_TYPE___S 16 +#define UMAC_TCL_R0_LCE_RULE_13__MATCH_VAL___M 0x0000FFFF +#define UMAC_TCL_R0_LCE_RULE_13__MATCH_VAL___S 0 +#define UMAC_TCL_R0_LCE_RULE_14 (0x00A44518) +#define UMAC_TCL_R0_LCE_RULE_14___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_RULE_14__MATCH_IP_PROT___M 0x00400000 +#define UMAC_TCL_R0_LCE_RULE_14__MATCH_IP_PROT___S 22 +#define UMAC_TCL_R0_LCE_RULE_14__MATCH_DEST_ADDR_BIT_0___M 0x00200000 +#define UMAC_TCL_R0_LCE_RULE_14__MATCH_DEST_ADDR_BIT_0___S 21 +#define UMAC_TCL_R0_LCE_RULE_14__TCP_OR_UDP___M 0x00180000 +#define UMAC_TCL_R0_LCE_RULE_14__TCP_OR_UDP___S 19 +#define UMAC_TCL_R0_LCE_RULE_14__MATCH_DEST_PORT___M 0x00040000 +#define UMAC_TCL_R0_LCE_RULE_14__MATCH_DEST_PORT___S 18 +#define UMAC_TCL_R0_LCE_RULE_14__MATCH_SRC_PORT___M 0x00020000 +#define UMAC_TCL_R0_LCE_RULE_14__MATCH_SRC_PORT___S 17 +#define UMAC_TCL_R0_LCE_RULE_14__MATCH_L3_TYPE___M 0x00010000 +#define UMAC_TCL_R0_LCE_RULE_14__MATCH_L3_TYPE___S 16 +#define UMAC_TCL_R0_LCE_RULE_14__MATCH_VAL___M 0x0000FFFF +#define UMAC_TCL_R0_LCE_RULE_14__MATCH_VAL___S 0 +#define UMAC_TCL_R0_LCE_RULE_15 (0x00A4451C) +#define UMAC_TCL_R0_LCE_RULE_15___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_RULE_15__MATCH_IP_PROT___M 0x00400000 +#define UMAC_TCL_R0_LCE_RULE_15__MATCH_IP_PROT___S 22 +#define UMAC_TCL_R0_LCE_RULE_15__MATCH_DEST_ADDR_BIT_0___M 0x00200000 +#define UMAC_TCL_R0_LCE_RULE_15__MATCH_DEST_ADDR_BIT_0___S 21 +#define UMAC_TCL_R0_LCE_RULE_15__TCP_OR_UDP___M 0x00180000 +#define UMAC_TCL_R0_LCE_RULE_15__TCP_OR_UDP___S 19 +#define UMAC_TCL_R0_LCE_RULE_15__MATCH_DEST_PORT___M 0x00040000 +#define UMAC_TCL_R0_LCE_RULE_15__MATCH_DEST_PORT___S 18 +#define UMAC_TCL_R0_LCE_RULE_15__MATCH_SRC_PORT___M 0x00020000 +#define UMAC_TCL_R0_LCE_RULE_15__MATCH_SRC_PORT___S 17 +#define UMAC_TCL_R0_LCE_RULE_15__MATCH_L3_TYPE___M 0x00010000 +#define UMAC_TCL_R0_LCE_RULE_15__MATCH_L3_TYPE___S 16 +#define UMAC_TCL_R0_LCE_RULE_15__MATCH_VAL___M 0x0000FFFF +#define UMAC_TCL_R0_LCE_RULE_15__MATCH_VAL___S 0 +#define UMAC_TCL_R0_LCE_RULE_16 (0x00A44520) +#define UMAC_TCL_R0_LCE_RULE_16___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_RULE_16__MATCH_IP_PROT___M 0x00400000 +#define UMAC_TCL_R0_LCE_RULE_16__MATCH_IP_PROT___S 22 +#define UMAC_TCL_R0_LCE_RULE_16__MATCH_DEST_ADDR_BIT_0___M 0x00200000 +#define UMAC_TCL_R0_LCE_RULE_16__MATCH_DEST_ADDR_BIT_0___S 21 +#define UMAC_TCL_R0_LCE_RULE_16__TCP_OR_UDP___M 0x00180000 +#define UMAC_TCL_R0_LCE_RULE_16__TCP_OR_UDP___S 19 +#define UMAC_TCL_R0_LCE_RULE_16__MATCH_DEST_PORT___M 0x00040000 +#define UMAC_TCL_R0_LCE_RULE_16__MATCH_DEST_PORT___S 18 +#define UMAC_TCL_R0_LCE_RULE_16__MATCH_SRC_PORT___M 0x00020000 +#define UMAC_TCL_R0_LCE_RULE_16__MATCH_SRC_PORT___S 17 +#define UMAC_TCL_R0_LCE_RULE_16__MATCH_L3_TYPE___M 0x00010000 +#define UMAC_TCL_R0_LCE_RULE_16__MATCH_L3_TYPE___S 16 +#define UMAC_TCL_R0_LCE_RULE_16__MATCH_VAL___M 0x0000FFFF +#define UMAC_TCL_R0_LCE_RULE_16__MATCH_VAL___S 0 +#define UMAC_TCL_R0_LCE_RULE_17 (0x00A44524) +#define UMAC_TCL_R0_LCE_RULE_17___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_RULE_17__MATCH_IP_PROT___M 0x00400000 +#define UMAC_TCL_R0_LCE_RULE_17__MATCH_IP_PROT___S 22 +#define UMAC_TCL_R0_LCE_RULE_17__MATCH_DEST_ADDR_BIT_0___M 0x00200000 +#define UMAC_TCL_R0_LCE_RULE_17__MATCH_DEST_ADDR_BIT_0___S 21 +#define UMAC_TCL_R0_LCE_RULE_17__TCP_OR_UDP___M 0x00180000 +#define UMAC_TCL_R0_LCE_RULE_17__TCP_OR_UDP___S 19 +#define UMAC_TCL_R0_LCE_RULE_17__MATCH_DEST_PORT___M 0x00040000 +#define UMAC_TCL_R0_LCE_RULE_17__MATCH_DEST_PORT___S 18 +#define UMAC_TCL_R0_LCE_RULE_17__MATCH_SRC_PORT___M 0x00020000 +#define UMAC_TCL_R0_LCE_RULE_17__MATCH_SRC_PORT___S 17 +#define UMAC_TCL_R0_LCE_RULE_17__MATCH_L3_TYPE___M 0x00010000 +#define UMAC_TCL_R0_LCE_RULE_17__MATCH_L3_TYPE___S 16 +#define UMAC_TCL_R0_LCE_RULE_17__MATCH_VAL___M 0x0000FFFF +#define UMAC_TCL_R0_LCE_RULE_17__MATCH_VAL___S 0 +#define UMAC_TCL_R0_LCE_RULE_18 (0x00A44528) +#define UMAC_TCL_R0_LCE_RULE_18___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_RULE_18__MATCH_IP_PROT___M 0x00400000 +#define UMAC_TCL_R0_LCE_RULE_18__MATCH_IP_PROT___S 22 +#define UMAC_TCL_R0_LCE_RULE_18__MATCH_DEST_ADDR_BIT_0___M 0x00200000 +#define UMAC_TCL_R0_LCE_RULE_18__MATCH_DEST_ADDR_BIT_0___S 21 +#define UMAC_TCL_R0_LCE_RULE_18__TCP_OR_UDP___M 0x00180000 +#define UMAC_TCL_R0_LCE_RULE_18__TCP_OR_UDP___S 19 +#define UMAC_TCL_R0_LCE_RULE_18__MATCH_DEST_PORT___M 0x00040000 +#define UMAC_TCL_R0_LCE_RULE_18__MATCH_DEST_PORT___S 18 +#define UMAC_TCL_R0_LCE_RULE_18__MATCH_SRC_PORT___M 0x00020000 +#define UMAC_TCL_R0_LCE_RULE_18__MATCH_SRC_PORT___S 17 +#define UMAC_TCL_R0_LCE_RULE_18__MATCH_L3_TYPE___M 0x00010000 +#define UMAC_TCL_R0_LCE_RULE_18__MATCH_L3_TYPE___S 16 +#define UMAC_TCL_R0_LCE_RULE_18__MATCH_VAL___M 0x0000FFFF +#define UMAC_TCL_R0_LCE_RULE_18__MATCH_VAL___S 0 +#define UMAC_TCL_R0_LCE_RULE_19 (0x00A4452C) +#define UMAC_TCL_R0_LCE_RULE_19___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_RULE_19__MATCH_IP_PROT___M 0x00400000 +#define UMAC_TCL_R0_LCE_RULE_19__MATCH_IP_PROT___S 22 +#define UMAC_TCL_R0_LCE_RULE_19__MATCH_DEST_ADDR_BIT_0___M 0x00200000 +#define UMAC_TCL_R0_LCE_RULE_19__MATCH_DEST_ADDR_BIT_0___S 21 +#define UMAC_TCL_R0_LCE_RULE_19__TCP_OR_UDP___M 0x00180000 +#define UMAC_TCL_R0_LCE_RULE_19__TCP_OR_UDP___S 19 +#define UMAC_TCL_R0_LCE_RULE_19__MATCH_DEST_PORT___M 0x00040000 +#define UMAC_TCL_R0_LCE_RULE_19__MATCH_DEST_PORT___S 18 +#define UMAC_TCL_R0_LCE_RULE_19__MATCH_SRC_PORT___M 0x00020000 +#define UMAC_TCL_R0_LCE_RULE_19__MATCH_SRC_PORT___S 17 +#define UMAC_TCL_R0_LCE_RULE_19__MATCH_L3_TYPE___M 0x00010000 +#define UMAC_TCL_R0_LCE_RULE_19__MATCH_L3_TYPE___S 16 +#define UMAC_TCL_R0_LCE_RULE_19__MATCH_VAL___M 0x0000FFFF +#define UMAC_TCL_R0_LCE_RULE_19__MATCH_VAL___S 0 +#define UMAC_TCL_R0_LCE_RULE_20 (0x00A44530) +#define UMAC_TCL_R0_LCE_RULE_20___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_RULE_20__MATCH_IP_PROT___M 0x00400000 +#define UMAC_TCL_R0_LCE_RULE_20__MATCH_IP_PROT___S 22 +#define UMAC_TCL_R0_LCE_RULE_20__MATCH_DEST_ADDR_BIT_0___M 0x00200000 +#define UMAC_TCL_R0_LCE_RULE_20__MATCH_DEST_ADDR_BIT_0___S 21 +#define UMAC_TCL_R0_LCE_RULE_20__TCP_OR_UDP___M 0x00180000 +#define UMAC_TCL_R0_LCE_RULE_20__TCP_OR_UDP___S 19 +#define UMAC_TCL_R0_LCE_RULE_20__MATCH_DEST_PORT___M 0x00040000 +#define UMAC_TCL_R0_LCE_RULE_20__MATCH_DEST_PORT___S 18 +#define UMAC_TCL_R0_LCE_RULE_20__MATCH_SRC_PORT___M 0x00020000 +#define UMAC_TCL_R0_LCE_RULE_20__MATCH_SRC_PORT___S 17 +#define UMAC_TCL_R0_LCE_RULE_20__MATCH_L3_TYPE___M 0x00010000 +#define UMAC_TCL_R0_LCE_RULE_20__MATCH_L3_TYPE___S 16 +#define UMAC_TCL_R0_LCE_RULE_20__MATCH_VAL___M 0x0000FFFF +#define UMAC_TCL_R0_LCE_RULE_20__MATCH_VAL___S 0 +#define UMAC_TCL_R0_LCE_RULE_21 (0x00A44534) +#define UMAC_TCL_R0_LCE_RULE_21___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_RULE_21__MATCH_IP_PROT___M 0x00400000 +#define UMAC_TCL_R0_LCE_RULE_21__MATCH_IP_PROT___S 22 +#define UMAC_TCL_R0_LCE_RULE_21__MATCH_DEST_ADDR_BIT_0___M 0x00200000 +#define UMAC_TCL_R0_LCE_RULE_21__MATCH_DEST_ADDR_BIT_0___S 21 +#define UMAC_TCL_R0_LCE_RULE_21__TCP_OR_UDP___M 0x00180000 +#define UMAC_TCL_R0_LCE_RULE_21__TCP_OR_UDP___S 19 +#define UMAC_TCL_R0_LCE_RULE_21__MATCH_DEST_PORT___M 0x00040000 +#define UMAC_TCL_R0_LCE_RULE_21__MATCH_DEST_PORT___S 18 +#define UMAC_TCL_R0_LCE_RULE_21__MATCH_SRC_PORT___M 0x00020000 +#define UMAC_TCL_R0_LCE_RULE_21__MATCH_SRC_PORT___S 17 +#define UMAC_TCL_R0_LCE_RULE_21__MATCH_L3_TYPE___M 0x00010000 +#define UMAC_TCL_R0_LCE_RULE_21__MATCH_L3_TYPE___S 16 +#define UMAC_TCL_R0_LCE_RULE_21__MATCH_VAL___M 0x0000FFFF +#define UMAC_TCL_R0_LCE_RULE_21__MATCH_VAL___S 0 +#define UMAC_TCL_R0_LCE_RULE_22 (0x00A44538) +#define UMAC_TCL_R0_LCE_RULE_22___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_RULE_22__MATCH_IP_PROT___M 0x00400000 +#define UMAC_TCL_R0_LCE_RULE_22__MATCH_IP_PROT___S 22 +#define UMAC_TCL_R0_LCE_RULE_22__MATCH_DEST_ADDR_BIT_0___M 0x00200000 +#define UMAC_TCL_R0_LCE_RULE_22__MATCH_DEST_ADDR_BIT_0___S 21 +#define UMAC_TCL_R0_LCE_RULE_22__TCP_OR_UDP___M 0x00180000 +#define UMAC_TCL_R0_LCE_RULE_22__TCP_OR_UDP___S 19 +#define UMAC_TCL_R0_LCE_RULE_22__MATCH_DEST_PORT___M 0x00040000 +#define UMAC_TCL_R0_LCE_RULE_22__MATCH_DEST_PORT___S 18 +#define UMAC_TCL_R0_LCE_RULE_22__MATCH_SRC_PORT___M 0x00020000 +#define UMAC_TCL_R0_LCE_RULE_22__MATCH_SRC_PORT___S 17 +#define UMAC_TCL_R0_LCE_RULE_22__MATCH_L3_TYPE___M 0x00010000 +#define UMAC_TCL_R0_LCE_RULE_22__MATCH_L3_TYPE___S 16 +#define UMAC_TCL_R0_LCE_RULE_22__MATCH_VAL___M 0x0000FFFF +#define UMAC_TCL_R0_LCE_RULE_22__MATCH_VAL___S 0 +#define UMAC_TCL_R0_LCE_RULE_23 (0x00A4453C) +#define UMAC_TCL_R0_LCE_RULE_23___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_RULE_23__MATCH_IP_PROT___M 0x00400000 +#define UMAC_TCL_R0_LCE_RULE_23__MATCH_IP_PROT___S 22 +#define UMAC_TCL_R0_LCE_RULE_23__MATCH_DEST_ADDR_BIT_0___M 0x00200000 +#define UMAC_TCL_R0_LCE_RULE_23__MATCH_DEST_ADDR_BIT_0___S 21 +#define UMAC_TCL_R0_LCE_RULE_23__TCP_OR_UDP___M 0x00180000 +#define UMAC_TCL_R0_LCE_RULE_23__TCP_OR_UDP___S 19 +#define UMAC_TCL_R0_LCE_RULE_23__MATCH_DEST_PORT___M 0x00040000 +#define UMAC_TCL_R0_LCE_RULE_23__MATCH_DEST_PORT___S 18 +#define UMAC_TCL_R0_LCE_RULE_23__MATCH_SRC_PORT___M 0x00020000 +#define UMAC_TCL_R0_LCE_RULE_23__MATCH_SRC_PORT___S 17 +#define UMAC_TCL_R0_LCE_RULE_23__MATCH_L3_TYPE___M 0x00010000 +#define UMAC_TCL_R0_LCE_RULE_23__MATCH_L3_TYPE___S 16 +#define UMAC_TCL_R0_LCE_RULE_23__MATCH_VAL___M 0x0000FFFF +#define UMAC_TCL_R0_LCE_RULE_23__MATCH_VAL___S 0 +#define UMAC_TCL_R0_LCE_RULE_24 (0x00A44540) +#define UMAC_TCL_R0_LCE_RULE_24___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_RULE_24__MATCH_IP_PROT___M 0x00400000 +#define UMAC_TCL_R0_LCE_RULE_24__MATCH_IP_PROT___S 22 +#define UMAC_TCL_R0_LCE_RULE_24__MATCH_DEST_ADDR_BIT_0___M 0x00200000 +#define UMAC_TCL_R0_LCE_RULE_24__MATCH_DEST_ADDR_BIT_0___S 21 +#define UMAC_TCL_R0_LCE_RULE_24__TCP_OR_UDP___M 0x00180000 +#define UMAC_TCL_R0_LCE_RULE_24__TCP_OR_UDP___S 19 +#define UMAC_TCL_R0_LCE_RULE_24__MATCH_DEST_PORT___M 0x00040000 +#define UMAC_TCL_R0_LCE_RULE_24__MATCH_DEST_PORT___S 18 +#define UMAC_TCL_R0_LCE_RULE_24__MATCH_SRC_PORT___M 0x00020000 +#define UMAC_TCL_R0_LCE_RULE_24__MATCH_SRC_PORT___S 17 +#define UMAC_TCL_R0_LCE_RULE_24__MATCH_L3_TYPE___M 0x00010000 +#define UMAC_TCL_R0_LCE_RULE_24__MATCH_L3_TYPE___S 16 +#define UMAC_TCL_R0_LCE_RULE_24__MATCH_VAL___M 0x0000FFFF +#define UMAC_TCL_R0_LCE_RULE_24__MATCH_VAL___S 0 +#define UMAC_TCL_R0_LCE_RULE_25 (0x00A44544) +#define UMAC_TCL_R0_LCE_RULE_25___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_RULE_25__MATCH_IP_PROT___M 0x00400000 +#define UMAC_TCL_R0_LCE_RULE_25__MATCH_IP_PROT___S 22 +#define UMAC_TCL_R0_LCE_RULE_25__MATCH_DEST_ADDR_BIT_0___M 0x00200000 +#define UMAC_TCL_R0_LCE_RULE_25__MATCH_DEST_ADDR_BIT_0___S 21 +#define UMAC_TCL_R0_LCE_RULE_25__TCP_OR_UDP___M 0x00180000 +#define UMAC_TCL_R0_LCE_RULE_25__TCP_OR_UDP___S 19 +#define UMAC_TCL_R0_LCE_RULE_25__MATCH_DEST_PORT___M 0x00040000 +#define UMAC_TCL_R0_LCE_RULE_25__MATCH_DEST_PORT___S 18 +#define UMAC_TCL_R0_LCE_RULE_25__MATCH_SRC_PORT___M 0x00020000 +#define UMAC_TCL_R0_LCE_RULE_25__MATCH_SRC_PORT___S 17 +#define UMAC_TCL_R0_LCE_RULE_25__MATCH_L3_TYPE___M 0x00010000 +#define UMAC_TCL_R0_LCE_RULE_25__MATCH_L3_TYPE___S 16 +#define UMAC_TCL_R0_LCE_RULE_25__MATCH_VAL___M 0x0000FFFF +#define UMAC_TCL_R0_LCE_RULE_25__MATCH_VAL___S 0 + +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n(n) (0x00A44548+0x4*(n)) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_nMIN 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_nMAX 25 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_ELEM 26 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n___POR 0x00000000 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n__VAL___POR 0x00000000 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n___M 0xFFFFFFFF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_0 (0x00A44548) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_0___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_0__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_0__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_1 (0x00A4454C) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_1___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_1__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_1__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_2 (0x00A44550) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_2___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_2__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_2__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_3 (0x00A44554) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_3___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_3__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_3__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_4 (0x00A44558) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_4___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_4__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_4__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_5 (0x00A4455C) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_5___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_5__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_5__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_6 (0x00A44560) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_6___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_6__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_6__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_7 (0x00A44564) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_7___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_7__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_7__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_8 (0x00A44568) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_8___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_8__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_8__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_9 (0x00A4456C) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_9___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_9__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_9__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_10 (0x00A44570) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_10___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_10__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_10__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_11 (0x00A44574) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_11___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_11__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_11__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_12 (0x00A44578) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_12___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_12__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_12__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_13 (0x00A4457C) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_13___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_13__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_13__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_14 (0x00A44580) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_14___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_14__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_14__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_15 (0x00A44584) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_15___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_15__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_15__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_16 (0x00A44588) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_16___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_16__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_16__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_17 (0x00A4458C) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_17___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_17__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_17__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_18 (0x00A44590) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_18___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_18__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_18__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_19 (0x00A44594) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_19___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_19__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_19__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_20 (0x00A44598) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_20___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_20__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_20__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_21 (0x00A4459C) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_21___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_21__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_21__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_22 (0x00A445A0) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_22___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_22__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_22__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_23 (0x00A445A4) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_23___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_23__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_23__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_24 (0x00A445A8) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_24___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_24__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_24__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_25 (0x00A445AC) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_25___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_25__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_25__VAL___S 0 + +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n(n) (0x00A445B0+0x4*(n)) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_nMIN 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_nMAX 25 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_ELEM 26 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n___POR 0x00000000 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n__VAL___POR 0x00 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n__VAL___M 0x000000FF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n___M 0x000000FF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_0 (0x00A445B0) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_0___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_0__VAL___M 0x000000FF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_0__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_1 (0x00A445B4) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_1___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_1__VAL___M 0x000000FF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_1__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_2 (0x00A445B8) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_2___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_2__VAL___M 0x000000FF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_2__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_3 (0x00A445BC) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_3___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_3__VAL___M 0x000000FF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_3__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_4 (0x00A445C0) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_4___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_4__VAL___M 0x000000FF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_4__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_5 (0x00A445C4) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_5___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_5__VAL___M 0x000000FF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_5__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_6 (0x00A445C8) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_6___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_6__VAL___M 0x000000FF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_6__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_7 (0x00A445CC) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_7___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_7__VAL___M 0x000000FF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_7__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_8 (0x00A445D0) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_8___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_8__VAL___M 0x000000FF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_8__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_9 (0x00A445D4) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_9___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_9__VAL___M 0x000000FF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_9__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_10 (0x00A445D8) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_10___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_10__VAL___M 0x000000FF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_10__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_11 (0x00A445DC) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_11___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_11__VAL___M 0x000000FF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_11__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_12 (0x00A445E0) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_12___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_12__VAL___M 0x000000FF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_12__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_13 (0x00A445E4) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_13___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_13__VAL___M 0x000000FF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_13__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_14 (0x00A445E8) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_14___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_14__VAL___M 0x000000FF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_14__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_15 (0x00A445EC) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_15___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_15__VAL___M 0x000000FF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_15__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_16 (0x00A445F0) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_16___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_16__VAL___M 0x000000FF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_16__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_17 (0x00A445F4) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_17___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_17__VAL___M 0x000000FF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_17__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_18 (0x00A445F8) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_18___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_18__VAL___M 0x000000FF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_18__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_19 (0x00A445FC) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_19___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_19__VAL___M 0x000000FF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_19__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_20 (0x00A44600) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_20___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_20__VAL___M 0x000000FF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_20__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_21 (0x00A44604) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_21___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_21__VAL___M 0x000000FF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_21__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_22 (0x00A44608) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_22___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_22__VAL___M 0x000000FF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_22__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_23 (0x00A4460C) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_23___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_23__VAL___M 0x000000FF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_23__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_24 (0x00A44610) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_24___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_24__VAL___M 0x000000FF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_24__VAL___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_25 (0x00A44614) +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_25___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_25__VAL___M 0x000000FF +#define UMAC_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_25__VAL___S 0 + +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n(n) (0x00A44618+0x4*(n)) +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n_nMIN 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n_nMAX 25 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n_ELEM 26 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n___POR 0x00000000 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__RULE_HIT___POR 0x0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__METADATA___POR 0x0000 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__MSDU_DROP___POR 0x0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__TO_TQM_IF_M0_FW___POR 0x0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__TQM_FLOW_LOOP_HANDLER___POR 0x0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__TQM_FLOW_HANDLER___POR 0x0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__RULE_HIT___M 0x00200000 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__RULE_HIT___S 21 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__METADATA___M 0x001FFFE0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__METADATA___S 5 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__MSDU_DROP___M 0x00000010 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__MSDU_DROP___S 4 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__TO_TQM_IF_M0_FW___M 0x00000008 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__TO_TQM_IF_M0_FW___S 3 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__TQM_FLOW_LOOP_HANDLER___M 0x00000004 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__TQM_FLOW_LOOP_HANDLER___S 2 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__TQM_FLOW_HANDLER___M 0x00000003 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n__TQM_FLOW_HANDLER___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n___M 0x003FFFFF +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_n___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_0 (0x00A44618) +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_0___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_0__RULE_HIT___M 0x00200000 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_0__RULE_HIT___S 21 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_0__METADATA___M 0x001FFFE0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_0__METADATA___S 5 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_0__MSDU_DROP___M 0x00000010 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_0__MSDU_DROP___S 4 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_0__TO_TQM_IF_M0_FW___M 0x00000008 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_0__TO_TQM_IF_M0_FW___S 3 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_0__TQM_FLOW_LOOP_HANDLER___M 0x00000004 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_0__TQM_FLOW_LOOP_HANDLER___S 2 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_0__TQM_FLOW_HANDLER___M 0x00000003 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_0__TQM_FLOW_HANDLER___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_1 (0x00A4461C) +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_1___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_1__RULE_HIT___M 0x00200000 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_1__RULE_HIT___S 21 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_1__METADATA___M 0x001FFFE0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_1__METADATA___S 5 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_1__MSDU_DROP___M 0x00000010 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_1__MSDU_DROP___S 4 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_1__TO_TQM_IF_M0_FW___M 0x00000008 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_1__TO_TQM_IF_M0_FW___S 3 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_1__TQM_FLOW_LOOP_HANDLER___M 0x00000004 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_1__TQM_FLOW_LOOP_HANDLER___S 2 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_1__TQM_FLOW_HANDLER___M 0x00000003 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_1__TQM_FLOW_HANDLER___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_2 (0x00A44620) +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_2___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_2__RULE_HIT___M 0x00200000 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_2__RULE_HIT___S 21 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_2__METADATA___M 0x001FFFE0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_2__METADATA___S 5 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_2__MSDU_DROP___M 0x00000010 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_2__MSDU_DROP___S 4 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_2__TO_TQM_IF_M0_FW___M 0x00000008 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_2__TO_TQM_IF_M0_FW___S 3 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_2__TQM_FLOW_LOOP_HANDLER___M 0x00000004 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_2__TQM_FLOW_LOOP_HANDLER___S 2 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_2__TQM_FLOW_HANDLER___M 0x00000003 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_2__TQM_FLOW_HANDLER___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_3 (0x00A44624) +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_3___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_3__RULE_HIT___M 0x00200000 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_3__RULE_HIT___S 21 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_3__METADATA___M 0x001FFFE0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_3__METADATA___S 5 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_3__MSDU_DROP___M 0x00000010 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_3__MSDU_DROP___S 4 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_3__TO_TQM_IF_M0_FW___M 0x00000008 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_3__TO_TQM_IF_M0_FW___S 3 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_3__TQM_FLOW_LOOP_HANDLER___M 0x00000004 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_3__TQM_FLOW_LOOP_HANDLER___S 2 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_3__TQM_FLOW_HANDLER___M 0x00000003 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_3__TQM_FLOW_HANDLER___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_4 (0x00A44628) +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_4___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_4__RULE_HIT___M 0x00200000 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_4__RULE_HIT___S 21 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_4__METADATA___M 0x001FFFE0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_4__METADATA___S 5 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_4__MSDU_DROP___M 0x00000010 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_4__MSDU_DROP___S 4 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_4__TO_TQM_IF_M0_FW___M 0x00000008 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_4__TO_TQM_IF_M0_FW___S 3 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_4__TQM_FLOW_LOOP_HANDLER___M 0x00000004 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_4__TQM_FLOW_LOOP_HANDLER___S 2 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_4__TQM_FLOW_HANDLER___M 0x00000003 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_4__TQM_FLOW_HANDLER___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_5 (0x00A4462C) +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_5___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_5__RULE_HIT___M 0x00200000 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_5__RULE_HIT___S 21 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_5__METADATA___M 0x001FFFE0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_5__METADATA___S 5 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_5__MSDU_DROP___M 0x00000010 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_5__MSDU_DROP___S 4 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_5__TO_TQM_IF_M0_FW___M 0x00000008 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_5__TO_TQM_IF_M0_FW___S 3 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_5__TQM_FLOW_LOOP_HANDLER___M 0x00000004 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_5__TQM_FLOW_LOOP_HANDLER___S 2 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_5__TQM_FLOW_HANDLER___M 0x00000003 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_5__TQM_FLOW_HANDLER___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_6 (0x00A44630) +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_6___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_6__RULE_HIT___M 0x00200000 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_6__RULE_HIT___S 21 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_6__METADATA___M 0x001FFFE0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_6__METADATA___S 5 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_6__MSDU_DROP___M 0x00000010 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_6__MSDU_DROP___S 4 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_6__TO_TQM_IF_M0_FW___M 0x00000008 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_6__TO_TQM_IF_M0_FW___S 3 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_6__TQM_FLOW_LOOP_HANDLER___M 0x00000004 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_6__TQM_FLOW_LOOP_HANDLER___S 2 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_6__TQM_FLOW_HANDLER___M 0x00000003 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_6__TQM_FLOW_HANDLER___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_7 (0x00A44634) +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_7___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_7__RULE_HIT___M 0x00200000 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_7__RULE_HIT___S 21 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_7__METADATA___M 0x001FFFE0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_7__METADATA___S 5 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_7__MSDU_DROP___M 0x00000010 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_7__MSDU_DROP___S 4 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_7__TO_TQM_IF_M0_FW___M 0x00000008 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_7__TO_TQM_IF_M0_FW___S 3 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_7__TQM_FLOW_LOOP_HANDLER___M 0x00000004 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_7__TQM_FLOW_LOOP_HANDLER___S 2 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_7__TQM_FLOW_HANDLER___M 0x00000003 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_7__TQM_FLOW_HANDLER___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_8 (0x00A44638) +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_8___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_8__RULE_HIT___M 0x00200000 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_8__RULE_HIT___S 21 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_8__METADATA___M 0x001FFFE0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_8__METADATA___S 5 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_8__MSDU_DROP___M 0x00000010 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_8__MSDU_DROP___S 4 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_8__TO_TQM_IF_M0_FW___M 0x00000008 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_8__TO_TQM_IF_M0_FW___S 3 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_8__TQM_FLOW_LOOP_HANDLER___M 0x00000004 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_8__TQM_FLOW_LOOP_HANDLER___S 2 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_8__TQM_FLOW_HANDLER___M 0x00000003 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_8__TQM_FLOW_HANDLER___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_9 (0x00A4463C) +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_9___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_9__RULE_HIT___M 0x00200000 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_9__RULE_HIT___S 21 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_9__METADATA___M 0x001FFFE0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_9__METADATA___S 5 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_9__MSDU_DROP___M 0x00000010 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_9__MSDU_DROP___S 4 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_9__TO_TQM_IF_M0_FW___M 0x00000008 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_9__TO_TQM_IF_M0_FW___S 3 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_9__TQM_FLOW_LOOP_HANDLER___M 0x00000004 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_9__TQM_FLOW_LOOP_HANDLER___S 2 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_9__TQM_FLOW_HANDLER___M 0x00000003 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_9__TQM_FLOW_HANDLER___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_10 (0x00A44640) +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_10___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_10__RULE_HIT___M 0x00200000 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_10__RULE_HIT___S 21 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_10__METADATA___M 0x001FFFE0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_10__METADATA___S 5 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_10__MSDU_DROP___M 0x00000010 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_10__MSDU_DROP___S 4 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_10__TO_TQM_IF_M0_FW___M 0x00000008 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_10__TO_TQM_IF_M0_FW___S 3 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_10__TQM_FLOW_LOOP_HANDLER___M 0x00000004 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_10__TQM_FLOW_LOOP_HANDLER___S 2 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_10__TQM_FLOW_HANDLER___M 0x00000003 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_10__TQM_FLOW_HANDLER___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_11 (0x00A44644) +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_11___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_11__RULE_HIT___M 0x00200000 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_11__RULE_HIT___S 21 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_11__METADATA___M 0x001FFFE0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_11__METADATA___S 5 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_11__MSDU_DROP___M 0x00000010 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_11__MSDU_DROP___S 4 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_11__TO_TQM_IF_M0_FW___M 0x00000008 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_11__TO_TQM_IF_M0_FW___S 3 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_11__TQM_FLOW_LOOP_HANDLER___M 0x00000004 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_11__TQM_FLOW_LOOP_HANDLER___S 2 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_11__TQM_FLOW_HANDLER___M 0x00000003 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_11__TQM_FLOW_HANDLER___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_12 (0x00A44648) +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_12___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_12__RULE_HIT___M 0x00200000 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_12__RULE_HIT___S 21 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_12__METADATA___M 0x001FFFE0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_12__METADATA___S 5 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_12__MSDU_DROP___M 0x00000010 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_12__MSDU_DROP___S 4 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_12__TO_TQM_IF_M0_FW___M 0x00000008 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_12__TO_TQM_IF_M0_FW___S 3 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_12__TQM_FLOW_LOOP_HANDLER___M 0x00000004 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_12__TQM_FLOW_LOOP_HANDLER___S 2 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_12__TQM_FLOW_HANDLER___M 0x00000003 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_12__TQM_FLOW_HANDLER___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_13 (0x00A4464C) +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_13___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_13__RULE_HIT___M 0x00200000 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_13__RULE_HIT___S 21 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_13__METADATA___M 0x001FFFE0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_13__METADATA___S 5 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_13__MSDU_DROP___M 0x00000010 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_13__MSDU_DROP___S 4 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_13__TO_TQM_IF_M0_FW___M 0x00000008 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_13__TO_TQM_IF_M0_FW___S 3 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_13__TQM_FLOW_LOOP_HANDLER___M 0x00000004 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_13__TQM_FLOW_LOOP_HANDLER___S 2 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_13__TQM_FLOW_HANDLER___M 0x00000003 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_13__TQM_FLOW_HANDLER___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_14 (0x00A44650) +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_14___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_14__RULE_HIT___M 0x00200000 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_14__RULE_HIT___S 21 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_14__METADATA___M 0x001FFFE0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_14__METADATA___S 5 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_14__MSDU_DROP___M 0x00000010 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_14__MSDU_DROP___S 4 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_14__TO_TQM_IF_M0_FW___M 0x00000008 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_14__TO_TQM_IF_M0_FW___S 3 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_14__TQM_FLOW_LOOP_HANDLER___M 0x00000004 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_14__TQM_FLOW_LOOP_HANDLER___S 2 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_14__TQM_FLOW_HANDLER___M 0x00000003 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_14__TQM_FLOW_HANDLER___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_15 (0x00A44654) +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_15___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_15__RULE_HIT___M 0x00200000 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_15__RULE_HIT___S 21 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_15__METADATA___M 0x001FFFE0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_15__METADATA___S 5 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_15__MSDU_DROP___M 0x00000010 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_15__MSDU_DROP___S 4 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_15__TO_TQM_IF_M0_FW___M 0x00000008 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_15__TO_TQM_IF_M0_FW___S 3 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_15__TQM_FLOW_LOOP_HANDLER___M 0x00000004 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_15__TQM_FLOW_LOOP_HANDLER___S 2 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_15__TQM_FLOW_HANDLER___M 0x00000003 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_15__TQM_FLOW_HANDLER___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_16 (0x00A44658) +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_16___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_16__RULE_HIT___M 0x00200000 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_16__RULE_HIT___S 21 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_16__METADATA___M 0x001FFFE0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_16__METADATA___S 5 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_16__MSDU_DROP___M 0x00000010 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_16__MSDU_DROP___S 4 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_16__TO_TQM_IF_M0_FW___M 0x00000008 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_16__TO_TQM_IF_M0_FW___S 3 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_16__TQM_FLOW_LOOP_HANDLER___M 0x00000004 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_16__TQM_FLOW_LOOP_HANDLER___S 2 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_16__TQM_FLOW_HANDLER___M 0x00000003 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_16__TQM_FLOW_HANDLER___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_17 (0x00A4465C) +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_17___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_17__RULE_HIT___M 0x00200000 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_17__RULE_HIT___S 21 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_17__METADATA___M 0x001FFFE0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_17__METADATA___S 5 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_17__MSDU_DROP___M 0x00000010 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_17__MSDU_DROP___S 4 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_17__TO_TQM_IF_M0_FW___M 0x00000008 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_17__TO_TQM_IF_M0_FW___S 3 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_17__TQM_FLOW_LOOP_HANDLER___M 0x00000004 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_17__TQM_FLOW_LOOP_HANDLER___S 2 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_17__TQM_FLOW_HANDLER___M 0x00000003 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_17__TQM_FLOW_HANDLER___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_18 (0x00A44660) +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_18___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_18__RULE_HIT___M 0x00200000 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_18__RULE_HIT___S 21 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_18__METADATA___M 0x001FFFE0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_18__METADATA___S 5 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_18__MSDU_DROP___M 0x00000010 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_18__MSDU_DROP___S 4 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_18__TO_TQM_IF_M0_FW___M 0x00000008 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_18__TO_TQM_IF_M0_FW___S 3 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_18__TQM_FLOW_LOOP_HANDLER___M 0x00000004 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_18__TQM_FLOW_LOOP_HANDLER___S 2 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_18__TQM_FLOW_HANDLER___M 0x00000003 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_18__TQM_FLOW_HANDLER___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_19 (0x00A44664) +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_19___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_19__RULE_HIT___M 0x00200000 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_19__RULE_HIT___S 21 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_19__METADATA___M 0x001FFFE0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_19__METADATA___S 5 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_19__MSDU_DROP___M 0x00000010 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_19__MSDU_DROP___S 4 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_19__TO_TQM_IF_M0_FW___M 0x00000008 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_19__TO_TQM_IF_M0_FW___S 3 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_19__TQM_FLOW_LOOP_HANDLER___M 0x00000004 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_19__TQM_FLOW_LOOP_HANDLER___S 2 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_19__TQM_FLOW_HANDLER___M 0x00000003 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_19__TQM_FLOW_HANDLER___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_20 (0x00A44668) +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_20___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_20__RULE_HIT___M 0x00200000 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_20__RULE_HIT___S 21 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_20__METADATA___M 0x001FFFE0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_20__METADATA___S 5 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_20__MSDU_DROP___M 0x00000010 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_20__MSDU_DROP___S 4 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_20__TO_TQM_IF_M0_FW___M 0x00000008 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_20__TO_TQM_IF_M0_FW___S 3 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_20__TQM_FLOW_LOOP_HANDLER___M 0x00000004 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_20__TQM_FLOW_LOOP_HANDLER___S 2 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_20__TQM_FLOW_HANDLER___M 0x00000003 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_20__TQM_FLOW_HANDLER___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_21 (0x00A4466C) +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_21___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_21__RULE_HIT___M 0x00200000 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_21__RULE_HIT___S 21 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_21__METADATA___M 0x001FFFE0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_21__METADATA___S 5 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_21__MSDU_DROP___M 0x00000010 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_21__MSDU_DROP___S 4 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_21__TO_TQM_IF_M0_FW___M 0x00000008 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_21__TO_TQM_IF_M0_FW___S 3 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_21__TQM_FLOW_LOOP_HANDLER___M 0x00000004 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_21__TQM_FLOW_LOOP_HANDLER___S 2 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_21__TQM_FLOW_HANDLER___M 0x00000003 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_21__TQM_FLOW_HANDLER___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_22 (0x00A44670) +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_22___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_22__RULE_HIT___M 0x00200000 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_22__RULE_HIT___S 21 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_22__METADATA___M 0x001FFFE0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_22__METADATA___S 5 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_22__MSDU_DROP___M 0x00000010 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_22__MSDU_DROP___S 4 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_22__TO_TQM_IF_M0_FW___M 0x00000008 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_22__TO_TQM_IF_M0_FW___S 3 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_22__TQM_FLOW_LOOP_HANDLER___M 0x00000004 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_22__TQM_FLOW_LOOP_HANDLER___S 2 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_22__TQM_FLOW_HANDLER___M 0x00000003 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_22__TQM_FLOW_HANDLER___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_23 (0x00A44674) +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_23___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_23__RULE_HIT___M 0x00200000 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_23__RULE_HIT___S 21 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_23__METADATA___M 0x001FFFE0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_23__METADATA___S 5 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_23__MSDU_DROP___M 0x00000010 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_23__MSDU_DROP___S 4 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_23__TO_TQM_IF_M0_FW___M 0x00000008 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_23__TO_TQM_IF_M0_FW___S 3 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_23__TQM_FLOW_LOOP_HANDLER___M 0x00000004 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_23__TQM_FLOW_LOOP_HANDLER___S 2 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_23__TQM_FLOW_HANDLER___M 0x00000003 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_23__TQM_FLOW_HANDLER___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_24 (0x00A44678) +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_24___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_24__RULE_HIT___M 0x00200000 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_24__RULE_HIT___S 21 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_24__METADATA___M 0x001FFFE0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_24__METADATA___S 5 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_24__MSDU_DROP___M 0x00000010 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_24__MSDU_DROP___S 4 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_24__TO_TQM_IF_M0_FW___M 0x00000008 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_24__TO_TQM_IF_M0_FW___S 3 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_24__TQM_FLOW_LOOP_HANDLER___M 0x00000004 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_24__TQM_FLOW_LOOP_HANDLER___S 2 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_24__TQM_FLOW_HANDLER___M 0x00000003 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_24__TQM_FLOW_HANDLER___S 0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_25 (0x00A4467C) +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_25___RWC QCSR_REG_RW +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_25__RULE_HIT___M 0x00200000 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_25__RULE_HIT___S 21 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_25__METADATA___M 0x001FFFE0 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_25__METADATA___S 5 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_25__MSDU_DROP___M 0x00000010 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_25__MSDU_DROP___S 4 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_25__TO_TQM_IF_M0_FW___M 0x00000008 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_25__TO_TQM_IF_M0_FW___S 3 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_25__TQM_FLOW_LOOP_HANDLER___M 0x00000004 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_25__TQM_FLOW_LOOP_HANDLER___S 2 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_25__TQM_FLOW_HANDLER___M 0x00000003 +#define UMAC_TCL_R0_LCE_CLFY_INFO_HANDLER_25__TQM_FLOW_HANDLER___S 0 + +#define UMAC_TCL_R0_CLKGATE_DISABLE (0x00A44680) +#define UMAC_TCL_R0_CLKGATE_DISABLE___RWC QCSR_REG_RW +#define UMAC_TCL_R0_CLKGATE_DISABLE___POR 0x00000000 +#define UMAC_TCL_R0_CLKGATE_DISABLE__CLK_ENS_EXTEND___POR 0x0 +#define UMAC_TCL_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___POR 0x0 +#define UMAC_TCL_R0_CLKGATE_DISABLE__APB_CLK___POR 0x0 +#define UMAC_TCL_R0_CLKGATE_DISABLE__FSE___POR 0x0 +#define UMAC_TCL_R0_CLKGATE_DISABLE__CLFY_RES_MEM___POR 0x0 +#define UMAC_TCL_R0_CLKGATE_DISABLE__GSE_CTRL___POR 0x0 +#define UMAC_TCL_R0_CLKGATE_DISABLE__GSE_CCE_RES___POR 0x0 +#define UMAC_TCL_R0_CLKGATE_DISABLE__TCL2_STATUS2_PROD_RING___POR 0x0 +#define UMAC_TCL_R0_CLKGATE_DISABLE__TCL2_STATUS1_PROD_RING___POR 0x0 +#define UMAC_TCL_R0_CLKGATE_DISABLE__TCL2FW_PROD_RING___POR 0x0 +#define UMAC_TCL_R0_CLKGATE_DISABLE__TCL2TQM_PROD_RING___POR 0x0 +#define UMAC_TCL_R0_CLKGATE_DISABLE__PROD_RING_CTRL___POR 0x0 +#define UMAC_TCL_R0_CLKGATE_DISABLE__TLV_DECODE___POR 0x0 +#define UMAC_TCL_R0_CLKGATE_DISABLE__TLV_GEN___POR 0x0 +#define UMAC_TCL_R0_CLKGATE_DISABLE__DATA_FETCH___POR 0x0 +#define UMAC_TCL_R0_CLKGATE_DISABLE__DATA_BUF___POR 0x0 +#define UMAC_TCL_R0_CLKGATE_DISABLE__DESC_BUF___POR 0x0 +#define UMAC_TCL_R0_CLKGATE_DISABLE__DESC_RD___POR 0x0 +#define UMAC_TCL_R0_CLKGATE_DISABLE__ASE___POR 0x0 +#define UMAC_TCL_R0_CLKGATE_DISABLE__GXI___POR 0x0 +#define UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_P_3___POR 0x0 +#define UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_P_2___POR 0x0 +#define UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_P_1___POR 0x0 +#define UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_P_0___POR 0x0 +#define UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_C_4___POR 0x0 +#define UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_C_3___POR 0x0 +#define UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_C_2___POR 0x0 +#define UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_C_1___POR 0x0 +#define UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_C_0___POR 0x0 +#define UMAC_TCL_R0_CLKGATE_DISABLE__TCL_IDLE_REQ_SM___POR 0x0 +#define UMAC_TCL_R0_CLKGATE_DISABLE__LCE_CCE___POR 0x0 +#define UMAC_TCL_R0_CLKGATE_DISABLE__PARSER___POR 0x0 +#define UMAC_TCL_R0_CLKGATE_DISABLE__CLK_ENS_EXTEND___M 0x80000000 +#define UMAC_TCL_R0_CLKGATE_DISABLE__CLK_ENS_EXTEND___S 31 +#define UMAC_TCL_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___M 0x40000000 +#define UMAC_TCL_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___S 30 +#define UMAC_TCL_R0_CLKGATE_DISABLE__APB_CLK___M 0x20000000 +#define UMAC_TCL_R0_CLKGATE_DISABLE__APB_CLK___S 29 +#define UMAC_TCL_R0_CLKGATE_DISABLE__FSE___M 0x10000000 +#define UMAC_TCL_R0_CLKGATE_DISABLE__FSE___S 28 +#define UMAC_TCL_R0_CLKGATE_DISABLE__CLFY_RES_MEM___M 0x08000000 +#define UMAC_TCL_R0_CLKGATE_DISABLE__CLFY_RES_MEM___S 27 +#define UMAC_TCL_R0_CLKGATE_DISABLE__GSE_CTRL___M 0x04000000 +#define UMAC_TCL_R0_CLKGATE_DISABLE__GSE_CTRL___S 26 +#define UMAC_TCL_R0_CLKGATE_DISABLE__GSE_CCE_RES___M 0x02000000 +#define UMAC_TCL_R0_CLKGATE_DISABLE__GSE_CCE_RES___S 25 +#define UMAC_TCL_R0_CLKGATE_DISABLE__TCL2_STATUS2_PROD_RING___M 0x01000000 +#define UMAC_TCL_R0_CLKGATE_DISABLE__TCL2_STATUS2_PROD_RING___S 24 +#define UMAC_TCL_R0_CLKGATE_DISABLE__TCL2_STATUS1_PROD_RING___M 0x00800000 +#define UMAC_TCL_R0_CLKGATE_DISABLE__TCL2_STATUS1_PROD_RING___S 23 +#define UMAC_TCL_R0_CLKGATE_DISABLE__TCL2FW_PROD_RING___M 0x00400000 +#define UMAC_TCL_R0_CLKGATE_DISABLE__TCL2FW_PROD_RING___S 22 +#define UMAC_TCL_R0_CLKGATE_DISABLE__TCL2TQM_PROD_RING___M 0x00200000 +#define UMAC_TCL_R0_CLKGATE_DISABLE__TCL2TQM_PROD_RING___S 21 +#define UMAC_TCL_R0_CLKGATE_DISABLE__PROD_RING_CTRL___M 0x00100000 +#define UMAC_TCL_R0_CLKGATE_DISABLE__PROD_RING_CTRL___S 20 +#define UMAC_TCL_R0_CLKGATE_DISABLE__TLV_DECODE___M 0x00080000 +#define UMAC_TCL_R0_CLKGATE_DISABLE__TLV_DECODE___S 19 +#define UMAC_TCL_R0_CLKGATE_DISABLE__TLV_GEN___M 0x00040000 +#define UMAC_TCL_R0_CLKGATE_DISABLE__TLV_GEN___S 18 +#define UMAC_TCL_R0_CLKGATE_DISABLE__DATA_FETCH___M 0x00020000 +#define UMAC_TCL_R0_CLKGATE_DISABLE__DATA_FETCH___S 17 +#define UMAC_TCL_R0_CLKGATE_DISABLE__DATA_BUF___M 0x00010000 +#define UMAC_TCL_R0_CLKGATE_DISABLE__DATA_BUF___S 16 +#define UMAC_TCL_R0_CLKGATE_DISABLE__DESC_BUF___M 0x00008000 +#define UMAC_TCL_R0_CLKGATE_DISABLE__DESC_BUF___S 15 +#define UMAC_TCL_R0_CLKGATE_DISABLE__DESC_RD___M 0x00004000 +#define UMAC_TCL_R0_CLKGATE_DISABLE__DESC_RD___S 14 +#define UMAC_TCL_R0_CLKGATE_DISABLE__ASE___M 0x00002000 +#define UMAC_TCL_R0_CLKGATE_DISABLE__ASE___S 13 +#define UMAC_TCL_R0_CLKGATE_DISABLE__GXI___M 0x00001000 +#define UMAC_TCL_R0_CLKGATE_DISABLE__GXI___S 12 +#define UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_P_3___M 0x00000800 +#define UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_P_3___S 11 +#define UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_P_2___M 0x00000400 +#define UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_P_2___S 10 +#define UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_P_1___M 0x00000200 +#define UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_P_1___S 9 +#define UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_P_0___M 0x00000100 +#define UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_P_0___S 8 +#define UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_C_4___M 0x00000080 +#define UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_C_4___S 7 +#define UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_C_3___M 0x00000040 +#define UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_C_3___S 6 +#define UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_C_2___M 0x00000020 +#define UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_C_2___S 5 +#define UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_C_1___M 0x00000010 +#define UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_C_1___S 4 +#define UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_C_0___M 0x00000008 +#define UMAC_TCL_R0_CLKGATE_DISABLE__SRNG_C_0___S 3 +#define UMAC_TCL_R0_CLKGATE_DISABLE__TCL_IDLE_REQ_SM___M 0x00000004 +#define UMAC_TCL_R0_CLKGATE_DISABLE__TCL_IDLE_REQ_SM___S 2 +#define UMAC_TCL_R0_CLKGATE_DISABLE__LCE_CCE___M 0x00000002 +#define UMAC_TCL_R0_CLKGATE_DISABLE__LCE_CCE___S 1 +#define UMAC_TCL_R0_CLKGATE_DISABLE__PARSER___M 0x00000001 +#define UMAC_TCL_R0_CLKGATE_DISABLE__PARSER___S 0 +#define UMAC_TCL_R0_CLKGATE_DISABLE___M 0xFFFFFFFF +#define UMAC_TCL_R0_CLKGATE_DISABLE___S 0 + +#define UMAC_TCL_R0_CREDIT_COUNT (0x00A44684) +#define UMAC_TCL_R0_CREDIT_COUNT___RWC QCSR_REG_RW +#define UMAC_TCL_R0_CREDIT_COUNT___POR 0x00000000 +#define UMAC_TCL_R0_CREDIT_COUNT__ENABLE___POR 0x0 +#define UMAC_TCL_R0_CREDIT_COUNT__VAL___POR 0x0000 +#define UMAC_TCL_R0_CREDIT_COUNT__ENABLE___M 0x00010000 +#define UMAC_TCL_R0_CREDIT_COUNT__ENABLE___S 16 +#define UMAC_TCL_R0_CREDIT_COUNT__VAL___M 0x0000FFFF +#define UMAC_TCL_R0_CREDIT_COUNT__VAL___S 0 +#define UMAC_TCL_R0_CREDIT_COUNT___M 0x0001FFFF +#define UMAC_TCL_R0_CREDIT_COUNT___S 0 + +#define UMAC_TCL_R0_CURRENT_CREDIT_COUNT (0x00A44688) +#define UMAC_TCL_R0_CURRENT_CREDIT_COUNT___RWC QCSR_REG_RO +#define UMAC_TCL_R0_CURRENT_CREDIT_COUNT___POR 0x00000000 +#define UMAC_TCL_R0_CURRENT_CREDIT_COUNT__VAL___POR 0x0000 +#define UMAC_TCL_R0_CURRENT_CREDIT_COUNT__VAL___M 0x0000FFFF +#define UMAC_TCL_R0_CURRENT_CREDIT_COUNT__VAL___S 0 +#define UMAC_TCL_R0_CURRENT_CREDIT_COUNT___M 0x0000FFFF +#define UMAC_TCL_R0_CURRENT_CREDIT_COUNT___S 0 + +#define UMAC_TCL_R0_S_PARE_REGISTER (0x00A4468C) +#define UMAC_TCL_R0_S_PARE_REGISTER___RWC QCSR_REG_RW +#define UMAC_TCL_R0_S_PARE_REGISTER___POR 0x00000000 +#define UMAC_TCL_R0_S_PARE_REGISTER__VAL___POR 0x00000000 +#define UMAC_TCL_R0_S_PARE_REGISTER__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_S_PARE_REGISTER__VAL___S 0 +#define UMAC_TCL_R0_S_PARE_REGISTER___M 0xFFFFFFFF +#define UMAC_TCL_R0_S_PARE_REGISTER___S 0 + +#define UMAC_TCL_R0_SW2TCL1_RING_BASE_LSB (0x00A44690) +#define UMAC_TCL_R0_SW2TCL1_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL1_RING_BASE_LSB___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL1_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL1_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL1_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_TCL_R0_SW2TCL1_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL1_RING_BASE_LSB___S 0 + +#define UMAC_TCL_R0_SW2TCL1_RING_BASE_MSB (0x00A44694) +#define UMAC_TCL_R0_SW2TCL1_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL1_RING_BASE_MSB___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL1_RING_BASE_MSB__RING_SIZE___POR 0x00000 +#define UMAC_TCL_R0_SW2TCL1_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_TCL_R0_SW2TCL1_RING_BASE_MSB__RING_SIZE___M 0x0FFFFF00 +#define UMAC_TCL_R0_SW2TCL1_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_TCL_R0_SW2TCL1_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_TCL_R0_SW2TCL1_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_TCL_R0_SW2TCL1_RING_BASE_MSB___M 0x0FFFFFFF +#define UMAC_TCL_R0_SW2TCL1_RING_BASE_MSB___S 0 + +#define UMAC_TCL_R0_SW2TCL1_RING_ID (0x00A44698) +#define UMAC_TCL_R0_SW2TCL1_RING_ID___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL1_RING_ID___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL1_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_TCL_R0_SW2TCL1_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_TCL_R0_SW2TCL1_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_TCL_R0_SW2TCL1_RING_ID___M 0x000000FF +#define UMAC_TCL_R0_SW2TCL1_RING_ID___S 0 + +#define UMAC_TCL_R0_SW2TCL1_RING_STATUS (0x00A4469C) +#define UMAC_TCL_R0_SW2TCL1_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_TCL_R0_SW2TCL1_RING_STATUS___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL1_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_TCL_R0_SW2TCL1_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_TCL_R0_SW2TCL1_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_TCL_R0_SW2TCL1_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_TCL_R0_SW2TCL1_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_TCL_R0_SW2TCL1_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_TCL_R0_SW2TCL1_RING_STATUS___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL1_RING_STATUS___S 0 + +#define UMAC_TCL_R0_SW2TCL1_RING_MISC (0x00A446A0) +#define UMAC_TCL_R0_SW2TCL1_RING_MISC___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL1_RING_MISC___POR 0x00000080 +#define UMAC_TCL_R0_SW2TCL1_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_TCL_R0_SW2TCL1_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_TCL_R0_SW2TCL1_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_TCL_R0_SW2TCL1_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_TCL_R0_SW2TCL1_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_TCL_R0_SW2TCL1_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_TCL_R0_SW2TCL1_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_TCL_R0_SW2TCL1_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_TCL_R0_SW2TCL1_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_TCL_R0_SW2TCL1_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_TCL_R0_SW2TCL1_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_TCL_R0_SW2TCL1_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_TCL_R0_SW2TCL1_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_TCL_R0_SW2TCL1_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_TCL_R0_SW2TCL1_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_TCL_R0_SW2TCL1_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_TCL_R0_SW2TCL1_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_TCL_R0_SW2TCL1_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_TCL_R0_SW2TCL1_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_TCL_R0_SW2TCL1_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_TCL_R0_SW2TCL1_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_TCL_R0_SW2TCL1_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_TCL_R0_SW2TCL1_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_TCL_R0_SW2TCL1_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_TCL_R0_SW2TCL1_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_TCL_R0_SW2TCL1_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_TCL_R0_SW2TCL1_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_TCL_R0_SW2TCL1_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_TCL_R0_SW2TCL1_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_TCL_R0_SW2TCL1_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_TCL_R0_SW2TCL1_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_TCL_R0_SW2TCL1_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_TCL_R0_SW2TCL1_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_TCL_R0_SW2TCL1_RING_MISC___M 0x003FFFFF +#define UMAC_TCL_R0_SW2TCL1_RING_MISC___S 0 + +#define UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB (0x00A446AC) +#define UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S 0 +#define UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB___S 0 + +#define UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB (0x00A446B0) +#define UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S 0 +#define UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB___M 0x000000FF +#define UMAC_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB___S 0 + +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0 (0x00A446C0) +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S 15 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0___S 0 + +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1 (0x00A446C4) +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S 0 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1___S 0 + +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS (0x00A446C8) +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S 15 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS___S 0 + +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER (0x00A446CC) +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S 0 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER___S 0 + +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER (0x00A446D0) +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER__MODE___S 0 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER___S 0 + +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS (0x00A446D4) +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x00000 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x0FF00000 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S 20 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x000FFFFF +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S 0 +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS___M 0x0FFFFFFF +#define UMAC_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS___S 0 + +#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB (0x00A446D8) +#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB (0x00A446DC) +#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_DATA (0x00A446E0) +#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL1_RING_MSI1_DATA___S 0 + +#define UMAC_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET (0x00A446E4) +#define UMAC_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_TCL_R0_SW2TCL2_RING_BASE_LSB (0x00A446E8) +#define UMAC_TCL_R0_SW2TCL2_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL2_RING_BASE_LSB___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL2_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL2_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL2_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_TCL_R0_SW2TCL2_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL2_RING_BASE_LSB___S 0 + +#define UMAC_TCL_R0_SW2TCL2_RING_BASE_MSB (0x00A446EC) +#define UMAC_TCL_R0_SW2TCL2_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL2_RING_BASE_MSB___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL2_RING_BASE_MSB__RING_SIZE___POR 0x00000 +#define UMAC_TCL_R0_SW2TCL2_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_TCL_R0_SW2TCL2_RING_BASE_MSB__RING_SIZE___M 0x0FFFFF00 +#define UMAC_TCL_R0_SW2TCL2_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_TCL_R0_SW2TCL2_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_TCL_R0_SW2TCL2_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_TCL_R0_SW2TCL2_RING_BASE_MSB___M 0x0FFFFFFF +#define UMAC_TCL_R0_SW2TCL2_RING_BASE_MSB___S 0 + +#define UMAC_TCL_R0_SW2TCL2_RING_ID (0x00A446F0) +#define UMAC_TCL_R0_SW2TCL2_RING_ID___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL2_RING_ID___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL2_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_TCL_R0_SW2TCL2_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_TCL_R0_SW2TCL2_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_TCL_R0_SW2TCL2_RING_ID___M 0x000000FF +#define UMAC_TCL_R0_SW2TCL2_RING_ID___S 0 + +#define UMAC_TCL_R0_SW2TCL2_RING_STATUS (0x00A446F4) +#define UMAC_TCL_R0_SW2TCL2_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_TCL_R0_SW2TCL2_RING_STATUS___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL2_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_TCL_R0_SW2TCL2_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_TCL_R0_SW2TCL2_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_TCL_R0_SW2TCL2_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_TCL_R0_SW2TCL2_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_TCL_R0_SW2TCL2_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_TCL_R0_SW2TCL2_RING_STATUS___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL2_RING_STATUS___S 0 + +#define UMAC_TCL_R0_SW2TCL2_RING_MISC (0x00A446F8) +#define UMAC_TCL_R0_SW2TCL2_RING_MISC___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL2_RING_MISC___POR 0x00000080 +#define UMAC_TCL_R0_SW2TCL2_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_TCL_R0_SW2TCL2_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_TCL_R0_SW2TCL2_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_TCL_R0_SW2TCL2_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_TCL_R0_SW2TCL2_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_TCL_R0_SW2TCL2_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_TCL_R0_SW2TCL2_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_TCL_R0_SW2TCL2_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_TCL_R0_SW2TCL2_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_TCL_R0_SW2TCL2_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_TCL_R0_SW2TCL2_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_TCL_R0_SW2TCL2_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_TCL_R0_SW2TCL2_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_TCL_R0_SW2TCL2_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_TCL_R0_SW2TCL2_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_TCL_R0_SW2TCL2_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_TCL_R0_SW2TCL2_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_TCL_R0_SW2TCL2_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_TCL_R0_SW2TCL2_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_TCL_R0_SW2TCL2_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_TCL_R0_SW2TCL2_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_TCL_R0_SW2TCL2_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_TCL_R0_SW2TCL2_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_TCL_R0_SW2TCL2_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_TCL_R0_SW2TCL2_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_TCL_R0_SW2TCL2_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_TCL_R0_SW2TCL2_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_TCL_R0_SW2TCL2_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_TCL_R0_SW2TCL2_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_TCL_R0_SW2TCL2_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_TCL_R0_SW2TCL2_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_TCL_R0_SW2TCL2_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_TCL_R0_SW2TCL2_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_TCL_R0_SW2TCL2_RING_MISC___M 0x003FFFFF +#define UMAC_TCL_R0_SW2TCL2_RING_MISC___S 0 + +#define UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB (0x00A44704) +#define UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S 0 +#define UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB___S 0 + +#define UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB (0x00A44708) +#define UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S 0 +#define UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB___M 0x000000FF +#define UMAC_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB___S 0 + +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0 (0x00A44718) +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S 15 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0___S 0 + +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1 (0x00A4471C) +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S 0 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1___S 0 + +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS (0x00A44720) +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S 15 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS___S 0 + +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER (0x00A44724) +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S 0 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER___S 0 + +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER (0x00A44728) +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER__MODE___S 0 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER___S 0 + +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS (0x00A4472C) +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x00000 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x0FF00000 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S 20 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x000FFFFF +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S 0 +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS___M 0x0FFFFFFF +#define UMAC_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS___S 0 + +#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB (0x00A44730) +#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB (0x00A44734) +#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_DATA (0x00A44738) +#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL2_RING_MSI1_DATA___S 0 + +#define UMAC_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET (0x00A4473C) +#define UMAC_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_TCL_R0_SW2TCL3_RING_BASE_LSB (0x00A44740) +#define UMAC_TCL_R0_SW2TCL3_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL3_RING_BASE_LSB___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL3_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL3_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL3_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_TCL_R0_SW2TCL3_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL3_RING_BASE_LSB___S 0 + +#define UMAC_TCL_R0_SW2TCL3_RING_BASE_MSB (0x00A44744) +#define UMAC_TCL_R0_SW2TCL3_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL3_RING_BASE_MSB___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL3_RING_BASE_MSB__RING_SIZE___POR 0x00000 +#define UMAC_TCL_R0_SW2TCL3_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_TCL_R0_SW2TCL3_RING_BASE_MSB__RING_SIZE___M 0x0FFFFF00 +#define UMAC_TCL_R0_SW2TCL3_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_TCL_R0_SW2TCL3_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_TCL_R0_SW2TCL3_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_TCL_R0_SW2TCL3_RING_BASE_MSB___M 0x0FFFFFFF +#define UMAC_TCL_R0_SW2TCL3_RING_BASE_MSB___S 0 + +#define UMAC_TCL_R0_SW2TCL3_RING_ID (0x00A44748) +#define UMAC_TCL_R0_SW2TCL3_RING_ID___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL3_RING_ID___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL3_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_TCL_R0_SW2TCL3_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_TCL_R0_SW2TCL3_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_TCL_R0_SW2TCL3_RING_ID___M 0x000000FF +#define UMAC_TCL_R0_SW2TCL3_RING_ID___S 0 + +#define UMAC_TCL_R0_SW2TCL3_RING_STATUS (0x00A4474C) +#define UMAC_TCL_R0_SW2TCL3_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_TCL_R0_SW2TCL3_RING_STATUS___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL3_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_TCL_R0_SW2TCL3_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_TCL_R0_SW2TCL3_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_TCL_R0_SW2TCL3_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_TCL_R0_SW2TCL3_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_TCL_R0_SW2TCL3_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_TCL_R0_SW2TCL3_RING_STATUS___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL3_RING_STATUS___S 0 + +#define UMAC_TCL_R0_SW2TCL3_RING_MISC (0x00A44750) +#define UMAC_TCL_R0_SW2TCL3_RING_MISC___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL3_RING_MISC___POR 0x00000080 +#define UMAC_TCL_R0_SW2TCL3_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_TCL_R0_SW2TCL3_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_TCL_R0_SW2TCL3_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_TCL_R0_SW2TCL3_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_TCL_R0_SW2TCL3_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_TCL_R0_SW2TCL3_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_TCL_R0_SW2TCL3_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_TCL_R0_SW2TCL3_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_TCL_R0_SW2TCL3_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_TCL_R0_SW2TCL3_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_TCL_R0_SW2TCL3_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_TCL_R0_SW2TCL3_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_TCL_R0_SW2TCL3_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_TCL_R0_SW2TCL3_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_TCL_R0_SW2TCL3_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_TCL_R0_SW2TCL3_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_TCL_R0_SW2TCL3_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_TCL_R0_SW2TCL3_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_TCL_R0_SW2TCL3_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_TCL_R0_SW2TCL3_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_TCL_R0_SW2TCL3_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_TCL_R0_SW2TCL3_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_TCL_R0_SW2TCL3_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_TCL_R0_SW2TCL3_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_TCL_R0_SW2TCL3_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_TCL_R0_SW2TCL3_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_TCL_R0_SW2TCL3_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_TCL_R0_SW2TCL3_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_TCL_R0_SW2TCL3_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_TCL_R0_SW2TCL3_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_TCL_R0_SW2TCL3_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_TCL_R0_SW2TCL3_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_TCL_R0_SW2TCL3_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_TCL_R0_SW2TCL3_RING_MISC___M 0x003FFFFF +#define UMAC_TCL_R0_SW2TCL3_RING_MISC___S 0 + +#define UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB (0x00A4475C) +#define UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S 0 +#define UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB___S 0 + +#define UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB (0x00A44760) +#define UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S 0 +#define UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB___M 0x000000FF +#define UMAC_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB___S 0 + +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0 (0x00A44770) +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S 15 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0___S 0 + +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1 (0x00A44774) +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S 0 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1___S 0 + +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS (0x00A44778) +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S 15 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS___S 0 + +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER (0x00A4477C) +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S 0 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER___S 0 + +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER (0x00A44780) +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER__MODE___S 0 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER___S 0 + +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS (0x00A44784) +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x00000 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x0FF00000 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S 20 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x000FFFFF +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S 0 +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS___M 0x0FFFFFFF +#define UMAC_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS___S 0 + +#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB (0x00A44788) +#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB (0x00A4478C) +#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_DATA (0x00A44790) +#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL3_RING_MSI1_DATA___S 0 + +#define UMAC_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET (0x00A44794) +#define UMAC_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB (0x00A44798) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB___S 0 + +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB (0x00A4479C) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB__RING_SIZE___POR 0x00000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB__RING_SIZE___M 0x0FFFFF00 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB___M 0x0FFFFFFF +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB___S 0 + +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_ID (0x00A447A0) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_ID___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_ID___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_ID___M 0x000000FF +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_ID___S 0 + +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_STATUS (0x00A447A4) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_STATUS___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_STATUS___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_STATUS___S 0 + +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC (0x00A447A8) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC___POR 0x00000080 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC___M 0x003FFFFF +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MISC___S 0 + +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB (0x00A447B4) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S 0 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB___S 0 + +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB (0x00A447B8) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S 0 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB___M 0x000000FF +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB___S 0 + +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0 (0x00A447C8) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S 15 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0___S 0 + +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1 (0x00A447CC) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S 0 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1___S 0 + +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS (0x00A447D0) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S 15 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS___S 0 + +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER (0x00A447D4) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S 0 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER___S 0 + +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER (0x00A447D8) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER__MODE___S 0 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER___S 0 + +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS (0x00A447DC) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x00000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x0FF00000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S 20 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x000FFFFF +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S 0 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS___M 0x0FFFFFFF +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS___S 0 + +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB (0x00A447E0) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB (0x00A447E4) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA (0x00A447E8) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA___S 0 + +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET (0x00A447EC) +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_TCL_R0_FW2TCL1_RING_BASE_LSB (0x00A447F0) +#define UMAC_TCL_R0_FW2TCL1_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_FW2TCL1_RING_BASE_LSB___POR 0x00000000 +#define UMAC_TCL_R0_FW2TCL1_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_TCL_R0_FW2TCL1_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_FW2TCL1_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_TCL_R0_FW2TCL1_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_FW2TCL1_RING_BASE_LSB___S 0 + +#define UMAC_TCL_R0_FW2TCL1_RING_BASE_MSB (0x00A447F4) +#define UMAC_TCL_R0_FW2TCL1_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_FW2TCL1_RING_BASE_MSB___POR 0x00000000 +#define UMAC_TCL_R0_FW2TCL1_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_TCL_R0_FW2TCL1_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_TCL_R0_FW2TCL1_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_TCL_R0_FW2TCL1_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_TCL_R0_FW2TCL1_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_TCL_R0_FW2TCL1_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_TCL_R0_FW2TCL1_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_TCL_R0_FW2TCL1_RING_BASE_MSB___S 0 + +#define UMAC_TCL_R0_FW2TCL1_RING_ID (0x00A447F8) +#define UMAC_TCL_R0_FW2TCL1_RING_ID___RWC QCSR_REG_RW +#define UMAC_TCL_R0_FW2TCL1_RING_ID___POR 0x00000000 +#define UMAC_TCL_R0_FW2TCL1_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_TCL_R0_FW2TCL1_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_TCL_R0_FW2TCL1_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_TCL_R0_FW2TCL1_RING_ID___M 0x000000FF +#define UMAC_TCL_R0_FW2TCL1_RING_ID___S 0 + +#define UMAC_TCL_R0_FW2TCL1_RING_STATUS (0x00A447FC) +#define UMAC_TCL_R0_FW2TCL1_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_TCL_R0_FW2TCL1_RING_STATUS___POR 0x00000000 +#define UMAC_TCL_R0_FW2TCL1_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_TCL_R0_FW2TCL1_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_TCL_R0_FW2TCL1_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_TCL_R0_FW2TCL1_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_TCL_R0_FW2TCL1_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_TCL_R0_FW2TCL1_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_TCL_R0_FW2TCL1_RING_STATUS___M 0xFFFFFFFF +#define UMAC_TCL_R0_FW2TCL1_RING_STATUS___S 0 + +#define UMAC_TCL_R0_FW2TCL1_RING_MISC (0x00A44800) +#define UMAC_TCL_R0_FW2TCL1_RING_MISC___RWC QCSR_REG_RW +#define UMAC_TCL_R0_FW2TCL1_RING_MISC___POR 0x00000080 +#define UMAC_TCL_R0_FW2TCL1_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_TCL_R0_FW2TCL1_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_TCL_R0_FW2TCL1_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_TCL_R0_FW2TCL1_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_TCL_R0_FW2TCL1_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_TCL_R0_FW2TCL1_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_TCL_R0_FW2TCL1_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_TCL_R0_FW2TCL1_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_TCL_R0_FW2TCL1_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_TCL_R0_FW2TCL1_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_TCL_R0_FW2TCL1_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_TCL_R0_FW2TCL1_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_TCL_R0_FW2TCL1_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_TCL_R0_FW2TCL1_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_TCL_R0_FW2TCL1_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_TCL_R0_FW2TCL1_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_TCL_R0_FW2TCL1_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_TCL_R0_FW2TCL1_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_TCL_R0_FW2TCL1_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_TCL_R0_FW2TCL1_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_TCL_R0_FW2TCL1_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_TCL_R0_FW2TCL1_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_TCL_R0_FW2TCL1_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_TCL_R0_FW2TCL1_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_TCL_R0_FW2TCL1_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_TCL_R0_FW2TCL1_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_TCL_R0_FW2TCL1_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_TCL_R0_FW2TCL1_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_TCL_R0_FW2TCL1_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_TCL_R0_FW2TCL1_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_TCL_R0_FW2TCL1_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_TCL_R0_FW2TCL1_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_TCL_R0_FW2TCL1_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_TCL_R0_FW2TCL1_RING_MISC___M 0x003FFFFF +#define UMAC_TCL_R0_FW2TCL1_RING_MISC___S 0 + +#define UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB (0x00A4480C) +#define UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB___POR 0x00000000 +#define UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S 0 +#define UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB___S 0 + +#define UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB (0x00A44810) +#define UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB___POR 0x00000000 +#define UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S 0 +#define UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB___M 0x000000FF +#define UMAC_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB___S 0 + +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0 (0x00A44820) +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S 15 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0___S 0 + +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1 (0x00A44824) +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S 0 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1___S 0 + +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS (0x00A44828) +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS___POR 0x00000000 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S 15 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS___S 0 + +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER (0x00A4482C) +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S 0 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER___S 0 + +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER (0x00A44830) +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER__MODE___S 0 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER___S 0 + +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS (0x00A44834) +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S 16 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S 0 +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF +#define UMAC_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS___S 0 + +#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB (0x00A44838) +#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB (0x00A4483C) +#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_DATA (0x00A44840) +#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_TCL_R0_FW2TCL1_RING_MSI1_DATA___S 0 + +#define UMAC_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET (0x00A44844) +#define UMAC_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_TCL_R0_TCL2TQM_RING_BASE_LSB (0x00A44848) +#define UMAC_TCL_R0_TCL2TQM_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL2TQM_RING_BASE_LSB___POR 0x00000000 +#define UMAC_TCL_R0_TCL2TQM_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_TCL_R0_TCL2TQM_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL2TQM_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_TCL_R0_TCL2TQM_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL2TQM_RING_BASE_LSB___S 0 + +#define UMAC_TCL_R0_TCL2TQM_RING_BASE_MSB (0x00A4484C) +#define UMAC_TCL_R0_TCL2TQM_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL2TQM_RING_BASE_MSB___POR 0x00000000 +#define UMAC_TCL_R0_TCL2TQM_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_TCL_R0_TCL2TQM_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_TCL_R0_TCL2TQM_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_TCL_R0_TCL2TQM_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_TCL_R0_TCL2TQM_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_TCL_R0_TCL2TQM_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_TCL_R0_TCL2TQM_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_TCL_R0_TCL2TQM_RING_BASE_MSB___S 0 + +#define UMAC_TCL_R0_TCL2TQM_RING_ID (0x00A44850) +#define UMAC_TCL_R0_TCL2TQM_RING_ID___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL2TQM_RING_ID___POR 0x00000000 +#define UMAC_TCL_R0_TCL2TQM_RING_ID__RING_ID___POR 0x00 +#define UMAC_TCL_R0_TCL2TQM_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_TCL_R0_TCL2TQM_RING_ID__RING_ID___M 0x0000FF00 +#define UMAC_TCL_R0_TCL2TQM_RING_ID__RING_ID___S 8 +#define UMAC_TCL_R0_TCL2TQM_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_TCL_R0_TCL2TQM_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_TCL_R0_TCL2TQM_RING_ID___M 0x0000FFFF +#define UMAC_TCL_R0_TCL2TQM_RING_ID___S 0 + +#define UMAC_TCL_R0_TCL2TQM_RING_STATUS (0x00A44854) +#define UMAC_TCL_R0_TCL2TQM_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_TCL_R0_TCL2TQM_RING_STATUS___POR 0x00000000 +#define UMAC_TCL_R0_TCL2TQM_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_TCL_R0_TCL2TQM_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_TCL_R0_TCL2TQM_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_TCL_R0_TCL2TQM_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_TCL_R0_TCL2TQM_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_TCL_R0_TCL2TQM_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_TCL_R0_TCL2TQM_RING_STATUS___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL2TQM_RING_STATUS___S 0 + +#define UMAC_TCL_R0_TCL2TQM_RING_MISC (0x00A44858) +#define UMAC_TCL_R0_TCL2TQM_RING_MISC___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL2TQM_RING_MISC___POR 0x00000080 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__LOOP_CNT___POR 0x0 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__LOOP_CNT___M 0x03C00000 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__LOOP_CNT___S 22 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_TCL_R0_TCL2TQM_RING_MISC___M 0x03FFFFFF +#define UMAC_TCL_R0_TCL2TQM_RING_MISC___S 0 + +#define UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB (0x00A4485C) +#define UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB___POR 0x00000000 +#define UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB___S 0 + +#define UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB (0x00A44860) +#define UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB___POR 0x00000000 +#define UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB___M 0x000000FF +#define UMAC_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB___S 0 + +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP (0x00A4486C) +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP___S 0 + +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS (0x00A44870) +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS___S 0 + +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER (0x00A44874) +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define UMAC_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER___S 0 + +#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB (0x00A44890) +#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB (0x00A44894) +#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_DATA (0x00A44898) +#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL2TQM_RING_MSI1_DATA___S 0 + +#define UMAC_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET (0x00A4489C) +#define UMAC_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_LSB (0x00A448A0) +#define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_LSB___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_LSB___S 0 + +#define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_MSB (0x00A448A4) +#define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_MSB___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_TCL_R0_TCL_STATUS1_RING_BASE_MSB___S 0 + +#define UMAC_TCL_R0_TCL_STATUS1_RING_ID (0x00A448A8) +#define UMAC_TCL_R0_TCL_STATUS1_RING_ID___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL_STATUS1_RING_ID___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_ID__RING_ID___POR 0x00 +#define UMAC_TCL_R0_TCL_STATUS1_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_TCL_R0_TCL_STATUS1_RING_ID__RING_ID___M 0x0000FF00 +#define UMAC_TCL_R0_TCL_STATUS1_RING_ID__RING_ID___S 8 +#define UMAC_TCL_R0_TCL_STATUS1_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_TCL_R0_TCL_STATUS1_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_TCL_R0_TCL_STATUS1_RING_ID___M 0x0000FFFF +#define UMAC_TCL_R0_TCL_STATUS1_RING_ID___S 0 + +#define UMAC_TCL_R0_TCL_STATUS1_RING_STATUS (0x00A448AC) +#define UMAC_TCL_R0_TCL_STATUS1_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_TCL_R0_TCL_STATUS1_RING_STATUS___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_TCL_R0_TCL_STATUS1_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_TCL_R0_TCL_STATUS1_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_TCL_R0_TCL_STATUS1_RING_STATUS___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL_STATUS1_RING_STATUS___S 0 + +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC (0x00A448B0) +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC___POR 0x00000080 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__LOOP_CNT___POR 0x0 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__LOOP_CNT___M 0x03C00000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__LOOP_CNT___S 22 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC___M 0x03FFFFFF +#define UMAC_TCL_R0_TCL_STATUS1_RING_MISC___S 0 + +#define UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB (0x00A448B4) +#define UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB___S 0 + +#define UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB (0x00A448B8) +#define UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB___M 0x000000FF +#define UMAC_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB___S 0 + +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP (0x00A448C4) +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP___S 0 + +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS (0x00A448C8) +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS___S 0 + +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER (0x00A448CC) +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define UMAC_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER___S 0 + +#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB (0x00A448E8) +#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB (0x00A448EC) +#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_DATA (0x00A448F0) +#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL_STATUS1_RING_MSI1_DATA___S 0 + +#define UMAC_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET (0x00A448F4) +#define UMAC_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_LSB (0x00A448F8) +#define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_LSB___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_LSB___S 0 + +#define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_MSB (0x00A448FC) +#define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_MSB___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_TCL_R0_TCL_STATUS2_RING_BASE_MSB___S 0 + +#define UMAC_TCL_R0_TCL_STATUS2_RING_ID (0x00A44900) +#define UMAC_TCL_R0_TCL_STATUS2_RING_ID___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL_STATUS2_RING_ID___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_ID__RING_ID___POR 0x00 +#define UMAC_TCL_R0_TCL_STATUS2_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_TCL_R0_TCL_STATUS2_RING_ID__RING_ID___M 0x0000FF00 +#define UMAC_TCL_R0_TCL_STATUS2_RING_ID__RING_ID___S 8 +#define UMAC_TCL_R0_TCL_STATUS2_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_TCL_R0_TCL_STATUS2_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_TCL_R0_TCL_STATUS2_RING_ID___M 0x0000FFFF +#define UMAC_TCL_R0_TCL_STATUS2_RING_ID___S 0 + +#define UMAC_TCL_R0_TCL_STATUS2_RING_STATUS (0x00A44904) +#define UMAC_TCL_R0_TCL_STATUS2_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_TCL_R0_TCL_STATUS2_RING_STATUS___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_TCL_R0_TCL_STATUS2_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_TCL_R0_TCL_STATUS2_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_TCL_R0_TCL_STATUS2_RING_STATUS___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL_STATUS2_RING_STATUS___S 0 + +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC (0x00A44908) +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC___POR 0x00000080 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__LOOP_CNT___POR 0x0 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__LOOP_CNT___M 0x03C00000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__LOOP_CNT___S 22 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC___M 0x03FFFFFF +#define UMAC_TCL_R0_TCL_STATUS2_RING_MISC___S 0 + +#define UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB (0x00A4490C) +#define UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB___S 0 + +#define UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB (0x00A44910) +#define UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB___M 0x000000FF +#define UMAC_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB___S 0 + +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP (0x00A4491C) +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP___S 0 + +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS (0x00A44920) +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS___S 0 + +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER (0x00A44924) +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define UMAC_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER___S 0 + +#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB (0x00A44940) +#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB (0x00A44944) +#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_DATA (0x00A44948) +#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL_STATUS2_RING_MSI1_DATA___S 0 + +#define UMAC_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET (0x00A4494C) +#define UMAC_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_TCL_R0_TCL2FW_RING_BASE_LSB (0x00A44950) +#define UMAC_TCL_R0_TCL2FW_RING_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL2FW_RING_BASE_LSB___POR 0x00000000 +#define UMAC_TCL_R0_TCL2FW_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define UMAC_TCL_R0_TCL2FW_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL2FW_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define UMAC_TCL_R0_TCL2FW_RING_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL2FW_RING_BASE_LSB___S 0 + +#define UMAC_TCL_R0_TCL2FW_RING_BASE_MSB (0x00A44954) +#define UMAC_TCL_R0_TCL2FW_RING_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL2FW_RING_BASE_MSB___POR 0x00000000 +#define UMAC_TCL_R0_TCL2FW_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define UMAC_TCL_R0_TCL2FW_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define UMAC_TCL_R0_TCL2FW_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define UMAC_TCL_R0_TCL2FW_RING_BASE_MSB__RING_SIZE___S 8 +#define UMAC_TCL_R0_TCL2FW_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define UMAC_TCL_R0_TCL2FW_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define UMAC_TCL_R0_TCL2FW_RING_BASE_MSB___M 0x00FFFFFF +#define UMAC_TCL_R0_TCL2FW_RING_BASE_MSB___S 0 + +#define UMAC_TCL_R0_TCL2FW_RING_ID (0x00A44958) +#define UMAC_TCL_R0_TCL2FW_RING_ID___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL2FW_RING_ID___POR 0x00000000 +#define UMAC_TCL_R0_TCL2FW_RING_ID__RING_ID___POR 0x00 +#define UMAC_TCL_R0_TCL2FW_RING_ID__ENTRY_SIZE___POR 0x00 +#define UMAC_TCL_R0_TCL2FW_RING_ID__RING_ID___M 0x0000FF00 +#define UMAC_TCL_R0_TCL2FW_RING_ID__RING_ID___S 8 +#define UMAC_TCL_R0_TCL2FW_RING_ID__ENTRY_SIZE___M 0x000000FF +#define UMAC_TCL_R0_TCL2FW_RING_ID__ENTRY_SIZE___S 0 +#define UMAC_TCL_R0_TCL2FW_RING_ID___M 0x0000FFFF +#define UMAC_TCL_R0_TCL2FW_RING_ID___S 0 + +#define UMAC_TCL_R0_TCL2FW_RING_STATUS (0x00A4495C) +#define UMAC_TCL_R0_TCL2FW_RING_STATUS___RWC QCSR_REG_RO +#define UMAC_TCL_R0_TCL2FW_RING_STATUS___POR 0x00000000 +#define UMAC_TCL_R0_TCL2FW_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define UMAC_TCL_R0_TCL2FW_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define UMAC_TCL_R0_TCL2FW_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define UMAC_TCL_R0_TCL2FW_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define UMAC_TCL_R0_TCL2FW_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define UMAC_TCL_R0_TCL2FW_RING_STATUS__NUM_VALID_WORDS___S 0 +#define UMAC_TCL_R0_TCL2FW_RING_STATUS___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL2FW_RING_STATUS___S 0 + +#define UMAC_TCL_R0_TCL2FW_RING_MISC (0x00A44960) +#define UMAC_TCL_R0_TCL2FW_RING_MISC___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL2FW_RING_MISC___POR 0x00000080 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__LOOP_CNT___POR 0x0 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__SPARE_CONTROL___POR 0x00 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__SRNG_ENABLE___POR 0x0 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__SECURITY_BIT___POR 0x0 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__LOOP_CNT___M 0x03C00000 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__LOOP_CNT___S 22 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__SPARE_CONTROL___S 14 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__SRNG_SM_STATE2___S 12 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__SRNG_SM_STATE1___S 8 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__SRNG_IS_IDLE___S 7 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__SRNG_ENABLE___S 6 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__MSI_SWAP_BIT___S 3 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__SECURITY_BIT___M 0x00000004 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__SECURITY_BIT___S 2 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__LOOPCNT_DISABLE___S 1 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define UMAC_TCL_R0_TCL2FW_RING_MISC__RING_ID_DISABLE___S 0 +#define UMAC_TCL_R0_TCL2FW_RING_MISC___M 0x03FFFFFF +#define UMAC_TCL_R0_TCL2FW_RING_MISC___S 0 + +#define UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_LSB (0x00A44964) +#define UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_LSB___POR 0x00000000 +#define UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_LSB___S 0 + +#define UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_MSB (0x00A44968) +#define UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_MSB___POR 0x00000000 +#define UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_MSB___M 0x000000FF +#define UMAC_TCL_R0_TCL2FW_RING_HP_ADDR_MSB___S 0 + +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP (0x00A44974) +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP___S 0 + +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS (0x00A44978) +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS___S 0 + +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER (0x00A4497C) +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define UMAC_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER___S 0 + +#define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB (0x00A44998) +#define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB___POR 0x00000000 +#define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB__ADDR___S 0 +#define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB___S 0 + +#define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB (0x00A4499C) +#define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB___POR 0x00000000 +#define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB__ADDR___S 0 +#define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB___M 0x000001FF +#define UMAC_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB___S 0 + +#define UMAC_TCL_R0_TCL2FW_RING_MSI1_DATA (0x00A449A0) +#define UMAC_TCL_R0_TCL2FW_RING_MSI1_DATA___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL2FW_RING_MSI1_DATA___POR 0x00000000 +#define UMAC_TCL_R0_TCL2FW_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define UMAC_TCL_R0_TCL2FW_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL2FW_RING_MSI1_DATA__VALUE___S 0 +#define UMAC_TCL_R0_TCL2FW_RING_MSI1_DATA___M 0xFFFFFFFF +#define UMAC_TCL_R0_TCL2FW_RING_MSI1_DATA___S 0 + +#define UMAC_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET (0x00A449A4) +#define UMAC_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define UMAC_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define UMAC_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define UMAC_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define UMAC_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define UMAC_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define UMAC_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET___S 0 + +#define UMAC_TCL_R0_GXI_TESTBUS_LOWER (0x00A449A8) +#define UMAC_TCL_R0_GXI_TESTBUS_LOWER___RWC QCSR_REG_RO +#define UMAC_TCL_R0_GXI_TESTBUS_LOWER___POR 0x00000000 +#define UMAC_TCL_R0_GXI_TESTBUS_LOWER__VALUE___POR 0x00000000 +#define UMAC_TCL_R0_GXI_TESTBUS_LOWER__VALUE___M 0xFFFFFFFF +#define UMAC_TCL_R0_GXI_TESTBUS_LOWER__VALUE___S 0 +#define UMAC_TCL_R0_GXI_TESTBUS_LOWER___M 0xFFFFFFFF +#define UMAC_TCL_R0_GXI_TESTBUS_LOWER___S 0 + +#define UMAC_TCL_R0_GXI_TESTBUS_UPPER (0x00A449AC) +#define UMAC_TCL_R0_GXI_TESTBUS_UPPER___RWC QCSR_REG_RO +#define UMAC_TCL_R0_GXI_TESTBUS_UPPER___POR 0x00000000 +#define UMAC_TCL_R0_GXI_TESTBUS_UPPER__VALUE___POR 0x00 +#define UMAC_TCL_R0_GXI_TESTBUS_UPPER__VALUE___M 0x000000FF +#define UMAC_TCL_R0_GXI_TESTBUS_UPPER__VALUE___S 0 +#define UMAC_TCL_R0_GXI_TESTBUS_UPPER___M 0x000000FF +#define UMAC_TCL_R0_GXI_TESTBUS_UPPER___S 0 + +#define UMAC_TCL_R0_GXI_SM_STATES_IX_0 (0x00A449B0) +#define UMAC_TCL_R0_GXI_SM_STATES_IX_0___RWC QCSR_REG_RO +#define UMAC_TCL_R0_GXI_SM_STATES_IX_0___POR 0x00000211 +#define UMAC_TCL_R0_GXI_SM_STATES_IX_0__SM_STATE_RD_ADDR___POR 0x1 +#define UMAC_TCL_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_ADDR___POR 0x01 +#define UMAC_TCL_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_DATA___POR 0x1 +#define UMAC_TCL_R0_GXI_SM_STATES_IX_0__SM_STATE_RD_ADDR___M 0x00000E00 +#define UMAC_TCL_R0_GXI_SM_STATES_IX_0__SM_STATE_RD_ADDR___S 9 +#define UMAC_TCL_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_ADDR___M 0x000001F0 +#define UMAC_TCL_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_ADDR___S 4 +#define UMAC_TCL_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_DATA___M 0x0000000F +#define UMAC_TCL_R0_GXI_SM_STATES_IX_0__SM_STATE_WR_DATA___S 0 +#define UMAC_TCL_R0_GXI_SM_STATES_IX_0___M 0x00000FFF +#define UMAC_TCL_R0_GXI_SM_STATES_IX_0___S 0 + +#define UMAC_TCL_R0_GXI_END_OF_TEST_CHECK (0x00A449B4) +#define UMAC_TCL_R0_GXI_END_OF_TEST_CHECK___RWC QCSR_REG_RW +#define UMAC_TCL_R0_GXI_END_OF_TEST_CHECK___POR 0x00000000 +#define UMAC_TCL_R0_GXI_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0 +#define UMAC_TCL_R0_GXI_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001 +#define UMAC_TCL_R0_GXI_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S 0 +#define UMAC_TCL_R0_GXI_END_OF_TEST_CHECK___M 0x00000001 +#define UMAC_TCL_R0_GXI_END_OF_TEST_CHECK___S 0 + +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE (0x00A449B8) +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE___RWC QCSR_REG_RW +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE___POR 0x00000000 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___POR 0x0 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__SPARE___POR 0x0 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WDOG_CTR___POR 0x0 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__RD_FIFO___POR 0x0 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_FIFO___POR 0x0 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_FIFO___POR 0x0 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__RD_AXI_MAS___POR 0x0 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_AXI_MAS___POR 0x0 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_AXI_MAS___POR 0x0 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_CMD___POR 0x0 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_CMD___POR 0x0 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__RD_CMD___POR 0x0 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__CORE___POR 0x0 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___M 0x80000000 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___S 31 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__SPARE___M 0x00000800 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__SPARE___S 11 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WDOG_CTR___M 0x00000400 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WDOG_CTR___S 10 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__RD_FIFO___M 0x00000200 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__RD_FIFO___S 9 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_FIFO___M 0x00000100 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_FIFO___S 8 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_FIFO___M 0x00000080 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_FIFO___S 7 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__RD_AXI_MAS___M 0x00000040 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__RD_AXI_MAS___S 6 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_AXI_MAS___M 0x00000020 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_AXI_MAS___S 5 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_AXI_MAS___M 0x00000010 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_AXI_MAS___S 4 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_CMD___M 0x00000008 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_DATA_CMD___S 3 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_CMD___M 0x00000004 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__WR_ADDR_CMD___S 2 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__RD_CMD___M 0x00000002 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__RD_CMD___S 1 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__CORE___M 0x00000001 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE__CORE___S 0 +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE___M 0x80000FFF +#define UMAC_TCL_R0_GXI_CLOCK_GATE_DISABLE___S 0 + +#define UMAC_TCL_R0_GXI_GXI_ERR_INTS (0x00A449BC) +#define UMAC_TCL_R0_GXI_GXI_ERR_INTS___RWC QCSR_REG_RO +#define UMAC_TCL_R0_GXI_GXI_ERR_INTS___POR 0x00000000 +#define UMAC_TCL_R0_GXI_GXI_ERR_INTS__GXI_WR_LAST_ERR_INT___POR 0x0 +#define UMAC_TCL_R0_GXI_GXI_ERR_INTS__GXI_AXI_WR_ERR_INT___POR 0x0 +#define UMAC_TCL_R0_GXI_GXI_ERR_INTS__GXI_AXI_RD_ERR_INT___POR 0x0 +#define UMAC_TCL_R0_GXI_GXI_ERR_INTS__GXI_WDTIMEOUT_INT___POR 0x0 +#define UMAC_TCL_R0_GXI_GXI_ERR_INTS__GXI_WR_LAST_ERR_INT___M 0x01000000 +#define UMAC_TCL_R0_GXI_GXI_ERR_INTS__GXI_WR_LAST_ERR_INT___S 24 +#define UMAC_TCL_R0_GXI_GXI_ERR_INTS__GXI_AXI_WR_ERR_INT___M 0x00010000 +#define UMAC_TCL_R0_GXI_GXI_ERR_INTS__GXI_AXI_WR_ERR_INT___S 16 +#define UMAC_TCL_R0_GXI_GXI_ERR_INTS__GXI_AXI_RD_ERR_INT___M 0x00000100 +#define UMAC_TCL_R0_GXI_GXI_ERR_INTS__GXI_AXI_RD_ERR_INT___S 8 +#define UMAC_TCL_R0_GXI_GXI_ERR_INTS__GXI_WDTIMEOUT_INT___M 0x00000001 +#define UMAC_TCL_R0_GXI_GXI_ERR_INTS__GXI_WDTIMEOUT_INT___S 0 +#define UMAC_TCL_R0_GXI_GXI_ERR_INTS___M 0x01010101 +#define UMAC_TCL_R0_GXI_GXI_ERR_INTS___S 0 + +#define UMAC_TCL_R0_GXI_GXI_ERR_STATS (0x00A449C0) +#define UMAC_TCL_R0_GXI_GXI_ERR_STATS___RWC QCSR_REG_RO +#define UMAC_TCL_R0_GXI_GXI_ERR_STATS___POR 0x00000000 +#define UMAC_TCL_R0_GXI_GXI_ERR_STATS__AXI_WR_LAST_ERR_PORT___POR 0x00 +#define UMAC_TCL_R0_GXI_GXI_ERR_STATS__AXI_WR_ERR_PORT___POR 0x00 +#define UMAC_TCL_R0_GXI_GXI_ERR_STATS__AXI_RD_ERR_PORT___POR 0x00 +#define UMAC_TCL_R0_GXI_GXI_ERR_STATS__AXI_WR_LAST_ERR_PORT___M 0x003F0000 +#define UMAC_TCL_R0_GXI_GXI_ERR_STATS__AXI_WR_LAST_ERR_PORT___S 16 +#define UMAC_TCL_R0_GXI_GXI_ERR_STATS__AXI_WR_ERR_PORT___M 0x00003F00 +#define UMAC_TCL_R0_GXI_GXI_ERR_STATS__AXI_WR_ERR_PORT___S 8 +#define UMAC_TCL_R0_GXI_GXI_ERR_STATS__AXI_RD_ERR_PORT___M 0x0000003F +#define UMAC_TCL_R0_GXI_GXI_ERR_STATS__AXI_RD_ERR_PORT___S 0 +#define UMAC_TCL_R0_GXI_GXI_ERR_STATS___M 0x003F3F3F +#define UMAC_TCL_R0_GXI_GXI_ERR_STATS___S 0 + +#define UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL (0x00A449C4) +#define UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL___RWC QCSR_REG_RW +#define UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL___POR 0x00000000 +#define UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READ_DATA___POR 0x00 +#define UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITE_DATA___POR 0x00 +#define UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READS___POR 0x00 +#define UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITES___POR 0x00 +#define UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READ_DATA___M 0xFF000000 +#define UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READ_DATA___S 24 +#define UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITE_DATA___M 0x00FF0000 +#define UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITE_DATA___S 16 +#define UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READS___M 0x00003F00 +#define UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READS___S 8 +#define UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITES___M 0x0000003F +#define UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITES___S 0 +#define UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL___M 0xFFFF3F3F +#define UMAC_TCL_R0_GXI_GXI_DEFAULT_CONTROL___S 0 + +#define UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL (0x00A449C8) +#define UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL___RWC QCSR_REG_RW +#define UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL___POR 0x00000000 +#define UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READ_DATA___POR 0x00 +#define UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITE_DATA___POR 0x00 +#define UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READS___POR 0x00 +#define UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITES___POR 0x00 +#define UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READ_DATA___M 0xFF000000 +#define UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READ_DATA___S 24 +#define UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITE_DATA___M 0x00FF0000 +#define UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITE_DATA___S 16 +#define UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READS___M 0x00003F00 +#define UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READS___S 8 +#define UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITES___M 0x0000003F +#define UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITES___S 0 +#define UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL___M 0xFFFF3F3F +#define UMAC_TCL_R0_GXI_GXI_REDUCED_CONTROL___S 0 + +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL (0x00A449CC) +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL___RWC QCSR_REG_RW +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL___POR 0x00240000 +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_RD_FLUSH___POR 0x0 +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_WR_FLUSH___POR 0x0 +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_DISABLE_WR_PREFIL___POR 0x0 +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_WR_BOUNDARY_SPLIT___POR 0x0 +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_RD_BOUNDARY_SPLIT___POR 0x0 +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_BURST_SIZE___POR 0x2 +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_READ_BURST_SIZE___POR 0x2 +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_READ_ISSUE_THRESHOLD___POR 0x00 +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_PREFETCH_THRESHOLD___POR 0x00 +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_CLEAR_STATS___POR 0x0 +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_RD_FLUSH___M 0x08000000 +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_RD_FLUSH___S 27 +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_WR_FLUSH___M 0x04000000 +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_DELAYED_WR_FLUSH___S 26 +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_DISABLE_WR_PREFIL___M 0x02000000 +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_DISABLE_WR_PREFIL___S 25 +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_WR_BOUNDARY_SPLIT___M 0x01000000 +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_WR_BOUNDARY_SPLIT___S 24 +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_RD_BOUNDARY_SPLIT___M 0x00800000 +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_MAX_RD_BOUNDARY_SPLIT___S 23 +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_BURST_SIZE___M 0x00700000 +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_BURST_SIZE___S 20 +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_READ_BURST_SIZE___M 0x000E0000 +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_READ_BURST_SIZE___S 17 +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_READ_ISSUE_THRESHOLD___M 0x0001FE00 +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_READ_ISSUE_THRESHOLD___S 9 +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_PREFETCH_THRESHOLD___M 0x000001FE +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_WRITE_PREFETCH_THRESHOLD___S 1 +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_CLEAR_STATS___M 0x00000001 +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL__GXI_CLEAR_STATS___S 0 +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL___M 0x0FFFFFFF +#define UMAC_TCL_R0_GXI_GXI_MISC_CONTROL___S 0 + +#define UMAC_TCL_R0_GXI_GXI_WDOG_CONTROL (0x00A449D0) +#define UMAC_TCL_R0_GXI_GXI_WDOG_CONTROL___RWC QCSR_REG_RW +#define UMAC_TCL_R0_GXI_GXI_WDOG_CONTROL___POR 0x00FF0000 +#define UMAC_TCL_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_LIMIT___POR 0x00FF +#define UMAC_TCL_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_DISABLE___POR 0x0 +#define UMAC_TCL_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_LIMIT___M 0xFFFF0000 +#define UMAC_TCL_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_LIMIT___S 16 +#define UMAC_TCL_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_DISABLE___M 0x00000001 +#define UMAC_TCL_R0_GXI_GXI_WDOG_CONTROL__GXI_WDOG_DISABLE___S 0 +#define UMAC_TCL_R0_GXI_GXI_WDOG_CONTROL___M 0xFFFF0001 +#define UMAC_TCL_R0_GXI_GXI_WDOG_CONTROL___S 0 + +#define UMAC_TCL_R0_GXI_GXI_WDOG_STATUS (0x00A449D4) +#define UMAC_TCL_R0_GXI_GXI_WDOG_STATUS___RWC QCSR_REG_RO +#define UMAC_TCL_R0_GXI_GXI_WDOG_STATUS___POR 0x00000000 +#define UMAC_TCL_R0_GXI_GXI_WDOG_STATUS__GXI_WDOG_STATUS___POR 0x0000 +#define UMAC_TCL_R0_GXI_GXI_WDOG_STATUS__GXI_WDOG_STATUS___M 0x0000FFFF +#define UMAC_TCL_R0_GXI_GXI_WDOG_STATUS__GXI_WDOG_STATUS___S 0 +#define UMAC_TCL_R0_GXI_GXI_WDOG_STATUS___M 0x0000FFFF +#define UMAC_TCL_R0_GXI_GXI_WDOG_STATUS___S 0 + +#define UMAC_TCL_R0_GXI_GXI_IDLE_COUNTERS (0x00A449D8) +#define UMAC_TCL_R0_GXI_GXI_IDLE_COUNTERS___RWC QCSR_REG_RO +#define UMAC_TCL_R0_GXI_GXI_IDLE_COUNTERS___POR 0x00000000 +#define UMAC_TCL_R0_GXI_GXI_IDLE_COUNTERS__GXI_READ_IDLE_CNT___POR 0x0000 +#define UMAC_TCL_R0_GXI_GXI_IDLE_COUNTERS__GXI_WRITE_IDLE_CNT___POR 0x0000 +#define UMAC_TCL_R0_GXI_GXI_IDLE_COUNTERS__GXI_READ_IDLE_CNT___M 0xFFFF0000 +#define UMAC_TCL_R0_GXI_GXI_IDLE_COUNTERS__GXI_READ_IDLE_CNT___S 16 +#define UMAC_TCL_R0_GXI_GXI_IDLE_COUNTERS__GXI_WRITE_IDLE_CNT___M 0x0000FFFF +#define UMAC_TCL_R0_GXI_GXI_IDLE_COUNTERS__GXI_WRITE_IDLE_CNT___S 0 +#define UMAC_TCL_R0_GXI_GXI_IDLE_COUNTERS___M 0xFFFFFFFF +#define UMAC_TCL_R0_GXI_GXI_IDLE_COUNTERS___S 0 + +#define UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL (0x00A449DC) +#define UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL___RWC QCSR_REG_RW +#define UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL___POR 0x00000000 +#define UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_RANGE___POR 0x0 +#define UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_EN___POR 0x0 +#define UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_MIN___POR 0x0000 +#define UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_RANGE___M 0x000E0000 +#define UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_RANGE___S 17 +#define UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_EN___M 0x00010000 +#define UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_EN___S 16 +#define UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_MIN___M 0x0000FFFF +#define UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_MIN___S 0 +#define UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL___M 0x000FFFFF +#define UMAC_TCL_R0_GXI_GXI_RD_LATENCY_CTRL___S 0 + +#define UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL (0x00A449E0) +#define UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL___RWC QCSR_REG_RW +#define UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL___POR 0x00000000 +#define UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_RANGE___POR 0x0 +#define UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_EN___POR 0x0 +#define UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_MIN___POR 0x0000 +#define UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_RANGE___M 0x000E0000 +#define UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_RANGE___S 17 +#define UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_EN___M 0x00010000 +#define UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_EN___S 16 +#define UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_MIN___M 0x0000FFFF +#define UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_MIN___S 0 +#define UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL___M 0x000FFFFF +#define UMAC_TCL_R0_GXI_GXI_WR_LATENCY_CTRL___S 0 + +#define UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0 (0x00A449E4) +#define UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___RWC QCSR_REG_RW +#define UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___POR 0x00000000 +#define UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0__VALUE___POR 0x00000000 +#define UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0__VALUE___M 0xFFFFFFFF +#define UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0__VALUE___S 0 +#define UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___M 0xFFFFFFFF +#define UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___S 0 + +#define UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1 (0x00A449E8) +#define UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___RWC QCSR_REG_RW +#define UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___POR 0x00000000 +#define UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1__VALUE___POR 0x00000000 +#define UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1__VALUE___M 0xFFFFFFFF +#define UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1__VALUE___S 0 +#define UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___M 0xFFFFFFFF +#define UMAC_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___S 0 + +#define UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0 (0x00A449EC) +#define UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___RWC QCSR_REG_RW +#define UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___POR 0x00000000 +#define UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0__VALUE___POR 0x00000000 +#define UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0__VALUE___M 0xFFFFFFFF +#define UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0__VALUE___S 0 +#define UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___M 0xFFFFFFFF +#define UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___S 0 + +#define UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1 (0x00A449F0) +#define UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___RWC QCSR_REG_RW +#define UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___POR 0x00000000 +#define UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1__VALUE___POR 0x00000000 +#define UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1__VALUE___M 0xFFFFFFFF +#define UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1__VALUE___S 0 +#define UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___M 0xFFFFFFFF +#define UMAC_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___S 0 + +#define UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL (0x00A449F4) +#define UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL___RWC QCSR_REG_RW +#define UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL___POR 0x00000000 +#define UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_EN___POR 0x0 +#define UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_CNT___POR 0x00 +#define UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_EN___POR 0x0 +#define UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_CNT___POR 0x00 +#define UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_EN___M 0x00008000 +#define UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_EN___S 15 +#define UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_CNT___M 0x00001F00 +#define UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_CNT___S 8 +#define UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_EN___M 0x00000080 +#define UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_EN___S 7 +#define UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_CNT___M 0x0000001F +#define UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_CNT___S 0 +#define UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL___M 0x00009F9F +#define UMAC_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL___S 0 + +#define UMAC_TCL_R0_ASE_GST_BASE_ADDR_LOW (0x00A449F8) +#define UMAC_TCL_R0_ASE_GST_BASE_ADDR_LOW___RWC QCSR_REG_RW +#define UMAC_TCL_R0_ASE_GST_BASE_ADDR_LOW___POR 0x00000000 +#define UMAC_TCL_R0_ASE_GST_BASE_ADDR_LOW__VAL___POR 0x00000000 +#define UMAC_TCL_R0_ASE_GST_BASE_ADDR_LOW__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R0_ASE_GST_BASE_ADDR_LOW__VAL___S 0 +#define UMAC_TCL_R0_ASE_GST_BASE_ADDR_LOW___M 0xFFFFFFFF +#define UMAC_TCL_R0_ASE_GST_BASE_ADDR_LOW___S 0 + +#define UMAC_TCL_R0_ASE_GST_BASE_ADDR_HIGH (0x00A449FC) +#define UMAC_TCL_R0_ASE_GST_BASE_ADDR_HIGH___RWC QCSR_REG_RW +#define UMAC_TCL_R0_ASE_GST_BASE_ADDR_HIGH___POR 0x00000000 +#define UMAC_TCL_R0_ASE_GST_BASE_ADDR_HIGH__VAL___POR 0x00 +#define UMAC_TCL_R0_ASE_GST_BASE_ADDR_HIGH__VAL___M 0x000000FF +#define UMAC_TCL_R0_ASE_GST_BASE_ADDR_HIGH__VAL___S 0 +#define UMAC_TCL_R0_ASE_GST_BASE_ADDR_HIGH___M 0x000000FF +#define UMAC_TCL_R0_ASE_GST_BASE_ADDR_HIGH___S 0 + +#define UMAC_TCL_R0_ASE_GST_SIZE (0x00A44A00) +#define UMAC_TCL_R0_ASE_GST_SIZE___RWC QCSR_REG_RW +#define UMAC_TCL_R0_ASE_GST_SIZE___POR 0x00000000 +#define UMAC_TCL_R0_ASE_GST_SIZE__VAL___POR 0x00000 +#define UMAC_TCL_R0_ASE_GST_SIZE__VAL___M 0x000FFFFF +#define UMAC_TCL_R0_ASE_GST_SIZE__VAL___S 0 +#define UMAC_TCL_R0_ASE_GST_SIZE___M 0x000FFFFF +#define UMAC_TCL_R0_ASE_GST_SIZE___S 0 + +#define UMAC_TCL_R0_ASE_SEARCH_CTRL (0x00A44A04) +#define UMAC_TCL_R0_ASE_SEARCH_CTRL___RWC QCSR_REG_RW +#define UMAC_TCL_R0_ASE_SEARCH_CTRL___POR 0x00003806 +#define UMAC_TCL_R0_ASE_SEARCH_CTRL__TIMEOUT_THRESH___POR 0x0000 +#define UMAC_TCL_R0_ASE_SEARCH_CTRL__CACHE_CMD_READ_BYPASS_EN___POR 0x1 +#define UMAC_TCL_R0_ASE_SEARCH_CTRL__CACHE_WRITE_BACK_FIX_EN___POR 0x1 +#define UMAC_TCL_R0_ASE_SEARCH_CTRL__CACHE_ONLY_ENTRY_CMD_FIX_EN___POR 0x1 +#define UMAC_TCL_R0_ASE_SEARCH_CTRL__CACHE_FAILURES_ENABLE___POR 0x0 +#define UMAC_TCL_R0_ASE_SEARCH_CTRL__CACHE_DISABLE___POR 0x0 +#define UMAC_TCL_R0_ASE_SEARCH_CTRL__SEARCH_SWAP___POR 0x0 +#define UMAC_TCL_R0_ASE_SEARCH_CTRL__MAX_SEARCH___POR 0x06 +#define UMAC_TCL_R0_ASE_SEARCH_CTRL__TIMEOUT_THRESH___M 0xFFFF0000 +#define UMAC_TCL_R0_ASE_SEARCH_CTRL__TIMEOUT_THRESH___S 16 +#define UMAC_TCL_R0_ASE_SEARCH_CTRL__CACHE_CMD_READ_BYPASS_EN___M 0x00002000 +#define UMAC_TCL_R0_ASE_SEARCH_CTRL__CACHE_CMD_READ_BYPASS_EN___S 13 +#define UMAC_TCL_R0_ASE_SEARCH_CTRL__CACHE_WRITE_BACK_FIX_EN___M 0x00001000 +#define UMAC_TCL_R0_ASE_SEARCH_CTRL__CACHE_WRITE_BACK_FIX_EN___S 12 +#define UMAC_TCL_R0_ASE_SEARCH_CTRL__CACHE_ONLY_ENTRY_CMD_FIX_EN___M 0x00000800 +#define UMAC_TCL_R0_ASE_SEARCH_CTRL__CACHE_ONLY_ENTRY_CMD_FIX_EN___S 11 +#define UMAC_TCL_R0_ASE_SEARCH_CTRL__CACHE_FAILURES_ENABLE___M 0x00000400 +#define UMAC_TCL_R0_ASE_SEARCH_CTRL__CACHE_FAILURES_ENABLE___S 10 +#define UMAC_TCL_R0_ASE_SEARCH_CTRL__CACHE_DISABLE___M 0x00000200 +#define UMAC_TCL_R0_ASE_SEARCH_CTRL__CACHE_DISABLE___S 9 +#define UMAC_TCL_R0_ASE_SEARCH_CTRL__SEARCH_SWAP___M 0x00000100 +#define UMAC_TCL_R0_ASE_SEARCH_CTRL__SEARCH_SWAP___S 8 +#define UMAC_TCL_R0_ASE_SEARCH_CTRL__MAX_SEARCH___M 0x000000FF +#define UMAC_TCL_R0_ASE_SEARCH_CTRL__MAX_SEARCH___S 0 +#define UMAC_TCL_R0_ASE_SEARCH_CTRL___M 0xFFFF3FFF +#define UMAC_TCL_R0_ASE_SEARCH_CTRL___S 0 + +#define UMAC_TCL_R0_ASE_WATCHDOG (0x00A44A08) +#define UMAC_TCL_R0_ASE_WATCHDOG___RWC QCSR_REG_RW +#define UMAC_TCL_R0_ASE_WATCHDOG___POR 0x0000FFFF +#define UMAC_TCL_R0_ASE_WATCHDOG__STATUS___POR 0x0000 +#define UMAC_TCL_R0_ASE_WATCHDOG__LIMIT___POR 0xFFFF +#define UMAC_TCL_R0_ASE_WATCHDOG__STATUS___M 0xFFFF0000 +#define UMAC_TCL_R0_ASE_WATCHDOG__STATUS___S 16 +#define UMAC_TCL_R0_ASE_WATCHDOG__LIMIT___M 0x0000FFFF +#define UMAC_TCL_R0_ASE_WATCHDOG__LIMIT___S 0 +#define UMAC_TCL_R0_ASE_WATCHDOG___M 0xFFFFFFFF +#define UMAC_TCL_R0_ASE_WATCHDOG___S 0 + +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE (0x00A44A0C) +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE___RWC QCSR_REG_RW +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE___POR 0x00000000 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__CLK_EXTEND___POR 0x0 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__CPU_IF_EXTEND___POR 0x0 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__GSE_RSRVD___POR 0x000000 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__GSE_TOP___POR 0x0 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__CACHE___POR 0x0 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__SLOTS_ARRAY_HASH___POR 0x0 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__APP_RETURN___POR 0x0 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__MEM_RESP2___POR 0x0 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__MEM_RESP1___POR 0x0 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__MEM_ISS2___POR 0x0 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__MEM_ISS1___POR 0x0 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__GSE_CTL___POR 0x0 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__CLK_EXTEND___M 0x80000000 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__CLK_EXTEND___S 31 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__CPU_IF_EXTEND___M 0x40000000 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__CPU_IF_EXTEND___S 30 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__GSE_RSRVD___M 0x3FFFFE00 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__GSE_RSRVD___S 9 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__GSE_TOP___M 0x00000100 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__GSE_TOP___S 8 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__CACHE___M 0x00000080 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__CACHE___S 7 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__SLOTS_ARRAY_HASH___M 0x00000040 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__SLOTS_ARRAY_HASH___S 6 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__APP_RETURN___M 0x00000020 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__APP_RETURN___S 5 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__MEM_RESP2___M 0x00000010 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__MEM_RESP2___S 4 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__MEM_RESP1___M 0x00000008 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__MEM_RESP1___S 3 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__MEM_ISS2___M 0x00000004 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__MEM_ISS2___S 2 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__MEM_ISS1___M 0x00000002 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__MEM_ISS1___S 1 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__GSE_CTL___M 0x00000001 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE__GSE_CTL___S 0 +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE___M 0xFFFFFFFF +#define UMAC_TCL_R0_ASE_CLKGATE_DISABLE___S 0 + +#define UMAC_TCL_R0_ASE_WRITE_BACK_PENDING (0x00A44A10) +#define UMAC_TCL_R0_ASE_WRITE_BACK_PENDING___RWC QCSR_REG_RO +#define UMAC_TCL_R0_ASE_WRITE_BACK_PENDING___POR 0x00000000 +#define UMAC_TCL_R0_ASE_WRITE_BACK_PENDING__STATUS___POR 0x0 +#define UMAC_TCL_R0_ASE_WRITE_BACK_PENDING__STATUS___M 0x00000001 +#define UMAC_TCL_R0_ASE_WRITE_BACK_PENDING__STATUS___S 0 +#define UMAC_TCL_R0_ASE_WRITE_BACK_PENDING___M 0x00000001 +#define UMAC_TCL_R0_ASE_WRITE_BACK_PENDING___S 0 + +#define UMAC_TCL_R1_CACHE_FLUSH (0x00A45000) +#define UMAC_TCL_R1_CACHE_FLUSH___RWC QCSR_REG_RW +#define UMAC_TCL_R1_CACHE_FLUSH___POR 0x00000000 +#define UMAC_TCL_R1_CACHE_FLUSH__STATUS___POR 0x0 +#define UMAC_TCL_R1_CACHE_FLUSH__ENABLE___POR 0x0 +#define UMAC_TCL_R1_CACHE_FLUSH__STATUS___M 0x00000002 +#define UMAC_TCL_R1_CACHE_FLUSH__STATUS___S 1 +#define UMAC_TCL_R1_CACHE_FLUSH__ENABLE___M 0x00000001 +#define UMAC_TCL_R1_CACHE_FLUSH__ENABLE___S 0 +#define UMAC_TCL_R1_CACHE_FLUSH___M 0x00000003 +#define UMAC_TCL_R1_CACHE_FLUSH___S 0 + +#define UMAC_TCL_R1_SM_STATES_IX_0 (0x00A45004) +#define UMAC_TCL_R1_SM_STATES_IX_0___RWC QCSR_REG_RO +#define UMAC_TCL_R1_SM_STATES_IX_0___POR 0x00000000 +#define UMAC_TCL_R1_SM_STATES_IX_0__GSE_CTRL___POR 0x0 +#define UMAC_TCL_R1_SM_STATES_IX_0__TLV_GEN___POR 0x0 +#define UMAC_TCL_R1_SM_STATES_IX_0__EXTN_DESC_FETCH___POR 0x0 +#define UMAC_TCL_R1_SM_STATES_IX_0__MSDU_FETCH___POR 0x0 +#define UMAC_TCL_R1_SM_STATES_IX_0__SW2TCL_CREDIT_RING___POR 0x0 +#define UMAC_TCL_R1_SM_STATES_IX_0__FW2TCL1_RING___POR 0x0 +#define UMAC_TCL_R1_SM_STATES_IX_0__SW2TCL3_RING___POR 0x0 +#define UMAC_TCL_R1_SM_STATES_IX_0__SW2TCL2_RING___POR 0x0 +#define UMAC_TCL_R1_SM_STATES_IX_0__SW2TCL1_RING___POR 0x0 +#define UMAC_TCL_R1_SM_STATES_IX_0__GSE_CTRL___M 0x07000000 +#define UMAC_TCL_R1_SM_STATES_IX_0__GSE_CTRL___S 24 +#define UMAC_TCL_R1_SM_STATES_IX_0__TLV_GEN___M 0x00E00000 +#define UMAC_TCL_R1_SM_STATES_IX_0__TLV_GEN___S 21 +#define UMAC_TCL_R1_SM_STATES_IX_0__EXTN_DESC_FETCH___M 0x001C0000 +#define UMAC_TCL_R1_SM_STATES_IX_0__EXTN_DESC_FETCH___S 18 +#define UMAC_TCL_R1_SM_STATES_IX_0__MSDU_FETCH___M 0x00038000 +#define UMAC_TCL_R1_SM_STATES_IX_0__MSDU_FETCH___S 15 +#define UMAC_TCL_R1_SM_STATES_IX_0__SW2TCL_CREDIT_RING___M 0x00007000 +#define UMAC_TCL_R1_SM_STATES_IX_0__SW2TCL_CREDIT_RING___S 12 +#define UMAC_TCL_R1_SM_STATES_IX_0__FW2TCL1_RING___M 0x00000E00 +#define UMAC_TCL_R1_SM_STATES_IX_0__FW2TCL1_RING___S 9 +#define UMAC_TCL_R1_SM_STATES_IX_0__SW2TCL3_RING___M 0x000001C0 +#define UMAC_TCL_R1_SM_STATES_IX_0__SW2TCL3_RING___S 6 +#define UMAC_TCL_R1_SM_STATES_IX_0__SW2TCL2_RING___M 0x00000038 +#define UMAC_TCL_R1_SM_STATES_IX_0__SW2TCL2_RING___S 3 +#define UMAC_TCL_R1_SM_STATES_IX_0__SW2TCL1_RING___M 0x00000007 +#define UMAC_TCL_R1_SM_STATES_IX_0__SW2TCL1_RING___S 0 +#define UMAC_TCL_R1_SM_STATES_IX_0___M 0x07FFFFFF +#define UMAC_TCL_R1_SM_STATES_IX_0___S 0 + +#define UMAC_TCL_R1_SM_STATES_IX_1 (0x00A45008) +#define UMAC_TCL_R1_SM_STATES_IX_1___RWC QCSR_REG_RO +#define UMAC_TCL_R1_SM_STATES_IX_1___POR 0x00000000 +#define UMAC_TCL_R1_SM_STATES_IX_1__DSCP_TABLE_ACC___POR 0x0 +#define UMAC_TCL_R1_SM_STATES_IX_1__PROD_CTRL___POR 0x0 +#define UMAC_TCL_R1_SM_STATES_IX_1__TCL_STATUS2___POR 0x0 +#define UMAC_TCL_R1_SM_STATES_IX_1__TCL_STATUS1___POR 0x0 +#define UMAC_TCL_R1_SM_STATES_IX_1__TCL2FW___POR 0x0 +#define UMAC_TCL_R1_SM_STATES_IX_1__TCL2TQM___POR 0x0 +#define UMAC_TCL_R1_SM_STATES_IX_1__DSCP_TABLE_ACC___M 0x00038000 +#define UMAC_TCL_R1_SM_STATES_IX_1__DSCP_TABLE_ACC___S 15 +#define UMAC_TCL_R1_SM_STATES_IX_1__PROD_CTRL___M 0x00007000 +#define UMAC_TCL_R1_SM_STATES_IX_1__PROD_CTRL___S 12 +#define UMAC_TCL_R1_SM_STATES_IX_1__TCL_STATUS2___M 0x00000E00 +#define UMAC_TCL_R1_SM_STATES_IX_1__TCL_STATUS2___S 9 +#define UMAC_TCL_R1_SM_STATES_IX_1__TCL_STATUS1___M 0x000001C0 +#define UMAC_TCL_R1_SM_STATES_IX_1__TCL_STATUS1___S 6 +#define UMAC_TCL_R1_SM_STATES_IX_1__TCL2FW___M 0x00000038 +#define UMAC_TCL_R1_SM_STATES_IX_1__TCL2FW___S 3 +#define UMAC_TCL_R1_SM_STATES_IX_1__TCL2TQM___M 0x00000007 +#define UMAC_TCL_R1_SM_STATES_IX_1__TCL2TQM___S 0 +#define UMAC_TCL_R1_SM_STATES_IX_1___M 0x0003FFFF +#define UMAC_TCL_R1_SM_STATES_IX_1___S 0 + +#define UMAC_TCL_R1_TESTBUS_CTRL_0 (0x00A4500C) +#define UMAC_TCL_R1_TESTBUS_CTRL_0___RWC QCSR_REG_RW +#define UMAC_TCL_R1_TESTBUS_CTRL_0___POR 0x00000000 +#define UMAC_TCL_R1_TESTBUS_CTRL_0__HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE___POR 0x0 +#define UMAC_TCL_R1_TESTBUS_CTRL_0__TCL_MAIN_SELECT___POR 0x00 +#define UMAC_TCL_R1_TESTBUS_CTRL_0__GXI_SELECT___POR 0x00 +#define UMAC_TCL_R1_TESTBUS_CTRL_0__FSE_SELECT___POR 0x0 +#define UMAC_TCL_R1_TESTBUS_CTRL_0__ASE_SELECT___POR 0x0 +#define UMAC_TCL_R1_TESTBUS_CTRL_0__PARSER_SELECT___POR 0x00 +#define UMAC_TCL_R1_TESTBUS_CTRL_0__CCE_SELECT___POR 0x00 +#define UMAC_TCL_R1_TESTBUS_CTRL_0__HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE___M 0x20000000 +#define UMAC_TCL_R1_TESTBUS_CTRL_0__HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE___S 29 +#define UMAC_TCL_R1_TESTBUS_CTRL_0__TCL_MAIN_SELECT___M 0x1F800000 +#define UMAC_TCL_R1_TESTBUS_CTRL_0__TCL_MAIN_SELECT___S 23 +#define UMAC_TCL_R1_TESTBUS_CTRL_0__GXI_SELECT___M 0x007C0000 +#define UMAC_TCL_R1_TESTBUS_CTRL_0__GXI_SELECT___S 18 +#define UMAC_TCL_R1_TESTBUS_CTRL_0__FSE_SELECT___M 0x0003C000 +#define UMAC_TCL_R1_TESTBUS_CTRL_0__FSE_SELECT___S 14 +#define UMAC_TCL_R1_TESTBUS_CTRL_0__ASE_SELECT___M 0x00003C00 +#define UMAC_TCL_R1_TESTBUS_CTRL_0__ASE_SELECT___S 10 +#define UMAC_TCL_R1_TESTBUS_CTRL_0__PARSER_SELECT___M 0x000003E0 +#define UMAC_TCL_R1_TESTBUS_CTRL_0__PARSER_SELECT___S 5 +#define UMAC_TCL_R1_TESTBUS_CTRL_0__CCE_SELECT___M 0x0000001F +#define UMAC_TCL_R1_TESTBUS_CTRL_0__CCE_SELECT___S 0 +#define UMAC_TCL_R1_TESTBUS_CTRL_0___M 0x3FFFFFFF +#define UMAC_TCL_R1_TESTBUS_CTRL_0___S 0 + +#define UMAC_TCL_R1_TESTBUS_LOW (0x00A45010) +#define UMAC_TCL_R1_TESTBUS_LOW___RWC QCSR_REG_RO +#define UMAC_TCL_R1_TESTBUS_LOW___POR 0x00000000 +#define UMAC_TCL_R1_TESTBUS_LOW__VAL___POR 0x00000000 +#define UMAC_TCL_R1_TESTBUS_LOW__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_TESTBUS_LOW__VAL___S 0 +#define UMAC_TCL_R1_TESTBUS_LOW___M 0xFFFFFFFF +#define UMAC_TCL_R1_TESTBUS_LOW___S 0 + +#define UMAC_TCL_R1_TESTBUS_HIGH (0x00A45014) +#define UMAC_TCL_R1_TESTBUS_HIGH___RWC QCSR_REG_RO +#define UMAC_TCL_R1_TESTBUS_HIGH___POR 0x00000000 +#define UMAC_TCL_R1_TESTBUS_HIGH__VAL___POR 0x00 +#define UMAC_TCL_R1_TESTBUS_HIGH__VAL___M 0x000000FF +#define UMAC_TCL_R1_TESTBUS_HIGH__VAL___S 0 +#define UMAC_TCL_R1_TESTBUS_HIGH___M 0x000000FF +#define UMAC_TCL_R1_TESTBUS_HIGH___S 0 + +#define UMAC_TCL_R1_EVENTMASK_IX_0 (0x00A45018) +#define UMAC_TCL_R1_EVENTMASK_IX_0___RWC QCSR_REG_RW +#define UMAC_TCL_R1_EVENTMASK_IX_0___POR 0x0000FFFF +#define UMAC_TCL_R1_EVENTMASK_IX_0__VAL___POR 0x0000FFFF +#define UMAC_TCL_R1_EVENTMASK_IX_0__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_EVENTMASK_IX_0__VAL___S 0 +#define UMAC_TCL_R1_EVENTMASK_IX_0___M 0xFFFFFFFF +#define UMAC_TCL_R1_EVENTMASK_IX_0___S 0 + +#define UMAC_TCL_R1_EVENTMASK_IX_1 (0x00A4501C) +#define UMAC_TCL_R1_EVENTMASK_IX_1___RWC QCSR_REG_RW +#define UMAC_TCL_R1_EVENTMASK_IX_1___POR 0x0000FFFF +#define UMAC_TCL_R1_EVENTMASK_IX_1__VAL___POR 0x0000FFFF +#define UMAC_TCL_R1_EVENTMASK_IX_1__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_EVENTMASK_IX_1__VAL___S 0 +#define UMAC_TCL_R1_EVENTMASK_IX_1___M 0xFFFFFFFF +#define UMAC_TCL_R1_EVENTMASK_IX_1___S 0 + +#define UMAC_TCL_R1_EVENTMASK_IX_2 (0x00A45020) +#define UMAC_TCL_R1_EVENTMASK_IX_2___RWC QCSR_REG_RW +#define UMAC_TCL_R1_EVENTMASK_IX_2___POR 0x0000FFFF +#define UMAC_TCL_R1_EVENTMASK_IX_2__VAL___POR 0x0000FFFF +#define UMAC_TCL_R1_EVENTMASK_IX_2__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_EVENTMASK_IX_2__VAL___S 0 +#define UMAC_TCL_R1_EVENTMASK_IX_2___M 0xFFFFFFFF +#define UMAC_TCL_R1_EVENTMASK_IX_2___S 0 + +#define UMAC_TCL_R1_EVENTMASK_IX_3 (0x00A45024) +#define UMAC_TCL_R1_EVENTMASK_IX_3___RWC QCSR_REG_RW +#define UMAC_TCL_R1_EVENTMASK_IX_3___POR 0x0000FFFF +#define UMAC_TCL_R1_EVENTMASK_IX_3__VAL___POR 0x0000FFFF +#define UMAC_TCL_R1_EVENTMASK_IX_3__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_EVENTMASK_IX_3__VAL___S 0 +#define UMAC_TCL_R1_EVENTMASK_IX_3___M 0xFFFFFFFF +#define UMAC_TCL_R1_EVENTMASK_IX_3___S 0 + +#define UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL (0x00A45028) +#define UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL___RWC QCSR_REG_RW +#define UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL___POR 0x7FFE0002 +#define UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___POR 0x3FFF +#define UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___POR 0x0000 +#define UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___POR 0x1 +#define UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___POR 0x0 +#define UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___M 0xFFFE0000 +#define UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___S 17 +#define UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___M 0x0001FFFC +#define UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___S 2 +#define UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___M 0x00000002 +#define UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___S 1 +#define UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___M 0x00000001 +#define UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___S 0 +#define UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL___M 0xFFFFFFFF +#define UMAC_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL___S 0 + +#define UMAC_TCL_R1_SPARE_REGISTER (0x00A4502C) +#define UMAC_TCL_R1_SPARE_REGISTER___RWC QCSR_REG_RW +#define UMAC_TCL_R1_SPARE_REGISTER___POR 0x00000000 +#define UMAC_TCL_R1_SPARE_REGISTER__TCL_SPARE_FIELD_32___POR 0x00000000 +#define UMAC_TCL_R1_SPARE_REGISTER__TCL_SPARE_FIELD_32___M 0xFFFFFFFF +#define UMAC_TCL_R1_SPARE_REGISTER__TCL_SPARE_FIELD_32___S 0 +#define UMAC_TCL_R1_SPARE_REGISTER___M 0xFFFFFFFF +#define UMAC_TCL_R1_SPARE_REGISTER___S 0 + +#define UMAC_TCL_R1_END_OF_TEST_CHECK (0x00A45030) +#define UMAC_TCL_R1_END_OF_TEST_CHECK___RWC QCSR_REG_RW +#define UMAC_TCL_R1_END_OF_TEST_CHECK___POR 0x00000000 +#define UMAC_TCL_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0 +#define UMAC_TCL_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001 +#define UMAC_TCL_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S 0 +#define UMAC_TCL_R1_END_OF_TEST_CHECK___M 0x00000001 +#define UMAC_TCL_R1_END_OF_TEST_CHECK___S 0 + +#define UMAC_TCL_R1_ASE_END_OF_TEST_CHECK (0x00A45034) +#define UMAC_TCL_R1_ASE_END_OF_TEST_CHECK___RWC QCSR_REG_RW +#define UMAC_TCL_R1_ASE_END_OF_TEST_CHECK___POR 0x00000000 +#define UMAC_TCL_R1_ASE_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0 +#define UMAC_TCL_R1_ASE_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001 +#define UMAC_TCL_R1_ASE_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S 0 +#define UMAC_TCL_R1_ASE_END_OF_TEST_CHECK___M 0x00000001 +#define UMAC_TCL_R1_ASE_END_OF_TEST_CHECK___S 0 + +#define UMAC_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS (0x00A45038) +#define UMAC_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS___RWC QCSR_REG_RW +#define UMAC_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS___POR 0x00000000 +#define UMAC_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS__EN___POR 0x0 +#define UMAC_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS__EN___M 0x00000001 +#define UMAC_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS__EN___S 0 +#define UMAC_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS___M 0x00000001 +#define UMAC_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS___S 0 + +#define UMAC_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER (0x00A4503C) +#define UMAC_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER___POR 0x00000000 +#define UMAC_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER__VAL___POR 0x00000000 +#define UMAC_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER__VAL___S 0 +#define UMAC_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER___S 0 + +#define UMAC_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER (0x00A45040) +#define UMAC_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER___POR 0x00000000 +#define UMAC_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER__VAL___POR 0x00000000 +#define UMAC_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER__VAL___S 0 +#define UMAC_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER___S 0 + +#define UMAC_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER (0x00A45044) +#define UMAC_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER___POR 0x00000000 +#define UMAC_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER__PEAK___POR 0x000 +#define UMAC_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER__CURR___POR 0x000 +#define UMAC_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER__PEAK___M 0x000FFC00 +#define UMAC_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER__PEAK___S 10 +#define UMAC_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER__CURR___M 0x000003FF +#define UMAC_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER__CURR___S 0 +#define UMAC_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER___M 0x000FFFFF +#define UMAC_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER___S 0 + +#define UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER (0x00A45048) +#define UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER___POR 0x00000000 +#define UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__SQUARE_OCCUPANCY___POR 0x0000 +#define UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__PEAK_NUM_SEARCH_PENDING___POR 0x00 +#define UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__NUM_SEARCH_PENDING___POR 0x00 +#define UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__SQUARE_OCCUPANCY___M 0x03FFFC00 +#define UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__SQUARE_OCCUPANCY___S 10 +#define UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__PEAK_NUM_SEARCH_PENDING___M 0x000003E0 +#define UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__PEAK_NUM_SEARCH_PENDING___S 5 +#define UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__NUM_SEARCH_PENDING___M 0x0000001F +#define UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__NUM_SEARCH_PENDING___S 0 +#define UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER___M 0x03FFFFFF +#define UMAC_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER___S 0 + +#define UMAC_TCL_R1_ASE_SM_STATES (0x00A4504C) +#define UMAC_TCL_R1_ASE_SM_STATES___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_SM_STATES___POR 0x00000000 +#define UMAC_TCL_R1_ASE_SM_STATES__GSE_CTRL_STATE___POR 0x0 +#define UMAC_TCL_R1_ASE_SM_STATES__CACHE_CHK_STATE___POR 0x0 +#define UMAC_TCL_R1_ASE_SM_STATES__MEM_ISS1_STATE___POR 0x0 +#define UMAC_TCL_R1_ASE_SM_STATES__MEM_ISS2_STATE___POR 0x0 +#define UMAC_TCL_R1_ASE_SM_STATES__MEM_RESP1_STATE___POR 0x0 +#define UMAC_TCL_R1_ASE_SM_STATES__MEM_RESP2_STATE___POR 0x0 +#define UMAC_TCL_R1_ASE_SM_STATES__APP_RETURN_STATE___POR 0x0 +#define UMAC_TCL_R1_ASE_SM_STATES__GSE_CTRL_STATE___M 0x00300000 +#define UMAC_TCL_R1_ASE_SM_STATES__GSE_CTRL_STATE___S 20 +#define UMAC_TCL_R1_ASE_SM_STATES__CACHE_CHK_STATE___M 0x000C0000 +#define UMAC_TCL_R1_ASE_SM_STATES__CACHE_CHK_STATE___S 18 +#define UMAC_TCL_R1_ASE_SM_STATES__MEM_ISS1_STATE___M 0x00030000 +#define UMAC_TCL_R1_ASE_SM_STATES__MEM_ISS1_STATE___S 16 +#define UMAC_TCL_R1_ASE_SM_STATES__MEM_ISS2_STATE___M 0x0000C000 +#define UMAC_TCL_R1_ASE_SM_STATES__MEM_ISS2_STATE___S 14 +#define UMAC_TCL_R1_ASE_SM_STATES__MEM_RESP1_STATE___M 0x00003800 +#define UMAC_TCL_R1_ASE_SM_STATES__MEM_RESP1_STATE___S 11 +#define UMAC_TCL_R1_ASE_SM_STATES__MEM_RESP2_STATE___M 0x00000700 +#define UMAC_TCL_R1_ASE_SM_STATES__MEM_RESP2_STATE___S 8 +#define UMAC_TCL_R1_ASE_SM_STATES__APP_RETURN_STATE___M 0x0000000F +#define UMAC_TCL_R1_ASE_SM_STATES__APP_RETURN_STATE___S 0 +#define UMAC_TCL_R1_ASE_SM_STATES___M 0x003FFF0F +#define UMAC_TCL_R1_ASE_SM_STATES___S 0 + +#define UMAC_TCL_R1_ASE_CACHE_DEBUG (0x00A45050) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG___RWC QCSR_REG_RW +#define UMAC_TCL_R1_ASE_CACHE_DEBUG___POR 0x00000000 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG__READ_IDX___POR 0x000 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG__READ_IDX___M 0x000003FF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG__READ_IDX___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG___M 0x000003FF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG___S 0 + +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS (0x00A45054) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS___POR 0x00000000 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS__GST_IDX___POR 0x00000 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS__CACHE_ONLY___POR 0x0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS__DIRTY___POR 0x0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS__VALID___POR 0x0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS__GST_IDX___M 0x007FFFF8 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS__GST_IDX___S 3 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS__CACHE_ONLY___M 0x00000004 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS__CACHE_ONLY___S 2 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS__DIRTY___M 0x00000002 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS__DIRTY___S 1 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS__VALID___M 0x00000001 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS__VALID___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS___M 0x007FFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS___S 0 + +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n(n) (0x00A45058+0x4*(n)) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_nMIN 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_nMAX 31 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ELEM 32 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n___POR 0x00000000 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n__VAL___POR 0x00000000 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n__VAL___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_0 (0x00A45058) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_0___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_0__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_0__VAL___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_1 (0x00A4505C) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_1___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_1__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_1__VAL___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_2 (0x00A45060) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_2___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_2__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_2__VAL___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_3 (0x00A45064) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_3___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_3__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_3__VAL___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_4 (0x00A45068) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_4___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_4__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_4__VAL___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_5 (0x00A4506C) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_5___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_5__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_5__VAL___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_6 (0x00A45070) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_6___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_6__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_6__VAL___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_7 (0x00A45074) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_7___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_7__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_7__VAL___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_8 (0x00A45078) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_8___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_8__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_8__VAL___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_9 (0x00A4507C) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_9___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_9__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_9__VAL___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_10 (0x00A45080) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_10___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_10__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_10__VAL___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_11 (0x00A45084) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_11___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_11__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_11__VAL___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_12 (0x00A45088) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_12___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_12__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_12__VAL___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_13 (0x00A4508C) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_13___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_13__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_13__VAL___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_14 (0x00A45090) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_14___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_14__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_14__VAL___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_15 (0x00A45094) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_15___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_15__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_15__VAL___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_16 (0x00A45098) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_16___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_16__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_16__VAL___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_17 (0x00A4509C) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_17___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_17__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_17__VAL___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_18 (0x00A450A0) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_18___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_18__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_18__VAL___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_19 (0x00A450A4) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_19___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_19__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_19__VAL___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_20 (0x00A450A8) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_20___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_20__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_20__VAL___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_21 (0x00A450AC) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_21___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_21__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_21__VAL___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_22 (0x00A450B0) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_22___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_22__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_22__VAL___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_23 (0x00A450B4) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_23___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_23__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_23__VAL___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_24 (0x00A450B8) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_24___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_24__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_24__VAL___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_25 (0x00A450BC) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_25___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_25__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_25__VAL___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_26 (0x00A450C0) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_26___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_26__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_26__VAL___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_27 (0x00A450C4) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_27___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_27__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_27__VAL___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_28 (0x00A450C8) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_28___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_28__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_28__VAL___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_29 (0x00A450CC) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_29___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_29__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_29__VAL___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_30 (0x00A450D0) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_30___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_30__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_30__VAL___S 0 +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_31 (0x00A450D4) +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_31___RWC QCSR_REG_RO +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_31__VAL___M 0xFFFFFFFF +#define UMAC_TCL_R1_ASE_CACHE_DEBUG_ENTRY_31__VAL___S 0 + +#define UMAC_TCL_R2_SW2TCL1_RING_HP (0x00A46000) +#define UMAC_TCL_R2_SW2TCL1_RING_HP___RWC QCSR_REG_RW +#define UMAC_TCL_R2_SW2TCL1_RING_HP___POR 0x00000000 +#define UMAC_TCL_R2_SW2TCL1_RING_HP__HEAD_PTR___POR 0x00000 +#define UMAC_TCL_R2_SW2TCL1_RING_HP__HEAD_PTR___M 0x000FFFFF +#define UMAC_TCL_R2_SW2TCL1_RING_HP__HEAD_PTR___S 0 +#define UMAC_TCL_R2_SW2TCL1_RING_HP___M 0x000FFFFF +#define UMAC_TCL_R2_SW2TCL1_RING_HP___S 0 + +#define UMAC_TCL_R2_SW2TCL1_RING_TP (0x00A46004) +#define UMAC_TCL_R2_SW2TCL1_RING_TP___RWC QCSR_REG_RW +#define UMAC_TCL_R2_SW2TCL1_RING_TP___POR 0x00000000 +#define UMAC_TCL_R2_SW2TCL1_RING_TP__TAIL_PTR___POR 0x00000 +#define UMAC_TCL_R2_SW2TCL1_RING_TP__TAIL_PTR___M 0x000FFFFF +#define UMAC_TCL_R2_SW2TCL1_RING_TP__TAIL_PTR___S 0 +#define UMAC_TCL_R2_SW2TCL1_RING_TP___M 0x000FFFFF +#define UMAC_TCL_R2_SW2TCL1_RING_TP___S 0 + +#define UMAC_TCL_R2_SW2TCL2_RING_HP (0x00A46008) +#define UMAC_TCL_R2_SW2TCL2_RING_HP___RWC QCSR_REG_RW +#define UMAC_TCL_R2_SW2TCL2_RING_HP___POR 0x00000000 +#define UMAC_TCL_R2_SW2TCL2_RING_HP__HEAD_PTR___POR 0x00000 +#define UMAC_TCL_R2_SW2TCL2_RING_HP__HEAD_PTR___M 0x000FFFFF +#define UMAC_TCL_R2_SW2TCL2_RING_HP__HEAD_PTR___S 0 +#define UMAC_TCL_R2_SW2TCL2_RING_HP___M 0x000FFFFF +#define UMAC_TCL_R2_SW2TCL2_RING_HP___S 0 + +#define UMAC_TCL_R2_SW2TCL2_RING_TP (0x00A4600C) +#define UMAC_TCL_R2_SW2TCL2_RING_TP___RWC QCSR_REG_RW +#define UMAC_TCL_R2_SW2TCL2_RING_TP___POR 0x00000000 +#define UMAC_TCL_R2_SW2TCL2_RING_TP__TAIL_PTR___POR 0x00000 +#define UMAC_TCL_R2_SW2TCL2_RING_TP__TAIL_PTR___M 0x000FFFFF +#define UMAC_TCL_R2_SW2TCL2_RING_TP__TAIL_PTR___S 0 +#define UMAC_TCL_R2_SW2TCL2_RING_TP___M 0x000FFFFF +#define UMAC_TCL_R2_SW2TCL2_RING_TP___S 0 + +#define UMAC_TCL_R2_SW2TCL3_RING_HP (0x00A46010) +#define UMAC_TCL_R2_SW2TCL3_RING_HP___RWC QCSR_REG_RW +#define UMAC_TCL_R2_SW2TCL3_RING_HP___POR 0x00000000 +#define UMAC_TCL_R2_SW2TCL3_RING_HP__HEAD_PTR___POR 0x00000 +#define UMAC_TCL_R2_SW2TCL3_RING_HP__HEAD_PTR___M 0x000FFFFF +#define UMAC_TCL_R2_SW2TCL3_RING_HP__HEAD_PTR___S 0 +#define UMAC_TCL_R2_SW2TCL3_RING_HP___M 0x000FFFFF +#define UMAC_TCL_R2_SW2TCL3_RING_HP___S 0 + +#define UMAC_TCL_R2_SW2TCL3_RING_TP (0x00A46014) +#define UMAC_TCL_R2_SW2TCL3_RING_TP___RWC QCSR_REG_RW +#define UMAC_TCL_R2_SW2TCL3_RING_TP___POR 0x00000000 +#define UMAC_TCL_R2_SW2TCL3_RING_TP__TAIL_PTR___POR 0x00000 +#define UMAC_TCL_R2_SW2TCL3_RING_TP__TAIL_PTR___M 0x000FFFFF +#define UMAC_TCL_R2_SW2TCL3_RING_TP__TAIL_PTR___S 0 +#define UMAC_TCL_R2_SW2TCL3_RING_TP___M 0x000FFFFF +#define UMAC_TCL_R2_SW2TCL3_RING_TP___S 0 + +#define UMAC_TCL_R2_SW2TCL_CREDIT_RING_HP (0x00A46018) +#define UMAC_TCL_R2_SW2TCL_CREDIT_RING_HP___RWC QCSR_REG_RW +#define UMAC_TCL_R2_SW2TCL_CREDIT_RING_HP___POR 0x00000000 +#define UMAC_TCL_R2_SW2TCL_CREDIT_RING_HP__HEAD_PTR___POR 0x00000 +#define UMAC_TCL_R2_SW2TCL_CREDIT_RING_HP__HEAD_PTR___M 0x000FFFFF +#define UMAC_TCL_R2_SW2TCL_CREDIT_RING_HP__HEAD_PTR___S 0 +#define UMAC_TCL_R2_SW2TCL_CREDIT_RING_HP___M 0x000FFFFF +#define UMAC_TCL_R2_SW2TCL_CREDIT_RING_HP___S 0 + +#define UMAC_TCL_R2_SW2TCL_CREDIT_RING_TP (0x00A4601C) +#define UMAC_TCL_R2_SW2TCL_CREDIT_RING_TP___RWC QCSR_REG_RW +#define UMAC_TCL_R2_SW2TCL_CREDIT_RING_TP___POR 0x00000000 +#define UMAC_TCL_R2_SW2TCL_CREDIT_RING_TP__TAIL_PTR___POR 0x00000 +#define UMAC_TCL_R2_SW2TCL_CREDIT_RING_TP__TAIL_PTR___M 0x000FFFFF +#define UMAC_TCL_R2_SW2TCL_CREDIT_RING_TP__TAIL_PTR___S 0 +#define UMAC_TCL_R2_SW2TCL_CREDIT_RING_TP___M 0x000FFFFF +#define UMAC_TCL_R2_SW2TCL_CREDIT_RING_TP___S 0 + +#define UMAC_TCL_R2_FW2TCL1_RING_HP (0x00A46020) +#define UMAC_TCL_R2_FW2TCL1_RING_HP___RWC QCSR_REG_RW +#define UMAC_TCL_R2_FW2TCL1_RING_HP___POR 0x00000000 +#define UMAC_TCL_R2_FW2TCL1_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_TCL_R2_FW2TCL1_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_TCL_R2_FW2TCL1_RING_HP__HEAD_PTR___S 0 +#define UMAC_TCL_R2_FW2TCL1_RING_HP___M 0x0000FFFF +#define UMAC_TCL_R2_FW2TCL1_RING_HP___S 0 + +#define UMAC_TCL_R2_FW2TCL1_RING_TP (0x00A46024) +#define UMAC_TCL_R2_FW2TCL1_RING_TP___RWC QCSR_REG_RW +#define UMAC_TCL_R2_FW2TCL1_RING_TP___POR 0x00000000 +#define UMAC_TCL_R2_FW2TCL1_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_TCL_R2_FW2TCL1_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_TCL_R2_FW2TCL1_RING_TP__TAIL_PTR___S 0 +#define UMAC_TCL_R2_FW2TCL1_RING_TP___M 0x0000FFFF +#define UMAC_TCL_R2_FW2TCL1_RING_TP___S 0 + +#define UMAC_TCL_R2_TCL2TQM_RING_HP (0x00A46028) +#define UMAC_TCL_R2_TCL2TQM_RING_HP___RWC QCSR_REG_RW +#define UMAC_TCL_R2_TCL2TQM_RING_HP___POR 0x00000000 +#define UMAC_TCL_R2_TCL2TQM_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_TCL_R2_TCL2TQM_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_TCL_R2_TCL2TQM_RING_HP__HEAD_PTR___S 0 +#define UMAC_TCL_R2_TCL2TQM_RING_HP___M 0x0000FFFF +#define UMAC_TCL_R2_TCL2TQM_RING_HP___S 0 + +#define UMAC_TCL_R2_TCL2TQM_RING_TP (0x00A4602C) +#define UMAC_TCL_R2_TCL2TQM_RING_TP___RWC QCSR_REG_RW +#define UMAC_TCL_R2_TCL2TQM_RING_TP___POR 0x00000000 +#define UMAC_TCL_R2_TCL2TQM_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_TCL_R2_TCL2TQM_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_TCL_R2_TCL2TQM_RING_TP__TAIL_PTR___S 0 +#define UMAC_TCL_R2_TCL2TQM_RING_TP___M 0x0000FFFF +#define UMAC_TCL_R2_TCL2TQM_RING_TP___S 0 + +#define UMAC_TCL_R2_TCL_STATUS1_RING_HP (0x00A46030) +#define UMAC_TCL_R2_TCL_STATUS1_RING_HP___RWC QCSR_REG_RW +#define UMAC_TCL_R2_TCL_STATUS1_RING_HP___POR 0x00000000 +#define UMAC_TCL_R2_TCL_STATUS1_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_TCL_R2_TCL_STATUS1_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_TCL_R2_TCL_STATUS1_RING_HP__HEAD_PTR___S 0 +#define UMAC_TCL_R2_TCL_STATUS1_RING_HP___M 0x0000FFFF +#define UMAC_TCL_R2_TCL_STATUS1_RING_HP___S 0 + +#define UMAC_TCL_R2_TCL_STATUS1_RING_TP (0x00A46034) +#define UMAC_TCL_R2_TCL_STATUS1_RING_TP___RWC QCSR_REG_RW +#define UMAC_TCL_R2_TCL_STATUS1_RING_TP___POR 0x00000000 +#define UMAC_TCL_R2_TCL_STATUS1_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_TCL_R2_TCL_STATUS1_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_TCL_R2_TCL_STATUS1_RING_TP__TAIL_PTR___S 0 +#define UMAC_TCL_R2_TCL_STATUS1_RING_TP___M 0x0000FFFF +#define UMAC_TCL_R2_TCL_STATUS1_RING_TP___S 0 + +#define UMAC_TCL_R2_TCL_STATUS2_RING_HP (0x00A46038) +#define UMAC_TCL_R2_TCL_STATUS2_RING_HP___RWC QCSR_REG_RW +#define UMAC_TCL_R2_TCL_STATUS2_RING_HP___POR 0x00000000 +#define UMAC_TCL_R2_TCL_STATUS2_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_TCL_R2_TCL_STATUS2_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_TCL_R2_TCL_STATUS2_RING_HP__HEAD_PTR___S 0 +#define UMAC_TCL_R2_TCL_STATUS2_RING_HP___M 0x0000FFFF +#define UMAC_TCL_R2_TCL_STATUS2_RING_HP___S 0 + +#define UMAC_TCL_R2_TCL_STATUS2_RING_TP (0x00A4603C) +#define UMAC_TCL_R2_TCL_STATUS2_RING_TP___RWC QCSR_REG_RW +#define UMAC_TCL_R2_TCL_STATUS2_RING_TP___POR 0x00000000 +#define UMAC_TCL_R2_TCL_STATUS2_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_TCL_R2_TCL_STATUS2_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_TCL_R2_TCL_STATUS2_RING_TP__TAIL_PTR___S 0 +#define UMAC_TCL_R2_TCL_STATUS2_RING_TP___M 0x0000FFFF +#define UMAC_TCL_R2_TCL_STATUS2_RING_TP___S 0 + +#define UMAC_TCL_R2_TCL2FW_RING_HP (0x00A46040) +#define UMAC_TCL_R2_TCL2FW_RING_HP___RWC QCSR_REG_RW +#define UMAC_TCL_R2_TCL2FW_RING_HP___POR 0x00000000 +#define UMAC_TCL_R2_TCL2FW_RING_HP__HEAD_PTR___POR 0x0000 +#define UMAC_TCL_R2_TCL2FW_RING_HP__HEAD_PTR___M 0x0000FFFF +#define UMAC_TCL_R2_TCL2FW_RING_HP__HEAD_PTR___S 0 +#define UMAC_TCL_R2_TCL2FW_RING_HP___M 0x0000FFFF +#define UMAC_TCL_R2_TCL2FW_RING_HP___S 0 + +#define UMAC_TCL_R2_TCL2FW_RING_TP (0x00A46044) +#define UMAC_TCL_R2_TCL2FW_RING_TP___RWC QCSR_REG_RW +#define UMAC_TCL_R2_TCL2FW_RING_TP___POR 0x00000000 +#define UMAC_TCL_R2_TCL2FW_RING_TP__TAIL_PTR___POR 0x0000 +#define UMAC_TCL_R2_TCL2FW_RING_TP__TAIL_PTR___M 0x0000FFFF +#define UMAC_TCL_R2_TCL2FW_RING_TP__TAIL_PTR___S 0 +#define UMAC_TCL_R2_TCL2FW_RING_TP___M 0x0000FFFF +#define UMAC_TCL_R2_TCL2FW_RING_TP___S 0 + +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_0 (0x00A47000) +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_0___RWC QCSR_REG_RO +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_0___POR 0x00000000 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_LEN___POR 0x000 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_ID___POR 0x00 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_LEN___M 0x000FFF00 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_LEN___S 8 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_ID___M 0x000000FF +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_ID___S 0 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_0___M 0x000FFFFF +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_0___S 0 + +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_1 (0x00A47004) +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_1___RWC QCSR_REG_RO +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_1___POR 0x0000002B +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_LEN___POR 0x000 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_ID___POR 0x2B +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_LEN___M 0x000FFF00 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_LEN___S 8 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_ID___M 0x000000FF +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_ID___S 0 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_1___M 0x000FFFFF +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_1___S 0 + +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_2 (0x00A47008) +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_2___RWC QCSR_REG_RO +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_2___POR 0x0000003C +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_LEN___POR 0x000 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_ID___POR 0x3C +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_LEN___M 0x000FFF00 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_LEN___S 8 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_ID___M 0x000000FF +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_ID___S 0 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_2___M 0x000FFFFF +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_2___S 0 + +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_3 (0x00A4700C) +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_3___RWC QCSR_REG_RO +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_3___POR 0x00000033 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_LEN___POR 0x000 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_ID___POR 0x33 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_LEN___M 0x000FFF00 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_LEN___S 8 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_ID___M 0x000000FF +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_ID___S 0 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_3___M 0x000FFFFF +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_3___S 0 + +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_4 (0x00A47010) +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_4___RWC QCSR_REG_RO +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_4___POR 0x00000887 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_LEN___POR 0x008 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_ID___POR 0x87 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_LEN___M 0x000FFF00 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_LEN___S 8 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_ID___M 0x000000FF +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_ID___S 0 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_4___M 0x000FFFFF +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_4___S 0 + +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_5 (0x00A47014) +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_5___RWC QCSR_REG_RO +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_5___POR 0x0000082C +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_LEN___POR 0x008 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_ID___POR 0x2C +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_LEN___M 0x000FFF00 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_LEN___S 8 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_ID___M 0x000000FF +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_ID___S 0 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_5___M 0x000FFFFF +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_5___S 0 + +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_6 (0x00A47018) +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_6___RWC QCSR_REG_RW +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_6___POR 0x00000000 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_LEN___POR 0x000 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_ID___POR 0x00 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_LEN___M 0x000FFF00 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_LEN___S 8 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_ID___M 0x000000FF +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_ID___S 0 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_6___M 0x000FFFFF +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_6___S 0 + +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_7 (0x00A4701C) +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_7___RWC QCSR_REG_RW +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_7___POR 0x00000000 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_LEN___POR 0x000 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_ID___POR 0x00 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_LEN___M 0x000FFF00 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_LEN___S 8 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_ID___M 0x000000FF +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_ID___S 0 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_7___M 0x000FFFFF +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_7___S 0 + +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_8 (0x00A47020) +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_8___RWC QCSR_REG_RW +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_8___POR 0x00000000 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_LEN___POR 0x000 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_ID___POR 0x00 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_LEN___M 0x000FFF00 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_LEN___S 8 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_ID___M 0x000000FF +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_ID___S 0 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_8___M 0x000FFFFF +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_8___S 0 + +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_9 (0x00A47024) +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_9___RWC QCSR_REG_RW +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_9___POR 0x00000000 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_LEN___POR 0x000 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_ID___POR 0x00 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_LEN___M 0x000FFF00 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_LEN___S 8 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_ID___M 0x000000FF +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_ID___S 0 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_9___M 0x000FFFFF +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_9___S 0 + +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_10 (0x00A47028) +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_10___RWC QCSR_REG_RW +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_10___POR 0x00000000 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_LEN___POR 0x000 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_ID___POR 0x00 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_LEN___M 0x000FFF00 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_LEN___S 8 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_ID___M 0x000000FF +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_ID___S 0 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_10___M 0x000FFFFF +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_10___S 0 + +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_11 (0x00A4702C) +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_11___RWC QCSR_REG_RW +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_11___POR 0x00000000 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_LEN___POR 0x000 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_ID___POR 0x00 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_LEN___M 0x000FFF00 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_LEN___S 8 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_ID___M 0x000000FF +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_ID___S 0 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_11___M 0x000FFFFF +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_11___S 0 + +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_12 (0x00A47030) +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_12___RWC QCSR_REG_RW +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_12___POR 0x00000000 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_LEN___POR 0x000 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_ID___POR 0x00 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_LEN___M 0x000FFF00 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_LEN___S 8 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_ID___M 0x000000FF +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_ID___S 0 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_12___M 0x000FFFFF +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_12___S 0 + +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_13 (0x00A47034) +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_13___RWC QCSR_REG_RW +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_13___POR 0x00000000 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_LEN___POR 0x000 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_ID___POR 0x00 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_LEN___M 0x000FFF00 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_LEN___S 8 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_ID___M 0x000000FF +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_ID___S 0 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_13___M 0x000FFFFF +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_13___S 0 + +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_14 (0x00A47038) +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_14___RWC QCSR_REG_RW +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_14___POR 0x00000000 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_LEN___POR 0x000 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_ID___POR 0x00 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_LEN___M 0x000FFF00 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_LEN___S 8 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_ID___M 0x000000FF +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_ID___S 0 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_14___M 0x000FFFFF +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_14___S 0 + +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_15 (0x00A4703C) +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_15___RWC QCSR_REG_RW +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_15___POR 0x00000000 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_LEN___POR 0x000 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_ID___POR 0x00 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_LEN___M 0x000FFF00 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_LEN___S 8 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_ID___M 0x000000FF +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_ID___S 0 +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_15___M 0x000FFFFF +#define UMAC_CP_R0_IPV6_EXTN_HDR_IX_15___S 0 + +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_EN (0x00A47040) +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_EN___RWC QCSR_REG_RW +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_EN___POR 0x00000000 +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS1___POR 0x0 +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS0___POR 0x0 +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS1___M 0x000000F0 +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS1___S 4 +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS0___M 0x0000000F +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS0___S 0 +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_EN___M 0x000000FF +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_EN___S 0 + +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0 (0x00A47044) +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0___RWC QCSR_REG_RW +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0___POR 0x00000000 +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL3___POR 0x00 +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL2___POR 0x00 +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL1___POR 0x00 +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL0___POR 0x00 +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL3___M 0xFF000000 +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL3___S 24 +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL2___M 0x00FF0000 +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL2___S 16 +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL1___M 0x0000FF00 +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL1___S 8 +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL0___M 0x000000FF +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL0___S 0 +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0___M 0xFFFFFFFF +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0___S 0 + +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1 (0x00A47048) +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1___RWC QCSR_REG_RW +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1___POR 0x00000000 +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL7___POR 0x00 +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL6___POR 0x00 +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL5___POR 0x00 +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL4___POR 0x00 +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL7___M 0xFF000000 +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL7___S 24 +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL6___M 0x00FF0000 +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL6___S 16 +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL5___M 0x0000FF00 +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL5___S 8 +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL4___M 0x000000FF +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL4___S 0 +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1___M 0xFFFFFFFF +#define UMAC_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1___S 0 + +#define UMAC_CP_R0_IPV6_CONFIG (0x00A4704C) +#define UMAC_CP_R0_IPV6_CONFIG___RWC QCSR_REG_RW +#define UMAC_CP_R0_IPV6_CONFIG___POR 0x00000080 +#define UMAC_CP_R0_IPV6_CONFIG__USE_AH_FOR_FLOW_ID___POR 0x0 +#define UMAC_CP_R0_IPV6_CONFIG__SPI_FROM_AH_OR_ESP___POR 0x0 +#define UMAC_CP_R0_IPV6_CONFIG__L4_BYTES_EXCEEDED_256___POR 0x0 +#define UMAC_CP_R0_IPV6_CONFIG__L3_BYTES_EXCEEDED_256___POR 0x0 +#define UMAC_CP_R0_IPV6_CONFIG__EXT_HEADER_BYTES___POR 0x80 +#define UMAC_CP_R0_IPV6_CONFIG__USE_AH_FOR_FLOW_ID___M 0x00000800 +#define UMAC_CP_R0_IPV6_CONFIG__USE_AH_FOR_FLOW_ID___S 11 +#define UMAC_CP_R0_IPV6_CONFIG__SPI_FROM_AH_OR_ESP___M 0x00000400 +#define UMAC_CP_R0_IPV6_CONFIG__SPI_FROM_AH_OR_ESP___S 10 +#define UMAC_CP_R0_IPV6_CONFIG__L4_BYTES_EXCEEDED_256___M 0x00000200 +#define UMAC_CP_R0_IPV6_CONFIG__L4_BYTES_EXCEEDED_256___S 9 +#define UMAC_CP_R0_IPV6_CONFIG__L3_BYTES_EXCEEDED_256___M 0x00000100 +#define UMAC_CP_R0_IPV6_CONFIG__L3_BYTES_EXCEEDED_256___S 8 +#define UMAC_CP_R0_IPV6_CONFIG__EXT_HEADER_BYTES___M 0x000000FF +#define UMAC_CP_R0_IPV6_CONFIG__EXT_HEADER_BYTES___S 0 +#define UMAC_CP_R0_IPV6_CONFIG___M 0x00000FFF +#define UMAC_CP_R0_IPV6_CONFIG___S 0 + +#define UMAC_CP_R0_COMMIT_TLV_CONFIG (0x00A47050) +#define UMAC_CP_R0_COMMIT_TLV_CONFIG___RWC QCSR_REG_RO +#define UMAC_CP_R0_COMMIT_TLV_CONFIG___POR 0x00010040 +#define UMAC_CP_R0_COMMIT_TLV_CONFIG__COMMIT_DONE_NUM___POR 0x100 +#define UMAC_CP_R0_COMMIT_TLV_CONFIG__COMMIT_NUM___POR 0x40 +#define UMAC_CP_R0_COMMIT_TLV_CONFIG__COMMIT_DONE_NUM___M 0x0001FF00 +#define UMAC_CP_R0_COMMIT_TLV_CONFIG__COMMIT_DONE_NUM___S 8 +#define UMAC_CP_R0_COMMIT_TLV_CONFIG__COMMIT_NUM___M 0x000000FF +#define UMAC_CP_R0_COMMIT_TLV_CONFIG__COMMIT_NUM___S 0 +#define UMAC_CP_R0_COMMIT_TLV_CONFIG___M 0x0001FFFF +#define UMAC_CP_R0_COMMIT_TLV_CONFIG___S 0 + +#define UMAC_CP_R0_CLKGATE_DISABLE (0x00A47054) +#define UMAC_CP_R0_CLKGATE_DISABLE___RWC QCSR_REG_RW +#define UMAC_CP_R0_CLKGATE_DISABLE___POR 0x00000000 +#define UMAC_CP_R0_CLKGATE_DISABLE__CLK_EXTEND___POR 0x0 +#define UMAC_CP_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___POR 0x0 +#define UMAC_CP_R0_CLKGATE_DISABLE__CP_RSRVD___POR 0x000000 +#define UMAC_CP_R0_CLKGATE_DISABLE__CCE_SM___POR 0x0 +#define UMAC_CP_R0_CLKGATE_DISABLE__NWIFI___POR 0x0 +#define UMAC_CP_R0_CLKGATE_DISABLE__ETH___POR 0x0 +#define UMAC_CP_R0_CLKGATE_DISABLE__AMSDU_11AH___POR 0x0 +#define UMAC_CP_R0_CLKGATE_DISABLE__AMSDU_11AC___POR 0x0 +#define UMAC_CP_R0_CLKGATE_DISABLE__WIFI___POR 0x0 +#define UMAC_CP_R0_CLKGATE_DISABLE__CORE___POR 0x0 +#define UMAC_CP_R0_CLKGATE_DISABLE__APB___POR 0x0 +#define UMAC_CP_R0_CLKGATE_DISABLE__CLK_EXTEND___M 0x80000000 +#define UMAC_CP_R0_CLKGATE_DISABLE__CLK_EXTEND___S 31 +#define UMAC_CP_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___M 0x40000000 +#define UMAC_CP_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___S 30 +#define UMAC_CP_R0_CLKGATE_DISABLE__CP_RSRVD___M 0x3FFFFF00 +#define UMAC_CP_R0_CLKGATE_DISABLE__CP_RSRVD___S 8 +#define UMAC_CP_R0_CLKGATE_DISABLE__CCE_SM___M 0x00000080 +#define UMAC_CP_R0_CLKGATE_DISABLE__CCE_SM___S 7 +#define UMAC_CP_R0_CLKGATE_DISABLE__NWIFI___M 0x00000040 +#define UMAC_CP_R0_CLKGATE_DISABLE__NWIFI___S 6 +#define UMAC_CP_R0_CLKGATE_DISABLE__ETH___M 0x00000020 +#define UMAC_CP_R0_CLKGATE_DISABLE__ETH___S 5 +#define UMAC_CP_R0_CLKGATE_DISABLE__AMSDU_11AH___M 0x00000010 +#define UMAC_CP_R0_CLKGATE_DISABLE__AMSDU_11AH___S 4 +#define UMAC_CP_R0_CLKGATE_DISABLE__AMSDU_11AC___M 0x00000008 +#define UMAC_CP_R0_CLKGATE_DISABLE__AMSDU_11AC___S 3 +#define UMAC_CP_R0_CLKGATE_DISABLE__WIFI___M 0x00000004 +#define UMAC_CP_R0_CLKGATE_DISABLE__WIFI___S 2 +#define UMAC_CP_R0_CLKGATE_DISABLE__CORE___M 0x00000002 +#define UMAC_CP_R0_CLKGATE_DISABLE__CORE___S 1 +#define UMAC_CP_R0_CLKGATE_DISABLE__APB___M 0x00000001 +#define UMAC_CP_R0_CLKGATE_DISABLE__APB___S 0 +#define UMAC_CP_R0_CLKGATE_DISABLE___M 0xFFFFFFFF +#define UMAC_CP_R0_CLKGATE_DISABLE___S 0 + +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_0 (0x00A47058) +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_0___RWC QCSR_REG_RW +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_0___POR 0x00000000 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_0__VALUE___POR 0x00000000 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_0__VALUE___M 0xFFFFFFFF +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_0__VALUE___S 0 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_0___M 0xFFFFFFFF +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_0___S 0 + +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_1 (0x00A4705C) +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_1___RWC QCSR_REG_RW +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_1___POR 0x00000000 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_1__VALUE___POR 0x00000000 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_1__VALUE___M 0xFFFFFFFF +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_1__VALUE___S 0 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_1___M 0xFFFFFFFF +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_1___S 0 + +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_2 (0x00A47060) +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_2___RWC QCSR_REG_RW +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_2___POR 0x00000000 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_2__VALUE___POR 0x00000000 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_2__VALUE___M 0xFFFFFFFF +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_2__VALUE___S 0 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_2___M 0xFFFFFFFF +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_2___S 0 + +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_3 (0x00A47064) +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_3___RWC QCSR_REG_RW +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_3___POR 0x00000000 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_3__VALUE___POR 0x00000000 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_3__VALUE___M 0xFFFFFFFF +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_3__VALUE___S 0 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_3___M 0xFFFFFFFF +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IX_3___S 0 + +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_0 (0x00A47068) +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_0___RWC QCSR_REG_RW +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_0___POR 0x00000000 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_0__VALUE___POR 0x00000000 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_0__VALUE___M 0xFFFFFFFF +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_0__VALUE___S 0 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_0___M 0xFFFFFFFF +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_0___S 0 + +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_1 (0x00A4706C) +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_1___RWC QCSR_REG_RW +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_1___POR 0x00000000 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_1__VALUE___POR 0x00000000 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_1__VALUE___M 0xFFFFFFFF +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_1__VALUE___S 0 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_1___M 0xFFFFFFFF +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_1___S 0 + +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_2 (0x00A47070) +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_2___RWC QCSR_REG_RW +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_2___POR 0x00000000 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_2__VALUE___POR 0x00000000 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_2__VALUE___M 0xFFFFFFFF +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_2__VALUE___S 0 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_2___M 0xFFFFFFFF +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_2___S 0 + +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_3 (0x00A47074) +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_3___RWC QCSR_REG_RW +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_3___POR 0x00000000 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_3__VALUE___POR 0x00000000 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_3__VALUE___M 0xFFFFFFFF +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_3__VALUE___S 0 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_3___M 0xFFFFFFFF +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_3___S 0 + +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_4 (0x00A47078) +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_4___RWC QCSR_REG_RW +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_4___POR 0x00000000 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_4__VALUE___POR 0x00000000 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_4__VALUE___M 0xFFFFFFFF +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_4__VALUE___S 0 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_4___M 0xFFFFFFFF +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_4___S 0 + +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_5 (0x00A4707C) +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_5___RWC QCSR_REG_RW +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_5___POR 0x00000000 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_5__VALUE___POR 0x00000000 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_5__VALUE___M 0xFFFFFFFF +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_5__VALUE___S 0 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_5___M 0xFFFFFFFF +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_5___S 0 + +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_6 (0x00A47080) +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_6___RWC QCSR_REG_RW +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_6___POR 0x00000000 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_6__VALUE___POR 0x00000000 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_6__VALUE___M 0xFFFFFFFF +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_6__VALUE___S 0 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_6___M 0xFFFFFFFF +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_6___S 0 + +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_7 (0x00A47084) +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_7___RWC QCSR_REG_RW +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_7___POR 0x00000000 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_7__VALUE___POR 0x00000000 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_7__VALUE___M 0xFFFFFFFF +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_7__VALUE___S 0 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_7___M 0xFFFFFFFF +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_7___S 0 + +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_8 (0x00A47088) +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_8___RWC QCSR_REG_RW +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_8___POR 0x00000000 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_8__VALUE___POR 0x00000000 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_8__VALUE___M 0xFFFFFFFF +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_8__VALUE___S 0 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_8___M 0xFFFFFFFF +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_8___S 0 + +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_9 (0x00A4708C) +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_9___RWC QCSR_REG_RW +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_9___POR 0x00000000 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_9__VALUE___POR 0x00000000 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_9__VALUE___M 0xFFFFFFFF +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_9__VALUE___S 0 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_9___M 0xFFFFFFFF +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV6_IX_9___S 0 + +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IPV6 (0x00A47090) +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IPV6___RWC QCSR_REG_RW +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IPV6___POR 0x00000000 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IPV6__VALUE_1___POR 0x00 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IPV6__VALUE_0___POR 0x00 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IPV6__VALUE_1___M 0x0000FF00 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IPV6__VALUE_1___S 8 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IPV6__VALUE_0___M 0x000000FF +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IPV6__VALUE_0___S 0 +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IPV6___M 0x0000FFFF +#define UMAC_CP_R0_TOEPLITZ_KEY_IPV4_IPV6___S 0 + +#define UMAC_CP_R0_MISC_CONFIG (0x00A47094) +#define UMAC_CP_R0_MISC_CONFIG___RWC QCSR_REG_RW +#define UMAC_CP_R0_MISC_CONFIG___POR 0x0001E110 +#define UMAC_CP_R0_MISC_CONFIG__REPORT_FLOW_ID_OR_HASH_3___POR 0x0 +#define UMAC_CP_R0_MISC_CONFIG__ETH_MIN_PACKET_LEN___POR 0x003C +#define UMAC_CP_R0_MISC_CONFIG__TIMEOUT_EN___POR 0x0 +#define UMAC_CP_R0_MISC_CONFIG__ENABLE_C9D1___POR 0x0 +#define UMAC_CP_R0_MISC_CONFIG__VLAN_LLC_FOR_802_3___POR 0x1 +#define UMAC_CP_R0_MISC_CONFIG__IP_DA_SA_PREFIX___POR 0x0 +#define UMAC_CP_R0_MISC_CONFIG__UDP_LITE_PARSE_EN___POR 0x0 +#define UMAC_CP_R0_MISC_CONFIG__TPID_BITMAP_VALUE___POR 0x10 +#define UMAC_CP_R0_MISC_CONFIG__REPORT_FLOW_ID_OR_HASH_3___M 0x08000000 +#define UMAC_CP_R0_MISC_CONFIG__REPORT_FLOW_ID_OR_HASH_3___S 27 +#define UMAC_CP_R0_MISC_CONFIG__ETH_MIN_PACKET_LEN___M 0x07FFF800 +#define UMAC_CP_R0_MISC_CONFIG__ETH_MIN_PACKET_LEN___S 11 +#define UMAC_CP_R0_MISC_CONFIG__TIMEOUT_EN___M 0x00000400 +#define UMAC_CP_R0_MISC_CONFIG__TIMEOUT_EN___S 10 +#define UMAC_CP_R0_MISC_CONFIG__ENABLE_C9D1___M 0x00000200 +#define UMAC_CP_R0_MISC_CONFIG__ENABLE_C9D1___S 9 +#define UMAC_CP_R0_MISC_CONFIG__VLAN_LLC_FOR_802_3___M 0x00000100 +#define UMAC_CP_R0_MISC_CONFIG__VLAN_LLC_FOR_802_3___S 8 +#define UMAC_CP_R0_MISC_CONFIG__IP_DA_SA_PREFIX___M 0x000000C0 +#define UMAC_CP_R0_MISC_CONFIG__IP_DA_SA_PREFIX___S 6 +#define UMAC_CP_R0_MISC_CONFIG__UDP_LITE_PARSE_EN___M 0x00000020 +#define UMAC_CP_R0_MISC_CONFIG__UDP_LITE_PARSE_EN___S 5 +#define UMAC_CP_R0_MISC_CONFIG__TPID_BITMAP_VALUE___M 0x0000001F +#define UMAC_CP_R0_MISC_CONFIG__TPID_BITMAP_VALUE___S 0 +#define UMAC_CP_R0_MISC_CONFIG___M 0x0FFFFFFF +#define UMAC_CP_R0_MISC_CONFIG___S 0 + +#define UMAC_CP_R0_WATCHDOG_TIMER (0x00A47098) +#define UMAC_CP_R0_WATCHDOG_TIMER___RWC QCSR_REG_RW +#define UMAC_CP_R0_WATCHDOG_TIMER___POR 0x00000000 +#define UMAC_CP_R0_WATCHDOG_TIMER__VALUE___POR 0x00000000 +#define UMAC_CP_R0_WATCHDOG_TIMER__ENABLE___POR 0x0 +#define UMAC_CP_R0_WATCHDOG_TIMER__VALUE___M 0xFFFFFFFE +#define UMAC_CP_R0_WATCHDOG_TIMER__VALUE___S 1 +#define UMAC_CP_R0_WATCHDOG_TIMER__ENABLE___M 0x00000001 +#define UMAC_CP_R0_WATCHDOG_TIMER__ENABLE___S 0 +#define UMAC_CP_R0_WATCHDOG_TIMER___M 0xFFFFFFFF +#define UMAC_CP_R0_WATCHDOG_TIMER___S 0 + +#define UMAC_CP_R1_REG_ACCESS_EVENT_GEN_CTRL (0x00A48000) +#define UMAC_CP_R1_REG_ACCESS_EVENT_GEN_CTRL___RWC QCSR_REG_RW +#define UMAC_CP_R1_REG_ACCESS_EVENT_GEN_CTRL___POR 0x7FFE0002 +#define UMAC_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___POR 0x3FFF +#define UMAC_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___POR 0x0000 +#define UMAC_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___POR 0x1 +#define UMAC_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___POR 0x0 +#define UMAC_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___M 0xFFFE0000 +#define UMAC_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___S 17 +#define UMAC_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___M 0x0001FFFC +#define UMAC_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___S 2 +#define UMAC_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___M 0x00000002 +#define UMAC_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___S 1 +#define UMAC_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___M 0x00000001 +#define UMAC_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___S 0 +#define UMAC_CP_R1_REG_ACCESS_EVENT_GEN_CTRL___M 0xFFFFFFFF +#define UMAC_CP_R1_REG_ACCESS_EVENT_GEN_CTRL___S 0 + +#define UMAC_CP_R1_SM_STATES (0x00A48004) +#define UMAC_CP_R1_SM_STATES___RWC QCSR_REG_RO +#define UMAC_CP_R1_SM_STATES___POR 0x00000000 +#define UMAC_CP_R1_SM_STATES__MISC___POR 0x000000 +#define UMAC_CP_R1_SM_STATES__STATE_INFO___POR 0x00 +#define UMAC_CP_R1_SM_STATES__STATE_MAIN___POR 0x00 +#define UMAC_CP_R1_SM_STATES__MISC___M 0xFFFFFC00 +#define UMAC_CP_R1_SM_STATES__MISC___S 10 +#define UMAC_CP_R1_SM_STATES__STATE_INFO___M 0x000003E0 +#define UMAC_CP_R1_SM_STATES__STATE_INFO___S 5 +#define UMAC_CP_R1_SM_STATES__STATE_MAIN___M 0x0000001F +#define UMAC_CP_R1_SM_STATES__STATE_MAIN___S 0 +#define UMAC_CP_R1_SM_STATES___M 0xFFFFFFFF +#define UMAC_CP_R1_SM_STATES___S 0 + +#define UMAC_CP_R1_END_OF_TEST_CHECK (0x00A48008) +#define UMAC_CP_R1_END_OF_TEST_CHECK___RWC QCSR_REG_RW +#define UMAC_CP_R1_END_OF_TEST_CHECK___POR 0x00000000 +#define UMAC_CP_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0 +#define UMAC_CP_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001 +#define UMAC_CP_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S 0 +#define UMAC_CP_R1_END_OF_TEST_CHECK___M 0x00000001 +#define UMAC_CP_R1_END_OF_TEST_CHECK___S 0 + + +#define WMAC0 (0x00A80000) + +#define WMAC0_PDG_R0_CONFIG (0x00A80000) +#define WMAC0_PDG_R0_CONFIG___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_CONFIG___POR 0x00000010 +#define WMAC0_PDG_R0_CONFIG__SW_11J_11AF_EN___POR 0x0 +#define WMAC0_PDG_R0_CONFIG__SW_11J_11AF_SCALE_FACTOR___POR 0x00 +#define WMAC0_PDG_R0_CONFIG__SW_SIFS_TIME___POR 0x10 +#define WMAC0_PDG_R0_CONFIG__SW_11J_11AF_EN___M 0x00002000 +#define WMAC0_PDG_R0_CONFIG__SW_11J_11AF_EN___S 13 +#define WMAC0_PDG_R0_CONFIG__SW_11J_11AF_SCALE_FACTOR___M 0x00001F00 +#define WMAC0_PDG_R0_CONFIG__SW_11J_11AF_SCALE_FACTOR___S 8 +#define WMAC0_PDG_R0_CONFIG__SW_SIFS_TIME___M 0x000000FF +#define WMAC0_PDG_R0_CONFIG__SW_SIFS_TIME___S 0 +#define WMAC0_PDG_R0_CONFIG___M 0x00003FFF +#define WMAC0_PDG_R0_CONFIG___S 0 + +#define WMAC0_PDG_R0_SCRAMBLING_OVERIDE (0x00A80004) +#define WMAC0_PDG_R0_SCRAMBLING_OVERIDE___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_SCRAMBLING_OVERIDE___POR 0x00000000 +#define WMAC0_PDG_R0_SCRAMBLING_OVERIDE__DISABLE_ALL_ZERO_CHECK___POR 0x0 +#define WMAC0_PDG_R0_SCRAMBLING_OVERIDE__FORCE_TX_SERVICE_ZERO___POR 0x0 +#define WMAC0_PDG_R0_SCRAMBLING_OVERIDE__FORCE_SW_SHIFT_REG_WORD___POR 0x0 +#define WMAC0_PDG_R0_SCRAMBLING_OVERIDE__SCRAMBLING_SHIFT_REG_WORD___POR 0x00 +#define WMAC0_PDG_R0_SCRAMBLING_OVERIDE__DISABLE_ALL_ZERO_CHECK___M 0x00000200 +#define WMAC0_PDG_R0_SCRAMBLING_OVERIDE__DISABLE_ALL_ZERO_CHECK___S 9 +#define WMAC0_PDG_R0_SCRAMBLING_OVERIDE__FORCE_TX_SERVICE_ZERO___M 0x00000100 +#define WMAC0_PDG_R0_SCRAMBLING_OVERIDE__FORCE_TX_SERVICE_ZERO___S 8 +#define WMAC0_PDG_R0_SCRAMBLING_OVERIDE__FORCE_SW_SHIFT_REG_WORD___M 0x00000080 +#define WMAC0_PDG_R0_SCRAMBLING_OVERIDE__FORCE_SW_SHIFT_REG_WORD___S 7 +#define WMAC0_PDG_R0_SCRAMBLING_OVERIDE__SCRAMBLING_SHIFT_REG_WORD___M 0x0000007F +#define WMAC0_PDG_R0_SCRAMBLING_OVERIDE__SCRAMBLING_SHIFT_REG_WORD___S 0 +#define WMAC0_PDG_R0_SCRAMBLING_OVERIDE___M 0x000003FF +#define WMAC0_PDG_R0_SCRAMBLING_OVERIDE___S 0 + +#define WMAC0_PDG_R0_CLKGATE_DISABLE (0x00A80008) +#define WMAC0_PDG_R0_CLKGATE_DISABLE___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_CLKGATE_DISABLE___POR 0x80000000 +#define WMAC0_PDG_R0_CLKGATE_DISABLE__CLK_ENS_EXTEND___POR 0x1 +#define WMAC0_PDG_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___POR 0x0 +#define WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_MEM___POR 0x0 +#define WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_DEBUG___POR 0x0 +#define WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_D2H___POR 0x0 +#define WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_H2D___POR 0x0 +#define WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_TXPCU_INTF___POR 0x0 +#define WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_AMPDU_COMP___POR 0x0 +#define WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_PROC_UNIT___POR 0x0 +#define WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_MAIN___POR 0x0 +#define WMAC0_PDG_R0_CLKGATE_DISABLE__CLK_ENS_EXTEND___M 0x80000000 +#define WMAC0_PDG_R0_CLKGATE_DISABLE__CLK_ENS_EXTEND___S 31 +#define WMAC0_PDG_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___M 0x40000000 +#define WMAC0_PDG_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___S 30 +#define WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_MEM___M 0x00000080 +#define WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_MEM___S 7 +#define WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_DEBUG___M 0x00000040 +#define WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_DEBUG___S 6 +#define WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_D2H___M 0x00000020 +#define WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_D2H___S 5 +#define WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_H2D___M 0x00000010 +#define WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_H2D___S 4 +#define WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_TXPCU_INTF___M 0x00000008 +#define WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_TXPCU_INTF___S 3 +#define WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_AMPDU_COMP___M 0x00000004 +#define WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_AMPDU_COMP___S 2 +#define WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_PROC_UNIT___M 0x00000002 +#define WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_PROC_UNIT___S 1 +#define WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_MAIN___M 0x00000001 +#define WMAC0_PDG_R0_CLKGATE_DISABLE__PDG_MAIN___S 0 +#define WMAC0_PDG_R0_CLKGATE_DISABLE___M 0xC00000FF +#define WMAC0_PDG_R0_CLKGATE_DISABLE___S 0 + +#define WMAC0_PDG_R0_SLOT_TIME (0x00A8000C) +#define WMAC0_PDG_R0_SLOT_TIME___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_SLOT_TIME___POR 0x00000009 +#define WMAC0_PDG_R0_SLOT_TIME__PDG_SLOT_TIME___POR 0x0009 +#define WMAC0_PDG_R0_SLOT_TIME__PDG_SLOT_TIME___M 0x0000FFFF +#define WMAC0_PDG_R0_SLOT_TIME__PDG_SLOT_TIME___S 0 +#define WMAC0_PDG_R0_SLOT_TIME___M 0x0000FFFF +#define WMAC0_PDG_R0_SLOT_TIME___S 0 + +#define WMAC0_PDG_R0_FEATURE_ENABLE (0x00A80010) +#define WMAC0_PDG_R0_FEATURE_ENABLE___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_FEATURE_ENABLE___POR 0x00396300 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ECO___POR 0x000E +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_CPU_IF_HW_UPDATE___POR 0x0 +#define WMAC0_PDG_R0_FEATURE_ENABLE__MPDU_INFO_END_OUT_OF_ORDER_ENABLE___POR 0x1 +#define WMAC0_PDG_R0_FEATURE_ENABLE__IMPROVE_BASE_MUL_FACTOR_ACCURACY___POR 0x0 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_FW_RBO_TRIG_CMN_BASE_VALUE___POR 0x1 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_MORE_DATA_TRIG_RESP_HARDCODE___POR 0x1 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_FLUSH_LDPC_EXTRA_EXCEED_TXOP___POR 0x0 +#define WMAC0_PDG_R0_FEATURE_ENABLE__H2D_TLV_LEAK_FIX_DISABLE___POR 0x0 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_FLUSH_PREM_TX_FES_SETUP___POR 0x0 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_HKV2_ECO_OUT_OF_ORDER_MPDU_INFO___POR 0x1 +#define WMAC0_PDG_R0_FEATURE_ENABLE__DISABLE_WAIT_FOR_TX_FLUSH___POR 0x1 +#define WMAC0_PDG_R0_FEATURE_ENABLE__DISABLE_RBO_QOS_NULL_ONE_USER_CHECK___POR 0x0 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_TRIG_PRI_CHK___POR 0x0 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_USER_UPDATE_SCRAM_SEED___POR 0x0 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_REMAINING_RX_TIME_CALC___POR 0x0 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_COEX_TX___POR 0x0 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_MPROT_UPDATE_SCRAM_SEED___POR 0x0 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_11AH_MPDU_AC_PAD___POR 0x0 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_11AH_MPDU_N_NPLD___POR 0x0 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ECO___M 0xFFFC0000 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ECO___S 18 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_CPU_IF_HW_UPDATE___M 0x00020000 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_CPU_IF_HW_UPDATE___S 17 +#define WMAC0_PDG_R0_FEATURE_ENABLE__MPDU_INFO_END_OUT_OF_ORDER_ENABLE___M 0x00010000 +#define WMAC0_PDG_R0_FEATURE_ENABLE__MPDU_INFO_END_OUT_OF_ORDER_ENABLE___S 16 +#define WMAC0_PDG_R0_FEATURE_ENABLE__IMPROVE_BASE_MUL_FACTOR_ACCURACY___M 0x00008000 +#define WMAC0_PDG_R0_FEATURE_ENABLE__IMPROVE_BASE_MUL_FACTOR_ACCURACY___S 15 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_FW_RBO_TRIG_CMN_BASE_VALUE___M 0x00004000 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_FW_RBO_TRIG_CMN_BASE_VALUE___S 14 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_MORE_DATA_TRIG_RESP_HARDCODE___M 0x00002000 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_MORE_DATA_TRIG_RESP_HARDCODE___S 13 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_FLUSH_LDPC_EXTRA_EXCEED_TXOP___M 0x00001000 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_FLUSH_LDPC_EXTRA_EXCEED_TXOP___S 12 +#define WMAC0_PDG_R0_FEATURE_ENABLE__H2D_TLV_LEAK_FIX_DISABLE___M 0x00000800 +#define WMAC0_PDG_R0_FEATURE_ENABLE__H2D_TLV_LEAK_FIX_DISABLE___S 11 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_FLUSH_PREM_TX_FES_SETUP___M 0x00000400 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_FLUSH_PREM_TX_FES_SETUP___S 10 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_HKV2_ECO_OUT_OF_ORDER_MPDU_INFO___M 0x00000200 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_HKV2_ECO_OUT_OF_ORDER_MPDU_INFO___S 9 +#define WMAC0_PDG_R0_FEATURE_ENABLE__DISABLE_WAIT_FOR_TX_FLUSH___M 0x00000100 +#define WMAC0_PDG_R0_FEATURE_ENABLE__DISABLE_WAIT_FOR_TX_FLUSH___S 8 +#define WMAC0_PDG_R0_FEATURE_ENABLE__DISABLE_RBO_QOS_NULL_ONE_USER_CHECK___M 0x00000080 +#define WMAC0_PDG_R0_FEATURE_ENABLE__DISABLE_RBO_QOS_NULL_ONE_USER_CHECK___S 7 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_TRIG_PRI_CHK___M 0x00000040 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_TRIG_PRI_CHK___S 6 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_USER_UPDATE_SCRAM_SEED___M 0x00000020 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_USER_UPDATE_SCRAM_SEED___S 5 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_REMAINING_RX_TIME_CALC___M 0x00000010 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_REMAINING_RX_TIME_CALC___S 4 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_COEX_TX___M 0x00000008 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_COEX_TX___S 3 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_MPROT_UPDATE_SCRAM_SEED___M 0x00000004 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_MPROT_UPDATE_SCRAM_SEED___S 2 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_11AH_MPDU_AC_PAD___M 0x00000002 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_11AH_MPDU_AC_PAD___S 1 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_11AH_MPDU_N_NPLD___M 0x00000001 +#define WMAC0_PDG_R0_FEATURE_ENABLE__ENABLE_11AH_MPDU_N_NPLD___S 0 +#define WMAC0_PDG_R0_FEATURE_ENABLE___M 0xFFFFFFFF +#define WMAC0_PDG_R0_FEATURE_ENABLE___S 0 + +#define WMAC0_PDG_R0_FEATURE_ENABLE_II (0x00A80014) +#define WMAC0_PDG_R0_FEATURE_ENABLE_II___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_FEATURE_ENABLE_II___POR 0x00005973 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__USE_MAX_PKT_EXT___POR 0x1 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_SU_MU_OFDMA_UPDATES___POR 0x0 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_MPDU_MU_SPACING_FACTOR_MUL_MMSB___POR 0x1 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_MPDU_MU_SPACING_FACTOR_MUL_FDPB___POR 0x1 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__MD_THRESHOLD_CHK___POR 0x0 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_WAIT_LATE_USER_MD___POR 0x0 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_WAIT_LATE_USER___POR 0x1 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__DISABLE_SU_D2T___POR 0x0 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__RESET_MPDU_INFO_ALL_DONE_IDLE_SIGNALLING___POR 0x1 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_SENDING_LATE_USER_MPDU_LIMIT___POR 0x1 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__PREVENT_UL_RESP_NO_MPDU_INFO_SFM_ACCESS___POR 0x1 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_TXOP_PROTECT_EXT_DUR_ADDITION___POR 0x0 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__CALC_ACCURATE_MIN_MPDU_DURATION_BITS___POR 0x0 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__IMPROVE_MIN_MPDU_DURATION_ACCURACY___POR 0x1 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_HE_RESP_TXOP_UNSPECIFIED_CHECK___POR 0x1 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__USE_MAX_PKT_EXT___M 0x00004000 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__USE_MAX_PKT_EXT___S 14 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_SU_MU_OFDMA_UPDATES___M 0x00002000 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_SU_MU_OFDMA_UPDATES___S 13 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_MPDU_MU_SPACING_FACTOR_MUL_MMSB___M 0x00001000 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_MPDU_MU_SPACING_FACTOR_MUL_MMSB___S 12 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_MPDU_MU_SPACING_FACTOR_MUL_FDPB___M 0x00000800 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_MPDU_MU_SPACING_FACTOR_MUL_FDPB___S 11 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__MD_THRESHOLD_CHK___M 0x00000400 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__MD_THRESHOLD_CHK___S 10 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_WAIT_LATE_USER_MD___M 0x00000200 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_WAIT_LATE_USER_MD___S 9 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_WAIT_LATE_USER___M 0x00000100 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_WAIT_LATE_USER___S 8 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__DISABLE_SU_D2T___M 0x00000080 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__DISABLE_SU_D2T___S 7 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__RESET_MPDU_INFO_ALL_DONE_IDLE_SIGNALLING___M 0x00000040 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__RESET_MPDU_INFO_ALL_DONE_IDLE_SIGNALLING___S 6 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_SENDING_LATE_USER_MPDU_LIMIT___M 0x00000020 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_SENDING_LATE_USER_MPDU_LIMIT___S 5 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__PREVENT_UL_RESP_NO_MPDU_INFO_SFM_ACCESS___M 0x00000010 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__PREVENT_UL_RESP_NO_MPDU_INFO_SFM_ACCESS___S 4 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_TXOP_PROTECT_EXT_DUR_ADDITION___M 0x00000008 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_TXOP_PROTECT_EXT_DUR_ADDITION___S 3 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__CALC_ACCURATE_MIN_MPDU_DURATION_BITS___M 0x00000004 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__CALC_ACCURATE_MIN_MPDU_DURATION_BITS___S 2 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__IMPROVE_MIN_MPDU_DURATION_ACCURACY___M 0x00000002 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__IMPROVE_MIN_MPDU_DURATION_ACCURACY___S 1 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_HE_RESP_TXOP_UNSPECIFIED_CHECK___M 0x00000001 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II__ENABLE_HE_RESP_TXOP_UNSPECIFIED_CHECK___S 0 +#define WMAC0_PDG_R0_FEATURE_ENABLE_II___M 0x00007FFF +#define WMAC0_PDG_R0_FEATURE_ENABLE_II___S 0 + +#define WMAC0_PDG_R0_SPARE_REG (0x00A80018) +#define WMAC0_PDG_R0_SPARE_REG___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_SPARE_REG___POR 0x00000000 +#define WMAC0_PDG_R0_SPARE_REG__ECO___POR 0x0000 +#define WMAC0_PDG_R0_SPARE_REG__ECO___M 0x0000FFFF +#define WMAC0_PDG_R0_SPARE_REG__ECO___S 0 +#define WMAC0_PDG_R0_SPARE_REG___M 0x0000FFFF +#define WMAC0_PDG_R0_SPARE_REG___S 0 + +#define WMAC0_PDG_R0_MASK_TIMER (0x00A8001C) +#define WMAC0_PDG_R0_MASK_TIMER___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_MASK_TIMER___POR 0x00000001 +#define WMAC0_PDG_R0_MASK_TIMER__WAIT_TX_FLUSH___POR 0x01 +#define WMAC0_PDG_R0_MASK_TIMER__WAIT_TX_FLUSH___M 0x000000FF +#define WMAC0_PDG_R0_MASK_TIMER__WAIT_TX_FLUSH___S 0 +#define WMAC0_PDG_R0_MASK_TIMER___M 0x000000FF +#define WMAC0_PDG_R0_MASK_TIMER___S 0 + +#define WMAC0_PDG_R0_CCK_PKT_PHY_LIMIT (0x00A80020) +#define WMAC0_PDG_R0_CCK_PKT_PHY_LIMIT___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_CCK_PKT_PHY_LIMIT___POR 0x000048C0 +#define WMAC0_PDG_R0_CCK_PKT_PHY_LIMIT__CCK_TIME_LIMIT___POR 0x48C0 +#define WMAC0_PDG_R0_CCK_PKT_PHY_LIMIT__CCK_TIME_LIMIT___M 0x0000FFFF +#define WMAC0_PDG_R0_CCK_PKT_PHY_LIMIT__CCK_TIME_LIMIT___S 0 +#define WMAC0_PDG_R0_CCK_PKT_PHY_LIMIT___M 0x0000FFFF +#define WMAC0_PDG_R0_CCK_PKT_PHY_LIMIT___S 0 + +#define WMAC0_PDG_R0_OFDM_11A_PKT_PHY_LIMIT (0x00A80024) +#define WMAC0_PDG_R0_OFDM_11A_PKT_PHY_LIMIT___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_OFDM_11A_PKT_PHY_LIMIT___POR 0x00000C1C +#define WMAC0_PDG_R0_OFDM_11A_PKT_PHY_LIMIT__OFDM_11A_TIME_LIMIT___POR 0x0C1C +#define WMAC0_PDG_R0_OFDM_11A_PKT_PHY_LIMIT__OFDM_11A_TIME_LIMIT___M 0x0000FFFF +#define WMAC0_PDG_R0_OFDM_11A_PKT_PHY_LIMIT__OFDM_11A_TIME_LIMIT___S 0 +#define WMAC0_PDG_R0_OFDM_11A_PKT_PHY_LIMIT___M 0x0000FFFF +#define WMAC0_PDG_R0_OFDM_11A_PKT_PHY_LIMIT___S 0 + +#define WMAC0_PDG_R0_OFDM_11NAC_PKT_PHY_LIMIT (0x00A80028) +#define WMAC0_PDG_R0_OFDM_11NAC_PKT_PHY_LIMIT___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_OFDM_11NAC_PKT_PHY_LIMIT___POR 0x0000156C +#define WMAC0_PDG_R0_OFDM_11NAC_PKT_PHY_LIMIT__OFDM_11NAC_TIME_LIMIT___POR 0x156C +#define WMAC0_PDG_R0_OFDM_11NAC_PKT_PHY_LIMIT__OFDM_11NAC_TIME_LIMIT___M 0x0000FFFF +#define WMAC0_PDG_R0_OFDM_11NAC_PKT_PHY_LIMIT__OFDM_11NAC_TIME_LIMIT___S 0 +#define WMAC0_PDG_R0_OFDM_11NAC_PKT_PHY_LIMIT___M 0x0000FFFF +#define WMAC0_PDG_R0_OFDM_11NAC_PKT_PHY_LIMIT___S 0 + +#define WMAC0_PDG_R0_RESP_MODE_PHY_LIMIT (0x00A8002C) +#define WMAC0_PDG_R0_RESP_MODE_PHY_LIMIT___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_RESP_MODE_PHY_LIMIT___POR 0x0000156C +#define WMAC0_PDG_R0_RESP_MODE_PHY_LIMIT__RESP_TIME_LIMIT___POR 0x156C +#define WMAC0_PDG_R0_RESP_MODE_PHY_LIMIT__RESP_TIME_LIMIT___M 0x0000FFFF +#define WMAC0_PDG_R0_RESP_MODE_PHY_LIMIT__RESP_TIME_LIMIT___S 0 +#define WMAC0_PDG_R0_RESP_MODE_PHY_LIMIT___M 0x0000FFFF +#define WMAC0_PDG_R0_RESP_MODE_PHY_LIMIT___S 0 + +#define WMAC0_PDG_R0_OFDM_11AH_1MHZ_PKT_PHY_LIMIT (0x00A80030) +#define WMAC0_PDG_R0_OFDM_11AH_1MHZ_PKT_PHY_LIMIT___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_OFDM_11AH_1MHZ_PKT_PHY_LIMIT___POR 0x0000156C +#define WMAC0_PDG_R0_OFDM_11AH_1MHZ_PKT_PHY_LIMIT__OFDM_11AH1MHZ_TIME_LIMIT___POR 0x156C +#define WMAC0_PDG_R0_OFDM_11AH_1MHZ_PKT_PHY_LIMIT__OFDM_11AH1MHZ_TIME_LIMIT___M 0x0000FFFF +#define WMAC0_PDG_R0_OFDM_11AH_1MHZ_PKT_PHY_LIMIT__OFDM_11AH1MHZ_TIME_LIMIT___S 0 +#define WMAC0_PDG_R0_OFDM_11AH_1MHZ_PKT_PHY_LIMIT___M 0x0000FFFF +#define WMAC0_PDG_R0_OFDM_11AH_1MHZ_PKT_PHY_LIMIT___S 0 + +#define WMAC0_PDG_R0_OFDM_11AH_2MHZ_PKT_PHY_LIMIT (0x00A80034) +#define WMAC0_PDG_R0_OFDM_11AH_2MHZ_PKT_PHY_LIMIT___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_OFDM_11AH_2MHZ_PKT_PHY_LIMIT___POR 0x0000156C +#define WMAC0_PDG_R0_OFDM_11AH_2MHZ_PKT_PHY_LIMIT__OFDM_11AH2MHZ_TIME_LIMIT___POR 0x156C +#define WMAC0_PDG_R0_OFDM_11AH_2MHZ_PKT_PHY_LIMIT__OFDM_11AH2MHZ_TIME_LIMIT___M 0x0000FFFF +#define WMAC0_PDG_R0_OFDM_11AH_2MHZ_PKT_PHY_LIMIT__OFDM_11AH2MHZ_TIME_LIMIT___S 0 +#define WMAC0_PDG_R0_OFDM_11AH_2MHZ_PKT_PHY_LIMIT___M 0x0000FFFF +#define WMAC0_PDG_R0_OFDM_11AH_2MHZ_PKT_PHY_LIMIT___S 0 + +#define WMAC0_PDG_R0_CCK_PKT_PHY_LTR_DELAY (0x00A80038) +#define WMAC0_PDG_R0_CCK_PKT_PHY_LTR_DELAY___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_CCK_PKT_PHY_LTR_DELAY___POR 0x00000000 +#define WMAC0_PDG_R0_CCK_PKT_PHY_LTR_DELAY__CCK_PHY_LTR_DELAY___POR 0x0000 +#define WMAC0_PDG_R0_CCK_PKT_PHY_LTR_DELAY__CCK_PHY_LTR_DELAY___M 0x0000FFFF +#define WMAC0_PDG_R0_CCK_PKT_PHY_LTR_DELAY__CCK_PHY_LTR_DELAY___S 0 +#define WMAC0_PDG_R0_CCK_PKT_PHY_LTR_DELAY___M 0x0000FFFF +#define WMAC0_PDG_R0_CCK_PKT_PHY_LTR_DELAY___S 0 + +#define WMAC0_PDG_R0_OFDM_11A_PKT_PHY_LTR_DELAY (0x00A8003C) +#define WMAC0_PDG_R0_OFDM_11A_PKT_PHY_LTR_DELAY___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_OFDM_11A_PKT_PHY_LTR_DELAY___POR 0x00000000 +#define WMAC0_PDG_R0_OFDM_11A_PKT_PHY_LTR_DELAY__OFDM_11A_LTR_DELAY___POR 0x0000 +#define WMAC0_PDG_R0_OFDM_11A_PKT_PHY_LTR_DELAY__OFDM_11A_LTR_DELAY___M 0x0000FFFF +#define WMAC0_PDG_R0_OFDM_11A_PKT_PHY_LTR_DELAY__OFDM_11A_LTR_DELAY___S 0 +#define WMAC0_PDG_R0_OFDM_11A_PKT_PHY_LTR_DELAY___M 0x0000FFFF +#define WMAC0_PDG_R0_OFDM_11A_PKT_PHY_LTR_DELAY___S 0 + +#define WMAC0_PDG_R0_OFDM_11NAC_PKT_PHY_LTR_DELAY (0x00A80040) +#define WMAC0_PDG_R0_OFDM_11NAC_PKT_PHY_LTR_DELAY___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_OFDM_11NAC_PKT_PHY_LTR_DELAY___POR 0x00000000 +#define WMAC0_PDG_R0_OFDM_11NAC_PKT_PHY_LTR_DELAY__OFDM_11NAC_LTR_DELAY___POR 0x0000 +#define WMAC0_PDG_R0_OFDM_11NAC_PKT_PHY_LTR_DELAY__OFDM_11NAC_LTR_DELAY___M 0x0000FFFF +#define WMAC0_PDG_R0_OFDM_11NAC_PKT_PHY_LTR_DELAY__OFDM_11NAC_LTR_DELAY___S 0 +#define WMAC0_PDG_R0_OFDM_11NAC_PKT_PHY_LTR_DELAY___M 0x0000FFFF +#define WMAC0_PDG_R0_OFDM_11NAC_PKT_PHY_LTR_DELAY___S 0 + +#define WMAC0_PDG_R0_OFDM_11AH_1MHZ_PKT_PHY_LTR_DELAY (0x00A80044) +#define WMAC0_PDG_R0_OFDM_11AH_1MHZ_PKT_PHY_LTR_DELAY___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_OFDM_11AH_1MHZ_PKT_PHY_LTR_DELAY___POR 0x00000000 +#define WMAC0_PDG_R0_OFDM_11AH_1MHZ_PKT_PHY_LTR_DELAY__OFDM_11AH1MHZ_LTR_DELAY___POR 0x0000 +#define WMAC0_PDG_R0_OFDM_11AH_1MHZ_PKT_PHY_LTR_DELAY__OFDM_11AH1MHZ_LTR_DELAY___M 0x0000FFFF +#define WMAC0_PDG_R0_OFDM_11AH_1MHZ_PKT_PHY_LTR_DELAY__OFDM_11AH1MHZ_LTR_DELAY___S 0 +#define WMAC0_PDG_R0_OFDM_11AH_1MHZ_PKT_PHY_LTR_DELAY___M 0x0000FFFF +#define WMAC0_PDG_R0_OFDM_11AH_1MHZ_PKT_PHY_LTR_DELAY___S 0 + +#define WMAC0_PDG_R0_OFDM_11AH_2MHZ_PKT_PHY_LTR_DELAY (0x00A80048) +#define WMAC0_PDG_R0_OFDM_11AH_2MHZ_PKT_PHY_LTR_DELAY___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_OFDM_11AH_2MHZ_PKT_PHY_LTR_DELAY___POR 0x00000000 +#define WMAC0_PDG_R0_OFDM_11AH_2MHZ_PKT_PHY_LTR_DELAY__OFDM_11AH2MHZ_LTR_DELAY___POR 0x0000 +#define WMAC0_PDG_R0_OFDM_11AH_2MHZ_PKT_PHY_LTR_DELAY__OFDM_11AH2MHZ_LTR_DELAY___M 0x0000FFFF +#define WMAC0_PDG_R0_OFDM_11AH_2MHZ_PKT_PHY_LTR_DELAY__OFDM_11AH2MHZ_LTR_DELAY___S 0 +#define WMAC0_PDG_R0_OFDM_11AH_2MHZ_PKT_PHY_LTR_DELAY___M 0x0000FFFF +#define WMAC0_PDG_R0_OFDM_11AH_2MHZ_PKT_PHY_LTR_DELAY___S 0 + +#define WMAC0_PDG_R0_PROTECTION_SIFS (0x00A8004C) +#define WMAC0_PDG_R0_PROTECTION_SIFS___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_PROTECTION_SIFS___POR 0x00000000 +#define WMAC0_PDG_R0_PROTECTION_SIFS__RESP_PATH_SW_SIFS_TIME___POR 0x00 +#define WMAC0_PDG_R0_PROTECTION_SIFS__MPROT_RESP_SW_SIFS_TIME___POR 0x00 +#define WMAC0_PDG_R0_PROTECTION_SIFS__MPROT_SW_SIFS_TIME___POR 0x00 +#define WMAC0_PDG_R0_PROTECTION_SIFS__RESP_PATH_SW_SIFS_TIME___M 0x00FF0000 +#define WMAC0_PDG_R0_PROTECTION_SIFS__RESP_PATH_SW_SIFS_TIME___S 16 +#define WMAC0_PDG_R0_PROTECTION_SIFS__MPROT_RESP_SW_SIFS_TIME___M 0x0000FF00 +#define WMAC0_PDG_R0_PROTECTION_SIFS__MPROT_RESP_SW_SIFS_TIME___S 8 +#define WMAC0_PDG_R0_PROTECTION_SIFS__MPROT_SW_SIFS_TIME___M 0x000000FF +#define WMAC0_PDG_R0_PROTECTION_SIFS__MPROT_SW_SIFS_TIME___S 0 +#define WMAC0_PDG_R0_PROTECTION_SIFS___M 0x00FFFFFF +#define WMAC0_PDG_R0_PROTECTION_SIFS___S 0 + +#define WMAC0_PDG_R0_CAL_CTRL (0x00A80050) +#define WMAC0_PDG_R0_CAL_CTRL___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_CAL_CTRL___POR 0x013F010A +#define WMAC0_PDG_R0_CAL_CTRL__WAIT_TIME_SEL___POR 0x0 +#define WMAC0_PDG_R0_CAL_CTRL__CNT_FOR_USEC___POR 0x13F +#define WMAC0_PDG_R0_CAL_CTRL__PDG_UNKNOWN_LENGTH_OFFSET___POR 0x01 +#define WMAC0_PDG_R0_CAL_CTRL__PDG_MPDU_INFO_WAIT_TIME___POR 0x0A +#define WMAC0_PDG_R0_CAL_CTRL__WAIT_TIME_SEL___M 0x02000000 +#define WMAC0_PDG_R0_CAL_CTRL__WAIT_TIME_SEL___S 25 +#define WMAC0_PDG_R0_CAL_CTRL__CNT_FOR_USEC___M 0x01FF0000 +#define WMAC0_PDG_R0_CAL_CTRL__CNT_FOR_USEC___S 16 +#define WMAC0_PDG_R0_CAL_CTRL__PDG_UNKNOWN_LENGTH_OFFSET___M 0x0000FF00 +#define WMAC0_PDG_R0_CAL_CTRL__PDG_UNKNOWN_LENGTH_OFFSET___S 8 +#define WMAC0_PDG_R0_CAL_CTRL__PDG_MPDU_INFO_WAIT_TIME___M 0x0000003F +#define WMAC0_PDG_R0_CAL_CTRL__PDG_MPDU_INFO_WAIT_TIME___S 0 +#define WMAC0_PDG_R0_CAL_CTRL___M 0x03FFFF3F +#define WMAC0_PDG_R0_CAL_CTRL___S 0 + +#define WMAC0_PDG_R0_DYNAMIC_BW_OVERRIDE (0x00A80054) +#define WMAC0_PDG_R0_DYNAMIC_BW_OVERRIDE___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_DYNAMIC_BW_OVERRIDE___POR 0x00000000 +#define WMAC0_PDG_R0_DYNAMIC_BW_OVERRIDE__OVERRIDE_DURATION_TX_SINGLE_MPDU___POR 0x0 +#define WMAC0_PDG_R0_DYNAMIC_BW_OVERRIDE__OVERRIDE_DURATION_TX_SINGLE_MPDU___M 0x00000001 +#define WMAC0_PDG_R0_DYNAMIC_BW_OVERRIDE__OVERRIDE_DURATION_TX_SINGLE_MPDU___S 0 +#define WMAC0_PDG_R0_DYNAMIC_BW_OVERRIDE___M 0x00000001 +#define WMAC0_PDG_R0_DYNAMIC_BW_OVERRIDE___S 0 + +#define WMAC0_PDG_R0_HE_SIGB_CONFIG_COMMON (0x00A80058) +#define WMAC0_PDG_R0_HE_SIGB_CONFIG_COMMON___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_HE_SIGB_CONFIG_COMMON___POR 0x2B1B1212 +#define WMAC0_PDG_R0_HE_SIGB_CONFIG_COMMON__LENGTH_BW160___POR 0x2B +#define WMAC0_PDG_R0_HE_SIGB_CONFIG_COMMON__LENGTH_BW80___POR 0x1B +#define WMAC0_PDG_R0_HE_SIGB_CONFIG_COMMON__LENGTH_BW40___POR 0x12 +#define WMAC0_PDG_R0_HE_SIGB_CONFIG_COMMON__LENGTH_BW20___POR 0x12 +#define WMAC0_PDG_R0_HE_SIGB_CONFIG_COMMON__LENGTH_BW160___M 0x3F000000 +#define WMAC0_PDG_R0_HE_SIGB_CONFIG_COMMON__LENGTH_BW160___S 24 +#define WMAC0_PDG_R0_HE_SIGB_CONFIG_COMMON__LENGTH_BW80___M 0x003F0000 +#define WMAC0_PDG_R0_HE_SIGB_CONFIG_COMMON__LENGTH_BW80___S 16 +#define WMAC0_PDG_R0_HE_SIGB_CONFIG_COMMON__LENGTH_BW40___M 0x00003F00 +#define WMAC0_PDG_R0_HE_SIGB_CONFIG_COMMON__LENGTH_BW40___S 8 +#define WMAC0_PDG_R0_HE_SIGB_CONFIG_COMMON__LENGTH_BW20___M 0x0000003F +#define WMAC0_PDG_R0_HE_SIGB_CONFIG_COMMON__LENGTH_BW20___S 0 +#define WMAC0_PDG_R0_HE_SIGB_CONFIG_COMMON___M 0x3F3F3F3F +#define WMAC0_PDG_R0_HE_SIGB_CONFIG_COMMON___S 0 + +#define WMAC0_PDG_R0_HE_SIGB_CONFIG_USER (0x00A8005C) +#define WMAC0_PDG_R0_HE_SIGB_CONFIG_USER___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_HE_SIGB_CONFIG_USER___POR 0x00001F34 +#define WMAC0_PDG_R0_HE_SIGB_CONFIG_USER__ODD_USER_LENGTH___POR 0x1F +#define WMAC0_PDG_R0_HE_SIGB_CONFIG_USER__EVEN_USER_LENGTH___POR 0x34 +#define WMAC0_PDG_R0_HE_SIGB_CONFIG_USER__ODD_USER_LENGTH___M 0x00003F00 +#define WMAC0_PDG_R0_HE_SIGB_CONFIG_USER__ODD_USER_LENGTH___S 8 +#define WMAC0_PDG_R0_HE_SIGB_CONFIG_USER__EVEN_USER_LENGTH___M 0x0000003F +#define WMAC0_PDG_R0_HE_SIGB_CONFIG_USER__EVEN_USER_LENGTH___S 0 +#define WMAC0_PDG_R0_HE_SIGB_CONFIG_USER___M 0x00003F3F +#define WMAC0_PDG_R0_HE_SIGB_CONFIG_USER___S 0 + +#define WMAC0_PDG_R0_RESP_MODE_CONFIG (0x00A80060) +#define WMAC0_PDG_R0_RESP_MODE_CONFIG___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_RESP_MODE_CONFIG___POR 0x00000000 +#define WMAC0_PDG_R0_RESP_MODE_CONFIG__MEASURE_POWER___POR 0x0 +#define WMAC0_PDG_R0_RESP_MODE_CONFIG__CLPC_ENABLE___POR 0x0 +#define WMAC0_PDG_R0_RESP_MODE_CONFIG__MEASURE_POWER___M 0x00000002 +#define WMAC0_PDG_R0_RESP_MODE_CONFIG__MEASURE_POWER___S 1 +#define WMAC0_PDG_R0_RESP_MODE_CONFIG__CLPC_ENABLE___M 0x00000001 +#define WMAC0_PDG_R0_RESP_MODE_CONFIG__CLPC_ENABLE___S 0 +#define WMAC0_PDG_R0_RESP_MODE_CONFIG___M 0x00000003 +#define WMAC0_PDG_R0_RESP_MODE_CONFIG___S 0 + +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG (0x00A80064) +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG___POR 0x02100000 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__BEAM_CHANGE___POR 0x0 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__CHAIN_CSD_EN___POR 0x0 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__RESPONSE_EXPECTED___POR 0x1 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__ANT_SEL___POR 0x0 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__ANTEL_SEL_VALID___POR 0x0 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__RX_CHAIN_MASK_VALID___POR 0x1 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__CLPC_ENABLE___POR 0x0 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__TPC_GLUT_SELF_CAL___POR 0x0 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__MEASURE_POWER___POR 0x0 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__DPD_ENABLE___POR 0x0 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__PAPRD_CHAIN_MASK___POR 0x00 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__TX_CHAIN_MASK___POR 0x00 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__BEAM_CHANGE___M 0x08000000 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__BEAM_CHANGE___S 27 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__CHAIN_CSD_EN___M 0x04000000 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__CHAIN_CSD_EN___S 26 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__RESPONSE_EXPECTED___M 0x02000000 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__RESPONSE_EXPECTED___S 25 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__ANT_SEL___M 0x00400000 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__ANT_SEL___S 22 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__ANTEL_SEL_VALID___M 0x00200000 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__ANTEL_SEL_VALID___S 21 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__RX_CHAIN_MASK_VALID___M 0x00100000 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__RX_CHAIN_MASK_VALID___S 20 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__CLPC_ENABLE___M 0x00080000 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__CLPC_ENABLE___S 19 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__TPC_GLUT_SELF_CAL___M 0x00040000 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__TPC_GLUT_SELF_CAL___S 18 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__MEASURE_POWER___M 0x00020000 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__MEASURE_POWER___S 17 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__DPD_ENABLE___M 0x00010000 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__DPD_ENABLE___S 16 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__PAPRD_CHAIN_MASK___M 0x0000FF00 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__PAPRD_CHAIN_MASK___S 8 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__TX_CHAIN_MASK___M 0x000000FF +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG__TX_CHAIN_MASK___S 0 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG___M 0x0E7FFFFF +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG___S 0 + +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG1 (0x00A80068) +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG1___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG1___POR 0x00000001 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG1__TX_CHAIN_MASK_CTS___POR 0x00 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG1__RX_CHAIN_MASK___POR 0x01 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG1__TX_CHAIN_MASK_CTS___M 0x0000FF00 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG1__TX_CHAIN_MASK_CTS___S 8 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG1__RX_CHAIN_MASK___M 0x000000FF +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG1__RX_CHAIN_MASK___S 0 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG1___M 0x0000FFFF +#define WMAC0_PDG_R0_OFDMA_TRIGGER_CONFIG1___S 0 + +#define WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA1 (0x00A8006C) +#define WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA1___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA1___POR 0x00000000 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA1__VALID___POR 0x0 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA1__BSS_COLOR_ID___POR 0x00 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA1__TX_ANTENNA_SECTOR_CTRL___POR 0x000000 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA1__VALID___M 0x40000000 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA1__VALID___S 30 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA1__BSS_COLOR_ID___M 0x3F000000 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA1__BSS_COLOR_ID___S 24 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA1__TX_ANTENNA_SECTOR_CTRL___M 0x00FFFFFF +#define WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA1__TX_ANTENNA_SECTOR_CTRL___S 0 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA1___M 0x7FFFFFFF +#define WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA1___S 0 + +#define WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA2 (0x00A80070) +#define WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA2___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA2___POR 0x00000000 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA2__VALID___POR 0x0 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA2__BSS_COLOR_ID___POR 0x00 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA2__TX_ANTENNA_SECTOR_CTRL___POR 0x000000 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA2__VALID___M 0x40000000 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA2__VALID___S 30 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA2__BSS_COLOR_ID___M 0x3F000000 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA2__BSS_COLOR_ID___S 24 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA2__TX_ANTENNA_SECTOR_CTRL___M 0x00FFFFFF +#define WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA2__TX_ANTENNA_SECTOR_CTRL___S 0 +#define WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA2___M 0x7FFFFFFF +#define WMAC0_PDG_R0_OFDMA_TRIGGER_TX_ANTENNA2___S 0 + +#define WMAC0_PDG_R0_HE_CONFIG (0x00A80074) +#define WMAC0_PDG_R0_HE_CONFIG___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_HE_CONFIG___POR 0x000C01FF +#define WMAC0_PDG_R0_HE_CONFIG__BEAM_CHANGE_EXT___POR 0x1 +#define WMAC0_PDG_R0_HE_CONFIG__BEAM_CHANGE___POR 0x1 +#define WMAC0_PDG_R0_HE_CONFIG__TXOP_DURATION_SWAP___POR 0x0 +#define WMAC0_PDG_R0_HE_CONFIG__MAX_MCS_FOR_DCM___POR 0x0 +#define WMAC0_PDG_R0_HE_CONFIG__STF_DURATION_HE_MU_DL___POR 0x0 +#define WMAC0_PDG_R0_HE_CONFIG__STF_DURATION_HE_SU_EXT___POR 0x0 +#define WMAC0_PDG_R0_HE_CONFIG__STF_DURATION_HE_SU___POR 0x0 +#define WMAC0_PDG_R0_HE_CONFIG__SPATIAL_CONFIG_ORDER___POR 0x0 +#define WMAC0_PDG_R0_HE_CONFIG__TXOP_SEL_TRIG_RESP___POR 0x1 +#define WMAC0_PDG_R0_HE_CONFIG__TXOP_SEL___POR 0x1 +#define WMAC0_PDG_R0_HE_CONFIG__TXOP_UNUSED_VALUE___POR 0x7F +#define WMAC0_PDG_R0_HE_CONFIG__BEAM_CHANGE_EXT___M 0x00080000 +#define WMAC0_PDG_R0_HE_CONFIG__BEAM_CHANGE_EXT___S 19 +#define WMAC0_PDG_R0_HE_CONFIG__BEAM_CHANGE___M 0x00040000 +#define WMAC0_PDG_R0_HE_CONFIG__BEAM_CHANGE___S 18 +#define WMAC0_PDG_R0_HE_CONFIG__TXOP_DURATION_SWAP___M 0x00020000 +#define WMAC0_PDG_R0_HE_CONFIG__TXOP_DURATION_SWAP___S 17 +#define WMAC0_PDG_R0_HE_CONFIG__MAX_MCS_FOR_DCM___M 0x0001E000 +#define WMAC0_PDG_R0_HE_CONFIG__MAX_MCS_FOR_DCM___S 13 +#define WMAC0_PDG_R0_HE_CONFIG__STF_DURATION_HE_MU_DL___M 0x00001000 +#define WMAC0_PDG_R0_HE_CONFIG__STF_DURATION_HE_MU_DL___S 12 +#define WMAC0_PDG_R0_HE_CONFIG__STF_DURATION_HE_SU_EXT___M 0x00000800 +#define WMAC0_PDG_R0_HE_CONFIG__STF_DURATION_HE_SU_EXT___S 11 +#define WMAC0_PDG_R0_HE_CONFIG__STF_DURATION_HE_SU___M 0x00000400 +#define WMAC0_PDG_R0_HE_CONFIG__STF_DURATION_HE_SU___S 10 +#define WMAC0_PDG_R0_HE_CONFIG__SPATIAL_CONFIG_ORDER___M 0x00000200 +#define WMAC0_PDG_R0_HE_CONFIG__SPATIAL_CONFIG_ORDER___S 9 +#define WMAC0_PDG_R0_HE_CONFIG__TXOP_SEL_TRIG_RESP___M 0x00000100 +#define WMAC0_PDG_R0_HE_CONFIG__TXOP_SEL_TRIG_RESP___S 8 +#define WMAC0_PDG_R0_HE_CONFIG__TXOP_SEL___M 0x00000080 +#define WMAC0_PDG_R0_HE_CONFIG__TXOP_SEL___S 7 +#define WMAC0_PDG_R0_HE_CONFIG__TXOP_UNUSED_VALUE___M 0x0000007F +#define WMAC0_PDG_R0_HE_CONFIG__TXOP_UNUSED_VALUE___S 0 +#define WMAC0_PDG_R0_HE_CONFIG___M 0x000FFFFF +#define WMAC0_PDG_R0_HE_CONFIG___S 0 + +#define WMAC0_PDG_R0_HE_A_CONTROL_CONFIG (0x00A80078) +#define WMAC0_PDG_R0_HE_A_CONTROL_CONFIG___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_HE_A_CONTROL_CONFIG___POR 0x00000000 +#define WMAC0_PDG_R0_HE_A_CONTROL_CONFIG__RESERVE_FIELD___POR 0x000 +#define WMAC0_PDG_R0_HE_A_CONTROL_CONFIG__DOPPLER___POR 0x0 +#define WMAC0_PDG_R0_HE_A_CONTROL_CONFIG__PACKET_EXTENSION___POR 0x0 +#define WMAC0_PDG_R0_HE_A_CONTROL_CONFIG__SPATIAL_REUSE___POR 0x0000 +#define WMAC0_PDG_R0_HE_A_CONTROL_CONFIG__RESERVE_FIELD___M 0x1FF00000 +#define WMAC0_PDG_R0_HE_A_CONTROL_CONFIG__RESERVE_FIELD___S 20 +#define WMAC0_PDG_R0_HE_A_CONTROL_CONFIG__DOPPLER___M 0x00080000 +#define WMAC0_PDG_R0_HE_A_CONTROL_CONFIG__DOPPLER___S 19 +#define WMAC0_PDG_R0_HE_A_CONTROL_CONFIG__PACKET_EXTENSION___M 0x00070000 +#define WMAC0_PDG_R0_HE_A_CONTROL_CONFIG__PACKET_EXTENSION___S 16 +#define WMAC0_PDG_R0_HE_A_CONTROL_CONFIG__SPATIAL_REUSE___M 0x0000FFFF +#define WMAC0_PDG_R0_HE_A_CONTROL_CONFIG__SPATIAL_REUSE___S 0 +#define WMAC0_PDG_R0_HE_A_CONTROL_CONFIG___M 0x1FFFFFFF +#define WMAC0_PDG_R0_HE_A_CONTROL_CONFIG___S 0 + +#define WMAC0_PDG_R0_UPC_CONFIG (0x00A8007C) +#define WMAC0_PDG_R0_UPC_CONFIG___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_UPC_CONFIG___POR 0x00003F36 +#define WMAC0_PDG_R0_UPC_CONFIG__TRIGGER_CTS_TX_PWR___POR 0x00 +#define WMAC0_PDG_R0_UPC_CONFIG__DELTA_BW_EN___POR 0x0 +#define WMAC0_PDG_R0_UPC_CONFIG__NOISE_FLOOR_BIAS___POR 0x00 +#define WMAC0_PDG_R0_UPC_CONFIG__HEADROOM_REPORT_OPTION___POR 0x0 +#define WMAC0_PDG_R0_UPC_CONFIG__RSSI_COMB_RESOLUTION___POR 0x0 +#define WMAC0_PDG_R0_UPC_CONFIG__TPC_COMP_FACTOR___POR 0x1F +#define WMAC0_PDG_R0_UPC_CONFIG__NOISE_FLOOR___POR 0x136 +#define WMAC0_PDG_R0_UPC_CONFIG__TRIGGER_CTS_TX_PWR___M 0xFF000000 +#define WMAC0_PDG_R0_UPC_CONFIG__TRIGGER_CTS_TX_PWR___S 24 +#define WMAC0_PDG_R0_UPC_CONFIG__DELTA_BW_EN___M 0x00800000 +#define WMAC0_PDG_R0_UPC_CONFIG__DELTA_BW_EN___S 23 +#define WMAC0_PDG_R0_UPC_CONFIG__NOISE_FLOOR_BIAS___M 0x007F0000 +#define WMAC0_PDG_R0_UPC_CONFIG__NOISE_FLOOR_BIAS___S 16 +#define WMAC0_PDG_R0_UPC_CONFIG__HEADROOM_REPORT_OPTION___M 0x00008000 +#define WMAC0_PDG_R0_UPC_CONFIG__HEADROOM_REPORT_OPTION___S 15 +#define WMAC0_PDG_R0_UPC_CONFIG__RSSI_COMB_RESOLUTION___M 0x00004000 +#define WMAC0_PDG_R0_UPC_CONFIG__RSSI_COMB_RESOLUTION___S 14 +#define WMAC0_PDG_R0_UPC_CONFIG__TPC_COMP_FACTOR___M 0x00003E00 +#define WMAC0_PDG_R0_UPC_CONFIG__TPC_COMP_FACTOR___S 9 +#define WMAC0_PDG_R0_UPC_CONFIG__NOISE_FLOOR___M 0x000001FF +#define WMAC0_PDG_R0_UPC_CONFIG__NOISE_FLOOR___S 0 +#define WMAC0_PDG_R0_UPC_CONFIG___M 0xFFFFFFFF +#define WMAC0_PDG_R0_UPC_CONFIG___S 0 + +#define WMAC0_PDG_R0_UPC_CONFIG2 (0x00A80080) +#define WMAC0_PDG_R0_UPC_CONFIG2___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_UPC_CONFIG2___POR 0x00000000 +#define WMAC0_PDG_R0_UPC_CONFIG2__TPC_OFFSET___POR 0x00 +#define WMAC0_PDG_R0_UPC_CONFIG2__LISTEN_RX_CHAIN_MASK___POR 0x00 +#define WMAC0_PDG_R0_UPC_CONFIG2__TPC_OFFSET___M 0x0000FF00 +#define WMAC0_PDG_R0_UPC_CONFIG2__TPC_OFFSET___S 8 +#define WMAC0_PDG_R0_UPC_CONFIG2__LISTEN_RX_CHAIN_MASK___M 0x000000FF +#define WMAC0_PDG_R0_UPC_CONFIG2__LISTEN_RX_CHAIN_MASK___S 0 +#define WMAC0_PDG_R0_UPC_CONFIG2___M 0x0000FFFF +#define WMAC0_PDG_R0_UPC_CONFIG2___S 0 + +#define WMAC0_PDG_R0_UPC_OVERRIDE (0x00A80084) +#define WMAC0_PDG_R0_UPC_OVERRIDE___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_UPC_OVERRIDE___POR 0x00000000 +#define WMAC0_PDG_R0_UPC_OVERRIDE__HEADROOM_SW_ENABLE___POR 0x0 +#define WMAC0_PDG_R0_UPC_OVERRIDE__HEADROOM___POR 0x00 +#define WMAC0_PDG_R0_UPC_OVERRIDE__TX_PWR_SHARED_SW_ENABLE___POR 0x0 +#define WMAC0_PDG_R0_UPC_OVERRIDE__TX_PWR_SHARED___POR 0x00 +#define WMAC0_PDG_R0_UPC_OVERRIDE__HEADROOM_SW_ENABLE___M 0x00008000 +#define WMAC0_PDG_R0_UPC_OVERRIDE__HEADROOM_SW_ENABLE___S 15 +#define WMAC0_PDG_R0_UPC_OVERRIDE__HEADROOM___M 0x00007E00 +#define WMAC0_PDG_R0_UPC_OVERRIDE__HEADROOM___S 9 +#define WMAC0_PDG_R0_UPC_OVERRIDE__TX_PWR_SHARED_SW_ENABLE___M 0x00000100 +#define WMAC0_PDG_R0_UPC_OVERRIDE__TX_PWR_SHARED_SW_ENABLE___S 8 +#define WMAC0_PDG_R0_UPC_OVERRIDE__TX_PWR_SHARED___M 0x000000FF +#define WMAC0_PDG_R0_UPC_OVERRIDE__TX_PWR_SHARED___S 0 +#define WMAC0_PDG_R0_UPC_OVERRIDE___M 0x0000FFFF +#define WMAC0_PDG_R0_UPC_OVERRIDE___S 0 + +#define WMAC0_PDG_R0_UPC_STATUS (0x00A80088) +#define WMAC0_PDG_R0_UPC_STATUS___RWC QCSR_REG_RO +#define WMAC0_PDG_R0_UPC_STATUS___POR 0x00000000 +#define WMAC0_PDG_R0_UPC_STATUS__REQ_UL_TXPWR___POR 0x00 +#define WMAC0_PDG_R0_UPC_STATUS__NRX___POR 0x0 +#define WMAC0_PDG_R0_UPC_STATUS__RSSI_COMB___POR 0x00 +#define WMAC0_PDG_R0_UPC_STATUS__AP_TXPWR___POR 0x00 +#define WMAC0_PDG_R0_UPC_STATUS__MIN_TX_PWR_REACHED___POR 0x0 +#define WMAC0_PDG_R0_UPC_STATUS__HEADROOM___POR 0x00 +#define WMAC0_PDG_R0_UPC_STATUS__REQ_UL_TXPWR___M 0xFF000000 +#define WMAC0_PDG_R0_UPC_STATUS__REQ_UL_TXPWR___S 24 +#define WMAC0_PDG_R0_UPC_STATUS__NRX___M 0x00F00000 +#define WMAC0_PDG_R0_UPC_STATUS__NRX___S 20 +#define WMAC0_PDG_R0_UPC_STATUS__RSSI_COMB___M 0x000FF000 +#define WMAC0_PDG_R0_UPC_STATUS__RSSI_COMB___S 12 +#define WMAC0_PDG_R0_UPC_STATUS__AP_TXPWR___M 0x00000FC0 +#define WMAC0_PDG_R0_UPC_STATUS__AP_TXPWR___S 6 +#define WMAC0_PDG_R0_UPC_STATUS__MIN_TX_PWR_REACHED___M 0x00000020 +#define WMAC0_PDG_R0_UPC_STATUS__MIN_TX_PWR_REACHED___S 5 +#define WMAC0_PDG_R0_UPC_STATUS__HEADROOM___M 0x0000001F +#define WMAC0_PDG_R0_UPC_STATUS__HEADROOM___S 0 +#define WMAC0_PDG_R0_UPC_STATUS___M 0xFFFFFFFF +#define WMAC0_PDG_R0_UPC_STATUS___S 0 + +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS0 (0x00A8008C) +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS0___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS0___POR 0x00000000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS0__PMAX_FULL_BW___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS0__PMAX_4RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS0__PMAX_2RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS0__PMAX_1RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS0__PMAX_FULL_BW___M 0xFF000000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS0__PMAX_FULL_BW___S 24 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS0__PMAX_4RU___M 0x00FF0000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS0__PMAX_4RU___S 16 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS0__PMAX_2RU___M 0x0000FF00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS0__PMAX_2RU___S 8 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS0__PMAX_1RU___M 0x000000FF +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS0__PMAX_1RU___S 0 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS0___M 0xFFFFFFFF +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS0___S 0 + +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS1 (0x00A80090) +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS1___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS1___POR 0x00000000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS1__PMAX_FULL_BW___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS1__PMAX_4RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS1__PMAX_2RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS1__PMAX_1RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS1__PMAX_FULL_BW___M 0xFF000000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS1__PMAX_FULL_BW___S 24 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS1__PMAX_4RU___M 0x00FF0000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS1__PMAX_4RU___S 16 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS1__PMAX_2RU___M 0x0000FF00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS1__PMAX_2RU___S 8 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS1__PMAX_1RU___M 0x000000FF +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS1__PMAX_1RU___S 0 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS1___M 0xFFFFFFFF +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS1___S 0 + +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS2 (0x00A80094) +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS2___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS2___POR 0x00000000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS2__PMAX_FULL_BW___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS2__PMAX_4RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS2__PMAX_2RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS2__PMAX_1RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS2__PMAX_FULL_BW___M 0xFF000000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS2__PMAX_FULL_BW___S 24 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS2__PMAX_4RU___M 0x00FF0000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS2__PMAX_4RU___S 16 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS2__PMAX_2RU___M 0x0000FF00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS2__PMAX_2RU___S 8 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS2__PMAX_1RU___M 0x000000FF +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS2__PMAX_1RU___S 0 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS2___M 0xFFFFFFFF +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS2___S 0 + +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS3 (0x00A80098) +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS3___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS3___POR 0x00000000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS3__PMAX_FULL_BW___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS3__PMAX_4RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS3__PMAX_2RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS3__PMAX_1RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS3__PMAX_FULL_BW___M 0xFF000000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS3__PMAX_FULL_BW___S 24 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS3__PMAX_4RU___M 0x00FF0000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS3__PMAX_4RU___S 16 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS3__PMAX_2RU___M 0x0000FF00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS3__PMAX_2RU___S 8 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS3__PMAX_1RU___M 0x000000FF +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS3__PMAX_1RU___S 0 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS3___M 0xFFFFFFFF +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS3___S 0 + +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS4 (0x00A8009C) +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS4___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS4___POR 0x00000000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS4__PMAX_FULL_BW___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS4__PMAX_4RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS4__PMAX_2RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS4__PMAX_1RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS4__PMAX_FULL_BW___M 0xFF000000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS4__PMAX_FULL_BW___S 24 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS4__PMAX_4RU___M 0x00FF0000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS4__PMAX_4RU___S 16 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS4__PMAX_2RU___M 0x0000FF00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS4__PMAX_2RU___S 8 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS4__PMAX_1RU___M 0x000000FF +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS4__PMAX_1RU___S 0 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS4___M 0xFFFFFFFF +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS4___S 0 + +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS5 (0x00A800A0) +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS5___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS5___POR 0x00000000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS5__PMAX_FULL_BW___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS5__PMAX_4RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS5__PMAX_2RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS5__PMAX_1RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS5__PMAX_FULL_BW___M 0xFF000000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS5__PMAX_FULL_BW___S 24 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS5__PMAX_4RU___M 0x00FF0000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS5__PMAX_4RU___S 16 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS5__PMAX_2RU___M 0x0000FF00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS5__PMAX_2RU___S 8 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS5__PMAX_1RU___M 0x000000FF +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS5__PMAX_1RU___S 0 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS5___M 0xFFFFFFFF +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS5___S 0 + +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS6 (0x00A800A4) +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS6___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS6___POR 0x00000000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS6__PMAX_FULL_BW___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS6__PMAX_4RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS6__PMAX_2RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS6__PMAX_1RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS6__PMAX_FULL_BW___M 0xFF000000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS6__PMAX_FULL_BW___S 24 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS6__PMAX_4RU___M 0x00FF0000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS6__PMAX_4RU___S 16 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS6__PMAX_2RU___M 0x0000FF00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS6__PMAX_2RU___S 8 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS6__PMAX_1RU___M 0x000000FF +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS6__PMAX_1RU___S 0 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS6___M 0xFFFFFFFF +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS6___S 0 + +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS7 (0x00A800A8) +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS7___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS7___POR 0x00000000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS7__PMAX_FULL_BW___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS7__PMAX_4RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS7__PMAX_2RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS7__PMAX_1RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS7__PMAX_FULL_BW___M 0xFF000000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS7__PMAX_FULL_BW___S 24 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS7__PMAX_4RU___M 0x00FF0000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS7__PMAX_4RU___S 16 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS7__PMAX_2RU___M 0x0000FF00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS7__PMAX_2RU___S 8 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS7__PMAX_1RU___M 0x000000FF +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS7__PMAX_1RU___S 0 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS7___M 0xFFFFFFFF +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS7___S 0 + +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS8 (0x00A800AC) +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS8___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS8___POR 0x00000000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS8__PMAX_FULL_BW___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS8__PMAX_4RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS8__PMAX_2RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS8__PMAX_1RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS8__PMAX_FULL_BW___M 0xFF000000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS8__PMAX_FULL_BW___S 24 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS8__PMAX_4RU___M 0x00FF0000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS8__PMAX_4RU___S 16 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS8__PMAX_2RU___M 0x0000FF00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS8__PMAX_2RU___S 8 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS8__PMAX_1RU___M 0x000000FF +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS8__PMAX_1RU___S 0 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS8___M 0xFFFFFFFF +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS8___S 0 + +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS9 (0x00A800B0) +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS9___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS9___POR 0x00000000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS9__PMAX_FULL_BW___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS9__PMAX_4RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS9__PMAX_2RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS9__PMAX_1RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS9__PMAX_FULL_BW___M 0xFF000000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS9__PMAX_FULL_BW___S 24 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS9__PMAX_4RU___M 0x00FF0000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS9__PMAX_4RU___S 16 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS9__PMAX_2RU___M 0x0000FF00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS9__PMAX_2RU___S 8 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS9__PMAX_1RU___M 0x000000FF +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS9__PMAX_1RU___S 0 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS9___M 0xFFFFFFFF +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS9___S 0 + +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS10 (0x00A800B4) +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS10___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS10___POR 0x00000000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS10__PMAX_FULL_BW___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS10__PMAX_4RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS10__PMAX_2RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS10__PMAX_1RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS10__PMAX_FULL_BW___M 0xFF000000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS10__PMAX_FULL_BW___S 24 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS10__PMAX_4RU___M 0x00FF0000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS10__PMAX_4RU___S 16 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS10__PMAX_2RU___M 0x0000FF00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS10__PMAX_2RU___S 8 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS10__PMAX_1RU___M 0x000000FF +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS10__PMAX_1RU___S 0 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS10___M 0xFFFFFFFF +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS10___S 0 + +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS11 (0x00A800B8) +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS11___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS11___POR 0x00000000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS11__PMAX_FULL_BW___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS11__PMAX_4RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS11__PMAX_2RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS11__PMAX_1RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS11__PMAX_FULL_BW___M 0xFF000000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS11__PMAX_FULL_BW___S 24 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS11__PMAX_4RU___M 0x00FF0000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS11__PMAX_4RU___S 16 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS11__PMAX_2RU___M 0x0000FF00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS11__PMAX_2RU___S 8 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS11__PMAX_1RU___M 0x000000FF +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS11__PMAX_1RU___S 0 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS11___M 0xFFFFFFFF +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS11___S 0 + +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS12 (0x00A800BC) +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS12___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS12___POR 0x00000000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS12__PMAX_FULL_BW___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS12__PMAX_4RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS12__PMAX_2RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS12__PMAX_1RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS12__PMAX_FULL_BW___M 0xFF000000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS12__PMAX_FULL_BW___S 24 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS12__PMAX_4RU___M 0x00FF0000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS12__PMAX_4RU___S 16 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS12__PMAX_2RU___M 0x0000FF00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS12__PMAX_2RU___S 8 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS12__PMAX_1RU___M 0x000000FF +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS12__PMAX_1RU___S 0 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS12___M 0xFFFFFFFF +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS12___S 0 + +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS13 (0x00A800C0) +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS13___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS13___POR 0x00000000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS13__PMAX_FULL_BW___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS13__PMAX_4RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS13__PMAX_2RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS13__PMAX_1RU___POR 0x00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS13__PMAX_FULL_BW___M 0xFF000000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS13__PMAX_FULL_BW___S 24 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS13__PMAX_4RU___M 0x00FF0000 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS13__PMAX_4RU___S 16 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS13__PMAX_2RU___M 0x0000FF00 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS13__PMAX_2RU___S 8 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS13__PMAX_1RU___M 0x000000FF +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS13__PMAX_1RU___S 0 +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS13___M 0xFFFFFFFF +#define WMAC0_PDG_R0_UPC_MAX_PWR_MCS13___S 0 + +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS0_3 (0x00A800C4) +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS0_3___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS0_3___POR 0x00000000 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS0_3__PMIN_MCS3___POR 0x00 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS0_3__PMIN_MCS2___POR 0x00 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS0_3__PMIN_MCS1___POR 0x00 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS0_3__PMIN_MCS0___POR 0x00 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS0_3__PMIN_MCS3___M 0xFF000000 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS0_3__PMIN_MCS3___S 24 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS0_3__PMIN_MCS2___M 0x00FF0000 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS0_3__PMIN_MCS2___S 16 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS0_3__PMIN_MCS1___M 0x0000FF00 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS0_3__PMIN_MCS1___S 8 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS0_3__PMIN_MCS0___M 0x000000FF +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS0_3__PMIN_MCS0___S 0 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS0_3___M 0xFFFFFFFF +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS0_3___S 0 + +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS4_7 (0x00A800C8) +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS4_7___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS4_7___POR 0x00000000 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS4_7__PMIN_MCS7___POR 0x00 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS4_7__PMIN_MCS6___POR 0x00 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS4_7__PMIN_MCS5___POR 0x00 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS4_7__PMIN_MCS4___POR 0x00 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS4_7__PMIN_MCS7___M 0xFF000000 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS4_7__PMIN_MCS7___S 24 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS4_7__PMIN_MCS6___M 0x00FF0000 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS4_7__PMIN_MCS6___S 16 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS4_7__PMIN_MCS5___M 0x0000FF00 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS4_7__PMIN_MCS5___S 8 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS4_7__PMIN_MCS4___M 0x000000FF +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS4_7__PMIN_MCS4___S 0 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS4_7___M 0xFFFFFFFF +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS4_7___S 0 + +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS8_11 (0x00A800CC) +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS8_11___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS8_11___POR 0x00000000 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS8_11__PMIN_MCS11___POR 0x00 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS8_11__PMIN_MCS10___POR 0x00 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS8_11__PMIN_MCS9___POR 0x00 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS8_11__PMIN_MCS8___POR 0x00 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS8_11__PMIN_MCS11___M 0xFF000000 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS8_11__PMIN_MCS11___S 24 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS8_11__PMIN_MCS10___M 0x00FF0000 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS8_11__PMIN_MCS10___S 16 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS8_11__PMIN_MCS9___M 0x0000FF00 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS8_11__PMIN_MCS9___S 8 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS8_11__PMIN_MCS8___M 0x000000FF +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS8_11__PMIN_MCS8___S 0 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS8_11___M 0xFFFFFFFF +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS8_11___S 0 + +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS12_13 (0x00A800D0) +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS12_13___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS12_13___POR 0x00000000 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS12_13__PMIN_MCS13___POR 0x00 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS12_13__PMIN_MCS12___POR 0x00 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS12_13__PMIN_MCS13___M 0x0000FF00 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS12_13__PMIN_MCS13___S 8 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS12_13__PMIN_MCS12___M 0x000000FF +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS12_13__PMIN_MCS12___S 0 +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS12_13___M 0x0000FFFF +#define WMAC0_PDG_R0_UPC_MIN_PWR_MCS12_13___S 0 + +#define WMAC0_PDG_R0_REGULATORY_PMAX (0x00A800D4) +#define WMAC0_PDG_R0_REGULATORY_PMAX___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_REGULATORY_PMAX___POR 0x00000000 +#define WMAC0_PDG_R0_REGULATORY_PMAX__PSDMAX___POR 0x00 +#define WMAC0_PDG_R0_REGULATORY_PMAX__POUTMAX___POR 0x00 +#define WMAC0_PDG_R0_REGULATORY_PMAX__PSDMAX___M 0x0000FF00 +#define WMAC0_PDG_R0_REGULATORY_PMAX__PSDMAX___S 8 +#define WMAC0_PDG_R0_REGULATORY_PMAX__POUTMAX___M 0x000000FF +#define WMAC0_PDG_R0_REGULATORY_PMAX__POUTMAX___S 0 +#define WMAC0_PDG_R0_REGULATORY_PMAX___M 0x0000FFFF +#define WMAC0_PDG_R0_REGULATORY_PMAX___S 0 + +#define WMAC0_PDG_R0_SPATIAL_REUSE (0x00A800D8) +#define WMAC0_PDG_R0_SPATIAL_REUSE___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_SPATIAL_REUSE___POR 0x02220000 +#define WMAC0_PDG_R0_SPATIAL_REUSE__OBSS_2TX_TRIG_RESP_DISABLE___POR 0x0 +#define WMAC0_PDG_R0_SPATIAL_REUSE__ENABLE_FLUSH_CHECK_TRIG_NO_CS___POR 0x0 +#define WMAC0_PDG_R0_SPATIAL_REUSE__RX_RCVD_TO_TX_START_DELAY___POR 0x4 +#define WMAC0_PDG_R0_SPATIAL_REUSE__BO_BASED_PRE_START_TO_TX_DELAY___POR 0x4 +#define WMAC0_PDG_R0_SPATIAL_REUSE__SRP_TRIG_RESP_DISABLE___POR 0x0 +#define WMAC0_PDG_R0_SPATIAL_REUSE__SRP_LEGACY_RESP_DISABLE___POR 0x1 +#define WMAC0_PDG_R0_SPATIAL_REUSE__IGNORE_SRP_DISABLE___POR 0x0 +#define WMAC0_PDG_R0_SPATIAL_REUSE__MARGIN2___POR 0x00 +#define WMAC0_PDG_R0_SPATIAL_REUSE__MARGIN___POR 0x00 +#define WMAC0_PDG_R0_SPATIAL_REUSE__OBSS_2TX_TRIG_RESP_DISABLE___M 0x10000000 +#define WMAC0_PDG_R0_SPATIAL_REUSE__OBSS_2TX_TRIG_RESP_DISABLE___S 28 +#define WMAC0_PDG_R0_SPATIAL_REUSE__ENABLE_FLUSH_CHECK_TRIG_NO_CS___M 0x08000000 +#define WMAC0_PDG_R0_SPATIAL_REUSE__ENABLE_FLUSH_CHECK_TRIG_NO_CS___S 27 +#define WMAC0_PDG_R0_SPATIAL_REUSE__RX_RCVD_TO_TX_START_DELAY___M 0x07800000 +#define WMAC0_PDG_R0_SPATIAL_REUSE__RX_RCVD_TO_TX_START_DELAY___S 23 +#define WMAC0_PDG_R0_SPATIAL_REUSE__BO_BASED_PRE_START_TO_TX_DELAY___M 0x00780000 +#define WMAC0_PDG_R0_SPATIAL_REUSE__BO_BASED_PRE_START_TO_TX_DELAY___S 19 +#define WMAC0_PDG_R0_SPATIAL_REUSE__SRP_TRIG_RESP_DISABLE___M 0x00040000 +#define WMAC0_PDG_R0_SPATIAL_REUSE__SRP_TRIG_RESP_DISABLE___S 18 +#define WMAC0_PDG_R0_SPATIAL_REUSE__SRP_LEGACY_RESP_DISABLE___M 0x00020000 +#define WMAC0_PDG_R0_SPATIAL_REUSE__SRP_LEGACY_RESP_DISABLE___S 17 +#define WMAC0_PDG_R0_SPATIAL_REUSE__IGNORE_SRP_DISABLE___M 0x00010000 +#define WMAC0_PDG_R0_SPATIAL_REUSE__IGNORE_SRP_DISABLE___S 16 +#define WMAC0_PDG_R0_SPATIAL_REUSE__MARGIN2___M 0x0000FF00 +#define WMAC0_PDG_R0_SPATIAL_REUSE__MARGIN2___S 8 +#define WMAC0_PDG_R0_SPATIAL_REUSE__MARGIN___M 0x000000FF +#define WMAC0_PDG_R0_SPATIAL_REUSE__MARGIN___S 0 +#define WMAC0_PDG_R0_SPATIAL_REUSE___M 0x1FFFFFFF +#define WMAC0_PDG_R0_SPATIAL_REUSE___S 0 + +#define WMAC0_PDG_R0_UPC_SR (0x00A800DC) +#define WMAC0_PDG_R0_UPC_SR___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_UPC_SR___POR 0x0000007F +#define WMAC0_PDG_R0_UPC_SR__OBSS_PD_THRESHOLD___POR 0x7F +#define WMAC0_PDG_R0_UPC_SR__OBSS_PD_THRESHOLD___M 0x000000FF +#define WMAC0_PDG_R0_UPC_SR__OBSS_PD_THRESHOLD___S 0 +#define WMAC0_PDG_R0_UPC_SR___M 0x000000FF +#define WMAC0_PDG_R0_UPC_SR___S 0 + +#define WMAC0_PDG_R0_UPC_SR_PBASE0 (0x00A800E0) +#define WMAC0_PDG_R0_UPC_SR_PBASE0___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_UPC_SR_PBASE0___POR 0x7F7F7F7F +#define WMAC0_PDG_R0_UPC_SR_PBASE0__RU242___POR 0x7F +#define WMAC0_PDG_R0_UPC_SR_PBASE0__RU106___POR 0x7F +#define WMAC0_PDG_R0_UPC_SR_PBASE0__RU52___POR 0x7F +#define WMAC0_PDG_R0_UPC_SR_PBASE0__RU26___POR 0x7F +#define WMAC0_PDG_R0_UPC_SR_PBASE0__RU242___M 0xFF000000 +#define WMAC0_PDG_R0_UPC_SR_PBASE0__RU242___S 24 +#define WMAC0_PDG_R0_UPC_SR_PBASE0__RU106___M 0x00FF0000 +#define WMAC0_PDG_R0_UPC_SR_PBASE0__RU106___S 16 +#define WMAC0_PDG_R0_UPC_SR_PBASE0__RU52___M 0x0000FF00 +#define WMAC0_PDG_R0_UPC_SR_PBASE0__RU52___S 8 +#define WMAC0_PDG_R0_UPC_SR_PBASE0__RU26___M 0x000000FF +#define WMAC0_PDG_R0_UPC_SR_PBASE0__RU26___S 0 +#define WMAC0_PDG_R0_UPC_SR_PBASE0___M 0xFFFFFFFF +#define WMAC0_PDG_R0_UPC_SR_PBASE0___S 0 + +#define WMAC0_PDG_R0_UPC_SR_PBASE1 (0x00A800E4) +#define WMAC0_PDG_R0_UPC_SR_PBASE1___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_UPC_SR_PBASE1___POR 0x007F7F7F +#define WMAC0_PDG_R0_UPC_SR_PBASE1__RU2X996___POR 0x7F +#define WMAC0_PDG_R0_UPC_SR_PBASE1__RU996___POR 0x7F +#define WMAC0_PDG_R0_UPC_SR_PBASE1__RU484___POR 0x7F +#define WMAC0_PDG_R0_UPC_SR_PBASE1__RU2X996___M 0x00FF0000 +#define WMAC0_PDG_R0_UPC_SR_PBASE1__RU2X996___S 16 +#define WMAC0_PDG_R0_UPC_SR_PBASE1__RU996___M 0x0000FF00 +#define WMAC0_PDG_R0_UPC_SR_PBASE1__RU996___S 8 +#define WMAC0_PDG_R0_UPC_SR_PBASE1__RU484___M 0x000000FF +#define WMAC0_PDG_R0_UPC_SR_PBASE1__RU484___S 0 +#define WMAC0_PDG_R0_UPC_SR_PBASE1___M 0x00FFFFFF +#define WMAC0_PDG_R0_UPC_SR_PBASE1___S 0 + +#define WMAC0_PDG_R0_HW_RU_MAX_UNUSED_RU (0x00A800E8) +#define WMAC0_PDG_R0_HW_RU_MAX_UNUSED_RU___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_HW_RU_MAX_UNUSED_RU___POR 0x25120904 +#define WMAC0_PDG_R0_HW_RU_MAX_UNUSED_RU__THRESHOLD_160___POR 0x25 +#define WMAC0_PDG_R0_HW_RU_MAX_UNUSED_RU__THRESHOLD_80___POR 0x12 +#define WMAC0_PDG_R0_HW_RU_MAX_UNUSED_RU__THRESHOLD_40___POR 0x09 +#define WMAC0_PDG_R0_HW_RU_MAX_UNUSED_RU__THRESHOLD_20___POR 0x4 +#define WMAC0_PDG_R0_HW_RU_MAX_UNUSED_RU__THRESHOLD_160___M 0x7F000000 +#define WMAC0_PDG_R0_HW_RU_MAX_UNUSED_RU__THRESHOLD_160___S 24 +#define WMAC0_PDG_R0_HW_RU_MAX_UNUSED_RU__THRESHOLD_80___M 0x003F0000 +#define WMAC0_PDG_R0_HW_RU_MAX_UNUSED_RU__THRESHOLD_80___S 16 +#define WMAC0_PDG_R0_HW_RU_MAX_UNUSED_RU__THRESHOLD_40___M 0x00001F00 +#define WMAC0_PDG_R0_HW_RU_MAX_UNUSED_RU__THRESHOLD_40___S 8 +#define WMAC0_PDG_R0_HW_RU_MAX_UNUSED_RU__THRESHOLD_20___M 0x0000000F +#define WMAC0_PDG_R0_HW_RU_MAX_UNUSED_RU__THRESHOLD_20___S 0 +#define WMAC0_PDG_R0_HW_RU_MAX_UNUSED_RU___M 0x7F3F1F0F +#define WMAC0_PDG_R0_HW_RU_MAX_UNUSED_RU___S 0 + +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP (0x00A800EC) +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP___POR 0x00000000 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_EIGHTH_20MHZ___POR 0x0 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_SEVENTH_20MHZ___POR 0x0 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_SIXTH_20MHZ___POR 0x0 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_FIFTH_20MHZ___POR 0x0 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_FOURTH_20MHZ___POR 0x0 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_THIRD_20MHZ___POR 0x0 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_SECOND_20MHZ___POR 0x0 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_FIRST_20MHZ___POR 0x0 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU242_IN_SECOND_80MHZ___POR 0x0 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU106_IN_SECOND_80MHZ___POR 0x0 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU52_IN_SECOND_80MHZ___POR 0x0 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU26_IN_SECOND_80MHZ___POR 0x0 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU242_IN_FIRST_80MHZ___POR 0x0 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU106_IN_FIRST_80MHZ___POR 0x0 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU52_IN_FIRST_80MHZ___POR 0x0 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU26_IN_FIRST_80MHZ___POR 0x0 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_EIGHTH_20MHZ___M 0x00800000 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_EIGHTH_20MHZ___S 23 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_SEVENTH_20MHZ___M 0x00400000 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_SEVENTH_20MHZ___S 22 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_SIXTH_20MHZ___M 0x00200000 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_SIXTH_20MHZ___S 21 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_FIFTH_20MHZ___M 0x00100000 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_FIFTH_20MHZ___S 20 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_FOURTH_20MHZ___M 0x00080000 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_FOURTH_20MHZ___S 19 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_THIRD_20MHZ___M 0x00040000 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_THIRD_20MHZ___S 18 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_SECOND_20MHZ___M 0x00020000 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_SECOND_20MHZ___S 17 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_FIRST_20MHZ___M 0x00010000 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU_TONE_IN_FIRST_20MHZ___S 16 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU242_IN_SECOND_80MHZ___M 0x00000800 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU242_IN_SECOND_80MHZ___S 11 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU106_IN_SECOND_80MHZ___M 0x00000400 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU106_IN_SECOND_80MHZ___S 10 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU52_IN_SECOND_80MHZ___M 0x00000200 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU52_IN_SECOND_80MHZ___S 9 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU26_IN_SECOND_80MHZ___M 0x00000100 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU26_IN_SECOND_80MHZ___S 8 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU242_IN_FIRST_80MHZ___M 0x00000008 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU242_IN_FIRST_80MHZ___S 3 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU106_IN_FIRST_80MHZ___M 0x00000004 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU106_IN_FIRST_80MHZ___S 2 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU52_IN_FIRST_80MHZ___M 0x00000002 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU52_IN_FIRST_80MHZ___S 1 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU26_IN_FIRST_80MHZ___M 0x00000001 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP__RU26_IN_FIRST_80MHZ___S 0 +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP___M 0x00FF0F0F +#define WMAC0_PDG_R0_BLOCK_TRIG_RESP___S 0 + +#define WMAC0_PDG_R0_OFDMA_TRIG_CS_DISABLE (0x00A800F0) +#define WMAC0_PDG_R0_OFDMA_TRIG_CS_DISABLE___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_OFDMA_TRIG_CS_DISABLE___POR 0x00000000 +#define WMAC0_PDG_R0_OFDMA_TRIG_CS_DISABLE__VALUE___POR 0x0000 +#define WMAC0_PDG_R0_OFDMA_TRIG_CS_DISABLE__VALUE___M 0x0000FFFF +#define WMAC0_PDG_R0_OFDMA_TRIG_CS_DISABLE__VALUE___S 0 +#define WMAC0_PDG_R0_OFDMA_TRIG_CS_DISABLE___M 0x0000FFFF +#define WMAC0_PDG_R0_OFDMA_TRIG_CS_DISABLE___S 0 + +#define WMAC0_PDG_R0_OFDMA_TRIG_TX_DURATION (0x00A800F4) +#define WMAC0_PDG_R0_OFDMA_TRIG_TX_DURATION___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_OFDMA_TRIG_TX_DURATION___POR 0x00000000 +#define WMAC0_PDG_R0_OFDMA_TRIG_TX_DURATION__OVERWRITE___POR 0x0 +#define WMAC0_PDG_R0_OFDMA_TRIG_TX_DURATION__OVERWRITE___M 0x00000001 +#define WMAC0_PDG_R0_OFDMA_TRIG_TX_DURATION__OVERWRITE___S 0 +#define WMAC0_PDG_R0_OFDMA_TRIG_TX_DURATION___M 0x00000001 +#define WMAC0_PDG_R0_OFDMA_TRIG_TX_DURATION___S 0 + +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH (0x00A800F8) +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH___POR 0x00FAC688 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT7___POR 0x7 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT6___POR 0x6 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT5___POR 0x5 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT4___POR 0x4 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT3___POR 0x3 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT2___POR 0x2 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT1___POR 0x1 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT0___POR 0x0 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT7___M 0x00E00000 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT7___S 21 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT6___M 0x001C0000 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT6___S 18 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT5___M 0x00038000 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT5___S 15 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT4___M 0x00007000 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT4___S 12 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT3___M 0x00000E00 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT3___S 9 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT2___M 0x000001C0 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT2___S 6 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT1___M 0x00000038 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT1___S 3 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT0___M 0x00000007 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH__BIT0___S 0 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH___M 0x00FFFFFF +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_CCA_FREQ_SWITCH___S 0 + +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH (0x00A800FC) +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH___POR 0x00FAC688 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT7___POR 0x7 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT6___POR 0x6 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT5___POR 0x5 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT4___POR 0x4 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT3___POR 0x3 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT2___POR 0x2 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT1___POR 0x1 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT0___POR 0x0 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT7___M 0x00E00000 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT7___S 21 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT6___M 0x001C0000 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT6___S 18 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT5___M 0x00038000 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT5___S 15 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT4___M 0x00007000 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT4___S 12 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT3___M 0x00000E00 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT3___S 9 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT2___M 0x000001C0 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT2___S 6 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT1___M 0x00000038 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT1___S 3 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT0___M 0x00000007 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH__BIT0___S 0 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH___M 0x00FFFFFF +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH___S 0 + +#define WMAC0_PDG_R0_CTS_RESP_TO_MU_RTS_MCS (0x00A80100) +#define WMAC0_PDG_R0_CTS_RESP_TO_MU_RTS_MCS___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_CTS_RESP_TO_MU_RTS_MCS___POR 0x00000003 +#define WMAC0_PDG_R0_CTS_RESP_TO_MU_RTS_MCS__VALUE___POR 0x3 +#define WMAC0_PDG_R0_CTS_RESP_TO_MU_RTS_MCS__VALUE___M 0x00000007 +#define WMAC0_PDG_R0_CTS_RESP_TO_MU_RTS_MCS__VALUE___S 0 +#define WMAC0_PDG_R0_CTS_RESP_TO_MU_RTS_MCS___M 0x00000007 +#define WMAC0_PDG_R0_CTS_RESP_TO_MU_RTS_MCS___S 0 + +#define WMAC0_PDG_R0_SW_RAW_CARRIER_SENSE_REQUIRED_BITMAP_29_0 (0x00A80104) +#define WMAC0_PDG_R0_SW_RAW_CARRIER_SENSE_REQUIRED_BITMAP_29_0___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_SW_RAW_CARRIER_SENSE_REQUIRED_BITMAP_29_0___POR 0x01041041 +#define WMAC0_PDG_R0_SW_RAW_CARRIER_SENSE_REQUIRED_BITMAP_29_0__VALUE___POR 0x01041041 +#define WMAC0_PDG_R0_SW_RAW_CARRIER_SENSE_REQUIRED_BITMAP_29_0__VALUE___M 0x3FFFFFFF +#define WMAC0_PDG_R0_SW_RAW_CARRIER_SENSE_REQUIRED_BITMAP_29_0__VALUE___S 0 +#define WMAC0_PDG_R0_SW_RAW_CARRIER_SENSE_REQUIRED_BITMAP_29_0___M 0x3FFFFFFF +#define WMAC0_PDG_R0_SW_RAW_CARRIER_SENSE_REQUIRED_BITMAP_29_0___S 0 + +#define WMAC0_PDG_R0_SW_RAW_CARRIER_SENSE_REQUIRED_BITMAP_47_30 (0x00A80108) +#define WMAC0_PDG_R0_SW_RAW_CARRIER_SENSE_REQUIRED_BITMAP_47_30___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_SW_RAW_CARRIER_SENSE_REQUIRED_BITMAP_47_30___POR 0x00001041 +#define WMAC0_PDG_R0_SW_RAW_CARRIER_SENSE_REQUIRED_BITMAP_47_30__VALUE___POR 0x01041 +#define WMAC0_PDG_R0_SW_RAW_CARRIER_SENSE_REQUIRED_BITMAP_47_30__VALUE___M 0x0003FFFF +#define WMAC0_PDG_R0_SW_RAW_CARRIER_SENSE_REQUIRED_BITMAP_47_30__VALUE___S 0 +#define WMAC0_PDG_R0_SW_RAW_CARRIER_SENSE_REQUIRED_BITMAP_47_30___M 0x0003FFFF +#define WMAC0_PDG_R0_SW_RAW_CARRIER_SENSE_REQUIRED_BITMAP_47_30___S 0 + +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS (0x00A8010C) +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS___POR 0x01FAC688 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__EN___POR 0x1 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT7___POR 0x7 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT6___POR 0x6 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT5___POR 0x5 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT4___POR 0x4 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT3___POR 0x3 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT2___POR 0x2 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT1___POR 0x1 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT0___POR 0x0 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__EN___M 0x01000000 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__EN___S 24 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT7___M 0x00E00000 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT7___S 21 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT6___M 0x001C0000 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT6___S 18 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT5___M 0x00038000 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT5___S 15 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT4___M 0x00007000 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT4___S 12 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT3___M 0x00000E00 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT3___S 9 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT2___M 0x000001C0 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT2___S 6 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT1___M 0x00000038 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT1___S 3 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT0___M 0x00000007 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS__BIT0___S 0 +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS___M 0x01FFFFFF +#define WMAC0_PDG_R0_SUBBAND_CHANNEL_BOND_MASK_FREQ_CCA_SWITCH_CTS___S 0 + +#define WMAC0_PDG_R0_CENTER_RU_CTRL (0x00A80110) +#define WMAC0_PDG_R0_CENTER_RU_CTRL___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_CENTER_RU_CTRL___POR 0x00000000 +#define WMAC0_PDG_R0_CENTER_RU_CTRL__EN___POR 0x0 +#define WMAC0_PDG_R0_CENTER_RU_CTRL__EN___M 0x00000001 +#define WMAC0_PDG_R0_CENTER_RU_CTRL__EN___S 0 +#define WMAC0_PDG_R0_CENTER_RU_CTRL___M 0x00000001 +#define WMAC0_PDG_R0_CENTER_RU_CTRL___S 0 + +#define WMAC0_PDG_R0_CTS_RESP_MU_RTS_STF_LTF_3DB_BOOST (0x00A80114) +#define WMAC0_PDG_R0_CTS_RESP_MU_RTS_STF_LTF_3DB_BOOST___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_CTS_RESP_MU_RTS_STF_LTF_3DB_BOOST___POR 0x00000000 +#define WMAC0_PDG_R0_CTS_RESP_MU_RTS_STF_LTF_3DB_BOOST__EN___POR 0x0 +#define WMAC0_PDG_R0_CTS_RESP_MU_RTS_STF_LTF_3DB_BOOST__EN___M 0x00000001 +#define WMAC0_PDG_R0_CTS_RESP_MU_RTS_STF_LTF_3DB_BOOST__EN___S 0 +#define WMAC0_PDG_R0_CTS_RESP_MU_RTS_STF_LTF_3DB_BOOST___M 0x00000001 +#define WMAC0_PDG_R0_CTS_RESP_MU_RTS_STF_LTF_3DB_BOOST___S 0 + +#define WMAC0_PDG_R0_TRIG_RESP_STA_NARROW_BW (0x00A80118) +#define WMAC0_PDG_R0_TRIG_RESP_STA_NARROW_BW___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_TRIG_RESP_STA_NARROW_BW___POR 0x00000003 +#define WMAC0_PDG_R0_TRIG_RESP_STA_NARROW_BW__MU_RTS_FLUSH___POR 0x0 +#define WMAC0_PDG_R0_TRIG_RESP_STA_NARROW_BW__RU_CHECK___POR 0x0 +#define WMAC0_PDG_R0_TRIG_RESP_STA_NARROW_BW__OP_BW___POR 0x3 +#define WMAC0_PDG_R0_TRIG_RESP_STA_NARROW_BW__MU_RTS_FLUSH___M 0x00000010 +#define WMAC0_PDG_R0_TRIG_RESP_STA_NARROW_BW__MU_RTS_FLUSH___S 4 +#define WMAC0_PDG_R0_TRIG_RESP_STA_NARROW_BW__RU_CHECK___M 0x00000008 +#define WMAC0_PDG_R0_TRIG_RESP_STA_NARROW_BW__RU_CHECK___S 3 +#define WMAC0_PDG_R0_TRIG_RESP_STA_NARROW_BW__OP_BW___M 0x00000007 +#define WMAC0_PDG_R0_TRIG_RESP_STA_NARROW_BW__OP_BW___S 0 +#define WMAC0_PDG_R0_TRIG_RESP_STA_NARROW_BW___M 0x0000001F +#define WMAC0_PDG_R0_TRIG_RESP_STA_NARROW_BW___S 0 + +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_n(n) (0x00A8011C+0x4*(n)) +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_n_nMIN 0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_n_nMAX 1 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_n_ELEM 2 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_n___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_n___POR 0x00000000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_n__TX_GAIN_SETTING___POR 0x00 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_n__TX_ANTENNA_SECTOR_CTRL___POR 0x000000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_n__TX_GAIN_SETTING___M 0xFF000000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_n__TX_GAIN_SETTING___S 24 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_n__TX_ANTENNA_SECTOR_CTRL___M 0x00FFFFFF +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_n__TX_ANTENNA_SECTOR_CTRL___S 0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_n___M 0xFFFFFFFF +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_n___S 0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_0 (0x00A8011C) +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_0___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_0__TX_GAIN_SETTING___M 0xFF000000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_0__TX_GAIN_SETTING___S 24 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_0__TX_ANTENNA_SECTOR_CTRL___M 0x00FFFFFF +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_0__TX_ANTENNA_SECTOR_CTRL___S 0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_1 (0x00A80120) +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_1___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_1__TX_GAIN_SETTING___M 0xFF000000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_1__TX_GAIN_SETTING___S 24 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_1__TX_ANTENNA_SECTOR_CTRL___M 0x00FFFFFF +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_I_1__TX_ANTENNA_SECTOR_CTRL___S 0 + +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n(n) (0x00A8013C+0x4*(n)) +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n_nMIN 0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n_nMAX 1 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n_ELEM 2 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n___POR 0x00000000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__DOT11AX_LTF_SIZE_RESP___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__DOT11AX_LTF_SIZE___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__SGI_RESP___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__SGI___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__DPD_ENABLE___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__DOT11AX_SU_EXTENDED_RESP___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__DOT11AX_SU_EXTENDED___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__STBC_RESP___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__STBC___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__SMOOTHING___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__PKT_TYPE_RESP___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__PKT_TYPE___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__DOT11AX_LTF_SIZE_RESP___M 0x00300000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__DOT11AX_LTF_SIZE_RESP___S 20 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__DOT11AX_LTF_SIZE___M 0x000C0000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__DOT11AX_LTF_SIZE___S 18 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__SGI_RESP___M 0x00030000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__SGI_RESP___S 16 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__SGI___M 0x0000C000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__SGI___S 14 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__DPD_ENABLE___M 0x00002000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__DPD_ENABLE___S 13 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__DOT11AX_SU_EXTENDED_RESP___M 0x00001000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__DOT11AX_SU_EXTENDED_RESP___S 12 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__DOT11AX_SU_EXTENDED___M 0x00000800 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__DOT11AX_SU_EXTENDED___S 11 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__STBC_RESP___M 0x00000400 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__STBC_RESP___S 10 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__STBC___M 0x00000200 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__STBC___S 9 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__SMOOTHING___M 0x00000100 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__SMOOTHING___S 8 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__PKT_TYPE_RESP___M 0x000000F0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__PKT_TYPE_RESP___S 4 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__PKT_TYPE___M 0x0000000F +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n__PKT_TYPE___S 0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n___M 0x003FFFFF +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_n___S 0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0 (0x00A8013C) +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__DOT11AX_LTF_SIZE_RESP___M 0x00300000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__DOT11AX_LTF_SIZE_RESP___S 20 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__DOT11AX_LTF_SIZE___M 0x000C0000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__DOT11AX_LTF_SIZE___S 18 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__SGI_RESP___M 0x00030000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__SGI_RESP___S 16 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__SGI___M 0x0000C000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__SGI___S 14 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__DPD_ENABLE___M 0x00002000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__DPD_ENABLE___S 13 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__DOT11AX_SU_EXTENDED_RESP___M 0x00001000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__DOT11AX_SU_EXTENDED_RESP___S 12 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__DOT11AX_SU_EXTENDED___M 0x00000800 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__DOT11AX_SU_EXTENDED___S 11 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__STBC_RESP___M 0x00000400 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__STBC_RESP___S 10 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__STBC___M 0x00000200 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__STBC___S 9 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__SMOOTHING___M 0x00000100 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__SMOOTHING___S 8 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__PKT_TYPE_RESP___M 0x000000F0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__PKT_TYPE_RESP___S 4 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__PKT_TYPE___M 0x0000000F +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_0__PKT_TYPE___S 0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1 (0x00A80140) +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__DOT11AX_LTF_SIZE_RESP___M 0x00300000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__DOT11AX_LTF_SIZE_RESP___S 20 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__DOT11AX_LTF_SIZE___M 0x000C0000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__DOT11AX_LTF_SIZE___S 18 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__SGI_RESP___M 0x00030000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__SGI_RESP___S 16 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__SGI___M 0x0000C000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__SGI___S 14 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__DPD_ENABLE___M 0x00002000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__DPD_ENABLE___S 13 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__DOT11AX_SU_EXTENDED_RESP___M 0x00001000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__DOT11AX_SU_EXTENDED_RESP___S 12 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__DOT11AX_SU_EXTENDED___M 0x00000800 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__DOT11AX_SU_EXTENDED___S 11 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__STBC_RESP___M 0x00000400 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__STBC_RESP___S 10 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__STBC___M 0x00000200 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__STBC___S 9 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__SMOOTHING___M 0x00000100 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__SMOOTHING___S 8 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__PKT_TYPE_RESP___M 0x000000F0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__PKT_TYPE_RESP___S 4 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__PKT_TYPE___M 0x0000000F +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_II_1__PKT_TYPE___S 0 + +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n(n) (0x00A8015C+0x4*(n)) +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n_nMIN 0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n_nMAX 1 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n_ELEM 2 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n___POR 0x00000000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n__TX_CHAIN_MASK___POR 0x00 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n__TX_PWR_1___POR 0x00 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n__MIN_TX_PWR___POR 0x00 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n__TX_PWR___POR 0x00 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n__TX_CHAIN_MASK___M 0xFF000000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n__TX_CHAIN_MASK___S 24 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n__TX_PWR_1___M 0x00FF0000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n__TX_PWR_1___S 16 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n__MIN_TX_PWR___M 0x0000FF00 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n__MIN_TX_PWR___S 8 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n__TX_PWR___M 0x000000FF +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n__TX_PWR___S 0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n___M 0xFFFFFFFF +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_n___S 0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_0 (0x00A8015C) +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_0___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_0__TX_CHAIN_MASK___M 0xFF000000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_0__TX_CHAIN_MASK___S 24 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_0__TX_PWR_1___M 0x00FF0000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_0__TX_PWR_1___S 16 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_0__MIN_TX_PWR___M 0x0000FF00 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_0__MIN_TX_PWR___S 8 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_0__TX_PWR___M 0x000000FF +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_0__TX_PWR___S 0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_1 (0x00A80160) +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_1___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_1__TX_CHAIN_MASK___M 0xFF000000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_1__TX_CHAIN_MASK___S 24 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_1__TX_PWR_1___M 0x00FF0000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_1__TX_PWR_1___S 16 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_1__MIN_TX_PWR___M 0x0000FF00 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_1__MIN_TX_PWR___S 8 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_1__TX_PWR___M 0x000000FF +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_III_1__TX_PWR___S 0 + +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n(n) (0x00A8017C+0x4*(n)) +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n_nMIN 0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n_nMAX 1 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n_ELEM 2 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n___POR 0x00000000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__DOT11AX_DCM_RESP___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__DOT11AX_DCM___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__NSS_RESP___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__NSS___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__LDPC_RESP___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__LDPC___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__RATE_MCS_RESP___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__RATE_MCS___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__DOT11AX_DCM_RESP___M 0x00020000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__DOT11AX_DCM_RESP___S 17 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__DOT11AX_DCM___M 0x00010000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__DOT11AX_DCM___S 16 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__NSS_RESP___M 0x0000E000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__NSS_RESP___S 13 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__NSS___M 0x00001C00 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__NSS___S 10 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__LDPC_RESP___M 0x00000200 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__LDPC_RESP___S 9 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__LDPC___M 0x00000100 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__LDPC___S 8 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__RATE_MCS_RESP___M 0x000000F0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__RATE_MCS_RESP___S 4 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__RATE_MCS___M 0x0000000F +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n__RATE_MCS___S 0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n___M 0x0003FFFF +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_n___S 0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0 (0x00A8017C) +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0__DOT11AX_DCM_RESP___M 0x00020000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0__DOT11AX_DCM_RESP___S 17 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0__DOT11AX_DCM___M 0x00010000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0__DOT11AX_DCM___S 16 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0__NSS_RESP___M 0x0000E000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0__NSS_RESP___S 13 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0__NSS___M 0x00001C00 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0__NSS___S 10 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0__LDPC_RESP___M 0x00000200 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0__LDPC_RESP___S 9 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0__LDPC___M 0x00000100 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0__LDPC___S 8 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0__RATE_MCS_RESP___M 0x000000F0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0__RATE_MCS_RESP___S 4 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0__RATE_MCS___M 0x0000000F +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_0__RATE_MCS___S 0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1 (0x00A80180) +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1__DOT11AX_DCM_RESP___M 0x00020000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1__DOT11AX_DCM_RESP___S 17 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1__DOT11AX_DCM___M 0x00010000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1__DOT11AX_DCM___S 16 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1__NSS_RESP___M 0x0000E000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1__NSS_RESP___S 13 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1__NSS___M 0x00001C00 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1__NSS___S 10 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1__LDPC_RESP___M 0x00000200 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1__LDPC_RESP___S 9 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1__LDPC___M 0x00000100 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1__LDPC___S 8 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1__RATE_MCS_RESP___M 0x000000F0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1__RATE_MCS_RESP___S 4 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1__RATE_MCS___M 0x0000000F +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IV_1__RATE_MCS___S 0 + +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n(n) (0x00A8019C+0x4*(n)) +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n_nMIN 0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n_nMAX 1 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n_ELEM 2 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n___POR 0x00000000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__BW_20_OVERRIDE_ENABLE___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__BACK_TO_BACK_TRANSMISSION_EXPECTED___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__COEX_TX_PRIORITY___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__MEASURE_POWER___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_DL_UL_FLAG___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_SPATIAL_REUSE___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_PE_CONTENT___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_PE_LTF_SIZE___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_PE_NSS___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_PE_CHAIN_CSD_EN___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_CHAIN_CSD_EN___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__STF_LTF_3DB_BOOST___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__BW_20_OVERRIDE_ENABLE___M 0x00100000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__BW_20_OVERRIDE_ENABLE___S 20 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__BACK_TO_BACK_TRANSMISSION_EXPECTED___M 0x00080000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__BACK_TO_BACK_TRANSMISSION_EXPECTED___S 19 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__COEX_TX_PRIORITY___M 0x00078000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__COEX_TX_PRIORITY___S 15 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__MEASURE_POWER___M 0x00004000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__MEASURE_POWER___S 14 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_DL_UL_FLAG___M 0x00002000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_DL_UL_FLAG___S 13 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_SPATIAL_REUSE___M 0x00001E00 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_SPATIAL_REUSE___S 9 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_PE_CONTENT___M 0x00000100 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_PE_CONTENT___S 8 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_PE_LTF_SIZE___M 0x000000C0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_PE_LTF_SIZE___S 6 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_PE_NSS___M 0x00000038 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_PE_NSS___S 3 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_PE_CHAIN_CSD_EN___M 0x00000004 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_PE_CHAIN_CSD_EN___S 2 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_CHAIN_CSD_EN___M 0x00000002 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__DOT11AX_CHAIN_CSD_EN___S 1 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__STF_LTF_3DB_BOOST___M 0x00000001 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n__STF_LTF_3DB_BOOST___S 0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n___M 0x001FFFFF +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_n___S 0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0 (0x00A8019C) +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__BW_20_OVERRIDE_ENABLE___M 0x00100000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__BW_20_OVERRIDE_ENABLE___S 20 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__BACK_TO_BACK_TRANSMISSION_EXPECTED___M 0x00080000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__BACK_TO_BACK_TRANSMISSION_EXPECTED___S 19 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__COEX_TX_PRIORITY___M 0x00078000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__COEX_TX_PRIORITY___S 15 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__MEASURE_POWER___M 0x00004000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__MEASURE_POWER___S 14 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__DOT11AX_DL_UL_FLAG___M 0x00002000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__DOT11AX_DL_UL_FLAG___S 13 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__DOT11AX_SPATIAL_REUSE___M 0x00001E00 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__DOT11AX_SPATIAL_REUSE___S 9 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__DOT11AX_PE_CONTENT___M 0x00000100 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__DOT11AX_PE_CONTENT___S 8 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__DOT11AX_PE_LTF_SIZE___M 0x000000C0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__DOT11AX_PE_LTF_SIZE___S 6 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__DOT11AX_PE_NSS___M 0x00000038 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__DOT11AX_PE_NSS___S 3 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__DOT11AX_PE_CHAIN_CSD_EN___M 0x00000004 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__DOT11AX_PE_CHAIN_CSD_EN___S 2 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__DOT11AX_CHAIN_CSD_EN___M 0x00000002 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__DOT11AX_CHAIN_CSD_EN___S 1 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__STF_LTF_3DB_BOOST___M 0x00000001 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_0__STF_LTF_3DB_BOOST___S 0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1 (0x00A801A0) +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__BW_20_OVERRIDE_ENABLE___M 0x00100000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__BW_20_OVERRIDE_ENABLE___S 20 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__BACK_TO_BACK_TRANSMISSION_EXPECTED___M 0x00080000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__BACK_TO_BACK_TRANSMISSION_EXPECTED___S 19 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__COEX_TX_PRIORITY___M 0x00078000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__COEX_TX_PRIORITY___S 15 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__MEASURE_POWER___M 0x00004000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__MEASURE_POWER___S 14 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__DOT11AX_DL_UL_FLAG___M 0x00002000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__DOT11AX_DL_UL_FLAG___S 13 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__DOT11AX_SPATIAL_REUSE___M 0x00001E00 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__DOT11AX_SPATIAL_REUSE___S 9 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__DOT11AX_PE_CONTENT___M 0x00000100 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__DOT11AX_PE_CONTENT___S 8 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__DOT11AX_PE_LTF_SIZE___M 0x000000C0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__DOT11AX_PE_LTF_SIZE___S 6 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__DOT11AX_PE_NSS___M 0x00000038 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__DOT11AX_PE_NSS___S 3 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__DOT11AX_PE_CHAIN_CSD_EN___M 0x00000004 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__DOT11AX_PE_CHAIN_CSD_EN___S 2 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__DOT11AX_CHAIN_CSD_EN___M 0x00000002 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__DOT11AX_CHAIN_CSD_EN___S 1 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__STF_LTF_3DB_BOOST___M 0x00000001 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_V_1__STF_LTF_3DB_BOOST___S 0 + +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n(n) (0x00A801BC+0x4*(n)) +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n_nMIN 0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n_nMAX 1 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n_ELEM 2 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n___POR 0x00000000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__TPC_GLUT_SELF_CAL___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__BEAM_CHANGE_RESP___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__BEAM_CHANGE___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__BF_ENABLED___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__RU_POSITION_END_RESP___POR 0x00 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__RU_POSITION_END___POR 0x00 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__RU_POSITION_START_RESP___POR 0x00 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__RU_POSITION_START___POR 0x00 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__TPC_GLUT_SELF_CAL___M 0x80000000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__TPC_GLUT_SELF_CAL___S 31 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__BEAM_CHANGE_RESP___M 0x40000000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__BEAM_CHANGE_RESP___S 30 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__BEAM_CHANGE___M 0x20000000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__BEAM_CHANGE___S 29 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__BF_ENABLED___M 0x10000000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__BF_ENABLED___S 28 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__RU_POSITION_END_RESP___M 0x0FE00000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__RU_POSITION_END_RESP___S 21 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__RU_POSITION_END___M 0x001FC000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__RU_POSITION_END___S 14 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__RU_POSITION_START_RESP___M 0x00003F80 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__RU_POSITION_START_RESP___S 7 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__RU_POSITION_START___M 0x0000007F +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n__RU_POSITION_START___S 0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n___M 0xFFFFFFFF +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_n___S 0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0 (0x00A801BC) +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0__TPC_GLUT_SELF_CAL___M 0x80000000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0__TPC_GLUT_SELF_CAL___S 31 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0__BEAM_CHANGE_RESP___M 0x40000000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0__BEAM_CHANGE_RESP___S 30 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0__BEAM_CHANGE___M 0x20000000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0__BEAM_CHANGE___S 29 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0__BF_ENABLED___M 0x10000000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0__BF_ENABLED___S 28 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0__RU_POSITION_END_RESP___M 0x0FE00000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0__RU_POSITION_END_RESP___S 21 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0__RU_POSITION_END___M 0x001FC000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0__RU_POSITION_END___S 14 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0__RU_POSITION_START_RESP___M 0x00003F80 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0__RU_POSITION_START_RESP___S 7 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0__RU_POSITION_START___M 0x0000007F +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_0__RU_POSITION_START___S 0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1 (0x00A801C0) +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1__TPC_GLUT_SELF_CAL___M 0x80000000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1__TPC_GLUT_SELF_CAL___S 31 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1__BEAM_CHANGE_RESP___M 0x40000000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1__BEAM_CHANGE_RESP___S 30 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1__BEAM_CHANGE___M 0x20000000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1__BEAM_CHANGE___S 29 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1__BF_ENABLED___M 0x10000000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1__BF_ENABLED___S 28 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1__RU_POSITION_END_RESP___M 0x0FE00000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1__RU_POSITION_END_RESP___S 21 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1__RU_POSITION_END___M 0x001FC000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1__RU_POSITION_END___S 14 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1__RU_POSITION_START_RESP___M 0x00003F80 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1__RU_POSITION_START_RESP___S 7 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1__RU_POSITION_START___M 0x0000007F +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VI_1__RU_POSITION_START___S 0 + +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n(n) (0x00A801DC+0x4*(n)) +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n_nMIN 0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n_nMAX 1 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n_ELEM 2 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n___POR 0x00000000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n__ALT_TX_CHAIN_MASK___POR 0x00 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n__ALT_TX_PWR_1___POR 0x00 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n__ALT_MIN_TX_PWR___POR 0x00 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n__ALT_TX_PWR___POR 0x00 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n__ALT_TX_CHAIN_MASK___M 0xFF000000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n__ALT_TX_CHAIN_MASK___S 24 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n__ALT_TX_PWR_1___M 0x00FF0000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n__ALT_TX_PWR_1___S 16 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n__ALT_MIN_TX_PWR___M 0x0000FF00 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n__ALT_MIN_TX_PWR___S 8 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n__ALT_TX_PWR___M 0x000000FF +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n__ALT_TX_PWR___S 0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n___M 0xFFFFFFFF +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_n___S 0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_0 (0x00A801DC) +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_0___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_0__ALT_TX_CHAIN_MASK___M 0xFF000000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_0__ALT_TX_CHAIN_MASK___S 24 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_0__ALT_TX_PWR_1___M 0x00FF0000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_0__ALT_TX_PWR_1___S 16 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_0__ALT_MIN_TX_PWR___M 0x0000FF00 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_0__ALT_MIN_TX_PWR___S 8 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_0__ALT_TX_PWR___M 0x000000FF +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_0__ALT_TX_PWR___S 0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_1 (0x00A801E0) +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_1___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_1__ALT_TX_CHAIN_MASK___M 0xFF000000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_1__ALT_TX_CHAIN_MASK___S 24 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_1__ALT_TX_PWR_1___M 0x00FF0000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_1__ALT_TX_PWR_1___S 16 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_1__ALT_MIN_TX_PWR___M 0x0000FF00 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_1__ALT_MIN_TX_PWR___S 8 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_1__ALT_TX_PWR___M 0x000000FF +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VII_1__ALT_TX_PWR___S 0 + +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n(n) (0x00A801FC+0x4*(n)) +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n_nMIN 0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n_nMAX 1 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n_ELEM 2 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n___POR 0x00000000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__USER_BF_TYPE___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__VHT_HE_SIG_TXBF___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__ALT_NSS_RESP___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__ALT_NSS___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__ALT_RATE_MCS_RESP___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__ALT_RATE_MCS___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__USER_BF_TYPE___M 0x00018000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__USER_BF_TYPE___S 15 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__VHT_HE_SIG_TXBF___M 0x00004000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__VHT_HE_SIG_TXBF___S 14 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__ALT_NSS_RESP___M 0x00003800 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__ALT_NSS_RESP___S 11 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__ALT_NSS___M 0x00000700 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__ALT_NSS___S 8 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__ALT_RATE_MCS_RESP___M 0x000000F0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__ALT_RATE_MCS_RESP___S 4 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__ALT_RATE_MCS___M 0x0000000F +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n__ALT_RATE_MCS___S 0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n___M 0x0001FFFF +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_n___S 0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_0 (0x00A801FC) +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_0___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_0__USER_BF_TYPE___M 0x00018000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_0__USER_BF_TYPE___S 15 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_0__VHT_HE_SIG_TXBF___M 0x00004000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_0__VHT_HE_SIG_TXBF___S 14 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_0__ALT_NSS_RESP___M 0x00003800 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_0__ALT_NSS_RESP___S 11 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_0__ALT_NSS___M 0x00000700 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_0__ALT_NSS___S 8 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_0__ALT_RATE_MCS_RESP___M 0x000000F0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_0__ALT_RATE_MCS_RESP___S 4 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_0__ALT_RATE_MCS___M 0x0000000F +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_0__ALT_RATE_MCS___S 0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_1 (0x00A80200) +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_1___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_1__USER_BF_TYPE___M 0x00018000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_1__USER_BF_TYPE___S 15 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_1__VHT_HE_SIG_TXBF___M 0x00004000 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_1__VHT_HE_SIG_TXBF___S 14 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_1__ALT_NSS_RESP___M 0x00003800 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_1__ALT_NSS_RESP___S 11 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_1__ALT_NSS___M 0x00000700 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_1__ALT_NSS___S 8 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_1__ALT_RATE_MCS_RESP___M 0x000000F0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_1__ALT_RATE_MCS_RESP___S 4 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_1__ALT_RATE_MCS___M 0x0000000F +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_VIII_1__ALT_RATE_MCS___S 0 + +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IX (0x00A8021C) +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IX___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IX___POR 0x00000E00 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IX__NOTIFY_FRAME_MASK___POR 0x7 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IX__WAIT_NOTIFY_EN___POR 0x0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IX__DPDTRAIN_CHAIN_MASK___POR 0x00 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IX__NOTIFY_FRAME_MASK___M 0x00000E00 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IX__NOTIFY_FRAME_MASK___S 9 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IX__WAIT_NOTIFY_EN___M 0x00000100 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IX__WAIT_NOTIFY_EN___S 8 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IX__DPDTRAIN_CHAIN_MASK___M 0x000000FF +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IX__DPDTRAIN_CHAIN_MASK___S 0 +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IX___M 0x00000FFF +#define WMAC0_PDG_R0_TX_NOTIFY_PARAMS_IX___S 0 + +#define WMAC0_PDG_R0_ILP_REGS (0x00A80220) +#define WMAC0_PDG_R0_ILP_REGS___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_ILP_REGS___POR 0x000044A3 +#define WMAC0_PDG_R0_ILP_REGS__QOS_NULL_BYTES___POR 0x22 +#define WMAC0_PDG_R0_ILP_REGS__PHY_MAC_PCIE_LATENCY___POR 0x51 +#define WMAC0_PDG_R0_ILP_REGS__ENABLE_ILP_PPDU_DURATION_CHECK___POR 0x1 +#define WMAC0_PDG_R0_ILP_REGS__QOS_NULL_BYTES___M 0x00007E00 +#define WMAC0_PDG_R0_ILP_REGS__QOS_NULL_BYTES___S 9 +#define WMAC0_PDG_R0_ILP_REGS__PHY_MAC_PCIE_LATENCY___M 0x000001FE +#define WMAC0_PDG_R0_ILP_REGS__PHY_MAC_PCIE_LATENCY___S 1 +#define WMAC0_PDG_R0_ILP_REGS__ENABLE_ILP_PPDU_DURATION_CHECK___M 0x00000001 +#define WMAC0_PDG_R0_ILP_REGS__ENABLE_ILP_PPDU_DURATION_CHECK___S 0 +#define WMAC0_PDG_R0_ILP_REGS___M 0x00007FFF +#define WMAC0_PDG_R0_ILP_REGS___S 0 + +#define WMAC0_PDG_R0_HW_MODE_COEX_DISABLE (0x00A80224) +#define WMAC0_PDG_R0_HW_MODE_COEX_DISABLE___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_HW_MODE_COEX_DISABLE___POR 0x00000000 +#define WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_BW_CHANGE___POR 0x0 +#define WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_TX_ANT_REDUCTION___POR 0x0 +#define WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_TX_MCS_CHANGE___POR 0x0 +#define WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_TX_NSS_CHANGE___POR 0x0 +#define WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_TX_PWR_REDUCTION___POR 0x0 +#define WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_RX_WINDOW_CHECK___POR 0x0 +#define WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_TX_WINDOW_CHECK___POR 0x0 +#define WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_BW_CHANGE___M 0x00000040 +#define WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_BW_CHANGE___S 6 +#define WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_TX_ANT_REDUCTION___M 0x00000020 +#define WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_TX_ANT_REDUCTION___S 5 +#define WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_TX_MCS_CHANGE___M 0x00000010 +#define WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_TX_MCS_CHANGE___S 4 +#define WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_TX_NSS_CHANGE___M 0x00000008 +#define WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_TX_NSS_CHANGE___S 3 +#define WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_TX_PWR_REDUCTION___M 0x00000004 +#define WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_TX_PWR_REDUCTION___S 2 +#define WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_RX_WINDOW_CHECK___M 0x00000002 +#define WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_RX_WINDOW_CHECK___S 1 +#define WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_TX_WINDOW_CHECK___M 0x00000001 +#define WMAC0_PDG_R0_HW_MODE_COEX_DISABLE__COEX_DISABLE_TX_WINDOW_CHECK___S 0 +#define WMAC0_PDG_R0_HW_MODE_COEX_DISABLE___M 0x0000007F +#define WMAC0_PDG_R0_HW_MODE_COEX_DISABLE___S 0 + +#define WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE (0x00A80228) +#define WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE___POR 0x00000000 +#define WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_BW_CHANGE___POR 0x0 +#define WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_TX_ANT_REDUCTION___POR 0x0 +#define WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_TX_MCS_CHANGE___POR 0x0 +#define WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_TX_NSS_CHANGE___POR 0x0 +#define WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_TX_PWR_REDUCTION___POR 0x0 +#define WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_RX_WINDOW_CHECK___POR 0x0 +#define WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_TX_WINDOW_CHECK___POR 0x0 +#define WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_BW_CHANGE___M 0x00000040 +#define WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_BW_CHANGE___S 6 +#define WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_TX_ANT_REDUCTION___M 0x00000020 +#define WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_TX_ANT_REDUCTION___S 5 +#define WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_TX_MCS_CHANGE___M 0x00000010 +#define WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_TX_MCS_CHANGE___S 4 +#define WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_TX_NSS_CHANGE___M 0x00000008 +#define WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_TX_NSS_CHANGE___S 3 +#define WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_TX_PWR_REDUCTION___M 0x00000004 +#define WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_TX_PWR_REDUCTION___S 2 +#define WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_RX_WINDOW_CHECK___M 0x00000002 +#define WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_RX_WINDOW_CHECK___S 1 +#define WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_TX_WINDOW_CHECK___M 0x00000001 +#define WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE__COEX_DISABLE_TX_WINDOW_CHECK___S 0 +#define WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE___M 0x0000007F +#define WMAC0_PDG_R0_RESP_MODE_COEX_DISABLE___S 0 + +#define WMAC0_PDG_R0_SW_MODE_COEX_DISABLE (0x00A8022C) +#define WMAC0_PDG_R0_SW_MODE_COEX_DISABLE___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_SW_MODE_COEX_DISABLE___POR 0x00000000 +#define WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_BW_CHANGE___POR 0x0 +#define WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_TX_ANT_REDUCTION___POR 0x0 +#define WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_TX_MCS_CHANGE___POR 0x0 +#define WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_TX_NSS_CHANGE___POR 0x0 +#define WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_TX_PWR_REDUCTION___POR 0x0 +#define WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_RX_WINDOW_CHECK___POR 0x0 +#define WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_TX_WINDOW_CHECK___POR 0x0 +#define WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_BW_CHANGE___M 0x00000040 +#define WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_BW_CHANGE___S 6 +#define WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_TX_ANT_REDUCTION___M 0x00000020 +#define WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_TX_ANT_REDUCTION___S 5 +#define WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_TX_MCS_CHANGE___M 0x00000010 +#define WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_TX_MCS_CHANGE___S 4 +#define WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_TX_NSS_CHANGE___M 0x00000008 +#define WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_TX_NSS_CHANGE___S 3 +#define WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_TX_PWR_REDUCTION___M 0x00000004 +#define WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_TX_PWR_REDUCTION___S 2 +#define WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_RX_WINDOW_CHECK___M 0x00000002 +#define WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_RX_WINDOW_CHECK___S 1 +#define WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_TX_WINDOW_CHECK___M 0x00000001 +#define WMAC0_PDG_R0_SW_MODE_COEX_DISABLE__COEX_DISABLE_TX_WINDOW_CHECK___S 0 +#define WMAC0_PDG_R0_SW_MODE_COEX_DISABLE___M 0x0000007F +#define WMAC0_PDG_R0_SW_MODE_COEX_DISABLE___S 0 + +#define WMAC0_PDG_R0_COEX_CTS_OFFSET (0x00A80230) +#define WMAC0_PDG_R0_COEX_CTS_OFFSET___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_COEX_CTS_OFFSET___POR 0x00000000 +#define WMAC0_PDG_R0_COEX_CTS_OFFSET__COEX_CTS_OFFSET___POR 0x0000 +#define WMAC0_PDG_R0_COEX_CTS_OFFSET__COEX_CTS_OFFSET___M 0x0000FFFF +#define WMAC0_PDG_R0_COEX_CTS_OFFSET__COEX_CTS_OFFSET___S 0 +#define WMAC0_PDG_R0_COEX_CTS_OFFSET___M 0x0000FFFF +#define WMAC0_PDG_R0_COEX_CTS_OFFSET___S 0 + +#define WMAC0_PDG_R0_COEX_CTS_MIN_FES_DURATION (0x00A80234) +#define WMAC0_PDG_R0_COEX_CTS_MIN_FES_DURATION___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_COEX_CTS_MIN_FES_DURATION___POR 0x00000000 +#define WMAC0_PDG_R0_COEX_CTS_MIN_FES_DURATION__COEX_CTS_MIN_DURATION___POR 0x0000 +#define WMAC0_PDG_R0_COEX_CTS_MIN_FES_DURATION__COEX_CTS_MIN_DURATION___M 0x0000FFFF +#define WMAC0_PDG_R0_COEX_CTS_MIN_FES_DURATION__COEX_CTS_MIN_DURATION___S 0 +#define WMAC0_PDG_R0_COEX_CTS_MIN_FES_DURATION___M 0x0000FFFF +#define WMAC0_PDG_R0_COEX_CTS_MIN_FES_DURATION___S 0 + +#define WMAC0_PDG_R0_COEX_CTS_MODE (0x00A80238) +#define WMAC0_PDG_R0_COEX_CTS_MODE___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_COEX_CTS_MODE___POR 0x00000000 +#define WMAC0_PDG_R0_COEX_CTS_MODE__COEX_CTS_MODE___POR 0x0 +#define WMAC0_PDG_R0_COEX_CTS_MODE__COEX_CTS_MODE___M 0x00000003 +#define WMAC0_PDG_R0_COEX_CTS_MODE__COEX_CTS_MODE___S 0 +#define WMAC0_PDG_R0_COEX_CTS_MODE___M 0x00000003 +#define WMAC0_PDG_R0_COEX_CTS_MODE___S 0 + +#define WMAC0_PDG_R0_OFDMA_TRIG_COEX_TX_PRIORITY (0x00A8023C) +#define WMAC0_PDG_R0_OFDMA_TRIG_COEX_TX_PRIORITY___RWC QCSR_REG_RW +#define WMAC0_PDG_R0_OFDMA_TRIG_COEX_TX_PRIORITY___POR 0x00000000 +#define WMAC0_PDG_R0_OFDMA_TRIG_COEX_TX_PRIORITY__VALUE___POR 0x0 +#define WMAC0_PDG_R0_OFDMA_TRIG_COEX_TX_PRIORITY__VALUE___M 0x0000000F +#define WMAC0_PDG_R0_OFDMA_TRIG_COEX_TX_PRIORITY__VALUE___S 0 +#define WMAC0_PDG_R0_OFDMA_TRIG_COEX_TX_PRIORITY___M 0x0000000F +#define WMAC0_PDG_R0_OFDMA_TRIG_COEX_TX_PRIORITY___S 0 + +#define WMAC0_PDG_R1_EVENTMASK_IX_0 (0x00A81000) +#define WMAC0_PDG_R1_EVENTMASK_IX_0___RWC QCSR_REG_RW +#define WMAC0_PDG_R1_EVENTMASK_IX_0___POR 0x00000000 +#define WMAC0_PDG_R1_EVENTMASK_IX_0__EVENT_MASK___POR 0x00000000 +#define WMAC0_PDG_R1_EVENTMASK_IX_0__EVENT_MASK___M 0xFFFFFFFF +#define WMAC0_PDG_R1_EVENTMASK_IX_0__EVENT_MASK___S 0 +#define WMAC0_PDG_R1_EVENTMASK_IX_0___M 0xFFFFFFFF +#define WMAC0_PDG_R1_EVENTMASK_IX_0___S 0 + +#define WMAC0_PDG_R1_EVENTMASK_IX_1 (0x00A81004) +#define WMAC0_PDG_R1_EVENTMASK_IX_1___RWC QCSR_REG_RW +#define WMAC0_PDG_R1_EVENTMASK_IX_1___POR 0x00000000 +#define WMAC0_PDG_R1_EVENTMASK_IX_1__EVENT_MASK___POR 0x00000000 +#define WMAC0_PDG_R1_EVENTMASK_IX_1__EVENT_MASK___M 0xFFFFFFFF +#define WMAC0_PDG_R1_EVENTMASK_IX_1__EVENT_MASK___S 0 +#define WMAC0_PDG_R1_EVENTMASK_IX_1___M 0xFFFFFFFF +#define WMAC0_PDG_R1_EVENTMASK_IX_1___S 0 + +#define WMAC0_PDG_R1_TESTBUS_CTRL (0x00A81008) +#define WMAC0_PDG_R1_TESTBUS_CTRL___RWC QCSR_REG_RW +#define WMAC0_PDG_R1_TESTBUS_CTRL___POR 0x00000000 +#define WMAC0_PDG_R1_TESTBUS_CTRL__TESTBUS_SEL___POR 0x000 +#define WMAC0_PDG_R1_TESTBUS_CTRL__TESTBUS_SEL___M 0x000001FF +#define WMAC0_PDG_R1_TESTBUS_CTRL__TESTBUS_SEL___S 0 +#define WMAC0_PDG_R1_TESTBUS_CTRL___M 0x000001FF +#define WMAC0_PDG_R1_TESTBUS_CTRL___S 0 + +#define WMAC0_PDG_R1_TESTBUS_LOWER (0x00A8100C) +#define WMAC0_PDG_R1_TESTBUS_LOWER___RWC QCSR_REG_RO +#define WMAC0_PDG_R1_TESTBUS_LOWER___POR 0x00000000 +#define WMAC0_PDG_R1_TESTBUS_LOWER__VALUE___POR 0x00000000 +#define WMAC0_PDG_R1_TESTBUS_LOWER__VALUE___M 0xFFFFFFFF +#define WMAC0_PDG_R1_TESTBUS_LOWER__VALUE___S 0 +#define WMAC0_PDG_R1_TESTBUS_LOWER___M 0xFFFFFFFF +#define WMAC0_PDG_R1_TESTBUS_LOWER___S 0 + +#define WMAC0_PDG_R1_TESTBUS_UPPER (0x00A81010) +#define WMAC0_PDG_R1_TESTBUS_UPPER___RWC QCSR_REG_RO +#define WMAC0_PDG_R1_TESTBUS_UPPER___POR 0x00000000 +#define WMAC0_PDG_R1_TESTBUS_UPPER__VALUE___POR 0x00 +#define WMAC0_PDG_R1_TESTBUS_UPPER__VALUE___M 0x000000FF +#define WMAC0_PDG_R1_TESTBUS_UPPER__VALUE___S 0 +#define WMAC0_PDG_R1_TESTBUS_UPPER___M 0x000000FF +#define WMAC0_PDG_R1_TESTBUS_UPPER___S 0 + +#define WMAC0_PDG_R1_SM_STATES_IX_0 (0x00A81014) +#define WMAC0_PDG_R1_SM_STATES_IX_0___RWC QCSR_REG_RO +#define WMAC0_PDG_R1_SM_STATES_IX_0___POR 0x00220841 +#define WMAC0_PDG_R1_SM_STATES_IX_0__D2H_FSM_STATUS___POR 0x01 +#define WMAC0_PDG_R1_SM_STATES_IX_0__H2D_FSM_STATUS___POR 0x1 +#define WMAC0_PDG_R1_SM_STATES_IX_0__TXPCU_FSM_STATUS___POR 0x01 +#define WMAC0_PDG_R1_SM_STATES_IX_0__COMP_FSM_STATUS___POR 0x01 +#define WMAC0_PDG_R1_SM_STATES_IX_0__MAIN_FSM_STATUS___POR 0x01 +#define WMAC0_PDG_R1_SM_STATES_IX_0__D2H_FSM_STATUS___M 0x03E00000 +#define WMAC0_PDG_R1_SM_STATES_IX_0__D2H_FSM_STATUS___S 21 +#define WMAC0_PDG_R1_SM_STATES_IX_0__H2D_FSM_STATUS___M 0x001E0000 +#define WMAC0_PDG_R1_SM_STATES_IX_0__H2D_FSM_STATUS___S 17 +#define WMAC0_PDG_R1_SM_STATES_IX_0__TXPCU_FSM_STATUS___M 0x0001F800 +#define WMAC0_PDG_R1_SM_STATES_IX_0__TXPCU_FSM_STATUS___S 11 +#define WMAC0_PDG_R1_SM_STATES_IX_0__COMP_FSM_STATUS___M 0x000007C0 +#define WMAC0_PDG_R1_SM_STATES_IX_0__COMP_FSM_STATUS___S 6 +#define WMAC0_PDG_R1_SM_STATES_IX_0__MAIN_FSM_STATUS___M 0x0000003F +#define WMAC0_PDG_R1_SM_STATES_IX_0__MAIN_FSM_STATUS___S 0 +#define WMAC0_PDG_R1_SM_STATES_IX_0___M 0x03FFFFFF +#define WMAC0_PDG_R1_SM_STATES_IX_0___S 0 + +#define WMAC0_PDG_R1_IDLE_STATUS (0x00A81018) +#define WMAC0_PDG_R1_IDLE_STATUS___RWC QCSR_REG_RO +#define WMAC0_PDG_R1_IDLE_STATUS___POR 0x000001FF +#define WMAC0_PDG_R1_IDLE_STATUS__PDG_IDLE___POR 0x1 +#define WMAC0_PDG_R1_IDLE_STATUS__AMPDU_IDLE___POR 0x1 +#define WMAC0_PDG_R1_IDLE_STATUS__COMP_IDLE___POR 0x1 +#define WMAC0_PDG_R1_IDLE_STATUS__TXPCU_IF_IDLE___POR 0x1 +#define WMAC0_PDG_R1_IDLE_STATUS__TXPCU_IDLE___POR 0x1 +#define WMAC0_PDG_R1_IDLE_STATUS__D2H_IF_IDLE___POR 0x1 +#define WMAC0_PDG_R1_IDLE_STATUS__D2H_IDLE___POR 0x1 +#define WMAC0_PDG_R1_IDLE_STATUS__H2D_IF_IDLE___POR 0x1 +#define WMAC0_PDG_R1_IDLE_STATUS__H2D_IDLE___POR 0x1 +#define WMAC0_PDG_R1_IDLE_STATUS__PDG_IDLE___M 0x00000100 +#define WMAC0_PDG_R1_IDLE_STATUS__PDG_IDLE___S 8 +#define WMAC0_PDG_R1_IDLE_STATUS__AMPDU_IDLE___M 0x00000080 +#define WMAC0_PDG_R1_IDLE_STATUS__AMPDU_IDLE___S 7 +#define WMAC0_PDG_R1_IDLE_STATUS__COMP_IDLE___M 0x00000040 +#define WMAC0_PDG_R1_IDLE_STATUS__COMP_IDLE___S 6 +#define WMAC0_PDG_R1_IDLE_STATUS__TXPCU_IF_IDLE___M 0x00000020 +#define WMAC0_PDG_R1_IDLE_STATUS__TXPCU_IF_IDLE___S 5 +#define WMAC0_PDG_R1_IDLE_STATUS__TXPCU_IDLE___M 0x00000010 +#define WMAC0_PDG_R1_IDLE_STATUS__TXPCU_IDLE___S 4 +#define WMAC0_PDG_R1_IDLE_STATUS__D2H_IF_IDLE___M 0x00000008 +#define WMAC0_PDG_R1_IDLE_STATUS__D2H_IF_IDLE___S 3 +#define WMAC0_PDG_R1_IDLE_STATUS__D2H_IDLE___M 0x00000004 +#define WMAC0_PDG_R1_IDLE_STATUS__D2H_IDLE___S 2 +#define WMAC0_PDG_R1_IDLE_STATUS__H2D_IF_IDLE___M 0x00000002 +#define WMAC0_PDG_R1_IDLE_STATUS__H2D_IF_IDLE___S 1 +#define WMAC0_PDG_R1_IDLE_STATUS__H2D_IDLE___M 0x00000001 +#define WMAC0_PDG_R1_IDLE_STATUS__H2D_IDLE___S 0 +#define WMAC0_PDG_R1_IDLE_STATUS___M 0x000001FF +#define WMAC0_PDG_R1_IDLE_STATUS___S 0 + +#define WMAC0_PDG_R1_WATCHDOG (0x00A8101C) +#define WMAC0_PDG_R1_WATCHDOG___RWC QCSR_REG_RW +#define WMAC0_PDG_R1_WATCHDOG___POR 0x0000FFFF +#define WMAC0_PDG_R1_WATCHDOG__STATUS___POR 0x0000 +#define WMAC0_PDG_R1_WATCHDOG__LIMIT___POR 0xFFFF +#define WMAC0_PDG_R1_WATCHDOG__STATUS___M 0xFFFF0000 +#define WMAC0_PDG_R1_WATCHDOG__STATUS___S 16 +#define WMAC0_PDG_R1_WATCHDOG__LIMIT___M 0x0000FFFF +#define WMAC0_PDG_R1_WATCHDOG__LIMIT___S 0 +#define WMAC0_PDG_R1_WATCHDOG___M 0xFFFFFFFF +#define WMAC0_PDG_R1_WATCHDOG___S 0 + +#define WMAC0_PDG_R1_TRUNCATE_DEBUG (0x00A81020) +#define WMAC0_PDG_R1_TRUNCATE_DEBUG___RWC QCSR_REG_RO +#define WMAC0_PDG_R1_TRUNCATE_DEBUG___POR 0x00000000 +#define WMAC0_PDG_R1_TRUNCATE_DEBUG__TRUNCATE_REASON_NO_MPDU_FIT___POR 0x0000 +#define WMAC0_PDG_R1_TRUNCATE_DEBUG__TRUNCATE_REASON_TRUNC___POR 0x000 +#define WMAC0_PDG_R1_TRUNCATE_DEBUG__TRUNCATE_REASON_NO_MPDU_FIT___M 0x01FFF000 +#define WMAC0_PDG_R1_TRUNCATE_DEBUG__TRUNCATE_REASON_NO_MPDU_FIT___S 12 +#define WMAC0_PDG_R1_TRUNCATE_DEBUG__TRUNCATE_REASON_TRUNC___M 0x00000FFF +#define WMAC0_PDG_R1_TRUNCATE_DEBUG__TRUNCATE_REASON_TRUNC___S 0 +#define WMAC0_PDG_R1_TRUNCATE_DEBUG___M 0x01FFFFFF +#define WMAC0_PDG_R1_TRUNCATE_DEBUG___S 0 + +#define WMAC0_PDG_R1_INVALID_APB_ACC_ADR (0x00A81024) +#define WMAC0_PDG_R1_INVALID_APB_ACC_ADR___RWC QCSR_REG_RO +#define WMAC0_PDG_R1_INVALID_APB_ACC_ADR___POR 0x00000000 +#define WMAC0_PDG_R1_INVALID_APB_ACC_ADR__VALUE___POR 0x00000 +#define WMAC0_PDG_R1_INVALID_APB_ACC_ADR__VALUE___M 0x0001FFFF +#define WMAC0_PDG_R1_INVALID_APB_ACC_ADR__VALUE___S 0 +#define WMAC0_PDG_R1_INVALID_APB_ACC_ADR___M 0x0001FFFF +#define WMAC0_PDG_R1_INVALID_APB_ACC_ADR___S 0 + +#define WMAC0_PDG_R1_AMPDU_RESULTS_USER (0x00A81028) +#define WMAC0_PDG_R1_AMPDU_RESULTS_USER___RWC QCSR_REG_RW +#define WMAC0_PDG_R1_AMPDU_RESULTS_USER___POR 0x00000000 +#define WMAC0_PDG_R1_AMPDU_RESULTS_USER__NUMBER___POR 0x00 +#define WMAC0_PDG_R1_AMPDU_RESULTS_USER__NUMBER___M 0x0000003F +#define WMAC0_PDG_R1_AMPDU_RESULTS_USER__NUMBER___S 0 +#define WMAC0_PDG_R1_AMPDU_RESULTS_USER___M 0x0000003F +#define WMAC0_PDG_R1_AMPDU_RESULTS_USER___S 0 + +#define WMAC0_PDG_R1_AMPDU_RESULTS (0x00A8102C) +#define WMAC0_PDG_R1_AMPDU_RESULTS___RWC QCSR_REG_RO +#define WMAC0_PDG_R1_AMPDU_RESULTS___POR 0x00000000 +#define WMAC0_PDG_R1_AMPDU_RESULTS__AMPDU_LENGTH___POR 0x000000 +#define WMAC0_PDG_R1_AMPDU_RESULTS__NUM_MPDU___POR 0x000 +#define WMAC0_PDG_R1_AMPDU_RESULTS__AMPDU_LENGTH___M 0xFFFFFE00 +#define WMAC0_PDG_R1_AMPDU_RESULTS__AMPDU_LENGTH___S 9 +#define WMAC0_PDG_R1_AMPDU_RESULTS__NUM_MPDU___M 0x000001FF +#define WMAC0_PDG_R1_AMPDU_RESULTS__NUM_MPDU___S 0 +#define WMAC0_PDG_R1_AMPDU_RESULTS___M 0xFFFFFFFF +#define WMAC0_PDG_R1_AMPDU_RESULTS___S 0 + +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS (0x00A81030) +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS___RWC QCSR_REG_RO +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS___POR 0x00000000 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__NO_TX_FLUSH___POR 0x0 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__LDPC_EXTRA_EXCEED_TXOP___POR 0x0 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__UNEXPECTED_SRP_SR_MODE___POR 0x0 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__TRIG_PRI_WRONG___POR 0x0 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__INVALID_FREQ_CCA_CTS___POR 0x0 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__OFDMA_TRIG_RESP_NO_QOS_NULL_ERROR___POR 0x0 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__RBO_QOS_NULL_ONE_USER_ERROR___POR 0x0 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_MPROT___POR 0x0 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_MPROT___POR 0x0 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_MPROT___POR 0x0 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_MPROT_RESP___POR 0x0 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_MPROT_RESP___POR 0x0 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_MPROT_RESP___POR 0x0 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_PPDU_RESP___POR 0x0 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_PPDU_RESP___POR 0x0 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_PPDU_RESP___POR 0x0 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_PPDU0___POR 0x0 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_PPDU0___POR 0x0 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_PPDU0___POR 0x0 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_HE_SIGB0___POR 0x0 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_HE_SIGB0___POR 0x0 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_HE_SIGB0___POR 0x0 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_HE_SIGB1___POR 0x0 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_HE_SIGB1___POR 0x0 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_HE_SIGB1___POR 0x0 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_RESP___POR 0x0 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_RESP___POR 0x0 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_RESP___POR 0x0 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__TRIG_RESP_LSIG_WRONG___POR 0x0 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__NO_TX_FLUSH___M 0x10000000 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__NO_TX_FLUSH___S 28 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__LDPC_EXTRA_EXCEED_TXOP___M 0x08000000 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__LDPC_EXTRA_EXCEED_TXOP___S 27 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__UNEXPECTED_SRP_SR_MODE___M 0x04000000 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__UNEXPECTED_SRP_SR_MODE___S 26 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__TRIG_PRI_WRONG___M 0x02000000 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__TRIG_PRI_WRONG___S 25 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__INVALID_FREQ_CCA_CTS___M 0x01000000 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__INVALID_FREQ_CCA_CTS___S 24 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__OFDMA_TRIG_RESP_NO_QOS_NULL_ERROR___M 0x00800000 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__OFDMA_TRIG_RESP_NO_QOS_NULL_ERROR___S 23 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__RBO_QOS_NULL_ONE_USER_ERROR___M 0x00400000 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__RBO_QOS_NULL_ONE_USER_ERROR___S 22 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_MPROT___M 0x00200000 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_MPROT___S 21 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_MPROT___M 0x00100000 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_MPROT___S 20 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_MPROT___M 0x00080000 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_MPROT___S 19 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_MPROT_RESP___M 0x00040000 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_MPROT_RESP___S 18 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_MPROT_RESP___M 0x00020000 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_MPROT_RESP___S 17 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_MPROT_RESP___M 0x00010000 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_MPROT_RESP___S 16 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_PPDU_RESP___M 0x00008000 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_PPDU_RESP___S 15 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_PPDU_RESP___M 0x00004000 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_PPDU_RESP___S 14 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_PPDU_RESP___M 0x00002000 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_PPDU_RESP___S 13 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_PPDU0___M 0x00001000 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_PPDU0___S 12 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_PPDU0___M 0x00000800 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_PPDU0___S 11 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_PPDU0___M 0x00000400 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_PPDU0___S 10 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_HE_SIGB0___M 0x00000200 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_HE_SIGB0___S 9 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_HE_SIGB0___M 0x00000100 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_HE_SIGB0___S 8 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_HE_SIGB0___M 0x00000080 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_HE_SIGB0___S 7 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_HE_SIGB1___M 0x00000040 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_HE_SIGB1___S 6 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_HE_SIGB1___M 0x00000020 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_HE_SIGB1___S 5 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_HE_SIGB1___M 0x00000010 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_HE_SIGB1___S 4 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_RESP___M 0x00000008 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__MCS_ERROR_RESP___S 3 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_RESP___M 0x00000004 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__NOT_ALLOWED_ERROR_RESP___S 2 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_RESP___M 0x00000002 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__STBC_DCM_ERROR_RESP___S 1 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__TRIG_RESP_LSIG_WRONG___M 0x00000001 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS__TRIG_RESP_LSIG_WRONG___S 0 +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS___M 0x1FFFFFFF +#define WMAC0_PDG_R1_SETUP_ERROR_STATUS___S 0 + +#define WMAC0_PDG_R1_CLEAR_R1 (0x00A81034) +#define WMAC0_PDG_R1_CLEAR_R1___RWC QCSR_REG_WO +#define WMAC0_PDG_R1_CLEAR_R1___POR 0x00000000 +#define WMAC0_PDG_R1_CLEAR_R1__CLEAR_SETUP_ERROR_STATUS___POR 0x0 +#define WMAC0_PDG_R1_CLEAR_R1__CLEAR_SETUP_ERROR_STATUS___M 0x00000001 +#define WMAC0_PDG_R1_CLEAR_R1__CLEAR_SETUP_ERROR_STATUS___S 0 +#define WMAC0_PDG_R1_CLEAR_R1___M 0x00000001 +#define WMAC0_PDG_R1_CLEAR_R1___S 0 + +#define WMAC0_PDG_R1_MPDU_LIMIT_USER_STATUS (0x00A81038) +#define WMAC0_PDG_R1_MPDU_LIMIT_USER_STATUS___RWC QCSR_REG_RO +#define WMAC0_PDG_R1_MPDU_LIMIT_USER_STATUS___POR 0x00000000 +#define WMAC0_PDG_R1_MPDU_LIMIT_USER_STATUS__USER_NUMBER___POR 0x00 +#define WMAC0_PDG_R1_MPDU_LIMIT_USER_STATUS__USER_NUMBER___M 0x0000003F +#define WMAC0_PDG_R1_MPDU_LIMIT_USER_STATUS__USER_NUMBER___S 0 +#define WMAC0_PDG_R1_MPDU_LIMIT_USER_STATUS___M 0x0000003F +#define WMAC0_PDG_R1_MPDU_LIMIT_USER_STATUS___S 0 + +#define WMAC0_PDG_R1_DEBUG_H2D_COUNTER (0x00A8103C) +#define WMAC0_PDG_R1_DEBUG_H2D_COUNTER___RWC QCSR_REG_RW +#define WMAC0_PDG_R1_DEBUG_H2D_COUNTER___POR 0x00000000 +#define WMAC0_PDG_R1_DEBUG_H2D_COUNTER__COEX_TX_RESP___POR 0x00 +#define WMAC0_PDG_R1_DEBUG_H2D_COUNTER__TX_FES_SETUP___POR 0x00 +#define WMAC0_PDG_R1_DEBUG_H2D_COUNTER__COEX_TX_RESP___M 0x0000FF00 +#define WMAC0_PDG_R1_DEBUG_H2D_COUNTER__COEX_TX_RESP___S 8 +#define WMAC0_PDG_R1_DEBUG_H2D_COUNTER__TX_FES_SETUP___M 0x000000FF +#define WMAC0_PDG_R1_DEBUG_H2D_COUNTER__TX_FES_SETUP___S 0 +#define WMAC0_PDG_R1_DEBUG_H2D_COUNTER___M 0x0000FFFF +#define WMAC0_PDG_R1_DEBUG_H2D_COUNTER___S 0 + +#define WMAC0_PDG_R1_DEBUG_D2H_COUNTER (0x00A81040) +#define WMAC0_PDG_R1_DEBUG_D2H_COUNTER___RWC QCSR_REG_RW +#define WMAC0_PDG_R1_DEBUG_D2H_COUNTER___POR 0x00000000 +#define WMAC0_PDG_R1_DEBUG_D2H_COUNTER__PDG_RESPONSE___POR 0x00 +#define WMAC0_PDG_R1_DEBUG_D2H_COUNTER__OFDM_TRIGGER_DETAILS___POR 0x00 +#define WMAC0_PDG_R1_DEBUG_D2H_COUNTER__PDG_TX_REQ___POR 0x00 +#define WMAC0_PDG_R1_DEBUG_D2H_COUNTER__PPDU_HEADER_INFO_REQ___POR 0x00 +#define WMAC0_PDG_R1_DEBUG_D2H_COUNTER__PDG_RESPONSE___M 0xFF000000 +#define WMAC0_PDG_R1_DEBUG_D2H_COUNTER__PDG_RESPONSE___S 24 +#define WMAC0_PDG_R1_DEBUG_D2H_COUNTER__OFDM_TRIGGER_DETAILS___M 0x00FF0000 +#define WMAC0_PDG_R1_DEBUG_D2H_COUNTER__OFDM_TRIGGER_DETAILS___S 16 +#define WMAC0_PDG_R1_DEBUG_D2H_COUNTER__PDG_TX_REQ___M 0x0000FF00 +#define WMAC0_PDG_R1_DEBUG_D2H_COUNTER__PDG_TX_REQ___S 8 +#define WMAC0_PDG_R1_DEBUG_D2H_COUNTER__PPDU_HEADER_INFO_REQ___M 0x000000FF +#define WMAC0_PDG_R1_DEBUG_D2H_COUNTER__PPDU_HEADER_INFO_REQ___S 0 +#define WMAC0_PDG_R1_DEBUG_D2H_COUNTER___M 0xFFFFFFFF +#define WMAC0_PDG_R1_DEBUG_D2H_COUNTER___S 0 + +#define WMAC0_PDG_R1_DEBUG_PROT_TX_REQ_COUNTER (0x00A81044) +#define WMAC0_PDG_R1_DEBUG_PROT_TX_REQ_COUNTER___RWC QCSR_REG_RW +#define WMAC0_PDG_R1_DEBUG_PROT_TX_REQ_COUNTER___POR 0x00000000 +#define WMAC0_PDG_R1_DEBUG_PROT_TX_REQ_COUNTER__VALUE___POR 0x0000 +#define WMAC0_PDG_R1_DEBUG_PROT_TX_REQ_COUNTER__VALUE___M 0x0000FFFF +#define WMAC0_PDG_R1_DEBUG_PROT_TX_REQ_COUNTER__VALUE___S 0 +#define WMAC0_PDG_R1_DEBUG_PROT_TX_REQ_COUNTER___M 0x0000FFFF +#define WMAC0_PDG_R1_DEBUG_PROT_TX_REQ_COUNTER___S 0 + +#define WMAC0_PDG_R1_DEBUG_PROT_TX_NO_ACK_COUNTER (0x00A81048) +#define WMAC0_PDG_R1_DEBUG_PROT_TX_NO_ACK_COUNTER___RWC QCSR_REG_RW +#define WMAC0_PDG_R1_DEBUG_PROT_TX_NO_ACK_COUNTER___POR 0x00000000 +#define WMAC0_PDG_R1_DEBUG_PROT_TX_NO_ACK_COUNTER__VALUE___POR 0x0000 +#define WMAC0_PDG_R1_DEBUG_PROT_TX_NO_ACK_COUNTER__VALUE___M 0x0000FFFF +#define WMAC0_PDG_R1_DEBUG_PROT_TX_NO_ACK_COUNTER__VALUE___S 0 +#define WMAC0_PDG_R1_DEBUG_PROT_TX_NO_ACK_COUNTER___M 0x0000FFFF +#define WMAC0_PDG_R1_DEBUG_PROT_TX_NO_ACK_COUNTER___S 0 + +#define WMAC0_PDG_R1_DEBUG_PROT_TX_ALT_COUNTER (0x00A8104C) +#define WMAC0_PDG_R1_DEBUG_PROT_TX_ALT_COUNTER___RWC QCSR_REG_RW +#define WMAC0_PDG_R1_DEBUG_PROT_TX_ALT_COUNTER___POR 0x00000000 +#define WMAC0_PDG_R1_DEBUG_PROT_TX_ALT_COUNTER__VALUE___POR 0x0000 +#define WMAC0_PDG_R1_DEBUG_PROT_TX_ALT_COUNTER__VALUE___M 0x0000FFFF +#define WMAC0_PDG_R1_DEBUG_PROT_TX_ALT_COUNTER__VALUE___S 0 +#define WMAC0_PDG_R1_DEBUG_PROT_TX_ALT_COUNTER___M 0x0000FFFF +#define WMAC0_PDG_R1_DEBUG_PROT_TX_ALT_COUNTER___S 0 + +#define WMAC0_PDG_R1_DEBUG_PPDU_TX_REQ_COUNTER (0x00A81050) +#define WMAC0_PDG_R1_DEBUG_PPDU_TX_REQ_COUNTER___RWC QCSR_REG_RW +#define WMAC0_PDG_R1_DEBUG_PPDU_TX_REQ_COUNTER___POR 0x00000000 +#define WMAC0_PDG_R1_DEBUG_PPDU_TX_REQ_COUNTER__VALUE___POR 0x000000 +#define WMAC0_PDG_R1_DEBUG_PPDU_TX_REQ_COUNTER__VALUE___M 0x00FFFFFF +#define WMAC0_PDG_R1_DEBUG_PPDU_TX_REQ_COUNTER__VALUE___S 0 +#define WMAC0_PDG_R1_DEBUG_PPDU_TX_REQ_COUNTER___M 0x00FFFFFF +#define WMAC0_PDG_R1_DEBUG_PPDU_TX_REQ_COUNTER___S 0 + +#define WMAC0_PDG_R1_DEBUG_PPDU_TX_NO_ACK_COUNTER (0x00A81054) +#define WMAC0_PDG_R1_DEBUG_PPDU_TX_NO_ACK_COUNTER___RWC QCSR_REG_RW +#define WMAC0_PDG_R1_DEBUG_PPDU_TX_NO_ACK_COUNTER___POR 0x00000000 +#define WMAC0_PDG_R1_DEBUG_PPDU_TX_NO_ACK_COUNTER__VALUE___POR 0x000000 +#define WMAC0_PDG_R1_DEBUG_PPDU_TX_NO_ACK_COUNTER__VALUE___M 0x00FFFFFF +#define WMAC0_PDG_R1_DEBUG_PPDU_TX_NO_ACK_COUNTER__VALUE___S 0 +#define WMAC0_PDG_R1_DEBUG_PPDU_TX_NO_ACK_COUNTER___M 0x00FFFFFF +#define WMAC0_PDG_R1_DEBUG_PPDU_TX_NO_ACK_COUNTER___S 0 + +#define WMAC0_PDG_R1_DEBUG_PPDU_TX_ALT_COUNTER (0x00A81058) +#define WMAC0_PDG_R1_DEBUG_PPDU_TX_ALT_COUNTER___RWC QCSR_REG_RW +#define WMAC0_PDG_R1_DEBUG_PPDU_TX_ALT_COUNTER___POR 0x00000000 +#define WMAC0_PDG_R1_DEBUG_PPDU_TX_ALT_COUNTER__VALUE___POR 0x000000 +#define WMAC0_PDG_R1_DEBUG_PPDU_TX_ALT_COUNTER__VALUE___M 0x00FFFFFF +#define WMAC0_PDG_R1_DEBUG_PPDU_TX_ALT_COUNTER__VALUE___S 0 +#define WMAC0_PDG_R1_DEBUG_PPDU_TX_ALT_COUNTER___M 0x00FFFFFF +#define WMAC0_PDG_R1_DEBUG_PPDU_TX_ALT_COUNTER___S 0 + +#define WMAC0_PDG_R1_DEBUG_RESP_TX_REQ_COUNTER (0x00A8105C) +#define WMAC0_PDG_R1_DEBUG_RESP_TX_REQ_COUNTER___RWC QCSR_REG_RW +#define WMAC0_PDG_R1_DEBUG_RESP_TX_REQ_COUNTER___POR 0x00000000 +#define WMAC0_PDG_R1_DEBUG_RESP_TX_REQ_COUNTER__VALUE___POR 0x000000 +#define WMAC0_PDG_R1_DEBUG_RESP_TX_REQ_COUNTER__VALUE___M 0x00FFFFFF +#define WMAC0_PDG_R1_DEBUG_RESP_TX_REQ_COUNTER__VALUE___S 0 +#define WMAC0_PDG_R1_DEBUG_RESP_TX_REQ_COUNTER___M 0x00FFFFFF +#define WMAC0_PDG_R1_DEBUG_RESP_TX_REQ_COUNTER___S 0 + +#define WMAC0_PDG_R1_DEBUG_RESP_TX_NO_ACK_COUNTER (0x00A81060) +#define WMAC0_PDG_R1_DEBUG_RESP_TX_NO_ACK_COUNTER___RWC QCSR_REG_RW +#define WMAC0_PDG_R1_DEBUG_RESP_TX_NO_ACK_COUNTER___POR 0x00000000 +#define WMAC0_PDG_R1_DEBUG_RESP_TX_NO_ACK_COUNTER__VALUE___POR 0x000000 +#define WMAC0_PDG_R1_DEBUG_RESP_TX_NO_ACK_COUNTER__VALUE___M 0x00FFFFFF +#define WMAC0_PDG_R1_DEBUG_RESP_TX_NO_ACK_COUNTER__VALUE___S 0 +#define WMAC0_PDG_R1_DEBUG_RESP_TX_NO_ACK_COUNTER___M 0x00FFFFFF +#define WMAC0_PDG_R1_DEBUG_RESP_TX_NO_ACK_COUNTER___S 0 + +#define WMAC0_PDG_R1_DEBUG_RESP_TX_ALT_COUNTER (0x00A81064) +#define WMAC0_PDG_R1_DEBUG_RESP_TX_ALT_COUNTER___RWC QCSR_REG_RW +#define WMAC0_PDG_R1_DEBUG_RESP_TX_ALT_COUNTER___POR 0x00000000 +#define WMAC0_PDG_R1_DEBUG_RESP_TX_ALT_COUNTER__VALUE___POR 0x000000 +#define WMAC0_PDG_R1_DEBUG_RESP_TX_ALT_COUNTER__VALUE___M 0x00FFFFFF +#define WMAC0_PDG_R1_DEBUG_RESP_TX_ALT_COUNTER__VALUE___S 0 +#define WMAC0_PDG_R1_DEBUG_RESP_TX_ALT_COUNTER___M 0x00FFFFFF +#define WMAC0_PDG_R1_DEBUG_RESP_TX_ALT_COUNTER___S 0 + +#define WMAC0_PDG_R1_CLEAR_DEBUG_COUNTERS (0x00A81068) +#define WMAC0_PDG_R1_CLEAR_DEBUG_COUNTERS___RWC QCSR_REG_RW +#define WMAC0_PDG_R1_CLEAR_DEBUG_COUNTERS___POR 0x00000000 +#define WMAC0_PDG_R1_CLEAR_DEBUG_COUNTERS__CLEAR_DEBUG_COUNTER___POR 0x0 +#define WMAC0_PDG_R1_CLEAR_DEBUG_COUNTERS__CLEAR_DEBUG_COUNTER___M 0x00000001 +#define WMAC0_PDG_R1_CLEAR_DEBUG_COUNTERS__CLEAR_DEBUG_COUNTER___S 0 +#define WMAC0_PDG_R1_CLEAR_DEBUG_COUNTERS___M 0x00000001 +#define WMAC0_PDG_R1_CLEAR_DEBUG_COUNTERS___S 0 + +#define WMAC0_PDG_R1_COEX_DEBUG (0x00A8106C) +#define WMAC0_PDG_R1_COEX_DEBUG___RWC QCSR_REG_RO +#define WMAC0_PDG_R1_COEX_DEBUG___POR 0x00000000 +#define WMAC0_PDG_R1_COEX_DEBUG__MCS_RED_CNT___POR 0x00 +#define WMAC0_PDG_R1_COEX_DEBUG__PWR_RED_CNT___POR 0x00 +#define WMAC0_PDG_R1_COEX_DEBUG__BW_RED_CNT___POR 0x00 +#define WMAC0_PDG_R1_COEX_DEBUG__ANT_RED_CNT___POR 0x00 +#define WMAC0_PDG_R1_COEX_DEBUG__MCS_RED_CNT___M 0xFF000000 +#define WMAC0_PDG_R1_COEX_DEBUG__MCS_RED_CNT___S 24 +#define WMAC0_PDG_R1_COEX_DEBUG__PWR_RED_CNT___M 0x00FF0000 +#define WMAC0_PDG_R1_COEX_DEBUG__PWR_RED_CNT___S 16 +#define WMAC0_PDG_R1_COEX_DEBUG__BW_RED_CNT___M 0x0000FF00 +#define WMAC0_PDG_R1_COEX_DEBUG__BW_RED_CNT___S 8 +#define WMAC0_PDG_R1_COEX_DEBUG__ANT_RED_CNT___M 0x000000FF +#define WMAC0_PDG_R1_COEX_DEBUG__ANT_RED_CNT___S 0 +#define WMAC0_PDG_R1_COEX_DEBUG___M 0xFFFFFFFF +#define WMAC0_PDG_R1_COEX_DEBUG___S 0 + +#define WMAC0_PDG_R1_COEX_DEBUG2 (0x00A81070) +#define WMAC0_PDG_R1_COEX_DEBUG2___RWC QCSR_REG_RO +#define WMAC0_PDG_R1_COEX_DEBUG2___POR 0x00000000 +#define WMAC0_PDG_R1_COEX_DEBUG2__RXWINDOW_RED_CNT___POR 0x00 +#define WMAC0_PDG_R1_COEX_DEBUG2__TXWINDOW_RED_CNT___POR 0x00 +#define WMAC0_PDG_R1_COEX_DEBUG2__RXWINDOW_RED_CNT___M 0x0000FF00 +#define WMAC0_PDG_R1_COEX_DEBUG2__RXWINDOW_RED_CNT___S 8 +#define WMAC0_PDG_R1_COEX_DEBUG2__TXWINDOW_RED_CNT___M 0x000000FF +#define WMAC0_PDG_R1_COEX_DEBUG2__TXWINDOW_RED_CNT___S 0 +#define WMAC0_PDG_R1_COEX_DEBUG2___M 0x0000FFFF +#define WMAC0_PDG_R1_COEX_DEBUG2___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_MSDU_INFO_FETCH_CFG (0x00A83000) +#define WMAC0_TXDMA_TXDMA_R0_MSDU_INFO_FETCH_CFG___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_MSDU_INFO_FETCH_CFG___POR 0x00000005 +#define WMAC0_TXDMA_TXDMA_R0_MSDU_INFO_FETCH_CFG__MAX_FRAG_TABLE_ENTRIES___POR 0x5 +#define WMAC0_TXDMA_TXDMA_R0_MSDU_INFO_FETCH_CFG__MAX_FRAG_TABLE_ENTRIES___M 0x00000007 +#define WMAC0_TXDMA_TXDMA_R0_MSDU_INFO_FETCH_CFG__MAX_FRAG_TABLE_ENTRIES___S 0 +#define WMAC0_TXDMA_TXDMA_R0_MSDU_INFO_FETCH_CFG___M 0x00000007 +#define WMAC0_TXDMA_TXDMA_R0_MSDU_INFO_FETCH_CFG___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_TXDATA_FETCH_CFG (0x00A83004) +#define WMAC0_TXDMA_TXDMA_R0_TXDATA_FETCH_CFG___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_TXDATA_FETCH_CFG___POR 0x00000314 +#define WMAC0_TXDMA_TXDMA_R0_TXDATA_FETCH_CFG__DISABLE_SPACE_AWARE_DMA___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_TXDATA_FETCH_CFG__MARGIN_OLE_CMD_FIFO_AVAIL_ENTRIES___POR 0x03 +#define WMAC0_TXDMA_TXDMA_R0_TXDATA_FETCH_CFG__MARGIN_OLE_BUF_AVAIL_DWORDS___POR 0x14 +#define WMAC0_TXDMA_TXDMA_R0_TXDATA_FETCH_CFG__DISABLE_SPACE_AWARE_DMA___M 0x00004000 +#define WMAC0_TXDMA_TXDMA_R0_TXDATA_FETCH_CFG__DISABLE_SPACE_AWARE_DMA___S 14 +#define WMAC0_TXDMA_TXDMA_R0_TXDATA_FETCH_CFG__MARGIN_OLE_CMD_FIFO_AVAIL_ENTRIES___M 0x00003F00 +#define WMAC0_TXDMA_TXDMA_R0_TXDATA_FETCH_CFG__MARGIN_OLE_CMD_FIFO_AVAIL_ENTRIES___S 8 +#define WMAC0_TXDMA_TXDMA_R0_TXDATA_FETCH_CFG__MARGIN_OLE_BUF_AVAIL_DWORDS___M 0x000000FF +#define WMAC0_TXDMA_TXDMA_R0_TXDATA_FETCH_CFG__MARGIN_OLE_BUF_AVAIL_DWORDS___S 0 +#define WMAC0_TXDMA_TXDMA_R0_TXDATA_FETCH_CFG___M 0x00007FFF +#define WMAC0_TXDMA_TXDMA_R0_TXDATA_FETCH_CFG___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_ERROR_OLE_CFG (0x00A83008) +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_ERROR_OLE_CFG___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_ERROR_OLE_CFG___POR 0x0000007F +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_ERROR_OLE_CFG__OLE_TIMEOUT_LIMIT___POR 0x7F +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_ERROR_OLE_CFG__OLE_TIMEOUT_LIMIT___M 0x000000FF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_ERROR_OLE_CFG__OLE_TIMEOUT_LIMIT___S 0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_ERROR_OLE_CFG___M 0x000000FF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_ERROR_OLE_CFG___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_WATCHDOG (0x00A8300C) +#define WMAC0_TXDMA_TXDMA_R0_WATCHDOG___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_WATCHDOG___POR 0x0000FFFF +#define WMAC0_TXDMA_TXDMA_R0_WATCHDOG__STATUS___POR 0x0000 +#define WMAC0_TXDMA_TXDMA_R0_WATCHDOG__LIMIT___POR 0xFFFF +#define WMAC0_TXDMA_TXDMA_R0_WATCHDOG__STATUS___M 0xFFFF0000 +#define WMAC0_TXDMA_TXDMA_R0_WATCHDOG__STATUS___S 16 +#define WMAC0_TXDMA_TXDMA_R0_WATCHDOG__LIMIT___M 0x0000FFFF +#define WMAC0_TXDMA_TXDMA_R0_WATCHDOG__LIMIT___S 0 +#define WMAC0_TXDMA_TXDMA_R0_WATCHDOG___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R0_WATCHDOG___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_CRYPTO_STATUS (0x00A83010) +#define WMAC0_TXDMA_TXDMA_R0_CRYPTO_STATUS___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_CRYPTO_STATUS___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_CRYPTO_STATUS__BYPASS___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_CRYPTO_STATUS__BYPASS___M 0x00000001 +#define WMAC0_TXDMA_TXDMA_R0_CRYPTO_STATUS__BYPASS___S 0 +#define WMAC0_TXDMA_TXDMA_R0_CRYPTO_STATUS___M 0x00000001 +#define WMAC0_TXDMA_TXDMA_R0_CRYPTO_STATUS___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP (0x00A83020) +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_SW4_BM___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_SW3_BM___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_SW2_BM___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_SW1_BM___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_SW0_BM___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_FW_BM___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_WBM_DESC_L___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_WBM_BUF_L___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_SW4_BM___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_SW3_BM___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_SW2_BM___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_SW1_BM___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_SW0_BM___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_FW_BM___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_WBM_DESC_L___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_WBM_BUF_L___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_SW4_BM___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_SW3_BM___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_SW2_BM___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_SW1_BM___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_SW0_BM___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_FW_BM___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_WBM_DESC_L___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_WBM_BUF_L___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_SW4_BM___M 0x00800000 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_SW4_BM___S 23 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_SW3_BM___M 0x00400000 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_SW3_BM___S 22 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_SW2_BM___M 0x00200000 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_SW2_BM___S 21 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_SW1_BM___M 0x00100000 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_SW1_BM___S 20 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_SW0_BM___M 0x00080000 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_SW0_BM___S 19 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_FW_BM___M 0x00040000 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_FW_BM___S 18 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_WBM_DESC_L___M 0x00020000 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_WBM_DESC_L___S 17 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_WBM_BUF_L___M 0x00010000 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_EXT_WBM_BUF_L___S 16 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_SW4_BM___M 0x00008000 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_SW4_BM___S 15 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_SW3_BM___M 0x00004000 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_SW3_BM___S 14 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_SW2_BM___M 0x00002000 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_SW2_BM___S 13 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_SW1_BM___M 0x00001000 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_SW1_BM___S 12 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_SW0_BM___M 0x00000800 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_SW0_BM___S 11 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_FW_BM___M 0x00000400 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_FW_BM___S 10 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_WBM_DESC_L___M 0x00000200 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_WBM_DESC_L___S 9 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_WBM_BUF_L___M 0x00000100 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__LINK_WBM_BUF_L___S 8 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_SW4_BM___M 0x00000080 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_SW4_BM___S 7 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_SW3_BM___M 0x00000040 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_SW3_BM___S 6 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_SW2_BM___M 0x00000020 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_SW2_BM___S 5 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_SW1_BM___M 0x00000010 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_SW1_BM___S 4 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_SW0_BM___M 0x00000008 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_SW0_BM___S 3 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_FW_BM___M 0x00000004 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_FW_BM___S 2 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_WBM_DESC_L___M 0x00000002 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_WBM_DESC_L___S 1 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_WBM_BUF_L___M 0x00000001 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP__DATA_WBM_BUF_L___S 0 +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP___M 0x00FFFFFF +#define WMAC0_TXDMA_TXDMA_R0_CFG_SWAP___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_ERROR_GXI_CFG (0x00A83050) +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_ERROR_GXI_CFG___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_ERROR_GXI_CFG___POR 0x000000FF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_ERROR_GXI_CFG__GXI_TIMEOUT_LIMIT___POR 0x00FF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_ERROR_GXI_CFG__GXI_TIMEOUT_LIMIT___M 0x0000FFFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_ERROR_GXI_CFG__GXI_TIMEOUT_LIMIT___S 0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_ERROR_GXI_CFG___M 0x0000FFFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_ERROR_GXI_CFG___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_DISABLE (0x00A83054) +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_DISABLE___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_DISABLE___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_DISABLE__RTLPA_VAL___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_DISABLE__MEM_VAL___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_DISABLE__VAL___POR 0x00 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_DISABLE__RTLPA_VAL___M 0x00000040 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_DISABLE__RTLPA_VAL___S 6 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_DISABLE__MEM_VAL___M 0x00000020 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_DISABLE__MEM_VAL___S 5 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_DISABLE__VAL___M 0x0000001F +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_DISABLE__VAL___S 0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_DISABLE___M 0x0000007F +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_DISABLE___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_GXI_TRANS_LIMIT_NU (0x00A83058) +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_GXI_TRANS_LIMIT_NU___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_GXI_TRANS_LIMIT_NU___POR 0x00000010 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_GXI_TRANS_LIMIT_NU__VAL___POR 0x0010 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_GXI_TRANS_LIMIT_NU__VAL___M 0x0000FFFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_GXI_TRANS_LIMIT_NU__VAL___S 0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_GXI_TRANS_LIMIT_NU___M 0x0000FFFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_GXI_TRANS_LIMIT_NU___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_GXI_TRANS_LIMIT_SIZE (0x00A8305C) +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_GXI_TRANS_LIMIT_SIZE___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_GXI_TRANS_LIMIT_SIZE___POR 0x00000FFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_GXI_TRANS_LIMIT_SIZE__VAL___POR 0x00000FFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_GXI_TRANS_LIMIT_SIZE__VAL___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_GXI_TRANS_LIMIT_SIZE__VAL___S 0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_GXI_TRANS_LIMIT_SIZE___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_GXI_TRANS_LIMIT_SIZE___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_INVALID_APB_ACC_ADR (0x00A8306C) +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_INVALID_APB_ACC_ADR___RWC QCSR_REG_RO +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_INVALID_APB_ACC_ADR___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_INVALID_APB_ACC_ADR__VALUE___POR 0x00000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_INVALID_APB_ACC_ADR__VALUE___M 0x0001FFFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_INVALID_APB_ACC_ADR__VALUE___S 0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_INVALID_APB_ACC_ADR___M 0x0001FFFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_INVALID_APB_ACC_ADR___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_CLK_EXTEND (0x00A83084) +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_CLK_EXTEND___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_CLK_EXTEND___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_CLK_EXTEND__VAL___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_CLK_EXTEND__VAL___M 0x00000001 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_CLK_EXTEND__VAL___S 0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_CLK_EXTEND___M 0x00000001 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_CLK_GATE_CLK_EXTEND___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1 (0x00A83088) +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1___POR 0x10285003 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__FST_BUF_SIZE_CHK___POR 0x1 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__BYPASS_MSDU_START_END___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__DA_SA_PRESENT___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__ENCAP_TYPE___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__WDS___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__MIN_LST_PKT_SIZE___POR 0x50 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__MIN_FST_PKT_SIZE___POR 0x50 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__INIT_TXPCU_SPACE_THR___POR 0x03 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__FST_BUF_SIZE_CHK___M 0x10000000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__FST_BUF_SIZE_CHK___S 28 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__BYPASS_MSDU_START_END___M 0x08000000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__BYPASS_MSDU_START_END___S 27 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__DA_SA_PRESENT___M 0x06000000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__DA_SA_PRESENT___S 25 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__ENCAP_TYPE___M 0x01800000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__ENCAP_TYPE___S 23 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__WDS___M 0x00400000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__WDS___S 22 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__MIN_LST_PKT_SIZE___M 0x003F8000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__MIN_LST_PKT_SIZE___S 15 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__MIN_FST_PKT_SIZE___M 0x00007F00 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__MIN_FST_PKT_SIZE___S 8 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__INIT_TXPCU_SPACE_THR___M 0x000000FF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1__INIT_TXPCU_SPACE_THR___S 0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1___M 0x1FFFFFFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG1___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG2 (0x00A8308C) +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG2___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG2___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG2__LINK_EXT_PAYLOAD_END_OFFSET___POR 0x0000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG2__LINK_EXT_PAYLOAD_START_OFFSET___POR 0x0000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG2__LINK_EXT_PAYLOAD_END_OFFSET___M 0x0FFFC000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG2__LINK_EXT_PAYLOAD_END_OFFSET___S 14 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG2__LINK_EXT_PAYLOAD_START_OFFSET___M 0x00003FFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG2__LINK_EXT_PAYLOAD_START_OFFSET___S 0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG2___M 0x0FFFFFFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG2___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG3 (0x00A83090) +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG3___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG3___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG3__LINK_EXT_IP_IDENTIFICATION___POR 0x0000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG3__LINK_EXT_PARTIAL_CHECKSUM_EN___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG3__LINK_EXT_CHECKSUM_OFFSET___POR 0x0000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG3__LINK_EXT_IP_IDENTIFICATION___M 0x7FFF8000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG3__LINK_EXT_IP_IDENTIFICATION___S 15 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG3__LINK_EXT_PARTIAL_CHECKSUM_EN___M 0x00004000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG3__LINK_EXT_PARTIAL_CHECKSUM_EN___S 14 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG3__LINK_EXT_CHECKSUM_OFFSET___M 0x00003FFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG3__LINK_EXT_CHECKSUM_OFFSET___S 0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG3___M 0x7FFFFFFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG3___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG4 (0x00A83094) +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG4___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG4___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG4__LINK_EXT_TCP_SEQ_NUMBER___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG4__LINK_EXT_TCP_SEQ_NUMBER___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG4__LINK_EXT_TCP_SEQ_NUMBER___S 0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG4___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG4___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG5 (0x00A83098) +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG5___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG5___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG5__LINK_EXT_IP_LENGTH___POR 0x0000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG5__LINK_EXT_L2_LENGTH___POR 0x0000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG5__LINK_EXT_IP_LENGTH___M 0xFFFF0000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG5__LINK_EXT_IP_LENGTH___S 16 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG5__LINK_EXT_L2_LENGTH___M 0x0000FFFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG5__LINK_EXT_L2_LENGTH___S 0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG5___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG5___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG6 (0x00A8309C) +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG6___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG6___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG6__LINK_EXT_TSO_ENABLE___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG6__LINK_EXT_TCP_FLAG___POR 0x000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG6__LINK_EXT_TCP_FLAG_MASK___POR 0x000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG6__LINK_EXT_TSO_ENABLE___M 0x00040000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG6__LINK_EXT_TSO_ENABLE___S 18 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG6__LINK_EXT_TCP_FLAG___M 0x0003FE00 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG6__LINK_EXT_TCP_FLAG___S 9 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG6__LINK_EXT_TCP_FLAG_MASK___M 0x000001FF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG6__LINK_EXT_TCP_FLAG_MASK___S 0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG6___M 0x0007FFFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG6___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG7 (0x00A830A0) +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG7___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG7___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG7__UDP_LENGTH___POR 0x0000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG7__UDP_LENGTH___M 0x0000FFFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG7__UDP_LENGTH___S 0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG7___M 0x0000FFFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_MSDU_START_CFG7___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_FLUSH_PER_USR (0x00A830A4) +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_FLUSH_PER_USR___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_FLUSH_PER_USR___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_FLUSH_PER_USR__ENABLE___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_FLUSH_PER_USR__ENABLE___M 0x00000001 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_FLUSH_PER_USR__ENABLE___S 0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_FLUSH_PER_USR___M 0x00000001 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_FLUSH_PER_USR___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG (0x00A830A8) +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG___POR 0x00008000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__WAIT_FOR_BW_INFO___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__BW_RESTRICTION_EN___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__NO_DATA_WAIT___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__SFM_USR_KEEP_BUGFIX_EN___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__GROUP_SWITCH_EN___POR 0x1 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__ENABLE___POR 0x0000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__WAIT_FOR_BW_INFO___M 0x00080000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__WAIT_FOR_BW_INFO___S 19 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__BW_RESTRICTION_EN___M 0x00040000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__BW_RESTRICTION_EN___S 18 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__NO_DATA_WAIT___M 0x00020000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__NO_DATA_WAIT___S 17 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__SFM_USR_KEEP_BUGFIX_EN___M 0x00010000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__SFM_USR_KEEP_BUGFIX_EN___S 16 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__GROUP_SWITCH_EN___M 0x00008000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__GROUP_SWITCH_EN___S 15 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__ENABLE___M 0x00007FFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG__ENABLE___S 0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG___M 0x000FFFFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_BK_CFG___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG (0x00A830AC) +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG__WRITE_REQ_THRESHOLD___POR 0x0000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG__SNOOP_MSDU_DATA_CNT___POR 0x00 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG__SNOOP_MSDU_DATA_OFFSET_VALUE___POR 0x00 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG__ENABLE___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG__WRITE_REQ_THRESHOLD___M 0x7FFF0000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG__WRITE_REQ_THRESHOLD___S 16 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG__SNOOP_MSDU_DATA_CNT___M 0x00007F00 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG__SNOOP_MSDU_DATA_CNT___S 8 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG__SNOOP_MSDU_DATA_OFFSET_VALUE___M 0x000000FE +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG__SNOOP_MSDU_DATA_OFFSET_VALUE___S 1 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG__ENABLE___M 0x00000001 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG__ENABLE___S 0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG___M 0x7FFF7FFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG_1 (0x00A830B0) +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG_1___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG_1___POR 0x00200000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG_1__NON_POSTED_TLV_CNT_THRSH___POR 0x010 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG_1__SNOOP_TLV_OFFSET_VAL___POR 0x00 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG_1__SNOOP_TAG_ID___POR 0x000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG_1__NON_POSTED_TLV_CNT_THRSH___M 0x1FFE0000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG_1__NON_POSTED_TLV_CNT_THRSH___S 17 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG_1__SNOOP_TLV_OFFSET_VAL___M 0x0001FC00 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG_1__SNOOP_TLV_OFFSET_VAL___S 10 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG_1__SNOOP_TAG_ID___M 0x000003FF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG_1__SNOOP_TAG_ID___S 0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG_1___M 0x1FFFFFFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_CFG_1___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_1 (0x00A830B4) +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_1___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_1___POR 0x000003FE +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_1__SPARE_TLV_USERID___POR 0x00 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_1__SPARE_TLV_TAG___POR 0x1FF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_1__SPARE_TLV_ENA___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_1__SPARE_TLV_USERID___M 0x0000FC00 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_1__SPARE_TLV_USERID___S 10 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_1__SPARE_TLV_TAG___M 0x000003FE +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_1__SPARE_TLV_TAG___S 1 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_1__SPARE_TLV_ENA___M 0x00000001 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_1__SPARE_TLV_ENA___S 0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_1___M 0x0000FFFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_1___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_2 (0x00A830B8) +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_2___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_2___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_2__SNOOP_SPARE_TLV_BITMAP_MSK___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_2__SNOOP_SPARE_TLV_BITMAP_MSK___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_2__SNOOP_SPARE_TLV_BITMAP_MSK___S 0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_2___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SPARE_TLV_CFG_2___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_UCODE_SNOOP_WATCHDOG_TIMEOUT_STATUS (0x00A830C8) +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_UCODE_SNOOP_WATCHDOG_TIMEOUT_STATUS___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_UCODE_SNOOP_WATCHDOG_TIMEOUT_STATUS___POR 0x0000FFFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_UCODE_SNOOP_WATCHDOG_TIMEOUT_STATUS__UCODE_WDOG_STATUS___POR 0x0000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_UCODE_SNOOP_WATCHDOG_TIMEOUT_STATUS__UCODE_WDOG_TIMEOUT___POR 0xFFFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_UCODE_SNOOP_WATCHDOG_TIMEOUT_STATUS__UCODE_WDOG_STATUS___M 0xFFFF0000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_UCODE_SNOOP_WATCHDOG_TIMEOUT_STATUS__UCODE_WDOG_STATUS___S 16 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_UCODE_SNOOP_WATCHDOG_TIMEOUT_STATUS__UCODE_WDOG_TIMEOUT___M 0x0000FFFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_UCODE_SNOOP_WATCHDOG_TIMEOUT_STATUS__UCODE_WDOG_TIMEOUT___S 0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_UCODE_SNOOP_WATCHDOG_TIMEOUT_STATUS___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_UCODE_SNOOP_WATCHDOG_TIMEOUT_STATUS___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_WATCHDOG_TIMEOUT_STATUS (0x00A830CC) +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_WATCHDOG_TIMEOUT_STATUS___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_WATCHDOG_TIMEOUT_STATUS___POR 0x0000FFFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_WATCHDOG_TIMEOUT_STATUS__SNOOP_WDOG_STATUS___POR 0x0000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_WATCHDOG_TIMEOUT_STATUS__SNOOP_WDOG_TIMEOUT___POR 0xFFFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_WATCHDOG_TIMEOUT_STATUS__SNOOP_WDOG_STATUS___M 0xFFFF0000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_WATCHDOG_TIMEOUT_STATUS__SNOOP_WDOG_STATUS___S 16 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_WATCHDOG_TIMEOUT_STATUS__SNOOP_WDOG_TIMEOUT___M 0x0000FFFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_WATCHDOG_TIMEOUT_STATUS__SNOOP_WDOG_TIMEOUT___S 0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_WATCHDOG_TIMEOUT_STATUS___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_WATCHDOG_TIMEOUT_STATUS___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SRNG_WATCHDOG_TIMEOUT (0x00A830D0) +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SRNG_WATCHDOG_TIMEOUT___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SRNG_WATCHDOG_TIMEOUT___POR 0x00000FFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SRNG_WATCHDOG_TIMEOUT__SNOOP_SRNG_WDOG_TIMEOUT___POR 0xFFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SRNG_WATCHDOG_TIMEOUT__SNOOP_SRNG_WDOG_TIMEOUT___M 0x00000FFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SRNG_WATCHDOG_TIMEOUT__SNOOP_SRNG_WDOG_TIMEOUT___S 0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SRNG_WATCHDOG_TIMEOUT___M 0x00000FFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_SRNG_WATCHDOG_TIMEOUT___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_STATUS (0x00A830D4) +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_STATUS___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_STATUS___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_STATUS__RING_REQ_ERR_INT_P___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_STATUS__TXDMA_SNOOP_GEN_CUR_ST___POR 0x00 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_STATUS__TLV_ROUTER0_SNOOP_OP_FSM_CUR_ST___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_STATUS__TLV_ROUTER0_SNOOP_IP_FSM_CUR_ST___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_STATUS__RING_REQ_ERR_INT_P___M 0x00002000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_STATUS__RING_REQ_ERR_INT_P___S 13 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_STATUS__TXDMA_SNOOP_GEN_CUR_ST___M 0x00001F00 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_STATUS__TXDMA_SNOOP_GEN_CUR_ST___S 8 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_STATUS__TLV_ROUTER0_SNOOP_OP_FSM_CUR_ST___M 0x000000F0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_STATUS__TLV_ROUTER0_SNOOP_OP_FSM_CUR_ST___S 4 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_STATUS__TLV_ROUTER0_SNOOP_IP_FSM_CUR_ST___M 0x0000000F +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_STATUS__TLV_ROUTER0_SNOOP_IP_FSM_CUR_ST___S 0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_STATUS___M 0x00003FFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_STATUS___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS (0x00A830D8) +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS___POR 0x00000700 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_UCODE_SNOOP_FLUSH_DONE___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_UCODE_SNOOP_FLUSH___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_SNOOP_SRNG_P_IDLE___POR 0x1 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_UCODE_SNOOP_LOGIC_IDLE___POR 0x1 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_SNOOP_GEN_FSM_IDLE___POR 0x1 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_SNOOP_SRNG_P_IDLE_OVERRIDE___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_UCODE_SNOOP_LOGIC_IDLE_OVERRIDE___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_SNOOP_GEN_FSM_IDLE_OVERRIDE___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_UCODE_SNOOP_FLUSH_DONE___M 0x00020000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_UCODE_SNOOP_FLUSH_DONE___S 17 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_UCODE_SNOOP_FLUSH___M 0x00010000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_UCODE_SNOOP_FLUSH___S 16 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_SNOOP_SRNG_P_IDLE___M 0x00000400 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_SNOOP_SRNG_P_IDLE___S 10 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_UCODE_SNOOP_LOGIC_IDLE___M 0x00000200 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_UCODE_SNOOP_LOGIC_IDLE___S 9 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_SNOOP_GEN_FSM_IDLE___M 0x00000100 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_SNOOP_GEN_FSM_IDLE___S 8 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_SNOOP_SRNG_P_IDLE_OVERRIDE___M 0x00000004 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_SNOOP_SRNG_P_IDLE_OVERRIDE___S 2 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_UCODE_SNOOP_LOGIC_IDLE_OVERRIDE___M 0x00000002 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_UCODE_SNOOP_LOGIC_IDLE_OVERRIDE___S 1 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_SNOOP_GEN_FSM_IDLE_OVERRIDE___M 0x00000001 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS__TXDMA_SNOOP_GEN_FSM_IDLE_OVERRIDE___S 0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS___M 0x00030707 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SNOOP_IDLE_CTRL_STATUS___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SPARE_CTRL (0x00A830DC) +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SPARE_CTRL___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SPARE_CTRL___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SPARE_CTRL__SPARE_REG___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SPARE_CTRL__SPARE_REG___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SPARE_CTRL__SPARE_REG___S 0 +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SPARE_CTRL___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R0_TXDMA_SPARE_CTRL___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_LSB (0x00A830E0) +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_LSB___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_LSB___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_LSB___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_LSB___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_MSB (0x00A830E4) +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_MSB___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_MSB___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_MSB__RING_SIZE___S 8 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_MSB___M 0x00FFFFFF +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_BASE_MSB___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_ID (0x00A830E8) +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_ID___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_ID___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_ID__RING_ID___POR 0x00 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_ID__ENTRY_SIZE___POR 0x00 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_ID__RING_ID___M 0x0000FF00 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_ID__RING_ID___S 8 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_ID__ENTRY_SIZE___M 0x000000FF +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_ID__ENTRY_SIZE___S 0 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_ID___M 0x0000FFFF +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_ID___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_STATUS (0x00A830EC) +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_STATUS___RWC QCSR_REG_RO +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_STATUS___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_STATUS__NUM_VALID_WORDS___S 0 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_STATUS___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_STATUS___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC (0x00A830F0) +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC___POR 0x00000080 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__LOOP_CNT___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SPARE_CONTROL___POR 0x00 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SRNG_ENABLE___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SECURITY_BIT___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__LOOP_CNT___M 0x03C00000 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__LOOP_CNT___S 22 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SPARE_CONTROL___S 14 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SRNG_SM_STATE2___S 12 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SRNG_SM_STATE1___S 8 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SRNG_IS_IDLE___S 7 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SRNG_ENABLE___S 6 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__MSI_SWAP_BIT___S 3 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SECURITY_BIT___M 0x00000004 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__SECURITY_BIT___S 2 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__LOOPCNT_DISABLE___S 1 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC__RING_ID_DISABLE___S 0 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC___M 0x03FFFFFF +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MISC___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_ADDR_LSB (0x00A830F4) +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_ADDR_LSB___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_ADDR_LSB___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_ADDR_MSB (0x00A830F8) +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_ADDR_MSB___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_ADDR_MSB___M 0x000000FF +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_ADDR_MSB___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_SETUP (0x00A83104) +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_SETUP___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_STATUS (0x00A83108) +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_INT_STATUS___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_FULL_COUNTER (0x00A8310C) +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_PRODUCER_FULL_COUNTER___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_LSB (0x00A83128) +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_LSB___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_LSB__ADDR___S 0 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_LSB___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_MSB (0x00A8312C) +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_MSB___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_MSB__ADDR___S 0 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_MSB___M 0x000001FF +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_BASE_MSB___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_DATA (0x00A83130) +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_DATA___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_DATA___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_DATA__VALUE___S 0 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_DATA___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_MSI1_DATA___S 0 + +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_TP_SW_OFFSET (0x00A83134) +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define WMAC0_TXDMA_TXDMA_R0_SNOOP_SRNG_0_RING_HP_TP_SW_OFFSET___S 0 + +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_TRACEBUS (0x00A84010) +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_TRACEBUS___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_TRACEBUS___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_TRACEBUS__SELECT___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_TRACEBUS__SELECT___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_TRACEBUS__SELECT___S 0 +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_TRACEBUS___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_TRACEBUS___S 0 + +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_DEBUG_SEL (0x00A84014) +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_DEBUG_SEL___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_DEBUG_SEL___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_DEBUG_SEL__MSDU_WORD_SEL___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_DEBUG_SEL__REQ_SEL___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_DEBUG_SEL__USER_SEL___POR 0x00 +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_DEBUG_SEL__MSDU_WORD_SEL___M 0x00000180 +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_DEBUG_SEL__MSDU_WORD_SEL___S 7 +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_DEBUG_SEL__REQ_SEL___M 0x00000040 +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_DEBUG_SEL__REQ_SEL___S 6 +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_DEBUG_SEL__USER_SEL___M 0x0000003F +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_DEBUG_SEL__USER_SEL___S 0 +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_DEBUG_SEL___M 0x000001FF +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_DEBUG_SEL___S 0 + +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE (0x00A84024) +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__TX_DATA_GXI_LATENCY___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__MSDU_LINK_EXT_GXI_LATENCY___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__MSDU_LINK_GXI_LATENCY___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__DATA_DWORDS___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__MPDU___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__FLUSH_REQ___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__FES_STATUS___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__FLUSH___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__FES_SETUP___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__TX_DATA_GXI_LATENCY___M 0x00000100 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__TX_DATA_GXI_LATENCY___S 8 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__MSDU_LINK_EXT_GXI_LATENCY___M 0x00000080 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__MSDU_LINK_EXT_GXI_LATENCY___S 7 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__MSDU_LINK_GXI_LATENCY___M 0x00000040 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__MSDU_LINK_GXI_LATENCY___S 6 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__DATA_DWORDS___M 0x00000020 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__DATA_DWORDS___S 5 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__MPDU___M 0x00000010 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__MPDU___S 4 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__FLUSH_REQ___M 0x00000008 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__FLUSH_REQ___S 3 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__FES_STATUS___M 0x00000004 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__FES_STATUS___S 2 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__FLUSH___M 0x00000002 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__FLUSH___S 1 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__FES_SETUP___M 0x00000001 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE__FES_SETUP___S 0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE___M 0x000001FF +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_COUNTER_ENABLE___S 0 + +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FES_SETUP (0x00A84028) +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FES_SETUP___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FES_SETUP___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FES_SETUP__COUNT___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FES_SETUP__COUNT___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FES_SETUP__COUNT___S 0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FES_SETUP___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FES_SETUP___S 0 + +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FLUSH (0x00A8402C) +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FLUSH___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FLUSH___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FLUSH__COUNT___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FLUSH__COUNT___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FLUSH__COUNT___S 0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FLUSH___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FLUSH___S 0 + +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FES_STATUS (0x00A84030) +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FES_STATUS___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FES_STATUS___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FES_STATUS__COUNT___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FES_STATUS__COUNT___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FES_STATUS__COUNT___S 0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FES_STATUS___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FES_STATUS___S 0 + +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FLUSH_REQ (0x00A84034) +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FLUSH_REQ___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FLUSH_REQ___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FLUSH_REQ__COUNT___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FLUSH_REQ__COUNT___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FLUSH_REQ__COUNT___S 0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FLUSH_REQ___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_FLUSH_REQ___S 0 + +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_MPDU (0x00A84038) +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_MPDU___RWC QCSR_REG_RO +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_MPDU___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_MPDU__COUNT___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_MPDU__COUNT___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_MPDU__COUNT___S 0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_MPDU___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_MPDU___S 0 + +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_MSDU_DATA_DWORDS (0x00A8403C) +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_MSDU_DATA_DWORDS___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_MSDU_DATA_DWORDS___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_MSDU_DATA_DWORDS__COUNT___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_MSDU_DATA_DWORDS__COUNT___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_MSDU_DATA_DWORDS__COUNT___S 0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_MSDU_DATA_DWORDS___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_MSDU_DATA_DWORDS___S 0 + +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0 (0x00A84040) +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0___RWC QCSR_REG_RO +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0___POR 0x00000008 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__PTI_ST___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__OTI_PTE_OLE_RDY_ST___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__OTI_PTE_ST___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__TX_DATA_FETCH_TLVOUT_ST___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__TX_DATA_FETCH_REQ_ST___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__MSDU_INFO_FETCH_LINK_EXT_REQ_ST___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__MSDU_INFO_FETCH_LINK_REQ_ST___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__MPDU_INFO_SFM_RD_ST___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__MPDU_INFO_SFM_WR_ST___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__OTE_TLVOUT_ST___POR 0x1 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__TXDMACTRL_ST___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__PTI_ST___M 0x07000000 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__PTI_ST___S 24 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__OTI_PTE_OLE_RDY_ST___M 0x00C00000 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__OTI_PTE_OLE_RDY_ST___S 22 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__OTI_PTE_ST___M 0x00300000 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__OTI_PTE_ST___S 20 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__TX_DATA_FETCH_TLVOUT_ST___M 0x000F0000 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__TX_DATA_FETCH_TLVOUT_ST___S 16 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__TX_DATA_FETCH_REQ_ST___M 0x0000F000 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__TX_DATA_FETCH_REQ_ST___S 12 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__MSDU_INFO_FETCH_LINK_EXT_REQ_ST___M 0x00000800 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__MSDU_INFO_FETCH_LINK_EXT_REQ_ST___S 11 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__MSDU_INFO_FETCH_LINK_REQ_ST___M 0x00000600 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__MSDU_INFO_FETCH_LINK_REQ_ST___S 9 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__MPDU_INFO_SFM_RD_ST___M 0x00000180 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__MPDU_INFO_SFM_RD_ST___S 7 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__MPDU_INFO_SFM_WR_ST___M 0x00000060 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__MPDU_INFO_SFM_WR_ST___S 5 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__OTE_TLVOUT_ST___M 0x00000018 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__OTE_TLVOUT_ST___S 3 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__TXDMACTRL_ST___M 0x00000007 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0__TXDMACTRL_ST___S 0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0___M 0x07FFFFFF +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_STATES_0___S 0 + +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_TRC_EVENTMASK_IX_0 (0x00A84048) +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_TRC_EVENTMASK_IX_0___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_TRC_EVENTMASK_IX_0___POR 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_TRC_EVENTMASK_IX_0__MASK___POR 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_TRC_EVENTMASK_IX_0__MASK___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_TRC_EVENTMASK_IX_0__MASK___S 0 +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_TRC_EVENTMASK_IX_0___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_TRC_EVENTMASK_IX_0___S 0 + +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_TRC_EVENTMASK_IX_1 (0x00A8404C) +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_TRC_EVENTMASK_IX_1___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_TRC_EVENTMASK_IX_1___POR 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_TRC_EVENTMASK_IX_1__MASK___POR 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_TRC_EVENTMASK_IX_1__MASK___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_TRC_EVENTMASK_IX_1__MASK___S 0 +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_TRC_EVENTMASK_IX_1___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R1_TXDMA_TRC_EVENTMASK_IX_1___S 0 + +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_MSDU_LINK (0x00A84060) +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_MSDU_LINK___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_MSDU_LINK___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_MSDU_LINK__COUNT___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_MSDU_LINK__COUNT___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_MSDU_LINK__COUNT___S 0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_MSDU_LINK___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_MSDU_LINK___S 0 + +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_MSDU_LINK_EXT (0x00A84064) +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_MSDU_LINK_EXT___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_MSDU_LINK_EXT___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_MSDU_LINK_EXT__COUNT___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_MSDU_LINK_EXT__COUNT___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_MSDU_LINK_EXT__COUNT___S 0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_MSDU_LINK_EXT___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_MSDU_LINK_EXT___S 0 + +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_TX_DATA (0x00A84068) +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_TX_DATA___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_TX_DATA___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_TX_DATA__COUNT___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_TX_DATA__COUNT___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_TX_DATA__COUNT___S 0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_TX_DATA___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_GXI_LATENCY_TX_DATA___S 0 + +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_TESTBUS_LSB (0x00A84070) +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_TESTBUS_LSB___RWC QCSR_REG_RO +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_TESTBUS_LSB___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_TESTBUS_LSB__VALUE___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_TESTBUS_LSB__VALUE___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_TESTBUS_LSB__VALUE___S 0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_TESTBUS_LSB___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_TESTBUS_LSB___S 0 + +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_TESTBUS_MSB (0x00A84074) +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_TESTBUS_MSB___RWC QCSR_REG_RO +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_TESTBUS_MSB___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_TESTBUS_MSB__VALUE___POR 0x00 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_TESTBUS_MSB__VALUE___M 0x000000FF +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_TESTBUS_MSB__VALUE___S 0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_TESTBUS_MSB___M 0x000000FF +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_TESTBUS_MSB___S 0 + +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_OUTSTANDING_REQ (0x00A84078) +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_OUTSTANDING_REQ___RWC QCSR_REG_RO +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_OUTSTANDING_REQ___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_OUTSTANDING_REQ__VALUE_1___POR 0x000000 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_OUTSTANDING_REQ__VALUE_0___POR 0x00 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_OUTSTANDING_REQ__VALUE_1___M 0xFFFFFF00 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_OUTSTANDING_REQ__VALUE_1___S 8 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_OUTSTANDING_REQ__VALUE_0___M 0x000000FF +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_OUTSTANDING_REQ__VALUE_0___S 0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_OUTSTANDING_REQ___M 0xFFFFFFFF +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_OUTSTANDING_REQ___S 0 + +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE (0x00A84080) +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE___RWC QCSR_REG_RO +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__OTE_ERR_INCOMPLETE_TLV_P___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__UNEXPECTED_NULL_LENGTH_P___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__APB_WR_TO_RD_ONLY_ADDR_P___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__APB_WR_INVALID_ADDR_P___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__APB_RD_INVALID_ADDR_P___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__MSDU_LENGTH_ERR_P___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__MSDU_LINK_TIMEOUT_P___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__MSDU_LINK_EXT_TIMEOUT_P___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__TX_DATA_GXI_TIMEOUT___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__OLE_RDY_TIMEOUT_P___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__WDG_TIMEOUT_P___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__MISSING_TLV_P___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__UNEXPT_FES_SETUP_TLV_P___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__INCMPLT_TLV_P___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__TXDMA_IDLE___POR 0x0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__OTE_ERR_INCOMPLETE_TLV_P___M 0x00004000 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__OTE_ERR_INCOMPLETE_TLV_P___S 14 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__UNEXPECTED_NULL_LENGTH_P___M 0x00002000 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__UNEXPECTED_NULL_LENGTH_P___S 13 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__APB_WR_TO_RD_ONLY_ADDR_P___M 0x00001000 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__APB_WR_TO_RD_ONLY_ADDR_P___S 12 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__APB_WR_INVALID_ADDR_P___M 0x00000800 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__APB_WR_INVALID_ADDR_P___S 11 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__APB_RD_INVALID_ADDR_P___M 0x00000400 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__APB_RD_INVALID_ADDR_P___S 10 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__MSDU_LENGTH_ERR_P___M 0x00000200 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__MSDU_LENGTH_ERR_P___S 9 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__MSDU_LINK_TIMEOUT_P___M 0x00000100 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__MSDU_LINK_TIMEOUT_P___S 8 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__MSDU_LINK_EXT_TIMEOUT_P___M 0x00000080 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__MSDU_LINK_EXT_TIMEOUT_P___S 7 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__TX_DATA_GXI_TIMEOUT___M 0x00000040 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__TX_DATA_GXI_TIMEOUT___S 6 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__OLE_RDY_TIMEOUT_P___M 0x00000020 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__OLE_RDY_TIMEOUT_P___S 5 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__WDG_TIMEOUT_P___M 0x00000010 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__WDG_TIMEOUT_P___S 4 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__MISSING_TLV_P___M 0x00000008 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__MISSING_TLV_P___S 3 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__UNEXPT_FES_SETUP_TLV_P___M 0x00000004 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__UNEXPT_FES_SETUP_TLV_P___S 2 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__INCMPLT_TLV_P___M 0x00000002 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__INCMPLT_TLV_P___S 1 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__TXDMA_IDLE___M 0x00000001 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE__TXDMA_IDLE___S 0 +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE___M 0x00007FFF +#define WMAC0_TXDMA_TXDMA_R1_DEBUG_ERROR_CASE___S 0 + +#define WMAC0_TXDMA_TXDMA_R2_SNOOP_SRNG_0_RING_HP (0x00A85000) +#define WMAC0_TXDMA_TXDMA_R2_SNOOP_SRNG_0_RING_HP___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R2_SNOOP_SRNG_0_RING_HP___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R2_SNOOP_SRNG_0_RING_HP__HEAD_PTR___POR 0x0000 +#define WMAC0_TXDMA_TXDMA_R2_SNOOP_SRNG_0_RING_HP__HEAD_PTR___M 0x0000FFFF +#define WMAC0_TXDMA_TXDMA_R2_SNOOP_SRNG_0_RING_HP__HEAD_PTR___S 0 +#define WMAC0_TXDMA_TXDMA_R2_SNOOP_SRNG_0_RING_HP___M 0x0000FFFF +#define WMAC0_TXDMA_TXDMA_R2_SNOOP_SRNG_0_RING_HP___S 0 + +#define WMAC0_TXDMA_TXDMA_R2_SNOOP_SRNG_0_RING_TP (0x00A85004) +#define WMAC0_TXDMA_TXDMA_R2_SNOOP_SRNG_0_RING_TP___RWC QCSR_REG_RW +#define WMAC0_TXDMA_TXDMA_R2_SNOOP_SRNG_0_RING_TP___POR 0x00000000 +#define WMAC0_TXDMA_TXDMA_R2_SNOOP_SRNG_0_RING_TP__TAIL_PTR___POR 0x0000 +#define WMAC0_TXDMA_TXDMA_R2_SNOOP_SRNG_0_RING_TP__TAIL_PTR___M 0x0000FFFF +#define WMAC0_TXDMA_TXDMA_R2_SNOOP_SRNG_0_RING_TP__TAIL_PTR___S 0 +#define WMAC0_TXDMA_TXDMA_R2_SNOOP_SRNG_0_RING_TP___M 0x0000FFFF +#define WMAC0_TXDMA_TXDMA_R2_SNOOP_SRNG_0_RING_TP___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_LSB (0x00A86000) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_LSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_MSB (0x00A86004) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_MSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_MSB__RING_SIZE___S 8 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_MSB___M 0x00FFFFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_BASE_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_ID (0x00A86008) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_ID___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_ID___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_ID__ENTRY_SIZE___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_ID__ENTRY_SIZE___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_ID__ENTRY_SIZE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_ID___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_ID___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_STATUS (0x00A8600C) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_STATUS___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_STATUS___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_STATUS__NUM_VALID_WORDS___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_STATUS___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_STATUS___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC (0x00A86010) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC___POR 0x00000080 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SPARE_CONTROL___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SRNG_ENABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SECURITY_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SPARE_CONTROL___S 14 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SRNG_SM_STATE2___S 12 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SRNG_SM_STATE1___S 8 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SRNG_IS_IDLE___S 7 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SRNG_ENABLE___S 6 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__MSI_SWAP_BIT___S 3 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SECURITY_BIT___M 0x00000004 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__SECURITY_BIT___S 2 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__LOOPCNT_DISABLE___S 1 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC__RING_ID_DISABLE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC___M 0x003FFFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MISC___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_TP_ADDR_LSB (0x00A8601C) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_TP_ADDR_LSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_TP_ADDR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_TP_ADDR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_TP_ADDR_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_TP_ADDR_MSB (0x00A86020) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_TP_ADDR_MSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_TP_ADDR_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_TP_ADDR_MSB___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_TP_ADDR_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0 (0x00A86030) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S 16 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S 15 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1 (0x00A86034) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_STATUS (0x00A86038) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_STATUS___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S 15 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_INT_STATUS___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER (0x00A8603C) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER (0x00A86040) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER__MODE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS (0x00A86044) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S 16 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_LSB (0x00A86048) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_LSB__ADDR___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_MSB (0x00A8604C) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_MSB__ADDR___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_MSB___M 0x000001FF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_BASE_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_DATA (0x00A86050) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_DATA___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_DATA___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_DATA__VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_DATA___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_MSI1_DATA___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_HP_TP_SW_OFFSET (0x00A86054) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_HP_TP_SW_OFFSET___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_EN_ACT (0x00A86058) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_EN_ACT___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_EN_ACT___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_EN_ACT__BUF_LEN___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_EN_ACT__BUF_LEN___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_EN_ACT__BUF_LEN___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_EN_ACT___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_EN_ACT___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_0 (0x00A8605C) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_0___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_0___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_0__PACKET_SWAP___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_0__STRUCT_SWAP___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_0__PACKET_SWAP___M 0x00000002 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_0__PACKET_SWAP___S 1 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_0__STRUCT_SWAP___M 0x00000001 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_0__STRUCT_SWAP___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_0___M 0x00000003 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_0___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_1 (0x00A86060) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_1___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_1___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_1__RX_PACKET_OFFSET___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_1__RX_HEADER_OFFSET___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_1__RX_PACKET_OFFSET___M 0x0FFC0000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_1__RX_PACKET_OFFSET___S 18 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_1__RX_HEADER_OFFSET___M 0x00000FFC +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_1__RX_HEADER_OFFSET___S 2 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_1___M 0x0FFC0FFC +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_1___S 2 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_2 (0x00A86064) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_2___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_2___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_2__RX_MPDU_END_OFFSET___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_2__RX_MPDU_START_OFFSET___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_2__RX_MPDU_END_OFFSET___M 0x0FFC0000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_2__RX_MPDU_END_OFFSET___S 18 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_2__RX_MPDU_START_OFFSET___M 0x00000FFC +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_2__RX_MPDU_START_OFFSET___S 2 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_2___M 0x0FFC0FFC +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_2___S 2 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_3 (0x00A86068) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_3___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_3___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_3__RX_MSDU_END_OFFSET___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_3__RX_MSDU_START_OFFSET___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_3__RX_MSDU_END_OFFSET___M 0x0FFC0000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_3__RX_MSDU_END_OFFSET___S 18 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_3__RX_MSDU_START_OFFSET___M 0x00000FFC +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_3__RX_MSDU_START_OFFSET___S 2 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_3___M 0x0FFC0FFC +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_3___S 2 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_4 (0x00A8606C) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_4___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_4___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_4__RX_ATTENTION_OFFSET___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_4__RX_ATTENTION_OFFSET___M 0x00000FFC +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_4__RX_ATTENTION_OFFSET___S 2 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_4___M 0x00000FFC +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_BUF_RING_CFG_4___S 2 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_LSB (0x00A86070) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_LSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_MSB (0x00A86074) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_MSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_MSB__RING_SIZE___S 8 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_MSB___M 0x00FFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_BASE_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_ID (0x00A86078) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_ID___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_ID___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_ID__ENTRY_SIZE___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_ID__ENTRY_SIZE___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_ID__ENTRY_SIZE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_ID___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_ID___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_STATUS (0x00A8607C) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_STATUS___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_STATUS___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_STATUS__NUM_VALID_WORDS___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_STATUS___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_STATUS___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC (0x00A86080) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC___POR 0x00000080 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SPARE_CONTROL___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SRNG_ENABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SECURITY_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SPARE_CONTROL___S 14 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SRNG_SM_STATE2___S 12 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SRNG_SM_STATE1___S 8 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SRNG_IS_IDLE___S 7 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SRNG_ENABLE___S 6 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__MSI_SWAP_BIT___S 3 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SECURITY_BIT___M 0x00000004 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__SECURITY_BIT___S 2 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__LOOPCNT_DISABLE___S 1 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC__RING_ID_DISABLE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC___M 0x003FFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MISC___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_TP_ADDR_LSB (0x00A8608C) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_TP_ADDR_LSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_TP_ADDR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_TP_ADDR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_TP_ADDR_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_TP_ADDR_MSB (0x00A86090) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_TP_ADDR_MSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_TP_ADDR_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_TP_ADDR_MSB___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_TP_ADDR_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0 (0x00A860A0) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S 16 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S 15 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1 (0x00A860A4) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_STATUS (0x00A860A8) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_STATUS___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S 15 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_INT_STATUS___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER (0x00A860AC) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER (0x00A860B0) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER__MODE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS (0x00A860B4) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S 16 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_LSB (0x00A860B8) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_LSB__ADDR___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_MSB (0x00A860BC) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_MSB__ADDR___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_MSB___M 0x000001FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_BASE_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_DATA (0x00A860C0) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_DATA___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_DATA___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_DATA__VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_DATA___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_MSI1_DATA___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_HP_TP_SW_OFFSET (0x00A860C4) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_HP_TP_SW_OFFSET___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_EN_ACT (0x00A860C8) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_EN_ACT___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_EN_ACT___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_EN_ACT__BUF_LEN___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_EN_ACT__BUF_LEN___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_EN_ACT__BUF_LEN___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_EN_ACT___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_EN_ACT___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_0 (0x00A860CC) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_0___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_0___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_0__PACKET_SWAP___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_0__STRUCT_SWAP___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_0__PACKET_SWAP___M 0x00000002 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_0__PACKET_SWAP___S 1 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_0__STRUCT_SWAP___M 0x00000001 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_0__STRUCT_SWAP___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_0___M 0x00000003 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_0___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_1 (0x00A860D0) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_1___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_1___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_1__RX_PACKET_OFFSET___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_1__RX_HEADER_OFFSET___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_1__RX_PACKET_OFFSET___M 0x0FFC0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_1__RX_PACKET_OFFSET___S 18 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_1__RX_HEADER_OFFSET___M 0x00000FFC +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_1__RX_HEADER_OFFSET___S 2 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_1___M 0x0FFC0FFC +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_1___S 2 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_2 (0x00A860D4) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_2___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_2___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_2__RX_MPDU_END_OFFSET___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_2__RX_MPDU_START_OFFSET___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_2__RX_MPDU_END_OFFSET___M 0x0FFC0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_2__RX_MPDU_END_OFFSET___S 18 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_2__RX_MPDU_START_OFFSET___M 0x00000FFC +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_2__RX_MPDU_START_OFFSET___S 2 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_2___M 0x0FFC0FFC +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_2___S 2 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_3 (0x00A860D8) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_3___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_3___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_3__RX_MSDU_END_OFFSET___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_3__RX_MSDU_START_OFFSET___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_3__RX_MSDU_END_OFFSET___M 0x0FFC0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_3__RX_MSDU_END_OFFSET___S 18 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_3__RX_MSDU_START_OFFSET___M 0x00000FFC +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_3__RX_MSDU_START_OFFSET___S 2 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_3___M 0x0FFC0FFC +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_3___S 2 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_4 (0x00A860DC) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_4___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_4___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_4__RX_ATTENTION_OFFSET___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_4__RX_ATTENTION_OFFSET___M 0x00000FFC +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_4__RX_ATTENTION_OFFSET___S 2 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_4___M 0x00000FFC +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_BUF_RING_CFG_4___S 2 + +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_LSB (0x00A860E0) +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_LSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_MSB (0x00A860E4) +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_MSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_MSB__RING_SIZE___S 8 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_MSB___M 0x00FFFFFF +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_BASE_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_ID (0x00A860E8) +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_ID___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_ID___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_ID__ENTRY_SIZE___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_ID__ENTRY_SIZE___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_ID__ENTRY_SIZE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_ID___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_ID___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_STATUS (0x00A860EC) +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_STATUS___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_STATUS___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_STATUS__NUM_VALID_WORDS___S 0 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_STATUS___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_STATUS___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC (0x00A860F0) +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC___POR 0x00000080 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SPARE_CONTROL___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SRNG_ENABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SECURITY_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SPARE_CONTROL___S 14 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SRNG_SM_STATE2___S 12 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SRNG_SM_STATE1___S 8 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SRNG_IS_IDLE___S 7 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SRNG_ENABLE___S 6 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__MSI_SWAP_BIT___S 3 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SECURITY_BIT___M 0x00000004 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__SECURITY_BIT___S 2 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__LOOPCNT_DISABLE___S 1 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC__RING_ID_DISABLE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC___M 0x003FFFFF +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MISC___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_TP_ADDR_LSB (0x00A860FC) +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_TP_ADDR_LSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_TP_ADDR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_TP_ADDR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_TP_ADDR_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_TP_ADDR_MSB (0x00A86100) +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_TP_ADDR_MSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_TP_ADDR_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_TP_ADDR_MSB___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_TP_ADDR_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0 (0x00A86110) +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S 16 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S 15 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S 0 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX0___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1 (0x00A86114) +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S 0 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_SETUP_IX1___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_STATUS (0x00A86118) +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_STATUS___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S 15 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_INT_STATUS___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER (0x00A8611C) +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S 0 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_EMPTY_COUNTER___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER (0x00A86120) +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER__MODE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_TIMER___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS (0x00A86124) +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S 16 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S 0 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CONSUMER_PREFETCH_STATUS___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_LSB (0x00A86128) +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_LSB__ADDR___S 0 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_MSB (0x00A8612C) +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_MSB__ADDR___S 0 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_MSB___M 0x000001FF +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_BASE_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_DATA (0x00A86130) +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_DATA___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_DATA___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_DATA__VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_DATA___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_MSI1_DATA___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_HP_TP_SW_OFFSET (0x00A86134) +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_HP_TP_SW_OFFSET___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_EN_ACT (0x00A86138) +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_EN_ACT___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_EN_ACT___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_EN_ACT__BUF_LEN___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_EN_ACT__BUF_LEN___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_EN_ACT__BUF_LEN___S 0 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_EN_ACT___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_EN_ACT___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_0 (0x00A8613C) +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_0___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_0___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_0__PACKET_SWAP___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_0__STRUCT_SWAP___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_0__PACKET_SWAP___M 0x00000002 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_0__PACKET_SWAP___S 1 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_0__STRUCT_SWAP___M 0x00000001 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_0__STRUCT_SWAP___S 0 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_0___M 0x00000003 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_0___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_1 (0x00A86140) +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_1___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_1___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_1__RX_PACKET_OFFSET___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_1__RX_HEADER_OFFSET___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_1__RX_PACKET_OFFSET___M 0x0FFC0000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_1__RX_PACKET_OFFSET___S 18 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_1__RX_HEADER_OFFSET___M 0x00000FFC +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_1__RX_HEADER_OFFSET___S 2 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_1___M 0x0FFC0FFC +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_1___S 2 + +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_2 (0x00A86144) +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_2___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_2___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_2__RX_MPDU_END_OFFSET___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_2__RX_MPDU_START_OFFSET___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_2__RX_MPDU_END_OFFSET___M 0x0FFC0000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_2__RX_MPDU_END_OFFSET___S 18 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_2__RX_MPDU_START_OFFSET___M 0x00000FFC +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_2__RX_MPDU_START_OFFSET___S 2 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_2___M 0x0FFC0FFC +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_2___S 2 + +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_3 (0x00A86148) +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_3___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_3___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_3__RX_MSDU_END_OFFSET___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_3__RX_MSDU_START_OFFSET___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_3__RX_MSDU_END_OFFSET___M 0x0FFC0000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_3__RX_MSDU_END_OFFSET___S 18 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_3__RX_MSDU_START_OFFSET___M 0x00000FFC +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_3__RX_MSDU_START_OFFSET___S 2 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_3___M 0x0FFC0FFC +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_3___S 2 + +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_4 (0x00A8614C) +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_4___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_4___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_4__RX_ATTENTION_OFFSET___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_4__RX_ATTENTION_OFFSET___M 0x00000FFC +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_4__RX_ATTENTION_OFFSET___S 2 +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_4___M 0x00000FFC +#define WMAC0_RXDMA_RXDMA_R0_SW2RXDMA_BUF_RING_CFG_4___S 2 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_LSB (0x00A86150) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_LSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_MSB (0x00A86154) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_MSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_MSB__RING_SIZE___S 8 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_MSB___M 0x00FFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_BASE_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_ID (0x00A86158) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_ID___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_ID___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_ID__ENTRY_SIZE___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_ID__ENTRY_SIZE___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_ID__ENTRY_SIZE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_ID___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_ID___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_STATUS (0x00A8615C) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_STATUS___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_STATUS___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_STATUS__NUM_VALID_WORDS___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_STATUS___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_STATUS___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC (0x00A86160) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC___POR 0x00000080 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SPARE_CONTROL___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SRNG_ENABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SECURITY_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SPARE_CONTROL___S 14 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SRNG_SM_STATE2___S 12 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SRNG_SM_STATE1___S 8 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SRNG_IS_IDLE___S 7 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SRNG_ENABLE___S 6 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__MSI_SWAP_BIT___S 3 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SECURITY_BIT___M 0x00000004 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__SECURITY_BIT___S 2 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__LOOPCNT_DISABLE___S 1 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC__RING_ID_DISABLE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC___M 0x003FFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MISC___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_TP_ADDR_LSB (0x00A8616C) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_TP_ADDR_LSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_TP_ADDR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_TP_ADDR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_TP_ADDR_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_TP_ADDR_MSB (0x00A86170) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_TP_ADDR_MSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_TP_ADDR_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_TP_ADDR_MSB___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_TP_ADDR_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX0 (0x00A86180) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S 16 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S 15 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX0___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX1 (0x00A86184) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_SETUP_IX1___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_STATUS (0x00A86188) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_STATUS___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S 15 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_INT_STATUS___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_EMPTY_COUNTER (0x00A8618C) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_EMPTY_COUNTER___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_TIMER (0x00A86190) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_TIMER__MODE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_TIMER___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_STATUS (0x00A86194) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S 16 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_CONSUMER_PREFETCH_STATUS___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_LSB (0x00A86198) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_LSB__ADDR___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_MSB (0x00A8619C) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_MSB__ADDR___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_MSB___M 0x000001FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_BASE_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_DATA (0x00A861A0) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_DATA___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_DATA___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_DATA__VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_DATA___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_MSI1_DATA___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_HP_TP_SW_OFFSET (0x00A861A4) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_HP_TP_SW_OFFSET___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_EN_ACT (0x00A861A8) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_EN_ACT___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_EN_ACT___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_EN_ACT__STRUCT_SWAP___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_EN_ACT__BUF_LEN___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_EN_ACT__STRUCT_SWAP___M 0x00010000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_EN_ACT__STRUCT_SWAP___S 16 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_EN_ACT__BUF_LEN___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_EN_ACT__BUF_LEN___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_EN_ACT___M 0x0001FFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_STATBUF_RING_EN_ACT___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_LSB (0x00A861AC) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_LSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_MSB (0x00A861B0) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_MSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_MSB__RING_SIZE___S 8 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_MSB___M 0x00FFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_BASE_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_ID (0x00A861B4) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_ID___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_ID___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_ID__ENTRY_SIZE___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_ID__ENTRY_SIZE___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_ID__ENTRY_SIZE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_ID___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_ID___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_STATUS (0x00A861B8) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_STATUS___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_STATUS___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_STATUS__NUM_VALID_WORDS___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_STATUS___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_STATUS___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC (0x00A861BC) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC___POR 0x00000080 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SPARE_CONTROL___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SRNG_ENABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SECURITY_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SPARE_CONTROL___S 14 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SRNG_SM_STATE2___S 12 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SRNG_SM_STATE1___S 8 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SRNG_IS_IDLE___S 7 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SRNG_ENABLE___S 6 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__MSI_SWAP_BIT___S 3 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SECURITY_BIT___M 0x00000004 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__SECURITY_BIT___S 2 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__LOOPCNT_DISABLE___S 1 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC__RING_ID_DISABLE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC___M 0x003FFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MISC___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_TP_ADDR_LSB (0x00A861C8) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_TP_ADDR_LSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_TP_ADDR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_TP_ADDR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_TP_ADDR_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_TP_ADDR_MSB (0x00A861CC) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_TP_ADDR_MSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_TP_ADDR_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_TP_ADDR_MSB___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_TP_ADDR_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX0 (0x00A861DC) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S 16 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S 15 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX0___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX1 (0x00A861E0) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_SETUP_IX1___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_STATUS (0x00A861E4) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_STATUS___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S 15 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_INT_STATUS___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_EMPTY_COUNTER (0x00A861E8) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_EMPTY_COUNTER___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_TIMER (0x00A861EC) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_TIMER__MODE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_TIMER___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_STATUS (0x00A861F0) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S 16 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_CONSUMER_PREFETCH_STATUS___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_LSB (0x00A861F4) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_LSB__ADDR___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_MSB (0x00A861F8) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_MSB__ADDR___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_MSB___M 0x000001FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_BASE_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_DATA (0x00A861FC) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_DATA___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_DATA___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_DATA__VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_DATA___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_MSI1_DATA___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_HP_TP_SW_OFFSET (0x00A86200) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_HP_TP_SW_OFFSET___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_EN_ACT (0x00A86204) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_EN_ACT___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_EN_ACT___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_EN_ACT__STRUCT_SWAP___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_EN_ACT__BUF_LEN___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_EN_ACT__STRUCT_SWAP___M 0x00010000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_EN_ACT__STRUCT_SWAP___S 16 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_EN_ACT__BUF_LEN___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_EN_ACT__BUF_LEN___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_EN_ACT___M 0x0001FFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA1_STATBUF_RING_EN_ACT___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_LSB (0x00A86208) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_LSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_MSB (0x00A8620C) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_MSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_MSB__RING_SIZE___S 8 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_MSB___M 0x00FFFFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_BASE_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_ID (0x00A86210) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_ID___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_ID___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_ID__ENTRY_SIZE___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_ID__ENTRY_SIZE___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_ID__ENTRY_SIZE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_ID___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_ID___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_STATUS (0x00A86214) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_STATUS___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_STATUS___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_STATUS__NUM_VALID_WORDS___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_STATUS___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_STATUS___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC (0x00A86218) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC___POR 0x00000080 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SPARE_CONTROL___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SRNG_ENABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SECURITY_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SPARE_CONTROL___S 14 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SRNG_SM_STATE2___S 12 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SRNG_SM_STATE1___S 8 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SRNG_IS_IDLE___S 7 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SRNG_ENABLE___S 6 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__MSI_SWAP_BIT___S 3 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SECURITY_BIT___M 0x00000004 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__SECURITY_BIT___S 2 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__LOOPCNT_DISABLE___S 1 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC__RING_ID_DISABLE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC___M 0x003FFFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MISC___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_TP_ADDR_LSB (0x00A86224) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_TP_ADDR_LSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_TP_ADDR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_TP_ADDR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_TP_ADDR_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_TP_ADDR_MSB (0x00A86228) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_TP_ADDR_MSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_TP_ADDR_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_TP_ADDR_MSB___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_TP_ADDR_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0 (0x00A86238) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S 16 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S 15 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX1 (0x00A8623C) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX1___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_STATUS (0x00A86240) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_STATUS___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S 15 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_INT_STATUS___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_EMPTY_COUNTER (0x00A86244) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_EMPTY_COUNTER___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_TIMER (0x00A86248) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_TIMER__MODE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_TIMER___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS (0x00A8624C) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S 16 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_LSB (0x00A86250) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_LSB__ADDR___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_MSB (0x00A86254) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_MSB__ADDR___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_MSB___M 0x000001FF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_BASE_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_DATA (0x00A86258) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_DATA___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_DATA___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_DATA__VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_DATA___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_MSI1_DATA___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_HP_TP_SW_OFFSET (0x00A8625C) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_HP_TP_SW_OFFSET___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_EN_ACT (0x00A86260) +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_EN_ACT___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_EN_ACT___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_EN_ACT__STRUCT_SWAP___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_EN_ACT__STRUCT_SWAP___M 0x00000001 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_EN_ACT__STRUCT_SWAP___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_EN_ACT___M 0x00000001 +#define WMAC0_RXDMA_RXDMA_R0_WBM2RXDMA_LINK_RING_EN_ACT___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_LSB (0x00A86264) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_LSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_MSB (0x00A86268) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_MSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_MSB__RING_SIZE___S 8 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_MSB___M 0x00FFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_BASE_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_ID (0x00A8626C) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_ID___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_ID___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_ID__ENTRY_SIZE___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_ID__ENTRY_SIZE___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_ID__ENTRY_SIZE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_ID___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_ID___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_STATUS (0x00A86270) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_STATUS___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_STATUS___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_STATUS__NUM_VALID_WORDS___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_STATUS___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_STATUS___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC (0x00A86274) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC___POR 0x00000080 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SPARE_CONTROL___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SRNG_ENABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SECURITY_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SPARE_CONTROL___S 14 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SRNG_SM_STATE2___S 12 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SRNG_SM_STATE1___S 8 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SRNG_IS_IDLE___S 7 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SRNG_ENABLE___S 6 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__MSI_SWAP_BIT___S 3 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SECURITY_BIT___M 0x00000004 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__SECURITY_BIT___S 2 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__LOOPCNT_DISABLE___S 1 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC__RING_ID_DISABLE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC___M 0x003FFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MISC___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_TP_ADDR_LSB (0x00A86280) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_TP_ADDR_LSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_TP_ADDR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_TP_ADDR_LSB__TAIL_PTR_MEMADDR_LSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_TP_ADDR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_TP_ADDR_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_TP_ADDR_MSB (0x00A86284) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_TP_ADDR_MSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_TP_ADDR_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_TP_ADDR_MSB__TAIL_PTR_MEMADDR_MSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_TP_ADDR_MSB___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_TP_ADDR_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0 (0x00A86294) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__INTERRUPT_TIMER_THRESHOLD___S 16 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___M 0x00008000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__SW_INTERRUPT_MODE___S 15 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0__BATCH_COUNTER_THRESHOLD___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX0___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX1 (0x00A86298) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX1___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX1___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX1__LOW_THRESHOLD___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX1___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_SETUP_IX1___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_STATUS (0x00A8629C) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_STATUS___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_STATUS___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___M 0x00008000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_STATUS__CURRENT_INT_WIRE_VALUE___S 15 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_STATUS___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_INT_STATUS___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_EMPTY_COUNTER (0x00A862A0) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_EMPTY_COUNTER___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_EMPTY_COUNTER___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___M 0x000003FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_EMPTY_COUNTER__RING_EMPTY_COUNTER___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_EMPTY_COUNTER___M 0x000003FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_EMPTY_COUNTER___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_TIMER (0x00A862A4) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_TIMER___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_TIMER___POR 0x00000003 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_TIMER__MODE___POR 0x3 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_TIMER__MODE___M 0x00000007 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_TIMER__MODE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_TIMER___M 0x00000007 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_TIMER___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS (0x00A862A8) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___M 0x00FF0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS__PREFETCH_COUNT___S 16 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS__INTERNAL_TAIL_PTR___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS___M 0x00FFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_CONSUMER_PREFETCH_STATUS___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_LSB (0x00A862AC) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_LSB__ADDR___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_MSB (0x00A862B0) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_MSB__ADDR___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_MSB___M 0x000001FF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_BASE_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_DATA (0x00A862B4) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_DATA___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_DATA___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_DATA__VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_DATA___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_MSI1_DATA___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_HP_TP_SW_OFFSET (0x00A862B8) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_HP_TP_SW_OFFSET___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_EN_ACT (0x00A862BC) +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_EN_ACT___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_EN_ACT___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_EN_ACT__STRUCT_SWAP___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_EN_ACT__STRUCT_SWAP___M 0x00000001 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_EN_ACT__STRUCT_SWAP___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_EN_ACT___M 0x00000001 +#define WMAC0_RXDMA_RXDMA_R0_FW2RXDMA_LINK_RING_EN_ACT___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_LSB (0x00A862C0) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_LSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_MSB (0x00A862C4) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_MSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_MSB__RING_SIZE___S 8 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_MSB___M 0x00FFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_BASE_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_ID (0x00A862C8) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_ID___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_ID___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_ID__RING_ID___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_ID__ENTRY_SIZE___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_ID__RING_ID___M 0x0000FF00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_ID__RING_ID___S 8 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_ID__ENTRY_SIZE___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_ID__ENTRY_SIZE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_ID___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_ID___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_STATUS (0x00A862CC) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_STATUS___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_STATUS___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_STATUS__NUM_VALID_WORDS___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_STATUS___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_STATUS___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC (0x00A862D0) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC___POR 0x00000080 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__LOOP_CNT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SPARE_CONTROL___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SRNG_ENABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SECURITY_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__LOOP_CNT___M 0x03C00000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__LOOP_CNT___S 22 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SPARE_CONTROL___S 14 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SRNG_SM_STATE2___S 12 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SRNG_SM_STATE1___S 8 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SRNG_IS_IDLE___S 7 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SRNG_ENABLE___S 6 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__MSI_SWAP_BIT___S 3 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SECURITY_BIT___M 0x00000004 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__SECURITY_BIT___S 2 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__LOOPCNT_DISABLE___S 1 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC__RING_ID_DISABLE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC___M 0x03FFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MISC___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_ADDR_LSB (0x00A862D4) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_ADDR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_ADDR_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_ADDR_MSB (0x00A862D8) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_ADDR_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_ADDR_MSB___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_ADDR_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_SETUP (0x00A862E4) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_SETUP___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_STATUS (0x00A862E8) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_INT_STATUS___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_FULL_COUNTER (0x00A862EC) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_PRODUCER_FULL_COUNTER___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_LSB (0x00A86308) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_LSB__ADDR___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_MSB (0x00A8630C) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_MSB__ADDR___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_MSB___M 0x000001FF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_BASE_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_DATA (0x00A86310) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_DATA___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_DATA___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_DATA__VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_DATA___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_MSI1_DATA___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_TP_SW_OFFSET (0x00A86314) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_RING_HP_TP_SW_OFFSET___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_LSB (0x00A86318) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_LSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_MSB (0x00A8631C) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_MSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_MSB__RING_SIZE___S 8 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_MSB___M 0x00FFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_BASE_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_ID (0x00A86320) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_ID___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_ID___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_ID__RING_ID___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_ID__ENTRY_SIZE___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_ID__RING_ID___M 0x0000FF00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_ID__RING_ID___S 8 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_ID__ENTRY_SIZE___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_ID__ENTRY_SIZE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_ID___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_ID___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_STATUS (0x00A86324) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_STATUS___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_STATUS___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_STATUS__NUM_VALID_WORDS___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_STATUS___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_STATUS___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC (0x00A86328) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC___POR 0x00000080 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__LOOP_CNT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SPARE_CONTROL___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SRNG_ENABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SECURITY_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__LOOP_CNT___M 0x03C00000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__LOOP_CNT___S 22 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SPARE_CONTROL___S 14 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SRNG_SM_STATE2___S 12 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SRNG_SM_STATE1___S 8 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SRNG_IS_IDLE___S 7 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SRNG_ENABLE___S 6 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__MSI_SWAP_BIT___S 3 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SECURITY_BIT___M 0x00000004 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__SECURITY_BIT___S 2 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__LOOPCNT_DISABLE___S 1 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC__RING_ID_DISABLE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC___M 0x03FFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MISC___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_ADDR_LSB (0x00A8632C) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_ADDR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_ADDR_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_ADDR_MSB (0x00A86330) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_ADDR_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_ADDR_MSB___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_ADDR_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_SETUP (0x00A8633C) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_SETUP___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_STATUS (0x00A86340) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_INT_STATUS___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_FULL_COUNTER (0x00A86344) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_PRODUCER_FULL_COUNTER___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_LSB (0x00A86360) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_LSB__ADDR___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_MSB (0x00A86364) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_MSB__ADDR___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_MSB___M 0x000001FF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_BASE_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_DATA (0x00A86368) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_DATA___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_DATA___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_DATA__VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_DATA___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_MSI1_DATA___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_TP_SW_OFFSET (0x00A8636C) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_RING_HP_TP_SW_OFFSET___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_LSB (0x00A86370) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_LSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_MSB (0x00A86374) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_MSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_MSB__RING_SIZE___S 8 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_MSB___M 0x00FFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_BASE_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_ID (0x00A86378) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_ID___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_ID___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_ID__RING_ID___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_ID__ENTRY_SIZE___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_ID__RING_ID___M 0x0000FF00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_ID__RING_ID___S 8 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_ID__ENTRY_SIZE___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_ID__ENTRY_SIZE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_ID___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_ID___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_STATUS (0x00A8637C) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_STATUS___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_STATUS___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_STATUS__NUM_VALID_WORDS___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_STATUS___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_STATUS___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC (0x00A86380) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC___POR 0x00000080 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__LOOP_CNT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SPARE_CONTROL___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SRNG_ENABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SECURITY_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__LOOP_CNT___M 0x03C00000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__LOOP_CNT___S 22 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SPARE_CONTROL___S 14 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SRNG_SM_STATE2___S 12 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SRNG_SM_STATE1___S 8 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SRNG_IS_IDLE___S 7 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SRNG_ENABLE___S 6 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__MSI_SWAP_BIT___S 3 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SECURITY_BIT___M 0x00000004 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__SECURITY_BIT___S 2 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__LOOPCNT_DISABLE___S 1 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC__RING_ID_DISABLE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC___M 0x03FFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MISC___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_ADDR_LSB (0x00A86384) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_ADDR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_ADDR_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_ADDR_MSB (0x00A86388) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_ADDR_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_ADDR_MSB___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_ADDR_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_SETUP (0x00A86394) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_SETUP___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_STATUS (0x00A86398) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_INT_STATUS___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_FULL_COUNTER (0x00A8639C) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_PRODUCER_FULL_COUNTER___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_LSB (0x00A863B8) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_LSB__ADDR___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_MSB (0x00A863BC) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_MSB__ADDR___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_MSB___M 0x000001FF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_BASE_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_DATA (0x00A863C0) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_DATA___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_DATA___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_DATA__VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_DATA___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_MSI1_DATA___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_TP_SW_OFFSET (0x00A863C4) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_RING_HP_TP_SW_OFFSET___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_LSB (0x00A863C8) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_LSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_MSB (0x00A863CC) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_MSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_MSB__RING_SIZE___S 8 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_MSB___M 0x00FFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_BASE_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_ID (0x00A863D0) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_ID___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_ID___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_ID__RING_ID___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_ID__ENTRY_SIZE___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_ID__RING_ID___M 0x0000FF00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_ID__RING_ID___S 8 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_ID__ENTRY_SIZE___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_ID__ENTRY_SIZE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_ID___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_ID___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_STATUS (0x00A863D4) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_STATUS___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_STATUS___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_STATUS__NUM_VALID_WORDS___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_STATUS___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_STATUS___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC (0x00A863D8) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC___POR 0x00000080 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__LOOP_CNT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SPARE_CONTROL___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SRNG_ENABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SECURITY_BIT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__LOOP_CNT___M 0x03C00000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__LOOP_CNT___S 22 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SPARE_CONTROL___S 14 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SRNG_SM_STATE2___S 12 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SRNG_SM_STATE1___S 8 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SRNG_IS_IDLE___S 7 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SRNG_ENABLE___S 6 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__MSI_SWAP_BIT___S 3 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SECURITY_BIT___M 0x00000004 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__SECURITY_BIT___S 2 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__LOOPCNT_DISABLE___S 1 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC__RING_ID_DISABLE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC___M 0x03FFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MISC___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_ADDR_LSB (0x00A863DC) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_ADDR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_ADDR_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_ADDR_MSB (0x00A863E0) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_ADDR_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_ADDR_MSB___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_ADDR_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_SETUP (0x00A863EC) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_SETUP___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_STATUS (0x00A863F0) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_INT_STATUS___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_FULL_COUNTER (0x00A863F4) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_PRODUCER_FULL_COUNTER___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_LSB (0x00A86410) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_LSB__ADDR___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_MSB (0x00A86414) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_MSB__ADDR___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_MSB___M 0x000001FF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_BASE_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_DATA (0x00A86418) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_DATA___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_DATA___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_DATA__VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_DATA___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_MSI1_DATA___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_TP_SW_OFFSET (0x00A8641C) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_RING_HP_TP_SW_OFFSET___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_LINK_SOURCE_BUFFER_SELECT (0x00A86420) +#define WMAC0_RXDMA_RXDMA_R0_LINK_SOURCE_BUFFER_SELECT___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_LINK_SOURCE_BUFFER_SELECT___POR 0x00000006 +#define WMAC0_RXDMA_RXDMA_R0_LINK_SOURCE_BUFFER_SELECT__SW2RXDMA_BUF_SOURCE___POR 0x1 +#define WMAC0_RXDMA_RXDMA_R0_LINK_SOURCE_BUFFER_SELECT__FW2RXDMA_BUF_SOURCE___POR 0x1 +#define WMAC0_RXDMA_RXDMA_R0_LINK_SOURCE_BUFFER_SELECT__WBM2RXDMA_BUF_SOURCE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_LINK_SOURCE_BUFFER_SELECT__SW2RXDMA_BUF_SOURCE___M 0x00000004 +#define WMAC0_RXDMA_RXDMA_R0_LINK_SOURCE_BUFFER_SELECT__SW2RXDMA_BUF_SOURCE___S 2 +#define WMAC0_RXDMA_RXDMA_R0_LINK_SOURCE_BUFFER_SELECT__FW2RXDMA_BUF_SOURCE___M 0x00000002 +#define WMAC0_RXDMA_RXDMA_R0_LINK_SOURCE_BUFFER_SELECT__FW2RXDMA_BUF_SOURCE___S 1 +#define WMAC0_RXDMA_RXDMA_R0_LINK_SOURCE_BUFFER_SELECT__WBM2RXDMA_BUF_SOURCE___M 0x00000001 +#define WMAC0_RXDMA_RXDMA_R0_LINK_SOURCE_BUFFER_SELECT__WBM2RXDMA_BUF_SOURCE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_LINK_SOURCE_BUFFER_SELECT___M 0x00000007 +#define WMAC0_RXDMA_RXDMA_R0_LINK_SOURCE_BUFFER_SELECT___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_ENTRANCE_FILTER (0x00A86424) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_ENTRANCE_FILTER___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_ENTRANCE_FILTER___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_ENTRANCE_FILTER__GLOBAL_EN___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_ENTRANCE_FILTER__RX_RING_MASK_SELECTION___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_ENTRANCE_FILTER__GLOBAL_EN___M 0x00000002 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_ENTRANCE_FILTER__GLOBAL_EN___S 1 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_ENTRANCE_FILTER__RX_RING_MASK_SELECTION___M 0x00000001 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_ENTRANCE_FILTER__RX_RING_MASK_SELECTION___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_ENTRANCE_FILTER___M 0x00000003 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_ENTRANCE_FILTER___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_FULL_MONITOR_MODE (0x00A86428) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_FULL_MONITOR_MODE___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_FULL_MONITOR_MODE___POR 0x00000010 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_FULL_MONITOR_MODE__DESTINATION_RING_SELECT___POR 0x2 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_FULL_MONITOR_MODE__ADDNL_DESC_AT_PPDU_END_FOR_NON_ZERO_MPDUS___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_FULL_MONITOR_MODE__ADDNL_DESC_AT_PPDU_END_FOR_ZERO_MPDUS___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_FULL_MONITOR_MODE__EN___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_FULL_MONITOR_MODE__DESTINATION_RING_SELECT___M 0x00000018 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_FULL_MONITOR_MODE__DESTINATION_RING_SELECT___S 3 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_FULL_MONITOR_MODE__ADDNL_DESC_AT_PPDU_END_FOR_NON_ZERO_MPDUS___M 0x00000004 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_FULL_MONITOR_MODE__ADDNL_DESC_AT_PPDU_END_FOR_NON_ZERO_MPDUS___S 2 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_FULL_MONITOR_MODE__ADDNL_DESC_AT_PPDU_END_FOR_ZERO_MPDUS___M 0x00000002 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_FULL_MONITOR_MODE__ADDNL_DESC_AT_PPDU_END_FOR_ZERO_MPDUS___S 1 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_FULL_MONITOR_MODE__EN___M 0x00000001 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_FULL_MONITOR_MODE__EN___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_FULL_MONITOR_MODE___M 0x0000001F +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_FULL_MONITOR_MODE___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0 (0x00A8642C) +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__AMSDU_PARSER_ERROR___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__WIFI_PARSER_ERR___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LIMIT_ERR___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LENGTH_ERR___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__UNENCRYPTED_FRAME_ERR___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__TKIP_MIC_ERR___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__DECRYPT_ERR___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__FCS_ERR___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__MPDU_LENGTH_ERR___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__OVERFLOW_ERR___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__AMSDU_PARSER_ERROR___M 0x38000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__AMSDU_PARSER_ERROR___S 27 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__WIFI_PARSER_ERR___M 0x07000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__WIFI_PARSER_ERR___S 24 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LIMIT_ERR___M 0x00E00000 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LIMIT_ERR___S 21 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LENGTH_ERR___M 0x001C0000 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LENGTH_ERR___S 18 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__UNENCRYPTED_FRAME_ERR___M 0x00038000 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__UNENCRYPTED_FRAME_ERR___S 15 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__TKIP_MIC_ERR___M 0x00007000 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__TKIP_MIC_ERR___S 12 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__DECRYPT_ERR___M 0x00000E00 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__DECRYPT_ERR___S 9 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__FCS_ERR___M 0x000001C0 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__FCS_ERR___S 6 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__MPDU_LENGTH_ERR___M 0x00000038 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__MPDU_LENGTH_ERR___S 3 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__OVERFLOW_ERR___M 0x00000007 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0__OVERFLOW_ERR___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0___M 0x3FFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX0___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1 (0x00A86430) +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1__AMSDU_FRAGMENT_ERROR___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLUSH_REQ___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLOW_IDX_TIMEOUT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1__DA_IDX_TIMEOUT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1__SA_IDX_TIMEOUT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1__AMSDU_FRAGMENT_ERROR___M 0x00007000 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1__AMSDU_FRAGMENT_ERROR___S 12 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLUSH_REQ___M 0x00000E00 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLUSH_REQ___S 9 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLOW_IDX_TIMEOUT___M 0x000001C0 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLOW_IDX_TIMEOUT___S 6 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1__DA_IDX_TIMEOUT___M 0x00000038 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1__DA_IDX_TIMEOUT___S 3 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1__SA_IDX_TIMEOUT___M 0x00000007 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1__SA_IDX_TIMEOUT___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1___M 0x00007FFF +#define WMAC0_RXDMA_RXDMA_R0_WBM_BUFFER_SOURCE_ERROR_ROUTING_IX1___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0 (0x00A86434) +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__AMSDU_PARSER_ERROR___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__WIFI_PARSER_ERR___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LIMIT_ERR___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LENGTH_ERR___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__UNENCRYPTED_FRAME_ERR___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__TKIP_MIC_ERR___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__DECRYPT_ERR___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__FCS_ERR___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MPDU_LENGTH_ERR___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__OVERFLOW_ERR___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__AMSDU_PARSER_ERROR___M 0x38000000 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__AMSDU_PARSER_ERROR___S 27 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__WIFI_PARSER_ERR___M 0x07000000 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__WIFI_PARSER_ERR___S 24 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LIMIT_ERR___M 0x00E00000 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LIMIT_ERR___S 21 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LENGTH_ERR___M 0x001C0000 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LENGTH_ERR___S 18 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__UNENCRYPTED_FRAME_ERR___M 0x00038000 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__UNENCRYPTED_FRAME_ERR___S 15 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__TKIP_MIC_ERR___M 0x00007000 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__TKIP_MIC_ERR___S 12 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__DECRYPT_ERR___M 0x00000E00 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__DECRYPT_ERR___S 9 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__FCS_ERR___M 0x000001C0 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__FCS_ERR___S 6 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MPDU_LENGTH_ERR___M 0x00000038 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MPDU_LENGTH_ERR___S 3 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__OVERFLOW_ERR___M 0x00000007 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0__OVERFLOW_ERR___S 0 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0___M 0x3FFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX0___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1 (0x00A86438) +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1__AMSDU_FRAGMENT_ERROR___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLUSH_REQ___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLOW_IDX_TIMEOUT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1__DA_IDX_TIMEOUT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1__SA_IDX_TIMEOUT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1__AMSDU_FRAGMENT_ERROR___M 0x00007000 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1__AMSDU_FRAGMENT_ERROR___S 12 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLUSH_REQ___M 0x00000E00 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLUSH_REQ___S 9 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLOW_IDX_TIMEOUT___M 0x000001C0 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLOW_IDX_TIMEOUT___S 6 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1__DA_IDX_TIMEOUT___M 0x00000038 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1__DA_IDX_TIMEOUT___S 3 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1__SA_IDX_TIMEOUT___M 0x00000007 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1__SA_IDX_TIMEOUT___S 0 +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1___M 0x00007FFF +#define WMAC0_RXDMA_RXDMA_R0_SW_BUFFER_SOURCE_ERROR_ROUTING_IX1___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0 (0x00A8643C) +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__AMSDU_PARSER_ERROR___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__WIFI_PARSER_ERR___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LIMIT_ERR___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LENGTH_ERR___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__UNENCRYPTED_FRAME_ERR___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__TKIP_MIC_ERR___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__DECRYPT_ERR___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__FCS_ERR___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MPDU_LENGTH_ERR___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__OVERFLOW_ERR___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__AMSDU_PARSER_ERROR___M 0x38000000 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__AMSDU_PARSER_ERROR___S 27 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__WIFI_PARSER_ERR___M 0x07000000 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__WIFI_PARSER_ERR___S 24 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LIMIT_ERR___M 0x00E00000 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LIMIT_ERR___S 21 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LENGTH_ERR___M 0x001C0000 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MSDU_LENGTH_ERR___S 18 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__UNENCRYPTED_FRAME_ERR___M 0x00038000 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__UNENCRYPTED_FRAME_ERR___S 15 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__TKIP_MIC_ERR___M 0x00007000 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__TKIP_MIC_ERR___S 12 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__DECRYPT_ERR___M 0x00000E00 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__DECRYPT_ERR___S 9 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__FCS_ERR___M 0x000001C0 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__FCS_ERR___S 6 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MPDU_LENGTH_ERR___M 0x00000038 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__MPDU_LENGTH_ERR___S 3 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__OVERFLOW_ERR___M 0x00000007 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0__OVERFLOW_ERR___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0___M 0x3FFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX0___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1 (0x00A86440) +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1__AMSDU_FRAGMENT_ERROR___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLUSH_REQ___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLOW_IDX_TIMEOUT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1__DA_IDX_TIMEOUT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1__SA_IDX_TIMEOUT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1__AMSDU_FRAGMENT_ERROR___M 0x00007000 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1__AMSDU_FRAGMENT_ERROR___S 12 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLUSH_REQ___M 0x00000E00 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLUSH_REQ___S 9 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLOW_IDX_TIMEOUT___M 0x000001C0 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1__FLOW_IDX_TIMEOUT___S 6 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1__DA_IDX_TIMEOUT___M 0x00000038 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1__DA_IDX_TIMEOUT___S 3 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1__SA_IDX_TIMEOUT___M 0x00000007 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1__SA_IDX_TIMEOUT___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1___M 0x00007FFF +#define WMAC0_RXDMA_RXDMA_R0_FW_BUFFER_SOURCE_ERROR_ROUTING_IX1___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2 (0x00A86444) +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2___POR 0x00000020 +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__BUS_REQUEST_AT_SFM_NEARLY_FULL_EN___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__DESC_FIFO_PENDING_EN___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__DESC_WRITE_AT_USER_STATS_TRIG_EN___POR 0x1 +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__WAIT_FOR_LINK_WRITE_COMPLETE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__WAIT_FOR_MPDU_COMPLETE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__BUS_REQUEST_AT_MSDU_END_EN___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__IDLE_FLAG___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__HOLD_DMA___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__BUS_REQUEST_AT_SFM_NEARLY_FULL_EN___M 0x00000180 +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__BUS_REQUEST_AT_SFM_NEARLY_FULL_EN___S 7 +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__DESC_FIFO_PENDING_EN___M 0x00000040 +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__DESC_FIFO_PENDING_EN___S 6 +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__DESC_WRITE_AT_USER_STATS_TRIG_EN___M 0x00000020 +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__DESC_WRITE_AT_USER_STATS_TRIG_EN___S 5 +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__WAIT_FOR_LINK_WRITE_COMPLETE___M 0x00000010 +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__WAIT_FOR_LINK_WRITE_COMPLETE___S 4 +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__WAIT_FOR_MPDU_COMPLETE___M 0x00000008 +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__WAIT_FOR_MPDU_COMPLETE___S 3 +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__BUS_REQUEST_AT_MSDU_END_EN___M 0x00000004 +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__BUS_REQUEST_AT_MSDU_END_EN___S 2 +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__IDLE_FLAG___M 0x00000002 +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__IDLE_FLAG___S 1 +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__HOLD_DMA___M 0x00000001 +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2__HOLD_DMA___S 0 +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2___M 0x000001FF +#define WMAC0_RXDMA_RXDMA_R0_CFG_MISC_2___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER (0x00A86448) +#define WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER___POR 0x00000100 +#define WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__RING_CFG_ACCESS___POR 0x1 +#define WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__FW2RXDMA_LINK_FIFO_RESET___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__WBM2RXDMA_LINK_FIFO_RESET___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__FW2RXDMA1_STATBUF_FIFO_RESET___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__FW2RXDMA_STATBUF_FIFO_RESET___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__SW2RXDMA_BUF_FIFO_RESET___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__FW2RXDMA_BUF_FIFO_RESET___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__WBM2RXDMA_BUF_FIFO_RESET___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__ENABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__RING_CFG_ACCESS___M 0x00000100 +#define WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__RING_CFG_ACCESS___S 8 +#define WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__FW2RXDMA_LINK_FIFO_RESET___M 0x00000080 +#define WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__FW2RXDMA_LINK_FIFO_RESET___S 7 +#define WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__WBM2RXDMA_LINK_FIFO_RESET___M 0x00000040 +#define WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__WBM2RXDMA_LINK_FIFO_RESET___S 6 +#define WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__FW2RXDMA1_STATBUF_FIFO_RESET___M 0x00000020 +#define WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__FW2RXDMA1_STATBUF_FIFO_RESET___S 5 +#define WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__FW2RXDMA_STATBUF_FIFO_RESET___M 0x00000010 +#define WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__FW2RXDMA_STATBUF_FIFO_RESET___S 4 +#define WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__SW2RXDMA_BUF_FIFO_RESET___M 0x00000008 +#define WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__SW2RXDMA_BUF_FIFO_RESET___S 3 +#define WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__FW2RXDMA_BUF_FIFO_RESET___M 0x00000004 +#define WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__FW2RXDMA_BUF_FIFO_RESET___S 2 +#define WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__WBM2RXDMA_BUF_FIFO_RESET___M 0x00000002 +#define WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__WBM2RXDMA_BUF_FIFO_RESET___S 1 +#define WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__ENABLE___M 0x00000001 +#define WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER__ENABLE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER___M 0x000001FF +#define WMAC0_RXDMA_RXDMA_R0_GLOBAL_RER___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_TRC_EVENTMASK_IX_0 (0x00A8644C) +#define WMAC0_RXDMA_RXDMA_R0_TRC_EVENTMASK_IX_0___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_TRC_EVENTMASK_IX_0___POR 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_TRC_EVENTMASK_IX_0__MASK___POR 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_TRC_EVENTMASK_IX_0__MASK___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_TRC_EVENTMASK_IX_0__MASK___S 0 +#define WMAC0_RXDMA_RXDMA_R0_TRC_EVENTMASK_IX_0___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_TRC_EVENTMASK_IX_0___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_TRC_EVENTMASK_IX_1 (0x00A86450) +#define WMAC0_RXDMA_RXDMA_R0_TRC_EVENTMASK_IX_1___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_TRC_EVENTMASK_IX_1___POR 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_TRC_EVENTMASK_IX_1__MASK___POR 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_TRC_EVENTMASK_IX_1__MASK___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_TRC_EVENTMASK_IX_1__MASK___S 0 +#define WMAC0_RXDMA_RXDMA_R0_TRC_EVENTMASK_IX_1___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_TRC_EVENTMASK_IX_1___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_PERFORMANCE (0x00A86454) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_PERFORMANCE___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_PERFORMANCE___POR 0x00000800 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_PERFORMANCE__DEST_RING_POSTED_COUNTER___POR 0x200 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_PERFORMANCE__DEST_RING_POSTED_FIX___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_PERFORMANCE__RX_ATTEN_FIX___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_PERFORMANCE__DEST_RING_POSTED_COUNTER___M 0x00000FFC +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_PERFORMANCE__DEST_RING_POSTED_COUNTER___S 2 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_PERFORMANCE__DEST_RING_POSTED_FIX___M 0x00000002 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_PERFORMANCE__DEST_RING_POSTED_FIX___S 1 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_PERFORMANCE__RX_ATTEN_FIX___M 0x00000001 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_PERFORMANCE__RX_ATTEN_FIX___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_PERFORMANCE___M 0x00000FFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_PERFORMANCE___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_FRAMELESS_BAR_CFG (0x00A86458) +#define WMAC0_RXDMA_RXDMA_R0_FRAMELESS_BAR_CFG___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_FRAMELESS_BAR_CFG___POR 0x00000007 +#define WMAC0_RXDMA_RXDMA_R0_FRAMELESS_BAR_CFG__DEST_RING_SELECT___POR 0x3 +#define WMAC0_RXDMA_RXDMA_R0_FRAMELESS_BAR_CFG__DROP___POR 0x1 +#define WMAC0_RXDMA_RXDMA_R0_FRAMELESS_BAR_CFG__DEST_RING_SELECT___M 0x00000006 +#define WMAC0_RXDMA_RXDMA_R0_FRAMELESS_BAR_CFG__DEST_RING_SELECT___S 1 +#define WMAC0_RXDMA_RXDMA_R0_FRAMELESS_BAR_CFG__DROP___M 0x00000001 +#define WMAC0_RXDMA_RXDMA_R0_FRAMELESS_BAR_CFG__DROP___S 0 +#define WMAC0_RXDMA_RXDMA_R0_FRAMELESS_BAR_CFG___M 0x00000007 +#define WMAC0_RXDMA_RXDMA_R0_FRAMELESS_BAR_CFG___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_0 (0x00A8645C) +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_0___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_0___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_0__SW2RXDMA_BUF_RING_THRESHOLD___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_0__FW2RXDMA_BUF_RING_THRESHOLD___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_0__WBM2RXDMA_BUF_RING_THRESHOLD___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_0__SW2RXDMA_BUF_RING_THRESHOLD___M 0x3FF00000 +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_0__SW2RXDMA_BUF_RING_THRESHOLD___S 20 +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_0__FW2RXDMA_BUF_RING_THRESHOLD___M 0x000FFC00 +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_0__FW2RXDMA_BUF_RING_THRESHOLD___S 10 +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_0__WBM2RXDMA_BUF_RING_THRESHOLD___M 0x000003FF +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_0__WBM2RXDMA_BUF_RING_THRESHOLD___S 0 +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_0___M 0x3FFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_0___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_1 (0x00A86460) +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_1___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_1___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_1__FW2RXDMA1_STATBUF_RING_THRESHOLD___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_1__FW2RXDMA_STATBUF_RING_THRESHOLD___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_1__FW2RXDMA1_STATBUF_RING_THRESHOLD___M 0x000FFC00 +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_1__FW2RXDMA1_STATBUF_RING_THRESHOLD___S 10 +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_1__FW2RXDMA_STATBUF_RING_THRESHOLD___M 0x000003FF +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_1__FW2RXDMA_STATBUF_RING_THRESHOLD___S 0 +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_1___M 0x000FFFFF +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_SOURCE_RING_THRESHOLD_1___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_LINK_RING_THRESHOLD (0x00A86464) +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_LINK_RING_THRESHOLD___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_LINK_RING_THRESHOLD___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_LINK_RING_THRESHOLD__FW2RXDMA_LINK_RING_THRESHOLD___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_LINK_RING_THRESHOLD__WBM2RXDMA_LINK_RING_THRESHOLD___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_LINK_RING_THRESHOLD__FW2RXDMA_LINK_RING_THRESHOLD___M 0x000FFC00 +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_LINK_RING_THRESHOLD__FW2RXDMA_LINK_RING_THRESHOLD___S 10 +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_LINK_RING_THRESHOLD__WBM2RXDMA_LINK_RING_THRESHOLD___M 0x000003FF +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_LINK_RING_THRESHOLD__WBM2RXDMA_LINK_RING_THRESHOLD___S 0 +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_LINK_RING_THRESHOLD___M 0x000FFFFF +#define WMAC0_RXDMA_RXDMA_R0_MONITOR_MODE_LINK_RING_THRESHOLD___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_UNUSED_CFG (0x00A86468) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_UNUSED_CFG___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_UNUSED_CFG___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_UNUSED_CFG__UNUSED___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_UNUSED_CFG__UNUSED___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_UNUSED_CFG__UNUSED___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_UNUSED_CFG___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_UNUSED_CFG___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_SFM_RXDMA_BUFFER_THR (0x00A8646C) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_SFM_RXDMA_BUFFER_THR___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_SFM_RXDMA_BUFFER_THR___POR 0x00010000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_SFM_RXDMA_BUFFER_THR__MAX_USED_BUFFER_CNT___POR 0x020 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_SFM_RXDMA_BUFFER_THR__MIN_FREE_BUFFER_CNT___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_SFM_RXDMA_BUFFER_THR__MAX_USED_BUFFER_CNT___M 0x003FF800 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_SFM_RXDMA_BUFFER_THR__MAX_USED_BUFFER_CNT___S 11 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_SFM_RXDMA_BUFFER_THR__MIN_FREE_BUFFER_CNT___M 0x000007FF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_SFM_RXDMA_BUFFER_THR__MIN_FREE_BUFFER_CNT___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_SFM_RXDMA_BUFFER_THR___M 0x003FFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_SFM_RXDMA_BUFFER_THR___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_ERROR_RECOVERY_CFG (0x00A86470) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_ERROR_RECOVERY_CFG___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_ERROR_RECOVERY_CFG___POR 0x00000001 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_ERROR_RECOVERY_CFG__STATUS___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_ERROR_RECOVERY_CFG__ENABLE___POR 0x1 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_ERROR_RECOVERY_CFG__STATUS___M 0x00000002 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_ERROR_RECOVERY_CFG__STATUS___S 1 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_ERROR_RECOVERY_CFG__ENABLE___M 0x00000001 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_ERROR_RECOVERY_CFG__ENABLE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_ERROR_RECOVERY_CFG___M 0x00000003 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_ERROR_RECOVERY_CFG___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_END_OF_TEST (0x00A86474) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_END_OF_TEST___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_END_OF_TEST___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_END_OF_TEST__STATUS___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_END_OF_TEST__CFG___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_END_OF_TEST__STATUS___M 0x00000002 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_END_OF_TEST__STATUS___S 1 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_END_OF_TEST__CFG___M 0x00000001 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_END_OF_TEST__CFG___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_END_OF_TEST___M 0x00000003 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_END_OF_TEST___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE (0x00A86478) +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__RING_THRESHOLD_FILTER_MPDU_DROP___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__REO_RING_MPDU_RCVD___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__SW_RING_MPDU_RCVD___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__FW_RING_MPDU_RCVD___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__RELEASE_RING_MPDU_RCVD___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__TOTAL_MPDU_RCVD___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__TOTAL_PPDU_RCVD___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__RING_THRESHOLD_FILTER_MPDU_DROP___M 0x00000040 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__RING_THRESHOLD_FILTER_MPDU_DROP___S 6 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__REO_RING_MPDU_RCVD___M 0x00000020 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__REO_RING_MPDU_RCVD___S 5 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__SW_RING_MPDU_RCVD___M 0x00000010 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__SW_RING_MPDU_RCVD___S 4 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__FW_RING_MPDU_RCVD___M 0x00000008 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__FW_RING_MPDU_RCVD___S 3 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__RELEASE_RING_MPDU_RCVD___M 0x00000004 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__RELEASE_RING_MPDU_RCVD___S 2 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__TOTAL_MPDU_RCVD___M 0x00000002 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__TOTAL_MPDU_RCVD___S 1 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__TOTAL_PPDU_RCVD___M 0x00000001 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE__TOTAL_PPDU_RCVD___S 0 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE___M 0x0000007F +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_COUNTER_ENABLE___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SELECT (0x00A8647C) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SELECT___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SELECT___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SELECT__USER___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SELECT__USER___M 0x0000003F +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SELECT__USER___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SELECT___M 0x0000003F +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SELECT___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_LSB (0x00A86480) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_LSB___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_LSB__PTR_31_0___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_LSB__PTR_31_0___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_LSB__PTR_31_0___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_MSB (0x00A86484) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_MSB___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_MSB__PTR_63_32___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_MSB__PTR_63_32___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_MSB__PTR_63_32___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_MSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_WBM2RXDMA_PTR_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_LSB (0x00A86488) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_LSB___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_LSB__PTR_31_0___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_LSB__PTR_31_0___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_LSB__PTR_31_0___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_MSB (0x00A8648C) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_MSB___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_MSB__PTR_63_32___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_MSB__PTR_63_32___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_MSB__PTR_63_32___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_MSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_FW2RXDMA_PTR_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_LSB (0x00A86490) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_LSB___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_LSB__PTR_31_0___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_LSB__PTR_31_0___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_LSB__PTR_31_0___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_MSB (0x00A86494) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_MSB___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_MSB__PTR_63_32___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_MSB__PTR_63_32___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_MSB__PTR_63_32___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_MSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_SW2RXDMA_PTR_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS (0x00A86498) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__RXDMA2REO_DEST_DESC_FIFO_POPCOUNT___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__RXDMA2SW_DEST_DESC_FIFO_POPCOUNT___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__RXDMA2FW_DEST_DESC_FIFO_POPCOUNT___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__RXDMA_RELEASE_DEST_DESC_FIFO_POPCOUNT___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__MSDU_BUF_CNT_IN_LINK___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__SW2RXDMA_PTR_VALID___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__FW2RXDMA_PTR_VALID___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__WBM2RXDMA_PTR_VALID___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__RXDMA2REO_DEST_DESC_FIFO_POPCOUNT___M 0x07C00000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__RXDMA2REO_DEST_DESC_FIFO_POPCOUNT___S 22 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__RXDMA2SW_DEST_DESC_FIFO_POPCOUNT___M 0x003E0000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__RXDMA2SW_DEST_DESC_FIFO_POPCOUNT___S 17 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__RXDMA2FW_DEST_DESC_FIFO_POPCOUNT___M 0x0001F000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__RXDMA2FW_DEST_DESC_FIFO_POPCOUNT___S 12 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__RXDMA_RELEASE_DEST_DESC_FIFO_POPCOUNT___M 0x00000F80 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__RXDMA_RELEASE_DEST_DESC_FIFO_POPCOUNT___S 7 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__MSDU_BUF_CNT_IN_LINK___M 0x00000078 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__MSDU_BUF_CNT_IN_LINK___S 3 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__SW2RXDMA_PTR_VALID___M 0x00000004 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__SW2RXDMA_PTR_VALID___S 2 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__FW2RXDMA_PTR_VALID___M 0x00000002 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__FW2RXDMA_PTR_VALID___S 1 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__WBM2RXDMA_PTR_VALID___M 0x00000001 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS__WBM2RXDMA_PTR_VALID___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS___M 0x07FFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_STATS___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH (0x00A8649C) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__RXDMA2REO_DEST_DESC_FIFO_READ___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__RXDMA2SW_DEST_DESC_FIFO_READ___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__RXDMA2FW_DEST_DESC_FIFO_READ___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__RXDMA_RELEASE_DEST_DESC_FIFO_READ___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__APB_ACCES_TO_MEM___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__DISABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__RXDMA2REO_DEST_DESC_FIFO_READ___M 0x00000020 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__RXDMA2REO_DEST_DESC_FIFO_READ___S 5 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__RXDMA2SW_DEST_DESC_FIFO_READ___M 0x00000010 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__RXDMA2SW_DEST_DESC_FIFO_READ___S 4 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__RXDMA2FW_DEST_DESC_FIFO_READ___M 0x00000008 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__RXDMA2FW_DEST_DESC_FIFO_READ___S 3 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__RXDMA_RELEASE_DEST_DESC_FIFO_READ___M 0x00000004 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__RXDMA_RELEASE_DEST_DESC_FIFO_READ___S 2 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__APB_ACCES_TO_MEM___M 0x00000002 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__APB_ACCES_TO_MEM___S 1 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__DISABLE___M 0x00000001 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH__DISABLE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH___M 0x0000003F +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_DISABLE_CFG_FLUSH___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_LSB (0x00A864A0) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_LSB___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_LSB__DATA_31_0___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_LSB__DATA_31_0___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_LSB__DATA_31_0___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_MSB (0x00A864A4) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_MSB___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_MSB__DATA_63_32___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_MSB__DATA_63_32___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_MSB__DATA_63_32___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_MSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_RELEASE_DEST_DESC_FIFO_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_LSB (0x00A864A8) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_LSB___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_LSB__DATA_31_0___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_LSB__DATA_31_0___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_LSB__DATA_31_0___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_MSB (0x00A864AC) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_MSB___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_MSB__DATA_63_32___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_MSB__DATA_63_32___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_MSB__DATA_63_32___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_MSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2FW_DEST_DESC_FIFO_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_LSB (0x00A864B0) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_LSB___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_LSB__DATA_31_0___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_LSB__DATA_31_0___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_LSB__DATA_31_0___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_MSB (0x00A864B4) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_MSB___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_MSB__DATA_63_32___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_MSB__DATA_63_32___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_MSB__DATA_63_32___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_MSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2SW_DEST_DESC_FIFO_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_LSB (0x00A864B8) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_LSB___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_LSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_LSB__DATA_31_0___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_LSB__DATA_31_0___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_LSB__DATA_31_0___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_LSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_LSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_MSB (0x00A864BC) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_MSB___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_MSB___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_MSB__DATA_63_32___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_MSB__DATA_63_32___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_MSB__DATA_63_32___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_MSB___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_RXDMA2REO_DEST_DESC_FIFO_MSB___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_TLV_SEQ_STAT (0x00A864C0) +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_TLV_SEQ_STAT___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_TLV_SEQ_STAT___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_TLV_SEQ_STAT__TLV_SEQ_USER_STATS___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_TLV_SEQ_STAT__TLV_SEQ_USER_STATS___M 0x0000003F +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_TLV_SEQ_STAT__TLV_SEQ_USER_STATS___S 0 +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_TLV_SEQ_STAT___M 0x0000003F +#define WMAC0_RXDMA_RXDMA_R0_RXDMA_USER_TLV_SEQ_STAT___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_ADDR (0x00A864C4) +#define WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_ADDR___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_ADDR___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_ADDR__VALUE___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_ADDR__VALUE___M 0x000007FF +#define WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_ADDR__VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_ADDR___M 0x000007FF +#define WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_ADDR___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_DATA (0x00A864C8) +#define WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_DATA___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_DATA___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_DATA__VALUE___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_DATA__VALUE___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_DATA__VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_DATA___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_MSDU_LINK_MEM_DATA___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_PPDU_RCVD (0x00A864CC) +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_PPDU_RCVD___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_PPDU_RCVD___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_PPDU_RCVD__COUNT___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_PPDU_RCVD__COUNT___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_PPDU_RCVD__COUNT___S 0 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_PPDU_RCVD___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_PPDU_RCVD___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_MPDU_RCVD (0x00A864D0) +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_MPDU_RCVD___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_MPDU_RCVD___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_MPDU_RCVD__COUNT___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_MPDU_RCVD__COUNT___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_MPDU_RCVD__COUNT___S 0 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_MPDU_RCVD___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_MPDU_RCVD___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_1 (0x00A864D4) +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_1___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_1___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_1__FW_COUNT___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_1__RELEASE_COUNT___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_1__FW_COUNT___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_1__FW_COUNT___S 16 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_1__RELEASE_COUNT___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_1__RELEASE_COUNT___S 0 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_1___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_1___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_2 (0x00A864D8) +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_2___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_2___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_2__REO_COUNT___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_2__SW_COUNT___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_2__REO_COUNT___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_2__REO_COUNT___S 16 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_2__SW_COUNT___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_2__SW_COUNT___S 0 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_2___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_DEST_RING_MPDU_RCVD_2___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_RING_THRESHOLD_MPDU_DROP (0x00A864DC) +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_RING_THRESHOLD_MPDU_DROP___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_RING_THRESHOLD_MPDU_DROP___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_RING_THRESHOLD_MPDU_DROP__COUNT___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_RING_THRESHOLD_MPDU_DROP__COUNT___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_RING_THRESHOLD_MPDU_DROP__COUNT___S 0 +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_RING_THRESHOLD_MPDU_DROP___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_DEBUG_RING_THRESHOLD_MPDU_DROP___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_WDOG (0x00A864E0) +#define WMAC0_RXDMA_RXDMA_R0_WDOG___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_WDOG___POR 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_WDOG__LIMIT___POR 0xFFFF +#define WMAC0_RXDMA_RXDMA_R0_WDOG__LIMIT___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_WDOG__LIMIT___S 0 +#define WMAC0_RXDMA_RXDMA_R0_WDOG___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R0_WDOG___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_TESTBUS_CTRL (0x00A864E4) +#define WMAC0_RXDMA_RXDMA_R0_TESTBUS_CTRL___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_TESTBUS_CTRL___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_TESTBUS_CTRL__SELECT___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R0_TESTBUS_CTRL__SELECT___M 0x0000003F +#define WMAC0_RXDMA_RXDMA_R0_TESTBUS_CTRL__SELECT___S 0 +#define WMAC0_RXDMA_RXDMA_R0_TESTBUS_CTRL___M 0x0000003F +#define WMAC0_RXDMA_RXDMA_R0_TESTBUS_CTRL___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_CLOCK_GATE (0x00A864E8) +#define WMAC0_RXDMA_RXDMA_R0_CLOCK_GATE___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R0_CLOCK_GATE___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_CLOCK_GATE__DISABLE___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_CLOCK_GATE__DISABLE___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_CLOCK_GATE__DISABLE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_CLOCK_GATE___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R0_CLOCK_GATE___S 0 + +#define WMAC0_RXDMA_RXDMA_R0_INVALID_APB_ACC_ADR (0x00A864EC) +#define WMAC0_RXDMA_RXDMA_R0_INVALID_APB_ACC_ADR___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R0_INVALID_APB_ACC_ADR___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R0_INVALID_APB_ACC_ADR__VALUE___POR 0x00000 +#define WMAC0_RXDMA_RXDMA_R0_INVALID_APB_ACC_ADR__VALUE___M 0x0001FFFF +#define WMAC0_RXDMA_RXDMA_R0_INVALID_APB_ACC_ADR__VALUE___S 0 +#define WMAC0_RXDMA_RXDMA_R0_INVALID_APB_ACC_ADR___M 0x0001FFFF +#define WMAC0_RXDMA_RXDMA_R0_INVALID_APB_ACC_ADR___S 0 + +#define WMAC0_RXDMA_RXDMA_R1_REG_ACCESS_EVENT_GEN_CTRL (0x00A87000) +#define WMAC0_RXDMA_RXDMA_R1_REG_ACCESS_EVENT_GEN_CTRL___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R1_REG_ACCESS_EVENT_GEN_CTRL___POR 0x7FFE0002 +#define WMAC0_RXDMA_RXDMA_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___POR 0x3FFF +#define WMAC0_RXDMA_RXDMA_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___POR 0x1 +#define WMAC0_RXDMA_RXDMA_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___M 0xFFFE0000 +#define WMAC0_RXDMA_RXDMA_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___S 17 +#define WMAC0_RXDMA_RXDMA_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___M 0x0001FFFC +#define WMAC0_RXDMA_RXDMA_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___S 2 +#define WMAC0_RXDMA_RXDMA_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___M 0x00000002 +#define WMAC0_RXDMA_RXDMA_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___S 1 +#define WMAC0_RXDMA_RXDMA_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___M 0x00000001 +#define WMAC0_RXDMA_RXDMA_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___S 0 +#define WMAC0_RXDMA_RXDMA_R1_REG_ACCESS_EVENT_GEN_CTRL___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R1_REG_ACCESS_EVENT_GEN_CTRL___S 0 + +#define WMAC0_RXDMA_RXDMA_R1_TESTBUS_LOWER (0x00A87004) +#define WMAC0_RXDMA_RXDMA_R1_TESTBUS_LOWER___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R1_TESTBUS_LOWER___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R1_TESTBUS_LOWER__VAL___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R1_TESTBUS_LOWER__VAL___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R1_TESTBUS_LOWER__VAL___S 0 +#define WMAC0_RXDMA_RXDMA_R1_TESTBUS_LOWER___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R1_TESTBUS_LOWER___S 0 + +#define WMAC0_RXDMA_RXDMA_R1_TESTBUS_UPPER (0x00A87008) +#define WMAC0_RXDMA_RXDMA_R1_TESTBUS_UPPER___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R1_TESTBUS_UPPER___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R1_TESTBUS_UPPER__VAL___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R1_TESTBUS_UPPER__VAL___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R1_TESTBUS_UPPER__VAL___S 0 +#define WMAC0_RXDMA_RXDMA_R1_TESTBUS_UPPER___M 0x000000FF +#define WMAC0_RXDMA_RXDMA_R1_TESTBUS_UPPER___S 0 + +#define WMAC0_RXDMA_RXDMA_R1_SM_STATUS (0x00A8700C) +#define WMAC0_RXDMA_RXDMA_R1_SM_STATUS___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R1_SM_STATUS___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R1_SM_STATUS__RXDMA_LINK_DESC_WRITE_CTL_FIFO_STATE___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R1_SM_STATUS__RXDMA_RCV_CTL_STATE___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R1_SM_STATUS__RXDMA_LINK_GEN_CTL_STATE___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R1_SM_STATUS__RXDMA_LINK_DESC_WRITE_CTL_STATE___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R1_SM_STATUS__RXDMA_SFM_CTL_STATE___POR 0x000 +#define WMAC0_RXDMA_RXDMA_R1_SM_STATUS__RXDMA_LINK_DESC_WRITE_CTL_FIFO_STATE___M 0x7F800000 +#define WMAC0_RXDMA_RXDMA_R1_SM_STATUS__RXDMA_LINK_DESC_WRITE_CTL_FIFO_STATE___S 23 +#define WMAC0_RXDMA_RXDMA_R1_SM_STATUS__RXDMA_RCV_CTL_STATE___M 0x007C0000 +#define WMAC0_RXDMA_RXDMA_R1_SM_STATUS__RXDMA_RCV_CTL_STATE___S 18 +#define WMAC0_RXDMA_RXDMA_R1_SM_STATUS__RXDMA_LINK_GEN_CTL_STATE___M 0x0003E000 +#define WMAC0_RXDMA_RXDMA_R1_SM_STATUS__RXDMA_LINK_GEN_CTL_STATE___S 13 +#define WMAC0_RXDMA_RXDMA_R1_SM_STATUS__RXDMA_LINK_DESC_WRITE_CTL_STATE___M 0x00001E00 +#define WMAC0_RXDMA_RXDMA_R1_SM_STATUS__RXDMA_LINK_DESC_WRITE_CTL_STATE___S 9 +#define WMAC0_RXDMA_RXDMA_R1_SM_STATUS__RXDMA_SFM_CTL_STATE___M 0x000001FF +#define WMAC0_RXDMA_RXDMA_R1_SM_STATUS__RXDMA_SFM_CTL_STATE___S 0 +#define WMAC0_RXDMA_RXDMA_R1_SM_STATUS___M 0x7FFFFFFF +#define WMAC0_RXDMA_RXDMA_R1_SM_STATUS___S 0 + +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG (0x00A87010) +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG__STATUS_TLV_EXCEEDED_BUF_LEN___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG__IDLE_STATUS___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG__USER_ID___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG__TLV_TYPE___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG__RINGMASK___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG__STATUS_TLV_EXCEEDED_BUF_LEN___M 0x00800000 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG__STATUS_TLV_EXCEEDED_BUF_LEN___S 23 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG__IDLE_STATUS___M 0x007F8000 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG__IDLE_STATUS___S 15 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG__USER_ID___M 0x00007E00 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG__USER_ID___S 9 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG__TLV_TYPE___M 0x000001F0 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG__TLV_TYPE___S 4 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG__RINGMASK___M 0x0000000F +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG__RINGMASK___S 0 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG___M 0x00FFFFFF +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_RCV_DBG___S 0 + +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_SRING_STATUS (0x00A87014) +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_SRING_STATUS___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_SRING_STATUS___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_SRING_STATUS__DESTINATION_RING_NOT_FULL___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_SRING_STATUS__SOURCE_RING_NOT_EMPTY___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_SRING_STATUS__DESTINATION_RING_NOT_FULL___M 0x00000780 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_SRING_STATUS__DESTINATION_RING_NOT_FULL___S 7 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_SRING_STATUS__SOURCE_RING_NOT_EMPTY___M 0x0000007F +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_SRING_STATUS__SOURCE_RING_NOT_EMPTY___S 0 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_SRING_STATUS___M 0x000007FF +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_SRING_STATUS___S 0 + +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1 (0x00A87018) +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__RXDMA_WDOG_STATUS___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__USR_ID___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__RXDMA_RCV_CTL_STATE___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__TLV_TYPE___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__RINGMASK___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__DESTINATION_RING_NOT_FULL___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__SOURCE_RING_NOT_EMPTY___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__RXDMA_WDOG_STATUS___M 0x80000000 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__RXDMA_WDOG_STATUS___S 31 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__USR_ID___M 0x7E000000 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__USR_ID___S 25 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__RXDMA_RCV_CTL_STATE___M 0x01F00000 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__RXDMA_RCV_CTL_STATE___S 20 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__TLV_TYPE___M 0x000F8000 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__TLV_TYPE___S 15 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__RINGMASK___M 0x00007800 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__RINGMASK___S 11 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__DESTINATION_RING_NOT_FULL___M 0x00000780 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__DESTINATION_RING_NOT_FULL___S 7 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__SOURCE_RING_NOT_EMPTY___M 0x0000007F +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1__SOURCE_RING_NOT_EMPTY___S 0 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_1___S 0 + +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2 (0x00A8701C) +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2___RWC QCSR_REG_RO +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__RXDMA_WDOG_STATUS___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__USR_ID___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__RXDMA_RCV_CTL_STATE___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__TLV_TYPE___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__RINGMASK___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__DESTINATION_RING_NOT_FULL___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__SOURCE_RING_NOT_EMPTY___POR 0x00 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__RXDMA_WDOG_STATUS___M 0x80000000 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__RXDMA_WDOG_STATUS___S 31 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__USR_ID___M 0x7E000000 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__USR_ID___S 25 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__RXDMA_RCV_CTL_STATE___M 0x01F00000 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__RXDMA_RCV_CTL_STATE___S 20 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__TLV_TYPE___M 0x000F8000 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__TLV_TYPE___S 15 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__RINGMASK___M 0x00007800 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__RINGMASK___S 11 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__DESTINATION_RING_NOT_FULL___M 0x00000780 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__DESTINATION_RING_NOT_FULL___S 7 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__SOURCE_RING_NOT_EMPTY___M 0x0000007F +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2__SOURCE_RING_NOT_EMPTY___S 0 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_WDOG_STATUS_2___S 0 + +#define WMAC0_RXDMA_RXDMA_R1_TLV_OUTPUT_TRACKING_MAX_RANGE (0x00A87020) +#define WMAC0_RXDMA_RXDMA_R1_TLV_OUTPUT_TRACKING_MAX_RANGE___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R1_TLV_OUTPUT_TRACKING_MAX_RANGE___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R1_TLV_OUTPUT_TRACKING_MAX_RANGE__SW_COOKIE___POR 0x00000 +#define WMAC0_RXDMA_RXDMA_R1_TLV_OUTPUT_TRACKING_MAX_RANGE__SW_COOKIE___M 0x000FFFFF +#define WMAC0_RXDMA_RXDMA_R1_TLV_OUTPUT_TRACKING_MAX_RANGE__SW_COOKIE___S 0 +#define WMAC0_RXDMA_RXDMA_R1_TLV_OUTPUT_TRACKING_MAX_RANGE___M 0x000FFFFF +#define WMAC0_RXDMA_RXDMA_R1_TLV_OUTPUT_TRACKING_MAX_RANGE___S 0 + +#define WMAC0_RXDMA_RXDMA_R1_TLV_OUTPUT_TRACKING_MIN_RANGE (0x00A87024) +#define WMAC0_RXDMA_RXDMA_R1_TLV_OUTPUT_TRACKING_MIN_RANGE___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R1_TLV_OUTPUT_TRACKING_MIN_RANGE___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R1_TLV_OUTPUT_TRACKING_MIN_RANGE__SW_COOKIE___POR 0x00000 +#define WMAC0_RXDMA_RXDMA_R1_TLV_OUTPUT_TRACKING_MIN_RANGE__SW_COOKIE___M 0x000FFFFF +#define WMAC0_RXDMA_RXDMA_R1_TLV_OUTPUT_TRACKING_MIN_RANGE__SW_COOKIE___S 0 +#define WMAC0_RXDMA_RXDMA_R1_TLV_OUTPUT_TRACKING_MIN_RANGE___M 0x000FFFFF +#define WMAC0_RXDMA_RXDMA_R1_TLV_OUTPUT_TRACKING_MIN_RANGE___S 0 + +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_LINK_GXI_WRITE_WDOG (0x00A87028) +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_LINK_GXI_WRITE_WDOG___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_LINK_GXI_WRITE_WDOG___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_LINK_GXI_WRITE_WDOG__LINK_GXI_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_LINK_GXI_WRITE_WDOG__LINK_GXI_THRESHOLD___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_LINK_GXI_WRITE_WDOG__LINK_GXI_VALUE___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_LINK_GXI_WRITE_WDOG__LINK_GXI_VALUE___S 16 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_LINK_GXI_WRITE_WDOG__LINK_GXI_THRESHOLD___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_LINK_GXI_WRITE_WDOG__LINK_GXI_THRESHOLD___S 0 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_LINK_GXI_WRITE_WDOG___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_LINK_GXI_WRITE_WDOG___S 0 + +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_TLV_GXI_WRITE_WDOG (0x00A8702C) +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_TLV_GXI_WRITE_WDOG___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_TLV_GXI_WRITE_WDOG___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_TLV_GXI_WRITE_WDOG__TLV_GXI_VALUE___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_TLV_GXI_WRITE_WDOG__TLV_GXI_THRESHOLD___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_TLV_GXI_WRITE_WDOG__TLV_GXI_VALUE___M 0xFFFF0000 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_TLV_GXI_WRITE_WDOG__TLV_GXI_VALUE___S 16 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_TLV_GXI_WRITE_WDOG__TLV_GXI_THRESHOLD___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_TLV_GXI_WRITE_WDOG__TLV_GXI_THRESHOLD___S 0 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_TLV_GXI_WRITE_WDOG___M 0xFFFFFFFF +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_TLV_GXI_WRITE_WDOG___S 0 + +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_GXI_WRITE_WDOG_STATUS (0x00A87030) +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_GXI_WRITE_WDOG_STATUS___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_GXI_WRITE_WDOG_STATUS___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_GXI_WRITE_WDOG_STATUS__TLV_GXI_WRITE_TIMEOUT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_GXI_WRITE_WDOG_STATUS__LINK_GXI_WRITE_TIMEOUT___POR 0x0 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_GXI_WRITE_WDOG_STATUS__TLV_GXI_WRITE_TIMEOUT___M 0x00000002 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_GXI_WRITE_WDOG_STATUS__TLV_GXI_WRITE_TIMEOUT___S 1 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_GXI_WRITE_WDOG_STATUS__LINK_GXI_WRITE_TIMEOUT___M 0x00000001 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_GXI_WRITE_WDOG_STATUS__LINK_GXI_WRITE_TIMEOUT___S 0 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_GXI_WRITE_WDOG_STATUS___M 0x00000003 +#define WMAC0_RXDMA_RXDMA_R1_RXDMA_GXI_WRITE_WDOG_STATUS___S 0 + +#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_BUF_RING_HP (0x00A88000) +#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_BUF_RING_HP___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_BUF_RING_HP___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_BUF_RING_HP__HEAD_PTR___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_BUF_RING_HP__HEAD_PTR___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_BUF_RING_HP__HEAD_PTR___S 0 +#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_BUF_RING_HP___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_BUF_RING_HP___S 0 + +#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_BUF_RING_TP (0x00A88004) +#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_BUF_RING_TP___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_BUF_RING_TP___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_BUF_RING_TP__TAIL_PTR___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_BUF_RING_TP__TAIL_PTR___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_BUF_RING_TP__TAIL_PTR___S 0 +#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_BUF_RING_TP___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_BUF_RING_TP___S 0 + +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_BUF_RING_HP (0x00A88008) +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_BUF_RING_HP___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_BUF_RING_HP___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_BUF_RING_HP__HEAD_PTR___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_BUF_RING_HP__HEAD_PTR___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_BUF_RING_HP__HEAD_PTR___S 0 +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_BUF_RING_HP___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_BUF_RING_HP___S 0 + +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_BUF_RING_TP (0x00A8800C) +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_BUF_RING_TP___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_BUF_RING_TP___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_BUF_RING_TP__TAIL_PTR___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_BUF_RING_TP__TAIL_PTR___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_BUF_RING_TP__TAIL_PTR___S 0 +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_BUF_RING_TP___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_BUF_RING_TP___S 0 + +#define WMAC0_RXDMA_RXDMA_R2_SW2RXDMA_BUF_RING_HP (0x00A88010) +#define WMAC0_RXDMA_RXDMA_R2_SW2RXDMA_BUF_RING_HP___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R2_SW2RXDMA_BUF_RING_HP___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R2_SW2RXDMA_BUF_RING_HP__HEAD_PTR___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R2_SW2RXDMA_BUF_RING_HP__HEAD_PTR___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_SW2RXDMA_BUF_RING_HP__HEAD_PTR___S 0 +#define WMAC0_RXDMA_RXDMA_R2_SW2RXDMA_BUF_RING_HP___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_SW2RXDMA_BUF_RING_HP___S 0 + +#define WMAC0_RXDMA_RXDMA_R2_SW2RXDMA_BUF_RING_TP (0x00A88014) +#define WMAC0_RXDMA_RXDMA_R2_SW2RXDMA_BUF_RING_TP___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R2_SW2RXDMA_BUF_RING_TP___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R2_SW2RXDMA_BUF_RING_TP__TAIL_PTR___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R2_SW2RXDMA_BUF_RING_TP__TAIL_PTR___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_SW2RXDMA_BUF_RING_TP__TAIL_PTR___S 0 +#define WMAC0_RXDMA_RXDMA_R2_SW2RXDMA_BUF_RING_TP___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_SW2RXDMA_BUF_RING_TP___S 0 + +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_STATBUF_RING_HP (0x00A88018) +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_STATBUF_RING_HP___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_STATBUF_RING_HP___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_STATBUF_RING_HP__HEAD_PTR___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_STATBUF_RING_HP__HEAD_PTR___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_STATBUF_RING_HP__HEAD_PTR___S 0 +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_STATBUF_RING_HP___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_STATBUF_RING_HP___S 0 + +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_STATBUF_RING_TP (0x00A8801C) +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_STATBUF_RING_TP___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_STATBUF_RING_TP___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_STATBUF_RING_TP__TAIL_PTR___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_STATBUF_RING_TP__TAIL_PTR___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_STATBUF_RING_TP__TAIL_PTR___S 0 +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_STATBUF_RING_TP___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_STATBUF_RING_TP___S 0 + +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA1_STATBUF_RING_HP (0x00A88020) +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA1_STATBUF_RING_HP___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA1_STATBUF_RING_HP___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA1_STATBUF_RING_HP__HEAD_PTR___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA1_STATBUF_RING_HP__HEAD_PTR___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA1_STATBUF_RING_HP__HEAD_PTR___S 0 +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA1_STATBUF_RING_HP___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA1_STATBUF_RING_HP___S 0 + +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA1_STATBUF_RING_TP (0x00A88024) +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA1_STATBUF_RING_TP___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA1_STATBUF_RING_TP___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA1_STATBUF_RING_TP__TAIL_PTR___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA1_STATBUF_RING_TP__TAIL_PTR___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA1_STATBUF_RING_TP__TAIL_PTR___S 0 +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA1_STATBUF_RING_TP___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA1_STATBUF_RING_TP___S 0 + +#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_LINK_RING_HP (0x00A88028) +#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_LINK_RING_HP___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_LINK_RING_HP___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_LINK_RING_HP__HEAD_PTR___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_LINK_RING_HP__HEAD_PTR___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_LINK_RING_HP__HEAD_PTR___S 0 +#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_LINK_RING_HP___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_LINK_RING_HP___S 0 + +#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_LINK_RING_TP (0x00A8802C) +#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_LINK_RING_TP___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_LINK_RING_TP___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_LINK_RING_TP__TAIL_PTR___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_LINK_RING_TP__TAIL_PTR___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_LINK_RING_TP__TAIL_PTR___S 0 +#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_LINK_RING_TP___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_WBM2RXDMA_LINK_RING_TP___S 0 + +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_LINK_RING_HP (0x00A88030) +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_LINK_RING_HP___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_LINK_RING_HP___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_LINK_RING_HP__HEAD_PTR___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_LINK_RING_HP__HEAD_PTR___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_LINK_RING_HP__HEAD_PTR___S 0 +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_LINK_RING_HP___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_LINK_RING_HP___S 0 + +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_LINK_RING_TP (0x00A88034) +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_LINK_RING_TP___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_LINK_RING_TP___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_LINK_RING_TP__TAIL_PTR___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_LINK_RING_TP__TAIL_PTR___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_LINK_RING_TP__TAIL_PTR___S 0 +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_LINK_RING_TP___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_FW2RXDMA_LINK_RING_TP___S 0 + +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2REO_RING_HP (0x00A88038) +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2REO_RING_HP___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2REO_RING_HP___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2REO_RING_HP__HEAD_PTR___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2REO_RING_HP__HEAD_PTR___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2REO_RING_HP__HEAD_PTR___S 0 +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2REO_RING_HP___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2REO_RING_HP___S 0 + +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2REO_RING_TP (0x00A8803C) +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2REO_RING_TP___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2REO_RING_TP___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2REO_RING_TP__TAIL_PTR___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2REO_RING_TP__TAIL_PTR___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2REO_RING_TP__TAIL_PTR___S 0 +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2REO_RING_TP___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2REO_RING_TP___S 0 + +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2SW_RING_HP (0x00A88040) +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2SW_RING_HP___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2SW_RING_HP___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2SW_RING_HP__HEAD_PTR___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2SW_RING_HP__HEAD_PTR___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2SW_RING_HP__HEAD_PTR___S 0 +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2SW_RING_HP___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2SW_RING_HP___S 0 + +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2SW_RING_TP (0x00A88044) +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2SW_RING_TP___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2SW_RING_TP___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2SW_RING_TP__TAIL_PTR___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2SW_RING_TP__TAIL_PTR___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2SW_RING_TP__TAIL_PTR___S 0 +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2SW_RING_TP___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2SW_RING_TP___S 0 + +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2FW_RING_HP (0x00A88048) +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2FW_RING_HP___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2FW_RING_HP___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2FW_RING_HP__HEAD_PTR___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2FW_RING_HP__HEAD_PTR___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2FW_RING_HP__HEAD_PTR___S 0 +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2FW_RING_HP___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2FW_RING_HP___S 0 + +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2FW_RING_TP (0x00A8804C) +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2FW_RING_TP___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2FW_RING_TP___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2FW_RING_TP__TAIL_PTR___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2FW_RING_TP__TAIL_PTR___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2FW_RING_TP__TAIL_PTR___S 0 +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2FW_RING_TP___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_RXDMA2FW_RING_TP___S 0 + +#define WMAC0_RXDMA_RXDMA_R2_RXDMA_RELEASE_RING_HP (0x00A88050) +#define WMAC0_RXDMA_RXDMA_R2_RXDMA_RELEASE_RING_HP___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R2_RXDMA_RELEASE_RING_HP___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R2_RXDMA_RELEASE_RING_HP__HEAD_PTR___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R2_RXDMA_RELEASE_RING_HP__HEAD_PTR___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_RXDMA_RELEASE_RING_HP__HEAD_PTR___S 0 +#define WMAC0_RXDMA_RXDMA_R2_RXDMA_RELEASE_RING_HP___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_RXDMA_RELEASE_RING_HP___S 0 + +#define WMAC0_RXDMA_RXDMA_R2_RXDMA_RELEASE_RING_TP (0x00A88054) +#define WMAC0_RXDMA_RXDMA_R2_RXDMA_RELEASE_RING_TP___RWC QCSR_REG_RW +#define WMAC0_RXDMA_RXDMA_R2_RXDMA_RELEASE_RING_TP___POR 0x00000000 +#define WMAC0_RXDMA_RXDMA_R2_RXDMA_RELEASE_RING_TP__TAIL_PTR___POR 0x0000 +#define WMAC0_RXDMA_RXDMA_R2_RXDMA_RELEASE_RING_TP__TAIL_PTR___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_RXDMA_RELEASE_RING_TP__TAIL_PTR___S 0 +#define WMAC0_RXDMA_RXDMA_R2_RXDMA_RELEASE_RING_TP___M 0x0000FFFF +#define WMAC0_RXDMA_RXDMA_R2_RXDMA_RELEASE_RING_TP___S 0 + +#define WMAC0_MCMN_R0_MCMN_ISR_S0 (0x00A89000) +#define WMAC0_MCMN_R0_MCMN_ISR_S0___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_ISR_S0___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__RX_KEY_ID_RECV_NOT_VALID_KEY___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__RX_WATCHDOG_TIMEOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__OVER_CAPACITY_TX_USER___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__RX_KEY_ID_RECV_NOT_DEFAULT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__RX_NO_MU_KEY_TYPE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__TX_NO_MU_KEY_TYPE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__RX_IN_TX_DECRYPT_BYP_INT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__RX_TLV_READY_TMOUT_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__AH_DEC_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__AH_ENC_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__MIN_LENGTH_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__TX_FLUSH_REQ___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__RX_ABORT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__TX_ABORT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__DECRPT_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__RX_TLV_OUT_SEQ___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__TX_TLV_OUT_SEQ___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__CRYP_WD_TMOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__RX_KEY_ID_RECV_NOT_VALID_KEY___M 0x00020000 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__RX_KEY_ID_RECV_NOT_VALID_KEY___S 17 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__RX_WATCHDOG_TIMEOUT___M 0x00010000 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__RX_WATCHDOG_TIMEOUT___S 16 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__OVER_CAPACITY_TX_USER___M 0x00008000 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__OVER_CAPACITY_TX_USER___S 15 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__RX_KEY_ID_RECV_NOT_DEFAULT___M 0x00004000 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__RX_KEY_ID_RECV_NOT_DEFAULT___S 14 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__RX_NO_MU_KEY_TYPE___M 0x00002000 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__RX_NO_MU_KEY_TYPE___S 13 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__TX_NO_MU_KEY_TYPE___M 0x00001000 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__TX_NO_MU_KEY_TYPE___S 12 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__RX_IN_TX_DECRYPT_BYP_INT___M 0x00000800 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__RX_IN_TX_DECRYPT_BYP_INT___S 11 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__RX_TLV_READY_TMOUT_ERR___M 0x00000400 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__RX_TLV_READY_TMOUT_ERR___S 10 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__AH_DEC_ERR___M 0x00000200 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__AH_DEC_ERR___S 9 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__AH_ENC_ERR___M 0x00000100 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__AH_ENC_ERR___S 8 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__MIN_LENGTH_ERR___M 0x00000080 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__MIN_LENGTH_ERR___S 7 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__TX_FLUSH_REQ___M 0x00000040 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__TX_FLUSH_REQ___S 6 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__RX_ABORT___M 0x00000020 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__RX_ABORT___S 5 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__TX_ABORT___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__TX_ABORT___S 4 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__DECRPT_ERR___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__DECRPT_ERR___S 3 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__RX_TLV_OUT_SEQ___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__RX_TLV_OUT_SEQ___S 2 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__TX_TLV_OUT_SEQ___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__TX_TLV_OUT_SEQ___S 1 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__CRYP_WD_TMOUT___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_ISR_S0__CRYP_WD_TMOUT___S 0 +#define WMAC0_MCMN_R0_MCMN_ISR_S0___M 0x0003FFFF +#define WMAC0_MCMN_R0_MCMN_ISR_S0___S 0 + +#define WMAC0_MCMN_R0_MCMN_ISR_S1 (0x00A89004) +#define WMAC0_MCMN_R0_MCMN_ISR_S1___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_ISR_S1___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__SNOOP_RING_WATCHDOG_ERR_INT_P___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__SNOOP_RING_REQ_ERR_INT_P___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__UCODE_WDOG_TIMEOUT_INTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__SNOOP_WDOG_TIMEOUT_INTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__SNOOP_RING_SW_INT_P___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__TXDMA_RESERVED_INT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__UNEXPECT_NULL_LENGTH___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__MSDU_LENGTH_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__MSDU_LINK_GXI_TMOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__MSDU_LINK_EXT_GXI_TMOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__TX_DATA_GXI_TMOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__OLE_RDY_TMOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__UNEX_NUL_PTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__WDG_TMOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__INVA_IDX___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__MISSIN_TLV___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__UNEX_FES___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__INCOM_TLV___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__TX_DMA_IDLE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__SNOOP_RING_WATCHDOG_ERR_INT_P___M 0x00400000 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__SNOOP_RING_WATCHDOG_ERR_INT_P___S 22 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__SNOOP_RING_REQ_ERR_INT_P___M 0x00200000 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__SNOOP_RING_REQ_ERR_INT_P___S 21 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__UCODE_WDOG_TIMEOUT_INTR___M 0x00100000 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__UCODE_WDOG_TIMEOUT_INTR___S 20 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__SNOOP_WDOG_TIMEOUT_INTR___M 0x00080000 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__SNOOP_WDOG_TIMEOUT_INTR___S 19 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__SNOOP_RING_SW_INT_P___M 0x00040000 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__SNOOP_RING_SW_INT_P___S 18 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__TXDMA_RESERVED_INT___M 0x0003C000 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__TXDMA_RESERVED_INT___S 14 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__UNEXPECT_NULL_LENGTH___M 0x00002000 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__UNEXPECT_NULL_LENGTH___S 13 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__MSDU_LENGTH_ERR___M 0x00001000 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__MSDU_LENGTH_ERR___S 12 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__MSDU_LINK_GXI_TMOUT___M 0x00000800 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__MSDU_LINK_GXI_TMOUT___S 11 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__MSDU_LINK_EXT_GXI_TMOUT___M 0x00000400 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__MSDU_LINK_EXT_GXI_TMOUT___S 10 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__TX_DATA_GXI_TMOUT___M 0x00000200 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__TX_DATA_GXI_TMOUT___S 9 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__OLE_RDY_TMOUT___M 0x00000100 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__OLE_RDY_TMOUT___S 8 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__UNEX_NUL_PTR___M 0x00000080 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__UNEX_NUL_PTR___S 7 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__WDG_TMOUT___M 0x00000040 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__WDG_TMOUT___S 6 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__INVA_IDX___M 0x00000020 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__INVA_IDX___S 5 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__MISSIN_TLV___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__MISSIN_TLV___S 3 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__UNEX_FES___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__UNEX_FES___S 2 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__INCOM_TLV___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__INCOM_TLV___S 1 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__TX_DMA_IDLE___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_ISR_S1__TX_DMA_IDLE___S 0 +#define WMAC0_MCMN_R0_MCMN_ISR_S1___M 0x007FFFEF +#define WMAC0_MCMN_R0_MCMN_ISR_S1___S 0 + +#define WMAC0_MCMN_R0_MCMN_ISR_S2 (0x00A89008) +#define WMAC0_MCMN_R0_MCMN_ISR_S2___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_ISR_S2___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__BUS_REQUEST_AT_SFM_NEARLY_FULL_INTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__AMSDU_FRAG_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__RXDMA_RESERVED_2___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__SFM_READ_UNDERFLOW_ERROR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__SFM_WRITE_OVERFLOW_ERROR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__OVERFLOW_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__MPDU_LENGTH_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__FCS_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__DECRYPT_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__TKIP_MIC_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__UNENCRYPTED_FRAME_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__MSDU_LENGTH_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__WIFI_PARSER_ERROR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__AMSDU_PARSER_ERROR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__MSDU_LIMIT_ERROR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__SA_IDX_TIMEOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__DA_IDX_TIMEOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__FLOW_IDX_TIMEOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__FLUSH_REQUEST_COMPLETED___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__BUS_REQUEST___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__TLV_FRME_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__TLV_SHORT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__INVAL_TAG_ID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__INVALID_RINGMASK___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__NON_PKT_BUF___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__RXDMA_WD_TOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__BUS_REQUEST_AT_SFM_NEARLY_FULL_INTR___M 0x04000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__BUS_REQUEST_AT_SFM_NEARLY_FULL_INTR___S 26 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__AMSDU_FRAG_ERR___M 0x02000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__AMSDU_FRAG_ERR___S 25 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__RXDMA_RESERVED_2___M 0x01800000 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__RXDMA_RESERVED_2___S 23 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__SFM_READ_UNDERFLOW_ERROR___M 0x00400000 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__SFM_READ_UNDERFLOW_ERROR___S 22 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__SFM_WRITE_OVERFLOW_ERROR___M 0x00200000 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__SFM_WRITE_OVERFLOW_ERROR___S 21 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__OVERFLOW_ERR___M 0x00100000 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__OVERFLOW_ERR___S 20 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__MPDU_LENGTH_ERR___M 0x00080000 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__MPDU_LENGTH_ERR___S 19 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__FCS_ERR___M 0x00040000 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__FCS_ERR___S 18 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__DECRYPT_ERR___M 0x00020000 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__DECRYPT_ERR___S 17 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__TKIP_MIC_ERR___M 0x00010000 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__TKIP_MIC_ERR___S 16 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__UNENCRYPTED_FRAME_ERR___M 0x00008000 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__UNENCRYPTED_FRAME_ERR___S 15 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__MSDU_LENGTH_ERR___M 0x00004000 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__MSDU_LENGTH_ERR___S 14 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__WIFI_PARSER_ERROR___M 0x00002000 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__WIFI_PARSER_ERROR___S 13 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__AMSDU_PARSER_ERROR___M 0x00001000 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__AMSDU_PARSER_ERROR___S 12 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__MSDU_LIMIT_ERROR___M 0x00000800 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__MSDU_LIMIT_ERROR___S 11 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__SA_IDX_TIMEOUT___M 0x00000400 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__SA_IDX_TIMEOUT___S 10 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__DA_IDX_TIMEOUT___M 0x00000200 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__DA_IDX_TIMEOUT___S 9 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__FLOW_IDX_TIMEOUT___M 0x00000100 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__FLOW_IDX_TIMEOUT___S 8 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__FLUSH_REQUEST_COMPLETED___M 0x00000080 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__FLUSH_REQUEST_COMPLETED___S 7 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__BUS_REQUEST___M 0x00000040 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__BUS_REQUEST___S 6 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__TLV_FRME_ERR___M 0x00000020 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__TLV_FRME_ERR___S 5 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__TLV_SHORT___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__TLV_SHORT___S 4 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__INVAL_TAG_ID___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__INVAL_TAG_ID___S 3 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__INVALID_RINGMASK___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__INVALID_RINGMASK___S 2 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__NON_PKT_BUF___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__NON_PKT_BUF___S 1 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__RXDMA_WD_TOUT___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_ISR_S2__RXDMA_WD_TOUT___S 0 +#define WMAC0_MCMN_R0_MCMN_ISR_S2___M 0x07FFFFFF +#define WMAC0_MCMN_R0_MCMN_ISR_S2___S 0 + +#define WMAC0_MCMN_R0_MCMN_ISR_S3 (0x00A8900C) +#define WMAC0_MCMN_R0_MCMN_ISR_S3___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_ISR_S3___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_RCVD_TLV_ABORT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_TX_FRAME_START_INTR___POR 0x00000 +#define WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_TX_PHY_ERROR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_RESPONSE_FRAME_ERROR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_TX_FRAME_END_INTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_WD_TOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S3__BFEE_CV_TOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S3__DATA_URUN___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S3__RECD_GT_MPDU___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S3__RECD_LT_MPDU___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_RCVD_TLV_ABORT___M 0x10000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_RCVD_TLV_ABORT___S 28 +#define WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_TX_FRAME_START_INTR___M 0x0FFFFF00 +#define WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_TX_FRAME_START_INTR___S 8 +#define WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_TX_PHY_ERROR___M 0x00000080 +#define WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_TX_PHY_ERROR___S 7 +#define WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_RESPONSE_FRAME_ERROR___M 0x00000040 +#define WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_RESPONSE_FRAME_ERROR___S 6 +#define WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_TX_FRAME_END_INTR___M 0x00000020 +#define WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_TX_FRAME_END_INTR___S 5 +#define WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_WD_TOUT___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_ISR_S3__TXPCU_WD_TOUT___S 4 +#define WMAC0_MCMN_R0_MCMN_ISR_S3__BFEE_CV_TOUT___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_ISR_S3__BFEE_CV_TOUT___S 3 +#define WMAC0_MCMN_R0_MCMN_ISR_S3__DATA_URUN___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_ISR_S3__DATA_URUN___S 2 +#define WMAC0_MCMN_R0_MCMN_ISR_S3__RECD_GT_MPDU___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_ISR_S3__RECD_GT_MPDU___S 1 +#define WMAC0_MCMN_R0_MCMN_ISR_S3__RECD_LT_MPDU___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_ISR_S3__RECD_LT_MPDU___S 0 +#define WMAC0_MCMN_R0_MCMN_ISR_S3___M 0x1FFFFFFF +#define WMAC0_MCMN_R0_MCMN_ISR_S3___S 0 + +#define WMAC0_MCMN_R0_MCMN_ISR_S4 (0x00A89010) +#define WMAC0_MCMN_R0_MCMN_ISR_S4___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_ISR_S4___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_NAP_DONE_NOT_RCVD_INTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_NAP_ACK_NOT_RCVD_INTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_SYNTH_ON_ACK_NOT_RCVD_INTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_SYNTH_OFF_ACK_NOT_RCVD_INTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_ABORT_ACK_NOT_RCVD_INTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_ON_ACK_NOT_RCVD_INTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_OFF_ACK_NOT_RCVD_INTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S4__CBF_READ_REQ_ACK_INTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_NAP_DONE_NOT_RCVD_INTR___M 0x00000080 +#define WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_NAP_DONE_NOT_RCVD_INTR___S 7 +#define WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_NAP_ACK_NOT_RCVD_INTR___M 0x00000040 +#define WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_NAP_ACK_NOT_RCVD_INTR___S 6 +#define WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_SYNTH_ON_ACK_NOT_RCVD_INTR___M 0x00000020 +#define WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_SYNTH_ON_ACK_NOT_RCVD_INTR___S 5 +#define WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_SYNTH_OFF_ACK_NOT_RCVD_INTR___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_SYNTH_OFF_ACK_NOT_RCVD_INTR___S 4 +#define WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_ABORT_ACK_NOT_RCVD_INTR___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_ABORT_ACK_NOT_RCVD_INTR___S 3 +#define WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_ON_ACK_NOT_RCVD_INTR___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_ON_ACK_NOT_RCVD_INTR___S 2 +#define WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_OFF_ACK_NOT_RCVD_INTR___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_ISR_S4__PHYTX_OFF_ACK_NOT_RCVD_INTR___S 1 +#define WMAC0_MCMN_R0_MCMN_ISR_S4__CBF_READ_REQ_ACK_INTR___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_ISR_S4__CBF_READ_REQ_ACK_INTR___S 0 +#define WMAC0_MCMN_R0_MCMN_ISR_S4___M 0x000000FF +#define WMAC0_MCMN_R0_MCMN_ISR_S4___S 0 + +#define WMAC0_MCMN_R0_MCMN_ISR_S5 (0x00A89014) +#define WMAC0_MCMN_R0_MCMN_ISR_S5___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_ISR_S5___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__RXPCU_AXI_TO_P___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__CHECK_BCN___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__FILTER_BCN_PASS___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__FILTER_PACKET_PASS___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__BCN_HASH_MISMATCH___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__BCN_LENGTH_MISMATCH___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__RX_EARLY_DTIM___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__BCN_TSF_OOR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__RX_EARLY_TIM___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__BCN_TOUT_INTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__RX_FLOW_CONTROL___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__PHY_RXPCU_TLV_LENGTH_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__RX_MAX_LENGTH___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__WDOG_TIMEOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__MIB_COUNTER___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__RX_OVFL___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__RX_DTIM___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__RX_TIM___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__RX_NOTIM___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__RSSI_LOW___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__RSSI_HIGH___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__BCON_MISS___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__RXPCU_AXI_TO_P___M 0x80000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__RXPCU_AXI_TO_P___S 31 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__CHECK_BCN___M 0x40000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__CHECK_BCN___S 30 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__FILTER_BCN_PASS___M 0x20000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__FILTER_BCN_PASS___S 29 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__FILTER_PACKET_PASS___M 0x10000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__FILTER_PACKET_PASS___S 28 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__BCN_HASH_MISMATCH___M 0x0C000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__BCN_HASH_MISMATCH___S 26 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__BCN_LENGTH_MISMATCH___M 0x03000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__BCN_LENGTH_MISMATCH___S 24 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__RX_EARLY_DTIM___M 0x00800000 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__RX_EARLY_DTIM___S 23 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__BCN_TSF_OOR___M 0x00600000 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__BCN_TSF_OOR___S 21 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__RX_EARLY_TIM___M 0x00100000 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__RX_EARLY_TIM___S 20 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__BCN_TOUT_INTR___M 0x00080000 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__BCN_TOUT_INTR___S 19 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__RX_FLOW_CONTROL___M 0x00040000 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__RX_FLOW_CONTROL___S 18 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__PHY_RXPCU_TLV_LENGTH_ERR___M 0x00020000 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__PHY_RXPCU_TLV_LENGTH_ERR___S 17 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__RX_MAX_LENGTH___M 0x00010000 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__RX_MAX_LENGTH___S 16 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__WDOG_TIMEOUT___M 0x00008000 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__WDOG_TIMEOUT___S 15 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__MIB_COUNTER___M 0x00004000 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__MIB_COUNTER___S 14 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__RX_OVFL___M 0x00002000 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__RX_OVFL___S 13 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__RX_DTIM___M 0x00000C00 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__RX_DTIM___S 10 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__RX_TIM___M 0x00000300 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__RX_TIM___S 8 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__RX_NOTIM___M 0x000000C0 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__RX_NOTIM___S 6 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__RSSI_LOW___M 0x00000030 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__RSSI_LOW___S 4 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__RSSI_HIGH___M 0x0000000C +#define WMAC0_MCMN_R0_MCMN_ISR_S5__RSSI_HIGH___S 2 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__BCON_MISS___M 0x00000003 +#define WMAC0_MCMN_R0_MCMN_ISR_S5__BCON_MISS___S 0 +#define WMAC0_MCMN_R0_MCMN_ISR_S5___M 0xFFFFEFFF +#define WMAC0_MCMN_R0_MCMN_ISR_S5___S 0 + +#define WMAC0_MCMN_R0_MCMN_ISR_S6 (0x00A89018) +#define WMAC0_MCMN_R0_MCMN_ISR_S6___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_ISR_S6___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__WILDCARD_TRIGGER_RESP_P___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__RXPCU_USER_SETUP_EXT_LOST_P___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__TWT_SP_DONE_P___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__AST_PRESEARCH_NOT_FIND___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__RXPCU_ERR_P___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__RXPCU_TRIGGER_INFO_SENT_P___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__RXPCU_START_OF_RX_P___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__RXPCU_END_OF_RX_P___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__MAC_SENT_PHY_OFF___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__TBTT_THRESHOLD_REACHED___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__AVG_BCN_MISS___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__DTIM_SW_ATTENTION___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__DTIM_MOREDATA0___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__PHYRX_TLV_OOO_ERR_P___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__WILDCARD_TRIGGER_RESP_P___M 0x0000C000 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__WILDCARD_TRIGGER_RESP_P___S 14 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__RXPCU_USER_SETUP_EXT_LOST_P___M 0x00002000 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__RXPCU_USER_SETUP_EXT_LOST_P___S 13 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__TWT_SP_DONE_P___M 0x00001800 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__TWT_SP_DONE_P___S 11 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__AST_PRESEARCH_NOT_FIND___M 0x00000400 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__AST_PRESEARCH_NOT_FIND___S 10 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__RXPCU_ERR_P___M 0x00000200 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__RXPCU_ERR_P___S 9 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__RXPCU_TRIGGER_INFO_SENT_P___M 0x00000100 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__RXPCU_TRIGGER_INFO_SENT_P___S 8 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__RXPCU_START_OF_RX_P___M 0x00000080 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__RXPCU_START_OF_RX_P___S 7 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__RXPCU_END_OF_RX_P___M 0x00000040 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__RXPCU_END_OF_RX_P___S 6 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__MAC_SENT_PHY_OFF___M 0x00000020 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__MAC_SENT_PHY_OFF___S 5 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__TBTT_THRESHOLD_REACHED___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__TBTT_THRESHOLD_REACHED___S 4 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__AVG_BCN_MISS___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__AVG_BCN_MISS___S 3 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__DTIM_SW_ATTENTION___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__DTIM_SW_ATTENTION___S 2 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__DTIM_MOREDATA0___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__DTIM_MOREDATA0___S 1 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__PHYRX_TLV_OOO_ERR_P___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_ISR_S6__PHYRX_TLV_OOO_ERR_P___S 0 +#define WMAC0_MCMN_R0_MCMN_ISR_S6___M 0x0000FFFF +#define WMAC0_MCMN_R0_MCMN_ISR_S6___S 0 + +#define WMAC0_MCMN_R0_MCMN_ISR_S7 (0x00A8901C) +#define WMAC0_MCMN_R0_MCMN_ISR_S7___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_ISR_S7___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__UNEXP_11AH_FESSETUP_INTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__NO_MPDU_FIT_INTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__COMP_AMPDU_TRUNC_INTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__COEX_TX_INT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__COEX_RX_INT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__REMAIN_TX_TM_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__MPDU_LENGTH_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__SETUP_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__OVERFLOW_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__TXDMA_PDG_LEN_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__HWSCH_PDG_TLV_LEN_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__WRNG_TLV_ORD___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__RCV_FCS_BSY___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__PDG_WD_TOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__UNEXP_11AH_FESSETUP_INTR___M 0x00002000 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__UNEXP_11AH_FESSETUP_INTR___S 13 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__NO_MPDU_FIT_INTR___M 0x00001000 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__NO_MPDU_FIT_INTR___S 12 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__COMP_AMPDU_TRUNC_INTR___M 0x00000800 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__COMP_AMPDU_TRUNC_INTR___S 11 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__COEX_TX_INT___M 0x00000400 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__COEX_TX_INT___S 10 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__COEX_RX_INT___M 0x00000200 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__COEX_RX_INT___S 9 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__REMAIN_TX_TM_ERR___M 0x00000100 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__REMAIN_TX_TM_ERR___S 8 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__MPDU_LENGTH_ERR___M 0x00000080 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__MPDU_LENGTH_ERR___S 7 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__SETUP_ERR___M 0x00000040 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__SETUP_ERR___S 6 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__OVERFLOW_ERR___M 0x00000020 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__OVERFLOW_ERR___S 5 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__TXDMA_PDG_LEN_ERR___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__TXDMA_PDG_LEN_ERR___S 4 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__HWSCH_PDG_TLV_LEN_ERR___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__HWSCH_PDG_TLV_LEN_ERR___S 3 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__WRNG_TLV_ORD___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__WRNG_TLV_ORD___S 2 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__RCV_FCS_BSY___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__RCV_FCS_BSY___S 1 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__PDG_WD_TOUT___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_ISR_S7__PDG_WD_TOUT___S 0 +#define WMAC0_MCMN_R0_MCMN_ISR_S7___M 0x00003FFF +#define WMAC0_MCMN_R0_MCMN_ISR_S7___S 0 + +#define WMAC0_MCMN_R0_MCMN_ISR_S8 (0x00A89020) +#define WMAC0_MCMN_R0_MCMN_ISR_S8___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_ISR_S8___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S8__HW_RNG_THR___POR 0x0000 +#define WMAC0_MCMN_R0_MCMN_ISR_S8__HW_RNG_PSD___POR 0x0000 +#define WMAC0_MCMN_R0_MCMN_ISR_S8__HW_RNG_THR___M 0xFFFF0000 +#define WMAC0_MCMN_R0_MCMN_ISR_S8__HW_RNG_THR___S 16 +#define WMAC0_MCMN_R0_MCMN_ISR_S8__HW_RNG_PSD___M 0x0000FFFF +#define WMAC0_MCMN_R0_MCMN_ISR_S8__HW_RNG_PSD___S 0 +#define WMAC0_MCMN_R0_MCMN_ISR_S8___M 0xFFFFFFFF +#define WMAC0_MCMN_R0_MCMN_ISR_S8___S 0 + +#define WMAC0_MCMN_R0_MCMN_ISR_S9 (0x00A89024) +#define WMAC0_MCMN_R0_MCMN_ISR_S9___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_ISR_S9___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S9__HWSCH_PCU_GEN_TM_THR___POR 0x00 +#define WMAC0_MCMN_R0_MCMN_ISR_S9__HWSCH_PCU_GEN_TM_TRI___POR 0x00 +#define WMAC0_MCMN_R0_MCMN_ISR_S9__MTU_BKOF___POR 0x0000 +#define WMAC0_MCMN_R0_MCMN_ISR_S9__HWSCH_PCU_GEN_TM_THR___M 0xFF000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S9__HWSCH_PCU_GEN_TM_THR___S 24 +#define WMAC0_MCMN_R0_MCMN_ISR_S9__HWSCH_PCU_GEN_TM_TRI___M 0x00FF0000 +#define WMAC0_MCMN_R0_MCMN_ISR_S9__HWSCH_PCU_GEN_TM_TRI___S 16 +#define WMAC0_MCMN_R0_MCMN_ISR_S9__MTU_BKOF___M 0x0000FFFF +#define WMAC0_MCMN_R0_MCMN_ISR_S9__MTU_BKOF___S 0 +#define WMAC0_MCMN_R0_MCMN_ISR_S9___M 0xFFFFFFFF +#define WMAC0_MCMN_R0_MCMN_ISR_S9___S 0 + +#define WMAC0_MCMN_R0_MCMN_ISR_S10 (0x00A89028) +#define WMAC0_MCMN_R0_MCMN_ISR_S10___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_ISR_S10___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_CMD_STATUS_BUFFER_ERR_P___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_FES_STATUS_BUFFER_ERR_P___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_SFM_DELAY_EXCEEDED_INT_P___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_FES_STATUS_END_TIMEOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_RECEIVED_TRIGGER_INFO_INT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__SCH_RING_REQ_ERR_INT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__TQM_RING_REQ_ERR_INT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_TQM_RING_UPDATE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_TQM_STATUS_LOW_UPDATE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_FES_STATUS_LOW_UPDATE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_SCH_STATUS_LOW_UPDATE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_TQM_STATUS_PANIC_UPDATE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_FES_STATUS_PANIC_UPDATE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_SCH_STATUS_PANIC_UPDATE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__SFM_READ_USR_ID_COLLISION___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__SFM_WRITE_USR_ID_COLLISION___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_PCU_GEN_TM_OVERFLOW___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__MTU_TX_BOUNDARY_INT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_TX_STATUS_LOW_WMARK_REACHED___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_TX_STATUS_PANIC_WMARK_REACHED___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__AXI_RD_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__AXI_WR_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_WD_TOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_CMD_STATUS_BUFFER_ERR_P___M 0x02000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_CMD_STATUS_BUFFER_ERR_P___S 25 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_FES_STATUS_BUFFER_ERR_P___M 0x01000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_FES_STATUS_BUFFER_ERR_P___S 24 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_SFM_DELAY_EXCEEDED_INT_P___M 0x00800000 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_SFM_DELAY_EXCEEDED_INT_P___S 23 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_FES_STATUS_END_TIMEOUT___M 0x00400000 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_FES_STATUS_END_TIMEOUT___S 22 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_RECEIVED_TRIGGER_INFO_INT___M 0x00200000 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_RECEIVED_TRIGGER_INFO_INT___S 21 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__SCH_RING_REQ_ERR_INT___M 0x00100000 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__SCH_RING_REQ_ERR_INT___S 20 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__TQM_RING_REQ_ERR_INT___M 0x00080000 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__TQM_RING_REQ_ERR_INT___S 19 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_TQM_RING_UPDATE___M 0x00040000 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_TQM_RING_UPDATE___S 18 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_TQM_STATUS_LOW_UPDATE___M 0x00020000 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_TQM_STATUS_LOW_UPDATE___S 17 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_FES_STATUS_LOW_UPDATE___M 0x00010000 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_FES_STATUS_LOW_UPDATE___S 16 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_SCH_STATUS_LOW_UPDATE___M 0x00008000 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_SCH_STATUS_LOW_UPDATE___S 15 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_TQM_STATUS_PANIC_UPDATE___M 0x00004000 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_TQM_STATUS_PANIC_UPDATE___S 14 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_FES_STATUS_PANIC_UPDATE___M 0x00002000 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_FES_STATUS_PANIC_UPDATE___S 13 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_SCH_STATUS_PANIC_UPDATE___M 0x00001000 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_SCH_STATUS_PANIC_UPDATE___S 12 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__SFM_READ_USR_ID_COLLISION___M 0x00000800 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__SFM_READ_USR_ID_COLLISION___S 11 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__SFM_WRITE_USR_ID_COLLISION___M 0x00000400 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__SFM_WRITE_USR_ID_COLLISION___S 10 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_PCU_GEN_TM_OVERFLOW___M 0x00000200 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_PCU_GEN_TM_OVERFLOW___S 9 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__MTU_TX_BOUNDARY_INT___M 0x000001E0 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__MTU_TX_BOUNDARY_INT___S 5 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_TX_STATUS_LOW_WMARK_REACHED___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_TX_STATUS_LOW_WMARK_REACHED___S 4 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_TX_STATUS_PANIC_WMARK_REACHED___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_TX_STATUS_PANIC_WMARK_REACHED___S 3 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__AXI_RD_ERR___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__AXI_RD_ERR___S 2 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__AXI_WR_ERR___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__AXI_WR_ERR___S 1 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_WD_TOUT___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_ISR_S10__HWSCH_WD_TOUT___S 0 +#define WMAC0_MCMN_R0_MCMN_ISR_S10___M 0x03FFFFFF +#define WMAC0_MCMN_R0_MCMN_ISR_S10___S 0 + +#define WMAC0_MCMN_R0_MCMN_ISR_S11 (0x00A8902C) +#define WMAC0_MCMN_R0_MCMN_ISR_S11___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_ISR_S11___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S11__WDTIMEOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S11__AXI_RD_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S11__AXI_WR_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S11__AXI_WR_LAST_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S11__WDTIMEOUT___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_ISR_S11__WDTIMEOUT___S 3 +#define WMAC0_MCMN_R0_MCMN_ISR_S11__AXI_RD_ERR___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_ISR_S11__AXI_RD_ERR___S 2 +#define WMAC0_MCMN_R0_MCMN_ISR_S11__AXI_WR_ERR___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_ISR_S11__AXI_WR_ERR___S 1 +#define WMAC0_MCMN_R0_MCMN_ISR_S11__AXI_WR_LAST_ERR___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_ISR_S11__AXI_WR_LAST_ERR___S 0 +#define WMAC0_MCMN_R0_MCMN_ISR_S11___M 0x0000000F +#define WMAC0_MCMN_R0_MCMN_ISR_S11___S 0 + +#define WMAC0_MCMN_R0_MCMN_ISR_S12 (0x00A89030) +#define WMAC0_MCMN_R0_MCMN_ISR_S12___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_ISR_S12___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S12__PHY2MAC_RX_FIFO_OVERFLOW_MAC_CLK_P___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S12__RX_TLV_ERROR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S12__TX_TLV_ERROR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S12__PHY2MAC_RX_FIFO_OVERFLOW_MAC_CLK_P___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_ISR_S12__PHY2MAC_RX_FIFO_OVERFLOW_MAC_CLK_P___S 2 +#define WMAC0_MCMN_R0_MCMN_ISR_S12__RX_TLV_ERROR___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_ISR_S12__RX_TLV_ERROR___S 1 +#define WMAC0_MCMN_R0_MCMN_ISR_S12__TX_TLV_ERROR___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_ISR_S12__TX_TLV_ERROR___S 0 +#define WMAC0_MCMN_R0_MCMN_ISR_S12___M 0x00000007 +#define WMAC0_MCMN_R0_MCMN_ISR_S12___S 0 + +#define WMAC0_MCMN_R0_MCMN_ISR_S13 (0x00A89034) +#define WMAC0_MCMN_R0_MCMN_ISR_S13___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_ISR_S13___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S13__RRI_ERR_INTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S13__RRI_ERR_INTR___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_ISR_S13__RRI_ERR_INTR___S 0 +#define WMAC0_MCMN_R0_MCMN_ISR_S13___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_ISR_S13___S 0 + +#define WMAC0_MCMN_R0_MCMN_ISR_S14 (0x00A89038) +#define WMAC0_MCMN_R0_MCMN_ISR_S14___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_ISR_S14___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__RRI_APB_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__RRI_APB_WR_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__RRI_APB_WR_TO_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__AMPI_APB_RD_WMAC_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__AMPI_APB_WR_WMAC_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__AMPI_APB_WR_TO_RD_WMAC_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__MXI_APB_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__MXI_APB_WR_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__MXI_APB_WR_TO_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__HWSCH_APB_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__HWSCH_APB_WR_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__HWSCH_APB_WR_TO_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__PDG_APB_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__PDG_APB_WR_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__PDG_APB_WR_TO_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__RXPCU_APB_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__RXPCU_APB_WR_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__RXPCU_APB_WR_TO_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__TXPCU_APB_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__TXPCU_APB_WR_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__TXPCU_APB_WR_TO_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__RXDMA_APB_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__RXDMA_APB_WR_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__RXDMA_APB_WR_TO_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__TXDMA_APB_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__TXDMA_APB_WR_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__TXDMA_APB_WR_TO_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__CRYPTO_APB_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__CRYPTO_APB_WR_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__CRYPTO_APB_WR_TO_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__RRI_APB_RD_INVALID___M 0x20000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__RRI_APB_RD_INVALID___S 29 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__RRI_APB_WR_INVALID___M 0x10000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__RRI_APB_WR_INVALID___S 28 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__RRI_APB_WR_TO_RD_INVALID___M 0x08000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__RRI_APB_WR_TO_RD_INVALID___S 27 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__AMPI_APB_RD_WMAC_INVALID___M 0x04000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__AMPI_APB_RD_WMAC_INVALID___S 26 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__AMPI_APB_WR_WMAC_INVALID___M 0x02000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__AMPI_APB_WR_WMAC_INVALID___S 25 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__AMPI_APB_WR_TO_RD_WMAC_INVALID___M 0x01000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__AMPI_APB_WR_TO_RD_WMAC_INVALID___S 24 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__MXI_APB_RD_INVALID___M 0x00800000 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__MXI_APB_RD_INVALID___S 23 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__MXI_APB_WR_INVALID___M 0x00400000 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__MXI_APB_WR_INVALID___S 22 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__MXI_APB_WR_TO_RD_INVALID___M 0x00200000 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__MXI_APB_WR_TO_RD_INVALID___S 21 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__HWSCH_APB_RD_INVALID___M 0x00100000 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__HWSCH_APB_RD_INVALID___S 20 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__HWSCH_APB_WR_INVALID___M 0x00080000 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__HWSCH_APB_WR_INVALID___S 19 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__HWSCH_APB_WR_TO_RD_INVALID___M 0x00040000 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__HWSCH_APB_WR_TO_RD_INVALID___S 18 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__PDG_APB_RD_INVALID___M 0x00020000 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__PDG_APB_RD_INVALID___S 17 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__PDG_APB_WR_INVALID___M 0x00010000 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__PDG_APB_WR_INVALID___S 16 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__PDG_APB_WR_TO_RD_INVALID___M 0x00008000 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__PDG_APB_WR_TO_RD_INVALID___S 15 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__RXPCU_APB_RD_INVALID___M 0x00004000 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__RXPCU_APB_RD_INVALID___S 14 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__RXPCU_APB_WR_INVALID___M 0x00002000 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__RXPCU_APB_WR_INVALID___S 13 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__RXPCU_APB_WR_TO_RD_INVALID___M 0x00001000 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__RXPCU_APB_WR_TO_RD_INVALID___S 12 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__TXPCU_APB_RD_INVALID___M 0x00000800 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__TXPCU_APB_RD_INVALID___S 11 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__TXPCU_APB_WR_INVALID___M 0x00000400 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__TXPCU_APB_WR_INVALID___S 10 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__TXPCU_APB_WR_TO_RD_INVALID___M 0x00000200 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__TXPCU_APB_WR_TO_RD_INVALID___S 9 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__RXDMA_APB_RD_INVALID___M 0x00000100 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__RXDMA_APB_RD_INVALID___S 8 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__RXDMA_APB_WR_INVALID___M 0x00000080 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__RXDMA_APB_WR_INVALID___S 7 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__RXDMA_APB_WR_TO_RD_INVALID___M 0x00000040 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__RXDMA_APB_WR_TO_RD_INVALID___S 6 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__TXDMA_APB_RD_INVALID___M 0x00000020 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__TXDMA_APB_RD_INVALID___S 5 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__TXDMA_APB_WR_INVALID___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__TXDMA_APB_WR_INVALID___S 4 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__TXDMA_APB_WR_TO_RD_INVALID___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__TXDMA_APB_WR_TO_RD_INVALID___S 3 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__CRYPTO_APB_RD_INVALID___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__CRYPTO_APB_RD_INVALID___S 2 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__CRYPTO_APB_WR_INVALID___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__CRYPTO_APB_WR_INVALID___S 1 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__CRYPTO_APB_WR_TO_RD_INVALID___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_ISR_S14__CRYPTO_APB_WR_TO_RD_INVALID___S 0 +#define WMAC0_MCMN_R0_MCMN_ISR_S14___M 0x3FFFFFFF +#define WMAC0_MCMN_R0_MCMN_ISR_S14___S 0 + +#define WMAC0_MCMN_R0_MCMN_ISR_S15 (0x00A8903C) +#define WMAC0_MCMN_R0_MCMN_ISR_S15___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_ISR_S15___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__MCMN_APB_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__MCMN_APB_WR_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__MCMN_APB_WR_TO_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__CMN_PARSER_APB_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__CMN_PARSER_APB_WR_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__CMN_PARSER_APB_WR_TO_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__AMPI_APB_RD_PHY_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__AMPI_APB_WR_PHY_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__AMPI_APB_WR_TO_RD_PHY_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__RXOLE_APB_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__RXOLE_APB_WR_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__RXOLE_APB_WR_TO_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__TXOLE_APB_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__TXOLE_APB_WR_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__TXOLE_APB_WR_TO_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__MCMN_APB_RD_INVALID___M 0x00004000 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__MCMN_APB_RD_INVALID___S 14 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__MCMN_APB_WR_INVALID___M 0x00002000 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__MCMN_APB_WR_INVALID___S 13 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__MCMN_APB_WR_TO_RD_INVALID___M 0x00001000 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__MCMN_APB_WR_TO_RD_INVALID___S 12 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__CMN_PARSER_APB_RD_INVALID___M 0x00000800 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__CMN_PARSER_APB_RD_INVALID___S 11 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__CMN_PARSER_APB_WR_INVALID___M 0x00000400 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__CMN_PARSER_APB_WR_INVALID___S 10 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__CMN_PARSER_APB_WR_TO_RD_INVALID___M 0x00000200 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__CMN_PARSER_APB_WR_TO_RD_INVALID___S 9 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__AMPI_APB_RD_PHY_INVALID___M 0x00000100 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__AMPI_APB_RD_PHY_INVALID___S 8 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__AMPI_APB_WR_PHY_INVALID___M 0x00000080 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__AMPI_APB_WR_PHY_INVALID___S 7 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__AMPI_APB_WR_TO_RD_PHY_INVALID___M 0x00000040 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__AMPI_APB_WR_TO_RD_PHY_INVALID___S 6 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__RXOLE_APB_RD_INVALID___M 0x00000020 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__RXOLE_APB_RD_INVALID___S 5 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__RXOLE_APB_WR_INVALID___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__RXOLE_APB_WR_INVALID___S 4 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__RXOLE_APB_WR_TO_RD_INVALID___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__RXOLE_APB_WR_TO_RD_INVALID___S 3 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__TXOLE_APB_RD_INVALID___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__TXOLE_APB_RD_INVALID___S 2 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__TXOLE_APB_WR_INVALID___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__TXOLE_APB_WR_INVALID___S 1 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__TXOLE_APB_WR_TO_RD_INVALID___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_ISR_S15__TXOLE_APB_WR_TO_RD_INVALID___S 0 +#define WMAC0_MCMN_R0_MCMN_ISR_S15___M 0x00007FFF +#define WMAC0_MCMN_R0_MCMN_ISR_S15___S 0 + +#define WMAC0_MCMN_R0_MCMN_ISR_S16 (0x00A89040) +#define WMAC0_MCMN_R0_MCMN_ISR_S16___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_ISR_S16___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_IPV6_JBGM___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_IPV6_EXT_HD_BYTES_EXCEEDED___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_MSDU_LENGTH_ERROR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_ETH_ERROR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_WMAC_ERROR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_WDOG_TOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__PV1_WRONG_KEY_TYPE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__FRAG_EN_SW_ENCTYPTED___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__TX_ILLEGAL___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__INCOMPLETE_LLC_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__LENGTH_MISMATCH_FOR_802_3_FRAME_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__NO_FULL_MSDU_FOR_CHECKSUM_EN_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__AMSDU_FRM_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__WEP_KEY_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__TX_PV1_AMSDU_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__TX_FRAG_AMSDU_AMPDU___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__TX_MORE_FRAG___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__TX_TLV_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__TX_WDOG_TOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_IPV6_JBGM___M 0x00040000 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_IPV6_JBGM___S 18 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_IPV6_EXT_HD_BYTES_EXCEEDED___M 0x00020000 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_IPV6_EXT_HD_BYTES_EXCEEDED___S 17 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_MSDU_LENGTH_ERROR___M 0x00010000 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_MSDU_LENGTH_ERROR___S 16 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_ETH_ERROR___M 0x00008000 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_ETH_ERROR___S 15 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_WMAC_ERROR___M 0x00004000 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_WMAC_ERROR___S 14 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_WDOG_TOUT___M 0x00002000 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__CMN_PARSER_WDOG_TOUT___S 13 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__PV1_WRONG_KEY_TYPE___M 0x00001000 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__PV1_WRONG_KEY_TYPE___S 12 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__FRAG_EN_SW_ENCTYPTED___M 0x00000800 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__FRAG_EN_SW_ENCTYPTED___S 11 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__TX_ILLEGAL___M 0x00000400 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__TX_ILLEGAL___S 10 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__INCOMPLETE_LLC_ERR___M 0x00000200 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__INCOMPLETE_LLC_ERR___S 9 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__LENGTH_MISMATCH_FOR_802_3_FRAME_ERR___M 0x00000100 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__LENGTH_MISMATCH_FOR_802_3_FRAME_ERR___S 8 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__NO_FULL_MSDU_FOR_CHECKSUM_EN_ERR___M 0x00000080 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__NO_FULL_MSDU_FOR_CHECKSUM_EN_ERR___S 7 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__AMSDU_FRM_ERR___M 0x00000040 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__AMSDU_FRM_ERR___S 6 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__WEP_KEY_ERR___M 0x00000020 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__WEP_KEY_ERR___S 5 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__TX_PV1_AMSDU_ERR___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__TX_PV1_AMSDU_ERR___S 4 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__TX_FRAG_AMSDU_AMPDU___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__TX_FRAG_AMSDU_AMPDU___S 3 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__TX_MORE_FRAG___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__TX_MORE_FRAG___S 2 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__TX_TLV_ERR___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__TX_TLV_ERR___S 1 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__TX_WDOG_TOUT___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_ISR_S16__TX_WDOG_TOUT___S 0 +#define WMAC0_MCMN_R0_MCMN_ISR_S16___M 0x0007FFFF +#define WMAC0_MCMN_R0_MCMN_ISR_S16___S 0 + +#define WMAC0_MCMN_R0_MCMN_ISR_S17 (0x00A89044) +#define WMAC0_MCMN_R0_MCMN_ISR_S17___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_ISR_S17___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_PPDU_END___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_L3_L4_HD_BYTES_EXCEEDED_256___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_CP_INT_WDOG___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_CCE_ERR_CLASSIFY_DIS___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_CCE_SW_REQ___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_CCE_WDOG___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_MCMN_IPV6_JMBG___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_IPV6_HD_BYTES___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_WMAC_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_AMSDU_PARSER_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_MSDU_LEN___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_TLV_ERROR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_WDOG_TOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_PPDU_END___M 0x00001000 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_PPDU_END___S 12 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_L3_L4_HD_BYTES_EXCEEDED_256___M 0x00000800 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_L3_L4_HD_BYTES_EXCEEDED_256___S 11 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_CP_INT_WDOG___M 0x00000400 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_CP_INT_WDOG___S 10 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_CCE_ERR_CLASSIFY_DIS___M 0x00000200 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_CCE_ERR_CLASSIFY_DIS___S 9 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_CCE_SW_REQ___M 0x00000100 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_CCE_SW_REQ___S 8 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_CCE_WDOG___M 0x00000080 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_CCE_WDOG___S 7 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_MCMN_IPV6_JMBG___M 0x00000040 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_MCMN_IPV6_JMBG___S 6 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_IPV6_HD_BYTES___M 0x00000020 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_IPV6_HD_BYTES___S 5 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_WMAC_ERR___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_WMAC_ERR___S 4 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_AMSDU_PARSER_ERR___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_AMSDU_PARSER_ERR___S 3 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_MSDU_LEN___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_MSDU_LEN___S 2 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_TLV_ERROR___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_TLV_ERROR___S 1 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_WDOG_TOUT___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_ISR_S17__RX_WDOG_TOUT___S 0 +#define WMAC0_MCMN_R0_MCMN_ISR_S17___M 0x00001FFF +#define WMAC0_MCMN_R0_MCMN_ISR_S17___S 0 + +#define WMAC0_MCMN_R0_MCMN_ISR_S18 (0x00A89048) +#define WMAC0_MCMN_R0_MCMN_ISR_S18___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_ISR_S18___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S18__RRI_MODIFIED_ACCESS_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S18__WDG_TIMEOUT_INT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S18__AP_WR_TO_RD_ONLY_ADDR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S18__APB_WR_INVALID_ADDR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S18__APB_RD_INVALID_ADDR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S18__INIT_NOT_ENOUGH_BUFFER___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S18__RRI_MODIFIED_ACCESS_ERR___M 0x00000020 +#define WMAC0_MCMN_R0_MCMN_ISR_S18__RRI_MODIFIED_ACCESS_ERR___S 5 +#define WMAC0_MCMN_R0_MCMN_ISR_S18__WDG_TIMEOUT_INT___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_ISR_S18__WDG_TIMEOUT_INT___S 4 +#define WMAC0_MCMN_R0_MCMN_ISR_S18__AP_WR_TO_RD_ONLY_ADDR___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_ISR_S18__AP_WR_TO_RD_ONLY_ADDR___S 3 +#define WMAC0_MCMN_R0_MCMN_ISR_S18__APB_WR_INVALID_ADDR___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_ISR_S18__APB_WR_INVALID_ADDR___S 2 +#define WMAC0_MCMN_R0_MCMN_ISR_S18__APB_RD_INVALID_ADDR___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_ISR_S18__APB_RD_INVALID_ADDR___S 1 +#define WMAC0_MCMN_R0_MCMN_ISR_S18__INIT_NOT_ENOUGH_BUFFER___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_ISR_S18__INIT_NOT_ENOUGH_BUFFER___S 0 +#define WMAC0_MCMN_R0_MCMN_ISR_S18___M 0x0000003F +#define WMAC0_MCMN_R0_MCMN_ISR_S18___S 0 + +#define WMAC0_MCMN_R0_MCMN_ISR_S20 (0x00A89050) +#define WMAC0_MCMN_R0_MCMN_ISR_S20___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_ISR_S20___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S20__SRC_RING_REQ_ERR___POR 0x00 +#define WMAC0_MCMN_R0_MCMN_ISR_S20__SRC_RING_WATCHDOG_ERR___POR 0x00 +#define WMAC0_MCMN_R0_MCMN_ISR_S20__SRC_RING_SW_INT___POR 0x00 +#define WMAC0_MCMN_R0_MCMN_ISR_S20__SRC_RING_REQ_ERR___M 0x0003F000 +#define WMAC0_MCMN_R0_MCMN_ISR_S20__SRC_RING_REQ_ERR___S 12 +#define WMAC0_MCMN_R0_MCMN_ISR_S20__SRC_RING_WATCHDOG_ERR___M 0x00000FC0 +#define WMAC0_MCMN_R0_MCMN_ISR_S20__SRC_RING_WATCHDOG_ERR___S 6 +#define WMAC0_MCMN_R0_MCMN_ISR_S20__SRC_RING_SW_INT___M 0x0000003F +#define WMAC0_MCMN_R0_MCMN_ISR_S20__SRC_RING_SW_INT___S 0 +#define WMAC0_MCMN_R0_MCMN_ISR_S20___M 0x0003FFFF +#define WMAC0_MCMN_R0_MCMN_ISR_S20___S 0 + +#define WMAC0_MCMN_R0_MCMN_ISR_S21 (0x00A89054) +#define WMAC0_MCMN_R0_MCMN_ISR_S21___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_ISR_S21___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S21__DEST_RING_REQ_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S21__DEST_RING_WATCHDOG_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S21__DEST_RING_SW_INT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S21__DEST_RING_REQ_ERR___M 0x00000F00 +#define WMAC0_MCMN_R0_MCMN_ISR_S21__DEST_RING_REQ_ERR___S 8 +#define WMAC0_MCMN_R0_MCMN_ISR_S21__DEST_RING_WATCHDOG_ERR___M 0x000000F0 +#define WMAC0_MCMN_R0_MCMN_ISR_S21__DEST_RING_WATCHDOG_ERR___S 4 +#define WMAC0_MCMN_R0_MCMN_ISR_S21__DEST_RING_SW_INT___M 0x0000000F +#define WMAC0_MCMN_R0_MCMN_ISR_S21__DEST_RING_SW_INT___S 0 +#define WMAC0_MCMN_R0_MCMN_ISR_S21___M 0x00000FFF +#define WMAC0_MCMN_R0_MCMN_ISR_S21___S 0 + +#define WMAC0_MCMN_R0_MCMN_ISR_S22 (0x00A89058) +#define WMAC0_MCMN_R0_MCMN_ISR_S22___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_ISR_S22___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S22__SRC_RING_REQ_ERR___POR 0x00 +#define WMAC0_MCMN_R0_MCMN_ISR_S22__SRC_RING_WATCHDOG_ERR___POR 0x00 +#define WMAC0_MCMN_R0_MCMN_ISR_S22__SRC_RING_SW_INT___POR 0x00 +#define WMAC0_MCMN_R0_MCMN_ISR_S22__SRC_RING_REQ_ERR___M 0x0003F000 +#define WMAC0_MCMN_R0_MCMN_ISR_S22__SRC_RING_REQ_ERR___S 12 +#define WMAC0_MCMN_R0_MCMN_ISR_S22__SRC_RING_WATCHDOG_ERR___M 0x00000FC0 +#define WMAC0_MCMN_R0_MCMN_ISR_S22__SRC_RING_WATCHDOG_ERR___S 6 +#define WMAC0_MCMN_R0_MCMN_ISR_S22__SRC_RING_SW_INT___M 0x0000003F +#define WMAC0_MCMN_R0_MCMN_ISR_S22__SRC_RING_SW_INT___S 0 +#define WMAC0_MCMN_R0_MCMN_ISR_S22___M 0x0003FFFF +#define WMAC0_MCMN_R0_MCMN_ISR_S22___S 0 + +#define WMAC0_MCMN_R0_MCMN_ISR_S26 (0x00A89068) +#define WMAC0_MCMN_R0_MCMN_ISR_S26___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_ISR_S26___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S26__SFM_WITH_DATA___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S26__HWSCH_CMD_RING_NOT_EMPTY___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S26__TX_FLUSH_NOT_RECEIVED___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S26__RX_FLUSH_NOT_RECEIVED___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S26__SFM_WITH_DATA___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_ISR_S26__SFM_WITH_DATA___S 3 +#define WMAC0_MCMN_R0_MCMN_ISR_S26__HWSCH_CMD_RING_NOT_EMPTY___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_ISR_S26__HWSCH_CMD_RING_NOT_EMPTY___S 2 +#define WMAC0_MCMN_R0_MCMN_ISR_S26__TX_FLUSH_NOT_RECEIVED___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_ISR_S26__TX_FLUSH_NOT_RECEIVED___S 1 +#define WMAC0_MCMN_R0_MCMN_ISR_S26__RX_FLUSH_NOT_RECEIVED___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_ISR_S26__RX_FLUSH_NOT_RECEIVED___S 0 +#define WMAC0_MCMN_R0_MCMN_ISR_S26___M 0x0000000F +#define WMAC0_MCMN_R0_MCMN_ISR_S26___S 0 + +#define WMAC0_MCMN_R0_MCMN_ISR_S8_EXT (0x00A8906C) +#define WMAC0_MCMN_R0_MCMN_ISR_S8_EXT___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_ISR_S8_EXT___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S8_EXT__HW_RNG_THR_19_16___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S8_EXT__HW_RNG_PSD_19_16___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S8_EXT__HW_RNG_THR_19_16___M 0x000000F0 +#define WMAC0_MCMN_R0_MCMN_ISR_S8_EXT__HW_RNG_THR_19_16___S 4 +#define WMAC0_MCMN_R0_MCMN_ISR_S8_EXT__HW_RNG_PSD_19_16___M 0x0000000F +#define WMAC0_MCMN_R0_MCMN_ISR_S8_EXT__HW_RNG_PSD_19_16___S 0 +#define WMAC0_MCMN_R0_MCMN_ISR_S8_EXT___M 0x000000FF +#define WMAC0_MCMN_R0_MCMN_ISR_S8_EXT___S 0 + +#define WMAC0_MCMN_R0_MCMN_ISR_S9_EXT (0x00A89070) +#define WMAC0_MCMN_R0_MCMN_ISR_S9_EXT___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_ISR_S9_EXT___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_ISR_S9_EXT__MTU_BKOF_19_16___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_S9_EXT__MTU_BKOF_19_16___M 0x0000000F +#define WMAC0_MCMN_R0_MCMN_ISR_S9_EXT__MTU_BKOF_19_16___S 0 +#define WMAC0_MCMN_R0_MCMN_ISR_S9_EXT___M 0x0000000F +#define WMAC0_MCMN_R0_MCMN_ISR_S9_EXT___S 0 + +#define WMAC0_MCMN_R0_MCMN_IMR_S0 (0x00A89100) +#define WMAC0_MCMN_R0_MCMN_IMR_S0___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_IMR_S0___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__RX_KEY_ID_RECV_NOT_VALID_KEY___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__RX_WATCHDOG_TIMEOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__OVER_CAPACITY_TX_USER___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__RX_KEY_ID_RECV_NOT_DEFAULT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__RX_NO_MU_KEY_TYPE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__TX_NO_MU_KEY_TYPE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__RX_IN_TX_DECRYPT_BYP_INT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__RX_TLV_READY_TMOUT_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__AH_DEC_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__AH_ENC_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__MIN_LENGTH_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__TX_FLUSH_REQ___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__RX_ABORT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__TX_ABORT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__DECRPT_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__RX_TLV_OUT_SEQ___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__TX_TLV_OUT_SEQ___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__CRYP_WD_TMOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__RX_KEY_ID_RECV_NOT_VALID_KEY___M 0x00020000 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__RX_KEY_ID_RECV_NOT_VALID_KEY___S 17 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__RX_WATCHDOG_TIMEOUT___M 0x00010000 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__RX_WATCHDOG_TIMEOUT___S 16 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__OVER_CAPACITY_TX_USER___M 0x00008000 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__OVER_CAPACITY_TX_USER___S 15 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__RX_KEY_ID_RECV_NOT_DEFAULT___M 0x00004000 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__RX_KEY_ID_RECV_NOT_DEFAULT___S 14 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__RX_NO_MU_KEY_TYPE___M 0x00002000 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__RX_NO_MU_KEY_TYPE___S 13 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__TX_NO_MU_KEY_TYPE___M 0x00001000 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__TX_NO_MU_KEY_TYPE___S 12 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__RX_IN_TX_DECRYPT_BYP_INT___M 0x00000800 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__RX_IN_TX_DECRYPT_BYP_INT___S 11 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__RX_TLV_READY_TMOUT_ERR___M 0x00000400 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__RX_TLV_READY_TMOUT_ERR___S 10 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__AH_DEC_ERR___M 0x00000200 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__AH_DEC_ERR___S 9 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__AH_ENC_ERR___M 0x00000100 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__AH_ENC_ERR___S 8 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__MIN_LENGTH_ERR___M 0x00000080 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__MIN_LENGTH_ERR___S 7 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__TX_FLUSH_REQ___M 0x00000040 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__TX_FLUSH_REQ___S 6 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__RX_ABORT___M 0x00000020 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__RX_ABORT___S 5 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__TX_ABORT___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__TX_ABORT___S 4 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__DECRPT_ERR___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__DECRPT_ERR___S 3 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__RX_TLV_OUT_SEQ___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__RX_TLV_OUT_SEQ___S 2 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__TX_TLV_OUT_SEQ___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__TX_TLV_OUT_SEQ___S 1 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__CRYP_WD_TMOUT___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_IMR_S0__CRYP_WD_TMOUT___S 0 +#define WMAC0_MCMN_R0_MCMN_IMR_S0___M 0x0003FFFF +#define WMAC0_MCMN_R0_MCMN_IMR_S0___S 0 + +#define WMAC0_MCMN_R0_MCMN_IMR_S1 (0x00A89104) +#define WMAC0_MCMN_R0_MCMN_IMR_S1___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_IMR_S1___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__SNOOP_RING_WATCHDOG_ERR_INT_P___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__SNOOP_RING_REQ_ERR_INT_P___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__UCODE_WDOG_TIMEOUT_INTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__SNOOP_WDOG_TIMEOUT_INTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__SNOOP_RING_SW_INT_P___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__TXDMA_RESERVED_INT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__UNEXPECT_NULL_LENGTH___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__MSDU_LENGTH_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__MSDU_LINK_GXI_TMOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__MSDU_LINK_EXT_GXI_TMOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__TX_DATA_GXI_TMOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__OLE_RDY_TMOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__UNEX_NUL_PTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__WDG_TMOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__INVA_IDX___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__MISSIN_TLV___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__UNEX_FES___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__INCOM_TLV___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__TX_DMA_IDLE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__SNOOP_RING_WATCHDOG_ERR_INT_P___M 0x00400000 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__SNOOP_RING_WATCHDOG_ERR_INT_P___S 22 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__SNOOP_RING_REQ_ERR_INT_P___M 0x00200000 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__SNOOP_RING_REQ_ERR_INT_P___S 21 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__UCODE_WDOG_TIMEOUT_INTR___M 0x00100000 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__UCODE_WDOG_TIMEOUT_INTR___S 20 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__SNOOP_WDOG_TIMEOUT_INTR___M 0x00080000 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__SNOOP_WDOG_TIMEOUT_INTR___S 19 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__SNOOP_RING_SW_INT_P___M 0x00040000 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__SNOOP_RING_SW_INT_P___S 18 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__TXDMA_RESERVED_INT___M 0x0003C000 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__TXDMA_RESERVED_INT___S 14 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__UNEXPECT_NULL_LENGTH___M 0x00002000 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__UNEXPECT_NULL_LENGTH___S 13 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__MSDU_LENGTH_ERR___M 0x00001000 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__MSDU_LENGTH_ERR___S 12 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__MSDU_LINK_GXI_TMOUT___M 0x00000800 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__MSDU_LINK_GXI_TMOUT___S 11 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__MSDU_LINK_EXT_GXI_TMOUT___M 0x00000400 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__MSDU_LINK_EXT_GXI_TMOUT___S 10 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__TX_DATA_GXI_TMOUT___M 0x00000200 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__TX_DATA_GXI_TMOUT___S 9 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__OLE_RDY_TMOUT___M 0x00000100 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__OLE_RDY_TMOUT___S 8 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__UNEX_NUL_PTR___M 0x00000080 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__UNEX_NUL_PTR___S 7 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__WDG_TMOUT___M 0x00000040 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__WDG_TMOUT___S 6 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__INVA_IDX___M 0x00000020 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__INVA_IDX___S 5 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__MISSIN_TLV___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__MISSIN_TLV___S 3 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__UNEX_FES___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__UNEX_FES___S 2 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__INCOM_TLV___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__INCOM_TLV___S 1 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__TX_DMA_IDLE___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_IMR_S1__TX_DMA_IDLE___S 0 +#define WMAC0_MCMN_R0_MCMN_IMR_S1___M 0x007FFFEF +#define WMAC0_MCMN_R0_MCMN_IMR_S1___S 0 + +#define WMAC0_MCMN_R0_MCMN_IMR_S2 (0x00A89108) +#define WMAC0_MCMN_R0_MCMN_IMR_S2___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_IMR_S2___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__BUS_REQUEST_AT_SFM_NEARLY_FULL_INTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__AMSDU_FRAG_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__RXDMA_RESERVED_2___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__SFM_READ_UNDERFLOW_ERROR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__SFM_WRITE_OVERFLOW_ERROR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__OVERFLOW_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__MPDU_LENGTH_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__FCS_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__DECRYPT_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__TKIP_MIC_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__UNENCRYPTED_FRAME_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__MSDU_LENGTH_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__WIFI_PARSER_ERROR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__AMSDU_PARSER_ERROR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__MSDU_LIMIT_ERROR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__SA_IDX_TIMEOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__DA_IDX_TIMEOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__FLOW_IDX_TIMEOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__FLUSH_REQUEST_COMPLETED___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__BUS_REQUEST___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__TLV_FRME_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__TLV_SHORT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__INVAL_TAG_ID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__INVALID_RINGMASK___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__NON_PKT_BUF___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__RXDMA_WD_TOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__BUS_REQUEST_AT_SFM_NEARLY_FULL_INTR___M 0x04000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__BUS_REQUEST_AT_SFM_NEARLY_FULL_INTR___S 26 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__AMSDU_FRAG_ERR___M 0x02000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__AMSDU_FRAG_ERR___S 25 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__RXDMA_RESERVED_2___M 0x01800000 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__RXDMA_RESERVED_2___S 23 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__SFM_READ_UNDERFLOW_ERROR___M 0x00400000 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__SFM_READ_UNDERFLOW_ERROR___S 22 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__SFM_WRITE_OVERFLOW_ERROR___M 0x00200000 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__SFM_WRITE_OVERFLOW_ERROR___S 21 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__OVERFLOW_ERR___M 0x00100000 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__OVERFLOW_ERR___S 20 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__MPDU_LENGTH_ERR___M 0x00080000 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__MPDU_LENGTH_ERR___S 19 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__FCS_ERR___M 0x00040000 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__FCS_ERR___S 18 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__DECRYPT_ERR___M 0x00020000 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__DECRYPT_ERR___S 17 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__TKIP_MIC_ERR___M 0x00010000 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__TKIP_MIC_ERR___S 16 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__UNENCRYPTED_FRAME_ERR___M 0x00008000 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__UNENCRYPTED_FRAME_ERR___S 15 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__MSDU_LENGTH_ERR___M 0x00004000 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__MSDU_LENGTH_ERR___S 14 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__WIFI_PARSER_ERROR___M 0x00002000 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__WIFI_PARSER_ERROR___S 13 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__AMSDU_PARSER_ERROR___M 0x00001000 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__AMSDU_PARSER_ERROR___S 12 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__MSDU_LIMIT_ERROR___M 0x00000800 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__MSDU_LIMIT_ERROR___S 11 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__SA_IDX_TIMEOUT___M 0x00000400 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__SA_IDX_TIMEOUT___S 10 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__DA_IDX_TIMEOUT___M 0x00000200 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__DA_IDX_TIMEOUT___S 9 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__FLOW_IDX_TIMEOUT___M 0x00000100 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__FLOW_IDX_TIMEOUT___S 8 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__FLUSH_REQUEST_COMPLETED___M 0x00000080 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__FLUSH_REQUEST_COMPLETED___S 7 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__BUS_REQUEST___M 0x00000040 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__BUS_REQUEST___S 6 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__TLV_FRME_ERR___M 0x00000020 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__TLV_FRME_ERR___S 5 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__TLV_SHORT___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__TLV_SHORT___S 4 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__INVAL_TAG_ID___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__INVAL_TAG_ID___S 3 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__INVALID_RINGMASK___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__INVALID_RINGMASK___S 2 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__NON_PKT_BUF___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__NON_PKT_BUF___S 1 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__RXDMA_WD_TOUT___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_IMR_S2__RXDMA_WD_TOUT___S 0 +#define WMAC0_MCMN_R0_MCMN_IMR_S2___M 0x07FFFFFF +#define WMAC0_MCMN_R0_MCMN_IMR_S2___S 0 + +#define WMAC0_MCMN_R0_MCMN_IMR_S3 (0x00A8910C) +#define WMAC0_MCMN_R0_MCMN_IMR_S3___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_IMR_S3___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_RCVD_TLV_ABORT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_TX_FRAME_START_INTR___POR 0x00000 +#define WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_TX_PHY_ERROR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_RESPONSE_FRAME_ERROR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_TX_FRAME_END_INTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_WD_TOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S3__BFEE_CV_TOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S3__DATA_URUN___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S3__RECD_GT_MPDU___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S3__RECD_LT_MPDU___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_RCVD_TLV_ABORT___M 0x10000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_RCVD_TLV_ABORT___S 28 +#define WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_TX_FRAME_START_INTR___M 0x0FFFFF00 +#define WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_TX_FRAME_START_INTR___S 8 +#define WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_TX_PHY_ERROR___M 0x00000080 +#define WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_TX_PHY_ERROR___S 7 +#define WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_RESPONSE_FRAME_ERROR___M 0x00000040 +#define WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_RESPONSE_FRAME_ERROR___S 6 +#define WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_TX_FRAME_END_INTR___M 0x00000020 +#define WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_TX_FRAME_END_INTR___S 5 +#define WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_WD_TOUT___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_IMR_S3__TXPCU_WD_TOUT___S 4 +#define WMAC0_MCMN_R0_MCMN_IMR_S3__BFEE_CV_TOUT___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_IMR_S3__BFEE_CV_TOUT___S 3 +#define WMAC0_MCMN_R0_MCMN_IMR_S3__DATA_URUN___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_IMR_S3__DATA_URUN___S 2 +#define WMAC0_MCMN_R0_MCMN_IMR_S3__RECD_GT_MPDU___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_IMR_S3__RECD_GT_MPDU___S 1 +#define WMAC0_MCMN_R0_MCMN_IMR_S3__RECD_LT_MPDU___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_IMR_S3__RECD_LT_MPDU___S 0 +#define WMAC0_MCMN_R0_MCMN_IMR_S3___M 0x1FFFFFFF +#define WMAC0_MCMN_R0_MCMN_IMR_S3___S 0 + +#define WMAC0_MCMN_R0_MCMN_IMR_S4 (0x00A89110) +#define WMAC0_MCMN_R0_MCMN_IMR_S4___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_IMR_S4___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_NAP_DONE_NOT_RCVD_INTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_NAP_ACK_NOT_RCVD_INTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_SYNTH_ON_ACK_NOT_RCVD_INTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_SYNTH_OFF_ACK_NOT_RCVD_INTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_ABORT_ACK_NOT_RCVD_INTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_ON_ACK_NOT_RCVD_INTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_OFF_ACK_NOT_RCVD_INTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S4__CBF_READ_REQ_ACK_INTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_NAP_DONE_NOT_RCVD_INTR___M 0x00000080 +#define WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_NAP_DONE_NOT_RCVD_INTR___S 7 +#define WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_NAP_ACK_NOT_RCVD_INTR___M 0x00000040 +#define WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_NAP_ACK_NOT_RCVD_INTR___S 6 +#define WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_SYNTH_ON_ACK_NOT_RCVD_INTR___M 0x00000020 +#define WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_SYNTH_ON_ACK_NOT_RCVD_INTR___S 5 +#define WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_SYNTH_OFF_ACK_NOT_RCVD_INTR___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_SYNTH_OFF_ACK_NOT_RCVD_INTR___S 4 +#define WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_ABORT_ACK_NOT_RCVD_INTR___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_ABORT_ACK_NOT_RCVD_INTR___S 3 +#define WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_ON_ACK_NOT_RCVD_INTR___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_ON_ACK_NOT_RCVD_INTR___S 2 +#define WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_OFF_ACK_NOT_RCVD_INTR___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_IMR_S4__PHYTX_OFF_ACK_NOT_RCVD_INTR___S 1 +#define WMAC0_MCMN_R0_MCMN_IMR_S4__CBF_READ_REQ_ACK_INTR___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_IMR_S4__CBF_READ_REQ_ACK_INTR___S 0 +#define WMAC0_MCMN_R0_MCMN_IMR_S4___M 0x000000FF +#define WMAC0_MCMN_R0_MCMN_IMR_S4___S 0 + +#define WMAC0_MCMN_R0_MCMN_IMR_S5 (0x00A89114) +#define WMAC0_MCMN_R0_MCMN_IMR_S5___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_IMR_S5___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__RXPCU_AXI_TO_P___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__CHECK_BCN___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__FILTER_BCN_PASS___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__FILTER_PACKET_PASS___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__BCN_HASH_MISMATCH___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__BCN_LENGTH_MISMATCH___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__RX_EARLY_DTIM___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__BCN_TSF_OOR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__RX_EARLY_TIM___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__BCN_TOUT_INTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__RX_FLOW_CONTROL___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__PHY_RXPCU_TLV_LENGTH_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__RX_MAX_LENGTH___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__WDOG_TIMEOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__MIB_COUNTER___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__RX_OVFL___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__RX_DTIM___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__RX_TIM___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__RX_NOTIM___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__RSSI_LOW___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__RSSI_HIGH___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__BCON_MISS___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__RXPCU_AXI_TO_P___M 0x80000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__RXPCU_AXI_TO_P___S 31 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__CHECK_BCN___M 0x40000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__CHECK_BCN___S 30 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__FILTER_BCN_PASS___M 0x20000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__FILTER_BCN_PASS___S 29 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__FILTER_PACKET_PASS___M 0x10000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__FILTER_PACKET_PASS___S 28 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__BCN_HASH_MISMATCH___M 0x0C000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__BCN_HASH_MISMATCH___S 26 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__BCN_LENGTH_MISMATCH___M 0x03000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__BCN_LENGTH_MISMATCH___S 24 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__RX_EARLY_DTIM___M 0x00800000 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__RX_EARLY_DTIM___S 23 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__BCN_TSF_OOR___M 0x00600000 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__BCN_TSF_OOR___S 21 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__RX_EARLY_TIM___M 0x00100000 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__RX_EARLY_TIM___S 20 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__BCN_TOUT_INTR___M 0x00080000 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__BCN_TOUT_INTR___S 19 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__RX_FLOW_CONTROL___M 0x00040000 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__RX_FLOW_CONTROL___S 18 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__PHY_RXPCU_TLV_LENGTH_ERR___M 0x00020000 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__PHY_RXPCU_TLV_LENGTH_ERR___S 17 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__RX_MAX_LENGTH___M 0x00010000 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__RX_MAX_LENGTH___S 16 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__WDOG_TIMEOUT___M 0x00008000 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__WDOG_TIMEOUT___S 15 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__MIB_COUNTER___M 0x00004000 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__MIB_COUNTER___S 14 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__RX_OVFL___M 0x00002000 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__RX_OVFL___S 13 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__RX_DTIM___M 0x00000C00 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__RX_DTIM___S 10 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__RX_TIM___M 0x00000300 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__RX_TIM___S 8 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__RX_NOTIM___M 0x000000C0 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__RX_NOTIM___S 6 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__RSSI_LOW___M 0x00000030 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__RSSI_LOW___S 4 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__RSSI_HIGH___M 0x0000000C +#define WMAC0_MCMN_R0_MCMN_IMR_S5__RSSI_HIGH___S 2 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__BCON_MISS___M 0x00000003 +#define WMAC0_MCMN_R0_MCMN_IMR_S5__BCON_MISS___S 0 +#define WMAC0_MCMN_R0_MCMN_IMR_S5___M 0xFFFFEFFF +#define WMAC0_MCMN_R0_MCMN_IMR_S5___S 0 + +#define WMAC0_MCMN_R0_MCMN_IMR_S6 (0x00A89118) +#define WMAC0_MCMN_R0_MCMN_IMR_S6___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_IMR_S6___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__WILDCARD_TRIGGER_RESP_P___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__RXPCU_USER_SETUP_EXT_LOST_P___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__TWT_SP_DONE_P___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__AST_PRESEARCH_NOT_FIND___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__RXPCU_ERR_P___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__RXPCU_TRIGGER_INFO_SENT_P___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__RXPCU_START_OF_RX_P___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__RXPCU_END_OF_RX_P___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__MAC_SENT_PHY_OFF___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__TBTT_THRESHOLD_REACHED___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__AVG_BCN_MISS___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__DTIM_SW_ATTENTION___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__DTIM_MOREDATA0___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__PHYRX_TLV_OOO_ERR_P___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__WILDCARD_TRIGGER_RESP_P___M 0x0000C000 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__WILDCARD_TRIGGER_RESP_P___S 14 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__RXPCU_USER_SETUP_EXT_LOST_P___M 0x00002000 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__RXPCU_USER_SETUP_EXT_LOST_P___S 13 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__TWT_SP_DONE_P___M 0x00001800 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__TWT_SP_DONE_P___S 11 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__AST_PRESEARCH_NOT_FIND___M 0x00000400 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__AST_PRESEARCH_NOT_FIND___S 10 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__RXPCU_ERR_P___M 0x00000200 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__RXPCU_ERR_P___S 9 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__RXPCU_TRIGGER_INFO_SENT_P___M 0x00000100 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__RXPCU_TRIGGER_INFO_SENT_P___S 8 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__RXPCU_START_OF_RX_P___M 0x00000080 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__RXPCU_START_OF_RX_P___S 7 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__RXPCU_END_OF_RX_P___M 0x00000040 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__RXPCU_END_OF_RX_P___S 6 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__MAC_SENT_PHY_OFF___M 0x00000020 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__MAC_SENT_PHY_OFF___S 5 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__TBTT_THRESHOLD_REACHED___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__TBTT_THRESHOLD_REACHED___S 4 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__AVG_BCN_MISS___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__AVG_BCN_MISS___S 3 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__DTIM_SW_ATTENTION___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__DTIM_SW_ATTENTION___S 2 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__DTIM_MOREDATA0___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__DTIM_MOREDATA0___S 1 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__PHYRX_TLV_OOO_ERR_P___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_IMR_S6__PHYRX_TLV_OOO_ERR_P___S 0 +#define WMAC0_MCMN_R0_MCMN_IMR_S6___M 0x0000FFFF +#define WMAC0_MCMN_R0_MCMN_IMR_S6___S 0 + +#define WMAC0_MCMN_R0_MCMN_IMR_S7 (0x00A8911C) +#define WMAC0_MCMN_R0_MCMN_IMR_S7___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_IMR_S7___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__UNEXP_11AH_FESSETUP_INTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__NO_MPDU_FIT_INTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__COMP_AMPDU_TRUNC_INTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__COEX_TX_INT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__COEX_RX_INT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__REMAIN_TX_TM_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__MPDU_LENGTH_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__SETUP_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__OVERFLOW_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__TXDMA_PDG_LEN_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__HWSCH_PDG_TLV_LEN_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__WRNG_TLV_ORD___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__RCV_FCS_BSY___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__PDG_WD_TOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__UNEXP_11AH_FESSETUP_INTR___M 0x00002000 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__UNEXP_11AH_FESSETUP_INTR___S 13 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__NO_MPDU_FIT_INTR___M 0x00001000 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__NO_MPDU_FIT_INTR___S 12 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__COMP_AMPDU_TRUNC_INTR___M 0x00000800 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__COMP_AMPDU_TRUNC_INTR___S 11 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__COEX_TX_INT___M 0x00000400 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__COEX_TX_INT___S 10 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__COEX_RX_INT___M 0x00000200 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__COEX_RX_INT___S 9 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__REMAIN_TX_TM_ERR___M 0x00000100 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__REMAIN_TX_TM_ERR___S 8 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__MPDU_LENGTH_ERR___M 0x00000080 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__MPDU_LENGTH_ERR___S 7 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__SETUP_ERR___M 0x00000040 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__SETUP_ERR___S 6 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__OVERFLOW_ERR___M 0x00000020 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__OVERFLOW_ERR___S 5 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__TXDMA_PDG_LEN_ERR___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__TXDMA_PDG_LEN_ERR___S 4 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__HWSCH_PDG_TLV_LEN_ERR___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__HWSCH_PDG_TLV_LEN_ERR___S 3 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__WRNG_TLV_ORD___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__WRNG_TLV_ORD___S 2 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__RCV_FCS_BSY___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__RCV_FCS_BSY___S 1 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__PDG_WD_TOUT___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_IMR_S7__PDG_WD_TOUT___S 0 +#define WMAC0_MCMN_R0_MCMN_IMR_S7___M 0x00003FFF +#define WMAC0_MCMN_R0_MCMN_IMR_S7___S 0 + +#define WMAC0_MCMN_R0_MCMN_IMR_S8 (0x00A89120) +#define WMAC0_MCMN_R0_MCMN_IMR_S8___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_IMR_S8___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S8__HW_RNG_THR___POR 0x0000 +#define WMAC0_MCMN_R0_MCMN_IMR_S8__HW_RNG_PSD___POR 0x0000 +#define WMAC0_MCMN_R0_MCMN_IMR_S8__HW_RNG_THR___M 0xFFFF0000 +#define WMAC0_MCMN_R0_MCMN_IMR_S8__HW_RNG_THR___S 16 +#define WMAC0_MCMN_R0_MCMN_IMR_S8__HW_RNG_PSD___M 0x0000FFFF +#define WMAC0_MCMN_R0_MCMN_IMR_S8__HW_RNG_PSD___S 0 +#define WMAC0_MCMN_R0_MCMN_IMR_S8___M 0xFFFFFFFF +#define WMAC0_MCMN_R0_MCMN_IMR_S8___S 0 + +#define WMAC0_MCMN_R0_MCMN_IMR_S9 (0x00A89124) +#define WMAC0_MCMN_R0_MCMN_IMR_S9___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_IMR_S9___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S9__HWSCH_PCU_GEN_TM_THR___POR 0x00 +#define WMAC0_MCMN_R0_MCMN_IMR_S9__HWSCH_PCU_GEN_TM_TRI___POR 0x00 +#define WMAC0_MCMN_R0_MCMN_IMR_S9__MTU_BKOF___POR 0x0000 +#define WMAC0_MCMN_R0_MCMN_IMR_S9__HWSCH_PCU_GEN_TM_THR___M 0xFF000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S9__HWSCH_PCU_GEN_TM_THR___S 24 +#define WMAC0_MCMN_R0_MCMN_IMR_S9__HWSCH_PCU_GEN_TM_TRI___M 0x00FF0000 +#define WMAC0_MCMN_R0_MCMN_IMR_S9__HWSCH_PCU_GEN_TM_TRI___S 16 +#define WMAC0_MCMN_R0_MCMN_IMR_S9__MTU_BKOF___M 0x0000FFFF +#define WMAC0_MCMN_R0_MCMN_IMR_S9__MTU_BKOF___S 0 +#define WMAC0_MCMN_R0_MCMN_IMR_S9___M 0xFFFFFFFF +#define WMAC0_MCMN_R0_MCMN_IMR_S9___S 0 + +#define WMAC0_MCMN_R0_MCMN_IMR_S10 (0x00A89128) +#define WMAC0_MCMN_R0_MCMN_IMR_S10___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_IMR_S10___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_CMD_STATUS_BUFFER_ERR_P___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_FES_STATUS_BUFFER_ERR_P___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_SFM_DELAY_EXCEEDED_INT_P___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_FES_STATUS_END_TIMEOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_RECEIVED_TRIGGER_INFO_INT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__SCH_RING_REQ_ERR_INT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__TQM_RING_REQ_ERR_INT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_TQM_RING_UPDATE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_TQM_STATUS_LOW_UPDATE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_FES_STATUS_LOW_UPDATE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_SCH_STATUS_LOW_UPDATE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_TQM_STATUS_PANIC_UPDATE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_FES_STATUS_PANIC_UPDATE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_SCH_STATUS_PANIC_UPDATE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__SFM_READ_USR_ID_COLLISION___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__SFM_WRITE_USR_ID_COLLISION___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_PCU_GEN_TM_OVERFLOW___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__MTU_TX_BOUNDARY_INT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_TX_STATUS_LOW_WMARK_REACHED___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_TX_STATUS_PANIC_WMARK_REACHED___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__AXI_RD_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__AXI_WR_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_WD_TOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_CMD_STATUS_BUFFER_ERR_P___M 0x02000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_CMD_STATUS_BUFFER_ERR_P___S 25 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_FES_STATUS_BUFFER_ERR_P___M 0x01000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_FES_STATUS_BUFFER_ERR_P___S 24 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_SFM_DELAY_EXCEEDED_INT_P___M 0x00800000 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_SFM_DELAY_EXCEEDED_INT_P___S 23 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_FES_STATUS_END_TIMEOUT___M 0x00400000 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_FES_STATUS_END_TIMEOUT___S 22 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_RECEIVED_TRIGGER_INFO_INT___M 0x00200000 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_RECEIVED_TRIGGER_INFO_INT___S 21 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__SCH_RING_REQ_ERR_INT___M 0x00100000 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__SCH_RING_REQ_ERR_INT___S 20 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__TQM_RING_REQ_ERR_INT___M 0x00080000 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__TQM_RING_REQ_ERR_INT___S 19 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_TQM_RING_UPDATE___M 0x00040000 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_TQM_RING_UPDATE___S 18 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_TQM_STATUS_LOW_UPDATE___M 0x00020000 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_TQM_STATUS_LOW_UPDATE___S 17 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_FES_STATUS_LOW_UPDATE___M 0x00010000 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_FES_STATUS_LOW_UPDATE___S 16 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_SCH_STATUS_LOW_UPDATE___M 0x00008000 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_SCH_STATUS_LOW_UPDATE___S 15 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_TQM_STATUS_PANIC_UPDATE___M 0x00004000 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_TQM_STATUS_PANIC_UPDATE___S 14 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_FES_STATUS_PANIC_UPDATE___M 0x00002000 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_FES_STATUS_PANIC_UPDATE___S 13 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_SCH_STATUS_PANIC_UPDATE___M 0x00001000 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_SCH_STATUS_PANIC_UPDATE___S 12 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__SFM_READ_USR_ID_COLLISION___M 0x00000800 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__SFM_READ_USR_ID_COLLISION___S 11 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__SFM_WRITE_USR_ID_COLLISION___M 0x00000400 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__SFM_WRITE_USR_ID_COLLISION___S 10 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_PCU_GEN_TM_OVERFLOW___M 0x00000200 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_PCU_GEN_TM_OVERFLOW___S 9 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__MTU_TX_BOUNDARY_INT___M 0x000001E0 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__MTU_TX_BOUNDARY_INT___S 5 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_TX_STATUS_LOW_WMARK_REACHED___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_TX_STATUS_LOW_WMARK_REACHED___S 4 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_TX_STATUS_PANIC_WMARK_REACHED___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_TX_STATUS_PANIC_WMARK_REACHED___S 3 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__AXI_RD_ERR___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__AXI_RD_ERR___S 2 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__AXI_WR_ERR___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__AXI_WR_ERR___S 1 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_WD_TOUT___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_IMR_S10__HWSCH_WD_TOUT___S 0 +#define WMAC0_MCMN_R0_MCMN_IMR_S10___M 0x03FFFFFF +#define WMAC0_MCMN_R0_MCMN_IMR_S10___S 0 + +#define WMAC0_MCMN_R0_MCMN_IMR_S11 (0x00A8912C) +#define WMAC0_MCMN_R0_MCMN_IMR_S11___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_IMR_S11___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S11__WDTIMEOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S11__AXI_RD_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S11__AXI_WR_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S11__AXI_WR_LAST_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S11__WDTIMEOUT___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_IMR_S11__WDTIMEOUT___S 3 +#define WMAC0_MCMN_R0_MCMN_IMR_S11__AXI_RD_ERR___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_IMR_S11__AXI_RD_ERR___S 2 +#define WMAC0_MCMN_R0_MCMN_IMR_S11__AXI_WR_ERR___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_IMR_S11__AXI_WR_ERR___S 1 +#define WMAC0_MCMN_R0_MCMN_IMR_S11__AXI_WR_LAST_ERR___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_IMR_S11__AXI_WR_LAST_ERR___S 0 +#define WMAC0_MCMN_R0_MCMN_IMR_S11___M 0x0000000F +#define WMAC0_MCMN_R0_MCMN_IMR_S11___S 0 + +#define WMAC0_MCMN_R0_MCMN_IMR_S12 (0x00A89130) +#define WMAC0_MCMN_R0_MCMN_IMR_S12___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_IMR_S12___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S12__PHY2MAC_RX_FIFO_OVERFLOW_MAC_CLK_P___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S12__RX_TLV_ERROR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S12__TX_TLV_ERROR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S12__PHY2MAC_RX_FIFO_OVERFLOW_MAC_CLK_P___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_IMR_S12__PHY2MAC_RX_FIFO_OVERFLOW_MAC_CLK_P___S 2 +#define WMAC0_MCMN_R0_MCMN_IMR_S12__RX_TLV_ERROR___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_IMR_S12__RX_TLV_ERROR___S 1 +#define WMAC0_MCMN_R0_MCMN_IMR_S12__TX_TLV_ERROR___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_IMR_S12__TX_TLV_ERROR___S 0 +#define WMAC0_MCMN_R0_MCMN_IMR_S12___M 0x00000007 +#define WMAC0_MCMN_R0_MCMN_IMR_S12___S 0 + +#define WMAC0_MCMN_R0_MCMN_IMR_S13 (0x00A89134) +#define WMAC0_MCMN_R0_MCMN_IMR_S13___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_IMR_S13___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S13__RRI_ERR_INTR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S13__RRI_ERR_INTR___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_IMR_S13__RRI_ERR_INTR___S 0 +#define WMAC0_MCMN_R0_MCMN_IMR_S13___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_IMR_S13___S 0 + +#define WMAC0_MCMN_R0_MCMN_IMR_S14 (0x00A89138) +#define WMAC0_MCMN_R0_MCMN_IMR_S14___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_IMR_S14___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__RRI_APB_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__RRI_APB_WR_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__RRI_APB_WR_TO_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__AMPI_APB_RD_WMAC_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__AMPI_APB_WR_WMAC_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__AMPI_APB_WR_TO_RD_WMAC_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__MXI_APB_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__MXI_APB_WR_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__MXI_APB_WR_TO_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__HWSCH_APB_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__HWSCH_APB_WR_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__HWSCH_APB_WR_TO_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__PDG_APB_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__PDG_APB_WR_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__PDG_APB_WR_TO_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__RXPCU_APB_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__RXPCU_APB_WR_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__RXPCU_APB_WR_TO_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__TXPCU_APB_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__TXPCU_APB_WR_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__TXPCU_APB_WR_TO_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__RXDMA_APB_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__RXDMA_APB_WR_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__RXDMA_APB_WR_TO_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__TXDMA_APB_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__TXDMA_APB_WR_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__TXDMA_APB_WR_TO_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__CRYPTO_APB_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__CRYPTO_APB_WR_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__CRYPTO_APB_WR_TO_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__RRI_APB_RD_INVALID___M 0x20000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__RRI_APB_RD_INVALID___S 29 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__RRI_APB_WR_INVALID___M 0x10000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__RRI_APB_WR_INVALID___S 28 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__RRI_APB_WR_TO_RD_INVALID___M 0x08000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__RRI_APB_WR_TO_RD_INVALID___S 27 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__AMPI_APB_RD_WMAC_INVALID___M 0x04000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__AMPI_APB_RD_WMAC_INVALID___S 26 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__AMPI_APB_WR_WMAC_INVALID___M 0x02000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__AMPI_APB_WR_WMAC_INVALID___S 25 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__AMPI_APB_WR_TO_RD_WMAC_INVALID___M 0x01000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__AMPI_APB_WR_TO_RD_WMAC_INVALID___S 24 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__MXI_APB_RD_INVALID___M 0x00800000 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__MXI_APB_RD_INVALID___S 23 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__MXI_APB_WR_INVALID___M 0x00400000 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__MXI_APB_WR_INVALID___S 22 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__MXI_APB_WR_TO_RD_INVALID___M 0x00200000 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__MXI_APB_WR_TO_RD_INVALID___S 21 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__HWSCH_APB_RD_INVALID___M 0x00100000 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__HWSCH_APB_RD_INVALID___S 20 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__HWSCH_APB_WR_INVALID___M 0x00080000 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__HWSCH_APB_WR_INVALID___S 19 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__HWSCH_APB_WR_TO_RD_INVALID___M 0x00040000 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__HWSCH_APB_WR_TO_RD_INVALID___S 18 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__PDG_APB_RD_INVALID___M 0x00020000 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__PDG_APB_RD_INVALID___S 17 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__PDG_APB_WR_INVALID___M 0x00010000 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__PDG_APB_WR_INVALID___S 16 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__PDG_APB_WR_TO_RD_INVALID___M 0x00008000 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__PDG_APB_WR_TO_RD_INVALID___S 15 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__RXPCU_APB_RD_INVALID___M 0x00004000 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__RXPCU_APB_RD_INVALID___S 14 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__RXPCU_APB_WR_INVALID___M 0x00002000 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__RXPCU_APB_WR_INVALID___S 13 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__RXPCU_APB_WR_TO_RD_INVALID___M 0x00001000 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__RXPCU_APB_WR_TO_RD_INVALID___S 12 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__TXPCU_APB_RD_INVALID___M 0x00000800 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__TXPCU_APB_RD_INVALID___S 11 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__TXPCU_APB_WR_INVALID___M 0x00000400 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__TXPCU_APB_WR_INVALID___S 10 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__TXPCU_APB_WR_TO_RD_INVALID___M 0x00000200 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__TXPCU_APB_WR_TO_RD_INVALID___S 9 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__RXDMA_APB_RD_INVALID___M 0x00000100 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__RXDMA_APB_RD_INVALID___S 8 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__RXDMA_APB_WR_INVALID___M 0x00000080 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__RXDMA_APB_WR_INVALID___S 7 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__RXDMA_APB_WR_TO_RD_INVALID___M 0x00000040 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__RXDMA_APB_WR_TO_RD_INVALID___S 6 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__TXDMA_APB_RD_INVALID___M 0x00000020 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__TXDMA_APB_RD_INVALID___S 5 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__TXDMA_APB_WR_INVALID___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__TXDMA_APB_WR_INVALID___S 4 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__TXDMA_APB_WR_TO_RD_INVALID___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__TXDMA_APB_WR_TO_RD_INVALID___S 3 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__CRYPTO_APB_RD_INVALID___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__CRYPTO_APB_RD_INVALID___S 2 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__CRYPTO_APB_WR_INVALID___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__CRYPTO_APB_WR_INVALID___S 1 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__CRYPTO_APB_WR_TO_RD_INVALID___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_IMR_S14__CRYPTO_APB_WR_TO_RD_INVALID___S 0 +#define WMAC0_MCMN_R0_MCMN_IMR_S14___M 0x3FFFFFFF +#define WMAC0_MCMN_R0_MCMN_IMR_S14___S 0 + +#define WMAC0_MCMN_R0_MCMN_IMR_S15 (0x00A8913C) +#define WMAC0_MCMN_R0_MCMN_IMR_S15___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_IMR_S15___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__MCMN_APB_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__MCMN_APB_WR_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__MCMN_APB_WR_TO_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__CMN_PARSER_APB_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__CMN_PARSER_APB_WR_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__CMN_PARSER_APB_WR_TO_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__AMPI_APB_RD_PHY_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__AMPI_APB_WR_PHY_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__AMPI_APB_WR_TO_RD_PHY_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__RXOLE_APB_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__RXOLE_APB_WR_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__RXOLE_APB_WR_TO_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__TXOLE_APB_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__TXOLE_APB_WR_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__TXOLE_APB_WR_TO_RD_INVALID___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__MCMN_APB_RD_INVALID___M 0x00004000 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__MCMN_APB_RD_INVALID___S 14 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__MCMN_APB_WR_INVALID___M 0x00002000 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__MCMN_APB_WR_INVALID___S 13 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__MCMN_APB_WR_TO_RD_INVALID___M 0x00001000 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__MCMN_APB_WR_TO_RD_INVALID___S 12 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__CMN_PARSER_APB_RD_INVALID___M 0x00000800 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__CMN_PARSER_APB_RD_INVALID___S 11 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__CMN_PARSER_APB_WR_INVALID___M 0x00000400 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__CMN_PARSER_APB_WR_INVALID___S 10 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__CMN_PARSER_APB_WR_TO_RD_INVALID___M 0x00000200 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__CMN_PARSER_APB_WR_TO_RD_INVALID___S 9 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__AMPI_APB_RD_PHY_INVALID___M 0x00000100 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__AMPI_APB_RD_PHY_INVALID___S 8 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__AMPI_APB_WR_PHY_INVALID___M 0x00000080 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__AMPI_APB_WR_PHY_INVALID___S 7 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__AMPI_APB_WR_TO_RD_PHY_INVALID___M 0x00000040 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__AMPI_APB_WR_TO_RD_PHY_INVALID___S 6 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__RXOLE_APB_RD_INVALID___M 0x00000020 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__RXOLE_APB_RD_INVALID___S 5 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__RXOLE_APB_WR_INVALID___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__RXOLE_APB_WR_INVALID___S 4 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__RXOLE_APB_WR_TO_RD_INVALID___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__RXOLE_APB_WR_TO_RD_INVALID___S 3 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__TXOLE_APB_RD_INVALID___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__TXOLE_APB_RD_INVALID___S 2 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__TXOLE_APB_WR_INVALID___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__TXOLE_APB_WR_INVALID___S 1 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__TXOLE_APB_WR_TO_RD_INVALID___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_IMR_S15__TXOLE_APB_WR_TO_RD_INVALID___S 0 +#define WMAC0_MCMN_R0_MCMN_IMR_S15___M 0x00007FFF +#define WMAC0_MCMN_R0_MCMN_IMR_S15___S 0 + +#define WMAC0_MCMN_R0_MCMN_IMR_S16 (0x00A89140) +#define WMAC0_MCMN_R0_MCMN_IMR_S16___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_IMR_S16___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_IPV6_JBGM___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_IPV6_EXT_HD_BYTES_EXCEEDED___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_MSDU_LENGTH_ERROR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_ETH_ERROR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_WMAC_ERROR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_WDOG_TOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__PV1_WRONG_KEY_TYPE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__FRAG_EN_SW_ENCTYPTED___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__TX_ILLEGAL___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__INCOMPLETE_LLC_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__LENGTH_MISMATCH_FOR_802_3_FRAME_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__NO_FULL_MSDU_FOR_CHECKSUM_EN_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__AMSDU_FRM_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__WEP_KEY_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__TX_PV1_AMSDU_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__TX_FRAG_AMSDU_AMPDU___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__TX_MORE_FRAG___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__TX_TLV_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__TX_WDOG_TOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_IPV6_JBGM___M 0x00040000 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_IPV6_JBGM___S 18 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_IPV6_EXT_HD_BYTES_EXCEEDED___M 0x00020000 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_IPV6_EXT_HD_BYTES_EXCEEDED___S 17 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_MSDU_LENGTH_ERROR___M 0x00010000 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_MSDU_LENGTH_ERROR___S 16 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_ETH_ERROR___M 0x00008000 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_ETH_ERROR___S 15 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_WMAC_ERROR___M 0x00004000 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_WMAC_ERROR___S 14 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_WDOG_TOUT___M 0x00002000 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__CMN_PARSER_WDOG_TOUT___S 13 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__PV1_WRONG_KEY_TYPE___M 0x00001000 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__PV1_WRONG_KEY_TYPE___S 12 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__FRAG_EN_SW_ENCTYPTED___M 0x00000800 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__FRAG_EN_SW_ENCTYPTED___S 11 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__TX_ILLEGAL___M 0x00000400 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__TX_ILLEGAL___S 10 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__INCOMPLETE_LLC_ERR___M 0x00000200 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__INCOMPLETE_LLC_ERR___S 9 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__LENGTH_MISMATCH_FOR_802_3_FRAME_ERR___M 0x00000100 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__LENGTH_MISMATCH_FOR_802_3_FRAME_ERR___S 8 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__NO_FULL_MSDU_FOR_CHECKSUM_EN_ERR___M 0x00000080 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__NO_FULL_MSDU_FOR_CHECKSUM_EN_ERR___S 7 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__AMSDU_FRM_ERR___M 0x00000040 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__AMSDU_FRM_ERR___S 6 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__WEP_KEY_ERR___M 0x00000020 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__WEP_KEY_ERR___S 5 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__TX_PV1_AMSDU_ERR___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__TX_PV1_AMSDU_ERR___S 4 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__TX_FRAG_AMSDU_AMPDU___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__TX_FRAG_AMSDU_AMPDU___S 3 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__TX_MORE_FRAG___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__TX_MORE_FRAG___S 2 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__TX_TLV_ERR___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__TX_TLV_ERR___S 1 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__TX_WDOG_TOUT___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_IMR_S16__TX_WDOG_TOUT___S 0 +#define WMAC0_MCMN_R0_MCMN_IMR_S16___M 0x0007FFFF +#define WMAC0_MCMN_R0_MCMN_IMR_S16___S 0 + +#define WMAC0_MCMN_R0_MCMN_IMR_S17 (0x00A89144) +#define WMAC0_MCMN_R0_MCMN_IMR_S17___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_IMR_S17___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_PPDU_END___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_L3_L4_HD_BYTES_EXCEEDED_256___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_CP_INT_WDOG___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_CCE_ERR_CLASSIFY_DIS___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_CCE_SW_REQ___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_CCE_WDOG___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_MCMN_IPV6_JMBG___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_IPV6_HD_BYTES___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_WMAC_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_AMSDU_PARSER_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_MSDU_LEN___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_TLV_ERROR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_WDOG_TOUT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_PPDU_END___M 0x00001000 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_PPDU_END___S 12 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_L3_L4_HD_BYTES_EXCEEDED_256___M 0x00000800 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_L3_L4_HD_BYTES_EXCEEDED_256___S 11 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_CP_INT_WDOG___M 0x00000400 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_CP_INT_WDOG___S 10 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_CCE_ERR_CLASSIFY_DIS___M 0x00000200 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_CCE_ERR_CLASSIFY_DIS___S 9 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_CCE_SW_REQ___M 0x00000100 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_CCE_SW_REQ___S 8 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_CCE_WDOG___M 0x00000080 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_CCE_WDOG___S 7 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_MCMN_IPV6_JMBG___M 0x00000040 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_MCMN_IPV6_JMBG___S 6 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_IPV6_HD_BYTES___M 0x00000020 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_IPV6_HD_BYTES___S 5 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_WMAC_ERR___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_WMAC_ERR___S 4 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_AMSDU_PARSER_ERR___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_AMSDU_PARSER_ERR___S 3 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_MSDU_LEN___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_MSDU_LEN___S 2 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_TLV_ERROR___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_TLV_ERROR___S 1 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_WDOG_TOUT___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_IMR_S17__RX_WDOG_TOUT___S 0 +#define WMAC0_MCMN_R0_MCMN_IMR_S17___M 0x00001FFF +#define WMAC0_MCMN_R0_MCMN_IMR_S17___S 0 + +#define WMAC0_MCMN_R0_MCMN_IMR_S18 (0x00A89148) +#define WMAC0_MCMN_R0_MCMN_IMR_S18___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_IMR_S18___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S18__RRI_MODIFIED_ACCESS_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S18__WDG_TIMEOUT_INT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S18__AP_WR_TO_RD_ONLY_ADDR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S18__APB_WR_INVALID_ADDR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S18__APB_RD_INVALID_ADDR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S18__INIT_NOT_ENOUGH_BUFFER___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S18__RRI_MODIFIED_ACCESS_ERR___M 0x00000020 +#define WMAC0_MCMN_R0_MCMN_IMR_S18__RRI_MODIFIED_ACCESS_ERR___S 5 +#define WMAC0_MCMN_R0_MCMN_IMR_S18__WDG_TIMEOUT_INT___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_IMR_S18__WDG_TIMEOUT_INT___S 4 +#define WMAC0_MCMN_R0_MCMN_IMR_S18__AP_WR_TO_RD_ONLY_ADDR___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_IMR_S18__AP_WR_TO_RD_ONLY_ADDR___S 3 +#define WMAC0_MCMN_R0_MCMN_IMR_S18__APB_WR_INVALID_ADDR___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_IMR_S18__APB_WR_INVALID_ADDR___S 2 +#define WMAC0_MCMN_R0_MCMN_IMR_S18__APB_RD_INVALID_ADDR___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_IMR_S18__APB_RD_INVALID_ADDR___S 1 +#define WMAC0_MCMN_R0_MCMN_IMR_S18__INIT_NOT_ENOUGH_BUFFER___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_IMR_S18__INIT_NOT_ENOUGH_BUFFER___S 0 +#define WMAC0_MCMN_R0_MCMN_IMR_S18___M 0x0000003F +#define WMAC0_MCMN_R0_MCMN_IMR_S18___S 0 + +#define WMAC0_MCMN_R0_MCMN_IMR_S20 (0x00A89150) +#define WMAC0_MCMN_R0_MCMN_IMR_S20___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_IMR_S20___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S20__SRC_RING_REQ_ERR___POR 0x00 +#define WMAC0_MCMN_R0_MCMN_IMR_S20__SRC_RING_WATCHDOG_ERR___POR 0x00 +#define WMAC0_MCMN_R0_MCMN_IMR_S20__SRC_RING_SW_INT___POR 0x00 +#define WMAC0_MCMN_R0_MCMN_IMR_S20__SRC_RING_REQ_ERR___M 0x0003F000 +#define WMAC0_MCMN_R0_MCMN_IMR_S20__SRC_RING_REQ_ERR___S 12 +#define WMAC0_MCMN_R0_MCMN_IMR_S20__SRC_RING_WATCHDOG_ERR___M 0x00000FC0 +#define WMAC0_MCMN_R0_MCMN_IMR_S20__SRC_RING_WATCHDOG_ERR___S 6 +#define WMAC0_MCMN_R0_MCMN_IMR_S20__SRC_RING_SW_INT___M 0x0000003F +#define WMAC0_MCMN_R0_MCMN_IMR_S20__SRC_RING_SW_INT___S 0 +#define WMAC0_MCMN_R0_MCMN_IMR_S20___M 0x0003FFFF +#define WMAC0_MCMN_R0_MCMN_IMR_S20___S 0 + +#define WMAC0_MCMN_R0_MCMN_IMR_S21 (0x00A89154) +#define WMAC0_MCMN_R0_MCMN_IMR_S21___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_IMR_S21___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S21__DEST_RING_REQ_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S21__DEST_RING_WATCHDOG_ERR___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S21__DEST_RING_SW_INT___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S21__DEST_RING_REQ_ERR___M 0x00000F00 +#define WMAC0_MCMN_R0_MCMN_IMR_S21__DEST_RING_REQ_ERR___S 8 +#define WMAC0_MCMN_R0_MCMN_IMR_S21__DEST_RING_WATCHDOG_ERR___M 0x000000F0 +#define WMAC0_MCMN_R0_MCMN_IMR_S21__DEST_RING_WATCHDOG_ERR___S 4 +#define WMAC0_MCMN_R0_MCMN_IMR_S21__DEST_RING_SW_INT___M 0x0000000F +#define WMAC0_MCMN_R0_MCMN_IMR_S21__DEST_RING_SW_INT___S 0 +#define WMAC0_MCMN_R0_MCMN_IMR_S21___M 0x00000FFF +#define WMAC0_MCMN_R0_MCMN_IMR_S21___S 0 + +#define WMAC0_MCMN_R0_MCMN_IMR_S22 (0x00A89158) +#define WMAC0_MCMN_R0_MCMN_IMR_S22___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_IMR_S22___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S22__SRC_RING_REQ_ERR___POR 0x00 +#define WMAC0_MCMN_R0_MCMN_IMR_S22__SRC_RING_WATCHDOG_ERR___POR 0x00 +#define WMAC0_MCMN_R0_MCMN_IMR_S22__SRC_RING_SW_INT___POR 0x00 +#define WMAC0_MCMN_R0_MCMN_IMR_S22__SRC_RING_REQ_ERR___M 0x0003F000 +#define WMAC0_MCMN_R0_MCMN_IMR_S22__SRC_RING_REQ_ERR___S 12 +#define WMAC0_MCMN_R0_MCMN_IMR_S22__SRC_RING_WATCHDOG_ERR___M 0x00000FC0 +#define WMAC0_MCMN_R0_MCMN_IMR_S22__SRC_RING_WATCHDOG_ERR___S 6 +#define WMAC0_MCMN_R0_MCMN_IMR_S22__SRC_RING_SW_INT___M 0x0000003F +#define WMAC0_MCMN_R0_MCMN_IMR_S22__SRC_RING_SW_INT___S 0 +#define WMAC0_MCMN_R0_MCMN_IMR_S22___M 0x0003FFFF +#define WMAC0_MCMN_R0_MCMN_IMR_S22___S 0 + +#define WMAC0_MCMN_R0_MCMN_IMR_S26 (0x00A89168) +#define WMAC0_MCMN_R0_MCMN_IMR_S26___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_IMR_S26___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S26__SFM_WITH_DATA___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S26__HWSCH_CMD_RING_NOT_EMPTY___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S26__TX_FLUSH_NOT_RECEIVED___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S26__RX_FLUSH_NOT_RECEIVED___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S26__SFM_WITH_DATA___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_IMR_S26__SFM_WITH_DATA___S 3 +#define WMAC0_MCMN_R0_MCMN_IMR_S26__HWSCH_CMD_RING_NOT_EMPTY___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_IMR_S26__HWSCH_CMD_RING_NOT_EMPTY___S 2 +#define WMAC0_MCMN_R0_MCMN_IMR_S26__TX_FLUSH_NOT_RECEIVED___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_IMR_S26__TX_FLUSH_NOT_RECEIVED___S 1 +#define WMAC0_MCMN_R0_MCMN_IMR_S26__RX_FLUSH_NOT_RECEIVED___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_IMR_S26__RX_FLUSH_NOT_RECEIVED___S 0 +#define WMAC0_MCMN_R0_MCMN_IMR_S26___M 0x0000000F +#define WMAC0_MCMN_R0_MCMN_IMR_S26___S 0 + +#define WMAC0_MCMN_R0_MCMN_IMR_S8_EXT (0x00A8916C) +#define WMAC0_MCMN_R0_MCMN_IMR_S8_EXT___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_IMR_S8_EXT___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S8_EXT__HW_RNG_THR_19_16___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S8_EXT__HW_RNG_PSD_19_16___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S8_EXT__HW_RNG_THR_19_16___M 0x000000F0 +#define WMAC0_MCMN_R0_MCMN_IMR_S8_EXT__HW_RNG_THR_19_16___S 4 +#define WMAC0_MCMN_R0_MCMN_IMR_S8_EXT__HW_RNG_PSD_19_16___M 0x0000000F +#define WMAC0_MCMN_R0_MCMN_IMR_S8_EXT__HW_RNG_PSD_19_16___S 0 +#define WMAC0_MCMN_R0_MCMN_IMR_S8_EXT___M 0x000000FF +#define WMAC0_MCMN_R0_MCMN_IMR_S8_EXT___S 0 + +#define WMAC0_MCMN_R0_MCMN_IMR_S9_EXT (0x00A89170) +#define WMAC0_MCMN_R0_MCMN_IMR_S9_EXT___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_IMR_S9_EXT___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_IMR_S9_EXT__MTU_BKOF_19_16___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_S9_EXT__MTU_BKOF_19_16___M 0x0000000F +#define WMAC0_MCMN_R0_MCMN_IMR_S9_EXT__MTU_BKOF_19_16___S 0 +#define WMAC0_MCMN_R0_MCMN_IMR_S9_EXT___M 0x0000000F +#define WMAC0_MCMN_R0_MCMN_IMR_S9_EXT___S 0 + +#define WMAC0_MCMN_R0_MCMN_ISR_P (0x00A89200) +#define WMAC0_MCMN_R0_MCMN_ISR_P___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_ISR_P___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_ISR_P__MCMN___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_P__LPEC1___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_P__LPEC0___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_P__RXDMA1_SRC_SRNG___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_P__RXDMA_DEST_SRNG___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_P__RXDMA_SRC_SRNG___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_P__SFM___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_P__RXOLE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_P__TXOLE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_P__APB1___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_P__APB0___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_P__RRI___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_P__AMPI___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_P__MXI___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_P__HWSCH2___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_P__HWSCH1___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_P__HWSCH0___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_P__PDG___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_P__RXPCU1___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_P__RXPCU0___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_P__TXPCU1___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_P__TXPCU0___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_P__RXDMA___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_P__TXDMA___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_P__CRYPTO___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_P__MCMN___M 0x04000000 +#define WMAC0_MCMN_R0_MCMN_ISR_P__MCMN___S 26 +#define WMAC0_MCMN_R0_MCMN_ISR_P__LPEC1___M 0x02000000 +#define WMAC0_MCMN_R0_MCMN_ISR_P__LPEC1___S 25 +#define WMAC0_MCMN_R0_MCMN_ISR_P__LPEC0___M 0x01000000 +#define WMAC0_MCMN_R0_MCMN_ISR_P__LPEC0___S 24 +#define WMAC0_MCMN_R0_MCMN_ISR_P__RXDMA1_SRC_SRNG___M 0x00400000 +#define WMAC0_MCMN_R0_MCMN_ISR_P__RXDMA1_SRC_SRNG___S 22 +#define WMAC0_MCMN_R0_MCMN_ISR_P__RXDMA_DEST_SRNG___M 0x00200000 +#define WMAC0_MCMN_R0_MCMN_ISR_P__RXDMA_DEST_SRNG___S 21 +#define WMAC0_MCMN_R0_MCMN_ISR_P__RXDMA_SRC_SRNG___M 0x00100000 +#define WMAC0_MCMN_R0_MCMN_ISR_P__RXDMA_SRC_SRNG___S 20 +#define WMAC0_MCMN_R0_MCMN_ISR_P__SFM___M 0x00040000 +#define WMAC0_MCMN_R0_MCMN_ISR_P__SFM___S 18 +#define WMAC0_MCMN_R0_MCMN_ISR_P__RXOLE___M 0x00020000 +#define WMAC0_MCMN_R0_MCMN_ISR_P__RXOLE___S 17 +#define WMAC0_MCMN_R0_MCMN_ISR_P__TXOLE___M 0x00010000 +#define WMAC0_MCMN_R0_MCMN_ISR_P__TXOLE___S 16 +#define WMAC0_MCMN_R0_MCMN_ISR_P__APB1___M 0x00008000 +#define WMAC0_MCMN_R0_MCMN_ISR_P__APB1___S 15 +#define WMAC0_MCMN_R0_MCMN_ISR_P__APB0___M 0x00004000 +#define WMAC0_MCMN_R0_MCMN_ISR_P__APB0___S 14 +#define WMAC0_MCMN_R0_MCMN_ISR_P__RRI___M 0x00002000 +#define WMAC0_MCMN_R0_MCMN_ISR_P__RRI___S 13 +#define WMAC0_MCMN_R0_MCMN_ISR_P__AMPI___M 0x00001000 +#define WMAC0_MCMN_R0_MCMN_ISR_P__AMPI___S 12 +#define WMAC0_MCMN_R0_MCMN_ISR_P__MXI___M 0x00000800 +#define WMAC0_MCMN_R0_MCMN_ISR_P__MXI___S 11 +#define WMAC0_MCMN_R0_MCMN_ISR_P__HWSCH2___M 0x00000400 +#define WMAC0_MCMN_R0_MCMN_ISR_P__HWSCH2___S 10 +#define WMAC0_MCMN_R0_MCMN_ISR_P__HWSCH1___M 0x00000200 +#define WMAC0_MCMN_R0_MCMN_ISR_P__HWSCH1___S 9 +#define WMAC0_MCMN_R0_MCMN_ISR_P__HWSCH0___M 0x00000100 +#define WMAC0_MCMN_R0_MCMN_ISR_P__HWSCH0___S 8 +#define WMAC0_MCMN_R0_MCMN_ISR_P__PDG___M 0x00000080 +#define WMAC0_MCMN_R0_MCMN_ISR_P__PDG___S 7 +#define WMAC0_MCMN_R0_MCMN_ISR_P__RXPCU1___M 0x00000040 +#define WMAC0_MCMN_R0_MCMN_ISR_P__RXPCU1___S 6 +#define WMAC0_MCMN_R0_MCMN_ISR_P__RXPCU0___M 0x00000020 +#define WMAC0_MCMN_R0_MCMN_ISR_P__RXPCU0___S 5 +#define WMAC0_MCMN_R0_MCMN_ISR_P__TXPCU1___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_ISR_P__TXPCU1___S 4 +#define WMAC0_MCMN_R0_MCMN_ISR_P__TXPCU0___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_ISR_P__TXPCU0___S 3 +#define WMAC0_MCMN_R0_MCMN_ISR_P__RXDMA___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_ISR_P__RXDMA___S 2 +#define WMAC0_MCMN_R0_MCMN_ISR_P__TXDMA___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_ISR_P__TXDMA___S 1 +#define WMAC0_MCMN_R0_MCMN_ISR_P__CRYPTO___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_ISR_P__CRYPTO___S 0 +#define WMAC0_MCMN_R0_MCMN_ISR_P___M 0x0777FFFF +#define WMAC0_MCMN_R0_MCMN_ISR_P___S 0 + +#define WMAC0_MCMN_R0_MCMN_IMR_P (0x00A89204) +#define WMAC0_MCMN_R0_MCMN_IMR_P___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_IMR_P___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_IMR_P__MCMN___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_P__LPEC1___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_P__LPEC0___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_P__RXDMA1_SRC_SRNG___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_P__RXDMA_DEST_SRNG___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_P__RXDMA_SRC_SRNG___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_P__SFM___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_P__RXOLE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_P__TXOLE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_P__APB1___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_P__APB0___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_P__RRI___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_P__AMPI___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_P__MXI___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_P__HWSCH2___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_P__HWSCH1___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_P__HWSCH0___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_P__PDG___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_P__RXPCU1___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_P__RXPCU0___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_P__TXPCU1___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_P__TXPCU0___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_P__RXDMA___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_P__TXDMA___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_P__CRYPTO___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_P__MCMN___M 0x04000000 +#define WMAC0_MCMN_R0_MCMN_IMR_P__MCMN___S 26 +#define WMAC0_MCMN_R0_MCMN_IMR_P__LPEC1___M 0x02000000 +#define WMAC0_MCMN_R0_MCMN_IMR_P__LPEC1___S 25 +#define WMAC0_MCMN_R0_MCMN_IMR_P__LPEC0___M 0x01000000 +#define WMAC0_MCMN_R0_MCMN_IMR_P__LPEC0___S 24 +#define WMAC0_MCMN_R0_MCMN_IMR_P__RXDMA1_SRC_SRNG___M 0x00400000 +#define WMAC0_MCMN_R0_MCMN_IMR_P__RXDMA1_SRC_SRNG___S 22 +#define WMAC0_MCMN_R0_MCMN_IMR_P__RXDMA_DEST_SRNG___M 0x00200000 +#define WMAC0_MCMN_R0_MCMN_IMR_P__RXDMA_DEST_SRNG___S 21 +#define WMAC0_MCMN_R0_MCMN_IMR_P__RXDMA_SRC_SRNG___M 0x00100000 +#define WMAC0_MCMN_R0_MCMN_IMR_P__RXDMA_SRC_SRNG___S 20 +#define WMAC0_MCMN_R0_MCMN_IMR_P__SFM___M 0x00040000 +#define WMAC0_MCMN_R0_MCMN_IMR_P__SFM___S 18 +#define WMAC0_MCMN_R0_MCMN_IMR_P__RXOLE___M 0x00020000 +#define WMAC0_MCMN_R0_MCMN_IMR_P__RXOLE___S 17 +#define WMAC0_MCMN_R0_MCMN_IMR_P__TXOLE___M 0x00010000 +#define WMAC0_MCMN_R0_MCMN_IMR_P__TXOLE___S 16 +#define WMAC0_MCMN_R0_MCMN_IMR_P__APB1___M 0x00008000 +#define WMAC0_MCMN_R0_MCMN_IMR_P__APB1___S 15 +#define WMAC0_MCMN_R0_MCMN_IMR_P__APB0___M 0x00004000 +#define WMAC0_MCMN_R0_MCMN_IMR_P__APB0___S 14 +#define WMAC0_MCMN_R0_MCMN_IMR_P__RRI___M 0x00002000 +#define WMAC0_MCMN_R0_MCMN_IMR_P__RRI___S 13 +#define WMAC0_MCMN_R0_MCMN_IMR_P__AMPI___M 0x00001000 +#define WMAC0_MCMN_R0_MCMN_IMR_P__AMPI___S 12 +#define WMAC0_MCMN_R0_MCMN_IMR_P__MXI___M 0x00000800 +#define WMAC0_MCMN_R0_MCMN_IMR_P__MXI___S 11 +#define WMAC0_MCMN_R0_MCMN_IMR_P__HWSCH2___M 0x00000400 +#define WMAC0_MCMN_R0_MCMN_IMR_P__HWSCH2___S 10 +#define WMAC0_MCMN_R0_MCMN_IMR_P__HWSCH1___M 0x00000200 +#define WMAC0_MCMN_R0_MCMN_IMR_P__HWSCH1___S 9 +#define WMAC0_MCMN_R0_MCMN_IMR_P__HWSCH0___M 0x00000100 +#define WMAC0_MCMN_R0_MCMN_IMR_P__HWSCH0___S 8 +#define WMAC0_MCMN_R0_MCMN_IMR_P__PDG___M 0x00000080 +#define WMAC0_MCMN_R0_MCMN_IMR_P__PDG___S 7 +#define WMAC0_MCMN_R0_MCMN_IMR_P__RXPCU1___M 0x00000040 +#define WMAC0_MCMN_R0_MCMN_IMR_P__RXPCU1___S 6 +#define WMAC0_MCMN_R0_MCMN_IMR_P__RXPCU0___M 0x00000020 +#define WMAC0_MCMN_R0_MCMN_IMR_P__RXPCU0___S 5 +#define WMAC0_MCMN_R0_MCMN_IMR_P__TXPCU1___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_IMR_P__TXPCU1___S 4 +#define WMAC0_MCMN_R0_MCMN_IMR_P__TXPCU0___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_IMR_P__TXPCU0___S 3 +#define WMAC0_MCMN_R0_MCMN_IMR_P__RXDMA___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_IMR_P__RXDMA___S 2 +#define WMAC0_MCMN_R0_MCMN_IMR_P__TXDMA___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_IMR_P__TXDMA___S 1 +#define WMAC0_MCMN_R0_MCMN_IMR_P__CRYPTO___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_IMR_P__CRYPTO___S 0 +#define WMAC0_MCMN_R0_MCMN_IMR_P___M 0x0777FFFF +#define WMAC0_MCMN_R0_MCMN_IMR_P___S 0 + +#define WMAC0_MCMN_R0_WCSS_CFG_BASE_ADDR (0x00A89208) +#define WMAC0_MCMN_R0_WCSS_CFG_BASE_ADDR___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_WCSS_CFG_BASE_ADDR___POR 0x00000000 +#define WMAC0_MCMN_R0_WCSS_CFG_BASE_ADDR__VAL___POR 0x00 +#define WMAC0_MCMN_R0_WCSS_CFG_BASE_ADDR__VAL___M 0x000000FF +#define WMAC0_MCMN_R0_WCSS_CFG_BASE_ADDR__VAL___S 0 +#define WMAC0_MCMN_R0_WCSS_CFG_BASE_ADDR___M 0x000000FF +#define WMAC0_MCMN_R0_WCSS_CFG_BASE_ADDR___S 0 + +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_L32 (0x00A8920C) +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_L32___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_L32___POR 0x00000000 +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_L32__ADDR_31_0___POR 0x00000000 +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_L32__ADDR_31_0___M 0xFFFFFFFF +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_L32__ADDR_31_0___S 0 +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_L32___M 0xFFFFFFFF +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_L32___S 0 + +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16 (0x00A89210) +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16___POR 0x00000000 +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16__ACKCTS_11AH___POR 0x0 +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16__BASE_RATE_11B___POR 0x0 +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16__ACKCTS_6MB___POR 0x0 +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16__STA_AP___POR 0x0 +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16__ADDR_47_32___POR 0x0000 +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16__ACKCTS_11AH___M 0x00080000 +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16__ACKCTS_11AH___S 19 +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16__BASE_RATE_11B___M 0x00040000 +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16__BASE_RATE_11B___S 18 +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16__ACKCTS_6MB___M 0x00020000 +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16__ACKCTS_6MB___S 17 +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16__STA_AP___M 0x00010000 +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16__STA_AP___S 16 +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16__ADDR_47_32___M 0x0000FFFF +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16__ADDR_47_32___S 0 +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16___M 0x000FFFFF +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_STA_ADDR_U16___S 0 + +#define WMAC0_MCMN_R0_WMAC_RTL_VERSION (0x00A89214) +#define WMAC0_MCMN_R0_WMAC_RTL_VERSION___RWC QCSR_REG_RO +#define WMAC0_MCMN_R0_WMAC_RTL_VERSION___POR 0x00000000 +#define WMAC0_MCMN_R0_WMAC_RTL_VERSION__VAL___POR 0x00000000 +#define WMAC0_MCMN_R0_WMAC_RTL_VERSION__VAL___M 0xFFFFFFFF +#define WMAC0_MCMN_R0_WMAC_RTL_VERSION__VAL___S 0 +#define WMAC0_MCMN_R0_WMAC_RTL_VERSION___M 0xFFFFFFFF +#define WMAC0_MCMN_R0_WMAC_RTL_VERSION___S 0 + +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_L32 (0x00A89218) +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_L32___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_L32___POR 0x00000000 +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_L32__ADDR___POR 0x00000000 +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_L32__ADDR___M 0xFFFFFFFF +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_L32__ADDR___S 0 +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_L32___M 0xFFFFFFFF +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_L32___S 0 + +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_U16 (0x00A8921C) +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_U16___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_U16___POR 0x00000000 +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_U16__TRANSMITTED_BSSID___POR 0x0 +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_U16__AID___POR 0x0000 +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_U16__ADDR___POR 0x0000 +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_U16__TRANSMITTED_BSSID___M 0x40000000 +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_U16__TRANSMITTED_BSSID___S 30 +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_U16__AID___M 0x1FFF0000 +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_U16__AID___S 16 +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_U16__ADDR___M 0x0000FFFF +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_U16__ADDR___S 0 +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_U16___M 0x5FFFFFFF +#define WMAC0_MCMN_R0_WC_SOC_RFF_MAC_PCU_BSSID_U16___S 0 + +#define WMAC0_MCMN_R0_MAC_PCU_AZIMUTH_MODE (0x00A89224) +#define WMAC0_MCMN_R0_MAC_PCU_AZIMUTH_MODE___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MAC_PCU_AZIMUTH_MODE___POR 0x00000002 +#define WMAC0_MCMN_R0_MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE___POR 0x1 +#define WMAC0_MCMN_R0_MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE___POR 0x0 +#define WMAC0_MCMN_R0_MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE___M 0x00000002 +#define WMAC0_MCMN_R0_MAC_PCU_AZIMUTH_MODE__PROXY_STA_FIX1_ENABLE___S 1 +#define WMAC0_MCMN_R0_MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE___M 0x00000001 +#define WMAC0_MCMN_R0_MAC_PCU_AZIMUTH_MODE__DISABLE_TSF_UPDATE___S 0 +#define WMAC0_MCMN_R0_MAC_PCU_AZIMUTH_MODE___M 0x00000003 +#define WMAC0_MCMN_R0_MAC_PCU_AZIMUTH_MODE___S 0 + +#define WMAC0_MCMN_R0_MAC_PCU_WARM_TX_CONTROL (0x00A89230) +#define WMAC0_MCMN_R0_MAC_PCU_WARM_TX_CONTROL___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MAC_PCU_WARM_TX_CONTROL___POR 0x00000280 +#define WMAC0_MCMN_R0_MAC_PCU_WARM_TX_CONTROL__ENABLE_SELF_GEN___POR 0x0 +#define WMAC0_MCMN_R0_MAC_PCU_WARM_TX_CONTROL__ENABLE_DATA___POR 0x0 +#define WMAC0_MCMN_R0_MAC_PCU_WARM_TX_CONTROL__SIFS_DUR___POR 0x0280 +#define WMAC0_MCMN_R0_MAC_PCU_WARM_TX_CONTROL__ENABLE_SELF_GEN___M 0x80000000 +#define WMAC0_MCMN_R0_MAC_PCU_WARM_TX_CONTROL__ENABLE_SELF_GEN___S 31 +#define WMAC0_MCMN_R0_MAC_PCU_WARM_TX_CONTROL__ENABLE_DATA___M 0x40000000 +#define WMAC0_MCMN_R0_MAC_PCU_WARM_TX_CONTROL__ENABLE_DATA___S 30 +#define WMAC0_MCMN_R0_MAC_PCU_WARM_TX_CONTROL__SIFS_DUR___M 0x0000FFFF +#define WMAC0_MCMN_R0_MAC_PCU_WARM_TX_CONTROL__SIFS_DUR___S 0 +#define WMAC0_MCMN_R0_MAC_PCU_WARM_TX_CONTROL___M 0xC000FFFF +#define WMAC0_MCMN_R0_MAC_PCU_WARM_TX_CONTROL___S 0 + +#define WMAC0_MCMN_R0_MCMN_GO_TO_IDLE (0x00A89234) +#define WMAC0_MCMN_R0_MCMN_GO_TO_IDLE___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_GO_TO_IDLE___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__SFM___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__RXOLE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__TXOLE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__AMPI___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__PDG___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__RXPCU___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__TXDMA___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__SFM___M 0x00000040 +#define WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__SFM___S 6 +#define WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__RXOLE___M 0x00000020 +#define WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__RXOLE___S 5 +#define WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__TXOLE___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__TXOLE___S 4 +#define WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__AMPI___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__AMPI___S 3 +#define WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__PDG___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__PDG___S 2 +#define WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__RXPCU___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__RXPCU___S 1 +#define WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__TXDMA___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_GO_TO_IDLE__TXDMA___S 0 +#define WMAC0_MCMN_R0_MCMN_GO_TO_IDLE___M 0x0000007F +#define WMAC0_MCMN_R0_MCMN_GO_TO_IDLE___S 0 + +#define WMAC0_MCMN_R0_WMAC_IDLE_LENGTH (0x00A89238) +#define WMAC0_MCMN_R0_WMAC_IDLE_LENGTH___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_WMAC_IDLE_LENGTH___POR 0x0000000A +#define WMAC0_MCMN_R0_WMAC_IDLE_LENGTH__VALUE___POR 0x0A +#define WMAC0_MCMN_R0_WMAC_IDLE_LENGTH__VALUE___M 0x0000003F +#define WMAC0_MCMN_R0_WMAC_IDLE_LENGTH__VALUE___S 0 +#define WMAC0_MCMN_R0_WMAC_IDLE_LENGTH___M 0x0000003F +#define WMAC0_MCMN_R0_WMAC_IDLE_LENGTH___S 0 + +#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK (0x00A89240) +#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK__RXDMA_SRNG_SW_INT___POR 0x000 +#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK__RXDMA_PPDU___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK__RXDMA_MPDU___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK__RXDMA_MSDU___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK__RXDMA_SRNG_SW_INT___M 0x00001FF8 +#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK__RXDMA_SRNG_SW_INT___S 3 +#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK__RXDMA_PPDU___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK__RXDMA_PPDU___S 2 +#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK__RXDMA_MPDU___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK__RXDMA_MPDU___S 1 +#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK__RXDMA_MSDU___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK__RXDMA_MSDU___S 0 +#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK___M 0x00001FFF +#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK___S 0 + +#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK1 (0x00A89244) +#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK1___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK1___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK1__RXDMA_SRNG_SW_INT___POR 0x000 +#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK1__RXDMA_PPDU___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK1__RXDMA_MPDU___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK1__RXDMA_MSDU___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK1__RXDMA_SRNG_SW_INT___M 0x00001FF8 +#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK1__RXDMA_SRNG_SW_INT___S 3 +#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK1__RXDMA_PPDU___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK1__RXDMA_PPDU___S 2 +#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK1__RXDMA_MPDU___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK1__RXDMA_MPDU___S 1 +#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK1__RXDMA_MSDU___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK1__RXDMA_MSDU___S 0 +#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK1___M 0x00001FFF +#define WMAC0_MCMN_R0_MCMN_ISR_RX_OK1___S 0 + +#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK (0x00A89248) +#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK__RXDMA_SRNG_SW_INT___POR 0x000 +#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK__RXDMA_PPDU___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK__RXDMA_MPDU___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK__RXDMA_MSDU___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK__RXDMA_SRNG_SW_INT___M 0x00001FF8 +#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK__RXDMA_SRNG_SW_INT___S 3 +#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK__RXDMA_PPDU___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK__RXDMA_PPDU___S 2 +#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK__RXDMA_MPDU___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK__RXDMA_MPDU___S 1 +#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK__RXDMA_MSDU___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK__RXDMA_MSDU___S 0 +#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK___M 0x00001FFF +#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK___S 0 + +#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK1 (0x00A8924C) +#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK1___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK1___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK1__RXDMA_SRNG_SW_INT___POR 0x000 +#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK1__RXDMA_PPDU___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK1__RXDMA_MPDU___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK1__RXDMA_MSDU___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK1__RXDMA_SRNG_SW_INT___M 0x00001FF8 +#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK1__RXDMA_SRNG_SW_INT___S 3 +#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK1__RXDMA_PPDU___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK1__RXDMA_PPDU___S 2 +#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK1__RXDMA_MPDU___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK1__RXDMA_MPDU___S 1 +#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK1__RXDMA_MSDU___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK1__RXDMA_MSDU___S 0 +#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK1___M 0x00001FFF +#define WMAC0_MCMN_R0_MCMN_IMR_RX_OK1___S 0 + +#define WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP (0x00A89250) +#define WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP__QBOOST_QOSDATA_SIFS_RESP___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP__QBOOST_BAR_SIFS_RESP___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP__QBOOST_EXPLICIT_SIFS_RESP___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP__UAPSD_SIFS_RESP___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP__PS_POLL_SIFS_RESP___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP__QBOOST_QOSDATA_SIFS_RESP___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP__QBOOST_QOSDATA_SIFS_RESP___S 4 +#define WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP__QBOOST_BAR_SIFS_RESP___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP__QBOOST_BAR_SIFS_RESP___S 3 +#define WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP__QBOOST_EXPLICIT_SIFS_RESP___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP__QBOOST_EXPLICIT_SIFS_RESP___S 2 +#define WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP__UAPSD_SIFS_RESP___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP__UAPSD_SIFS_RESP___S 1 +#define WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP__PS_POLL_SIFS_RESP___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP__PS_POLL_SIFS_RESP___S 0 +#define WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP___M 0x0000001F +#define WMAC0_MCMN_R0_MCMN_ISR_SIFS_RESP___S 0 + +#define WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP (0x00A89254) +#define WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP__QBOOST_QOSDATA_SIFS_RESP___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP__QBOOST_BAR_SIFS_RESP___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP__QBOOST_EXPLICIT_SIFS_RESP___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP__UAPSD_SIFS_RESP___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP__PS_POLL_SIFS_RESP___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP__QBOOST_QOSDATA_SIFS_RESP___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP__QBOOST_QOSDATA_SIFS_RESP___S 4 +#define WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP__QBOOST_BAR_SIFS_RESP___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP__QBOOST_BAR_SIFS_RESP___S 3 +#define WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP__QBOOST_EXPLICIT_SIFS_RESP___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP__QBOOST_EXPLICIT_SIFS_RESP___S 2 +#define WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP__UAPSD_SIFS_RESP___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP__UAPSD_SIFS_RESP___S 1 +#define WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP__PS_POLL_SIFS_RESP___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP__PS_POLL_SIFS_RESP___S 0 +#define WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP___M 0x0000001F +#define WMAC0_MCMN_R0_MCMN_IMR_SIFS_RESP___S 0 + +#define WMAC0_MCMN_R0_MCMN_ISR_TX_OK (0x00A89258) +#define WMAC0_MCMN_R0_MCMN_ISR_TX_OK___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_ISR_TX_OK___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_ISR_TX_OK__HWSCH_TX_FES_STATUS_UPDATE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_TX_OK__HWSCH_SCHEDULER_TX_STATUS_UPDATE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_ISR_TX_OK__HWSCH_TX_FES_STATUS_UPDATE___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_ISR_TX_OK__HWSCH_TX_FES_STATUS_UPDATE___S 1 +#define WMAC0_MCMN_R0_MCMN_ISR_TX_OK__HWSCH_SCHEDULER_TX_STATUS_UPDATE___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_ISR_TX_OK__HWSCH_SCHEDULER_TX_STATUS_UPDATE___S 0 +#define WMAC0_MCMN_R0_MCMN_ISR_TX_OK___M 0x00000003 +#define WMAC0_MCMN_R0_MCMN_ISR_TX_OK___S 0 + +#define WMAC0_MCMN_R0_MCMN_IMR_TX_OK (0x00A8925C) +#define WMAC0_MCMN_R0_MCMN_IMR_TX_OK___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_IMR_TX_OK___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_IMR_TX_OK__HWSCH_TX_FES_STATUS_UPDATE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_TX_OK__HWSCH_SCHEDULER_TX_STATUS_UPDATE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_IMR_TX_OK__HWSCH_TX_FES_STATUS_UPDATE___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_IMR_TX_OK__HWSCH_TX_FES_STATUS_UPDATE___S 1 +#define WMAC0_MCMN_R0_MCMN_IMR_TX_OK__HWSCH_SCHEDULER_TX_STATUS_UPDATE___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_IMR_TX_OK__HWSCH_SCHEDULER_TX_STATUS_UPDATE___S 0 +#define WMAC0_MCMN_R0_MCMN_IMR_TX_OK___M 0x00000003 +#define WMAC0_MCMN_R0_MCMN_IMR_TX_OK___S 0 + +#define WMAC0_MCMN_R0_MCMN_WOCLR_ISR_P_EN (0x00A89260) +#define WMAC0_MCMN_R0_MCMN_WOCLR_ISR_P_EN___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_WOCLR_ISR_P_EN___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_WOCLR_ISR_P_EN__VAL___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_WOCLR_ISR_P_EN__VAL___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_WOCLR_ISR_P_EN__VAL___S 0 +#define WMAC0_MCMN_R0_MCMN_WOCLR_ISR_P_EN___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_WOCLR_ISR_P_EN___S 0 + +#define WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL (0x00A89264) +#define WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL___POR 0x00000000 +#define WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL__WRAP_CNT_EN___POR 0x0 +#define WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL__PCI_MIB_FORCE___POR 0x0 +#define WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL__PCI_MIB_CLEAR___POR 0x0 +#define WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL__PCI_MIB_FREEZE___POR 0x0 +#define WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL__WMAC_RX_ABORT___POR 0x0 +#define WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL__WRAP_CNT_EN___M 0x00000010 +#define WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL__WRAP_CNT_EN___S 4 +#define WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL__PCI_MIB_FORCE___M 0x00000008 +#define WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL__PCI_MIB_FORCE___S 3 +#define WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL__PCI_MIB_CLEAR___M 0x00000004 +#define WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL__PCI_MIB_CLEAR___S 2 +#define WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL__PCI_MIB_FREEZE___M 0x00000002 +#define WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL__PCI_MIB_FREEZE___S 1 +#define WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL__WMAC_RX_ABORT___M 0x00000001 +#define WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL__WMAC_RX_ABORT___S 0 +#define WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL___M 0x0000001F +#define WMAC0_MCMN_R0_MAC_PCU_MIB_CNT_CTRL___S 0 + +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN (0x00A89268) +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN___POR 0x0002FFFF +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__LPEC___POR 0x1 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__SFM___POR 0x1 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__APB_IF___POR 0x1 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__MAPB_MAC___POR 0x1 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__AMPI_PHY___POR 0x1 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__RXOLE___POR 0x1 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__TXOLE___POR 0x1 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__RRI___POR 0x1 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__CRYPTO___POR 0x1 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__HWSCH___POR 0x1 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__MXI___POR 0x1 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__PDG___POR 0x1 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__RXDMA___POR 0x1 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__RXPCU___POR 0x1 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__TXDMA___POR 0x1 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__TXPCU___POR 0x1 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__AMPI_MAC___POR 0x1 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__LPEC___M 0x00020000 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__LPEC___S 17 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__SFM___M 0x00008000 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__SFM___S 15 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__APB_IF___M 0x00004000 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__APB_IF___S 14 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__MAPB_MAC___M 0x00002000 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__MAPB_MAC___S 13 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__AMPI_PHY___M 0x00001000 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__AMPI_PHY___S 12 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__RXOLE___M 0x00000800 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__RXOLE___S 11 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__TXOLE___M 0x00000400 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__TXOLE___S 10 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__RRI___M 0x00000200 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__RRI___S 9 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__CRYPTO___M 0x00000100 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__CRYPTO___S 8 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__HWSCH___M 0x00000080 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__HWSCH___S 7 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__MXI___M 0x00000040 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__MXI___S 6 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__PDG___M 0x00000020 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__PDG___S 5 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__RXDMA___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__RXDMA___S 4 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__RXPCU___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__RXPCU___S 3 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__TXDMA___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__TXDMA___S 2 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__TXPCU___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__TXPCU___S 1 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__AMPI_MAC___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN__AMPI_MAC___S 0 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN___M 0x0002FFFF +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKEN___S 0 + +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS (0x00A8926C) +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS___POR 0x000088C8 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__LPEC___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__SFM___POR 0x1 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__APB_IF___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__MAPB_MAC___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__AMPI_PHY___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__RXOLE___POR 0x1 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__TXOLE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__RRI___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__CRYPTO___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__HWSCH___POR 0x1 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__MXI___POR 0x1 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__PDG___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__RXDMA___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__RXPCU___POR 0x1 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__TXDMA___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__TXPCU___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__AMPI_MAC___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__LPEC___M 0x00020000 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__LPEC___S 17 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__SFM___M 0x00008000 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__SFM___S 15 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__APB_IF___M 0x00004000 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__APB_IF___S 14 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__MAPB_MAC___M 0x00002000 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__MAPB_MAC___S 13 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__AMPI_PHY___M 0x00001000 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__AMPI_PHY___S 12 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__RXOLE___M 0x00000800 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__RXOLE___S 11 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__TXOLE___M 0x00000400 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__TXOLE___S 10 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__RRI___M 0x00000200 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__RRI___S 9 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__CRYPTO___M 0x00000100 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__CRYPTO___S 8 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__HWSCH___M 0x00000080 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__HWSCH___S 7 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__MXI___M 0x00000040 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__MXI___S 6 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__PDG___M 0x00000020 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__PDG___S 5 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__RXDMA___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__RXDMA___S 4 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__RXPCU___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__RXPCU___S 3 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__TXDMA___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__TXDMA___S 2 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__TXPCU___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__TXPCU___S 1 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__AMPI_MAC___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS__AMPI_MAC___S 0 +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS___M 0x0002FFFF +#define WMAC0_MCMN_R0_MCMN_MRCM_ROOT_CLKGATE_DIS___S 0 + +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET (0x00A89270) +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__LPEC___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__SFM___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__MAPB_AHB___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__APB_IF___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__MAPB_MAC___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__AMPI_PHY___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__RXOLE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__TXOLE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__RRI___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__CRYPTO___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__HWSCH___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__MXI___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__PDG___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__RXDMA___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__RXPCU___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__TXDMA___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__TXPCU___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__AMPI_MAC___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__LPEC___M 0x00040000 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__LPEC___S 18 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__SFM___M 0x00010000 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__SFM___S 16 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__MAPB_AHB___M 0x00008000 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__MAPB_AHB___S 15 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__APB_IF___M 0x00004000 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__APB_IF___S 14 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__MAPB_MAC___M 0x00002000 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__MAPB_MAC___S 13 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__AMPI_PHY___M 0x00001000 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__AMPI_PHY___S 12 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__RXOLE___M 0x00000800 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__RXOLE___S 11 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__TXOLE___M 0x00000400 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__TXOLE___S 10 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__RRI___M 0x00000200 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__RRI___S 9 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__CRYPTO___M 0x00000100 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__CRYPTO___S 8 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__HWSCH___M 0x00000080 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__HWSCH___S 7 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__MXI___M 0x00000040 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__MXI___S 6 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__PDG___M 0x00000020 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__PDG___S 5 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__RXDMA___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__RXDMA___S 4 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__RXPCU___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__RXPCU___S 3 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__TXDMA___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__TXDMA___S 2 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__TXPCU___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__TXPCU___S 1 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__AMPI_MAC___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET__AMPI_MAC___S 0 +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET___M 0x0005FFFF +#define WMAC0_MCMN_R0_MCMN_MRCM_SOFTRESET___S 0 + +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET (0x00A89274) +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__LPEC___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__SFM___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__APB_IF___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__MAPB_MAC___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__AMPI_PHY___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__RXOLE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__TXOLE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__RRI___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__CRYPTO___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__HWSCH___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__MXI___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__PDG___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__RXDMA___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__RXPCU___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__TXDMA___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__TXPCU___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__AMPI_MAC___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__LPEC___M 0x00020000 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__LPEC___S 17 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__SFM___M 0x00008000 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__SFM___S 15 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__APB_IF___M 0x00004000 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__APB_IF___S 14 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__MAPB_MAC___M 0x00002000 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__MAPB_MAC___S 13 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__AMPI_PHY___M 0x00001000 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__AMPI_PHY___S 12 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__RXOLE___M 0x00000800 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__RXOLE___S 11 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__TXOLE___M 0x00000400 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__TXOLE___S 10 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__RRI___M 0x00000200 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__RRI___S 9 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__CRYPTO___M 0x00000100 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__CRYPTO___S 8 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__HWSCH___M 0x00000080 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__HWSCH___S 7 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__MXI___M 0x00000040 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__MXI___S 6 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__PDG___M 0x00000020 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__PDG___S 5 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__RXDMA___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__RXDMA___S 4 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__RXPCU___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__RXPCU___S 3 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__TXDMA___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__TXDMA___S 2 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__TXPCU___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__TXPCU___S 1 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__AMPI_MAC___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET__AMPI_MAC___S 0 +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET___M 0x0002FFFF +#define WMAC0_MCMN_R0_MCMN_MRCM_CONFIGRESET___S 0 + +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE (0x00A89278) +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__LPEC___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__SFM___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__RXOLE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__TXOLE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__RRI___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__CRYPTO___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__HWSCH___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__MXI___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__PDG___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__RXDMA___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__RXPCU___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__TXDMA___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__TXPCU___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__AMPI___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__LPEC___M 0x00004000 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__LPEC___S 14 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__SFM___M 0x00001000 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__SFM___S 12 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__RXOLE___M 0x00000800 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__RXOLE___S 11 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__TXOLE___M 0x00000400 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__TXOLE___S 10 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__RRI___M 0x00000200 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__RRI___S 9 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__CRYPTO___M 0x00000100 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__CRYPTO___S 8 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__HWSCH___M 0x00000080 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__HWSCH___S 7 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__MXI___M 0x00000040 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__MXI___S 6 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__PDG___M 0x00000020 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__PDG___S 5 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__RXDMA___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__RXDMA___S 4 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__RXPCU___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__RXPCU___S 3 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__TXDMA___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__TXDMA___S 2 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__TXPCU___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__TXPCU___S 1 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__AMPI___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE__AMPI___S 0 +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE___M 0x00005FFF +#define WMAC0_MCMN_R0_MCMN_APB_CLKGATE_DISABLE___S 0 + +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE (0x00A8927C) +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__CLK_ENS_EXTEND___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__DEBUG_BUS___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__VAL___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_P___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S26___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S25___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S24___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_TX_OK___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S22___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S21___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S20___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_SIFS_RESP___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S18___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S17___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S16___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S15___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S14___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S13___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S12___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S11___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S10___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S9___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S8___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S7___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S6___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S5___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S4___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S3___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S2___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S1___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S0___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__CLK_ENS_EXTEND___M 0x80000000 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__CLK_ENS_EXTEND___S 31 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__DEBUG_BUS___M 0x40000000 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__DEBUG_BUS___S 30 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__VAL___M 0x30000000 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__VAL___S 28 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_P___M 0x08000000 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_P___S 27 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S26___M 0x04000000 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S26___S 26 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S25___M 0x02000000 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S25___S 25 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S24___M 0x01000000 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S24___S 24 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_TX_OK___M 0x00800000 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_TX_OK___S 23 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S22___M 0x00400000 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S22___S 22 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S21___M 0x00200000 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S21___S 21 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S20___M 0x00100000 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S20___S 20 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_SIFS_RESP___M 0x00080000 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_SIFS_RESP___S 19 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S18___M 0x00040000 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S18___S 18 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S17___M 0x00020000 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S17___S 17 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S16___M 0x00010000 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S16___S 16 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S15___M 0x00008000 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S15___S 15 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S14___M 0x00004000 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S14___S 14 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S13___M 0x00002000 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S13___S 13 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S12___M 0x00001000 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S12___S 12 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S11___M 0x00000800 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S11___S 11 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S10___M 0x00000400 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S10___S 10 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S9___M 0x00000200 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S9___S 9 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S8___M 0x00000100 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S8___S 8 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S7___M 0x00000080 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S7___S 7 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S6___M 0x00000040 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S6___S 6 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S5___M 0x00000020 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S5___S 5 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S4___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S4___S 4 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S3___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S3___S 3 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S2___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S2___S 2 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S1___M 0x00000002 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S1___S 1 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S0___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE__ISR_S0___S 0 +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE___M 0xFFFFFFFF +#define WMAC0_MCMN_R0_MCMN_CLK_GATE_DISABLE___S 0 + +#define WMAC0_MCMN_R0_WMAC_REVISION (0x00A89280) +#define WMAC0_MCMN_R0_WMAC_REVISION___RWC QCSR_REG_RO +#define WMAC0_MCMN_R0_WMAC_REVISION___POR 0x10080000 +#define WMAC0_MCMN_R0_WMAC_REVISION__MAJOR___POR 0x1 +#define WMAC0_MCMN_R0_WMAC_REVISION__MINOR___POR 0x008 +#define WMAC0_MCMN_R0_WMAC_REVISION__STEP___POR 0x0000 +#define WMAC0_MCMN_R0_WMAC_REVISION__MAJOR___M 0xF0000000 +#define WMAC0_MCMN_R0_WMAC_REVISION__MAJOR___S 28 +#define WMAC0_MCMN_R0_WMAC_REVISION__MINOR___M 0x0FFF0000 +#define WMAC0_MCMN_R0_WMAC_REVISION__MINOR___S 16 +#define WMAC0_MCMN_R0_WMAC_REVISION__STEP___M 0x0000FFFF +#define WMAC0_MCMN_R0_WMAC_REVISION__STEP___S 0 +#define WMAC0_MCMN_R0_WMAC_REVISION___M 0xFFFFFFFF +#define WMAC0_MCMN_R0_WMAC_REVISION___S 0 + +#define WMAC0_MCMN_R0_MCMN_INVALID_APB (0x00A89284) +#define WMAC0_MCMN_R0_MCMN_INVALID_APB___RWC QCSR_REG_RO +#define WMAC0_MCMN_R0_MCMN_INVALID_APB___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_INVALID_APB__ACC_ADR___POR 0x00000 +#define WMAC0_MCMN_R0_MCMN_INVALID_APB__ACC_ADR___M 0x0001FFFF +#define WMAC0_MCMN_R0_MCMN_INVALID_APB__ACC_ADR___S 0 +#define WMAC0_MCMN_R0_MCMN_INVALID_APB___M 0x0001FFFF +#define WMAC0_MCMN_R0_MCMN_INVALID_APB___S 0 + +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE (0x00A89288) +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE___RWC QCSR_REG_RO +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__RX___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__TX___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__RXPCU_IDLE_RESP___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__HWSCH_IDLE_RESP___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__MAPB___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__RXDMA_DTIM___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__SFM_FSM___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__SFM___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__MXI___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__RRI___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__AMPI_RX___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__AMPI_TX___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__CRYPTO_RX___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__CRYPTO_TX___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__RXPCU___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__TXPCU___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__RXOLE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__TXOLE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__RXDMA___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__TXDMA___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__PDG___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__HWSCH___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__MAC___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__RX___M 0x01000000 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__RX___S 24 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__TX___M 0x00800000 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__TX___S 23 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__RXPCU_IDLE_RESP___M 0x00400000 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__RXPCU_IDLE_RESP___S 22 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__HWSCH_IDLE_RESP___M 0x00200000 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__HWSCH_IDLE_RESP___S 21 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__MAPB___M 0x00100000 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__MAPB___S 20 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__RXDMA_DTIM___M 0x00080000 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__RXDMA_DTIM___S 19 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__SFM_FSM___M 0x00040000 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__SFM_FSM___S 18 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__SFM___M 0x00010000 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__SFM___S 16 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__MXI___M 0x00008000 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__MXI___S 15 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__RRI___M 0x00004000 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__RRI___S 14 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__AMPI_RX___M 0x00002000 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__AMPI_RX___S 13 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__AMPI_TX___M 0x00001000 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__AMPI_TX___S 12 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__CRYPTO_RX___M 0x00000800 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__CRYPTO_RX___S 11 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__CRYPTO_TX___M 0x00000400 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__CRYPTO_TX___S 10 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__RXPCU___M 0x00000200 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__RXPCU___S 9 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__TXPCU___M 0x00000100 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__TXPCU___S 8 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__RXOLE___M 0x00000080 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__RXOLE___S 7 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__TXOLE___M 0x00000040 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__TXOLE___S 6 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__RXDMA___M 0x00000020 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__RXDMA___S 5 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__TXDMA___M 0x00000010 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__TXDMA___S 4 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__PDG___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__PDG___S 3 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__HWSCH___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__HWSCH___S 2 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__MAC___M 0x00000001 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE__MAC___S 0 +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE___M 0x01FDFFFD +#define WMAC0_MCMN_R0_MCMN_MAC_IDLE___S 0 + +#define WMAC0_MCMN_R0_MCMN_CONFIG (0x00A8928C) +#define WMAC0_MCMN_R0_MCMN_CONFIG___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_MCMN_CONFIG___POR 0x00000000 +#define WMAC0_MCMN_R0_MCMN_CONFIG__FIPS_MODE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_CONFIG__RX_FILTER_PROMISCUOUS___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_CONFIG__MAC_MODE___POR 0x0 +#define WMAC0_MCMN_R0_MCMN_CONFIG__FIPS_MODE___M 0x00000008 +#define WMAC0_MCMN_R0_MCMN_CONFIG__FIPS_MODE___S 3 +#define WMAC0_MCMN_R0_MCMN_CONFIG__RX_FILTER_PROMISCUOUS___M 0x00000004 +#define WMAC0_MCMN_R0_MCMN_CONFIG__RX_FILTER_PROMISCUOUS___S 2 +#define WMAC0_MCMN_R0_MCMN_CONFIG__MAC_MODE___M 0x00000003 +#define WMAC0_MCMN_R0_MCMN_CONFIG__MAC_MODE___S 0 +#define WMAC0_MCMN_R0_MCMN_CONFIG___M 0x0000000F +#define WMAC0_MCMN_R0_MCMN_CONFIG___S 0 + +#define WMAC0_MCMN_R0_IDLE_CTRL0 (0x00A89290) +#define WMAC0_MCMN_R0_IDLE_CTRL0___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_IDLE_CTRL0___POR 0x00007810 +#define WMAC0_MCMN_R0_IDLE_CTRL0__IDLE_INTG_CHK_DLY___POR 0x00F +#define WMAC0_MCMN_R0_IDLE_CTRL0__IDLE_CHK_DLY___POR 0x008 +#define WMAC0_MCMN_R0_IDLE_CTRL0__SW_IDLE_REQ___POR 0x0 +#define WMAC0_MCMN_R0_IDLE_CTRL0__IDLE_INTG_CHK_DLY___M 0x001FF800 +#define WMAC0_MCMN_R0_IDLE_CTRL0__IDLE_INTG_CHK_DLY___S 11 +#define WMAC0_MCMN_R0_IDLE_CTRL0__IDLE_CHK_DLY___M 0x000007FE +#define WMAC0_MCMN_R0_IDLE_CTRL0__IDLE_CHK_DLY___S 1 +#define WMAC0_MCMN_R0_IDLE_CTRL0__SW_IDLE_REQ___M 0x00000001 +#define WMAC0_MCMN_R0_IDLE_CTRL0__SW_IDLE_REQ___S 0 +#define WMAC0_MCMN_R0_IDLE_CTRL0___M 0x001FFFFF +#define WMAC0_MCMN_R0_IDLE_CTRL0___S 0 + +#define WMAC0_MCMN_R0_IDLE_CTRL1 (0x00A89294) +#define WMAC0_MCMN_R0_IDLE_CTRL1___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_IDLE_CTRL1___POR 0x7FFFFBFF +#define WMAC0_MCMN_R0_IDLE_CTRL1__MAIN_SM_IDLE_WAIT_TO_DLY___POR 0x3FF +#define WMAC0_MCMN_R0_IDLE_CTRL1__RX_SM_MOD_IDLE_WAIT_TO_DLY___POR 0x3FF +#define WMAC0_MCMN_R0_IDLE_CTRL1__TX_FLUSH_ON_MOD_IDLE_TO___POR 0x0 +#define WMAC0_MCMN_R0_IDLE_CTRL1__TX_SM_MOD_IDLE_WAIT_TO_DLY___POR 0x3FF +#define WMAC0_MCMN_R0_IDLE_CTRL1__MAIN_SM_IDLE_WAIT_TO_DLY___M 0x7FE00000 +#define WMAC0_MCMN_R0_IDLE_CTRL1__MAIN_SM_IDLE_WAIT_TO_DLY___S 21 +#define WMAC0_MCMN_R0_IDLE_CTRL1__RX_SM_MOD_IDLE_WAIT_TO_DLY___M 0x001FF800 +#define WMAC0_MCMN_R0_IDLE_CTRL1__RX_SM_MOD_IDLE_WAIT_TO_DLY___S 11 +#define WMAC0_MCMN_R0_IDLE_CTRL1__TX_FLUSH_ON_MOD_IDLE_TO___M 0x00000400 +#define WMAC0_MCMN_R0_IDLE_CTRL1__TX_FLUSH_ON_MOD_IDLE_TO___S 10 +#define WMAC0_MCMN_R0_IDLE_CTRL1__TX_SM_MOD_IDLE_WAIT_TO_DLY___M 0x000003FF +#define WMAC0_MCMN_R0_IDLE_CTRL1__TX_SM_MOD_IDLE_WAIT_TO_DLY___S 0 +#define WMAC0_MCMN_R0_IDLE_CTRL1___M 0x7FFFFFFF +#define WMAC0_MCMN_R0_IDLE_CTRL1___S 0 + +#define WMAC0_MCMN_R0_IDLE_CTRL2 (0x00A89298) +#define WMAC0_MCMN_R0_IDLE_CTRL2___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_IDLE_CTRL2___POR 0x00000000 +#define WMAC0_MCMN_R0_IDLE_CTRL2__RX_FLUSH_ON_MOD_IDLE_TO___POR 0x0 +#define WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_TXPCU_NOT_IDLE___POR 0x0 +#define WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_CRYPTO_NOT_IDLE___POR 0x0 +#define WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_TXOLE_NOT_IDLE___POR 0x0 +#define WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_TXDMA_NOT_IDLE___POR 0x0 +#define WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_PDG_NOT_IDLE___POR 0x0 +#define WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_HWSCH_NOT_IDLE___POR 0x0 +#define WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_RX_IF_RXDMA_NOT_IDLE___POR 0x0 +#define WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_RX_IF_CRYPTO_NOT_IDLE___POR 0x0 +#define WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_RX_IF_RXPCU_NOT_IDLE___POR 0x0 +#define WMAC0_MCMN_R0_IDLE_CTRL2__RX_FLUSH_ON_MOD_IDLE_TO___M 0x00000200 +#define WMAC0_MCMN_R0_IDLE_CTRL2__RX_FLUSH_ON_MOD_IDLE_TO___S 9 +#define WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_TXPCU_NOT_IDLE___M 0x00000100 +#define WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_TXPCU_NOT_IDLE___S 8 +#define WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_CRYPTO_NOT_IDLE___M 0x00000080 +#define WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_CRYPTO_NOT_IDLE___S 7 +#define WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_TXOLE_NOT_IDLE___M 0x00000040 +#define WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_TXOLE_NOT_IDLE___S 6 +#define WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_TXDMA_NOT_IDLE___M 0x00000020 +#define WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_TXDMA_NOT_IDLE___S 5 +#define WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_PDG_NOT_IDLE___M 0x00000010 +#define WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_PDG_NOT_IDLE___S 4 +#define WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_HWSCH_NOT_IDLE___M 0x00000008 +#define WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_TX_IF_HWSCH_NOT_IDLE___S 3 +#define WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_RX_IF_RXDMA_NOT_IDLE___M 0x00000004 +#define WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_RX_IF_RXDMA_NOT_IDLE___S 2 +#define WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_RX_IF_CRYPTO_NOT_IDLE___M 0x00000002 +#define WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_RX_IF_CRYPTO_NOT_IDLE___S 1 +#define WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_RX_IF_RXPCU_NOT_IDLE___M 0x00000001 +#define WMAC0_MCMN_R0_IDLE_CTRL2__FLUSH_RX_IF_RXPCU_NOT_IDLE___S 0 +#define WMAC0_MCMN_R0_IDLE_CTRL2___M 0x000003FF +#define WMAC0_MCMN_R0_IDLE_CTRL2___S 0 + +#define WMAC0_MCMN_R0_IDLE_CTRL3 (0x00A8929C) +#define WMAC0_MCMN_R0_IDLE_CTRL3___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_IDLE_CTRL3___POR 0x0003FCFF +#define WMAC0_MCMN_R0_IDLE_CTRL3__RX_FLUSH_WAIT_DLY___POR 0x0FF +#define WMAC0_MCMN_R0_IDLE_CTRL3__TX_FLUSH_WAIT_DLY___POR 0x0FF +#define WMAC0_MCMN_R0_IDLE_CTRL3__RX_FLUSH_WAIT_DLY___M 0x000FFC00 +#define WMAC0_MCMN_R0_IDLE_CTRL3__RX_FLUSH_WAIT_DLY___S 10 +#define WMAC0_MCMN_R0_IDLE_CTRL3__TX_FLUSH_WAIT_DLY___M 0x000003FF +#define WMAC0_MCMN_R0_IDLE_CTRL3__TX_FLUSH_WAIT_DLY___S 0 +#define WMAC0_MCMN_R0_IDLE_CTRL3___M 0x000FFFFF +#define WMAC0_MCMN_R0_IDLE_CTRL3___S 0 + +#define WMAC0_MCMN_R0_IDLE_CTRL4 (0x00A892A0) +#define WMAC0_MCMN_R0_IDLE_CTRL4___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_IDLE_CTRL4___POR 0x0003FCFF +#define WMAC0_MCMN_R0_IDLE_CTRL4__TX_FLUSH_ACK_TO_DLY___POR 0x0FF +#define WMAC0_MCMN_R0_IDLE_CTRL4__RX_FLUSH_ACK_TO_DLY___POR 0x0FF +#define WMAC0_MCMN_R0_IDLE_CTRL4__TX_FLUSH_ACK_TO_DLY___M 0x000FFC00 +#define WMAC0_MCMN_R0_IDLE_CTRL4__TX_FLUSH_ACK_TO_DLY___S 10 +#define WMAC0_MCMN_R0_IDLE_CTRL4__RX_FLUSH_ACK_TO_DLY___M 0x000003FF +#define WMAC0_MCMN_R0_IDLE_CTRL4__RX_FLUSH_ACK_TO_DLY___S 0 +#define WMAC0_MCMN_R0_IDLE_CTRL4___M 0x000FFFFF +#define WMAC0_MCMN_R0_IDLE_CTRL4___S 0 + +#define WMAC0_MCMN_R0_IDLE_CTRL5 (0x00A892A4) +#define WMAC0_MCMN_R0_IDLE_CTRL5___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_IDLE_CTRL5___POR 0x00000000 +#define WMAC0_MCMN_R0_IDLE_CTRL5__USE_RXDMA_PARTIAL_IDLE___POR 0x0 +#define WMAC0_MCMN_R0_IDLE_CTRL5__USE_SFM_PARTIAL_IDLE___POR 0x0 +#define WMAC0_MCMN_R0_IDLE_CTRL5__IGNORE_HWSCH_CMD_RING_NOT_EMPTY___POR 0x0 +#define WMAC0_MCMN_R0_IDLE_CTRL5__USE_RXDMA_PARTIAL_IDLE___M 0x00000004 +#define WMAC0_MCMN_R0_IDLE_CTRL5__USE_RXDMA_PARTIAL_IDLE___S 2 +#define WMAC0_MCMN_R0_IDLE_CTRL5__USE_SFM_PARTIAL_IDLE___M 0x00000002 +#define WMAC0_MCMN_R0_IDLE_CTRL5__USE_SFM_PARTIAL_IDLE___S 1 +#define WMAC0_MCMN_R0_IDLE_CTRL5__IGNORE_HWSCH_CMD_RING_NOT_EMPTY___M 0x00000001 +#define WMAC0_MCMN_R0_IDLE_CTRL5__IGNORE_HWSCH_CMD_RING_NOT_EMPTY___S 0 +#define WMAC0_MCMN_R0_IDLE_CTRL5___M 0x00000007 +#define WMAC0_MCMN_R0_IDLE_CTRL5___S 0 + +#define WMAC0_MCMN_R0_S_PARE0 (0x00A892A8) +#define WMAC0_MCMN_R0_S_PARE0___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_S_PARE0___POR 0x00000000 +#define WMAC0_MCMN_R0_S_PARE0__VAL___POR 0x00000000 +#define WMAC0_MCMN_R0_S_PARE0__VAL___M 0xFFFFFFFF +#define WMAC0_MCMN_R0_S_PARE0__VAL___S 0 +#define WMAC0_MCMN_R0_S_PARE0___M 0xFFFFFFFF +#define WMAC0_MCMN_R0_S_PARE0___S 0 + +#define WMAC0_MCMN_R0_S_PARE1 (0x00A892AC) +#define WMAC0_MCMN_R0_S_PARE1___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_S_PARE1___POR 0x00000000 +#define WMAC0_MCMN_R0_S_PARE1__VAL___POR 0x00000000 +#define WMAC0_MCMN_R0_S_PARE1__VAL___M 0xFFFFFFFF +#define WMAC0_MCMN_R0_S_PARE1__VAL___S 0 +#define WMAC0_MCMN_R0_S_PARE1___M 0xFFFFFFFF +#define WMAC0_MCMN_R0_S_PARE1___S 0 + +#define WMAC0_MCMN_R0_S_PARE2 (0x00A892B0) +#define WMAC0_MCMN_R0_S_PARE2___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_S_PARE2___POR 0x00000000 +#define WMAC0_MCMN_R0_S_PARE2__VAL___POR 0x00000000 +#define WMAC0_MCMN_R0_S_PARE2__VAL___M 0xFFFFFFFF +#define WMAC0_MCMN_R0_S_PARE2__VAL___S 0 +#define WMAC0_MCMN_R0_S_PARE2___M 0xFFFFFFFF +#define WMAC0_MCMN_R0_S_PARE2___S 0 + +#define WMAC0_MCMN_R0_S_PARE3 (0x00A892B4) +#define WMAC0_MCMN_R0_S_PARE3___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_S_PARE3___POR 0x00000000 +#define WMAC0_MCMN_R0_S_PARE3__VAL___POR 0x00000000 +#define WMAC0_MCMN_R0_S_PARE3__VAL___M 0xFFFFFFFF +#define WMAC0_MCMN_R0_S_PARE3__VAL___S 0 +#define WMAC0_MCMN_R0_S_PARE3___M 0xFFFFFFFF +#define WMAC0_MCMN_R0_S_PARE3___S 0 + +#define WMAC0_MCMN_R0_L0_REQ_OVERIDE (0x00A892BC) +#define WMAC0_MCMN_R0_L0_REQ_OVERIDE___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_L0_REQ_OVERIDE___POR 0x00000000 +#define WMAC0_MCMN_R0_L0_REQ_OVERIDE__VALUE___POR 0x0 +#define WMAC0_MCMN_R0_L0_REQ_OVERIDE__ENABLE___POR 0x0 +#define WMAC0_MCMN_R0_L0_REQ_OVERIDE__VALUE___M 0x00000002 +#define WMAC0_MCMN_R0_L0_REQ_OVERIDE__VALUE___S 1 +#define WMAC0_MCMN_R0_L0_REQ_OVERIDE__ENABLE___M 0x00000001 +#define WMAC0_MCMN_R0_L0_REQ_OVERIDE__ENABLE___S 0 +#define WMAC0_MCMN_R0_L0_REQ_OVERIDE___M 0x00000003 +#define WMAC0_MCMN_R0_L0_REQ_OVERIDE___S 0 + +#define WMAC0_MCMN_R0_WMAC_IDLE_LENGTH_ATB (0x00A892C0) +#define WMAC0_MCMN_R0_WMAC_IDLE_LENGTH_ATB___RWC QCSR_REG_RW +#define WMAC0_MCMN_R0_WMAC_IDLE_LENGTH_ATB___POR 0x0000000A +#define WMAC0_MCMN_R0_WMAC_IDLE_LENGTH_ATB__VALUE___POR 0x0A +#define WMAC0_MCMN_R0_WMAC_IDLE_LENGTH_ATB__VALUE___M 0x0000003F +#define WMAC0_MCMN_R0_WMAC_IDLE_LENGTH_ATB__VALUE___S 0 +#define WMAC0_MCMN_R0_WMAC_IDLE_LENGTH_ATB___M 0x0000003F +#define WMAC0_MCMN_R0_WMAC_IDLE_LENGTH_ATB___S 0 + +#define WMAC0_MCMN_R1_MAC_PCU_RX_FRAME_CNT (0x00A8A000) +#define WMAC0_MCMN_R1_MAC_PCU_RX_FRAME_CNT___RWC QCSR_REG_RW +#define WMAC0_MCMN_R1_MAC_PCU_RX_FRAME_CNT___POR 0x00000000 +#define WMAC0_MCMN_R1_MAC_PCU_RX_FRAME_CNT__VALUE___POR 0x00000000 +#define WMAC0_MCMN_R1_MAC_PCU_RX_FRAME_CNT__VALUE___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_MAC_PCU_RX_FRAME_CNT__VALUE___S 0 +#define WMAC0_MCMN_R1_MAC_PCU_RX_FRAME_CNT___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_MAC_PCU_RX_FRAME_CNT___S 0 + +#define WMAC0_MCMN_R1_MAC_PCU_TX_FRAME_CNT (0x00A8A004) +#define WMAC0_MCMN_R1_MAC_PCU_TX_FRAME_CNT___RWC QCSR_REG_RW +#define WMAC0_MCMN_R1_MAC_PCU_TX_FRAME_CNT___POR 0x00000000 +#define WMAC0_MCMN_R1_MAC_PCU_TX_FRAME_CNT__VALUE___POR 0x00000000 +#define WMAC0_MCMN_R1_MAC_PCU_TX_FRAME_CNT__VALUE___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_MAC_PCU_TX_FRAME_CNT__VALUE___S 0 +#define WMAC0_MCMN_R1_MAC_PCU_TX_FRAME_CNT___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_MAC_PCU_TX_FRAME_CNT___S 0 + +#define WMAC0_MCMN_R1_MAC_PCU_RX_CLEAR_CNT (0x00A8A008) +#define WMAC0_MCMN_R1_MAC_PCU_RX_CLEAR_CNT___RWC QCSR_REG_RW +#define WMAC0_MCMN_R1_MAC_PCU_RX_CLEAR_CNT___POR 0x00000000 +#define WMAC0_MCMN_R1_MAC_PCU_RX_CLEAR_CNT__VALUE___POR 0x00000000 +#define WMAC0_MCMN_R1_MAC_PCU_RX_CLEAR_CNT__VALUE___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_MAC_PCU_RX_CLEAR_CNT__VALUE___S 0 +#define WMAC0_MCMN_R1_MAC_PCU_RX_CLEAR_CNT___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_MAC_PCU_RX_CLEAR_CNT___S 0 + +#define WMAC0_MCMN_R1_TRC_VID0 (0x00A8A00C) +#define WMAC0_MCMN_R1_TRC_VID0___RWC QCSR_REG_RW +#define WMAC0_MCMN_R1_TRC_VID0___POR 0x0C520C41 +#define WMAC0_MCMN_R1_TRC_VID0__RXOLE___POR 0x06 +#define WMAC0_MCMN_R1_TRC_VID0__TXOLE___POR 0x05 +#define WMAC0_MCMN_R1_TRC_VID0__RXDMA___POR 0x04 +#define WMAC0_MCMN_R1_TRC_VID0__TXDMA___POR 0x03 +#define WMAC0_MCMN_R1_TRC_VID0__PDG___POR 0x02 +#define WMAC0_MCMN_R1_TRC_VID0__HWSCH___POR 0x01 +#define WMAC0_MCMN_R1_TRC_VID0__RXOLE___M 0x3E000000 +#define WMAC0_MCMN_R1_TRC_VID0__RXOLE___S 25 +#define WMAC0_MCMN_R1_TRC_VID0__TXOLE___M 0x01F00000 +#define WMAC0_MCMN_R1_TRC_VID0__TXOLE___S 20 +#define WMAC0_MCMN_R1_TRC_VID0__RXDMA___M 0x000F8000 +#define WMAC0_MCMN_R1_TRC_VID0__RXDMA___S 15 +#define WMAC0_MCMN_R1_TRC_VID0__TXDMA___M 0x00007C00 +#define WMAC0_MCMN_R1_TRC_VID0__TXDMA___S 10 +#define WMAC0_MCMN_R1_TRC_VID0__PDG___M 0x000003E0 +#define WMAC0_MCMN_R1_TRC_VID0__PDG___S 5 +#define WMAC0_MCMN_R1_TRC_VID0__HWSCH___M 0x0000001F +#define WMAC0_MCMN_R1_TRC_VID0__HWSCH___S 0 +#define WMAC0_MCMN_R1_TRC_VID0___M 0x3FFFFFFF +#define WMAC0_MCMN_R1_TRC_VID0___S 0 + +#define WMAC0_MCMN_R1_TRC_VID1 (0x00A8A010) +#define WMAC0_MCMN_R1_TRC_VID1___RWC QCSR_REG_RW +#define WMAC0_MCMN_R1_TRC_VID1___POR 0x18B52507 +#define WMAC0_MCMN_R1_TRC_VID1__C___POR 0x0C +#define WMAC0_MCMN_R1_TRC_VID1__AMPI___POR 0x0B +#define WMAC0_MCMN_R1_TRC_VID1__RRI___POR 0x0A +#define WMAC0_MCMN_R1_TRC_VID1__RXPCU___POR 0x09 +#define WMAC0_MCMN_R1_TRC_VID1__TXPCU___POR 0x08 +#define WMAC0_MCMN_R1_TRC_VID1__CRYPTO___POR 0x07 +#define WMAC0_MCMN_R1_TRC_VID1__C___M 0x3E000000 +#define WMAC0_MCMN_R1_TRC_VID1__C___S 25 +#define WMAC0_MCMN_R1_TRC_VID1__AMPI___M 0x01F00000 +#define WMAC0_MCMN_R1_TRC_VID1__AMPI___S 20 +#define WMAC0_MCMN_R1_TRC_VID1__RRI___M 0x000F8000 +#define WMAC0_MCMN_R1_TRC_VID1__RRI___S 15 +#define WMAC0_MCMN_R1_TRC_VID1__RXPCU___M 0x00007C00 +#define WMAC0_MCMN_R1_TRC_VID1__RXPCU___S 10 +#define WMAC0_MCMN_R1_TRC_VID1__TXPCU___M 0x000003E0 +#define WMAC0_MCMN_R1_TRC_VID1__TXPCU___S 5 +#define WMAC0_MCMN_R1_TRC_VID1__CRYPTO___M 0x0000001F +#define WMAC0_MCMN_R1_TRC_VID1__CRYPTO___S 0 +#define WMAC0_MCMN_R1_TRC_VID1___M 0x3FFFFFFF +#define WMAC0_MCMN_R1_TRC_VID1___S 0 + +#define WMAC0_MCMN_R1_TRC_VID2 (0x00A8A014) +#define WMAC0_MCMN_R1_TRC_VID2___RWC QCSR_REG_RW +#define WMAC0_MCMN_R1_TRC_VID2___POR 0x251801CD +#define WMAC0_MCMN_R1_TRC_VID2__OVERWRITE_MODE___POR 0x0 +#define WMAC0_MCMN_R1_TRC_VID2__SFM___POR 0x12 +#define WMAC0_MCMN_R1_TRC_VID2__RXOLEB1___POR 0x11 +#define WMAC0_MCMN_R1_TRC_VID2__LPEC___POR 0x10 +#define WMAC0_MCMN_R1_TRC_VID2__MCMN___POR 0x0E +#define WMAC0_MCMN_R1_TRC_VID2__MXI___POR 0x0D +#define WMAC0_MCMN_R1_TRC_VID2__OVERWRITE_MODE___M 0x80000000 +#define WMAC0_MCMN_R1_TRC_VID2__OVERWRITE_MODE___S 31 +#define WMAC0_MCMN_R1_TRC_VID2__SFM___M 0x3E000000 +#define WMAC0_MCMN_R1_TRC_VID2__SFM___S 25 +#define WMAC0_MCMN_R1_TRC_VID2__RXOLEB1___M 0x01F00000 +#define WMAC0_MCMN_R1_TRC_VID2__RXOLEB1___S 20 +#define WMAC0_MCMN_R1_TRC_VID2__LPEC___M 0x000F8000 +#define WMAC0_MCMN_R1_TRC_VID2__LPEC___S 15 +#define WMAC0_MCMN_R1_TRC_VID2__MCMN___M 0x000003E0 +#define WMAC0_MCMN_R1_TRC_VID2__MCMN___S 5 +#define WMAC0_MCMN_R1_TRC_VID2__MXI___M 0x0000001F +#define WMAC0_MCMN_R1_TRC_VID2__MXI___S 0 +#define WMAC0_MCMN_R1_TRC_VID2___M 0xBFFF83FF +#define WMAC0_MCMN_R1_TRC_VID2___S 0 + +#define WMAC0_MCMN_R1_TRC_VID3 (0x00A8A018) +#define WMAC0_MCMN_R1_TRC_VID3___RWC QCSR_REG_RW +#define WMAC0_MCMN_R1_TRC_VID3___POR 0x00000013 +#define WMAC0_MCMN_R1_TRC_VID3__LPECEB1___POR 0x13 +#define WMAC0_MCMN_R1_TRC_VID3__LPECEB1___M 0x0000001F +#define WMAC0_MCMN_R1_TRC_VID3__LPECEB1___S 0 +#define WMAC0_MCMN_R1_TRC_VID3___M 0x0000001F +#define WMAC0_MCMN_R1_TRC_VID3___S 0 + +#define WMAC0_MCMN_R1_MAC_PCU_CYCLE_CNT (0x00A8A01C) +#define WMAC0_MCMN_R1_MAC_PCU_CYCLE_CNT___RWC QCSR_REG_RW +#define WMAC0_MCMN_R1_MAC_PCU_CYCLE_CNT___POR 0x00000000 +#define WMAC0_MCMN_R1_MAC_PCU_CYCLE_CNT__VALUE___POR 0x00000000 +#define WMAC0_MCMN_R1_MAC_PCU_CYCLE_CNT__VALUE___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_MAC_PCU_CYCLE_CNT__VALUE___S 0 +#define WMAC0_MCMN_R1_MAC_PCU_CYCLE_CNT___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_MAC_PCU_CYCLE_CNT___S 0 + +#define WMAC0_MCMN_R1_MCMN_STM_MUX_SELECT (0x00A8A020) +#define WMAC0_MCMN_R1_MCMN_STM_MUX_SELECT___RWC QCSR_REG_RW +#define WMAC0_MCMN_R1_MCMN_STM_MUX_SELECT___POR 0x00000000 +#define WMAC0_MCMN_R1_MCMN_STM_MUX_SELECT__VAL___POR 0x0 +#define WMAC0_MCMN_R1_MCMN_STM_MUX_SELECT__VAL___M 0x00000001 +#define WMAC0_MCMN_R1_MCMN_STM_MUX_SELECT__VAL___S 0 +#define WMAC0_MCMN_R1_MCMN_STM_MUX_SELECT___M 0x00000001 +#define WMAC0_MCMN_R1_MCMN_STM_MUX_SELECT___S 0 + +#define WMAC0_MCMN_R1_DEBUG_LMAC (0x00A8A024) +#define WMAC0_MCMN_R1_DEBUG_LMAC___RWC QCSR_REG_RW +#define WMAC0_MCMN_R1_DEBUG_LMAC___POR 0x00000000 +#define WMAC0_MCMN_R1_DEBUG_LMAC__TLV_SEL___POR 0x0 +#define WMAC0_MCMN_R1_DEBUG_LMAC__TLV_SEL___M 0x0000000F +#define WMAC0_MCMN_R1_DEBUG_LMAC__TLV_SEL___S 0 +#define WMAC0_MCMN_R1_DEBUG_LMAC___M 0x0000000F +#define WMAC0_MCMN_R1_DEBUG_LMAC___S 0 + +#define WMAC0_MCMN_R1_LMAC_IDLE (0x00A8A028) +#define WMAC0_MCMN_R1_LMAC_IDLE___RWC QCSR_REG_RO +#define WMAC0_MCMN_R1_LMAC_IDLE___POR 0x00000000 +#define WMAC0_MCMN_R1_LMAC_IDLE__LMAC_IDLE_GEN_MOD_BUSY___POR 0x0 +#define WMAC0_MCMN_R1_LMAC_IDLE__MAIN_SM_CS___POR 0x000 +#define WMAC0_MCMN_R1_LMAC_IDLE__RX_SM_CS___POR 0x00 +#define WMAC0_MCMN_R1_LMAC_IDLE__TX_SM_CS___POR 0x000 +#define WMAC0_MCMN_R1_LMAC_IDLE__VALUE___POR 0x0 +#define WMAC0_MCMN_R1_LMAC_IDLE__LMAC_IDLE_GEN_MOD_BUSY___M 0x10000000 +#define WMAC0_MCMN_R1_LMAC_IDLE__LMAC_IDLE_GEN_MOD_BUSY___S 28 +#define WMAC0_MCMN_R1_LMAC_IDLE__MAIN_SM_CS___M 0x0FF80000 +#define WMAC0_MCMN_R1_LMAC_IDLE__MAIN_SM_CS___S 19 +#define WMAC0_MCMN_R1_LMAC_IDLE__RX_SM_CS___M 0x0007F800 +#define WMAC0_MCMN_R1_LMAC_IDLE__RX_SM_CS___S 11 +#define WMAC0_MCMN_R1_LMAC_IDLE__TX_SM_CS___M 0x000007FE +#define WMAC0_MCMN_R1_LMAC_IDLE__TX_SM_CS___S 1 +#define WMAC0_MCMN_R1_LMAC_IDLE__VALUE___M 0x00000001 +#define WMAC0_MCMN_R1_LMAC_IDLE__VALUE___S 0 +#define WMAC0_MCMN_R1_LMAC_IDLE___M 0x1FFFFFFF +#define WMAC0_MCMN_R1_LMAC_IDLE___S 0 + +#define WMAC0_MCMN_R1_MCMN_STM_SELECT1 (0x00A8A02C) +#define WMAC0_MCMN_R1_MCMN_STM_SELECT1___RWC QCSR_REG_RW +#define WMAC0_MCMN_R1_MCMN_STM_SELECT1___POR 0x00000000 +#define WMAC0_MCMN_R1_MCMN_STM_SELECT1__VAL___POR 0x0 +#define WMAC0_MCMN_R1_MCMN_STM_SELECT1__VAL___M 0x0000000F +#define WMAC0_MCMN_R1_MCMN_STM_SELECT1__VAL___S 0 +#define WMAC0_MCMN_R1_MCMN_STM_SELECT1___M 0x0000000F +#define WMAC0_MCMN_R1_MCMN_STM_SELECT1___S 0 + +#define WMAC0_MCMN_R1_TESTBUS_SELECT (0x00A8A030) +#define WMAC0_MCMN_R1_TESTBUS_SELECT___RWC QCSR_REG_RW +#define WMAC0_MCMN_R1_TESTBUS_SELECT___POR 0x00000000 +#define WMAC0_MCMN_R1_TESTBUS_SELECT__WMAC_SEL___POR 0x00 +#define WMAC0_MCMN_R1_TESTBUS_SELECT__WMAC_SEL___M 0x0000001F +#define WMAC0_MCMN_R1_TESTBUS_SELECT__WMAC_SEL___S 0 +#define WMAC0_MCMN_R1_TESTBUS_SELECT___M 0x0000001F +#define WMAC0_MCMN_R1_TESTBUS_SELECT___S 0 + +#define WMAC0_MCMN_R1_TLV_READY (0x00A8A034) +#define WMAC0_MCMN_R1_TLV_READY___RWC QCSR_REG_RO +#define WMAC0_MCMN_R1_TLV_READY___POR 0x00000000 +#define WMAC0_MCMN_R1_TLV_READY__HWSCH_COEX_TLV___POR 0x0 +#define WMAC0_MCMN_R1_TLV_READY__TXOLE_TXDMA_TLV___POR 0x0 +#define WMAC0_MCMN_R1_TLV_READY__PDG_TXDMA_TLV___POR 0x0 +#define WMAC0_MCMN_R1_TLV_READY__TXDMA_TXOLE_TLV___POR 0x0 +#define WMAC0_MCMN_R1_TLV_READY__TXDMA_PDG_TLV___POR 0x0 +#define WMAC0_MCMN_R1_TLV_READY__HWSCH_PDG_TLV___POR 0x0 +#define WMAC0_MCMN_R1_TLV_READY__PDG_HWSCH_TLV___POR 0x0 +#define WMAC0_MCMN_R1_TLV_READY__CRYPTO_RXOLE_TLV___POR 0x0 +#define WMAC0_MCMN_R1_TLV_READY__CRYPTO_TXOLE_TLV___POR 0x0 +#define WMAC0_MCMN_R1_TLV_READY__CRYPTO_TXPCU_TLV___POR 0x0 +#define WMAC0_MCMN_R1_TLV_READY__TXOLE_CRYPTO_TLV___POR 0x0 +#define WMAC0_MCMN_R1_TLV_READY__RXPCU_CRYPTO_TLV___POR 0x0 +#define WMAC0_MCMN_R1_TLV_READY__TXPCU_CRYPTO_TLV___POR 0x0 +#define WMAC0_MCMN_R1_TLV_READY__RXOLE_RXDMA_TLV___POR 0x0 +#define WMAC0_MCMN_R1_TLV_READY__PDG_TXPCU_TLV___POR 0x0 +#define WMAC0_MCMN_R1_TLV_READY__COEX_HWSCH_TLV___POR 0x0 +#define WMAC0_MCMN_R1_TLV_READY__RXPCU_TXPCU_TLV___POR 0x0 +#define WMAC0_MCMN_R1_TLV_READY__TXPCU_RXPCU_TLV___POR 0x0 +#define WMAC0_MCMN_R1_TLV_READY__AMPI_TXPCU_TLV___POR 0x0 +#define WMAC0_MCMN_R1_TLV_READY__TXPCU_AMPI_TLV___POR 0x0 +#define WMAC0_MCMN_R1_TLV_READY__HWSCH_COEX_TLV___M 0x00080000 +#define WMAC0_MCMN_R1_TLV_READY__HWSCH_COEX_TLV___S 19 +#define WMAC0_MCMN_R1_TLV_READY__TXOLE_TXDMA_TLV___M 0x00040000 +#define WMAC0_MCMN_R1_TLV_READY__TXOLE_TXDMA_TLV___S 18 +#define WMAC0_MCMN_R1_TLV_READY__PDG_TXDMA_TLV___M 0x00020000 +#define WMAC0_MCMN_R1_TLV_READY__PDG_TXDMA_TLV___S 17 +#define WMAC0_MCMN_R1_TLV_READY__TXDMA_TXOLE_TLV___M 0x00010000 +#define WMAC0_MCMN_R1_TLV_READY__TXDMA_TXOLE_TLV___S 16 +#define WMAC0_MCMN_R1_TLV_READY__TXDMA_PDG_TLV___M 0x00008000 +#define WMAC0_MCMN_R1_TLV_READY__TXDMA_PDG_TLV___S 15 +#define WMAC0_MCMN_R1_TLV_READY__HWSCH_PDG_TLV___M 0x00004000 +#define WMAC0_MCMN_R1_TLV_READY__HWSCH_PDG_TLV___S 14 +#define WMAC0_MCMN_R1_TLV_READY__PDG_HWSCH_TLV___M 0x00002000 +#define WMAC0_MCMN_R1_TLV_READY__PDG_HWSCH_TLV___S 13 +#define WMAC0_MCMN_R1_TLV_READY__CRYPTO_RXOLE_TLV___M 0x00001000 +#define WMAC0_MCMN_R1_TLV_READY__CRYPTO_RXOLE_TLV___S 12 +#define WMAC0_MCMN_R1_TLV_READY__CRYPTO_TXOLE_TLV___M 0x00000800 +#define WMAC0_MCMN_R1_TLV_READY__CRYPTO_TXOLE_TLV___S 11 +#define WMAC0_MCMN_R1_TLV_READY__CRYPTO_TXPCU_TLV___M 0x00000400 +#define WMAC0_MCMN_R1_TLV_READY__CRYPTO_TXPCU_TLV___S 10 +#define WMAC0_MCMN_R1_TLV_READY__TXOLE_CRYPTO_TLV___M 0x00000200 +#define WMAC0_MCMN_R1_TLV_READY__TXOLE_CRYPTO_TLV___S 9 +#define WMAC0_MCMN_R1_TLV_READY__RXPCU_CRYPTO_TLV___M 0x00000100 +#define WMAC0_MCMN_R1_TLV_READY__RXPCU_CRYPTO_TLV___S 8 +#define WMAC0_MCMN_R1_TLV_READY__TXPCU_CRYPTO_TLV___M 0x00000080 +#define WMAC0_MCMN_R1_TLV_READY__TXPCU_CRYPTO_TLV___S 7 +#define WMAC0_MCMN_R1_TLV_READY__RXOLE_RXDMA_TLV___M 0x00000040 +#define WMAC0_MCMN_R1_TLV_READY__RXOLE_RXDMA_TLV___S 6 +#define WMAC0_MCMN_R1_TLV_READY__PDG_TXPCU_TLV___M 0x00000020 +#define WMAC0_MCMN_R1_TLV_READY__PDG_TXPCU_TLV___S 5 +#define WMAC0_MCMN_R1_TLV_READY__COEX_HWSCH_TLV___M 0x00000010 +#define WMAC0_MCMN_R1_TLV_READY__COEX_HWSCH_TLV___S 4 +#define WMAC0_MCMN_R1_TLV_READY__RXPCU_TXPCU_TLV___M 0x00000008 +#define WMAC0_MCMN_R1_TLV_READY__RXPCU_TXPCU_TLV___S 3 +#define WMAC0_MCMN_R1_TLV_READY__TXPCU_RXPCU_TLV___M 0x00000004 +#define WMAC0_MCMN_R1_TLV_READY__TXPCU_RXPCU_TLV___S 2 +#define WMAC0_MCMN_R1_TLV_READY__AMPI_TXPCU_TLV___M 0x00000002 +#define WMAC0_MCMN_R1_TLV_READY__AMPI_TXPCU_TLV___S 1 +#define WMAC0_MCMN_R1_TLV_READY__TXPCU_AMPI_TLV___M 0x00000001 +#define WMAC0_MCMN_R1_TLV_READY__TXPCU_AMPI_TLV___S 0 +#define WMAC0_MCMN_R1_TLV_READY___M 0x000FFFFF +#define WMAC0_MCMN_R1_TLV_READY___S 0 + +#define WMAC0_MCMN_R1_TRC_SELECT (0x00A8A038) +#define WMAC0_MCMN_R1_TRC_SELECT___RWC QCSR_REG_RW +#define WMAC0_MCMN_R1_TRC_SELECT___POR 0x00000001 +#define WMAC0_MCMN_R1_TRC_SELECT__AMPI_MAC_EVENT___POR 0x0 +#define WMAC0_MCMN_R1_TRC_SELECT__VAL___POR 0x1 +#define WMAC0_MCMN_R1_TRC_SELECT__AMPI_MAC_EVENT___M 0x00000002 +#define WMAC0_MCMN_R1_TRC_SELECT__AMPI_MAC_EVENT___S 1 +#define WMAC0_MCMN_R1_TRC_SELECT__VAL___M 0x00000001 +#define WMAC0_MCMN_R1_TRC_SELECT__VAL___S 0 +#define WMAC0_MCMN_R1_TRC_SELECT___M 0x00000003 +#define WMAC0_MCMN_R1_TRC_SELECT___S 0 + +#define WMAC0_MCMN_R1_TRC_BLOCK_MASK (0x00A8A03C) +#define WMAC0_MCMN_R1_TRC_BLOCK_MASK___RWC QCSR_REG_RW +#define WMAC0_MCMN_R1_TRC_BLOCK_MASK___POR 0x00000000 +#define WMAC0_MCMN_R1_TRC_BLOCK_MASK__VAL___POR 0x00000 +#define WMAC0_MCMN_R1_TRC_BLOCK_MASK__VAL___M 0x000FFFFF +#define WMAC0_MCMN_R1_TRC_BLOCK_MASK__VAL___S 0 +#define WMAC0_MCMN_R1_TRC_BLOCK_MASK___M 0x000FFFFF +#define WMAC0_MCMN_R1_TRC_BLOCK_MASK___S 0 + +#define WMAC0_MCMN_R1_TRC_SW_EVENT (0x00A8A040) +#define WMAC0_MCMN_R1_TRC_SW_EVENT___RWC QCSR_REG_RW +#define WMAC0_MCMN_R1_TRC_SW_EVENT___POR 0x00000000 +#define WMAC0_MCMN_R1_TRC_SW_EVENT__VALID___POR 0x0 +#define WMAC0_MCMN_R1_TRC_SW_EVENT__IN___POR 0x00000000 +#define WMAC0_MCMN_R1_TRC_SW_EVENT__VALID___M 0x40000000 +#define WMAC0_MCMN_R1_TRC_SW_EVENT__VALID___S 30 +#define WMAC0_MCMN_R1_TRC_SW_EVENT__IN___M 0x3FFFFFFF +#define WMAC0_MCMN_R1_TRC_SW_EVENT__IN___S 0 +#define WMAC0_MCMN_R1_TRC_SW_EVENT___M 0x7FFFFFFF +#define WMAC0_MCMN_R1_TRC_SW_EVENT___S 0 + +#define WMAC0_MCMN_R1_MAC_PCU_PRIMARY_CCA_ED0_CNT (0x00A8A044) +#define WMAC0_MCMN_R1_MAC_PCU_PRIMARY_CCA_ED0_CNT___RWC QCSR_REG_RW +#define WMAC0_MCMN_R1_MAC_PCU_PRIMARY_CCA_ED0_CNT___POR 0x00000000 +#define WMAC0_MCMN_R1_MAC_PCU_PRIMARY_CCA_ED0_CNT__VALUE___POR 0x00000000 +#define WMAC0_MCMN_R1_MAC_PCU_PRIMARY_CCA_ED0_CNT__VALUE___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_MAC_PCU_PRIMARY_CCA_ED0_CNT__VALUE___S 0 +#define WMAC0_MCMN_R1_MAC_PCU_PRIMARY_CCA_ED0_CNT___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_MAC_PCU_PRIMARY_CCA_ED0_CNT___S 0 + +#define WMAC0_MCMN_R1_MAC_PCU_SECONDARY_20_CCA_ED0_CNT (0x00A8A048) +#define WMAC0_MCMN_R1_MAC_PCU_SECONDARY_20_CCA_ED0_CNT___RWC QCSR_REG_RW +#define WMAC0_MCMN_R1_MAC_PCU_SECONDARY_20_CCA_ED0_CNT___POR 0x00000000 +#define WMAC0_MCMN_R1_MAC_PCU_SECONDARY_20_CCA_ED0_CNT__VALUE___POR 0x00000000 +#define WMAC0_MCMN_R1_MAC_PCU_SECONDARY_20_CCA_ED0_CNT__VALUE___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_MAC_PCU_SECONDARY_20_CCA_ED0_CNT__VALUE___S 0 +#define WMAC0_MCMN_R1_MAC_PCU_SECONDARY_20_CCA_ED0_CNT___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_MAC_PCU_SECONDARY_20_CCA_ED0_CNT___S 0 + +#define WMAC0_MCMN_R1_MAC_PCU_SECONDARY_40_CCA_ED0_CNT (0x00A8A04C) +#define WMAC0_MCMN_R1_MAC_PCU_SECONDARY_40_CCA_ED0_CNT___RWC QCSR_REG_RW +#define WMAC0_MCMN_R1_MAC_PCU_SECONDARY_40_CCA_ED0_CNT___POR 0x00000000 +#define WMAC0_MCMN_R1_MAC_PCU_SECONDARY_40_CCA_ED0_CNT__VALUE___POR 0x00000000 +#define WMAC0_MCMN_R1_MAC_PCU_SECONDARY_40_CCA_ED0_CNT__VALUE___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_MAC_PCU_SECONDARY_40_CCA_ED0_CNT__VALUE___S 0 +#define WMAC0_MCMN_R1_MAC_PCU_SECONDARY_40_CCA_ED0_CNT___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_MAC_PCU_SECONDARY_40_CCA_ED0_CNT___S 0 + +#define WMAC0_MCMN_R1_MAC_PCU_SECONDARY_80_CCA_ED0_CNT (0x00A8A050) +#define WMAC0_MCMN_R1_MAC_PCU_SECONDARY_80_CCA_ED0_CNT___RWC QCSR_REG_RW +#define WMAC0_MCMN_R1_MAC_PCU_SECONDARY_80_CCA_ED0_CNT___POR 0x00000000 +#define WMAC0_MCMN_R1_MAC_PCU_SECONDARY_80_CCA_ED0_CNT__VALUE___POR 0x00000000 +#define WMAC0_MCMN_R1_MAC_PCU_SECONDARY_80_CCA_ED0_CNT__VALUE___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_MAC_PCU_SECONDARY_80_CCA_ED0_CNT__VALUE___S 0 +#define WMAC0_MCMN_R1_MAC_PCU_SECONDARY_80_CCA_ED0_CNT___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_MAC_PCU_SECONDARY_80_CCA_ED0_CNT___S 0 + +#define WMAC0_MCMN_R1_TLV_TESTBUS_SELECT (0x00A8A054) +#define WMAC0_MCMN_R1_TLV_TESTBUS_SELECT___RWC QCSR_REG_RW +#define WMAC0_MCMN_R1_TLV_TESTBUS_SELECT___POR 0x00000000 +#define WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__SPECIFIC_TAG_ID___POR 0x00 +#define WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__TLV_TYPE___POR 0x0 +#define WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__OTHER_TLV___POR 0x0 +#define WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__SPECIFIC_TLV___POR 0x0 +#define WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__DATA_TLV___POR 0x0 +#define WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__EN___POR 0x0 +#define WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__VAL___POR 0x00 +#define WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__SPECIFIC_TAG_ID___M 0x003FC000 +#define WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__SPECIFIC_TAG_ID___S 14 +#define WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__TLV_TYPE___M 0x00003000 +#define WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__TLV_TYPE___S 12 +#define WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__OTHER_TLV___M 0x00000C00 +#define WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__OTHER_TLV___S 10 +#define WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__SPECIFIC_TLV___M 0x00000300 +#define WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__SPECIFIC_TLV___S 8 +#define WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__DATA_TLV___M 0x000000C0 +#define WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__DATA_TLV___S 6 +#define WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__EN___M 0x00000020 +#define WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__EN___S 5 +#define WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__VAL___M 0x0000001F +#define WMAC0_MCMN_R1_TLV_TESTBUS_SELECT__VAL___S 0 +#define WMAC0_MCMN_R1_TLV_TESTBUS_SELECT___M 0x003FFFFF +#define WMAC0_MCMN_R1_TLV_TESTBUS_SELECT___S 0 + +#define WMAC0_MCMN_R1_TESTBUS_VALID_CONTROL (0x00A8A058) +#define WMAC0_MCMN_R1_TESTBUS_VALID_CONTROL___RWC QCSR_REG_RW +#define WMAC0_MCMN_R1_TESTBUS_VALID_CONTROL___POR 0x00000000 +#define WMAC0_MCMN_R1_TESTBUS_VALID_CONTROL__VAL___POR 0x0 +#define WMAC0_MCMN_R1_TESTBUS_VALID_CONTROL__VAL___M 0x00000003 +#define WMAC0_MCMN_R1_TESTBUS_VALID_CONTROL__VAL___S 0 +#define WMAC0_MCMN_R1_TESTBUS_VALID_CONTROL___M 0x00000003 +#define WMAC0_MCMN_R1_TESTBUS_VALID_CONTROL___S 0 + +#define WMAC0_MCMN_R1_SUBSYSTEM_ID (0x00A8A05C) +#define WMAC0_MCMN_R1_SUBSYSTEM_ID___RWC QCSR_REG_RW +#define WMAC0_MCMN_R1_SUBSYSTEM_ID___POR 0x00000001 +#define WMAC0_MCMN_R1_SUBSYSTEM_ID__VAL___POR 0x1 +#define WMAC0_MCMN_R1_SUBSYSTEM_ID__VAL___M 0x00000003 +#define WMAC0_MCMN_R1_SUBSYSTEM_ID__VAL___S 0 +#define WMAC0_MCMN_R1_SUBSYSTEM_ID___M 0x00000003 +#define WMAC0_MCMN_R1_SUBSYSTEM_ID___S 0 + +#define WMAC0_MCMN_R1_DEBUG_ENABLE (0x00A8A060) +#define WMAC0_MCMN_R1_DEBUG_ENABLE___RWC QCSR_REG_RW +#define WMAC0_MCMN_R1_DEBUG_ENABLE___POR 0x00000000 +#define WMAC0_MCMN_R1_DEBUG_ENABLE__TMESTMP_TLV_THRESHLD_VAL___POR 0x000 +#define WMAC0_MCMN_R1_DEBUG_ENABLE__TIMESTAMP_INSERTION___POR 0x0 +#define WMAC0_MCMN_R1_DEBUG_ENABLE__VAL___POR 0x0 +#define WMAC0_MCMN_R1_DEBUG_ENABLE__TMESTMP_TLV_THRESHLD_VAL___M 0x0FFF0000 +#define WMAC0_MCMN_R1_DEBUG_ENABLE__TMESTMP_TLV_THRESHLD_VAL___S 16 +#define WMAC0_MCMN_R1_DEBUG_ENABLE__TIMESTAMP_INSERTION___M 0x00000002 +#define WMAC0_MCMN_R1_DEBUG_ENABLE__TIMESTAMP_INSERTION___S 1 +#define WMAC0_MCMN_R1_DEBUG_ENABLE__VAL___M 0x00000001 +#define WMAC0_MCMN_R1_DEBUG_ENABLE__VAL___S 0 +#define WMAC0_MCMN_R1_DEBUG_ENABLE___M 0x0FFF0003 +#define WMAC0_MCMN_R1_DEBUG_ENABLE___S 0 + +#define WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ (0x00A8A064) +#define WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ___RWC QCSR_REG_RO +#define WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ___POR 0x00000000 +#define WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ__COUNT___POR 0x00000000 +#define WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ__COUNT___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ__COUNT___S 0 +#define WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ___S 0 + +#define WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ_TIME (0x00A8A068) +#define WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ_TIME___RWC QCSR_REG_RO +#define WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ_TIME___POR 0x00000000 +#define WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ_TIME__DURATION___POR 0x00000000 +#define WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ_TIME__DURATION___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ_TIME__DURATION___S 0 +#define WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ_TIME___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_DEBUG_ILP_HWSCH_L0_REQ_TIME___S 0 + +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ (0x00A8A06C) +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ___RWC QCSR_REG_RO +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ___POR 0x00000000 +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ__COUNT___POR 0x00000000 +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ__COUNT___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ__COUNT___S 0 +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ___S 0 + +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ_TIME (0x00A8A070) +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ_TIME___RWC QCSR_REG_RO +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ_TIME___POR 0x00000000 +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ_TIME__DURATION___POR 0x00000000 +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ_TIME__DURATION___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ_TIME__DURATION___S 0 +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ_TIME___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_L0_REQ_TIME___S 0 + +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ (0x00A8A074) +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ___RWC QCSR_REG_RO +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ___POR 0x00000000 +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ__COUNT___POR 0x00000000 +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ__COUNT___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ__COUNT___S 0 +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ___S 0 + +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ_TIME (0x00A8A078) +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ_TIME___RWC QCSR_REG_RO +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ_TIME___POR 0x00000000 +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ_TIME__DURATION___POR 0x00000000 +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ_TIME__DURATION___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ_TIME__DURATION___S 0 +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ_TIME___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_DEBUG_ILP_RXPCU_MASK_HWSCH_L0_REQ_TIME___S 0 + +#define WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ (0x00A8A07C) +#define WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ___RWC QCSR_REG_RO +#define WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ___POR 0x00000000 +#define WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ__COUNT___POR 0x00000000 +#define WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ__COUNT___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ__COUNT___S 0 +#define WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ___S 0 + +#define WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ_TIME (0x00A8A080) +#define WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ_TIME___RWC QCSR_REG_RO +#define WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ_TIME___POR 0x00000000 +#define WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ_TIME__DURATION___POR 0x00000000 +#define WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ_TIME__DURATION___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ_TIME__DURATION___S 0 +#define WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ_TIME___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_DEBUG_ILP_COMBINED_L0_REQ_TIME___S 0 + +#define WMAC0_MCMN_R1_MAC_PCU_DIAG_SW (0x00A8A220) +#define WMAC0_MCMN_R1_MAC_PCU_DIAG_SW___RWC QCSR_REG_RW +#define WMAC0_MCMN_R1_MAC_PCU_DIAG_SW___POR 0x00000000 +#define WMAC0_MCMN_R1_MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT___POR 0x0 +#define WMAC0_MCMN_R1_MAC_PCU_DIAG_SW__FORCE_RX_ABORT___POR 0x0 +#define WMAC0_MCMN_R1_MAC_PCU_DIAG_SW__ACCEPT_NON_V0___POR 0x0 +#define WMAC0_MCMN_R1_MAC_PCU_DIAG_SW__HALT_RX___POR 0x0 +#define WMAC0_MCMN_R1_MAC_PCU_DIAG_SW__NO_DECRYPT___POR 0x0 +#define WMAC0_MCMN_R1_MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT___M 0x00000010 +#define WMAC0_MCMN_R1_MAC_PCU_DIAG_SW__SATURATE_CYCLE_CNT___S 4 +#define WMAC0_MCMN_R1_MAC_PCU_DIAG_SW__FORCE_RX_ABORT___M 0x00000008 +#define WMAC0_MCMN_R1_MAC_PCU_DIAG_SW__FORCE_RX_ABORT___S 3 +#define WMAC0_MCMN_R1_MAC_PCU_DIAG_SW__ACCEPT_NON_V0___M 0x00000004 +#define WMAC0_MCMN_R1_MAC_PCU_DIAG_SW__ACCEPT_NON_V0___S 2 +#define WMAC0_MCMN_R1_MAC_PCU_DIAG_SW__HALT_RX___M 0x00000002 +#define WMAC0_MCMN_R1_MAC_PCU_DIAG_SW__HALT_RX___S 1 +#define WMAC0_MCMN_R1_MAC_PCU_DIAG_SW__NO_DECRYPT___M 0x00000001 +#define WMAC0_MCMN_R1_MAC_PCU_DIAG_SW__NO_DECRYPT___S 0 +#define WMAC0_MCMN_R1_MAC_PCU_DIAG_SW___M 0x0000001F +#define WMAC0_MCMN_R1_MAC_PCU_DIAG_SW___S 0 + +#define WMAC0_MCMN_R1_MCMN_TRC_EVENTMASK_IX_0 (0x00A8A228) +#define WMAC0_MCMN_R1_MCMN_TRC_EVENTMASK_IX_0___RWC QCSR_REG_RW +#define WMAC0_MCMN_R1_MCMN_TRC_EVENTMASK_IX_0___POR 0x00000000 +#define WMAC0_MCMN_R1_MCMN_TRC_EVENTMASK_IX_0__VAL___POR 0x00000000 +#define WMAC0_MCMN_R1_MCMN_TRC_EVENTMASK_IX_0__VAL___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_MCMN_TRC_EVENTMASK_IX_0__VAL___S 0 +#define WMAC0_MCMN_R1_MCMN_TRC_EVENTMASK_IX_0___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_MCMN_TRC_EVENTMASK_IX_0___S 0 + +#define WMAC0_MCMN_R1_MCMN_TRC_EVENTMASK_IX_1 (0x00A8A22C) +#define WMAC0_MCMN_R1_MCMN_TRC_EVENTMASK_IX_1___RWC QCSR_REG_RW +#define WMAC0_MCMN_R1_MCMN_TRC_EVENTMASK_IX_1___POR 0x00000000 +#define WMAC0_MCMN_R1_MCMN_TRC_EVENTMASK_IX_1__VAL___POR 0x000 +#define WMAC0_MCMN_R1_MCMN_TRC_EVENTMASK_IX_1__VAL___M 0x00000FFF +#define WMAC0_MCMN_R1_MCMN_TRC_EVENTMASK_IX_1__VAL___S 0 +#define WMAC0_MCMN_R1_MCMN_TRC_EVENTMASK_IX_1___M 0x00000FFF +#define WMAC0_MCMN_R1_MCMN_TRC_EVENTMASK_IX_1___S 0 + +#define WMAC0_MCMN_R1_MCMN_STM_SELECT0 (0x00A8A23C) +#define WMAC0_MCMN_R1_MCMN_STM_SELECT0___RWC QCSR_REG_RW +#define WMAC0_MCMN_R1_MCMN_STM_SELECT0___POR 0x00000000 +#define WMAC0_MCMN_R1_MCMN_STM_SELECT0__VAL___POR 0x00000000 +#define WMAC0_MCMN_R1_MCMN_STM_SELECT0__VAL___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_MCMN_STM_SELECT0__VAL___S 0 +#define WMAC0_MCMN_R1_MCMN_STM_SELECT0___M 0xFFFFFFFF +#define WMAC0_MCMN_R1_MCMN_STM_SELECT0___S 0 + +#define WMAC0_RXPCU_R0_BSSID2_L32 (0x00A8C000) +#define WMAC0_RXPCU_R0_BSSID2_L32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_BSSID2_L32___POR 0x00000000 +#define WMAC0_RXPCU_R0_BSSID2_L32__ADDR___POR 0x00000000 +#define WMAC0_RXPCU_R0_BSSID2_L32__ADDR___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_BSSID2_L32__ADDR___S 0 +#define WMAC0_RXPCU_R0_BSSID2_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_BSSID2_L32___S 0 + +#define WMAC0_RXPCU_R0_BSSID2_U16 (0x00A8C004) +#define WMAC0_RXPCU_R0_BSSID2_U16___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_BSSID2_U16___POR 0x00000000 +#define WMAC0_RXPCU_R0_BSSID2_U16__TRANSMITTED_BSSID___POR 0x0 +#define WMAC0_RXPCU_R0_BSSID2_U16__AID___POR 0x0000 +#define WMAC0_RXPCU_R0_BSSID2_U16__ADDR___POR 0x0000 +#define WMAC0_RXPCU_R0_BSSID2_U16__TRANSMITTED_BSSID___M 0x40000000 +#define WMAC0_RXPCU_R0_BSSID2_U16__TRANSMITTED_BSSID___S 30 +#define WMAC0_RXPCU_R0_BSSID2_U16__AID___M 0x3FFE0000 +#define WMAC0_RXPCU_R0_BSSID2_U16__AID___S 17 +#define WMAC0_RXPCU_R0_BSSID2_U16__ADDR___M 0x0000FFFF +#define WMAC0_RXPCU_R0_BSSID2_U16__ADDR___S 0 +#define WMAC0_RXPCU_R0_BSSID2_U16___M 0x7FFEFFFF +#define WMAC0_RXPCU_R0_BSSID2_U16___S 0 + +#define WMAC0_RXPCU_R0_BSSID3_L32 (0x00A8C008) +#define WMAC0_RXPCU_R0_BSSID3_L32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_BSSID3_L32___POR 0x00000000 +#define WMAC0_RXPCU_R0_BSSID3_L32__ADDR___POR 0x00000000 +#define WMAC0_RXPCU_R0_BSSID3_L32__ADDR___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_BSSID3_L32__ADDR___S 0 +#define WMAC0_RXPCU_R0_BSSID3_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_BSSID3_L32___S 0 + +#define WMAC0_RXPCU_R0_BSSID3_U16 (0x00A8C00C) +#define WMAC0_RXPCU_R0_BSSID3_U16___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_BSSID3_U16___POR 0x00000000 +#define WMAC0_RXPCU_R0_BSSID3_U16__AID___POR 0x0000 +#define WMAC0_RXPCU_R0_BSSID3_U16__ADDR___POR 0x0000 +#define WMAC0_RXPCU_R0_BSSID3_U16__AID___M 0x3FFE0000 +#define WMAC0_RXPCU_R0_BSSID3_U16__AID___S 17 +#define WMAC0_RXPCU_R0_BSSID3_U16__ADDR___M 0x0000FFFF +#define WMAC0_RXPCU_R0_BSSID3_U16__ADDR___S 0 +#define WMAC0_RXPCU_R0_BSSID3_U16___M 0x3FFEFFFF +#define WMAC0_RXPCU_R0_BSSID3_U16___S 0 + +#define WMAC0_RXPCU_R0_BSSID4_L32 (0x00A8C010) +#define WMAC0_RXPCU_R0_BSSID4_L32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_BSSID4_L32___POR 0x00000000 +#define WMAC0_RXPCU_R0_BSSID4_L32__ADDR___POR 0x00000000 +#define WMAC0_RXPCU_R0_BSSID4_L32__ADDR___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_BSSID4_L32__ADDR___S 0 +#define WMAC0_RXPCU_R0_BSSID4_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_BSSID4_L32___S 0 + +#define WMAC0_RXPCU_R0_BSSID4_U16 (0x00A8C014) +#define WMAC0_RXPCU_R0_BSSID4_U16___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_BSSID4_U16___POR 0x00000000 +#define WMAC0_RXPCU_R0_BSSID4_U16__AID___POR 0x0000 +#define WMAC0_RXPCU_R0_BSSID4_U16__ADDR___POR 0x0000 +#define WMAC0_RXPCU_R0_BSSID4_U16__AID___M 0x3FFE0000 +#define WMAC0_RXPCU_R0_BSSID4_U16__AID___S 17 +#define WMAC0_RXPCU_R0_BSSID4_U16__ADDR___M 0x0000FFFF +#define WMAC0_RXPCU_R0_BSSID4_U16__ADDR___S 0 +#define WMAC0_RXPCU_R0_BSSID4_U16___M 0x3FFEFFFF +#define WMAC0_RXPCU_R0_BSSID4_U16___S 0 + +#define WMAC0_RXPCU_R0_BSSID5_L32 (0x00A8C018) +#define WMAC0_RXPCU_R0_BSSID5_L32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_BSSID5_L32___POR 0x00000000 +#define WMAC0_RXPCU_R0_BSSID5_L32__ADDR___POR 0x00000000 +#define WMAC0_RXPCU_R0_BSSID5_L32__ADDR___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_BSSID5_L32__ADDR___S 0 +#define WMAC0_RXPCU_R0_BSSID5_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_BSSID5_L32___S 0 + +#define WMAC0_RXPCU_R0_BSSID5_U16 (0x00A8C01C) +#define WMAC0_RXPCU_R0_BSSID5_U16___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_BSSID5_U16___POR 0x00000000 +#define WMAC0_RXPCU_R0_BSSID5_U16__AID___POR 0x0000 +#define WMAC0_RXPCU_R0_BSSID5_U16__ADDR___POR 0x0000 +#define WMAC0_RXPCU_R0_BSSID5_U16__AID___M 0x3FFE0000 +#define WMAC0_RXPCU_R0_BSSID5_U16__AID___S 17 +#define WMAC0_RXPCU_R0_BSSID5_U16__ADDR___M 0x0000FFFF +#define WMAC0_RXPCU_R0_BSSID5_U16__ADDR___S 0 +#define WMAC0_RXPCU_R0_BSSID5_U16___M 0x3FFEFFFF +#define WMAC0_RXPCU_R0_BSSID5_U16___S 0 + +#define WMAC0_RXPCU_R0_BSSID6_L32 (0x00A8C020) +#define WMAC0_RXPCU_R0_BSSID6_L32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_BSSID6_L32___POR 0x00000000 +#define WMAC0_RXPCU_R0_BSSID6_L32__ADDR___POR 0x00000000 +#define WMAC0_RXPCU_R0_BSSID6_L32__ADDR___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_BSSID6_L32__ADDR___S 0 +#define WMAC0_RXPCU_R0_BSSID6_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_BSSID6_L32___S 0 + +#define WMAC0_RXPCU_R0_BSSID6_U16 (0x00A8C024) +#define WMAC0_RXPCU_R0_BSSID6_U16___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_BSSID6_U16___POR 0x00000000 +#define WMAC0_RXPCU_R0_BSSID6_U16__AID___POR 0x0000 +#define WMAC0_RXPCU_R0_BSSID6_U16__ADDR___POR 0x0000 +#define WMAC0_RXPCU_R0_BSSID6_U16__AID___M 0x3FFE0000 +#define WMAC0_RXPCU_R0_BSSID6_U16__AID___S 17 +#define WMAC0_RXPCU_R0_BSSID6_U16__ADDR___M 0x0000FFFF +#define WMAC0_RXPCU_R0_BSSID6_U16__ADDR___S 0 +#define WMAC0_RXPCU_R0_BSSID6_U16___M 0x3FFEFFFF +#define WMAC0_RXPCU_R0_BSSID6_U16___S 0 + +#define WMAC0_RXPCU_R0_BSSID7_L32 (0x00A8C028) +#define WMAC0_RXPCU_R0_BSSID7_L32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_BSSID7_L32___POR 0x00000000 +#define WMAC0_RXPCU_R0_BSSID7_L32__ADDR___POR 0x00000000 +#define WMAC0_RXPCU_R0_BSSID7_L32__ADDR___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_BSSID7_L32__ADDR___S 0 +#define WMAC0_RXPCU_R0_BSSID7_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_BSSID7_L32___S 0 + +#define WMAC0_RXPCU_R0_BSSID7_U16 (0x00A8C02C) +#define WMAC0_RXPCU_R0_BSSID7_U16___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_BSSID7_U16___POR 0x00000000 +#define WMAC0_RXPCU_R0_BSSID7_U16__AID___POR 0x0000 +#define WMAC0_RXPCU_R0_BSSID7_U16__ADDR___POR 0x0000 +#define WMAC0_RXPCU_R0_BSSID7_U16__AID___M 0x3FFE0000 +#define WMAC0_RXPCU_R0_BSSID7_U16__AID___S 17 +#define WMAC0_RXPCU_R0_BSSID7_U16__ADDR___M 0x0000FFFF +#define WMAC0_RXPCU_R0_BSSID7_U16__ADDR___S 0 +#define WMAC0_RXPCU_R0_BSSID7_U16___M 0x3FFEFFFF +#define WMAC0_RXPCU_R0_BSSID7_U16___S 0 + +#define WMAC0_RXPCU_R0_BSSID8_L32 (0x00A8C030) +#define WMAC0_RXPCU_R0_BSSID8_L32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_BSSID8_L32___POR 0x00000000 +#define WMAC0_RXPCU_R0_BSSID8_L32__ADDR___POR 0x00000000 +#define WMAC0_RXPCU_R0_BSSID8_L32__ADDR___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_BSSID8_L32__ADDR___S 0 +#define WMAC0_RXPCU_R0_BSSID8_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_BSSID8_L32___S 0 + +#define WMAC0_RXPCU_R0_BSSID8_U16 (0x00A8C034) +#define WMAC0_RXPCU_R0_BSSID8_U16___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_BSSID8_U16___POR 0x00000000 +#define WMAC0_RXPCU_R0_BSSID8_U16__AID___POR 0x0000 +#define WMAC0_RXPCU_R0_BSSID8_U16__ADDR___POR 0x0000 +#define WMAC0_RXPCU_R0_BSSID8_U16__AID___M 0x3FFE0000 +#define WMAC0_RXPCU_R0_BSSID8_U16__AID___S 17 +#define WMAC0_RXPCU_R0_BSSID8_U16__ADDR___M 0x0000FFFF +#define WMAC0_RXPCU_R0_BSSID8_U16__ADDR___S 0 +#define WMAC0_RXPCU_R0_BSSID8_U16___M 0x3FFEFFFF +#define WMAC0_RXPCU_R0_BSSID8_U16___S 0 + +#define WMAC0_RXPCU_R0_STA_ADDR2_L32 (0x00A8C038) +#define WMAC0_RXPCU_R0_STA_ADDR2_L32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_STA_ADDR2_L32___POR 0x00000000 +#define WMAC0_RXPCU_R0_STA_ADDR2_L32__ADDR_31_0___POR 0x00000000 +#define WMAC0_RXPCU_R0_STA_ADDR2_L32__ADDR_31_0___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_STA_ADDR2_L32__ADDR_31_0___S 0 +#define WMAC0_RXPCU_R0_STA_ADDR2_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_STA_ADDR2_L32___S 0 + +#define WMAC0_RXPCU_R0_STA_ADDR2_U16 (0x00A8C03C) +#define WMAC0_RXPCU_R0_STA_ADDR2_U16___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_STA_ADDR2_U16___POR 0x00000000 +#define WMAC0_RXPCU_R0_STA_ADDR2_U16__STA_AP___POR 0x0 +#define WMAC0_RXPCU_R0_STA_ADDR2_U16__ADDR_47_32___POR 0x0000 +#define WMAC0_RXPCU_R0_STA_ADDR2_U16__STA_AP___M 0x80000000 +#define WMAC0_RXPCU_R0_STA_ADDR2_U16__STA_AP___S 31 +#define WMAC0_RXPCU_R0_STA_ADDR2_U16__ADDR_47_32___M 0x0000FFFF +#define WMAC0_RXPCU_R0_STA_ADDR2_U16__ADDR_47_32___S 0 +#define WMAC0_RXPCU_R0_STA_ADDR2_U16___M 0x8000FFFF +#define WMAC0_RXPCU_R0_STA_ADDR2_U16___S 0 + +#define WMAC0_RXPCU_R0_STA_ADDR3_L32 (0x00A8C040) +#define WMAC0_RXPCU_R0_STA_ADDR3_L32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_STA_ADDR3_L32___POR 0x00000000 +#define WMAC0_RXPCU_R0_STA_ADDR3_L32__ADDR_31_0___POR 0x00000000 +#define WMAC0_RXPCU_R0_STA_ADDR3_L32__ADDR_31_0___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_STA_ADDR3_L32__ADDR_31_0___S 0 +#define WMAC0_RXPCU_R0_STA_ADDR3_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_STA_ADDR3_L32___S 0 + +#define WMAC0_RXPCU_R0_STA_ADDR3_U16 (0x00A8C044) +#define WMAC0_RXPCU_R0_STA_ADDR3_U16___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_STA_ADDR3_U16___POR 0x00000000 +#define WMAC0_RXPCU_R0_STA_ADDR3_U16__STA_AP___POR 0x0 +#define WMAC0_RXPCU_R0_STA_ADDR3_U16__ADDR_47_32___POR 0x0000 +#define WMAC0_RXPCU_R0_STA_ADDR3_U16__STA_AP___M 0x80000000 +#define WMAC0_RXPCU_R0_STA_ADDR3_U16__STA_AP___S 31 +#define WMAC0_RXPCU_R0_STA_ADDR3_U16__ADDR_47_32___M 0x0000FFFF +#define WMAC0_RXPCU_R0_STA_ADDR3_U16__ADDR_47_32___S 0 +#define WMAC0_RXPCU_R0_STA_ADDR3_U16___M 0x8000FFFF +#define WMAC0_RXPCU_R0_STA_ADDR3_U16___S 0 + +#define WMAC0_RXPCU_R0_STA_ADDR4_L32 (0x00A8C048) +#define WMAC0_RXPCU_R0_STA_ADDR4_L32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_STA_ADDR4_L32___POR 0x00000000 +#define WMAC0_RXPCU_R0_STA_ADDR4_L32__ADDR_31_0___POR 0x00000000 +#define WMAC0_RXPCU_R0_STA_ADDR4_L32__ADDR_31_0___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_STA_ADDR4_L32__ADDR_31_0___S 0 +#define WMAC0_RXPCU_R0_STA_ADDR4_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_STA_ADDR4_L32___S 0 + +#define WMAC0_RXPCU_R0_STA_ADDR4_U16 (0x00A8C04C) +#define WMAC0_RXPCU_R0_STA_ADDR4_U16___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_STA_ADDR4_U16___POR 0x00000000 +#define WMAC0_RXPCU_R0_STA_ADDR4_U16__STA_AP___POR 0x0 +#define WMAC0_RXPCU_R0_STA_ADDR4_U16__ADDR_47_32___POR 0x0000 +#define WMAC0_RXPCU_R0_STA_ADDR4_U16__STA_AP___M 0x80000000 +#define WMAC0_RXPCU_R0_STA_ADDR4_U16__STA_AP___S 31 +#define WMAC0_RXPCU_R0_STA_ADDR4_U16__ADDR_47_32___M 0x0000FFFF +#define WMAC0_RXPCU_R0_STA_ADDR4_U16__ADDR_47_32___S 0 +#define WMAC0_RXPCU_R0_STA_ADDR4_U16___M 0x8000FFFF +#define WMAC0_RXPCU_R0_STA_ADDR4_U16___S 0 + +#define WMAC0_RXPCU_R0_ADDR4_MASK_L32 (0x00A8C050) +#define WMAC0_RXPCU_R0_ADDR4_MASK_L32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_ADDR4_MASK_L32___POR 0xFFFFFFFF +#define WMAC0_RXPCU_R0_ADDR4_MASK_L32__VALUE___POR 0xFFFFFFFF +#define WMAC0_RXPCU_R0_ADDR4_MASK_L32__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_ADDR4_MASK_L32__VALUE___S 0 +#define WMAC0_RXPCU_R0_ADDR4_MASK_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_ADDR4_MASK_L32___S 0 + +#define WMAC0_RXPCU_R0_ADDR4_MASK_U16 (0x00A8C054) +#define WMAC0_RXPCU_R0_ADDR4_MASK_U16___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_ADDR4_MASK_U16___POR 0x0000FFFF +#define WMAC0_RXPCU_R0_ADDR4_MASK_U16__VALUE___POR 0xFFFF +#define WMAC0_RXPCU_R0_ADDR4_MASK_U16__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R0_ADDR4_MASK_U16__VALUE___S 0 +#define WMAC0_RXPCU_R0_ADDR4_MASK_U16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_ADDR4_MASK_U16___S 0 + +#define WMAC0_RXPCU_R0_HE_BSS1 (0x00A8C058) +#define WMAC0_RXPCU_R0_HE_BSS1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_HE_BSS1___POR 0x00000000 +#define WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_4_EN___POR 0x0 +#define WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_4_VALUE___POR 0x00 +#define WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_3_EN___POR 0x0 +#define WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_3_VALUE___POR 0x00 +#define WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_2_EN___POR 0x0 +#define WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_2_VALUE___POR 0x00 +#define WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_1_EN___POR 0x0 +#define WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_1_VALUE___POR 0x00 +#define WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_4_EN___M 0x40000000 +#define WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_4_EN___S 30 +#define WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_4_VALUE___M 0x3F000000 +#define WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_4_VALUE___S 24 +#define WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_3_EN___M 0x00400000 +#define WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_3_EN___S 22 +#define WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_3_VALUE___M 0x003F0000 +#define WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_3_VALUE___S 16 +#define WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_2_EN___M 0x00004000 +#define WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_2_EN___S 14 +#define WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_2_VALUE___M 0x00003F00 +#define WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_2_VALUE___S 8 +#define WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_1_EN___M 0x00000040 +#define WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_1_EN___S 6 +#define WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_1_VALUE___M 0x0000003F +#define WMAC0_RXPCU_R0_HE_BSS1__BSS_COLOR_1_VALUE___S 0 +#define WMAC0_RXPCU_R0_HE_BSS1___M 0x7F7F7F7F +#define WMAC0_RXPCU_R0_HE_BSS1___S 0 + +#define WMAC0_RXPCU_R0_HE_BSS2 (0x00A8C05C) +#define WMAC0_RXPCU_R0_HE_BSS2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_HE_BSS2___POR 0x00000000 +#define WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_8_EN___POR 0x0 +#define WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_8_VALUE___POR 0x00 +#define WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_7_EN___POR 0x0 +#define WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_7_VALUE___POR 0x00 +#define WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_6_EN___POR 0x0 +#define WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_6_VALUE___POR 0x00 +#define WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_5_EN___POR 0x0 +#define WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_5_VALUE___POR 0x00 +#define WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_8_EN___M 0x40000000 +#define WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_8_EN___S 30 +#define WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_8_VALUE___M 0x3F000000 +#define WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_8_VALUE___S 24 +#define WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_7_EN___M 0x00400000 +#define WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_7_EN___S 22 +#define WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_7_VALUE___M 0x003F0000 +#define WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_7_VALUE___S 16 +#define WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_6_EN___M 0x00004000 +#define WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_6_EN___S 14 +#define WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_6_VALUE___M 0x00003F00 +#define WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_6_VALUE___S 8 +#define WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_5_EN___M 0x00000040 +#define WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_5_EN___S 6 +#define WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_5_VALUE___M 0x0000003F +#define WMAC0_RXPCU_R0_HE_BSS2__BSS_COLOR_5_VALUE___S 0 +#define WMAC0_RXPCU_R0_HE_BSS2___M 0x7F7F7F7F +#define WMAC0_RXPCU_R0_HE_BSS2___S 0 + +#define WMAC0_RXPCU_R0_HE_BSS3 (0x00A8C060) +#define WMAC0_RXPCU_R0_HE_BSS3___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_HE_BSS3___POR 0x00000040 +#define WMAC0_RXPCU_R0_HE_BSS3__TRIGGER_DETAILS_COLOR_DIS_EN___POR 0x0 +#define WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_8_DIS___POR 0x0 +#define WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_7_DIS___POR 0x0 +#define WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_6_DIS___POR 0x0 +#define WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_5_DIS___POR 0x0 +#define WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_4_DIS___POR 0x0 +#define WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_3_DIS___POR 0x0 +#define WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_2_DIS___POR 0x0 +#define WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_1_DIS___POR 0x0 +#define WMAC0_RXPCU_R0_HE_BSS3__INBSS_NAV_OPT___POR 0x0 +#define WMAC0_RXPCU_R0_HE_BSS3__COLOR_FETCH_ASSO___POR 0x1 +#define WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_UASSO_VALUE___POR 0x00 +#define WMAC0_RXPCU_R0_HE_BSS3__TRIGGER_DETAILS_COLOR_DIS_EN___M 0x00020000 +#define WMAC0_RXPCU_R0_HE_BSS3__TRIGGER_DETAILS_COLOR_DIS_EN___S 17 +#define WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_8_DIS___M 0x00010000 +#define WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_8_DIS___S 16 +#define WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_7_DIS___M 0x00008000 +#define WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_7_DIS___S 15 +#define WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_6_DIS___M 0x00004000 +#define WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_6_DIS___S 14 +#define WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_5_DIS___M 0x00002000 +#define WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_5_DIS___S 13 +#define WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_4_DIS___M 0x00001000 +#define WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_4_DIS___S 12 +#define WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_3_DIS___M 0x00000800 +#define WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_3_DIS___S 11 +#define WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_2_DIS___M 0x00000400 +#define WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_2_DIS___S 10 +#define WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_1_DIS___M 0x00000200 +#define WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_1_DIS___S 9 +#define WMAC0_RXPCU_R0_HE_BSS3__INBSS_NAV_OPT___M 0x00000180 +#define WMAC0_RXPCU_R0_HE_BSS3__INBSS_NAV_OPT___S 7 +#define WMAC0_RXPCU_R0_HE_BSS3__COLOR_FETCH_ASSO___M 0x00000040 +#define WMAC0_RXPCU_R0_HE_BSS3__COLOR_FETCH_ASSO___S 6 +#define WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_UASSO_VALUE___M 0x0000003F +#define WMAC0_RXPCU_R0_HE_BSS3__BSS_COLOR_UASSO_VALUE___S 0 +#define WMAC0_RXPCU_R0_HE_BSS3___M 0x0003FFFF +#define WMAC0_RXPCU_R0_HE_BSS3___S 0 + +#define WMAC0_RXPCU_R0_RFF_MCAST_FILTER_L32 (0x00A8C064) +#define WMAC0_RXPCU_R0_RFF_MCAST_FILTER_L32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_MCAST_FILTER_L32___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_MCAST_FILTER_L32__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_MCAST_FILTER_L32__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_MCAST_FILTER_L32__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_MCAST_FILTER_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_MCAST_FILTER_L32___S 0 + +#define WMAC0_RXPCU_R0_RFF_MCAST_FILTER_U32 (0x00A8C068) +#define WMAC0_RXPCU_R0_RFF_MCAST_FILTER_U32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_MCAST_FILTER_U32___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_MCAST_FILTER_U32__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_MCAST_FILTER_U32__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_MCAST_FILTER_U32__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_MCAST_FILTER_U32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_MCAST_FILTER_U32___S 0 + +#define WMAC0_RXPCU_R0_RFF_RX_FILTER (0x00A8C06C) +#define WMAC0_RXPCU_R0_RFF_RX_FILTER___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_RX_FILTER___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__BSSID_BASED_MULTICAST___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__PHY_DATA___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__MY_BEACON2___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__GENERIC_FILTER___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__GENERIC_FTYPE___POR 0x00 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__FROM_TO_DS___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__CONTROL_WRAPPER___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__MY_MGMT_ACTION_MCAST___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__GROUP_PUBLIC_ACTION___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__ANY_MGMT_ACTION_MCAST___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__MCAST_BCAST_ALL___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__PS_POLL___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__DISABLE_CBF_FRAME___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__UNCOMPRESSED_BA_BAR___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__COMPRESSED_BA___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__COMPRESSED_BAR___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__MY_BEACON___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__ASSOC_BEACON___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__PROBE_REQ___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__TRIGGER_DIRECT___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__TRIGGER___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__BEACON___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__CONTROL___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__BROADCAST___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__MULTICAST___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__UNICAST___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__BSSID_BASED_MULTICAST___M 0x80000000 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__BSSID_BASED_MULTICAST___S 31 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__PHY_DATA___M 0x40000000 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__PHY_DATA___S 30 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__MY_BEACON2___M 0x20000000 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__MY_BEACON2___S 29 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__GENERIC_FILTER___M 0x18000000 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__GENERIC_FILTER___S 27 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__GENERIC_FTYPE___M 0x07E00000 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__GENERIC_FTYPE___S 21 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__FROM_TO_DS___M 0x00100000 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__FROM_TO_DS___S 20 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__CONTROL_WRAPPER___M 0x00080000 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__CONTROL_WRAPPER___S 19 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__MY_MGMT_ACTION_MCAST___M 0x00040000 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__MY_MGMT_ACTION_MCAST___S 18 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__GROUP_PUBLIC_ACTION___M 0x00020000 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__GROUP_PUBLIC_ACTION___S 17 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__ANY_MGMT_ACTION_MCAST___M 0x00010000 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__ANY_MGMT_ACTION_MCAST___S 16 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__MCAST_BCAST_ALL___M 0x00008000 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__MCAST_BCAST_ALL___S 15 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__PS_POLL___M 0x00004000 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__PS_POLL___S 14 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__DISABLE_CBF_FRAME___M 0x00002000 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__DISABLE_CBF_FRAME___S 13 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__UNCOMPRESSED_BA_BAR___M 0x00001000 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__UNCOMPRESSED_BA_BAR___S 12 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__COMPRESSED_BA___M 0x00000800 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__COMPRESSED_BA___S 11 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__COMPRESSED_BAR___M 0x00000400 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__COMPRESSED_BAR___S 10 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__MY_BEACON___M 0x00000200 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__MY_BEACON___S 9 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__ASSOC_BEACON___M 0x00000100 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__ASSOC_BEACON___S 8 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__PROBE_REQ___M 0x00000080 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__PROBE_REQ___S 7 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__TRIGGER_DIRECT___M 0x00000040 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__TRIGGER_DIRECT___S 6 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__TRIGGER___M 0x00000020 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__TRIGGER___S 5 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__BEACON___M 0x00000010 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__BEACON___S 4 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__CONTROL___M 0x00000008 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__CONTROL___S 3 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__BROADCAST___M 0x00000004 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__BROADCAST___S 2 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__MULTICAST___M 0x00000002 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__MULTICAST___S 1 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__UNICAST___M 0x00000001 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER__UNICAST___S 0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_RX_FILTER___S 0 + +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2 (0x00A8C070) +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__GENERIC_FTYPE3___POR 0x00 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__GENERIC_FTYPE2___POR 0x00 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__MY_11V_TIM_FCS_PASS___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__EBT_PASS___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__MY_BEACON2_FCS_PASS___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__MY_BEACON_FCS_PASS___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__FTM___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__CTS_DIRECTED___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__RTS_DIRECTED___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__BRPOLL_DIRECTED___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__BRPOLL___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__NDPA___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__BSSID_BASED_UNICAST___POR 0x00 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__GENERIC_FTYPE3___M 0xFC000000 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__GENERIC_FTYPE3___S 26 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__GENERIC_FTYPE2___M 0x03F00000 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__GENERIC_FTYPE2___S 20 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__MY_11V_TIM_FCS_PASS___M 0x00080000 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__MY_11V_TIM_FCS_PASS___S 19 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__EBT_PASS___M 0x00040000 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__EBT_PASS___S 18 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__MY_BEACON2_FCS_PASS___M 0x00030000 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__MY_BEACON2_FCS_PASS___S 16 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__MY_BEACON_FCS_PASS___M 0x0000C000 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__MY_BEACON_FCS_PASS___S 14 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__FTM___M 0x00002000 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__FTM___S 13 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__CTS_DIRECTED___M 0x00001000 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__CTS_DIRECTED___S 12 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__RTS_DIRECTED___M 0x00000800 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__RTS_DIRECTED___S 11 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__BRPOLL_DIRECTED___M 0x00000400 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__BRPOLL_DIRECTED___S 10 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__BRPOLL___M 0x00000200 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__BRPOLL___S 9 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__NDPA___M 0x00000100 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__NDPA___S 8 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__BSSID_BASED_UNICAST___M 0x000000FF +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2__BSSID_BASED_UNICAST___S 0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_RX_FILTER2___S 0 + +#define WMAC0_RXPCU_R0_PHY_DATA_LENGTH_THRESH (0x00A8C074) +#define WMAC0_RXPCU_R0_PHY_DATA_LENGTH_THRESH___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_PHY_DATA_LENGTH_THRESH___POR 0x00000064 +#define WMAC0_RXPCU_R0_PHY_DATA_LENGTH_THRESH__ENABLE___POR 0x0 +#define WMAC0_RXPCU_R0_PHY_DATA_LENGTH_THRESH__VALUE___POR 0x0064 +#define WMAC0_RXPCU_R0_PHY_DATA_LENGTH_THRESH__ENABLE___M 0x00010000 +#define WMAC0_RXPCU_R0_PHY_DATA_LENGTH_THRESH__ENABLE___S 16 +#define WMAC0_RXPCU_R0_PHY_DATA_LENGTH_THRESH__VALUE___M 0x00003FFF +#define WMAC0_RXPCU_R0_PHY_DATA_LENGTH_THRESH__VALUE___S 0 +#define WMAC0_RXPCU_R0_PHY_DATA_LENGTH_THRESH___M 0x00013FFF +#define WMAC0_RXPCU_R0_PHY_DATA_LENGTH_THRESH___S 0 + +#define WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL (0x00A8C078) +#define WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL__RESET___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL__WEIGHT___POR 0x00 +#define WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL__RSSI_HIGH_THRESH___POR 0x00 +#define WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL__MISS_THRESH___POR 0x00 +#define WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL__RSSI_LOW_THRESH___POR 0x00 +#define WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL__RESET___M 0x20000000 +#define WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL__RESET___S 29 +#define WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL__WEIGHT___M 0x1F000000 +#define WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL__WEIGHT___S 24 +#define WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL__RSSI_HIGH_THRESH___M 0x00FF0000 +#define WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL__RSSI_HIGH_THRESH___S 16 +#define WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL__MISS_THRESH___M 0x0000FF00 +#define WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL__MISS_THRESH___S 8 +#define WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL__RSSI_LOW_THRESH___M 0x000000FF +#define WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL__RSSI_LOW_THRESH___S 0 +#define WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL___M 0x3FFFFFFF +#define WMAC0_RXPCU_R0_RFF_BCN_RSSI_CTL___S 0 + +#define WMAC0_RXPCU_R0_BCN_RSSI_CTL2 (0x00A8C07C) +#define WMAC0_RXPCU_R0_BCN_RSSI_CTL2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_BCN_RSSI_CTL2___POR 0x00000000 +#define WMAC0_RXPCU_R0_BCN_RSSI_CTL2__RESET2___POR 0x0 +#define WMAC0_RXPCU_R0_BCN_RSSI_CTL2__RSSI2_HIGH_THRESH___POR 0x00 +#define WMAC0_RXPCU_R0_BCN_RSSI_CTL2__RSSI2_LOW_THRESH___POR 0x00 +#define WMAC0_RXPCU_R0_BCN_RSSI_CTL2__RESET2___M 0x20000000 +#define WMAC0_RXPCU_R0_BCN_RSSI_CTL2__RESET2___S 29 +#define WMAC0_RXPCU_R0_BCN_RSSI_CTL2__RSSI2_HIGH_THRESH___M 0x00FF0000 +#define WMAC0_RXPCU_R0_BCN_RSSI_CTL2__RSSI2_HIGH_THRESH___S 16 +#define WMAC0_RXPCU_R0_BCN_RSSI_CTL2__RSSI2_LOW_THRESH___M 0x000000FF +#define WMAC0_RXPCU_R0_BCN_RSSI_CTL2__RSSI2_LOW_THRESH___S 0 +#define WMAC0_RXPCU_R0_BCN_RSSI_CTL2___M 0x20FF00FF +#define WMAC0_RXPCU_R0_BCN_RSSI_CTL2___S 0 + +#define WMAC0_RXPCU_R0_RFF_BCN_RSSI_AVE (0x00A8C080) +#define WMAC0_RXPCU_R0_RFF_BCN_RSSI_AVE___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_BCN_RSSI_AVE___POR 0x08000800 +#define WMAC0_RXPCU_R0_RFF_BCN_RSSI_AVE__AVE_VALUE2___POR 0x800 +#define WMAC0_RXPCU_R0_RFF_BCN_RSSI_AVE__AVE_VALUE___POR 0x800 +#define WMAC0_RXPCU_R0_RFF_BCN_RSSI_AVE__AVE_VALUE2___M 0x0FFF0000 +#define WMAC0_RXPCU_R0_RFF_BCN_RSSI_AVE__AVE_VALUE2___S 16 +#define WMAC0_RXPCU_R0_RFF_BCN_RSSI_AVE__AVE_VALUE___M 0x00000FFF +#define WMAC0_RXPCU_R0_RFF_BCN_RSSI_AVE__AVE_VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_BCN_RSSI_AVE___M 0x0FFF0FFF +#define WMAC0_RXPCU_R0_RFF_BCN_RSSI_AVE___S 0 + +#define WMAC0_RXPCU_R0_FILTER_RSSI_AVE (0x00A8C084) +#define WMAC0_RXPCU_R0_FILTER_RSSI_AVE___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_FILTER_RSSI_AVE___POR 0x00000580 +#define WMAC0_RXPCU_R0_FILTER_RSSI_AVE__RESET___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_RSSI_AVE__ENABLE___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT___POR 0x5 +#define WMAC0_RXPCU_R0_FILTER_RSSI_AVE__AVE_VALUE___POR 0x80 +#define WMAC0_RXPCU_R0_FILTER_RSSI_AVE__RESET___M 0x00001000 +#define WMAC0_RXPCU_R0_FILTER_RSSI_AVE__RESET___S 12 +#define WMAC0_RXPCU_R0_FILTER_RSSI_AVE__ENABLE___M 0x00000800 +#define WMAC0_RXPCU_R0_FILTER_RSSI_AVE__ENABLE___S 11 +#define WMAC0_RXPCU_R0_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT___M 0x00000700 +#define WMAC0_RXPCU_R0_FILTER_RSSI_AVE__NUM_FRAMES_EXPONENT___S 8 +#define WMAC0_RXPCU_R0_FILTER_RSSI_AVE__AVE_VALUE___M 0x000000FF +#define WMAC0_RXPCU_R0_FILTER_RSSI_AVE__AVE_VALUE___S 0 +#define WMAC0_RXPCU_R0_FILTER_RSSI_AVE___M 0x00001FFF +#define WMAC0_RXPCU_R0_FILTER_RSSI_AVE___S 0 + +#define WMAC0_RXPCU_R0_BA_BAR_CONTROL (0x00A8C088) +#define WMAC0_RXPCU_R0_BA_BAR_CONTROL___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_BA_BAR_CONTROL___POR 0x00000000 +#define WMAC0_RXPCU_R0_BA_BAR_CONTROL__FORCE_NO_MATCH___POR 0x0 +#define WMAC0_RXPCU_R0_BA_BAR_CONTROL__FORCE_NO_MATCH___M 0x00000400 +#define WMAC0_RXPCU_R0_BA_BAR_CONTROL__FORCE_NO_MATCH___S 10 +#define WMAC0_RXPCU_R0_BA_BAR_CONTROL___M 0x00000400 +#define WMAC0_RXPCU_R0_BA_BAR_CONTROL___S 10 + +#define WMAC0_RXPCU_R0_RTT_CTRL_IX0 (0x00A8C08C) +#define WMAC0_RXPCU_R0_RTT_CTRL_IX0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RTT_CTRL_IX0___POR 0x04002100 +#define WMAC0_RXPCU_R0_RTT_CTRL_IX0__FTM_CATEGORY___POR 0x04 +#define WMAC0_RXPCU_R0_RTT_CTRL_IX0__FTM_ALLOW_HT_VHT_ACK_BA___POR 0x0 +#define WMAC0_RXPCU_R0_RTT_CTRL_IX0__FTM_ACTION___POR 0x21 +#define WMAC0_RXPCU_R0_RTT_CTRL_IX0__AUTO_CLEAR___POR 0x0 +#define WMAC0_RXPCU_R0_RTT_CTRL_IX0__FREEZE_CHANNEL_CAPTURE_CLEAR___POR 0x0 +#define WMAC0_RXPCU_R0_RTT_CTRL_IX0__FTM_CATEGORY___M 0xFF000000 +#define WMAC0_RXPCU_R0_RTT_CTRL_IX0__FTM_CATEGORY___S 24 +#define WMAC0_RXPCU_R0_RTT_CTRL_IX0__FTM_ALLOW_HT_VHT_ACK_BA___M 0x00010000 +#define WMAC0_RXPCU_R0_RTT_CTRL_IX0__FTM_ALLOW_HT_VHT_ACK_BA___S 16 +#define WMAC0_RXPCU_R0_RTT_CTRL_IX0__FTM_ACTION___M 0x0000FF00 +#define WMAC0_RXPCU_R0_RTT_CTRL_IX0__FTM_ACTION___S 8 +#define WMAC0_RXPCU_R0_RTT_CTRL_IX0__AUTO_CLEAR___M 0x00000002 +#define WMAC0_RXPCU_R0_RTT_CTRL_IX0__AUTO_CLEAR___S 1 +#define WMAC0_RXPCU_R0_RTT_CTRL_IX0__FREEZE_CHANNEL_CAPTURE_CLEAR___M 0x00000001 +#define WMAC0_RXPCU_R0_RTT_CTRL_IX0__FREEZE_CHANNEL_CAPTURE_CLEAR___S 0 +#define WMAC0_RXPCU_R0_RTT_CTRL_IX0___M 0xFF01FF03 +#define WMAC0_RXPCU_R0_RTT_CTRL_IX0___S 0 + +#define WMAC0_RXPCU_R0_RTT_CTRL_IX1 (0x00A8C090) +#define WMAC0_RXPCU_R0_RTT_CTRL_IX1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RTT_CTRL_IX1___POR 0x0B000100 +#define WMAC0_RXPCU_R0_RTT_CTRL_IX1__TM_CATEGORY___POR 0x0B +#define WMAC0_RXPCU_R0_RTT_CTRL_IX1__TM_ALLOW_HT_VHT_ACK_BA___POR 0x0 +#define WMAC0_RXPCU_R0_RTT_CTRL_IX1__TM_ACTION___POR 0x01 +#define WMAC0_RXPCU_R0_RTT_CTRL_IX1__TM_CATEGORY___M 0xFF000000 +#define WMAC0_RXPCU_R0_RTT_CTRL_IX1__TM_CATEGORY___S 24 +#define WMAC0_RXPCU_R0_RTT_CTRL_IX1__TM_ALLOW_HT_VHT_ACK_BA___M 0x00010000 +#define WMAC0_RXPCU_R0_RTT_CTRL_IX1__TM_ALLOW_HT_VHT_ACK_BA___S 16 +#define WMAC0_RXPCU_R0_RTT_CTRL_IX1__TM_ACTION___M 0x0000FF00 +#define WMAC0_RXPCU_R0_RTT_CTRL_IX1__TM_ACTION___S 8 +#define WMAC0_RXPCU_R0_RTT_CTRL_IX1___M 0xFF01FF00 +#define WMAC0_RXPCU_R0_RTT_CTRL_IX1___S 8 + +#define WMAC0_RXPCU_R0_RTT_CTRL_IX2 (0x00A8C094) +#define WMAC0_RXPCU_R0_RTT_CTRL_IX2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RTT_CTRL_IX2___POR 0x00000000 +#define WMAC0_RXPCU_R0_RTT_CTRL_IX2__ACK_FILTER_WINDOW___POR 0x0000 +#define WMAC0_RXPCU_R0_RTT_CTRL_IX2__ACK_FILTER_WINDOW___M 0x0000FFFF +#define WMAC0_RXPCU_R0_RTT_CTRL_IX2__ACK_FILTER_WINDOW___S 0 +#define WMAC0_RXPCU_R0_RTT_CTRL_IX2___M 0x0000FFFF +#define WMAC0_RXPCU_R0_RTT_CTRL_IX2___S 0 + +#define WMAC0_RXPCU_R0_TXBF_CNTL (0x00A8C098) +#define WMAC0_RXPCU_R0_TXBF_CNTL___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_TXBF_CNTL___POR 0x00190002 +#define WMAC0_RXPCU_R0_TXBF_CNTL__NDP_TIMEOUT_VALUE___POR 0x19 +#define WMAC0_RXPCU_R0_TXBF_CNTL__SIFS_TIME___POR 0x00 +#define WMAC0_RXPCU_R0_TXBF_CNTL__MAX_NC_INDEX___POR 0x1 +#define WMAC0_RXPCU_R0_TXBF_CNTL__CHECK_CH_STATUS_EN___POR 0x0 +#define WMAC0_RXPCU_R0_TXBF_CNTL__NDP_TIMEOUT_VALUE___M 0x00FF0000 +#define WMAC0_RXPCU_R0_TXBF_CNTL__NDP_TIMEOUT_VALUE___S 16 +#define WMAC0_RXPCU_R0_TXBF_CNTL__SIFS_TIME___M 0x0000FF00 +#define WMAC0_RXPCU_R0_TXBF_CNTL__SIFS_TIME___S 8 +#define WMAC0_RXPCU_R0_TXBF_CNTL__MAX_NC_INDEX___M 0x0000000E +#define WMAC0_RXPCU_R0_TXBF_CNTL__MAX_NC_INDEX___S 1 +#define WMAC0_RXPCU_R0_TXBF_CNTL__CHECK_CH_STATUS_EN___M 0x00000001 +#define WMAC0_RXPCU_R0_TXBF_CNTL__CHECK_CH_STATUS_EN___S 0 +#define WMAC0_RXPCU_R0_TXBF_CNTL___M 0x00FFFF0F +#define WMAC0_RXPCU_R0_TXBF_CNTL___S 0 + +#define WMAC0_RXPCU_R0_SEC_CHANNEL_RX_PIFS_CNT (0x00A8C09C) +#define WMAC0_RXPCU_R0_SEC_CHANNEL_RX_PIFS_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SEC_CHANNEL_RX_PIFS_CNT___POR 0x1F400FA0 +#define WMAC0_RXPCU_R0_SEC_CHANNEL_RX_PIFS_CNT__ACK_VALUE___POR 0x1F40 +#define WMAC0_RXPCU_R0_SEC_CHANNEL_RX_PIFS_CNT__VALUE___POR 0x0FA0 +#define WMAC0_RXPCU_R0_SEC_CHANNEL_RX_PIFS_CNT__ACK_VALUE___M 0xFFFF0000 +#define WMAC0_RXPCU_R0_SEC_CHANNEL_RX_PIFS_CNT__ACK_VALUE___S 16 +#define WMAC0_RXPCU_R0_SEC_CHANNEL_RX_PIFS_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R0_SEC_CHANNEL_RX_PIFS_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R0_SEC_CHANNEL_RX_PIFS_CNT___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SEC_CHANNEL_RX_PIFS_CNT___S 0 + +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC20 (0x00A8C0A0) +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC20___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC20___POR 0x00000077 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC20__SEC_CLR_MON_SEL___POR 0x0 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC20__SEC_CLR_MON_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC20__EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC20__CNT___POR 0x77 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC20__SEC_CLR_MON_SEL___M 0x00000400 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC20__SEC_CLR_MON_SEL___S 10 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC20__SEC_CLR_MON_EN___M 0x00000200 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC20__SEC_CLR_MON_EN___S 9 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC20__EN___M 0x00000100 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC20__EN___S 8 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC20__CNT___M 0x000000FF +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC20__CNT___S 0 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC20___M 0x000007FF +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC20___S 0 + +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC40 (0x00A8C0A4) +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC40___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC40___POR 0x00000077 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC40__SEC_CLR_MON_SEL___POR 0x0 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC40__SEC_CLR_MON_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC40__EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC40__CNT___POR 0x77 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC40__SEC_CLR_MON_SEL___M 0x00000400 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC40__SEC_CLR_MON_SEL___S 10 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC40__SEC_CLR_MON_EN___M 0x00000200 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC40__SEC_CLR_MON_EN___S 9 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC40__EN___M 0x00000100 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC40__EN___S 8 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC40__CNT___M 0x000000FF +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC40__CNT___S 0 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC40___M 0x000007FF +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC40___S 0 + +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC80 (0x00A8C0A8) +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC80___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC80___POR 0x00000077 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC80__SEC_CLR_MON_SEL___POR 0x0 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC80__SEC_CLR_MON_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC80__EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC80__CNT___POR 0x77 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC80__SEC_CLR_MON_SEL___M 0x00000400 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC80__SEC_CLR_MON_SEL___S 10 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC80__SEC_CLR_MON_EN___M 0x00000200 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC80__SEC_CLR_MON_EN___S 9 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC80__EN___M 0x00000100 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC80__EN___S 8 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC80__CNT___M 0x000000FF +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC80__CNT___S 0 +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC80___M 0x000007FF +#define WMAC0_RXPCU_R0_RX_CLEAR_PHY_DLY_SEC80___S 0 + +#define WMAC0_RXPCU_R0_PROXY_STA (0x00A8C0AC) +#define WMAC0_RXPCU_R0_PROXY_STA___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_PROXY_STA___POR 0x00000000 +#define WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID8___POR 0x0 +#define WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID7___POR 0x0 +#define WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID6___POR 0x0 +#define WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID5___POR 0x0 +#define WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID4___POR 0x0 +#define WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID3___POR 0x0 +#define WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID2___POR 0x0 +#define WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID1___POR 0x0 +#define WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID8___POR 0x0 +#define WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID7___POR 0x0 +#define WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID6___POR 0x0 +#define WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID5___POR 0x0 +#define WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID4___POR 0x0 +#define WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID3___POR 0x0 +#define WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID2___POR 0x0 +#define WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID1___POR 0x0 +#define WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID8___M 0x00008000 +#define WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID8___S 15 +#define WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID7___M 0x00004000 +#define WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID7___S 14 +#define WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID6___M 0x00002000 +#define WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID6___S 13 +#define WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID5___M 0x00001000 +#define WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID5___S 12 +#define WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID4___M 0x00000800 +#define WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID4___S 11 +#define WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID3___M 0x00000400 +#define WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID3___S 10 +#define WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID2___M 0x00000200 +#define WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID2___S 9 +#define WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID1___M 0x00000100 +#define WMAC0_RXPCU_R0_PROXY_STA__INVALID_ENTRY_NO_ACK_BSSID1___S 8 +#define WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID8___M 0x00000080 +#define WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID8___S 7 +#define WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID7___M 0x00000040 +#define WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID7___S 6 +#define WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID6___M 0x00000020 +#define WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID6___S 5 +#define WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID5___M 0x00000010 +#define WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID5___S 4 +#define WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID4___M 0x00000008 +#define WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID4___S 3 +#define WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID3___M 0x00000004 +#define WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID3___S 2 +#define WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID2___M 0x00000002 +#define WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID2___S 1 +#define WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID1___M 0x00000001 +#define WMAC0_RXPCU_R0_PROXY_STA__PROXY_STA_AD1_SEARCH_BSSID1___S 0 +#define WMAC0_RXPCU_R0_PROXY_STA___M 0x0000FFFF +#define WMAC0_RXPCU_R0_PROXY_STA___S 0 + +#define WMAC0_RXPCU_R0_RX_ANTENNA (0x00A8C0B0) +#define WMAC0_RXPCU_R0_RX_ANTENNA___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RX_ANTENNA___POR 0x00000000 +#define WMAC0_RXPCU_R0_RX_ANTENNA__VALUE___POR 0x000000 +#define WMAC0_RXPCU_R0_RX_ANTENNA__VALUE___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_RX_ANTENNA__VALUE___S 0 +#define WMAC0_RXPCU_R0_RX_ANTENNA___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_RX_ANTENNA___S 0 + +#define WMAC0_RXPCU_R0_NAV_CFG (0x00A8C0B4) +#define WMAC0_RXPCU_R0_NAV_CFG___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_NAV_CFG___POR 0x2803C13A +#define WMAC0_RXPCU_R0_NAV_CFG__SET_NAV_INBSS_DIR_NORESP___POR 0x0 +#define WMAC0_RXPCU_R0_NAV_CFG__SET_NAV_FOR_ABORTED_PPDU___POR 0x1 +#define WMAC0_RXPCU_R0_NAV_CFG__REVERSE_TXOP_DURATION___POR 0x0 +#define WMAC0_RXPCU_R0_NAV_CFG__SET_NAV_BY_TXOP_DURATION___POR 0x1 +#define WMAC0_RXPCU_R0_NAV_CFG__NO_NAV_CHECK_FOR_CTS___POR 0x0 +#define WMAC0_RXPCU_R0_NAV_CFG__EN_11G_MODE___POR 0x0 +#define WMAC0_RXPCU_R0_NAV_CFG__NAV_UPDATE_FOR_MU_EN___POR 0x0 +#define WMAC0_RXPCU_R0_NAV_CFG__OFDM___POR 0x03C +#define WMAC0_RXPCU_R0_NAV_CFG__CCK___POR 0x13A +#define WMAC0_RXPCU_R0_NAV_CFG__SET_NAV_INBSS_DIR_NORESP___M 0x40000000 +#define WMAC0_RXPCU_R0_NAV_CFG__SET_NAV_INBSS_DIR_NORESP___S 30 +#define WMAC0_RXPCU_R0_NAV_CFG__SET_NAV_FOR_ABORTED_PPDU___M 0x20000000 +#define WMAC0_RXPCU_R0_NAV_CFG__SET_NAV_FOR_ABORTED_PPDU___S 29 +#define WMAC0_RXPCU_R0_NAV_CFG__REVERSE_TXOP_DURATION___M 0x10000000 +#define WMAC0_RXPCU_R0_NAV_CFG__REVERSE_TXOP_DURATION___S 28 +#define WMAC0_RXPCU_R0_NAV_CFG__SET_NAV_BY_TXOP_DURATION___M 0x08000000 +#define WMAC0_RXPCU_R0_NAV_CFG__SET_NAV_BY_TXOP_DURATION___S 27 +#define WMAC0_RXPCU_R0_NAV_CFG__NO_NAV_CHECK_FOR_CTS___M 0x04000000 +#define WMAC0_RXPCU_R0_NAV_CFG__NO_NAV_CHECK_FOR_CTS___S 26 +#define WMAC0_RXPCU_R0_NAV_CFG__EN_11G_MODE___M 0x02000000 +#define WMAC0_RXPCU_R0_NAV_CFG__EN_11G_MODE___S 25 +#define WMAC0_RXPCU_R0_NAV_CFG__NAV_UPDATE_FOR_MU_EN___M 0x01000000 +#define WMAC0_RXPCU_R0_NAV_CFG__NAV_UPDATE_FOR_MU_EN___S 24 +#define WMAC0_RXPCU_R0_NAV_CFG__OFDM___M 0x00FFF000 +#define WMAC0_RXPCU_R0_NAV_CFG__OFDM___S 12 +#define WMAC0_RXPCU_R0_NAV_CFG__CCK___M 0x00000FFF +#define WMAC0_RXPCU_R0_NAV_CFG__CCK___S 0 +#define WMAC0_RXPCU_R0_NAV_CFG___M 0x7FFFFFFF +#define WMAC0_RXPCU_R0_NAV_CFG___S 0 + +#define WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG1 (0x00A8C0B8) +#define WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG1___POR 0x00000000 +#define WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG1__CTL_BITMAP___POR 0x0000 +#define WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG1__MGMT_BITMAP___POR 0x0000 +#define WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG1__CTL_BITMAP___M 0xFFFF0000 +#define WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG1__CTL_BITMAP___S 16 +#define WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG1__MGMT_BITMAP___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG1__MGMT_BITMAP___S 0 +#define WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG1___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG1___S 0 + +#define WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG2 (0x00A8C0BC) +#define WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG2___POR 0x00000000 +#define WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG2__TYPE11_BITMAP___POR 0x0000 +#define WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG2__DATA_BITMAP___POR 0x0000 +#define WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG2__TYPE11_BITMAP___M 0xFFFF0000 +#define WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG2__TYPE11_BITMAP___S 16 +#define WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG2__DATA_BITMAP___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG2__DATA_BITMAP___S 0 +#define WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG2___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CLASS_1_FRAME_CFG2___S 0 + +#define WMAC0_RXPCU_R0_SPATIAL_REUSE (0x00A8C0C0) +#define WMAC0_RXPCU_R0_SPATIAL_REUSE___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SPATIAL_REUSE___POR 0x42801380 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__MACRX_ABORT_REQUEST_EN___POR 0x0 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__SR_ABORT_REQUEST_EN___POR 0x1 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__CLEAR_OBSS_NAV_BY_INBSS_CF_END___POR 0x0 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__OBSS_PD_EN___POR 0x0 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__SRG_OBSS_PD_EN___POR 0x0 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__UPDATE_NAV_FOR_CONTROL_PPDU___POR 0x0 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__NO_OBSS_PD_FOR_SRP_PPDU___POR 0x1 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__NO_OBSS_PD_DURING_TXOP___POR 0x0 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__SRG_OBSS_PD_THRESHOLD___POR 0x80 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__USE_RSSI_COMB___POR 0x0 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__OBSS_PD_EN_FOR_TXOP_UNSPECIFY___POR 0x1 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__OBSS_PD_ER_OFFSET___POR 0x3 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__OBSS_PD_THRESHOLD___POR 0x80 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__MACRX_ABORT_REQUEST_EN___M 0x80000000 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__MACRX_ABORT_REQUEST_EN___S 31 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__SR_ABORT_REQUEST_EN___M 0x40000000 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__SR_ABORT_REQUEST_EN___S 30 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__CLEAR_OBSS_NAV_BY_INBSS_CF_END___M 0x20000000 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__CLEAR_OBSS_NAV_BY_INBSS_CF_END___S 29 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__OBSS_PD_EN___M 0x10000000 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__OBSS_PD_EN___S 28 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__SRG_OBSS_PD_EN___M 0x08000000 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__SRG_OBSS_PD_EN___S 27 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__UPDATE_NAV_FOR_CONTROL_PPDU___M 0x04000000 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__UPDATE_NAV_FOR_CONTROL_PPDU___S 26 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__NO_OBSS_PD_FOR_SRP_PPDU___M 0x02000000 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__NO_OBSS_PD_FOR_SRP_PPDU___S 25 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__NO_OBSS_PD_DURING_TXOP___M 0x01000000 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__NO_OBSS_PD_DURING_TXOP___S 24 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__SRG_OBSS_PD_THRESHOLD___M 0x00FF0000 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__SRG_OBSS_PD_THRESHOLD___S 16 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__USE_RSSI_COMB___M 0x00008000 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__USE_RSSI_COMB___S 15 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__OBSS_PD_EN_FOR_TXOP_UNSPECIFY___M 0x00001000 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__OBSS_PD_EN_FOR_TXOP_UNSPECIFY___S 12 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__OBSS_PD_ER_OFFSET___M 0x00000F00 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__OBSS_PD_ER_OFFSET___S 8 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__OBSS_PD_THRESHOLD___M 0x000000FF +#define WMAC0_RXPCU_R0_SPATIAL_REUSE__OBSS_PD_THRESHOLD___S 0 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE___M 0xFFFF9FFF +#define WMAC0_RXPCU_R0_SPATIAL_REUSE___S 0 + +#define WMAC0_RXPCU_R0_SPATIAL_REUSE2 (0x00A8C0C4) +#define WMAC0_RXPCU_R0_SPATIAL_REUSE2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SPATIAL_REUSE2___POR 0x004A8000 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE2__SRP_SR_EN___POR 0x0 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE2__SRP_SR_BY_ULMU_EN___POR 0x0 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE2__NO_SRP_DURING_TXOP___POR 0x0 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE2__CCA_ED_SEL___POR 0x0 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE2__NO_SRP_SR_VALID_DURATION___POR 0x4A +#define WMAC0_RXPCU_R0_SPATIAL_REUSE2__MIN_RSSI_SENSITIVITY___POR 0x80 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE2__MAX_TX_POWER___POR 0x00 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE2__SRP_SR_EN___M 0x80000000 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE2__SRP_SR_EN___S 31 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE2__SRP_SR_BY_ULMU_EN___M 0x40000000 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE2__SRP_SR_BY_ULMU_EN___S 30 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE2__NO_SRP_DURING_TXOP___M 0x20000000 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE2__NO_SRP_DURING_TXOP___S 29 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE2__CCA_ED_SEL___M 0x03000000 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE2__CCA_ED_SEL___S 24 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE2__NO_SRP_SR_VALID_DURATION___M 0x00FF0000 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE2__NO_SRP_SR_VALID_DURATION___S 16 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE2__MIN_RSSI_SENSITIVITY___M 0x0000FF00 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE2__MIN_RSSI_SENSITIVITY___S 8 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE2__MAX_TX_POWER___M 0x000000FF +#define WMAC0_RXPCU_R0_SPATIAL_REUSE2__MAX_TX_POWER___S 0 +#define WMAC0_RXPCU_R0_SPATIAL_REUSE2___M 0xE3FFFFFF +#define WMAC0_RXPCU_R0_SPATIAL_REUSE2___S 0 + +#define WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_n(n) (0x00A8C0C8+0x4*(n)) +#define WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_n_nMIN 0 +#define WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_n_nMAX 1 +#define WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_n_ELEM 2 +#define WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_n___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_n___POR 0x00000000 +#define WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_n__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_n__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_n__VALUE___S 0 +#define WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_n___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_n___S 0 +#define WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_0 (0x00A8C0C8) +#define WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_0__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_0__VALUE___S 0 +#define WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_1 (0x00A8C0CC) +#define WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_1__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_BSS_COLOR_BITMAP_1__VALUE___S 0 + +#define WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_n(n) (0x00A8C0D0+0x4*(n)) +#define WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_n_nMIN 0 +#define WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_n_nMAX 1 +#define WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_n_ELEM 2 +#define WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_n___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_n___POR 0x00000000 +#define WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_n__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_n__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_n__VALUE___S 0 +#define WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_n___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_n___S 0 +#define WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_0 (0x00A8C0D0) +#define WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_0__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_0__VALUE___S 0 +#define WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_1 (0x00A8C0D4) +#define WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_1__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PARTIAL_BSSID_BITMAP_1__VALUE___S 0 + +#define WMAC0_RXPCU_R0_SRP_LUT_0 (0x00A8C0D8) +#define WMAC0_RXPCU_R0_SRP_LUT_0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SRP_LUT_0___POR 0x00000000 +#define WMAC0_RXPCU_R0_SRP_LUT_0__SRP3___POR 0x00 +#define WMAC0_RXPCU_R0_SRP_LUT_0__SRP2___POR 0x00 +#define WMAC0_RXPCU_R0_SRP_LUT_0__SRP1___POR 0x00 +#define WMAC0_RXPCU_R0_SRP_LUT_0__SRP3___M 0xFF000000 +#define WMAC0_RXPCU_R0_SRP_LUT_0__SRP3___S 24 +#define WMAC0_RXPCU_R0_SRP_LUT_0__SRP2___M 0x00FF0000 +#define WMAC0_RXPCU_R0_SRP_LUT_0__SRP2___S 16 +#define WMAC0_RXPCU_R0_SRP_LUT_0__SRP1___M 0x0000FF00 +#define WMAC0_RXPCU_R0_SRP_LUT_0__SRP1___S 8 +#define WMAC0_RXPCU_R0_SRP_LUT_0___M 0xFFFFFF00 +#define WMAC0_RXPCU_R0_SRP_LUT_0___S 8 + +#define WMAC0_RXPCU_R0_SRP_LUT_1 (0x00A8C0DC) +#define WMAC0_RXPCU_R0_SRP_LUT_1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SRP_LUT_1___POR 0x00000000 +#define WMAC0_RXPCU_R0_SRP_LUT_1__SRP7___POR 0x00 +#define WMAC0_RXPCU_R0_SRP_LUT_1__SRP6___POR 0x00 +#define WMAC0_RXPCU_R0_SRP_LUT_1__SRP5___POR 0x00 +#define WMAC0_RXPCU_R0_SRP_LUT_1__SRP4___POR 0x00 +#define WMAC0_RXPCU_R0_SRP_LUT_1__SRP7___M 0xFF000000 +#define WMAC0_RXPCU_R0_SRP_LUT_1__SRP7___S 24 +#define WMAC0_RXPCU_R0_SRP_LUT_1__SRP6___M 0x00FF0000 +#define WMAC0_RXPCU_R0_SRP_LUT_1__SRP6___S 16 +#define WMAC0_RXPCU_R0_SRP_LUT_1__SRP5___M 0x0000FF00 +#define WMAC0_RXPCU_R0_SRP_LUT_1__SRP5___S 8 +#define WMAC0_RXPCU_R0_SRP_LUT_1__SRP4___M 0x000000FF +#define WMAC0_RXPCU_R0_SRP_LUT_1__SRP4___S 0 +#define WMAC0_RXPCU_R0_SRP_LUT_1___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRP_LUT_1___S 0 + +#define WMAC0_RXPCU_R0_SRP_LUT_2 (0x00A8C0E0) +#define WMAC0_RXPCU_R0_SRP_LUT_2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SRP_LUT_2___POR 0x00000000 +#define WMAC0_RXPCU_R0_SRP_LUT_2__SRP11___POR 0x00 +#define WMAC0_RXPCU_R0_SRP_LUT_2__SRP10___POR 0x00 +#define WMAC0_RXPCU_R0_SRP_LUT_2__SRP9___POR 0x00 +#define WMAC0_RXPCU_R0_SRP_LUT_2__SRP8___POR 0x00 +#define WMAC0_RXPCU_R0_SRP_LUT_2__SRP11___M 0xFF000000 +#define WMAC0_RXPCU_R0_SRP_LUT_2__SRP11___S 24 +#define WMAC0_RXPCU_R0_SRP_LUT_2__SRP10___M 0x00FF0000 +#define WMAC0_RXPCU_R0_SRP_LUT_2__SRP10___S 16 +#define WMAC0_RXPCU_R0_SRP_LUT_2__SRP9___M 0x0000FF00 +#define WMAC0_RXPCU_R0_SRP_LUT_2__SRP9___S 8 +#define WMAC0_RXPCU_R0_SRP_LUT_2__SRP8___M 0x000000FF +#define WMAC0_RXPCU_R0_SRP_LUT_2__SRP8___S 0 +#define WMAC0_RXPCU_R0_SRP_LUT_2___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRP_LUT_2___S 0 + +#define WMAC0_RXPCU_R0_SRP_LUT_3 (0x00A8C0E4) +#define WMAC0_RXPCU_R0_SRP_LUT_3___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SRP_LUT_3___POR 0x00000000 +#define WMAC0_RXPCU_R0_SRP_LUT_3__SRP14___POR 0x00 +#define WMAC0_RXPCU_R0_SRP_LUT_3__SRP13___POR 0x00 +#define WMAC0_RXPCU_R0_SRP_LUT_3__SRP12___POR 0x00 +#define WMAC0_RXPCU_R0_SRP_LUT_3__SRP14___M 0x00FF0000 +#define WMAC0_RXPCU_R0_SRP_LUT_3__SRP14___S 16 +#define WMAC0_RXPCU_R0_SRP_LUT_3__SRP13___M 0x0000FF00 +#define WMAC0_RXPCU_R0_SRP_LUT_3__SRP13___S 8 +#define WMAC0_RXPCU_R0_SRP_LUT_3__SRP12___M 0x000000FF +#define WMAC0_RXPCU_R0_SRP_LUT_3__SRP12___S 0 +#define WMAC0_RXPCU_R0_SRP_LUT_3___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_SRP_LUT_3___S 0 + +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT (0x00A8C0E8) +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT___POR 0x27D09010 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__ONE_USEC___POR 0x09F +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_11V_TIM___POR 0x1 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_UCAST_PROBE_RESP___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_UCAST_MOON_PROBE_RESP___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_MCAST_PROBE_RESP___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_BCAST_PROBE_RESP___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_BEACON___POR 0x1 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__RX_LATENCY_OFDM___POR 0x10 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__MY_BEACON2_PROC___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__MY_BEACON_PROC___POR 0x1 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__CHECK_DTIM_COUNT_FOR_NONTRANS_BSSID_DTIM___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__ONE_USEC___M 0xFFC00000 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__ONE_USEC___S 22 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_11V_TIM___M 0x00100000 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_11V_TIM___S 20 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_UCAST_PROBE_RESP___M 0x00080000 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_UCAST_PROBE_RESP___S 19 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_UCAST_MOON_PROBE_RESP___M 0x00040000 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_UCAST_MOON_PROBE_RESP___S 18 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_MCAST_PROBE_RESP___M 0x00020000 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_MCAST_PROBE_RESP___S 17 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_BCAST_PROBE_RESP___M 0x00010000 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_BCAST_PROBE_RESP___S 16 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_BEACON___M 0x00008000 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__SYNC_TSF_ON_BEACON___S 15 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__RX_LATENCY_OFDM___M 0x00003F00 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__RX_LATENCY_OFDM___S 8 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__MY_BEACON2_PROC___M 0x00000020 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__MY_BEACON2_PROC___S 5 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__MY_BEACON_PROC___M 0x00000010 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__MY_BEACON_PROC___S 4 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__CHECK_DTIM_COUNT_FOR_NONTRANS_BSSID_DTIM___M 0x00000008 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT__CHECK_DTIM_COUNT_FOR_NONTRANS_BSSID_DTIM___S 3 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT___M 0xFFDFBF38 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT___S 3 + +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT2 (0x00A8C0EC) +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT2___POR 0x10101010 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT2__RX_LATENCY_VHT_SU___POR 0x10 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT2__RX_LATENCY_HE_MU___POR 0x10 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT2__RX_LATENCY_HE_SU___POR 0x10 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT2__RX_LATENCY_CCK___POR 0x10 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT2__RX_LATENCY_VHT_SU___M 0x3F000000 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT2__RX_LATENCY_VHT_SU___S 24 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT2__RX_LATENCY_HE_MU___M 0x003F0000 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT2__RX_LATENCY_HE_MU___S 16 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT2__RX_LATENCY_HE_SU___M 0x00003F00 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT2__RX_LATENCY_HE_SU___S 8 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT2__RX_LATENCY_CCK___M 0x0000003F +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT2__RX_LATENCY_CCK___S 0 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT2___M 0x3F3F3F3F +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT2___S 0 + +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT3 (0x00A8C0F0) +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT3___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT3___POR 0x00000010 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT3__RX_LATENCY_VHT_MU___POR 0x10 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT3__RX_LATENCY_VHT_MU___M 0x0000003F +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT3__RX_LATENCY_VHT_MU___S 0 +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT3___M 0x0000003F +#define WMAC0_RXPCU_R0_RFF_DIRECT_CONNECT3___S 0 + +#define WMAC0_RXPCU_R0_LAST_BEACON_TSF (0x00A8C0F4) +#define WMAC0_RXPCU_R0_LAST_BEACON_TSF___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_LAST_BEACON_TSF___POR 0x00000000 +#define WMAC0_RXPCU_R0_LAST_BEACON_TSF__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_LAST_BEACON_TSF__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_LAST_BEACON_TSF__VALUE___S 0 +#define WMAC0_RXPCU_R0_LAST_BEACON_TSF___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_LAST_BEACON_TSF___S 0 + +#define WMAC0_RXPCU_R0_LAST_BEACON_TSF_HIGH (0x00A8C0F8) +#define WMAC0_RXPCU_R0_LAST_BEACON_TSF_HIGH___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_LAST_BEACON_TSF_HIGH___POR 0x00000000 +#define WMAC0_RXPCU_R0_LAST_BEACON_TSF_HIGH__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_LAST_BEACON_TSF_HIGH__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_LAST_BEACON_TSF_HIGH__VALUE___S 0 +#define WMAC0_RXPCU_R0_LAST_BEACON_TSF_HIGH___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_LAST_BEACON_TSF_HIGH___S 0 + +#define WMAC0_RXPCU_R0_LAST_BEACON2_TSF (0x00A8C0FC) +#define WMAC0_RXPCU_R0_LAST_BEACON2_TSF___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_LAST_BEACON2_TSF___POR 0x00000000 +#define WMAC0_RXPCU_R0_LAST_BEACON2_TSF__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_LAST_BEACON2_TSF__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_LAST_BEACON2_TSF__VALUE___S 0 +#define WMAC0_RXPCU_R0_LAST_BEACON2_TSF___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_LAST_BEACON2_TSF___S 0 + +#define WMAC0_RXPCU_R0_LAST_BEACON2_TSF_HIGH (0x00A8C100) +#define WMAC0_RXPCU_R0_LAST_BEACON2_TSF_HIGH___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_LAST_BEACON2_TSF_HIGH___POR 0x00000000 +#define WMAC0_RXPCU_R0_LAST_BEACON2_TSF_HIGH__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_LAST_BEACON2_TSF_HIGH__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_LAST_BEACON2_TSF_HIGH__VALUE___S 0 +#define WMAC0_RXPCU_R0_LAST_BEACON2_TSF_HIGH___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_LAST_BEACON2_TSF_HIGH___S 0 + +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1 (0x00A8C104) +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__ELM2_ID___POR 0x00 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__ELM1_ID___POR 0x00 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__ELM0_ID___POR 0x00 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__EXCLUDE_ELM2___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__EXCLUDE_ELM1___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__EXCLUDE_ELM0___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__EXCLUDE_CAP_INFO___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__EXCLUDE_BCN_INTVL___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__CRC_ENABLE2___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__CRC_ENABLE___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__ELM2_ID___M 0xFF000000 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__ELM2_ID___S 24 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__ELM1_ID___M 0x00FF0000 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__ELM1_ID___S 16 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__ELM0_ID___M 0x0000FF00 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__ELM0_ID___S 8 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__EXCLUDE_ELM2___M 0x00000080 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__EXCLUDE_ELM2___S 7 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__EXCLUDE_ELM1___M 0x00000040 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__EXCLUDE_ELM1___S 6 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__EXCLUDE_ELM0___M 0x00000020 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__EXCLUDE_ELM0___S 5 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__EXCLUDE_CAP_INFO___M 0x00000008 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__EXCLUDE_CAP_INFO___S 3 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__EXCLUDE_BCN_INTVL___M 0x00000004 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__EXCLUDE_BCN_INTVL___S 2 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__CRC_ENABLE2___M 0x00000002 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__CRC_ENABLE2___S 1 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__CRC_ENABLE___M 0x00000001 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1__CRC_ENABLE___S 0 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1___M 0xFFFFFFEF +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC1___S 0 + +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC2 (0x00A8C108) +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC2___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC2__LENGTH_ENABLE2___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC2__LENGTH_ENABLE___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC2__ELM3_ID___POR 0x00 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC2__EXCLUDE_ELM3___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC2__LENGTH_ENABLE2___M 0x00020000 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC2__LENGTH_ENABLE2___S 17 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC2__LENGTH_ENABLE___M 0x00010000 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC2__LENGTH_ENABLE___S 16 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC2__ELM3_ID___M 0x0000FF00 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC2__ELM3_ID___S 8 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC2__EXCLUDE_ELM3___M 0x00000004 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC2__EXCLUDE_ELM3___S 2 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC2___M 0x0003FF04 +#define WMAC0_RXPCU_R0_RFF_HW_BCN_PROC2___S 2 + +#define WMAC0_RXPCU_R0_RFF_BCN_MISS_CNT (0x00A8C10C) +#define WMAC0_RXPCU_R0_RFF_BCN_MISS_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_BCN_MISS_CNT___POR 0x0FFC0000 +#define WMAC0_RXPCU_R0_RFF_BCN_MISS_CNT__STEP_UP___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_BCN_MISS_CNT__TSF_UPDATE_MISSED_THRESH___POR 0x3FF +#define WMAC0_RXPCU_R0_RFF_BCN_MISS_CNT__BCN_MISS_BY_CNT___POR 0x00 +#define WMAC0_RXPCU_R0_RFF_BCN_MISS_CNT__TSF_UPDATE_MISSED_CNT___POR 0x000 +#define WMAC0_RXPCU_R0_RFF_BCN_MISS_CNT__STEP_UP___M 0x70000000 +#define WMAC0_RXPCU_R0_RFF_BCN_MISS_CNT__STEP_UP___S 28 +#define WMAC0_RXPCU_R0_RFF_BCN_MISS_CNT__TSF_UPDATE_MISSED_THRESH___M 0x0FFC0000 +#define WMAC0_RXPCU_R0_RFF_BCN_MISS_CNT__TSF_UPDATE_MISSED_THRESH___S 18 +#define WMAC0_RXPCU_R0_RFF_BCN_MISS_CNT__BCN_MISS_BY_CNT___M 0x0003FC00 +#define WMAC0_RXPCU_R0_RFF_BCN_MISS_CNT__BCN_MISS_BY_CNT___S 10 +#define WMAC0_RXPCU_R0_RFF_BCN_MISS_CNT__TSF_UPDATE_MISSED_CNT___M 0x000003FF +#define WMAC0_RXPCU_R0_RFF_BCN_MISS_CNT__TSF_UPDATE_MISSED_CNT___S 0 +#define WMAC0_RXPCU_R0_RFF_BCN_MISS_CNT___M 0x7FFFFFFF +#define WMAC0_RXPCU_R0_RFF_BCN_MISS_CNT___S 0 + +#define WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT1 (0x00A8C110) +#define WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT1___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT1__BCN_MISS_INC___POR 0x000 +#define WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT1__BCN_TIMEOUT_TIME___POR 0x000 +#define WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT1__BCN_MISS_INC___M 0x03FF0000 +#define WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT1__BCN_MISS_INC___S 16 +#define WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT1__BCN_TIMEOUT_TIME___M 0x00000FFF +#define WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT1__BCN_TIMEOUT_TIME___S 0 +#define WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT1___M 0x03FF0FFF +#define WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT1___S 0 + +#define WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT2 (0x00A8C114) +#define WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT2___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT2__CAB_AWAKE_TIMEOUT_TIME___POR 0x000 +#define WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT2__CAB_END_TIME___POR 0x00 +#define WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT2__CAB_AWAKE_TIMEOUT_TIME___M 0x000FFF00 +#define WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT2__CAB_AWAKE_TIMEOUT_TIME___S 8 +#define WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT2__CAB_END_TIME___M 0x000000FF +#define WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT2__CAB_END_TIME___S 0 +#define WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT2___M 0x000FFFFF +#define WMAC0_RXPCU_R0_RFF_BCN_TIMEOUT2___S 0 + +#define WMAC0_RXPCU_R0_RFF_BCN_MISS (0x00A8C118) +#define WMAC0_RXPCU_R0_RFF_BCN_MISS___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_BCN_MISS___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_BCN_MISS__TYPE___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_BCN_MISS__BY_TIME_THRESHOLD___POR 0x0000 +#define WMAC0_RXPCU_R0_RFF_BCN_MISS__TYPE___M 0x80000000 +#define WMAC0_RXPCU_R0_RFF_BCN_MISS__TYPE___S 31 +#define WMAC0_RXPCU_R0_RFF_BCN_MISS__BY_TIME_THRESHOLD___M 0x00003FFF +#define WMAC0_RXPCU_R0_RFF_BCN_MISS__BY_TIME_THRESHOLD___S 0 +#define WMAC0_RXPCU_R0_RFF_BCN_MISS___M 0x80003FFF +#define WMAC0_RXPCU_R0_RFF_BCN_MISS___S 0 + +#define WMAC0_RXPCU_R0_RFF_BCN_EARLY_RX (0x00A8C11C) +#define WMAC0_RXPCU_R0_RFF_BCN_EARLY_RX___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_BCN_EARLY_RX___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_BCN_EARLY_RX__EARLY_RX_INC___POR 0x000 +#define WMAC0_RXPCU_R0_RFF_BCN_EARLY_RX__SLEEP_SLOP_OFFSET___POR 0x0000 +#define WMAC0_RXPCU_R0_RFF_BCN_EARLY_RX__EARLY_RX_INC___M 0x03FF0000 +#define WMAC0_RXPCU_R0_RFF_BCN_EARLY_RX__EARLY_RX_INC___S 16 +#define WMAC0_RXPCU_R0_RFF_BCN_EARLY_RX__SLEEP_SLOP_OFFSET___M 0x00003FFF +#define WMAC0_RXPCU_R0_RFF_BCN_EARLY_RX__SLEEP_SLOP_OFFSET___S 0 +#define WMAC0_RXPCU_R0_RFF_BCN_EARLY_RX___M 0x03FF3FFF +#define WMAC0_RXPCU_R0_RFF_BCN_EARLY_RX___S 0 + +#define WMAC0_RXPCU_R0_RFF_BCN1_LENGTH_WO_TIM (0x00A8C120) +#define WMAC0_RXPCU_R0_RFF_BCN1_LENGTH_WO_TIM___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_BCN1_LENGTH_WO_TIM___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_BCN1_LENGTH_WO_TIM__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R0_RFF_BCN1_LENGTH_WO_TIM__VALUE___M 0x00003FFF +#define WMAC0_RXPCU_R0_RFF_BCN1_LENGTH_WO_TIM__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_BCN1_LENGTH_WO_TIM___M 0x00003FFF +#define WMAC0_RXPCU_R0_RFF_BCN1_LENGTH_WO_TIM___S 0 + +#define WMAC0_RXPCU_R0_BCN2_LENGTH_WO_TIM (0x00A8C124) +#define WMAC0_RXPCU_R0_BCN2_LENGTH_WO_TIM___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_BCN2_LENGTH_WO_TIM___POR 0x00000000 +#define WMAC0_RXPCU_R0_BCN2_LENGTH_WO_TIM__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R0_BCN2_LENGTH_WO_TIM__VALUE___M 0x00003FFF +#define WMAC0_RXPCU_R0_BCN2_LENGTH_WO_TIM__VALUE___S 0 +#define WMAC0_RXPCU_R0_BCN2_LENGTH_WO_TIM___M 0x00003FFF +#define WMAC0_RXPCU_R0_BCN2_LENGTH_WO_TIM___S 0 + +#define WMAC0_RXPCU_R0_RFF_BCN1_CRC (0x00A8C128) +#define WMAC0_RXPCU_R0_RFF_BCN1_CRC___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_BCN1_CRC___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_BCN1_CRC__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_BCN1_CRC__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_BCN1_CRC__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_BCN1_CRC___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_BCN1_CRC___S 0 + +#define WMAC0_RXPCU_R0_BCN2_CRC (0x00A8C12C) +#define WMAC0_RXPCU_R0_BCN2_CRC___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_BCN2_CRC___POR 0x00000000 +#define WMAC0_RXPCU_R0_BCN2_CRC__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_BCN2_CRC__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_BCN2_CRC__VALUE___S 0 +#define WMAC0_RXPCU_R0_BCN2_CRC___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_BCN2_CRC___S 0 + +#define WMAC0_RXPCU_R0_RFF_BCN1_GLOBAL_CNT_31_0 (0x00A8C130) +#define WMAC0_RXPCU_R0_RFF_BCN1_GLOBAL_CNT_31_0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_BCN1_GLOBAL_CNT_31_0___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_BCN1_GLOBAL_CNT_31_0__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_BCN1_GLOBAL_CNT_31_0__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_BCN1_GLOBAL_CNT_31_0__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_BCN1_GLOBAL_CNT_31_0___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_BCN1_GLOBAL_CNT_31_0___S 0 + +#define WMAC0_RXPCU_R0_RFF_BCN1_GLOBAL_CNT_63_32 (0x00A8C134) +#define WMAC0_RXPCU_R0_RFF_BCN1_GLOBAL_CNT_63_32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_BCN1_GLOBAL_CNT_63_32___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_BCN1_GLOBAL_CNT_63_32__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_BCN1_GLOBAL_CNT_63_32__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_BCN1_GLOBAL_CNT_63_32__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_BCN1_GLOBAL_CNT_63_32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_BCN1_GLOBAL_CNT_63_32___S 0 + +#define WMAC0_RXPCU_R0_BCN2_GLOBAL_CNT_31_0 (0x00A8C138) +#define WMAC0_RXPCU_R0_BCN2_GLOBAL_CNT_31_0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_BCN2_GLOBAL_CNT_31_0___POR 0x00000000 +#define WMAC0_RXPCU_R0_BCN2_GLOBAL_CNT_31_0__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_BCN2_GLOBAL_CNT_31_0__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_BCN2_GLOBAL_CNT_31_0__VALUE___S 0 +#define WMAC0_RXPCU_R0_BCN2_GLOBAL_CNT_31_0___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_BCN2_GLOBAL_CNT_31_0___S 0 + +#define WMAC0_RXPCU_R0_BCN2_GLOBAL_CNT_63_32 (0x00A8C13C) +#define WMAC0_RXPCU_R0_BCN2_GLOBAL_CNT_63_32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_BCN2_GLOBAL_CNT_63_32___POR 0x00000000 +#define WMAC0_RXPCU_R0_BCN2_GLOBAL_CNT_63_32__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_BCN2_GLOBAL_CNT_63_32__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_BCN2_GLOBAL_CNT_63_32__VALUE___S 0 +#define WMAC0_RXPCU_R0_BCN2_GLOBAL_CNT_63_32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_BCN2_GLOBAL_CNT_63_32___S 0 + +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS (0x00A8C140) +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS___POR 0x00200008 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__FIX_EN_DMPS_HANG_BY_OTHER_PHYOFF___POR 0x1 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__SEND_PHYOFF_FOR_MIMOPS___POR 0x0 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__COLLIDE_BY_RXPCU_PHY_OFF___POR 0x0 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__COLLIDE_BY_RXPCU_PHY_ON___POR 0x0 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__COLLIDE_BY_PMM_PHY_OFF___POR 0x0 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__COLLIDE_BY_PMM_PHY_ON___POR 0x0 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__SEND_ANT_SEL___POR 0x0 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__ANT_SEL___POR 0x0 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__CURRENT_MODE___POR 0x0 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__RX_SINGLE_CHAIN_MODE___POR 0x0 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__RX_FULL_CHAIN_MODE___POR 0x0 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__SEND_RX_CHAIN_MASK_ON_TXOP_EXPIRY___POR 0x1 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__TRIGGER_EN___POR 0x0 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__DIRECTED_PKT_EN___POR 0x0 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__RTS_EN___POR 0x0 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__FIX_EN_DMPS_HANG_BY_OTHER_PHYOFF___M 0x00200000 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__FIX_EN_DMPS_HANG_BY_OTHER_PHYOFF___S 21 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__SEND_PHYOFF_FOR_MIMOPS___M 0x00100000 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__SEND_PHYOFF_FOR_MIMOPS___S 20 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__COLLIDE_BY_RXPCU_PHY_OFF___M 0x00080000 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__COLLIDE_BY_RXPCU_PHY_OFF___S 19 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__COLLIDE_BY_RXPCU_PHY_ON___M 0x00040000 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__COLLIDE_BY_RXPCU_PHY_ON___S 18 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__COLLIDE_BY_PMM_PHY_OFF___M 0x00020000 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__COLLIDE_BY_PMM_PHY_OFF___S 17 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__COLLIDE_BY_PMM_PHY_ON___M 0x00010000 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__COLLIDE_BY_PMM_PHY_ON___S 16 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__SEND_ANT_SEL___M 0x00004000 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__SEND_ANT_SEL___S 14 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__ANT_SEL___M 0x00002000 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__ANT_SEL___S 13 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__CURRENT_MODE___M 0x00001000 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__CURRENT_MODE___S 12 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__RX_SINGLE_CHAIN_MODE___M 0x00000F00 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__RX_SINGLE_CHAIN_MODE___S 8 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__RX_FULL_CHAIN_MODE___M 0x000000F0 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__RX_FULL_CHAIN_MODE___S 4 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__SEND_RX_CHAIN_MASK_ON_TXOP_EXPIRY___M 0x00000008 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__SEND_RX_CHAIN_MASK_ON_TXOP_EXPIRY___S 3 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__TRIGGER_EN___M 0x00000004 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__TRIGGER_EN___S 2 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__DIRECTED_PKT_EN___M 0x00000002 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__DIRECTED_PKT_EN___S 1 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__RTS_EN___M 0x00000001 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS__RTS_EN___S 0 +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS___M 0x003F7FFF +#define WMAC0_RXPCU_R0_DYNAMIC_MIMO_PS___S 0 + +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0 (0x00A8C144) +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0___POR 0x0C800000 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__PHY_ON_OFF_DELAY___POR 0x0C8 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__ADDR_MISMATCH_WITH_FCS___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__ADDR_MISMATCH_NO_FCS_CHK___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__STA_ID_MISMATCH_ENABLE___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__BSS_COLOR_MISMATCH_ENABLE___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__HE_UPLINK_ENABLE___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__ADDR_MISMATCH_EXTN_ENABLE___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__ADDR_MISMATCH_DATA_ENABLE___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__ADDR_MISMATCH_MGMT_ENABLE___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__PHYRX_ABORT_REQUEST_ENABLE___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__PHY_NAP_EIFS_ENABLE___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__GID_NSTS_ZERO_ENABLE___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__DELIMITER_CRC_FAIL_ENABLE___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__EARLY_DTIM_CLEAR_ENABLE___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__EARLY_TIM_CLEAR_ENABLE___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__EOF_PAD_DELIMITER_ENABLE___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__GID_MATCH_ENABLE___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__PARTIAL_AID_MATCH_ENABLE___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__PHY_ON_OFF_DELAY___M 0xFFF00000 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__PHY_ON_OFF_DELAY___S 20 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__ADDR_MISMATCH_WITH_FCS___M 0x00080000 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__ADDR_MISMATCH_WITH_FCS___S 19 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__ADDR_MISMATCH_NO_FCS_CHK___M 0x00040000 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__ADDR_MISMATCH_NO_FCS_CHK___S 18 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__STA_ID_MISMATCH_ENABLE___M 0x00020000 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__STA_ID_MISMATCH_ENABLE___S 17 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__BSS_COLOR_MISMATCH_ENABLE___M 0x00010000 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__BSS_COLOR_MISMATCH_ENABLE___S 16 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__HE_UPLINK_ENABLE___M 0x00008000 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__HE_UPLINK_ENABLE___S 15 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__ADDR_MISMATCH_EXTN_ENABLE___M 0x00004000 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__ADDR_MISMATCH_EXTN_ENABLE___S 14 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__ADDR_MISMATCH_DATA_ENABLE___M 0x00002000 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__ADDR_MISMATCH_DATA_ENABLE___S 13 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__ADDR_MISMATCH_MGMT_ENABLE___M 0x00001000 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__ADDR_MISMATCH_MGMT_ENABLE___S 12 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__PHYRX_ABORT_REQUEST_ENABLE___M 0x00000800 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__PHYRX_ABORT_REQUEST_ENABLE___S 11 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__PHY_NAP_EIFS_ENABLE___M 0x00000400 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__PHY_NAP_EIFS_ENABLE___S 10 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__GID_NSTS_ZERO_ENABLE___M 0x00000100 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__GID_NSTS_ZERO_ENABLE___S 8 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__DELIMITER_CRC_FAIL_ENABLE___M 0x00000080 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__DELIMITER_CRC_FAIL_ENABLE___S 7 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__EARLY_DTIM_CLEAR_ENABLE___M 0x00000010 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__EARLY_DTIM_CLEAR_ENABLE___S 4 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__EARLY_TIM_CLEAR_ENABLE___M 0x00000008 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__EARLY_TIM_CLEAR_ENABLE___S 3 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__EOF_PAD_DELIMITER_ENABLE___M 0x00000004 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__EOF_PAD_DELIMITER_ENABLE___S 2 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__GID_MATCH_ENABLE___M 0x00000002 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__GID_MATCH_ENABLE___S 1 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__PARTIAL_AID_MATCH_ENABLE___M 0x00000001 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0__PARTIAL_AID_MATCH_ENABLE___S 0 +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0___M 0xFFFFFD9F +#define WMAC0_RXPCU_R0_RFF_POWER_SAVE_0___S 0 + +#define WMAC0_RXPCU_R0_POWER_SAVE_1 (0x00A8C148) +#define WMAC0_RXPCU_R0_POWER_SAVE_1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_POWER_SAVE_1___POR 0x00000000 +#define WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_2_MATCH_EN___POR 0x0 +#define WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_2_MATCH_VALUE___POR 0x000 +#define WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_1_MATCH_EN___POR 0x0 +#define WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_1_MATCH_VALUE___POR 0x000 +#define WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_0_MATCH_EN___POR 0x0 +#define WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_0_MATCH_VALUE___POR 0x000 +#define WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_2_MATCH_EN___M 0x20000000 +#define WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_2_MATCH_EN___S 29 +#define WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_2_MATCH_VALUE___M 0x1FF00000 +#define WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_2_MATCH_VALUE___S 20 +#define WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_1_MATCH_EN___M 0x00080000 +#define WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_1_MATCH_EN___S 19 +#define WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_1_MATCH_VALUE___M 0x0007FC00 +#define WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_1_MATCH_VALUE___S 10 +#define WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_0_MATCH_EN___M 0x00000200 +#define WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_0_MATCH_EN___S 9 +#define WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_0_MATCH_VALUE___M 0x000001FF +#define WMAC0_RXPCU_R0_POWER_SAVE_1__P_AID_0_MATCH_VALUE___S 0 +#define WMAC0_RXPCU_R0_POWER_SAVE_1___M 0x3FFFFFFF +#define WMAC0_RXPCU_R0_POWER_SAVE_1___S 0 + +#define WMAC0_RXPCU_R0_POWER_SAVE_2 (0x00A8C14C) +#define WMAC0_RXPCU_R0_POWER_SAVE_2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_POWER_SAVE_2___POR 0x00000000 +#define WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_5_MATCH_EN___POR 0x0 +#define WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_5_MATCH_VALUE___POR 0x000 +#define WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_4_MATCH_EN___POR 0x0 +#define WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_4_MATCH_VALUE___POR 0x000 +#define WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_3_MATCH_EN___POR 0x0 +#define WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_3_MATCH_VALUE___POR 0x000 +#define WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_5_MATCH_EN___M 0x20000000 +#define WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_5_MATCH_EN___S 29 +#define WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_5_MATCH_VALUE___M 0x1FF00000 +#define WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_5_MATCH_VALUE___S 20 +#define WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_4_MATCH_EN___M 0x00080000 +#define WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_4_MATCH_EN___S 19 +#define WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_4_MATCH_VALUE___M 0x0007FC00 +#define WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_4_MATCH_VALUE___S 10 +#define WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_3_MATCH_EN___M 0x00000200 +#define WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_3_MATCH_EN___S 9 +#define WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_3_MATCH_VALUE___M 0x000001FF +#define WMAC0_RXPCU_R0_POWER_SAVE_2__P_AID_3_MATCH_VALUE___S 0 +#define WMAC0_RXPCU_R0_POWER_SAVE_2___M 0x3FFFFFFF +#define WMAC0_RXPCU_R0_POWER_SAVE_2___S 0 + +#define WMAC0_RXPCU_R0_POWER_SAVE_3 (0x00A8C150) +#define WMAC0_RXPCU_R0_POWER_SAVE_3___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_POWER_SAVE_3___POR 0x00000000 +#define WMAC0_RXPCU_R0_POWER_SAVE_3__GID_LSB_BITMAP_VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_POWER_SAVE_3__GID_LSB_BITMAP_VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_POWER_SAVE_3__GID_LSB_BITMAP_VALUE___S 0 +#define WMAC0_RXPCU_R0_POWER_SAVE_3___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_POWER_SAVE_3___S 0 + +#define WMAC0_RXPCU_R0_POWER_SAVE_4 (0x00A8C154) +#define WMAC0_RXPCU_R0_POWER_SAVE_4___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_POWER_SAVE_4___POR 0x00000000 +#define WMAC0_RXPCU_R0_POWER_SAVE_4__GID_MSB_BITMAP_VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_POWER_SAVE_4__GID_MSB_BITMAP_VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_POWER_SAVE_4__GID_MSB_BITMAP_VALUE___S 0 +#define WMAC0_RXPCU_R0_POWER_SAVE_4___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_POWER_SAVE_4___S 0 + +#define WMAC0_RXPCU_R0_POWER_SAVE_5 (0x00A8C158) +#define WMAC0_RXPCU_R0_POWER_SAVE_5___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_POWER_SAVE_5___POR 0x00000000 +#define WMAC0_RXPCU_R0_POWER_SAVE_5__GID_USER_NUMBER_REGISTER_0___POR 0x00000000 +#define WMAC0_RXPCU_R0_POWER_SAVE_5__GID_USER_NUMBER_REGISTER_0___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_POWER_SAVE_5__GID_USER_NUMBER_REGISTER_0___S 0 +#define WMAC0_RXPCU_R0_POWER_SAVE_5___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_POWER_SAVE_5___S 0 + +#define WMAC0_RXPCU_R0_POWER_SAVE_6 (0x00A8C15C) +#define WMAC0_RXPCU_R0_POWER_SAVE_6___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_POWER_SAVE_6___POR 0x00000000 +#define WMAC0_RXPCU_R0_POWER_SAVE_6__GID_USER_NUMBER_REGISTER_1___POR 0x00000000 +#define WMAC0_RXPCU_R0_POWER_SAVE_6__GID_USER_NUMBER_REGISTER_1___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_POWER_SAVE_6__GID_USER_NUMBER_REGISTER_1___S 0 +#define WMAC0_RXPCU_R0_POWER_SAVE_6___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_POWER_SAVE_6___S 0 + +#define WMAC0_RXPCU_R0_POWER_SAVE_7 (0x00A8C160) +#define WMAC0_RXPCU_R0_POWER_SAVE_7___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_POWER_SAVE_7___POR 0x00000000 +#define WMAC0_RXPCU_R0_POWER_SAVE_7__GID_USER_NUMBER_REGISTER_2___POR 0x00000000 +#define WMAC0_RXPCU_R0_POWER_SAVE_7__GID_USER_NUMBER_REGISTER_2___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_POWER_SAVE_7__GID_USER_NUMBER_REGISTER_2___S 0 +#define WMAC0_RXPCU_R0_POWER_SAVE_7___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_POWER_SAVE_7___S 0 + +#define WMAC0_RXPCU_R0_POWER_SAVE_8 (0x00A8C164) +#define WMAC0_RXPCU_R0_POWER_SAVE_8___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_POWER_SAVE_8___POR 0x00000000 +#define WMAC0_RXPCU_R0_POWER_SAVE_8__GID_USER_NUMBER_REGISTER_3___POR 0x00000000 +#define WMAC0_RXPCU_R0_POWER_SAVE_8__GID_USER_NUMBER_REGISTER_3___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_POWER_SAVE_8__GID_USER_NUMBER_REGISTER_3___S 0 +#define WMAC0_RXPCU_R0_POWER_SAVE_8___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_POWER_SAVE_8___S 0 + +#define WMAC0_RXPCU_R0_RFF_NAP_CTRL (0x00A8C168) +#define WMAC0_RXPCU_R0_RFF_NAP_CTRL___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_NAP_CTRL___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_NAP_CTRL__PHY_ABORT_HE_INBSS_THRESH___POR 0x00 +#define WMAC0_RXPCU_R0_RFF_NAP_CTRL__USE_LEGACY_NAP___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_NAP_CTRL__OBSS_THRESH___POR 0x00 +#define WMAC0_RXPCU_R0_RFF_NAP_CTRL__INBSS_THRESH___POR 0x00 +#define WMAC0_RXPCU_R0_RFF_NAP_CTRL__PHY_ABORT_HE_INBSS_THRESH___M 0xFF000000 +#define WMAC0_RXPCU_R0_RFF_NAP_CTRL__PHY_ABORT_HE_INBSS_THRESH___S 24 +#define WMAC0_RXPCU_R0_RFF_NAP_CTRL__USE_LEGACY_NAP___M 0x00010000 +#define WMAC0_RXPCU_R0_RFF_NAP_CTRL__USE_LEGACY_NAP___S 16 +#define WMAC0_RXPCU_R0_RFF_NAP_CTRL__OBSS_THRESH___M 0x0000FF00 +#define WMAC0_RXPCU_R0_RFF_NAP_CTRL__OBSS_THRESH___S 8 +#define WMAC0_RXPCU_R0_RFF_NAP_CTRL__INBSS_THRESH___M 0x000000FF +#define WMAC0_RXPCU_R0_RFF_NAP_CTRL__INBSS_THRESH___S 0 +#define WMAC0_RXPCU_R0_RFF_NAP_CTRL___M 0xFF01FFFF +#define WMAC0_RXPCU_R0_RFF_NAP_CTRL___S 0 + +#define WMAC0_RXPCU_R0_RFF_EBT_CFG0 (0x00A8C16C) +#define WMAC0_RXPCU_R0_RFF_EBT_CFG0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_EBT_CFG0___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG0__PHY_DISABLE_CFGXX___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG0__PHY_DISABLE_CFG11___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG0__PHY_DISABLE_CFG10___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG0__PHY_DISABLE_CFG01___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG0__PHY_DISABLE_CFG00___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG0__EBT_COUNT___POR 0x000 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG0__EBT_CNT_THRESH___POR 0x000 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG0__PHY_DISABLE_CFGXX___M 0xC0000000 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG0__PHY_DISABLE_CFGXX___S 30 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG0__PHY_DISABLE_CFG11___M 0x30000000 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG0__PHY_DISABLE_CFG11___S 28 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG0__PHY_DISABLE_CFG10___M 0x0C000000 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG0__PHY_DISABLE_CFG10___S 26 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG0__PHY_DISABLE_CFG01___M 0x03000000 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG0__PHY_DISABLE_CFG01___S 24 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG0__PHY_DISABLE_CFG00___M 0x00C00000 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG0__PHY_DISABLE_CFG00___S 22 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG0__EBT_COUNT___M 0x003FF800 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG0__EBT_COUNT___S 11 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG0__EBT_CNT_THRESH___M 0x000007FF +#define WMAC0_RXPCU_R0_RFF_EBT_CFG0__EBT_CNT_THRESH___S 0 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG0___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_EBT_CFG0___S 0 + +#define WMAC0_RXPCU_R0_RFF_EBT_CFG1 (0x00A8C170) +#define WMAC0_RXPCU_R0_RFF_EBT_CFG1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_EBT_CFG1___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG1__CHANGE_SEQUENCE2___POR 0x00 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG1__CHANGE_SEQUENCE___POR 0x00 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG1__CHECK_BEACON___POR 0x00 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG1__DISABLE_PKT_FORWARDING___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG1__CAB_AFTER_BCN_FCS_FAIL___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG1__TIM_FRAME_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG1__CHANGE_SEQUENCE2___M 0xFF000000 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG1__CHANGE_SEQUENCE2___S 24 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG1__CHANGE_SEQUENCE___M 0x00FF0000 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG1__CHANGE_SEQUENCE___S 16 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG1__CHECK_BEACON___M 0x0000FF00 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG1__CHECK_BEACON___S 8 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG1__DISABLE_PKT_FORWARDING___M 0x00000010 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG1__DISABLE_PKT_FORWARDING___S 4 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG1__CAB_AFTER_BCN_FCS_FAIL___M 0x00000004 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG1__CAB_AFTER_BCN_FCS_FAIL___S 2 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG1__TIM_FRAME_EN___M 0x00000001 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG1__TIM_FRAME_EN___S 0 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG1___M 0xFFFFFF15 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG1___S 0 + +#define WMAC0_RXPCU_R0_RFF_EBT_CFG2 (0x00A8C174) +#define WMAC0_RXPCU_R0_RFF_EBT_CFG2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_EBT_CFG2___POR 0x00000080 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG2__EARLY_RX_COUNT___POR 0x00 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG2__TSF_RSSI_THRESH___POR 0x80 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG2__EARLY_RX_COUNT___M 0x0000FF00 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG2__EARLY_RX_COUNT___S 8 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG2__TSF_RSSI_THRESH___M 0x000000FF +#define WMAC0_RXPCU_R0_RFF_EBT_CFG2__TSF_RSSI_THRESH___S 0 +#define WMAC0_RXPCU_R0_RFF_EBT_CFG2___M 0x0000FFFF +#define WMAC0_RXPCU_R0_RFF_EBT_CFG2___S 0 + +#define WMAC0_RXPCU_R0_RFF_TSFOOR_CFG (0x00A8C178) +#define WMAC0_RXPCU_R0_RFF_TSFOOR_CFG___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_TSFOOR_CFG___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_TSFOOR_CFG__TSF_OOR_THRESH___POR 0x00 +#define WMAC0_RXPCU_R0_RFF_TSFOOR_CFG__OOR_CNT_THRESH___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_TSFOOR_CFG__OOR_COUNT2___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_TSFOOR_CFG__OOR_COUNT1___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_TSFOOR_CFG__TSF_OOR_THRESH___M 0x000FF000 +#define WMAC0_RXPCU_R0_RFF_TSFOOR_CFG__TSF_OOR_THRESH___S 12 +#define WMAC0_RXPCU_R0_RFF_TSFOOR_CFG__OOR_CNT_THRESH___M 0x00000F00 +#define WMAC0_RXPCU_R0_RFF_TSFOOR_CFG__OOR_CNT_THRESH___S 8 +#define WMAC0_RXPCU_R0_RFF_TSFOOR_CFG__OOR_COUNT2___M 0x000000F0 +#define WMAC0_RXPCU_R0_RFF_TSFOOR_CFG__OOR_COUNT2___S 4 +#define WMAC0_RXPCU_R0_RFF_TSFOOR_CFG__OOR_COUNT1___M 0x0000000F +#define WMAC0_RXPCU_R0_RFF_TSFOOR_CFG__OOR_COUNT1___S 0 +#define WMAC0_RXPCU_R0_RFF_TSFOOR_CFG___M 0x000FFFFF +#define WMAC0_RXPCU_R0_RFF_TSFOOR_CFG___S 0 + +#define WMAC0_RXPCU_R0_RFF_MY_RX_FRAME_CNT (0x00A8C17C) +#define WMAC0_RXPCU_R0_RFF_MY_RX_FRAME_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_MY_RX_FRAME_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_MY_RX_FRAME_CNT__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_MY_RX_FRAME_CNT__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_MY_RX_FRAME_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_MY_RX_FRAME_CNT___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_MY_RX_FRAME_CNT___S 0 + +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST0 (0x00A8C180) +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST0___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST0__CE_MODE___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST0__CE_TIME___POR 0x00 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST0__CE_THRESHOLD___POR 0x0000 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST0__CE_MODE___M 0xC0000000 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST0__CE_MODE___S 30 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST0__CE_TIME___M 0x00FF0000 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST0__CE_TIME___S 16 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST0__CE_THRESHOLD___M 0x0000FFFF +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST0__CE_THRESHOLD___S 0 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST0___M 0xC0FFFFFF +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST0___S 0 + +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST1 (0x00A8C184) +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST1___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST1__CE_TIME___POR 0x00 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST1__CE_THRESHOLD___POR 0x0000 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST1__CE_TIME___M 0x00FF0000 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST1__CE_TIME___S 16 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST1__CE_THRESHOLD___M 0x0000FFFF +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST1__CE_THRESHOLD___S 0 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST1___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST1___S 0 + +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST2 (0x00A8C188) +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST2___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST2__CE_TIME___POR 0x00 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST2__CE_THRESHOLD___POR 0x0000 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST2__CE_TIME___M 0x00FF0000 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST2__CE_TIME___S 16 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST2__CE_THRESHOLD___M 0x0000FFFF +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST2__CE_THRESHOLD___S 0 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST2___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST2___S 0 + +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST3 (0x00A8C18C) +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST3___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST3___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST3__CE_TIME___POR 0x00 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST3__CE_THRESHOLD___POR 0x0000 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST3__CE_TIME___M 0x00FF0000 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST3__CE_TIME___S 16 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST3__CE_THRESHOLD___M 0x0000FFFF +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST3__CE_THRESHOLD___S 0 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST3___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST3___S 0 + +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST4 (0x00A8C190) +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST4___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST4___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST4__CE_TIME___POR 0x00 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST4__CE_THRESHOLD___POR 0x0000 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST4__CE_TIME___M 0x00FF0000 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST4__CE_TIME___S 16 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST4__CE_THRESHOLD___M 0x0000FFFF +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST4__CE_THRESHOLD___S 0 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST4___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST4___S 0 + +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST5 (0x00A8C194) +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST5___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST5___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST5__CE_TIME___POR 0x00 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST5__CE_THRESHOLD___POR 0x0000 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST5__CE_TIME___M 0x00FF0000 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST5__CE_TIME___S 16 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST5__CE_THRESHOLD___M 0x0000FFFF +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST5__CE_THRESHOLD___S 0 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST5___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST5___S 0 + +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST6 (0x00A8C198) +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST6___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST6___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST6__CE_TIME___POR 0x00 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST6__CE_THRESHOLD___POR 0x0000 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST6__CE_TIME___M 0x00FF0000 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST6__CE_TIME___S 16 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST6__CE_THRESHOLD___M 0x0000FFFF +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST6__CE_THRESHOLD___S 0 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST6___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST6___S 0 + +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST7 (0x00A8C19C) +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST7___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST7___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST7__CE_TIME___POR 0x00 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST7__CE_THRESHOLD___POR 0x0000 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST7__CE_TIME___M 0x00FF0000 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST7__CE_TIME___S 16 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST7__CE_THRESHOLD___M 0x0000FFFF +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST7__CE_THRESHOLD___S 0 +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST7___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_RFF_CONGEST_EST7___S 0 + +#define WMAC0_RXPCU_R0_RFF_TBTT (0x00A8C1A0) +#define WMAC0_RXPCU_R0_RFF_TBTT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_TBTT___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_TBTT__BCN_COUNT___POR 0x00 +#define WMAC0_RXPCU_R0_RFF_TBTT__BCN_THRESHOLD___POR 0x00 +#define WMAC0_RXPCU_R0_RFF_TBTT__BCN_MISS_COUNT___POR 0x00 +#define WMAC0_RXPCU_R0_RFF_TBTT__BCN_MISS_THRESHOLD___POR 0x00 +#define WMAC0_RXPCU_R0_RFF_TBTT__BCN_COUNT___M 0xFF000000 +#define WMAC0_RXPCU_R0_RFF_TBTT__BCN_COUNT___S 24 +#define WMAC0_RXPCU_R0_RFF_TBTT__BCN_THRESHOLD___M 0x00FF0000 +#define WMAC0_RXPCU_R0_RFF_TBTT__BCN_THRESHOLD___S 16 +#define WMAC0_RXPCU_R0_RFF_TBTT__BCN_MISS_COUNT___M 0x0000FF00 +#define WMAC0_RXPCU_R0_RFF_TBTT__BCN_MISS_COUNT___S 8 +#define WMAC0_RXPCU_R0_RFF_TBTT__BCN_MISS_THRESHOLD___M 0x000000FF +#define WMAC0_RXPCU_R0_RFF_TBTT__BCN_MISS_THRESHOLD___S 0 +#define WMAC0_RXPCU_R0_RFF_TBTT___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_TBTT___S 0 + +#define WMAC0_RXPCU_R0_RFF_TBTT_CFG (0x00A8C1A4) +#define WMAC0_RXPCU_R0_RFF_TBTT_CFG___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_TBTT_CFG___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_TBTT_CFG__RESET_FIELD___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_TBTT_CFG__ABMS_ACTIVE___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_TBTT_CFG__ABMS_WINDOW_SEL___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_TBTT_CFG__RESET_FIELD___M 0x00000008 +#define WMAC0_RXPCU_R0_RFF_TBTT_CFG__RESET_FIELD___S 3 +#define WMAC0_RXPCU_R0_RFF_TBTT_CFG__ABMS_ACTIVE___M 0x00000004 +#define WMAC0_RXPCU_R0_RFF_TBTT_CFG__ABMS_ACTIVE___S 2 +#define WMAC0_RXPCU_R0_RFF_TBTT_CFG__ABMS_WINDOW_SEL___M 0x00000003 +#define WMAC0_RXPCU_R0_RFF_TBTT_CFG__ABMS_WINDOW_SEL___S 0 +#define WMAC0_RXPCU_R0_RFF_TBTT_CFG___M 0x0000000F +#define WMAC0_RXPCU_R0_RFF_TBTT_CFG___S 0 + +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP0 (0x00A8C1A8) +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP0___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP0__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP0__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP0__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP0___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP0___S 0 + +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP1 (0x00A8C1AC) +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP1___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP1__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP1__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP1__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP1___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP1___S 0 + +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP2 (0x00A8C1B0) +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP2___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP2__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP2__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP2__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP2___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP2___S 0 + +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP3 (0x00A8C1B4) +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP3___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP3___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP3__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP3__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP3__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP3___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP3___S 0 + +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP4 (0x00A8C1B8) +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP4___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP4___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP4__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP4__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP4__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP4___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP4___S 0 + +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP5 (0x00A8C1BC) +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP5___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP5___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP5__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP5__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP5__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP5___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP5___S 0 + +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP6 (0x00A8C1C0) +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP6___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP6___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP6__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP6__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP6__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP6___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP6___S 0 + +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP7 (0x00A8C1C4) +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP7___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP7___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP7__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP7__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP7__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP7___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_TBTT_BITMAP7___S 0 + +#define WMAC0_RXPCU_R0_EBT_DEBUG (0x00A8C1C8) +#define WMAC0_RXPCU_R0_EBT_DEBUG___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_EBT_DEBUG___POR 0x00000000 +#define WMAC0_RXPCU_R0_EBT_DEBUG__DTIM_MODE_ACTIVATED___POR 0x0 +#define WMAC0_RXPCU_R0_EBT_DEBUG__STOP_DTIM_MODE___POR 0x0 +#define WMAC0_RXPCU_R0_EBT_DEBUG__PHY_OFF_SYNTH_OFF_SENT___POR 0x0 +#define WMAC0_RXPCU_R0_EBT_DEBUG__SET_PHY_ON___POR 0x0 +#define WMAC0_RXPCU_R0_EBT_DEBUG__DTIM_MODE_ACTIVATED___M 0x00000020 +#define WMAC0_RXPCU_R0_EBT_DEBUG__DTIM_MODE_ACTIVATED___S 5 +#define WMAC0_RXPCU_R0_EBT_DEBUG__STOP_DTIM_MODE___M 0x00000010 +#define WMAC0_RXPCU_R0_EBT_DEBUG__STOP_DTIM_MODE___S 4 +#define WMAC0_RXPCU_R0_EBT_DEBUG__PHY_OFF_SYNTH_OFF_SENT___M 0x00000002 +#define WMAC0_RXPCU_R0_EBT_DEBUG__PHY_OFF_SYNTH_OFF_SENT___S 1 +#define WMAC0_RXPCU_R0_EBT_DEBUG__SET_PHY_ON___M 0x00000001 +#define WMAC0_RXPCU_R0_EBT_DEBUG__SET_PHY_ON___S 0 +#define WMAC0_RXPCU_R0_EBT_DEBUG___M 0x00000033 +#define WMAC0_RXPCU_R0_EBT_DEBUG___S 0 + +#define WMAC0_RXPCU_R0_GSE_GST_BASE_ADDR_LOW (0x00A8C1CC) +#define WMAC0_RXPCU_R0_GSE_GST_BASE_ADDR_LOW___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GSE_GST_BASE_ADDR_LOW___POR 0x00000000 +#define WMAC0_RXPCU_R0_GSE_GST_BASE_ADDR_LOW__VAL___POR 0x00000000 +#define WMAC0_RXPCU_R0_GSE_GST_BASE_ADDR_LOW__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GSE_GST_BASE_ADDR_LOW__VAL___S 0 +#define WMAC0_RXPCU_R0_GSE_GST_BASE_ADDR_LOW___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GSE_GST_BASE_ADDR_LOW___S 0 + +#define WMAC0_RXPCU_R0_GSE_GST_BASE_ADDR_HIGH (0x00A8C1D0) +#define WMAC0_RXPCU_R0_GSE_GST_BASE_ADDR_HIGH___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GSE_GST_BASE_ADDR_HIGH___POR 0x00000000 +#define WMAC0_RXPCU_R0_GSE_GST_BASE_ADDR_HIGH__VAL___POR 0x00 +#define WMAC0_RXPCU_R0_GSE_GST_BASE_ADDR_HIGH__VAL___M 0x000000FF +#define WMAC0_RXPCU_R0_GSE_GST_BASE_ADDR_HIGH__VAL___S 0 +#define WMAC0_RXPCU_R0_GSE_GST_BASE_ADDR_HIGH___M 0x000000FF +#define WMAC0_RXPCU_R0_GSE_GST_BASE_ADDR_HIGH___S 0 + +#define WMAC0_RXPCU_R0_GSE_GST_SIZE (0x00A8C1D4) +#define WMAC0_RXPCU_R0_GSE_GST_SIZE___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GSE_GST_SIZE___POR 0x00000000 +#define WMAC0_RXPCU_R0_GSE_GST_SIZE__VAL___POR 0x00000 +#define WMAC0_RXPCU_R0_GSE_GST_SIZE__VAL___M 0x000FFFFF +#define WMAC0_RXPCU_R0_GSE_GST_SIZE__VAL___S 0 +#define WMAC0_RXPCU_R0_GSE_GST_SIZE___M 0x000FFFFF +#define WMAC0_RXPCU_R0_GSE_GST_SIZE___S 0 + +#define WMAC0_RXPCU_R0_GSE_SEARCH_CTRL (0x00A8C1D8) +#define WMAC0_RXPCU_R0_GSE_SEARCH_CTRL___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GSE_SEARCH_CTRL___POR 0x00003806 +#define WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__TIMEOUT_THRESH___POR 0x0000 +#define WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__CACHE_CMD_READ_BYPASS_EN___POR 0x1 +#define WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__CACHE_WRITE_BACK_FIX_EN___POR 0x1 +#define WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__CACHE_ONLY_ENTRY_CMD_FIX_EN___POR 0x1 +#define WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__CACHE_FAILURES_ENABLE___POR 0x0 +#define WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__CACHE_DISABLE___POR 0x0 +#define WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__SEARCH_SWAP___POR 0x0 +#define WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__MAX_SEARCH___POR 0x06 +#define WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__TIMEOUT_THRESH___M 0xFFFF0000 +#define WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__TIMEOUT_THRESH___S 16 +#define WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__CACHE_CMD_READ_BYPASS_EN___M 0x00002000 +#define WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__CACHE_CMD_READ_BYPASS_EN___S 13 +#define WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__CACHE_WRITE_BACK_FIX_EN___M 0x00001000 +#define WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__CACHE_WRITE_BACK_FIX_EN___S 12 +#define WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__CACHE_ONLY_ENTRY_CMD_FIX_EN___M 0x00000800 +#define WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__CACHE_ONLY_ENTRY_CMD_FIX_EN___S 11 +#define WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__CACHE_FAILURES_ENABLE___M 0x00000400 +#define WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__CACHE_FAILURES_ENABLE___S 10 +#define WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__CACHE_DISABLE___M 0x00000200 +#define WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__CACHE_DISABLE___S 9 +#define WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__SEARCH_SWAP___M 0x00000100 +#define WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__SEARCH_SWAP___S 8 +#define WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__MAX_SEARCH___M 0x000000FF +#define WMAC0_RXPCU_R0_GSE_SEARCH_CTRL__MAX_SEARCH___S 0 +#define WMAC0_RXPCU_R0_GSE_SEARCH_CTRL___M 0xFFFF3FFF +#define WMAC0_RXPCU_R0_GSE_SEARCH_CTRL___S 0 + +#define WMAC0_RXPCU_R0_GSE_WATCHDOG (0x00A8C1DC) +#define WMAC0_RXPCU_R0_GSE_WATCHDOG___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GSE_WATCHDOG___POR 0x0000FFFF +#define WMAC0_RXPCU_R0_GSE_WATCHDOG__STATUS___POR 0x0000 +#define WMAC0_RXPCU_R0_GSE_WATCHDOG__LIMIT___POR 0xFFFF +#define WMAC0_RXPCU_R0_GSE_WATCHDOG__STATUS___M 0xFFFF0000 +#define WMAC0_RXPCU_R0_GSE_WATCHDOG__STATUS___S 16 +#define WMAC0_RXPCU_R0_GSE_WATCHDOG__LIMIT___M 0x0000FFFF +#define WMAC0_RXPCU_R0_GSE_WATCHDOG__LIMIT___S 0 +#define WMAC0_RXPCU_R0_GSE_WATCHDOG___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GSE_WATCHDOG___S 0 + +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE (0x00A8C1E0) +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE___POR 0x00000000 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__CLK_EXTEND___POR 0x0 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__CPU_IF_EXTEND___POR 0x0 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__GSE_RSRVD___POR 0x000000 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__GSE_TOP___POR 0x0 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__CACHE___POR 0x0 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__SLOTS_ARRAY_HASH___POR 0x0 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__APP_RETURN___POR 0x0 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__MEM_RESP2___POR 0x0 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__MEM_RESP1___POR 0x0 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__MEM_ISS2___POR 0x0 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__MEM_ISS1___POR 0x0 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__GSE_CTL___POR 0x0 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__CLK_EXTEND___M 0x80000000 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__CLK_EXTEND___S 31 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__CPU_IF_EXTEND___M 0x40000000 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__CPU_IF_EXTEND___S 30 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__GSE_RSRVD___M 0x3FFFFE00 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__GSE_RSRVD___S 9 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__GSE_TOP___M 0x00000100 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__GSE_TOP___S 8 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__CACHE___M 0x00000080 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__CACHE___S 7 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__SLOTS_ARRAY_HASH___M 0x00000040 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__SLOTS_ARRAY_HASH___S 6 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__APP_RETURN___M 0x00000020 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__APP_RETURN___S 5 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__MEM_RESP2___M 0x00000010 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__MEM_RESP2___S 4 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__MEM_RESP1___M 0x00000008 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__MEM_RESP1___S 3 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__MEM_ISS2___M 0x00000004 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__MEM_ISS2___S 2 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__MEM_ISS1___M 0x00000002 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__MEM_ISS1___S 1 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__GSE_CTL___M 0x00000001 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE__GSE_CTL___S 0 +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GSE_CLKGATE_DISABLE___S 0 + +#define WMAC0_RXPCU_R0_GSE_WRITE_BACK_PENDING (0x00A8C1E4) +#define WMAC0_RXPCU_R0_GSE_WRITE_BACK_PENDING___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_GSE_WRITE_BACK_PENDING___POR 0x00000000 +#define WMAC0_RXPCU_R0_GSE_WRITE_BACK_PENDING__STATUS___POR 0x0 +#define WMAC0_RXPCU_R0_GSE_WRITE_BACK_PENDING__STATUS___M 0x00000001 +#define WMAC0_RXPCU_R0_GSE_WRITE_BACK_PENDING__STATUS___S 0 +#define WMAC0_RXPCU_R0_GSE_WRITE_BACK_PENDING___M 0x00000001 +#define WMAC0_RXPCU_R0_GSE_WRITE_BACK_PENDING___S 0 + +#define WMAC0_RXPCU_R0_ASE_SEARCH_CTRL (0x00A8C1E8) +#define WMAC0_RXPCU_R0_ASE_SEARCH_CTRL___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_ASE_SEARCH_CTRL___POR 0x00000000 +#define WMAC0_RXPCU_R0_ASE_SEARCH_CTRL__MAC_ID___POR 0x0 +#define WMAC0_RXPCU_R0_ASE_SEARCH_CTRL__MAC_ID___M 0x00000003 +#define WMAC0_RXPCU_R0_ASE_SEARCH_CTRL__MAC_ID___S 0 +#define WMAC0_RXPCU_R0_ASE_SEARCH_CTRL___M 0x00000003 +#define WMAC0_RXPCU_R0_ASE_SEARCH_CTRL___S 0 + +#define WMAC0_RXPCU_R0_ASE_HASH_KEY_1 (0x00A8C1EC) +#define WMAC0_RXPCU_R0_ASE_HASH_KEY_1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_ASE_HASH_KEY_1___POR 0x00000000 +#define WMAC0_RXPCU_R0_ASE_HASH_KEY_1__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_ASE_HASH_KEY_1__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_ASE_HASH_KEY_1__VALUE___S 0 +#define WMAC0_RXPCU_R0_ASE_HASH_KEY_1___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_ASE_HASH_KEY_1___S 0 + +#define WMAC0_RXPCU_R0_ASE_HASH_KEY_2 (0x00A8C1F0) +#define WMAC0_RXPCU_R0_ASE_HASH_KEY_2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_ASE_HASH_KEY_2___POR 0x00000000 +#define WMAC0_RXPCU_R0_ASE_HASH_KEY_2__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_ASE_HASH_KEY_2__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_ASE_HASH_KEY_2__VALUE___S 0 +#define WMAC0_RXPCU_R0_ASE_HASH_KEY_2___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_ASE_HASH_KEY_2___S 0 + +#define WMAC0_RXPCU_R0_ASE_HASH_KEY_3 (0x00A8C1F4) +#define WMAC0_RXPCU_R0_ASE_HASH_KEY_3___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_ASE_HASH_KEY_3___POR 0x00000000 +#define WMAC0_RXPCU_R0_ASE_HASH_KEY_3__VALUE___POR 0x00 +#define WMAC0_RXPCU_R0_ASE_HASH_KEY_3__VALUE___M 0x0000001F +#define WMAC0_RXPCU_R0_ASE_HASH_KEY_3__VALUE___S 0 +#define WMAC0_RXPCU_R0_ASE_HASH_KEY_3___M 0x0000001F +#define WMAC0_RXPCU_R0_ASE_HASH_KEY_3___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG (0x00A8C1F8) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__SW_PEER_ID___POR 0x0000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__ALL_FRAMES_SHALL_BE_ENCRYPTED___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__VLAN_LLC_MODE___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__EPD_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__RX_INSERT_VLAN_S_TAG_PADDING___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__STRIP_VLAN_S_TAG_DECAP___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__RX_INSERT_VLAN_C_TAG_PADDING___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__STRIP_VLAN_C_TAG_DECAP___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__DECAP_TYPE___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__KEY_TYPE___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__SW_PEER_ID___M 0xFFFF0000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__SW_PEER_ID___S 16 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__ALL_FRAMES_SHALL_BE_ENCRYPTED___M 0x00001000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__ALL_FRAMES_SHALL_BE_ENCRYPTED___S 12 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__VLAN_LLC_MODE___M 0x00000800 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__VLAN_LLC_MODE___S 11 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__EPD_EN___M 0x00000400 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__EPD_EN___S 10 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__RX_INSERT_VLAN_S_TAG_PADDING___M 0x00000200 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__RX_INSERT_VLAN_S_TAG_PADDING___S 9 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__STRIP_VLAN_S_TAG_DECAP___M 0x00000100 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__STRIP_VLAN_S_TAG_DECAP___S 8 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__RX_INSERT_VLAN_C_TAG_PADDING___M 0x00000080 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__RX_INSERT_VLAN_C_TAG_PADDING___S 7 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__STRIP_VLAN_C_TAG_DECAP___M 0x00000040 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__STRIP_VLAN_C_TAG_DECAP___S 6 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__DECAP_TYPE___M 0x00000030 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__DECAP_TYPE___S 4 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__KEY_TYPE___M 0x0000000F +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG__KEY_TYPE___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG___M 0xFFFF1FFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG_2 (0x00A8C1FC) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG_2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG_2___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG_2__PEER_META_DATA___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG_2__PEER_META_DATA___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG_2__PEER_META_DATA___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG_2___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG_2___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG_3 (0x00A8C200) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG_3___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG_3___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG_3__RXPT_CLASSIFY_INFO___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG_3__RXPT_CLASSIFY_INFO___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG_3__RXPT_CLASSIFY_INFO___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG_3___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_CFG_3___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_31_00 (0x00A8C204) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_31_00___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_31_00___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_31_00__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_31_00__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_31_00__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_31_00___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_31_00___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_63_32 (0x00A8C208) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_63_32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_63_32___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_63_32__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_63_32__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_63_32__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_63_32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_63_32___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_95_64 (0x00A8C20C) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_95_64___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_95_64___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_95_64__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_95_64__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_95_64__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_95_64___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_95_64___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_127_96 (0x00A8C210) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_127_96___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_127_96___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_127_96__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_127_96__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_127_96__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_127_96___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_127_96___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_159_128 (0x00A8C214) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_159_128___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_159_128___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_159_128__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_159_128__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_159_128__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_159_128___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_159_128___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_191_160 (0x00A8C218) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_191_160___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_191_160___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_191_160__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_191_160__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_191_160__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_191_160___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_191_160___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_223_192 (0x00A8C21C) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_223_192___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_223_192___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_223_192__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_223_192__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_223_192__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_223_192___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_223_192___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_255_224 (0x00A8C220) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_255_224___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_255_224___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_255_224__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_255_224__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_255_224__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_255_224___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_A_255_224___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_31_00 (0x00A8C224) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_31_00___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_31_00___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_31_00__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_31_00__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_31_00__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_31_00___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_31_00___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_63_32 (0x00A8C228) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_63_32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_63_32___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_63_32__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_63_32__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_63_32__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_63_32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_63_32___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_95_64 (0x00A8C22C) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_95_64___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_95_64___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_95_64__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_95_64__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_95_64__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_95_64___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_95_64___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_127_96 (0x00A8C230) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_127_96___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_127_96___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_127_96__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_127_96__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_127_96__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_127_96___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_127_96___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_159_128 (0x00A8C234) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_159_128___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_159_128___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_159_128__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_159_128__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_159_128__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_159_128___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_159_128___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_191_160 (0x00A8C238) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_191_160___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_191_160___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_191_160__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_191_160__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_191_160__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_191_160___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_191_160___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_223_192 (0x00A8C23C) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_223_192___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_223_192___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_223_192__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_223_192__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_223_192__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_223_192___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_223_192___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_255_224 (0x00A8C240) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_255_224___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_255_224___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_255_224__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_255_224__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_255_224__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_255_224___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_B_255_224___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_31_00 (0x00A8C244) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_31_00___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_31_00___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_31_00__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_31_00__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_31_00__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_31_00___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_31_00___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_63_32 (0x00A8C248) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_63_32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_63_32___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_63_32__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_63_32__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_63_32__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_63_32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_63_32___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_95_64 (0x00A8C24C) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_95_64___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_95_64___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_95_64__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_95_64__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_95_64__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_95_64___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_95_64___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_127_96 (0x00A8C250) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_127_96___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_127_96___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_127_96__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_127_96__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_127_96__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_127_96___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_127_96___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_159_128 (0x00A8C254) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_159_128___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_159_128___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_159_128__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_159_128__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_159_128__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_159_128___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_159_128___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_191_160 (0x00A8C258) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_191_160___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_191_160___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_191_160__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_191_160__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_191_160__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_191_160___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_191_160___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_223_192 (0x00A8C25C) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_223_192___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_223_192___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_223_192__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_223_192__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_223_192__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_223_192___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_223_192___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_255_224 (0x00A8C260) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_255_224___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_255_224___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_255_224__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_255_224__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_255_224__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_255_224___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_C_255_224___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_31_00 (0x00A8C264) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_31_00___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_31_00___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_31_00__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_31_00__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_31_00__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_31_00___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_31_00___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_63_32 (0x00A8C268) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_63_32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_63_32___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_63_32__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_63_32__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_63_32__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_63_32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_63_32___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_95_64 (0x00A8C26C) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_95_64___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_95_64___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_95_64__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_95_64__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_95_64__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_95_64___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_95_64___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_127_96 (0x00A8C270) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_127_96___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_127_96___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_127_96__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_127_96__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_127_96__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_127_96___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_127_96___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_159_128 (0x00A8C274) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_159_128___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_159_128___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_159_128__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_159_128__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_159_128__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_159_128___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_159_128___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_191_160 (0x00A8C278) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_191_160___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_191_160___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_191_160__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_191_160__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_191_160__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_191_160___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_191_160___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_223_192 (0x00A8C27C) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_223_192___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_223_192___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_223_192__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_223_192__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_223_192__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_223_192___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_223_192___S 0 + +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_255_224 (0x00A8C280) +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_255_224___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_255_224___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_255_224__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_255_224__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_255_224__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_255_224___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RFF_DTIM_KEY_D_255_224___S 0 + +#define WMAC0_RXPCU_R0_MISC_MODE (0x00A8C284) +#define WMAC0_RXPCU_R0_MISC_MODE___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_MISC_MODE___POR 0x00070000 +#define WMAC0_RXPCU_R0_MISC_MODE__TWT_FLOW_CONTROL_ENABLE___POR 0x0 +#define WMAC0_RXPCU_R0_MISC_MODE__ACCEPT_BAT_AS_BA___POR 0x0 +#define WMAC0_RXPCU_R0_MISC_MODE__ACCEPT_TACK_STACK_AS_ACK___POR 0x0 +#define WMAC0_RXPCU_R0_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH___POR 0x0 +#define WMAC0_RXPCU_R0_MISC_MODE__IGNORE_OBSS_NAV_FOR_TXOP_FOR_UORA___POR 0x0 +#define WMAC0_RXPCU_R0_MISC_MODE__IGNORE_INBSS_NAV_FOR_TXOP_SET_BY_STA___POR 0x0 +#define WMAC0_RXPCU_R0_MISC_MODE__IGNORE_OBSS_NAV_FOR_TXOP_SET_BY_STA___POR 0x0 +#define WMAC0_RXPCU_R0_MISC_MODE__CHECK_OBSS_NAV_FOR_ASSOC_UORA___POR 0x1 +#define WMAC0_RXPCU_R0_MISC_MODE__CHECK_INBSS_NAV_FOR_UNASSOC_UORA___POR 0x1 +#define WMAC0_RXPCU_R0_MISC_MODE__MBSSID_MBA_TA_HOLD_BY_TXOP_HOLDER___POR 0x1 +#define WMAC0_RXPCU_R0_MISC_MODE__RXDMA_BLOCK_MPDU_SFM_THRESHOLD___POR 0x00 +#define WMAC0_RXPCU_R0_MISC_MODE__RXDMA_MPDU_DROP_OVERFLOW_INT_EN___POR 0x0 +#define WMAC0_RXPCU_R0_MISC_MODE__LATCH_RXDMA_BLOCK_MPDU___POR 0x0 +#define WMAC0_RXPCU_R0_MISC_MODE__RXDMA_DROP_WHOLE_MPDU___POR 0x0 +#define WMAC0_RXPCU_R0_MISC_MODE__RXDMA_TRUNCATE_MPDU___POR 0x0 +#define WMAC0_RXPCU_R0_MISC_MODE__ACCESS_AST_PTE___POR 0x0 +#define WMAC0_RXPCU_R0_MISC_MODE__BSSID_MATCH_FORCE___POR 0x0 +#define WMAC0_RXPCU_R0_MISC_MODE__TWT_FLOW_CONTROL_ENABLE___M 0x80000000 +#define WMAC0_RXPCU_R0_MISC_MODE__TWT_FLOW_CONTROL_ENABLE___S 31 +#define WMAC0_RXPCU_R0_MISC_MODE__ACCEPT_BAT_AS_BA___M 0x40000000 +#define WMAC0_RXPCU_R0_MISC_MODE__ACCEPT_BAT_AS_BA___S 30 +#define WMAC0_RXPCU_R0_MISC_MODE__ACCEPT_TACK_STACK_AS_ACK___M 0x20000000 +#define WMAC0_RXPCU_R0_MISC_MODE__ACCEPT_TACK_STACK_AS_ACK___S 29 +#define WMAC0_RXPCU_R0_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH___M 0x10000000 +#define WMAC0_RXPCU_R0_MISC_MODE__ALWAYS_PERFORM_KEY_SEARCH___S 28 +#define WMAC0_RXPCU_R0_MISC_MODE__IGNORE_OBSS_NAV_FOR_TXOP_FOR_UORA___M 0x08000000 +#define WMAC0_RXPCU_R0_MISC_MODE__IGNORE_OBSS_NAV_FOR_TXOP_FOR_UORA___S 27 +#define WMAC0_RXPCU_R0_MISC_MODE__IGNORE_INBSS_NAV_FOR_TXOP_SET_BY_STA___M 0x00100000 +#define WMAC0_RXPCU_R0_MISC_MODE__IGNORE_INBSS_NAV_FOR_TXOP_SET_BY_STA___S 20 +#define WMAC0_RXPCU_R0_MISC_MODE__IGNORE_OBSS_NAV_FOR_TXOP_SET_BY_STA___M 0x00080000 +#define WMAC0_RXPCU_R0_MISC_MODE__IGNORE_OBSS_NAV_FOR_TXOP_SET_BY_STA___S 19 +#define WMAC0_RXPCU_R0_MISC_MODE__CHECK_OBSS_NAV_FOR_ASSOC_UORA___M 0x00040000 +#define WMAC0_RXPCU_R0_MISC_MODE__CHECK_OBSS_NAV_FOR_ASSOC_UORA___S 18 +#define WMAC0_RXPCU_R0_MISC_MODE__CHECK_INBSS_NAV_FOR_UNASSOC_UORA___M 0x00020000 +#define WMAC0_RXPCU_R0_MISC_MODE__CHECK_INBSS_NAV_FOR_UNASSOC_UORA___S 17 +#define WMAC0_RXPCU_R0_MISC_MODE__MBSSID_MBA_TA_HOLD_BY_TXOP_HOLDER___M 0x00010000 +#define WMAC0_RXPCU_R0_MISC_MODE__MBSSID_MBA_TA_HOLD_BY_TXOP_HOLDER___S 16 +#define WMAC0_RXPCU_R0_MISC_MODE__RXDMA_BLOCK_MPDU_SFM_THRESHOLD___M 0x0000FF00 +#define WMAC0_RXPCU_R0_MISC_MODE__RXDMA_BLOCK_MPDU_SFM_THRESHOLD___S 8 +#define WMAC0_RXPCU_R0_MISC_MODE__RXDMA_MPDU_DROP_OVERFLOW_INT_EN___M 0x00000020 +#define WMAC0_RXPCU_R0_MISC_MODE__RXDMA_MPDU_DROP_OVERFLOW_INT_EN___S 5 +#define WMAC0_RXPCU_R0_MISC_MODE__LATCH_RXDMA_BLOCK_MPDU___M 0x00000010 +#define WMAC0_RXPCU_R0_MISC_MODE__LATCH_RXDMA_BLOCK_MPDU___S 4 +#define WMAC0_RXPCU_R0_MISC_MODE__RXDMA_DROP_WHOLE_MPDU___M 0x00000008 +#define WMAC0_RXPCU_R0_MISC_MODE__RXDMA_DROP_WHOLE_MPDU___S 3 +#define WMAC0_RXPCU_R0_MISC_MODE__RXDMA_TRUNCATE_MPDU___M 0x00000004 +#define WMAC0_RXPCU_R0_MISC_MODE__RXDMA_TRUNCATE_MPDU___S 2 +#define WMAC0_RXPCU_R0_MISC_MODE__ACCESS_AST_PTE___M 0x00000002 +#define WMAC0_RXPCU_R0_MISC_MODE__ACCESS_AST_PTE___S 1 +#define WMAC0_RXPCU_R0_MISC_MODE__BSSID_MATCH_FORCE___M 0x00000001 +#define WMAC0_RXPCU_R0_MISC_MODE__BSSID_MATCH_FORCE___S 0 +#define WMAC0_RXPCU_R0_MISC_MODE___M 0xF81FFF3F +#define WMAC0_RXPCU_R0_MISC_MODE___S 0 + +#define WMAC0_RXPCU_R0_MISC_MODE2 (0x00A8C288) +#define WMAC0_RXPCU_R0_MISC_MODE2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_MISC_MODE2___POR 0x00100000 +#define WMAC0_RXPCU_R0_MISC_MODE2__MPDU_DENSITY_STS_FIX___POR 0x0 +#define WMAC0_RXPCU_R0_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT___POR 0x0 +#define WMAC0_RXPCU_R0_MISC_MODE2__DISABLE_MONITOR_MODE___POR 0x1 +#define WMAC0_RXPCU_R0_MISC_MODE2__LATCH_RXOLE_BLOCK_MPDU___POR 0x0 +#define WMAC0_RXPCU_R0_MISC_MODE2__RXOLE_DROP_WHOLE_MPDU___POR 0x0 +#define WMAC0_RXPCU_R0_MISC_MODE2__RXOLE_TRUNCATE_MPDU___POR 0x0 +#define WMAC0_RXPCU_R0_MISC_MODE2__RXOLE_BLOCK_MPDU_SFM_THRESHOLD___POR 0x000 +#define WMAC0_RXPCU_R0_MISC_MODE2__MPDU_DENSITY_STS_FIX___M 0x00800000 +#define WMAC0_RXPCU_R0_MISC_MODE2__MPDU_DENSITY_STS_FIX___S 23 +#define WMAC0_RXPCU_R0_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT___M 0x00400000 +#define WMAC0_RXPCU_R0_MISC_MODE2__NO_CRYPTO_FOR_NON_DATA_PKT___S 22 +#define WMAC0_RXPCU_R0_MISC_MODE2__DISABLE_MONITOR_MODE___M 0x00100000 +#define WMAC0_RXPCU_R0_MISC_MODE2__DISABLE_MONITOR_MODE___S 20 +#define WMAC0_RXPCU_R0_MISC_MODE2__LATCH_RXOLE_BLOCK_MPDU___M 0x00002000 +#define WMAC0_RXPCU_R0_MISC_MODE2__LATCH_RXOLE_BLOCK_MPDU___S 13 +#define WMAC0_RXPCU_R0_MISC_MODE2__RXOLE_DROP_WHOLE_MPDU___M 0x00001000 +#define WMAC0_RXPCU_R0_MISC_MODE2__RXOLE_DROP_WHOLE_MPDU___S 12 +#define WMAC0_RXPCU_R0_MISC_MODE2__RXOLE_TRUNCATE_MPDU___M 0x00000800 +#define WMAC0_RXPCU_R0_MISC_MODE2__RXOLE_TRUNCATE_MPDU___S 11 +#define WMAC0_RXPCU_R0_MISC_MODE2__RXOLE_BLOCK_MPDU_SFM_THRESHOLD___M 0x000007FF +#define WMAC0_RXPCU_R0_MISC_MODE2__RXOLE_BLOCK_MPDU_SFM_THRESHOLD___S 0 +#define WMAC0_RXPCU_R0_MISC_MODE2___M 0x00D03FFF +#define WMAC0_RXPCU_R0_MISC_MODE2___S 0 + +#define WMAC0_RXPCU_R0_MISC_MODE3 (0x00A8C28C) +#define WMAC0_RXPCU_R0_MISC_MODE3___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_MISC_MODE3___POR 0x00901900 +#define WMAC0_RXPCU_R0_MISC_MODE3__KEY_MISS_FIX___POR 0x0 +#define WMAC0_RXPCU_R0_MISC_MODE3__BEACON_FROM_TO_DS_CHECK___POR 0x1 +#define WMAC0_RXPCU_R0_MISC_MODE3__ALLOW_RAC___POR 0x0 +#define WMAC0_RXPCU_R0_MISC_MODE3__RA_BASED_HE_SOUNDING___POR 0x1 +#define WMAC0_RXPCU_R0_MISC_MODE3__NDPA_BRPOLL_SIFS_VALUE___POR 0x19 +#define WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID8___POR 0x0 +#define WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID7___POR 0x0 +#define WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID6___POR 0x0 +#define WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID5___POR 0x0 +#define WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID4___POR 0x0 +#define WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID3___POR 0x0 +#define WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID2___POR 0x0 +#define WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID1___POR 0x0 +#define WMAC0_RXPCU_R0_MISC_MODE3__KEY_MISS_FIX___M 0x20000000 +#define WMAC0_RXPCU_R0_MISC_MODE3__KEY_MISS_FIX___S 29 +#define WMAC0_RXPCU_R0_MISC_MODE3__BEACON_FROM_TO_DS_CHECK___M 0x00800000 +#define WMAC0_RXPCU_R0_MISC_MODE3__BEACON_FROM_TO_DS_CHECK___S 23 +#define WMAC0_RXPCU_R0_MISC_MODE3__ALLOW_RAC___M 0x00200000 +#define WMAC0_RXPCU_R0_MISC_MODE3__ALLOW_RAC___S 21 +#define WMAC0_RXPCU_R0_MISC_MODE3__RA_BASED_HE_SOUNDING___M 0x00100000 +#define WMAC0_RXPCU_R0_MISC_MODE3__RA_BASED_HE_SOUNDING___S 20 +#define WMAC0_RXPCU_R0_MISC_MODE3__NDPA_BRPOLL_SIFS_VALUE___M 0x00007F00 +#define WMAC0_RXPCU_R0_MISC_MODE3__NDPA_BRPOLL_SIFS_VALUE___S 8 +#define WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID8___M 0x00000080 +#define WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID8___S 7 +#define WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID7___M 0x00000040 +#define WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID7___S 6 +#define WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID6___M 0x00000020 +#define WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID6___S 5 +#define WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID5___M 0x00000010 +#define WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID5___S 4 +#define WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID4___M 0x00000008 +#define WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID4___S 3 +#define WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID3___M 0x00000004 +#define WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID3___S 2 +#define WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID2___M 0x00000002 +#define WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID2___S 1 +#define WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID1___M 0x00000001 +#define WMAC0_RXPCU_R0_MISC_MODE3__SNOOP_BSSID1___S 0 +#define WMAC0_RXPCU_R0_MISC_MODE3___M 0x20B07FFF +#define WMAC0_RXPCU_R0_MISC_MODE3___S 0 + +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4 (0x00A8C290) +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4___POR 0x01001080 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__RX_CLEAR_PRI_PULL_PERIOD___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__FCS_BASED_MPDU_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__PPDU_END_USER_STATS_QOS_DATA_ONLY___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__FRAME_GROUP_ID_NULL_DATA___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__ACCEPT_ONLY_FIRST_BEACON_IN_TBTT_INTERVAL___POR 0x1 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__ENABLE_RX_PACKET_MPDU_END_B2B_FIX___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__DISABLE_LSIG_A_PKT_TYPE___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__DISABLE_ROUTE_MUBAR_TO_REO___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__ENABLE_PHY_ERR_FILTER_CHECK___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__DISABLE_QUALIFY_RA_FOR_AST___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__SET_PHY_ERR_DURING_MPDU_HEADER___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__FILTER_IN_MC_BC_CTRL_PKT___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__USE_11AC_TIM_FOR_S1G___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__HT_RTS_PIFS_CHECK_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__HT_RTS_DYNAMIC_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__ACK_TO_PCF_HCF_EN___POR 0x1 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__EIFS_FOR_MU_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__PEER_ENTRY_SWAP___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__IGNORE_FCS_ERR_FOR_EIFS___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__ALWAYS_REQ_IMPLICIT_FB___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__LP_SYNTH_WARMUP_EN___POR 0x1 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__LP_SYNTH_FOR_DIRECTED_UNICAST_FRAME___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__RX_CLEAR_PRI_PULL_PERIOD___M 0xF0000000 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__RX_CLEAR_PRI_PULL_PERIOD___S 28 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__FCS_BASED_MPDU_DROP___M 0x08000000 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__FCS_BASED_MPDU_DROP___S 27 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__PPDU_END_USER_STATS_QOS_DATA_ONLY___M 0x04000000 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__PPDU_END_USER_STATS_QOS_DATA_ONLY___S 26 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__FRAME_GROUP_ID_NULL_DATA___M 0x02000000 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__FRAME_GROUP_ID_NULL_DATA___S 25 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__ACCEPT_ONLY_FIRST_BEACON_IN_TBTT_INTERVAL___M 0x01000000 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__ACCEPT_ONLY_FIRST_BEACON_IN_TBTT_INTERVAL___S 24 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__ENABLE_RX_PACKET_MPDU_END_B2B_FIX___M 0x00400000 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__ENABLE_RX_PACKET_MPDU_END_B2B_FIX___S 22 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__DISABLE_LSIG_A_PKT_TYPE___M 0x00200000 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__DISABLE_LSIG_A_PKT_TYPE___S 21 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__DISABLE_ROUTE_MUBAR_TO_REO___M 0x00100000 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__DISABLE_ROUTE_MUBAR_TO_REO___S 20 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__ENABLE_PHY_ERR_FILTER_CHECK___M 0x00080000 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__ENABLE_PHY_ERR_FILTER_CHECK___S 19 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__DISABLE_QUALIFY_RA_FOR_AST___M 0x00040000 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__DISABLE_QUALIFY_RA_FOR_AST___S 18 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__SET_PHY_ERR_DURING_MPDU_HEADER___M 0x00020000 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__SET_PHY_ERR_DURING_MPDU_HEADER___S 17 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__FILTER_IN_MC_BC_CTRL_PKT___M 0x00010000 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__FILTER_IN_MC_BC_CTRL_PKT___S 16 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__USE_11AC_TIM_FOR_S1G___M 0x00008000 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__USE_11AC_TIM_FOR_S1G___S 15 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__HT_RTS_PIFS_CHECK_EN___M 0x00004000 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__HT_RTS_PIFS_CHECK_EN___S 14 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__HT_RTS_DYNAMIC_EN___M 0x00002000 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__HT_RTS_DYNAMIC_EN___S 13 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__ACK_TO_PCF_HCF_EN___M 0x00001000 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__ACK_TO_PCF_HCF_EN___S 12 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__EIFS_FOR_MU_EN___M 0x00000800 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__EIFS_FOR_MU_EN___S 11 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__PEER_ENTRY_SWAP___M 0x00000400 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__PEER_ENTRY_SWAP___S 10 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__IGNORE_FCS_ERR_FOR_EIFS___M 0x00000200 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__IGNORE_FCS_ERR_FOR_EIFS___S 9 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__ALWAYS_REQ_IMPLICIT_FB___M 0x00000100 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__ALWAYS_REQ_IMPLICIT_FB___S 8 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__LP_SYNTH_WARMUP_EN___M 0x00000080 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__LP_SYNTH_WARMUP_EN___S 7 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__LP_SYNTH_FOR_DIRECTED_UNICAST_FRAME___M 0x00000040 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4__LP_SYNTH_FOR_DIRECTED_UNICAST_FRAME___S 6 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4___M 0xFF7FFFC0 +#define WMAC0_RXPCU_R0_RFF_MISC_MODE4___S 6 + +#define WMAC0_RXPCU_R0_DIAGNOSTIC_MODE (0x00A8C294) +#define WMAC0_RXPCU_R0_DIAGNOSTIC_MODE___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_DIAGNOSTIC_MODE___POR 0x00000000 +#define WMAC0_RXPCU_R0_DIAGNOSTIC_MODE__RXBUF_DEBUG_EN___POR 0x0 +#define WMAC0_RXPCU_R0_DIAGNOSTIC_MODE__RXBUF_DEBUG_EN___M 0x00000002 +#define WMAC0_RXPCU_R0_DIAGNOSTIC_MODE__RXBUF_DEBUG_EN___S 1 +#define WMAC0_RXPCU_R0_DIAGNOSTIC_MODE___M 0x00000002 +#define WMAC0_RXPCU_R0_DIAGNOSTIC_MODE___S 1 + +#define WMAC0_RXPCU_R0_WATCHDOG (0x00A8C298) +#define WMAC0_RXPCU_R0_WATCHDOG___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_WATCHDOG___POR 0x0000FFFF +#define WMAC0_RXPCU_R0_WATCHDOG__STATUS___POR 0x0000 +#define WMAC0_RXPCU_R0_WATCHDOG__LIMIT___POR 0xFFFF +#define WMAC0_RXPCU_R0_WATCHDOG__STATUS___M 0xFFFF0000 +#define WMAC0_RXPCU_R0_WATCHDOG__STATUS___S 16 +#define WMAC0_RXPCU_R0_WATCHDOG__LIMIT___M 0x0000FFFF +#define WMAC0_RXPCU_R0_WATCHDOG__LIMIT___S 0 +#define WMAC0_RXPCU_R0_WATCHDOG___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_WATCHDOG___S 0 + +#define WMAC0_RXPCU_R0_FCS_FAIL_CNT (0x00A8C29C) +#define WMAC0_RXPCU_R0_FCS_FAIL_CNT___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_FCS_FAIL_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R0_FCS_FAIL_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R0_FCS_FAIL_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R0_FCS_FAIL_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R0_FCS_FAIL_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R0_FCS_FAIL_CNT___S 0 + +#define WMAC0_RXPCU_R0_RFF_BEACON_CNT (0x00A8C2A0) +#define WMAC0_RXPCU_R0_RFF_BEACON_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_BEACON_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_BEACON_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R0_RFF_BEACON_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R0_RFF_BEACON_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R0_RFF_BEACON_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R0_RFF_BEACON_CNT___S 0 + +#define WMAC0_RXPCU_R0_BEACON2_CNT (0x00A8C2A4) +#define WMAC0_RXPCU_R0_BEACON2_CNT___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_BEACON2_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R0_BEACON2_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R0_BEACON2_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R0_BEACON2_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R0_BEACON2_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R0_BEACON2_CNT___S 0 + +#define WMAC0_RXPCU_R0_FILTER_OFDM_CNT (0x00A8C2A8) +#define WMAC0_RXPCU_R0_FILTER_OFDM_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_FILTER_OFDM_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R0_FILTER_OFDM_CNT__VALUE___POR 0x000000 +#define WMAC0_RXPCU_R0_FILTER_OFDM_CNT__VALUE___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_FILTER_OFDM_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R0_FILTER_OFDM_CNT___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_FILTER_OFDM_CNT___S 0 + +#define WMAC0_RXPCU_R0_FILTER_CCK_CNT (0x00A8C2AC) +#define WMAC0_RXPCU_R0_FILTER_CCK_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_FILTER_CCK_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R0_FILTER_CCK_CNT__VALUE___POR 0x000000 +#define WMAC0_RXPCU_R0_FILTER_CCK_CNT__VALUE___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_FILTER_CCK_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R0_FILTER_CCK_CNT___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_FILTER_CCK_CNT___S 0 + +#define WMAC0_RXPCU_R0_SIFS_RESP_CTRL (0x00A8C2B0) +#define WMAC0_RXPCU_R0_SIFS_RESP_CTRL___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SIFS_RESP_CTRL___POR 0x00005500 +#define WMAC0_RXPCU_R0_SIFS_RESP_CTRL__PSPOLL_EN_DIS_ULMU___POR 0x0 +#define WMAC0_RXPCU_R0_SIFS_RESP_CTRL__TRIGGER_WAIT_SIFS___POR 0x1 +#define WMAC0_RXPCU_R0_SIFS_RESP_CTRL__OTHERS_WAIT_SIFS___POR 0x1 +#define WMAC0_RXPCU_R0_SIFS_RESP_CTRL__FTM_WAIT_SIFS___POR 0x1 +#define WMAC0_RXPCU_R0_SIFS_RESP_CTRL__TM_WAIT_SIFS___POR 0x1 +#define WMAC0_RXPCU_R0_SIFS_RESP_CTRL__UL_TRIGGER_EN___POR 0x0 +#define WMAC0_RXPCU_R0_SIFS_RESP_CTRL__QBOOST_EN___POR 0x0 +#define WMAC0_RXPCU_R0_SIFS_RESP_CTRL__PSPOLL_EN___POR 0x0 +#define WMAC0_RXPCU_R0_SIFS_RESP_CTRL__UAPSD_EN___POR 0x0 +#define WMAC0_RXPCU_R0_SIFS_RESP_CTRL__PSPOLL_EN_DIS_ULMU___M 0x00010000 +#define WMAC0_RXPCU_R0_SIFS_RESP_CTRL__PSPOLL_EN_DIS_ULMU___S 16 +#define WMAC0_RXPCU_R0_SIFS_RESP_CTRL__TRIGGER_WAIT_SIFS___M 0x0000C000 +#define WMAC0_RXPCU_R0_SIFS_RESP_CTRL__TRIGGER_WAIT_SIFS___S 14 +#define WMAC0_RXPCU_R0_SIFS_RESP_CTRL__OTHERS_WAIT_SIFS___M 0x00003000 +#define WMAC0_RXPCU_R0_SIFS_RESP_CTRL__OTHERS_WAIT_SIFS___S 12 +#define WMAC0_RXPCU_R0_SIFS_RESP_CTRL__FTM_WAIT_SIFS___M 0x00000C00 +#define WMAC0_RXPCU_R0_SIFS_RESP_CTRL__FTM_WAIT_SIFS___S 10 +#define WMAC0_RXPCU_R0_SIFS_RESP_CTRL__TM_WAIT_SIFS___M 0x00000300 +#define WMAC0_RXPCU_R0_SIFS_RESP_CTRL__TM_WAIT_SIFS___S 8 +#define WMAC0_RXPCU_R0_SIFS_RESP_CTRL__UL_TRIGGER_EN___M 0x00000008 +#define WMAC0_RXPCU_R0_SIFS_RESP_CTRL__UL_TRIGGER_EN___S 3 +#define WMAC0_RXPCU_R0_SIFS_RESP_CTRL__QBOOST_EN___M 0x00000004 +#define WMAC0_RXPCU_R0_SIFS_RESP_CTRL__QBOOST_EN___S 2 +#define WMAC0_RXPCU_R0_SIFS_RESP_CTRL__PSPOLL_EN___M 0x00000002 +#define WMAC0_RXPCU_R0_SIFS_RESP_CTRL__PSPOLL_EN___S 1 +#define WMAC0_RXPCU_R0_SIFS_RESP_CTRL__UAPSD_EN___M 0x00000001 +#define WMAC0_RXPCU_R0_SIFS_RESP_CTRL__UAPSD_EN___S 0 +#define WMAC0_RXPCU_R0_SIFS_RESP_CTRL___M 0x0001FF0F +#define WMAC0_RXPCU_R0_SIFS_RESP_CTRL___S 0 + +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS (0x00A8C2B4) +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS___POR 0x00000000 +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS__SEQUENCE_CONTROL___POR 0x0000 +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS__QOS_CONTROL___POR 0x0000 +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS__SEQUENCE_CONTROL___M 0xFFFF0000 +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS__SEQUENCE_CONTROL___S 16 +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS__QOS_CONTROL___M 0x0000FFFF +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS__QOS_CONTROL___S 0 +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS___S 0 + +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS2 (0x00A8C2B8) +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS2___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS2___POR 0x00000000 +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS2__BW___POR 0x0 +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS2__AST_IDX___POR 0x0000 +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS2__BW___M 0x00070000 +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS2__BW___S 16 +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS2__AST_IDX___M 0x0000FFFF +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS2__AST_IDX___S 0 +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS2___M 0x0007FFFF +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS2___S 0 + +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS3 (0x00A8C2BC) +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS3___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS3___POR 0x00000000 +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS3__AID___POR 0x0000 +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS3__FRAME_CONTOL___POR 0x0000 +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS3__AID___M 0xFFFF0000 +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS3__AID___S 16 +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS3__FRAME_CONTOL___M 0x0000FFFF +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS3__FRAME_CONTOL___S 0 +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS3___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS3___S 0 + +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_n(n) (0x00A8C2C0+0x4*(n)) +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_n_nMIN 0 +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_n_nMAX 1 +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_n_ELEM 2 +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_n___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_n___POR 0x00000000 +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_n__TIMESTAMP___POR 0x00000000 +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_n__TIMESTAMP___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_n__TIMESTAMP___S 0 +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_n___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_n___S 0 +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_0 (0x00A8C2C0) +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_0___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_0__TIMESTAMP___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_0__TIMESTAMP___S 0 +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_1 (0x00A8C2C4) +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_1___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_1__TIMESTAMP___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SIFS_RESP_STATUS4_1__TIMESTAMP___S 0 + +#define WMAC0_RXPCU_R0_COEX_BCAST_NON_PAIRED_CNT (0x00A8C2C8) +#define WMAC0_RXPCU_R0_COEX_BCAST_NON_PAIRED_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_COEX_BCAST_NON_PAIRED_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R0_COEX_BCAST_NON_PAIRED_CNT__VALUE___POR 0x00 +#define WMAC0_RXPCU_R0_COEX_BCAST_NON_PAIRED_CNT__VALUE___M 0x000000FF +#define WMAC0_RXPCU_R0_COEX_BCAST_NON_PAIRED_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R0_COEX_BCAST_NON_PAIRED_CNT___M 0x000000FF +#define WMAC0_RXPCU_R0_COEX_BCAST_NON_PAIRED_CNT___S 0 + +#define WMAC0_RXPCU_R0_TX_PKT_END_ERR_CNT (0x00A8C2CC) +#define WMAC0_RXPCU_R0_TX_PKT_END_ERR_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_TX_PKT_END_ERR_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R0_TX_PKT_END_ERR_CNT__VALUE___POR 0x00 +#define WMAC0_RXPCU_R0_TX_PKT_END_ERR_CNT__VALUE___M 0x000000FF +#define WMAC0_RXPCU_R0_TX_PKT_END_ERR_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R0_TX_PKT_END_ERR_CNT___M 0x000000FF +#define WMAC0_RXPCU_R0_TX_PKT_END_ERR_CNT___S 0 + +#define WMAC0_RXPCU_R0_PHY_ERROR_MASK (0x00A8C2D0) +#define WMAC0_RXPCU_R0_PHY_ERROR_MASK___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_PHY_ERROR_MASK___POR 0x00000000 +#define WMAC0_RXPCU_R0_PHY_ERROR_MASK__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_PHY_ERROR_MASK__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PHY_ERROR_MASK__VALUE___S 0 +#define WMAC0_RXPCU_R0_PHY_ERROR_MASK___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PHY_ERROR_MASK___S 0 + +#define WMAC0_RXPCU_R0_PHY_ERROR_MASK_CONT (0x00A8C2D4) +#define WMAC0_RXPCU_R0_PHY_ERROR_MASK_CONT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_PHY_ERROR_MASK_CONT___POR 0x00000000 +#define WMAC0_RXPCU_R0_PHY_ERROR_MASK_CONT__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_PHY_ERROR_MASK_CONT__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PHY_ERROR_MASK_CONT__VALUE___S 0 +#define WMAC0_RXPCU_R0_PHY_ERROR_MASK_CONT___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PHY_ERROR_MASK_CONT___S 0 + +#define WMAC0_RXPCU_R0_PHY_ERROR_EIFS_MASK (0x00A8C2D8) +#define WMAC0_RXPCU_R0_PHY_ERROR_EIFS_MASK___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_PHY_ERROR_EIFS_MASK___POR 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PHY_ERROR_EIFS_MASK__VALUE___POR 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PHY_ERROR_EIFS_MASK__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PHY_ERROR_EIFS_MASK__VALUE___S 0 +#define WMAC0_RXPCU_R0_PHY_ERROR_EIFS_MASK___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PHY_ERROR_EIFS_MASK___S 0 + +#define WMAC0_RXPCU_R0_PHY_ERROR_EIFS_MASK_CONT (0x00A8C2DC) +#define WMAC0_RXPCU_R0_PHY_ERROR_EIFS_MASK_CONT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_PHY_ERROR_EIFS_MASK_CONT___POR 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PHY_ERROR_EIFS_MASK_CONT__VALUE___POR 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PHY_ERROR_EIFS_MASK_CONT__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PHY_ERROR_EIFS_MASK_CONT__VALUE___S 0 +#define WMAC0_RXPCU_R0_PHY_ERROR_EIFS_MASK_CONT___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PHY_ERROR_EIFS_MASK_CONT___S 0 + +#define WMAC0_RXPCU_R0_PHY_ERROR_AIFS (0x00A8C2E0) +#define WMAC0_RXPCU_R0_PHY_ERROR_AIFS___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_PHY_ERROR_AIFS___POR 0x00000000 +#define WMAC0_RXPCU_R0_PHY_ERROR_AIFS__MASK_ENABLE___POR 0x0 +#define WMAC0_RXPCU_R0_PHY_ERROR_AIFS__MASK_ENABLE___M 0x00000001 +#define WMAC0_RXPCU_R0_PHY_ERROR_AIFS__MASK_ENABLE___S 0 +#define WMAC0_RXPCU_R0_PHY_ERROR_AIFS___M 0x00000001 +#define WMAC0_RXPCU_R0_PHY_ERROR_AIFS___S 0 + +#define WMAC0_RXPCU_R0_PHY_ERROR_AIFS_MASK (0x00A8C2E4) +#define WMAC0_RXPCU_R0_PHY_ERROR_AIFS_MASK___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_PHY_ERROR_AIFS_MASK___POR 0x00000000 +#define WMAC0_RXPCU_R0_PHY_ERROR_AIFS_MASK__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_PHY_ERROR_AIFS_MASK__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PHY_ERROR_AIFS_MASK__VALUE___S 0 +#define WMAC0_RXPCU_R0_PHY_ERROR_AIFS_MASK___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PHY_ERROR_AIFS_MASK___S 0 + +#define WMAC0_RXPCU_R0_PHY_ERROR_AIFS_MASK_CONT (0x00A8C2E8) +#define WMAC0_RXPCU_R0_PHY_ERROR_AIFS_MASK_CONT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_PHY_ERROR_AIFS_MASK_CONT___POR 0x00000000 +#define WMAC0_RXPCU_R0_PHY_ERROR_AIFS_MASK_CONT__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_PHY_ERROR_AIFS_MASK_CONT__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PHY_ERROR_AIFS_MASK_CONT__VALUE___S 0 +#define WMAC0_RXPCU_R0_PHY_ERROR_AIFS_MASK_CONT___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PHY_ERROR_AIFS_MASK_CONT___S 0 + +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_1 (0x00A8C2EC) +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_1___POR 0x00000000 +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_1__VALUE___POR 0x000000 +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_1__VALUE___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_1__VALUE___S 0 +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_1___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_1___S 0 + +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_1_MASK (0x00A8C2F0) +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_1_MASK___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_1_MASK___POR 0x00000000 +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_1_MASK__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_1_MASK__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_1_MASK__VALUE___S 0 +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_1_MASK___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_1_MASK___S 0 + +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_1_MASK_CONT (0x00A8C2F4) +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_1_MASK_CONT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_1_MASK_CONT___POR 0x00000000 +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_1_MASK_CONT__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_1_MASK_CONT__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_1_MASK_CONT__VALUE___S 0 +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_1_MASK_CONT___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_1_MASK_CONT___S 0 + +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_2 (0x00A8C2F8) +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_2___POR 0x00000000 +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_2__VALUE___POR 0x000000 +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_2__VALUE___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_2__VALUE___S 0 +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_2___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_2___S 0 + +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_2_MASK (0x00A8C2FC) +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_2_MASK___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_2_MASK___POR 0x00000000 +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_2_MASK__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_2_MASK__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_2_MASK__VALUE___S 0 +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_2_MASK___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_2_MASK___S 0 + +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_2_MASK_CONT (0x00A8C300) +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_2_MASK_CONT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_2_MASK_CONT___POR 0x00000000 +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_2_MASK_CONT__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_2_MASK_CONT__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_2_MASK_CONT__VALUE___S 0 +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_2_MASK_CONT___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_2_MASK_CONT___S 0 + +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_3 (0x00A8C304) +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_3___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_3___POR 0x00000000 +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_3__VALUE___POR 0x000000 +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_3__VALUE___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_3__VALUE___S 0 +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_3___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_3___S 0 + +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_3_MASK (0x00A8C308) +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_3_MASK___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_3_MASK___POR 0x00000000 +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_3_MASK__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_3_MASK__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_3_MASK__VALUE___S 0 +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_3_MASK___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_3_MASK___S 0 + +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_3_MASK_CONT (0x00A8C30C) +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_3_MASK_CONT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_3_MASK_CONT___POR 0x00000000 +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_3_MASK_CONT__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_3_MASK_CONT__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_3_MASK_CONT__VALUE___S 0 +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_3_MASK_CONT___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PHY_ERR_CNT_3_MASK_CONT___S 0 + +#define WMAC0_RXPCU_R0_SPARE_REG1 (0x00A8C310) +#define WMAC0_RXPCU_R0_SPARE_REG1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SPARE_REG1___POR 0x00000000 +#define WMAC0_RXPCU_R0_SPARE_REG1__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_SPARE_REG1__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SPARE_REG1__VALUE___S 0 +#define WMAC0_RXPCU_R0_SPARE_REG1___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SPARE_REG1___S 0 + +#define WMAC0_RXPCU_R0_SPARE_REG2 (0x00A8C314) +#define WMAC0_RXPCU_R0_SPARE_REG2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SPARE_REG2___POR 0x00000000 +#define WMAC0_RXPCU_R0_SPARE_REG2__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_SPARE_REG2__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SPARE_REG2__VALUE___S 0 +#define WMAC0_RXPCU_R0_SPARE_REG2___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SPARE_REG2___S 0 + +#define WMAC0_RXPCU_R0_INVALID_APB_ACC_ADR (0x00A8C318) +#define WMAC0_RXPCU_R0_INVALID_APB_ACC_ADR___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_INVALID_APB_ACC_ADR___POR 0x00000000 +#define WMAC0_RXPCU_R0_INVALID_APB_ACC_ADR__VALUE___POR 0x00000 +#define WMAC0_RXPCU_R0_INVALID_APB_ACC_ADR__VALUE___M 0x0001FFFF +#define WMAC0_RXPCU_R0_INVALID_APB_ACC_ADR__VALUE___S 0 +#define WMAC0_RXPCU_R0_INVALID_APB_ACC_ADR___M 0x0001FFFF +#define WMAC0_RXPCU_R0_INVALID_APB_ACC_ADR___S 0 + +#define WMAC0_RXPCU_R0_PREFETCH_STATUS (0x00A8C31C) +#define WMAC0_RXPCU_R0_PREFETCH_STATUS___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_PREFETCH_STATUS___POR 0x00000000 +#define WMAC0_RXPCU_R0_PREFETCH_STATUS__FAIL_DETECTED___POR 0x0 +#define WMAC0_RXPCU_R0_PREFETCH_STATUS__PTE_PTR___POR 0x0000000 +#define WMAC0_RXPCU_R0_PREFETCH_STATUS__USER_ID___POR 0x00 +#define WMAC0_RXPCU_R0_PREFETCH_STATUS__FAIL_DETECTED___M 0x80000000 +#define WMAC0_RXPCU_R0_PREFETCH_STATUS__FAIL_DETECTED___S 31 +#define WMAC0_RXPCU_R0_PREFETCH_STATUS__PTE_PTR___M 0x7FFFFFC0 +#define WMAC0_RXPCU_R0_PREFETCH_STATUS__PTE_PTR___S 6 +#define WMAC0_RXPCU_R0_PREFETCH_STATUS__USER_ID___M 0x0000003F +#define WMAC0_RXPCU_R0_PREFETCH_STATUS__USER_ID___S 0 +#define WMAC0_RXPCU_R0_PREFETCH_STATUS___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PREFETCH_STATUS___S 0 + +#define WMAC0_RXPCU_R0_FCS_DEBUG (0x00A8C320) +#define WMAC0_RXPCU_R0_FCS_DEBUG___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_FCS_DEBUG___POR 0x00000000 +#define WMAC0_RXPCU_R0_FCS_DEBUG__SRP_TRIGGER_MISMATCH_CNT___POR 0x00 +#define WMAC0_RXPCU_R0_FCS_DEBUG__SRP_TRIGGER_MATCH_CNT___POR 0x00 +#define WMAC0_RXPCU_R0_FCS_DEBUG__FCS_CNT___POR 0x0000 +#define WMAC0_RXPCU_R0_FCS_DEBUG__SRP_TRIGGER_MISMATCH_CNT___M 0xFF000000 +#define WMAC0_RXPCU_R0_FCS_DEBUG__SRP_TRIGGER_MISMATCH_CNT___S 24 +#define WMAC0_RXPCU_R0_FCS_DEBUG__SRP_TRIGGER_MATCH_CNT___M 0x00FF0000 +#define WMAC0_RXPCU_R0_FCS_DEBUG__SRP_TRIGGER_MATCH_CNT___S 16 +#define WMAC0_RXPCU_R0_FCS_DEBUG__FCS_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R0_FCS_DEBUG__FCS_CNT___S 0 +#define WMAC0_RXPCU_R0_FCS_DEBUG___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_FCS_DEBUG___S 0 + +#define WMAC0_RXPCU_R0_SR_HAPPEN_DEBUG (0x00A8C324) +#define WMAC0_RXPCU_R0_SR_HAPPEN_DEBUG___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_SR_HAPPEN_DEBUG___POR 0x00000000 +#define WMAC0_RXPCU_R0_SR_HAPPEN_DEBUG__OBSS_RSSI___POR 0x00 +#define WMAC0_RXPCU_R0_SR_HAPPEN_DEBUG__NON_SRG_OBSS_CNT___POR 0x00 +#define WMAC0_RXPCU_R0_SR_HAPPEN_DEBUG__SRG_OBSS_CNT___POR 0x00 +#define WMAC0_RXPCU_R0_SR_HAPPEN_DEBUG__SRP_HE_TB_CNT___POR 0x00 +#define WMAC0_RXPCU_R0_SR_HAPPEN_DEBUG__OBSS_RSSI___M 0xFF000000 +#define WMAC0_RXPCU_R0_SR_HAPPEN_DEBUG__OBSS_RSSI___S 24 +#define WMAC0_RXPCU_R0_SR_HAPPEN_DEBUG__NON_SRG_OBSS_CNT___M 0x00FF0000 +#define WMAC0_RXPCU_R0_SR_HAPPEN_DEBUG__NON_SRG_OBSS_CNT___S 16 +#define WMAC0_RXPCU_R0_SR_HAPPEN_DEBUG__SRG_OBSS_CNT___M 0x0000FF00 +#define WMAC0_RXPCU_R0_SR_HAPPEN_DEBUG__SRG_OBSS_CNT___S 8 +#define WMAC0_RXPCU_R0_SR_HAPPEN_DEBUG__SRP_HE_TB_CNT___M 0x000000FF +#define WMAC0_RXPCU_R0_SR_HAPPEN_DEBUG__SRP_HE_TB_CNT___S 0 +#define WMAC0_RXPCU_R0_SR_HAPPEN_DEBUG___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SR_HAPPEN_DEBUG___S 0 + +#define WMAC0_RXPCU_R0_OBSS_PKT_DEBUG (0x00A8C328) +#define WMAC0_RXPCU_R0_OBSS_PKT_DEBUG___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_OBSS_PKT_DEBUG___POR 0x00000000 +#define WMAC0_RXPCU_R0_OBSS_PKT_DEBUG__OBSS_BSSID_CNT___POR 0x0000 +#define WMAC0_RXPCU_R0_OBSS_PKT_DEBUG__OBSS_COLOR_CNT___POR 0x0000 +#define WMAC0_RXPCU_R0_OBSS_PKT_DEBUG__OBSS_BSSID_CNT___M 0xFFFF0000 +#define WMAC0_RXPCU_R0_OBSS_PKT_DEBUG__OBSS_BSSID_CNT___S 16 +#define WMAC0_RXPCU_R0_OBSS_PKT_DEBUG__OBSS_COLOR_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R0_OBSS_PKT_DEBUG__OBSS_COLOR_CNT___S 0 +#define WMAC0_RXPCU_R0_OBSS_PKT_DEBUG___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_OBSS_PKT_DEBUG___S 0 + +#define WMAC0_RXPCU_R0_SRP_DUR_DEBUG (0x00A8C32C) +#define WMAC0_RXPCU_R0_SRP_DUR_DEBUG___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_SRP_DUR_DEBUG___POR 0x00000000 +#define WMAC0_RXPCU_R0_SRP_DUR_DEBUG__SRP_VLD_DUR___POR 0x0000 +#define WMAC0_RXPCU_R0_SRP_DUR_DEBUG__SRP_OP_DUR___POR 0x0000 +#define WMAC0_RXPCU_R0_SRP_DUR_DEBUG__SRP_VLD_DUR___M 0xFFFF0000 +#define WMAC0_RXPCU_R0_SRP_DUR_DEBUG__SRP_VLD_DUR___S 16 +#define WMAC0_RXPCU_R0_SRP_DUR_DEBUG__SRP_OP_DUR___M 0x0000FFFF +#define WMAC0_RXPCU_R0_SRP_DUR_DEBUG__SRP_OP_DUR___S 0 +#define WMAC0_RXPCU_R0_SRP_DUR_DEBUG___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRP_DUR_DEBUG___S 0 + +#define WMAC0_RXPCU_R0_SR_DUR_DEBUG (0x00A8C330) +#define WMAC0_RXPCU_R0_SR_DUR_DEBUG___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_SR_DUR_DEBUG___POR 0x00000000 +#define WMAC0_RXPCU_R0_SR_DUR_DEBUG__NON_SRG_DUR___POR 0x0000 +#define WMAC0_RXPCU_R0_SR_DUR_DEBUG__SRG_DUR___POR 0x0000 +#define WMAC0_RXPCU_R0_SR_DUR_DEBUG__NON_SRG_DUR___M 0xFFFF0000 +#define WMAC0_RXPCU_R0_SR_DUR_DEBUG__NON_SRG_DUR___S 16 +#define WMAC0_RXPCU_R0_SR_DUR_DEBUG__SRG_DUR___M 0x0000FFFF +#define WMAC0_RXPCU_R0_SR_DUR_DEBUG__SRG_DUR___S 0 +#define WMAC0_RXPCU_R0_SR_DUR_DEBUG___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SR_DUR_DEBUG___S 0 + +#define WMAC0_RXPCU_R0_NAV_UPD_DEBUG (0x00A8C334) +#define WMAC0_RXPCU_R0_NAV_UPD_DEBUG___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_NAV_UPD_DEBUG___POR 0x00000000 +#define WMAC0_RXPCU_R0_NAV_UPD_DEBUG__IBSS_NAV_CLR_CNT___POR 0x00 +#define WMAC0_RXPCU_R0_NAV_UPD_DEBUG__IBSS_NAV_UPD_CNT___POR 0x00 +#define WMAC0_RXPCU_R0_NAV_UPD_DEBUG__OBSS_NAV_CLR_CNT___POR 0x00 +#define WMAC0_RXPCU_R0_NAV_UPD_DEBUG__OBSS_NAV_UPD_CNT___POR 0x00 +#define WMAC0_RXPCU_R0_NAV_UPD_DEBUG__IBSS_NAV_CLR_CNT___M 0xFF000000 +#define WMAC0_RXPCU_R0_NAV_UPD_DEBUG__IBSS_NAV_CLR_CNT___S 24 +#define WMAC0_RXPCU_R0_NAV_UPD_DEBUG__IBSS_NAV_UPD_CNT___M 0x00FF0000 +#define WMAC0_RXPCU_R0_NAV_UPD_DEBUG__IBSS_NAV_UPD_CNT___S 16 +#define WMAC0_RXPCU_R0_NAV_UPD_DEBUG__OBSS_NAV_CLR_CNT___M 0x0000FF00 +#define WMAC0_RXPCU_R0_NAV_UPD_DEBUG__OBSS_NAV_CLR_CNT___S 8 +#define WMAC0_RXPCU_R0_NAV_UPD_DEBUG__OBSS_NAV_UPD_CNT___M 0x000000FF +#define WMAC0_RXPCU_R0_NAV_UPD_DEBUG__OBSS_NAV_UPD_CNT___S 0 +#define WMAC0_RXPCU_R0_NAV_UPD_DEBUG___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_NAV_UPD_DEBUG___S 0 + +#define WMAC0_RXPCU_R0_SR_ABORT_DEBUG (0x00A8C338) +#define WMAC0_RXPCU_R0_SR_ABORT_DEBUG___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_SR_ABORT_DEBUG___POR 0x00000000 +#define WMAC0_RXPCU_R0_SR_ABORT_DEBUG__NON_SRG_BSSID_ABORT_CNT___POR 0x00 +#define WMAC0_RXPCU_R0_SR_ABORT_DEBUG__NON_SRG_COLOR_ABORT_CNT___POR 0x00 +#define WMAC0_RXPCU_R0_SR_ABORT_DEBUG__SRG_BSSID_ABORT_CNT___POR 0x00 +#define WMAC0_RXPCU_R0_SR_ABORT_DEBUG__SRG_COLOR_ABORT_CNT___POR 0x00 +#define WMAC0_RXPCU_R0_SR_ABORT_DEBUG__NON_SRG_BSSID_ABORT_CNT___M 0xFF000000 +#define WMAC0_RXPCU_R0_SR_ABORT_DEBUG__NON_SRG_BSSID_ABORT_CNT___S 24 +#define WMAC0_RXPCU_R0_SR_ABORT_DEBUG__NON_SRG_COLOR_ABORT_CNT___M 0x00FF0000 +#define WMAC0_RXPCU_R0_SR_ABORT_DEBUG__NON_SRG_COLOR_ABORT_CNT___S 16 +#define WMAC0_RXPCU_R0_SR_ABORT_DEBUG__SRG_BSSID_ABORT_CNT___M 0x0000FF00 +#define WMAC0_RXPCU_R0_SR_ABORT_DEBUG__SRG_BSSID_ABORT_CNT___S 8 +#define WMAC0_RXPCU_R0_SR_ABORT_DEBUG__SRG_COLOR_ABORT_CNT___M 0x000000FF +#define WMAC0_RXPCU_R0_SR_ABORT_DEBUG__SRG_COLOR_ABORT_CNT___S 0 +#define WMAC0_RXPCU_R0_SR_ABORT_DEBUG___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SR_ABORT_DEBUG___S 0 + +#define WMAC0_RXPCU_R0_LATEST_NAV_DEBUG (0x00A8C33C) +#define WMAC0_RXPCU_R0_LATEST_NAV_DEBUG___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_LATEST_NAV_DEBUG___POR 0x00000000 +#define WMAC0_RXPCU_R0_LATEST_NAV_DEBUG__IBSS_NAV_CLEAR___POR 0x0 +#define WMAC0_RXPCU_R0_LATEST_NAV_DEBUG__IBSS_NAV_VALUE___POR 0x0000 +#define WMAC0_RXPCU_R0_LATEST_NAV_DEBUG__OBSS_NAV_CLEAR___POR 0x0 +#define WMAC0_RXPCU_R0_LATEST_NAV_DEBUG__OBSS_NAV_VALUE___POR 0x0000 +#define WMAC0_RXPCU_R0_LATEST_NAV_DEBUG__IBSS_NAV_CLEAR___M 0x80000000 +#define WMAC0_RXPCU_R0_LATEST_NAV_DEBUG__IBSS_NAV_CLEAR___S 31 +#define WMAC0_RXPCU_R0_LATEST_NAV_DEBUG__IBSS_NAV_VALUE___M 0x7FFF0000 +#define WMAC0_RXPCU_R0_LATEST_NAV_DEBUG__IBSS_NAV_VALUE___S 16 +#define WMAC0_RXPCU_R0_LATEST_NAV_DEBUG__OBSS_NAV_CLEAR___M 0x00008000 +#define WMAC0_RXPCU_R0_LATEST_NAV_DEBUG__OBSS_NAV_CLEAR___S 15 +#define WMAC0_RXPCU_R0_LATEST_NAV_DEBUG__OBSS_NAV_VALUE___M 0x00007FFF +#define WMAC0_RXPCU_R0_LATEST_NAV_DEBUG__OBSS_NAV_VALUE___S 0 +#define WMAC0_RXPCU_R0_LATEST_NAV_DEBUG___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_LATEST_NAV_DEBUG___S 0 + +#define WMAC0_RXPCU_R0_LATEST_SR_DEBUG (0x00A8C340) +#define WMAC0_RXPCU_R0_LATEST_SR_DEBUG___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_LATEST_SR_DEBUG___POR 0x00000000 +#define WMAC0_RXPCU_R0_LATEST_SR_DEBUG__LATEST_NON_SRG___POR 0x0 +#define WMAC0_RXPCU_R0_LATEST_SR_DEBUG__LATEST_NON_SRG_DUR___POR 0x0000 +#define WMAC0_RXPCU_R0_LATEST_SR_DEBUG__LATEST_SRG___POR 0x0 +#define WMAC0_RXPCU_R0_LATEST_SR_DEBUG__LATEST_SRG_DUR___POR 0x0000 +#define WMAC0_RXPCU_R0_LATEST_SR_DEBUG__LATEST_NON_SRG___M 0x80000000 +#define WMAC0_RXPCU_R0_LATEST_SR_DEBUG__LATEST_NON_SRG___S 31 +#define WMAC0_RXPCU_R0_LATEST_SR_DEBUG__LATEST_NON_SRG_DUR___M 0x7FFF0000 +#define WMAC0_RXPCU_R0_LATEST_SR_DEBUG__LATEST_NON_SRG_DUR___S 16 +#define WMAC0_RXPCU_R0_LATEST_SR_DEBUG__LATEST_SRG___M 0x00008000 +#define WMAC0_RXPCU_R0_LATEST_SR_DEBUG__LATEST_SRG___S 15 +#define WMAC0_RXPCU_R0_LATEST_SR_DEBUG__LATEST_SRG_DUR___M 0x00007FFF +#define WMAC0_RXPCU_R0_LATEST_SR_DEBUG__LATEST_SRG_DUR___S 0 +#define WMAC0_RXPCU_R0_LATEST_SR_DEBUG___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_LATEST_SR_DEBUG___S 0 + +#define WMAC0_RXPCU_R0_LATEST_SRP_DEBUG (0x00A8C344) +#define WMAC0_RXPCU_R0_LATEST_SRP_DEBUG___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_LATEST_SRP_DEBUG___POR 0x00000000 +#define WMAC0_RXPCU_R0_LATEST_SRP_DEBUG__HE_TB_SRP___POR 0x0 +#define WMAC0_RXPCU_R0_LATEST_SRP_DEBUG__TRIGGER_SRP___POR 0x0 +#define WMAC0_RXPCU_R0_LATEST_SRP_DEBUG__LATEST_SRP_DUR___POR 0x0000 +#define WMAC0_RXPCU_R0_LATEST_SRP_DEBUG__HE_TB_SRP___M 0x00020000 +#define WMAC0_RXPCU_R0_LATEST_SRP_DEBUG__HE_TB_SRP___S 17 +#define WMAC0_RXPCU_R0_LATEST_SRP_DEBUG__TRIGGER_SRP___M 0x00010000 +#define WMAC0_RXPCU_R0_LATEST_SRP_DEBUG__TRIGGER_SRP___S 16 +#define WMAC0_RXPCU_R0_LATEST_SRP_DEBUG__LATEST_SRP_DUR___M 0x0000FFFF +#define WMAC0_RXPCU_R0_LATEST_SRP_DEBUG__LATEST_SRP_DUR___S 0 +#define WMAC0_RXPCU_R0_LATEST_SRP_DEBUG___M 0x0003FFFF +#define WMAC0_RXPCU_R0_LATEST_SRP_DEBUG___S 0 + +#define WMAC0_RXPCU_R0_MPDU_NUM_DEBUG (0x00A8C348) +#define WMAC0_RXPCU_R0_MPDU_NUM_DEBUG___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_MPDU_NUM_DEBUG___POR 0x00000000 +#define WMAC0_RXPCU_R0_MPDU_NUM_DEBUG__FCS_CUR_CNT___POR 0x0000 +#define WMAC0_RXPCU_R0_MPDU_NUM_DEBUG__MPDU_CUR_CNT___POR 0x0000 +#define WMAC0_RXPCU_R0_MPDU_NUM_DEBUG__FCS_CUR_CNT___M 0xFFFF0000 +#define WMAC0_RXPCU_R0_MPDU_NUM_DEBUG__FCS_CUR_CNT___S 16 +#define WMAC0_RXPCU_R0_MPDU_NUM_DEBUG__MPDU_CUR_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R0_MPDU_NUM_DEBUG__MPDU_CUR_CNT___S 0 +#define WMAC0_RXPCU_R0_MPDU_NUM_DEBUG___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_MPDU_NUM_DEBUG___S 0 + +#define WMAC0_RXPCU_R0_NAP_DEBUG (0x00A8C34C) +#define WMAC0_RXPCU_R0_NAP_DEBUG___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_NAP_DEBUG___POR 0x00000000 +#define WMAC0_RXPCU_R0_NAP_DEBUG__LATEST_NAP_DURATION___POR 0x0000 +#define WMAC0_RXPCU_R0_NAP_DEBUG__NAP_CNT___POR 0x0000 +#define WMAC0_RXPCU_R0_NAP_DEBUG__LATEST_NAP_DURATION___M 0xFFFF0000 +#define WMAC0_RXPCU_R0_NAP_DEBUG__LATEST_NAP_DURATION___S 16 +#define WMAC0_RXPCU_R0_NAP_DEBUG__NAP_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R0_NAP_DEBUG__NAP_CNT___S 0 +#define WMAC0_RXPCU_R0_NAP_DEBUG___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_NAP_DEBUG___S 0 + +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA (0x00A8C350) +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA___POR 0x00000000 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA__VALUE___M 0x00003FFF +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA__VALUE___S 0 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA___M 0x00003FFF +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA___S 0 + +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA_BC_MC (0x00A8C354) +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA_BC_MC___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA_BC_MC___POR 0x00000000 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA_BC_MC__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA_BC_MC__VALUE___M 0x00003FFF +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA_BC_MC__VALUE___S 0 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA_BC_MC___M 0x00003FFF +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA_BC_MC___S 0 + +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA_NULL (0x00A8C358) +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA_NULL___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA_NULL___POR 0x00000000 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA_NULL__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA_NULL__VALUE___M 0x00003FFF +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA_NULL__VALUE___S 0 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA_NULL___M 0x00003FFF +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_DATA_NULL___S 0 + +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_CTRL (0x00A8C35C) +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_CTRL___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_CTRL___POR 0x00000000 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_CTRL__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_CTRL__VALUE___M 0x00003FFF +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_CTRL__VALUE___S 0 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_CTRL___M 0x00003FFF +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_CTRL___S 0 + +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_MGMT (0x00A8C360) +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_MGMT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_MGMT___POR 0x00000000 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_MGMT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_MGMT__VALUE___M 0x00003FFF +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_MGMT__VALUE___S 0 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_MGMT___M 0x00003FFF +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_MGMT___S 0 + +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_EXTN (0x00A8C364) +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_EXTN___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_EXTN___POR 0x00000000 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_EXTN__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_EXTN__VALUE___M 0x00003FFF +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_EXTN__VALUE___S 0 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_EXTN___M 0x00003FFF +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_EXTN___S 0 + +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_EXTN_ERR_CNT (0x00A8C368) +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_EXTN_ERR_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_EXTN_ERR_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_EXTN_ERR_CNT__VALUE___POR 0x00 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_EXTN_ERR_CNT__VALUE___M 0x000000FF +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_EXTN_ERR_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_EXTN_ERR_CNT___M 0x000000FF +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_EXTN_ERR_CNT___S 0 + +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_MGMT_ERR_CNT (0x00A8C36C) +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_MGMT_ERR_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_MGMT_ERR_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_MGMT_ERR_CNT__VALUE___POR 0x00 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_MGMT_ERR_CNT__VALUE___M 0x000000FF +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_MGMT_ERR_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_MGMT_ERR_CNT___M 0x000000FF +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_MGMT_ERR_CNT___S 0 + +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_CTRL_ERR_CNT (0x00A8C370) +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_CTRL_ERR_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_CTRL_ERR_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_CTRL_ERR_CNT__VALUE___POR 0x00 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_CTRL_ERR_CNT__VALUE___M 0x0000FF00 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_CTRL_ERR_CNT__VALUE___S 8 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_CTRL_ERR_CNT___M 0x0000FF00 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_CTRL_ERR_CNT___S 8 + +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_ERR_CNT (0x00A8C374) +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_ERR_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_ERR_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_ERR_CNT__VALUE___POR 0x00 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_ERR_CNT__VALUE___M 0x000000FF +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_ERR_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_ERR_CNT___M 0x000000FF +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_ERR_CNT___S 0 + +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_BC_MC_ERR_CNT (0x00A8C378) +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_BC_MC_ERR_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_BC_MC_ERR_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_BC_MC_ERR_CNT__VALUE___POR 0x00 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_BC_MC_ERR_CNT__VALUE___M 0x000000FF +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_BC_MC_ERR_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_BC_MC_ERR_CNT___M 0x000000FF +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_BC_MC_ERR_CNT___S 0 + +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_NULL_ERR_CNT (0x00A8C37C) +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_NULL_ERR_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_NULL_ERR_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_NULL_ERR_CNT__VALUE___POR 0x00 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_NULL_ERR_CNT__VALUE___M 0x000000FF +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_NULL_ERR_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_NULL_ERR_CNT___M 0x000000FF +#define WMAC0_RXPCU_R0_MAX_RX_LENGTH_ERR_DATA_NULL_ERR_CNT___S 0 + +#define WMAC0_RXPCU_R0_CLKGATE_CTRL (0x00A8C380) +#define WMAC0_RXPCU_R0_CLKGATE_CTRL___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CLKGATE_CTRL___POR 0x00000000 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLK_EN_EXTEND___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CPU_IF_EXTEND___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PHU_MSG___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BPU___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_HE_TFD___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_FEPU_MISC___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BEPU_MISC___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_CSM_MEMBANK___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BRU_MEMBANK___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BABU_MEMBANK___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_SPF_MEMBANK___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_SCF_MEMBANK___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_USM_MEMBANK___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PIMA___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PIM_MEMBANK___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PIM_MEM2P___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_DEBUG___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_RFC___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_SPF___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_SCF___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_CIA___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_TSU___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PFU___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_UDU_TOP___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BABU___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BRU___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PCU___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_RTI___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_TRI___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_MPI___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PMI___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_GSE___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLK_EN_EXTEND___M 0x80000000 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLK_EN_EXTEND___S 31 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CPU_IF_EXTEND___M 0x40000000 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CPU_IF_EXTEND___S 30 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PHU_MSG___M 0x20000000 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PHU_MSG___S 29 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BPU___M 0x10000000 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BPU___S 28 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_HE_TFD___M 0x08000000 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_HE_TFD___S 27 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_FEPU_MISC___M 0x04000000 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_FEPU_MISC___S 26 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BEPU_MISC___M 0x02000000 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BEPU_MISC___S 25 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_CSM_MEMBANK___M 0x01000000 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_CSM_MEMBANK___S 24 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BRU_MEMBANK___M 0x00800000 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BRU_MEMBANK___S 23 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BABU_MEMBANK___M 0x00400000 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BABU_MEMBANK___S 22 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_SPF_MEMBANK___M 0x00200000 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_SPF_MEMBANK___S 21 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_SCF_MEMBANK___M 0x00100000 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_SCF_MEMBANK___S 20 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_USM_MEMBANK___M 0x00080000 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_USM_MEMBANK___S 19 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PIMA___M 0x00040000 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PIMA___S 18 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PIM_MEMBANK___M 0x00020000 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PIM_MEMBANK___S 17 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PIM_MEM2P___M 0x00010000 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PIM_MEM2P___S 16 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_DEBUG___M 0x00008000 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_DEBUG___S 15 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_RFC___M 0x00004000 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_RFC___S 14 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_SPF___M 0x00002000 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_SPF___S 13 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_SCF___M 0x00001000 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_SCF___S 12 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_CIA___M 0x00000800 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_CIA___S 11 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_TSU___M 0x00000400 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_TSU___S 10 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PFU___M 0x00000200 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PFU___S 9 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_UDU_TOP___M 0x00000100 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_UDU_TOP___S 8 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BABU___M 0x00000080 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BABU___S 7 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BRU___M 0x00000040 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_BRU___S 6 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PCU___M 0x00000020 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PCU___S 5 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_RTI___M 0x00000010 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_RTI___S 4 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_TRI___M 0x00000008 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_TRI___S 3 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_MPI___M 0x00000004 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_MPI___S 2 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PMI___M 0x00000002 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_PMI___S 1 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_GSE___M 0x00000001 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL__CLKGAT_DISABLE_GSE___S 0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CLKGATE_CTRL___S 0 + +#define WMAC0_RXPCU_R0_PHY_ERROR_PROMISCUOUS_MASK (0x00A8C384) +#define WMAC0_RXPCU_R0_PHY_ERROR_PROMISCUOUS_MASK___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_PHY_ERROR_PROMISCUOUS_MASK___POR 0x00000000 +#define WMAC0_RXPCU_R0_PHY_ERROR_PROMISCUOUS_MASK__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_PHY_ERROR_PROMISCUOUS_MASK__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PHY_ERROR_PROMISCUOUS_MASK__VALUE___S 0 +#define WMAC0_RXPCU_R0_PHY_ERROR_PROMISCUOUS_MASK___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PHY_ERROR_PROMISCUOUS_MASK___S 0 + +#define WMAC0_RXPCU_R0_PHY_ERROR_PROMISCUOUS_MASK_CONT (0x00A8C388) +#define WMAC0_RXPCU_R0_PHY_ERROR_PROMISCUOUS_MASK_CONT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_PHY_ERROR_PROMISCUOUS_MASK_CONT___POR 0x00000000 +#define WMAC0_RXPCU_R0_PHY_ERROR_PROMISCUOUS_MASK_CONT__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_PHY_ERROR_PROMISCUOUS_MASK_CONT__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PHY_ERROR_PROMISCUOUS_MASK_CONT__VALUE___S 0 +#define WMAC0_RXPCU_R0_PHY_ERROR_PROMISCUOUS_MASK_CONT___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PHY_ERROR_PROMISCUOUS_MASK_CONT___S 0 + +#define WMAC0_RXPCU_R0_COEX_CTRL (0x00A8C38C) +#define WMAC0_RXPCU_R0_COEX_CTRL___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_COEX_CTRL___POR 0x00000001 +#define WMAC0_RXPCU_R0_COEX_CTRL__COEX_RX_STATUS_NOFILTERIN___POR 0x0 +#define WMAC0_RXPCU_R0_COEX_CTRL__SEND_COEX_RX_STATUS___POR 0x0 +#define WMAC0_RXPCU_R0_COEX_CTRL__DISABLE___POR 0x1 +#define WMAC0_RXPCU_R0_COEX_CTRL__COEX_RX_STATUS_NOFILTERIN___M 0x00000004 +#define WMAC0_RXPCU_R0_COEX_CTRL__COEX_RX_STATUS_NOFILTERIN___S 2 +#define WMAC0_RXPCU_R0_COEX_CTRL__SEND_COEX_RX_STATUS___M 0x00000002 +#define WMAC0_RXPCU_R0_COEX_CTRL__SEND_COEX_RX_STATUS___S 1 +#define WMAC0_RXPCU_R0_COEX_CTRL__DISABLE___M 0x00000001 +#define WMAC0_RXPCU_R0_COEX_CTRL__DISABLE___S 0 +#define WMAC0_RXPCU_R0_COEX_CTRL___M 0x00000007 +#define WMAC0_RXPCU_R0_COEX_CTRL___S 0 + +#define WMAC0_RXPCU_R0_EIFS_CTRL (0x00A8C390) +#define WMAC0_RXPCU_R0_EIFS_CTRL___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_EIFS_CTRL___POR 0x00000000 +#define WMAC0_RXPCU_R0_EIFS_CTRL__RATE_MCS___POR 0x0 +#define WMAC0_RXPCU_R0_EIFS_CTRL__PKT_TYPE___POR 0x0 +#define WMAC0_RXPCU_R0_EIFS_CTRL__RATE_MCS___M 0x000000F0 +#define WMAC0_RXPCU_R0_EIFS_CTRL__RATE_MCS___S 4 +#define WMAC0_RXPCU_R0_EIFS_CTRL__PKT_TYPE___M 0x0000000F +#define WMAC0_RXPCU_R0_EIFS_CTRL__PKT_TYPE___S 0 +#define WMAC0_RXPCU_R0_EIFS_CTRL___M 0x000000FF +#define WMAC0_RXPCU_R0_EIFS_CTRL___S 0 + +#define WMAC0_RXPCU_R0_CBF_CTRL (0x00A8C394) +#define WMAC0_RXPCU_R0_CBF_CTRL___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_CBF_CTRL___POR 0x00000000 +#define WMAC0_RXPCU_R0_CBF_CTRL__CBF1_STA___POR 0x0 +#define WMAC0_RXPCU_R0_CBF_CTRL__CBF1_BSSID_IDX___POR 0x0 +#define WMAC0_RXPCU_R0_CBF_CTRL__CBF1_VALID___POR 0x0 +#define WMAC0_RXPCU_R0_CBF_CTRL__CBF0_STA___POR 0x0 +#define WMAC0_RXPCU_R0_CBF_CTRL__CBF0_BSSID_IDX___POR 0x0 +#define WMAC0_RXPCU_R0_CBF_CTRL__CBF0_VALID___POR 0x0 +#define WMAC0_RXPCU_R0_CBF_CTRL__LATEST_IDX___POR 0x0 +#define WMAC0_RXPCU_R0_CBF_CTRL__CBF1_STA___M 0x00000400 +#define WMAC0_RXPCU_R0_CBF_CTRL__CBF1_STA___S 10 +#define WMAC0_RXPCU_R0_CBF_CTRL__CBF1_BSSID_IDX___M 0x00000380 +#define WMAC0_RXPCU_R0_CBF_CTRL__CBF1_BSSID_IDX___S 7 +#define WMAC0_RXPCU_R0_CBF_CTRL__CBF1_VALID___M 0x00000040 +#define WMAC0_RXPCU_R0_CBF_CTRL__CBF1_VALID___S 6 +#define WMAC0_RXPCU_R0_CBF_CTRL__CBF0_STA___M 0x00000020 +#define WMAC0_RXPCU_R0_CBF_CTRL__CBF0_STA___S 5 +#define WMAC0_RXPCU_R0_CBF_CTRL__CBF0_BSSID_IDX___M 0x0000001C +#define WMAC0_RXPCU_R0_CBF_CTRL__CBF0_BSSID_IDX___S 2 +#define WMAC0_RXPCU_R0_CBF_CTRL__CBF0_VALID___M 0x00000002 +#define WMAC0_RXPCU_R0_CBF_CTRL__CBF0_VALID___S 1 +#define WMAC0_RXPCU_R0_CBF_CTRL__LATEST_IDX___M 0x00000001 +#define WMAC0_RXPCU_R0_CBF_CTRL__LATEST_IDX___S 0 +#define WMAC0_RXPCU_R0_CBF_CTRL___M 0x000007FF +#define WMAC0_RXPCU_R0_CBF_CTRL___S 0 + +#define WMAC0_RXPCU_R0_SOCIAL_WIFI_CTRL (0x00A8C398) +#define WMAC0_RXPCU_R0_SOCIAL_WIFI_CTRL___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SOCIAL_WIFI_CTRL___POR 0x00000000 +#define WMAC0_RXPCU_R0_SOCIAL_WIFI_CTRL__DIS_PAUSE_NAN_BEACON___POR 0x0 +#define WMAC0_RXPCU_R0_SOCIAL_WIFI_CTRL__DIS_PAUSE_NAN_BEACON___M 0x00000001 +#define WMAC0_RXPCU_R0_SOCIAL_WIFI_CTRL__DIS_PAUSE_NAN_BEACON___S 0 +#define WMAC0_RXPCU_R0_SOCIAL_WIFI_CTRL___M 0x00000001 +#define WMAC0_RXPCU_R0_SOCIAL_WIFI_CTRL___S 0 + +#define WMAC0_RXPCU_R0_SOCIAL_WIFI_BSSID_L32 (0x00A8C39C) +#define WMAC0_RXPCU_R0_SOCIAL_WIFI_BSSID_L32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SOCIAL_WIFI_BSSID_L32___POR 0x00000000 +#define WMAC0_RXPCU_R0_SOCIAL_WIFI_BSSID_L32__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_SOCIAL_WIFI_BSSID_L32__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SOCIAL_WIFI_BSSID_L32__VALUE___S 0 +#define WMAC0_RXPCU_R0_SOCIAL_WIFI_BSSID_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SOCIAL_WIFI_BSSID_L32___S 0 + +#define WMAC0_RXPCU_R0_SOCIAL_WIFI_BSSID_U16 (0x00A8C3A0) +#define WMAC0_RXPCU_R0_SOCIAL_WIFI_BSSID_U16___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SOCIAL_WIFI_BSSID_U16___POR 0x00000000 +#define WMAC0_RXPCU_R0_SOCIAL_WIFI_BSSID_U16__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R0_SOCIAL_WIFI_BSSID_U16__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R0_SOCIAL_WIFI_BSSID_U16__VALUE___S 0 +#define WMAC0_RXPCU_R0_SOCIAL_WIFI_BSSID_U16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_SOCIAL_WIFI_BSSID_U16___S 0 + +#define WMAC0_RXPCU_R0_GP_CTRL (0x00A8C3A4) +#define WMAC0_RXPCU_R0_GP_CTRL___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GP_CTRL___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_CTRL__ENTRY_VALID___POR 0x0000 +#define WMAC0_RXPCU_R0_GP_CTRL__BSSID_SEL___POR 0x0 +#define WMAC0_RXPCU_R0_GP_CTRL__BCAST_ACK_ENABLE___POR 0x0 +#define WMAC0_RXPCU_R0_GP_CTRL__BSSID_CHECK_DISABLE___POR 0x0 +#define WMAC0_RXPCU_R0_GP_CTRL__MGMT_ACK_ENABLE___POR 0x0 +#define WMAC0_RXPCU_R0_GP_CTRL__ACK_POLICY_IGNORE___POR 0x0 +#define WMAC0_RXPCU_R0_GP_CTRL__A1A2_MATCH_ENABLE___POR 0x0 +#define WMAC0_RXPCU_R0_GP_CTRL__GROUP_PLAY_ENABLE___POR 0x0 +#define WMAC0_RXPCU_R0_GP_CTRL__ENTRY_VALID___M 0x00FFFF00 +#define WMAC0_RXPCU_R0_GP_CTRL__ENTRY_VALID___S 8 +#define WMAC0_RXPCU_R0_GP_CTRL__BSSID_SEL___M 0x00000040 +#define WMAC0_RXPCU_R0_GP_CTRL__BSSID_SEL___S 6 +#define WMAC0_RXPCU_R0_GP_CTRL__BCAST_ACK_ENABLE___M 0x00000020 +#define WMAC0_RXPCU_R0_GP_CTRL__BCAST_ACK_ENABLE___S 5 +#define WMAC0_RXPCU_R0_GP_CTRL__BSSID_CHECK_DISABLE___M 0x00000010 +#define WMAC0_RXPCU_R0_GP_CTRL__BSSID_CHECK_DISABLE___S 4 +#define WMAC0_RXPCU_R0_GP_CTRL__MGMT_ACK_ENABLE___M 0x00000008 +#define WMAC0_RXPCU_R0_GP_CTRL__MGMT_ACK_ENABLE___S 3 +#define WMAC0_RXPCU_R0_GP_CTRL__ACK_POLICY_IGNORE___M 0x00000004 +#define WMAC0_RXPCU_R0_GP_CTRL__ACK_POLICY_IGNORE___S 2 +#define WMAC0_RXPCU_R0_GP_CTRL__A1A2_MATCH_ENABLE___M 0x00000002 +#define WMAC0_RXPCU_R0_GP_CTRL__A1A2_MATCH_ENABLE___S 1 +#define WMAC0_RXPCU_R0_GP_CTRL__GROUP_PLAY_ENABLE___M 0x00000001 +#define WMAC0_RXPCU_R0_GP_CTRL__GROUP_PLAY_ENABLE___S 0 +#define WMAC0_RXPCU_R0_GP_CTRL___M 0x00FFFF7F +#define WMAC0_RXPCU_R0_GP_CTRL___S 0 + +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_0_L32 (0x00A8C3A8) +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_0_L32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_0_L32___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_0_L32__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_0_L32__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_0_L32__VALUE___S 0 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_0_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_0_L32___S 0 + +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_0_U16 (0x00A8C3AC) +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_0_U16___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_0_U16___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_0_U16__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_0_U16__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_0_U16__VALUE___S 0 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_0_U16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_0_U16___S 0 + +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_1_L32 (0x00A8C3B0) +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_1_L32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_1_L32___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_1_L32__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_1_L32__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_1_L32__VALUE___S 0 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_1_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_1_L32___S 0 + +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_1_U16 (0x00A8C3B4) +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_1_U16___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_1_U16___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_1_U16__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_1_U16__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_1_U16__VALUE___S 0 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_1_U16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_1_U16___S 0 + +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_2_L32 (0x00A8C3B8) +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_2_L32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_2_L32___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_2_L32__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_2_L32__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_2_L32__VALUE___S 0 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_2_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_2_L32___S 0 + +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_2_U16 (0x00A8C3BC) +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_2_U16___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_2_U16___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_2_U16__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_2_U16__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_2_U16__VALUE___S 0 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_2_U16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_2_U16___S 0 + +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_3_L32 (0x00A8C3C0) +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_3_L32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_3_L32___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_3_L32__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_3_L32__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_3_L32__VALUE___S 0 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_3_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_3_L32___S 0 + +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_3_U16 (0x00A8C3C4) +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_3_U16___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_3_U16___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_3_U16__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_3_U16__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_3_U16__VALUE___S 0 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_3_U16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_3_U16___S 0 + +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_4_L32 (0x00A8C3C8) +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_4_L32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_4_L32___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_4_L32__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_4_L32__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_4_L32__VALUE___S 0 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_4_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_4_L32___S 0 + +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_4_U16 (0x00A8C3CC) +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_4_U16___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_4_U16___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_4_U16__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_4_U16__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_4_U16__VALUE___S 0 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_4_U16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_4_U16___S 0 + +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_5_L32 (0x00A8C3D0) +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_5_L32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_5_L32___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_5_L32__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_5_L32__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_5_L32__VALUE___S 0 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_5_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_5_L32___S 0 + +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_5_U16 (0x00A8C3D4) +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_5_U16___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_5_U16___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_5_U16__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_5_U16__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_5_U16__VALUE___S 0 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_5_U16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_5_U16___S 0 + +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_6_L32 (0x00A8C3D8) +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_6_L32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_6_L32___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_6_L32__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_6_L32__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_6_L32__VALUE___S 0 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_6_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_6_L32___S 0 + +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_6_U16 (0x00A8C3DC) +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_6_U16___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_6_U16___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_6_U16__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_6_U16__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_6_U16__VALUE___S 0 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_6_U16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_6_U16___S 0 + +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_7_L32 (0x00A8C3E0) +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_7_L32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_7_L32___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_7_L32__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_7_L32__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_7_L32__VALUE___S 0 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_7_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_7_L32___S 0 + +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_7_U16 (0x00A8C3E4) +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_7_U16___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_7_U16___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_7_U16__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_7_U16__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_7_U16__VALUE___S 0 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_7_U16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_7_U16___S 0 + +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_8_L32 (0x00A8C3E8) +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_8_L32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_8_L32___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_8_L32__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_8_L32__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_8_L32__VALUE___S 0 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_8_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_8_L32___S 0 + +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_8_U16 (0x00A8C3EC) +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_8_U16___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_8_U16___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_8_U16__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_8_U16__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_8_U16__VALUE___S 0 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_8_U16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_8_U16___S 0 + +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_9_L32 (0x00A8C3F0) +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_9_L32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_9_L32___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_9_L32__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_9_L32__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_9_L32__VALUE___S 0 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_9_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_9_L32___S 0 + +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_9_U16 (0x00A8C3F4) +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_9_U16___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_9_U16___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_9_U16__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_9_U16__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_9_U16__VALUE___S 0 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_9_U16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_9_U16___S 0 + +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_10_L32 (0x00A8C3F8) +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_10_L32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_10_L32___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_10_L32__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_10_L32__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_10_L32__VALUE___S 0 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_10_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_10_L32___S 0 + +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_10_U16 (0x00A8C3FC) +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_10_U16___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_10_U16___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_10_U16__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_10_U16__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_10_U16__VALUE___S 0 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_10_U16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_10_U16___S 0 + +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_11_L32 (0x00A8C400) +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_11_L32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_11_L32___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_11_L32__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_11_L32__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_11_L32__VALUE___S 0 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_11_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_11_L32___S 0 + +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_11_U16 (0x00A8C404) +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_11_U16___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_11_U16___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_11_U16__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_11_U16__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_11_U16__VALUE___S 0 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_11_U16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_11_U16___S 0 + +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_12_L32 (0x00A8C408) +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_12_L32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_12_L32___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_12_L32__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_12_L32__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_12_L32__VALUE___S 0 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_12_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_12_L32___S 0 + +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_12_U16 (0x00A8C40C) +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_12_U16___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_12_U16___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_12_U16__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_12_U16__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_12_U16__VALUE___S 0 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_12_U16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_12_U16___S 0 + +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_13_L32 (0x00A8C410) +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_13_L32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_13_L32___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_13_L32__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_13_L32__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_13_L32__VALUE___S 0 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_13_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_13_L32___S 0 + +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_13_U16 (0x00A8C414) +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_13_U16___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_13_U16___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_13_U16__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_13_U16__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_13_U16__VALUE___S 0 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_13_U16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_13_U16___S 0 + +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_14_L32 (0x00A8C418) +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_14_L32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_14_L32___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_14_L32__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_14_L32__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_14_L32__VALUE___S 0 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_14_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_14_L32___S 0 + +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_14_U16 (0x00A8C41C) +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_14_U16___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_14_U16___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_14_U16__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_14_U16__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_14_U16__VALUE___S 0 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_14_U16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_14_U16___S 0 + +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_15_L32 (0x00A8C420) +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_15_L32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_15_L32___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_15_L32__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_15_L32__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_15_L32__VALUE___S 0 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_15_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_15_L32___S 0 + +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_15_U16 (0x00A8C424) +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_15_U16___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_15_U16___POR 0x00000000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_15_U16__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_15_U16__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_15_U16__VALUE___S 0 +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_15_U16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_GP_ADDR_CACHE_15_U16___S 0 + +#define WMAC0_RXPCU_R0_PFU_CTRL (0x00A8C428) +#define WMAC0_RXPCU_R0_PFU_CTRL___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_PFU_CTRL___POR 0x01000210 +#define WMAC0_RXPCU_R0_PFU_CTRL__DWSIZE_OF_ALLOCATED_SFM_CLIENT1___POR 0x0100 +#define WMAC0_RXPCU_R0_PFU_CTRL__DISABLE_KEY_ID_COMPARE___POR 0x0 +#define WMAC0_RXPCU_R0_PFU_CTRL__GXI_SECURITY_ID___POR 0x0 +#define WMAC0_RXPCU_R0_PFU_CTRL__GXI_BYTE_SWAP___POR 0x0 +#define WMAC0_RXPCU_R0_PFU_CTRL__GXI_HIGH_PRIORITY___POR 0x0 +#define WMAC0_RXPCU_R0_PFU_CTRL__MARGIN___POR 0x1 +#define WMAC0_RXPCU_R0_PFU_CTRL__FLOW_CTRL_EN___POR 0x0 +#define WMAC0_RXPCU_R0_PFU_CTRL__MAX_OUTSTANDING_REQ___POR 0x10 +#define WMAC0_RXPCU_R0_PFU_CTRL__DWSIZE_OF_ALLOCATED_SFM_CLIENT1___M 0xFFFF0000 +#define WMAC0_RXPCU_R0_PFU_CTRL__DWSIZE_OF_ALLOCATED_SFM_CLIENT1___S 16 +#define WMAC0_RXPCU_R0_PFU_CTRL__DISABLE_KEY_ID_COMPARE___M 0x00008000 +#define WMAC0_RXPCU_R0_PFU_CTRL__DISABLE_KEY_ID_COMPARE___S 15 +#define WMAC0_RXPCU_R0_PFU_CTRL__GXI_SECURITY_ID___M 0x00006000 +#define WMAC0_RXPCU_R0_PFU_CTRL__GXI_SECURITY_ID___S 13 +#define WMAC0_RXPCU_R0_PFU_CTRL__GXI_BYTE_SWAP___M 0x00001000 +#define WMAC0_RXPCU_R0_PFU_CTRL__GXI_BYTE_SWAP___S 12 +#define WMAC0_RXPCU_R0_PFU_CTRL__GXI_HIGH_PRIORITY___M 0x00000800 +#define WMAC0_RXPCU_R0_PFU_CTRL__GXI_HIGH_PRIORITY___S 11 +#define WMAC0_RXPCU_R0_PFU_CTRL__MARGIN___M 0x00000600 +#define WMAC0_RXPCU_R0_PFU_CTRL__MARGIN___S 9 +#define WMAC0_RXPCU_R0_PFU_CTRL__FLOW_CTRL_EN___M 0x00000100 +#define WMAC0_RXPCU_R0_PFU_CTRL__FLOW_CTRL_EN___S 8 +#define WMAC0_RXPCU_R0_PFU_CTRL__MAX_OUTSTANDING_REQ___M 0x000000FF +#define WMAC0_RXPCU_R0_PFU_CTRL__MAX_OUTSTANDING_REQ___S 0 +#define WMAC0_RXPCU_R0_PFU_CTRL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PFU_CTRL___S 0 + +#define WMAC0_RXPCU_R0_RX_THRESHOLD (0x00A8C42C) +#define WMAC0_RXPCU_R0_RX_THRESHOLD___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RX_THRESHOLD___POR 0x00000000 +#define WMAC0_RXPCU_R0_RX_THRESHOLD__MPDU_THRESHOLD_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_THRESHOLD__MPDU_THRESHOLD___POR 0x00 +#define WMAC0_RXPCU_R0_RX_THRESHOLD__PPDU_THRESHOLD_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_THRESHOLD__PPDU_THRESHOLD___POR 0x00 +#define WMAC0_RXPCU_R0_RX_THRESHOLD__MPDU_THRESHOLD_EN___M 0x01000000 +#define WMAC0_RXPCU_R0_RX_THRESHOLD__MPDU_THRESHOLD_EN___S 24 +#define WMAC0_RXPCU_R0_RX_THRESHOLD__MPDU_THRESHOLD___M 0x00FF0000 +#define WMAC0_RXPCU_R0_RX_THRESHOLD__MPDU_THRESHOLD___S 16 +#define WMAC0_RXPCU_R0_RX_THRESHOLD__PPDU_THRESHOLD_EN___M 0x00000100 +#define WMAC0_RXPCU_R0_RX_THRESHOLD__PPDU_THRESHOLD_EN___S 8 +#define WMAC0_RXPCU_R0_RX_THRESHOLD__PPDU_THRESHOLD___M 0x000000FF +#define WMAC0_RXPCU_R0_RX_THRESHOLD__PPDU_THRESHOLD___S 0 +#define WMAC0_RXPCU_R0_RX_THRESHOLD___M 0x01FF01FF +#define WMAC0_RXPCU_R0_RX_THRESHOLD___S 0 + +#define WMAC0_RXPCU_R0_RAM_CPUIF_CTRL (0x00A8C430) +#define WMAC0_RXPCU_R0_RAM_CPUIF_CTRL___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RAM_CPUIF_CTRL___POR 0x00000000 +#define WMAC0_RXPCU_R0_RAM_CPUIF_CTRL__MEM_ADDR___POR 0x000 +#define WMAC0_RXPCU_R0_RAM_CPUIF_CTRL__MEM_SEL___POR 0x0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_CTRL__CPU_ACCESS_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_CTRL__MEM_ADDR___M 0x0000FFF0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_CTRL__MEM_ADDR___S 4 +#define WMAC0_RXPCU_R0_RAM_CPUIF_CTRL__MEM_SEL___M 0x0000000E +#define WMAC0_RXPCU_R0_RAM_CPUIF_CTRL__MEM_SEL___S 1 +#define WMAC0_RXPCU_R0_RAM_CPUIF_CTRL__CPU_ACCESS_EN___M 0x00000001 +#define WMAC0_RXPCU_R0_RAM_CPUIF_CTRL__CPU_ACCESS_EN___S 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_CTRL___M 0x0000FFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_CTRL___S 0 + +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_n(n) (0x00A8C434+0x4*(n)) +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_n_nMIN 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_n_nMAX 31 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_n_ELEM 32 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_n___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_n___POR 0x00000000 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_n__MEM_RDDATA___POR 0x00000000 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_n__MEM_RDDATA___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_n__MEM_RDDATA___S 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_n___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_n___S 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_0 (0x00A8C434) +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_0___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_0__MEM_RDDATA___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_0__MEM_RDDATA___S 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_1 (0x00A8C438) +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_1___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_1__MEM_RDDATA___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_1__MEM_RDDATA___S 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_2 (0x00A8C43C) +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_2___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_2__MEM_RDDATA___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_2__MEM_RDDATA___S 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_3 (0x00A8C440) +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_3___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_3__MEM_RDDATA___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_3__MEM_RDDATA___S 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_4 (0x00A8C444) +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_4___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_4__MEM_RDDATA___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_4__MEM_RDDATA___S 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_5 (0x00A8C448) +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_5___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_5__MEM_RDDATA___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_5__MEM_RDDATA___S 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_6 (0x00A8C44C) +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_6___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_6__MEM_RDDATA___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_6__MEM_RDDATA___S 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_7 (0x00A8C450) +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_7___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_7__MEM_RDDATA___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_7__MEM_RDDATA___S 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_8 (0x00A8C454) +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_8___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_8__MEM_RDDATA___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_8__MEM_RDDATA___S 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_9 (0x00A8C458) +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_9___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_9__MEM_RDDATA___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_9__MEM_RDDATA___S 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_10 (0x00A8C45C) +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_10___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_10__MEM_RDDATA___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_10__MEM_RDDATA___S 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_11 (0x00A8C460) +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_11___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_11__MEM_RDDATA___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_11__MEM_RDDATA___S 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_12 (0x00A8C464) +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_12___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_12__MEM_RDDATA___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_12__MEM_RDDATA___S 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_13 (0x00A8C468) +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_13___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_13__MEM_RDDATA___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_13__MEM_RDDATA___S 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_14 (0x00A8C46C) +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_14___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_14__MEM_RDDATA___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_14__MEM_RDDATA___S 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_15 (0x00A8C470) +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_15___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_15__MEM_RDDATA___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_15__MEM_RDDATA___S 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_16 (0x00A8C474) +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_16___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_16__MEM_RDDATA___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_16__MEM_RDDATA___S 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_17 (0x00A8C478) +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_17___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_17__MEM_RDDATA___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_17__MEM_RDDATA___S 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_18 (0x00A8C47C) +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_18___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_18__MEM_RDDATA___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_18__MEM_RDDATA___S 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_19 (0x00A8C480) +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_19___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_19__MEM_RDDATA___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_19__MEM_RDDATA___S 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_20 (0x00A8C484) +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_20___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_20__MEM_RDDATA___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_20__MEM_RDDATA___S 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_21 (0x00A8C488) +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_21___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_21__MEM_RDDATA___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_21__MEM_RDDATA___S 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_22 (0x00A8C48C) +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_22___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_22__MEM_RDDATA___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_22__MEM_RDDATA___S 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_23 (0x00A8C490) +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_23___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_23__MEM_RDDATA___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_23__MEM_RDDATA___S 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_24 (0x00A8C494) +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_24___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_24__MEM_RDDATA___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_24__MEM_RDDATA___S 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_25 (0x00A8C498) +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_25___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_25__MEM_RDDATA___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_25__MEM_RDDATA___S 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_26 (0x00A8C49C) +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_26___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_26__MEM_RDDATA___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_26__MEM_RDDATA___S 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_27 (0x00A8C4A0) +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_27___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_27__MEM_RDDATA___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_27__MEM_RDDATA___S 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_28 (0x00A8C4A4) +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_28___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_28__MEM_RDDATA___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_28__MEM_RDDATA___S 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_29 (0x00A8C4A8) +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_29___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_29__MEM_RDDATA___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_29__MEM_RDDATA___S 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_30 (0x00A8C4AC) +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_30___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_30__MEM_RDDATA___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_30__MEM_RDDATA___S 0 +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_31 (0x00A8C4B0) +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_31___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_31__MEM_RDDATA___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RAM_CPUIF_RD_DATA_31__MEM_RDDATA___S 0 + +#define WMAC0_RXPCU_R0_RX_FLUSH_CTRL (0x00A8C4B4) +#define WMAC0_RXPCU_R0_RX_FLUSH_CTRL___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RX_FLUSH_CTRL___POR 0x00000000 +#define WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FLUSH_CNT___POR 0x0 +#define WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FLUSH_BACK_GXI___POR 0x0 +#define WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FLUSH_BACK_SFM1___POR 0x0 +#define WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FLUSH_BACK_GSE___POR 0x0 +#define WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FLUSH_BACK_SFM0___POR 0x0 +#define WMAC0_RXPCU_R0_RX_FLUSH_CTRL__EBT_TRIGGER_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FW_TRIGGER_RX_FLUSH_ACK___POR 0x0 +#define WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FW_TRIGGER_RX_FLUSH_REQ___POR 0x0 +#define WMAC0_RXPCU_R0_RX_FLUSH_CTRL__RX_FLUSH_MIN_DURATION___POR 0x0000 +#define WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FLUSH_CNT___M 0x0F000000 +#define WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FLUSH_CNT___S 24 +#define WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FLUSH_BACK_GXI___M 0x00400000 +#define WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FLUSH_BACK_GXI___S 22 +#define WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FLUSH_BACK_SFM1___M 0x00200000 +#define WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FLUSH_BACK_SFM1___S 21 +#define WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FLUSH_BACK_GSE___M 0x00100000 +#define WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FLUSH_BACK_GSE___S 20 +#define WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FLUSH_BACK_SFM0___M 0x00080000 +#define WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FLUSH_BACK_SFM0___S 19 +#define WMAC0_RXPCU_R0_RX_FLUSH_CTRL__EBT_TRIGGER_EN___M 0x00040000 +#define WMAC0_RXPCU_R0_RX_FLUSH_CTRL__EBT_TRIGGER_EN___S 18 +#define WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FW_TRIGGER_RX_FLUSH_ACK___M 0x00020000 +#define WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FW_TRIGGER_RX_FLUSH_ACK___S 17 +#define WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FW_TRIGGER_RX_FLUSH_REQ___M 0x00010000 +#define WMAC0_RXPCU_R0_RX_FLUSH_CTRL__FW_TRIGGER_RX_FLUSH_REQ___S 16 +#define WMAC0_RXPCU_R0_RX_FLUSH_CTRL__RX_FLUSH_MIN_DURATION___M 0x0000FFFF +#define WMAC0_RXPCU_R0_RX_FLUSH_CTRL__RX_FLUSH_MIN_DURATION___S 0 +#define WMAC0_RXPCU_R0_RX_FLUSH_CTRL___M 0x0F7FFFFF +#define WMAC0_RXPCU_R0_RX_FLUSH_CTRL___S 0 + +#define WMAC0_RXPCU_R0_RX_INT_CTRL (0x00A8C4B8) +#define WMAC0_RXPCU_R0_RX_INT_CTRL___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RX_INT_CTRL___POR 0x00000000 +#define WMAC0_RXPCU_R0_RX_INT_CTRL__RX_END_INT_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_INT_CTRL__RX_START_INT_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_INT_CTRL__USER_INDEX___POR 0x00 +#define WMAC0_RXPCU_R0_RX_INT_CTRL__RX_END_INT_EN___M 0x00000080 +#define WMAC0_RXPCU_R0_RX_INT_CTRL__RX_END_INT_EN___S 7 +#define WMAC0_RXPCU_R0_RX_INT_CTRL__RX_START_INT_EN___M 0x00000040 +#define WMAC0_RXPCU_R0_RX_INT_CTRL__RX_START_INT_EN___S 6 +#define WMAC0_RXPCU_R0_RX_INT_CTRL__USER_INDEX___M 0x0000003F +#define WMAC0_RXPCU_R0_RX_INT_CTRL__USER_INDEX___S 0 +#define WMAC0_RXPCU_R0_RX_INT_CTRL___M 0x000000FF +#define WMAC0_RXPCU_R0_RX_INT_CTRL___S 0 + +#define WMAC0_RXPCU_R0_PPDU_ID (0x00A8C4BC) +#define WMAC0_RXPCU_R0_PPDU_ID___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_PPDU_ID___POR 0x00000000 +#define WMAC0_RXPCU_R0_PPDU_ID__BE_IDLE___POR 0x0 +#define WMAC0_RXPCU_R0_PPDU_ID__FE_IDLE___POR 0x0 +#define WMAC0_RXPCU_R0_PPDU_ID__BE_PPDU_ID___POR 0x0 +#define WMAC0_RXPCU_R0_PPDU_ID__FE_PPDU_ID___POR 0x0 +#define WMAC0_RXPCU_R0_PPDU_ID__BE_IDLE___M 0x00000200 +#define WMAC0_RXPCU_R0_PPDU_ID__BE_IDLE___S 9 +#define WMAC0_RXPCU_R0_PPDU_ID__FE_IDLE___M 0x00000100 +#define WMAC0_RXPCU_R0_PPDU_ID__FE_IDLE___S 8 +#define WMAC0_RXPCU_R0_PPDU_ID__BE_PPDU_ID___M 0x000000F0 +#define WMAC0_RXPCU_R0_PPDU_ID__BE_PPDU_ID___S 4 +#define WMAC0_RXPCU_R0_PPDU_ID__FE_PPDU_ID___M 0x0000000F +#define WMAC0_RXPCU_R0_PPDU_ID__FE_PPDU_ID___S 0 +#define WMAC0_RXPCU_R0_PPDU_ID___M 0x000003FF +#define WMAC0_RXPCU_R0_PPDU_ID___S 0 + +#define WMAC0_RXPCU_R0_LSIG_DELAY (0x00A8C4C0) +#define WMAC0_RXPCU_R0_LSIG_DELAY___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_LSIG_DELAY___POR 0x00000000 +#define WMAC0_RXPCU_R0_LSIG_DELAY__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R0_LSIG_DELAY__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R0_LSIG_DELAY__VALUE___S 0 +#define WMAC0_RXPCU_R0_LSIG_DELAY___M 0x0000FFFF +#define WMAC0_RXPCU_R0_LSIG_DELAY___S 0 + +#define WMAC0_RXPCU_R0_RX_PPDU_SIG_REFERENCE (0x00A8C4C4) +#define WMAC0_RXPCU_R0_RX_PPDU_SIG_REFERENCE___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RX_PPDU_SIG_REFERENCE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RX_PPDU_SIG_REFERENCE__VHT_HE_SIG_B_ENC___POR 0x0 +#define WMAC0_RXPCU_R0_RX_PPDU_SIG_REFERENCE__HT_VHT_HE_SIG_A_ENC___POR 0x0 +#define WMAC0_RXPCU_R0_RX_PPDU_SIG_REFERENCE__L_SIG_A_B_ENC___POR 0x0 +#define WMAC0_RXPCU_R0_RX_PPDU_SIG_REFERENCE__VHT_HE_SIG_B_ENC___M 0x000001E0 +#define WMAC0_RXPCU_R0_RX_PPDU_SIG_REFERENCE__VHT_HE_SIG_B_ENC___S 5 +#define WMAC0_RXPCU_R0_RX_PPDU_SIG_REFERENCE__HT_VHT_HE_SIG_A_ENC___M 0x0000001C +#define WMAC0_RXPCU_R0_RX_PPDU_SIG_REFERENCE__HT_VHT_HE_SIG_A_ENC___S 2 +#define WMAC0_RXPCU_R0_RX_PPDU_SIG_REFERENCE__L_SIG_A_B_ENC___M 0x00000003 +#define WMAC0_RXPCU_R0_RX_PPDU_SIG_REFERENCE__L_SIG_A_B_ENC___S 0 +#define WMAC0_RXPCU_R0_RX_PPDU_SIG_REFERENCE___M 0x000001FF +#define WMAC0_RXPCU_R0_RX_PPDU_SIG_REFERENCE___S 0 + +#define WMAC0_RXPCU_R0_RX_PPDU_L_SIG_A_B (0x00A8C4C8) +#define WMAC0_RXPCU_R0_RX_PPDU_L_SIG_A_B___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RX_PPDU_L_SIG_A_B___POR 0x00000000 +#define WMAC0_RXPCU_R0_RX_PPDU_L_SIG_A_B__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RX_PPDU_L_SIG_A_B__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RX_PPDU_L_SIG_A_B__VALUE___S 0 +#define WMAC0_RXPCU_R0_RX_PPDU_L_SIG_A_B___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RX_PPDU_L_SIG_A_B___S 0 + +#define WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_n(n) (0x00A8C4CC+0x4*(n)) +#define WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_n_nMIN 0 +#define WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_n_nMAX 3 +#define WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_n_ELEM 4 +#define WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_n___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_n___POR 0x00000000 +#define WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_n__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_n__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_n__VALUE___S 0 +#define WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_n___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_n___S 0 +#define WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_0 (0x00A8C4CC) +#define WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_0___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_0__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_0__VALUE___S 0 +#define WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_1 (0x00A8C4D0) +#define WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_1___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_1__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_1__VALUE___S 0 +#define WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_2 (0x00A8C4D4) +#define WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_2___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_2__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_2__VALUE___S 0 +#define WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_3 (0x00A8C4D8) +#define WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_3___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_3__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RX_PPDU_HT_VHT_HE_SIG_A_3__VALUE___S 0 + +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_n(n) (0x00A8C4DC+0x4*(n)) +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_n_nMIN 0 +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_n_nMAX 7 +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_n_ELEM 8 +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_n___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_n___POR 0x00000000 +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_n__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_n__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_n__VALUE___S 0 +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_n___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_n___S 0 +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_0 (0x00A8C4DC) +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_0___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_0__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_0__VALUE___S 0 +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_1 (0x00A8C4E0) +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_1___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_1__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_1__VALUE___S 0 +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_2 (0x00A8C4E4) +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_2___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_2__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_2__VALUE___S 0 +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_3 (0x00A8C4E8) +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_3___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_3__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_3__VALUE___S 0 +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_4 (0x00A8C4EC) +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_4___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_4__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_4__VALUE___S 0 +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_5 (0x00A8C4F0) +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_5___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_5__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_5__VALUE___S 0 +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_6 (0x00A8C4F4) +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_6___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_6__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_6__VALUE___S 0 +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_7 (0x00A8C4F8) +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_7___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_7__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RX_PPDU_VHT_HE_SIG_B_7__VALUE___S 0 + +#define WMAC0_RXPCU_R0_MPDU_HDR_n(n) (0x00A8C4FC+0x4*(n)) +#define WMAC0_RXPCU_R0_MPDU_HDR_n_nMIN 0 +#define WMAC0_RXPCU_R0_MPDU_HDR_n_nMAX 15 +#define WMAC0_RXPCU_R0_MPDU_HDR_n_ELEM 16 +#define WMAC0_RXPCU_R0_MPDU_HDR_n___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_MPDU_HDR_n___POR 0x00000000 +#define WMAC0_RXPCU_R0_MPDU_HDR_n__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R0_MPDU_HDR_n__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_MPDU_HDR_n__VALUE___S 0 +#define WMAC0_RXPCU_R0_MPDU_HDR_n___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_MPDU_HDR_n___S 0 +#define WMAC0_RXPCU_R0_MPDU_HDR_0 (0x00A8C4FC) +#define WMAC0_RXPCU_R0_MPDU_HDR_0___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_MPDU_HDR_0__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_MPDU_HDR_0__VALUE___S 0 +#define WMAC0_RXPCU_R0_MPDU_HDR_1 (0x00A8C500) +#define WMAC0_RXPCU_R0_MPDU_HDR_1___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_MPDU_HDR_1__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_MPDU_HDR_1__VALUE___S 0 +#define WMAC0_RXPCU_R0_MPDU_HDR_2 (0x00A8C504) +#define WMAC0_RXPCU_R0_MPDU_HDR_2___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_MPDU_HDR_2__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_MPDU_HDR_2__VALUE___S 0 +#define WMAC0_RXPCU_R0_MPDU_HDR_3 (0x00A8C508) +#define WMAC0_RXPCU_R0_MPDU_HDR_3___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_MPDU_HDR_3__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_MPDU_HDR_3__VALUE___S 0 +#define WMAC0_RXPCU_R0_MPDU_HDR_4 (0x00A8C50C) +#define WMAC0_RXPCU_R0_MPDU_HDR_4___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_MPDU_HDR_4__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_MPDU_HDR_4__VALUE___S 0 +#define WMAC0_RXPCU_R0_MPDU_HDR_5 (0x00A8C510) +#define WMAC0_RXPCU_R0_MPDU_HDR_5___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_MPDU_HDR_5__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_MPDU_HDR_5__VALUE___S 0 +#define WMAC0_RXPCU_R0_MPDU_HDR_6 (0x00A8C514) +#define WMAC0_RXPCU_R0_MPDU_HDR_6___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_MPDU_HDR_6__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_MPDU_HDR_6__VALUE___S 0 +#define WMAC0_RXPCU_R0_MPDU_HDR_7 (0x00A8C518) +#define WMAC0_RXPCU_R0_MPDU_HDR_7___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_MPDU_HDR_7__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_MPDU_HDR_7__VALUE___S 0 +#define WMAC0_RXPCU_R0_MPDU_HDR_8 (0x00A8C51C) +#define WMAC0_RXPCU_R0_MPDU_HDR_8___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_MPDU_HDR_8__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_MPDU_HDR_8__VALUE___S 0 +#define WMAC0_RXPCU_R0_MPDU_HDR_9 (0x00A8C520) +#define WMAC0_RXPCU_R0_MPDU_HDR_9___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_MPDU_HDR_9__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_MPDU_HDR_9__VALUE___S 0 +#define WMAC0_RXPCU_R0_MPDU_HDR_10 (0x00A8C524) +#define WMAC0_RXPCU_R0_MPDU_HDR_10___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_MPDU_HDR_10__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_MPDU_HDR_10__VALUE___S 0 +#define WMAC0_RXPCU_R0_MPDU_HDR_11 (0x00A8C528) +#define WMAC0_RXPCU_R0_MPDU_HDR_11___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_MPDU_HDR_11__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_MPDU_HDR_11__VALUE___S 0 +#define WMAC0_RXPCU_R0_MPDU_HDR_12 (0x00A8C52C) +#define WMAC0_RXPCU_R0_MPDU_HDR_12___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_MPDU_HDR_12__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_MPDU_HDR_12__VALUE___S 0 +#define WMAC0_RXPCU_R0_MPDU_HDR_13 (0x00A8C530) +#define WMAC0_RXPCU_R0_MPDU_HDR_13___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_MPDU_HDR_13__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_MPDU_HDR_13__VALUE___S 0 +#define WMAC0_RXPCU_R0_MPDU_HDR_14 (0x00A8C534) +#define WMAC0_RXPCU_R0_MPDU_HDR_14___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_MPDU_HDR_14__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_MPDU_HDR_14__VALUE___S 0 +#define WMAC0_RXPCU_R0_MPDU_HDR_15 (0x00A8C538) +#define WMAC0_RXPCU_R0_MPDU_HDR_15___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R0_MPDU_HDR_15__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_MPDU_HDR_15__VALUE___S 0 + +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL (0x00A8C53C) +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL___POR 0x00000000 +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__AST_PREFECH_NOT_FIND_INT_EN___POR 0x0 +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__USER_SETUP_EXT_LOST_INT_EN___POR 0x0 +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__BA_LOST_INT_EN___POR 0x0 +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__BA_OCUUPIED_REWRITE_INT_EN___POR 0x0 +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__INDEX_FIFO_FULL_INT_EN___POR 0x0 +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__SFM_CLIENT_1_FIFO_FULL_INT_EN___POR 0x0 +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__SFM_CLIENT_0_FIFO_FULL_INT_EN___POR 0x0 +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__RXPCU_BUSY_INT_EN___POR 0x0 +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__GSE_CMD_FULL_INT_EN___POR 0x0 +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__SPF_FIFO_FULL_INT_EN___POR 0x0 +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__SCF_FIFO_FULL_INT_EN___POR 0x0 +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__AST_PREFECH_NOT_FIND_INT_EN___M 0x00010000 +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__AST_PREFECH_NOT_FIND_INT_EN___S 16 +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__USER_SETUP_EXT_LOST_INT_EN___M 0x00000200 +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__USER_SETUP_EXT_LOST_INT_EN___S 9 +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__BA_LOST_INT_EN___M 0x00000100 +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__BA_LOST_INT_EN___S 8 +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__BA_OCUUPIED_REWRITE_INT_EN___M 0x00000080 +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__BA_OCUUPIED_REWRITE_INT_EN___S 7 +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__INDEX_FIFO_FULL_INT_EN___M 0x00000040 +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__INDEX_FIFO_FULL_INT_EN___S 6 +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__SFM_CLIENT_1_FIFO_FULL_INT_EN___M 0x00000020 +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__SFM_CLIENT_1_FIFO_FULL_INT_EN___S 5 +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__SFM_CLIENT_0_FIFO_FULL_INT_EN___M 0x00000010 +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__SFM_CLIENT_0_FIFO_FULL_INT_EN___S 4 +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__RXPCU_BUSY_INT_EN___M 0x00000008 +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__RXPCU_BUSY_INT_EN___S 3 +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__GSE_CMD_FULL_INT_EN___M 0x00000004 +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__GSE_CMD_FULL_INT_EN___S 2 +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__SPF_FIFO_FULL_INT_EN___M 0x00000002 +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__SPF_FIFO_FULL_INT_EN___S 1 +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__SCF_FIFO_FULL_INT_EN___M 0x00000001 +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL__SCF_FIFO_FULL_INT_EN___S 0 +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL___M 0x000103FF +#define WMAC0_RXPCU_R0_FIFO_FULL_INT_CTRL___S 0 + +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS (0x00A8C540) +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS___POR 0x00000000 +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__PHY_PPDU_ID___POR 0x0000 +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__FEPU_OVERFLOW_INT_SOURCE___POR 0x0 +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__USER_SETUP_EXT_LOST___POR 0x0 +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__BA_LOST___POR 0x0 +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__BA_OCUUPIED_REWRITE___POR 0x0 +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__SFM_CLIENT_0_FIFO_FULL___POR 0x0 +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__RXPCU_BUSY___POR 0x0 +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__GSE_CMD_FULL___POR 0x0 +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__SPF_FIFO_FULL___POR 0x0 +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__SCF_FIFO_FULL___POR 0x0 +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__PHY_PPDU_ID___M 0xFFFF0000 +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__PHY_PPDU_ID___S 16 +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__FEPU_OVERFLOW_INT_SOURCE___M 0x0000F000 +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__FEPU_OVERFLOW_INT_SOURCE___S 12 +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__USER_SETUP_EXT_LOST___M 0x00000080 +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__USER_SETUP_EXT_LOST___S 7 +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__BA_LOST___M 0x00000040 +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__BA_LOST___S 6 +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__BA_OCUUPIED_REWRITE___M 0x00000020 +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__BA_OCUUPIED_REWRITE___S 5 +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__SFM_CLIENT_0_FIFO_FULL___M 0x00000010 +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__SFM_CLIENT_0_FIFO_FULL___S 4 +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__RXPCU_BUSY___M 0x00000008 +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__RXPCU_BUSY___S 3 +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__GSE_CMD_FULL___M 0x00000004 +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__GSE_CMD_FULL___S 2 +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__SPF_FIFO_FULL___M 0x00000002 +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__SPF_FIFO_FULL___S 1 +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__SCF_FIFO_FULL___M 0x00000001 +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS__SCF_FIFO_FULL___S 0 +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS___M 0xFFFFF0FF +#define WMAC0_RXPCU_R0_FEPU_FIFO_FULL_STATUS___S 0 + +#define WMAC0_RXPCU_R0_BEPU_FIFO_FULL_STATUS (0x00A8C544) +#define WMAC0_RXPCU_R0_BEPU_FIFO_FULL_STATUS___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_BEPU_FIFO_FULL_STATUS___POR 0x00000000 +#define WMAC0_RXPCU_R0_BEPU_FIFO_FULL_STATUS__BEPU_OVERFLOW_INT_SOURCE___POR 0x0 +#define WMAC0_RXPCU_R0_BEPU_FIFO_FULL_STATUS__INDEX_FIFO_FULL___POR 0x0 +#define WMAC0_RXPCU_R0_BEPU_FIFO_FULL_STATUS__SFM_CLIENT_1_FIFO_FULL___POR 0x0 +#define WMAC0_RXPCU_R0_BEPU_FIFO_FULL_STATUS__BEPU_OVERFLOW_INT_SOURCE___M 0x0000F000 +#define WMAC0_RXPCU_R0_BEPU_FIFO_FULL_STATUS__BEPU_OVERFLOW_INT_SOURCE___S 12 +#define WMAC0_RXPCU_R0_BEPU_FIFO_FULL_STATUS__INDEX_FIFO_FULL___M 0x00000002 +#define WMAC0_RXPCU_R0_BEPU_FIFO_FULL_STATUS__INDEX_FIFO_FULL___S 1 +#define WMAC0_RXPCU_R0_BEPU_FIFO_FULL_STATUS__SFM_CLIENT_1_FIFO_FULL___M 0x00000001 +#define WMAC0_RXPCU_R0_BEPU_FIFO_FULL_STATUS__SFM_CLIENT_1_FIFO_FULL___S 0 +#define WMAC0_RXPCU_R0_BEPU_FIFO_FULL_STATUS___M 0x0000F003 +#define WMAC0_RXPCU_R0_BEPU_FIFO_FULL_STATUS___S 0 + +#define WMAC0_RXPCU_R0_RFF_SFM_OVERFLOW_CFG (0x00A8C548) +#define WMAC0_RXPCU_R0_RFF_SFM_OVERFLOW_CFG___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_SFM_OVERFLOW_CFG___POR 0x002041CC +#define WMAC0_RXPCU_R0_RFF_SFM_OVERFLOW_CFG__CLIENT_1_PPDU_START_THRESH___POR 0x08 +#define WMAC0_RXPCU_R0_RFF_SFM_OVERFLOW_CFG__CLIENT_0_PPDU_END_THRESH___POR 0x04 +#define WMAC0_RXPCU_R0_RFF_SFM_OVERFLOW_CFG__CLIENT_0_MPDU_THRESH___POR 0x07 +#define WMAC0_RXPCU_R0_RFF_SFM_OVERFLOW_CFG__CLIENT_0_PPDU_START_THRESH___POR 0x0C +#define WMAC0_RXPCU_R0_RFF_SFM_OVERFLOW_CFG__CLIENT_1_PPDU_START_THRESH___M 0x00FC0000 +#define WMAC0_RXPCU_R0_RFF_SFM_OVERFLOW_CFG__CLIENT_1_PPDU_START_THRESH___S 18 +#define WMAC0_RXPCU_R0_RFF_SFM_OVERFLOW_CFG__CLIENT_0_PPDU_END_THRESH___M 0x0003F000 +#define WMAC0_RXPCU_R0_RFF_SFM_OVERFLOW_CFG__CLIENT_0_PPDU_END_THRESH___S 12 +#define WMAC0_RXPCU_R0_RFF_SFM_OVERFLOW_CFG__CLIENT_0_MPDU_THRESH___M 0x00000FC0 +#define WMAC0_RXPCU_R0_RFF_SFM_OVERFLOW_CFG__CLIENT_0_MPDU_THRESH___S 6 +#define WMAC0_RXPCU_R0_RFF_SFM_OVERFLOW_CFG__CLIENT_0_PPDU_START_THRESH___M 0x0000003F +#define WMAC0_RXPCU_R0_RFF_SFM_OVERFLOW_CFG__CLIENT_0_PPDU_START_THRESH___S 0 +#define WMAC0_RXPCU_R0_RFF_SFM_OVERFLOW_CFG___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_RFF_SFM_OVERFLOW_CFG___S 0 + +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX0 (0x00A8C54C) +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX0___POR 0x00000000 +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX0__DUE_TO_SPF_CNT___POR 0x0000 +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX0__DUE_TO_SCF_CNT___POR 0x0000 +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX0__DUE_TO_SPF_CNT___M 0xFFFF0000 +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX0__DUE_TO_SPF_CNT___S 16 +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX0__DUE_TO_SCF_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX0__DUE_TO_SCF_CNT___S 0 +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX0___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX0___S 0 + +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX1 (0x00A8C550) +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX1___POR 0x00000000 +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX1__DUE_TO_RXPCU_BUSY_CNT___POR 0x0000 +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX1__DUE_TO_SFM_CNT___POR 0x0000 +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX1__DUE_TO_RXPCU_BUSY_CNT___M 0xFFFF0000 +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX1__DUE_TO_RXPCU_BUSY_CNT___S 16 +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX1__DUE_TO_SFM_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX1__DUE_TO_SFM_CNT___S 0 +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX1___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_PPDU_CNT_IX1___S 0 + +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX0 (0x00A8C554) +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX0___POR 0x00000000 +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX0__DUE_TO_SPF_CNT___POR 0x0000 +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX0__DUE_TO_SCF_CNT___POR 0x0000 +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX0__DUE_TO_SPF_CNT___M 0xFFFF0000 +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX0__DUE_TO_SPF_CNT___S 16 +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX0__DUE_TO_SCF_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX0__DUE_TO_SCF_CNT___S 0 +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX0___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX0___S 0 + +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX1 (0x00A8C558) +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX1___POR 0x00000000 +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX1__DUE_TO_GSE_CNT___POR 0x0000 +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX1__DUE_TO_SFM_CNT___POR 0x0000 +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX1__DUE_TO_GSE_CNT___M 0xFFFF0000 +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX1__DUE_TO_GSE_CNT___S 16 +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX1__DUE_TO_SFM_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX1__DUE_TO_SFM_CNT___S 0 +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX1___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_NO_RESOURCE_AND_DROP_MPDU_CNT_IX1___S 0 + +#define WMAC0_RXPCU_R0_BRU_CTRL (0x00A8C55C) +#define WMAC0_RXPCU_R0_BRU_CTRL___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_BRU_CTRL___POR 0x00000000 +#define WMAC0_RXPCU_R0_BRU_CTRL__LEVEL_2_DEFARGMENTATION_ENABLE___POR 0x0 +#define WMAC0_RXPCU_R0_BRU_CTRL__EN_256_BA_BITMAP___POR 0x0 +#define WMAC0_RXPCU_R0_BRU_CTRL__INVALID_BITMAP_DONE___POR 0x0 +#define WMAC0_RXPCU_R0_BRU_CTRL__INVALID_BITMAP___POR 0x0 +#define WMAC0_RXPCU_R0_BRU_CTRL__INVALID_BITMAP_FOR_QOS___POR 0x0 +#define WMAC0_RXPCU_R0_BRU_CTRL__LEVEL_2_DEFARGMENTATION_ENABLE___M 0x00000010 +#define WMAC0_RXPCU_R0_BRU_CTRL__LEVEL_2_DEFARGMENTATION_ENABLE___S 4 +#define WMAC0_RXPCU_R0_BRU_CTRL__EN_256_BA_BITMAP___M 0x00000008 +#define WMAC0_RXPCU_R0_BRU_CTRL__EN_256_BA_BITMAP___S 3 +#define WMAC0_RXPCU_R0_BRU_CTRL__INVALID_BITMAP_DONE___M 0x00000004 +#define WMAC0_RXPCU_R0_BRU_CTRL__INVALID_BITMAP_DONE___S 2 +#define WMAC0_RXPCU_R0_BRU_CTRL__INVALID_BITMAP___M 0x00000002 +#define WMAC0_RXPCU_R0_BRU_CTRL__INVALID_BITMAP___S 1 +#define WMAC0_RXPCU_R0_BRU_CTRL__INVALID_BITMAP_FOR_QOS___M 0x00000001 +#define WMAC0_RXPCU_R0_BRU_CTRL__INVALID_BITMAP_FOR_QOS___S 0 +#define WMAC0_RXPCU_R0_BRU_CTRL___M 0x0000001F +#define WMAC0_RXPCU_R0_BRU_CTRL___S 0 + +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL (0x00A8C560) +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL___POR 0x0003FFFF +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_NO_RESPONSE_CAS_NAV_FAIL___POR 0x1 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_NO_ACK_REPORT___POR 0x1 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_NO_RESPONSE_OTHER___POR 0x1 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_MAC_ABORT___POR 0x1 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_TRIGGER_NO_AID___POR 0x1 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_TRIGGER_NAV_BLOCKED___POR 0x1 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_NDP_FRAME___POR 0x1 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_NDPA_FRAME___POR 0x1 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_RTS_BW_NOT_AVAILABLE___POR 0x1 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_PHY_ERROR___POR 0x1 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_PHY_AID_MISMATCH___POR 0x1 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_PHY_GID_MISMATCH___POR 0x1 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_AST_NO_ACK___POR 0x1 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_NOT_DIRECTED___POR 0x1 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_MCAST___POR 0x1 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_BCAST___POR 0x1 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_UCAST_NO_ACK_FRAME___POR 0x1 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_FCS_ERRORS___POR 0x1 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_NO_RESPONSE_CAS_NAV_FAIL___M 0x00020000 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_NO_RESPONSE_CAS_NAV_FAIL___S 17 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_NO_ACK_REPORT___M 0x00010000 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_NO_ACK_REPORT___S 16 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_NO_RESPONSE_OTHER___M 0x00008000 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_NO_RESPONSE_OTHER___S 15 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_MAC_ABORT___M 0x00004000 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_MAC_ABORT___S 14 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_TRIGGER_NO_AID___M 0x00002000 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_TRIGGER_NO_AID___S 13 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_TRIGGER_NAV_BLOCKED___M 0x00001000 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_TRIGGER_NAV_BLOCKED___S 12 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_NDP_FRAME___M 0x00000800 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_NDP_FRAME___S 11 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_NDPA_FRAME___M 0x00000400 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_NDPA_FRAME___S 10 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_RTS_BW_NOT_AVAILABLE___M 0x00000200 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_RTS_BW_NOT_AVAILABLE___S 9 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_PHY_ERROR___M 0x00000100 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_PHY_ERROR___S 8 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_PHY_AID_MISMATCH___M 0x00000080 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_PHY_AID_MISMATCH___S 7 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_PHY_GID_MISMATCH___M 0x00000040 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_PHY_GID_MISMATCH___S 6 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_AST_NO_ACK___M 0x00000020 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_AST_NO_ACK___S 5 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_NOT_DIRECTED___M 0x00000010 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_NOT_DIRECTED___S 4 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_MCAST___M 0x00000008 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_MCAST___S 3 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_BCAST___M 0x00000004 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_BCAST___S 2 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_UCAST_NO_ACK_FRAME___M 0x00000002 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_UCAST_NO_ACK_FRAME___S 1 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_FCS_ERRORS___M 0x00000001 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL__DISABLE_REPORT_FCS_ERRORS___S 0 +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL___M 0x0003FFFF +#define WMAC0_RXPCU_R0_NOACK_REPORT_CTRL___S 0 + +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL (0x00A8C564) +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL___POR 0x003FC07F +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_BA_FRAME_CAS___POR 0x1 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_ACK_FRAME_CAS___POR 0x1 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_ACK_REPORT___POR 0x1 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__FORCE_ACK_REPORT_FOR_TM_FTM___POR 0x1 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_RESP_TO_RESP_FRAME___POR 0x1 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_11AX_MU_RTS___POR 0x1 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_11AX_MU_BAR___POR 0x1 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_11AX_BRPOLL___POR 0x1 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_WILDCARD_BUF_SIZE_TRIGGER___POR 0x0 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_BUF_SIZE_TRIGGER___POR 0x0 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_WILDCARD_BQRP_TRIGGER___POR 0x0 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_BQRP_TRIGGER___POR 0x0 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_USASSOC_WILDCARD_BASIC_TRIGGER___POR 0x0 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_WILDCARD_BASIC_TRIGGER___POR 0x0 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_BASIC_TRIGGER___POR 0x0 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_CBF_FRAME___POR 0x1 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_UAPSD_TRIGGER___POR 0x1 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_PSPOLL_TRIGGER___POR 0x1 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_QBOOST_TRIGGER___POR 0x1 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_BA_FRAME___POR 0x1 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_ACK_FRAME___POR 0x1 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_CTS_FRAME___POR 0x1 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_BA_FRAME_CAS___M 0x00200000 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_BA_FRAME_CAS___S 21 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_ACK_FRAME_CAS___M 0x00100000 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_ACK_FRAME_CAS___S 20 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_ACK_REPORT___M 0x00080000 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_ACK_REPORT___S 19 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__FORCE_ACK_REPORT_FOR_TM_FTM___M 0x00040000 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__FORCE_ACK_REPORT_FOR_TM_FTM___S 18 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_RESP_TO_RESP_FRAME___M 0x00020000 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_RESP_TO_RESP_FRAME___S 17 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_11AX_MU_RTS___M 0x00010000 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_11AX_MU_RTS___S 16 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_11AX_MU_BAR___M 0x00008000 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_11AX_MU_BAR___S 15 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_11AX_BRPOLL___M 0x00004000 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_11AX_BRPOLL___S 14 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_WILDCARD_BUF_SIZE_TRIGGER___M 0x00002000 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_WILDCARD_BUF_SIZE_TRIGGER___S 13 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_BUF_SIZE_TRIGGER___M 0x00001000 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_BUF_SIZE_TRIGGER___S 12 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_WILDCARD_BQRP_TRIGGER___M 0x00000800 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_WILDCARD_BQRP_TRIGGER___S 11 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_BQRP_TRIGGER___M 0x00000400 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_BQRP_TRIGGER___S 10 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_USASSOC_WILDCARD_BASIC_TRIGGER___M 0x00000200 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_USASSOC_WILDCARD_BASIC_TRIGGER___S 9 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_WILDCARD_BASIC_TRIGGER___M 0x00000100 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_WILDCARD_BASIC_TRIGGER___S 8 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_BASIC_TRIGGER___M 0x00000080 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_OFDMA_BASIC_TRIGGER___S 7 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_CBF_FRAME___M 0x00000040 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_CBF_FRAME___S 6 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_UAPSD_TRIGGER___M 0x00000020 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_UAPSD_TRIGGER___S 5 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_PSPOLL_TRIGGER___M 0x00000010 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_PSPOLL_TRIGGER___S 4 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_QBOOST_TRIGGER___M 0x00000008 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_QBOOST_TRIGGER___S 3 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_BA_FRAME___M 0x00000004 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_BA_FRAME___S 2 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_ACK_FRAME___M 0x00000002 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_ACK_FRAME___S 1 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_CTS_FRAME___M 0x00000001 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL__DISABLE_REPORT_CTS_FRAME___S 0 +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL___M 0x003FFFFF +#define WMAC0_RXPCU_R0_ACK_REPORT_CTRL___S 0 + +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0 (0x00A8C568) +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0___POR 0x00000000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_F_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_E_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_D_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_C_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_B_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_A_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_9_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_8_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_7_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_6_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_5_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_4_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_3_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_2_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_1_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_0_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_F_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_E_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_D_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_C_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_B_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_A_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_9_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_8_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_7_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_6_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_5_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_4_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_3_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_2_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_1_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_0_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_F_DROP___M 0x80000000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_F_DROP___S 31 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_E_DROP___M 0x40000000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_E_DROP___S 30 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_D_DROP___M 0x20000000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_D_DROP___S 29 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_C_DROP___M 0x10000000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_C_DROP___S 28 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_B_DROP___M 0x08000000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_B_DROP___S 27 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_A_DROP___M 0x04000000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_A_DROP___S 26 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_9_DROP___M 0x02000000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_9_DROP___S 25 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_8_DROP___M 0x01000000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_8_DROP___S 24 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_7_DROP___M 0x00800000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_7_DROP___S 23 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_6_DROP___M 0x00400000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_6_DROP___S 22 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_5_DROP___M 0x00200000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_5_DROP___S 21 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_4_DROP___M 0x00100000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_4_DROP___S 20 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_3_DROP___M 0x00080000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_3_DROP___S 19 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_2_DROP___M 0x00040000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_2_DROP___S 18 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_1_DROP___M 0x00020000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_1_DROP___S 17 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_0_DROP___M 0x00010000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_1_0_DROP___S 16 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_F_DROP___M 0x00008000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_F_DROP___S 15 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_E_DROP___M 0x00004000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_E_DROP___S 14 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_D_DROP___M 0x00002000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_D_DROP___S 13 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_C_DROP___M 0x00001000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_C_DROP___S 12 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_B_DROP___M 0x00000800 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_B_DROP___S 11 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_A_DROP___M 0x00000400 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_A_DROP___S 10 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_9_DROP___M 0x00000200 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_9_DROP___S 9 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_8_DROP___M 0x00000100 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_8_DROP___S 8 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_7_DROP___M 0x00000080 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_7_DROP___S 7 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_6_DROP___M 0x00000040 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_6_DROP___S 6 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_5_DROP___M 0x00000020 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_5_DROP___S 5 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_4_DROP___M 0x00000010 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_4_DROP___S 4 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_3_DROP___M 0x00000008 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_3_DROP___S 3 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_2_DROP___M 0x00000004 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_2_DROP___S 2 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_1_DROP___M 0x00000002 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_1_DROP___S 1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_0_DROP___M 0x00000001 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0__TYPE_SUBTYPE_0_0_DROP___S 0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX0___S 0 + +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1 (0x00A8C56C) +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1___POR 0x00000000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_F_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_E_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_D_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_C_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_B_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_A_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_9_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_8_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_7_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_6_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_5_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_4_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_3_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_2_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_1_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_0_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_F_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_E_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_D_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_C_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_B_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_A_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_9_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_8_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_7_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_6_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_5_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_4_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_3_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_2_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_1_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_0_DROP___POR 0x0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_F_DROP___M 0x80000000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_F_DROP___S 31 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_E_DROP___M 0x40000000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_E_DROP___S 30 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_D_DROP___M 0x20000000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_D_DROP___S 29 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_C_DROP___M 0x10000000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_C_DROP___S 28 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_B_DROP___M 0x08000000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_B_DROP___S 27 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_A_DROP___M 0x04000000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_A_DROP___S 26 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_9_DROP___M 0x02000000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_9_DROP___S 25 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_8_DROP___M 0x01000000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_8_DROP___S 24 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_7_DROP___M 0x00800000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_7_DROP___S 23 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_6_DROP___M 0x00400000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_6_DROP___S 22 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_5_DROP___M 0x00200000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_5_DROP___S 21 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_4_DROP___M 0x00100000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_4_DROP___S 20 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_3_DROP___M 0x00080000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_3_DROP___S 19 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_2_DROP___M 0x00040000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_2_DROP___S 18 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_1_DROP___M 0x00020000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_1_DROP___S 17 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_0_DROP___M 0x00010000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_3_0_DROP___S 16 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_F_DROP___M 0x00008000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_F_DROP___S 15 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_E_DROP___M 0x00004000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_E_DROP___S 14 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_D_DROP___M 0x00002000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_D_DROP___S 13 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_C_DROP___M 0x00001000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_C_DROP___S 12 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_B_DROP___M 0x00000800 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_B_DROP___S 11 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_A_DROP___M 0x00000400 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_A_DROP___S 10 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_9_DROP___M 0x00000200 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_9_DROP___S 9 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_8_DROP___M 0x00000100 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_8_DROP___S 8 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_7_DROP___M 0x00000080 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_7_DROP___S 7 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_6_DROP___M 0x00000040 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_6_DROP___S 6 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_5_DROP___M 0x00000020 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_5_DROP___S 5 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_4_DROP___M 0x00000010 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_4_DROP___S 4 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_3_DROP___M 0x00000008 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_3_DROP___S 3 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_2_DROP___M 0x00000004 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_2_DROP___S 2 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_1_DROP___M 0x00000002 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_1_DROP___S 1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_0_DROP___M 0x00000001 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1__TYPE_SUBTYPE_2_0_DROP___S 0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_FILTER_MONITOR_DIRECT_IX1___S 0 + +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0 (0x00A8C570) +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0___POR 0xFFFFFFFF +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_F_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_E_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_D_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_C_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_B_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_A_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_9_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_8_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_7_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_6_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_5_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_4_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_3_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_2_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_1_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_0_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_F_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_E_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_D_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_C_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_B_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_A_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_9_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_8_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_7_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_6_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_5_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_4_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_3_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_2_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_1_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_0_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_F_DROP___M 0x80000000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_F_DROP___S 31 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_E_DROP___M 0x40000000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_E_DROP___S 30 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_D_DROP___M 0x20000000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_D_DROP___S 29 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_C_DROP___M 0x10000000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_C_DROP___S 28 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_B_DROP___M 0x08000000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_B_DROP___S 27 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_A_DROP___M 0x04000000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_A_DROP___S 26 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_9_DROP___M 0x02000000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_9_DROP___S 25 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_8_DROP___M 0x01000000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_8_DROP___S 24 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_7_DROP___M 0x00800000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_7_DROP___S 23 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_6_DROP___M 0x00400000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_6_DROP___S 22 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_5_DROP___M 0x00200000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_5_DROP___S 21 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_4_DROP___M 0x00100000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_4_DROP___S 20 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_3_DROP___M 0x00080000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_3_DROP___S 19 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_2_DROP___M 0x00040000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_2_DROP___S 18 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_1_DROP___M 0x00020000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_1_DROP___S 17 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_0_DROP___M 0x00010000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_1_0_DROP___S 16 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_F_DROP___M 0x00008000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_F_DROP___S 15 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_E_DROP___M 0x00004000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_E_DROP___S 14 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_D_DROP___M 0x00002000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_D_DROP___S 13 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_C_DROP___M 0x00001000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_C_DROP___S 12 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_B_DROP___M 0x00000800 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_B_DROP___S 11 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_A_DROP___M 0x00000400 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_A_DROP___S 10 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_9_DROP___M 0x00000200 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_9_DROP___S 9 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_8_DROP___M 0x00000100 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_8_DROP___S 8 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_7_DROP___M 0x00000080 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_7_DROP___S 7 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_6_DROP___M 0x00000040 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_6_DROP___S 6 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_5_DROP___M 0x00000020 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_5_DROP___S 5 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_4_DROP___M 0x00000010 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_4_DROP___S 4 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_3_DROP___M 0x00000008 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_3_DROP___S 3 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_2_DROP___M 0x00000004 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_2_DROP___S 2 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_1_DROP___M 0x00000002 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_1_DROP___S 1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_0_DROP___M 0x00000001 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0__TYPE_SUBTYPE_0_0_DROP___S 0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX0___S 0 + +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1 (0x00A8C574) +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1___POR 0xFFFFFFFF +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_F_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_E_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_D_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_C_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_B_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_A_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_9_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_8_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_7_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_6_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_5_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_4_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_3_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_2_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_1_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_0_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_F_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_E_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_D_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_C_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_B_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_A_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_9_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_8_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_7_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_6_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_5_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_4_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_3_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_2_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_1_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_0_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_F_DROP___M 0x80000000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_F_DROP___S 31 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_E_DROP___M 0x40000000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_E_DROP___S 30 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_D_DROP___M 0x20000000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_D_DROP___S 29 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_C_DROP___M 0x10000000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_C_DROP___S 28 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_B_DROP___M 0x08000000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_B_DROP___S 27 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_A_DROP___M 0x04000000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_A_DROP___S 26 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_9_DROP___M 0x02000000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_9_DROP___S 25 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_8_DROP___M 0x01000000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_8_DROP___S 24 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_7_DROP___M 0x00800000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_7_DROP___S 23 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_6_DROP___M 0x00400000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_6_DROP___S 22 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_5_DROP___M 0x00200000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_5_DROP___S 21 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_4_DROP___M 0x00100000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_4_DROP___S 20 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_3_DROP___M 0x00080000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_3_DROP___S 19 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_2_DROP___M 0x00040000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_2_DROP___S 18 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_1_DROP___M 0x00020000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_1_DROP___S 17 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_0_DROP___M 0x00010000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_3_0_DROP___S 16 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_F_DROP___M 0x00008000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_F_DROP___S 15 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_E_DROP___M 0x00004000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_E_DROP___S 14 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_D_DROP___M 0x00002000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_D_DROP___S 13 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_C_DROP___M 0x00001000 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_C_DROP___S 12 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_B_DROP___M 0x00000800 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_B_DROP___S 11 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_A_DROP___M 0x00000400 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_A_DROP___S 10 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_9_DROP___M 0x00000200 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_9_DROP___S 9 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_8_DROP___M 0x00000100 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_8_DROP___S 8 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_7_DROP___M 0x00000080 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_7_DROP___S 7 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_6_DROP___M 0x00000040 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_6_DROP___S 6 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_5_DROP___M 0x00000020 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_5_DROP___S 5 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_4_DROP___M 0x00000010 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_4_DROP___S 4 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_3_DROP___M 0x00000008 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_3_DROP___S 3 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_2_DROP___M 0x00000004 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_2_DROP___S 2 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_1_DROP___M 0x00000002 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_1_DROP___S 1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_0_DROP___M 0x00000001 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1__TYPE_SUBTYPE_2_0_DROP___S 0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX1___S 0 + +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX2 (0x00A8C578) +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX2___POR 0x00000001 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX2__NDP_DROP___POR 0x1 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX2__NDP_DROP___M 0x00000001 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX2__NDP_DROP___S 0 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX2___M 0x00000001 +#define WMAC0_RXPCU_R0_FILTER_MONITOR_OTHER_IX2___S 0 + +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX0 (0x00A8C57C) +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX0___POR 0x00000001 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX0__GI_THRESH1_EN___POR 0x00 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX0__ED_THRESH3_EN___POR 0x00 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX0__ED_THRESH2_EN___POR 0x00 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX0__ED_THRESH1_EN___POR 0x01 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX0__GI_THRESH1_EN___M 0xFF000000 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX0__GI_THRESH1_EN___S 24 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX0__ED_THRESH3_EN___M 0x00FF0000 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX0__ED_THRESH3_EN___S 16 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX0__ED_THRESH2_EN___M 0x0000FF00 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX0__ED_THRESH2_EN___S 8 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX0__ED_THRESH1_EN___M 0x000000FF +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX0__ED_THRESH1_EN___S 0 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX0___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX0___S 0 + +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX1 (0x00A8C580) +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX1___POR 0x00000000 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX1__GI_THRESH3_EN___POR 0x00 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX1__GI_THRESH2_EN___POR 0x00 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX1__GI_THRESH3_EN___M 0x0000FF00 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX1__GI_THRESH3_EN___S 8 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX1__GI_THRESH2_EN___M 0x000000FF +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX1__GI_THRESH2_EN___S 0 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX1___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_PRI_IX1___S 0 + +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX0 (0x00A8C584) +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX0___POR 0x00000003 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX0__GI_THRESH1_EN___POR 0x00 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX0__ED_THRESH3_EN___POR 0x00 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX0__ED_THRESH2_EN___POR 0x00 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX0__ED_THRESH1_EN___POR 0x03 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX0__GI_THRESH1_EN___M 0xFF000000 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX0__GI_THRESH1_EN___S 24 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX0__ED_THRESH3_EN___M 0x00FF0000 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX0__ED_THRESH3_EN___S 16 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX0__ED_THRESH2_EN___M 0x0000FF00 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX0__ED_THRESH2_EN___S 8 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX0__ED_THRESH1_EN___M 0x000000FF +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX0__ED_THRESH1_EN___S 0 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX0___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX0___S 0 + +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX1 (0x00A8C588) +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX1___POR 0x00000000 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX1__GI_THRESH3_EN___POR 0x00 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX1__GI_THRESH2_EN___POR 0x00 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX1__GI_THRESH3_EN___M 0x0000FF00 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX1__GI_THRESH3_EN___S 8 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX1__GI_THRESH2_EN___M 0x000000FF +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX1__GI_THRESH2_EN___S 0 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX1___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC20_IX1___S 0 + +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX0 (0x00A8C58C) +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX0___POR 0x0000000F +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX0__GI_THRESH1_EN___POR 0x00 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX0__ED_THRESH3_EN___POR 0x00 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX0__ED_THRESH2_EN___POR 0x00 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX0__ED_THRESH1_EN___POR 0x0F +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX0__GI_THRESH1_EN___M 0xFF000000 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX0__GI_THRESH1_EN___S 24 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX0__ED_THRESH3_EN___M 0x00FF0000 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX0__ED_THRESH3_EN___S 16 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX0__ED_THRESH2_EN___M 0x0000FF00 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX0__ED_THRESH2_EN___S 8 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX0__ED_THRESH1_EN___M 0x000000FF +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX0__ED_THRESH1_EN___S 0 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX0___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX0___S 0 + +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX1 (0x00A8C590) +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX1___POR 0x00000000 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX1__GI_THRESH3_EN___POR 0x00 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX1__GI_THRESH2_EN___POR 0x00 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX1__GI_THRESH3_EN___M 0x0000FF00 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX1__GI_THRESH3_EN___S 8 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX1__GI_THRESH2_EN___M 0x000000FF +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX1__GI_THRESH2_EN___S 0 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX1___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC40_IX1___S 0 + +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX0 (0x00A8C594) +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX0___POR 0x000000FF +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX0__GI_THRESH1_EN___POR 0x00 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX0__ED_THRESH3_EN___POR 0x00 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX0__ED_THRESH2_EN___POR 0x00 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX0__ED_THRESH1_EN___POR 0xFF +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX0__GI_THRESH1_EN___M 0xFF000000 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX0__GI_THRESH1_EN___S 24 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX0__ED_THRESH3_EN___M 0x00FF0000 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX0__ED_THRESH3_EN___S 16 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX0__ED_THRESH2_EN___M 0x0000FF00 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX0__ED_THRESH2_EN___S 8 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX0__ED_THRESH1_EN___M 0x000000FF +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX0__ED_THRESH1_EN___S 0 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX0___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX0___S 0 + +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX1 (0x00A8C598) +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX1___POR 0x00000000 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX1__GI_THRESH3_EN___POR 0x00 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX1__GI_THRESH2_EN___POR 0x00 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX1__GI_THRESH3_EN___M 0x0000FF00 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX1__GI_THRESH3_EN___S 8 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX1__GI_THRESH2_EN___M 0x000000FF +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX1__GI_THRESH2_EN___S 0 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX1___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_SEC80_IX1___S 0 + +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_VECTOR_IX0 (0x00A8C59C) +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_VECTOR_IX0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_VECTOR_IX0___POR 0x000000FF +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_VECTOR_IX0__ED_THRESH3_EN___POR 0x00 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_VECTOR_IX0__ED_THRESH2_EN___POR 0x00 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_VECTOR_IX0__ED_THRESH1_EN___POR 0xFF +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_VECTOR_IX0__ED_THRESH3_EN___M 0x00FF0000 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_VECTOR_IX0__ED_THRESH3_EN___S 16 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_VECTOR_IX0__ED_THRESH2_EN___M 0x0000FF00 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_VECTOR_IX0__ED_THRESH2_EN___S 8 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_VECTOR_IX0__ED_THRESH1_EN___M 0x000000FF +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_VECTOR_IX0__ED_THRESH1_EN___S 0 +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_VECTOR_IX0___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_CCA_RX_CLEAR_VECTOR_IX0___S 0 + +#define WMAC0_RXPCU_R0_HE_MISC_CFG (0x00A8C5A0) +#define WMAC0_RXPCU_R0_HE_MISC_CFG___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_HE_MISC_CFG___POR 0x00000100 +#define WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_UMRS_CONTROL___POR 0x1 +#define WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_BQRP___POR 0x0 +#define WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_GCR_MUBAR___POR 0x0 +#define WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_BSRP___POR 0x0 +#define WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_MURTS___POR 0x0 +#define WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_MUBAR___POR 0x0 +#define WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_BRPOLL___POR 0x0 +#define WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_BASIC___POR 0x0 +#define WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_UMRS_CONTROL___M 0x00000100 +#define WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_UMRS_CONTROL___S 8 +#define WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_BQRP___M 0x00000040 +#define WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_BQRP___S 6 +#define WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_GCR_MUBAR___M 0x00000020 +#define WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_GCR_MUBAR___S 5 +#define WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_BSRP___M 0x00000010 +#define WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_BSRP___S 4 +#define WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_MURTS___M 0x00000008 +#define WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_MURTS___S 3 +#define WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_MUBAR___M 0x00000004 +#define WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_MUBAR___S 2 +#define WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_BRPOLL___M 0x00000002 +#define WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_BRPOLL___S 1 +#define WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_BASIC___M 0x00000001 +#define WMAC0_RXPCU_R0_HE_MISC_CFG__DISABLE_TRIGGER_BASIC___S 0 +#define WMAC0_RXPCU_R0_HE_MISC_CFG___M 0x0000017F +#define WMAC0_RXPCU_R0_HE_MISC_CFG___S 0 + +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1 (0x00A8C5A4) +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1___POR 0xAC5A0010 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1__EOCW_MAX___POR 0x5 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1__EOCW_MIN___POR 0x3 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1__EOCW___POR 0x0 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1__OCW_RAND___POR 0x5A +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1__OCW_USED___POR 0x00 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1__BSSID_IDX___POR 0x1 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1__RANDOM_RU___POR 0x0 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1__UORA_UNASSOC___POR 0x0 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1__OCW_RAND_EN___POR 0x0 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1__OBO_EN___POR 0x0 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1__EOCW_MAX___M 0xE0000000 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1__EOCW_MAX___S 29 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1__EOCW_MIN___M 0x1C000000 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1__EOCW_MIN___S 26 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1__EOCW___M 0x03800000 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1__EOCW___S 23 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1__OCW_RAND___M 0x007F0000 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1__OCW_RAND___S 16 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1__OCW_USED___M 0x00007F00 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1__OCW_USED___S 8 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1__BSSID_IDX___M 0x00000070 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1__BSSID_IDX___S 4 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1__RANDOM_RU___M 0x00000008 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1__RANDOM_RU___S 3 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1__UORA_UNASSOC___M 0x00000004 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1__UORA_UNASSOC___S 2 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1__OCW_RAND_EN___M 0x00000002 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1__OCW_RAND_EN___S 1 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1__OBO_EN___M 0x00000001 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1__OBO_EN___S 0 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1___M 0xFFFF7F7F +#define WMAC0_RXPCU_R0_TFD_OBO_CFG1___S 0 + +#define WMAC0_RXPCU_R0_TFD_OBO_CNT1 (0x00A8C5A8) +#define WMAC0_RXPCU_R0_TFD_OBO_CNT1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_TFD_OBO_CNT1___POR 0x00000000 +#define WMAC0_RXPCU_R0_TFD_OBO_CNT1__OBO_ACTIVATED___POR 0x0 +#define WMAC0_RXPCU_R0_TFD_OBO_CNT1__WC_WAS_SENT___POR 0x0 +#define WMAC0_RXPCU_R0_TFD_OBO_CNT1__TB_FRAME_CNT___POR 0x00 +#define WMAC0_RXPCU_R0_TFD_OBO_CNT1__OBO_VALUE___POR 0x00 +#define WMAC0_RXPCU_R0_TFD_OBO_CNT1__OBO_ACTIVATED___M 0x80000000 +#define WMAC0_RXPCU_R0_TFD_OBO_CNT1__OBO_ACTIVATED___S 31 +#define WMAC0_RXPCU_R0_TFD_OBO_CNT1__WC_WAS_SENT___M 0x00010000 +#define WMAC0_RXPCU_R0_TFD_OBO_CNT1__WC_WAS_SENT___S 16 +#define WMAC0_RXPCU_R0_TFD_OBO_CNT1__TB_FRAME_CNT___M 0x0000FF00 +#define WMAC0_RXPCU_R0_TFD_OBO_CNT1__TB_FRAME_CNT___S 8 +#define WMAC0_RXPCU_R0_TFD_OBO_CNT1__OBO_VALUE___M 0x000000FF +#define WMAC0_RXPCU_R0_TFD_OBO_CNT1__OBO_VALUE___S 0 +#define WMAC0_RXPCU_R0_TFD_OBO_CNT1___M 0x8001FFFF +#define WMAC0_RXPCU_R0_TFD_OBO_CNT1___S 0 + +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2 (0x00A8C5AC) +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2___POR 0xAC5A0010 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2__EOCW_MAX___POR 0x5 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2__EOCW_MIN___POR 0x3 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2__EOCW___POR 0x0 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2__OCW_RAND___POR 0x5A +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2__OCW_USED___POR 0x00 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2__BSSID_IDX___POR 0x1 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2__RANDOM_RU___POR 0x0 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2__UORA_UNASSOC___POR 0x0 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2__OCW_RAND_EN___POR 0x0 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2__OBO_EN___POR 0x0 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2__EOCW_MAX___M 0xE0000000 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2__EOCW_MAX___S 29 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2__EOCW_MIN___M 0x1C000000 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2__EOCW_MIN___S 26 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2__EOCW___M 0x03800000 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2__EOCW___S 23 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2__OCW_RAND___M 0x007F0000 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2__OCW_RAND___S 16 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2__OCW_USED___M 0x00007F00 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2__OCW_USED___S 8 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2__BSSID_IDX___M 0x00000070 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2__BSSID_IDX___S 4 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2__RANDOM_RU___M 0x00000008 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2__RANDOM_RU___S 3 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2__UORA_UNASSOC___M 0x00000004 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2__UORA_UNASSOC___S 2 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2__OCW_RAND_EN___M 0x00000002 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2__OCW_RAND_EN___S 1 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2__OBO_EN___M 0x00000001 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2__OBO_EN___S 0 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2___M 0xFFFF7F7F +#define WMAC0_RXPCU_R0_TFD_OBO_CFG2___S 0 + +#define WMAC0_RXPCU_R0_TFD_OBO_CFG3 (0x00A8C5B0) +#define WMAC0_RXPCU_R0_TFD_OBO_CFG3___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_TFD_OBO_CFG3___POR 0x00000000 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG3__TICK_LFSR_EVERY_CLK_EN___POR 0x0 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG3__RU2_RAND_SEL_USED___POR 0x00 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG3__RU1_RAND_SEL_USED___POR 0x00 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG3__SIMPLIFIED_RAND_EN___POR 0x0 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG3__TICK_LFSR_EVERY_CLK_EN___M 0x00008000 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG3__TICK_LFSR_EVERY_CLK_EN___S 15 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG3__RU2_RAND_SEL_USED___M 0x00007F00 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG3__RU2_RAND_SEL_USED___S 8 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG3__RU1_RAND_SEL_USED___M 0x000000FE +#define WMAC0_RXPCU_R0_TFD_OBO_CFG3__RU1_RAND_SEL_USED___S 1 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG3__SIMPLIFIED_RAND_EN___M 0x00000001 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG3__SIMPLIFIED_RAND_EN___S 0 +#define WMAC0_RXPCU_R0_TFD_OBO_CFG3___M 0x0000FFFF +#define WMAC0_RXPCU_R0_TFD_OBO_CFG3___S 0 + +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1 (0x00A8C5B4) +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1___POR 0x00000000 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND1_FOR_OCW_127___POR 0x00 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_63___POR 0x00 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_31___POR 0x00 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_15___POR 0x0 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_7___POR 0x0 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_3___POR 0x0 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_1___POR 0x0 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__ENABLE_FULL_FW_RAND___POR 0x0 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND1_FOR_OCW_127___M 0x1FC00000 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND1_FOR_OCW_127___S 22 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_63___M 0x003F0000 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_63___S 16 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_31___M 0x0000F800 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_31___S 11 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_15___M 0x00000780 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_15___S 7 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_7___M 0x00000070 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_7___S 4 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_3___M 0x0000000C +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_3___S 2 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_1___M 0x00000002 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__OBO_RAND_FOR_OCW_1___S 1 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__ENABLE_FULL_FW_RAND___M 0x00000001 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1__ENABLE_FULL_FW_RAND___S 0 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1___M 0x1FFFFFFF +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_1___S 0 + +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_2 (0x00A8C5B8) +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_2___POR 0x00000000 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_2__OBO_RAND5_FOR_OCW_127___POR 0x00 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_2__OBO_RAND4_FOR_OCW_127___POR 0x00 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_2__OBO_RAND3_FOR_OCW_127___POR 0x00 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_2__OBO_RAND2_FOR_OCW_127___POR 0x00 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_2__OBO_RAND5_FOR_OCW_127___M 0x0FE00000 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_2__OBO_RAND5_FOR_OCW_127___S 21 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_2__OBO_RAND4_FOR_OCW_127___M 0x001FC000 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_2__OBO_RAND4_FOR_OCW_127___S 14 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_2__OBO_RAND3_FOR_OCW_127___M 0x00003F80 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_2__OBO_RAND3_FOR_OCW_127___S 7 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_2__OBO_RAND2_FOR_OCW_127___M 0x0000007F +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_2__OBO_RAND2_FOR_OCW_127___S 0 +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_2___M 0x0FFFFFFF +#define WMAC0_RXPCU_R0_TFD_OBO1_FW_RAND_2___S 0 + +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1 (0x00A8C5BC) +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1___POR 0x00000000 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND1_FOR_OCW_127___POR 0x00 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_63___POR 0x00 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_31___POR 0x00 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_15___POR 0x0 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_7___POR 0x0 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_3___POR 0x0 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_1___POR 0x0 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__ENABLE_FULL_FW_RAND___POR 0x0 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND1_FOR_OCW_127___M 0x1FC00000 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND1_FOR_OCW_127___S 22 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_63___M 0x003F0000 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_63___S 16 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_31___M 0x0000F800 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_31___S 11 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_15___M 0x00000780 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_15___S 7 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_7___M 0x00000070 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_7___S 4 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_3___M 0x0000000C +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_3___S 2 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_1___M 0x00000002 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__OBO_RAND_FOR_OCW_1___S 1 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__ENABLE_FULL_FW_RAND___M 0x00000001 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1__ENABLE_FULL_FW_RAND___S 0 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1___M 0x1FFFFFFF +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_1___S 0 + +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_2 (0x00A8C5C0) +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_2___POR 0x00000000 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_2__OBO_RAND5_FOR_OCW_127___POR 0x00 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_2__OBO_RAND4_FOR_OCW_127___POR 0x00 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_2__OBO_RAND3_FOR_OCW_127___POR 0x00 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_2__OBO_RAND2_FOR_OCW_127___POR 0x00 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_2__OBO_RAND5_FOR_OCW_127___M 0x0FE00000 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_2__OBO_RAND5_FOR_OCW_127___S 21 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_2__OBO_RAND4_FOR_OCW_127___M 0x001FC000 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_2__OBO_RAND4_FOR_OCW_127___S 14 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_2__OBO_RAND3_FOR_OCW_127___M 0x00003F80 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_2__OBO_RAND3_FOR_OCW_127___S 7 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_2__OBO_RAND2_FOR_OCW_127___M 0x0000007F +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_2__OBO_RAND2_FOR_OCW_127___S 0 +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_2___M 0x0FFFFFFF +#define WMAC0_RXPCU_R0_TFD_OBO2_FW_RAND_2___S 0 + +#define WMAC0_RXPCU_R0_TFD_OBO_CNT2 (0x00A8C5C4) +#define WMAC0_RXPCU_R0_TFD_OBO_CNT2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_TFD_OBO_CNT2___POR 0x00000000 +#define WMAC0_RXPCU_R0_TFD_OBO_CNT2__OBO_ACTIVATED___POR 0x0 +#define WMAC0_RXPCU_R0_TFD_OBO_CNT2__WC_WAS_SENT___POR 0x0 +#define WMAC0_RXPCU_R0_TFD_OBO_CNT2__TB_FRAME_CNT___POR 0x00 +#define WMAC0_RXPCU_R0_TFD_OBO_CNT2__OBO_VALUE___POR 0x00 +#define WMAC0_RXPCU_R0_TFD_OBO_CNT2__OBO_ACTIVATED___M 0x80000000 +#define WMAC0_RXPCU_R0_TFD_OBO_CNT2__OBO_ACTIVATED___S 31 +#define WMAC0_RXPCU_R0_TFD_OBO_CNT2__WC_WAS_SENT___M 0x00010000 +#define WMAC0_RXPCU_R0_TFD_OBO_CNT2__WC_WAS_SENT___S 16 +#define WMAC0_RXPCU_R0_TFD_OBO_CNT2__TB_FRAME_CNT___M 0x0000FF00 +#define WMAC0_RXPCU_R0_TFD_OBO_CNT2__TB_FRAME_CNT___S 8 +#define WMAC0_RXPCU_R0_TFD_OBO_CNT2__OBO_VALUE___M 0x000000FF +#define WMAC0_RXPCU_R0_TFD_OBO_CNT2__OBO_VALUE___S 0 +#define WMAC0_RXPCU_R0_TFD_OBO_CNT2___M 0x8001FFFF +#define WMAC0_RXPCU_R0_TFD_OBO_CNT2___S 0 + +#define WMAC0_RXPCU_R0_UNASSOC_BSSID_L32 (0x00A8C5C8) +#define WMAC0_RXPCU_R0_UNASSOC_BSSID_L32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_UNASSOC_BSSID_L32___POR 0x00000000 +#define WMAC0_RXPCU_R0_UNASSOC_BSSID_L32__ADDR___POR 0x00000000 +#define WMAC0_RXPCU_R0_UNASSOC_BSSID_L32__ADDR___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_UNASSOC_BSSID_L32__ADDR___S 0 +#define WMAC0_RXPCU_R0_UNASSOC_BSSID_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_UNASSOC_BSSID_L32___S 0 + +#define WMAC0_RXPCU_R0_UNASSOC_BSSID_U16 (0x00A8C5CC) +#define WMAC0_RXPCU_R0_UNASSOC_BSSID_U16___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_UNASSOC_BSSID_U16___POR 0x00000000 +#define WMAC0_RXPCU_R0_UNASSOC_BSSID_U16__ADDR___POR 0x0000 +#define WMAC0_RXPCU_R0_UNASSOC_BSSID_U16__ADDR___M 0x0000FFFF +#define WMAC0_RXPCU_R0_UNASSOC_BSSID_U16__ADDR___S 0 +#define WMAC0_RXPCU_R0_UNASSOC_BSSID_U16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_UNASSOC_BSSID_U16___S 0 + +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_1 (0x00A8C5D0) +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_1___POR 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_1__ELIGIBILITY_26_TONE_RU_IN_PRI_80_31_0___POR 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_1__ELIGIBILITY_26_TONE_RU_IN_PRI_80_31_0___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_1__ELIGIBILITY_26_TONE_RU_IN_PRI_80_31_0___S 0 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_1___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_1___S 0 + +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2 (0x00A8C5D4) +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2___POR 0xFFFFFFF8 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__ELIGIBILITY_26_TONE_RU_IN_PRI_80_36_32___POR 0x1F +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__ELIGIBILITY_52_TONE_RU_IN_PRI_80___POR 0xFFFF +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__ELIGIBILITY_106_TONE_RU_IN_PRI_80___POR 0xFF +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__DISABLE_26_TONE_RU___POR 0x0 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__DISABLE_52_TONE_RU___POR 0x0 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__DISABLE_106_TONE_RU___POR 0x0 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__ELIGIBILITY_26_TONE_RU_IN_PRI_80_36_32___M 0xF8000000 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__ELIGIBILITY_26_TONE_RU_IN_PRI_80_36_32___S 27 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__ELIGIBILITY_52_TONE_RU_IN_PRI_80___M 0x07FFF800 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__ELIGIBILITY_52_TONE_RU_IN_PRI_80___S 11 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__ELIGIBILITY_106_TONE_RU_IN_PRI_80___M 0x000007F8 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__ELIGIBILITY_106_TONE_RU_IN_PRI_80___S 3 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__DISABLE_26_TONE_RU___M 0x00000004 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__DISABLE_26_TONE_RU___S 2 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__DISABLE_52_TONE_RU___M 0x00000002 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__DISABLE_52_TONE_RU___S 1 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__DISABLE_106_TONE_RU___M 0x00000001 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2__DISABLE_106_TONE_RU___S 0 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_2___S 0 + +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3 (0x00A8C5D8) +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3___POR 0xFF3FFFFF +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__RU_9_8_ELIGIBILITY_IN_PRI_40___POR 0x3 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__RU_41_40_ELIGIBILITY_IN_PRI_40___POR 0x3 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__RU_55_54_ELIGIBILITY_IN_PRI_40___POR 0x3 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__RU_62_61_ELIGIBILITY_IN_PRI_40___POR 0x3 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__PRI_40_IS_UPPER_40___POR 0x0 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__PRI_20_IS_UPPER_20___POR 0x0 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__ELIGIBILITY_FOR_ILLEGAL_RU___POR 0x1 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__ELIGIBILITY_PER_20MHZ_IN_SEC80___POR 0xF +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__UL_STBC_SUPPORTED___POR 0x1 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__DOPPLER_SUPPORTED___POR 0x1 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__MAX_LTFS___POR 0x7 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__UL_LDPC_SUPPORTED___POR 0x1 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__MAX_MCS___POR 0xF +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__MAX_TARGET_RSSI___POR 0x7F +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__RU_9_8_ELIGIBILITY_IN_PRI_40___M 0xC0000000 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__RU_9_8_ELIGIBILITY_IN_PRI_40___S 30 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__RU_41_40_ELIGIBILITY_IN_PRI_40___M 0x30000000 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__RU_41_40_ELIGIBILITY_IN_PRI_40___S 28 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__RU_55_54_ELIGIBILITY_IN_PRI_40___M 0x0C000000 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__RU_55_54_ELIGIBILITY_IN_PRI_40___S 26 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__RU_62_61_ELIGIBILITY_IN_PRI_40___M 0x03000000 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__RU_62_61_ELIGIBILITY_IN_PRI_40___S 24 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__PRI_40_IS_UPPER_40___M 0x00800000 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__PRI_40_IS_UPPER_40___S 23 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__PRI_20_IS_UPPER_20___M 0x00400000 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__PRI_20_IS_UPPER_20___S 22 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__ELIGIBILITY_FOR_ILLEGAL_RU___M 0x00200000 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__ELIGIBILITY_FOR_ILLEGAL_RU___S 21 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__ELIGIBILITY_PER_20MHZ_IN_SEC80___M 0x001E0000 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__ELIGIBILITY_PER_20MHZ_IN_SEC80___S 17 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__UL_STBC_SUPPORTED___M 0x00010000 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__UL_STBC_SUPPORTED___S 16 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__DOPPLER_SUPPORTED___M 0x00008000 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__DOPPLER_SUPPORTED___S 15 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__MAX_LTFS___M 0x00007000 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__MAX_LTFS___S 12 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__UL_LDPC_SUPPORTED___M 0x00000800 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__UL_LDPC_SUPPORTED___S 11 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__MAX_MCS___M 0x00000780 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__MAX_MCS___S 7 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__MAX_TARGET_RSSI___M 0x0000007F +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3__MAX_TARGET_RSSI___S 0 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_3___S 0 + +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4 (0x00A8C5DC) +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4___POR 0xFFF00000 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__UL_DCM_SUPPORTED___POR 0x1 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__MAX_BW___POR 0x3 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__ELIGIBILITY_242_TONE_RU_IN_PRI_80___POR 0xF +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__ELIGIBILITY_484_TONE_RU_IN_PRI_80___POR 0x3 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__ELIGIBILITY_996_TONE_RU_IN_PRI_80___POR 0x1 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__ELIGIBILITY_2X996_TONE___POR 0x1 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__DISABLE_ELIGIBILITY_CHECK___POR 0x1 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__UL_DCM_SUPPORTED___M 0x80000000 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__UL_DCM_SUPPORTED___S 31 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__MAX_BW___M 0x60000000 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__MAX_BW___S 29 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__ELIGIBILITY_242_TONE_RU_IN_PRI_80___M 0x1E000000 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__ELIGIBILITY_242_TONE_RU_IN_PRI_80___S 25 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__ELIGIBILITY_484_TONE_RU_IN_PRI_80___M 0x01800000 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__ELIGIBILITY_484_TONE_RU_IN_PRI_80___S 23 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__ELIGIBILITY_996_TONE_RU_IN_PRI_80___M 0x00400000 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__ELIGIBILITY_996_TONE_RU_IN_PRI_80___S 22 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__ELIGIBILITY_2X996_TONE___M 0x00200000 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__ELIGIBILITY_2X996_TONE___S 21 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__DISABLE_ELIGIBILITY_CHECK___M 0x00100000 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4__DISABLE_ELIGIBILITY_CHECK___S 20 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4___M 0xFFF00000 +#define WMAC0_RXPCU_R0_RA_RU_ELIGIBILTY_4___S 20 + +#define WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL (0x00A8C5E0) +#define WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL___POR 0x0008C410 +#define WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL__PER_USER_PRIMARY_INFO_SIZE___POR 0x4 +#define WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL__PER_USER_INFO_START_BYTE_OFFSET___POR 0x1 +#define WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL__PER_USER_INFO_OFFSET___POR 0x11 +#define WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL__FORMAT_TYPE_BIT_OFFSET___POR 0x00 +#define WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL__FORMAT_TYPE_OFFSET___POR 0x10 +#define WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL__PER_USER_PRIMARY_INFO_SIZE___M 0x001E0000 +#define WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL__PER_USER_PRIMARY_INFO_SIZE___S 17 +#define WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL__PER_USER_INFO_START_BYTE_OFFSET___M 0x00018000 +#define WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL__PER_USER_INFO_START_BYTE_OFFSET___S 15 +#define WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL__PER_USER_INFO_OFFSET___M 0x00007C00 +#define WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL__PER_USER_INFO_OFFSET___S 10 +#define WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL__FORMAT_TYPE_BIT_OFFSET___M 0x000003E0 +#define WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL__FORMAT_TYPE_BIT_OFFSET___S 5 +#define WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL__FORMAT_TYPE_OFFSET___M 0x0000001F +#define WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL__FORMAT_TYPE_OFFSET___S 0 +#define WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL___M 0x001FFFFF +#define WMAC0_RXPCU_R0_NDPA_HE_FORMAT_CTRL___S 0 + +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0 (0x00A8C5E4) +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0___POR 0x025203A0 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_1_EN___POR 0x1 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_1_LENGTH___POR 0x05 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_1_ID___POR 0x2 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_0_EN___POR 0x1 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_0_LENGTH___POR 0x1A +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_0_ID___POR 0x0 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_1_EN___M 0x02000000 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_1_EN___S 25 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_1_LENGTH___M 0x01F00000 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_1_LENGTH___S 20 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_1_ID___M 0x000F0000 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_1_ID___S 16 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_0_EN___M 0x00000200 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_0_EN___S 9 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_0_LENGTH___M 0x000001F0 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_0_LENGTH___S 4 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_0_ID___M 0x0000000F +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0__ELEM_0_ID___S 0 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0___M 0x03FF03FF +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_0___S 0 + +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1 (0x00A8C5E8) +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1___POR 0x025203A0 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_3_EN___POR 0x1 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_3_LENGTH___POR 0x05 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_3_ID___POR 0x2 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_2_EN___POR 0x1 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_2_LENGTH___POR 0x1A +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_2_ID___POR 0x0 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_3_EN___M 0x02000000 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_3_EN___S 25 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_3_LENGTH___M 0x01F00000 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_3_LENGTH___S 20 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_3_ID___M 0x000F0000 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_3_ID___S 16 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_2_EN___M 0x00000200 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_2_EN___S 9 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_2_LENGTH___M 0x000001F0 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_2_LENGTH___S 4 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_2_ID___M 0x0000000F +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1__ELEM_2_ID___S 0 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1___M 0x03FF03FF +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_1___S 0 + +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2 (0x00A8C5EC) +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2___POR 0x00050004 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_5_EN___POR 0x0 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_5_LENGTH___POR 0x00 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_5_ID___POR 0x5 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_4_EN___POR 0x0 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_4_LENGTH___POR 0x00 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_4_ID___POR 0x4 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_5_EN___M 0x02000000 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_5_EN___S 25 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_5_LENGTH___M 0x01F00000 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_5_LENGTH___S 20 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_5_ID___M 0x000F0000 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_5_ID___S 16 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_4_EN___M 0x00000200 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_4_EN___S 9 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_4_LENGTH___M 0x000001F0 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_4_LENGTH___S 4 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_4_ID___M 0x0000000F +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2__ELEM_4_ID___S 0 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2___M 0x03FF03FF +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_2___S 0 + +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3 (0x00A8C5F0) +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3___POR 0x00070006 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_7_EN___POR 0x0 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_7_LENGTH___POR 0x00 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_7_ID___POR 0x7 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_6_EN___POR 0x0 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_6_LENGTH___POR 0x00 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_6_ID___POR 0x6 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_7_EN___M 0x02000000 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_7_EN___S 25 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_7_LENGTH___M 0x01F00000 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_7_LENGTH___S 20 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_7_ID___M 0x000F0000 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_7_ID___S 16 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_6_EN___M 0x00000200 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_6_EN___S 9 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_6_LENGTH___M 0x000001F0 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_6_LENGTH___S 4 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_6_ID___M 0x0000000F +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3__ELEM_6_ID___S 0 +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3___M 0x03FF03FF +#define WMAC0_RXPCU_R0_HEC_DEC_CTRL_IX_3___S 0 + +#define WMAC0_RXPCU_R0_MACRX_ABORT_REQUEST_CTRL (0x00A8C5F4) +#define WMAC0_RXPCU_R0_MACRX_ABORT_REQUEST_CTRL___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_MACRX_ABORT_REQUEST_CTRL___POR 0x00000000 +#define WMAC0_RXPCU_R0_MACRX_ABORT_REQUEST_CTRL__SEND___POR 0x0 +#define WMAC0_RXPCU_R0_MACRX_ABORT_REQUEST_CTRL__ABORT_REASON___POR 0x00 +#define WMAC0_RXPCU_R0_MACRX_ABORT_REQUEST_CTRL__SEND___M 0x00000100 +#define WMAC0_RXPCU_R0_MACRX_ABORT_REQUEST_CTRL__SEND___S 8 +#define WMAC0_RXPCU_R0_MACRX_ABORT_REQUEST_CTRL__ABORT_REASON___M 0x000000FF +#define WMAC0_RXPCU_R0_MACRX_ABORT_REQUEST_CTRL__ABORT_REASON___S 0 +#define WMAC0_RXPCU_R0_MACRX_ABORT_REQUEST_CTRL___M 0x000001FF +#define WMAC0_RXPCU_R0_MACRX_ABORT_REQUEST_CTRL___S 0 + +#define WMAC0_RXPCU_R0_MACRX_ABORT_REQUST_AND_ACK_STATUS (0x00A8C5F8) +#define WMAC0_RXPCU_R0_MACRX_ABORT_REQUST_AND_ACK_STATUS___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_MACRX_ABORT_REQUST_AND_ACK_STATUS___POR 0x00000000 +#define WMAC0_RXPCU_R0_MACRX_ABORT_REQUST_AND_ACK_STATUS__ACK_RCVD___POR 0x0 +#define WMAC0_RXPCU_R0_MACRX_ABORT_REQUST_AND_ACK_STATUS__REQUEST_GENERATED___POR 0x0 +#define WMAC0_RXPCU_R0_MACRX_ABORT_REQUST_AND_ACK_STATUS__ACK_RCVD___M 0x00000002 +#define WMAC0_RXPCU_R0_MACRX_ABORT_REQUST_AND_ACK_STATUS__ACK_RCVD___S 1 +#define WMAC0_RXPCU_R0_MACRX_ABORT_REQUST_AND_ACK_STATUS__REQUEST_GENERATED___M 0x00000001 +#define WMAC0_RXPCU_R0_MACRX_ABORT_REQUST_AND_ACK_STATUS__REQUEST_GENERATED___S 0 +#define WMAC0_RXPCU_R0_MACRX_ABORT_REQUST_AND_ACK_STATUS___M 0x00000003 +#define WMAC0_RXPCU_R0_MACRX_ABORT_REQUST_AND_ACK_STATUS___S 0 + +#define WMAC0_RXPCU_R0_MACRX_CBF_READ_REQUST_AND_ACK_STATUS (0x00A8C5FC) +#define WMAC0_RXPCU_R0_MACRX_CBF_READ_REQUST_AND_ACK_STATUS___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_MACRX_CBF_READ_REQUST_AND_ACK_STATUS___POR 0x00000000 +#define WMAC0_RXPCU_R0_MACRX_CBF_READ_REQUST_AND_ACK_STATUS__ACK_RCVD___POR 0x0 +#define WMAC0_RXPCU_R0_MACRX_CBF_READ_REQUST_AND_ACK_STATUS__REQUEST_GENERATED___POR 0x0 +#define WMAC0_RXPCU_R0_MACRX_CBF_READ_REQUST_AND_ACK_STATUS__ACK_RCVD___M 0x00000002 +#define WMAC0_RXPCU_R0_MACRX_CBF_READ_REQUST_AND_ACK_STATUS__ACK_RCVD___S 1 +#define WMAC0_RXPCU_R0_MACRX_CBF_READ_REQUST_AND_ACK_STATUS__REQUEST_GENERATED___M 0x00000001 +#define WMAC0_RXPCU_R0_MACRX_CBF_READ_REQUST_AND_ACK_STATUS__REQUEST_GENERATED___S 0 +#define WMAC0_RXPCU_R0_MACRX_CBF_READ_REQUST_AND_ACK_STATUS___M 0x00000003 +#define WMAC0_RXPCU_R0_MACRX_CBF_READ_REQUST_AND_ACK_STATUS___S 0 + +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM (0x00A8C600) +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM___POR 0x10000000 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM__STA_RESP_BA_TBSSID___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM__UCAST_MBA___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM__BAR_REMAP___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM__BIG_ENDIAN___POR 0x1 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM__AP_ENABLE___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM__BSSID_IDX___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM__MAX_NUM___POR 0x000 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM__BID___POR 0x000 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM__ENABLE___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM__STA_RESP_BA_TBSSID___M 0x80000000 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM__STA_RESP_BA_TBSSID___S 31 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM__UCAST_MBA___M 0x40000000 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM__UCAST_MBA___S 30 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM__BAR_REMAP___M 0x20000000 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM__BAR_REMAP___S 29 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM__BIG_ENDIAN___M 0x10000000 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM__BIG_ENDIAN___S 28 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM__AP_ENABLE___M 0x08000000 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM__AP_ENABLE___S 27 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM__BSSID_IDX___M 0x07000000 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM__BSSID_IDX___S 24 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM__MAX_NUM___M 0x007FF000 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM__MAX_NUM___S 12 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM__BID___M 0x00000FFE +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM__BID___S 1 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM__ENABLE___M 0x00000001 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM__ENABLE___S 0 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM___M 0xFF7FFFFF +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM___S 0 + +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM2 (0x00A8C604) +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM2___POR 0x00000001 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM2__WAKEUP_COUNT_CHECK_EN_FOR_NON_TX_BSSID_DTIM___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM2__WAKEUPS_PER_DTIM_CHECK___POR 0x001 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM2__WAKEUP_COUNT_CHECK_EN_FOR_NON_TX_BSSID_DTIM___M 0x00010000 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM2__WAKEUP_COUNT_CHECK_EN_FOR_NON_TX_BSSID_DTIM___S 16 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM2__WAKEUPS_PER_DTIM_CHECK___M 0x000001FF +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM2__WAKEUPS_PER_DTIM_CHECK___S 0 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM2___M 0x000101FF +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM2___S 0 + +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM3 (0x00A8C608) +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM3___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM3___POR 0x00000001 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM3__WAKEUP_COUNT___POR 0x001 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM3__WAKEUP_COUNT___M 0x000001FF +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM3__WAKEUP_COUNT___S 0 +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM3___M 0x000001FF +#define WMAC0_RXPCU_R0_RFF_MBSSID_TIM3___S 0 + +#define WMAC0_RXPCU_R0_MBSSID_MASK (0x00A8C60C) +#define WMAC0_RXPCU_R0_MBSSID_MASK___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_MBSSID_MASK___POR 0x000003FF +#define WMAC0_RXPCU_R0_MBSSID_MASK__VALUE___POR 0x3FF +#define WMAC0_RXPCU_R0_MBSSID_MASK__VALUE___M 0x000003FF +#define WMAC0_RXPCU_R0_MBSSID_MASK__VALUE___S 0 +#define WMAC0_RXPCU_R0_MBSSID_MASK___M 0x000003FF +#define WMAC0_RXPCU_R0_MBSSID_MASK___S 0 + +#define WMAC0_RXPCU_R0_RFF_RX_FILTER3 (0x00A8C610) +#define WMAC0_RXPCU_R0_RFF_RX_FILTER3___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RFF_RX_FILTER3___POR 0x00000000 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER3__MUBAR_UL_TRIGGER_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER3__MBSSID_TIM_PACKET___POR 0x0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER3__MUBAR_UL_TRIGGER_EN___M 0x00000002 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER3__MUBAR_UL_TRIGGER_EN___S 1 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER3__MBSSID_TIM_PACKET___M 0x00000001 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER3__MBSSID_TIM_PACKET___S 0 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER3___M 0x00000003 +#define WMAC0_RXPCU_R0_RFF_RX_FILTER3___S 0 + +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL (0x00A8C614) +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL___POR 0x0717EE6A +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__OOO_PHYABORTACK_END_DIS___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__EXPECT_CTS_TQM_DUMMY_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TQM_ACKED_MPDU_DUMMY_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__RXPCU_USER0_SETUP_DUMMY_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TQM_ACKED_MPDU_USER0_TID0_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TQM_ACKED_MPDU_ORDER_DIS___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__CHK_RECEIVED_RESP_EN___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__BABU_FCS_AST_PARSER_EN___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__BABU_FCS_PARSER_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__BA_TID_CONS_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__EN_UNEXPECTED_BA_OR_ACK___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__EN_ALL_ACK_MBA___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__CLEAR_USER_BABU_MEET___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__CLEAR_USER_EXT_BABU_MEET___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__DISABLE_PM_BA_ACK_CTS_EN___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__FRAMELESS_BAR_TLV_EN___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__PPDU_COME_PEER_ENTRY_CHK_EN___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__PROXYSTA_FILTER_AST_GET_EN___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__BAR_MTID_ENABLE___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__DISABLE_AST_NOT_FOUND_RESP_IN_ALL_ULMU___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__DISABLE_AST_NOT_FOUND_RESP_ULMU___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__DISABLE_ASSOC_REQ_RESP_ULMU___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TLV_COMPRESSED_CHK_DIS___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TQM_ACKED_MPDU_RSEVD_3A_TID_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TSU_ARB_ROUND_EN___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__PFU_PREFETCH_ALL_PTE_EN___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__BITMAP_PREFETCH_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__EXPECT_RESP_SKIP___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__CLR_SW_PEER_ID_A1_MISMATCH_PROXYSTA___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__MBA_UNASSO_ACK_EN___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__MTID_SMPDU_ACK_DIS___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__OOO_PHYABORTACK_END_DIS___M 0x80000000 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__OOO_PHYABORTACK_END_DIS___S 31 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__EXPECT_CTS_TQM_DUMMY_EN___M 0x40000000 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__EXPECT_CTS_TQM_DUMMY_EN___S 30 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TQM_ACKED_MPDU_DUMMY_EN___M 0x20000000 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TQM_ACKED_MPDU_DUMMY_EN___S 29 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__RXPCU_USER0_SETUP_DUMMY_EN___M 0x10000000 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__RXPCU_USER0_SETUP_DUMMY_EN___S 28 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TQM_ACKED_MPDU_USER0_TID0_EN___M 0x08000000 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TQM_ACKED_MPDU_USER0_TID0_EN___S 27 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TQM_ACKED_MPDU_ORDER_DIS___M 0x04000000 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TQM_ACKED_MPDU_ORDER_DIS___S 26 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__CHK_RECEIVED_RESP_EN___M 0x02000000 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__CHK_RECEIVED_RESP_EN___S 25 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__BABU_FCS_AST_PARSER_EN___M 0x01000000 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__BABU_FCS_AST_PARSER_EN___S 24 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__BABU_FCS_PARSER_EN___M 0x00800000 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__BABU_FCS_PARSER_EN___S 23 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__BA_TID_CONS_EN___M 0x00200000 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__BA_TID_CONS_EN___S 21 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__EN_UNEXPECTED_BA_OR_ACK___M 0x00100000 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__EN_UNEXPECTED_BA_OR_ACK___S 20 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__EN_ALL_ACK_MBA___M 0x00080000 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__EN_ALL_ACK_MBA___S 19 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__CLEAR_USER_BABU_MEET___M 0x00040000 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__CLEAR_USER_BABU_MEET___S 18 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__CLEAR_USER_EXT_BABU_MEET___M 0x00020000 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__CLEAR_USER_EXT_BABU_MEET___S 17 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__DISABLE_PM_BA_ACK_CTS_EN___M 0x00010000 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__DISABLE_PM_BA_ACK_CTS_EN___S 16 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__FRAMELESS_BAR_TLV_EN___M 0x00008000 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__FRAMELESS_BAR_TLV_EN___S 15 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__PPDU_COME_PEER_ENTRY_CHK_EN___M 0x00004000 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__PPDU_COME_PEER_ENTRY_CHK_EN___S 14 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__PROXYSTA_FILTER_AST_GET_EN___M 0x00002000 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__PROXYSTA_FILTER_AST_GET_EN___S 13 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__BAR_MTID_ENABLE___M 0x00001000 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__BAR_MTID_ENABLE___S 12 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__DISABLE_AST_NOT_FOUND_RESP_IN_ALL_ULMU___M 0x00000800 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__DISABLE_AST_NOT_FOUND_RESP_IN_ALL_ULMU___S 11 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__DISABLE_AST_NOT_FOUND_RESP_ULMU___M 0x00000400 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__DISABLE_AST_NOT_FOUND_RESP_ULMU___S 10 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__DISABLE_ASSOC_REQ_RESP_ULMU___M 0x00000200 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__DISABLE_ASSOC_REQ_RESP_ULMU___S 9 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TLV_COMPRESSED_CHK_DIS___M 0x00000100 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TLV_COMPRESSED_CHK_DIS___S 8 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TQM_ACKED_MPDU_RSEVD_3A_TID_EN___M 0x00000080 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TQM_ACKED_MPDU_RSEVD_3A_TID_EN___S 7 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TSU_ARB_ROUND_EN___M 0x00000040 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__TSU_ARB_ROUND_EN___S 6 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__PFU_PREFETCH_ALL_PTE_EN___M 0x00000020 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__PFU_PREFETCH_ALL_PTE_EN___S 5 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__BITMAP_PREFETCH_EN___M 0x00000010 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__BITMAP_PREFETCH_EN___S 4 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__EXPECT_RESP_SKIP___M 0x00000008 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__EXPECT_RESP_SKIP___S 3 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__CLR_SW_PEER_ID_A1_MISMATCH_PROXYSTA___M 0x00000004 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__CLR_SW_PEER_ID_A1_MISMATCH_PROXYSTA___S 2 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__MBA_UNASSO_ACK_EN___M 0x00000002 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__MBA_UNASSO_ACK_EN___S 1 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__MTID_SMPDU_ACK_DIS___M 0x00000001 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL__MTID_SMPDU_ACK_DIS___S 0 +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL___M 0xFFBFFFFF +#define WMAC0_RXPCU_R0_RX_MTID_AMPDU_OPT_CTRL___S 0 + +#define WMAC0_RXPCU_R0_BABU_OCCUPIED_INT_INFO (0x00A8C618) +#define WMAC0_RXPCU_R0_BABU_OCCUPIED_INT_INFO___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_BABU_OCCUPIED_INT_INFO___POR 0x00000000 +#define WMAC0_RXPCU_R0_BABU_OCCUPIED_INT_INFO__TIME_STAMP___POR 0x00 +#define WMAC0_RXPCU_R0_BABU_OCCUPIED_INT_INFO__REWRITE_ENTRY___POR 0x00 +#define WMAC0_RXPCU_R0_BABU_OCCUPIED_INT_INFO__ORIG_BA_USER___POR 0x00 +#define WMAC0_RXPCU_R0_BABU_OCCUPIED_INT_INFO__COMING_BA_USER___POR 0x00 +#define WMAC0_RXPCU_R0_BABU_OCCUPIED_INT_INFO__TIME_STAMP___M 0xFF000000 +#define WMAC0_RXPCU_R0_BABU_OCCUPIED_INT_INFO__TIME_STAMP___S 24 +#define WMAC0_RXPCU_R0_BABU_OCCUPIED_INT_INFO__REWRITE_ENTRY___M 0x00FF0000 +#define WMAC0_RXPCU_R0_BABU_OCCUPIED_INT_INFO__REWRITE_ENTRY___S 16 +#define WMAC0_RXPCU_R0_BABU_OCCUPIED_INT_INFO__ORIG_BA_USER___M 0x0000FF00 +#define WMAC0_RXPCU_R0_BABU_OCCUPIED_INT_INFO__ORIG_BA_USER___S 8 +#define WMAC0_RXPCU_R0_BABU_OCCUPIED_INT_INFO__COMING_BA_USER___M 0x000000FF +#define WMAC0_RXPCU_R0_BABU_OCCUPIED_INT_INFO__COMING_BA_USER___S 0 +#define WMAC0_RXPCU_R0_BABU_OCCUPIED_INT_INFO___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_BABU_OCCUPIED_INT_INFO___S 0 + +#define WMAC0_RXPCU_R0_BABU_LOST_INT_INFO (0x00A8C61C) +#define WMAC0_RXPCU_R0_BABU_LOST_INT_INFO___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_BABU_LOST_INT_INFO___POR 0x00000000 +#define WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__TIME_STAMP___POR 0x00 +#define WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__RXPCU_SETUP_COMPLETE_SEQ_ERR___POR 0x0 +#define WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__RTI_READY_DEASSERT_HAPPEN___POR 0x0 +#define WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__BABU_OCCUPIED_INT___POR 0x0 +#define WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__LOST_BA_TID_INT___POR 0x0 +#define WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__LOST_BA_TID___POR 0x0 +#define WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__LOST_BA_USER___POR 0x00 +#define WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__TIME_STAMP___M 0xFF000000 +#define WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__TIME_STAMP___S 24 +#define WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__RXPCU_SETUP_COMPLETE_SEQ_ERR___M 0x00008000 +#define WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__RXPCU_SETUP_COMPLETE_SEQ_ERR___S 15 +#define WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__RTI_READY_DEASSERT_HAPPEN___M 0x00004000 +#define WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__RTI_READY_DEASSERT_HAPPEN___S 14 +#define WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__BABU_OCCUPIED_INT___M 0x00002000 +#define WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__BABU_OCCUPIED_INT___S 13 +#define WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__LOST_BA_TID_INT___M 0x00001000 +#define WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__LOST_BA_TID_INT___S 12 +#define WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__LOST_BA_TID___M 0x00000F00 +#define WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__LOST_BA_TID___S 8 +#define WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__LOST_BA_USER___M 0x000000FF +#define WMAC0_RXPCU_R0_BABU_LOST_INT_INFO__LOST_BA_USER___S 0 +#define WMAC0_RXPCU_R0_BABU_LOST_INT_INFO___M 0xFF00FFFF +#define WMAC0_RXPCU_R0_BABU_LOST_INT_INFO___S 0 + +#define WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO (0x00A8C620) +#define WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO___POR 0x00000000 +#define WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__TIME_STAMP___POR 0x00 +#define WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__RXPCU_USER_SETUP_RECOME___POR 0x0 +#define WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__USER_SETUP_EXT_LOST___POR 0x0 +#define WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__USER_SETUP_EXT_DUP___POR 0x0 +#define WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__USER_SETUP_DUP___POR 0x0 +#define WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__USER_SETUP_EXT_NO_SETUP___POR 0x0 +#define WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__LOST_TID_VALID___POR 0x0 +#define WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__LOST_TID___POR 0x0 +#define WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__LOST_USER___POR 0x00 +#define WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__TIME_STAMP___M 0xFF000000 +#define WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__TIME_STAMP___S 24 +#define WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__RXPCU_USER_SETUP_RECOME___M 0x00020000 +#define WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__RXPCU_USER_SETUP_RECOME___S 17 +#define WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__USER_SETUP_EXT_LOST___M 0x00010000 +#define WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__USER_SETUP_EXT_LOST___S 16 +#define WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__USER_SETUP_EXT_DUP___M 0x00008000 +#define WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__USER_SETUP_EXT_DUP___S 15 +#define WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__USER_SETUP_DUP___M 0x00004000 +#define WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__USER_SETUP_DUP___S 14 +#define WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__USER_SETUP_EXT_NO_SETUP___M 0x00002000 +#define WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__USER_SETUP_EXT_NO_SETUP___S 13 +#define WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__LOST_TID_VALID___M 0x00001000 +#define WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__LOST_TID_VALID___S 12 +#define WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__LOST_TID___M 0x00000F00 +#define WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__LOST_TID___S 8 +#define WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__LOST_USER___M 0x000000FF +#define WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO__LOST_USER___S 0 +#define WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO___M 0xFF03FFFF +#define WMAC0_RXPCU_R0_USER_SETUP_EXT_LOST_INT_INFO___S 0 + +#define WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO0 (0x00A8C624) +#define WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO0___POR 0x00000000 +#define WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO0__ADDR_H16___POR 0x0000 +#define WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO0__MPDU_ID___POR 0x0 +#define WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO0__PPDU_ID___POR 0x0 +#define WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO0__AST_REQ_USER___POR 0x00 +#define WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO0__ADDR_H16___M 0xFFFF0000 +#define WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO0__ADDR_H16___S 16 +#define WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO0__MPDU_ID___M 0x0000F000 +#define WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO0__MPDU_ID___S 12 +#define WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO0__PPDU_ID___M 0x00000F00 +#define WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO0__PPDU_ID___S 8 +#define WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO0__AST_REQ_USER___M 0x000000FF +#define WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO0__AST_REQ_USER___S 0 +#define WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO0___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO0___S 0 + +#define WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO1 (0x00A8C628) +#define WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO1___POR 0x00000000 +#define WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO1__ADDR_L32___POR 0x00000000 +#define WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO1__ADDR_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO1__ADDR_L32___S 0 +#define WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO1___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_AST_REQ_OVERFLOW_INT_INFO1___S 0 + +#define WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO0 (0x00A8C62C) +#define WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO0___POR 0x00000000 +#define WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO0__ADDR_H16___POR 0x0000 +#define WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO0__MPDU_ID___POR 0x0 +#define WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO0__PPDU_ID___POR 0x0 +#define WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO0__AST_REQ_USER___POR 0x00 +#define WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO0__ADDR_H16___M 0xFFFF0000 +#define WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO0__ADDR_H16___S 16 +#define WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO0__MPDU_ID___M 0x0000F000 +#define WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO0__MPDU_ID___S 12 +#define WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO0__PPDU_ID___M 0x00000F00 +#define WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO0__PPDU_ID___S 8 +#define WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO0__AST_REQ_USER___M 0x000000FF +#define WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO0__AST_REQ_USER___S 0 +#define WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO0___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO0___S 0 + +#define WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO1 (0x00A8C630) +#define WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO1___POR 0x00000000 +#define WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO1__ADDR_L32___POR 0x00000000 +#define WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO1__ADDR_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO1__ADDR_L32___S 0 +#define WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO1___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_AST_PRESEARCH_NOT_FIND_INT_INFO1___S 0 + +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG (0x00A8C634) +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG___POR 0x00100000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__SW_FLUSH_CNT_FORCE___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__PHYRX_ABORT_ACK_TO_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__RXPCU_FSM_BUSY_FLUSH_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DATADONE_PKTEND_FLUSH_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DATA_FLUSH_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__PLCP_HEADER_FLUSH_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__IDLE_FLUSH_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__TLV_TRUN_CNT_FORCE___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MACRX_ABORT_ACK_TO_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MACRX_ABORT_ACK_TLV_MASK_EN___POR 0x1 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__RX_FRAME_DEASSERT_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DATADONE_PKTEND_TRUN_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DATA_TRUN_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__PLCP_HEADER_TRUN_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__ERR_INJ_ERR_TYPE___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__OTHER_ERR_INJ_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__PADDING_ERR_INJ_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MPDU_ERR_INJ_CRC32_OK_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MPDU_CRC_ERR_INJ_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MPDU_PAYLOAD_ERR_INJ_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MPDU_HEADER_ERR_INJ_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DELIM_ERR_INJ_CRC8_OK_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DELIM_CRC_ERR_INJ_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DELIM_SIG_ERR_INJ_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DELIM_LEN_ERR_INJ_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DELIM_EOF_ERR_INJ_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__SERVICE_ERR_INJ_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__AMPI_ERR_SEL___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__SW_FLUSH_CNT_FORCE___M 0x40000000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__SW_FLUSH_CNT_FORCE___S 30 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__PHYRX_ABORT_ACK_TO_EN___M 0x20000000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__PHYRX_ABORT_ACK_TO_EN___S 29 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__RXPCU_FSM_BUSY_FLUSH_EN___M 0x10000000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__RXPCU_FSM_BUSY_FLUSH_EN___S 28 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DATADONE_PKTEND_FLUSH_EN___M 0x08000000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DATADONE_PKTEND_FLUSH_EN___S 27 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DATA_FLUSH_EN___M 0x04000000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DATA_FLUSH_EN___S 26 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__PLCP_HEADER_FLUSH_EN___M 0x02000000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__PLCP_HEADER_FLUSH_EN___S 25 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__IDLE_FLUSH_EN___M 0x01000000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__IDLE_FLUSH_EN___S 24 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__TLV_TRUN_CNT_FORCE___M 0x00400000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__TLV_TRUN_CNT_FORCE___S 22 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MACRX_ABORT_ACK_TO_EN___M 0x00200000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MACRX_ABORT_ACK_TO_EN___S 21 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MACRX_ABORT_ACK_TLV_MASK_EN___M 0x00100000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MACRX_ABORT_ACK_TLV_MASK_EN___S 20 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__RX_FRAME_DEASSERT_EN___M 0x00080000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__RX_FRAME_DEASSERT_EN___S 19 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DATADONE_PKTEND_TRUN_EN___M 0x00040000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DATADONE_PKTEND_TRUN_EN___S 18 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DATA_TRUN_EN___M 0x00020000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DATA_TRUN_EN___S 17 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__PLCP_HEADER_TRUN_EN___M 0x00010000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__PLCP_HEADER_TRUN_EN___S 16 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__ERR_INJ_ERR_TYPE___M 0x00006000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__ERR_INJ_ERR_TYPE___S 13 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__OTHER_ERR_INJ_EN___M 0x00001000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__OTHER_ERR_INJ_EN___S 12 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__PADDING_ERR_INJ_EN___M 0x00000800 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__PADDING_ERR_INJ_EN___S 11 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MPDU_ERR_INJ_CRC32_OK_EN___M 0x00000400 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MPDU_ERR_INJ_CRC32_OK_EN___S 10 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MPDU_CRC_ERR_INJ_EN___M 0x00000200 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MPDU_CRC_ERR_INJ_EN___S 9 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MPDU_PAYLOAD_ERR_INJ_EN___M 0x00000100 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MPDU_PAYLOAD_ERR_INJ_EN___S 8 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MPDU_HEADER_ERR_INJ_EN___M 0x00000080 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__MPDU_HEADER_ERR_INJ_EN___S 7 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DELIM_ERR_INJ_CRC8_OK_EN___M 0x00000040 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DELIM_ERR_INJ_CRC8_OK_EN___S 6 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DELIM_CRC_ERR_INJ_EN___M 0x00000020 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DELIM_CRC_ERR_INJ_EN___S 5 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DELIM_SIG_ERR_INJ_EN___M 0x00000010 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DELIM_SIG_ERR_INJ_EN___S 4 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DELIM_LEN_ERR_INJ_EN___M 0x00000008 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DELIM_LEN_ERR_INJ_EN___S 3 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DELIM_EOF_ERR_INJ_EN___M 0x00000004 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__DELIM_EOF_ERR_INJ_EN___S 2 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__SERVICE_ERR_INJ_EN___M 0x00000002 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__SERVICE_ERR_INJ_EN___S 1 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__AMPI_ERR_SEL___M 0x00000001 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG__AMPI_ERR_SEL___S 0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG___M 0x7F7F7FFF +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG___S 0 + +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1 (0x00A8C638) +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1___POR 0x00000000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1__ERR_INJ_COUNT___POR 0x0000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1__ERR_INJ_COUNT_SEL___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1__ERR_INJ_VALUE_INIT_FORCE___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1__ERR_INJ_BASE_COMPARE_FORCE___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1__ERR_INJ_CONTENT_FORCE_CFG___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1__ERR_INJ_COUNT___M 0xFFFF0000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1__ERR_INJ_COUNT___S 16 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1__ERR_INJ_COUNT_SEL___M 0x00000F00 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1__ERR_INJ_COUNT_SEL___S 8 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1__ERR_INJ_VALUE_INIT_FORCE___M 0x00000030 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1__ERR_INJ_VALUE_INIT_FORCE___S 4 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1__ERR_INJ_BASE_COMPARE_FORCE___M 0x0000000C +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1__ERR_INJ_BASE_COMPARE_FORCE___S 2 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1__ERR_INJ_CONTENT_FORCE_CFG___M 0x00000003 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1__ERR_INJ_CONTENT_FORCE_CFG___S 0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1___M 0xFFFF0F3F +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_CFG1___S 0 + +#define WMAC0_RXPCU_R0_PPDU_DATA_ERR_INJ (0x00A8C63C) +#define WMAC0_RXPCU_R0_PPDU_DATA_ERR_INJ___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_PPDU_DATA_ERR_INJ___POR 0x5A5A5A5A +#define WMAC0_RXPCU_R0_PPDU_DATA_ERR_INJ__DATA_ERR_RANDOM1___POR 0x5A5A5A5A +#define WMAC0_RXPCU_R0_PPDU_DATA_ERR_INJ__DATA_ERR_RANDOM1___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PPDU_DATA_ERR_INJ__DATA_ERR_RANDOM1___S 0 +#define WMAC0_RXPCU_R0_PPDU_DATA_ERR_INJ___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PPDU_DATA_ERR_INJ___S 0 + +#define WMAC0_RXPCU_R0_PPDU_DATA_VALUE (0x00A8C640) +#define WMAC0_RXPCU_R0_PPDU_DATA_VALUE___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_PPDU_DATA_VALUE___POR 0xC3C3C3C3 +#define WMAC0_RXPCU_R0_PPDU_DATA_VALUE__DATA_VALUE_RANDOM2___POR 0xC3C3C3C3 +#define WMAC0_RXPCU_R0_PPDU_DATA_VALUE__DATA_VALUE_RANDOM2___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PPDU_DATA_VALUE__DATA_VALUE_RANDOM2___S 0 +#define WMAC0_RXPCU_R0_PPDU_DATA_VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PPDU_DATA_VALUE___S 0 + +#define WMAC0_RXPCU_R0_PPDU_DATA_BASE (0x00A8C644) +#define WMAC0_RXPCU_R0_PPDU_DATA_BASE___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_PPDU_DATA_BASE___POR 0xA5A5A5A5 +#define WMAC0_RXPCU_R0_PPDU_DATA_BASE__BASE_VALUE_RANDOM3___POR 0xA5A5A5A5 +#define WMAC0_RXPCU_R0_PPDU_DATA_BASE__BASE_VALUE_RANDOM3___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PPDU_DATA_BASE__BASE_VALUE_RANDOM3___S 0 +#define WMAC0_RXPCU_R0_PPDU_DATA_BASE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PPDU_DATA_BASE___S 0 + +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE (0x00A8C648) +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE___POR 0x00400102 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__CLKGAT_DISABLE_TLV_TRUNCATION___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__CLKGAT_DISABLE_SW_FLUSH___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__CLKGAT_DISABLE_CONTENT_ERR_LFSR___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__CLKGAT_DISABLE_CONTENT_ERR___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__MPDU_MH_LENGHT___POR 0x40 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__DELIM_CORRECT_RANGE___POR 0x1 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__MPDU_CRC_CORRECT_RANGE___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__NORMAL_RANGE___POR 0x2 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__CLKGAT_DISABLE_TLV_TRUNCATION___M 0x08000000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__CLKGAT_DISABLE_TLV_TRUNCATION___S 27 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__CLKGAT_DISABLE_SW_FLUSH___M 0x04000000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__CLKGAT_DISABLE_SW_FLUSH___S 26 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__CLKGAT_DISABLE_CONTENT_ERR_LFSR___M 0x02000000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__CLKGAT_DISABLE_CONTENT_ERR_LFSR___S 25 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__CLKGAT_DISABLE_CONTENT_ERR___M 0x01000000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__CLKGAT_DISABLE_CONTENT_ERR___S 24 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__MPDU_MH_LENGHT___M 0x007F0000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__MPDU_MH_LENGHT___S 16 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__DELIM_CORRECT_RANGE___M 0x00000F00 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__DELIM_CORRECT_RANGE___S 8 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__MPDU_CRC_CORRECT_RANGE___M 0x000000F0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__MPDU_CRC_CORRECT_RANGE___S 4 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__NORMAL_RANGE___M 0x0000000F +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE__NORMAL_RANGE___S 0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE___M 0x0F7F0FFF +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_RANGE___S 0 + +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK (0x00A8C64C) +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK___POR 0x00000000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK__TRC_EVENT_MASK_CRYPTO_TLV_WR___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK__TRC_EVENT_MASK_SFM_READ___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK__TRC_EVENT_MASK_PCU_START___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK__TRC_EVENT_MASK_BRU___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK__ERR_INJ_TRC_EVENT_MASK___POR 0x00 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK__TRC_EVENT_MASK_CRYPTO_TLV_WR___M 0x00000800 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK__TRC_EVENT_MASK_CRYPTO_TLV_WR___S 11 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK__TRC_EVENT_MASK_SFM_READ___M 0x00000400 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK__TRC_EVENT_MASK_SFM_READ___S 10 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK__TRC_EVENT_MASK_PCU_START___M 0x00000200 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK__TRC_EVENT_MASK_PCU_START___S 9 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK__TRC_EVENT_MASK_BRU___M 0x00000100 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK__TRC_EVENT_MASK_BRU___S 8 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK__ERR_INJ_TRC_EVENT_MASK___M 0x000000FF +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK__ERR_INJ_TRC_EVENT_MASK___S 0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK___M 0x00000FFF +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_DBG_MASK___S 0 + +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CNT (0x00A8C650) +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CNT___POR 0x002F0000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CNT__MPDU_STEPWISE_END_CNT___POR 0x002F +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CNT__MPDU_STEPWISE_START_CNT___POR 0x0000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CNT__MPDU_STEPWISE_END_CNT___M 0xFFFF0000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CNT__MPDU_STEPWISE_END_CNT___S 16 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CNT__MPDU_STEPWISE_START_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CNT__MPDU_STEPWISE_START_CNT___S 0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CNT___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CNT___S 0 + +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CFG (0x00A8C654) +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CFG___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CFG___POR 0x00000000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CFG__MPDU_STEPWISE_ERR_INTERVAL___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CFG__MPDU_STEPWISE_INFO_USER_SEL___POR 0x00 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CFG__MPDU_STEPWISE_MODE___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CFG__MPDU_STEPWISE_ERR_INJ_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CFG__MPDU_STEPWISE_ERR_INTERVAL___M 0x0F000000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CFG__MPDU_STEPWISE_ERR_INTERVAL___S 24 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CFG__MPDU_STEPWISE_INFO_USER_SEL___M 0x00FF0000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CFG__MPDU_STEPWISE_INFO_USER_SEL___S 16 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CFG__MPDU_STEPWISE_MODE___M 0x00000300 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CFG__MPDU_STEPWISE_MODE___S 8 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CFG__MPDU_STEPWISE_ERR_INJ_EN___M 0x00000001 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CFG__MPDU_STEPWISE_ERR_INJ_EN___S 0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CFG___M 0x0FFF0301 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_CFG___S 0 + +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_INFO (0x00A8C658) +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_INFO___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_INFO___POR 0x00000000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_INFO__MPDU_STEPWISE_CORRUPT_ROUND_NUM___POR 0x0000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_INFO__MPDU_STEPWISE_CORRUPT_BYTE_NUM___POR 0x0000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_INFO__MPDU_STEPWISE_CORRUPT_ROUND_NUM___M 0xFFFF0000 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_INFO__MPDU_STEPWISE_CORRUPT_ROUND_NUM___S 16 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_INFO__MPDU_STEPWISE_CORRUPT_BYTE_NUM___M 0x0000FFFF +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_INFO__MPDU_STEPWISE_CORRUPT_BYTE_NUM___S 0 +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_INFO___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RX_ERR_INJECTION_STEPWISE_INFO___S 0 + +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0 (0x00A8C65C) +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0___POR 0x00000000 +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_RX_ABORT_TOGGLE___POR 0x0 +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_RX_ABORT_REQ___POR 0x0 +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_FLUSH_TOGGLE___POR 0x0 +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_FLUSH_REQ___POR 0x0 +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_RX_ABORT_EN___POR 0x0 +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_EN___POR 0x0 +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_START_CNT___POR 0x000000 +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_RX_ABORT_TOGGLE___M 0x20000000 +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_RX_ABORT_TOGGLE___S 29 +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_RX_ABORT_REQ___M 0x10000000 +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_RX_ABORT_REQ___S 28 +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_FLUSH_TOGGLE___M 0x08000000 +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_FLUSH_TOGGLE___S 27 +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_FLUSH_REQ___M 0x04000000 +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_FLUSH_REQ___S 26 +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_RX_ABORT_EN___M 0x02000000 +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_RX_ABORT_EN___S 25 +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_EN___M 0x01000000 +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_EN___S 24 +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_START_CNT___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0__SW_FLUSH_STEPWISE_START_CNT___S 0 +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0___M 0x3FFFFFFF +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG0___S 0 + +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG1 (0x00A8C660) +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG1___POR 0x00000000 +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG1__SW_FLUSH_STEPWISE_END_CNT___POR 0x000000 +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG1__SW_FLUSH_STEPWISE_END_CNT___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG1__SW_FLUSH_STEPWISE_END_CNT___S 0 +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG1___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_CFG1___S 0 + +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_INFO0 (0x00A8C664) +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_INFO0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_INFO0___POR 0x00000000 +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_INFO0__SW_FLUSH_STEPWISE_TLV_NUM___POR 0x000000 +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_INFO0__SW_FLUSH_STEPWISE_TLV_NUM___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_INFO0__SW_FLUSH_STEPWISE_TLV_NUM___S 0 +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_INFO0___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_INFO0___S 0 + +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_INFO1 (0x00A8C668) +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_INFO1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_INFO1___POR 0x00000000 +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_INFO1__SW_FLUSH_STEPWISE_ROUND_NUM___POR 0x0000 +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_INFO1__SW_FLUSH_STEPWISE_ROUND_NUM___M 0x0000FFFF +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_INFO1__SW_FLUSH_STEPWISE_ROUND_NUM___S 0 +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_INFO1___M 0x0000FFFF +#define WMAC0_RXPCU_R0_SW_FLUSH_STEPWISE_INFO1___S 0 + +#define WMAC0_RXPCU_R0_SW_PHY_TLV_TRUNCATION (0x00A8C66C) +#define WMAC0_RXPCU_R0_SW_PHY_TLV_TRUNCATION___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SW_PHY_TLV_TRUNCATION___POR 0x00000000 +#define WMAC0_RXPCU_R0_SW_PHY_TLV_TRUNCATION__SW_PHY_MACRX_ABORT_ACK___POR 0x0 +#define WMAC0_RXPCU_R0_SW_PHY_TLV_TRUNCATION__SW_PHY_TLV_WAIT_TLV_NOT_IDLE___POR 0x0 +#define WMAC0_RXPCU_R0_SW_PHY_TLV_TRUNCATION__SW_PHY_TLV_TRUNCATION_REQ___POR 0x0 +#define WMAC0_RXPCU_R0_SW_PHY_TLV_TRUNCATION__SW_PHY_MACRX_ABORT_ACK___M 0x00000004 +#define WMAC0_RXPCU_R0_SW_PHY_TLV_TRUNCATION__SW_PHY_MACRX_ABORT_ACK___S 2 +#define WMAC0_RXPCU_R0_SW_PHY_TLV_TRUNCATION__SW_PHY_TLV_WAIT_TLV_NOT_IDLE___M 0x00000002 +#define WMAC0_RXPCU_R0_SW_PHY_TLV_TRUNCATION__SW_PHY_TLV_WAIT_TLV_NOT_IDLE___S 1 +#define WMAC0_RXPCU_R0_SW_PHY_TLV_TRUNCATION__SW_PHY_TLV_TRUNCATION_REQ___M 0x00000001 +#define WMAC0_RXPCU_R0_SW_PHY_TLV_TRUNCATION__SW_PHY_TLV_TRUNCATION_REQ___S 0 +#define WMAC0_RXPCU_R0_SW_PHY_TLV_TRUNCATION___M 0x00000007 +#define WMAC0_RXPCU_R0_SW_PHY_TLV_TRUNCATION___S 0 + +#define WMAC0_RXPCU_R0_SW_PHY_TLV_ABORT_REQ_DETAIL (0x00A8C670) +#define WMAC0_RXPCU_R0_SW_PHY_TLV_ABORT_REQ_DETAIL___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SW_PHY_TLV_ABORT_REQ_DETAIL___POR 0x00000000 +#define WMAC0_RXPCU_R0_SW_PHY_TLV_ABORT_REQ_DETAIL__SW_PHY_TLV_ABORT_REQ_DETAIL___POR 0x00000000 +#define WMAC0_RXPCU_R0_SW_PHY_TLV_ABORT_REQ_DETAIL__SW_PHY_TLV_ABORT_REQ_DETAIL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SW_PHY_TLV_ABORT_REQ_DETAIL__SW_PHY_TLV_ABORT_REQ_DETAIL___S 0 +#define WMAC0_RXPCU_R0_SW_PHY_TLV_ABORT_REQ_DETAIL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SW_PHY_TLV_ABORT_REQ_DETAIL___S 0 + +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0 (0x00A8C674) +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0___POR 0x00000000 +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0__RX_ABORT_STEPWISE_RX_ABORT_TOGGLE___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0__RX_ABORT_STEPWISE_RX_ABORT_REQ___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0__RX_ABORT_STEPWISE_MODE___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0__RX_ABORT_STEPWISE_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0__RX_ABORT_STEPWISE_START_CNT___POR 0x000000 +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0__RX_ABORT_STEPWISE_RX_ABORT_TOGGLE___M 0x08000000 +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0__RX_ABORT_STEPWISE_RX_ABORT_TOGGLE___S 27 +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0__RX_ABORT_STEPWISE_RX_ABORT_REQ___M 0x04000000 +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0__RX_ABORT_STEPWISE_RX_ABORT_REQ___S 26 +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0__RX_ABORT_STEPWISE_MODE___M 0x02000000 +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0__RX_ABORT_STEPWISE_MODE___S 25 +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0__RX_ABORT_STEPWISE_EN___M 0x01000000 +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0__RX_ABORT_STEPWISE_EN___S 24 +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0__RX_ABORT_STEPWISE_START_CNT___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0__RX_ABORT_STEPWISE_START_CNT___S 0 +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0___M 0x0FFFFFFF +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG0___S 0 + +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG1 (0x00A8C678) +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG1___POR 0x00000000 +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG1__RX_ABORT_STEPWISE_END_CNT___POR 0x000000 +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG1__RX_ABORT_STEPWISE_END_CNT___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG1__RX_ABORT_STEPWISE_END_CNT___S 0 +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG1___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_CFG1___S 0 + +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_INFO0 (0x00A8C67C) +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_INFO0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_INFO0___POR 0x00000000 +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_INFO0__RX_ABORT_STEPWISE_COUNT_NUM___POR 0x000000 +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_INFO0__RX_ABORT_STEPWISE_COUNT_NUM___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_INFO0__RX_ABORT_STEPWISE_COUNT_NUM___S 0 +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_INFO0___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_INFO0___S 0 + +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_INFO1 (0x00A8C680) +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_INFO1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_INFO1___POR 0x00000000 +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_INFO1__RX_ABORT_STEPWISE_ROUND_NUM___POR 0x0000 +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_INFO1__RX_ABORT_STEPWISE_ROUND_NUM___M 0x0000FFFF +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_INFO1__RX_ABORT_STEPWISE_ROUND_NUM___S 0 +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_INFO1___M 0x0000FFFF +#define WMAC0_RXPCU_R0_RX_ABORT_STEPWISE_INFO1___S 0 + +#define WMAC0_RXPCU_R0_RESPONSE_TLV_DELAY_CNT (0x00A8C684) +#define WMAC0_RXPCU_R0_RESPONSE_TLV_DELAY_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RESPONSE_TLV_DELAY_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R0_RESPONSE_TLV_DELAY_CNT__THRESH___POR 0x00 +#define WMAC0_RXPCU_R0_RESPONSE_TLV_DELAY_CNT__EN___POR 0x0 +#define WMAC0_RXPCU_R0_RESPONSE_TLV_DELAY_CNT__THRESH___M 0x0000FF00 +#define WMAC0_RXPCU_R0_RESPONSE_TLV_DELAY_CNT__THRESH___S 8 +#define WMAC0_RXPCU_R0_RESPONSE_TLV_DELAY_CNT__EN___M 0x00000001 +#define WMAC0_RXPCU_R0_RESPONSE_TLV_DELAY_CNT__EN___S 0 +#define WMAC0_RXPCU_R0_RESPONSE_TLV_DELAY_CNT___M 0x0000FF01 +#define WMAC0_RXPCU_R0_RESPONSE_TLV_DELAY_CNT___S 0 + +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0 (0x00A8C688) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0___POR 0x000000C1 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__TA_RA_TYPE_FILTER_SET_EN___POR 0x0000 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_AS_FP_TA_RA_TYPE___POR 0x0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_EN_ALL___POR 0x0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_EN_NDPA_NDP_ALL___POR 0x0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_EN_TA_RA_TYPE___POR 0x0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_EN_RTT5_FTM_ACK_ALL___POR 0x0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_EN_LEGACY_RTT_ACK___POR 0x1 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__UPDATE_BB_CAPTURED_CHANNEL_ONLY_FOR_RTT___POR 0x1 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__ALL_EN___POR 0x0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__NDPA_NDP_ALL_EN___POR 0x0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__NDPA_NDP_DIRECTED_EN___POR 0x0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__TA_RA_TYPE_FILTER_EN___POR 0x0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__RTT5_FTM_ACK_EN___POR 0x0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__LEGACY_RTT_FTM_TM_ACK_EN___POR 0x1 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__TA_RA_TYPE_FILTER_SET_EN___M 0xFFFF0000 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__TA_RA_TYPE_FILTER_SET_EN___S 16 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_AS_FP_TA_RA_TYPE___M 0x00001000 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_AS_FP_TA_RA_TYPE___S 12 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_EN_ALL___M 0x00000800 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_EN_ALL___S 11 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_EN_NDPA_NDP_ALL___M 0x00000400 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_EN_NDPA_NDP_ALL___S 10 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_EN_TA_RA_TYPE___M 0x00000200 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_EN_TA_RA_TYPE___S 9 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_EN_RTT5_FTM_ACK_ALL___M 0x00000100 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_EN_RTT5_FTM_ACK_ALL___S 8 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_EN_LEGACY_RTT_ACK___M 0x00000080 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__FILTER_IN_EN_LEGACY_RTT_ACK___S 7 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__UPDATE_BB_CAPTURED_CHANNEL_ONLY_FOR_RTT___M 0x00000040 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__UPDATE_BB_CAPTURED_CHANNEL_ONLY_FOR_RTT___S 6 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__ALL_EN___M 0x00000020 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__ALL_EN___S 5 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__NDPA_NDP_ALL_EN___M 0x00000010 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__NDPA_NDP_ALL_EN___S 4 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__NDPA_NDP_DIRECTED_EN___M 0x00000008 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__NDPA_NDP_DIRECTED_EN___S 3 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__TA_RA_TYPE_FILTER_EN___M 0x00000004 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__TA_RA_TYPE_FILTER_EN___S 2 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__RTT5_FTM_ACK_EN___M 0x00000002 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__RTT5_FTM_ACK_EN___S 1 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__LEGACY_RTT_FTM_TM_ACK_EN___M 0x00000001 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0__LEGACY_RTT_FTM_TM_ACK_EN___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0___M 0xFFFF1FFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_0___S 0 + +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_1 (0x00A8C68C) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_1___POR 0x00000000 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_1__CAPTURE_INTERVAL___POR 0x000000 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_1__CAPTURE_INTERVAL___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_1__CAPTURE_INTERVAL___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_1___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_1___S 0 + +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_2 (0x00A8C690) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_2___POR 0x00000000 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_2__UL_MU_USER_MASK_L32___POR 0x00000000 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_2__UL_MU_USER_MASK_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_2__UL_MU_USER_MASK_L32___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_2___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_2___S 0 + +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_3 (0x00A8C694) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_3___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_3___POR 0x00000000 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_3__MU_SUPPORT_IN_TLV___POR 0x0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_3__UL_MU_USER_MASK_U5___POR 0x00 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_3__MU_SUPPORT_IN_TLV___M 0x00000100 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_3__MU_SUPPORT_IN_TLV___S 8 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_3__UL_MU_USER_MASK_U5___M 0x0000001F +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_3__UL_MU_USER_MASK_U5___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_3___M 0x0000011F +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_3___S 0 + +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_4 (0x00A8C698) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_4___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_4___POR 0x00000000 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_4__CAPTURE_DURATION___POR 0x000000 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_4__CAPTURE_DURATION___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_4__CAPTURE_DURATION___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_4___M 0x00FFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_4___S 0 + +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_5 (0x00A8C69C) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_5___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_5___POR 0x00000000 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_5__FREEZE_TLV_DELAY_CNT_THRESH___POR 0x00 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_5__FREEZE_TLV_DELAY_CNT_EN___POR 0x0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_5__FREEZE_TLV_DELAY_CNT_THRESH___M 0x0000FF00 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_5__FREEZE_TLV_DELAY_CNT_THRESH___S 8 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_5__FREEZE_TLV_DELAY_CNT_EN___M 0x00000001 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_5__FREEZE_TLV_DELAY_CNT_EN___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_5___M 0x0000FF01 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_5___S 0 + +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_6 (0x00A8C6A0) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_6___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_6___POR 0x00000000 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_6__CAPTURE_INTERVAL_MODE_SEL___POR 0x0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_6__CAPTURE_COUNT___POR 0x0000 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_6__CAPTURE_INTERVAL_MODE_SEL___M 0x00010000 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_6__CAPTURE_INTERVAL_MODE_SEL___S 16 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_6__CAPTURE_COUNT___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_6__CAPTURE_COUNT___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_6___M 0x0001FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_CTRL_6___S 0 + +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_n(n) (0x00A8C6A4+0x4*(n)) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_n_nMIN 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_n_nMAX 3 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_n_ELEM 4 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_n___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_n___POR 0x00000000 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_n__EXPECT_TA_L_32___POR 0x00000000 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_n__EXPECT_TA_L_32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_n__EXPECT_TA_L_32___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_n___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_n___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_0 (0x00A8C6A4) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_0__EXPECT_TA_L_32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_0__EXPECT_TA_L_32___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_1 (0x00A8C6A8) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_1__EXPECT_TA_L_32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_1__EXPECT_TA_L_32___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_2 (0x00A8C6AC) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_2__EXPECT_TA_L_32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_2__EXPECT_TA_L_32___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_3 (0x00A8C6B0) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_3___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_3__EXPECT_TA_L_32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG0_GRP_3__EXPECT_TA_L_32___S 0 + +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_n(n) (0x00A8C6E4+0x4*(n)) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_n_nMIN 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_n_nMAX 3 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_n_ELEM 4 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_n___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_n___POR 0x00000000 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_n__EXPECT_TA_U_16___POR 0x0000 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_n__EXPECT_TA_U_16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_n__EXPECT_TA_U_16___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_n___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_n___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_0 (0x00A8C6E4) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_0__EXPECT_TA_U_16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_0__EXPECT_TA_U_16___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_1 (0x00A8C6E8) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_1__EXPECT_TA_U_16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_1__EXPECT_TA_U_16___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_2 (0x00A8C6EC) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_2__EXPECT_TA_U_16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_2__EXPECT_TA_U_16___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_3 (0x00A8C6F0) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_3___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_3__EXPECT_TA_U_16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG1_GRP_3__EXPECT_TA_U_16___S 0 + +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_n(n) (0x00A8C724+0x4*(n)) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_n_nMIN 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_n_nMAX 3 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_n_ELEM 4 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_n___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_n___POR 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_n__EXPECT_TA_MASK_L_32___POR 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_n__EXPECT_TA_MASK_L_32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_n__EXPECT_TA_MASK_L_32___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_n___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_n___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_0 (0x00A8C724) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_0__EXPECT_TA_MASK_L_32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_0__EXPECT_TA_MASK_L_32___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_1 (0x00A8C728) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_1__EXPECT_TA_MASK_L_32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_1__EXPECT_TA_MASK_L_32___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_2 (0x00A8C72C) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_2__EXPECT_TA_MASK_L_32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_2__EXPECT_TA_MASK_L_32___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_3 (0x00A8C730) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_3___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_3__EXPECT_TA_MASK_L_32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG2_GRP_3__EXPECT_TA_MASK_L_32___S 0 + +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_n(n) (0x00A8C764+0x4*(n)) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_n_nMIN 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_n_nMAX 3 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_n_ELEM 4 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_n___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_n___POR 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_n__EXPECT_TA_MASK_U_16___POR 0xFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_n__EXPECT_TA_MASK_U_16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_n__EXPECT_TA_MASK_U_16___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_n___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_n___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_0 (0x00A8C764) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_0__EXPECT_TA_MASK_U_16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_0__EXPECT_TA_MASK_U_16___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_1 (0x00A8C768) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_1__EXPECT_TA_MASK_U_16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_1__EXPECT_TA_MASK_U_16___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_2 (0x00A8C76C) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_2__EXPECT_TA_MASK_U_16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_2__EXPECT_TA_MASK_U_16___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_3 (0x00A8C770) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_3___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_3__EXPECT_TA_MASK_U_16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG3_GRP_3__EXPECT_TA_MASK_U_16___S 0 + +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_n(n) (0x00A8C7A4+0x4*(n)) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_n_nMIN 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_n_nMAX 3 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_n_ELEM 4 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_n___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_n___POR 0x00000000 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_n__EXPECT_RA_L_32___POR 0x00000000 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_n__EXPECT_RA_L_32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_n__EXPECT_RA_L_32___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_n___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_n___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_0 (0x00A8C7A4) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_0__EXPECT_RA_L_32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_0__EXPECT_RA_L_32___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_1 (0x00A8C7A8) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_1__EXPECT_RA_L_32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_1__EXPECT_RA_L_32___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_2 (0x00A8C7AC) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_2__EXPECT_RA_L_32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_2__EXPECT_RA_L_32___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_3 (0x00A8C7B0) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_3___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_3__EXPECT_RA_L_32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG4_GRP_3__EXPECT_RA_L_32___S 0 + +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_n(n) (0x00A8C7E4+0x4*(n)) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_n_nMIN 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_n_nMAX 3 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_n_ELEM 4 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_n___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_n___POR 0x00000000 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_n__EXPECT_RA_U_16___POR 0x0000 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_n__EXPECT_RA_U_16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_n__EXPECT_RA_U_16___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_n___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_n___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_0 (0x00A8C7E4) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_0__EXPECT_RA_U_16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_0__EXPECT_RA_U_16___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_1 (0x00A8C7E8) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_1__EXPECT_RA_U_16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_1__EXPECT_RA_U_16___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_2 (0x00A8C7EC) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_2__EXPECT_RA_U_16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_2__EXPECT_RA_U_16___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_3 (0x00A8C7F0) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_3___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_3__EXPECT_RA_U_16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG5_GRP_3__EXPECT_RA_U_16___S 0 + +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_n(n) (0x00A8C824+0x4*(n)) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_n_nMIN 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_n_nMAX 3 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_n_ELEM 4 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_n___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_n___POR 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_n__EXPECT_RA_MASK_L_32___POR 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_n__EXPECT_RA_MASK_L_32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_n__EXPECT_RA_MASK_L_32___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_n___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_n___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_0 (0x00A8C824) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_0__EXPECT_RA_MASK_L_32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_0__EXPECT_RA_MASK_L_32___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_1 (0x00A8C828) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_1__EXPECT_RA_MASK_L_32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_1__EXPECT_RA_MASK_L_32___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_2 (0x00A8C82C) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_2__EXPECT_RA_MASK_L_32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_2__EXPECT_RA_MASK_L_32___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_3 (0x00A8C830) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_3___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_3__EXPECT_RA_MASK_L_32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG6_GRP_3__EXPECT_RA_MASK_L_32___S 0 + +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_n(n) (0x00A8C864+0x4*(n)) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_n_nMIN 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_n_nMAX 3 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_n_ELEM 4 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_n___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_n___POR 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_n__EXPECT_RA_MASK_U_16___POR 0xFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_n__EXPECT_RA_MASK_U_16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_n__EXPECT_RA_MASK_U_16___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_n___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_n___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_0 (0x00A8C864) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_0__EXPECT_RA_MASK_U_16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_0__EXPECT_RA_MASK_U_16___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_1 (0x00A8C868) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_1__EXPECT_RA_MASK_U_16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_1__EXPECT_RA_MASK_U_16___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_2 (0x00A8C86C) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_2__EXPECT_RA_MASK_U_16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_2__EXPECT_RA_MASK_U_16___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_3 (0x00A8C870) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_3___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_3__EXPECT_RA_MASK_U_16___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG7_GRP_3__EXPECT_RA_MASK_U_16___S 0 + +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_n(n) (0x00A8C8A4+0x4*(n)) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_n_nMIN 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_n_nMAX 3 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_n_ELEM 4 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_n___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_n___POR 0x00000000 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_n__EXPECT_NSS___POR 0x00 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_n__EXPECT_BW___POR 0x0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_n__EXPECT_NSS___M 0x00000FF0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_n__EXPECT_NSS___S 4 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_n__EXPECT_BW___M 0x0000000F +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_n__EXPECT_BW___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_n___M 0x00000FFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_n___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_0 (0x00A8C8A4) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_0__EXPECT_NSS___M 0x00000FF0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_0__EXPECT_NSS___S 4 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_0__EXPECT_BW___M 0x0000000F +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_0__EXPECT_BW___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_1 (0x00A8C8A8) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_1__EXPECT_NSS___M 0x00000FF0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_1__EXPECT_NSS___S 4 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_1__EXPECT_BW___M 0x0000000F +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_1__EXPECT_BW___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_2 (0x00A8C8AC) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_2__EXPECT_NSS___M 0x00000FF0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_2__EXPECT_NSS___S 4 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_2__EXPECT_BW___M 0x0000000F +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_2__EXPECT_BW___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_3 (0x00A8C8B0) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_3___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_3__EXPECT_NSS___M 0x00000FF0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_3__EXPECT_NSS___S 4 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_3__EXPECT_BW___M 0x0000000F +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG8_GRP_3__EXPECT_BW___S 0 + +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_n(n) (0x00A8C8E4+0x4*(n)) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_n_nMIN 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_n_nMAX 3 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_n_ELEM 4 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_n___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_n___POR 0x00000000 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_n__EXPECT_CTRL_SUB_TYPE___POR 0x0000 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_n__EXPECT_MGMT_SUB_TYPE___POR 0x0000 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_n__EXPECT_CTRL_SUB_TYPE___M 0xFFFF0000 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_n__EXPECT_CTRL_SUB_TYPE___S 16 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_n__EXPECT_MGMT_SUB_TYPE___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_n__EXPECT_MGMT_SUB_TYPE___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_n___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_n___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_0 (0x00A8C8E4) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_0__EXPECT_CTRL_SUB_TYPE___M 0xFFFF0000 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_0__EXPECT_CTRL_SUB_TYPE___S 16 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_0__EXPECT_MGMT_SUB_TYPE___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_0__EXPECT_MGMT_SUB_TYPE___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_1 (0x00A8C8E8) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_1__EXPECT_CTRL_SUB_TYPE___M 0xFFFF0000 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_1__EXPECT_CTRL_SUB_TYPE___S 16 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_1__EXPECT_MGMT_SUB_TYPE___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_1__EXPECT_MGMT_SUB_TYPE___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_2 (0x00A8C8EC) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_2__EXPECT_CTRL_SUB_TYPE___M 0xFFFF0000 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_2__EXPECT_CTRL_SUB_TYPE___S 16 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_2__EXPECT_MGMT_SUB_TYPE___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_2__EXPECT_MGMT_SUB_TYPE___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_3 (0x00A8C8F0) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_3___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_3__EXPECT_CTRL_SUB_TYPE___M 0xFFFF0000 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_3__EXPECT_CTRL_SUB_TYPE___S 16 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_3__EXPECT_MGMT_SUB_TYPE___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG9_GRP_3__EXPECT_MGMT_SUB_TYPE___S 0 + +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_n(n) (0x00A8C924+0x4*(n)) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_n_nMIN 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_n_nMAX 3 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_n_ELEM 4 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_n___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_n___POR 0x00000000 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_n__EXPECT_DATA_SUB_TYPE___POR 0x0000 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_n__EXPECT_DATA_SUB_TYPE___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_n__EXPECT_DATA_SUB_TYPE___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_n___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_n___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_0 (0x00A8C924) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_0__EXPECT_DATA_SUB_TYPE___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_0__EXPECT_DATA_SUB_TYPE___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_1 (0x00A8C928) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_1__EXPECT_DATA_SUB_TYPE___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_1__EXPECT_DATA_SUB_TYPE___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_2 (0x00A8C92C) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_2__EXPECT_DATA_SUB_TYPE___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_2__EXPECT_DATA_SUB_TYPE___S 0 +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_3 (0x00A8C930) +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_3___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_3__EXPECT_DATA_SUB_TYPE___M 0x0000FFFF +#define WMAC0_RXPCU_R0_CHANNEL_CAPTURE_FILTER_CFG10_GRP_3__EXPECT_DATA_SUB_TYPE___S 0 + +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL (0x00A8C964) +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL___POR 0x78FC0C3C +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__SRP_HE_TB_ABORT___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__FORCE_ULMU_PPDU_END_USER_ST___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__UL_MU_RESP_ADDR_CHK___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__MUBAR_TRIG_FRAME_ONE_TIME___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__RXPCU_SETUP_CLEAR_EXT___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__SAME_USER_CLEAR_EXT___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__USER_INFO_WR_AFTER_ABORT_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__DATA_CHUNK_256B___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TSU_DIFF_USER_BURST___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TSU_USER_MIDD_BURST___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TSU_USER_GNT_BURST___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TSU_USER_START_BURST___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TSU_USER_WHOLE_BURST___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__BCN_TIMEOUT_CHECK_FCS_ABORT___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__AID_CTN_MATCH___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__PPDU_ACK_RPT_ADJ___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__PRE_SEARCH_PHASE_CLEAR_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__DISABLE_MONITOR_OTHER_DECRYPT___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__DISABLE_MONITOR_DIRECT_DECRYPT___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__RXPCU_TXPCU_TLV_READY_CHK_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__ULMU_BAR_RESP_CHK_EN___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__DROP_AST_NO_ACK_BRU_EN___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__MBSSID_IMPL_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TQM_ACKED_MPDU_USER___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__CLEAR_INBSS_NAV_BY_OBSS_CF_END___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__CLEAR_INDETERMINISTIC_NAV_BY_INBSS_CF_END___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__UDU_IDLE_PRESEARCH___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__A2_MISMATCH_CLR_AST___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__MBA_UNASSO2045_OPT___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__RXFLUSH_SKIP_PHYABORT_REQ___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__RXPCU_SETUP_COMP_CHK_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__OLE_MPDU_DROP_OVERFLOW_INT_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__SRP_HE_TB_ABORT___M 0x80000000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__SRP_HE_TB_ABORT___S 31 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__FORCE_ULMU_PPDU_END_USER_ST___M 0x40000000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__FORCE_ULMU_PPDU_END_USER_ST___S 30 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__UL_MU_RESP_ADDR_CHK___M 0x20000000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__UL_MU_RESP_ADDR_CHK___S 29 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__MUBAR_TRIG_FRAME_ONE_TIME___M 0x10000000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__MUBAR_TRIG_FRAME_ONE_TIME___S 28 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__RXPCU_SETUP_CLEAR_EXT___M 0x08000000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__RXPCU_SETUP_CLEAR_EXT___S 27 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__SAME_USER_CLEAR_EXT___M 0x04000000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__SAME_USER_CLEAR_EXT___S 26 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__USER_INFO_WR_AFTER_ABORT_EN___M 0x02000000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__USER_INFO_WR_AFTER_ABORT_EN___S 25 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__DATA_CHUNK_256B___M 0x01000000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__DATA_CHUNK_256B___S 24 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TSU_DIFF_USER_BURST___M 0x00800000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TSU_DIFF_USER_BURST___S 23 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TSU_USER_MIDD_BURST___M 0x00400000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TSU_USER_MIDD_BURST___S 22 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TSU_USER_GNT_BURST___M 0x00200000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TSU_USER_GNT_BURST___S 21 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TSU_USER_START_BURST___M 0x00100000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TSU_USER_START_BURST___S 20 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TSU_USER_WHOLE_BURST___M 0x00080000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TSU_USER_WHOLE_BURST___S 19 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__BCN_TIMEOUT_CHECK_FCS_ABORT___M 0x00040000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__BCN_TIMEOUT_CHECK_FCS_ABORT___S 18 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__AID_CTN_MATCH___M 0x00020000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__AID_CTN_MATCH___S 17 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__PPDU_ACK_RPT_ADJ___M 0x00010000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__PPDU_ACK_RPT_ADJ___S 16 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__PRE_SEARCH_PHASE_CLEAR_EN___M 0x00008000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__PRE_SEARCH_PHASE_CLEAR_EN___S 15 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__DISABLE_MONITOR_OTHER_DECRYPT___M 0x00004000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__DISABLE_MONITOR_OTHER_DECRYPT___S 14 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__DISABLE_MONITOR_DIRECT_DECRYPT___M 0x00002000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__DISABLE_MONITOR_DIRECT_DECRYPT___S 13 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__RXPCU_TXPCU_TLV_READY_CHK_EN___M 0x00001000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__RXPCU_TXPCU_TLV_READY_CHK_EN___S 12 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__ULMU_BAR_RESP_CHK_EN___M 0x00000800 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__ULMU_BAR_RESP_CHK_EN___S 11 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__DROP_AST_NO_ACK_BRU_EN___M 0x00000400 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__DROP_AST_NO_ACK_BRU_EN___S 10 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__MBSSID_IMPL_EN___M 0x00000200 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__MBSSID_IMPL_EN___S 9 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TQM_ACKED_MPDU_USER___M 0x00000100 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__TQM_ACKED_MPDU_USER___S 8 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__CLEAR_INBSS_NAV_BY_OBSS_CF_END___M 0x00000080 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__CLEAR_INBSS_NAV_BY_OBSS_CF_END___S 7 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__CLEAR_INDETERMINISTIC_NAV_BY_INBSS_CF_END___M 0x00000040 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__CLEAR_INDETERMINISTIC_NAV_BY_INBSS_CF_END___S 6 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__UDU_IDLE_PRESEARCH___M 0x00000020 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__UDU_IDLE_PRESEARCH___S 5 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__A2_MISMATCH_CLR_AST___M 0x00000010 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__A2_MISMATCH_CLR_AST___S 4 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__MBA_UNASSO2045_OPT___M 0x00000008 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__MBA_UNASSO2045_OPT___S 3 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__RXFLUSH_SKIP_PHYABORT_REQ___M 0x00000004 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__RXFLUSH_SKIP_PHYABORT_REQ___S 2 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__RXPCU_SETUP_COMP_CHK_EN___M 0x00000002 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__RXPCU_SETUP_COMP_CHK_EN___S 1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__OLE_MPDU_DROP_OVERFLOW_INT_EN___M 0x00000001 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL__OLE_MPDU_DROP_OVERFLOW_INT_EN___S 0 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL___S 0 + +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2 (0x00A8C968) +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2___POR 0x4E95D21F +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__OBSS_SR_EXT_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__SRP_DUP_NAV_UPDATE_EN___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__SRG_NON_SRG_EN_SAME_TIME___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__MUBAR_ACK_POLICY_CHK___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__AST_SKIP_NOENOUGH_DATA___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__AST_SKIP_NO_DATA___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__NORESP_UNSUPPORTED_BAR___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__DIS_CBAR_FRAGMENT___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__UNASSO_MGMT_RESP___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__TX_CBF_CANCEL___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__RESPONSE_REQ_CANCEL___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__TX_CBF_INFO_BRPOLL_ADJUST___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__TX_CBF_INFO_NDP_ADJUST___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__NORESP_ULMU_DATA___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__HWSCH_NEED_RESP___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__RXPCU_TXPCU_TLV_ADJUST___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__RXPCU_SETUP_TLV_DELAY___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__UNASSO_USER_AST_SKIP___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__UNASSO_PUBLIC_ACTION_RESP___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__PRE_SEARCH_AST_LATCH___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__UNASSO_TRIGGER_AST_SKIP___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__IGNORE_EXPECT_TYPE_ACK___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__NOT_PARSE_UNSUPPORTED_BA___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__UL_MU_ACK_EN___POR 0x0 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__MAX_SUPPORTED_TID___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__VHT_BAR_TBSSID_RESP_EN___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__VHT_BAR_A2_TBSSID_CONV_EN___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__BCAST_MBA_RESP_A1_CONV_EN___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__FILTER_OUT_DRAIN_FIRST___POR 0x1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__OBSS_SR_EXT_EN___M 0x80000000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__OBSS_SR_EXT_EN___S 31 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__SRP_DUP_NAV_UPDATE_EN___M 0x40000000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__SRP_DUP_NAV_UPDATE_EN___S 30 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__SRG_NON_SRG_EN_SAME_TIME___M 0x20000000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__SRG_NON_SRG_EN_SAME_TIME___S 29 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__MUBAR_ACK_POLICY_CHK___M 0x10000000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__MUBAR_ACK_POLICY_CHK___S 28 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__AST_SKIP_NOENOUGH_DATA___M 0x08000000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__AST_SKIP_NOENOUGH_DATA___S 27 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__AST_SKIP_NO_DATA___M 0x04000000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__AST_SKIP_NO_DATA___S 26 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__NORESP_UNSUPPORTED_BAR___M 0x02000000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__NORESP_UNSUPPORTED_BAR___S 25 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__DIS_CBAR_FRAGMENT___M 0x01000000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__DIS_CBAR_FRAGMENT___S 24 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__UNASSO_MGMT_RESP___M 0x00800000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__UNASSO_MGMT_RESP___S 23 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__TX_CBF_CANCEL___M 0x00400000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__TX_CBF_CANCEL___S 22 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__RESPONSE_REQ_CANCEL___M 0x00200000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__RESPONSE_REQ_CANCEL___S 21 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__TX_CBF_INFO_BRPOLL_ADJUST___M 0x00100000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__TX_CBF_INFO_BRPOLL_ADJUST___S 20 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__TX_CBF_INFO_NDP_ADJUST___M 0x00080000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__TX_CBF_INFO_NDP_ADJUST___S 19 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__NORESP_ULMU_DATA___M 0x00040000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__NORESP_ULMU_DATA___S 18 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__HWSCH_NEED_RESP___M 0x00020000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__HWSCH_NEED_RESP___S 17 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__RXPCU_TXPCU_TLV_ADJUST___M 0x00010000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__RXPCU_TXPCU_TLV_ADJUST___S 16 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__RXPCU_SETUP_TLV_DELAY___M 0x00008000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__RXPCU_SETUP_TLV_DELAY___S 15 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__UNASSO_USER_AST_SKIP___M 0x00004000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__UNASSO_USER_AST_SKIP___S 14 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__UNASSO_PUBLIC_ACTION_RESP___M 0x00002000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__UNASSO_PUBLIC_ACTION_RESP___S 13 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__PRE_SEARCH_AST_LATCH___M 0x00001000 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__PRE_SEARCH_AST_LATCH___S 12 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__UNASSO_TRIGGER_AST_SKIP___M 0x00000800 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__UNASSO_TRIGGER_AST_SKIP___S 11 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__IGNORE_EXPECT_TYPE_ACK___M 0x00000400 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__IGNORE_EXPECT_TYPE_ACK___S 10 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__NOT_PARSE_UNSUPPORTED_BA___M 0x00000200 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__NOT_PARSE_UNSUPPORTED_BA___S 9 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__UL_MU_ACK_EN___M 0x00000100 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__UL_MU_ACK_EN___S 8 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__MAX_SUPPORTED_TID___M 0x000000F0 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__MAX_SUPPORTED_TID___S 4 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__VHT_BAR_TBSSID_RESP_EN___M 0x00000008 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__VHT_BAR_TBSSID_RESP_EN___S 3 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__VHT_BAR_A2_TBSSID_CONV_EN___M 0x00000004 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__VHT_BAR_A2_TBSSID_CONV_EN___S 2 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__BCAST_MBA_RESP_A1_CONV_EN___M 0x00000002 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__BCAST_MBA_RESP_A1_CONV_EN___S 1 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__FILTER_OUT_DRAIN_FIRST___M 0x00000001 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2__FILTER_OUT_DRAIN_FIRST___S 0 +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_RX_MPDU_OPT_CTRL2___S 0 + +#define WMAC0_RXPCU_R0_CLKGATE_CTRL2 (0x00A8C96C) +#define WMAC0_RXPCU_R0_CLKGATE_CTRL2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_CLKGATE_CTRL2___POR 0x00000004 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL2__CLKGAT_DISABLE_AXI_TIMEOUT___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL2__CLKGAT_UDU_TOP_LEGACY___POR 0x1 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL2__CLKGAT_DISABLE_PUS___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL2__CLKGAT_DISABLE_TESTBUS___POR 0x0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL2__CLKGAT_DISABLE_AXI_TIMEOUT___M 0x00000008 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL2__CLKGAT_DISABLE_AXI_TIMEOUT___S 3 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL2__CLKGAT_UDU_TOP_LEGACY___M 0x00000004 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL2__CLKGAT_UDU_TOP_LEGACY___S 2 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL2__CLKGAT_DISABLE_PUS___M 0x00000002 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL2__CLKGAT_DISABLE_PUS___S 1 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL2__CLKGAT_DISABLE_TESTBUS___M 0x00000001 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL2__CLKGAT_DISABLE_TESTBUS___S 0 +#define WMAC0_RXPCU_R0_CLKGATE_CTRL2___M 0x0000000F +#define WMAC0_RXPCU_R0_CLKGATE_CTRL2___S 0 + +#define WMAC0_RXPCU_R0_MISC_MODE5 (0x00A8C970) +#define WMAC0_RXPCU_R0_MISC_MODE5___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_MISC_MODE5___POR 0x00002008 +#define WMAC0_RXPCU_R0_MISC_MODE5__SU_MTID_MBA_BITMAP___POR 0x0 +#define WMAC0_RXPCU_R0_MISC_MODE5__RXOLE_AVAIL_RXPCU_CRYPTO_TLV_SFM_THRESHOLD2___POR 0x010 +#define WMAC0_RXPCU_R0_MISC_MODE5__RXOLE_AVAIL_RXPCU_CRYPTO_TLV_SFM_THRESHOLD1___POR 0x008 +#define WMAC0_RXPCU_R0_MISC_MODE5__SU_MTID_MBA_BITMAP___M 0x00040000 +#define WMAC0_RXPCU_R0_MISC_MODE5__SU_MTID_MBA_BITMAP___S 18 +#define WMAC0_RXPCU_R0_MISC_MODE5__RXOLE_AVAIL_RXPCU_CRYPTO_TLV_SFM_THRESHOLD2___M 0x0003FE00 +#define WMAC0_RXPCU_R0_MISC_MODE5__RXOLE_AVAIL_RXPCU_CRYPTO_TLV_SFM_THRESHOLD2___S 9 +#define WMAC0_RXPCU_R0_MISC_MODE5__RXOLE_AVAIL_RXPCU_CRYPTO_TLV_SFM_THRESHOLD1___M 0x000001FF +#define WMAC0_RXPCU_R0_MISC_MODE5__RXOLE_AVAIL_RXPCU_CRYPTO_TLV_SFM_THRESHOLD1___S 0 +#define WMAC0_RXPCU_R0_MISC_MODE5___M 0x0007FFFF +#define WMAC0_RXPCU_R0_MISC_MODE5___S 0 + +#define WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY (0x00A8C974) +#define WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY___POR 0x00000000 +#define WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY__PHYRX_DATA_DONE_LONGEST_PPDU_ID___POR 0x00 +#define WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY__PHYRX_DATA_DONE_DELAY_LONGEST___POR 0x00 +#define WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY__PHYRX_DATA_DONE_LAST_PPDU_ID___POR 0x00 +#define WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY__PHYRX_DATA_DONE_DELAY_LAST___POR 0x00 +#define WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY__PHYRX_DATA_DONE_LONGEST_PPDU_ID___M 0xFF000000 +#define WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY__PHYRX_DATA_DONE_LONGEST_PPDU_ID___S 24 +#define WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY__PHYRX_DATA_DONE_DELAY_LONGEST___M 0x00FF0000 +#define WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY__PHYRX_DATA_DONE_DELAY_LONGEST___S 16 +#define WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY__PHYRX_DATA_DONE_LAST_PPDU_ID___M 0x0000FF00 +#define WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY__PHYRX_DATA_DONE_LAST_PPDU_ID___S 8 +#define WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY__PHYRX_DATA_DONE_DELAY_LAST___M 0x000000FF +#define WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY__PHYRX_DATA_DONE_DELAY_LAST___S 0 +#define WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PHYRX_DATA_DONE_DELAY___S 0 + +#define WMAC0_RXPCU_R0_PHYRX_PKT_END_DELAY (0x00A8C978) +#define WMAC0_RXPCU_R0_PHYRX_PKT_END_DELAY___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_PHYRX_PKT_END_DELAY___POR 0x00000000 +#define WMAC0_RXPCU_R0_PHYRX_PKT_END_DELAY__PHYRX_PKT_END_LONGEST_PPDU_ID___POR 0x00 +#define WMAC0_RXPCU_R0_PHYRX_PKT_END_DELAY__PHYRX_PKT_END_DELAY_LONGEST___POR 0x00 +#define WMAC0_RXPCU_R0_PHYRX_PKT_END_DELAY__PHYRX_PKT_END_LAST_PPDU_ID___POR 0x00 +#define WMAC0_RXPCU_R0_PHYRX_PKT_END_DELAY__PHYRX_PKT_END_DELAY_LAST___POR 0x00 +#define WMAC0_RXPCU_R0_PHYRX_PKT_END_DELAY__PHYRX_PKT_END_LONGEST_PPDU_ID___M 0xFF000000 +#define WMAC0_RXPCU_R0_PHYRX_PKT_END_DELAY__PHYRX_PKT_END_LONGEST_PPDU_ID___S 24 +#define WMAC0_RXPCU_R0_PHYRX_PKT_END_DELAY__PHYRX_PKT_END_DELAY_LONGEST___M 0x00FF0000 +#define WMAC0_RXPCU_R0_PHYRX_PKT_END_DELAY__PHYRX_PKT_END_DELAY_LONGEST___S 16 +#define WMAC0_RXPCU_R0_PHYRX_PKT_END_DELAY__PHYRX_PKT_END_LAST_PPDU_ID___M 0x0000FF00 +#define WMAC0_RXPCU_R0_PHYRX_PKT_END_DELAY__PHYRX_PKT_END_LAST_PPDU_ID___S 8 +#define WMAC0_RXPCU_R0_PHYRX_PKT_END_DELAY__PHYRX_PKT_END_DELAY_LAST___M 0x000000FF +#define WMAC0_RXPCU_R0_PHYRX_PKT_END_DELAY__PHYRX_PKT_END_DELAY_LAST___S 0 +#define WMAC0_RXPCU_R0_PHYRX_PKT_END_DELAY___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_PHYRX_PKT_END_DELAY___S 0 + +#define WMAC0_RXPCU_R0_AXI_TIMEOUT (0x00A8C97C) +#define WMAC0_RXPCU_R0_AXI_TIMEOUT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_AXI_TIMEOUT___POR 0x00000000 +#define WMAC0_RXPCU_R0_AXI_TIMEOUT__GSE_AXI_TO___POR 0x0 +#define WMAC0_RXPCU_R0_AXI_TIMEOUT__PEER_ENTRY_AXI_TO___POR 0x0 +#define WMAC0_RXPCU_R0_AXI_TIMEOUT__TIMEOUT_STATUS___POR 0x0000 +#define WMAC0_RXPCU_R0_AXI_TIMEOUT__TIMEOUT_LIMIT___POR 0x0000 +#define WMAC0_RXPCU_R0_AXI_TIMEOUT__GSE_AXI_TO___M 0x40000000 +#define WMAC0_RXPCU_R0_AXI_TIMEOUT__GSE_AXI_TO___S 30 +#define WMAC0_RXPCU_R0_AXI_TIMEOUT__PEER_ENTRY_AXI_TO___M 0x20000000 +#define WMAC0_RXPCU_R0_AXI_TIMEOUT__PEER_ENTRY_AXI_TO___S 29 +#define WMAC0_RXPCU_R0_AXI_TIMEOUT__TIMEOUT_STATUS___M 0x1FFF0000 +#define WMAC0_RXPCU_R0_AXI_TIMEOUT__TIMEOUT_STATUS___S 16 +#define WMAC0_RXPCU_R0_AXI_TIMEOUT__TIMEOUT_LIMIT___M 0x00001FFF +#define WMAC0_RXPCU_R0_AXI_TIMEOUT__TIMEOUT_LIMIT___S 0 +#define WMAC0_RXPCU_R0_AXI_TIMEOUT___M 0x7FFF1FFF +#define WMAC0_RXPCU_R0_AXI_TIMEOUT___S 0 + +#define WMAC0_RXPCU_R0_GSE_AXI_DELAY (0x00A8C980) +#define WMAC0_RXPCU_R0_GSE_AXI_DELAY___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_GSE_AXI_DELAY___POR 0x00000000 +#define WMAC0_RXPCU_R0_GSE_AXI_DELAY__GSE_DELAY_LONGEST___POR 0x0000 +#define WMAC0_RXPCU_R0_GSE_AXI_DELAY__GSE_DELAY_LAST___POR 0x0000 +#define WMAC0_RXPCU_R0_GSE_AXI_DELAY__GSE_DELAY_LONGEST___M 0x1FFF0000 +#define WMAC0_RXPCU_R0_GSE_AXI_DELAY__GSE_DELAY_LONGEST___S 16 +#define WMAC0_RXPCU_R0_GSE_AXI_DELAY__GSE_DELAY_LAST___M 0x00001FFF +#define WMAC0_RXPCU_R0_GSE_AXI_DELAY__GSE_DELAY_LAST___S 0 +#define WMAC0_RXPCU_R0_GSE_AXI_DELAY___M 0x1FFF1FFF +#define WMAC0_RXPCU_R0_GSE_AXI_DELAY___S 0 + +#define WMAC0_RXPCU_R0_PEER_ENTRY_AXI_DELAY (0x00A8C984) +#define WMAC0_RXPCU_R0_PEER_ENTRY_AXI_DELAY___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_PEER_ENTRY_AXI_DELAY___POR 0x00000000 +#define WMAC0_RXPCU_R0_PEER_ENTRY_AXI_DELAY__PEER_ENTRY_DELAY_LONGEST___POR 0x0000 +#define WMAC0_RXPCU_R0_PEER_ENTRY_AXI_DELAY__PEER_ENTRY_DELAY_LAST___POR 0x0000 +#define WMAC0_RXPCU_R0_PEER_ENTRY_AXI_DELAY__PEER_ENTRY_DELAY_LONGEST___M 0x1FFF0000 +#define WMAC0_RXPCU_R0_PEER_ENTRY_AXI_DELAY__PEER_ENTRY_DELAY_LONGEST___S 16 +#define WMAC0_RXPCU_R0_PEER_ENTRY_AXI_DELAY__PEER_ENTRY_DELAY_LAST___M 0x00001FFF +#define WMAC0_RXPCU_R0_PEER_ENTRY_AXI_DELAY__PEER_ENTRY_DELAY_LAST___S 0 +#define WMAC0_RXPCU_R0_PEER_ENTRY_AXI_DELAY___M 0x1FFF1FFF +#define WMAC0_RXPCU_R0_PEER_ENTRY_AXI_DELAY___S 0 + +#define WMAC0_RXPCU_R0_TRI_TLV_INFO (0x00A8C988) +#define WMAC0_RXPCU_R0_TRI_TLV_INFO___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_TRI_TLV_INFO___POR 0x00000001 +#define WMAC0_RXPCU_R0_TRI_TLV_INFO__USER0_SW_PEER_ID___POR 0x000 +#define WMAC0_RXPCU_R0_TRI_TLV_INFO__TRI_TLV_INCOM_TAG___POR 0x000 +#define WMAC0_RXPCU_R0_TRI_TLV_INFO__TRI_TLV_COME_TAG___POR 0x000 +#define WMAC0_RXPCU_R0_TRI_TLV_INFO__TRI_TLV_INCOM___POR 0x0 +#define WMAC0_RXPCU_R0_TRI_TLV_INFO__TRI_TLV_IMCOM_INTR_EN___POR 0x1 +#define WMAC0_RXPCU_R0_TRI_TLV_INFO__USER0_SW_PEER_ID___M 0xFFF00000 +#define WMAC0_RXPCU_R0_TRI_TLV_INFO__USER0_SW_PEER_ID___S 20 +#define WMAC0_RXPCU_R0_TRI_TLV_INFO__TRI_TLV_INCOM_TAG___M 0x000FF800 +#define WMAC0_RXPCU_R0_TRI_TLV_INFO__TRI_TLV_INCOM_TAG___S 11 +#define WMAC0_RXPCU_R0_TRI_TLV_INFO__TRI_TLV_COME_TAG___M 0x000007FC +#define WMAC0_RXPCU_R0_TRI_TLV_INFO__TRI_TLV_COME_TAG___S 2 +#define WMAC0_RXPCU_R0_TRI_TLV_INFO__TRI_TLV_INCOM___M 0x00000002 +#define WMAC0_RXPCU_R0_TRI_TLV_INFO__TRI_TLV_INCOM___S 1 +#define WMAC0_RXPCU_R0_TRI_TLV_INFO__TRI_TLV_IMCOM_INTR_EN___M 0x00000001 +#define WMAC0_RXPCU_R0_TRI_TLV_INFO__TRI_TLV_IMCOM_INTR_EN___S 0 +#define WMAC0_RXPCU_R0_TRI_TLV_INFO___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_TRI_TLV_INFO___S 0 + +#define WMAC0_RXPCU_R0_TWT_SP_CFG (0x00A8C98C) +#define WMAC0_RXPCU_R0_TWT_SP_CFG___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_TWT_SP_CFG___POR 0x60000B16 +#define WMAC0_RXPCU_R0_TWT_SP_CFG__TWT_SP_PAUSE_MASK___POR 0x60 +#define WMAC0_RXPCU_R0_TWT_SP_CFG__TWT_SP_PAUSE_VALUE___POR 0x00 +#define WMAC0_RXPCU_R0_TWT_SP_CFG__TWT_SP_PAUSE_ACTION___POR 0x0B +#define WMAC0_RXPCU_R0_TWT_SP_CFG__TWT_SP_PAUSE_CAT___POR 0x16 +#define WMAC0_RXPCU_R0_TWT_SP_CFG__TWT_SP_PAUSE_MASK___M 0xFF000000 +#define WMAC0_RXPCU_R0_TWT_SP_CFG__TWT_SP_PAUSE_MASK___S 24 +#define WMAC0_RXPCU_R0_TWT_SP_CFG__TWT_SP_PAUSE_VALUE___M 0x00FF0000 +#define WMAC0_RXPCU_R0_TWT_SP_CFG__TWT_SP_PAUSE_VALUE___S 16 +#define WMAC0_RXPCU_R0_TWT_SP_CFG__TWT_SP_PAUSE_ACTION___M 0x0000FF00 +#define WMAC0_RXPCU_R0_TWT_SP_CFG__TWT_SP_PAUSE_ACTION___S 8 +#define WMAC0_RXPCU_R0_TWT_SP_CFG__TWT_SP_PAUSE_CAT___M 0x000000FF +#define WMAC0_RXPCU_R0_TWT_SP_CFG__TWT_SP_PAUSE_CAT___S 0 +#define WMAC0_RXPCU_R0_TWT_SP_CFG___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_TWT_SP_CFG___S 0 + +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_n(n) (0x00A8C990+0x4*(n)) +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_n_nMIN 0 +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_n_nMAX 1 +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_n_ELEM 2 +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_n___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_n___POR 0xFFFFFFFF +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_n__BITMAP_EN___POR 0xFFFFFFFF +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_n__BITMAP_EN___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_n__BITMAP_EN___S 0 +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_n___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_n___S 0 +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_0 (0x00A8C990) +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_0__BITMAP_EN___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_0__BITMAP_EN___S 0 +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_1 (0x00A8C994) +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_1__BITMAP_EN___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_COLOR_1__BITMAP_EN___S 0 + +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_n(n) (0x00A8C998+0x4*(n)) +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_n_nMIN 0 +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_n_nMAX 1 +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_n_ELEM 2 +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_n___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_n___POR 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_n__BITMAP_EN___POR 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_n__BITMAP_EN___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_n__BITMAP_EN___S 0 +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_n___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_n___S 0 +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_0 (0x00A8C998) +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_0__BITMAP_EN___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_0__BITMAP_EN___S 0 +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_1 (0x00A8C99C) +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_1__BITMAP_EN___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_COLOR_1__BITMAP_EN___S 0 + +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_n(n) (0x00A8C9A0+0x4*(n)) +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_n_nMIN 0 +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_n_nMAX 1 +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_n_ELEM 2 +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_n___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_n___POR 0xFFFFFFFF +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_n__BITMAP_EN___POR 0xFFFFFFFF +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_n__BITMAP_EN___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_n__BITMAP_EN___S 0 +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_n___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_n___S 0 +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_0 (0x00A8C9A0) +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_0__BITMAP_EN___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_0__BITMAP_EN___S 0 +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_1 (0x00A8C9A4) +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_1__BITMAP_EN___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_NON_SRG_OBSS_EN_BSSID_1__BITMAP_EN___S 0 + +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_n(n) (0x00A8C9A8+0x4*(n)) +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_n_nMIN 0 +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_n_nMAX 1 +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_n_ELEM 2 +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_n___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_n___POR 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_n__BITMAP_EN___POR 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_n__BITMAP_EN___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_n__BITMAP_EN___S 0 +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_n___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_n___S 0 +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_0 (0x00A8C9A8) +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_0__BITMAP_EN___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_0__BITMAP_EN___S 0 +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_1 (0x00A8C9AC) +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_1__BITMAP_EN___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRG_OBSS_EN_BSSID_1__BITMAP_EN___S 0 + +#define WMAC0_RXPCU_R0_SR_CFG_MISC (0x00A8C9B0) +#define WMAC0_RXPCU_R0_SR_CFG_MISC___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SR_CFG_MISC___POR 0x00000001 +#define WMAC0_RXPCU_R0_SR_CFG_MISC__NON_SRG_SR_BITMAP_DIS___POR 0x000 +#define WMAC0_RXPCU_R0_SR_CFG_MISC__SRP_SR_BITMAP_DIS___POR 0x000 +#define WMAC0_RXPCU_R0_SR_CFG_MISC__NON_SRG_OBSS_ACK_EN___POR 0x0 +#define WMAC0_RXPCU_R0_SR_CFG_MISC__SRG_OBSS_ACK_EN___POR 0x0 +#define WMAC0_RXPCU_R0_SR_CFG_MISC__RSSI_SEL_TRIGGER_RESP___POR 0x0 +#define WMAC0_RXPCU_R0_SR_CFG_MISC__SRG_OBSS_CTS_EN___POR 0x0 +#define WMAC0_RXPCU_R0_SR_CFG_MISC__NON_SRG_OBSS_NON_BSSID_EN___POR 0x1 +#define WMAC0_RXPCU_R0_SR_CFG_MISC__NON_SRG_SR_BITMAP_DIS___M 0x1FFE0000 +#define WMAC0_RXPCU_R0_SR_CFG_MISC__NON_SRG_SR_BITMAP_DIS___S 17 +#define WMAC0_RXPCU_R0_SR_CFG_MISC__SRP_SR_BITMAP_DIS___M 0x0001FFE0 +#define WMAC0_RXPCU_R0_SR_CFG_MISC__SRP_SR_BITMAP_DIS___S 5 +#define WMAC0_RXPCU_R0_SR_CFG_MISC__NON_SRG_OBSS_ACK_EN___M 0x00000010 +#define WMAC0_RXPCU_R0_SR_CFG_MISC__NON_SRG_OBSS_ACK_EN___S 4 +#define WMAC0_RXPCU_R0_SR_CFG_MISC__SRG_OBSS_ACK_EN___M 0x00000008 +#define WMAC0_RXPCU_R0_SR_CFG_MISC__SRG_OBSS_ACK_EN___S 3 +#define WMAC0_RXPCU_R0_SR_CFG_MISC__RSSI_SEL_TRIGGER_RESP___M 0x00000004 +#define WMAC0_RXPCU_R0_SR_CFG_MISC__RSSI_SEL_TRIGGER_RESP___S 2 +#define WMAC0_RXPCU_R0_SR_CFG_MISC__SRG_OBSS_CTS_EN___M 0x00000002 +#define WMAC0_RXPCU_R0_SR_CFG_MISC__SRG_OBSS_CTS_EN___S 1 +#define WMAC0_RXPCU_R0_SR_CFG_MISC__NON_SRG_OBSS_NON_BSSID_EN___M 0x00000001 +#define WMAC0_RXPCU_R0_SR_CFG_MISC__NON_SRG_OBSS_NON_BSSID_EN___S 0 +#define WMAC0_RXPCU_R0_SR_CFG_MISC___M 0x1FFFFFFF +#define WMAC0_RXPCU_R0_SR_CFG_MISC___S 0 + +#define WMAC0_RXPCU_R0_SRP_RESP_CFG (0x00A8C9B4) +#define WMAC0_RXPCU_R0_SRP_RESP_CFG___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SRP_RESP_CFG___POR 0x00000000 +#define WMAC0_RXPCU_R0_SRP_RESP_CFG__OBSS_NAV_DIS___POR 0x0 +#define WMAC0_RXPCU_R0_SRP_RESP_CFG__CAS_PATTERN_EN___POR 0x00 +#define WMAC0_RXPCU_R0_SRP_RESP_CFG__OBSS_NAV_DIS___M 0x00000040 +#define WMAC0_RXPCU_R0_SRP_RESP_CFG__OBSS_NAV_DIS___S 6 +#define WMAC0_RXPCU_R0_SRP_RESP_CFG__CAS_PATTERN_EN___M 0x0000003F +#define WMAC0_RXPCU_R0_SRP_RESP_CFG__CAS_PATTERN_EN___S 0 +#define WMAC0_RXPCU_R0_SRP_RESP_CFG___M 0x0000007F +#define WMAC0_RXPCU_R0_SRP_RESP_CFG___S 0 + +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE0 (0x00A8C9B8) +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE0___POR 0x01180007 +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE0__PATTERN___POR 0x01180007 +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE0__PATTERN___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE0__PATTERN___S 0 +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE0___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE0___S 0 + +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE1 (0x00A8C9BC) +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE1___POR 0x00118013 +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE1__PATTERN___POR 0x00118013 +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE1__PATTERN___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE1__PATTERN___S 0 +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE1___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE1___S 0 + +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE2 (0x00A8C9C0) +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE2___POR 0x00460017 +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE2__PATTERN___POR 0x00460017 +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE2__PATTERN___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE2__PATTERN___S 0 +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE2___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE2___S 0 + +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE3 (0x00A8C9C4) +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE3___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE3___POR 0x0000011B +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE3__PATTERN___POR 0x0000011B +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE3__PATTERN___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE3__PATTERN___S 0 +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE3___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE3___S 0 + +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE4 (0x00A8C9C8) +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE4___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE4___POR 0x00000000 +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE4__PATTERN___POR 0x00000000 +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE4__PATTERN___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE4__PATTERN___S 0 +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE4___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE4___S 0 + +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE5 (0x00A8C9CC) +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE5___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE5___POR 0x00000000 +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE5__PATTERN___POR 0x00000000 +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE5__PATTERN___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE5__PATTERN___S 0 +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE5___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRP_RESP_VALUE5___S 0 + +#define WMAC0_RXPCU_R0_SRP_RESP_MASK0 (0x00A8C9D0) +#define WMAC0_RXPCU_R0_SRP_RESP_MASK0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SRP_RESP_MASK0___POR 0x013C003F +#define WMAC0_RXPCU_R0_SRP_RESP_MASK0__PATTERN___POR 0x013C003F +#define WMAC0_RXPCU_R0_SRP_RESP_MASK0__PATTERN___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRP_RESP_MASK0__PATTERN___S 0 +#define WMAC0_RXPCU_R0_SRP_RESP_MASK0___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRP_RESP_MASK0___S 0 + +#define WMAC0_RXPCU_R0_SRP_RESP_MASK1 (0x00A8C9D4) +#define WMAC0_RXPCU_R0_SRP_RESP_MASK1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SRP_RESP_MASK1___POR 0x0013C03F +#define WMAC0_RXPCU_R0_SRP_RESP_MASK1__PATTERN___POR 0x0013C03F +#define WMAC0_RXPCU_R0_SRP_RESP_MASK1__PATTERN___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRP_RESP_MASK1__PATTERN___S 0 +#define WMAC0_RXPCU_R0_SRP_RESP_MASK1___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRP_RESP_MASK1___S 0 + +#define WMAC0_RXPCU_R0_SRP_RESP_MASK2 (0x00A8C9D8) +#define WMAC0_RXPCU_R0_SRP_RESP_MASK2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SRP_RESP_MASK2___POR 0x004F003F +#define WMAC0_RXPCU_R0_SRP_RESP_MASK2__PATTERN___POR 0x004F003F +#define WMAC0_RXPCU_R0_SRP_RESP_MASK2__PATTERN___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRP_RESP_MASK2__PATTERN___S 0 +#define WMAC0_RXPCU_R0_SRP_RESP_MASK2___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRP_RESP_MASK2___S 0 + +#define WMAC0_RXPCU_R0_SRP_RESP_MASK3 (0x00A8C9DC) +#define WMAC0_RXPCU_R0_SRP_RESP_MASK3___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SRP_RESP_MASK3___POR 0x0000013F +#define WMAC0_RXPCU_R0_SRP_RESP_MASK3__PATTERN___POR 0x0000013F +#define WMAC0_RXPCU_R0_SRP_RESP_MASK3__PATTERN___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRP_RESP_MASK3__PATTERN___S 0 +#define WMAC0_RXPCU_R0_SRP_RESP_MASK3___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRP_RESP_MASK3___S 0 + +#define WMAC0_RXPCU_R0_SRP_RESP_MASK4 (0x00A8C9E0) +#define WMAC0_RXPCU_R0_SRP_RESP_MASK4___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SRP_RESP_MASK4___POR 0x00000000 +#define WMAC0_RXPCU_R0_SRP_RESP_MASK4__PATTERN___POR 0x00000000 +#define WMAC0_RXPCU_R0_SRP_RESP_MASK4__PATTERN___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRP_RESP_MASK4__PATTERN___S 0 +#define WMAC0_RXPCU_R0_SRP_RESP_MASK4___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRP_RESP_MASK4___S 0 + +#define WMAC0_RXPCU_R0_SRP_RESP_MASK5 (0x00A8C9E4) +#define WMAC0_RXPCU_R0_SRP_RESP_MASK5___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_SRP_RESP_MASK5___POR 0x00000000 +#define WMAC0_RXPCU_R0_SRP_RESP_MASK5__PATTERN___POR 0x00000000 +#define WMAC0_RXPCU_R0_SRP_RESP_MASK5__PATTERN___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRP_RESP_MASK5__PATTERN___S 0 +#define WMAC0_RXPCU_R0_SRP_RESP_MASK5___M 0xFFFFFFFF +#define WMAC0_RXPCU_R0_SRP_RESP_MASK5___S 0 + +#define WMAC0_RXPCU_R0_ILP_CFG_1 (0x00A8C9E8) +#define WMAC0_RXPCU_R0_ILP_CFG_1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_ILP_CFG_1___POR 0x1D000000 +#define WMAC0_RXPCU_R0_ILP_CFG_1__ILP_DISABLE___POR 0x1 +#define WMAC0_RXPCU_R0_ILP_CFG_1__L0_REQ_B4_PPDU_END_EN___POR 0x1 +#define WMAC0_RXPCU_R0_ILP_CFG_1__L0_REQ_ONLY_FOR_FILTERED_IN_FRAME___POR 0x1 +#define WMAC0_RXPCU_R0_ILP_CFG_1__DEASSERT_L0_REQ_IF_FCS_FAILS___POR 0x0 +#define WMAC0_RXPCU_R0_ILP_CFG_1__DISABLE_AST_QUAL_FOR_TRIGGER_DETECTION___POR 0x1 +#define WMAC0_RXPCU_R0_ILP_CFG_1__DEASSERT_L0_REQ_AFTER_PPDU_END_DURATION___POR 0x00 +#define WMAC0_RXPCU_R0_ILP_CFG_1__ASSERT_L0_REQ_B4_PPDU_END_DURATION___POR 0x00 +#define WMAC0_RXPCU_R0_ILP_CFG_1__UNMASK_L0_REQ_B4_PPDU_END_DURATION___POR 0x00 +#define WMAC0_RXPCU_R0_ILP_CFG_1__ILP_DISABLE___M 0x10000000 +#define WMAC0_RXPCU_R0_ILP_CFG_1__ILP_DISABLE___S 28 +#define WMAC0_RXPCU_R0_ILP_CFG_1__L0_REQ_B4_PPDU_END_EN___M 0x08000000 +#define WMAC0_RXPCU_R0_ILP_CFG_1__L0_REQ_B4_PPDU_END_EN___S 27 +#define WMAC0_RXPCU_R0_ILP_CFG_1__L0_REQ_ONLY_FOR_FILTERED_IN_FRAME___M 0x04000000 +#define WMAC0_RXPCU_R0_ILP_CFG_1__L0_REQ_ONLY_FOR_FILTERED_IN_FRAME___S 26 +#define WMAC0_RXPCU_R0_ILP_CFG_1__DEASSERT_L0_REQ_IF_FCS_FAILS___M 0x02000000 +#define WMAC0_RXPCU_R0_ILP_CFG_1__DEASSERT_L0_REQ_IF_FCS_FAILS___S 25 +#define WMAC0_RXPCU_R0_ILP_CFG_1__DISABLE_AST_QUAL_FOR_TRIGGER_DETECTION___M 0x01000000 +#define WMAC0_RXPCU_R0_ILP_CFG_1__DISABLE_AST_QUAL_FOR_TRIGGER_DETECTION___S 24 +#define WMAC0_RXPCU_R0_ILP_CFG_1__DEASSERT_L0_REQ_AFTER_PPDU_END_DURATION___M 0x00FF0000 +#define WMAC0_RXPCU_R0_ILP_CFG_1__DEASSERT_L0_REQ_AFTER_PPDU_END_DURATION___S 16 +#define WMAC0_RXPCU_R0_ILP_CFG_1__ASSERT_L0_REQ_B4_PPDU_END_DURATION___M 0x0000FF00 +#define WMAC0_RXPCU_R0_ILP_CFG_1__ASSERT_L0_REQ_B4_PPDU_END_DURATION___S 8 +#define WMAC0_RXPCU_R0_ILP_CFG_1__UNMASK_L0_REQ_B4_PPDU_END_DURATION___M 0x000000FF +#define WMAC0_RXPCU_R0_ILP_CFG_1__UNMASK_L0_REQ_B4_PPDU_END_DURATION___S 0 +#define WMAC0_RXPCU_R0_ILP_CFG_1___M 0x1FFFFFFF +#define WMAC0_RXPCU_R0_ILP_CFG_1___S 0 + +#define WMAC0_RXPCU_R0_ILP_CFG_2 (0x00A8C9EC) +#define WMAC0_RXPCU_R0_ILP_CFG_2___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_ILP_CFG_2___POR 0x00000000 +#define WMAC0_RXPCU_R0_ILP_CFG_2__THRESHOLD_FOR_RATE_400_TO_LESS_THAN_600___POR 0x000 +#define WMAC0_RXPCU_R0_ILP_CFG_2__THRESHOLD_FOR_RATE_200_TO_LESS_THAN_400___POR 0x000 +#define WMAC0_RXPCU_R0_ILP_CFG_2__THRESHOLD_FOR_RATE_0_TO_LESS_THAN_200___POR 0x000 +#define WMAC0_RXPCU_R0_ILP_CFG_2__THRESHOLD_FOR_RATE_400_TO_LESS_THAN_600___M 0x07FC0000 +#define WMAC0_RXPCU_R0_ILP_CFG_2__THRESHOLD_FOR_RATE_400_TO_LESS_THAN_600___S 18 +#define WMAC0_RXPCU_R0_ILP_CFG_2__THRESHOLD_FOR_RATE_200_TO_LESS_THAN_400___M 0x0003FE00 +#define WMAC0_RXPCU_R0_ILP_CFG_2__THRESHOLD_FOR_RATE_200_TO_LESS_THAN_400___S 9 +#define WMAC0_RXPCU_R0_ILP_CFG_2__THRESHOLD_FOR_RATE_0_TO_LESS_THAN_200___M 0x000001FF +#define WMAC0_RXPCU_R0_ILP_CFG_2__THRESHOLD_FOR_RATE_0_TO_LESS_THAN_200___S 0 +#define WMAC0_RXPCU_R0_ILP_CFG_2___M 0x07FFFFFF +#define WMAC0_RXPCU_R0_ILP_CFG_2___S 0 + +#define WMAC0_RXPCU_R0_ILP_CFG_3 (0x00A8C9F0) +#define WMAC0_RXPCU_R0_ILP_CFG_3___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_ILP_CFG_3___POR 0x00000000 +#define WMAC0_RXPCU_R0_ILP_CFG_3__THRESHOLD_FOR_RATE_1000_TO_LESS_THAN_1200___POR 0x000 +#define WMAC0_RXPCU_R0_ILP_CFG_3__THRESHOLD_FOR_RATE_800_TO_LESS_THAN_1000___POR 0x000 +#define WMAC0_RXPCU_R0_ILP_CFG_3__THRESHOLD_FOR_RATE_600_TO_LESS_THAN_800___POR 0x000 +#define WMAC0_RXPCU_R0_ILP_CFG_3__THRESHOLD_FOR_RATE_1000_TO_LESS_THAN_1200___M 0x07FC0000 +#define WMAC0_RXPCU_R0_ILP_CFG_3__THRESHOLD_FOR_RATE_1000_TO_LESS_THAN_1200___S 18 +#define WMAC0_RXPCU_R0_ILP_CFG_3__THRESHOLD_FOR_RATE_800_TO_LESS_THAN_1000___M 0x0003FE00 +#define WMAC0_RXPCU_R0_ILP_CFG_3__THRESHOLD_FOR_RATE_800_TO_LESS_THAN_1000___S 9 +#define WMAC0_RXPCU_R0_ILP_CFG_3__THRESHOLD_FOR_RATE_600_TO_LESS_THAN_800___M 0x000001FF +#define WMAC0_RXPCU_R0_ILP_CFG_3__THRESHOLD_FOR_RATE_600_TO_LESS_THAN_800___S 0 +#define WMAC0_RXPCU_R0_ILP_CFG_3___M 0x07FFFFFF +#define WMAC0_RXPCU_R0_ILP_CFG_3___S 0 + +#define WMAC0_RXPCU_R0_ILP_CFG_4 (0x00A8C9F4) +#define WMAC0_RXPCU_R0_ILP_CFG_4___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_ILP_CFG_4___POR 0x00000000 +#define WMAC0_RXPCU_R0_ILP_CFG_4__THRESHOLD_FOR_RATE_1600_TO_LESS_THAN_1800___POR 0x000 +#define WMAC0_RXPCU_R0_ILP_CFG_4__THRESHOLD_FOR_RATE_1400_TO_LESS_THAN_1600___POR 0x000 +#define WMAC0_RXPCU_R0_ILP_CFG_4__THRESHOLD_FOR_RATE_1200_TO_LESS_THAN_1400___POR 0x000 +#define WMAC0_RXPCU_R0_ILP_CFG_4__THRESHOLD_FOR_RATE_1600_TO_LESS_THAN_1800___M 0x07FC0000 +#define WMAC0_RXPCU_R0_ILP_CFG_4__THRESHOLD_FOR_RATE_1600_TO_LESS_THAN_1800___S 18 +#define WMAC0_RXPCU_R0_ILP_CFG_4__THRESHOLD_FOR_RATE_1400_TO_LESS_THAN_1600___M 0x0003FE00 +#define WMAC0_RXPCU_R0_ILP_CFG_4__THRESHOLD_FOR_RATE_1400_TO_LESS_THAN_1600___S 9 +#define WMAC0_RXPCU_R0_ILP_CFG_4__THRESHOLD_FOR_RATE_1200_TO_LESS_THAN_1400___M 0x000001FF +#define WMAC0_RXPCU_R0_ILP_CFG_4__THRESHOLD_FOR_RATE_1200_TO_LESS_THAN_1400___S 0 +#define WMAC0_RXPCU_R0_ILP_CFG_4___M 0x07FFFFFF +#define WMAC0_RXPCU_R0_ILP_CFG_4___S 0 + +#define WMAC0_RXPCU_R0_ILP_CFG_5 (0x00A8C9F8) +#define WMAC0_RXPCU_R0_ILP_CFG_5___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_ILP_CFG_5___POR 0x00000000 +#define WMAC0_RXPCU_R0_ILP_CFG_5__THRESHOLD_FOR_RATE_2200_TO_LESS_THAN_2400___POR 0x000 +#define WMAC0_RXPCU_R0_ILP_CFG_5__THRESHOLD_FOR_RATE_2000_TO_LESS_THAN_2200___POR 0x000 +#define WMAC0_RXPCU_R0_ILP_CFG_5__THRESHOLD_FOR_RATE_1800_TO_LESS_THAN_2000___POR 0x000 +#define WMAC0_RXPCU_R0_ILP_CFG_5__THRESHOLD_FOR_RATE_2200_TO_LESS_THAN_2400___M 0x07FC0000 +#define WMAC0_RXPCU_R0_ILP_CFG_5__THRESHOLD_FOR_RATE_2200_TO_LESS_THAN_2400___S 18 +#define WMAC0_RXPCU_R0_ILP_CFG_5__THRESHOLD_FOR_RATE_2000_TO_LESS_THAN_2200___M 0x0003FE00 +#define WMAC0_RXPCU_R0_ILP_CFG_5__THRESHOLD_FOR_RATE_2000_TO_LESS_THAN_2200___S 9 +#define WMAC0_RXPCU_R0_ILP_CFG_5__THRESHOLD_FOR_RATE_1800_TO_LESS_THAN_2000___M 0x000001FF +#define WMAC0_RXPCU_R0_ILP_CFG_5__THRESHOLD_FOR_RATE_1800_TO_LESS_THAN_2000___S 0 +#define WMAC0_RXPCU_R0_ILP_CFG_5___M 0x07FFFFFF +#define WMAC0_RXPCU_R0_ILP_CFG_5___S 0 + +#define WMAC0_RXPCU_R0_ILP_CFG_6 (0x00A8C9FC) +#define WMAC0_RXPCU_R0_ILP_CFG_6___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_ILP_CFG_6___POR 0x00000000 +#define WMAC0_RXPCU_R0_ILP_CFG_6__THRESHOLD_FOR_RATE_2800_TO_LESS_THAN_3000___POR 0x000 +#define WMAC0_RXPCU_R0_ILP_CFG_6__THRESHOLD_FOR_RATE_2600_TO_LESS_THAN_2800___POR 0x000 +#define WMAC0_RXPCU_R0_ILP_CFG_6__THRESHOLD_FOR_RATE_2400_TO_LESS_THAN_2600___POR 0x000 +#define WMAC0_RXPCU_R0_ILP_CFG_6__THRESHOLD_FOR_RATE_2800_TO_LESS_THAN_3000___M 0x07FC0000 +#define WMAC0_RXPCU_R0_ILP_CFG_6__THRESHOLD_FOR_RATE_2800_TO_LESS_THAN_3000___S 18 +#define WMAC0_RXPCU_R0_ILP_CFG_6__THRESHOLD_FOR_RATE_2600_TO_LESS_THAN_2800___M 0x0003FE00 +#define WMAC0_RXPCU_R0_ILP_CFG_6__THRESHOLD_FOR_RATE_2600_TO_LESS_THAN_2800___S 9 +#define WMAC0_RXPCU_R0_ILP_CFG_6__THRESHOLD_FOR_RATE_2400_TO_LESS_THAN_2600___M 0x000001FF +#define WMAC0_RXPCU_R0_ILP_CFG_6__THRESHOLD_FOR_RATE_2400_TO_LESS_THAN_2600___S 0 +#define WMAC0_RXPCU_R0_ILP_CFG_6___M 0x07FFFFFF +#define WMAC0_RXPCU_R0_ILP_CFG_6___S 0 + +#define WMAC0_RXPCU_R0_ILP_CFG_7 (0x00A8CA00) +#define WMAC0_RXPCU_R0_ILP_CFG_7___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R0_ILP_CFG_7___POR 0x00008000 +#define WMAC0_RXPCU_R0_ILP_CFG_7__TAG_FIFO_OCCUPANCY_THRESHOLD___POR 0x40 +#define WMAC0_RXPCU_R0_ILP_CFG_7__SFM_LOW_THRESHOLD___POR 0x000 +#define WMAC0_RXPCU_R0_ILP_CFG_7__TAG_FIFO_OCCUPANCY_THRESHOLD___M 0x0000FE00 +#define WMAC0_RXPCU_R0_ILP_CFG_7__TAG_FIFO_OCCUPANCY_THRESHOLD___S 9 +#define WMAC0_RXPCU_R0_ILP_CFG_7__SFM_LOW_THRESHOLD___M 0x000001FF +#define WMAC0_RXPCU_R0_ILP_CFG_7__SFM_LOW_THRESHOLD___S 0 +#define WMAC0_RXPCU_R0_ILP_CFG_7___M 0x0000FFFF +#define WMAC0_RXPCU_R0_ILP_CFG_7___S 0 + +#define WMAC0_RXPCU_R1_GSE_END_OF_TEST_CHECK (0x00A8D000) +#define WMAC0_RXPCU_R1_GSE_END_OF_TEST_CHECK___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_GSE_END_OF_TEST_CHECK___POR 0x00000000 +#define WMAC0_RXPCU_R1_GSE_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0 +#define WMAC0_RXPCU_R1_GSE_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001 +#define WMAC0_RXPCU_R1_GSE_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S 0 +#define WMAC0_RXPCU_R1_GSE_END_OF_TEST_CHECK___M 0x00000001 +#define WMAC0_RXPCU_R1_GSE_END_OF_TEST_CHECK___S 0 + +#define WMAC0_RXPCU_R1_GSE_DEBUG_CLEAR_COUNTERS (0x00A8D004) +#define WMAC0_RXPCU_R1_GSE_DEBUG_CLEAR_COUNTERS___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_GSE_DEBUG_CLEAR_COUNTERS___POR 0x00000000 +#define WMAC0_RXPCU_R1_GSE_DEBUG_CLEAR_COUNTERS__EN___POR 0x0 +#define WMAC0_RXPCU_R1_GSE_DEBUG_CLEAR_COUNTERS__EN___M 0x00000001 +#define WMAC0_RXPCU_R1_GSE_DEBUG_CLEAR_COUNTERS__EN___S 0 +#define WMAC0_RXPCU_R1_GSE_DEBUG_CLEAR_COUNTERS___M 0x00000001 +#define WMAC0_RXPCU_R1_GSE_DEBUG_CLEAR_COUNTERS___S 0 + +#define WMAC0_RXPCU_R1_GSE_DEBUG_NUM_CACHE_HITS_COUNTER (0x00A8D008) +#define WMAC0_RXPCU_R1_GSE_DEBUG_NUM_CACHE_HITS_COUNTER___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_DEBUG_NUM_CACHE_HITS_COUNTER___POR 0x00000000 +#define WMAC0_RXPCU_R1_GSE_DEBUG_NUM_CACHE_HITS_COUNTER__VAL___POR 0x00000000 +#define WMAC0_RXPCU_R1_GSE_DEBUG_NUM_CACHE_HITS_COUNTER__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_DEBUG_NUM_CACHE_HITS_COUNTER__VAL___S 0 +#define WMAC0_RXPCU_R1_GSE_DEBUG_NUM_CACHE_HITS_COUNTER___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_DEBUG_NUM_CACHE_HITS_COUNTER___S 0 + +#define WMAC0_RXPCU_R1_GSE_DEBUG_NUM_SEARCHES_COUNTER (0x00A8D00C) +#define WMAC0_RXPCU_R1_GSE_DEBUG_NUM_SEARCHES_COUNTER___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_DEBUG_NUM_SEARCHES_COUNTER___POR 0x00000000 +#define WMAC0_RXPCU_R1_GSE_DEBUG_NUM_SEARCHES_COUNTER__VAL___POR 0x00000000 +#define WMAC0_RXPCU_R1_GSE_DEBUG_NUM_SEARCHES_COUNTER__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_DEBUG_NUM_SEARCHES_COUNTER__VAL___S 0 +#define WMAC0_RXPCU_R1_GSE_DEBUG_NUM_SEARCHES_COUNTER___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_DEBUG_NUM_SEARCHES_COUNTER___S 0 + +#define WMAC0_RXPCU_R1_GSE_DEBUG_CACHE_OCCUPANCY_COUNTER (0x00A8D010) +#define WMAC0_RXPCU_R1_GSE_DEBUG_CACHE_OCCUPANCY_COUNTER___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_DEBUG_CACHE_OCCUPANCY_COUNTER___POR 0x00000000 +#define WMAC0_RXPCU_R1_GSE_DEBUG_CACHE_OCCUPANCY_COUNTER__PEAK___POR 0x000 +#define WMAC0_RXPCU_R1_GSE_DEBUG_CACHE_OCCUPANCY_COUNTER__CURR___POR 0x000 +#define WMAC0_RXPCU_R1_GSE_DEBUG_CACHE_OCCUPANCY_COUNTER__PEAK___M 0x000FFC00 +#define WMAC0_RXPCU_R1_GSE_DEBUG_CACHE_OCCUPANCY_COUNTER__PEAK___S 10 +#define WMAC0_RXPCU_R1_GSE_DEBUG_CACHE_OCCUPANCY_COUNTER__CURR___M 0x000003FF +#define WMAC0_RXPCU_R1_GSE_DEBUG_CACHE_OCCUPANCY_COUNTER__CURR___S 0 +#define WMAC0_RXPCU_R1_GSE_DEBUG_CACHE_OCCUPANCY_COUNTER___M 0x000FFFFF +#define WMAC0_RXPCU_R1_GSE_DEBUG_CACHE_OCCUPANCY_COUNTER___S 0 + +#define WMAC0_RXPCU_R1_GSE_DEBUG_SEARCH_STAT_COUNTER (0x00A8D014) +#define WMAC0_RXPCU_R1_GSE_DEBUG_SEARCH_STAT_COUNTER___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_DEBUG_SEARCH_STAT_COUNTER___POR 0x00000000 +#define WMAC0_RXPCU_R1_GSE_DEBUG_SEARCH_STAT_COUNTER__SQUARE_OCCUPANCY___POR 0x0000 +#define WMAC0_RXPCU_R1_GSE_DEBUG_SEARCH_STAT_COUNTER__PEAK_NUM_SEARCH_PENDING___POR 0x00 +#define WMAC0_RXPCU_R1_GSE_DEBUG_SEARCH_STAT_COUNTER__NUM_SEARCH_PENDING___POR 0x00 +#define WMAC0_RXPCU_R1_GSE_DEBUG_SEARCH_STAT_COUNTER__SQUARE_OCCUPANCY___M 0x03FFFC00 +#define WMAC0_RXPCU_R1_GSE_DEBUG_SEARCH_STAT_COUNTER__SQUARE_OCCUPANCY___S 10 +#define WMAC0_RXPCU_R1_GSE_DEBUG_SEARCH_STAT_COUNTER__PEAK_NUM_SEARCH_PENDING___M 0x000003E0 +#define WMAC0_RXPCU_R1_GSE_DEBUG_SEARCH_STAT_COUNTER__PEAK_NUM_SEARCH_PENDING___S 5 +#define WMAC0_RXPCU_R1_GSE_DEBUG_SEARCH_STAT_COUNTER__NUM_SEARCH_PENDING___M 0x0000001F +#define WMAC0_RXPCU_R1_GSE_DEBUG_SEARCH_STAT_COUNTER__NUM_SEARCH_PENDING___S 0 +#define WMAC0_RXPCU_R1_GSE_DEBUG_SEARCH_STAT_COUNTER___M 0x03FFFFFF +#define WMAC0_RXPCU_R1_GSE_DEBUG_SEARCH_STAT_COUNTER___S 0 + +#define WMAC0_RXPCU_R1_GSE_SM_STATES (0x00A8D018) +#define WMAC0_RXPCU_R1_GSE_SM_STATES___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_SM_STATES___POR 0x00000000 +#define WMAC0_RXPCU_R1_GSE_SM_STATES__GSE_CTRL_STATE___POR 0x0 +#define WMAC0_RXPCU_R1_GSE_SM_STATES__CACHE_CHK_STATE___POR 0x0 +#define WMAC0_RXPCU_R1_GSE_SM_STATES__MEM_ISS1_STATE___POR 0x0 +#define WMAC0_RXPCU_R1_GSE_SM_STATES__MEM_ISS2_STATE___POR 0x0 +#define WMAC0_RXPCU_R1_GSE_SM_STATES__MEM_RESP1_STATE___POR 0x0 +#define WMAC0_RXPCU_R1_GSE_SM_STATES__MEM_RESP2_STATE___POR 0x0 +#define WMAC0_RXPCU_R1_GSE_SM_STATES__APP_RETURN_STATE___POR 0x0 +#define WMAC0_RXPCU_R1_GSE_SM_STATES__GSE_CTRL_STATE___M 0x00300000 +#define WMAC0_RXPCU_R1_GSE_SM_STATES__GSE_CTRL_STATE___S 20 +#define WMAC0_RXPCU_R1_GSE_SM_STATES__CACHE_CHK_STATE___M 0x000C0000 +#define WMAC0_RXPCU_R1_GSE_SM_STATES__CACHE_CHK_STATE___S 18 +#define WMAC0_RXPCU_R1_GSE_SM_STATES__MEM_ISS1_STATE___M 0x00030000 +#define WMAC0_RXPCU_R1_GSE_SM_STATES__MEM_ISS1_STATE___S 16 +#define WMAC0_RXPCU_R1_GSE_SM_STATES__MEM_ISS2_STATE___M 0x0000C000 +#define WMAC0_RXPCU_R1_GSE_SM_STATES__MEM_ISS2_STATE___S 14 +#define WMAC0_RXPCU_R1_GSE_SM_STATES__MEM_RESP1_STATE___M 0x00003800 +#define WMAC0_RXPCU_R1_GSE_SM_STATES__MEM_RESP1_STATE___S 11 +#define WMAC0_RXPCU_R1_GSE_SM_STATES__MEM_RESP2_STATE___M 0x00000700 +#define WMAC0_RXPCU_R1_GSE_SM_STATES__MEM_RESP2_STATE___S 8 +#define WMAC0_RXPCU_R1_GSE_SM_STATES__APP_RETURN_STATE___M 0x0000000F +#define WMAC0_RXPCU_R1_GSE_SM_STATES__APP_RETURN_STATE___S 0 +#define WMAC0_RXPCU_R1_GSE_SM_STATES___M 0x003FFF0F +#define WMAC0_RXPCU_R1_GSE_SM_STATES___S 0 + +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG (0x00A8D01C) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG___POR 0x00000000 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG__READ_IDX___POR 0x000 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG__READ_IDX___M 0x000003FF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG__READ_IDX___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG___M 0x000003FF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG___S 0 + +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_STATS (0x00A8D020) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_STATS___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_STATS___POR 0x00000000 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_STATS__GST_IDX___POR 0x00000 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_STATS__CACHE_ONLY___POR 0x0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_STATS__DIRTY___POR 0x0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_STATS__VALID___POR 0x0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_STATS__GST_IDX___M 0x007FFFF8 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_STATS__GST_IDX___S 3 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_STATS__CACHE_ONLY___M 0x00000004 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_STATS__CACHE_ONLY___S 2 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_STATS__DIRTY___M 0x00000002 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_STATS__DIRTY___S 1 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_STATS__VALID___M 0x00000001 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_STATS__VALID___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_STATS___M 0x007FFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_STATS___S 0 + +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_n(n) (0x00A8D024+0x4*(n)) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_n_nMIN 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_n_nMAX 31 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_n_ELEM 32 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_n___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_n___POR 0x00000000 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_n__VAL___POR 0x00000000 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_n__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_n__VAL___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_n___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_n___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_0 (0x00A8D024) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_0___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_0__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_0__VAL___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_1 (0x00A8D028) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_1___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_1__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_1__VAL___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_2 (0x00A8D02C) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_2___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_2__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_2__VAL___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_3 (0x00A8D030) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_3___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_3__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_3__VAL___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_4 (0x00A8D034) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_4___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_4__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_4__VAL___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_5 (0x00A8D038) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_5___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_5__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_5__VAL___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_6 (0x00A8D03C) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_6___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_6__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_6__VAL___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_7 (0x00A8D040) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_7___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_7__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_7__VAL___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_8 (0x00A8D044) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_8___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_8__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_8__VAL___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_9 (0x00A8D048) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_9___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_9__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_9__VAL___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_10 (0x00A8D04C) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_10___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_10__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_10__VAL___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_11 (0x00A8D050) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_11___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_11__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_11__VAL___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_12 (0x00A8D054) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_12___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_12__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_12__VAL___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_13 (0x00A8D058) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_13___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_13__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_13__VAL___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_14 (0x00A8D05C) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_14___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_14__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_14__VAL___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_15 (0x00A8D060) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_15___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_15__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_15__VAL___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_16 (0x00A8D064) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_16___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_16__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_16__VAL___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_17 (0x00A8D068) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_17___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_17__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_17__VAL___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_18 (0x00A8D06C) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_18___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_18__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_18__VAL___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_19 (0x00A8D070) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_19___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_19__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_19__VAL___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_20 (0x00A8D074) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_20___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_20__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_20__VAL___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_21 (0x00A8D078) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_21___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_21__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_21__VAL___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_22 (0x00A8D07C) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_22___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_22__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_22__VAL___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_23 (0x00A8D080) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_23___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_23__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_23__VAL___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_24 (0x00A8D084) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_24___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_24__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_24__VAL___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_25 (0x00A8D088) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_25___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_25__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_25__VAL___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_26 (0x00A8D08C) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_26___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_26__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_26__VAL___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_27 (0x00A8D090) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_27___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_27__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_27__VAL___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_28 (0x00A8D094) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_28___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_28__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_28__VAL___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_29 (0x00A8D098) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_29___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_29__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_29__VAL___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_30 (0x00A8D09C) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_30___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_30__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_30__VAL___S 0 +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_31 (0x00A8D0A0) +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_31___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_31__VAL___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_GSE_CACHE_DEBUG_ENTRY_31__VAL___S 0 + +#define WMAC0_RXPCU_R1_PHY_ERR_CODE (0x00A8D0A4) +#define WMAC0_RXPCU_R1_PHY_ERR_CODE___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_PHY_ERR_CODE___POR 0x00000000 +#define WMAC0_RXPCU_R1_PHY_ERR_CODE__PHYRX_ABORT_REASON___POR 0x00 +#define WMAC0_RXPCU_R1_PHY_ERR_CODE__PHYRX_ABORT_REASON___M 0x000000FF +#define WMAC0_RXPCU_R1_PHY_ERR_CODE__PHYRX_ABORT_REASON___S 0 +#define WMAC0_RXPCU_R1_PHY_ERR_CODE___M 0x000000FF +#define WMAC0_RXPCU_R1_PHY_ERR_CODE___S 0 + +#define WMAC0_RXPCU_R1_TESTBUS_CTRL (0x00A8D0A8) +#define WMAC0_RXPCU_R1_TESTBUS_CTRL___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_TESTBUS_CTRL___POR 0x00000000 +#define WMAC0_RXPCU_R1_TESTBUS_CTRL__GSE_SEL___POR 0x0 +#define WMAC0_RXPCU_R1_TESTBUS_CTRL__SEL_HIGH___POR 0x0 +#define WMAC0_RXPCU_R1_TESTBUS_CTRL__REARRAGE_EN___POR 0x0 +#define WMAC0_RXPCU_R1_TESTBUS_CTRL__REARRANGED_FORMAT___POR 0x0 +#define WMAC0_RXPCU_R1_TESTBUS_CTRL__SHIFT2___POR 0x0 +#define WMAC0_RXPCU_R1_TESTBUS_CTRL__SEL2___POR 0x00 +#define WMAC0_RXPCU_R1_TESTBUS_CTRL__SHIFT___POR 0x0 +#define WMAC0_RXPCU_R1_TESTBUS_CTRL__SEL___POR 0x00 +#define WMAC0_RXPCU_R1_TESTBUS_CTRL__GSE_SEL___M 0xF0000000 +#define WMAC0_RXPCU_R1_TESTBUS_CTRL__GSE_SEL___S 28 +#define WMAC0_RXPCU_R1_TESTBUS_CTRL__SEL_HIGH___M 0x00800000 +#define WMAC0_RXPCU_R1_TESTBUS_CTRL__SEL_HIGH___S 23 +#define WMAC0_RXPCU_R1_TESTBUS_CTRL__REARRAGE_EN___M 0x00400000 +#define WMAC0_RXPCU_R1_TESTBUS_CTRL__REARRAGE_EN___S 22 +#define WMAC0_RXPCU_R1_TESTBUS_CTRL__REARRANGED_FORMAT___M 0x003C0000 +#define WMAC0_RXPCU_R1_TESTBUS_CTRL__REARRANGED_FORMAT___S 18 +#define WMAC0_RXPCU_R1_TESTBUS_CTRL__SHIFT2___M 0x00038000 +#define WMAC0_RXPCU_R1_TESTBUS_CTRL__SHIFT2___S 15 +#define WMAC0_RXPCU_R1_TESTBUS_CTRL__SEL2___M 0x00007E00 +#define WMAC0_RXPCU_R1_TESTBUS_CTRL__SEL2___S 9 +#define WMAC0_RXPCU_R1_TESTBUS_CTRL__SHIFT___M 0x000001C0 +#define WMAC0_RXPCU_R1_TESTBUS_CTRL__SHIFT___S 6 +#define WMAC0_RXPCU_R1_TESTBUS_CTRL__SEL___M 0x0000003F +#define WMAC0_RXPCU_R1_TESTBUS_CTRL__SEL___S 0 +#define WMAC0_RXPCU_R1_TESTBUS_CTRL___M 0xF0FFFFFF +#define WMAC0_RXPCU_R1_TESTBUS_CTRL___S 0 + +#define WMAC0_RXPCU_R1_TESTBUS_UPPER_STATUS (0x00A8D0AC) +#define WMAC0_RXPCU_R1_TESTBUS_UPPER_STATUS___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_TESTBUS_UPPER_STATUS___POR 0x00000000 +#define WMAC0_RXPCU_R1_TESTBUS_UPPER_STATUS__VALUE___POR 0x00 +#define WMAC0_RXPCU_R1_TESTBUS_UPPER_STATUS__VALUE___M 0x000000FF +#define WMAC0_RXPCU_R1_TESTBUS_UPPER_STATUS__VALUE___S 0 +#define WMAC0_RXPCU_R1_TESTBUS_UPPER_STATUS___M 0x000000FF +#define WMAC0_RXPCU_R1_TESTBUS_UPPER_STATUS___S 0 + +#define WMAC0_RXPCU_R1_TESTBUS_LOWER_STATUS (0x00A8D0B0) +#define WMAC0_RXPCU_R1_TESTBUS_LOWER_STATUS___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_TESTBUS_LOWER_STATUS___POR 0x00000000 +#define WMAC0_RXPCU_R1_TESTBUS_LOWER_STATUS__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R1_TESTBUS_LOWER_STATUS__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_TESTBUS_LOWER_STATUS__VALUE___S 0 +#define WMAC0_RXPCU_R1_TESTBUS_LOWER_STATUS___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_TESTBUS_LOWER_STATUS___S 0 + +#define WMAC0_RXPCU_R1_FSM_STATUS_0 (0x00A8D0B4) +#define WMAC0_RXPCU_R1_FSM_STATUS_0___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_FSM_STATUS_0___POR 0x00000000 +#define WMAC0_RXPCU_R1_FSM_STATUS_0__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R1_FSM_STATUS_0__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_FSM_STATUS_0__VALUE___S 0 +#define WMAC0_RXPCU_R1_FSM_STATUS_0___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_FSM_STATUS_0___S 0 + +#define WMAC0_RXPCU_R1_FSM_STATUS_1 (0x00A8D0B8) +#define WMAC0_RXPCU_R1_FSM_STATUS_1___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_FSM_STATUS_1___POR 0x00000000 +#define WMAC0_RXPCU_R1_FSM_STATUS_1__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R1_FSM_STATUS_1__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_FSM_STATUS_1__VALUE___S 0 +#define WMAC0_RXPCU_R1_FSM_STATUS_1___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_FSM_STATUS_1___S 0 + +#define WMAC0_RXPCU_R1_FSM_STATUS_2 (0x00A8D0BC) +#define WMAC0_RXPCU_R1_FSM_STATUS_2___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_FSM_STATUS_2___POR 0x00000000 +#define WMAC0_RXPCU_R1_FSM_STATUS_2__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R1_FSM_STATUS_2__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_FSM_STATUS_2__VALUE___S 0 +#define WMAC0_RXPCU_R1_FSM_STATUS_2___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_FSM_STATUS_2___S 0 + +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_RSSI_LEGACY_CNT (0x00A8D0C0) +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_RSSI_LEGACY_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_RSSI_LEGACY_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_RSSI_LEGACY_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_RSSI_LEGACY_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_RSSI_LEGACY_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_RSSI_LEGACY_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_RSSI_LEGACY_CNT___S 0 + +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_PKT_END_CNT (0x00A8D0C4) +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_PKT_END_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_PKT_END_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_PKT_END_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_PKT_END_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_PKT_END_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_PKT_END_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_PKT_END_CNT___S 0 + +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_ABORT_REQUEST_CNT (0x00A8D0C8) +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_ABORT_REQUEST_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_ABORT_REQUEST_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_ABORT_REQUEST_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_ABORT_REQUEST_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_ABORT_REQUEST_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_ABORT_REQUEST_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_ABORT_REQUEST_CNT___S 0 + +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_ABORT_ACK_CNT (0x00A8D0CC) +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_ABORT_ACK_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_ABORT_ACK_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_ABORT_ACK_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_ABORT_ACK_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_ABORT_ACK_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_ABORT_ACK_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_ABORT_ACK_CNT___S 0 + +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_MACRX_ABORT_REQUEST_CNT (0x00A8D0D0) +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_MACRX_ABORT_REQUEST_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_MACRX_ABORT_REQUEST_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_MACRX_ABORT_REQUEST_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_MACRX_ABORT_REQUEST_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_MACRX_ABORT_REQUEST_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_MACRX_ABORT_REQUEST_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_MACRX_ABORT_REQUEST_CNT___S 0 + +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_MACRX_ABORT_ACK_CNT (0x00A8D0D4) +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_MACRX_ABORT_ACK_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_MACRX_ABORT_ACK_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_MACRX_ABORT_ACK_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_MACRX_ABORT_ACK_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_MACRX_ABORT_ACK_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_MACRX_ABORT_ACK_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_MACRX_ABORT_ACK_CNT___S 0 + +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_DATA_CNT (0x00A8D0D8) +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_DATA_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_DATA_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_DATA_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_DATA_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_DATA_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_DATA_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_PHYRX_DATA_CNT___S 0 + +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11B_PKT_CNT (0x00A8D0DC) +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11B_PKT_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11B_PKT_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11B_PKT_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11B_PKT_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11B_PKT_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11B_PKT_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11B_PKT_CNT___S 0 + +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11A_PKT_CNT (0x00A8D0E0) +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11A_PKT_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11A_PKT_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11A_PKT_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11A_PKT_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11A_PKT_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11A_PKT_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11A_PKT_CNT___S 0 + +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11N_PKT_CNT (0x00A8D0E4) +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11N_PKT_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11N_PKT_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11N_PKT_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11N_PKT_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11N_PKT_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11N_PKT_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11N_PKT_CNT___S 0 + +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AC_SU_PKT_CNT (0x00A8D0E8) +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AC_SU_PKT_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AC_SU_PKT_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AC_SU_PKT_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AC_SU_PKT_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AC_SU_PKT_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AC_SU_PKT_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AC_SU_PKT_CNT___S 0 + +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AC_MU_PKT_CNT (0x00A8D0EC) +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AC_MU_PKT_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AC_MU_PKT_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AC_MU_PKT_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AC_MU_PKT_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AC_MU_PKT_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AC_MU_PKT_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AC_MU_PKT_CNT___S 0 + +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_SU_PKT_CNT (0x00A8D0F0) +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_SU_PKT_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_SU_PKT_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_SU_PKT_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_SU_PKT_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_SU_PKT_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_SU_PKT_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_SU_PKT_CNT___S 0 + +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_DL_MU_PKT_CNT (0x00A8D0F4) +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_DL_MU_PKT_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_DL_MU_PKT_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_DL_MU_PKT_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_DL_MU_PKT_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_DL_MU_PKT_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_DL_MU_PKT_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_DL_MU_PKT_CNT___S 0 + +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_UL_MU_PKT_CNT (0x00A8D0F8) +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_UL_MU_PKT_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_UL_MU_PKT_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_UL_MU_PKT_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_UL_MU_PKT_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_UL_MU_PKT_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_UL_MU_PKT_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_PKT_11AX_UL_MU_PKT_CNT___S 0 + +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_RCVD (0x00A8D0FC) +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_RCVD___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_RCVD___POR 0x00000000 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_RCVD__BITMAP_PREVIOUS___POR 0x0000 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_RCVD__BITMAP_CURRENT___POR 0x0000 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_RCVD__BITMAP_PREVIOUS___M 0xFFFF0000 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_RCVD__BITMAP_PREVIOUS___S 16 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_RCVD__BITMAP_CURRENT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_RCVD__BITMAP_CURRENT___S 0 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_RCVD___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_RCVD___S 0 + +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_EXPECTED_RESPONSE_CNT (0x00A8D100) +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_EXPECTED_RESPONSE_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_EXPECTED_RESPONSE_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_EXPECTED_RESPONSE_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_EXPECTED_RESPONSE_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_EXPECTED_RESPONSE_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_EXPECTED_RESPONSE_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_EXPECTED_RESPONSE_CNT___S 0 + +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_RECEIVED_RESPONSE_INFO_CNT (0x00A8D104) +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_RECEIVED_RESPONSE_INFO_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_RECEIVED_RESPONSE_INFO_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_RECEIVED_RESPONSE_INFO_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_RECEIVED_RESPONSE_INFO_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_RECEIVED_RESPONSE_INFO_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_RECEIVED_RESPONSE_INFO_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_RECEIVED_RESPONSE_INFO_CNT___S 0 + +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_RX_RESPONSE_REQUIRED_INFO_CNT (0x00A8D108) +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_RX_RESPONSE_REQUIRED_INFO_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_RX_RESPONSE_REQUIRED_INFO_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_RX_RESPONSE_REQUIRED_INFO_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_RX_RESPONSE_REQUIRED_INFO_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_RX_RESPONSE_REQUIRED_INFO_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_RX_RESPONSE_REQUIRED_INFO_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_RX_RESPONSE_REQUIRED_INFO_CNT___S 0 + +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_TX_CBF_INFO_CNT (0x00A8D10C) +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_TX_CBF_INFO_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_TX_CBF_INFO_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_TX_CBF_INFO_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_TX_CBF_INFO_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_TX_CBF_INFO_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_TX_CBF_INFO_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_TX_CBF_INFO_CNT___S 0 + +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_REQ_IMPLICIT_FB_CNT (0x00A8D110) +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_REQ_IMPLICIT_FB_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_REQ_IMPLICIT_FB_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_REQ_IMPLICIT_FB_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_REQ_IMPLICIT_FB_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_REQ_IMPLICIT_FB_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_REQ_IMPLICIT_FB_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_REQ_IMPLICIT_FB_CNT___S 0 + +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_NDP_TIMEOUT_CNT (0x00A8D114) +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_NDP_TIMEOUT_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_NDP_TIMEOUT_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_NDP_TIMEOUT_CNT__NDP_TIMEOUT_CNT___POR 0x0000 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_NDP_TIMEOUT_CNT__NDP_TIMEOUT_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_NDP_TIMEOUT_CNT__NDP_TIMEOUT_CNT___S 0 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_NDP_TIMEOUT_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_NDP_TIMEOUT_CNT___S 0 + +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_EXPECT_NDP_RECEPTION_CNT (0x00A8D118) +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_EXPECT_NDP_RECEPTION_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_EXPECT_NDP_RECEPTION_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_EXPECT_NDP_RECEPTION_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_EXPECT_NDP_RECEPTION_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_EXPECT_NDP_RECEPTION_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_EXPECT_NDP_RECEPTION_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_EXPECT_NDP_RECEPTION_CNT___S 0 + +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_FREEZE_CAPTURE_CHANNEL_CNT (0x00A8D11C) +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_FREEZE_CAPTURE_CHANNEL_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_FREEZE_CAPTURE_CHANNEL_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_FREEZE_CAPTURE_CHANNEL_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_FREEZE_CAPTURE_CHANNEL_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_FREEZE_CAPTURE_CHANNEL_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_FREEZE_CAPTURE_CHANNEL_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_FREEZE_CAPTURE_CHANNEL_CNT___S 0 + +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_CHAIN_MASK_CNT (0x00A8D120) +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_CHAIN_MASK_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_CHAIN_MASK_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_CHAIN_MASK_CNT__SINGLE_CHAIN_CNT___POR 0x00 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_CHAIN_MASK_CNT__FULL_CHAIN_CNT___POR 0x00 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_CHAIN_MASK_CNT__ANT_SEL_CNT___POR 0x00 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_CHAIN_MASK_CNT__SINGLE_CHAIN_CNT___M 0x00FF0000 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_CHAIN_MASK_CNT__SINGLE_CHAIN_CNT___S 16 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_CHAIN_MASK_CNT__FULL_CHAIN_CNT___M 0x0000FF00 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_CHAIN_MASK_CNT__FULL_CHAIN_CNT___S 8 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_CHAIN_MASK_CNT__ANT_SEL_CNT___M 0x000000FF +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_CHAIN_MASK_CNT__ANT_SEL_CNT___S 0 +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_CHAIN_MASK_CNT___M 0x00FFFFFF +#define WMAC0_RXPCU_R1_PHY_INTF_TLV_CHAIN_MASK_CNT___S 0 + +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_NAP_CNT (0x00A8D124) +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_NAP_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_NAP_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_NAP_CNT__VALUE___POR 0x00 +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_NAP_CNT__VALUE___M 0x000000FF +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_NAP_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_NAP_CNT___M 0x000000FF +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_NAP_CNT___S 0 + +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_OFF_CNT (0x00A8D128) +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_OFF_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_OFF_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_OFF_CNT__VALUE___POR 0x00 +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_OFF_CNT__VALUE___M 0x000000FF +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_OFF_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_OFF_CNT___M 0x000000FF +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_OFF_CNT___S 0 + +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_ON_CNT (0x00A8D12C) +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_ON_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_ON_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_ON_CNT__VALUE___POR 0x00 +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_ON_CNT__VALUE___M 0x000000FF +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_ON_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_ON_CNT___M 0x000000FF +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_PHY_ON_CNT___S 0 + +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_SYNTH_OFF_CNT (0x00A8D130) +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_SYNTH_OFF_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_SYNTH_OFF_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_SYNTH_OFF_CNT__VALUE___POR 0x00 +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_SYNTH_OFF_CNT__VALUE___M 0x000000FF +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_SYNTH_OFF_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_SYNTH_OFF_CNT___M 0x000000FF +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_SYNTH_OFF_CNT___S 0 + +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_SYNTH_ON_CNT (0x00A8D134) +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_SYNTH_ON_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_SYNTH_ON_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_SYNTH_ON_CNT__VALUE___POR 0x00 +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_SYNTH_ON_CNT__VALUE___M 0x000000FF +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_SYNTH_ON_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_SYNTH_ON_CNT___M 0x000000FF +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_SYNTH_ON_CNT___S 0 + +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_BITMAP (0x00A8D138) +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_BITMAP___RWC QCSR_REG_RO +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_BITMAP___POR 0x00000000 +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_BITMAP__BITMAP___POR 0x00000000 +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_BITMAP__BITMAP___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_BITMAP__BITMAP___S 0 +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_BITMAP___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_TXPCU_INTF_TLV_BITMAP___S 0 + +#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_MPDU_END_CNT (0x00A8D13C) +#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_MPDU_END_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_MPDU_END_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_MPDU_END_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_MPDU_END_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_MPDU_END_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_MPDU_END_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_MPDU_END_CNT___S 0 + +#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_MPDU_PCU_START_CNT (0x00A8D140) +#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_MPDU_PCU_START_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_MPDU_PCU_START_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_MPDU_PCU_START_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_MPDU_PCU_START_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_MPDU_PCU_START_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_MPDU_PCU_START_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_MPDU_PCU_START_CNT___S 0 + +#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_PPDU_END_CNT (0x00A8D144) +#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_PPDU_END_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_PPDU_END_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_PPDU_END_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_PPDU_END_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_PPDU_END_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_PPDU_END_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_PPDU_END_CNT___S 0 + +#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_PPDU_START_CNT (0x00A8D148) +#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_PPDU_START_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_PPDU_START_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_PPDU_START_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_PPDU_START_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_PPDU_START_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_PPDU_START_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_CRYPTO_INTF_TLV_RX_PPDU_START_CNT___S 0 + +#define WMAC0_RXPCU_R1_PKT_DEBUG_NDPA_RCVD_CNT (0x00A8D14C) +#define WMAC0_RXPCU_R1_PKT_DEBUG_NDPA_RCVD_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_PKT_DEBUG_NDPA_RCVD_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_PKT_DEBUG_NDPA_RCVD_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R1_PKT_DEBUG_NDPA_RCVD_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PKT_DEBUG_NDPA_RCVD_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_PKT_DEBUG_NDPA_RCVD_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PKT_DEBUG_NDPA_RCVD_CNT___S 0 + +#define WMAC0_RXPCU_R1_PKT_DEBUG_TRIGGER_RCVD_CNT (0x00A8D150) +#define WMAC0_RXPCU_R1_PKT_DEBUG_TRIGGER_RCVD_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_PKT_DEBUG_TRIGGER_RCVD_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_PKT_DEBUG_TRIGGER_RCVD_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R1_PKT_DEBUG_TRIGGER_RCVD_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PKT_DEBUG_TRIGGER_RCVD_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_PKT_DEBUG_TRIGGER_RCVD_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PKT_DEBUG_TRIGGER_RCVD_CNT___S 0 + +#define WMAC0_RXPCU_R1_PKT_DEBUG_MPDU_CNT (0x00A8D154) +#define WMAC0_RXPCU_R1_PKT_DEBUG_MPDU_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_PKT_DEBUG_MPDU_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_PKT_DEBUG_MPDU_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R1_PKT_DEBUG_MPDU_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PKT_DEBUG_MPDU_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_PKT_DEBUG_MPDU_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PKT_DEBUG_MPDU_CNT___S 0 + +#define WMAC0_RXPCU_R1_PKT_DEBUG_AMPDU_CNT (0x00A8D158) +#define WMAC0_RXPCU_R1_PKT_DEBUG_AMPDU_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_PKT_DEBUG_AMPDU_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_PKT_DEBUG_AMPDU_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R1_PKT_DEBUG_AMPDU_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PKT_DEBUG_AMPDU_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_PKT_DEBUG_AMPDU_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PKT_DEBUG_AMPDU_CNT___S 0 + +#define WMAC0_RXPCU_R1_PKT_DEBUG_FILTER_IN_CNT (0x00A8D15C) +#define WMAC0_RXPCU_R1_PKT_DEBUG_FILTER_IN_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_PKT_DEBUG_FILTER_IN_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_PKT_DEBUG_FILTER_IN_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R1_PKT_DEBUG_FILTER_IN_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PKT_DEBUG_FILTER_IN_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_PKT_DEBUG_FILTER_IN_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PKT_DEBUG_FILTER_IN_CNT___S 0 + +#define WMAC0_RXPCU_R1_PKT_DEBUG_FILTER_OUT_CNT (0x00A8D160) +#define WMAC0_RXPCU_R1_PKT_DEBUG_FILTER_OUT_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_PKT_DEBUG_FILTER_OUT_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_PKT_DEBUG_FILTER_OUT_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R1_PKT_DEBUG_FILTER_OUT_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PKT_DEBUG_FILTER_OUT_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_PKT_DEBUG_FILTER_OUT_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_PKT_DEBUG_FILTER_OUT_CNT___S 0 + +#define WMAC0_RXPCU_R1_PKT_DEBUG_OVERFLOW_CNT (0x00A8D164) +#define WMAC0_RXPCU_R1_PKT_DEBUG_OVERFLOW_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_PKT_DEBUG_OVERFLOW_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_PKT_DEBUG_OVERFLOW_CNT__VALUE___POR 0x00 +#define WMAC0_RXPCU_R1_PKT_DEBUG_OVERFLOW_CNT__VALUE___M 0x000000FF +#define WMAC0_RXPCU_R1_PKT_DEBUG_OVERFLOW_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_PKT_DEBUG_OVERFLOW_CNT___M 0x000000FF +#define WMAC0_RXPCU_R1_PKT_DEBUG_OVERFLOW_CNT___S 0 + +#define WMAC0_RXPCU_R1_TRC_EVENTMASK_IX_0 (0x00A8D168) +#define WMAC0_RXPCU_R1_TRC_EVENTMASK_IX_0___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_TRC_EVENTMASK_IX_0___POR 0x00000000 +#define WMAC0_RXPCU_R1_TRC_EVENTMASK_IX_0__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R1_TRC_EVENTMASK_IX_0__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_TRC_EVENTMASK_IX_0__VALUE___S 0 +#define WMAC0_RXPCU_R1_TRC_EVENTMASK_IX_0___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_TRC_EVENTMASK_IX_0___S 0 + +#define WMAC0_RXPCU_R1_TRC_EVENTMASK_IX_1 (0x00A8D16C) +#define WMAC0_RXPCU_R1_TRC_EVENTMASK_IX_1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_TRC_EVENTMASK_IX_1___POR 0x00000000 +#define WMAC0_RXPCU_R1_TRC_EVENTMASK_IX_1__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R1_TRC_EVENTMASK_IX_1__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_TRC_EVENTMASK_IX_1__VALUE___S 0 +#define WMAC0_RXPCU_R1_TRC_EVENTMASK_IX_1___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_TRC_EVENTMASK_IX_1___S 0 + +#define WMAC0_RXPCU_R1_EVENT_BUS_CFG1 (0x00A8D170) +#define WMAC0_RXPCU_R1_EVENT_BUS_CFG1___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_EVENT_BUS_CFG1___POR 0x00000032 +#define WMAC0_RXPCU_R1_EVENT_BUS_CFG1__DRAIN_THRESH___POR 0x32 +#define WMAC0_RXPCU_R1_EVENT_BUS_CFG1__DRAIN_THRESH___M 0x000000FF +#define WMAC0_RXPCU_R1_EVENT_BUS_CFG1__DRAIN_THRESH___S 0 +#define WMAC0_RXPCU_R1_EVENT_BUS_CFG1___M 0x000000FF +#define WMAC0_RXPCU_R1_EVENT_BUS_CFG1___S 0 + +#define WMAC0_RXPCU_R1_CMNTRIG_CFG (0x00A8D174) +#define WMAC0_RXPCU_R1_CMNTRIG_CFG___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_CMNTRIG_CFG___POR 0x00000000 +#define WMAC0_RXPCU_R1_CMNTRIG_CFG__TESTBUS_SEL___POR 0x0 +#define WMAC0_RXPCU_R1_CMNTRIG_CFG__SEL___POR 0x00 +#define WMAC0_RXPCU_R1_CMNTRIG_CFG__TESTBUS_SEL___M 0x00000700 +#define WMAC0_RXPCU_R1_CMNTRIG_CFG__TESTBUS_SEL___S 8 +#define WMAC0_RXPCU_R1_CMNTRIG_CFG__SEL___M 0x000000FF +#define WMAC0_RXPCU_R1_CMNTRIG_CFG__SEL___S 0 +#define WMAC0_RXPCU_R1_CMNTRIG_CFG___M 0x000007FF +#define WMAC0_RXPCU_R1_CMNTRIG_CFG___S 0 + +#define WMAC0_RXPCU_R1_CMNTRIG_MASK_L32 (0x00A8D178) +#define WMAC0_RXPCU_R1_CMNTRIG_MASK_L32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_CMNTRIG_MASK_L32___POR 0x00000000 +#define WMAC0_RXPCU_R1_CMNTRIG_MASK_L32__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R1_CMNTRIG_MASK_L32__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_CMNTRIG_MASK_L32__VALUE___S 0 +#define WMAC0_RXPCU_R1_CMNTRIG_MASK_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_CMNTRIG_MASK_L32___S 0 + +#define WMAC0_RXPCU_R1_CMNTRIG_MASK_U07 (0x00A8D17C) +#define WMAC0_RXPCU_R1_CMNTRIG_MASK_U07___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_CMNTRIG_MASK_U07___POR 0x00000000 +#define WMAC0_RXPCU_R1_CMNTRIG_MASK_U07__VALUE___POR 0x00 +#define WMAC0_RXPCU_R1_CMNTRIG_MASK_U07__VALUE___M 0x0000007F +#define WMAC0_RXPCU_R1_CMNTRIG_MASK_U07__VALUE___S 0 +#define WMAC0_RXPCU_R1_CMNTRIG_MASK_U07___M 0x0000007F +#define WMAC0_RXPCU_R1_CMNTRIG_MASK_U07___S 0 + +#define WMAC0_RXPCU_R1_CMNTRIG_MATCH_L32 (0x00A8D180) +#define WMAC0_RXPCU_R1_CMNTRIG_MATCH_L32___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_CMNTRIG_MATCH_L32___POR 0x00000000 +#define WMAC0_RXPCU_R1_CMNTRIG_MATCH_L32__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R1_CMNTRIG_MATCH_L32__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_CMNTRIG_MATCH_L32__VALUE___S 0 +#define WMAC0_RXPCU_R1_CMNTRIG_MATCH_L32___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_CMNTRIG_MATCH_L32___S 0 + +#define WMAC0_RXPCU_R1_CMNTRIG_MATCH_U07 (0x00A8D184) +#define WMAC0_RXPCU_R1_CMNTRIG_MATCH_U07___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_CMNTRIG_MATCH_U07___POR 0x00000000 +#define WMAC0_RXPCU_R1_CMNTRIG_MATCH_U07__VALUE___POR 0x00 +#define WMAC0_RXPCU_R1_CMNTRIG_MATCH_U07__VALUE___M 0x0000007F +#define WMAC0_RXPCU_R1_CMNTRIG_MATCH_U07__VALUE___S 0 +#define WMAC0_RXPCU_R1_CMNTRIG_MATCH_U07___M 0x0000007F +#define WMAC0_RXPCU_R1_CMNTRIG_MATCH_U07___S 0 + +#define WMAC0_RXPCU_R1_FCS_PASS_AMPDU (0x00A8D188) +#define WMAC0_RXPCU_R1_FCS_PASS_AMPDU___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_FCS_PASS_AMPDU___POR 0x00000000 +#define WMAC0_RXPCU_R1_FCS_PASS_AMPDU__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R1_FCS_PASS_AMPDU__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_FCS_PASS_AMPDU__VALUE___S 0 +#define WMAC0_RXPCU_R1_FCS_PASS_AMPDU___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_FCS_PASS_AMPDU___S 0 + +#define WMAC0_RXPCU_R1_FCS_PASS_NON_AMPDU (0x00A8D18C) +#define WMAC0_RXPCU_R1_FCS_PASS_NON_AMPDU___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_FCS_PASS_NON_AMPDU___POR 0x00000000 +#define WMAC0_RXPCU_R1_FCS_PASS_NON_AMPDU__VALUE___POR 0x00000000 +#define WMAC0_RXPCU_R1_FCS_PASS_NON_AMPDU__VALUE___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_FCS_PASS_NON_AMPDU__VALUE___S 0 +#define WMAC0_RXPCU_R1_FCS_PASS_NON_AMPDU___M 0xFFFFFFFF +#define WMAC0_RXPCU_R1_FCS_PASS_NON_AMPDU___S 0 + +#define WMAC0_RXPCU_R1_GP_ACK_CNT (0x00A8D190) +#define WMAC0_RXPCU_R1_GP_ACK_CNT___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_GP_ACK_CNT___POR 0x00000000 +#define WMAC0_RXPCU_R1_GP_ACK_CNT__VALUE___POR 0x0000 +#define WMAC0_RXPCU_R1_GP_ACK_CNT__VALUE___M 0x0000FFFF +#define WMAC0_RXPCU_R1_GP_ACK_CNT__VALUE___S 0 +#define WMAC0_RXPCU_R1_GP_ACK_CNT___M 0x0000FFFF +#define WMAC0_RXPCU_R1_GP_ACK_CNT___S 0 + +#define WMAC0_RXPCU_R1_PMI_ERROR_STATUS (0x00A8D194) +#define WMAC0_RXPCU_R1_PMI_ERROR_STATUS___RWC QCSR_REG_RW +#define WMAC0_RXPCU_R1_PMI_ERROR_STATUS___POR 0x00000000 +#define WMAC0_RXPCU_R1_PMI_ERROR_STATUS__TLV_TAG_LENGTH_ERROR___POR 0x0 +#define WMAC0_RXPCU_R1_PMI_ERROR_STATUS__TLV_LENGTH_ERROR___POR 0x0 +#define WMAC0_RXPCU_R1_PMI_ERROR_STATUS__TLV_OOR___POR 0x0 +#define WMAC0_RXPCU_R1_PMI_ERROR_STATUS__PHY_PPDU_ID___POR 0x00 +#define WMAC0_RXPCU_R1_PMI_ERROR_STATUS__NEW_TLV_TAG___POR 0x000 +#define WMAC0_RXPCU_R1_PMI_ERROR_STATUS__NEW_TLV_CFLAG___POR 0x0 +#define WMAC0_RXPCU_R1_PMI_ERROR_STATUS__CUR_TLV_TAG___POR 0x000 +#define WMAC0_RXPCU_R1_PMI_ERROR_STATUS__CUR_TLV_CFLAG___POR 0x0 +#define WMAC0_RXPCU_R1_PMI_ERROR_STATUS__TLV_TAG_LENGTH_ERROR___M 0x40000000 +#define WMAC0_RXPCU_R1_PMI_ERROR_STATUS__TLV_TAG_LENGTH_ERROR___S 30 +#define WMAC0_RXPCU_R1_PMI_ERROR_STATUS__TLV_LENGTH_ERROR___M 0x20000000 +#define WMAC0_RXPCU_R1_PMI_ERROR_STATUS__TLV_LENGTH_ERROR___S 29 +#define WMAC0_RXPCU_R1_PMI_ERROR_STATUS__TLV_OOR___M 0x10000000 +#define WMAC0_RXPCU_R1_PMI_ERROR_STATUS__TLV_OOR___S 28 +#define WMAC0_RXPCU_R1_PMI_ERROR_STATUS__PHY_PPDU_ID___M 0x0FF00000 +#define WMAC0_RXPCU_R1_PMI_ERROR_STATUS__PHY_PPDU_ID___S 20 +#define WMAC0_RXPCU_R1_PMI_ERROR_STATUS__NEW_TLV_TAG___M 0x000FF800 +#define WMAC0_RXPCU_R1_PMI_ERROR_STATUS__NEW_TLV_TAG___S 11 +#define WMAC0_RXPCU_R1_PMI_ERROR_STATUS__NEW_TLV_CFLAG___M 0x00000400 +#define WMAC0_RXPCU_R1_PMI_ERROR_STATUS__NEW_TLV_CFLAG___S 10 +#define WMAC0_RXPCU_R1_PMI_ERROR_STATUS__CUR_TLV_TAG___M 0x000003FE +#define WMAC0_RXPCU_R1_PMI_ERROR_STATUS__CUR_TLV_TAG___S 1 +#define WMAC0_RXPCU_R1_PMI_ERROR_STATUS__CUR_TLV_CFLAG___M 0x00000001 +#define WMAC0_RXPCU_R1_PMI_ERROR_STATUS__CUR_TLV_CFLAG___S 0 +#define WMAC0_RXPCU_R1_PMI_ERROR_STATUS___M 0x7FFFFFFF +#define WMAC0_RXPCU_R1_PMI_ERROR_STATUS___S 0 + +#define WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS (0x00A8F000) +#define WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS___POR 0x30301919 +#define WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS__RX_FRAME_CTS_TIMEOUT___POR 0x30 +#define WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS__RX_FRAME_ACK_TIMEOUT___POR 0x30 +#define WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS__PRE_RX_FRAME_CTS_TIMEOUT___POR 0x19 +#define WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS__PRE_RX_FRAME_ACK_TIMEOUT___POR 0x19 +#define WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS__RX_FRAME_CTS_TIMEOUT___M 0xFF000000 +#define WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS__RX_FRAME_CTS_TIMEOUT___S 24 +#define WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS__RX_FRAME_ACK_TIMEOUT___M 0x00FF0000 +#define WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS__RX_FRAME_ACK_TIMEOUT___S 16 +#define WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS__PRE_RX_FRAME_CTS_TIMEOUT___M 0x0000FF00 +#define WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS__PRE_RX_FRAME_CTS_TIMEOUT___S 8 +#define WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS__PRE_RX_FRAME_ACK_TIMEOUT___M 0x000000FF +#define WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS__PRE_RX_FRAME_ACK_TIMEOUT___S 0 +#define WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_TIMEOUT_ACK_CTS___S 0 + +#define WMAC0_TXPCU_R0_TIMEOUT_CBF (0x00A8F004) +#define WMAC0_TXPCU_R0_TIMEOUT_CBF___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_TIMEOUT_CBF___POR 0x00004019 +#define WMAC0_TXPCU_R0_TIMEOUT_CBF__RX_FRAME_CBF_TIMEOUT___POR 0x40 +#define WMAC0_TXPCU_R0_TIMEOUT_CBF__PRE_RX_FRAME_CBF_TIMEOUT___POR 0x19 +#define WMAC0_TXPCU_R0_TIMEOUT_CBF__RX_FRAME_CBF_TIMEOUT___M 0x0000FF00 +#define WMAC0_TXPCU_R0_TIMEOUT_CBF__RX_FRAME_CBF_TIMEOUT___S 8 +#define WMAC0_TXPCU_R0_TIMEOUT_CBF__PRE_RX_FRAME_CBF_TIMEOUT___M 0x000000FF +#define WMAC0_TXPCU_R0_TIMEOUT_CBF__PRE_RX_FRAME_CBF_TIMEOUT___S 0 +#define WMAC0_TXPCU_R0_TIMEOUT_CBF___M 0x0000FFFF +#define WMAC0_TXPCU_R0_TIMEOUT_CBF___S 0 + +#define WMAC0_TXPCU_R0_RESPONSE_TIMEOUT (0x00A8F008) +#define WMAC0_TXPCU_R0_RESPONSE_TIMEOUT___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESPONSE_TIMEOUT___POR 0x0014000E +#define WMAC0_TXPCU_R0_RESPONSE_TIMEOUT__GLOBAL_TIMEOUT___POR 0x1400 +#define WMAC0_TXPCU_R0_RESPONSE_TIMEOUT__RX_FRAME_TO_RXPCU_RESP___POR 0x0E +#define WMAC0_TXPCU_R0_RESPONSE_TIMEOUT__GLOBAL_TIMEOUT___M 0x00FFFF00 +#define WMAC0_TXPCU_R0_RESPONSE_TIMEOUT__GLOBAL_TIMEOUT___S 8 +#define WMAC0_TXPCU_R0_RESPONSE_TIMEOUT__RX_FRAME_TO_RXPCU_RESP___M 0x000000FF +#define WMAC0_TXPCU_R0_RESPONSE_TIMEOUT__RX_FRAME_TO_RXPCU_RESP___S 0 +#define WMAC0_TXPCU_R0_RESPONSE_TIMEOUT___M 0x00FFFFFF +#define WMAC0_TXPCU_R0_RESPONSE_TIMEOUT___S 0 + +#define WMAC0_TXPCU_R0_WUR_CONTROL (0x00A8F00C) +#define WMAC0_TXPCU_R0_WUR_CONTROL___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_WUR_CONTROL___POR 0x00050000 +#define WMAC0_TXPCU_R0_WUR_CONTROL__PARTIAL_TSF_LSB___POR 0x05 +#define WMAC0_TXPCU_R0_WUR_CONTROL__INVALID_TSF_OFFSET___POR 0x0 +#define WMAC0_TXPCU_R0_WUR_CONTROL__LATENCY_ADD_SEL___POR 0x0 +#define WMAC0_TXPCU_R0_WUR_CONTROL__PHY_WUR_TX_LATENCY___POR 0x00 +#define WMAC0_TXPCU_R0_WUR_CONTROL__PARTIAL_TSF_LSB___M 0x003F0000 +#define WMAC0_TXPCU_R0_WUR_CONTROL__PARTIAL_TSF_LSB___S 16 +#define WMAC0_TXPCU_R0_WUR_CONTROL__INVALID_TSF_OFFSET___M 0x00001000 +#define WMAC0_TXPCU_R0_WUR_CONTROL__INVALID_TSF_OFFSET___S 12 +#define WMAC0_TXPCU_R0_WUR_CONTROL__LATENCY_ADD_SEL___M 0x00000100 +#define WMAC0_TXPCU_R0_WUR_CONTROL__LATENCY_ADD_SEL___S 8 +#define WMAC0_TXPCU_R0_WUR_CONTROL__PHY_WUR_TX_LATENCY___M 0x000000FF +#define WMAC0_TXPCU_R0_WUR_CONTROL__PHY_WUR_TX_LATENCY___S 0 +#define WMAC0_TXPCU_R0_WUR_CONTROL___M 0x003F11FF +#define WMAC0_TXPCU_R0_WUR_CONTROL___S 0 + +#define WMAC0_TXPCU_R0_WATCHDOG (0x00A8F010) +#define WMAC0_TXPCU_R0_WATCHDOG___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_WATCHDOG___POR 0x00002710 +#define WMAC0_TXPCU_R0_WATCHDOG__STATUS___POR 0x0000 +#define WMAC0_TXPCU_R0_WATCHDOG__LIMIT___POR 0x2710 +#define WMAC0_TXPCU_R0_WATCHDOG__STATUS___M 0xFFFF0000 +#define WMAC0_TXPCU_R0_WATCHDOG__STATUS___S 16 +#define WMAC0_TXPCU_R0_WATCHDOG__LIMIT___M 0x0000FFFF +#define WMAC0_TXPCU_R0_WATCHDOG__LIMIT___S 0 +#define WMAC0_TXPCU_R0_WATCHDOG___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_WATCHDOG___S 0 + +#define WMAC0_TXPCU_R0_SIFS_TIMEOUT (0x00A8F014) +#define WMAC0_TXPCU_R0_SIFS_TIMEOUT___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_SIFS_TIMEOUT___POR 0x000000FF +#define WMAC0_TXPCU_R0_SIFS_TIMEOUT__WAIT_SIFS___POR 0x0 +#define WMAC0_TXPCU_R0_SIFS_TIMEOUT__VALUE___POR 0xFF +#define WMAC0_TXPCU_R0_SIFS_TIMEOUT__WAIT_SIFS___M 0x00000100 +#define WMAC0_TXPCU_R0_SIFS_TIMEOUT__WAIT_SIFS___S 8 +#define WMAC0_TXPCU_R0_SIFS_TIMEOUT__VALUE___M 0x000000FF +#define WMAC0_TXPCU_R0_SIFS_TIMEOUT__VALUE___S 0 +#define WMAC0_TXPCU_R0_SIFS_TIMEOUT___M 0x000001FF +#define WMAC0_TXPCU_R0_SIFS_TIMEOUT___S 0 + +#define WMAC0_TXPCU_R0_PHY_TX_LATENCY (0x00A8F018) +#define WMAC0_TXPCU_R0_PHY_TX_LATENCY___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PHY_TX_LATENCY___POR 0x00000000 +#define WMAC0_TXPCU_R0_PHY_TX_LATENCY__CLK_FREQ_RATIO_PHY_TO_MAC___POR 0x00 +#define WMAC0_TXPCU_R0_PHY_TX_LATENCY__VALUE___POR 0x00 +#define WMAC0_TXPCU_R0_PHY_TX_LATENCY__CLK_FREQ_RATIO_PHY_TO_MAC___M 0x00003F00 +#define WMAC0_TXPCU_R0_PHY_TX_LATENCY__CLK_FREQ_RATIO_PHY_TO_MAC___S 8 +#define WMAC0_TXPCU_R0_PHY_TX_LATENCY__VALUE___M 0x000000FF +#define WMAC0_TXPCU_R0_PHY_TX_LATENCY__VALUE___S 0 +#define WMAC0_TXPCU_R0_PHY_TX_LATENCY___M 0x00003FFF +#define WMAC0_TXPCU_R0_PHY_TX_LATENCY___S 0 + +#define WMAC0_TXPCU_R0_TX_ANT_CTL (0x00A8F01C) +#define WMAC0_TXPCU_R0_TX_ANT_CTL___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_TX_ANT_CTL___POR 0x80000000 +#define WMAC0_TXPCU_R0_TX_ANT_CTL__RUCKUS_ANT_MODE_SEL___POR 0x1 +#define WMAC0_TXPCU_R0_TX_ANT_CTL__ANTENNA_INFO_SHIFT_FACTOR___POR 0x0 +#define WMAC0_TXPCU_R0_TX_ANT_CTL__DEF_ANT_VALUE___POR 0x000000 +#define WMAC0_TXPCU_R0_TX_ANT_CTL__RUCKUS_ANT_MODE_SEL___M 0x80000000 +#define WMAC0_TXPCU_R0_TX_ANT_CTL__RUCKUS_ANT_MODE_SEL___S 31 +#define WMAC0_TXPCU_R0_TX_ANT_CTL__ANTENNA_INFO_SHIFT_FACTOR___M 0x03000000 +#define WMAC0_TXPCU_R0_TX_ANT_CTL__ANTENNA_INFO_SHIFT_FACTOR___S 24 +#define WMAC0_TXPCU_R0_TX_ANT_CTL__DEF_ANT_VALUE___M 0x00FFFFFF +#define WMAC0_TXPCU_R0_TX_ANT_CTL__DEF_ANT_VALUE___S 0 +#define WMAC0_TXPCU_R0_TX_ANT_CTL___M 0x83FFFFFF +#define WMAC0_TXPCU_R0_TX_ANT_CTL___S 0 + +#define WMAC0_TXPCU_R0_MGMT_SEQ_NUM (0x00A8F020) +#define WMAC0_TXPCU_R0_MGMT_SEQ_NUM___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_MGMT_SEQ_NUM___POR 0x02FF0000 +#define WMAC0_TXPCU_R0_MGMT_SEQ_NUM__MAX___POR 0x2FF +#define WMAC0_TXPCU_R0_MGMT_SEQ_NUM__MIN___POR 0x000 +#define WMAC0_TXPCU_R0_MGMT_SEQ_NUM__MAX___M 0x0FFF0000 +#define WMAC0_TXPCU_R0_MGMT_SEQ_NUM__MAX___S 16 +#define WMAC0_TXPCU_R0_MGMT_SEQ_NUM__MIN___M 0x00000FFF +#define WMAC0_TXPCU_R0_MGMT_SEQ_NUM__MIN___S 0 +#define WMAC0_TXPCU_R0_MGMT_SEQ_NUM___M 0x0FFF0FFF +#define WMAC0_TXPCU_R0_MGMT_SEQ_NUM___S 0 + +#define WMAC0_TXPCU_R0_MISC_MODE (0x00A8F024) +#define WMAC0_TXPCU_R0_MISC_MODE___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_MISC_MODE___POR 0xB01FF20C +#define WMAC0_TXPCU_R0_MISC_MODE__BLOCK_RXPCU_BYPASS_TLVS___POR 0x1 +#define WMAC0_TXPCU_R0_MISC_MODE__GEN_FLUSH_FOR_LATE_TRIG_TLVS___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE__ENABLE_CLNUP_FOR_LATE_TRIG_TLVS___POR 0x1 +#define WMAC0_TXPCU_R0_MISC_MODE__TRIG_RESP_CTS_PKT_TYPE___POR 0x1 +#define WMAC0_TXPCU_R0_MISC_MODE__ENABLE_DEBUG_CLOCK___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE__ENABLE_CV_PERF_BOOST___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE__RX_TX_CONFLICT_DET_EN___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE__DISABLE_DELAYED_SETUP_CLR___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE__TX_RX_CONFLICT_DET_EN___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE__SEND_SIFS_DELAYED___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE__BA_POLICY_FOR_MBA___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE__NULL_DELIM_AFTER_CBF___POR 0x1 +#define WMAC0_TXPCU_R0_MISC_MODE__NULL_DELIM_AFTER_BA___POR 0x1 +#define WMAC0_TXPCU_R0_MISC_MODE__BW_DROP_BEF_SFM___POR 0x1 +#define WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_MBA___POR 0x1 +#define WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_SU_BA___POR 0x1 +#define WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_CBF___POR 0x1 +#define WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_CTS___POR 0x1 +#define WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_BA___POR 0x1 +#define WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_RTT___POR 0x1 +#define WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_ACK___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE__CBF_DETAILS_CLEAR_ON_FLUSH___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE__USE_WARM_TX_SIFS___POR 0x1 +#define WMAC0_TXPCU_R0_MISC_MODE__LOOPBACK_PREAMBLES_TRIG_RESP___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE__LOOPBACK_PREAMBLES_SELF_GEN___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE__LOOPBACK_PREAMBLES_PPDU___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE__LOOPBACK_PREAMBLES_PROT___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE__BLOCK_RESP_FRAMES___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE__MIMIC_PHY_SOFT_ABORT___POR 0x1 +#define WMAC0_TXPCU_R0_MISC_MODE__ABORT_AFTER_MAC_PKT_END___POR 0x1 +#define WMAC0_TXPCU_R0_MISC_MODE__EN_PER_STA_CBF_RESP___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE__ALLOW_RAC___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE__BLOCK_RXPCU_BYPASS_TLVS___M 0x80000000 +#define WMAC0_TXPCU_R0_MISC_MODE__BLOCK_RXPCU_BYPASS_TLVS___S 31 +#define WMAC0_TXPCU_R0_MISC_MODE__GEN_FLUSH_FOR_LATE_TRIG_TLVS___M 0x40000000 +#define WMAC0_TXPCU_R0_MISC_MODE__GEN_FLUSH_FOR_LATE_TRIG_TLVS___S 30 +#define WMAC0_TXPCU_R0_MISC_MODE__ENABLE_CLNUP_FOR_LATE_TRIG_TLVS___M 0x20000000 +#define WMAC0_TXPCU_R0_MISC_MODE__ENABLE_CLNUP_FOR_LATE_TRIG_TLVS___S 29 +#define WMAC0_TXPCU_R0_MISC_MODE__TRIG_RESP_CTS_PKT_TYPE___M 0x10000000 +#define WMAC0_TXPCU_R0_MISC_MODE__TRIG_RESP_CTS_PKT_TYPE___S 28 +#define WMAC0_TXPCU_R0_MISC_MODE__ENABLE_DEBUG_CLOCK___M 0x08000000 +#define WMAC0_TXPCU_R0_MISC_MODE__ENABLE_DEBUG_CLOCK___S 27 +#define WMAC0_TXPCU_R0_MISC_MODE__ENABLE_CV_PERF_BOOST___M 0x04000000 +#define WMAC0_TXPCU_R0_MISC_MODE__ENABLE_CV_PERF_BOOST___S 26 +#define WMAC0_TXPCU_R0_MISC_MODE__RX_TX_CONFLICT_DET_EN___M 0x02000000 +#define WMAC0_TXPCU_R0_MISC_MODE__RX_TX_CONFLICT_DET_EN___S 25 +#define WMAC0_TXPCU_R0_MISC_MODE__DISABLE_DELAYED_SETUP_CLR___M 0x01000000 +#define WMAC0_TXPCU_R0_MISC_MODE__DISABLE_DELAYED_SETUP_CLR___S 24 +#define WMAC0_TXPCU_R0_MISC_MODE__TX_RX_CONFLICT_DET_EN___M 0x00800000 +#define WMAC0_TXPCU_R0_MISC_MODE__TX_RX_CONFLICT_DET_EN___S 23 +#define WMAC0_TXPCU_R0_MISC_MODE__SEND_SIFS_DELAYED___M 0x00400000 +#define WMAC0_TXPCU_R0_MISC_MODE__SEND_SIFS_DELAYED___S 22 +#define WMAC0_TXPCU_R0_MISC_MODE__BA_POLICY_FOR_MBA___M 0x00200000 +#define WMAC0_TXPCU_R0_MISC_MODE__BA_POLICY_FOR_MBA___S 21 +#define WMAC0_TXPCU_R0_MISC_MODE__NULL_DELIM_AFTER_CBF___M 0x00100000 +#define WMAC0_TXPCU_R0_MISC_MODE__NULL_DELIM_AFTER_CBF___S 20 +#define WMAC0_TXPCU_R0_MISC_MODE__NULL_DELIM_AFTER_BA___M 0x00080000 +#define WMAC0_TXPCU_R0_MISC_MODE__NULL_DELIM_AFTER_BA___S 19 +#define WMAC0_TXPCU_R0_MISC_MODE__BW_DROP_BEF_SFM___M 0x00040000 +#define WMAC0_TXPCU_R0_MISC_MODE__BW_DROP_BEF_SFM___S 18 +#define WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_MBA___M 0x00020000 +#define WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_MBA___S 17 +#define WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_SU_BA___M 0x00010000 +#define WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_SU_BA___S 16 +#define WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_CBF___M 0x00008000 +#define WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_CBF___S 15 +#define WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_CTS___M 0x00004000 +#define WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_CTS___S 14 +#define WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_BA___M 0x00002000 +#define WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_BA___S 13 +#define WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_RTT___M 0x00001000 +#define WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_RTT___S 12 +#define WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_ACK___M 0x00000800 +#define WMAC0_TXPCU_R0_MISC_MODE__SEND_RESP_STATUS_ACK___S 11 +#define WMAC0_TXPCU_R0_MISC_MODE__CBF_DETAILS_CLEAR_ON_FLUSH___M 0x00000400 +#define WMAC0_TXPCU_R0_MISC_MODE__CBF_DETAILS_CLEAR_ON_FLUSH___S 10 +#define WMAC0_TXPCU_R0_MISC_MODE__USE_WARM_TX_SIFS___M 0x00000200 +#define WMAC0_TXPCU_R0_MISC_MODE__USE_WARM_TX_SIFS___S 9 +#define WMAC0_TXPCU_R0_MISC_MODE__LOOPBACK_PREAMBLES_TRIG_RESP___M 0x00000100 +#define WMAC0_TXPCU_R0_MISC_MODE__LOOPBACK_PREAMBLES_TRIG_RESP___S 8 +#define WMAC0_TXPCU_R0_MISC_MODE__LOOPBACK_PREAMBLES_SELF_GEN___M 0x00000080 +#define WMAC0_TXPCU_R0_MISC_MODE__LOOPBACK_PREAMBLES_SELF_GEN___S 7 +#define WMAC0_TXPCU_R0_MISC_MODE__LOOPBACK_PREAMBLES_PPDU___M 0x00000040 +#define WMAC0_TXPCU_R0_MISC_MODE__LOOPBACK_PREAMBLES_PPDU___S 6 +#define WMAC0_TXPCU_R0_MISC_MODE__LOOPBACK_PREAMBLES_PROT___M 0x00000020 +#define WMAC0_TXPCU_R0_MISC_MODE__LOOPBACK_PREAMBLES_PROT___S 5 +#define WMAC0_TXPCU_R0_MISC_MODE__BLOCK_RESP_FRAMES___M 0x00000010 +#define WMAC0_TXPCU_R0_MISC_MODE__BLOCK_RESP_FRAMES___S 4 +#define WMAC0_TXPCU_R0_MISC_MODE__MIMIC_PHY_SOFT_ABORT___M 0x00000008 +#define WMAC0_TXPCU_R0_MISC_MODE__MIMIC_PHY_SOFT_ABORT___S 3 +#define WMAC0_TXPCU_R0_MISC_MODE__ABORT_AFTER_MAC_PKT_END___M 0x00000004 +#define WMAC0_TXPCU_R0_MISC_MODE__ABORT_AFTER_MAC_PKT_END___S 2 +#define WMAC0_TXPCU_R0_MISC_MODE__EN_PER_STA_CBF_RESP___M 0x00000002 +#define WMAC0_TXPCU_R0_MISC_MODE__EN_PER_STA_CBF_RESP___S 1 +#define WMAC0_TXPCU_R0_MISC_MODE__ALLOW_RAC___M 0x00000001 +#define WMAC0_TXPCU_R0_MISC_MODE__ALLOW_RAC___S 0 +#define WMAC0_TXPCU_R0_MISC_MODE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_MISC_MODE___S 0 + +#define WMAC0_TXPCU_R0_RTT_CTRL (0x00A8F028) +#define WMAC0_TXPCU_R0_RTT_CTRL___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RTT_CTRL___POR 0x00000000 +#define WMAC0_TXPCU_R0_RTT_CTRL__ALLOW_HT_VHT_ACK_BA_FTM___POR 0x0 +#define WMAC0_TXPCU_R0_RTT_CTRL__ALLOW_HT_VHT_ACK_BA_TM___POR 0x0 +#define WMAC0_TXPCU_R0_RTT_CTRL__ALLOW_HT_VHT_ACK_BA_FTM___M 0x00000002 +#define WMAC0_TXPCU_R0_RTT_CTRL__ALLOW_HT_VHT_ACK_BA_FTM___S 1 +#define WMAC0_TXPCU_R0_RTT_CTRL__ALLOW_HT_VHT_ACK_BA_TM___M 0x00000001 +#define WMAC0_TXPCU_R0_RTT_CTRL__ALLOW_HT_VHT_ACK_BA_TM___S 0 +#define WMAC0_TXPCU_R0_RTT_CTRL___M 0x00000003 +#define WMAC0_TXPCU_R0_RTT_CTRL___S 0 + +#define WMAC0_TXPCU_R0_SFM_USER_THRESHOLD (0x00A8F02C) +#define WMAC0_TXPCU_R0_SFM_USER_THRESHOLD___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_SFM_USER_THRESHOLD___POR 0x00200020 +#define WMAC0_TXPCU_R0_SFM_USER_THRESHOLD__DRAINED___POR 0x0020 +#define WMAC0_TXPCU_R0_SFM_USER_THRESHOLD__RECEIVED___POR 0x0020 +#define WMAC0_TXPCU_R0_SFM_USER_THRESHOLD__DRAINED___M 0xFFFF0000 +#define WMAC0_TXPCU_R0_SFM_USER_THRESHOLD__DRAINED___S 16 +#define WMAC0_TXPCU_R0_SFM_USER_THRESHOLD__RECEIVED___M 0x0000FFFF +#define WMAC0_TXPCU_R0_SFM_USER_THRESHOLD__RECEIVED___S 0 +#define WMAC0_TXPCU_R0_SFM_USER_THRESHOLD___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_SFM_USER_THRESHOLD___S 0 + +#define WMAC0_TXPCU_R0_SFM_OVERALL_BUF_THRESHOLD (0x00A8F030) +#define WMAC0_TXPCU_R0_SFM_OVERALL_BUF_THRESHOLD___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_SFM_OVERALL_BUF_THRESHOLD___POR 0x00000002 +#define WMAC0_TXPCU_R0_SFM_OVERALL_BUF_THRESHOLD__DATA_TLVS___POR 0x0000 +#define WMAC0_TXPCU_R0_SFM_OVERALL_BUF_THRESHOLD__VALUE___POR 0x0002 +#define WMAC0_TXPCU_R0_SFM_OVERALL_BUF_THRESHOLD__DATA_TLVS___M 0xFFFF0000 +#define WMAC0_TXPCU_R0_SFM_OVERALL_BUF_THRESHOLD__DATA_TLVS___S 16 +#define WMAC0_TXPCU_R0_SFM_OVERALL_BUF_THRESHOLD__VALUE___M 0x0000FFFF +#define WMAC0_TXPCU_R0_SFM_OVERALL_BUF_THRESHOLD__VALUE___S 0 +#define WMAC0_TXPCU_R0_SFM_OVERALL_BUF_THRESHOLD___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_SFM_OVERALL_BUF_THRESHOLD___S 0 + +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL (0x00A8F034) +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL___POR 0x00006490 +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__FINAL_MAX_BW___POR 0x3 +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__AGC_BW_SEL_FOR_NONCTS_RESP___POR 0x0 +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__MAX_AGC_NONCTS_BW___POR 0x1 +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__AGC_BW_SEL_FOR_CTS_RESP___POR 0x0 +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__MAX_AGC_CTS_BW___POR 0x1 +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__IGNORE_CCA_BW_AT_START_TX___POR 0x0 +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__USE_RTS_BW_FOR_PPDU___POR 0x0 +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__VHT_SERVICE_DYNAMIC___POR 0x1 +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__DPD_TRAINING_SELF_CTS_BW___POR 0x0 +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__HT_DYNAMIC_CBW___POR 0x0 +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__AGC_DYNAMIC_BW_SEL_PPDU___POR 0x0 +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__FINAL_MAX_BW___M 0x00006000 +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__FINAL_MAX_BW___S 13 +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__AGC_BW_SEL_FOR_NONCTS_RESP___M 0x00001000 +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__AGC_BW_SEL_FOR_NONCTS_RESP___S 12 +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__MAX_AGC_NONCTS_BW___M 0x00000C00 +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__MAX_AGC_NONCTS_BW___S 10 +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__AGC_BW_SEL_FOR_CTS_RESP___M 0x00000200 +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__AGC_BW_SEL_FOR_CTS_RESP___S 9 +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__MAX_AGC_CTS_BW___M 0x00000180 +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__MAX_AGC_CTS_BW___S 7 +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__IGNORE_CCA_BW_AT_START_TX___M 0x00000040 +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__IGNORE_CCA_BW_AT_START_TX___S 6 +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__USE_RTS_BW_FOR_PPDU___M 0x00000020 +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__USE_RTS_BW_FOR_PPDU___S 5 +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__VHT_SERVICE_DYNAMIC___M 0x00000010 +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__VHT_SERVICE_DYNAMIC___S 4 +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__DPD_TRAINING_SELF_CTS_BW___M 0x0000000C +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__DPD_TRAINING_SELF_CTS_BW___S 2 +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__HT_DYNAMIC_CBW___M 0x00000002 +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__HT_DYNAMIC_CBW___S 1 +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__AGC_DYNAMIC_BW_SEL_PPDU___M 0x00000001 +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL__AGC_DYNAMIC_BW_SEL_PPDU___S 0 +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL___M 0x00007FFF +#define WMAC0_TXPCU_R0_DYNAMIC_BW_CTL___S 0 + +#define WMAC0_TXPCU_R0_REQD_TLVS_WAIT_TIME (0x00A8F038) +#define WMAC0_TXPCU_R0_REQD_TLVS_WAIT_TIME___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_REQD_TLVS_WAIT_TIME___POR 0x00000007 +#define WMAC0_TXPCU_R0_REQD_TLVS_WAIT_TIME__VALUE___POR 0x0007 +#define WMAC0_TXPCU_R0_REQD_TLVS_WAIT_TIME__VALUE___M 0x0000FFFF +#define WMAC0_TXPCU_R0_REQD_TLVS_WAIT_TIME__VALUE___S 0 +#define WMAC0_TXPCU_R0_REQD_TLVS_WAIT_TIME___M 0x0000FFFF +#define WMAC0_TXPCU_R0_REQD_TLVS_WAIT_TIME___S 0 + +#define WMAC0_TXPCU_R0_TX_FRM_START_INTR_DELAY (0x00A8F03C) +#define WMAC0_TXPCU_R0_TX_FRM_START_INTR_DELAY___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_TX_FRM_START_INTR_DELAY___POR 0x00000001 +#define WMAC0_TXPCU_R0_TX_FRM_START_INTR_DELAY__VALUE___POR 0x01 +#define WMAC0_TXPCU_R0_TX_FRM_START_INTR_DELAY__VALUE___M 0x000000FF +#define WMAC0_TXPCU_R0_TX_FRM_START_INTR_DELAY__VALUE___S 0 +#define WMAC0_TXPCU_R0_TX_FRM_START_INTR_DELAY___M 0x000000FF +#define WMAC0_TXPCU_R0_TX_FRM_START_INTR_DELAY___S 0 + +#define WMAC0_TXPCU_R0_CBF_DETAILS (0x00A8F040) +#define WMAC0_TXPCU_R0_CBF_DETAILS___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R0_CBF_DETAILS___POR 0x00000000 +#define WMAC0_TXPCU_R0_CBF_DETAILS__CBF_DETAILS_BFER1_VALID___POR 0x0 +#define WMAC0_TXPCU_R0_CBF_DETAILS__CBF_DETAILS_BFER0_VALID___POR 0x0 +#define WMAC0_TXPCU_R0_CBF_DETAILS__CBF_DETAILS_BFER1_VALID___M 0x00000002 +#define WMAC0_TXPCU_R0_CBF_DETAILS__CBF_DETAILS_BFER1_VALID___S 1 +#define WMAC0_TXPCU_R0_CBF_DETAILS__CBF_DETAILS_BFER0_VALID___M 0x00000001 +#define WMAC0_TXPCU_R0_CBF_DETAILS__CBF_DETAILS_BFER0_VALID___S 0 +#define WMAC0_TXPCU_R0_CBF_DETAILS___M 0x00000003 +#define WMAC0_TXPCU_R0_CBF_DETAILS___S 0 + +#define WMAC0_TXPCU_R0_SOFT_ABORT_INT_PKT_END_DELAY (0x00A8F044) +#define WMAC0_TXPCU_R0_SOFT_ABORT_INT_PKT_END_DELAY___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_SOFT_ABORT_INT_PKT_END_DELAY___POR 0x00000005 +#define WMAC0_TXPCU_R0_SOFT_ABORT_INT_PKT_END_DELAY__USEC___POR 0x0005 +#define WMAC0_TXPCU_R0_SOFT_ABORT_INT_PKT_END_DELAY__USEC___M 0x0000FFFF +#define WMAC0_TXPCU_R0_SOFT_ABORT_INT_PKT_END_DELAY__USEC___S 0 +#define WMAC0_TXPCU_R0_SOFT_ABORT_INT_PKT_END_DELAY___M 0x0000FFFF +#define WMAC0_TXPCU_R0_SOFT_ABORT_INT_PKT_END_DELAY___S 0 + +#define WMAC0_TXPCU_R0_MISC_MODE_EXT (0x00A8F048) +#define WMAC0_TXPCU_R0_MISC_MODE_EXT___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_MISC_MODE_EXT___POR 0x0A000840 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__PRE_PHY_WINDOW_TIME_FES___POR 0x280 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_FLUSH_FOR_LATE_PRE_PHY___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_LATE_PRE_PHY_DET_RESP___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_LATE_PRE_PHY_DET_CTS2S___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_LATE_PRE_PHY_DET_FES___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISCARD_RESP_TYPE_CHECK_FOR_CAS___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__GLOBAL_TXPCU_DEBUG_COUNTERS_ENABLE___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_EVENT_CAPTURE_LOGIC___POR 0x1 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_BQR_OVERWRITE___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_CAS_OVERWRITE___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__ALWAYS_PICK_HT_OW_SRC_FOR_SRP_ON_TX_IN_SRP_WINDOW___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__AMPDU_WITH_PKT_TYPE___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__PHY_ABORT_OVER_SOFT_ABORT___POR 0x1 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_11AH_BW_DUPLICATION___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__EARLY_SECTOR_INDICATOR___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__ADDRESS_INDICATOR___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__RELAYED_FRAME___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DURATION_INDICATION___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__MORE_DATA___POR 0x0 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__PRE_PHY_WINDOW_TIME_FES___M 0x0FFC0000 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__PRE_PHY_WINDOW_TIME_FES___S 18 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_FLUSH_FOR_LATE_PRE_PHY___M 0x00020000 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_FLUSH_FOR_LATE_PRE_PHY___S 17 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_LATE_PRE_PHY_DET_RESP___M 0x00010000 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_LATE_PRE_PHY_DET_RESP___S 16 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_LATE_PRE_PHY_DET_CTS2S___M 0x00008000 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_LATE_PRE_PHY_DET_CTS2S___S 15 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_LATE_PRE_PHY_DET_FES___M 0x00004000 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_LATE_PRE_PHY_DET_FES___S 14 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISCARD_RESP_TYPE_CHECK_FOR_CAS___M 0x00002000 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISCARD_RESP_TYPE_CHECK_FOR_CAS___S 13 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__GLOBAL_TXPCU_DEBUG_COUNTERS_ENABLE___M 0x00001000 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__GLOBAL_TXPCU_DEBUG_COUNTERS_ENABLE___S 12 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_EVENT_CAPTURE_LOGIC___M 0x00000800 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_EVENT_CAPTURE_LOGIC___S 11 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_BQR_OVERWRITE___M 0x00000400 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_BQR_OVERWRITE___S 10 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_CAS_OVERWRITE___M 0x00000200 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_CAS_OVERWRITE___S 9 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__ALWAYS_PICK_HT_OW_SRC_FOR_SRP_ON_TX_IN_SRP_WINDOW___M 0x00000100 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__ALWAYS_PICK_HT_OW_SRC_FOR_SRP_ON_TX_IN_SRP_WINDOW___S 8 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__AMPDU_WITH_PKT_TYPE___M 0x00000080 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__AMPDU_WITH_PKT_TYPE___S 7 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__PHY_ABORT_OVER_SOFT_ABORT___M 0x00000040 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__PHY_ABORT_OVER_SOFT_ABORT___S 6 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_11AH_BW_DUPLICATION___M 0x00000020 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DISABLE_11AH_BW_DUPLICATION___S 5 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__EARLY_SECTOR_INDICATOR___M 0x00000010 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__EARLY_SECTOR_INDICATOR___S 4 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__ADDRESS_INDICATOR___M 0x00000008 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__ADDRESS_INDICATOR___S 3 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__RELAYED_FRAME___M 0x00000004 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__RELAYED_FRAME___S 2 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DURATION_INDICATION___M 0x00000002 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__DURATION_INDICATION___S 1 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__MORE_DATA___M 0x00000001 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT__MORE_DATA___S 0 +#define WMAC0_TXPCU_R0_MISC_MODE_EXT___M 0x0FFFFFFF +#define WMAC0_TXPCU_R0_MISC_MODE_EXT___S 0 + +#define WMAC0_TXPCU_R0_TQM_UPDATE (0x00A8F04C) +#define WMAC0_TXPCU_R0_TQM_UPDATE___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_TQM_UPDATE___POR 0x00000000 +#define WMAC0_TXPCU_R0_TQM_UPDATE__STATUS_RING___POR 0x0 +#define WMAC0_TXPCU_R0_TQM_UPDATE__STATUS_REQD___POR 0x0 +#define WMAC0_TXPCU_R0_TQM_UPDATE__CMD_NUMBER___POR 0x000000 +#define WMAC0_TXPCU_R0_TQM_UPDATE__STATUS_RING___M 0x02000000 +#define WMAC0_TXPCU_R0_TQM_UPDATE__STATUS_RING___S 25 +#define WMAC0_TXPCU_R0_TQM_UPDATE__STATUS_REQD___M 0x01000000 +#define WMAC0_TXPCU_R0_TQM_UPDATE__STATUS_REQD___S 24 +#define WMAC0_TXPCU_R0_TQM_UPDATE__CMD_NUMBER___M 0x00FFFFFF +#define WMAC0_TXPCU_R0_TQM_UPDATE__CMD_NUMBER___S 0 +#define WMAC0_TXPCU_R0_TQM_UPDATE___M 0x03FFFFFF +#define WMAC0_TXPCU_R0_TQM_UPDATE___S 0 + +#define WMAC0_TXPCU_R0_BITMAP_REQ_DELAY (0x00A8F050) +#define WMAC0_TXPCU_R0_BITMAP_REQ_DELAY___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_BITMAP_REQ_DELAY___POR 0x01400001 +#define WMAC0_TXPCU_R0_BITMAP_REQ_DELAY__R2R_WAIT_VALUE___POR 0x0140 +#define WMAC0_TXPCU_R0_BITMAP_REQ_DELAY__VALUE___POR 0x01 +#define WMAC0_TXPCU_R0_BITMAP_REQ_DELAY__R2R_WAIT_VALUE___M 0xFFFF0000 +#define WMAC0_TXPCU_R0_BITMAP_REQ_DELAY__R2R_WAIT_VALUE___S 16 +#define WMAC0_TXPCU_R0_BITMAP_REQ_DELAY__VALUE___M 0x000000FF +#define WMAC0_TXPCU_R0_BITMAP_REQ_DELAY__VALUE___S 0 +#define WMAC0_TXPCU_R0_BITMAP_REQ_DELAY___M 0xFFFF00FF +#define WMAC0_TXPCU_R0_BITMAP_REQ_DELAY___S 0 + +#define WMAC0_TXPCU_R0_MAX_ALLOWED_CBF_MPDU_SIZE (0x00A8F054) +#define WMAC0_TXPCU_R0_MAX_ALLOWED_CBF_MPDU_SIZE___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_MAX_ALLOWED_CBF_MPDU_SIZE___POR 0x00000C00 +#define WMAC0_TXPCU_R0_MAX_ALLOWED_CBF_MPDU_SIZE__VALUE___POR 0x0C00 +#define WMAC0_TXPCU_R0_MAX_ALLOWED_CBF_MPDU_SIZE__VALUE___M 0x0000FFFF +#define WMAC0_TXPCU_R0_MAX_ALLOWED_CBF_MPDU_SIZE__VALUE___S 0 +#define WMAC0_TXPCU_R0_MAX_ALLOWED_CBF_MPDU_SIZE___M 0x0000FFFF +#define WMAC0_TXPCU_R0_MAX_ALLOWED_CBF_MPDU_SIZE___S 0 + +#define WMAC0_TXPCU_R0_CBF_DATA_REQUEST_SIZE (0x00A8F058) +#define WMAC0_TXPCU_R0_CBF_DATA_REQUEST_SIZE___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_CBF_DATA_REQUEST_SIZE___POR 0x00000080 +#define WMAC0_TXPCU_R0_CBF_DATA_REQUEST_SIZE__VALUE___POR 0x0080 +#define WMAC0_TXPCU_R0_CBF_DATA_REQUEST_SIZE__VALUE___M 0x0000FFFF +#define WMAC0_TXPCU_R0_CBF_DATA_REQUEST_SIZE__VALUE___S 0 +#define WMAC0_TXPCU_R0_CBF_DATA_REQUEST_SIZE___M 0x0000FFFF +#define WMAC0_TXPCU_R0_CBF_DATA_REQUEST_SIZE___S 0 + +#define WMAC0_TXPCU_R0_CBF_REQ_TO_ACK_DELAY_TIME (0x00A8F05C) +#define WMAC0_TXPCU_R0_CBF_REQ_TO_ACK_DELAY_TIME___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_CBF_REQ_TO_ACK_DELAY_TIME___POR 0x00000009 +#define WMAC0_TXPCU_R0_CBF_REQ_TO_ACK_DELAY_TIME__VALUE___POR 0x09 +#define WMAC0_TXPCU_R0_CBF_REQ_TO_ACK_DELAY_TIME__VALUE___M 0x000000FF +#define WMAC0_TXPCU_R0_CBF_REQ_TO_ACK_DELAY_TIME__VALUE___S 0 +#define WMAC0_TXPCU_R0_CBF_REQ_TO_ACK_DELAY_TIME___M 0x000000FF +#define WMAC0_TXPCU_R0_CBF_REQ_TO_ACK_DELAY_TIME___S 0 + +#define WMAC0_TXPCU_R0_CBF_PADDING (0x00A8F060) +#define WMAC0_TXPCU_R0_CBF_PADDING___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_CBF_PADDING___POR 0x00040001 +#define WMAC0_TXPCU_R0_CBF_PADDING__RESPONSE_DENSITY___POR 0x04 +#define WMAC0_TXPCU_R0_CBF_PADDING__EOF_COUNT___POR 0x0001 +#define WMAC0_TXPCU_R0_CBF_PADDING__RESPONSE_DENSITY___M 0x001F0000 +#define WMAC0_TXPCU_R0_CBF_PADDING__RESPONSE_DENSITY___S 16 +#define WMAC0_TXPCU_R0_CBF_PADDING__EOF_COUNT___M 0x0000FFFF +#define WMAC0_TXPCU_R0_CBF_PADDING__EOF_COUNT___S 0 +#define WMAC0_TXPCU_R0_CBF_PADDING___M 0x001FFFFF +#define WMAC0_TXPCU_R0_CBF_PADDING___S 0 + +#define WMAC0_TXPCU_R0_RESP_MAC_PRE_PHY_DESC (0x00A8F064) +#define WMAC0_TXPCU_R0_RESP_MAC_PRE_PHY_DESC___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_MAC_PRE_PHY_DESC___POR 0x00A00780 +#define WMAC0_TXPCU_R0_RESP_MAC_PRE_PHY_DESC__MAC_CLK___POR 0x00A0 +#define WMAC0_TXPCU_R0_RESP_MAC_PRE_PHY_DESC__TIME___POR 0x0780 +#define WMAC0_TXPCU_R0_RESP_MAC_PRE_PHY_DESC__MAC_CLK___M 0xFFFF0000 +#define WMAC0_TXPCU_R0_RESP_MAC_PRE_PHY_DESC__MAC_CLK___S 16 +#define WMAC0_TXPCU_R0_RESP_MAC_PRE_PHY_DESC__TIME___M 0x0000FFFF +#define WMAC0_TXPCU_R0_RESP_MAC_PRE_PHY_DESC__TIME___S 0 +#define WMAC0_TXPCU_R0_RESP_MAC_PRE_PHY_DESC___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_MAC_PRE_PHY_DESC___S 0 + +#define WMAC0_TXPCU_R0_RESP_PIFS_TIMER (0x00A8F068) +#define WMAC0_TXPCU_R0_RESP_PIFS_TIMER___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_PIFS_TIMER___POR 0x0E600D20 +#define WMAC0_TXPCU_R0_RESP_PIFS_TIMER__TIMEOUT_PIFS___POR 0x0E60 +#define WMAC0_TXPCU_R0_RESP_PIFS_TIMER__PRE_PHY_DESC_PIFS___POR 0x0D20 +#define WMAC0_TXPCU_R0_RESP_PIFS_TIMER__TIMEOUT_PIFS___M 0xFFFF0000 +#define WMAC0_TXPCU_R0_RESP_PIFS_TIMER__TIMEOUT_PIFS___S 16 +#define WMAC0_TXPCU_R0_RESP_PIFS_TIMER__PRE_PHY_DESC_PIFS___M 0x0000FFFF +#define WMAC0_TXPCU_R0_RESP_PIFS_TIMER__PRE_PHY_DESC_PIFS___S 0 +#define WMAC0_TXPCU_R0_RESP_PIFS_TIMER___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_PIFS_TIMER___S 0 + +#define WMAC0_TXPCU_R0_TRIG_RESP_CTRL (0x00A8F06C) +#define WMAC0_TXPCU_R0_TRIG_RESP_CTRL___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_TRIG_RESP_CTRL___POR 0x001F0780 +#define WMAC0_TXPCU_R0_TRIG_RESP_CTRL__STATUS_TLV_UPD_ENA___POR 0x001F +#define WMAC0_TXPCU_R0_TRIG_RESP_CTRL__PRE_PHY_TIME___POR 0x0780 +#define WMAC0_TXPCU_R0_TRIG_RESP_CTRL__STATUS_TLV_UPD_ENA___M 0xFFFF0000 +#define WMAC0_TXPCU_R0_TRIG_RESP_CTRL__STATUS_TLV_UPD_ENA___S 16 +#define WMAC0_TXPCU_R0_TRIG_RESP_CTRL__PRE_PHY_TIME___M 0x0000FFFF +#define WMAC0_TXPCU_R0_TRIG_RESP_CTRL__PRE_PHY_TIME___S 0 +#define WMAC0_TXPCU_R0_TRIG_RESP_CTRL___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_TRIG_RESP_CTRL___S 0 + +#define WMAC0_TXPCU_R0_INVALID_APB_ACC_ADR (0x00A8F074) +#define WMAC0_TXPCU_R0_INVALID_APB_ACC_ADR___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R0_INVALID_APB_ACC_ADR___POR 0x00000000 +#define WMAC0_TXPCU_R0_INVALID_APB_ACC_ADR__VALUE___POR 0x00000 +#define WMAC0_TXPCU_R0_INVALID_APB_ACC_ADR__VALUE___M 0x0001FFFF +#define WMAC0_TXPCU_R0_INVALID_APB_ACC_ADR__VALUE___S 0 +#define WMAC0_TXPCU_R0_INVALID_APB_ACC_ADR___M 0x0001FFFF +#define WMAC0_TXPCU_R0_INVALID_APB_ACC_ADR___S 0 + +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX0 (0x00A8F078) +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX0___POR 0x00000000 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX0__TID3___POR 0x00 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX0__TID2___POR 0x00 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX0__TID1___POR 0x00 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX0__TID0___POR 0x00 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX0__TID3___M 0xFF000000 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX0__TID3___S 24 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX0__TID2___M 0x00FF0000 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX0__TID2___S 16 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX0__TID1___M 0x0000FF00 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX0__TID1___S 8 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX0__TID0___M 0x000000FF +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX0__TID0___S 0 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX0___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX0___S 0 + +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX1 (0x00A8F07C) +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX1___POR 0x00000000 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX1__TID7___POR 0x00 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX1__TID6___POR 0x00 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX1__TID5___POR 0x00 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX1__TID4___POR 0x00 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX1__TID7___M 0xFF000000 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX1__TID7___S 24 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX1__TID6___M 0x00FF0000 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX1__TID6___S 16 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX1__TID5___M 0x0000FF00 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX1__TID5___S 8 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX1__TID4___M 0x000000FF +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX1__TID4___S 0 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX1___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0_IX1___S 0 + +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0 (0x00A8F080) +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0___POR 0x00000000 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0__SUB_ENA___POR 0x000 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0__SUM___POR 0x00 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0__SUB_ENA___M 0x0001FF00 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0__SUB_ENA___S 8 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0__SUM___M 0x000000FF +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0__SUM___S 0 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0___M 0x0001FFFF +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA0___S 0 + +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX0 (0x00A8F084) +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX0___POR 0x00000000 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX0__TID3___POR 0x00 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX0__TID2___POR 0x00 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX0__TID1___POR 0x00 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX0__TID0___POR 0x00 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX0__TID3___M 0xFF000000 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX0__TID3___S 24 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX0__TID2___M 0x00FF0000 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX0__TID2___S 16 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX0__TID1___M 0x0000FF00 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX0__TID1___S 8 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX0__TID0___M 0x000000FF +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX0__TID0___S 0 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX0___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX0___S 0 + +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX1 (0x00A8F088) +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX1___POR 0x00000000 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX1__TID7___POR 0x00 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX1__TID6___POR 0x00 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX1__TID5___POR 0x00 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX1__TID4___POR 0x00 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX1__TID7___M 0xFF000000 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX1__TID7___S 24 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX1__TID6___M 0x00FF0000 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX1__TID6___S 16 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX1__TID5___M 0x0000FF00 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX1__TID5___S 8 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX1__TID4___M 0x000000FF +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX1__TID4___S 0 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX1___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1_IX1___S 0 + +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1 (0x00A8F08C) +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1___POR 0x00000000 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1__SUB_ENA___POR 0x000 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1__SUM___POR 0x00 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1__SUB_ENA___M 0x0001FF00 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1__SUB_ENA___S 8 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1__SUM___M 0x000000FF +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1__SUM___S 0 +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1___M 0x0001FFFF +#define WMAC0_TXPCU_R0_QOS_BUF_STATE_STA1___S 0 + +#define WMAC0_TXPCU_R0_SELF_GEN_ERROR (0x00A8F0E0) +#define WMAC0_TXPCU_R0_SELF_GEN_ERROR___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R0_SELF_GEN_ERROR___POR 0x00000000 +#define WMAC0_TXPCU_R0_SELF_GEN_ERROR__STATUS___POR 0x00 +#define WMAC0_TXPCU_R0_SELF_GEN_ERROR__STATUS___M 0x000000FF +#define WMAC0_TXPCU_R0_SELF_GEN_ERROR__STATUS___S 0 +#define WMAC0_TXPCU_R0_SELF_GEN_ERROR___M 0x000000FF +#define WMAC0_TXPCU_R0_SELF_GEN_ERROR___S 0 + +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_n(n) (0x00A8F104+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_n_nMIN 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_n_nMAX 6 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_n_ELEM 7 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_n___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_n___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_n__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_n__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_n__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_n___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_n___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_0 (0x00A8F104) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_1 (0x00A8F108) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_1__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_2 (0x00A8F10C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_2___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_2__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_2__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_3 (0x00A8F110) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_3___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_3__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_3__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_4 (0x00A8F114) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_4___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_4__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_4__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_5 (0x00A8F118) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_5___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_5__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_5__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_6 (0x00A8F11C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_6___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_6__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CCK_6__VALUE___S 0 + +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_n(n) (0x00A8F120+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_n_nMIN 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_n_nMAX 7 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_n_ELEM 8 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_n___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_n___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_n__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_n__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_n__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_n___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_n___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_0 (0x00A8F120) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_1 (0x00A8F124) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_1__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_2 (0x00A8F128) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_2___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_2__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_2__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_3 (0x00A8F12C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_3___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_3__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_3__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_4 (0x00A8F130) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_4___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_4__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_4__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_5 (0x00A8F134) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_5___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_5__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_5__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_6 (0x00A8F138) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_6___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_6__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_6__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_7 (0x00A8F13C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_7___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_7__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_OFDM_7__VALUE___S 0 + +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_n(n) (0x00A8F140+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_n_nMIN 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_n_nMAX 7 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_n_ELEM 8 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_n___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_n___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_n__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_n__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_n__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_n___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_n___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_0 (0x00A8F140) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_1 (0x00A8F144) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_1__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_2 (0x00A8F148) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_2___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_2__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_2__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_3 (0x00A8F14C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_3___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_3__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_3__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_4 (0x00A8F150) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_4___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_4__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_4__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_5 (0x00A8F154) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_5___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_5__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_5__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_6 (0x00A8F158) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_6___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_6__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_6__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_7 (0x00A8F15C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_7___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_7__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_HT_7__VALUE___S 0 + +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_n(n) (0x00A8F160+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_n_nMIN 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_n_nMAX 11 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_n_ELEM 12 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_n___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_n___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_n__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_n__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_n__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_n___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_n___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_0 (0x00A8F160) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_1 (0x00A8F164) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_1__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_2 (0x00A8F168) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_2___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_2__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_2__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_3 (0x00A8F16C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_3___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_3__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_3__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_4 (0x00A8F170) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_4___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_4__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_4__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_5 (0x00A8F174) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_5___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_5__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_5__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_6 (0x00A8F178) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_6___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_6__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_6__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_7 (0x00A8F17C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_7___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_7__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_7__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_8 (0x00A8F180) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_8___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_8__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_8__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_9 (0x00A8F184) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_9___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_9__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_9__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_10 (0x00A8F188) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_10___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_10__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_10__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_11 (0x00A8F18C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_11___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_11__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_VHT_11__VALUE___S 0 + +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_n(n) (0x00A8F190+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_n_nMIN 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_n_nMAX 13 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_n_ELEM 14 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_n___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_n___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_n__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_n__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_n__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_n___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_n___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_0 (0x00A8F190) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_1 (0x00A8F194) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_1__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_2 (0x00A8F198) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_2___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_2__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_2__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_3 (0x00A8F19C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_3___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_3__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_3__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_4 (0x00A8F1A0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_4___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_4__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_4__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_5 (0x00A8F1A4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_5___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_5__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_5__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_6 (0x00A8F1A8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_6___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_6__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_6__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_7 (0x00A8F1AC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_7___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_7__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_7__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_8 (0x00A8F1B0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_8___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_8__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_8__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_9 (0x00A8F1B4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_9___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_9__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_9__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_10 (0x00A8F1B8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_10___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_10__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_10__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_11 (0x00A8F1BC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_11___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_11__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_11__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_12 (0x00A8F1C0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_12___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_12__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_12__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_13 (0x00A8F1C4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_13___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_13__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_13__VALUE___S 0 + +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_n(n) (0x00A8F1C8+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_n_nMIN 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_n_nMAX 7 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_n_ELEM 8 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_n___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_n___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_n__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_n__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_n__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_n___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_n___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_0 (0x00A8F1C8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_1 (0x00A8F1CC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_1__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_2 (0x00A8F1D0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_2___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_2__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_2__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_3 (0x00A8F1D4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_3___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_3__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_3__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_4 (0x00A8F1D8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_4___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_4__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_4__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_5 (0x00A8F1DC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_5___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_5__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_5__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_6 (0x00A8F1E0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_6___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_6__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_6__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_7 (0x00A8F1E4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_7___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_7__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_7__VALUE___S 0 + +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_n(n) (0x00A8F1E8+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_n_nMIN 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_n_nMAX 7 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_n_ELEM 8 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_n___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_n___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_n__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_n__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_n__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_n___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_n___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_0 (0x00A8F1E8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_1 (0x00A8F1EC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_1__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_2 (0x00A8F1F0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_2___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_2__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_2__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_3 (0x00A8F1F4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_3___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_3__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_3__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_4 (0x00A8F1F8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_4___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_4__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_4__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_5 (0x00A8F1FC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_5___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_5__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_5__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_6 (0x00A8F200) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_6___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_6__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_6__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_7 (0x00A8F204) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_7___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_7__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_7__VALUE___S 0 + +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_n(n) (0x00A8F208+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_n_nMIN 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_n_nMAX 7 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_n_ELEM 8 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_n___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_n___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_n__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_n__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_n__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_n___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_n___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_0 (0x00A8F208) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_1 (0x00A8F20C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_1__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_2 (0x00A8F210) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_2___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_2__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_2__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_3 (0x00A8F214) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_3___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_3__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_3__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_4 (0x00A8F218) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_4___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_4__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_4__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_5 (0x00A8F21C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_5___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_5__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_5__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_6 (0x00A8F220) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_6___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_6__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_6__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_7 (0x00A8F224) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_7___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_7__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11N_7__VALUE___S 0 + +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_n(n) (0x00A8F228+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_n_nMIN 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_n_nMAX 11 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_n_ELEM 12 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_n___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_n___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_n__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_n__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_n__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_n___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_n___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_0 (0x00A8F228) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_1 (0x00A8F22C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_1__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_2 (0x00A8F230) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_2___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_2__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_2__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_3 (0x00A8F234) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_3___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_3__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_3__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_4 (0x00A8F238) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_4___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_4__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_4__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_5 (0x00A8F23C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_5___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_5__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_5__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_6 (0x00A8F240) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_6___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_6__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_6__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_7 (0x00A8F244) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_7___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_7__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_7__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_8 (0x00A8F248) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_8___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_8__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_8__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_9 (0x00A8F24C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_9___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_9__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_9__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_10 (0x00A8F250) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_10___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_10__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_10__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_11 (0x00A8F254) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_11___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_11__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AC_11__VALUE___S 0 + +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_n(n) (0x00A8F258+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_n_nMIN 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_n_nMAX 13 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_n_ELEM 14 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_n___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_n___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_n__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_n__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_n__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_n___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_n___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_0 (0x00A8F258) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_1 (0x00A8F25C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_1__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_2 (0x00A8F260) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_2___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_2__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_2__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_3 (0x00A8F264) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_3___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_3__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_3__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_4 (0x00A8F268) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_4___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_4__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_4__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_5 (0x00A8F26C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_5___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_5__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_5__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_6 (0x00A8F270) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_6___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_6__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_6__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_7 (0x00A8F274) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_7___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_7__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_7__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_8 (0x00A8F278) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_8___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_8__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_8__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_9 (0x00A8F27C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_9___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_9__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_9__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_10 (0x00A8F280) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_10___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_10__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_10__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_11 (0x00A8F284) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_11___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_11__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_11__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_12 (0x00A8F288) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_12___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_12__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_12__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_13 (0x00A8F28C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_13___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_13__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_13__VALUE___S 0 + +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_n(n) (0x00A8F290+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_n_nMIN 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_n_nMAX 13 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_n_ELEM 14 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_n___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_n___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_n__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_n__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_n__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_n___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_n___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_0 (0x00A8F290) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_1 (0x00A8F294) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_1__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_2 (0x00A8F298) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_2___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_2__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_2__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_3 (0x00A8F29C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_3___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_3__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_3__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_4 (0x00A8F2A0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_4___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_4__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_4__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_5 (0x00A8F2A4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_5___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_5__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_5__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_6 (0x00A8F2A8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_6___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_6__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_6__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_7 (0x00A8F2AC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_7___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_7__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_7__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_8 (0x00A8F2B0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_8___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_8__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_8__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_9 (0x00A8F2B4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_9___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_9__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_9__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_10 (0x00A8F2B8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_10___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_10__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_10__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_11 (0x00A8F2BC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_11___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_11__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_11__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_12 (0x00A8F2C0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_12___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_12__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_12__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_13 (0x00A8F2C4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_13___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_13__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11AX_EXT_13__VALUE___S 0 + +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_n(n) (0x00A8F2C8+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_n_nMIN 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_n_nMAX 7 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_n_ELEM 8 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_n___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_n___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_n__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_n__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_n__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_n___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_n___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_0 (0x00A8F2C8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_1 (0x00A8F2CC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_1__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_2 (0x00A8F2D0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_2___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_2__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_2__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_3 (0x00A8F2D4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_3___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_3__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_3__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_4 (0x00A8F2D8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_4___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_4__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_4__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_5 (0x00A8F2DC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_5___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_5__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_5__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_6 (0x00A8F2E0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_6___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_6__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_6__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_7 (0x00A8F2E4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_7___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_7__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11N_7__VALUE___S 0 + +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_n(n) (0x00A8F2E8+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_n_nMIN 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_n_nMAX 11 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_n_ELEM 12 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_n___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_n___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_n__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_n__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_n__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_n___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_n___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_0 (0x00A8F2E8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_1 (0x00A8F2EC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_1__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_2 (0x00A8F2F0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_2___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_2__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_2__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_3 (0x00A8F2F4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_3___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_3__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_3__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_4 (0x00A8F2F8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_4___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_4__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_4__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_5 (0x00A8F2FC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_5___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_5__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_5__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_6 (0x00A8F300) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_6___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_6__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_6__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_7 (0x00A8F304) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_7___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_7__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_7__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_8 (0x00A8F308) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_8___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_8__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_8__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_9 (0x00A8F30C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_9___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_9__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_9__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_10 (0x00A8F310) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_10___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_10__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_10__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_11 (0x00A8F314) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_11___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_11__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AC_11__VALUE___S 0 + +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_n(n) (0x00A8F318+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_n_nMIN 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_n_nMAX 13 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_n_ELEM 14 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_n___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_n___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_n__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_n__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_n__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_n___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_n___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_0 (0x00A8F318) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_1 (0x00A8F31C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_1__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_2 (0x00A8F320) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_2___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_2__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_2__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_3 (0x00A8F324) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_3___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_3__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_3__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_4 (0x00A8F328) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_4___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_4__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_4__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_5 (0x00A8F32C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_5___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_5__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_5__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_6 (0x00A8F330) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_6___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_6__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_6__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_7 (0x00A8F334) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_7___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_7__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_7__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_8 (0x00A8F338) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_8___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_8__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_8__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_9 (0x00A8F33C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_9___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_9__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_9__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_10 (0x00A8F340) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_10___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_10__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_10__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_11 (0x00A8F344) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_11___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_11__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_11__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_12 (0x00A8F348) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_12___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_12__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_12__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_13 (0x00A8F34C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_13___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_13__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_13__VALUE___S 0 + +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_n(n) (0x00A8F350+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_n_nMIN 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_n_nMAX 13 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_n_ELEM 14 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_n___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_n___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_n__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_n__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_n__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_n___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_n___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_0 (0x00A8F350) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_1 (0x00A8F354) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_1__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_2 (0x00A8F358) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_2___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_2__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_2__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_3 (0x00A8F35C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_3___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_3__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_3__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_4 (0x00A8F360) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_4___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_4__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_4__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_5 (0x00A8F364) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_5___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_5__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_5__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_6 (0x00A8F368) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_6___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_6__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_6__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_7 (0x00A8F36C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_7___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_7__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_7__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_8 (0x00A8F370) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_8___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_8__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_8__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_9 (0x00A8F374) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_9___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_9__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_9__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_10 (0x00A8F378) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_10___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_10__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_10__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_11 (0x00A8F37C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_11___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_11__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_11__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_12 (0x00A8F380) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_12___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_12__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_12__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_13 (0x00A8F384) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_13___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_13__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11AX_EXT_13__VALUE___S 0 + +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_n(n) (0x00A8F388+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_n_nMIN 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_n_nMAX 7 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_n_ELEM 8 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_n___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_n___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_n__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_n__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_n__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_n___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_n___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_0 (0x00A8F388) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_1 (0x00A8F38C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_1__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_2 (0x00A8F390) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_2___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_2__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_2__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_3 (0x00A8F394) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_3___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_3__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_3__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_4 (0x00A8F398) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_4___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_4__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_4__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_5 (0x00A8F39C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_5___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_5__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_5__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_6 (0x00A8F3A0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_6___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_6__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_6__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_7 (0x00A8F3A4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_7___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_7__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AC_7__VALUE___S 0 + +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_n(n) (0x00A8F3A8+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_n_nMIN 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_n_nMAX 7 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_n_ELEM 8 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_n___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_n___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_n__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_n__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_n__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_n___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_n___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_0 (0x00A8F3A8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_1 (0x00A8F3AC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_1__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_2 (0x00A8F3B0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_2___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_2__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_2__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_3 (0x00A8F3B4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_3___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_3__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_3__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_4 (0x00A8F3B8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_4___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_4__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_4__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_5 (0x00A8F3BC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_5___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_5__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_5__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_6 (0x00A8F3C0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_6___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_6__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_6__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_7 (0x00A8F3C4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_7___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_7__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AC_7__VALUE___S 0 + +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_n(n) (0x00A8F3C8+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_n_nMIN 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_n_nMAX 7 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_n_ELEM 8 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_n___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_n___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_n__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_n__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_n__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_n___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_n___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_0 (0x00A8F3C8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_1 (0x00A8F3CC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_1__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_2 (0x00A8F3D0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_2___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_2__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_2__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_3 (0x00A8F3D4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_3___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_3__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_3__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_4 (0x00A8F3D8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_4___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_4__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_4__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_5 (0x00A8F3DC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_5___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_5__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_5__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_6 (0x00A8F3E0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_6___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_6__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_6__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_7 (0x00A8F3E4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_7___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_7__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11N_7__VALUE___S 0 + +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_n(n) (0x00A8F3E8+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_n_nMIN 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_n_nMAX 7 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_n_ELEM 8 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_n___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_n___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_n__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_n__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_n__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_n___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_n___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_0 (0x00A8F3E8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_1 (0x00A8F3EC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_1__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_2 (0x00A8F3F0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_2___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_2__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_2__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_3 (0x00A8F3F4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_3___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_3__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_3__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_4 (0x00A8F3F8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_4___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_4__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_4__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_5 (0x00A8F3FC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_5___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_5__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_5__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_6 (0x00A8F400) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_6___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_6__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_6__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_7 (0x00A8F404) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_7___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_7__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11N_7__VALUE___S 0 + +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_n(n) (0x00A8F408+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_n_nMIN 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_n_nMAX 7 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_n_ELEM 8 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_n___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_n___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_n__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_n__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_n__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_n___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_n___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_0 (0x00A8F408) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_1 (0x00A8F40C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_1__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_2 (0x00A8F410) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_2___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_2__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_2__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_3 (0x00A8F414) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_3___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_3__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_3__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_4 (0x00A8F418) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_4___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_4__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_4__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_5 (0x00A8F41C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_5___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_5__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_5__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_6 (0x00A8F420) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_6___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_6__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_6__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_7 (0x00A8F424) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_7___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_7__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_7__VALUE___S 0 + +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_n(n) (0x00A8F428+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_n_nMIN 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_n_nMAX 7 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_n_ELEM 8 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_n___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_n___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_n__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_n__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_n__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_n___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_n___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_0 (0x00A8F428) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_1 (0x00A8F42C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_1__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_2 (0x00A8F430) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_2___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_2__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_2__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_3 (0x00A8F434) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_3___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_3__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_3__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_4 (0x00A8F438) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_4___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_4__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_4__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_5 (0x00A8F43C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_5___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_5__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_5__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_6 (0x00A8F440) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_6___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_6__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_6__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_7 (0x00A8F444) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_7___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_7__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_FTM_RTT_11A_11AX_EXT_7__VALUE___S 0 + +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_n(n) (0x00A8F448+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_n_nMIN 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_n_nMAX 7 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_n_ELEM 8 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_n___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_n___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_n__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_n__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_n__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_n___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_n___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_0 (0x00A8F448) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_1 (0x00A8F44C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_1__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_2 (0x00A8F450) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_2___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_2__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_2__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_3 (0x00A8F454) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_3___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_3__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_3__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_4 (0x00A8F458) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_4___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_4__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_4__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_5 (0x00A8F45C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_5___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_5__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_5__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_6 (0x00A8F460) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_6___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_6__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_6__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_7 (0x00A8F464) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_7___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_7__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_7__VALUE___S 0 + +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_n(n) (0x00A8F468+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_n_nMIN 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_n_nMAX 7 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_n_ELEM 8 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_n___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_n___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_n__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_n__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_n__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_n___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_n___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_0 (0x00A8F468) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_1 (0x00A8F46C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_1__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_2 (0x00A8F470) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_2___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_2__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_2__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_3 (0x00A8F474) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_3___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_3__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_3__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_4 (0x00A8F478) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_4___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_4__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_4__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_5 (0x00A8F47C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_5___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_5__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_5__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_6 (0x00A8F480) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_6___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_6__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_6__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_7 (0x00A8F484) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_7___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_7__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_TM_RTT_11A_11AX_EXT_7__VALUE___S 0 + +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_n(n) (0x00A8F488+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_n_nMIN 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_n_nMAX 3 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_n_ELEM 4 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_n___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_n___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_n__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_n__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_n__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_n___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_n___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_0 (0x00A8F488) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_1 (0x00A8F48C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_1__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_2 (0x00A8F490) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_2___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_2__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_2__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_3 (0x00A8F494) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_3___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_3__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_3_0_3__VALUE___S 0 + +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_n(n) (0x00A8F498+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_n_nMIN 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_n_nMAX 3 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_n_ELEM 4 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_n___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_n___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_n__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_n__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_n__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_n___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_n___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_0 (0x00A8F498) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_1 (0x00A8F49C) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_1__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_2 (0x00A8F4A0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_2___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_2__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_2__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_3 (0x00A8F4A4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_3___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_3__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_7_4_3__VALUE___S 0 + +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_n(n) (0x00A8F4A8+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_n_nMIN 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_n_nMAX 3 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_n_ELEM 4 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_n___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_n___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_n__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_n__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_n__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_n___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_n___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_0 (0x00A8F4A8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_1 (0x00A8F4AC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_1__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_2 (0x00A8F4B0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_2___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_2__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_2__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_3 (0x00A8F4B4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_3___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_3__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_3_0_3__VALUE___S 0 + +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_n(n) (0x00A8F4B8+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_n_nMIN 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_n_nMAX 3 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_n_ELEM 4 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_n___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_n___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_n__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_n__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_n__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_n___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_n___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_0 (0x00A8F4B8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_1 (0x00A8F4BC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_1__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_2 (0x00A8F4C0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_2___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_2__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_2__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_3 (0x00A8F4C4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_3___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_3__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_EXT_7_4_3__VALUE___S 0 + +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_n(n) (0x00A8F4C8+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_n_nMIN 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_n_nMAX 13 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_n_ELEM 14 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_n___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_n___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_n__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_n__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_n__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_n___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_n___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_0 (0x00A8F4C8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_1 (0x00A8F4CC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_1__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_2 (0x00A8F4D0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_2___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_2__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_2__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_3 (0x00A8F4D4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_3___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_3__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_3__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_4 (0x00A8F4D8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_4___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_4__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_4__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_5 (0x00A8F4DC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_5___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_5__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_5__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_6 (0x00A8F4E0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_6___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_6__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_6__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_7 (0x00A8F4E4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_7___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_7__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_7__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_8 (0x00A8F4E8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_8___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_8__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_8__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_9 (0x00A8F4EC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_9___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_9__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_9__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_10 (0x00A8F4F0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_10___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_10__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_10__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_11 (0x00A8F4F4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_11___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_11__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_11__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_12 (0x00A8F4F8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_12___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_12__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_12__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_13 (0x00A8F4FC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_13___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_13__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_AX_EXT_13__VALUE___S 0 + +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_n(n) (0x00A8F500+0x4*(n)) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_n_nMIN 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_n_nMAX 1023 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_n_ELEM 1024 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_n___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_n___POR 0x00000000 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_n__DATA___POR 0x00000000 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_n__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_n__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_n___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_n___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_0 (0x00A8F500) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_0__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_0__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1 (0x00A8F504) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_2 (0x00A8F508) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_2___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_2__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_2__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_3 (0x00A8F50C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_3___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_3__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_3__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_4 (0x00A8F510) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_4___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_4__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_4__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_5 (0x00A8F514) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_5___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_5__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_5__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_6 (0x00A8F518) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_6___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_6__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_6__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_7 (0x00A8F51C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_7___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_7__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_7__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_8 (0x00A8F520) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_8___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_8__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_8__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_9 (0x00A8F524) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_9___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_9__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_9__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_10 (0x00A8F528) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_10___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_10__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_10__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_11 (0x00A8F52C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_11___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_11__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_11__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_12 (0x00A8F530) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_12___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_12__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_12__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_13 (0x00A8F534) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_13___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_13__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_13__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_14 (0x00A8F538) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_14___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_14__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_14__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_15 (0x00A8F53C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_15___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_15__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_15__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_16 (0x00A8F540) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_16___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_16__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_16__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_17 (0x00A8F544) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_17___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_17__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_17__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_18 (0x00A8F548) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_18___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_18__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_18__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_19 (0x00A8F54C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_19___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_19__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_19__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_20 (0x00A8F550) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_20___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_20__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_20__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_21 (0x00A8F554) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_21___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_21__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_21__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_22 (0x00A8F558) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_22___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_22__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_22__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_23 (0x00A8F55C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_23___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_23__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_23__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_24 (0x00A8F560) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_24___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_24__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_24__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_25 (0x00A8F564) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_25___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_25__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_25__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_26 (0x00A8F568) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_26___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_26__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_26__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_27 (0x00A8F56C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_27___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_27__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_27__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_28 (0x00A8F570) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_28___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_28__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_28__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_29 (0x00A8F574) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_29___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_29__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_29__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_30 (0x00A8F578) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_30___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_30__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_30__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_31 (0x00A8F57C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_31___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_31__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_31__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_32 (0x00A8F580) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_32___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_32__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_32__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_33 (0x00A8F584) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_33___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_33__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_33__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_34 (0x00A8F588) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_34___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_34__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_34__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_35 (0x00A8F58C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_35___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_35__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_35__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_36 (0x00A8F590) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_36___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_36__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_36__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_37 (0x00A8F594) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_37___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_37__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_37__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_38 (0x00A8F598) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_38___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_38__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_38__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_39 (0x00A8F59C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_39___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_39__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_39__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_40 (0x00A8F5A0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_40___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_40__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_40__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_41 (0x00A8F5A4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_41___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_41__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_41__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_42 (0x00A8F5A8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_42___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_42__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_42__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_43 (0x00A8F5AC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_43___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_43__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_43__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_44 (0x00A8F5B0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_44___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_44__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_44__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_45 (0x00A8F5B4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_45___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_45__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_45__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_46 (0x00A8F5B8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_46___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_46__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_46__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_47 (0x00A8F5BC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_47___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_47__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_47__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_48 (0x00A8F5C0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_48___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_48__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_48__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_49 (0x00A8F5C4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_49___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_49__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_49__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_50 (0x00A8F5C8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_50___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_50__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_50__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_51 (0x00A8F5CC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_51___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_51__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_51__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_52 (0x00A8F5D0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_52___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_52__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_52__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_53 (0x00A8F5D4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_53___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_53__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_53__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_54 (0x00A8F5D8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_54___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_54__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_54__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_55 (0x00A8F5DC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_55___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_55__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_55__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_56 (0x00A8F5E0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_56___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_56__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_56__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_57 (0x00A8F5E4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_57___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_57__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_57__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_58 (0x00A8F5E8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_58___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_58__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_58__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_59 (0x00A8F5EC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_59___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_59__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_59__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_60 (0x00A8F5F0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_60___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_60__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_60__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_61 (0x00A8F5F4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_61___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_61__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_61__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_62 (0x00A8F5F8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_62___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_62__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_62__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_63 (0x00A8F5FC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_63___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_63__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_63__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_64 (0x00A8F600) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_64___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_64__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_64__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_65 (0x00A8F604) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_65___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_65__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_65__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_66 (0x00A8F608) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_66___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_66__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_66__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_67 (0x00A8F60C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_67___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_67__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_67__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_68 (0x00A8F610) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_68___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_68__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_68__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_69 (0x00A8F614) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_69___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_69__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_69__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_70 (0x00A8F618) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_70___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_70__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_70__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_71 (0x00A8F61C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_71___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_71__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_71__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_72 (0x00A8F620) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_72___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_72__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_72__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_73 (0x00A8F624) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_73___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_73__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_73__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_74 (0x00A8F628) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_74___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_74__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_74__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_75 (0x00A8F62C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_75___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_75__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_75__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_76 (0x00A8F630) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_76___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_76__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_76__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_77 (0x00A8F634) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_77___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_77__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_77__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_78 (0x00A8F638) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_78___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_78__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_78__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_79 (0x00A8F63C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_79___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_79__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_79__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_80 (0x00A8F640) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_80___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_80__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_80__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_81 (0x00A8F644) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_81___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_81__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_81__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_82 (0x00A8F648) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_82___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_82__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_82__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_83 (0x00A8F64C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_83___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_83__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_83__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_84 (0x00A8F650) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_84___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_84__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_84__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_85 (0x00A8F654) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_85___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_85__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_85__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_86 (0x00A8F658) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_86___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_86__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_86__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_87 (0x00A8F65C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_87___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_87__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_87__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_88 (0x00A8F660) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_88___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_88__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_88__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_89 (0x00A8F664) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_89___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_89__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_89__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_90 (0x00A8F668) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_90___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_90__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_90__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_91 (0x00A8F66C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_91___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_91__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_91__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_92 (0x00A8F670) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_92___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_92__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_92__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_93 (0x00A8F674) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_93___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_93__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_93__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_94 (0x00A8F678) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_94___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_94__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_94__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_95 (0x00A8F67C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_95___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_95__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_95__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_96 (0x00A8F680) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_96___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_96__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_96__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_97 (0x00A8F684) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_97___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_97__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_97__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_98 (0x00A8F688) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_98___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_98__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_98__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_99 (0x00A8F68C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_99___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_99__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_99__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_100 (0x00A8F690) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_100___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_100__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_100__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_101 (0x00A8F694) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_101___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_101__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_101__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_102 (0x00A8F698) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_102___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_102__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_102__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_103 (0x00A8F69C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_103___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_103__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_103__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_104 (0x00A8F6A0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_104___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_104__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_104__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_105 (0x00A8F6A4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_105___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_105__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_105__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_106 (0x00A8F6A8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_106___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_106__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_106__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_107 (0x00A8F6AC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_107___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_107__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_107__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_108 (0x00A8F6B0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_108___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_108__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_108__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_109 (0x00A8F6B4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_109___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_109__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_109__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_110 (0x00A8F6B8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_110___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_110__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_110__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_111 (0x00A8F6BC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_111___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_111__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_111__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_112 (0x00A8F6C0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_112___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_112__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_112__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_113 (0x00A8F6C4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_113___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_113__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_113__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_114 (0x00A8F6C8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_114___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_114__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_114__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_115 (0x00A8F6CC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_115___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_115__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_115__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_116 (0x00A8F6D0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_116___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_116__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_116__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_117 (0x00A8F6D4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_117___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_117__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_117__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_118 (0x00A8F6D8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_118___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_118__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_118__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_119 (0x00A8F6DC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_119___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_119__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_119__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_120 (0x00A8F6E0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_120___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_120__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_120__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_121 (0x00A8F6E4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_121___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_121__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_121__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_122 (0x00A8F6E8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_122___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_122__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_122__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_123 (0x00A8F6EC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_123___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_123__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_123__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_124 (0x00A8F6F0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_124___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_124__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_124__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_125 (0x00A8F6F4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_125___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_125__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_125__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_126 (0x00A8F6F8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_126___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_126__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_126__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_127 (0x00A8F6FC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_127___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_127__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_127__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_128 (0x00A8F700) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_128___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_128__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_128__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_129 (0x00A8F704) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_129___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_129__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_129__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_130 (0x00A8F708) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_130___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_130__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_130__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_131 (0x00A8F70C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_131___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_131__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_131__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_132 (0x00A8F710) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_132___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_132__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_132__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_133 (0x00A8F714) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_133___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_133__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_133__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_134 (0x00A8F718) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_134___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_134__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_134__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_135 (0x00A8F71C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_135___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_135__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_135__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_136 (0x00A8F720) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_136___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_136__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_136__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_137 (0x00A8F724) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_137___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_137__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_137__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_138 (0x00A8F728) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_138___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_138__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_138__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_139 (0x00A8F72C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_139___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_139__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_139__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_140 (0x00A8F730) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_140___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_140__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_140__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_141 (0x00A8F734) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_141___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_141__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_141__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_142 (0x00A8F738) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_142___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_142__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_142__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_143 (0x00A8F73C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_143___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_143__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_143__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_144 (0x00A8F740) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_144___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_144__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_144__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_145 (0x00A8F744) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_145___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_145__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_145__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_146 (0x00A8F748) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_146___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_146__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_146__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_147 (0x00A8F74C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_147___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_147__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_147__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_148 (0x00A8F750) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_148___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_148__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_148__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_149 (0x00A8F754) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_149___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_149__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_149__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_150 (0x00A8F758) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_150___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_150__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_150__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_151 (0x00A8F75C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_151___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_151__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_151__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_152 (0x00A8F760) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_152___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_152__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_152__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_153 (0x00A8F764) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_153___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_153__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_153__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_154 (0x00A8F768) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_154___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_154__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_154__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_155 (0x00A8F76C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_155___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_155__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_155__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_156 (0x00A8F770) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_156___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_156__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_156__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_157 (0x00A8F774) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_157___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_157__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_157__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_158 (0x00A8F778) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_158___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_158__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_158__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_159 (0x00A8F77C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_159___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_159__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_159__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_160 (0x00A8F780) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_160___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_160__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_160__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_161 (0x00A8F784) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_161___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_161__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_161__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_162 (0x00A8F788) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_162___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_162__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_162__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_163 (0x00A8F78C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_163___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_163__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_163__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_164 (0x00A8F790) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_164___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_164__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_164__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_165 (0x00A8F794) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_165___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_165__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_165__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_166 (0x00A8F798) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_166___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_166__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_166__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_167 (0x00A8F79C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_167___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_167__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_167__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_168 (0x00A8F7A0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_168___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_168__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_168__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_169 (0x00A8F7A4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_169___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_169__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_169__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_170 (0x00A8F7A8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_170___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_170__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_170__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_171 (0x00A8F7AC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_171___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_171__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_171__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_172 (0x00A8F7B0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_172___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_172__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_172__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_173 (0x00A8F7B4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_173___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_173__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_173__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_174 (0x00A8F7B8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_174___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_174__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_174__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_175 (0x00A8F7BC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_175___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_175__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_175__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_176 (0x00A8F7C0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_176___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_176__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_176__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_177 (0x00A8F7C4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_177___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_177__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_177__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_178 (0x00A8F7C8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_178___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_178__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_178__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_179 (0x00A8F7CC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_179___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_179__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_179__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_180 (0x00A8F7D0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_180___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_180__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_180__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_181 (0x00A8F7D4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_181___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_181__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_181__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_182 (0x00A8F7D8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_182___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_182__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_182__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_183 (0x00A8F7DC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_183___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_183__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_183__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_184 (0x00A8F7E0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_184___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_184__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_184__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_185 (0x00A8F7E4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_185___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_185__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_185__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_186 (0x00A8F7E8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_186___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_186__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_186__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_187 (0x00A8F7EC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_187___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_187__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_187__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_188 (0x00A8F7F0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_188___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_188__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_188__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_189 (0x00A8F7F4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_189___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_189__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_189__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_190 (0x00A8F7F8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_190___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_190__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_190__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_191 (0x00A8F7FC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_191___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_191__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_191__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_192 (0x00A8F800) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_192___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_192__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_192__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_193 (0x00A8F804) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_193___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_193__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_193__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_194 (0x00A8F808) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_194___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_194__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_194__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_195 (0x00A8F80C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_195___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_195__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_195__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_196 (0x00A8F810) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_196___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_196__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_196__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_197 (0x00A8F814) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_197___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_197__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_197__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_198 (0x00A8F818) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_198___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_198__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_198__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_199 (0x00A8F81C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_199___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_199__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_199__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_200 (0x00A8F820) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_200___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_200__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_200__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_201 (0x00A8F824) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_201___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_201__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_201__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_202 (0x00A8F828) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_202___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_202__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_202__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_203 (0x00A8F82C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_203___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_203__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_203__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_204 (0x00A8F830) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_204___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_204__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_204__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_205 (0x00A8F834) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_205___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_205__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_205__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_206 (0x00A8F838) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_206___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_206__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_206__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_207 (0x00A8F83C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_207___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_207__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_207__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_208 (0x00A8F840) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_208___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_208__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_208__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_209 (0x00A8F844) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_209___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_209__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_209__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_210 (0x00A8F848) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_210___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_210__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_210__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_211 (0x00A8F84C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_211___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_211__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_211__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_212 (0x00A8F850) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_212___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_212__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_212__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_213 (0x00A8F854) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_213___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_213__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_213__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_214 (0x00A8F858) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_214___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_214__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_214__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_215 (0x00A8F85C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_215___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_215__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_215__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_216 (0x00A8F860) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_216___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_216__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_216__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_217 (0x00A8F864) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_217___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_217__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_217__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_218 (0x00A8F868) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_218___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_218__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_218__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_219 (0x00A8F86C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_219___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_219__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_219__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_220 (0x00A8F870) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_220___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_220__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_220__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_221 (0x00A8F874) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_221___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_221__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_221__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_222 (0x00A8F878) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_222___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_222__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_222__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_223 (0x00A8F87C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_223___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_223__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_223__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_224 (0x00A8F880) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_224___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_224__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_224__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_225 (0x00A8F884) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_225___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_225__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_225__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_226 (0x00A8F888) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_226___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_226__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_226__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_227 (0x00A8F88C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_227___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_227__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_227__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_228 (0x00A8F890) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_228___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_228__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_228__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_229 (0x00A8F894) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_229___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_229__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_229__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_230 (0x00A8F898) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_230___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_230__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_230__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_231 (0x00A8F89C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_231___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_231__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_231__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_232 (0x00A8F8A0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_232___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_232__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_232__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_233 (0x00A8F8A4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_233___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_233__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_233__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_234 (0x00A8F8A8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_234___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_234__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_234__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_235 (0x00A8F8AC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_235___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_235__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_235__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_236 (0x00A8F8B0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_236___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_236__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_236__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_237 (0x00A8F8B4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_237___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_237__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_237__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_238 (0x00A8F8B8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_238___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_238__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_238__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_239 (0x00A8F8BC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_239___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_239__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_239__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_240 (0x00A8F8C0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_240___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_240__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_240__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_241 (0x00A8F8C4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_241___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_241__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_241__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_242 (0x00A8F8C8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_242___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_242__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_242__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_243 (0x00A8F8CC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_243___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_243__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_243__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_244 (0x00A8F8D0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_244___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_244__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_244__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_245 (0x00A8F8D4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_245___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_245__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_245__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_246 (0x00A8F8D8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_246___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_246__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_246__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_247 (0x00A8F8DC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_247___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_247__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_247__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_248 (0x00A8F8E0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_248___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_248__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_248__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_249 (0x00A8F8E4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_249___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_249__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_249__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_250 (0x00A8F8E8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_250___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_250__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_250__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_251 (0x00A8F8EC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_251___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_251__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_251__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_252 (0x00A8F8F0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_252___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_252__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_252__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_253 (0x00A8F8F4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_253___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_253__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_253__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_254 (0x00A8F8F8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_254___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_254__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_254__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_255 (0x00A8F8FC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_255___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_255__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_255__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_256 (0x00A8F900) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_256___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_256__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_256__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_257 (0x00A8F904) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_257___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_257__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_257__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_258 (0x00A8F908) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_258___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_258__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_258__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_259 (0x00A8F90C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_259___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_259__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_259__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_260 (0x00A8F910) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_260___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_260__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_260__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_261 (0x00A8F914) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_261___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_261__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_261__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_262 (0x00A8F918) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_262___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_262__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_262__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_263 (0x00A8F91C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_263___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_263__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_263__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_264 (0x00A8F920) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_264___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_264__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_264__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_265 (0x00A8F924) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_265___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_265__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_265__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_266 (0x00A8F928) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_266___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_266__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_266__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_267 (0x00A8F92C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_267___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_267__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_267__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_268 (0x00A8F930) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_268___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_268__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_268__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_269 (0x00A8F934) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_269___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_269__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_269__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_270 (0x00A8F938) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_270___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_270__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_270__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_271 (0x00A8F93C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_271___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_271__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_271__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_272 (0x00A8F940) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_272___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_272__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_272__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_273 (0x00A8F944) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_273___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_273__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_273__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_274 (0x00A8F948) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_274___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_274__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_274__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_275 (0x00A8F94C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_275___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_275__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_275__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_276 (0x00A8F950) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_276___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_276__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_276__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_277 (0x00A8F954) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_277___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_277__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_277__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_278 (0x00A8F958) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_278___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_278__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_278__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_279 (0x00A8F95C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_279___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_279__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_279__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_280 (0x00A8F960) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_280___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_280__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_280__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_281 (0x00A8F964) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_281___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_281__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_281__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_282 (0x00A8F968) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_282___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_282__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_282__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_283 (0x00A8F96C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_283___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_283__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_283__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_284 (0x00A8F970) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_284___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_284__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_284__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_285 (0x00A8F974) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_285___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_285__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_285__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_286 (0x00A8F978) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_286___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_286__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_286__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_287 (0x00A8F97C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_287___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_287__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_287__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_288 (0x00A8F980) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_288___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_288__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_288__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_289 (0x00A8F984) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_289___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_289__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_289__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_290 (0x00A8F988) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_290___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_290__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_290__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_291 (0x00A8F98C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_291___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_291__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_291__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_292 (0x00A8F990) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_292___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_292__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_292__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_293 (0x00A8F994) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_293___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_293__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_293__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_294 (0x00A8F998) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_294___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_294__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_294__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_295 (0x00A8F99C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_295___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_295__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_295__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_296 (0x00A8F9A0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_296___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_296__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_296__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_297 (0x00A8F9A4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_297___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_297__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_297__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_298 (0x00A8F9A8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_298___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_298__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_298__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_299 (0x00A8F9AC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_299___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_299__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_299__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_300 (0x00A8F9B0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_300___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_300__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_300__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_301 (0x00A8F9B4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_301___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_301__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_301__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_302 (0x00A8F9B8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_302___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_302__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_302__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_303 (0x00A8F9BC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_303___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_303__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_303__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_304 (0x00A8F9C0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_304___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_304__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_304__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_305 (0x00A8F9C4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_305___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_305__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_305__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_306 (0x00A8F9C8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_306___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_306__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_306__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_307 (0x00A8F9CC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_307___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_307__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_307__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_308 (0x00A8F9D0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_308___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_308__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_308__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_309 (0x00A8F9D4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_309___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_309__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_309__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_310 (0x00A8F9D8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_310___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_310__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_310__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_311 (0x00A8F9DC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_311___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_311__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_311__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_312 (0x00A8F9E0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_312___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_312__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_312__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_313 (0x00A8F9E4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_313___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_313__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_313__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_314 (0x00A8F9E8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_314___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_314__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_314__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_315 (0x00A8F9EC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_315___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_315__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_315__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_316 (0x00A8F9F0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_316___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_316__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_316__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_317 (0x00A8F9F4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_317___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_317__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_317__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_318 (0x00A8F9F8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_318___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_318__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_318__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_319 (0x00A8F9FC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_319___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_319__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_319__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_320 (0x00A8FA00) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_320___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_320__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_320__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_321 (0x00A8FA04) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_321___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_321__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_321__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_322 (0x00A8FA08) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_322___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_322__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_322__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_323 (0x00A8FA0C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_323___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_323__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_323__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_324 (0x00A8FA10) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_324___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_324__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_324__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_325 (0x00A8FA14) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_325___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_325__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_325__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_326 (0x00A8FA18) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_326___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_326__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_326__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_327 (0x00A8FA1C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_327___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_327__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_327__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_328 (0x00A8FA20) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_328___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_328__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_328__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_329 (0x00A8FA24) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_329___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_329__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_329__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_330 (0x00A8FA28) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_330___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_330__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_330__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_331 (0x00A8FA2C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_331___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_331__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_331__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_332 (0x00A8FA30) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_332___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_332__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_332__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_333 (0x00A8FA34) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_333___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_333__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_333__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_334 (0x00A8FA38) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_334___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_334__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_334__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_335 (0x00A8FA3C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_335___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_335__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_335__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_336 (0x00A8FA40) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_336___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_336__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_336__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_337 (0x00A8FA44) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_337___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_337__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_337__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_338 (0x00A8FA48) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_338___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_338__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_338__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_339 (0x00A8FA4C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_339___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_339__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_339__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_340 (0x00A8FA50) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_340___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_340__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_340__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_341 (0x00A8FA54) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_341___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_341__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_341__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_342 (0x00A8FA58) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_342___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_342__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_342__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_343 (0x00A8FA5C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_343___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_343__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_343__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_344 (0x00A8FA60) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_344___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_344__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_344__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_345 (0x00A8FA64) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_345___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_345__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_345__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_346 (0x00A8FA68) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_346___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_346__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_346__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_347 (0x00A8FA6C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_347___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_347__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_347__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_348 (0x00A8FA70) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_348___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_348__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_348__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_349 (0x00A8FA74) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_349___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_349__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_349__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_350 (0x00A8FA78) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_350___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_350__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_350__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_351 (0x00A8FA7C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_351___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_351__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_351__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_352 (0x00A8FA80) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_352___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_352__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_352__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_353 (0x00A8FA84) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_353___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_353__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_353__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_354 (0x00A8FA88) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_354___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_354__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_354__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_355 (0x00A8FA8C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_355___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_355__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_355__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_356 (0x00A8FA90) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_356___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_356__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_356__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_357 (0x00A8FA94) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_357___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_357__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_357__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_358 (0x00A8FA98) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_358___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_358__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_358__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_359 (0x00A8FA9C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_359___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_359__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_359__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_360 (0x00A8FAA0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_360___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_360__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_360__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_361 (0x00A8FAA4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_361___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_361__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_361__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_362 (0x00A8FAA8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_362___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_362__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_362__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_363 (0x00A8FAAC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_363___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_363__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_363__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_364 (0x00A8FAB0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_364___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_364__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_364__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_365 (0x00A8FAB4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_365___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_365__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_365__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_366 (0x00A8FAB8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_366___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_366__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_366__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_367 (0x00A8FABC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_367___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_367__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_367__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_368 (0x00A8FAC0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_368___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_368__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_368__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_369 (0x00A8FAC4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_369___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_369__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_369__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_370 (0x00A8FAC8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_370___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_370__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_370__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_371 (0x00A8FACC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_371___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_371__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_371__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_372 (0x00A8FAD0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_372___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_372__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_372__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_373 (0x00A8FAD4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_373___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_373__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_373__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_374 (0x00A8FAD8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_374___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_374__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_374__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_375 (0x00A8FADC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_375___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_375__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_375__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_376 (0x00A8FAE0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_376___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_376__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_376__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_377 (0x00A8FAE4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_377___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_377__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_377__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_378 (0x00A8FAE8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_378___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_378__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_378__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_379 (0x00A8FAEC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_379___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_379__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_379__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_380 (0x00A8FAF0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_380___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_380__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_380__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_381 (0x00A8FAF4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_381___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_381__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_381__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_382 (0x00A8FAF8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_382___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_382__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_382__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_383 (0x00A8FAFC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_383___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_383__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_383__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_384 (0x00A8FB00) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_384___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_384__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_384__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_385 (0x00A8FB04) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_385___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_385__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_385__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_386 (0x00A8FB08) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_386___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_386__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_386__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_387 (0x00A8FB0C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_387___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_387__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_387__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_388 (0x00A8FB10) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_388___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_388__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_388__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_389 (0x00A8FB14) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_389___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_389__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_389__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_390 (0x00A8FB18) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_390___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_390__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_390__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_391 (0x00A8FB1C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_391___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_391__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_391__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_392 (0x00A8FB20) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_392___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_392__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_392__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_393 (0x00A8FB24) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_393___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_393__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_393__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_394 (0x00A8FB28) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_394___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_394__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_394__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_395 (0x00A8FB2C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_395___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_395__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_395__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_396 (0x00A8FB30) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_396___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_396__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_396__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_397 (0x00A8FB34) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_397___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_397__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_397__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_398 (0x00A8FB38) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_398___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_398__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_398__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_399 (0x00A8FB3C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_399___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_399__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_399__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_400 (0x00A8FB40) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_400___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_400__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_400__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_401 (0x00A8FB44) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_401___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_401__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_401__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_402 (0x00A8FB48) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_402___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_402__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_402__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_403 (0x00A8FB4C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_403___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_403__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_403__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_404 (0x00A8FB50) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_404___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_404__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_404__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_405 (0x00A8FB54) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_405___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_405__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_405__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_406 (0x00A8FB58) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_406___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_406__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_406__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_407 (0x00A8FB5C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_407___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_407__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_407__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_408 (0x00A8FB60) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_408___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_408__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_408__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_409 (0x00A8FB64) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_409___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_409__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_409__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_410 (0x00A8FB68) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_410___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_410__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_410__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_411 (0x00A8FB6C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_411___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_411__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_411__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_412 (0x00A8FB70) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_412___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_412__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_412__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_413 (0x00A8FB74) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_413___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_413__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_413__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_414 (0x00A8FB78) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_414___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_414__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_414__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_415 (0x00A8FB7C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_415___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_415__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_415__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_416 (0x00A8FB80) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_416___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_416__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_416__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_417 (0x00A8FB84) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_417___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_417__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_417__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_418 (0x00A8FB88) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_418___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_418__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_418__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_419 (0x00A8FB8C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_419___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_419__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_419__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_420 (0x00A8FB90) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_420___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_420__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_420__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_421 (0x00A8FB94) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_421___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_421__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_421__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_422 (0x00A8FB98) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_422___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_422__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_422__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_423 (0x00A8FB9C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_423___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_423__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_423__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_424 (0x00A8FBA0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_424___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_424__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_424__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_425 (0x00A8FBA4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_425___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_425__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_425__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_426 (0x00A8FBA8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_426___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_426__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_426__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_427 (0x00A8FBAC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_427___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_427__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_427__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_428 (0x00A8FBB0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_428___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_428__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_428__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_429 (0x00A8FBB4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_429___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_429__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_429__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_430 (0x00A8FBB8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_430___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_430__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_430__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_431 (0x00A8FBBC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_431___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_431__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_431__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_432 (0x00A8FBC0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_432___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_432__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_432__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_433 (0x00A8FBC4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_433___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_433__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_433__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_434 (0x00A8FBC8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_434___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_434__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_434__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_435 (0x00A8FBCC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_435___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_435__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_435__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_436 (0x00A8FBD0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_436___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_436__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_436__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_437 (0x00A8FBD4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_437___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_437__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_437__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_438 (0x00A8FBD8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_438___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_438__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_438__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_439 (0x00A8FBDC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_439___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_439__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_439__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_440 (0x00A8FBE0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_440___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_440__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_440__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_441 (0x00A8FBE4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_441___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_441__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_441__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_442 (0x00A8FBE8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_442___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_442__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_442__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_443 (0x00A8FBEC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_443___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_443__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_443__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_444 (0x00A8FBF0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_444___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_444__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_444__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_445 (0x00A8FBF4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_445___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_445__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_445__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_446 (0x00A8FBF8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_446___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_446__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_446__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_447 (0x00A8FBFC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_447___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_447__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_447__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_448 (0x00A8FC00) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_448___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_448__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_448__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_449 (0x00A8FC04) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_449___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_449__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_449__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_450 (0x00A8FC08) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_450___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_450__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_450__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_451 (0x00A8FC0C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_451___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_451__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_451__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_452 (0x00A8FC10) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_452___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_452__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_452__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_453 (0x00A8FC14) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_453___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_453__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_453__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_454 (0x00A8FC18) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_454___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_454__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_454__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_455 (0x00A8FC1C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_455___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_455__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_455__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_456 (0x00A8FC20) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_456___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_456__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_456__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_457 (0x00A8FC24) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_457___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_457__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_457__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_458 (0x00A8FC28) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_458___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_458__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_458__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_459 (0x00A8FC2C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_459___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_459__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_459__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_460 (0x00A8FC30) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_460___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_460__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_460__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_461 (0x00A8FC34) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_461___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_461__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_461__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_462 (0x00A8FC38) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_462___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_462__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_462__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_463 (0x00A8FC3C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_463___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_463__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_463__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_464 (0x00A8FC40) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_464___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_464__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_464__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_465 (0x00A8FC44) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_465___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_465__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_465__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_466 (0x00A8FC48) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_466___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_466__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_466__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_467 (0x00A8FC4C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_467___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_467__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_467__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_468 (0x00A8FC50) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_468___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_468__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_468__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_469 (0x00A8FC54) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_469___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_469__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_469__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_470 (0x00A8FC58) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_470___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_470__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_470__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_471 (0x00A8FC5C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_471___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_471__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_471__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_472 (0x00A8FC60) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_472___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_472__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_472__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_473 (0x00A8FC64) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_473___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_473__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_473__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_474 (0x00A8FC68) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_474___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_474__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_474__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_475 (0x00A8FC6C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_475___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_475__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_475__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_476 (0x00A8FC70) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_476___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_476__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_476__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_477 (0x00A8FC74) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_477___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_477__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_477__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_478 (0x00A8FC78) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_478___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_478__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_478__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_479 (0x00A8FC7C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_479___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_479__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_479__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_480 (0x00A8FC80) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_480___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_480__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_480__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_481 (0x00A8FC84) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_481___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_481__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_481__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_482 (0x00A8FC88) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_482___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_482__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_482__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_483 (0x00A8FC8C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_483___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_483__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_483__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_484 (0x00A8FC90) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_484___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_484__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_484__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_485 (0x00A8FC94) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_485___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_485__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_485__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_486 (0x00A8FC98) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_486___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_486__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_486__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_487 (0x00A8FC9C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_487___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_487__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_487__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_488 (0x00A8FCA0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_488___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_488__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_488__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_489 (0x00A8FCA4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_489___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_489__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_489__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_490 (0x00A8FCA8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_490___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_490__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_490__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_491 (0x00A8FCAC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_491___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_491__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_491__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_492 (0x00A8FCB0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_492___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_492__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_492__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_493 (0x00A8FCB4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_493___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_493__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_493__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_494 (0x00A8FCB8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_494___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_494__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_494__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_495 (0x00A8FCBC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_495___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_495__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_495__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_496 (0x00A8FCC0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_496___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_496__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_496__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_497 (0x00A8FCC4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_497___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_497__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_497__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_498 (0x00A8FCC8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_498___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_498__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_498__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_499 (0x00A8FCCC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_499___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_499__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_499__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_500 (0x00A8FCD0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_500___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_500__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_500__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_501 (0x00A8FCD4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_501___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_501__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_501__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_502 (0x00A8FCD8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_502___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_502__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_502__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_503 (0x00A8FCDC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_503___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_503__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_503__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_504 (0x00A8FCE0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_504___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_504__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_504__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_505 (0x00A8FCE4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_505___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_505__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_505__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_506 (0x00A8FCE8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_506___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_506__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_506__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_507 (0x00A8FCEC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_507___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_507__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_507__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_508 (0x00A8FCF0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_508___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_508__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_508__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_509 (0x00A8FCF4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_509___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_509__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_509__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_510 (0x00A8FCF8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_510___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_510__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_510__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_511 (0x00A8FCFC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_511___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_511__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_511__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_512 (0x00A8FD00) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_512___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_512__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_512__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_513 (0x00A8FD04) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_513___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_513__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_513__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_514 (0x00A8FD08) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_514___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_514__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_514__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_515 (0x00A8FD0C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_515___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_515__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_515__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_516 (0x00A8FD10) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_516___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_516__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_516__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_517 (0x00A8FD14) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_517___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_517__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_517__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_518 (0x00A8FD18) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_518___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_518__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_518__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_519 (0x00A8FD1C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_519___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_519__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_519__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_520 (0x00A8FD20) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_520___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_520__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_520__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_521 (0x00A8FD24) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_521___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_521__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_521__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_522 (0x00A8FD28) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_522___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_522__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_522__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_523 (0x00A8FD2C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_523___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_523__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_523__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_524 (0x00A8FD30) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_524___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_524__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_524__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_525 (0x00A8FD34) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_525___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_525__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_525__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_526 (0x00A8FD38) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_526___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_526__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_526__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_527 (0x00A8FD3C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_527___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_527__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_527__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_528 (0x00A8FD40) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_528___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_528__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_528__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_529 (0x00A8FD44) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_529___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_529__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_529__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_530 (0x00A8FD48) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_530___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_530__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_530__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_531 (0x00A8FD4C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_531___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_531__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_531__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_532 (0x00A8FD50) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_532___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_532__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_532__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_533 (0x00A8FD54) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_533___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_533__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_533__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_534 (0x00A8FD58) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_534___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_534__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_534__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_535 (0x00A8FD5C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_535___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_535__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_535__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_536 (0x00A8FD60) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_536___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_536__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_536__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_537 (0x00A8FD64) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_537___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_537__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_537__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_538 (0x00A8FD68) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_538___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_538__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_538__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_539 (0x00A8FD6C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_539___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_539__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_539__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_540 (0x00A8FD70) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_540___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_540__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_540__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_541 (0x00A8FD74) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_541___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_541__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_541__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_542 (0x00A8FD78) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_542___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_542__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_542__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_543 (0x00A8FD7C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_543___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_543__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_543__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_544 (0x00A8FD80) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_544___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_544__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_544__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_545 (0x00A8FD84) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_545___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_545__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_545__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_546 (0x00A8FD88) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_546___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_546__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_546__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_547 (0x00A8FD8C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_547___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_547__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_547__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_548 (0x00A8FD90) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_548___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_548__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_548__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_549 (0x00A8FD94) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_549___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_549__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_549__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_550 (0x00A8FD98) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_550___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_550__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_550__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_551 (0x00A8FD9C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_551___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_551__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_551__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_552 (0x00A8FDA0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_552___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_552__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_552__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_553 (0x00A8FDA4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_553___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_553__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_553__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_554 (0x00A8FDA8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_554___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_554__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_554__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_555 (0x00A8FDAC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_555___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_555__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_555__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_556 (0x00A8FDB0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_556___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_556__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_556__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_557 (0x00A8FDB4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_557___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_557__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_557__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_558 (0x00A8FDB8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_558___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_558__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_558__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_559 (0x00A8FDBC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_559___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_559__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_559__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_560 (0x00A8FDC0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_560___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_560__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_560__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_561 (0x00A8FDC4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_561___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_561__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_561__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_562 (0x00A8FDC8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_562___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_562__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_562__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_563 (0x00A8FDCC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_563___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_563__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_563__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_564 (0x00A8FDD0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_564___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_564__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_564__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_565 (0x00A8FDD4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_565___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_565__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_565__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_566 (0x00A8FDD8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_566___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_566__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_566__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_567 (0x00A8FDDC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_567___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_567__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_567__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_568 (0x00A8FDE0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_568___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_568__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_568__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_569 (0x00A8FDE4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_569___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_569__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_569__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_570 (0x00A8FDE8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_570___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_570__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_570__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_571 (0x00A8FDEC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_571___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_571__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_571__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_572 (0x00A8FDF0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_572___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_572__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_572__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_573 (0x00A8FDF4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_573___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_573__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_573__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_574 (0x00A8FDF8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_574___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_574__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_574__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_575 (0x00A8FDFC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_575___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_575__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_575__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_576 (0x00A8FE00) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_576___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_576__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_576__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_577 (0x00A8FE04) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_577___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_577__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_577__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_578 (0x00A8FE08) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_578___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_578__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_578__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_579 (0x00A8FE0C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_579___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_579__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_579__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_580 (0x00A8FE10) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_580___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_580__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_580__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_581 (0x00A8FE14) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_581___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_581__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_581__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_582 (0x00A8FE18) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_582___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_582__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_582__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_583 (0x00A8FE1C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_583___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_583__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_583__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_584 (0x00A8FE20) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_584___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_584__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_584__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_585 (0x00A8FE24) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_585___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_585__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_585__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_586 (0x00A8FE28) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_586___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_586__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_586__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_587 (0x00A8FE2C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_587___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_587__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_587__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_588 (0x00A8FE30) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_588___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_588__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_588__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_589 (0x00A8FE34) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_589___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_589__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_589__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_590 (0x00A8FE38) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_590___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_590__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_590__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_591 (0x00A8FE3C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_591___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_591__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_591__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_592 (0x00A8FE40) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_592___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_592__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_592__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_593 (0x00A8FE44) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_593___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_593__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_593__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_594 (0x00A8FE48) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_594___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_594__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_594__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_595 (0x00A8FE4C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_595___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_595__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_595__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_596 (0x00A8FE50) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_596___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_596__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_596__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_597 (0x00A8FE54) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_597___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_597__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_597__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_598 (0x00A8FE58) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_598___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_598__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_598__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_599 (0x00A8FE5C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_599___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_599__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_599__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_600 (0x00A8FE60) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_600___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_600__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_600__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_601 (0x00A8FE64) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_601___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_601__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_601__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_602 (0x00A8FE68) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_602___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_602__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_602__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_603 (0x00A8FE6C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_603___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_603__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_603__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_604 (0x00A8FE70) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_604___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_604__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_604__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_605 (0x00A8FE74) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_605___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_605__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_605__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_606 (0x00A8FE78) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_606___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_606__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_606__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_607 (0x00A8FE7C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_607___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_607__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_607__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_608 (0x00A8FE80) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_608___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_608__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_608__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_609 (0x00A8FE84) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_609___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_609__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_609__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_610 (0x00A8FE88) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_610___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_610__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_610__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_611 (0x00A8FE8C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_611___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_611__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_611__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_612 (0x00A8FE90) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_612___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_612__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_612__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_613 (0x00A8FE94) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_613___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_613__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_613__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_614 (0x00A8FE98) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_614___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_614__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_614__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_615 (0x00A8FE9C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_615___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_615__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_615__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_616 (0x00A8FEA0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_616___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_616__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_616__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_617 (0x00A8FEA4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_617___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_617__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_617__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_618 (0x00A8FEA8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_618___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_618__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_618__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_619 (0x00A8FEAC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_619___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_619__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_619__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_620 (0x00A8FEB0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_620___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_620__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_620__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_621 (0x00A8FEB4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_621___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_621__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_621__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_622 (0x00A8FEB8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_622___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_622__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_622__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_623 (0x00A8FEBC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_623___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_623__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_623__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_624 (0x00A8FEC0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_624___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_624__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_624__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_625 (0x00A8FEC4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_625___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_625__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_625__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_626 (0x00A8FEC8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_626___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_626__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_626__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_627 (0x00A8FECC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_627___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_627__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_627__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_628 (0x00A8FED0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_628___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_628__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_628__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_629 (0x00A8FED4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_629___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_629__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_629__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_630 (0x00A8FED8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_630___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_630__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_630__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_631 (0x00A8FEDC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_631___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_631__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_631__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_632 (0x00A8FEE0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_632___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_632__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_632__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_633 (0x00A8FEE4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_633___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_633__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_633__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_634 (0x00A8FEE8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_634___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_634__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_634__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_635 (0x00A8FEEC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_635___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_635__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_635__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_636 (0x00A8FEF0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_636___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_636__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_636__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_637 (0x00A8FEF4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_637___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_637__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_637__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_638 (0x00A8FEF8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_638___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_638__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_638__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_639 (0x00A8FEFC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_639___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_639__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_639__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_640 (0x00A8FF00) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_640___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_640__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_640__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_641 (0x00A8FF04) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_641___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_641__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_641__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_642 (0x00A8FF08) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_642___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_642__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_642__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_643 (0x00A8FF0C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_643___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_643__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_643__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_644 (0x00A8FF10) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_644___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_644__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_644__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_645 (0x00A8FF14) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_645___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_645__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_645__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_646 (0x00A8FF18) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_646___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_646__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_646__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_647 (0x00A8FF1C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_647___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_647__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_647__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_648 (0x00A8FF20) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_648___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_648__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_648__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_649 (0x00A8FF24) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_649___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_649__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_649__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_650 (0x00A8FF28) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_650___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_650__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_650__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_651 (0x00A8FF2C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_651___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_651__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_651__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_652 (0x00A8FF30) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_652___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_652__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_652__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_653 (0x00A8FF34) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_653___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_653__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_653__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_654 (0x00A8FF38) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_654___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_654__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_654__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_655 (0x00A8FF3C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_655___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_655__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_655__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_656 (0x00A8FF40) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_656___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_656__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_656__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_657 (0x00A8FF44) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_657___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_657__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_657__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_658 (0x00A8FF48) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_658___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_658__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_658__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_659 (0x00A8FF4C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_659___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_659__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_659__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_660 (0x00A8FF50) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_660___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_660__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_660__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_661 (0x00A8FF54) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_661___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_661__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_661__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_662 (0x00A8FF58) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_662___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_662__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_662__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_663 (0x00A8FF5C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_663___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_663__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_663__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_664 (0x00A8FF60) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_664___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_664__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_664__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_665 (0x00A8FF64) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_665___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_665__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_665__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_666 (0x00A8FF68) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_666___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_666__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_666__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_667 (0x00A8FF6C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_667___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_667__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_667__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_668 (0x00A8FF70) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_668___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_668__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_668__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_669 (0x00A8FF74) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_669___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_669__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_669__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_670 (0x00A8FF78) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_670___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_670__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_670__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_671 (0x00A8FF7C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_671___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_671__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_671__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_672 (0x00A8FF80) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_672___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_672__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_672__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_673 (0x00A8FF84) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_673___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_673__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_673__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_674 (0x00A8FF88) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_674___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_674__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_674__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_675 (0x00A8FF8C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_675___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_675__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_675__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_676 (0x00A8FF90) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_676___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_676__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_676__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_677 (0x00A8FF94) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_677___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_677__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_677__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_678 (0x00A8FF98) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_678___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_678__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_678__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_679 (0x00A8FF9C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_679___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_679__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_679__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_680 (0x00A8FFA0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_680___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_680__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_680__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_681 (0x00A8FFA4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_681___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_681__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_681__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_682 (0x00A8FFA8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_682___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_682__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_682__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_683 (0x00A8FFAC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_683___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_683__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_683__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_684 (0x00A8FFB0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_684___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_684__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_684__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_685 (0x00A8FFB4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_685___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_685__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_685__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_686 (0x00A8FFB8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_686___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_686__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_686__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_687 (0x00A8FFBC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_687___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_687__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_687__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_688 (0x00A8FFC0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_688___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_688__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_688__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_689 (0x00A8FFC4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_689___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_689__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_689__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_690 (0x00A8FFC8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_690___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_690__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_690__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_691 (0x00A8FFCC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_691___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_691__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_691__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_692 (0x00A8FFD0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_692___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_692__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_692__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_693 (0x00A8FFD4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_693___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_693__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_693__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_694 (0x00A8FFD8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_694___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_694__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_694__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_695 (0x00A8FFDC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_695___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_695__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_695__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_696 (0x00A8FFE0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_696___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_696__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_696__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_697 (0x00A8FFE4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_697___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_697__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_697__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_698 (0x00A8FFE8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_698___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_698__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_698__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_699 (0x00A8FFEC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_699___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_699__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_699__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_700 (0x00A8FFF0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_700___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_700__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_700__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_701 (0x00A8FFF4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_701___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_701__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_701__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_702 (0x00A8FFF8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_702___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_702__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_702__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_703 (0x00A8FFFC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_703___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_703__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_703__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_704 (0x00A90000) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_704___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_704__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_704__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_705 (0x00A90004) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_705___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_705__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_705__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_706 (0x00A90008) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_706___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_706__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_706__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_707 (0x00A9000C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_707___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_707__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_707__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_708 (0x00A90010) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_708___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_708__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_708__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_709 (0x00A90014) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_709___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_709__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_709__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_710 (0x00A90018) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_710___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_710__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_710__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_711 (0x00A9001C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_711___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_711__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_711__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_712 (0x00A90020) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_712___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_712__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_712__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_713 (0x00A90024) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_713___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_713__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_713__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_714 (0x00A90028) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_714___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_714__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_714__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_715 (0x00A9002C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_715___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_715__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_715__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_716 (0x00A90030) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_716___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_716__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_716__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_717 (0x00A90034) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_717___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_717__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_717__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_718 (0x00A90038) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_718___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_718__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_718__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_719 (0x00A9003C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_719___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_719__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_719__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_720 (0x00A90040) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_720___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_720__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_720__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_721 (0x00A90044) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_721___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_721__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_721__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_722 (0x00A90048) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_722___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_722__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_722__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_723 (0x00A9004C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_723___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_723__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_723__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_724 (0x00A90050) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_724___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_724__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_724__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_725 (0x00A90054) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_725___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_725__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_725__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_726 (0x00A90058) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_726___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_726__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_726__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_727 (0x00A9005C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_727___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_727__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_727__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_728 (0x00A90060) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_728___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_728__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_728__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_729 (0x00A90064) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_729___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_729__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_729__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_730 (0x00A90068) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_730___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_730__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_730__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_731 (0x00A9006C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_731___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_731__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_731__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_732 (0x00A90070) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_732___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_732__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_732__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_733 (0x00A90074) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_733___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_733__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_733__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_734 (0x00A90078) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_734___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_734__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_734__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_735 (0x00A9007C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_735___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_735__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_735__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_736 (0x00A90080) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_736___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_736__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_736__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_737 (0x00A90084) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_737___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_737__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_737__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_738 (0x00A90088) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_738___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_738__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_738__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_739 (0x00A9008C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_739___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_739__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_739__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_740 (0x00A90090) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_740___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_740__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_740__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_741 (0x00A90094) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_741___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_741__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_741__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_742 (0x00A90098) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_742___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_742__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_742__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_743 (0x00A9009C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_743___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_743__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_743__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_744 (0x00A900A0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_744___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_744__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_744__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_745 (0x00A900A4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_745___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_745__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_745__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_746 (0x00A900A8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_746___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_746__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_746__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_747 (0x00A900AC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_747___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_747__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_747__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_748 (0x00A900B0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_748___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_748__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_748__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_749 (0x00A900B4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_749___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_749__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_749__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_750 (0x00A900B8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_750___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_750__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_750__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_751 (0x00A900BC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_751___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_751__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_751__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_752 (0x00A900C0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_752___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_752__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_752__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_753 (0x00A900C4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_753___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_753__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_753__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_754 (0x00A900C8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_754___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_754__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_754__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_755 (0x00A900CC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_755___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_755__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_755__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_756 (0x00A900D0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_756___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_756__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_756__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_757 (0x00A900D4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_757___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_757__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_757__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_758 (0x00A900D8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_758___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_758__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_758__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_759 (0x00A900DC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_759___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_759__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_759__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_760 (0x00A900E0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_760___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_760__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_760__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_761 (0x00A900E4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_761___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_761__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_761__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_762 (0x00A900E8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_762___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_762__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_762__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_763 (0x00A900EC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_763___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_763__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_763__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_764 (0x00A900F0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_764___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_764__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_764__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_765 (0x00A900F4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_765___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_765__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_765__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_766 (0x00A900F8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_766___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_766__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_766__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_767 (0x00A900FC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_767___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_767__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_767__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_768 (0x00A90100) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_768___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_768__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_768__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_769 (0x00A90104) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_769___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_769__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_769__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_770 (0x00A90108) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_770___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_770__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_770__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_771 (0x00A9010C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_771___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_771__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_771__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_772 (0x00A90110) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_772___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_772__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_772__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_773 (0x00A90114) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_773___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_773__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_773__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_774 (0x00A90118) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_774___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_774__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_774__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_775 (0x00A9011C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_775___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_775__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_775__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_776 (0x00A90120) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_776___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_776__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_776__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_777 (0x00A90124) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_777___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_777__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_777__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_778 (0x00A90128) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_778___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_778__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_778__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_779 (0x00A9012C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_779___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_779__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_779__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_780 (0x00A90130) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_780___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_780__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_780__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_781 (0x00A90134) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_781___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_781__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_781__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_782 (0x00A90138) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_782___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_782__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_782__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_783 (0x00A9013C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_783___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_783__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_783__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_784 (0x00A90140) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_784___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_784__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_784__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_785 (0x00A90144) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_785___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_785__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_785__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_786 (0x00A90148) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_786___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_786__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_786__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_787 (0x00A9014C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_787___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_787__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_787__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_788 (0x00A90150) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_788___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_788__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_788__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_789 (0x00A90154) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_789___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_789__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_789__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_790 (0x00A90158) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_790___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_790__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_790__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_791 (0x00A9015C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_791___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_791__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_791__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_792 (0x00A90160) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_792___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_792__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_792__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_793 (0x00A90164) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_793___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_793__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_793__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_794 (0x00A90168) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_794___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_794__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_794__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_795 (0x00A9016C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_795___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_795__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_795__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_796 (0x00A90170) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_796___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_796__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_796__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_797 (0x00A90174) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_797___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_797__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_797__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_798 (0x00A90178) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_798___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_798__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_798__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_799 (0x00A9017C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_799___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_799__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_799__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_800 (0x00A90180) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_800___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_800__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_800__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_801 (0x00A90184) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_801___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_801__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_801__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_802 (0x00A90188) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_802___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_802__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_802__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_803 (0x00A9018C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_803___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_803__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_803__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_804 (0x00A90190) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_804___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_804__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_804__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_805 (0x00A90194) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_805___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_805__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_805__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_806 (0x00A90198) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_806___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_806__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_806__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_807 (0x00A9019C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_807___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_807__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_807__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_808 (0x00A901A0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_808___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_808__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_808__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_809 (0x00A901A4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_809___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_809__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_809__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_810 (0x00A901A8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_810___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_810__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_810__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_811 (0x00A901AC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_811___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_811__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_811__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_812 (0x00A901B0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_812___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_812__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_812__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_813 (0x00A901B4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_813___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_813__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_813__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_814 (0x00A901B8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_814___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_814__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_814__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_815 (0x00A901BC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_815___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_815__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_815__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_816 (0x00A901C0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_816___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_816__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_816__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_817 (0x00A901C4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_817___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_817__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_817__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_818 (0x00A901C8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_818___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_818__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_818__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_819 (0x00A901CC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_819___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_819__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_819__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_820 (0x00A901D0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_820___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_820__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_820__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_821 (0x00A901D4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_821___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_821__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_821__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_822 (0x00A901D8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_822___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_822__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_822__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_823 (0x00A901DC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_823___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_823__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_823__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_824 (0x00A901E0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_824___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_824__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_824__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_825 (0x00A901E4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_825___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_825__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_825__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_826 (0x00A901E8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_826___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_826__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_826__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_827 (0x00A901EC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_827___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_827__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_827__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_828 (0x00A901F0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_828___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_828__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_828__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_829 (0x00A901F4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_829___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_829__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_829__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_830 (0x00A901F8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_830___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_830__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_830__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_831 (0x00A901FC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_831___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_831__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_831__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_832 (0x00A90200) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_832___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_832__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_832__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_833 (0x00A90204) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_833___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_833__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_833__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_834 (0x00A90208) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_834___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_834__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_834__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_835 (0x00A9020C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_835___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_835__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_835__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_836 (0x00A90210) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_836___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_836__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_836__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_837 (0x00A90214) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_837___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_837__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_837__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_838 (0x00A90218) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_838___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_838__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_838__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_839 (0x00A9021C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_839___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_839__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_839__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_840 (0x00A90220) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_840___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_840__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_840__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_841 (0x00A90224) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_841___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_841__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_841__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_842 (0x00A90228) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_842___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_842__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_842__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_843 (0x00A9022C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_843___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_843__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_843__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_844 (0x00A90230) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_844___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_844__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_844__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_845 (0x00A90234) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_845___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_845__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_845__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_846 (0x00A90238) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_846___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_846__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_846__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_847 (0x00A9023C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_847___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_847__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_847__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_848 (0x00A90240) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_848___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_848__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_848__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_849 (0x00A90244) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_849___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_849__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_849__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_850 (0x00A90248) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_850___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_850__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_850__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_851 (0x00A9024C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_851___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_851__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_851__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_852 (0x00A90250) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_852___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_852__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_852__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_853 (0x00A90254) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_853___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_853__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_853__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_854 (0x00A90258) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_854___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_854__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_854__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_855 (0x00A9025C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_855___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_855__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_855__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_856 (0x00A90260) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_856___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_856__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_856__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_857 (0x00A90264) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_857___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_857__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_857__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_858 (0x00A90268) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_858___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_858__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_858__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_859 (0x00A9026C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_859___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_859__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_859__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_860 (0x00A90270) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_860___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_860__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_860__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_861 (0x00A90274) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_861___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_861__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_861__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_862 (0x00A90278) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_862___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_862__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_862__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_863 (0x00A9027C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_863___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_863__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_863__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_864 (0x00A90280) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_864___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_864__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_864__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_865 (0x00A90284) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_865___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_865__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_865__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_866 (0x00A90288) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_866___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_866__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_866__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_867 (0x00A9028C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_867___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_867__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_867__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_868 (0x00A90290) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_868___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_868__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_868__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_869 (0x00A90294) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_869___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_869__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_869__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_870 (0x00A90298) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_870___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_870__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_870__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_871 (0x00A9029C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_871___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_871__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_871__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_872 (0x00A902A0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_872___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_872__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_872__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_873 (0x00A902A4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_873___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_873__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_873__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_874 (0x00A902A8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_874___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_874__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_874__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_875 (0x00A902AC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_875___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_875__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_875__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_876 (0x00A902B0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_876___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_876__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_876__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_877 (0x00A902B4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_877___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_877__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_877__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_878 (0x00A902B8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_878___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_878__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_878__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_879 (0x00A902BC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_879___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_879__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_879__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_880 (0x00A902C0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_880___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_880__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_880__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_881 (0x00A902C4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_881___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_881__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_881__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_882 (0x00A902C8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_882___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_882__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_882__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_883 (0x00A902CC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_883___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_883__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_883__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_884 (0x00A902D0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_884___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_884__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_884__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_885 (0x00A902D4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_885___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_885__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_885__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_886 (0x00A902D8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_886___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_886__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_886__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_887 (0x00A902DC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_887___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_887__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_887__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_888 (0x00A902E0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_888___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_888__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_888__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_889 (0x00A902E4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_889___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_889__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_889__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_890 (0x00A902E8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_890___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_890__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_890__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_891 (0x00A902EC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_891___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_891__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_891__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_892 (0x00A902F0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_892___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_892__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_892__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_893 (0x00A902F4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_893___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_893__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_893__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_894 (0x00A902F8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_894___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_894__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_894__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_895 (0x00A902FC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_895___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_895__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_895__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_896 (0x00A90300) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_896___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_896__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_896__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_897 (0x00A90304) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_897___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_897__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_897__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_898 (0x00A90308) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_898___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_898__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_898__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_899 (0x00A9030C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_899___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_899__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_899__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_900 (0x00A90310) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_900___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_900__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_900__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_901 (0x00A90314) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_901___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_901__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_901__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_902 (0x00A90318) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_902___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_902__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_902__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_903 (0x00A9031C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_903___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_903__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_903__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_904 (0x00A90320) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_904___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_904__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_904__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_905 (0x00A90324) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_905___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_905__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_905__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_906 (0x00A90328) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_906___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_906__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_906__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_907 (0x00A9032C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_907___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_907__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_907__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_908 (0x00A90330) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_908___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_908__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_908__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_909 (0x00A90334) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_909___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_909__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_909__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_910 (0x00A90338) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_910___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_910__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_910__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_911 (0x00A9033C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_911___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_911__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_911__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_912 (0x00A90340) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_912___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_912__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_912__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_913 (0x00A90344) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_913___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_913__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_913__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_914 (0x00A90348) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_914___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_914__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_914__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_915 (0x00A9034C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_915___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_915__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_915__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_916 (0x00A90350) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_916___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_916__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_916__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_917 (0x00A90354) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_917___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_917__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_917__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_918 (0x00A90358) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_918___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_918__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_918__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_919 (0x00A9035C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_919___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_919__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_919__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_920 (0x00A90360) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_920___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_920__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_920__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_921 (0x00A90364) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_921___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_921__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_921__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_922 (0x00A90368) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_922___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_922__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_922__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_923 (0x00A9036C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_923___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_923__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_923__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_924 (0x00A90370) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_924___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_924__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_924__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_925 (0x00A90374) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_925___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_925__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_925__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_926 (0x00A90378) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_926___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_926__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_926__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_927 (0x00A9037C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_927___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_927__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_927__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_928 (0x00A90380) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_928___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_928__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_928__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_929 (0x00A90384) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_929___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_929__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_929__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_930 (0x00A90388) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_930___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_930__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_930__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_931 (0x00A9038C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_931___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_931__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_931__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_932 (0x00A90390) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_932___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_932__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_932__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_933 (0x00A90394) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_933___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_933__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_933__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_934 (0x00A90398) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_934___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_934__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_934__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_935 (0x00A9039C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_935___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_935__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_935__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_936 (0x00A903A0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_936___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_936__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_936__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_937 (0x00A903A4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_937___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_937__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_937__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_938 (0x00A903A8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_938___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_938__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_938__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_939 (0x00A903AC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_939___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_939__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_939__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_940 (0x00A903B0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_940___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_940__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_940__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_941 (0x00A903B4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_941___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_941__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_941__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_942 (0x00A903B8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_942___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_942__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_942__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_943 (0x00A903BC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_943___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_943__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_943__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_944 (0x00A903C0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_944___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_944__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_944__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_945 (0x00A903C4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_945___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_945__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_945__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_946 (0x00A903C8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_946___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_946__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_946__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_947 (0x00A903CC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_947___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_947__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_947__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_948 (0x00A903D0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_948___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_948__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_948__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_949 (0x00A903D4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_949___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_949__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_949__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_950 (0x00A903D8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_950___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_950__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_950__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_951 (0x00A903DC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_951___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_951__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_951__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_952 (0x00A903E0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_952___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_952__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_952__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_953 (0x00A903E4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_953___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_953__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_953__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_954 (0x00A903E8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_954___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_954__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_954__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_955 (0x00A903EC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_955___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_955__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_955__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_956 (0x00A903F0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_956___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_956__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_956__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_957 (0x00A903F4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_957___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_957__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_957__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_958 (0x00A903F8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_958___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_958__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_958__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_959 (0x00A903FC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_959___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_959__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_959__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_960 (0x00A90400) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_960___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_960__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_960__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_961 (0x00A90404) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_961___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_961__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_961__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_962 (0x00A90408) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_962___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_962__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_962__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_963 (0x00A9040C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_963___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_963__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_963__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_964 (0x00A90410) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_964___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_964__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_964__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_965 (0x00A90414) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_965___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_965__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_965__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_966 (0x00A90418) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_966___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_966__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_966__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_967 (0x00A9041C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_967___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_967__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_967__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_968 (0x00A90420) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_968___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_968__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_968__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_969 (0x00A90424) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_969___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_969__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_969__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_970 (0x00A90428) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_970___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_970__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_970__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_971 (0x00A9042C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_971___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_971__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_971__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_972 (0x00A90430) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_972___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_972__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_972__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_973 (0x00A90434) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_973___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_973__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_973__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_974 (0x00A90438) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_974___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_974__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_974__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_975 (0x00A9043C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_975___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_975__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_975__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_976 (0x00A90440) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_976___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_976__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_976__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_977 (0x00A90444) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_977___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_977__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_977__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_978 (0x00A90448) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_978___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_978__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_978__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_979 (0x00A9044C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_979___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_979__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_979__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_980 (0x00A90450) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_980___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_980__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_980__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_981 (0x00A90454) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_981___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_981__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_981__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_982 (0x00A90458) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_982___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_982__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_982__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_983 (0x00A9045C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_983___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_983__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_983__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_984 (0x00A90460) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_984___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_984__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_984__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_985 (0x00A90464) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_985___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_985__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_985__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_986 (0x00A90468) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_986___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_986__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_986__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_987 (0x00A9046C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_987___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_987__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_987__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_988 (0x00A90470) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_988___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_988__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_988__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_989 (0x00A90474) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_989___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_989__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_989__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_990 (0x00A90478) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_990___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_990__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_990__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_991 (0x00A9047C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_991___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_991__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_991__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_992 (0x00A90480) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_992___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_992__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_992__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_993 (0x00A90484) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_993___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_993__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_993__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_994 (0x00A90488) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_994___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_994__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_994__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_995 (0x00A9048C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_995___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_995__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_995__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_996 (0x00A90490) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_996___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_996__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_996__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_997 (0x00A90494) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_997___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_997__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_997__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_998 (0x00A90498) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_998___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_998__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_998__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_999 (0x00A9049C) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_999___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_999__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_999__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1000 (0x00A904A0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1000___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1000__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1000__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1001 (0x00A904A4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1001___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1001__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1001__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1002 (0x00A904A8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1002___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1002__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1002__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1003 (0x00A904AC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1003___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1003__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1003__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1004 (0x00A904B0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1004___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1004__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1004__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1005 (0x00A904B4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1005___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1005__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1005__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1006 (0x00A904B8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1006___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1006__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1006__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1007 (0x00A904BC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1007___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1007__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1007__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1008 (0x00A904C0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1008___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1008__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1008__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1009 (0x00A904C4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1009___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1009__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1009__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1010 (0x00A904C8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1010___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1010__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1010__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1011 (0x00A904CC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1011___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1011__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1011__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1012 (0x00A904D0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1012___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1012__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1012__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1013 (0x00A904D4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1013___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1013__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1013__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1014 (0x00A904D8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1014___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1014__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1014__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1015 (0x00A904DC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1015___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1015__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1015__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1016 (0x00A904E0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1016___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1016__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1016__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1017 (0x00A904E4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1017___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1017__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1017__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1018 (0x00A904E8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1018___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1018__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1018__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1019 (0x00A904EC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1019___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1019__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1019__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1020 (0x00A904F0) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1020___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1020__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1020__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1021 (0x00A904F4) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1021___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1021__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1021__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1022 (0x00A904F8) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1022___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1022__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1022__DATA___S 0 +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1023 (0x00A904FC) +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1023___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1023__DATA___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PDG_RESPONSE_FRAME_PARAMS_1023__DATA___S 0 + +#define WMAC0_TXPCU_R0_CLOCK_GATE_DISABLE (0x00A90500) +#define WMAC0_TXPCU_R0_CLOCK_GATE_DISABLE___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_CLOCK_GATE_DISABLE___POR 0x00000000 +#define WMAC0_TXPCU_R0_CLOCK_GATE_DISABLE__VALUE___POR 0x0000 +#define WMAC0_TXPCU_R0_CLOCK_GATE_DISABLE__VALUE___M 0x0000FFFF +#define WMAC0_TXPCU_R0_CLOCK_GATE_DISABLE__VALUE___S 0 +#define WMAC0_TXPCU_R0_CLOCK_GATE_DISABLE___M 0x0000FFFF +#define WMAC0_TXPCU_R0_CLOCK_GATE_DISABLE___S 0 + +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS (0x00A90504) +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS___POR 0x00000000 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHYRX_CBF_READ_ACK_RCVD___POR 0x0 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__MACRX_CBF_READ_REQ_SENT___POR 0x0 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHYTX_ABORT_ACK_RCVD___POR 0x0 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__MACTX_ABORT_REQ_SENT___POR 0x0 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__SYNTH_ON_ACK_RCVD___POR 0x0 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__SYNTH_ON_MSG_SENT___POR 0x0 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__SYNTH_OFF_ACK_RCVD___POR 0x0 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__SYNTH_OFF_SENT___POR 0x0 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_NAP_DONE_RCVD___POR 0x0 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_NAP_ACK_RCVD___POR 0x0 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_NAP_MSG_SENT___POR 0x0 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_ON_ACK_RCVD___POR 0x0 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_ON_MSG_SENT___POR 0x0 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_OFF_ACK_RCVD___POR 0x0 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_OFF_MSG_SENT___POR 0x0 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHYRX_CBF_READ_ACK_RCVD___M 0x00004000 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHYRX_CBF_READ_ACK_RCVD___S 14 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__MACRX_CBF_READ_REQ_SENT___M 0x00002000 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__MACRX_CBF_READ_REQ_SENT___S 13 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHYTX_ABORT_ACK_RCVD___M 0x00001000 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHYTX_ABORT_ACK_RCVD___S 12 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__MACTX_ABORT_REQ_SENT___M 0x00000800 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__MACTX_ABORT_REQ_SENT___S 11 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__SYNTH_ON_ACK_RCVD___M 0x00000400 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__SYNTH_ON_ACK_RCVD___S 10 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__SYNTH_ON_MSG_SENT___M 0x00000200 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__SYNTH_ON_MSG_SENT___S 9 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__SYNTH_OFF_ACK_RCVD___M 0x00000100 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__SYNTH_OFF_ACK_RCVD___S 8 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__SYNTH_OFF_SENT___M 0x00000080 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__SYNTH_OFF_SENT___S 7 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_NAP_DONE_RCVD___M 0x00000040 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_NAP_DONE_RCVD___S 6 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_NAP_ACK_RCVD___M 0x00000020 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_NAP_ACK_RCVD___S 5 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_NAP_MSG_SENT___M 0x00000010 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_NAP_MSG_SENT___S 4 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_ON_ACK_RCVD___M 0x00000008 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_ON_ACK_RCVD___S 3 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_ON_MSG_SENT___M 0x00000004 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_ON_MSG_SENT___S 2 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_OFF_ACK_RCVD___M 0x00000002 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_OFF_ACK_RCVD___S 1 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_OFF_MSG_SENT___M 0x00000001 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS__PHY_OFF_MSG_SENT___S 0 +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS___M 0x00007FFF +#define WMAC0_TXPCU_R0_PHY_ACK_STATUS___S 0 + +#define WMAC0_TXPCU_R0_ABORT_REQ_ACK (0x00A90508) +#define WMAC0_TXPCU_R0_ABORT_REQ_ACK___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_ABORT_REQ_ACK___POR 0x00000030 +#define WMAC0_TXPCU_R0_ABORT_REQ_ACK__DELAY___POR 0x0030 +#define WMAC0_TXPCU_R0_ABORT_REQ_ACK__DELAY___M 0x0000FFFF +#define WMAC0_TXPCU_R0_ABORT_REQ_ACK__DELAY___S 0 +#define WMAC0_TXPCU_R0_ABORT_REQ_ACK___M 0x0000FFFF +#define WMAC0_TXPCU_R0_ABORT_REQ_ACK___S 0 + +#define WMAC0_TXPCU_R0_PHY_OFF_ON_RESPONSE (0x00A9050C) +#define WMAC0_TXPCU_R0_PHY_OFF_ON_RESPONSE___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PHY_OFF_ON_RESPONSE___POR 0x01000100 +#define WMAC0_TXPCU_R0_PHY_OFF_ON_RESPONSE__PHY_ON_ACK_DELAY___POR 0x0100 +#define WMAC0_TXPCU_R0_PHY_OFF_ON_RESPONSE__PHY_OFF_ACK_DELAY___POR 0x0100 +#define WMAC0_TXPCU_R0_PHY_OFF_ON_RESPONSE__PHY_ON_ACK_DELAY___M 0xFFFF0000 +#define WMAC0_TXPCU_R0_PHY_OFF_ON_RESPONSE__PHY_ON_ACK_DELAY___S 16 +#define WMAC0_TXPCU_R0_PHY_OFF_ON_RESPONSE__PHY_OFF_ACK_DELAY___M 0x0000FFFF +#define WMAC0_TXPCU_R0_PHY_OFF_ON_RESPONSE__PHY_OFF_ACK_DELAY___S 0 +#define WMAC0_TXPCU_R0_PHY_OFF_ON_RESPONSE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PHY_OFF_ON_RESPONSE___S 0 + +#define WMAC0_TXPCU_R0_SYNTH_OFF_ON_RESPONSE (0x00A90510) +#define WMAC0_TXPCU_R0_SYNTH_OFF_ON_RESPONSE___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_SYNTH_OFF_ON_RESPONSE___POR 0x01000100 +#define WMAC0_TXPCU_R0_SYNTH_OFF_ON_RESPONSE__SYNTH_ON_ACK_DELAY___POR 0x0100 +#define WMAC0_TXPCU_R0_SYNTH_OFF_ON_RESPONSE__SYNTH_OFF_ACK_DELAY___POR 0x0100 +#define WMAC0_TXPCU_R0_SYNTH_OFF_ON_RESPONSE__SYNTH_ON_ACK_DELAY___M 0xFFFF0000 +#define WMAC0_TXPCU_R0_SYNTH_OFF_ON_RESPONSE__SYNTH_ON_ACK_DELAY___S 16 +#define WMAC0_TXPCU_R0_SYNTH_OFF_ON_RESPONSE__SYNTH_OFF_ACK_DELAY___M 0x0000FFFF +#define WMAC0_TXPCU_R0_SYNTH_OFF_ON_RESPONSE__SYNTH_OFF_ACK_DELAY___S 0 +#define WMAC0_TXPCU_R0_SYNTH_OFF_ON_RESPONSE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_SYNTH_OFF_ON_RESPONSE___S 0 + +#define WMAC0_TXPCU_R0_PHY_NAP_RESPONSE (0x00A90514) +#define WMAC0_TXPCU_R0_PHY_NAP_RESPONSE___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PHY_NAP_RESPONSE___POR 0x00000100 +#define WMAC0_TXPCU_R0_PHY_NAP_RESPONSE__PHY_NAP_ACK_DELAY___POR 0x0100 +#define WMAC0_TXPCU_R0_PHY_NAP_RESPONSE__PHY_NAP_ACK_DELAY___M 0x0000FFFF +#define WMAC0_TXPCU_R0_PHY_NAP_RESPONSE__PHY_NAP_ACK_DELAY___S 0 +#define WMAC0_TXPCU_R0_PHY_NAP_RESPONSE___M 0x0000FFFF +#define WMAC0_TXPCU_R0_PHY_NAP_RESPONSE___S 0 + +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_0 (0x00A90518) +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_0___POR 0x00000000 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_0__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_0___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_0___S 0 + +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_1 (0x00A9051C) +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_1___POR 0x00000000 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_1__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_1__VALUE___S 0 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_1___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_1___S 0 + +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_2 (0x00A90520) +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_2___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_2___POR 0x00000000 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_2__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_2__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_2__VALUE___S 0 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_2___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_2___S 0 + +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_3 (0x00A90524) +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_3___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_3___POR 0x00000000 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_3__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_3__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_3__VALUE___S 0 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_3___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_3___S 0 + +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_4 (0x00A90528) +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_4___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_4___POR 0x00000000 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_4__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_4__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_4__VALUE___S 0 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_4___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_4___S 0 + +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_5 (0x00A9052C) +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_5___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_5___POR 0x00000000 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_5__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_5__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_5__VALUE___S 0 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_5___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_5___S 0 + +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_6 (0x00A90530) +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_6___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_6___POR 0x00000000 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_6__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_6__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_6__VALUE___S 0 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_6___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_6___S 0 + +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_7 (0x00A90534) +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_7___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_7___POR 0x00000000 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_7__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_7__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_7__VALUE___S 0 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_7___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_7___S 0 + +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_8 (0x00A90538) +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_8___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_8___POR 0x00000000 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_8__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_8__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_8__VALUE___S 0 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_8___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_8___S 0 + +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_9 (0x00A9053C) +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_9___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_9___POR 0x00000000 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_9__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_9__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_9__VALUE___S 0 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_9___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_9___S 0 + +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_10 (0x00A90540) +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_10___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_10___POR 0x00000000 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_10__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_10__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_10__VALUE___S 0 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_10___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_10___S 0 + +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_11 (0x00A90544) +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_11___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_11___POR 0x00000000 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_11__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_11__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_11__VALUE___S 0 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_11___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_11___S 0 + +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_12 (0x00A90548) +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_12___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_12___POR 0x00000000 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_12__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_12__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_12__VALUE___S 0 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_12___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_12___S 0 + +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_13 (0x00A9054C) +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_13___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_13___POR 0x00000000 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_13__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_13__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_13__VALUE___S 0 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_13___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_13___S 0 + +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_14 (0x00A90550) +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_14___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_14___POR 0x00000000 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_14__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_14__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_14__VALUE___S 0 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_14___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_14___S 0 + +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_15 (0x00A90554) +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_15___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_15___POR 0x00000000 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_15__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_15__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_15__VALUE___S 0 +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_15___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_HT_CONTROL_OVERWRITE_IX_15___S 0 + +#define WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK (0x00A90558) +#define WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK___POR 0x00000000 +#define WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK__SW_RESP_4_MUBAR___POR 0x0 +#define WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK__SW_RESP_4_MURTS___POR 0x0 +#define WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK__SW_RESP_4_MUBRPOLL___POR 0x0 +#define WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK__SW_RESP_4_MUBAR___M 0x00000004 +#define WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK__SW_RESP_4_MUBAR___S 2 +#define WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK__SW_RESP_4_MURTS___M 0x00000002 +#define WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK__SW_RESP_4_MURTS___S 1 +#define WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK__SW_RESP_4_MUBRPOLL___M 0x00000001 +#define WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK__SW_RESP_4_MUBRPOLL___S 0 +#define WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK___M 0x00000007 +#define WMAC0_TXPCU_R0_TRIG_RESP_ENA_MASK___S 0 + +#define WMAC0_TXPCU_R0_ANTENNA_INFO_4_TRIG_RESP (0x00A9055C) +#define WMAC0_TXPCU_R0_ANTENNA_INFO_4_TRIG_RESP___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_ANTENNA_INFO_4_TRIG_RESP___POR 0x00000000 +#define WMAC0_TXPCU_R0_ANTENNA_INFO_4_TRIG_RESP__VAL___POR 0x000000 +#define WMAC0_TXPCU_R0_ANTENNA_INFO_4_TRIG_RESP__VAL___M 0x00FFFFFF +#define WMAC0_TXPCU_R0_ANTENNA_INFO_4_TRIG_RESP__VAL___S 0 +#define WMAC0_TXPCU_R0_ANTENNA_INFO_4_TRIG_RESP___M 0x00FFFFFF +#define WMAC0_TXPCU_R0_ANTENNA_INFO_4_TRIG_RESP___S 0 + +#define WMAC0_TXPCU_R0_ANTENNA_SHIFT_ENA_4_TRIG_RESP (0x00A90560) +#define WMAC0_TXPCU_R0_ANTENNA_SHIFT_ENA_4_TRIG_RESP___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_ANTENNA_SHIFT_ENA_4_TRIG_RESP___POR 0x00000000 +#define WMAC0_TXPCU_R0_ANTENNA_SHIFT_ENA_4_TRIG_RESP__PSPOLL_SHIFT_BACK_ENA___POR 0x0 +#define WMAC0_TXPCU_R0_ANTENNA_SHIFT_ENA_4_TRIG_RESP__MASK___POR 0x00000 +#define WMAC0_TXPCU_R0_ANTENNA_SHIFT_ENA_4_TRIG_RESP__PSPOLL_SHIFT_BACK_ENA___M 0x00020000 +#define WMAC0_TXPCU_R0_ANTENNA_SHIFT_ENA_4_TRIG_RESP__PSPOLL_SHIFT_BACK_ENA___S 17 +#define WMAC0_TXPCU_R0_ANTENNA_SHIFT_ENA_4_TRIG_RESP__MASK___M 0x0001FFFF +#define WMAC0_TXPCU_R0_ANTENNA_SHIFT_ENA_4_TRIG_RESP__MASK___S 0 +#define WMAC0_TXPCU_R0_ANTENNA_SHIFT_ENA_4_TRIG_RESP___M 0x0003FFFF +#define WMAC0_TXPCU_R0_ANTENNA_SHIFT_ENA_4_TRIG_RESP___S 0 + +#define WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_31_0 (0x00A90564) +#define WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_31_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_31_0___POR 0x00000000 +#define WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_31_0__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_31_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_31_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_31_0___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_31_0___S 0 + +#define WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_63_32 (0x00A90568) +#define WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_63_32___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_63_32___POR 0x00000000 +#define WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_63_32__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_63_32__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_63_32__VALUE___S 0 +#define WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_63_32___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PREV_START_OF_TX_TIMESTAMP_63_32___S 0 + +#define WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_31_0 (0x00A9056C) +#define WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_31_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_31_0___POR 0x00000000 +#define WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_31_0__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_31_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_31_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_31_0___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_31_0___S 0 + +#define WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_63_32 (0x00A90570) +#define WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_63_32___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_63_32___POR 0x00000000 +#define WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_63_32__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_63_32__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_63_32__VALUE___S 0 +#define WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_63_32___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_PREV_END_OF_LAST_RX_TIMESTAMP_63_32___S 0 + +#define WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_31_0 (0x00A90574) +#define WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_31_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_31_0___POR 0x00000000 +#define WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_31_0__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_31_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_31_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_31_0___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_31_0___S 0 + +#define WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_63_32 (0x00A90578) +#define WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_63_32___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_63_32___POR 0x00000000 +#define WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_63_32__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_63_32__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_63_32__VALUE___S 0 +#define WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_63_32___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_CURR_START_OF_TX_TIMESTAMP_63_32___S 0 + +#define WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_31_0 (0x00A9057C) +#define WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_31_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_31_0___POR 0x00000000 +#define WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_31_0__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_31_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_31_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_31_0___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_31_0___S 0 + +#define WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_63_32 (0x00A90580) +#define WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_63_32___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_63_32___POR 0x00000000 +#define WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_63_32__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_63_32__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_63_32__VALUE___S 0 +#define WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_63_32___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_CURR_END_OF_LAST_RX_TIMESTAMP_63_32___S 0 + +#define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL0 (0x00A90588) +#define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL0___POR 0x000000FF +#define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL0__NEXT_RX_DURATION___POR 0x0000 +#define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL0__CURRENT_TX_DURATION___POR 0x00FF +#define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL0__NEXT_RX_DURATION___M 0xFFFF0000 +#define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL0__NEXT_RX_DURATION___S 16 +#define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL0__CURRENT_TX_DURATION___M 0x0000FFFF +#define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL0__CURRENT_TX_DURATION___S 0 +#define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL0___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL0___S 0 + +#define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL1 (0x00A9058C) +#define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL1___POR 0x000000FF +#define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL1__ENABLE_EARLY_TX_STATUS_TLV___POR 0x0 +#define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL1__REMAINING_FES_TIME___POR 0x00FF +#define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL1__ENABLE_EARLY_TX_STATUS_TLV___M 0x00010000 +#define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL1__ENABLE_EARLY_TX_STATUS_TLV___S 16 +#define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL1__REMAINING_FES_TIME___M 0x0000FFFF +#define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL1__REMAINING_FES_TIME___S 0 +#define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL1___M 0x0001FFFF +#define WMAC0_TXPCU_R0_EARLY_COEX_TX_STATUS_TLV_CTRL1___S 0 + +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1 (0x00A90590) +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1___POR 0x00249249 +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1__SUB_CH3_CS_MASK___POR 0x09 +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1__SUB_CH2_CS_MASK___POR 0x09 +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1__SUB_CH1_CS_MASK___POR 0x09 +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1__SUB_CH0_CS_MASK___POR 0x09 +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1__SUB_CH3_CS_MASK___M 0x00FC0000 +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1__SUB_CH3_CS_MASK___S 18 +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1__SUB_CH2_CS_MASK___M 0x0003F000 +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1__SUB_CH2_CS_MASK___S 12 +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1__SUB_CH1_CS_MASK___M 0x00000FC0 +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1__SUB_CH1_CS_MASK___S 6 +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1__SUB_CH0_CS_MASK___M 0x0000003F +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1__SUB_CH0_CS_MASK___S 0 +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1___M 0x00FFFFFF +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL1___S 0 + +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2 (0x00A90594) +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2___POR 0x00249249 +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2__SUB_CH7_CS_MASK___POR 0x09 +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2__SUB_CH6_CS_MASK___POR 0x09 +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2__SUB_CH5_CS_MASK___POR 0x09 +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2__SUB_CH4_CS_MASK___POR 0x09 +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2__SUB_CH7_CS_MASK___M 0x00FC0000 +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2__SUB_CH7_CS_MASK___S 18 +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2__SUB_CH6_CS_MASK___M 0x0003F000 +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2__SUB_CH6_CS_MASK___S 12 +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2__SUB_CH5_CS_MASK___M 0x00000FC0 +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2__SUB_CH5_CS_MASK___S 6 +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2__SUB_CH4_CS_MASK___M 0x0000003F +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2__SUB_CH4_CS_MASK___S 0 +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2___M 0x00FFFFFF +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL2___S 0 + +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL3 (0x00A90598) +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL3___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL3___POR 0x01800000 +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL3__CHK_POINT___POR 0x3 +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL3__LENG_THR___POR 0x000000 +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL3__CHK_POINT___M 0x01800000 +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL3__CHK_POINT___S 23 +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL3__LENG_THR___M 0x007FFFFF +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL3__LENG_THR___S 0 +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL3___M 0x01FFFFFF +#define WMAC0_TXPCU_R0_TRIG_RESP_CS_CTRL3___S 0 + +#define WMAC0_TXPCU_R0_MU_CTS_TIMEOUT (0x00A9059C) +#define WMAC0_TXPCU_R0_MU_CTS_TIMEOUT___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_MU_CTS_TIMEOUT___POR 0x00003019 +#define WMAC0_TXPCU_R0_MU_CTS_TIMEOUT__RX_FRAME_MU_CTS_TIMEOUT___POR 0x30 +#define WMAC0_TXPCU_R0_MU_CTS_TIMEOUT__PRE_RX_FRAME_MU_CTS_TIMEOUT___POR 0x19 +#define WMAC0_TXPCU_R0_MU_CTS_TIMEOUT__RX_FRAME_MU_CTS_TIMEOUT___M 0x0000FF00 +#define WMAC0_TXPCU_R0_MU_CTS_TIMEOUT__RX_FRAME_MU_CTS_TIMEOUT___S 8 +#define WMAC0_TXPCU_R0_MU_CTS_TIMEOUT__PRE_RX_FRAME_MU_CTS_TIMEOUT___M 0x000000FF +#define WMAC0_TXPCU_R0_MU_CTS_TIMEOUT__PRE_RX_FRAME_MU_CTS_TIMEOUT___S 0 +#define WMAC0_TXPCU_R0_MU_CTS_TIMEOUT___M 0x0000FFFF +#define WMAC0_TXPCU_R0_MU_CTS_TIMEOUT___S 0 + +#define WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY (0x00A905A0) +#define WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY___POR 0x15001E00 +#define WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY__VHT_ACTION_FIELD___POR 0x15 +#define WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY__VHT_CBF_CQI_ACTION_FIELD___POR 0x00 +#define WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY__HE_ACTION_FIELD___POR 0x1E +#define WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY__HE_CBF_CQI_ACTION_FIELD___POR 0x00 +#define WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY__VHT_ACTION_FIELD___M 0xFF000000 +#define WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY__VHT_ACTION_FIELD___S 24 +#define WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY__VHT_CBF_CQI_ACTION_FIELD___M 0x00FF0000 +#define WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY__VHT_CBF_CQI_ACTION_FIELD___S 16 +#define WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY__HE_ACTION_FIELD___M 0x0000FF00 +#define WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY__HE_ACTION_FIELD___S 8 +#define WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY__HE_CBF_CQI_ACTION_FIELD___M 0x000000FF +#define WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY__HE_CBF_CQI_ACTION_FIELD___S 0 +#define WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_CBF_ACTION_CATEGORY___S 0 + +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_n(n) (0x00A905A4+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_n_nMIN 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_n_nMAX 3 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_n_ELEM 4 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_n___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_n___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_n__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_n__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_n__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_n___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_n___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_0 (0x00A905A4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_1 (0x00A905A8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_1__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_2 (0x00A905AC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_2___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_2__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_2__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_3 (0x00A905B0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_3___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_3__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_3_0_3__VALUE___S 0 + +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_n(n) (0x00A905B4+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_n_nMIN 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_n_nMAX 3 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_n_ELEM 4 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_n___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_n___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_n__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_n__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_n__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_n___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_n___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_0 (0x00A905B4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_1 (0x00A905B8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_1__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_2 (0x00A905BC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_2___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_2__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_2__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_3 (0x00A905C0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_3___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_3__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_CBF_11AX_7_4_3__VALUE___S 0 + +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_n(n) (0x00A905C4+0x4*(n)) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_n_nMIN 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_n_nMAX 13 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_n_ELEM 14 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_n___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_n___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_n__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_n__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_n__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_n___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_n___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_0 (0x00A905C4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_0__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_1 (0x00A905C8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_1__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_2 (0x00A905CC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_2___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_2__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_2__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_3 (0x00A905D0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_3___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_3__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_3__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_4 (0x00A905D4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_4___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_4__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_4__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_5 (0x00A905D8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_5___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_5__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_5__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_6 (0x00A905DC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_6___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_6__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_6__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_7 (0x00A905E0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_7___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_7__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_7__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_8 (0x00A905E4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_8___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_8__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_8__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_9 (0x00A905E8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_9___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_9__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_9__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_10 (0x00A905EC) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_10___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_10__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_10__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_11 (0x00A905F0) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_11___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_11__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_11__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_12 (0x00A905F4) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_12___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_12__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_12__VALUE___S 0 +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_13 (0x00A905F8) +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_13___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_13__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_RESP_FRAME_INDEX_LUT_UNASSOC_AX_EXT_13__VALUE___S 0 + +#define WMAC0_TXPCU_R0_MU_RTS_CTS_RESP_CTRL (0x00A905FC) +#define WMAC0_TXPCU_R0_MU_RTS_CTS_RESP_CTRL___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_MU_RTS_CTS_RESP_CTRL___POR 0x00000000 +#define WMAC0_TXPCU_R0_MU_RTS_CTS_RESP_CTRL__CTS_3DB_BOOST_ENABLE___POR 0x0 +#define WMAC0_TXPCU_R0_MU_RTS_CTS_RESP_CTRL__CTS_3DB_BOOST_ENABLE___M 0x00000001 +#define WMAC0_TXPCU_R0_MU_RTS_CTS_RESP_CTRL__CTS_3DB_BOOST_ENABLE___S 0 +#define WMAC0_TXPCU_R0_MU_RTS_CTS_RESP_CTRL___M 0x00000001 +#define WMAC0_TXPCU_R0_MU_RTS_CTS_RESP_CTRL___S 0 + +#define WMAC0_TXPCU_R0_TSF_TIMESTAMP_CAPTURE_CTRL (0x00A90600) +#define WMAC0_TXPCU_R0_TSF_TIMESTAMP_CAPTURE_CTRL___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_TSF_TIMESTAMP_CAPTURE_CTRL___POR 0x00000000 +#define WMAC0_TXPCU_R0_TSF_TIMESTAMP_CAPTURE_CTRL__CAPTURE_AT_START_TX___POR 0x0 +#define WMAC0_TXPCU_R0_TSF_TIMESTAMP_CAPTURE_CTRL__CAPTURE_AT_START_TX___M 0x00000001 +#define WMAC0_TXPCU_R0_TSF_TIMESTAMP_CAPTURE_CTRL__CAPTURE_AT_START_TX___S 0 +#define WMAC0_TXPCU_R0_TSF_TIMESTAMP_CAPTURE_CTRL___M 0x00000001 +#define WMAC0_TXPCU_R0_TSF_TIMESTAMP_CAPTURE_CTRL___S 0 + +#define WMAC0_TXPCU_R0_CBF_HT_INSERTION_CTRL (0x00A90604) +#define WMAC0_TXPCU_R0_CBF_HT_INSERTION_CTRL___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_CBF_HT_INSERTION_CTRL___POR 0x00000002 +#define WMAC0_TXPCU_R0_CBF_HT_INSERTION_CTRL__CBF_UPH_RSV_BITS___POR 0x0 +#define WMAC0_TXPCU_R0_CBF_HT_INSERTION_CTRL__CBF_UL_HEADROOM_OFFSET___POR 0x02 +#define WMAC0_TXPCU_R0_CBF_HT_INSERTION_CTRL__CBF_UPH_RSV_BITS___M 0x00000060 +#define WMAC0_TXPCU_R0_CBF_HT_INSERTION_CTRL__CBF_UPH_RSV_BITS___S 5 +#define WMAC0_TXPCU_R0_CBF_HT_INSERTION_CTRL__CBF_UL_HEADROOM_OFFSET___M 0x0000001F +#define WMAC0_TXPCU_R0_CBF_HT_INSERTION_CTRL__CBF_UL_HEADROOM_OFFSET___S 0 +#define WMAC0_TXPCU_R0_CBF_HT_INSERTION_CTRL___M 0x0000007F +#define WMAC0_TXPCU_R0_CBF_HT_INSERTION_CTRL___S 0 + +#define WMAC0_TXPCU_R0_CBF_HT_CONTROL_VAL (0x00A90608) +#define WMAC0_TXPCU_R0_CBF_HT_CONTROL_VAL___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_CBF_HT_CONTROL_VAL___POR 0x00000003 +#define WMAC0_TXPCU_R0_CBF_HT_CONTROL_VAL__CBF_HT_CONTROL___POR 0x00000003 +#define WMAC0_TXPCU_R0_CBF_HT_CONTROL_VAL__CBF_HT_CONTROL___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_CBF_HT_CONTROL_VAL__CBF_HT_CONTROL___S 0 +#define WMAC0_TXPCU_R0_CBF_HT_CONTROL_VAL___M 0xFFFFFFFF +#define WMAC0_TXPCU_R0_CBF_HT_CONTROL_VAL___S 0 + +#define WMAC0_TXPCU_R0_SPR_FLOPS (0x00A906CC) +#define WMAC0_TXPCU_R0_SPR_FLOPS___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_SPR_FLOPS___POR 0x00000000 +#define WMAC0_TXPCU_R0_SPR_FLOPS__SPR_FLOPS___POR 0x0000 +#define WMAC0_TXPCU_R0_SPR_FLOPS__SPR_FLOPS___M 0x0000FFFF +#define WMAC0_TXPCU_R0_SPR_FLOPS__SPR_FLOPS___S 0 +#define WMAC0_TXPCU_R0_SPR_FLOPS___M 0x0000FFFF +#define WMAC0_TXPCU_R0_SPR_FLOPS___S 0 + +#define WMAC0_TXPCU_R0_FLUSH_HANDLER (0x00A906D0) +#define WMAC0_TXPCU_R0_FLUSH_HANDLER___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_FLUSH_HANDLER___POR 0x000001F0 +#define WMAC0_TXPCU_R0_FLUSH_HANDLER__ENABLE_SELECTIVE_ABORT_ON_FLUSH___POR 0x1 +#define WMAC0_TXPCU_R0_FLUSH_HANDLER__ENABLE_ABORT_ON_FLUSH_CODE___POR 0xF +#define WMAC0_TXPCU_R0_FLUSH_HANDLER__TLV_MASK_ON_ABORT_COEX___POR 0x0 +#define WMAC0_TXPCU_R0_FLUSH_HANDLER__TLV_MASK_ON_ABORT_PDG___POR 0x0 +#define WMAC0_TXPCU_R0_FLUSH_HANDLER__TLV_MASK_ON_ABORT_RXPCU___POR 0x0 +#define WMAC0_TXPCU_R0_FLUSH_HANDLER__TLV_MASK_ON_ABORT_CRYPTO___POR 0x0 +#define WMAC0_TXPCU_R0_FLUSH_HANDLER__ENABLE_SELECTIVE_ABORT_ON_FLUSH___M 0x00000100 +#define WMAC0_TXPCU_R0_FLUSH_HANDLER__ENABLE_SELECTIVE_ABORT_ON_FLUSH___S 8 +#define WMAC0_TXPCU_R0_FLUSH_HANDLER__ENABLE_ABORT_ON_FLUSH_CODE___M 0x000000F0 +#define WMAC0_TXPCU_R0_FLUSH_HANDLER__ENABLE_ABORT_ON_FLUSH_CODE___S 4 +#define WMAC0_TXPCU_R0_FLUSH_HANDLER__TLV_MASK_ON_ABORT_COEX___M 0x00000008 +#define WMAC0_TXPCU_R0_FLUSH_HANDLER__TLV_MASK_ON_ABORT_COEX___S 3 +#define WMAC0_TXPCU_R0_FLUSH_HANDLER__TLV_MASK_ON_ABORT_PDG___M 0x00000004 +#define WMAC0_TXPCU_R0_FLUSH_HANDLER__TLV_MASK_ON_ABORT_PDG___S 2 +#define WMAC0_TXPCU_R0_FLUSH_HANDLER__TLV_MASK_ON_ABORT_RXPCU___M 0x00000002 +#define WMAC0_TXPCU_R0_FLUSH_HANDLER__TLV_MASK_ON_ABORT_RXPCU___S 1 +#define WMAC0_TXPCU_R0_FLUSH_HANDLER__TLV_MASK_ON_ABORT_CRYPTO___M 0x00000001 +#define WMAC0_TXPCU_R0_FLUSH_HANDLER__TLV_MASK_ON_ABORT_CRYPTO___S 0 +#define WMAC0_TXPCU_R0_FLUSH_HANDLER___M 0x000001FF +#define WMAC0_TXPCU_R0_FLUSH_HANDLER___S 0 + +#define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP (0x00A906D4) +#define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP___POR 0x00FAC688 +#define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_7___POR 0x7 +#define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_6___POR 0x6 +#define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_5___POR 0x5 +#define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_4___POR 0x4 +#define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_3___POR 0x3 +#define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_2___POR 0x2 +#define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_1___POR 0x1 +#define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_0___POR 0x0 +#define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_7___M 0x00E00000 +#define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_7___S 21 +#define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_6___M 0x001C0000 +#define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_6___S 18 +#define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_5___M 0x00038000 +#define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_5___S 15 +#define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_4___M 0x00007000 +#define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_4___S 12 +#define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_3___M 0x00000E00 +#define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_3___S 9 +#define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_2___M 0x000001C0 +#define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_2___S 6 +#define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_1___M 0x00000038 +#define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_1___S 3 +#define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_0___M 0x00000007 +#define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP__CHAN_MAP_0___S 0 +#define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP___M 0x00FFFFFF +#define WMAC0_TXPCU_R0_BQR_CHANNEL_MAP___S 0 + +#define WMAC0_TXPCU_R1_POWER_HEAD_ROOM_CTRL (0x00A91584) +#define WMAC0_TXPCU_R1_POWER_HEAD_ROOM_CTRL___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R1_POWER_HEAD_ROOM_CTRL___POR 0x00000000 +#define WMAC0_TXPCU_R1_POWER_HEAD_ROOM_CTRL__COEX_TX_STATUS_TX_ENA___POR 0x0 +#define WMAC0_TXPCU_R1_POWER_HEAD_ROOM_CTRL__MASK___POR 0x0000 +#define WMAC0_TXPCU_R1_POWER_HEAD_ROOM_CTRL__COEX_TX_STATUS_TX_ENA___M 0x00010000 +#define WMAC0_TXPCU_R1_POWER_HEAD_ROOM_CTRL__COEX_TX_STATUS_TX_ENA___S 16 +#define WMAC0_TXPCU_R1_POWER_HEAD_ROOM_CTRL__MASK___M 0x0000FFFF +#define WMAC0_TXPCU_R1_POWER_HEAD_ROOM_CTRL__MASK___S 0 +#define WMAC0_TXPCU_R1_POWER_HEAD_ROOM_CTRL___M 0x0001FFFF +#define WMAC0_TXPCU_R1_POWER_HEAD_ROOM_CTRL___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT (0x00A9160C) +#define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT__VALUE_B2___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT__VALUE_B1___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT__VALUE_B0___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT__VALUE_B2___M 0x00FF0000 +#define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT__VALUE_B2___S 16 +#define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT__VALUE_B1___M 0x0000FF00 +#define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT__VALUE_B1___S 8 +#define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT__VALUE_B0___M 0x000000FF +#define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT__VALUE_B0___S 0 +#define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT___M 0x00FFFFFF +#define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_TRANSMIT_CNT___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_RESP_CNT (0x00A91610) +#define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_RESP_CNT___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_RESP_CNT___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_RESP_CNT__VALUE_B1___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_RESP_CNT__VALUE_B0___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_RESP_CNT__VALUE_B1___M 0x0000FF00 +#define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_RESP_CNT__VALUE_B1___S 8 +#define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_RESP_CNT__VALUE_B0___M 0x000000FF +#define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_RESP_CNT__VALUE_B0___S 0 +#define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_RESP_CNT___M 0x0000FFFF +#define WMAC0_TXPCU_R1_DEBUG_COEX_TX_STATUS_RESP_CNT___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_COEX_SOFT_ABORT_CNT (0x00A91614) +#define WMAC0_TXPCU_R1_DEBUG_COEX_SOFT_ABORT_CNT___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_COEX_SOFT_ABORT_CNT___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_COEX_SOFT_ABORT_CNT__VALUE_B1___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_COEX_SOFT_ABORT_CNT__VALUE_B0___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_COEX_SOFT_ABORT_CNT__VALUE_B1___M 0x0000FF00 +#define WMAC0_TXPCU_R1_DEBUG_COEX_SOFT_ABORT_CNT__VALUE_B1___S 8 +#define WMAC0_TXPCU_R1_DEBUG_COEX_SOFT_ABORT_CNT__VALUE_B0___M 0x000000FF +#define WMAC0_TXPCU_R1_DEBUG_COEX_SOFT_ABORT_CNT__VALUE_B0___S 0 +#define WMAC0_TXPCU_R1_DEBUG_COEX_SOFT_ABORT_CNT___M 0x0000FFFF +#define WMAC0_TXPCU_R1_DEBUG_COEX_SOFT_ABORT_CNT___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_COEX_PHY_CTRL_CNT (0x00A91618) +#define WMAC0_TXPCU_R1_DEBUG_COEX_PHY_CTRL_CNT___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_COEX_PHY_CTRL_CNT___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_COEX_PHY_CTRL_CNT__VALUE___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_COEX_PHY_CTRL_CNT__VALUE___M 0x000000FF +#define WMAC0_TXPCU_R1_DEBUG_COEX_PHY_CTRL_CNT__VALUE___S 0 +#define WMAC0_TXPCU_R1_DEBUG_COEX_PHY_CTRL_CNT___M 0x000000FF +#define WMAC0_TXPCU_R1_DEBUG_COEX_PHY_CTRL_CNT___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_STATE (0x00A9161C) +#define WMAC0_TXPCU_R1_DEBUG_STATE___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_STATE___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_STATE__TX_DMA_STATE___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_STATE__GEN_CBF_RESP_REQ_CBF_STATE___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_STATE__GEN_CBF_RESP_CBF_WR_STATE___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_STATE__GEN_FRAME_SM_RX_BA_STATE___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_STATE__GEN_FRAME_SM_TX_STATE___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_STATE__FES_PREAMBLES_STATE___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_STATE__PREAM_STATE___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_STATE__STATE_TX___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_STATE__TX_DMA_STATE___M 0x3C000000 +#define WMAC0_TXPCU_R1_DEBUG_STATE__TX_DMA_STATE___S 26 +#define WMAC0_TXPCU_R1_DEBUG_STATE__GEN_CBF_RESP_REQ_CBF_STATE___M 0x03C00000 +#define WMAC0_TXPCU_R1_DEBUG_STATE__GEN_CBF_RESP_REQ_CBF_STATE___S 22 +#define WMAC0_TXPCU_R1_DEBUG_STATE__GEN_CBF_RESP_CBF_WR_STATE___M 0x00380000 +#define WMAC0_TXPCU_R1_DEBUG_STATE__GEN_CBF_RESP_CBF_WR_STATE___S 19 +#define WMAC0_TXPCU_R1_DEBUG_STATE__GEN_FRAME_SM_RX_BA_STATE___M 0x00070000 +#define WMAC0_TXPCU_R1_DEBUG_STATE__GEN_FRAME_SM_RX_BA_STATE___S 16 +#define WMAC0_TXPCU_R1_DEBUG_STATE__GEN_FRAME_SM_TX_STATE___M 0x0000E000 +#define WMAC0_TXPCU_R1_DEBUG_STATE__GEN_FRAME_SM_TX_STATE___S 13 +#define WMAC0_TXPCU_R1_DEBUG_STATE__FES_PREAMBLES_STATE___M 0x00001C00 +#define WMAC0_TXPCU_R1_DEBUG_STATE__FES_PREAMBLES_STATE___S 10 +#define WMAC0_TXPCU_R1_DEBUG_STATE__PREAM_STATE___M 0x000003C0 +#define WMAC0_TXPCU_R1_DEBUG_STATE__PREAM_STATE___S 6 +#define WMAC0_TXPCU_R1_DEBUG_STATE__STATE_TX___M 0x0000003F +#define WMAC0_TXPCU_R1_DEBUG_STATE__STATE_TX___S 0 +#define WMAC0_TXPCU_R1_DEBUG_STATE___M 0x3FFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_STATE___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_0 (0x00A91620) +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_0___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_0___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_0__INFORMATION___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_0__INFORMATION___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_0__INFORMATION___S 0 +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_0___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_0___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_1 (0x00A91624) +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_1___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_1___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_1__INFORMATION___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_1__INFORMATION___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_1__INFORMATION___S 0 +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_1___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_1___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_2 (0x00A91628) +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_2___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_2___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_2__INFORMATION___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_2__INFORMATION___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_2__INFORMATION___S 0 +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_2___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_2___S 0 + +#define WMAC0_TXPCU_R1_TRACEBUS_CTRL (0x00A9162C) +#define WMAC0_TXPCU_R1_TRACEBUS_CTRL___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R1_TRACEBUS_CTRL___POR 0x00000000 +#define WMAC0_TXPCU_R1_TRACEBUS_CTRL__SELECT___POR 0x00000000 +#define WMAC0_TXPCU_R1_TRACEBUS_CTRL__SELECT___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_TRACEBUS_CTRL__SELECT___S 0 +#define WMAC0_TXPCU_R1_TRACEBUS_CTRL___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_TRACEBUS_CTRL___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_LOWER (0x00A91630) +#define WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_LOWER___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_LOWER___POR 0x08000000 +#define WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_LOWER__VALUE___POR 0x08000000 +#define WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_LOWER__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_LOWER__VALUE___S 0 +#define WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_LOWER___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_LOWER___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_UPPER (0x00A91634) +#define WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_UPPER___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_UPPER___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_UPPER__VALUE___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_UPPER__VALUE___M 0x000000FF +#define WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_UPPER__VALUE___S 0 +#define WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_UPPER___M 0x000000FF +#define WMAC0_TXPCU_R1_DEBUG_TRACE_BUS_UPPER___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_START_TX_CNT (0x00A91638) +#define WMAC0_TXPCU_R1_DEBUG_START_TX_CNT___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_START_TX_CNT___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_START_TX_CNT__VALUE___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_START_TX_CNT__VALUE___M 0x000000FF +#define WMAC0_TXPCU_R1_DEBUG_START_TX_CNT__VALUE___S 0 +#define WMAC0_TXPCU_R1_DEBUG_START_TX_CNT___M 0x000000FF +#define WMAC0_TXPCU_R1_DEBUG_START_TX_CNT___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_TX_FLUSH_CNT (0x00A9163C) +#define WMAC0_TXPCU_R1_DEBUG_TX_FLUSH_CNT___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_TX_FLUSH_CNT___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_TX_FLUSH_CNT__VALUE___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_TX_FLUSH_CNT__VALUE___M 0x000000FF +#define WMAC0_TXPCU_R1_DEBUG_TX_FLUSH_CNT__VALUE___S 0 +#define WMAC0_TXPCU_R1_DEBUG_TX_FLUSH_CNT___M 0x000000FF +#define WMAC0_TXPCU_R1_DEBUG_TX_FLUSH_CNT___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_RTS_SUCCESS_CNT (0x00A91640) +#define WMAC0_TXPCU_R1_DEBUG_RTS_SUCCESS_CNT___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_RTS_SUCCESS_CNT___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_RTS_SUCCESS_CNT__VALUE___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_RTS_SUCCESS_CNT__VALUE___M 0x000000FF +#define WMAC0_TXPCU_R1_DEBUG_RTS_SUCCESS_CNT__VALUE___S 0 +#define WMAC0_TXPCU_R1_DEBUG_RTS_SUCCESS_CNT___M 0x000000FF +#define WMAC0_TXPCU_R1_DEBUG_RTS_SUCCESS_CNT___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_RTS_FAIL_CNT (0x00A91644) +#define WMAC0_TXPCU_R1_DEBUG_RTS_FAIL_CNT___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_RTS_FAIL_CNT___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_RTS_FAIL_CNT__VALUE___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_RTS_FAIL_CNT__VALUE___M 0x000000FF +#define WMAC0_TXPCU_R1_DEBUG_RTS_FAIL_CNT__VALUE___S 0 +#define WMAC0_TXPCU_R1_DEBUG_RTS_FAIL_CNT___M 0x000000FF +#define WMAC0_TXPCU_R1_DEBUG_RTS_FAIL_CNT___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_ACK_SUCCESS_CNT (0x00A91648) +#define WMAC0_TXPCU_R1_DEBUG_ACK_SUCCESS_CNT___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_ACK_SUCCESS_CNT___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_ACK_SUCCESS_CNT__VALUE___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_ACK_SUCCESS_CNT__VALUE___M 0x000000FF +#define WMAC0_TXPCU_R1_DEBUG_ACK_SUCCESS_CNT__VALUE___S 0 +#define WMAC0_TXPCU_R1_DEBUG_ACK_SUCCESS_CNT___M 0x000000FF +#define WMAC0_TXPCU_R1_DEBUG_ACK_SUCCESS_CNT___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_ACK_FAIL_CNT (0x00A9164C) +#define WMAC0_TXPCU_R1_DEBUG_ACK_FAIL_CNT___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_ACK_FAIL_CNT___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_ACK_FAIL_CNT__VALUE___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_ACK_FAIL_CNT__VALUE___M 0x000000FF +#define WMAC0_TXPCU_R1_DEBUG_ACK_FAIL_CNT__VALUE___S 0 +#define WMAC0_TXPCU_R1_DEBUG_ACK_FAIL_CNT___M 0x000000FF +#define WMAC0_TXPCU_R1_DEBUG_ACK_FAIL_CNT___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_RX_FRAME_CNT (0x00A91650) +#define WMAC0_TXPCU_R1_DEBUG_RX_FRAME_CNT___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_RX_FRAME_CNT___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_RX_FRAME_CNT__VALUE___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_RX_FRAME_CNT__VALUE___M 0x000000FF +#define WMAC0_TXPCU_R1_DEBUG_RX_FRAME_CNT__VALUE___S 0 +#define WMAC0_TXPCU_R1_DEBUG_RX_FRAME_CNT___M 0x000000FF +#define WMAC0_TXPCU_R1_DEBUG_RX_FRAME_CNT___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_PDG_RESPONSE_CNT (0x00A91654) +#define WMAC0_TXPCU_R1_DEBUG_PDG_RESPONSE_CNT___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_PDG_RESPONSE_CNT___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_PDG_RESPONSE_CNT__VALUE___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_PDG_RESPONSE_CNT__VALUE___M 0x000000FF +#define WMAC0_TXPCU_R1_DEBUG_PDG_RESPONSE_CNT__VALUE___S 0 +#define WMAC0_TXPCU_R1_DEBUG_PDG_RESPONSE_CNT___M 0x000000FF +#define WMAC0_TXPCU_R1_DEBUG_PDG_RESPONSE_CNT___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_SUCCESS_CNT (0x00A91658) +#define WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_SUCCESS_CNT___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_SUCCESS_CNT___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_SUCCESS_CNT__VALUE___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_SUCCESS_CNT__VALUE___M 0x000000FF +#define WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_SUCCESS_CNT__VALUE___S 0 +#define WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_SUCCESS_CNT___M 0x000000FF +#define WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_SUCCESS_CNT___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_FAIL_CNT (0x00A9165C) +#define WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_FAIL_CNT___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_FAIL_CNT___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_FAIL_CNT__VALUE___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_FAIL_CNT__VALUE___M 0x000000FF +#define WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_FAIL_CNT__VALUE___S 0 +#define WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_FAIL_CNT___M 0x000000FF +#define WMAC0_TXPCU_R1_DEBUG_RESP_FRAME_FAIL_CNT___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_STATUS_UPDATE_CNT (0x00A91660) +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_STATUS_UPDATE_CNT___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_STATUS_UPDATE_CNT___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_STATUS_UPDATE_CNT__VALUE___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_STATUS_UPDATE_CNT__VALUE___M 0x000000FF +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_STATUS_UPDATE_CNT__VALUE___S 0 +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_STATUS_UPDATE_CNT___M 0x000000FF +#define WMAC0_TXPCU_R1_DEBUG_TX_FES_STATUS_UPDATE_CNT___S 0 + +#define WMAC0_TXPCU_R1_EVENTMASK_IX_0 (0x00A91664) +#define WMAC0_TXPCU_R1_EVENTMASK_IX_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R1_EVENTMASK_IX_0___POR 0xFFFFFFFF +#define WMAC0_TXPCU_R1_EVENTMASK_IX_0__VALUE___POR 0xFFFFFFFF +#define WMAC0_TXPCU_R1_EVENTMASK_IX_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_EVENTMASK_IX_0__VALUE___S 0 +#define WMAC0_TXPCU_R1_EVENTMASK_IX_0___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_EVENTMASK_IX_0___S 0 + +#define WMAC0_TXPCU_R1_EVENTMASK_IX_1 (0x00A91668) +#define WMAC0_TXPCU_R1_EVENTMASK_IX_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R1_EVENTMASK_IX_1___POR 0xFFFFFFFF +#define WMAC0_TXPCU_R1_EVENTMASK_IX_1__VALUE___POR 0xFFFFFFFF +#define WMAC0_TXPCU_R1_EVENTMASK_IX_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_EVENTMASK_IX_1__VALUE___S 0 +#define WMAC0_TXPCU_R1_EVENTMASK_IX_1___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_EVENTMASK_IX_1___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_TLV (0x00A9166C) +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_TLV___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_TLV___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_TLV__SENT_COUNT___POR 0x0000 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_TLV__RCVD_COUNT___POR 0x0000 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_TLV__SENT_COUNT___M 0xFFFF0000 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_TLV__SENT_COUNT___S 16 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_TLV__RCVD_COUNT___M 0x0000FFFF +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_TLV__RCVD_COUNT___S 0 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_TLV___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_TLV___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0 (0x00A91670) +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0__SYNTH_OFF_CNT___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0__SYNTH_ON_CNT___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0__PHY_OFF_CNT___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0__PHY_ON_CNT___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0__SYNTH_OFF_CNT___M 0xFF000000 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0__SYNTH_OFF_CNT___S 24 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0__SYNTH_ON_CNT___M 0x00FF0000 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0__SYNTH_ON_CNT___S 16 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0__PHY_OFF_CNT___M 0x0000FF00 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0__PHY_OFF_CNT___S 8 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0__PHY_ON_CNT___M 0x000000FF +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0__PHY_ON_CNT___S 0 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT0___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1 (0x00A91674) +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1__PHYTX_SYNTH_OFF_ACK_CNT___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1__PHYTX_OFF_ACK_CNT___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1__PHYTX_ON_ACK_CNT___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1__MACTX_PHY_NAP_CNT___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1__PHYTX_SYNTH_OFF_ACK_CNT___M 0xFF000000 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1__PHYTX_SYNTH_OFF_ACK_CNT___S 24 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1__PHYTX_OFF_ACK_CNT___M 0x00FF0000 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1__PHYTX_OFF_ACK_CNT___S 16 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1__PHYTX_ON_ACK_CNT___M 0x0000FF00 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1__PHYTX_ON_ACK_CNT___S 8 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1__MACTX_PHY_NAP_CNT___M 0x000000FF +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1__MACTX_PHY_NAP_CNT___S 0 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT1___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2 (0x00A91678) +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2__PHYTX_ABORT_ACK_CNT___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2__PHYTX_ABORT_REQ_CNT___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2__PHYTX_NAP_ACK_CNT___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2__PHYTX_SYNTH_ON_ACK_CNT___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2__PHYTX_ABORT_ACK_CNT___M 0xFF000000 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2__PHYTX_ABORT_ACK_CNT___S 24 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2__PHYTX_ABORT_REQ_CNT___M 0x00FF0000 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2__PHYTX_ABORT_REQ_CNT___S 16 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2__PHYTX_NAP_ACK_CNT___M 0x0000FF00 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2__PHYTX_NAP_ACK_CNT___S 8 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2__PHYTX_SYNTH_ON_ACK_CNT___M 0x000000FF +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2__PHYTX_SYNTH_ON_ACK_CNT___S 0 +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_RX_MESSAGE_COUNT2___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0 (0x00A9167C) +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0__MACTX_ABORT_REQ_CNT___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0__MACTX_ABORT_ACK_CNT___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0__MACTX_PRE_PHY_DESC_CNT___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0__MAC_PKT_END_CNT___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0__MACTX_ABORT_REQ_CNT___M 0xFF000000 +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0__MACTX_ABORT_REQ_CNT___S 24 +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0__MACTX_ABORT_ACK_CNT___M 0x00FF0000 +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0__MACTX_ABORT_ACK_CNT___S 16 +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0__MACTX_PRE_PHY_DESC_CNT___M 0x0000FF00 +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0__MACTX_PRE_PHY_DESC_CNT___S 8 +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0__MAC_PKT_END_CNT___M 0x000000FF +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0__MAC_PKT_END_CNT___S 0 +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT0___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1 (0x00A91680) +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1__MACTX_SYNTH_ON_CNT___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1__MACTX_SYNTH_OFF_CNT___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1__MACTX_PHY_ON_CNT___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1__MACTX_PHY_OFF_CNT___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1__MACTX_SYNTH_ON_CNT___M 0xFF000000 +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1__MACTX_SYNTH_ON_CNT___S 24 +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1__MACTX_SYNTH_OFF_CNT___M 0x00FF0000 +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1__MACTX_SYNTH_OFF_CNT___S 16 +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1__MACTX_PHY_ON_CNT___M 0x0000FF00 +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1__MACTX_PHY_ON_CNT___S 8 +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1__MACTX_PHY_OFF_CNT___M 0x000000FF +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1__MACTX_PHY_OFF_CNT___S 0 +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_TX_MESSAGE_COUNT1___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_PHY_ERROR (0x00A91684) +#define WMAC0_TXPCU_R1_DEBUG_PHY_ERROR___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_PHY_ERROR___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_PHY_ERROR__VALUE___POR 0x0000 +#define WMAC0_TXPCU_R1_DEBUG_PHY_ERROR__VALUE___M 0x0000FFFF +#define WMAC0_TXPCU_R1_DEBUG_PHY_ERROR__VALUE___S 0 +#define WMAC0_TXPCU_R1_DEBUG_PHY_ERROR___M 0x0000FFFF +#define WMAC0_TXPCU_R1_DEBUG_PHY_ERROR___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS (0x00A91688) +#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__PHY_RDY_VIOLATED___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_RD_DELAY_VIOLATED___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_WR_CBF_RDY_VIOLATED___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_WR_PREAMBLES_RDY_VIOLATED___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_RD_RDY_VIOLATED___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_UNDERFLOW_1___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_UNDERFLOW_0___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_OVERFLOW_1___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_OVERFLOW_0___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__PHY_RDY_VIOLATED___M 0x00000100 +#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__PHY_RDY_VIOLATED___S 8 +#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_RD_DELAY_VIOLATED___M 0x00000080 +#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_RD_DELAY_VIOLATED___S 7 +#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_WR_CBF_RDY_VIOLATED___M 0x00000040 +#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_WR_CBF_RDY_VIOLATED___S 6 +#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_WR_PREAMBLES_RDY_VIOLATED___M 0x00000020 +#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_WR_PREAMBLES_RDY_VIOLATED___S 5 +#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_RD_RDY_VIOLATED___M 0x00000010 +#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_RD_RDY_VIOLATED___S 4 +#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_UNDERFLOW_1___M 0x00000008 +#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_UNDERFLOW_1___S 3 +#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_UNDERFLOW_0___M 0x00000004 +#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_UNDERFLOW_0___S 2 +#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_OVERFLOW_1___M 0x00000002 +#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_OVERFLOW_1___S 1 +#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_OVERFLOW_0___M 0x00000001 +#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS__SFM_OVERFLOW_0___S 0 +#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS___M 0x000001FF +#define WMAC0_TXPCU_R1_DEBUG_ERRORS_STATUS___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_TXDMA_EVENT_ENGINE (0x00A9168C) +#define WMAC0_TXPCU_R1_DEBUG_TXDMA_EVENT_ENGINE___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R1_DEBUG_TXDMA_EVENT_ENGINE___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_TXDMA_EVENT_ENGINE__MODULE_ID___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_TXDMA_EVENT_ENGINE__MODULE_ID___M 0x0000003F +#define WMAC0_TXPCU_R1_DEBUG_TXDMA_EVENT_ENGINE__MODULE_ID___S 0 +#define WMAC0_TXPCU_R1_DEBUG_TXDMA_EVENT_ENGINE___M 0x0000003F +#define WMAC0_TXPCU_R1_DEBUG_TXDMA_EVENT_ENGINE___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_UNDERRUN_MPDU_CNT (0x00A91690) +#define WMAC0_TXPCU_R1_DEBUG_UNDERRUN_MPDU_CNT___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_UNDERRUN_MPDU_CNT___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_UNDERRUN_MPDU_CNT__UNDERRUN_WITHIN_MPDU_CNT___POR 0x0000 +#define WMAC0_TXPCU_R1_DEBUG_UNDERRUN_MPDU_CNT__UNDERRUN_BTWN_MPDU_CNT___POR 0x0000 +#define WMAC0_TXPCU_R1_DEBUG_UNDERRUN_MPDU_CNT__UNDERRUN_WITHIN_MPDU_CNT___M 0xFFFF0000 +#define WMAC0_TXPCU_R1_DEBUG_UNDERRUN_MPDU_CNT__UNDERRUN_WITHIN_MPDU_CNT___S 16 +#define WMAC0_TXPCU_R1_DEBUG_UNDERRUN_MPDU_CNT__UNDERRUN_BTWN_MPDU_CNT___M 0x0000FFFF +#define WMAC0_TXPCU_R1_DEBUG_UNDERRUN_MPDU_CNT__UNDERRUN_BTWN_MPDU_CNT___S 0 +#define WMAC0_TXPCU_R1_DEBUG_UNDERRUN_MPDU_CNT___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_UNDERRUN_MPDU_CNT___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_MPDU_TX_FRAME_CNT (0x00A91694) +#define WMAC0_TXPCU_R1_DEBUG_MPDU_TX_FRAME_CNT___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_MPDU_TX_FRAME_CNT___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_MPDU_TX_FRAME_CNT__MPDU_TX_CNT___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_MPDU_TX_FRAME_CNT__MPDU_TX_CNT___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_MPDU_TX_FRAME_CNT__MPDU_TX_CNT___S 0 +#define WMAC0_TXPCU_R1_DEBUG_MPDU_TX_FRAME_CNT___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_MPDU_TX_FRAME_CNT___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_AMPDU_TX_FRAME_CNT (0x00A91698) +#define WMAC0_TXPCU_R1_DEBUG_AMPDU_TX_FRAME_CNT___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_AMPDU_TX_FRAME_CNT___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_AMPDU_TX_FRAME_CNT__AMPDU_TX_CNT___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_AMPDU_TX_FRAME_CNT__AMPDU_TX_CNT___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_AMPDU_TX_FRAME_CNT__AMPDU_TX_CNT___S 0 +#define WMAC0_TXPCU_R1_DEBUG_AMPDU_TX_FRAME_CNT___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_AMPDU_TX_FRAME_CNT___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_CORRUPT_DMA_DATA_CNT (0x00A9169C) +#define WMAC0_TXPCU_R1_DEBUG_CORRUPT_DMA_DATA_CNT___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_CORRUPT_DMA_DATA_CNT___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_CORRUPT_DMA_DATA_CNT__CORRUPT_DMA_DATA_CNT___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_CORRUPT_DMA_DATA_CNT__CORRUPT_DMA_DATA_CNT___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_CORRUPT_DMA_DATA_CNT__CORRUPT_DMA_DATA_CNT___S 0 +#define WMAC0_TXPCU_R1_DEBUG_CORRUPT_DMA_DATA_CNT___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_CORRUPT_DMA_DATA_CNT___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL (0x00A916A0) +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_MISC_GROUP___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_MACTX_ABORT_REQUEST___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_MACTX_ABORT_ACK___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_MACTX_PKT_END___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_CBF_GROUP___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_MACTX_COEX_PHY_CTRL___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_COEX_TX_STATUS___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_PDG_GROUP___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_RESPONSE_STATUS_GROUP___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_TX_FES_STATUS_GROUP___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_TX_MPDU_COUNT_TRANSFER_END___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_TXPCU_PREAMBLE_DONE___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_EXAMPLE_TLV_32___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_CBF_GROUP___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_RECEIVED_RESPONSE_GROUP___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_TX_FES_STATUS_ACK_OR_BA___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_RX_RESPONSE_REQUIRED_INFO___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_RX_FRAME_BITMAP_ACK___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_RECEIVED_TRIGGER_INFO___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_PHYRX_TX_START_TIMING___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_OFDMA_TRIGGER_DETAILS___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_MACTX_PHY_NAP___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_PHY_MISC_GROUP___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_PHY_PHYTX_PKT_END___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_PHY_PHYTX_REQUEST_CTRL_INFO___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_PHY_PHYTX_PPDU_HEADER_INFO_REQUEST___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_PDG_GROUP___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_CRYPTO_SETUP_GROUP___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_CRYPTO_TX_MPDU_START___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_CRYPTO_MISC_SETUP___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_MISC_GROUP___M 0x20000000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_MISC_GROUP___S 29 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_MACTX_ABORT_REQUEST___M 0x10000000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_MACTX_ABORT_REQUEST___S 28 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_MACTX_ABORT_ACK___M 0x08000000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_MACTX_ABORT_ACK___S 27 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_MACTX_PKT_END___M 0x04000000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_MACTX_PKT_END___S 26 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_CBF_GROUP___M 0x02000000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_CBF_GROUP___S 25 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_MACTX_COEX_PHY_CTRL___M 0x01000000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_PHY_MACTX_COEX_PHY_CTRL___S 24 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_COEX_TX_STATUS___M 0x00800000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_COEX_TX_STATUS___S 23 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_PDG_GROUP___M 0x00400000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_PDG_GROUP___S 22 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_RESPONSE_STATUS_GROUP___M 0x00200000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_RESPONSE_STATUS_GROUP___S 21 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_TX_FES_STATUS_GROUP___M 0x00100000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_TX_FES_STATUS_GROUP___S 20 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_TX_MPDU_COUNT_TRANSFER_END___M 0x00080000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_TX_MPDU_COUNT_TRANSFER_END___S 19 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_TXPCU_PREAMBLE_DONE___M 0x00040000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_TXPCU_PREAMBLE_DONE___S 18 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_EXAMPLE_TLV_32___M 0x00020000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVO_CRYPTO_EXAMPLE_TLV_32___S 17 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_CBF_GROUP___M 0x00010000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_CBF_GROUP___S 16 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_RECEIVED_RESPONSE_GROUP___M 0x00008000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_RECEIVED_RESPONSE_GROUP___S 15 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_TX_FES_STATUS_ACK_OR_BA___M 0x00004000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_TX_FES_STATUS_ACK_OR_BA___S 14 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_RX_RESPONSE_REQUIRED_INFO___M 0x00002000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_RX_RESPONSE_REQUIRED_INFO___S 13 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_RX_FRAME_BITMAP_ACK___M 0x00001000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_RX_FRAME_BITMAP_ACK___S 12 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_RECEIVED_TRIGGER_INFO___M 0x00000800 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_RECEIVED_TRIGGER_INFO___S 11 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_PHYRX_TX_START_TIMING___M 0x00000400 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_PHYRX_TX_START_TIMING___S 10 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_OFDMA_TRIGGER_DETAILS___M 0x00000200 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_OFDMA_TRIGGER_DETAILS___S 9 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_MACTX_PHY_NAP___M 0x00000100 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_RXPCU_MACTX_PHY_NAP___S 8 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_PHY_MISC_GROUP___M 0x00000080 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_PHY_MISC_GROUP___S 7 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_PHY_PHYTX_PKT_END___M 0x00000040 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_PHY_PHYTX_PKT_END___S 6 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_PHY_PHYTX_REQUEST_CTRL_INFO___M 0x00000020 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_PHY_PHYTX_REQUEST_CTRL_INFO___S 5 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_PHY_PHYTX_PPDU_HEADER_INFO_REQUEST___M 0x00000010 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_PHY_PHYTX_PPDU_HEADER_INFO_REQUEST___S 4 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_PDG_GROUP___M 0x00000008 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_PDG_GROUP___S 3 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_CRYPTO_SETUP_GROUP___M 0x00000004 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_CRYPTO_SETUP_GROUP___S 2 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_CRYPTO_TX_MPDU_START___M 0x00000002 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_CRYPTO_TX_MPDU_START___S 1 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_CRYPTO_MISC_SETUP___M 0x00000001 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL__TLVI_CRYPTO_MISC_SETUP___S 0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL___M 0x3FFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_TLV_BITMAP_FILTER_MODE_CTRL___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS (0x00A916A4) +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS___POR 0x007C0000 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__MOST_RECENT_ERR_OR_INT_EVENT___POR 0x1F +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__GLOBAL_UNDERRUN_FLAG___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__CBF_READ_REQ_ACK_INTR___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_OFF_ACK_NOT_RCVD_INTR___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_ON_ACK_NOT_RCVD_INTR___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_ABORT_ACK_NOT_RCVD_INTR___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_SYNTH_OFF_ACK_NOT_RCVD_INTR___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_SYNTH_ON_ACK_NOT_RCVD_INTR___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_NAP_ACK_NOT_RCVD_INTR___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_NAP_DONE_NOT_RCVD_INTR___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PDG_TLVIN_INCOMPLETE_ERR___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__CRYPTO_TLVIN_INCOMPLETE_ERR___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__COEX_TLVIN_INCOMPLETE_ERR___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHY_TLVIN_16_INCOMPLETE_ERR___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__RXPCU_TLVIN_42_INCOMPLETE_ERR___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__RXPCU_TLVIN_32_INCOMPLETE_ERR___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__WDOG_TIMEOUT_INTR___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__RECD_GT_MPDU_LEN_INTR___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__RECD_LT_MPDU_LEN_INTR___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__MOST_RECENT_ERR_OR_INT_EVENT___M 0x007C0000 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__MOST_RECENT_ERR_OR_INT_EVENT___S 18 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__GLOBAL_UNDERRUN_FLAG___M 0x00020000 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__GLOBAL_UNDERRUN_FLAG___S 17 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__CBF_READ_REQ_ACK_INTR___M 0x00010000 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__CBF_READ_REQ_ACK_INTR___S 16 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_OFF_ACK_NOT_RCVD_INTR___M 0x00008000 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_OFF_ACK_NOT_RCVD_INTR___S 15 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_ON_ACK_NOT_RCVD_INTR___M 0x00004000 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_ON_ACK_NOT_RCVD_INTR___S 14 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_ABORT_ACK_NOT_RCVD_INTR___M 0x00002000 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_ABORT_ACK_NOT_RCVD_INTR___S 13 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_SYNTH_OFF_ACK_NOT_RCVD_INTR___M 0x00001000 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_SYNTH_OFF_ACK_NOT_RCVD_INTR___S 12 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_SYNTH_ON_ACK_NOT_RCVD_INTR___M 0x00000800 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_SYNTH_ON_ACK_NOT_RCVD_INTR___S 11 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_NAP_ACK_NOT_RCVD_INTR___M 0x00000400 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_NAP_ACK_NOT_RCVD_INTR___S 10 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_NAP_DONE_NOT_RCVD_INTR___M 0x00000200 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHYTX_NAP_DONE_NOT_RCVD_INTR___S 9 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PDG_TLVIN_INCOMPLETE_ERR___M 0x00000100 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PDG_TLVIN_INCOMPLETE_ERR___S 8 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__CRYPTO_TLVIN_INCOMPLETE_ERR___M 0x00000080 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__CRYPTO_TLVIN_INCOMPLETE_ERR___S 7 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__COEX_TLVIN_INCOMPLETE_ERR___M 0x00000040 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__COEX_TLVIN_INCOMPLETE_ERR___S 6 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHY_TLVIN_16_INCOMPLETE_ERR___M 0x00000020 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__PHY_TLVIN_16_INCOMPLETE_ERR___S 5 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__RXPCU_TLVIN_42_INCOMPLETE_ERR___M 0x00000010 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__RXPCU_TLVIN_42_INCOMPLETE_ERR___S 4 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__RXPCU_TLVIN_32_INCOMPLETE_ERR___M 0x00000008 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__RXPCU_TLVIN_32_INCOMPLETE_ERR___S 3 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__WDOG_TIMEOUT_INTR___M 0x00000004 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__WDOG_TIMEOUT_INTR___S 2 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__RECD_GT_MPDU_LEN_INTR___M 0x00000002 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__RECD_GT_MPDU_LEN_INTR___S 1 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__RECD_LT_MPDU_LEN_INTR___M 0x00000001 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS__RECD_LT_MPDU_LEN_INTR___S 0 +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS___M 0x007FFFFF +#define WMAC0_TXPCU_R1_DEBUG_INT_OR_ERR_STATUS___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK (0x00A916A8) +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__GLOBAL_UNDERRUN_FLAG_MASK___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__CBF_READ_REQ_ACK_INTR_MASK___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_OFF_ACK_NOT_RCVD_INTR_MASK___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_ON_ACK_NOT_RCVD_INTR_MASK___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_ABORT_ACK_NOT_RCVD_INTR_MASK___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_SYNTH_OFF_ACK_NOT_RCVD_INTR_MASK___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_SYNTH_ON_ACK_NOT_RCVD_INTR_MASK___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_NAP_ACK_NOT_RCVD_INTR_MASK___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_NAP_DONE_NOT_RCVD_INTR_MASK___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PDG_TLVIN_INCOMPLETE_ERR_MASK___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__CRYPTO_TLVIN_INCOMPLETE_ERR_MASK___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__COEX_TLVIN_INCOMPLETE_ERR_MASK___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHY_TLVIN_16_INCOMPLETE_ERR_MASK___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__RXPCU_TLVIN_42_INCOMPLETE_ERR_MASK___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__RXPCU_TLVIN_32_INCOMPLETE_ERR_MASK___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__GLOBAL_UNDERRUN_FLAG_MASK___M 0x00004000 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__GLOBAL_UNDERRUN_FLAG_MASK___S 14 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__CBF_READ_REQ_ACK_INTR_MASK___M 0x00002000 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__CBF_READ_REQ_ACK_INTR_MASK___S 13 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_OFF_ACK_NOT_RCVD_INTR_MASK___M 0x00001000 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_OFF_ACK_NOT_RCVD_INTR_MASK___S 12 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_ON_ACK_NOT_RCVD_INTR_MASK___M 0x00000800 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_ON_ACK_NOT_RCVD_INTR_MASK___S 11 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_ABORT_ACK_NOT_RCVD_INTR_MASK___M 0x00000400 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_ABORT_ACK_NOT_RCVD_INTR_MASK___S 10 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_SYNTH_OFF_ACK_NOT_RCVD_INTR_MASK___M 0x00000200 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_SYNTH_OFF_ACK_NOT_RCVD_INTR_MASK___S 9 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_SYNTH_ON_ACK_NOT_RCVD_INTR_MASK___M 0x00000100 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_SYNTH_ON_ACK_NOT_RCVD_INTR_MASK___S 8 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_NAP_ACK_NOT_RCVD_INTR_MASK___M 0x00000080 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_NAP_ACK_NOT_RCVD_INTR_MASK___S 7 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_NAP_DONE_NOT_RCVD_INTR_MASK___M 0x00000040 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHYTX_NAP_DONE_NOT_RCVD_INTR_MASK___S 6 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PDG_TLVIN_INCOMPLETE_ERR_MASK___M 0x00000020 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PDG_TLVIN_INCOMPLETE_ERR_MASK___S 5 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__CRYPTO_TLVIN_INCOMPLETE_ERR_MASK___M 0x00000010 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__CRYPTO_TLVIN_INCOMPLETE_ERR_MASK___S 4 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__COEX_TLVIN_INCOMPLETE_ERR_MASK___M 0x00000008 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__COEX_TLVIN_INCOMPLETE_ERR_MASK___S 3 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHY_TLVIN_16_INCOMPLETE_ERR_MASK___M 0x00000004 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__PHY_TLVIN_16_INCOMPLETE_ERR_MASK___S 2 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__RXPCU_TLVIN_42_INCOMPLETE_ERR_MASK___M 0x00000002 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__RXPCU_TLVIN_42_INCOMPLETE_ERR_MASK___S 1 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__RXPCU_TLVIN_32_INCOMPLETE_ERR_MASK___M 0x00000001 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK__RXPCU_TLVIN_32_INCOMPLETE_ERR_MASK___S 0 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK___M 0x00007FFF +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS_MASK___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS (0x00A916AC) +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS___POR 0x0000001F +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS__ERR_OR_INT_DATA___POR 0x000000 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS__MAIN_SM_STATE_TX___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS__MOST_RECENT_ERR_OR_INT_EVENT___POR 0x1F +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS__ERR_OR_INT_DATA___M 0xFFFFF800 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS__ERR_OR_INT_DATA___S 11 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS__MAIN_SM_STATE_TX___M 0x000007E0 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS__MAIN_SM_STATE_TX___S 5 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS__MOST_RECENT_ERR_OR_INT_EVENT___M 0x0000001F +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS__MOST_RECENT_ERR_OR_INT_EVENT___S 0 +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_LAST_INT_OR_ERR_STATUS___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL (0x00A916B0) +#define WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL___POR 0x00100040 +#define WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__PSDU_LENGTH_SECOND_USER_SELECT___POR 0x01 +#define WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__PSDU_LENGTH_FIRST_USER_SELECT___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__ENABLE_SECOND_COUNTER___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__ENABLE_FIRST_COUNTER___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__SECOND_COUNTER_USER___POR 0x01 +#define WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__FIRST_COUNTER_USER___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__PSDU_LENGTH_SECOND_USER_SELECT___M 0x03F00000 +#define WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__PSDU_LENGTH_SECOND_USER_SELECT___S 20 +#define WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__PSDU_LENGTH_FIRST_USER_SELECT___M 0x000FC000 +#define WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__PSDU_LENGTH_FIRST_USER_SELECT___S 14 +#define WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__ENABLE_SECOND_COUNTER___M 0x00002000 +#define WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__ENABLE_SECOND_COUNTER___S 13 +#define WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__ENABLE_FIRST_COUNTER___M 0x00001000 +#define WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__ENABLE_FIRST_COUNTER___S 12 +#define WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__SECOND_COUNTER_USER___M 0x00000FC0 +#define WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__SECOND_COUNTER_USER___S 6 +#define WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__FIRST_COUNTER_USER___M 0x0000003F +#define WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL__FIRST_COUNTER_USER___S 0 +#define WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL___M 0x03FFFFFF +#define WMAC0_TXPCU_R1_DEBUG_MAC_PHY_IF_COUNTER_CTRL___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS (0x00A916B4) +#define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS__RCVD_REQ_GT_DATA_RESP___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS__USER_ID___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS__RCVD_WORD_COUNT___POR 0x000000 +#define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS__RCVD_REQ_GT_DATA_RESP___M 0xF8000000 +#define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS__RCVD_REQ_GT_DATA_RESP___S 27 +#define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS__USER_ID___M 0x07E00000 +#define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS__USER_ID___S 21 +#define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS__RCVD_WORD_COUNT___M 0x001FFFFF +#define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS__RCVD_WORD_COUNT___S 0 +#define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_1_STATUS___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS (0x00A916B8) +#define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS__DATA_RESP_GT_RCVD_REQ___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS__USER_ID___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS__SENT_WORD_COUNT___POR 0x000000 +#define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS__DATA_RESP_GT_RCVD_REQ___M 0xF8000000 +#define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS__DATA_RESP_GT_RCVD_REQ___S 27 +#define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS__USER_ID___M 0x07E00000 +#define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS__USER_ID___S 21 +#define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS__SENT_WORD_COUNT___M 0x001FFFFF +#define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS__SENT_WORD_COUNT___S 0 +#define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_1_STATUS___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS (0x00A916BC) +#define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS___POR 0x00200000 +#define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS__RCVD_REQ_GT_DATA_RESP___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS__USER_ID___POR 0x01 +#define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS__RCVD_WORD_COUNT___POR 0x000000 +#define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS__RCVD_REQ_GT_DATA_RESP___M 0xF8000000 +#define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS__RCVD_REQ_GT_DATA_RESP___S 27 +#define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS__USER_ID___M 0x07E00000 +#define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS__USER_ID___S 21 +#define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS__RCVD_WORD_COUNT___M 0x001FFFFF +#define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS__RCVD_WORD_COUNT___S 0 +#define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_PHYTX_DATA_REQ_COUNTER_2_STATUS___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS (0x00A916C0) +#define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS___POR 0x00200000 +#define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS__DATA_RESP_GT_RCVD_REQ___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS__USER_ID___POR 0x01 +#define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS__SENT_WORD_COUNT___POR 0x000000 +#define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS__DATA_RESP_GT_RCVD_REQ___M 0xF8000000 +#define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS__DATA_RESP_GT_RCVD_REQ___S 27 +#define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS__USER_ID___M 0x07E00000 +#define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS__USER_ID___S 21 +#define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS__SENT_WORD_COUNT___M 0x001FFFFF +#define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS__SENT_WORD_COUNT___S 0 +#define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_MACTX_DATA_RESP_COUNTER_2_STATUS___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_FIRST_USER_PSDU_LENGTH_STATUS (0x00A916C4) +#define WMAC0_TXPCU_R1_DEBUG_FIRST_USER_PSDU_LENGTH_STATUS___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_FIRST_USER_PSDU_LENGTH_STATUS___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_FIRST_USER_PSDU_LENGTH_STATUS__USER_ID___POR 0x00 +#define WMAC0_TXPCU_R1_DEBUG_FIRST_USER_PSDU_LENGTH_STATUS__PSDU_LENGTH___POR 0x000000 +#define WMAC0_TXPCU_R1_DEBUG_FIRST_USER_PSDU_LENGTH_STATUS__USER_ID___M 0x1F800000 +#define WMAC0_TXPCU_R1_DEBUG_FIRST_USER_PSDU_LENGTH_STATUS__USER_ID___S 23 +#define WMAC0_TXPCU_R1_DEBUG_FIRST_USER_PSDU_LENGTH_STATUS__PSDU_LENGTH___M 0x007FFFFF +#define WMAC0_TXPCU_R1_DEBUG_FIRST_USER_PSDU_LENGTH_STATUS__PSDU_LENGTH___S 0 +#define WMAC0_TXPCU_R1_DEBUG_FIRST_USER_PSDU_LENGTH_STATUS___M 0x1FFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_FIRST_USER_PSDU_LENGTH_STATUS___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_SECOND_USER_PSDU_LENGTH_STATUS (0x00A916C8) +#define WMAC0_TXPCU_R1_DEBUG_SECOND_USER_PSDU_LENGTH_STATUS___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_SECOND_USER_PSDU_LENGTH_STATUS___POR 0x00800000 +#define WMAC0_TXPCU_R1_DEBUG_SECOND_USER_PSDU_LENGTH_STATUS__USER_ID___POR 0x01 +#define WMAC0_TXPCU_R1_DEBUG_SECOND_USER_PSDU_LENGTH_STATUS__PSDU_LENGTH___POR 0x000000 +#define WMAC0_TXPCU_R1_DEBUG_SECOND_USER_PSDU_LENGTH_STATUS__USER_ID___M 0x1F800000 +#define WMAC0_TXPCU_R1_DEBUG_SECOND_USER_PSDU_LENGTH_STATUS__USER_ID___S 23 +#define WMAC0_TXPCU_R1_DEBUG_SECOND_USER_PSDU_LENGTH_STATUS__PSDU_LENGTH___M 0x007FFFFF +#define WMAC0_TXPCU_R1_DEBUG_SECOND_USER_PSDU_LENGTH_STATUS__PSDU_LENGTH___S 0 +#define WMAC0_TXPCU_R1_DEBUG_SECOND_USER_PSDU_LENGTH_STATUS___M 0x1FFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_SECOND_USER_PSDU_LENGTH_STATUS___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_0 (0x00A916D8) +#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_0___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_0___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_0__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_0__VALUE___S 0 +#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_0___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_0___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_1 (0x00A916DC) +#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_1___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_1___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_1__VALUE___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_1__VALUE___S 0 +#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_1___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_BITMAP_1___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL (0x00A916E0) +#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL___RWC QCSR_REG_RW +#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL__INTR_HIJACK_PRESET_BITMAP___POR 0x0000000 +#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL__INTR_HIJACK_PIN_SELECT___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL__INTR_HIJACK_ENABLE___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL__INTR_HIJACK_PRESET_BITMAP___M 0xFFFFFFF0 +#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL__INTR_HIJACK_PRESET_BITMAP___S 4 +#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL__INTR_HIJACK_PIN_SELECT___M 0x0000000E +#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL__INTR_HIJACK_PIN_SELECT___S 1 +#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL__INTR_HIJACK_ENABLE___M 0x00000001 +#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL__INTR_HIJACK_ENABLE___S 0 +#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_INTR_HIJACK_CTRL___S 0 + +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER (0x00A916E4) +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER___RWC QCSR_REG_RO +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER___POR 0x00000000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PHYTX_PKT_END_RCVD___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__EXPECTED_RESPONSE_SENT___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RCPCU_TX_SETUP_CLEAR_SENT___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RXPCU_SETUP_COMPLETE_RCVD___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RXPCU_SETUP_RCVD___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__TX_FES_STATUS_END___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PHYTX_ABORT_ACK_RCVD___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_ABORT_REQUEST_SENT___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_ABORT_ACK_SENT___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PHYTX_ABORT_REQUEST_RCVD___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_SERVICE_COUNT_REACHED___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_PHY_DESC_SENT___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_PHY_DESC_RCVD___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_PRE_PHY_DESC_SENT___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RECEIVE_TRIGGER_INFO___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__OFDMA_TRIGGER_DETAILS___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RX_RESPONSE_REQUIRED_INFO___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RECEIVED_RESPONSE_INFO___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PDG_TRIG_RESPONSE___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PDG_RESPONSE___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PDG_TX_REQ___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PCU_PPDU_SETUP_DONE___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PCU_PPDU_SETUP_END___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PCU_PPDU_SETUP_START___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PCU_PPDU_SETUP_INIT___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__COEX_TX_STOP_CTRL___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__TX_FES_SETUP_COMPLETE___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__TX_CBF_INFO___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_PKT_END___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PRE_START_TX_PULSE___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__START_TX_PULSE___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__TX_FES_SETUP___POR 0x0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PHYTX_PKT_END_RCVD___M 0x80000000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PHYTX_PKT_END_RCVD___S 31 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__EXPECTED_RESPONSE_SENT___M 0x40000000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__EXPECTED_RESPONSE_SENT___S 30 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RCPCU_TX_SETUP_CLEAR_SENT___M 0x20000000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RCPCU_TX_SETUP_CLEAR_SENT___S 29 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RXPCU_SETUP_COMPLETE_RCVD___M 0x10000000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RXPCU_SETUP_COMPLETE_RCVD___S 28 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RXPCU_SETUP_RCVD___M 0x08000000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RXPCU_SETUP_RCVD___S 27 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__TX_FES_STATUS_END___M 0x04000000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__TX_FES_STATUS_END___S 26 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PHYTX_ABORT_ACK_RCVD___M 0x02000000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PHYTX_ABORT_ACK_RCVD___S 25 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_ABORT_REQUEST_SENT___M 0x01000000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_ABORT_REQUEST_SENT___S 24 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_ABORT_ACK_SENT___M 0x00800000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_ABORT_ACK_SENT___S 23 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PHYTX_ABORT_REQUEST_RCVD___M 0x00400000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PHYTX_ABORT_REQUEST_RCVD___S 22 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_SERVICE_COUNT_REACHED___M 0x00200000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_SERVICE_COUNT_REACHED___S 21 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_PHY_DESC_SENT___M 0x00100000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_PHY_DESC_SENT___S 20 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_PHY_DESC_RCVD___M 0x00080000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_PHY_DESC_RCVD___S 19 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_PRE_PHY_DESC_SENT___M 0x00040000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_PRE_PHY_DESC_SENT___S 18 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RECEIVE_TRIGGER_INFO___M 0x00020000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RECEIVE_TRIGGER_INFO___S 17 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__OFDMA_TRIGGER_DETAILS___M 0x00010000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__OFDMA_TRIGGER_DETAILS___S 16 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RX_RESPONSE_REQUIRED_INFO___M 0x00008000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RX_RESPONSE_REQUIRED_INFO___S 15 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RECEIVED_RESPONSE_INFO___M 0x00004000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__RECEIVED_RESPONSE_INFO___S 14 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PDG_TRIG_RESPONSE___M 0x00002000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PDG_TRIG_RESPONSE___S 13 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PDG_RESPONSE___M 0x00001000 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PDG_RESPONSE___S 12 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PDG_TX_REQ___M 0x00000800 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PDG_TX_REQ___S 11 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PCU_PPDU_SETUP_DONE___M 0x00000400 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PCU_PPDU_SETUP_DONE___S 10 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PCU_PPDU_SETUP_END___M 0x00000200 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PCU_PPDU_SETUP_END___S 9 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PCU_PPDU_SETUP_START___M 0x00000100 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PCU_PPDU_SETUP_START___S 8 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PCU_PPDU_SETUP_INIT___M 0x00000080 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PCU_PPDU_SETUP_INIT___S 7 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__COEX_TX_STOP_CTRL___M 0x00000040 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__COEX_TX_STOP_CTRL___S 6 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__TX_FES_SETUP_COMPLETE___M 0x00000020 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__TX_FES_SETUP_COMPLETE___S 5 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__TX_CBF_INFO___M 0x00000010 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__TX_CBF_INFO___S 4 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_PKT_END___M 0x00000008 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__MACTX_PKT_END___S 3 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PRE_START_TX_PULSE___M 0x00000004 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__PRE_START_TX_PULSE___S 2 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__START_TX_PULSE___M 0x00000002 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__START_TX_PULSE___S 1 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__TX_FES_SETUP___M 0x00000001 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER__TX_FES_SETUP___S 0 +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER___M 0xFFFFFFFF +#define WMAC0_TXPCU_R1_DEBUG_TLV_TRACKER___S 0 + +#define WMAC0_AMPI_R0_TX_SIFS (0x00A92000) +#define WMAC0_AMPI_R0_TX_SIFS___RWC QCSR_REG_RW +#define WMAC0_AMPI_R0_TX_SIFS___POR 0x000004F4 +#define WMAC0_AMPI_R0_TX_SIFS__TX_SIFS_VALUE___POR 0x04F4 +#define WMAC0_AMPI_R0_TX_SIFS__TX_SIFS_VALUE___M 0x0000FFFF +#define WMAC0_AMPI_R0_TX_SIFS__TX_SIFS_VALUE___S 0 +#define WMAC0_AMPI_R0_TX_SIFS___M 0x0000FFFF +#define WMAC0_AMPI_R0_TX_SIFS___S 0 + +#define WMAC0_AMPI_R0_CLKGATE_DISABLE (0x00A92004) +#define WMAC0_AMPI_R0_CLKGATE_DISABLE___RWC QCSR_REG_RW +#define WMAC0_AMPI_R0_CLKGATE_DISABLE___POR 0x00000000 +#define WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DSIABLE_LOOPBACK_MAC___POR 0x0 +#define WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_LOOPBACK_PHY___POR 0x0 +#define WMAC0_AMPI_R0_CLKGATE_DISABLE__APB_CLK_EXTEND___POR 0x0 +#define WMAC0_AMPI_R0_CLKGATE_DISABLE__CLK_ENS_EXTEND___POR 0x0 +#define WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_DEBUG___POR 0x0 +#define WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_PHY_COUNTER_CLOCK_LOGIC___POR 0x0 +#define WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_PHY_COUNTER_LOGIC___POR 0x0 +#define WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_PHY_RX_CLOCK___POR 0x0 +#define WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_PHY_TX_CLOCK___POR 0x0 +#define WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DSIABLE_LOOPBACK_MAC___M 0x00000100 +#define WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DSIABLE_LOOPBACK_MAC___S 8 +#define WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_LOOPBACK_PHY___M 0x00000080 +#define WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_LOOPBACK_PHY___S 7 +#define WMAC0_AMPI_R0_CLKGATE_DISABLE__APB_CLK_EXTEND___M 0x00000040 +#define WMAC0_AMPI_R0_CLKGATE_DISABLE__APB_CLK_EXTEND___S 6 +#define WMAC0_AMPI_R0_CLKGATE_DISABLE__CLK_ENS_EXTEND___M 0x00000020 +#define WMAC0_AMPI_R0_CLKGATE_DISABLE__CLK_ENS_EXTEND___S 5 +#define WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_DEBUG___M 0x00000010 +#define WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_DEBUG___S 4 +#define WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_PHY_COUNTER_CLOCK_LOGIC___M 0x00000008 +#define WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_PHY_COUNTER_CLOCK_LOGIC___S 3 +#define WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_PHY_COUNTER_LOGIC___M 0x00000004 +#define WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_PHY_COUNTER_LOGIC___S 2 +#define WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_PHY_RX_CLOCK___M 0x00000002 +#define WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_PHY_RX_CLOCK___S 1 +#define WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_PHY_TX_CLOCK___M 0x00000001 +#define WMAC0_AMPI_R0_CLKGATE_DISABLE__CLOCK_GATE_DISABLE_PHY_TX_CLOCK___S 0 +#define WMAC0_AMPI_R0_CLKGATE_DISABLE___M 0x000001FF +#define WMAC0_AMPI_R0_CLKGATE_DISABLE___S 0 + +#define WMAC0_AMPI_R0_FEATURE_DISABLE (0x00A92008) +#define WMAC0_AMPI_R0_FEATURE_DISABLE___RWC QCSR_REG_RW +#define WMAC0_AMPI_R0_FEATURE_DISABLE___POR 0x00000060 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__ENABLE_ECO___POR 0x00 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__FINE_SIFS_NEGATE___POR 0x0 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__TX_FIFO_SYNC_RST_MAC_CLK___POR 0x0 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__RX_FIFO_SYNC_RST_MAC_CLK___POR 0x0 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__TX_FIFO_SYNC_RST_PHY_CLK___POR 0x0 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__RX_FIFO_SYNC_RST_PHY_CLK___POR 0x0 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__DISABLE_TX_TIMESTAMP_INSERTION___POR 0x1 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__WAIT_FINE_SIFS_DISABLE___POR 0x1 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__DISABLE_IDLE_FILTER___POR 0x0 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__DISABLE_RX_CLEAR_FILTER___POR 0x0 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__DISABLE_TIMESTAMP_INSERTION___POR 0x0 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__DISABLE_STALE_TIMESTAMP_DETECTION___POR 0x0 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__ENABLE_ECO___M 0x0003F000 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__ENABLE_ECO___S 12 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__FINE_SIFS_NEGATE___M 0x00000800 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__FINE_SIFS_NEGATE___S 11 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__TX_FIFO_SYNC_RST_MAC_CLK___M 0x00000400 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__TX_FIFO_SYNC_RST_MAC_CLK___S 10 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__RX_FIFO_SYNC_RST_MAC_CLK___M 0x00000200 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__RX_FIFO_SYNC_RST_MAC_CLK___S 9 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__TX_FIFO_SYNC_RST_PHY_CLK___M 0x00000100 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__TX_FIFO_SYNC_RST_PHY_CLK___S 8 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__RX_FIFO_SYNC_RST_PHY_CLK___M 0x00000080 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__RX_FIFO_SYNC_RST_PHY_CLK___S 7 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__DISABLE_TX_TIMESTAMP_INSERTION___M 0x00000040 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__DISABLE_TX_TIMESTAMP_INSERTION___S 6 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__WAIT_FINE_SIFS_DISABLE___M 0x00000020 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__WAIT_FINE_SIFS_DISABLE___S 5 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__DISABLE_IDLE_FILTER___M 0x00000008 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__DISABLE_IDLE_FILTER___S 3 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__DISABLE_RX_CLEAR_FILTER___M 0x00000004 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__DISABLE_RX_CLEAR_FILTER___S 2 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__DISABLE_TIMESTAMP_INSERTION___M 0x00000002 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__DISABLE_TIMESTAMP_INSERTION___S 1 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__DISABLE_STALE_TIMESTAMP_DETECTION___M 0x00000001 +#define WMAC0_AMPI_R0_FEATURE_DISABLE__DISABLE_STALE_TIMESTAMP_DETECTION___S 0 +#define WMAC0_AMPI_R0_FEATURE_DISABLE___M 0x0003FFEF +#define WMAC0_AMPI_R0_FEATURE_DISABLE___S 0 + +#define WMAC0_AMPI_R0_CCA_ED_OVERRIDE_VALUE (0x00A9200C) +#define WMAC0_AMPI_R0_CCA_ED_OVERRIDE_VALUE___RWC QCSR_REG_RW +#define WMAC0_AMPI_R0_CCA_ED_OVERRIDE_VALUE___POR 0x00000000 +#define WMAC0_AMPI_R0_CCA_ED_OVERRIDE_VALUE__VALUE___POR 0x000000 +#define WMAC0_AMPI_R0_CCA_ED_OVERRIDE_VALUE__VALUE___M 0x00FFFFFF +#define WMAC0_AMPI_R0_CCA_ED_OVERRIDE_VALUE__VALUE___S 0 +#define WMAC0_AMPI_R0_CCA_ED_OVERRIDE_VALUE___M 0x00FFFFFF +#define WMAC0_AMPI_R0_CCA_ED_OVERRIDE_VALUE___S 0 + +#define WMAC0_AMPI_R0_CCA_GI_OVERRIDE_VALUE (0x00A92010) +#define WMAC0_AMPI_R0_CCA_GI_OVERRIDE_VALUE___RWC QCSR_REG_RW +#define WMAC0_AMPI_R0_CCA_GI_OVERRIDE_VALUE___POR 0x00000000 +#define WMAC0_AMPI_R0_CCA_GI_OVERRIDE_VALUE__VALUE___POR 0x000000 +#define WMAC0_AMPI_R0_CCA_GI_OVERRIDE_VALUE__VALUE___M 0x00FFFFFF +#define WMAC0_AMPI_R0_CCA_GI_OVERRIDE_VALUE__VALUE___S 0 +#define WMAC0_AMPI_R0_CCA_GI_OVERRIDE_VALUE___M 0x00FFFFFF +#define WMAC0_AMPI_R0_CCA_GI_OVERRIDE_VALUE___S 0 + +#define WMAC0_AMPI_R0_CCA_FRAME_DETECT_OVERRIDE_VALUE (0x00A92014) +#define WMAC0_AMPI_R0_CCA_FRAME_DETECT_OVERRIDE_VALUE___RWC QCSR_REG_RW +#define WMAC0_AMPI_R0_CCA_FRAME_DETECT_OVERRIDE_VALUE___POR 0x00000000 +#define WMAC0_AMPI_R0_CCA_FRAME_DETECT_OVERRIDE_VALUE__TX_FRAME_VALUE___POR 0x0 +#define WMAC0_AMPI_R0_CCA_FRAME_DETECT_OVERRIDE_VALUE__RX_FRAME_VALUE___POR 0x0 +#define WMAC0_AMPI_R0_CCA_FRAME_DETECT_OVERRIDE_VALUE__PRE_RX_FRAME_VALUE___POR 0x0 +#define WMAC0_AMPI_R0_CCA_FRAME_DETECT_OVERRIDE_VALUE__TX_FRAME_VALUE___M 0x00000004 +#define WMAC0_AMPI_R0_CCA_FRAME_DETECT_OVERRIDE_VALUE__TX_FRAME_VALUE___S 2 +#define WMAC0_AMPI_R0_CCA_FRAME_DETECT_OVERRIDE_VALUE__RX_FRAME_VALUE___M 0x00000002 +#define WMAC0_AMPI_R0_CCA_FRAME_DETECT_OVERRIDE_VALUE__RX_FRAME_VALUE___S 1 +#define WMAC0_AMPI_R0_CCA_FRAME_DETECT_OVERRIDE_VALUE__PRE_RX_FRAME_VALUE___M 0x00000001 +#define WMAC0_AMPI_R0_CCA_FRAME_DETECT_OVERRIDE_VALUE__PRE_RX_FRAME_VALUE___S 0 +#define WMAC0_AMPI_R0_CCA_FRAME_DETECT_OVERRIDE_VALUE___M 0x00000007 +#define WMAC0_AMPI_R0_CCA_FRAME_DETECT_OVERRIDE_VALUE___S 0 + +#define WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL (0x00A92018) +#define WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL___RWC QCSR_REG_RW +#define WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL___POR 0x00000000 +#define WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL__TX_FRAME_EN___POR 0x0 +#define WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL__RX_FRAME_EN___POR 0x0 +#define WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL__PRE_RX_FRAME_EN___POR 0x0 +#define WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL__CCA_GI_EN___POR 0x0 +#define WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL__CCA_ED_EN___POR 0x0 +#define WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL__TX_FRAME_EN___M 0x00000010 +#define WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL__TX_FRAME_EN___S 4 +#define WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL__RX_FRAME_EN___M 0x00000008 +#define WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL__RX_FRAME_EN___S 3 +#define WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL__PRE_RX_FRAME_EN___M 0x00000004 +#define WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL__PRE_RX_FRAME_EN___S 2 +#define WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL__CCA_GI_EN___M 0x00000002 +#define WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL__CCA_GI_EN___S 1 +#define WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL__CCA_ED_EN___M 0x00000001 +#define WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL__CCA_ED_EN___S 0 +#define WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL___M 0x0000001F +#define WMAC0_AMPI_R0_CCA_OVERRIDE_CTRL___S 0 + +#define WMAC0_AMPI_R0_LOOPBACK_CTRL (0x00A9201C) +#define WMAC0_AMPI_R0_LOOPBACK_CTRL___RWC QCSR_REG_RW +#define WMAC0_AMPI_R0_LOOPBACK_CTRL___POR 0x00020040 +#define WMAC0_AMPI_R0_LOOPBACK_CTRL__TX_DONE_INDICATOR___POR 0x0 +#define WMAC0_AMPI_R0_LOOPBACK_CTRL__BASE_TIMER_VALUE_FOR_QUARTER_US___POR 0x000 +#define WMAC0_AMPI_R0_LOOPBACK_CTRL__BACK_TO_BACK_REQUEST_COUNT___POR 0x040 +#define WMAC0_AMPI_R0_LOOPBACK_CTRL__IDLE_INTERVAL_COUNT___POR 0x020 +#define WMAC0_AMPI_R0_LOOPBACK_CTRL__LOOPBACK_ENA___POR 0x0 +#define WMAC0_AMPI_R0_LOOPBACK_CTRL__TX_DONE_INDICATOR___M 0x80000000 +#define WMAC0_AMPI_R0_LOOPBACK_CTRL__TX_DONE_INDICATOR___S 31 +#define WMAC0_AMPI_R0_LOOPBACK_CTRL__BASE_TIMER_VALUE_FOR_QUARTER_US___M 0x7FE00000 +#define WMAC0_AMPI_R0_LOOPBACK_CTRL__BASE_TIMER_VALUE_FOR_QUARTER_US___S 21 +#define WMAC0_AMPI_R0_LOOPBACK_CTRL__BACK_TO_BACK_REQUEST_COUNT___M 0x001FF800 +#define WMAC0_AMPI_R0_LOOPBACK_CTRL__BACK_TO_BACK_REQUEST_COUNT___S 11 +#define WMAC0_AMPI_R0_LOOPBACK_CTRL__IDLE_INTERVAL_COUNT___M 0x000007FE +#define WMAC0_AMPI_R0_LOOPBACK_CTRL__IDLE_INTERVAL_COUNT___S 1 +#define WMAC0_AMPI_R0_LOOPBACK_CTRL__LOOPBACK_ENA___M 0x00000001 +#define WMAC0_AMPI_R0_LOOPBACK_CTRL__LOOPBACK_ENA___S 0 +#define WMAC0_AMPI_R0_LOOPBACK_CTRL___M 0xFFFFFFFF +#define WMAC0_AMPI_R0_LOOPBACK_CTRL___S 0 + +#define WMAC0_AMPI_R0_AMPI_RFA_LISTEN_CONFIG (0x00A92020) +#define WMAC0_AMPI_R0_AMPI_RFA_LISTEN_CONFIG___RWC QCSR_REG_RW +#define WMAC0_AMPI_R0_AMPI_RFA_LISTEN_CONFIG___POR 0x00000000 +#define WMAC0_AMPI_R0_AMPI_RFA_LISTEN_CONFIG__FORCE_ON___POR 0x0 +#define WMAC0_AMPI_R0_AMPI_RFA_LISTEN_CONFIG__FORCE_OFF___POR 0x0 +#define WMAC0_AMPI_R0_AMPI_RFA_LISTEN_CONFIG__FORCE_ON___M 0x00000002 +#define WMAC0_AMPI_R0_AMPI_RFA_LISTEN_CONFIG__FORCE_ON___S 1 +#define WMAC0_AMPI_R0_AMPI_RFA_LISTEN_CONFIG__FORCE_OFF___M 0x00000001 +#define WMAC0_AMPI_R0_AMPI_RFA_LISTEN_CONFIG__FORCE_OFF___S 0 +#define WMAC0_AMPI_R0_AMPI_RFA_LISTEN_CONFIG___M 0x00000003 +#define WMAC0_AMPI_R0_AMPI_RFA_LISTEN_CONFIG___S 0 + +#define WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_n(n) (0x00A93000+0x4*(n)) +#define WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_n_nMIN 0 +#define WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_n_nMAX 1 +#define WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_n_ELEM 2 +#define WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_n___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_n___POR 0x00000000 +#define WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_n__VAL___POR 0x00000000 +#define WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_n__VAL___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_n__VAL___S 0 +#define WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_n___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_n___S 0 +#define WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_0 (0x00A93000) +#define WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_0___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_0__VAL___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_0__VAL___S 0 +#define WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_1 (0x00A93004) +#define WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_1___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_1__VAL___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_CURRENT_TIMESTAMP_IX_1__VAL___S 0 + +#define WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_n(n) (0x00A93008+0x4*(n)) +#define WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_n_nMIN 0 +#define WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_n_nMAX 1 +#define WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_n_ELEM 2 +#define WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_n___RWC QCSR_REG_RO +#define WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_n___POR 0x00000000 +#define WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_n__VAL___POR 0x00000000 +#define WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_n__VAL___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_n__VAL___S 0 +#define WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_n___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_n___S 0 +#define WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_0 (0x00A93008) +#define WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_0___RWC QCSR_REG_RO +#define WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_0__VAL___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_0__VAL___S 0 +#define WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_1 (0x00A9300C) +#define WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_1___RWC QCSR_REG_RO +#define WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_1__VAL___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_PHY_TIMESTAMP1_IX_1__VAL___S 0 + +#define WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_n(n) (0x00A93010+0x4*(n)) +#define WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_n_nMIN 0 +#define WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_n_nMAX 1 +#define WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_n_ELEM 2 +#define WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_n___RWC QCSR_REG_RO +#define WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_n___POR 0x00000000 +#define WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_n__VAL___POR 0x00000000 +#define WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_n__VAL___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_n__VAL___S 0 +#define WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_n___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_n___S 0 +#define WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_0 (0x00A93010) +#define WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_0___RWC QCSR_REG_RO +#define WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_0__VAL___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_0__VAL___S 0 +#define WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_1 (0x00A93014) +#define WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_1___RWC QCSR_REG_RO +#define WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_1__VAL___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_PHY_TIMESTAMP2_IX_1__VAL___S 0 + +#define WMAC0_AMPI_R1_TESTBUS_CTRL (0x00A93018) +#define WMAC0_AMPI_R1_TESTBUS_CTRL___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_TESTBUS_CTRL___POR 0x00000000 +#define WMAC0_AMPI_R1_TESTBUS_CTRL__TESTBUS_SELECT___POR 0x00000000 +#define WMAC0_AMPI_R1_TESTBUS_CTRL__TESTBUS_SELECT___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_TESTBUS_CTRL__TESTBUS_SELECT___S 0 +#define WMAC0_AMPI_R1_TESTBUS_CTRL___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_TESTBUS_CTRL___S 0 + +#define WMAC0_AMPI_R1_DEBUG_RX_ERROR_COUNT (0x00A9301C) +#define WMAC0_AMPI_R1_DEBUG_RX_ERROR_COUNT___RWC QCSR_REG_RO +#define WMAC0_AMPI_R1_DEBUG_RX_ERROR_COUNT___POR 0x00000000 +#define WMAC0_AMPI_R1_DEBUG_RX_ERROR_COUNT__RX_TLV_ERROR___POR 0x0000 +#define WMAC0_AMPI_R1_DEBUG_RX_ERROR_COUNT__RX_TLV_ERROR___M 0x0000FFFF +#define WMAC0_AMPI_R1_DEBUG_RX_ERROR_COUNT__RX_TLV_ERROR___S 0 +#define WMAC0_AMPI_R1_DEBUG_RX_ERROR_COUNT___M 0x0000FFFF +#define WMAC0_AMPI_R1_DEBUG_RX_ERROR_COUNT___S 0 + +#define WMAC0_AMPI_R1_DEBUG_TX_ERROR_COUNT (0x00A93020) +#define WMAC0_AMPI_R1_DEBUG_TX_ERROR_COUNT___RWC QCSR_REG_RO +#define WMAC0_AMPI_R1_DEBUG_TX_ERROR_COUNT___POR 0x00000000 +#define WMAC0_AMPI_R1_DEBUG_TX_ERROR_COUNT__TX_TLV_ERROR___POR 0x0000 +#define WMAC0_AMPI_R1_DEBUG_TX_ERROR_COUNT__TX_TLV_ERROR___M 0x0000FFFF +#define WMAC0_AMPI_R1_DEBUG_TX_ERROR_COUNT__TX_TLV_ERROR___S 0 +#define WMAC0_AMPI_R1_DEBUG_TX_ERROR_COUNT___M 0x0000FFFF +#define WMAC0_AMPI_R1_DEBUG_TX_ERROR_COUNT___S 0 + +#define WMAC0_AMPI_R1_STALE_TIMESTAMP_COUNT (0x00A93024) +#define WMAC0_AMPI_R1_STALE_TIMESTAMP_COUNT___RWC QCSR_REG_RO +#define WMAC0_AMPI_R1_STALE_TIMESTAMP_COUNT___POR 0x00000000 +#define WMAC0_AMPI_R1_STALE_TIMESTAMP_COUNT__VAL___POR 0x0000 +#define WMAC0_AMPI_R1_STALE_TIMESTAMP_COUNT__VAL___M 0x0000FFFF +#define WMAC0_AMPI_R1_STALE_TIMESTAMP_COUNT__VAL___S 0 +#define WMAC0_AMPI_R1_STALE_TIMESTAMP_COUNT___M 0x0000FFFF +#define WMAC0_AMPI_R1_STALE_TIMESTAMP_COUNT___S 0 + +#define WMAC0_AMPI_R1_RX_SYNC_EVENT_COUNT (0x00A93028) +#define WMAC0_AMPI_R1_RX_SYNC_EVENT_COUNT___RWC QCSR_REG_RO +#define WMAC0_AMPI_R1_RX_SYNC_EVENT_COUNT___POR 0x00000000 +#define WMAC0_AMPI_R1_RX_SYNC_EVENT_COUNT__VAL___POR 0x0000 +#define WMAC0_AMPI_R1_RX_SYNC_EVENT_COUNT__VAL___M 0x0000FFFF +#define WMAC0_AMPI_R1_RX_SYNC_EVENT_COUNT__VAL___S 0 +#define WMAC0_AMPI_R1_RX_SYNC_EVENT_COUNT___M 0x0000FFFF +#define WMAC0_AMPI_R1_RX_SYNC_EVENT_COUNT___S 0 + +#define WMAC0_AMPI_R1_INSERT_TIMESTAMP_COUNT (0x00A9302C) +#define WMAC0_AMPI_R1_INSERT_TIMESTAMP_COUNT___RWC QCSR_REG_RO +#define WMAC0_AMPI_R1_INSERT_TIMESTAMP_COUNT___POR 0x00000000 +#define WMAC0_AMPI_R1_INSERT_TIMESTAMP_COUNT__VAL___POR 0x0000 +#define WMAC0_AMPI_R1_INSERT_TIMESTAMP_COUNT__VAL___M 0x0000FFFF +#define WMAC0_AMPI_R1_INSERT_TIMESTAMP_COUNT__VAL___S 0 +#define WMAC0_AMPI_R1_INSERT_TIMESTAMP_COUNT___M 0x0000FFFF +#define WMAC0_AMPI_R1_INSERT_TIMESTAMP_COUNT___S 0 + +#define WMAC0_AMPI_R1_INSERT_TX_TIMESTAMP_COUNT (0x00A93030) +#define WMAC0_AMPI_R1_INSERT_TX_TIMESTAMP_COUNT___RWC QCSR_REG_RO +#define WMAC0_AMPI_R1_INSERT_TX_TIMESTAMP_COUNT___POR 0x00000000 +#define WMAC0_AMPI_R1_INSERT_TX_TIMESTAMP_COUNT__VAL___POR 0x0000 +#define WMAC0_AMPI_R1_INSERT_TX_TIMESTAMP_COUNT__VAL___M 0x0000FFFF +#define WMAC0_AMPI_R1_INSERT_TX_TIMESTAMP_COUNT__VAL___S 0 +#define WMAC0_AMPI_R1_INSERT_TX_TIMESTAMP_COUNT___M 0x0000FFFF +#define WMAC0_AMPI_R1_INSERT_TX_TIMESTAMP_COUNT___S 0 + +#define WMAC0_AMPI_R1_PHY_CLK_INVALID_APB_ACC_ADR (0x00A93034) +#define WMAC0_AMPI_R1_PHY_CLK_INVALID_APB_ACC_ADR___RWC QCSR_REG_RO +#define WMAC0_AMPI_R1_PHY_CLK_INVALID_APB_ACC_ADR___POR 0x00000000 +#define WMAC0_AMPI_R1_PHY_CLK_INVALID_APB_ACC_ADR__VALUE___POR 0x00000 +#define WMAC0_AMPI_R1_PHY_CLK_INVALID_APB_ACC_ADR__VALUE___M 0x0001FFFF +#define WMAC0_AMPI_R1_PHY_CLK_INVALID_APB_ACC_ADR__VALUE___S 0 +#define WMAC0_AMPI_R1_PHY_CLK_INVALID_APB_ACC_ADR___M 0x0001FFFF +#define WMAC0_AMPI_R1_PHY_CLK_INVALID_APB_ACC_ADR___S 0 + +#define WMAC0_AMPI_R1_SM_STATES_IX_0 (0x00A93038) +#define WMAC0_AMPI_R1_SM_STATES_IX_0___RWC QCSR_REG_RO +#define WMAC0_AMPI_R1_SM_STATES_IX_0___POR 0x00000000 +#define WMAC0_AMPI_R1_SM_STATES_IX_0__TX_IDLE___POR 0x0 +#define WMAC0_AMPI_R1_SM_STATES_IX_0__TX_STATE___POR 0x00 +#define WMAC0_AMPI_R1_SM_STATES_IX_0__TX_IDLE___M 0x80000000 +#define WMAC0_AMPI_R1_SM_STATES_IX_0__TX_IDLE___S 31 +#define WMAC0_AMPI_R1_SM_STATES_IX_0__TX_STATE___M 0x0000003F +#define WMAC0_AMPI_R1_SM_STATES_IX_0__TX_STATE___S 0 +#define WMAC0_AMPI_R1_SM_STATES_IX_0___M 0x8000003F +#define WMAC0_AMPI_R1_SM_STATES_IX_0___S 0 + +#define WMAC0_AMPI_R1_SM_STATES_IX_1 (0x00A9303C) +#define WMAC0_AMPI_R1_SM_STATES_IX_1___RWC QCSR_REG_RO +#define WMAC0_AMPI_R1_SM_STATES_IX_1___POR 0x00000000 +#define WMAC0_AMPI_R1_SM_STATES_IX_1__RX_IDLE___POR 0x0 +#define WMAC0_AMPI_R1_SM_STATES_IX_1__RX_STATE___POR 0x000 +#define WMAC0_AMPI_R1_SM_STATES_IX_1__RX_IDLE___M 0x80000000 +#define WMAC0_AMPI_R1_SM_STATES_IX_1__RX_IDLE___S 31 +#define WMAC0_AMPI_R1_SM_STATES_IX_1__RX_STATE___M 0x000001FF +#define WMAC0_AMPI_R1_SM_STATES_IX_1__RX_STATE___S 0 +#define WMAC0_AMPI_R1_SM_STATES_IX_1___M 0x800001FF +#define WMAC0_AMPI_R1_SM_STATES_IX_1___S 0 + +#define WMAC0_AMPI_R1_EVENTMASK_IX_0 (0x00A93040) +#define WMAC0_AMPI_R1_EVENTMASK_IX_0___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_EVENTMASK_IX_0___POR 0x00000000 +#define WMAC0_AMPI_R1_EVENTMASK_IX_0__MASK___POR 0x00000000 +#define WMAC0_AMPI_R1_EVENTMASK_IX_0__MASK___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_EVENTMASK_IX_0__MASK___S 0 +#define WMAC0_AMPI_R1_EVENTMASK_IX_0___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_EVENTMASK_IX_0___S 0 + +#define WMAC0_AMPI_R1_DEBUG_EVENT_SELECT (0x00A93044) +#define WMAC0_AMPI_R1_DEBUG_EVENT_SELECT___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_DEBUG_EVENT_SELECT___POR 0x00000000 +#define WMAC0_AMPI_R1_DEBUG_EVENT_SELECT__EVENT_SEL___POR 0x0 +#define WMAC0_AMPI_R1_DEBUG_EVENT_SELECT__ENABLE_TPDM_STATUS___POR 0x0 +#define WMAC0_AMPI_R1_DEBUG_EVENT_SELECT__CDC_DEBUG_SEL___POR 0x0 +#define WMAC0_AMPI_R1_DEBUG_EVENT_SELECT__EVENT_SEL___M 0x00000078 +#define WMAC0_AMPI_R1_DEBUG_EVENT_SELECT__EVENT_SEL___S 3 +#define WMAC0_AMPI_R1_DEBUG_EVENT_SELECT__ENABLE_TPDM_STATUS___M 0x00000004 +#define WMAC0_AMPI_R1_DEBUG_EVENT_SELECT__ENABLE_TPDM_STATUS___S 2 +#define WMAC0_AMPI_R1_DEBUG_EVENT_SELECT__CDC_DEBUG_SEL___M 0x00000003 +#define WMAC0_AMPI_R1_DEBUG_EVENT_SELECT__CDC_DEBUG_SEL___S 0 +#define WMAC0_AMPI_R1_DEBUG_EVENT_SELECT___M 0x0000007F +#define WMAC0_AMPI_R1_DEBUG_EVENT_SELECT___S 0 + +#define WMAC0_AMPI_R1_TESTBUS_LOWER (0x00A93048) +#define WMAC0_AMPI_R1_TESTBUS_LOWER___RWC QCSR_REG_RO +#define WMAC0_AMPI_R1_TESTBUS_LOWER___POR 0x00000000 +#define WMAC0_AMPI_R1_TESTBUS_LOWER__VALUE___POR 0x00000000 +#define WMAC0_AMPI_R1_TESTBUS_LOWER__VALUE___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_TESTBUS_LOWER__VALUE___S 0 +#define WMAC0_AMPI_R1_TESTBUS_LOWER___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_TESTBUS_LOWER___S 0 + +#define WMAC0_AMPI_R1_TESTBUS_UPPER (0x00A9304C) +#define WMAC0_AMPI_R1_TESTBUS_UPPER___RWC QCSR_REG_RO +#define WMAC0_AMPI_R1_TESTBUS_UPPER___POR 0x00000000 +#define WMAC0_AMPI_R1_TESTBUS_UPPER__VALUE___POR 0x00 +#define WMAC0_AMPI_R1_TESTBUS_UPPER__VALUE___M 0x000000FF +#define WMAC0_AMPI_R1_TESTBUS_UPPER__VALUE___S 0 +#define WMAC0_AMPI_R1_TESTBUS_UPPER___M 0x000000FF +#define WMAC0_AMPI_R1_TESTBUS_UPPER___S 0 + +#define WMAC0_AMPI_R1_REG_ACCESS_EVENT_GEN_CTRL (0x00A93050) +#define WMAC0_AMPI_R1_REG_ACCESS_EVENT_GEN_CTRL___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_REG_ACCESS_EVENT_GEN_CTRL___POR 0x7FFE0002 +#define WMAC0_AMPI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___POR 0x3FFF +#define WMAC0_AMPI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___POR 0x0000 +#define WMAC0_AMPI_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___POR 0x1 +#define WMAC0_AMPI_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___POR 0x0 +#define WMAC0_AMPI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___M 0xFFFE0000 +#define WMAC0_AMPI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___S 17 +#define WMAC0_AMPI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___M 0x0001FFFC +#define WMAC0_AMPI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___S 2 +#define WMAC0_AMPI_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___M 0x00000002 +#define WMAC0_AMPI_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___S 1 +#define WMAC0_AMPI_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___M 0x00000001 +#define WMAC0_AMPI_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___S 0 +#define WMAC0_AMPI_R1_REG_ACCESS_EVENT_GEN_CTRL___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_REG_ACCESS_EVENT_GEN_CTRL___S 0 + +#define WMAC0_AMPI_R1_AMPI_SPARE_REGISTER (0x00A93054) +#define WMAC0_AMPI_R1_AMPI_SPARE_REGISTER___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_AMPI_SPARE_REGISTER___POR 0x00000000 +#define WMAC0_AMPI_R1_AMPI_SPARE_REGISTER__SPARE_FIELD___POR 0x0000 +#define WMAC0_AMPI_R1_AMPI_SPARE_REGISTER__SPARE_FIELD___M 0x0000FFFF +#define WMAC0_AMPI_R1_AMPI_SPARE_REGISTER__SPARE_FIELD___S 0 +#define WMAC0_AMPI_R1_AMPI_SPARE_REGISTER___M 0x0000FFFF +#define WMAC0_AMPI_R1_AMPI_SPARE_REGISTER___S 0 + +#define WMAC0_AMPI_R1_LOOPBACK_STATUS_1 (0x00A9305C) +#define WMAC0_AMPI_R1_LOOPBACK_STATUS_1___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_STATUS_1___POR 0x00000000 +#define WMAC0_AMPI_R1_LOOPBACK_STATUS_1__FETCH_SM_NON_IDLE___POR 0x0 +#define WMAC0_AMPI_R1_LOOPBACK_STATUS_1__OUTPUT_CONTROL_SM_NON_IDLE___POR 0x0 +#define WMAC0_AMPI_R1_LOOPBACK_STATUS_1__RX_CONTROL_SM_NON_IDLE___POR 0x0 +#define WMAC0_AMPI_R1_LOOPBACK_STATUS_1__INPUT_CONTROL_SM_NON_IDLE___POR 0x0 +#define WMAC0_AMPI_R1_LOOPBACK_STATUS_1__FETCH_CNT_CLR___POR 0x0 +#define WMAC0_AMPI_R1_LOOPBACK_STATUS_1__FETCH_CNT___POR 0x0000 +#define WMAC0_AMPI_R1_LOOPBACK_STATUS_1__FETCH_SM_NON_IDLE___M 0x00080000 +#define WMAC0_AMPI_R1_LOOPBACK_STATUS_1__FETCH_SM_NON_IDLE___S 19 +#define WMAC0_AMPI_R1_LOOPBACK_STATUS_1__OUTPUT_CONTROL_SM_NON_IDLE___M 0x00040000 +#define WMAC0_AMPI_R1_LOOPBACK_STATUS_1__OUTPUT_CONTROL_SM_NON_IDLE___S 18 +#define WMAC0_AMPI_R1_LOOPBACK_STATUS_1__RX_CONTROL_SM_NON_IDLE___M 0x00020000 +#define WMAC0_AMPI_R1_LOOPBACK_STATUS_1__RX_CONTROL_SM_NON_IDLE___S 17 +#define WMAC0_AMPI_R1_LOOPBACK_STATUS_1__INPUT_CONTROL_SM_NON_IDLE___M 0x00010000 +#define WMAC0_AMPI_R1_LOOPBACK_STATUS_1__INPUT_CONTROL_SM_NON_IDLE___S 16 +#define WMAC0_AMPI_R1_LOOPBACK_STATUS_1__FETCH_CNT_CLR___M 0x00008000 +#define WMAC0_AMPI_R1_LOOPBACK_STATUS_1__FETCH_CNT_CLR___S 15 +#define WMAC0_AMPI_R1_LOOPBACK_STATUS_1__FETCH_CNT___M 0x00007FFF +#define WMAC0_AMPI_R1_LOOPBACK_STATUS_1__FETCH_CNT___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_STATUS_1___M 0x000FFFFF +#define WMAC0_AMPI_R1_LOOPBACK_STATUS_1___S 0 + +#define WMAC0_AMPI_R1_LOOPBACK_STATUS_2 (0x00A93060) +#define WMAC0_AMPI_R1_LOOPBACK_STATUS_2___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_STATUS_2___POR 0x00000000 +#define WMAC0_AMPI_R1_LOOPBACK_STATUS_2__TX_CNT_CLR___POR 0x0 +#define WMAC0_AMPI_R1_LOOPBACK_STATUS_2__TX_CNT___POR 0x0000 +#define WMAC0_AMPI_R1_LOOPBACK_STATUS_2__TX_CNT_CLR___M 0x00008000 +#define WMAC0_AMPI_R1_LOOPBACK_STATUS_2__TX_CNT_CLR___S 15 +#define WMAC0_AMPI_R1_LOOPBACK_STATUS_2__TX_CNT___M 0x00007FFF +#define WMAC0_AMPI_R1_LOOPBACK_STATUS_2__TX_CNT___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_STATUS_2___M 0x0000FFFF +#define WMAC0_AMPI_R1_LOOPBACK_STATUS_2___S 0 + +#define WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1 (0x00A93064) +#define WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1___POR 0x00000000 +#define WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__RX_DONE_INDICATOR___POR 0x0 +#define WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__LOOPBACK_DUTY_CYCLE_CCA_EN___POR 0x0 +#define WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__TRIGGER_TIME___POR 0x00 +#define WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__RX_DUTY_CYCLE_BASED_TRIGGER___POR 0x0 +#define WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__RX_FETCH_TRIGGER___POR 0x0 +#define WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__RX_MODE_SEL___POR 0x0 +#define WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__RX_DONE_INDICATOR___M 0x00004000 +#define WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__RX_DONE_INDICATOR___S 14 +#define WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__LOOPBACK_DUTY_CYCLE_CCA_EN___M 0x00002000 +#define WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__LOOPBACK_DUTY_CYCLE_CCA_EN___S 13 +#define WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__TRIGGER_TIME___M 0x00001FE0 +#define WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__TRIGGER_TIME___S 5 +#define WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__RX_DUTY_CYCLE_BASED_TRIGGER___M 0x00000010 +#define WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__RX_DUTY_CYCLE_BASED_TRIGGER___S 4 +#define WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__RX_FETCH_TRIGGER___M 0x00000008 +#define WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__RX_FETCH_TRIGGER___S 3 +#define WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__RX_MODE_SEL___M 0x00000007 +#define WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1__RX_MODE_SEL___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1___M 0x00007FFF +#define WMAC0_AMPI_R1_LOOPBACK_RX_CTRL1___S 0 + +#define WMAC0_AMPI_R1_LOOPBACK_RX_CTRL2 (0x00A93068) +#define WMAC0_AMPI_R1_LOOPBACK_RX_CTRL2___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_RX_CTRL2___POR 0x00000000 +#define WMAC0_AMPI_R1_LOOPBACK_RX_CTRL2__RX_TLV_PTR_31_0___POR 0x00000000 +#define WMAC0_AMPI_R1_LOOPBACK_RX_CTRL2__RX_TLV_PTR_31_0___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_RX_CTRL2__RX_TLV_PTR_31_0___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_RX_CTRL2___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_RX_CTRL2___S 0 + +#define WMAC0_AMPI_R1_CCA_CTRL (0x00A9306C) +#define WMAC0_AMPI_R1_CCA_CTRL___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_CCA_CTRL___POR 0x00000000 +#define WMAC0_AMPI_R1_CCA_CTRL__CCA_IDLE_TIME___POR 0x0000 +#define WMAC0_AMPI_R1_CCA_CTRL__CCA_BUSY_TIME___POR 0x0000 +#define WMAC0_AMPI_R1_CCA_CTRL__CCA_IDLE_TIME___M 0xFFFF0000 +#define WMAC0_AMPI_R1_CCA_CTRL__CCA_IDLE_TIME___S 16 +#define WMAC0_AMPI_R1_CCA_CTRL__CCA_BUSY_TIME___M 0x0000FFFF +#define WMAC0_AMPI_R1_CCA_CTRL__CCA_BUSY_TIME___S 0 +#define WMAC0_AMPI_R1_CCA_CTRL___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_CCA_CTRL___S 0 + +#define WMAC0_AMPI_R1_LOOPBACK_CCA_CFG (0x00A93070) +#define WMAC0_AMPI_R1_LOOPBACK_CCA_CFG___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_CCA_CFG___POR 0x00000000 +#define WMAC0_AMPI_R1_LOOPBACK_CCA_CFG__THR_VALUE___POR 0x00 +#define WMAC0_AMPI_R1_LOOPBACK_CCA_CFG__SELECT___POR 0x00 +#define WMAC0_AMPI_R1_LOOPBACK_CCA_CFG__THR_VALUE___M 0x00003FC0 +#define WMAC0_AMPI_R1_LOOPBACK_CCA_CFG__THR_VALUE___S 6 +#define WMAC0_AMPI_R1_LOOPBACK_CCA_CFG__SELECT___M 0x0000003F +#define WMAC0_AMPI_R1_LOOPBACK_CCA_CFG__SELECT___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_CCA_CFG___M 0x00003FFF +#define WMAC0_AMPI_R1_LOOPBACK_CCA_CFG___S 0 + +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_n(n) (0x00A93074+0x4*(n)) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_n_nMIN 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_n_nMAX 511 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_n_ELEM 512 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_n___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_n___POR 0x00000000 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_n__DATA___POR 0x00000000 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_n__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_n__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_n___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_n___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_0 (0x00A93074) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_0___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_0__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_0__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_1 (0x00A93078) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_1___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_1__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_1__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_2 (0x00A9307C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_2___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_2__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_2__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_3 (0x00A93080) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_3___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_3__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_3__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_4 (0x00A93084) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_4___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_4__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_4__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_5 (0x00A93088) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_5___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_5__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_5__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_6 (0x00A9308C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_6___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_6__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_6__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_7 (0x00A93090) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_7___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_7__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_7__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_8 (0x00A93094) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_8___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_8__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_8__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_9 (0x00A93098) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_9___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_9__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_9__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_10 (0x00A9309C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_10___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_10__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_10__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_11 (0x00A930A0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_11___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_11__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_11__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_12 (0x00A930A4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_12___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_12__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_12__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_13 (0x00A930A8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_13___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_13__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_13__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_14 (0x00A930AC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_14___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_14__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_14__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_15 (0x00A930B0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_15___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_15__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_15__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_16 (0x00A930B4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_16___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_16__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_16__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_17 (0x00A930B8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_17___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_17__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_17__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_18 (0x00A930BC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_18___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_18__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_18__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_19 (0x00A930C0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_19___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_19__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_19__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_20 (0x00A930C4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_20___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_20__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_20__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_21 (0x00A930C8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_21___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_21__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_21__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_22 (0x00A930CC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_22___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_22__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_22__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_23 (0x00A930D0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_23___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_23__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_23__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_24 (0x00A930D4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_24___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_24__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_24__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_25 (0x00A930D8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_25___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_25__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_25__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_26 (0x00A930DC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_26___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_26__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_26__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_27 (0x00A930E0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_27___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_27__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_27__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_28 (0x00A930E4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_28___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_28__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_28__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_29 (0x00A930E8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_29___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_29__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_29__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_30 (0x00A930EC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_30___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_30__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_30__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_31 (0x00A930F0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_31___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_31__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_31__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_32 (0x00A930F4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_32___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_32__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_32__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_33 (0x00A930F8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_33___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_33__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_33__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_34 (0x00A930FC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_34___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_34__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_34__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_35 (0x00A93100) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_35___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_35__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_35__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_36 (0x00A93104) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_36___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_36__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_36__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_37 (0x00A93108) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_37___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_37__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_37__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_38 (0x00A9310C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_38___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_38__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_38__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_39 (0x00A93110) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_39___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_39__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_39__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_40 (0x00A93114) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_40___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_40__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_40__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_41 (0x00A93118) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_41___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_41__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_41__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_42 (0x00A9311C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_42___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_42__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_42__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_43 (0x00A93120) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_43___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_43__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_43__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_44 (0x00A93124) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_44___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_44__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_44__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_45 (0x00A93128) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_45___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_45__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_45__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_46 (0x00A9312C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_46___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_46__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_46__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_47 (0x00A93130) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_47___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_47__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_47__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_48 (0x00A93134) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_48___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_48__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_48__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_49 (0x00A93138) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_49___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_49__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_49__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_50 (0x00A9313C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_50___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_50__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_50__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_51 (0x00A93140) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_51___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_51__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_51__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_52 (0x00A93144) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_52___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_52__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_52__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_53 (0x00A93148) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_53___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_53__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_53__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_54 (0x00A9314C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_54___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_54__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_54__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_55 (0x00A93150) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_55___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_55__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_55__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_56 (0x00A93154) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_56___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_56__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_56__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_57 (0x00A93158) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_57___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_57__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_57__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_58 (0x00A9315C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_58___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_58__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_58__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_59 (0x00A93160) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_59___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_59__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_59__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_60 (0x00A93164) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_60___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_60__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_60__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_61 (0x00A93168) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_61___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_61__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_61__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_62 (0x00A9316C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_62___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_62__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_62__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_63 (0x00A93170) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_63___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_63__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_63__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_64 (0x00A93174) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_64___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_64__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_64__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_65 (0x00A93178) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_65___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_65__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_65__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_66 (0x00A9317C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_66___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_66__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_66__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_67 (0x00A93180) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_67___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_67__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_67__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_68 (0x00A93184) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_68___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_68__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_68__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_69 (0x00A93188) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_69___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_69__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_69__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_70 (0x00A9318C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_70___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_70__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_70__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_71 (0x00A93190) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_71___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_71__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_71__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_72 (0x00A93194) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_72___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_72__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_72__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_73 (0x00A93198) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_73___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_73__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_73__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_74 (0x00A9319C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_74___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_74__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_74__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_75 (0x00A931A0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_75___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_75__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_75__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_76 (0x00A931A4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_76___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_76__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_76__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_77 (0x00A931A8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_77___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_77__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_77__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_78 (0x00A931AC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_78___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_78__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_78__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_79 (0x00A931B0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_79___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_79__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_79__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_80 (0x00A931B4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_80___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_80__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_80__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_81 (0x00A931B8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_81___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_81__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_81__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_82 (0x00A931BC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_82___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_82__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_82__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_83 (0x00A931C0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_83___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_83__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_83__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_84 (0x00A931C4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_84___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_84__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_84__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_85 (0x00A931C8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_85___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_85__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_85__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_86 (0x00A931CC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_86___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_86__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_86__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_87 (0x00A931D0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_87___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_87__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_87__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_88 (0x00A931D4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_88___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_88__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_88__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_89 (0x00A931D8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_89___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_89__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_89__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_90 (0x00A931DC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_90___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_90__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_90__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_91 (0x00A931E0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_91___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_91__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_91__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_92 (0x00A931E4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_92___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_92__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_92__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_93 (0x00A931E8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_93___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_93__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_93__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_94 (0x00A931EC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_94___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_94__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_94__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_95 (0x00A931F0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_95___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_95__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_95__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_96 (0x00A931F4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_96___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_96__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_96__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_97 (0x00A931F8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_97___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_97__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_97__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_98 (0x00A931FC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_98___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_98__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_98__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_99 (0x00A93200) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_99___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_99__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_99__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_100 (0x00A93204) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_100___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_100__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_100__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_101 (0x00A93208) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_101___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_101__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_101__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_102 (0x00A9320C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_102___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_102__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_102__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_103 (0x00A93210) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_103___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_103__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_103__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_104 (0x00A93214) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_104___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_104__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_104__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_105 (0x00A93218) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_105___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_105__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_105__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_106 (0x00A9321C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_106___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_106__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_106__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_107 (0x00A93220) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_107___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_107__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_107__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_108 (0x00A93224) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_108___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_108__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_108__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_109 (0x00A93228) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_109___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_109__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_109__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_110 (0x00A9322C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_110___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_110__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_110__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_111 (0x00A93230) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_111___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_111__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_111__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_112 (0x00A93234) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_112___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_112__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_112__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_113 (0x00A93238) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_113___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_113__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_113__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_114 (0x00A9323C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_114___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_114__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_114__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_115 (0x00A93240) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_115___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_115__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_115__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_116 (0x00A93244) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_116___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_116__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_116__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_117 (0x00A93248) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_117___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_117__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_117__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_118 (0x00A9324C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_118___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_118__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_118__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_119 (0x00A93250) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_119___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_119__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_119__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_120 (0x00A93254) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_120___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_120__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_120__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_121 (0x00A93258) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_121___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_121__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_121__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_122 (0x00A9325C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_122___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_122__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_122__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_123 (0x00A93260) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_123___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_123__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_123__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_124 (0x00A93264) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_124___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_124__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_124__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_125 (0x00A93268) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_125___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_125__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_125__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_126 (0x00A9326C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_126___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_126__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_126__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_127 (0x00A93270) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_127___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_127__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_127__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_128 (0x00A93274) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_128___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_128__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_128__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_129 (0x00A93278) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_129___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_129__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_129__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_130 (0x00A9327C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_130___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_130__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_130__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_131 (0x00A93280) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_131___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_131__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_131__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_132 (0x00A93284) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_132___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_132__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_132__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_133 (0x00A93288) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_133___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_133__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_133__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_134 (0x00A9328C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_134___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_134__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_134__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_135 (0x00A93290) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_135___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_135__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_135__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_136 (0x00A93294) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_136___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_136__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_136__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_137 (0x00A93298) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_137___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_137__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_137__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_138 (0x00A9329C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_138___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_138__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_138__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_139 (0x00A932A0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_139___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_139__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_139__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_140 (0x00A932A4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_140___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_140__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_140__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_141 (0x00A932A8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_141___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_141__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_141__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_142 (0x00A932AC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_142___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_142__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_142__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_143 (0x00A932B0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_143___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_143__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_143__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_144 (0x00A932B4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_144___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_144__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_144__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_145 (0x00A932B8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_145___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_145__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_145__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_146 (0x00A932BC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_146___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_146__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_146__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_147 (0x00A932C0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_147___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_147__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_147__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_148 (0x00A932C4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_148___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_148__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_148__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_149 (0x00A932C8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_149___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_149__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_149__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_150 (0x00A932CC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_150___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_150__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_150__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_151 (0x00A932D0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_151___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_151__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_151__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_152 (0x00A932D4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_152___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_152__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_152__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_153 (0x00A932D8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_153___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_153__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_153__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_154 (0x00A932DC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_154___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_154__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_154__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_155 (0x00A932E0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_155___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_155__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_155__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_156 (0x00A932E4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_156___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_156__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_156__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_157 (0x00A932E8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_157___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_157__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_157__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_158 (0x00A932EC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_158___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_158__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_158__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_159 (0x00A932F0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_159___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_159__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_159__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_160 (0x00A932F4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_160___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_160__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_160__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_161 (0x00A932F8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_161___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_161__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_161__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_162 (0x00A932FC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_162___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_162__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_162__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_163 (0x00A93300) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_163___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_163__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_163__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_164 (0x00A93304) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_164___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_164__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_164__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_165 (0x00A93308) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_165___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_165__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_165__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_166 (0x00A9330C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_166___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_166__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_166__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_167 (0x00A93310) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_167___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_167__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_167__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_168 (0x00A93314) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_168___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_168__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_168__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_169 (0x00A93318) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_169___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_169__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_169__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_170 (0x00A9331C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_170___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_170__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_170__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_171 (0x00A93320) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_171___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_171__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_171__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_172 (0x00A93324) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_172___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_172__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_172__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_173 (0x00A93328) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_173___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_173__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_173__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_174 (0x00A9332C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_174___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_174__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_174__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_175 (0x00A93330) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_175___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_175__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_175__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_176 (0x00A93334) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_176___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_176__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_176__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_177 (0x00A93338) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_177___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_177__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_177__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_178 (0x00A9333C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_178___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_178__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_178__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_179 (0x00A93340) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_179___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_179__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_179__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_180 (0x00A93344) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_180___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_180__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_180__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_181 (0x00A93348) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_181___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_181__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_181__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_182 (0x00A9334C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_182___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_182__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_182__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_183 (0x00A93350) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_183___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_183__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_183__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_184 (0x00A93354) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_184___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_184__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_184__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_185 (0x00A93358) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_185___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_185__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_185__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_186 (0x00A9335C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_186___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_186__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_186__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_187 (0x00A93360) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_187___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_187__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_187__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_188 (0x00A93364) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_188___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_188__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_188__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_189 (0x00A93368) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_189___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_189__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_189__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_190 (0x00A9336C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_190___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_190__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_190__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_191 (0x00A93370) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_191___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_191__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_191__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_192 (0x00A93374) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_192___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_192__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_192__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_193 (0x00A93378) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_193___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_193__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_193__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_194 (0x00A9337C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_194___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_194__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_194__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_195 (0x00A93380) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_195___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_195__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_195__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_196 (0x00A93384) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_196___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_196__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_196__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_197 (0x00A93388) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_197___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_197__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_197__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_198 (0x00A9338C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_198___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_198__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_198__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_199 (0x00A93390) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_199___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_199__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_199__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_200 (0x00A93394) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_200___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_200__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_200__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_201 (0x00A93398) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_201___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_201__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_201__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_202 (0x00A9339C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_202___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_202__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_202__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_203 (0x00A933A0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_203___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_203__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_203__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_204 (0x00A933A4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_204___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_204__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_204__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_205 (0x00A933A8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_205___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_205__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_205__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_206 (0x00A933AC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_206___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_206__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_206__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_207 (0x00A933B0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_207___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_207__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_207__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_208 (0x00A933B4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_208___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_208__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_208__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_209 (0x00A933B8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_209___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_209__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_209__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_210 (0x00A933BC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_210___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_210__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_210__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_211 (0x00A933C0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_211___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_211__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_211__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_212 (0x00A933C4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_212___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_212__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_212__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_213 (0x00A933C8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_213___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_213__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_213__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_214 (0x00A933CC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_214___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_214__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_214__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_215 (0x00A933D0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_215___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_215__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_215__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_216 (0x00A933D4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_216___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_216__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_216__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_217 (0x00A933D8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_217___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_217__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_217__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_218 (0x00A933DC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_218___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_218__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_218__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_219 (0x00A933E0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_219___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_219__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_219__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_220 (0x00A933E4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_220___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_220__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_220__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_221 (0x00A933E8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_221___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_221__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_221__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_222 (0x00A933EC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_222___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_222__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_222__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_223 (0x00A933F0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_223___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_223__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_223__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_224 (0x00A933F4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_224___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_224__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_224__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_225 (0x00A933F8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_225___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_225__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_225__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_226 (0x00A933FC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_226___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_226__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_226__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_227 (0x00A93400) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_227___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_227__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_227__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_228 (0x00A93404) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_228___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_228__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_228__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_229 (0x00A93408) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_229___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_229__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_229__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_230 (0x00A9340C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_230___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_230__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_230__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_231 (0x00A93410) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_231___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_231__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_231__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_232 (0x00A93414) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_232___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_232__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_232__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_233 (0x00A93418) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_233___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_233__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_233__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_234 (0x00A9341C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_234___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_234__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_234__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_235 (0x00A93420) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_235___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_235__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_235__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_236 (0x00A93424) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_236___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_236__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_236__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_237 (0x00A93428) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_237___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_237__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_237__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_238 (0x00A9342C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_238___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_238__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_238__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_239 (0x00A93430) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_239___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_239__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_239__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_240 (0x00A93434) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_240___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_240__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_240__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_241 (0x00A93438) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_241___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_241__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_241__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_242 (0x00A9343C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_242___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_242__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_242__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_243 (0x00A93440) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_243___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_243__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_243__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_244 (0x00A93444) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_244___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_244__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_244__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_245 (0x00A93448) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_245___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_245__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_245__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_246 (0x00A9344C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_246___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_246__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_246__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_247 (0x00A93450) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_247___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_247__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_247__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_248 (0x00A93454) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_248___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_248__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_248__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_249 (0x00A93458) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_249___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_249__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_249__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_250 (0x00A9345C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_250___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_250__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_250__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_251 (0x00A93460) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_251___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_251__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_251__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_252 (0x00A93464) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_252___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_252__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_252__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_253 (0x00A93468) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_253___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_253__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_253__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_254 (0x00A9346C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_254___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_254__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_254__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_255 (0x00A93470) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_255___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_255__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_255__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_256 (0x00A93474) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_256___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_256__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_256__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_257 (0x00A93478) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_257___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_257__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_257__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_258 (0x00A9347C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_258___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_258__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_258__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_259 (0x00A93480) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_259___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_259__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_259__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_260 (0x00A93484) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_260___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_260__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_260__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_261 (0x00A93488) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_261___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_261__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_261__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_262 (0x00A9348C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_262___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_262__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_262__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_263 (0x00A93490) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_263___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_263__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_263__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_264 (0x00A93494) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_264___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_264__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_264__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_265 (0x00A93498) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_265___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_265__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_265__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_266 (0x00A9349C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_266___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_266__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_266__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_267 (0x00A934A0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_267___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_267__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_267__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_268 (0x00A934A4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_268___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_268__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_268__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_269 (0x00A934A8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_269___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_269__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_269__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_270 (0x00A934AC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_270___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_270__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_270__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_271 (0x00A934B0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_271___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_271__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_271__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_272 (0x00A934B4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_272___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_272__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_272__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_273 (0x00A934B8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_273___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_273__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_273__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_274 (0x00A934BC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_274___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_274__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_274__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_275 (0x00A934C0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_275___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_275__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_275__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_276 (0x00A934C4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_276___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_276__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_276__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_277 (0x00A934C8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_277___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_277__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_277__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_278 (0x00A934CC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_278___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_278__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_278__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_279 (0x00A934D0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_279___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_279__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_279__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_280 (0x00A934D4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_280___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_280__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_280__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_281 (0x00A934D8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_281___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_281__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_281__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_282 (0x00A934DC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_282___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_282__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_282__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_283 (0x00A934E0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_283___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_283__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_283__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_284 (0x00A934E4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_284___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_284__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_284__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_285 (0x00A934E8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_285___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_285__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_285__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_286 (0x00A934EC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_286___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_286__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_286__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_287 (0x00A934F0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_287___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_287__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_287__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_288 (0x00A934F4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_288___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_288__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_288__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_289 (0x00A934F8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_289___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_289__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_289__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_290 (0x00A934FC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_290___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_290__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_290__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_291 (0x00A93500) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_291___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_291__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_291__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_292 (0x00A93504) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_292___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_292__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_292__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_293 (0x00A93508) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_293___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_293__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_293__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_294 (0x00A9350C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_294___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_294__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_294__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_295 (0x00A93510) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_295___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_295__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_295__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_296 (0x00A93514) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_296___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_296__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_296__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_297 (0x00A93518) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_297___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_297__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_297__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_298 (0x00A9351C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_298___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_298__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_298__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_299 (0x00A93520) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_299___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_299__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_299__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_300 (0x00A93524) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_300___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_300__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_300__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_301 (0x00A93528) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_301___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_301__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_301__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_302 (0x00A9352C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_302___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_302__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_302__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_303 (0x00A93530) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_303___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_303__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_303__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_304 (0x00A93534) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_304___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_304__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_304__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_305 (0x00A93538) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_305___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_305__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_305__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_306 (0x00A9353C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_306___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_306__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_306__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_307 (0x00A93540) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_307___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_307__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_307__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_308 (0x00A93544) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_308___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_308__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_308__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_309 (0x00A93548) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_309___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_309__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_309__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_310 (0x00A9354C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_310___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_310__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_310__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_311 (0x00A93550) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_311___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_311__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_311__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_312 (0x00A93554) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_312___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_312__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_312__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_313 (0x00A93558) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_313___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_313__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_313__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_314 (0x00A9355C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_314___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_314__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_314__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_315 (0x00A93560) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_315___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_315__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_315__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_316 (0x00A93564) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_316___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_316__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_316__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_317 (0x00A93568) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_317___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_317__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_317__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_318 (0x00A9356C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_318___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_318__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_318__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_319 (0x00A93570) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_319___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_319__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_319__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_320 (0x00A93574) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_320___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_320__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_320__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_321 (0x00A93578) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_321___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_321__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_321__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_322 (0x00A9357C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_322___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_322__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_322__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_323 (0x00A93580) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_323___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_323__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_323__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_324 (0x00A93584) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_324___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_324__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_324__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_325 (0x00A93588) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_325___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_325__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_325__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_326 (0x00A9358C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_326___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_326__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_326__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_327 (0x00A93590) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_327___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_327__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_327__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_328 (0x00A93594) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_328___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_328__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_328__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_329 (0x00A93598) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_329___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_329__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_329__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_330 (0x00A9359C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_330___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_330__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_330__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_331 (0x00A935A0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_331___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_331__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_331__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_332 (0x00A935A4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_332___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_332__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_332__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_333 (0x00A935A8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_333___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_333__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_333__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_334 (0x00A935AC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_334___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_334__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_334__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_335 (0x00A935B0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_335___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_335__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_335__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_336 (0x00A935B4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_336___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_336__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_336__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_337 (0x00A935B8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_337___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_337__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_337__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_338 (0x00A935BC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_338___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_338__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_338__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_339 (0x00A935C0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_339___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_339__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_339__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_340 (0x00A935C4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_340___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_340__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_340__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_341 (0x00A935C8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_341___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_341__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_341__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_342 (0x00A935CC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_342___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_342__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_342__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_343 (0x00A935D0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_343___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_343__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_343__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_344 (0x00A935D4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_344___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_344__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_344__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_345 (0x00A935D8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_345___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_345__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_345__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_346 (0x00A935DC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_346___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_346__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_346__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_347 (0x00A935E0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_347___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_347__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_347__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_348 (0x00A935E4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_348___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_348__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_348__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_349 (0x00A935E8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_349___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_349__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_349__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_350 (0x00A935EC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_350___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_350__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_350__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_351 (0x00A935F0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_351___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_351__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_351__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_352 (0x00A935F4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_352___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_352__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_352__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_353 (0x00A935F8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_353___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_353__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_353__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_354 (0x00A935FC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_354___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_354__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_354__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_355 (0x00A93600) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_355___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_355__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_355__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_356 (0x00A93604) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_356___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_356__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_356__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_357 (0x00A93608) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_357___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_357__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_357__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_358 (0x00A9360C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_358___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_358__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_358__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_359 (0x00A93610) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_359___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_359__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_359__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_360 (0x00A93614) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_360___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_360__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_360__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_361 (0x00A93618) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_361___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_361__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_361__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_362 (0x00A9361C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_362___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_362__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_362__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_363 (0x00A93620) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_363___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_363__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_363__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_364 (0x00A93624) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_364___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_364__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_364__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_365 (0x00A93628) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_365___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_365__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_365__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_366 (0x00A9362C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_366___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_366__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_366__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_367 (0x00A93630) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_367___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_367__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_367__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_368 (0x00A93634) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_368___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_368__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_368__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_369 (0x00A93638) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_369___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_369__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_369__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_370 (0x00A9363C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_370___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_370__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_370__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_371 (0x00A93640) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_371___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_371__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_371__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_372 (0x00A93644) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_372___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_372__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_372__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_373 (0x00A93648) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_373___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_373__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_373__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_374 (0x00A9364C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_374___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_374__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_374__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_375 (0x00A93650) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_375___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_375__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_375__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_376 (0x00A93654) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_376___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_376__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_376__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_377 (0x00A93658) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_377___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_377__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_377__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_378 (0x00A9365C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_378___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_378__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_378__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_379 (0x00A93660) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_379___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_379__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_379__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_380 (0x00A93664) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_380___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_380__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_380__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_381 (0x00A93668) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_381___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_381__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_381__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_382 (0x00A9366C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_382___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_382__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_382__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_383 (0x00A93670) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_383___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_383__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_383__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_384 (0x00A93674) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_384___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_384__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_384__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_385 (0x00A93678) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_385___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_385__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_385__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_386 (0x00A9367C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_386___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_386__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_386__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_387 (0x00A93680) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_387___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_387__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_387__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_388 (0x00A93684) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_388___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_388__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_388__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_389 (0x00A93688) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_389___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_389__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_389__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_390 (0x00A9368C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_390___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_390__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_390__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_391 (0x00A93690) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_391___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_391__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_391__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_392 (0x00A93694) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_392___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_392__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_392__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_393 (0x00A93698) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_393___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_393__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_393__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_394 (0x00A9369C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_394___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_394__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_394__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_395 (0x00A936A0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_395___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_395__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_395__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_396 (0x00A936A4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_396___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_396__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_396__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_397 (0x00A936A8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_397___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_397__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_397__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_398 (0x00A936AC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_398___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_398__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_398__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_399 (0x00A936B0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_399___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_399__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_399__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_400 (0x00A936B4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_400___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_400__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_400__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_401 (0x00A936B8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_401___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_401__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_401__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_402 (0x00A936BC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_402___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_402__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_402__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_403 (0x00A936C0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_403___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_403__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_403__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_404 (0x00A936C4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_404___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_404__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_404__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_405 (0x00A936C8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_405___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_405__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_405__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_406 (0x00A936CC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_406___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_406__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_406__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_407 (0x00A936D0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_407___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_407__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_407__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_408 (0x00A936D4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_408___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_408__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_408__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_409 (0x00A936D8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_409___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_409__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_409__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_410 (0x00A936DC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_410___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_410__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_410__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_411 (0x00A936E0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_411___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_411__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_411__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_412 (0x00A936E4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_412___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_412__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_412__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_413 (0x00A936E8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_413___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_413__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_413__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_414 (0x00A936EC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_414___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_414__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_414__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_415 (0x00A936F0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_415___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_415__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_415__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_416 (0x00A936F4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_416___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_416__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_416__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_417 (0x00A936F8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_417___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_417__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_417__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_418 (0x00A936FC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_418___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_418__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_418__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_419 (0x00A93700) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_419___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_419__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_419__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_420 (0x00A93704) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_420___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_420__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_420__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_421 (0x00A93708) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_421___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_421__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_421__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_422 (0x00A9370C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_422___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_422__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_422__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_423 (0x00A93710) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_423___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_423__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_423__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_424 (0x00A93714) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_424___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_424__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_424__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_425 (0x00A93718) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_425___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_425__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_425__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_426 (0x00A9371C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_426___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_426__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_426__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_427 (0x00A93720) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_427___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_427__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_427__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_428 (0x00A93724) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_428___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_428__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_428__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_429 (0x00A93728) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_429___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_429__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_429__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_430 (0x00A9372C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_430___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_430__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_430__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_431 (0x00A93730) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_431___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_431__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_431__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_432 (0x00A93734) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_432___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_432__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_432__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_433 (0x00A93738) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_433___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_433__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_433__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_434 (0x00A9373C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_434___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_434__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_434__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_435 (0x00A93740) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_435___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_435__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_435__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_436 (0x00A93744) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_436___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_436__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_436__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_437 (0x00A93748) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_437___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_437__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_437__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_438 (0x00A9374C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_438___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_438__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_438__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_439 (0x00A93750) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_439___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_439__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_439__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_440 (0x00A93754) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_440___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_440__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_440__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_441 (0x00A93758) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_441___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_441__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_441__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_442 (0x00A9375C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_442___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_442__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_442__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_443 (0x00A93760) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_443___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_443__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_443__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_444 (0x00A93764) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_444___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_444__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_444__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_445 (0x00A93768) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_445___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_445__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_445__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_446 (0x00A9376C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_446___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_446__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_446__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_447 (0x00A93770) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_447___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_447__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_447__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_448 (0x00A93774) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_448___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_448__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_448__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_449 (0x00A93778) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_449___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_449__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_449__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_450 (0x00A9377C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_450___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_450__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_450__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_451 (0x00A93780) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_451___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_451__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_451__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_452 (0x00A93784) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_452___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_452__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_452__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_453 (0x00A93788) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_453___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_453__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_453__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_454 (0x00A9378C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_454___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_454__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_454__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_455 (0x00A93790) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_455___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_455__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_455__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_456 (0x00A93794) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_456___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_456__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_456__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_457 (0x00A93798) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_457___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_457__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_457__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_458 (0x00A9379C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_458___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_458__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_458__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_459 (0x00A937A0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_459___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_459__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_459__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_460 (0x00A937A4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_460___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_460__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_460__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_461 (0x00A937A8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_461___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_461__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_461__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_462 (0x00A937AC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_462___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_462__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_462__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_463 (0x00A937B0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_463___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_463__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_463__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_464 (0x00A937B4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_464___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_464__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_464__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_465 (0x00A937B8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_465___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_465__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_465__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_466 (0x00A937BC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_466___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_466__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_466__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_467 (0x00A937C0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_467___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_467__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_467__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_468 (0x00A937C4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_468___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_468__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_468__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_469 (0x00A937C8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_469___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_469__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_469__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_470 (0x00A937CC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_470___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_470__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_470__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_471 (0x00A937D0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_471___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_471__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_471__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_472 (0x00A937D4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_472___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_472__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_472__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_473 (0x00A937D8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_473___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_473__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_473__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_474 (0x00A937DC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_474___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_474__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_474__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_475 (0x00A937E0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_475___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_475__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_475__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_476 (0x00A937E4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_476___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_476__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_476__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_477 (0x00A937E8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_477___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_477__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_477__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_478 (0x00A937EC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_478___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_478__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_478__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_479 (0x00A937F0) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_479___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_479__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_479__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_480 (0x00A937F4) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_480___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_480__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_480__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_481 (0x00A937F8) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_481___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_481__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_481__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_482 (0x00A937FC) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_482___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_482__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_482__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_483 (0x00A93800) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_483___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_483__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_483__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_484 (0x00A93804) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_484___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_484__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_484__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_485 (0x00A93808) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_485___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_485__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_485__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_486 (0x00A9380C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_486___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_486__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_486__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_487 (0x00A93810) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_487___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_487__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_487__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_488 (0x00A93814) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_488___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_488__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_488__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_489 (0x00A93818) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_489___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_489__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_489__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_490 (0x00A9381C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_490___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_490__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_490__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_491 (0x00A93820) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_491___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_491__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_491__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_492 (0x00A93824) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_492___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_492__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_492__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_493 (0x00A93828) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_493___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_493__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_493__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_494 (0x00A9382C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_494___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_494__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_494__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_495 (0x00A93830) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_495___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_495__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_495__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_496 (0x00A93834) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_496___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_496__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_496__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_497 (0x00A93838) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_497___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_497__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_497__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_498 (0x00A9383C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_498___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_498__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_498__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_499 (0x00A93840) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_499___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_499__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_499__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_500 (0x00A93844) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_500___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_500__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_500__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_501 (0x00A93848) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_501___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_501__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_501__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_502 (0x00A9384C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_502___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_502__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_502__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_503 (0x00A93850) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_503___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_503__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_503__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_504 (0x00A93854) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_504___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_504__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_504__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_505 (0x00A93858) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_505___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_505__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_505__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_506 (0x00A9385C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_506___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_506__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_506__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_507 (0x00A93860) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_507___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_507__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_507__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_508 (0x00A93864) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_508___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_508__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_508__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_509 (0x00A93868) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_509___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_509__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_509__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_510 (0x00A9386C) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_510___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_510__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_510__DATA___S 0 +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_511 (0x00A93870) +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_511___RWC QCSR_REG_RW +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_511__DATA___M 0xFFFFFFFF +#define WMAC0_AMPI_R1_LOOPBACK_BUFFER_511__DATA___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_CONFIG (0x00A95000) +#define WMAC0_RXOLE_RXOLE_R0_CONFIG___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_CONFIG___POR 0xDECF8300 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_FLUSH_ON_INCOMPLETE_TLV___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_FLUSH_ON_TLV_SEQ_ERR___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__OVERRIDE_INTR_ON_TIMEOUT___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_TIMEOUT_IDLE___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_TIMEOUT_CORE___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_TIMEOUT_MSDU_PARSE___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_TIMEOUT_SFM_READ___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_TIMEOUT_FLUSH___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__REPORT_DA_SW_PEER_ID___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__PROTOCOL_FROM_AH_OR_L4___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__PROTOCOL_FROM_AH_OR_ESP___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__UPDATE_DA_STATS___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__MAC_ID___POR 0x3 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__ASE_SA_SEARCH_SKIP___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__ASE_DA_SEARCH_SKIP___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__FLOW_SEARCH_SKIP___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__STOP_NEXT_PPDU_ENABLE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__STOP_NEXT_PPDU___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__CCE_ENABLE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__ALWAYS_FORCE_BYPASS___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__PACKET_OFFSET_RXDMA_SELECT___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_FORCE_BYPASS___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__RX_HDR_BYTELEN___POR 0x100 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_FLUSH_ON_INCOMPLETE_TLV___M 0x80000000 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_FLUSH_ON_INCOMPLETE_TLV___S 31 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_FLUSH_ON_TLV_SEQ_ERR___M 0x40000000 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_FLUSH_ON_TLV_SEQ_ERR___S 30 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__OVERRIDE_INTR_ON_TIMEOUT___M 0x20000000 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__OVERRIDE_INTR_ON_TIMEOUT___S 29 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_TIMEOUT_IDLE___M 0x10000000 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_TIMEOUT_IDLE___S 28 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_TIMEOUT_CORE___M 0x08000000 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_TIMEOUT_CORE___S 27 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_TIMEOUT_MSDU_PARSE___M 0x04000000 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_TIMEOUT_MSDU_PARSE___S 26 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_TIMEOUT_SFM_READ___M 0x02000000 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_TIMEOUT_SFM_READ___S 25 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_TIMEOUT_FLUSH___M 0x01000000 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_TIMEOUT_FLUSH___S 24 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__REPORT_DA_SW_PEER_ID___M 0x00800000 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__REPORT_DA_SW_PEER_ID___S 23 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__PROTOCOL_FROM_AH_OR_L4___M 0x00400000 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__PROTOCOL_FROM_AH_OR_L4___S 22 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__PROTOCOL_FROM_AH_OR_ESP___M 0x00200000 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__PROTOCOL_FROM_AH_OR_ESP___S 21 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__UPDATE_DA_STATS___M 0x00100000 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__UPDATE_DA_STATS___S 20 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__MAC_ID___M 0x000C0000 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__MAC_ID___S 18 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__ASE_SA_SEARCH_SKIP___M 0x00020000 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__ASE_SA_SEARCH_SKIP___S 17 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__ASE_DA_SEARCH_SKIP___M 0x00010000 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__ASE_DA_SEARCH_SKIP___S 16 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__FLOW_SEARCH_SKIP___M 0x00008000 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__FLOW_SEARCH_SKIP___S 15 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__STOP_NEXT_PPDU_ENABLE___M 0x00004000 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__STOP_NEXT_PPDU_ENABLE___S 14 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__STOP_NEXT_PPDU___M 0x00002000 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__STOP_NEXT_PPDU___S 13 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__CCE_ENABLE___M 0x00001000 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__CCE_ENABLE___S 12 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__ALWAYS_FORCE_BYPASS___M 0x00000800 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__ALWAYS_FORCE_BYPASS___S 11 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__PACKET_OFFSET_RXDMA_SELECT___M 0x00000400 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__PACKET_OFFSET_RXDMA_SELECT___S 10 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_FORCE_BYPASS___M 0x00000200 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__ENABLE_FORCE_BYPASS___S 9 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__RX_HDR_BYTELEN___M 0x000001FF +#define WMAC0_RXOLE_RXOLE_R0_CONFIG__RX_HDR_BYTELEN___S 0 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_CONFIG___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_PACKET_OFFSET (0x00A95004) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_PACKET_OFFSET___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_PACKET_OFFSET___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_PACKET_OFFSET__NOBUF___POR 0x00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_PACKET_OFFSET__SW___POR 0x00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_PACKET_OFFSET__FW___POR 0x00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_PACKET_OFFSET__WBM___POR 0x00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_PACKET_OFFSET__NOBUF___M 0x00FC0000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_PACKET_OFFSET__NOBUF___S 18 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_PACKET_OFFSET__SW___M 0x0003F000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_PACKET_OFFSET__SW___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_PACKET_OFFSET__FW___M 0x00000FC0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_PACKET_OFFSET__FW___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_PACKET_OFFSET__WBM___M 0x0000003F +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_PACKET_OFFSET__WBM___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_PACKET_OFFSET___M 0x00FFFFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_PACKET_OFFSET___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_PACKET_OFFSET (0x00A95008) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_PACKET_OFFSET___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_PACKET_OFFSET___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_PACKET_OFFSET__NOBUF___POR 0x00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_PACKET_OFFSET__SW___POR 0x00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_PACKET_OFFSET__FW___POR 0x00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_PACKET_OFFSET__WBM___POR 0x00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_PACKET_OFFSET__NOBUF___M 0x00FC0000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_PACKET_OFFSET__NOBUF___S 18 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_PACKET_OFFSET__SW___M 0x0003F000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_PACKET_OFFSET__SW___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_PACKET_OFFSET__FW___M 0x00000FC0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_PACKET_OFFSET__FW___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_PACKET_OFFSET__WBM___M 0x0000003F +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_PACKET_OFFSET__WBM___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_PACKET_OFFSET___M 0x00FFFFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_PACKET_OFFSET___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT (0x00A9500C) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MO_NULL_DATA_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MD_NULL_DATA_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__FP_NULL_DATA_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MO_UCAST_DATA_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MD_UCAST_DATA_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__FP_UCAST_DATA_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MO_MCAST_DATA_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MD_MCAST_DATA_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__FP_MCAST_DATA_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MO_NULL_DATA_BUF_SOURCE___M 0x00030000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MO_NULL_DATA_BUF_SOURCE___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MD_NULL_DATA_BUF_SOURCE___M 0x0000C000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MD_NULL_DATA_BUF_SOURCE___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__FP_NULL_DATA_BUF_SOURCE___M 0x00003000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__FP_NULL_DATA_BUF_SOURCE___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MO_UCAST_DATA_BUF_SOURCE___M 0x00000C00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MO_UCAST_DATA_BUF_SOURCE___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MD_UCAST_DATA_BUF_SOURCE___M 0x00000300 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MD_UCAST_DATA_BUF_SOURCE___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__FP_UCAST_DATA_BUF_SOURCE___M 0x000000C0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__FP_UCAST_DATA_BUF_SOURCE___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MO_MCAST_DATA_BUF_SOURCE___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MO_MCAST_DATA_BUF_SOURCE___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MD_MCAST_DATA_BUF_SOURCE___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__MD_MCAST_DATA_BUF_SOURCE___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__FP_MCAST_DATA_BUF_SOURCE___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT__FP_MCAST_DATA_BUF_SOURCE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT___M 0x0003FFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_BUFFER_SOURCE_SELECT___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0 (0x00A95010) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0100_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0100_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0100_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0011_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0011_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0011_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0010_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0010_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0010_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0001_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0001_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0001_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0000_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0000_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0000_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0100_BUF_SOURCE___M 0x30000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0100_BUF_SOURCE___S 28 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0100_BUF_SOURCE___M 0x0C000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0100_BUF_SOURCE___S 26 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0100_BUF_SOURCE___M 0x03000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0100_BUF_SOURCE___S 24 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0011_BUF_SOURCE___M 0x00C00000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0011_BUF_SOURCE___S 22 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0011_BUF_SOURCE___M 0x00300000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0011_BUF_SOURCE___S 20 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0011_BUF_SOURCE___M 0x000C0000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0011_BUF_SOURCE___S 18 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0010_BUF_SOURCE___M 0x00030000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0010_BUF_SOURCE___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0010_BUF_SOURCE___M 0x0000C000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0010_BUF_SOURCE___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0010_BUF_SOURCE___M 0x00003000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0010_BUF_SOURCE___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0001_BUF_SOURCE___M 0x00000C00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0001_BUF_SOURCE___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0001_BUF_SOURCE___M 0x00000300 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0001_BUF_SOURCE___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0001_BUF_SOURCE___M 0x000000C0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0001_BUF_SOURCE___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0000_BUF_SOURCE___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0000_BUF_SOURCE___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0000_BUF_SOURCE___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0000_BUF_SOURCE___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0000_BUF_SOURCE___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0000_BUF_SOURCE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0___M 0x3FFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX0___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1 (0x00A95014) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_1001_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_1001_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_1001_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_1000_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_1000_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_1000_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0111_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0111_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0111_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0110_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0110_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0110_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0101_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0101_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0101_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_1001_BUF_SOURCE___M 0x30000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_1001_BUF_SOURCE___S 28 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_1001_BUF_SOURCE___M 0x0C000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_1001_BUF_SOURCE___S 26 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_1001_BUF_SOURCE___M 0x03000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_1001_BUF_SOURCE___S 24 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_1000_BUF_SOURCE___M 0x00C00000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_1000_BUF_SOURCE___S 22 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_1000_BUF_SOURCE___M 0x00300000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_1000_BUF_SOURCE___S 20 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_1000_BUF_SOURCE___M 0x000C0000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_1000_BUF_SOURCE___S 18 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0111_BUF_SOURCE___M 0x00030000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0111_BUF_SOURCE___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0111_BUF_SOURCE___M 0x0000C000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0111_BUF_SOURCE___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0111_BUF_SOURCE___M 0x00003000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0111_BUF_SOURCE___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0110_BUF_SOURCE___M 0x00000C00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0110_BUF_SOURCE___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0110_BUF_SOURCE___M 0x00000300 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0110_BUF_SOURCE___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0110_BUF_SOURCE___M 0x000000C0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0110_BUF_SOURCE___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0101_BUF_SOURCE___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0101_BUF_SOURCE___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0101_BUF_SOURCE___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0101_BUF_SOURCE___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0101_BUF_SOURCE___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0101_BUF_SOURCE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1___M 0x3FFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX1___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2 (0x00A95018) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1110_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1110_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1110_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1101_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1101_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1101_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1100_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1100_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1100_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1011_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1011_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1011_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1010_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1010_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1010_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1110_BUF_SOURCE___M 0x30000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1110_BUF_SOURCE___S 28 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1110_BUF_SOURCE___M 0x0C000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1110_BUF_SOURCE___S 26 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1110_BUF_SOURCE___M 0x03000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1110_BUF_SOURCE___S 24 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1101_BUF_SOURCE___M 0x00C00000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1101_BUF_SOURCE___S 22 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1101_BUF_SOURCE___M 0x00300000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1101_BUF_SOURCE___S 20 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1101_BUF_SOURCE___M 0x000C0000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1101_BUF_SOURCE___S 18 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1100_BUF_SOURCE___M 0x00030000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1100_BUF_SOURCE___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1100_BUF_SOURCE___M 0x0000C000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1100_BUF_SOURCE___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1100_BUF_SOURCE___M 0x00003000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1100_BUF_SOURCE___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1011_BUF_SOURCE___M 0x00000C00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1011_BUF_SOURCE___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1011_BUF_SOURCE___M 0x00000300 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1011_BUF_SOURCE___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1011_BUF_SOURCE___M 0x000000C0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1011_BUF_SOURCE___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1010_BUF_SOURCE___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1010_BUF_SOURCE___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1010_BUF_SOURCE___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1010_BUF_SOURCE___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1010_BUF_SOURCE___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1010_BUF_SOURCE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2___M 0x3FFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX2___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX3 (0x00A9501C) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX3___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX3___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX3__MO_MGMT_1111_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX3__MD_MGMT_1111_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX3__FP_MGMT_1111_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX3__MO_MGMT_1111_BUF_SOURCE___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX3__MO_MGMT_1111_BUF_SOURCE___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX3__MD_MGMT_1111_BUF_SOURCE___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX3__MD_MGMT_1111_BUF_SOURCE___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX3__FP_MGMT_1111_BUF_SOURCE___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX3__FP_MGMT_1111_BUF_SOURCE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX3___M 0x0000003F +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_BUFFER_SOURCE_SELECT_IX3___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0 (0x00A95020) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0100_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0100_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0100_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0011_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0011_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0011_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0010_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0010_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0010_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0001_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0001_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0001_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0000_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0000_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0000_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0100_BUF_SOURCE___M 0x30000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0100_BUF_SOURCE___S 28 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0100_BUF_SOURCE___M 0x0C000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0100_BUF_SOURCE___S 26 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0100_BUF_SOURCE___M 0x03000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0100_BUF_SOURCE___S 24 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0011_BUF_SOURCE___M 0x00C00000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0011_BUF_SOURCE___S 22 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0011_BUF_SOURCE___M 0x00300000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0011_BUF_SOURCE___S 20 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0011_BUF_SOURCE___M 0x000C0000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0011_BUF_SOURCE___S 18 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0010_BUF_SOURCE___M 0x00030000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0010_BUF_SOURCE___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0010_BUF_SOURCE___M 0x0000C000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0010_BUF_SOURCE___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0010_BUF_SOURCE___M 0x00003000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0010_BUF_SOURCE___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0001_BUF_SOURCE___M 0x00000C00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0001_BUF_SOURCE___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0001_BUF_SOURCE___M 0x00000300 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0001_BUF_SOURCE___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0001_BUF_SOURCE___M 0x000000C0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0001_BUF_SOURCE___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0000_BUF_SOURCE___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0000_BUF_SOURCE___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0000_BUF_SOURCE___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0000_BUF_SOURCE___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0000_BUF_SOURCE___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0000_BUF_SOURCE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0___M 0x3FFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX0___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1 (0x00A95024) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_1001_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_1001_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_1001_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_1000_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_1000_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_1000_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0111_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0111_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0111_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0110_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0110_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0110_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0101_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0101_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0101_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_1001_BUF_SOURCE___M 0x30000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_1001_BUF_SOURCE___S 28 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_1001_BUF_SOURCE___M 0x0C000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_1001_BUF_SOURCE___S 26 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_1001_BUF_SOURCE___M 0x03000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_1001_BUF_SOURCE___S 24 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_1000_BUF_SOURCE___M 0x00C00000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_1000_BUF_SOURCE___S 22 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_1000_BUF_SOURCE___M 0x00300000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_1000_BUF_SOURCE___S 20 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_1000_BUF_SOURCE___M 0x000C0000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_1000_BUF_SOURCE___S 18 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0111_BUF_SOURCE___M 0x00030000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0111_BUF_SOURCE___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0111_BUF_SOURCE___M 0x0000C000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0111_BUF_SOURCE___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0111_BUF_SOURCE___M 0x00003000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0111_BUF_SOURCE___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0110_BUF_SOURCE___M 0x00000C00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0110_BUF_SOURCE___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0110_BUF_SOURCE___M 0x00000300 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0110_BUF_SOURCE___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0110_BUF_SOURCE___M 0x000000C0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0110_BUF_SOURCE___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0101_BUF_SOURCE___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0101_BUF_SOURCE___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0101_BUF_SOURCE___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0101_BUF_SOURCE___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0101_BUF_SOURCE___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0101_BUF_SOURCE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1___M 0x3FFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX1___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2 (0x00A95028) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1110_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1110_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1110_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1101_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1101_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1101_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1100_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1100_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1100_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1011_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1011_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1011_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1010_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1010_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1010_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1110_BUF_SOURCE___M 0x30000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1110_BUF_SOURCE___S 28 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1110_BUF_SOURCE___M 0x0C000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1110_BUF_SOURCE___S 26 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1110_BUF_SOURCE___M 0x03000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1110_BUF_SOURCE___S 24 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1101_BUF_SOURCE___M 0x00C00000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1101_BUF_SOURCE___S 22 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1101_BUF_SOURCE___M 0x00300000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1101_BUF_SOURCE___S 20 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1101_BUF_SOURCE___M 0x000C0000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1101_BUF_SOURCE___S 18 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1100_BUF_SOURCE___M 0x00030000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1100_BUF_SOURCE___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1100_BUF_SOURCE___M 0x0000C000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1100_BUF_SOURCE___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1100_BUF_SOURCE___M 0x00003000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1100_BUF_SOURCE___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1011_BUF_SOURCE___M 0x00000C00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1011_BUF_SOURCE___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1011_BUF_SOURCE___M 0x00000300 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1011_BUF_SOURCE___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1011_BUF_SOURCE___M 0x000000C0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1011_BUF_SOURCE___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1010_BUF_SOURCE___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1010_BUF_SOURCE___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1010_BUF_SOURCE___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1010_BUF_SOURCE___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1010_BUF_SOURCE___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1010_BUF_SOURCE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2___M 0x3FFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX2___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX3 (0x00A9502C) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX3___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX3___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX3__MO_CTRL_1111_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX3__MD_CTRL_1111_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX3__FP_CTRL_1111_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX3__MO_CTRL_1111_BUF_SOURCE___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX3__MO_CTRL_1111_BUF_SOURCE___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX3__MD_CTRL_1111_BUF_SOURCE___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX3__MD_CTRL_1111_BUF_SOURCE___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX3__FP_CTRL_1111_BUF_SOURCE___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX3__FP_CTRL_1111_BUF_SOURCE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX3___M 0x0000003F +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_BUFFER_SOURCE_SELECT_IX3___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT (0x00A95030) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT___POR 0x00000FF1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__FP_UNSUPP_BUF_SOURCE___POR 0x3 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__MD_UNSUPP_BUF_SOURCE___POR 0x3 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__FP_PHY_ERR_BUF_SOURCE___POR 0x3 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__MO_UNSUPP_BUF_SOURCE___POR 0x3 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__MO_NDP_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__FP_NDP_BUF_SOURCE___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__FP_UNSUPP_BUF_SOURCE___M 0x00000C00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__FP_UNSUPP_BUF_SOURCE___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__MD_UNSUPP_BUF_SOURCE___M 0x00000300 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__MD_UNSUPP_BUF_SOURCE___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__FP_PHY_ERR_BUF_SOURCE___M 0x000000C0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__FP_PHY_ERR_BUF_SOURCE___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__MO_UNSUPP_BUF_SOURCE___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__MO_UNSUPP_BUF_SOURCE___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__MO_NDP_BUF_SOURCE___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__MO_NDP_BUF_SOURCE___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__FP_NDP_BUF_SOURCE___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT__FP_NDP_BUF_SOURCE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT___M 0x00000FFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_BUFFER_SOURCE_SELECT___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT (0x00A95034) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MO_NULL_DATA_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MD_NULL_DATA_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__FP_NULL_DATA_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MO_UCAST_DATA_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MD_UCAST_DATA_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__FP_UCAST_DATA_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MO_MCAST_DATA_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MD_MCAST_DATA_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__FP_MCAST_DATA_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MO_NULL_DATA_BUF_SOURCE___M 0x00030000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MO_NULL_DATA_BUF_SOURCE___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MD_NULL_DATA_BUF_SOURCE___M 0x0000C000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MD_NULL_DATA_BUF_SOURCE___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__FP_NULL_DATA_BUF_SOURCE___M 0x00003000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__FP_NULL_DATA_BUF_SOURCE___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MO_UCAST_DATA_BUF_SOURCE___M 0x00000C00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MO_UCAST_DATA_BUF_SOURCE___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MD_UCAST_DATA_BUF_SOURCE___M 0x00000300 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MD_UCAST_DATA_BUF_SOURCE___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__FP_UCAST_DATA_BUF_SOURCE___M 0x000000C0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__FP_UCAST_DATA_BUF_SOURCE___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MO_MCAST_DATA_BUF_SOURCE___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MO_MCAST_DATA_BUF_SOURCE___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MD_MCAST_DATA_BUF_SOURCE___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__MD_MCAST_DATA_BUF_SOURCE___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__FP_MCAST_DATA_BUF_SOURCE___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT__FP_MCAST_DATA_BUF_SOURCE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT___M 0x0003FFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_BUFFER_SOURCE_SELECT___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0 (0x00A95038) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0100_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0100_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0100_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0011_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0011_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0011_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0010_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0010_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0010_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0001_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0001_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0001_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0000_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0000_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0000_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0100_BUF_SOURCE___M 0x30000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0100_BUF_SOURCE___S 28 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0100_BUF_SOURCE___M 0x0C000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0100_BUF_SOURCE___S 26 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0100_BUF_SOURCE___M 0x03000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0100_BUF_SOURCE___S 24 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0011_BUF_SOURCE___M 0x00C00000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0011_BUF_SOURCE___S 22 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0011_BUF_SOURCE___M 0x00300000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0011_BUF_SOURCE___S 20 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0011_BUF_SOURCE___M 0x000C0000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0011_BUF_SOURCE___S 18 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0010_BUF_SOURCE___M 0x00030000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0010_BUF_SOURCE___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0010_BUF_SOURCE___M 0x0000C000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0010_BUF_SOURCE___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0010_BUF_SOURCE___M 0x00003000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0010_BUF_SOURCE___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0001_BUF_SOURCE___M 0x00000C00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0001_BUF_SOURCE___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0001_BUF_SOURCE___M 0x00000300 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0001_BUF_SOURCE___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0001_BUF_SOURCE___M 0x000000C0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0001_BUF_SOURCE___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0000_BUF_SOURCE___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MO_MGMT_0000_BUF_SOURCE___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0000_BUF_SOURCE___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__MD_MGMT_0000_BUF_SOURCE___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0000_BUF_SOURCE___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0__FP_MGMT_0000_BUF_SOURCE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0___M 0x3FFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX0___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1 (0x00A9503C) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_1001_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_1001_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_1001_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_1000_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_1000_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_1000_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0111_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0111_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0111_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0110_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0110_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0110_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0101_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0101_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0101_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_1001_BUF_SOURCE___M 0x30000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_1001_BUF_SOURCE___S 28 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_1001_BUF_SOURCE___M 0x0C000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_1001_BUF_SOURCE___S 26 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_1001_BUF_SOURCE___M 0x03000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_1001_BUF_SOURCE___S 24 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_1000_BUF_SOURCE___M 0x00C00000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_1000_BUF_SOURCE___S 22 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_1000_BUF_SOURCE___M 0x00300000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_1000_BUF_SOURCE___S 20 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_1000_BUF_SOURCE___M 0x000C0000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_1000_BUF_SOURCE___S 18 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0111_BUF_SOURCE___M 0x00030000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0111_BUF_SOURCE___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0111_BUF_SOURCE___M 0x0000C000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0111_BUF_SOURCE___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0111_BUF_SOURCE___M 0x00003000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0111_BUF_SOURCE___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0110_BUF_SOURCE___M 0x00000C00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0110_BUF_SOURCE___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0110_BUF_SOURCE___M 0x00000300 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0110_BUF_SOURCE___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0110_BUF_SOURCE___M 0x000000C0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0110_BUF_SOURCE___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0101_BUF_SOURCE___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MO_MGMT_0101_BUF_SOURCE___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0101_BUF_SOURCE___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__MD_MGMT_0101_BUF_SOURCE___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0101_BUF_SOURCE___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1__FP_MGMT_0101_BUF_SOURCE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1___M 0x3FFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX1___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2 (0x00A95040) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1110_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1110_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1110_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1101_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1101_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1101_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1100_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1100_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1100_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1011_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1011_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1011_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1010_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1010_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1010_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1110_BUF_SOURCE___M 0x30000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1110_BUF_SOURCE___S 28 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1110_BUF_SOURCE___M 0x0C000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1110_BUF_SOURCE___S 26 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1110_BUF_SOURCE___M 0x03000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1110_BUF_SOURCE___S 24 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1101_BUF_SOURCE___M 0x00C00000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1101_BUF_SOURCE___S 22 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1101_BUF_SOURCE___M 0x00300000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1101_BUF_SOURCE___S 20 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1101_BUF_SOURCE___M 0x000C0000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1101_BUF_SOURCE___S 18 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1100_BUF_SOURCE___M 0x00030000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1100_BUF_SOURCE___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1100_BUF_SOURCE___M 0x0000C000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1100_BUF_SOURCE___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1100_BUF_SOURCE___M 0x00003000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1100_BUF_SOURCE___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1011_BUF_SOURCE___M 0x00000C00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1011_BUF_SOURCE___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1011_BUF_SOURCE___M 0x00000300 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1011_BUF_SOURCE___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1011_BUF_SOURCE___M 0x000000C0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1011_BUF_SOURCE___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1010_BUF_SOURCE___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MO_MGMT_1010_BUF_SOURCE___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1010_BUF_SOURCE___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__MD_MGMT_1010_BUF_SOURCE___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1010_BUF_SOURCE___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2__FP_MGMT_1010_BUF_SOURCE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2___M 0x3FFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX2___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX3 (0x00A95044) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX3___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX3___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX3__MO_MGMT_1111_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX3__MD_MGMT_1111_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX3__FP_MGMT_1111_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX3__MO_MGMT_1111_BUF_SOURCE___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX3__MO_MGMT_1111_BUF_SOURCE___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX3__MD_MGMT_1111_BUF_SOURCE___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX3__MD_MGMT_1111_BUF_SOURCE___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX3__FP_MGMT_1111_BUF_SOURCE___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX3__FP_MGMT_1111_BUF_SOURCE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX3___M 0x0000003F +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_BUFFER_SOURCE_SELECT_IX3___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0 (0x00A95048) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0100_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0100_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0100_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0011_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0011_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0011_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0010_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0010_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0010_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0001_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0001_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0001_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0000_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0000_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0000_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0100_BUF_SOURCE___M 0x30000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0100_BUF_SOURCE___S 28 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0100_BUF_SOURCE___M 0x0C000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0100_BUF_SOURCE___S 26 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0100_BUF_SOURCE___M 0x03000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0100_BUF_SOURCE___S 24 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0011_BUF_SOURCE___M 0x00C00000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0011_BUF_SOURCE___S 22 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0011_BUF_SOURCE___M 0x00300000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0011_BUF_SOURCE___S 20 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0011_BUF_SOURCE___M 0x000C0000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0011_BUF_SOURCE___S 18 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0010_BUF_SOURCE___M 0x00030000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0010_BUF_SOURCE___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0010_BUF_SOURCE___M 0x0000C000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0010_BUF_SOURCE___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0010_BUF_SOURCE___M 0x00003000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0010_BUF_SOURCE___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0001_BUF_SOURCE___M 0x00000C00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0001_BUF_SOURCE___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0001_BUF_SOURCE___M 0x00000300 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0001_BUF_SOURCE___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0001_BUF_SOURCE___M 0x000000C0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0001_BUF_SOURCE___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0000_BUF_SOURCE___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MO_CTRL_0000_BUF_SOURCE___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0000_BUF_SOURCE___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__MD_CTRL_0000_BUF_SOURCE___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0000_BUF_SOURCE___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0__FP_CTRL_0000_BUF_SOURCE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0___M 0x3FFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX0___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1 (0x00A9504C) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_1001_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_1001_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_1001_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_1000_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_1000_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_1000_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0111_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0111_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0111_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0110_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0110_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0110_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0101_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0101_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0101_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_1001_BUF_SOURCE___M 0x30000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_1001_BUF_SOURCE___S 28 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_1001_BUF_SOURCE___M 0x0C000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_1001_BUF_SOURCE___S 26 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_1001_BUF_SOURCE___M 0x03000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_1001_BUF_SOURCE___S 24 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_1000_BUF_SOURCE___M 0x00C00000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_1000_BUF_SOURCE___S 22 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_1000_BUF_SOURCE___M 0x00300000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_1000_BUF_SOURCE___S 20 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_1000_BUF_SOURCE___M 0x000C0000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_1000_BUF_SOURCE___S 18 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0111_BUF_SOURCE___M 0x00030000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0111_BUF_SOURCE___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0111_BUF_SOURCE___M 0x0000C000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0111_BUF_SOURCE___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0111_BUF_SOURCE___M 0x00003000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0111_BUF_SOURCE___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0110_BUF_SOURCE___M 0x00000C00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0110_BUF_SOURCE___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0110_BUF_SOURCE___M 0x00000300 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0110_BUF_SOURCE___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0110_BUF_SOURCE___M 0x000000C0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0110_BUF_SOURCE___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0101_BUF_SOURCE___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MO_CTRL_0101_BUF_SOURCE___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0101_BUF_SOURCE___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__MD_CTRL_0101_BUF_SOURCE___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0101_BUF_SOURCE___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1__FP_CTRL_0101_BUF_SOURCE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1___M 0x3FFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX1___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2 (0x00A95050) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1110_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1110_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1110_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1101_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1101_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1101_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1100_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1100_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1100_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1011_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1011_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1011_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1010_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1010_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1010_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1110_BUF_SOURCE___M 0x30000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1110_BUF_SOURCE___S 28 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1110_BUF_SOURCE___M 0x0C000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1110_BUF_SOURCE___S 26 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1110_BUF_SOURCE___M 0x03000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1110_BUF_SOURCE___S 24 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1101_BUF_SOURCE___M 0x00C00000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1101_BUF_SOURCE___S 22 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1101_BUF_SOURCE___M 0x00300000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1101_BUF_SOURCE___S 20 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1101_BUF_SOURCE___M 0x000C0000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1101_BUF_SOURCE___S 18 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1100_BUF_SOURCE___M 0x00030000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1100_BUF_SOURCE___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1100_BUF_SOURCE___M 0x0000C000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1100_BUF_SOURCE___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1100_BUF_SOURCE___M 0x00003000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1100_BUF_SOURCE___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1011_BUF_SOURCE___M 0x00000C00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1011_BUF_SOURCE___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1011_BUF_SOURCE___M 0x00000300 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1011_BUF_SOURCE___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1011_BUF_SOURCE___M 0x000000C0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1011_BUF_SOURCE___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1010_BUF_SOURCE___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MO_CTRL_1010_BUF_SOURCE___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1010_BUF_SOURCE___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__MD_CTRL_1010_BUF_SOURCE___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1010_BUF_SOURCE___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2__FP_CTRL_1010_BUF_SOURCE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2___M 0x3FFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX2___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX3 (0x00A95054) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX3___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX3___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX3__MO_CTRL_1111_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX3__MD_CTRL_1111_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX3__FP_CTRL_1111_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX3__MO_CTRL_1111_BUF_SOURCE___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX3__MO_CTRL_1111_BUF_SOURCE___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX3__MD_CTRL_1111_BUF_SOURCE___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX3__MD_CTRL_1111_BUF_SOURCE___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX3__FP_CTRL_1111_BUF_SOURCE___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX3__FP_CTRL_1111_BUF_SOURCE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX3___M 0x0000003F +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_BUFFER_SOURCE_SELECT_IX3___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT (0x00A95058) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT___POR 0x00000FF1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__FP_UNSUPP_BUF_SOURCE___POR 0x3 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__MD_UNSUPP_BUF_SOURCE___POR 0x3 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__FP_PHY_ERR_BUF_SOURCE___POR 0x3 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__MO_UNSUPP_BUF_SOURCE___POR 0x3 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__MO_NDP_BUF_SOURCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__FP_NDP_BUF_SOURCE___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__FP_UNSUPP_BUF_SOURCE___M 0x00000C00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__FP_UNSUPP_BUF_SOURCE___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__MD_UNSUPP_BUF_SOURCE___M 0x00000300 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__MD_UNSUPP_BUF_SOURCE___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__FP_PHY_ERR_BUF_SOURCE___M 0x000000C0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__FP_PHY_ERR_BUF_SOURCE___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__MO_UNSUPP_BUF_SOURCE___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__MO_UNSUPP_BUF_SOURCE___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__MO_NDP_BUF_SOURCE___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__MO_NDP_BUF_SOURCE___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__FP_NDP_BUF_SOURCE___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT__FP_NDP_BUF_SOURCE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT___M 0x00000FFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_BUFFER_SOURCE_SELECT___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL (0x00A9505C) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL___POR 0x000001FF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___M 0x00000100 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___M 0x00000080 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___S 7 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___M 0x00000040 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___M 0x00000020 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___S 5 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___M 0x00000010 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___M 0x00000008 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___S 3 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___S 1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL___M 0x000001FF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL (0x00A95060) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL___POR 0x000001FF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___M 0x00000100 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___M 0x00000080 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___S 7 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___M 0x00000040 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___M 0x00000020 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___S 5 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___M 0x00000010 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___M 0x00000008 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___S 3 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___S 1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL___M 0x000001FF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL (0x00A95064) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL___POR 0x000001FF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___M 0x00000100 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___M 0x00000080 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___S 7 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___M 0x00000040 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___M 0x00000020 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___S 5 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___M 0x00000010 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___M 0x00000008 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___S 3 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___S 1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL___M 0x000001FF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL (0x00A95068) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL___POR 0x000001FF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___M 0x00000100 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___M 0x00000080 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___S 7 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___M 0x00000040 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___M 0x00000020 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___S 5 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___M 0x00000010 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___M 0x00000008 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___S 3 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___S 1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL___M 0x000001FF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_WBM_BUF_SOURCE_TLV_FILTER_IN_CONTROL___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL (0x00A9506C) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL___POR 0x000001FF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___M 0x00000100 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___M 0x00000080 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___S 7 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___M 0x00000040 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___M 0x00000020 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___S 5 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___M 0x00000010 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___M 0x00000008 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___S 3 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___S 1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL___M 0x000001FF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_SW_BUF_SOURCE_TLV_FILTER_IN_CONTROL___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL (0x00A95070) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL___POR 0x000001FF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___M 0x00000100 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_FRAMELESS_BAR___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___M 0x00000080 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_ATTENTION___S 7 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___M 0x00000040 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__RX_HEADER_PER_MSDU___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___M 0x00000020 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_HEADER___S 5 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___M 0x00000010 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_END___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___M 0x00000008 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_END___S 3 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PACKET___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MSDU_START___S 1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_MPDU_START___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL___M 0x000001FF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_FW_BUF_SOURCE_TLV_FILTER_IN_CONTROL___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL (0x00A95074) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_NULL_DATA_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_NULL_DATA_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_NULL_DATA_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_UCAST_DATA_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_UCAST_DATA_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_UCAST_DATA_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_MCAST_DATA_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_MCAST_DATA_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_MCAST_DATA_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_NULL_DATA_STATUS_FILTER___M 0x00000100 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_NULL_DATA_STATUS_FILTER___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_NULL_DATA_STATUS_FILTER___M 0x00000080 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_NULL_DATA_STATUS_FILTER___S 7 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_NULL_DATA_STATUS_FILTER___M 0x00000040 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_NULL_DATA_STATUS_FILTER___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_UCAST_DATA_STATUS_FILTER___M 0x00000020 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_UCAST_DATA_STATUS_FILTER___S 5 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_UCAST_DATA_STATUS_FILTER___M 0x00000010 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_UCAST_DATA_STATUS_FILTER___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_UCAST_DATA_STATUS_FILTER___M 0x00000008 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_UCAST_DATA_STATUS_FILTER___S 3 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_MCAST_DATA_STATUS_FILTER___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_MCAST_DATA_STATUS_FILTER___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_MCAST_DATA_STATUS_FILTER___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_MCAST_DATA_STATUS_FILTER___S 1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_MCAST_DATA_STATUS_FILTER___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_MCAST_DATA_STATUS_FILTER___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL___M 0x000001FF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_DATA_FILTER_IN_CONTROL___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0 (0x00A95078) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_1001_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_1001_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_1001_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_1000_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_1000_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_1000_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0111_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0111_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0111_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0110_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0110_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0110_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0101_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0101_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0101_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0100_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0100_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0100_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0011_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0011_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0011_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0010_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0010_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0010_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0001_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0001_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0001_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0000_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0000_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0000_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_1001_STATUS_FILTER___M 0x20000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_1001_STATUS_FILTER___S 29 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_1001_STATUS_FILTER___M 0x10000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_1001_STATUS_FILTER___S 28 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_1001_STATUS_FILTER___M 0x08000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_1001_STATUS_FILTER___S 27 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_1000_STATUS_FILTER___M 0x04000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_1000_STATUS_FILTER___S 26 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_1000_STATUS_FILTER___M 0x02000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_1000_STATUS_FILTER___S 25 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_1000_STATUS_FILTER___M 0x01000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_1000_STATUS_FILTER___S 24 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0111_STATUS_FILTER___M 0x00800000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0111_STATUS_FILTER___S 23 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0111_STATUS_FILTER___M 0x00400000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0111_STATUS_FILTER___S 22 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0111_STATUS_FILTER___M 0x00200000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0111_STATUS_FILTER___S 21 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0110_STATUS_FILTER___M 0x00100000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0110_STATUS_FILTER___S 20 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0110_STATUS_FILTER___M 0x00080000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0110_STATUS_FILTER___S 19 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0110_STATUS_FILTER___M 0x00040000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0110_STATUS_FILTER___S 18 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0101_STATUS_FILTER___M 0x00020000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0101_STATUS_FILTER___S 17 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0101_STATUS_FILTER___M 0x00010000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0101_STATUS_FILTER___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0101_STATUS_FILTER___M 0x00008000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0101_STATUS_FILTER___S 15 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0100_STATUS_FILTER___M 0x00004000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0100_STATUS_FILTER___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0100_STATUS_FILTER___M 0x00002000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0100_STATUS_FILTER___S 13 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0100_STATUS_FILTER___M 0x00001000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0100_STATUS_FILTER___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0011_STATUS_FILTER___M 0x00000800 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0011_STATUS_FILTER___S 11 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0011_STATUS_FILTER___M 0x00000400 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0011_STATUS_FILTER___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0011_STATUS_FILTER___M 0x00000200 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0011_STATUS_FILTER___S 9 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0010_STATUS_FILTER___M 0x00000100 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0010_STATUS_FILTER___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0010_STATUS_FILTER___M 0x00000080 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0010_STATUS_FILTER___S 7 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0010_STATUS_FILTER___M 0x00000040 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0010_STATUS_FILTER___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0001_STATUS_FILTER___M 0x00000020 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0001_STATUS_FILTER___S 5 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0001_STATUS_FILTER___M 0x00000010 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0001_STATUS_FILTER___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0001_STATUS_FILTER___M 0x00000008 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0001_STATUS_FILTER___S 3 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0000_STATUS_FILTER___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0000_STATUS_FILTER___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0000_STATUS_FILTER___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0000_STATUS_FILTER___S 1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0000_STATUS_FILTER___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0000_STATUS_FILTER___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0___M 0x3FFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1 (0x00A9507C) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1111_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1111_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1111_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1110_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1110_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1110_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1101_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1101_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1101_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1100_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1100_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1100_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1011_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1011_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1011_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1010_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1010_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1010_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1111_STATUS_FILTER___M 0x00020000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1111_STATUS_FILTER___S 17 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1111_STATUS_FILTER___M 0x00010000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1111_STATUS_FILTER___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1111_STATUS_FILTER___M 0x00008000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1111_STATUS_FILTER___S 15 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1110_STATUS_FILTER___M 0x00004000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1110_STATUS_FILTER___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1110_STATUS_FILTER___M 0x00002000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1110_STATUS_FILTER___S 13 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1110_STATUS_FILTER___M 0x00001000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1110_STATUS_FILTER___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1101_STATUS_FILTER___M 0x00000800 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1101_STATUS_FILTER___S 11 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1101_STATUS_FILTER___M 0x00000400 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1101_STATUS_FILTER___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1101_STATUS_FILTER___M 0x00000200 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1101_STATUS_FILTER___S 9 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1100_STATUS_FILTER___M 0x00000100 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1100_STATUS_FILTER___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1100_STATUS_FILTER___M 0x00000080 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1100_STATUS_FILTER___S 7 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1100_STATUS_FILTER___M 0x00000040 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1100_STATUS_FILTER___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1011_STATUS_FILTER___M 0x00000020 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1011_STATUS_FILTER___S 5 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1011_STATUS_FILTER___M 0x00000010 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1011_STATUS_FILTER___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1011_STATUS_FILTER___M 0x00000008 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1011_STATUS_FILTER___S 3 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1010_STATUS_FILTER___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1010_STATUS_FILTER___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1010_STATUS_FILTER___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1010_STATUS_FILTER___S 1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1010_STATUS_FILTER___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1010_STATUS_FILTER___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1___M 0x0003FFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0 (0x00A95080) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_1001_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_1001_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_1001_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_1000_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_1000_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_1000_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0111_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0111_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0111_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0110_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0110_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0110_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0101_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0101_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0101_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0100_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0100_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0100_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0011_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0011_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0011_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0010_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0010_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0010_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0001_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0001_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0001_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0000_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0000_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0000_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_1001_STATUS_FILTER___M 0x20000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_1001_STATUS_FILTER___S 29 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_1001_STATUS_FILTER___M 0x10000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_1001_STATUS_FILTER___S 28 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_1001_STATUS_FILTER___M 0x08000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_1001_STATUS_FILTER___S 27 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_1000_STATUS_FILTER___M 0x04000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_1000_STATUS_FILTER___S 26 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_1000_STATUS_FILTER___M 0x02000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_1000_STATUS_FILTER___S 25 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_1000_STATUS_FILTER___M 0x01000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_1000_STATUS_FILTER___S 24 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0111_STATUS_FILTER___M 0x00800000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0111_STATUS_FILTER___S 23 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0111_STATUS_FILTER___M 0x00400000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0111_STATUS_FILTER___S 22 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0111_STATUS_FILTER___M 0x00200000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0111_STATUS_FILTER___S 21 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0110_STATUS_FILTER___M 0x00100000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0110_STATUS_FILTER___S 20 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0110_STATUS_FILTER___M 0x00080000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0110_STATUS_FILTER___S 19 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0110_STATUS_FILTER___M 0x00040000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0110_STATUS_FILTER___S 18 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0101_STATUS_FILTER___M 0x00020000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0101_STATUS_FILTER___S 17 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0101_STATUS_FILTER___M 0x00010000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0101_STATUS_FILTER___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0101_STATUS_FILTER___M 0x00008000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0101_STATUS_FILTER___S 15 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0100_STATUS_FILTER___M 0x00004000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0100_STATUS_FILTER___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0100_STATUS_FILTER___M 0x00002000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0100_STATUS_FILTER___S 13 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0100_STATUS_FILTER___M 0x00001000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0100_STATUS_FILTER___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0011_STATUS_FILTER___M 0x00000800 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0011_STATUS_FILTER___S 11 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0011_STATUS_FILTER___M 0x00000400 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0011_STATUS_FILTER___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0011_STATUS_FILTER___M 0x00000200 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0011_STATUS_FILTER___S 9 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0010_STATUS_FILTER___M 0x00000100 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0010_STATUS_FILTER___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0010_STATUS_FILTER___M 0x00000080 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0010_STATUS_FILTER___S 7 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0010_STATUS_FILTER___M 0x00000040 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0010_STATUS_FILTER___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0001_STATUS_FILTER___M 0x00000020 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0001_STATUS_FILTER___S 5 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0001_STATUS_FILTER___M 0x00000010 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0001_STATUS_FILTER___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0001_STATUS_FILTER___M 0x00000008 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0001_STATUS_FILTER___S 3 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0000_STATUS_FILTER___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0000_STATUS_FILTER___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0000_STATUS_FILTER___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0000_STATUS_FILTER___S 1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0000_STATUS_FILTER___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0000_STATUS_FILTER___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0___M 0x3FFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1 (0x00A95084) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1111_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1111_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1111_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1110_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1110_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1110_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1101_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1101_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1101_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1100_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1100_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1100_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1011_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1011_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1011_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1010_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1010_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1010_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1111_STATUS_FILTER___M 0x00020000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1111_STATUS_FILTER___S 17 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1111_STATUS_FILTER___M 0x00010000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1111_STATUS_FILTER___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1111_STATUS_FILTER___M 0x00008000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1111_STATUS_FILTER___S 15 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1110_STATUS_FILTER___M 0x00004000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1110_STATUS_FILTER___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1110_STATUS_FILTER___M 0x00002000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1110_STATUS_FILTER___S 13 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1110_STATUS_FILTER___M 0x00001000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1110_STATUS_FILTER___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1101_STATUS_FILTER___M 0x00000800 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1101_STATUS_FILTER___S 11 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1101_STATUS_FILTER___M 0x00000400 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1101_STATUS_FILTER___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1101_STATUS_FILTER___M 0x00000200 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1101_STATUS_FILTER___S 9 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1100_STATUS_FILTER___M 0x00000100 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1100_STATUS_FILTER___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1100_STATUS_FILTER___M 0x00000080 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1100_STATUS_FILTER___S 7 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1100_STATUS_FILTER___M 0x00000040 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1100_STATUS_FILTER___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1011_STATUS_FILTER___M 0x00000020 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1011_STATUS_FILTER___S 5 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1011_STATUS_FILTER___M 0x00000010 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1011_STATUS_FILTER___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1011_STATUS_FILTER___M 0x00000008 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1011_STATUS_FILTER___S 3 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1010_STATUS_FILTER___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1010_STATUS_FILTER___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1010_STATUS_FILTER___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1010_STATUS_FILTER___S 1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1010_STATUS_FILTER___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1010_STATUS_FILTER___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1___M 0x0003FFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL (0x00A95088) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL___POR 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_UNSUPP_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__MD_UNSUPP_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_PHY_ERR_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__MO_UNSUPP_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__MO_NDP_STATUS_FILTER___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_NDP_STATUS_FILTER___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_UNSUPP_STATUS_FILTER___M 0x00000020 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_UNSUPP_STATUS_FILTER___S 5 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__MD_UNSUPP_STATUS_FILTER___M 0x00000010 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__MD_UNSUPP_STATUS_FILTER___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_PHY_ERR_STATUS_FILTER___M 0x00000008 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_PHY_ERR_STATUS_FILTER___S 3 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__MO_UNSUPP_STATUS_FILTER___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__MO_UNSUPP_STATUS_FILTER___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__MO_NDP_STATUS_FILTER___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__MO_NDP_STATUS_FILTER___S 1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_NDP_STATUS_FILTER___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_NDP_STATUS_FILTER___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL___M 0x0000003F +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MISC_FILTER_IN_CONTROL___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL (0x00A9508C) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL___POR 0x7ECFD9FB +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_FRAMELESS_BAR___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_ATTENTION___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_RX_HEADER_PER_MSDU___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_HEADER___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MPDU_END___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MSDU_END___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PACKET___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MSDU_START___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MPDU_START___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_FRAMELESS_BAR___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_ATTENTION___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_RX_HEADER_PER_MSDU___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_HEADER___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MPDU_END___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MSDU_END___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PACKET___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MSDU_START___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MPDU_START___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_FRAMELESS_BAR___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_ATTENTION___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_RX_HEADER_PER_MSDU___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_HEADER___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MPDU_END___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MSDU_END___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PACKET___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MSDU_START___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MPDU_START___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_FRAMELESS_BAR___M 0x40000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_FRAMELESS_BAR___S 30 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_ATTENTION___M 0x20000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_ATTENTION___S 29 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_RX_HEADER_PER_MSDU___M 0x10000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_RX_HEADER_PER_MSDU___S 28 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_HEADER___M 0x08000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_HEADER___S 27 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MPDU_END___M 0x04000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MPDU_END___S 26 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MSDU_END___M 0x02000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MSDU_END___S 25 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PACKET___M 0x01000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PACKET___S 24 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MSDU_START___M 0x00800000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MSDU_START___S 23 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MPDU_START___M 0x00400000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MPDU_START___S 22 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_FRAMELESS_BAR___M 0x00080000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_FRAMELESS_BAR___S 19 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_ATTENTION___M 0x00040000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_ATTENTION___S 18 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_RX_HEADER_PER_MSDU___M 0x00020000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_RX_HEADER_PER_MSDU___S 17 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_HEADER___M 0x00010000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_HEADER___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MPDU_END___M 0x00008000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MPDU_END___S 15 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MSDU_END___M 0x00004000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MSDU_END___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PACKET___M 0x00002000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PACKET___S 13 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MSDU_START___M 0x00001000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MSDU_START___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MPDU_START___M 0x00000800 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MPDU_START___S 11 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_FRAMELESS_BAR___M 0x00000100 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_FRAMELESS_BAR___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_ATTENTION___M 0x00000080 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_ATTENTION___S 7 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_RX_HEADER_PER_MSDU___M 0x00000040 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_RX_HEADER_PER_MSDU___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_HEADER___M 0x00000020 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_HEADER___S 5 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MPDU_END___M 0x00000010 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MPDU_END___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MSDU_END___M 0x00000008 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MSDU_END___S 3 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PACKET___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PACKET___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MSDU_START___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MSDU_START___S 1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MPDU_START___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MPDU_START___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL___M 0x7FCFF9FF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL (0x00A95090) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL___POR 0x00AAAAAB +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PPDU_START_USER_INFO___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_STATUS_DONE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_STATUS_DONE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_STATUS_DONE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_USER_STATS___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_USER_STATS___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_USER_STATS___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PPDU_START___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PPDU_START_USER_INFO___M 0x02000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PPDU_START_USER_INFO___S 25 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_STATUS_DONE___M 0x01000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_STATUS_DONE___S 24 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___M 0x00800000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___S 23 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_STATUS_DONE___M 0x00400000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_STATUS_DONE___S 22 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___M 0x00200000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___S 21 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_STATUS_DONE___M 0x00100000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_STATUS_DONE___S 20 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___M 0x00080000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___S 19 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___M 0x00040000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___S 18 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___M 0x00020000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___S 17 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___M 0x00010000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___M 0x00008000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___S 15 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___M 0x00004000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___M 0x00002000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___S 13 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_USER_STATS___M 0x00001000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_USER_STATS___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___M 0x00000800 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___S 11 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_USER_STATS___M 0x00000400 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_USER_STATS___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___M 0x00000200 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___S 9 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_USER_STATS___M 0x00000100 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_USER_STATS___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___M 0x00000080 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___S 7 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END___M 0x00000040 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END___M 0x00000020 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END___S 5 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END___M 0x00000010 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END___M 0x00000008 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END___S 3 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END___S 1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PPDU_START___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PPDU_START___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL___M 0x03FFFFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL (0x00A95094) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_NULL_DATA_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_NULL_DATA_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_NULL_DATA_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_UCAST_DATA_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_UCAST_DATA_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_UCAST_DATA_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_MCAST_DATA_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_MCAST_DATA_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_MCAST_DATA_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_NULL_DATA_STATUS_FILTER___M 0x00000100 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_NULL_DATA_STATUS_FILTER___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_NULL_DATA_STATUS_FILTER___M 0x00000080 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_NULL_DATA_STATUS_FILTER___S 7 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_NULL_DATA_STATUS_FILTER___M 0x00000040 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_NULL_DATA_STATUS_FILTER___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_UCAST_DATA_STATUS_FILTER___M 0x00000020 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_UCAST_DATA_STATUS_FILTER___S 5 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_UCAST_DATA_STATUS_FILTER___M 0x00000010 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_UCAST_DATA_STATUS_FILTER___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_UCAST_DATA_STATUS_FILTER___M 0x00000008 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_UCAST_DATA_STATUS_FILTER___S 3 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_MCAST_DATA_STATUS_FILTER___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MO_MCAST_DATA_STATUS_FILTER___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_MCAST_DATA_STATUS_FILTER___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__MD_MCAST_DATA_STATUS_FILTER___S 1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_MCAST_DATA_STATUS_FILTER___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL__FP_MCAST_DATA_STATUS_FILTER___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL___M 0x000001FF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_DATA_FILTER_IN_CONTROL___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0 (0x00A95098) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_1001_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_1001_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_1001_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_1000_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_1000_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_1000_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0111_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0111_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0111_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0110_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0110_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0110_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0101_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0101_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0101_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0100_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0100_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0100_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0011_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0011_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0011_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0010_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0010_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0010_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0001_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0001_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0001_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0000_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0000_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0000_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_1001_STATUS_FILTER___M 0x20000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_1001_STATUS_FILTER___S 29 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_1001_STATUS_FILTER___M 0x10000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_1001_STATUS_FILTER___S 28 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_1001_STATUS_FILTER___M 0x08000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_1001_STATUS_FILTER___S 27 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_1000_STATUS_FILTER___M 0x04000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_1000_STATUS_FILTER___S 26 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_1000_STATUS_FILTER___M 0x02000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_1000_STATUS_FILTER___S 25 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_1000_STATUS_FILTER___M 0x01000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_1000_STATUS_FILTER___S 24 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0111_STATUS_FILTER___M 0x00800000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0111_STATUS_FILTER___S 23 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0111_STATUS_FILTER___M 0x00400000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0111_STATUS_FILTER___S 22 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0111_STATUS_FILTER___M 0x00200000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0111_STATUS_FILTER___S 21 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0110_STATUS_FILTER___M 0x00100000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0110_STATUS_FILTER___S 20 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0110_STATUS_FILTER___M 0x00080000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0110_STATUS_FILTER___S 19 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0110_STATUS_FILTER___M 0x00040000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0110_STATUS_FILTER___S 18 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0101_STATUS_FILTER___M 0x00020000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0101_STATUS_FILTER___S 17 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0101_STATUS_FILTER___M 0x00010000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0101_STATUS_FILTER___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0101_STATUS_FILTER___M 0x00008000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0101_STATUS_FILTER___S 15 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0100_STATUS_FILTER___M 0x00004000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0100_STATUS_FILTER___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0100_STATUS_FILTER___M 0x00002000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0100_STATUS_FILTER___S 13 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0100_STATUS_FILTER___M 0x00001000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0100_STATUS_FILTER___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0011_STATUS_FILTER___M 0x00000800 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0011_STATUS_FILTER___S 11 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0011_STATUS_FILTER___M 0x00000400 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0011_STATUS_FILTER___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0011_STATUS_FILTER___M 0x00000200 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0011_STATUS_FILTER___S 9 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0010_STATUS_FILTER___M 0x00000100 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0010_STATUS_FILTER___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0010_STATUS_FILTER___M 0x00000080 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0010_STATUS_FILTER___S 7 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0010_STATUS_FILTER___M 0x00000040 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0010_STATUS_FILTER___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0001_STATUS_FILTER___M 0x00000020 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0001_STATUS_FILTER___S 5 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0001_STATUS_FILTER___M 0x00000010 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0001_STATUS_FILTER___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0001_STATUS_FILTER___M 0x00000008 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0001_STATUS_FILTER___S 3 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0000_STATUS_FILTER___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MO_MGMT_0000_STATUS_FILTER___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0000_STATUS_FILTER___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__MD_MGMT_0000_STATUS_FILTER___S 1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0000_STATUS_FILTER___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0__FP_MGMT_0000_STATUS_FILTER___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0___M 0x3FFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX0___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1 (0x00A9509C) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1111_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1111_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1111_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1110_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1110_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1110_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1101_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1101_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1101_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1100_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1100_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1100_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1011_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1011_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1011_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1010_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1010_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1010_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1111_STATUS_FILTER___M 0x00020000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1111_STATUS_FILTER___S 17 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1111_STATUS_FILTER___M 0x00010000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1111_STATUS_FILTER___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1111_STATUS_FILTER___M 0x00008000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1111_STATUS_FILTER___S 15 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1110_STATUS_FILTER___M 0x00004000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1110_STATUS_FILTER___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1110_STATUS_FILTER___M 0x00002000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1110_STATUS_FILTER___S 13 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1110_STATUS_FILTER___M 0x00001000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1110_STATUS_FILTER___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1101_STATUS_FILTER___M 0x00000800 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1101_STATUS_FILTER___S 11 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1101_STATUS_FILTER___M 0x00000400 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1101_STATUS_FILTER___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1101_STATUS_FILTER___M 0x00000200 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1101_STATUS_FILTER___S 9 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1100_STATUS_FILTER___M 0x00000100 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1100_STATUS_FILTER___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1100_STATUS_FILTER___M 0x00000080 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1100_STATUS_FILTER___S 7 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1100_STATUS_FILTER___M 0x00000040 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1100_STATUS_FILTER___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1011_STATUS_FILTER___M 0x00000020 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1011_STATUS_FILTER___S 5 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1011_STATUS_FILTER___M 0x00000010 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1011_STATUS_FILTER___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1011_STATUS_FILTER___M 0x00000008 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1011_STATUS_FILTER___S 3 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1010_STATUS_FILTER___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MO_MGMT_1010_STATUS_FILTER___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1010_STATUS_FILTER___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__MD_MGMT_1010_STATUS_FILTER___S 1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1010_STATUS_FILTER___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1__FP_MGMT_1010_STATUS_FILTER___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1___M 0x0003FFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MGMT_FILTER_IN_CONTROL_IX1___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0 (0x00A950A0) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_1001_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_1001_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_1001_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_1000_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_1000_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_1000_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0111_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0111_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0111_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0110_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0110_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0110_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0101_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0101_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0101_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0100_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0100_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0100_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0011_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0011_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0011_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0010_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0010_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0010_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0001_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0001_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0001_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0000_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0000_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0000_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_1001_STATUS_FILTER___M 0x20000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_1001_STATUS_FILTER___S 29 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_1001_STATUS_FILTER___M 0x10000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_1001_STATUS_FILTER___S 28 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_1001_STATUS_FILTER___M 0x08000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_1001_STATUS_FILTER___S 27 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_1000_STATUS_FILTER___M 0x04000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_1000_STATUS_FILTER___S 26 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_1000_STATUS_FILTER___M 0x02000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_1000_STATUS_FILTER___S 25 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_1000_STATUS_FILTER___M 0x01000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_1000_STATUS_FILTER___S 24 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0111_STATUS_FILTER___M 0x00800000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0111_STATUS_FILTER___S 23 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0111_STATUS_FILTER___M 0x00400000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0111_STATUS_FILTER___S 22 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0111_STATUS_FILTER___M 0x00200000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0111_STATUS_FILTER___S 21 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0110_STATUS_FILTER___M 0x00100000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0110_STATUS_FILTER___S 20 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0110_STATUS_FILTER___M 0x00080000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0110_STATUS_FILTER___S 19 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0110_STATUS_FILTER___M 0x00040000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0110_STATUS_FILTER___S 18 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0101_STATUS_FILTER___M 0x00020000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0101_STATUS_FILTER___S 17 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0101_STATUS_FILTER___M 0x00010000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0101_STATUS_FILTER___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0101_STATUS_FILTER___M 0x00008000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0101_STATUS_FILTER___S 15 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0100_STATUS_FILTER___M 0x00004000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0100_STATUS_FILTER___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0100_STATUS_FILTER___M 0x00002000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0100_STATUS_FILTER___S 13 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0100_STATUS_FILTER___M 0x00001000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0100_STATUS_FILTER___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0011_STATUS_FILTER___M 0x00000800 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0011_STATUS_FILTER___S 11 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0011_STATUS_FILTER___M 0x00000400 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0011_STATUS_FILTER___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0011_STATUS_FILTER___M 0x00000200 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0011_STATUS_FILTER___S 9 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0010_STATUS_FILTER___M 0x00000100 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0010_STATUS_FILTER___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0010_STATUS_FILTER___M 0x00000080 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0010_STATUS_FILTER___S 7 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0010_STATUS_FILTER___M 0x00000040 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0010_STATUS_FILTER___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0001_STATUS_FILTER___M 0x00000020 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0001_STATUS_FILTER___S 5 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0001_STATUS_FILTER___M 0x00000010 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0001_STATUS_FILTER___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0001_STATUS_FILTER___M 0x00000008 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0001_STATUS_FILTER___S 3 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0000_STATUS_FILTER___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MO_CTRL_0000_STATUS_FILTER___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0000_STATUS_FILTER___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__MD_CTRL_0000_STATUS_FILTER___S 1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0000_STATUS_FILTER___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0__FP_CTRL_0000_STATUS_FILTER___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0___M 0x3FFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX0___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1 (0x00A950A4) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1111_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1111_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1111_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1110_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1110_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1110_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1101_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1101_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1101_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1100_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1100_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1100_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1011_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1011_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1011_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1010_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1010_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1010_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1111_STATUS_FILTER___M 0x00020000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1111_STATUS_FILTER___S 17 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1111_STATUS_FILTER___M 0x00010000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1111_STATUS_FILTER___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1111_STATUS_FILTER___M 0x00008000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1111_STATUS_FILTER___S 15 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1110_STATUS_FILTER___M 0x00004000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1110_STATUS_FILTER___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1110_STATUS_FILTER___M 0x00002000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1110_STATUS_FILTER___S 13 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1110_STATUS_FILTER___M 0x00001000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1110_STATUS_FILTER___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1101_STATUS_FILTER___M 0x00000800 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1101_STATUS_FILTER___S 11 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1101_STATUS_FILTER___M 0x00000400 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1101_STATUS_FILTER___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1101_STATUS_FILTER___M 0x00000200 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1101_STATUS_FILTER___S 9 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1100_STATUS_FILTER___M 0x00000100 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1100_STATUS_FILTER___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1100_STATUS_FILTER___M 0x00000080 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1100_STATUS_FILTER___S 7 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1100_STATUS_FILTER___M 0x00000040 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1100_STATUS_FILTER___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1011_STATUS_FILTER___M 0x00000020 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1011_STATUS_FILTER___S 5 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1011_STATUS_FILTER___M 0x00000010 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1011_STATUS_FILTER___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1011_STATUS_FILTER___M 0x00000008 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1011_STATUS_FILTER___S 3 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1010_STATUS_FILTER___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MO_CTRL_1010_STATUS_FILTER___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1010_STATUS_FILTER___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__MD_CTRL_1010_STATUS_FILTER___S 1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1010_STATUS_FILTER___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1__FP_CTRL_1010_STATUS_FILTER___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1___M 0x0003FFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_CTRL_FILTER_IN_CONTROL_IX1___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL (0x00A950A8) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL___POR 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_UNSUPP_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__MD_UNSUPP_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_PHY_ERR_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__MO_UNSUPP_STATUS_FILTER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__MO_NDP_STATUS_FILTER___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_NDP_STATUS_FILTER___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_UNSUPP_STATUS_FILTER___M 0x00000020 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_UNSUPP_STATUS_FILTER___S 5 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__MD_UNSUPP_STATUS_FILTER___M 0x00000010 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__MD_UNSUPP_STATUS_FILTER___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_PHY_ERR_STATUS_FILTER___M 0x00000008 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_PHY_ERR_STATUS_FILTER___S 3 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__MO_UNSUPP_STATUS_FILTER___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__MO_UNSUPP_STATUS_FILTER___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__MO_NDP_STATUS_FILTER___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__MO_NDP_STATUS_FILTER___S 1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_NDP_STATUS_FILTER___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL__FP_NDP_STATUS_FILTER___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL___M 0x0000003F +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MISC_FILTER_IN_CONTROL___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL (0x00A950AC) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL___POR 0x7ECFD9FB +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_FRAMELESS_BAR___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_ATTENTION___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_RX_HEADER_PER_MSDU___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_HEADER___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MPDU_END___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MSDU_END___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PACKET___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MSDU_START___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MPDU_START___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_FRAMELESS_BAR___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_ATTENTION___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_RX_HEADER_PER_MSDU___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_HEADER___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MPDU_END___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MSDU_END___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PACKET___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MSDU_START___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MPDU_START___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_FRAMELESS_BAR___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_ATTENTION___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_RX_HEADER_PER_MSDU___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_HEADER___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MPDU_END___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MSDU_END___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PACKET___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MSDU_START___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MPDU_START___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_FRAMELESS_BAR___M 0x40000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_FRAMELESS_BAR___S 30 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_ATTENTION___M 0x20000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_ATTENTION___S 29 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_RX_HEADER_PER_MSDU___M 0x10000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_RX_HEADER_PER_MSDU___S 28 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_HEADER___M 0x08000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_HEADER___S 27 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MPDU_END___M 0x04000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MPDU_END___S 26 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MSDU_END___M 0x02000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MSDU_END___S 25 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PACKET___M 0x01000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PACKET___S 24 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MSDU_START___M 0x00800000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MSDU_START___S 23 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MPDU_START___M 0x00400000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_MPDU_START___S 22 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_FRAMELESS_BAR___M 0x00080000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_FRAMELESS_BAR___S 19 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_ATTENTION___M 0x00040000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_ATTENTION___S 18 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_RX_HEADER_PER_MSDU___M 0x00020000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_RX_HEADER_PER_MSDU___S 17 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_HEADER___M 0x00010000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_HEADER___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MPDU_END___M 0x00008000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MPDU_END___S 15 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MSDU_END___M 0x00004000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MSDU_END___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PACKET___M 0x00002000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PACKET___S 13 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MSDU_START___M 0x00001000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MSDU_START___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MPDU_START___M 0x00000800 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_MPDU_START___S 11 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_FRAMELESS_BAR___M 0x00000100 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_FRAMELESS_BAR___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_ATTENTION___M 0x00000080 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_ATTENTION___S 7 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_RX_HEADER_PER_MSDU___M 0x00000040 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_RX_HEADER_PER_MSDU___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_HEADER___M 0x00000020 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_HEADER___S 5 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MPDU_END___M 0x00000010 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MPDU_END___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MSDU_END___M 0x00000008 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MSDU_END___S 3 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PACKET___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PACKET___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MSDU_START___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MSDU_START___S 1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MPDU_START___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_MPDU_START___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL___M 0x7FCFF9FF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_MPDU_TLV_FILTER_IN_CONTROL___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL (0x00A950B0) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL___POR 0x00AAAAAB +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PPDU_START_USER_INFO___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_STATUS_DONE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_STATUS_DONE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_STATUS_DONE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_USER_STATS___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_USER_STATS___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_USER_STATS___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PPDU_START___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PPDU_START_USER_INFO___M 0x02000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PPDU_START_USER_INFO___S 25 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_STATUS_DONE___M 0x01000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_STATUS_DONE___S 24 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___M 0x00800000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___S 23 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_STATUS_DONE___M 0x00400000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_STATUS_DONE___S 22 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___M 0x00200000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___S 21 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_STATUS_DONE___M 0x00100000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_STATUS_DONE___S 20 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___M 0x00080000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_STATUS_DONE___S 19 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___M 0x00040000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___S 18 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___M 0x00020000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___S 17 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___M 0x00010000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___M 0x00008000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___S 15 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___M 0x00004000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_USER_STATS_EXT___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___M 0x00002000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_USER_STATS_EXT___S 13 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_USER_STATS___M 0x00001000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END_USER_STATS___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___M 0x00000800 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___S 11 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_USER_STATS___M 0x00000400 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END_USER_STATS___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___M 0x00000200 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___S 9 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_USER_STATS___M 0x00000100 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END_USER_STATS___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___M 0x00000080 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END_USER_STATS___S 7 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END___M 0x00000040 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_RX_PPDU_END___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END___M 0x00000020 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MO_FILTER_IN_ALL_RX_PPDU_END___S 5 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END___M 0x00000010 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_RX_PPDU_END___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END___M 0x00000008 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__MD_FILTER_IN_ALL_RX_PPDU_END___S 3 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_RX_PPDU_END___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FP_FILTER_IN_ALL_RX_PPDU_END___S 1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PPDU_START___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL__FILTER_IN_RX_PPDU_START___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL___M 0x03FFFFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_STATUS_RING_PPDU_TLV_FILTER_IN_CONTROL___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT (0x00A950B4) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MO_NULL_DATA_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MD_NULL_DATA_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__FP_NULL_DATA_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MO_UCAST_DATA_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MD_UCAST_DATA_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__FP_UCAST_DATA_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MO_MCAST_DATA_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MD_MCAST_DATA_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__FP_MCAST_DATA_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MO_NULL_DATA_DESTINATION___M 0x00030000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MO_NULL_DATA_DESTINATION___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MD_NULL_DATA_DESTINATION___M 0x0000C000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MD_NULL_DATA_DESTINATION___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__FP_NULL_DATA_DESTINATION___M 0x00003000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__FP_NULL_DATA_DESTINATION___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MO_UCAST_DATA_DESTINATION___M 0x00000C00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MO_UCAST_DATA_DESTINATION___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MD_UCAST_DATA_DESTINATION___M 0x00000300 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MD_UCAST_DATA_DESTINATION___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__FP_UCAST_DATA_DESTINATION___M 0x000000C0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__FP_UCAST_DATA_DESTINATION___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MO_MCAST_DATA_DESTINATION___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MO_MCAST_DATA_DESTINATION___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MD_MCAST_DATA_DESTINATION___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__MD_MCAST_DATA_DESTINATION___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__FP_MCAST_DATA_DESTINATION___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT__FP_MCAST_DATA_DESTINATION___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT___M 0x0003FFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_DATA_DESTINATION_SELECT___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0 (0x00A950B8) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0100_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0100_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0100_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0011_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0011_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0011_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0010_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0010_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0010_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0001_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0001_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0001_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0000_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0000_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0000_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0100_DESTINATION___M 0x30000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0100_DESTINATION___S 28 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0100_DESTINATION___M 0x0C000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0100_DESTINATION___S 26 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0100_DESTINATION___M 0x03000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0100_DESTINATION___S 24 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0011_DESTINATION___M 0x00C00000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0011_DESTINATION___S 22 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0011_DESTINATION___M 0x00300000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0011_DESTINATION___S 20 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0011_DESTINATION___M 0x000C0000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0011_DESTINATION___S 18 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0010_DESTINATION___M 0x00030000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0010_DESTINATION___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0010_DESTINATION___M 0x0000C000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0010_DESTINATION___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0010_DESTINATION___M 0x00003000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0010_DESTINATION___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0001_DESTINATION___M 0x00000C00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0001_DESTINATION___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0001_DESTINATION___M 0x00000300 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0001_DESTINATION___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0001_DESTINATION___M 0x000000C0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0001_DESTINATION___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0000_DESTINATION___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0000_DESTINATION___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0000_DESTINATION___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0000_DESTINATION___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0000_DESTINATION___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0000_DESTINATION___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0___M 0x3FFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX0___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1 (0x00A950BC) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_1001_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_1001_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_1001_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_1000_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_1000_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_1000_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0111_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0111_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0111_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0110_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0110_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0110_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0101_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0101_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0101_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_1001_DESTINATION___M 0x30000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_1001_DESTINATION___S 28 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_1001_DESTINATION___M 0x0C000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_1001_DESTINATION___S 26 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_1001_DESTINATION___M 0x03000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_1001_DESTINATION___S 24 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_1000_DESTINATION___M 0x00C00000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_1000_DESTINATION___S 22 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_1000_DESTINATION___M 0x00300000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_1000_DESTINATION___S 20 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_1000_DESTINATION___M 0x000C0000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_1000_DESTINATION___S 18 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0111_DESTINATION___M 0x00030000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0111_DESTINATION___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0111_DESTINATION___M 0x0000C000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0111_DESTINATION___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0111_DESTINATION___M 0x00003000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0111_DESTINATION___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0110_DESTINATION___M 0x00000C00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0110_DESTINATION___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0110_DESTINATION___M 0x00000300 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0110_DESTINATION___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0110_DESTINATION___M 0x000000C0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0110_DESTINATION___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0101_DESTINATION___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0101_DESTINATION___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0101_DESTINATION___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0101_DESTINATION___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0101_DESTINATION___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0101_DESTINATION___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1___M 0x3FFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX1___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2 (0x00A950C0) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1110_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1110_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1110_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1101_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1101_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1101_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1100_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1100_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1100_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1011_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1011_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1011_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1010_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1010_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1010_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1110_DESTINATION___M 0x30000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1110_DESTINATION___S 28 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1110_DESTINATION___M 0x0C000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1110_DESTINATION___S 26 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1110_DESTINATION___M 0x03000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1110_DESTINATION___S 24 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1101_DESTINATION___M 0x00C00000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1101_DESTINATION___S 22 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1101_DESTINATION___M 0x00300000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1101_DESTINATION___S 20 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1101_DESTINATION___M 0x000C0000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1101_DESTINATION___S 18 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1100_DESTINATION___M 0x00030000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1100_DESTINATION___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1100_DESTINATION___M 0x0000C000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1100_DESTINATION___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1100_DESTINATION___M 0x00003000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1100_DESTINATION___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1011_DESTINATION___M 0x00000C00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1011_DESTINATION___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1011_DESTINATION___M 0x00000300 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1011_DESTINATION___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1011_DESTINATION___M 0x000000C0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1011_DESTINATION___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1010_DESTINATION___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1010_DESTINATION___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1010_DESTINATION___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1010_DESTINATION___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1010_DESTINATION___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1010_DESTINATION___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2___M 0x3FFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX2___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX3 (0x00A950C4) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX3___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX3___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX3__MO_MGMT_1111_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX3__MD_MGMT_1111_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX3__FP_MGMT_1111_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX3__MO_MGMT_1111_DESTINATION___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX3__MO_MGMT_1111_DESTINATION___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX3__MD_MGMT_1111_DESTINATION___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX3__MD_MGMT_1111_DESTINATION___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX3__FP_MGMT_1111_DESTINATION___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX3__FP_MGMT_1111_DESTINATION___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX3___M 0x0000003F +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MGMT_DESTINATION_SELECT_IX3___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0 (0x00A950C8) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0100_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0100_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0100_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0011_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0011_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0011_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0010_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0010_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0010_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0001_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0001_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0001_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0000_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0000_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0000_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0100_DESTINATION___M 0x30000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0100_DESTINATION___S 28 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0100_DESTINATION___M 0x0C000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0100_DESTINATION___S 26 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0100_DESTINATION___M 0x03000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0100_DESTINATION___S 24 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0011_DESTINATION___M 0x00C00000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0011_DESTINATION___S 22 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0011_DESTINATION___M 0x00300000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0011_DESTINATION___S 20 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0011_DESTINATION___M 0x000C0000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0011_DESTINATION___S 18 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0010_DESTINATION___M 0x00030000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0010_DESTINATION___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0010_DESTINATION___M 0x0000C000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0010_DESTINATION___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0010_DESTINATION___M 0x00003000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0010_DESTINATION___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0001_DESTINATION___M 0x00000C00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0001_DESTINATION___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0001_DESTINATION___M 0x00000300 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0001_DESTINATION___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0001_DESTINATION___M 0x000000C0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0001_DESTINATION___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0000_DESTINATION___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0000_DESTINATION___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0000_DESTINATION___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0000_DESTINATION___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0000_DESTINATION___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0000_DESTINATION___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0___M 0x3FFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX0___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1 (0x00A950CC) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_1001_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_1001_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_1001_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_1000_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_1000_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_1000_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0111_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0111_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0111_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0110_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0110_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0110_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0101_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0101_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0101_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_1001_DESTINATION___M 0x30000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_1001_DESTINATION___S 28 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_1001_DESTINATION___M 0x0C000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_1001_DESTINATION___S 26 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_1001_DESTINATION___M 0x03000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_1001_DESTINATION___S 24 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_1000_DESTINATION___M 0x00C00000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_1000_DESTINATION___S 22 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_1000_DESTINATION___M 0x00300000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_1000_DESTINATION___S 20 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_1000_DESTINATION___M 0x000C0000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_1000_DESTINATION___S 18 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0111_DESTINATION___M 0x00030000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0111_DESTINATION___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0111_DESTINATION___M 0x0000C000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0111_DESTINATION___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0111_DESTINATION___M 0x00003000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0111_DESTINATION___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0110_DESTINATION___M 0x00000C00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0110_DESTINATION___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0110_DESTINATION___M 0x00000300 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0110_DESTINATION___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0110_DESTINATION___M 0x000000C0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0110_DESTINATION___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0101_DESTINATION___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0101_DESTINATION___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0101_DESTINATION___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0101_DESTINATION___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0101_DESTINATION___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0101_DESTINATION___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1___M 0x3FFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX1___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2 (0x00A950D0) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1110_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1110_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1110_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1101_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1101_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1101_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1100_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1100_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1100_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1011_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1011_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1011_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1010_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1010_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1010_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1110_DESTINATION___M 0x30000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1110_DESTINATION___S 28 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1110_DESTINATION___M 0x0C000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1110_DESTINATION___S 26 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1110_DESTINATION___M 0x03000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1110_DESTINATION___S 24 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1101_DESTINATION___M 0x00C00000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1101_DESTINATION___S 22 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1101_DESTINATION___M 0x00300000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1101_DESTINATION___S 20 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1101_DESTINATION___M 0x000C0000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1101_DESTINATION___S 18 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1100_DESTINATION___M 0x00030000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1100_DESTINATION___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1100_DESTINATION___M 0x0000C000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1100_DESTINATION___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1100_DESTINATION___M 0x00003000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1100_DESTINATION___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1011_DESTINATION___M 0x00000C00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1011_DESTINATION___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1011_DESTINATION___M 0x00000300 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1011_DESTINATION___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1011_DESTINATION___M 0x000000C0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1011_DESTINATION___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1010_DESTINATION___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1010_DESTINATION___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1010_DESTINATION___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1010_DESTINATION___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1010_DESTINATION___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1010_DESTINATION___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2___M 0x3FFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX2___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX3 (0x00A950D4) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX3___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX3___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX3__MO_CTRL_1111_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX3__MD_CTRL_1111_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX3__FP_CTRL_1111_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX3__MO_CTRL_1111_DESTINATION___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX3__MO_CTRL_1111_DESTINATION___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX3__MD_CTRL_1111_DESTINATION___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX3__MD_CTRL_1111_DESTINATION___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX3__FP_CTRL_1111_DESTINATION___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX3__FP_CTRL_1111_DESTINATION___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX3___M 0x0000003F +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_CTRL_DESTINATION_SELECT_IX3___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT (0x00A950D8) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT___POR 0x00000005 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__FP_UNSUPP_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__MD_UNSUPP_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__FP_PHY_ERR_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__MO_UNSUPP_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__MO_NDP_DESTINATION___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__FP_NDP_DESTINATION___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__FP_UNSUPP_DESTINATION___M 0x00000C00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__FP_UNSUPP_DESTINATION___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__MD_UNSUPP_DESTINATION___M 0x00000300 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__MD_UNSUPP_DESTINATION___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__FP_PHY_ERR_DESTINATION___M 0x000000C0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__FP_PHY_ERR_DESTINATION___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__MO_UNSUPP_DESTINATION___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__MO_UNSUPP_DESTINATION___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__MO_NDP_DESTINATION___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__MO_NDP_DESTINATION___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__FP_NDP_DESTINATION___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT__FP_NDP_DESTINATION___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT___M 0x00000FFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA0_MISC_DESTINATION_SELECT___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT (0x00A950DC) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MO_NULL_DATA_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MD_NULL_DATA_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__FP_NULL_DATA_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MO_UCAST_DATA_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MD_UCAST_DATA_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__FP_UCAST_DATA_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MO_MCAST_DATA_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MD_MCAST_DATA_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__FP_MCAST_DATA_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MO_NULL_DATA_DESTINATION___M 0x00030000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MO_NULL_DATA_DESTINATION___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MD_NULL_DATA_DESTINATION___M 0x0000C000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MD_NULL_DATA_DESTINATION___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__FP_NULL_DATA_DESTINATION___M 0x00003000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__FP_NULL_DATA_DESTINATION___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MO_UCAST_DATA_DESTINATION___M 0x00000C00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MO_UCAST_DATA_DESTINATION___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MD_UCAST_DATA_DESTINATION___M 0x00000300 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MD_UCAST_DATA_DESTINATION___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__FP_UCAST_DATA_DESTINATION___M 0x000000C0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__FP_UCAST_DATA_DESTINATION___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MO_MCAST_DATA_DESTINATION___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MO_MCAST_DATA_DESTINATION___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MD_MCAST_DATA_DESTINATION___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__MD_MCAST_DATA_DESTINATION___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__FP_MCAST_DATA_DESTINATION___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT__FP_MCAST_DATA_DESTINATION___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT___M 0x0003FFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_DATA_DESTINATION_SELECT___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0 (0x00A950E0) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0100_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0100_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0100_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0011_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0011_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0011_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0010_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0010_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0010_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0001_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0001_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0001_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0000_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0000_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0000_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0100_DESTINATION___M 0x30000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0100_DESTINATION___S 28 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0100_DESTINATION___M 0x0C000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0100_DESTINATION___S 26 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0100_DESTINATION___M 0x03000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0100_DESTINATION___S 24 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0011_DESTINATION___M 0x00C00000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0011_DESTINATION___S 22 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0011_DESTINATION___M 0x00300000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0011_DESTINATION___S 20 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0011_DESTINATION___M 0x000C0000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0011_DESTINATION___S 18 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0010_DESTINATION___M 0x00030000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0010_DESTINATION___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0010_DESTINATION___M 0x0000C000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0010_DESTINATION___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0010_DESTINATION___M 0x00003000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0010_DESTINATION___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0001_DESTINATION___M 0x00000C00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0001_DESTINATION___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0001_DESTINATION___M 0x00000300 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0001_DESTINATION___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0001_DESTINATION___M 0x000000C0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0001_DESTINATION___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0000_DESTINATION___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MO_MGMT_0000_DESTINATION___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0000_DESTINATION___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__MD_MGMT_0000_DESTINATION___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0000_DESTINATION___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0__FP_MGMT_0000_DESTINATION___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0___M 0x3FFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX0___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1 (0x00A950E4) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_1001_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_1001_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_1001_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_1000_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_1000_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_1000_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0111_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0111_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0111_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0110_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0110_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0110_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0101_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0101_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0101_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_1001_DESTINATION___M 0x30000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_1001_DESTINATION___S 28 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_1001_DESTINATION___M 0x0C000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_1001_DESTINATION___S 26 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_1001_DESTINATION___M 0x03000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_1001_DESTINATION___S 24 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_1000_DESTINATION___M 0x00C00000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_1000_DESTINATION___S 22 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_1000_DESTINATION___M 0x00300000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_1000_DESTINATION___S 20 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_1000_DESTINATION___M 0x000C0000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_1000_DESTINATION___S 18 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0111_DESTINATION___M 0x00030000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0111_DESTINATION___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0111_DESTINATION___M 0x0000C000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0111_DESTINATION___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0111_DESTINATION___M 0x00003000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0111_DESTINATION___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0110_DESTINATION___M 0x00000C00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0110_DESTINATION___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0110_DESTINATION___M 0x00000300 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0110_DESTINATION___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0110_DESTINATION___M 0x000000C0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0110_DESTINATION___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0101_DESTINATION___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MO_MGMT_0101_DESTINATION___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0101_DESTINATION___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__MD_MGMT_0101_DESTINATION___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0101_DESTINATION___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1__FP_MGMT_0101_DESTINATION___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1___M 0x3FFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX1___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2 (0x00A950E8) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1110_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1110_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1110_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1101_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1101_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1101_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1100_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1100_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1100_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1011_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1011_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1011_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1010_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1010_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1010_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1110_DESTINATION___M 0x30000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1110_DESTINATION___S 28 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1110_DESTINATION___M 0x0C000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1110_DESTINATION___S 26 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1110_DESTINATION___M 0x03000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1110_DESTINATION___S 24 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1101_DESTINATION___M 0x00C00000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1101_DESTINATION___S 22 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1101_DESTINATION___M 0x00300000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1101_DESTINATION___S 20 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1101_DESTINATION___M 0x000C0000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1101_DESTINATION___S 18 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1100_DESTINATION___M 0x00030000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1100_DESTINATION___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1100_DESTINATION___M 0x0000C000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1100_DESTINATION___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1100_DESTINATION___M 0x00003000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1100_DESTINATION___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1011_DESTINATION___M 0x00000C00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1011_DESTINATION___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1011_DESTINATION___M 0x00000300 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1011_DESTINATION___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1011_DESTINATION___M 0x000000C0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1011_DESTINATION___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1010_DESTINATION___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MO_MGMT_1010_DESTINATION___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1010_DESTINATION___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__MD_MGMT_1010_DESTINATION___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1010_DESTINATION___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2__FP_MGMT_1010_DESTINATION___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2___M 0x3FFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX2___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX3 (0x00A950EC) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX3___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX3___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX3__MO_MGMT_1111_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX3__MD_MGMT_1111_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX3__FP_MGMT_1111_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX3__MO_MGMT_1111_DESTINATION___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX3__MO_MGMT_1111_DESTINATION___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX3__MD_MGMT_1111_DESTINATION___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX3__MD_MGMT_1111_DESTINATION___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX3__FP_MGMT_1111_DESTINATION___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX3__FP_MGMT_1111_DESTINATION___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX3___M 0x0000003F +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MGMT_DESTINATION_SELECT_IX3___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0 (0x00A950F0) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0100_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0100_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0100_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0011_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0011_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0011_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0010_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0010_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0010_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0001_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0001_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0001_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0000_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0000_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0000_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0100_DESTINATION___M 0x30000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0100_DESTINATION___S 28 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0100_DESTINATION___M 0x0C000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0100_DESTINATION___S 26 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0100_DESTINATION___M 0x03000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0100_DESTINATION___S 24 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0011_DESTINATION___M 0x00C00000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0011_DESTINATION___S 22 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0011_DESTINATION___M 0x00300000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0011_DESTINATION___S 20 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0011_DESTINATION___M 0x000C0000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0011_DESTINATION___S 18 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0010_DESTINATION___M 0x00030000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0010_DESTINATION___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0010_DESTINATION___M 0x0000C000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0010_DESTINATION___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0010_DESTINATION___M 0x00003000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0010_DESTINATION___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0001_DESTINATION___M 0x00000C00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0001_DESTINATION___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0001_DESTINATION___M 0x00000300 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0001_DESTINATION___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0001_DESTINATION___M 0x000000C0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0001_DESTINATION___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0000_DESTINATION___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MO_CTRL_0000_DESTINATION___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0000_DESTINATION___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__MD_CTRL_0000_DESTINATION___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0000_DESTINATION___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0__FP_CTRL_0000_DESTINATION___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0___M 0x3FFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX0___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1 (0x00A950F4) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_1001_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_1001_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_1001_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_1000_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_1000_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_1000_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0111_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0111_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0111_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0110_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0110_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0110_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0101_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0101_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0101_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_1001_DESTINATION___M 0x30000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_1001_DESTINATION___S 28 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_1001_DESTINATION___M 0x0C000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_1001_DESTINATION___S 26 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_1001_DESTINATION___M 0x03000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_1001_DESTINATION___S 24 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_1000_DESTINATION___M 0x00C00000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_1000_DESTINATION___S 22 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_1000_DESTINATION___M 0x00300000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_1000_DESTINATION___S 20 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_1000_DESTINATION___M 0x000C0000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_1000_DESTINATION___S 18 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0111_DESTINATION___M 0x00030000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0111_DESTINATION___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0111_DESTINATION___M 0x0000C000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0111_DESTINATION___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0111_DESTINATION___M 0x00003000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0111_DESTINATION___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0110_DESTINATION___M 0x00000C00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0110_DESTINATION___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0110_DESTINATION___M 0x00000300 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0110_DESTINATION___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0110_DESTINATION___M 0x000000C0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0110_DESTINATION___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0101_DESTINATION___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MO_CTRL_0101_DESTINATION___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0101_DESTINATION___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__MD_CTRL_0101_DESTINATION___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0101_DESTINATION___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1__FP_CTRL_0101_DESTINATION___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1___M 0x3FFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX1___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2 (0x00A950F8) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1110_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1110_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1110_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1101_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1101_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1101_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1100_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1100_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1100_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1011_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1011_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1011_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1010_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1010_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1010_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1110_DESTINATION___M 0x30000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1110_DESTINATION___S 28 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1110_DESTINATION___M 0x0C000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1110_DESTINATION___S 26 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1110_DESTINATION___M 0x03000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1110_DESTINATION___S 24 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1101_DESTINATION___M 0x00C00000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1101_DESTINATION___S 22 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1101_DESTINATION___M 0x00300000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1101_DESTINATION___S 20 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1101_DESTINATION___M 0x000C0000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1101_DESTINATION___S 18 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1100_DESTINATION___M 0x00030000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1100_DESTINATION___S 16 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1100_DESTINATION___M 0x0000C000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1100_DESTINATION___S 14 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1100_DESTINATION___M 0x00003000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1100_DESTINATION___S 12 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1011_DESTINATION___M 0x00000C00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1011_DESTINATION___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1011_DESTINATION___M 0x00000300 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1011_DESTINATION___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1011_DESTINATION___M 0x000000C0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1011_DESTINATION___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1010_DESTINATION___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MO_CTRL_1010_DESTINATION___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1010_DESTINATION___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__MD_CTRL_1010_DESTINATION___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1010_DESTINATION___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2__FP_CTRL_1010_DESTINATION___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2___M 0x3FFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX2___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX3 (0x00A950FC) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX3___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX3___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX3__MO_CTRL_1111_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX3__MD_CTRL_1111_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX3__FP_CTRL_1111_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX3__MO_CTRL_1111_DESTINATION___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX3__MO_CTRL_1111_DESTINATION___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX3__MD_CTRL_1111_DESTINATION___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX3__MD_CTRL_1111_DESTINATION___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX3__FP_CTRL_1111_DESTINATION___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX3__FP_CTRL_1111_DESTINATION___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX3___M 0x0000003F +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_CTRL_DESTINATION_SELECT_IX3___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT (0x00A95100) +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT___POR 0x00000005 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__FP_UNSUPP_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__MD_UNSUPP_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__FP_PHY_ERR_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__MO_UNSUPP_DESTINATION___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__MO_NDP_DESTINATION___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__FP_NDP_DESTINATION___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__FP_UNSUPP_DESTINATION___M 0x00000C00 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__FP_UNSUPP_DESTINATION___S 10 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__MD_UNSUPP_DESTINATION___M 0x00000300 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__MD_UNSUPP_DESTINATION___S 8 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__FP_PHY_ERR_DESTINATION___M 0x000000C0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__FP_PHY_ERR_DESTINATION___S 6 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__MO_UNSUPP_DESTINATION___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__MO_UNSUPP_DESTINATION___S 4 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__MO_NDP_DESTINATION___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__MO_NDP_DESTINATION___S 2 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__FP_NDP_DESTINATION___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT__FP_NDP_DESTINATION___S 0 +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT___M 0x00000FFF +#define WMAC0_RXOLE_RXOLE_R0_RXDMA1_MISC_DESTINATION_SELECT___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION (0x00A95104) +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION___POR 0x81000024 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_FLOW_ID_TOEPLITZ_CLFY___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__CCE_UPDATE_DISABLE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__FSE_UPDATE_DISABLE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ASE_UPDATE_DISABLE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__CCE_FAIL_DROP___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__FSE_FAIL_DROP___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ASE_FAIL_DROP___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__HASH_BASED_DESTINATION___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__CCE_FAIL_NUM___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__FSE_FAIL_NUM___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ASE_FAIL_NUM___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_2_CLFY_FOR_IPV6___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_2_CLFY_FOR_IPV4___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_4_CLFY_FOR_UDP_OVER_IPV6___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_4_CLFY_FOR_TCP_OVER_IPV6___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_4_CLFY_FOR_UDP_OVER_IPV4___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_4_CLFY_FOR_TCP_OVER_IPV4___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__CCE_FAIL_HANDLER___POR 0x2 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__FSE_FAIL_HANDLER___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ASE_FAIL_HANDLER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_FLOW_ID_TOEPLITZ_CLFY___M 0x80000000 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_FLOW_ID_TOEPLITZ_CLFY___S 31 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__CCE_UPDATE_DISABLE___M 0x40000000 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__CCE_UPDATE_DISABLE___S 30 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__FSE_UPDATE_DISABLE___M 0x20000000 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__FSE_UPDATE_DISABLE___S 29 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ASE_UPDATE_DISABLE___M 0x10000000 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ASE_UPDATE_DISABLE___S 28 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__CCE_FAIL_DROP___M 0x08000000 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__CCE_FAIL_DROP___S 27 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__FSE_FAIL_DROP___M 0x04000000 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__FSE_FAIL_DROP___S 26 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ASE_FAIL_DROP___M 0x02000000 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ASE_FAIL_DROP___S 25 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__HASH_BASED_DESTINATION___M 0x01000000 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__HASH_BASED_DESTINATION___S 24 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__CCE_FAIL_NUM___M 0x00F00000 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__CCE_FAIL_NUM___S 20 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__FSE_FAIL_NUM___M 0x000F0000 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__FSE_FAIL_NUM___S 16 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ASE_FAIL_NUM___M 0x0000F000 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ASE_FAIL_NUM___S 12 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_2_CLFY_FOR_IPV6___M 0x00000800 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_2_CLFY_FOR_IPV6___S 11 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_2_CLFY_FOR_IPV4___M 0x00000400 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_2_CLFY_FOR_IPV4___S 10 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_4_CLFY_FOR_UDP_OVER_IPV6___M 0x00000200 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_4_CLFY_FOR_UDP_OVER_IPV6___S 9 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_4_CLFY_FOR_TCP_OVER_IPV6___M 0x00000100 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_4_CLFY_FOR_TCP_OVER_IPV6___S 8 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_4_CLFY_FOR_UDP_OVER_IPV4___M 0x00000080 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_4_CLFY_FOR_UDP_OVER_IPV4___S 7 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_4_CLFY_FOR_TCP_OVER_IPV4___M 0x00000040 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ENABLE_TOEPLITZ_HASH_4_CLFY_FOR_TCP_OVER_IPV4___S 6 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__CCE_FAIL_HANDLER___M 0x00000030 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__CCE_FAIL_HANDLER___S 4 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__FSE_FAIL_HANDLER___M 0x0000000C +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__FSE_FAIL_HANDLER___S 2 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ASE_FAIL_HANDLER___M 0x00000003 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION__ASE_FAIL_HANDLER___S 0 +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_CONFIG_REO_DESTINATION___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG (0x00A95108) +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG___POR 0x00410072 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__ENABLE_MAX_SECTION_SIZE___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__ENABLE_C9D1___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__L4_OFFSET_FROM_RX_HEADER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__L3_OFFSET_FROM_RX_HEADER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__L2_PAYLOAD_CHECKSUM_ENABLE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__L3_PAYLOAD_CHKSUM_ENABLE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__ENABLE_PE___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__ONLY_DIRECTED_MCAST_BCAST___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__TCP_UDP_CHECKSUM_SEL___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__IP_CHECKSUM_SEL___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__REMOVE_VLAN_TAG___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__TARGET_FORMAT___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__ENABLE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__ENABLE_MAX_SECTION_SIZE___M 0x00400000 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__ENABLE_MAX_SECTION_SIZE___S 22 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__ENABLE_C9D1___M 0x00200000 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__ENABLE_C9D1___S 21 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__L4_OFFSET_FROM_RX_HEADER___M 0x00100000 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__L4_OFFSET_FROM_RX_HEADER___S 20 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__L3_OFFSET_FROM_RX_HEADER___M 0x00080000 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__L3_OFFSET_FROM_RX_HEADER___S 19 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__L2_PAYLOAD_CHECKSUM_ENABLE___M 0x00040000 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__L2_PAYLOAD_CHECKSUM_ENABLE___S 18 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__L3_PAYLOAD_CHKSUM_ENABLE___M 0x00020000 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__L3_PAYLOAD_CHKSUM_ENABLE___S 17 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__ENABLE_PE___M 0x00010000 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__ENABLE_PE___S 16 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__ONLY_DIRECTED_MCAST_BCAST___M 0x00000040 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__ONLY_DIRECTED_MCAST_BCAST___S 6 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__TCP_UDP_CHECKSUM_SEL___M 0x00000020 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__TCP_UDP_CHECKSUM_SEL___S 5 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__IP_CHECKSUM_SEL___M 0x00000010 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__IP_CHECKSUM_SEL___S 4 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__REMOVE_VLAN_TAG___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__REMOVE_VLAN_TAG___S 2 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__TARGET_FORMAT___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__TARGET_FORMAT___S 1 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__ENABLE___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG__ENABLE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG___M 0x007F0077 +#define WMAC0_RXOLE_RXOLE_R0_DECAP_CONFIG___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_HEADER_PADDING (0x00A9510C) +#define WMAC0_RXOLE_RXOLE_R0_HEADER_PADDING___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_HEADER_PADDING___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_HEADER_PADDING__RX_L3_HEADER_PADDING___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_HEADER_PADDING__RX_L3_HEADER_PADDING___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_HEADER_PADDING__RX_L3_HEADER_PADDING___S 2 +#define WMAC0_RXOLE_RXOLE_R0_HEADER_PADDING___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_HEADER_PADDING___S 2 + +#define WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT (0x00A95110) +#define WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT___POR 0x03010300 +#define WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__COUNT_THRESHOLD___POR 0x030 +#define WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__COUNT_THRESHOLD_MCAST___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__SIZE_THRESHOLD___POR 0x030 +#define WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__COUNT_ENABLE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__COUNT_ENABLE_MCAST___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__SIZE_ENABLE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__COUNT_THRESHOLD___M 0xFFF00000 +#define WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__COUNT_THRESHOLD___S 20 +#define WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__COUNT_THRESHOLD_MCAST___M 0x000F0000 +#define WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__COUNT_THRESHOLD_MCAST___S 16 +#define WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__SIZE_THRESHOLD___M 0x0000FFF0 +#define WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__SIZE_THRESHOLD___S 4 +#define WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__COUNT_ENABLE___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__COUNT_ENABLE___S 2 +#define WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__COUNT_ENABLE_MCAST___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__COUNT_ENABLE_MCAST___S 1 +#define WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__SIZE_ENABLE___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT__SIZE_ENABLE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT___M 0xFFFFFFF7 +#define WMAC0_RXOLE_RXOLE_R0_AMSDU_LIMIT___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_LRO (0x00A95114) +#define WMAC0_RXOLE_RXOLE_R0_LRO___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_LRO___POR 0x00000006 +#define WMAC0_RXOLE_RXOLE_R0_LRO__TCP_FLAG_MASK___POR 0x000 +#define WMAC0_RXOLE_RXOLE_R0_LRO__TCP_FLAG___POR 0x000 +#define WMAC0_RXOLE_RXOLE_R0_LRO__PAYLOAD_CHECKSUM_ALWAYS___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_LRO__PAYLOAD_CHECKSUM_ON_LRO___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_LRO__ENABLE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_LRO__TCP_FLAG_MASK___M 0x003FE000 +#define WMAC0_RXOLE_RXOLE_R0_LRO__TCP_FLAG_MASK___S 13 +#define WMAC0_RXOLE_RXOLE_R0_LRO__TCP_FLAG___M 0x00001FF0 +#define WMAC0_RXOLE_RXOLE_R0_LRO__TCP_FLAG___S 4 +#define WMAC0_RXOLE_RXOLE_R0_LRO__PAYLOAD_CHECKSUM_ALWAYS___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_LRO__PAYLOAD_CHECKSUM_ALWAYS___S 2 +#define WMAC0_RXOLE_RXOLE_R0_LRO__PAYLOAD_CHECKSUM_ON_LRO___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_LRO__PAYLOAD_CHECKSUM_ON_LRO___S 1 +#define WMAC0_RXOLE_RXOLE_R0_LRO__ENABLE___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_LRO__ENABLE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_LRO___M 0x003FFFF7 +#define WMAC0_RXOLE_RXOLE_R0_LRO___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL (0x00A95118) +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL___POR 0x0003E068 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__LIMIT___POR 0xF +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_MSDU_DROP_CHECK___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_DECRYPT_ERR_CHECK___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_RAW_CHECK___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_QOS_CHECK___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_TA_CHECK___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_TID_CHECK___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__CHKSUM_CUM_IP_LEN_EN___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_UDP_HDR_LEN___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_TCP_FIXED_HDR_LEN___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_IPV6_FIXED_HDR_LEN___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_IPV4_FIXED_HDR_LEN___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__NON_TCP_SKIP_SEARCH___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__IPSEC_SKIP_SEARCH___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ENABLE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__LIMIT___M 0x0003C000 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__LIMIT___S 14 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_MSDU_DROP_CHECK___M 0x00002000 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_MSDU_DROP_CHECK___S 13 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_DECRYPT_ERR_CHECK___M 0x00001000 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_DECRYPT_ERR_CHECK___S 12 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_RAW_CHECK___M 0x00000800 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_RAW_CHECK___S 11 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_QOS_CHECK___M 0x00000400 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_QOS_CHECK___S 10 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_TA_CHECK___M 0x00000200 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_TA_CHECK___S 9 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_TID_CHECK___M 0x00000100 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__DISABLE_TID_CHECK___S 8 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__CHKSUM_CUM_IP_LEN_EN___M 0x00000080 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__CHKSUM_CUM_IP_LEN_EN___S 7 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_UDP_HDR_LEN___M 0x00000040 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_UDP_HDR_LEN___S 6 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_TCP_FIXED_HDR_LEN___M 0x00000020 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_TCP_FIXED_HDR_LEN___S 5 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_IPV6_FIXED_HDR_LEN___M 0x00000010 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_IPV6_FIXED_HDR_LEN___S 4 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_IPV4_FIXED_HDR_LEN___M 0x00000008 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ADD_IPV4_FIXED_HDR_LEN___S 3 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__NON_TCP_SKIP_SEARCH___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__NON_TCP_SKIP_SEARCH___S 2 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__IPSEC_SKIP_SEARCH___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__IPSEC_SKIP_SEARCH___S 1 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ENABLE___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL__ENABLE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL___M 0x0003FFFF +#define WMAC0_RXOLE_RXOLE_R0_FISA_CTRL___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_FISA_TIMEOUT_THRESH (0x00A9511C) +#define WMAC0_RXOLE_RXOLE_R0_FISA_TIMEOUT_THRESH___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_FISA_TIMEOUT_THRESH___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_FISA_TIMEOUT_THRESH__VALUE___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_FISA_TIMEOUT_THRESH__VALUE___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_FISA_TIMEOUT_THRESH__VALUE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_FISA_TIMEOUT_THRESH___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_FISA_TIMEOUT_THRESH___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_WATCHDOG (0x00A95120) +#define WMAC0_RXOLE_RXOLE_R0_WATCHDOG___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_WATCHDOG___POR 0x0000FFFF +#define WMAC0_RXOLE_RXOLE_R0_WATCHDOG__STATUS___POR 0x0000 +#define WMAC0_RXOLE_RXOLE_R0_WATCHDOG__LIMIT___POR 0xFFFF +#define WMAC0_RXOLE_RXOLE_R0_WATCHDOG__STATUS___M 0xFFFF0000 +#define WMAC0_RXOLE_RXOLE_R0_WATCHDOG__STATUS___S 16 +#define WMAC0_RXOLE_RXOLE_R0_WATCHDOG__LIMIT___M 0x0000FFFF +#define WMAC0_RXOLE_RXOLE_R0_WATCHDOG__LIMIT___S 0 +#define WMAC0_RXOLE_RXOLE_R0_WATCHDOG___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_WATCHDOG___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE (0x00A95124) +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CLK_EXTEND___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__RSRVD___POR 0x00000 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__FSE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__ASE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__SFM_READ___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__SFM_WRITE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CCE_APB___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__PARSER_APB___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__INVALID_APB_ACC___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__BUF___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__PARSER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CCE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CORE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CLK_EXTEND___M 0x80000000 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CLK_EXTEND___S 31 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___M 0x40000000 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___S 30 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__RSRVD___M 0x3FFFF800 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__RSRVD___S 11 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__FSE___M 0x00000400 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__FSE___S 10 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__ASE___M 0x00000200 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__ASE___S 9 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__SFM_READ___M 0x00000100 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__SFM_READ___S 8 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__SFM_WRITE___M 0x00000080 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__SFM_WRITE___S 7 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CCE_APB___M 0x00000040 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CCE_APB___S 6 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__PARSER_APB___M 0x00000020 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__PARSER_APB___S 5 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__INVALID_APB_ACC___M 0x00000010 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__INVALID_APB_ACC___S 4 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__BUF___M 0x00000008 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__BUF___S 3 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__PARSER___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__PARSER___S 2 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CCE___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CCE___S 1 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CORE___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE__CORE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_CLKGATE_DISABLE___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG (0x00A95128) +#define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG___POR 0x000000C0 +#define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__MAX_MSDU_SIZE___POR 0x0C +#define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__OVERRIDE_MSDU_END_FIELDS___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__REPORT_3_TUPLE_HASH_IN_2_OR_4___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__REPORT_3_TUPLE_HASH_IN_FLOW_ID_TOEPLITZ___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__MAX_MSDU_SIZE___M 0x000001F0 +#define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__MAX_MSDU_SIZE___S 4 +#define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__OVERRIDE_MSDU_END_FIELDS___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__OVERRIDE_MSDU_END_FIELDS___S 2 +#define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__REPORT_3_TUPLE_HASH_IN_2_OR_4___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__REPORT_3_TUPLE_HASH_IN_2_OR_4___S 1 +#define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__REPORT_3_TUPLE_HASH_IN_FLOW_ID_TOEPLITZ___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG__REPORT_3_TUPLE_HASH_IN_FLOW_ID_TOEPLITZ___S 0 +#define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG___M 0x000001F7 +#define WMAC0_RXOLE_RXOLE_R0_MISC_CONFIG___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG (0x00A9512C) +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG___POR 0x00000606 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__TAG_MATCH_WITH_CURRENT_PPDU___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__ENABLE_USEC_TIMEOUT___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FLUSH_ON_WDOG___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX7_DISABLE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX6_ENABLE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX5_ENABLE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX4_ENABLE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX3_ENABLE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX2_ENABLE___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX1_ENABLE___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__DISABLE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__TAG_MATCH_WITH_CURRENT_PPDU___M 0x00000400 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__TAG_MATCH_WITH_CURRENT_PPDU___S 10 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__ENABLE_USEC_TIMEOUT___M 0x00000200 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__ENABLE_USEC_TIMEOUT___S 9 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FLUSH_ON_WDOG___M 0x00000100 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FLUSH_ON_WDOG___S 8 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX7_DISABLE___M 0x00000080 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX7_DISABLE___S 7 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX6_ENABLE___M 0x00000040 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX6_ENABLE___S 6 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX5_ENABLE___M 0x00000020 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX5_ENABLE___S 5 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX4_ENABLE___M 0x00000010 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX4_ENABLE___S 4 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX3_ENABLE___M 0x00000008 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX3_ENABLE___S 3 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX2_ENABLE___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX2_ENABLE___S 2 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX1_ENABLE___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__FIX1_ENABLE___S 1 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__DISABLE___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG__DISABLE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG___M 0x000007FF +#define WMAC0_RXOLE_RXOLE_R0_MISC2_CONFIG___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_31_0 (0x00A95130) +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_31_0___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_31_0___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_31_0__VALUE___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_31_0__VALUE___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_31_0__VALUE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_31_0___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_31_0___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_63_32 (0x00A95134) +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_63_32___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_63_32___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_63_32__VALUE___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_63_32__VALUE___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_63_32__VALUE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_63_32___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_63_32___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_64 (0x00A95138) +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_64___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_64___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_64__VALUE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_64__VALUE___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_64__VALUE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_64___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_AST_64___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_31_0 (0x00A9513C) +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_31_0___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_31_0___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_31_0__VALUE___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_31_0__VALUE___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_31_0__VALUE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_31_0___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_31_0___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_63_32 (0x00A95140) +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_63_32___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_63_32___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_63_32__VALUE___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_63_32__VALUE___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_63_32__VALUE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_63_32___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_63_32___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_95_64 (0x00A95144) +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_95_64___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_95_64___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_95_64__VALUE___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_95_64__VALUE___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_95_64__VALUE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_95_64___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_95_64___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_127_96 (0x00A95148) +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_127_96___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_127_96___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_127_96__VALUE___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_127_96__VALUE___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_127_96__VALUE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_127_96___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_127_96___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_159_128 (0x00A9514C) +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_159_128___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_159_128___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_159_128__VALUE___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_159_128__VALUE___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_159_128__VALUE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_159_128___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_159_128___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_191_160 (0x00A95150) +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_191_160___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_191_160___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_191_160__VALUE___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_191_160__VALUE___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_191_160__VALUE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_191_160___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_191_160___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_223_192 (0x00A95154) +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_223_192___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_223_192___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_223_192__VALUE___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_223_192__VALUE___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_223_192__VALUE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_223_192___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_223_192___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_255_224 (0x00A95158) +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_255_224___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_255_224___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_255_224__VALUE___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_255_224__VALUE___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_255_224__VALUE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_255_224___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_255_224___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_287_256 (0x00A9515C) +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_287_256___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_287_256___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_287_256__VALUE___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_287_256__VALUE___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_287_256__VALUE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_287_256___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_287_256___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_314_288 (0x00A95160) +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_314_288___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_314_288___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_314_288__VALUE___POR 0x0000000 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_314_288__VALUE___M 0x07FFFFFF +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_314_288__VALUE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_314_288___M 0x07FFFFFF +#define WMAC0_RXOLE_RXOLE_R0_TOEPLITZ_KEY_FT_314_288___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_31_0 (0x00A95164) +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_31_0___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_31_0___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_31_0__VALUE___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_31_0__VALUE___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_31_0__VALUE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_31_0___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_31_0___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_63_32 (0x00A95168) +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_63_32___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_63_32___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_63_32__VALUE___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_63_32__VALUE___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_63_32__VALUE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_63_32___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_63_32___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_95_64 (0x00A9516C) +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_95_64___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_95_64___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_95_64__VALUE___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_95_64__VALUE___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_95_64__VALUE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_95_64___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_95_64___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_127_96 (0x00A95170) +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_127_96___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_127_96___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_127_96__VALUE___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_127_96__VALUE___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_127_96__VALUE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_127_96___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_SA_127_96___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_31_0 (0x00A95174) +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_31_0___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_31_0___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_31_0__VALUE___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_31_0__VALUE___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_31_0__VALUE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_31_0___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_31_0___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_63_32 (0x00A95178) +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_63_32___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_63_32___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_63_32__VALUE___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_63_32__VALUE___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_63_32__VALUE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_63_32___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_63_32___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_95_64 (0x00A9517C) +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_95_64___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_95_64___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_95_64__VALUE___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_95_64__VALUE___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_95_64__VALUE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_95_64___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_95_64___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_127_96 (0x00A95180) +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_127_96___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_127_96___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_127_96__VALUE___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_127_96__VALUE___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_127_96__VALUE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_127_96___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_IP_DA_127_96___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PORT (0x00A95184) +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PORT___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PORT___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PORT__DST___POR 0x0000 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PORT__SRC___POR 0x0000 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PORT__DST___M 0xFFFF0000 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PORT__DST___S 16 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PORT__SRC___M 0x0000FFFF +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PORT__SRC___S 0 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PORT___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PORT___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PROTO (0x00A95188) +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PROTO___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PROTO___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PROTO__VALUE___POR 0x00 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PROTO__VALUE___M 0x000000FF +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PROTO__VALUE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PROTO___M 0x000000FF +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_L4_PROTO___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND (0x00A9518C) +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND__FULL_CACHE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND__CACHE_INVALIDATE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND__WRITE_BACK___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND__CLEAR_STATS___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND__WRITE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND__FULL_CACHE___M 0x00000010 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND__FULL_CACHE___S 4 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND__CACHE_INVALIDATE___M 0x00000008 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND__CACHE_INVALIDATE___S 3 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND__WRITE_BACK___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND__WRITE_BACK___S 2 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND__CLEAR_STATS___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND__CLEAR_STATS___S 1 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND__WRITE___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND__WRITE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND___M 0x0000001F +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_COMMAND___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_0 (0x00A95190) +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_0___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_0___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_0__MSDU_CNT___POR 0x000000 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_0__MATCH_FOUND___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_0__DONE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_0__MSDU_CNT___M 0x0FFFFFF0 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_0__MSDU_CNT___S 4 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_0__MATCH_FOUND___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_0__MATCH_FOUND___S 1 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_0__DONE___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_0__DONE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_0___M 0x0FFFFFF3 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_0___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_1 (0x00A95194) +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_1___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_1___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_1__MSDU_BYTE_CNT___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_1__MSDU_BYTE_CNT___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_1__MSDU_BYTE_CNT___S 0 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_1___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_1___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_2 (0x00A95198) +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_2___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_2___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_2__TIMESTAMP___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_2__TIMESTAMP___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_2__TIMESTAMP___S 0 +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_2___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_FLOW_SEARCH_CACHE_RESPONSE_IX_2___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_31_0 (0x00A9519C) +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_31_0___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_31_0___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_31_0__MAC_ADDR_31_0___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_31_0__MAC_ADDR_31_0___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_31_0__MAC_ADDR_31_0___S 0 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_31_0___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_31_0___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_47_32_MAC_ID (0x00A951A0) +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_47_32_MAC_ID___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_47_32_MAC_ID___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_47_32_MAC_ID__MAC_ID___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_47_32_MAC_ID__MAC_ADDR_47_32___POR 0x0000 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_47_32_MAC_ID__MAC_ID___M 0x00030000 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_47_32_MAC_ID__MAC_ID___S 16 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_47_32_MAC_ID__MAC_ADDR_47_32___M 0x0000FFFF +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_47_32_MAC_ID__MAC_ADDR_47_32___S 0 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_47_32_MAC_ID___M 0x0003FFFF +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_ADDR_47_32_MAC_ID___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND (0x00A951A4) +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND__FULL_CACHE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND__CACHE_INVALIDATE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND__WRITE_BACK___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND__CLEAR_STATS___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND__WRITE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND__FULL_CACHE___M 0x00000010 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND__FULL_CACHE___S 4 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND__CACHE_INVALIDATE___M 0x00000008 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND__CACHE_INVALIDATE___S 3 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND__WRITE_BACK___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND__WRITE_BACK___S 2 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND__CLEAR_STATS___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND__CLEAR_STATS___S 1 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND__WRITE___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND__WRITE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND___M 0x0000001F +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_COMMAND___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_0 (0x00A951A8) +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_0___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_0___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_0__MSDU_CNT___POR 0x000000 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_0__MATCH_FOUND___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_0__DONE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_0__MSDU_CNT___M 0x0FFFFFF0 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_0__MSDU_CNT___S 4 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_0__MATCH_FOUND___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_0__MATCH_FOUND___S 1 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_0__DONE___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_0__DONE___S 0 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_0___M 0x0FFFFFF3 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_0___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_1 (0x00A951AC) +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_1___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_1___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_1__MSDU_BYTE_CNT___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_1__MSDU_BYTE_CNT___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_1__MSDU_BYTE_CNT___S 0 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_1___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_1___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_2 (0x00A951B0) +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_2___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_2___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_2__TIMESTAMP___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_2__TIMESTAMP___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_2__TIMESTAMP___S 0 +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_2___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_ADDR_SEARCH_CACHE_RESPONSE_IX_2___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_ASE_GST_BASE_ADDR_LOW (0x00A951B4) +#define WMAC0_RXOLE_RXOLE_R0_ASE_GST_BASE_ADDR_LOW___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_ASE_GST_BASE_ADDR_LOW___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_ASE_GST_BASE_ADDR_LOW__VAL___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_ASE_GST_BASE_ADDR_LOW__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_ASE_GST_BASE_ADDR_LOW__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R0_ASE_GST_BASE_ADDR_LOW___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_ASE_GST_BASE_ADDR_LOW___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_ASE_GST_BASE_ADDR_HIGH (0x00A951B8) +#define WMAC0_RXOLE_RXOLE_R0_ASE_GST_BASE_ADDR_HIGH___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_ASE_GST_BASE_ADDR_HIGH___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_ASE_GST_BASE_ADDR_HIGH__VAL___POR 0x00 +#define WMAC0_RXOLE_RXOLE_R0_ASE_GST_BASE_ADDR_HIGH__VAL___M 0x000000FF +#define WMAC0_RXOLE_RXOLE_R0_ASE_GST_BASE_ADDR_HIGH__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R0_ASE_GST_BASE_ADDR_HIGH___M 0x000000FF +#define WMAC0_RXOLE_RXOLE_R0_ASE_GST_BASE_ADDR_HIGH___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_ASE_GST_SIZE (0x00A951BC) +#define WMAC0_RXOLE_RXOLE_R0_ASE_GST_SIZE___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_ASE_GST_SIZE___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_ASE_GST_SIZE__VAL___POR 0x00000 +#define WMAC0_RXOLE_RXOLE_R0_ASE_GST_SIZE__VAL___M 0x000FFFFF +#define WMAC0_RXOLE_RXOLE_R0_ASE_GST_SIZE__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R0_ASE_GST_SIZE___M 0x000FFFFF +#define WMAC0_RXOLE_RXOLE_R0_ASE_GST_SIZE___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL (0x00A951C0) +#define WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL___POR 0x00003806 +#define WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__TIMEOUT_THRESH___POR 0x0000 +#define WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__CACHE_CMD_READ_BYPASS_EN___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__CACHE_WRITE_BACK_FIX_EN___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__CACHE_ONLY_ENTRY_CMD_FIX_EN___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__CACHE_FAILURES_ENABLE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__CACHE_DISABLE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__SEARCH_SWAP___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__MAX_SEARCH___POR 0x06 +#define WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__TIMEOUT_THRESH___M 0xFFFF0000 +#define WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__TIMEOUT_THRESH___S 16 +#define WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__CACHE_CMD_READ_BYPASS_EN___M 0x00002000 +#define WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__CACHE_CMD_READ_BYPASS_EN___S 13 +#define WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__CACHE_WRITE_BACK_FIX_EN___M 0x00001000 +#define WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__CACHE_WRITE_BACK_FIX_EN___S 12 +#define WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__CACHE_ONLY_ENTRY_CMD_FIX_EN___M 0x00000800 +#define WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__CACHE_ONLY_ENTRY_CMD_FIX_EN___S 11 +#define WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__CACHE_FAILURES_ENABLE___M 0x00000400 +#define WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__CACHE_FAILURES_ENABLE___S 10 +#define WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__CACHE_DISABLE___M 0x00000200 +#define WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__CACHE_DISABLE___S 9 +#define WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__SEARCH_SWAP___M 0x00000100 +#define WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__SEARCH_SWAP___S 8 +#define WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__MAX_SEARCH___M 0x000000FF +#define WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL__MAX_SEARCH___S 0 +#define WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL___M 0xFFFF3FFF +#define WMAC0_RXOLE_RXOLE_R0_ASE_SEARCH_CTRL___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_ASE_WATCHDOG (0x00A951C4) +#define WMAC0_RXOLE_RXOLE_R0_ASE_WATCHDOG___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_ASE_WATCHDOG___POR 0x0000FFFF +#define WMAC0_RXOLE_RXOLE_R0_ASE_WATCHDOG__STATUS___POR 0x0000 +#define WMAC0_RXOLE_RXOLE_R0_ASE_WATCHDOG__LIMIT___POR 0xFFFF +#define WMAC0_RXOLE_RXOLE_R0_ASE_WATCHDOG__STATUS___M 0xFFFF0000 +#define WMAC0_RXOLE_RXOLE_R0_ASE_WATCHDOG__STATUS___S 16 +#define WMAC0_RXOLE_RXOLE_R0_ASE_WATCHDOG__LIMIT___M 0x0000FFFF +#define WMAC0_RXOLE_RXOLE_R0_ASE_WATCHDOG__LIMIT___S 0 +#define WMAC0_RXOLE_RXOLE_R0_ASE_WATCHDOG___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_ASE_WATCHDOG___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE (0x00A951C8) +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__CLK_EXTEND___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__CPU_IF_EXTEND___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__GSE_RSRVD___POR 0x000000 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__GSE_TOP___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__CACHE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__SLOTS_ARRAY_HASH___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__APP_RETURN___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__MEM_RESP2___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__MEM_RESP1___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__MEM_ISS2___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__MEM_ISS1___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__GSE_CTL___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__CLK_EXTEND___M 0x80000000 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__CLK_EXTEND___S 31 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__CPU_IF_EXTEND___M 0x40000000 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__CPU_IF_EXTEND___S 30 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__GSE_RSRVD___M 0x3FFFFE00 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__GSE_RSRVD___S 9 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__GSE_TOP___M 0x00000100 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__GSE_TOP___S 8 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__CACHE___M 0x00000080 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__CACHE___S 7 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__SLOTS_ARRAY_HASH___M 0x00000040 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__SLOTS_ARRAY_HASH___S 6 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__APP_RETURN___M 0x00000020 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__APP_RETURN___S 5 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__MEM_RESP2___M 0x00000010 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__MEM_RESP2___S 4 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__MEM_RESP1___M 0x00000008 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__MEM_RESP1___S 3 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__MEM_ISS2___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__MEM_ISS2___S 2 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__MEM_ISS1___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__MEM_ISS1___S 1 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__GSE_CTL___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE__GSE_CTL___S 0 +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_ASE_CLKGATE_DISABLE___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_ASE_WRITE_BACK_PENDING (0x00A951CC) +#define WMAC0_RXOLE_RXOLE_R0_ASE_WRITE_BACK_PENDING___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R0_ASE_WRITE_BACK_PENDING___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_ASE_WRITE_BACK_PENDING__STATUS___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_ASE_WRITE_BACK_PENDING__STATUS___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_ASE_WRITE_BACK_PENDING__STATUS___S 0 +#define WMAC0_RXOLE_RXOLE_R0_ASE_WRITE_BACK_PENDING___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_ASE_WRITE_BACK_PENDING___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_FSE_GST_BASE_ADDR_LOW (0x00A951D0) +#define WMAC0_RXOLE_RXOLE_R0_FSE_GST_BASE_ADDR_LOW___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_FSE_GST_BASE_ADDR_LOW___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_FSE_GST_BASE_ADDR_LOW__VAL___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_FSE_GST_BASE_ADDR_LOW__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_FSE_GST_BASE_ADDR_LOW__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R0_FSE_GST_BASE_ADDR_LOW___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_FSE_GST_BASE_ADDR_LOW___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_FSE_GST_BASE_ADDR_HIGH (0x00A951D4) +#define WMAC0_RXOLE_RXOLE_R0_FSE_GST_BASE_ADDR_HIGH___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_FSE_GST_BASE_ADDR_HIGH___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_FSE_GST_BASE_ADDR_HIGH__VAL___POR 0x00 +#define WMAC0_RXOLE_RXOLE_R0_FSE_GST_BASE_ADDR_HIGH__VAL___M 0x000000FF +#define WMAC0_RXOLE_RXOLE_R0_FSE_GST_BASE_ADDR_HIGH__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R0_FSE_GST_BASE_ADDR_HIGH___M 0x000000FF +#define WMAC0_RXOLE_RXOLE_R0_FSE_GST_BASE_ADDR_HIGH___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_FSE_GST_SIZE (0x00A951D8) +#define WMAC0_RXOLE_RXOLE_R0_FSE_GST_SIZE___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_FSE_GST_SIZE___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_FSE_GST_SIZE__VAL___POR 0x00000 +#define WMAC0_RXOLE_RXOLE_R0_FSE_GST_SIZE__VAL___M 0x000FFFFF +#define WMAC0_RXOLE_RXOLE_R0_FSE_GST_SIZE__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R0_FSE_GST_SIZE___M 0x000FFFFF +#define WMAC0_RXOLE_RXOLE_R0_FSE_GST_SIZE___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL (0x00A951DC) +#define WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL___POR 0x00003806 +#define WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__TIMEOUT_THRESH___POR 0x0000 +#define WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__CACHE_CMD_READ_BYPASS_EN___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__CACHE_WRITE_BACK_FIX_EN___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__CACHE_ONLY_ENTRY_CMD_FIX_EN___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__CACHE_FAILURES_ENABLE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__CACHE_DISABLE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__SEARCH_SWAP___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__MAX_SEARCH___POR 0x06 +#define WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__TIMEOUT_THRESH___M 0xFFFF0000 +#define WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__TIMEOUT_THRESH___S 16 +#define WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__CACHE_CMD_READ_BYPASS_EN___M 0x00002000 +#define WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__CACHE_CMD_READ_BYPASS_EN___S 13 +#define WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__CACHE_WRITE_BACK_FIX_EN___M 0x00001000 +#define WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__CACHE_WRITE_BACK_FIX_EN___S 12 +#define WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__CACHE_ONLY_ENTRY_CMD_FIX_EN___M 0x00000800 +#define WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__CACHE_ONLY_ENTRY_CMD_FIX_EN___S 11 +#define WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__CACHE_FAILURES_ENABLE___M 0x00000400 +#define WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__CACHE_FAILURES_ENABLE___S 10 +#define WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__CACHE_DISABLE___M 0x00000200 +#define WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__CACHE_DISABLE___S 9 +#define WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__SEARCH_SWAP___M 0x00000100 +#define WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__SEARCH_SWAP___S 8 +#define WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__MAX_SEARCH___M 0x000000FF +#define WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL__MAX_SEARCH___S 0 +#define WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL___M 0xFFFF3FFF +#define WMAC0_RXOLE_RXOLE_R0_FSE_SEARCH_CTRL___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_FSE_WATCHDOG (0x00A951E0) +#define WMAC0_RXOLE_RXOLE_R0_FSE_WATCHDOG___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_FSE_WATCHDOG___POR 0x0000FFFF +#define WMAC0_RXOLE_RXOLE_R0_FSE_WATCHDOG__STATUS___POR 0x0000 +#define WMAC0_RXOLE_RXOLE_R0_FSE_WATCHDOG__LIMIT___POR 0xFFFF +#define WMAC0_RXOLE_RXOLE_R0_FSE_WATCHDOG__STATUS___M 0xFFFF0000 +#define WMAC0_RXOLE_RXOLE_R0_FSE_WATCHDOG__STATUS___S 16 +#define WMAC0_RXOLE_RXOLE_R0_FSE_WATCHDOG__LIMIT___M 0x0000FFFF +#define WMAC0_RXOLE_RXOLE_R0_FSE_WATCHDOG__LIMIT___S 0 +#define WMAC0_RXOLE_RXOLE_R0_FSE_WATCHDOG___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_FSE_WATCHDOG___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE (0x00A951E4) +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__CLK_EXTEND___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__CPU_IF_EXTEND___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__GSE_RSRVD___POR 0x000000 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__GSE_TOP___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__CACHE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__SLOTS_ARRAY_HASH___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__APP_RETURN___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__MEM_RESP2___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__MEM_RESP1___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__MEM_ISS2___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__MEM_ISS1___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__GSE_CTL___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__CLK_EXTEND___M 0x80000000 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__CLK_EXTEND___S 31 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__CPU_IF_EXTEND___M 0x40000000 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__CPU_IF_EXTEND___S 30 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__GSE_RSRVD___M 0x3FFFFE00 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__GSE_RSRVD___S 9 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__GSE_TOP___M 0x00000100 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__GSE_TOP___S 8 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__CACHE___M 0x00000080 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__CACHE___S 7 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__SLOTS_ARRAY_HASH___M 0x00000040 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__SLOTS_ARRAY_HASH___S 6 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__APP_RETURN___M 0x00000020 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__APP_RETURN___S 5 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__MEM_RESP2___M 0x00000010 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__MEM_RESP2___S 4 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__MEM_RESP1___M 0x00000008 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__MEM_RESP1___S 3 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__MEM_ISS2___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__MEM_ISS2___S 2 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__MEM_ISS1___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__MEM_ISS1___S 1 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__GSE_CTL___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE__GSE_CTL___S 0 +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R0_FSE_CLKGATE_DISABLE___S 0 + +#define WMAC0_RXOLE_RXOLE_R0_FSE_WRITE_BACK_PENDING (0x00A951E8) +#define WMAC0_RXOLE_RXOLE_R0_FSE_WRITE_BACK_PENDING___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R0_FSE_WRITE_BACK_PENDING___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R0_FSE_WRITE_BACK_PENDING__STATUS___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R0_FSE_WRITE_BACK_PENDING__STATUS___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_FSE_WRITE_BACK_PENDING__STATUS___S 0 +#define WMAC0_RXOLE_RXOLE_R0_FSE_WRITE_BACK_PENDING___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R0_FSE_WRITE_BACK_PENDING___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL (0x00A96000) +#define WMAC0_RXOLE_RXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL___POR 0x7FFE0002 +#define WMAC0_RXOLE_RXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___POR 0x3FFF +#define WMAC0_RXOLE_RXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___POR 0x0000 +#define WMAC0_RXOLE_RXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___POR 0x1 +#define WMAC0_RXOLE_RXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___M 0xFFFE0000 +#define WMAC0_RXOLE_RXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___S 17 +#define WMAC0_RXOLE_RXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___M 0x0001FFFC +#define WMAC0_RXOLE_RXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___S 2 +#define WMAC0_RXOLE_RXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___S 1 +#define WMAC0_RXOLE_RXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___S 0 +#define WMAC0_RXOLE_RXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL (0x00A96004) +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__SELECT_FSE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__SELECT_ASE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__SELECT_CCE___POR 0x00 +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__SELECT_PARSER___POR 0x00 +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__SELECT_CORE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE___M 0x80000000 +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE___S 31 +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__SELECT_FSE___M 0x003C0000 +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__SELECT_FSE___S 18 +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__SELECT_ASE___M 0x0003C000 +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__SELECT_ASE___S 14 +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__SELECT_CCE___M 0x00003E00 +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__SELECT_CCE___S 9 +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__SELECT_PARSER___M 0x000001F0 +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__SELECT_PARSER___S 4 +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__SELECT_CORE___M 0x0000000F +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL__SELECT_CORE___S 0 +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL___M 0x803FFFFF +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_CTRL___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_LOWER (0x00A96008) +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_LOWER___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_LOWER___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_LOWER__VALUE___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_LOWER__VALUE___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_LOWER__VALUE___S 0 +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_LOWER___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_LOWER___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_UPPER (0x00A9600C) +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_UPPER___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_UPPER___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_UPPER__VALUE___POR 0x00 +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_UPPER__VALUE___M 0x000000FF +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_UPPER__VALUE___S 0 +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_UPPER___M 0x000000FF +#define WMAC0_RXOLE_RXOLE_R1_TESTBUS_UPPER___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_END_OF_TEST_CHECK (0x00A96010) +#define WMAC0_RXOLE_RXOLE_R1_END_OF_TEST_CHECK___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R1_END_OF_TEST_CHECK___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_END_OF_TEST_CHECK__ON___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_END_OF_TEST_CHECK__ON___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R1_END_OF_TEST_CHECK__ON___S 0 +#define WMAC0_RXOLE_RXOLE_R1_END_OF_TEST_CHECK___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R1_END_OF_TEST_CHECK___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_INVALID_APB_ACC_ADR (0x00A96014) +#define WMAC0_RXOLE_RXOLE_R1_INVALID_APB_ACC_ADR___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_INVALID_APB_ACC_ADR___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_INVALID_APB_ACC_ADR__VALUE___POR 0x00000 +#define WMAC0_RXOLE_RXOLE_R1_INVALID_APB_ACC_ADR__VALUE___M 0x0001FFFF +#define WMAC0_RXOLE_RXOLE_R1_INVALID_APB_ACC_ADR__VALUE___S 0 +#define WMAC0_RXOLE_RXOLE_R1_INVALID_APB_ACC_ADR___M 0x0001FFFF +#define WMAC0_RXOLE_RXOLE_R1_INVALID_APB_ACC_ADR___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_0 (0x00A96018) +#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_0___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_0___POR 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_0__MASK___POR 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_0__MASK___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_0__MASK___S 0 +#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_0___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_0___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_1 (0x00A9601C) +#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_1___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_1___POR 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_1__MASK___POR 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_1__MASK___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_1__MASK___S 0 +#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_1___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_1___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_2 (0x00A96020) +#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_2___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_2___POR 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_2__MASK___POR 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_2__MASK___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_2__MASK___S 0 +#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_2___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_2___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_3 (0x00A96024) +#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_3___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_3___POR 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_3__MASK___POR 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_3__MASK___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_3__MASK___S 0 +#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_3___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_EVENTMASK_IX_3___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_SM_STATES (0x00A96028) +#define WMAC0_RXOLE_RXOLE_R1_SM_STATES___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_SM_STATES___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_SM_STATES__MSDU_PARSE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_SM_STATES__SFM_READ___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_SM_STATES__USER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_SM_STATES__PUSH_PARSER___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_SM_STATES__CORE___POR 0x00 +#define WMAC0_RXOLE_RXOLE_R1_SM_STATES__MSDU_PARSE___M 0x00001800 +#define WMAC0_RXOLE_RXOLE_R1_SM_STATES__MSDU_PARSE___S 11 +#define WMAC0_RXOLE_RXOLE_R1_SM_STATES__SFM_READ___M 0x00000400 +#define WMAC0_RXOLE_RXOLE_R1_SM_STATES__SFM_READ___S 10 +#define WMAC0_RXOLE_RXOLE_R1_SM_STATES__USER___M 0x00000300 +#define WMAC0_RXOLE_RXOLE_R1_SM_STATES__USER___S 8 +#define WMAC0_RXOLE_RXOLE_R1_SM_STATES__PUSH_PARSER___M 0x000000E0 +#define WMAC0_RXOLE_RXOLE_R1_SM_STATES__PUSH_PARSER___S 5 +#define WMAC0_RXOLE_RXOLE_R1_SM_STATES__CORE___M 0x0000001F +#define WMAC0_RXOLE_RXOLE_R1_SM_STATES__CORE___S 0 +#define WMAC0_RXOLE_RXOLE_R1_SM_STATES___M 0x00001FFF +#define WMAC0_RXOLE_RXOLE_R1_SM_STATES___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_0 (0x00A9602C) +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_0___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_0___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_0__COUNT___POR 0x0000 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_0__ENABLE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_0__COUNT___M 0x0001FFFE +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_0__COUNT___S 1 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_0__ENABLE___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_0__ENABLE___S 0 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_0___M 0x0001FFFF +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_0___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_1 (0x00A96030) +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_1___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_1___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_1__SUPER_RULE___POR 0x00 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_1__COUNT___POR 0x0000 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_1__ENABLE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_1__SUPER_RULE___M 0x007E0000 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_1__SUPER_RULE___S 17 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_1__COUNT___M 0x0001FFFE +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_1__COUNT___S 1 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_1__ENABLE___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_1__ENABLE___S 0 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_1___M 0x007FFFFF +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_1___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_2 (0x00A96034) +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_2___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_2___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_2__SUPER_RULE___POR 0x00 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_2__COUNT___POR 0x0000 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_2__ENABLE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_2__SUPER_RULE___M 0x007E0000 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_2__SUPER_RULE___S 17 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_2__COUNT___M 0x0001FFFE +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_2__COUNT___S 1 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_2__ENABLE___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_2__ENABLE___S 0 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_2___M 0x007FFFFF +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_2___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_3 (0x00A96038) +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_3___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_3___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_3__SUPER_RULE___POR 0x00 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_3__COUNT___POR 0x0000 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_3__ENABLE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_3__SUPER_RULE___M 0x007E0000 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_3__SUPER_RULE___S 17 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_3__COUNT___M 0x0001FFFE +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_3__COUNT___S 1 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_3__ENABLE___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_3__ENABLE___S 0 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_3___M 0x007FFFFF +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_3___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_4 (0x00A9603C) +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_4___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_4___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_4__SUPER_RULE___POR 0x00 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_4__COUNT___POR 0x0000 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_4__ENABLE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_4__SUPER_RULE___M 0x007E0000 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_4__SUPER_RULE___S 17 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_4__COUNT___M 0x0001FFFE +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_4__COUNT___S 1 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_4__ENABLE___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_4__ENABLE___S 0 +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_4___M 0x007FFFFF +#define WMAC0_RXOLE_RXOLE_R1_DROP_COUNTER_IX_4___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_ASE_END_OF_TEST_CHECK (0x00A96040) +#define WMAC0_RXOLE_RXOLE_R1_ASE_END_OF_TEST_CHECK___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R1_ASE_END_OF_TEST_CHECK___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_ASE_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R1_ASE_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_END_OF_TEST_CHECK___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R1_ASE_END_OF_TEST_CHECK___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CLEAR_COUNTERS (0x00A96044) +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CLEAR_COUNTERS___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CLEAR_COUNTERS___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CLEAR_COUNTERS__EN___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CLEAR_COUNTERS__EN___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CLEAR_COUNTERS__EN___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CLEAR_COUNTERS___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CLEAR_COUNTERS___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER (0x00A96048) +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER__VAL___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER (0x00A9604C) +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER__VAL___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER (0x00A96050) +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER__PEAK___POR 0x000 +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER__CURR___POR 0x000 +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER__PEAK___M 0x000FFC00 +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER__PEAK___S 10 +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER__CURR___M 0x000003FF +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER__CURR___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER___M 0x000FFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_SEARCH_STAT_COUNTER (0x00A96054) +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_SEARCH_STAT_COUNTER___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_SEARCH_STAT_COUNTER___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__SQUARE_OCCUPANCY___POR 0x0000 +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__PEAK_NUM_SEARCH_PENDING___POR 0x00 +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__NUM_SEARCH_PENDING___POR 0x00 +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__SQUARE_OCCUPANCY___M 0x03FFFC00 +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__SQUARE_OCCUPANCY___S 10 +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__PEAK_NUM_SEARCH_PENDING___M 0x000003E0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__PEAK_NUM_SEARCH_PENDING___S 5 +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__NUM_SEARCH_PENDING___M 0x0000001F +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_SEARCH_STAT_COUNTER__NUM_SEARCH_PENDING___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_SEARCH_STAT_COUNTER___M 0x03FFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_DEBUG_SEARCH_STAT_COUNTER___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES (0x00A96058) +#define WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__GSE_CTRL_STATE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__CACHE_CHK_STATE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__MEM_ISS1_STATE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__MEM_ISS2_STATE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__MEM_RESP1_STATE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__MEM_RESP2_STATE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__APP_RETURN_STATE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__GSE_CTRL_STATE___M 0x00300000 +#define WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__GSE_CTRL_STATE___S 20 +#define WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__CACHE_CHK_STATE___M 0x000C0000 +#define WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__CACHE_CHK_STATE___S 18 +#define WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__MEM_ISS1_STATE___M 0x00030000 +#define WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__MEM_ISS1_STATE___S 16 +#define WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__MEM_ISS2_STATE___M 0x0000C000 +#define WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__MEM_ISS2_STATE___S 14 +#define WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__MEM_RESP1_STATE___M 0x00003800 +#define WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__MEM_RESP1_STATE___S 11 +#define WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__MEM_RESP2_STATE___M 0x00000700 +#define WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__MEM_RESP2_STATE___S 8 +#define WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__APP_RETURN_STATE___M 0x0000000F +#define WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES__APP_RETURN_STATE___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES___M 0x003FFF0F +#define WMAC0_RXOLE_RXOLE_R1_ASE_SM_STATES___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG (0x00A9605C) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG__READ_IDX___POR 0x000 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG__READ_IDX___M 0x000003FF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG__READ_IDX___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG___M 0x000003FF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_STATS (0x00A96060) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_STATS___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_STATS___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_STATS__GST_IDX___POR 0x00000 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_STATS__CACHE_ONLY___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_STATS__DIRTY___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_STATS__VALID___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_STATS__GST_IDX___M 0x007FFFF8 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_STATS__GST_IDX___S 3 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_STATS__CACHE_ONLY___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_STATS__CACHE_ONLY___S 2 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_STATS__DIRTY___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_STATS__DIRTY___S 1 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_STATS__VALID___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_STATS__VALID___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_STATS___M 0x007FFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_STATS___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_n(n) (0x00A96064+0x4*(n)) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_n_nMIN 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_n_nMAX 31 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_n_ELEM 32 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_n___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_n___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_n__VAL___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_n__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_n__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_n___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_n___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_0 (0x00A96064) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_0___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_0__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_0__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_1 (0x00A96068) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_1___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_1__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_1__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_2 (0x00A9606C) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_2___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_2__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_2__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_3 (0x00A96070) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_3___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_3__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_3__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_4 (0x00A96074) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_4___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_4__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_4__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_5 (0x00A96078) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_5___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_5__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_5__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_6 (0x00A9607C) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_6___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_6__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_6__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_7 (0x00A96080) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_7___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_7__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_7__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_8 (0x00A96084) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_8___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_8__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_8__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_9 (0x00A96088) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_9___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_9__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_9__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_10 (0x00A9608C) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_10___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_10__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_10__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_11 (0x00A96090) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_11___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_11__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_11__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_12 (0x00A96094) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_12___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_12__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_12__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_13 (0x00A96098) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_13___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_13__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_13__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_14 (0x00A9609C) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_14___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_14__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_14__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_15 (0x00A960A0) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_15___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_15__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_15__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_16 (0x00A960A4) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_16___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_16__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_16__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_17 (0x00A960A8) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_17___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_17__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_17__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_18 (0x00A960AC) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_18___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_18__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_18__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_19 (0x00A960B0) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_19___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_19__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_19__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_20 (0x00A960B4) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_20___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_20__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_20__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_21 (0x00A960B8) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_21___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_21__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_21__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_22 (0x00A960BC) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_22___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_22__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_22__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_23 (0x00A960C0) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_23___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_23__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_23__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_24 (0x00A960C4) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_24___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_24__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_24__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_25 (0x00A960C8) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_25___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_25__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_25__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_26 (0x00A960CC) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_26___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_26__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_26__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_27 (0x00A960D0) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_27___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_27__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_27__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_28 (0x00A960D4) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_28___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_28__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_28__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_29 (0x00A960D8) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_29___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_29__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_29__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_30 (0x00A960DC) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_30___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_30__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_30__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_31 (0x00A960E0) +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_31___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_31__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_ASE_CACHE_DEBUG_ENTRY_31__VAL___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_FSE_END_OF_TEST_CHECK (0x00A960E4) +#define WMAC0_RXOLE_RXOLE_R1_FSE_END_OF_TEST_CHECK___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R1_FSE_END_OF_TEST_CHECK___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_FSE_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R1_FSE_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_END_OF_TEST_CHECK___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R1_FSE_END_OF_TEST_CHECK___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CLEAR_COUNTERS (0x00A960E8) +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CLEAR_COUNTERS___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CLEAR_COUNTERS___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CLEAR_COUNTERS__EN___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CLEAR_COUNTERS__EN___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CLEAR_COUNTERS__EN___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CLEAR_COUNTERS___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CLEAR_COUNTERS___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER (0x00A960EC) +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER__VAL___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_NUM_CACHE_HITS_COUNTER___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER (0x00A960F0) +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER__VAL___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_NUM_SEARCHES_COUNTER___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER (0x00A960F4) +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER__PEAK___POR 0x000 +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER__CURR___POR 0x000 +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER__PEAK___M 0x000FFC00 +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER__PEAK___S 10 +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER__CURR___M 0x000003FF +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER__CURR___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER___M 0x000FFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_CACHE_OCCUPANCY_COUNTER___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_SEARCH_STAT_COUNTER (0x00A960F8) +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_SEARCH_STAT_COUNTER___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_SEARCH_STAT_COUNTER___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_SEARCH_STAT_COUNTER__SQUARE_OCCUPANCY___POR 0x0000 +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_SEARCH_STAT_COUNTER__PEAK_NUM_SEARCH_PENDING___POR 0x00 +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_SEARCH_STAT_COUNTER__NUM_SEARCH_PENDING___POR 0x00 +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_SEARCH_STAT_COUNTER__SQUARE_OCCUPANCY___M 0x03FFFC00 +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_SEARCH_STAT_COUNTER__SQUARE_OCCUPANCY___S 10 +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_SEARCH_STAT_COUNTER__PEAK_NUM_SEARCH_PENDING___M 0x000003E0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_SEARCH_STAT_COUNTER__PEAK_NUM_SEARCH_PENDING___S 5 +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_SEARCH_STAT_COUNTER__NUM_SEARCH_PENDING___M 0x0000001F +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_SEARCH_STAT_COUNTER__NUM_SEARCH_PENDING___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_SEARCH_STAT_COUNTER___M 0x03FFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_DEBUG_SEARCH_STAT_COUNTER___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES (0x00A960FC) +#define WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__GSE_CTRL_STATE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__CACHE_CHK_STATE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__MEM_ISS1_STATE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__MEM_ISS2_STATE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__MEM_RESP1_STATE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__MEM_RESP2_STATE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__APP_RETURN_STATE___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__GSE_CTRL_STATE___M 0x00300000 +#define WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__GSE_CTRL_STATE___S 20 +#define WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__CACHE_CHK_STATE___M 0x000C0000 +#define WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__CACHE_CHK_STATE___S 18 +#define WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__MEM_ISS1_STATE___M 0x00030000 +#define WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__MEM_ISS1_STATE___S 16 +#define WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__MEM_ISS2_STATE___M 0x0000C000 +#define WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__MEM_ISS2_STATE___S 14 +#define WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__MEM_RESP1_STATE___M 0x00003800 +#define WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__MEM_RESP1_STATE___S 11 +#define WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__MEM_RESP2_STATE___M 0x00000700 +#define WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__MEM_RESP2_STATE___S 8 +#define WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__APP_RETURN_STATE___M 0x0000000F +#define WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES__APP_RETURN_STATE___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES___M 0x003FFF0F +#define WMAC0_RXOLE_RXOLE_R1_FSE_SM_STATES___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG (0x00A96100) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG___RWC QCSR_REG_RW +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG__READ_IDX___POR 0x000 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG__READ_IDX___M 0x000003FF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG__READ_IDX___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG___M 0x000003FF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_STATS (0x00A96104) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_STATS___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_STATS___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_STATS__GST_IDX___POR 0x00000 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_STATS__CACHE_ONLY___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_STATS__DIRTY___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_STATS__VALID___POR 0x0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_STATS__GST_IDX___M 0x007FFFF8 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_STATS__GST_IDX___S 3 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_STATS__CACHE_ONLY___M 0x00000004 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_STATS__CACHE_ONLY___S 2 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_STATS__DIRTY___M 0x00000002 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_STATS__DIRTY___S 1 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_STATS__VALID___M 0x00000001 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_STATS__VALID___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_STATS___M 0x007FFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_STATS___S 0 + +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_n(n) (0x00A96108+0x4*(n)) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_n_nMIN 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_n_nMAX 31 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_n_ELEM 32 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_n___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_n___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_n__VAL___POR 0x00000000 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_n__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_n__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_n___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_n___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_0 (0x00A96108) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_0___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_0__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_0__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_1 (0x00A9610C) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_1___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_1__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_1__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_2 (0x00A96110) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_2___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_2__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_2__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_3 (0x00A96114) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_3___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_3__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_3__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_4 (0x00A96118) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_4___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_4__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_4__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_5 (0x00A9611C) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_5___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_5__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_5__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_6 (0x00A96120) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_6___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_6__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_6__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_7 (0x00A96124) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_7___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_7__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_7__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_8 (0x00A96128) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_8___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_8__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_8__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_9 (0x00A9612C) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_9___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_9__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_9__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_10 (0x00A96130) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_10___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_10__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_10__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_11 (0x00A96134) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_11___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_11__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_11__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_12 (0x00A96138) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_12___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_12__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_12__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_13 (0x00A9613C) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_13___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_13__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_13__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_14 (0x00A96140) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_14___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_14__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_14__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_15 (0x00A96144) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_15___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_15__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_15__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_16 (0x00A96148) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_16___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_16__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_16__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_17 (0x00A9614C) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_17___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_17__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_17__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_18 (0x00A96150) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_18___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_18__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_18__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_19 (0x00A96154) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_19___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_19__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_19__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_20 (0x00A96158) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_20___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_20__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_20__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_21 (0x00A9615C) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_21___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_21__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_21__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_22 (0x00A96160) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_22___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_22__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_22__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_23 (0x00A96164) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_23___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_23__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_23__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_24 (0x00A96168) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_24___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_24__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_24__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_25 (0x00A9616C) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_25___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_25__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_25__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_26 (0x00A96170) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_26___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_26__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_26__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_27 (0x00A96174) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_27___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_27__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_27__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_28 (0x00A96178) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_28___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_28__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_28__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_29 (0x00A9617C) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_29___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_29__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_29__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_30 (0x00A96180) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_30___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_30__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_30__VAL___S 0 +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_31 (0x00A96184) +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_31___RWC QCSR_REG_RO +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_31__VAL___M 0xFFFFFFFF +#define WMAC0_RXOLE_RXOLE_R1_FSE_CACHE_DEBUG_ENTRY_31__VAL___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0 (0x00A98000) +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0___RWC QCSR_REG_RO +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_LEN___POR 0x000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_ID___POR 0x00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_LEN___M 0x000FFF00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_LEN___S 8 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_ID___M 0x000000FF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_ID___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0___M 0x000FFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1 (0x00A98004) +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1___RWC QCSR_REG_RO +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1___POR 0x0000002B +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_LEN___POR 0x000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_ID___POR 0x2B +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_LEN___M 0x000FFF00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_LEN___S 8 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_ID___M 0x000000FF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_ID___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1___M 0x000FFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2 (0x00A98008) +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2___RWC QCSR_REG_RO +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2___POR 0x0000003C +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_LEN___POR 0x000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_ID___POR 0x3C +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_LEN___M 0x000FFF00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_LEN___S 8 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_ID___M 0x000000FF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_ID___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2___M 0x000FFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3 (0x00A9800C) +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3___RWC QCSR_REG_RO +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3___POR 0x00000033 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_LEN___POR 0x000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_ID___POR 0x33 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_LEN___M 0x000FFF00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_LEN___S 8 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_ID___M 0x000000FF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_ID___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3___M 0x000FFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4 (0x00A98010) +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4___RWC QCSR_REG_RO +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4___POR 0x00000887 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_LEN___POR 0x008 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_ID___POR 0x87 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_LEN___M 0x000FFF00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_LEN___S 8 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_ID___M 0x000000FF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_ID___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4___M 0x000FFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5 (0x00A98014) +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5___RWC QCSR_REG_RO +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5___POR 0x0000082C +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_LEN___POR 0x008 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_ID___POR 0x2C +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_LEN___M 0x000FFF00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_LEN___S 8 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_ID___M 0x000000FF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_ID___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5___M 0x000FFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6 (0x00A98018) +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6___RWC QCSR_REG_RW +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_LEN___POR 0x000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_ID___POR 0x00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_LEN___M 0x000FFF00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_LEN___S 8 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_ID___M 0x000000FF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_ID___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6___M 0x000FFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7 (0x00A9801C) +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7___RWC QCSR_REG_RW +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_LEN___POR 0x000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_ID___POR 0x00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_LEN___M 0x000FFF00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_LEN___S 8 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_ID___M 0x000000FF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_ID___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7___M 0x000FFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8 (0x00A98020) +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8___RWC QCSR_REG_RW +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_LEN___POR 0x000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_ID___POR 0x00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_LEN___M 0x000FFF00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_LEN___S 8 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_ID___M 0x000000FF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_ID___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8___M 0x000FFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9 (0x00A98024) +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9___RWC QCSR_REG_RW +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_LEN___POR 0x000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_ID___POR 0x00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_LEN___M 0x000FFF00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_LEN___S 8 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_ID___M 0x000000FF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_ID___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9___M 0x000FFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10 (0x00A98028) +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10___RWC QCSR_REG_RW +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_LEN___POR 0x000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_ID___POR 0x00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_LEN___M 0x000FFF00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_LEN___S 8 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_ID___M 0x000000FF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_ID___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10___M 0x000FFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11 (0x00A9802C) +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11___RWC QCSR_REG_RW +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_LEN___POR 0x000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_ID___POR 0x00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_LEN___M 0x000FFF00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_LEN___S 8 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_ID___M 0x000000FF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_ID___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11___M 0x000FFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12 (0x00A98030) +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12___RWC QCSR_REG_RW +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_LEN___POR 0x000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_ID___POR 0x00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_LEN___M 0x000FFF00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_LEN___S 8 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_ID___M 0x000000FF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_ID___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12___M 0x000FFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13 (0x00A98034) +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13___RWC QCSR_REG_RW +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_LEN___POR 0x000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_ID___POR 0x00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_LEN___M 0x000FFF00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_LEN___S 8 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_ID___M 0x000000FF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_ID___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13___M 0x000FFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14 (0x00A98038) +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14___RWC QCSR_REG_RW +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_LEN___POR 0x000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_ID___POR 0x00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_LEN___M 0x000FFF00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_LEN___S 8 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_ID___M 0x000000FF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_ID___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14___M 0x000FFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15 (0x00A9803C) +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15___RWC QCSR_REG_RW +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_LEN___POR 0x000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_ID___POR 0x00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_LEN___M 0x000FFF00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_LEN___S 8 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_ID___M 0x000000FF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_ID___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15___M 0x000FFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN (0x00A98040) +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN___RWC QCSR_REG_RW +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS1___POR 0x0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS0___POR 0x0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS1___M 0x000000F0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS1___S 4 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS0___M 0x0000000F +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS0___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN___M 0x000000FF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0 (0x00A98044) +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0___RWC QCSR_REG_RW +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL3___POR 0x00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL2___POR 0x00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL1___POR 0x00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL0___POR 0x00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL3___M 0xFF000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL3___S 24 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL2___M 0x00FF0000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL2___S 16 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL1___M 0x0000FF00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL1___S 8 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL0___M 0x000000FF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL0___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0___M 0xFFFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1 (0x00A98048) +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1___RWC QCSR_REG_RW +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL7___POR 0x00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL6___POR 0x00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL5___POR 0x00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL4___POR 0x00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL7___M 0xFF000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL7___S 24 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL6___M 0x00FF0000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL6___S 16 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL5___M 0x0000FF00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL5___S 8 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL4___M 0x000000FF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL4___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1___M 0xFFFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG (0x00A9804C) +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG___RWC QCSR_REG_RW +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG___POR 0x00000080 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG__USE_AH_FOR_FLOW_ID___POR 0x0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG__SPI_FROM_AH_OR_ESP___POR 0x0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG__L4_BYTES_EXCEEDED_256___POR 0x0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG__L3_BYTES_EXCEEDED_256___POR 0x0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG__EXT_HEADER_BYTES___POR 0x80 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG__USE_AH_FOR_FLOW_ID___M 0x00000800 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG__USE_AH_FOR_FLOW_ID___S 11 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG__SPI_FROM_AH_OR_ESP___M 0x00000400 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG__SPI_FROM_AH_OR_ESP___S 10 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG__L4_BYTES_EXCEEDED_256___M 0x00000200 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG__L4_BYTES_EXCEEDED_256___S 9 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG__L3_BYTES_EXCEEDED_256___M 0x00000100 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG__L3_BYTES_EXCEEDED_256___S 8 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG__EXT_HEADER_BYTES___M 0x000000FF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG__EXT_HEADER_BYTES___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG___M 0x00000FFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_IPV6_CONFIG___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_COMMIT_TLV_CONFIG (0x00A98050) +#define WMAC0_A_RXOLE_PARSER_CP_R0_COMMIT_TLV_CONFIG___RWC QCSR_REG_RO +#define WMAC0_A_RXOLE_PARSER_CP_R0_COMMIT_TLV_CONFIG___POR 0x00010040 +#define WMAC0_A_RXOLE_PARSER_CP_R0_COMMIT_TLV_CONFIG__COMMIT_DONE_NUM___POR 0x100 +#define WMAC0_A_RXOLE_PARSER_CP_R0_COMMIT_TLV_CONFIG__COMMIT_NUM___POR 0x40 +#define WMAC0_A_RXOLE_PARSER_CP_R0_COMMIT_TLV_CONFIG__COMMIT_DONE_NUM___M 0x0001FF00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_COMMIT_TLV_CONFIG__COMMIT_DONE_NUM___S 8 +#define WMAC0_A_RXOLE_PARSER_CP_R0_COMMIT_TLV_CONFIG__COMMIT_NUM___M 0x000000FF +#define WMAC0_A_RXOLE_PARSER_CP_R0_COMMIT_TLV_CONFIG__COMMIT_NUM___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_COMMIT_TLV_CONFIG___M 0x0001FFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_COMMIT_TLV_CONFIG___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE (0x00A98054) +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE___RWC QCSR_REG_RW +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CLK_EXTEND___POR 0x0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___POR 0x0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CP_RSRVD___POR 0x000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CCE_SM___POR 0x0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__NWIFI___POR 0x0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__ETH___POR 0x0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__AMSDU_11AH___POR 0x0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__AMSDU_11AC___POR 0x0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__WIFI___POR 0x0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CORE___POR 0x0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__APB___POR 0x0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CLK_EXTEND___M 0x80000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CLK_EXTEND___S 31 +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___M 0x40000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___S 30 +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CP_RSRVD___M 0x3FFFFF00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CP_RSRVD___S 8 +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CCE_SM___M 0x00000080 +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CCE_SM___S 7 +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__NWIFI___M 0x00000040 +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__NWIFI___S 6 +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__ETH___M 0x00000020 +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__ETH___S 5 +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__AMSDU_11AH___M 0x00000010 +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__AMSDU_11AH___S 4 +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__AMSDU_11AC___M 0x00000008 +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__AMSDU_11AC___S 3 +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__WIFI___M 0x00000004 +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__WIFI___S 2 +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CORE___M 0x00000002 +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CORE___S 1 +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__APB___M 0x00000001 +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE__APB___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE___M 0xFFFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_CLKGATE_DISABLE___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_0 (0x00A98058) +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_0___RWC QCSR_REG_RW +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_0___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_0__VALUE___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_0__VALUE___M 0xFFFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_0__VALUE___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_0___M 0xFFFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_0___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_1 (0x00A9805C) +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_1___RWC QCSR_REG_RW +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_1___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_1__VALUE___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_1__VALUE___M 0xFFFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_1__VALUE___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_1___M 0xFFFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_1___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_2 (0x00A98060) +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_2___RWC QCSR_REG_RW +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_2___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_2__VALUE___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_2__VALUE___M 0xFFFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_2__VALUE___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_2___M 0xFFFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_2___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_3 (0x00A98064) +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_3___RWC QCSR_REG_RW +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_3___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_3__VALUE___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_3__VALUE___M 0xFFFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_3__VALUE___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_3___M 0xFFFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IX_3___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_0 (0x00A98068) +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_0___RWC QCSR_REG_RW +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_0___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_0__VALUE___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_0__VALUE___M 0xFFFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_0__VALUE___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_0___M 0xFFFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_0___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_1 (0x00A9806C) +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_1___RWC QCSR_REG_RW +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_1___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_1__VALUE___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_1__VALUE___M 0xFFFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_1__VALUE___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_1___M 0xFFFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_1___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_2 (0x00A98070) +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_2___RWC QCSR_REG_RW +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_2___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_2__VALUE___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_2__VALUE___M 0xFFFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_2__VALUE___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_2___M 0xFFFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_2___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_3 (0x00A98074) +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_3___RWC QCSR_REG_RW +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_3___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_3__VALUE___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_3__VALUE___M 0xFFFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_3__VALUE___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_3___M 0xFFFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_3___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_4 (0x00A98078) +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_4___RWC QCSR_REG_RW +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_4___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_4__VALUE___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_4__VALUE___M 0xFFFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_4__VALUE___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_4___M 0xFFFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_4___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_5 (0x00A9807C) +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_5___RWC QCSR_REG_RW +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_5___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_5__VALUE___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_5__VALUE___M 0xFFFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_5__VALUE___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_5___M 0xFFFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_5___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_6 (0x00A98080) +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_6___RWC QCSR_REG_RW +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_6___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_6__VALUE___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_6__VALUE___M 0xFFFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_6__VALUE___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_6___M 0xFFFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_6___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_7 (0x00A98084) +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_7___RWC QCSR_REG_RW +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_7___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_7__VALUE___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_7__VALUE___M 0xFFFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_7__VALUE___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_7___M 0xFFFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_7___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_8 (0x00A98088) +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_8___RWC QCSR_REG_RW +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_8___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_8__VALUE___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_8__VALUE___M 0xFFFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_8__VALUE___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_8___M 0xFFFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_8___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_9 (0x00A9808C) +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_9___RWC QCSR_REG_RW +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_9___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_9__VALUE___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_9__VALUE___M 0xFFFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_9__VALUE___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_9___M 0xFFFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV6_IX_9___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IPV6 (0x00A98090) +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IPV6___RWC QCSR_REG_RW +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IPV6___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IPV6__VALUE_1___POR 0x00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IPV6__VALUE_0___POR 0x00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IPV6__VALUE_1___M 0x0000FF00 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IPV6__VALUE_1___S 8 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IPV6__VALUE_0___M 0x000000FF +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IPV6__VALUE_0___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IPV6___M 0x0000FFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_TOEPLITZ_KEY_IPV4_IPV6___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG (0x00A98094) +#define WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG___RWC QCSR_REG_RW +#define WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG___POR 0x0001E110 +#define WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__REPORT_FLOW_ID_OR_HASH_3___POR 0x0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__ETH_MIN_PACKET_LEN___POR 0x003C +#define WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__TIMEOUT_EN___POR 0x0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__ENABLE_C9D1___POR 0x0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__VLAN_LLC_FOR_802_3___POR 0x1 +#define WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__IP_DA_SA_PREFIX___POR 0x0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__UDP_LITE_PARSE_EN___POR 0x0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__TPID_BITMAP_VALUE___POR 0x10 +#define WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__REPORT_FLOW_ID_OR_HASH_3___M 0x08000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__REPORT_FLOW_ID_OR_HASH_3___S 27 +#define WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__ETH_MIN_PACKET_LEN___M 0x07FFF800 +#define WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__ETH_MIN_PACKET_LEN___S 11 +#define WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__TIMEOUT_EN___M 0x00000400 +#define WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__TIMEOUT_EN___S 10 +#define WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__ENABLE_C9D1___M 0x00000200 +#define WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__ENABLE_C9D1___S 9 +#define WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__VLAN_LLC_FOR_802_3___M 0x00000100 +#define WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__VLAN_LLC_FOR_802_3___S 8 +#define WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__IP_DA_SA_PREFIX___M 0x000000C0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__IP_DA_SA_PREFIX___S 6 +#define WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__UDP_LITE_PARSE_EN___M 0x00000020 +#define WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__UDP_LITE_PARSE_EN___S 5 +#define WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__TPID_BITMAP_VALUE___M 0x0000001F +#define WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG__TPID_BITMAP_VALUE___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG___M 0x0FFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_MISC_CONFIG___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R0_WATCHDOG_TIMER (0x00A98098) +#define WMAC0_A_RXOLE_PARSER_CP_R0_WATCHDOG_TIMER___RWC QCSR_REG_RW +#define WMAC0_A_RXOLE_PARSER_CP_R0_WATCHDOG_TIMER___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_WATCHDOG_TIMER__VALUE___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R0_WATCHDOG_TIMER__ENABLE___POR 0x0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_WATCHDOG_TIMER__VALUE___M 0xFFFFFFFE +#define WMAC0_A_RXOLE_PARSER_CP_R0_WATCHDOG_TIMER__VALUE___S 1 +#define WMAC0_A_RXOLE_PARSER_CP_R0_WATCHDOG_TIMER__ENABLE___M 0x00000001 +#define WMAC0_A_RXOLE_PARSER_CP_R0_WATCHDOG_TIMER__ENABLE___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R0_WATCHDOG_TIMER___M 0xFFFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R0_WATCHDOG_TIMER___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL (0x00A99000) +#define WMAC0_A_RXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL___RWC QCSR_REG_RW +#define WMAC0_A_RXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL___POR 0x7FFE0002 +#define WMAC0_A_RXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___POR 0x3FFF +#define WMAC0_A_RXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___POR 0x0000 +#define WMAC0_A_RXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___POR 0x1 +#define WMAC0_A_RXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___POR 0x0 +#define WMAC0_A_RXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___M 0xFFFE0000 +#define WMAC0_A_RXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___S 17 +#define WMAC0_A_RXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___M 0x0001FFFC +#define WMAC0_A_RXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___S 2 +#define WMAC0_A_RXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___M 0x00000002 +#define WMAC0_A_RXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___S 1 +#define WMAC0_A_RXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___M 0x00000001 +#define WMAC0_A_RXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL___M 0xFFFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R1_SM_STATES (0x00A99004) +#define WMAC0_A_RXOLE_PARSER_CP_R1_SM_STATES___RWC QCSR_REG_RO +#define WMAC0_A_RXOLE_PARSER_CP_R1_SM_STATES___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R1_SM_STATES__MISC___POR 0x000000 +#define WMAC0_A_RXOLE_PARSER_CP_R1_SM_STATES__STATE_INFO___POR 0x00 +#define WMAC0_A_RXOLE_PARSER_CP_R1_SM_STATES__STATE_MAIN___POR 0x00 +#define WMAC0_A_RXOLE_PARSER_CP_R1_SM_STATES__MISC___M 0xFFFFFC00 +#define WMAC0_A_RXOLE_PARSER_CP_R1_SM_STATES__MISC___S 10 +#define WMAC0_A_RXOLE_PARSER_CP_R1_SM_STATES__STATE_INFO___M 0x000003E0 +#define WMAC0_A_RXOLE_PARSER_CP_R1_SM_STATES__STATE_INFO___S 5 +#define WMAC0_A_RXOLE_PARSER_CP_R1_SM_STATES__STATE_MAIN___M 0x0000001F +#define WMAC0_A_RXOLE_PARSER_CP_R1_SM_STATES__STATE_MAIN___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R1_SM_STATES___M 0xFFFFFFFF +#define WMAC0_A_RXOLE_PARSER_CP_R1_SM_STATES___S 0 + +#define WMAC0_A_RXOLE_PARSER_CP_R1_END_OF_TEST_CHECK (0x00A99008) +#define WMAC0_A_RXOLE_PARSER_CP_R1_END_OF_TEST_CHECK___RWC QCSR_REG_RW +#define WMAC0_A_RXOLE_PARSER_CP_R1_END_OF_TEST_CHECK___POR 0x00000000 +#define WMAC0_A_RXOLE_PARSER_CP_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0 +#define WMAC0_A_RXOLE_PARSER_CP_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001 +#define WMAC0_A_RXOLE_PARSER_CP_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S 0 +#define WMAC0_A_RXOLE_PARSER_CP_R1_END_OF_TEST_CHECK___M 0x00000001 +#define WMAC0_A_RXOLE_PARSER_CP_R1_END_OF_TEST_CHECK___S 0 + +#define WMAC0_CCE_CCE_R0_CONTROL_FOR_SW_PROGRAMMING (0x00A9B000) +#define WMAC0_CCE_CCE_R0_CONTROL_FOR_SW_PROGRAMMING___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_CONTROL_FOR_SW_PROGRAMMING___POR 0x00000000 +#define WMAC0_CCE_CCE_R0_CONTROL_FOR_SW_PROGRAMMING__RULES_DONE___POR 0x0 +#define WMAC0_CCE_CCE_R0_CONTROL_FOR_SW_PROGRAMMING__SW_PRG_REQ___POR 0x0 +#define WMAC0_CCE_CCE_R0_CONTROL_FOR_SW_PROGRAMMING__RULES_DONE___M 0x00000002 +#define WMAC0_CCE_CCE_R0_CONTROL_FOR_SW_PROGRAMMING__RULES_DONE___S 1 +#define WMAC0_CCE_CCE_R0_CONTROL_FOR_SW_PROGRAMMING__SW_PRG_REQ___M 0x00000001 +#define WMAC0_CCE_CCE_R0_CONTROL_FOR_SW_PROGRAMMING__SW_PRG_REQ___S 0 +#define WMAC0_CCE_CCE_R0_CONTROL_FOR_SW_PROGRAMMING___M 0x00000003 +#define WMAC0_CCE_CCE_R0_CONTROL_FOR_SW_PROGRAMMING___S 0 + +#define WMAC0_CCE_CCE_R0_ANCHOR_TYPE_PRESERVE (0x00A9B004) +#define WMAC0_CCE_CCE_R0_ANCHOR_TYPE_PRESERVE___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_ANCHOR_TYPE_PRESERVE___POR 0x00000000 +#define WMAC0_CCE_CCE_R0_ANCHOR_TYPE_PRESERVE__VALUE___POR 0x00000000 +#define WMAC0_CCE_CCE_R0_ANCHOR_TYPE_PRESERVE__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_ANCHOR_TYPE_PRESERVE__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_ANCHOR_TYPE_PRESERVE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_ANCHOR_TYPE_PRESERVE___S 0 + +#define WMAC0_CCE_CCE_R0_LAST_RULE_VALID (0x00A9B008) +#define WMAC0_CCE_CCE_R0_LAST_RULE_VALID___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_LAST_RULE_VALID___POR 0x00000000 +#define WMAC0_CCE_CCE_R0_LAST_RULE_VALID__VALUE___POR 0x00 +#define WMAC0_CCE_CCE_R0_LAST_RULE_VALID__VALUE___M 0x0000003F +#define WMAC0_CCE_CCE_R0_LAST_RULE_VALID__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_LAST_RULE_VALID___M 0x0000003F +#define WMAC0_CCE_CCE_R0_LAST_RULE_VALID___S 0 + +#define WMAC0_CCE_CCE_R0_LAST_SUPER_RULE_VALID (0x00A9B00C) +#define WMAC0_CCE_CCE_R0_LAST_SUPER_RULE_VALID___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_LAST_SUPER_RULE_VALID___POR 0x00000000 +#define WMAC0_CCE_CCE_R0_LAST_SUPER_RULE_VALID__VALUE___POR 0x00 +#define WMAC0_CCE_CCE_R0_LAST_SUPER_RULE_VALID__VALUE___M 0x0000001F +#define WMAC0_CCE_CCE_R0_LAST_SUPER_RULE_VALID__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_LAST_SUPER_RULE_VALID___M 0x0000001F +#define WMAC0_CCE_CCE_R0_LAST_SUPER_RULE_VALID___S 0 + +#define WMAC0_CCE_CCE_R0_RULE_VALIDS_IX_0 (0x00A9B010) +#define WMAC0_CCE_CCE_R0_RULE_VALIDS_IX_0___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_VALIDS_IX_0___POR 0x00000000 +#define WMAC0_CCE_CCE_R0_RULE_VALIDS_IX_0__VALUE___POR 0x00000000 +#define WMAC0_CCE_CCE_R0_RULE_VALIDS_IX_0__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_VALIDS_IX_0__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_VALIDS_IX_0___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_VALIDS_IX_0___S 0 + +#define WMAC0_CCE_CCE_R0_RULE_VALIDS_IX_1 (0x00A9B014) +#define WMAC0_CCE_CCE_R0_RULE_VALIDS_IX_1___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_VALIDS_IX_1___POR 0x00000000 +#define WMAC0_CCE_CCE_R0_RULE_VALIDS_IX_1__VALUE___POR 0x00000000 +#define WMAC0_CCE_CCE_R0_RULE_VALIDS_IX_1__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_VALIDS_IX_1__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_VALIDS_IX_1___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_VALIDS_IX_1___S 0 + +#define WMAC0_CCE_CCE_R0_SUPER_RULE_VALIDS (0x00A9B018) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_VALIDS___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_VALIDS___POR 0x00000000 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_VALIDS__VALUE___POR 0x00000000 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_VALIDS__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_VALIDS__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_VALIDS___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_VALIDS___S 0 + +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE (0x00A9B01C) +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE___POR 0x00000000 +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__CLK_EXTEND___POR 0x0 +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___POR 0x0 +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__CCE_APB___POR 0x0 +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__CCE_TOP___POR 0x0 +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__TLV_DEC_ENC___POR 0x0 +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__SW_PRG___POR 0x0 +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__DATA_BUF___POR 0x0 +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__SUPER_RULE___POR 0x0 +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__RULE_PRESERVE_MEM___POR 0x0 +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__RULE___POR 0x0 +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__CLK_EXTEND___M 0x80000000 +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__CLK_EXTEND___S 31 +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___M 0x40000000 +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___S 30 +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__CCE_APB___M 0x00000080 +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__CCE_APB___S 7 +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__CCE_TOP___M 0x00000040 +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__CCE_TOP___S 6 +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__TLV_DEC_ENC___M 0x00000020 +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__TLV_DEC_ENC___S 5 +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__SW_PRG___M 0x00000010 +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__SW_PRG___S 4 +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__DATA_BUF___M 0x00000008 +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__DATA_BUF___S 3 +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__SUPER_RULE___M 0x00000004 +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__SUPER_RULE___S 2 +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__RULE_PRESERVE_MEM___M 0x00000002 +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__RULE_PRESERVE_MEM___S 1 +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__RULE___M 0x00000001 +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE__RULE___S 0 +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE___M 0xC00000FF +#define WMAC0_CCE_CCE_R0_CLKGATE_DISABLE___S 0 + +#define WMAC0_CCE_CCE_R0_RULE_PRESERVE_RST_ANCHOR_TYPE (0x00A9B020) +#define WMAC0_CCE_CCE_R0_RULE_PRESERVE_RST_ANCHOR_TYPE___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_PRESERVE_RST_ANCHOR_TYPE___POR 0x00000000 +#define WMAC0_CCE_CCE_R0_RULE_PRESERVE_RST_ANCHOR_TYPE__VALUE___POR 0x00 +#define WMAC0_CCE_CCE_R0_RULE_PRESERVE_RST_ANCHOR_TYPE__VALUE___M 0x0000001F +#define WMAC0_CCE_CCE_R0_RULE_PRESERVE_RST_ANCHOR_TYPE__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_PRESERVE_RST_ANCHOR_TYPE___M 0x0000001F +#define WMAC0_CCE_CCE_R0_RULE_PRESERVE_RST_ANCHOR_TYPE___S 0 + +#define WMAC0_CCE_CCE_R0_WATCHDOG (0x00A9B024) +#define WMAC0_CCE_CCE_R0_WATCHDOG___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_WATCHDOG___POR 0x0000FFFF +#define WMAC0_CCE_CCE_R0_WATCHDOG__STATUS___POR 0x0000 +#define WMAC0_CCE_CCE_R0_WATCHDOG__LIMIT___POR 0xFFFF +#define WMAC0_CCE_CCE_R0_WATCHDOG__STATUS___M 0xFFFF0000 +#define WMAC0_CCE_CCE_R0_WATCHDOG__STATUS___S 16 +#define WMAC0_CCE_CCE_R0_WATCHDOG__LIMIT___M 0x0000FFFF +#define WMAC0_CCE_CCE_R0_WATCHDOG__LIMIT___S 0 +#define WMAC0_CCE_CCE_R0_WATCHDOG___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_WATCHDOG___S 0 + +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_n(n) (0x00A9B100+0x4*(n)) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_n_nMIN 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_n_nMAX 127 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_n_ELEM 128 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_n___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_n___POR 0x00000000 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_n__VALUE___POR 0x00000000 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_n__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_n__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_n___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_n___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_0 (0x00A9B100) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_0___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_0__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_0__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_1 (0x00A9B104) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_1___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_1__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_1__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_2 (0x00A9B108) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_2___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_2__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_2__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_3 (0x00A9B10C) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_3___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_3__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_3__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_4 (0x00A9B110) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_4___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_4__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_4__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_5 (0x00A9B114) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_5___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_5__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_5__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_6 (0x00A9B118) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_6___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_6__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_6__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_7 (0x00A9B11C) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_7___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_7__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_7__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_8 (0x00A9B120) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_8___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_8__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_8__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_9 (0x00A9B124) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_9___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_9__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_9__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_10 (0x00A9B128) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_10___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_10__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_10__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_11 (0x00A9B12C) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_11___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_11__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_11__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_12 (0x00A9B130) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_12___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_12__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_12__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_13 (0x00A9B134) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_13___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_13__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_13__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_14 (0x00A9B138) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_14___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_14__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_14__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_15 (0x00A9B13C) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_15___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_15__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_15__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_16 (0x00A9B140) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_16___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_16__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_16__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_17 (0x00A9B144) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_17___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_17__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_17__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_18 (0x00A9B148) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_18___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_18__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_18__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_19 (0x00A9B14C) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_19___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_19__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_19__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_20 (0x00A9B150) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_20___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_20__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_20__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_21 (0x00A9B154) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_21___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_21__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_21__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_22 (0x00A9B158) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_22___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_22__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_22__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_23 (0x00A9B15C) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_23___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_23__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_23__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_24 (0x00A9B160) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_24___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_24__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_24__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_25 (0x00A9B164) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_25___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_25__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_25__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_26 (0x00A9B168) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_26___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_26__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_26__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_27 (0x00A9B16C) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_27___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_27__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_27__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_28 (0x00A9B170) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_28___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_28__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_28__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_29 (0x00A9B174) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_29___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_29__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_29__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_30 (0x00A9B178) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_30___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_30__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_30__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_31 (0x00A9B17C) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_31___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_31__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_31__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_32 (0x00A9B180) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_32___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_32__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_32__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_33 (0x00A9B184) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_33___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_33__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_33__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_34 (0x00A9B188) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_34___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_34__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_34__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_35 (0x00A9B18C) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_35___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_35__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_35__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_36 (0x00A9B190) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_36___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_36__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_36__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_37 (0x00A9B194) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_37___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_37__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_37__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_38 (0x00A9B198) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_38___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_38__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_38__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_39 (0x00A9B19C) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_39___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_39__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_39__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_40 (0x00A9B1A0) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_40___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_40__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_40__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_41 (0x00A9B1A4) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_41___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_41__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_41__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_42 (0x00A9B1A8) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_42___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_42__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_42__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_43 (0x00A9B1AC) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_43___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_43__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_43__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_44 (0x00A9B1B0) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_44___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_44__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_44__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_45 (0x00A9B1B4) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_45___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_45__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_45__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_46 (0x00A9B1B8) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_46___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_46__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_46__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_47 (0x00A9B1BC) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_47___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_47__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_47__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_48 (0x00A9B1C0) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_48___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_48__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_48__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_49 (0x00A9B1C4) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_49___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_49__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_49__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_50 (0x00A9B1C8) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_50___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_50__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_50__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_51 (0x00A9B1CC) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_51___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_51__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_51__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_52 (0x00A9B1D0) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_52___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_52__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_52__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_53 (0x00A9B1D4) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_53___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_53__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_53__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_54 (0x00A9B1D8) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_54___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_54__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_54__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_55 (0x00A9B1DC) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_55___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_55__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_55__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_56 (0x00A9B1E0) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_56___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_56__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_56__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_57 (0x00A9B1E4) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_57___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_57__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_57__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_58 (0x00A9B1E8) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_58___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_58__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_58__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_59 (0x00A9B1EC) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_59___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_59__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_59__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_60 (0x00A9B1F0) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_60___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_60__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_60__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_61 (0x00A9B1F4) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_61___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_61__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_61__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_62 (0x00A9B1F8) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_62___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_62__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_62__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_63 (0x00A9B1FC) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_63___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_63__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_63__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_64 (0x00A9B200) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_64___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_64__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_64__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_65 (0x00A9B204) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_65___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_65__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_65__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_66 (0x00A9B208) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_66___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_66__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_66__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_67 (0x00A9B20C) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_67___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_67__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_67__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_68 (0x00A9B210) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_68___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_68__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_68__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_69 (0x00A9B214) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_69___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_69__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_69__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_70 (0x00A9B218) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_70___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_70__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_70__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_71 (0x00A9B21C) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_71___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_71__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_71__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_72 (0x00A9B220) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_72___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_72__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_72__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_73 (0x00A9B224) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_73___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_73__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_73__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_74 (0x00A9B228) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_74___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_74__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_74__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_75 (0x00A9B22C) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_75___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_75__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_75__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_76 (0x00A9B230) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_76___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_76__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_76__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_77 (0x00A9B234) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_77___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_77__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_77__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_78 (0x00A9B238) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_78___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_78__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_78__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_79 (0x00A9B23C) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_79___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_79__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_79__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_80 (0x00A9B240) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_80___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_80__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_80__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_81 (0x00A9B244) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_81___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_81__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_81__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_82 (0x00A9B248) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_82___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_82__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_82__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_83 (0x00A9B24C) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_83___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_83__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_83__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_84 (0x00A9B250) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_84___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_84__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_84__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_85 (0x00A9B254) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_85___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_85__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_85__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_86 (0x00A9B258) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_86___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_86__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_86__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_87 (0x00A9B25C) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_87___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_87__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_87__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_88 (0x00A9B260) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_88___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_88__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_88__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_89 (0x00A9B264) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_89___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_89__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_89__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_90 (0x00A9B268) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_90___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_90__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_90__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_91 (0x00A9B26C) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_91___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_91__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_91__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_92 (0x00A9B270) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_92___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_92__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_92__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_93 (0x00A9B274) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_93___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_93__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_93__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_94 (0x00A9B278) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_94___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_94__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_94__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_95 (0x00A9B27C) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_95___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_95__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_95__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_96 (0x00A9B280) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_96___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_96__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_96__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_97 (0x00A9B284) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_97___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_97__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_97__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_98 (0x00A9B288) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_98___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_98__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_98__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_99 (0x00A9B28C) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_99___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_99__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_99__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_100 (0x00A9B290) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_100___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_100__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_100__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_101 (0x00A9B294) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_101___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_101__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_101__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_102 (0x00A9B298) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_102___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_102__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_102__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_103 (0x00A9B29C) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_103___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_103__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_103__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_104 (0x00A9B2A0) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_104___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_104__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_104__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_105 (0x00A9B2A4) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_105___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_105__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_105__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_106 (0x00A9B2A8) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_106___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_106__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_106__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_107 (0x00A9B2AC) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_107___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_107__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_107__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_108 (0x00A9B2B0) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_108___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_108__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_108__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_109 (0x00A9B2B4) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_109___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_109__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_109__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_110 (0x00A9B2B8) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_110___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_110__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_110__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_111 (0x00A9B2BC) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_111___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_111__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_111__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_112 (0x00A9B2C0) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_112___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_112__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_112__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_113 (0x00A9B2C4) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_113___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_113__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_113__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_114 (0x00A9B2C8) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_114___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_114__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_114__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_115 (0x00A9B2CC) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_115___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_115__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_115__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_116 (0x00A9B2D0) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_116___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_116__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_116__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_117 (0x00A9B2D4) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_117___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_117__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_117__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_118 (0x00A9B2D8) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_118___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_118__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_118__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_119 (0x00A9B2DC) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_119___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_119__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_119__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_120 (0x00A9B2E0) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_120___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_120__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_120__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_121 (0x00A9B2E4) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_121___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_121__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_121__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_122 (0x00A9B2E8) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_122___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_122__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_122__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_123 (0x00A9B2EC) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_123___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_123__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_123__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_124 (0x00A9B2F0) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_124___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_124__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_124__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_125 (0x00A9B2F4) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_125___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_125__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_125__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_126 (0x00A9B2F8) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_126___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_126__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_126__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_127 (0x00A9B2FC) +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_127___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_127__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_RULE_MEM_DATA_127__VALUE___S 0 + +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_n(n) (0x00A9B300+0x4*(n)) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_n_nMIN 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_n_nMAX 255 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_n_ELEM 256 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_n___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_n___POR 0x00000000 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_n__VALUE___POR 0x00000000 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_n__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_n__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_n___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_n___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_0 (0x00A9B300) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_0___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_0__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_0__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_1 (0x00A9B304) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_1___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_1__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_1__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_2 (0x00A9B308) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_2___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_2__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_2__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_3 (0x00A9B30C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_3___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_3__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_3__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_4 (0x00A9B310) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_4___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_4__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_4__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_5 (0x00A9B314) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_5___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_5__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_5__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_6 (0x00A9B318) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_6___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_6__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_6__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_7 (0x00A9B31C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_7___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_7__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_7__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_8 (0x00A9B320) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_8___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_8__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_8__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_9 (0x00A9B324) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_9___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_9__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_9__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_10 (0x00A9B328) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_10___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_10__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_10__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_11 (0x00A9B32C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_11___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_11__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_11__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_12 (0x00A9B330) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_12___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_12__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_12__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_13 (0x00A9B334) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_13___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_13__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_13__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_14 (0x00A9B338) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_14___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_14__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_14__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_15 (0x00A9B33C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_15___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_15__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_15__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_16 (0x00A9B340) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_16___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_16__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_16__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_17 (0x00A9B344) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_17___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_17__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_17__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_18 (0x00A9B348) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_18___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_18__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_18__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_19 (0x00A9B34C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_19___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_19__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_19__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_20 (0x00A9B350) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_20___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_20__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_20__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_21 (0x00A9B354) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_21___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_21__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_21__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_22 (0x00A9B358) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_22___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_22__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_22__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_23 (0x00A9B35C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_23___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_23__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_23__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_24 (0x00A9B360) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_24___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_24__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_24__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_25 (0x00A9B364) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_25___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_25__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_25__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_26 (0x00A9B368) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_26___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_26__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_26__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_27 (0x00A9B36C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_27___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_27__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_27__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_28 (0x00A9B370) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_28___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_28__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_28__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_29 (0x00A9B374) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_29___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_29__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_29__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_30 (0x00A9B378) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_30___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_30__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_30__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_31 (0x00A9B37C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_31___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_31__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_31__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_32 (0x00A9B380) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_32___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_32__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_32__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_33 (0x00A9B384) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_33___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_33__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_33__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_34 (0x00A9B388) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_34___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_34__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_34__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_35 (0x00A9B38C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_35___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_35__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_35__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_36 (0x00A9B390) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_36___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_36__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_36__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_37 (0x00A9B394) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_37___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_37__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_37__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_38 (0x00A9B398) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_38___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_38__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_38__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_39 (0x00A9B39C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_39___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_39__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_39__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_40 (0x00A9B3A0) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_40___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_40__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_40__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_41 (0x00A9B3A4) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_41___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_41__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_41__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_42 (0x00A9B3A8) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_42___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_42__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_42__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_43 (0x00A9B3AC) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_43___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_43__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_43__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_44 (0x00A9B3B0) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_44___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_44__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_44__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_45 (0x00A9B3B4) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_45___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_45__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_45__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_46 (0x00A9B3B8) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_46___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_46__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_46__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_47 (0x00A9B3BC) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_47___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_47__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_47__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_48 (0x00A9B3C0) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_48___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_48__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_48__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_49 (0x00A9B3C4) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_49___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_49__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_49__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_50 (0x00A9B3C8) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_50___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_50__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_50__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_51 (0x00A9B3CC) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_51___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_51__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_51__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_52 (0x00A9B3D0) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_52___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_52__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_52__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_53 (0x00A9B3D4) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_53___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_53__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_53__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_54 (0x00A9B3D8) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_54___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_54__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_54__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_55 (0x00A9B3DC) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_55___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_55__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_55__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_56 (0x00A9B3E0) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_56___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_56__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_56__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_57 (0x00A9B3E4) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_57___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_57__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_57__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_58 (0x00A9B3E8) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_58___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_58__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_58__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_59 (0x00A9B3EC) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_59___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_59__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_59__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_60 (0x00A9B3F0) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_60___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_60__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_60__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_61 (0x00A9B3F4) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_61___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_61__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_61__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_62 (0x00A9B3F8) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_62___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_62__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_62__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_63 (0x00A9B3FC) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_63___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_63__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_63__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_64 (0x00A9B400) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_64___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_64__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_64__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_65 (0x00A9B404) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_65___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_65__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_65__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_66 (0x00A9B408) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_66___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_66__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_66__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_67 (0x00A9B40C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_67___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_67__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_67__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_68 (0x00A9B410) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_68___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_68__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_68__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_69 (0x00A9B414) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_69___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_69__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_69__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_70 (0x00A9B418) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_70___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_70__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_70__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_71 (0x00A9B41C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_71___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_71__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_71__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_72 (0x00A9B420) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_72___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_72__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_72__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_73 (0x00A9B424) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_73___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_73__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_73__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_74 (0x00A9B428) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_74___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_74__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_74__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_75 (0x00A9B42C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_75___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_75__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_75__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_76 (0x00A9B430) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_76___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_76__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_76__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_77 (0x00A9B434) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_77___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_77__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_77__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_78 (0x00A9B438) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_78___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_78__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_78__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_79 (0x00A9B43C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_79___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_79__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_79__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_80 (0x00A9B440) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_80___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_80__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_80__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_81 (0x00A9B444) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_81___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_81__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_81__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_82 (0x00A9B448) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_82___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_82__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_82__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_83 (0x00A9B44C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_83___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_83__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_83__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_84 (0x00A9B450) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_84___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_84__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_84__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_85 (0x00A9B454) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_85___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_85__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_85__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_86 (0x00A9B458) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_86___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_86__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_86__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_87 (0x00A9B45C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_87___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_87__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_87__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_88 (0x00A9B460) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_88___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_88__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_88__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_89 (0x00A9B464) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_89___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_89__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_89__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_90 (0x00A9B468) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_90___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_90__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_90__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_91 (0x00A9B46C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_91___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_91__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_91__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_92 (0x00A9B470) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_92___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_92__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_92__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_93 (0x00A9B474) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_93___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_93__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_93__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_94 (0x00A9B478) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_94___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_94__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_94__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_95 (0x00A9B47C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_95___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_95__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_95__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_96 (0x00A9B480) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_96___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_96__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_96__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_97 (0x00A9B484) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_97___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_97__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_97__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_98 (0x00A9B488) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_98___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_98__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_98__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_99 (0x00A9B48C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_99___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_99__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_99__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_100 (0x00A9B490) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_100___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_100__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_100__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_101 (0x00A9B494) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_101___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_101__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_101__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_102 (0x00A9B498) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_102___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_102__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_102__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_103 (0x00A9B49C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_103___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_103__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_103__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_104 (0x00A9B4A0) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_104___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_104__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_104__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_105 (0x00A9B4A4) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_105___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_105__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_105__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_106 (0x00A9B4A8) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_106___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_106__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_106__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_107 (0x00A9B4AC) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_107___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_107__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_107__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_108 (0x00A9B4B0) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_108___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_108__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_108__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_109 (0x00A9B4B4) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_109___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_109__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_109__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_110 (0x00A9B4B8) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_110___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_110__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_110__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_111 (0x00A9B4BC) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_111___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_111__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_111__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_112 (0x00A9B4C0) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_112___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_112__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_112__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_113 (0x00A9B4C4) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_113___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_113__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_113__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_114 (0x00A9B4C8) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_114___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_114__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_114__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_115 (0x00A9B4CC) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_115___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_115__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_115__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_116 (0x00A9B4D0) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_116___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_116__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_116__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_117 (0x00A9B4D4) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_117___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_117__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_117__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_118 (0x00A9B4D8) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_118___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_118__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_118__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_119 (0x00A9B4DC) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_119___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_119__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_119__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_120 (0x00A9B4E0) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_120___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_120__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_120__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_121 (0x00A9B4E4) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_121___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_121__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_121__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_122 (0x00A9B4E8) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_122___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_122__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_122__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_123 (0x00A9B4EC) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_123___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_123__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_123__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_124 (0x00A9B4F0) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_124___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_124__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_124__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_125 (0x00A9B4F4) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_125___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_125__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_125__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_126 (0x00A9B4F8) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_126___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_126__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_126__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_127 (0x00A9B4FC) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_127___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_127__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_127__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_128 (0x00A9B500) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_128___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_128__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_128__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_129 (0x00A9B504) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_129___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_129__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_129__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_130 (0x00A9B508) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_130___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_130__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_130__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_131 (0x00A9B50C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_131___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_131__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_131__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_132 (0x00A9B510) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_132___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_132__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_132__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_133 (0x00A9B514) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_133___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_133__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_133__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_134 (0x00A9B518) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_134___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_134__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_134__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_135 (0x00A9B51C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_135___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_135__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_135__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_136 (0x00A9B520) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_136___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_136__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_136__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_137 (0x00A9B524) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_137___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_137__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_137__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_138 (0x00A9B528) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_138___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_138__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_138__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_139 (0x00A9B52C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_139___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_139__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_139__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_140 (0x00A9B530) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_140___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_140__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_140__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_141 (0x00A9B534) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_141___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_141__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_141__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_142 (0x00A9B538) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_142___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_142__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_142__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_143 (0x00A9B53C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_143___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_143__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_143__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_144 (0x00A9B540) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_144___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_144__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_144__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_145 (0x00A9B544) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_145___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_145__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_145__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_146 (0x00A9B548) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_146___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_146__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_146__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_147 (0x00A9B54C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_147___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_147__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_147__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_148 (0x00A9B550) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_148___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_148__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_148__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_149 (0x00A9B554) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_149___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_149__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_149__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_150 (0x00A9B558) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_150___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_150__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_150__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_151 (0x00A9B55C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_151___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_151__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_151__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_152 (0x00A9B560) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_152___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_152__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_152__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_153 (0x00A9B564) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_153___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_153__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_153__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_154 (0x00A9B568) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_154___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_154__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_154__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_155 (0x00A9B56C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_155___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_155__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_155__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_156 (0x00A9B570) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_156___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_156__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_156__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_157 (0x00A9B574) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_157___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_157__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_157__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_158 (0x00A9B578) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_158___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_158__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_158__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_159 (0x00A9B57C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_159___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_159__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_159__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_160 (0x00A9B580) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_160___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_160__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_160__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_161 (0x00A9B584) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_161___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_161__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_161__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_162 (0x00A9B588) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_162___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_162__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_162__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_163 (0x00A9B58C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_163___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_163__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_163__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_164 (0x00A9B590) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_164___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_164__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_164__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_165 (0x00A9B594) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_165___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_165__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_165__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_166 (0x00A9B598) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_166___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_166__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_166__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_167 (0x00A9B59C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_167___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_167__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_167__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_168 (0x00A9B5A0) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_168___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_168__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_168__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_169 (0x00A9B5A4) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_169___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_169__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_169__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_170 (0x00A9B5A8) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_170___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_170__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_170__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_171 (0x00A9B5AC) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_171___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_171__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_171__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_172 (0x00A9B5B0) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_172___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_172__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_172__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_173 (0x00A9B5B4) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_173___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_173__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_173__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_174 (0x00A9B5B8) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_174___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_174__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_174__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_175 (0x00A9B5BC) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_175___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_175__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_175__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_176 (0x00A9B5C0) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_176___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_176__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_176__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_177 (0x00A9B5C4) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_177___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_177__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_177__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_178 (0x00A9B5C8) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_178___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_178__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_178__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_179 (0x00A9B5CC) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_179___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_179__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_179__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_180 (0x00A9B5D0) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_180___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_180__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_180__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_181 (0x00A9B5D4) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_181___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_181__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_181__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_182 (0x00A9B5D8) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_182___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_182__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_182__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_183 (0x00A9B5DC) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_183___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_183__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_183__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_184 (0x00A9B5E0) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_184___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_184__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_184__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_185 (0x00A9B5E4) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_185___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_185__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_185__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_186 (0x00A9B5E8) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_186___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_186__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_186__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_187 (0x00A9B5EC) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_187___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_187__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_187__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_188 (0x00A9B5F0) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_188___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_188__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_188__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_189 (0x00A9B5F4) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_189___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_189__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_189__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_190 (0x00A9B5F8) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_190___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_190__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_190__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_191 (0x00A9B5FC) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_191___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_191__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_191__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_192 (0x00A9B600) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_192___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_192__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_192__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_193 (0x00A9B604) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_193___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_193__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_193__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_194 (0x00A9B608) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_194___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_194__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_194__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_195 (0x00A9B60C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_195___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_195__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_195__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_196 (0x00A9B610) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_196___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_196__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_196__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_197 (0x00A9B614) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_197___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_197__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_197__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_198 (0x00A9B618) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_198___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_198__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_198__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_199 (0x00A9B61C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_199___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_199__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_199__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_200 (0x00A9B620) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_200___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_200__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_200__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_201 (0x00A9B624) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_201___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_201__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_201__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_202 (0x00A9B628) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_202___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_202__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_202__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_203 (0x00A9B62C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_203___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_203__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_203__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_204 (0x00A9B630) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_204___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_204__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_204__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_205 (0x00A9B634) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_205___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_205__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_205__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_206 (0x00A9B638) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_206___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_206__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_206__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_207 (0x00A9B63C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_207___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_207__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_207__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_208 (0x00A9B640) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_208___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_208__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_208__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_209 (0x00A9B644) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_209___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_209__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_209__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_210 (0x00A9B648) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_210___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_210__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_210__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_211 (0x00A9B64C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_211___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_211__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_211__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_212 (0x00A9B650) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_212___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_212__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_212__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_213 (0x00A9B654) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_213___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_213__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_213__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_214 (0x00A9B658) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_214___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_214__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_214__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_215 (0x00A9B65C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_215___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_215__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_215__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_216 (0x00A9B660) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_216___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_216__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_216__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_217 (0x00A9B664) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_217___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_217__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_217__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_218 (0x00A9B668) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_218___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_218__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_218__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_219 (0x00A9B66C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_219___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_219__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_219__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_220 (0x00A9B670) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_220___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_220__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_220__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_221 (0x00A9B674) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_221___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_221__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_221__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_222 (0x00A9B678) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_222___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_222__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_222__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_223 (0x00A9B67C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_223___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_223__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_223__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_224 (0x00A9B680) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_224___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_224__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_224__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_225 (0x00A9B684) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_225___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_225__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_225__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_226 (0x00A9B688) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_226___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_226__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_226__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_227 (0x00A9B68C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_227___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_227__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_227__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_228 (0x00A9B690) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_228___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_228__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_228__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_229 (0x00A9B694) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_229___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_229__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_229__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_230 (0x00A9B698) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_230___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_230__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_230__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_231 (0x00A9B69C) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_231___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_231__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_231__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_232 (0x00A9B6A0) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_232___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_232__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_232__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_233 (0x00A9B6A4) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_233___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_233__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_233__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_234 (0x00A9B6A8) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_234___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_234__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_234__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_235 (0x00A9B6AC) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_235___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_235__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_235__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_236 (0x00A9B6B0) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_236___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_236__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_236__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_237 (0x00A9B6B4) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_237___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_237__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_237__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_238 (0x00A9B6B8) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_238___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_238__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_238__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_239 (0x00A9B6BC) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_239___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_239__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_239__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_240 (0x00A9B6C0) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_240___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_240__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_240__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_241 (0x00A9B6C4) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_241___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_241__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_241__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_242 (0x00A9B6C8) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_242___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_242__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_242__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_243 (0x00A9B6CC) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_243___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_243__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_243__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_244 (0x00A9B6D0) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_244___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_244__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_244__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_245 (0x00A9B6D4) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_245___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_245__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_245__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_246 (0x00A9B6D8) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_246___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_246__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_246__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_247 (0x00A9B6DC) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_247___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_247__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_247__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_248 (0x00A9B6E0) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_248___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_248__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_248__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_249 (0x00A9B6E4) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_249___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_249__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_249__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_250 (0x00A9B6E8) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_250___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_250__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_250__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_251 (0x00A9B6EC) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_251___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_251__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_251__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_252 (0x00A9B6F0) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_252___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_252__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_252__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_253 (0x00A9B6F4) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_253___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_253__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_253__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_254 (0x00A9B6F8) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_254___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_254__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_254__VALUE___S 0 +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_255 (0x00A9B6FC) +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_255___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_255__VALUE___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R0_SUPER_RULE_MEM_DATA_255__VALUE___S 0 + +#define WMAC0_CCE_CCE_R1_REG_ACCESS_EVENT_GEN_CTRL (0x00A9C000) +#define WMAC0_CCE_CCE_R1_REG_ACCESS_EVENT_GEN_CTRL___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R1_REG_ACCESS_EVENT_GEN_CTRL___POR 0x7FFE0002 +#define WMAC0_CCE_CCE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___POR 0x3FFF +#define WMAC0_CCE_CCE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___POR 0x0000 +#define WMAC0_CCE_CCE_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___POR 0x1 +#define WMAC0_CCE_CCE_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___POR 0x0 +#define WMAC0_CCE_CCE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___M 0xFFFE0000 +#define WMAC0_CCE_CCE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___S 17 +#define WMAC0_CCE_CCE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___M 0x0001FFFC +#define WMAC0_CCE_CCE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___S 2 +#define WMAC0_CCE_CCE_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___M 0x00000002 +#define WMAC0_CCE_CCE_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___S 1 +#define WMAC0_CCE_CCE_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___M 0x00000001 +#define WMAC0_CCE_CCE_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___S 0 +#define WMAC0_CCE_CCE_R1_REG_ACCESS_EVENT_GEN_CTRL___M 0xFFFFFFFF +#define WMAC0_CCE_CCE_R1_REG_ACCESS_EVENT_GEN_CTRL___S 0 + +#define WMAC0_CCE_CCE_R1_END_OF_TEST_CHECK (0x00A9C004) +#define WMAC0_CCE_CCE_R1_END_OF_TEST_CHECK___RWC QCSR_REG_RW +#define WMAC0_CCE_CCE_R1_END_OF_TEST_CHECK___POR 0x00000000 +#define WMAC0_CCE_CCE_R1_END_OF_TEST_CHECK__VALUE___POR 0x0 +#define WMAC0_CCE_CCE_R1_END_OF_TEST_CHECK__VALUE___M 0x00000001 +#define WMAC0_CCE_CCE_R1_END_OF_TEST_CHECK__VALUE___S 0 +#define WMAC0_CCE_CCE_R1_END_OF_TEST_CHECK___M 0x00000001 +#define WMAC0_CCE_CCE_R1_END_OF_TEST_CHECK___S 0 + +#define WMAC0_CCE_CCE_R1_SM_STATES (0x00A9C008) +#define WMAC0_CCE_CCE_R1_SM_STATES___RWC QCSR_REG_RO +#define WMAC0_CCE_CCE_R1_SM_STATES___POR 0x00000000 +#define WMAC0_CCE_CCE_R1_SM_STATES__STATE_CCE_BUF___POR 0x0 +#define WMAC0_CCE_CCE_R1_SM_STATES__STATE_PKT_COMP___POR 0x0 +#define WMAC0_CCE_CCE_R1_SM_STATES__STATE_MSDU_VAL___POR 0x0 +#define WMAC0_CCE_CCE_R1_SM_STATES__STATE_RULE_EXE___POR 0x0 +#define WMAC0_CCE_CCE_R1_SM_STATES__STATE_RULE_RESERVE_RST___POR 0x0 +#define WMAC0_CCE_CCE_R1_SM_STATES__STATE_CCE_SW_PRG___POR 0x0 +#define WMAC0_CCE_CCE_R1_SM_STATES__STATE_CCE_IDLE___POR 0x0 +#define WMAC0_CCE_CCE_R1_SM_STATES__STATE_CCE_BUF___M 0x00003000 +#define WMAC0_CCE_CCE_R1_SM_STATES__STATE_CCE_BUF___S 12 +#define WMAC0_CCE_CCE_R1_SM_STATES__STATE_PKT_COMP___M 0x00000C00 +#define WMAC0_CCE_CCE_R1_SM_STATES__STATE_PKT_COMP___S 10 +#define WMAC0_CCE_CCE_R1_SM_STATES__STATE_MSDU_VAL___M 0x00000300 +#define WMAC0_CCE_CCE_R1_SM_STATES__STATE_MSDU_VAL___S 8 +#define WMAC0_CCE_CCE_R1_SM_STATES__STATE_RULE_EXE___M 0x000000C0 +#define WMAC0_CCE_CCE_R1_SM_STATES__STATE_RULE_EXE___S 6 +#define WMAC0_CCE_CCE_R1_SM_STATES__STATE_RULE_RESERVE_RST___M 0x00000030 +#define WMAC0_CCE_CCE_R1_SM_STATES__STATE_RULE_RESERVE_RST___S 4 +#define WMAC0_CCE_CCE_R1_SM_STATES__STATE_CCE_SW_PRG___M 0x0000000E +#define WMAC0_CCE_CCE_R1_SM_STATES__STATE_CCE_SW_PRG___S 1 +#define WMAC0_CCE_CCE_R1_SM_STATES__STATE_CCE_IDLE___M 0x00000001 +#define WMAC0_CCE_CCE_R1_SM_STATES__STATE_CCE_IDLE___S 0 +#define WMAC0_CCE_CCE_R1_SM_STATES___M 0x00003FFF +#define WMAC0_CCE_CCE_R1_SM_STATES___S 0 + +#define WMAC0_TXOLE_TXOLE_R0_CONFIG (0x00A9E000) +#define WMAC0_TXOLE_TXOLE_R0_CONFIG___RWC QCSR_REG_RW +#define WMAC0_TXOLE_TXOLE_R0_CONFIG___POR 0x00000000 +#define WMAC0_TXOLE_TXOLE_R0_CONFIG__TXOLE_FLUSH_CODE_FIX_DISABLE___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R0_CONFIG__ENABLE_C9D1___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R0_CONFIG__CONSUME_MSDU_TLVS_IN_TXOLE___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R0_CONFIG__INVERT_PARTIAL_CHKSUM_IF_ZERO___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R0_CONFIG__TXOLE_FLUSH_CODE_FIX_DISABLE___M 0x00000008 +#define WMAC0_TXOLE_TXOLE_R0_CONFIG__TXOLE_FLUSH_CODE_FIX_DISABLE___S 3 +#define WMAC0_TXOLE_TXOLE_R0_CONFIG__ENABLE_C9D1___M 0x00000004 +#define WMAC0_TXOLE_TXOLE_R0_CONFIG__ENABLE_C9D1___S 2 +#define WMAC0_TXOLE_TXOLE_R0_CONFIG__CONSUME_MSDU_TLVS_IN_TXOLE___M 0x00000002 +#define WMAC0_TXOLE_TXOLE_R0_CONFIG__CONSUME_MSDU_TLVS_IN_TXOLE___S 1 +#define WMAC0_TXOLE_TXOLE_R0_CONFIG__INVERT_PARTIAL_CHKSUM_IF_ZERO___M 0x00000001 +#define WMAC0_TXOLE_TXOLE_R0_CONFIG__INVERT_PARTIAL_CHKSUM_IF_ZERO___S 0 +#define WMAC0_TXOLE_TXOLE_R0_CONFIG___M 0x0000000F +#define WMAC0_TXOLE_TXOLE_R0_CONFIG___S 0 + +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE (0x00A9E004) +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE___RWC QCSR_REG_RW +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE___POR 0x00000000 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__CLK_EXTEND___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__TXOLE_SPARE___POR 0x0000 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__PER_USER_TLV_FIFO___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__APB_CMN_PARSER___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__TXOLE_APB_INVALID_ACCESS___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__CMN_PARSER_TLV_DEC___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__PARTIAL_CHECKSUM___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__PARSER_FIFO___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__DATA_FIFO___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__CMD_FIFO___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__BYPASS_FIFO___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__ENCAP___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__DATA___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__TXOLE_BUF_STATUS___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__TXOLE_CORE___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__CMN_PARSER_CORE___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__CLK_EXTEND___M 0x80000000 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__CLK_EXTEND___S 31 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___M 0x40000000 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___S 30 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__TXOLE_SPARE___M 0x3FFFC000 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__TXOLE_SPARE___S 14 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__PER_USER_TLV_FIFO___M 0x00002000 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__PER_USER_TLV_FIFO___S 13 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__APB_CMN_PARSER___M 0x00001000 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__APB_CMN_PARSER___S 12 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__TXOLE_APB_INVALID_ACCESS___M 0x00000800 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__TXOLE_APB_INVALID_ACCESS___S 11 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__CMN_PARSER_TLV_DEC___M 0x00000400 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__CMN_PARSER_TLV_DEC___S 10 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__PARTIAL_CHECKSUM___M 0x00000200 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__PARTIAL_CHECKSUM___S 9 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__PARSER_FIFO___M 0x00000100 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__PARSER_FIFO___S 8 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__DATA_FIFO___M 0x00000080 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__DATA_FIFO___S 7 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__CMD_FIFO___M 0x00000040 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__CMD_FIFO___S 6 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__BYPASS_FIFO___M 0x00000020 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__BYPASS_FIFO___S 5 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__ENCAP___M 0x00000010 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__ENCAP___S 4 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__DATA___M 0x00000008 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__DATA___S 3 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__TXOLE_BUF_STATUS___M 0x00000004 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__TXOLE_BUF_STATUS___S 2 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__TXOLE_CORE___M 0x00000002 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__TXOLE_CORE___S 1 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__CMN_PARSER_CORE___M 0x00000001 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE__CMN_PARSER_CORE___S 0 +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE___M 0xFFFFFFFF +#define WMAC0_TXOLE_TXOLE_R0_CLKGATE_DISABLE___S 0 + +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN (0x00A9E008) +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN___RWC QCSR_REG_RW +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN___POR 0x00000000 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__INCONSISTENT_MESH_MSDU___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__MESH_EN_FOR_ETH_FRAME___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__MSDU_LENGTH_TOO_HIGH___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__INCOMPLETE_LLC_FRAME___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__LENGTH_MISMATCH_802_3_ETH_FRAME___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__NO_FULL_MSDU_FOR_CHECKSUM_EN___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__ILLEGAL_FRAME___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__MPDU_FRAG_EN_SW_ENCRYPTED_ERROR___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__MORE_FRAG_SET_FOR_LAST_FRAG_ERROR___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__MPDU_FRAG_EN_AMSDU_AMPDU_ERROR___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__PV1_WRONG_KEY_TYPE_ERROR___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__PV1_TYPE3_AMSDU_ERROR___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__WEP_KEY_TYPE_ERROR___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__AMSDU_FRAME_ERROR___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__INCONSISTENT_MESH_MSDU___M 0x00002000 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__INCONSISTENT_MESH_MSDU___S 13 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__MESH_EN_FOR_ETH_FRAME___M 0x00001000 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__MESH_EN_FOR_ETH_FRAME___S 12 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__MSDU_LENGTH_TOO_HIGH___M 0x00000800 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__MSDU_LENGTH_TOO_HIGH___S 11 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__INCOMPLETE_LLC_FRAME___M 0x00000400 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__INCOMPLETE_LLC_FRAME___S 10 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__LENGTH_MISMATCH_802_3_ETH_FRAME___M 0x00000200 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__LENGTH_MISMATCH_802_3_ETH_FRAME___S 9 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__NO_FULL_MSDU_FOR_CHECKSUM_EN___M 0x00000100 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__NO_FULL_MSDU_FOR_CHECKSUM_EN___S 8 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__ILLEGAL_FRAME___M 0x00000080 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__ILLEGAL_FRAME___S 7 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__MPDU_FRAG_EN_SW_ENCRYPTED_ERROR___M 0x00000040 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__MPDU_FRAG_EN_SW_ENCRYPTED_ERROR___S 6 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__MORE_FRAG_SET_FOR_LAST_FRAG_ERROR___M 0x00000020 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__MORE_FRAG_SET_FOR_LAST_FRAG_ERROR___S 5 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__MPDU_FRAG_EN_AMSDU_AMPDU_ERROR___M 0x00000010 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__MPDU_FRAG_EN_AMSDU_AMPDU_ERROR___S 4 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__PV1_WRONG_KEY_TYPE_ERROR___M 0x00000008 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__PV1_WRONG_KEY_TYPE_ERROR___S 3 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__PV1_TYPE3_AMSDU_ERROR___M 0x00000004 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__PV1_TYPE3_AMSDU_ERROR___S 2 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__WEP_KEY_TYPE_ERROR___M 0x00000002 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__WEP_KEY_TYPE_ERROR___S 1 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__AMSDU_FRAME_ERROR___M 0x00000001 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN__AMSDU_FRAME_ERROR___S 0 +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN___M 0x00003FFF +#define WMAC0_TXOLE_TXOLE_R0_FLUSH_EN___S 0 + +#define WMAC0_TXOLE_TXOLE_R0_BUF_STATUS (0x00A9E00C) +#define WMAC0_TXOLE_TXOLE_R0_BUF_STATUS___RWC QCSR_REG_RW +#define WMAC0_TXOLE_TXOLE_R0_BUF_STATUS___POR 0x00001020 +#define WMAC0_TXOLE_TXOLE_R0_BUF_STATUS__CMD_FIFO_THRESHOLD___POR 0x08 +#define WMAC0_TXOLE_TXOLE_R0_BUF_STATUS__DATA_FIFO_THRESHOLD___POR 0x020 +#define WMAC0_TXOLE_TXOLE_R0_BUF_STATUS__CMD_FIFO_THRESHOLD___M 0x00003E00 +#define WMAC0_TXOLE_TXOLE_R0_BUF_STATUS__CMD_FIFO_THRESHOLD___S 9 +#define WMAC0_TXOLE_TXOLE_R0_BUF_STATUS__DATA_FIFO_THRESHOLD___M 0x000001FF +#define WMAC0_TXOLE_TXOLE_R0_BUF_STATUS__DATA_FIFO_THRESHOLD___S 0 +#define WMAC0_TXOLE_TXOLE_R0_BUF_STATUS___M 0x00003FFF +#define WMAC0_TXOLE_TXOLE_R0_BUF_STATUS___S 0 + +#define WMAC0_TXOLE_TXOLE_R0_PM_STATE_PER_VIF (0x00A9E010) +#define WMAC0_TXOLE_TXOLE_R0_PM_STATE_PER_VIF___RWC QCSR_REG_RW +#define WMAC0_TXOLE_TXOLE_R0_PM_STATE_PER_VIF___POR 0x00000000 +#define WMAC0_TXOLE_TXOLE_R0_PM_STATE_PER_VIF__VALUE___POR 0x00000000 +#define WMAC0_TXOLE_TXOLE_R0_PM_STATE_PER_VIF__VALUE___M 0xFFFFFFFF +#define WMAC0_TXOLE_TXOLE_R0_PM_STATE_PER_VIF__VALUE___S 0 +#define WMAC0_TXOLE_TXOLE_R0_PM_STATE_PER_VIF___M 0xFFFFFFFF +#define WMAC0_TXOLE_TXOLE_R0_PM_STATE_PER_VIF___S 0 + +#define WMAC0_TXOLE_TXOLE_R0_WATCHDOG (0x00A9E014) +#define WMAC0_TXOLE_TXOLE_R0_WATCHDOG___RWC QCSR_REG_RW +#define WMAC0_TXOLE_TXOLE_R0_WATCHDOG___POR 0x0000FFFF +#define WMAC0_TXOLE_TXOLE_R0_WATCHDOG__STATUS___POR 0x0000 +#define WMAC0_TXOLE_TXOLE_R0_WATCHDOG__LIMIT___POR 0xFFFF +#define WMAC0_TXOLE_TXOLE_R0_WATCHDOG__STATUS___M 0xFFFF0000 +#define WMAC0_TXOLE_TXOLE_R0_WATCHDOG__STATUS___S 16 +#define WMAC0_TXOLE_TXOLE_R0_WATCHDOG__LIMIT___M 0x0000FFFF +#define WMAC0_TXOLE_TXOLE_R0_WATCHDOG__LIMIT___S 0 +#define WMAC0_TXOLE_TXOLE_R0_WATCHDOG___M 0xFFFFFFFF +#define WMAC0_TXOLE_TXOLE_R0_WATCHDOG___S 0 + +#define WMAC0_TXOLE_TXOLE_R1_TESTBUS_CTRL (0x00A9F000) +#define WMAC0_TXOLE_TXOLE_R1_TESTBUS_CTRL___RWC QCSR_REG_RW +#define WMAC0_TXOLE_TXOLE_R1_TESTBUS_CTRL___POR 0x00000000 +#define WMAC0_TXOLE_TXOLE_R1_TESTBUS_CTRL__HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R1_TESTBUS_CTRL__PARSER_SELECT___POR 0x00 +#define WMAC0_TXOLE_TXOLE_R1_TESTBUS_CTRL__TXOLE_SELECT___POR 0x00 +#define WMAC0_TXOLE_TXOLE_R1_TESTBUS_CTRL__HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE___M 0x00000400 +#define WMAC0_TXOLE_TXOLE_R1_TESTBUS_CTRL__HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE___S 10 +#define WMAC0_TXOLE_TXOLE_R1_TESTBUS_CTRL__PARSER_SELECT___M 0x000003E0 +#define WMAC0_TXOLE_TXOLE_R1_TESTBUS_CTRL__PARSER_SELECT___S 5 +#define WMAC0_TXOLE_TXOLE_R1_TESTBUS_CTRL__TXOLE_SELECT___M 0x0000001F +#define WMAC0_TXOLE_TXOLE_R1_TESTBUS_CTRL__TXOLE_SELECT___S 0 +#define WMAC0_TXOLE_TXOLE_R1_TESTBUS_CTRL___M 0x000007FF +#define WMAC0_TXOLE_TXOLE_R1_TESTBUS_CTRL___S 0 + +#define WMAC0_TXOLE_TXOLE_R1_END_OF_TEST_CHECK (0x00A9F004) +#define WMAC0_TXOLE_TXOLE_R1_END_OF_TEST_CHECK___RWC QCSR_REG_RW +#define WMAC0_TXOLE_TXOLE_R1_END_OF_TEST_CHECK___POR 0x00000000 +#define WMAC0_TXOLE_TXOLE_R1_END_OF_TEST_CHECK__VALUE___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R1_END_OF_TEST_CHECK__VALUE___M 0x00000001 +#define WMAC0_TXOLE_TXOLE_R1_END_OF_TEST_CHECK__VALUE___S 0 +#define WMAC0_TXOLE_TXOLE_R1_END_OF_TEST_CHECK___M 0x00000001 +#define WMAC0_TXOLE_TXOLE_R1_END_OF_TEST_CHECK___S 0 + +#define WMAC0_TXOLE_TXOLE_R1_EVENTMASK_IX_0 (0x00A9F008) +#define WMAC0_TXOLE_TXOLE_R1_EVENTMASK_IX_0___RWC QCSR_REG_RW +#define WMAC0_TXOLE_TXOLE_R1_EVENTMASK_IX_0___POR 0x00000000 +#define WMAC0_TXOLE_TXOLE_R1_EVENTMASK_IX_0__VALUE___POR 0x00000000 +#define WMAC0_TXOLE_TXOLE_R1_EVENTMASK_IX_0__VALUE___M 0xFFFFFFFF +#define WMAC0_TXOLE_TXOLE_R1_EVENTMASK_IX_0__VALUE___S 0 +#define WMAC0_TXOLE_TXOLE_R1_EVENTMASK_IX_0___M 0xFFFFFFFF +#define WMAC0_TXOLE_TXOLE_R1_EVENTMASK_IX_0___S 0 + +#define WMAC0_TXOLE_TXOLE_R1_EVENTMASK_IX_1 (0x00A9F00C) +#define WMAC0_TXOLE_TXOLE_R1_EVENTMASK_IX_1___RWC QCSR_REG_RW +#define WMAC0_TXOLE_TXOLE_R1_EVENTMASK_IX_1___POR 0x00000000 +#define WMAC0_TXOLE_TXOLE_R1_EVENTMASK_IX_1__VALUE___POR 0x00000000 +#define WMAC0_TXOLE_TXOLE_R1_EVENTMASK_IX_1__VALUE___M 0xFFFFFFFF +#define WMAC0_TXOLE_TXOLE_R1_EVENTMASK_IX_1__VALUE___S 0 +#define WMAC0_TXOLE_TXOLE_R1_EVENTMASK_IX_1___M 0xFFFFFFFF +#define WMAC0_TXOLE_TXOLE_R1_EVENTMASK_IX_1___S 0 + +#define WMAC0_TXOLE_TXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL (0x00A9F010) +#define WMAC0_TXOLE_TXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL___RWC QCSR_REG_RW +#define WMAC0_TXOLE_TXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL___POR 0x7FFE0002 +#define WMAC0_TXOLE_TXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___POR 0x3FFF +#define WMAC0_TXOLE_TXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___POR 0x0000 +#define WMAC0_TXOLE_TXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___POR 0x1 +#define WMAC0_TXOLE_TXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___M 0xFFFE0000 +#define WMAC0_TXOLE_TXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___S 17 +#define WMAC0_TXOLE_TXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___M 0x0001FFFC +#define WMAC0_TXOLE_TXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___S 2 +#define WMAC0_TXOLE_TXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___M 0x00000002 +#define WMAC0_TXOLE_TXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___S 1 +#define WMAC0_TXOLE_TXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___M 0x00000001 +#define WMAC0_TXOLE_TXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___S 0 +#define WMAC0_TXOLE_TXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL___M 0xFFFFFFFF +#define WMAC0_TXOLE_TXOLE_R1_REG_ACCESS_EVENT_GEN_CTRL___S 0 + +#define WMAC0_TXOLE_TXOLE_R1_TESTBUS_LOWER (0x00A9F014) +#define WMAC0_TXOLE_TXOLE_R1_TESTBUS_LOWER___RWC QCSR_REG_RO +#define WMAC0_TXOLE_TXOLE_R1_TESTBUS_LOWER___POR 0x00000000 +#define WMAC0_TXOLE_TXOLE_R1_TESTBUS_LOWER__VALUE___POR 0x00000000 +#define WMAC0_TXOLE_TXOLE_R1_TESTBUS_LOWER__VALUE___M 0xFFFFFFFF +#define WMAC0_TXOLE_TXOLE_R1_TESTBUS_LOWER__VALUE___S 0 +#define WMAC0_TXOLE_TXOLE_R1_TESTBUS_LOWER___M 0xFFFFFFFF +#define WMAC0_TXOLE_TXOLE_R1_TESTBUS_LOWER___S 0 + +#define WMAC0_TXOLE_TXOLE_R1_TESTBUS_UPPER (0x00A9F018) +#define WMAC0_TXOLE_TXOLE_R1_TESTBUS_UPPER___RWC QCSR_REG_RO +#define WMAC0_TXOLE_TXOLE_R1_TESTBUS_UPPER___POR 0x00000000 +#define WMAC0_TXOLE_TXOLE_R1_TESTBUS_UPPER__VALUE___POR 0x00 +#define WMAC0_TXOLE_TXOLE_R1_TESTBUS_UPPER__VALUE___M 0x000000FF +#define WMAC0_TXOLE_TXOLE_R1_TESTBUS_UPPER__VALUE___S 0 +#define WMAC0_TXOLE_TXOLE_R1_TESTBUS_UPPER___M 0x000000FF +#define WMAC0_TXOLE_TXOLE_R1_TESTBUS_UPPER___S 0 + +#define WMAC0_TXOLE_TXOLE_R1_SM_STATES (0x00A9F01C) +#define WMAC0_TXOLE_TXOLE_R1_SM_STATES___RWC QCSR_REG_RO +#define WMAC0_TXOLE_TXOLE_R1_SM_STATES___POR 0x00000000 +#define WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_TXOLE_TXDMA_TLV___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_CMN_PARSER_DEC_2___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_CMN_PARSER_DEC___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_FLUSH_REQ___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_PARTIAL_CHECKSUM___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_CMN_PARSER_ENC___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_CMD_FIFO_WRITE___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_ENCAP___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_TXOLE___POR 0x00 +#define WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_TXOLE_TXDMA_TLV___M 0x18000000 +#define WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_TXOLE_TXDMA_TLV___S 27 +#define WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_CMN_PARSER_DEC_2___M 0x06000000 +#define WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_CMN_PARSER_DEC_2___S 25 +#define WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_CMN_PARSER_DEC___M 0x01E00000 +#define WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_CMN_PARSER_DEC___S 21 +#define WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_FLUSH_REQ___M 0x00180000 +#define WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_FLUSH_REQ___S 19 +#define WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_PARTIAL_CHECKSUM___M 0x00070000 +#define WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_PARTIAL_CHECKSUM___S 16 +#define WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_CMN_PARSER_ENC___M 0x0000E000 +#define WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_CMN_PARSER_ENC___S 13 +#define WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_CMD_FIFO_WRITE___M 0x00001C00 +#define WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_CMD_FIFO_WRITE___S 10 +#define WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_ENCAP___M 0x000003C0 +#define WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_ENCAP___S 6 +#define WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_TXOLE___M 0x0000003F +#define WMAC0_TXOLE_TXOLE_R1_SM_STATES__STATE_TXOLE___S 0 +#define WMAC0_TXOLE_TXOLE_R1_SM_STATES___M 0x1FFFFFFF +#define WMAC0_TXOLE_TXOLE_R1_SM_STATES___S 0 + +#define WMAC0_TXOLE_TXOLE_R1_WATCHDOG_INTR_STATUS (0x00A9F020) +#define WMAC0_TXOLE_TXOLE_R1_WATCHDOG_INTR_STATUS___RWC QCSR_REG_RO +#define WMAC0_TXOLE_TXOLE_R1_WATCHDOG_INTR_STATUS___POR 0x00000000 +#define WMAC0_TXOLE_TXOLE_R1_WATCHDOG_INTR_STATUS__TX___POR 0x0 +#define WMAC0_TXOLE_TXOLE_R1_WATCHDOG_INTR_STATUS__TX___M 0x00000001 +#define WMAC0_TXOLE_TXOLE_R1_WATCHDOG_INTR_STATUS__TX___S 0 +#define WMAC0_TXOLE_TXOLE_R1_WATCHDOG_INTR_STATUS___M 0x00000001 +#define WMAC0_TXOLE_TXOLE_R1_WATCHDOG_INTR_STATUS___S 0 + +#define WMAC0_TXOLE_TXOLE_R1_INVALID_APB_ACC_ADR (0x00A9F024) +#define WMAC0_TXOLE_TXOLE_R1_INVALID_APB_ACC_ADR___RWC QCSR_REG_RO +#define WMAC0_TXOLE_TXOLE_R1_INVALID_APB_ACC_ADR___POR 0x00000000 +#define WMAC0_TXOLE_TXOLE_R1_INVALID_APB_ACC_ADR__VALUE___POR 0x00000 +#define WMAC0_TXOLE_TXOLE_R1_INVALID_APB_ACC_ADR__VALUE___M 0x0001FFFF +#define WMAC0_TXOLE_TXOLE_R1_INVALID_APB_ACC_ADR__VALUE___S 0 +#define WMAC0_TXOLE_TXOLE_R1_INVALID_APB_ACC_ADR___M 0x0001FFFF +#define WMAC0_TXOLE_TXOLE_R1_INVALID_APB_ACC_ADR___S 0 + +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0 (0x00AA1000) +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0___RWC QCSR_REG_RO +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0___POR 0x00000000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_LEN___POR 0x000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_ID___POR 0x00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_LEN___M 0x000FFF00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_LEN___S 8 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_ID___M 0x000000FF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0__HDR_ID___S 0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0___M 0x000FFFFF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_0___S 0 + +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1 (0x00AA1004) +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1___RWC QCSR_REG_RO +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1___POR 0x0000002B +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_LEN___POR 0x000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_ID___POR 0x2B +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_LEN___M 0x000FFF00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_LEN___S 8 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_ID___M 0x000000FF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1__HDR_ID___S 0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1___M 0x000FFFFF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_1___S 0 + +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2 (0x00AA1008) +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2___RWC QCSR_REG_RO +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2___POR 0x0000003C +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_LEN___POR 0x000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_ID___POR 0x3C +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_LEN___M 0x000FFF00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_LEN___S 8 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_ID___M 0x000000FF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2__HDR_ID___S 0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2___M 0x000FFFFF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_2___S 0 + +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3 (0x00AA100C) +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3___RWC QCSR_REG_RO +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3___POR 0x00000033 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_LEN___POR 0x000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_ID___POR 0x33 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_LEN___M 0x000FFF00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_LEN___S 8 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_ID___M 0x000000FF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3__HDR_ID___S 0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3___M 0x000FFFFF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_3___S 0 + +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4 (0x00AA1010) +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4___RWC QCSR_REG_RO +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4___POR 0x00000887 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_LEN___POR 0x008 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_ID___POR 0x87 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_LEN___M 0x000FFF00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_LEN___S 8 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_ID___M 0x000000FF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4__HDR_ID___S 0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4___M 0x000FFFFF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_4___S 0 + +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5 (0x00AA1014) +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5___RWC QCSR_REG_RO +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5___POR 0x0000082C +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_LEN___POR 0x008 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_ID___POR 0x2C +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_LEN___M 0x000FFF00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_LEN___S 8 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_ID___M 0x000000FF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5__HDR_ID___S 0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5___M 0x000FFFFF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_5___S 0 + +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6 (0x00AA1018) +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6___RWC QCSR_REG_RW +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6___POR 0x00000000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_LEN___POR 0x000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_ID___POR 0x00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_LEN___M 0x000FFF00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_LEN___S 8 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_ID___M 0x000000FF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6__HDR_ID___S 0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6___M 0x000FFFFF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_6___S 0 + +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7 (0x00AA101C) +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7___RWC QCSR_REG_RW +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7___POR 0x00000000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_LEN___POR 0x000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_ID___POR 0x00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_LEN___M 0x000FFF00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_LEN___S 8 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_ID___M 0x000000FF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7__HDR_ID___S 0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7___M 0x000FFFFF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_7___S 0 + +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8 (0x00AA1020) +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8___RWC QCSR_REG_RW +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8___POR 0x00000000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_LEN___POR 0x000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_ID___POR 0x00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_LEN___M 0x000FFF00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_LEN___S 8 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_ID___M 0x000000FF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8__HDR_ID___S 0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8___M 0x000FFFFF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_8___S 0 + +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9 (0x00AA1024) +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9___RWC QCSR_REG_RW +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9___POR 0x00000000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_LEN___POR 0x000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_ID___POR 0x00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_LEN___M 0x000FFF00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_LEN___S 8 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_ID___M 0x000000FF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9__HDR_ID___S 0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9___M 0x000FFFFF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_9___S 0 + +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10 (0x00AA1028) +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10___RWC QCSR_REG_RW +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10___POR 0x00000000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_LEN___POR 0x000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_ID___POR 0x00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_LEN___M 0x000FFF00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_LEN___S 8 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_ID___M 0x000000FF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10__HDR_ID___S 0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10___M 0x000FFFFF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_10___S 0 + +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11 (0x00AA102C) +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11___RWC QCSR_REG_RW +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11___POR 0x00000000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_LEN___POR 0x000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_ID___POR 0x00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_LEN___M 0x000FFF00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_LEN___S 8 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_ID___M 0x000000FF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11__HDR_ID___S 0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11___M 0x000FFFFF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_11___S 0 + +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12 (0x00AA1030) +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12___RWC QCSR_REG_RW +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12___POR 0x00000000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_LEN___POR 0x000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_ID___POR 0x00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_LEN___M 0x000FFF00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_LEN___S 8 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_ID___M 0x000000FF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12__HDR_ID___S 0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12___M 0x000FFFFF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_12___S 0 + +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13 (0x00AA1034) +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13___RWC QCSR_REG_RW +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13___POR 0x00000000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_LEN___POR 0x000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_ID___POR 0x00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_LEN___M 0x000FFF00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_LEN___S 8 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_ID___M 0x000000FF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13__HDR_ID___S 0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13___M 0x000FFFFF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_13___S 0 + +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14 (0x00AA1038) +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14___RWC QCSR_REG_RW +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14___POR 0x00000000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_LEN___POR 0x000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_ID___POR 0x00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_LEN___M 0x000FFF00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_LEN___S 8 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_ID___M 0x000000FF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14__HDR_ID___S 0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14___M 0x000FFFFF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_14___S 0 + +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15 (0x00AA103C) +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15___RWC QCSR_REG_RW +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15___POR 0x00000000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_LEN___POR 0x000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_ID___POR 0x00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_LEN___M 0x000FFF00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_LEN___S 8 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_ID___M 0x000000FF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15__HDR_ID___S 0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15___M 0x000FFFFF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_EXTN_HDR_IX_15___S 0 + +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN (0x00AA1040) +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN___RWC QCSR_REG_RW +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN___POR 0x00000000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS1___POR 0x0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS0___POR 0x0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS1___M 0x000000F0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS1___S 4 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS0___M 0x0000000F +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN__HEADERS0___S 0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN___M 0x000000FF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_EN___S 0 + +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0 (0x00AA1044) +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0___RWC QCSR_REG_RW +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0___POR 0x00000000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL3___POR 0x00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL2___POR 0x00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL1___POR 0x00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL0___POR 0x00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL3___M 0xFF000000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL3___S 24 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL2___M 0x00FF0000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL2___S 16 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL1___M 0x0000FF00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL1___S 8 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL0___M 0x000000FF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0__SEL0___S 0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0___M 0xFFFFFFFF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_0___S 0 + +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1 (0x00AA1048) +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1___RWC QCSR_REG_RW +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1___POR 0x00000000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL7___POR 0x00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL6___POR 0x00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL5___POR 0x00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL4___POR 0x00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL7___M 0xFF000000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL7___S 24 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL6___M 0x00FF0000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL6___S 16 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL5___M 0x0000FF00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL5___S 8 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL4___M 0x000000FF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1__SEL4___S 0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1___M 0xFFFFFFFF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CRC_OPTIONS_HEADERS_IX_1___S 0 + +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG (0x00AA104C) +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG___RWC QCSR_REG_RW +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG___POR 0x00000080 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG__USE_AH_FOR_FLOW_ID___POR 0x0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG__SPI_FROM_AH_OR_ESP___POR 0x0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG__L4_BYTES_EXCEEDED_256___POR 0x0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG__L3_BYTES_EXCEEDED_256___POR 0x0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG__EXT_HEADER_BYTES___POR 0x80 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG__USE_AH_FOR_FLOW_ID___M 0x00000800 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG__USE_AH_FOR_FLOW_ID___S 11 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG__SPI_FROM_AH_OR_ESP___M 0x00000400 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG__SPI_FROM_AH_OR_ESP___S 10 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG__L4_BYTES_EXCEEDED_256___M 0x00000200 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG__L4_BYTES_EXCEEDED_256___S 9 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG__L3_BYTES_EXCEEDED_256___M 0x00000100 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG__L3_BYTES_EXCEEDED_256___S 8 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG__EXT_HEADER_BYTES___M 0x000000FF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG__EXT_HEADER_BYTES___S 0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG___M 0x00000FFF +#define WMAC0_A_TXOLE_PARSER_CP_R0_IPV6_CONFIG___S 0 + +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE (0x00AA1054) +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE___RWC QCSR_REG_RW +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE___POR 0x00000000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CLK_EXTEND___POR 0x0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___POR 0x0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CP_RSRVD___POR 0x000000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CCE_SM___POR 0x0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__NWIFI___POR 0x0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__ETH___POR 0x0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__AMSDU_11AH___POR 0x0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__AMSDU_11AC___POR 0x0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__WIFI___POR 0x0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CORE___POR 0x0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__APB___POR 0x0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CLK_EXTEND___M 0x80000000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CLK_EXTEND___S 31 +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___M 0x40000000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CPU_IF_EXTEND___S 30 +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CP_RSRVD___M 0x3FFFFF00 +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CP_RSRVD___S 8 +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CCE_SM___M 0x00000080 +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CCE_SM___S 7 +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__NWIFI___M 0x00000040 +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__NWIFI___S 6 +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__ETH___M 0x00000020 +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__ETH___S 5 +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__AMSDU_11AH___M 0x00000010 +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__AMSDU_11AH___S 4 +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__AMSDU_11AC___M 0x00000008 +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__AMSDU_11AC___S 3 +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__WIFI___M 0x00000004 +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__WIFI___S 2 +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CORE___M 0x00000002 +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__CORE___S 1 +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__APB___M 0x00000001 +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE__APB___S 0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE___M 0xFFFFFFFF +#define WMAC0_A_TXOLE_PARSER_CP_R0_CLKGATE_DISABLE___S 0 + +#define WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG (0x00AA1094) +#define WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG___RWC QCSR_REG_RW +#define WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG___POR 0x0001E110 +#define WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__REPORT_FLOW_ID_OR_HASH_3___POR 0x0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__ETH_MIN_PACKET_LEN___POR 0x003C +#define WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__TIMEOUT_EN___POR 0x0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__ENABLE_C9D1___POR 0x0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__VLAN_LLC_FOR_802_3___POR 0x1 +#define WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__UDP_LITE_PARSE_EN___POR 0x0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__TPID_BITMAP_VALUE___POR 0x10 +#define WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__REPORT_FLOW_ID_OR_HASH_3___M 0x08000000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__REPORT_FLOW_ID_OR_HASH_3___S 27 +#define WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__ETH_MIN_PACKET_LEN___M 0x07FFF800 +#define WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__ETH_MIN_PACKET_LEN___S 11 +#define WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__TIMEOUT_EN___M 0x00000400 +#define WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__TIMEOUT_EN___S 10 +#define WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__ENABLE_C9D1___M 0x00000200 +#define WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__ENABLE_C9D1___S 9 +#define WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__VLAN_LLC_FOR_802_3___M 0x00000100 +#define WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__VLAN_LLC_FOR_802_3___S 8 +#define WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__UDP_LITE_PARSE_EN___M 0x00000020 +#define WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__UDP_LITE_PARSE_EN___S 5 +#define WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__TPID_BITMAP_VALUE___M 0x0000001F +#define WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG__TPID_BITMAP_VALUE___S 0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG___M 0x0FFFFF3F +#define WMAC0_A_TXOLE_PARSER_CP_R0_MISC_CONFIG___S 0 + +#define WMAC0_A_TXOLE_PARSER_CP_R0_WATCHDOG_TIMER (0x00AA1098) +#define WMAC0_A_TXOLE_PARSER_CP_R0_WATCHDOG_TIMER___RWC QCSR_REG_RW +#define WMAC0_A_TXOLE_PARSER_CP_R0_WATCHDOG_TIMER___POR 0x00000000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_WATCHDOG_TIMER__VALUE___POR 0x00000000 +#define WMAC0_A_TXOLE_PARSER_CP_R0_WATCHDOG_TIMER__ENABLE___POR 0x0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_WATCHDOG_TIMER__VALUE___M 0xFFFFFFFE +#define WMAC0_A_TXOLE_PARSER_CP_R0_WATCHDOG_TIMER__VALUE___S 1 +#define WMAC0_A_TXOLE_PARSER_CP_R0_WATCHDOG_TIMER__ENABLE___M 0x00000001 +#define WMAC0_A_TXOLE_PARSER_CP_R0_WATCHDOG_TIMER__ENABLE___S 0 +#define WMAC0_A_TXOLE_PARSER_CP_R0_WATCHDOG_TIMER___M 0xFFFFFFFF +#define WMAC0_A_TXOLE_PARSER_CP_R0_WATCHDOG_TIMER___S 0 + +#define WMAC0_A_TXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL (0x00AA2000) +#define WMAC0_A_TXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL___RWC QCSR_REG_RW +#define WMAC0_A_TXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL___POR 0x7FFE0002 +#define WMAC0_A_TXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___POR 0x3FFF +#define WMAC0_A_TXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___POR 0x0000 +#define WMAC0_A_TXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___POR 0x1 +#define WMAC0_A_TXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___POR 0x0 +#define WMAC0_A_TXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___M 0xFFFE0000 +#define WMAC0_A_TXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___S 17 +#define WMAC0_A_TXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___M 0x0001FFFC +#define WMAC0_A_TXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___S 2 +#define WMAC0_A_TXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___M 0x00000002 +#define WMAC0_A_TXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___S 1 +#define WMAC0_A_TXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___M 0x00000001 +#define WMAC0_A_TXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___S 0 +#define WMAC0_A_TXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL___M 0xFFFFFFFF +#define WMAC0_A_TXOLE_PARSER_CP_R1_REG_ACCESS_EVENT_GEN_CTRL___S 0 + +#define WMAC0_A_TXOLE_PARSER_CP_R1_SM_STATES (0x00AA2004) +#define WMAC0_A_TXOLE_PARSER_CP_R1_SM_STATES___RWC QCSR_REG_RO +#define WMAC0_A_TXOLE_PARSER_CP_R1_SM_STATES___POR 0x00000000 +#define WMAC0_A_TXOLE_PARSER_CP_R1_SM_STATES__MISC___POR 0x000000 +#define WMAC0_A_TXOLE_PARSER_CP_R1_SM_STATES__STATE_INFO___POR 0x00 +#define WMAC0_A_TXOLE_PARSER_CP_R1_SM_STATES__STATE_MAIN___POR 0x00 +#define WMAC0_A_TXOLE_PARSER_CP_R1_SM_STATES__MISC___M 0xFFFFFC00 +#define WMAC0_A_TXOLE_PARSER_CP_R1_SM_STATES__MISC___S 10 +#define WMAC0_A_TXOLE_PARSER_CP_R1_SM_STATES__STATE_INFO___M 0x000003E0 +#define WMAC0_A_TXOLE_PARSER_CP_R1_SM_STATES__STATE_INFO___S 5 +#define WMAC0_A_TXOLE_PARSER_CP_R1_SM_STATES__STATE_MAIN___M 0x0000001F +#define WMAC0_A_TXOLE_PARSER_CP_R1_SM_STATES__STATE_MAIN___S 0 +#define WMAC0_A_TXOLE_PARSER_CP_R1_SM_STATES___M 0xFFFFFFFF +#define WMAC0_A_TXOLE_PARSER_CP_R1_SM_STATES___S 0 + +#define WMAC0_A_TXOLE_PARSER_CP_R1_END_OF_TEST_CHECK (0x00AA2008) +#define WMAC0_A_TXOLE_PARSER_CP_R1_END_OF_TEST_CHECK___RWC QCSR_REG_RW +#define WMAC0_A_TXOLE_PARSER_CP_R1_END_OF_TEST_CHECK___POR 0x00000000 +#define WMAC0_A_TXOLE_PARSER_CP_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0 +#define WMAC0_A_TXOLE_PARSER_CP_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001 +#define WMAC0_A_TXOLE_PARSER_CP_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S 0 +#define WMAC0_A_TXOLE_PARSER_CP_R1_END_OF_TEST_CHECK___M 0x00000001 +#define WMAC0_A_TXOLE_PARSER_CP_R1_END_OF_TEST_CHECK___S 0 + +#define WMAC0_RRI_R0_SW_REG_REINIT_P (0x00AA4000) +#define WMAC0_RRI_R0_SW_REG_REINIT_P___RWC QCSR_REG_RW +#define WMAC0_RRI_R0_SW_REG_REINIT_P___POR 0x00000000 +#define WMAC0_RRI_R0_SW_REG_REINIT_P__SPARE___POR 0x00000000 +#define WMAC0_RRI_R0_SW_REG_REINIT_P__VAL___POR 0x0 +#define WMAC0_RRI_R0_SW_REG_REINIT_P__SPARE___M 0xFFFFFFFE +#define WMAC0_RRI_R0_SW_REG_REINIT_P__SPARE___S 1 +#define WMAC0_RRI_R0_SW_REG_REINIT_P__VAL___M 0x00000001 +#define WMAC0_RRI_R0_SW_REG_REINIT_P__VAL___S 0 +#define WMAC0_RRI_R0_SW_REG_REINIT_P___M 0xFFFFFFFF +#define WMAC0_RRI_R0_SW_REG_REINIT_P___S 0 + +#define WMAC0_RRI_R0_SW_REG_REINIT_ADDR (0x00AA4004) +#define WMAC0_RRI_R0_SW_REG_REINIT_ADDR___RWC QCSR_REG_RW +#define WMAC0_RRI_R0_SW_REG_REINIT_ADDR___POR 0x00000000 +#define WMAC0_RRI_R0_SW_REG_REINIT_ADDR__VAL___POR 0x00000000 +#define WMAC0_RRI_R0_SW_REG_REINIT_ADDR__VAL___M 0xFFFFFFFC +#define WMAC0_RRI_R0_SW_REG_REINIT_ADDR__VAL___S 2 +#define WMAC0_RRI_R0_SW_REG_REINIT_ADDR___M 0xFFFFFFFC +#define WMAC0_RRI_R0_SW_REG_REINIT_ADDR___S 2 + +#define WMAC0_RRI_R0_MISC_CFG (0x00AA4008) +#define WMAC0_RRI_R0_MISC_CFG___RWC QCSR_REG_RW +#define WMAC0_RRI_R0_MISC_CFG___POR 0x00000000 +#define WMAC0_RRI_R0_MISC_CFG__SPARE___POR 0x0 +#define WMAC0_RRI_R0_MISC_CFG__GOTO_IDLE_FOR_INVALID_CMD___POR 0x0 +#define WMAC0_RRI_R0_MISC_CFG__SW_RRI_DONE_FOR_INVALID_CMD___POR 0x0 +#define WMAC0_RRI_R0_MISC_CFG__SW_REG_REINIT_CMD_EXT_BASE_ADDR___POR 0x00 +#define WMAC0_RRI_R0_MISC_CFG__ENCODED_FSM___POR 0x00 +#define WMAC0_RRI_R0_MISC_CFG__SPARE2___POR 0x0 +#define WMAC0_RRI_R0_MISC_CFG__GOTO_IDLE___POR 0x0 +#define WMAC0_RRI_R0_MISC_CFG__ERR_STATE_CFG___POR 0x0 +#define WMAC0_RRI_R0_MISC_CFG__ERR_EXIT___POR 0x0 +#define WMAC0_RRI_R0_MISC_CFG__ONE_USEC_LIMIT___POR 0x00 +#define WMAC0_RRI_R0_MISC_CFG__SPARE___M 0xC0000000 +#define WMAC0_RRI_R0_MISC_CFG__SPARE___S 30 +#define WMAC0_RRI_R0_MISC_CFG__GOTO_IDLE_FOR_INVALID_CMD___M 0x20000000 +#define WMAC0_RRI_R0_MISC_CFG__GOTO_IDLE_FOR_INVALID_CMD___S 29 +#define WMAC0_RRI_R0_MISC_CFG__SW_RRI_DONE_FOR_INVALID_CMD___M 0x10000000 +#define WMAC0_RRI_R0_MISC_CFG__SW_RRI_DONE_FOR_INVALID_CMD___S 28 +#define WMAC0_RRI_R0_MISC_CFG__SW_REG_REINIT_CMD_EXT_BASE_ADDR___M 0x0FF00000 +#define WMAC0_RRI_R0_MISC_CFG__SW_REG_REINIT_CMD_EXT_BASE_ADDR___S 20 +#define WMAC0_RRI_R0_MISC_CFG__ENCODED_FSM___M 0x000F8000 +#define WMAC0_RRI_R0_MISC_CFG__ENCODED_FSM___S 15 +#define WMAC0_RRI_R0_MISC_CFG__SPARE2___M 0x00007800 +#define WMAC0_RRI_R0_MISC_CFG__SPARE2___S 11 +#define WMAC0_RRI_R0_MISC_CFG__GOTO_IDLE___M 0x00000400 +#define WMAC0_RRI_R0_MISC_CFG__GOTO_IDLE___S 10 +#define WMAC0_RRI_R0_MISC_CFG__ERR_STATE_CFG___M 0x00000200 +#define WMAC0_RRI_R0_MISC_CFG__ERR_STATE_CFG___S 9 +#define WMAC0_RRI_R0_MISC_CFG__ERR_EXIT___M 0x00000100 +#define WMAC0_RRI_R0_MISC_CFG__ERR_EXIT___S 8 +#define WMAC0_RRI_R0_MISC_CFG__ONE_USEC_LIMIT___M 0x000000FF +#define WMAC0_RRI_R0_MISC_CFG__ONE_USEC_LIMIT___S 0 +#define WMAC0_RRI_R0_MISC_CFG___M 0xFFFFFFFF +#define WMAC0_RRI_R0_MISC_CFG___S 0 + +#define WMAC0_RRI_R0_MEM_RANGE_START (0x00AA400C) +#define WMAC0_RRI_R0_MEM_RANGE_START___RWC QCSR_REG_RW +#define WMAC0_RRI_R0_MEM_RANGE_START___POR 0x00000000 +#define WMAC0_RRI_R0_MEM_RANGE_START__ADDR___POR 0x00000000 +#define WMAC0_RRI_R0_MEM_RANGE_START__ADDR___M 0xFFFFFFFF +#define WMAC0_RRI_R0_MEM_RANGE_START__ADDR___S 0 +#define WMAC0_RRI_R0_MEM_RANGE_START___M 0xFFFFFFFF +#define WMAC0_RRI_R0_MEM_RANGE_START___S 0 + +#define WMAC0_RRI_R0_MEM_RANGE_END (0x00AA4010) +#define WMAC0_RRI_R0_MEM_RANGE_END___RWC QCSR_REG_RW +#define WMAC0_RRI_R0_MEM_RANGE_END___POR 0x0000407F +#define WMAC0_RRI_R0_MEM_RANGE_END__ADDR___POR 0x0000407F +#define WMAC0_RRI_R0_MEM_RANGE_END__ADDR___M 0xFFFFFFFF +#define WMAC0_RRI_R0_MEM_RANGE_END__ADDR___S 0 +#define WMAC0_RRI_R0_MEM_RANGE_END___M 0xFFFFFFFF +#define WMAC0_RRI_R0_MEM_RANGE_END___S 0 + +#define WMAC0_RRI_R0_PMM_DONE_EXTEND_PULSE (0x00AA4014) +#define WMAC0_RRI_R0_PMM_DONE_EXTEND_PULSE___RWC QCSR_REG_RW +#define WMAC0_RRI_R0_PMM_DONE_EXTEND_PULSE___POR 0x00000000 +#define WMAC0_RRI_R0_PMM_DONE_EXTEND_PULSE__VAL___POR 0x00 +#define WMAC0_RRI_R0_PMM_DONE_EXTEND_PULSE__VAL___M 0x0000003F +#define WMAC0_RRI_R0_PMM_DONE_EXTEND_PULSE__VAL___S 0 +#define WMAC0_RRI_R0_PMM_DONE_EXTEND_PULSE___M 0x0000003F +#define WMAC0_RRI_R0_PMM_DONE_EXTEND_PULSE___S 0 + +#define WMAC0_RRI_R0_TRC_REG_REINIT_ADDR (0x00AA4018) +#define WMAC0_RRI_R0_TRC_REG_REINIT_ADDR___RWC QCSR_REG_RW +#define WMAC0_RRI_R0_TRC_REG_REINIT_ADDR___POR 0x00000000 +#define WMAC0_RRI_R0_TRC_REG_REINIT_ADDR__VAL___POR 0x00000000 +#define WMAC0_RRI_R0_TRC_REG_REINIT_ADDR__VAL___M 0xFFFFFFFC +#define WMAC0_RRI_R0_TRC_REG_REINIT_ADDR__VAL___S 2 +#define WMAC0_RRI_R0_TRC_REG_REINIT_ADDR___M 0xFFFFFFFC +#define WMAC0_RRI_R0_TRC_REG_REINIT_ADDR___S 2 + +#define WMAC0_RRI_R1_POLL_CMD_ERR_ADDR (0x00AA5000) +#define WMAC0_RRI_R1_POLL_CMD_ERR_ADDR___RWC QCSR_REG_RO +#define WMAC0_RRI_R1_POLL_CMD_ERR_ADDR___POR 0x00000000 +#define WMAC0_RRI_R1_POLL_CMD_ERR_ADDR__VAL___POR 0x00000000 +#define WMAC0_RRI_R1_POLL_CMD_ERR_ADDR__VAL___M 0xFFFFFFFC +#define WMAC0_RRI_R1_POLL_CMD_ERR_ADDR__VAL___S 2 +#define WMAC0_RRI_R1_POLL_CMD_ERR_ADDR___M 0xFFFFFFFC +#define WMAC0_RRI_R1_POLL_CMD_ERR_ADDR___S 2 + +#define WMAC0_RRI_R1_ERR_INT_P (0x00AA5004) +#define WMAC0_RRI_R1_ERR_INT_P___RWC QCSR_REG_RO +#define WMAC0_RRI_R1_ERR_INT_P___POR 0x00000000 +#define WMAC0_RRI_R1_ERR_INT_P__SW_TRIG_REININT_DONE___POR 0x0 +#define WMAC0_RRI_R1_ERR_INT_P__POLL_CMD_ERR___POR 0x0 +#define WMAC0_RRI_R1_ERR_INT_P__APB_ERR___POR 0x0 +#define WMAC0_RRI_R1_ERR_INT_P__SW_TRIG_REININT_DONE___M 0x00000004 +#define WMAC0_RRI_R1_ERR_INT_P__SW_TRIG_REININT_DONE___S 2 +#define WMAC0_RRI_R1_ERR_INT_P__POLL_CMD_ERR___M 0x00000002 +#define WMAC0_RRI_R1_ERR_INT_P__POLL_CMD_ERR___S 1 +#define WMAC0_RRI_R1_ERR_INT_P__APB_ERR___M 0x00000001 +#define WMAC0_RRI_R1_ERR_INT_P__APB_ERR___S 0 +#define WMAC0_RRI_R1_ERR_INT_P___M 0x00000007 +#define WMAC0_RRI_R1_ERR_INT_P___S 0 + +#define WMAC0_RRI_R1_ERR_INT_BITMASK (0x00AA5008) +#define WMAC0_RRI_R1_ERR_INT_BITMASK___RWC QCSR_REG_RW +#define WMAC0_RRI_R1_ERR_INT_BITMASK___POR 0x00000080 +#define WMAC0_RRI_R1_ERR_INT_BITMASK__INVALID_CMD_ERR___POR 0x0 +#define WMAC0_RRI_R1_ERR_INT_BITMASK__TRC_TRIG_REINIT_DONE___POR 0x1 +#define WMAC0_RRI_R1_ERR_INT_BITMASK__APB_STATE_TIMEOUT_ERR___POR 0x0 +#define WMAC0_RRI_R1_ERR_INT_BITMASK__APB_RD_INVALID_ADDR___POR 0x0 +#define WMAC0_RRI_R1_ERR_INT_BITMASK__APB_WR_INVALID_ADDR___POR 0x0 +#define WMAC0_RRI_R1_ERR_INT_BITMASK__APB_WR_TO_RD_ONLY_ADDR___POR 0x0 +#define WMAC0_RRI_R1_ERR_INT_BITMASK__SW_TRIG_REININT_DONE___POR 0x0 +#define WMAC0_RRI_R1_ERR_INT_BITMASK__POLL_CMD_ERR___POR 0x0 +#define WMAC0_RRI_R1_ERR_INT_BITMASK__APB_ERR___POR 0x0 +#define WMAC0_RRI_R1_ERR_INT_BITMASK__INVALID_CMD_ERR___M 0x00000100 +#define WMAC0_RRI_R1_ERR_INT_BITMASK__INVALID_CMD_ERR___S 8 +#define WMAC0_RRI_R1_ERR_INT_BITMASK__TRC_TRIG_REINIT_DONE___M 0x00000080 +#define WMAC0_RRI_R1_ERR_INT_BITMASK__TRC_TRIG_REINIT_DONE___S 7 +#define WMAC0_RRI_R1_ERR_INT_BITMASK__APB_STATE_TIMEOUT_ERR___M 0x00000040 +#define WMAC0_RRI_R1_ERR_INT_BITMASK__APB_STATE_TIMEOUT_ERR___S 6 +#define WMAC0_RRI_R1_ERR_INT_BITMASK__APB_RD_INVALID_ADDR___M 0x00000020 +#define WMAC0_RRI_R1_ERR_INT_BITMASK__APB_RD_INVALID_ADDR___S 5 +#define WMAC0_RRI_R1_ERR_INT_BITMASK__APB_WR_INVALID_ADDR___M 0x00000010 +#define WMAC0_RRI_R1_ERR_INT_BITMASK__APB_WR_INVALID_ADDR___S 4 +#define WMAC0_RRI_R1_ERR_INT_BITMASK__APB_WR_TO_RD_ONLY_ADDR___M 0x00000008 +#define WMAC0_RRI_R1_ERR_INT_BITMASK__APB_WR_TO_RD_ONLY_ADDR___S 3 +#define WMAC0_RRI_R1_ERR_INT_BITMASK__SW_TRIG_REININT_DONE___M 0x00000004 +#define WMAC0_RRI_R1_ERR_INT_BITMASK__SW_TRIG_REININT_DONE___S 2 +#define WMAC0_RRI_R1_ERR_INT_BITMASK__POLL_CMD_ERR___M 0x00000002 +#define WMAC0_RRI_R1_ERR_INT_BITMASK__POLL_CMD_ERR___S 1 +#define WMAC0_RRI_R1_ERR_INT_BITMASK__APB_ERR___M 0x00000001 +#define WMAC0_RRI_R1_ERR_INT_BITMASK__APB_ERR___S 0 +#define WMAC0_RRI_R1_ERR_INT_BITMASK___M 0x000001FF +#define WMAC0_RRI_R1_ERR_INT_BITMASK___S 0 + +#define WMAC0_RRI_R1_ERR_INT_STATUS (0x00AA500C) +#define WMAC0_RRI_R1_ERR_INT_STATUS___RWC QCSR_REG_RW +#define WMAC0_RRI_R1_ERR_INT_STATUS___POR 0x00000000 +#define WMAC0_RRI_R1_ERR_INT_STATUS__INVALID_CMD_ERR___POR 0x0 +#define WMAC0_RRI_R1_ERR_INT_STATUS__TRC_TRIG_REINIT_DONE___POR 0x0 +#define WMAC0_RRI_R1_ERR_INT_STATUS__APB_STATE_TIMEOUT_ERR___POR 0x0 +#define WMAC0_RRI_R1_ERR_INT_STATUS__APB_RD_INVALID_ADDR___POR 0x0 +#define WMAC0_RRI_R1_ERR_INT_STATUS__APB_WR_INVALID_ADDR___POR 0x0 +#define WMAC0_RRI_R1_ERR_INT_STATUS__APB_WR_TO_RD_ONLY_ADDR___POR 0x0 +#define WMAC0_RRI_R1_ERR_INT_STATUS__SW_TRIG_REININT_DONE___POR 0x0 +#define WMAC0_RRI_R1_ERR_INT_STATUS__POLL_CMD_ERR___POR 0x0 +#define WMAC0_RRI_R1_ERR_INT_STATUS__APB_ERR___POR 0x0 +#define WMAC0_RRI_R1_ERR_INT_STATUS__INVALID_CMD_ERR___M 0x00000100 +#define WMAC0_RRI_R1_ERR_INT_STATUS__INVALID_CMD_ERR___S 8 +#define WMAC0_RRI_R1_ERR_INT_STATUS__TRC_TRIG_REINIT_DONE___M 0x00000080 +#define WMAC0_RRI_R1_ERR_INT_STATUS__TRC_TRIG_REINIT_DONE___S 7 +#define WMAC0_RRI_R1_ERR_INT_STATUS__APB_STATE_TIMEOUT_ERR___M 0x00000040 +#define WMAC0_RRI_R1_ERR_INT_STATUS__APB_STATE_TIMEOUT_ERR___S 6 +#define WMAC0_RRI_R1_ERR_INT_STATUS__APB_RD_INVALID_ADDR___M 0x00000020 +#define WMAC0_RRI_R1_ERR_INT_STATUS__APB_RD_INVALID_ADDR___S 5 +#define WMAC0_RRI_R1_ERR_INT_STATUS__APB_WR_INVALID_ADDR___M 0x00000010 +#define WMAC0_RRI_R1_ERR_INT_STATUS__APB_WR_INVALID_ADDR___S 4 +#define WMAC0_RRI_R1_ERR_INT_STATUS__APB_WR_TO_RD_ONLY_ADDR___M 0x00000008 +#define WMAC0_RRI_R1_ERR_INT_STATUS__APB_WR_TO_RD_ONLY_ADDR___S 3 +#define WMAC0_RRI_R1_ERR_INT_STATUS__SW_TRIG_REININT_DONE___M 0x00000004 +#define WMAC0_RRI_R1_ERR_INT_STATUS__SW_TRIG_REININT_DONE___S 2 +#define WMAC0_RRI_R1_ERR_INT_STATUS__POLL_CMD_ERR___M 0x00000002 +#define WMAC0_RRI_R1_ERR_INT_STATUS__POLL_CMD_ERR___S 1 +#define WMAC0_RRI_R1_ERR_INT_STATUS__APB_ERR___M 0x00000001 +#define WMAC0_RRI_R1_ERR_INT_STATUS__APB_ERR___S 0 +#define WMAC0_RRI_R1_ERR_INT_STATUS___M 0x000001FF +#define WMAC0_RRI_R1_ERR_INT_STATUS___S 0 + +#define WMAC0_RRI_R1_CURRENT_ADDR (0x00AA5010) +#define WMAC0_RRI_R1_CURRENT_ADDR___RWC QCSR_REG_RO +#define WMAC0_RRI_R1_CURRENT_ADDR___POR 0x00000000 +#define WMAC0_RRI_R1_CURRENT_ADDR__VAL___POR 0x00000000 +#define WMAC0_RRI_R1_CURRENT_ADDR__VAL___M 0xFFFFFFFF +#define WMAC0_RRI_R1_CURRENT_ADDR__VAL___S 0 +#define WMAC0_RRI_R1_CURRENT_ADDR___M 0xFFFFFFFF +#define WMAC0_RRI_R1_CURRENT_ADDR___S 0 + +#define WMAC0_RRI_R1_EVENTMASK_IX_0 (0x00AA5014) +#define WMAC0_RRI_R1_EVENTMASK_IX_0___RWC QCSR_REG_RW +#define WMAC0_RRI_R1_EVENTMASK_IX_0___POR 0x00000000 +#define WMAC0_RRI_R1_EVENTMASK_IX_0__MASK___POR 0x0000000 +#define WMAC0_RRI_R1_EVENTMASK_IX_0__MASK___M 0x03FFFFFF +#define WMAC0_RRI_R1_EVENTMASK_IX_0__MASK___S 0 +#define WMAC0_RRI_R1_EVENTMASK_IX_0___M 0x03FFFFFF +#define WMAC0_RRI_R1_EVENTMASK_IX_0___S 0 + +#define WMAC0_RRI_R1_INVALID_APB_ACC_ADR (0x00AA5018) +#define WMAC0_RRI_R1_INVALID_APB_ACC_ADR___RWC QCSR_REG_RO +#define WMAC0_RRI_R1_INVALID_APB_ACC_ADR___POR 0x00000000 +#define WMAC0_RRI_R1_INVALID_APB_ACC_ADR__VAL___POR 0x00000 +#define WMAC0_RRI_R1_INVALID_APB_ACC_ADR__VAL___M 0x0001FFFF +#define WMAC0_RRI_R1_INVALID_APB_ACC_ADR__VAL___S 0 +#define WMAC0_RRI_R1_INVALID_APB_ACC_ADR___M 0x0001FFFF +#define WMAC0_RRI_R1_INVALID_APB_ACC_ADR___S 0 + +#define WMAC0_RRI_R1_SM_STATES_IX_0 (0x00AA501C) +#define WMAC0_RRI_R1_SM_STATES_IX_0___RWC QCSR_REG_RO +#define WMAC0_RRI_R1_SM_STATES_IX_0___POR 0x00000000 +#define WMAC0_RRI_R1_SM_STATES_IX_0__SM_STATE_MEM___POR 0x0 +#define WMAC0_RRI_R1_SM_STATES_IX_0__SM_STATE_APB___POR 0x00 +#define WMAC0_RRI_R1_SM_STATES_IX_0__SM_STATE_CMD___POR 0x00 +#define WMAC0_RRI_R1_SM_STATES_IX_0__SM_STATE_MEM___M 0x0000E000 +#define WMAC0_RRI_R1_SM_STATES_IX_0__SM_STATE_MEM___S 13 +#define WMAC0_RRI_R1_SM_STATES_IX_0__SM_STATE_APB___M 0x00001FE0 +#define WMAC0_RRI_R1_SM_STATES_IX_0__SM_STATE_APB___S 5 +#define WMAC0_RRI_R1_SM_STATES_IX_0__SM_STATE_CMD___M 0x0000001F +#define WMAC0_RRI_R1_SM_STATES_IX_0__SM_STATE_CMD___S 0 +#define WMAC0_RRI_R1_SM_STATES_IX_0___M 0x0000FFFF +#define WMAC0_RRI_R1_SM_STATES_IX_0___S 0 + +#define WMAC0_RRI_R1_ACTIVE (0x00AA5020) +#define WMAC0_RRI_R1_ACTIVE___RWC QCSR_REG_RO +#define WMAC0_RRI_R1_ACTIVE___POR 0x00000000 +#define WMAC0_RRI_R1_ACTIVE__VAL___POR 0x0 +#define WMAC0_RRI_R1_ACTIVE__VAL___M 0x00000001 +#define WMAC0_RRI_R1_ACTIVE__VAL___S 0 +#define WMAC0_RRI_R1_ACTIVE___M 0x00000001 +#define WMAC0_RRI_R1_ACTIVE___S 0 + +#define WMAC0_RRI_R1_APB_TIMEOUT (0x00AA5024) +#define WMAC0_RRI_R1_APB_TIMEOUT___RWC QCSR_REG_RW +#define WMAC0_RRI_R1_APB_TIMEOUT___POR 0x000000FF +#define WMAC0_RRI_R1_APB_TIMEOUT__VAL___POR 0x000000FF +#define WMAC0_RRI_R1_APB_TIMEOUT__VAL___M 0xFFFFFFFF +#define WMAC0_RRI_R1_APB_TIMEOUT__VAL___S 0 +#define WMAC0_RRI_R1_APB_TIMEOUT___M 0xFFFFFFFF +#define WMAC0_RRI_R1_APB_TIMEOUT___S 0 + +#define WMAC0_RRI_R1_INVALID_CMD_WORD (0x00AA5028) +#define WMAC0_RRI_R1_INVALID_CMD_WORD___RWC QCSR_REG_RO +#define WMAC0_RRI_R1_INVALID_CMD_WORD___POR 0x00000000 +#define WMAC0_RRI_R1_INVALID_CMD_WORD__VAL___POR 0x00000000 +#define WMAC0_RRI_R1_INVALID_CMD_WORD__VAL___M 0xFFFFFFFF +#define WMAC0_RRI_R1_INVALID_CMD_WORD__VAL___S 0 +#define WMAC0_RRI_R1_INVALID_CMD_WORD___M 0xFFFFFFFF +#define WMAC0_RRI_R1_INVALID_CMD_WORD___S 0 + +#define WMAC0_RRI_R1_TESTBUS_LOWER (0x00AA502C) +#define WMAC0_RRI_R1_TESTBUS_LOWER___RWC QCSR_REG_RO +#define WMAC0_RRI_R1_TESTBUS_LOWER___POR 0x00000000 +#define WMAC0_RRI_R1_TESTBUS_LOWER__VALUE___POR 0x00000000 +#define WMAC0_RRI_R1_TESTBUS_LOWER__VALUE___M 0xFFFFFFFF +#define WMAC0_RRI_R1_TESTBUS_LOWER__VALUE___S 0 +#define WMAC0_RRI_R1_TESTBUS_LOWER___M 0xFFFFFFFF +#define WMAC0_RRI_R1_TESTBUS_LOWER___S 0 + +#define WMAC0_RRI_R1_TESTBUS_UPPER (0x00AA5030) +#define WMAC0_RRI_R1_TESTBUS_UPPER___RWC QCSR_REG_RO +#define WMAC0_RRI_R1_TESTBUS_UPPER___POR 0x00000000 +#define WMAC0_RRI_R1_TESTBUS_UPPER__VALUE___POR 0x00 +#define WMAC0_RRI_R1_TESTBUS_UPPER__VALUE___M 0x000000FF +#define WMAC0_RRI_R1_TESTBUS_UPPER__VALUE___S 0 +#define WMAC0_RRI_R1_TESTBUS_UPPER___M 0x000000FF +#define WMAC0_RRI_R1_TESTBUS_UPPER___S 0 + +#define WMAC0_RRI_R1_ERR_INT_STATUS_MASKED (0x00AA5034) +#define WMAC0_RRI_R1_ERR_INT_STATUS_MASKED___RWC QCSR_REG_RO +#define WMAC0_RRI_R1_ERR_INT_STATUS_MASKED___POR 0x00000000 +#define WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__INVALID_CMD_STATUS___POR 0x0 +#define WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__TRC_TRIG_REINIT_DONE_P_STATUS___POR 0x0 +#define WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__APB_STATE_TIMEOUT_ERR_P_STATUS___POR 0x0 +#define WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__APB_RD_INVALID_ADDR_P_STATUS___POR 0x0 +#define WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__APB_WR_INVALID_ADDR_P_STATUS___POR 0x0 +#define WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__APB_WR_TO_RD_ONLY_ADDR_P_TEMP_STATUS___POR 0x0 +#define WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__SW_TRIG_REININT_DONE_P_STATUS___POR 0x0 +#define WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__POLL_CMD_ERR_STATUS___POR 0x0 +#define WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__APB_ERR_STATUS___POR 0x0 +#define WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__INVALID_CMD_STATUS___M 0x00000100 +#define WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__INVALID_CMD_STATUS___S 8 +#define WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__TRC_TRIG_REINIT_DONE_P_STATUS___M 0x00000080 +#define WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__TRC_TRIG_REINIT_DONE_P_STATUS___S 7 +#define WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__APB_STATE_TIMEOUT_ERR_P_STATUS___M 0x00000040 +#define WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__APB_STATE_TIMEOUT_ERR_P_STATUS___S 6 +#define WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__APB_RD_INVALID_ADDR_P_STATUS___M 0x00000020 +#define WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__APB_RD_INVALID_ADDR_P_STATUS___S 5 +#define WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__APB_WR_INVALID_ADDR_P_STATUS___M 0x00000010 +#define WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__APB_WR_INVALID_ADDR_P_STATUS___S 4 +#define WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__APB_WR_TO_RD_ONLY_ADDR_P_TEMP_STATUS___M 0x00000008 +#define WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__APB_WR_TO_RD_ONLY_ADDR_P_TEMP_STATUS___S 3 +#define WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__SW_TRIG_REININT_DONE_P_STATUS___M 0x00000004 +#define WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__SW_TRIG_REININT_DONE_P_STATUS___S 2 +#define WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__POLL_CMD_ERR_STATUS___M 0x00000002 +#define WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__POLL_CMD_ERR_STATUS___S 1 +#define WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__APB_ERR_STATUS___M 0x00000001 +#define WMAC0_RRI_R1_ERR_INT_STATUS_MASKED__APB_ERR_STATUS___S 0 +#define WMAC0_RRI_R1_ERR_INT_STATUS_MASKED___M 0x000001FF +#define WMAC0_RRI_R1_ERR_INT_STATUS_MASKED___S 0 + +#define WMAC0_RRI_R1_TESTBUS_CTRL (0x00AA5038) +#define WMAC0_RRI_R1_TESTBUS_CTRL___RWC QCSR_REG_RW +#define WMAC0_RRI_R1_TESTBUS_CTRL___POR 0x00000000 +#define WMAC0_RRI_R1_TESTBUS_CTRL__TESTBUS_SELECT___POR 0x0 +#define WMAC0_RRI_R1_TESTBUS_CTRL__TESTBUS_SELECT___M 0x0000000F +#define WMAC0_RRI_R1_TESTBUS_CTRL__TESTBUS_SELECT___S 0 +#define WMAC0_RRI_R1_TESTBUS_CTRL___M 0x0000000F +#define WMAC0_RRI_R1_TESTBUS_CTRL___S 0 + +#define WMAC0_RRI_R1_REG_ACCESS_EVENT_GEN_CTRL (0x00AA503C) +#define WMAC0_RRI_R1_REG_ACCESS_EVENT_GEN_CTRL___RWC QCSR_REG_RW +#define WMAC0_RRI_R1_REG_ACCESS_EVENT_GEN_CTRL___POR 0x7FFE0002 +#define WMAC0_RRI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___POR 0x3FFF +#define WMAC0_RRI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___POR 0x0000 +#define WMAC0_RRI_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___POR 0x1 +#define WMAC0_RRI_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___POR 0x0 +#define WMAC0_RRI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___M 0xFFFE0000 +#define WMAC0_RRI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___S 17 +#define WMAC0_RRI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___M 0x0001FFFC +#define WMAC0_RRI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___S 2 +#define WMAC0_RRI_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___M 0x00000002 +#define WMAC0_RRI_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___S 1 +#define WMAC0_RRI_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___M 0x00000001 +#define WMAC0_RRI_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___S 0 +#define WMAC0_RRI_R1_REG_ACCESS_EVENT_GEN_CTRL___M 0xFFFFFFFF +#define WMAC0_RRI_R1_REG_ACCESS_EVENT_GEN_CTRL___S 0 + +#define WMAC0_RRI_R1_RRI_SPARE_REGISTER (0x00AA5040) +#define WMAC0_RRI_R1_RRI_SPARE_REGISTER___RWC QCSR_REG_RW +#define WMAC0_RRI_R1_RRI_SPARE_REGISTER___POR 0x00000000 +#define WMAC0_RRI_R1_RRI_SPARE_REGISTER__SPARE_FIELD___POR 0x0000 +#define WMAC0_RRI_R1_RRI_SPARE_REGISTER__SPARE_FIELD___M 0x0000FFFF +#define WMAC0_RRI_R1_RRI_SPARE_REGISTER__SPARE_FIELD___S 0 +#define WMAC0_RRI_R1_RRI_SPARE_REGISTER___M 0x0000FFFF +#define WMAC0_RRI_R1_RRI_SPARE_REGISTER___S 0 + +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_0 (0x00AA7000) +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_0___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_0___POR 0x000F478F +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_0__QOS___POR 0x000F +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_0__FC___POR 0x478F +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_0__QOS___M 0xFFFF0000 +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_0__QOS___S 16 +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_0__FC___M 0x0000FFFF +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_0__FC___S 0 +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_0___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_0___S 0 + +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_1 (0x00AA7004) +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_1___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_1___POR 0xC7FF000F +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_1__FC_MGMT___POR 0xC7FF +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_1__SEQ___POR 0x000F +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_1__FC_MGMT___M 0xFFFF0000 +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_1__FC_MGMT___S 16 +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_1__SEQ___M 0x0000FFFF +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_1__SEQ___S 0 +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_1___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_1___S 0 + +#define WMAC0_CRYPTO_R0_MIC_QOS_CONTROL (0x00AA7008) +#define WMAC0_CRYPTO_R0_MIC_QOS_CONTROL___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R0_MIC_QOS_CONTROL___POR 0x000000AA +#define WMAC0_CRYPTO_R0_MIC_QOS_CONTROL__MIC_QOS_CONTROL___POR 0x00AA +#define WMAC0_CRYPTO_R0_MIC_QOS_CONTROL__MIC_QOS_CONTROL___M 0x0000FFFF +#define WMAC0_CRYPTO_R0_MIC_QOS_CONTROL__MIC_QOS_CONTROL___S 0 +#define WMAC0_CRYPTO_R0_MIC_QOS_CONTROL___M 0x0000FFFF +#define WMAC0_CRYPTO_R0_MIC_QOS_CONTROL___S 0 + +#define WMAC0_CRYPTO_R0_MIC_QOS_SELECT (0x00AA700C) +#define WMAC0_CRYPTO_R0_MIC_QOS_SELECT___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R0_MIC_QOS_SELECT___POR 0x00003210 +#define WMAC0_CRYPTO_R0_MIC_QOS_SELECT__MIC_QOS_SELECT___POR 0x00003210 +#define WMAC0_CRYPTO_R0_MIC_QOS_SELECT__MIC_QOS_SELECT___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R0_MIC_QOS_SELECT__MIC_QOS_SELECT___S 0 +#define WMAC0_CRYPTO_R0_MIC_QOS_SELECT___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R0_MIC_QOS_SELECT___S 0 + +#define WMAC0_CRYPTO_R0_ALT_AES_MUTE_MASK (0x00AA7010) +#define WMAC0_CRYPTO_R0_ALT_AES_MUTE_MASK___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R0_ALT_AES_MUTE_MASK___POR 0x0000008F +#define WMAC0_CRYPTO_R0_ALT_AES_MUTE_MASK__QOS___POR 0x008F +#define WMAC0_CRYPTO_R0_ALT_AES_MUTE_MASK__QOS___M 0x0000FFFF +#define WMAC0_CRYPTO_R0_ALT_AES_MUTE_MASK__QOS___S 0 +#define WMAC0_CRYPTO_R0_ALT_AES_MUTE_MASK___M 0x0000FFFF +#define WMAC0_CRYPTO_R0_ALT_AES_MUTE_MASK___S 0 + +#define WMAC0_CRYPTO_R0_MISC_CONTROL (0x00AA7014) +#define WMAC0_CRYPTO_R0_MISC_CONTROL___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R0_MISC_CONTROL___POR 0x1E100009 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__RX_USER_MPDU_END_CRYPTO_STATUS_EN___POR 0x1 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__WAPI_INTERLEAVE_EN___POR 0x1 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__NO_CIPHER_INTERLEAVE_EN___POR 0x1 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__AES_INTERLEAVE_EN___POR 0x1 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__RX_BACKPRESSURE_EN___POR 0x0 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__MGMT_QOS___POR 0x10 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__BC_MC_WAPI_MODE2___POR 0x0 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__BC_MC_WAPI_MODE2_EN___POR 0x0 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__NO_CRYPTO_FOR_NON_DATA_PKT___POR 0x0 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__CRPT_MIC_ENABLE___POR 0x0 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__ZEROLEN_CRYPTO_ENABLE___POR 0x1 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__WAPI_ORDER_MASK___POR 0x0 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__SM_STATE_CONTROL___POR 0x0 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__MGMT_CRYPTO_ENABLE___POR 0x1 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__RX_USER_MPDU_END_CRYPTO_STATUS_EN___M 0x10000000 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__RX_USER_MPDU_END_CRYPTO_STATUS_EN___S 28 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__WAPI_INTERLEAVE_EN___M 0x08000000 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__WAPI_INTERLEAVE_EN___S 27 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__NO_CIPHER_INTERLEAVE_EN___M 0x04000000 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__NO_CIPHER_INTERLEAVE_EN___S 26 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__AES_INTERLEAVE_EN___M 0x02000000 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__AES_INTERLEAVE_EN___S 25 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__RX_BACKPRESSURE_EN___M 0x01000000 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__RX_BACKPRESSURE_EN___S 24 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__MGMT_QOS___M 0x00FF0000 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__MGMT_QOS___S 16 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__BC_MC_WAPI_MODE2___M 0x00000080 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__BC_MC_WAPI_MODE2___S 7 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__BC_MC_WAPI_MODE2_EN___M 0x00000040 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__BC_MC_WAPI_MODE2_EN___S 6 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__NO_CRYPTO_FOR_NON_DATA_PKT___M 0x00000020 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__NO_CRYPTO_FOR_NON_DATA_PKT___S 5 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__CRPT_MIC_ENABLE___M 0x00000010 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__CRPT_MIC_ENABLE___S 4 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__ZEROLEN_CRYPTO_ENABLE___M 0x00000008 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__ZEROLEN_CRYPTO_ENABLE___S 3 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__WAPI_ORDER_MASK___M 0x00000004 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__WAPI_ORDER_MASK___S 2 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__SM_STATE_CONTROL___M 0x00000002 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__SM_STATE_CONTROL___S 1 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__MGMT_CRYPTO_ENABLE___M 0x00000001 +#define WMAC0_CRYPTO_R0_MISC_CONTROL__MGMT_CRYPTO_ENABLE___S 0 +#define WMAC0_CRYPTO_R0_MISC_CONTROL___M 0x1FFF00FF +#define WMAC0_CRYPTO_R0_MISC_CONTROL___S 0 + +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE (0x00AA7018) +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE___POR 0x00000080 +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__WDOG_CLK_GATE_DISABLE___POR 0x0 +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__RX_TLV_CLK_GATE_DISABLE___POR 0x0 +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__CLK_GATE_EXTEND___POR 0x1 +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__DEBUG_CLK_GATE_DISABLE___POR 0x0 +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__RC4_CLK_GATE_DISABLE___POR 0x0 +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__WAPI_CLK_GATE_DISABLE___POR 0x0 +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__WEP_CLK_GATE_DISABLE___POR 0x0 +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__TX_TLV_CLK_GATE_DISABLE___POR 0x0 +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__CNTRL_CLK_GATE_DISABLE___POR 0x0 +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__AES_CLK_GATE_DISABLE___POR 0x0 +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__WDOG_CLK_GATE_DISABLE___M 0x00000200 +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__WDOG_CLK_GATE_DISABLE___S 9 +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__RX_TLV_CLK_GATE_DISABLE___M 0x00000100 +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__RX_TLV_CLK_GATE_DISABLE___S 8 +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__CLK_GATE_EXTEND___M 0x00000080 +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__CLK_GATE_EXTEND___S 7 +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__DEBUG_CLK_GATE_DISABLE___M 0x00000040 +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__DEBUG_CLK_GATE_DISABLE___S 6 +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__RC4_CLK_GATE_DISABLE___M 0x00000020 +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__RC4_CLK_GATE_DISABLE___S 5 +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__WAPI_CLK_GATE_DISABLE___M 0x00000010 +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__WAPI_CLK_GATE_DISABLE___S 4 +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__WEP_CLK_GATE_DISABLE___M 0x00000008 +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__WEP_CLK_GATE_DISABLE___S 3 +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__TX_TLV_CLK_GATE_DISABLE___M 0x00000004 +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__TX_TLV_CLK_GATE_DISABLE___S 2 +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__CNTRL_CLK_GATE_DISABLE___M 0x00000002 +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__CNTRL_CLK_GATE_DISABLE___S 1 +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__AES_CLK_GATE_DISABLE___M 0x00000001 +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE__AES_CLK_GATE_DISABLE___S 0 +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE___M 0x000003FF +#define WMAC0_CRYPTO_R0_CLOCK_GATE_DISABLE___S 0 + +#define WMAC0_CRYPTO_R0_BEELINER_MODE_CONFIG (0x00AA701C) +#define WMAC0_CRYPTO_R0_BEELINER_MODE_CONFIG___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R0_BEELINER_MODE_CONFIG___POR 0x00000000 +#define WMAC0_CRYPTO_R0_BEELINER_MODE_CONFIG__ENABLE_TX_PUSHBACK_MODE___POR 0x0 +#define WMAC0_CRYPTO_R0_BEELINER_MODE_CONFIG__DISABLE_HOLD_TX_TLV_IN_RX___POR 0x0 +#define WMAC0_CRYPTO_R0_BEELINER_MODE_CONFIG__RX_ABORT_INT_EN___POR 0x0 +#define WMAC0_CRYPTO_R0_BEELINER_MODE_CONFIG__TX_ABORT_INT_EN___POR 0x0 +#define WMAC0_CRYPTO_R0_BEELINER_MODE_CONFIG__ENABLE_TX_PUSHBACK_MODE___M 0x00000008 +#define WMAC0_CRYPTO_R0_BEELINER_MODE_CONFIG__ENABLE_TX_PUSHBACK_MODE___S 3 +#define WMAC0_CRYPTO_R0_BEELINER_MODE_CONFIG__DISABLE_HOLD_TX_TLV_IN_RX___M 0x00000004 +#define WMAC0_CRYPTO_R0_BEELINER_MODE_CONFIG__DISABLE_HOLD_TX_TLV_IN_RX___S 2 +#define WMAC0_CRYPTO_R0_BEELINER_MODE_CONFIG__RX_ABORT_INT_EN___M 0x00000002 +#define WMAC0_CRYPTO_R0_BEELINER_MODE_CONFIG__RX_ABORT_INT_EN___S 1 +#define WMAC0_CRYPTO_R0_BEELINER_MODE_CONFIG__TX_ABORT_INT_EN___M 0x00000001 +#define WMAC0_CRYPTO_R0_BEELINER_MODE_CONFIG__TX_ABORT_INT_EN___S 0 +#define WMAC0_CRYPTO_R0_BEELINER_MODE_CONFIG___M 0x0000000F +#define WMAC0_CRYPTO_R0_BEELINER_MODE_CONFIG___S 0 + +#define WMAC0_CRYPTO_R0_FIPS_CONTROL (0x00AA7020) +#define WMAC0_CRYPTO_R0_FIPS_CONTROL___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R0_FIPS_CONTROL___POR 0x00000000 +#define WMAC0_CRYPTO_R0_FIPS_CONTROL__AES_ENG_1_2___POR 0x0 +#define WMAC0_CRYPTO_R0_FIPS_CONTROL__AES_KEY_128_256___POR 0x0 +#define WMAC0_CRYPTO_R0_FIPS_CONTROL__FIPS_TEST_ENABLE___POR 0x0 +#define WMAC0_CRYPTO_R0_FIPS_CONTROL__AES_ENG_1_2___M 0x00000004 +#define WMAC0_CRYPTO_R0_FIPS_CONTROL__AES_ENG_1_2___S 2 +#define WMAC0_CRYPTO_R0_FIPS_CONTROL__AES_KEY_128_256___M 0x00000002 +#define WMAC0_CRYPTO_R0_FIPS_CONTROL__AES_KEY_128_256___S 1 +#define WMAC0_CRYPTO_R0_FIPS_CONTROL__FIPS_TEST_ENABLE___M 0x00000001 +#define WMAC0_CRYPTO_R0_FIPS_CONTROL__FIPS_TEST_ENABLE___S 0 +#define WMAC0_CRYPTO_R0_FIPS_CONTROL___M 0x00000007 +#define WMAC0_CRYPTO_R0_FIPS_CONTROL___S 0 + +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_n(n) (0x00AA7024+0x4*(n)) +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_n_nMIN 0 +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_n_nMAX 7 +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_n_ELEM 8 +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_n___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_n___POR 0x00000000 +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_n__AES_KEY___POR 0x00000000 +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_n__AES_KEY___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_n__AES_KEY___S 0 +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_n___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_n___S 0 +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_0 (0x00AA7024) +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_0___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_0__AES_KEY___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_0__AES_KEY___S 0 +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_1 (0x00AA7028) +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_1___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_1__AES_KEY___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_1__AES_KEY___S 0 +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_2 (0x00AA702C) +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_2___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_2__AES_KEY___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_2__AES_KEY___S 0 +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_3 (0x00AA7030) +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_3___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_3__AES_KEY___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_3__AES_KEY___S 0 +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_4 (0x00AA7034) +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_4___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_4__AES_KEY___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_4__AES_KEY___S 0 +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_5 (0x00AA7038) +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_5___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_5__AES_KEY___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_5__AES_KEY___S 0 +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_6 (0x00AA703C) +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_6___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_6__AES_KEY___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_6__AES_KEY___S 0 +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_7 (0x00AA7040) +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_7___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_7__AES_KEY___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R0_FIPS_AES_KEY_7__AES_KEY___S 0 + +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_n(n) (0x00AA7044+0x4*(n)) +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_n_nMIN 0 +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_n_nMAX 3 +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_n_ELEM 4 +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_n___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_n___POR 0x00000000 +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_n__AES_DATA_IN___POR 0x00000000 +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_n__AES_DATA_IN___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_n__AES_DATA_IN___S 0 +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_n___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_n___S 0 +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_0 (0x00AA7044) +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_0___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_0__AES_DATA_IN___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_0__AES_DATA_IN___S 0 +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_1 (0x00AA7048) +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_1___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_1__AES_DATA_IN___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_1__AES_DATA_IN___S 0 +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_2 (0x00AA704C) +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_2___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_2__AES_DATA_IN___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_2__AES_DATA_IN___S 0 +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_3 (0x00AA7050) +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_3___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_3__AES_DATA_IN___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_IN_3__AES_DATA_IN___S 0 + +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_n(n) (0x00AA7054+0x4*(n)) +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_n_nMIN 0 +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_n_nMAX 3 +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_n_ELEM 4 +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_n___RWC QCSR_REG_RO +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_n___POR 0x00000000 +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_n__AES_DATA_OUT___POR 0x00000000 +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_n__AES_DATA_OUT___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_n__AES_DATA_OUT___S 0 +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_n___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_n___S 0 +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_0 (0x00AA7054) +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_0___RWC QCSR_REG_RO +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_0__AES_DATA_OUT___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_0__AES_DATA_OUT___S 0 +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_1 (0x00AA7058) +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_1___RWC QCSR_REG_RO +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_1__AES_DATA_OUT___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_1__AES_DATA_OUT___S 0 +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_2 (0x00AA705C) +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_2___RWC QCSR_REG_RO +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_2__AES_DATA_OUT___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_2__AES_DATA_OUT___S 0 +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_3 (0x00AA7060) +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_3___RWC QCSR_REG_RO +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_3__AES_DATA_OUT___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R0_FIPS_AES_DATA_OUT_3__AES_DATA_OUT___S 0 + +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_0_AH (0x00AA7064) +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_0_AH___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_0_AH___POR 0x000013E3 +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_0_AH__FC___POR 0x13E3 +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_0_AH__FC___M 0x0000FFFF +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_0_AH__FC___S 0 +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_0_AH___M 0x0000FFFF +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_0_AH___S 0 + +#define WMAC0_CRYPTO_R0_WAPI_GCM_SM4_IV (0x00AA7068) +#define WMAC0_CRYPTO_R0_WAPI_GCM_SM4_IV___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R0_WAPI_GCM_SM4_IV___POR 0x00000000 +#define WMAC0_CRYPTO_R0_WAPI_GCM_SM4_IV__IV127_TO_96___POR 0x00000000 +#define WMAC0_CRYPTO_R0_WAPI_GCM_SM4_IV__IV127_TO_96___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R0_WAPI_GCM_SM4_IV__IV127_TO_96___S 0 +#define WMAC0_CRYPTO_R0_WAPI_GCM_SM4_IV___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R0_WAPI_GCM_SM4_IV___S 0 + +#define WMAC0_CRYPTO_R0_WAPI_WPI_SMS4_MUTE_MASK (0x00AA706C) +#define WMAC0_CRYPTO_R0_WAPI_WPI_SMS4_MUTE_MASK___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R0_WAPI_WPI_SMS4_MUTE_MASK___POR 0x000FC78F +#define WMAC0_CRYPTO_R0_WAPI_WPI_SMS4_MUTE_MASK__SC___POR 0x000F +#define WMAC0_CRYPTO_R0_WAPI_WPI_SMS4_MUTE_MASK__FC___POR 0xC78F +#define WMAC0_CRYPTO_R0_WAPI_WPI_SMS4_MUTE_MASK__SC___M 0xFFFF0000 +#define WMAC0_CRYPTO_R0_WAPI_WPI_SMS4_MUTE_MASK__SC___S 16 +#define WMAC0_CRYPTO_R0_WAPI_WPI_SMS4_MUTE_MASK__FC___M 0x0000FFFF +#define WMAC0_CRYPTO_R0_WAPI_WPI_SMS4_MUTE_MASK__FC___S 0 +#define WMAC0_CRYPTO_R0_WAPI_WPI_SMS4_MUTE_MASK___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R0_WAPI_WPI_SMS4_MUTE_MASK___S 0 + +#define WMAC0_CRYPTO_R0_WAPI_GCM_SM4_MUTE_MASK (0x00AA7070) +#define WMAC0_CRYPTO_R0_WAPI_GCM_SM4_MUTE_MASK___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R0_WAPI_GCM_SM4_MUTE_MASK___POR 0x000FC78F +#define WMAC0_CRYPTO_R0_WAPI_GCM_SM4_MUTE_MASK__SC___POR 0x000F +#define WMAC0_CRYPTO_R0_WAPI_GCM_SM4_MUTE_MASK__FC___POR 0xC78F +#define WMAC0_CRYPTO_R0_WAPI_GCM_SM4_MUTE_MASK__SC___M 0xFFFF0000 +#define WMAC0_CRYPTO_R0_WAPI_GCM_SM4_MUTE_MASK__SC___S 16 +#define WMAC0_CRYPTO_R0_WAPI_GCM_SM4_MUTE_MASK__FC___M 0x0000FFFF +#define WMAC0_CRYPTO_R0_WAPI_GCM_SM4_MUTE_MASK__FC___S 0 +#define WMAC0_CRYPTO_R0_WAPI_GCM_SM4_MUTE_MASK___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R0_WAPI_GCM_SM4_MUTE_MASK___S 0 + +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL (0x00AA7074) +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL___POR 0x00010E0E +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_A4_INSERT_ZERO___POR 0x1 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_LEN_POS___POR 0x0 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_LEN_REV___POR 0x0 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_CNTR_IV_POS___POR 0x0 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_CNTR_REV___POR 0x0 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_DATA_REV___POR 0x1 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_KEY_REV___POR 0x1 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_AAD_REV___POR 0x1 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_IV_REV___POR 0x0 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__WPI_SMS4_DATA_REV___POR 0x1 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__WPI_SMS4_KEY_REV___POR 0x1 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__WPI_SMS4_AAD_REV___POR 0x1 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__WPI_SMS4_IV_REV___POR 0x0 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_A4_INSERT_ZERO___M 0x00010000 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_A4_INSERT_ZERO___S 16 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_LEN_POS___M 0x00008000 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_LEN_POS___S 15 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_LEN_REV___M 0x00004000 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_LEN_REV___S 14 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_CNTR_IV_POS___M 0x00002000 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_CNTR_IV_POS___S 13 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_CNTR_REV___M 0x00001000 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_CNTR_REV___S 12 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_DATA_REV___M 0x00000800 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_DATA_REV___S 11 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_KEY_REV___M 0x00000400 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_KEY_REV___S 10 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_AAD_REV___M 0x00000200 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_AAD_REV___S 9 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_IV_REV___M 0x00000100 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__GCM_SM4_IV_REV___S 8 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__WPI_SMS4_DATA_REV___M 0x00000008 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__WPI_SMS4_DATA_REV___S 3 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__WPI_SMS4_KEY_REV___M 0x00000004 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__WPI_SMS4_KEY_REV___S 2 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__WPI_SMS4_AAD_REV___M 0x00000002 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__WPI_SMS4_AAD_REV___S 1 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__WPI_SMS4_IV_REV___M 0x00000001 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL__WPI_SMS4_IV_REV___S 0 +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL___M 0x0001FF0F +#define WMAC0_CRYPTO_R0_WAPI_MISC_CTRL___S 0 + +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_1_AH (0x00AA7078) +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_1_AH___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_1_AH___POR 0x1FFF1FFF +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_1_AH__A2___POR 0x1FFF +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_1_AH__A1___POR 0x1FFF +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_1_AH__A2___M 0xFFFF0000 +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_1_AH__A2___S 16 +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_1_AH__A1___M 0x0000FFFF +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_1_AH__A1___S 0 +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_1_AH___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R0_AES_MUTE_MASK_1_AH___S 0 + +#define WMAC0_CRYPTO_R0_USER_SWITCH_CNT (0x00AA707C) +#define WMAC0_CRYPTO_R0_USER_SWITCH_CNT___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R0_USER_SWITCH_CNT___POR 0x00000101 +#define WMAC0_CRYPTO_R0_USER_SWITCH_CNT__RX_USER_SWITCH_CNT___POR 0x01 +#define WMAC0_CRYPTO_R0_USER_SWITCH_CNT__TX_USER_SWITCH_CNT___POR 0x01 +#define WMAC0_CRYPTO_R0_USER_SWITCH_CNT__RX_USER_SWITCH_CNT___M 0x0000FF00 +#define WMAC0_CRYPTO_R0_USER_SWITCH_CNT__RX_USER_SWITCH_CNT___S 8 +#define WMAC0_CRYPTO_R0_USER_SWITCH_CNT__TX_USER_SWITCH_CNT___M 0x000000FF +#define WMAC0_CRYPTO_R0_USER_SWITCH_CNT__TX_USER_SWITCH_CNT___S 0 +#define WMAC0_CRYPTO_R0_USER_SWITCH_CNT___M 0x0000FFFF +#define WMAC0_CRYPTO_R0_USER_SWITCH_CNT___S 0 + +#define WMAC0_CRYPTO_R0_ARBITER_CTRL (0x00AA7080) +#define WMAC0_CRYPTO_R0_ARBITER_CTRL___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R0_ARBITER_CTRL___POR 0x00010000 +#define WMAC0_CRYPTO_R0_ARBITER_CTRL__ARBITER_ENABLE___POR 0x1 +#define WMAC0_CRYPTO_R0_ARBITER_CTRL__WAIT_COUNT_AFTER_RX_TLV___POR 0x00 +#define WMAC0_CRYPTO_R0_ARBITER_CTRL__WAIT_COUNT_AFTER_TX_TLV___POR 0x00 +#define WMAC0_CRYPTO_R0_ARBITER_CTRL__ARBITER_ENABLE___M 0x00010000 +#define WMAC0_CRYPTO_R0_ARBITER_CTRL__ARBITER_ENABLE___S 16 +#define WMAC0_CRYPTO_R0_ARBITER_CTRL__WAIT_COUNT_AFTER_RX_TLV___M 0x0000FF00 +#define WMAC0_CRYPTO_R0_ARBITER_CTRL__WAIT_COUNT_AFTER_RX_TLV___S 8 +#define WMAC0_CRYPTO_R0_ARBITER_CTRL__WAIT_COUNT_AFTER_TX_TLV___M 0x000000FF +#define WMAC0_CRYPTO_R0_ARBITER_CTRL__WAIT_COUNT_AFTER_TX_TLV___S 0 +#define WMAC0_CRYPTO_R0_ARBITER_CTRL___M 0x0001FFFF +#define WMAC0_CRYPTO_R0_ARBITER_CTRL___S 0 + +#define WMAC0_CRYPTO_R0_SPARE_CTRL (0x00AA7084) +#define WMAC0_CRYPTO_R0_SPARE_CTRL___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R0_SPARE_CTRL___POR 0x0000FF01 +#define WMAC0_CRYPTO_R0_SPARE_CTRL__SPARE_BITS___POR 0x7F80 +#define WMAC0_CRYPTO_R0_SPARE_CTRL__WAPI_SHORT_PKT_MIC_FAIL_FIX___POR 0x1 +#define WMAC0_CRYPTO_R0_SPARE_CTRL__SPARE_BITS___M 0x0000FFFE +#define WMAC0_CRYPTO_R0_SPARE_CTRL__SPARE_BITS___S 1 +#define WMAC0_CRYPTO_R0_SPARE_CTRL__WAPI_SHORT_PKT_MIC_FAIL_FIX___M 0x00000001 +#define WMAC0_CRYPTO_R0_SPARE_CTRL__WAPI_SHORT_PKT_MIC_FAIL_FIX___S 0 +#define WMAC0_CRYPTO_R0_SPARE_CTRL___M 0x0000FFFF +#define WMAC0_CRYPTO_R0_SPARE_CTRL___S 0 + +#define WMAC0_CRYPTO_R0_FLUSH_RESET_CTRL (0x00AA7088) +#define WMAC0_CRYPTO_R0_FLUSH_RESET_CTRL___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R0_FLUSH_RESET_CTRL___POR 0x00000007 +#define WMAC0_CRYPTO_R0_FLUSH_RESET_CTRL__SPARE_BITS___POR 0x0000 +#define WMAC0_CRYPTO_R0_FLUSH_RESET_CTRL__WAIT_CYCLES___POR 0x7 +#define WMAC0_CRYPTO_R0_FLUSH_RESET_CTRL__SPARE_BITS___M 0x0000FFF8 +#define WMAC0_CRYPTO_R0_FLUSH_RESET_CTRL__SPARE_BITS___S 3 +#define WMAC0_CRYPTO_R0_FLUSH_RESET_CTRL__WAIT_CYCLES___M 0x00000007 +#define WMAC0_CRYPTO_R0_FLUSH_RESET_CTRL__WAIT_CYCLES___S 0 +#define WMAC0_CRYPTO_R0_FLUSH_RESET_CTRL___M 0x0000FFFF +#define WMAC0_CRYPTO_R0_FLUSH_RESET_CTRL___S 0 + +#define WMAC0_CRYPTO_R1_SM_STATES_IX_0 (0x00AA8000) +#define WMAC0_CRYPTO_R1_SM_STATES_IX_0___RWC QCSR_REG_RO +#define WMAC0_CRYPTO_R1_SM_STATES_IX_0___POR 0x00000000 +#define WMAC0_CRYPTO_R1_SM_STATES_IX_0__CCM_WBUF_EMPTY___POR 0x0 +#define WMAC0_CRYPTO_R1_SM_STATES_IX_0__CCM_RBUF_EMPTY___POR 0x0 +#define WMAC0_CRYPTO_R1_SM_STATES_IX_0__CCM_RD_STATE___POR 0x0 +#define WMAC0_CRYPTO_R1_SM_STATES_IX_0__CCM_CTRL_STATE___POR 0x00 +#define WMAC0_CRYPTO_R1_SM_STATES_IX_0__WEP_CTRL_STATE___POR 0x00 +#define WMAC0_CRYPTO_R1_SM_STATES_IX_0__RX_CTRL_STATE___POR 0x0 +#define WMAC0_CRYPTO_R1_SM_STATES_IX_0__TX_CTRL_STATE___POR 0x0 +#define WMAC0_CRYPTO_R1_SM_STATES_IX_0__CCM_WBUF_EMPTY___M 0x01000000 +#define WMAC0_CRYPTO_R1_SM_STATES_IX_0__CCM_WBUF_EMPTY___S 24 +#define WMAC0_CRYPTO_R1_SM_STATES_IX_0__CCM_RBUF_EMPTY___M 0x00800000 +#define WMAC0_CRYPTO_R1_SM_STATES_IX_0__CCM_RBUF_EMPTY___S 23 +#define WMAC0_CRYPTO_R1_SM_STATES_IX_0__CCM_RD_STATE___M 0x00600000 +#define WMAC0_CRYPTO_R1_SM_STATES_IX_0__CCM_RD_STATE___S 21 +#define WMAC0_CRYPTO_R1_SM_STATES_IX_0__CCM_CTRL_STATE___M 0x000F8000 +#define WMAC0_CRYPTO_R1_SM_STATES_IX_0__CCM_CTRL_STATE___S 15 +#define WMAC0_CRYPTO_R1_SM_STATES_IX_0__WEP_CTRL_STATE___M 0x00001F00 +#define WMAC0_CRYPTO_R1_SM_STATES_IX_0__WEP_CTRL_STATE___S 8 +#define WMAC0_CRYPTO_R1_SM_STATES_IX_0__RX_CTRL_STATE___M 0x000000F0 +#define WMAC0_CRYPTO_R1_SM_STATES_IX_0__RX_CTRL_STATE___S 4 +#define WMAC0_CRYPTO_R1_SM_STATES_IX_0__TX_CTRL_STATE___M 0x0000000F +#define WMAC0_CRYPTO_R1_SM_STATES_IX_0__TX_CTRL_STATE___S 0 +#define WMAC0_CRYPTO_R1_SM_STATES_IX_0___M 0x01EF9FFF +#define WMAC0_CRYPTO_R1_SM_STATES_IX_0___S 0 + +#define WMAC0_CRYPTO_R1_TESTBUS_CTRL (0x00AA8004) +#define WMAC0_CRYPTO_R1_TESTBUS_CTRL___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R1_TESTBUS_CTRL___POR 0x00000000 +#define WMAC0_CRYPTO_R1_TESTBUS_CTRL__TESTBUS_SELECT___POR 0x00 +#define WMAC0_CRYPTO_R1_TESTBUS_CTRL__TESTBUS_SELECT___M 0x000000FF +#define WMAC0_CRYPTO_R1_TESTBUS_CTRL__TESTBUS_SELECT___S 0 +#define WMAC0_CRYPTO_R1_TESTBUS_CTRL___M 0x000000FF +#define WMAC0_CRYPTO_R1_TESTBUS_CTRL___S 0 + +#define WMAC0_CRYPTO_R1_TESTBUS_LOWER (0x00AA8008) +#define WMAC0_CRYPTO_R1_TESTBUS_LOWER___RWC QCSR_REG_RO +#define WMAC0_CRYPTO_R1_TESTBUS_LOWER___POR 0x00000000 +#define WMAC0_CRYPTO_R1_TESTBUS_LOWER__VALUE___POR 0x00000000 +#define WMAC0_CRYPTO_R1_TESTBUS_LOWER__VALUE___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_TESTBUS_LOWER__VALUE___S 0 +#define WMAC0_CRYPTO_R1_TESTBUS_LOWER___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_TESTBUS_LOWER___S 0 + +#define WMAC0_CRYPTO_R1_TESTBUS_UPPER (0x00AA800C) +#define WMAC0_CRYPTO_R1_TESTBUS_UPPER___RWC QCSR_REG_RO +#define WMAC0_CRYPTO_R1_TESTBUS_UPPER___POR 0x00000000 +#define WMAC0_CRYPTO_R1_TESTBUS_UPPER__VALUE___POR 0x00 +#define WMAC0_CRYPTO_R1_TESTBUS_UPPER__VALUE___M 0x000000FF +#define WMAC0_CRYPTO_R1_TESTBUS_UPPER__VALUE___S 0 +#define WMAC0_CRYPTO_R1_TESTBUS_UPPER___M 0x000000FF +#define WMAC0_CRYPTO_R1_TESTBUS_UPPER___S 0 + +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS (0x00AA8010) +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS___RWC QCSR_REG_RO +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS___POR 0x00000000 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_OVER_CAPACITY_TX_USER_INT_P___POR 0x0 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_RX_KEY_ID_RECV_NOT_VALID_KEY_INT_P___POR 0x0 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_RX_KEY_ID_RECV_NOT_DEFAULT_INT_P___POR 0x0 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_RX_NO_MU_KEY_TYPE_INT_P___POR 0x0 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_TX_NO_MU_KEY_TYPE_INT_P___POR 0x0 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_RX_IN_TX_DECRYPT_BYP_INT_P___POR 0x0 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_RX_TLV_READY_TIMEOUT_ERR_INT_P___POR 0x0 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_11AH_UNSUP_DEC_TYPE_ERR_INT_P___POR 0x0 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_11AH_UNSUP_ENC_TYPE_ERR_INT_P___POR 0x0 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MIN_LENGTH_ERR_INT_P___POR 0x0 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_WATCHDOG_TIMEOUT_INT_P___POR 0x0 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_TXTLV_OUT_OF_SEQ_INT_P___POR 0x0 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_RXTLV_OUT_OF_SEQ_INT_P___POR 0x0 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_DECRYPT_ERR_INT_P___POR 0x0 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_TX_ABORT_INT_P___POR 0x0 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_RX_ABORT_INT_P___POR 0x0 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_TX_FLUSH_REQ_P___POR 0x0 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_OVER_CAPACITY_TX_USER_INT_P___M 0x00010000 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_OVER_CAPACITY_TX_USER_INT_P___S 16 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_RX_KEY_ID_RECV_NOT_VALID_KEY_INT_P___M 0x00008000 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_RX_KEY_ID_RECV_NOT_VALID_KEY_INT_P___S 15 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_RX_KEY_ID_RECV_NOT_DEFAULT_INT_P___M 0x00004000 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_RX_KEY_ID_RECV_NOT_DEFAULT_INT_P___S 14 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_RX_NO_MU_KEY_TYPE_INT_P___M 0x00002000 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_RX_NO_MU_KEY_TYPE_INT_P___S 13 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_TX_NO_MU_KEY_TYPE_INT_P___M 0x00001000 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_TX_NO_MU_KEY_TYPE_INT_P___S 12 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_RX_IN_TX_DECRYPT_BYP_INT_P___M 0x00000800 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_RX_IN_TX_DECRYPT_BYP_INT_P___S 11 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_RX_TLV_READY_TIMEOUT_ERR_INT_P___M 0x00000400 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_RX_TLV_READY_TIMEOUT_ERR_INT_P___S 10 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_11AH_UNSUP_DEC_TYPE_ERR_INT_P___M 0x00000200 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_11AH_UNSUP_DEC_TYPE_ERR_INT_P___S 9 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_11AH_UNSUP_ENC_TYPE_ERR_INT_P___M 0x00000100 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_11AH_UNSUP_ENC_TYPE_ERR_INT_P___S 8 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MIN_LENGTH_ERR_INT_P___M 0x00000080 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MIN_LENGTH_ERR_INT_P___S 7 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_WATCHDOG_TIMEOUT_INT_P___M 0x00000040 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_WATCHDOG_TIMEOUT_INT_P___S 6 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_TXTLV_OUT_OF_SEQ_INT_P___M 0x00000020 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_TXTLV_OUT_OF_SEQ_INT_P___S 5 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_RXTLV_OUT_OF_SEQ_INT_P___M 0x00000010 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_RXTLV_OUT_OF_SEQ_INT_P___S 4 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_DECRYPT_ERR_INT_P___M 0x00000008 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_DECRYPT_ERR_INT_P___S 3 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_TX_ABORT_INT_P___M 0x00000004 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_TX_ABORT_INT_P___S 2 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_RX_ABORT_INT_P___M 0x00000002 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_RX_ABORT_INT_P___S 1 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_TX_FLUSH_REQ_P___M 0x00000001 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS__CRYPTO_MCMN_TX_FLUSH_REQ_P___S 0 +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS___M 0x0001FFFF +#define WMAC0_CRYPTO_R1_DEBUG_INTERRUPT_STATUS___S 0 + +#define WMAC0_CRYPTO_R1_TX_WATCHDOG_TIMER_VALUE (0x00AA8014) +#define WMAC0_CRYPTO_R1_TX_WATCHDOG_TIMER_VALUE___RWC QCSR_REG_RO +#define WMAC0_CRYPTO_R1_TX_WATCHDOG_TIMER_VALUE___POR 0x00000000 +#define WMAC0_CRYPTO_R1_TX_WATCHDOG_TIMER_VALUE__TX_WATCHDOG_VALUE___POR 0x00000000 +#define WMAC0_CRYPTO_R1_TX_WATCHDOG_TIMER_VALUE__TX_WATCHDOG_VALUE___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_TX_WATCHDOG_TIMER_VALUE__TX_WATCHDOG_VALUE___S 0 +#define WMAC0_CRYPTO_R1_TX_WATCHDOG_TIMER_VALUE___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_TX_WATCHDOG_TIMER_VALUE___S 0 + +#define WMAC0_CRYPTO_R1_TX_WATCHDOG_TIMER_THRESHOLD (0x00AA8018) +#define WMAC0_CRYPTO_R1_TX_WATCHDOG_TIMER_THRESHOLD___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R1_TX_WATCHDOG_TIMER_THRESHOLD___POR 0x00000000 +#define WMAC0_CRYPTO_R1_TX_WATCHDOG_TIMER_THRESHOLD__TX_WATCHDOG_THRESHOLD___POR 0x00000000 +#define WMAC0_CRYPTO_R1_TX_WATCHDOG_TIMER_THRESHOLD__TX_WATCHDOG_THRESHOLD___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_TX_WATCHDOG_TIMER_THRESHOLD__TX_WATCHDOG_THRESHOLD___S 0 +#define WMAC0_CRYPTO_R1_TX_WATCHDOG_TIMER_THRESHOLD___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_TX_WATCHDOG_TIMER_THRESHOLD___S 0 + +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL (0x00AA801C) +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL___POR 0x00000021 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_USER_MPDU_END_CNT_ENABLE___POR 0x0 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_USER_MPDU_END_CNT_ENABLE___POR 0x0 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_PPDU_CNT_ENABLE___POR 0x0 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_FES_CNT_ENABLE___POR 0x0 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_DATA_CNT_ENABLE___POR 0x0 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_SHORT_FRAME_CNT_ENABLE___POR 0x0 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_SHORT_FRAME_CNT_ENABLE___POR 0x0 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_ABORT_CNT_ENABLE___POR 0x0 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_DECR_FRAME_CNT_ENABLE___POR 0x0 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_MPDU_CNT_ENABLE___POR 0x1 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_ABORT_CNT_ENABLE___POR 0x0 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_FLUSH_REQ_CNT_ENABLE___POR 0x0 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_FLUSH_RCV_CNT_ENABLE___POR 0x0 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_ENCR_FRAME_CNT_ENABLE___POR 0x0 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_MPDU_CNT_ENABLE___POR 0x1 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_USER_MPDU_END_CNT_ENABLE___M 0x00004000 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_USER_MPDU_END_CNT_ENABLE___S 14 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_USER_MPDU_END_CNT_ENABLE___M 0x00002000 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_USER_MPDU_END_CNT_ENABLE___S 13 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_PPDU_CNT_ENABLE___M 0x00001000 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_PPDU_CNT_ENABLE___S 12 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_FES_CNT_ENABLE___M 0x00000800 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_FES_CNT_ENABLE___S 11 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_DATA_CNT_ENABLE___M 0x00000400 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_DATA_CNT_ENABLE___S 10 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_SHORT_FRAME_CNT_ENABLE___M 0x00000200 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_SHORT_FRAME_CNT_ENABLE___S 9 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_SHORT_FRAME_CNT_ENABLE___M 0x00000100 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_SHORT_FRAME_CNT_ENABLE___S 8 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_ABORT_CNT_ENABLE___M 0x00000080 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_ABORT_CNT_ENABLE___S 7 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_DECR_FRAME_CNT_ENABLE___M 0x00000040 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_DECR_FRAME_CNT_ENABLE___S 6 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_MPDU_CNT_ENABLE___M 0x00000020 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__RX_MPDU_CNT_ENABLE___S 5 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_ABORT_CNT_ENABLE___M 0x00000010 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_ABORT_CNT_ENABLE___S 4 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_FLUSH_REQ_CNT_ENABLE___M 0x00000008 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_FLUSH_REQ_CNT_ENABLE___S 3 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_FLUSH_RCV_CNT_ENABLE___M 0x00000004 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_FLUSH_RCV_CNT_ENABLE___S 2 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_ENCR_FRAME_CNT_ENABLE___M 0x00000002 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_ENCR_FRAME_CNT_ENABLE___S 1 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_MPDU_CNT_ENABLE___M 0x00000001 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL__TX_MPDU_CNT_ENABLE___S 0 +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL___M 0x00007FFF +#define WMAC0_CRYPTO_R1_DBG_COUNTERS_CONTROL___S 0 + +#define WMAC0_CRYPTO_R1_DBG_TX_MPDU_CNT (0x00AA8020) +#define WMAC0_CRYPTO_R1_DBG_TX_MPDU_CNT___RWC QCSR_REG_RO +#define WMAC0_CRYPTO_R1_DBG_TX_MPDU_CNT___POR 0x00000000 +#define WMAC0_CRYPTO_R1_DBG_TX_MPDU_CNT__TX_MPDU_CNT___POR 0x00000000 +#define WMAC0_CRYPTO_R1_DBG_TX_MPDU_CNT__TX_MPDU_CNT___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_DBG_TX_MPDU_CNT__TX_MPDU_CNT___S 0 +#define WMAC0_CRYPTO_R1_DBG_TX_MPDU_CNT___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_DBG_TX_MPDU_CNT___S 0 + +#define WMAC0_CRYPTO_R1_DBG_TX_ENCR_FRAME_CNT (0x00AA8024) +#define WMAC0_CRYPTO_R1_DBG_TX_ENCR_FRAME_CNT___RWC QCSR_REG_RO +#define WMAC0_CRYPTO_R1_DBG_TX_ENCR_FRAME_CNT___POR 0x00000000 +#define WMAC0_CRYPTO_R1_DBG_TX_ENCR_FRAME_CNT__TX_ENCR_FRAME_CNT___POR 0x00000000 +#define WMAC0_CRYPTO_R1_DBG_TX_ENCR_FRAME_CNT__TX_ENCR_FRAME_CNT___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_DBG_TX_ENCR_FRAME_CNT__TX_ENCR_FRAME_CNT___S 0 +#define WMAC0_CRYPTO_R1_DBG_TX_ENCR_FRAME_CNT___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_DBG_TX_ENCR_FRAME_CNT___S 0 + +#define WMAC0_CRYPTO_R1_DBG_TX_FLUSH_RCV_CNT (0x00AA8028) +#define WMAC0_CRYPTO_R1_DBG_TX_FLUSH_RCV_CNT___RWC QCSR_REG_RO +#define WMAC0_CRYPTO_R1_DBG_TX_FLUSH_RCV_CNT___POR 0x00000000 +#define WMAC0_CRYPTO_R1_DBG_TX_FLUSH_RCV_CNT__TX_FLUSH_RCV_CNT___POR 0x0000 +#define WMAC0_CRYPTO_R1_DBG_TX_FLUSH_RCV_CNT__TX_FLUSH_RCV_CNT___M 0x0000FFFF +#define WMAC0_CRYPTO_R1_DBG_TX_FLUSH_RCV_CNT__TX_FLUSH_RCV_CNT___S 0 +#define WMAC0_CRYPTO_R1_DBG_TX_FLUSH_RCV_CNT___M 0x0000FFFF +#define WMAC0_CRYPTO_R1_DBG_TX_FLUSH_RCV_CNT___S 0 + +#define WMAC0_CRYPTO_R1_DBG_TX_FLUSH_REQ_CNT (0x00AA802C) +#define WMAC0_CRYPTO_R1_DBG_TX_FLUSH_REQ_CNT___RWC QCSR_REG_RO +#define WMAC0_CRYPTO_R1_DBG_TX_FLUSH_REQ_CNT___POR 0x00000000 +#define WMAC0_CRYPTO_R1_DBG_TX_FLUSH_REQ_CNT__TX_FLUSH_REQ_CNT___POR 0x0000 +#define WMAC0_CRYPTO_R1_DBG_TX_FLUSH_REQ_CNT__TX_FLUSH_REQ_CNT___M 0x0000FFFF +#define WMAC0_CRYPTO_R1_DBG_TX_FLUSH_REQ_CNT__TX_FLUSH_REQ_CNT___S 0 +#define WMAC0_CRYPTO_R1_DBG_TX_FLUSH_REQ_CNT___M 0x0000FFFF +#define WMAC0_CRYPTO_R1_DBG_TX_FLUSH_REQ_CNT___S 0 + +#define WMAC0_CRYPTO_R1_DBG_TX_ABORT_CNT (0x00AA8030) +#define WMAC0_CRYPTO_R1_DBG_TX_ABORT_CNT___RWC QCSR_REG_RO +#define WMAC0_CRYPTO_R1_DBG_TX_ABORT_CNT___POR 0x00000000 +#define WMAC0_CRYPTO_R1_DBG_TX_ABORT_CNT__TX_ABORT_CNT___POR 0x0000 +#define WMAC0_CRYPTO_R1_DBG_TX_ABORT_CNT__TX_ABORT_CNT___M 0x0000FFFF +#define WMAC0_CRYPTO_R1_DBG_TX_ABORT_CNT__TX_ABORT_CNT___S 0 +#define WMAC0_CRYPTO_R1_DBG_TX_ABORT_CNT___M 0x0000FFFF +#define WMAC0_CRYPTO_R1_DBG_TX_ABORT_CNT___S 0 + +#define WMAC0_CRYPTO_R1_DBG_RX_MPDU_CNT (0x00AA8034) +#define WMAC0_CRYPTO_R1_DBG_RX_MPDU_CNT___RWC QCSR_REG_RO +#define WMAC0_CRYPTO_R1_DBG_RX_MPDU_CNT___POR 0x00000000 +#define WMAC0_CRYPTO_R1_DBG_RX_MPDU_CNT__RX_MPDU_CNT___POR 0x00000000 +#define WMAC0_CRYPTO_R1_DBG_RX_MPDU_CNT__RX_MPDU_CNT___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_DBG_RX_MPDU_CNT__RX_MPDU_CNT___S 0 +#define WMAC0_CRYPTO_R1_DBG_RX_MPDU_CNT___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_DBG_RX_MPDU_CNT___S 0 + +#define WMAC0_CRYPTO_R1_DBG_RX_DECR_FRAME_CNT (0x00AA8038) +#define WMAC0_CRYPTO_R1_DBG_RX_DECR_FRAME_CNT___RWC QCSR_REG_RO +#define WMAC0_CRYPTO_R1_DBG_RX_DECR_FRAME_CNT___POR 0x00000000 +#define WMAC0_CRYPTO_R1_DBG_RX_DECR_FRAME_CNT__RX_DECR_FRAME_CNT___POR 0x00000000 +#define WMAC0_CRYPTO_R1_DBG_RX_DECR_FRAME_CNT__RX_DECR_FRAME_CNT___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_DBG_RX_DECR_FRAME_CNT__RX_DECR_FRAME_CNT___S 0 +#define WMAC0_CRYPTO_R1_DBG_RX_DECR_FRAME_CNT___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_DBG_RX_DECR_FRAME_CNT___S 0 + +#define WMAC0_CRYPTO_R1_DBG_RX_ABORT_CNT (0x00AA803C) +#define WMAC0_CRYPTO_R1_DBG_RX_ABORT_CNT___RWC QCSR_REG_RO +#define WMAC0_CRYPTO_R1_DBG_RX_ABORT_CNT___POR 0x00000000 +#define WMAC0_CRYPTO_R1_DBG_RX_ABORT_CNT__RX_ABORT_CNT___POR 0x0000 +#define WMAC0_CRYPTO_R1_DBG_RX_ABORT_CNT__RX_ABORT_CNT___M 0x0000FFFF +#define WMAC0_CRYPTO_R1_DBG_RX_ABORT_CNT__RX_ABORT_CNT___S 0 +#define WMAC0_CRYPTO_R1_DBG_RX_ABORT_CNT___M 0x0000FFFF +#define WMAC0_CRYPTO_R1_DBG_RX_ABORT_CNT___S 0 + +#define WMAC0_CRYPTO_R1_EVENTMASK_IX_0 (0x00AA8040) +#define WMAC0_CRYPTO_R1_EVENTMASK_IX_0___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R1_EVENTMASK_IX_0___POR 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_EVENTMASK_IX_0__EVENTBUS_MASK___POR 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_EVENTMASK_IX_0__EVENTBUS_MASK___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_EVENTMASK_IX_0__EVENTBUS_MASK___S 0 +#define WMAC0_CRYPTO_R1_EVENTMASK_IX_0___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_EVENTMASK_IX_0___S 0 + +#define WMAC0_CRYPTO_R1_EVENTMASK_IX_1 (0x00AA8044) +#define WMAC0_CRYPTO_R1_EVENTMASK_IX_1___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R1_EVENTMASK_IX_1___POR 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_EVENTMASK_IX_1__EVENTBUS_MASK___POR 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_EVENTMASK_IX_1__EVENTBUS_MASK___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_EVENTMASK_IX_1__EVENTBUS_MASK___S 0 +#define WMAC0_CRYPTO_R1_EVENTMASK_IX_1___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_EVENTMASK_IX_1___S 0 + +#define WMAC0_CRYPTO_R1_DBG_TX_SHORT_FRAME_CNT (0x00AA8048) +#define WMAC0_CRYPTO_R1_DBG_TX_SHORT_FRAME_CNT___RWC QCSR_REG_RO +#define WMAC0_CRYPTO_R1_DBG_TX_SHORT_FRAME_CNT___POR 0x00000000 +#define WMAC0_CRYPTO_R1_DBG_TX_SHORT_FRAME_CNT__TX_SHORT_FRAME_CNT___POR 0x00000000 +#define WMAC0_CRYPTO_R1_DBG_TX_SHORT_FRAME_CNT__TX_SHORT_FRAME_CNT___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_DBG_TX_SHORT_FRAME_CNT__TX_SHORT_FRAME_CNT___S 0 +#define WMAC0_CRYPTO_R1_DBG_TX_SHORT_FRAME_CNT___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_DBG_TX_SHORT_FRAME_CNT___S 0 + +#define WMAC0_CRYPTO_R1_DBG_RX_SHORT_FRAME_CNT (0x00AA804C) +#define WMAC0_CRYPTO_R1_DBG_RX_SHORT_FRAME_CNT___RWC QCSR_REG_RO +#define WMAC0_CRYPTO_R1_DBG_RX_SHORT_FRAME_CNT___POR 0x00000000 +#define WMAC0_CRYPTO_R1_DBG_RX_SHORT_FRAME_CNT__RX_SHORT_FRAME_CNT___POR 0x00000000 +#define WMAC0_CRYPTO_R1_DBG_RX_SHORT_FRAME_CNT__RX_SHORT_FRAME_CNT___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_DBG_RX_SHORT_FRAME_CNT__RX_SHORT_FRAME_CNT___S 0 +#define WMAC0_CRYPTO_R1_DBG_RX_SHORT_FRAME_CNT___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_DBG_RX_SHORT_FRAME_CNT___S 0 + +#define WMAC0_CRYPTO_R1_DBG_TX_DATA_CNT (0x00AA8050) +#define WMAC0_CRYPTO_R1_DBG_TX_DATA_CNT___RWC QCSR_REG_RO +#define WMAC0_CRYPTO_R1_DBG_TX_DATA_CNT___POR 0x00000000 +#define WMAC0_CRYPTO_R1_DBG_TX_DATA_CNT__TX_DATA_CNT___POR 0x00000000 +#define WMAC0_CRYPTO_R1_DBG_TX_DATA_CNT__TX_DATA_CNT___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_DBG_TX_DATA_CNT__TX_DATA_CNT___S 0 +#define WMAC0_CRYPTO_R1_DBG_TX_DATA_CNT___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_DBG_TX_DATA_CNT___S 0 + +#define WMAC0_CRYPTO_R1_DBG_TX_FES_CNT (0x00AA8054) +#define WMAC0_CRYPTO_R1_DBG_TX_FES_CNT___RWC QCSR_REG_RO +#define WMAC0_CRYPTO_R1_DBG_TX_FES_CNT___POR 0x00000000 +#define WMAC0_CRYPTO_R1_DBG_TX_FES_CNT__TX_FES_CNT___POR 0x00000000 +#define WMAC0_CRYPTO_R1_DBG_TX_FES_CNT__TX_FES_CNT___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_DBG_TX_FES_CNT__TX_FES_CNT___S 0 +#define WMAC0_CRYPTO_R1_DBG_TX_FES_CNT___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_DBG_TX_FES_CNT___S 0 + +#define WMAC0_CRYPTO_R1_DBG_RX_PPDU_CNT (0x00AA8058) +#define WMAC0_CRYPTO_R1_DBG_RX_PPDU_CNT___RWC QCSR_REG_RO +#define WMAC0_CRYPTO_R1_DBG_RX_PPDU_CNT___POR 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_DBG_RX_PPDU_CNT__RX_PPDU_CNT___POR 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_DBG_RX_PPDU_CNT__RX_PPDU_CNT___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_DBG_RX_PPDU_CNT__RX_PPDU_CNT___S 0 +#define WMAC0_CRYPTO_R1_DBG_RX_PPDU_CNT___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_DBG_RX_PPDU_CNT___S 0 + +#define WMAC0_CRYPTO_R1_RX_TLV_READY_TIMEOUT_VALUE (0x00AA805C) +#define WMAC0_CRYPTO_R1_RX_TLV_READY_TIMEOUT_VALUE___RWC QCSR_REG_RO +#define WMAC0_CRYPTO_R1_RX_TLV_READY_TIMEOUT_VALUE___POR 0x00000000 +#define WMAC0_CRYPTO_R1_RX_TLV_READY_TIMEOUT_VALUE__RX_TLV_READY_TIMEOUT_VALUE___POR 0x00000000 +#define WMAC0_CRYPTO_R1_RX_TLV_READY_TIMEOUT_VALUE__RX_TLV_READY_TIMEOUT_VALUE___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_RX_TLV_READY_TIMEOUT_VALUE__RX_TLV_READY_TIMEOUT_VALUE___S 0 +#define WMAC0_CRYPTO_R1_RX_TLV_READY_TIMEOUT_VALUE___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_RX_TLV_READY_TIMEOUT_VALUE___S 0 + +#define WMAC0_CRYPTO_R1_RX_TLV_READY_TIMEOUT_THRESHOLD (0x00AA8060) +#define WMAC0_CRYPTO_R1_RX_TLV_READY_TIMEOUT_THRESHOLD___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R1_RX_TLV_READY_TIMEOUT_THRESHOLD___POR 0x00000000 +#define WMAC0_CRYPTO_R1_RX_TLV_READY_TIMEOUT_THRESHOLD__RX_TLV_READY_TIMEOUT_THRESHOLD___POR 0x00000000 +#define WMAC0_CRYPTO_R1_RX_TLV_READY_TIMEOUT_THRESHOLD__RX_TLV_READY_TIMEOUT_THRESHOLD___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_RX_TLV_READY_TIMEOUT_THRESHOLD__RX_TLV_READY_TIMEOUT_THRESHOLD___S 0 +#define WMAC0_CRYPTO_R1_RX_TLV_READY_TIMEOUT_THRESHOLD___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_RX_TLV_READY_TIMEOUT_THRESHOLD___S 0 + +#define WMAC0_CRYPTO_R1_INVALID_APB_ACC_ADR (0x00AA8064) +#define WMAC0_CRYPTO_R1_INVALID_APB_ACC_ADR___RWC QCSR_REG_RO +#define WMAC0_CRYPTO_R1_INVALID_APB_ACC_ADR___POR 0x00000000 +#define WMAC0_CRYPTO_R1_INVALID_APB_ACC_ADR__APB_ADDRESS___POR 0x00000000 +#define WMAC0_CRYPTO_R1_INVALID_APB_ACC_ADR__APB_ADDRESS___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_INVALID_APB_ACC_ADR__APB_ADDRESS___S 0 +#define WMAC0_CRYPTO_R1_INVALID_APB_ACC_ADR___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_INVALID_APB_ACC_ADR___S 0 + +#define WMAC0_CRYPTO_R1_SM_STATES_IX_1 (0x00AA8068) +#define WMAC0_CRYPTO_R1_SM_STATES_IX_1___RWC QCSR_REG_RO +#define WMAC0_CRYPTO_R1_SM_STATES_IX_1___POR 0x00000000 +#define WMAC0_CRYPTO_R1_SM_STATES_IX_1__WAPI_LAST_BYTE_CNT___POR 0x0 +#define WMAC0_CRYPTO_R1_SM_STATES_IX_1__WAPI_NOT_A_16_BYTE_BLOCK___POR 0x0 +#define WMAC0_CRYPTO_R1_SM_STATES_IX_1__WAPI_OUT_BUF_EMPTY___POR 0x0 +#define WMAC0_CRYPTO_R1_SM_STATES_IX_1__WAPI_SM_ENC___POR 0x00 +#define WMAC0_CRYPTO_R1_SM_STATES_IX_1__WAPI_LAST_BYTE_CNT___M 0x00000E00 +#define WMAC0_CRYPTO_R1_SM_STATES_IX_1__WAPI_LAST_BYTE_CNT___S 9 +#define WMAC0_CRYPTO_R1_SM_STATES_IX_1__WAPI_NOT_A_16_BYTE_BLOCK___M 0x00000100 +#define WMAC0_CRYPTO_R1_SM_STATES_IX_1__WAPI_NOT_A_16_BYTE_BLOCK___S 8 +#define WMAC0_CRYPTO_R1_SM_STATES_IX_1__WAPI_OUT_BUF_EMPTY___M 0x00000080 +#define WMAC0_CRYPTO_R1_SM_STATES_IX_1__WAPI_OUT_BUF_EMPTY___S 7 +#define WMAC0_CRYPTO_R1_SM_STATES_IX_1__WAPI_SM_ENC___M 0x0000007F +#define WMAC0_CRYPTO_R1_SM_STATES_IX_1__WAPI_SM_ENC___S 0 +#define WMAC0_CRYPTO_R1_SM_STATES_IX_1___M 0x00000FFF +#define WMAC0_CRYPTO_R1_SM_STATES_IX_1___S 0 + +#define WMAC0_CRYPTO_R1_BUSY_STATUS (0x00AA806C) +#define WMAC0_CRYPTO_R1_BUSY_STATUS___RWC QCSR_REG_RO +#define WMAC0_CRYPTO_R1_BUSY_STATUS___POR 0x00000000 +#define WMAC0_CRYPTO_R1_BUSY_STATUS__CCM_RX_BUSY___POR 0x0 +#define WMAC0_CRYPTO_R1_BUSY_STATUS__CCM_TX_BUSY___POR 0x0 +#define WMAC0_CRYPTO_R1_BUSY_STATUS__CRYPTO_RX_WEPSTART___POR 0x0 +#define WMAC0_CRYPTO_R1_BUSY_STATUS__CRYPTO_TX_WEPSTART___POR 0x0 +#define WMAC0_CRYPTO_R1_BUSY_STATUS__CLK_CRYPTO_ENS___POR 0x00 +#define WMAC0_CRYPTO_R1_BUSY_STATUS__RXOLE_CRYPTO_READY___POR 0x0 +#define WMAC0_CRYPTO_R1_BUSY_STATUS__CRYPTO_RXPCU_READY___POR 0x0 +#define WMAC0_CRYPTO_R1_BUSY_STATUS__TXOLE_CRYPTO_READY___POR 0x0 +#define WMAC0_CRYPTO_R1_BUSY_STATUS__CRYPTO_TXPCU_READY___POR 0x0 +#define WMAC0_CRYPTO_R1_BUSY_STATUS__TXPCU_CRPTO_READY___POR 0x0 +#define WMAC0_CRYPTO_R1_BUSY_STATUS__CRYPTO_TXOLE_READY___POR 0x0 +#define WMAC0_CRYPTO_R1_BUSY_STATUS__CCM_RX_BUSY___M 0x00020000 +#define WMAC0_CRYPTO_R1_BUSY_STATUS__CCM_RX_BUSY___S 17 +#define WMAC0_CRYPTO_R1_BUSY_STATUS__CCM_TX_BUSY___M 0x00010000 +#define WMAC0_CRYPTO_R1_BUSY_STATUS__CCM_TX_BUSY___S 16 +#define WMAC0_CRYPTO_R1_BUSY_STATUS__CRYPTO_RX_WEPSTART___M 0x00008000 +#define WMAC0_CRYPTO_R1_BUSY_STATUS__CRYPTO_RX_WEPSTART___S 15 +#define WMAC0_CRYPTO_R1_BUSY_STATUS__CRYPTO_TX_WEPSTART___M 0x00004000 +#define WMAC0_CRYPTO_R1_BUSY_STATUS__CRYPTO_TX_WEPSTART___S 14 +#define WMAC0_CRYPTO_R1_BUSY_STATUS__CLK_CRYPTO_ENS___M 0x00003FC0 +#define WMAC0_CRYPTO_R1_BUSY_STATUS__CLK_CRYPTO_ENS___S 6 +#define WMAC0_CRYPTO_R1_BUSY_STATUS__RXOLE_CRYPTO_READY___M 0x00000020 +#define WMAC0_CRYPTO_R1_BUSY_STATUS__RXOLE_CRYPTO_READY___S 5 +#define WMAC0_CRYPTO_R1_BUSY_STATUS__CRYPTO_RXPCU_READY___M 0x00000010 +#define WMAC0_CRYPTO_R1_BUSY_STATUS__CRYPTO_RXPCU_READY___S 4 +#define WMAC0_CRYPTO_R1_BUSY_STATUS__TXOLE_CRYPTO_READY___M 0x00000008 +#define WMAC0_CRYPTO_R1_BUSY_STATUS__TXOLE_CRYPTO_READY___S 3 +#define WMAC0_CRYPTO_R1_BUSY_STATUS__CRYPTO_TXPCU_READY___M 0x00000004 +#define WMAC0_CRYPTO_R1_BUSY_STATUS__CRYPTO_TXPCU_READY___S 2 +#define WMAC0_CRYPTO_R1_BUSY_STATUS__TXPCU_CRPTO_READY___M 0x00000002 +#define WMAC0_CRYPTO_R1_BUSY_STATUS__TXPCU_CRPTO_READY___S 1 +#define WMAC0_CRYPTO_R1_BUSY_STATUS__CRYPTO_TXOLE_READY___M 0x00000001 +#define WMAC0_CRYPTO_R1_BUSY_STATUS__CRYPTO_TXOLE_READY___S 0 +#define WMAC0_CRYPTO_R1_BUSY_STATUS___M 0x0003FFFF +#define WMAC0_CRYPTO_R1_BUSY_STATUS___S 0 + +#define WMAC0_CRYPTO_R1_CSB_READ_CONFIG (0x00AA8070) +#define WMAC0_CRYPTO_R1_CSB_READ_CONFIG___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R1_CSB_READ_CONFIG___POR 0x00000000 +#define WMAC0_CRYPTO_R1_CSB_READ_CONFIG__CSB_COLN_CNT___POR 0x00 +#define WMAC0_CRYPTO_R1_CSB_READ_CONFIG__CSB_ROW_CNT___POR 0x00 +#define WMAC0_CRYPTO_R1_CSB_READ_CONFIG__CSB_COLN_CNT___M 0x0000FF00 +#define WMAC0_CRYPTO_R1_CSB_READ_CONFIG__CSB_COLN_CNT___S 8 +#define WMAC0_CRYPTO_R1_CSB_READ_CONFIG__CSB_ROW_CNT___M 0x000000FF +#define WMAC0_CRYPTO_R1_CSB_READ_CONFIG__CSB_ROW_CNT___S 0 +#define WMAC0_CRYPTO_R1_CSB_READ_CONFIG___M 0x0000FFFF +#define WMAC0_CRYPTO_R1_CSB_READ_CONFIG___S 0 + +#define WMAC0_CRYPTO_R1_CSB_USER_COUNT (0x00AA8074) +#define WMAC0_CRYPTO_R1_CSB_USER_COUNT___RWC QCSR_REG_RO +#define WMAC0_CRYPTO_R1_CSB_USER_COUNT___POR 0x00000000 +#define WMAC0_CRYPTO_R1_CSB_USER_COUNT__RX_USER_CNT___POR 0x00 +#define WMAC0_CRYPTO_R1_CSB_USER_COUNT__TX_USER_CNT___POR 0x00 +#define WMAC0_CRYPTO_R1_CSB_USER_COUNT__RX_USER_CNT___M 0x0000FF00 +#define WMAC0_CRYPTO_R1_CSB_USER_COUNT__RX_USER_CNT___S 8 +#define WMAC0_CRYPTO_R1_CSB_USER_COUNT__TX_USER_CNT___M 0x000000FF +#define WMAC0_CRYPTO_R1_CSB_USER_COUNT__TX_USER_CNT___S 0 +#define WMAC0_CRYPTO_R1_CSB_USER_COUNT___M 0x0000FFFF +#define WMAC0_CRYPTO_R1_CSB_USER_COUNT___S 0 + +#define WMAC0_CRYPTO_R1_TX_WEP_LEN (0x00AA8078) +#define WMAC0_CRYPTO_R1_TX_WEP_LEN___RWC QCSR_REG_RO +#define WMAC0_CRYPTO_R1_TX_WEP_LEN___POR 0x00000000 +#define WMAC0_CRYPTO_R1_TX_WEP_LEN__TX_DATA_LEN___POR 0x0000 +#define WMAC0_CRYPTO_R1_TX_WEP_LEN__TX_WEPLEN___POR 0x0000 +#define WMAC0_CRYPTO_R1_TX_WEP_LEN__TX_DATA_LEN___M 0xFFFF0000 +#define WMAC0_CRYPTO_R1_TX_WEP_LEN__TX_DATA_LEN___S 16 +#define WMAC0_CRYPTO_R1_TX_WEP_LEN__TX_WEPLEN___M 0x0000FFFF +#define WMAC0_CRYPTO_R1_TX_WEP_LEN__TX_WEPLEN___S 0 +#define WMAC0_CRYPTO_R1_TX_WEP_LEN___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_TX_WEP_LEN___S 0 + +#define WMAC0_CRYPTO_R1_RX_WATCHDOG_TIMER_VALUE (0x00AA807C) +#define WMAC0_CRYPTO_R1_RX_WATCHDOG_TIMER_VALUE___RWC QCSR_REG_RO +#define WMAC0_CRYPTO_R1_RX_WATCHDOG_TIMER_VALUE___POR 0x00000000 +#define WMAC0_CRYPTO_R1_RX_WATCHDOG_TIMER_VALUE__RX_WATCHDOG_VALUE___POR 0x00000000 +#define WMAC0_CRYPTO_R1_RX_WATCHDOG_TIMER_VALUE__RX_WATCHDOG_VALUE___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_RX_WATCHDOG_TIMER_VALUE__RX_WATCHDOG_VALUE___S 0 +#define WMAC0_CRYPTO_R1_RX_WATCHDOG_TIMER_VALUE___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_RX_WATCHDOG_TIMER_VALUE___S 0 + +#define WMAC0_CRYPTO_R1_RX_WATCHDOG_TIMER_THRESHOLD (0x00AA8080) +#define WMAC0_CRYPTO_R1_RX_WATCHDOG_TIMER_THRESHOLD___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R1_RX_WATCHDOG_TIMER_THRESHOLD___POR 0x00000000 +#define WMAC0_CRYPTO_R1_RX_WATCHDOG_TIMER_THRESHOLD__RX_WATCHDOG_THRESHOLD___POR 0x00000000 +#define WMAC0_CRYPTO_R1_RX_WATCHDOG_TIMER_THRESHOLD__RX_WATCHDOG_THRESHOLD___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_RX_WATCHDOG_TIMER_THRESHOLD__RX_WATCHDOG_THRESHOLD___S 0 +#define WMAC0_CRYPTO_R1_RX_WATCHDOG_TIMER_THRESHOLD___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_RX_WATCHDOG_TIMER_THRESHOLD___S 0 + +#define WMAC0_CRYPTO_R1_REG_ACCESS_EVENT_GEN_CTRL (0x00AA8084) +#define WMAC0_CRYPTO_R1_REG_ACCESS_EVENT_GEN_CTRL___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R1_REG_ACCESS_EVENT_GEN_CTRL___POR 0x7FFE0002 +#define WMAC0_CRYPTO_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___POR 0x3FFF +#define WMAC0_CRYPTO_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___POR 0x0000 +#define WMAC0_CRYPTO_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___POR 0x1 +#define WMAC0_CRYPTO_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___POR 0x0 +#define WMAC0_CRYPTO_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___M 0xFFFE0000 +#define WMAC0_CRYPTO_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___S 17 +#define WMAC0_CRYPTO_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___M 0x0001FFFC +#define WMAC0_CRYPTO_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___S 2 +#define WMAC0_CRYPTO_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___M 0x00000002 +#define WMAC0_CRYPTO_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___S 1 +#define WMAC0_CRYPTO_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___M 0x00000001 +#define WMAC0_CRYPTO_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___S 0 +#define WMAC0_CRYPTO_R1_REG_ACCESS_EVENT_GEN_CTRL___M 0xFFFFFFFF +#define WMAC0_CRYPTO_R1_REG_ACCESS_EVENT_GEN_CTRL___S 0 + +#define WMAC0_CRYPTO_R1_END_OF_TEST_CHECK (0x00AA8088) +#define WMAC0_CRYPTO_R1_END_OF_TEST_CHECK___RWC QCSR_REG_RW +#define WMAC0_CRYPTO_R1_END_OF_TEST_CHECK___POR 0x00000000 +#define WMAC0_CRYPTO_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0 +#define WMAC0_CRYPTO_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001 +#define WMAC0_CRYPTO_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S 0 +#define WMAC0_CRYPTO_R1_END_OF_TEST_CHECK___M 0x00000001 +#define WMAC0_CRYPTO_R1_END_OF_TEST_CHECK___S 0 + +#define WMAC0_HWSCH_R0_DIFS_LIMIT_1_0 (0x00AAA000) +#define WMAC0_HWSCH_R0_DIFS_LIMIT_1_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_DIFS_LIMIT_1_0___POR 0x001C0025 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_1_0__SW_MTU_DIFS_LIMIT_1___POR 0x01C +#define WMAC0_HWSCH_R0_DIFS_LIMIT_1_0__SW_MTU_DIFS_LIMIT_0___POR 0x025 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_1_0__SW_MTU_DIFS_LIMIT_1___M 0x03FF0000 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_1_0__SW_MTU_DIFS_LIMIT_1___S 16 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_1_0__SW_MTU_DIFS_LIMIT_0___M 0x000003FF +#define WMAC0_HWSCH_R0_DIFS_LIMIT_1_0__SW_MTU_DIFS_LIMIT_0___S 0 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_1_0___M 0x03FF03FF +#define WMAC0_HWSCH_R0_DIFS_LIMIT_1_0___S 0 + +#define WMAC0_HWSCH_R0_DIFS_LIMIT_3_2 (0x00AAA004) +#define WMAC0_HWSCH_R0_DIFS_LIMIT_3_2___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_DIFS_LIMIT_3_2___POR 0x001C0025 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_3_2__SW_MTU_DIFS_LIMIT_3___POR 0x01C +#define WMAC0_HWSCH_R0_DIFS_LIMIT_3_2__SW_MTU_DIFS_LIMIT_2___POR 0x025 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_3_2__SW_MTU_DIFS_LIMIT_3___M 0x03FF0000 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_3_2__SW_MTU_DIFS_LIMIT_3___S 16 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_3_2__SW_MTU_DIFS_LIMIT_2___M 0x000003FF +#define WMAC0_HWSCH_R0_DIFS_LIMIT_3_2__SW_MTU_DIFS_LIMIT_2___S 0 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_3_2___M 0x03FF03FF +#define WMAC0_HWSCH_R0_DIFS_LIMIT_3_2___S 0 + +#define WMAC0_HWSCH_R0_DIFS_LIMIT_5_4 (0x00AAA008) +#define WMAC0_HWSCH_R0_DIFS_LIMIT_5_4___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_DIFS_LIMIT_5_4___POR 0x001C0025 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_5_4__SW_MTU_DIFS_LIMIT_5___POR 0x01C +#define WMAC0_HWSCH_R0_DIFS_LIMIT_5_4__SW_MTU_DIFS_LIMIT_4___POR 0x025 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_5_4__SW_MTU_DIFS_LIMIT_5___M 0x03FF0000 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_5_4__SW_MTU_DIFS_LIMIT_5___S 16 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_5_4__SW_MTU_DIFS_LIMIT_4___M 0x000003FF +#define WMAC0_HWSCH_R0_DIFS_LIMIT_5_4__SW_MTU_DIFS_LIMIT_4___S 0 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_5_4___M 0x03FF03FF +#define WMAC0_HWSCH_R0_DIFS_LIMIT_5_4___S 0 + +#define WMAC0_HWSCH_R0_DIFS_LIMIT_7_6 (0x00AAA00C) +#define WMAC0_HWSCH_R0_DIFS_LIMIT_7_6___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_DIFS_LIMIT_7_6___POR 0x001C0025 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_7_6__SW_MTU_DIFS_LIMIT_7___POR 0x01C +#define WMAC0_HWSCH_R0_DIFS_LIMIT_7_6__SW_MTU_DIFS_LIMIT_6___POR 0x025 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_7_6__SW_MTU_DIFS_LIMIT_7___M 0x03FF0000 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_7_6__SW_MTU_DIFS_LIMIT_7___S 16 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_7_6__SW_MTU_DIFS_LIMIT_6___M 0x000003FF +#define WMAC0_HWSCH_R0_DIFS_LIMIT_7_6__SW_MTU_DIFS_LIMIT_6___S 0 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_7_6___M 0x03FF03FF +#define WMAC0_HWSCH_R0_DIFS_LIMIT_7_6___S 0 + +#define WMAC0_HWSCH_R0_DIFS_LIMIT_9_8 (0x00AAA010) +#define WMAC0_HWSCH_R0_DIFS_LIMIT_9_8___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_DIFS_LIMIT_9_8___POR 0x001C0025 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_9_8__SW_MTU_DIFS_LIMIT_9___POR 0x01C +#define WMAC0_HWSCH_R0_DIFS_LIMIT_9_8__SW_MTU_DIFS_LIMIT_8___POR 0x025 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_9_8__SW_MTU_DIFS_LIMIT_9___M 0x03FF0000 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_9_8__SW_MTU_DIFS_LIMIT_9___S 16 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_9_8__SW_MTU_DIFS_LIMIT_8___M 0x000003FF +#define WMAC0_HWSCH_R0_DIFS_LIMIT_9_8__SW_MTU_DIFS_LIMIT_8___S 0 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_9_8___M 0x03FF03FF +#define WMAC0_HWSCH_R0_DIFS_LIMIT_9_8___S 0 + +#define WMAC0_HWSCH_R0_DIFS_LIMIT_11_10 (0x00AAA014) +#define WMAC0_HWSCH_R0_DIFS_LIMIT_11_10___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_DIFS_LIMIT_11_10___POR 0x001C0025 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_11_10__SW_MTU_DIFS_LIMIT_11___POR 0x01C +#define WMAC0_HWSCH_R0_DIFS_LIMIT_11_10__SW_MTU_DIFS_LIMIT_10___POR 0x025 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_11_10__SW_MTU_DIFS_LIMIT_11___M 0x03FF0000 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_11_10__SW_MTU_DIFS_LIMIT_11___S 16 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_11_10__SW_MTU_DIFS_LIMIT_10___M 0x000003FF +#define WMAC0_HWSCH_R0_DIFS_LIMIT_11_10__SW_MTU_DIFS_LIMIT_10___S 0 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_11_10___M 0x03FF03FF +#define WMAC0_HWSCH_R0_DIFS_LIMIT_11_10___S 0 + +#define WMAC0_HWSCH_R0_DIFS_LIMIT_13_12 (0x00AAA018) +#define WMAC0_HWSCH_R0_DIFS_LIMIT_13_12___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_DIFS_LIMIT_13_12___POR 0x001C0025 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_13_12__SW_MTU_DIFS_LIMIT_13___POR 0x01C +#define WMAC0_HWSCH_R0_DIFS_LIMIT_13_12__SW_MTU_DIFS_LIMIT_12___POR 0x025 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_13_12__SW_MTU_DIFS_LIMIT_13___M 0x03FF0000 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_13_12__SW_MTU_DIFS_LIMIT_13___S 16 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_13_12__SW_MTU_DIFS_LIMIT_12___M 0x000003FF +#define WMAC0_HWSCH_R0_DIFS_LIMIT_13_12__SW_MTU_DIFS_LIMIT_12___S 0 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_13_12___M 0x03FF03FF +#define WMAC0_HWSCH_R0_DIFS_LIMIT_13_12___S 0 + +#define WMAC0_HWSCH_R0_DIFS_LIMIT_15_14 (0x00AAA01C) +#define WMAC0_HWSCH_R0_DIFS_LIMIT_15_14___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_DIFS_LIMIT_15_14___POR 0x001C0025 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_15_14__SW_MTU_DIFS_LIMIT_15___POR 0x01C +#define WMAC0_HWSCH_R0_DIFS_LIMIT_15_14__SW_MTU_DIFS_LIMIT_14___POR 0x025 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_15_14__SW_MTU_DIFS_LIMIT_15___M 0x03FF0000 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_15_14__SW_MTU_DIFS_LIMIT_15___S 16 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_15_14__SW_MTU_DIFS_LIMIT_14___M 0x000003FF +#define WMAC0_HWSCH_R0_DIFS_LIMIT_15_14__SW_MTU_DIFS_LIMIT_14___S 0 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_15_14___M 0x03FF03FF +#define WMAC0_HWSCH_R0_DIFS_LIMIT_15_14___S 0 + +#define WMAC0_HWSCH_R0_DIFS_LIMIT_17_16 (0x00AAA020) +#define WMAC0_HWSCH_R0_DIFS_LIMIT_17_16___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_DIFS_LIMIT_17_16___POR 0x001C0025 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_17_16__SW_MTU_DIFS_LIMIT_17___POR 0x01C +#define WMAC0_HWSCH_R0_DIFS_LIMIT_17_16__SW_MTU_DIFS_LIMIT_16___POR 0x025 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_17_16__SW_MTU_DIFS_LIMIT_17___M 0x03FF0000 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_17_16__SW_MTU_DIFS_LIMIT_17___S 16 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_17_16__SW_MTU_DIFS_LIMIT_16___M 0x000003FF +#define WMAC0_HWSCH_R0_DIFS_LIMIT_17_16__SW_MTU_DIFS_LIMIT_16___S 0 +#define WMAC0_HWSCH_R0_DIFS_LIMIT_17_16___M 0x03FF03FF +#define WMAC0_HWSCH_R0_DIFS_LIMIT_17_16___S 0 + +#define WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT (0x00AAA028) +#define WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT___POR 0x00001909 +#define WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT__DYNAMIC_EIFS_ENABLE___POR 0x0 +#define WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT__SW_PIFS_LIMIT___POR 0x019 +#define WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT__SW_MTU_SLOT_LIMIT___POR 0x09 +#define WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT__DYNAMIC_EIFS_ENABLE___M 0x00020000 +#define WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT__DYNAMIC_EIFS_ENABLE___S 17 +#define WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT__SW_PIFS_LIMIT___M 0x0001FF00 +#define WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT__SW_PIFS_LIMIT___S 8 +#define WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT__SW_MTU_SLOT_LIMIT___M 0x000000FF +#define WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT__SW_MTU_SLOT_LIMIT___S 0 +#define WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT___M 0x0003FFFF +#define WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT___S 0 + +#define WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT_1 (0x00AAA02C) +#define WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT_1___POR 0x0000005A +#define WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT_1__SW_MTU_EIFS_LIMIT___POR 0x005A +#define WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT_1__SW_MTU_EIFS_LIMIT___M 0x0000FFFF +#define WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT_1__SW_MTU_EIFS_LIMIT___S 0 +#define WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT_1___M 0x0000FFFF +#define WMAC0_HWSCH_R0_EIFS_PIFS_BCN_SLOT_LIMIT_1___S 0 + +#define WMAC0_HWSCH_R0_COEX_CTRL (0x00AAA030) +#define WMAC0_HWSCH_R0_COEX_CTRL___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_COEX_CTRL___POR 0x00000F18 +#define WMAC0_HWSCH_R0_COEX_CTRL__IGNORE_INBSS_NAV_ZERO_COEX_STAT___POR 0x0 +#define WMAC0_HWSCH_R0_COEX_CTRL__IGNORE_FIELDS_IN_BLOCK_CANCEL___POR 0x0 +#define WMAC0_HWSCH_R0_COEX_CTRL__BCAST_MASK_WLAN_TX_START___POR 0x1 +#define WMAC0_HWSCH_R0_COEX_CTRL__BCAST_MASK_WLAN_TX_END___POR 0x1 +#define WMAC0_HWSCH_R0_COEX_CTRL__BCAST_MASK_WLAN_RX_START___POR 0x1 +#define WMAC0_HWSCH_R0_COEX_CTRL__BCAST_MASK_WLAN_RX_END___POR 0x1 +#define WMAC0_HWSCH_R0_COEX_CTRL__FORCE_SEND_SCH_STATUS_TLV___POR 0x0 +#define WMAC0_HWSCH_R0_COEX_CTRL__BLOCK_SCH_STATUS_TLV___POR 0x0 +#define WMAC0_HWSCH_R0_COEX_CTRL__ENABLE_FILTER_SOFT_ABORT___POR 0x0 +#define WMAC0_HWSCH_R0_COEX_CTRL__ENABLE_SOFT_2_HARD_ABORT___POR 0x1 +#define WMAC0_HWSCH_R0_COEX_CTRL__DISABLE_COEX_AUTO_FLUSH___POR 0x1 +#define WMAC0_HWSCH_R0_COEX_CTRL__IGNORE_INBSS_NAV_ZERO_COEX_STAT___M 0x00002000 +#define WMAC0_HWSCH_R0_COEX_CTRL__IGNORE_INBSS_NAV_ZERO_COEX_STAT___S 13 +#define WMAC0_HWSCH_R0_COEX_CTRL__IGNORE_FIELDS_IN_BLOCK_CANCEL___M 0x00001000 +#define WMAC0_HWSCH_R0_COEX_CTRL__IGNORE_FIELDS_IN_BLOCK_CANCEL___S 12 +#define WMAC0_HWSCH_R0_COEX_CTRL__BCAST_MASK_WLAN_TX_START___M 0x00000800 +#define WMAC0_HWSCH_R0_COEX_CTRL__BCAST_MASK_WLAN_TX_START___S 11 +#define WMAC0_HWSCH_R0_COEX_CTRL__BCAST_MASK_WLAN_TX_END___M 0x00000400 +#define WMAC0_HWSCH_R0_COEX_CTRL__BCAST_MASK_WLAN_TX_END___S 10 +#define WMAC0_HWSCH_R0_COEX_CTRL__BCAST_MASK_WLAN_RX_START___M 0x00000200 +#define WMAC0_HWSCH_R0_COEX_CTRL__BCAST_MASK_WLAN_RX_START___S 9 +#define WMAC0_HWSCH_R0_COEX_CTRL__BCAST_MASK_WLAN_RX_END___M 0x00000100 +#define WMAC0_HWSCH_R0_COEX_CTRL__BCAST_MASK_WLAN_RX_END___S 8 +#define WMAC0_HWSCH_R0_COEX_CTRL__FORCE_SEND_SCH_STATUS_TLV___M 0x00000080 +#define WMAC0_HWSCH_R0_COEX_CTRL__FORCE_SEND_SCH_STATUS_TLV___S 7 +#define WMAC0_HWSCH_R0_COEX_CTRL__BLOCK_SCH_STATUS_TLV___M 0x00000040 +#define WMAC0_HWSCH_R0_COEX_CTRL__BLOCK_SCH_STATUS_TLV___S 6 +#define WMAC0_HWSCH_R0_COEX_CTRL__ENABLE_FILTER_SOFT_ABORT___M 0x00000020 +#define WMAC0_HWSCH_R0_COEX_CTRL__ENABLE_FILTER_SOFT_ABORT___S 5 +#define WMAC0_HWSCH_R0_COEX_CTRL__ENABLE_SOFT_2_HARD_ABORT___M 0x00000010 +#define WMAC0_HWSCH_R0_COEX_CTRL__ENABLE_SOFT_2_HARD_ABORT___S 4 +#define WMAC0_HWSCH_R0_COEX_CTRL__DISABLE_COEX_AUTO_FLUSH___M 0x00000008 +#define WMAC0_HWSCH_R0_COEX_CTRL__DISABLE_COEX_AUTO_FLUSH___S 3 +#define WMAC0_HWSCH_R0_COEX_CTRL___M 0x00003FF8 +#define WMAC0_HWSCH_R0_COEX_CTRL___S 3 + +#define WMAC0_HWSCH_R0_RID_CNT (0x00AAA034) +#define WMAC0_HWSCH_R0_RID_CNT___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_RID_CNT___POR 0x000000FF +#define WMAC0_HWSCH_R0_RID_CNT__RID_CNT___POR 0x000000FF +#define WMAC0_HWSCH_R0_RID_CNT__RID_CNT___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_RID_CNT__RID_CNT___S 0 +#define WMAC0_HWSCH_R0_RID_CNT___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_RID_CNT___S 0 + +#define WMAC0_HWSCH_R0_NAV_CNT (0x00AAA038) +#define WMAC0_HWSCH_R0_NAV_CNT___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_NAV_CNT___POR 0x000000FF +#define WMAC0_HWSCH_R0_NAV_CNT__NAV_CNT___POR 0x000000FF +#define WMAC0_HWSCH_R0_NAV_CNT__NAV_CNT___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_NAV_CNT__NAV_CNT___S 0 +#define WMAC0_HWSCH_R0_NAV_CNT___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_NAV_CNT___S 0 + +#define WMAC0_HWSCH_R0_SW_MTU_SHADOW_NAV_CNT (0x00AAA03C) +#define WMAC0_HWSCH_R0_SW_MTU_SHADOW_NAV_CNT___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SW_MTU_SHADOW_NAV_CNT___POR 0x000000FF +#define WMAC0_HWSCH_R0_SW_MTU_SHADOW_NAV_CNT__SW_MTU_SHADOW_NAV_CNT___POR 0x000000FF +#define WMAC0_HWSCH_R0_SW_MTU_SHADOW_NAV_CNT__SW_MTU_SHADOW_NAV_CNT___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SW_MTU_SHADOW_NAV_CNT__SW_MTU_SHADOW_NAV_CNT___S 0 +#define WMAC0_HWSCH_R0_SW_MTU_SHADOW_NAV_CNT___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SW_MTU_SHADOW_NAV_CNT___S 0 + +#define WMAC0_HWSCH_R0_BKOF_CNT_0 (0x00AAA040) +#define WMAC0_HWSCH_R0_BKOF_CNT_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_BKOF_CNT_0___POR 0x00040003 +#define WMAC0_HWSCH_R0_BKOF_CNT_0__REMAINING_SLOT_COUNT_0___POR 0x04 +#define WMAC0_HWSCH_R0_BKOF_CNT_0__BKOF_CNT_0___POR 0x0003 +#define WMAC0_HWSCH_R0_BKOF_CNT_0__REMAINING_SLOT_COUNT_0___M 0x00FF0000 +#define WMAC0_HWSCH_R0_BKOF_CNT_0__REMAINING_SLOT_COUNT_0___S 16 +#define WMAC0_HWSCH_R0_BKOF_CNT_0__BKOF_CNT_0___M 0x0000FFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_0__BKOF_CNT_0___S 0 +#define WMAC0_HWSCH_R0_BKOF_CNT_0___M 0x00FFFFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_0___S 0 + +#define WMAC0_HWSCH_R0_BKOF_CNT_1 (0x00AAA044) +#define WMAC0_HWSCH_R0_BKOF_CNT_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_BKOF_CNT_1___POR 0x00040003 +#define WMAC0_HWSCH_R0_BKOF_CNT_1__REMAINING_SLOT_COUNT_1___POR 0x04 +#define WMAC0_HWSCH_R0_BKOF_CNT_1__BKOF_CNT_1___POR 0x0003 +#define WMAC0_HWSCH_R0_BKOF_CNT_1__REMAINING_SLOT_COUNT_1___M 0x00FF0000 +#define WMAC0_HWSCH_R0_BKOF_CNT_1__REMAINING_SLOT_COUNT_1___S 16 +#define WMAC0_HWSCH_R0_BKOF_CNT_1__BKOF_CNT_1___M 0x0000FFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_1__BKOF_CNT_1___S 0 +#define WMAC0_HWSCH_R0_BKOF_CNT_1___M 0x00FFFFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_1___S 0 + +#define WMAC0_HWSCH_R0_BKOF_CNT_2 (0x00AAA048) +#define WMAC0_HWSCH_R0_BKOF_CNT_2___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_BKOF_CNT_2___POR 0x00040003 +#define WMAC0_HWSCH_R0_BKOF_CNT_2__REMAINING_SLOT_COUNT_2___POR 0x04 +#define WMAC0_HWSCH_R0_BKOF_CNT_2__BKOF_CNT_2___POR 0x0003 +#define WMAC0_HWSCH_R0_BKOF_CNT_2__REMAINING_SLOT_COUNT_2___M 0x00FF0000 +#define WMAC0_HWSCH_R0_BKOF_CNT_2__REMAINING_SLOT_COUNT_2___S 16 +#define WMAC0_HWSCH_R0_BKOF_CNT_2__BKOF_CNT_2___M 0x0000FFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_2__BKOF_CNT_2___S 0 +#define WMAC0_HWSCH_R0_BKOF_CNT_2___M 0x00FFFFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_2___S 0 + +#define WMAC0_HWSCH_R0_BKOF_CNT_3 (0x00AAA04C) +#define WMAC0_HWSCH_R0_BKOF_CNT_3___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_BKOF_CNT_3___POR 0x00040003 +#define WMAC0_HWSCH_R0_BKOF_CNT_3__REMAINING_SLOT_COUNT_3___POR 0x04 +#define WMAC0_HWSCH_R0_BKOF_CNT_3__BKOF_CNT_3___POR 0x0003 +#define WMAC0_HWSCH_R0_BKOF_CNT_3__REMAINING_SLOT_COUNT_3___M 0x00FF0000 +#define WMAC0_HWSCH_R0_BKOF_CNT_3__REMAINING_SLOT_COUNT_3___S 16 +#define WMAC0_HWSCH_R0_BKOF_CNT_3__BKOF_CNT_3___M 0x0000FFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_3__BKOF_CNT_3___S 0 +#define WMAC0_HWSCH_R0_BKOF_CNT_3___M 0x00FFFFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_3___S 0 + +#define WMAC0_HWSCH_R0_BKOF_CNT_4 (0x00AAA050) +#define WMAC0_HWSCH_R0_BKOF_CNT_4___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_BKOF_CNT_4___POR 0x00040003 +#define WMAC0_HWSCH_R0_BKOF_CNT_4__REMAINING_SLOT_COUNT_4___POR 0x04 +#define WMAC0_HWSCH_R0_BKOF_CNT_4__BKOF_CNT_4___POR 0x0003 +#define WMAC0_HWSCH_R0_BKOF_CNT_4__REMAINING_SLOT_COUNT_4___M 0x00FF0000 +#define WMAC0_HWSCH_R0_BKOF_CNT_4__REMAINING_SLOT_COUNT_4___S 16 +#define WMAC0_HWSCH_R0_BKOF_CNT_4__BKOF_CNT_4___M 0x0000FFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_4__BKOF_CNT_4___S 0 +#define WMAC0_HWSCH_R0_BKOF_CNT_4___M 0x00FFFFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_4___S 0 + +#define WMAC0_HWSCH_R0_BKOF_CNT_5 (0x00AAA054) +#define WMAC0_HWSCH_R0_BKOF_CNT_5___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_BKOF_CNT_5___POR 0x00040003 +#define WMAC0_HWSCH_R0_BKOF_CNT_5__REMAINING_SLOT_COUNT_5___POR 0x04 +#define WMAC0_HWSCH_R0_BKOF_CNT_5__BKOF_CNT_5___POR 0x0003 +#define WMAC0_HWSCH_R0_BKOF_CNT_5__REMAINING_SLOT_COUNT_5___M 0x00FF0000 +#define WMAC0_HWSCH_R0_BKOF_CNT_5__REMAINING_SLOT_COUNT_5___S 16 +#define WMAC0_HWSCH_R0_BKOF_CNT_5__BKOF_CNT_5___M 0x0000FFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_5__BKOF_CNT_5___S 0 +#define WMAC0_HWSCH_R0_BKOF_CNT_5___M 0x00FFFFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_5___S 0 + +#define WMAC0_HWSCH_R0_BKOF_CNT_6 (0x00AAA058) +#define WMAC0_HWSCH_R0_BKOF_CNT_6___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_BKOF_CNT_6___POR 0x00040003 +#define WMAC0_HWSCH_R0_BKOF_CNT_6__REMAINING_SLOT_COUNT_6___POR 0x04 +#define WMAC0_HWSCH_R0_BKOF_CNT_6__BKOF_CNT_6___POR 0x0003 +#define WMAC0_HWSCH_R0_BKOF_CNT_6__REMAINING_SLOT_COUNT_6___M 0x00FF0000 +#define WMAC0_HWSCH_R0_BKOF_CNT_6__REMAINING_SLOT_COUNT_6___S 16 +#define WMAC0_HWSCH_R0_BKOF_CNT_6__BKOF_CNT_6___M 0x0000FFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_6__BKOF_CNT_6___S 0 +#define WMAC0_HWSCH_R0_BKOF_CNT_6___M 0x00FFFFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_6___S 0 + +#define WMAC0_HWSCH_R0_BKOF_CNT_7 (0x00AAA05C) +#define WMAC0_HWSCH_R0_BKOF_CNT_7___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_BKOF_CNT_7___POR 0x00040003 +#define WMAC0_HWSCH_R0_BKOF_CNT_7__REMAINING_SLOT_COUNT_7___POR 0x04 +#define WMAC0_HWSCH_R0_BKOF_CNT_7__BKOF_CNT_7___POR 0x0003 +#define WMAC0_HWSCH_R0_BKOF_CNT_7__REMAINING_SLOT_COUNT_7___M 0x00FF0000 +#define WMAC0_HWSCH_R0_BKOF_CNT_7__REMAINING_SLOT_COUNT_7___S 16 +#define WMAC0_HWSCH_R0_BKOF_CNT_7__BKOF_CNT_7___M 0x0000FFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_7__BKOF_CNT_7___S 0 +#define WMAC0_HWSCH_R0_BKOF_CNT_7___M 0x00FFFFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_7___S 0 + +#define WMAC0_HWSCH_R0_BKOF_CNT_8 (0x00AAA060) +#define WMAC0_HWSCH_R0_BKOF_CNT_8___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_BKOF_CNT_8___POR 0x00040003 +#define WMAC0_HWSCH_R0_BKOF_CNT_8__REMAINING_SLOT_COUNT_8___POR 0x04 +#define WMAC0_HWSCH_R0_BKOF_CNT_8__BKOF_CNT_8___POR 0x0003 +#define WMAC0_HWSCH_R0_BKOF_CNT_8__REMAINING_SLOT_COUNT_8___M 0x00FF0000 +#define WMAC0_HWSCH_R0_BKOF_CNT_8__REMAINING_SLOT_COUNT_8___S 16 +#define WMAC0_HWSCH_R0_BKOF_CNT_8__BKOF_CNT_8___M 0x0000FFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_8__BKOF_CNT_8___S 0 +#define WMAC0_HWSCH_R0_BKOF_CNT_8___M 0x00FFFFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_8___S 0 + +#define WMAC0_HWSCH_R0_BKOF_CNT_9 (0x00AAA064) +#define WMAC0_HWSCH_R0_BKOF_CNT_9___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_BKOF_CNT_9___POR 0x00040003 +#define WMAC0_HWSCH_R0_BKOF_CNT_9__REMAINING_SLOT_COUNT_9___POR 0x04 +#define WMAC0_HWSCH_R0_BKOF_CNT_9__BKOF_CNT_9___POR 0x0003 +#define WMAC0_HWSCH_R0_BKOF_CNT_9__REMAINING_SLOT_COUNT_9___M 0x00FF0000 +#define WMAC0_HWSCH_R0_BKOF_CNT_9__REMAINING_SLOT_COUNT_9___S 16 +#define WMAC0_HWSCH_R0_BKOF_CNT_9__BKOF_CNT_9___M 0x0000FFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_9__BKOF_CNT_9___S 0 +#define WMAC0_HWSCH_R0_BKOF_CNT_9___M 0x00FFFFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_9___S 0 + +#define WMAC0_HWSCH_R0_BKOF_CNT_10 (0x00AAA068) +#define WMAC0_HWSCH_R0_BKOF_CNT_10___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_BKOF_CNT_10___POR 0x00040003 +#define WMAC0_HWSCH_R0_BKOF_CNT_10__REMAINING_SLOT_COUNT_10___POR 0x04 +#define WMAC0_HWSCH_R0_BKOF_CNT_10__BKOF_CNT_10___POR 0x0003 +#define WMAC0_HWSCH_R0_BKOF_CNT_10__REMAINING_SLOT_COUNT_10___M 0x00FF0000 +#define WMAC0_HWSCH_R0_BKOF_CNT_10__REMAINING_SLOT_COUNT_10___S 16 +#define WMAC0_HWSCH_R0_BKOF_CNT_10__BKOF_CNT_10___M 0x0000FFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_10__BKOF_CNT_10___S 0 +#define WMAC0_HWSCH_R0_BKOF_CNT_10___M 0x00FFFFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_10___S 0 + +#define WMAC0_HWSCH_R0_BKOF_CNT_11 (0x00AAA06C) +#define WMAC0_HWSCH_R0_BKOF_CNT_11___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_BKOF_CNT_11___POR 0x00040003 +#define WMAC0_HWSCH_R0_BKOF_CNT_11__REMAINING_SLOT_COUNT_11___POR 0x04 +#define WMAC0_HWSCH_R0_BKOF_CNT_11__BKOF_CNT_11___POR 0x0003 +#define WMAC0_HWSCH_R0_BKOF_CNT_11__REMAINING_SLOT_COUNT_11___M 0x00FF0000 +#define WMAC0_HWSCH_R0_BKOF_CNT_11__REMAINING_SLOT_COUNT_11___S 16 +#define WMAC0_HWSCH_R0_BKOF_CNT_11__BKOF_CNT_11___M 0x0000FFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_11__BKOF_CNT_11___S 0 +#define WMAC0_HWSCH_R0_BKOF_CNT_11___M 0x00FFFFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_11___S 0 + +#define WMAC0_HWSCH_R0_BKOF_CNT_12 (0x00AAA070) +#define WMAC0_HWSCH_R0_BKOF_CNT_12___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_BKOF_CNT_12___POR 0x00040003 +#define WMAC0_HWSCH_R0_BKOF_CNT_12__REMAINING_SLOT_COUNT_12___POR 0x04 +#define WMAC0_HWSCH_R0_BKOF_CNT_12__BKOF_CNT_12___POR 0x0003 +#define WMAC0_HWSCH_R0_BKOF_CNT_12__REMAINING_SLOT_COUNT_12___M 0x00FF0000 +#define WMAC0_HWSCH_R0_BKOF_CNT_12__REMAINING_SLOT_COUNT_12___S 16 +#define WMAC0_HWSCH_R0_BKOF_CNT_12__BKOF_CNT_12___M 0x0000FFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_12__BKOF_CNT_12___S 0 +#define WMAC0_HWSCH_R0_BKOF_CNT_12___M 0x00FFFFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_12___S 0 + +#define WMAC0_HWSCH_R0_BKOF_CNT_13 (0x00AAA074) +#define WMAC0_HWSCH_R0_BKOF_CNT_13___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_BKOF_CNT_13___POR 0x00040003 +#define WMAC0_HWSCH_R0_BKOF_CNT_13__REMAINING_SLOT_COUNT_13___POR 0x04 +#define WMAC0_HWSCH_R0_BKOF_CNT_13__BKOF_CNT_13___POR 0x0003 +#define WMAC0_HWSCH_R0_BKOF_CNT_13__REMAINING_SLOT_COUNT_13___M 0x00FF0000 +#define WMAC0_HWSCH_R0_BKOF_CNT_13__REMAINING_SLOT_COUNT_13___S 16 +#define WMAC0_HWSCH_R0_BKOF_CNT_13__BKOF_CNT_13___M 0x0000FFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_13__BKOF_CNT_13___S 0 +#define WMAC0_HWSCH_R0_BKOF_CNT_13___M 0x00FFFFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_13___S 0 + +#define WMAC0_HWSCH_R0_BKOF_CNT_14 (0x00AAA078) +#define WMAC0_HWSCH_R0_BKOF_CNT_14___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_BKOF_CNT_14___POR 0x00040003 +#define WMAC0_HWSCH_R0_BKOF_CNT_14__REMAINING_SLOT_COUNT_14___POR 0x04 +#define WMAC0_HWSCH_R0_BKOF_CNT_14__BKOF_CNT_14___POR 0x0003 +#define WMAC0_HWSCH_R0_BKOF_CNT_14__REMAINING_SLOT_COUNT_14___M 0x00FF0000 +#define WMAC0_HWSCH_R0_BKOF_CNT_14__REMAINING_SLOT_COUNT_14___S 16 +#define WMAC0_HWSCH_R0_BKOF_CNT_14__BKOF_CNT_14___M 0x0000FFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_14__BKOF_CNT_14___S 0 +#define WMAC0_HWSCH_R0_BKOF_CNT_14___M 0x00FFFFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_14___S 0 + +#define WMAC0_HWSCH_R0_BKOF_CNT_15 (0x00AAA07C) +#define WMAC0_HWSCH_R0_BKOF_CNT_15___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_BKOF_CNT_15___POR 0x00040003 +#define WMAC0_HWSCH_R0_BKOF_CNT_15__REMAINING_SLOT_COUNT_15___POR 0x04 +#define WMAC0_HWSCH_R0_BKOF_CNT_15__BKOF_CNT_15___POR 0x0003 +#define WMAC0_HWSCH_R0_BKOF_CNT_15__REMAINING_SLOT_COUNT_15___M 0x00FF0000 +#define WMAC0_HWSCH_R0_BKOF_CNT_15__REMAINING_SLOT_COUNT_15___S 16 +#define WMAC0_HWSCH_R0_BKOF_CNT_15__BKOF_CNT_15___M 0x0000FFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_15__BKOF_CNT_15___S 0 +#define WMAC0_HWSCH_R0_BKOF_CNT_15___M 0x00FFFFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_15___S 0 + +#define WMAC0_HWSCH_R0_BKOF_CNT_16 (0x00AAA080) +#define WMAC0_HWSCH_R0_BKOF_CNT_16___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_BKOF_CNT_16___POR 0x00040003 +#define WMAC0_HWSCH_R0_BKOF_CNT_16__REMAINING_SLOT_COUNT_16___POR 0x04 +#define WMAC0_HWSCH_R0_BKOF_CNT_16__BKOF_CNT_16___POR 0x0003 +#define WMAC0_HWSCH_R0_BKOF_CNT_16__REMAINING_SLOT_COUNT_16___M 0x00FF0000 +#define WMAC0_HWSCH_R0_BKOF_CNT_16__REMAINING_SLOT_COUNT_16___S 16 +#define WMAC0_HWSCH_R0_BKOF_CNT_16__BKOF_CNT_16___M 0x0000FFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_16__BKOF_CNT_16___S 0 +#define WMAC0_HWSCH_R0_BKOF_CNT_16___M 0x00FFFFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_16___S 0 + +#define WMAC0_HWSCH_R0_BKOF_CNT_17 (0x00AAA084) +#define WMAC0_HWSCH_R0_BKOF_CNT_17___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_BKOF_CNT_17___POR 0x00040003 +#define WMAC0_HWSCH_R0_BKOF_CNT_17__REMAINING_SLOT_COUNT_17___POR 0x04 +#define WMAC0_HWSCH_R0_BKOF_CNT_17__BKOF_CNT_17___POR 0x0003 +#define WMAC0_HWSCH_R0_BKOF_CNT_17__REMAINING_SLOT_COUNT_17___M 0x00FF0000 +#define WMAC0_HWSCH_R0_BKOF_CNT_17__REMAINING_SLOT_COUNT_17___S 16 +#define WMAC0_HWSCH_R0_BKOF_CNT_17__BKOF_CNT_17___M 0x0000FFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_17__BKOF_CNT_17___S 0 +#define WMAC0_HWSCH_R0_BKOF_CNT_17___M 0x00FFFFFF +#define WMAC0_HWSCH_R0_BKOF_CNT_17___S 0 + +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_0 (0x00AAA090) +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_0___POR 0x00000007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_0__SW_MTU_CW_REG_0___POR 0x0007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_0__SW_MTU_CW_REG_0___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_0__SW_MTU_CW_REG_0___S 0 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_0___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_0___S 0 + +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_1 (0x00AAA094) +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_1___POR 0x00000007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_1__SW_MTU_CW_REG_1___POR 0x0007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_1__SW_MTU_CW_REG_1___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_1__SW_MTU_CW_REG_1___S 0 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_1___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_1___S 0 + +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_2 (0x00AAA098) +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_2___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_2___POR 0x00000007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_2__SW_MTU_CW_REG_2___POR 0x0007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_2__SW_MTU_CW_REG_2___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_2__SW_MTU_CW_REG_2___S 0 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_2___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_2___S 0 + +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_3 (0x00AAA09C) +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_3___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_3___POR 0x00000007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_3__SW_MTU_CW_REG_3___POR 0x0007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_3__SW_MTU_CW_REG_3___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_3__SW_MTU_CW_REG_3___S 0 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_3___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_3___S 0 + +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_4 (0x00AAA0A0) +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_4___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_4___POR 0x00000007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_4__SW_MTU_CW_REG_4___POR 0x0007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_4__SW_MTU_CW_REG_4___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_4__SW_MTU_CW_REG_4___S 0 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_4___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_4___S 0 + +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_5 (0x00AAA0A4) +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_5___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_5___POR 0x00000007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_5__SW_MTU_CW_REG_5___POR 0x0007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_5__SW_MTU_CW_REG_5___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_5__SW_MTU_CW_REG_5___S 0 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_5___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_5___S 0 + +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_6 (0x00AAA0A8) +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_6___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_6___POR 0x00000007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_6__SW_MTU_CW_REG_6___POR 0x0007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_6__SW_MTU_CW_REG_6___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_6__SW_MTU_CW_REG_6___S 0 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_6___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_6___S 0 + +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_7 (0x00AAA0AC) +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_7___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_7___POR 0x00000007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_7__SW_MTU_CW_REG_7___POR 0x0007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_7__SW_MTU_CW_REG_7___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_7__SW_MTU_CW_REG_7___S 0 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_7___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_7___S 0 + +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_8 (0x00AAA0B0) +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_8___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_8___POR 0x00000007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_8__SW_MTU_CW_REG_8___POR 0x0007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_8__SW_MTU_CW_REG_8___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_8__SW_MTU_CW_REG_8___S 0 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_8___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_8___S 0 + +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_9 (0x00AAA0B4) +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_9___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_9___POR 0x00000007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_9__SW_MTU_CW_REG_9___POR 0x0007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_9__SW_MTU_CW_REG_9___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_9__SW_MTU_CW_REG_9___S 0 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_9___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_9___S 0 + +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_10 (0x00AAA0B8) +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_10___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_10___POR 0x00000007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_10__SW_MTU_CW_REG_10___POR 0x0007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_10__SW_MTU_CW_REG_10___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_10__SW_MTU_CW_REG_10___S 0 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_10___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_10___S 0 + +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_11 (0x00AAA0BC) +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_11___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_11___POR 0x00000007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_11__SW_MTU_CW_REG_11___POR 0x0007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_11__SW_MTU_CW_REG_11___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_11__SW_MTU_CW_REG_11___S 0 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_11___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_11___S 0 + +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_12 (0x00AAA0C0) +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_12___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_12___POR 0x00000007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_12__SW_MTU_CW_REG_12___POR 0x0007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_12__SW_MTU_CW_REG_12___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_12__SW_MTU_CW_REG_12___S 0 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_12___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_12___S 0 + +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_13 (0x00AAA0C4) +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_13___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_13___POR 0x00000007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_13__SW_MTU_CW_REG_13___POR 0x0007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_13__SW_MTU_CW_REG_13___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_13__SW_MTU_CW_REG_13___S 0 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_13___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_13___S 0 + +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_14 (0x00AAA0C8) +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_14___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_14___POR 0x00000007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_14__SW_MTU_CW_REG_14___POR 0x0007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_14__SW_MTU_CW_REG_14___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_14__SW_MTU_CW_REG_14___S 0 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_14___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_14___S 0 + +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_15 (0x00AAA0CC) +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_15___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_15___POR 0x00000007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_15__SW_MTU_CW_REG_15___POR 0x0007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_15__SW_MTU_CW_REG_15___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_15__SW_MTU_CW_REG_15___S 0 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_15___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_15___S 0 + +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_16 (0x00AAA0D0) +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_16___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_16___POR 0x00000007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_16__SW_MTU_CW_REG_16___POR 0x0007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_16__SW_MTU_CW_REG_16___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_16__SW_MTU_CW_REG_16___S 0 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_16___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_16___S 0 + +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_17 (0x00AAA0D4) +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_17___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_17___POR 0x00000007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_17__SW_MTU_CW_REG_17___POR 0x0007 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_17__SW_MTU_CW_REG_17___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_17__SW_MTU_CW_REG_17___S 0 +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_17___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CW_REG_CONTROL_FOR_BACKOFF_17___S 0 + +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_0 (0x00AAA0E0) +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_0___POR 0x03FF000F +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_0__SW_CW_MAX_0___POR 0x03FF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_0__SW_CW_MIN_0___POR 0x000F +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_0__SW_CW_MAX_0___M 0xFFFF0000 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_0__SW_CW_MAX_0___S 16 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_0__SW_CW_MIN_0___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_0__SW_CW_MIN_0___S 0 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_0___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_0___S 0 + +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_1 (0x00AAA0E4) +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_1___POR 0x03FF000F +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_1__SW_CW_MAX_1___POR 0x03FF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_1__SW_CW_MIN_1___POR 0x000F +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_1__SW_CW_MAX_1___M 0xFFFF0000 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_1__SW_CW_MAX_1___S 16 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_1__SW_CW_MIN_1___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_1__SW_CW_MIN_1___S 0 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_1___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_1___S 0 + +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_2 (0x00AAA0E8) +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_2___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_2___POR 0x00070003 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_2__SW_CW_MAX_2___POR 0x0007 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_2__SW_CW_MIN_2___POR 0x0003 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_2__SW_CW_MAX_2___M 0xFFFF0000 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_2__SW_CW_MAX_2___S 16 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_2__SW_CW_MIN_2___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_2__SW_CW_MIN_2___S 0 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_2___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_2___S 0 + +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_3 (0x00AAA0EC) +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_3___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_3___POR 0x00070003 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_3__SW_CW_MAX_3___POR 0x0007 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_3__SW_CW_MIN_3___POR 0x0003 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_3__SW_CW_MAX_3___M 0xFFFF0000 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_3__SW_CW_MAX_3___S 16 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_3__SW_CW_MIN_3___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_3__SW_CW_MIN_3___S 0 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_3___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_3___S 0 + +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_4 (0x00AAA0F0) +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_4___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_4___POR 0x00070003 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_4__SW_CW_MAX_4___POR 0x0007 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_4__SW_CW_MIN_4___POR 0x0003 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_4__SW_CW_MAX_4___M 0xFFFF0000 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_4__SW_CW_MAX_4___S 16 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_4__SW_CW_MIN_4___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_4__SW_CW_MIN_4___S 0 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_4___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_4___S 0 + +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_5 (0x00AAA0F4) +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_5___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_5___POR 0x000F0007 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_5__SW_CW_MAX_5___POR 0x000F +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_5__SW_CW_MIN_5___POR 0x0007 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_5__SW_CW_MAX_5___M 0xFFFF0000 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_5__SW_CW_MAX_5___S 16 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_5__SW_CW_MIN_5___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_5__SW_CW_MIN_5___S 0 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_5___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_5___S 0 + +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_6 (0x00AAA0F8) +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_6___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_6___POR 0x03FF000F +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_6__SW_CW_MAX_6___POR 0x03FF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_6__SW_CW_MIN_6___POR 0x000F +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_6__SW_CW_MAX_6___M 0xFFFF0000 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_6__SW_CW_MAX_6___S 16 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_6__SW_CW_MIN_6___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_6__SW_CW_MIN_6___S 0 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_6___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_6___S 0 + +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_7 (0x00AAA0FC) +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_7___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_7___POR 0x03FF000F +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_7__SW_CW_MAX_7___POR 0x03FF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_7__SW_CW_MIN_7___POR 0x000F +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_7__SW_CW_MAX_7___M 0xFFFF0000 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_7__SW_CW_MAX_7___S 16 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_7__SW_CW_MIN_7___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_7__SW_CW_MIN_7___S 0 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_7___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_7___S 0 + +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_8 (0x00AAA100) +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_8___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_8___POR 0x03FF000F +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_8__SW_CW_MAX_8___POR 0x03FF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_8__SW_CW_MIN_8___POR 0x000F +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_8__SW_CW_MAX_8___M 0xFFFF0000 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_8__SW_CW_MAX_8___S 16 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_8__SW_CW_MIN_8___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_8__SW_CW_MIN_8___S 0 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_8___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_8___S 0 + +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_9 (0x00AAA104) +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_9___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_9___POR 0x03FF000F +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_9__SW_CW_MAX_9___POR 0x03FF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_9__SW_CW_MIN_9___POR 0x000F +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_9__SW_CW_MAX_9___M 0xFFFF0000 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_9__SW_CW_MAX_9___S 16 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_9__SW_CW_MIN_9___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_9__SW_CW_MIN_9___S 0 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_9___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_9___S 0 + +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_10 (0x00AAA108) +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_10___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_10___POR 0x03FF000F +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_10__SW_CW_MAX_10___POR 0x03FF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_10__SW_CW_MIN_10___POR 0x000F +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_10__SW_CW_MAX_10___M 0xFFFF0000 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_10__SW_CW_MAX_10___S 16 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_10__SW_CW_MIN_10___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_10__SW_CW_MIN_10___S 0 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_10___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_10___S 0 + +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_11 (0x00AAA10C) +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_11___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_11___POR 0x03FF000F +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_11__SW_CW_MAX_11___POR 0x03FF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_11__SW_CW_MIN_11___POR 0x000F +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_11__SW_CW_MAX_11___M 0xFFFF0000 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_11__SW_CW_MAX_11___S 16 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_11__SW_CW_MIN_11___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_11__SW_CW_MIN_11___S 0 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_11___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_11___S 0 + +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_12 (0x00AAA110) +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_12___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_12___POR 0x03FF000F +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_12__SW_CW_MAX_12___POR 0x03FF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_12__SW_CW_MIN_12___POR 0x000F +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_12__SW_CW_MAX_12___M 0xFFFF0000 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_12__SW_CW_MAX_12___S 16 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_12__SW_CW_MIN_12___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_12__SW_CW_MIN_12___S 0 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_12___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_12___S 0 + +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_13 (0x00AAA114) +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_13___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_13___POR 0x03FF000F +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_13__SW_CW_MAX_13___POR 0x03FF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_13__SW_CW_MIN_13___POR 0x000F +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_13__SW_CW_MAX_13___M 0xFFFF0000 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_13__SW_CW_MAX_13___S 16 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_13__SW_CW_MIN_13___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_13__SW_CW_MIN_13___S 0 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_13___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_13___S 0 + +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_14 (0x00AAA118) +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_14___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_14___POR 0x03FF000F +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_14__SW_CW_MAX_14___POR 0x03FF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_14__SW_CW_MIN_14___POR 0x000F +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_14__SW_CW_MAX_14___M 0xFFFF0000 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_14__SW_CW_MAX_14___S 16 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_14__SW_CW_MIN_14___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_14__SW_CW_MIN_14___S 0 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_14___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_14___S 0 + +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_15 (0x00AAA11C) +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_15___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_15___POR 0x03FF000F +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_15__SW_CW_MAX_15___POR 0x03FF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_15__SW_CW_MIN_15___POR 0x000F +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_15__SW_CW_MAX_15___M 0xFFFF0000 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_15__SW_CW_MAX_15___S 16 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_15__SW_CW_MIN_15___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_15__SW_CW_MIN_15___S 0 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_15___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_15___S 0 + +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_16 (0x00AAA120) +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_16___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_16___POR 0x03FF000F +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_16__SW_CW_MAX_16___POR 0x03FF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_16__SW_CW_MIN_16___POR 0x000F +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_16__SW_CW_MAX_16___M 0xFFFF0000 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_16__SW_CW_MAX_16___S 16 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_16__SW_CW_MIN_16___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_16__SW_CW_MIN_16___S 0 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_16___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_16___S 0 + +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_17 (0x00AAA124) +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_17___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_17___POR 0x03FF000F +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_17__SW_CW_MAX_17___POR 0x03FF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_17__SW_CW_MIN_17___POR 0x000F +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_17__SW_CW_MAX_17___M 0xFFFF0000 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_17__SW_CW_MAX_17___S 16 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_17__SW_CW_MIN_17___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_17__SW_CW_MIN_17___S 0 +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_17___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SW_CW_MIN_CW_MAX_17___S 0 + +#define WMAC0_HWSCH_R0_CW_ACTION_CTRL (0x00AAA130) +#define WMAC0_HWSCH_R0_CW_ACTION_CTRL___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CW_ACTION_CTRL___POR 0x00010082 +#define WMAC0_HWSCH_R0_CW_ACTION_CTRL__CW_ACTION_CTRL___POR 0x0010082 +#define WMAC0_HWSCH_R0_CW_ACTION_CTRL__CW_ACTION_CTRL___M 0x0FFFFFFF +#define WMAC0_HWSCH_R0_CW_ACTION_CTRL__CW_ACTION_CTRL___S 0 +#define WMAC0_HWSCH_R0_CW_ACTION_CTRL___M 0x0FFFFFFF +#define WMAC0_HWSCH_R0_CW_ACTION_CTRL___S 0 + +#define WMAC0_HWSCH_R0_MTU_11AH_CTRL0 (0x00AAA134) +#define WMAC0_HWSCH_R0_MTU_11AH_CTRL0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_MTU_11AH_CTRL0___POR 0x0000000F +#define WMAC0_HWSCH_R0_MTU_11AH_CTRL0__NAV_CF_END_TOLERANCE___POR 0xF +#define WMAC0_HWSCH_R0_MTU_11AH_CTRL0__NAV_CF_END_TOLERANCE___M 0x0000000F +#define WMAC0_HWSCH_R0_MTU_11AH_CTRL0__NAV_CF_END_TOLERANCE___S 0 +#define WMAC0_HWSCH_R0_MTU_11AH_CTRL0___M 0x0000000F +#define WMAC0_HWSCH_R0_MTU_11AH_CTRL0___S 0 + +#define WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS (0x00AAA138) +#define WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS___POR 0x00000000 +#define WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS__QUATERNARY_CCA_TO___POR 0x0 +#define WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS__TERTIARY_CCA_TO___POR 0x0 +#define WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS__SECONDARY_CCA_TO___POR 0x0 +#define WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS__SIFS_TO___POR 0x0 +#define WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS__PIFS_TO___POR 0x0 +#define WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS__QUATERNARY_CCA_TO___M 0x00000010 +#define WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS__QUATERNARY_CCA_TO___S 4 +#define WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS__TERTIARY_CCA_TO___M 0x00000008 +#define WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS__TERTIARY_CCA_TO___S 3 +#define WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS__SECONDARY_CCA_TO___M 0x00000004 +#define WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS__SECONDARY_CCA_TO___S 2 +#define WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS__SIFS_TO___M 0x00000002 +#define WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS__SIFS_TO___S 1 +#define WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS__PIFS_TO___M 0x00000001 +#define WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS__PIFS_TO___S 0 +#define WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS___M 0x0000001F +#define WMAC0_HWSCH_R0_MTU_TIMEOUT_STATUS___S 0 + +#define WMAC0_HWSCH_R0_PRE_START_TX_LIMITS (0x00AAA13C) +#define WMAC0_HWSCH_R0_PRE_START_TX_LIMITS___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_PRE_START_TX_LIMITS___POR 0x0002BA04 +#define WMAC0_HWSCH_R0_PRE_START_TX_LIMITS__SW_MTU_PRE_START_TX_LIMIT_SIFS___POR 0x02BA +#define WMAC0_HWSCH_R0_PRE_START_TX_LIMITS__SW_MTU_PRE_START_TX_LIMIT_RBO___POR 0x04 +#define WMAC0_HWSCH_R0_PRE_START_TX_LIMITS__SW_MTU_PRE_START_TX_LIMIT_SIFS___M 0x007FFF00 +#define WMAC0_HWSCH_R0_PRE_START_TX_LIMITS__SW_MTU_PRE_START_TX_LIMIT_SIFS___S 8 +#define WMAC0_HWSCH_R0_PRE_START_TX_LIMITS__SW_MTU_PRE_START_TX_LIMIT_RBO___M 0x000000FF +#define WMAC0_HWSCH_R0_PRE_START_TX_LIMITS__SW_MTU_PRE_START_TX_LIMIT_RBO___S 0 +#define WMAC0_HWSCH_R0_PRE_START_TX_LIMITS___M 0x007FFFFF +#define WMAC0_HWSCH_R0_PRE_START_TX_LIMITS___S 0 + +#define WMAC0_HWSCH_R0_BURST_EXTENSION_CTRL (0x00AAA140) +#define WMAC0_HWSCH_R0_BURST_EXTENSION_CTRL___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_BURST_EXTENSION_CTRL___POR 0x000105BB +#define WMAC0_HWSCH_R0_BURST_EXTENSION_CTRL__SW_MTU_DISABLE_OFDMA_TRIG_RESP_BEXT___POR 0x1 +#define WMAC0_HWSCH_R0_BURST_EXTENSION_CTRL__SW_MTU_SIFS_BEXT_LIMIT___POR 0x02DD +#define WMAC0_HWSCH_R0_BURST_EXTENSION_CTRL__SW_MTU_SIFS_BEXT_ENABLE___POR 0x1 +#define WMAC0_HWSCH_R0_BURST_EXTENSION_CTRL__SW_MTU_DISABLE_OFDMA_TRIG_RESP_BEXT___M 0x00010000 +#define WMAC0_HWSCH_R0_BURST_EXTENSION_CTRL__SW_MTU_DISABLE_OFDMA_TRIG_RESP_BEXT___S 16 +#define WMAC0_HWSCH_R0_BURST_EXTENSION_CTRL__SW_MTU_SIFS_BEXT_LIMIT___M 0x0000FFFE +#define WMAC0_HWSCH_R0_BURST_EXTENSION_CTRL__SW_MTU_SIFS_BEXT_LIMIT___S 1 +#define WMAC0_HWSCH_R0_BURST_EXTENSION_CTRL__SW_MTU_SIFS_BEXT_ENABLE___M 0x00000001 +#define WMAC0_HWSCH_R0_BURST_EXTENSION_CTRL__SW_MTU_SIFS_BEXT_ENABLE___S 0 +#define WMAC0_HWSCH_R0_BURST_EXTENSION_CTRL___M 0x0001FFFF +#define WMAC0_HWSCH_R0_BURST_EXTENSION_CTRL___S 0 + +#define WMAC0_HWSCH_R0_CCA_COUNTER0 (0x00AAA144) +#define WMAC0_HWSCH_R0_CCA_COUNTER0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_COUNTER0___POR 0x00000000 +#define WMAC0_HWSCH_R0_CCA_COUNTER0__CCA_COUNTER0___POR 0x00000000 +#define WMAC0_HWSCH_R0_CCA_COUNTER0__CCA_COUNTER0___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_COUNTER0__CCA_COUNTER0___S 0 +#define WMAC0_HWSCH_R0_CCA_COUNTER0___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_COUNTER0___S 0 + +#define WMAC0_HWSCH_R0_CCA_COUNTER1 (0x00AAA148) +#define WMAC0_HWSCH_R0_CCA_COUNTER1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_COUNTER1___POR 0x00000000 +#define WMAC0_HWSCH_R0_CCA_COUNTER1__CCA_COUNTER1___POR 0x00000000 +#define WMAC0_HWSCH_R0_CCA_COUNTER1__CCA_COUNTER1___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_COUNTER1__CCA_COUNTER1___S 0 +#define WMAC0_HWSCH_R0_CCA_COUNTER1___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_COUNTER1___S 0 + +#define WMAC0_HWSCH_R0_CCA_COUNTER2 (0x00AAA14C) +#define WMAC0_HWSCH_R0_CCA_COUNTER2___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_COUNTER2___POR 0x00000000 +#define WMAC0_HWSCH_R0_CCA_COUNTER2__CCA_COUNTER2___POR 0x00000000 +#define WMAC0_HWSCH_R0_CCA_COUNTER2__CCA_COUNTER2___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_COUNTER2__CCA_COUNTER2___S 0 +#define WMAC0_HWSCH_R0_CCA_COUNTER2___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_COUNTER2___S 0 + +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_1 (0x00AAA150) +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_1___POR 0x00700000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__CCA_COUNT2_IDLE_BUSY_SEL___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__CCA_COUNT1_IDLE_BUSY_SEL___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__CCA_COUNT0_IDLE_BUSY_SEL___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__SW_MTU_BKOF_GOTO_IDLE___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__SW_MTU_CCA_FLAG___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__COEX_TM_WL_WAIT_BEACON_CFG___POR 0x3 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__IBSS_TBTT_SEL___POR 0x1 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__SW_MTU_EIFS_CCA_SEL___POR 0x00000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__CCA_COUNT2_IDLE_BUSY_SEL___M 0x08000000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__CCA_COUNT2_IDLE_BUSY_SEL___S 27 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__CCA_COUNT1_IDLE_BUSY_SEL___M 0x04000000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__CCA_COUNT1_IDLE_BUSY_SEL___S 26 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__CCA_COUNT0_IDLE_BUSY_SEL___M 0x02000000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__CCA_COUNT0_IDLE_BUSY_SEL___S 25 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__SW_MTU_BKOF_GOTO_IDLE___M 0x01000000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__SW_MTU_BKOF_GOTO_IDLE___S 24 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__SW_MTU_CCA_FLAG___M 0x00800000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__SW_MTU_CCA_FLAG___S 23 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__COEX_TM_WL_WAIT_BEACON_CFG___M 0x00600000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__COEX_TM_WL_WAIT_BEACON_CFG___S 21 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__IBSS_TBTT_SEL___M 0x00100000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__IBSS_TBTT_SEL___S 20 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__SW_MTU_EIFS_CCA_SEL___M 0x0003FFFF +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_1__SW_MTU_EIFS_CCA_SEL___S 0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_1___M 0x0FF3FFFF +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_1___S 0 + +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_2 (0x00AAA154) +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_2___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_2___POR 0x00000219 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_CCA_GATE_DURING_PHY_ABORT___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_MAC_NAP_CLR___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__TX_BCN_TBTT_SEL___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_COEX_NAP_GATING_DISABLE___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_COEX_NAP_END_CFG___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_RXFRAME_CCA_DELAY_MASK_LIMIT___POR 0x000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_RXPCU_PHY_OFF_GATING_DISABLE___POR 0x1 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_PRIMARY_CCA_LIMIT___POR 0x019 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_CCA_GATE_DURING_PHY_ABORT___M 0x40000000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_CCA_GATE_DURING_PHY_ABORT___S 30 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_MAC_NAP_CLR___M 0x20000000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_MAC_NAP_CLR___S 29 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__TX_BCN_TBTT_SEL___M 0x0F000000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__TX_BCN_TBTT_SEL___S 24 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_COEX_NAP_GATING_DISABLE___M 0x00800000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_COEX_NAP_GATING_DISABLE___S 23 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_COEX_NAP_END_CFG___M 0x00400000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_COEX_NAP_END_CFG___S 22 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_RXFRAME_CCA_DELAY_MASK_LIMIT___M 0x003FFC00 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_RXFRAME_CCA_DELAY_MASK_LIMIT___S 10 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_RXPCU_PHY_OFF_GATING_DISABLE___M 0x00000200 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_RXPCU_PHY_OFF_GATING_DISABLE___S 9 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_PRIMARY_CCA_LIMIT___M 0x000001FF +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_2__SW_MTU_PRIMARY_CCA_LIMIT___S 0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_2___M 0x6FFFFFFF +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_2___S 0 + +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_3 (0x00AAA158) +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_3___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_3___POR 0xBBBBBBBB +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL7___POR 0xB +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL6___POR 0xB +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL5___POR 0xB +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL4___POR 0xB +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL3___POR 0xB +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL2___POR 0xB +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL1___POR 0xB +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL0___POR 0xB +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL7___M 0xF0000000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL7___S 28 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL6___M 0x0F000000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL6___S 24 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL5___M 0x00F00000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL5___S 20 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL4___M 0x000F0000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL4___S 16 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL3___M 0x0000F000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL3___S 12 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL2___M 0x00000F00 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL2___S 8 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL1___M 0x000000F0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL1___S 4 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL0___M 0x0000000F +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_3__SW_MTU_RAW_CCA_SEL0___S 0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_3___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_3___S 0 + +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_4 (0x00AAA15C) +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_4___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_4___POR 0xBBBBBBBB +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL15___POR 0xB +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL14___POR 0xB +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL13___POR 0xB +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL12___POR 0xB +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL11___POR 0xB +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL10___POR 0xB +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL9___POR 0xB +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL8___POR 0xB +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL15___M 0xF0000000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL15___S 28 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL14___M 0x0F000000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL14___S 24 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL13___M 0x00F00000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL13___S 20 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL12___M 0x000F0000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL12___S 16 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL11___M 0x0000F000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL11___S 12 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL10___M 0x00000F00 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL10___S 8 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL9___M 0x000000F0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL9___S 4 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL8___M 0x0000000F +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_4__SW_MTU_RAW_CCA_SEL8___S 0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_4___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_4___S 0 + +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_5 (0x00AAA160) +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_5___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_5___POR 0x00000000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL7___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL6___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL5___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL4___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL3___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL2___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL1___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL0___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL7___M 0xF0000000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL7___S 28 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL6___M 0x0F000000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL6___S 24 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL5___M 0x00F00000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL5___S 20 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL4___M 0x000F0000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL4___S 16 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL3___M 0x0000F000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL3___S 12 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL2___M 0x00000F00 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL2___S 8 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL1___M 0x000000F0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL1___S 4 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL0___M 0x0000000F +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_5__SW_MTU_FINAL_CCA_SEL0___S 0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_5___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_5___S 0 + +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_6 (0x00AAA164) +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_6___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_6___POR 0x00000000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL15___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL14___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL13___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL12___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL11___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL10___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL9___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL8___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL15___M 0xF0000000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL15___S 28 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL14___M 0x0F000000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL14___S 24 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL13___M 0x00F00000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL13___S 20 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL12___M 0x000F0000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL12___S 16 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL11___M 0x0000F000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL11___S 12 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL10___M 0x00000F00 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL10___S 8 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL9___M 0x000000F0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL9___S 4 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL8___M 0x0000000F +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_6__SW_MTU_FINAL_CCA_SEL8___S 0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_6___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_6___S 0 + +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_7 (0x00AAA168) +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_7___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_7___POR 0x000000BB +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_7__SW_MTU_RAW_CCA_SEL17___POR 0xB +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_7__SW_MTU_RAW_CCA_SEL16___POR 0xB +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_7__SW_MTU_RAW_CCA_SEL17___M 0x000000F0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_7__SW_MTU_RAW_CCA_SEL17___S 4 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_7__SW_MTU_RAW_CCA_SEL16___M 0x0000000F +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_7__SW_MTU_RAW_CCA_SEL16___S 0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_7___M 0x000000FF +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_7___S 0 + +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_8 (0x00AAA16C) +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_8___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_8___POR 0x00000000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_8__SW_MTU_FINAL_CCA_SEL17___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_8__SW_MTU_FINAL_CCA_SEL16___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_8__SW_MTU_FINAL_CCA_SEL17___M 0x000000F0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_8__SW_MTU_FINAL_CCA_SEL17___S 4 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_8__SW_MTU_FINAL_CCA_SEL16___M 0x0000000F +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_8__SW_MTU_FINAL_CCA_SEL16___S 0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_8___M 0x000000FF +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_8___S 0 + +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_9 (0x00AAA170) +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_9___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_9___POR 0x00000000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_9__CRYPTO_RX_IDLE_SENSE_LIMIT___POR 0x000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_9__CRYPTO_RX_IDLE_SENSE_ENABLE___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_9__QUALIFY_RESP_EXPECTED_FOR_BLOCK___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_9__QUALIFY_RX_BUSY_FOR_BLOCK___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_9__RX_END_DELAY_BLOCK_WIN___POR 0x0000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_9__CRYPTO_RX_IDLE_SENSE_LIMIT___M 0x7FF80000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_9__CRYPTO_RX_IDLE_SENSE_LIMIT___S 19 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_9__CRYPTO_RX_IDLE_SENSE_ENABLE___M 0x00040000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_9__CRYPTO_RX_IDLE_SENSE_ENABLE___S 18 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_9__QUALIFY_RESP_EXPECTED_FOR_BLOCK___M 0x00020000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_9__QUALIFY_RESP_EXPECTED_FOR_BLOCK___S 17 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_9__QUALIFY_RX_BUSY_FOR_BLOCK___M 0x00010000 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_9__QUALIFY_RX_BUSY_FOR_BLOCK___S 16 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_9__RX_END_DELAY_BLOCK_WIN___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_9__RX_END_DELAY_BLOCK_WIN___S 0 +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_9___M 0x7FFFFFFF +#define WMAC0_HWSCH_R0_CCA_CONTROL_REG_9___S 0 + +#define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL (0x00AAA174) +#define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL___POR 0x0877500F +#define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__IGNORE_NAV_CNT_BACKOFF___POR 0x0 +#define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__FES_FAIL_AUTO_FLUSH_LATE_MPDU_INFO___POR 0x1 +#define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__SW_MTU_RTS_NAV_11B_TO_LIMIT___POR 0x0EE +#define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__ENABLE_CCA_SENSING_IN_PIFS_BURST___POR 0x1 +#define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__SW_MTU_NAV_BASED_ON_RTS_VALID___POR 0x1 +#define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__SW_MTU_RTS_NAV_TO_LIMIT___POR 0x00F +#define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__IGNORE_NAV_CNT_BACKOFF___M 0x30000000 +#define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__IGNORE_NAV_CNT_BACKOFF___S 28 +#define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__FES_FAIL_AUTO_FLUSH_LATE_MPDU_INFO___M 0x08000000 +#define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__FES_FAIL_AUTO_FLUSH_LATE_MPDU_INFO___S 27 +#define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__SW_MTU_RTS_NAV_11B_TO_LIMIT___M 0x07FF8000 +#define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__SW_MTU_RTS_NAV_11B_TO_LIMIT___S 15 +#define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__ENABLE_CCA_SENSING_IN_PIFS_BURST___M 0x00004000 +#define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__ENABLE_CCA_SENSING_IN_PIFS_BURST___S 14 +#define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__SW_MTU_NAV_BASED_ON_RTS_VALID___M 0x00001000 +#define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__SW_MTU_NAV_BASED_ON_RTS_VALID___S 12 +#define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__SW_MTU_RTS_NAV_TO_LIMIT___M 0x00000FFF +#define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL__SW_MTU_RTS_NAV_TO_LIMIT___S 0 +#define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL___M 0x3FFFDFFF +#define WMAC0_HWSCH_R0_MTU_GLOBAL_CONTROL___S 0 + +#define WMAC0_HWSCH_R0_PREBKOFF_LIMITS (0x00AAA178) +#define WMAC0_HWSCH_R0_PREBKOFF_LIMITS___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_PREBKOFF_LIMITS___POR 0x01440111 +#define WMAC0_HWSCH_R0_PREBKOFF_LIMITS__IGNORE_SIFS_PIFS_WIDTH_LIMIT_RX___POR 0x0 +#define WMAC0_HWSCH_R0_PREBKOFF_LIMITS__SW_MTU_TXP_PIFS_WIDTH_LIMIT___POR 0x05 +#define WMAC0_HWSCH_R0_PREBKOFF_LIMITS__SW_MTU_TXP_SIFS_WIDTH_LIMIT___POR 0x04 +#define WMAC0_HWSCH_R0_PREBKOFF_LIMITS__SW_MTU_EARLY_SW_INT_LIMIT_CLKS___POR 0x01 +#define WMAC0_HWSCH_R0_PREBKOFF_LIMITS__SW_MTU_EARLY_SW_INT_LIMIT_US___POR 0x11 +#define WMAC0_HWSCH_R0_PREBKOFF_LIMITS__IGNORE_SIFS_PIFS_WIDTH_LIMIT_RX___M 0x10000000 +#define WMAC0_HWSCH_R0_PREBKOFF_LIMITS__IGNORE_SIFS_PIFS_WIDTH_LIMIT_RX___S 28 +#define WMAC0_HWSCH_R0_PREBKOFF_LIMITS__SW_MTU_TXP_PIFS_WIDTH_LIMIT___M 0x0FC00000 +#define WMAC0_HWSCH_R0_PREBKOFF_LIMITS__SW_MTU_TXP_PIFS_WIDTH_LIMIT___S 22 +#define WMAC0_HWSCH_R0_PREBKOFF_LIMITS__SW_MTU_TXP_SIFS_WIDTH_LIMIT___M 0x003F0000 +#define WMAC0_HWSCH_R0_PREBKOFF_LIMITS__SW_MTU_TXP_SIFS_WIDTH_LIMIT___S 16 +#define WMAC0_HWSCH_R0_PREBKOFF_LIMITS__SW_MTU_EARLY_SW_INT_LIMIT_CLKS___M 0x0000FF00 +#define WMAC0_HWSCH_R0_PREBKOFF_LIMITS__SW_MTU_EARLY_SW_INT_LIMIT_CLKS___S 8 +#define WMAC0_HWSCH_R0_PREBKOFF_LIMITS__SW_MTU_EARLY_SW_INT_LIMIT_US___M 0x000000FF +#define WMAC0_HWSCH_R0_PREBKOFF_LIMITS__SW_MTU_EARLY_SW_INT_LIMIT_US___S 0 +#define WMAC0_HWSCH_R0_PREBKOFF_LIMITS___M 0x1FFFFFFF +#define WMAC0_HWSCH_R0_PREBKOFF_LIMITS___S 0 + +#define WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS (0x00AAA17C) +#define WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS___POR 0xEC000000 +#define WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__DELAY_UPLOAD_FES_STATUS_TLV_UNTIL_START_TX___POR 0x1 +#define WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__FES_FAIL_AUTO_FLUSH_INCLUDE_UNDERRUN___POR 0x1 +#define WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__FES_FAIL_AUTO_FLUSH_ENABLE___POR 0x1 +#define WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__SVD_RDY_TIMEOUT_CHECK_ENABLE_SIFS___POR 0x0 +#define WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__SVD_RDY_TIMEOUT_CHECK_ENABLE___POR 0x1 +#define WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__SVD_RDY_TIMEOUT_SLOT_LIMIT___POR 0x4 +#define WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__SW_MTU_WARM_TX_LIMIT_US___POR 0x0 +#define WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__SW_MTU_HW_BACKOFF_VALID___POR 0x00000 +#define WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__DELAY_UPLOAD_FES_STATUS_TLV_UNTIL_START_TX___M 0x80000000 +#define WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__DELAY_UPLOAD_FES_STATUS_TLV_UNTIL_START_TX___S 31 +#define WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__FES_FAIL_AUTO_FLUSH_INCLUDE_UNDERRUN___M 0x40000000 +#define WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__FES_FAIL_AUTO_FLUSH_INCLUDE_UNDERRUN___S 30 +#define WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__FES_FAIL_AUTO_FLUSH_ENABLE___M 0x20000000 +#define WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__FES_FAIL_AUTO_FLUSH_ENABLE___S 29 +#define WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__SVD_RDY_TIMEOUT_CHECK_ENABLE_SIFS___M 0x10000000 +#define WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__SVD_RDY_TIMEOUT_CHECK_ENABLE_SIFS___S 28 +#define WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__SVD_RDY_TIMEOUT_CHECK_ENABLE___M 0x08000000 +#define WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__SVD_RDY_TIMEOUT_CHECK_ENABLE___S 27 +#define WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__SVD_RDY_TIMEOUT_SLOT_LIMIT___M 0x07000000 +#define WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__SVD_RDY_TIMEOUT_SLOT_LIMIT___S 24 +#define WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__SW_MTU_WARM_TX_LIMIT_US___M 0x00F00000 +#define WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__SW_MTU_WARM_TX_LIMIT_US___S 20 +#define WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__SW_MTU_HW_BACKOFF_VALID___M 0x0003FFFF +#define WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS__SW_MTU_HW_BACKOFF_VALID___S 0 +#define WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS___M 0xFFF3FFFF +#define WMAC0_HWSCH_R0_MTU_FOR_HMAC_CONTROLS___S 0 + +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_0 (0x00AAA180) +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_0___POR 0x00000000 +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_0__SW_LONG_SHORT_XMIT_LIMIT_BKOF_3_TO_0___POR 0x00000000 +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_0__SW_LONG_SHORT_XMIT_LIMIT_BKOF_3_TO_0___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_0__SW_LONG_SHORT_XMIT_LIMIT_BKOF_3_TO_0___S 0 +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_0___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_0___S 0 + +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_1 (0x00AAA184) +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_1___POR 0x00000000 +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_1__SW_LONG_SHORT_XMIT_LIMIT_BKOF_7_TO_4___POR 0x00000000 +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_1__SW_LONG_SHORT_XMIT_LIMIT_BKOF_7_TO_4___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_1__SW_LONG_SHORT_XMIT_LIMIT_BKOF_7_TO_4___S 0 +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_1___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_1___S 0 + +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_2 (0x00AAA188) +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_2___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_2___POR 0x00000000 +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_2__SW_LONG_SHORT_XMIT_LIMIT_BKOF_11_TO_8___POR 0x00000000 +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_2__SW_LONG_SHORT_XMIT_LIMIT_BKOF_11_TO_8___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_2__SW_LONG_SHORT_XMIT_LIMIT_BKOF_11_TO_8___S 0 +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_2___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_2___S 0 + +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_3 (0x00AAA18C) +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_3___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_3___POR 0x00000000 +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_3__SW_LONG_SHORT_XMIT_LIMIT_BKOF_15_TO_12___POR 0x00000000 +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_3__SW_LONG_SHORT_XMIT_LIMIT_BKOF_15_TO_12___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_3__SW_LONG_SHORT_XMIT_LIMIT_BKOF_15_TO_12___S 0 +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_3___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_3___S 0 + +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_4 (0x00AAA190) +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_4___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_4___POR 0x00000000 +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_4__SW_LONG_SHORT_XMIT_LIMIT_BKOF_17_TO_16___POR 0x0000 +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_4__SW_LONG_SHORT_XMIT_LIMIT_BKOF_17_TO_16___M 0x0000FFFF +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_4__SW_LONG_SHORT_XMIT_LIMIT_BKOF_17_TO_16___S 0 +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_4___M 0x0000FFFF +#define WMAC0_HWSCH_R0_LONG_SHORT_XMIT_LIMIT_4___S 0 + +#define WMAC0_HWSCH_R0_SW_MTU_SIFS_LIMIT_FORINNAV (0x00AAA194) +#define WMAC0_HWSCH_R0_SW_MTU_SIFS_LIMIT_FORINNAV___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SW_MTU_SIFS_LIMIT_FORINNAV___POR 0x00000A16 +#define WMAC0_HWSCH_R0_SW_MTU_SIFS_LIMIT_FORINNAV__SW_MTU_SIFS_LIMIT_FORINNAV___POR 0x0A16 +#define WMAC0_HWSCH_R0_SW_MTU_SIFS_LIMIT_FORINNAV__SW_MTU_SIFS_LIMIT_FORINNAV___M 0x00007FFF +#define WMAC0_HWSCH_R0_SW_MTU_SIFS_LIMIT_FORINNAV__SW_MTU_SIFS_LIMIT_FORINNAV___S 0 +#define WMAC0_HWSCH_R0_SW_MTU_SIFS_LIMIT_FORINNAV___M 0x00007FFF +#define WMAC0_HWSCH_R0_SW_MTU_SIFS_LIMIT_FORINNAV___S 0 + +#define WMAC0_HWSCH_R0_PRIMARY_CCA_HISTOGRAM_LOW (0x00AAA198) +#define WMAC0_HWSCH_R0_PRIMARY_CCA_HISTOGRAM_LOW___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_PRIMARY_CCA_HISTOGRAM_LOW___POR 0xFFFFFFFF +#define WMAC0_HWSCH_R0_PRIMARY_CCA_HISTOGRAM_LOW__PRIMARY_CCA_HISTOGRAM31TO0___POR 0xFFFFFFFF +#define WMAC0_HWSCH_R0_PRIMARY_CCA_HISTOGRAM_LOW__PRIMARY_CCA_HISTOGRAM31TO0___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_PRIMARY_CCA_HISTOGRAM_LOW__PRIMARY_CCA_HISTOGRAM31TO0___S 0 +#define WMAC0_HWSCH_R0_PRIMARY_CCA_HISTOGRAM_LOW___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_PRIMARY_CCA_HISTOGRAM_LOW___S 0 + +#define WMAC0_HWSCH_R0_PRIMARY_CCA_HISTOGRAM_HIGH (0x00AAA19C) +#define WMAC0_HWSCH_R0_PRIMARY_CCA_HISTOGRAM_HIGH___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_PRIMARY_CCA_HISTOGRAM_HIGH___POR 0xFFFFFFFF +#define WMAC0_HWSCH_R0_PRIMARY_CCA_HISTOGRAM_HIGH__PRIMARY_CCA_HISTOGRAM63TO32___POR 0xFFFFFFFF +#define WMAC0_HWSCH_R0_PRIMARY_CCA_HISTOGRAM_HIGH__PRIMARY_CCA_HISTOGRAM63TO32___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_PRIMARY_CCA_HISTOGRAM_HIGH__PRIMARY_CCA_HISTOGRAM63TO32___S 0 +#define WMAC0_HWSCH_R0_PRIMARY_CCA_HISTOGRAM_HIGH___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_PRIMARY_CCA_HISTOGRAM_HIGH___S 0 + +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL0 (0x00AAA1A0) +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL0___POR 0x00000000 +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL0__ED_GI_CCA_EN_15_TO_0___POR 0x0000 +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL0__LIMIT___POR 0x0000 +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL0__ED_GI_CCA_EN_15_TO_0___M 0xFFFF0000 +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL0__ED_GI_CCA_EN_15_TO_0___S 16 +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL0__LIMIT___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL0__LIMIT___S 0 +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL0___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL0___S 0 + +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL1 (0x00AAA1A4) +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL1___POR 0x00000000 +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL1__ED_GI_CCA_EN_48_TO_16___POR 0x00000000 +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL1__ED_GI_CCA_EN_48_TO_16___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL1__ED_GI_CCA_EN_48_TO_16___S 0 +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL1___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_CONTROL1___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_0 (0x00AAA1A8) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_0___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_0__CMD_RING_BASE_DATA___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_0__CMD_RING_BASE_DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_0__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_0___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_0___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_1 (0x00AAA1AC) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_1___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_1__CMD_RING_BASE_DATA___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_1__CMD_RING_BASE_DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_1__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_1___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_1___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_2 (0x00AAA1B0) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_2___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_2___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_2__CMD_RING_BASE_DATA___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_2__CMD_RING_BASE_DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_2__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_2___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_2___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_3 (0x00AAA1B4) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_3___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_3___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_3__CMD_RING_BASE_DATA___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_3__CMD_RING_BASE_DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_3__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_3___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_3___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_4 (0x00AAA1B8) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_4___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_4___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_4__CMD_RING_BASE_DATA___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_4__CMD_RING_BASE_DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_4__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_4___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_4___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_5 (0x00AAA1BC) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_5___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_5___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_5__CMD_RING_BASE_DATA___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_5__CMD_RING_BASE_DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_5__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_5___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_5___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_6 (0x00AAA1C0) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_6___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_6___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_6__CMD_RING_BASE_DATA___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_6__CMD_RING_BASE_DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_6__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_6___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_6___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_7 (0x00AAA1C4) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_7___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_7___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_7__CMD_RING_BASE_DATA___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_7__CMD_RING_BASE_DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_7__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_7___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_7___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_8 (0x00AAA1C8) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_8___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_8___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_8__CMD_RING_BASE_DATA___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_8__CMD_RING_BASE_DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_8__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_8___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_8___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_9 (0x00AAA1CC) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_9___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_9___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_9__CMD_RING_BASE_DATA___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_9__CMD_RING_BASE_DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_9__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_9___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_9___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_10 (0x00AAA1D0) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_10___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_10___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_10__CMD_RING_BASE_DATA___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_10__CMD_RING_BASE_DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_10__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_10___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_10___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_11 (0x00AAA1D4) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_11___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_11___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_11__CMD_RING_BASE_DATA___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_11__CMD_RING_BASE_DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_11__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_11___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_11___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_12 (0x00AAA1D8) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_12___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_12___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_12__CMD_RING_BASE_DATA___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_12__CMD_RING_BASE_DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_12__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_12___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_12___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_13 (0x00AAA1DC) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_13___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_13___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_13__CMD_RING_BASE_DATA___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_13__CMD_RING_BASE_DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_13__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_13___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_13___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_14 (0x00AAA1E0) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_14___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_14___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_14__CMD_RING_BASE_DATA___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_14__CMD_RING_BASE_DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_14__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_14___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_14___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_15 (0x00AAA1E4) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_15___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_15___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_15__CMD_RING_BASE_DATA___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_15__CMD_RING_BASE_DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_15__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_15___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_15___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_16 (0x00AAA1E8) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_16___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_16___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_16__CMD_RING_BASE_DATA___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_16__CMD_RING_BASE_DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_16__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_16___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_16___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_17 (0x00AAA1EC) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_17___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_17___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_17__CMD_RING_BASE_DATA___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_17__CMD_RING_BASE_DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_17__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_17___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_LSB_IX_17___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_0 (0x00AAA1F8) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_0___POR 0x00000100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_0__CMD_RING_NUM_ENTRY_DATA___POR 0x0100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_0__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_0__CMD_RING_NUM_ENTRY_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_0___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_0___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_1 (0x00AAA1FC) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_1___POR 0x00000100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_1__CMD_RING_NUM_ENTRY_DATA___POR 0x0100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_1__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_1__CMD_RING_NUM_ENTRY_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_1___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_1___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_2 (0x00AAA200) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_2___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_2___POR 0x00000100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_2__CMD_RING_NUM_ENTRY_DATA___POR 0x0100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_2__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_2__CMD_RING_NUM_ENTRY_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_2___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_2___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_3 (0x00AAA204) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_3___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_3___POR 0x00000100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_3__CMD_RING_NUM_ENTRY_DATA___POR 0x0100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_3__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_3__CMD_RING_NUM_ENTRY_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_3___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_3___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_4 (0x00AAA208) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_4___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_4___POR 0x00000100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_4__CMD_RING_NUM_ENTRY_DATA___POR 0x0100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_4__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_4__CMD_RING_NUM_ENTRY_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_4___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_4___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_5 (0x00AAA20C) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_5___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_5___POR 0x00000100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_5__CMD_RING_NUM_ENTRY_DATA___POR 0x0100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_5__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_5__CMD_RING_NUM_ENTRY_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_5___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_5___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_6 (0x00AAA210) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_6___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_6___POR 0x00000100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_6__CMD_RING_NUM_ENTRY_DATA___POR 0x0100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_6__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_6__CMD_RING_NUM_ENTRY_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_6___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_6___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_7 (0x00AAA214) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_7___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_7___POR 0x00000100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_7__CMD_RING_NUM_ENTRY_DATA___POR 0x0100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_7__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_7__CMD_RING_NUM_ENTRY_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_7___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_7___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_8 (0x00AAA218) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_8___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_8___POR 0x00000100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_8__CMD_RING_NUM_ENTRY_DATA___POR 0x0100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_8__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_8__CMD_RING_NUM_ENTRY_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_8___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_8___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_9 (0x00AAA21C) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_9___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_9___POR 0x00000100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_9__CMD_RING_NUM_ENTRY_DATA___POR 0x0100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_9__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_9__CMD_RING_NUM_ENTRY_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_9___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_9___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_10 (0x00AAA220) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_10___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_10___POR 0x00000100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_10__CMD_RING_NUM_ENTRY_DATA___POR 0x0100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_10__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_10__CMD_RING_NUM_ENTRY_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_10___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_10___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_11 (0x00AAA224) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_11___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_11___POR 0x00000100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_11__CMD_RING_NUM_ENTRY_DATA___POR 0x0100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_11__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_11__CMD_RING_NUM_ENTRY_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_11___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_11___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_12 (0x00AAA228) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_12___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_12___POR 0x00000100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_12__CMD_RING_NUM_ENTRY_DATA___POR 0x0100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_12__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_12__CMD_RING_NUM_ENTRY_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_12___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_12___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_13 (0x00AAA22C) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_13___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_13___POR 0x00000100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_13__CMD_RING_NUM_ENTRY_DATA___POR 0x0100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_13__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_13__CMD_RING_NUM_ENTRY_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_13___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_13___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_14 (0x00AAA230) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_14___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_14___POR 0x00000100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_14__CMD_RING_NUM_ENTRY_DATA___POR 0x0100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_14__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_14__CMD_RING_NUM_ENTRY_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_14___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_14___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_15 (0x00AAA234) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_15___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_15___POR 0x00000100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_15__CMD_RING_NUM_ENTRY_DATA___POR 0x0100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_15__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_15__CMD_RING_NUM_ENTRY_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_15___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_15___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_16 (0x00AAA238) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_16___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_16___POR 0x00000100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_16__CMD_RING_NUM_ENTRY_DATA___POR 0x0100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_16__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_16__CMD_RING_NUM_ENTRY_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_16___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_16___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_17 (0x00AAA23C) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_17___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_17___POR 0x00000100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_17__CMD_RING_NUM_ENTRY_DATA___POR 0x0100 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_17__CMD_RING_NUM_ENTRY_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_17__CMD_RING_NUM_ENTRY_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_17___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_NUM_ENTRY_IX_17___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_0 (0x00AAA248) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_0___POR 0x000000F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_0__CMD_RING_THRESHOLD_DATA___POR 0x00F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_0__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_0__CMD_RING_THRESHOLD_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_0___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_0___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_1 (0x00AAA24C) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_1___POR 0x000000F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_1__CMD_RING_THRESHOLD_DATA___POR 0x00F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_1__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_1__CMD_RING_THRESHOLD_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_1___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_1___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_2 (0x00AAA250) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_2___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_2___POR 0x000000F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_2__CMD_RING_THRESHOLD_DATA___POR 0x00F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_2__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_2__CMD_RING_THRESHOLD_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_2___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_2___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_3 (0x00AAA254) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_3___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_3___POR 0x000000F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_3__CMD_RING_THRESHOLD_DATA___POR 0x00F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_3__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_3__CMD_RING_THRESHOLD_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_3___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_3___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_4 (0x00AAA258) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_4___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_4___POR 0x000000F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_4__CMD_RING_THRESHOLD_DATA___POR 0x00F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_4__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_4__CMD_RING_THRESHOLD_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_4___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_4___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_5 (0x00AAA25C) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_5___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_5___POR 0x000000F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_5__CMD_RING_THRESHOLD_DATA___POR 0x00F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_5__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_5__CMD_RING_THRESHOLD_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_5___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_5___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_6 (0x00AAA260) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_6___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_6___POR 0x000000F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_6__CMD_RING_THRESHOLD_DATA___POR 0x00F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_6__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_6__CMD_RING_THRESHOLD_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_6___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_6___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_7 (0x00AAA264) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_7___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_7___POR 0x000000F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_7__CMD_RING_THRESHOLD_DATA___POR 0x00F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_7__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_7__CMD_RING_THRESHOLD_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_7___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_7___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_8 (0x00AAA268) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_8___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_8___POR 0x000000F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_8__CMD_RING_THRESHOLD_DATA___POR 0x00F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_8__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_8__CMD_RING_THRESHOLD_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_8___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_8___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_9 (0x00AAA26C) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_9___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_9___POR 0x000000F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_9__CMD_RING_THRESHOLD_DATA___POR 0x00F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_9__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_9__CMD_RING_THRESHOLD_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_9___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_9___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_10 (0x00AAA270) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_10___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_10___POR 0x000000F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_10__CMD_RING_THRESHOLD_DATA___POR 0x00F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_10__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_10__CMD_RING_THRESHOLD_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_10___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_10___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_11 (0x00AAA274) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_11___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_11___POR 0x000000F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_11__CMD_RING_THRESHOLD_DATA___POR 0x00F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_11__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_11__CMD_RING_THRESHOLD_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_11___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_11___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_12 (0x00AAA278) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_12___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_12___POR 0x000000F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_12__CMD_RING_THRESHOLD_DATA___POR 0x00F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_12__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_12__CMD_RING_THRESHOLD_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_12___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_12___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_13 (0x00AAA27C) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_13___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_13___POR 0x000000F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_13__CMD_RING_THRESHOLD_DATA___POR 0x00F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_13__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_13__CMD_RING_THRESHOLD_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_13___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_13___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_14 (0x00AAA280) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_14___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_14___POR 0x000000F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_14__CMD_RING_THRESHOLD_DATA___POR 0x00F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_14__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_14__CMD_RING_THRESHOLD_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_14___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_14___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_15 (0x00AAA284) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_15___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_15___POR 0x000000F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_15__CMD_RING_THRESHOLD_DATA___POR 0x00F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_15__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_15__CMD_RING_THRESHOLD_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_15___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_15___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_16 (0x00AAA288) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_16___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_16___POR 0x000000F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_16__CMD_RING_THRESHOLD_DATA___POR 0x00F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_16__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_16__CMD_RING_THRESHOLD_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_16___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_16___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_17 (0x00AAA28C) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_17___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_17___POR 0x000000F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_17__CMD_RING_THRESHOLD_DATA___POR 0x00F0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_17__CMD_RING_THRESHOLD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_17__CMD_RING_THRESHOLD_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_17___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_THRESHOLD_IX_17___S 0 + +#define WMAC0_HWSCH_R0_FES_STATUS_RING_BASE_LSB (0x00AAA298) +#define WMAC0_HWSCH_R0_FES_STATUS_RING_BASE_LSB___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_FES_STATUS_RING_BASE_LSB___POR 0x00000000 +#define WMAC0_HWSCH_R0_FES_STATUS_RING_BASE_LSB__FES_STATUS_BASE_DATA___POR 0x00000000 +#define WMAC0_HWSCH_R0_FES_STATUS_RING_BASE_LSB__FES_STATUS_BASE_DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_FES_STATUS_RING_BASE_LSB__FES_STATUS_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_FES_STATUS_RING_BASE_LSB___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_FES_STATUS_RING_BASE_LSB___S 0 + +#define WMAC0_HWSCH_R0_FES_STATUS_RING_NUM_ENTRY (0x00AAA29C) +#define WMAC0_HWSCH_R0_FES_STATUS_RING_NUM_ENTRY___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_FES_STATUS_RING_NUM_ENTRY___POR 0x00000800 +#define WMAC0_HWSCH_R0_FES_STATUS_RING_NUM_ENTRY__FES_STATUS_NUM_ENTRY_DATA___POR 0x0800 +#define WMAC0_HWSCH_R0_FES_STATUS_RING_NUM_ENTRY__FES_STATUS_NUM_ENTRY_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R0_FES_STATUS_RING_NUM_ENTRY__FES_STATUS_NUM_ENTRY_DATA___S 0 +#define WMAC0_HWSCH_R0_FES_STATUS_RING_NUM_ENTRY___M 0x0000FFFF +#define WMAC0_HWSCH_R0_FES_STATUS_RING_NUM_ENTRY___S 0 + +#define WMAC0_HWSCH_R0_FES_STATUS_RING_THRESHOLDS (0x00AAA2A0) +#define WMAC0_HWSCH_R0_FES_STATUS_RING_THRESHOLDS___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_FES_STATUS_RING_THRESHOLDS___POR 0x00010200 +#define WMAC0_HWSCH_R0_FES_STATUS_RING_THRESHOLDS__PANIC_WATERMARK___POR 0x0001 +#define WMAC0_HWSCH_R0_FES_STATUS_RING_THRESHOLDS__LOW_WATERMARK___POR 0x0200 +#define WMAC0_HWSCH_R0_FES_STATUS_RING_THRESHOLDS__PANIC_WATERMARK___M 0xFFFF0000 +#define WMAC0_HWSCH_R0_FES_STATUS_RING_THRESHOLDS__PANIC_WATERMARK___S 16 +#define WMAC0_HWSCH_R0_FES_STATUS_RING_THRESHOLDS__LOW_WATERMARK___M 0x0000FFFF +#define WMAC0_HWSCH_R0_FES_STATUS_RING_THRESHOLDS__LOW_WATERMARK___S 0 +#define WMAC0_HWSCH_R0_FES_STATUS_RING_THRESHOLDS___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_FES_STATUS_RING_THRESHOLDS___S 0 + +#define WMAC0_HWSCH_R0_WATCHDOG_TIMER (0x00AAA2A4) +#define WMAC0_HWSCH_R0_WATCHDOG_TIMER___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_WATCHDOG_TIMER___POR 0x00010000 +#define WMAC0_HWSCH_R0_WATCHDOG_TIMER__WATCHDOG_TIMEOUT___POR 0x010000 +#define WMAC0_HWSCH_R0_WATCHDOG_TIMER__WATCHDOG_TIMEOUT___M 0x003FFFFF +#define WMAC0_HWSCH_R0_WATCHDOG_TIMER__WATCHDOG_TIMEOUT___S 0 +#define WMAC0_HWSCH_R0_WATCHDOG_TIMER___M 0x003FFFFF +#define WMAC0_HWSCH_R0_WATCHDOG_TIMER___S 0 + +#define WMAC0_HWSCH_R0_AXI_TIMEOUT (0x00AAA2A8) +#define WMAC0_HWSCH_R0_AXI_TIMEOUT___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_AXI_TIMEOUT___POR 0x000001F4 +#define WMAC0_HWSCH_R0_AXI_TIMEOUT__AXI_TIMEOUT___POR 0x01F4 +#define WMAC0_HWSCH_R0_AXI_TIMEOUT__AXI_TIMEOUT___M 0x0000FFFF +#define WMAC0_HWSCH_R0_AXI_TIMEOUT__AXI_TIMEOUT___S 0 +#define WMAC0_HWSCH_R0_AXI_TIMEOUT___M 0x0000FFFF +#define WMAC0_HWSCH_R0_AXI_TIMEOUT___S 0 + +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE (0x00AAA2AC) +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE___POR 0x00000000 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING17_PAUSED___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING16_PAUSED___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING15_PAUSED___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING14_PAUSED___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING13_PAUSED___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING12_PAUSED___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING11_PAUSED___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING10_PAUSED___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING9_PAUSED___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING8_PAUSED___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING7_PAUSED___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING6_PAUSED___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING5_PAUSED___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING4_PAUSED___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING3_PAUSED___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING2_PAUSED___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING1_PAUSED___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING0_PAUSED___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING17_PAUSED___M 0x00020000 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING17_PAUSED___S 17 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING16_PAUSED___M 0x00010000 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING16_PAUSED___S 16 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING15_PAUSED___M 0x00008000 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING15_PAUSED___S 15 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING14_PAUSED___M 0x00004000 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING14_PAUSED___S 14 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING13_PAUSED___M 0x00002000 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING13_PAUSED___S 13 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING12_PAUSED___M 0x00001000 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING12_PAUSED___S 12 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING11_PAUSED___M 0x00000800 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING11_PAUSED___S 11 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING10_PAUSED___M 0x00000400 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING10_PAUSED___S 10 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING9_PAUSED___M 0x00000200 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING9_PAUSED___S 9 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING8_PAUSED___M 0x00000100 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING8_PAUSED___S 8 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING7_PAUSED___M 0x00000080 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING7_PAUSED___S 7 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING6_PAUSED___M 0x00000040 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING6_PAUSED___S 6 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING5_PAUSED___M 0x00000020 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING5_PAUSED___S 5 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING4_PAUSED___M 0x00000010 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING4_PAUSED___S 4 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING3_PAUSED___M 0x00000008 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING3_PAUSED___S 3 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING2_PAUSED___M 0x00000004 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING2_PAUSED___S 2 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING1_PAUSED___M 0x00000002 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING1_PAUSED___S 1 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING0_PAUSED___M 0x00000001 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE__CMD_RING0_PAUSED___S 0 +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE___M 0x0003FFFF +#define WMAC0_HWSCH_R0_CMD_RING_PAUSE___S 0 + +#define WMAC0_HWSCH_R0_LOWPOWER_FEATURE_CTRL (0x00AAA2B0) +#define WMAC0_HWSCH_R0_LOWPOWER_FEATURE_CTRL___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_LOWPOWER_FEATURE_CTRL___POR 0x00000003 +#define WMAC0_HWSCH_R0_LOWPOWER_FEATURE_CTRL__LP_RING_BLOCK_CTRL___POR 0x1 +#define WMAC0_HWSCH_R0_LOWPOWER_FEATURE_CTRL__DISABLE_LP_IDLE_REQ___POR 0x1 +#define WMAC0_HWSCH_R0_LOWPOWER_FEATURE_CTRL__LP_RING_BLOCK_CTRL___M 0x00000002 +#define WMAC0_HWSCH_R0_LOWPOWER_FEATURE_CTRL__LP_RING_BLOCK_CTRL___S 1 +#define WMAC0_HWSCH_R0_LOWPOWER_FEATURE_CTRL__DISABLE_LP_IDLE_REQ___M 0x00000001 +#define WMAC0_HWSCH_R0_LOWPOWER_FEATURE_CTRL__DISABLE_LP_IDLE_REQ___S 0 +#define WMAC0_HWSCH_R0_LOWPOWER_FEATURE_CTRL___M 0x00000003 +#define WMAC0_HWSCH_R0_LOWPOWER_FEATURE_CTRL___S 0 + +#define WMAC0_HWSCH_R0_SEND_FLUSH (0x00AAA2B4) +#define WMAC0_HWSCH_R0_SEND_FLUSH___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SEND_FLUSH___POR 0x00000000 +#define WMAC0_HWSCH_R0_SEND_FLUSH__SEND_FLUSH___POR 0x0 +#define WMAC0_HWSCH_R0_SEND_FLUSH__FLUSH_MASK___POR 0x00000 +#define WMAC0_HWSCH_R0_SEND_FLUSH__SEND_FLUSH___M 0x80000000 +#define WMAC0_HWSCH_R0_SEND_FLUSH__SEND_FLUSH___S 31 +#define WMAC0_HWSCH_R0_SEND_FLUSH__FLUSH_MASK___M 0x0003FFFF +#define WMAC0_HWSCH_R0_SEND_FLUSH__FLUSH_MASK___S 0 +#define WMAC0_HWSCH_R0_SEND_FLUSH___M 0x8003FFFF +#define WMAC0_HWSCH_R0_SEND_FLUSH___S 0 + +#define WMAC0_HWSCH_R0_FLUSH_STATUS (0x00AAA2B8) +#define WMAC0_HWSCH_R0_FLUSH_STATUS___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_FLUSH_STATUS___POR 0x00000000 +#define WMAC0_HWSCH_R0_FLUSH_STATUS__FLUSH_STATUS___POR 0x0 +#define WMAC0_HWSCH_R0_FLUSH_STATUS__FLUSH_STATUS___M 0x00000001 +#define WMAC0_HWSCH_R0_FLUSH_STATUS__FLUSH_STATUS___S 0 +#define WMAC0_HWSCH_R0_FLUSH_STATUS___M 0x00000001 +#define WMAC0_HWSCH_R0_FLUSH_STATUS___S 0 + +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER0 (0x00AAA2BC) +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER0___POR 0x00000000 +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER0__BOUNDARY_TIMER_ENABLE___POR 0x0 +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER0__BOUNDARY_TIMER_COUNT___POR 0x0000 +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER0__BOUNDARY_TIMER_ENABLE___M 0x80000000 +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER0__BOUNDARY_TIMER_ENABLE___S 31 +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER0__BOUNDARY_TIMER_COUNT___M 0x00007FFF +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER0__BOUNDARY_TIMER_COUNT___S 0 +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER0___M 0x80007FFF +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER0___S 0 + +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER1 (0x00AAA2C0) +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER1___POR 0x00000000 +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER1__BOUNDARY_TIMER_ENABLE___POR 0x0 +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER1__BOUNDARY_TIMER_COUNT___POR 0x0000 +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER1__BOUNDARY_TIMER_ENABLE___M 0x80000000 +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER1__BOUNDARY_TIMER_ENABLE___S 31 +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER1__BOUNDARY_TIMER_COUNT___M 0x00007FFF +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER1__BOUNDARY_TIMER_COUNT___S 0 +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER1___M 0x80007FFF +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER1___S 0 + +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER2 (0x00AAA2C4) +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER2___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER2___POR 0x00000000 +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER2__BOUNDARY_TIMER_ENABLE___POR 0x0 +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER2__BOUNDARY_TIMER_COUNT___POR 0x0000 +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER2__BOUNDARY_TIMER_ENABLE___M 0x80000000 +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER2__BOUNDARY_TIMER_ENABLE___S 31 +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER2__BOUNDARY_TIMER_COUNT___M 0x00007FFF +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER2__BOUNDARY_TIMER_COUNT___S 0 +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER2___M 0x80007FFF +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER2___S 0 + +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER3 (0x00AAA2C8) +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER3___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER3___POR 0x00000000 +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER3__BOUNDARY_TIMER_ENABLE___POR 0x0 +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER3__BOUNDARY_TIMER_COUNT___POR 0x0000 +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER3__BOUNDARY_TIMER_ENABLE___M 0x80000000 +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER3__BOUNDARY_TIMER_ENABLE___S 31 +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER3__BOUNDARY_TIMER_COUNT___M 0x00007FFF +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER3__BOUNDARY_TIMER_COUNT___S 0 +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER3___M 0x80007FFF +#define WMAC0_HWSCH_R0_BOUNDARY_TIMER3___S 0 + +#define WMAC0_HWSCH_R0_TXOP_CONTROL0 (0x00AAA2CC) +#define WMAC0_HWSCH_R0_TXOP_CONTROL0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_TXOP_CONTROL0___POR 0x03030303 +#define WMAC0_HWSCH_R0_TXOP_CONTROL0__TXOP_SEL_MASK_RING3___POR 0x03 +#define WMAC0_HWSCH_R0_TXOP_CONTROL0__TXOP_SEL_MASK_RING2___POR 0x03 +#define WMAC0_HWSCH_R0_TXOP_CONTROL0__TXOP_SEL_MASK_RING1___POR 0x03 +#define WMAC0_HWSCH_R0_TXOP_CONTROL0__TXOP_SEL_MASK_RING0___POR 0x03 +#define WMAC0_HWSCH_R0_TXOP_CONTROL0__TXOP_SEL_MASK_RING3___M 0xFF000000 +#define WMAC0_HWSCH_R0_TXOP_CONTROL0__TXOP_SEL_MASK_RING3___S 24 +#define WMAC0_HWSCH_R0_TXOP_CONTROL0__TXOP_SEL_MASK_RING2___M 0x00FF0000 +#define WMAC0_HWSCH_R0_TXOP_CONTROL0__TXOP_SEL_MASK_RING2___S 16 +#define WMAC0_HWSCH_R0_TXOP_CONTROL0__TXOP_SEL_MASK_RING1___M 0x0000FF00 +#define WMAC0_HWSCH_R0_TXOP_CONTROL0__TXOP_SEL_MASK_RING1___S 8 +#define WMAC0_HWSCH_R0_TXOP_CONTROL0__TXOP_SEL_MASK_RING0___M 0x000000FF +#define WMAC0_HWSCH_R0_TXOP_CONTROL0__TXOP_SEL_MASK_RING0___S 0 +#define WMAC0_HWSCH_R0_TXOP_CONTROL0___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TXOP_CONTROL0___S 0 + +#define WMAC0_HWSCH_R0_TXOP_CONTROL1 (0x00AAA2D0) +#define WMAC0_HWSCH_R0_TXOP_CONTROL1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_TXOP_CONTROL1___POR 0x03030303 +#define WMAC0_HWSCH_R0_TXOP_CONTROL1__TXOP_SEL_MASK_RING7___POR 0x03 +#define WMAC0_HWSCH_R0_TXOP_CONTROL1__TXOP_SEL_MASK_RING6___POR 0x03 +#define WMAC0_HWSCH_R0_TXOP_CONTROL1__TXOP_SEL_MASK_RING5___POR 0x03 +#define WMAC0_HWSCH_R0_TXOP_CONTROL1__TXOP_SEL_MASK_RING4___POR 0x03 +#define WMAC0_HWSCH_R0_TXOP_CONTROL1__TXOP_SEL_MASK_RING7___M 0xFF000000 +#define WMAC0_HWSCH_R0_TXOP_CONTROL1__TXOP_SEL_MASK_RING7___S 24 +#define WMAC0_HWSCH_R0_TXOP_CONTROL1__TXOP_SEL_MASK_RING6___M 0x00FF0000 +#define WMAC0_HWSCH_R0_TXOP_CONTROL1__TXOP_SEL_MASK_RING6___S 16 +#define WMAC0_HWSCH_R0_TXOP_CONTROL1__TXOP_SEL_MASK_RING5___M 0x0000FF00 +#define WMAC0_HWSCH_R0_TXOP_CONTROL1__TXOP_SEL_MASK_RING5___S 8 +#define WMAC0_HWSCH_R0_TXOP_CONTROL1__TXOP_SEL_MASK_RING4___M 0x000000FF +#define WMAC0_HWSCH_R0_TXOP_CONTROL1__TXOP_SEL_MASK_RING4___S 0 +#define WMAC0_HWSCH_R0_TXOP_CONTROL1___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TXOP_CONTROL1___S 0 + +#define WMAC0_HWSCH_R0_TXOP_CONTROL2 (0x00AAA2D4) +#define WMAC0_HWSCH_R0_TXOP_CONTROL2___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_TXOP_CONTROL2___POR 0x03030303 +#define WMAC0_HWSCH_R0_TXOP_CONTROL2__TXOP_SEL_MASK_RING11___POR 0x03 +#define WMAC0_HWSCH_R0_TXOP_CONTROL2__TXOP_SEL_MASK_RING10___POR 0x03 +#define WMAC0_HWSCH_R0_TXOP_CONTROL2__TXOP_SEL_MASK_RING9___POR 0x03 +#define WMAC0_HWSCH_R0_TXOP_CONTROL2__TXOP_SEL_MASK_RING8___POR 0x03 +#define WMAC0_HWSCH_R0_TXOP_CONTROL2__TXOP_SEL_MASK_RING11___M 0xFF000000 +#define WMAC0_HWSCH_R0_TXOP_CONTROL2__TXOP_SEL_MASK_RING11___S 24 +#define WMAC0_HWSCH_R0_TXOP_CONTROL2__TXOP_SEL_MASK_RING10___M 0x00FF0000 +#define WMAC0_HWSCH_R0_TXOP_CONTROL2__TXOP_SEL_MASK_RING10___S 16 +#define WMAC0_HWSCH_R0_TXOP_CONTROL2__TXOP_SEL_MASK_RING9___M 0x0000FF00 +#define WMAC0_HWSCH_R0_TXOP_CONTROL2__TXOP_SEL_MASK_RING9___S 8 +#define WMAC0_HWSCH_R0_TXOP_CONTROL2__TXOP_SEL_MASK_RING8___M 0x000000FF +#define WMAC0_HWSCH_R0_TXOP_CONTROL2__TXOP_SEL_MASK_RING8___S 0 +#define WMAC0_HWSCH_R0_TXOP_CONTROL2___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TXOP_CONTROL2___S 0 + +#define WMAC0_HWSCH_R0_TXOP_CONTROL3 (0x00AAA2D8) +#define WMAC0_HWSCH_R0_TXOP_CONTROL3___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_TXOP_CONTROL3___POR 0x03030303 +#define WMAC0_HWSCH_R0_TXOP_CONTROL3__TXOP_SEL_MASK_RING15___POR 0x03 +#define WMAC0_HWSCH_R0_TXOP_CONTROL3__TXOP_SEL_MASK_RING14___POR 0x03 +#define WMAC0_HWSCH_R0_TXOP_CONTROL3__TXOP_SEL_MASK_RING13___POR 0x03 +#define WMAC0_HWSCH_R0_TXOP_CONTROL3__TXOP_SEL_MASK_RING12___POR 0x03 +#define WMAC0_HWSCH_R0_TXOP_CONTROL3__TXOP_SEL_MASK_RING15___M 0xFF000000 +#define WMAC0_HWSCH_R0_TXOP_CONTROL3__TXOP_SEL_MASK_RING15___S 24 +#define WMAC0_HWSCH_R0_TXOP_CONTROL3__TXOP_SEL_MASK_RING14___M 0x00FF0000 +#define WMAC0_HWSCH_R0_TXOP_CONTROL3__TXOP_SEL_MASK_RING14___S 16 +#define WMAC0_HWSCH_R0_TXOP_CONTROL3__TXOP_SEL_MASK_RING13___M 0x0000FF00 +#define WMAC0_HWSCH_R0_TXOP_CONTROL3__TXOP_SEL_MASK_RING13___S 8 +#define WMAC0_HWSCH_R0_TXOP_CONTROL3__TXOP_SEL_MASK_RING12___M 0x000000FF +#define WMAC0_HWSCH_R0_TXOP_CONTROL3__TXOP_SEL_MASK_RING12___S 0 +#define WMAC0_HWSCH_R0_TXOP_CONTROL3___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TXOP_CONTROL3___S 0 + +#define WMAC0_HWSCH_R0_TXOP_CONTROL4 (0x00AAA2DC) +#define WMAC0_HWSCH_R0_TXOP_CONTROL4___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_TXOP_CONTROL4___POR 0x00000303 +#define WMAC0_HWSCH_R0_TXOP_CONTROL4__TXOP_SEL_MASK_RING17___POR 0x03 +#define WMAC0_HWSCH_R0_TXOP_CONTROL4__TXOP_SEL_MASK_RING16___POR 0x03 +#define WMAC0_HWSCH_R0_TXOP_CONTROL4__TXOP_SEL_MASK_RING17___M 0x0000FF00 +#define WMAC0_HWSCH_R0_TXOP_CONTROL4__TXOP_SEL_MASK_RING17___S 8 +#define WMAC0_HWSCH_R0_TXOP_CONTROL4__TXOP_SEL_MASK_RING16___M 0x000000FF +#define WMAC0_HWSCH_R0_TXOP_CONTROL4__TXOP_SEL_MASK_RING16___S 0 +#define WMAC0_HWSCH_R0_TXOP_CONTROL4___M 0x0000FFFF +#define WMAC0_HWSCH_R0_TXOP_CONTROL4___S 0 + +#define WMAC0_HWSCH_R0_TESTBUS_CTRL (0x00AAA2E0) +#define WMAC0_HWSCH_R0_TESTBUS_CTRL___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_TESTBUS_CTRL___POR 0x00000000 +#define WMAC0_HWSCH_R0_TESTBUS_CTRL__BLOCK_SELECT___POR 0x00 +#define WMAC0_HWSCH_R0_TESTBUS_CTRL__SIGNAL_SELECT___POR 0x0 +#define WMAC0_HWSCH_R0_TESTBUS_CTRL__BLOCK_SELECT___M 0x000003F0 +#define WMAC0_HWSCH_R0_TESTBUS_CTRL__BLOCK_SELECT___S 4 +#define WMAC0_HWSCH_R0_TESTBUS_CTRL__SIGNAL_SELECT___M 0x0000000F +#define WMAC0_HWSCH_R0_TESTBUS_CTRL__SIGNAL_SELECT___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_CTRL___M 0x000003FF +#define WMAC0_HWSCH_R0_TESTBUS_CTRL___S 0 + +#define WMAC0_HWSCH_R0_TESTBUS_n(n) (0x00AAA2E4+0x4*(n)) +#define WMAC0_HWSCH_R0_TESTBUS_n_nMIN 0 +#define WMAC0_HWSCH_R0_TESTBUS_n_nMAX 2047 +#define WMAC0_HWSCH_R0_TESTBUS_n_ELEM 2048 +#define WMAC0_HWSCH_R0_TESTBUS_n___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_n___POR 0x00000000 +#define WMAC0_HWSCH_R0_TESTBUS_n__DATA___POR 0x00000000 +#define WMAC0_HWSCH_R0_TESTBUS_n__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_n__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_n___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_n___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_0 (0x00AAA2E4) +#define WMAC0_HWSCH_R0_TESTBUS_0___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_0__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_0__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1 (0x00AAA2E8) +#define WMAC0_HWSCH_R0_TESTBUS_1___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2 (0x00AAA2EC) +#define WMAC0_HWSCH_R0_TESTBUS_2___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_3 (0x00AAA2F0) +#define WMAC0_HWSCH_R0_TESTBUS_3___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_3__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_3__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_4 (0x00AAA2F4) +#define WMAC0_HWSCH_R0_TESTBUS_4___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_4__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_4__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_5 (0x00AAA2F8) +#define WMAC0_HWSCH_R0_TESTBUS_5___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_5__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_5__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_6 (0x00AAA2FC) +#define WMAC0_HWSCH_R0_TESTBUS_6___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_6__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_6__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_7 (0x00AAA300) +#define WMAC0_HWSCH_R0_TESTBUS_7___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_7__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_7__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_8 (0x00AAA304) +#define WMAC0_HWSCH_R0_TESTBUS_8___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_8__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_8__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_9 (0x00AAA308) +#define WMAC0_HWSCH_R0_TESTBUS_9___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_9__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_9__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_10 (0x00AAA30C) +#define WMAC0_HWSCH_R0_TESTBUS_10___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_10__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_10__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_11 (0x00AAA310) +#define WMAC0_HWSCH_R0_TESTBUS_11___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_11__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_11__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_12 (0x00AAA314) +#define WMAC0_HWSCH_R0_TESTBUS_12___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_12__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_12__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_13 (0x00AAA318) +#define WMAC0_HWSCH_R0_TESTBUS_13___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_13__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_13__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_14 (0x00AAA31C) +#define WMAC0_HWSCH_R0_TESTBUS_14___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_14__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_14__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_15 (0x00AAA320) +#define WMAC0_HWSCH_R0_TESTBUS_15___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_15__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_15__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_16 (0x00AAA324) +#define WMAC0_HWSCH_R0_TESTBUS_16___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_16__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_16__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_17 (0x00AAA328) +#define WMAC0_HWSCH_R0_TESTBUS_17___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_17__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_17__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_18 (0x00AAA32C) +#define WMAC0_HWSCH_R0_TESTBUS_18___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_18__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_18__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_19 (0x00AAA330) +#define WMAC0_HWSCH_R0_TESTBUS_19___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_19__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_19__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_20 (0x00AAA334) +#define WMAC0_HWSCH_R0_TESTBUS_20___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_20__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_20__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_21 (0x00AAA338) +#define WMAC0_HWSCH_R0_TESTBUS_21___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_21__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_21__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_22 (0x00AAA33C) +#define WMAC0_HWSCH_R0_TESTBUS_22___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_22__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_22__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_23 (0x00AAA340) +#define WMAC0_HWSCH_R0_TESTBUS_23___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_23__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_23__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_24 (0x00AAA344) +#define WMAC0_HWSCH_R0_TESTBUS_24___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_24__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_24__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_25 (0x00AAA348) +#define WMAC0_HWSCH_R0_TESTBUS_25___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_25__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_25__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_26 (0x00AAA34C) +#define WMAC0_HWSCH_R0_TESTBUS_26___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_26__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_26__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_27 (0x00AAA350) +#define WMAC0_HWSCH_R0_TESTBUS_27___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_27__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_27__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_28 (0x00AAA354) +#define WMAC0_HWSCH_R0_TESTBUS_28___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_28__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_28__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_29 (0x00AAA358) +#define WMAC0_HWSCH_R0_TESTBUS_29___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_29__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_29__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_30 (0x00AAA35C) +#define WMAC0_HWSCH_R0_TESTBUS_30___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_30__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_30__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_31 (0x00AAA360) +#define WMAC0_HWSCH_R0_TESTBUS_31___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_31__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_31__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_32 (0x00AAA364) +#define WMAC0_HWSCH_R0_TESTBUS_32___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_32__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_32__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_33 (0x00AAA368) +#define WMAC0_HWSCH_R0_TESTBUS_33___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_33__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_33__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_34 (0x00AAA36C) +#define WMAC0_HWSCH_R0_TESTBUS_34___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_34__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_34__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_35 (0x00AAA370) +#define WMAC0_HWSCH_R0_TESTBUS_35___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_35__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_35__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_36 (0x00AAA374) +#define WMAC0_HWSCH_R0_TESTBUS_36___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_36__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_36__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_37 (0x00AAA378) +#define WMAC0_HWSCH_R0_TESTBUS_37___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_37__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_37__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_38 (0x00AAA37C) +#define WMAC0_HWSCH_R0_TESTBUS_38___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_38__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_38__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_39 (0x00AAA380) +#define WMAC0_HWSCH_R0_TESTBUS_39___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_39__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_39__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_40 (0x00AAA384) +#define WMAC0_HWSCH_R0_TESTBUS_40___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_40__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_40__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_41 (0x00AAA388) +#define WMAC0_HWSCH_R0_TESTBUS_41___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_41__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_41__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_42 (0x00AAA38C) +#define WMAC0_HWSCH_R0_TESTBUS_42___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_42__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_42__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_43 (0x00AAA390) +#define WMAC0_HWSCH_R0_TESTBUS_43___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_43__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_43__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_44 (0x00AAA394) +#define WMAC0_HWSCH_R0_TESTBUS_44___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_44__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_44__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_45 (0x00AAA398) +#define WMAC0_HWSCH_R0_TESTBUS_45___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_45__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_45__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_46 (0x00AAA39C) +#define WMAC0_HWSCH_R0_TESTBUS_46___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_46__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_46__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_47 (0x00AAA3A0) +#define WMAC0_HWSCH_R0_TESTBUS_47___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_47__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_47__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_48 (0x00AAA3A4) +#define WMAC0_HWSCH_R0_TESTBUS_48___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_48__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_48__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_49 (0x00AAA3A8) +#define WMAC0_HWSCH_R0_TESTBUS_49___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_49__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_49__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_50 (0x00AAA3AC) +#define WMAC0_HWSCH_R0_TESTBUS_50___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_50__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_50__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_51 (0x00AAA3B0) +#define WMAC0_HWSCH_R0_TESTBUS_51___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_51__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_51__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_52 (0x00AAA3B4) +#define WMAC0_HWSCH_R0_TESTBUS_52___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_52__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_52__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_53 (0x00AAA3B8) +#define WMAC0_HWSCH_R0_TESTBUS_53___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_53__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_53__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_54 (0x00AAA3BC) +#define WMAC0_HWSCH_R0_TESTBUS_54___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_54__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_54__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_55 (0x00AAA3C0) +#define WMAC0_HWSCH_R0_TESTBUS_55___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_55__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_55__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_56 (0x00AAA3C4) +#define WMAC0_HWSCH_R0_TESTBUS_56___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_56__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_56__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_57 (0x00AAA3C8) +#define WMAC0_HWSCH_R0_TESTBUS_57___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_57__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_57__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_58 (0x00AAA3CC) +#define WMAC0_HWSCH_R0_TESTBUS_58___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_58__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_58__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_59 (0x00AAA3D0) +#define WMAC0_HWSCH_R0_TESTBUS_59___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_59__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_59__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_60 (0x00AAA3D4) +#define WMAC0_HWSCH_R0_TESTBUS_60___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_60__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_60__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_61 (0x00AAA3D8) +#define WMAC0_HWSCH_R0_TESTBUS_61___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_61__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_61__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_62 (0x00AAA3DC) +#define WMAC0_HWSCH_R0_TESTBUS_62___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_62__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_62__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_63 (0x00AAA3E0) +#define WMAC0_HWSCH_R0_TESTBUS_63___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_63__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_63__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_64 (0x00AAA3E4) +#define WMAC0_HWSCH_R0_TESTBUS_64___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_64__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_64__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_65 (0x00AAA3E8) +#define WMAC0_HWSCH_R0_TESTBUS_65___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_65__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_65__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_66 (0x00AAA3EC) +#define WMAC0_HWSCH_R0_TESTBUS_66___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_66__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_66__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_67 (0x00AAA3F0) +#define WMAC0_HWSCH_R0_TESTBUS_67___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_67__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_67__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_68 (0x00AAA3F4) +#define WMAC0_HWSCH_R0_TESTBUS_68___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_68__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_68__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_69 (0x00AAA3F8) +#define WMAC0_HWSCH_R0_TESTBUS_69___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_69__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_69__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_70 (0x00AAA3FC) +#define WMAC0_HWSCH_R0_TESTBUS_70___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_70__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_70__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_71 (0x00AAA400) +#define WMAC0_HWSCH_R0_TESTBUS_71___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_71__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_71__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_72 (0x00AAA404) +#define WMAC0_HWSCH_R0_TESTBUS_72___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_72__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_72__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_73 (0x00AAA408) +#define WMAC0_HWSCH_R0_TESTBUS_73___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_73__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_73__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_74 (0x00AAA40C) +#define WMAC0_HWSCH_R0_TESTBUS_74___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_74__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_74__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_75 (0x00AAA410) +#define WMAC0_HWSCH_R0_TESTBUS_75___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_75__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_75__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_76 (0x00AAA414) +#define WMAC0_HWSCH_R0_TESTBUS_76___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_76__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_76__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_77 (0x00AAA418) +#define WMAC0_HWSCH_R0_TESTBUS_77___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_77__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_77__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_78 (0x00AAA41C) +#define WMAC0_HWSCH_R0_TESTBUS_78___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_78__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_78__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_79 (0x00AAA420) +#define WMAC0_HWSCH_R0_TESTBUS_79___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_79__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_79__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_80 (0x00AAA424) +#define WMAC0_HWSCH_R0_TESTBUS_80___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_80__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_80__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_81 (0x00AAA428) +#define WMAC0_HWSCH_R0_TESTBUS_81___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_81__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_81__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_82 (0x00AAA42C) +#define WMAC0_HWSCH_R0_TESTBUS_82___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_82__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_82__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_83 (0x00AAA430) +#define WMAC0_HWSCH_R0_TESTBUS_83___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_83__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_83__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_84 (0x00AAA434) +#define WMAC0_HWSCH_R0_TESTBUS_84___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_84__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_84__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_85 (0x00AAA438) +#define WMAC0_HWSCH_R0_TESTBUS_85___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_85__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_85__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_86 (0x00AAA43C) +#define WMAC0_HWSCH_R0_TESTBUS_86___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_86__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_86__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_87 (0x00AAA440) +#define WMAC0_HWSCH_R0_TESTBUS_87___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_87__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_87__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_88 (0x00AAA444) +#define WMAC0_HWSCH_R0_TESTBUS_88___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_88__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_88__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_89 (0x00AAA448) +#define WMAC0_HWSCH_R0_TESTBUS_89___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_89__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_89__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_90 (0x00AAA44C) +#define WMAC0_HWSCH_R0_TESTBUS_90___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_90__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_90__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_91 (0x00AAA450) +#define WMAC0_HWSCH_R0_TESTBUS_91___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_91__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_91__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_92 (0x00AAA454) +#define WMAC0_HWSCH_R0_TESTBUS_92___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_92__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_92__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_93 (0x00AAA458) +#define WMAC0_HWSCH_R0_TESTBUS_93___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_93__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_93__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_94 (0x00AAA45C) +#define WMAC0_HWSCH_R0_TESTBUS_94___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_94__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_94__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_95 (0x00AAA460) +#define WMAC0_HWSCH_R0_TESTBUS_95___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_95__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_95__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_96 (0x00AAA464) +#define WMAC0_HWSCH_R0_TESTBUS_96___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_96__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_96__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_97 (0x00AAA468) +#define WMAC0_HWSCH_R0_TESTBUS_97___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_97__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_97__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_98 (0x00AAA46C) +#define WMAC0_HWSCH_R0_TESTBUS_98___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_98__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_98__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_99 (0x00AAA470) +#define WMAC0_HWSCH_R0_TESTBUS_99___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_99__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_99__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_100 (0x00AAA474) +#define WMAC0_HWSCH_R0_TESTBUS_100___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_100__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_100__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_101 (0x00AAA478) +#define WMAC0_HWSCH_R0_TESTBUS_101___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_101__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_101__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_102 (0x00AAA47C) +#define WMAC0_HWSCH_R0_TESTBUS_102___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_102__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_102__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_103 (0x00AAA480) +#define WMAC0_HWSCH_R0_TESTBUS_103___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_103__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_103__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_104 (0x00AAA484) +#define WMAC0_HWSCH_R0_TESTBUS_104___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_104__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_104__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_105 (0x00AAA488) +#define WMAC0_HWSCH_R0_TESTBUS_105___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_105__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_105__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_106 (0x00AAA48C) +#define WMAC0_HWSCH_R0_TESTBUS_106___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_106__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_106__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_107 (0x00AAA490) +#define WMAC0_HWSCH_R0_TESTBUS_107___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_107__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_107__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_108 (0x00AAA494) +#define WMAC0_HWSCH_R0_TESTBUS_108___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_108__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_108__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_109 (0x00AAA498) +#define WMAC0_HWSCH_R0_TESTBUS_109___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_109__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_109__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_110 (0x00AAA49C) +#define WMAC0_HWSCH_R0_TESTBUS_110___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_110__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_110__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_111 (0x00AAA4A0) +#define WMAC0_HWSCH_R0_TESTBUS_111___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_111__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_111__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_112 (0x00AAA4A4) +#define WMAC0_HWSCH_R0_TESTBUS_112___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_112__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_112__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_113 (0x00AAA4A8) +#define WMAC0_HWSCH_R0_TESTBUS_113___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_113__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_113__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_114 (0x00AAA4AC) +#define WMAC0_HWSCH_R0_TESTBUS_114___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_114__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_114__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_115 (0x00AAA4B0) +#define WMAC0_HWSCH_R0_TESTBUS_115___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_115__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_115__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_116 (0x00AAA4B4) +#define WMAC0_HWSCH_R0_TESTBUS_116___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_116__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_116__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_117 (0x00AAA4B8) +#define WMAC0_HWSCH_R0_TESTBUS_117___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_117__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_117__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_118 (0x00AAA4BC) +#define WMAC0_HWSCH_R0_TESTBUS_118___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_118__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_118__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_119 (0x00AAA4C0) +#define WMAC0_HWSCH_R0_TESTBUS_119___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_119__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_119__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_120 (0x00AAA4C4) +#define WMAC0_HWSCH_R0_TESTBUS_120___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_120__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_120__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_121 (0x00AAA4C8) +#define WMAC0_HWSCH_R0_TESTBUS_121___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_121__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_121__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_122 (0x00AAA4CC) +#define WMAC0_HWSCH_R0_TESTBUS_122___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_122__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_122__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_123 (0x00AAA4D0) +#define WMAC0_HWSCH_R0_TESTBUS_123___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_123__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_123__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_124 (0x00AAA4D4) +#define WMAC0_HWSCH_R0_TESTBUS_124___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_124__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_124__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_125 (0x00AAA4D8) +#define WMAC0_HWSCH_R0_TESTBUS_125___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_125__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_125__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_126 (0x00AAA4DC) +#define WMAC0_HWSCH_R0_TESTBUS_126___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_126__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_126__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_127 (0x00AAA4E0) +#define WMAC0_HWSCH_R0_TESTBUS_127___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_127__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_127__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_128 (0x00AAA4E4) +#define WMAC0_HWSCH_R0_TESTBUS_128___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_128__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_128__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_129 (0x00AAA4E8) +#define WMAC0_HWSCH_R0_TESTBUS_129___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_129__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_129__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_130 (0x00AAA4EC) +#define WMAC0_HWSCH_R0_TESTBUS_130___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_130__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_130__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_131 (0x00AAA4F0) +#define WMAC0_HWSCH_R0_TESTBUS_131___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_131__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_131__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_132 (0x00AAA4F4) +#define WMAC0_HWSCH_R0_TESTBUS_132___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_132__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_132__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_133 (0x00AAA4F8) +#define WMAC0_HWSCH_R0_TESTBUS_133___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_133__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_133__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_134 (0x00AAA4FC) +#define WMAC0_HWSCH_R0_TESTBUS_134___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_134__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_134__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_135 (0x00AAA500) +#define WMAC0_HWSCH_R0_TESTBUS_135___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_135__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_135__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_136 (0x00AAA504) +#define WMAC0_HWSCH_R0_TESTBUS_136___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_136__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_136__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_137 (0x00AAA508) +#define WMAC0_HWSCH_R0_TESTBUS_137___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_137__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_137__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_138 (0x00AAA50C) +#define WMAC0_HWSCH_R0_TESTBUS_138___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_138__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_138__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_139 (0x00AAA510) +#define WMAC0_HWSCH_R0_TESTBUS_139___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_139__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_139__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_140 (0x00AAA514) +#define WMAC0_HWSCH_R0_TESTBUS_140___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_140__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_140__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_141 (0x00AAA518) +#define WMAC0_HWSCH_R0_TESTBUS_141___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_141__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_141__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_142 (0x00AAA51C) +#define WMAC0_HWSCH_R0_TESTBUS_142___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_142__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_142__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_143 (0x00AAA520) +#define WMAC0_HWSCH_R0_TESTBUS_143___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_143__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_143__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_144 (0x00AAA524) +#define WMAC0_HWSCH_R0_TESTBUS_144___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_144__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_144__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_145 (0x00AAA528) +#define WMAC0_HWSCH_R0_TESTBUS_145___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_145__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_145__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_146 (0x00AAA52C) +#define WMAC0_HWSCH_R0_TESTBUS_146___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_146__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_146__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_147 (0x00AAA530) +#define WMAC0_HWSCH_R0_TESTBUS_147___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_147__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_147__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_148 (0x00AAA534) +#define WMAC0_HWSCH_R0_TESTBUS_148___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_148__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_148__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_149 (0x00AAA538) +#define WMAC0_HWSCH_R0_TESTBUS_149___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_149__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_149__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_150 (0x00AAA53C) +#define WMAC0_HWSCH_R0_TESTBUS_150___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_150__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_150__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_151 (0x00AAA540) +#define WMAC0_HWSCH_R0_TESTBUS_151___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_151__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_151__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_152 (0x00AAA544) +#define WMAC0_HWSCH_R0_TESTBUS_152___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_152__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_152__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_153 (0x00AAA548) +#define WMAC0_HWSCH_R0_TESTBUS_153___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_153__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_153__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_154 (0x00AAA54C) +#define WMAC0_HWSCH_R0_TESTBUS_154___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_154__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_154__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_155 (0x00AAA550) +#define WMAC0_HWSCH_R0_TESTBUS_155___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_155__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_155__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_156 (0x00AAA554) +#define WMAC0_HWSCH_R0_TESTBUS_156___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_156__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_156__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_157 (0x00AAA558) +#define WMAC0_HWSCH_R0_TESTBUS_157___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_157__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_157__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_158 (0x00AAA55C) +#define WMAC0_HWSCH_R0_TESTBUS_158___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_158__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_158__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_159 (0x00AAA560) +#define WMAC0_HWSCH_R0_TESTBUS_159___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_159__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_159__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_160 (0x00AAA564) +#define WMAC0_HWSCH_R0_TESTBUS_160___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_160__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_160__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_161 (0x00AAA568) +#define WMAC0_HWSCH_R0_TESTBUS_161___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_161__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_161__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_162 (0x00AAA56C) +#define WMAC0_HWSCH_R0_TESTBUS_162___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_162__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_162__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_163 (0x00AAA570) +#define WMAC0_HWSCH_R0_TESTBUS_163___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_163__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_163__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_164 (0x00AAA574) +#define WMAC0_HWSCH_R0_TESTBUS_164___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_164__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_164__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_165 (0x00AAA578) +#define WMAC0_HWSCH_R0_TESTBUS_165___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_165__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_165__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_166 (0x00AAA57C) +#define WMAC0_HWSCH_R0_TESTBUS_166___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_166__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_166__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_167 (0x00AAA580) +#define WMAC0_HWSCH_R0_TESTBUS_167___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_167__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_167__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_168 (0x00AAA584) +#define WMAC0_HWSCH_R0_TESTBUS_168___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_168__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_168__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_169 (0x00AAA588) +#define WMAC0_HWSCH_R0_TESTBUS_169___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_169__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_169__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_170 (0x00AAA58C) +#define WMAC0_HWSCH_R0_TESTBUS_170___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_170__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_170__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_171 (0x00AAA590) +#define WMAC0_HWSCH_R0_TESTBUS_171___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_171__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_171__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_172 (0x00AAA594) +#define WMAC0_HWSCH_R0_TESTBUS_172___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_172__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_172__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_173 (0x00AAA598) +#define WMAC0_HWSCH_R0_TESTBUS_173___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_173__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_173__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_174 (0x00AAA59C) +#define WMAC0_HWSCH_R0_TESTBUS_174___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_174__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_174__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_175 (0x00AAA5A0) +#define WMAC0_HWSCH_R0_TESTBUS_175___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_175__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_175__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_176 (0x00AAA5A4) +#define WMAC0_HWSCH_R0_TESTBUS_176___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_176__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_176__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_177 (0x00AAA5A8) +#define WMAC0_HWSCH_R0_TESTBUS_177___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_177__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_177__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_178 (0x00AAA5AC) +#define WMAC0_HWSCH_R0_TESTBUS_178___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_178__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_178__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_179 (0x00AAA5B0) +#define WMAC0_HWSCH_R0_TESTBUS_179___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_179__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_179__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_180 (0x00AAA5B4) +#define WMAC0_HWSCH_R0_TESTBUS_180___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_180__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_180__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_181 (0x00AAA5B8) +#define WMAC0_HWSCH_R0_TESTBUS_181___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_181__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_181__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_182 (0x00AAA5BC) +#define WMAC0_HWSCH_R0_TESTBUS_182___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_182__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_182__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_183 (0x00AAA5C0) +#define WMAC0_HWSCH_R0_TESTBUS_183___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_183__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_183__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_184 (0x00AAA5C4) +#define WMAC0_HWSCH_R0_TESTBUS_184___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_184__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_184__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_185 (0x00AAA5C8) +#define WMAC0_HWSCH_R0_TESTBUS_185___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_185__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_185__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_186 (0x00AAA5CC) +#define WMAC0_HWSCH_R0_TESTBUS_186___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_186__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_186__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_187 (0x00AAA5D0) +#define WMAC0_HWSCH_R0_TESTBUS_187___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_187__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_187__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_188 (0x00AAA5D4) +#define WMAC0_HWSCH_R0_TESTBUS_188___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_188__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_188__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_189 (0x00AAA5D8) +#define WMAC0_HWSCH_R0_TESTBUS_189___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_189__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_189__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_190 (0x00AAA5DC) +#define WMAC0_HWSCH_R0_TESTBUS_190___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_190__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_190__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_191 (0x00AAA5E0) +#define WMAC0_HWSCH_R0_TESTBUS_191___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_191__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_191__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_192 (0x00AAA5E4) +#define WMAC0_HWSCH_R0_TESTBUS_192___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_192__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_192__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_193 (0x00AAA5E8) +#define WMAC0_HWSCH_R0_TESTBUS_193___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_193__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_193__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_194 (0x00AAA5EC) +#define WMAC0_HWSCH_R0_TESTBUS_194___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_194__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_194__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_195 (0x00AAA5F0) +#define WMAC0_HWSCH_R0_TESTBUS_195___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_195__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_195__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_196 (0x00AAA5F4) +#define WMAC0_HWSCH_R0_TESTBUS_196___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_196__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_196__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_197 (0x00AAA5F8) +#define WMAC0_HWSCH_R0_TESTBUS_197___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_197__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_197__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_198 (0x00AAA5FC) +#define WMAC0_HWSCH_R0_TESTBUS_198___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_198__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_198__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_199 (0x00AAA600) +#define WMAC0_HWSCH_R0_TESTBUS_199___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_199__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_199__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_200 (0x00AAA604) +#define WMAC0_HWSCH_R0_TESTBUS_200___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_200__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_200__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_201 (0x00AAA608) +#define WMAC0_HWSCH_R0_TESTBUS_201___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_201__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_201__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_202 (0x00AAA60C) +#define WMAC0_HWSCH_R0_TESTBUS_202___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_202__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_202__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_203 (0x00AAA610) +#define WMAC0_HWSCH_R0_TESTBUS_203___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_203__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_203__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_204 (0x00AAA614) +#define WMAC0_HWSCH_R0_TESTBUS_204___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_204__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_204__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_205 (0x00AAA618) +#define WMAC0_HWSCH_R0_TESTBUS_205___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_205__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_205__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_206 (0x00AAA61C) +#define WMAC0_HWSCH_R0_TESTBUS_206___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_206__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_206__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_207 (0x00AAA620) +#define WMAC0_HWSCH_R0_TESTBUS_207___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_207__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_207__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_208 (0x00AAA624) +#define WMAC0_HWSCH_R0_TESTBUS_208___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_208__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_208__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_209 (0x00AAA628) +#define WMAC0_HWSCH_R0_TESTBUS_209___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_209__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_209__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_210 (0x00AAA62C) +#define WMAC0_HWSCH_R0_TESTBUS_210___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_210__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_210__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_211 (0x00AAA630) +#define WMAC0_HWSCH_R0_TESTBUS_211___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_211__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_211__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_212 (0x00AAA634) +#define WMAC0_HWSCH_R0_TESTBUS_212___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_212__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_212__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_213 (0x00AAA638) +#define WMAC0_HWSCH_R0_TESTBUS_213___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_213__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_213__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_214 (0x00AAA63C) +#define WMAC0_HWSCH_R0_TESTBUS_214___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_214__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_214__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_215 (0x00AAA640) +#define WMAC0_HWSCH_R0_TESTBUS_215___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_215__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_215__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_216 (0x00AAA644) +#define WMAC0_HWSCH_R0_TESTBUS_216___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_216__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_216__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_217 (0x00AAA648) +#define WMAC0_HWSCH_R0_TESTBUS_217___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_217__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_217__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_218 (0x00AAA64C) +#define WMAC0_HWSCH_R0_TESTBUS_218___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_218__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_218__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_219 (0x00AAA650) +#define WMAC0_HWSCH_R0_TESTBUS_219___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_219__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_219__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_220 (0x00AAA654) +#define WMAC0_HWSCH_R0_TESTBUS_220___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_220__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_220__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_221 (0x00AAA658) +#define WMAC0_HWSCH_R0_TESTBUS_221___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_221__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_221__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_222 (0x00AAA65C) +#define WMAC0_HWSCH_R0_TESTBUS_222___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_222__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_222__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_223 (0x00AAA660) +#define WMAC0_HWSCH_R0_TESTBUS_223___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_223__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_223__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_224 (0x00AAA664) +#define WMAC0_HWSCH_R0_TESTBUS_224___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_224__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_224__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_225 (0x00AAA668) +#define WMAC0_HWSCH_R0_TESTBUS_225___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_225__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_225__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_226 (0x00AAA66C) +#define WMAC0_HWSCH_R0_TESTBUS_226___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_226__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_226__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_227 (0x00AAA670) +#define WMAC0_HWSCH_R0_TESTBUS_227___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_227__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_227__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_228 (0x00AAA674) +#define WMAC0_HWSCH_R0_TESTBUS_228___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_228__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_228__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_229 (0x00AAA678) +#define WMAC0_HWSCH_R0_TESTBUS_229___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_229__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_229__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_230 (0x00AAA67C) +#define WMAC0_HWSCH_R0_TESTBUS_230___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_230__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_230__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_231 (0x00AAA680) +#define WMAC0_HWSCH_R0_TESTBUS_231___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_231__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_231__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_232 (0x00AAA684) +#define WMAC0_HWSCH_R0_TESTBUS_232___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_232__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_232__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_233 (0x00AAA688) +#define WMAC0_HWSCH_R0_TESTBUS_233___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_233__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_233__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_234 (0x00AAA68C) +#define WMAC0_HWSCH_R0_TESTBUS_234___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_234__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_234__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_235 (0x00AAA690) +#define WMAC0_HWSCH_R0_TESTBUS_235___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_235__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_235__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_236 (0x00AAA694) +#define WMAC0_HWSCH_R0_TESTBUS_236___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_236__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_236__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_237 (0x00AAA698) +#define WMAC0_HWSCH_R0_TESTBUS_237___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_237__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_237__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_238 (0x00AAA69C) +#define WMAC0_HWSCH_R0_TESTBUS_238___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_238__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_238__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_239 (0x00AAA6A0) +#define WMAC0_HWSCH_R0_TESTBUS_239___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_239__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_239__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_240 (0x00AAA6A4) +#define WMAC0_HWSCH_R0_TESTBUS_240___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_240__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_240__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_241 (0x00AAA6A8) +#define WMAC0_HWSCH_R0_TESTBUS_241___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_241__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_241__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_242 (0x00AAA6AC) +#define WMAC0_HWSCH_R0_TESTBUS_242___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_242__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_242__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_243 (0x00AAA6B0) +#define WMAC0_HWSCH_R0_TESTBUS_243___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_243__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_243__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_244 (0x00AAA6B4) +#define WMAC0_HWSCH_R0_TESTBUS_244___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_244__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_244__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_245 (0x00AAA6B8) +#define WMAC0_HWSCH_R0_TESTBUS_245___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_245__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_245__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_246 (0x00AAA6BC) +#define WMAC0_HWSCH_R0_TESTBUS_246___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_246__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_246__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_247 (0x00AAA6C0) +#define WMAC0_HWSCH_R0_TESTBUS_247___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_247__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_247__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_248 (0x00AAA6C4) +#define WMAC0_HWSCH_R0_TESTBUS_248___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_248__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_248__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_249 (0x00AAA6C8) +#define WMAC0_HWSCH_R0_TESTBUS_249___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_249__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_249__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_250 (0x00AAA6CC) +#define WMAC0_HWSCH_R0_TESTBUS_250___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_250__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_250__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_251 (0x00AAA6D0) +#define WMAC0_HWSCH_R0_TESTBUS_251___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_251__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_251__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_252 (0x00AAA6D4) +#define WMAC0_HWSCH_R0_TESTBUS_252___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_252__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_252__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_253 (0x00AAA6D8) +#define WMAC0_HWSCH_R0_TESTBUS_253___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_253__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_253__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_254 (0x00AAA6DC) +#define WMAC0_HWSCH_R0_TESTBUS_254___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_254__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_254__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_255 (0x00AAA6E0) +#define WMAC0_HWSCH_R0_TESTBUS_255___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_255__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_255__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_256 (0x00AAA6E4) +#define WMAC0_HWSCH_R0_TESTBUS_256___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_256__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_256__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_257 (0x00AAA6E8) +#define WMAC0_HWSCH_R0_TESTBUS_257___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_257__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_257__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_258 (0x00AAA6EC) +#define WMAC0_HWSCH_R0_TESTBUS_258___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_258__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_258__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_259 (0x00AAA6F0) +#define WMAC0_HWSCH_R0_TESTBUS_259___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_259__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_259__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_260 (0x00AAA6F4) +#define WMAC0_HWSCH_R0_TESTBUS_260___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_260__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_260__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_261 (0x00AAA6F8) +#define WMAC0_HWSCH_R0_TESTBUS_261___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_261__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_261__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_262 (0x00AAA6FC) +#define WMAC0_HWSCH_R0_TESTBUS_262___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_262__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_262__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_263 (0x00AAA700) +#define WMAC0_HWSCH_R0_TESTBUS_263___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_263__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_263__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_264 (0x00AAA704) +#define WMAC0_HWSCH_R0_TESTBUS_264___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_264__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_264__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_265 (0x00AAA708) +#define WMAC0_HWSCH_R0_TESTBUS_265___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_265__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_265__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_266 (0x00AAA70C) +#define WMAC0_HWSCH_R0_TESTBUS_266___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_266__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_266__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_267 (0x00AAA710) +#define WMAC0_HWSCH_R0_TESTBUS_267___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_267__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_267__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_268 (0x00AAA714) +#define WMAC0_HWSCH_R0_TESTBUS_268___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_268__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_268__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_269 (0x00AAA718) +#define WMAC0_HWSCH_R0_TESTBUS_269___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_269__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_269__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_270 (0x00AAA71C) +#define WMAC0_HWSCH_R0_TESTBUS_270___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_270__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_270__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_271 (0x00AAA720) +#define WMAC0_HWSCH_R0_TESTBUS_271___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_271__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_271__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_272 (0x00AAA724) +#define WMAC0_HWSCH_R0_TESTBUS_272___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_272__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_272__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_273 (0x00AAA728) +#define WMAC0_HWSCH_R0_TESTBUS_273___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_273__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_273__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_274 (0x00AAA72C) +#define WMAC0_HWSCH_R0_TESTBUS_274___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_274__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_274__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_275 (0x00AAA730) +#define WMAC0_HWSCH_R0_TESTBUS_275___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_275__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_275__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_276 (0x00AAA734) +#define WMAC0_HWSCH_R0_TESTBUS_276___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_276__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_276__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_277 (0x00AAA738) +#define WMAC0_HWSCH_R0_TESTBUS_277___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_277__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_277__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_278 (0x00AAA73C) +#define WMAC0_HWSCH_R0_TESTBUS_278___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_278__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_278__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_279 (0x00AAA740) +#define WMAC0_HWSCH_R0_TESTBUS_279___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_279__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_279__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_280 (0x00AAA744) +#define WMAC0_HWSCH_R0_TESTBUS_280___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_280__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_280__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_281 (0x00AAA748) +#define WMAC0_HWSCH_R0_TESTBUS_281___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_281__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_281__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_282 (0x00AAA74C) +#define WMAC0_HWSCH_R0_TESTBUS_282___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_282__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_282__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_283 (0x00AAA750) +#define WMAC0_HWSCH_R0_TESTBUS_283___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_283__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_283__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_284 (0x00AAA754) +#define WMAC0_HWSCH_R0_TESTBUS_284___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_284__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_284__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_285 (0x00AAA758) +#define WMAC0_HWSCH_R0_TESTBUS_285___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_285__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_285__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_286 (0x00AAA75C) +#define WMAC0_HWSCH_R0_TESTBUS_286___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_286__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_286__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_287 (0x00AAA760) +#define WMAC0_HWSCH_R0_TESTBUS_287___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_287__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_287__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_288 (0x00AAA764) +#define WMAC0_HWSCH_R0_TESTBUS_288___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_288__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_288__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_289 (0x00AAA768) +#define WMAC0_HWSCH_R0_TESTBUS_289___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_289__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_289__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_290 (0x00AAA76C) +#define WMAC0_HWSCH_R0_TESTBUS_290___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_290__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_290__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_291 (0x00AAA770) +#define WMAC0_HWSCH_R0_TESTBUS_291___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_291__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_291__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_292 (0x00AAA774) +#define WMAC0_HWSCH_R0_TESTBUS_292___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_292__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_292__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_293 (0x00AAA778) +#define WMAC0_HWSCH_R0_TESTBUS_293___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_293__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_293__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_294 (0x00AAA77C) +#define WMAC0_HWSCH_R0_TESTBUS_294___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_294__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_294__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_295 (0x00AAA780) +#define WMAC0_HWSCH_R0_TESTBUS_295___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_295__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_295__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_296 (0x00AAA784) +#define WMAC0_HWSCH_R0_TESTBUS_296___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_296__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_296__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_297 (0x00AAA788) +#define WMAC0_HWSCH_R0_TESTBUS_297___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_297__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_297__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_298 (0x00AAA78C) +#define WMAC0_HWSCH_R0_TESTBUS_298___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_298__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_298__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_299 (0x00AAA790) +#define WMAC0_HWSCH_R0_TESTBUS_299___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_299__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_299__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_300 (0x00AAA794) +#define WMAC0_HWSCH_R0_TESTBUS_300___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_300__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_300__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_301 (0x00AAA798) +#define WMAC0_HWSCH_R0_TESTBUS_301___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_301__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_301__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_302 (0x00AAA79C) +#define WMAC0_HWSCH_R0_TESTBUS_302___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_302__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_302__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_303 (0x00AAA7A0) +#define WMAC0_HWSCH_R0_TESTBUS_303___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_303__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_303__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_304 (0x00AAA7A4) +#define WMAC0_HWSCH_R0_TESTBUS_304___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_304__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_304__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_305 (0x00AAA7A8) +#define WMAC0_HWSCH_R0_TESTBUS_305___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_305__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_305__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_306 (0x00AAA7AC) +#define WMAC0_HWSCH_R0_TESTBUS_306___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_306__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_306__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_307 (0x00AAA7B0) +#define WMAC0_HWSCH_R0_TESTBUS_307___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_307__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_307__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_308 (0x00AAA7B4) +#define WMAC0_HWSCH_R0_TESTBUS_308___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_308__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_308__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_309 (0x00AAA7B8) +#define WMAC0_HWSCH_R0_TESTBUS_309___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_309__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_309__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_310 (0x00AAA7BC) +#define WMAC0_HWSCH_R0_TESTBUS_310___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_310__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_310__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_311 (0x00AAA7C0) +#define WMAC0_HWSCH_R0_TESTBUS_311___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_311__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_311__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_312 (0x00AAA7C4) +#define WMAC0_HWSCH_R0_TESTBUS_312___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_312__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_312__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_313 (0x00AAA7C8) +#define WMAC0_HWSCH_R0_TESTBUS_313___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_313__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_313__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_314 (0x00AAA7CC) +#define WMAC0_HWSCH_R0_TESTBUS_314___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_314__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_314__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_315 (0x00AAA7D0) +#define WMAC0_HWSCH_R0_TESTBUS_315___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_315__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_315__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_316 (0x00AAA7D4) +#define WMAC0_HWSCH_R0_TESTBUS_316___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_316__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_316__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_317 (0x00AAA7D8) +#define WMAC0_HWSCH_R0_TESTBUS_317___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_317__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_317__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_318 (0x00AAA7DC) +#define WMAC0_HWSCH_R0_TESTBUS_318___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_318__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_318__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_319 (0x00AAA7E0) +#define WMAC0_HWSCH_R0_TESTBUS_319___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_319__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_319__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_320 (0x00AAA7E4) +#define WMAC0_HWSCH_R0_TESTBUS_320___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_320__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_320__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_321 (0x00AAA7E8) +#define WMAC0_HWSCH_R0_TESTBUS_321___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_321__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_321__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_322 (0x00AAA7EC) +#define WMAC0_HWSCH_R0_TESTBUS_322___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_322__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_322__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_323 (0x00AAA7F0) +#define WMAC0_HWSCH_R0_TESTBUS_323___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_323__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_323__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_324 (0x00AAA7F4) +#define WMAC0_HWSCH_R0_TESTBUS_324___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_324__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_324__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_325 (0x00AAA7F8) +#define WMAC0_HWSCH_R0_TESTBUS_325___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_325__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_325__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_326 (0x00AAA7FC) +#define WMAC0_HWSCH_R0_TESTBUS_326___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_326__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_326__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_327 (0x00AAA800) +#define WMAC0_HWSCH_R0_TESTBUS_327___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_327__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_327__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_328 (0x00AAA804) +#define WMAC0_HWSCH_R0_TESTBUS_328___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_328__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_328__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_329 (0x00AAA808) +#define WMAC0_HWSCH_R0_TESTBUS_329___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_329__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_329__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_330 (0x00AAA80C) +#define WMAC0_HWSCH_R0_TESTBUS_330___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_330__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_330__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_331 (0x00AAA810) +#define WMAC0_HWSCH_R0_TESTBUS_331___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_331__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_331__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_332 (0x00AAA814) +#define WMAC0_HWSCH_R0_TESTBUS_332___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_332__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_332__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_333 (0x00AAA818) +#define WMAC0_HWSCH_R0_TESTBUS_333___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_333__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_333__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_334 (0x00AAA81C) +#define WMAC0_HWSCH_R0_TESTBUS_334___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_334__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_334__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_335 (0x00AAA820) +#define WMAC0_HWSCH_R0_TESTBUS_335___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_335__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_335__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_336 (0x00AAA824) +#define WMAC0_HWSCH_R0_TESTBUS_336___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_336__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_336__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_337 (0x00AAA828) +#define WMAC0_HWSCH_R0_TESTBUS_337___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_337__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_337__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_338 (0x00AAA82C) +#define WMAC0_HWSCH_R0_TESTBUS_338___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_338__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_338__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_339 (0x00AAA830) +#define WMAC0_HWSCH_R0_TESTBUS_339___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_339__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_339__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_340 (0x00AAA834) +#define WMAC0_HWSCH_R0_TESTBUS_340___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_340__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_340__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_341 (0x00AAA838) +#define WMAC0_HWSCH_R0_TESTBUS_341___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_341__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_341__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_342 (0x00AAA83C) +#define WMAC0_HWSCH_R0_TESTBUS_342___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_342__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_342__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_343 (0x00AAA840) +#define WMAC0_HWSCH_R0_TESTBUS_343___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_343__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_343__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_344 (0x00AAA844) +#define WMAC0_HWSCH_R0_TESTBUS_344___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_344__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_344__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_345 (0x00AAA848) +#define WMAC0_HWSCH_R0_TESTBUS_345___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_345__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_345__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_346 (0x00AAA84C) +#define WMAC0_HWSCH_R0_TESTBUS_346___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_346__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_346__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_347 (0x00AAA850) +#define WMAC0_HWSCH_R0_TESTBUS_347___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_347__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_347__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_348 (0x00AAA854) +#define WMAC0_HWSCH_R0_TESTBUS_348___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_348__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_348__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_349 (0x00AAA858) +#define WMAC0_HWSCH_R0_TESTBUS_349___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_349__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_349__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_350 (0x00AAA85C) +#define WMAC0_HWSCH_R0_TESTBUS_350___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_350__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_350__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_351 (0x00AAA860) +#define WMAC0_HWSCH_R0_TESTBUS_351___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_351__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_351__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_352 (0x00AAA864) +#define WMAC0_HWSCH_R0_TESTBUS_352___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_352__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_352__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_353 (0x00AAA868) +#define WMAC0_HWSCH_R0_TESTBUS_353___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_353__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_353__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_354 (0x00AAA86C) +#define WMAC0_HWSCH_R0_TESTBUS_354___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_354__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_354__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_355 (0x00AAA870) +#define WMAC0_HWSCH_R0_TESTBUS_355___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_355__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_355__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_356 (0x00AAA874) +#define WMAC0_HWSCH_R0_TESTBUS_356___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_356__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_356__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_357 (0x00AAA878) +#define WMAC0_HWSCH_R0_TESTBUS_357___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_357__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_357__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_358 (0x00AAA87C) +#define WMAC0_HWSCH_R0_TESTBUS_358___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_358__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_358__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_359 (0x00AAA880) +#define WMAC0_HWSCH_R0_TESTBUS_359___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_359__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_359__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_360 (0x00AAA884) +#define WMAC0_HWSCH_R0_TESTBUS_360___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_360__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_360__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_361 (0x00AAA888) +#define WMAC0_HWSCH_R0_TESTBUS_361___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_361__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_361__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_362 (0x00AAA88C) +#define WMAC0_HWSCH_R0_TESTBUS_362___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_362__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_362__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_363 (0x00AAA890) +#define WMAC0_HWSCH_R0_TESTBUS_363___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_363__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_363__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_364 (0x00AAA894) +#define WMAC0_HWSCH_R0_TESTBUS_364___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_364__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_364__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_365 (0x00AAA898) +#define WMAC0_HWSCH_R0_TESTBUS_365___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_365__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_365__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_366 (0x00AAA89C) +#define WMAC0_HWSCH_R0_TESTBUS_366___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_366__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_366__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_367 (0x00AAA8A0) +#define WMAC0_HWSCH_R0_TESTBUS_367___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_367__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_367__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_368 (0x00AAA8A4) +#define WMAC0_HWSCH_R0_TESTBUS_368___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_368__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_368__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_369 (0x00AAA8A8) +#define WMAC0_HWSCH_R0_TESTBUS_369___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_369__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_369__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_370 (0x00AAA8AC) +#define WMAC0_HWSCH_R0_TESTBUS_370___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_370__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_370__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_371 (0x00AAA8B0) +#define WMAC0_HWSCH_R0_TESTBUS_371___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_371__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_371__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_372 (0x00AAA8B4) +#define WMAC0_HWSCH_R0_TESTBUS_372___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_372__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_372__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_373 (0x00AAA8B8) +#define WMAC0_HWSCH_R0_TESTBUS_373___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_373__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_373__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_374 (0x00AAA8BC) +#define WMAC0_HWSCH_R0_TESTBUS_374___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_374__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_374__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_375 (0x00AAA8C0) +#define WMAC0_HWSCH_R0_TESTBUS_375___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_375__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_375__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_376 (0x00AAA8C4) +#define WMAC0_HWSCH_R0_TESTBUS_376___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_376__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_376__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_377 (0x00AAA8C8) +#define WMAC0_HWSCH_R0_TESTBUS_377___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_377__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_377__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_378 (0x00AAA8CC) +#define WMAC0_HWSCH_R0_TESTBUS_378___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_378__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_378__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_379 (0x00AAA8D0) +#define WMAC0_HWSCH_R0_TESTBUS_379___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_379__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_379__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_380 (0x00AAA8D4) +#define WMAC0_HWSCH_R0_TESTBUS_380___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_380__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_380__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_381 (0x00AAA8D8) +#define WMAC0_HWSCH_R0_TESTBUS_381___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_381__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_381__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_382 (0x00AAA8DC) +#define WMAC0_HWSCH_R0_TESTBUS_382___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_382__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_382__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_383 (0x00AAA8E0) +#define WMAC0_HWSCH_R0_TESTBUS_383___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_383__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_383__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_384 (0x00AAA8E4) +#define WMAC0_HWSCH_R0_TESTBUS_384___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_384__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_384__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_385 (0x00AAA8E8) +#define WMAC0_HWSCH_R0_TESTBUS_385___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_385__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_385__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_386 (0x00AAA8EC) +#define WMAC0_HWSCH_R0_TESTBUS_386___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_386__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_386__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_387 (0x00AAA8F0) +#define WMAC0_HWSCH_R0_TESTBUS_387___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_387__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_387__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_388 (0x00AAA8F4) +#define WMAC0_HWSCH_R0_TESTBUS_388___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_388__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_388__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_389 (0x00AAA8F8) +#define WMAC0_HWSCH_R0_TESTBUS_389___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_389__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_389__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_390 (0x00AAA8FC) +#define WMAC0_HWSCH_R0_TESTBUS_390___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_390__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_390__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_391 (0x00AAA900) +#define WMAC0_HWSCH_R0_TESTBUS_391___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_391__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_391__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_392 (0x00AAA904) +#define WMAC0_HWSCH_R0_TESTBUS_392___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_392__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_392__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_393 (0x00AAA908) +#define WMAC0_HWSCH_R0_TESTBUS_393___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_393__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_393__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_394 (0x00AAA90C) +#define WMAC0_HWSCH_R0_TESTBUS_394___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_394__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_394__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_395 (0x00AAA910) +#define WMAC0_HWSCH_R0_TESTBUS_395___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_395__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_395__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_396 (0x00AAA914) +#define WMAC0_HWSCH_R0_TESTBUS_396___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_396__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_396__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_397 (0x00AAA918) +#define WMAC0_HWSCH_R0_TESTBUS_397___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_397__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_397__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_398 (0x00AAA91C) +#define WMAC0_HWSCH_R0_TESTBUS_398___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_398__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_398__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_399 (0x00AAA920) +#define WMAC0_HWSCH_R0_TESTBUS_399___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_399__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_399__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_400 (0x00AAA924) +#define WMAC0_HWSCH_R0_TESTBUS_400___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_400__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_400__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_401 (0x00AAA928) +#define WMAC0_HWSCH_R0_TESTBUS_401___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_401__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_401__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_402 (0x00AAA92C) +#define WMAC0_HWSCH_R0_TESTBUS_402___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_402__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_402__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_403 (0x00AAA930) +#define WMAC0_HWSCH_R0_TESTBUS_403___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_403__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_403__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_404 (0x00AAA934) +#define WMAC0_HWSCH_R0_TESTBUS_404___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_404__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_404__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_405 (0x00AAA938) +#define WMAC0_HWSCH_R0_TESTBUS_405___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_405__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_405__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_406 (0x00AAA93C) +#define WMAC0_HWSCH_R0_TESTBUS_406___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_406__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_406__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_407 (0x00AAA940) +#define WMAC0_HWSCH_R0_TESTBUS_407___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_407__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_407__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_408 (0x00AAA944) +#define WMAC0_HWSCH_R0_TESTBUS_408___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_408__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_408__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_409 (0x00AAA948) +#define WMAC0_HWSCH_R0_TESTBUS_409___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_409__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_409__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_410 (0x00AAA94C) +#define WMAC0_HWSCH_R0_TESTBUS_410___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_410__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_410__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_411 (0x00AAA950) +#define WMAC0_HWSCH_R0_TESTBUS_411___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_411__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_411__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_412 (0x00AAA954) +#define WMAC0_HWSCH_R0_TESTBUS_412___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_412__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_412__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_413 (0x00AAA958) +#define WMAC0_HWSCH_R0_TESTBUS_413___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_413__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_413__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_414 (0x00AAA95C) +#define WMAC0_HWSCH_R0_TESTBUS_414___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_414__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_414__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_415 (0x00AAA960) +#define WMAC0_HWSCH_R0_TESTBUS_415___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_415__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_415__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_416 (0x00AAA964) +#define WMAC0_HWSCH_R0_TESTBUS_416___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_416__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_416__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_417 (0x00AAA968) +#define WMAC0_HWSCH_R0_TESTBUS_417___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_417__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_417__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_418 (0x00AAA96C) +#define WMAC0_HWSCH_R0_TESTBUS_418___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_418__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_418__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_419 (0x00AAA970) +#define WMAC0_HWSCH_R0_TESTBUS_419___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_419__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_419__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_420 (0x00AAA974) +#define WMAC0_HWSCH_R0_TESTBUS_420___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_420__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_420__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_421 (0x00AAA978) +#define WMAC0_HWSCH_R0_TESTBUS_421___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_421__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_421__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_422 (0x00AAA97C) +#define WMAC0_HWSCH_R0_TESTBUS_422___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_422__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_422__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_423 (0x00AAA980) +#define WMAC0_HWSCH_R0_TESTBUS_423___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_423__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_423__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_424 (0x00AAA984) +#define WMAC0_HWSCH_R0_TESTBUS_424___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_424__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_424__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_425 (0x00AAA988) +#define WMAC0_HWSCH_R0_TESTBUS_425___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_425__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_425__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_426 (0x00AAA98C) +#define WMAC0_HWSCH_R0_TESTBUS_426___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_426__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_426__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_427 (0x00AAA990) +#define WMAC0_HWSCH_R0_TESTBUS_427___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_427__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_427__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_428 (0x00AAA994) +#define WMAC0_HWSCH_R0_TESTBUS_428___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_428__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_428__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_429 (0x00AAA998) +#define WMAC0_HWSCH_R0_TESTBUS_429___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_429__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_429__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_430 (0x00AAA99C) +#define WMAC0_HWSCH_R0_TESTBUS_430___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_430__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_430__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_431 (0x00AAA9A0) +#define WMAC0_HWSCH_R0_TESTBUS_431___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_431__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_431__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_432 (0x00AAA9A4) +#define WMAC0_HWSCH_R0_TESTBUS_432___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_432__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_432__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_433 (0x00AAA9A8) +#define WMAC0_HWSCH_R0_TESTBUS_433___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_433__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_433__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_434 (0x00AAA9AC) +#define WMAC0_HWSCH_R0_TESTBUS_434___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_434__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_434__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_435 (0x00AAA9B0) +#define WMAC0_HWSCH_R0_TESTBUS_435___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_435__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_435__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_436 (0x00AAA9B4) +#define WMAC0_HWSCH_R0_TESTBUS_436___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_436__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_436__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_437 (0x00AAA9B8) +#define WMAC0_HWSCH_R0_TESTBUS_437___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_437__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_437__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_438 (0x00AAA9BC) +#define WMAC0_HWSCH_R0_TESTBUS_438___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_438__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_438__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_439 (0x00AAA9C0) +#define WMAC0_HWSCH_R0_TESTBUS_439___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_439__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_439__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_440 (0x00AAA9C4) +#define WMAC0_HWSCH_R0_TESTBUS_440___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_440__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_440__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_441 (0x00AAA9C8) +#define WMAC0_HWSCH_R0_TESTBUS_441___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_441__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_441__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_442 (0x00AAA9CC) +#define WMAC0_HWSCH_R0_TESTBUS_442___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_442__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_442__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_443 (0x00AAA9D0) +#define WMAC0_HWSCH_R0_TESTBUS_443___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_443__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_443__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_444 (0x00AAA9D4) +#define WMAC0_HWSCH_R0_TESTBUS_444___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_444__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_444__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_445 (0x00AAA9D8) +#define WMAC0_HWSCH_R0_TESTBUS_445___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_445__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_445__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_446 (0x00AAA9DC) +#define WMAC0_HWSCH_R0_TESTBUS_446___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_446__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_446__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_447 (0x00AAA9E0) +#define WMAC0_HWSCH_R0_TESTBUS_447___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_447__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_447__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_448 (0x00AAA9E4) +#define WMAC0_HWSCH_R0_TESTBUS_448___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_448__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_448__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_449 (0x00AAA9E8) +#define WMAC0_HWSCH_R0_TESTBUS_449___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_449__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_449__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_450 (0x00AAA9EC) +#define WMAC0_HWSCH_R0_TESTBUS_450___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_450__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_450__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_451 (0x00AAA9F0) +#define WMAC0_HWSCH_R0_TESTBUS_451___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_451__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_451__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_452 (0x00AAA9F4) +#define WMAC0_HWSCH_R0_TESTBUS_452___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_452__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_452__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_453 (0x00AAA9F8) +#define WMAC0_HWSCH_R0_TESTBUS_453___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_453__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_453__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_454 (0x00AAA9FC) +#define WMAC0_HWSCH_R0_TESTBUS_454___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_454__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_454__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_455 (0x00AAAA00) +#define WMAC0_HWSCH_R0_TESTBUS_455___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_455__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_455__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_456 (0x00AAAA04) +#define WMAC0_HWSCH_R0_TESTBUS_456___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_456__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_456__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_457 (0x00AAAA08) +#define WMAC0_HWSCH_R0_TESTBUS_457___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_457__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_457__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_458 (0x00AAAA0C) +#define WMAC0_HWSCH_R0_TESTBUS_458___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_458__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_458__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_459 (0x00AAAA10) +#define WMAC0_HWSCH_R0_TESTBUS_459___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_459__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_459__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_460 (0x00AAAA14) +#define WMAC0_HWSCH_R0_TESTBUS_460___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_460__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_460__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_461 (0x00AAAA18) +#define WMAC0_HWSCH_R0_TESTBUS_461___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_461__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_461__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_462 (0x00AAAA1C) +#define WMAC0_HWSCH_R0_TESTBUS_462___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_462__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_462__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_463 (0x00AAAA20) +#define WMAC0_HWSCH_R0_TESTBUS_463___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_463__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_463__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_464 (0x00AAAA24) +#define WMAC0_HWSCH_R0_TESTBUS_464___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_464__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_464__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_465 (0x00AAAA28) +#define WMAC0_HWSCH_R0_TESTBUS_465___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_465__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_465__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_466 (0x00AAAA2C) +#define WMAC0_HWSCH_R0_TESTBUS_466___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_466__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_466__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_467 (0x00AAAA30) +#define WMAC0_HWSCH_R0_TESTBUS_467___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_467__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_467__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_468 (0x00AAAA34) +#define WMAC0_HWSCH_R0_TESTBUS_468___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_468__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_468__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_469 (0x00AAAA38) +#define WMAC0_HWSCH_R0_TESTBUS_469___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_469__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_469__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_470 (0x00AAAA3C) +#define WMAC0_HWSCH_R0_TESTBUS_470___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_470__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_470__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_471 (0x00AAAA40) +#define WMAC0_HWSCH_R0_TESTBUS_471___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_471__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_471__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_472 (0x00AAAA44) +#define WMAC0_HWSCH_R0_TESTBUS_472___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_472__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_472__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_473 (0x00AAAA48) +#define WMAC0_HWSCH_R0_TESTBUS_473___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_473__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_473__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_474 (0x00AAAA4C) +#define WMAC0_HWSCH_R0_TESTBUS_474___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_474__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_474__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_475 (0x00AAAA50) +#define WMAC0_HWSCH_R0_TESTBUS_475___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_475__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_475__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_476 (0x00AAAA54) +#define WMAC0_HWSCH_R0_TESTBUS_476___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_476__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_476__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_477 (0x00AAAA58) +#define WMAC0_HWSCH_R0_TESTBUS_477___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_477__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_477__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_478 (0x00AAAA5C) +#define WMAC0_HWSCH_R0_TESTBUS_478___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_478__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_478__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_479 (0x00AAAA60) +#define WMAC0_HWSCH_R0_TESTBUS_479___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_479__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_479__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_480 (0x00AAAA64) +#define WMAC0_HWSCH_R0_TESTBUS_480___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_480__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_480__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_481 (0x00AAAA68) +#define WMAC0_HWSCH_R0_TESTBUS_481___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_481__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_481__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_482 (0x00AAAA6C) +#define WMAC0_HWSCH_R0_TESTBUS_482___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_482__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_482__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_483 (0x00AAAA70) +#define WMAC0_HWSCH_R0_TESTBUS_483___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_483__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_483__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_484 (0x00AAAA74) +#define WMAC0_HWSCH_R0_TESTBUS_484___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_484__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_484__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_485 (0x00AAAA78) +#define WMAC0_HWSCH_R0_TESTBUS_485___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_485__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_485__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_486 (0x00AAAA7C) +#define WMAC0_HWSCH_R0_TESTBUS_486___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_486__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_486__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_487 (0x00AAAA80) +#define WMAC0_HWSCH_R0_TESTBUS_487___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_487__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_487__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_488 (0x00AAAA84) +#define WMAC0_HWSCH_R0_TESTBUS_488___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_488__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_488__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_489 (0x00AAAA88) +#define WMAC0_HWSCH_R0_TESTBUS_489___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_489__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_489__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_490 (0x00AAAA8C) +#define WMAC0_HWSCH_R0_TESTBUS_490___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_490__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_490__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_491 (0x00AAAA90) +#define WMAC0_HWSCH_R0_TESTBUS_491___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_491__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_491__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_492 (0x00AAAA94) +#define WMAC0_HWSCH_R0_TESTBUS_492___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_492__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_492__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_493 (0x00AAAA98) +#define WMAC0_HWSCH_R0_TESTBUS_493___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_493__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_493__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_494 (0x00AAAA9C) +#define WMAC0_HWSCH_R0_TESTBUS_494___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_494__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_494__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_495 (0x00AAAAA0) +#define WMAC0_HWSCH_R0_TESTBUS_495___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_495__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_495__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_496 (0x00AAAAA4) +#define WMAC0_HWSCH_R0_TESTBUS_496___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_496__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_496__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_497 (0x00AAAAA8) +#define WMAC0_HWSCH_R0_TESTBUS_497___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_497__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_497__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_498 (0x00AAAAAC) +#define WMAC0_HWSCH_R0_TESTBUS_498___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_498__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_498__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_499 (0x00AAAAB0) +#define WMAC0_HWSCH_R0_TESTBUS_499___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_499__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_499__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_500 (0x00AAAAB4) +#define WMAC0_HWSCH_R0_TESTBUS_500___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_500__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_500__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_501 (0x00AAAAB8) +#define WMAC0_HWSCH_R0_TESTBUS_501___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_501__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_501__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_502 (0x00AAAABC) +#define WMAC0_HWSCH_R0_TESTBUS_502___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_502__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_502__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_503 (0x00AAAAC0) +#define WMAC0_HWSCH_R0_TESTBUS_503___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_503__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_503__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_504 (0x00AAAAC4) +#define WMAC0_HWSCH_R0_TESTBUS_504___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_504__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_504__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_505 (0x00AAAAC8) +#define WMAC0_HWSCH_R0_TESTBUS_505___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_505__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_505__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_506 (0x00AAAACC) +#define WMAC0_HWSCH_R0_TESTBUS_506___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_506__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_506__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_507 (0x00AAAAD0) +#define WMAC0_HWSCH_R0_TESTBUS_507___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_507__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_507__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_508 (0x00AAAAD4) +#define WMAC0_HWSCH_R0_TESTBUS_508___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_508__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_508__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_509 (0x00AAAAD8) +#define WMAC0_HWSCH_R0_TESTBUS_509___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_509__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_509__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_510 (0x00AAAADC) +#define WMAC0_HWSCH_R0_TESTBUS_510___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_510__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_510__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_511 (0x00AAAAE0) +#define WMAC0_HWSCH_R0_TESTBUS_511___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_511__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_511__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_512 (0x00AAAAE4) +#define WMAC0_HWSCH_R0_TESTBUS_512___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_512__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_512__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_513 (0x00AAAAE8) +#define WMAC0_HWSCH_R0_TESTBUS_513___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_513__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_513__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_514 (0x00AAAAEC) +#define WMAC0_HWSCH_R0_TESTBUS_514___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_514__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_514__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_515 (0x00AAAAF0) +#define WMAC0_HWSCH_R0_TESTBUS_515___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_515__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_515__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_516 (0x00AAAAF4) +#define WMAC0_HWSCH_R0_TESTBUS_516___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_516__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_516__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_517 (0x00AAAAF8) +#define WMAC0_HWSCH_R0_TESTBUS_517___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_517__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_517__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_518 (0x00AAAAFC) +#define WMAC0_HWSCH_R0_TESTBUS_518___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_518__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_518__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_519 (0x00AAAB00) +#define WMAC0_HWSCH_R0_TESTBUS_519___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_519__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_519__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_520 (0x00AAAB04) +#define WMAC0_HWSCH_R0_TESTBUS_520___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_520__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_520__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_521 (0x00AAAB08) +#define WMAC0_HWSCH_R0_TESTBUS_521___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_521__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_521__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_522 (0x00AAAB0C) +#define WMAC0_HWSCH_R0_TESTBUS_522___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_522__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_522__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_523 (0x00AAAB10) +#define WMAC0_HWSCH_R0_TESTBUS_523___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_523__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_523__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_524 (0x00AAAB14) +#define WMAC0_HWSCH_R0_TESTBUS_524___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_524__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_524__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_525 (0x00AAAB18) +#define WMAC0_HWSCH_R0_TESTBUS_525___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_525__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_525__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_526 (0x00AAAB1C) +#define WMAC0_HWSCH_R0_TESTBUS_526___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_526__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_526__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_527 (0x00AAAB20) +#define WMAC0_HWSCH_R0_TESTBUS_527___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_527__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_527__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_528 (0x00AAAB24) +#define WMAC0_HWSCH_R0_TESTBUS_528___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_528__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_528__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_529 (0x00AAAB28) +#define WMAC0_HWSCH_R0_TESTBUS_529___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_529__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_529__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_530 (0x00AAAB2C) +#define WMAC0_HWSCH_R0_TESTBUS_530___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_530__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_530__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_531 (0x00AAAB30) +#define WMAC0_HWSCH_R0_TESTBUS_531___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_531__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_531__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_532 (0x00AAAB34) +#define WMAC0_HWSCH_R0_TESTBUS_532___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_532__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_532__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_533 (0x00AAAB38) +#define WMAC0_HWSCH_R0_TESTBUS_533___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_533__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_533__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_534 (0x00AAAB3C) +#define WMAC0_HWSCH_R0_TESTBUS_534___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_534__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_534__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_535 (0x00AAAB40) +#define WMAC0_HWSCH_R0_TESTBUS_535___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_535__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_535__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_536 (0x00AAAB44) +#define WMAC0_HWSCH_R0_TESTBUS_536___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_536__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_536__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_537 (0x00AAAB48) +#define WMAC0_HWSCH_R0_TESTBUS_537___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_537__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_537__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_538 (0x00AAAB4C) +#define WMAC0_HWSCH_R0_TESTBUS_538___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_538__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_538__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_539 (0x00AAAB50) +#define WMAC0_HWSCH_R0_TESTBUS_539___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_539__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_539__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_540 (0x00AAAB54) +#define WMAC0_HWSCH_R0_TESTBUS_540___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_540__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_540__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_541 (0x00AAAB58) +#define WMAC0_HWSCH_R0_TESTBUS_541___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_541__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_541__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_542 (0x00AAAB5C) +#define WMAC0_HWSCH_R0_TESTBUS_542___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_542__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_542__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_543 (0x00AAAB60) +#define WMAC0_HWSCH_R0_TESTBUS_543___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_543__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_543__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_544 (0x00AAAB64) +#define WMAC0_HWSCH_R0_TESTBUS_544___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_544__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_544__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_545 (0x00AAAB68) +#define WMAC0_HWSCH_R0_TESTBUS_545___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_545__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_545__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_546 (0x00AAAB6C) +#define WMAC0_HWSCH_R0_TESTBUS_546___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_546__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_546__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_547 (0x00AAAB70) +#define WMAC0_HWSCH_R0_TESTBUS_547___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_547__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_547__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_548 (0x00AAAB74) +#define WMAC0_HWSCH_R0_TESTBUS_548___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_548__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_548__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_549 (0x00AAAB78) +#define WMAC0_HWSCH_R0_TESTBUS_549___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_549__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_549__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_550 (0x00AAAB7C) +#define WMAC0_HWSCH_R0_TESTBUS_550___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_550__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_550__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_551 (0x00AAAB80) +#define WMAC0_HWSCH_R0_TESTBUS_551___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_551__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_551__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_552 (0x00AAAB84) +#define WMAC0_HWSCH_R0_TESTBUS_552___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_552__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_552__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_553 (0x00AAAB88) +#define WMAC0_HWSCH_R0_TESTBUS_553___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_553__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_553__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_554 (0x00AAAB8C) +#define WMAC0_HWSCH_R0_TESTBUS_554___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_554__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_554__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_555 (0x00AAAB90) +#define WMAC0_HWSCH_R0_TESTBUS_555___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_555__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_555__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_556 (0x00AAAB94) +#define WMAC0_HWSCH_R0_TESTBUS_556___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_556__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_556__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_557 (0x00AAAB98) +#define WMAC0_HWSCH_R0_TESTBUS_557___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_557__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_557__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_558 (0x00AAAB9C) +#define WMAC0_HWSCH_R0_TESTBUS_558___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_558__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_558__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_559 (0x00AAABA0) +#define WMAC0_HWSCH_R0_TESTBUS_559___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_559__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_559__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_560 (0x00AAABA4) +#define WMAC0_HWSCH_R0_TESTBUS_560___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_560__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_560__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_561 (0x00AAABA8) +#define WMAC0_HWSCH_R0_TESTBUS_561___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_561__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_561__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_562 (0x00AAABAC) +#define WMAC0_HWSCH_R0_TESTBUS_562___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_562__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_562__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_563 (0x00AAABB0) +#define WMAC0_HWSCH_R0_TESTBUS_563___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_563__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_563__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_564 (0x00AAABB4) +#define WMAC0_HWSCH_R0_TESTBUS_564___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_564__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_564__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_565 (0x00AAABB8) +#define WMAC0_HWSCH_R0_TESTBUS_565___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_565__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_565__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_566 (0x00AAABBC) +#define WMAC0_HWSCH_R0_TESTBUS_566___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_566__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_566__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_567 (0x00AAABC0) +#define WMAC0_HWSCH_R0_TESTBUS_567___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_567__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_567__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_568 (0x00AAABC4) +#define WMAC0_HWSCH_R0_TESTBUS_568___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_568__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_568__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_569 (0x00AAABC8) +#define WMAC0_HWSCH_R0_TESTBUS_569___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_569__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_569__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_570 (0x00AAABCC) +#define WMAC0_HWSCH_R0_TESTBUS_570___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_570__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_570__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_571 (0x00AAABD0) +#define WMAC0_HWSCH_R0_TESTBUS_571___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_571__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_571__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_572 (0x00AAABD4) +#define WMAC0_HWSCH_R0_TESTBUS_572___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_572__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_572__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_573 (0x00AAABD8) +#define WMAC0_HWSCH_R0_TESTBUS_573___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_573__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_573__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_574 (0x00AAABDC) +#define WMAC0_HWSCH_R0_TESTBUS_574___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_574__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_574__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_575 (0x00AAABE0) +#define WMAC0_HWSCH_R0_TESTBUS_575___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_575__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_575__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_576 (0x00AAABE4) +#define WMAC0_HWSCH_R0_TESTBUS_576___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_576__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_576__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_577 (0x00AAABE8) +#define WMAC0_HWSCH_R0_TESTBUS_577___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_577__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_577__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_578 (0x00AAABEC) +#define WMAC0_HWSCH_R0_TESTBUS_578___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_578__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_578__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_579 (0x00AAABF0) +#define WMAC0_HWSCH_R0_TESTBUS_579___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_579__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_579__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_580 (0x00AAABF4) +#define WMAC0_HWSCH_R0_TESTBUS_580___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_580__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_580__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_581 (0x00AAABF8) +#define WMAC0_HWSCH_R0_TESTBUS_581___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_581__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_581__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_582 (0x00AAABFC) +#define WMAC0_HWSCH_R0_TESTBUS_582___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_582__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_582__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_583 (0x00AAAC00) +#define WMAC0_HWSCH_R0_TESTBUS_583___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_583__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_583__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_584 (0x00AAAC04) +#define WMAC0_HWSCH_R0_TESTBUS_584___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_584__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_584__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_585 (0x00AAAC08) +#define WMAC0_HWSCH_R0_TESTBUS_585___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_585__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_585__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_586 (0x00AAAC0C) +#define WMAC0_HWSCH_R0_TESTBUS_586___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_586__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_586__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_587 (0x00AAAC10) +#define WMAC0_HWSCH_R0_TESTBUS_587___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_587__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_587__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_588 (0x00AAAC14) +#define WMAC0_HWSCH_R0_TESTBUS_588___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_588__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_588__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_589 (0x00AAAC18) +#define WMAC0_HWSCH_R0_TESTBUS_589___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_589__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_589__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_590 (0x00AAAC1C) +#define WMAC0_HWSCH_R0_TESTBUS_590___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_590__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_590__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_591 (0x00AAAC20) +#define WMAC0_HWSCH_R0_TESTBUS_591___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_591__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_591__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_592 (0x00AAAC24) +#define WMAC0_HWSCH_R0_TESTBUS_592___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_592__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_592__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_593 (0x00AAAC28) +#define WMAC0_HWSCH_R0_TESTBUS_593___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_593__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_593__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_594 (0x00AAAC2C) +#define WMAC0_HWSCH_R0_TESTBUS_594___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_594__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_594__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_595 (0x00AAAC30) +#define WMAC0_HWSCH_R0_TESTBUS_595___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_595__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_595__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_596 (0x00AAAC34) +#define WMAC0_HWSCH_R0_TESTBUS_596___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_596__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_596__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_597 (0x00AAAC38) +#define WMAC0_HWSCH_R0_TESTBUS_597___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_597__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_597__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_598 (0x00AAAC3C) +#define WMAC0_HWSCH_R0_TESTBUS_598___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_598__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_598__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_599 (0x00AAAC40) +#define WMAC0_HWSCH_R0_TESTBUS_599___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_599__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_599__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_600 (0x00AAAC44) +#define WMAC0_HWSCH_R0_TESTBUS_600___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_600__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_600__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_601 (0x00AAAC48) +#define WMAC0_HWSCH_R0_TESTBUS_601___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_601__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_601__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_602 (0x00AAAC4C) +#define WMAC0_HWSCH_R0_TESTBUS_602___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_602__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_602__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_603 (0x00AAAC50) +#define WMAC0_HWSCH_R0_TESTBUS_603___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_603__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_603__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_604 (0x00AAAC54) +#define WMAC0_HWSCH_R0_TESTBUS_604___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_604__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_604__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_605 (0x00AAAC58) +#define WMAC0_HWSCH_R0_TESTBUS_605___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_605__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_605__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_606 (0x00AAAC5C) +#define WMAC0_HWSCH_R0_TESTBUS_606___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_606__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_606__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_607 (0x00AAAC60) +#define WMAC0_HWSCH_R0_TESTBUS_607___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_607__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_607__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_608 (0x00AAAC64) +#define WMAC0_HWSCH_R0_TESTBUS_608___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_608__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_608__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_609 (0x00AAAC68) +#define WMAC0_HWSCH_R0_TESTBUS_609___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_609__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_609__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_610 (0x00AAAC6C) +#define WMAC0_HWSCH_R0_TESTBUS_610___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_610__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_610__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_611 (0x00AAAC70) +#define WMAC0_HWSCH_R0_TESTBUS_611___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_611__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_611__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_612 (0x00AAAC74) +#define WMAC0_HWSCH_R0_TESTBUS_612___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_612__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_612__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_613 (0x00AAAC78) +#define WMAC0_HWSCH_R0_TESTBUS_613___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_613__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_613__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_614 (0x00AAAC7C) +#define WMAC0_HWSCH_R0_TESTBUS_614___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_614__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_614__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_615 (0x00AAAC80) +#define WMAC0_HWSCH_R0_TESTBUS_615___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_615__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_615__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_616 (0x00AAAC84) +#define WMAC0_HWSCH_R0_TESTBUS_616___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_616__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_616__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_617 (0x00AAAC88) +#define WMAC0_HWSCH_R0_TESTBUS_617___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_617__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_617__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_618 (0x00AAAC8C) +#define WMAC0_HWSCH_R0_TESTBUS_618___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_618__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_618__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_619 (0x00AAAC90) +#define WMAC0_HWSCH_R0_TESTBUS_619___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_619__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_619__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_620 (0x00AAAC94) +#define WMAC0_HWSCH_R0_TESTBUS_620___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_620__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_620__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_621 (0x00AAAC98) +#define WMAC0_HWSCH_R0_TESTBUS_621___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_621__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_621__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_622 (0x00AAAC9C) +#define WMAC0_HWSCH_R0_TESTBUS_622___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_622__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_622__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_623 (0x00AAACA0) +#define WMAC0_HWSCH_R0_TESTBUS_623___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_623__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_623__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_624 (0x00AAACA4) +#define WMAC0_HWSCH_R0_TESTBUS_624___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_624__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_624__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_625 (0x00AAACA8) +#define WMAC0_HWSCH_R0_TESTBUS_625___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_625__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_625__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_626 (0x00AAACAC) +#define WMAC0_HWSCH_R0_TESTBUS_626___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_626__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_626__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_627 (0x00AAACB0) +#define WMAC0_HWSCH_R0_TESTBUS_627___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_627__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_627__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_628 (0x00AAACB4) +#define WMAC0_HWSCH_R0_TESTBUS_628___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_628__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_628__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_629 (0x00AAACB8) +#define WMAC0_HWSCH_R0_TESTBUS_629___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_629__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_629__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_630 (0x00AAACBC) +#define WMAC0_HWSCH_R0_TESTBUS_630___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_630__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_630__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_631 (0x00AAACC0) +#define WMAC0_HWSCH_R0_TESTBUS_631___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_631__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_631__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_632 (0x00AAACC4) +#define WMAC0_HWSCH_R0_TESTBUS_632___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_632__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_632__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_633 (0x00AAACC8) +#define WMAC0_HWSCH_R0_TESTBUS_633___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_633__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_633__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_634 (0x00AAACCC) +#define WMAC0_HWSCH_R0_TESTBUS_634___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_634__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_634__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_635 (0x00AAACD0) +#define WMAC0_HWSCH_R0_TESTBUS_635___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_635__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_635__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_636 (0x00AAACD4) +#define WMAC0_HWSCH_R0_TESTBUS_636___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_636__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_636__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_637 (0x00AAACD8) +#define WMAC0_HWSCH_R0_TESTBUS_637___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_637__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_637__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_638 (0x00AAACDC) +#define WMAC0_HWSCH_R0_TESTBUS_638___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_638__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_638__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_639 (0x00AAACE0) +#define WMAC0_HWSCH_R0_TESTBUS_639___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_639__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_639__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_640 (0x00AAACE4) +#define WMAC0_HWSCH_R0_TESTBUS_640___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_640__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_640__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_641 (0x00AAACE8) +#define WMAC0_HWSCH_R0_TESTBUS_641___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_641__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_641__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_642 (0x00AAACEC) +#define WMAC0_HWSCH_R0_TESTBUS_642___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_642__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_642__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_643 (0x00AAACF0) +#define WMAC0_HWSCH_R0_TESTBUS_643___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_643__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_643__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_644 (0x00AAACF4) +#define WMAC0_HWSCH_R0_TESTBUS_644___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_644__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_644__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_645 (0x00AAACF8) +#define WMAC0_HWSCH_R0_TESTBUS_645___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_645__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_645__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_646 (0x00AAACFC) +#define WMAC0_HWSCH_R0_TESTBUS_646___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_646__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_646__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_647 (0x00AAAD00) +#define WMAC0_HWSCH_R0_TESTBUS_647___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_647__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_647__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_648 (0x00AAAD04) +#define WMAC0_HWSCH_R0_TESTBUS_648___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_648__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_648__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_649 (0x00AAAD08) +#define WMAC0_HWSCH_R0_TESTBUS_649___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_649__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_649__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_650 (0x00AAAD0C) +#define WMAC0_HWSCH_R0_TESTBUS_650___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_650__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_650__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_651 (0x00AAAD10) +#define WMAC0_HWSCH_R0_TESTBUS_651___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_651__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_651__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_652 (0x00AAAD14) +#define WMAC0_HWSCH_R0_TESTBUS_652___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_652__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_652__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_653 (0x00AAAD18) +#define WMAC0_HWSCH_R0_TESTBUS_653___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_653__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_653__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_654 (0x00AAAD1C) +#define WMAC0_HWSCH_R0_TESTBUS_654___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_654__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_654__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_655 (0x00AAAD20) +#define WMAC0_HWSCH_R0_TESTBUS_655___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_655__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_655__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_656 (0x00AAAD24) +#define WMAC0_HWSCH_R0_TESTBUS_656___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_656__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_656__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_657 (0x00AAAD28) +#define WMAC0_HWSCH_R0_TESTBUS_657___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_657__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_657__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_658 (0x00AAAD2C) +#define WMAC0_HWSCH_R0_TESTBUS_658___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_658__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_658__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_659 (0x00AAAD30) +#define WMAC0_HWSCH_R0_TESTBUS_659___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_659__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_659__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_660 (0x00AAAD34) +#define WMAC0_HWSCH_R0_TESTBUS_660___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_660__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_660__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_661 (0x00AAAD38) +#define WMAC0_HWSCH_R0_TESTBUS_661___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_661__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_661__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_662 (0x00AAAD3C) +#define WMAC0_HWSCH_R0_TESTBUS_662___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_662__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_662__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_663 (0x00AAAD40) +#define WMAC0_HWSCH_R0_TESTBUS_663___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_663__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_663__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_664 (0x00AAAD44) +#define WMAC0_HWSCH_R0_TESTBUS_664___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_664__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_664__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_665 (0x00AAAD48) +#define WMAC0_HWSCH_R0_TESTBUS_665___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_665__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_665__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_666 (0x00AAAD4C) +#define WMAC0_HWSCH_R0_TESTBUS_666___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_666__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_666__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_667 (0x00AAAD50) +#define WMAC0_HWSCH_R0_TESTBUS_667___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_667__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_667__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_668 (0x00AAAD54) +#define WMAC0_HWSCH_R0_TESTBUS_668___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_668__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_668__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_669 (0x00AAAD58) +#define WMAC0_HWSCH_R0_TESTBUS_669___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_669__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_669__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_670 (0x00AAAD5C) +#define WMAC0_HWSCH_R0_TESTBUS_670___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_670__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_670__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_671 (0x00AAAD60) +#define WMAC0_HWSCH_R0_TESTBUS_671___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_671__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_671__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_672 (0x00AAAD64) +#define WMAC0_HWSCH_R0_TESTBUS_672___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_672__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_672__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_673 (0x00AAAD68) +#define WMAC0_HWSCH_R0_TESTBUS_673___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_673__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_673__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_674 (0x00AAAD6C) +#define WMAC0_HWSCH_R0_TESTBUS_674___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_674__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_674__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_675 (0x00AAAD70) +#define WMAC0_HWSCH_R0_TESTBUS_675___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_675__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_675__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_676 (0x00AAAD74) +#define WMAC0_HWSCH_R0_TESTBUS_676___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_676__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_676__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_677 (0x00AAAD78) +#define WMAC0_HWSCH_R0_TESTBUS_677___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_677__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_677__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_678 (0x00AAAD7C) +#define WMAC0_HWSCH_R0_TESTBUS_678___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_678__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_678__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_679 (0x00AAAD80) +#define WMAC0_HWSCH_R0_TESTBUS_679___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_679__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_679__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_680 (0x00AAAD84) +#define WMAC0_HWSCH_R0_TESTBUS_680___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_680__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_680__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_681 (0x00AAAD88) +#define WMAC0_HWSCH_R0_TESTBUS_681___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_681__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_681__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_682 (0x00AAAD8C) +#define WMAC0_HWSCH_R0_TESTBUS_682___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_682__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_682__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_683 (0x00AAAD90) +#define WMAC0_HWSCH_R0_TESTBUS_683___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_683__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_683__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_684 (0x00AAAD94) +#define WMAC0_HWSCH_R0_TESTBUS_684___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_684__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_684__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_685 (0x00AAAD98) +#define WMAC0_HWSCH_R0_TESTBUS_685___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_685__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_685__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_686 (0x00AAAD9C) +#define WMAC0_HWSCH_R0_TESTBUS_686___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_686__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_686__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_687 (0x00AAADA0) +#define WMAC0_HWSCH_R0_TESTBUS_687___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_687__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_687__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_688 (0x00AAADA4) +#define WMAC0_HWSCH_R0_TESTBUS_688___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_688__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_688__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_689 (0x00AAADA8) +#define WMAC0_HWSCH_R0_TESTBUS_689___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_689__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_689__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_690 (0x00AAADAC) +#define WMAC0_HWSCH_R0_TESTBUS_690___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_690__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_690__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_691 (0x00AAADB0) +#define WMAC0_HWSCH_R0_TESTBUS_691___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_691__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_691__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_692 (0x00AAADB4) +#define WMAC0_HWSCH_R0_TESTBUS_692___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_692__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_692__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_693 (0x00AAADB8) +#define WMAC0_HWSCH_R0_TESTBUS_693___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_693__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_693__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_694 (0x00AAADBC) +#define WMAC0_HWSCH_R0_TESTBUS_694___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_694__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_694__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_695 (0x00AAADC0) +#define WMAC0_HWSCH_R0_TESTBUS_695___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_695__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_695__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_696 (0x00AAADC4) +#define WMAC0_HWSCH_R0_TESTBUS_696___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_696__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_696__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_697 (0x00AAADC8) +#define WMAC0_HWSCH_R0_TESTBUS_697___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_697__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_697__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_698 (0x00AAADCC) +#define WMAC0_HWSCH_R0_TESTBUS_698___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_698__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_698__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_699 (0x00AAADD0) +#define WMAC0_HWSCH_R0_TESTBUS_699___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_699__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_699__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_700 (0x00AAADD4) +#define WMAC0_HWSCH_R0_TESTBUS_700___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_700__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_700__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_701 (0x00AAADD8) +#define WMAC0_HWSCH_R0_TESTBUS_701___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_701__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_701__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_702 (0x00AAADDC) +#define WMAC0_HWSCH_R0_TESTBUS_702___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_702__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_702__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_703 (0x00AAADE0) +#define WMAC0_HWSCH_R0_TESTBUS_703___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_703__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_703__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_704 (0x00AAADE4) +#define WMAC0_HWSCH_R0_TESTBUS_704___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_704__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_704__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_705 (0x00AAADE8) +#define WMAC0_HWSCH_R0_TESTBUS_705___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_705__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_705__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_706 (0x00AAADEC) +#define WMAC0_HWSCH_R0_TESTBUS_706___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_706__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_706__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_707 (0x00AAADF0) +#define WMAC0_HWSCH_R0_TESTBUS_707___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_707__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_707__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_708 (0x00AAADF4) +#define WMAC0_HWSCH_R0_TESTBUS_708___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_708__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_708__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_709 (0x00AAADF8) +#define WMAC0_HWSCH_R0_TESTBUS_709___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_709__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_709__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_710 (0x00AAADFC) +#define WMAC0_HWSCH_R0_TESTBUS_710___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_710__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_710__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_711 (0x00AAAE00) +#define WMAC0_HWSCH_R0_TESTBUS_711___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_711__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_711__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_712 (0x00AAAE04) +#define WMAC0_HWSCH_R0_TESTBUS_712___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_712__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_712__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_713 (0x00AAAE08) +#define WMAC0_HWSCH_R0_TESTBUS_713___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_713__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_713__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_714 (0x00AAAE0C) +#define WMAC0_HWSCH_R0_TESTBUS_714___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_714__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_714__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_715 (0x00AAAE10) +#define WMAC0_HWSCH_R0_TESTBUS_715___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_715__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_715__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_716 (0x00AAAE14) +#define WMAC0_HWSCH_R0_TESTBUS_716___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_716__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_716__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_717 (0x00AAAE18) +#define WMAC0_HWSCH_R0_TESTBUS_717___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_717__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_717__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_718 (0x00AAAE1C) +#define WMAC0_HWSCH_R0_TESTBUS_718___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_718__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_718__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_719 (0x00AAAE20) +#define WMAC0_HWSCH_R0_TESTBUS_719___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_719__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_719__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_720 (0x00AAAE24) +#define WMAC0_HWSCH_R0_TESTBUS_720___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_720__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_720__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_721 (0x00AAAE28) +#define WMAC0_HWSCH_R0_TESTBUS_721___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_721__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_721__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_722 (0x00AAAE2C) +#define WMAC0_HWSCH_R0_TESTBUS_722___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_722__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_722__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_723 (0x00AAAE30) +#define WMAC0_HWSCH_R0_TESTBUS_723___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_723__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_723__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_724 (0x00AAAE34) +#define WMAC0_HWSCH_R0_TESTBUS_724___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_724__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_724__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_725 (0x00AAAE38) +#define WMAC0_HWSCH_R0_TESTBUS_725___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_725__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_725__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_726 (0x00AAAE3C) +#define WMAC0_HWSCH_R0_TESTBUS_726___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_726__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_726__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_727 (0x00AAAE40) +#define WMAC0_HWSCH_R0_TESTBUS_727___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_727__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_727__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_728 (0x00AAAE44) +#define WMAC0_HWSCH_R0_TESTBUS_728___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_728__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_728__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_729 (0x00AAAE48) +#define WMAC0_HWSCH_R0_TESTBUS_729___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_729__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_729__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_730 (0x00AAAE4C) +#define WMAC0_HWSCH_R0_TESTBUS_730___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_730__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_730__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_731 (0x00AAAE50) +#define WMAC0_HWSCH_R0_TESTBUS_731___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_731__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_731__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_732 (0x00AAAE54) +#define WMAC0_HWSCH_R0_TESTBUS_732___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_732__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_732__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_733 (0x00AAAE58) +#define WMAC0_HWSCH_R0_TESTBUS_733___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_733__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_733__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_734 (0x00AAAE5C) +#define WMAC0_HWSCH_R0_TESTBUS_734___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_734__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_734__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_735 (0x00AAAE60) +#define WMAC0_HWSCH_R0_TESTBUS_735___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_735__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_735__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_736 (0x00AAAE64) +#define WMAC0_HWSCH_R0_TESTBUS_736___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_736__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_736__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_737 (0x00AAAE68) +#define WMAC0_HWSCH_R0_TESTBUS_737___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_737__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_737__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_738 (0x00AAAE6C) +#define WMAC0_HWSCH_R0_TESTBUS_738___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_738__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_738__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_739 (0x00AAAE70) +#define WMAC0_HWSCH_R0_TESTBUS_739___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_739__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_739__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_740 (0x00AAAE74) +#define WMAC0_HWSCH_R0_TESTBUS_740___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_740__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_740__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_741 (0x00AAAE78) +#define WMAC0_HWSCH_R0_TESTBUS_741___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_741__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_741__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_742 (0x00AAAE7C) +#define WMAC0_HWSCH_R0_TESTBUS_742___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_742__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_742__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_743 (0x00AAAE80) +#define WMAC0_HWSCH_R0_TESTBUS_743___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_743__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_743__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_744 (0x00AAAE84) +#define WMAC0_HWSCH_R0_TESTBUS_744___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_744__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_744__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_745 (0x00AAAE88) +#define WMAC0_HWSCH_R0_TESTBUS_745___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_745__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_745__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_746 (0x00AAAE8C) +#define WMAC0_HWSCH_R0_TESTBUS_746___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_746__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_746__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_747 (0x00AAAE90) +#define WMAC0_HWSCH_R0_TESTBUS_747___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_747__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_747__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_748 (0x00AAAE94) +#define WMAC0_HWSCH_R0_TESTBUS_748___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_748__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_748__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_749 (0x00AAAE98) +#define WMAC0_HWSCH_R0_TESTBUS_749___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_749__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_749__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_750 (0x00AAAE9C) +#define WMAC0_HWSCH_R0_TESTBUS_750___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_750__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_750__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_751 (0x00AAAEA0) +#define WMAC0_HWSCH_R0_TESTBUS_751___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_751__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_751__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_752 (0x00AAAEA4) +#define WMAC0_HWSCH_R0_TESTBUS_752___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_752__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_752__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_753 (0x00AAAEA8) +#define WMAC0_HWSCH_R0_TESTBUS_753___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_753__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_753__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_754 (0x00AAAEAC) +#define WMAC0_HWSCH_R0_TESTBUS_754___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_754__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_754__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_755 (0x00AAAEB0) +#define WMAC0_HWSCH_R0_TESTBUS_755___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_755__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_755__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_756 (0x00AAAEB4) +#define WMAC0_HWSCH_R0_TESTBUS_756___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_756__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_756__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_757 (0x00AAAEB8) +#define WMAC0_HWSCH_R0_TESTBUS_757___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_757__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_757__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_758 (0x00AAAEBC) +#define WMAC0_HWSCH_R0_TESTBUS_758___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_758__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_758__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_759 (0x00AAAEC0) +#define WMAC0_HWSCH_R0_TESTBUS_759___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_759__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_759__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_760 (0x00AAAEC4) +#define WMAC0_HWSCH_R0_TESTBUS_760___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_760__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_760__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_761 (0x00AAAEC8) +#define WMAC0_HWSCH_R0_TESTBUS_761___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_761__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_761__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_762 (0x00AAAECC) +#define WMAC0_HWSCH_R0_TESTBUS_762___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_762__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_762__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_763 (0x00AAAED0) +#define WMAC0_HWSCH_R0_TESTBUS_763___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_763__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_763__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_764 (0x00AAAED4) +#define WMAC0_HWSCH_R0_TESTBUS_764___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_764__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_764__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_765 (0x00AAAED8) +#define WMAC0_HWSCH_R0_TESTBUS_765___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_765__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_765__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_766 (0x00AAAEDC) +#define WMAC0_HWSCH_R0_TESTBUS_766___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_766__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_766__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_767 (0x00AAAEE0) +#define WMAC0_HWSCH_R0_TESTBUS_767___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_767__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_767__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_768 (0x00AAAEE4) +#define WMAC0_HWSCH_R0_TESTBUS_768___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_768__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_768__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_769 (0x00AAAEE8) +#define WMAC0_HWSCH_R0_TESTBUS_769___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_769__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_769__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_770 (0x00AAAEEC) +#define WMAC0_HWSCH_R0_TESTBUS_770___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_770__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_770__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_771 (0x00AAAEF0) +#define WMAC0_HWSCH_R0_TESTBUS_771___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_771__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_771__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_772 (0x00AAAEF4) +#define WMAC0_HWSCH_R0_TESTBUS_772___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_772__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_772__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_773 (0x00AAAEF8) +#define WMAC0_HWSCH_R0_TESTBUS_773___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_773__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_773__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_774 (0x00AAAEFC) +#define WMAC0_HWSCH_R0_TESTBUS_774___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_774__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_774__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_775 (0x00AAAF00) +#define WMAC0_HWSCH_R0_TESTBUS_775___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_775__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_775__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_776 (0x00AAAF04) +#define WMAC0_HWSCH_R0_TESTBUS_776___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_776__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_776__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_777 (0x00AAAF08) +#define WMAC0_HWSCH_R0_TESTBUS_777___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_777__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_777__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_778 (0x00AAAF0C) +#define WMAC0_HWSCH_R0_TESTBUS_778___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_778__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_778__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_779 (0x00AAAF10) +#define WMAC0_HWSCH_R0_TESTBUS_779___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_779__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_779__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_780 (0x00AAAF14) +#define WMAC0_HWSCH_R0_TESTBUS_780___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_780__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_780__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_781 (0x00AAAF18) +#define WMAC0_HWSCH_R0_TESTBUS_781___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_781__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_781__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_782 (0x00AAAF1C) +#define WMAC0_HWSCH_R0_TESTBUS_782___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_782__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_782__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_783 (0x00AAAF20) +#define WMAC0_HWSCH_R0_TESTBUS_783___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_783__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_783__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_784 (0x00AAAF24) +#define WMAC0_HWSCH_R0_TESTBUS_784___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_784__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_784__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_785 (0x00AAAF28) +#define WMAC0_HWSCH_R0_TESTBUS_785___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_785__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_785__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_786 (0x00AAAF2C) +#define WMAC0_HWSCH_R0_TESTBUS_786___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_786__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_786__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_787 (0x00AAAF30) +#define WMAC0_HWSCH_R0_TESTBUS_787___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_787__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_787__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_788 (0x00AAAF34) +#define WMAC0_HWSCH_R0_TESTBUS_788___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_788__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_788__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_789 (0x00AAAF38) +#define WMAC0_HWSCH_R0_TESTBUS_789___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_789__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_789__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_790 (0x00AAAF3C) +#define WMAC0_HWSCH_R0_TESTBUS_790___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_790__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_790__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_791 (0x00AAAF40) +#define WMAC0_HWSCH_R0_TESTBUS_791___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_791__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_791__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_792 (0x00AAAF44) +#define WMAC0_HWSCH_R0_TESTBUS_792___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_792__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_792__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_793 (0x00AAAF48) +#define WMAC0_HWSCH_R0_TESTBUS_793___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_793__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_793__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_794 (0x00AAAF4C) +#define WMAC0_HWSCH_R0_TESTBUS_794___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_794__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_794__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_795 (0x00AAAF50) +#define WMAC0_HWSCH_R0_TESTBUS_795___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_795__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_795__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_796 (0x00AAAF54) +#define WMAC0_HWSCH_R0_TESTBUS_796___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_796__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_796__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_797 (0x00AAAF58) +#define WMAC0_HWSCH_R0_TESTBUS_797___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_797__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_797__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_798 (0x00AAAF5C) +#define WMAC0_HWSCH_R0_TESTBUS_798___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_798__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_798__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_799 (0x00AAAF60) +#define WMAC0_HWSCH_R0_TESTBUS_799___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_799__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_799__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_800 (0x00AAAF64) +#define WMAC0_HWSCH_R0_TESTBUS_800___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_800__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_800__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_801 (0x00AAAF68) +#define WMAC0_HWSCH_R0_TESTBUS_801___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_801__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_801__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_802 (0x00AAAF6C) +#define WMAC0_HWSCH_R0_TESTBUS_802___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_802__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_802__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_803 (0x00AAAF70) +#define WMAC0_HWSCH_R0_TESTBUS_803___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_803__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_803__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_804 (0x00AAAF74) +#define WMAC0_HWSCH_R0_TESTBUS_804___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_804__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_804__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_805 (0x00AAAF78) +#define WMAC0_HWSCH_R0_TESTBUS_805___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_805__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_805__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_806 (0x00AAAF7C) +#define WMAC0_HWSCH_R0_TESTBUS_806___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_806__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_806__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_807 (0x00AAAF80) +#define WMAC0_HWSCH_R0_TESTBUS_807___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_807__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_807__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_808 (0x00AAAF84) +#define WMAC0_HWSCH_R0_TESTBUS_808___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_808__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_808__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_809 (0x00AAAF88) +#define WMAC0_HWSCH_R0_TESTBUS_809___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_809__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_809__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_810 (0x00AAAF8C) +#define WMAC0_HWSCH_R0_TESTBUS_810___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_810__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_810__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_811 (0x00AAAF90) +#define WMAC0_HWSCH_R0_TESTBUS_811___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_811__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_811__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_812 (0x00AAAF94) +#define WMAC0_HWSCH_R0_TESTBUS_812___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_812__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_812__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_813 (0x00AAAF98) +#define WMAC0_HWSCH_R0_TESTBUS_813___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_813__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_813__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_814 (0x00AAAF9C) +#define WMAC0_HWSCH_R0_TESTBUS_814___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_814__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_814__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_815 (0x00AAAFA0) +#define WMAC0_HWSCH_R0_TESTBUS_815___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_815__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_815__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_816 (0x00AAAFA4) +#define WMAC0_HWSCH_R0_TESTBUS_816___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_816__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_816__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_817 (0x00AAAFA8) +#define WMAC0_HWSCH_R0_TESTBUS_817___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_817__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_817__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_818 (0x00AAAFAC) +#define WMAC0_HWSCH_R0_TESTBUS_818___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_818__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_818__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_819 (0x00AAAFB0) +#define WMAC0_HWSCH_R0_TESTBUS_819___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_819__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_819__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_820 (0x00AAAFB4) +#define WMAC0_HWSCH_R0_TESTBUS_820___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_820__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_820__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_821 (0x00AAAFB8) +#define WMAC0_HWSCH_R0_TESTBUS_821___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_821__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_821__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_822 (0x00AAAFBC) +#define WMAC0_HWSCH_R0_TESTBUS_822___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_822__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_822__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_823 (0x00AAAFC0) +#define WMAC0_HWSCH_R0_TESTBUS_823___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_823__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_823__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_824 (0x00AAAFC4) +#define WMAC0_HWSCH_R0_TESTBUS_824___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_824__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_824__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_825 (0x00AAAFC8) +#define WMAC0_HWSCH_R0_TESTBUS_825___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_825__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_825__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_826 (0x00AAAFCC) +#define WMAC0_HWSCH_R0_TESTBUS_826___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_826__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_826__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_827 (0x00AAAFD0) +#define WMAC0_HWSCH_R0_TESTBUS_827___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_827__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_827__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_828 (0x00AAAFD4) +#define WMAC0_HWSCH_R0_TESTBUS_828___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_828__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_828__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_829 (0x00AAAFD8) +#define WMAC0_HWSCH_R0_TESTBUS_829___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_829__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_829__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_830 (0x00AAAFDC) +#define WMAC0_HWSCH_R0_TESTBUS_830___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_830__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_830__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_831 (0x00AAAFE0) +#define WMAC0_HWSCH_R0_TESTBUS_831___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_831__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_831__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_832 (0x00AAAFE4) +#define WMAC0_HWSCH_R0_TESTBUS_832___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_832__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_832__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_833 (0x00AAAFE8) +#define WMAC0_HWSCH_R0_TESTBUS_833___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_833__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_833__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_834 (0x00AAAFEC) +#define WMAC0_HWSCH_R0_TESTBUS_834___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_834__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_834__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_835 (0x00AAAFF0) +#define WMAC0_HWSCH_R0_TESTBUS_835___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_835__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_835__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_836 (0x00AAAFF4) +#define WMAC0_HWSCH_R0_TESTBUS_836___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_836__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_836__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_837 (0x00AAAFF8) +#define WMAC0_HWSCH_R0_TESTBUS_837___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_837__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_837__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_838 (0x00AAAFFC) +#define WMAC0_HWSCH_R0_TESTBUS_838___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_838__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_838__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_839 (0x00AAB000) +#define WMAC0_HWSCH_R0_TESTBUS_839___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_839__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_839__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_840 (0x00AAB004) +#define WMAC0_HWSCH_R0_TESTBUS_840___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_840__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_840__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_841 (0x00AAB008) +#define WMAC0_HWSCH_R0_TESTBUS_841___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_841__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_841__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_842 (0x00AAB00C) +#define WMAC0_HWSCH_R0_TESTBUS_842___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_842__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_842__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_843 (0x00AAB010) +#define WMAC0_HWSCH_R0_TESTBUS_843___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_843__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_843__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_844 (0x00AAB014) +#define WMAC0_HWSCH_R0_TESTBUS_844___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_844__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_844__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_845 (0x00AAB018) +#define WMAC0_HWSCH_R0_TESTBUS_845___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_845__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_845__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_846 (0x00AAB01C) +#define WMAC0_HWSCH_R0_TESTBUS_846___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_846__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_846__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_847 (0x00AAB020) +#define WMAC0_HWSCH_R0_TESTBUS_847___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_847__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_847__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_848 (0x00AAB024) +#define WMAC0_HWSCH_R0_TESTBUS_848___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_848__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_848__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_849 (0x00AAB028) +#define WMAC0_HWSCH_R0_TESTBUS_849___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_849__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_849__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_850 (0x00AAB02C) +#define WMAC0_HWSCH_R0_TESTBUS_850___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_850__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_850__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_851 (0x00AAB030) +#define WMAC0_HWSCH_R0_TESTBUS_851___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_851__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_851__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_852 (0x00AAB034) +#define WMAC0_HWSCH_R0_TESTBUS_852___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_852__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_852__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_853 (0x00AAB038) +#define WMAC0_HWSCH_R0_TESTBUS_853___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_853__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_853__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_854 (0x00AAB03C) +#define WMAC0_HWSCH_R0_TESTBUS_854___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_854__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_854__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_855 (0x00AAB040) +#define WMAC0_HWSCH_R0_TESTBUS_855___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_855__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_855__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_856 (0x00AAB044) +#define WMAC0_HWSCH_R0_TESTBUS_856___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_856__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_856__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_857 (0x00AAB048) +#define WMAC0_HWSCH_R0_TESTBUS_857___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_857__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_857__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_858 (0x00AAB04C) +#define WMAC0_HWSCH_R0_TESTBUS_858___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_858__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_858__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_859 (0x00AAB050) +#define WMAC0_HWSCH_R0_TESTBUS_859___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_859__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_859__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_860 (0x00AAB054) +#define WMAC0_HWSCH_R0_TESTBUS_860___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_860__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_860__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_861 (0x00AAB058) +#define WMAC0_HWSCH_R0_TESTBUS_861___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_861__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_861__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_862 (0x00AAB05C) +#define WMAC0_HWSCH_R0_TESTBUS_862___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_862__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_862__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_863 (0x00AAB060) +#define WMAC0_HWSCH_R0_TESTBUS_863___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_863__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_863__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_864 (0x00AAB064) +#define WMAC0_HWSCH_R0_TESTBUS_864___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_864__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_864__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_865 (0x00AAB068) +#define WMAC0_HWSCH_R0_TESTBUS_865___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_865__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_865__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_866 (0x00AAB06C) +#define WMAC0_HWSCH_R0_TESTBUS_866___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_866__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_866__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_867 (0x00AAB070) +#define WMAC0_HWSCH_R0_TESTBUS_867___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_867__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_867__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_868 (0x00AAB074) +#define WMAC0_HWSCH_R0_TESTBUS_868___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_868__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_868__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_869 (0x00AAB078) +#define WMAC0_HWSCH_R0_TESTBUS_869___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_869__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_869__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_870 (0x00AAB07C) +#define WMAC0_HWSCH_R0_TESTBUS_870___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_870__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_870__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_871 (0x00AAB080) +#define WMAC0_HWSCH_R0_TESTBUS_871___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_871__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_871__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_872 (0x00AAB084) +#define WMAC0_HWSCH_R0_TESTBUS_872___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_872__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_872__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_873 (0x00AAB088) +#define WMAC0_HWSCH_R0_TESTBUS_873___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_873__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_873__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_874 (0x00AAB08C) +#define WMAC0_HWSCH_R0_TESTBUS_874___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_874__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_874__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_875 (0x00AAB090) +#define WMAC0_HWSCH_R0_TESTBUS_875___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_875__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_875__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_876 (0x00AAB094) +#define WMAC0_HWSCH_R0_TESTBUS_876___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_876__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_876__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_877 (0x00AAB098) +#define WMAC0_HWSCH_R0_TESTBUS_877___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_877__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_877__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_878 (0x00AAB09C) +#define WMAC0_HWSCH_R0_TESTBUS_878___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_878__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_878__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_879 (0x00AAB0A0) +#define WMAC0_HWSCH_R0_TESTBUS_879___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_879__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_879__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_880 (0x00AAB0A4) +#define WMAC0_HWSCH_R0_TESTBUS_880___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_880__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_880__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_881 (0x00AAB0A8) +#define WMAC0_HWSCH_R0_TESTBUS_881___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_881__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_881__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_882 (0x00AAB0AC) +#define WMAC0_HWSCH_R0_TESTBUS_882___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_882__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_882__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_883 (0x00AAB0B0) +#define WMAC0_HWSCH_R0_TESTBUS_883___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_883__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_883__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_884 (0x00AAB0B4) +#define WMAC0_HWSCH_R0_TESTBUS_884___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_884__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_884__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_885 (0x00AAB0B8) +#define WMAC0_HWSCH_R0_TESTBUS_885___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_885__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_885__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_886 (0x00AAB0BC) +#define WMAC0_HWSCH_R0_TESTBUS_886___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_886__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_886__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_887 (0x00AAB0C0) +#define WMAC0_HWSCH_R0_TESTBUS_887___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_887__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_887__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_888 (0x00AAB0C4) +#define WMAC0_HWSCH_R0_TESTBUS_888___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_888__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_888__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_889 (0x00AAB0C8) +#define WMAC0_HWSCH_R0_TESTBUS_889___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_889__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_889__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_890 (0x00AAB0CC) +#define WMAC0_HWSCH_R0_TESTBUS_890___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_890__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_890__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_891 (0x00AAB0D0) +#define WMAC0_HWSCH_R0_TESTBUS_891___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_891__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_891__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_892 (0x00AAB0D4) +#define WMAC0_HWSCH_R0_TESTBUS_892___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_892__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_892__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_893 (0x00AAB0D8) +#define WMAC0_HWSCH_R0_TESTBUS_893___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_893__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_893__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_894 (0x00AAB0DC) +#define WMAC0_HWSCH_R0_TESTBUS_894___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_894__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_894__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_895 (0x00AAB0E0) +#define WMAC0_HWSCH_R0_TESTBUS_895___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_895__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_895__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_896 (0x00AAB0E4) +#define WMAC0_HWSCH_R0_TESTBUS_896___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_896__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_896__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_897 (0x00AAB0E8) +#define WMAC0_HWSCH_R0_TESTBUS_897___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_897__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_897__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_898 (0x00AAB0EC) +#define WMAC0_HWSCH_R0_TESTBUS_898___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_898__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_898__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_899 (0x00AAB0F0) +#define WMAC0_HWSCH_R0_TESTBUS_899___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_899__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_899__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_900 (0x00AAB0F4) +#define WMAC0_HWSCH_R0_TESTBUS_900___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_900__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_900__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_901 (0x00AAB0F8) +#define WMAC0_HWSCH_R0_TESTBUS_901___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_901__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_901__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_902 (0x00AAB0FC) +#define WMAC0_HWSCH_R0_TESTBUS_902___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_902__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_902__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_903 (0x00AAB100) +#define WMAC0_HWSCH_R0_TESTBUS_903___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_903__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_903__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_904 (0x00AAB104) +#define WMAC0_HWSCH_R0_TESTBUS_904___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_904__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_904__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_905 (0x00AAB108) +#define WMAC0_HWSCH_R0_TESTBUS_905___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_905__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_905__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_906 (0x00AAB10C) +#define WMAC0_HWSCH_R0_TESTBUS_906___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_906__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_906__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_907 (0x00AAB110) +#define WMAC0_HWSCH_R0_TESTBUS_907___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_907__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_907__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_908 (0x00AAB114) +#define WMAC0_HWSCH_R0_TESTBUS_908___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_908__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_908__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_909 (0x00AAB118) +#define WMAC0_HWSCH_R0_TESTBUS_909___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_909__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_909__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_910 (0x00AAB11C) +#define WMAC0_HWSCH_R0_TESTBUS_910___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_910__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_910__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_911 (0x00AAB120) +#define WMAC0_HWSCH_R0_TESTBUS_911___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_911__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_911__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_912 (0x00AAB124) +#define WMAC0_HWSCH_R0_TESTBUS_912___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_912__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_912__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_913 (0x00AAB128) +#define WMAC0_HWSCH_R0_TESTBUS_913___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_913__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_913__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_914 (0x00AAB12C) +#define WMAC0_HWSCH_R0_TESTBUS_914___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_914__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_914__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_915 (0x00AAB130) +#define WMAC0_HWSCH_R0_TESTBUS_915___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_915__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_915__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_916 (0x00AAB134) +#define WMAC0_HWSCH_R0_TESTBUS_916___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_916__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_916__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_917 (0x00AAB138) +#define WMAC0_HWSCH_R0_TESTBUS_917___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_917__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_917__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_918 (0x00AAB13C) +#define WMAC0_HWSCH_R0_TESTBUS_918___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_918__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_918__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_919 (0x00AAB140) +#define WMAC0_HWSCH_R0_TESTBUS_919___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_919__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_919__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_920 (0x00AAB144) +#define WMAC0_HWSCH_R0_TESTBUS_920___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_920__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_920__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_921 (0x00AAB148) +#define WMAC0_HWSCH_R0_TESTBUS_921___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_921__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_921__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_922 (0x00AAB14C) +#define WMAC0_HWSCH_R0_TESTBUS_922___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_922__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_922__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_923 (0x00AAB150) +#define WMAC0_HWSCH_R0_TESTBUS_923___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_923__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_923__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_924 (0x00AAB154) +#define WMAC0_HWSCH_R0_TESTBUS_924___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_924__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_924__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_925 (0x00AAB158) +#define WMAC0_HWSCH_R0_TESTBUS_925___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_925__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_925__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_926 (0x00AAB15C) +#define WMAC0_HWSCH_R0_TESTBUS_926___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_926__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_926__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_927 (0x00AAB160) +#define WMAC0_HWSCH_R0_TESTBUS_927___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_927__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_927__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_928 (0x00AAB164) +#define WMAC0_HWSCH_R0_TESTBUS_928___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_928__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_928__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_929 (0x00AAB168) +#define WMAC0_HWSCH_R0_TESTBUS_929___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_929__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_929__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_930 (0x00AAB16C) +#define WMAC0_HWSCH_R0_TESTBUS_930___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_930__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_930__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_931 (0x00AAB170) +#define WMAC0_HWSCH_R0_TESTBUS_931___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_931__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_931__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_932 (0x00AAB174) +#define WMAC0_HWSCH_R0_TESTBUS_932___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_932__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_932__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_933 (0x00AAB178) +#define WMAC0_HWSCH_R0_TESTBUS_933___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_933__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_933__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_934 (0x00AAB17C) +#define WMAC0_HWSCH_R0_TESTBUS_934___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_934__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_934__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_935 (0x00AAB180) +#define WMAC0_HWSCH_R0_TESTBUS_935___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_935__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_935__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_936 (0x00AAB184) +#define WMAC0_HWSCH_R0_TESTBUS_936___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_936__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_936__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_937 (0x00AAB188) +#define WMAC0_HWSCH_R0_TESTBUS_937___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_937__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_937__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_938 (0x00AAB18C) +#define WMAC0_HWSCH_R0_TESTBUS_938___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_938__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_938__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_939 (0x00AAB190) +#define WMAC0_HWSCH_R0_TESTBUS_939___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_939__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_939__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_940 (0x00AAB194) +#define WMAC0_HWSCH_R0_TESTBUS_940___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_940__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_940__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_941 (0x00AAB198) +#define WMAC0_HWSCH_R0_TESTBUS_941___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_941__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_941__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_942 (0x00AAB19C) +#define WMAC0_HWSCH_R0_TESTBUS_942___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_942__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_942__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_943 (0x00AAB1A0) +#define WMAC0_HWSCH_R0_TESTBUS_943___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_943__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_943__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_944 (0x00AAB1A4) +#define WMAC0_HWSCH_R0_TESTBUS_944___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_944__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_944__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_945 (0x00AAB1A8) +#define WMAC0_HWSCH_R0_TESTBUS_945___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_945__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_945__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_946 (0x00AAB1AC) +#define WMAC0_HWSCH_R0_TESTBUS_946___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_946__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_946__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_947 (0x00AAB1B0) +#define WMAC0_HWSCH_R0_TESTBUS_947___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_947__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_947__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_948 (0x00AAB1B4) +#define WMAC0_HWSCH_R0_TESTBUS_948___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_948__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_948__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_949 (0x00AAB1B8) +#define WMAC0_HWSCH_R0_TESTBUS_949___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_949__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_949__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_950 (0x00AAB1BC) +#define WMAC0_HWSCH_R0_TESTBUS_950___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_950__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_950__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_951 (0x00AAB1C0) +#define WMAC0_HWSCH_R0_TESTBUS_951___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_951__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_951__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_952 (0x00AAB1C4) +#define WMAC0_HWSCH_R0_TESTBUS_952___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_952__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_952__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_953 (0x00AAB1C8) +#define WMAC0_HWSCH_R0_TESTBUS_953___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_953__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_953__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_954 (0x00AAB1CC) +#define WMAC0_HWSCH_R0_TESTBUS_954___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_954__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_954__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_955 (0x00AAB1D0) +#define WMAC0_HWSCH_R0_TESTBUS_955___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_955__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_955__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_956 (0x00AAB1D4) +#define WMAC0_HWSCH_R0_TESTBUS_956___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_956__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_956__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_957 (0x00AAB1D8) +#define WMAC0_HWSCH_R0_TESTBUS_957___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_957__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_957__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_958 (0x00AAB1DC) +#define WMAC0_HWSCH_R0_TESTBUS_958___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_958__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_958__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_959 (0x00AAB1E0) +#define WMAC0_HWSCH_R0_TESTBUS_959___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_959__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_959__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_960 (0x00AAB1E4) +#define WMAC0_HWSCH_R0_TESTBUS_960___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_960__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_960__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_961 (0x00AAB1E8) +#define WMAC0_HWSCH_R0_TESTBUS_961___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_961__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_961__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_962 (0x00AAB1EC) +#define WMAC0_HWSCH_R0_TESTBUS_962___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_962__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_962__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_963 (0x00AAB1F0) +#define WMAC0_HWSCH_R0_TESTBUS_963___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_963__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_963__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_964 (0x00AAB1F4) +#define WMAC0_HWSCH_R0_TESTBUS_964___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_964__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_964__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_965 (0x00AAB1F8) +#define WMAC0_HWSCH_R0_TESTBUS_965___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_965__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_965__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_966 (0x00AAB1FC) +#define WMAC0_HWSCH_R0_TESTBUS_966___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_966__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_966__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_967 (0x00AAB200) +#define WMAC0_HWSCH_R0_TESTBUS_967___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_967__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_967__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_968 (0x00AAB204) +#define WMAC0_HWSCH_R0_TESTBUS_968___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_968__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_968__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_969 (0x00AAB208) +#define WMAC0_HWSCH_R0_TESTBUS_969___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_969__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_969__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_970 (0x00AAB20C) +#define WMAC0_HWSCH_R0_TESTBUS_970___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_970__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_970__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_971 (0x00AAB210) +#define WMAC0_HWSCH_R0_TESTBUS_971___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_971__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_971__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_972 (0x00AAB214) +#define WMAC0_HWSCH_R0_TESTBUS_972___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_972__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_972__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_973 (0x00AAB218) +#define WMAC0_HWSCH_R0_TESTBUS_973___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_973__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_973__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_974 (0x00AAB21C) +#define WMAC0_HWSCH_R0_TESTBUS_974___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_974__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_974__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_975 (0x00AAB220) +#define WMAC0_HWSCH_R0_TESTBUS_975___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_975__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_975__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_976 (0x00AAB224) +#define WMAC0_HWSCH_R0_TESTBUS_976___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_976__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_976__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_977 (0x00AAB228) +#define WMAC0_HWSCH_R0_TESTBUS_977___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_977__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_977__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_978 (0x00AAB22C) +#define WMAC0_HWSCH_R0_TESTBUS_978___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_978__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_978__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_979 (0x00AAB230) +#define WMAC0_HWSCH_R0_TESTBUS_979___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_979__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_979__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_980 (0x00AAB234) +#define WMAC0_HWSCH_R0_TESTBUS_980___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_980__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_980__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_981 (0x00AAB238) +#define WMAC0_HWSCH_R0_TESTBUS_981___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_981__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_981__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_982 (0x00AAB23C) +#define WMAC0_HWSCH_R0_TESTBUS_982___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_982__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_982__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_983 (0x00AAB240) +#define WMAC0_HWSCH_R0_TESTBUS_983___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_983__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_983__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_984 (0x00AAB244) +#define WMAC0_HWSCH_R0_TESTBUS_984___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_984__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_984__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_985 (0x00AAB248) +#define WMAC0_HWSCH_R0_TESTBUS_985___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_985__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_985__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_986 (0x00AAB24C) +#define WMAC0_HWSCH_R0_TESTBUS_986___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_986__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_986__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_987 (0x00AAB250) +#define WMAC0_HWSCH_R0_TESTBUS_987___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_987__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_987__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_988 (0x00AAB254) +#define WMAC0_HWSCH_R0_TESTBUS_988___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_988__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_988__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_989 (0x00AAB258) +#define WMAC0_HWSCH_R0_TESTBUS_989___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_989__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_989__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_990 (0x00AAB25C) +#define WMAC0_HWSCH_R0_TESTBUS_990___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_990__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_990__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_991 (0x00AAB260) +#define WMAC0_HWSCH_R0_TESTBUS_991___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_991__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_991__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_992 (0x00AAB264) +#define WMAC0_HWSCH_R0_TESTBUS_992___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_992__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_992__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_993 (0x00AAB268) +#define WMAC0_HWSCH_R0_TESTBUS_993___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_993__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_993__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_994 (0x00AAB26C) +#define WMAC0_HWSCH_R0_TESTBUS_994___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_994__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_994__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_995 (0x00AAB270) +#define WMAC0_HWSCH_R0_TESTBUS_995___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_995__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_995__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_996 (0x00AAB274) +#define WMAC0_HWSCH_R0_TESTBUS_996___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_996__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_996__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_997 (0x00AAB278) +#define WMAC0_HWSCH_R0_TESTBUS_997___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_997__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_997__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_998 (0x00AAB27C) +#define WMAC0_HWSCH_R0_TESTBUS_998___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_998__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_998__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_999 (0x00AAB280) +#define WMAC0_HWSCH_R0_TESTBUS_999___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_999__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_999__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1000 (0x00AAB284) +#define WMAC0_HWSCH_R0_TESTBUS_1000___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1000__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1000__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1001 (0x00AAB288) +#define WMAC0_HWSCH_R0_TESTBUS_1001___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1001__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1001__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1002 (0x00AAB28C) +#define WMAC0_HWSCH_R0_TESTBUS_1002___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1002__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1002__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1003 (0x00AAB290) +#define WMAC0_HWSCH_R0_TESTBUS_1003___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1003__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1003__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1004 (0x00AAB294) +#define WMAC0_HWSCH_R0_TESTBUS_1004___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1004__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1004__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1005 (0x00AAB298) +#define WMAC0_HWSCH_R0_TESTBUS_1005___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1005__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1005__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1006 (0x00AAB29C) +#define WMAC0_HWSCH_R0_TESTBUS_1006___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1006__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1006__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1007 (0x00AAB2A0) +#define WMAC0_HWSCH_R0_TESTBUS_1007___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1007__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1007__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1008 (0x00AAB2A4) +#define WMAC0_HWSCH_R0_TESTBUS_1008___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1008__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1008__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1009 (0x00AAB2A8) +#define WMAC0_HWSCH_R0_TESTBUS_1009___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1009__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1009__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1010 (0x00AAB2AC) +#define WMAC0_HWSCH_R0_TESTBUS_1010___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1010__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1010__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1011 (0x00AAB2B0) +#define WMAC0_HWSCH_R0_TESTBUS_1011___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1011__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1011__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1012 (0x00AAB2B4) +#define WMAC0_HWSCH_R0_TESTBUS_1012___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1012__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1012__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1013 (0x00AAB2B8) +#define WMAC0_HWSCH_R0_TESTBUS_1013___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1013__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1013__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1014 (0x00AAB2BC) +#define WMAC0_HWSCH_R0_TESTBUS_1014___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1014__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1014__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1015 (0x00AAB2C0) +#define WMAC0_HWSCH_R0_TESTBUS_1015___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1015__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1015__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1016 (0x00AAB2C4) +#define WMAC0_HWSCH_R0_TESTBUS_1016___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1016__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1016__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1017 (0x00AAB2C8) +#define WMAC0_HWSCH_R0_TESTBUS_1017___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1017__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1017__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1018 (0x00AAB2CC) +#define WMAC0_HWSCH_R0_TESTBUS_1018___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1018__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1018__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1019 (0x00AAB2D0) +#define WMAC0_HWSCH_R0_TESTBUS_1019___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1019__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1019__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1020 (0x00AAB2D4) +#define WMAC0_HWSCH_R0_TESTBUS_1020___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1020__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1020__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1021 (0x00AAB2D8) +#define WMAC0_HWSCH_R0_TESTBUS_1021___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1021__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1021__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1022 (0x00AAB2DC) +#define WMAC0_HWSCH_R0_TESTBUS_1022___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1022__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1022__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1023 (0x00AAB2E0) +#define WMAC0_HWSCH_R0_TESTBUS_1023___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1023__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1023__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1024 (0x00AAB2E4) +#define WMAC0_HWSCH_R0_TESTBUS_1024___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1024__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1024__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1025 (0x00AAB2E8) +#define WMAC0_HWSCH_R0_TESTBUS_1025___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1025__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1025__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1026 (0x00AAB2EC) +#define WMAC0_HWSCH_R0_TESTBUS_1026___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1026__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1026__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1027 (0x00AAB2F0) +#define WMAC0_HWSCH_R0_TESTBUS_1027___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1027__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1027__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1028 (0x00AAB2F4) +#define WMAC0_HWSCH_R0_TESTBUS_1028___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1028__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1028__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1029 (0x00AAB2F8) +#define WMAC0_HWSCH_R0_TESTBUS_1029___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1029__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1029__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1030 (0x00AAB2FC) +#define WMAC0_HWSCH_R0_TESTBUS_1030___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1030__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1030__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1031 (0x00AAB300) +#define WMAC0_HWSCH_R0_TESTBUS_1031___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1031__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1031__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1032 (0x00AAB304) +#define WMAC0_HWSCH_R0_TESTBUS_1032___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1032__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1032__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1033 (0x00AAB308) +#define WMAC0_HWSCH_R0_TESTBUS_1033___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1033__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1033__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1034 (0x00AAB30C) +#define WMAC0_HWSCH_R0_TESTBUS_1034___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1034__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1034__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1035 (0x00AAB310) +#define WMAC0_HWSCH_R0_TESTBUS_1035___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1035__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1035__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1036 (0x00AAB314) +#define WMAC0_HWSCH_R0_TESTBUS_1036___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1036__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1036__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1037 (0x00AAB318) +#define WMAC0_HWSCH_R0_TESTBUS_1037___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1037__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1037__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1038 (0x00AAB31C) +#define WMAC0_HWSCH_R0_TESTBUS_1038___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1038__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1038__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1039 (0x00AAB320) +#define WMAC0_HWSCH_R0_TESTBUS_1039___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1039__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1039__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1040 (0x00AAB324) +#define WMAC0_HWSCH_R0_TESTBUS_1040___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1040__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1040__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1041 (0x00AAB328) +#define WMAC0_HWSCH_R0_TESTBUS_1041___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1041__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1041__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1042 (0x00AAB32C) +#define WMAC0_HWSCH_R0_TESTBUS_1042___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1042__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1042__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1043 (0x00AAB330) +#define WMAC0_HWSCH_R0_TESTBUS_1043___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1043__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1043__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1044 (0x00AAB334) +#define WMAC0_HWSCH_R0_TESTBUS_1044___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1044__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1044__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1045 (0x00AAB338) +#define WMAC0_HWSCH_R0_TESTBUS_1045___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1045__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1045__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1046 (0x00AAB33C) +#define WMAC0_HWSCH_R0_TESTBUS_1046___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1046__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1046__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1047 (0x00AAB340) +#define WMAC0_HWSCH_R0_TESTBUS_1047___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1047__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1047__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1048 (0x00AAB344) +#define WMAC0_HWSCH_R0_TESTBUS_1048___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1048__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1048__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1049 (0x00AAB348) +#define WMAC0_HWSCH_R0_TESTBUS_1049___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1049__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1049__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1050 (0x00AAB34C) +#define WMAC0_HWSCH_R0_TESTBUS_1050___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1050__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1050__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1051 (0x00AAB350) +#define WMAC0_HWSCH_R0_TESTBUS_1051___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1051__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1051__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1052 (0x00AAB354) +#define WMAC0_HWSCH_R0_TESTBUS_1052___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1052__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1052__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1053 (0x00AAB358) +#define WMAC0_HWSCH_R0_TESTBUS_1053___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1053__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1053__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1054 (0x00AAB35C) +#define WMAC0_HWSCH_R0_TESTBUS_1054___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1054__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1054__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1055 (0x00AAB360) +#define WMAC0_HWSCH_R0_TESTBUS_1055___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1055__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1055__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1056 (0x00AAB364) +#define WMAC0_HWSCH_R0_TESTBUS_1056___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1056__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1056__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1057 (0x00AAB368) +#define WMAC0_HWSCH_R0_TESTBUS_1057___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1057__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1057__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1058 (0x00AAB36C) +#define WMAC0_HWSCH_R0_TESTBUS_1058___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1058__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1058__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1059 (0x00AAB370) +#define WMAC0_HWSCH_R0_TESTBUS_1059___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1059__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1059__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1060 (0x00AAB374) +#define WMAC0_HWSCH_R0_TESTBUS_1060___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1060__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1060__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1061 (0x00AAB378) +#define WMAC0_HWSCH_R0_TESTBUS_1061___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1061__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1061__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1062 (0x00AAB37C) +#define WMAC0_HWSCH_R0_TESTBUS_1062___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1062__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1062__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1063 (0x00AAB380) +#define WMAC0_HWSCH_R0_TESTBUS_1063___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1063__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1063__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1064 (0x00AAB384) +#define WMAC0_HWSCH_R0_TESTBUS_1064___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1064__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1064__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1065 (0x00AAB388) +#define WMAC0_HWSCH_R0_TESTBUS_1065___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1065__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1065__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1066 (0x00AAB38C) +#define WMAC0_HWSCH_R0_TESTBUS_1066___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1066__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1066__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1067 (0x00AAB390) +#define WMAC0_HWSCH_R0_TESTBUS_1067___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1067__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1067__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1068 (0x00AAB394) +#define WMAC0_HWSCH_R0_TESTBUS_1068___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1068__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1068__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1069 (0x00AAB398) +#define WMAC0_HWSCH_R0_TESTBUS_1069___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1069__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1069__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1070 (0x00AAB39C) +#define WMAC0_HWSCH_R0_TESTBUS_1070___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1070__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1070__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1071 (0x00AAB3A0) +#define WMAC0_HWSCH_R0_TESTBUS_1071___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1071__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1071__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1072 (0x00AAB3A4) +#define WMAC0_HWSCH_R0_TESTBUS_1072___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1072__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1072__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1073 (0x00AAB3A8) +#define WMAC0_HWSCH_R0_TESTBUS_1073___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1073__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1073__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1074 (0x00AAB3AC) +#define WMAC0_HWSCH_R0_TESTBUS_1074___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1074__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1074__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1075 (0x00AAB3B0) +#define WMAC0_HWSCH_R0_TESTBUS_1075___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1075__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1075__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1076 (0x00AAB3B4) +#define WMAC0_HWSCH_R0_TESTBUS_1076___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1076__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1076__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1077 (0x00AAB3B8) +#define WMAC0_HWSCH_R0_TESTBUS_1077___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1077__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1077__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1078 (0x00AAB3BC) +#define WMAC0_HWSCH_R0_TESTBUS_1078___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1078__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1078__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1079 (0x00AAB3C0) +#define WMAC0_HWSCH_R0_TESTBUS_1079___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1079__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1079__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1080 (0x00AAB3C4) +#define WMAC0_HWSCH_R0_TESTBUS_1080___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1080__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1080__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1081 (0x00AAB3C8) +#define WMAC0_HWSCH_R0_TESTBUS_1081___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1081__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1081__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1082 (0x00AAB3CC) +#define WMAC0_HWSCH_R0_TESTBUS_1082___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1082__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1082__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1083 (0x00AAB3D0) +#define WMAC0_HWSCH_R0_TESTBUS_1083___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1083__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1083__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1084 (0x00AAB3D4) +#define WMAC0_HWSCH_R0_TESTBUS_1084___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1084__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1084__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1085 (0x00AAB3D8) +#define WMAC0_HWSCH_R0_TESTBUS_1085___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1085__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1085__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1086 (0x00AAB3DC) +#define WMAC0_HWSCH_R0_TESTBUS_1086___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1086__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1086__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1087 (0x00AAB3E0) +#define WMAC0_HWSCH_R0_TESTBUS_1087___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1087__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1087__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1088 (0x00AAB3E4) +#define WMAC0_HWSCH_R0_TESTBUS_1088___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1088__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1088__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1089 (0x00AAB3E8) +#define WMAC0_HWSCH_R0_TESTBUS_1089___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1089__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1089__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1090 (0x00AAB3EC) +#define WMAC0_HWSCH_R0_TESTBUS_1090___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1090__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1090__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1091 (0x00AAB3F0) +#define WMAC0_HWSCH_R0_TESTBUS_1091___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1091__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1091__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1092 (0x00AAB3F4) +#define WMAC0_HWSCH_R0_TESTBUS_1092___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1092__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1092__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1093 (0x00AAB3F8) +#define WMAC0_HWSCH_R0_TESTBUS_1093___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1093__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1093__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1094 (0x00AAB3FC) +#define WMAC0_HWSCH_R0_TESTBUS_1094___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1094__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1094__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1095 (0x00AAB400) +#define WMAC0_HWSCH_R0_TESTBUS_1095___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1095__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1095__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1096 (0x00AAB404) +#define WMAC0_HWSCH_R0_TESTBUS_1096___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1096__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1096__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1097 (0x00AAB408) +#define WMAC0_HWSCH_R0_TESTBUS_1097___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1097__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1097__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1098 (0x00AAB40C) +#define WMAC0_HWSCH_R0_TESTBUS_1098___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1098__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1098__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1099 (0x00AAB410) +#define WMAC0_HWSCH_R0_TESTBUS_1099___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1099__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1099__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1100 (0x00AAB414) +#define WMAC0_HWSCH_R0_TESTBUS_1100___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1100__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1100__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1101 (0x00AAB418) +#define WMAC0_HWSCH_R0_TESTBUS_1101___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1101__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1101__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1102 (0x00AAB41C) +#define WMAC0_HWSCH_R0_TESTBUS_1102___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1102__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1102__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1103 (0x00AAB420) +#define WMAC0_HWSCH_R0_TESTBUS_1103___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1103__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1103__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1104 (0x00AAB424) +#define WMAC0_HWSCH_R0_TESTBUS_1104___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1104__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1104__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1105 (0x00AAB428) +#define WMAC0_HWSCH_R0_TESTBUS_1105___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1105__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1105__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1106 (0x00AAB42C) +#define WMAC0_HWSCH_R0_TESTBUS_1106___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1106__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1106__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1107 (0x00AAB430) +#define WMAC0_HWSCH_R0_TESTBUS_1107___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1107__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1107__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1108 (0x00AAB434) +#define WMAC0_HWSCH_R0_TESTBUS_1108___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1108__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1108__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1109 (0x00AAB438) +#define WMAC0_HWSCH_R0_TESTBUS_1109___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1109__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1109__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1110 (0x00AAB43C) +#define WMAC0_HWSCH_R0_TESTBUS_1110___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1110__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1110__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1111 (0x00AAB440) +#define WMAC0_HWSCH_R0_TESTBUS_1111___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1111__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1111__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1112 (0x00AAB444) +#define WMAC0_HWSCH_R0_TESTBUS_1112___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1112__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1112__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1113 (0x00AAB448) +#define WMAC0_HWSCH_R0_TESTBUS_1113___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1113__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1113__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1114 (0x00AAB44C) +#define WMAC0_HWSCH_R0_TESTBUS_1114___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1114__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1114__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1115 (0x00AAB450) +#define WMAC0_HWSCH_R0_TESTBUS_1115___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1115__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1115__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1116 (0x00AAB454) +#define WMAC0_HWSCH_R0_TESTBUS_1116___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1116__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1116__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1117 (0x00AAB458) +#define WMAC0_HWSCH_R0_TESTBUS_1117___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1117__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1117__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1118 (0x00AAB45C) +#define WMAC0_HWSCH_R0_TESTBUS_1118___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1118__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1118__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1119 (0x00AAB460) +#define WMAC0_HWSCH_R0_TESTBUS_1119___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1119__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1119__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1120 (0x00AAB464) +#define WMAC0_HWSCH_R0_TESTBUS_1120___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1120__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1120__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1121 (0x00AAB468) +#define WMAC0_HWSCH_R0_TESTBUS_1121___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1121__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1121__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1122 (0x00AAB46C) +#define WMAC0_HWSCH_R0_TESTBUS_1122___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1122__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1122__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1123 (0x00AAB470) +#define WMAC0_HWSCH_R0_TESTBUS_1123___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1123__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1123__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1124 (0x00AAB474) +#define WMAC0_HWSCH_R0_TESTBUS_1124___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1124__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1124__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1125 (0x00AAB478) +#define WMAC0_HWSCH_R0_TESTBUS_1125___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1125__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1125__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1126 (0x00AAB47C) +#define WMAC0_HWSCH_R0_TESTBUS_1126___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1126__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1126__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1127 (0x00AAB480) +#define WMAC0_HWSCH_R0_TESTBUS_1127___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1127__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1127__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1128 (0x00AAB484) +#define WMAC0_HWSCH_R0_TESTBUS_1128___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1128__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1128__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1129 (0x00AAB488) +#define WMAC0_HWSCH_R0_TESTBUS_1129___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1129__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1129__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1130 (0x00AAB48C) +#define WMAC0_HWSCH_R0_TESTBUS_1130___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1130__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1130__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1131 (0x00AAB490) +#define WMAC0_HWSCH_R0_TESTBUS_1131___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1131__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1131__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1132 (0x00AAB494) +#define WMAC0_HWSCH_R0_TESTBUS_1132___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1132__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1132__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1133 (0x00AAB498) +#define WMAC0_HWSCH_R0_TESTBUS_1133___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1133__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1133__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1134 (0x00AAB49C) +#define WMAC0_HWSCH_R0_TESTBUS_1134___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1134__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1134__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1135 (0x00AAB4A0) +#define WMAC0_HWSCH_R0_TESTBUS_1135___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1135__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1135__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1136 (0x00AAB4A4) +#define WMAC0_HWSCH_R0_TESTBUS_1136___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1136__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1136__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1137 (0x00AAB4A8) +#define WMAC0_HWSCH_R0_TESTBUS_1137___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1137__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1137__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1138 (0x00AAB4AC) +#define WMAC0_HWSCH_R0_TESTBUS_1138___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1138__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1138__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1139 (0x00AAB4B0) +#define WMAC0_HWSCH_R0_TESTBUS_1139___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1139__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1139__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1140 (0x00AAB4B4) +#define WMAC0_HWSCH_R0_TESTBUS_1140___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1140__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1140__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1141 (0x00AAB4B8) +#define WMAC0_HWSCH_R0_TESTBUS_1141___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1141__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1141__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1142 (0x00AAB4BC) +#define WMAC0_HWSCH_R0_TESTBUS_1142___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1142__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1142__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1143 (0x00AAB4C0) +#define WMAC0_HWSCH_R0_TESTBUS_1143___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1143__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1143__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1144 (0x00AAB4C4) +#define WMAC0_HWSCH_R0_TESTBUS_1144___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1144__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1144__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1145 (0x00AAB4C8) +#define WMAC0_HWSCH_R0_TESTBUS_1145___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1145__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1145__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1146 (0x00AAB4CC) +#define WMAC0_HWSCH_R0_TESTBUS_1146___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1146__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1146__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1147 (0x00AAB4D0) +#define WMAC0_HWSCH_R0_TESTBUS_1147___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1147__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1147__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1148 (0x00AAB4D4) +#define WMAC0_HWSCH_R0_TESTBUS_1148___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1148__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1148__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1149 (0x00AAB4D8) +#define WMAC0_HWSCH_R0_TESTBUS_1149___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1149__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1149__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1150 (0x00AAB4DC) +#define WMAC0_HWSCH_R0_TESTBUS_1150___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1150__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1150__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1151 (0x00AAB4E0) +#define WMAC0_HWSCH_R0_TESTBUS_1151___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1151__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1151__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1152 (0x00AAB4E4) +#define WMAC0_HWSCH_R0_TESTBUS_1152___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1152__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1152__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1153 (0x00AAB4E8) +#define WMAC0_HWSCH_R0_TESTBUS_1153___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1153__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1153__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1154 (0x00AAB4EC) +#define WMAC0_HWSCH_R0_TESTBUS_1154___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1154__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1154__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1155 (0x00AAB4F0) +#define WMAC0_HWSCH_R0_TESTBUS_1155___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1155__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1155__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1156 (0x00AAB4F4) +#define WMAC0_HWSCH_R0_TESTBUS_1156___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1156__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1156__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1157 (0x00AAB4F8) +#define WMAC0_HWSCH_R0_TESTBUS_1157___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1157__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1157__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1158 (0x00AAB4FC) +#define WMAC0_HWSCH_R0_TESTBUS_1158___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1158__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1158__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1159 (0x00AAB500) +#define WMAC0_HWSCH_R0_TESTBUS_1159___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1159__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1159__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1160 (0x00AAB504) +#define WMAC0_HWSCH_R0_TESTBUS_1160___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1160__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1160__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1161 (0x00AAB508) +#define WMAC0_HWSCH_R0_TESTBUS_1161___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1161__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1161__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1162 (0x00AAB50C) +#define WMAC0_HWSCH_R0_TESTBUS_1162___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1162__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1162__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1163 (0x00AAB510) +#define WMAC0_HWSCH_R0_TESTBUS_1163___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1163__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1163__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1164 (0x00AAB514) +#define WMAC0_HWSCH_R0_TESTBUS_1164___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1164__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1164__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1165 (0x00AAB518) +#define WMAC0_HWSCH_R0_TESTBUS_1165___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1165__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1165__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1166 (0x00AAB51C) +#define WMAC0_HWSCH_R0_TESTBUS_1166___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1166__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1166__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1167 (0x00AAB520) +#define WMAC0_HWSCH_R0_TESTBUS_1167___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1167__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1167__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1168 (0x00AAB524) +#define WMAC0_HWSCH_R0_TESTBUS_1168___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1168__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1168__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1169 (0x00AAB528) +#define WMAC0_HWSCH_R0_TESTBUS_1169___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1169__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1169__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1170 (0x00AAB52C) +#define WMAC0_HWSCH_R0_TESTBUS_1170___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1170__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1170__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1171 (0x00AAB530) +#define WMAC0_HWSCH_R0_TESTBUS_1171___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1171__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1171__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1172 (0x00AAB534) +#define WMAC0_HWSCH_R0_TESTBUS_1172___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1172__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1172__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1173 (0x00AAB538) +#define WMAC0_HWSCH_R0_TESTBUS_1173___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1173__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1173__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1174 (0x00AAB53C) +#define WMAC0_HWSCH_R0_TESTBUS_1174___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1174__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1174__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1175 (0x00AAB540) +#define WMAC0_HWSCH_R0_TESTBUS_1175___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1175__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1175__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1176 (0x00AAB544) +#define WMAC0_HWSCH_R0_TESTBUS_1176___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1176__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1176__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1177 (0x00AAB548) +#define WMAC0_HWSCH_R0_TESTBUS_1177___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1177__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1177__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1178 (0x00AAB54C) +#define WMAC0_HWSCH_R0_TESTBUS_1178___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1178__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1178__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1179 (0x00AAB550) +#define WMAC0_HWSCH_R0_TESTBUS_1179___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1179__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1179__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1180 (0x00AAB554) +#define WMAC0_HWSCH_R0_TESTBUS_1180___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1180__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1180__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1181 (0x00AAB558) +#define WMAC0_HWSCH_R0_TESTBUS_1181___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1181__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1181__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1182 (0x00AAB55C) +#define WMAC0_HWSCH_R0_TESTBUS_1182___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1182__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1182__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1183 (0x00AAB560) +#define WMAC0_HWSCH_R0_TESTBUS_1183___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1183__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1183__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1184 (0x00AAB564) +#define WMAC0_HWSCH_R0_TESTBUS_1184___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1184__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1184__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1185 (0x00AAB568) +#define WMAC0_HWSCH_R0_TESTBUS_1185___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1185__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1185__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1186 (0x00AAB56C) +#define WMAC0_HWSCH_R0_TESTBUS_1186___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1186__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1186__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1187 (0x00AAB570) +#define WMAC0_HWSCH_R0_TESTBUS_1187___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1187__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1187__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1188 (0x00AAB574) +#define WMAC0_HWSCH_R0_TESTBUS_1188___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1188__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1188__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1189 (0x00AAB578) +#define WMAC0_HWSCH_R0_TESTBUS_1189___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1189__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1189__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1190 (0x00AAB57C) +#define WMAC0_HWSCH_R0_TESTBUS_1190___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1190__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1190__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1191 (0x00AAB580) +#define WMAC0_HWSCH_R0_TESTBUS_1191___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1191__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1191__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1192 (0x00AAB584) +#define WMAC0_HWSCH_R0_TESTBUS_1192___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1192__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1192__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1193 (0x00AAB588) +#define WMAC0_HWSCH_R0_TESTBUS_1193___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1193__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1193__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1194 (0x00AAB58C) +#define WMAC0_HWSCH_R0_TESTBUS_1194___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1194__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1194__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1195 (0x00AAB590) +#define WMAC0_HWSCH_R0_TESTBUS_1195___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1195__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1195__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1196 (0x00AAB594) +#define WMAC0_HWSCH_R0_TESTBUS_1196___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1196__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1196__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1197 (0x00AAB598) +#define WMAC0_HWSCH_R0_TESTBUS_1197___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1197__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1197__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1198 (0x00AAB59C) +#define WMAC0_HWSCH_R0_TESTBUS_1198___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1198__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1198__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1199 (0x00AAB5A0) +#define WMAC0_HWSCH_R0_TESTBUS_1199___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1199__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1199__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1200 (0x00AAB5A4) +#define WMAC0_HWSCH_R0_TESTBUS_1200___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1200__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1200__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1201 (0x00AAB5A8) +#define WMAC0_HWSCH_R0_TESTBUS_1201___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1201__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1201__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1202 (0x00AAB5AC) +#define WMAC0_HWSCH_R0_TESTBUS_1202___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1202__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1202__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1203 (0x00AAB5B0) +#define WMAC0_HWSCH_R0_TESTBUS_1203___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1203__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1203__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1204 (0x00AAB5B4) +#define WMAC0_HWSCH_R0_TESTBUS_1204___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1204__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1204__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1205 (0x00AAB5B8) +#define WMAC0_HWSCH_R0_TESTBUS_1205___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1205__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1205__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1206 (0x00AAB5BC) +#define WMAC0_HWSCH_R0_TESTBUS_1206___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1206__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1206__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1207 (0x00AAB5C0) +#define WMAC0_HWSCH_R0_TESTBUS_1207___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1207__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1207__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1208 (0x00AAB5C4) +#define WMAC0_HWSCH_R0_TESTBUS_1208___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1208__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1208__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1209 (0x00AAB5C8) +#define WMAC0_HWSCH_R0_TESTBUS_1209___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1209__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1209__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1210 (0x00AAB5CC) +#define WMAC0_HWSCH_R0_TESTBUS_1210___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1210__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1210__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1211 (0x00AAB5D0) +#define WMAC0_HWSCH_R0_TESTBUS_1211___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1211__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1211__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1212 (0x00AAB5D4) +#define WMAC0_HWSCH_R0_TESTBUS_1212___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1212__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1212__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1213 (0x00AAB5D8) +#define WMAC0_HWSCH_R0_TESTBUS_1213___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1213__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1213__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1214 (0x00AAB5DC) +#define WMAC0_HWSCH_R0_TESTBUS_1214___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1214__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1214__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1215 (0x00AAB5E0) +#define WMAC0_HWSCH_R0_TESTBUS_1215___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1215__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1215__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1216 (0x00AAB5E4) +#define WMAC0_HWSCH_R0_TESTBUS_1216___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1216__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1216__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1217 (0x00AAB5E8) +#define WMAC0_HWSCH_R0_TESTBUS_1217___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1217__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1217__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1218 (0x00AAB5EC) +#define WMAC0_HWSCH_R0_TESTBUS_1218___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1218__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1218__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1219 (0x00AAB5F0) +#define WMAC0_HWSCH_R0_TESTBUS_1219___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1219__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1219__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1220 (0x00AAB5F4) +#define WMAC0_HWSCH_R0_TESTBUS_1220___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1220__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1220__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1221 (0x00AAB5F8) +#define WMAC0_HWSCH_R0_TESTBUS_1221___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1221__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1221__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1222 (0x00AAB5FC) +#define WMAC0_HWSCH_R0_TESTBUS_1222___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1222__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1222__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1223 (0x00AAB600) +#define WMAC0_HWSCH_R0_TESTBUS_1223___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1223__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1223__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1224 (0x00AAB604) +#define WMAC0_HWSCH_R0_TESTBUS_1224___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1224__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1224__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1225 (0x00AAB608) +#define WMAC0_HWSCH_R0_TESTBUS_1225___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1225__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1225__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1226 (0x00AAB60C) +#define WMAC0_HWSCH_R0_TESTBUS_1226___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1226__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1226__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1227 (0x00AAB610) +#define WMAC0_HWSCH_R0_TESTBUS_1227___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1227__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1227__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1228 (0x00AAB614) +#define WMAC0_HWSCH_R0_TESTBUS_1228___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1228__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1228__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1229 (0x00AAB618) +#define WMAC0_HWSCH_R0_TESTBUS_1229___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1229__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1229__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1230 (0x00AAB61C) +#define WMAC0_HWSCH_R0_TESTBUS_1230___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1230__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1230__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1231 (0x00AAB620) +#define WMAC0_HWSCH_R0_TESTBUS_1231___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1231__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1231__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1232 (0x00AAB624) +#define WMAC0_HWSCH_R0_TESTBUS_1232___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1232__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1232__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1233 (0x00AAB628) +#define WMAC0_HWSCH_R0_TESTBUS_1233___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1233__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1233__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1234 (0x00AAB62C) +#define WMAC0_HWSCH_R0_TESTBUS_1234___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1234__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1234__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1235 (0x00AAB630) +#define WMAC0_HWSCH_R0_TESTBUS_1235___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1235__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1235__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1236 (0x00AAB634) +#define WMAC0_HWSCH_R0_TESTBUS_1236___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1236__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1236__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1237 (0x00AAB638) +#define WMAC0_HWSCH_R0_TESTBUS_1237___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1237__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1237__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1238 (0x00AAB63C) +#define WMAC0_HWSCH_R0_TESTBUS_1238___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1238__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1238__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1239 (0x00AAB640) +#define WMAC0_HWSCH_R0_TESTBUS_1239___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1239__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1239__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1240 (0x00AAB644) +#define WMAC0_HWSCH_R0_TESTBUS_1240___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1240__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1240__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1241 (0x00AAB648) +#define WMAC0_HWSCH_R0_TESTBUS_1241___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1241__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1241__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1242 (0x00AAB64C) +#define WMAC0_HWSCH_R0_TESTBUS_1242___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1242__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1242__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1243 (0x00AAB650) +#define WMAC0_HWSCH_R0_TESTBUS_1243___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1243__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1243__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1244 (0x00AAB654) +#define WMAC0_HWSCH_R0_TESTBUS_1244___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1244__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1244__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1245 (0x00AAB658) +#define WMAC0_HWSCH_R0_TESTBUS_1245___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1245__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1245__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1246 (0x00AAB65C) +#define WMAC0_HWSCH_R0_TESTBUS_1246___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1246__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1246__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1247 (0x00AAB660) +#define WMAC0_HWSCH_R0_TESTBUS_1247___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1247__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1247__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1248 (0x00AAB664) +#define WMAC0_HWSCH_R0_TESTBUS_1248___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1248__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1248__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1249 (0x00AAB668) +#define WMAC0_HWSCH_R0_TESTBUS_1249___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1249__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1249__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1250 (0x00AAB66C) +#define WMAC0_HWSCH_R0_TESTBUS_1250___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1250__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1250__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1251 (0x00AAB670) +#define WMAC0_HWSCH_R0_TESTBUS_1251___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1251__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1251__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1252 (0x00AAB674) +#define WMAC0_HWSCH_R0_TESTBUS_1252___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1252__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1252__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1253 (0x00AAB678) +#define WMAC0_HWSCH_R0_TESTBUS_1253___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1253__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1253__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1254 (0x00AAB67C) +#define WMAC0_HWSCH_R0_TESTBUS_1254___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1254__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1254__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1255 (0x00AAB680) +#define WMAC0_HWSCH_R0_TESTBUS_1255___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1255__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1255__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1256 (0x00AAB684) +#define WMAC0_HWSCH_R0_TESTBUS_1256___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1256__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1256__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1257 (0x00AAB688) +#define WMAC0_HWSCH_R0_TESTBUS_1257___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1257__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1257__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1258 (0x00AAB68C) +#define WMAC0_HWSCH_R0_TESTBUS_1258___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1258__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1258__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1259 (0x00AAB690) +#define WMAC0_HWSCH_R0_TESTBUS_1259___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1259__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1259__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1260 (0x00AAB694) +#define WMAC0_HWSCH_R0_TESTBUS_1260___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1260__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1260__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1261 (0x00AAB698) +#define WMAC0_HWSCH_R0_TESTBUS_1261___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1261__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1261__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1262 (0x00AAB69C) +#define WMAC0_HWSCH_R0_TESTBUS_1262___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1262__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1262__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1263 (0x00AAB6A0) +#define WMAC0_HWSCH_R0_TESTBUS_1263___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1263__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1263__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1264 (0x00AAB6A4) +#define WMAC0_HWSCH_R0_TESTBUS_1264___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1264__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1264__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1265 (0x00AAB6A8) +#define WMAC0_HWSCH_R0_TESTBUS_1265___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1265__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1265__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1266 (0x00AAB6AC) +#define WMAC0_HWSCH_R0_TESTBUS_1266___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1266__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1266__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1267 (0x00AAB6B0) +#define WMAC0_HWSCH_R0_TESTBUS_1267___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1267__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1267__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1268 (0x00AAB6B4) +#define WMAC0_HWSCH_R0_TESTBUS_1268___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1268__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1268__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1269 (0x00AAB6B8) +#define WMAC0_HWSCH_R0_TESTBUS_1269___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1269__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1269__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1270 (0x00AAB6BC) +#define WMAC0_HWSCH_R0_TESTBUS_1270___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1270__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1270__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1271 (0x00AAB6C0) +#define WMAC0_HWSCH_R0_TESTBUS_1271___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1271__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1271__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1272 (0x00AAB6C4) +#define WMAC0_HWSCH_R0_TESTBUS_1272___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1272__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1272__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1273 (0x00AAB6C8) +#define WMAC0_HWSCH_R0_TESTBUS_1273___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1273__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1273__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1274 (0x00AAB6CC) +#define WMAC0_HWSCH_R0_TESTBUS_1274___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1274__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1274__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1275 (0x00AAB6D0) +#define WMAC0_HWSCH_R0_TESTBUS_1275___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1275__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1275__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1276 (0x00AAB6D4) +#define WMAC0_HWSCH_R0_TESTBUS_1276___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1276__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1276__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1277 (0x00AAB6D8) +#define WMAC0_HWSCH_R0_TESTBUS_1277___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1277__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1277__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1278 (0x00AAB6DC) +#define WMAC0_HWSCH_R0_TESTBUS_1278___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1278__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1278__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1279 (0x00AAB6E0) +#define WMAC0_HWSCH_R0_TESTBUS_1279___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1279__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1279__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1280 (0x00AAB6E4) +#define WMAC0_HWSCH_R0_TESTBUS_1280___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1280__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1280__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1281 (0x00AAB6E8) +#define WMAC0_HWSCH_R0_TESTBUS_1281___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1281__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1281__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1282 (0x00AAB6EC) +#define WMAC0_HWSCH_R0_TESTBUS_1282___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1282__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1282__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1283 (0x00AAB6F0) +#define WMAC0_HWSCH_R0_TESTBUS_1283___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1283__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1283__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1284 (0x00AAB6F4) +#define WMAC0_HWSCH_R0_TESTBUS_1284___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1284__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1284__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1285 (0x00AAB6F8) +#define WMAC0_HWSCH_R0_TESTBUS_1285___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1285__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1285__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1286 (0x00AAB6FC) +#define WMAC0_HWSCH_R0_TESTBUS_1286___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1286__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1286__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1287 (0x00AAB700) +#define WMAC0_HWSCH_R0_TESTBUS_1287___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1287__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1287__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1288 (0x00AAB704) +#define WMAC0_HWSCH_R0_TESTBUS_1288___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1288__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1288__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1289 (0x00AAB708) +#define WMAC0_HWSCH_R0_TESTBUS_1289___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1289__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1289__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1290 (0x00AAB70C) +#define WMAC0_HWSCH_R0_TESTBUS_1290___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1290__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1290__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1291 (0x00AAB710) +#define WMAC0_HWSCH_R0_TESTBUS_1291___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1291__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1291__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1292 (0x00AAB714) +#define WMAC0_HWSCH_R0_TESTBUS_1292___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1292__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1292__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1293 (0x00AAB718) +#define WMAC0_HWSCH_R0_TESTBUS_1293___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1293__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1293__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1294 (0x00AAB71C) +#define WMAC0_HWSCH_R0_TESTBUS_1294___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1294__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1294__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1295 (0x00AAB720) +#define WMAC0_HWSCH_R0_TESTBUS_1295___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1295__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1295__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1296 (0x00AAB724) +#define WMAC0_HWSCH_R0_TESTBUS_1296___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1296__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1296__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1297 (0x00AAB728) +#define WMAC0_HWSCH_R0_TESTBUS_1297___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1297__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1297__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1298 (0x00AAB72C) +#define WMAC0_HWSCH_R0_TESTBUS_1298___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1298__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1298__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1299 (0x00AAB730) +#define WMAC0_HWSCH_R0_TESTBUS_1299___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1299__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1299__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1300 (0x00AAB734) +#define WMAC0_HWSCH_R0_TESTBUS_1300___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1300__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1300__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1301 (0x00AAB738) +#define WMAC0_HWSCH_R0_TESTBUS_1301___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1301__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1301__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1302 (0x00AAB73C) +#define WMAC0_HWSCH_R0_TESTBUS_1302___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1302__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1302__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1303 (0x00AAB740) +#define WMAC0_HWSCH_R0_TESTBUS_1303___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1303__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1303__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1304 (0x00AAB744) +#define WMAC0_HWSCH_R0_TESTBUS_1304___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1304__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1304__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1305 (0x00AAB748) +#define WMAC0_HWSCH_R0_TESTBUS_1305___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1305__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1305__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1306 (0x00AAB74C) +#define WMAC0_HWSCH_R0_TESTBUS_1306___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1306__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1306__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1307 (0x00AAB750) +#define WMAC0_HWSCH_R0_TESTBUS_1307___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1307__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1307__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1308 (0x00AAB754) +#define WMAC0_HWSCH_R0_TESTBUS_1308___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1308__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1308__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1309 (0x00AAB758) +#define WMAC0_HWSCH_R0_TESTBUS_1309___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1309__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1309__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1310 (0x00AAB75C) +#define WMAC0_HWSCH_R0_TESTBUS_1310___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1310__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1310__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1311 (0x00AAB760) +#define WMAC0_HWSCH_R0_TESTBUS_1311___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1311__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1311__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1312 (0x00AAB764) +#define WMAC0_HWSCH_R0_TESTBUS_1312___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1312__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1312__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1313 (0x00AAB768) +#define WMAC0_HWSCH_R0_TESTBUS_1313___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1313__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1313__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1314 (0x00AAB76C) +#define WMAC0_HWSCH_R0_TESTBUS_1314___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1314__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1314__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1315 (0x00AAB770) +#define WMAC0_HWSCH_R0_TESTBUS_1315___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1315__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1315__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1316 (0x00AAB774) +#define WMAC0_HWSCH_R0_TESTBUS_1316___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1316__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1316__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1317 (0x00AAB778) +#define WMAC0_HWSCH_R0_TESTBUS_1317___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1317__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1317__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1318 (0x00AAB77C) +#define WMAC0_HWSCH_R0_TESTBUS_1318___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1318__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1318__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1319 (0x00AAB780) +#define WMAC0_HWSCH_R0_TESTBUS_1319___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1319__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1319__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1320 (0x00AAB784) +#define WMAC0_HWSCH_R0_TESTBUS_1320___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1320__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1320__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1321 (0x00AAB788) +#define WMAC0_HWSCH_R0_TESTBUS_1321___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1321__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1321__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1322 (0x00AAB78C) +#define WMAC0_HWSCH_R0_TESTBUS_1322___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1322__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1322__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1323 (0x00AAB790) +#define WMAC0_HWSCH_R0_TESTBUS_1323___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1323__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1323__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1324 (0x00AAB794) +#define WMAC0_HWSCH_R0_TESTBUS_1324___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1324__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1324__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1325 (0x00AAB798) +#define WMAC0_HWSCH_R0_TESTBUS_1325___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1325__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1325__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1326 (0x00AAB79C) +#define WMAC0_HWSCH_R0_TESTBUS_1326___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1326__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1326__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1327 (0x00AAB7A0) +#define WMAC0_HWSCH_R0_TESTBUS_1327___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1327__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1327__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1328 (0x00AAB7A4) +#define WMAC0_HWSCH_R0_TESTBUS_1328___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1328__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1328__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1329 (0x00AAB7A8) +#define WMAC0_HWSCH_R0_TESTBUS_1329___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1329__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1329__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1330 (0x00AAB7AC) +#define WMAC0_HWSCH_R0_TESTBUS_1330___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1330__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1330__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1331 (0x00AAB7B0) +#define WMAC0_HWSCH_R0_TESTBUS_1331___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1331__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1331__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1332 (0x00AAB7B4) +#define WMAC0_HWSCH_R0_TESTBUS_1332___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1332__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1332__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1333 (0x00AAB7B8) +#define WMAC0_HWSCH_R0_TESTBUS_1333___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1333__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1333__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1334 (0x00AAB7BC) +#define WMAC0_HWSCH_R0_TESTBUS_1334___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1334__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1334__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1335 (0x00AAB7C0) +#define WMAC0_HWSCH_R0_TESTBUS_1335___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1335__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1335__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1336 (0x00AAB7C4) +#define WMAC0_HWSCH_R0_TESTBUS_1336___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1336__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1336__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1337 (0x00AAB7C8) +#define WMAC0_HWSCH_R0_TESTBUS_1337___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1337__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1337__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1338 (0x00AAB7CC) +#define WMAC0_HWSCH_R0_TESTBUS_1338___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1338__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1338__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1339 (0x00AAB7D0) +#define WMAC0_HWSCH_R0_TESTBUS_1339___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1339__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1339__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1340 (0x00AAB7D4) +#define WMAC0_HWSCH_R0_TESTBUS_1340___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1340__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1340__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1341 (0x00AAB7D8) +#define WMAC0_HWSCH_R0_TESTBUS_1341___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1341__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1341__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1342 (0x00AAB7DC) +#define WMAC0_HWSCH_R0_TESTBUS_1342___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1342__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1342__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1343 (0x00AAB7E0) +#define WMAC0_HWSCH_R0_TESTBUS_1343___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1343__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1343__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1344 (0x00AAB7E4) +#define WMAC0_HWSCH_R0_TESTBUS_1344___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1344__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1344__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1345 (0x00AAB7E8) +#define WMAC0_HWSCH_R0_TESTBUS_1345___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1345__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1345__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1346 (0x00AAB7EC) +#define WMAC0_HWSCH_R0_TESTBUS_1346___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1346__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1346__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1347 (0x00AAB7F0) +#define WMAC0_HWSCH_R0_TESTBUS_1347___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1347__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1347__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1348 (0x00AAB7F4) +#define WMAC0_HWSCH_R0_TESTBUS_1348___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1348__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1348__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1349 (0x00AAB7F8) +#define WMAC0_HWSCH_R0_TESTBUS_1349___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1349__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1349__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1350 (0x00AAB7FC) +#define WMAC0_HWSCH_R0_TESTBUS_1350___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1350__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1350__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1351 (0x00AAB800) +#define WMAC0_HWSCH_R0_TESTBUS_1351___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1351__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1351__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1352 (0x00AAB804) +#define WMAC0_HWSCH_R0_TESTBUS_1352___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1352__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1352__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1353 (0x00AAB808) +#define WMAC0_HWSCH_R0_TESTBUS_1353___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1353__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1353__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1354 (0x00AAB80C) +#define WMAC0_HWSCH_R0_TESTBUS_1354___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1354__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1354__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1355 (0x00AAB810) +#define WMAC0_HWSCH_R0_TESTBUS_1355___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1355__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1355__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1356 (0x00AAB814) +#define WMAC0_HWSCH_R0_TESTBUS_1356___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1356__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1356__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1357 (0x00AAB818) +#define WMAC0_HWSCH_R0_TESTBUS_1357___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1357__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1357__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1358 (0x00AAB81C) +#define WMAC0_HWSCH_R0_TESTBUS_1358___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1358__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1358__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1359 (0x00AAB820) +#define WMAC0_HWSCH_R0_TESTBUS_1359___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1359__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1359__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1360 (0x00AAB824) +#define WMAC0_HWSCH_R0_TESTBUS_1360___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1360__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1360__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1361 (0x00AAB828) +#define WMAC0_HWSCH_R0_TESTBUS_1361___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1361__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1361__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1362 (0x00AAB82C) +#define WMAC0_HWSCH_R0_TESTBUS_1362___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1362__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1362__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1363 (0x00AAB830) +#define WMAC0_HWSCH_R0_TESTBUS_1363___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1363__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1363__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1364 (0x00AAB834) +#define WMAC0_HWSCH_R0_TESTBUS_1364___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1364__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1364__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1365 (0x00AAB838) +#define WMAC0_HWSCH_R0_TESTBUS_1365___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1365__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1365__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1366 (0x00AAB83C) +#define WMAC0_HWSCH_R0_TESTBUS_1366___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1366__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1366__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1367 (0x00AAB840) +#define WMAC0_HWSCH_R0_TESTBUS_1367___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1367__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1367__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1368 (0x00AAB844) +#define WMAC0_HWSCH_R0_TESTBUS_1368___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1368__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1368__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1369 (0x00AAB848) +#define WMAC0_HWSCH_R0_TESTBUS_1369___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1369__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1369__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1370 (0x00AAB84C) +#define WMAC0_HWSCH_R0_TESTBUS_1370___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1370__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1370__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1371 (0x00AAB850) +#define WMAC0_HWSCH_R0_TESTBUS_1371___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1371__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1371__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1372 (0x00AAB854) +#define WMAC0_HWSCH_R0_TESTBUS_1372___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1372__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1372__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1373 (0x00AAB858) +#define WMAC0_HWSCH_R0_TESTBUS_1373___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1373__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1373__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1374 (0x00AAB85C) +#define WMAC0_HWSCH_R0_TESTBUS_1374___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1374__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1374__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1375 (0x00AAB860) +#define WMAC0_HWSCH_R0_TESTBUS_1375___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1375__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1375__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1376 (0x00AAB864) +#define WMAC0_HWSCH_R0_TESTBUS_1376___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1376__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1376__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1377 (0x00AAB868) +#define WMAC0_HWSCH_R0_TESTBUS_1377___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1377__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1377__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1378 (0x00AAB86C) +#define WMAC0_HWSCH_R0_TESTBUS_1378___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1378__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1378__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1379 (0x00AAB870) +#define WMAC0_HWSCH_R0_TESTBUS_1379___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1379__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1379__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1380 (0x00AAB874) +#define WMAC0_HWSCH_R0_TESTBUS_1380___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1380__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1380__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1381 (0x00AAB878) +#define WMAC0_HWSCH_R0_TESTBUS_1381___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1381__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1381__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1382 (0x00AAB87C) +#define WMAC0_HWSCH_R0_TESTBUS_1382___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1382__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1382__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1383 (0x00AAB880) +#define WMAC0_HWSCH_R0_TESTBUS_1383___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1383__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1383__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1384 (0x00AAB884) +#define WMAC0_HWSCH_R0_TESTBUS_1384___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1384__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1384__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1385 (0x00AAB888) +#define WMAC0_HWSCH_R0_TESTBUS_1385___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1385__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1385__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1386 (0x00AAB88C) +#define WMAC0_HWSCH_R0_TESTBUS_1386___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1386__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1386__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1387 (0x00AAB890) +#define WMAC0_HWSCH_R0_TESTBUS_1387___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1387__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1387__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1388 (0x00AAB894) +#define WMAC0_HWSCH_R0_TESTBUS_1388___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1388__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1388__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1389 (0x00AAB898) +#define WMAC0_HWSCH_R0_TESTBUS_1389___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1389__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1389__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1390 (0x00AAB89C) +#define WMAC0_HWSCH_R0_TESTBUS_1390___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1390__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1390__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1391 (0x00AAB8A0) +#define WMAC0_HWSCH_R0_TESTBUS_1391___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1391__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1391__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1392 (0x00AAB8A4) +#define WMAC0_HWSCH_R0_TESTBUS_1392___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1392__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1392__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1393 (0x00AAB8A8) +#define WMAC0_HWSCH_R0_TESTBUS_1393___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1393__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1393__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1394 (0x00AAB8AC) +#define WMAC0_HWSCH_R0_TESTBUS_1394___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1394__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1394__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1395 (0x00AAB8B0) +#define WMAC0_HWSCH_R0_TESTBUS_1395___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1395__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1395__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1396 (0x00AAB8B4) +#define WMAC0_HWSCH_R0_TESTBUS_1396___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1396__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1396__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1397 (0x00AAB8B8) +#define WMAC0_HWSCH_R0_TESTBUS_1397___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1397__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1397__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1398 (0x00AAB8BC) +#define WMAC0_HWSCH_R0_TESTBUS_1398___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1398__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1398__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1399 (0x00AAB8C0) +#define WMAC0_HWSCH_R0_TESTBUS_1399___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1399__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1399__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1400 (0x00AAB8C4) +#define WMAC0_HWSCH_R0_TESTBUS_1400___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1400__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1400__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1401 (0x00AAB8C8) +#define WMAC0_HWSCH_R0_TESTBUS_1401___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1401__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1401__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1402 (0x00AAB8CC) +#define WMAC0_HWSCH_R0_TESTBUS_1402___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1402__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1402__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1403 (0x00AAB8D0) +#define WMAC0_HWSCH_R0_TESTBUS_1403___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1403__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1403__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1404 (0x00AAB8D4) +#define WMAC0_HWSCH_R0_TESTBUS_1404___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1404__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1404__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1405 (0x00AAB8D8) +#define WMAC0_HWSCH_R0_TESTBUS_1405___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1405__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1405__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1406 (0x00AAB8DC) +#define WMAC0_HWSCH_R0_TESTBUS_1406___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1406__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1406__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1407 (0x00AAB8E0) +#define WMAC0_HWSCH_R0_TESTBUS_1407___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1407__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1407__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1408 (0x00AAB8E4) +#define WMAC0_HWSCH_R0_TESTBUS_1408___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1408__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1408__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1409 (0x00AAB8E8) +#define WMAC0_HWSCH_R0_TESTBUS_1409___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1409__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1409__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1410 (0x00AAB8EC) +#define WMAC0_HWSCH_R0_TESTBUS_1410___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1410__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1410__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1411 (0x00AAB8F0) +#define WMAC0_HWSCH_R0_TESTBUS_1411___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1411__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1411__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1412 (0x00AAB8F4) +#define WMAC0_HWSCH_R0_TESTBUS_1412___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1412__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1412__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1413 (0x00AAB8F8) +#define WMAC0_HWSCH_R0_TESTBUS_1413___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1413__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1413__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1414 (0x00AAB8FC) +#define WMAC0_HWSCH_R0_TESTBUS_1414___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1414__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1414__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1415 (0x00AAB900) +#define WMAC0_HWSCH_R0_TESTBUS_1415___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1415__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1415__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1416 (0x00AAB904) +#define WMAC0_HWSCH_R0_TESTBUS_1416___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1416__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1416__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1417 (0x00AAB908) +#define WMAC0_HWSCH_R0_TESTBUS_1417___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1417__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1417__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1418 (0x00AAB90C) +#define WMAC0_HWSCH_R0_TESTBUS_1418___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1418__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1418__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1419 (0x00AAB910) +#define WMAC0_HWSCH_R0_TESTBUS_1419___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1419__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1419__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1420 (0x00AAB914) +#define WMAC0_HWSCH_R0_TESTBUS_1420___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1420__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1420__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1421 (0x00AAB918) +#define WMAC0_HWSCH_R0_TESTBUS_1421___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1421__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1421__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1422 (0x00AAB91C) +#define WMAC0_HWSCH_R0_TESTBUS_1422___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1422__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1422__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1423 (0x00AAB920) +#define WMAC0_HWSCH_R0_TESTBUS_1423___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1423__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1423__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1424 (0x00AAB924) +#define WMAC0_HWSCH_R0_TESTBUS_1424___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1424__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1424__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1425 (0x00AAB928) +#define WMAC0_HWSCH_R0_TESTBUS_1425___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1425__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1425__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1426 (0x00AAB92C) +#define WMAC0_HWSCH_R0_TESTBUS_1426___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1426__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1426__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1427 (0x00AAB930) +#define WMAC0_HWSCH_R0_TESTBUS_1427___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1427__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1427__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1428 (0x00AAB934) +#define WMAC0_HWSCH_R0_TESTBUS_1428___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1428__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1428__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1429 (0x00AAB938) +#define WMAC0_HWSCH_R0_TESTBUS_1429___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1429__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1429__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1430 (0x00AAB93C) +#define WMAC0_HWSCH_R0_TESTBUS_1430___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1430__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1430__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1431 (0x00AAB940) +#define WMAC0_HWSCH_R0_TESTBUS_1431___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1431__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1431__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1432 (0x00AAB944) +#define WMAC0_HWSCH_R0_TESTBUS_1432___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1432__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1432__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1433 (0x00AAB948) +#define WMAC0_HWSCH_R0_TESTBUS_1433___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1433__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1433__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1434 (0x00AAB94C) +#define WMAC0_HWSCH_R0_TESTBUS_1434___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1434__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1434__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1435 (0x00AAB950) +#define WMAC0_HWSCH_R0_TESTBUS_1435___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1435__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1435__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1436 (0x00AAB954) +#define WMAC0_HWSCH_R0_TESTBUS_1436___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1436__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1436__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1437 (0x00AAB958) +#define WMAC0_HWSCH_R0_TESTBUS_1437___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1437__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1437__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1438 (0x00AAB95C) +#define WMAC0_HWSCH_R0_TESTBUS_1438___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1438__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1438__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1439 (0x00AAB960) +#define WMAC0_HWSCH_R0_TESTBUS_1439___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1439__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1439__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1440 (0x00AAB964) +#define WMAC0_HWSCH_R0_TESTBUS_1440___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1440__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1440__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1441 (0x00AAB968) +#define WMAC0_HWSCH_R0_TESTBUS_1441___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1441__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1441__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1442 (0x00AAB96C) +#define WMAC0_HWSCH_R0_TESTBUS_1442___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1442__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1442__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1443 (0x00AAB970) +#define WMAC0_HWSCH_R0_TESTBUS_1443___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1443__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1443__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1444 (0x00AAB974) +#define WMAC0_HWSCH_R0_TESTBUS_1444___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1444__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1444__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1445 (0x00AAB978) +#define WMAC0_HWSCH_R0_TESTBUS_1445___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1445__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1445__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1446 (0x00AAB97C) +#define WMAC0_HWSCH_R0_TESTBUS_1446___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1446__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1446__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1447 (0x00AAB980) +#define WMAC0_HWSCH_R0_TESTBUS_1447___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1447__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1447__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1448 (0x00AAB984) +#define WMAC0_HWSCH_R0_TESTBUS_1448___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1448__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1448__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1449 (0x00AAB988) +#define WMAC0_HWSCH_R0_TESTBUS_1449___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1449__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1449__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1450 (0x00AAB98C) +#define WMAC0_HWSCH_R0_TESTBUS_1450___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1450__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1450__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1451 (0x00AAB990) +#define WMAC0_HWSCH_R0_TESTBUS_1451___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1451__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1451__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1452 (0x00AAB994) +#define WMAC0_HWSCH_R0_TESTBUS_1452___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1452__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1452__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1453 (0x00AAB998) +#define WMAC0_HWSCH_R0_TESTBUS_1453___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1453__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1453__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1454 (0x00AAB99C) +#define WMAC0_HWSCH_R0_TESTBUS_1454___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1454__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1454__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1455 (0x00AAB9A0) +#define WMAC0_HWSCH_R0_TESTBUS_1455___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1455__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1455__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1456 (0x00AAB9A4) +#define WMAC0_HWSCH_R0_TESTBUS_1456___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1456__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1456__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1457 (0x00AAB9A8) +#define WMAC0_HWSCH_R0_TESTBUS_1457___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1457__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1457__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1458 (0x00AAB9AC) +#define WMAC0_HWSCH_R0_TESTBUS_1458___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1458__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1458__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1459 (0x00AAB9B0) +#define WMAC0_HWSCH_R0_TESTBUS_1459___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1459__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1459__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1460 (0x00AAB9B4) +#define WMAC0_HWSCH_R0_TESTBUS_1460___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1460__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1460__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1461 (0x00AAB9B8) +#define WMAC0_HWSCH_R0_TESTBUS_1461___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1461__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1461__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1462 (0x00AAB9BC) +#define WMAC0_HWSCH_R0_TESTBUS_1462___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1462__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1462__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1463 (0x00AAB9C0) +#define WMAC0_HWSCH_R0_TESTBUS_1463___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1463__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1463__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1464 (0x00AAB9C4) +#define WMAC0_HWSCH_R0_TESTBUS_1464___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1464__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1464__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1465 (0x00AAB9C8) +#define WMAC0_HWSCH_R0_TESTBUS_1465___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1465__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1465__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1466 (0x00AAB9CC) +#define WMAC0_HWSCH_R0_TESTBUS_1466___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1466__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1466__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1467 (0x00AAB9D0) +#define WMAC0_HWSCH_R0_TESTBUS_1467___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1467__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1467__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1468 (0x00AAB9D4) +#define WMAC0_HWSCH_R0_TESTBUS_1468___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1468__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1468__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1469 (0x00AAB9D8) +#define WMAC0_HWSCH_R0_TESTBUS_1469___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1469__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1469__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1470 (0x00AAB9DC) +#define WMAC0_HWSCH_R0_TESTBUS_1470___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1470__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1470__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1471 (0x00AAB9E0) +#define WMAC0_HWSCH_R0_TESTBUS_1471___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1471__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1471__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1472 (0x00AAB9E4) +#define WMAC0_HWSCH_R0_TESTBUS_1472___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1472__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1472__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1473 (0x00AAB9E8) +#define WMAC0_HWSCH_R0_TESTBUS_1473___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1473__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1473__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1474 (0x00AAB9EC) +#define WMAC0_HWSCH_R0_TESTBUS_1474___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1474__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1474__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1475 (0x00AAB9F0) +#define WMAC0_HWSCH_R0_TESTBUS_1475___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1475__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1475__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1476 (0x00AAB9F4) +#define WMAC0_HWSCH_R0_TESTBUS_1476___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1476__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1476__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1477 (0x00AAB9F8) +#define WMAC0_HWSCH_R0_TESTBUS_1477___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1477__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1477__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1478 (0x00AAB9FC) +#define WMAC0_HWSCH_R0_TESTBUS_1478___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1478__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1478__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1479 (0x00AABA00) +#define WMAC0_HWSCH_R0_TESTBUS_1479___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1479__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1479__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1480 (0x00AABA04) +#define WMAC0_HWSCH_R0_TESTBUS_1480___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1480__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1480__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1481 (0x00AABA08) +#define WMAC0_HWSCH_R0_TESTBUS_1481___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1481__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1481__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1482 (0x00AABA0C) +#define WMAC0_HWSCH_R0_TESTBUS_1482___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1482__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1482__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1483 (0x00AABA10) +#define WMAC0_HWSCH_R0_TESTBUS_1483___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1483__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1483__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1484 (0x00AABA14) +#define WMAC0_HWSCH_R0_TESTBUS_1484___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1484__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1484__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1485 (0x00AABA18) +#define WMAC0_HWSCH_R0_TESTBUS_1485___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1485__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1485__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1486 (0x00AABA1C) +#define WMAC0_HWSCH_R0_TESTBUS_1486___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1486__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1486__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1487 (0x00AABA20) +#define WMAC0_HWSCH_R0_TESTBUS_1487___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1487__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1487__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1488 (0x00AABA24) +#define WMAC0_HWSCH_R0_TESTBUS_1488___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1488__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1488__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1489 (0x00AABA28) +#define WMAC0_HWSCH_R0_TESTBUS_1489___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1489__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1489__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1490 (0x00AABA2C) +#define WMAC0_HWSCH_R0_TESTBUS_1490___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1490__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1490__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1491 (0x00AABA30) +#define WMAC0_HWSCH_R0_TESTBUS_1491___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1491__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1491__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1492 (0x00AABA34) +#define WMAC0_HWSCH_R0_TESTBUS_1492___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1492__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1492__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1493 (0x00AABA38) +#define WMAC0_HWSCH_R0_TESTBUS_1493___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1493__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1493__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1494 (0x00AABA3C) +#define WMAC0_HWSCH_R0_TESTBUS_1494___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1494__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1494__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1495 (0x00AABA40) +#define WMAC0_HWSCH_R0_TESTBUS_1495___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1495__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1495__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1496 (0x00AABA44) +#define WMAC0_HWSCH_R0_TESTBUS_1496___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1496__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1496__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1497 (0x00AABA48) +#define WMAC0_HWSCH_R0_TESTBUS_1497___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1497__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1497__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1498 (0x00AABA4C) +#define WMAC0_HWSCH_R0_TESTBUS_1498___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1498__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1498__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1499 (0x00AABA50) +#define WMAC0_HWSCH_R0_TESTBUS_1499___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1499__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1499__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1500 (0x00AABA54) +#define WMAC0_HWSCH_R0_TESTBUS_1500___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1500__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1500__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1501 (0x00AABA58) +#define WMAC0_HWSCH_R0_TESTBUS_1501___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1501__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1501__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1502 (0x00AABA5C) +#define WMAC0_HWSCH_R0_TESTBUS_1502___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1502__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1502__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1503 (0x00AABA60) +#define WMAC0_HWSCH_R0_TESTBUS_1503___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1503__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1503__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1504 (0x00AABA64) +#define WMAC0_HWSCH_R0_TESTBUS_1504___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1504__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1504__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1505 (0x00AABA68) +#define WMAC0_HWSCH_R0_TESTBUS_1505___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1505__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1505__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1506 (0x00AABA6C) +#define WMAC0_HWSCH_R0_TESTBUS_1506___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1506__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1506__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1507 (0x00AABA70) +#define WMAC0_HWSCH_R0_TESTBUS_1507___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1507__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1507__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1508 (0x00AABA74) +#define WMAC0_HWSCH_R0_TESTBUS_1508___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1508__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1508__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1509 (0x00AABA78) +#define WMAC0_HWSCH_R0_TESTBUS_1509___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1509__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1509__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1510 (0x00AABA7C) +#define WMAC0_HWSCH_R0_TESTBUS_1510___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1510__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1510__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1511 (0x00AABA80) +#define WMAC0_HWSCH_R0_TESTBUS_1511___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1511__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1511__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1512 (0x00AABA84) +#define WMAC0_HWSCH_R0_TESTBUS_1512___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1512__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1512__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1513 (0x00AABA88) +#define WMAC0_HWSCH_R0_TESTBUS_1513___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1513__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1513__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1514 (0x00AABA8C) +#define WMAC0_HWSCH_R0_TESTBUS_1514___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1514__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1514__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1515 (0x00AABA90) +#define WMAC0_HWSCH_R0_TESTBUS_1515___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1515__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1515__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1516 (0x00AABA94) +#define WMAC0_HWSCH_R0_TESTBUS_1516___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1516__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1516__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1517 (0x00AABA98) +#define WMAC0_HWSCH_R0_TESTBUS_1517___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1517__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1517__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1518 (0x00AABA9C) +#define WMAC0_HWSCH_R0_TESTBUS_1518___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1518__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1518__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1519 (0x00AABAA0) +#define WMAC0_HWSCH_R0_TESTBUS_1519___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1519__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1519__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1520 (0x00AABAA4) +#define WMAC0_HWSCH_R0_TESTBUS_1520___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1520__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1520__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1521 (0x00AABAA8) +#define WMAC0_HWSCH_R0_TESTBUS_1521___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1521__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1521__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1522 (0x00AABAAC) +#define WMAC0_HWSCH_R0_TESTBUS_1522___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1522__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1522__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1523 (0x00AABAB0) +#define WMAC0_HWSCH_R0_TESTBUS_1523___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1523__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1523__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1524 (0x00AABAB4) +#define WMAC0_HWSCH_R0_TESTBUS_1524___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1524__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1524__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1525 (0x00AABAB8) +#define WMAC0_HWSCH_R0_TESTBUS_1525___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1525__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1525__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1526 (0x00AABABC) +#define WMAC0_HWSCH_R0_TESTBUS_1526___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1526__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1526__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1527 (0x00AABAC0) +#define WMAC0_HWSCH_R0_TESTBUS_1527___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1527__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1527__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1528 (0x00AABAC4) +#define WMAC0_HWSCH_R0_TESTBUS_1528___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1528__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1528__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1529 (0x00AABAC8) +#define WMAC0_HWSCH_R0_TESTBUS_1529___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1529__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1529__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1530 (0x00AABACC) +#define WMAC0_HWSCH_R0_TESTBUS_1530___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1530__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1530__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1531 (0x00AABAD0) +#define WMAC0_HWSCH_R0_TESTBUS_1531___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1531__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1531__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1532 (0x00AABAD4) +#define WMAC0_HWSCH_R0_TESTBUS_1532___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1532__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1532__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1533 (0x00AABAD8) +#define WMAC0_HWSCH_R0_TESTBUS_1533___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1533__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1533__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1534 (0x00AABADC) +#define WMAC0_HWSCH_R0_TESTBUS_1534___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1534__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1534__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1535 (0x00AABAE0) +#define WMAC0_HWSCH_R0_TESTBUS_1535___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1535__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1535__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1536 (0x00AABAE4) +#define WMAC0_HWSCH_R0_TESTBUS_1536___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1536__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1536__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1537 (0x00AABAE8) +#define WMAC0_HWSCH_R0_TESTBUS_1537___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1537__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1537__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1538 (0x00AABAEC) +#define WMAC0_HWSCH_R0_TESTBUS_1538___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1538__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1538__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1539 (0x00AABAF0) +#define WMAC0_HWSCH_R0_TESTBUS_1539___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1539__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1539__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1540 (0x00AABAF4) +#define WMAC0_HWSCH_R0_TESTBUS_1540___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1540__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1540__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1541 (0x00AABAF8) +#define WMAC0_HWSCH_R0_TESTBUS_1541___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1541__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1541__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1542 (0x00AABAFC) +#define WMAC0_HWSCH_R0_TESTBUS_1542___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1542__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1542__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1543 (0x00AABB00) +#define WMAC0_HWSCH_R0_TESTBUS_1543___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1543__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1543__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1544 (0x00AABB04) +#define WMAC0_HWSCH_R0_TESTBUS_1544___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1544__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1544__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1545 (0x00AABB08) +#define WMAC0_HWSCH_R0_TESTBUS_1545___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1545__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1545__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1546 (0x00AABB0C) +#define WMAC0_HWSCH_R0_TESTBUS_1546___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1546__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1546__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1547 (0x00AABB10) +#define WMAC0_HWSCH_R0_TESTBUS_1547___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1547__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1547__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1548 (0x00AABB14) +#define WMAC0_HWSCH_R0_TESTBUS_1548___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1548__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1548__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1549 (0x00AABB18) +#define WMAC0_HWSCH_R0_TESTBUS_1549___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1549__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1549__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1550 (0x00AABB1C) +#define WMAC0_HWSCH_R0_TESTBUS_1550___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1550__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1550__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1551 (0x00AABB20) +#define WMAC0_HWSCH_R0_TESTBUS_1551___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1551__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1551__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1552 (0x00AABB24) +#define WMAC0_HWSCH_R0_TESTBUS_1552___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1552__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1552__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1553 (0x00AABB28) +#define WMAC0_HWSCH_R0_TESTBUS_1553___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1553__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1553__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1554 (0x00AABB2C) +#define WMAC0_HWSCH_R0_TESTBUS_1554___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1554__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1554__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1555 (0x00AABB30) +#define WMAC0_HWSCH_R0_TESTBUS_1555___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1555__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1555__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1556 (0x00AABB34) +#define WMAC0_HWSCH_R0_TESTBUS_1556___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1556__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1556__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1557 (0x00AABB38) +#define WMAC0_HWSCH_R0_TESTBUS_1557___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1557__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1557__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1558 (0x00AABB3C) +#define WMAC0_HWSCH_R0_TESTBUS_1558___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1558__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1558__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1559 (0x00AABB40) +#define WMAC0_HWSCH_R0_TESTBUS_1559___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1559__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1559__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1560 (0x00AABB44) +#define WMAC0_HWSCH_R0_TESTBUS_1560___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1560__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1560__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1561 (0x00AABB48) +#define WMAC0_HWSCH_R0_TESTBUS_1561___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1561__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1561__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1562 (0x00AABB4C) +#define WMAC0_HWSCH_R0_TESTBUS_1562___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1562__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1562__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1563 (0x00AABB50) +#define WMAC0_HWSCH_R0_TESTBUS_1563___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1563__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1563__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1564 (0x00AABB54) +#define WMAC0_HWSCH_R0_TESTBUS_1564___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1564__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1564__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1565 (0x00AABB58) +#define WMAC0_HWSCH_R0_TESTBUS_1565___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1565__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1565__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1566 (0x00AABB5C) +#define WMAC0_HWSCH_R0_TESTBUS_1566___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1566__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1566__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1567 (0x00AABB60) +#define WMAC0_HWSCH_R0_TESTBUS_1567___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1567__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1567__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1568 (0x00AABB64) +#define WMAC0_HWSCH_R0_TESTBUS_1568___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1568__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1568__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1569 (0x00AABB68) +#define WMAC0_HWSCH_R0_TESTBUS_1569___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1569__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1569__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1570 (0x00AABB6C) +#define WMAC0_HWSCH_R0_TESTBUS_1570___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1570__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1570__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1571 (0x00AABB70) +#define WMAC0_HWSCH_R0_TESTBUS_1571___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1571__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1571__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1572 (0x00AABB74) +#define WMAC0_HWSCH_R0_TESTBUS_1572___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1572__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1572__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1573 (0x00AABB78) +#define WMAC0_HWSCH_R0_TESTBUS_1573___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1573__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1573__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1574 (0x00AABB7C) +#define WMAC0_HWSCH_R0_TESTBUS_1574___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1574__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1574__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1575 (0x00AABB80) +#define WMAC0_HWSCH_R0_TESTBUS_1575___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1575__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1575__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1576 (0x00AABB84) +#define WMAC0_HWSCH_R0_TESTBUS_1576___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1576__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1576__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1577 (0x00AABB88) +#define WMAC0_HWSCH_R0_TESTBUS_1577___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1577__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1577__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1578 (0x00AABB8C) +#define WMAC0_HWSCH_R0_TESTBUS_1578___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1578__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1578__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1579 (0x00AABB90) +#define WMAC0_HWSCH_R0_TESTBUS_1579___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1579__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1579__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1580 (0x00AABB94) +#define WMAC0_HWSCH_R0_TESTBUS_1580___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1580__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1580__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1581 (0x00AABB98) +#define WMAC0_HWSCH_R0_TESTBUS_1581___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1581__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1581__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1582 (0x00AABB9C) +#define WMAC0_HWSCH_R0_TESTBUS_1582___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1582__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1582__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1583 (0x00AABBA0) +#define WMAC0_HWSCH_R0_TESTBUS_1583___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1583__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1583__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1584 (0x00AABBA4) +#define WMAC0_HWSCH_R0_TESTBUS_1584___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1584__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1584__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1585 (0x00AABBA8) +#define WMAC0_HWSCH_R0_TESTBUS_1585___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1585__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1585__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1586 (0x00AABBAC) +#define WMAC0_HWSCH_R0_TESTBUS_1586___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1586__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1586__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1587 (0x00AABBB0) +#define WMAC0_HWSCH_R0_TESTBUS_1587___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1587__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1587__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1588 (0x00AABBB4) +#define WMAC0_HWSCH_R0_TESTBUS_1588___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1588__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1588__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1589 (0x00AABBB8) +#define WMAC0_HWSCH_R0_TESTBUS_1589___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1589__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1589__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1590 (0x00AABBBC) +#define WMAC0_HWSCH_R0_TESTBUS_1590___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1590__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1590__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1591 (0x00AABBC0) +#define WMAC0_HWSCH_R0_TESTBUS_1591___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1591__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1591__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1592 (0x00AABBC4) +#define WMAC0_HWSCH_R0_TESTBUS_1592___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1592__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1592__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1593 (0x00AABBC8) +#define WMAC0_HWSCH_R0_TESTBUS_1593___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1593__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1593__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1594 (0x00AABBCC) +#define WMAC0_HWSCH_R0_TESTBUS_1594___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1594__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1594__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1595 (0x00AABBD0) +#define WMAC0_HWSCH_R0_TESTBUS_1595___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1595__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1595__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1596 (0x00AABBD4) +#define WMAC0_HWSCH_R0_TESTBUS_1596___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1596__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1596__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1597 (0x00AABBD8) +#define WMAC0_HWSCH_R0_TESTBUS_1597___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1597__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1597__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1598 (0x00AABBDC) +#define WMAC0_HWSCH_R0_TESTBUS_1598___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1598__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1598__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1599 (0x00AABBE0) +#define WMAC0_HWSCH_R0_TESTBUS_1599___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1599__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1599__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1600 (0x00AABBE4) +#define WMAC0_HWSCH_R0_TESTBUS_1600___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1600__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1600__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1601 (0x00AABBE8) +#define WMAC0_HWSCH_R0_TESTBUS_1601___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1601__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1601__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1602 (0x00AABBEC) +#define WMAC0_HWSCH_R0_TESTBUS_1602___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1602__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1602__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1603 (0x00AABBF0) +#define WMAC0_HWSCH_R0_TESTBUS_1603___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1603__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1603__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1604 (0x00AABBF4) +#define WMAC0_HWSCH_R0_TESTBUS_1604___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1604__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1604__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1605 (0x00AABBF8) +#define WMAC0_HWSCH_R0_TESTBUS_1605___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1605__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1605__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1606 (0x00AABBFC) +#define WMAC0_HWSCH_R0_TESTBUS_1606___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1606__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1606__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1607 (0x00AABC00) +#define WMAC0_HWSCH_R0_TESTBUS_1607___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1607__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1607__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1608 (0x00AABC04) +#define WMAC0_HWSCH_R0_TESTBUS_1608___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1608__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1608__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1609 (0x00AABC08) +#define WMAC0_HWSCH_R0_TESTBUS_1609___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1609__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1609__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1610 (0x00AABC0C) +#define WMAC0_HWSCH_R0_TESTBUS_1610___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1610__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1610__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1611 (0x00AABC10) +#define WMAC0_HWSCH_R0_TESTBUS_1611___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1611__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1611__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1612 (0x00AABC14) +#define WMAC0_HWSCH_R0_TESTBUS_1612___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1612__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1612__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1613 (0x00AABC18) +#define WMAC0_HWSCH_R0_TESTBUS_1613___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1613__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1613__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1614 (0x00AABC1C) +#define WMAC0_HWSCH_R0_TESTBUS_1614___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1614__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1614__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1615 (0x00AABC20) +#define WMAC0_HWSCH_R0_TESTBUS_1615___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1615__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1615__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1616 (0x00AABC24) +#define WMAC0_HWSCH_R0_TESTBUS_1616___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1616__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1616__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1617 (0x00AABC28) +#define WMAC0_HWSCH_R0_TESTBUS_1617___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1617__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1617__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1618 (0x00AABC2C) +#define WMAC0_HWSCH_R0_TESTBUS_1618___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1618__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1618__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1619 (0x00AABC30) +#define WMAC0_HWSCH_R0_TESTBUS_1619___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1619__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1619__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1620 (0x00AABC34) +#define WMAC0_HWSCH_R0_TESTBUS_1620___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1620__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1620__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1621 (0x00AABC38) +#define WMAC0_HWSCH_R0_TESTBUS_1621___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1621__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1621__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1622 (0x00AABC3C) +#define WMAC0_HWSCH_R0_TESTBUS_1622___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1622__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1622__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1623 (0x00AABC40) +#define WMAC0_HWSCH_R0_TESTBUS_1623___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1623__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1623__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1624 (0x00AABC44) +#define WMAC0_HWSCH_R0_TESTBUS_1624___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1624__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1624__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1625 (0x00AABC48) +#define WMAC0_HWSCH_R0_TESTBUS_1625___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1625__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1625__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1626 (0x00AABC4C) +#define WMAC0_HWSCH_R0_TESTBUS_1626___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1626__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1626__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1627 (0x00AABC50) +#define WMAC0_HWSCH_R0_TESTBUS_1627___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1627__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1627__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1628 (0x00AABC54) +#define WMAC0_HWSCH_R0_TESTBUS_1628___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1628__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1628__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1629 (0x00AABC58) +#define WMAC0_HWSCH_R0_TESTBUS_1629___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1629__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1629__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1630 (0x00AABC5C) +#define WMAC0_HWSCH_R0_TESTBUS_1630___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1630__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1630__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1631 (0x00AABC60) +#define WMAC0_HWSCH_R0_TESTBUS_1631___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1631__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1631__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1632 (0x00AABC64) +#define WMAC0_HWSCH_R0_TESTBUS_1632___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1632__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1632__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1633 (0x00AABC68) +#define WMAC0_HWSCH_R0_TESTBUS_1633___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1633__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1633__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1634 (0x00AABC6C) +#define WMAC0_HWSCH_R0_TESTBUS_1634___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1634__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1634__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1635 (0x00AABC70) +#define WMAC0_HWSCH_R0_TESTBUS_1635___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1635__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1635__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1636 (0x00AABC74) +#define WMAC0_HWSCH_R0_TESTBUS_1636___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1636__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1636__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1637 (0x00AABC78) +#define WMAC0_HWSCH_R0_TESTBUS_1637___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1637__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1637__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1638 (0x00AABC7C) +#define WMAC0_HWSCH_R0_TESTBUS_1638___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1638__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1638__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1639 (0x00AABC80) +#define WMAC0_HWSCH_R0_TESTBUS_1639___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1639__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1639__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1640 (0x00AABC84) +#define WMAC0_HWSCH_R0_TESTBUS_1640___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1640__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1640__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1641 (0x00AABC88) +#define WMAC0_HWSCH_R0_TESTBUS_1641___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1641__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1641__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1642 (0x00AABC8C) +#define WMAC0_HWSCH_R0_TESTBUS_1642___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1642__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1642__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1643 (0x00AABC90) +#define WMAC0_HWSCH_R0_TESTBUS_1643___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1643__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1643__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1644 (0x00AABC94) +#define WMAC0_HWSCH_R0_TESTBUS_1644___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1644__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1644__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1645 (0x00AABC98) +#define WMAC0_HWSCH_R0_TESTBUS_1645___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1645__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1645__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1646 (0x00AABC9C) +#define WMAC0_HWSCH_R0_TESTBUS_1646___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1646__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1646__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1647 (0x00AABCA0) +#define WMAC0_HWSCH_R0_TESTBUS_1647___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1647__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1647__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1648 (0x00AABCA4) +#define WMAC0_HWSCH_R0_TESTBUS_1648___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1648__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1648__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1649 (0x00AABCA8) +#define WMAC0_HWSCH_R0_TESTBUS_1649___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1649__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1649__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1650 (0x00AABCAC) +#define WMAC0_HWSCH_R0_TESTBUS_1650___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1650__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1650__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1651 (0x00AABCB0) +#define WMAC0_HWSCH_R0_TESTBUS_1651___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1651__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1651__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1652 (0x00AABCB4) +#define WMAC0_HWSCH_R0_TESTBUS_1652___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1652__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1652__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1653 (0x00AABCB8) +#define WMAC0_HWSCH_R0_TESTBUS_1653___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1653__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1653__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1654 (0x00AABCBC) +#define WMAC0_HWSCH_R0_TESTBUS_1654___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1654__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1654__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1655 (0x00AABCC0) +#define WMAC0_HWSCH_R0_TESTBUS_1655___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1655__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1655__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1656 (0x00AABCC4) +#define WMAC0_HWSCH_R0_TESTBUS_1656___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1656__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1656__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1657 (0x00AABCC8) +#define WMAC0_HWSCH_R0_TESTBUS_1657___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1657__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1657__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1658 (0x00AABCCC) +#define WMAC0_HWSCH_R0_TESTBUS_1658___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1658__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1658__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1659 (0x00AABCD0) +#define WMAC0_HWSCH_R0_TESTBUS_1659___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1659__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1659__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1660 (0x00AABCD4) +#define WMAC0_HWSCH_R0_TESTBUS_1660___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1660__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1660__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1661 (0x00AABCD8) +#define WMAC0_HWSCH_R0_TESTBUS_1661___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1661__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1661__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1662 (0x00AABCDC) +#define WMAC0_HWSCH_R0_TESTBUS_1662___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1662__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1662__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1663 (0x00AABCE0) +#define WMAC0_HWSCH_R0_TESTBUS_1663___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1663__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1663__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1664 (0x00AABCE4) +#define WMAC0_HWSCH_R0_TESTBUS_1664___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1664__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1664__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1665 (0x00AABCE8) +#define WMAC0_HWSCH_R0_TESTBUS_1665___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1665__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1665__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1666 (0x00AABCEC) +#define WMAC0_HWSCH_R0_TESTBUS_1666___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1666__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1666__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1667 (0x00AABCF0) +#define WMAC0_HWSCH_R0_TESTBUS_1667___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1667__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1667__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1668 (0x00AABCF4) +#define WMAC0_HWSCH_R0_TESTBUS_1668___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1668__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1668__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1669 (0x00AABCF8) +#define WMAC0_HWSCH_R0_TESTBUS_1669___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1669__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1669__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1670 (0x00AABCFC) +#define WMAC0_HWSCH_R0_TESTBUS_1670___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1670__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1670__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1671 (0x00AABD00) +#define WMAC0_HWSCH_R0_TESTBUS_1671___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1671__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1671__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1672 (0x00AABD04) +#define WMAC0_HWSCH_R0_TESTBUS_1672___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1672__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1672__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1673 (0x00AABD08) +#define WMAC0_HWSCH_R0_TESTBUS_1673___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1673__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1673__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1674 (0x00AABD0C) +#define WMAC0_HWSCH_R0_TESTBUS_1674___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1674__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1674__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1675 (0x00AABD10) +#define WMAC0_HWSCH_R0_TESTBUS_1675___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1675__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1675__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1676 (0x00AABD14) +#define WMAC0_HWSCH_R0_TESTBUS_1676___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1676__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1676__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1677 (0x00AABD18) +#define WMAC0_HWSCH_R0_TESTBUS_1677___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1677__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1677__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1678 (0x00AABD1C) +#define WMAC0_HWSCH_R0_TESTBUS_1678___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1678__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1678__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1679 (0x00AABD20) +#define WMAC0_HWSCH_R0_TESTBUS_1679___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1679__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1679__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1680 (0x00AABD24) +#define WMAC0_HWSCH_R0_TESTBUS_1680___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1680__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1680__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1681 (0x00AABD28) +#define WMAC0_HWSCH_R0_TESTBUS_1681___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1681__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1681__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1682 (0x00AABD2C) +#define WMAC0_HWSCH_R0_TESTBUS_1682___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1682__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1682__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1683 (0x00AABD30) +#define WMAC0_HWSCH_R0_TESTBUS_1683___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1683__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1683__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1684 (0x00AABD34) +#define WMAC0_HWSCH_R0_TESTBUS_1684___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1684__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1684__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1685 (0x00AABD38) +#define WMAC0_HWSCH_R0_TESTBUS_1685___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1685__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1685__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1686 (0x00AABD3C) +#define WMAC0_HWSCH_R0_TESTBUS_1686___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1686__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1686__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1687 (0x00AABD40) +#define WMAC0_HWSCH_R0_TESTBUS_1687___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1687__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1687__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1688 (0x00AABD44) +#define WMAC0_HWSCH_R0_TESTBUS_1688___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1688__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1688__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1689 (0x00AABD48) +#define WMAC0_HWSCH_R0_TESTBUS_1689___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1689__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1689__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1690 (0x00AABD4C) +#define WMAC0_HWSCH_R0_TESTBUS_1690___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1690__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1690__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1691 (0x00AABD50) +#define WMAC0_HWSCH_R0_TESTBUS_1691___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1691__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1691__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1692 (0x00AABD54) +#define WMAC0_HWSCH_R0_TESTBUS_1692___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1692__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1692__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1693 (0x00AABD58) +#define WMAC0_HWSCH_R0_TESTBUS_1693___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1693__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1693__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1694 (0x00AABD5C) +#define WMAC0_HWSCH_R0_TESTBUS_1694___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1694__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1694__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1695 (0x00AABD60) +#define WMAC0_HWSCH_R0_TESTBUS_1695___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1695__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1695__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1696 (0x00AABD64) +#define WMAC0_HWSCH_R0_TESTBUS_1696___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1696__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1696__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1697 (0x00AABD68) +#define WMAC0_HWSCH_R0_TESTBUS_1697___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1697__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1697__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1698 (0x00AABD6C) +#define WMAC0_HWSCH_R0_TESTBUS_1698___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1698__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1698__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1699 (0x00AABD70) +#define WMAC0_HWSCH_R0_TESTBUS_1699___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1699__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1699__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1700 (0x00AABD74) +#define WMAC0_HWSCH_R0_TESTBUS_1700___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1700__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1700__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1701 (0x00AABD78) +#define WMAC0_HWSCH_R0_TESTBUS_1701___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1701__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1701__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1702 (0x00AABD7C) +#define WMAC0_HWSCH_R0_TESTBUS_1702___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1702__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1702__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1703 (0x00AABD80) +#define WMAC0_HWSCH_R0_TESTBUS_1703___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1703__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1703__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1704 (0x00AABD84) +#define WMAC0_HWSCH_R0_TESTBUS_1704___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1704__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1704__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1705 (0x00AABD88) +#define WMAC0_HWSCH_R0_TESTBUS_1705___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1705__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1705__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1706 (0x00AABD8C) +#define WMAC0_HWSCH_R0_TESTBUS_1706___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1706__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1706__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1707 (0x00AABD90) +#define WMAC0_HWSCH_R0_TESTBUS_1707___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1707__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1707__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1708 (0x00AABD94) +#define WMAC0_HWSCH_R0_TESTBUS_1708___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1708__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1708__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1709 (0x00AABD98) +#define WMAC0_HWSCH_R0_TESTBUS_1709___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1709__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1709__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1710 (0x00AABD9C) +#define WMAC0_HWSCH_R0_TESTBUS_1710___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1710__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1710__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1711 (0x00AABDA0) +#define WMAC0_HWSCH_R0_TESTBUS_1711___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1711__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1711__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1712 (0x00AABDA4) +#define WMAC0_HWSCH_R0_TESTBUS_1712___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1712__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1712__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1713 (0x00AABDA8) +#define WMAC0_HWSCH_R0_TESTBUS_1713___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1713__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1713__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1714 (0x00AABDAC) +#define WMAC0_HWSCH_R0_TESTBUS_1714___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1714__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1714__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1715 (0x00AABDB0) +#define WMAC0_HWSCH_R0_TESTBUS_1715___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1715__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1715__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1716 (0x00AABDB4) +#define WMAC0_HWSCH_R0_TESTBUS_1716___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1716__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1716__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1717 (0x00AABDB8) +#define WMAC0_HWSCH_R0_TESTBUS_1717___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1717__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1717__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1718 (0x00AABDBC) +#define WMAC0_HWSCH_R0_TESTBUS_1718___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1718__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1718__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1719 (0x00AABDC0) +#define WMAC0_HWSCH_R0_TESTBUS_1719___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1719__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1719__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1720 (0x00AABDC4) +#define WMAC0_HWSCH_R0_TESTBUS_1720___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1720__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1720__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1721 (0x00AABDC8) +#define WMAC0_HWSCH_R0_TESTBUS_1721___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1721__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1721__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1722 (0x00AABDCC) +#define WMAC0_HWSCH_R0_TESTBUS_1722___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1722__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1722__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1723 (0x00AABDD0) +#define WMAC0_HWSCH_R0_TESTBUS_1723___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1723__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1723__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1724 (0x00AABDD4) +#define WMAC0_HWSCH_R0_TESTBUS_1724___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1724__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1724__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1725 (0x00AABDD8) +#define WMAC0_HWSCH_R0_TESTBUS_1725___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1725__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1725__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1726 (0x00AABDDC) +#define WMAC0_HWSCH_R0_TESTBUS_1726___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1726__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1726__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1727 (0x00AABDE0) +#define WMAC0_HWSCH_R0_TESTBUS_1727___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1727__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1727__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1728 (0x00AABDE4) +#define WMAC0_HWSCH_R0_TESTBUS_1728___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1728__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1728__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1729 (0x00AABDE8) +#define WMAC0_HWSCH_R0_TESTBUS_1729___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1729__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1729__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1730 (0x00AABDEC) +#define WMAC0_HWSCH_R0_TESTBUS_1730___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1730__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1730__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1731 (0x00AABDF0) +#define WMAC0_HWSCH_R0_TESTBUS_1731___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1731__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1731__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1732 (0x00AABDF4) +#define WMAC0_HWSCH_R0_TESTBUS_1732___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1732__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1732__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1733 (0x00AABDF8) +#define WMAC0_HWSCH_R0_TESTBUS_1733___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1733__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1733__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1734 (0x00AABDFC) +#define WMAC0_HWSCH_R0_TESTBUS_1734___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1734__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1734__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1735 (0x00AABE00) +#define WMAC0_HWSCH_R0_TESTBUS_1735___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1735__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1735__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1736 (0x00AABE04) +#define WMAC0_HWSCH_R0_TESTBUS_1736___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1736__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1736__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1737 (0x00AABE08) +#define WMAC0_HWSCH_R0_TESTBUS_1737___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1737__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1737__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1738 (0x00AABE0C) +#define WMAC0_HWSCH_R0_TESTBUS_1738___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1738__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1738__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1739 (0x00AABE10) +#define WMAC0_HWSCH_R0_TESTBUS_1739___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1739__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1739__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1740 (0x00AABE14) +#define WMAC0_HWSCH_R0_TESTBUS_1740___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1740__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1740__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1741 (0x00AABE18) +#define WMAC0_HWSCH_R0_TESTBUS_1741___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1741__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1741__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1742 (0x00AABE1C) +#define WMAC0_HWSCH_R0_TESTBUS_1742___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1742__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1742__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1743 (0x00AABE20) +#define WMAC0_HWSCH_R0_TESTBUS_1743___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1743__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1743__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1744 (0x00AABE24) +#define WMAC0_HWSCH_R0_TESTBUS_1744___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1744__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1744__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1745 (0x00AABE28) +#define WMAC0_HWSCH_R0_TESTBUS_1745___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1745__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1745__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1746 (0x00AABE2C) +#define WMAC0_HWSCH_R0_TESTBUS_1746___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1746__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1746__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1747 (0x00AABE30) +#define WMAC0_HWSCH_R0_TESTBUS_1747___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1747__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1747__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1748 (0x00AABE34) +#define WMAC0_HWSCH_R0_TESTBUS_1748___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1748__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1748__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1749 (0x00AABE38) +#define WMAC0_HWSCH_R0_TESTBUS_1749___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1749__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1749__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1750 (0x00AABE3C) +#define WMAC0_HWSCH_R0_TESTBUS_1750___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1750__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1750__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1751 (0x00AABE40) +#define WMAC0_HWSCH_R0_TESTBUS_1751___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1751__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1751__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1752 (0x00AABE44) +#define WMAC0_HWSCH_R0_TESTBUS_1752___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1752__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1752__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1753 (0x00AABE48) +#define WMAC0_HWSCH_R0_TESTBUS_1753___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1753__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1753__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1754 (0x00AABE4C) +#define WMAC0_HWSCH_R0_TESTBUS_1754___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1754__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1754__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1755 (0x00AABE50) +#define WMAC0_HWSCH_R0_TESTBUS_1755___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1755__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1755__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1756 (0x00AABE54) +#define WMAC0_HWSCH_R0_TESTBUS_1756___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1756__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1756__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1757 (0x00AABE58) +#define WMAC0_HWSCH_R0_TESTBUS_1757___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1757__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1757__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1758 (0x00AABE5C) +#define WMAC0_HWSCH_R0_TESTBUS_1758___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1758__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1758__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1759 (0x00AABE60) +#define WMAC0_HWSCH_R0_TESTBUS_1759___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1759__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1759__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1760 (0x00AABE64) +#define WMAC0_HWSCH_R0_TESTBUS_1760___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1760__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1760__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1761 (0x00AABE68) +#define WMAC0_HWSCH_R0_TESTBUS_1761___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1761__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1761__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1762 (0x00AABE6C) +#define WMAC0_HWSCH_R0_TESTBUS_1762___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1762__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1762__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1763 (0x00AABE70) +#define WMAC0_HWSCH_R0_TESTBUS_1763___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1763__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1763__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1764 (0x00AABE74) +#define WMAC0_HWSCH_R0_TESTBUS_1764___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1764__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1764__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1765 (0x00AABE78) +#define WMAC0_HWSCH_R0_TESTBUS_1765___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1765__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1765__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1766 (0x00AABE7C) +#define WMAC0_HWSCH_R0_TESTBUS_1766___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1766__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1766__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1767 (0x00AABE80) +#define WMAC0_HWSCH_R0_TESTBUS_1767___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1767__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1767__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1768 (0x00AABE84) +#define WMAC0_HWSCH_R0_TESTBUS_1768___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1768__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1768__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1769 (0x00AABE88) +#define WMAC0_HWSCH_R0_TESTBUS_1769___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1769__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1769__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1770 (0x00AABE8C) +#define WMAC0_HWSCH_R0_TESTBUS_1770___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1770__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1770__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1771 (0x00AABE90) +#define WMAC0_HWSCH_R0_TESTBUS_1771___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1771__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1771__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1772 (0x00AABE94) +#define WMAC0_HWSCH_R0_TESTBUS_1772___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1772__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1772__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1773 (0x00AABE98) +#define WMAC0_HWSCH_R0_TESTBUS_1773___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1773__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1773__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1774 (0x00AABE9C) +#define WMAC0_HWSCH_R0_TESTBUS_1774___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1774__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1774__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1775 (0x00AABEA0) +#define WMAC0_HWSCH_R0_TESTBUS_1775___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1775__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1775__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1776 (0x00AABEA4) +#define WMAC0_HWSCH_R0_TESTBUS_1776___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1776__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1776__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1777 (0x00AABEA8) +#define WMAC0_HWSCH_R0_TESTBUS_1777___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1777__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1777__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1778 (0x00AABEAC) +#define WMAC0_HWSCH_R0_TESTBUS_1778___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1778__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1778__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1779 (0x00AABEB0) +#define WMAC0_HWSCH_R0_TESTBUS_1779___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1779__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1779__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1780 (0x00AABEB4) +#define WMAC0_HWSCH_R0_TESTBUS_1780___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1780__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1780__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1781 (0x00AABEB8) +#define WMAC0_HWSCH_R0_TESTBUS_1781___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1781__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1781__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1782 (0x00AABEBC) +#define WMAC0_HWSCH_R0_TESTBUS_1782___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1782__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1782__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1783 (0x00AABEC0) +#define WMAC0_HWSCH_R0_TESTBUS_1783___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1783__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1783__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1784 (0x00AABEC4) +#define WMAC0_HWSCH_R0_TESTBUS_1784___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1784__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1784__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1785 (0x00AABEC8) +#define WMAC0_HWSCH_R0_TESTBUS_1785___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1785__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1785__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1786 (0x00AABECC) +#define WMAC0_HWSCH_R0_TESTBUS_1786___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1786__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1786__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1787 (0x00AABED0) +#define WMAC0_HWSCH_R0_TESTBUS_1787___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1787__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1787__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1788 (0x00AABED4) +#define WMAC0_HWSCH_R0_TESTBUS_1788___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1788__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1788__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1789 (0x00AABED8) +#define WMAC0_HWSCH_R0_TESTBUS_1789___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1789__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1789__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1790 (0x00AABEDC) +#define WMAC0_HWSCH_R0_TESTBUS_1790___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1790__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1790__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1791 (0x00AABEE0) +#define WMAC0_HWSCH_R0_TESTBUS_1791___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1791__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1791__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1792 (0x00AABEE4) +#define WMAC0_HWSCH_R0_TESTBUS_1792___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1792__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1792__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1793 (0x00AABEE8) +#define WMAC0_HWSCH_R0_TESTBUS_1793___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1793__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1793__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1794 (0x00AABEEC) +#define WMAC0_HWSCH_R0_TESTBUS_1794___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1794__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1794__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1795 (0x00AABEF0) +#define WMAC0_HWSCH_R0_TESTBUS_1795___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1795__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1795__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1796 (0x00AABEF4) +#define WMAC0_HWSCH_R0_TESTBUS_1796___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1796__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1796__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1797 (0x00AABEF8) +#define WMAC0_HWSCH_R0_TESTBUS_1797___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1797__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1797__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1798 (0x00AABEFC) +#define WMAC0_HWSCH_R0_TESTBUS_1798___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1798__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1798__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1799 (0x00AABF00) +#define WMAC0_HWSCH_R0_TESTBUS_1799___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1799__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1799__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1800 (0x00AABF04) +#define WMAC0_HWSCH_R0_TESTBUS_1800___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1800__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1800__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1801 (0x00AABF08) +#define WMAC0_HWSCH_R0_TESTBUS_1801___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1801__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1801__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1802 (0x00AABF0C) +#define WMAC0_HWSCH_R0_TESTBUS_1802___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1802__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1802__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1803 (0x00AABF10) +#define WMAC0_HWSCH_R0_TESTBUS_1803___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1803__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1803__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1804 (0x00AABF14) +#define WMAC0_HWSCH_R0_TESTBUS_1804___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1804__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1804__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1805 (0x00AABF18) +#define WMAC0_HWSCH_R0_TESTBUS_1805___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1805__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1805__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1806 (0x00AABF1C) +#define WMAC0_HWSCH_R0_TESTBUS_1806___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1806__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1806__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1807 (0x00AABF20) +#define WMAC0_HWSCH_R0_TESTBUS_1807___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1807__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1807__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1808 (0x00AABF24) +#define WMAC0_HWSCH_R0_TESTBUS_1808___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1808__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1808__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1809 (0x00AABF28) +#define WMAC0_HWSCH_R0_TESTBUS_1809___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1809__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1809__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1810 (0x00AABF2C) +#define WMAC0_HWSCH_R0_TESTBUS_1810___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1810__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1810__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1811 (0x00AABF30) +#define WMAC0_HWSCH_R0_TESTBUS_1811___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1811__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1811__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1812 (0x00AABF34) +#define WMAC0_HWSCH_R0_TESTBUS_1812___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1812__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1812__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1813 (0x00AABF38) +#define WMAC0_HWSCH_R0_TESTBUS_1813___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1813__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1813__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1814 (0x00AABF3C) +#define WMAC0_HWSCH_R0_TESTBUS_1814___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1814__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1814__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1815 (0x00AABF40) +#define WMAC0_HWSCH_R0_TESTBUS_1815___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1815__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1815__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1816 (0x00AABF44) +#define WMAC0_HWSCH_R0_TESTBUS_1816___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1816__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1816__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1817 (0x00AABF48) +#define WMAC0_HWSCH_R0_TESTBUS_1817___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1817__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1817__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1818 (0x00AABF4C) +#define WMAC0_HWSCH_R0_TESTBUS_1818___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1818__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1818__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1819 (0x00AABF50) +#define WMAC0_HWSCH_R0_TESTBUS_1819___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1819__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1819__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1820 (0x00AABF54) +#define WMAC0_HWSCH_R0_TESTBUS_1820___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1820__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1820__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1821 (0x00AABF58) +#define WMAC0_HWSCH_R0_TESTBUS_1821___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1821__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1821__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1822 (0x00AABF5C) +#define WMAC0_HWSCH_R0_TESTBUS_1822___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1822__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1822__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1823 (0x00AABF60) +#define WMAC0_HWSCH_R0_TESTBUS_1823___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1823__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1823__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1824 (0x00AABF64) +#define WMAC0_HWSCH_R0_TESTBUS_1824___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1824__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1824__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1825 (0x00AABF68) +#define WMAC0_HWSCH_R0_TESTBUS_1825___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1825__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1825__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1826 (0x00AABF6C) +#define WMAC0_HWSCH_R0_TESTBUS_1826___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1826__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1826__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1827 (0x00AABF70) +#define WMAC0_HWSCH_R0_TESTBUS_1827___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1827__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1827__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1828 (0x00AABF74) +#define WMAC0_HWSCH_R0_TESTBUS_1828___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1828__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1828__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1829 (0x00AABF78) +#define WMAC0_HWSCH_R0_TESTBUS_1829___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1829__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1829__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1830 (0x00AABF7C) +#define WMAC0_HWSCH_R0_TESTBUS_1830___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1830__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1830__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1831 (0x00AABF80) +#define WMAC0_HWSCH_R0_TESTBUS_1831___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1831__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1831__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1832 (0x00AABF84) +#define WMAC0_HWSCH_R0_TESTBUS_1832___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1832__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1832__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1833 (0x00AABF88) +#define WMAC0_HWSCH_R0_TESTBUS_1833___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1833__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1833__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1834 (0x00AABF8C) +#define WMAC0_HWSCH_R0_TESTBUS_1834___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1834__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1834__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1835 (0x00AABF90) +#define WMAC0_HWSCH_R0_TESTBUS_1835___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1835__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1835__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1836 (0x00AABF94) +#define WMAC0_HWSCH_R0_TESTBUS_1836___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1836__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1836__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1837 (0x00AABF98) +#define WMAC0_HWSCH_R0_TESTBUS_1837___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1837__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1837__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1838 (0x00AABF9C) +#define WMAC0_HWSCH_R0_TESTBUS_1838___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1838__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1838__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1839 (0x00AABFA0) +#define WMAC0_HWSCH_R0_TESTBUS_1839___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1839__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1839__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1840 (0x00AABFA4) +#define WMAC0_HWSCH_R0_TESTBUS_1840___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1840__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1840__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1841 (0x00AABFA8) +#define WMAC0_HWSCH_R0_TESTBUS_1841___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1841__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1841__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1842 (0x00AABFAC) +#define WMAC0_HWSCH_R0_TESTBUS_1842___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1842__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1842__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1843 (0x00AABFB0) +#define WMAC0_HWSCH_R0_TESTBUS_1843___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1843__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1843__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1844 (0x00AABFB4) +#define WMAC0_HWSCH_R0_TESTBUS_1844___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1844__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1844__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1845 (0x00AABFB8) +#define WMAC0_HWSCH_R0_TESTBUS_1845___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1845__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1845__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1846 (0x00AABFBC) +#define WMAC0_HWSCH_R0_TESTBUS_1846___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1846__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1846__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1847 (0x00AABFC0) +#define WMAC0_HWSCH_R0_TESTBUS_1847___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1847__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1847__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1848 (0x00AABFC4) +#define WMAC0_HWSCH_R0_TESTBUS_1848___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1848__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1848__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1849 (0x00AABFC8) +#define WMAC0_HWSCH_R0_TESTBUS_1849___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1849__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1849__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1850 (0x00AABFCC) +#define WMAC0_HWSCH_R0_TESTBUS_1850___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1850__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1850__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1851 (0x00AABFD0) +#define WMAC0_HWSCH_R0_TESTBUS_1851___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1851__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1851__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1852 (0x00AABFD4) +#define WMAC0_HWSCH_R0_TESTBUS_1852___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1852__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1852__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1853 (0x00AABFD8) +#define WMAC0_HWSCH_R0_TESTBUS_1853___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1853__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1853__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1854 (0x00AABFDC) +#define WMAC0_HWSCH_R0_TESTBUS_1854___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1854__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1854__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1855 (0x00AABFE0) +#define WMAC0_HWSCH_R0_TESTBUS_1855___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1855__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1855__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1856 (0x00AABFE4) +#define WMAC0_HWSCH_R0_TESTBUS_1856___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1856__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1856__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1857 (0x00AABFE8) +#define WMAC0_HWSCH_R0_TESTBUS_1857___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1857__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1857__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1858 (0x00AABFEC) +#define WMAC0_HWSCH_R0_TESTBUS_1858___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1858__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1858__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1859 (0x00AABFF0) +#define WMAC0_HWSCH_R0_TESTBUS_1859___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1859__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1859__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1860 (0x00AABFF4) +#define WMAC0_HWSCH_R0_TESTBUS_1860___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1860__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1860__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1861 (0x00AABFF8) +#define WMAC0_HWSCH_R0_TESTBUS_1861___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1861__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1861__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1862 (0x00AABFFC) +#define WMAC0_HWSCH_R0_TESTBUS_1862___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1862__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1862__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1863 (0x00AAC000) +#define WMAC0_HWSCH_R0_TESTBUS_1863___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1863__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1863__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1864 (0x00AAC004) +#define WMAC0_HWSCH_R0_TESTBUS_1864___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1864__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1864__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1865 (0x00AAC008) +#define WMAC0_HWSCH_R0_TESTBUS_1865___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1865__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1865__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1866 (0x00AAC00C) +#define WMAC0_HWSCH_R0_TESTBUS_1866___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1866__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1866__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1867 (0x00AAC010) +#define WMAC0_HWSCH_R0_TESTBUS_1867___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1867__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1867__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1868 (0x00AAC014) +#define WMAC0_HWSCH_R0_TESTBUS_1868___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1868__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1868__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1869 (0x00AAC018) +#define WMAC0_HWSCH_R0_TESTBUS_1869___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1869__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1869__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1870 (0x00AAC01C) +#define WMAC0_HWSCH_R0_TESTBUS_1870___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1870__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1870__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1871 (0x00AAC020) +#define WMAC0_HWSCH_R0_TESTBUS_1871___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1871__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1871__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1872 (0x00AAC024) +#define WMAC0_HWSCH_R0_TESTBUS_1872___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1872__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1872__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1873 (0x00AAC028) +#define WMAC0_HWSCH_R0_TESTBUS_1873___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1873__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1873__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1874 (0x00AAC02C) +#define WMAC0_HWSCH_R0_TESTBUS_1874___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1874__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1874__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1875 (0x00AAC030) +#define WMAC0_HWSCH_R0_TESTBUS_1875___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1875__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1875__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1876 (0x00AAC034) +#define WMAC0_HWSCH_R0_TESTBUS_1876___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1876__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1876__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1877 (0x00AAC038) +#define WMAC0_HWSCH_R0_TESTBUS_1877___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1877__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1877__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1878 (0x00AAC03C) +#define WMAC0_HWSCH_R0_TESTBUS_1878___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1878__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1878__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1879 (0x00AAC040) +#define WMAC0_HWSCH_R0_TESTBUS_1879___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1879__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1879__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1880 (0x00AAC044) +#define WMAC0_HWSCH_R0_TESTBUS_1880___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1880__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1880__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1881 (0x00AAC048) +#define WMAC0_HWSCH_R0_TESTBUS_1881___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1881__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1881__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1882 (0x00AAC04C) +#define WMAC0_HWSCH_R0_TESTBUS_1882___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1882__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1882__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1883 (0x00AAC050) +#define WMAC0_HWSCH_R0_TESTBUS_1883___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1883__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1883__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1884 (0x00AAC054) +#define WMAC0_HWSCH_R0_TESTBUS_1884___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1884__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1884__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1885 (0x00AAC058) +#define WMAC0_HWSCH_R0_TESTBUS_1885___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1885__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1885__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1886 (0x00AAC05C) +#define WMAC0_HWSCH_R0_TESTBUS_1886___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1886__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1886__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1887 (0x00AAC060) +#define WMAC0_HWSCH_R0_TESTBUS_1887___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1887__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1887__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1888 (0x00AAC064) +#define WMAC0_HWSCH_R0_TESTBUS_1888___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1888__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1888__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1889 (0x00AAC068) +#define WMAC0_HWSCH_R0_TESTBUS_1889___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1889__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1889__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1890 (0x00AAC06C) +#define WMAC0_HWSCH_R0_TESTBUS_1890___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1890__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1890__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1891 (0x00AAC070) +#define WMAC0_HWSCH_R0_TESTBUS_1891___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1891__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1891__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1892 (0x00AAC074) +#define WMAC0_HWSCH_R0_TESTBUS_1892___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1892__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1892__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1893 (0x00AAC078) +#define WMAC0_HWSCH_R0_TESTBUS_1893___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1893__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1893__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1894 (0x00AAC07C) +#define WMAC0_HWSCH_R0_TESTBUS_1894___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1894__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1894__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1895 (0x00AAC080) +#define WMAC0_HWSCH_R0_TESTBUS_1895___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1895__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1895__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1896 (0x00AAC084) +#define WMAC0_HWSCH_R0_TESTBUS_1896___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1896__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1896__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1897 (0x00AAC088) +#define WMAC0_HWSCH_R0_TESTBUS_1897___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1897__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1897__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1898 (0x00AAC08C) +#define WMAC0_HWSCH_R0_TESTBUS_1898___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1898__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1898__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1899 (0x00AAC090) +#define WMAC0_HWSCH_R0_TESTBUS_1899___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1899__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1899__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1900 (0x00AAC094) +#define WMAC0_HWSCH_R0_TESTBUS_1900___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1900__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1900__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1901 (0x00AAC098) +#define WMAC0_HWSCH_R0_TESTBUS_1901___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1901__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1901__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1902 (0x00AAC09C) +#define WMAC0_HWSCH_R0_TESTBUS_1902___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1902__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1902__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1903 (0x00AAC0A0) +#define WMAC0_HWSCH_R0_TESTBUS_1903___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1903__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1903__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1904 (0x00AAC0A4) +#define WMAC0_HWSCH_R0_TESTBUS_1904___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1904__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1904__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1905 (0x00AAC0A8) +#define WMAC0_HWSCH_R0_TESTBUS_1905___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1905__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1905__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1906 (0x00AAC0AC) +#define WMAC0_HWSCH_R0_TESTBUS_1906___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1906__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1906__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1907 (0x00AAC0B0) +#define WMAC0_HWSCH_R0_TESTBUS_1907___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1907__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1907__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1908 (0x00AAC0B4) +#define WMAC0_HWSCH_R0_TESTBUS_1908___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1908__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1908__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1909 (0x00AAC0B8) +#define WMAC0_HWSCH_R0_TESTBUS_1909___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1909__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1909__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1910 (0x00AAC0BC) +#define WMAC0_HWSCH_R0_TESTBUS_1910___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1910__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1910__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1911 (0x00AAC0C0) +#define WMAC0_HWSCH_R0_TESTBUS_1911___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1911__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1911__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1912 (0x00AAC0C4) +#define WMAC0_HWSCH_R0_TESTBUS_1912___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1912__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1912__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1913 (0x00AAC0C8) +#define WMAC0_HWSCH_R0_TESTBUS_1913___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1913__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1913__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1914 (0x00AAC0CC) +#define WMAC0_HWSCH_R0_TESTBUS_1914___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1914__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1914__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1915 (0x00AAC0D0) +#define WMAC0_HWSCH_R0_TESTBUS_1915___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1915__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1915__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1916 (0x00AAC0D4) +#define WMAC0_HWSCH_R0_TESTBUS_1916___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1916__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1916__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1917 (0x00AAC0D8) +#define WMAC0_HWSCH_R0_TESTBUS_1917___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1917__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1917__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1918 (0x00AAC0DC) +#define WMAC0_HWSCH_R0_TESTBUS_1918___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1918__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1918__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1919 (0x00AAC0E0) +#define WMAC0_HWSCH_R0_TESTBUS_1919___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1919__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1919__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1920 (0x00AAC0E4) +#define WMAC0_HWSCH_R0_TESTBUS_1920___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1920__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1920__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1921 (0x00AAC0E8) +#define WMAC0_HWSCH_R0_TESTBUS_1921___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1921__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1921__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1922 (0x00AAC0EC) +#define WMAC0_HWSCH_R0_TESTBUS_1922___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1922__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1922__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1923 (0x00AAC0F0) +#define WMAC0_HWSCH_R0_TESTBUS_1923___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1923__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1923__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1924 (0x00AAC0F4) +#define WMAC0_HWSCH_R0_TESTBUS_1924___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1924__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1924__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1925 (0x00AAC0F8) +#define WMAC0_HWSCH_R0_TESTBUS_1925___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1925__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1925__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1926 (0x00AAC0FC) +#define WMAC0_HWSCH_R0_TESTBUS_1926___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1926__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1926__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1927 (0x00AAC100) +#define WMAC0_HWSCH_R0_TESTBUS_1927___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1927__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1927__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1928 (0x00AAC104) +#define WMAC0_HWSCH_R0_TESTBUS_1928___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1928__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1928__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1929 (0x00AAC108) +#define WMAC0_HWSCH_R0_TESTBUS_1929___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1929__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1929__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1930 (0x00AAC10C) +#define WMAC0_HWSCH_R0_TESTBUS_1930___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1930__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1930__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1931 (0x00AAC110) +#define WMAC0_HWSCH_R0_TESTBUS_1931___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1931__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1931__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1932 (0x00AAC114) +#define WMAC0_HWSCH_R0_TESTBUS_1932___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1932__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1932__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1933 (0x00AAC118) +#define WMAC0_HWSCH_R0_TESTBUS_1933___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1933__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1933__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1934 (0x00AAC11C) +#define WMAC0_HWSCH_R0_TESTBUS_1934___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1934__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1934__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1935 (0x00AAC120) +#define WMAC0_HWSCH_R0_TESTBUS_1935___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1935__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1935__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1936 (0x00AAC124) +#define WMAC0_HWSCH_R0_TESTBUS_1936___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1936__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1936__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1937 (0x00AAC128) +#define WMAC0_HWSCH_R0_TESTBUS_1937___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1937__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1937__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1938 (0x00AAC12C) +#define WMAC0_HWSCH_R0_TESTBUS_1938___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1938__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1938__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1939 (0x00AAC130) +#define WMAC0_HWSCH_R0_TESTBUS_1939___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1939__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1939__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1940 (0x00AAC134) +#define WMAC0_HWSCH_R0_TESTBUS_1940___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1940__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1940__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1941 (0x00AAC138) +#define WMAC0_HWSCH_R0_TESTBUS_1941___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1941__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1941__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1942 (0x00AAC13C) +#define WMAC0_HWSCH_R0_TESTBUS_1942___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1942__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1942__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1943 (0x00AAC140) +#define WMAC0_HWSCH_R0_TESTBUS_1943___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1943__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1943__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1944 (0x00AAC144) +#define WMAC0_HWSCH_R0_TESTBUS_1944___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1944__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1944__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1945 (0x00AAC148) +#define WMAC0_HWSCH_R0_TESTBUS_1945___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1945__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1945__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1946 (0x00AAC14C) +#define WMAC0_HWSCH_R0_TESTBUS_1946___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1946__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1946__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1947 (0x00AAC150) +#define WMAC0_HWSCH_R0_TESTBUS_1947___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1947__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1947__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1948 (0x00AAC154) +#define WMAC0_HWSCH_R0_TESTBUS_1948___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1948__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1948__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1949 (0x00AAC158) +#define WMAC0_HWSCH_R0_TESTBUS_1949___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1949__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1949__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1950 (0x00AAC15C) +#define WMAC0_HWSCH_R0_TESTBUS_1950___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1950__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1950__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1951 (0x00AAC160) +#define WMAC0_HWSCH_R0_TESTBUS_1951___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1951__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1951__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1952 (0x00AAC164) +#define WMAC0_HWSCH_R0_TESTBUS_1952___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1952__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1952__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1953 (0x00AAC168) +#define WMAC0_HWSCH_R0_TESTBUS_1953___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1953__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1953__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1954 (0x00AAC16C) +#define WMAC0_HWSCH_R0_TESTBUS_1954___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1954__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1954__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1955 (0x00AAC170) +#define WMAC0_HWSCH_R0_TESTBUS_1955___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1955__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1955__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1956 (0x00AAC174) +#define WMAC0_HWSCH_R0_TESTBUS_1956___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1956__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1956__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1957 (0x00AAC178) +#define WMAC0_HWSCH_R0_TESTBUS_1957___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1957__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1957__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1958 (0x00AAC17C) +#define WMAC0_HWSCH_R0_TESTBUS_1958___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1958__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1958__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1959 (0x00AAC180) +#define WMAC0_HWSCH_R0_TESTBUS_1959___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1959__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1959__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1960 (0x00AAC184) +#define WMAC0_HWSCH_R0_TESTBUS_1960___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1960__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1960__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1961 (0x00AAC188) +#define WMAC0_HWSCH_R0_TESTBUS_1961___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1961__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1961__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1962 (0x00AAC18C) +#define WMAC0_HWSCH_R0_TESTBUS_1962___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1962__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1962__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1963 (0x00AAC190) +#define WMAC0_HWSCH_R0_TESTBUS_1963___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1963__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1963__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1964 (0x00AAC194) +#define WMAC0_HWSCH_R0_TESTBUS_1964___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1964__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1964__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1965 (0x00AAC198) +#define WMAC0_HWSCH_R0_TESTBUS_1965___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1965__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1965__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1966 (0x00AAC19C) +#define WMAC0_HWSCH_R0_TESTBUS_1966___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1966__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1966__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1967 (0x00AAC1A0) +#define WMAC0_HWSCH_R0_TESTBUS_1967___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1967__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1967__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1968 (0x00AAC1A4) +#define WMAC0_HWSCH_R0_TESTBUS_1968___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1968__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1968__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1969 (0x00AAC1A8) +#define WMAC0_HWSCH_R0_TESTBUS_1969___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1969__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1969__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1970 (0x00AAC1AC) +#define WMAC0_HWSCH_R0_TESTBUS_1970___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1970__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1970__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1971 (0x00AAC1B0) +#define WMAC0_HWSCH_R0_TESTBUS_1971___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1971__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1971__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1972 (0x00AAC1B4) +#define WMAC0_HWSCH_R0_TESTBUS_1972___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1972__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1972__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1973 (0x00AAC1B8) +#define WMAC0_HWSCH_R0_TESTBUS_1973___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1973__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1973__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1974 (0x00AAC1BC) +#define WMAC0_HWSCH_R0_TESTBUS_1974___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1974__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1974__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1975 (0x00AAC1C0) +#define WMAC0_HWSCH_R0_TESTBUS_1975___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1975__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1975__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1976 (0x00AAC1C4) +#define WMAC0_HWSCH_R0_TESTBUS_1976___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1976__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1976__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1977 (0x00AAC1C8) +#define WMAC0_HWSCH_R0_TESTBUS_1977___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1977__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1977__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1978 (0x00AAC1CC) +#define WMAC0_HWSCH_R0_TESTBUS_1978___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1978__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1978__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1979 (0x00AAC1D0) +#define WMAC0_HWSCH_R0_TESTBUS_1979___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1979__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1979__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1980 (0x00AAC1D4) +#define WMAC0_HWSCH_R0_TESTBUS_1980___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1980__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1980__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1981 (0x00AAC1D8) +#define WMAC0_HWSCH_R0_TESTBUS_1981___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1981__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1981__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1982 (0x00AAC1DC) +#define WMAC0_HWSCH_R0_TESTBUS_1982___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1982__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1982__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1983 (0x00AAC1E0) +#define WMAC0_HWSCH_R0_TESTBUS_1983___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1983__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1983__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1984 (0x00AAC1E4) +#define WMAC0_HWSCH_R0_TESTBUS_1984___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1984__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1984__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1985 (0x00AAC1E8) +#define WMAC0_HWSCH_R0_TESTBUS_1985___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1985__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1985__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1986 (0x00AAC1EC) +#define WMAC0_HWSCH_R0_TESTBUS_1986___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1986__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1986__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1987 (0x00AAC1F0) +#define WMAC0_HWSCH_R0_TESTBUS_1987___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1987__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1987__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1988 (0x00AAC1F4) +#define WMAC0_HWSCH_R0_TESTBUS_1988___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1988__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1988__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1989 (0x00AAC1F8) +#define WMAC0_HWSCH_R0_TESTBUS_1989___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1989__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1989__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1990 (0x00AAC1FC) +#define WMAC0_HWSCH_R0_TESTBUS_1990___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1990__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1990__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1991 (0x00AAC200) +#define WMAC0_HWSCH_R0_TESTBUS_1991___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1991__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1991__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1992 (0x00AAC204) +#define WMAC0_HWSCH_R0_TESTBUS_1992___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1992__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1992__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1993 (0x00AAC208) +#define WMAC0_HWSCH_R0_TESTBUS_1993___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1993__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1993__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1994 (0x00AAC20C) +#define WMAC0_HWSCH_R0_TESTBUS_1994___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1994__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1994__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1995 (0x00AAC210) +#define WMAC0_HWSCH_R0_TESTBUS_1995___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1995__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1995__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1996 (0x00AAC214) +#define WMAC0_HWSCH_R0_TESTBUS_1996___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1996__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1996__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1997 (0x00AAC218) +#define WMAC0_HWSCH_R0_TESTBUS_1997___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1997__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1997__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1998 (0x00AAC21C) +#define WMAC0_HWSCH_R0_TESTBUS_1998___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1998__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1998__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_1999 (0x00AAC220) +#define WMAC0_HWSCH_R0_TESTBUS_1999___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_1999__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_1999__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2000 (0x00AAC224) +#define WMAC0_HWSCH_R0_TESTBUS_2000___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2000__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2000__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2001 (0x00AAC228) +#define WMAC0_HWSCH_R0_TESTBUS_2001___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2001__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2001__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2002 (0x00AAC22C) +#define WMAC0_HWSCH_R0_TESTBUS_2002___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2002__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2002__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2003 (0x00AAC230) +#define WMAC0_HWSCH_R0_TESTBUS_2003___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2003__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2003__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2004 (0x00AAC234) +#define WMAC0_HWSCH_R0_TESTBUS_2004___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2004__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2004__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2005 (0x00AAC238) +#define WMAC0_HWSCH_R0_TESTBUS_2005___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2005__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2005__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2006 (0x00AAC23C) +#define WMAC0_HWSCH_R0_TESTBUS_2006___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2006__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2006__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2007 (0x00AAC240) +#define WMAC0_HWSCH_R0_TESTBUS_2007___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2007__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2007__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2008 (0x00AAC244) +#define WMAC0_HWSCH_R0_TESTBUS_2008___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2008__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2008__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2009 (0x00AAC248) +#define WMAC0_HWSCH_R0_TESTBUS_2009___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2009__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2009__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2010 (0x00AAC24C) +#define WMAC0_HWSCH_R0_TESTBUS_2010___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2010__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2010__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2011 (0x00AAC250) +#define WMAC0_HWSCH_R0_TESTBUS_2011___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2011__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2011__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2012 (0x00AAC254) +#define WMAC0_HWSCH_R0_TESTBUS_2012___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2012__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2012__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2013 (0x00AAC258) +#define WMAC0_HWSCH_R0_TESTBUS_2013___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2013__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2013__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2014 (0x00AAC25C) +#define WMAC0_HWSCH_R0_TESTBUS_2014___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2014__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2014__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2015 (0x00AAC260) +#define WMAC0_HWSCH_R0_TESTBUS_2015___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2015__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2015__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2016 (0x00AAC264) +#define WMAC0_HWSCH_R0_TESTBUS_2016___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2016__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2016__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2017 (0x00AAC268) +#define WMAC0_HWSCH_R0_TESTBUS_2017___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2017__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2017__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2018 (0x00AAC26C) +#define WMAC0_HWSCH_R0_TESTBUS_2018___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2018__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2018__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2019 (0x00AAC270) +#define WMAC0_HWSCH_R0_TESTBUS_2019___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2019__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2019__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2020 (0x00AAC274) +#define WMAC0_HWSCH_R0_TESTBUS_2020___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2020__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2020__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2021 (0x00AAC278) +#define WMAC0_HWSCH_R0_TESTBUS_2021___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2021__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2021__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2022 (0x00AAC27C) +#define WMAC0_HWSCH_R0_TESTBUS_2022___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2022__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2022__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2023 (0x00AAC280) +#define WMAC0_HWSCH_R0_TESTBUS_2023___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2023__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2023__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2024 (0x00AAC284) +#define WMAC0_HWSCH_R0_TESTBUS_2024___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2024__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2024__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2025 (0x00AAC288) +#define WMAC0_HWSCH_R0_TESTBUS_2025___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2025__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2025__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2026 (0x00AAC28C) +#define WMAC0_HWSCH_R0_TESTBUS_2026___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2026__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2026__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2027 (0x00AAC290) +#define WMAC0_HWSCH_R0_TESTBUS_2027___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2027__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2027__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2028 (0x00AAC294) +#define WMAC0_HWSCH_R0_TESTBUS_2028___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2028__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2028__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2029 (0x00AAC298) +#define WMAC0_HWSCH_R0_TESTBUS_2029___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2029__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2029__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2030 (0x00AAC29C) +#define WMAC0_HWSCH_R0_TESTBUS_2030___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2030__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2030__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2031 (0x00AAC2A0) +#define WMAC0_HWSCH_R0_TESTBUS_2031___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2031__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2031__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2032 (0x00AAC2A4) +#define WMAC0_HWSCH_R0_TESTBUS_2032___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2032__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2032__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2033 (0x00AAC2A8) +#define WMAC0_HWSCH_R0_TESTBUS_2033___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2033__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2033__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2034 (0x00AAC2AC) +#define WMAC0_HWSCH_R0_TESTBUS_2034___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2034__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2034__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2035 (0x00AAC2B0) +#define WMAC0_HWSCH_R0_TESTBUS_2035___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2035__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2035__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2036 (0x00AAC2B4) +#define WMAC0_HWSCH_R0_TESTBUS_2036___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2036__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2036__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2037 (0x00AAC2B8) +#define WMAC0_HWSCH_R0_TESTBUS_2037___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2037__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2037__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2038 (0x00AAC2BC) +#define WMAC0_HWSCH_R0_TESTBUS_2038___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2038__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2038__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2039 (0x00AAC2C0) +#define WMAC0_HWSCH_R0_TESTBUS_2039___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2039__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2039__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2040 (0x00AAC2C4) +#define WMAC0_HWSCH_R0_TESTBUS_2040___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2040__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2040__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2041 (0x00AAC2C8) +#define WMAC0_HWSCH_R0_TESTBUS_2041___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2041__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2041__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2042 (0x00AAC2CC) +#define WMAC0_HWSCH_R0_TESTBUS_2042___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2042__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2042__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2043 (0x00AAC2D0) +#define WMAC0_HWSCH_R0_TESTBUS_2043___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2043__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2043__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2044 (0x00AAC2D4) +#define WMAC0_HWSCH_R0_TESTBUS_2044___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2044__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2044__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2045 (0x00AAC2D8) +#define WMAC0_HWSCH_R0_TESTBUS_2045___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2045__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2045__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2046 (0x00AAC2DC) +#define WMAC0_HWSCH_R0_TESTBUS_2046___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2046__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2046__DATA___S 0 +#define WMAC0_HWSCH_R0_TESTBUS_2047 (0x00AAC2E0) +#define WMAC0_HWSCH_R0_TESTBUS_2047___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TESTBUS_2047__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TESTBUS_2047__DATA___S 0 + +#define WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL (0x00AAC2E4) +#define WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL___POR 0x0003FFFF +#define WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__ENABLE_ADDITIONAL_TQM_TLV_UPLOAD___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__DISABLE_DESC_TXOP_VALUE_CHK___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__ENABLE_MINFO_FC_RETRY_UPDATE___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__HALT_ALL_SCH_CMD_RINGS___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__HALT_FES_STAT_RING___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__BLOCK_TLV_TX_IN_CRYPTO_RX___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__SIFS_RESP_PRE_QUEUE_MODE___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__DISABLE_TX_PREAMBLE_CHECK___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__DISABLE_PM_FILTERING_CHECK___POR 0x3FFFF +#define WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__ENABLE_ADDITIONAL_TQM_TLV_UPLOAD___M 0x80000000 +#define WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__ENABLE_ADDITIONAL_TQM_TLV_UPLOAD___S 31 +#define WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__DISABLE_DESC_TXOP_VALUE_CHK___M 0x40000000 +#define WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__DISABLE_DESC_TXOP_VALUE_CHK___S 30 +#define WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__ENABLE_MINFO_FC_RETRY_UPDATE___M 0x20000000 +#define WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__ENABLE_MINFO_FC_RETRY_UPDATE___S 29 +#define WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__HALT_ALL_SCH_CMD_RINGS___M 0x10000000 +#define WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__HALT_ALL_SCH_CMD_RINGS___S 28 +#define WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__HALT_FES_STAT_RING___M 0x08000000 +#define WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__HALT_FES_STAT_RING___S 27 +#define WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__BLOCK_TLV_TX_IN_CRYPTO_RX___M 0x04000000 +#define WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__BLOCK_TLV_TX_IN_CRYPTO_RX___S 26 +#define WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__SIFS_RESP_PRE_QUEUE_MODE___M 0x02000000 +#define WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__SIFS_RESP_PRE_QUEUE_MODE___S 25 +#define WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__DISABLE_TX_PREAMBLE_CHECK___M 0x01000000 +#define WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__DISABLE_TX_PREAMBLE_CHECK___S 24 +#define WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__DISABLE_PM_FILTERING_CHECK___M 0x0003FFFF +#define WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL__DISABLE_PM_FILTERING_CHECK___S 0 +#define WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL___M 0xFF03FFFF +#define WMAC0_HWSCH_R0_CMD_MGR_GLB_CTRL___S 0 + +#define WMAC0_HWSCH_R0_AXI_ERR_STATUS (0x00AAC2E8) +#define WMAC0_HWSCH_R0_AXI_ERR_STATUS___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_AXI_ERR_STATUS___POR 0x00000000 +#define WMAC0_HWSCH_R0_AXI_ERR_STATUS__FES_END_TIMEOUT___POR 0x0 +#define WMAC0_HWSCH_R0_AXI_ERR_STATUS__CONVERSION_ERR_1___POR 0x0 +#define WMAC0_HWSCH_R0_AXI_ERR_STATUS__CONVERSION_ERR_0___POR 0x0 +#define WMAC0_HWSCH_R0_AXI_ERR_STATUS__AXI_WR_TIMEOUT_3___POR 0x0 +#define WMAC0_HWSCH_R0_AXI_ERR_STATUS__AXI_WR_TIMEOUT_2___POR 0x0 +#define WMAC0_HWSCH_R0_AXI_ERR_STATUS__AXI_WR_TIMEOUT_1___POR 0x0 +#define WMAC0_HWSCH_R0_AXI_ERR_STATUS__AXI_WR_TIMEOUT_0___POR 0x0 +#define WMAC0_HWSCH_R0_AXI_ERR_STATUS__AXI_RD_TIMEOUT___POR 0x0 +#define WMAC0_HWSCH_R0_AXI_ERR_STATUS__FES_END_TIMEOUT___M 0x00000080 +#define WMAC0_HWSCH_R0_AXI_ERR_STATUS__FES_END_TIMEOUT___S 7 +#define WMAC0_HWSCH_R0_AXI_ERR_STATUS__CONVERSION_ERR_1___M 0x00000040 +#define WMAC0_HWSCH_R0_AXI_ERR_STATUS__CONVERSION_ERR_1___S 6 +#define WMAC0_HWSCH_R0_AXI_ERR_STATUS__CONVERSION_ERR_0___M 0x00000020 +#define WMAC0_HWSCH_R0_AXI_ERR_STATUS__CONVERSION_ERR_0___S 5 +#define WMAC0_HWSCH_R0_AXI_ERR_STATUS__AXI_WR_TIMEOUT_3___M 0x00000010 +#define WMAC0_HWSCH_R0_AXI_ERR_STATUS__AXI_WR_TIMEOUT_3___S 4 +#define WMAC0_HWSCH_R0_AXI_ERR_STATUS__AXI_WR_TIMEOUT_2___M 0x00000008 +#define WMAC0_HWSCH_R0_AXI_ERR_STATUS__AXI_WR_TIMEOUT_2___S 3 +#define WMAC0_HWSCH_R0_AXI_ERR_STATUS__AXI_WR_TIMEOUT_1___M 0x00000004 +#define WMAC0_HWSCH_R0_AXI_ERR_STATUS__AXI_WR_TIMEOUT_1___S 2 +#define WMAC0_HWSCH_R0_AXI_ERR_STATUS__AXI_WR_TIMEOUT_0___M 0x00000002 +#define WMAC0_HWSCH_R0_AXI_ERR_STATUS__AXI_WR_TIMEOUT_0___S 1 +#define WMAC0_HWSCH_R0_AXI_ERR_STATUS__AXI_RD_TIMEOUT___M 0x00000001 +#define WMAC0_HWSCH_R0_AXI_ERR_STATUS__AXI_RD_TIMEOUT___S 0 +#define WMAC0_HWSCH_R0_AXI_ERR_STATUS___M 0x000000FF +#define WMAC0_HWSCH_R0_AXI_ERR_STATUS___S 0 + +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_STATUS (0x00AAC2EC) +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_STATUS___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_STATUS___POR 0x00000000 +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_STATUS__COMBO___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_STATUS__TX_FRAME___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_STATUS__RX_FRAME___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_STATUS__PRE_RX_FRAME___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_STATUS__COMBO___M 0x00000008 +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_STATUS__COMBO___S 3 +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_STATUS__TX_FRAME___M 0x00000004 +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_STATUS__TX_FRAME___S 2 +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_STATUS__RX_FRAME___M 0x00000002 +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_STATUS__RX_FRAME___S 1 +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_STATUS__PRE_RX_FRAME___M 0x00000001 +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_STATUS__PRE_RX_FRAME___S 0 +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_STATUS___M 0x0000000F +#define WMAC0_HWSCH_R0_CCA_WATCHDOG_STATUS___S 0 + +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0 (0x00AAC2F0) +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0___POR 0x00000000 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING17___POR 0x0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING16___POR 0x0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING15___POR 0x0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING14___POR 0x0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING13___POR 0x0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING12___POR 0x0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING11___POR 0x0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING10___POR 0x0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING9___POR 0x0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING8___POR 0x0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING7___POR 0x0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING6___POR 0x0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING5___POR 0x0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING4___POR 0x0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING3___POR 0x0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING2___POR 0x0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING1___POR 0x0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING0___POR 0x0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING17___M 0x00020000 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING17___S 17 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING16___M 0x00010000 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING16___S 16 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING15___M 0x00008000 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING15___S 15 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING14___M 0x00004000 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING14___S 14 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING13___M 0x00002000 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING13___S 13 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING12___M 0x00001000 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING12___S 12 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING11___M 0x00000800 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING11___S 11 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING10___M 0x00000400 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING10___S 10 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING9___M 0x00000200 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING9___S 9 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING8___M 0x00000100 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING8___S 8 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING7___M 0x00000080 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING7___S 7 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING6___M 0x00000040 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING6___S 6 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING5___M 0x00000020 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING5___S 5 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING4___M 0x00000010 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING4___S 4 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING3___M 0x00000008 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING3___S 3 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING2___M 0x00000004 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING2___S 2 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING1___M 0x00000002 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING1___S 1 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING0___M 0x00000001 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0__CMD_RING0___S 0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0___M 0x0003FFFF +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_0___S 0 + +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1 (0x00AAC2F4) +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1___POR 0x00000000 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__CMD_STAT_BUF_INGRESS___POR 0x0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__CMD_STAT_BUF_EGRESS___POR 0x0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__FES_STAT_BUF_INGRESS___POR 0x0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__FES_STAT_BUF_EGRESS___POR 0x0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__SRNG_SCH_CTRL___POR 0x0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__SFM_APB_CTRL___POR 0x0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__SFM_WRITE_CTRL___POR 0x0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__SFM_READ_CTRL___POR 0x0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__FLUSH_CTRL___POR 0x0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__STATUS_CTRL_FLUSH_SM___POR 0x0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__STATUS_CTRL_SCH_SM___POR 0x0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__STATUS_CTRL_TQM_SM___POR 0x0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__STATUS_CTRL_FES_SM___POR 0x0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__FES_SETUP___POR 0x0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__MTU_WRAP___POR 0x0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__COEX_CTRL___POR 0x0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__CMD_STAT_BUF_INGRESS___M 0x00008000 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__CMD_STAT_BUF_INGRESS___S 15 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__CMD_STAT_BUF_EGRESS___M 0x00004000 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__CMD_STAT_BUF_EGRESS___S 14 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__FES_STAT_BUF_INGRESS___M 0x00002000 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__FES_STAT_BUF_INGRESS___S 13 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__FES_STAT_BUF_EGRESS___M 0x00001000 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__FES_STAT_BUF_EGRESS___S 12 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__SRNG_SCH_CTRL___M 0x00000800 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__SRNG_SCH_CTRL___S 11 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__SFM_APB_CTRL___M 0x00000400 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__SFM_APB_CTRL___S 10 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__SFM_WRITE_CTRL___M 0x00000200 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__SFM_WRITE_CTRL___S 9 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__SFM_READ_CTRL___M 0x00000100 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__SFM_READ_CTRL___S 8 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__FLUSH_CTRL___M 0x00000080 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__FLUSH_CTRL___S 7 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__STATUS_CTRL_FLUSH_SM___M 0x00000040 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__STATUS_CTRL_FLUSH_SM___S 6 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__STATUS_CTRL_SCH_SM___M 0x00000020 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__STATUS_CTRL_SCH_SM___S 5 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__STATUS_CTRL_TQM_SM___M 0x00000010 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__STATUS_CTRL_TQM_SM___S 4 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__STATUS_CTRL_FES_SM___M 0x00000008 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__STATUS_CTRL_FES_SM___S 3 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__FES_SETUP___M 0x00000004 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__FES_SETUP___S 2 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__MTU_WRAP___M 0x00000002 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__MTU_WRAP___S 1 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__COEX_CTRL___M 0x00000001 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1__COEX_CTRL___S 0 +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1___M 0x0000FFFF +#define WMAC0_HWSCH_R0_WATCHDOG_STATUS_IX_1___S 0 + +#define WMAC0_HWSCH_R0_CLK_GATE_CONTROL (0x00AAC2F8) +#define WMAC0_HWSCH_R0_CLK_GATE_CONTROL___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CLK_GATE_CONTROL___POR 0x00000000 +#define WMAC0_HWSCH_R0_CLK_GATE_CONTROL__CLK_GATE_OVERRIDE___POR 0x00000000 +#define WMAC0_HWSCH_R0_CLK_GATE_CONTROL__CLK_GATE_OVERRIDE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CLK_GATE_CONTROL__CLK_GATE_OVERRIDE___S 0 +#define WMAC0_HWSCH_R0_CLK_GATE_CONTROL___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CLK_GATE_CONTROL___S 0 + +#define WMAC0_HWSCH_R0_CLK_GATE_CONTROL2 (0x00AAC2FC) +#define WMAC0_HWSCH_R0_CLK_GATE_CONTROL2___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CLK_GATE_CONTROL2___POR 0x00000000 +#define WMAC0_HWSCH_R0_CLK_GATE_CONTROL2__CLK_GATE_OVERRIDE___POR 0x00000000 +#define WMAC0_HWSCH_R0_CLK_GATE_CONTROL2__CLK_GATE_OVERRIDE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CLK_GATE_CONTROL2__CLK_GATE_OVERRIDE___S 0 +#define WMAC0_HWSCH_R0_CLK_GATE_CONTROL2___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CLK_GATE_CONTROL2___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_0 (0x00AAC300) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_0___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_0__CMD_RING_BASE_DATA___POR 0x00 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_0__CMD_RING_BASE_DATA___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_0__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_0___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_0___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_1 (0x00AAC304) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_1___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_1__CMD_RING_BASE_DATA___POR 0x00 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_1__CMD_RING_BASE_DATA___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_1__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_1___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_1___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_2 (0x00AAC308) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_2___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_2___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_2__CMD_RING_BASE_DATA___POR 0x00 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_2__CMD_RING_BASE_DATA___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_2__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_2___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_2___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_3 (0x00AAC30C) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_3___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_3___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_3__CMD_RING_BASE_DATA___POR 0x00 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_3__CMD_RING_BASE_DATA___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_3__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_3___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_3___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_4 (0x00AAC310) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_4___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_4___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_4__CMD_RING_BASE_DATA___POR 0x00 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_4__CMD_RING_BASE_DATA___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_4__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_4___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_4___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_5 (0x00AAC314) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_5___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_5___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_5__CMD_RING_BASE_DATA___POR 0x00 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_5__CMD_RING_BASE_DATA___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_5__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_5___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_5___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_6 (0x00AAC318) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_6___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_6___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_6__CMD_RING_BASE_DATA___POR 0x00 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_6__CMD_RING_BASE_DATA___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_6__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_6___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_6___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_7 (0x00AAC31C) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_7___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_7___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_7__CMD_RING_BASE_DATA___POR 0x00 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_7__CMD_RING_BASE_DATA___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_7__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_7___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_7___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_8 (0x00AAC320) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_8___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_8___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_8__CMD_RING_BASE_DATA___POR 0x00 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_8__CMD_RING_BASE_DATA___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_8__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_8___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_8___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_9 (0x00AAC324) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_9___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_9___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_9__CMD_RING_BASE_DATA___POR 0x00 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_9__CMD_RING_BASE_DATA___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_9__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_9___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_9___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_10 (0x00AAC328) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_10___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_10___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_10__CMD_RING_BASE_DATA___POR 0x00 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_10__CMD_RING_BASE_DATA___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_10__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_10___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_10___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_11 (0x00AAC32C) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_11___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_11___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_11__CMD_RING_BASE_DATA___POR 0x00 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_11__CMD_RING_BASE_DATA___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_11__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_11___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_11___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_12 (0x00AAC330) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_12___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_12___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_12__CMD_RING_BASE_DATA___POR 0x00 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_12__CMD_RING_BASE_DATA___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_12__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_12___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_12___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_13 (0x00AAC334) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_13___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_13___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_13__CMD_RING_BASE_DATA___POR 0x00 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_13__CMD_RING_BASE_DATA___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_13__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_13___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_13___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_14 (0x00AAC338) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_14___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_14___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_14__CMD_RING_BASE_DATA___POR 0x00 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_14__CMD_RING_BASE_DATA___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_14__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_14___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_14___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_15 (0x00AAC33C) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_15___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_15___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_15__CMD_RING_BASE_DATA___POR 0x00 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_15__CMD_RING_BASE_DATA___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_15__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_15___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_15___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_16 (0x00AAC340) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_16___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_16___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_16__CMD_RING_BASE_DATA___POR 0x00 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_16__CMD_RING_BASE_DATA___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_16__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_16___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_16___S 0 + +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_17 (0x00AAC344) +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_17___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_17___POR 0x00000000 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_17__CMD_RING_BASE_DATA___POR 0x00 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_17__CMD_RING_BASE_DATA___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_17__CMD_RING_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_17___M 0x000000FF +#define WMAC0_HWSCH_R0_SCH_CMD_RING_BASE_MSB_IX_17___S 0 + +#define WMAC0_HWSCH_R0_FES_STATUS_RING_BASE_MSB (0x00AAC350) +#define WMAC0_HWSCH_R0_FES_STATUS_RING_BASE_MSB___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_FES_STATUS_RING_BASE_MSB___POR 0x00000000 +#define WMAC0_HWSCH_R0_FES_STATUS_RING_BASE_MSB__FES_STATUS_BASE_DATA___POR 0x00 +#define WMAC0_HWSCH_R0_FES_STATUS_RING_BASE_MSB__FES_STATUS_BASE_DATA___M 0x000000FF +#define WMAC0_HWSCH_R0_FES_STATUS_RING_BASE_MSB__FES_STATUS_BASE_DATA___S 0 +#define WMAC0_HWSCH_R0_FES_STATUS_RING_BASE_MSB___M 0x000000FF +#define WMAC0_HWSCH_R0_FES_STATUS_RING_BASE_MSB___S 0 + +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_n(n) (0x00AAC354+0x4*(n)) +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_n_nMIN 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_n_nMAX 31 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_n_ELEM 32 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_n___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_n___POR 0x00000000 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_n__DATA___POR 0x00000000 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_n__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_n__DATA___S 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_n___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_n___S 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_0 (0x00AAC354) +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_0__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_0__DATA___S 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_1 (0x00AAC358) +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_1__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_1__DATA___S 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_2 (0x00AAC35C) +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_2___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_2__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_2__DATA___S 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_3 (0x00AAC360) +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_3___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_3__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_3__DATA___S 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_4 (0x00AAC364) +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_4___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_4__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_4__DATA___S 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_5 (0x00AAC368) +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_5___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_5__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_5__DATA___S 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_6 (0x00AAC36C) +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_6___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_6__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_6__DATA___S 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_7 (0x00AAC370) +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_7___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_7__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_7__DATA___S 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_8 (0x00AAC374) +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_8___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_8__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_8__DATA___S 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_9 (0x00AAC378) +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_9___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_9__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_9__DATA___S 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_10 (0x00AAC37C) +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_10___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_10__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_10__DATA___S 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_11 (0x00AAC380) +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_11___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_11__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_11__DATA___S 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_12 (0x00AAC384) +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_12___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_12__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_12__DATA___S 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_13 (0x00AAC388) +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_13___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_13__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_13__DATA___S 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_14 (0x00AAC38C) +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_14___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_14__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_14__DATA___S 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_15 (0x00AAC390) +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_15___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_15__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_15__DATA___S 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_16 (0x00AAC394) +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_16___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_16__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_16__DATA___S 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_17 (0x00AAC398) +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_17___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_17__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_17__DATA___S 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_18 (0x00AAC39C) +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_18___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_18__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_18__DATA___S 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_19 (0x00AAC3A0) +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_19___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_19__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_19__DATA___S 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_20 (0x00AAC3A4) +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_20___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_20__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_20__DATA___S 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_21 (0x00AAC3A8) +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_21___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_21__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_21__DATA___S 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_22 (0x00AAC3AC) +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_22___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_22__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_22__DATA___S 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_23 (0x00AAC3B0) +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_23___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_23__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_23__DATA___S 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_24 (0x00AAC3B4) +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_24___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_24__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_24__DATA___S 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_25 (0x00AAC3B8) +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_25___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_25__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_25__DATA___S 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_26 (0x00AAC3BC) +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_26___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_26__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_26__DATA___S 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_27 (0x00AAC3C0) +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_27___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_27__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_27__DATA___S 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_28 (0x00AAC3C4) +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_28___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_28__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_28__DATA___S 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_29 (0x00AAC3C8) +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_29___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_29__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_29__DATA___S 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_30 (0x00AAC3CC) +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_30___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_30__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_30__DATA___S 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_31 (0x00AAC3D0) +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_31___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_31__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_31__DATA___S 0 + +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_MODE (0x00AAC3D4) +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_MODE___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_MODE___POR 0x00100000 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_MODE__THRESH___POR 0x00100 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_MODE__OVERFLOW_INDEX___POR 0x0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_MODE__ENABLE___POR 0x00 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_MODE__THRESH___M 0xFFFFF000 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_MODE__THRESH___S 12 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_MODE__OVERFLOW_INDEX___M 0x00000700 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_MODE__OVERFLOW_INDEX___S 8 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_MODE__ENABLE___M 0x000000FF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_MODE__ENABLE___S 0 +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_MODE___M 0xFFFFF7FF +#define WMAC0_HWSCH_R0_GENERIC_TIMERS_MODE___S 0 + +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_n(n) (0x00AAC3D8+0x4*(n)) +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_n_nMIN 0 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_n_nMAX 3 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_n_ELEM 4 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_n___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_n___POR 0x00000000 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_n__VALUE___POR 0x00000000 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_n__VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_n__VALUE___S 0 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_n___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_n___S 0 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_0 (0x00AAC3D8) +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_0__VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_0__VALUE___S 0 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_1 (0x00AAC3DC) +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_1__VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_1__VALUE___S 0 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_2 (0x00AAC3E0) +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_2___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_2__VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_2__VALUE___S 0 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_3 (0x00AAC3E4) +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_3___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_3__VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TSF_OFFSETS_3__VALUE___S 0 + +#define WMAC0_HWSCH_R0_TSF_UPDATE (0x00AAC3E8) +#define WMAC0_HWSCH_R0_TSF_UPDATE___RWC QCSR_REG_WO +#define WMAC0_HWSCH_R0_TSF_UPDATE___POR 0x00000000 +#define WMAC0_HWSCH_R0_TSF_UPDATE__RESET_TSF2_CTRL___POR 0x0 +#define WMAC0_HWSCH_R0_TSF_UPDATE__RESET_TSF1_CTRL___POR 0x0 +#define WMAC0_HWSCH_R0_TSF_UPDATE__UPDATE_TSF___POR 0x0 +#define WMAC0_HWSCH_R0_TSF_UPDATE__RESET_TSF2_CTRL___M 0x00000004 +#define WMAC0_HWSCH_R0_TSF_UPDATE__RESET_TSF2_CTRL___S 2 +#define WMAC0_HWSCH_R0_TSF_UPDATE__RESET_TSF1_CTRL___M 0x00000002 +#define WMAC0_HWSCH_R0_TSF_UPDATE__RESET_TSF1_CTRL___S 1 +#define WMAC0_HWSCH_R0_TSF_UPDATE__UPDATE_TSF___M 0x00000001 +#define WMAC0_HWSCH_R0_TSF_UPDATE__UPDATE_TSF___S 0 +#define WMAC0_HWSCH_R0_TSF_UPDATE___M 0x00000007 +#define WMAC0_HWSCH_R0_TSF_UPDATE___S 0 + +#define WMAC0_HWSCH_R0_WC_SOC_RFF_GENERIC_TIMERS_TSF_SEL (0x00AAC3EC) +#define WMAC0_HWSCH_R0_WC_SOC_RFF_GENERIC_TIMERS_TSF_SEL___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_WC_SOC_RFF_GENERIC_TIMERS_TSF_SEL___POR 0x00000000 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_GENERIC_TIMERS_TSF_SEL__VALUE___POR 0x00 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_GENERIC_TIMERS_TSF_SEL__VALUE___M 0x000000FF +#define WMAC0_HWSCH_R0_WC_SOC_RFF_GENERIC_TIMERS_TSF_SEL__VALUE___S 0 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_GENERIC_TIMERS_TSF_SEL___M 0x000000FF +#define WMAC0_HWSCH_R0_WC_SOC_RFF_GENERIC_TIMERS_TSF_SEL___S 0 + +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL (0x00AAC3F0) +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL___POR 0x000001A9 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__SW_DTIM_OOR_UPD_TBTT_REM_DISABLE___POR 0x1 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__SW_DTIM_EARLY_RX_DET_DISABLE___POR 0x1 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__RXPCU_TSF1_UPDATE_CONTROL___POR 0x1 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__RXPCU_TSF0_UPDATE_CONTROL___POR 0x1 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__DISABLE_WAIT_FOR_PMM_VALID___POR 0x0 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__TXPCU_INSERT_TSF_SELECT___POR 0x0 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__TBTT_PROTECT___POR 0x1 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__SW_DTIM_OOR_UPD_TBTT_REM_DISABLE___M 0x00000100 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__SW_DTIM_OOR_UPD_TBTT_REM_DISABLE___S 8 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__SW_DTIM_EARLY_RX_DET_DISABLE___M 0x00000080 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__SW_DTIM_EARLY_RX_DET_DISABLE___S 7 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__RXPCU_TSF1_UPDATE_CONTROL___M 0x00000060 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__RXPCU_TSF1_UPDATE_CONTROL___S 5 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__RXPCU_TSF0_UPDATE_CONTROL___M 0x00000018 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__RXPCU_TSF0_UPDATE_CONTROL___S 3 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__DISABLE_WAIT_FOR_PMM_VALID___M 0x00000004 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__DISABLE_WAIT_FOR_PMM_VALID___S 2 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__TXPCU_INSERT_TSF_SELECT___M 0x00000002 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__TXPCU_INSERT_TSF_SELECT___S 1 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__TBTT_PROTECT___M 0x00000001 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL__TBTT_PROTECT___S 0 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL___M 0x000001FF +#define WMAC0_HWSCH_R0_WC_SOC_RFF_TIMERS_MISC_CTRL___S 0 + +#define WMAC0_HWSCH_R0_WC_SOC_RFF_USEC_LIMIT (0x00AAC3F4) +#define WMAC0_HWSCH_R0_WC_SOC_RFF_USEC_LIMIT___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_WC_SOC_RFF_USEC_LIMIT___POR 0x0000009F +#define WMAC0_HWSCH_R0_WC_SOC_RFF_USEC_LIMIT__USEC_FRAC_DENOMINATOR___POR 0x0 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_USEC_LIMIT__USEC_FRAC_NUMERATOR___POR 0x0 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_USEC_LIMIT__USEC___POR 0x09F +#define WMAC0_HWSCH_R0_WC_SOC_RFF_USEC_LIMIT__USEC_FRAC_DENOMINATOR___M 0x0003C000 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_USEC_LIMIT__USEC_FRAC_DENOMINATOR___S 14 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_USEC_LIMIT__USEC_FRAC_NUMERATOR___M 0x00003C00 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_USEC_LIMIT__USEC_FRAC_NUMERATOR___S 10 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_USEC_LIMIT__USEC___M 0x000003FF +#define WMAC0_HWSCH_R0_WC_SOC_RFF_USEC_LIMIT__USEC___S 0 +#define WMAC0_HWSCH_R0_WC_SOC_RFF_USEC_LIMIT___M 0x0003FFFF +#define WMAC0_HWSCH_R0_WC_SOC_RFF_USEC_LIMIT___S 0 + +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_n(n) (0x00AAC3F8+0x4*(n)) +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_n_nMIN 0 +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_n_nMAX 9 +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_n_ELEM 10 +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_n___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_n___POR 0x00000000 +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_n__VALUE___POR 0x00000000 +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_n__VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_n__VALUE___S 0 +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_n___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_n___S 0 +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_0 (0x00AAC3F8) +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_0___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_0__VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_0__VALUE___S 0 +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_1 (0x00AAC3FC) +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_1___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_1__VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_1__VALUE___S 0 +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_2 (0x00AAC400) +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_2___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_2__VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_2__VALUE___S 0 +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_3 (0x00AAC404) +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_3___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_3__VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_3__VALUE___S 0 +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_4 (0x00AAC408) +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_4___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_4__VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_4__VALUE___S 0 +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_5 (0x00AAC40C) +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_5___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_5__VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_5__VALUE___S 0 +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_6 (0x00AAC410) +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_6___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_6__VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_6__VALUE___S 0 +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_7 (0x00AAC414) +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_7___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_7__VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_7__VALUE___S 0 +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_8 (0x00AAC418) +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_8___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_8__VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_8__VALUE___S 0 +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_9 (0x00AAC41C) +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_9___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_9__VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_TSF_GLOBAL_COUNTS_9__VALUE___S 0 + +#define WMAC0_HWSCH_R0_DYN_EIFS_6MBPS (0x00AAC420) +#define WMAC0_HWSCH_R0_DYN_EIFS_6MBPS___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_DYN_EIFS_6MBPS___POR 0x005C005C +#define WMAC0_HWSCH_R0_DYN_EIFS_6MBPS__EIFS_LIMIT_FOR_BA___POR 0x005C +#define WMAC0_HWSCH_R0_DYN_EIFS_6MBPS__EIFS_LIMIT_FOR_ACK___POR 0x005C +#define WMAC0_HWSCH_R0_DYN_EIFS_6MBPS__EIFS_LIMIT_FOR_BA___M 0xFFFF0000 +#define WMAC0_HWSCH_R0_DYN_EIFS_6MBPS__EIFS_LIMIT_FOR_BA___S 16 +#define WMAC0_HWSCH_R0_DYN_EIFS_6MBPS__EIFS_LIMIT_FOR_ACK___M 0x0000FFFF +#define WMAC0_HWSCH_R0_DYN_EIFS_6MBPS__EIFS_LIMIT_FOR_ACK___S 0 +#define WMAC0_HWSCH_R0_DYN_EIFS_6MBPS___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_DYN_EIFS_6MBPS___S 0 + +#define WMAC0_HWSCH_R0_DYN_EIFS_12MBPS (0x00AAC424) +#define WMAC0_HWSCH_R0_DYN_EIFS_12MBPS___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_DYN_EIFS_12MBPS___POR 0x005C005C +#define WMAC0_HWSCH_R0_DYN_EIFS_12MBPS__EIFS_LIMIT_FOR_BA___POR 0x005C +#define WMAC0_HWSCH_R0_DYN_EIFS_12MBPS__EIFS_LIMIT_FOR_ACK___POR 0x005C +#define WMAC0_HWSCH_R0_DYN_EIFS_12MBPS__EIFS_LIMIT_FOR_BA___M 0xFFFF0000 +#define WMAC0_HWSCH_R0_DYN_EIFS_12MBPS__EIFS_LIMIT_FOR_BA___S 16 +#define WMAC0_HWSCH_R0_DYN_EIFS_12MBPS__EIFS_LIMIT_FOR_ACK___M 0x0000FFFF +#define WMAC0_HWSCH_R0_DYN_EIFS_12MBPS__EIFS_LIMIT_FOR_ACK___S 0 +#define WMAC0_HWSCH_R0_DYN_EIFS_12MBPS___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_DYN_EIFS_12MBPS___S 0 + +#define WMAC0_HWSCH_R0_DYN_EIFS_24MBPS (0x00AAC428) +#define WMAC0_HWSCH_R0_DYN_EIFS_24MBPS___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_DYN_EIFS_24MBPS___POR 0x005C005C +#define WMAC0_HWSCH_R0_DYN_EIFS_24MBPS__EIFS_LIMIT_FOR_BA___POR 0x005C +#define WMAC0_HWSCH_R0_DYN_EIFS_24MBPS__EIFS_LIMIT_FOR_ACK___POR 0x005C +#define WMAC0_HWSCH_R0_DYN_EIFS_24MBPS__EIFS_LIMIT_FOR_BA___M 0xFFFF0000 +#define WMAC0_HWSCH_R0_DYN_EIFS_24MBPS__EIFS_LIMIT_FOR_BA___S 16 +#define WMAC0_HWSCH_R0_DYN_EIFS_24MBPS__EIFS_LIMIT_FOR_ACK___M 0x0000FFFF +#define WMAC0_HWSCH_R0_DYN_EIFS_24MBPS__EIFS_LIMIT_FOR_ACK___S 0 +#define WMAC0_HWSCH_R0_DYN_EIFS_24MBPS___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_DYN_EIFS_24MBPS___S 0 + +#define WMAC0_HWSCH_R0_DYN_EIFS_UNMAPPED (0x00AAC42C) +#define WMAC0_HWSCH_R0_DYN_EIFS_UNMAPPED___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_DYN_EIFS_UNMAPPED___POR 0x0000005C +#define WMAC0_HWSCH_R0_DYN_EIFS_UNMAPPED__EIFS_LIMIT___POR 0x005C +#define WMAC0_HWSCH_R0_DYN_EIFS_UNMAPPED__EIFS_LIMIT___M 0x0000FFFF +#define WMAC0_HWSCH_R0_DYN_EIFS_UNMAPPED__EIFS_LIMIT___S 0 +#define WMAC0_HWSCH_R0_DYN_EIFS_UNMAPPED___M 0x0000FFFF +#define WMAC0_HWSCH_R0_DYN_EIFS_UNMAPPED___S 0 + +#define WMAC0_HWSCH_R0_INVALID_APB_ACC (0x00AAC430) +#define WMAC0_HWSCH_R0_INVALID_APB_ACC___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_INVALID_APB_ACC___POR 0x00000000 +#define WMAC0_HWSCH_R0_INVALID_APB_ACC__ADR___POR 0x00000 +#define WMAC0_HWSCH_R0_INVALID_APB_ACC__ADR___M 0x0001FFFF +#define WMAC0_HWSCH_R0_INVALID_APB_ACC__ADR___S 0 +#define WMAC0_HWSCH_R0_INVALID_APB_ACC___M 0x0001FFFF +#define WMAC0_HWSCH_R0_INVALID_APB_ACC___S 0 + +#define WMAC0_HWSCH_R0_DBG_NON_ZERO_XMIT_FREE_TIME_CNT (0x00AAC434) +#define WMAC0_HWSCH_R0_DBG_NON_ZERO_XMIT_FREE_TIME_CNT___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_DBG_NON_ZERO_XMIT_FREE_TIME_CNT___POR 0x00000000 +#define WMAC0_HWSCH_R0_DBG_NON_ZERO_XMIT_FREE_TIME_CNT__DBG_NON_ZERO_XMIT_FREE_TIME_CNT___POR 0x00000000 +#define WMAC0_HWSCH_R0_DBG_NON_ZERO_XMIT_FREE_TIME_CNT__DBG_NON_ZERO_XMIT_FREE_TIME_CNT___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_DBG_NON_ZERO_XMIT_FREE_TIME_CNT__DBG_NON_ZERO_XMIT_FREE_TIME_CNT___S 0 +#define WMAC0_HWSCH_R0_DBG_NON_ZERO_XMIT_FREE_TIME_CNT___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_DBG_NON_ZERO_XMIT_FREE_TIME_CNT___S 0 + +#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_0 (0x00AAC438) +#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_0___POR 0x00000000 +#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_0__DATA___POR 0x00000000 +#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_0__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_0__DATA___S 0 +#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_0___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_0___S 0 + +#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_1 (0x00AAC43C) +#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_1___POR 0x00000000 +#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_1__DATA___POR 0x00000000 +#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_1__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_1__DATA___S 0 +#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_1___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_1___S 0 + +#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_2 (0x00AAC440) +#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_2___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_2___POR 0x00000000 +#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_2__DATA___POR 0x00000000 +#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_2__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_2__DATA___S 0 +#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_2___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_2___S 0 + +#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_3 (0x00AAC444) +#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_3___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_3___POR 0x00000000 +#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_3__DATA___POR 0x000 +#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_3__DATA___M 0x00000FFF +#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_3__DATA___S 0 +#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_3___M 0x00000FFF +#define WMAC0_HWSCH_R0_FLREQ_WIN_MASK_3___S 0 + +#define WMAC0_HWSCH_R0_XMIT_FREE_TIME_RX_REMAIN_TIME (0x00AAC448) +#define WMAC0_HWSCH_R0_XMIT_FREE_TIME_RX_REMAIN_TIME___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_XMIT_FREE_TIME_RX_REMAIN_TIME___POR 0x00000000 +#define WMAC0_HWSCH_R0_XMIT_FREE_TIME_RX_REMAIN_TIME__XMIT_FREE_TIME_CNT___POR 0x0000 +#define WMAC0_HWSCH_R0_XMIT_FREE_TIME_RX_REMAIN_TIME__REMAIN_RX_TIME_CNT___POR 0x0000 +#define WMAC0_HWSCH_R0_XMIT_FREE_TIME_RX_REMAIN_TIME__XMIT_FREE_TIME_CNT___M 0xFFFF0000 +#define WMAC0_HWSCH_R0_XMIT_FREE_TIME_RX_REMAIN_TIME__XMIT_FREE_TIME_CNT___S 16 +#define WMAC0_HWSCH_R0_XMIT_FREE_TIME_RX_REMAIN_TIME__REMAIN_RX_TIME_CNT___M 0x0000FFFF +#define WMAC0_HWSCH_R0_XMIT_FREE_TIME_RX_REMAIN_TIME__REMAIN_RX_TIME_CNT___S 0 +#define WMAC0_HWSCH_R0_XMIT_FREE_TIME_RX_REMAIN_TIME___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_XMIT_FREE_TIME_RX_REMAIN_TIME___S 0 + +#define WMAC0_HWSCH_R0_NAV_OVERRIDE_CTRL (0x00AAC44C) +#define WMAC0_HWSCH_R0_NAV_OVERRIDE_CTRL___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_NAV_OVERRIDE_CTRL___POR 0xFFFFFFFC +#define WMAC0_HWSCH_R0_NAV_OVERRIDE_CTRL__NAV_UPDATE_THRESHOLD___POR 0x3FFFFFFF +#define WMAC0_HWSCH_R0_NAV_OVERRIDE_CTRL__NAV_UPDATE_CTRL___POR 0x0 +#define WMAC0_HWSCH_R0_NAV_OVERRIDE_CTRL__NAV_UPDATE_THRESHOLD___M 0xFFFFFFFC +#define WMAC0_HWSCH_R0_NAV_OVERRIDE_CTRL__NAV_UPDATE_THRESHOLD___S 2 +#define WMAC0_HWSCH_R0_NAV_OVERRIDE_CTRL__NAV_UPDATE_CTRL___M 0x00000003 +#define WMAC0_HWSCH_R0_NAV_OVERRIDE_CTRL__NAV_UPDATE_CTRL___S 0 +#define WMAC0_HWSCH_R0_NAV_OVERRIDE_CTRL___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_NAV_OVERRIDE_CTRL___S 0 + +#define WMAC0_HWSCH_R0_INBSS_NAV_OVERRIDE_CTRL (0x00AAC450) +#define WMAC0_HWSCH_R0_INBSS_NAV_OVERRIDE_CTRL___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_INBSS_NAV_OVERRIDE_CTRL___POR 0xFFFFFFFC +#define WMAC0_HWSCH_R0_INBSS_NAV_OVERRIDE_CTRL__INBSS_NAV_UPDATE_THRESHOLD___POR 0x3FFFFFFF +#define WMAC0_HWSCH_R0_INBSS_NAV_OVERRIDE_CTRL__INBSS_NAV_UPDATE_CTRL___POR 0x0 +#define WMAC0_HWSCH_R0_INBSS_NAV_OVERRIDE_CTRL__INBSS_NAV_UPDATE_THRESHOLD___M 0xFFFFFFFC +#define WMAC0_HWSCH_R0_INBSS_NAV_OVERRIDE_CTRL__INBSS_NAV_UPDATE_THRESHOLD___S 2 +#define WMAC0_HWSCH_R0_INBSS_NAV_OVERRIDE_CTRL__INBSS_NAV_UPDATE_CTRL___M 0x00000003 +#define WMAC0_HWSCH_R0_INBSS_NAV_OVERRIDE_CTRL__INBSS_NAV_UPDATE_CTRL___S 0 +#define WMAC0_HWSCH_R0_INBSS_NAV_OVERRIDE_CTRL___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_INBSS_NAV_OVERRIDE_CTRL___S 0 + +#define WMAC0_HWSCH_R0_GLOBAL_POST_RESPONSE_TIMEOUT (0x00AAC454) +#define WMAC0_HWSCH_R0_GLOBAL_POST_RESPONSE_TIMEOUT___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GLOBAL_POST_RESPONSE_TIMEOUT___POR 0x00000000 +#define WMAC0_HWSCH_R0_GLOBAL_POST_RESPONSE_TIMEOUT__VALUE___POR 0x0000 +#define WMAC0_HWSCH_R0_GLOBAL_POST_RESPONSE_TIMEOUT__VALUE___M 0x0000FFFF +#define WMAC0_HWSCH_R0_GLOBAL_POST_RESPONSE_TIMEOUT__VALUE___S 0 +#define WMAC0_HWSCH_R0_GLOBAL_POST_RESPONSE_TIMEOUT___M 0x0000FFFF +#define WMAC0_HWSCH_R0_GLOBAL_POST_RESPONSE_TIMEOUT___S 0 + +#define WMAC0_HWSCH_R0_PPDU_DURATION_FRAC (0x00AAC458) +#define WMAC0_HWSCH_R0_PPDU_DURATION_FRAC___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_PPDU_DURATION_FRAC___POR 0x00000000 +#define WMAC0_HWSCH_R0_PPDU_DURATION_FRAC__VALUE___POR 0x0 +#define WMAC0_HWSCH_R0_PPDU_DURATION_FRAC__VALUE___M 0x00000003 +#define WMAC0_HWSCH_R0_PPDU_DURATION_FRAC__VALUE___S 0 +#define WMAC0_HWSCH_R0_PPDU_DURATION_FRAC___M 0x00000003 +#define WMAC0_HWSCH_R0_PPDU_DURATION_FRAC___S 0 + +#define WMAC0_HWSCH_R0_SCH_STATUS_RING_THRESHOLDS (0x00AAC45C) +#define WMAC0_HWSCH_R0_SCH_STATUS_RING_THRESHOLDS___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_STATUS_RING_THRESHOLDS___POR 0x00010040 +#define WMAC0_HWSCH_R0_SCH_STATUS_RING_THRESHOLDS__PANIC_WATERMARK___POR 0x0001 +#define WMAC0_HWSCH_R0_SCH_STATUS_RING_THRESHOLDS__LOW_WATERMARK___POR 0x0040 +#define WMAC0_HWSCH_R0_SCH_STATUS_RING_THRESHOLDS__PANIC_WATERMARK___M 0xFFFF0000 +#define WMAC0_HWSCH_R0_SCH_STATUS_RING_THRESHOLDS__PANIC_WATERMARK___S 16 +#define WMAC0_HWSCH_R0_SCH_STATUS_RING_THRESHOLDS__LOW_WATERMARK___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SCH_STATUS_RING_THRESHOLDS__LOW_WATERMARK___S 0 +#define WMAC0_HWSCH_R0_SCH_STATUS_RING_THRESHOLDS___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SCH_STATUS_RING_THRESHOLDS___S 0 + +#define WMAC0_HWSCH_R0_FES_STATUS_END_TIMEOUT (0x00AAC460) +#define WMAC0_HWSCH_R0_FES_STATUS_END_TIMEOUT___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_FES_STATUS_END_TIMEOUT___POR 0x00001F40 +#define WMAC0_HWSCH_R0_FES_STATUS_END_TIMEOUT__VALUE___POR 0x1F40 +#define WMAC0_HWSCH_R0_FES_STATUS_END_TIMEOUT__VALUE___M 0x0000FFFF +#define WMAC0_HWSCH_R0_FES_STATUS_END_TIMEOUT__VALUE___S 0 +#define WMAC0_HWSCH_R0_FES_STATUS_END_TIMEOUT___M 0x0000FFFF +#define WMAC0_HWSCH_R0_FES_STATUS_END_TIMEOUT___S 0 + +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_LSB (0x00AAC464) +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_LSB___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_LSB___POR 0x00000000 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_LSB__RING_BASE_ADDR_LSB___POR 0x00000000 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_LSB__RING_BASE_ADDR_LSB___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_LSB__RING_BASE_ADDR_LSB___S 0 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_LSB___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_LSB___S 0 + +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_MSB (0x00AAC468) +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_MSB___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_MSB___POR 0x00000000 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_MSB__RING_SIZE___POR 0x0000 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_MSB__RING_BASE_ADDR_MSB___POR 0x00 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_MSB__RING_SIZE___M 0x00FFFF00 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_MSB__RING_SIZE___S 8 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_MSB__RING_BASE_ADDR_MSB___M 0x000000FF +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_MSB__RING_BASE_ADDR_MSB___S 0 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_MSB___M 0x00FFFFFF +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_BASE_MSB___S 0 + +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_ID (0x00AAC46C) +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_ID___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_ID___POR 0x00000000 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_ID__RING_ID___POR 0x00 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_ID__ENTRY_SIZE___POR 0x00 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_ID__RING_ID___M 0x0000FF00 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_ID__RING_ID___S 8 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_ID__ENTRY_SIZE___M 0x000000FF +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_ID__ENTRY_SIZE___S 0 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_ID___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_ID___S 0 + +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_STATUS (0x00AAC470) +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_STATUS___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_STATUS___POR 0x00000000 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_STATUS__NUM_AVAIL_WORDS___POR 0x0000 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_STATUS__NUM_VALID_WORDS___POR 0x0000 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_STATUS__NUM_AVAIL_WORDS___M 0xFFFF0000 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_STATUS__NUM_AVAIL_WORDS___S 16 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_STATUS__NUM_VALID_WORDS___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_STATUS__NUM_VALID_WORDS___S 0 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_STATUS___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_STATUS___S 0 + +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC (0x00AAC474) +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC___POR 0x00000080 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__LOOP_CNT___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SPARE_CONTROL___POR 0x00 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SRNG_SM_STATE2___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SRNG_SM_STATE1___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SRNG_IS_IDLE___POR 0x1 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SRNG_ENABLE___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__DATA_TLV_SWAP_BIT___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__HOST_FW_SWAP_BIT___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__MSI_SWAP_BIT___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SECURITY_BIT___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__LOOPCNT_DISABLE___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__RING_ID_DISABLE___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__LOOP_CNT___M 0x03C00000 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__LOOP_CNT___S 22 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SPARE_CONTROL___M 0x003FC000 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SPARE_CONTROL___S 14 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SRNG_SM_STATE2___M 0x00003000 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SRNG_SM_STATE2___S 12 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SRNG_SM_STATE1___M 0x00000F00 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SRNG_SM_STATE1___S 8 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SRNG_IS_IDLE___M 0x00000080 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SRNG_IS_IDLE___S 7 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SRNG_ENABLE___M 0x00000040 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SRNG_ENABLE___S 6 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__DATA_TLV_SWAP_BIT___M 0x00000020 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__DATA_TLV_SWAP_BIT___S 5 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__HOST_FW_SWAP_BIT___M 0x00000010 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__HOST_FW_SWAP_BIT___S 4 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__MSI_SWAP_BIT___M 0x00000008 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__MSI_SWAP_BIT___S 3 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SECURITY_BIT___M 0x00000004 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__SECURITY_BIT___S 2 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__LOOPCNT_DISABLE___M 0x00000002 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__LOOPCNT_DISABLE___S 1 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__RING_ID_DISABLE___M 0x00000001 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC__RING_ID_DISABLE___S 0 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC___M 0x03FFFFFF +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MISC___S 0 + +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_ADDR_LSB (0x00AAC478) +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_ADDR_LSB___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_ADDR_LSB___POR 0x00000000 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___POR 0x00000000 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_ADDR_LSB__HEAD_PTR_MEMADDR_LSB___S 0 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_ADDR_LSB___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_ADDR_LSB___S 0 + +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_ADDR_MSB (0x00AAC47C) +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_ADDR_MSB___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_ADDR_MSB___POR 0x00000000 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___POR 0x00 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___M 0x000000FF +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_ADDR_MSB__HEAD_PTR_MEMADDR_MSB___S 0 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_ADDR_MSB___M 0x000000FF +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_ADDR_MSB___S 0 + +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_SETUP (0x00AAC488) +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_SETUP___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_SETUP___POR 0x00000000 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___POR 0x0000 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___POR 0x0000 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___M 0xFFFF0000 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_SETUP__INTERRUPT_TIMER_THRESHOLD___S 16 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___M 0x00008000 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_SETUP__SW_INTERRUPT_MODE___S 15 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___M 0x00007FFF +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_SETUP__BATCH_COUNTER_THRESHOLD___S 0 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_SETUP___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_SETUP___S 0 + +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_STATUS (0x00AAC48C) +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_STATUS___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_STATUS___POR 0x00000000 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___POR 0x0000 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___POR 0x0000 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___M 0xFFFF0000 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_INTERRUPT_TIMER_VALUE___S 16 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___M 0x00008000 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_STATUS__CURRENT_SW_INT_WIRE_VALUE___S 15 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___M 0x00007FFF +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_STATUS__INTERNAL_BATCH_COUNTER_VALUE___S 0 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_STATUS___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_INT_STATUS___S 0 + +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_FULL_COUNTER (0x00AAC490) +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_FULL_COUNTER___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_FULL_COUNTER___POR 0x00000000 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___POR 0x000 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___M 0x000003FF +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_FULL_COUNTER__RING_FULL_COUNTER___S 0 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_FULL_COUNTER___M 0x000003FF +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_PRODUCER_FULL_COUNTER___S 0 + +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_LSB (0x00AAC4AC) +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_LSB___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_LSB___POR 0x00000000 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_LSB__ADDR___POR 0x00000000 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_LSB__ADDR___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_LSB__ADDR___S 0 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_LSB___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_LSB___S 0 + +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_MSB (0x00AAC4B0) +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_MSB___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_MSB___POR 0x00000000 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_MSB__MSI1_ENABLE___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_MSB__ADDR___POR 0x00 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_MSB__MSI1_ENABLE___M 0x00000100 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_MSB__MSI1_ENABLE___S 8 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_MSB__ADDR___M 0x000000FF +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_MSB__ADDR___S 0 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_MSB___M 0x000001FF +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_BASE_MSB___S 0 + +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_DATA (0x00AAC4B4) +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_DATA___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_DATA___POR 0x00000000 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_DATA__VALUE___POR 0x00000000 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_DATA__VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_DATA__VALUE___S 0 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_MSI1_DATA___S 0 + +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_TP_SW_OFFSET (0x00AAC4B8) +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_TP_SW_OFFSET___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_TP_SW_OFFSET___POR 0x00000000 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___POR 0x0000 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_TP_SW_OFFSET__HP_TP_OFFSET_VALUE___S 0 +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_TP_SW_OFFSET___M 0x0000FFFF +#define WMAC0_HWSCH_R0_CMD_STATUS_RING_HP_TP_SW_OFFSET___S 0 + +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n(n) (0x00AAC4BC+0x4*(n)) +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n_nMIN 0 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n_nMAX 15 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n_ELEM 16 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n___POR 0x00000000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n__LOCK___POR 0x0 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n__VALID___POR 0x0 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n__WEIGHT___POR 0x00 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n__PM_SETTING___POR 0x0 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n__PEER_ID___POR 0x0000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n__LOCK___M 0x01000000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n__LOCK___S 24 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n__VALID___M 0x00800000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n__VALID___S 23 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n__WEIGHT___M 0x003E0000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n__WEIGHT___S 17 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n__PM_SETTING___M 0x00010000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n__PM_SETTING___S 16 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n__PEER_ID___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n__PEER_ID___S 0 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n___M 0x01BFFFFF +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_n___S 0 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_0 (0x00AAC4BC) +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_0___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_0__LOCK___M 0x01000000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_0__LOCK___S 24 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_0__VALID___M 0x00800000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_0__VALID___S 23 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_0__WEIGHT___M 0x003E0000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_0__WEIGHT___S 17 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_0__PM_SETTING___M 0x00010000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_0__PM_SETTING___S 16 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_0__PEER_ID___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_0__PEER_ID___S 0 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_1 (0x00AAC4C0) +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_1___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_1__LOCK___M 0x01000000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_1__LOCK___S 24 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_1__VALID___M 0x00800000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_1__VALID___S 23 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_1__WEIGHT___M 0x003E0000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_1__WEIGHT___S 17 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_1__PM_SETTING___M 0x00010000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_1__PM_SETTING___S 16 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_1__PEER_ID___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_1__PEER_ID___S 0 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_2 (0x00AAC4C4) +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_2___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_2__LOCK___M 0x01000000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_2__LOCK___S 24 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_2__VALID___M 0x00800000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_2__VALID___S 23 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_2__WEIGHT___M 0x003E0000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_2__WEIGHT___S 17 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_2__PM_SETTING___M 0x00010000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_2__PM_SETTING___S 16 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_2__PEER_ID___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_2__PEER_ID___S 0 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_3 (0x00AAC4C8) +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_3___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_3__LOCK___M 0x01000000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_3__LOCK___S 24 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_3__VALID___M 0x00800000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_3__VALID___S 23 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_3__WEIGHT___M 0x003E0000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_3__WEIGHT___S 17 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_3__PM_SETTING___M 0x00010000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_3__PM_SETTING___S 16 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_3__PEER_ID___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_3__PEER_ID___S 0 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_4 (0x00AAC4CC) +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_4___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_4__LOCK___M 0x01000000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_4__LOCK___S 24 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_4__VALID___M 0x00800000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_4__VALID___S 23 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_4__WEIGHT___M 0x003E0000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_4__WEIGHT___S 17 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_4__PM_SETTING___M 0x00010000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_4__PM_SETTING___S 16 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_4__PEER_ID___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_4__PEER_ID___S 0 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_5 (0x00AAC4D0) +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_5___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_5__LOCK___M 0x01000000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_5__LOCK___S 24 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_5__VALID___M 0x00800000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_5__VALID___S 23 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_5__WEIGHT___M 0x003E0000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_5__WEIGHT___S 17 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_5__PM_SETTING___M 0x00010000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_5__PM_SETTING___S 16 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_5__PEER_ID___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_5__PEER_ID___S 0 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_6 (0x00AAC4D4) +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_6___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_6__LOCK___M 0x01000000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_6__LOCK___S 24 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_6__VALID___M 0x00800000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_6__VALID___S 23 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_6__WEIGHT___M 0x003E0000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_6__WEIGHT___S 17 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_6__PM_SETTING___M 0x00010000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_6__PM_SETTING___S 16 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_6__PEER_ID___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_6__PEER_ID___S 0 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_7 (0x00AAC4D8) +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_7___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_7__LOCK___M 0x01000000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_7__LOCK___S 24 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_7__VALID___M 0x00800000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_7__VALID___S 23 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_7__WEIGHT___M 0x003E0000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_7__WEIGHT___S 17 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_7__PM_SETTING___M 0x00010000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_7__PM_SETTING___S 16 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_7__PEER_ID___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_7__PEER_ID___S 0 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_8 (0x00AAC4DC) +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_8___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_8__LOCK___M 0x01000000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_8__LOCK___S 24 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_8__VALID___M 0x00800000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_8__VALID___S 23 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_8__WEIGHT___M 0x003E0000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_8__WEIGHT___S 17 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_8__PM_SETTING___M 0x00010000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_8__PM_SETTING___S 16 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_8__PEER_ID___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_8__PEER_ID___S 0 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_9 (0x00AAC4E0) +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_9___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_9__LOCK___M 0x01000000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_9__LOCK___S 24 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_9__VALID___M 0x00800000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_9__VALID___S 23 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_9__WEIGHT___M 0x003E0000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_9__WEIGHT___S 17 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_9__PM_SETTING___M 0x00010000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_9__PM_SETTING___S 16 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_9__PEER_ID___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_9__PEER_ID___S 0 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_10 (0x00AAC4E4) +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_10___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_10__LOCK___M 0x01000000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_10__LOCK___S 24 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_10__VALID___M 0x00800000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_10__VALID___S 23 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_10__WEIGHT___M 0x003E0000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_10__WEIGHT___S 17 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_10__PM_SETTING___M 0x00010000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_10__PM_SETTING___S 16 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_10__PEER_ID___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_10__PEER_ID___S 0 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_11 (0x00AAC4E8) +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_11___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_11__LOCK___M 0x01000000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_11__LOCK___S 24 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_11__VALID___M 0x00800000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_11__VALID___S 23 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_11__WEIGHT___M 0x003E0000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_11__WEIGHT___S 17 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_11__PM_SETTING___M 0x00010000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_11__PM_SETTING___S 16 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_11__PEER_ID___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_11__PEER_ID___S 0 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_12 (0x00AAC4EC) +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_12___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_12__LOCK___M 0x01000000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_12__LOCK___S 24 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_12__VALID___M 0x00800000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_12__VALID___S 23 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_12__WEIGHT___M 0x003E0000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_12__WEIGHT___S 17 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_12__PM_SETTING___M 0x00010000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_12__PM_SETTING___S 16 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_12__PEER_ID___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_12__PEER_ID___S 0 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_13 (0x00AAC4F0) +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_13___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_13__LOCK___M 0x01000000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_13__LOCK___S 24 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_13__VALID___M 0x00800000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_13__VALID___S 23 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_13__WEIGHT___M 0x003E0000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_13__WEIGHT___S 17 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_13__PM_SETTING___M 0x00010000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_13__PM_SETTING___S 16 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_13__PEER_ID___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_13__PEER_ID___S 0 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_14 (0x00AAC4F4) +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_14___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_14__LOCK___M 0x01000000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_14__LOCK___S 24 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_14__VALID___M 0x00800000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_14__VALID___S 23 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_14__WEIGHT___M 0x003E0000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_14__WEIGHT___S 17 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_14__PM_SETTING___M 0x00010000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_14__PM_SETTING___S 16 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_14__PEER_ID___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_14__PEER_ID___S 0 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_15 (0x00AAC4F8) +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_15___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_15__LOCK___M 0x01000000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_15__LOCK___S 24 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_15__VALID___M 0x00800000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_15__VALID___S 23 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_15__WEIGHT___M 0x003E0000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_15__WEIGHT___S 17 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_15__PM_SETTING___M 0x00010000 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_15__PM_SETTING___S 16 +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_15__PEER_ID___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_RD_RX_PM_INFO_15__PEER_ID___S 0 + +#define WMAC0_HWSCH_R0_SW_WR_RX_PM_INFO (0x00AAC504) +#define WMAC0_HWSCH_R0_SW_WR_RX_PM_INFO___RWC QCSR_REG_WO +#define WMAC0_HWSCH_R0_SW_WR_RX_PM_INFO___POR 0x00000000 +#define WMAC0_HWSCH_R0_SW_WR_RX_PM_INFO__LOCK___POR 0x0 +#define WMAC0_HWSCH_R0_SW_WR_RX_PM_INFO__PM_SETTING___POR 0x0 +#define WMAC0_HWSCH_R0_SW_WR_RX_PM_INFO__PEER_ID___POR 0x0000 +#define WMAC0_HWSCH_R0_SW_WR_RX_PM_INFO__LOCK___M 0x00020000 +#define WMAC0_HWSCH_R0_SW_WR_RX_PM_INFO__LOCK___S 17 +#define WMAC0_HWSCH_R0_SW_WR_RX_PM_INFO__PM_SETTING___M 0x00010000 +#define WMAC0_HWSCH_R0_SW_WR_RX_PM_INFO__PM_SETTING___S 16 +#define WMAC0_HWSCH_R0_SW_WR_RX_PM_INFO__PEER_ID___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SW_WR_RX_PM_INFO__PEER_ID___S 0 +#define WMAC0_HWSCH_R0_SW_WR_RX_PM_INFO___M 0x0003FFFF +#define WMAC0_HWSCH_R0_SW_WR_RX_PM_INFO___S 0 + +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_n(n) (0x00AAC508+0x4*(n)) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_n_nMIN 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_n_nMAX 35 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_n_ELEM 36 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_n___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_n___POR 0x00000000 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_n__LUT_VALUE___POR 0x00000000 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_n__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_n__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_n___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_n___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_0 (0x00AAC508) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_0__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_0__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_1 (0x00AAC50C) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_1__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_1__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_2 (0x00AAC510) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_2___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_2__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_2__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_3 (0x00AAC514) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_3___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_3__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_3__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_4 (0x00AAC518) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_4___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_4__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_4__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_5 (0x00AAC51C) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_5___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_5__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_5__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_6 (0x00AAC520) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_6___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_6__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_6__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_7 (0x00AAC524) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_7___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_7__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_7__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_8 (0x00AAC528) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_8___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_8__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_8__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_9 (0x00AAC52C) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_9___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_9__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_9__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_10 (0x00AAC530) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_10___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_10__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_10__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_11 (0x00AAC534) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_11___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_11__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_11__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_12 (0x00AAC538) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_12___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_12__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_12__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_13 (0x00AAC53C) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_13___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_13__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_13__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_14 (0x00AAC540) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_14___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_14__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_14__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_15 (0x00AAC544) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_15___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_15__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_15__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_16 (0x00AAC548) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_16___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_16__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_16__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_17 (0x00AAC54C) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_17___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_17__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_17__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_18 (0x00AAC550) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_18___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_18__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_18__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_19 (0x00AAC554) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_19___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_19__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_19__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_20 (0x00AAC558) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_20___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_20__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_20__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_21 (0x00AAC55C) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_21___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_21__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_21__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_22 (0x00AAC560) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_22___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_22__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_22__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_23 (0x00AAC564) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_23___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_23__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_23__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_24 (0x00AAC568) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_24___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_24__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_24__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_25 (0x00AAC56C) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_25___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_25__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_25__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_26 (0x00AAC570) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_26___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_26__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_26__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_27 (0x00AAC574) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_27___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_27__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_27__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_28 (0x00AAC578) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_28___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_28__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_28__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_29 (0x00AAC57C) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_29___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_29__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_29__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_30 (0x00AAC580) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_30___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_30__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_30__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_31 (0x00AAC584) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_31___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_31__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_31__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_32 (0x00AAC588) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_32___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_32__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_32__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_33 (0x00AAC58C) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_33___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_33__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_33__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_34 (0x00AAC590) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_34___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_34__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_34__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_35 (0x00AAC594) +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_35___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_35__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_BKOFF_35__LUT_VALUE___S 0 + +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_n(n) (0x00AAC5A8+0x4*(n)) +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_n_nMIN 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_n_nMAX 7 +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_n_ELEM 8 +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_n___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_n___POR 0x00111100 +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_n__LUT_VALUE___POR 0x00111100 +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_n__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_n__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_n___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_n___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_0 (0x00AAC5A8) +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_0__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_0__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_1 (0x00AAC5AC) +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_1__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_1__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_2 (0x00AAC5B0) +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_2___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_2__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_2__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_3 (0x00AAC5B4) +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_3___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_3__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_3__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_4 (0x00AAC5B8) +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_4___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_4__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_4__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_5 (0x00AAC5BC) +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_5___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_5__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_5__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_6 (0x00AAC5C0) +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_6___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_6__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_6__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_7 (0x00AAC5C4) +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_7___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_7__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_DEBUG_7__LUT_VALUE___S 0 + +#define WMAC0_HWSCH_R0_CCA_SW_EN_COEX (0x00AAC5C8) +#define WMAC0_HWSCH_R0_CCA_SW_EN_COEX___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_COEX___POR 0x00000200 +#define WMAC0_HWSCH_R0_CCA_SW_EN_COEX__LUT_VALUE_RX_FRAME___POR 0x1 +#define WMAC0_HWSCH_R0_CCA_SW_EN_COEX__LUT_VALUE___POR 0x000 +#define WMAC0_HWSCH_R0_CCA_SW_EN_COEX__LUT_VALUE_RX_FRAME___M 0x00000600 +#define WMAC0_HWSCH_R0_CCA_SW_EN_COEX__LUT_VALUE_RX_FRAME___S 9 +#define WMAC0_HWSCH_R0_CCA_SW_EN_COEX__LUT_VALUE___M 0x000001FF +#define WMAC0_HWSCH_R0_CCA_SW_EN_COEX__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_COEX___M 0x000007FF +#define WMAC0_HWSCH_R0_CCA_SW_EN_COEX___S 0 + +#define WMAC0_HWSCH_R0_CCA_SW_EN_SIFS (0x00AAC5CC) +#define WMAC0_HWSCH_R0_CCA_SW_EN_SIFS___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_SIFS___POR 0x00000000 +#define WMAC0_HWSCH_R0_CCA_SW_EN_SIFS__LUT_VALUE___POR 0x0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_SIFS__LUT_VALUE___M 0x00000007 +#define WMAC0_HWSCH_R0_CCA_SW_EN_SIFS__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_SIFS___M 0x00000007 +#define WMAC0_HWSCH_R0_CCA_SW_EN_SIFS___S 0 + +#define WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_n(n) (0x00AAC5D0+0x4*(n)) +#define WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_n_nMIN 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_n_nMAX 1 +#define WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_n_ELEM 2 +#define WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_n___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_n___POR 0x00000000 +#define WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_n__LUT_VALUE___POR 0x00000000 +#define WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_n__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_n__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_n___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_n___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_0 (0x00AAC5D0) +#define WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_0__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_0__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_1 (0x00AAC5D4) +#define WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_1__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CCA_SW_EN_TXPCU_1__LUT_VALUE___S 0 + +#define WMAC0_HWSCH_R0_REJECTION_FILTER_THRESHOLD (0x00AAC5D8) +#define WMAC0_HWSCH_R0_REJECTION_FILTER_THRESHOLD___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_REJECTION_FILTER_THRESHOLD___POR 0x00000000 +#define WMAC0_HWSCH_R0_REJECTION_FILTER_THRESHOLD__THRESHOLD_VALUE___POR 0x0000 +#define WMAC0_HWSCH_R0_REJECTION_FILTER_THRESHOLD__THRESHOLD_VALUE___M 0x0000FFFF +#define WMAC0_HWSCH_R0_REJECTION_FILTER_THRESHOLD__THRESHOLD_VALUE___S 0 +#define WMAC0_HWSCH_R0_REJECTION_FILTER_THRESHOLD___M 0x0000FFFF +#define WMAC0_HWSCH_R0_REJECTION_FILTER_THRESHOLD___S 0 + +#define WMAC0_HWSCH_R0_CCA_SW_EN_RX_CLEAR (0x00AAC5DC) +#define WMAC0_HWSCH_R0_CCA_SW_EN_RX_CLEAR___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CCA_SW_EN_RX_CLEAR___POR 0x000001C0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_RX_CLEAR__LUT_VALUE___POR 0x1C0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_RX_CLEAR__LUT_VALUE___M 0x000003FF +#define WMAC0_HWSCH_R0_CCA_SW_EN_RX_CLEAR__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_CCA_SW_EN_RX_CLEAR___M 0x000003FF +#define WMAC0_HWSCH_R0_CCA_SW_EN_RX_CLEAR___S 0 + +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_n(n) (0x00AAC5E0+0x4*(n)) +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_n_nMIN 0 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_n_nMAX 9 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_n_ELEM 10 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_n___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_n___POR 0x00000000 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_n__CNT_VALUE___POR 0x00000000 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_n__CNT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_n__CNT_VALUE___S 0 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_n___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_n___S 0 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_0 (0x00AAC5E0) +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_0__CNT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_0__CNT_VALUE___S 0 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_1 (0x00AAC5E4) +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_1__CNT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_1__CNT_VALUE___S 0 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_2 (0x00AAC5E8) +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_2___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_2__CNT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_2__CNT_VALUE___S 0 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_3 (0x00AAC5EC) +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_3___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_3__CNT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_3__CNT_VALUE___S 0 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_4 (0x00AAC5F0) +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_4___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_4__CNT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_4__CNT_VALUE___S 0 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_5 (0x00AAC5F4) +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_5___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_5__CNT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_5__CNT_VALUE___S 0 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_6 (0x00AAC5F8) +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_6___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_6__CNT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_6__CNT_VALUE___S 0 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_7 (0x00AAC5FC) +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_7___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_7__CNT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_7__CNT_VALUE___S 0 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_8 (0x00AAC600) +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_8___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_8__CNT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_8__CNT_VALUE___S 0 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_9 (0x00AAC604) +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_9___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_9__CNT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_9__CNT_VALUE___S 0 + +#define WMAC0_HWSCH_R0_TQM_FLUSH_ACK (0x00AAC608) +#define WMAC0_HWSCH_R0_TQM_FLUSH_ACK___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_TQM_FLUSH_ACK___POR 0x00000000 +#define WMAC0_HWSCH_R0_TQM_FLUSH_ACK__VALUE___POR 0x0 +#define WMAC0_HWSCH_R0_TQM_FLUSH_ACK__VALUE___M 0x00000001 +#define WMAC0_HWSCH_R0_TQM_FLUSH_ACK__VALUE___S 0 +#define WMAC0_HWSCH_R0_TQM_FLUSH_ACK___M 0x00000001 +#define WMAC0_HWSCH_R0_TQM_FLUSH_ACK___S 0 + +#define WMAC0_HWSCH_R0_MASK_FES_STATUS_INTR (0x00AAC60C) +#define WMAC0_HWSCH_R0_MASK_FES_STATUS_INTR___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_MASK_FES_STATUS_INTR___POR 0x00000000 +#define WMAC0_HWSCH_R0_MASK_FES_STATUS_INTR__VALUE___POR 0x00000000 +#define WMAC0_HWSCH_R0_MASK_FES_STATUS_INTR__VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_MASK_FES_STATUS_INTR__VALUE___S 0 +#define WMAC0_HWSCH_R0_MASK_FES_STATUS_INTR___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_MASK_FES_STATUS_INTR___S 0 + +#define WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_MSB (0x00AAC610) +#define WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_MSB___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_MSB___POR 0x00000000 +#define WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_MSB__VALUE___POR 0x00 +#define WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_MSB__VALUE___M 0x000000FF +#define WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_MSB__VALUE___S 0 +#define WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_MSB___M 0x000000FF +#define WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_MSB___S 0 + +#define WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_LSB (0x00AAC614) +#define WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_LSB___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_LSB___POR 0x00000000 +#define WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_LSB__VALUE___POR 0x00000000 +#define WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_LSB__VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_LSB__VALUE___S 0 +#define WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_LSB___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_FES_STATUS_HEAD_PTR_ADDR_LSB___S 0 + +#define WMAC0_HWSCH_R0_SFM_BLK_CTRL (0x00AAC618) +#define WMAC0_HWSCH_R0_SFM_BLK_CTRL___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SFM_BLK_CTRL___POR 0x00040020 +#define WMAC0_HWSCH_R0_SFM_BLK_CTRL__FES_STAT_PACKING_EN___POR 0x0 +#define WMAC0_HWSCH_R0_SFM_BLK_CTRL__MPK_PACKING_LIMIT___POR 0x04 +#define WMAC0_HWSCH_R0_SFM_BLK_CTRL__SFM_SPACE_CHECK_EN___POR 0x0 +#define WMAC0_HWSCH_R0_SFM_BLK_CTRL__SFM_APB_DELAY_LIMIT___POR 0x20 +#define WMAC0_HWSCH_R0_SFM_BLK_CTRL__FES_STAT_PACKING_EN___M 0x01000000 +#define WMAC0_HWSCH_R0_SFM_BLK_CTRL__FES_STAT_PACKING_EN___S 24 +#define WMAC0_HWSCH_R0_SFM_BLK_CTRL__MPK_PACKING_LIMIT___M 0x00FF0000 +#define WMAC0_HWSCH_R0_SFM_BLK_CTRL__MPK_PACKING_LIMIT___S 16 +#define WMAC0_HWSCH_R0_SFM_BLK_CTRL__SFM_SPACE_CHECK_EN___M 0x00000100 +#define WMAC0_HWSCH_R0_SFM_BLK_CTRL__SFM_SPACE_CHECK_EN___S 8 +#define WMAC0_HWSCH_R0_SFM_BLK_CTRL__SFM_APB_DELAY_LIMIT___M 0x000000FF +#define WMAC0_HWSCH_R0_SFM_BLK_CTRL__SFM_APB_DELAY_LIMIT___S 0 +#define WMAC0_HWSCH_R0_SFM_BLK_CTRL___M 0x01FF01FF +#define WMAC0_HWSCH_R0_SFM_BLK_CTRL___S 0 + +#define WMAC0_HWSCH_R0_INBSS_NAV_CNT (0x00AAC61C) +#define WMAC0_HWSCH_R0_INBSS_NAV_CNT___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_INBSS_NAV_CNT___POR 0x00000000 +#define WMAC0_HWSCH_R0_INBSS_NAV_CNT__INBSS_NAV_CNT___POR 0x00000000 +#define WMAC0_HWSCH_R0_INBSS_NAV_CNT__INBSS_NAV_CNT___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_INBSS_NAV_CNT__INBSS_NAV_CNT___S 0 +#define WMAC0_HWSCH_R0_INBSS_NAV_CNT___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_INBSS_NAV_CNT___S 0 + +#define WMAC0_HWSCH_R0_SW_MTU_SHADOW_INBSS_NAV_CNT (0x00AAC620) +#define WMAC0_HWSCH_R0_SW_MTU_SHADOW_INBSS_NAV_CNT___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SW_MTU_SHADOW_INBSS_NAV_CNT___POR 0x00000000 +#define WMAC0_HWSCH_R0_SW_MTU_SHADOW_INBSS_NAV_CNT__SW_MTU_SHADOW_INBSS_NAV_CNT___POR 0x00000000 +#define WMAC0_HWSCH_R0_SW_MTU_SHADOW_INBSS_NAV_CNT__SW_MTU_SHADOW_INBSS_NAV_CNT___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SW_MTU_SHADOW_INBSS_NAV_CNT__SW_MTU_SHADOW_INBSS_NAV_CNT___S 0 +#define WMAC0_HWSCH_R0_SW_MTU_SHADOW_INBSS_NAV_CNT___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SW_MTU_SHADOW_INBSS_NAV_CNT___S 0 + +#define WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL (0x00AAC624) +#define WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL___POR 0x0077000F +#define WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL__SW_MTU_RTS_INBSS_NAV_11B_TO_LIMIT___POR 0x0EE +#define WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL__SW_MTU_INBSS_NAV_BASED_ON_RTS_VALID___POR 0x0 +#define WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL__SW_MTU_RTS_INBSS_NAV_TO_LIMIT___POR 0x00F +#define WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL__SW_MTU_RTS_INBSS_NAV_11B_TO_LIMIT___M 0x07FF8000 +#define WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL__SW_MTU_RTS_INBSS_NAV_11B_TO_LIMIT___S 15 +#define WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL__SW_MTU_INBSS_NAV_BASED_ON_RTS_VALID___M 0x00001000 +#define WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL__SW_MTU_INBSS_NAV_BASED_ON_RTS_VALID___S 12 +#define WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL__SW_MTU_RTS_INBSS_NAV_TO_LIMIT___M 0x00000FFF +#define WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL__SW_MTU_RTS_INBSS_NAV_TO_LIMIT___S 0 +#define WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL___M 0x07FF9FFF +#define WMAC0_HWSCH_R0_MTU_INBSS_NAV_CONTROL___S 0 + +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_n(n) (0x00AAC628+0x4*(n)) +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_n_nMIN 0 +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_n_nMAX 4 +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_n_ELEM 5 +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_n___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_n___POR 0x00000000 +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_n__VALUE___POR 0x00000000 +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_n__VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_n__VALUE___S 0 +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_n___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_n___S 0 +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_0 (0x00AAC628) +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_0___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_0__VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_0__VALUE___S 0 +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_1 (0x00AAC62C) +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_1___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_1__VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_1__VALUE___S 0 +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_2 (0x00AAC630) +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_2___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_2__VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_2__VALUE___S 0 +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_3 (0x00AAC634) +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_3___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_3__VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_3__VALUE___S 0 +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_4 (0x00AAC638) +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_4___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_4__VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_RECEIVED_TRIGGER_INFO_DETAILS_4__VALUE___S 0 + +#define WMAC0_HWSCH_R0_ENABLE_PM_FILTERING_MU (0x00AAC63C) +#define WMAC0_HWSCH_R0_ENABLE_PM_FILTERING_MU___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_ENABLE_PM_FILTERING_MU___POR 0x0000000C +#define WMAC0_HWSCH_R0_ENABLE_PM_FILTERING_MU__LOCK_CACHE_SIZE___POR 0x06 +#define WMAC0_HWSCH_R0_ENABLE_PM_FILTERING_MU__VALUE___POR 0x0 +#define WMAC0_HWSCH_R0_ENABLE_PM_FILTERING_MU__LOCK_CACHE_SIZE___M 0x0000003E +#define WMAC0_HWSCH_R0_ENABLE_PM_FILTERING_MU__LOCK_CACHE_SIZE___S 1 +#define WMAC0_HWSCH_R0_ENABLE_PM_FILTERING_MU__VALUE___M 0x00000001 +#define WMAC0_HWSCH_R0_ENABLE_PM_FILTERING_MU__VALUE___S 0 +#define WMAC0_HWSCH_R0_ENABLE_PM_FILTERING_MU___M 0x0000003F +#define WMAC0_HWSCH_R0_ENABLE_PM_FILTERING_MU___S 0 + +#define WMAC0_HWSCH_R0_DEBUG_SFM_CLR (0x00AAC640) +#define WMAC0_HWSCH_R0_DEBUG_SFM_CLR___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_DEBUG_SFM_CLR___POR 0x00000000 +#define WMAC0_HWSCH_R0_DEBUG_SFM_CLR__VALUE___POR 0x000000 +#define WMAC0_HWSCH_R0_DEBUG_SFM_CLR__VALUE___M 0x00FFFFFF +#define WMAC0_HWSCH_R0_DEBUG_SFM_CLR__VALUE___S 0 +#define WMAC0_HWSCH_R0_DEBUG_SFM_CLR___M 0x00FFFFFF +#define WMAC0_HWSCH_R0_DEBUG_SFM_CLR___S 0 + +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL (0x00AAC644) +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL___POR 0x00000000 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__SELECT_LP_SR_CNTR_NEW___POR 0x0 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__LP_SR_SIGNAL_SEL___POR 0x0 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__IGNORE_NAV_CNT_IN_MED_RX_IDLE___POR 0x0 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__OBSS_CCA_COUNT_CONDITION___POR 0x0 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__RX_CLEAR_COUNT_CONDITION___POR 0x0 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__FREEZE_CNT___POR 0x0 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__WRAP_CNT___POR 0x0 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__SELECT_LP_SR_CNTR_NEW___M 0x00000100 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__SELECT_LP_SR_CNTR_NEW___S 8 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__LP_SR_SIGNAL_SEL___M 0x000000C0 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__LP_SR_SIGNAL_SEL___S 6 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__IGNORE_NAV_CNT_IN_MED_RX_IDLE___M 0x00000030 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__IGNORE_NAV_CNT_IN_MED_RX_IDLE___S 4 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__OBSS_CCA_COUNT_CONDITION___M 0x00000008 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__OBSS_CCA_COUNT_CONDITION___S 3 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__RX_CLEAR_COUNT_CONDITION___M 0x00000004 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__RX_CLEAR_COUNT_CONDITION___S 2 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__FREEZE_CNT___M 0x00000002 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__FREEZE_CNT___S 1 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__WRAP_CNT___M 0x00000001 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL__WRAP_CNT___S 0 +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL___M 0x000001FF +#define WMAC0_HWSCH_R0_LOW_POWER_CNTR_CTRL___S 0 + +#define WMAC0_HWSCH_R0_LOW_POWER_IDLE_CNTR_CONTROL (0x00AAC648) +#define WMAC0_HWSCH_R0_LOW_POWER_IDLE_CNTR_CONTROL___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_LOW_POWER_IDLE_CNTR_CONTROL___POR 0x00000000 +#define WMAC0_HWSCH_R0_LOW_POWER_IDLE_CNTR_CONTROL__RING_SELECT___POR 0x00000 +#define WMAC0_HWSCH_R0_LOW_POWER_IDLE_CNTR_CONTROL__RING_SELECT___M 0x0003FFFF +#define WMAC0_HWSCH_R0_LOW_POWER_IDLE_CNTR_CONTROL__RING_SELECT___S 0 +#define WMAC0_HWSCH_R0_LOW_POWER_IDLE_CNTR_CONTROL___M 0x0003FFFF +#define WMAC0_HWSCH_R0_LOW_POWER_IDLE_CNTR_CONTROL___S 0 + +#define WMAC0_HWSCH_R0_DEBUG_FES_STAT_HD_PTR_WR (0x00AAC64C) +#define WMAC0_HWSCH_R0_DEBUG_FES_STAT_HD_PTR_WR___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_DEBUG_FES_STAT_HD_PTR_WR___POR 0x00000000 +#define WMAC0_HWSCH_R0_DEBUG_FES_STAT_HD_PTR_WR__VALUE___POR 0x0000 +#define WMAC0_HWSCH_R0_DEBUG_FES_STAT_HD_PTR_WR__VALUE___M 0x0000FFFF +#define WMAC0_HWSCH_R0_DEBUG_FES_STAT_HD_PTR_WR__VALUE___S 0 +#define WMAC0_HWSCH_R0_DEBUG_FES_STAT_HD_PTR_WR___M 0x0000FFFF +#define WMAC0_HWSCH_R0_DEBUG_FES_STAT_HD_PTR_WR___S 0 + +#define WMAC0_HWSCH_R0_DEBUG_NO_SYNC_STAGE (0x00AAC650) +#define WMAC0_HWSCH_R0_DEBUG_NO_SYNC_STAGE___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_DEBUG_NO_SYNC_STAGE___POR 0x00000004 +#define WMAC0_HWSCH_R0_DEBUG_NO_SYNC_STAGE__VALUE___POR 0x04 +#define WMAC0_HWSCH_R0_DEBUG_NO_SYNC_STAGE__VALUE___M 0x0000001F +#define WMAC0_HWSCH_R0_DEBUG_NO_SYNC_STAGE__VALUE___S 0 +#define WMAC0_HWSCH_R0_DEBUG_NO_SYNC_STAGE___M 0x0000001F +#define WMAC0_HWSCH_R0_DEBUG_NO_SYNC_STAGE___S 0 + +#define WMAC0_HWSCH_R0_COEX_POWER_SAVE_NAP_OFFSET (0x00AAC654) +#define WMAC0_HWSCH_R0_COEX_POWER_SAVE_NAP_OFFSET___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_COEX_POWER_SAVE_NAP_OFFSET___POR 0x00000000 +#define WMAC0_HWSCH_R0_COEX_POWER_SAVE_NAP_OFFSET__VALUE___POR 0x0000 +#define WMAC0_HWSCH_R0_COEX_POWER_SAVE_NAP_OFFSET__VALUE___M 0x00003FFF +#define WMAC0_HWSCH_R0_COEX_POWER_SAVE_NAP_OFFSET__VALUE___S 0 +#define WMAC0_HWSCH_R0_COEX_POWER_SAVE_NAP_OFFSET___M 0x00003FFF +#define WMAC0_HWSCH_R0_COEX_POWER_SAVE_NAP_OFFSET___S 0 + +#define WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE (0x00AAC658) +#define WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE___POR 0x027FFFFB +#define WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE__OFDMA_TRIG_DETAILS_IN_SCH_STAT_EN___POR 0x0 +#define WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE__VALUE___POR 0x027FFFFB +#define WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE__OFDMA_TRIG_DETAILS_IN_SCH_STAT_EN___M 0x80000000 +#define WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE__OFDMA_TRIG_DETAILS_IN_SCH_STAT_EN___S 31 +#define WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE__VALUE___M 0x7FFFFFFF +#define WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE__VALUE___S 0 +#define WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_STATUS_DESC_UPLOAD_ENABLE___S 0 + +#define WMAC0_HWSCH_R0_SPR_REG (0x00AAC65C) +#define WMAC0_HWSCH_R0_SPR_REG___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SPR_REG___POR 0x00000009 +#define WMAC0_HWSCH_R0_SPR_REG__SPR_VAL___POR 0x00000009 +#define WMAC0_HWSCH_R0_SPR_REG__SPR_VAL___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SPR_REG__SPR_VAL___S 0 +#define WMAC0_HWSCH_R0_SPR_REG___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SPR_REG___S 0 + +#define WMAC0_HWSCH_R0_SPR_EXT_REG (0x00AAC660) +#define WMAC0_HWSCH_R0_SPR_EXT_REG___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SPR_EXT_REG___POR 0xFFFF0000 +#define WMAC0_HWSCH_R0_SPR_EXT_REG__SPR_EXT_VAL___POR 0xFFFF0000 +#define WMAC0_HWSCH_R0_SPR_EXT_REG__SPR_EXT_VAL___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SPR_EXT_REG__SPR_EXT_VAL___S 0 +#define WMAC0_HWSCH_R0_SPR_EXT_REG___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SPR_EXT_REG___S 0 + +#define WMAC0_HWSCH_R0_SPR2_REG (0x00AAC664) +#define WMAC0_HWSCH_R0_SPR2_REG___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SPR2_REG___POR 0x00000000 +#define WMAC0_HWSCH_R0_SPR2_REG__SPR_VAL___POR 0x00000000 +#define WMAC0_HWSCH_R0_SPR2_REG__SPR_VAL___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SPR2_REG__SPR_VAL___S 0 +#define WMAC0_HWSCH_R0_SPR2_REG___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SPR2_REG___S 0 + +#define WMAC0_HWSCH_R0_PREBKOFF_SLOT_ALIGNMENT_CTRL (0x00AAC668) +#define WMAC0_HWSCH_R0_PREBKOFF_SLOT_ALIGNMENT_CTRL___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_PREBKOFF_SLOT_ALIGNMENT_CTRL___POR 0x00000000 +#define WMAC0_HWSCH_R0_PREBKOFF_SLOT_ALIGNMENT_CTRL__ENABLE___POR 0x00000 +#define WMAC0_HWSCH_R0_PREBKOFF_SLOT_ALIGNMENT_CTRL__ENABLE___M 0x0003FFFF +#define WMAC0_HWSCH_R0_PREBKOFF_SLOT_ALIGNMENT_CTRL__ENABLE___S 0 +#define WMAC0_HWSCH_R0_PREBKOFF_SLOT_ALIGNMENT_CTRL___M 0x0003FFFF +#define WMAC0_HWSCH_R0_PREBKOFF_SLOT_ALIGNMENT_CTRL___S 0 + +#define WMAC0_HWSCH_R0_ENABLE_DYN_AIFS_ADJUST_FOR_LOW_BKOFF (0x00AAC66C) +#define WMAC0_HWSCH_R0_ENABLE_DYN_AIFS_ADJUST_FOR_LOW_BKOFF___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_ENABLE_DYN_AIFS_ADJUST_FOR_LOW_BKOFF___POR 0x00000000 +#define WMAC0_HWSCH_R0_ENABLE_DYN_AIFS_ADJUST_FOR_LOW_BKOFF__ENABLE___POR 0x00000 +#define WMAC0_HWSCH_R0_ENABLE_DYN_AIFS_ADJUST_FOR_LOW_BKOFF__ENABLE___M 0x0003FFFF +#define WMAC0_HWSCH_R0_ENABLE_DYN_AIFS_ADJUST_FOR_LOW_BKOFF__ENABLE___S 0 +#define WMAC0_HWSCH_R0_ENABLE_DYN_AIFS_ADJUST_FOR_LOW_BKOFF___M 0x0003FFFF +#define WMAC0_HWSCH_R0_ENABLE_DYN_AIFS_ADJUST_FOR_LOW_BKOFF___S 0 + +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0 (0x00AAC670) +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0___POR 0x00000000 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0__ALT_PRE_BKOFF_RING3___POR 0x00 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0__ALT_PRE_BKOFF_RING2___POR 0x00 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0__ALT_PRE_BKOFF_RING1___POR 0x00 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0__ALT_PRE_BKOFF_RING0___POR 0x00 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0__ALT_PRE_BKOFF_RING3___M 0xFF000000 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0__ALT_PRE_BKOFF_RING3___S 24 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0__ALT_PRE_BKOFF_RING2___M 0x00FF0000 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0__ALT_PRE_BKOFF_RING2___S 16 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0__ALT_PRE_BKOFF_RING1___M 0x0000FF00 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0__ALT_PRE_BKOFF_RING1___S 8 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0__ALT_PRE_BKOFF_RING0___M 0x000000FF +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0__ALT_PRE_BKOFF_RING0___S 0 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_0___S 0 + +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1 (0x00AAC674) +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1___POR 0x00000000 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1__ALT_PRE_BKOFF_RING7___POR 0x00 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1__ALT_PRE_BKOFF_RING6___POR 0x00 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1__ALT_PRE_BKOFF_RING5___POR 0x00 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1__ALT_PRE_BKOFF_RING4___POR 0x00 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1__ALT_PRE_BKOFF_RING7___M 0xFF000000 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1__ALT_PRE_BKOFF_RING7___S 24 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1__ALT_PRE_BKOFF_RING6___M 0x00FF0000 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1__ALT_PRE_BKOFF_RING6___S 16 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1__ALT_PRE_BKOFF_RING5___M 0x0000FF00 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1__ALT_PRE_BKOFF_RING5___S 8 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1__ALT_PRE_BKOFF_RING4___M 0x000000FF +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1__ALT_PRE_BKOFF_RING4___S 0 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_1___S 0 + +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2 (0x00AAC678) +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2___POR 0x00000000 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2__ALT_PRE_BKOFF_RING11___POR 0x00 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2__ALT_PRE_BKOFF_RING10___POR 0x00 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2__ALT_PRE_BKOFF_RING9___POR 0x00 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2__ALT_PRE_BKOFF_RING8___POR 0x00 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2__ALT_PRE_BKOFF_RING11___M 0xFF000000 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2__ALT_PRE_BKOFF_RING11___S 24 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2__ALT_PRE_BKOFF_RING10___M 0x00FF0000 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2__ALT_PRE_BKOFF_RING10___S 16 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2__ALT_PRE_BKOFF_RING9___M 0x0000FF00 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2__ALT_PRE_BKOFF_RING9___S 8 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2__ALT_PRE_BKOFF_RING8___M 0x000000FF +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2__ALT_PRE_BKOFF_RING8___S 0 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_2___S 0 + +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3 (0x00AAC67C) +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3___POR 0x00000000 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3__ALT_PRE_BKOFF_RING15___POR 0x00 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3__ALT_PRE_BKOFF_RING14___POR 0x00 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3__ALT_PRE_BKOFF_RING13___POR 0x00 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3__ALT_PRE_BKOFF_RING12___POR 0x00 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3__ALT_PRE_BKOFF_RING15___M 0xFF000000 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3__ALT_PRE_BKOFF_RING15___S 24 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3__ALT_PRE_BKOFF_RING14___M 0x00FF0000 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3__ALT_PRE_BKOFF_RING14___S 16 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3__ALT_PRE_BKOFF_RING13___M 0x0000FF00 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3__ALT_PRE_BKOFF_RING13___S 8 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3__ALT_PRE_BKOFF_RING12___M 0x000000FF +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3__ALT_PRE_BKOFF_RING12___S 0 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_3___S 0 + +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_4 (0x00AAC680) +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_4___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_4___POR 0x00000000 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_4__ALT_PRE_BKOFF_RING17___POR 0x00 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_4__ALT_PRE_BKOFF_RING16___POR 0x00 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_4__ALT_PRE_BKOFF_RING17___M 0x0000FF00 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_4__ALT_PRE_BKOFF_RING17___S 8 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_4__ALT_PRE_BKOFF_RING16___M 0x000000FF +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_4__ALT_PRE_BKOFF_RING16___S 0 +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_4___M 0x0000FFFF +#define WMAC0_HWSCH_R0_ALTERNATIVE_HWSCH_PREBKOFF_LIMITS_IX_4___S 0 + +#define WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_0 (0x00AAC684) +#define WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_0___POR 0x00000400 +#define WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_0__SW_MTU_COEX_BKOFF_BLOCK_TIMEOUT___POR 0x0400 +#define WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_0__SW_MTU_COEX_BKOFF_BLOCK_TIMEOUT___M 0x0000FFFF +#define WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_0__SW_MTU_COEX_BKOFF_BLOCK_TIMEOUT___S 0 +#define WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_0___M 0x0000FFFF +#define WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_0___S 0 + +#define WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_1 (0x00AAC688) +#define WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_1___POR 0x00000000 +#define WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_1__SW_MTU_COEX_BKOFF_BLOCK_ENABLE___POR 0x00000 +#define WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_1__SW_MTU_COEX_BKOFF_BLOCK_ENABLE___M 0x0003FFFF +#define WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_1__SW_MTU_COEX_BKOFF_BLOCK_ENABLE___S 0 +#define WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_1___M 0x0003FFFF +#define WMAC0_HWSCH_R0_COEX_VIRTUAL_CCA_CTRL_IX_1___S 0 + +#define WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL (0x00AAC68C) +#define WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL___POR 0x00000000 +#define WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL__ENABLE_CARRIER_SENSE_FOR_ALL_TRIGGERS___POR 0x0 +#define WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL__ENABLE_R2R_MBA_WAIT_WITH_RESP_STATS___POR 0x0 +#define WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL__ENABLE_R2R_MBA_WAIT_WO_RESP_STATS___POR 0x0 +#define WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL__ENABLE_TRIG_TID_AGG_LIM_ZERO_CHK___POR 0x0 +#define WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL__SW_MTU_RAW_BW_AVAIL_WIN_LIMIT___POR 0x0000 +#define WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL__ENABLE_CARRIER_SENSE_FOR_ALL_TRIGGERS___M 0x00080000 +#define WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL__ENABLE_CARRIER_SENSE_FOR_ALL_TRIGGERS___S 19 +#define WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL__ENABLE_R2R_MBA_WAIT_WITH_RESP_STATS___M 0x00040000 +#define WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL__ENABLE_R2R_MBA_WAIT_WITH_RESP_STATS___S 18 +#define WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL__ENABLE_R2R_MBA_WAIT_WO_RESP_STATS___M 0x00020000 +#define WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL__ENABLE_R2R_MBA_WAIT_WO_RESP_STATS___S 17 +#define WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL__ENABLE_TRIG_TID_AGG_LIM_ZERO_CHK___M 0x00010000 +#define WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL__ENABLE_TRIG_TID_AGG_LIM_ZERO_CHK___S 16 +#define WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL__SW_MTU_RAW_BW_AVAIL_WIN_LIMIT___M 0x0000FFFF +#define WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL__SW_MTU_RAW_BW_AVAIL_WIN_LIMIT___S 0 +#define WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL___M 0x000FFFFF +#define WMAC0_HWSCH_R0_11AX_CCA_SENSING_CTRL___S 0 + +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL (0x00AAC690) +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL___POR 0x00000000 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR17_RBO_LKAHD_EN___POR 0x0 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR16_RBO_LKAHD_EN___POR 0x0 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR15_RBO_LKAHD_EN___POR 0x0 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR14_RBO_LKAHD_EN___POR 0x0 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR13_RBO_LKAHD_EN___POR 0x0 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR12_RBO_LKAHD_EN___POR 0x0 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR11_RBO_LKAHD_EN___POR 0x0 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR10_RBO_LKAHD_EN___POR 0x0 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR9_RBO_LKAHD_EN___POR 0x0 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR8_RBO_LKAHD_EN___POR 0x0 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR7_RBO_LKAHD_EN___POR 0x0 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR6_RBO_LKAHD_EN___POR 0x0 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR5_RBO_LKAHD_EN___POR 0x0 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR4_RBO_LKAHD_EN___POR 0x0 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR3_RBO_LKAHD_EN___POR 0x0 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR2_RBO_LKAHD_EN___POR 0x0 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR1_RBO_LKAHD_EN___POR 0x0 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR0_RBO_LKAHD_EN___POR 0x0 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR17_RBO_LKAHD_EN___M 0x00020000 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR17_RBO_LKAHD_EN___S 17 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR16_RBO_LKAHD_EN___M 0x00010000 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR16_RBO_LKAHD_EN___S 16 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR15_RBO_LKAHD_EN___M 0x00008000 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR15_RBO_LKAHD_EN___S 15 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR14_RBO_LKAHD_EN___M 0x00004000 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR14_RBO_LKAHD_EN___S 14 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR13_RBO_LKAHD_EN___M 0x00002000 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR13_RBO_LKAHD_EN___S 13 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR12_RBO_LKAHD_EN___M 0x00001000 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR12_RBO_LKAHD_EN___S 12 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR11_RBO_LKAHD_EN___M 0x00000800 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR11_RBO_LKAHD_EN___S 11 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR10_RBO_LKAHD_EN___M 0x00000400 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR10_RBO_LKAHD_EN___S 10 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR9_RBO_LKAHD_EN___M 0x00000200 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR9_RBO_LKAHD_EN___S 9 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR8_RBO_LKAHD_EN___M 0x00000100 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR8_RBO_LKAHD_EN___S 8 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR7_RBO_LKAHD_EN___M 0x00000080 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR7_RBO_LKAHD_EN___S 7 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR6_RBO_LKAHD_EN___M 0x00000040 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR6_RBO_LKAHD_EN___S 6 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR5_RBO_LKAHD_EN___M 0x00000020 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR5_RBO_LKAHD_EN___S 5 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR4_RBO_LKAHD_EN___M 0x00000010 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR4_RBO_LKAHD_EN___S 4 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR3_RBO_LKAHD_EN___M 0x00000008 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR3_RBO_LKAHD_EN___S 3 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR2_RBO_LKAHD_EN___M 0x00000004 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR2_RBO_LKAHD_EN___S 2 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR1_RBO_LKAHD_EN___M 0x00000002 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR1_RBO_LKAHD_EN___S 1 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR0_RBO_LKAHD_EN___M 0x00000001 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL__CMD_MGR0_RBO_LKAHD_EN___S 0 +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL___M 0x0003FFFF +#define WMAC0_HWSCH_R0_RBO_LOOKAHEAD_CONTROL___S 0 + +#define WMAC0_HWSCH_R0_CW_ACTION_CTRL2 (0x00AAC694) +#define WMAC0_HWSCH_R0_CW_ACTION_CTRL2___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CW_ACTION_CTRL2___POR 0x00000000 +#define WMAC0_HWSCH_R0_CW_ACTION_CTRL2__CW_ACTION_CTRL2___POR 0x00000000 +#define WMAC0_HWSCH_R0_CW_ACTION_CTRL2__CW_ACTION_CTRL2___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CW_ACTION_CTRL2__CW_ACTION_CTRL2___S 0 +#define WMAC0_HWSCH_R0_CW_ACTION_CTRL2___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CW_ACTION_CTRL2___S 0 + +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0 (0x00AAC698) +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0___POR 0x00000000 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL15___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL14___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL13___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL12___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL11___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL10___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL9___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL8___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL7___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL6___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL5___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL4___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL3___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL2___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL1___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL0___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL15___M 0xC0000000 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL15___S 30 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL14___M 0x30000000 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL14___S 28 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL13___M 0x0C000000 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL13___S 26 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL12___M 0x03000000 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL12___S 24 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL11___M 0x00C00000 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL11___S 22 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL10___M 0x00300000 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL10___S 20 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL9___M 0x000C0000 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL9___S 18 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL8___M 0x00030000 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL8___S 16 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL7___M 0x0000C000 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL7___S 14 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL6___M 0x00003000 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL6___S 12 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL5___M 0x00000C00 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL5___S 10 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL4___M 0x00000300 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL4___S 8 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL3___M 0x000000C0 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL3___S 6 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL2___M 0x00000030 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL2___S 4 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL1___M 0x0000000C +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL1___S 2 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL0___M 0x00000003 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0__FLEX_REQ_LIM_SEL0___S 0 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_0___S 0 + +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1 (0x00AAC69C) +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1___POR 0x00000000 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL26___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL25___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL24___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL23___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL22___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL21___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL20___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL19___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL18___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL17___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL16___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL26___M 0x00300000 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL26___S 20 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL25___M 0x000C0000 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL25___S 18 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL24___M 0x00030000 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL24___S 16 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL23___M 0x0000C000 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL23___S 14 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL22___M 0x00003000 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL22___S 12 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL21___M 0x00000C00 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL21___S 10 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL20___M 0x00000300 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL20___S 8 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL19___M 0x000000C0 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL19___S 6 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL18___M 0x00000030 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL18___S 4 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL17___M 0x0000000C +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL17___S 2 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL16___M 0x00000003 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1__FLEX_REQ_LIM_SEL16___S 0 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1___M 0x003FFFFF +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_1___S 0 + +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2 (0x00AAC6A0) +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2___POR 0xFFFFFF03 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2__FLEX_REQ_LIM2___POR 0xFF +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2__FLEX_REQ_LIM1___POR 0xFF +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2__FLEX_REQ_LIM0___POR 0xFF +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2__REQUEUE_LIMIT___POR 0x03 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2__FLEX_REQ_LIM2___M 0xFF000000 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2__FLEX_REQ_LIM2___S 24 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2__FLEX_REQ_LIM1___M 0x00FF0000 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2__FLEX_REQ_LIM1___S 16 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2__FLEX_REQ_LIM0___M 0x0000FF00 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2__FLEX_REQ_LIM0___S 8 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2__REQUEUE_LIMIT___M 0x000000FF +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2__REQUEUE_LIMIT___S 0 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_2___S 0 + +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3 (0x00AAC6A4) +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3___POR 0x00000005 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3__INCORRECT_FLREQ_FIX_ENABLE___POR 0x1 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3__EN_HWSCH_RXPCU_SR_SIDEBAND___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3__EN_HWSCH_RXPCU_UORA_SIDEBAND___POR 0x1 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3__INCORRECT_FLREQ_FIX_ENABLE___M 0x00000004 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3__INCORRECT_FLREQ_FIX_ENABLE___S 2 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3__EN_HWSCH_RXPCU_SR_SIDEBAND___M 0x00000002 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3__EN_HWSCH_RXPCU_SR_SIDEBAND___S 1 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3__EN_HWSCH_RXPCU_UORA_SIDEBAND___M 0x00000001 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3__EN_HWSCH_RXPCU_UORA_SIDEBAND___S 0 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3___M 0x00000007 +#define WMAC0_HWSCH_R0_CMD_MGR_ADL_GLB_CTRL_IX_3___S 0 + +#define WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES (0x00AAC6A8) +#define WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES___POR 0x00000010 +#define WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_WR_CH_FES_STAT_WRITE_SECURITY___POR 0x0 +#define WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_WR_CH_FES_STAT_WRITE_POSTED___POR 0x1 +#define WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_WR_CH_FES_STAT_WRITE_PRIORITY___POR 0x0 +#define WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_WR_CH_FES_STAT_BYTE_SWAP___POR 0x0 +#define WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_RD_CH_READ_PRIORITY___POR 0x0 +#define WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_RD_CH_BYTE_SWAP___POR 0x0 +#define WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_WR_CH_FES_STAT_WRITE_SECURITY___M 0x00000020 +#define WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_WR_CH_FES_STAT_WRITE_SECURITY___S 5 +#define WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_WR_CH_FES_STAT_WRITE_POSTED___M 0x00000010 +#define WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_WR_CH_FES_STAT_WRITE_POSTED___S 4 +#define WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_WR_CH_FES_STAT_WRITE_PRIORITY___M 0x00000008 +#define WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_WR_CH_FES_STAT_WRITE_PRIORITY___S 3 +#define WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_WR_CH_FES_STAT_BYTE_SWAP___M 0x00000004 +#define WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_WR_CH_FES_STAT_BYTE_SWAP___S 2 +#define WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_RD_CH_READ_PRIORITY___M 0x00000002 +#define WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_RD_CH_READ_PRIORITY___S 1 +#define WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_RD_CH_BYTE_SWAP___M 0x00000001 +#define WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES__HWSCH_RD_CH_BYTE_SWAP___S 0 +#define WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES___M 0x0000003F +#define WMAC0_HWSCH_R0_GXI_INTERFACE_ATTRIBUTES___S 0 + +#define WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT (0x00AAC6AC) +#define WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT___POR 0x000112C0 +#define WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT__PREBKOF_FORCE_CCA_EN___POR 0x0 +#define WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT__PREBKOF_FORCE_CCA_FRAME_CNT_THR___POR 0x01 +#define WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT__PREBKOF_FORCE_CCA_LIMIT___POR 0x12C0 +#define WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT__PREBKOF_FORCE_CCA_EN___M 0x01000000 +#define WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT__PREBKOF_FORCE_CCA_EN___S 24 +#define WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT__PREBKOF_FORCE_CCA_FRAME_CNT_THR___M 0x00FF0000 +#define WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT__PREBKOF_FORCE_CCA_FRAME_CNT_THR___S 16 +#define WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT__PREBKOF_FORCE_CCA_LIMIT___M 0x0000FFFF +#define WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT__PREBKOF_FORCE_CCA_LIMIT___S 0 +#define WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT___M 0x01FFFFFF +#define WMAC0_HWSCH_R0_PREBKOF_FORCE_CCA_LIMIT___S 0 + +#define WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_0 (0x00AAC6B0) +#define WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_0___POR 0x00000000 +#define WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_0__LUT_VALUE___POR 0x00000000 +#define WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_0__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_0__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_0___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_0___S 0 + +#define WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_1 (0x00AAC6B4) +#define WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_1___POR 0x00000000 +#define WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_1__LUT_VALUE___POR 0x0000 +#define WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_1__LUT_VALUE___M 0x0000FFFF +#define WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_1__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_1___M 0x0000FFFF +#define WMAC0_HWSCH_R0_OBSS_CCA_SW_EN_TXPCU_1___S 0 + +#define WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_LOWER (0x00AAC6B8) +#define WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_LOWER___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_LOWER___POR 0xF0008888 +#define WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_LOWER__LUT_VALUE___POR 0xF0008888 +#define WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_LOWER__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_LOWER__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_LOWER___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_LOWER___S 0 + +#define WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_UPPER (0x00AAC6BC) +#define WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_UPPER___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_UPPER___POR 0xF0000000 +#define WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_UPPER__LUT_VALUE___POR 0xF0000000 +#define WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_UPPER__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_UPPER__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_UPPER___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_OBSS_BKOFF_CFG_LUT_UPPER___S 0 + +#define WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_LOWER (0x00AAC6C0) +#define WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_LOWER___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_LOWER___POR 0xF0008888 +#define WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_LOWER__LUT_VALUE___POR 0xF0008888 +#define WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_LOWER__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_LOWER__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_LOWER___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_LOWER___S 0 + +#define WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_UPPER (0x00AAC6C4) +#define WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_UPPER___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_UPPER___POR 0xF0000000 +#define WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_UPPER__LUT_VALUE___POR 0xF0000000 +#define WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_UPPER__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_UPPER__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_UPPER___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_OBSS_TXPCU_ED0_CFG_LUT_UPPER___S 0 + +#define WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_LOWER (0x00AAC6C8) +#define WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_LOWER___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_LOWER___POR 0xF0008888 +#define WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_LOWER__LUT_VALUE___POR 0xF0008888 +#define WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_LOWER__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_LOWER__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_LOWER___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_LOWER___S 0 + +#define WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_UPPER (0x00AAC6CC) +#define WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_UPPER___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_UPPER___POR 0xF0000000 +#define WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_UPPER__LUT_VALUE___POR 0xF0000000 +#define WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_UPPER__LUT_VALUE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_UPPER__LUT_VALUE___S 0 +#define WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_UPPER___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_OBSS_TXPCU_GI0_CFG_LUT_UPPER___S 0 + +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_0 (0x00AAC6D0) +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_0___POR 0x00000000 +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_0__ASSERT_HP_SYNTH_WHEN_CMD_PENDING___POR 0x00000 +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_0__ASSERT_HP_SYNTH_WHEN_CMD_PENDING___M 0x0003FFFF +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_0__ASSERT_HP_SYNTH_WHEN_CMD_PENDING___S 0 +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_0___M 0x0003FFFF +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_0___S 0 + +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_1 (0x00AAC6D4) +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_1___POR 0x00000000 +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_1__ASSERT_HP_SYNTH_JUST_BEFORE_TX___POR 0x00000 +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_1__ASSERT_HP_SYNTH_JUST_BEFORE_TX___M 0x0003FFFF +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_1__ASSERT_HP_SYNTH_JUST_BEFORE_TX___S 0 +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_1___M 0x0003FFFF +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_1___S 0 + +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2 (0x00AAC6D8) +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2___POR 0x40020020 +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__SW_MTU_HP_SYNTH_FES_END_CHK_FOR_CLR___POR 0x1 +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__SW_MTU_HP_SYNTH_CCA_DLY_EN___POR 0x0 +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__HP_SYNTH_TXFRAME_HYSTERESIS_TIME___POR 0x00 +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__SW_HP_SYNTH_OVERRIDE_CLR___POR 0x0 +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__SW_HP_SYNTH_OVERRIDE_SET___POR 0x0 +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__SW_HP_SYNTH_OVERRIDE_EN___POR 0x0 +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__HP_SYNTH_BKOFF_THRESHOLD___POR 0x2 +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__HP_SYNTH_MIN_SET_TIME___POR 0x0020 +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__SW_MTU_HP_SYNTH_FES_END_CHK_FOR_CLR___M 0x40000000 +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__SW_MTU_HP_SYNTH_FES_END_CHK_FOR_CLR___S 30 +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__SW_MTU_HP_SYNTH_CCA_DLY_EN___M 0x20000000 +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__SW_MTU_HP_SYNTH_CCA_DLY_EN___S 29 +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__HP_SYNTH_TXFRAME_HYSTERESIS_TIME___M 0x1FC00000 +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__HP_SYNTH_TXFRAME_HYSTERESIS_TIME___S 22 +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__SW_HP_SYNTH_OVERRIDE_CLR___M 0x00200000 +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__SW_HP_SYNTH_OVERRIDE_CLR___S 21 +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__SW_HP_SYNTH_OVERRIDE_SET___M 0x00100000 +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__SW_HP_SYNTH_OVERRIDE_SET___S 20 +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__SW_HP_SYNTH_OVERRIDE_EN___M 0x00080000 +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__SW_HP_SYNTH_OVERRIDE_EN___S 19 +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__HP_SYNTH_BKOFF_THRESHOLD___M 0x00070000 +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__HP_SYNTH_BKOFF_THRESHOLD___S 16 +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__HP_SYNTH_MIN_SET_TIME___M 0x0000FFFF +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2__HP_SYNTH_MIN_SET_TIME___S 0 +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2___M 0x7FFFFFFF +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_2___S 0 + +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_3 (0x00AAC6DC) +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_3___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_3___POR 0x00000009 +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_3__HP_VIRCCA_PREEMPT_LIMIT___POR 0x09 +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_3__HP_VIRCCA_PREEMPT_LIMIT___M 0x0000003F +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_3__HP_VIRCCA_PREEMPT_LIMIT___S 0 +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_3___M 0x0000003F +#define WMAC0_HWSCH_R0_LISTEN_MODE_CFG_IX_3___S 0 + +#define WMAC0_HWSCH_R0_SW_MSG_CTRL (0x00AAC6E0) +#define WMAC0_HWSCH_R0_SW_MSG_CTRL___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SW_MSG_CTRL___POR 0x00000000 +#define WMAC0_HWSCH_R0_SW_MSG_CTRL__SW_WRITE_MSG_STATUS___POR 0x0 +#define WMAC0_HWSCH_R0_SW_MSG_CTRL__SW_WRITE_MSG___POR 0x0 +#define WMAC0_HWSCH_R0_SW_MSG_CTRL__SW_WRITE_MSG_STATUS___M 0x80000000 +#define WMAC0_HWSCH_R0_SW_MSG_CTRL__SW_WRITE_MSG_STATUS___S 31 +#define WMAC0_HWSCH_R0_SW_MSG_CTRL__SW_WRITE_MSG___M 0x00000001 +#define WMAC0_HWSCH_R0_SW_MSG_CTRL__SW_WRITE_MSG___S 0 +#define WMAC0_HWSCH_R0_SW_MSG_CTRL___M 0x80000001 +#define WMAC0_HWSCH_R0_SW_MSG_CTRL___S 0 + +#define WMAC0_HWSCH_R0_SW_MSG_DATA_IX_0 (0x00AAC6E4) +#define WMAC0_HWSCH_R0_SW_MSG_DATA_IX_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SW_MSG_DATA_IX_0___POR 0x00000000 +#define WMAC0_HWSCH_R0_SW_MSG_DATA_IX_0__DATA___POR 0x00000000 +#define WMAC0_HWSCH_R0_SW_MSG_DATA_IX_0__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SW_MSG_DATA_IX_0__DATA___S 0 +#define WMAC0_HWSCH_R0_SW_MSG_DATA_IX_0___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SW_MSG_DATA_IX_0___S 0 + +#define WMAC0_HWSCH_R0_SW_MSG_DATA_IX_1 (0x00AAC6E8) +#define WMAC0_HWSCH_R0_SW_MSG_DATA_IX_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SW_MSG_DATA_IX_1___POR 0x00000000 +#define WMAC0_HWSCH_R0_SW_MSG_DATA_IX_1__DATA___POR 0x00000000 +#define WMAC0_HWSCH_R0_SW_MSG_DATA_IX_1__DATA___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SW_MSG_DATA_IX_1__DATA___S 0 +#define WMAC0_HWSCH_R0_SW_MSG_DATA_IX_1___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_SW_MSG_DATA_IX_1___S 0 + +#define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_CFG (0x00AAC6EC) +#define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_CFG___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_CFG___POR 0x00000010 +#define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_CFG__MAX_PENDING_AXI_WRITE_LIMIT___POR 0x08 +#define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_CFG__GXI2GXI_BUFFER_ENABLE___POR 0x0 +#define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_CFG__MAX_PENDING_AXI_WRITE_LIMIT___M 0x0000003E +#define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_CFG__MAX_PENDING_AXI_WRITE_LIMIT___S 1 +#define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_CFG__GXI2GXI_BUFFER_ENABLE___M 0x00000001 +#define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_CFG__GXI2GXI_BUFFER_ENABLE___S 0 +#define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_CFG___M 0x0000003F +#define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_CFG___S 0 + +#define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS (0x00AAC6F0) +#define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS___POR 0x00000000 +#define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS__ERROR_COUNT___POR 0x00 +#define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS__EGRESS_COUNT___POR 0x00 +#define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS__INGRESS_COUNT___POR 0x00 +#define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS__ERROR_COUNT___M 0x00FF0000 +#define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS__ERROR_COUNT___S 16 +#define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS__EGRESS_COUNT___M 0x0000FF00 +#define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS__EGRESS_COUNT___S 8 +#define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS__INGRESS_COUNT___M 0x000000FF +#define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS__INGRESS_COUNT___S 0 +#define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS___M 0x00FFFFFF +#define WMAC0_HWSCH_R0_FES_STATUS_BUFFER_STATS___S 0 + +#define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_CFG (0x00AAC6F4) +#define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_CFG___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_CFG___POR 0x00000000 +#define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_CFG__SRNG2SRNG_BUFFER_ENABLE___POR 0x0 +#define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_CFG__SRNG2SRNG_BUFFER_ENABLE___M 0x00000001 +#define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_CFG__SRNG2SRNG_BUFFER_ENABLE___S 0 +#define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_CFG___M 0x00000001 +#define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_CFG___S 0 + +#define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS (0x00AAC6F8) +#define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS___POR 0x00000000 +#define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS__ERROR_COUNT___POR 0x00 +#define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS__EGR_COUNT___POR 0x00 +#define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS__IGR_COUNT___POR 0x00 +#define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS__ERROR_COUNT___M 0x00FF0000 +#define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS__ERROR_COUNT___S 16 +#define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS__EGR_COUNT___M 0x0000FF00 +#define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS__EGR_COUNT___S 8 +#define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS__IGR_COUNT___M 0x000000FF +#define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS__IGR_COUNT___S 0 +#define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS___M 0x00FFFFFF +#define WMAC0_HWSCH_R0_CMD_STATUS_BUFFER_STATS___S 0 + +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS (0x00AAC6FC) +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS___POR 0x00000000 +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__RESET_ALL_HARD___POR 0x0 +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__RESET_ALL_SOFT___POR 0x0 +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__SET_ALL_HARD___POR 0x0 +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__SET_ALL_SOFT___POR 0x0 +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__HARD_FILTER_VALUE___POR 0x0 +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__SOFT_FILTER_VALUE___POR 0x0 +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__HARD_FILTER_MASK___POR 0x0 +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__SOFT_FILTER_MASK___POR 0x0 +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__ACCESS_TYPE___POR 0x0 +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__FILTER_ID___POR 0x0000 +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__RESET_ALL_HARD___M 0x01000000 +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__RESET_ALL_HARD___S 24 +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__RESET_ALL_SOFT___M 0x00800000 +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__RESET_ALL_SOFT___S 23 +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__SET_ALL_HARD___M 0x00400000 +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__SET_ALL_HARD___S 22 +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__SET_ALL_SOFT___M 0x00200000 +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__SET_ALL_SOFT___S 21 +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__HARD_FILTER_VALUE___M 0x00100000 +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__HARD_FILTER_VALUE___S 20 +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__SOFT_FILTER_VALUE___M 0x00080000 +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__SOFT_FILTER_VALUE___S 19 +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__HARD_FILTER_MASK___M 0x00040000 +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__HARD_FILTER_MASK___S 18 +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__SOFT_FILTER_MASK___M 0x00020000 +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__SOFT_FILTER_MASK___S 17 +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__ACCESS_TYPE___M 0x00010000 +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__ACCESS_TYPE___S 16 +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__FILTER_ID___M 0x0000FFFF +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS__FILTER_ID___S 0 +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS___M 0x01FFFFFF +#define WMAC0_HWSCH_R0_FILTER_LUT_ACCESS___S 0 + +#define WMAC0_HWSCH_R0_FILTER_LUT_DATA (0x00AAC700) +#define WMAC0_HWSCH_R0_FILTER_LUT_DATA___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_FILTER_LUT_DATA___POR 0x00000000 +#define WMAC0_HWSCH_R0_FILTER_LUT_DATA__HARD_FILTER_VALUE___POR 0x0 +#define WMAC0_HWSCH_R0_FILTER_LUT_DATA__SOFT_FILTER_VALUE___POR 0x0 +#define WMAC0_HWSCH_R0_FILTER_LUT_DATA__ACCESS_TYPE___POR 0x0 +#define WMAC0_HWSCH_R0_FILTER_LUT_DATA__FILTER_ID___POR 0x0000 +#define WMAC0_HWSCH_R0_FILTER_LUT_DATA__HARD_FILTER_VALUE___M 0x00040000 +#define WMAC0_HWSCH_R0_FILTER_LUT_DATA__HARD_FILTER_VALUE___S 18 +#define WMAC0_HWSCH_R0_FILTER_LUT_DATA__SOFT_FILTER_VALUE___M 0x00020000 +#define WMAC0_HWSCH_R0_FILTER_LUT_DATA__SOFT_FILTER_VALUE___S 17 +#define WMAC0_HWSCH_R0_FILTER_LUT_DATA__ACCESS_TYPE___M 0x00010000 +#define WMAC0_HWSCH_R0_FILTER_LUT_DATA__ACCESS_TYPE___S 16 +#define WMAC0_HWSCH_R0_FILTER_LUT_DATA__FILTER_ID___M 0x0000FFFF +#define WMAC0_HWSCH_R0_FILTER_LUT_DATA__FILTER_ID___S 0 +#define WMAC0_HWSCH_R0_FILTER_LUT_DATA___M 0x0007FFFF +#define WMAC0_HWSCH_R0_FILTER_LUT_DATA___S 0 + +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n(n) (0x00AAC704+0x4*(n)) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n_nMIN 0 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n_nMAX 17 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n_ELEM 18 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n___POR 0x00000000 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n__PREFERRED_AC_EXCLUSION_BITMAP___POR 0x0 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n__VALID___POR 0x0 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n__PREFERRED_AC_EXCLUSION_BITMAP___S 1 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n__VALID___M 0x00000001 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n__VALID___S 0 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n___M 0x0000001F +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_n___S 0 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_0 (0x00AAC704) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_0__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_0__PREFERRED_AC_EXCLUSION_BITMAP___S 1 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_0__VALID___M 0x00000001 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_0__VALID___S 0 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_1 (0x00AAC708) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_1__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_1__PREFERRED_AC_EXCLUSION_BITMAP___S 1 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_1__VALID___M 0x00000001 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_1__VALID___S 0 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_2 (0x00AAC70C) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_2___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_2__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_2__PREFERRED_AC_EXCLUSION_BITMAP___S 1 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_2__VALID___M 0x00000001 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_2__VALID___S 0 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_3 (0x00AAC710) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_3___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_3__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_3__PREFERRED_AC_EXCLUSION_BITMAP___S 1 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_3__VALID___M 0x00000001 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_3__VALID___S 0 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_4 (0x00AAC714) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_4___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_4__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_4__PREFERRED_AC_EXCLUSION_BITMAP___S 1 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_4__VALID___M 0x00000001 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_4__VALID___S 0 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_5 (0x00AAC718) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_5___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_5__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_5__PREFERRED_AC_EXCLUSION_BITMAP___S 1 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_5__VALID___M 0x00000001 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_5__VALID___S 0 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_6 (0x00AAC71C) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_6___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_6__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_6__PREFERRED_AC_EXCLUSION_BITMAP___S 1 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_6__VALID___M 0x00000001 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_6__VALID___S 0 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_7 (0x00AAC720) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_7___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_7__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_7__PREFERRED_AC_EXCLUSION_BITMAP___S 1 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_7__VALID___M 0x00000001 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_7__VALID___S 0 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_8 (0x00AAC724) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_8___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_8__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_8__PREFERRED_AC_EXCLUSION_BITMAP___S 1 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_8__VALID___M 0x00000001 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_8__VALID___S 0 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_9 (0x00AAC728) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_9___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_9__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_9__PREFERRED_AC_EXCLUSION_BITMAP___S 1 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_9__VALID___M 0x00000001 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_9__VALID___S 0 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_10 (0x00AAC72C) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_10___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_10__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_10__PREFERRED_AC_EXCLUSION_BITMAP___S 1 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_10__VALID___M 0x00000001 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_10__VALID___S 0 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_11 (0x00AAC730) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_11___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_11__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_11__PREFERRED_AC_EXCLUSION_BITMAP___S 1 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_11__VALID___M 0x00000001 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_11__VALID___S 0 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_12 (0x00AAC734) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_12___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_12__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_12__PREFERRED_AC_EXCLUSION_BITMAP___S 1 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_12__VALID___M 0x00000001 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_12__VALID___S 0 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_13 (0x00AAC738) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_13___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_13__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_13__PREFERRED_AC_EXCLUSION_BITMAP___S 1 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_13__VALID___M 0x00000001 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_13__VALID___S 0 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_14 (0x00AAC73C) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_14___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_14__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_14__PREFERRED_AC_EXCLUSION_BITMAP___S 1 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_14__VALID___M 0x00000001 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_14__VALID___S 0 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_15 (0x00AAC740) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_15___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_15__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_15__PREFERRED_AC_EXCLUSION_BITMAP___S 1 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_15__VALID___M 0x00000001 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_15__VALID___S 0 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_16 (0x00AAC744) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_16___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_16__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_16__PREFERRED_AC_EXCLUSION_BITMAP___S 1 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_16__VALID___M 0x00000001 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_16__VALID___S 0 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_17 (0x00AAC748) +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_17___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_17__PREFERRED_AC_EXCLUSION_BITMAP___M 0x0000001E +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_17__PREFERRED_AC_EXCLUSION_BITMAP___S 1 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_17__VALID___M 0x00000001 +#define WMAC0_HWSCH_R0_PREFERRED_AC_EXCL_BMAP_17__VALID___S 0 + +#define WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG (0x00AAC74C) +#define WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG___POR 0x00000010 +#define WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG__DISABLE_ECC_CHECK___POR 0x1 +#define WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG__DISABLE_HDR_TAG_AND_LEN_CHECK___POR 0x0 +#define WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG__DISABLE_HDR_LEN_CHECK___POR 0x0 +#define WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG__DISABLE_HDR_TAG_OO_XML_CHECK___POR 0x0 +#define WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG__DISABLE_ZERO_HDR_CHECK___POR 0x0 +#define WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG__DISABLE_ECC_CHECK___M 0x00000010 +#define WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG__DISABLE_ECC_CHECK___S 4 +#define WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG__DISABLE_HDR_TAG_AND_LEN_CHECK___M 0x00000008 +#define WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG__DISABLE_HDR_TAG_AND_LEN_CHECK___S 3 +#define WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG__DISABLE_HDR_LEN_CHECK___M 0x00000004 +#define WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG__DISABLE_HDR_LEN_CHECK___S 2 +#define WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG__DISABLE_HDR_TAG_OO_XML_CHECK___M 0x00000002 +#define WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG__DISABLE_HDR_TAG_OO_XML_CHECK___S 1 +#define WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG__DISABLE_ZERO_HDR_CHECK___M 0x00000001 +#define WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG__DISABLE_ZERO_HDR_CHECK___S 0 +#define WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG___M 0x0000001F +#define WMAC0_HWSCH_R0_SCH_TLV_ERR_CHK_CFG___S 0 + +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL (0x00AAC750) +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL___POR 0x0083C600 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__UPLOAD_SRP_INFO_EN___POR 0x0 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__UPLOAD_OBSS_SR_INFO_EN___POR 0x0 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__ENABLE_OBSS_PD_LUT_FOR_NEW_SR_MODES___POR 0x0 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__OBSS_SR_INFO_TXOP_CHECK___POR 0x0 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__CLEAR_SRG_OBSS_PD_PWR_RESTR_PERIOD___POR 0x0 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__CLEAR_NON_SRG_OBSS_PD_PWR_RESTR_PERIOD___POR 0x0 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__OBSS_CCA_INDEX___POR 0x08 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__OBSS_PD_PWR_RESTR_ON_TX_OFDMA_CS_REQ___POR 0x0 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__SR_OPPORT_CCA_EN_MASK___POR 0x3C +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__SR_OPPORT_CCA_MUX_SEL_MASK___POR 0x3 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__NO_CLEAR_RSSI_ON_TX_WHEN_OBSS_HIGH___POR 0x0 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__STALL_FLUSH_OR_IGNORE_SRP_FOR_BKOF___POR 0x0 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__ENABLE_SRP___POR 0x0 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__SEL_SRP_PWR_THR_REG___POR 0x0 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__STALL_FLUSH_OR_IGNORE_OBSS_PD_FOR_BKOF___POR 0x0 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__ENABLE_OBSS_PD___POR 0x0 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__SEL_OBSS_RSSI_THR_REG___POR 0x0 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__UPLOAD_SRP_INFO_EN___M 0x80000000 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__UPLOAD_SRP_INFO_EN___S 31 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__UPLOAD_OBSS_SR_INFO_EN___M 0x40000000 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__UPLOAD_OBSS_SR_INFO_EN___S 30 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__ENABLE_OBSS_PD_LUT_FOR_NEW_SR_MODES___M 0x20000000 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__ENABLE_OBSS_PD_LUT_FOR_NEW_SR_MODES___S 29 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__OBSS_SR_INFO_TXOP_CHECK___M 0x10000000 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__OBSS_SR_INFO_TXOP_CHECK___S 28 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__CLEAR_SRG_OBSS_PD_PWR_RESTR_PERIOD___M 0x08000000 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__CLEAR_SRG_OBSS_PD_PWR_RESTR_PERIOD___S 27 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__CLEAR_NON_SRG_OBSS_PD_PWR_RESTR_PERIOD___M 0x04000000 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__CLEAR_NON_SRG_OBSS_PD_PWR_RESTR_PERIOD___S 26 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__OBSS_CCA_INDEX___M 0x03F00000 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__OBSS_CCA_INDEX___S 20 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__OBSS_PD_PWR_RESTR_ON_TX_OFDMA_CS_REQ___M 0x00080000 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__OBSS_PD_PWR_RESTR_ON_TX_OFDMA_CS_REQ___S 19 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__SR_OPPORT_CCA_EN_MASK___M 0x0007F000 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__SR_OPPORT_CCA_EN_MASK___S 12 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__SR_OPPORT_CCA_MUX_SEL_MASK___M 0x00000E00 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__SR_OPPORT_CCA_MUX_SEL_MASK___S 9 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__NO_CLEAR_RSSI_ON_TX_WHEN_OBSS_HIGH___M 0x00000100 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__NO_CLEAR_RSSI_ON_TX_WHEN_OBSS_HIGH___S 8 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__STALL_FLUSH_OR_IGNORE_SRP_FOR_BKOF___M 0x000000C0 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__STALL_FLUSH_OR_IGNORE_SRP_FOR_BKOF___S 6 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__ENABLE_SRP___M 0x00000020 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__ENABLE_SRP___S 5 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__SEL_SRP_PWR_THR_REG___M 0x00000010 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__SEL_SRP_PWR_THR_REG___S 4 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__STALL_FLUSH_OR_IGNORE_OBSS_PD_FOR_BKOF___M 0x0000000C +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__STALL_FLUSH_OR_IGNORE_OBSS_PD_FOR_BKOF___S 2 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__ENABLE_OBSS_PD___M 0x00000002 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__ENABLE_OBSS_PD___S 1 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__SEL_OBSS_RSSI_THR_REG___M 0x00000001 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL__SEL_OBSS_RSSI_THR_REG___S 0 +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_OBSS_CCA_CONTROL___S 0 + +#define WMAC0_HWSCH_R0_SRP_RESTORE_BACKOFF_ENABLE (0x00AAC754) +#define WMAC0_HWSCH_R0_SRP_RESTORE_BACKOFF_ENABLE___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SRP_RESTORE_BACKOFF_ENABLE___POR 0x00000000 +#define WMAC0_HWSCH_R0_SRP_RESTORE_BACKOFF_ENABLE__SRP_RESTORE_BACKOFF_EN___POR 0x00000 +#define WMAC0_HWSCH_R0_SRP_RESTORE_BACKOFF_ENABLE__SRP_RESTORE_BACKOFF_EN___M 0x0003FFFF +#define WMAC0_HWSCH_R0_SRP_RESTORE_BACKOFF_ENABLE__SRP_RESTORE_BACKOFF_EN___S 0 +#define WMAC0_HWSCH_R0_SRP_RESTORE_BACKOFF_ENABLE___M 0x0003FFFF +#define WMAC0_HWSCH_R0_SRP_RESTORE_BACKOFF_ENABLE___S 0 + +#define WMAC0_HWSCH_R0_SRP_REDO_AIFS_ENABLE (0x00AAC758) +#define WMAC0_HWSCH_R0_SRP_REDO_AIFS_ENABLE___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SRP_REDO_AIFS_ENABLE___POR 0x00000000 +#define WMAC0_HWSCH_R0_SRP_REDO_AIFS_ENABLE__SRP_REDO_AIFS_EN___POR 0x00000 +#define WMAC0_HWSCH_R0_SRP_REDO_AIFS_ENABLE__SRP_REDO_AIFS_EN___M 0x0003FFFF +#define WMAC0_HWSCH_R0_SRP_REDO_AIFS_ENABLE__SRP_REDO_AIFS_EN___S 0 +#define WMAC0_HWSCH_R0_SRP_REDO_AIFS_ENABLE___M 0x0003FFFF +#define WMAC0_HWSCH_R0_SRP_REDO_AIFS_ENABLE___S 0 + +#define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION (0x00AAC75C) +#define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION___POR 0x00800080 +#define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION__ENABLE_LATENCY_MITIGATION___POR 0x0 +#define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION__LATENCY_DEACTIVATE_THRESHOLD___POR 0x0100 +#define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION__LATENCY_ACTIVATE_THRESHOLD___POR 0x0080 +#define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION__ENABLE_LATENCY_MITIGATION___M 0x80000000 +#define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION__ENABLE_LATENCY_MITIGATION___S 31 +#define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION__LATENCY_DEACTIVATE_THRESHOLD___M 0x3FFF8000 +#define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION__LATENCY_DEACTIVATE_THRESHOLD___S 15 +#define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION__LATENCY_ACTIVATE_THRESHOLD___M 0x00007FFF +#define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION__LATENCY_ACTIVATE_THRESHOLD___S 0 +#define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION___M 0xBFFFFFFF +#define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_MITIGATION___S 0 + +#define WMAC0_HWSCH_R0_STATUS_RING_SW_LATENCY_STATUS (0x00AAC760) +#define WMAC0_HWSCH_R0_STATUS_RING_SW_LATENCY_STATUS___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R0_STATUS_RING_SW_LATENCY_STATUS___POR 0x00000000 +#define WMAC0_HWSCH_R0_STATUS_RING_SW_LATENCY_STATUS__FES_STATUS_IGNORED___POR 0x0 +#define WMAC0_HWSCH_R0_STATUS_RING_SW_LATENCY_STATUS__FES_STATUS_RING_LAT_THRS_REACHED___POR 0x0 +#define WMAC0_HWSCH_R0_STATUS_RING_SW_LATENCY_STATUS__FES_STATUS_IGNORED___M 0x00000002 +#define WMAC0_HWSCH_R0_STATUS_RING_SW_LATENCY_STATUS__FES_STATUS_IGNORED___S 1 +#define WMAC0_HWSCH_R0_STATUS_RING_SW_LATENCY_STATUS__FES_STATUS_RING_LAT_THRS_REACHED___M 0x00000001 +#define WMAC0_HWSCH_R0_STATUS_RING_SW_LATENCY_STATUS__FES_STATUS_RING_LAT_THRS_REACHED___S 0 +#define WMAC0_HWSCH_R0_STATUS_RING_SW_LATENCY_STATUS___M 0x00000003 +#define WMAC0_HWSCH_R0_STATUS_RING_SW_LATENCY_STATUS___S 0 + +#define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER (0x00AAC764) +#define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER___POR 0x00000000 +#define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER__IGNORE_TLV_COUNT___POR 0x0000 +#define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER__EXIT_HYSTERISIS_COUNT___POR 0x00 +#define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER__IN_HYSTERISIS_COUNT___POR 0x00 +#define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER__IGNORE_TLV_COUNT___M 0xFFFF0000 +#define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER__IGNORE_TLV_COUNT___S 16 +#define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER__EXIT_HYSTERISIS_COUNT___M 0x0000FF00 +#define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER__EXIT_HYSTERISIS_COUNT___S 8 +#define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER__IN_HYSTERISIS_COUNT___M 0x000000FF +#define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER__IN_HYSTERISIS_COUNT___S 0 +#define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER___M 0xFFFFFFFF +#define WMAC0_HWSCH_R0_FES_STATUS_RING_SW_LATENCY_COUNTER___S 0 + +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CTRL (0x00AAC768) +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CTRL___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CTRL___POR 0x00000000 +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CTRL__MSG_ENABLE___POR 0x0 +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CTRL__MSG_ENABLE___M 0x00000001 +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CTRL__MSG_ENABLE___S 0 +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CTRL___M 0x00000001 +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CTRL___S 0 + +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n(n) (0x00AAC76C+0x4*(n)) +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n_nMIN 0 +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n_nMAX 3 +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n_ELEM 4 +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n___POR 0x00000000 +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n__UCODE_MSG___POR 0x00 +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n__FLUSH_CODE___POR 0x00 +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n__UCODE_MSG___M 0x00003F00 +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n__UCODE_MSG___S 8 +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n__FLUSH_CODE___M 0x000000FF +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n__FLUSH_CODE___S 0 +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n___M 0x00003FFF +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_n___S 0 +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_0 (0x00AAC76C) +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_0__UCODE_MSG___M 0x00003F00 +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_0__UCODE_MSG___S 8 +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_0__FLUSH_CODE___M 0x000000FF +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_0__FLUSH_CODE___S 0 +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_1 (0x00AAC770) +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_1__UCODE_MSG___M 0x00003F00 +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_1__UCODE_MSG___S 8 +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_1__FLUSH_CODE___M 0x000000FF +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_1__FLUSH_CODE___S 0 +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_2 (0x00AAC774) +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_2___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_2__UCODE_MSG___M 0x00003F00 +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_2__UCODE_MSG___S 8 +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_2__FLUSH_CODE___M 0x000000FF +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_2__FLUSH_CODE___S 0 +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_3 (0x00AAC778) +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_3___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_3__UCODE_MSG___M 0x00003F00 +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_3__UCODE_MSG___S 8 +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_3__FLUSH_CODE___M 0x000000FF +#define WMAC0_HWSCH_R0_FLUSH_TLV_MSG_CFG_3__FLUSH_CODE___S 0 + +#define WMAC0_HWSCH_R0_UORA_TRIGGER_TYPE_BITMAP (0x00AAC77C) +#define WMAC0_HWSCH_R0_UORA_TRIGGER_TYPE_BITMAP___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_UORA_TRIGGER_TYPE_BITMAP___POR 0x00010001 +#define WMAC0_HWSCH_R0_UORA_TRIGGER_TYPE_BITMAP__UORA_TRIGGER_UNASSOC_WILDCARD_RESPONSE_ENABLE___POR 0x1 +#define WMAC0_HWSCH_R0_UORA_TRIGGER_TYPE_BITMAP__UORA_TRIGGER_WILDCARD_RESPONSE_ENABLE_BITMAP___POR 0x0001 +#define WMAC0_HWSCH_R0_UORA_TRIGGER_TYPE_BITMAP__UORA_TRIGGER_UNASSOC_WILDCARD_RESPONSE_ENABLE___M 0x00010000 +#define WMAC0_HWSCH_R0_UORA_TRIGGER_TYPE_BITMAP__UORA_TRIGGER_UNASSOC_WILDCARD_RESPONSE_ENABLE___S 16 +#define WMAC0_HWSCH_R0_UORA_TRIGGER_TYPE_BITMAP__UORA_TRIGGER_WILDCARD_RESPONSE_ENABLE_BITMAP___M 0x0000FFFF +#define WMAC0_HWSCH_R0_UORA_TRIGGER_TYPE_BITMAP__UORA_TRIGGER_WILDCARD_RESPONSE_ENABLE_BITMAP___S 0 +#define WMAC0_HWSCH_R0_UORA_TRIGGER_TYPE_BITMAP___M 0x0001FFFF +#define WMAC0_HWSCH_R0_UORA_TRIGGER_TYPE_BITMAP___S 0 + +#define WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT (0x00AAC780) +#define WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT___POR 0xFF17FFFF +#define WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__SRP_INFO_TLV_TIMEOUT___POR 0xFF +#define WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__SET_SRP_INFO_TIMEOUT_STATUS___POR 0x1 +#define WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__CLEAR_SRP_OPPORT_ON_TIMEOUT___POR 0x0 +#define WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__CLEAR_SRG_OPPORT_ON_TIMEOUT___POR 0x1 +#define WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__CLEAR_NON_SRG_OPPORT_ON_TIMEOUT___POR 0x1 +#define WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__ENABLE_SR_TIMEOUT_STATUS___POR 0x1 +#define WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__SR_OPPORT_TIMEOUT___POR 0xFFFF +#define WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__SRP_INFO_TLV_TIMEOUT___M 0xFF000000 +#define WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__SRP_INFO_TLV_TIMEOUT___S 24 +#define WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__SET_SRP_INFO_TIMEOUT_STATUS___M 0x00100000 +#define WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__SET_SRP_INFO_TIMEOUT_STATUS___S 20 +#define WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__CLEAR_SRP_OPPORT_ON_TIMEOUT___M 0x00080000 +#define WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__CLEAR_SRP_OPPORT_ON_TIMEOUT___S 19 +#define WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__CLEAR_SRG_OPPORT_ON_TIMEOUT___M 0x00040000 +#define WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__CLEAR_SRG_OPPORT_ON_TIMEOUT___S 18 +#define WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__CLEAR_NON_SRG_OPPORT_ON_TIMEOUT___M 0x00020000 +#define WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__CLEAR_NON_SRG_OPPORT_ON_TIMEOUT___S 17 +#define WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__ENABLE_SR_TIMEOUT_STATUS___M 0x00010000 +#define WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__ENABLE_SR_TIMEOUT_STATUS___S 16 +#define WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__SR_OPPORT_TIMEOUT___M 0x0000FFFF +#define WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT__SR_OPPORT_TIMEOUT___S 0 +#define WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT___M 0xFF1FFFFF +#define WMAC0_HWSCH_R0_SR_OPPORT_TIMEOUT___S 0 + +#define WMAC0_HWSCH_R0_SR_ERR_STATUS (0x00AAC784) +#define WMAC0_HWSCH_R0_SR_ERR_STATUS___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_SR_ERR_STATUS___POR 0x00000000 +#define WMAC0_HWSCH_R0_SR_ERR_STATUS__SRP_INFO_TLV_TIMEOUT_STATUS_P___POR 0x0 +#define WMAC0_HWSCH_R0_SR_ERR_STATUS__SR_OPPORT_TIMEOUT_US_STATUS_SRP_P___POR 0x0 +#define WMAC0_HWSCH_R0_SR_ERR_STATUS__SR_OPPORT_TIMEOUT_US_STATUS_SRG_P___POR 0x0 +#define WMAC0_HWSCH_R0_SR_ERR_STATUS__SR_OPPORT_TIMEOUT_US_STATUS_NON_SRG_P___POR 0x0 +#define WMAC0_HWSCH_R0_SR_ERR_STATUS__SRP_INFO_TLV_TIMEOUT_STATUS_P___M 0x00000008 +#define WMAC0_HWSCH_R0_SR_ERR_STATUS__SRP_INFO_TLV_TIMEOUT_STATUS_P___S 3 +#define WMAC0_HWSCH_R0_SR_ERR_STATUS__SR_OPPORT_TIMEOUT_US_STATUS_SRP_P___M 0x00000004 +#define WMAC0_HWSCH_R0_SR_ERR_STATUS__SR_OPPORT_TIMEOUT_US_STATUS_SRP_P___S 2 +#define WMAC0_HWSCH_R0_SR_ERR_STATUS__SR_OPPORT_TIMEOUT_US_STATUS_SRG_P___M 0x00000002 +#define WMAC0_HWSCH_R0_SR_ERR_STATUS__SR_OPPORT_TIMEOUT_US_STATUS_SRG_P___S 1 +#define WMAC0_HWSCH_R0_SR_ERR_STATUS__SR_OPPORT_TIMEOUT_US_STATUS_NON_SRG_P___M 0x00000001 +#define WMAC0_HWSCH_R0_SR_ERR_STATUS__SR_OPPORT_TIMEOUT_US_STATUS_NON_SRG_P___S 0 +#define WMAC0_HWSCH_R0_SR_ERR_STATUS___M 0x0000000F +#define WMAC0_HWSCH_R0_SR_ERR_STATUS___S 0 + +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0 (0x00AAC788) +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0___POR 0x000FFFFF +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING19___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING18___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING17___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING16___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING15___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING14___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING13___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING12___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING11___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING10___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING9___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING8___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING7___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING6___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING5___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING4___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING3___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING2___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING1___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING0___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING19___M 0x00080000 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING19___S 19 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING18___M 0x00040000 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING18___S 18 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING17___M 0x00020000 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING17___S 17 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING16___M 0x00010000 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING16___S 16 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING15___M 0x00008000 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING15___S 15 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING14___M 0x00004000 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING14___S 14 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING13___M 0x00002000 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING13___S 13 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING12___M 0x00001000 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING12___S 12 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING11___M 0x00000800 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING11___S 11 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING10___M 0x00000400 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING10___S 10 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING9___M 0x00000200 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING9___S 9 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING8___M 0x00000100 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING8___S 8 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING7___M 0x00000080 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING7___S 7 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING6___M 0x00000040 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING6___S 6 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING5___M 0x00000020 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING5___S 5 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING4___M 0x00000010 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING4___S 4 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING3___M 0x00000008 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING3___S 3 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING2___M 0x00000004 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING2___S 2 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING1___M 0x00000002 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING1___S 1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING0___M 0x00000001 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0__CMD_RING0___S 0 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0___M 0x000FFFFF +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_0___S 0 + +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1 (0x00AAC78C) +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1___POR 0x00007FFF +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__FES_STAT_BUF_EGRESS___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__FES_STAT_BUF_INGRESS___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__CCA_WATCHDOG___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__SRNG_SCH_CTRL___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__SFM_APB_CTRL___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__SFM_WRITE_CTRL___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__SFM_READ_CTRL___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__FLUSH_CTRL___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__STATUS_CTRL_FLUSH_SM___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__STATUS_CTRL_SCH_SM___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__STATUS_CTRL_TQM_SM___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__STATUS_CTRL_FES_SM___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__FES_SETUP___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__MTU_WRAP___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__COEX_CTRL___POR 0x1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__FES_STAT_BUF_EGRESS___M 0x00004000 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__FES_STAT_BUF_EGRESS___S 14 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__FES_STAT_BUF_INGRESS___M 0x00002000 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__FES_STAT_BUF_INGRESS___S 13 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__CCA_WATCHDOG___M 0x00001000 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__CCA_WATCHDOG___S 12 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__SRNG_SCH_CTRL___M 0x00000800 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__SRNG_SCH_CTRL___S 11 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__SFM_APB_CTRL___M 0x00000400 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__SFM_APB_CTRL___S 10 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__SFM_WRITE_CTRL___M 0x00000200 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__SFM_WRITE_CTRL___S 9 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__SFM_READ_CTRL___M 0x00000100 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__SFM_READ_CTRL___S 8 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__FLUSH_CTRL___M 0x00000080 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__FLUSH_CTRL___S 7 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__STATUS_CTRL_FLUSH_SM___M 0x00000040 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__STATUS_CTRL_FLUSH_SM___S 6 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__STATUS_CTRL_SCH_SM___M 0x00000020 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__STATUS_CTRL_SCH_SM___S 5 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__STATUS_CTRL_TQM_SM___M 0x00000010 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__STATUS_CTRL_TQM_SM___S 4 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__STATUS_CTRL_FES_SM___M 0x00000008 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__STATUS_CTRL_FES_SM___S 3 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__FES_SETUP___M 0x00000004 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__FES_SETUP___S 2 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__MTU_WRAP___M 0x00000002 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__MTU_WRAP___S 1 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__COEX_CTRL___M 0x00000001 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1__COEX_CTRL___S 0 +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1___M 0x00007FFF +#define WMAC0_HWSCH_R0_ERROR_ASSERTION_EVT_EN_IX_1___S 0 + +#define WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_0 (0x00AAC790) +#define WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_0___POR 0x00000000 +#define WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_0__POSTRX_DMZ_WIN_LIMIT___POR 0x00000 +#define WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_0__POSTRX_DMZ_WIN_LIMIT___M 0x0003FFFF +#define WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_0__POSTRX_DMZ_WIN_LIMIT___S 0 +#define WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_0___M 0x0003FFFF +#define WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_0___S 0 + +#define WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_1 (0x00AAC794) +#define WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_1___POR 0x00000000 +#define WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_1__POSTRX_DMZ_RING_SELECT___POR 0x00000 +#define WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_1__POSTRX_DMZ_RING_SELECT___M 0x0003FFFF +#define WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_1__POSTRX_DMZ_RING_SELECT___S 0 +#define WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_1___M 0x0003FFFF +#define WMAC0_HWSCH_R0_POST_RX_FES_DMZ_TIMER_CFG_IX_1___S 0 + +#define WMAC0_HWSCH_R0_ILP_CTRL_IX_0 (0x00AAC798) +#define WMAC0_HWSCH_R0_ILP_CTRL_IX_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_ILP_CTRL_IX_0___POR 0x00000000 +#define WMAC0_HWSCH_R0_ILP_CTRL_IX_0__L0_REQ_RX_ABORT_OFFSET___POR 0x00 +#define WMAC0_HWSCH_R0_ILP_CTRL_IX_0__L0_REQ_OFFSET___POR 0x00 +#define WMAC0_HWSCH_R0_ILP_CTRL_IX_0__L0_REQ_RX_ABORT_OFFSET___M 0x0000FF00 +#define WMAC0_HWSCH_R0_ILP_CTRL_IX_0__L0_REQ_RX_ABORT_OFFSET___S 8 +#define WMAC0_HWSCH_R0_ILP_CTRL_IX_0__L0_REQ_OFFSET___M 0x000000FF +#define WMAC0_HWSCH_R0_ILP_CTRL_IX_0__L0_REQ_OFFSET___S 0 +#define WMAC0_HWSCH_R0_ILP_CTRL_IX_0___M 0x0000FFFF +#define WMAC0_HWSCH_R0_ILP_CTRL_IX_0___S 0 + +#define WMAC0_HWSCH_R0_ILP_CTRL_IX_1 (0x00AAC79C) +#define WMAC0_HWSCH_R0_ILP_CTRL_IX_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_ILP_CTRL_IX_1___POR 0x00000000 +#define WMAC0_HWSCH_R0_ILP_CTRL_IX_1__L0_REQ_RX_ABORT_OFFSET_EN___POR 0x00000 +#define WMAC0_HWSCH_R0_ILP_CTRL_IX_1__L0_REQ_RX_ABORT_OFFSET_EN___M 0x0003FFFF +#define WMAC0_HWSCH_R0_ILP_CTRL_IX_1__L0_REQ_RX_ABORT_OFFSET_EN___S 0 +#define WMAC0_HWSCH_R0_ILP_CTRL_IX_1___M 0x0003FFFF +#define WMAC0_HWSCH_R0_ILP_CTRL_IX_1___S 0 + +#define WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL (0x00AAC7A0) +#define WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL___POR 0x00000006 +#define WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL__DISABLE_AUTO_FLUSH_BASIC_TRIGGER_TID_AGGR_0___POR 0x1 +#define WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL__DISABLE_AUTO_FLUSH_BASIC_TRIGGER___POR 0x1 +#define WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL__ENABLE_AUTO_FLUSH_ALL_11AX_RESP___POR 0x0 +#define WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL__DISABLE_AUTO_FLUSH_BASIC_TRIGGER_TID_AGGR_0___M 0x00000004 +#define WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL__DISABLE_AUTO_FLUSH_BASIC_TRIGGER_TID_AGGR_0___S 2 +#define WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL__DISABLE_AUTO_FLUSH_BASIC_TRIGGER___M 0x00000002 +#define WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL__DISABLE_AUTO_FLUSH_BASIC_TRIGGER___S 1 +#define WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL__ENABLE_AUTO_FLUSH_ALL_11AX_RESP___M 0x00000001 +#define WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL__ENABLE_AUTO_FLUSH_ALL_11AX_RESP___S 0 +#define WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL___M 0x00000007 +#define WMAC0_HWSCH_R0_AUTO_FLUSH_CTRL___S 0 + +#define WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_0 (0x00AAC7A4) +#define WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_0___POR 0x00000000 +#define WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_0__EN___POR 0x00000 +#define WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_0__EN___M 0x0003FFFF +#define WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_0__EN___S 0 +#define WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_0___M 0x0003FFFF +#define WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_0___S 0 + +#define WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_1 (0x00AAC7A8) +#define WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_1___POR 0x00000000 +#define WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_1__DIS___POR 0x00000 +#define WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_1__DIS___M 0x0003FFFF +#define WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_1__DIS___S 0 +#define WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_1___M 0x0003FFFF +#define WMAC0_HWSCH_R0_ILP_TRIGGER_MATCH_BITMAP_OVERRIDE_IX_1___S 0 + +#define WMAC0_HWSCH_R1_LFSR_DATA_1_0 (0x00AAE000) +#define WMAC0_HWSCH_R1_LFSR_DATA_1_0___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R1_LFSR_DATA_1_0___POR 0x00000000 +#define WMAC0_HWSCH_R1_LFSR_DATA_1_0__LFSR_DATA_1___POR 0x0000 +#define WMAC0_HWSCH_R1_LFSR_DATA_1_0__LFSR_DATA_0___POR 0x0000 +#define WMAC0_HWSCH_R1_LFSR_DATA_1_0__LFSR_DATA_1___M 0xFFFF0000 +#define WMAC0_HWSCH_R1_LFSR_DATA_1_0__LFSR_DATA_1___S 16 +#define WMAC0_HWSCH_R1_LFSR_DATA_1_0__LFSR_DATA_0___M 0x0000FFFF +#define WMAC0_HWSCH_R1_LFSR_DATA_1_0__LFSR_DATA_0___S 0 +#define WMAC0_HWSCH_R1_LFSR_DATA_1_0___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_LFSR_DATA_1_0___S 0 + +#define WMAC0_HWSCH_R1_LFSR_DATA_3_2 (0x00AAE004) +#define WMAC0_HWSCH_R1_LFSR_DATA_3_2___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R1_LFSR_DATA_3_2___POR 0x00000000 +#define WMAC0_HWSCH_R1_LFSR_DATA_3_2__LFSR_DATA_3___POR 0x0000 +#define WMAC0_HWSCH_R1_LFSR_DATA_3_2__LFSR_DATA_2___POR 0x0000 +#define WMAC0_HWSCH_R1_LFSR_DATA_3_2__LFSR_DATA_3___M 0xFFFF0000 +#define WMAC0_HWSCH_R1_LFSR_DATA_3_2__LFSR_DATA_3___S 16 +#define WMAC0_HWSCH_R1_LFSR_DATA_3_2__LFSR_DATA_2___M 0x0000FFFF +#define WMAC0_HWSCH_R1_LFSR_DATA_3_2__LFSR_DATA_2___S 0 +#define WMAC0_HWSCH_R1_LFSR_DATA_3_2___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_LFSR_DATA_3_2___S 0 + +#define WMAC0_HWSCH_R1_LFSR_DATA_5_4 (0x00AAE008) +#define WMAC0_HWSCH_R1_LFSR_DATA_5_4___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R1_LFSR_DATA_5_4___POR 0x00000000 +#define WMAC0_HWSCH_R1_LFSR_DATA_5_4__LFSR_DATA_5___POR 0x0000 +#define WMAC0_HWSCH_R1_LFSR_DATA_5_4__LFSR_DATA_4___POR 0x0000 +#define WMAC0_HWSCH_R1_LFSR_DATA_5_4__LFSR_DATA_5___M 0xFFFF0000 +#define WMAC0_HWSCH_R1_LFSR_DATA_5_4__LFSR_DATA_5___S 16 +#define WMAC0_HWSCH_R1_LFSR_DATA_5_4__LFSR_DATA_4___M 0x0000FFFF +#define WMAC0_HWSCH_R1_LFSR_DATA_5_4__LFSR_DATA_4___S 0 +#define WMAC0_HWSCH_R1_LFSR_DATA_5_4___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_LFSR_DATA_5_4___S 0 + +#define WMAC0_HWSCH_R1_LFSR_DATA_7_6 (0x00AAE00C) +#define WMAC0_HWSCH_R1_LFSR_DATA_7_6___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R1_LFSR_DATA_7_6___POR 0x00000000 +#define WMAC0_HWSCH_R1_LFSR_DATA_7_6__LFSR_DATA_7___POR 0x0000 +#define WMAC0_HWSCH_R1_LFSR_DATA_7_6__LFSR_DATA_6___POR 0x0000 +#define WMAC0_HWSCH_R1_LFSR_DATA_7_6__LFSR_DATA_7___M 0xFFFF0000 +#define WMAC0_HWSCH_R1_LFSR_DATA_7_6__LFSR_DATA_7___S 16 +#define WMAC0_HWSCH_R1_LFSR_DATA_7_6__LFSR_DATA_6___M 0x0000FFFF +#define WMAC0_HWSCH_R1_LFSR_DATA_7_6__LFSR_DATA_6___S 0 +#define WMAC0_HWSCH_R1_LFSR_DATA_7_6___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_LFSR_DATA_7_6___S 0 + +#define WMAC0_HWSCH_R1_LFSR_DATA_9_8 (0x00AAE010) +#define WMAC0_HWSCH_R1_LFSR_DATA_9_8___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R1_LFSR_DATA_9_8___POR 0x00000000 +#define WMAC0_HWSCH_R1_LFSR_DATA_9_8__LFSR_DATA_9___POR 0x0000 +#define WMAC0_HWSCH_R1_LFSR_DATA_9_8__LFSR_DATA_8___POR 0x0000 +#define WMAC0_HWSCH_R1_LFSR_DATA_9_8__LFSR_DATA_9___M 0xFFFF0000 +#define WMAC0_HWSCH_R1_LFSR_DATA_9_8__LFSR_DATA_9___S 16 +#define WMAC0_HWSCH_R1_LFSR_DATA_9_8__LFSR_DATA_8___M 0x0000FFFF +#define WMAC0_HWSCH_R1_LFSR_DATA_9_8__LFSR_DATA_8___S 0 +#define WMAC0_HWSCH_R1_LFSR_DATA_9_8___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_LFSR_DATA_9_8___S 0 + +#define WMAC0_HWSCH_R1_LFSR_DATA_11_10 (0x00AAE014) +#define WMAC0_HWSCH_R1_LFSR_DATA_11_10___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R1_LFSR_DATA_11_10___POR 0x00000000 +#define WMAC0_HWSCH_R1_LFSR_DATA_11_10__LFSR_DATA_11___POR 0x0000 +#define WMAC0_HWSCH_R1_LFSR_DATA_11_10__LFSR_DATA_10___POR 0x0000 +#define WMAC0_HWSCH_R1_LFSR_DATA_11_10__LFSR_DATA_11___M 0xFFFF0000 +#define WMAC0_HWSCH_R1_LFSR_DATA_11_10__LFSR_DATA_11___S 16 +#define WMAC0_HWSCH_R1_LFSR_DATA_11_10__LFSR_DATA_10___M 0x0000FFFF +#define WMAC0_HWSCH_R1_LFSR_DATA_11_10__LFSR_DATA_10___S 0 +#define WMAC0_HWSCH_R1_LFSR_DATA_11_10___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_LFSR_DATA_11_10___S 0 + +#define WMAC0_HWSCH_R1_LFSR_DATA_13_12 (0x00AAE018) +#define WMAC0_HWSCH_R1_LFSR_DATA_13_12___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R1_LFSR_DATA_13_12___POR 0x00000000 +#define WMAC0_HWSCH_R1_LFSR_DATA_13_12__LFSR_DATA_13___POR 0x0000 +#define WMAC0_HWSCH_R1_LFSR_DATA_13_12__LFSR_DATA_12___POR 0x0000 +#define WMAC0_HWSCH_R1_LFSR_DATA_13_12__LFSR_DATA_13___M 0xFFFF0000 +#define WMAC0_HWSCH_R1_LFSR_DATA_13_12__LFSR_DATA_13___S 16 +#define WMAC0_HWSCH_R1_LFSR_DATA_13_12__LFSR_DATA_12___M 0x0000FFFF +#define WMAC0_HWSCH_R1_LFSR_DATA_13_12__LFSR_DATA_12___S 0 +#define WMAC0_HWSCH_R1_LFSR_DATA_13_12___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_LFSR_DATA_13_12___S 0 + +#define WMAC0_HWSCH_R1_LFSR_DATA_15_14 (0x00AAE01C) +#define WMAC0_HWSCH_R1_LFSR_DATA_15_14___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R1_LFSR_DATA_15_14___POR 0x00000000 +#define WMAC0_HWSCH_R1_LFSR_DATA_15_14__LFSR_DATA_15___POR 0x0000 +#define WMAC0_HWSCH_R1_LFSR_DATA_15_14__LFSR_DATA_14___POR 0x0000 +#define WMAC0_HWSCH_R1_LFSR_DATA_15_14__LFSR_DATA_15___M 0xFFFF0000 +#define WMAC0_HWSCH_R1_LFSR_DATA_15_14__LFSR_DATA_15___S 16 +#define WMAC0_HWSCH_R1_LFSR_DATA_15_14__LFSR_DATA_14___M 0x0000FFFF +#define WMAC0_HWSCH_R1_LFSR_DATA_15_14__LFSR_DATA_14___S 0 +#define WMAC0_HWSCH_R1_LFSR_DATA_15_14___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_LFSR_DATA_15_14___S 0 + +#define WMAC0_HWSCH_R1_LFSR_DATA_17_16 (0x00AAE020) +#define WMAC0_HWSCH_R1_LFSR_DATA_17_16___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R1_LFSR_DATA_17_16___POR 0x00000000 +#define WMAC0_HWSCH_R1_LFSR_DATA_17_16__LFSR_DATA_17___POR 0x0000 +#define WMAC0_HWSCH_R1_LFSR_DATA_17_16__LFSR_DATA_16___POR 0x0000 +#define WMAC0_HWSCH_R1_LFSR_DATA_17_16__LFSR_DATA_17___M 0xFFFF0000 +#define WMAC0_HWSCH_R1_LFSR_DATA_17_16__LFSR_DATA_17___S 16 +#define WMAC0_HWSCH_R1_LFSR_DATA_17_16__LFSR_DATA_16___M 0x0000FFFF +#define WMAC0_HWSCH_R1_LFSR_DATA_17_16__LFSR_DATA_16___S 0 +#define WMAC0_HWSCH_R1_LFSR_DATA_17_16___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_LFSR_DATA_17_16___S 0 + +#define WMAC0_HWSCH_R1_MGMT_STATS_CTRL (0x00AAE028) +#define WMAC0_HWSCH_R1_MGMT_STATS_CTRL___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_MGMT_STATS_CTRL___POR 0x0003FFFF +#define WMAC0_HWSCH_R1_MGMT_STATS_CTRL__RESET_ALL___POR 0x0 +#define WMAC0_HWSCH_R1_MGMT_STATS_CTRL__MONITOR_BITMAP___POR 0x3FFFF +#define WMAC0_HWSCH_R1_MGMT_STATS_CTRL__RESET_ALL___M 0x80000000 +#define WMAC0_HWSCH_R1_MGMT_STATS_CTRL__RESET_ALL___S 31 +#define WMAC0_HWSCH_R1_MGMT_STATS_CTRL__MONITOR_BITMAP___M 0x0003FFFF +#define WMAC0_HWSCH_R1_MGMT_STATS_CTRL__MONITOR_BITMAP___S 0 +#define WMAC0_HWSCH_R1_MGMT_STATS_CTRL___M 0x8003FFFF +#define WMAC0_HWSCH_R1_MGMT_STATS_CTRL___S 0 + +#define WMAC0_HWSCH_R1_ACK_PASS_STATS (0x00AAE02C) +#define WMAC0_HWSCH_R1_ACK_PASS_STATS___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_ACK_PASS_STATS___POR 0x00000000 +#define WMAC0_HWSCH_R1_ACK_PASS_STATS__STATS_DIST___POR 0x00000 +#define WMAC0_HWSCH_R1_ACK_PASS_STATS__STATS_COUNT___POR 0x000 +#define WMAC0_HWSCH_R1_ACK_PASS_STATS__STATS_DIST___M 0x3FFFF000 +#define WMAC0_HWSCH_R1_ACK_PASS_STATS__STATS_DIST___S 12 +#define WMAC0_HWSCH_R1_ACK_PASS_STATS__STATS_COUNT___M 0x00000FFF +#define WMAC0_HWSCH_R1_ACK_PASS_STATS__STATS_COUNT___S 0 +#define WMAC0_HWSCH_R1_ACK_PASS_STATS___M 0x3FFFFFFF +#define WMAC0_HWSCH_R1_ACK_PASS_STATS___S 0 + +#define WMAC0_HWSCH_R1_RETRY_STATS (0x00AAE030) +#define WMAC0_HWSCH_R1_RETRY_STATS___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_RETRY_STATS___POR 0x00000000 +#define WMAC0_HWSCH_R1_RETRY_STATS__STATS_DIST___POR 0x00000 +#define WMAC0_HWSCH_R1_RETRY_STATS__STATS_COUNT___POR 0x000 +#define WMAC0_HWSCH_R1_RETRY_STATS__STATS_DIST___M 0x3FFFF000 +#define WMAC0_HWSCH_R1_RETRY_STATS__STATS_DIST___S 12 +#define WMAC0_HWSCH_R1_RETRY_STATS__STATS_COUNT___M 0x00000FFF +#define WMAC0_HWSCH_R1_RETRY_STATS__STATS_COUNT___S 0 +#define WMAC0_HWSCH_R1_RETRY_STATS___M 0x3FFFFFFF +#define WMAC0_HWSCH_R1_RETRY_STATS___S 0 + +#define WMAC0_HWSCH_R1_REQUEUE_STATS (0x00AAE034) +#define WMAC0_HWSCH_R1_REQUEUE_STATS___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_REQUEUE_STATS___POR 0x00000000 +#define WMAC0_HWSCH_R1_REQUEUE_STATS__STATS_DIST___POR 0x00000 +#define WMAC0_HWSCH_R1_REQUEUE_STATS__STATS_COUNT___POR 0x000 +#define WMAC0_HWSCH_R1_REQUEUE_STATS__STATS_DIST___M 0x3FFFF000 +#define WMAC0_HWSCH_R1_REQUEUE_STATS__STATS_DIST___S 12 +#define WMAC0_HWSCH_R1_REQUEUE_STATS__STATS_COUNT___M 0x00000FFF +#define WMAC0_HWSCH_R1_REQUEUE_STATS__STATS_COUNT___S 0 +#define WMAC0_HWSCH_R1_REQUEUE_STATS___M 0x3FFFFFFF +#define WMAC0_HWSCH_R1_REQUEUE_STATS___S 0 + +#define WMAC0_HWSCH_R1_FILTER_STATS (0x00AAE038) +#define WMAC0_HWSCH_R1_FILTER_STATS___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_FILTER_STATS___POR 0x00000000 +#define WMAC0_HWSCH_R1_FILTER_STATS__STATS_DIST___POR 0x00000 +#define WMAC0_HWSCH_R1_FILTER_STATS__STATS_COUNT___POR 0x000 +#define WMAC0_HWSCH_R1_FILTER_STATS__STATS_DIST___M 0x3FFFF000 +#define WMAC0_HWSCH_R1_FILTER_STATS__STATS_DIST___S 12 +#define WMAC0_HWSCH_R1_FILTER_STATS__STATS_COUNT___M 0x00000FFF +#define WMAC0_HWSCH_R1_FILTER_STATS__STATS_COUNT___S 0 +#define WMAC0_HWSCH_R1_FILTER_STATS___M 0x3FFFFFFF +#define WMAC0_HWSCH_R1_FILTER_STATS___S 0 + +#define WMAC0_HWSCH_R1_BSPLIT_STATS (0x00AAE03C) +#define WMAC0_HWSCH_R1_BSPLIT_STATS___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_BSPLIT_STATS___POR 0x00000000 +#define WMAC0_HWSCH_R1_BSPLIT_STATS__STATS_DIST___POR 0x00000 +#define WMAC0_HWSCH_R1_BSPLIT_STATS__STATS_COUNT___POR 0x000 +#define WMAC0_HWSCH_R1_BSPLIT_STATS__STATS_DIST___M 0x3FFFF000 +#define WMAC0_HWSCH_R1_BSPLIT_STATS__STATS_DIST___S 12 +#define WMAC0_HWSCH_R1_BSPLIT_STATS__STATS_COUNT___M 0x00000FFF +#define WMAC0_HWSCH_R1_BSPLIT_STATS__STATS_COUNT___S 0 +#define WMAC0_HWSCH_R1_BSPLIT_STATS___M 0x3FFFFFFF +#define WMAC0_HWSCH_R1_BSPLIT_STATS___S 0 + +#define WMAC0_HWSCH_R1_FLUSH_STATS (0x00AAE040) +#define WMAC0_HWSCH_R1_FLUSH_STATS___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_FLUSH_STATS___POR 0x00000000 +#define WMAC0_HWSCH_R1_FLUSH_STATS__STATS_DIST___POR 0x00000 +#define WMAC0_HWSCH_R1_FLUSH_STATS__STATS_COUNT___POR 0x000 +#define WMAC0_HWSCH_R1_FLUSH_STATS__STATS_DIST___M 0x3FFFF000 +#define WMAC0_HWSCH_R1_FLUSH_STATS__STATS_DIST___S 12 +#define WMAC0_HWSCH_R1_FLUSH_STATS__STATS_COUNT___M 0x00000FFF +#define WMAC0_HWSCH_R1_FLUSH_STATS__STATS_COUNT___S 0 +#define WMAC0_HWSCH_R1_FLUSH_STATS___M 0x3FFFFFFF +#define WMAC0_HWSCH_R1_FLUSH_STATS___S 0 + +#define WMAC0_HWSCH_R1_RXP_FILT_ID_OOR_STATS (0x00AAE044) +#define WMAC0_HWSCH_R1_RXP_FILT_ID_OOR_STATS___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_RXP_FILT_ID_OOR_STATS___POR 0x00000000 +#define WMAC0_HWSCH_R1_RXP_FILT_ID_OOR_STATS__STATS_COUNT___POR 0x00 +#define WMAC0_HWSCH_R1_RXP_FILT_ID_OOR_STATS__STATS_COUNT___M 0x000000FF +#define WMAC0_HWSCH_R1_RXP_FILT_ID_OOR_STATS__STATS_COUNT___S 0 +#define WMAC0_HWSCH_R1_RXP_FILT_ID_OOR_STATS___M 0x000000FF +#define WMAC0_HWSCH_R1_RXP_FILT_ID_OOR_STATS___S 0 + +#define WMAC0_HWSCH_R1_SRP_SR_OPP_STATS_CFG (0x00AAE048) +#define WMAC0_HWSCH_R1_SRP_SR_OPP_STATS_CFG___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_SRP_SR_OPP_STATS_CFG___POR 0x00000000 +#define WMAC0_HWSCH_R1_SRP_SR_OPP_STATS_CFG__SELECT_SRG_OR_SRP___POR 0x0 +#define WMAC0_HWSCH_R1_SRP_SR_OPP_STATS_CFG__SELECT___POR 0x0 +#define WMAC0_HWSCH_R1_SRP_SR_OPP_STATS_CFG__SELECT_SRG_OR_SRP___M 0x00000002 +#define WMAC0_HWSCH_R1_SRP_SR_OPP_STATS_CFG__SELECT_SRG_OR_SRP___S 1 +#define WMAC0_HWSCH_R1_SRP_SR_OPP_STATS_CFG__SELECT___M 0x00000001 +#define WMAC0_HWSCH_R1_SRP_SR_OPP_STATS_CFG__SELECT___S 0 +#define WMAC0_HWSCH_R1_SRP_SR_OPP_STATS_CFG___M 0x00000003 +#define WMAC0_HWSCH_R1_SRP_SR_OPP_STATS_CFG___S 0 + +#define WMAC0_HWSCH_R1_SR_SRP_STATS_0 (0x00AAE04C) +#define WMAC0_HWSCH_R1_SR_SRP_STATS_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_SR_SRP_STATS_0___POR 0x00000000 +#define WMAC0_HWSCH_R1_SR_SRP_STATS_0__SR_SRP_OPP_COUNT___POR 0x0000 +#define WMAC0_HWSCH_R1_SR_SRP_STATS_0__OBSS_NON_SRG_RISE_COUNT___POR 0x0000 +#define WMAC0_HWSCH_R1_SR_SRP_STATS_0__SR_SRP_OPP_COUNT___M 0xFFFF0000 +#define WMAC0_HWSCH_R1_SR_SRP_STATS_0__SR_SRP_OPP_COUNT___S 16 +#define WMAC0_HWSCH_R1_SR_SRP_STATS_0__OBSS_NON_SRG_RISE_COUNT___M 0x0000FFFF +#define WMAC0_HWSCH_R1_SR_SRP_STATS_0__OBSS_NON_SRG_RISE_COUNT___S 0 +#define WMAC0_HWSCH_R1_SR_SRP_STATS_0___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_SR_SRP_STATS_0___S 0 + +#define WMAC0_HWSCH_R1_SR_SRP_STATS_1 (0x00AAE050) +#define WMAC0_HWSCH_R1_SR_SRP_STATS_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_SR_SRP_STATS_1___POR 0x00000000 +#define WMAC0_HWSCH_R1_SR_SRP_STATS_1__OBSS_NON_SRG_RISE_COUNT___POR 0x0000 +#define WMAC0_HWSCH_R1_SR_SRP_STATS_1__SR_RSSI_LATD_NON_SRG_COUNT___POR 0x0000 +#define WMAC0_HWSCH_R1_SR_SRP_STATS_1__OBSS_NON_SRG_RISE_COUNT___M 0xFFFF0000 +#define WMAC0_HWSCH_R1_SR_SRP_STATS_1__OBSS_NON_SRG_RISE_COUNT___S 16 +#define WMAC0_HWSCH_R1_SR_SRP_STATS_1__SR_RSSI_LATD_NON_SRG_COUNT___M 0x0000FFFF +#define WMAC0_HWSCH_R1_SR_SRP_STATS_1__SR_RSSI_LATD_NON_SRG_COUNT___S 0 +#define WMAC0_HWSCH_R1_SR_SRP_STATS_1___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_SR_SRP_STATS_1___S 0 + +#define WMAC0_HWSCH_R1_SR_SRP_STATS_2 (0x00AAE054) +#define WMAC0_HWSCH_R1_SR_SRP_STATS_2___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_SR_SRP_STATS_2___POR 0x00000000 +#define WMAC0_HWSCH_R1_SR_SRP_STATS_2__SR_RSSI_LATD_SRG_COUNT___POR 0x0000 +#define WMAC0_HWSCH_R1_SR_SRP_STATS_2__SRP_PWR_LATD_COUNT___POR 0x0000 +#define WMAC0_HWSCH_R1_SR_SRP_STATS_2__SR_RSSI_LATD_SRG_COUNT___M 0xFFFF0000 +#define WMAC0_HWSCH_R1_SR_SRP_STATS_2__SR_RSSI_LATD_SRG_COUNT___S 16 +#define WMAC0_HWSCH_R1_SR_SRP_STATS_2__SRP_PWR_LATD_COUNT___M 0x0000FFFF +#define WMAC0_HWSCH_R1_SR_SRP_STATS_2__SRP_PWR_LATD_COUNT___S 0 +#define WMAC0_HWSCH_R1_SR_SRP_STATS_2___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_SR_SRP_STATS_2___S 0 + +#define WMAC0_HWSCH_R1_SR_SRP_STATS_3 (0x00AAE058) +#define WMAC0_HWSCH_R1_SR_SRP_STATS_3___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_SR_SRP_STATS_3___POR 0x00000000 +#define WMAC0_HWSCH_R1_SR_SRP_STATS_3__SRG_OR_SRP_MULT_INF_LATD_COUNT___POR 0x0000 +#define WMAC0_HWSCH_R1_SR_SRP_STATS_3__NON_SRG_MULT_INF_LATD_COUNT___POR 0x0000 +#define WMAC0_HWSCH_R1_SR_SRP_STATS_3__SRG_OR_SRP_MULT_INF_LATD_COUNT___M 0xFFFF0000 +#define WMAC0_HWSCH_R1_SR_SRP_STATS_3__SRG_OR_SRP_MULT_INF_LATD_COUNT___S 16 +#define WMAC0_HWSCH_R1_SR_SRP_STATS_3__NON_SRG_MULT_INF_LATD_COUNT___M 0x0000FFFF +#define WMAC0_HWSCH_R1_SR_SRP_STATS_3__NON_SRG_MULT_INF_LATD_COUNT___S 0 +#define WMAC0_HWSCH_R1_SR_SRP_STATS_3___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_SR_SRP_STATS_3___S 0 + +#define WMAC0_HWSCH_R1_NAV_STATS_0 (0x00AAE05C) +#define WMAC0_HWSCH_R1_NAV_STATS_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_NAV_STATS_0___POR 0x00000000 +#define WMAC0_HWSCH_R1_NAV_STATS_0__INBSS_NAV_UPDATE_P_COUNT___POR 0x0000 +#define WMAC0_HWSCH_R1_NAV_STATS_0__NAV_UPDATE_P_COUNT___POR 0x0000 +#define WMAC0_HWSCH_R1_NAV_STATS_0__INBSS_NAV_UPDATE_P_COUNT___M 0xFFFF0000 +#define WMAC0_HWSCH_R1_NAV_STATS_0__INBSS_NAV_UPDATE_P_COUNT___S 16 +#define WMAC0_HWSCH_R1_NAV_STATS_0__NAV_UPDATE_P_COUNT___M 0x0000FFFF +#define WMAC0_HWSCH_R1_NAV_STATS_0__NAV_UPDATE_P_COUNT___S 0 +#define WMAC0_HWSCH_R1_NAV_STATS_0___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_NAV_STATS_0___S 0 + +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_0 (0x00AAE060) +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_0___POR 0x00000000 +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_0__REQUE_TYPE___POR 0x00000000 +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_0__REQUE_TYPE___M 0xFFFFFFFC +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_0__REQUE_TYPE___S 2 +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_0___M 0xFFFFFFFC +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_0___S 2 + +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_1 (0x00AAE064) +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_1___POR 0x00000000 +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_1__FILTER_TYPE___POR 0x00000000 +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_1__FILTER_TYPE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_1__FILTER_TYPE___S 0 +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_1___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_1___S 0 + +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_2 (0x00AAE068) +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_2___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_2___POR 0x00000000 +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_2__FILTER_TYPE___POR 0x000 +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_2__FILTER_TYPE___M 0x000001FF +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_2__FILTER_TYPE___S 0 +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_2___M 0x000001FF +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_2___S 0 + +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_3 (0x00AAE06C) +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_3___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_3___POR 0x00000000 +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_3__FLUSH_TYPE___POR 0x00000000 +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_3__FLUSH_TYPE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_3__FLUSH_TYPE___S 0 +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_3___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_3___S 0 + +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_4 (0x00AAE070) +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_4___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_4___POR 0x00000000 +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_4__FLUSH_TYPE___POR 0x00000000 +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_4__FLUSH_TYPE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_4__FLUSH_TYPE___S 0 +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_4___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_4___S 0 + +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_5 (0x00AAE074) +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_5___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_5___POR 0x00000000 +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_5__FLUSH_TYPE___POR 0x00000000 +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_5__FLUSH_TYPE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_5__FLUSH_TYPE___S 0 +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_5___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_5___S 0 + +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_6 (0x00AAE078) +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_6___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_6___POR 0x00000000 +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_6__FLUSH_TYPE___POR 0x00000000 +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_6__FLUSH_TYPE___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_6__FLUSH_TYPE___S 0 +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_6___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_6___S 0 + +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_7 (0x00AAE07C) +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_7___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_7___POR 0x00000000 +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_7__FLUSH_TYPE___POR 0x0 +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_7__FLUSH_TYPE___M 0x00000007 +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_7__FLUSH_TYPE___S 0 +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_7___M 0x00000007 +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_7___S 0 + +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_8 (0x00AAE080) +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_8___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_8___POR 0x00000000 +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_8__RETRY_TYPE___POR 0x0 +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_8__RETRY_TYPE___M 0x0000000F +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_8__RETRY_TYPE___S 0 +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_8___M 0x0000000F +#define WMAC0_HWSCH_R1_SEQEND_BIN_REG_8___S 0 + +#define WMAC0_HWSCH_R1_TLV_IF_STATS (0x00AAE084) +#define WMAC0_HWSCH_R1_TLV_IF_STATS___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_TLV_IF_STATS___POR 0x00000000 +#define WMAC0_HWSCH_R1_TLV_IF_STATS__TLV_OUT_COUNT___POR 0x0000 +#define WMAC0_HWSCH_R1_TLV_IF_STATS__TLV_IN_COUNT___POR 0x0000 +#define WMAC0_HWSCH_R1_TLV_IF_STATS__TLV_OUT_COUNT___M 0xFFFF0000 +#define WMAC0_HWSCH_R1_TLV_IF_STATS__TLV_OUT_COUNT___S 16 +#define WMAC0_HWSCH_R1_TLV_IF_STATS__TLV_IN_COUNT___M 0x0000FFFF +#define WMAC0_HWSCH_R1_TLV_IF_STATS__TLV_IN_COUNT___S 0 +#define WMAC0_HWSCH_R1_TLV_IF_STATS___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_TLV_IF_STATS___S 0 + +#define WMAC0_HWSCH_R1_TRC_EVENTMASK_IX_0 (0x00AAE088) +#define WMAC0_HWSCH_R1_TRC_EVENTMASK_IX_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_TRC_EVENTMASK_IX_0___POR 0x00000000 +#define WMAC0_HWSCH_R1_TRC_EVENTMASK_IX_0__MASK___POR 0x00000000 +#define WMAC0_HWSCH_R1_TRC_EVENTMASK_IX_0__MASK___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_TRC_EVENTMASK_IX_0__MASK___S 0 +#define WMAC0_HWSCH_R1_TRC_EVENTMASK_IX_0___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_TRC_EVENTMASK_IX_0___S 0 + +#define WMAC0_HWSCH_R1_TRC_EVENTMASK_IX_1 (0x00AAE08C) +#define WMAC0_HWSCH_R1_TRC_EVENTMASK_IX_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_TRC_EVENTMASK_IX_1___POR 0x00000000 +#define WMAC0_HWSCH_R1_TRC_EVENTMASK_IX_1__MASK___POR 0x00000000 +#define WMAC0_HWSCH_R1_TRC_EVENTMASK_IX_1__MASK___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_TRC_EVENTMASK_IX_1__MASK___S 0 +#define WMAC0_HWSCH_R1_TRC_EVENTMASK_IX_1___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_TRC_EVENTMASK_IX_1___S 0 + +#define WMAC0_HWSCH_R1_QUIET_FLUSH_STATS (0x00AAE090) +#define WMAC0_HWSCH_R1_QUIET_FLUSH_STATS___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_QUIET_FLUSH_STATS___POR 0x00000000 +#define WMAC0_HWSCH_R1_QUIET_FLUSH_STATS__AUTO_FLUSH_COUNT___POR 0x0000 +#define WMAC0_HWSCH_R1_QUIET_FLUSH_STATS__PREBKOF_FLUSH_COUNT___POR 0x0000 +#define WMAC0_HWSCH_R1_QUIET_FLUSH_STATS__AUTO_FLUSH_COUNT___M 0xFFFF0000 +#define WMAC0_HWSCH_R1_QUIET_FLUSH_STATS__AUTO_FLUSH_COUNT___S 16 +#define WMAC0_HWSCH_R1_QUIET_FLUSH_STATS__PREBKOF_FLUSH_COUNT___M 0x0000FFFF +#define WMAC0_HWSCH_R1_QUIET_FLUSH_STATS__PREBKOF_FLUSH_COUNT___S 0 +#define WMAC0_HWSCH_R1_QUIET_FLUSH_STATS___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_QUIET_FLUSH_STATS___S 0 + +#define WMAC0_HWSCH_R1_AXI_STATS (0x00AAE094) +#define WMAC0_HWSCH_R1_AXI_STATS___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_AXI_STATS___POR 0x00000000 +#define WMAC0_HWSCH_R1_AXI_STATS__CLEAR_STATS___POR 0x0 +#define WMAC0_HWSCH_R1_AXI_STATS__AXI_RD_CH_MAX_LATENCY___POR 0x0000 +#define WMAC0_HWSCH_R1_AXI_STATS__CLEAR_STATS___M 0x80000000 +#define WMAC0_HWSCH_R1_AXI_STATS__CLEAR_STATS___S 31 +#define WMAC0_HWSCH_R1_AXI_STATS__AXI_RD_CH_MAX_LATENCY___M 0x0000FFFF +#define WMAC0_HWSCH_R1_AXI_STATS__AXI_RD_CH_MAX_LATENCY___S 0 +#define WMAC0_HWSCH_R1_AXI_STATS___M 0x8000FFFF +#define WMAC0_HWSCH_R1_AXI_STATS___S 0 + +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_n(n) (0x00AAE098+0x4*(n)) +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_n_nMIN 0 +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_n_nMAX 19 +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_n_ELEM 20 +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_n___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_n___POR 0x000000FF +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_n__SELECT___POR 0xFF +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_n__SELECT___M 0x000000FF +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_n__SELECT___S 0 +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_n___M 0x000000FF +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_n___S 0 +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_0 (0x00AAE098) +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_0__SELECT___M 0x000000FF +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_0__SELECT___S 0 +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_1 (0x00AAE09C) +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_1__SELECT___M 0x000000FF +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_1__SELECT___S 0 +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_2 (0x00AAE0A0) +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_2___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_2__SELECT___M 0x000000FF +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_2__SELECT___S 0 +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_3 (0x00AAE0A4) +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_3___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_3__SELECT___M 0x000000FF +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_3__SELECT___S 0 +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_4 (0x00AAE0A8) +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_4___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_4__SELECT___M 0x000000FF +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_4__SELECT___S 0 +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_5 (0x00AAE0AC) +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_5___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_5__SELECT___M 0x000000FF +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_5__SELECT___S 0 +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_6 (0x00AAE0B0) +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_6___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_6__SELECT___M 0x000000FF +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_6__SELECT___S 0 +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_7 (0x00AAE0B4) +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_7___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_7__SELECT___M 0x000000FF +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_7__SELECT___S 0 +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_8 (0x00AAE0B8) +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_8___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_8__SELECT___M 0x000000FF +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_8__SELECT___S 0 +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_9 (0x00AAE0BC) +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_9___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_9__SELECT___M 0x000000FF +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_9__SELECT___S 0 +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_10 (0x00AAE0C0) +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_10___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_10__SELECT___M 0x000000FF +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_10__SELECT___S 0 +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_11 (0x00AAE0C4) +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_11___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_11__SELECT___M 0x000000FF +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_11__SELECT___S 0 +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_12 (0x00AAE0C8) +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_12___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_12__SELECT___M 0x000000FF +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_12__SELECT___S 0 +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_13 (0x00AAE0CC) +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_13___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_13__SELECT___M 0x000000FF +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_13__SELECT___S 0 +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_14 (0x00AAE0D0) +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_14___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_14__SELECT___M 0x000000FF +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_14__SELECT___S 0 +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_15 (0x00AAE0D4) +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_15___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_15__SELECT___M 0x000000FF +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_15__SELECT___S 0 +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_16 (0x00AAE0D8) +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_16___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_16__SELECT___M 0x000000FF +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_16__SELECT___S 0 +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_17 (0x00AAE0DC) +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_17___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_17__SELECT___M 0x000000FF +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_17__SELECT___S 0 +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_18 (0x00AAE0E0) +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_18___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_18__SELECT___M 0x000000FF +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_18__SELECT___S 0 +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_19 (0x00AAE0E4) +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_19___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_19__SELECT___M 0x000000FF +#define WMAC0_HWSCH_R1_MTU_CCA_EVT_CFG_19__SELECT___S 0 + +#define WMAC0_HWSCH_R1_REG_ACCESS_EVENT_GEN_CTRL (0x00AAE0E8) +#define WMAC0_HWSCH_R1_REG_ACCESS_EVENT_GEN_CTRL___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_REG_ACCESS_EVENT_GEN_CTRL___POR 0x7FFE0002 +#define WMAC0_HWSCH_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___POR 0x3FFF +#define WMAC0_HWSCH_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___POR 0x0000 +#define WMAC0_HWSCH_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___POR 0x1 +#define WMAC0_HWSCH_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___POR 0x0 +#define WMAC0_HWSCH_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___M 0xFFFE0000 +#define WMAC0_HWSCH_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___S 17 +#define WMAC0_HWSCH_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___M 0x0001FFFC +#define WMAC0_HWSCH_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___S 2 +#define WMAC0_HWSCH_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___M 0x00000002 +#define WMAC0_HWSCH_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___S 1 +#define WMAC0_HWSCH_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___M 0x00000001 +#define WMAC0_HWSCH_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___S 0 +#define WMAC0_HWSCH_R1_REG_ACCESS_EVENT_GEN_CTRL___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_REG_ACCESS_EVENT_GEN_CTRL___S 0 + +#define WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL (0x00AAE0EC) +#define WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL___POR 0x00200000 +#define WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL__TLVIF_SELECT___POR 0x0 +#define WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL__HILO___POR 0x0 +#define WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL__NUM_DW_TO_CAPTURE___POR 0x008 +#define WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL__TRIGGER_TAG_1___POR 0x000 +#define WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL__TRIGGER_TAG_0___POR 0x000 +#define WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL__TLVIF_SELECT___M 0xE0000000 +#define WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL__TLVIF_SELECT___S 29 +#define WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL__HILO___M 0x10000000 +#define WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL__HILO___S 28 +#define WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL__NUM_DW_TO_CAPTURE___M 0x0FFC0000 +#define WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL__NUM_DW_TO_CAPTURE___S 18 +#define WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL__TRIGGER_TAG_1___M 0x0003FE00 +#define WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL__TRIGGER_TAG_1___S 9 +#define WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL__TRIGGER_TAG_0___M 0x000001FF +#define WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL__TRIGGER_TAG_0___S 0 +#define WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL___S 0 + +#define WMAC0_HWSCH_R1_APT_CTRL_SPR (0x00AAE0F0) +#define WMAC0_HWSCH_R1_APT_CTRL_SPR___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_APT_CTRL_SPR___POR 0x00000000 +#define WMAC0_HWSCH_R1_APT_CTRL_SPR__APT_SPR_OUT___POR 0x00 +#define WMAC0_HWSCH_R1_APT_CTRL_SPR__APT_SPR_IN___POR 0x00 +#define WMAC0_HWSCH_R1_APT_CTRL_SPR__APT_SPR_OUT___M 0x0000FF00 +#define WMAC0_HWSCH_R1_APT_CTRL_SPR__APT_SPR_OUT___S 8 +#define WMAC0_HWSCH_R1_APT_CTRL_SPR__APT_SPR_IN___M 0x000000FF +#define WMAC0_HWSCH_R1_APT_CTRL_SPR__APT_SPR_IN___S 0 +#define WMAC0_HWSCH_R1_APT_CTRL_SPR___M 0x0000FFFF +#define WMAC0_HWSCH_R1_APT_CTRL_SPR___S 0 + +#define WMAC0_HWSCH_R1_LMODE_VIOL_STATS (0x00AAE0F4) +#define WMAC0_HWSCH_R1_LMODE_VIOL_STATS___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_LMODE_VIOL_STATS___POR 0x00000000 +#define WMAC0_HWSCH_R1_LMODE_VIOL_STATS__COUNT___POR 0x0000 +#define WMAC0_HWSCH_R1_LMODE_VIOL_STATS__COUNT___M 0x0000FFFF +#define WMAC0_HWSCH_R1_LMODE_VIOL_STATS__COUNT___S 0 +#define WMAC0_HWSCH_R1_LMODE_VIOL_STATS___M 0x0000FFFF +#define WMAC0_HWSCH_R1_LMODE_VIOL_STATS___S 0 + +#define WMAC0_HWSCH_R1_LMODE_VIOL_THRESHOLD (0x00AAE0F8) +#define WMAC0_HWSCH_R1_LMODE_VIOL_THRESHOLD___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_LMODE_VIOL_THRESHOLD___POR 0x00000016 +#define WMAC0_HWSCH_R1_LMODE_VIOL_THRESHOLD__DATA___POR 0x16 +#define WMAC0_HWSCH_R1_LMODE_VIOL_THRESHOLD__DATA___M 0x0000001F +#define WMAC0_HWSCH_R1_LMODE_VIOL_THRESHOLD__DATA___S 0 +#define WMAC0_HWSCH_R1_LMODE_VIOL_THRESHOLD___M 0x0000001F +#define WMAC0_HWSCH_R1_LMODE_VIOL_THRESHOLD___S 0 + +#define WMAC0_HWSCH_R1_HWSCH2TQM_FLUSH_STATS (0x00AAE0FC) +#define WMAC0_HWSCH_R1_HWSCH2TQM_FLUSH_STATS___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_HWSCH2TQM_FLUSH_STATS___POR 0x00000000 +#define WMAC0_HWSCH_R1_HWSCH2TQM_FLUSH_STATS__TQM2HWSCH_FLUSH_ACK_CNT___POR 0x0000 +#define WMAC0_HWSCH_R1_HWSCH2TQM_FLUSH_STATS__HWSCH2TQM_FLUSH_REQ_CNT___POR 0x0000 +#define WMAC0_HWSCH_R1_HWSCH2TQM_FLUSH_STATS__TQM2HWSCH_FLUSH_ACK_CNT___M 0xFFFF0000 +#define WMAC0_HWSCH_R1_HWSCH2TQM_FLUSH_STATS__TQM2HWSCH_FLUSH_ACK_CNT___S 16 +#define WMAC0_HWSCH_R1_HWSCH2TQM_FLUSH_STATS__HWSCH2TQM_FLUSH_REQ_CNT___M 0x0000FFFF +#define WMAC0_HWSCH_R1_HWSCH2TQM_FLUSH_STATS__HWSCH2TQM_FLUSH_REQ_CNT___S 0 +#define WMAC0_HWSCH_R1_HWSCH2TQM_FLUSH_STATS___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_HWSCH2TQM_FLUSH_STATS___S 0 + +#define WMAC0_HWSCH_R1_HWSCH_SPR_STAT (0x00AAE100) +#define WMAC0_HWSCH_R1_HWSCH_SPR_STAT___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_HWSCH_SPR_STAT___POR 0x00000000 +#define WMAC0_HWSCH_R1_HWSCH_SPR_STAT__SPR_CNTR1___POR 0x0000 +#define WMAC0_HWSCH_R1_HWSCH_SPR_STAT__SPR_CNTR2___POR 0x0000 +#define WMAC0_HWSCH_R1_HWSCH_SPR_STAT__SPR_CNTR1___M 0xFFFF0000 +#define WMAC0_HWSCH_R1_HWSCH_SPR_STAT__SPR_CNTR1___S 16 +#define WMAC0_HWSCH_R1_HWSCH_SPR_STAT__SPR_CNTR2___M 0x0000FFFF +#define WMAC0_HWSCH_R1_HWSCH_SPR_STAT__SPR_CNTR2___S 0 +#define WMAC0_HWSCH_R1_HWSCH_SPR_STAT___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_HWSCH_SPR_STAT___S 0 + +#define WMAC0_HWSCH_R1_HWSCH_OBSS_PD_RSSI_THR (0x00AAE104) +#define WMAC0_HWSCH_R1_HWSCH_OBSS_PD_RSSI_THR___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_HWSCH_OBSS_PD_RSSI_THR___POR 0x0E0E0E0E +#define WMAC0_HWSCH_R1_HWSCH_OBSS_PD_RSSI_THR__RSSI_THR_ALT_SRG___POR 0x0E +#define WMAC0_HWSCH_R1_HWSCH_OBSS_PD_RSSI_THR__RSSI_THR_PRI_SRG___POR 0x0E +#define WMAC0_HWSCH_R1_HWSCH_OBSS_PD_RSSI_THR__RSSI_THR_ALT_NON_SRG___POR 0x0E +#define WMAC0_HWSCH_R1_HWSCH_OBSS_PD_RSSI_THR__RSSI_THR_PRI_NON_SRG___POR 0x0E +#define WMAC0_HWSCH_R1_HWSCH_OBSS_PD_RSSI_THR__RSSI_THR_ALT_SRG___M 0xFF000000 +#define WMAC0_HWSCH_R1_HWSCH_OBSS_PD_RSSI_THR__RSSI_THR_ALT_SRG___S 24 +#define WMAC0_HWSCH_R1_HWSCH_OBSS_PD_RSSI_THR__RSSI_THR_PRI_SRG___M 0x00FF0000 +#define WMAC0_HWSCH_R1_HWSCH_OBSS_PD_RSSI_THR__RSSI_THR_PRI_SRG___S 16 +#define WMAC0_HWSCH_R1_HWSCH_OBSS_PD_RSSI_THR__RSSI_THR_ALT_NON_SRG___M 0x0000FF00 +#define WMAC0_HWSCH_R1_HWSCH_OBSS_PD_RSSI_THR__RSSI_THR_ALT_NON_SRG___S 8 +#define WMAC0_HWSCH_R1_HWSCH_OBSS_PD_RSSI_THR__RSSI_THR_PRI_NON_SRG___M 0x000000FF +#define WMAC0_HWSCH_R1_HWSCH_OBSS_PD_RSSI_THR__RSSI_THR_PRI_NON_SRG___S 0 +#define WMAC0_HWSCH_R1_HWSCH_OBSS_PD_RSSI_THR___M 0xFFFFFFFF +#define WMAC0_HWSCH_R1_HWSCH_OBSS_PD_RSSI_THR___S 0 + +#define WMAC0_HWSCH_R1_HWSCH_SRP_PWR_THR (0x00AAE108) +#define WMAC0_HWSCH_R1_HWSCH_SRP_PWR_THR___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_HWSCH_SRP_PWR_THR___POR 0x00000E0E +#define WMAC0_HWSCH_R1_HWSCH_SRP_PWR_THR__SET_SRP_INFO___POR 0x0 +#define WMAC0_HWSCH_R1_HWSCH_SRP_PWR_THR__VAL_SRP_INFO___POR 0x00 +#define WMAC0_HWSCH_R1_HWSCH_SRP_PWR_THR__SRP_PWR_THR_ALT___POR 0x0E +#define WMAC0_HWSCH_R1_HWSCH_SRP_PWR_THR__SRP_PWR_THR_PRI___POR 0x0E +#define WMAC0_HWSCH_R1_HWSCH_SRP_PWR_THR__SET_SRP_INFO___M 0x01000000 +#define WMAC0_HWSCH_R1_HWSCH_SRP_PWR_THR__SET_SRP_INFO___S 24 +#define WMAC0_HWSCH_R1_HWSCH_SRP_PWR_THR__VAL_SRP_INFO___M 0x00FF0000 +#define WMAC0_HWSCH_R1_HWSCH_SRP_PWR_THR__VAL_SRP_INFO___S 16 +#define WMAC0_HWSCH_R1_HWSCH_SRP_PWR_THR__SRP_PWR_THR_ALT___M 0x0000FF00 +#define WMAC0_HWSCH_R1_HWSCH_SRP_PWR_THR__SRP_PWR_THR_ALT___S 8 +#define WMAC0_HWSCH_R1_HWSCH_SRP_PWR_THR__SRP_PWR_THR_PRI___M 0x000000FF +#define WMAC0_HWSCH_R1_HWSCH_SRP_PWR_THR__SRP_PWR_THR_PRI___S 0 +#define WMAC0_HWSCH_R1_HWSCH_SRP_PWR_THR___M 0x01FFFFFF +#define WMAC0_HWSCH_R1_HWSCH_SRP_PWR_THR___S 0 + +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_CLR (0x00AAE10C) +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_CLR___RWC QCSR_REG_WO +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_CLR___POR 0x00000000 +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_CLR__CLEAR___POR 0x0 +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_CLR__CLEAR___M 0x00000001 +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_CLR__CLEAR___S 0 +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_CLR___M 0x00000001 +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_CLR___S 0 + +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_n(n) (0x00AAE110+0x4*(n)) +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_n_nMIN 0 +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_n_nMAX 7 +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_n_ELEM 8 +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_n___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_n___POR 0x00000000 +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_n__ERROR_INTR_CODE___POR 0x00 +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_n__ERROR_INTR_CODE___M 0x000000FF +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_n__ERROR_INTR_CODE___S 0 +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_n___M 0x000000FF +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_n___S 0 +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_0 (0x00AAE110) +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_0___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_0__ERROR_INTR_CODE___M 0x000000FF +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_0__ERROR_INTR_CODE___S 0 +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_1 (0x00AAE114) +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_1___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_1__ERROR_INTR_CODE___M 0x000000FF +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_1__ERROR_INTR_CODE___S 0 +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_2 (0x00AAE118) +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_2___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_2__ERROR_INTR_CODE___M 0x000000FF +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_2__ERROR_INTR_CODE___S 0 +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_3 (0x00AAE11C) +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_3___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_3__ERROR_INTR_CODE___M 0x000000FF +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_3__ERROR_INTR_CODE___S 0 +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_4 (0x00AAE120) +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_4___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_4__ERROR_INTR_CODE___M 0x000000FF +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_4__ERROR_INTR_CODE___S 0 +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_5 (0x00AAE124) +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_5___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_5__ERROR_INTR_CODE___M 0x000000FF +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_5__ERROR_INTR_CODE___S 0 +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_6 (0x00AAE128) +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_6___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_6__ERROR_INTR_CODE___M 0x000000FF +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_6__ERROR_INTR_CODE___S 0 +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_7 (0x00AAE12C) +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_7___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_7__ERROR_INTR_CODE___M 0x000000FF +#define WMAC0_HWSCH_R1_ERROR_INTR_HISTOGRAM_7__ERROR_INTR_CODE___S 0 + +#define WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL2 (0x00AAE130) +#define WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL2___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL2___POR 0x00000000 +#define WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL2__DISABLE_TLV_TAG_CHECK___POR 0x0 +#define WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL2__DISABLE_TLV_TAG_CHECK___M 0x00000001 +#define WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL2__DISABLE_TLV_TAG_CHECK___S 0 +#define WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL2___M 0x00000001 +#define WMAC0_HWSCH_R1_GENERIC_TLVIF_CAPTURE_EVENT_CTRL2___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_0 (0x00AAF000) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_0___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_0__CMD_RING_HEAD_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_0__CMD_RING_HEAD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_0__CMD_RING_HEAD_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_0___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_0___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_1 (0x00AAF004) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_1___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_1__CMD_RING_HEAD_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_1__CMD_RING_HEAD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_1__CMD_RING_HEAD_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_1___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_1___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_2 (0x00AAF008) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_2___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_2___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_2__CMD_RING_HEAD_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_2__CMD_RING_HEAD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_2__CMD_RING_HEAD_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_2___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_2___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_3 (0x00AAF00C) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_3___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_3___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_3__CMD_RING_HEAD_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_3__CMD_RING_HEAD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_3__CMD_RING_HEAD_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_3___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_3___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_4 (0x00AAF010) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_4___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_4___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_4__CMD_RING_HEAD_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_4__CMD_RING_HEAD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_4__CMD_RING_HEAD_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_4___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_4___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_5 (0x00AAF014) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_5___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_5___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_5__CMD_RING_HEAD_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_5__CMD_RING_HEAD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_5__CMD_RING_HEAD_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_5___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_5___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_6 (0x00AAF018) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_6___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_6___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_6__CMD_RING_HEAD_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_6__CMD_RING_HEAD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_6__CMD_RING_HEAD_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_6___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_6___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_7 (0x00AAF01C) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_7___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_7___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_7__CMD_RING_HEAD_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_7__CMD_RING_HEAD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_7__CMD_RING_HEAD_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_7___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_7___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_8 (0x00AAF020) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_8___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_8___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_8__CMD_RING_HEAD_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_8__CMD_RING_HEAD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_8__CMD_RING_HEAD_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_8___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_8___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_9 (0x00AAF024) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_9___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_9___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_9__CMD_RING_HEAD_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_9__CMD_RING_HEAD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_9__CMD_RING_HEAD_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_9___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_9___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_10 (0x00AAF028) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_10___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_10___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_10__CMD_RING_HEAD_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_10__CMD_RING_HEAD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_10__CMD_RING_HEAD_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_10___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_10___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_11 (0x00AAF02C) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_11___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_11___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_11__CMD_RING_HEAD_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_11__CMD_RING_HEAD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_11__CMD_RING_HEAD_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_11___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_11___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_12 (0x00AAF030) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_12___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_12___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_12__CMD_RING_HEAD_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_12__CMD_RING_HEAD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_12__CMD_RING_HEAD_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_12___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_12___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_13 (0x00AAF034) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_13___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_13___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_13__CMD_RING_HEAD_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_13__CMD_RING_HEAD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_13__CMD_RING_HEAD_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_13___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_13___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_14 (0x00AAF038) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_14___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_14___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_14__CMD_RING_HEAD_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_14__CMD_RING_HEAD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_14__CMD_RING_HEAD_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_14___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_14___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_15 (0x00AAF03C) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_15___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_15___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_15__CMD_RING_HEAD_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_15__CMD_RING_HEAD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_15__CMD_RING_HEAD_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_15___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_15___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_16 (0x00AAF040) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_16___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_16___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_16__CMD_RING_HEAD_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_16__CMD_RING_HEAD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_16__CMD_RING_HEAD_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_16___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_16___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_17 (0x00AAF044) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_17___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_17___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_17__CMD_RING_HEAD_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_17__CMD_RING_HEAD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_17__CMD_RING_HEAD_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_17___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_HEAD_IX_17___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_0 (0x00AAF050) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_0___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_0___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_0__CMD_RING_TAIL_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_0__CMD_RING_TAIL_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_0__CMD_RING_TAIL_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_0___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_0___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_1 (0x00AAF054) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_1___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_1___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_1__CMD_RING_TAIL_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_1__CMD_RING_TAIL_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_1__CMD_RING_TAIL_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_1___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_1___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_2 (0x00AAF058) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_2___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_2___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_2__CMD_RING_TAIL_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_2__CMD_RING_TAIL_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_2__CMD_RING_TAIL_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_2___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_2___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_3 (0x00AAF05C) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_3___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_3___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_3__CMD_RING_TAIL_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_3__CMD_RING_TAIL_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_3__CMD_RING_TAIL_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_3___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_3___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_4 (0x00AAF060) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_4___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_4___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_4__CMD_RING_TAIL_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_4__CMD_RING_TAIL_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_4__CMD_RING_TAIL_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_4___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_4___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_5 (0x00AAF064) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_5___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_5___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_5__CMD_RING_TAIL_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_5__CMD_RING_TAIL_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_5__CMD_RING_TAIL_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_5___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_5___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_6 (0x00AAF068) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_6___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_6___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_6__CMD_RING_TAIL_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_6__CMD_RING_TAIL_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_6__CMD_RING_TAIL_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_6___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_6___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_7 (0x00AAF06C) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_7___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_7___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_7__CMD_RING_TAIL_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_7__CMD_RING_TAIL_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_7__CMD_RING_TAIL_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_7___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_7___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_8 (0x00AAF070) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_8___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_8___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_8__CMD_RING_TAIL_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_8__CMD_RING_TAIL_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_8__CMD_RING_TAIL_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_8___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_8___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_9 (0x00AAF074) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_9___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_9___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_9__CMD_RING_TAIL_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_9__CMD_RING_TAIL_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_9__CMD_RING_TAIL_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_9___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_9___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_10 (0x00AAF078) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_10___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_10___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_10__CMD_RING_TAIL_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_10__CMD_RING_TAIL_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_10__CMD_RING_TAIL_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_10___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_10___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_11 (0x00AAF07C) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_11___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_11___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_11__CMD_RING_TAIL_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_11__CMD_RING_TAIL_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_11__CMD_RING_TAIL_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_11___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_11___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_12 (0x00AAF080) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_12___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_12___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_12__CMD_RING_TAIL_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_12__CMD_RING_TAIL_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_12__CMD_RING_TAIL_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_12___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_12___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_13 (0x00AAF084) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_13___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_13___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_13__CMD_RING_TAIL_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_13__CMD_RING_TAIL_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_13__CMD_RING_TAIL_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_13___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_13___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_14 (0x00AAF088) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_14___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_14___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_14__CMD_RING_TAIL_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_14__CMD_RING_TAIL_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_14__CMD_RING_TAIL_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_14___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_14___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_15 (0x00AAF08C) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_15___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_15___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_15__CMD_RING_TAIL_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_15__CMD_RING_TAIL_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_15__CMD_RING_TAIL_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_15___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_15___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_16 (0x00AAF090) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_16___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_16___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_16__CMD_RING_TAIL_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_16__CMD_RING_TAIL_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_16__CMD_RING_TAIL_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_16___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_16___S 0 + +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_17 (0x00AAF094) +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_17___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_17___POR 0x00000000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_17__CMD_RING_TAIL_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_17__CMD_RING_TAIL_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_17__CMD_RING_TAIL_DATA___S 0 +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_17___M 0x0000FFFF +#define WMAC0_HWSCH_R2_SCH_CMD_RING_TAIL_IX_17___S 0 + +#define WMAC0_HWSCH_R2_FES_STATUS_RING_HEAD (0x00AAF0A0) +#define WMAC0_HWSCH_R2_FES_STATUS_RING_HEAD___RWC QCSR_REG_RO +#define WMAC0_HWSCH_R2_FES_STATUS_RING_HEAD___POR 0x00000000 +#define WMAC0_HWSCH_R2_FES_STATUS_RING_HEAD__FES_STATUS_HEAD_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_FES_STATUS_RING_HEAD__FES_STATUS_HEAD_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_FES_STATUS_RING_HEAD__FES_STATUS_HEAD_DATA___S 0 +#define WMAC0_HWSCH_R2_FES_STATUS_RING_HEAD___M 0x0000FFFF +#define WMAC0_HWSCH_R2_FES_STATUS_RING_HEAD___S 0 + +#define WMAC0_HWSCH_R2_FES_STATUS_RING_TAIL (0x00AAF0A4) +#define WMAC0_HWSCH_R2_FES_STATUS_RING_TAIL___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_FES_STATUS_RING_TAIL___POR 0x00000000 +#define WMAC0_HWSCH_R2_FES_STATUS_RING_TAIL__FES_STATUS_TAIL_DATA___POR 0x0000 +#define WMAC0_HWSCH_R2_FES_STATUS_RING_TAIL__FES_STATUS_TAIL_DATA___M 0x0000FFFF +#define WMAC0_HWSCH_R2_FES_STATUS_RING_TAIL__FES_STATUS_TAIL_DATA___S 0 +#define WMAC0_HWSCH_R2_FES_STATUS_RING_TAIL___M 0x0000FFFF +#define WMAC0_HWSCH_R2_FES_STATUS_RING_TAIL___S 0 + +#define WMAC0_HWSCH_R2_CMD_STATUS_RING_HP (0x00AAF0A8) +#define WMAC0_HWSCH_R2_CMD_STATUS_RING_HP___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_CMD_STATUS_RING_HP___POR 0x00000000 +#define WMAC0_HWSCH_R2_CMD_STATUS_RING_HP__HEAD_PTR___POR 0x0000 +#define WMAC0_HWSCH_R2_CMD_STATUS_RING_HP__HEAD_PTR___M 0x0000FFFF +#define WMAC0_HWSCH_R2_CMD_STATUS_RING_HP__HEAD_PTR___S 0 +#define WMAC0_HWSCH_R2_CMD_STATUS_RING_HP___M 0x0000FFFF +#define WMAC0_HWSCH_R2_CMD_STATUS_RING_HP___S 0 + +#define WMAC0_HWSCH_R2_CMD_STATUS_RING_TP (0x00AAF0AC) +#define WMAC0_HWSCH_R2_CMD_STATUS_RING_TP___RWC QCSR_REG_RW +#define WMAC0_HWSCH_R2_CMD_STATUS_RING_TP___POR 0x00000000 +#define WMAC0_HWSCH_R2_CMD_STATUS_RING_TP__TAIL_PTR___POR 0x0000 +#define WMAC0_HWSCH_R2_CMD_STATUS_RING_TP__TAIL_PTR___M 0x0000FFFF +#define WMAC0_HWSCH_R2_CMD_STATUS_RING_TP__TAIL_PTR___S 0 +#define WMAC0_HWSCH_R2_CMD_STATUS_RING_TP___M 0x0000FFFF +#define WMAC0_HWSCH_R2_CMD_STATUS_RING_TP___S 0 + +#define WMAC0_MXI_R0_CLOCK_GATE_DISABLE (0x00AB0000) +#define WMAC0_MXI_R0_CLOCK_GATE_DISABLE___RWC QCSR_REG_RW +#define WMAC0_MXI_R0_CLOCK_GATE_DISABLE___POR 0x00000000 +#define WMAC0_MXI_R0_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___POR 0x0 +#define WMAC0_MXI_R0_CLOCK_GATE_DISABLE__WR_PERF_CNT_1___POR 0x0 +#define WMAC0_MXI_R0_CLOCK_GATE_DISABLE__WR_PERF_CNT_0___POR 0x0 +#define WMAC0_MXI_R0_CLOCK_GATE_DISABLE__RD_PERF_CNT_3___POR 0x0 +#define WMAC0_MXI_R0_CLOCK_GATE_DISABLE__RD_PERF_CNT_2___POR 0x0 +#define WMAC0_MXI_R0_CLOCK_GATE_DISABLE__RD_PERF_CNT_1___POR 0x0 +#define WMAC0_MXI_R0_CLOCK_GATE_DISABLE__RD_PERF_CNT_0___POR 0x0 +#define WMAC0_MXI_R0_CLOCK_GATE_DISABLE__UNUSED___POR 0x0 +#define WMAC0_MXI_R0_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___M 0x80000000 +#define WMAC0_MXI_R0_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___S 31 +#define WMAC0_MXI_R0_CLOCK_GATE_DISABLE__WR_PERF_CNT_1___M 0x00000040 +#define WMAC0_MXI_R0_CLOCK_GATE_DISABLE__WR_PERF_CNT_1___S 6 +#define WMAC0_MXI_R0_CLOCK_GATE_DISABLE__WR_PERF_CNT_0___M 0x00000020 +#define WMAC0_MXI_R0_CLOCK_GATE_DISABLE__WR_PERF_CNT_0___S 5 +#define WMAC0_MXI_R0_CLOCK_GATE_DISABLE__RD_PERF_CNT_3___M 0x00000010 +#define WMAC0_MXI_R0_CLOCK_GATE_DISABLE__RD_PERF_CNT_3___S 4 +#define WMAC0_MXI_R0_CLOCK_GATE_DISABLE__RD_PERF_CNT_2___M 0x00000008 +#define WMAC0_MXI_R0_CLOCK_GATE_DISABLE__RD_PERF_CNT_2___S 3 +#define WMAC0_MXI_R0_CLOCK_GATE_DISABLE__RD_PERF_CNT_1___M 0x00000004 +#define WMAC0_MXI_R0_CLOCK_GATE_DISABLE__RD_PERF_CNT_1___S 2 +#define WMAC0_MXI_R0_CLOCK_GATE_DISABLE__RD_PERF_CNT_0___M 0x00000002 +#define WMAC0_MXI_R0_CLOCK_GATE_DISABLE__RD_PERF_CNT_0___S 1 +#define WMAC0_MXI_R0_CLOCK_GATE_DISABLE__UNUSED___M 0x00000001 +#define WMAC0_MXI_R0_CLOCK_GATE_DISABLE__UNUSED___S 0 +#define WMAC0_MXI_R0_CLOCK_GATE_DISABLE___M 0x8000007F +#define WMAC0_MXI_R0_CLOCK_GATE_DISABLE___S 0 + +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_0 (0x00AB0004) +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_0___RWC QCSR_REG_RW +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_0___POR 0x00000000 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_0__WINDOW_SIZE___POR 0x0 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_0__RESET_CNT___POR 0x0 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_0__CNTR_EN___POR 0x0 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_0__ID_BITMAP___POR 0x0000000 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_0__WINDOW_SIZE___M 0x38000000 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_0__WINDOW_SIZE___S 27 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_0__RESET_CNT___M 0x04000000 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_0__RESET_CNT___S 26 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_0__CNTR_EN___M 0x02000000 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_0__CNTR_EN___S 25 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_0__ID_BITMAP___M 0x01FFFFFF +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_0__ID_BITMAP___S 0 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_0___M 0x3FFFFFFF +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_0___S 0 + +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_0 (0x00AB0008) +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_0___RWC QCSR_REG_RO +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_0___POR 0x00000000 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_0__VALUE___POR 0x00000000 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_0__VALUE___M 0xFFFFFFFF +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_0__VALUE___S 0 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_0___M 0xFFFFFFFF +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_0___S 0 + +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_1 (0x00AB000C) +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_1___RWC QCSR_REG_RW +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_1___POR 0x00000000 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_1__WINDOW_SIZE___POR 0x0 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_1__RESET_CNT___POR 0x0 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_1__CNTR_EN___POR 0x0 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_1__ID_BITMAP___POR 0x0000000 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_1__WINDOW_SIZE___M 0x38000000 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_1__WINDOW_SIZE___S 27 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_1__RESET_CNT___M 0x04000000 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_1__RESET_CNT___S 26 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_1__CNTR_EN___M 0x02000000 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_1__CNTR_EN___S 25 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_1__ID_BITMAP___M 0x01FFFFFF +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_1__ID_BITMAP___S 0 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_1___M 0x3FFFFFFF +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_1___S 0 + +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_1 (0x00AB0010) +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_1___RWC QCSR_REG_RO +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_1___POR 0x00000000 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_1__VALUE___POR 0x00000000 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_1__VALUE___M 0xFFFFFFFF +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_1__VALUE___S 0 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_1___M 0xFFFFFFFF +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_1___S 0 + +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_2 (0x00AB0014) +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_2___RWC QCSR_REG_RW +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_2___POR 0x00000000 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_2__WINDOW_SIZE___POR 0x0 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_2__RESET_CNT___POR 0x0 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_2__CNTR_EN___POR 0x0 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_2__ID_BITMAP___POR 0x0000000 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_2__WINDOW_SIZE___M 0x38000000 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_2__WINDOW_SIZE___S 27 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_2__RESET_CNT___M 0x04000000 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_2__RESET_CNT___S 26 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_2__CNTR_EN___M 0x02000000 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_2__CNTR_EN___S 25 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_2__ID_BITMAP___M 0x01FFFFFF +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_2__ID_BITMAP___S 0 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_2___M 0x3FFFFFFF +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_2___S 0 + +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_2 (0x00AB0018) +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_2___RWC QCSR_REG_RO +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_2___POR 0x00000000 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_2__VALUE___POR 0x00000000 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_2__VALUE___M 0xFFFFFFFF +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_2__VALUE___S 0 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_2___M 0xFFFFFFFF +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_2___S 0 + +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_3 (0x00AB001C) +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_3___RWC QCSR_REG_RW +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_3___POR 0x00000000 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_3__WINDOW_SIZE___POR 0x0 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_3__RESET_CNT___POR 0x0 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_3__CNTR_EN___POR 0x0 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_3__ID_BITMAP___POR 0x0000000 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_3__WINDOW_SIZE___M 0x38000000 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_3__WINDOW_SIZE___S 27 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_3__RESET_CNT___M 0x04000000 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_3__RESET_CNT___S 26 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_3__CNTR_EN___M 0x02000000 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_3__CNTR_EN___S 25 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_3__ID_BITMAP___M 0x01FFFFFF +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_3__ID_BITMAP___S 0 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_3___M 0x3FFFFFFF +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_CFG_3___S 0 + +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_3 (0x00AB0020) +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_3___RWC QCSR_REG_RO +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_3___POR 0x00000000 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_3__VALUE___POR 0x00000000 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_3__VALUE___M 0xFFFFFFFF +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_3__VALUE___S 0 +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_3___M 0xFFFFFFFF +#define WMAC0_MXI_R0_MXI_RD_PERF_CNTR_VAL_3___S 0 + +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_0 (0x00AB0024) +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_0___RWC QCSR_REG_RW +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_0___POR 0x00000000 +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_0__WINDOW_SIZE___POR 0x0 +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_0__RESET_CNT___POR 0x0 +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_0__CNTR_EN___POR 0x0 +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_0__WINDOW_SIZE___M 0x00070000 +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_0__WINDOW_SIZE___S 16 +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_0__RESET_CNT___M 0x00000100 +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_0__RESET_CNT___S 8 +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_0__CNTR_EN___M 0x00000001 +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_0__CNTR_EN___S 0 +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_0___M 0x00070101 +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_0___S 0 + +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0 (0x00AB0028) +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0___RWC QCSR_REG_RW +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0___POR 0x00000000 +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0__ID_BITMAP___POR 0x00000000 +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0__ID_BITMAP___M 0x3FFFFFFF +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0__ID_BITMAP___S 0 +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0___M 0x3FFFFFFF +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_0___S 0 + +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_VAL_0 (0x00AB002C) +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_VAL_0___RWC QCSR_REG_RO +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_VAL_0___POR 0x00000000 +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_VAL_0__VALUE___POR 0x00000000 +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_VAL_0__VALUE___M 0xFFFFFFFF +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_VAL_0__VALUE___S 0 +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_VAL_0___M 0xFFFFFFFF +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_VAL_0___S 0 + +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_1 (0x00AB0030) +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_1___RWC QCSR_REG_RW +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_1___POR 0x00000000 +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_1__WINDOW_SIZE___POR 0x0 +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_1__RESET_CNT___POR 0x0 +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_1__CNTR_EN___POR 0x0 +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_1__WINDOW_SIZE___M 0x00070000 +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_1__WINDOW_SIZE___S 16 +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_1__RESET_CNT___M 0x00000100 +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_1__RESET_CNT___S 8 +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_1__CNTR_EN___M 0x00000001 +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_1__CNTR_EN___S 0 +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_1___M 0x00070101 +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_CFG_1___S 0 + +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1 (0x00AB0034) +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1___RWC QCSR_REG_RW +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1___POR 0x00000000 +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1__ID_BITMAP___POR 0x00000000 +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1__ID_BITMAP___M 0x3FFFFFFF +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1__ID_BITMAP___S 0 +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1___M 0x3FFFFFFF +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_ID_CFG_1___S 0 + +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_VAL_1 (0x00AB0038) +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_VAL_1___RWC QCSR_REG_RO +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_VAL_1___POR 0x00000000 +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_VAL_1__VALUE___POR 0x00000000 +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_VAL_1__VALUE___M 0xFFFFFFFF +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_VAL_1__VALUE___S 0 +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_VAL_1___M 0xFFFFFFFF +#define WMAC0_MXI_R0_MXI_WR_PERF_CNTR_VAL_1___S 0 + +#define WMAC0_MXI_R0_MXI_S_PARE_REGISTER (0x00AB003C) +#define WMAC0_MXI_R0_MXI_S_PARE_REGISTER___RWC QCSR_REG_RW +#define WMAC0_MXI_R0_MXI_S_PARE_REGISTER___POR 0x00000000 +#define WMAC0_MXI_R0_MXI_S_PARE_REGISTER__VAL___POR 0x00000000 +#define WMAC0_MXI_R0_MXI_S_PARE_REGISTER__VAL___M 0xFFFFFFFF +#define WMAC0_MXI_R0_MXI_S_PARE_REGISTER__VAL___S 0 +#define WMAC0_MXI_R0_MXI_S_PARE_REGISTER___M 0xFFFFFFFF +#define WMAC0_MXI_R0_MXI_S_PARE_REGISTER___S 0 + +#define WMAC0_MXI_R0_WMAC_GXI_TESTBUS_LOWER (0x00AB0040) +#define WMAC0_MXI_R0_WMAC_GXI_TESTBUS_LOWER___RWC QCSR_REG_RO +#define WMAC0_MXI_R0_WMAC_GXI_TESTBUS_LOWER___POR 0x00000000 +#define WMAC0_MXI_R0_WMAC_GXI_TESTBUS_LOWER__VALUE___POR 0x00000000 +#define WMAC0_MXI_R0_WMAC_GXI_TESTBUS_LOWER__VALUE___M 0xFFFFFFFF +#define WMAC0_MXI_R0_WMAC_GXI_TESTBUS_LOWER__VALUE___S 0 +#define WMAC0_MXI_R0_WMAC_GXI_TESTBUS_LOWER___M 0xFFFFFFFF +#define WMAC0_MXI_R0_WMAC_GXI_TESTBUS_LOWER___S 0 + +#define WMAC0_MXI_R0_WMAC_GXI_TESTBUS_UPPER (0x00AB0044) +#define WMAC0_MXI_R0_WMAC_GXI_TESTBUS_UPPER___RWC QCSR_REG_RO +#define WMAC0_MXI_R0_WMAC_GXI_TESTBUS_UPPER___POR 0x00000000 +#define WMAC0_MXI_R0_WMAC_GXI_TESTBUS_UPPER__VALUE___POR 0x00 +#define WMAC0_MXI_R0_WMAC_GXI_TESTBUS_UPPER__VALUE___M 0x000000FF +#define WMAC0_MXI_R0_WMAC_GXI_TESTBUS_UPPER__VALUE___S 0 +#define WMAC0_MXI_R0_WMAC_GXI_TESTBUS_UPPER___M 0x000000FF +#define WMAC0_MXI_R0_WMAC_GXI_TESTBUS_UPPER___S 0 + +#define WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0 (0x00AB0048) +#define WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0___RWC QCSR_REG_RO +#define WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0___POR 0x00000211 +#define WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0__SM_STATE_RD_ADDR___POR 0x1 +#define WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0__SM_STATE_WR_ADDR___POR 0x01 +#define WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0__SM_STATE_WR_DATA___POR 0x1 +#define WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0__SM_STATE_RD_ADDR___M 0x00000E00 +#define WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0__SM_STATE_RD_ADDR___S 9 +#define WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0__SM_STATE_WR_ADDR___M 0x000001F0 +#define WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0__SM_STATE_WR_ADDR___S 4 +#define WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0__SM_STATE_WR_DATA___M 0x0000000F +#define WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0__SM_STATE_WR_DATA___S 0 +#define WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0___M 0x00000FFF +#define WMAC0_MXI_R0_WMAC_GXI_SM_STATES_IX_0___S 0 + +#define WMAC0_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK (0x00AB004C) +#define WMAC0_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK___RWC QCSR_REG_RW +#define WMAC0_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK___POR 0x00000000 +#define WMAC0_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0 +#define WMAC0_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001 +#define WMAC0_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S 0 +#define WMAC0_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK___M 0x00000001 +#define WMAC0_MXI_R0_WMAC_GXI_END_OF_TEST_CHECK___S 0 + +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE (0x00AB0050) +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE___RWC QCSR_REG_RW +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE___POR 0x00000000 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___POR 0x0 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__SPARE___POR 0x0 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WDOG_CTR___POR 0x0 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__RD_FIFO___POR 0x0 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_DATA_FIFO___POR 0x0 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_ADDR_FIFO___POR 0x0 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__RD_AXI_MAS___POR 0x0 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_DATA_AXI_MAS___POR 0x0 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_ADDR_AXI_MAS___POR 0x0 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_DATA_CMD___POR 0x0 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_ADDR_CMD___POR 0x0 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__RD_CMD___POR 0x0 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__CORE___POR 0x0 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___M 0x80000000 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__CLOCK_GATE_EXTEND___S 31 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__SPARE___M 0x00000800 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__SPARE___S 11 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WDOG_CTR___M 0x00000400 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WDOG_CTR___S 10 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__RD_FIFO___M 0x00000200 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__RD_FIFO___S 9 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_DATA_FIFO___M 0x00000100 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_DATA_FIFO___S 8 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_ADDR_FIFO___M 0x00000080 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_ADDR_FIFO___S 7 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__RD_AXI_MAS___M 0x00000040 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__RD_AXI_MAS___S 6 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_DATA_AXI_MAS___M 0x00000020 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_DATA_AXI_MAS___S 5 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_ADDR_AXI_MAS___M 0x00000010 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_ADDR_AXI_MAS___S 4 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_DATA_CMD___M 0x00000008 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_DATA_CMD___S 3 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_ADDR_CMD___M 0x00000004 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__WR_ADDR_CMD___S 2 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__RD_CMD___M 0x00000002 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__RD_CMD___S 1 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__CORE___M 0x00000001 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE__CORE___S 0 +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE___M 0x80000FFF +#define WMAC0_MXI_R0_WMAC_GXI_CLOCK_GATE_DISABLE___S 0 + +#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS (0x00AB0054) +#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS___RWC QCSR_REG_RO +#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS___POR 0x00000000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS__GXI_WR_LAST_ERR_INT___POR 0x0 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS__GXI_AXI_WR_ERR_INT___POR 0x0 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS__GXI_AXI_RD_ERR_INT___POR 0x0 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS__GXI_WDTIMEOUT_INT___POR 0x0 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS__GXI_WR_LAST_ERR_INT___M 0x01000000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS__GXI_WR_LAST_ERR_INT___S 24 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS__GXI_AXI_WR_ERR_INT___M 0x00010000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS__GXI_AXI_WR_ERR_INT___S 16 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS__GXI_AXI_RD_ERR_INT___M 0x00000100 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS__GXI_AXI_RD_ERR_INT___S 8 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS__GXI_WDTIMEOUT_INT___M 0x00000001 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS__GXI_WDTIMEOUT_INT___S 0 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS___M 0x01010101 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_INTS___S 0 + +#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS (0x00AB0058) +#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS___RWC QCSR_REG_RO +#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS___POR 0x00000000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS__AXI_WR_LAST_ERR_PORT___POR 0x00 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS__AXI_WR_ERR_PORT___POR 0x00 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS__AXI_RD_ERR_PORT___POR 0x00 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS__AXI_WR_LAST_ERR_PORT___M 0x003F0000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS__AXI_WR_LAST_ERR_PORT___S 16 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS__AXI_WR_ERR_PORT___M 0x00003F00 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS__AXI_WR_ERR_PORT___S 8 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS__AXI_RD_ERR_PORT___M 0x0000003F +#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS__AXI_RD_ERR_PORT___S 0 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS___M 0x003F3F3F +#define WMAC0_MXI_R0_WMAC_GXI_GXI_ERR_STATS___S 0 + +#define WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL (0x00AB005C) +#define WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL___RWC QCSR_REG_RW +#define WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL___POR 0x00000000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READ_DATA___POR 0x00 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITE_DATA___POR 0x00 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READS___POR 0x00 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITES___POR 0x00 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READ_DATA___M 0xFF000000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READ_DATA___S 24 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITE_DATA___M 0x00FF0000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITE_DATA___S 16 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READS___M 0x00003F00 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_READS___S 8 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITES___M 0x0000003F +#define WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL__GXI_DEFAULT_MAX_PENDING_WRITES___S 0 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL___M 0xFFFF3F3F +#define WMAC0_MXI_R0_WMAC_GXI_GXI_DEFAULT_CONTROL___S 0 + +#define WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL (0x00AB0060) +#define WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL___RWC QCSR_REG_RW +#define WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL___POR 0x00000000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READ_DATA___POR 0x00 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITE_DATA___POR 0x00 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READS___POR 0x00 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITES___POR 0x00 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READ_DATA___M 0xFF000000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READ_DATA___S 24 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITE_DATA___M 0x00FF0000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITE_DATA___S 16 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READS___M 0x00003F00 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_READS___S 8 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITES___M 0x0000003F +#define WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL__GXI_REDUCED_MAX_PENDING_WRITES___S 0 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL___M 0xFFFF3F3F +#define WMAC0_MXI_R0_WMAC_GXI_GXI_REDUCED_CONTROL___S 0 + +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL (0x00AB0064) +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL___RWC QCSR_REG_RW +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL___POR 0x00240000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_DELAYED_RD_FLUSH___POR 0x0 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_DELAYED_WR_FLUSH___POR 0x0 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_DISABLE_WR_PREFIL___POR 0x0 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_MAX_WR_BOUNDARY_SPLIT___POR 0x0 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_MAX_RD_BOUNDARY_SPLIT___POR 0x0 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_WRITE_BURST_SIZE___POR 0x2 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_READ_BURST_SIZE___POR 0x2 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_READ_ISSUE_THRESHOLD___POR 0x00 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_WRITE_PREFETCH_THRESHOLD___POR 0x00 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_CLEAR_STATS___POR 0x0 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_DELAYED_RD_FLUSH___M 0x08000000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_DELAYED_RD_FLUSH___S 27 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_DELAYED_WR_FLUSH___M 0x04000000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_DELAYED_WR_FLUSH___S 26 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_DISABLE_WR_PREFIL___M 0x02000000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_DISABLE_WR_PREFIL___S 25 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_MAX_WR_BOUNDARY_SPLIT___M 0x01000000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_MAX_WR_BOUNDARY_SPLIT___S 24 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_MAX_RD_BOUNDARY_SPLIT___M 0x00800000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_MAX_RD_BOUNDARY_SPLIT___S 23 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_WRITE_BURST_SIZE___M 0x00700000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_WRITE_BURST_SIZE___S 20 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_READ_BURST_SIZE___M 0x000E0000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_READ_BURST_SIZE___S 17 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_READ_ISSUE_THRESHOLD___M 0x0001FE00 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_READ_ISSUE_THRESHOLD___S 9 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_WRITE_PREFETCH_THRESHOLD___M 0x000001FE +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_WRITE_PREFETCH_THRESHOLD___S 1 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_CLEAR_STATS___M 0x00000001 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL__GXI_CLEAR_STATS___S 0 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL___M 0x0FFFFFFF +#define WMAC0_MXI_R0_WMAC_GXI_GXI_MISC_CONTROL___S 0 + +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_CONTROL (0x00AB0068) +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_CONTROL___RWC QCSR_REG_RW +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_CONTROL___POR 0x00FF0000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_CONTROL__GXI_WDOG_LIMIT___POR 0x00FF +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_CONTROL__GXI_WDOG_DISABLE___POR 0x0 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_CONTROL__GXI_WDOG_LIMIT___M 0xFFFF0000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_CONTROL__GXI_WDOG_LIMIT___S 16 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_CONTROL__GXI_WDOG_DISABLE___M 0x00000001 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_CONTROL__GXI_WDOG_DISABLE___S 0 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_CONTROL___M 0xFFFF0001 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_CONTROL___S 0 + +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_STATUS (0x00AB006C) +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_STATUS___RWC QCSR_REG_RO +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_STATUS___POR 0x00000000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_STATUS__GXI_WDOG_STATUS___POR 0x0000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_STATUS__GXI_WDOG_STATUS___M 0x0000FFFF +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_STATUS__GXI_WDOG_STATUS___S 0 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_STATUS___M 0x0000FFFF +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WDOG_STATUS___S 0 + +#define WMAC0_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS (0x00AB0070) +#define WMAC0_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS___RWC QCSR_REG_RO +#define WMAC0_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS___POR 0x00000000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS__GXI_READ_IDLE_CNT___POR 0x0000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS__GXI_WRITE_IDLE_CNT___POR 0x0000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS__GXI_READ_IDLE_CNT___M 0xFFFF0000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS__GXI_READ_IDLE_CNT___S 16 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS__GXI_WRITE_IDLE_CNT___M 0x0000FFFF +#define WMAC0_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS__GXI_WRITE_IDLE_CNT___S 0 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS___M 0xFFFFFFFF +#define WMAC0_MXI_R0_WMAC_GXI_GXI_IDLE_COUNTERS___S 0 + +#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL (0x00AB0074) +#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL___RWC QCSR_REG_RW +#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL___POR 0x00000000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_RANGE___POR 0x0 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_EN___POR 0x0 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_MIN___POR 0x0000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_RANGE___M 0x000E0000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_RANGE___S 17 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_EN___M 0x00010000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_EN___S 16 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_MIN___M 0x0000FFFF +#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL__AXI_LATENCY_MIN___S 0 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL___M 0x000FFFFF +#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_LATENCY_CTRL___S 0 + +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL (0x00AB0078) +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL___RWC QCSR_REG_RW +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL___POR 0x00000000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_RANGE___POR 0x0 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_EN___POR 0x0 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_MIN___POR 0x0000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_RANGE___M 0x000E0000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_RANGE___S 17 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_EN___M 0x00010000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_EN___S 16 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_MIN___M 0x0000FFFF +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL__AXI_LATENCY_MIN___S 0 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL___M 0x000FFFFF +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_LATENCY_CTRL___S 0 + +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0 (0x00AB007C) +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___RWC QCSR_REG_RW +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___POR 0x00000000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0__VALUE___POR 0x00000000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0__VALUE___M 0xFFFFFFFF +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0__VALUE___S 0 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___M 0xFFFFFFFF +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0___S 0 + +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1 (0x00AB0080) +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___RWC QCSR_REG_RW +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___POR 0x00000000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1__VALUE___POR 0x00000000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1__VALUE___M 0xFFFFFFFF +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1__VALUE___S 0 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___M 0xFFFFFFFF +#define WMAC0_MXI_R0_WMAC_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1___S 0 + +#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0 (0x00AB0084) +#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___RWC QCSR_REG_RW +#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___POR 0x00000000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0__VALUE___POR 0x00000000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0__VALUE___M 0xFFFFFFFF +#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0__VALUE___S 0 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___M 0xFFFFFFFF +#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0___S 0 + +#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1 (0x00AB0088) +#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___RWC QCSR_REG_RW +#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___POR 0x00000000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1__VALUE___POR 0x00000000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1__VALUE___M 0xFFFFFFFF +#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1__VALUE___S 0 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___M 0xFFFFFFFF +#define WMAC0_MXI_R0_WMAC_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1___S 0 + +#define WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL (0x00AB008C) +#define WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL___RWC QCSR_REG_RW +#define WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL___POR 0x00000000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_EN___POR 0x0 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_CNT___POR 0x00 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_EN___POR 0x0 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_CNT___POR 0x00 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_EN___M 0x00008000 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_EN___S 15 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_CNT___M 0x00001F00 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL__WR_OVR_CNT___S 8 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_EN___M 0x00000080 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_EN___S 7 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_CNT___M 0x0000001F +#define WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL__RD_OVR_CNT___S 0 +#define WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL___M 0x00009F9F +#define WMAC0_MXI_R0_WMAC_GXI_GXI_AXI_OUTSANDING_CTL___S 0 + +#define WMAC0_MXI_R1_TESTBUS_CTRL (0x00AB1000) +#define WMAC0_MXI_R1_TESTBUS_CTRL___RWC QCSR_REG_RW +#define WMAC0_MXI_R1_TESTBUS_CTRL___POR 0x00000000 +#define WMAC0_MXI_R1_TESTBUS_CTRL__HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE___POR 0x0 +#define WMAC0_MXI_R1_TESTBUS_CTRL__TESTBUS_SELECT___POR 0x00 +#define WMAC0_MXI_R1_TESTBUS_CTRL__HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE___M 0x00010000 +#define WMAC0_MXI_R1_TESTBUS_CTRL__HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE___S 16 +#define WMAC0_MXI_R1_TESTBUS_CTRL__TESTBUS_SELECT___M 0x0000001F +#define WMAC0_MXI_R1_TESTBUS_CTRL__TESTBUS_SELECT___S 0 +#define WMAC0_MXI_R1_TESTBUS_CTRL___M 0x0001001F +#define WMAC0_MXI_R1_TESTBUS_CTRL___S 0 + +#define WMAC0_MXI_R1_EVENTMASK_IX_0 (0x00AB1004) +#define WMAC0_MXI_R1_EVENTMASK_IX_0___RWC QCSR_REG_RW +#define WMAC0_MXI_R1_EVENTMASK_IX_0___POR 0xFFFFFFFF +#define WMAC0_MXI_R1_EVENTMASK_IX_0__MASK___POR 0xFFFFFFFF +#define WMAC0_MXI_R1_EVENTMASK_IX_0__MASK___M 0xFFFFFFFF +#define WMAC0_MXI_R1_EVENTMASK_IX_0__MASK___S 0 +#define WMAC0_MXI_R1_EVENTMASK_IX_0___M 0xFFFFFFFF +#define WMAC0_MXI_R1_EVENTMASK_IX_0___S 0 + +#define WMAC0_MXI_R1_EVENTMASK_IX_1 (0x00AB1008) +#define WMAC0_MXI_R1_EVENTMASK_IX_1___RWC QCSR_REG_RW +#define WMAC0_MXI_R1_EVENTMASK_IX_1___POR 0xFFFFFFFF +#define WMAC0_MXI_R1_EVENTMASK_IX_1__MASK___POR 0xFFFFFFFF +#define WMAC0_MXI_R1_EVENTMASK_IX_1__MASK___M 0xFFFFFFFF +#define WMAC0_MXI_R1_EVENTMASK_IX_1__MASK___S 0 +#define WMAC0_MXI_R1_EVENTMASK_IX_1___M 0xFFFFFFFF +#define WMAC0_MXI_R1_EVENTMASK_IX_1___S 0 + +#define WMAC0_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL (0x00AB100C) +#define WMAC0_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL___RWC QCSR_REG_RW +#define WMAC0_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL___POR 0x7FFE0002 +#define WMAC0_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___POR 0x3FFF +#define WMAC0_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___POR 0x0000 +#define WMAC0_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___POR 0x1 +#define WMAC0_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___POR 0x0 +#define WMAC0_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___M 0xFFFE0000 +#define WMAC0_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_END___S 17 +#define WMAC0_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___M 0x0001FFFC +#define WMAC0_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL__ADDRESS_RANGE_START___S 2 +#define WMAC0_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___M 0x00000002 +#define WMAC0_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL__WRITE_ACCESS_REPORT_ENABLE___S 1 +#define WMAC0_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___M 0x00000001 +#define WMAC0_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL__READ_ACCESS_REPORT_ENABLE___S 0 +#define WMAC0_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL___M 0xFFFFFFFF +#define WMAC0_MXI_R1_REG_ACCESS_EVENT_GEN_CTRL___S 0 + +#define WMAC0_MXI_R1_END_OF_TEST_CHECK (0x00AB1010) +#define WMAC0_MXI_R1_END_OF_TEST_CHECK___RWC QCSR_REG_RW +#define WMAC0_MXI_R1_END_OF_TEST_CHECK___POR 0x00000000 +#define WMAC0_MXI_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___POR 0x0 +#define WMAC0_MXI_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___M 0x00000001 +#define WMAC0_MXI_R1_END_OF_TEST_CHECK__END_OF_TEST_SELF_CHECK___S 0 +#define WMAC0_MXI_R1_END_OF_TEST_CHECK___M 0x00000001 +#define WMAC0_MXI_R1_END_OF_TEST_CHECK___S 0 + +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_n(n) (0x00AB3000+0x4*(n)) +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_n_nMIN 0 +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_n_nMAX 9 +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_n_ELEM 10 +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_n___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_n___POR 0x00000010 +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_n__VALUE___POR 0x010 +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_n__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_n__VALUE___S 0 +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_n___M 0x000003FF +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_n___S 0 +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_0 (0x00AB3000) +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_0___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_0__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_0__VALUE___S 0 +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_1 (0x00AB3004) +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_1___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_1__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_1__VALUE___S 0 +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_2 (0x00AB3008) +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_2___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_2__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_2__VALUE___S 0 +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_3 (0x00AB300C) +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_3___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_3__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_3__VALUE___S 0 +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_4 (0x00AB3010) +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_4___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_4__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_4__VALUE___S 0 +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_5 (0x00AB3014) +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_5___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_5__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_5__VALUE___S 0 +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_6 (0x00AB3018) +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_6___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_6__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_6__VALUE___S 0 +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_7 (0x00AB301C) +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_7___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_7__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_7__VALUE___S 0 +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_8 (0x00AB3020) +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_8___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_8__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_8__VALUE___S 0 +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_9 (0x00AB3024) +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_9___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_9__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_MINIMUM_BUFFERS_9__VALUE___S 0 + +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_n(n) (0x00AB3028+0x4*(n)) +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_n_nMIN 0 +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_n_nMAX 9 +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_n_ELEM 10 +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_n___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_n___POR 0x00000190 +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_n__VALUE___POR 0x190 +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_n__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_n__VALUE___S 0 +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_n___M 0x000003FF +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_n___S 0 +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_0 (0x00AB3028) +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_0___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_0__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_0__VALUE___S 0 +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_1 (0x00AB302C) +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_1___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_1__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_1__VALUE___S 0 +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_2 (0x00AB3030) +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_2___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_2__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_2__VALUE___S 0 +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_3 (0x00AB3034) +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_3___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_3__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_3__VALUE___S 0 +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_4 (0x00AB3038) +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_4___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_4__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_4__VALUE___S 0 +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_5 (0x00AB303C) +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_5___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_5__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_5__VALUE___S 0 +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_6 (0x00AB3040) +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_6___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_6__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_6__VALUE___S 0 +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_7 (0x00AB3044) +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_7___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_7__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_7__VALUE___S 0 +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_8 (0x00AB3048) +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_8___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_8__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_8__VALUE___S 0 +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_9 (0x00AB304C) +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_9___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_9__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_MAXIMUM_BUFFERS_9__VALUE___S 0 + +#define WMAC0_SFM_R0_BUSY_BUFFERS_n(n) (0x00AB3050+0x4*(n)) +#define WMAC0_SFM_R0_BUSY_BUFFERS_n_nMIN 0 +#define WMAC0_SFM_R0_BUSY_BUFFERS_n_nMAX 9 +#define WMAC0_SFM_R0_BUSY_BUFFERS_n_ELEM 10 +#define WMAC0_SFM_R0_BUSY_BUFFERS_n___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_BUSY_BUFFERS_n___POR 0x00000000 +#define WMAC0_SFM_R0_BUSY_BUFFERS_n__VALUE___POR 0x000 +#define WMAC0_SFM_R0_BUSY_BUFFERS_n__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_BUSY_BUFFERS_n__VALUE___S 0 +#define WMAC0_SFM_R0_BUSY_BUFFERS_n___M 0x000003FF +#define WMAC0_SFM_R0_BUSY_BUFFERS_n___S 0 +#define WMAC0_SFM_R0_BUSY_BUFFERS_0 (0x00AB3050) +#define WMAC0_SFM_R0_BUSY_BUFFERS_0___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_BUSY_BUFFERS_0__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_BUSY_BUFFERS_0__VALUE___S 0 +#define WMAC0_SFM_R0_BUSY_BUFFERS_1 (0x00AB3054) +#define WMAC0_SFM_R0_BUSY_BUFFERS_1___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_BUSY_BUFFERS_1__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_BUSY_BUFFERS_1__VALUE___S 0 +#define WMAC0_SFM_R0_BUSY_BUFFERS_2 (0x00AB3058) +#define WMAC0_SFM_R0_BUSY_BUFFERS_2___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_BUSY_BUFFERS_2__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_BUSY_BUFFERS_2__VALUE___S 0 +#define WMAC0_SFM_R0_BUSY_BUFFERS_3 (0x00AB305C) +#define WMAC0_SFM_R0_BUSY_BUFFERS_3___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_BUSY_BUFFERS_3__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_BUSY_BUFFERS_3__VALUE___S 0 +#define WMAC0_SFM_R0_BUSY_BUFFERS_4 (0x00AB3060) +#define WMAC0_SFM_R0_BUSY_BUFFERS_4___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_BUSY_BUFFERS_4__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_BUSY_BUFFERS_4__VALUE___S 0 +#define WMAC0_SFM_R0_BUSY_BUFFERS_5 (0x00AB3064) +#define WMAC0_SFM_R0_BUSY_BUFFERS_5___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_BUSY_BUFFERS_5__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_BUSY_BUFFERS_5__VALUE___S 0 +#define WMAC0_SFM_R0_BUSY_BUFFERS_6 (0x00AB3068) +#define WMAC0_SFM_R0_BUSY_BUFFERS_6___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_BUSY_BUFFERS_6__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_BUSY_BUFFERS_6__VALUE___S 0 +#define WMAC0_SFM_R0_BUSY_BUFFERS_7 (0x00AB306C) +#define WMAC0_SFM_R0_BUSY_BUFFERS_7___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_BUSY_BUFFERS_7__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_BUSY_BUFFERS_7__VALUE___S 0 +#define WMAC0_SFM_R0_BUSY_BUFFERS_8 (0x00AB3070) +#define WMAC0_SFM_R0_BUSY_BUFFERS_8___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_BUSY_BUFFERS_8__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_BUSY_BUFFERS_8__VALUE___S 0 +#define WMAC0_SFM_R0_BUSY_BUFFERS_9 (0x00AB3074) +#define WMAC0_SFM_R0_BUSY_BUFFERS_9___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_BUSY_BUFFERS_9__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_BUSY_BUFFERS_9__VALUE___S 0 + +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_n(n) (0x00AB3078+0x4*(n)) +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_n_nMIN 0 +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_n_nMAX 9 +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_n_ELEM 10 +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_n___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_n___POR 0x00000000 +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_n__VALUE___POR 0x000 +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_n__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_n__VALUE___S 0 +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_n___M 0x000003FF +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_n___S 0 +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_0 (0x00AB3078) +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_0___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_0__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_0__VALUE___S 0 +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_1 (0x00AB307C) +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_1___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_1__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_1__VALUE___S 0 +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_2 (0x00AB3080) +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_2___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_2__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_2__VALUE___S 0 +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_3 (0x00AB3084) +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_3___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_3__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_3__VALUE___S 0 +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_4 (0x00AB3088) +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_4___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_4__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_4__VALUE___S 0 +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_5 (0x00AB308C) +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_5___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_5__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_5__VALUE___S 0 +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_6 (0x00AB3090) +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_6___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_6__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_6__VALUE___S 0 +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_7 (0x00AB3094) +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_7___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_7__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_7__VALUE___S 0 +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_8 (0x00AB3098) +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_8___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_8__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_8__VALUE___S 0 +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_9 (0x00AB309C) +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_9___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_9__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_ALLOCATED_BUFFERS_9__VALUE___S 0 + +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_n(n) (0x00AB30A0+0x4*(n)) +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_n_nMIN 0 +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_n_nMAX 9 +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_n_ELEM 10 +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_n___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_n___POR 0x00000000 +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_n__VALUE___POR 0x000 +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_n__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_n__VALUE___S 0 +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_n___M 0x000003FF +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_n___S 0 +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_0 (0x00AB30A0) +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_0___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_0__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_0__VALUE___S 0 +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_1 (0x00AB30A4) +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_1___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_1__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_1__VALUE___S 0 +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_2 (0x00AB30A8) +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_2___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_2__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_2__VALUE___S 0 +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_3 (0x00AB30AC) +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_3___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_3__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_3__VALUE___S 0 +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_4 (0x00AB30B0) +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_4___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_4__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_4__VALUE___S 0 +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_5 (0x00AB30B4) +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_5___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_5__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_5__VALUE___S 0 +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_6 (0x00AB30B8) +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_6___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_6__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_6__VALUE___S 0 +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_7 (0x00AB30BC) +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_7___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_7__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_7__VALUE___S 0 +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_8 (0x00AB30C0) +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_8___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_8__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_8__VALUE___S 0 +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_9 (0x00AB30C4) +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_9___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_9__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_9__VALUE___S 0 + +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS (0x00AB30C8) +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS___POR 0x00000000 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT9___POR 0x0 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT8___POR 0x0 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT7___POR 0x0 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT6___POR 0x0 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT5___POR 0x0 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT4___POR 0x0 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT3___POR 0x0 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT2___POR 0x0 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT1___POR 0x0 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT0___POR 0x0 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT9___M 0x00000200 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT9___S 9 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT8___M 0x00000100 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT8___S 8 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT7___M 0x00000080 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT7___S 7 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT6___M 0x00000040 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT6___S 6 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT5___M 0x00000020 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT5___S 5 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT4___M 0x00000010 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT4___S 4 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT3___M 0x00000008 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT3___S 3 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT2___M 0x00000004 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT2___S 2 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT1___M 0x00000002 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT1___S 1 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT0___M 0x00000001 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS__CLIENT0___S 0 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS___M 0x000003FF +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS___S 0 + +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE (0x00AB30CC) +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE___POR 0x00000000 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT9___POR 0x0 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT8___POR 0x0 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT7___POR 0x0 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT6___POR 0x0 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT5___POR 0x0 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT4___POR 0x0 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT3___POR 0x0 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT2___POR 0x0 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT1___POR 0x0 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT0___POR 0x0 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT9___M 0x00000200 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT9___S 9 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT8___M 0x00000100 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT8___S 8 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT7___M 0x00000080 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT7___S 7 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT6___M 0x00000040 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT6___S 6 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT5___M 0x00000020 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT5___S 5 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT4___M 0x00000010 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT4___S 4 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT3___M 0x00000008 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT3___S 3 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT2___M 0x00000004 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT2___S 2 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT1___M 0x00000002 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT1___S 1 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT0___M 0x00000001 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE__CLIENT0___S 0 +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE___M 0x000003FF +#define WMAC0_SFM_R0_DEALLOCATE_BUFFERS_DONE___S 0 + +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_POOL (0x00AB30D0) +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_POOL___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_POOL___POR 0x00000100 +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_POOL__VALUE___POR 0x100 +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_POOL__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_POOL__VALUE___S 0 +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_POOL___M 0x000003FF +#define WMAC0_SFM_R0_AVAILABLE_BUFFERS_POOL___S 0 + +#define WMAC0_SFM_R0_HW_INIT (0x00AB30D4) +#define WMAC0_SFM_R0_HW_INIT___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_HW_INIT___POR 0x00000000 +#define WMAC0_SFM_R0_HW_INIT__INITIALIZATION_DONE___POR 0x0 +#define WMAC0_SFM_R0_HW_INIT__INITIALIZE_FREE_POOL___POR 0x0 +#define WMAC0_SFM_R0_HW_INIT__INITIALIZATION_DONE___M 0x00000002 +#define WMAC0_SFM_R0_HW_INIT__INITIALIZATION_DONE___S 1 +#define WMAC0_SFM_R0_HW_INIT__INITIALIZE_FREE_POOL___M 0x00000001 +#define WMAC0_SFM_R0_HW_INIT__INITIALIZE_FREE_POOL___S 0 +#define WMAC0_SFM_R0_HW_INIT___M 0x00000003 +#define WMAC0_SFM_R0_HW_INIT___S 0 + +#define WMAC0_SFM_R0_TOTAL_NUMBER_OF_BUFFERS (0x00AB30D8) +#define WMAC0_SFM_R0_TOTAL_NUMBER_OF_BUFFERS___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_TOTAL_NUMBER_OF_BUFFERS___POR 0x00000320 +#define WMAC0_SFM_R0_TOTAL_NUMBER_OF_BUFFERS__VALUE___POR 0x320 +#define WMAC0_SFM_R0_TOTAL_NUMBER_OF_BUFFERS__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_TOTAL_NUMBER_OF_BUFFERS__VALUE___S 0 +#define WMAC0_SFM_R0_TOTAL_NUMBER_OF_BUFFERS___M 0x000003FF +#define WMAC0_SFM_R0_TOTAL_NUMBER_OF_BUFFERS___S 0 + +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_n(n) (0x00AB30DC+0x4*(n)) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_n_nMIN 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_n_nMAX 2 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_n_ELEM 3 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_n___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_n___POR 0x00000000 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_n__VALUE___POR 0x0000 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_n__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_n__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_n___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_n___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_0 (0x00AB30DC) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_0___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_0__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_0__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_1 (0x00AB30E0) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_1___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_1__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_1__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_2 (0x00AB30E4) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_2___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_2__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT0_2__VALUE___S 0 + +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT1 (0x00AB3178) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT1___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT1___POR 0x00000000 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT1__VALUE___POR 0x0000 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT1__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT1__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT1___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT1___S 0 + +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_n(n) (0x00AB317C+0x4*(n)) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_n_nMIN 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_n_nMAX 2 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_n_ELEM 3 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_n___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_n___POR 0x00000000 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_n__VALUE___POR 0x0000 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_n__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_n__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_n___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_n___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_0 (0x00AB317C) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_0___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_0__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_0__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_1 (0x00AB3180) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_1___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_1__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_1__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_2 (0x00AB3184) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_2___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_2__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT2_2__VALUE___S 0 + +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_n(n) (0x00AB3210+0x4*(n)) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_n_nMIN 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_n_nMAX 2 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_n_ELEM 3 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_n___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_n___POR 0x00000000 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_n__VALUE___POR 0x0000 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_n__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_n__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_n___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_n___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_0 (0x00AB3210) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_0___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_0__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_0__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_1 (0x00AB3214) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_1___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_1__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_1__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_2 (0x00AB3218) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_2___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_2__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT3_2__VALUE___S 0 + +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_n(n) (0x00AB321C+0x4*(n)) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_n_nMIN 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_n_nMAX 25 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_n_ELEM 26 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_n___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_n___POR 0x00000000 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_n__VALUE___POR 0x0000 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_n__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_n__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_n___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_n___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_0 (0x00AB321C) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_0___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_0__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_0__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_1 (0x00AB3220) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_1___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_1__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_1__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_2 (0x00AB3224) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_2___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_2__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_2__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_3 (0x00AB3228) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_3___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_3__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_3__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_4 (0x00AB322C) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_4___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_4__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_4__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_5 (0x00AB3230) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_5___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_5__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_5__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_6 (0x00AB3234) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_6___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_6__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_6__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_7 (0x00AB3238) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_7___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_7__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_7__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_8 (0x00AB323C) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_8___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_8__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_8__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_9 (0x00AB3240) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_9___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_9__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_9__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_10 (0x00AB3244) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_10___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_10__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_10__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_11 (0x00AB3248) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_11___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_11__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_11__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_12 (0x00AB324C) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_12___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_12__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_12__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_13 (0x00AB3250) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_13___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_13__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_13__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_14 (0x00AB3254) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_14___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_14__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_14__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_15 (0x00AB3258) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_15___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_15__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_15__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_16 (0x00AB325C) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_16___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_16__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_16__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_17 (0x00AB3260) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_17___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_17__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_17__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_18 (0x00AB3264) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_18___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_18__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_18__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_19 (0x00AB3268) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_19___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_19__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_19__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_20 (0x00AB326C) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_20___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_20__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_20__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_21 (0x00AB3270) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_21___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_21__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_21__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_22 (0x00AB3274) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_22___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_22__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_22__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_23 (0x00AB3278) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_23___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_23__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_23__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_24 (0x00AB327C) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_24___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_24__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_24__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_25 (0x00AB3280) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_25___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_25__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT4_25__VALUE___S 0 + +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_n(n) (0x00AB3288+0x4*(n)) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_n_nMIN 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_n_nMAX 3 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_n_ELEM 4 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_n___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_n___POR 0x00000000 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_n__VALUE___POR 0x0000 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_n__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_n__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_n___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_n___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_0 (0x00AB3288) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_0___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_0__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_0__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_1 (0x00AB328C) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_1___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_1__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_1__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_2 (0x00AB3290) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_2___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_2__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_2__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_3 (0x00AB3294) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_3___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_3__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT5_3__VALUE___S 0 + +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_n(n) (0x00AB331C+0x4*(n)) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_n_nMIN 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_n_nMAX 2 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_n_ELEM 3 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_n___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_n___POR 0x00000000 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_n__VALUE___POR 0x0000 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_n__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_n__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_n___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_n___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_0 (0x00AB331C) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_0___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_0__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_0__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_1 (0x00AB3320) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_1___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_1__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_1__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_2 (0x00AB3324) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_2___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_2__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT6_2__VALUE___S 0 + +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT7 (0x00AB33B0) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT7___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT7___POR 0x00000000 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT7__VALUE___POR 0x0000 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT7__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT7__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT7___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT7___S 0 + +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT8 (0x00AB33B4) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT8___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT8___POR 0x00000000 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT8__VALUE___POR 0x0000 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT8__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT8__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT8___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT8___S 0 + +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT9 (0x00AB3448) +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT9___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT9___POR 0x00000000 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT9__VALUE___POR 0x0000 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT9__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT9__VALUE___S 0 +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT9___M 0x00007FFF +#define WMAC0_SFM_R0_NUM_DWORDS_USED_CLIENT9___S 0 + +#define WMAC0_SFM_R0_FREE_LIST_DESCRIPTOR (0x00AB344C) +#define WMAC0_SFM_R0_FREE_LIST_DESCRIPTOR___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_FREE_LIST_DESCRIPTOR___POR 0x00000000 +#define WMAC0_SFM_R0_FREE_LIST_DESCRIPTOR__HEAD___POR 0x0000 +#define WMAC0_SFM_R0_FREE_LIST_DESCRIPTOR__TAIL___POR 0x0000 +#define WMAC0_SFM_R0_FREE_LIST_DESCRIPTOR__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_FREE_LIST_DESCRIPTOR__HEAD___S 16 +#define WMAC0_SFM_R0_FREE_LIST_DESCRIPTOR__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_FREE_LIST_DESCRIPTOR__TAIL___S 0 +#define WMAC0_SFM_R0_FREE_LIST_DESCRIPTOR___M 0xFFFFFFFF +#define WMAC0_SFM_R0_FREE_LIST_DESCRIPTOR___S 0 + +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_n(n) (0x00AB3450+0x4*(n)) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_n_nMIN 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_n_nMAX 2 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_n_ELEM 3 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_n___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_n___POR 0x00000000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_n__HEAD___POR 0x0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_n__TAIL___POR 0x0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_n__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_n__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_n__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_n__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_n___M 0xFFFFFFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_n___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_0 (0x00AB3450) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_0___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_0__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_0__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_0__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_0__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_1 (0x00AB3454) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_1___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_1__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_1__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_1__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_1__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_2 (0x00AB3458) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_2___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_2__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_2__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_2__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT2_2__TAIL___S 0 + +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_n(n) (0x00AB34E4+0x4*(n)) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_n_nMIN 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_n_nMAX 2 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_n_ELEM 3 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_n___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_n___POR 0x00000000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_n__NEXT_HEAD___POR 0x0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_n__SAVED_HEAD___POR 0x0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_n__NEXT_HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_n__NEXT_HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_n__SAVED_HEAD___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_n__SAVED_HEAD___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_n___M 0xFFFFFFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_n___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_0 (0x00AB34E4) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_0___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_0__NEXT_HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_0__NEXT_HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_0__SAVED_HEAD___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_0__SAVED_HEAD___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_1 (0x00AB34E8) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_1___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_1__NEXT_HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_1__NEXT_HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_1__SAVED_HEAD___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_1__SAVED_HEAD___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_2 (0x00AB34EC) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_2___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_2__NEXT_HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_2__NEXT_HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_2__SAVED_HEAD___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT2_2__SAVED_HEAD___S 0 + +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_n(n) (0x00AB3578+0x4*(n)) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_n_nMIN 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_n_nMAX 2 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_n_ELEM 3 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_n___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_n___POR 0x00000000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_n__HEAD___POR 0x0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_n__TAIL___POR 0x0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_n__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_n__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_n__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_n__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_n___M 0xFFFFFFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_n___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_0 (0x00AB3578) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_0___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_0__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_0__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_0__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_0__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_1 (0x00AB357C) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_1___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_1__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_1__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_1__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_1__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_2 (0x00AB3580) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_2___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_2__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_2__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_2__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_LOWER_CLIENT3_2__TAIL___S 0 + +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_n(n) (0x00AB3584+0x4*(n)) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_n_nMIN 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_n_nMAX 2 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_n_ELEM 3 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_n___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_n___POR 0x00000000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_n__NEXT_HEAD___POR 0x0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_n__SAVED_HEAD___POR 0x0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_n__NEXT_HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_n__NEXT_HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_n__SAVED_HEAD___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_n__SAVED_HEAD___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_n___M 0xFFFFFFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_n___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_0 (0x00AB3584) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_0___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_0__NEXT_HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_0__NEXT_HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_0__SAVED_HEAD___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_0__SAVED_HEAD___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_1 (0x00AB3588) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_1___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_1__NEXT_HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_1__NEXT_HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_1__SAVED_HEAD___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_1__SAVED_HEAD___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_2 (0x00AB358C) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_2___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_2__NEXT_HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_2__NEXT_HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_2__SAVED_HEAD___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_UPPER_CLIENT3_2__SAVED_HEAD___S 0 + +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_n(n) (0x00AB3590+0x4*(n)) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_n_nMIN 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_n_nMAX 2 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_n_ELEM 3 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_n___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_n___POR 0x00000000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_n__HEAD___POR 0x0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_n__TAIL___POR 0x0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_n__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_n__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_n__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_n__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_n___M 0xFFFFFFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_n___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_0 (0x00AB3590) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_0___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_0__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_0__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_0__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_0__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_1 (0x00AB3594) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_1___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_1__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_1__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_1__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_1__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_2 (0x00AB3598) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_2___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_2__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_2__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_2__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT0_2__TAIL___S 0 + +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT1 (0x00AB362C) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT1___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT1___POR 0x00000000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT1__HEAD___POR 0x0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT1__TAIL___POR 0x0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT1__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT1__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT1__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT1__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT1___M 0xFFFFFFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT1___S 0 + +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_n(n) (0x00AB3630+0x4*(n)) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_n_nMIN 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_n_nMAX 25 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_n_ELEM 26 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_n___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_n___POR 0x00000000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_n__HEAD___POR 0x0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_n__TAIL___POR 0x0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_n__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_n__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_n__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_n__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_n___M 0xFFFFFFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_n___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_0 (0x00AB3630) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_0___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_0__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_0__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_0__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_0__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_1 (0x00AB3634) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_1___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_1__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_1__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_1__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_1__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_2 (0x00AB3638) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_2___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_2__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_2__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_2__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_2__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_3 (0x00AB363C) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_3___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_3__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_3__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_3__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_3__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_4 (0x00AB3640) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_4___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_4__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_4__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_4__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_4__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_5 (0x00AB3644) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_5___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_5__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_5__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_5__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_5__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_6 (0x00AB3648) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_6___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_6__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_6__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_6__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_6__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_7 (0x00AB364C) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_7___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_7__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_7__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_7__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_7__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_8 (0x00AB3650) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_8___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_8__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_8__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_8__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_8__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_9 (0x00AB3654) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_9___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_9__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_9__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_9__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_9__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_10 (0x00AB3658) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_10___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_10__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_10__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_10__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_10__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_11 (0x00AB365C) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_11___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_11__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_11__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_11__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_11__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_12 (0x00AB3660) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_12___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_12__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_12__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_12__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_12__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_13 (0x00AB3664) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_13___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_13__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_13__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_13__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_13__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_14 (0x00AB3668) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_14___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_14__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_14__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_14__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_14__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_15 (0x00AB366C) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_15___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_15__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_15__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_15__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_15__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_16 (0x00AB3670) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_16___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_16__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_16__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_16__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_16__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_17 (0x00AB3674) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_17___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_17__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_17__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_17__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_17__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_18 (0x00AB3678) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_18___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_18__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_18__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_18__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_18__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_19 (0x00AB367C) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_19___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_19__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_19__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_19__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_19__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_20 (0x00AB3680) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_20___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_20__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_20__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_20__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_20__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_21 (0x00AB3684) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_21___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_21__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_21__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_21__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_21__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_22 (0x00AB3688) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_22___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_22__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_22__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_22__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_22__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_23 (0x00AB368C) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_23___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_23__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_23__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_23__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_23__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_24 (0x00AB3690) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_24___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_24__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_24__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_24__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_24__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_25 (0x00AB3694) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_25___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_25__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_25__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_25__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT4_25__TAIL___S 0 + +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_n(n) (0x00AB369C+0x4*(n)) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_n_nMIN 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_n_nMAX 3 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_n_ELEM 4 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_n___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_n___POR 0x00000000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_n__HEAD___POR 0x0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_n__TAIL___POR 0x0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_n__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_n__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_n__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_n__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_n___M 0xFFFFFFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_n___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_0 (0x00AB369C) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_0___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_0__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_0__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_0__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_0__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_1 (0x00AB36A0) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_1___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_1__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_1__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_1__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_1__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_2 (0x00AB36A4) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_2___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_2__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_2__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_2__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_2__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_3 (0x00AB36A8) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_3___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_3__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_3__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_3__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT5_3__TAIL___S 0 + +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_n(n) (0x00AB3730+0x4*(n)) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_n_nMIN 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_n_nMAX 2 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_n_ELEM 3 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_n___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_n___POR 0x00000000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_n__HEAD___POR 0x0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_n__TAIL___POR 0x0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_n__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_n__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_n__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_n__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_n___M 0xFFFFFFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_n___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_0 (0x00AB3730) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_0___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_0__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_0__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_0__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_0__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_1 (0x00AB3734) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_1___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_1__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_1__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_1__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_1__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_2 (0x00AB3738) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_2___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_2__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_2__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_2__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT6_2__TAIL___S 0 + +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT7 (0x00AB37C4) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT7___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT7___POR 0x00000000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT7__HEAD___POR 0x0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT7__TAIL___POR 0x0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT7__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT7__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT7__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT7__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT7___M 0xFFFFFFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT7___S 0 + +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT8 (0x00AB37C8) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT8___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT8___POR 0x00000000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT8__HEAD___POR 0x0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT8__TAIL___POR 0x0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT8__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT8__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT8__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT8__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT8___M 0xFFFFFFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT8___S 0 + +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT9 (0x00AB385C) +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT9___RWC QCSR_REG_RO +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT9___POR 0x00000000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT9__HEAD___POR 0x0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT9__TAIL___POR 0x0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT9__HEAD___M 0xFFFF0000 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT9__HEAD___S 16 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT9__TAIL___M 0x0000FFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT9__TAIL___S 0 +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT9___M 0xFFFFFFFF +#define WMAC0_SFM_R0_LINK_LIST_DESCRIPTOR_CLIENT9___S 0 + +#define WMAC0_SFM_R0_RRI_TABLE_ADDR (0x00AB3860) +#define WMAC0_SFM_R0_RRI_TABLE_ADDR___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_RRI_TABLE_ADDR___POR 0x00000000 +#define WMAC0_SFM_R0_RRI_TABLE_ADDR__VALUE___POR 0x0000 +#define WMAC0_SFM_R0_RRI_TABLE_ADDR__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_RRI_TABLE_ADDR__VALUE___S 0 +#define WMAC0_SFM_R0_RRI_TABLE_ADDR___M 0x00007FFF +#define WMAC0_SFM_R0_RRI_TABLE_ADDR___S 0 + +#define WMAC0_SFM_R0_RRI_TABLE_DATA (0x00AB3864) +#define WMAC0_SFM_R0_RRI_TABLE_DATA___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_RRI_TABLE_DATA___POR 0x00000000 +#define WMAC0_SFM_R0_RRI_TABLE_DATA__VALUE___POR 0x00000000 +#define WMAC0_SFM_R0_RRI_TABLE_DATA__VALUE___M 0xFFFFFFFF +#define WMAC0_SFM_R0_RRI_TABLE_DATA__VALUE___S 0 +#define WMAC0_SFM_R0_RRI_TABLE_DATA___M 0xFFFFFFFF +#define WMAC0_SFM_R0_RRI_TABLE_DATA___S 0 + +#define WMAC0_SFM_R0_RRI_TABLE_AUTO_INC (0x00AB3868) +#define WMAC0_SFM_R0_RRI_TABLE_AUTO_INC___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_RRI_TABLE_AUTO_INC___POR 0x00000000 +#define WMAC0_SFM_R0_RRI_TABLE_AUTO_INC__ENABLE___POR 0x0 +#define WMAC0_SFM_R0_RRI_TABLE_AUTO_INC__ENABLE___M 0x00000001 +#define WMAC0_SFM_R0_RRI_TABLE_AUTO_INC__ENABLE___S 0 +#define WMAC0_SFM_R0_RRI_TABLE_AUTO_INC___M 0x00000001 +#define WMAC0_SFM_R0_RRI_TABLE_AUTO_INC___S 0 + +#define WMAC0_SFM_R0_CMEM_CONTROL (0x00AB386C) +#define WMAC0_SFM_R0_CMEM_CONTROL___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_CMEM_CONTROL___POR 0x00000000 +#define WMAC0_SFM_R0_CMEM_CONTROL__DEBUG_MODE___POR 0x0 +#define WMAC0_SFM_R0_CMEM_CONTROL__AUTO_INC_ENABLE___POR 0x0 +#define WMAC0_SFM_R0_CMEM_CONTROL__DEBUG_MODE___M 0x00000002 +#define WMAC0_SFM_R0_CMEM_CONTROL__DEBUG_MODE___S 1 +#define WMAC0_SFM_R0_CMEM_CONTROL__AUTO_INC_ENABLE___M 0x00000001 +#define WMAC0_SFM_R0_CMEM_CONTROL__AUTO_INC_ENABLE___S 0 +#define WMAC0_SFM_R0_CMEM_CONTROL___M 0x00000003 +#define WMAC0_SFM_R0_CMEM_CONTROL___S 0 + +#define WMAC0_SFM_R0_CMEM_ADDR (0x00AB3870) +#define WMAC0_SFM_R0_CMEM_ADDR___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_CMEM_ADDR___POR 0x00000000 +#define WMAC0_SFM_R0_CMEM_ADDR__VALUE___POR 0x0000 +#define WMAC0_SFM_R0_CMEM_ADDR__VALUE___M 0x00007FFF +#define WMAC0_SFM_R0_CMEM_ADDR__VALUE___S 0 +#define WMAC0_SFM_R0_CMEM_ADDR___M 0x00007FFF +#define WMAC0_SFM_R0_CMEM_ADDR___S 0 + +#define WMAC0_SFM_R0_CMEM_DATA (0x00AB3874) +#define WMAC0_SFM_R0_CMEM_DATA___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_CMEM_DATA___POR 0x00000000 +#define WMAC0_SFM_R0_CMEM_DATA__VALUE___POR 0x00000000 +#define WMAC0_SFM_R0_CMEM_DATA__VALUE___M 0xFFFFFFFF +#define WMAC0_SFM_R0_CMEM_DATA__VALUE___S 0 +#define WMAC0_SFM_R0_CMEM_DATA___M 0xFFFFFFFF +#define WMAC0_SFM_R0_CMEM_DATA___S 0 + +#define WMAC0_SFM_R0_CMEM_DATA_33_32 (0x00AB3878) +#define WMAC0_SFM_R0_CMEM_DATA_33_32___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_CMEM_DATA_33_32___POR 0x00000000 +#define WMAC0_SFM_R0_CMEM_DATA_33_32__VALUE___POR 0x0 +#define WMAC0_SFM_R0_CMEM_DATA_33_32__VALUE___M 0x00000003 +#define WMAC0_SFM_R0_CMEM_DATA_33_32__VALUE___S 0 +#define WMAC0_SFM_R0_CMEM_DATA_33_32___M 0x00000003 +#define WMAC0_SFM_R0_CMEM_DATA_33_32___S 0 + +#define WMAC0_SFM_R0_LMEM_ADDR (0x00AB387C) +#define WMAC0_SFM_R0_LMEM_ADDR___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_LMEM_ADDR___POR 0x00000000 +#define WMAC0_SFM_R0_LMEM_ADDR__VALUE___POR 0x000 +#define WMAC0_SFM_R0_LMEM_ADDR__VALUE___M 0x000003FF +#define WMAC0_SFM_R0_LMEM_ADDR__VALUE___S 0 +#define WMAC0_SFM_R0_LMEM_ADDR___M 0x000003FF +#define WMAC0_SFM_R0_LMEM_ADDR___S 0 + +#define WMAC0_SFM_R0_LMEM_DATA (0x00AB3880) +#define WMAC0_SFM_R0_LMEM_DATA___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_LMEM_DATA___POR 0x00000000 +#define WMAC0_SFM_R0_LMEM_DATA__VALUE___POR 0x00000 +#define WMAC0_SFM_R0_LMEM_DATA__VALUE___M 0x000FFFFF +#define WMAC0_SFM_R0_LMEM_DATA__VALUE___S 0 +#define WMAC0_SFM_R0_LMEM_DATA___M 0x000FFFFF +#define WMAC0_SFM_R0_LMEM_DATA___S 0 + +#define WMAC0_SFM_R0_RRI_START_ADDR (0x00AB3884) +#define WMAC0_SFM_R0_RRI_START_ADDR___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_RRI_START_ADDR___POR 0x00000000 +#define WMAC0_SFM_R0_RRI_START_ADDR__VALUE___POR 0x0000 +#define WMAC0_SFM_R0_RRI_START_ADDR__VALUE___M 0x0000FFFF +#define WMAC0_SFM_R0_RRI_START_ADDR__VALUE___S 0 +#define WMAC0_SFM_R0_RRI_START_ADDR___M 0x0000FFFF +#define WMAC0_SFM_R0_RRI_START_ADDR___S 0 + +#define WMAC0_SFM_R0_RRI_ACCESS_CTRL (0x00AB3888) +#define WMAC0_SFM_R0_RRI_ACCESS_CTRL___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_RRI_ACCESS_CTRL___POR 0x00000001 +#define WMAC0_SFM_R0_RRI_ACCESS_CTRL__ENABLE___POR 0x1 +#define WMAC0_SFM_R0_RRI_ACCESS_CTRL__ENABLE___M 0x00000001 +#define WMAC0_SFM_R0_RRI_ACCESS_CTRL__ENABLE___S 0 +#define WMAC0_SFM_R0_RRI_ACCESS_CTRL___M 0x00000001 +#define WMAC0_SFM_R0_RRI_ACCESS_CTRL___S 0 + +#define WMAC0_SFM_R0_SW_ACCESS_CTRL (0x00AB388C) +#define WMAC0_SFM_R0_SW_ACCESS_CTRL___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_SW_ACCESS_CTRL___POR 0xFFFF0000 +#define WMAC0_SFM_R0_SW_ACCESS_CTRL__ECO1___POR 0xFFFF +#define WMAC0_SFM_R0_SW_ACCESS_CTRL__ECO0___POR 0x0000 +#define WMAC0_SFM_R0_SW_ACCESS_CTRL__ENABLE___POR 0x0 +#define WMAC0_SFM_R0_SW_ACCESS_CTRL__ECO1___M 0xFFFF0000 +#define WMAC0_SFM_R0_SW_ACCESS_CTRL__ECO1___S 16 +#define WMAC0_SFM_R0_SW_ACCESS_CTRL__ECO0___M 0x0000FFFE +#define WMAC0_SFM_R0_SW_ACCESS_CTRL__ECO0___S 1 +#define WMAC0_SFM_R0_SW_ACCESS_CTRL__ENABLE___M 0x00000001 +#define WMAC0_SFM_R0_SW_ACCESS_CTRL__ENABLE___S 0 +#define WMAC0_SFM_R0_SW_ACCESS_CTRL___M 0xFFFFFFFF +#define WMAC0_SFM_R0_SW_ACCESS_CTRL___S 0 + +#define WMAC0_SFM_R0_CLK_GATE_DISABLE (0x00AB3890) +#define WMAC0_SFM_R0_CLK_GATE_DISABLE___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_CLK_GATE_DISABLE___POR 0x80000000 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND___POR 0x1 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__TBD___POR 0x00 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__BMGR___POR 0x0 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__LMEM___POR 0x0 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__LMEM_CTRL___POR 0x0 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK7___POR 0x0 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK6___POR 0x0 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK5___POR 0x0 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK4___POR 0x0 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK3___POR 0x0 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK2___POR 0x0 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK1___POR 0x0 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK0___POR 0x0 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_CTRL___POR 0x0 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__HW_INIT___POR 0x0 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT9___POR 0x0 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT8___POR 0x0 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT7___POR 0x0 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT6___POR 0x0 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT5___POR 0x0 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT4___POR 0x0 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT3___POR 0x0 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT2___POR 0x0 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT1___POR 0x0 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT0___POR 0x0 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND___M 0x80000000 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLK_ENS_EXTEND___S 31 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__TBD___M 0x7F800000 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__TBD___S 23 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__BMGR___M 0x00400000 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__BMGR___S 22 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__LMEM___M 0x00200000 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__LMEM___S 21 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__LMEM_CTRL___M 0x00100000 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__LMEM_CTRL___S 20 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK7___M 0x00080000 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK7___S 19 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK6___M 0x00040000 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK6___S 18 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK5___M 0x00020000 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK5___S 17 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK4___M 0x00010000 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK4___S 16 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK3___M 0x00008000 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK3___S 15 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK2___M 0x00004000 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK2___S 14 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK1___M 0x00002000 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK1___S 13 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK0___M 0x00001000 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_BANK0___S 12 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_CTRL___M 0x00000800 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CMEM_CTRL___S 11 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__HW_INIT___M 0x00000400 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__HW_INIT___S 10 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT9___M 0x00000200 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT9___S 9 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT8___M 0x00000100 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT8___S 8 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT7___M 0x00000080 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT7___S 7 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT6___M 0x00000040 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT6___S 6 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT5___M 0x00000020 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT5___S 5 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT4___M 0x00000010 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT4___S 4 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT3___M 0x00000008 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT3___S 3 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT2___M 0x00000004 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT2___S 2 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT1___M 0x00000002 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT1___S 1 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT0___M 0x00000001 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE__CLIENT0___S 0 +#define WMAC0_SFM_R0_CLK_GATE_DISABLE___M 0xFFFFFFFF +#define WMAC0_SFM_R0_CLK_GATE_DISABLE___S 0 + +#define WMAC0_SFM_R0_RRI_MODE (0x00AB3894) +#define WMAC0_SFM_R0_RRI_MODE___RWC QCSR_REG_RW +#define WMAC0_SFM_R0_RRI_MODE___POR 0x00000001 +#define WMAC0_SFM_R0_RRI_MODE__RRI_MODIFIED_ACCESS_EN___POR 0x0 +#define WMAC0_SFM_R0_RRI_MODE__ENABLE___POR 0x1 +#define WMAC0_SFM_R0_RRI_MODE__RRI_MODIFIED_ACCESS_EN___M 0x00000002 +#define WMAC0_SFM_R0_RRI_MODE__RRI_MODIFIED_ACCESS_EN___S 1 +#define WMAC0_SFM_R0_RRI_MODE__ENABLE___M 0x00000001 +#define WMAC0_SFM_R0_RRI_MODE__ENABLE___S 0 +#define WMAC0_SFM_R0_RRI_MODE___M 0x00000003 +#define WMAC0_SFM_R0_RRI_MODE___S 0 + +#define WMAC0_SFM_R1_WATCHDOG (0x00AB4000) +#define WMAC0_SFM_R1_WATCHDOG___RWC QCSR_REG_RW +#define WMAC0_SFM_R1_WATCHDOG___POR 0x0000FFFF +#define WMAC0_SFM_R1_WATCHDOG__STATUS___POR 0x0000 +#define WMAC0_SFM_R1_WATCHDOG__LIMIT___POR 0xFFFF +#define WMAC0_SFM_R1_WATCHDOG__STATUS___M 0xFFFF0000 +#define WMAC0_SFM_R1_WATCHDOG__STATUS___S 16 +#define WMAC0_SFM_R1_WATCHDOG__LIMIT___M 0x0000FFFF +#define WMAC0_SFM_R1_WATCHDOG__LIMIT___S 0 +#define WMAC0_SFM_R1_WATCHDOG___M 0xFFFFFFFF +#define WMAC0_SFM_R1_WATCHDOG___S 0 + +#define WMAC0_SFM_R1_EVENTMASK_IX_0 (0x00AB4004) +#define WMAC0_SFM_R1_EVENTMASK_IX_0___RWC QCSR_REG_RW +#define WMAC0_SFM_R1_EVENTMASK_IX_0___POR 0xFFFFFFFF +#define WMAC0_SFM_R1_EVENTMASK_IX_0__MASK___POR 0xFFFFFFFF +#define WMAC0_SFM_R1_EVENTMASK_IX_0__MASK___M 0xFFFFFFFF +#define WMAC0_SFM_R1_EVENTMASK_IX_0__MASK___S 0 +#define WMAC0_SFM_R1_EVENTMASK_IX_0___M 0xFFFFFFFF +#define WMAC0_SFM_R1_EVENTMASK_IX_0___S 0 + +#define WMAC0_SFM_R1_EVENTMASK_IX_1 (0x00AB4008) +#define WMAC0_SFM_R1_EVENTMASK_IX_1___RWC QCSR_REG_RW +#define WMAC0_SFM_R1_EVENTMASK_IX_1___POR 0xFFFFFFFF +#define WMAC0_SFM_R1_EVENTMASK_IX_1__MASK___POR 0xFFFFFFFF +#define WMAC0_SFM_R1_EVENTMASK_IX_1__MASK___M 0xFFFFFFFF +#define WMAC0_SFM_R1_EVENTMASK_IX_1__MASK___S 0 +#define WMAC0_SFM_R1_EVENTMASK_IX_1___M 0xFFFFFFFF +#define WMAC0_SFM_R1_EVENTMASK_IX_1___S 0 + +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX0 (0x00AB400C) +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX0___RWC QCSR_REG_RW +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX0___POR 0x00000000 +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX0__SELECT_CLIENT0___POR 0x00 +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX0__SELECT_CLIENT0___M 0x0000001F +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX0__SELECT_CLIENT0___S 0 +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX0___M 0x0000001F +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX0___S 0 + +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX1 (0x00AB4010) +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX1___RWC QCSR_REG_RW +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX1___POR 0x00000000 +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX1__SELECT_CLIENT1___POR 0x00 +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX1__SELECT_CLIENT1___M 0x0000001F +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX1__SELECT_CLIENT1___S 0 +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX1___M 0x0000001F +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX1___S 0 + +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX2 (0x00AB4014) +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX2___RWC QCSR_REG_RW +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX2___POR 0x00000000 +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX2__SELECT_CLIENT2___POR 0x00 +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX2__SELECT_CLIENT2___M 0x0000001F +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX2__SELECT_CLIENT2___S 0 +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX2___M 0x0000001F +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX2___S 0 + +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX3 (0x00AB4018) +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX3___RWC QCSR_REG_RW +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX3___POR 0x00000000 +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX3__SELECT_CLIENT3___POR 0x00 +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX3__SELECT_CLIENT3___M 0x0000001F +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX3__SELECT_CLIENT3___S 0 +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX3___M 0x0000001F +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX3___S 0 + +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX4 (0x00AB401C) +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX4___RWC QCSR_REG_RW +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX4___POR 0x00000000 +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX4__SELECT_CLIENT4___POR 0x00 +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX4__SELECT_CLIENT4___M 0x0000001F +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX4__SELECT_CLIENT4___S 0 +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX4___M 0x0000001F +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX4___S 0 + +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX5 (0x00AB4020) +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX5___RWC QCSR_REG_RW +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX5___POR 0x00000000 +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX5__SELECT_CLIENT5___POR 0x00 +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX5__SELECT_CLIENT5___M 0x0000001F +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX5__SELECT_CLIENT5___S 0 +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX5___M 0x0000001F +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX5___S 0 + +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX6 (0x00AB4024) +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX6___RWC QCSR_REG_RW +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX6___POR 0x00000000 +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX6__SELECT_CLIENT6___POR 0x00 +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX6__SELECT_CLIENT6___M 0x0000001F +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX6__SELECT_CLIENT6___S 0 +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX6___M 0x0000001F +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX6___S 0 + +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX7 (0x00AB4028) +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX7___RWC QCSR_REG_RW +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX7___POR 0x00000000 +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX7__SELECT_CLIENT7___POR 0x00 +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX7__SELECT_CLIENT7___M 0x0000001F +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX7__SELECT_CLIENT7___S 0 +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX7___M 0x0000001F +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX7___S 0 + +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX8 (0x00AB402C) +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX8___RWC QCSR_REG_RW +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX8___POR 0x00000000 +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX8__SELECT_CLIENT8___POR 0x00 +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX8__SELECT_CLIENT8___M 0x0000001F +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX8__SELECT_CLIENT8___S 0 +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX8___M 0x0000001F +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX8___S 0 + +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX9 (0x00AB4030) +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX9___RWC QCSR_REG_RW +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX9___POR 0x00000000 +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX9__SELECT_CLIENT9___POR 0x00 +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX9__SELECT_CLIENT9___M 0x0000001F +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX9__SELECT_CLIENT9___S 0 +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX9___M 0x0000001F +#define WMAC0_SFM_R1_TESTBUS_CTRL_IX9___S 0 + +#define WMAC0_SFM_R1_TESTBUS_CTRL (0x00AB4034) +#define WMAC0_SFM_R1_TESTBUS_CTRL___RWC QCSR_REG_RW +#define WMAC0_SFM_R1_TESTBUS_CTRL___POR 0x00000000 +#define WMAC0_SFM_R1_TESTBUS_CTRL__SELECT_TBD___POR 0x0000 +#define WMAC0_SFM_R1_TESTBUS_CTRL__SELECT_BMGR___POR 0x0 +#define WMAC0_SFM_R1_TESTBUS_CTRL__SELECT_LMEM___POR 0x0 +#define WMAC0_SFM_R1_TESTBUS_CTRL__SELECT_CMEM___POR 0x00 +#define WMAC0_SFM_R1_TESTBUS_CTRL__SELECT_FINAL___POR 0x00 +#define WMAC0_SFM_R1_TESTBUS_CTRL__SELECT_TBD___M 0xFFFE0000 +#define WMAC0_SFM_R1_TESTBUS_CTRL__SELECT_TBD___S 17 +#define WMAC0_SFM_R1_TESTBUS_CTRL__SELECT_BMGR___M 0x0001C000 +#define WMAC0_SFM_R1_TESTBUS_CTRL__SELECT_BMGR___S 14 +#define WMAC0_SFM_R1_TESTBUS_CTRL__SELECT_LMEM___M 0x00003C00 +#define WMAC0_SFM_R1_TESTBUS_CTRL__SELECT_LMEM___S 10 +#define WMAC0_SFM_R1_TESTBUS_CTRL__SELECT_CMEM___M 0x000003E0 +#define WMAC0_SFM_R1_TESTBUS_CTRL__SELECT_CMEM___S 5 +#define WMAC0_SFM_R1_TESTBUS_CTRL__SELECT_FINAL___M 0x0000001F +#define WMAC0_SFM_R1_TESTBUS_CTRL__SELECT_FINAL___S 0 +#define WMAC0_SFM_R1_TESTBUS_CTRL___M 0xFFFFFFFF +#define WMAC0_SFM_R1_TESTBUS_CTRL___S 0 + +#define WMAC0_SFM_R1_TESTBUS_OUT_LOW (0x00AB4038) +#define WMAC0_SFM_R1_TESTBUS_OUT_LOW___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_TESTBUS_OUT_LOW___POR 0x00000000 +#define WMAC0_SFM_R1_TESTBUS_OUT_LOW__VALUE___POR 0x00000000 +#define WMAC0_SFM_R1_TESTBUS_OUT_LOW__VALUE___M 0xFFFFFFFF +#define WMAC0_SFM_R1_TESTBUS_OUT_LOW__VALUE___S 0 +#define WMAC0_SFM_R1_TESTBUS_OUT_LOW___M 0xFFFFFFFF +#define WMAC0_SFM_R1_TESTBUS_OUT_LOW___S 0 + +#define WMAC0_SFM_R1_TESTBUS_OUT_HIGH (0x00AB403C) +#define WMAC0_SFM_R1_TESTBUS_OUT_HIGH___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_TESTBUS_OUT_HIGH___POR 0x00000000 +#define WMAC0_SFM_R1_TESTBUS_OUT_HIGH__VALUE___POR 0x00 +#define WMAC0_SFM_R1_TESTBUS_OUT_HIGH__VALUE___M 0x000000FF +#define WMAC0_SFM_R1_TESTBUS_OUT_HIGH__VALUE___S 0 +#define WMAC0_SFM_R1_TESTBUS_OUT_HIGH___M 0x000000FF +#define WMAC0_SFM_R1_TESTBUS_OUT_HIGH___S 0 + +#define WMAC0_SFM_R1_SETUP_DEBUG (0x00AB4040) +#define WMAC0_SFM_R1_SETUP_DEBUG___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_SETUP_DEBUG___POR 0x00000000 +#define WMAC0_SFM_R1_SETUP_DEBUG__DEALLOC_COUNT___POR 0x00 +#define WMAC0_SFM_R1_SETUP_DEBUG__INIT_COUNT___POR 0x00 +#define WMAC0_SFM_R1_SETUP_DEBUG__DEALLOC_AFTER_INIT___POR 0x0 +#define WMAC0_SFM_R1_SETUP_DEBUG__SET_MIN_AFTER_INIT___POR 0x0 +#define WMAC0_SFM_R1_SETUP_DEBUG__DEALLOC_COUNT___M 0x0003FC00 +#define WMAC0_SFM_R1_SETUP_DEBUG__DEALLOC_COUNT___S 10 +#define WMAC0_SFM_R1_SETUP_DEBUG__INIT_COUNT___M 0x000003FC +#define WMAC0_SFM_R1_SETUP_DEBUG__INIT_COUNT___S 2 +#define WMAC0_SFM_R1_SETUP_DEBUG__DEALLOC_AFTER_INIT___M 0x00000002 +#define WMAC0_SFM_R1_SETUP_DEBUG__DEALLOC_AFTER_INIT___S 1 +#define WMAC0_SFM_R1_SETUP_DEBUG__SET_MIN_AFTER_INIT___M 0x00000001 +#define WMAC0_SFM_R1_SETUP_DEBUG__SET_MIN_AFTER_INIT___S 0 +#define WMAC0_SFM_R1_SETUP_DEBUG___M 0x0003FFFF +#define WMAC0_SFM_R1_SETUP_DEBUG___S 0 + +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_n(n) (0x00AB4044+0x4*(n)) +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_n_nMIN 0 +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_n_nMAX 9 +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_n_ELEM 10 +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_n___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_n___POR 0x00000000 +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_n__VALUE___POR 0x00 +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_n__VALUE___M 0x000000FF +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_n__VALUE___S 0 +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_n___M 0x000000FF +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_n___S 0 +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_0 (0x00AB4044) +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_0___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_0__VALUE___M 0x000000FF +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_0__VALUE___S 0 +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_1 (0x00AB4048) +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_1___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_1__VALUE___M 0x000000FF +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_1__VALUE___S 0 +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_2 (0x00AB404C) +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_2___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_2__VALUE___M 0x000000FF +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_2__VALUE___S 0 +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_3 (0x00AB4050) +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_3___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_3__VALUE___M 0x000000FF +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_3__VALUE___S 0 +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_4 (0x00AB4054) +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_4___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_4__VALUE___M 0x000000FF +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_4__VALUE___S 0 +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_5 (0x00AB4058) +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_5___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_5__VALUE___M 0x000000FF +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_5__VALUE___S 0 +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_6 (0x00AB405C) +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_6___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_6__VALUE___M 0x000000FF +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_6__VALUE___S 0 +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_7 (0x00AB4060) +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_7___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_7__VALUE___M 0x000000FF +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_7__VALUE___S 0 +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_8 (0x00AB4064) +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_8___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_8__VALUE___M 0x000000FF +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_8__VALUE___S 0 +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_9 (0x00AB4068) +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_9___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_9__VALUE___M 0x000000FF +#define WMAC0_SFM_R1_FLUSH_FSM_STATUS_9__VALUE___S 0 + +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_n(n) (0x00AB406C+0x4*(n)) +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_n_nMIN 0 +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_n_nMAX 9 +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_n_ELEM 10 +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_n___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_n___POR 0x00000000 +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_n__VALUE___POR 0x0000 +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_n__VALUE___M 0x00001FFF +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_n__VALUE___S 0 +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_n___M 0x00001FFF +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_n___S 0 +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_0 (0x00AB406C) +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_0___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_0__VALUE___M 0x00001FFF +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_0__VALUE___S 0 +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_1 (0x00AB4070) +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_1___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_1__VALUE___M 0x00001FFF +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_1__VALUE___S 0 +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_2 (0x00AB4074) +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_2___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_2__VALUE___M 0x00001FFF +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_2__VALUE___S 0 +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_3 (0x00AB4078) +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_3___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_3__VALUE___M 0x00001FFF +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_3__VALUE___S 0 +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_4 (0x00AB407C) +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_4___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_4__VALUE___M 0x00001FFF +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_4__VALUE___S 0 +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_5 (0x00AB4080) +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_5___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_5__VALUE___M 0x00001FFF +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_5__VALUE___S 0 +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_6 (0x00AB4084) +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_6___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_6__VALUE___M 0x00001FFF +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_6__VALUE___S 0 +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_7 (0x00AB4088) +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_7___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_7__VALUE___M 0x00001FFF +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_7__VALUE___S 0 +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_8 (0x00AB408C) +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_8___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_8__VALUE___M 0x00001FFF +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_8__VALUE___S 0 +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_9 (0x00AB4090) +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_9___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_9__VALUE___M 0x00001FFF +#define WMAC0_SFM_R1_BUFFER_PREFETCH_RELEASE_CNT_9__VALUE___S 0 + +#define WMAC0_SFM_R1_WR_RD_ERROR_STATUS (0x00AB4094) +#define WMAC0_SFM_R1_WR_RD_ERROR_STATUS___RWC QCSR_REG_RW +#define WMAC0_SFM_R1_WR_RD_ERROR_STATUS___POR 0x00000000 +#define WMAC0_SFM_R1_WR_RD_ERROR_STATUS__LAST_UF_USER___POR 0x00 +#define WMAC0_SFM_R1_WR_RD_ERROR_STATUS__RD_UNDERFLOW___POR 0x000 +#define WMAC0_SFM_R1_WR_RD_ERROR_STATUS__LAST_OF_USER___POR 0x00 +#define WMAC0_SFM_R1_WR_RD_ERROR_STATUS__WR_OVERFLOW___POR 0x000 +#define WMAC0_SFM_R1_WR_RD_ERROR_STATUS__LAST_UF_USER___M 0xFC000000 +#define WMAC0_SFM_R1_WR_RD_ERROR_STATUS__LAST_UF_USER___S 26 +#define WMAC0_SFM_R1_WR_RD_ERROR_STATUS__RD_UNDERFLOW___M 0x03FF0000 +#define WMAC0_SFM_R1_WR_RD_ERROR_STATUS__RD_UNDERFLOW___S 16 +#define WMAC0_SFM_R1_WR_RD_ERROR_STATUS__LAST_OF_USER___M 0x0000FC00 +#define WMAC0_SFM_R1_WR_RD_ERROR_STATUS__LAST_OF_USER___S 10 +#define WMAC0_SFM_R1_WR_RD_ERROR_STATUS__WR_OVERFLOW___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_ERROR_STATUS__WR_OVERFLOW___S 0 +#define WMAC0_SFM_R1_WR_RD_ERROR_STATUS___M 0xFFFFFFFF +#define WMAC0_SFM_R1_WR_RD_ERROR_STATUS___S 0 + +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_n(n) (0x00AB4098+0x4*(n)) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_n_nMIN 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_n_nMAX 2 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_n_ELEM 3 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_n___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_n___POR 0x00000000 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_n__VALUE___POR 0x000 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_n__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_n__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_n___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_n___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_0 (0x00AB4098) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_0___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_0__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_0__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_1 (0x00AB409C) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_1___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_1__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_1__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_2 (0x00AB40A0) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_2___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_2__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT0_2__VALUE___S 0 + +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT1 (0x00AB4134) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT1___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT1___POR 0x00000000 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT1__VALUE___POR 0x000 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT1__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT1__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT1___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT1___S 0 + +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_n(n) (0x00AB4138+0x4*(n)) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_n_nMIN 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_n_nMAX 2 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_n_ELEM 3 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_n___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_n___POR 0x00000000 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_n__VALUE___POR 0x000 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_n__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_n__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_n___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_n___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_0 (0x00AB4138) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_0___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_0__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_0__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_1 (0x00AB413C) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_1___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_1__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_1__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_2 (0x00AB4140) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_2___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_2__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT2_2__VALUE___S 0 + +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_n(n) (0x00AB41CC+0x4*(n)) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_n_nMIN 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_n_nMAX 2 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_n_ELEM 3 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_n___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_n___POR 0x00000000 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_n__VALUE___POR 0x000 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_n__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_n__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_n___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_n___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_0 (0x00AB41CC) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_0___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_0__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_0__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_1 (0x00AB41D0) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_1___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_1__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_1__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_2 (0x00AB41D4) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_2___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_2__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT3_2__VALUE___S 0 + +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_n(n) (0x00AB41D8+0x4*(n)) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_n_nMIN 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_n_nMAX 25 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_n_ELEM 26 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_n___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_n___POR 0x00000000 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_n__VALUE___POR 0x000 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_n__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_n__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_n___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_n___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_0 (0x00AB41D8) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_0___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_0__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_0__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_1 (0x00AB41DC) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_1___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_1__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_1__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_2 (0x00AB41E0) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_2___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_2__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_2__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_3 (0x00AB41E4) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_3___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_3__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_3__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_4 (0x00AB41E8) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_4___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_4__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_4__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_5 (0x00AB41EC) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_5___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_5__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_5__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_6 (0x00AB41F0) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_6___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_6__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_6__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_7 (0x00AB41F4) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_7___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_7__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_7__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_8 (0x00AB41F8) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_8___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_8__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_8__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_9 (0x00AB41FC) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_9___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_9__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_9__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_10 (0x00AB4200) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_10___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_10__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_10__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_11 (0x00AB4204) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_11___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_11__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_11__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_12 (0x00AB4208) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_12___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_12__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_12__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_13 (0x00AB420C) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_13___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_13__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_13__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_14 (0x00AB4210) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_14___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_14__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_14__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_15 (0x00AB4214) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_15___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_15__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_15__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_16 (0x00AB4218) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_16___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_16__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_16__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_17 (0x00AB421C) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_17___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_17__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_17__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_18 (0x00AB4220) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_18___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_18__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_18__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_19 (0x00AB4224) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_19___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_19__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_19__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_20 (0x00AB4228) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_20___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_20__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_20__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_21 (0x00AB422C) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_21___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_21__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_21__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_22 (0x00AB4230) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_22___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_22__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_22__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_23 (0x00AB4234) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_23___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_23__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_23__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_24 (0x00AB4238) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_24___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_24__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_24__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_25 (0x00AB423C) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_25___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_25__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT4_25__VALUE___S 0 + +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_n(n) (0x00AB4244+0x4*(n)) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_n_nMIN 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_n_nMAX 3 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_n_ELEM 4 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_n___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_n___POR 0x00000000 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_n__VALUE___POR 0x000 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_n__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_n__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_n___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_n___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_0 (0x00AB4244) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_0___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_0__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_0__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_1 (0x00AB4248) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_1___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_1__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_1__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_2 (0x00AB424C) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_2___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_2__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_2__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_3 (0x00AB4250) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_3___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_3__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT5_3__VALUE___S 0 + +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_n(n) (0x00AB42D8+0x4*(n)) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_n_nMIN 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_n_nMAX 2 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_n_ELEM 3 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_n___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_n___POR 0x00000000 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_n__VALUE___POR 0x000 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_n__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_n__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_n___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_n___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_0 (0x00AB42D8) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_0___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_0__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_0__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_1 (0x00AB42DC) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_1___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_1__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_1__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_2 (0x00AB42E0) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_2___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_2__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT6_2__VALUE___S 0 + +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT7 (0x00AB436C) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT7___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT7___POR 0x00000000 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT7__VALUE___POR 0x000 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT7__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT7__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT7___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT7___S 0 + +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT8 (0x00AB4370) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT8___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT8___POR 0x00000000 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT8__VALUE___POR 0x000 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT8__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT8__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT8___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT8___S 0 + +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT9 (0x00AB4404) +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT9___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT9___POR 0x00000000 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT9__VALUE___POR 0x000 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT9__VALUE___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT9__VALUE___S 0 +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT9___M 0x000003FF +#define WMAC0_SFM_R1_WR_RD_OFFSET_CLIENT9___S 0 + +#define WMAC0_SFM_R1_HW_INIT_BMGR_FSM_STATUS (0x00AB4408) +#define WMAC0_SFM_R1_HW_INIT_BMGR_FSM_STATUS___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_HW_INIT_BMGR_FSM_STATUS___POR 0x00000000 +#define WMAC0_SFM_R1_HW_INIT_BMGR_FSM_STATUS__VALUE___POR 0x00 +#define WMAC0_SFM_R1_HW_INIT_BMGR_FSM_STATUS__VALUE___M 0x0000003F +#define WMAC0_SFM_R1_HW_INIT_BMGR_FSM_STATUS__VALUE___S 0 +#define WMAC0_SFM_R1_HW_INIT_BMGR_FSM_STATUS___M 0x0000003F +#define WMAC0_SFM_R1_HW_INIT_BMGR_FSM_STATUS___S 0 + +#define WMAC0_SFM_R1_MEM_EMPTY (0x00AB440C) +#define WMAC0_SFM_R1_MEM_EMPTY___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_MEM_EMPTY___POR 0x000007FF +#define WMAC0_SFM_R1_MEM_EMPTY__TOTAL___POR 0x1 +#define WMAC0_SFM_R1_MEM_EMPTY__CLIENT9___POR 0x1 +#define WMAC0_SFM_R1_MEM_EMPTY__CLIENT8___POR 0x1 +#define WMAC0_SFM_R1_MEM_EMPTY__CLIENT7___POR 0x1 +#define WMAC0_SFM_R1_MEM_EMPTY__CLIENT6___POR 0x1 +#define WMAC0_SFM_R1_MEM_EMPTY__CLIENT5___POR 0x1 +#define WMAC0_SFM_R1_MEM_EMPTY__CLIENT4___POR 0x1 +#define WMAC0_SFM_R1_MEM_EMPTY__CLIENT3___POR 0x1 +#define WMAC0_SFM_R1_MEM_EMPTY__CLIENT2___POR 0x1 +#define WMAC0_SFM_R1_MEM_EMPTY__CLIENT1___POR 0x1 +#define WMAC0_SFM_R1_MEM_EMPTY__CLIENT0___POR 0x1 +#define WMAC0_SFM_R1_MEM_EMPTY__TOTAL___M 0x00000400 +#define WMAC0_SFM_R1_MEM_EMPTY__TOTAL___S 10 +#define WMAC0_SFM_R1_MEM_EMPTY__CLIENT9___M 0x00000200 +#define WMAC0_SFM_R1_MEM_EMPTY__CLIENT9___S 9 +#define WMAC0_SFM_R1_MEM_EMPTY__CLIENT8___M 0x00000100 +#define WMAC0_SFM_R1_MEM_EMPTY__CLIENT8___S 8 +#define WMAC0_SFM_R1_MEM_EMPTY__CLIENT7___M 0x00000080 +#define WMAC0_SFM_R1_MEM_EMPTY__CLIENT7___S 7 +#define WMAC0_SFM_R1_MEM_EMPTY__CLIENT6___M 0x00000040 +#define WMAC0_SFM_R1_MEM_EMPTY__CLIENT6___S 6 +#define WMAC0_SFM_R1_MEM_EMPTY__CLIENT5___M 0x00000020 +#define WMAC0_SFM_R1_MEM_EMPTY__CLIENT5___S 5 +#define WMAC0_SFM_R1_MEM_EMPTY__CLIENT4___M 0x00000010 +#define WMAC0_SFM_R1_MEM_EMPTY__CLIENT4___S 4 +#define WMAC0_SFM_R1_MEM_EMPTY__CLIENT3___M 0x00000008 +#define WMAC0_SFM_R1_MEM_EMPTY__CLIENT3___S 3 +#define WMAC0_SFM_R1_MEM_EMPTY__CLIENT2___M 0x00000004 +#define WMAC0_SFM_R1_MEM_EMPTY__CLIENT2___S 2 +#define WMAC0_SFM_R1_MEM_EMPTY__CLIENT1___M 0x00000002 +#define WMAC0_SFM_R1_MEM_EMPTY__CLIENT1___S 1 +#define WMAC0_SFM_R1_MEM_EMPTY__CLIENT0___M 0x00000001 +#define WMAC0_SFM_R1_MEM_EMPTY__CLIENT0___S 0 +#define WMAC0_SFM_R1_MEM_EMPTY___M 0x000007FF +#define WMAC0_SFM_R1_MEM_EMPTY___S 0 + +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_n(n) (0x00AB4410+0x4*(n)) +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_n_nMIN 0 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_n_nMAX 9 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_n_ELEM 10 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_n___RWC QCSR_REG_RW +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_n___POR 0x000000FF +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_n__RD___POR 0xF +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_n__WR___POR 0xF +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_n__RD___M 0x000000F0 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_n__RD___S 4 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_n__WR___M 0x0000000F +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_n__WR___S 0 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_n___M 0x000000FF +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_n___S 0 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_0 (0x00AB4410) +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_0___RWC QCSR_REG_RW +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_0__RD___M 0x000000F0 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_0__RD___S 4 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_0__WR___M 0x0000000F +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_0__WR___S 0 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_1 (0x00AB4414) +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_1___RWC QCSR_REG_RW +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_1__RD___M 0x000000F0 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_1__RD___S 4 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_1__WR___M 0x0000000F +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_1__WR___S 0 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_2 (0x00AB4418) +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_2___RWC QCSR_REG_RW +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_2__RD___M 0x000000F0 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_2__RD___S 4 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_2__WR___M 0x0000000F +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_2__WR___S 0 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_3 (0x00AB441C) +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_3___RWC QCSR_REG_RW +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_3__RD___M 0x000000F0 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_3__RD___S 4 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_3__WR___M 0x0000000F +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_3__WR___S 0 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_4 (0x00AB4420) +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_4___RWC QCSR_REG_RW +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_4__RD___M 0x000000F0 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_4__RD___S 4 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_4__WR___M 0x0000000F +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_4__WR___S 0 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_5 (0x00AB4424) +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_5___RWC QCSR_REG_RW +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_5__RD___M 0x000000F0 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_5__RD___S 4 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_5__WR___M 0x0000000F +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_5__WR___S 0 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_6 (0x00AB4428) +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_6___RWC QCSR_REG_RW +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_6__RD___M 0x000000F0 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_6__RD___S 4 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_6__WR___M 0x0000000F +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_6__WR___S 0 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_7 (0x00AB442C) +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_7___RWC QCSR_REG_RW +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_7__RD___M 0x000000F0 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_7__RD___S 4 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_7__WR___M 0x0000000F +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_7__WR___S 0 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_8 (0x00AB4430) +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_8___RWC QCSR_REG_RW +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_8__RD___M 0x000000F0 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_8__RD___S 4 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_8__WR___M 0x0000000F +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_8__WR___S 0 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_9 (0x00AB4434) +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_9___RWC QCSR_REG_RW +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_9__RD___M 0x000000F0 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_9__RD___S 4 +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_9__WR___M 0x0000000F +#define WMAC0_SFM_R1_CLIENT_READY_THRESHOLD_9__WR___S 0 + +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_n(n) (0x00AB4438+0x4*(n)) +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_n_nMIN 0 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_n_nMAX 9 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_n_ELEM 10 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_n___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_n___POR 0x00000000 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_n__RD___POR 0x0 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_n__WR___POR 0x0 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_n__RD___M 0x00000002 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_n__RD___S 1 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_n__WR___M 0x00000001 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_n__WR___S 0 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_n___M 0x00000003 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_n___S 0 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_0 (0x00AB4438) +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_0___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_0__RD___M 0x00000002 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_0__RD___S 1 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_0__WR___M 0x00000001 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_0__WR___S 0 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_1 (0x00AB443C) +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_1___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_1__RD___M 0x00000002 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_1__RD___S 1 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_1__WR___M 0x00000001 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_1__WR___S 0 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_2 (0x00AB4440) +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_2___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_2__RD___M 0x00000002 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_2__RD___S 1 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_2__WR___M 0x00000001 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_2__WR___S 0 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_3 (0x00AB4444) +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_3___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_3__RD___M 0x00000002 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_3__RD___S 1 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_3__WR___M 0x00000001 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_3__WR___S 0 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_4 (0x00AB4448) +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_4___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_4__RD___M 0x00000002 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_4__RD___S 1 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_4__WR___M 0x00000001 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_4__WR___S 0 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_5 (0x00AB444C) +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_5___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_5__RD___M 0x00000002 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_5__RD___S 1 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_5__WR___M 0x00000001 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_5__WR___S 0 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_6 (0x00AB4450) +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_6___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_6__RD___M 0x00000002 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_6__RD___S 1 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_6__WR___M 0x00000001 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_6__WR___S 0 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_7 (0x00AB4454) +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_7___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_7__RD___M 0x00000002 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_7__RD___S 1 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_7__WR___M 0x00000001 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_7__WR___S 0 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_8 (0x00AB4458) +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_8___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_8__RD___M 0x00000002 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_8__RD___S 1 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_8__WR___M 0x00000001 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_8__WR___S 0 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_9 (0x00AB445C) +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_9___RWC QCSR_REG_RO +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_9__RD___M 0x00000002 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_9__RD___S 1 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_9__WR___M 0x00000001 +#define WMAC0_SFM_R1_CLIENT_READY_TIMEOUT_9__WR___S 0 + + +#define DBG (0x00B90000) + +#define DBG_CSR_ROM_WORD (0x00B90000) +#define DBG_CSR_ROM_WORD___RWC QCSR_REG_RO +#define DBG_CSR_ROM_WORD___POR 0x00001007 +#define DBG_CSR_ROM_WORD__ADDR_OFFSET___POR 0x00001 +#define DBG_CSR_ROM_WORD__PWRDMNID___POR 0x00 +#define DBG_CSR_ROM_WORD__PWRDMNID_VAL___POR 0x1 +#define DBG_CSR_ROM_WORD__FORMAT___POR 0x1 +#define DBG_CSR_ROM_WORD__PRESENT___POR 0x1 +#define DBG_CSR_ROM_WORD__ADDR_OFFSET___M 0xFFFFF000 +#define DBG_CSR_ROM_WORD__ADDR_OFFSET___S 12 +#define DBG_CSR_ROM_WORD__PWRDMNID___M 0x000001F0 +#define DBG_CSR_ROM_WORD__PWRDMNID___S 4 +#define DBG_CSR_ROM_WORD__PWRDMNID_VAL___M 0x00000004 +#define DBG_CSR_ROM_WORD__PWRDMNID_VAL___S 2 +#define DBG_CSR_ROM_WORD__FORMAT___M 0x00000002 +#define DBG_CSR_ROM_WORD__FORMAT___S 1 +#define DBG_CSR_ROM_WORD__PRESENT___M 0x00000001 +#define DBG_CSR_ROM_WORD__PRESENT___S 0 +#define DBG_CSR_ROM_WORD___M 0xFFFFF1F7 +#define DBG_CSR_ROM_WORD___S 0 + +#define DBG_TSGEN_ROM_WORD (0x00B90004) +#define DBG_TSGEN_ROM_WORD___RWC QCSR_REG_RO +#define DBG_TSGEN_ROM_WORD___POR 0x00002007 +#define DBG_TSGEN_ROM_WORD__ADDR_OFFSET___POR 0x00002 +#define DBG_TSGEN_ROM_WORD__PWRDMNID___POR 0x00 +#define DBG_TSGEN_ROM_WORD__PWRDMNID_VAL___POR 0x1 +#define DBG_TSGEN_ROM_WORD__FORMAT___POR 0x1 +#define DBG_TSGEN_ROM_WORD__PRESENT___POR 0x1 +#define DBG_TSGEN_ROM_WORD__ADDR_OFFSET___M 0xFFFFF000 +#define DBG_TSGEN_ROM_WORD__ADDR_OFFSET___S 12 +#define DBG_TSGEN_ROM_WORD__PWRDMNID___M 0x000001F0 +#define DBG_TSGEN_ROM_WORD__PWRDMNID___S 4 +#define DBG_TSGEN_ROM_WORD__PWRDMNID_VAL___M 0x00000004 +#define DBG_TSGEN_ROM_WORD__PWRDMNID_VAL___S 2 +#define DBG_TSGEN_ROM_WORD__FORMAT___M 0x00000002 +#define DBG_TSGEN_ROM_WORD__FORMAT___S 1 +#define DBG_TSGEN_ROM_WORD__PRESENT___M 0x00000001 +#define DBG_TSGEN_ROM_WORD__PRESENT___S 0 +#define DBG_TSGEN_ROM_WORD___M 0xFFFFF1F7 +#define DBG_TSGEN_ROM_WORD___S 0 + +#define DBG_CTI_DBG_ROM_WORD (0x00B90008) +#define DBG_CTI_DBG_ROM_WORD___RWC QCSR_REG_RO +#define DBG_CTI_DBG_ROM_WORD___POR 0x00004007 +#define DBG_CTI_DBG_ROM_WORD__ADDR_OFFSET___POR 0x00004 +#define DBG_CTI_DBG_ROM_WORD__PWRDMNID___POR 0x00 +#define DBG_CTI_DBG_ROM_WORD__PWRDMNID_VAL___POR 0x1 +#define DBG_CTI_DBG_ROM_WORD__FORMAT___POR 0x1 +#define DBG_CTI_DBG_ROM_WORD__PRESENT___POR 0x1 +#define DBG_CTI_DBG_ROM_WORD__ADDR_OFFSET___M 0xFFFFF000 +#define DBG_CTI_DBG_ROM_WORD__ADDR_OFFSET___S 12 +#define DBG_CTI_DBG_ROM_WORD__PWRDMNID___M 0x000001F0 +#define DBG_CTI_DBG_ROM_WORD__PWRDMNID___S 4 +#define DBG_CTI_DBG_ROM_WORD__PWRDMNID_VAL___M 0x00000004 +#define DBG_CTI_DBG_ROM_WORD__PWRDMNID_VAL___S 2 +#define DBG_CTI_DBG_ROM_WORD__FORMAT___M 0x00000002 +#define DBG_CTI_DBG_ROM_WORD__FORMAT___S 1 +#define DBG_CTI_DBG_ROM_WORD__PRESENT___M 0x00000001 +#define DBG_CTI_DBG_ROM_WORD__PRESENT___S 0 +#define DBG_CTI_DBG_ROM_WORD___M 0xFFFFF1F7 +#define DBG_CTI_DBG_ROM_WORD___S 0 + +#define DBG_CTI_NOC_ROM_WORD (0x00B9000C) +#define DBG_CTI_NOC_ROM_WORD___RWC QCSR_REG_RO +#define DBG_CTI_NOC_ROM_WORD___POR 0x00005007 +#define DBG_CTI_NOC_ROM_WORD__ADDR_OFFSET___POR 0x00005 +#define DBG_CTI_NOC_ROM_WORD__PWRDMNID___POR 0x00 +#define DBG_CTI_NOC_ROM_WORD__PWRDMNID_VAL___POR 0x1 +#define DBG_CTI_NOC_ROM_WORD__FORMAT___POR 0x1 +#define DBG_CTI_NOC_ROM_WORD__PRESENT___POR 0x1 +#define DBG_CTI_NOC_ROM_WORD__ADDR_OFFSET___M 0xFFFFF000 +#define DBG_CTI_NOC_ROM_WORD__ADDR_OFFSET___S 12 +#define DBG_CTI_NOC_ROM_WORD__PWRDMNID___M 0x000001F0 +#define DBG_CTI_NOC_ROM_WORD__PWRDMNID___S 4 +#define DBG_CTI_NOC_ROM_WORD__PWRDMNID_VAL___M 0x00000004 +#define DBG_CTI_NOC_ROM_WORD__PWRDMNID_VAL___S 2 +#define DBG_CTI_NOC_ROM_WORD__FORMAT___M 0x00000002 +#define DBG_CTI_NOC_ROM_WORD__FORMAT___S 1 +#define DBG_CTI_NOC_ROM_WORD__PRESENT___M 0x00000001 +#define DBG_CTI_NOC_ROM_WORD__PRESENT___S 0 +#define DBG_CTI_NOC_ROM_WORD___M 0xFFFFF1F7 +#define DBG_CTI_NOC_ROM_WORD___S 0 + +#define DBG_CTI_INTR_ROM_WORD (0x00B90010) +#define DBG_CTI_INTR_ROM_WORD___RWC QCSR_REG_RO +#define DBG_CTI_INTR_ROM_WORD___POR 0x00006007 +#define DBG_CTI_INTR_ROM_WORD__ADDR_OFFSET___POR 0x00006 +#define DBG_CTI_INTR_ROM_WORD__PWRDMNID___POR 0x00 +#define DBG_CTI_INTR_ROM_WORD__PWRDMNID_VAL___POR 0x1 +#define DBG_CTI_INTR_ROM_WORD__FORMAT___POR 0x1 +#define DBG_CTI_INTR_ROM_WORD__PRESENT___POR 0x1 +#define DBG_CTI_INTR_ROM_WORD__ADDR_OFFSET___M 0xFFFFF000 +#define DBG_CTI_INTR_ROM_WORD__ADDR_OFFSET___S 12 +#define DBG_CTI_INTR_ROM_WORD__PWRDMNID___M 0x000001F0 +#define DBG_CTI_INTR_ROM_WORD__PWRDMNID___S 4 +#define DBG_CTI_INTR_ROM_WORD__PWRDMNID_VAL___M 0x00000004 +#define DBG_CTI_INTR_ROM_WORD__PWRDMNID_VAL___S 2 +#define DBG_CTI_INTR_ROM_WORD__FORMAT___M 0x00000002 +#define DBG_CTI_INTR_ROM_WORD__FORMAT___S 1 +#define DBG_CTI_INTR_ROM_WORD__PRESENT___M 0x00000001 +#define DBG_CTI_INTR_ROM_WORD__PRESENT___S 0 +#define DBG_CTI_INTR_ROM_WORD___M 0xFFFFF1F7 +#define DBG_CTI_INTR_ROM_WORD___S 0 + +#define DBG_TPDM_CSR_ROM_WORD (0x00B90014) +#define DBG_TPDM_CSR_ROM_WORD___RWC QCSR_REG_RO +#define DBG_TPDM_CSR_ROM_WORD___POR 0x00011007 +#define DBG_TPDM_CSR_ROM_WORD__ADDR_OFFSET___POR 0x00011 +#define DBG_TPDM_CSR_ROM_WORD__PWRDMNID___POR 0x00 +#define DBG_TPDM_CSR_ROM_WORD__PWRDMNID_VAL___POR 0x1 +#define DBG_TPDM_CSR_ROM_WORD__FORMAT___POR 0x1 +#define DBG_TPDM_CSR_ROM_WORD__PRESENT___POR 0x1 +#define DBG_TPDM_CSR_ROM_WORD__ADDR_OFFSET___M 0xFFFFF000 +#define DBG_TPDM_CSR_ROM_WORD__ADDR_OFFSET___S 12 +#define DBG_TPDM_CSR_ROM_WORD__PWRDMNID___M 0x000001F0 +#define DBG_TPDM_CSR_ROM_WORD__PWRDMNID___S 4 +#define DBG_TPDM_CSR_ROM_WORD__PWRDMNID_VAL___M 0x00000004 +#define DBG_TPDM_CSR_ROM_WORD__PWRDMNID_VAL___S 2 +#define DBG_TPDM_CSR_ROM_WORD__FORMAT___M 0x00000002 +#define DBG_TPDM_CSR_ROM_WORD__FORMAT___S 1 +#define DBG_TPDM_CSR_ROM_WORD__PRESENT___M 0x00000001 +#define DBG_TPDM_CSR_ROM_WORD__PRESENT___S 0 +#define DBG_TPDM_CSR_ROM_WORD___M 0xFFFFF1F7 +#define DBG_TPDM_CSR_ROM_WORD___S 0 + +#define DBG_TPDA_CSR_ROM_WORD (0x00B90018) +#define DBG_TPDA_CSR_ROM_WORD___RWC QCSR_REG_RO +#define DBG_TPDA_CSR_ROM_WORD___POR 0x00012007 +#define DBG_TPDA_CSR_ROM_WORD__ADDR_OFFSET___POR 0x00012 +#define DBG_TPDA_CSR_ROM_WORD__PWRDMNID___POR 0x00 +#define DBG_TPDA_CSR_ROM_WORD__PWRDMNID_VAL___POR 0x1 +#define DBG_TPDA_CSR_ROM_WORD__FORMAT___POR 0x1 +#define DBG_TPDA_CSR_ROM_WORD__PRESENT___POR 0x1 +#define DBG_TPDA_CSR_ROM_WORD__ADDR_OFFSET___M 0xFFFFF000 +#define DBG_TPDA_CSR_ROM_WORD__ADDR_OFFSET___S 12 +#define DBG_TPDA_CSR_ROM_WORD__PWRDMNID___M 0x000001F0 +#define DBG_TPDA_CSR_ROM_WORD__PWRDMNID___S 4 +#define DBG_TPDA_CSR_ROM_WORD__PWRDMNID_VAL___M 0x00000004 +#define DBG_TPDA_CSR_ROM_WORD__PWRDMNID_VAL___S 2 +#define DBG_TPDA_CSR_ROM_WORD__FORMAT___M 0x00000002 +#define DBG_TPDA_CSR_ROM_WORD__FORMAT___S 1 +#define DBG_TPDA_CSR_ROM_WORD__PRESENT___M 0x00000001 +#define DBG_TPDA_CSR_ROM_WORD__PRESENT___S 0 +#define DBG_TPDA_CSR_ROM_WORD___M 0xFFFFF1F7 +#define DBG_TPDA_CSR_ROM_WORD___S 0 + +#define DBG_FUN_ROM_WORD (0x00B9001C) +#define DBG_FUN_ROM_WORD___RWC QCSR_REG_RO +#define DBG_FUN_ROM_WORD___POR 0x00013007 +#define DBG_FUN_ROM_WORD__ADDR_OFFSET___POR 0x00013 +#define DBG_FUN_ROM_WORD__PWRDMNID___POR 0x00 +#define DBG_FUN_ROM_WORD__PWRDMNID_VAL___POR 0x1 +#define DBG_FUN_ROM_WORD__FORMAT___POR 0x1 +#define DBG_FUN_ROM_WORD__PRESENT___POR 0x1 +#define DBG_FUN_ROM_WORD__ADDR_OFFSET___M 0xFFFFF000 +#define DBG_FUN_ROM_WORD__ADDR_OFFSET___S 12 +#define DBG_FUN_ROM_WORD__PWRDMNID___M 0x000001F0 +#define DBG_FUN_ROM_WORD__PWRDMNID___S 4 +#define DBG_FUN_ROM_WORD__PWRDMNID_VAL___M 0x00000004 +#define DBG_FUN_ROM_WORD__PWRDMNID_VAL___S 2 +#define DBG_FUN_ROM_WORD__FORMAT___M 0x00000002 +#define DBG_FUN_ROM_WORD__FORMAT___S 1 +#define DBG_FUN_ROM_WORD__PRESENT___M 0x00000001 +#define DBG_FUN_ROM_WORD__PRESENT___S 0 +#define DBG_FUN_ROM_WORD___M 0xFFFFF1F7 +#define DBG_FUN_ROM_WORD___S 0 + +#define DBG_ETBETF_ROM_WORD (0x00B90020) +#define DBG_ETBETF_ROM_WORD___RWC QCSR_REG_RO +#define DBG_ETBETF_ROM_WORD___POR 0x00014007 +#define DBG_ETBETF_ROM_WORD__ADDR_OFFSET___POR 0x00014 +#define DBG_ETBETF_ROM_WORD__PWRDMNID___POR 0x00 +#define DBG_ETBETF_ROM_WORD__PWRDMNID_VAL___POR 0x1 +#define DBG_ETBETF_ROM_WORD__FORMAT___POR 0x1 +#define DBG_ETBETF_ROM_WORD__PRESENT___POR 0x1 +#define DBG_ETBETF_ROM_WORD__ADDR_OFFSET___M 0xFFFFF000 +#define DBG_ETBETF_ROM_WORD__ADDR_OFFSET___S 12 +#define DBG_ETBETF_ROM_WORD__PWRDMNID___M 0x000001F0 +#define DBG_ETBETF_ROM_WORD__PWRDMNID___S 4 +#define DBG_ETBETF_ROM_WORD__PWRDMNID_VAL___M 0x00000004 +#define DBG_ETBETF_ROM_WORD__PWRDMNID_VAL___S 2 +#define DBG_ETBETF_ROM_WORD__FORMAT___M 0x00000002 +#define DBG_ETBETF_ROM_WORD__FORMAT___S 1 +#define DBG_ETBETF_ROM_WORD__PRESENT___M 0x00000001 +#define DBG_ETBETF_ROM_WORD__PRESENT___S 0 +#define DBG_ETBETF_ROM_WORD___M 0xFFFFF1F7 +#define DBG_ETBETF_ROM_WORD___S 0 + +#define DBG_OUTFUN_ROM_WORD (0x00B90024) +#define DBG_OUTFUN_ROM_WORD___RWC QCSR_REG_RO +#define DBG_OUTFUN_ROM_WORD___POR 0x00016007 +#define DBG_OUTFUN_ROM_WORD__ADDR_OFFSET___POR 0x00016 +#define DBG_OUTFUN_ROM_WORD__PWRDMNID___POR 0x00 +#define DBG_OUTFUN_ROM_WORD__PWRDMNID_VAL___POR 0x1 +#define DBG_OUTFUN_ROM_WORD__FORMAT___POR 0x1 +#define DBG_OUTFUN_ROM_WORD__PRESENT___POR 0x1 +#define DBG_OUTFUN_ROM_WORD__ADDR_OFFSET___M 0xFFFFF000 +#define DBG_OUTFUN_ROM_WORD__ADDR_OFFSET___S 12 +#define DBG_OUTFUN_ROM_WORD__PWRDMNID___M 0x000001F0 +#define DBG_OUTFUN_ROM_WORD__PWRDMNID___S 4 +#define DBG_OUTFUN_ROM_WORD__PWRDMNID_VAL___M 0x00000004 +#define DBG_OUTFUN_ROM_WORD__PWRDMNID_VAL___S 2 +#define DBG_OUTFUN_ROM_WORD__FORMAT___M 0x00000002 +#define DBG_OUTFUN_ROM_WORD__FORMAT___S 1 +#define DBG_OUTFUN_ROM_WORD__PRESENT___M 0x00000001 +#define DBG_OUTFUN_ROM_WORD__PRESENT___S 0 +#define DBG_OUTFUN_ROM_WORD___M 0xFFFFF1F7 +#define DBG_OUTFUN_ROM_WORD___S 0 + +#define DBG_GPWRREQ_ROM_WORD (0x00B90028) +#define DBG_GPWRREQ_ROM_WORD___RWC QCSR_REG_RO +#define DBG_GPWRREQ_ROM_WORD___POR 0x0007E047 +#define DBG_GPWRREQ_ROM_WORD__ADDR_OFFSET___POR 0x0007E +#define DBG_GPWRREQ_ROM_WORD__PWRDMNID___POR 0x04 +#define DBG_GPWRREQ_ROM_WORD__PWRDMNID_VAL___POR 0x1 +#define DBG_GPWRREQ_ROM_WORD__FORMAT___POR 0x1 +#define DBG_GPWRREQ_ROM_WORD__PRESENT___POR 0x1 +#define DBG_GPWRREQ_ROM_WORD__ADDR_OFFSET___M 0xFFFFF000 +#define DBG_GPWRREQ_ROM_WORD__ADDR_OFFSET___S 12 +#define DBG_GPWRREQ_ROM_WORD__PWRDMNID___M 0x000001F0 +#define DBG_GPWRREQ_ROM_WORD__PWRDMNID___S 4 +#define DBG_GPWRREQ_ROM_WORD__PWRDMNID_VAL___M 0x00000004 +#define DBG_GPWRREQ_ROM_WORD__PWRDMNID_VAL___S 2 +#define DBG_GPWRREQ_ROM_WORD__FORMAT___M 0x00000002 +#define DBG_GPWRREQ_ROM_WORD__FORMAT___S 1 +#define DBG_GPWRREQ_ROM_WORD__PRESENT___M 0x00000001 +#define DBG_GPWRREQ_ROM_WORD__PRESENT___S 0 +#define DBG_GPWRREQ_ROM_WORD___M 0xFFFFF1F7 +#define DBG_GPWRREQ_ROM_WORD___S 0 + +#define DBG_PHYA_FUN_ROM_WORD (0x00B9002C) +#define DBG_PHYA_FUN_ROM_WORD___RWC QCSR_REG_RO +#define DBG_PHYA_FUN_ROM_WORD___POR 0x00054027 +#define DBG_PHYA_FUN_ROM_WORD__ADDR_OFFSET___POR 0x54 +#define DBG_PHYA_FUN_ROM_WORD__PWRDMNID___POR 0x02 +#define DBG_PHYA_FUN_ROM_WORD__PWRDMNID_VAL___POR 0x1 +#define DBG_PHYA_FUN_ROM_WORD__FORMAT___POR 0x1 +#define DBG_PHYA_FUN_ROM_WORD__PRESENT___POR 0x1 +#define DBG_PHYA_FUN_ROM_WORD__ADDR_OFFSET___M 0xFFFFF000 +#define DBG_PHYA_FUN_ROM_WORD__ADDR_OFFSET___S 12 +#define DBG_PHYA_FUN_ROM_WORD__PWRDMNID___M 0x000001F0 +#define DBG_PHYA_FUN_ROM_WORD__PWRDMNID___S 4 +#define DBG_PHYA_FUN_ROM_WORD__PWRDMNID_VAL___M 0x00000004 +#define DBG_PHYA_FUN_ROM_WORD__PWRDMNID_VAL___S 2 +#define DBG_PHYA_FUN_ROM_WORD__FORMAT___M 0x00000002 +#define DBG_PHYA_FUN_ROM_WORD__FORMAT___S 1 +#define DBG_PHYA_FUN_ROM_WORD__PRESENT___M 0x00000001 +#define DBG_PHYA_FUN_ROM_WORD__PRESENT___S 0 +#define DBG_PHYA_FUN_ROM_WORD___M 0xFFFFF1F7 +#define DBG_PHYA_FUN_ROM_WORD___S 0 + +#define DBG_PHYA_CTI_ROM_WORD (0x00B90030) +#define DBG_PHYA_CTI_ROM_WORD___RWC QCSR_REG_RO +#define DBG_PHYA_CTI_ROM_WORD___POR 0x00055027 +#define DBG_PHYA_CTI_ROM_WORD__ADDR_OFFSET___POR 0x55 +#define DBG_PHYA_CTI_ROM_WORD__PWRDMNID___POR 0x02 +#define DBG_PHYA_CTI_ROM_WORD__PWRDMNID_VAL___POR 0x1 +#define DBG_PHYA_CTI_ROM_WORD__FORMAT___POR 0x1 +#define DBG_PHYA_CTI_ROM_WORD__PRESENT___POR 0x1 +#define DBG_PHYA_CTI_ROM_WORD__ADDR_OFFSET___M 0xFFFFF000 +#define DBG_PHYA_CTI_ROM_WORD__ADDR_OFFSET___S 12 +#define DBG_PHYA_CTI_ROM_WORD__PWRDMNID___M 0x000001F0 +#define DBG_PHYA_CTI_ROM_WORD__PWRDMNID___S 4 +#define DBG_PHYA_CTI_ROM_WORD__PWRDMNID_VAL___M 0x00000004 +#define DBG_PHYA_CTI_ROM_WORD__PWRDMNID_VAL___S 2 +#define DBG_PHYA_CTI_ROM_WORD__FORMAT___M 0x00000002 +#define DBG_PHYA_CTI_ROM_WORD__FORMAT___S 1 +#define DBG_PHYA_CTI_ROM_WORD__PRESENT___M 0x00000001 +#define DBG_PHYA_CTI_ROM_WORD__PRESENT___S 0 +#define DBG_PHYA_CTI_ROM_WORD___M 0xFFFFF1F7 +#define DBG_PHYA_CTI_ROM_WORD___S 0 + +#define DBG_PHYA_M3_ITM_ROM_WORD (0x00B90034) +#define DBG_PHYA_M3_ITM_ROM_WORD___RWC QCSR_REG_RO +#define DBG_PHYA_M3_ITM_ROM_WORD___POR 0x00058027 +#define DBG_PHYA_M3_ITM_ROM_WORD__ADDR_OFFSET___POR 0x58 +#define DBG_PHYA_M3_ITM_ROM_WORD__PWRDMNID___POR 0x02 +#define DBG_PHYA_M3_ITM_ROM_WORD__PWRDMNID_VAL___POR 0x1 +#define DBG_PHYA_M3_ITM_ROM_WORD__FORMAT___POR 0x1 +#define DBG_PHYA_M3_ITM_ROM_WORD__PRESENT___POR 0x1 +#define DBG_PHYA_M3_ITM_ROM_WORD__ADDR_OFFSET___M 0xFFFFF000 +#define DBG_PHYA_M3_ITM_ROM_WORD__ADDR_OFFSET___S 12 +#define DBG_PHYA_M3_ITM_ROM_WORD__PWRDMNID___M 0x000001F0 +#define DBG_PHYA_M3_ITM_ROM_WORD__PWRDMNID___S 4 +#define DBG_PHYA_M3_ITM_ROM_WORD__PWRDMNID_VAL___M 0x00000004 +#define DBG_PHYA_M3_ITM_ROM_WORD__PWRDMNID_VAL___S 2 +#define DBG_PHYA_M3_ITM_ROM_WORD__FORMAT___M 0x00000002 +#define DBG_PHYA_M3_ITM_ROM_WORD__FORMAT___S 1 +#define DBG_PHYA_M3_ITM_ROM_WORD__PRESENT___M 0x00000001 +#define DBG_PHYA_M3_ITM_ROM_WORD__PRESENT___S 0 +#define DBG_PHYA_M3_ITM_ROM_WORD___M 0xFFFFF1F7 +#define DBG_PHYA_M3_ITM_ROM_WORD___S 0 + +#define DBG_PHYA_M3_DWT_ROM_WORD (0x00B90038) +#define DBG_PHYA_M3_DWT_ROM_WORD___RWC QCSR_REG_RO +#define DBG_PHYA_M3_DWT_ROM_WORD___POR 0x00059027 +#define DBG_PHYA_M3_DWT_ROM_WORD__ADDR_OFFSET___POR 0x59 +#define DBG_PHYA_M3_DWT_ROM_WORD__PWRDMNID___POR 0x02 +#define DBG_PHYA_M3_DWT_ROM_WORD__PWRDMNID_VAL___POR 0x1 +#define DBG_PHYA_M3_DWT_ROM_WORD__FORMAT___POR 0x1 +#define DBG_PHYA_M3_DWT_ROM_WORD__PRESENT___POR 0x1 +#define DBG_PHYA_M3_DWT_ROM_WORD__ADDR_OFFSET___M 0xFFFFF000 +#define DBG_PHYA_M3_DWT_ROM_WORD__ADDR_OFFSET___S 12 +#define DBG_PHYA_M3_DWT_ROM_WORD__PWRDMNID___M 0x000001F0 +#define DBG_PHYA_M3_DWT_ROM_WORD__PWRDMNID___S 4 +#define DBG_PHYA_M3_DWT_ROM_WORD__PWRDMNID_VAL___M 0x00000004 +#define DBG_PHYA_M3_DWT_ROM_WORD__PWRDMNID_VAL___S 2 +#define DBG_PHYA_M3_DWT_ROM_WORD__FORMAT___M 0x00000002 +#define DBG_PHYA_M3_DWT_ROM_WORD__FORMAT___S 1 +#define DBG_PHYA_M3_DWT_ROM_WORD__PRESENT___M 0x00000001 +#define DBG_PHYA_M3_DWT_ROM_WORD__PRESENT___S 0 +#define DBG_PHYA_M3_DWT_ROM_WORD___M 0xFFFFF1F7 +#define DBG_PHYA_M3_DWT_ROM_WORD___S 0 + +#define DBG_PHYA_M3_FPB_ROM_WORD (0x00B9003C) +#define DBG_PHYA_M3_FPB_ROM_WORD___RWC QCSR_REG_RO +#define DBG_PHYA_M3_FPB_ROM_WORD___POR 0x0005A027 +#define DBG_PHYA_M3_FPB_ROM_WORD__ADDR_OFFSET___POR 0x5A +#define DBG_PHYA_M3_FPB_ROM_WORD__PWRDMNID___POR 0x02 +#define DBG_PHYA_M3_FPB_ROM_WORD__PWRDMNID_VAL___POR 0x1 +#define DBG_PHYA_M3_FPB_ROM_WORD__FORMAT___POR 0x1 +#define DBG_PHYA_M3_FPB_ROM_WORD__PRESENT___POR 0x1 +#define DBG_PHYA_M3_FPB_ROM_WORD__ADDR_OFFSET___M 0xFFFFF000 +#define DBG_PHYA_M3_FPB_ROM_WORD__ADDR_OFFSET___S 12 +#define DBG_PHYA_M3_FPB_ROM_WORD__PWRDMNID___M 0x000001F0 +#define DBG_PHYA_M3_FPB_ROM_WORD__PWRDMNID___S 4 +#define DBG_PHYA_M3_FPB_ROM_WORD__PWRDMNID_VAL___M 0x00000004 +#define DBG_PHYA_M3_FPB_ROM_WORD__PWRDMNID_VAL___S 2 +#define DBG_PHYA_M3_FPB_ROM_WORD__FORMAT___M 0x00000002 +#define DBG_PHYA_M3_FPB_ROM_WORD__FORMAT___S 1 +#define DBG_PHYA_M3_FPB_ROM_WORD__PRESENT___M 0x00000001 +#define DBG_PHYA_M3_FPB_ROM_WORD__PRESENT___S 0 +#define DBG_PHYA_M3_FPB_ROM_WORD___M 0xFFFFF1F7 +#define DBG_PHYA_M3_FPB_ROM_WORD___S 0 + +#define DBG_PHYA_M3_SCS_ROM_WORD (0x00B90040) +#define DBG_PHYA_M3_SCS_ROM_WORD___RWC QCSR_REG_RO +#define DBG_PHYA_M3_SCS_ROM_WORD___POR 0x0005B027 +#define DBG_PHYA_M3_SCS_ROM_WORD__ADDR_OFFSET___POR 0x5B +#define DBG_PHYA_M3_SCS_ROM_WORD__PWRDMNID___POR 0x02 +#define DBG_PHYA_M3_SCS_ROM_WORD__PWRDMNID_VAL___POR 0x1 +#define DBG_PHYA_M3_SCS_ROM_WORD__FORMAT___POR 0x1 +#define DBG_PHYA_M3_SCS_ROM_WORD__PRESENT___POR 0x1 +#define DBG_PHYA_M3_SCS_ROM_WORD__ADDR_OFFSET___M 0xFFFFF000 +#define DBG_PHYA_M3_SCS_ROM_WORD__ADDR_OFFSET___S 12 +#define DBG_PHYA_M3_SCS_ROM_WORD__PWRDMNID___M 0x000001F0 +#define DBG_PHYA_M3_SCS_ROM_WORD__PWRDMNID___S 4 +#define DBG_PHYA_M3_SCS_ROM_WORD__PWRDMNID_VAL___M 0x00000004 +#define DBG_PHYA_M3_SCS_ROM_WORD__PWRDMNID_VAL___S 2 +#define DBG_PHYA_M3_SCS_ROM_WORD__FORMAT___M 0x00000002 +#define DBG_PHYA_M3_SCS_ROM_WORD__FORMAT___S 1 +#define DBG_PHYA_M3_SCS_ROM_WORD__PRESENT___M 0x00000001 +#define DBG_PHYA_M3_SCS_ROM_WORD__PRESENT___S 0 +#define DBG_PHYA_M3_SCS_ROM_WORD___M 0xFFFFF1F7 +#define DBG_PHYA_M3_SCS_ROM_WORD___S 0 + +#define DBG_PHYA_M3_ETM_ROM_WORD (0x00B90044) +#define DBG_PHYA_M3_ETM_ROM_WORD___RWC QCSR_REG_RO +#define DBG_PHYA_M3_ETM_ROM_WORD___POR 0x0005C027 +#define DBG_PHYA_M3_ETM_ROM_WORD__ADDR_OFFSET___POR 0x5C +#define DBG_PHYA_M3_ETM_ROM_WORD__PWRDMNID___POR 0x02 +#define DBG_PHYA_M3_ETM_ROM_WORD__PWRDMNID_VAL___POR 0x1 +#define DBG_PHYA_M3_ETM_ROM_WORD__FORMAT___POR 0x1 +#define DBG_PHYA_M3_ETM_ROM_WORD__PRESENT___POR 0x1 +#define DBG_PHYA_M3_ETM_ROM_WORD__ADDR_OFFSET___M 0xFFFFF000 +#define DBG_PHYA_M3_ETM_ROM_WORD__ADDR_OFFSET___S 12 +#define DBG_PHYA_M3_ETM_ROM_WORD__PWRDMNID___M 0x000001F0 +#define DBG_PHYA_M3_ETM_ROM_WORD__PWRDMNID___S 4 +#define DBG_PHYA_M3_ETM_ROM_WORD__PWRDMNID_VAL___M 0x00000004 +#define DBG_PHYA_M3_ETM_ROM_WORD__PWRDMNID_VAL___S 2 +#define DBG_PHYA_M3_ETM_ROM_WORD__FORMAT___M 0x00000002 +#define DBG_PHYA_M3_ETM_ROM_WORD__FORMAT___S 1 +#define DBG_PHYA_M3_ETM_ROM_WORD__PRESENT___M 0x00000001 +#define DBG_PHYA_M3_ETM_ROM_WORD__PRESENT___S 0 +#define DBG_PHYA_M3_ETM_ROM_WORD___M 0xFFFFF1F7 +#define DBG_PHYA_M3_ETM_ROM_WORD___S 0 + +#define DBG_PHYA_M3_CTI_ROM_WORD (0x00B90048) +#define DBG_PHYA_M3_CTI_ROM_WORD___RWC QCSR_REG_RO +#define DBG_PHYA_M3_CTI_ROM_WORD___POR 0x0005D027 +#define DBG_PHYA_M3_CTI_ROM_WORD__ADDR_OFFSET___POR 0x5D +#define DBG_PHYA_M3_CTI_ROM_WORD__PWRDMNID___POR 0x02 +#define DBG_PHYA_M3_CTI_ROM_WORD__PWRDMNID_VAL___POR 0x1 +#define DBG_PHYA_M3_CTI_ROM_WORD__FORMAT___POR 0x1 +#define DBG_PHYA_M3_CTI_ROM_WORD__PRESENT___POR 0x1 +#define DBG_PHYA_M3_CTI_ROM_WORD__ADDR_OFFSET___M 0xFFFFF000 +#define DBG_PHYA_M3_CTI_ROM_WORD__ADDR_OFFSET___S 12 +#define DBG_PHYA_M3_CTI_ROM_WORD__PWRDMNID___M 0x000001F0 +#define DBG_PHYA_M3_CTI_ROM_WORD__PWRDMNID___S 4 +#define DBG_PHYA_M3_CTI_ROM_WORD__PWRDMNID_VAL___M 0x00000004 +#define DBG_PHYA_M3_CTI_ROM_WORD__PWRDMNID_VAL___S 2 +#define DBG_PHYA_M3_CTI_ROM_WORD__FORMAT___M 0x00000002 +#define DBG_PHYA_M3_CTI_ROM_WORD__FORMAT___S 1 +#define DBG_PHYA_M3_CTI_ROM_WORD__PRESENT___M 0x00000001 +#define DBG_PHYA_M3_CTI_ROM_WORD__PRESENT___S 0 +#define DBG_PHYA_M3_CTI_ROM_WORD___M 0xFFFFF1F7 +#define DBG_PHYA_M3_CTI_ROM_WORD___S 0 + +#define DBG_DAPROM_TABLE_END (0x00B90080) +#define DBG_DAPROM_TABLE_END___RWC QCSR_REG_RO +#define DBG_DAPROM_TABLE_END___POR 0x00000000 +#define DBG_DAPROM_TABLE_END__DAPROM_TABLE_END___POR 0x00000000 +#define DBG_DAPROM_TABLE_END__DAPROM_TABLE_END___M 0xFFFFFFFF +#define DBG_DAPROM_TABLE_END__DAPROM_TABLE_END___S 0 +#define DBG_DAPROM_TABLE_END___M 0xFFFFFFFF +#define DBG_DAPROM_TABLE_END___S 0 + +#define DBG_DAPROM_MEMTYPE (0x00B90FCC) +#define DBG_DAPROM_MEMTYPE___RWC QCSR_REG_RO +#define DBG_DAPROM_MEMTYPE___POR 0x00000001 +#define DBG_DAPROM_MEMTYPE__SYSMEM___POR 0x1 +#define DBG_DAPROM_MEMTYPE__SYSMEM___M 0x00000001 +#define DBG_DAPROM_MEMTYPE__SYSMEM___S 0 +#define DBG_DAPROM_MEMTYPE___M 0x00000001 +#define DBG_DAPROM_MEMTYPE___S 0 + +#define DBG_DAPROM_PERIPHERAL_ID4 (0x00B90FD0) +#define DBG_DAPROM_PERIPHERAL_ID4___RWC QCSR_REG_RO +#define DBG_DAPROM_PERIPHERAL_ID4___POR 0x00000000 +#define DBG_DAPROM_PERIPHERAL_ID4__RFU___POR 0x000000 +#define DBG_DAPROM_PERIPHERAL_ID4__FIELD_4KB_COUNT___POR 0x0 +#define DBG_DAPROM_PERIPHERAL_ID4__JEP106_CC___POR 0x0 +#define DBG_DAPROM_PERIPHERAL_ID4__RFU___M 0xFFFFFF00 +#define DBG_DAPROM_PERIPHERAL_ID4__RFU___S 8 +#define DBG_DAPROM_PERIPHERAL_ID4__FIELD_4KB_COUNT___M 0x000000F0 +#define DBG_DAPROM_PERIPHERAL_ID4__FIELD_4KB_COUNT___S 4 +#define DBG_DAPROM_PERIPHERAL_ID4__JEP106_CC___M 0x0000000F +#define DBG_DAPROM_PERIPHERAL_ID4__JEP106_CC___S 0 +#define DBG_DAPROM_PERIPHERAL_ID4___M 0xFFFFFFFF +#define DBG_DAPROM_PERIPHERAL_ID4___S 0 + +#define DBG_DAPROM_PERIPHERAL_ID5 (0x00B90FD4) +#define DBG_DAPROM_PERIPHERAL_ID5___RWC QCSR_REG_RO +#define DBG_DAPROM_PERIPHERAL_ID5___POR 0x00000000 +#define DBG_DAPROM_PERIPHERAL_ID5__RFU___POR 0x00000000 +#define DBG_DAPROM_PERIPHERAL_ID5__SBZ___POR 0x0 +#define DBG_DAPROM_PERIPHERAL_ID5__RFU___M 0xFFFFFFFE +#define DBG_DAPROM_PERIPHERAL_ID5__RFU___S 1 +#define DBG_DAPROM_PERIPHERAL_ID5__SBZ___M 0x00000001 +#define DBG_DAPROM_PERIPHERAL_ID5__SBZ___S 0 +#define DBG_DAPROM_PERIPHERAL_ID5___M 0xFFFFFFFF +#define DBG_DAPROM_PERIPHERAL_ID5___S 0 + +#define DBG_DAPROM_PERIPHERAL_ID6 (0x00B90FD8) +#define DBG_DAPROM_PERIPHERAL_ID6___RWC QCSR_REG_RO +#define DBG_DAPROM_PERIPHERAL_ID6___POR 0x00000000 +#define DBG_DAPROM_PERIPHERAL_ID6__RFU___POR 0x000000 +#define DBG_DAPROM_PERIPHERAL_ID6__SBZ___POR 0x00 +#define DBG_DAPROM_PERIPHERAL_ID6__RFU___M 0xFFFFFF00 +#define DBG_DAPROM_PERIPHERAL_ID6__RFU___S 8 +#define DBG_DAPROM_PERIPHERAL_ID6__SBZ___M 0x000000FF +#define DBG_DAPROM_PERIPHERAL_ID6__SBZ___S 0 +#define DBG_DAPROM_PERIPHERAL_ID6___M 0xFFFFFFFF +#define DBG_DAPROM_PERIPHERAL_ID6___S 0 + +#define DBG_DAPROM_PERIPHERAL_ID7 (0x00B90FDC) +#define DBG_DAPROM_PERIPHERAL_ID7___RWC QCSR_REG_RO +#define DBG_DAPROM_PERIPHERAL_ID7___POR 0x00000000 +#define DBG_DAPROM_PERIPHERAL_ID7__RFU___POR 0x000000 +#define DBG_DAPROM_PERIPHERAL_ID7__SBZ___POR 0x00 +#define DBG_DAPROM_PERIPHERAL_ID7__RFU___M 0xFFFFFF00 +#define DBG_DAPROM_PERIPHERAL_ID7__RFU___S 8 +#define DBG_DAPROM_PERIPHERAL_ID7__SBZ___M 0x000000FF +#define DBG_DAPROM_PERIPHERAL_ID7__SBZ___S 0 +#define DBG_DAPROM_PERIPHERAL_ID7___M 0xFFFFFFFF +#define DBG_DAPROM_PERIPHERAL_ID7___S 0 + +#define DBG_DAPROM_PERIPHERAL_ID0 (0x00B90FE0) +#define DBG_DAPROM_PERIPHERAL_ID0___RWC QCSR_REG_RO +#define DBG_DAPROM_PERIPHERAL_ID0___POR 0x00000000 +#define DBG_DAPROM_PERIPHERAL_ID0__RFU___POR 0x000000 +#define DBG_DAPROM_PERIPHERAL_ID0__PART_NUM_7_0___POR 0x0 +#define DBG_DAPROM_PERIPHERAL_ID0__RFU___M 0xFFFFFF00 +#define DBG_DAPROM_PERIPHERAL_ID0__RFU___S 8 +#define DBG_DAPROM_PERIPHERAL_ID0__PART_NUM_7_0___M 0x000000FF +#define DBG_DAPROM_PERIPHERAL_ID0__PART_NUM_7_0___S 0 +#define DBG_DAPROM_PERIPHERAL_ID0___M 0xFFFFFFFF +#define DBG_DAPROM_PERIPHERAL_ID0___S 0 + +#define DBG_DAPROM_PERIPHERAL_ID1 (0x00B90FE4) +#define DBG_DAPROM_PERIPHERAL_ID1___RWC QCSR_REG_RO +#define DBG_DAPROM_PERIPHERAL_ID1___POR 0x00000000 +#define DBG_DAPROM_PERIPHERAL_ID1__RFU___POR 0x000000 +#define DBG_DAPROM_PERIPHERAL_ID1__JEP106_ID_3_0___POR 0x0 +#define DBG_DAPROM_PERIPHERAL_ID1__PART_NUM_11_8___POR 0x0 +#define DBG_DAPROM_PERIPHERAL_ID1__RFU___M 0xFFFFFF00 +#define DBG_DAPROM_PERIPHERAL_ID1__RFU___S 8 +#define DBG_DAPROM_PERIPHERAL_ID1__JEP106_ID_3_0___M 0x000000F0 +#define DBG_DAPROM_PERIPHERAL_ID1__JEP106_ID_3_0___S 4 +#define DBG_DAPROM_PERIPHERAL_ID1__PART_NUM_11_8___M 0x0000000F +#define DBG_DAPROM_PERIPHERAL_ID1__PART_NUM_11_8___S 0 +#define DBG_DAPROM_PERIPHERAL_ID1___M 0xFFFFFFFF +#define DBG_DAPROM_PERIPHERAL_ID1___S 0 + +#define DBG_DAPROM_PERIPHERAL_ID2 (0x00B90FE8) +#define DBG_DAPROM_PERIPHERAL_ID2___RWC QCSR_REG_RO +#define DBG_DAPROM_PERIPHERAL_ID2___POR 0x0000000F +#define DBG_DAPROM_PERIPHERAL_ID2__RFU___POR 0x000000 +#define DBG_DAPROM_PERIPHERAL_ID2__PERIPH_REV___POR 0x0 +#define DBG_DAPROM_PERIPHERAL_ID2__JEP106_ASS___POR 0x1 +#define DBG_DAPROM_PERIPHERAL_ID2__JEP106_ID_6_4___POR 0x7 +#define DBG_DAPROM_PERIPHERAL_ID2__RFU___M 0xFFFFFF00 +#define DBG_DAPROM_PERIPHERAL_ID2__RFU___S 8 +#define DBG_DAPROM_PERIPHERAL_ID2__PERIPH_REV___M 0x000000F0 +#define DBG_DAPROM_PERIPHERAL_ID2__PERIPH_REV___S 4 +#define DBG_DAPROM_PERIPHERAL_ID2__JEP106_ASS___M 0x00000008 +#define DBG_DAPROM_PERIPHERAL_ID2__JEP106_ASS___S 3 +#define DBG_DAPROM_PERIPHERAL_ID2__JEP106_ID_6_4___M 0x00000007 +#define DBG_DAPROM_PERIPHERAL_ID2__JEP106_ID_6_4___S 0 +#define DBG_DAPROM_PERIPHERAL_ID2___M 0xFFFFFFFF +#define DBG_DAPROM_PERIPHERAL_ID2___S 0 + +#define DBG_DAPROM_PERIPHERAL_ID3 (0x00B90FEC) +#define DBG_DAPROM_PERIPHERAL_ID3___RWC QCSR_REG_RO +#define DBG_DAPROM_PERIPHERAL_ID3___POR 0x00000000 +#define DBG_DAPROM_PERIPHERAL_ID3__RFU___POR 0x000000 +#define DBG_DAPROM_PERIPHERAL_ID3__REV_AND___POR 0x0 +#define DBG_DAPROM_PERIPHERAL_ID3__MODIFIED___POR 0x0 +#define DBG_DAPROM_PERIPHERAL_ID3__RFU___M 0xFFFFFF00 +#define DBG_DAPROM_PERIPHERAL_ID3__RFU___S 8 +#define DBG_DAPROM_PERIPHERAL_ID3__REV_AND___M 0x000000F0 +#define DBG_DAPROM_PERIPHERAL_ID3__REV_AND___S 4 +#define DBG_DAPROM_PERIPHERAL_ID3__MODIFIED___M 0x0000000F +#define DBG_DAPROM_PERIPHERAL_ID3__MODIFIED___S 0 +#define DBG_DAPROM_PERIPHERAL_ID3___M 0xFFFFFFFF +#define DBG_DAPROM_PERIPHERAL_ID3___S 0 + +#define DBG_DAPROM_COMPONENT_ID0 (0x00B90FF0) +#define DBG_DAPROM_COMPONENT_ID0___RWC QCSR_REG_RO +#define DBG_DAPROM_COMPONENT_ID0___POR 0x0000000D +#define DBG_DAPROM_COMPONENT_ID0__RFU___POR 0x000000 +#define DBG_DAPROM_COMPONENT_ID0__PREAMBLE_7_0___POR 0x0D +#define DBG_DAPROM_COMPONENT_ID0__RFU___M 0xFFFFFF00 +#define DBG_DAPROM_COMPONENT_ID0__RFU___S 8 +#define DBG_DAPROM_COMPONENT_ID0__PREAMBLE_7_0___M 0x000000FF +#define DBG_DAPROM_COMPONENT_ID0__PREAMBLE_7_0___S 0 +#define DBG_DAPROM_COMPONENT_ID0___M 0xFFFFFFFF +#define DBG_DAPROM_COMPONENT_ID0___S 0 + +#define DBG_DAPROM_COMPONENT_ID1 (0x00B90FF4) +#define DBG_DAPROM_COMPONENT_ID1___RWC QCSR_REG_RO +#define DBG_DAPROM_COMPONENT_ID1___POR 0x00000010 +#define DBG_DAPROM_COMPONENT_ID1__RFU___POR 0x000000 +#define DBG_DAPROM_COMPONENT_ID1__PREAMBLE_15_12___POR 0x1 +#define DBG_DAPROM_COMPONENT_ID1__PREAMBLE_11_8___POR 0x0 +#define DBG_DAPROM_COMPONENT_ID1__RFU___M 0xFFFFFF00 +#define DBG_DAPROM_COMPONENT_ID1__RFU___S 8 +#define DBG_DAPROM_COMPONENT_ID1__PREAMBLE_15_12___M 0x000000F0 +#define DBG_DAPROM_COMPONENT_ID1__PREAMBLE_15_12___S 4 +#define DBG_DAPROM_COMPONENT_ID1__PREAMBLE_11_8___M 0x0000000F +#define DBG_DAPROM_COMPONENT_ID1__PREAMBLE_11_8___S 0 +#define DBG_DAPROM_COMPONENT_ID1___M 0xFFFFFFFF +#define DBG_DAPROM_COMPONENT_ID1___S 0 + +#define DBG_DAPROM_COMPONENT_ID2 (0x00B90FF8) +#define DBG_DAPROM_COMPONENT_ID2___RWC QCSR_REG_RO +#define DBG_DAPROM_COMPONENT_ID2___POR 0x00000005 +#define DBG_DAPROM_COMPONENT_ID2__RFU___POR 0x000000 +#define DBG_DAPROM_COMPONENT_ID2__PREAMBLE_23_16___POR 0x05 +#define DBG_DAPROM_COMPONENT_ID2__RFU___M 0xFFFFFF00 +#define DBG_DAPROM_COMPONENT_ID2__RFU___S 8 +#define DBG_DAPROM_COMPONENT_ID2__PREAMBLE_23_16___M 0x000000FF +#define DBG_DAPROM_COMPONENT_ID2__PREAMBLE_23_16___S 0 +#define DBG_DAPROM_COMPONENT_ID2___M 0xFFFFFFFF +#define DBG_DAPROM_COMPONENT_ID2___S 0 + +#define DBG_DAPROM_COMPONENT_ID3 (0x00B90FFC) +#define DBG_DAPROM_COMPONENT_ID3___RWC QCSR_REG_RO +#define DBG_DAPROM_COMPONENT_ID3___POR 0x000000B1 +#define DBG_DAPROM_COMPONENT_ID3__RFU___POR 0x000000 +#define DBG_DAPROM_COMPONENT_ID3__PREAMBLE_31_24___POR 0xB1 +#define DBG_DAPROM_COMPONENT_ID3__RFU___M 0xFFFFFF00 +#define DBG_DAPROM_COMPONENT_ID3__RFU___S 8 +#define DBG_DAPROM_COMPONENT_ID3__PREAMBLE_31_24___M 0x000000FF +#define DBG_DAPROM_COMPONENT_ID3__PREAMBLE_31_24___S 0 +#define DBG_DAPROM_COMPONENT_ID3___M 0xFFFFFFFF +#define DBG_DAPROM_COMPONENT_ID3___S 0 + +#define DBG_CSR_PRESERVEETF (0x00B91000) +#define DBG_CSR_PRESERVEETF___RWC QCSR_REG_RO +#define DBG_CSR_PRESERVEETF___POR 0x00000000 +#define DBG_CSR_PRESERVEETF__STS_MEMERR___POR 0x0 +#define DBG_CSR_PRESERVEETF__AFVALIDS___POR 0x0 +#define DBG_CSR_PRESERVEETF__STS_EMPTY___POR 0x0 +#define DBG_CSR_PRESERVEETF__ACQCOMP___POR 0x0 +#define DBG_CSR_PRESERVEETF__STS_TMCREADY___POR 0x0 +#define DBG_CSR_PRESERVEETF__STS_TRIGGERED___POR 0x0 +#define DBG_CSR_PRESERVEETF__FULL___POR 0x0 +#define DBG_CSR_PRESERVEETF__RWP_PRESERVE___POR 0x0000 +#define DBG_CSR_PRESERVEETF__STS_MEMERR___M 0x00400000 +#define DBG_CSR_PRESERVEETF__STS_MEMERR___S 22 +#define DBG_CSR_PRESERVEETF__AFVALIDS___M 0x00200000 +#define DBG_CSR_PRESERVEETF__AFVALIDS___S 21 +#define DBG_CSR_PRESERVEETF__STS_EMPTY___M 0x00100000 +#define DBG_CSR_PRESERVEETF__STS_EMPTY___S 20 +#define DBG_CSR_PRESERVEETF__ACQCOMP___M 0x00080000 +#define DBG_CSR_PRESERVEETF__ACQCOMP___S 19 +#define DBG_CSR_PRESERVEETF__STS_TMCREADY___M 0x00040000 +#define DBG_CSR_PRESERVEETF__STS_TMCREADY___S 18 +#define DBG_CSR_PRESERVEETF__STS_TRIGGERED___M 0x00020000 +#define DBG_CSR_PRESERVEETF__STS_TRIGGERED___S 17 +#define DBG_CSR_PRESERVEETF__FULL___M 0x00010000 +#define DBG_CSR_PRESERVEETF__FULL___S 16 +#define DBG_CSR_PRESERVEETF__RWP_PRESERVE___M 0x0000FFFF +#define DBG_CSR_PRESERVEETF__RWP_PRESERVE___S 0 +#define DBG_CSR_PRESERVEETF___M 0x007FFFFF +#define DBG_CSR_PRESERVEETF___S 0 + +#define DBG_CSR_TRC_CFG (0x00B91004) +#define DBG_CSR_TRC_CFG___RWC QCSR_REG_RW +#define DBG_CSR_TRC_CFG___POR 0x00000000 +#define DBG_CSR_TRC_CFG__PERIODIC_TRIG_EN___POR 0x0 +#define DBG_CSR_TRC_CFG__PERIODIC_HW_EVENT_EN___POR 0x0 +#define DBG_CSR_TRC_CFG__AFV_ALLOW_EXT_EN___POR 0x0 +#define DBG_CSR_TRC_CFG__AFV_SW_EN___POR 0x0 +#define DBG_CSR_TRC_CFG__CMB_OWNER___POR 0x0 +#define DBG_CSR_TRC_CFG__MEM_OWNER___POR 0x0 +#define DBG_CSR_TRC_CFG__PERIODIC_TRIG_EN___M 0x00000200 +#define DBG_CSR_TRC_CFG__PERIODIC_TRIG_EN___S 9 +#define DBG_CSR_TRC_CFG__PERIODIC_TRIG_EN__DISABLED 0x0 +#define DBG_CSR_TRC_CFG__PERIODIC_TRIG_EN__ENABLED 0x1 +#define DBG_CSR_TRC_CFG__PERIODIC_HW_EVENT_EN___M 0x00000100 +#define DBG_CSR_TRC_CFG__PERIODIC_HW_EVENT_EN___S 8 +#define DBG_CSR_TRC_CFG__PERIODIC_HW_EVENT_EN__DISABLED 0x0 +#define DBG_CSR_TRC_CFG__PERIODIC_HW_EVENT_EN__ENABLED 0x1 +#define DBG_CSR_TRC_CFG__AFV_ALLOW_EXT_EN___M 0x00000080 +#define DBG_CSR_TRC_CFG__AFV_ALLOW_EXT_EN___S 7 +#define DBG_CSR_TRC_CFG__AFV_ALLOW_EXT_EN__DISABLED 0x0 +#define DBG_CSR_TRC_CFG__AFV_ALLOW_EXT_EN__ENABLED 0x1 +#define DBG_CSR_TRC_CFG__AFV_SW_EN___M 0x00000040 +#define DBG_CSR_TRC_CFG__AFV_SW_EN___S 6 +#define DBG_CSR_TRC_CFG__AFV_SW_EN__DISABLED 0x0 +#define DBG_CSR_TRC_CFG__AFV_SW_EN__ENABLED 0x1 +#define DBG_CSR_TRC_CFG__CMB_OWNER___M 0x00000038 +#define DBG_CSR_TRC_CFG__CMB_OWNER___S 3 +#define DBG_CSR_TRC_CFG__CMB_OWNER__ARB 0x0 +#define DBG_CSR_TRC_CFG__CMB_OWNER__TRACER 0x1 +#define DBG_CSR_TRC_CFG__CMB_OWNER__APBMON 0x3 +#define DBG_CSR_TRC_CFG__CMB_OWNER__SWGEN 0x5 +#define DBG_CSR_TRC_CFG__CMB_OWNER__DATDUMPR 0x7 +#define DBG_CSR_TRC_CFG__MEM_OWNER___M 0x00000003 +#define DBG_CSR_TRC_CFG__MEM_OWNER___S 0 +#define DBG_CSR_TRC_CFG__MEM_OWNER__ETB 0x0 +#define DBG_CSR_TRC_CFG__MEM_OWNER__APB 0x1 +#define DBG_CSR_TRC_CFG___M 0x000003FB +#define DBG_CSR_TRC_CFG___S 0 + +#define DBG_CSR_TSTMP_CFG (0x00B91008) +#define DBG_CSR_TSTMP_CFG___RWC QCSR_REG_RW +#define DBG_CSR_TSTMP_CFG___POR 0x00000039 +#define DBG_CSR_TSTMP_CFG__INTP_BYPASS___POR 0x1 +#define DBG_CSR_TSTMP_CFG__TPDA_FREQREQ_EN___POR 0x1 +#define DBG_CSR_TSTMP_CFG__SLP_CORR_EN___POR 0x1 +#define DBG_CSR_TSTMP_CFG__SOURCE___POR 0x1 +#define DBG_CSR_TSTMP_CFG__INTP_BYPASS___M 0x00000020 +#define DBG_CSR_TSTMP_CFG__INTP_BYPASS___S 5 +#define DBG_CSR_TSTMP_CFG__TPDA_FREQREQ_EN___M 0x00000010 +#define DBG_CSR_TSTMP_CFG__TPDA_FREQREQ_EN___S 4 +#define DBG_CSR_TSTMP_CFG__SLP_CORR_EN___M 0x00000008 +#define DBG_CSR_TSTMP_CFG__SLP_CORR_EN___S 3 +#define DBG_CSR_TSTMP_CFG__SLP_CORR_EN__NOCORRECTION 0x0 +#define DBG_CSR_TSTMP_CFG__SLP_CORR_EN__CORRECT4TIMEINSLP 0x1 +#define DBG_CSR_TSTMP_CFG__SOURCE___M 0x00000007 +#define DBG_CSR_TSTMP_CFG__SOURCE___S 0 +#define DBG_CSR_TSTMP_CFG__SOURCE__QDSS 0x0 +#define DBG_CSR_TSTMP_CFG__SOURCE__QTMR 0x1 +#define DBG_CSR_TSTMP_CFG__SOURCE__WCSSDBG 0x2 +#define DBG_CSR_TSTMP_CFG__SOURCE__AUTO_QDSS_WCSSDBG 0x3 +#define DBG_CSR_TSTMP_CFG__SOURCE__AUTO_QTMR_WCSSDBG 0x4 +#define DBG_CSR_TSTMP_CFG___M 0x0000003F +#define DBG_CSR_TSTMP_CFG___S 0 + +#define DBG_CSR_QDSS_TS_FREQ (0x00B9100C) +#define DBG_CSR_QDSS_TS_FREQ___RWC QCSR_REG_RW +#define DBG_CSR_QDSS_TS_FREQ___POR 0x00000000 +#define DBG_CSR_QDSS_TS_FREQ__FREQ_IN_HZ___POR 0x00000000 +#define DBG_CSR_QDSS_TS_FREQ__FREQ_IN_HZ___M 0xFFFFFFFF +#define DBG_CSR_QDSS_TS_FREQ__FREQ_IN_HZ___S 0 +#define DBG_CSR_QDSS_TS_FREQ___M 0xFFFFFFFF +#define DBG_CSR_QDSS_TS_FREQ___S 0 + +#define DBG_CSR_QDSS_TSTMP_VAL_LO (0x00B91010) +#define DBG_CSR_QDSS_TSTMP_VAL_LO___RWC QCSR_REG_RO +#define DBG_CSR_QDSS_TSTMP_VAL_LO___POR 0x00000000 +#define DBG_CSR_QDSS_TSTMP_VAL_LO__TSTMP_VAL_31_0___POR 0x00000000 +#define DBG_CSR_QDSS_TSTMP_VAL_LO__TSTMP_VAL_31_0___M 0xFFFFFFFF +#define DBG_CSR_QDSS_TSTMP_VAL_LO__TSTMP_VAL_31_0___S 0 +#define DBG_CSR_QDSS_TSTMP_VAL_LO___M 0xFFFFFFFF +#define DBG_CSR_QDSS_TSTMP_VAL_LO___S 0 + +#define DBG_CSR_QDSS_TSTMP_VAL_HI (0x00B91014) +#define DBG_CSR_QDSS_TSTMP_VAL_HI___RWC QCSR_REG_RO +#define DBG_CSR_QDSS_TSTMP_VAL_HI___POR 0x00000000 +#define DBG_CSR_QDSS_TSTMP_VAL_HI__TSTMP_VAL_63_32___POR 0x00000000 +#define DBG_CSR_QDSS_TSTMP_VAL_HI__TSTMP_VAL_63_32___M 0xFFFFFFFF +#define DBG_CSR_QDSS_TSTMP_VAL_HI__TSTMP_VAL_63_32___S 0 +#define DBG_CSR_QDSS_TSTMP_VAL_HI___M 0xFFFFFFFF +#define DBG_CSR_QDSS_TSTMP_VAL_HI___S 0 + +#define DBG_CSR_INT_TSTMP_VAL_LO (0x00B91018) +#define DBG_CSR_INT_TSTMP_VAL_LO___RWC QCSR_REG_RO +#define DBG_CSR_INT_TSTMP_VAL_LO___POR 0x00000000 +#define DBG_CSR_INT_TSTMP_VAL_LO__TSTMP_VAL_31_0___POR 0x00000000 +#define DBG_CSR_INT_TSTMP_VAL_LO__TSTMP_VAL_31_0___M 0xFFFFFFFF +#define DBG_CSR_INT_TSTMP_VAL_LO__TSTMP_VAL_31_0___S 0 +#define DBG_CSR_INT_TSTMP_VAL_LO___M 0xFFFFFFFF +#define DBG_CSR_INT_TSTMP_VAL_LO___S 0 + +#define DBG_CSR_INT_TSTMP_VAL_HI (0x00B9101C) +#define DBG_CSR_INT_TSTMP_VAL_HI___RWC QCSR_REG_RO +#define DBG_CSR_INT_TSTMP_VAL_HI___POR 0x00000000 +#define DBG_CSR_INT_TSTMP_VAL_HI__TSTMP_VAL_63_32___POR 0x00000000 +#define DBG_CSR_INT_TSTMP_VAL_HI__TSTMP_VAL_63_32___M 0xFFFFFFFF +#define DBG_CSR_INT_TSTMP_VAL_HI__TSTMP_VAL_63_32___S 0 +#define DBG_CSR_INT_TSTMP_VAL_HI___M 0xFFFFFFFF +#define DBG_CSR_INT_TSTMP_VAL_HI___S 0 + +#define DBG_CSR_SWGEN_DSB (0x00B91020) +#define DBG_CSR_SWGEN_DSB___RWC QCSR_REG_WO +#define DBG_CSR_SWGEN_DSB___POR 0x00000000 +#define DBG_CSR_SWGEN_DSB__EVENT7___POR 0x0 +#define DBG_CSR_SWGEN_DSB__EVENT6___POR 0x0 +#define DBG_CSR_SWGEN_DSB__EVENT5___POR 0x0 +#define DBG_CSR_SWGEN_DSB__EVENT4___POR 0x0 +#define DBG_CSR_SWGEN_DSB__EVENT3___POR 0x0 +#define DBG_CSR_SWGEN_DSB__EVENT2___POR 0x0 +#define DBG_CSR_SWGEN_DSB__EVENT1___POR 0x0 +#define DBG_CSR_SWGEN_DSB__EVENT0___POR 0x0 +#define DBG_CSR_SWGEN_DSB__EVENT7___M 0x00000080 +#define DBG_CSR_SWGEN_DSB__EVENT7___S 7 +#define DBG_CSR_SWGEN_DSB__EVENT6___M 0x00000040 +#define DBG_CSR_SWGEN_DSB__EVENT6___S 6 +#define DBG_CSR_SWGEN_DSB__EVENT5___M 0x00000020 +#define DBG_CSR_SWGEN_DSB__EVENT5___S 5 +#define DBG_CSR_SWGEN_DSB__EVENT4___M 0x00000010 +#define DBG_CSR_SWGEN_DSB__EVENT4___S 4 +#define DBG_CSR_SWGEN_DSB__EVENT3___M 0x00000008 +#define DBG_CSR_SWGEN_DSB__EVENT3___S 3 +#define DBG_CSR_SWGEN_DSB__EVENT2___M 0x00000004 +#define DBG_CSR_SWGEN_DSB__EVENT2___S 2 +#define DBG_CSR_SWGEN_DSB__EVENT1___M 0x00000002 +#define DBG_CSR_SWGEN_DSB__EVENT1___S 1 +#define DBG_CSR_SWGEN_DSB__EVENT0___M 0x00000001 +#define DBG_CSR_SWGEN_DSB__EVENT0___S 0 +#define DBG_CSR_SWGEN_DSB___M 0x000000FF +#define DBG_CSR_SWGEN_DSB___S 0 + +#define DBG_CSR_CLK_INFO (0x00B91024) +#define DBG_CSR_CLK_INFO___RWC QCSR_REG_RO +#define DBG_CSR_CLK_INFO___POR 0x00303000 +#define DBG_CSR_CLK_INFO__DAPBUS_DIV___POR 0x3 +#define DBG_CSR_CLK_INFO__TSTMP_DIV___POR 0x0 +#define DBG_CSR_CLK_INFO__APB_DIV___POR 0x3 +#define DBG_CSR_CLK_INFO__ATB_DIV___POR 0x00 +#define DBG_CSR_CLK_INFO__SRC___POR 0x0 +#define DBG_CSR_CLK_INFO__DAPBUS_DIV___M 0x00F00000 +#define DBG_CSR_CLK_INFO__DAPBUS_DIV___S 20 +#define DBG_CSR_CLK_INFO__TSTMP_DIV___M 0x000F0000 +#define DBG_CSR_CLK_INFO__TSTMP_DIV___S 16 +#define DBG_CSR_CLK_INFO__APB_DIV___M 0x0000F000 +#define DBG_CSR_CLK_INFO__APB_DIV___S 12 +#define DBG_CSR_CLK_INFO__ATB_DIV___M 0x000001F0 +#define DBG_CSR_CLK_INFO__ATB_DIV___S 4 +#define DBG_CSR_CLK_INFO__SRC___M 0x00000001 +#define DBG_CSR_CLK_INFO__SRC___S 0 +#define DBG_CSR_CLK_INFO__SRC__PLL 0x0 +#define DBG_CSR_CLK_INFO__SRC__XO 0x1 +#define DBG_CSR_CLK_INFO___M 0x00FFF1F1 +#define DBG_CSR_CLK_INFO___S 0 + +#define DBG_CSR_CXO_FREQ (0x00B91028) +#define DBG_CSR_CXO_FREQ___RWC QCSR_REG_RW +#define DBG_CSR_CXO_FREQ___POR 0x0249F000 +#define DBG_CSR_CXO_FREQ__FREQ___POR 0x249F000 +#define DBG_CSR_CXO_FREQ__FREQ___M 0x03FFFFFF +#define DBG_CSR_CXO_FREQ__FREQ___S 0 +#define DBG_CSR_CXO_FREQ___M 0x03FFFFFF +#define DBG_CSR_CXO_FREQ___S 0 + +#define DBG_CSR_CXO_FREQ_IN_KHZ (0x00B9102C) +#define DBG_CSR_CXO_FREQ_IN_KHZ___RWC QCSR_REG_RW +#define DBG_CSR_CXO_FREQ_IN_KHZ___POR 0x00009600 +#define DBG_CSR_CXO_FREQ_IN_KHZ__FREQ___POR 0x9600 +#define DBG_CSR_CXO_FREQ_IN_KHZ__FREQ___M 0x0000FFFF +#define DBG_CSR_CXO_FREQ_IN_KHZ__FREQ___S 0 +#define DBG_CSR_CXO_FREQ_IN_KHZ___M 0x0000FFFF +#define DBG_CSR_CXO_FREQ_IN_KHZ___S 0 + +#define DBG_CSR_SPARE (0x00B91030) +#define DBG_CSR_SPARE___RWC QCSR_REG_RW +#define DBG_CSR_SPARE___POR 0x00000000 +#define DBG_CSR_SPARE__SPARE___POR 0x00000000 +#define DBG_CSR_SPARE__SPARE___M 0xFFFFFFFF +#define DBG_CSR_SPARE__SPARE___S 0 +#define DBG_CSR_SPARE___M 0xFFFFFFFF +#define DBG_CSR_SPARE___S 0 + +#define DBG_CSR_IPCAT (0x00B91034) +#define DBG_CSR_IPCAT___RWC QCSR_REG_RO +#define DBG_CSR_IPCAT___POR 0x10000000 +#define DBG_CSR_IPCAT__MAJ___POR 0x1 +#define DBG_CSR_IPCAT__MIN___POR 0x000 +#define DBG_CSR_IPCAT__STEP___POR 0x0000 +#define DBG_CSR_IPCAT__MAJ___M 0xF0000000 +#define DBG_CSR_IPCAT__MAJ___S 28 +#define DBG_CSR_IPCAT__MIN___M 0x0FFF0000 +#define DBG_CSR_IPCAT__MIN___S 16 +#define DBG_CSR_IPCAT__STEP___M 0x0000FFFF +#define DBG_CSR_IPCAT__STEP___S 0 +#define DBG_CSR_IPCAT___M 0xFFFFFFFF +#define DBG_CSR_IPCAT___S 0 + +#define DBG_CSR_EXT_MSTR_SYS_NOC_BASE_ADDR (0x00B91038) +#define DBG_CSR_EXT_MSTR_SYS_NOC_BASE_ADDR___RWC QCSR_REG_RW +#define DBG_CSR_EXT_MSTR_SYS_NOC_BASE_ADDR___POR 0x00000000 +#define DBG_CSR_EXT_MSTR_SYS_NOC_BASE_ADDR__ADDR___POR 0x00 +#define DBG_CSR_EXT_MSTR_SYS_NOC_BASE_ADDR__ADDR___M 0x00FE0000 +#define DBG_CSR_EXT_MSTR_SYS_NOC_BASE_ADDR__ADDR___S 17 +#define DBG_CSR_EXT_MSTR_SYS_NOC_BASE_ADDR___M 0x00FE0000 +#define DBG_CSR_EXT_MSTR_SYS_NOC_BASE_ADDR___S 17 + +#define DBG_CSR_INT_MSTR_SYS_NOC_BASE_ADDR (0x00B9103C) +#define DBG_CSR_INT_MSTR_SYS_NOC_BASE_ADDR___RWC QCSR_REG_RW +#define DBG_CSR_INT_MSTR_SYS_NOC_BASE_ADDR___POR 0x00000000 +#define DBG_CSR_INT_MSTR_SYS_NOC_BASE_ADDR__ADDR___POR 0x00 +#define DBG_CSR_INT_MSTR_SYS_NOC_BASE_ADDR__ADDR___M 0x00FE0000 +#define DBG_CSR_INT_MSTR_SYS_NOC_BASE_ADDR__ADDR___S 17 +#define DBG_CSR_INT_MSTR_SYS_NOC_BASE_ADDR___M 0x00FE0000 +#define DBG_CSR_INT_MSTR_SYS_NOC_BASE_ADDR___S 17 + +#define DBG_CSR_LPI_IFC_OWNER (0x00B91040) +#define DBG_CSR_LPI_IFC_OWNER___RWC QCSR_REG_RW +#define DBG_CSR_LPI_IFC_OWNER___POR 0x00000000 +#define DBG_CSR_LPI_IFC_OWNER__PHYB_NTS___POR 0x0 +#define DBG_CSR_LPI_IFC_OWNER__PHYB_ATB___POR 0x0 +#define DBG_CSR_LPI_IFC_OWNER__PHYB_DAP___POR 0x0 +#define DBG_CSR_LPI_IFC_OWNER__PHYB_APB___POR 0x0 +#define DBG_CSR_LPI_IFC_OWNER__PHYA_NTS___POR 0x0 +#define DBG_CSR_LPI_IFC_OWNER__PHYA_ATB___POR 0x0 +#define DBG_CSR_LPI_IFC_OWNER__PHYA_DAP___POR 0x0 +#define DBG_CSR_LPI_IFC_OWNER__PHYA_APB___POR 0x0 +#define DBG_CSR_LPI_IFC_OWNER__NOC_NTS___POR 0x0 +#define DBG_CSR_LPI_IFC_OWNER__NOC_ATB___POR 0x0 +#define DBG_CSR_LPI_IFC_OWNER__NOC_APB___POR 0x0 +#define DBG_CSR_LPI_IFC_OWNER__PHYB_NTS___M 0x00002000 +#define DBG_CSR_LPI_IFC_OWNER__PHYB_NTS___S 13 +#define DBG_CSR_LPI_IFC_OWNER__PHYB_NTS__PMM 0x0 +#define DBG_CSR_LPI_IFC_OWNER__PHYB_NTS__CSR 0x1 +#define DBG_CSR_LPI_IFC_OWNER__PHYB_ATB___M 0x00001000 +#define DBG_CSR_LPI_IFC_OWNER__PHYB_ATB___S 12 +#define DBG_CSR_LPI_IFC_OWNER__PHYB_ATB__PMM 0x0 +#define DBG_CSR_LPI_IFC_OWNER__PHYB_ATB__CSR 0x1 +#define DBG_CSR_LPI_IFC_OWNER__PHYB_DAP___M 0x00000800 +#define DBG_CSR_LPI_IFC_OWNER__PHYB_DAP___S 11 +#define DBG_CSR_LPI_IFC_OWNER__PHYB_DAP__PMM 0x0 +#define DBG_CSR_LPI_IFC_OWNER__PHYB_DAP__CSR 0x1 +#define DBG_CSR_LPI_IFC_OWNER__PHYB_APB___M 0x00000400 +#define DBG_CSR_LPI_IFC_OWNER__PHYB_APB___S 10 +#define DBG_CSR_LPI_IFC_OWNER__PHYB_APB__PMM 0x0 +#define DBG_CSR_LPI_IFC_OWNER__PHYB_APB__CSR 0x1 +#define DBG_CSR_LPI_IFC_OWNER__PHYA_NTS___M 0x00000100 +#define DBG_CSR_LPI_IFC_OWNER__PHYA_NTS___S 8 +#define DBG_CSR_LPI_IFC_OWNER__PHYA_NTS__PMM 0x0 +#define DBG_CSR_LPI_IFC_OWNER__PHYA_NTS__CSR 0x1 +#define DBG_CSR_LPI_IFC_OWNER__PHYA_ATB___M 0x00000080 +#define DBG_CSR_LPI_IFC_OWNER__PHYA_ATB___S 7 +#define DBG_CSR_LPI_IFC_OWNER__PHYA_ATB__PMM 0x0 +#define DBG_CSR_LPI_IFC_OWNER__PHYA_ATB__CSR 0x1 +#define DBG_CSR_LPI_IFC_OWNER__PHYA_DAP___M 0x00000040 +#define DBG_CSR_LPI_IFC_OWNER__PHYA_DAP___S 6 +#define DBG_CSR_LPI_IFC_OWNER__PHYA_DAP__PMM 0x0 +#define DBG_CSR_LPI_IFC_OWNER__PHYA_DAP__CSR 0x1 +#define DBG_CSR_LPI_IFC_OWNER__PHYA_APB___M 0x00000020 +#define DBG_CSR_LPI_IFC_OWNER__PHYA_APB___S 5 +#define DBG_CSR_LPI_IFC_OWNER__PHYA_APB__PMM 0x0 +#define DBG_CSR_LPI_IFC_OWNER__PHYA_APB__CSR 0x1 +#define DBG_CSR_LPI_IFC_OWNER__NOC_NTS___M 0x00000008 +#define DBG_CSR_LPI_IFC_OWNER__NOC_NTS___S 3 +#define DBG_CSR_LPI_IFC_OWNER__NOC_NTS__PMM 0x0 +#define DBG_CSR_LPI_IFC_OWNER__NOC_NTS__CSR 0x1 +#define DBG_CSR_LPI_IFC_OWNER__NOC_ATB___M 0x00000004 +#define DBG_CSR_LPI_IFC_OWNER__NOC_ATB___S 2 +#define DBG_CSR_LPI_IFC_OWNER__NOC_ATB__PMM 0x0 +#define DBG_CSR_LPI_IFC_OWNER__NOC_ATB__CSR 0x1 +#define DBG_CSR_LPI_IFC_OWNER__NOC_APB___M 0x00000002 +#define DBG_CSR_LPI_IFC_OWNER__NOC_APB___S 1 +#define DBG_CSR_LPI_IFC_OWNER__NOC_APB__PMM 0x0 +#define DBG_CSR_LPI_IFC_OWNER__NOC_APB__CSR 0x1 +#define DBG_CSR_LPI_IFC_OWNER___M 0x00003DEE +#define DBG_CSR_LPI_IFC_OWNER___S 1 + +#define DBG_CSR_LPI_IFC_SW_CSYSREQ (0x00B91044) +#define DBG_CSR_LPI_IFC_SW_CSYSREQ___RWC QCSR_REG_RW +#define DBG_CSR_LPI_IFC_SW_CSYSREQ___POR 0x00003DEE +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_NTS___POR 0x1 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_ATB___POR 0x1 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_DAP___POR 0x1 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_APB___POR 0x1 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_NTS___POR 0x1 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_ATB___POR 0x1 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_DAP___POR 0x1 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_APB___POR 0x1 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__NOC_NTS___POR 0x1 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__NOC_ATB___POR 0x1 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__NOC_APB___POR 0x1 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_NTS___M 0x00002000 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_NTS___S 13 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_NTS__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_NTS__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_ATB___M 0x00001000 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_ATB___S 12 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_ATB__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_ATB__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_DAP___M 0x00000800 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_DAP___S 11 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_DAP__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_DAP__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_APB___M 0x00000400 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_APB___S 10 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_APB__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYB_APB__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_NTS___M 0x00000100 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_NTS___S 8 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_NTS__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_NTS__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_ATB___M 0x00000080 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_ATB___S 7 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_ATB__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_ATB__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_DAP___M 0x00000040 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_DAP___S 6 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_DAP__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_DAP__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_APB___M 0x00000020 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_APB___S 5 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_APB__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__PHYA_APB__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__NOC_NTS___M 0x00000008 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__NOC_NTS___S 3 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__NOC_NTS__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__NOC_NTS__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__NOC_ATB___M 0x00000004 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__NOC_ATB___S 2 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__NOC_ATB__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__NOC_ATB__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__NOC_APB___M 0x00000002 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__NOC_APB___S 1 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__NOC_APB__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ__NOC_APB__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_SW_CSYSREQ___M 0x00003DEE +#define DBG_CSR_LPI_IFC_SW_CSYSREQ___S 1 + +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT (0x00B91048) +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT___RWC QCSR_REG_RO +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT___POR 0x00003FFF +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_NTS___POR 0x1 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_ATB___POR 0x1 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_DAP___POR 0x1 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_APB___POR 0x1 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_EXT___POR 0x1 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_NTS___POR 0x1 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_ATB___POR 0x1 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_DAP___POR 0x1 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_APB___POR 0x1 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_EXT___POR 0x1 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_NTS___POR 0x1 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_ATB___POR 0x1 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_APB___POR 0x1 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_EXT___POR 0x1 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_NTS___M 0x00002000 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_NTS___S 13 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_NTS__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_NTS__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_ATB___M 0x00001000 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_ATB___S 12 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_ATB__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_ATB__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_DAP___M 0x00000800 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_DAP___S 11 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_DAP__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_DAP__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_APB___M 0x00000400 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_APB___S 10 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_APB__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_APB__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_EXT___M 0x00000200 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_EXT___S 9 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_EXT__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYB_EXT__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_NTS___M 0x00000100 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_NTS___S 8 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_NTS__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_NTS__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_ATB___M 0x00000080 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_ATB___S 7 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_ATB__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_ATB__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_DAP___M 0x00000040 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_DAP___S 6 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_DAP__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_DAP__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_APB___M 0x00000020 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_APB___S 5 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_APB__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_APB__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_EXT___M 0x00000010 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_EXT___S 4 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_EXT__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__PHYA_EXT__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_NTS___M 0x00000008 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_NTS___S 3 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_NTS__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_NTS__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_ATB___M 0x00000004 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_ATB___S 2 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_ATB__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_ATB__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_APB___M 0x00000002 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_APB___S 1 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_APB__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_APB__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_EXT___M 0x00000001 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_EXT___S 0 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_EXT__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT__NOC_EXT__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT___M 0x00003FFF +#define DBG_CSR_LPI_IFC_CSYSREQ_STAT___S 0 + +#define DBG_CSR_LPI_IFC_CSYSACK_STAT (0x00B9104C) +#define DBG_CSR_LPI_IFC_CSYSACK_STAT___RWC QCSR_REG_RO +#define DBG_CSR_LPI_IFC_CSYSACK_STAT___POR 0x00003FFF +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_NTS___POR 0x1 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_ATB___POR 0x1 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_DAP___POR 0x1 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_APB___POR 0x1 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB___POR 0x1 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_NTS___POR 0x1 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_ATB___POR 0x1 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_DAP___POR 0x1 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_APB___POR 0x1 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA___POR 0x1 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC_NTS___POR 0x1 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC_ATB___POR 0x1 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC_APB___POR 0x1 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC___POR 0x1 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_NTS___M 0x00002000 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_NTS___S 13 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_NTS__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_NTS__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_ATB___M 0x00001000 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_ATB___S 12 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_ATB__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_ATB__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_DAP___M 0x00000800 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_DAP___S 11 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_DAP__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_DAP__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_APB___M 0x00000400 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_APB___S 10 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_APB__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB_APB__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB___M 0x00000200 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB___S 9 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYB__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_NTS___M 0x00000100 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_NTS___S 8 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_NTS__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_NTS__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_ATB___M 0x00000080 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_ATB___S 7 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_ATB__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_ATB__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_DAP___M 0x00000040 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_DAP___S 6 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_DAP__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_DAP__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_APB___M 0x00000020 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_APB___S 5 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_APB__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA_APB__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA___M 0x00000010 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA___S 4 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__PHYA__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC_NTS___M 0x00000008 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC_NTS___S 3 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC_NTS__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC_NTS__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC_ATB___M 0x00000004 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC_ATB___S 2 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC_ATB__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC_ATB__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC_APB___M 0x00000002 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC_APB___S 1 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC_APB__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC_APB__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC___M 0x00000001 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC___S 0 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC__PWRDWN 0x0 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT__NOC__PWRUP 0x1 +#define DBG_CSR_LPI_IFC_CSYSACK_STAT___M 0x00003FFF +#define DBG_CSR_LPI_IFC_CSYSACK_STAT___S 0 + +#define DBG_CSR_LPI_IFC_CACTIVE_STAT (0x00B91050) +#define DBG_CSR_LPI_IFC_CACTIVE_STAT___RWC QCSR_REG_RO +#define DBG_CSR_LPI_IFC_CACTIVE_STAT___POR 0x00003FFF +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYB_NTS___POR 0x1 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYB_ATB___POR 0x1 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYB_DAP___POR 0x1 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYB_APB___POR 0x1 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYB___POR 0x1 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYA_NTS___POR 0x1 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYA_ATB___POR 0x1 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYA_DAP___POR 0x1 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYA_APB___POR 0x1 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYA___POR 0x1 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__NOC_NTS___POR 0x1 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__NOC_ATB___POR 0x1 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__NOC_APB___POR 0x1 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__NOC___POR 0x1 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYB_NTS___M 0x00002000 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYB_NTS___S 13 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYB_ATB___M 0x00001000 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYB_ATB___S 12 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYB_DAP___M 0x00000800 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYB_DAP___S 11 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYB_APB___M 0x00000400 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYB_APB___S 10 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYB___M 0x00000200 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYB___S 9 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYA_NTS___M 0x00000100 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYA_NTS___S 8 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYA_ATB___M 0x00000080 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYA_ATB___S 7 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYA_DAP___M 0x00000040 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYA_DAP___S 6 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYA_APB___M 0x00000020 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYA_APB___S 5 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYA___M 0x00000010 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__PHYA___S 4 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__NOC_NTS___M 0x00000008 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__NOC_NTS___S 3 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__NOC_ATB___M 0x00000004 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__NOC_ATB___S 2 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__NOC_APB___M 0x00000002 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__NOC_APB___S 1 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__NOC___M 0x00000001 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT__NOC___S 0 +#define DBG_CSR_LPI_IFC_CACTIVE_STAT___M 0x00003FFF +#define DBG_CSR_LPI_IFC_CACTIVE_STAT___S 0 + +#define DBG_CSR_TIMER (0x00B91054) +#define DBG_CSR_TIMER___RWC QCSR_REG_RW +#define DBG_CSR_TIMER___POR 0x00000000 +#define DBG_CSR_TIMER__VALUE___POR 0x00000000 +#define DBG_CSR_TIMER__VALUE___M 0xFFFFFFFF +#define DBG_CSR_TIMER__VALUE___S 0 +#define DBG_CSR_TIMER___M 0xFFFFFFFF +#define DBG_CSR_TIMER___S 0 + +#define DBG_CSR_PMM_TRC_CFG (0x00B91058) +#define DBG_CSR_PMM_TRC_CFG___RWC QCSR_REG_RW +#define DBG_CSR_PMM_TRC_CFG___POR 0x00004F9C +#define DBG_CSR_PMM_TRC_CFG__ATID1___POR 0x4F +#define DBG_CSR_PMM_TRC_CFG__ATID0___POR 0x4E +#define DBG_CSR_PMM_TRC_CFG__MODE___POR 0x0 +#define DBG_CSR_PMM_TRC_CFG__ATID1___M 0x00007F00 +#define DBG_CSR_PMM_TRC_CFG__ATID1___S 8 +#define DBG_CSR_PMM_TRC_CFG__ATID0___M 0x000000FE +#define DBG_CSR_PMM_TRC_CFG__ATID0___S 1 +#define DBG_CSR_PMM_TRC_CFG__MODE___M 0x00000001 +#define DBG_CSR_PMM_TRC_CFG__MODE___S 0 +#define DBG_CSR_PMM_TRC_CFG__MODE__CMB 0x0 +#define DBG_CSR_PMM_TRC_CFG__MODE__ATB 0x1 +#define DBG_CSR_PMM_TRC_CFG___M 0x00007FFF +#define DBG_CSR_PMM_TRC_CFG___S 0 + +#define DBG_CSR_TGU_CFG (0x00B9105C) +#define DBG_CSR_TGU_CFG___RWC QCSR_REG_RW +#define DBG_CSR_TGU_CFG___POR 0x00000000 +#define DBG_CSR_TGU_CFG__SRC_SEL___POR 0x0 +#define DBG_CSR_TGU_CFG__EN___POR 0x0 +#define DBG_CSR_TGU_CFG__SRC_SEL___M 0x0000001E +#define DBG_CSR_TGU_CFG__SRC_SEL___S 1 +#define DBG_CSR_TGU_CFG__SRC_SEL__MACEVENT 0x0 +#define DBG_CSR_TGU_CFG__SRC_SEL__MACTLV 0x1 +#define DBG_CSR_TGU_CFG__SRC_SEL__MACTBUS 0x2 +#define DBG_CSR_TGU_CFG__SRC_SEL__PMM 0x3 +#define DBG_CSR_TGU_CFG__SRC_SEL__PHYA 0x4 +#define DBG_CSR_TGU_CFG__SRC_SEL__PHYB 0x5 +#define DBG_CSR_TGU_CFG__SRC_SEL__APBMON 0x6 +#define DBG_CSR_TGU_CFG__SRC_SEL__DATDUMPR 0x7 +#define DBG_CSR_TGU_CFG__SRC_SEL__SWGENCMB 0x8 +#define DBG_CSR_TGU_CFG__EN___M 0x00000001 +#define DBG_CSR_TGU_CFG__EN___S 0 +#define DBG_CSR_TGU_CFG__EN__DISABLED 0x0 +#define DBG_CSR_TGU_CFG__EN__ENABLED 0x1 +#define DBG_CSR_TGU_CFG___M 0x0000001F +#define DBG_CSR_TGU_CFG___S 0 + +#define DBG_CSR_PHYA_TGU_CFG (0x00B91060) +#define DBG_CSR_PHYA_TGU_CFG___RWC QCSR_REG_RW +#define DBG_CSR_PHYA_TGU_CFG___POR 0x000000F0 +#define DBG_CSR_PHYA_TGU_CFG__ATID___POR 0x00 +#define DBG_CSR_PHYA_TGU_CFG__TRIG_COMBOP___POR 0x0 +#define DBG_CSR_PHYA_TGU_CFG__TRIG_POL___POR 0xF +#define DBG_CSR_PHYA_TGU_CFG__TRIG_EN___POR 0x0 +#define DBG_CSR_PHYA_TGU_CFG__ATID___M 0x0000FE00 +#define DBG_CSR_PHYA_TGU_CFG__ATID___S 9 +#define DBG_CSR_PHYA_TGU_CFG__TRIG_COMBOP___M 0x00000100 +#define DBG_CSR_PHYA_TGU_CFG__TRIG_COMBOP___S 8 +#define DBG_CSR_PHYA_TGU_CFG__TRIG_POL___M 0x000000F0 +#define DBG_CSR_PHYA_TGU_CFG__TRIG_POL___S 4 +#define DBG_CSR_PHYA_TGU_CFG__TRIG_EN___M 0x0000000F +#define DBG_CSR_PHYA_TGU_CFG__TRIG_EN___S 0 +#define DBG_CSR_PHYA_TGU_CFG___M 0x0000FFFF +#define DBG_CSR_PHYA_TGU_CFG___S 0 + +#define DBG_CSR_PHYB_TGU_CFG (0x00B91064) +#define DBG_CSR_PHYB_TGU_CFG___RWC QCSR_REG_RW +#define DBG_CSR_PHYB_TGU_CFG___POR 0x000000F0 +#define DBG_CSR_PHYB_TGU_CFG__ATID___POR 0x00 +#define DBG_CSR_PHYB_TGU_CFG__TRIG_COMBOP___POR 0x0 +#define DBG_CSR_PHYB_TGU_CFG__TRIG_POL___POR 0xF +#define DBG_CSR_PHYB_TGU_CFG__TRIG_EN___POR 0x0 +#define DBG_CSR_PHYB_TGU_CFG__ATID___M 0x0000FE00 +#define DBG_CSR_PHYB_TGU_CFG__ATID___S 9 +#define DBG_CSR_PHYB_TGU_CFG__TRIG_COMBOP___M 0x00000100 +#define DBG_CSR_PHYB_TGU_CFG__TRIG_COMBOP___S 8 +#define DBG_CSR_PHYB_TGU_CFG__TRIG_POL___M 0x000000F0 +#define DBG_CSR_PHYB_TGU_CFG__TRIG_POL___S 4 +#define DBG_CSR_PHYB_TGU_CFG__TRIG_EN___M 0x0000000F +#define DBG_CSR_PHYB_TGU_CFG__TRIG_EN___S 0 +#define DBG_CSR_PHYB_TGU_CFG___M 0x0000FFFF +#define DBG_CSR_PHYB_TGU_CFG___S 0 + +#define DBG_CSR_PMM_TGU_CFG (0x00B91068) +#define DBG_CSR_PMM_TGU_CFG___RWC QCSR_REG_RW +#define DBG_CSR_PMM_TGU_CFG___POR 0x000000F0 +#define DBG_CSR_PMM_TGU_CFG__TRIG_COMBOP___POR 0x0 +#define DBG_CSR_PMM_TGU_CFG__TRIG_POL___POR 0xF +#define DBG_CSR_PMM_TGU_CFG__TRIG_EN___POR 0x0 +#define DBG_CSR_PMM_TGU_CFG__TRIG_COMBOP___M 0x00000100 +#define DBG_CSR_PMM_TGU_CFG__TRIG_COMBOP___S 8 +#define DBG_CSR_PMM_TGU_CFG__TRIG_POL___M 0x000000F0 +#define DBG_CSR_PMM_TGU_CFG__TRIG_POL___S 4 +#define DBG_CSR_PMM_TGU_CFG__TRIG_EN___M 0x0000000F +#define DBG_CSR_PMM_TGU_CFG__TRIG_EN___S 0 +#define DBG_CSR_PMM_TGU_CFG___M 0x000001FF +#define DBG_CSR_PMM_TGU_CFG___S 0 + +#define DBG_CSR_APBMON_TGU_CFG (0x00B9106C) +#define DBG_CSR_APBMON_TGU_CFG___RWC QCSR_REG_RW +#define DBG_CSR_APBMON_TGU_CFG___POR 0x000000F0 +#define DBG_CSR_APBMON_TGU_CFG__TRIG_COMBOP___POR 0x0 +#define DBG_CSR_APBMON_TGU_CFG__TRIG_POL___POR 0xF +#define DBG_CSR_APBMON_TGU_CFG__TRIG_EN___POR 0x0 +#define DBG_CSR_APBMON_TGU_CFG__TRIG_COMBOP___M 0x00000100 +#define DBG_CSR_APBMON_TGU_CFG__TRIG_COMBOP___S 8 +#define DBG_CSR_APBMON_TGU_CFG__TRIG_POL___M 0x000000F0 +#define DBG_CSR_APBMON_TGU_CFG__TRIG_POL___S 4 +#define DBG_CSR_APBMON_TGU_CFG__TRIG_EN___M 0x0000000F +#define DBG_CSR_APBMON_TGU_CFG__TRIG_EN___S 0 +#define DBG_CSR_APBMON_TGU_CFG___M 0x000001FF +#define DBG_CSR_APBMON_TGU_CFG___S 0 + +#define DBG_CSR_DATDUMPR_TGU_CFG (0x00B91070) +#define DBG_CSR_DATDUMPR_TGU_CFG___RWC QCSR_REG_RW +#define DBG_CSR_DATDUMPR_TGU_CFG___POR 0x000000F0 +#define DBG_CSR_DATDUMPR_TGU_CFG__TRIG_COMBOP___POR 0x0 +#define DBG_CSR_DATDUMPR_TGU_CFG__TRIG_POL___POR 0xF +#define DBG_CSR_DATDUMPR_TGU_CFG__TRIG_EN___POR 0x0 +#define DBG_CSR_DATDUMPR_TGU_CFG__TRIG_COMBOP___M 0x00000100 +#define DBG_CSR_DATDUMPR_TGU_CFG__TRIG_COMBOP___S 8 +#define DBG_CSR_DATDUMPR_TGU_CFG__TRIG_POL___M 0x000000F0 +#define DBG_CSR_DATDUMPR_TGU_CFG__TRIG_POL___S 4 +#define DBG_CSR_DATDUMPR_TGU_CFG__TRIG_EN___M 0x0000000F +#define DBG_CSR_DATDUMPR_TGU_CFG__TRIG_EN___S 0 +#define DBG_CSR_DATDUMPR_TGU_CFG___M 0x000001FF +#define DBG_CSR_DATDUMPR_TGU_CFG___S 0 + +#define DBG_CSR_SWGENCMB_TGU_CFG (0x00B91074) +#define DBG_CSR_SWGENCMB_TGU_CFG___RWC QCSR_REG_RW +#define DBG_CSR_SWGENCMB_TGU_CFG___POR 0x000000F0 +#define DBG_CSR_SWGENCMB_TGU_CFG__TRIG_COMBOP___POR 0x0 +#define DBG_CSR_SWGENCMB_TGU_CFG__TRIG_POL___POR 0xF +#define DBG_CSR_SWGENCMB_TGU_CFG__TRIG_EN___POR 0x0 +#define DBG_CSR_SWGENCMB_TGU_CFG__TRIG_COMBOP___M 0x00000100 +#define DBG_CSR_SWGENCMB_TGU_CFG__TRIG_COMBOP___S 8 +#define DBG_CSR_SWGENCMB_TGU_CFG__TRIG_POL___M 0x000000F0 +#define DBG_CSR_SWGENCMB_TGU_CFG__TRIG_POL___S 4 +#define DBG_CSR_SWGENCMB_TGU_CFG__TRIG_EN___M 0x0000000F +#define DBG_CSR_SWGENCMB_TGU_CFG__TRIG_EN___S 0 +#define DBG_CSR_SWGENCMB_TGU_CFG___M 0x000001FF +#define DBG_CSR_SWGENCMB_TGU_CFG___S 0 + +#define DBG_CSR_QTMR_TSTMP_VAL_LO (0x00B91078) +#define DBG_CSR_QTMR_TSTMP_VAL_LO___RWC QCSR_REG_RO +#define DBG_CSR_QTMR_TSTMP_VAL_LO___POR 0x00000000 +#define DBG_CSR_QTMR_TSTMP_VAL_LO__TSTMP_VAL_31_0___POR 0x00000000 +#define DBG_CSR_QTMR_TSTMP_VAL_LO__TSTMP_VAL_31_0___M 0xFFFFFFFF +#define DBG_CSR_QTMR_TSTMP_VAL_LO__TSTMP_VAL_31_0___S 0 +#define DBG_CSR_QTMR_TSTMP_VAL_LO___M 0xFFFFFFFF +#define DBG_CSR_QTMR_TSTMP_VAL_LO___S 0 + +#define DBG_CSR_QTMR_TSTMP_VAL_HI (0x00B9107C) +#define DBG_CSR_QTMR_TSTMP_VAL_HI___RWC QCSR_REG_RO +#define DBG_CSR_QTMR_TSTMP_VAL_HI___POR 0x00000000 +#define DBG_CSR_QTMR_TSTMP_VAL_HI__TSTMP_VAL_63_32___POR 0x00000000 +#define DBG_CSR_QTMR_TSTMP_VAL_HI__TSTMP_VAL_63_32___M 0xFFFFFFFF +#define DBG_CSR_QTMR_TSTMP_VAL_HI__TSTMP_VAL_63_32___S 0 +#define DBG_CSR_QTMR_TSTMP_VAL_HI___M 0xFFFFFFFF +#define DBG_CSR_QTMR_TSTMP_VAL_HI___S 0 + +#define DBG_CSR_DATDUMPER_CTRL (0x00B91200) +#define DBG_CSR_DATDUMPER_CTRL___RWC QCSR_REG_RW +#define DBG_CSR_DATDUMPER_CTRL___POR 0x00000000 +#define DBG_CSR_DATDUMPER_CTRL__BUSY___POR 0x0 +#define DBG_CSR_DATDUMPER_CTRL__DESCR_EN___POR 0x0 +#define DBG_CSR_DATDUMPER_CTRL__DISCARD_PATTERN_EN___POR 0x0 +#define DBG_CSR_DATDUMPER_CTRL__DISCARD_CMN_EN___POR 0x0 +#define DBG_CSR_DATDUMPER_CTRL__DISCARD_ERR_EN___POR 0x0 +#define DBG_CSR_DATDUMPER_CTRL__TRIGEN___POR 0x0 +#define DBG_CSR_DATDUMPER_CTRL__SWSTART___POR 0x0 +#define DBG_CSR_DATDUMPER_CTRL__BUSY___M 0x00000040 +#define DBG_CSR_DATDUMPER_CTRL__BUSY___S 6 +#define DBG_CSR_DATDUMPER_CTRL__DESCR_EN___M 0x00000020 +#define DBG_CSR_DATDUMPER_CTRL__DESCR_EN___S 5 +#define DBG_CSR_DATDUMPER_CTRL__DISCARD_PATTERN_EN___M 0x00000010 +#define DBG_CSR_DATDUMPER_CTRL__DISCARD_PATTERN_EN___S 4 +#define DBG_CSR_DATDUMPER_CTRL__DISCARD_CMN_EN___M 0x00000008 +#define DBG_CSR_DATDUMPER_CTRL__DISCARD_CMN_EN___S 3 +#define DBG_CSR_DATDUMPER_CTRL__DISCARD_ERR_EN___M 0x00000004 +#define DBG_CSR_DATDUMPER_CTRL__DISCARD_ERR_EN___S 2 +#define DBG_CSR_DATDUMPER_CTRL__TRIGEN___M 0x00000002 +#define DBG_CSR_DATDUMPER_CTRL__TRIGEN___S 1 +#define DBG_CSR_DATDUMPER_CTRL__SWSTART___M 0x00000001 +#define DBG_CSR_DATDUMPER_CTRL__SWSTART___S 0 +#define DBG_CSR_DATDUMPER_CTRL___M 0x0000007F +#define DBG_CSR_DATDUMPER_CTRL___S 0 + +#define DBG_CSR_DATDUMPER_START_ADDR (0x00B91204) +#define DBG_CSR_DATDUMPER_START_ADDR___RWC QCSR_REG_RW +#define DBG_CSR_DATDUMPER_START_ADDR___POR 0x00000000 +#define DBG_CSR_DATDUMPER_START_ADDR__ADDR___POR 0x000000 +#define DBG_CSR_DATDUMPER_START_ADDR__ADDR___M 0x00FFFFFF +#define DBG_CSR_DATDUMPER_START_ADDR__ADDR___S 0 +#define DBG_CSR_DATDUMPER_START_ADDR___M 0x00FFFFFF +#define DBG_CSR_DATDUMPER_START_ADDR___S 0 + +#define DBG_CSR_DATDUMPER_END_ADDR (0x00B91208) +#define DBG_CSR_DATDUMPER_END_ADDR___RWC QCSR_REG_RW +#define DBG_CSR_DATDUMPER_END_ADDR___POR 0x00000000 +#define DBG_CSR_DATDUMPER_END_ADDR__ADDR___POR 0x000000 +#define DBG_CSR_DATDUMPER_END_ADDR__ADDR___M 0x00FFFFFF +#define DBG_CSR_DATDUMPER_END_ADDR__ADDR___S 0 +#define DBG_CSR_DATDUMPER_END_ADDR___M 0x00FFFFFF +#define DBG_CSR_DATDUMPER_END_ADDR___S 0 + +#define DBG_CSR_DATDUMPER_DISCARD_VALUE (0x00B9120C) +#define DBG_CSR_DATDUMPER_DISCARD_VALUE___RWC QCSR_REG_RW +#define DBG_CSR_DATDUMPER_DISCARD_VALUE___POR 0x00000000 +#define DBG_CSR_DATDUMPER_DISCARD_VALUE__VALUE___POR 0x00000000 +#define DBG_CSR_DATDUMPER_DISCARD_VALUE__VALUE___M 0xFFFFFFFF +#define DBG_CSR_DATDUMPER_DISCARD_VALUE__VALUE___S 0 +#define DBG_CSR_DATDUMPER_DISCARD_VALUE___M 0xFFFFFFFF +#define DBG_CSR_DATDUMPER_DISCARD_VALUE___S 0 + +#define DBG_CSR_DATDUMPER_LAST_ADDR (0x00B91210) +#define DBG_CSR_DATDUMPER_LAST_ADDR___RWC QCSR_REG_RO +#define DBG_CSR_DATDUMPER_LAST_ADDR___POR 0x00000000 +#define DBG_CSR_DATDUMPER_LAST_ADDR__ADDR___POR 0x000000 +#define DBG_CSR_DATDUMPER_LAST_ADDR__ADDR___M 0x00FFFFFF +#define DBG_CSR_DATDUMPER_LAST_ADDR__ADDR___S 0 +#define DBG_CSR_DATDUMPER_LAST_ADDR___M 0x00FFFFFF +#define DBG_CSR_DATDUMPER_LAST_ADDR___S 0 + +#define DBG_CSR_DATDUMPER_LAST_DATA (0x00B91214) +#define DBG_CSR_DATDUMPER_LAST_DATA___RWC QCSR_REG_RO +#define DBG_CSR_DATDUMPER_LAST_DATA___POR 0x00000000 +#define DBG_CSR_DATDUMPER_LAST_DATA__DATA___POR 0x00000000 +#define DBG_CSR_DATDUMPER_LAST_DATA__DATA___M 0xFFFFFFFF +#define DBG_CSR_DATDUMPER_LAST_DATA__DATA___S 0 +#define DBG_CSR_DATDUMPER_LAST_DATA___M 0xFFFFFFFF +#define DBG_CSR_DATDUMPER_LAST_DATA___S 0 + +#define DBG_CSR_DATDUMPER_LAST_RESP (0x00B91218) +#define DBG_CSR_DATDUMPER_LAST_RESP___RWC QCSR_REG_RO +#define DBG_CSR_DATDUMPER_LAST_RESP___POR 0x00000000 +#define DBG_CSR_DATDUMPER_LAST_RESP__RESP___POR 0x0 +#define DBG_CSR_DATDUMPER_LAST_RESP__RESP___M 0x00000001 +#define DBG_CSR_DATDUMPER_LAST_RESP__RESP___S 0 +#define DBG_CSR_DATDUMPER_LAST_RESP__RESP__OKAY 0x0 +#define DBG_CSR_DATDUMPER_LAST_RESP__RESP__ERROR 0x1 +#define DBG_CSR_DATDUMPER_LAST_RESP___M 0x00000001 +#define DBG_CSR_DATDUMPER_LAST_RESP___S 0 + +#define DBG_CSR_DATDUMPER_DESCR_TBL_ADDR (0x00B9121C) +#define DBG_CSR_DATDUMPER_DESCR_TBL_ADDR___RWC QCSR_REG_RW +#define DBG_CSR_DATDUMPER_DESCR_TBL_ADDR___POR 0x00000000 +#define DBG_CSR_DATDUMPER_DESCR_TBL_ADDR__ADDR___POR 0x000000 +#define DBG_CSR_DATDUMPER_DESCR_TBL_ADDR__ADDR___M 0x00FFFFFF +#define DBG_CSR_DATDUMPER_DESCR_TBL_ADDR__ADDR___S 0 +#define DBG_CSR_DATDUMPER_DESCR_TBL_ADDR___M 0x00FFFFFF +#define DBG_CSR_DATDUMPER_DESCR_TBL_ADDR___S 0 + +#define DBG_CSR_APBMON_DSB_MATCH0_CTRL (0x00B91400) +#define DBG_CSR_APBMON_DSB_MATCH0_CTRL___RWC QCSR_REG_RW +#define DBG_CSR_APBMON_DSB_MATCH0_CTRL___POR 0x00000000 +#define DBG_CSR_APBMON_DSB_MATCH0_CTRL__DATA_EN___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH0_CTRL__LATENCY_EN___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH0_CTRL__RESP_TYPE_EN___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH0_CTRL__XFER_TYPE_EN___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH0_CTRL__PSEL_EN___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH0_CTRL__ADDR_EN___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH0_CTRL__ENABLE___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH0_CTRL__DATA_EN___M 0x00000040 +#define DBG_CSR_APBMON_DSB_MATCH0_CTRL__DATA_EN___S 6 +#define DBG_CSR_APBMON_DSB_MATCH0_CTRL__LATENCY_EN___M 0x00000020 +#define DBG_CSR_APBMON_DSB_MATCH0_CTRL__LATENCY_EN___S 5 +#define DBG_CSR_APBMON_DSB_MATCH0_CTRL__RESP_TYPE_EN___M 0x00000010 +#define DBG_CSR_APBMON_DSB_MATCH0_CTRL__RESP_TYPE_EN___S 4 +#define DBG_CSR_APBMON_DSB_MATCH0_CTRL__XFER_TYPE_EN___M 0x00000008 +#define DBG_CSR_APBMON_DSB_MATCH0_CTRL__XFER_TYPE_EN___S 3 +#define DBG_CSR_APBMON_DSB_MATCH0_CTRL__PSEL_EN___M 0x00000004 +#define DBG_CSR_APBMON_DSB_MATCH0_CTRL__PSEL_EN___S 2 +#define DBG_CSR_APBMON_DSB_MATCH0_CTRL__ADDR_EN___M 0x00000002 +#define DBG_CSR_APBMON_DSB_MATCH0_CTRL__ADDR_EN___S 1 +#define DBG_CSR_APBMON_DSB_MATCH0_CTRL__ENABLE___M 0x00000001 +#define DBG_CSR_APBMON_DSB_MATCH0_CTRL__ENABLE___S 0 +#define DBG_CSR_APBMON_DSB_MATCH0_CTRL___M 0x0000007F +#define DBG_CSR_APBMON_DSB_MATCH0_CTRL___S 0 + +#define DBG_CSR_APBMON_DSB_MATCH0_PADDR_MASK (0x00B91404) +#define DBG_CSR_APBMON_DSB_MATCH0_PADDR_MASK___RWC QCSR_REG_RW +#define DBG_CSR_APBMON_DSB_MATCH0_PADDR_MASK___POR 0x00FFFFFF +#define DBG_CSR_APBMON_DSB_MATCH0_PADDR_MASK__MASK___POR 0xFFFFFF +#define DBG_CSR_APBMON_DSB_MATCH0_PADDR_MASK__MASK___M 0x00FFFFFF +#define DBG_CSR_APBMON_DSB_MATCH0_PADDR_MASK__MASK___S 0 +#define DBG_CSR_APBMON_DSB_MATCH0_PADDR_MASK___M 0x00FFFFFF +#define DBG_CSR_APBMON_DSB_MATCH0_PADDR_MASK___S 0 + +#define DBG_CSR_APBMON_DSB_MATCH0_PADDR_LO (0x00B91408) +#define DBG_CSR_APBMON_DSB_MATCH0_PADDR_LO___RWC QCSR_REG_RW +#define DBG_CSR_APBMON_DSB_MATCH0_PADDR_LO___POR 0x00000000 +#define DBG_CSR_APBMON_DSB_MATCH0_PADDR_LO__ADDRLO___POR 0x000000 +#define DBG_CSR_APBMON_DSB_MATCH0_PADDR_LO__ADDRLO___M 0x00FFFFFF +#define DBG_CSR_APBMON_DSB_MATCH0_PADDR_LO__ADDRLO___S 0 +#define DBG_CSR_APBMON_DSB_MATCH0_PADDR_LO___M 0x00FFFFFF +#define DBG_CSR_APBMON_DSB_MATCH0_PADDR_LO___S 0 + +#define DBG_CSR_APBMON_DSB_MATCH0_PADDR_HI (0x00B9140C) +#define DBG_CSR_APBMON_DSB_MATCH0_PADDR_HI___RWC QCSR_REG_RW +#define DBG_CSR_APBMON_DSB_MATCH0_PADDR_HI___POR 0x00000000 +#define DBG_CSR_APBMON_DSB_MATCH0_PADDR_HI__ADDRHI___POR 0x000000 +#define DBG_CSR_APBMON_DSB_MATCH0_PADDR_HI__ADDRHI___M 0x00FFFFFF +#define DBG_CSR_APBMON_DSB_MATCH0_PADDR_HI__ADDRHI___S 0 +#define DBG_CSR_APBMON_DSB_MATCH0_PADDR_HI___M 0x00FFFFFF +#define DBG_CSR_APBMON_DSB_MATCH0_PADDR_HI___S 0 + +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS (0x00B91410) +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS___RWC QCSR_REG_RW +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS___POR 0x00000000 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__RESP_TYPE___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__XFER_TYPE___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL15_RSVD___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL14_RSVD___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL13_RSVD___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL12_RSVD___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL11_RSVD___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL10_RSVD___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL9_RSVD___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_WCSS_DBG___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_PMM_TOP___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_WFSS_PMM___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_WCMN_CORE___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_WCMN___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_TSLV___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_WMAC0___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_UMAC___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_PHYA___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__RESP_TYPE___M 0x00020000 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__RESP_TYPE___S 17 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__RESP_TYPE__OKAY 0x0 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__RESP_TYPE__ERROR 0x1 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__XFER_TYPE___M 0x00010000 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__XFER_TYPE___S 16 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__XFER_TYPE__READ 0x0 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__XFER_TYPE__WRITE 0x1 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL15_RSVD___M 0x00008000 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL15_RSVD___S 15 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL14_RSVD___M 0x00004000 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL14_RSVD___S 14 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL13_RSVD___M 0x00002000 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL13_RSVD___S 13 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL12_RSVD___M 0x00001000 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL12_RSVD___S 12 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL11_RSVD___M 0x00000800 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL11_RSVD___S 11 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL10_RSVD___M 0x00000400 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL10_RSVD___S 10 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL9_RSVD___M 0x00000200 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL9_RSVD___S 9 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_WCSS_DBG___M 0x00000100 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_WCSS_DBG___S 8 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_PMM_TOP___M 0x00000080 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_PMM_TOP___S 7 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_WFSS_PMM___M 0x00000040 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_WFSS_PMM___S 6 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_WCMN_CORE___M 0x00000020 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_WCMN_CORE___S 5 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_WCMN___M 0x00000010 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_WCMN___S 4 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_TSLV___M 0x00000008 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_TSLV___S 3 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_WMAC0___M 0x00000004 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_WMAC0___S 2 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_UMAC___M 0x00000002 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_UMAC___S 1 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_PHYA___M 0x00000001 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS__PSEL_PHYA___S 0 +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS___M 0x0003FFFF +#define DBG_CSR_APBMON_DSB_MATCH0_DETAILS___S 0 + +#define DBG_CSR_APBMON_DSB_MATCH0_PDATA_MASK (0x00B91414) +#define DBG_CSR_APBMON_DSB_MATCH0_PDATA_MASK___RWC QCSR_REG_RW +#define DBG_CSR_APBMON_DSB_MATCH0_PDATA_MASK___POR 0xFFFFFFFF +#define DBG_CSR_APBMON_DSB_MATCH0_PDATA_MASK__MASK___POR 0xFFFFFFFF +#define DBG_CSR_APBMON_DSB_MATCH0_PDATA_MASK__MASK___M 0xFFFFFFFF +#define DBG_CSR_APBMON_DSB_MATCH0_PDATA_MASK__MASK___S 0 +#define DBG_CSR_APBMON_DSB_MATCH0_PDATA_MASK___M 0xFFFFFFFF +#define DBG_CSR_APBMON_DSB_MATCH0_PDATA_MASK___S 0 + +#define DBG_CSR_APBMON_DSB_MATCH0_PDATA (0x00B91418) +#define DBG_CSR_APBMON_DSB_MATCH0_PDATA___RWC QCSR_REG_RW +#define DBG_CSR_APBMON_DSB_MATCH0_PDATA___POR 0x00000000 +#define DBG_CSR_APBMON_DSB_MATCH0_PDATA__DATA___POR 0x00000000 +#define DBG_CSR_APBMON_DSB_MATCH0_PDATA__DATA___M 0xFFFFFFFF +#define DBG_CSR_APBMON_DSB_MATCH0_PDATA__DATA___S 0 +#define DBG_CSR_APBMON_DSB_MATCH0_PDATA___M 0xFFFFFFFF +#define DBG_CSR_APBMON_DSB_MATCH0_PDATA___S 0 + +#define DBG_CSR_APBMON_DSB_MATCH1_CTRL (0x00B9141C) +#define DBG_CSR_APBMON_DSB_MATCH1_CTRL___RWC QCSR_REG_RW +#define DBG_CSR_APBMON_DSB_MATCH1_CTRL___POR 0x00000000 +#define DBG_CSR_APBMON_DSB_MATCH1_CTRL__DATA_EN___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH1_CTRL__LATENCY_EN___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH1_CTRL__RESP_TYPE_EN___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH1_CTRL__XFER_TYPE_EN___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH1_CTRL__PSEL_EN___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH1_CTRL__ADDR_EN___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH1_CTRL__ENABLE___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH1_CTRL__DATA_EN___M 0x00000040 +#define DBG_CSR_APBMON_DSB_MATCH1_CTRL__DATA_EN___S 6 +#define DBG_CSR_APBMON_DSB_MATCH1_CTRL__LATENCY_EN___M 0x00000020 +#define DBG_CSR_APBMON_DSB_MATCH1_CTRL__LATENCY_EN___S 5 +#define DBG_CSR_APBMON_DSB_MATCH1_CTRL__RESP_TYPE_EN___M 0x00000010 +#define DBG_CSR_APBMON_DSB_MATCH1_CTRL__RESP_TYPE_EN___S 4 +#define DBG_CSR_APBMON_DSB_MATCH1_CTRL__XFER_TYPE_EN___M 0x00000008 +#define DBG_CSR_APBMON_DSB_MATCH1_CTRL__XFER_TYPE_EN___S 3 +#define DBG_CSR_APBMON_DSB_MATCH1_CTRL__PSEL_EN___M 0x00000004 +#define DBG_CSR_APBMON_DSB_MATCH1_CTRL__PSEL_EN___S 2 +#define DBG_CSR_APBMON_DSB_MATCH1_CTRL__ADDR_EN___M 0x00000002 +#define DBG_CSR_APBMON_DSB_MATCH1_CTRL__ADDR_EN___S 1 +#define DBG_CSR_APBMON_DSB_MATCH1_CTRL__ENABLE___M 0x00000001 +#define DBG_CSR_APBMON_DSB_MATCH1_CTRL__ENABLE___S 0 +#define DBG_CSR_APBMON_DSB_MATCH1_CTRL___M 0x0000007F +#define DBG_CSR_APBMON_DSB_MATCH1_CTRL___S 0 + +#define DBG_CSR_APBMON_DSB_MATCH1_PADDR_MASK (0x00B91420) +#define DBG_CSR_APBMON_DSB_MATCH1_PADDR_MASK___RWC QCSR_REG_RW +#define DBG_CSR_APBMON_DSB_MATCH1_PADDR_MASK___POR 0x00FFFFFF +#define DBG_CSR_APBMON_DSB_MATCH1_PADDR_MASK__MASK___POR 0xFFFFFF +#define DBG_CSR_APBMON_DSB_MATCH1_PADDR_MASK__MASK___M 0x00FFFFFF +#define DBG_CSR_APBMON_DSB_MATCH1_PADDR_MASK__MASK___S 0 +#define DBG_CSR_APBMON_DSB_MATCH1_PADDR_MASK___M 0x00FFFFFF +#define DBG_CSR_APBMON_DSB_MATCH1_PADDR_MASK___S 0 + +#define DBG_CSR_APBMON_DSB_MATCH1_PADDR_LO (0x00B91424) +#define DBG_CSR_APBMON_DSB_MATCH1_PADDR_LO___RWC QCSR_REG_RW +#define DBG_CSR_APBMON_DSB_MATCH1_PADDR_LO___POR 0x00000000 +#define DBG_CSR_APBMON_DSB_MATCH1_PADDR_LO__ADDRLO___POR 0x000000 +#define DBG_CSR_APBMON_DSB_MATCH1_PADDR_LO__ADDRLO___M 0x00FFFFFF +#define DBG_CSR_APBMON_DSB_MATCH1_PADDR_LO__ADDRLO___S 0 +#define DBG_CSR_APBMON_DSB_MATCH1_PADDR_LO___M 0x00FFFFFF +#define DBG_CSR_APBMON_DSB_MATCH1_PADDR_LO___S 0 + +#define DBG_CSR_APBMON_DSB_MATCH1_PADDR_HI (0x00B91428) +#define DBG_CSR_APBMON_DSB_MATCH1_PADDR_HI___RWC QCSR_REG_RW +#define DBG_CSR_APBMON_DSB_MATCH1_PADDR_HI___POR 0x00000000 +#define DBG_CSR_APBMON_DSB_MATCH1_PADDR_HI__ADDRHI___POR 0x000000 +#define DBG_CSR_APBMON_DSB_MATCH1_PADDR_HI__ADDRHI___M 0x00FFFFFF +#define DBG_CSR_APBMON_DSB_MATCH1_PADDR_HI__ADDRHI___S 0 +#define DBG_CSR_APBMON_DSB_MATCH1_PADDR_HI___M 0x00FFFFFF +#define DBG_CSR_APBMON_DSB_MATCH1_PADDR_HI___S 0 + +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS (0x00B9142C) +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS___RWC QCSR_REG_RW +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS___POR 0x00000000 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__RESP_TYPE___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__XFER_TYPE___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL15_RSVD___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL14_RSVD___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL13_RSVD___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL12_RSVD___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL11_RSVD___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL10_RSVD___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL9_RSVD___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_WCSS_DBG___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_PMM_TOP___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_WFSS_PMM___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_WCMN_CORE___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_WCMN___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_TSLV___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_WMAC0___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_UMAC___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_PHYA___POR 0x0 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__RESP_TYPE___M 0x00020000 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__RESP_TYPE___S 17 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__RESP_TYPE__OKAY 0x0 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__RESP_TYPE__ERROR 0x1 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__XFER_TYPE___M 0x00010000 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__XFER_TYPE___S 16 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__XFER_TYPE__READ 0x0 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__XFER_TYPE__WRITE 0x1 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL15_RSVD___M 0x00008000 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL15_RSVD___S 15 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL14_RSVD___M 0x00004000 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL14_RSVD___S 14 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL13_RSVD___M 0x00002000 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL13_RSVD___S 13 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL12_RSVD___M 0x00001000 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL12_RSVD___S 12 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL11_RSVD___M 0x00000800 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL11_RSVD___S 11 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL10_RSVD___M 0x00000400 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL10_RSVD___S 10 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL9_RSVD___M 0x00000200 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL9_RSVD___S 9 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_WCSS_DBG___M 0x00000100 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_WCSS_DBG___S 8 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_PMM_TOP___M 0x00000080 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_PMM_TOP___S 7 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_WFSS_PMM___M 0x00000040 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_WFSS_PMM___S 6 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_WCMN_CORE___M 0x00000020 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_WCMN_CORE___S 5 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_WCMN___M 0x00000010 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_WCMN___S 4 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_TSLV___M 0x00000008 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_TSLV___S 3 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_WMAC0___M 0x00000004 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_WMAC0___S 2 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_UMAC___M 0x00000002 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_UMAC___S 1 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_PHYA___M 0x00000001 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS__PSEL_PHYA___S 0 +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS___M 0x0003FFFF +#define DBG_CSR_APBMON_DSB_MATCH1_DETAILS___S 0 + +#define DBG_CSR_APBMON_DSB_MATCH1_PDATA_MASK (0x00B91430) +#define DBG_CSR_APBMON_DSB_MATCH1_PDATA_MASK___RWC QCSR_REG_RW +#define DBG_CSR_APBMON_DSB_MATCH1_PDATA_MASK___POR 0xFFFFFFFF +#define DBG_CSR_APBMON_DSB_MATCH1_PDATA_MASK__MASK___POR 0xFFFFFFFF +#define DBG_CSR_APBMON_DSB_MATCH1_PDATA_MASK__MASK___M 0xFFFFFFFF +#define DBG_CSR_APBMON_DSB_MATCH1_PDATA_MASK__MASK___S 0 +#define DBG_CSR_APBMON_DSB_MATCH1_PDATA_MASK___M 0xFFFFFFFF +#define DBG_CSR_APBMON_DSB_MATCH1_PDATA_MASK___S 0 + +#define DBG_CSR_APBMON_DSB_MATCH1_PDATA (0x00B91434) +#define DBG_CSR_APBMON_DSB_MATCH1_PDATA___RWC QCSR_REG_RW +#define DBG_CSR_APBMON_DSB_MATCH1_PDATA___POR 0x00000000 +#define DBG_CSR_APBMON_DSB_MATCH1_PDATA__DATA___POR 0x00000000 +#define DBG_CSR_APBMON_DSB_MATCH1_PDATA__DATA___M 0xFFFFFFFF +#define DBG_CSR_APBMON_DSB_MATCH1_PDATA__DATA___S 0 +#define DBG_CSR_APBMON_DSB_MATCH1_PDATA___M 0xFFFFFFFF +#define DBG_CSR_APBMON_DSB_MATCH1_PDATA___S 0 + +#define DBG_CSR_APBMON_MAX_LATENCY (0x00B91438) +#define DBG_CSR_APBMON_MAX_LATENCY___RWC QCSR_REG_RW +#define DBG_CSR_APBMON_MAX_LATENCY___POR 0x00000400 +#define DBG_CSR_APBMON_MAX_LATENCY__LATENCY___POR 0x00400 +#define DBG_CSR_APBMON_MAX_LATENCY__LATENCY___M 0x0001FFFF +#define DBG_CSR_APBMON_MAX_LATENCY__LATENCY___S 0 +#define DBG_CSR_APBMON_MAX_LATENCY___M 0x0001FFFF +#define DBG_CSR_APBMON_MAX_LATENCY___S 0 + +#define DBG_CSR_APBMON_CMB_CFG (0x00B9143C) +#define DBG_CSR_APBMON_CMB_CFG___RWC QCSR_REG_RW +#define DBG_CSR_APBMON_CMB_CFG___POR 0x00000000 +#define DBG_CSR_APBMON_CMB_CFG__DATA_EN___POR 0x0 +#define DBG_CSR_APBMON_CMB_CFG__ENABLE___POR 0x0 +#define DBG_CSR_APBMON_CMB_CFG__DATA_EN___M 0x00000002 +#define DBG_CSR_APBMON_CMB_CFG__DATA_EN___S 1 +#define DBG_CSR_APBMON_CMB_CFG__ENABLE___M 0x00000001 +#define DBG_CSR_APBMON_CMB_CFG__ENABLE___S 0 +#define DBG_CSR_APBMON_CMB_CFG___M 0x00000003 +#define DBG_CSR_APBMON_CMB_CFG___S 0 + +#define DBG_CSR_APBMON_CMB_MATCH_CTRL (0x00B91440) +#define DBG_CSR_APBMON_CMB_MATCH_CTRL___RWC QCSR_REG_RW +#define DBG_CSR_APBMON_CMB_MATCH_CTRL___POR 0x00000000 +#define DBG_CSR_APBMON_CMB_MATCH_CTRL__DATA_EN___POR 0x0 +#define DBG_CSR_APBMON_CMB_MATCH_CTRL__LATENCY_EN___POR 0x0 +#define DBG_CSR_APBMON_CMB_MATCH_CTRL__RESP_TYPE_EN___POR 0x0 +#define DBG_CSR_APBMON_CMB_MATCH_CTRL__XFER_TYPE_EN___POR 0x0 +#define DBG_CSR_APBMON_CMB_MATCH_CTRL__PSEL_EN___POR 0x0 +#define DBG_CSR_APBMON_CMB_MATCH_CTRL__ADDR_EN___POR 0x0 +#define DBG_CSR_APBMON_CMB_MATCH_CTRL__ENABLE___POR 0x0 +#define DBG_CSR_APBMON_CMB_MATCH_CTRL__DATA_EN___M 0x00000040 +#define DBG_CSR_APBMON_CMB_MATCH_CTRL__DATA_EN___S 6 +#define DBG_CSR_APBMON_CMB_MATCH_CTRL__LATENCY_EN___M 0x00000020 +#define DBG_CSR_APBMON_CMB_MATCH_CTRL__LATENCY_EN___S 5 +#define DBG_CSR_APBMON_CMB_MATCH_CTRL__RESP_TYPE_EN___M 0x00000010 +#define DBG_CSR_APBMON_CMB_MATCH_CTRL__RESP_TYPE_EN___S 4 +#define DBG_CSR_APBMON_CMB_MATCH_CTRL__XFER_TYPE_EN___M 0x00000008 +#define DBG_CSR_APBMON_CMB_MATCH_CTRL__XFER_TYPE_EN___S 3 +#define DBG_CSR_APBMON_CMB_MATCH_CTRL__PSEL_EN___M 0x00000004 +#define DBG_CSR_APBMON_CMB_MATCH_CTRL__PSEL_EN___S 2 +#define DBG_CSR_APBMON_CMB_MATCH_CTRL__ADDR_EN___M 0x00000002 +#define DBG_CSR_APBMON_CMB_MATCH_CTRL__ADDR_EN___S 1 +#define DBG_CSR_APBMON_CMB_MATCH_CTRL__ENABLE___M 0x00000001 +#define DBG_CSR_APBMON_CMB_MATCH_CTRL__ENABLE___S 0 +#define DBG_CSR_APBMON_CMB_MATCH_CTRL___M 0x0000007F +#define DBG_CSR_APBMON_CMB_MATCH_CTRL___S 0 + +#define DBG_CSR_APBMON_CMB_MATCH_PADDR_MASK (0x00B91444) +#define DBG_CSR_APBMON_CMB_MATCH_PADDR_MASK___RWC QCSR_REG_RW +#define DBG_CSR_APBMON_CMB_MATCH_PADDR_MASK___POR 0x00000000 +#define DBG_CSR_APBMON_CMB_MATCH_PADDR_MASK__MASK___POR 0x000000 +#define DBG_CSR_APBMON_CMB_MATCH_PADDR_MASK__MASK___M 0x00FFFFFF +#define DBG_CSR_APBMON_CMB_MATCH_PADDR_MASK__MASK___S 0 +#define DBG_CSR_APBMON_CMB_MATCH_PADDR_MASK___M 0x00FFFFFF +#define DBG_CSR_APBMON_CMB_MATCH_PADDR_MASK___S 0 + +#define DBG_CSR_APBMON_CMB_MATCH_PADDR_LO (0x00B91448) +#define DBG_CSR_APBMON_CMB_MATCH_PADDR_LO___RWC QCSR_REG_RW +#define DBG_CSR_APBMON_CMB_MATCH_PADDR_LO___POR 0x00000000 +#define DBG_CSR_APBMON_CMB_MATCH_PADDR_LO__ADDRLO___POR 0x000000 +#define DBG_CSR_APBMON_CMB_MATCH_PADDR_LO__ADDRLO___M 0x00FFFFFF +#define DBG_CSR_APBMON_CMB_MATCH_PADDR_LO__ADDRLO___S 0 +#define DBG_CSR_APBMON_CMB_MATCH_PADDR_LO___M 0x00FFFFFF +#define DBG_CSR_APBMON_CMB_MATCH_PADDR_LO___S 0 + +#define DBG_CSR_APBMON_CMB_MATCH_PADDR_HI (0x00B9144C) +#define DBG_CSR_APBMON_CMB_MATCH_PADDR_HI___RWC QCSR_REG_RW +#define DBG_CSR_APBMON_CMB_MATCH_PADDR_HI___POR 0x00000000 +#define DBG_CSR_APBMON_CMB_MATCH_PADDR_HI__ADDRHI___POR 0x000000 +#define DBG_CSR_APBMON_CMB_MATCH_PADDR_HI__ADDRHI___M 0x00FFFFFF +#define DBG_CSR_APBMON_CMB_MATCH_PADDR_HI__ADDRHI___S 0 +#define DBG_CSR_APBMON_CMB_MATCH_PADDR_HI___M 0x00FFFFFF +#define DBG_CSR_APBMON_CMB_MATCH_PADDR_HI___S 0 + +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS (0x00B91450) +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS___RWC QCSR_REG_RW +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS___POR 0x00000000 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__RESP_TYPE___POR 0x0 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__XFER_TYPE___POR 0x0 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL15_RSVD___POR 0x0 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL14_RSVD___POR 0x0 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL13_RSVD___POR 0x0 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL12_RSVD___POR 0x0 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL11_RSVD___POR 0x0 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL10_RSVD___POR 0x0 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL9_RSVD___POR 0x0 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_WCSS_DBG___POR 0x0 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_PMM_TOP___POR 0x0 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_WFSS_PMM___POR 0x0 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_WCMN_CORE___POR 0x0 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_WCMN___POR 0x0 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_TSLV___POR 0x0 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_WMAC0___POR 0x0 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_UMAC___POR 0x0 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_PHYA___POR 0x0 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__RESP_TYPE___M 0x00020000 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__RESP_TYPE___S 17 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__RESP_TYPE__OKAY 0x0 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__RESP_TYPE__ERROR 0x1 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__XFER_TYPE___M 0x00010000 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__XFER_TYPE___S 16 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__XFER_TYPE__READ 0x0 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__XFER_TYPE__WRITE 0x1 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL15_RSVD___M 0x00008000 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL15_RSVD___S 15 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL14_RSVD___M 0x00004000 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL14_RSVD___S 14 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL13_RSVD___M 0x00002000 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL13_RSVD___S 13 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL12_RSVD___M 0x00001000 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL12_RSVD___S 12 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL11_RSVD___M 0x00000800 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL11_RSVD___S 11 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL10_RSVD___M 0x00000400 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL10_RSVD___S 10 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL9_RSVD___M 0x00000200 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL9_RSVD___S 9 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_WCSS_DBG___M 0x00000100 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_WCSS_DBG___S 8 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_PMM_TOP___M 0x00000080 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_PMM_TOP___S 7 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_WFSS_PMM___M 0x00000040 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_WFSS_PMM___S 6 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_WCMN_CORE___M 0x00000020 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_WCMN_CORE___S 5 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_WCMN___M 0x00000010 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_WCMN___S 4 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_TSLV___M 0x00000008 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_TSLV___S 3 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_WMAC0___M 0x00000004 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_WMAC0___S 2 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_UMAC___M 0x00000002 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_UMAC___S 1 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_PHYA___M 0x00000001 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS__PSEL_PHYA___S 0 +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS___M 0x0003FFFF +#define DBG_CSR_APBMON_CMB_MATCH_DETAILS___S 0 + +#define DBG_CSR_APBMON_CMB_MATCH_PDATA_MASK (0x00B91454) +#define DBG_CSR_APBMON_CMB_MATCH_PDATA_MASK___RWC QCSR_REG_RW +#define DBG_CSR_APBMON_CMB_MATCH_PDATA_MASK___POR 0x00000000 +#define DBG_CSR_APBMON_CMB_MATCH_PDATA_MASK__MASK___POR 0x00000000 +#define DBG_CSR_APBMON_CMB_MATCH_PDATA_MASK__MASK___M 0xFFFFFFFF +#define DBG_CSR_APBMON_CMB_MATCH_PDATA_MASK__MASK___S 0 +#define DBG_CSR_APBMON_CMB_MATCH_PDATA_MASK___M 0xFFFFFFFF +#define DBG_CSR_APBMON_CMB_MATCH_PDATA_MASK___S 0 + +#define DBG_CSR_APBMON_CMB_MATCH_PDATA (0x00B91458) +#define DBG_CSR_APBMON_CMB_MATCH_PDATA___RWC QCSR_REG_RW +#define DBG_CSR_APBMON_CMB_MATCH_PDATA___POR 0x00000000 +#define DBG_CSR_APBMON_CMB_MATCH_PDATA__DATA___POR 0x00000000 +#define DBG_CSR_APBMON_CMB_MATCH_PDATA__DATA___M 0xFFFFFFFF +#define DBG_CSR_APBMON_CMB_MATCH_PDATA__DATA___S 0 +#define DBG_CSR_APBMON_CMB_MATCH_PDATA___M 0xFFFFFFFF +#define DBG_CSR_APBMON_CMB_MATCH_PDATA___S 0 + +#define DBG_CSR_APBMON_LST_XFER_ADDR (0x00B9145C) +#define DBG_CSR_APBMON_LST_XFER_ADDR___RWC QCSR_REG_RO +#define DBG_CSR_APBMON_LST_XFER_ADDR___POR 0x00000000 +#define DBG_CSR_APBMON_LST_XFER_ADDR__ADDR___POR 0x000000 +#define DBG_CSR_APBMON_LST_XFER_ADDR__ADDR___M 0x00FFFFFF +#define DBG_CSR_APBMON_LST_XFER_ADDR__ADDR___S 0 +#define DBG_CSR_APBMON_LST_XFER_ADDR___M 0x00FFFFFF +#define DBG_CSR_APBMON_LST_XFER_ADDR___S 0 + +#define DBG_CSR_APBMON_LST_XFER_DETAILS (0x00B91460) +#define DBG_CSR_APBMON_LST_XFER_DETAILS___RWC QCSR_REG_RO +#define DBG_CSR_APBMON_LST_XFER_DETAILS___POR 0x00000000 +#define DBG_CSR_APBMON_LST_XFER_DETAILS__LATENCY___POR 0x00000 +#define DBG_CSR_APBMON_LST_XFER_DETAILS__RESP_TYPE___POR 0x0 +#define DBG_CSR_APBMON_LST_XFER_DETAILS__XFER_TYPE___POR 0x0 +#define DBG_CSR_APBMON_LST_XFER_DETAILS__PSEL___POR 0x0 +#define DBG_CSR_APBMON_LST_XFER_DETAILS__LATENCY___M 0x01FFFFC0 +#define DBG_CSR_APBMON_LST_XFER_DETAILS__LATENCY___S 6 +#define DBG_CSR_APBMON_LST_XFER_DETAILS__RESP_TYPE___M 0x00000020 +#define DBG_CSR_APBMON_LST_XFER_DETAILS__RESP_TYPE___S 5 +#define DBG_CSR_APBMON_LST_XFER_DETAILS__RESP_TYPE__OKAY 0x0 +#define DBG_CSR_APBMON_LST_XFER_DETAILS__RESP_TYPE__ERROR 0x1 +#define DBG_CSR_APBMON_LST_XFER_DETAILS__XFER_TYPE___M 0x00000010 +#define DBG_CSR_APBMON_LST_XFER_DETAILS__XFER_TYPE___S 4 +#define DBG_CSR_APBMON_LST_XFER_DETAILS__XFER_TYPE__READ 0x0 +#define DBG_CSR_APBMON_LST_XFER_DETAILS__XFER_TYPE__WRITE 0x1 +#define DBG_CSR_APBMON_LST_XFER_DETAILS__PSEL___M 0x0000000F +#define DBG_CSR_APBMON_LST_XFER_DETAILS__PSEL___S 0 +#define DBG_CSR_APBMON_LST_XFER_DETAILS__PSEL__PHYA 0x0 +#define DBG_CSR_APBMON_LST_XFER_DETAILS__PSEL__UMAC 0x1 +#define DBG_CSR_APBMON_LST_XFER_DETAILS__PSEL__WMAC0 0x2 +#define DBG_CSR_APBMON_LST_XFER_DETAILS__PSEL__TSLV 0x3 +#define DBG_CSR_APBMON_LST_XFER_DETAILS__PSEL__WCMN 0x4 +#define DBG_CSR_APBMON_LST_XFER_DETAILS__PSEL__WCMN_CORE 0x5 +#define DBG_CSR_APBMON_LST_XFER_DETAILS__PSEL__WFSSPMM 0x6 +#define DBG_CSR_APBMON_LST_XFER_DETAILS__PSEL__TOPPMM 0x7 +#define DBG_CSR_APBMON_LST_XFER_DETAILS__PSEL__WCSS_DBG 0x8 +#define DBG_CSR_APBMON_LST_XFER_DETAILS___M 0x01FFFFFF +#define DBG_CSR_APBMON_LST_XFER_DETAILS___S 0 + +#define DBG_CSR_APBMON_LST_XFER_DATA (0x00B91464) +#define DBG_CSR_APBMON_LST_XFER_DATA___RWC QCSR_REG_RO +#define DBG_CSR_APBMON_LST_XFER_DATA___POR 0x00000000 +#define DBG_CSR_APBMON_LST_XFER_DATA__DATA___POR 0x00000000 +#define DBG_CSR_APBMON_LST_XFER_DATA__DATA___M 0xFFFFFFFF +#define DBG_CSR_APBMON_LST_XFER_DATA__DATA___S 0 +#define DBG_CSR_APBMON_LST_XFER_DATA___M 0xFFFFFFFF +#define DBG_CSR_APBMON_LST_XFER_DATA___S 0 + +#define DBG_CSR_APBMON_LST_XFER_TSTMP_LO (0x00B91468) +#define DBG_CSR_APBMON_LST_XFER_TSTMP_LO___RWC QCSR_REG_RO +#define DBG_CSR_APBMON_LST_XFER_TSTMP_LO___POR 0x00000000 +#define DBG_CSR_APBMON_LST_XFER_TSTMP_LO__TSTMP_31_0___POR 0x00000000 +#define DBG_CSR_APBMON_LST_XFER_TSTMP_LO__TSTMP_31_0___M 0xFFFFFFFF +#define DBG_CSR_APBMON_LST_XFER_TSTMP_LO__TSTMP_31_0___S 0 +#define DBG_CSR_APBMON_LST_XFER_TSTMP_LO___M 0xFFFFFFFF +#define DBG_CSR_APBMON_LST_XFER_TSTMP_LO___S 0 + +#define DBG_CSR_APBMON_LST_XFER_TSTMP_HI (0x00B9146C) +#define DBG_CSR_APBMON_LST_XFER_TSTMP_HI___RWC QCSR_REG_RO +#define DBG_CSR_APBMON_LST_XFER_TSTMP_HI___POR 0x00000000 +#define DBG_CSR_APBMON_LST_XFER_TSTMP_HI__TSTMP_63_32___POR 0x00000000 +#define DBG_CSR_APBMON_LST_XFER_TSTMP_HI__TSTMP_63_32___M 0xFFFFFFFF +#define DBG_CSR_APBMON_LST_XFER_TSTMP_HI__TSTMP_63_32___S 0 +#define DBG_CSR_APBMON_LST_XFER_TSTMP_HI___M 0xFFFFFFFF +#define DBG_CSR_APBMON_LST_XFER_TSTMP_HI___S 0 + +#define DBG_CSR_INTR_EDGE_SEL0 (0x00B91800) +#define DBG_CSR_INTR_EDGE_SEL0___RWC QCSR_REG_RW +#define DBG_CSR_INTR_EDGE_SEL0___POR 0x00000000 +#define DBG_CSR_INTR_EDGE_SEL0__BIT15_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL0__BIT14_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL0__BIT13_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL0__BIT12_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL0__BIT11_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL0__BIT10_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL0__BIT9_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL0__BIT8_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL0__BIT7_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL0__BIT6_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL0__BIT5_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL0__BIT4_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL0__BIT3_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL0__BIT2_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL0__BIT1_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL0__BIT0_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL0__BIT15_EDGE_SEL___M 0xC0000000 +#define DBG_CSR_INTR_EDGE_SEL0__BIT15_EDGE_SEL___S 30 +#define DBG_CSR_INTR_EDGE_SEL0__BIT15_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL0__BIT15_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL0__BIT15_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL0__BIT14_EDGE_SEL___M 0x30000000 +#define DBG_CSR_INTR_EDGE_SEL0__BIT14_EDGE_SEL___S 28 +#define DBG_CSR_INTR_EDGE_SEL0__BIT14_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL0__BIT14_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL0__BIT14_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL0__BIT13_EDGE_SEL___M 0x0C000000 +#define DBG_CSR_INTR_EDGE_SEL0__BIT13_EDGE_SEL___S 26 +#define DBG_CSR_INTR_EDGE_SEL0__BIT13_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL0__BIT13_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL0__BIT13_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL0__BIT12_EDGE_SEL___M 0x03000000 +#define DBG_CSR_INTR_EDGE_SEL0__BIT12_EDGE_SEL___S 24 +#define DBG_CSR_INTR_EDGE_SEL0__BIT12_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL0__BIT12_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL0__BIT12_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL0__BIT11_EDGE_SEL___M 0x00C00000 +#define DBG_CSR_INTR_EDGE_SEL0__BIT11_EDGE_SEL___S 22 +#define DBG_CSR_INTR_EDGE_SEL0__BIT11_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL0__BIT11_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL0__BIT11_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL0__BIT10_EDGE_SEL___M 0x00300000 +#define DBG_CSR_INTR_EDGE_SEL0__BIT10_EDGE_SEL___S 20 +#define DBG_CSR_INTR_EDGE_SEL0__BIT10_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL0__BIT10_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL0__BIT10_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL0__BIT9_EDGE_SEL___M 0x000C0000 +#define DBG_CSR_INTR_EDGE_SEL0__BIT9_EDGE_SEL___S 18 +#define DBG_CSR_INTR_EDGE_SEL0__BIT9_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL0__BIT9_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL0__BIT9_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL0__BIT8_EDGE_SEL___M 0x00030000 +#define DBG_CSR_INTR_EDGE_SEL0__BIT8_EDGE_SEL___S 16 +#define DBG_CSR_INTR_EDGE_SEL0__BIT8_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL0__BIT8_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL0__BIT8_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL0__BIT7_EDGE_SEL___M 0x0000C000 +#define DBG_CSR_INTR_EDGE_SEL0__BIT7_EDGE_SEL___S 14 +#define DBG_CSR_INTR_EDGE_SEL0__BIT7_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL0__BIT7_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL0__BIT7_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL0__BIT6_EDGE_SEL___M 0x00003000 +#define DBG_CSR_INTR_EDGE_SEL0__BIT6_EDGE_SEL___S 12 +#define DBG_CSR_INTR_EDGE_SEL0__BIT6_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL0__BIT6_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL0__BIT6_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL0__BIT5_EDGE_SEL___M 0x00000C00 +#define DBG_CSR_INTR_EDGE_SEL0__BIT5_EDGE_SEL___S 10 +#define DBG_CSR_INTR_EDGE_SEL0__BIT5_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL0__BIT5_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL0__BIT5_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL0__BIT4_EDGE_SEL___M 0x00000300 +#define DBG_CSR_INTR_EDGE_SEL0__BIT4_EDGE_SEL___S 8 +#define DBG_CSR_INTR_EDGE_SEL0__BIT4_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL0__BIT4_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL0__BIT4_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL0__BIT3_EDGE_SEL___M 0x000000C0 +#define DBG_CSR_INTR_EDGE_SEL0__BIT3_EDGE_SEL___S 6 +#define DBG_CSR_INTR_EDGE_SEL0__BIT3_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL0__BIT3_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL0__BIT3_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL0__BIT2_EDGE_SEL___M 0x00000030 +#define DBG_CSR_INTR_EDGE_SEL0__BIT2_EDGE_SEL___S 4 +#define DBG_CSR_INTR_EDGE_SEL0__BIT2_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL0__BIT2_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL0__BIT2_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL0__BIT1_EDGE_SEL___M 0x0000000C +#define DBG_CSR_INTR_EDGE_SEL0__BIT1_EDGE_SEL___S 2 +#define DBG_CSR_INTR_EDGE_SEL0__BIT1_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL0__BIT1_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL0__BIT1_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL0__BIT0_EDGE_SEL___M 0x00000003 +#define DBG_CSR_INTR_EDGE_SEL0__BIT0_EDGE_SEL___S 0 +#define DBG_CSR_INTR_EDGE_SEL0__BIT0_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL0__BIT0_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL0__BIT0_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL0___M 0xFFFFFFFF +#define DBG_CSR_INTR_EDGE_SEL0___S 0 + +#define DBG_CSR_INTR_EDGE_SEL1 (0x00B91804) +#define DBG_CSR_INTR_EDGE_SEL1___RWC QCSR_REG_RW +#define DBG_CSR_INTR_EDGE_SEL1___POR 0x00000000 +#define DBG_CSR_INTR_EDGE_SEL1__BIT31_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL1__BIT30_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL1__BIT29_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL1__BIT28_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL1__BIT27_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL1__BIT26_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL1__BIT25_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL1__BIT24_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL1__BIT23_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL1__BIT22_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL1__BIT21_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL1__BIT20_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL1__BIT19_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL1__BIT18_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL1__BIT17_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL1__BIT16_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL1__BIT31_EDGE_SEL___M 0xC0000000 +#define DBG_CSR_INTR_EDGE_SEL1__BIT31_EDGE_SEL___S 30 +#define DBG_CSR_INTR_EDGE_SEL1__BIT31_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL1__BIT31_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL1__BIT31_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL1__BIT30_EDGE_SEL___M 0x30000000 +#define DBG_CSR_INTR_EDGE_SEL1__BIT30_EDGE_SEL___S 28 +#define DBG_CSR_INTR_EDGE_SEL1__BIT30_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL1__BIT30_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL1__BIT30_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL1__BIT29_EDGE_SEL___M 0x0C000000 +#define DBG_CSR_INTR_EDGE_SEL1__BIT29_EDGE_SEL___S 26 +#define DBG_CSR_INTR_EDGE_SEL1__BIT29_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL1__BIT29_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL1__BIT29_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL1__BIT28_EDGE_SEL___M 0x03000000 +#define DBG_CSR_INTR_EDGE_SEL1__BIT28_EDGE_SEL___S 24 +#define DBG_CSR_INTR_EDGE_SEL1__BIT28_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL1__BIT28_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL1__BIT28_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL1__BIT27_EDGE_SEL___M 0x00C00000 +#define DBG_CSR_INTR_EDGE_SEL1__BIT27_EDGE_SEL___S 22 +#define DBG_CSR_INTR_EDGE_SEL1__BIT27_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL1__BIT27_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL1__BIT27_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL1__BIT26_EDGE_SEL___M 0x00300000 +#define DBG_CSR_INTR_EDGE_SEL1__BIT26_EDGE_SEL___S 20 +#define DBG_CSR_INTR_EDGE_SEL1__BIT26_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL1__BIT26_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL1__BIT26_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL1__BIT25_EDGE_SEL___M 0x000C0000 +#define DBG_CSR_INTR_EDGE_SEL1__BIT25_EDGE_SEL___S 18 +#define DBG_CSR_INTR_EDGE_SEL1__BIT25_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL1__BIT25_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL1__BIT25_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL1__BIT24_EDGE_SEL___M 0x00030000 +#define DBG_CSR_INTR_EDGE_SEL1__BIT24_EDGE_SEL___S 16 +#define DBG_CSR_INTR_EDGE_SEL1__BIT24_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL1__BIT24_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL1__BIT24_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL1__BIT23_EDGE_SEL___M 0x0000C000 +#define DBG_CSR_INTR_EDGE_SEL1__BIT23_EDGE_SEL___S 14 +#define DBG_CSR_INTR_EDGE_SEL1__BIT23_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL1__BIT23_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL1__BIT23_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL1__BIT22_EDGE_SEL___M 0x00003000 +#define DBG_CSR_INTR_EDGE_SEL1__BIT22_EDGE_SEL___S 12 +#define DBG_CSR_INTR_EDGE_SEL1__BIT22_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL1__BIT22_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL1__BIT22_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL1__BIT21_EDGE_SEL___M 0x00000C00 +#define DBG_CSR_INTR_EDGE_SEL1__BIT21_EDGE_SEL___S 10 +#define DBG_CSR_INTR_EDGE_SEL1__BIT21_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL1__BIT21_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL1__BIT21_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL1__BIT20_EDGE_SEL___M 0x00000300 +#define DBG_CSR_INTR_EDGE_SEL1__BIT20_EDGE_SEL___S 8 +#define DBG_CSR_INTR_EDGE_SEL1__BIT20_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL1__BIT20_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL1__BIT20_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL1__BIT19_EDGE_SEL___M 0x000000C0 +#define DBG_CSR_INTR_EDGE_SEL1__BIT19_EDGE_SEL___S 6 +#define DBG_CSR_INTR_EDGE_SEL1__BIT19_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL1__BIT19_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL1__BIT19_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL1__BIT18_EDGE_SEL___M 0x00000030 +#define DBG_CSR_INTR_EDGE_SEL1__BIT18_EDGE_SEL___S 4 +#define DBG_CSR_INTR_EDGE_SEL1__BIT18_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL1__BIT18_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL1__BIT18_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL1__BIT17_EDGE_SEL___M 0x0000000C +#define DBG_CSR_INTR_EDGE_SEL1__BIT17_EDGE_SEL___S 2 +#define DBG_CSR_INTR_EDGE_SEL1__BIT17_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL1__BIT17_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL1__BIT17_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL1__BIT16_EDGE_SEL___M 0x00000003 +#define DBG_CSR_INTR_EDGE_SEL1__BIT16_EDGE_SEL___S 0 +#define DBG_CSR_INTR_EDGE_SEL1__BIT16_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL1__BIT16_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL1__BIT16_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL1___M 0xFFFFFFFF +#define DBG_CSR_INTR_EDGE_SEL1___S 0 + +#define DBG_CSR_INTR_EDGE_SEL2 (0x00B91808) +#define DBG_CSR_INTR_EDGE_SEL2___RWC QCSR_REG_RW +#define DBG_CSR_INTR_EDGE_SEL2___POR 0x00000000 +#define DBG_CSR_INTR_EDGE_SEL2__BIT47_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL2__BIT46_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL2__BIT45_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL2__BIT44_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL2__BIT43_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL2__BIT42_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL2__BIT41_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL2__BIT40_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL2__BIT39_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL2__BIT38_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL2__BIT37_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL2__BIT36_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL2__BIT35_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL2__BIT34_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL2__BIT33_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL2__BIT32_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL2__BIT47_EDGE_SEL___M 0xC0000000 +#define DBG_CSR_INTR_EDGE_SEL2__BIT47_EDGE_SEL___S 30 +#define DBG_CSR_INTR_EDGE_SEL2__BIT47_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL2__BIT47_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL2__BIT47_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL2__BIT46_EDGE_SEL___M 0x30000000 +#define DBG_CSR_INTR_EDGE_SEL2__BIT46_EDGE_SEL___S 28 +#define DBG_CSR_INTR_EDGE_SEL2__BIT46_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL2__BIT46_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL2__BIT46_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL2__BIT45_EDGE_SEL___M 0x0C000000 +#define DBG_CSR_INTR_EDGE_SEL2__BIT45_EDGE_SEL___S 26 +#define DBG_CSR_INTR_EDGE_SEL2__BIT45_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL2__BIT45_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL2__BIT45_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL2__BIT44_EDGE_SEL___M 0x03000000 +#define DBG_CSR_INTR_EDGE_SEL2__BIT44_EDGE_SEL___S 24 +#define DBG_CSR_INTR_EDGE_SEL2__BIT44_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL2__BIT44_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL2__BIT44_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL2__BIT43_EDGE_SEL___M 0x00C00000 +#define DBG_CSR_INTR_EDGE_SEL2__BIT43_EDGE_SEL___S 22 +#define DBG_CSR_INTR_EDGE_SEL2__BIT43_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL2__BIT43_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL2__BIT43_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL2__BIT42_EDGE_SEL___M 0x00300000 +#define DBG_CSR_INTR_EDGE_SEL2__BIT42_EDGE_SEL___S 20 +#define DBG_CSR_INTR_EDGE_SEL2__BIT42_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL2__BIT42_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL2__BIT42_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL2__BIT41_EDGE_SEL___M 0x000C0000 +#define DBG_CSR_INTR_EDGE_SEL2__BIT41_EDGE_SEL___S 18 +#define DBG_CSR_INTR_EDGE_SEL2__BIT41_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL2__BIT41_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL2__BIT41_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL2__BIT40_EDGE_SEL___M 0x00030000 +#define DBG_CSR_INTR_EDGE_SEL2__BIT40_EDGE_SEL___S 16 +#define DBG_CSR_INTR_EDGE_SEL2__BIT40_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL2__BIT40_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL2__BIT40_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL2__BIT39_EDGE_SEL___M 0x0000C000 +#define DBG_CSR_INTR_EDGE_SEL2__BIT39_EDGE_SEL___S 14 +#define DBG_CSR_INTR_EDGE_SEL2__BIT39_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL2__BIT39_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL2__BIT39_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL2__BIT38_EDGE_SEL___M 0x00003000 +#define DBG_CSR_INTR_EDGE_SEL2__BIT38_EDGE_SEL___S 12 +#define DBG_CSR_INTR_EDGE_SEL2__BIT38_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL2__BIT38_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL2__BIT38_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL2__BIT37_EDGE_SEL___M 0x00000C00 +#define DBG_CSR_INTR_EDGE_SEL2__BIT37_EDGE_SEL___S 10 +#define DBG_CSR_INTR_EDGE_SEL2__BIT37_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL2__BIT37_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL2__BIT37_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL2__BIT36_EDGE_SEL___M 0x00000300 +#define DBG_CSR_INTR_EDGE_SEL2__BIT36_EDGE_SEL___S 8 +#define DBG_CSR_INTR_EDGE_SEL2__BIT36_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL2__BIT36_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL2__BIT36_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL2__BIT35_EDGE_SEL___M 0x000000C0 +#define DBG_CSR_INTR_EDGE_SEL2__BIT35_EDGE_SEL___S 6 +#define DBG_CSR_INTR_EDGE_SEL2__BIT35_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL2__BIT35_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL2__BIT35_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL2__BIT34_EDGE_SEL___M 0x00000030 +#define DBG_CSR_INTR_EDGE_SEL2__BIT34_EDGE_SEL___S 4 +#define DBG_CSR_INTR_EDGE_SEL2__BIT34_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL2__BIT34_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL2__BIT34_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL2__BIT33_EDGE_SEL___M 0x0000000C +#define DBG_CSR_INTR_EDGE_SEL2__BIT33_EDGE_SEL___S 2 +#define DBG_CSR_INTR_EDGE_SEL2__BIT33_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL2__BIT33_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL2__BIT33_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL2__BIT32_EDGE_SEL___M 0x00000003 +#define DBG_CSR_INTR_EDGE_SEL2__BIT32_EDGE_SEL___S 0 +#define DBG_CSR_INTR_EDGE_SEL2__BIT32_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL2__BIT32_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL2__BIT32_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL2___M 0xFFFFFFFF +#define DBG_CSR_INTR_EDGE_SEL2___S 0 + +#define DBG_CSR_INTR_EDGE_SEL3 (0x00B9180C) +#define DBG_CSR_INTR_EDGE_SEL3___RWC QCSR_REG_RW +#define DBG_CSR_INTR_EDGE_SEL3___POR 0x00000000 +#define DBG_CSR_INTR_EDGE_SEL3__BIT63_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL3__BIT62_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL3__BIT61_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL3__BIT60_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL3__BIT59_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL3__BIT58_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL3__BIT57_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL3__BIT56_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL3__BIT55_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL3__BIT54_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL3__BIT53_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL3__BIT52_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL3__BIT51_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL3__BIT50_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL3__BIT49_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL3__BIT48_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL3__BIT63_EDGE_SEL___M 0xC0000000 +#define DBG_CSR_INTR_EDGE_SEL3__BIT63_EDGE_SEL___S 30 +#define DBG_CSR_INTR_EDGE_SEL3__BIT63_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL3__BIT63_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL3__BIT63_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL3__BIT62_EDGE_SEL___M 0x30000000 +#define DBG_CSR_INTR_EDGE_SEL3__BIT62_EDGE_SEL___S 28 +#define DBG_CSR_INTR_EDGE_SEL3__BIT62_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL3__BIT62_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL3__BIT62_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL3__BIT61_EDGE_SEL___M 0x0C000000 +#define DBG_CSR_INTR_EDGE_SEL3__BIT61_EDGE_SEL___S 26 +#define DBG_CSR_INTR_EDGE_SEL3__BIT61_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL3__BIT61_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL3__BIT61_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL3__BIT60_EDGE_SEL___M 0x03000000 +#define DBG_CSR_INTR_EDGE_SEL3__BIT60_EDGE_SEL___S 24 +#define DBG_CSR_INTR_EDGE_SEL3__BIT60_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL3__BIT60_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL3__BIT60_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL3__BIT59_EDGE_SEL___M 0x00C00000 +#define DBG_CSR_INTR_EDGE_SEL3__BIT59_EDGE_SEL___S 22 +#define DBG_CSR_INTR_EDGE_SEL3__BIT59_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL3__BIT59_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL3__BIT59_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL3__BIT58_EDGE_SEL___M 0x00300000 +#define DBG_CSR_INTR_EDGE_SEL3__BIT58_EDGE_SEL___S 20 +#define DBG_CSR_INTR_EDGE_SEL3__BIT58_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL3__BIT58_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL3__BIT58_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL3__BIT57_EDGE_SEL___M 0x000C0000 +#define DBG_CSR_INTR_EDGE_SEL3__BIT57_EDGE_SEL___S 18 +#define DBG_CSR_INTR_EDGE_SEL3__BIT57_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL3__BIT57_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL3__BIT57_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL3__BIT56_EDGE_SEL___M 0x00030000 +#define DBG_CSR_INTR_EDGE_SEL3__BIT56_EDGE_SEL___S 16 +#define DBG_CSR_INTR_EDGE_SEL3__BIT56_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL3__BIT56_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL3__BIT56_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL3__BIT55_EDGE_SEL___M 0x0000C000 +#define DBG_CSR_INTR_EDGE_SEL3__BIT55_EDGE_SEL___S 14 +#define DBG_CSR_INTR_EDGE_SEL3__BIT55_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL3__BIT55_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL3__BIT55_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL3__BIT54_EDGE_SEL___M 0x00003000 +#define DBG_CSR_INTR_EDGE_SEL3__BIT54_EDGE_SEL___S 12 +#define DBG_CSR_INTR_EDGE_SEL3__BIT54_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL3__BIT54_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL3__BIT54_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL3__BIT53_EDGE_SEL___M 0x00000C00 +#define DBG_CSR_INTR_EDGE_SEL3__BIT53_EDGE_SEL___S 10 +#define DBG_CSR_INTR_EDGE_SEL3__BIT53_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL3__BIT53_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL3__BIT53_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL3__BIT52_EDGE_SEL___M 0x00000300 +#define DBG_CSR_INTR_EDGE_SEL3__BIT52_EDGE_SEL___S 8 +#define DBG_CSR_INTR_EDGE_SEL3__BIT52_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL3__BIT52_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL3__BIT52_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL3__BIT51_EDGE_SEL___M 0x000000C0 +#define DBG_CSR_INTR_EDGE_SEL3__BIT51_EDGE_SEL___S 6 +#define DBG_CSR_INTR_EDGE_SEL3__BIT51_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL3__BIT51_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL3__BIT51_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL3__BIT50_EDGE_SEL___M 0x00000030 +#define DBG_CSR_INTR_EDGE_SEL3__BIT50_EDGE_SEL___S 4 +#define DBG_CSR_INTR_EDGE_SEL3__BIT50_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL3__BIT50_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL3__BIT50_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL3__BIT49_EDGE_SEL___M 0x0000000C +#define DBG_CSR_INTR_EDGE_SEL3__BIT49_EDGE_SEL___S 2 +#define DBG_CSR_INTR_EDGE_SEL3__BIT49_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL3__BIT49_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL3__BIT49_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL3__BIT48_EDGE_SEL___M 0x00000003 +#define DBG_CSR_INTR_EDGE_SEL3__BIT48_EDGE_SEL___S 0 +#define DBG_CSR_INTR_EDGE_SEL3__BIT48_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL3__BIT48_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL3__BIT48_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL3___M 0xFFFFFFFF +#define DBG_CSR_INTR_EDGE_SEL3___S 0 + +#define DBG_CSR_INTR_EDGE_SEL4 (0x00B91810) +#define DBG_CSR_INTR_EDGE_SEL4___RWC QCSR_REG_RW +#define DBG_CSR_INTR_EDGE_SEL4___POR 0x00000000 +#define DBG_CSR_INTR_EDGE_SEL4__BIT79_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL4__BIT78_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL4__BIT77_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL4__BIT76_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL4__BIT75_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL4__BIT74_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL4__BIT73_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL4__BIT72_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL4__BIT71_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL4__BIT70_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL4__BIT69_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL4__BIT68_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL4__BIT67_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL4__BIT66_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL4__BIT65_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL4__BIT64_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL4__BIT79_EDGE_SEL___M 0xC0000000 +#define DBG_CSR_INTR_EDGE_SEL4__BIT79_EDGE_SEL___S 30 +#define DBG_CSR_INTR_EDGE_SEL4__BIT79_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL4__BIT79_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL4__BIT79_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL4__BIT78_EDGE_SEL___M 0x30000000 +#define DBG_CSR_INTR_EDGE_SEL4__BIT78_EDGE_SEL___S 28 +#define DBG_CSR_INTR_EDGE_SEL4__BIT78_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL4__BIT78_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL4__BIT78_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL4__BIT77_EDGE_SEL___M 0x0C000000 +#define DBG_CSR_INTR_EDGE_SEL4__BIT77_EDGE_SEL___S 26 +#define DBG_CSR_INTR_EDGE_SEL4__BIT77_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL4__BIT77_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL4__BIT77_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL4__BIT76_EDGE_SEL___M 0x03000000 +#define DBG_CSR_INTR_EDGE_SEL4__BIT76_EDGE_SEL___S 24 +#define DBG_CSR_INTR_EDGE_SEL4__BIT76_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL4__BIT76_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL4__BIT76_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL4__BIT75_EDGE_SEL___M 0x00C00000 +#define DBG_CSR_INTR_EDGE_SEL4__BIT75_EDGE_SEL___S 22 +#define DBG_CSR_INTR_EDGE_SEL4__BIT75_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL4__BIT75_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL4__BIT75_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL4__BIT74_EDGE_SEL___M 0x00300000 +#define DBG_CSR_INTR_EDGE_SEL4__BIT74_EDGE_SEL___S 20 +#define DBG_CSR_INTR_EDGE_SEL4__BIT74_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL4__BIT74_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL4__BIT74_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL4__BIT73_EDGE_SEL___M 0x000C0000 +#define DBG_CSR_INTR_EDGE_SEL4__BIT73_EDGE_SEL___S 18 +#define DBG_CSR_INTR_EDGE_SEL4__BIT73_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL4__BIT73_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL4__BIT73_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL4__BIT72_EDGE_SEL___M 0x00030000 +#define DBG_CSR_INTR_EDGE_SEL4__BIT72_EDGE_SEL___S 16 +#define DBG_CSR_INTR_EDGE_SEL4__BIT72_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL4__BIT72_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL4__BIT72_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL4__BIT71_EDGE_SEL___M 0x0000C000 +#define DBG_CSR_INTR_EDGE_SEL4__BIT71_EDGE_SEL___S 14 +#define DBG_CSR_INTR_EDGE_SEL4__BIT71_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL4__BIT71_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL4__BIT71_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL4__BIT70_EDGE_SEL___M 0x00003000 +#define DBG_CSR_INTR_EDGE_SEL4__BIT70_EDGE_SEL___S 12 +#define DBG_CSR_INTR_EDGE_SEL4__BIT70_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL4__BIT70_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL4__BIT70_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL4__BIT69_EDGE_SEL___M 0x00000C00 +#define DBG_CSR_INTR_EDGE_SEL4__BIT69_EDGE_SEL___S 10 +#define DBG_CSR_INTR_EDGE_SEL4__BIT69_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL4__BIT69_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL4__BIT69_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL4__BIT68_EDGE_SEL___M 0x00000300 +#define DBG_CSR_INTR_EDGE_SEL4__BIT68_EDGE_SEL___S 8 +#define DBG_CSR_INTR_EDGE_SEL4__BIT68_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL4__BIT68_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL4__BIT68_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL4__BIT67_EDGE_SEL___M 0x000000C0 +#define DBG_CSR_INTR_EDGE_SEL4__BIT67_EDGE_SEL___S 6 +#define DBG_CSR_INTR_EDGE_SEL4__BIT67_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL4__BIT67_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL4__BIT67_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL4__BIT66_EDGE_SEL___M 0x00000030 +#define DBG_CSR_INTR_EDGE_SEL4__BIT66_EDGE_SEL___S 4 +#define DBG_CSR_INTR_EDGE_SEL4__BIT66_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL4__BIT66_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL4__BIT66_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL4__BIT65_EDGE_SEL___M 0x0000000C +#define DBG_CSR_INTR_EDGE_SEL4__BIT65_EDGE_SEL___S 2 +#define DBG_CSR_INTR_EDGE_SEL4__BIT65_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL4__BIT65_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL4__BIT65_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL4__BIT64_EDGE_SEL___M 0x00000003 +#define DBG_CSR_INTR_EDGE_SEL4__BIT64_EDGE_SEL___S 0 +#define DBG_CSR_INTR_EDGE_SEL4__BIT64_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL4__BIT64_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL4__BIT64_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL4___M 0xFFFFFFFF +#define DBG_CSR_INTR_EDGE_SEL4___S 0 + +#define DBG_CSR_INTR_EDGE_SEL5 (0x00B91814) +#define DBG_CSR_INTR_EDGE_SEL5___RWC QCSR_REG_RW +#define DBG_CSR_INTR_EDGE_SEL5___POR 0x00000000 +#define DBG_CSR_INTR_EDGE_SEL5__BIT95_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL5__BIT94_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL5__BIT93_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL5__BIT92_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL5__BIT91_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL5__BIT90_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL5__BIT89_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL5__BIT88_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL5__BIT87_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL5__BIT86_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL5__BIT85_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL5__BIT84_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL5__BIT83_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL5__BIT82_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL5__BIT81_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL5__BIT80_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL5__BIT95_EDGE_SEL___M 0xC0000000 +#define DBG_CSR_INTR_EDGE_SEL5__BIT95_EDGE_SEL___S 30 +#define DBG_CSR_INTR_EDGE_SEL5__BIT95_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL5__BIT95_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL5__BIT95_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL5__BIT94_EDGE_SEL___M 0x30000000 +#define DBG_CSR_INTR_EDGE_SEL5__BIT94_EDGE_SEL___S 28 +#define DBG_CSR_INTR_EDGE_SEL5__BIT94_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL5__BIT94_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL5__BIT94_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL5__BIT93_EDGE_SEL___M 0x0C000000 +#define DBG_CSR_INTR_EDGE_SEL5__BIT93_EDGE_SEL___S 26 +#define DBG_CSR_INTR_EDGE_SEL5__BIT93_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL5__BIT93_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL5__BIT93_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL5__BIT92_EDGE_SEL___M 0x03000000 +#define DBG_CSR_INTR_EDGE_SEL5__BIT92_EDGE_SEL___S 24 +#define DBG_CSR_INTR_EDGE_SEL5__BIT92_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL5__BIT92_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL5__BIT92_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL5__BIT91_EDGE_SEL___M 0x00C00000 +#define DBG_CSR_INTR_EDGE_SEL5__BIT91_EDGE_SEL___S 22 +#define DBG_CSR_INTR_EDGE_SEL5__BIT91_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL5__BIT91_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL5__BIT91_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL5__BIT90_EDGE_SEL___M 0x00300000 +#define DBG_CSR_INTR_EDGE_SEL5__BIT90_EDGE_SEL___S 20 +#define DBG_CSR_INTR_EDGE_SEL5__BIT90_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL5__BIT90_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL5__BIT90_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL5__BIT89_EDGE_SEL___M 0x000C0000 +#define DBG_CSR_INTR_EDGE_SEL5__BIT89_EDGE_SEL___S 18 +#define DBG_CSR_INTR_EDGE_SEL5__BIT89_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL5__BIT89_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL5__BIT89_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL5__BIT88_EDGE_SEL___M 0x00030000 +#define DBG_CSR_INTR_EDGE_SEL5__BIT88_EDGE_SEL___S 16 +#define DBG_CSR_INTR_EDGE_SEL5__BIT88_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL5__BIT88_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL5__BIT88_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL5__BIT87_EDGE_SEL___M 0x0000C000 +#define DBG_CSR_INTR_EDGE_SEL5__BIT87_EDGE_SEL___S 14 +#define DBG_CSR_INTR_EDGE_SEL5__BIT87_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL5__BIT87_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL5__BIT87_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL5__BIT86_EDGE_SEL___M 0x00003000 +#define DBG_CSR_INTR_EDGE_SEL5__BIT86_EDGE_SEL___S 12 +#define DBG_CSR_INTR_EDGE_SEL5__BIT86_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL5__BIT86_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL5__BIT86_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL5__BIT85_EDGE_SEL___M 0x00000C00 +#define DBG_CSR_INTR_EDGE_SEL5__BIT85_EDGE_SEL___S 10 +#define DBG_CSR_INTR_EDGE_SEL5__BIT85_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL5__BIT85_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL5__BIT85_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL5__BIT84_EDGE_SEL___M 0x00000300 +#define DBG_CSR_INTR_EDGE_SEL5__BIT84_EDGE_SEL___S 8 +#define DBG_CSR_INTR_EDGE_SEL5__BIT84_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL5__BIT84_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL5__BIT84_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL5__BIT83_EDGE_SEL___M 0x000000C0 +#define DBG_CSR_INTR_EDGE_SEL5__BIT83_EDGE_SEL___S 6 +#define DBG_CSR_INTR_EDGE_SEL5__BIT83_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL5__BIT83_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL5__BIT83_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL5__BIT82_EDGE_SEL___M 0x00000030 +#define DBG_CSR_INTR_EDGE_SEL5__BIT82_EDGE_SEL___S 4 +#define DBG_CSR_INTR_EDGE_SEL5__BIT82_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL5__BIT82_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL5__BIT82_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL5__BIT81_EDGE_SEL___M 0x0000000C +#define DBG_CSR_INTR_EDGE_SEL5__BIT81_EDGE_SEL___S 2 +#define DBG_CSR_INTR_EDGE_SEL5__BIT81_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL5__BIT81_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL5__BIT81_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL5__BIT80_EDGE_SEL___M 0x00000003 +#define DBG_CSR_INTR_EDGE_SEL5__BIT80_EDGE_SEL___S 0 +#define DBG_CSR_INTR_EDGE_SEL5__BIT80_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL5__BIT80_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL5__BIT80_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL5___M 0xFFFFFFFF +#define DBG_CSR_INTR_EDGE_SEL5___S 0 + +#define DBG_CSR_INTR_EDGE_SEL6 (0x00B91818) +#define DBG_CSR_INTR_EDGE_SEL6___RWC QCSR_REG_RW +#define DBG_CSR_INTR_EDGE_SEL6___POR 0x00000000 +#define DBG_CSR_INTR_EDGE_SEL6__BIT111_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL6__BIT110_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL6__BIT109_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL6__BIT108_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL6__BIT107_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL6__BIT106_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL6__BIT105_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL6__BIT104_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL6__BIT103_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL6__BIT102_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL6__BIT101_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL6__BIT100_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL6__BIT99_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL6__BIT98_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL6__BIT97_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL6__BIT96_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL6__BIT111_EDGE_SEL___M 0xC0000000 +#define DBG_CSR_INTR_EDGE_SEL6__BIT111_EDGE_SEL___S 30 +#define DBG_CSR_INTR_EDGE_SEL6__BIT111_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL6__BIT111_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL6__BIT111_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL6__BIT110_EDGE_SEL___M 0x30000000 +#define DBG_CSR_INTR_EDGE_SEL6__BIT110_EDGE_SEL___S 28 +#define DBG_CSR_INTR_EDGE_SEL6__BIT110_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL6__BIT110_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL6__BIT110_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL6__BIT109_EDGE_SEL___M 0x0C000000 +#define DBG_CSR_INTR_EDGE_SEL6__BIT109_EDGE_SEL___S 26 +#define DBG_CSR_INTR_EDGE_SEL6__BIT109_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL6__BIT109_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL6__BIT109_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL6__BIT108_EDGE_SEL___M 0x03000000 +#define DBG_CSR_INTR_EDGE_SEL6__BIT108_EDGE_SEL___S 24 +#define DBG_CSR_INTR_EDGE_SEL6__BIT108_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL6__BIT108_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL6__BIT108_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL6__BIT107_EDGE_SEL___M 0x00C00000 +#define DBG_CSR_INTR_EDGE_SEL6__BIT107_EDGE_SEL___S 22 +#define DBG_CSR_INTR_EDGE_SEL6__BIT107_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL6__BIT107_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL6__BIT107_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL6__BIT106_EDGE_SEL___M 0x00300000 +#define DBG_CSR_INTR_EDGE_SEL6__BIT106_EDGE_SEL___S 20 +#define DBG_CSR_INTR_EDGE_SEL6__BIT106_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL6__BIT106_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL6__BIT106_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL6__BIT105_EDGE_SEL___M 0x000C0000 +#define DBG_CSR_INTR_EDGE_SEL6__BIT105_EDGE_SEL___S 18 +#define DBG_CSR_INTR_EDGE_SEL6__BIT105_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL6__BIT105_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL6__BIT105_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL6__BIT104_EDGE_SEL___M 0x00030000 +#define DBG_CSR_INTR_EDGE_SEL6__BIT104_EDGE_SEL___S 16 +#define DBG_CSR_INTR_EDGE_SEL6__BIT104_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL6__BIT104_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL6__BIT104_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL6__BIT103_EDGE_SEL___M 0x0000C000 +#define DBG_CSR_INTR_EDGE_SEL6__BIT103_EDGE_SEL___S 14 +#define DBG_CSR_INTR_EDGE_SEL6__BIT103_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL6__BIT103_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL6__BIT103_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL6__BIT102_EDGE_SEL___M 0x00003000 +#define DBG_CSR_INTR_EDGE_SEL6__BIT102_EDGE_SEL___S 12 +#define DBG_CSR_INTR_EDGE_SEL6__BIT102_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL6__BIT102_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL6__BIT102_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL6__BIT101_EDGE_SEL___M 0x00000C00 +#define DBG_CSR_INTR_EDGE_SEL6__BIT101_EDGE_SEL___S 10 +#define DBG_CSR_INTR_EDGE_SEL6__BIT101_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL6__BIT101_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL6__BIT101_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL6__BIT100_EDGE_SEL___M 0x00000300 +#define DBG_CSR_INTR_EDGE_SEL6__BIT100_EDGE_SEL___S 8 +#define DBG_CSR_INTR_EDGE_SEL6__BIT100_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL6__BIT100_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL6__BIT100_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL6__BIT99_EDGE_SEL___M 0x000000C0 +#define DBG_CSR_INTR_EDGE_SEL6__BIT99_EDGE_SEL___S 6 +#define DBG_CSR_INTR_EDGE_SEL6__BIT99_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL6__BIT99_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL6__BIT99_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL6__BIT98_EDGE_SEL___M 0x00000030 +#define DBG_CSR_INTR_EDGE_SEL6__BIT98_EDGE_SEL___S 4 +#define DBG_CSR_INTR_EDGE_SEL6__BIT98_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL6__BIT98_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL6__BIT98_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL6__BIT97_EDGE_SEL___M 0x0000000C +#define DBG_CSR_INTR_EDGE_SEL6__BIT97_EDGE_SEL___S 2 +#define DBG_CSR_INTR_EDGE_SEL6__BIT97_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL6__BIT97_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL6__BIT97_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL6__BIT96_EDGE_SEL___M 0x00000003 +#define DBG_CSR_INTR_EDGE_SEL6__BIT96_EDGE_SEL___S 0 +#define DBG_CSR_INTR_EDGE_SEL6__BIT96_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL6__BIT96_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL6__BIT96_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL6___M 0xFFFFFFFF +#define DBG_CSR_INTR_EDGE_SEL6___S 0 + +#define DBG_CSR_INTR_EDGE_SEL7 (0x00B9181C) +#define DBG_CSR_INTR_EDGE_SEL7___RWC QCSR_REG_RW +#define DBG_CSR_INTR_EDGE_SEL7___POR 0x00000000 +#define DBG_CSR_INTR_EDGE_SEL7__BIT127_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL7__BIT126_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL7__BIT125_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL7__BIT124_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL7__BIT123_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL7__BIT122_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL7__BIT121_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL7__BIT120_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL7__BIT119_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL7__BIT118_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL7__BIT117_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL7__BIT116_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL7__BIT115_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL7__BIT114_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL7__BIT113_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL7__BIT112_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL7__BIT127_EDGE_SEL___M 0xC0000000 +#define DBG_CSR_INTR_EDGE_SEL7__BIT127_EDGE_SEL___S 30 +#define DBG_CSR_INTR_EDGE_SEL7__BIT127_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL7__BIT127_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL7__BIT127_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL7__BIT126_EDGE_SEL___M 0x30000000 +#define DBG_CSR_INTR_EDGE_SEL7__BIT126_EDGE_SEL___S 28 +#define DBG_CSR_INTR_EDGE_SEL7__BIT126_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL7__BIT126_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL7__BIT126_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL7__BIT125_EDGE_SEL___M 0x0C000000 +#define DBG_CSR_INTR_EDGE_SEL7__BIT125_EDGE_SEL___S 26 +#define DBG_CSR_INTR_EDGE_SEL7__BIT125_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL7__BIT125_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL7__BIT125_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL7__BIT124_EDGE_SEL___M 0x03000000 +#define DBG_CSR_INTR_EDGE_SEL7__BIT124_EDGE_SEL___S 24 +#define DBG_CSR_INTR_EDGE_SEL7__BIT124_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL7__BIT124_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL7__BIT124_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL7__BIT123_EDGE_SEL___M 0x00C00000 +#define DBG_CSR_INTR_EDGE_SEL7__BIT123_EDGE_SEL___S 22 +#define DBG_CSR_INTR_EDGE_SEL7__BIT123_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL7__BIT123_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL7__BIT123_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL7__BIT122_EDGE_SEL___M 0x00300000 +#define DBG_CSR_INTR_EDGE_SEL7__BIT122_EDGE_SEL___S 20 +#define DBG_CSR_INTR_EDGE_SEL7__BIT122_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL7__BIT122_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL7__BIT122_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL7__BIT121_EDGE_SEL___M 0x000C0000 +#define DBG_CSR_INTR_EDGE_SEL7__BIT121_EDGE_SEL___S 18 +#define DBG_CSR_INTR_EDGE_SEL7__BIT121_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL7__BIT121_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL7__BIT121_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL7__BIT120_EDGE_SEL___M 0x00030000 +#define DBG_CSR_INTR_EDGE_SEL7__BIT120_EDGE_SEL___S 16 +#define DBG_CSR_INTR_EDGE_SEL7__BIT120_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL7__BIT120_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL7__BIT120_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL7__BIT119_EDGE_SEL___M 0x0000C000 +#define DBG_CSR_INTR_EDGE_SEL7__BIT119_EDGE_SEL___S 14 +#define DBG_CSR_INTR_EDGE_SEL7__BIT119_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL7__BIT119_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL7__BIT119_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL7__BIT118_EDGE_SEL___M 0x00003000 +#define DBG_CSR_INTR_EDGE_SEL7__BIT118_EDGE_SEL___S 12 +#define DBG_CSR_INTR_EDGE_SEL7__BIT118_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL7__BIT118_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL7__BIT118_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL7__BIT117_EDGE_SEL___M 0x00000C00 +#define DBG_CSR_INTR_EDGE_SEL7__BIT117_EDGE_SEL___S 10 +#define DBG_CSR_INTR_EDGE_SEL7__BIT117_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL7__BIT117_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL7__BIT117_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL7__BIT116_EDGE_SEL___M 0x00000300 +#define DBG_CSR_INTR_EDGE_SEL7__BIT116_EDGE_SEL___S 8 +#define DBG_CSR_INTR_EDGE_SEL7__BIT116_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL7__BIT116_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL7__BIT116_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL7__BIT115_EDGE_SEL___M 0x000000C0 +#define DBG_CSR_INTR_EDGE_SEL7__BIT115_EDGE_SEL___S 6 +#define DBG_CSR_INTR_EDGE_SEL7__BIT115_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL7__BIT115_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL7__BIT115_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL7__BIT114_EDGE_SEL___M 0x00000030 +#define DBG_CSR_INTR_EDGE_SEL7__BIT114_EDGE_SEL___S 4 +#define DBG_CSR_INTR_EDGE_SEL7__BIT114_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL7__BIT114_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL7__BIT114_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL7__BIT113_EDGE_SEL___M 0x0000000C +#define DBG_CSR_INTR_EDGE_SEL7__BIT113_EDGE_SEL___S 2 +#define DBG_CSR_INTR_EDGE_SEL7__BIT113_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL7__BIT113_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL7__BIT113_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL7__BIT112_EDGE_SEL___M 0x00000003 +#define DBG_CSR_INTR_EDGE_SEL7__BIT112_EDGE_SEL___S 0 +#define DBG_CSR_INTR_EDGE_SEL7__BIT112_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL7__BIT112_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL7__BIT112_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL7___M 0xFFFFFFFF +#define DBG_CSR_INTR_EDGE_SEL7___S 0 + +#define DBG_CSR_INTR_EDGE_SEL8 (0x00B91820) +#define DBG_CSR_INTR_EDGE_SEL8___RWC QCSR_REG_RW +#define DBG_CSR_INTR_EDGE_SEL8___POR 0x00000000 +#define DBG_CSR_INTR_EDGE_SEL8__BIT143_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL8__BIT142_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL8__BIT141_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL8__BIT140_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL8__BIT139_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL8__BIT138_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL8__BIT137_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL8__BIT136_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL8__BIT135_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL8__BIT134_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL8__BIT133_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL8__BIT132_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL8__BIT131_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL8__BIT130_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL8__BIT129_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL8__BIT128_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL8__BIT143_EDGE_SEL___M 0xC0000000 +#define DBG_CSR_INTR_EDGE_SEL8__BIT143_EDGE_SEL___S 30 +#define DBG_CSR_INTR_EDGE_SEL8__BIT143_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL8__BIT143_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL8__BIT143_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL8__BIT142_EDGE_SEL___M 0x30000000 +#define DBG_CSR_INTR_EDGE_SEL8__BIT142_EDGE_SEL___S 28 +#define DBG_CSR_INTR_EDGE_SEL8__BIT142_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL8__BIT142_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL8__BIT142_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL8__BIT141_EDGE_SEL___M 0x0C000000 +#define DBG_CSR_INTR_EDGE_SEL8__BIT141_EDGE_SEL___S 26 +#define DBG_CSR_INTR_EDGE_SEL8__BIT141_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL8__BIT141_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL8__BIT141_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL8__BIT140_EDGE_SEL___M 0x03000000 +#define DBG_CSR_INTR_EDGE_SEL8__BIT140_EDGE_SEL___S 24 +#define DBG_CSR_INTR_EDGE_SEL8__BIT140_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL8__BIT140_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL8__BIT140_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL8__BIT139_EDGE_SEL___M 0x00C00000 +#define DBG_CSR_INTR_EDGE_SEL8__BIT139_EDGE_SEL___S 22 +#define DBG_CSR_INTR_EDGE_SEL8__BIT139_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL8__BIT139_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL8__BIT139_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL8__BIT138_EDGE_SEL___M 0x00300000 +#define DBG_CSR_INTR_EDGE_SEL8__BIT138_EDGE_SEL___S 20 +#define DBG_CSR_INTR_EDGE_SEL8__BIT138_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL8__BIT138_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL8__BIT138_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL8__BIT137_EDGE_SEL___M 0x000C0000 +#define DBG_CSR_INTR_EDGE_SEL8__BIT137_EDGE_SEL___S 18 +#define DBG_CSR_INTR_EDGE_SEL8__BIT137_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL8__BIT137_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL8__BIT137_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL8__BIT136_EDGE_SEL___M 0x00030000 +#define DBG_CSR_INTR_EDGE_SEL8__BIT136_EDGE_SEL___S 16 +#define DBG_CSR_INTR_EDGE_SEL8__BIT136_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL8__BIT136_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL8__BIT136_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL8__BIT135_EDGE_SEL___M 0x0000C000 +#define DBG_CSR_INTR_EDGE_SEL8__BIT135_EDGE_SEL___S 14 +#define DBG_CSR_INTR_EDGE_SEL8__BIT135_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL8__BIT135_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL8__BIT135_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL8__BIT134_EDGE_SEL___M 0x00003000 +#define DBG_CSR_INTR_EDGE_SEL8__BIT134_EDGE_SEL___S 12 +#define DBG_CSR_INTR_EDGE_SEL8__BIT134_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL8__BIT134_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL8__BIT134_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL8__BIT133_EDGE_SEL___M 0x00000C00 +#define DBG_CSR_INTR_EDGE_SEL8__BIT133_EDGE_SEL___S 10 +#define DBG_CSR_INTR_EDGE_SEL8__BIT133_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL8__BIT133_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL8__BIT133_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL8__BIT132_EDGE_SEL___M 0x00000300 +#define DBG_CSR_INTR_EDGE_SEL8__BIT132_EDGE_SEL___S 8 +#define DBG_CSR_INTR_EDGE_SEL8__BIT132_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL8__BIT132_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL8__BIT132_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL8__BIT131_EDGE_SEL___M 0x000000C0 +#define DBG_CSR_INTR_EDGE_SEL8__BIT131_EDGE_SEL___S 6 +#define DBG_CSR_INTR_EDGE_SEL8__BIT131_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL8__BIT131_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL8__BIT131_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL8__BIT130_EDGE_SEL___M 0x00000030 +#define DBG_CSR_INTR_EDGE_SEL8__BIT130_EDGE_SEL___S 4 +#define DBG_CSR_INTR_EDGE_SEL8__BIT130_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL8__BIT130_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL8__BIT130_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL8__BIT129_EDGE_SEL___M 0x0000000C +#define DBG_CSR_INTR_EDGE_SEL8__BIT129_EDGE_SEL___S 2 +#define DBG_CSR_INTR_EDGE_SEL8__BIT129_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL8__BIT129_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL8__BIT129_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL8__BIT128_EDGE_SEL___M 0x00000003 +#define DBG_CSR_INTR_EDGE_SEL8__BIT128_EDGE_SEL___S 0 +#define DBG_CSR_INTR_EDGE_SEL8__BIT128_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL8__BIT128_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL8__BIT128_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL8___M 0xFFFFFFFF +#define DBG_CSR_INTR_EDGE_SEL8___S 0 + +#define DBG_CSR_INTR_EDGE_SEL9 (0x00B91824) +#define DBG_CSR_INTR_EDGE_SEL9___RWC QCSR_REG_RW +#define DBG_CSR_INTR_EDGE_SEL9___POR 0x00000000 +#define DBG_CSR_INTR_EDGE_SEL9__BIT159_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL9__BIT158_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL9__BIT157_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL9__BIT156_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL9__BIT155_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL9__BIT154_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL9__BIT153_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL9__BIT152_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL9__BIT151_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL9__BIT150_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL9__BIT149_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL9__BIT148_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL9__BIT147_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL9__BIT146_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL9__BIT145_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL9__BIT144_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL9__BIT159_EDGE_SEL___M 0xC0000000 +#define DBG_CSR_INTR_EDGE_SEL9__BIT159_EDGE_SEL___S 30 +#define DBG_CSR_INTR_EDGE_SEL9__BIT159_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL9__BIT159_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL9__BIT159_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL9__BIT158_EDGE_SEL___M 0x30000000 +#define DBG_CSR_INTR_EDGE_SEL9__BIT158_EDGE_SEL___S 28 +#define DBG_CSR_INTR_EDGE_SEL9__BIT158_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL9__BIT158_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL9__BIT158_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL9__BIT157_EDGE_SEL___M 0x0C000000 +#define DBG_CSR_INTR_EDGE_SEL9__BIT157_EDGE_SEL___S 26 +#define DBG_CSR_INTR_EDGE_SEL9__BIT157_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL9__BIT157_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL9__BIT157_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL9__BIT156_EDGE_SEL___M 0x03000000 +#define DBG_CSR_INTR_EDGE_SEL9__BIT156_EDGE_SEL___S 24 +#define DBG_CSR_INTR_EDGE_SEL9__BIT156_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL9__BIT156_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL9__BIT156_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL9__BIT155_EDGE_SEL___M 0x00C00000 +#define DBG_CSR_INTR_EDGE_SEL9__BIT155_EDGE_SEL___S 22 +#define DBG_CSR_INTR_EDGE_SEL9__BIT155_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL9__BIT155_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL9__BIT155_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL9__BIT154_EDGE_SEL___M 0x00300000 +#define DBG_CSR_INTR_EDGE_SEL9__BIT154_EDGE_SEL___S 20 +#define DBG_CSR_INTR_EDGE_SEL9__BIT154_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL9__BIT154_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL9__BIT154_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL9__BIT153_EDGE_SEL___M 0x000C0000 +#define DBG_CSR_INTR_EDGE_SEL9__BIT153_EDGE_SEL___S 18 +#define DBG_CSR_INTR_EDGE_SEL9__BIT153_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL9__BIT153_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL9__BIT153_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL9__BIT152_EDGE_SEL___M 0x00030000 +#define DBG_CSR_INTR_EDGE_SEL9__BIT152_EDGE_SEL___S 16 +#define DBG_CSR_INTR_EDGE_SEL9__BIT152_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL9__BIT152_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL9__BIT152_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL9__BIT151_EDGE_SEL___M 0x0000C000 +#define DBG_CSR_INTR_EDGE_SEL9__BIT151_EDGE_SEL___S 14 +#define DBG_CSR_INTR_EDGE_SEL9__BIT151_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL9__BIT151_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL9__BIT151_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL9__BIT150_EDGE_SEL___M 0x00003000 +#define DBG_CSR_INTR_EDGE_SEL9__BIT150_EDGE_SEL___S 12 +#define DBG_CSR_INTR_EDGE_SEL9__BIT150_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL9__BIT150_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL9__BIT150_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL9__BIT149_EDGE_SEL___M 0x00000C00 +#define DBG_CSR_INTR_EDGE_SEL9__BIT149_EDGE_SEL___S 10 +#define DBG_CSR_INTR_EDGE_SEL9__BIT149_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL9__BIT149_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL9__BIT149_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL9__BIT148_EDGE_SEL___M 0x00000300 +#define DBG_CSR_INTR_EDGE_SEL9__BIT148_EDGE_SEL___S 8 +#define DBG_CSR_INTR_EDGE_SEL9__BIT148_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL9__BIT148_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL9__BIT148_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL9__BIT147_EDGE_SEL___M 0x000000C0 +#define DBG_CSR_INTR_EDGE_SEL9__BIT147_EDGE_SEL___S 6 +#define DBG_CSR_INTR_EDGE_SEL9__BIT147_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL9__BIT147_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL9__BIT147_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL9__BIT146_EDGE_SEL___M 0x00000030 +#define DBG_CSR_INTR_EDGE_SEL9__BIT146_EDGE_SEL___S 4 +#define DBG_CSR_INTR_EDGE_SEL9__BIT146_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL9__BIT146_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL9__BIT146_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL9__BIT145_EDGE_SEL___M 0x0000000C +#define DBG_CSR_INTR_EDGE_SEL9__BIT145_EDGE_SEL___S 2 +#define DBG_CSR_INTR_EDGE_SEL9__BIT145_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL9__BIT145_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL9__BIT145_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL9__BIT144_EDGE_SEL___M 0x00000003 +#define DBG_CSR_INTR_EDGE_SEL9__BIT144_EDGE_SEL___S 0 +#define DBG_CSR_INTR_EDGE_SEL9__BIT144_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL9__BIT144_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL9__BIT144_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL9___M 0xFFFFFFFF +#define DBG_CSR_INTR_EDGE_SEL9___S 0 + +#define DBG_CSR_INTR_EDGE_SEL10 (0x00B91828) +#define DBG_CSR_INTR_EDGE_SEL10___RWC QCSR_REG_RW +#define DBG_CSR_INTR_EDGE_SEL10___POR 0x00000000 +#define DBG_CSR_INTR_EDGE_SEL10__BIT175_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL10__BIT174_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL10__BIT173_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL10__BIT172_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL10__BIT171_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL10__BIT170_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL10__BIT169_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL10__BIT168_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL10__BIT167_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL10__BIT166_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL10__BIT165_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL10__BIT164_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL10__BIT163_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL10__BIT162_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL10__BIT161_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL10__BIT160_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL10__BIT175_EDGE_SEL___M 0xC0000000 +#define DBG_CSR_INTR_EDGE_SEL10__BIT175_EDGE_SEL___S 30 +#define DBG_CSR_INTR_EDGE_SEL10__BIT175_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL10__BIT175_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL10__BIT175_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL10__BIT174_EDGE_SEL___M 0x30000000 +#define DBG_CSR_INTR_EDGE_SEL10__BIT174_EDGE_SEL___S 28 +#define DBG_CSR_INTR_EDGE_SEL10__BIT174_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL10__BIT174_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL10__BIT174_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL10__BIT173_EDGE_SEL___M 0x0C000000 +#define DBG_CSR_INTR_EDGE_SEL10__BIT173_EDGE_SEL___S 26 +#define DBG_CSR_INTR_EDGE_SEL10__BIT173_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL10__BIT173_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL10__BIT173_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL10__BIT172_EDGE_SEL___M 0x03000000 +#define DBG_CSR_INTR_EDGE_SEL10__BIT172_EDGE_SEL___S 24 +#define DBG_CSR_INTR_EDGE_SEL10__BIT172_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL10__BIT172_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL10__BIT172_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL10__BIT171_EDGE_SEL___M 0x00C00000 +#define DBG_CSR_INTR_EDGE_SEL10__BIT171_EDGE_SEL___S 22 +#define DBG_CSR_INTR_EDGE_SEL10__BIT171_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL10__BIT171_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL10__BIT171_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL10__BIT170_EDGE_SEL___M 0x00300000 +#define DBG_CSR_INTR_EDGE_SEL10__BIT170_EDGE_SEL___S 20 +#define DBG_CSR_INTR_EDGE_SEL10__BIT170_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL10__BIT170_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL10__BIT170_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL10__BIT169_EDGE_SEL___M 0x000C0000 +#define DBG_CSR_INTR_EDGE_SEL10__BIT169_EDGE_SEL___S 18 +#define DBG_CSR_INTR_EDGE_SEL10__BIT169_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL10__BIT169_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL10__BIT169_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL10__BIT168_EDGE_SEL___M 0x00030000 +#define DBG_CSR_INTR_EDGE_SEL10__BIT168_EDGE_SEL___S 16 +#define DBG_CSR_INTR_EDGE_SEL10__BIT168_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL10__BIT168_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL10__BIT168_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL10__BIT167_EDGE_SEL___M 0x0000C000 +#define DBG_CSR_INTR_EDGE_SEL10__BIT167_EDGE_SEL___S 14 +#define DBG_CSR_INTR_EDGE_SEL10__BIT167_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL10__BIT167_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL10__BIT167_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL10__BIT166_EDGE_SEL___M 0x00003000 +#define DBG_CSR_INTR_EDGE_SEL10__BIT166_EDGE_SEL___S 12 +#define DBG_CSR_INTR_EDGE_SEL10__BIT166_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL10__BIT166_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL10__BIT166_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL10__BIT165_EDGE_SEL___M 0x00000C00 +#define DBG_CSR_INTR_EDGE_SEL10__BIT165_EDGE_SEL___S 10 +#define DBG_CSR_INTR_EDGE_SEL10__BIT165_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL10__BIT165_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL10__BIT165_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL10__BIT164_EDGE_SEL___M 0x00000300 +#define DBG_CSR_INTR_EDGE_SEL10__BIT164_EDGE_SEL___S 8 +#define DBG_CSR_INTR_EDGE_SEL10__BIT164_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL10__BIT164_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL10__BIT164_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL10__BIT163_EDGE_SEL___M 0x000000C0 +#define DBG_CSR_INTR_EDGE_SEL10__BIT163_EDGE_SEL___S 6 +#define DBG_CSR_INTR_EDGE_SEL10__BIT163_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL10__BIT163_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL10__BIT163_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL10__BIT162_EDGE_SEL___M 0x00000030 +#define DBG_CSR_INTR_EDGE_SEL10__BIT162_EDGE_SEL___S 4 +#define DBG_CSR_INTR_EDGE_SEL10__BIT162_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL10__BIT162_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL10__BIT162_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL10__BIT161_EDGE_SEL___M 0x0000000C +#define DBG_CSR_INTR_EDGE_SEL10__BIT161_EDGE_SEL___S 2 +#define DBG_CSR_INTR_EDGE_SEL10__BIT161_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL10__BIT161_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL10__BIT161_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL10__BIT160_EDGE_SEL___M 0x00000003 +#define DBG_CSR_INTR_EDGE_SEL10__BIT160_EDGE_SEL___S 0 +#define DBG_CSR_INTR_EDGE_SEL10__BIT160_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL10__BIT160_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL10__BIT160_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL10___M 0xFFFFFFFF +#define DBG_CSR_INTR_EDGE_SEL10___S 0 + +#define DBG_CSR_INTR_EDGE_SEL11 (0x00B9182C) +#define DBG_CSR_INTR_EDGE_SEL11___RWC QCSR_REG_RW +#define DBG_CSR_INTR_EDGE_SEL11___POR 0x00000000 +#define DBG_CSR_INTR_EDGE_SEL11__BIT191_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL11__BIT190_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL11__BIT189_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL11__BIT188_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL11__BIT187_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL11__BIT186_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL11__BIT185_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL11__BIT184_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL11__BIT183_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL11__BIT182_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL11__BIT181_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL11__BIT180_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL11__BIT179_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL11__BIT178_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL11__BIT177_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL11__BIT176_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL11__BIT191_EDGE_SEL___M 0xC0000000 +#define DBG_CSR_INTR_EDGE_SEL11__BIT191_EDGE_SEL___S 30 +#define DBG_CSR_INTR_EDGE_SEL11__BIT191_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL11__BIT191_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL11__BIT191_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL11__BIT190_EDGE_SEL___M 0x30000000 +#define DBG_CSR_INTR_EDGE_SEL11__BIT190_EDGE_SEL___S 28 +#define DBG_CSR_INTR_EDGE_SEL11__BIT190_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL11__BIT190_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL11__BIT190_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL11__BIT189_EDGE_SEL___M 0x0C000000 +#define DBG_CSR_INTR_EDGE_SEL11__BIT189_EDGE_SEL___S 26 +#define DBG_CSR_INTR_EDGE_SEL11__BIT189_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL11__BIT189_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL11__BIT189_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL11__BIT188_EDGE_SEL___M 0x03000000 +#define DBG_CSR_INTR_EDGE_SEL11__BIT188_EDGE_SEL___S 24 +#define DBG_CSR_INTR_EDGE_SEL11__BIT188_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL11__BIT188_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL11__BIT188_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL11__BIT187_EDGE_SEL___M 0x00C00000 +#define DBG_CSR_INTR_EDGE_SEL11__BIT187_EDGE_SEL___S 22 +#define DBG_CSR_INTR_EDGE_SEL11__BIT187_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL11__BIT187_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL11__BIT187_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL11__BIT186_EDGE_SEL___M 0x00300000 +#define DBG_CSR_INTR_EDGE_SEL11__BIT186_EDGE_SEL___S 20 +#define DBG_CSR_INTR_EDGE_SEL11__BIT186_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL11__BIT186_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL11__BIT186_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL11__BIT185_EDGE_SEL___M 0x000C0000 +#define DBG_CSR_INTR_EDGE_SEL11__BIT185_EDGE_SEL___S 18 +#define DBG_CSR_INTR_EDGE_SEL11__BIT185_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL11__BIT185_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL11__BIT185_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL11__BIT184_EDGE_SEL___M 0x00030000 +#define DBG_CSR_INTR_EDGE_SEL11__BIT184_EDGE_SEL___S 16 +#define DBG_CSR_INTR_EDGE_SEL11__BIT184_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL11__BIT184_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL11__BIT184_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL11__BIT183_EDGE_SEL___M 0x0000C000 +#define DBG_CSR_INTR_EDGE_SEL11__BIT183_EDGE_SEL___S 14 +#define DBG_CSR_INTR_EDGE_SEL11__BIT183_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL11__BIT183_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL11__BIT183_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL11__BIT182_EDGE_SEL___M 0x00003000 +#define DBG_CSR_INTR_EDGE_SEL11__BIT182_EDGE_SEL___S 12 +#define DBG_CSR_INTR_EDGE_SEL11__BIT182_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL11__BIT182_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL11__BIT182_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL11__BIT181_EDGE_SEL___M 0x00000C00 +#define DBG_CSR_INTR_EDGE_SEL11__BIT181_EDGE_SEL___S 10 +#define DBG_CSR_INTR_EDGE_SEL11__BIT181_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL11__BIT181_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL11__BIT181_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL11__BIT180_EDGE_SEL___M 0x00000300 +#define DBG_CSR_INTR_EDGE_SEL11__BIT180_EDGE_SEL___S 8 +#define DBG_CSR_INTR_EDGE_SEL11__BIT180_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL11__BIT180_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL11__BIT180_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL11__BIT179_EDGE_SEL___M 0x000000C0 +#define DBG_CSR_INTR_EDGE_SEL11__BIT179_EDGE_SEL___S 6 +#define DBG_CSR_INTR_EDGE_SEL11__BIT179_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL11__BIT179_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL11__BIT179_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL11__BIT178_EDGE_SEL___M 0x00000030 +#define DBG_CSR_INTR_EDGE_SEL11__BIT178_EDGE_SEL___S 4 +#define DBG_CSR_INTR_EDGE_SEL11__BIT178_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL11__BIT178_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL11__BIT178_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL11__BIT177_EDGE_SEL___M 0x0000000C +#define DBG_CSR_INTR_EDGE_SEL11__BIT177_EDGE_SEL___S 2 +#define DBG_CSR_INTR_EDGE_SEL11__BIT177_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL11__BIT177_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL11__BIT177_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL11__BIT176_EDGE_SEL___M 0x00000003 +#define DBG_CSR_INTR_EDGE_SEL11__BIT176_EDGE_SEL___S 0 +#define DBG_CSR_INTR_EDGE_SEL11__BIT176_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL11__BIT176_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL11__BIT176_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL11___M 0xFFFFFFFF +#define DBG_CSR_INTR_EDGE_SEL11___S 0 + +#define DBG_CSR_INTR_EDGE_SEL12 (0x00B91830) +#define DBG_CSR_INTR_EDGE_SEL12___RWC QCSR_REG_RW +#define DBG_CSR_INTR_EDGE_SEL12___POR 0x00000000 +#define DBG_CSR_INTR_EDGE_SEL12__BIT207_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL12__BIT206_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL12__BIT205_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL12__BIT204_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL12__BIT203_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL12__BIT202_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL12__BIT201_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL12__BIT200_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL12__BIT199_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL12__BIT198_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL12__BIT197_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL12__BIT196_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL12__BIT195_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL12__BIT194_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL12__BIT193_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL12__BIT192_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL12__BIT207_EDGE_SEL___M 0xC0000000 +#define DBG_CSR_INTR_EDGE_SEL12__BIT207_EDGE_SEL___S 30 +#define DBG_CSR_INTR_EDGE_SEL12__BIT207_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL12__BIT207_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL12__BIT207_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL12__BIT206_EDGE_SEL___M 0x30000000 +#define DBG_CSR_INTR_EDGE_SEL12__BIT206_EDGE_SEL___S 28 +#define DBG_CSR_INTR_EDGE_SEL12__BIT206_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL12__BIT206_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL12__BIT206_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL12__BIT205_EDGE_SEL___M 0x0C000000 +#define DBG_CSR_INTR_EDGE_SEL12__BIT205_EDGE_SEL___S 26 +#define DBG_CSR_INTR_EDGE_SEL12__BIT205_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL12__BIT205_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL12__BIT205_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL12__BIT204_EDGE_SEL___M 0x03000000 +#define DBG_CSR_INTR_EDGE_SEL12__BIT204_EDGE_SEL___S 24 +#define DBG_CSR_INTR_EDGE_SEL12__BIT204_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL12__BIT204_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL12__BIT204_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL12__BIT203_EDGE_SEL___M 0x00C00000 +#define DBG_CSR_INTR_EDGE_SEL12__BIT203_EDGE_SEL___S 22 +#define DBG_CSR_INTR_EDGE_SEL12__BIT203_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL12__BIT203_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL12__BIT203_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL12__BIT202_EDGE_SEL___M 0x00300000 +#define DBG_CSR_INTR_EDGE_SEL12__BIT202_EDGE_SEL___S 20 +#define DBG_CSR_INTR_EDGE_SEL12__BIT202_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL12__BIT202_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL12__BIT202_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL12__BIT201_EDGE_SEL___M 0x000C0000 +#define DBG_CSR_INTR_EDGE_SEL12__BIT201_EDGE_SEL___S 18 +#define DBG_CSR_INTR_EDGE_SEL12__BIT201_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL12__BIT201_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL12__BIT201_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL12__BIT200_EDGE_SEL___M 0x00030000 +#define DBG_CSR_INTR_EDGE_SEL12__BIT200_EDGE_SEL___S 16 +#define DBG_CSR_INTR_EDGE_SEL12__BIT200_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL12__BIT200_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL12__BIT200_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL12__BIT199_EDGE_SEL___M 0x0000C000 +#define DBG_CSR_INTR_EDGE_SEL12__BIT199_EDGE_SEL___S 14 +#define DBG_CSR_INTR_EDGE_SEL12__BIT199_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL12__BIT199_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL12__BIT199_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL12__BIT198_EDGE_SEL___M 0x00003000 +#define DBG_CSR_INTR_EDGE_SEL12__BIT198_EDGE_SEL___S 12 +#define DBG_CSR_INTR_EDGE_SEL12__BIT198_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL12__BIT198_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL12__BIT198_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL12__BIT197_EDGE_SEL___M 0x00000C00 +#define DBG_CSR_INTR_EDGE_SEL12__BIT197_EDGE_SEL___S 10 +#define DBG_CSR_INTR_EDGE_SEL12__BIT197_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL12__BIT197_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL12__BIT197_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL12__BIT196_EDGE_SEL___M 0x00000300 +#define DBG_CSR_INTR_EDGE_SEL12__BIT196_EDGE_SEL___S 8 +#define DBG_CSR_INTR_EDGE_SEL12__BIT196_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL12__BIT196_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL12__BIT196_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL12__BIT195_EDGE_SEL___M 0x000000C0 +#define DBG_CSR_INTR_EDGE_SEL12__BIT195_EDGE_SEL___S 6 +#define DBG_CSR_INTR_EDGE_SEL12__BIT195_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL12__BIT195_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL12__BIT195_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL12__BIT194_EDGE_SEL___M 0x00000030 +#define DBG_CSR_INTR_EDGE_SEL12__BIT194_EDGE_SEL___S 4 +#define DBG_CSR_INTR_EDGE_SEL12__BIT194_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL12__BIT194_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL12__BIT194_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL12__BIT193_EDGE_SEL___M 0x0000000C +#define DBG_CSR_INTR_EDGE_SEL12__BIT193_EDGE_SEL___S 2 +#define DBG_CSR_INTR_EDGE_SEL12__BIT193_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL12__BIT193_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL12__BIT193_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL12__BIT192_EDGE_SEL___M 0x00000003 +#define DBG_CSR_INTR_EDGE_SEL12__BIT192_EDGE_SEL___S 0 +#define DBG_CSR_INTR_EDGE_SEL12__BIT192_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL12__BIT192_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL12__BIT192_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL12___M 0xFFFFFFFF +#define DBG_CSR_INTR_EDGE_SEL12___S 0 + +#define DBG_CSR_INTR_EDGE_SEL13 (0x00B91834) +#define DBG_CSR_INTR_EDGE_SEL13___RWC QCSR_REG_RW +#define DBG_CSR_INTR_EDGE_SEL13___POR 0x00000000 +#define DBG_CSR_INTR_EDGE_SEL13__BIT223_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL13__BIT222_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL13__BIT221_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL13__BIT220_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL13__BIT219_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL13__BIT218_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL13__BIT217_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL13__BIT216_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL13__BIT215_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL13__BIT214_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL13__BIT213_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL13__BIT212_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL13__BIT211_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL13__BIT210_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL13__BIT209_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL13__BIT208_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL13__BIT223_EDGE_SEL___M 0xC0000000 +#define DBG_CSR_INTR_EDGE_SEL13__BIT223_EDGE_SEL___S 30 +#define DBG_CSR_INTR_EDGE_SEL13__BIT223_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL13__BIT223_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL13__BIT223_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL13__BIT222_EDGE_SEL___M 0x30000000 +#define DBG_CSR_INTR_EDGE_SEL13__BIT222_EDGE_SEL___S 28 +#define DBG_CSR_INTR_EDGE_SEL13__BIT222_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL13__BIT222_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL13__BIT222_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL13__BIT221_EDGE_SEL___M 0x0C000000 +#define DBG_CSR_INTR_EDGE_SEL13__BIT221_EDGE_SEL___S 26 +#define DBG_CSR_INTR_EDGE_SEL13__BIT221_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL13__BIT221_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL13__BIT221_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL13__BIT220_EDGE_SEL___M 0x03000000 +#define DBG_CSR_INTR_EDGE_SEL13__BIT220_EDGE_SEL___S 24 +#define DBG_CSR_INTR_EDGE_SEL13__BIT220_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL13__BIT220_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL13__BIT220_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL13__BIT219_EDGE_SEL___M 0x00C00000 +#define DBG_CSR_INTR_EDGE_SEL13__BIT219_EDGE_SEL___S 22 +#define DBG_CSR_INTR_EDGE_SEL13__BIT219_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL13__BIT219_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL13__BIT219_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL13__BIT218_EDGE_SEL___M 0x00300000 +#define DBG_CSR_INTR_EDGE_SEL13__BIT218_EDGE_SEL___S 20 +#define DBG_CSR_INTR_EDGE_SEL13__BIT218_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL13__BIT218_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL13__BIT218_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL13__BIT217_EDGE_SEL___M 0x000C0000 +#define DBG_CSR_INTR_EDGE_SEL13__BIT217_EDGE_SEL___S 18 +#define DBG_CSR_INTR_EDGE_SEL13__BIT217_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL13__BIT217_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL13__BIT217_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL13__BIT216_EDGE_SEL___M 0x00030000 +#define DBG_CSR_INTR_EDGE_SEL13__BIT216_EDGE_SEL___S 16 +#define DBG_CSR_INTR_EDGE_SEL13__BIT216_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL13__BIT216_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL13__BIT216_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL13__BIT215_EDGE_SEL___M 0x0000C000 +#define DBG_CSR_INTR_EDGE_SEL13__BIT215_EDGE_SEL___S 14 +#define DBG_CSR_INTR_EDGE_SEL13__BIT215_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL13__BIT215_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL13__BIT215_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL13__BIT214_EDGE_SEL___M 0x00003000 +#define DBG_CSR_INTR_EDGE_SEL13__BIT214_EDGE_SEL___S 12 +#define DBG_CSR_INTR_EDGE_SEL13__BIT214_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL13__BIT214_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL13__BIT214_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL13__BIT213_EDGE_SEL___M 0x00000C00 +#define DBG_CSR_INTR_EDGE_SEL13__BIT213_EDGE_SEL___S 10 +#define DBG_CSR_INTR_EDGE_SEL13__BIT213_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL13__BIT213_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL13__BIT213_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL13__BIT212_EDGE_SEL___M 0x00000300 +#define DBG_CSR_INTR_EDGE_SEL13__BIT212_EDGE_SEL___S 8 +#define DBG_CSR_INTR_EDGE_SEL13__BIT212_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL13__BIT212_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL13__BIT212_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL13__BIT211_EDGE_SEL___M 0x000000C0 +#define DBG_CSR_INTR_EDGE_SEL13__BIT211_EDGE_SEL___S 6 +#define DBG_CSR_INTR_EDGE_SEL13__BIT211_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL13__BIT211_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL13__BIT211_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL13__BIT210_EDGE_SEL___M 0x00000030 +#define DBG_CSR_INTR_EDGE_SEL13__BIT210_EDGE_SEL___S 4 +#define DBG_CSR_INTR_EDGE_SEL13__BIT210_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL13__BIT210_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL13__BIT210_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL13__BIT209_EDGE_SEL___M 0x0000000C +#define DBG_CSR_INTR_EDGE_SEL13__BIT209_EDGE_SEL___S 2 +#define DBG_CSR_INTR_EDGE_SEL13__BIT209_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL13__BIT209_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL13__BIT209_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL13__BIT208_EDGE_SEL___M 0x00000003 +#define DBG_CSR_INTR_EDGE_SEL13__BIT208_EDGE_SEL___S 0 +#define DBG_CSR_INTR_EDGE_SEL13__BIT208_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL13__BIT208_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL13__BIT208_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL13___M 0xFFFFFFFF +#define DBG_CSR_INTR_EDGE_SEL13___S 0 + +#define DBG_CSR_INTR_EDGE_SEL14 (0x00B91838) +#define DBG_CSR_INTR_EDGE_SEL14___RWC QCSR_REG_RW +#define DBG_CSR_INTR_EDGE_SEL14___POR 0x00000000 +#define DBG_CSR_INTR_EDGE_SEL14__BIT239_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL14__BIT238_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL14__BIT237_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL14__BIT236_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL14__BIT235_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL14__BIT234_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL14__BIT233_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL14__BIT232_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL14__BIT231_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL14__BIT230_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL14__BIT229_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL14__BIT228_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL14__BIT227_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL14__BIT226_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL14__BIT225_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL14__BIT224_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL14__BIT239_EDGE_SEL___M 0xC0000000 +#define DBG_CSR_INTR_EDGE_SEL14__BIT239_EDGE_SEL___S 30 +#define DBG_CSR_INTR_EDGE_SEL14__BIT239_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL14__BIT239_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL14__BIT239_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL14__BIT238_EDGE_SEL___M 0x30000000 +#define DBG_CSR_INTR_EDGE_SEL14__BIT238_EDGE_SEL___S 28 +#define DBG_CSR_INTR_EDGE_SEL14__BIT238_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL14__BIT238_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL14__BIT238_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL14__BIT237_EDGE_SEL___M 0x0C000000 +#define DBG_CSR_INTR_EDGE_SEL14__BIT237_EDGE_SEL___S 26 +#define DBG_CSR_INTR_EDGE_SEL14__BIT237_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL14__BIT237_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL14__BIT237_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL14__BIT236_EDGE_SEL___M 0x03000000 +#define DBG_CSR_INTR_EDGE_SEL14__BIT236_EDGE_SEL___S 24 +#define DBG_CSR_INTR_EDGE_SEL14__BIT236_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL14__BIT236_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL14__BIT236_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL14__BIT235_EDGE_SEL___M 0x00C00000 +#define DBG_CSR_INTR_EDGE_SEL14__BIT235_EDGE_SEL___S 22 +#define DBG_CSR_INTR_EDGE_SEL14__BIT235_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL14__BIT235_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL14__BIT235_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL14__BIT234_EDGE_SEL___M 0x00300000 +#define DBG_CSR_INTR_EDGE_SEL14__BIT234_EDGE_SEL___S 20 +#define DBG_CSR_INTR_EDGE_SEL14__BIT234_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL14__BIT234_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL14__BIT234_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL14__BIT233_EDGE_SEL___M 0x000C0000 +#define DBG_CSR_INTR_EDGE_SEL14__BIT233_EDGE_SEL___S 18 +#define DBG_CSR_INTR_EDGE_SEL14__BIT233_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL14__BIT233_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL14__BIT233_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL14__BIT232_EDGE_SEL___M 0x00030000 +#define DBG_CSR_INTR_EDGE_SEL14__BIT232_EDGE_SEL___S 16 +#define DBG_CSR_INTR_EDGE_SEL14__BIT232_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL14__BIT232_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL14__BIT232_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL14__BIT231_EDGE_SEL___M 0x0000C000 +#define DBG_CSR_INTR_EDGE_SEL14__BIT231_EDGE_SEL___S 14 +#define DBG_CSR_INTR_EDGE_SEL14__BIT231_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL14__BIT231_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL14__BIT231_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL14__BIT230_EDGE_SEL___M 0x00003000 +#define DBG_CSR_INTR_EDGE_SEL14__BIT230_EDGE_SEL___S 12 +#define DBG_CSR_INTR_EDGE_SEL14__BIT230_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL14__BIT230_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL14__BIT230_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL14__BIT229_EDGE_SEL___M 0x00000C00 +#define DBG_CSR_INTR_EDGE_SEL14__BIT229_EDGE_SEL___S 10 +#define DBG_CSR_INTR_EDGE_SEL14__BIT229_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL14__BIT229_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL14__BIT229_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL14__BIT228_EDGE_SEL___M 0x00000300 +#define DBG_CSR_INTR_EDGE_SEL14__BIT228_EDGE_SEL___S 8 +#define DBG_CSR_INTR_EDGE_SEL14__BIT228_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL14__BIT228_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL14__BIT228_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL14__BIT227_EDGE_SEL___M 0x000000C0 +#define DBG_CSR_INTR_EDGE_SEL14__BIT227_EDGE_SEL___S 6 +#define DBG_CSR_INTR_EDGE_SEL14__BIT227_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL14__BIT227_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL14__BIT227_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL14__BIT226_EDGE_SEL___M 0x00000030 +#define DBG_CSR_INTR_EDGE_SEL14__BIT226_EDGE_SEL___S 4 +#define DBG_CSR_INTR_EDGE_SEL14__BIT226_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL14__BIT226_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL14__BIT226_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL14__BIT225_EDGE_SEL___M 0x0000000C +#define DBG_CSR_INTR_EDGE_SEL14__BIT225_EDGE_SEL___S 2 +#define DBG_CSR_INTR_EDGE_SEL14__BIT225_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL14__BIT225_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL14__BIT225_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL14__BIT224_EDGE_SEL___M 0x00000003 +#define DBG_CSR_INTR_EDGE_SEL14__BIT224_EDGE_SEL___S 0 +#define DBG_CSR_INTR_EDGE_SEL14__BIT224_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL14__BIT224_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL14__BIT224_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL14___M 0xFFFFFFFF +#define DBG_CSR_INTR_EDGE_SEL14___S 0 + +#define DBG_CSR_INTR_EDGE_SEL15 (0x00B9183C) +#define DBG_CSR_INTR_EDGE_SEL15___RWC QCSR_REG_RW +#define DBG_CSR_INTR_EDGE_SEL15___POR 0x00000000 +#define DBG_CSR_INTR_EDGE_SEL15__BIT255_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL15__BIT254_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL15__BIT253_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL15__BIT252_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL15__BIT251_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL15__BIT250_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL15__BIT249_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL15__BIT248_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL15__BIT247_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL15__BIT246_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL15__BIT245_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL15__BIT244_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL15__BIT243_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL15__BIT242_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL15__BIT241_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL15__BIT240_EDGE_SEL___POR 0x0 +#define DBG_CSR_INTR_EDGE_SEL15__BIT255_EDGE_SEL___M 0xC0000000 +#define DBG_CSR_INTR_EDGE_SEL15__BIT255_EDGE_SEL___S 30 +#define DBG_CSR_INTR_EDGE_SEL15__BIT255_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL15__BIT255_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL15__BIT255_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL15__BIT254_EDGE_SEL___M 0x30000000 +#define DBG_CSR_INTR_EDGE_SEL15__BIT254_EDGE_SEL___S 28 +#define DBG_CSR_INTR_EDGE_SEL15__BIT254_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL15__BIT254_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL15__BIT254_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL15__BIT253_EDGE_SEL___M 0x0C000000 +#define DBG_CSR_INTR_EDGE_SEL15__BIT253_EDGE_SEL___S 26 +#define DBG_CSR_INTR_EDGE_SEL15__BIT253_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL15__BIT253_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL15__BIT253_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL15__BIT252_EDGE_SEL___M 0x03000000 +#define DBG_CSR_INTR_EDGE_SEL15__BIT252_EDGE_SEL___S 24 +#define DBG_CSR_INTR_EDGE_SEL15__BIT252_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL15__BIT252_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL15__BIT252_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL15__BIT251_EDGE_SEL___M 0x00C00000 +#define DBG_CSR_INTR_EDGE_SEL15__BIT251_EDGE_SEL___S 22 +#define DBG_CSR_INTR_EDGE_SEL15__BIT251_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL15__BIT251_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL15__BIT251_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL15__BIT250_EDGE_SEL___M 0x00300000 +#define DBG_CSR_INTR_EDGE_SEL15__BIT250_EDGE_SEL___S 20 +#define DBG_CSR_INTR_EDGE_SEL15__BIT250_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL15__BIT250_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL15__BIT250_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL15__BIT249_EDGE_SEL___M 0x000C0000 +#define DBG_CSR_INTR_EDGE_SEL15__BIT249_EDGE_SEL___S 18 +#define DBG_CSR_INTR_EDGE_SEL15__BIT249_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL15__BIT249_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL15__BIT249_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL15__BIT248_EDGE_SEL___M 0x00030000 +#define DBG_CSR_INTR_EDGE_SEL15__BIT248_EDGE_SEL___S 16 +#define DBG_CSR_INTR_EDGE_SEL15__BIT248_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL15__BIT248_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL15__BIT248_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL15__BIT247_EDGE_SEL___M 0x0000C000 +#define DBG_CSR_INTR_EDGE_SEL15__BIT247_EDGE_SEL___S 14 +#define DBG_CSR_INTR_EDGE_SEL15__BIT247_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL15__BIT247_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL15__BIT247_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL15__BIT246_EDGE_SEL___M 0x00003000 +#define DBG_CSR_INTR_EDGE_SEL15__BIT246_EDGE_SEL___S 12 +#define DBG_CSR_INTR_EDGE_SEL15__BIT246_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL15__BIT246_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL15__BIT246_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL15__BIT245_EDGE_SEL___M 0x00000C00 +#define DBG_CSR_INTR_EDGE_SEL15__BIT245_EDGE_SEL___S 10 +#define DBG_CSR_INTR_EDGE_SEL15__BIT245_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL15__BIT245_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL15__BIT245_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL15__BIT244_EDGE_SEL___M 0x00000300 +#define DBG_CSR_INTR_EDGE_SEL15__BIT244_EDGE_SEL___S 8 +#define DBG_CSR_INTR_EDGE_SEL15__BIT244_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL15__BIT244_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL15__BIT244_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL15__BIT243_EDGE_SEL___M 0x000000C0 +#define DBG_CSR_INTR_EDGE_SEL15__BIT243_EDGE_SEL___S 6 +#define DBG_CSR_INTR_EDGE_SEL15__BIT243_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL15__BIT243_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL15__BIT243_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL15__BIT242_EDGE_SEL___M 0x00000030 +#define DBG_CSR_INTR_EDGE_SEL15__BIT242_EDGE_SEL___S 4 +#define DBG_CSR_INTR_EDGE_SEL15__BIT242_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL15__BIT242_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL15__BIT242_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL15__BIT241_EDGE_SEL___M 0x0000000C +#define DBG_CSR_INTR_EDGE_SEL15__BIT241_EDGE_SEL___S 2 +#define DBG_CSR_INTR_EDGE_SEL15__BIT241_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL15__BIT241_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL15__BIT241_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL15__BIT240_EDGE_SEL___M 0x00000003 +#define DBG_CSR_INTR_EDGE_SEL15__BIT240_EDGE_SEL___S 0 +#define DBG_CSR_INTR_EDGE_SEL15__BIT240_EDGE_SEL__RSNG_EDGE 0x0 +#define DBG_CSR_INTR_EDGE_SEL15__BIT240_EDGE_SEL__FLNG_EDGE 0x1 +#define DBG_CSR_INTR_EDGE_SEL15__BIT240_EDGE_SEL__EITHER_EDGE 0x2 +#define DBG_CSR_INTR_EDGE_SEL15___M 0xFFFFFFFF +#define DBG_CSR_INTR_EDGE_SEL15___S 0 + +#define DBG_CSR_INTR_DSB_SEL0 (0x00B91840) +#define DBG_CSR_INTR_DSB_SEL0___RWC QCSR_REG_RW +#define DBG_CSR_INTR_DSB_SEL0___POR 0x03020100 +#define DBG_CSR_INTR_DSB_SEL0__BIT3_DSB_SEL___POR 0x03 +#define DBG_CSR_INTR_DSB_SEL0__BIT2_DSB_SEL___POR 0x02 +#define DBG_CSR_INTR_DSB_SEL0__BIT1_DSB_SEL___POR 0x01 +#define DBG_CSR_INTR_DSB_SEL0__BIT0_DSB_SEL___POR 0x00 +#define DBG_CSR_INTR_DSB_SEL0__BIT3_DSB_SEL___M 0xFF000000 +#define DBG_CSR_INTR_DSB_SEL0__BIT3_DSB_SEL___S 24 +#define DBG_CSR_INTR_DSB_SEL0__BIT2_DSB_SEL___M 0x00FF0000 +#define DBG_CSR_INTR_DSB_SEL0__BIT2_DSB_SEL___S 16 +#define DBG_CSR_INTR_DSB_SEL0__BIT1_DSB_SEL___M 0x0000FF00 +#define DBG_CSR_INTR_DSB_SEL0__BIT1_DSB_SEL___S 8 +#define DBG_CSR_INTR_DSB_SEL0__BIT0_DSB_SEL___M 0x000000FF +#define DBG_CSR_INTR_DSB_SEL0__BIT0_DSB_SEL___S 0 +#define DBG_CSR_INTR_DSB_SEL0___M 0xFFFFFFFF +#define DBG_CSR_INTR_DSB_SEL0___S 0 + +#define DBG_CSR_INTR_DSB_SEL1 (0x00B91844) +#define DBG_CSR_INTR_DSB_SEL1___RWC QCSR_REG_RW +#define DBG_CSR_INTR_DSB_SEL1___POR 0x07060504 +#define DBG_CSR_INTR_DSB_SEL1__BIT7_DSB_SEL___POR 0x07 +#define DBG_CSR_INTR_DSB_SEL1__BIT6_DSB_SEL___POR 0x06 +#define DBG_CSR_INTR_DSB_SEL1__BIT5_DSB_SEL___POR 0x05 +#define DBG_CSR_INTR_DSB_SEL1__BIT4_DSB_SEL___POR 0x04 +#define DBG_CSR_INTR_DSB_SEL1__BIT7_DSB_SEL___M 0xFF000000 +#define DBG_CSR_INTR_DSB_SEL1__BIT7_DSB_SEL___S 24 +#define DBG_CSR_INTR_DSB_SEL1__BIT6_DSB_SEL___M 0x00FF0000 +#define DBG_CSR_INTR_DSB_SEL1__BIT6_DSB_SEL___S 16 +#define DBG_CSR_INTR_DSB_SEL1__BIT5_DSB_SEL___M 0x0000FF00 +#define DBG_CSR_INTR_DSB_SEL1__BIT5_DSB_SEL___S 8 +#define DBG_CSR_INTR_DSB_SEL1__BIT4_DSB_SEL___M 0x000000FF +#define DBG_CSR_INTR_DSB_SEL1__BIT4_DSB_SEL___S 0 +#define DBG_CSR_INTR_DSB_SEL1___M 0xFFFFFFFF +#define DBG_CSR_INTR_DSB_SEL1___S 0 + +#define DBG_CSR_INTR_DSB_SEL2 (0x00B91848) +#define DBG_CSR_INTR_DSB_SEL2___RWC QCSR_REG_RW +#define DBG_CSR_INTR_DSB_SEL2___POR 0x0B0A0908 +#define DBG_CSR_INTR_DSB_SEL2__BIT11_DSB_SEL___POR 0x0B +#define DBG_CSR_INTR_DSB_SEL2__BIT10_DSB_SEL___POR 0x0A +#define DBG_CSR_INTR_DSB_SEL2__BIT9_DSB_SEL___POR 0x09 +#define DBG_CSR_INTR_DSB_SEL2__BIT8_DSB_SEL___POR 0x08 +#define DBG_CSR_INTR_DSB_SEL2__BIT11_DSB_SEL___M 0xFF000000 +#define DBG_CSR_INTR_DSB_SEL2__BIT11_DSB_SEL___S 24 +#define DBG_CSR_INTR_DSB_SEL2__BIT10_DSB_SEL___M 0x00FF0000 +#define DBG_CSR_INTR_DSB_SEL2__BIT10_DSB_SEL___S 16 +#define DBG_CSR_INTR_DSB_SEL2__BIT9_DSB_SEL___M 0x0000FF00 +#define DBG_CSR_INTR_DSB_SEL2__BIT9_DSB_SEL___S 8 +#define DBG_CSR_INTR_DSB_SEL2__BIT8_DSB_SEL___M 0x000000FF +#define DBG_CSR_INTR_DSB_SEL2__BIT8_DSB_SEL___S 0 +#define DBG_CSR_INTR_DSB_SEL2___M 0xFFFFFFFF +#define DBG_CSR_INTR_DSB_SEL2___S 0 + +#define DBG_CSR_INTR_DSB_SEL3 (0x00B9184C) +#define DBG_CSR_INTR_DSB_SEL3___RWC QCSR_REG_RW +#define DBG_CSR_INTR_DSB_SEL3___POR 0x0F0E0D0C +#define DBG_CSR_INTR_DSB_SEL3__BIT15_DSB_SEL___POR 0x0F +#define DBG_CSR_INTR_DSB_SEL3__BIT14_DSB_SEL___POR 0x0E +#define DBG_CSR_INTR_DSB_SEL3__BIT13_DSB_SEL___POR 0x0D +#define DBG_CSR_INTR_DSB_SEL3__BIT12_DSB_SEL___POR 0x0C +#define DBG_CSR_INTR_DSB_SEL3__BIT15_DSB_SEL___M 0xFF000000 +#define DBG_CSR_INTR_DSB_SEL3__BIT15_DSB_SEL___S 24 +#define DBG_CSR_INTR_DSB_SEL3__BIT14_DSB_SEL___M 0x00FF0000 +#define DBG_CSR_INTR_DSB_SEL3__BIT14_DSB_SEL___S 16 +#define DBG_CSR_INTR_DSB_SEL3__BIT13_DSB_SEL___M 0x0000FF00 +#define DBG_CSR_INTR_DSB_SEL3__BIT13_DSB_SEL___S 8 +#define DBG_CSR_INTR_DSB_SEL3__BIT12_DSB_SEL___M 0x000000FF +#define DBG_CSR_INTR_DSB_SEL3__BIT12_DSB_SEL___S 0 +#define DBG_CSR_INTR_DSB_SEL3___M 0xFFFFFFFF +#define DBG_CSR_INTR_DSB_SEL3___S 0 + +#define DBG_CSR_INTR_DSB_SEL4 (0x00B91850) +#define DBG_CSR_INTR_DSB_SEL4___RWC QCSR_REG_RW +#define DBG_CSR_INTR_DSB_SEL4___POR 0x13121110 +#define DBG_CSR_INTR_DSB_SEL4__BIT19_DSB_SEL___POR 0x13 +#define DBG_CSR_INTR_DSB_SEL4__BIT18_DSB_SEL___POR 0x12 +#define DBG_CSR_INTR_DSB_SEL4__BIT17_DSB_SEL___POR 0x11 +#define DBG_CSR_INTR_DSB_SEL4__BIT16_DSB_SEL___POR 0x10 +#define DBG_CSR_INTR_DSB_SEL4__BIT19_DSB_SEL___M 0xFF000000 +#define DBG_CSR_INTR_DSB_SEL4__BIT19_DSB_SEL___S 24 +#define DBG_CSR_INTR_DSB_SEL4__BIT18_DSB_SEL___M 0x00FF0000 +#define DBG_CSR_INTR_DSB_SEL4__BIT18_DSB_SEL___S 16 +#define DBG_CSR_INTR_DSB_SEL4__BIT17_DSB_SEL___M 0x0000FF00 +#define DBG_CSR_INTR_DSB_SEL4__BIT17_DSB_SEL___S 8 +#define DBG_CSR_INTR_DSB_SEL4__BIT16_DSB_SEL___M 0x000000FF +#define DBG_CSR_INTR_DSB_SEL4__BIT16_DSB_SEL___S 0 +#define DBG_CSR_INTR_DSB_SEL4___M 0xFFFFFFFF +#define DBG_CSR_INTR_DSB_SEL4___S 0 + +#define DBG_CSR_INTR_DSB_SEL5 (0x00B91854) +#define DBG_CSR_INTR_DSB_SEL5___RWC QCSR_REG_RW +#define DBG_CSR_INTR_DSB_SEL5___POR 0x17161514 +#define DBG_CSR_INTR_DSB_SEL5__BIT23_DSB_SEL___POR 0x17 +#define DBG_CSR_INTR_DSB_SEL5__BIT22_DSB_SEL___POR 0x16 +#define DBG_CSR_INTR_DSB_SEL5__BIT21_DSB_SEL___POR 0x15 +#define DBG_CSR_INTR_DSB_SEL5__BIT20_DSB_SEL___POR 0x14 +#define DBG_CSR_INTR_DSB_SEL5__BIT23_DSB_SEL___M 0xFF000000 +#define DBG_CSR_INTR_DSB_SEL5__BIT23_DSB_SEL___S 24 +#define DBG_CSR_INTR_DSB_SEL5__BIT22_DSB_SEL___M 0x00FF0000 +#define DBG_CSR_INTR_DSB_SEL5__BIT22_DSB_SEL___S 16 +#define DBG_CSR_INTR_DSB_SEL5__BIT21_DSB_SEL___M 0x0000FF00 +#define DBG_CSR_INTR_DSB_SEL5__BIT21_DSB_SEL___S 8 +#define DBG_CSR_INTR_DSB_SEL5__BIT20_DSB_SEL___M 0x000000FF +#define DBG_CSR_INTR_DSB_SEL5__BIT20_DSB_SEL___S 0 +#define DBG_CSR_INTR_DSB_SEL5___M 0xFFFFFFFF +#define DBG_CSR_INTR_DSB_SEL5___S 0 + +#define DBG_CSR_INTR_DSB_SEL6 (0x00B91858) +#define DBG_CSR_INTR_DSB_SEL6___RWC QCSR_REG_RW +#define DBG_CSR_INTR_DSB_SEL6___POR 0x1B1A1918 +#define DBG_CSR_INTR_DSB_SEL6__BIT27_DSB_SEL___POR 0x1B +#define DBG_CSR_INTR_DSB_SEL6__BIT26_DSB_SEL___POR 0x1A +#define DBG_CSR_INTR_DSB_SEL6__BIT25_DSB_SEL___POR 0x19 +#define DBG_CSR_INTR_DSB_SEL6__BIT24_DSB_SEL___POR 0x18 +#define DBG_CSR_INTR_DSB_SEL6__BIT27_DSB_SEL___M 0xFF000000 +#define DBG_CSR_INTR_DSB_SEL6__BIT27_DSB_SEL___S 24 +#define DBG_CSR_INTR_DSB_SEL6__BIT26_DSB_SEL___M 0x00FF0000 +#define DBG_CSR_INTR_DSB_SEL6__BIT26_DSB_SEL___S 16 +#define DBG_CSR_INTR_DSB_SEL6__BIT25_DSB_SEL___M 0x0000FF00 +#define DBG_CSR_INTR_DSB_SEL6__BIT25_DSB_SEL___S 8 +#define DBG_CSR_INTR_DSB_SEL6__BIT24_DSB_SEL___M 0x000000FF +#define DBG_CSR_INTR_DSB_SEL6__BIT24_DSB_SEL___S 0 +#define DBG_CSR_INTR_DSB_SEL6___M 0xFFFFFFFF +#define DBG_CSR_INTR_DSB_SEL6___S 0 + +#define DBG_CSR_INTR_DSB_SEL7 (0x00B9185C) +#define DBG_CSR_INTR_DSB_SEL7___RWC QCSR_REG_RW +#define DBG_CSR_INTR_DSB_SEL7___POR 0x1F1E1D1C +#define DBG_CSR_INTR_DSB_SEL7__BIT31_DSB_SEL___POR 0x1F +#define DBG_CSR_INTR_DSB_SEL7__BIT30_DSB_SEL___POR 0x1E +#define DBG_CSR_INTR_DSB_SEL7__BIT29_DSB_SEL___POR 0x1D +#define DBG_CSR_INTR_DSB_SEL7__BIT28_DSB_SEL___POR 0x1C +#define DBG_CSR_INTR_DSB_SEL7__BIT31_DSB_SEL___M 0xFF000000 +#define DBG_CSR_INTR_DSB_SEL7__BIT31_DSB_SEL___S 24 +#define DBG_CSR_INTR_DSB_SEL7__BIT30_DSB_SEL___M 0x00FF0000 +#define DBG_CSR_INTR_DSB_SEL7__BIT30_DSB_SEL___S 16 +#define DBG_CSR_INTR_DSB_SEL7__BIT29_DSB_SEL___M 0x0000FF00 +#define DBG_CSR_INTR_DSB_SEL7__BIT29_DSB_SEL___S 8 +#define DBG_CSR_INTR_DSB_SEL7__BIT28_DSB_SEL___M 0x000000FF +#define DBG_CSR_INTR_DSB_SEL7__BIT28_DSB_SEL___S 0 +#define DBG_CSR_INTR_DSB_SEL7___M 0xFFFFFFFF +#define DBG_CSR_INTR_DSB_SEL7___S 0 + +#define DBG_CSR_INTR_DSB_SEL8 (0x00B91860) +#define DBG_CSR_INTR_DSB_SEL8___RWC QCSR_REG_RW +#define DBG_CSR_INTR_DSB_SEL8___POR 0x23222120 +#define DBG_CSR_INTR_DSB_SEL8__BIT35_DSB_SEL___POR 0x23 +#define DBG_CSR_INTR_DSB_SEL8__BIT34_DSB_SEL___POR 0x22 +#define DBG_CSR_INTR_DSB_SEL8__BIT33_DSB_SEL___POR 0x21 +#define DBG_CSR_INTR_DSB_SEL8__BIT32_DSB_SEL___POR 0x20 +#define DBG_CSR_INTR_DSB_SEL8__BIT35_DSB_SEL___M 0xFF000000 +#define DBG_CSR_INTR_DSB_SEL8__BIT35_DSB_SEL___S 24 +#define DBG_CSR_INTR_DSB_SEL8__BIT34_DSB_SEL___M 0x00FF0000 +#define DBG_CSR_INTR_DSB_SEL8__BIT34_DSB_SEL___S 16 +#define DBG_CSR_INTR_DSB_SEL8__BIT33_DSB_SEL___M 0x0000FF00 +#define DBG_CSR_INTR_DSB_SEL8__BIT33_DSB_SEL___S 8 +#define DBG_CSR_INTR_DSB_SEL8__BIT32_DSB_SEL___M 0x000000FF +#define DBG_CSR_INTR_DSB_SEL8__BIT32_DSB_SEL___S 0 +#define DBG_CSR_INTR_DSB_SEL8___M 0xFFFFFFFF +#define DBG_CSR_INTR_DSB_SEL8___S 0 + +#define DBG_CSR_INTR_DSB_SEL9 (0x00B91864) +#define DBG_CSR_INTR_DSB_SEL9___RWC QCSR_REG_RW +#define DBG_CSR_INTR_DSB_SEL9___POR 0x27262524 +#define DBG_CSR_INTR_DSB_SEL9__BIT39_DSB_SEL___POR 0x27 +#define DBG_CSR_INTR_DSB_SEL9__BIT38_DSB_SEL___POR 0x26 +#define DBG_CSR_INTR_DSB_SEL9__BIT37_DSB_SEL___POR 0x25 +#define DBG_CSR_INTR_DSB_SEL9__BIT36_DSB_SEL___POR 0x24 +#define DBG_CSR_INTR_DSB_SEL9__BIT39_DSB_SEL___M 0xFF000000 +#define DBG_CSR_INTR_DSB_SEL9__BIT39_DSB_SEL___S 24 +#define DBG_CSR_INTR_DSB_SEL9__BIT38_DSB_SEL___M 0x00FF0000 +#define DBG_CSR_INTR_DSB_SEL9__BIT38_DSB_SEL___S 16 +#define DBG_CSR_INTR_DSB_SEL9__BIT37_DSB_SEL___M 0x0000FF00 +#define DBG_CSR_INTR_DSB_SEL9__BIT37_DSB_SEL___S 8 +#define DBG_CSR_INTR_DSB_SEL9__BIT36_DSB_SEL___M 0x000000FF +#define DBG_CSR_INTR_DSB_SEL9__BIT36_DSB_SEL___S 0 +#define DBG_CSR_INTR_DSB_SEL9___M 0xFFFFFFFF +#define DBG_CSR_INTR_DSB_SEL9___S 0 + +#define DBG_CSR_INTR_DSB_SEL10 (0x00B91868) +#define DBG_CSR_INTR_DSB_SEL10___RWC QCSR_REG_RW +#define DBG_CSR_INTR_DSB_SEL10___POR 0x2B2A2928 +#define DBG_CSR_INTR_DSB_SEL10__BIT43_DSB_SEL___POR 0x2B +#define DBG_CSR_INTR_DSB_SEL10__BIT42_DSB_SEL___POR 0x2A +#define DBG_CSR_INTR_DSB_SEL10__BIT41_DSB_SEL___POR 0x29 +#define DBG_CSR_INTR_DSB_SEL10__BIT40_DSB_SEL___POR 0x28 +#define DBG_CSR_INTR_DSB_SEL10__BIT43_DSB_SEL___M 0xFF000000 +#define DBG_CSR_INTR_DSB_SEL10__BIT43_DSB_SEL___S 24 +#define DBG_CSR_INTR_DSB_SEL10__BIT42_DSB_SEL___M 0x00FF0000 +#define DBG_CSR_INTR_DSB_SEL10__BIT42_DSB_SEL___S 16 +#define DBG_CSR_INTR_DSB_SEL10__BIT41_DSB_SEL___M 0x0000FF00 +#define DBG_CSR_INTR_DSB_SEL10__BIT41_DSB_SEL___S 8 +#define DBG_CSR_INTR_DSB_SEL10__BIT40_DSB_SEL___M 0x000000FF +#define DBG_CSR_INTR_DSB_SEL10__BIT40_DSB_SEL___S 0 +#define DBG_CSR_INTR_DSB_SEL10___M 0xFFFFFFFF +#define DBG_CSR_INTR_DSB_SEL10___S 0 + +#define DBG_CSR_INTR_DSB_SEL11 (0x00B9186C) +#define DBG_CSR_INTR_DSB_SEL11___RWC QCSR_REG_RW +#define DBG_CSR_INTR_DSB_SEL11___POR 0x2F2E2D2C +#define DBG_CSR_INTR_DSB_SEL11__BIT47_DSB_SEL___POR 0x2F +#define DBG_CSR_INTR_DSB_SEL11__BIT46_DSB_SEL___POR 0x2E +#define DBG_CSR_INTR_DSB_SEL11__BIT45_DSB_SEL___POR 0x2D +#define DBG_CSR_INTR_DSB_SEL11__BIT44_DSB_SEL___POR 0x2C +#define DBG_CSR_INTR_DSB_SEL11__BIT47_DSB_SEL___M 0xFF000000 +#define DBG_CSR_INTR_DSB_SEL11__BIT47_DSB_SEL___S 24 +#define DBG_CSR_INTR_DSB_SEL11__BIT46_DSB_SEL___M 0x00FF0000 +#define DBG_CSR_INTR_DSB_SEL11__BIT46_DSB_SEL___S 16 +#define DBG_CSR_INTR_DSB_SEL11__BIT45_DSB_SEL___M 0x0000FF00 +#define DBG_CSR_INTR_DSB_SEL11__BIT45_DSB_SEL___S 8 +#define DBG_CSR_INTR_DSB_SEL11__BIT44_DSB_SEL___M 0x000000FF +#define DBG_CSR_INTR_DSB_SEL11__BIT44_DSB_SEL___S 0 +#define DBG_CSR_INTR_DSB_SEL11___M 0xFFFFFFFF +#define DBG_CSR_INTR_DSB_SEL11___S 0 + +#define DBG_CSR_INTR_DSB_SEL12 (0x00B91870) +#define DBG_CSR_INTR_DSB_SEL12___RWC QCSR_REG_RW +#define DBG_CSR_INTR_DSB_SEL12___POR 0x33323130 +#define DBG_CSR_INTR_DSB_SEL12__BIT51_DSB_SEL___POR 0x33 +#define DBG_CSR_INTR_DSB_SEL12__BIT50_DSB_SEL___POR 0x32 +#define DBG_CSR_INTR_DSB_SEL12__BIT49_DSB_SEL___POR 0x31 +#define DBG_CSR_INTR_DSB_SEL12__BIT48_DSB_SEL___POR 0x30 +#define DBG_CSR_INTR_DSB_SEL12__BIT51_DSB_SEL___M 0xFF000000 +#define DBG_CSR_INTR_DSB_SEL12__BIT51_DSB_SEL___S 24 +#define DBG_CSR_INTR_DSB_SEL12__BIT50_DSB_SEL___M 0x00FF0000 +#define DBG_CSR_INTR_DSB_SEL12__BIT50_DSB_SEL___S 16 +#define DBG_CSR_INTR_DSB_SEL12__BIT49_DSB_SEL___M 0x0000FF00 +#define DBG_CSR_INTR_DSB_SEL12__BIT49_DSB_SEL___S 8 +#define DBG_CSR_INTR_DSB_SEL12__BIT48_DSB_SEL___M 0x000000FF +#define DBG_CSR_INTR_DSB_SEL12__BIT48_DSB_SEL___S 0 +#define DBG_CSR_INTR_DSB_SEL12___M 0xFFFFFFFF +#define DBG_CSR_INTR_DSB_SEL12___S 0 + +#define DBG_CSR_INTR_DSB_SEL13 (0x00B91874) +#define DBG_CSR_INTR_DSB_SEL13___RWC QCSR_REG_RW +#define DBG_CSR_INTR_DSB_SEL13___POR 0x37363534 +#define DBG_CSR_INTR_DSB_SEL13__BIT55_DSB_SEL___POR 0x37 +#define DBG_CSR_INTR_DSB_SEL13__BIT54_DSB_SEL___POR 0x36 +#define DBG_CSR_INTR_DSB_SEL13__BIT53_DSB_SEL___POR 0x35 +#define DBG_CSR_INTR_DSB_SEL13__BIT52_DSB_SEL___POR 0x34 +#define DBG_CSR_INTR_DSB_SEL13__BIT55_DSB_SEL___M 0xFF000000 +#define DBG_CSR_INTR_DSB_SEL13__BIT55_DSB_SEL___S 24 +#define DBG_CSR_INTR_DSB_SEL13__BIT54_DSB_SEL___M 0x00FF0000 +#define DBG_CSR_INTR_DSB_SEL13__BIT54_DSB_SEL___S 16 +#define DBG_CSR_INTR_DSB_SEL13__BIT53_DSB_SEL___M 0x0000FF00 +#define DBG_CSR_INTR_DSB_SEL13__BIT53_DSB_SEL___S 8 +#define DBG_CSR_INTR_DSB_SEL13__BIT52_DSB_SEL___M 0x000000FF +#define DBG_CSR_INTR_DSB_SEL13__BIT52_DSB_SEL___S 0 +#define DBG_CSR_INTR_DSB_SEL13___M 0xFFFFFFFF +#define DBG_CSR_INTR_DSB_SEL13___S 0 + +#define DBG_CSR_INTR_DSB_SEL14 (0x00B91878) +#define DBG_CSR_INTR_DSB_SEL14___RWC QCSR_REG_RW +#define DBG_CSR_INTR_DSB_SEL14___POR 0x3B3A3938 +#define DBG_CSR_INTR_DSB_SEL14__BIT59_DSB_SEL___POR 0x3B +#define DBG_CSR_INTR_DSB_SEL14__BIT58_DSB_SEL___POR 0x3A +#define DBG_CSR_INTR_DSB_SEL14__BIT57_DSB_SEL___POR 0x39 +#define DBG_CSR_INTR_DSB_SEL14__BIT56_DSB_SEL___POR 0x38 +#define DBG_CSR_INTR_DSB_SEL14__BIT59_DSB_SEL___M 0xFF000000 +#define DBG_CSR_INTR_DSB_SEL14__BIT59_DSB_SEL___S 24 +#define DBG_CSR_INTR_DSB_SEL14__BIT58_DSB_SEL___M 0x00FF0000 +#define DBG_CSR_INTR_DSB_SEL14__BIT58_DSB_SEL___S 16 +#define DBG_CSR_INTR_DSB_SEL14__BIT57_DSB_SEL___M 0x0000FF00 +#define DBG_CSR_INTR_DSB_SEL14__BIT57_DSB_SEL___S 8 +#define DBG_CSR_INTR_DSB_SEL14__BIT56_DSB_SEL___M 0x000000FF +#define DBG_CSR_INTR_DSB_SEL14__BIT56_DSB_SEL___S 0 +#define DBG_CSR_INTR_DSB_SEL14___M 0xFFFFFFFF +#define DBG_CSR_INTR_DSB_SEL14___S 0 + +#define DBG_CSR_INTR_DSB_SEL15 (0x00B9187C) +#define DBG_CSR_INTR_DSB_SEL15___RWC QCSR_REG_RW +#define DBG_CSR_INTR_DSB_SEL15___POR 0x3F3E3D3C +#define DBG_CSR_INTR_DSB_SEL15__BIT63_DSB_SEL___POR 0x3F +#define DBG_CSR_INTR_DSB_SEL15__BIT62_DSB_SEL___POR 0x3E +#define DBG_CSR_INTR_DSB_SEL15__BIT61_DSB_SEL___POR 0x3D +#define DBG_CSR_INTR_DSB_SEL15__BIT60_DSB_SEL___POR 0x3C +#define DBG_CSR_INTR_DSB_SEL15__BIT63_DSB_SEL___M 0xFF000000 +#define DBG_CSR_INTR_DSB_SEL15__BIT63_DSB_SEL___S 24 +#define DBG_CSR_INTR_DSB_SEL15__BIT62_DSB_SEL___M 0x00FF0000 +#define DBG_CSR_INTR_DSB_SEL15__BIT62_DSB_SEL___S 16 +#define DBG_CSR_INTR_DSB_SEL15__BIT61_DSB_SEL___M 0x0000FF00 +#define DBG_CSR_INTR_DSB_SEL15__BIT61_DSB_SEL___S 8 +#define DBG_CSR_INTR_DSB_SEL15__BIT60_DSB_SEL___M 0x000000FF +#define DBG_CSR_INTR_DSB_SEL15__BIT60_DSB_SEL___S 0 +#define DBG_CSR_INTR_DSB_SEL15___M 0xFFFFFFFF +#define DBG_CSR_INTR_DSB_SEL15___S 0 + +#define DBG_CSR_INTR_CTI_SEL0 (0x00B91880) +#define DBG_CSR_INTR_CTI_SEL0___RWC QCSR_REG_RW +#define DBG_CSR_INTR_CTI_SEL0___POR 0x03020100 +#define DBG_CSR_INTR_CTI_SEL0__BIT3_CTI_SEL___POR 0x03 +#define DBG_CSR_INTR_CTI_SEL0__BIT2_CTI_SEL___POR 0x02 +#define DBG_CSR_INTR_CTI_SEL0__BIT1_CTI_SEL___POR 0x01 +#define DBG_CSR_INTR_CTI_SEL0__BIT0_CTI_SEL___POR 0x00 +#define DBG_CSR_INTR_CTI_SEL0__BIT3_CTI_SEL___M 0xFF000000 +#define DBG_CSR_INTR_CTI_SEL0__BIT3_CTI_SEL___S 24 +#define DBG_CSR_INTR_CTI_SEL0__BIT2_CTI_SEL___M 0x00FF0000 +#define DBG_CSR_INTR_CTI_SEL0__BIT2_CTI_SEL___S 16 +#define DBG_CSR_INTR_CTI_SEL0__BIT1_CTI_SEL___M 0x0000FF00 +#define DBG_CSR_INTR_CTI_SEL0__BIT1_CTI_SEL___S 8 +#define DBG_CSR_INTR_CTI_SEL0__BIT0_CTI_SEL___M 0x000000FF +#define DBG_CSR_INTR_CTI_SEL0__BIT0_CTI_SEL___S 0 +#define DBG_CSR_INTR_CTI_SEL0___M 0xFFFFFFFF +#define DBG_CSR_INTR_CTI_SEL0___S 0 + +#define DBG_CSR_INTR_CTI_SEL1 (0x00B91884) +#define DBG_CSR_INTR_CTI_SEL1___RWC QCSR_REG_RW +#define DBG_CSR_INTR_CTI_SEL1___POR 0x07060504 +#define DBG_CSR_INTR_CTI_SEL1__BIT7_CTI_SEL___POR 0x07 +#define DBG_CSR_INTR_CTI_SEL1__BIT6_CTI_SEL___POR 0x06 +#define DBG_CSR_INTR_CTI_SEL1__BIT5_CTI_SEL___POR 0x05 +#define DBG_CSR_INTR_CTI_SEL1__BIT4_CTI_SEL___POR 0x04 +#define DBG_CSR_INTR_CTI_SEL1__BIT7_CTI_SEL___M 0xFF000000 +#define DBG_CSR_INTR_CTI_SEL1__BIT7_CTI_SEL___S 24 +#define DBG_CSR_INTR_CTI_SEL1__BIT6_CTI_SEL___M 0x00FF0000 +#define DBG_CSR_INTR_CTI_SEL1__BIT6_CTI_SEL___S 16 +#define DBG_CSR_INTR_CTI_SEL1__BIT5_CTI_SEL___M 0x0000FF00 +#define DBG_CSR_INTR_CTI_SEL1__BIT5_CTI_SEL___S 8 +#define DBG_CSR_INTR_CTI_SEL1__BIT4_CTI_SEL___M 0x000000FF +#define DBG_CSR_INTR_CTI_SEL1__BIT4_CTI_SEL___S 0 +#define DBG_CSR_INTR_CTI_SEL1___M 0xFFFFFFFF +#define DBG_CSR_INTR_CTI_SEL1___S 0 + +#define DBG_CSR_INTR_CTI_SEL2 (0x00B91888) +#define DBG_CSR_INTR_CTI_SEL2___RWC QCSR_REG_RW +#define DBG_CSR_INTR_CTI_SEL2___POR 0x0B0A0908 +#define DBG_CSR_INTR_CTI_SEL2__BIT11_CTI_SEL___POR 0x0B +#define DBG_CSR_INTR_CTI_SEL2__BIT10_CTI_SEL___POR 0x0A +#define DBG_CSR_INTR_CTI_SEL2__BIT9_CTI_SEL___POR 0x09 +#define DBG_CSR_INTR_CTI_SEL2__BIT8_CTI_SEL___POR 0x08 +#define DBG_CSR_INTR_CTI_SEL2__BIT11_CTI_SEL___M 0xFF000000 +#define DBG_CSR_INTR_CTI_SEL2__BIT11_CTI_SEL___S 24 +#define DBG_CSR_INTR_CTI_SEL2__BIT10_CTI_SEL___M 0x00FF0000 +#define DBG_CSR_INTR_CTI_SEL2__BIT10_CTI_SEL___S 16 +#define DBG_CSR_INTR_CTI_SEL2__BIT9_CTI_SEL___M 0x0000FF00 +#define DBG_CSR_INTR_CTI_SEL2__BIT9_CTI_SEL___S 8 +#define DBG_CSR_INTR_CTI_SEL2__BIT8_CTI_SEL___M 0x000000FF +#define DBG_CSR_INTR_CTI_SEL2__BIT8_CTI_SEL___S 0 +#define DBG_CSR_INTR_CTI_SEL2___M 0xFFFFFFFF +#define DBG_CSR_INTR_CTI_SEL2___S 0 + +#define DBG_CSR_INTR_CTI_SEL3 (0x00B9188C) +#define DBG_CSR_INTR_CTI_SEL3___RWC QCSR_REG_RW +#define DBG_CSR_INTR_CTI_SEL3___POR 0x0F0E0D0C +#define DBG_CSR_INTR_CTI_SEL3__BIT15_CTI_SEL___POR 0x0F +#define DBG_CSR_INTR_CTI_SEL3__BIT14_CTI_SEL___POR 0x0E +#define DBG_CSR_INTR_CTI_SEL3__BIT13_CTI_SEL___POR 0x0D +#define DBG_CSR_INTR_CTI_SEL3__BIT12_CTI_SEL___POR 0x0C +#define DBG_CSR_INTR_CTI_SEL3__BIT15_CTI_SEL___M 0xFF000000 +#define DBG_CSR_INTR_CTI_SEL3__BIT15_CTI_SEL___S 24 +#define DBG_CSR_INTR_CTI_SEL3__BIT14_CTI_SEL___M 0x00FF0000 +#define DBG_CSR_INTR_CTI_SEL3__BIT14_CTI_SEL___S 16 +#define DBG_CSR_INTR_CTI_SEL3__BIT13_CTI_SEL___M 0x0000FF00 +#define DBG_CSR_INTR_CTI_SEL3__BIT13_CTI_SEL___S 8 +#define DBG_CSR_INTR_CTI_SEL3__BIT12_CTI_SEL___M 0x000000FF +#define DBG_CSR_INTR_CTI_SEL3__BIT12_CTI_SEL___S 0 +#define DBG_CSR_INTR_CTI_SEL3___M 0xFFFFFFFF +#define DBG_CSR_INTR_CTI_SEL3___S 0 + +#define DBG_CSR_INTR_CTI_SEL4 (0x00B91890) +#define DBG_CSR_INTR_CTI_SEL4___RWC QCSR_REG_RW +#define DBG_CSR_INTR_CTI_SEL4___POR 0x13121110 +#define DBG_CSR_INTR_CTI_SEL4__BIT19_CTI_SEL___POR 0x13 +#define DBG_CSR_INTR_CTI_SEL4__BIT18_CTI_SEL___POR 0x12 +#define DBG_CSR_INTR_CTI_SEL4__BIT17_CTI_SEL___POR 0x11 +#define DBG_CSR_INTR_CTI_SEL4__BIT16_CTI_SEL___POR 0x10 +#define DBG_CSR_INTR_CTI_SEL4__BIT19_CTI_SEL___M 0xFF000000 +#define DBG_CSR_INTR_CTI_SEL4__BIT19_CTI_SEL___S 24 +#define DBG_CSR_INTR_CTI_SEL4__BIT18_CTI_SEL___M 0x00FF0000 +#define DBG_CSR_INTR_CTI_SEL4__BIT18_CTI_SEL___S 16 +#define DBG_CSR_INTR_CTI_SEL4__BIT17_CTI_SEL___M 0x0000FF00 +#define DBG_CSR_INTR_CTI_SEL4__BIT17_CTI_SEL___S 8 +#define DBG_CSR_INTR_CTI_SEL4__BIT16_CTI_SEL___M 0x000000FF +#define DBG_CSR_INTR_CTI_SEL4__BIT16_CTI_SEL___S 0 +#define DBG_CSR_INTR_CTI_SEL4___M 0xFFFFFFFF +#define DBG_CSR_INTR_CTI_SEL4___S 0 + +#define DBG_CSR_INTR_CTI_SEL5 (0x00B91894) +#define DBG_CSR_INTR_CTI_SEL5___RWC QCSR_REG_RW +#define DBG_CSR_INTR_CTI_SEL5___POR 0x17161514 +#define DBG_CSR_INTR_CTI_SEL5__BIT23_CTI_SEL___POR 0x17 +#define DBG_CSR_INTR_CTI_SEL5__BIT22_CTI_SEL___POR 0x16 +#define DBG_CSR_INTR_CTI_SEL5__BIT21_CTI_SEL___POR 0x15 +#define DBG_CSR_INTR_CTI_SEL5__BIT20_CTI_SEL___POR 0x14 +#define DBG_CSR_INTR_CTI_SEL5__BIT23_CTI_SEL___M 0xFF000000 +#define DBG_CSR_INTR_CTI_SEL5__BIT23_CTI_SEL___S 24 +#define DBG_CSR_INTR_CTI_SEL5__BIT22_CTI_SEL___M 0x00FF0000 +#define DBG_CSR_INTR_CTI_SEL5__BIT22_CTI_SEL___S 16 +#define DBG_CSR_INTR_CTI_SEL5__BIT21_CTI_SEL___M 0x0000FF00 +#define DBG_CSR_INTR_CTI_SEL5__BIT21_CTI_SEL___S 8 +#define DBG_CSR_INTR_CTI_SEL5__BIT20_CTI_SEL___M 0x000000FF +#define DBG_CSR_INTR_CTI_SEL5__BIT20_CTI_SEL___S 0 +#define DBG_CSR_INTR_CTI_SEL5___M 0xFFFFFFFF +#define DBG_CSR_INTR_CTI_SEL5___S 0 + +#define DBG_CSR_INTR_CTI_SEL6 (0x00B91898) +#define DBG_CSR_INTR_CTI_SEL6___RWC QCSR_REG_RW +#define DBG_CSR_INTR_CTI_SEL6___POR 0x1B1A1918 +#define DBG_CSR_INTR_CTI_SEL6__BIT27_CTI_SEL___POR 0x1B +#define DBG_CSR_INTR_CTI_SEL6__BIT26_CTI_SEL___POR 0x1A +#define DBG_CSR_INTR_CTI_SEL6__BIT25_CTI_SEL___POR 0x19 +#define DBG_CSR_INTR_CTI_SEL6__BIT24_CTI_SEL___POR 0x18 +#define DBG_CSR_INTR_CTI_SEL6__BIT27_CTI_SEL___M 0xFF000000 +#define DBG_CSR_INTR_CTI_SEL6__BIT27_CTI_SEL___S 24 +#define DBG_CSR_INTR_CTI_SEL6__BIT26_CTI_SEL___M 0x00FF0000 +#define DBG_CSR_INTR_CTI_SEL6__BIT26_CTI_SEL___S 16 +#define DBG_CSR_INTR_CTI_SEL6__BIT25_CTI_SEL___M 0x0000FF00 +#define DBG_CSR_INTR_CTI_SEL6__BIT25_CTI_SEL___S 8 +#define DBG_CSR_INTR_CTI_SEL6__BIT24_CTI_SEL___M 0x000000FF +#define DBG_CSR_INTR_CTI_SEL6__BIT24_CTI_SEL___S 0 +#define DBG_CSR_INTR_CTI_SEL6___M 0xFFFFFFFF +#define DBG_CSR_INTR_CTI_SEL6___S 0 + +#define DBG_CSR_INTR_CTI_SEL7 (0x00B9189C) +#define DBG_CSR_INTR_CTI_SEL7___RWC QCSR_REG_RW +#define DBG_CSR_INTR_CTI_SEL7___POR 0x1F1E1D1C +#define DBG_CSR_INTR_CTI_SEL7__BIT31_CTI_SEL___POR 0x1F +#define DBG_CSR_INTR_CTI_SEL7__BIT30_CTI_SEL___POR 0x1E +#define DBG_CSR_INTR_CTI_SEL7__BIT29_CTI_SEL___POR 0x1D +#define DBG_CSR_INTR_CTI_SEL7__BIT28_CTI_SEL___POR 0x1C +#define DBG_CSR_INTR_CTI_SEL7__BIT31_CTI_SEL___M 0xFF000000 +#define DBG_CSR_INTR_CTI_SEL7__BIT31_CTI_SEL___S 24 +#define DBG_CSR_INTR_CTI_SEL7__BIT30_CTI_SEL___M 0x00FF0000 +#define DBG_CSR_INTR_CTI_SEL7__BIT30_CTI_SEL___S 16 +#define DBG_CSR_INTR_CTI_SEL7__BIT29_CTI_SEL___M 0x0000FF00 +#define DBG_CSR_INTR_CTI_SEL7__BIT29_CTI_SEL___S 8 +#define DBG_CSR_INTR_CTI_SEL7__BIT28_CTI_SEL___M 0x000000FF +#define DBG_CSR_INTR_CTI_SEL7__BIT28_CTI_SEL___S 0 +#define DBG_CSR_INTR_CTI_SEL7___M 0xFFFFFFFF +#define DBG_CSR_INTR_CTI_SEL7___S 0 + +#define DBG_CSR_INTR_ANY_MASK0 (0x00B918C0) +#define DBG_CSR_INTR_ANY_MASK0___RWC QCSR_REG_RW +#define DBG_CSR_INTR_ANY_MASK0___POR 0xFFFFFFFF +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT31_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT30_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT29_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT28_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT27_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT26_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT25_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT24_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT23_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT22_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT21_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT20_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT19_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT18_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT17_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT16_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT15_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT14_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT13_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT12_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT11_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT10_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT9_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT8_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT7_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT6_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT5_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT4_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT3_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT2_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT1_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT0_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT31_MASK___M 0x80000000 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT31_MASK___S 31 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT30_MASK___M 0x40000000 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT30_MASK___S 30 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT29_MASK___M 0x20000000 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT29_MASK___S 29 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT28_MASK___M 0x10000000 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT28_MASK___S 28 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT27_MASK___M 0x08000000 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT27_MASK___S 27 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT26_MASK___M 0x04000000 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT26_MASK___S 26 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT25_MASK___M 0x02000000 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT25_MASK___S 25 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT24_MASK___M 0x01000000 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT24_MASK___S 24 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT23_MASK___M 0x00800000 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT23_MASK___S 23 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT22_MASK___M 0x00400000 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT22_MASK___S 22 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT21_MASK___M 0x00200000 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT21_MASK___S 21 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT20_MASK___M 0x00100000 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT20_MASK___S 20 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT19_MASK___M 0x00080000 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT19_MASK___S 19 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT18_MASK___M 0x00040000 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT18_MASK___S 18 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT17_MASK___M 0x00020000 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT17_MASK___S 17 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT16_MASK___M 0x00010000 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT16_MASK___S 16 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT15_MASK___M 0x00008000 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT15_MASK___S 15 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT14_MASK___M 0x00004000 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT14_MASK___S 14 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT13_MASK___M 0x00002000 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT13_MASK___S 13 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT12_MASK___M 0x00001000 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT12_MASK___S 12 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT11_MASK___M 0x00000800 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT11_MASK___S 11 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT10_MASK___M 0x00000400 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT10_MASK___S 10 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT9_MASK___M 0x00000200 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT9_MASK___S 9 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT8_MASK___M 0x00000100 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT8_MASK___S 8 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT7_MASK___M 0x00000080 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT7_MASK___S 7 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT6_MASK___M 0x00000040 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT6_MASK___S 6 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT5_MASK___M 0x00000020 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT5_MASK___S 5 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT4_MASK___M 0x00000010 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT4_MASK___S 4 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT3_MASK___M 0x00000008 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT3_MASK___S 3 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT2_MASK___M 0x00000004 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT2_MASK___S 2 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT1_MASK___M 0x00000002 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT1_MASK___S 1 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT0_MASK___M 0x00000001 +#define DBG_CSR_INTR_ANY_MASK0__INTR_BIT0_MASK___S 0 +#define DBG_CSR_INTR_ANY_MASK0___M 0xFFFFFFFF +#define DBG_CSR_INTR_ANY_MASK0___S 0 + +#define DBG_CSR_INTR_ANY_MASK1 (0x00B918C4) +#define DBG_CSR_INTR_ANY_MASK1___RWC QCSR_REG_RW +#define DBG_CSR_INTR_ANY_MASK1___POR 0xFFFFFFFF +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT63_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT62_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT61_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT60_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT59_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT58_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT57_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT56_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT55_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT54_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT53_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT52_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT51_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT50_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT49_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT48_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT47_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT46_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT45_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT44_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT43_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT42_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT41_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT40_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT39_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT38_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT37_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT36_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT35_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT34_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT33_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT32_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT63_MASK___M 0x80000000 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT63_MASK___S 31 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT62_MASK___M 0x40000000 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT62_MASK___S 30 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT61_MASK___M 0x20000000 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT61_MASK___S 29 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT60_MASK___M 0x10000000 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT60_MASK___S 28 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT59_MASK___M 0x08000000 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT59_MASK___S 27 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT58_MASK___M 0x04000000 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT58_MASK___S 26 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT57_MASK___M 0x02000000 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT57_MASK___S 25 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT56_MASK___M 0x01000000 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT56_MASK___S 24 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT55_MASK___M 0x00800000 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT55_MASK___S 23 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT54_MASK___M 0x00400000 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT54_MASK___S 22 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT53_MASK___M 0x00200000 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT53_MASK___S 21 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT52_MASK___M 0x00100000 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT52_MASK___S 20 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT51_MASK___M 0x00080000 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT51_MASK___S 19 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT50_MASK___M 0x00040000 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT50_MASK___S 18 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT49_MASK___M 0x00020000 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT49_MASK___S 17 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT48_MASK___M 0x00010000 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT48_MASK___S 16 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT47_MASK___M 0x00008000 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT47_MASK___S 15 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT46_MASK___M 0x00004000 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT46_MASK___S 14 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT45_MASK___M 0x00002000 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT45_MASK___S 13 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT44_MASK___M 0x00001000 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT44_MASK___S 12 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT43_MASK___M 0x00000800 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT43_MASK___S 11 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT42_MASK___M 0x00000400 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT42_MASK___S 10 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT41_MASK___M 0x00000200 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT41_MASK___S 9 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT40_MASK___M 0x00000100 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT40_MASK___S 8 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT39_MASK___M 0x00000080 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT39_MASK___S 7 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT38_MASK___M 0x00000040 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT38_MASK___S 6 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT37_MASK___M 0x00000020 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT37_MASK___S 5 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT36_MASK___M 0x00000010 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT36_MASK___S 4 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT35_MASK___M 0x00000008 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT35_MASK___S 3 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT34_MASK___M 0x00000004 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT34_MASK___S 2 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT33_MASK___M 0x00000002 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT33_MASK___S 1 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT32_MASK___M 0x00000001 +#define DBG_CSR_INTR_ANY_MASK1__INTR_BIT32_MASK___S 0 +#define DBG_CSR_INTR_ANY_MASK1___M 0xFFFFFFFF +#define DBG_CSR_INTR_ANY_MASK1___S 0 + +#define DBG_CSR_INTR_ANY_MASK2 (0x00B918C8) +#define DBG_CSR_INTR_ANY_MASK2___RWC QCSR_REG_RW +#define DBG_CSR_INTR_ANY_MASK2___POR 0xFFFFFFFF +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT95_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT94_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT93_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT92_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT91_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT90_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT89_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT88_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT87_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT86_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT85_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT84_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT83_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT82_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT81_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT80_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT79_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT78_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT77_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT76_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT75_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT74_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT73_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT72_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT71_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT70_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT69_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT68_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT67_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT66_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT65_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT64_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT95_MASK___M 0x80000000 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT95_MASK___S 31 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT94_MASK___M 0x40000000 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT94_MASK___S 30 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT93_MASK___M 0x20000000 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT93_MASK___S 29 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT92_MASK___M 0x10000000 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT92_MASK___S 28 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT91_MASK___M 0x08000000 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT91_MASK___S 27 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT90_MASK___M 0x04000000 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT90_MASK___S 26 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT89_MASK___M 0x02000000 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT89_MASK___S 25 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT88_MASK___M 0x01000000 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT88_MASK___S 24 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT87_MASK___M 0x00800000 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT87_MASK___S 23 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT86_MASK___M 0x00400000 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT86_MASK___S 22 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT85_MASK___M 0x00200000 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT85_MASK___S 21 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT84_MASK___M 0x00100000 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT84_MASK___S 20 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT83_MASK___M 0x00080000 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT83_MASK___S 19 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT82_MASK___M 0x00040000 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT82_MASK___S 18 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT81_MASK___M 0x00020000 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT81_MASK___S 17 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT80_MASK___M 0x00010000 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT80_MASK___S 16 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT79_MASK___M 0x00008000 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT79_MASK___S 15 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT78_MASK___M 0x00004000 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT78_MASK___S 14 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT77_MASK___M 0x00002000 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT77_MASK___S 13 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT76_MASK___M 0x00001000 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT76_MASK___S 12 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT75_MASK___M 0x00000800 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT75_MASK___S 11 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT74_MASK___M 0x00000400 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT74_MASK___S 10 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT73_MASK___M 0x00000200 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT73_MASK___S 9 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT72_MASK___M 0x00000100 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT72_MASK___S 8 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT71_MASK___M 0x00000080 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT71_MASK___S 7 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT70_MASK___M 0x00000040 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT70_MASK___S 6 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT69_MASK___M 0x00000020 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT69_MASK___S 5 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT68_MASK___M 0x00000010 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT68_MASK___S 4 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT67_MASK___M 0x00000008 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT67_MASK___S 3 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT66_MASK___M 0x00000004 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT66_MASK___S 2 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT65_MASK___M 0x00000002 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT65_MASK___S 1 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT64_MASK___M 0x00000001 +#define DBG_CSR_INTR_ANY_MASK2__INTR_BIT64_MASK___S 0 +#define DBG_CSR_INTR_ANY_MASK2___M 0xFFFFFFFF +#define DBG_CSR_INTR_ANY_MASK2___S 0 + +#define DBG_CSR_INTR_ANY_MASK3 (0x00B918CC) +#define DBG_CSR_INTR_ANY_MASK3___RWC QCSR_REG_RW +#define DBG_CSR_INTR_ANY_MASK3___POR 0xFFFFFFFF +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT127_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT126_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT125_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT124_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT123_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT122_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT121_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT120_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT119_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT118_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT117_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT116_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT115_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT114_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT113_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT112_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT111_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT110_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT109_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT108_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT107_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT106_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT105_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT104_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT103_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT102_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT101_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT100_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT99_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT98_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT97_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT96_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT127_MASK___M 0x80000000 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT127_MASK___S 31 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT126_MASK___M 0x40000000 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT126_MASK___S 30 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT125_MASK___M 0x20000000 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT125_MASK___S 29 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT124_MASK___M 0x10000000 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT124_MASK___S 28 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT123_MASK___M 0x08000000 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT123_MASK___S 27 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT122_MASK___M 0x04000000 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT122_MASK___S 26 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT121_MASK___M 0x02000000 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT121_MASK___S 25 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT120_MASK___M 0x01000000 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT120_MASK___S 24 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT119_MASK___M 0x00800000 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT119_MASK___S 23 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT118_MASK___M 0x00400000 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT118_MASK___S 22 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT117_MASK___M 0x00200000 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT117_MASK___S 21 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT116_MASK___M 0x00100000 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT116_MASK___S 20 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT115_MASK___M 0x00080000 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT115_MASK___S 19 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT114_MASK___M 0x00040000 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT114_MASK___S 18 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT113_MASK___M 0x00020000 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT113_MASK___S 17 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT112_MASK___M 0x00010000 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT112_MASK___S 16 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT111_MASK___M 0x00008000 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT111_MASK___S 15 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT110_MASK___M 0x00004000 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT110_MASK___S 14 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT109_MASK___M 0x00002000 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT109_MASK___S 13 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT108_MASK___M 0x00001000 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT108_MASK___S 12 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT107_MASK___M 0x00000800 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT107_MASK___S 11 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT106_MASK___M 0x00000400 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT106_MASK___S 10 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT105_MASK___M 0x00000200 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT105_MASK___S 9 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT104_MASK___M 0x00000100 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT104_MASK___S 8 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT103_MASK___M 0x00000080 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT103_MASK___S 7 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT102_MASK___M 0x00000040 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT102_MASK___S 6 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT101_MASK___M 0x00000020 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT101_MASK___S 5 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT100_MASK___M 0x00000010 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT100_MASK___S 4 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT99_MASK___M 0x00000008 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT99_MASK___S 3 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT98_MASK___M 0x00000004 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT98_MASK___S 2 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT97_MASK___M 0x00000002 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT97_MASK___S 1 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT96_MASK___M 0x00000001 +#define DBG_CSR_INTR_ANY_MASK3__INTR_BIT96_MASK___S 0 +#define DBG_CSR_INTR_ANY_MASK3___M 0xFFFFFFFF +#define DBG_CSR_INTR_ANY_MASK3___S 0 + +#define DBG_CSR_INTR_ANY_MASK4 (0x00B918D0) +#define DBG_CSR_INTR_ANY_MASK4___RWC QCSR_REG_RW +#define DBG_CSR_INTR_ANY_MASK4___POR 0xFFFFFFFF +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT159_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT158_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT157_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT156_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT155_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT154_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT153_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT152_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT151_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT150_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT149_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT148_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT147_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT146_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT145_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT144_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT143_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT142_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT141_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT140_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT139_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT138_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT137_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT136_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT135_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT134_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT133_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT132_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT131_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT130_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT129_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT128_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT159_MASK___M 0x80000000 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT159_MASK___S 31 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT158_MASK___M 0x40000000 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT158_MASK___S 30 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT157_MASK___M 0x20000000 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT157_MASK___S 29 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT156_MASK___M 0x10000000 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT156_MASK___S 28 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT155_MASK___M 0x08000000 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT155_MASK___S 27 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT154_MASK___M 0x04000000 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT154_MASK___S 26 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT153_MASK___M 0x02000000 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT153_MASK___S 25 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT152_MASK___M 0x01000000 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT152_MASK___S 24 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT151_MASK___M 0x00800000 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT151_MASK___S 23 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT150_MASK___M 0x00400000 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT150_MASK___S 22 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT149_MASK___M 0x00200000 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT149_MASK___S 21 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT148_MASK___M 0x00100000 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT148_MASK___S 20 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT147_MASK___M 0x00080000 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT147_MASK___S 19 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT146_MASK___M 0x00040000 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT146_MASK___S 18 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT145_MASK___M 0x00020000 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT145_MASK___S 17 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT144_MASK___M 0x00010000 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT144_MASK___S 16 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT143_MASK___M 0x00008000 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT143_MASK___S 15 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT142_MASK___M 0x00004000 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT142_MASK___S 14 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT141_MASK___M 0x00002000 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT141_MASK___S 13 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT140_MASK___M 0x00001000 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT140_MASK___S 12 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT139_MASK___M 0x00000800 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT139_MASK___S 11 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT138_MASK___M 0x00000400 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT138_MASK___S 10 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT137_MASK___M 0x00000200 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT137_MASK___S 9 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT136_MASK___M 0x00000100 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT136_MASK___S 8 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT135_MASK___M 0x00000080 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT135_MASK___S 7 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT134_MASK___M 0x00000040 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT134_MASK___S 6 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT133_MASK___M 0x00000020 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT133_MASK___S 5 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT132_MASK___M 0x00000010 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT132_MASK___S 4 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT131_MASK___M 0x00000008 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT131_MASK___S 3 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT130_MASK___M 0x00000004 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT130_MASK___S 2 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT129_MASK___M 0x00000002 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT129_MASK___S 1 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT128_MASK___M 0x00000001 +#define DBG_CSR_INTR_ANY_MASK4__INTR_BIT128_MASK___S 0 +#define DBG_CSR_INTR_ANY_MASK4___M 0xFFFFFFFF +#define DBG_CSR_INTR_ANY_MASK4___S 0 + +#define DBG_CSR_INTR_ANY_MASK5 (0x00B918D4) +#define DBG_CSR_INTR_ANY_MASK5___RWC QCSR_REG_RW +#define DBG_CSR_INTR_ANY_MASK5___POR 0xFFFFFFFF +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT191_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT190_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT189_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT188_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT187_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT186_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT185_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT184_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT183_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT182_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT181_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT180_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT179_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT178_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT177_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT176_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT175_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT174_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT173_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT172_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT171_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT170_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT169_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT168_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT167_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT166_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT165_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT164_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT163_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT162_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT161_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT160_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT191_MASK___M 0x80000000 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT191_MASK___S 31 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT190_MASK___M 0x40000000 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT190_MASK___S 30 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT189_MASK___M 0x20000000 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT189_MASK___S 29 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT188_MASK___M 0x10000000 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT188_MASK___S 28 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT187_MASK___M 0x08000000 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT187_MASK___S 27 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT186_MASK___M 0x04000000 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT186_MASK___S 26 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT185_MASK___M 0x02000000 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT185_MASK___S 25 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT184_MASK___M 0x01000000 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT184_MASK___S 24 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT183_MASK___M 0x00800000 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT183_MASK___S 23 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT182_MASK___M 0x00400000 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT182_MASK___S 22 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT181_MASK___M 0x00200000 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT181_MASK___S 21 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT180_MASK___M 0x00100000 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT180_MASK___S 20 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT179_MASK___M 0x00080000 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT179_MASK___S 19 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT178_MASK___M 0x00040000 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT178_MASK___S 18 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT177_MASK___M 0x00020000 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT177_MASK___S 17 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT176_MASK___M 0x00010000 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT176_MASK___S 16 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT175_MASK___M 0x00008000 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT175_MASK___S 15 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT174_MASK___M 0x00004000 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT174_MASK___S 14 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT173_MASK___M 0x00002000 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT173_MASK___S 13 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT172_MASK___M 0x00001000 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT172_MASK___S 12 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT171_MASK___M 0x00000800 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT171_MASK___S 11 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT170_MASK___M 0x00000400 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT170_MASK___S 10 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT169_MASK___M 0x00000200 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT169_MASK___S 9 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT168_MASK___M 0x00000100 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT168_MASK___S 8 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT167_MASK___M 0x00000080 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT167_MASK___S 7 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT166_MASK___M 0x00000040 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT166_MASK___S 6 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT165_MASK___M 0x00000020 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT165_MASK___S 5 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT164_MASK___M 0x00000010 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT164_MASK___S 4 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT163_MASK___M 0x00000008 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT163_MASK___S 3 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT162_MASK___M 0x00000004 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT162_MASK___S 2 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT161_MASK___M 0x00000002 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT161_MASK___S 1 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT160_MASK___M 0x00000001 +#define DBG_CSR_INTR_ANY_MASK5__INTR_BIT160_MASK___S 0 +#define DBG_CSR_INTR_ANY_MASK5___M 0xFFFFFFFF +#define DBG_CSR_INTR_ANY_MASK5___S 0 + +#define DBG_CSR_INTR_ANY_MASK6 (0x00B918D8) +#define DBG_CSR_INTR_ANY_MASK6___RWC QCSR_REG_RW +#define DBG_CSR_INTR_ANY_MASK6___POR 0xFFFFFFFF +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT223_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT222_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT221_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT220_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT219_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT218_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT217_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT216_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT215_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT214_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT213_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT212_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT211_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT210_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT209_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT208_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT207_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT206_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT205_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT204_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT203_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT202_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT201_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT200_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT199_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT198_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT197_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT196_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT195_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT194_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT193_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT192_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT223_MASK___M 0x80000000 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT223_MASK___S 31 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT222_MASK___M 0x40000000 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT222_MASK___S 30 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT221_MASK___M 0x20000000 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT221_MASK___S 29 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT220_MASK___M 0x10000000 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT220_MASK___S 28 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT219_MASK___M 0x08000000 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT219_MASK___S 27 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT218_MASK___M 0x04000000 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT218_MASK___S 26 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT217_MASK___M 0x02000000 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT217_MASK___S 25 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT216_MASK___M 0x01000000 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT216_MASK___S 24 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT215_MASK___M 0x00800000 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT215_MASK___S 23 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT214_MASK___M 0x00400000 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT214_MASK___S 22 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT213_MASK___M 0x00200000 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT213_MASK___S 21 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT212_MASK___M 0x00100000 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT212_MASK___S 20 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT211_MASK___M 0x00080000 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT211_MASK___S 19 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT210_MASK___M 0x00040000 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT210_MASK___S 18 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT209_MASK___M 0x00020000 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT209_MASK___S 17 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT208_MASK___M 0x00010000 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT208_MASK___S 16 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT207_MASK___M 0x00008000 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT207_MASK___S 15 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT206_MASK___M 0x00004000 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT206_MASK___S 14 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT205_MASK___M 0x00002000 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT205_MASK___S 13 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT204_MASK___M 0x00001000 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT204_MASK___S 12 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT203_MASK___M 0x00000800 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT203_MASK___S 11 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT202_MASK___M 0x00000400 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT202_MASK___S 10 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT201_MASK___M 0x00000200 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT201_MASK___S 9 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT200_MASK___M 0x00000100 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT200_MASK___S 8 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT199_MASK___M 0x00000080 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT199_MASK___S 7 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT198_MASK___M 0x00000040 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT198_MASK___S 6 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT197_MASK___M 0x00000020 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT197_MASK___S 5 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT196_MASK___M 0x00000010 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT196_MASK___S 4 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT195_MASK___M 0x00000008 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT195_MASK___S 3 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT194_MASK___M 0x00000004 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT194_MASK___S 2 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT193_MASK___M 0x00000002 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT193_MASK___S 1 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT192_MASK___M 0x00000001 +#define DBG_CSR_INTR_ANY_MASK6__INTR_BIT192_MASK___S 0 +#define DBG_CSR_INTR_ANY_MASK6___M 0xFFFFFFFF +#define DBG_CSR_INTR_ANY_MASK6___S 0 + +#define DBG_CSR_INTR_ANY_MASK7 (0x00B918DC) +#define DBG_CSR_INTR_ANY_MASK7___RWC QCSR_REG_RW +#define DBG_CSR_INTR_ANY_MASK7___POR 0xFFFFFFFF +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT255_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT254_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT253_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT252_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT251_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT250_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT249_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT248_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT247_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT246_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT245_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT244_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT243_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT242_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT241_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT240_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT239_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT238_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT237_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT236_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT235_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT234_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT233_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT232_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT231_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT230_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT229_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT228_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT227_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT226_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT225_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT224_MASK___POR 0x1 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT255_MASK___M 0x80000000 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT255_MASK___S 31 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT254_MASK___M 0x40000000 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT254_MASK___S 30 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT253_MASK___M 0x20000000 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT253_MASK___S 29 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT252_MASK___M 0x10000000 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT252_MASK___S 28 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT251_MASK___M 0x08000000 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT251_MASK___S 27 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT250_MASK___M 0x04000000 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT250_MASK___S 26 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT249_MASK___M 0x02000000 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT249_MASK___S 25 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT248_MASK___M 0x01000000 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT248_MASK___S 24 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT247_MASK___M 0x00800000 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT247_MASK___S 23 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT246_MASK___M 0x00400000 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT246_MASK___S 22 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT245_MASK___M 0x00200000 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT245_MASK___S 21 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT244_MASK___M 0x00100000 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT244_MASK___S 20 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT243_MASK___M 0x00080000 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT243_MASK___S 19 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT242_MASK___M 0x00040000 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT242_MASK___S 18 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT241_MASK___M 0x00020000 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT241_MASK___S 17 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT240_MASK___M 0x00010000 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT240_MASK___S 16 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT239_MASK___M 0x00008000 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT239_MASK___S 15 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT238_MASK___M 0x00004000 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT238_MASK___S 14 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT237_MASK___M 0x00002000 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT237_MASK___S 13 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT236_MASK___M 0x00001000 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT236_MASK___S 12 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT235_MASK___M 0x00000800 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT235_MASK___S 11 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT234_MASK___M 0x00000400 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT234_MASK___S 10 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT233_MASK___M 0x00000200 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT233_MASK___S 9 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT232_MASK___M 0x00000100 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT232_MASK___S 8 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT231_MASK___M 0x00000080 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT231_MASK___S 7 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT230_MASK___M 0x00000040 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT230_MASK___S 6 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT229_MASK___M 0x00000020 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT229_MASK___S 5 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT228_MASK___M 0x00000010 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT228_MASK___S 4 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT227_MASK___M 0x00000008 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT227_MASK___S 3 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT226_MASK___M 0x00000004 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT226_MASK___S 2 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT225_MASK___M 0x00000002 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT225_MASK___S 1 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT224_MASK___M 0x00000001 +#define DBG_CSR_INTR_ANY_MASK7__INTR_BIT224_MASK___S 0 +#define DBG_CSR_INTR_ANY_MASK7___M 0xFFFFFFFF +#define DBG_CSR_INTR_ANY_MASK7___S 0 + +#define DBG_CSR_CS_ITCTL (0x00B91F00) +#define DBG_CSR_CS_ITCTL___RWC QCSR_REG_RO +#define DBG_CSR_CS_ITCTL___POR 0x00000000 +#define DBG_CSR_CS_ITCTL__RFU___POR 0x00000000 +#define DBG_CSR_CS_ITCTL__RFU___M 0xFFFFFFFF +#define DBG_CSR_CS_ITCTL__RFU___S 0 +#define DBG_CSR_CS_ITCTL___M 0xFFFFFFFF +#define DBG_CSR_CS_ITCTL___S 0 + +#define DBG_CSR_CS_CLAIMSET (0x00B91FA0) +#define DBG_CSR_CS_CLAIMSET___RWC QCSR_REG_RO +#define DBG_CSR_CS_CLAIMSET___POR 0x00000000 +#define DBG_CSR_CS_CLAIMSET__RFU___POR 0x00000000 +#define DBG_CSR_CS_CLAIMSET__RFU___M 0xFFFFFFFF +#define DBG_CSR_CS_CLAIMSET__RFU___S 0 +#define DBG_CSR_CS_CLAIMSET___M 0xFFFFFFFF +#define DBG_CSR_CS_CLAIMSET___S 0 + +#define DBG_CSR_CS_CLAIMCLR (0x00B91FA4) +#define DBG_CSR_CS_CLAIMCLR___RWC QCSR_REG_RO +#define DBG_CSR_CS_CLAIMCLR___POR 0x00000000 +#define DBG_CSR_CS_CLAIMCLR__RFU___POR 0x00000000 +#define DBG_CSR_CS_CLAIMCLR__RFU___M 0xFFFFFFFF +#define DBG_CSR_CS_CLAIMCLR__RFU___S 0 +#define DBG_CSR_CS_CLAIMCLR___M 0xFFFFFFFF +#define DBG_CSR_CS_CLAIMCLR___S 0 + +#define DBG_CSR_CS_LOCKACCESS (0x00B91FB0) +#define DBG_CSR_CS_LOCKACCESS___RWC QCSR_REG_RO +#define DBG_CSR_CS_LOCKACCESS___POR 0x00000000 +#define DBG_CSR_CS_LOCKACCESS__RFU___POR 0x00000000 +#define DBG_CSR_CS_LOCKACCESS__RFU___M 0xFFFFFFFF +#define DBG_CSR_CS_LOCKACCESS__RFU___S 0 +#define DBG_CSR_CS_LOCKACCESS___M 0xFFFFFFFF +#define DBG_CSR_CS_LOCKACCESS___S 0 + +#define DBG_CSR_CS_LOCKSTATUS (0x00B91FB4) +#define DBG_CSR_CS_LOCKSTATUS___RWC QCSR_REG_RO +#define DBG_CSR_CS_LOCKSTATUS___POR 0x00000000 +#define DBG_CSR_CS_LOCKSTATUS__RFU___POR 0x00000000 +#define DBG_CSR_CS_LOCKSTATUS__RFU___M 0xFFFFFFFF +#define DBG_CSR_CS_LOCKSTATUS__RFU___S 0 +#define DBG_CSR_CS_LOCKSTATUS___M 0xFFFFFFFF +#define DBG_CSR_CS_LOCKSTATUS___S 0 + +#define DBG_CSR_CS_AUTHSTATUS (0x00B91FB8) +#define DBG_CSR_CS_AUTHSTATUS___RWC QCSR_REG_RO +#define DBG_CSR_CS_AUTHSTATUS___POR 0x00000000 +#define DBG_CSR_CS_AUTHSTATUS__SI___POR 0x0 +#define DBG_CSR_CS_AUTHSTATUS__NSI___POR 0x0 +#define DBG_CSR_CS_AUTHSTATUS__SNI___POR 0x0 +#define DBG_CSR_CS_AUTHSTATUS__NSNI___POR 0x0 +#define DBG_CSR_CS_AUTHSTATUS__SI___M 0x000000C0 +#define DBG_CSR_CS_AUTHSTATUS__SI___S 6 +#define DBG_CSR_CS_AUTHSTATUS__NSI___M 0x00000030 +#define DBG_CSR_CS_AUTHSTATUS__NSI___S 4 +#define DBG_CSR_CS_AUTHSTATUS__SNI___M 0x0000000C +#define DBG_CSR_CS_AUTHSTATUS__SNI___S 2 +#define DBG_CSR_CS_AUTHSTATUS__NSNI___M 0x00000003 +#define DBG_CSR_CS_AUTHSTATUS__NSNI___S 0 +#define DBG_CSR_CS_AUTHSTATUS___M 0x000000FF +#define DBG_CSR_CS_AUTHSTATUS___S 0 + +#define DBG_CSR_CS_DEVARCH (0x00B91FBC) +#define DBG_CSR_CS_DEVARCH___RWC QCSR_REG_RO +#define DBG_CSR_CS_DEVARCH___POR 0x0E100000 +#define DBG_CSR_CS_DEVARCH__ARCHITECT___POR 0x070 +#define DBG_CSR_CS_DEVARCH__PRESENT___POR 0x1 +#define DBG_CSR_CS_DEVARCH__REVISION___POR 0x0 +#define DBG_CSR_CS_DEVARCH__ARCHID___POR 0x0000 +#define DBG_CSR_CS_DEVARCH__ARCHITECT___M 0xFFE00000 +#define DBG_CSR_CS_DEVARCH__ARCHITECT___S 21 +#define DBG_CSR_CS_DEVARCH__PRESENT___M 0x00100000 +#define DBG_CSR_CS_DEVARCH__PRESENT___S 20 +#define DBG_CSR_CS_DEVARCH__REVISION___M 0x000F0000 +#define DBG_CSR_CS_DEVARCH__REVISION___S 16 +#define DBG_CSR_CS_DEVARCH__ARCHID___M 0x0000FFFF +#define DBG_CSR_CS_DEVARCH__ARCHID___S 0 +#define DBG_CSR_CS_DEVARCH___M 0xFFFFFFFF +#define DBG_CSR_CS_DEVARCH___S 0 + +#define DBG_CSR_CS_DEVID2 (0x00B91FC0) +#define DBG_CSR_CS_DEVID2___RWC QCSR_REG_RO +#define DBG_CSR_CS_DEVID2___POR 0x00000000 +#define DBG_CSR_CS_DEVID2__IMPLDEF___POR 0x0 +#define DBG_CSR_CS_DEVID2__IMPLDEF___M 0x00000001 +#define DBG_CSR_CS_DEVID2__IMPLDEF___S 0 +#define DBG_CSR_CS_DEVID2___M 0x00000001 +#define DBG_CSR_CS_DEVID2___S 0 + +#define DBG_CSR_CS_DEVID1 (0x00B91FC4) +#define DBG_CSR_CS_DEVID1___RWC QCSR_REG_RO +#define DBG_CSR_CS_DEVID1___POR 0x00000000 +#define DBG_CSR_CS_DEVID1__IMPLDEF___POR 0x0 +#define DBG_CSR_CS_DEVID1__IMPLDEF___M 0x00000001 +#define DBG_CSR_CS_DEVID1__IMPLDEF___S 0 +#define DBG_CSR_CS_DEVID1___M 0x00000001 +#define DBG_CSR_CS_DEVID1___S 0 + +#define DBG_CSR_CS_DEVICEID (0x00B91FC8) +#define DBG_CSR_CS_DEVICEID___RWC QCSR_REG_RO +#define DBG_CSR_CS_DEVICEID___POR 0x00000000 +#define DBG_CSR_CS_DEVICEID__RFU___POR 0x000000 +#define DBG_CSR_CS_DEVICEID__DEVID___POR 0x00 +#define DBG_CSR_CS_DEVICEID__RFU___M 0xFFFFFF00 +#define DBG_CSR_CS_DEVICEID__RFU___S 8 +#define DBG_CSR_CS_DEVICEID__DEVID___M 0x000000FF +#define DBG_CSR_CS_DEVICEID__DEVID___S 0 +#define DBG_CSR_CS_DEVICEID___M 0xFFFFFFFF +#define DBG_CSR_CS_DEVICEID___S 0 + +#define DBG_CSR_CS_DEVICETYPE (0x00B91FCC) +#define DBG_CSR_CS_DEVICETYPE___RWC QCSR_REG_RO +#define DBG_CSR_CS_DEVICETYPE___POR 0x00000004 +#define DBG_CSR_CS_DEVICETYPE__RFU___POR 0x000000 +#define DBG_CSR_CS_DEVICETYPE__SUBTYPE___POR 0x0 +#define DBG_CSR_CS_DEVICETYPE__MAJTYPE___POR 0x4 +#define DBG_CSR_CS_DEVICETYPE__RFU___M 0xFFFFFF00 +#define DBG_CSR_CS_DEVICETYPE__RFU___S 8 +#define DBG_CSR_CS_DEVICETYPE__SUBTYPE___M 0x000000F0 +#define DBG_CSR_CS_DEVICETYPE__SUBTYPE___S 4 +#define DBG_CSR_CS_DEVICETYPE__MAJTYPE___M 0x0000000F +#define DBG_CSR_CS_DEVICETYPE__MAJTYPE___S 0 +#define DBG_CSR_CS_DEVICETYPE___M 0xFFFFFFFF +#define DBG_CSR_CS_DEVICETYPE___S 0 + +#define DBG_CSR_CS_PERIPHID4 (0x00B91FD0) +#define DBG_CSR_CS_PERIPHID4___RWC QCSR_REG_RO +#define DBG_CSR_CS_PERIPHID4___POR 0x00000000 +#define DBG_CSR_CS_PERIPHID4__RFU___POR 0x000000 +#define DBG_CSR_CS_PERIPHID4__FIELD_4KB_COUNT___POR 0x0 +#define DBG_CSR_CS_PERIPHID4__JEP106_CONTINUATION___POR 0x0 +#define DBG_CSR_CS_PERIPHID4__RFU___M 0xFFFFFF00 +#define DBG_CSR_CS_PERIPHID4__RFU___S 8 +#define DBG_CSR_CS_PERIPHID4__FIELD_4KB_COUNT___M 0x000000F0 +#define DBG_CSR_CS_PERIPHID4__FIELD_4KB_COUNT___S 4 +#define DBG_CSR_CS_PERIPHID4__JEP106_CONTINUATION___M 0x0000000F +#define DBG_CSR_CS_PERIPHID4__JEP106_CONTINUATION___S 0 +#define DBG_CSR_CS_PERIPHID4___M 0xFFFFFFFF +#define DBG_CSR_CS_PERIPHID4___S 0 + +#define DBG_CSR_CS_PERIPHID5 (0x00B91FD4) +#define DBG_CSR_CS_PERIPHID5___RWC QCSR_REG_RO +#define DBG_CSR_CS_PERIPHID5___POR 0x00000000 +#define DBG_CSR_CS_PERIPHID5__RFU___POR 0x00000000 +#define DBG_CSR_CS_PERIPHID5__RFU___M 0xFFFFFFFF +#define DBG_CSR_CS_PERIPHID5__RFU___S 0 +#define DBG_CSR_CS_PERIPHID5___M 0xFFFFFFFF +#define DBG_CSR_CS_PERIPHID5___S 0 + +#define DBG_CSR_CS_PERIPHID6 (0x00B91FD8) +#define DBG_CSR_CS_PERIPHID6___RWC QCSR_REG_RO +#define DBG_CSR_CS_PERIPHID6___POR 0x00000000 +#define DBG_CSR_CS_PERIPHID6__RFU___POR 0x00000000 +#define DBG_CSR_CS_PERIPHID6__RFU___M 0xFFFFFFFF +#define DBG_CSR_CS_PERIPHID6__RFU___S 0 +#define DBG_CSR_CS_PERIPHID6___M 0xFFFFFFFF +#define DBG_CSR_CS_PERIPHID6___S 0 + +#define DBG_CSR_CS_PERIPHID7 (0x00B91FDC) +#define DBG_CSR_CS_PERIPHID7___RWC QCSR_REG_RO +#define DBG_CSR_CS_PERIPHID7___POR 0x00000000 +#define DBG_CSR_CS_PERIPHID7__RFU___POR 0x00000000 +#define DBG_CSR_CS_PERIPHID7__RFU___M 0xFFFFFFFF +#define DBG_CSR_CS_PERIPHID7__RFU___S 0 +#define DBG_CSR_CS_PERIPHID7___M 0xFFFFFFFF +#define DBG_CSR_CS_PERIPHID7___S 0 + +#define DBG_CSR_CS_PERIPHID0 (0x00B91FE0) +#define DBG_CSR_CS_PERIPHID0___RWC QCSR_REG_RO +#define DBG_CSR_CS_PERIPHID0___POR 0x00000000 +#define DBG_CSR_CS_PERIPHID0__RFU___POR 0x000000 +#define DBG_CSR_CS_PERIPHID0__PARTNUM_7_0___POR 0x00 +#define DBG_CSR_CS_PERIPHID0__RFU___M 0xFFFFFF00 +#define DBG_CSR_CS_PERIPHID0__RFU___S 8 +#define DBG_CSR_CS_PERIPHID0__PARTNUM_7_0___M 0x000000FF +#define DBG_CSR_CS_PERIPHID0__PARTNUM_7_0___S 0 +#define DBG_CSR_CS_PERIPHID0___M 0xFFFFFFFF +#define DBG_CSR_CS_PERIPHID0___S 0 + +#define DBG_CSR_CS_PERIPHID1 (0x00B91FE4) +#define DBG_CSR_CS_PERIPHID1___RWC QCSR_REG_RO +#define DBG_CSR_CS_PERIPHID1___POR 0x00000004 +#define DBG_CSR_CS_PERIPHID1__RFU___POR 0x000000 +#define DBG_CSR_CS_PERIPHID1__JEP106_IDENTITY_3_0___POR 0x0 +#define DBG_CSR_CS_PERIPHID1__PARTNUM_11_8___POR 0x4 +#define DBG_CSR_CS_PERIPHID1__RFU___M 0xFFFFFF00 +#define DBG_CSR_CS_PERIPHID1__RFU___S 8 +#define DBG_CSR_CS_PERIPHID1__JEP106_IDENTITY_3_0___M 0x000000F0 +#define DBG_CSR_CS_PERIPHID1__JEP106_IDENTITY_3_0___S 4 +#define DBG_CSR_CS_PERIPHID1__PARTNUM_11_8___M 0x0000000F +#define DBG_CSR_CS_PERIPHID1__PARTNUM_11_8___S 0 +#define DBG_CSR_CS_PERIPHID1___M 0xFFFFFFFF +#define DBG_CSR_CS_PERIPHID1___S 0 + +#define DBG_CSR_CS_PERIPHID2 (0x00B91FE8) +#define DBG_CSR_CS_PERIPHID2___RWC QCSR_REG_RO +#define DBG_CSR_CS_PERIPHID2___POR 0x00000018 +#define DBG_CSR_CS_PERIPHID2__RFU___POR 0x000000 +#define DBG_CSR_CS_PERIPHID2__MAJREV___POR 0x1 +#define DBG_CSR_CS_PERIPHID2__JEDEC___POR 0x1 +#define DBG_CSR_CS_PERIPHID2__JEP106_IDENTITY_6_4___POR 0x0 +#define DBG_CSR_CS_PERIPHID2__RFU___M 0xFFFFFF00 +#define DBG_CSR_CS_PERIPHID2__RFU___S 8 +#define DBG_CSR_CS_PERIPHID2__MAJREV___M 0x000000F0 +#define DBG_CSR_CS_PERIPHID2__MAJREV___S 4 +#define DBG_CSR_CS_PERIPHID2__JEDEC___M 0x00000008 +#define DBG_CSR_CS_PERIPHID2__JEDEC___S 3 +#define DBG_CSR_CS_PERIPHID2__JEP106_IDENTITY_6_4___M 0x00000007 +#define DBG_CSR_CS_PERIPHID2__JEP106_IDENTITY_6_4___S 0 +#define DBG_CSR_CS_PERIPHID2___M 0xFFFFFFFF +#define DBG_CSR_CS_PERIPHID2___S 0 + +#define DBG_CSR_CS_PERIPHID3 (0x00B91FEC) +#define DBG_CSR_CS_PERIPHID3___RWC QCSR_REG_RO +#define DBG_CSR_CS_PERIPHID3___POR 0x00000000 +#define DBG_CSR_CS_PERIPHID3__RFU___POR 0x000000 +#define DBG_CSR_CS_PERIPHID3__REV_AND___POR 0x0 +#define DBG_CSR_CS_PERIPHID3__CUSTOMER_MODIFIED___POR 0x0 +#define DBG_CSR_CS_PERIPHID3__RFU___M 0xFFFFFF00 +#define DBG_CSR_CS_PERIPHID3__RFU___S 8 +#define DBG_CSR_CS_PERIPHID3__REV_AND___M 0x000000F0 +#define DBG_CSR_CS_PERIPHID3__REV_AND___S 4 +#define DBG_CSR_CS_PERIPHID3__CUSTOMER_MODIFIED___M 0x0000000F +#define DBG_CSR_CS_PERIPHID3__CUSTOMER_MODIFIED___S 0 +#define DBG_CSR_CS_PERIPHID3___M 0xFFFFFFFF +#define DBG_CSR_CS_PERIPHID3___S 0 + +#define DBG_CSR_CS_COMPID0 (0x00B91FF0) +#define DBG_CSR_CS_COMPID0___RWC QCSR_REG_RO +#define DBG_CSR_CS_COMPID0___POR 0x0000000D +#define DBG_CSR_CS_COMPID0__RFU___POR 0x000000 +#define DBG_CSR_CS_COMPID0__PREAMBLE_7_0___POR 0x0D +#define DBG_CSR_CS_COMPID0__RFU___M 0xFFFFFF00 +#define DBG_CSR_CS_COMPID0__RFU___S 8 +#define DBG_CSR_CS_COMPID0__PREAMBLE_7_0___M 0x000000FF +#define DBG_CSR_CS_COMPID0__PREAMBLE_7_0___S 0 +#define DBG_CSR_CS_COMPID0___M 0xFFFFFFFF +#define DBG_CSR_CS_COMPID0___S 0 + +#define DBG_CSR_CS_COMPID1 (0x00B91FF4) +#define DBG_CSR_CS_COMPID1___RWC QCSR_REG_RO +#define DBG_CSR_CS_COMPID1___POR 0x00000090 +#define DBG_CSR_CS_COMPID1__RFU___POR 0x000000 +#define DBG_CSR_CS_COMPID1__PREAMBLE_15_12___POR 0x9 +#define DBG_CSR_CS_COMPID1__PREAMBLE_11_8___POR 0x0 +#define DBG_CSR_CS_COMPID1__RFU___M 0xFFFFFF00 +#define DBG_CSR_CS_COMPID1__RFU___S 8 +#define DBG_CSR_CS_COMPID1__PREAMBLE_15_12___M 0x000000F0 +#define DBG_CSR_CS_COMPID1__PREAMBLE_15_12___S 4 +#define DBG_CSR_CS_COMPID1__PREAMBLE_11_8___M 0x0000000F +#define DBG_CSR_CS_COMPID1__PREAMBLE_11_8___S 0 +#define DBG_CSR_CS_COMPID1___M 0xFFFFFFFF +#define DBG_CSR_CS_COMPID1___S 0 + +#define DBG_CSR_CS_COMPID2 (0x00B91FF8) +#define DBG_CSR_CS_COMPID2___RWC QCSR_REG_RO +#define DBG_CSR_CS_COMPID2___POR 0x00000005 +#define DBG_CSR_CS_COMPID2__RFU___POR 0x000000 +#define DBG_CSR_CS_COMPID2__PREAMBLE_23_16___POR 0x05 +#define DBG_CSR_CS_COMPID2__RFU___M 0xFFFFFF00 +#define DBG_CSR_CS_COMPID2__RFU___S 8 +#define DBG_CSR_CS_COMPID2__PREAMBLE_23_16___M 0x000000FF +#define DBG_CSR_CS_COMPID2__PREAMBLE_23_16___S 0 +#define DBG_CSR_CS_COMPID2___M 0xFFFFFFFF +#define DBG_CSR_CS_COMPID2___S 0 + +#define DBG_CSR_CS_COMPID3 (0x00B91FFC) +#define DBG_CSR_CS_COMPID3___RWC QCSR_REG_RO +#define DBG_CSR_CS_COMPID3___POR 0x000000B1 +#define DBG_CSR_CS_COMPID3__RFU___POR 0x000000 +#define DBG_CSR_CS_COMPID3__PREAMBLE_31_24___POR 0xB1 +#define DBG_CSR_CS_COMPID3__RFU___M 0xFFFFFF00 +#define DBG_CSR_CS_COMPID3__RFU___S 8 +#define DBG_CSR_CS_COMPID3__PREAMBLE_31_24___M 0x000000FF +#define DBG_CSR_CS_COMPID3__PREAMBLE_31_24___S 0 +#define DBG_CSR_CS_COMPID3___M 0xFFFFFFFF +#define DBG_CSR_CS_COMPID3___S 0 + +#define DBG_TSGEN_CNTCR (0x00B92000) +#define DBG_TSGEN_CNTCR___RWC QCSR_REG_RW +#define DBG_TSGEN_CNTCR___POR 0x00000000 +#define DBG_TSGEN_CNTCR__CNTCR_HDBG___POR 0x0 +#define DBG_TSGEN_CNTCR__CNTCR_EN___POR 0x0 +#define DBG_TSGEN_CNTCR__CNTCR_HDBG___M 0x00000002 +#define DBG_TSGEN_CNTCR__CNTCR_HDBG___S 1 +#define DBG_TSGEN_CNTCR__CNTCR_HDBG__LOW 0x0 +#define DBG_TSGEN_CNTCR__CNTCR_HDBG__HIGH 0x1 +#define DBG_TSGEN_CNTCR__CNTCR_EN___M 0x00000001 +#define DBG_TSGEN_CNTCR__CNTCR_EN___S 0 +#define DBG_TSGEN_CNTCR__CNTCR_EN__LOW 0x0 +#define DBG_TSGEN_CNTCR__CNTCR_EN__HIGH 0x1 +#define DBG_TSGEN_CNTCR___M 0x00000003 +#define DBG_TSGEN_CNTCR___S 0 + +#define DBG_TSGEN_CNTSR (0x00B92004) +#define DBG_TSGEN_CNTSR___RWC QCSR_REG_RO +#define DBG_TSGEN_CNTSR___POR 0x00000000 +#define DBG_TSGEN_CNTSR__CNTSR_DBGH___POR 0x0 +#define DBG_TSGEN_CNTSR__CNTSR_DBGH___M 0x00000002 +#define DBG_TSGEN_CNTSR__CNTSR_DBGH___S 1 +#define DBG_TSGEN_CNTSR__CNTSR_DBGH__LOW 0x0 +#define DBG_TSGEN_CNTSR__CNTSR_DBGH__HIGH 0x1 +#define DBG_TSGEN_CNTSR___M 0x00000002 +#define DBG_TSGEN_CNTSR___S 1 + +#define DBG_TSGEN_CNTCVL (0x00B92008) +#define DBG_TSGEN_CNTCVL___RWC QCSR_REG_RW +#define DBG_TSGEN_CNTCVL___POR 0x00000000 +#define DBG_TSGEN_CNTCVL__CNTCVL_L_32___POR 0x00000000 +#define DBG_TSGEN_CNTCVL__CNTCVL_L_32___M 0xFFFFFFFF +#define DBG_TSGEN_CNTCVL__CNTCVL_L_32___S 0 +#define DBG_TSGEN_CNTCVL___M 0xFFFFFFFF +#define DBG_TSGEN_CNTCVL___S 0 + +#define DBG_TSGEN_CNTCVU (0x00B9200C) +#define DBG_TSGEN_CNTCVU___RWC QCSR_REG_RW +#define DBG_TSGEN_CNTCVU___POR 0x00000000 +#define DBG_TSGEN_CNTCVU__CNTCVU_U_32___POR 0x00000000 +#define DBG_TSGEN_CNTCVU__CNTCVU_U_32___M 0xFFFFFFFF +#define DBG_TSGEN_CNTCVU__CNTCVU_U_32___S 0 +#define DBG_TSGEN_CNTCVU___M 0xFFFFFFFF +#define DBG_TSGEN_CNTCVU___S 0 + +#define DBG_TSGEN_CNTFID0 (0x00B92020) +#define DBG_TSGEN_CNTFID0___RWC QCSR_REG_RW +#define DBG_TSGEN_CNTFID0___POR 0x00000000 +#define DBG_TSGEN_CNTFID0__CNTFID0___POR 0x00000000 +#define DBG_TSGEN_CNTFID0__CNTFID0___M 0xFFFFFFFF +#define DBG_TSGEN_CNTFID0__CNTFID0___S 0 +#define DBG_TSGEN_CNTFID0___M 0xFFFFFFFF +#define DBG_TSGEN_CNTFID0___S 0 + +#define DBG_TSGEN_PIDR0 (0x00B92FE0) +#define DBG_TSGEN_PIDR0___RWC QCSR_REG_RO +#define DBG_TSGEN_PIDR0___POR 0x00000001 +#define DBG_TSGEN_PIDR0__PART_0___POR 0x01 +#define DBG_TSGEN_PIDR0__PART_0___M 0x000000FF +#define DBG_TSGEN_PIDR0__PART_0___S 0 +#define DBG_TSGEN_PIDR0__PART_0__TIME_STAMP_GENERATOR_PART_NUMBER_BITS7TO0 0x01 +#define DBG_TSGEN_PIDR0___M 0x000000FF +#define DBG_TSGEN_PIDR0___S 0 + +#define DBG_TSGEN_PIDR1 (0x00B92FE4) +#define DBG_TSGEN_PIDR1___RWC QCSR_REG_RO +#define DBG_TSGEN_PIDR1___POR 0x000000B1 +#define DBG_TSGEN_PIDR1__DES_0___POR 0xB +#define DBG_TSGEN_PIDR1__PART_1___POR 0x1 +#define DBG_TSGEN_PIDR1__DES_0___M 0x000000F0 +#define DBG_TSGEN_PIDR1__DES_0___S 4 +#define DBG_TSGEN_PIDR1__DES_0__ARM_JEP106_IDENTITY_CODE_BITS7TO0 0xB +#define DBG_TSGEN_PIDR1__PART_1___M 0x0000000F +#define DBG_TSGEN_PIDR1__PART_1___S 0 +#define DBG_TSGEN_PIDR1__PART_1__TIME_STAMP_GENERATOR_PART_NUMBER_BITS11TO8 0x1 +#define DBG_TSGEN_PIDR1___M 0x000000FF +#define DBG_TSGEN_PIDR1___S 0 + +#define DBG_TSGEN_PIDR2 (0x00B92FE8) +#define DBG_TSGEN_PIDR2___RWC QCSR_REG_RO +#define DBG_TSGEN_PIDR2___POR 0x0000000B +#define DBG_TSGEN_PIDR2__REVISION___POR 0x0 +#define DBG_TSGEN_PIDR2__JEDEC___POR 0x1 +#define DBG_TSGEN_PIDR2__DES_1___POR 0x3 +#define DBG_TSGEN_PIDR2__REVISION___M 0x000000F0 +#define DBG_TSGEN_PIDR2__REVISION___S 4 +#define DBG_TSGEN_PIDR2__REVISION__R0P1 0x1 +#define DBG_TSGEN_PIDR2__JEDEC___M 0x00000008 +#define DBG_TSGEN_PIDR2__JEDEC___S 3 +#define DBG_TSGEN_PIDR2__JEDEC__JEDEC_IDENTITY 0x1 +#define DBG_TSGEN_PIDR2__DES_1___M 0x00000007 +#define DBG_TSGEN_PIDR2__DES_1___S 0 +#define DBG_TSGEN_PIDR2__DES_1__ARM_JEP106_IDENTITY_CODE_BITS6TO4 0x3 +#define DBG_TSGEN_PIDR2___M 0x000000FF +#define DBG_TSGEN_PIDR2___S 0 + +#define DBG_TSGEN_PIDR3 (0x00B92FEC) +#define DBG_TSGEN_PIDR3___RWC QCSR_REG_RO +#define DBG_TSGEN_PIDR3___POR 0x00000000 +#define DBG_TSGEN_PIDR3__REVAND___POR 0x0 +#define DBG_TSGEN_PIDR3__CMOD___POR 0x0 +#define DBG_TSGEN_PIDR3__REVAND___M 0x000000F0 +#define DBG_TSGEN_PIDR3__REVAND___S 4 +#define DBG_TSGEN_PIDR3__REVAND__NO_MODS 0x0 +#define DBG_TSGEN_PIDR3__CMOD___M 0x0000000F +#define DBG_TSGEN_PIDR3__CMOD___S 0 +#define DBG_TSGEN_PIDR3__CMOD__NO_MODS 0x0 +#define DBG_TSGEN_PIDR3___M 0x000000FF +#define DBG_TSGEN_PIDR3___S 0 + +#define DBG_TSGEN_PIDR4 (0x00B92FD0) +#define DBG_TSGEN_PIDR4___RWC QCSR_REG_RO +#define DBG_TSGEN_PIDR4___POR 0x00000004 +#define DBG_TSGEN_PIDR4__SIZE___POR 0x0 +#define DBG_TSGEN_PIDR4__DES_2___POR 0x4 +#define DBG_TSGEN_PIDR4__SIZE___M 0x000000F0 +#define DBG_TSGEN_PIDR4__SIZE___S 4 +#define DBG_TSGEN_PIDR4__SIZE__SIZE_4KB 0x0 +#define DBG_TSGEN_PIDR4__DES_2___M 0x0000000F +#define DBG_TSGEN_PIDR4__DES_2___S 0 +#define DBG_TSGEN_PIDR4__DES_2__ARM_JEP106_CONTINUATION_CODE 0x4 +#define DBG_TSGEN_PIDR4___M 0x000000FF +#define DBG_TSGEN_PIDR4___S 0 + +#define DBG_TSGEN_PIDR5 (0x00B92FD4) +#define DBG_TSGEN_PIDR5___RWC QCSR_REG_RW +#define DBG_TSGEN_PIDR5__PIDR5___M 0xFFFFFFFF +#define DBG_TSGEN_PIDR5__PIDR5___S 0 +#define DBG_TSGEN_PIDR5___M 0xFFFFFFFF +#define DBG_TSGEN_PIDR5___S 0 + +#define DBG_TSGEN_PIDR6 (0x00B92FD8) +#define DBG_TSGEN_PIDR6___RWC QCSR_REG_RW +#define DBG_TSGEN_PIDR6__PIDR6___M 0xFFFFFFFF +#define DBG_TSGEN_PIDR6__PIDR6___S 0 +#define DBG_TSGEN_PIDR6___M 0xFFFFFFFF +#define DBG_TSGEN_PIDR6___S 0 + +#define DBG_TSGEN_PIDR7 (0x00B92FDC) +#define DBG_TSGEN_PIDR7___RWC QCSR_REG_RW +#define DBG_TSGEN_PIDR7__PIDR7___M 0xFFFFFFFF +#define DBG_TSGEN_PIDR7__PIDR7___S 0 +#define DBG_TSGEN_PIDR7___M 0xFFFFFFFF +#define DBG_TSGEN_PIDR7___S 0 + +#define DBG_TSGEN_CIDR0 (0x00B92FF0) +#define DBG_TSGEN_CIDR0___RWC QCSR_REG_RO +#define DBG_TSGEN_CIDR0___POR 0x0000000D +#define DBG_TSGEN_CIDR0__PRMBL_0___POR 0x0D +#define DBG_TSGEN_CIDR0__PRMBL_0___M 0x000000FF +#define DBG_TSGEN_CIDR0__PRMBL_0___S 0 +#define DBG_TSGEN_CIDR0__PRMBL_0__ID_VALUE_0D 0x0D +#define DBG_TSGEN_CIDR0___M 0x000000FF +#define DBG_TSGEN_CIDR0___S 0 + +#define DBG_TSGEN_CIDR1 (0x00B92FF4) +#define DBG_TSGEN_CIDR1___RWC QCSR_REG_RO +#define DBG_TSGEN_CIDR1___POR 0x000000F0 +#define DBG_TSGEN_CIDR1__CLASS___POR 0xF +#define DBG_TSGEN_CIDR1__PRMBL_1___POR 0x0 +#define DBG_TSGEN_CIDR1__CLASS___M 0x000000F0 +#define DBG_TSGEN_CIDR1__CLASS___S 4 +#define DBG_TSGEN_CIDR1__CLASS__PRIMECELL_COMPONENT 0xF +#define DBG_TSGEN_CIDR1__PRMBL_1___M 0x0000000F +#define DBG_TSGEN_CIDR1__PRMBL_1___S 0 +#define DBG_TSGEN_CIDR1__PRMBL_1__ID_VALUE_0 0x0 +#define DBG_TSGEN_CIDR1___M 0x000000FF +#define DBG_TSGEN_CIDR1___S 0 + +#define DBG_TSGEN_CIDR2 (0x00B92FF8) +#define DBG_TSGEN_CIDR2___RWC QCSR_REG_RO +#define DBG_TSGEN_CIDR2___POR 0x00000005 +#define DBG_TSGEN_CIDR2__PRMBL_2___POR 0x05 +#define DBG_TSGEN_CIDR2__PRMBL_2___M 0x000000FF +#define DBG_TSGEN_CIDR2__PRMBL_2___S 0 +#define DBG_TSGEN_CIDR2__PRMBL_2__ID_VALUE_05 0x05 +#define DBG_TSGEN_CIDR2___M 0x000000FF +#define DBG_TSGEN_CIDR2___S 0 + +#define DBG_TSGEN_CIDR3 (0x00B92FFC) +#define DBG_TSGEN_CIDR3___RWC QCSR_REG_RO +#define DBG_TSGEN_CIDR3___POR 0x000000B1 +#define DBG_TSGEN_CIDR3__PRMBL_3___POR 0xB1 +#define DBG_TSGEN_CIDR3__PRMBL_3___M 0x000000FF +#define DBG_TSGEN_CIDR3__PRMBL_3___S 0 +#define DBG_TSGEN_CIDR3__PRMBL_3__ID_VALUE_B1 0xB1 +#define DBG_TSGEN_CIDR3___M 0x000000FF +#define DBG_TSGEN_CIDR3___S 0 + +#define DBG_CTIDBG_CTICONTROL (0x00B94000) +#define DBG_CTIDBG_CTICONTROL___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTICONTROL___POR 0x00000000 +#define DBG_CTIDBG_CTICONTROL__GLBEN___POR 0x0 +#define DBG_CTIDBG_CTICONTROL__GLBEN___M 0x00000001 +#define DBG_CTIDBG_CTICONTROL__GLBEN___S 0 +#define DBG_CTIDBG_CTICONTROL__GLBEN__DISABLED 0x0 +#define DBG_CTIDBG_CTICONTROL__GLBEN__ENABLED 0x1 +#define DBG_CTIDBG_CTICONTROL___M 0x00000001 +#define DBG_CTIDBG_CTICONTROL___S 0 + +#define DBG_CTIDBG_CTIINTACK (0x00B94010) +#define DBG_CTIDBG_CTIINTACK___RWC QCSR_REG_WO +#define DBG_CTIDBG_CTIINTACK___POR 0x00000000 +#define DBG_CTIDBG_CTIINTACK__INTACK___POR 0x00000000 +#define DBG_CTIDBG_CTIINTACK__INTACK___M 0xFFFFFFFF +#define DBG_CTIDBG_CTIINTACK__INTACK___S 0 +#define DBG_CTIDBG_CTIINTACK___M 0xFFFFFFFF +#define DBG_CTIDBG_CTIINTACK___S 0 + +#define DBG_CTIDBG_CTIAPPSET (0x00B94014) +#define DBG_CTIDBG_CTIAPPSET___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIAPPSET___POR 0x00000000 +#define DBG_CTIDBG_CTIAPPSET__APPSET___POR 0x00 +#define DBG_CTIDBG_CTIAPPSET__APPSET___M 0x000000FF +#define DBG_CTIDBG_CTIAPPSET__APPSET___S 0 +#define DBG_CTIDBG_CTIAPPSET___M 0x000000FF +#define DBG_CTIDBG_CTIAPPSET___S 0 + +#define DBG_CTIDBG_CTIAPPCLEAR (0x00B94018) +#define DBG_CTIDBG_CTIAPPCLEAR___RWC QCSR_REG_WO +#define DBG_CTIDBG_CTIAPPCLEAR___POR 0x00000000 +#define DBG_CTIDBG_CTIAPPCLEAR__APPCLEAR___POR 0x00 +#define DBG_CTIDBG_CTIAPPCLEAR__APPCLEAR___M 0x000000FF +#define DBG_CTIDBG_CTIAPPCLEAR__APPCLEAR___S 0 +#define DBG_CTIDBG_CTIAPPCLEAR___M 0x000000FF +#define DBG_CTIDBG_CTIAPPCLEAR___S 0 + +#define DBG_CTIDBG_CTIAPPPULSE (0x00B9401C) +#define DBG_CTIDBG_CTIAPPPULSE___RWC QCSR_REG_WO +#define DBG_CTIDBG_CTIAPPPULSE___POR 0x00000000 +#define DBG_CTIDBG_CTIAPPPULSE__APPULSE___POR 0x00 +#define DBG_CTIDBG_CTIAPPPULSE__APPULSE___M 0x000000FF +#define DBG_CTIDBG_CTIAPPPULSE__APPULSE___S 0 +#define DBG_CTIDBG_CTIAPPPULSE___M 0x000000FF +#define DBG_CTIDBG_CTIAPPPULSE___S 0 + +#define DBG_CTIDBG_CTIINEN0 (0x00B94020) +#define DBG_CTIDBG_CTIINEN0___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIINEN0___POR 0x00000000 +#define DBG_CTIDBG_CTIINEN0__TRIGINEN___POR 0x00 +#define DBG_CTIDBG_CTIINEN0__TRIGINEN___M 0x000000FF +#define DBG_CTIDBG_CTIINEN0__TRIGINEN___S 0 +#define DBG_CTIDBG_CTIINEN0___M 0x000000FF +#define DBG_CTIDBG_CTIINEN0___S 0 + +#define DBG_CTIDBG_CTIINEN1 (0x00B94024) +#define DBG_CTIDBG_CTIINEN1___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIINEN1___POR 0x00000000 +#define DBG_CTIDBG_CTIINEN1__TRIGINEN___POR 0x00 +#define DBG_CTIDBG_CTIINEN1__TRIGINEN___M 0x000000FF +#define DBG_CTIDBG_CTIINEN1__TRIGINEN___S 0 +#define DBG_CTIDBG_CTIINEN1___M 0x000000FF +#define DBG_CTIDBG_CTIINEN1___S 0 + +#define DBG_CTIDBG_CTIINEN2 (0x00B94028) +#define DBG_CTIDBG_CTIINEN2___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIINEN2___POR 0x00000000 +#define DBG_CTIDBG_CTIINEN2__TRIGINEN___POR 0x00 +#define DBG_CTIDBG_CTIINEN2__TRIGINEN___M 0x000000FF +#define DBG_CTIDBG_CTIINEN2__TRIGINEN___S 0 +#define DBG_CTIDBG_CTIINEN2___M 0x000000FF +#define DBG_CTIDBG_CTIINEN2___S 0 + +#define DBG_CTIDBG_CTIINEN3 (0x00B9402C) +#define DBG_CTIDBG_CTIINEN3___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIINEN3___POR 0x00000000 +#define DBG_CTIDBG_CTIINEN3__TRIGINEN___POR 0x00 +#define DBG_CTIDBG_CTIINEN3__TRIGINEN___M 0x000000FF +#define DBG_CTIDBG_CTIINEN3__TRIGINEN___S 0 +#define DBG_CTIDBG_CTIINEN3___M 0x000000FF +#define DBG_CTIDBG_CTIINEN3___S 0 + +#define DBG_CTIDBG_CTIINEN4 (0x00B94030) +#define DBG_CTIDBG_CTIINEN4___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIINEN4___POR 0x00000000 +#define DBG_CTIDBG_CTIINEN4__TRIGINEN___POR 0x00 +#define DBG_CTIDBG_CTIINEN4__TRIGINEN___M 0x000000FF +#define DBG_CTIDBG_CTIINEN4__TRIGINEN___S 0 +#define DBG_CTIDBG_CTIINEN4___M 0x000000FF +#define DBG_CTIDBG_CTIINEN4___S 0 + +#define DBG_CTIDBG_CTIINEN5 (0x00B94034) +#define DBG_CTIDBG_CTIINEN5___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIINEN5___POR 0x00000000 +#define DBG_CTIDBG_CTIINEN5__TRIGINEN___POR 0x00 +#define DBG_CTIDBG_CTIINEN5__TRIGINEN___M 0x000000FF +#define DBG_CTIDBG_CTIINEN5__TRIGINEN___S 0 +#define DBG_CTIDBG_CTIINEN5___M 0x000000FF +#define DBG_CTIDBG_CTIINEN5___S 0 + +#define DBG_CTIDBG_CTIINEN6 (0x00B94038) +#define DBG_CTIDBG_CTIINEN6___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIINEN6___POR 0x00000000 +#define DBG_CTIDBG_CTIINEN6__TRIGINEN___POR 0x00 +#define DBG_CTIDBG_CTIINEN6__TRIGINEN___M 0x000000FF +#define DBG_CTIDBG_CTIINEN6__TRIGINEN___S 0 +#define DBG_CTIDBG_CTIINEN6___M 0x000000FF +#define DBG_CTIDBG_CTIINEN6___S 0 + +#define DBG_CTIDBG_CTIINEN7 (0x00B9403C) +#define DBG_CTIDBG_CTIINEN7___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIINEN7___POR 0x00000000 +#define DBG_CTIDBG_CTIINEN7__TRIGINEN___POR 0x00 +#define DBG_CTIDBG_CTIINEN7__TRIGINEN___M 0x000000FF +#define DBG_CTIDBG_CTIINEN7__TRIGINEN___S 0 +#define DBG_CTIDBG_CTIINEN7___M 0x000000FF +#define DBG_CTIDBG_CTIINEN7___S 0 + +#define DBG_CTIDBG_CTIINEN8 (0x00B94040) +#define DBG_CTIDBG_CTIINEN8___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIINEN8___POR 0x00000000 +#define DBG_CTIDBG_CTIINEN8__TRIGINEN___POR 0x00 +#define DBG_CTIDBG_CTIINEN8__TRIGINEN___M 0x000000FF +#define DBG_CTIDBG_CTIINEN8__TRIGINEN___S 0 +#define DBG_CTIDBG_CTIINEN8___M 0x000000FF +#define DBG_CTIDBG_CTIINEN8___S 0 + +#define DBG_CTIDBG_CTIINEN9 (0x00B94044) +#define DBG_CTIDBG_CTIINEN9___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIINEN9___POR 0x00000000 +#define DBG_CTIDBG_CTIINEN9__TRIGINEN___POR 0x00 +#define DBG_CTIDBG_CTIINEN9__TRIGINEN___M 0x000000FF +#define DBG_CTIDBG_CTIINEN9__TRIGINEN___S 0 +#define DBG_CTIDBG_CTIINEN9___M 0x000000FF +#define DBG_CTIDBG_CTIINEN9___S 0 + +#define DBG_CTIDBG_CTIINEN10 (0x00B94048) +#define DBG_CTIDBG_CTIINEN10___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIINEN10___POR 0x00000000 +#define DBG_CTIDBG_CTIINEN10__TRIGINEN___POR 0x00 +#define DBG_CTIDBG_CTIINEN10__TRIGINEN___M 0x000000FF +#define DBG_CTIDBG_CTIINEN10__TRIGINEN___S 0 +#define DBG_CTIDBG_CTIINEN10___M 0x000000FF +#define DBG_CTIDBG_CTIINEN10___S 0 + +#define DBG_CTIDBG_CTIINEN11 (0x00B9404C) +#define DBG_CTIDBG_CTIINEN11___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIINEN11___POR 0x00000000 +#define DBG_CTIDBG_CTIINEN11__TRIGINEN___POR 0x00 +#define DBG_CTIDBG_CTIINEN11__TRIGINEN___M 0x000000FF +#define DBG_CTIDBG_CTIINEN11__TRIGINEN___S 0 +#define DBG_CTIDBG_CTIINEN11___M 0x000000FF +#define DBG_CTIDBG_CTIINEN11___S 0 + +#define DBG_CTIDBG_CTIINEN12 (0x00B94050) +#define DBG_CTIDBG_CTIINEN12___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIINEN12___POR 0x00000000 +#define DBG_CTIDBG_CTIINEN12__TRIGINEN___POR 0x00 +#define DBG_CTIDBG_CTIINEN12__TRIGINEN___M 0x000000FF +#define DBG_CTIDBG_CTIINEN12__TRIGINEN___S 0 +#define DBG_CTIDBG_CTIINEN12___M 0x000000FF +#define DBG_CTIDBG_CTIINEN12___S 0 + +#define DBG_CTIDBG_CTIINEN13 (0x00B94054) +#define DBG_CTIDBG_CTIINEN13___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIINEN13___POR 0x00000000 +#define DBG_CTIDBG_CTIINEN13__TRIGINEN___POR 0x00 +#define DBG_CTIDBG_CTIINEN13__TRIGINEN___M 0x000000FF +#define DBG_CTIDBG_CTIINEN13__TRIGINEN___S 0 +#define DBG_CTIDBG_CTIINEN13___M 0x000000FF +#define DBG_CTIDBG_CTIINEN13___S 0 + +#define DBG_CTIDBG_CTIINEN14 (0x00B94058) +#define DBG_CTIDBG_CTIINEN14___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIINEN14___POR 0x00000000 +#define DBG_CTIDBG_CTIINEN14__TRIGINEN___POR 0x00 +#define DBG_CTIDBG_CTIINEN14__TRIGINEN___M 0x000000FF +#define DBG_CTIDBG_CTIINEN14__TRIGINEN___S 0 +#define DBG_CTIDBG_CTIINEN14___M 0x000000FF +#define DBG_CTIDBG_CTIINEN14___S 0 + +#define DBG_CTIDBG_CTIINEN15 (0x00B9405C) +#define DBG_CTIDBG_CTIINEN15___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIINEN15___POR 0x00000000 +#define DBG_CTIDBG_CTIINEN15__TRIGINEN___POR 0x00 +#define DBG_CTIDBG_CTIINEN15__TRIGINEN___M 0x000000FF +#define DBG_CTIDBG_CTIINEN15__TRIGINEN___S 0 +#define DBG_CTIDBG_CTIINEN15___M 0x000000FF +#define DBG_CTIDBG_CTIINEN15___S 0 + +#define DBG_CTIDBG_CTIINEN16 (0x00B94060) +#define DBG_CTIDBG_CTIINEN16___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIINEN16___POR 0x00000000 +#define DBG_CTIDBG_CTIINEN16__TRIGINEN___POR 0x00 +#define DBG_CTIDBG_CTIINEN16__TRIGINEN___M 0x000000FF +#define DBG_CTIDBG_CTIINEN16__TRIGINEN___S 0 +#define DBG_CTIDBG_CTIINEN16___M 0x000000FF +#define DBG_CTIDBG_CTIINEN16___S 0 + +#define DBG_CTIDBG_CTIINEN17 (0x00B94064) +#define DBG_CTIDBG_CTIINEN17___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIINEN17___POR 0x00000000 +#define DBG_CTIDBG_CTIINEN17__TRIGINEN___POR 0x00 +#define DBG_CTIDBG_CTIINEN17__TRIGINEN___M 0x000000FF +#define DBG_CTIDBG_CTIINEN17__TRIGINEN___S 0 +#define DBG_CTIDBG_CTIINEN17___M 0x000000FF +#define DBG_CTIDBG_CTIINEN17___S 0 + +#define DBG_CTIDBG_CTIINEN18 (0x00B94068) +#define DBG_CTIDBG_CTIINEN18___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIINEN18___POR 0x00000000 +#define DBG_CTIDBG_CTIINEN18__TRIGINEN___POR 0x00 +#define DBG_CTIDBG_CTIINEN18__TRIGINEN___M 0x000000FF +#define DBG_CTIDBG_CTIINEN18__TRIGINEN___S 0 +#define DBG_CTIDBG_CTIINEN18___M 0x000000FF +#define DBG_CTIDBG_CTIINEN18___S 0 + +#define DBG_CTIDBG_CTIINEN19 (0x00B9406C) +#define DBG_CTIDBG_CTIINEN19___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIINEN19___POR 0x00000000 +#define DBG_CTIDBG_CTIINEN19__TRIGINEN___POR 0x00 +#define DBG_CTIDBG_CTIINEN19__TRIGINEN___M 0x000000FF +#define DBG_CTIDBG_CTIINEN19__TRIGINEN___S 0 +#define DBG_CTIDBG_CTIINEN19___M 0x000000FF +#define DBG_CTIDBG_CTIINEN19___S 0 + +#define DBG_CTIDBG_CTIINEN20 (0x00B94070) +#define DBG_CTIDBG_CTIINEN20___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIINEN20___POR 0x00000000 +#define DBG_CTIDBG_CTIINEN20__TRIGINEN___POR 0x00 +#define DBG_CTIDBG_CTIINEN20__TRIGINEN___M 0x000000FF +#define DBG_CTIDBG_CTIINEN20__TRIGINEN___S 0 +#define DBG_CTIDBG_CTIINEN20___M 0x000000FF +#define DBG_CTIDBG_CTIINEN20___S 0 + +#define DBG_CTIDBG_CTIINEN21 (0x00B94074) +#define DBG_CTIDBG_CTIINEN21___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIINEN21___POR 0x00000000 +#define DBG_CTIDBG_CTIINEN21__TRIGINEN___POR 0x00 +#define DBG_CTIDBG_CTIINEN21__TRIGINEN___M 0x000000FF +#define DBG_CTIDBG_CTIINEN21__TRIGINEN___S 0 +#define DBG_CTIDBG_CTIINEN21___M 0x000000FF +#define DBG_CTIDBG_CTIINEN21___S 0 + +#define DBG_CTIDBG_CTIINEN22 (0x00B94078) +#define DBG_CTIDBG_CTIINEN22___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIINEN22___POR 0x00000000 +#define DBG_CTIDBG_CTIINEN22__TRIGINEN___POR 0x00 +#define DBG_CTIDBG_CTIINEN22__TRIGINEN___M 0x000000FF +#define DBG_CTIDBG_CTIINEN22__TRIGINEN___S 0 +#define DBG_CTIDBG_CTIINEN22___M 0x000000FF +#define DBG_CTIDBG_CTIINEN22___S 0 + +#define DBG_CTIDBG_CTIINEN23 (0x00B9407C) +#define DBG_CTIDBG_CTIINEN23___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIINEN23___POR 0x00000000 +#define DBG_CTIDBG_CTIINEN23__TRIGINEN___POR 0x00 +#define DBG_CTIDBG_CTIINEN23__TRIGINEN___M 0x000000FF +#define DBG_CTIDBG_CTIINEN23__TRIGINEN___S 0 +#define DBG_CTIDBG_CTIINEN23___M 0x000000FF +#define DBG_CTIDBG_CTIINEN23___S 0 + +#define DBG_CTIDBG_CTIINEN24 (0x00B94080) +#define DBG_CTIDBG_CTIINEN24___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIINEN24___POR 0x00000000 +#define DBG_CTIDBG_CTIINEN24__TRIGINEN___POR 0x00 +#define DBG_CTIDBG_CTIINEN24__TRIGINEN___M 0x000000FF +#define DBG_CTIDBG_CTIINEN24__TRIGINEN___S 0 +#define DBG_CTIDBG_CTIINEN24___M 0x000000FF +#define DBG_CTIDBG_CTIINEN24___S 0 + +#define DBG_CTIDBG_CTIINEN25 (0x00B94084) +#define DBG_CTIDBG_CTIINEN25___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIINEN25___POR 0x00000000 +#define DBG_CTIDBG_CTIINEN25__TRIGINEN___POR 0x00 +#define DBG_CTIDBG_CTIINEN25__TRIGINEN___M 0x000000FF +#define DBG_CTIDBG_CTIINEN25__TRIGINEN___S 0 +#define DBG_CTIDBG_CTIINEN25___M 0x000000FF +#define DBG_CTIDBG_CTIINEN25___S 0 + +#define DBG_CTIDBG_CTIINEN26 (0x00B94088) +#define DBG_CTIDBG_CTIINEN26___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIINEN26___POR 0x00000000 +#define DBG_CTIDBG_CTIINEN26__TRIGINEN___POR 0x00 +#define DBG_CTIDBG_CTIINEN26__TRIGINEN___M 0x000000FF +#define DBG_CTIDBG_CTIINEN26__TRIGINEN___S 0 +#define DBG_CTIDBG_CTIINEN26___M 0x000000FF +#define DBG_CTIDBG_CTIINEN26___S 0 + +#define DBG_CTIDBG_CTIINEN27 (0x00B9408C) +#define DBG_CTIDBG_CTIINEN27___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIINEN27___POR 0x00000000 +#define DBG_CTIDBG_CTIINEN27__TRIGINEN___POR 0x00 +#define DBG_CTIDBG_CTIINEN27__TRIGINEN___M 0x000000FF +#define DBG_CTIDBG_CTIINEN27__TRIGINEN___S 0 +#define DBG_CTIDBG_CTIINEN27___M 0x000000FF +#define DBG_CTIDBG_CTIINEN27___S 0 + +#define DBG_CTIDBG_CTIINEN28 (0x00B94090) +#define DBG_CTIDBG_CTIINEN28___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIINEN28___POR 0x00000000 +#define DBG_CTIDBG_CTIINEN28__TRIGINEN___POR 0x00 +#define DBG_CTIDBG_CTIINEN28__TRIGINEN___M 0x000000FF +#define DBG_CTIDBG_CTIINEN28__TRIGINEN___S 0 +#define DBG_CTIDBG_CTIINEN28___M 0x000000FF +#define DBG_CTIDBG_CTIINEN28___S 0 + +#define DBG_CTIDBG_CTIINEN29 (0x00B94094) +#define DBG_CTIDBG_CTIINEN29___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIINEN29___POR 0x00000000 +#define DBG_CTIDBG_CTIINEN29__TRIGINEN___POR 0x00 +#define DBG_CTIDBG_CTIINEN29__TRIGINEN___M 0x000000FF +#define DBG_CTIDBG_CTIINEN29__TRIGINEN___S 0 +#define DBG_CTIDBG_CTIINEN29___M 0x000000FF +#define DBG_CTIDBG_CTIINEN29___S 0 + +#define DBG_CTIDBG_CTIINEN30 (0x00B94098) +#define DBG_CTIDBG_CTIINEN30___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIINEN30___POR 0x00000000 +#define DBG_CTIDBG_CTIINEN30__TRIGINEN___POR 0x00 +#define DBG_CTIDBG_CTIINEN30__TRIGINEN___M 0x000000FF +#define DBG_CTIDBG_CTIINEN30__TRIGINEN___S 0 +#define DBG_CTIDBG_CTIINEN30___M 0x000000FF +#define DBG_CTIDBG_CTIINEN30___S 0 + +#define DBG_CTIDBG_CTIINEN31 (0x00B9409C) +#define DBG_CTIDBG_CTIINEN31___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIINEN31___POR 0x00000000 +#define DBG_CTIDBG_CTIINEN31__TRIGINEN___POR 0x00 +#define DBG_CTIDBG_CTIINEN31__TRIGINEN___M 0x000000FF +#define DBG_CTIDBG_CTIINEN31__TRIGINEN___S 0 +#define DBG_CTIDBG_CTIINEN31___M 0x000000FF +#define DBG_CTIDBG_CTIINEN31___S 0 + +#define DBG_CTIDBG_CTIOUTEN0 (0x00B940A0) +#define DBG_CTIDBG_CTIOUTEN0___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIOUTEN0___POR 0x00000000 +#define DBG_CTIDBG_CTIOUTEN0__TRIGOUTEN___POR 0x00 +#define DBG_CTIDBG_CTIOUTEN0__TRIGOUTEN___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN0__TRIGOUTEN___S 0 +#define DBG_CTIDBG_CTIOUTEN0___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN0___S 0 + +#define DBG_CTIDBG_CTIOUTEN1 (0x00B940A4) +#define DBG_CTIDBG_CTIOUTEN1___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIOUTEN1___POR 0x00000000 +#define DBG_CTIDBG_CTIOUTEN1__TRIGOUTEN___POR 0x00 +#define DBG_CTIDBG_CTIOUTEN1__TRIGOUTEN___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN1__TRIGOUTEN___S 0 +#define DBG_CTIDBG_CTIOUTEN1___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN1___S 0 + +#define DBG_CTIDBG_CTIOUTEN2 (0x00B940A8) +#define DBG_CTIDBG_CTIOUTEN2___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIOUTEN2___POR 0x00000000 +#define DBG_CTIDBG_CTIOUTEN2__TRIGOUTEN___POR 0x00 +#define DBG_CTIDBG_CTIOUTEN2__TRIGOUTEN___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN2__TRIGOUTEN___S 0 +#define DBG_CTIDBG_CTIOUTEN2___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN2___S 0 + +#define DBG_CTIDBG_CTIOUTEN3 (0x00B940AC) +#define DBG_CTIDBG_CTIOUTEN3___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIOUTEN3___POR 0x00000000 +#define DBG_CTIDBG_CTIOUTEN3__TRIGOUTEN___POR 0x00 +#define DBG_CTIDBG_CTIOUTEN3__TRIGOUTEN___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN3__TRIGOUTEN___S 0 +#define DBG_CTIDBG_CTIOUTEN3___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN3___S 0 + +#define DBG_CTIDBG_CTIOUTEN4 (0x00B940B0) +#define DBG_CTIDBG_CTIOUTEN4___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIOUTEN4___POR 0x00000000 +#define DBG_CTIDBG_CTIOUTEN4__TRIGOUTEN___POR 0x00 +#define DBG_CTIDBG_CTIOUTEN4__TRIGOUTEN___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN4__TRIGOUTEN___S 0 +#define DBG_CTIDBG_CTIOUTEN4___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN4___S 0 + +#define DBG_CTIDBG_CTIOUTEN5 (0x00B940B4) +#define DBG_CTIDBG_CTIOUTEN5___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIOUTEN5___POR 0x00000000 +#define DBG_CTIDBG_CTIOUTEN5__TRIGOUTEN___POR 0x00 +#define DBG_CTIDBG_CTIOUTEN5__TRIGOUTEN___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN5__TRIGOUTEN___S 0 +#define DBG_CTIDBG_CTIOUTEN5___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN5___S 0 + +#define DBG_CTIDBG_CTIOUTEN6 (0x00B940B8) +#define DBG_CTIDBG_CTIOUTEN6___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIOUTEN6___POR 0x00000000 +#define DBG_CTIDBG_CTIOUTEN6__TRIGOUTEN___POR 0x00 +#define DBG_CTIDBG_CTIOUTEN6__TRIGOUTEN___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN6__TRIGOUTEN___S 0 +#define DBG_CTIDBG_CTIOUTEN6___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN6___S 0 + +#define DBG_CTIDBG_CTIOUTEN7 (0x00B940BC) +#define DBG_CTIDBG_CTIOUTEN7___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIOUTEN7___POR 0x00000000 +#define DBG_CTIDBG_CTIOUTEN7__TRIGOUTEN___POR 0x00 +#define DBG_CTIDBG_CTIOUTEN7__TRIGOUTEN___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN7__TRIGOUTEN___S 0 +#define DBG_CTIDBG_CTIOUTEN7___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN7___S 0 + +#define DBG_CTIDBG_CTIOUTEN8 (0x00B940C0) +#define DBG_CTIDBG_CTIOUTEN8___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIOUTEN8___POR 0x00000000 +#define DBG_CTIDBG_CTIOUTEN8__TRIGOUTEN___POR 0x00 +#define DBG_CTIDBG_CTIOUTEN8__TRIGOUTEN___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN8__TRIGOUTEN___S 0 +#define DBG_CTIDBG_CTIOUTEN8___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN8___S 0 + +#define DBG_CTIDBG_CTIOUTEN9 (0x00B940C4) +#define DBG_CTIDBG_CTIOUTEN9___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIOUTEN9___POR 0x00000000 +#define DBG_CTIDBG_CTIOUTEN9__TRIGOUTEN___POR 0x00 +#define DBG_CTIDBG_CTIOUTEN9__TRIGOUTEN___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN9__TRIGOUTEN___S 0 +#define DBG_CTIDBG_CTIOUTEN9___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN9___S 0 + +#define DBG_CTIDBG_CTIOUTEN10 (0x00B940C8) +#define DBG_CTIDBG_CTIOUTEN10___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIOUTEN10___POR 0x00000000 +#define DBG_CTIDBG_CTIOUTEN10__TRIGOUTEN___POR 0x00 +#define DBG_CTIDBG_CTIOUTEN10__TRIGOUTEN___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN10__TRIGOUTEN___S 0 +#define DBG_CTIDBG_CTIOUTEN10___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN10___S 0 + +#define DBG_CTIDBG_CTIOUTEN11 (0x00B940CC) +#define DBG_CTIDBG_CTIOUTEN11___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIOUTEN11___POR 0x00000000 +#define DBG_CTIDBG_CTIOUTEN11__TRIGOUTEN___POR 0x00 +#define DBG_CTIDBG_CTIOUTEN11__TRIGOUTEN___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN11__TRIGOUTEN___S 0 +#define DBG_CTIDBG_CTIOUTEN11___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN11___S 0 + +#define DBG_CTIDBG_CTIOUTEN12 (0x00B940D0) +#define DBG_CTIDBG_CTIOUTEN12___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIOUTEN12___POR 0x00000000 +#define DBG_CTIDBG_CTIOUTEN12__TRIGOUTEN___POR 0x00 +#define DBG_CTIDBG_CTIOUTEN12__TRIGOUTEN___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN12__TRIGOUTEN___S 0 +#define DBG_CTIDBG_CTIOUTEN12___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN12___S 0 + +#define DBG_CTIDBG_CTIOUTEN13 (0x00B940D4) +#define DBG_CTIDBG_CTIOUTEN13___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIOUTEN13___POR 0x00000000 +#define DBG_CTIDBG_CTIOUTEN13__TRIGOUTEN___POR 0x00 +#define DBG_CTIDBG_CTIOUTEN13__TRIGOUTEN___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN13__TRIGOUTEN___S 0 +#define DBG_CTIDBG_CTIOUTEN13___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN13___S 0 + +#define DBG_CTIDBG_CTIOUTEN14 (0x00B940D8) +#define DBG_CTIDBG_CTIOUTEN14___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIOUTEN14___POR 0x00000000 +#define DBG_CTIDBG_CTIOUTEN14__TRIGOUTEN___POR 0x00 +#define DBG_CTIDBG_CTIOUTEN14__TRIGOUTEN___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN14__TRIGOUTEN___S 0 +#define DBG_CTIDBG_CTIOUTEN14___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN14___S 0 + +#define DBG_CTIDBG_CTIOUTEN15 (0x00B940DC) +#define DBG_CTIDBG_CTIOUTEN15___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIOUTEN15___POR 0x00000000 +#define DBG_CTIDBG_CTIOUTEN15__TRIGOUTEN___POR 0x00 +#define DBG_CTIDBG_CTIOUTEN15__TRIGOUTEN___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN15__TRIGOUTEN___S 0 +#define DBG_CTIDBG_CTIOUTEN15___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN15___S 0 + +#define DBG_CTIDBG_CTIOUTEN16 (0x00B940E0) +#define DBG_CTIDBG_CTIOUTEN16___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIOUTEN16___POR 0x00000000 +#define DBG_CTIDBG_CTIOUTEN16__TRIGOUTEN___POR 0x00 +#define DBG_CTIDBG_CTIOUTEN16__TRIGOUTEN___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN16__TRIGOUTEN___S 0 +#define DBG_CTIDBG_CTIOUTEN16___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN16___S 0 + +#define DBG_CTIDBG_CTIOUTEN17 (0x00B940E4) +#define DBG_CTIDBG_CTIOUTEN17___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIOUTEN17___POR 0x00000000 +#define DBG_CTIDBG_CTIOUTEN17__TRIGOUTEN___POR 0x00 +#define DBG_CTIDBG_CTIOUTEN17__TRIGOUTEN___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN17__TRIGOUTEN___S 0 +#define DBG_CTIDBG_CTIOUTEN17___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN17___S 0 + +#define DBG_CTIDBG_CTIOUTEN18 (0x00B940E8) +#define DBG_CTIDBG_CTIOUTEN18___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIOUTEN18___POR 0x00000000 +#define DBG_CTIDBG_CTIOUTEN18__TRIGOUTEN___POR 0x00 +#define DBG_CTIDBG_CTIOUTEN18__TRIGOUTEN___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN18__TRIGOUTEN___S 0 +#define DBG_CTIDBG_CTIOUTEN18___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN18___S 0 + +#define DBG_CTIDBG_CTIOUTEN19 (0x00B940EC) +#define DBG_CTIDBG_CTIOUTEN19___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIOUTEN19___POR 0x00000000 +#define DBG_CTIDBG_CTIOUTEN19__TRIGOUTEN___POR 0x00 +#define DBG_CTIDBG_CTIOUTEN19__TRIGOUTEN___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN19__TRIGOUTEN___S 0 +#define DBG_CTIDBG_CTIOUTEN19___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN19___S 0 + +#define DBG_CTIDBG_CTIOUTEN20 (0x00B940F0) +#define DBG_CTIDBG_CTIOUTEN20___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIOUTEN20___POR 0x00000000 +#define DBG_CTIDBG_CTIOUTEN20__TRIGOUTEN___POR 0x00 +#define DBG_CTIDBG_CTIOUTEN20__TRIGOUTEN___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN20__TRIGOUTEN___S 0 +#define DBG_CTIDBG_CTIOUTEN20___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN20___S 0 + +#define DBG_CTIDBG_CTIOUTEN21 (0x00B940F4) +#define DBG_CTIDBG_CTIOUTEN21___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIOUTEN21___POR 0x00000000 +#define DBG_CTIDBG_CTIOUTEN21__TRIGOUTEN___POR 0x00 +#define DBG_CTIDBG_CTIOUTEN21__TRIGOUTEN___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN21__TRIGOUTEN___S 0 +#define DBG_CTIDBG_CTIOUTEN21___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN21___S 0 + +#define DBG_CTIDBG_CTIOUTEN22 (0x00B940F8) +#define DBG_CTIDBG_CTIOUTEN22___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIOUTEN22___POR 0x00000000 +#define DBG_CTIDBG_CTIOUTEN22__TRIGOUTEN___POR 0x00 +#define DBG_CTIDBG_CTIOUTEN22__TRIGOUTEN___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN22__TRIGOUTEN___S 0 +#define DBG_CTIDBG_CTIOUTEN22___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN22___S 0 + +#define DBG_CTIDBG_CTIOUTEN23 (0x00B940FC) +#define DBG_CTIDBG_CTIOUTEN23___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIOUTEN23___POR 0x00000000 +#define DBG_CTIDBG_CTIOUTEN23__TRIGOUTEN___POR 0x00 +#define DBG_CTIDBG_CTIOUTEN23__TRIGOUTEN___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN23__TRIGOUTEN___S 0 +#define DBG_CTIDBG_CTIOUTEN23___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN23___S 0 + +#define DBG_CTIDBG_CTIOUTEN24 (0x00B94100) +#define DBG_CTIDBG_CTIOUTEN24___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIOUTEN24___POR 0x00000000 +#define DBG_CTIDBG_CTIOUTEN24__TRIGOUTEN___POR 0x00 +#define DBG_CTIDBG_CTIOUTEN24__TRIGOUTEN___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN24__TRIGOUTEN___S 0 +#define DBG_CTIDBG_CTIOUTEN24___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN24___S 0 + +#define DBG_CTIDBG_CTIOUTEN25 (0x00B94104) +#define DBG_CTIDBG_CTIOUTEN25___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIOUTEN25___POR 0x00000000 +#define DBG_CTIDBG_CTIOUTEN25__TRIGOUTEN___POR 0x00 +#define DBG_CTIDBG_CTIOUTEN25__TRIGOUTEN___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN25__TRIGOUTEN___S 0 +#define DBG_CTIDBG_CTIOUTEN25___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN25___S 0 + +#define DBG_CTIDBG_CTIOUTEN26 (0x00B94108) +#define DBG_CTIDBG_CTIOUTEN26___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIOUTEN26___POR 0x00000000 +#define DBG_CTIDBG_CTIOUTEN26__TRIGOUTEN___POR 0x00 +#define DBG_CTIDBG_CTIOUTEN26__TRIGOUTEN___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN26__TRIGOUTEN___S 0 +#define DBG_CTIDBG_CTIOUTEN26___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN26___S 0 + +#define DBG_CTIDBG_CTIOUTEN27 (0x00B9410C) +#define DBG_CTIDBG_CTIOUTEN27___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIOUTEN27___POR 0x00000000 +#define DBG_CTIDBG_CTIOUTEN27__TRIGOUTEN___POR 0x00 +#define DBG_CTIDBG_CTIOUTEN27__TRIGOUTEN___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN27__TRIGOUTEN___S 0 +#define DBG_CTIDBG_CTIOUTEN27___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN27___S 0 + +#define DBG_CTIDBG_CTIOUTEN28 (0x00B94110) +#define DBG_CTIDBG_CTIOUTEN28___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIOUTEN28___POR 0x00000000 +#define DBG_CTIDBG_CTIOUTEN28__TRIGOUTEN___POR 0x00 +#define DBG_CTIDBG_CTIOUTEN28__TRIGOUTEN___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN28__TRIGOUTEN___S 0 +#define DBG_CTIDBG_CTIOUTEN28___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN28___S 0 + +#define DBG_CTIDBG_CTIOUTEN29 (0x00B94114) +#define DBG_CTIDBG_CTIOUTEN29___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIOUTEN29___POR 0x00000000 +#define DBG_CTIDBG_CTIOUTEN29__TRIGOUTEN___POR 0x00 +#define DBG_CTIDBG_CTIOUTEN29__TRIGOUTEN___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN29__TRIGOUTEN___S 0 +#define DBG_CTIDBG_CTIOUTEN29___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN29___S 0 + +#define DBG_CTIDBG_CTIOUTEN30 (0x00B94118) +#define DBG_CTIDBG_CTIOUTEN30___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIOUTEN30___POR 0x00000000 +#define DBG_CTIDBG_CTIOUTEN30__TRIGOUTEN___POR 0x00 +#define DBG_CTIDBG_CTIOUTEN30__TRIGOUTEN___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN30__TRIGOUTEN___S 0 +#define DBG_CTIDBG_CTIOUTEN30___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN30___S 0 + +#define DBG_CTIDBG_CTIOUTEN31 (0x00B9411C) +#define DBG_CTIDBG_CTIOUTEN31___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIOUTEN31___POR 0x00000000 +#define DBG_CTIDBG_CTIOUTEN31__TRIGOUTEN___POR 0x00 +#define DBG_CTIDBG_CTIOUTEN31__TRIGOUTEN___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN31__TRIGOUTEN___S 0 +#define DBG_CTIDBG_CTIOUTEN31___M 0x000000FF +#define DBG_CTIDBG_CTIOUTEN31___S 0 + +#define DBG_CTIDBG_CTITRIGINSTATUS (0x00B94130) +#define DBG_CTIDBG_CTITRIGINSTATUS___RWC QCSR_REG_RO +#define DBG_CTIDBG_CTITRIGINSTATUS__TRIGINSTATUS___M 0xFFFFFFFF +#define DBG_CTIDBG_CTITRIGINSTATUS__TRIGINSTATUS___S 0 +#define DBG_CTIDBG_CTITRIGINSTATUS___M 0xFFFFFFFF +#define DBG_CTIDBG_CTITRIGINSTATUS___S 0 + +#define DBG_CTIDBG_CTITRIGOUTSTATUS (0x00B94134) +#define DBG_CTIDBG_CTITRIGOUTSTATUS___RWC QCSR_REG_RO +#define DBG_CTIDBG_CTITRIGOUTSTATUS___POR 0x00000000 +#define DBG_CTIDBG_CTITRIGOUTSTATUS__TRIGOUTSTATUS___POR 0x00000000 +#define DBG_CTIDBG_CTITRIGOUTSTATUS__TRIGOUTSTATUS___M 0xFFFFFFFF +#define DBG_CTIDBG_CTITRIGOUTSTATUS__TRIGOUTSTATUS___S 0 +#define DBG_CTIDBG_CTITRIGOUTSTATUS___M 0xFFFFFFFF +#define DBG_CTIDBG_CTITRIGOUTSTATUS___S 0 + +#define DBG_CTIDBG_CTICHINSTATUS (0x00B94138) +#define DBG_CTIDBG_CTICHINSTATUS___RWC QCSR_REG_RO +#define DBG_CTIDBG_CTICHINSTATUS__CTICHINSTATUS___M 0x000000FF +#define DBG_CTIDBG_CTICHINSTATUS__CTICHINSTATUS___S 0 +#define DBG_CTIDBG_CTICHINSTATUS___M 0x000000FF +#define DBG_CTIDBG_CTICHINSTATUS___S 0 + +#define DBG_CTIDBG_CTICHOUTSTATUS (0x00B9413C) +#define DBG_CTIDBG_CTICHOUTSTATUS___RWC QCSR_REG_RO +#define DBG_CTIDBG_CTICHOUTSTATUS___POR 0x00000000 +#define DBG_CTIDBG_CTICHOUTSTATUS__CTICHOUTSTATUS___POR 0x00 +#define DBG_CTIDBG_CTICHOUTSTATUS__CTICHOUTSTATUS___M 0x000000FF +#define DBG_CTIDBG_CTICHOUTSTATUS__CTICHOUTSTATUS___S 0 +#define DBG_CTIDBG_CTICHOUTSTATUS___M 0x000000FF +#define DBG_CTIDBG_CTICHOUTSTATUS___S 0 + +#define DBG_CTIDBG_CTIGATE (0x00B94140) +#define DBG_CTIDBG_CTIGATE___RWC QCSR_REG_RW +#define DBG_CTIDBG_CTIGATE___POR 0x000000FF +#define DBG_CTIDBG_CTIGATE__CTIGATEEN7___POR 0x1 +#define DBG_CTIDBG_CTIGATE__CTIGATEEN6___POR 0x1 +#define DBG_CTIDBG_CTIGATE__CTIGATEEN5___POR 0x1 +#define DBG_CTIDBG_CTIGATE__CTIGATEEN4___POR 0x1 +#define DBG_CTIDBG_CTIGATE__CTIGATEEN3___POR 0x1 +#define DBG_CTIDBG_CTIGATE__CTIGATEEN2___POR 0x1 +#define DBG_CTIDBG_CTIGATE__CTIGATEEN1___POR 0x1 +#define DBG_CTIDBG_CTIGATE__CTIGATEEN0___POR 0x1 +#define DBG_CTIDBG_CTIGATE__CTIGATEEN7___M 0x00000080 +#define DBG_CTIDBG_CTIGATE__CTIGATEEN7___S 7 +#define DBG_CTIDBG_CTIGATE__CTIGATEEN6___M 0x00000040 +#define DBG_CTIDBG_CTIGATE__CTIGATEEN6___S 6 +#define DBG_CTIDBG_CTIGATE__CTIGATEEN5___M 0x00000020 +#define DBG_CTIDBG_CTIGATE__CTIGATEEN5___S 5 +#define DBG_CTIDBG_CTIGATE__CTIGATEEN4___M 0x00000010 +#define DBG_CTIDBG_CTIGATE__CTIGATEEN4___S 4 +#define DBG_CTIDBG_CTIGATE__CTIGATEEN3___M 0x00000008 +#define DBG_CTIDBG_CTIGATE__CTIGATEEN3___S 3 +#define DBG_CTIDBG_CTIGATE__CTIGATEEN2___M 0x00000004 +#define DBG_CTIDBG_CTIGATE__CTIGATEEN2___S 2 +#define DBG_CTIDBG_CTIGATE__CTIGATEEN1___M 0x00000002 +#define DBG_CTIDBG_CTIGATE__CTIGATEEN1___S 1 +#define DBG_CTIDBG_CTIGATE__CTIGATEEN0___M 0x00000001 +#define DBG_CTIDBG_CTIGATE__CTIGATEEN0___S 0 +#define DBG_CTIDBG_CTIGATE___M 0x000000FF +#define DBG_CTIDBG_CTIGATE___S 0 + +#define DBG_CTIDBG_ASICCTL (0x00B94144) +#define DBG_CTIDBG_ASICCTL___RWC QCSR_REG_RW +#define DBG_CTIDBG_ASICCTL___POR 0x00000000 +#define DBG_CTIDBG_ASICCTL__ASICCTL___POR 0x00000000 +#define DBG_CTIDBG_ASICCTL__ASICCTL___M 0xFFFFFFFF +#define DBG_CTIDBG_ASICCTL__ASICCTL___S 0 +#define DBG_CTIDBG_ASICCTL___M 0xFFFFFFFF +#define DBG_CTIDBG_ASICCTL___S 0 + +#define DBG_CTIDBG_ITCHINACK (0x00B94EDC) +#define DBG_CTIDBG_ITCHINACK___RWC QCSR_REG_WO +#define DBG_CTIDBG_ITCHINACK___POR 0x00000000 +#define DBG_CTIDBG_ITCHINACK__CTCHINACK___POR 0x00 +#define DBG_CTIDBG_ITCHINACK__CTCHINACK___M 0x000000FF +#define DBG_CTIDBG_ITCHINACK__CTCHINACK___S 0 +#define DBG_CTIDBG_ITCHINACK___M 0x000000FF +#define DBG_CTIDBG_ITCHINACK___S 0 + +#define DBG_CTIDBG_ITTRIGINACK (0x00B94EE0) +#define DBG_CTIDBG_ITTRIGINACK___RWC QCSR_REG_WO +#define DBG_CTIDBG_ITTRIGINACK___POR 0x00000000 +#define DBG_CTIDBG_ITTRIGINACK__CTTRIGINACK___POR 0x00000000 +#define DBG_CTIDBG_ITTRIGINACK__CTTRIGINACK___M 0xFFFFFFFF +#define DBG_CTIDBG_ITTRIGINACK__CTTRIGINACK___S 0 +#define DBG_CTIDBG_ITTRIGINACK___M 0xFFFFFFFF +#define DBG_CTIDBG_ITTRIGINACK___S 0 + +#define DBG_CTIDBG_ITCHOUT (0x00B94EE4) +#define DBG_CTIDBG_ITCHOUT___RWC QCSR_REG_WO +#define DBG_CTIDBG_ITCHOUT___POR 0x00000000 +#define DBG_CTIDBG_ITCHOUT__CTCHOUT___POR 0x00 +#define DBG_CTIDBG_ITCHOUT__CTCHOUT___M 0x000000FF +#define DBG_CTIDBG_ITCHOUT__CTCHOUT___S 0 +#define DBG_CTIDBG_ITCHOUT___M 0x000000FF +#define DBG_CTIDBG_ITCHOUT___S 0 + +#define DBG_CTIDBG_ITTRIGOUT (0x00B94EE8) +#define DBG_CTIDBG_ITTRIGOUT___RWC QCSR_REG_WO +#define DBG_CTIDBG_ITTRIGOUT___POR 0x00000000 +#define DBG_CTIDBG_ITTRIGOUT__CTTRIGOUT___POR 0x00000000 +#define DBG_CTIDBG_ITTRIGOUT__CTTRIGOUT___M 0xFFFFFFFF +#define DBG_CTIDBG_ITTRIGOUT__CTTRIGOUT___S 0 +#define DBG_CTIDBG_ITTRIGOUT___M 0xFFFFFFFF +#define DBG_CTIDBG_ITTRIGOUT___S 0 + +#define DBG_CTIDBG_ITCHOUTACK (0x00B94EEC) +#define DBG_CTIDBG_ITCHOUTACK___RWC QCSR_REG_RO +#define DBG_CTIDBG_ITCHOUTACK___POR 0x00000000 +#define DBG_CTIDBG_ITCHOUTACK__CTCHOUTACK___POR 0x00 +#define DBG_CTIDBG_ITCHOUTACK__CTCHOUTACK___M 0x000000FF +#define DBG_CTIDBG_ITCHOUTACK__CTCHOUTACK___S 0 +#define DBG_CTIDBG_ITCHOUTACK___M 0x000000FF +#define DBG_CTIDBG_ITCHOUTACK___S 0 + +#define DBG_CTIDBG_ITTRIGOUTACK (0x00B94EF0) +#define DBG_CTIDBG_ITTRIGOUTACK___RWC QCSR_REG_RO +#define DBG_CTIDBG_ITTRIGOUTACK___POR 0x00000000 +#define DBG_CTIDBG_ITTRIGOUTACK__CTTRIGOUTACK___POR 0x00000000 +#define DBG_CTIDBG_ITTRIGOUTACK__CTTRIGOUTACK___M 0xFFFFFFFF +#define DBG_CTIDBG_ITTRIGOUTACK__CTTRIGOUTACK___S 0 +#define DBG_CTIDBG_ITTRIGOUTACK___M 0xFFFFFFFF +#define DBG_CTIDBG_ITTRIGOUTACK___S 0 + +#define DBG_CTIDBG_ITCHIN (0x00B94EF4) +#define DBG_CTIDBG_ITCHIN___RWC QCSR_REG_RO +#define DBG_CTIDBG_ITCHIN___POR 0x00000000 +#define DBG_CTIDBG_ITCHIN__CTCHIN___POR 0x00 +#define DBG_CTIDBG_ITCHIN__CTCHIN___M 0x000000FF +#define DBG_CTIDBG_ITCHIN__CTCHIN___S 0 +#define DBG_CTIDBG_ITCHIN___M 0x000000FF +#define DBG_CTIDBG_ITCHIN___S 0 + +#define DBG_CTIDBG_ITTRIGIN (0x00B94EF8) +#define DBG_CTIDBG_ITTRIGIN___RWC QCSR_REG_RO +#define DBG_CTIDBG_ITTRIGIN___POR 0x00000000 +#define DBG_CTIDBG_ITTRIGIN__CTTRIGIN___POR 0x00000000 +#define DBG_CTIDBG_ITTRIGIN__CTTRIGIN___M 0xFFFFFFFF +#define DBG_CTIDBG_ITTRIGIN__CTTRIGIN___S 0 +#define DBG_CTIDBG_ITTRIGIN___M 0xFFFFFFFF +#define DBG_CTIDBG_ITTRIGIN___S 0 + +#define DBG_CTIDBG_ITCTRL (0x00B94F00) +#define DBG_CTIDBG_ITCTRL___RWC QCSR_REG_RW +#define DBG_CTIDBG_ITCTRL___POR 0x00000000 +#define DBG_CTIDBG_ITCTRL__INTEGRATION_MODE___POR 0x0 +#define DBG_CTIDBG_ITCTRL__INTEGRATION_MODE___M 0x00000001 +#define DBG_CTIDBG_ITCTRL__INTEGRATION_MODE___S 0 +#define DBG_CTIDBG_ITCTRL__INTEGRATION_MODE__FUNCTIONAL_MODE 0x0 +#define DBG_CTIDBG_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE 0x1 +#define DBG_CTIDBG_ITCTRL___M 0x00000001 +#define DBG_CTIDBG_ITCTRL___S 0 + +#define DBG_CTIDBG_CLAIMSET (0x00B94FA0) +#define DBG_CTIDBG_CLAIMSET___RWC QCSR_REG_RW +#define DBG_CTIDBG_CLAIMSET___POR 0x0000000F +#define DBG_CTIDBG_CLAIMSET__CLAIMSET___POR 0xF +#define DBG_CTIDBG_CLAIMSET__CLAIMSET___M 0x0000000F +#define DBG_CTIDBG_CLAIMSET__CLAIMSET___S 0 +#define DBG_CTIDBG_CLAIMSET__CLAIMSET__CLAIM_TAG_IMPLEMENTED_BITS 0xF +#define DBG_CTIDBG_CLAIMSET___M 0x0000000F +#define DBG_CTIDBG_CLAIMSET___S 0 + +#define DBG_CTIDBG_CLAIMCLR (0x00B94FA4) +#define DBG_CTIDBG_CLAIMCLR___RWC QCSR_REG_RW +#define DBG_CTIDBG_CLAIMCLR___POR 0x00000000 +#define DBG_CTIDBG_CLAIMCLR__CLAIMCLR___POR 0x0 +#define DBG_CTIDBG_CLAIMCLR__CLAIMCLR___M 0x0000000F +#define DBG_CTIDBG_CLAIMCLR__CLAIMCLR___S 0 +#define DBG_CTIDBG_CLAIMCLR___M 0x0000000F +#define DBG_CTIDBG_CLAIMCLR___S 0 + +#define DBG_CTIDBG_DEVAFF0 (0x00B94FA8) +#define DBG_CTIDBG_DEVAFF0___RWC QCSR_REG_RO +#define DBG_CTIDBG_DEVAFF0___POR 0x00000000 +#define DBG_CTIDBG_DEVAFF0__VAL___POR 0x00000000 +#define DBG_CTIDBG_DEVAFF0__VAL___M 0xFFFFFFFF +#define DBG_CTIDBG_DEVAFF0__VAL___S 0 +#define DBG_CTIDBG_DEVAFF0___M 0xFFFFFFFF +#define DBG_CTIDBG_DEVAFF0___S 0 + +#define DBG_CTIDBG_DEVAFF1 (0x00B94FAC) +#define DBG_CTIDBG_DEVAFF1___RWC QCSR_REG_RO +#define DBG_CTIDBG_DEVAFF1___POR 0x00000000 +#define DBG_CTIDBG_DEVAFF1__VAL___POR 0x00000000 +#define DBG_CTIDBG_DEVAFF1__VAL___M 0xFFFFFFFF +#define DBG_CTIDBG_DEVAFF1__VAL___S 0 +#define DBG_CTIDBG_DEVAFF1___M 0xFFFFFFFF +#define DBG_CTIDBG_DEVAFF1___S 0 + +#define DBG_CTIDBG_LAR (0x00B94FB0) +#define DBG_CTIDBG_LAR___RWC QCSR_REG_WO +#define DBG_CTIDBG_LAR__ACCESS_W___M 0xFFFFFFFF +#define DBG_CTIDBG_LAR__ACCESS_W___S 0 +#define DBG_CTIDBG_LAR__ACCESS_W__UNLOCK 0xC5ACCE55 +#define DBG_CTIDBG_LAR___M 0xFFFFFFFF +#define DBG_CTIDBG_LAR___S 0 + +#define DBG_CTIDBG_LSR (0x00B94FB4) +#define DBG_CTIDBG_LSR___RWC QCSR_REG_RO +#define DBG_CTIDBG_LSR___POR 0x00000003 +#define DBG_CTIDBG_LSR__LOCKTYPE___POR 0x0 +#define DBG_CTIDBG_LSR__LOCKGRANT___POR 0x1 +#define DBG_CTIDBG_LSR__LOCKEXIST___POR 0x1 +#define DBG_CTIDBG_LSR__LOCKTYPE___M 0x00000004 +#define DBG_CTIDBG_LSR__LOCKTYPE___S 2 +#define DBG_CTIDBG_LSR__LOCKTYPE__SIZE_32BIT 0x0 +#define DBG_CTIDBG_LSR__LOCKGRANT___M 0x00000002 +#define DBG_CTIDBG_LSR__LOCKGRANT___S 1 +#define DBG_CTIDBG_LSR__LOCKGRANT__ACCESS_PERMITTED 0x0 +#define DBG_CTIDBG_LSR__LOCKGRANT__DEVICE_LOCKED 0x1 +#define DBG_CTIDBG_LSR__LOCKEXIST___M 0x00000001 +#define DBG_CTIDBG_LSR__LOCKEXIST___S 0 +#define DBG_CTIDBG_LSR__LOCKEXIST__LOCK_NOT_PRESENT 0x0 +#define DBG_CTIDBG_LSR__LOCKEXIST__LOCK_PRESENT 0x1 +#define DBG_CTIDBG_LSR___M 0x00000007 +#define DBG_CTIDBG_LSR___S 0 + +#define DBG_CTIDBG_AUTHSTATUS (0x00B94FB8) +#define DBG_CTIDBG_AUTHSTATUS___RWC QCSR_REG_RO +#define DBG_CTIDBG_AUTHSTATUS__SNID___M 0x000000C0 +#define DBG_CTIDBG_AUTHSTATUS__SNID___S 6 +#define DBG_CTIDBG_AUTHSTATUS__SNID__NOT_IMPLEMENTED 0x0 +#define DBG_CTIDBG_AUTHSTATUS__SID___M 0x00000030 +#define DBG_CTIDBG_AUTHSTATUS__SID___S 4 +#define DBG_CTIDBG_AUTHSTATUS__SID__NOT_IMPLEMENTED 0x0 +#define DBG_CTIDBG_AUTHSTATUS__NSNID___M 0x0000000C +#define DBG_CTIDBG_AUTHSTATUS__NSNID___S 2 +#define DBG_CTIDBG_AUTHSTATUS__NSNID__DISABLED 0x2 +#define DBG_CTIDBG_AUTHSTATUS__NSNID__ENABLED 0x3 +#define DBG_CTIDBG_AUTHSTATUS__NSID___M 0x00000003 +#define DBG_CTIDBG_AUTHSTATUS__NSID___S 0 +#define DBG_CTIDBG_AUTHSTATUS__NSID__DISABLED 0x2 +#define DBG_CTIDBG_AUTHSTATUS__NSID__ENABLED 0x3 +#define DBG_CTIDBG_AUTHSTATUS___M 0x000000FF +#define DBG_CTIDBG_AUTHSTATUS___S 0 + +#define DBG_CTIDBG_DEVARCH (0x00B94FBC) +#define DBG_CTIDBG_DEVARCH___RWC QCSR_REG_RO +#define DBG_CTIDBG_DEVARCH___POR 0x8EF00A14 +#define DBG_CTIDBG_DEVARCH__ARCHITECT___POR 0x477 +#define DBG_CTIDBG_DEVARCH__PRESENT___POR 0x1 +#define DBG_CTIDBG_DEVARCH__REVISION___POR 0x0 +#define DBG_CTIDBG_DEVARCH__ARCHID___POR 0x0A14 +#define DBG_CTIDBG_DEVARCH__ARCHITECT___M 0xFFE00000 +#define DBG_CTIDBG_DEVARCH__ARCHITECT___S 21 +#define DBG_CTIDBG_DEVARCH__PRESENT___M 0x00100000 +#define DBG_CTIDBG_DEVARCH__PRESENT___S 20 +#define DBG_CTIDBG_DEVARCH__REVISION___M 0x000F0000 +#define DBG_CTIDBG_DEVARCH__REVISION___S 16 +#define DBG_CTIDBG_DEVARCH__ARCHID___M 0x0000FFFF +#define DBG_CTIDBG_DEVARCH__ARCHID___S 0 +#define DBG_CTIDBG_DEVARCH___M 0xFFFFFFFF +#define DBG_CTIDBG_DEVARCH___S 0 + +#define DBG_CTIDBG_DEVID2 (0x00B94FC0) +#define DBG_CTIDBG_DEVID2___RWC QCSR_REG_RO +#define DBG_CTIDBG_DEVID2___POR 0x00000000 +#define DBG_CTIDBG_DEVID2__IMPLDEF___POR 0x0 +#define DBG_CTIDBG_DEVID2__IMPLDEF___M 0x00000001 +#define DBG_CTIDBG_DEVID2__IMPLDEF___S 0 +#define DBG_CTIDBG_DEVID2___M 0x00000001 +#define DBG_CTIDBG_DEVID2___S 0 + +#define DBG_CTIDBG_DEVID1 (0x00B94FC4) +#define DBG_CTIDBG_DEVID1___RWC QCSR_REG_RO +#define DBG_CTIDBG_DEVID1___POR 0x00000000 +#define DBG_CTIDBG_DEVID1__IMPLDEF___POR 0x0 +#define DBG_CTIDBG_DEVID1__IMPLDEF___M 0x00000001 +#define DBG_CTIDBG_DEVID1__IMPLDEF___S 0 +#define DBG_CTIDBG_DEVID1___M 0x00000001 +#define DBG_CTIDBG_DEVID1___S 0 + +#define DBG_CTIDBG_DEVID (0x00B94FC8) +#define DBG_CTIDBG_DEVID___RWC QCSR_REG_RO +#define DBG_CTIDBG_DEVID___POR 0x00082000 +#define DBG_CTIDBG_DEVID__NUMCH___POR 0x8 +#define DBG_CTIDBG_DEVID__NUMTRIG___POR 0x20 +#define DBG_CTIDBG_DEVID__EXTMUXNUM___POR 0x00 +#define DBG_CTIDBG_DEVID__NUMCH___M 0x003F0000 +#define DBG_CTIDBG_DEVID__NUMCH___S 16 +#define DBG_CTIDBG_DEVID__NUMTRIG___M 0x0000FF00 +#define DBG_CTIDBG_DEVID__NUMTRIG___S 8 +#define DBG_CTIDBG_DEVID__EXTMUXNUM___M 0x0000001F +#define DBG_CTIDBG_DEVID__EXTMUXNUM___S 0 +#define DBG_CTIDBG_DEVID___M 0x003FFF1F +#define DBG_CTIDBG_DEVID___S 0 + +#define DBG_CTIDBG_DEVTYPE (0x00B94FCC) +#define DBG_CTIDBG_DEVTYPE___RWC QCSR_REG_RO +#define DBG_CTIDBG_DEVTYPE___POR 0x00000014 +#define DBG_CTIDBG_DEVTYPE__SUB_TYPE___POR 0x1 +#define DBG_CTIDBG_DEVTYPE__MAJOR_TYPE___POR 0x4 +#define DBG_CTIDBG_DEVTYPE__SUB_TYPE___M 0x000000F0 +#define DBG_CTIDBG_DEVTYPE__SUB_TYPE___S 4 +#define DBG_CTIDBG_DEVTYPE__SUB_TYPE__TRIGGER_MATRIX 0x1 +#define DBG_CTIDBG_DEVTYPE__MAJOR_TYPE___M 0x0000000F +#define DBG_CTIDBG_DEVTYPE__MAJOR_TYPE___S 0 +#define DBG_CTIDBG_DEVTYPE__MAJOR_TYPE__DEBUG_CONTROL 0x4 +#define DBG_CTIDBG_DEVTYPE___M 0x000000FF +#define DBG_CTIDBG_DEVTYPE___S 0 + +#define DBG_CTIDBG_PIDR0 (0x00B94FE0) +#define DBG_CTIDBG_PIDR0___RWC QCSR_REG_RO +#define DBG_CTIDBG_PIDR0___POR 0x00000006 +#define DBG_CTIDBG_PIDR0__PART_0___POR 0x06 +#define DBG_CTIDBG_PIDR0__PART_0___M 0x000000FF +#define DBG_CTIDBG_PIDR0__PART_0___S 0 +#define DBG_CTIDBG_PIDR0__PART_0__CTI_PART_NUMBER_7_0 0x06 +#define DBG_CTIDBG_PIDR0___M 0x000000FF +#define DBG_CTIDBG_PIDR0___S 0 + +#define DBG_CTIDBG_PIDR1 (0x00B94FE4) +#define DBG_CTIDBG_PIDR1___RWC QCSR_REG_RO +#define DBG_CTIDBG_PIDR1___POR 0x000000B9 +#define DBG_CTIDBG_PIDR1__DES_0___POR 0xB +#define DBG_CTIDBG_PIDR1__PART_1___POR 0x9 +#define DBG_CTIDBG_PIDR1__DES_0___M 0x000000F0 +#define DBG_CTIDBG_PIDR1__DES_0___S 4 +#define DBG_CTIDBG_PIDR1__DES_0__ARM_JEP106_IDENTITY_CODE_3_0 0xB +#define DBG_CTIDBG_PIDR1__PART_1___M 0x0000000F +#define DBG_CTIDBG_PIDR1__PART_1___S 0 +#define DBG_CTIDBG_PIDR1__PART_1__CTI_PART_NUMBER_11_8 0x9 +#define DBG_CTIDBG_PIDR1___M 0x000000FF +#define DBG_CTIDBG_PIDR1___S 0 + +#define DBG_CTIDBG_PIDR2 (0x00B94FE8) +#define DBG_CTIDBG_PIDR2___RWC QCSR_REG_RO +#define DBG_CTIDBG_PIDR2___POR 0x0000004B +#define DBG_CTIDBG_PIDR2__REVISION___POR 0x4 +#define DBG_CTIDBG_PIDR2__JEDEC___POR 0x1 +#define DBG_CTIDBG_PIDR2__DES_1___POR 0x3 +#define DBG_CTIDBG_PIDR2__REVISION___M 0x000000F0 +#define DBG_CTIDBG_PIDR2__REVISION___S 4 +#define DBG_CTIDBG_PIDR2__REVISION__R0P4 0x4 +#define DBG_CTIDBG_PIDR2__REVISION__R0P5 0x5 +#define DBG_CTIDBG_PIDR2__JEDEC___M 0x00000008 +#define DBG_CTIDBG_PIDR2__JEDEC___S 3 +#define DBG_CTIDBG_PIDR2__JEDEC__JEDEC_IDENTITY 0x1 +#define DBG_CTIDBG_PIDR2__DES_1___M 0x00000007 +#define DBG_CTIDBG_PIDR2__DES_1___S 0 +#define DBG_CTIDBG_PIDR2__DES_1__ARM_JEP106_IDENTITY_CODE_6_4 0x3 +#define DBG_CTIDBG_PIDR2___M 0x000000FF +#define DBG_CTIDBG_PIDR2___S 0 + +#define DBG_CTIDBG_PIDR3 (0x00B94FEC) +#define DBG_CTIDBG_PIDR3___RWC QCSR_REG_RO +#define DBG_CTIDBG_PIDR3___POR 0x00000000 +#define DBG_CTIDBG_PIDR3__REVAND___POR 0x0 +#define DBG_CTIDBG_PIDR3__CMOD___POR 0x0 +#define DBG_CTIDBG_PIDR3__REVAND___M 0x000000F0 +#define DBG_CTIDBG_PIDR3__REVAND___S 4 +#define DBG_CTIDBG_PIDR3__REVAND__NO_MODIFICATION 0x0 +#define DBG_CTIDBG_PIDR3__CMOD___M 0x0000000F +#define DBG_CTIDBG_PIDR3__CMOD___S 0 +#define DBG_CTIDBG_PIDR3__CMOD__NO_MODIFICATION 0x0 +#define DBG_CTIDBG_PIDR3___M 0x000000FF +#define DBG_CTIDBG_PIDR3___S 0 + +#define DBG_CTIDBG_PIDR4 (0x00B94FD0) +#define DBG_CTIDBG_PIDR4___RWC QCSR_REG_RO +#define DBG_CTIDBG_PIDR4___POR 0x00000004 +#define DBG_CTIDBG_PIDR4__SIZE___POR 0x0 +#define DBG_CTIDBG_PIDR4__DES_2___POR 0x4 +#define DBG_CTIDBG_PIDR4__SIZE___M 0x000000F0 +#define DBG_CTIDBG_PIDR4__SIZE___S 4 +#define DBG_CTIDBG_PIDR4__SIZE__SIZE_4KB 0x0 +#define DBG_CTIDBG_PIDR4__DES_2___M 0x0000000F +#define DBG_CTIDBG_PIDR4__DES_2___S 0 +#define DBG_CTIDBG_PIDR4__DES_2__ARM_JEP106_CONTINUATION_CODE 0x4 +#define DBG_CTIDBG_PIDR4___M 0x000000FF +#define DBG_CTIDBG_PIDR4___S 0 + +#define DBG_CTIDBG_PIDR5 (0x00B94FD4) +#define DBG_CTIDBG_PIDR5___RWC QCSR_REG_RW +#define DBG_CTIDBG_PIDR5__PERIPHID5___M 0xFFFFFFFF +#define DBG_CTIDBG_PIDR5__PERIPHID5___S 0 +#define DBG_CTIDBG_PIDR5___M 0xFFFFFFFF +#define DBG_CTIDBG_PIDR5___S 0 + +#define DBG_CTIDBG_PIDR6 (0x00B94FD8) +#define DBG_CTIDBG_PIDR6___RWC QCSR_REG_RW +#define DBG_CTIDBG_PIDR6__PERIPHID6___M 0xFFFFFFFF +#define DBG_CTIDBG_PIDR6__PERIPHID6___S 0 +#define DBG_CTIDBG_PIDR6___M 0xFFFFFFFF +#define DBG_CTIDBG_PIDR6___S 0 + +#define DBG_CTIDBG_PIDR7 (0x00B94FDC) +#define DBG_CTIDBG_PIDR7___RWC QCSR_REG_RW +#define DBG_CTIDBG_PIDR7__PERIPHID7___M 0xFFFFFFFF +#define DBG_CTIDBG_PIDR7__PERIPHID7___S 0 +#define DBG_CTIDBG_PIDR7___M 0xFFFFFFFF +#define DBG_CTIDBG_PIDR7___S 0 + +#define DBG_CTIDBG_CIDR0 (0x00B94FF0) +#define DBG_CTIDBG_CIDR0___RWC QCSR_REG_RO +#define DBG_CTIDBG_CIDR0___POR 0x0000000D +#define DBG_CTIDBG_CIDR0__PRMBL_0___POR 0x0D +#define DBG_CTIDBG_CIDR0__PRMBL_0___M 0x000000FF +#define DBG_CTIDBG_CIDR0__PRMBL_0___S 0 +#define DBG_CTIDBG_CIDR0__PRMBL_0__ID_VALUE_0D 0x0D +#define DBG_CTIDBG_CIDR0___M 0x000000FF +#define DBG_CTIDBG_CIDR0___S 0 + +#define DBG_CTIDBG_CIDR1 (0x00B94FF4) +#define DBG_CTIDBG_CIDR1___RWC QCSR_REG_RO +#define DBG_CTIDBG_CIDR1___POR 0x00000090 +#define DBG_CTIDBG_CIDR1__CLASS___POR 0x9 +#define DBG_CTIDBG_CIDR1__PRMBL_1___POR 0x0 +#define DBG_CTIDBG_CIDR1__CLASS___M 0x000000F0 +#define DBG_CTIDBG_CIDR1__CLASS___S 4 +#define DBG_CTIDBG_CIDR1__CLASS__CORESIGHT_COMPONENT 0x9 +#define DBG_CTIDBG_CIDR1__PRMBL_1___M 0x0000000F +#define DBG_CTIDBG_CIDR1__PRMBL_1___S 0 +#define DBG_CTIDBG_CIDR1__PRMBL_1__ID_VALUE_0 0x0 +#define DBG_CTIDBG_CIDR1___M 0x000000FF +#define DBG_CTIDBG_CIDR1___S 0 + +#define DBG_CTIDBG_CIDR2 (0x00B94FF8) +#define DBG_CTIDBG_CIDR2___RWC QCSR_REG_RO +#define DBG_CTIDBG_CIDR2___POR 0x00000005 +#define DBG_CTIDBG_CIDR2__PRMBL_2___POR 0x05 +#define DBG_CTIDBG_CIDR2__PRMBL_2___M 0x000000FF +#define DBG_CTIDBG_CIDR2__PRMBL_2___S 0 +#define DBG_CTIDBG_CIDR2__PRMBL_2__ID_VALUE_05 0x05 +#define DBG_CTIDBG_CIDR2___M 0x000000FF +#define DBG_CTIDBG_CIDR2___S 0 + +#define DBG_CTIDBG_CIDR3 (0x00B94FFC) +#define DBG_CTIDBG_CIDR3___RWC QCSR_REG_RO +#define DBG_CTIDBG_CIDR3___POR 0x000000B1 +#define DBG_CTIDBG_CIDR3__PRMBL_3___POR 0xB1 +#define DBG_CTIDBG_CIDR3__PRMBL_3___M 0x000000FF +#define DBG_CTIDBG_CIDR3__PRMBL_3___S 0 +#define DBG_CTIDBG_CIDR3__PRMBL_3__ID_VALUE_B1 0xB1 +#define DBG_CTIDBG_CIDR3___M 0x000000FF +#define DBG_CTIDBG_CIDR3___S 0 + +#define DBG_CTINOC_CTICONTROL (0x00B95000) +#define DBG_CTINOC_CTICONTROL___RWC QCSR_REG_RW +#define DBG_CTINOC_CTICONTROL___POR 0x00000000 +#define DBG_CTINOC_CTICONTROL__GLBEN___POR 0x0 +#define DBG_CTINOC_CTICONTROL__GLBEN___M 0x00000001 +#define DBG_CTINOC_CTICONTROL__GLBEN___S 0 +#define DBG_CTINOC_CTICONTROL__GLBEN__DISABLED 0x0 +#define DBG_CTINOC_CTICONTROL__GLBEN__ENABLED 0x1 +#define DBG_CTINOC_CTICONTROL___M 0x00000001 +#define DBG_CTINOC_CTICONTROL___S 0 + +#define DBG_CTINOC_CTIINTACK (0x00B95010) +#define DBG_CTINOC_CTIINTACK___RWC QCSR_REG_WO +#define DBG_CTINOC_CTIINTACK___POR 0x00000000 +#define DBG_CTINOC_CTIINTACK__INTACK___POR 0x00 +#define DBG_CTINOC_CTIINTACK__INTACK___M 0x000000FF +#define DBG_CTINOC_CTIINTACK__INTACK___S 0 +#define DBG_CTINOC_CTIINTACK___M 0x000000FF +#define DBG_CTINOC_CTIINTACK___S 0 + +#define DBG_CTINOC_CTIAPPSET (0x00B95014) +#define DBG_CTINOC_CTIAPPSET___RWC QCSR_REG_RW +#define DBG_CTINOC_CTIAPPSET___POR 0x00000000 +#define DBG_CTINOC_CTIAPPSET__APPSET___POR 0x00 +#define DBG_CTINOC_CTIAPPSET__APPSET___M 0x000000FF +#define DBG_CTINOC_CTIAPPSET__APPSET___S 0 +#define DBG_CTINOC_CTIAPPSET___M 0x000000FF +#define DBG_CTINOC_CTIAPPSET___S 0 + +#define DBG_CTINOC_CTIAPPCLEAR (0x00B95018) +#define DBG_CTINOC_CTIAPPCLEAR___RWC QCSR_REG_WO +#define DBG_CTINOC_CTIAPPCLEAR___POR 0x00000000 +#define DBG_CTINOC_CTIAPPCLEAR__APPCLEAR___POR 0x00 +#define DBG_CTINOC_CTIAPPCLEAR__APPCLEAR___M 0x000000FF +#define DBG_CTINOC_CTIAPPCLEAR__APPCLEAR___S 0 +#define DBG_CTINOC_CTIAPPCLEAR___M 0x000000FF +#define DBG_CTINOC_CTIAPPCLEAR___S 0 + +#define DBG_CTINOC_CTIAPPPULSE (0x00B9501C) +#define DBG_CTINOC_CTIAPPPULSE___RWC QCSR_REG_WO +#define DBG_CTINOC_CTIAPPPULSE___POR 0x00000000 +#define DBG_CTINOC_CTIAPPPULSE__APPULSE___POR 0x00 +#define DBG_CTINOC_CTIAPPPULSE__APPULSE___M 0x000000FF +#define DBG_CTINOC_CTIAPPPULSE__APPULSE___S 0 +#define DBG_CTINOC_CTIAPPPULSE___M 0x000000FF +#define DBG_CTINOC_CTIAPPPULSE___S 0 + +#define DBG_CTINOC_CTIINEN0 (0x00B95020) +#define DBG_CTINOC_CTIINEN0___RWC QCSR_REG_RW +#define DBG_CTINOC_CTIINEN0___POR 0x00000000 +#define DBG_CTINOC_CTIINEN0__TRIGINEN___POR 0x00 +#define DBG_CTINOC_CTIINEN0__TRIGINEN___M 0x000000FF +#define DBG_CTINOC_CTIINEN0__TRIGINEN___S 0 +#define DBG_CTINOC_CTIINEN0___M 0x000000FF +#define DBG_CTINOC_CTIINEN0___S 0 + +#define DBG_CTINOC_CTIINEN1 (0x00B95024) +#define DBG_CTINOC_CTIINEN1___RWC QCSR_REG_RW +#define DBG_CTINOC_CTIINEN1___POR 0x00000000 +#define DBG_CTINOC_CTIINEN1__TRIGINEN___POR 0x00 +#define DBG_CTINOC_CTIINEN1__TRIGINEN___M 0x000000FF +#define DBG_CTINOC_CTIINEN1__TRIGINEN___S 0 +#define DBG_CTINOC_CTIINEN1___M 0x000000FF +#define DBG_CTINOC_CTIINEN1___S 0 + +#define DBG_CTINOC_CTIINEN2 (0x00B95028) +#define DBG_CTINOC_CTIINEN2___RWC QCSR_REG_RW +#define DBG_CTINOC_CTIINEN2___POR 0x00000000 +#define DBG_CTINOC_CTIINEN2__TRIGINEN___POR 0x00 +#define DBG_CTINOC_CTIINEN2__TRIGINEN___M 0x000000FF +#define DBG_CTINOC_CTIINEN2__TRIGINEN___S 0 +#define DBG_CTINOC_CTIINEN2___M 0x000000FF +#define DBG_CTINOC_CTIINEN2___S 0 + +#define DBG_CTINOC_CTIINEN3 (0x00B9502C) +#define DBG_CTINOC_CTIINEN3___RWC QCSR_REG_RW +#define DBG_CTINOC_CTIINEN3___POR 0x00000000 +#define DBG_CTINOC_CTIINEN3__TRIGINEN___POR 0x00 +#define DBG_CTINOC_CTIINEN3__TRIGINEN___M 0x000000FF +#define DBG_CTINOC_CTIINEN3__TRIGINEN___S 0 +#define DBG_CTINOC_CTIINEN3___M 0x000000FF +#define DBG_CTINOC_CTIINEN3___S 0 + +#define DBG_CTINOC_CTIINEN4 (0x00B95030) +#define DBG_CTINOC_CTIINEN4___RWC QCSR_REG_RW +#define DBG_CTINOC_CTIINEN4___POR 0x00000000 +#define DBG_CTINOC_CTIINEN4__TRIGINEN___POR 0x00 +#define DBG_CTINOC_CTIINEN4__TRIGINEN___M 0x000000FF +#define DBG_CTINOC_CTIINEN4__TRIGINEN___S 0 +#define DBG_CTINOC_CTIINEN4___M 0x000000FF +#define DBG_CTINOC_CTIINEN4___S 0 + +#define DBG_CTINOC_CTIINEN5 (0x00B95034) +#define DBG_CTINOC_CTIINEN5___RWC QCSR_REG_RW +#define DBG_CTINOC_CTIINEN5___POR 0x00000000 +#define DBG_CTINOC_CTIINEN5__TRIGINEN___POR 0x00 +#define DBG_CTINOC_CTIINEN5__TRIGINEN___M 0x000000FF +#define DBG_CTINOC_CTIINEN5__TRIGINEN___S 0 +#define DBG_CTINOC_CTIINEN5___M 0x000000FF +#define DBG_CTINOC_CTIINEN5___S 0 + +#define DBG_CTINOC_CTIINEN6 (0x00B95038) +#define DBG_CTINOC_CTIINEN6___RWC QCSR_REG_RW +#define DBG_CTINOC_CTIINEN6___POR 0x00000000 +#define DBG_CTINOC_CTIINEN6__TRIGINEN___POR 0x00 +#define DBG_CTINOC_CTIINEN6__TRIGINEN___M 0x000000FF +#define DBG_CTINOC_CTIINEN6__TRIGINEN___S 0 +#define DBG_CTINOC_CTIINEN6___M 0x000000FF +#define DBG_CTINOC_CTIINEN6___S 0 + +#define DBG_CTINOC_CTIINEN7 (0x00B9503C) +#define DBG_CTINOC_CTIINEN7___RWC QCSR_REG_RW +#define DBG_CTINOC_CTIINEN7___POR 0x00000000 +#define DBG_CTINOC_CTIINEN7__TRIGINEN___POR 0x00 +#define DBG_CTINOC_CTIINEN7__TRIGINEN___M 0x000000FF +#define DBG_CTINOC_CTIINEN7__TRIGINEN___S 0 +#define DBG_CTINOC_CTIINEN7___M 0x000000FF +#define DBG_CTINOC_CTIINEN7___S 0 + +#define DBG_CTINOC_CTIOUTEN0 (0x00B950A0) +#define DBG_CTINOC_CTIOUTEN0___RWC QCSR_REG_RW +#define DBG_CTINOC_CTIOUTEN0___POR 0x00000000 +#define DBG_CTINOC_CTIOUTEN0__TRIGOUTEN___POR 0x00 +#define DBG_CTINOC_CTIOUTEN0__TRIGOUTEN___M 0x000000FF +#define DBG_CTINOC_CTIOUTEN0__TRIGOUTEN___S 0 +#define DBG_CTINOC_CTIOUTEN0___M 0x000000FF +#define DBG_CTINOC_CTIOUTEN0___S 0 + +#define DBG_CTINOC_CTIOUTEN1 (0x00B950A4) +#define DBG_CTINOC_CTIOUTEN1___RWC QCSR_REG_RW +#define DBG_CTINOC_CTIOUTEN1___POR 0x00000000 +#define DBG_CTINOC_CTIOUTEN1__TRIGOUTEN___POR 0x00 +#define DBG_CTINOC_CTIOUTEN1__TRIGOUTEN___M 0x000000FF +#define DBG_CTINOC_CTIOUTEN1__TRIGOUTEN___S 0 +#define DBG_CTINOC_CTIOUTEN1___M 0x000000FF +#define DBG_CTINOC_CTIOUTEN1___S 0 + +#define DBG_CTINOC_CTIOUTEN2 (0x00B950A8) +#define DBG_CTINOC_CTIOUTEN2___RWC QCSR_REG_RW +#define DBG_CTINOC_CTIOUTEN2___POR 0x00000000 +#define DBG_CTINOC_CTIOUTEN2__TRIGOUTEN___POR 0x00 +#define DBG_CTINOC_CTIOUTEN2__TRIGOUTEN___M 0x000000FF +#define DBG_CTINOC_CTIOUTEN2__TRIGOUTEN___S 0 +#define DBG_CTINOC_CTIOUTEN2___M 0x000000FF +#define DBG_CTINOC_CTIOUTEN2___S 0 + +#define DBG_CTINOC_CTIOUTEN3 (0x00B950AC) +#define DBG_CTINOC_CTIOUTEN3___RWC QCSR_REG_RW +#define DBG_CTINOC_CTIOUTEN3___POR 0x00000000 +#define DBG_CTINOC_CTIOUTEN3__TRIGOUTEN___POR 0x00 +#define DBG_CTINOC_CTIOUTEN3__TRIGOUTEN___M 0x000000FF +#define DBG_CTINOC_CTIOUTEN3__TRIGOUTEN___S 0 +#define DBG_CTINOC_CTIOUTEN3___M 0x000000FF +#define DBG_CTINOC_CTIOUTEN3___S 0 + +#define DBG_CTINOC_CTIOUTEN4 (0x00B950B0) +#define DBG_CTINOC_CTIOUTEN4___RWC QCSR_REG_RW +#define DBG_CTINOC_CTIOUTEN4___POR 0x00000000 +#define DBG_CTINOC_CTIOUTEN4__TRIGOUTEN___POR 0x00 +#define DBG_CTINOC_CTIOUTEN4__TRIGOUTEN___M 0x000000FF +#define DBG_CTINOC_CTIOUTEN4__TRIGOUTEN___S 0 +#define DBG_CTINOC_CTIOUTEN4___M 0x000000FF +#define DBG_CTINOC_CTIOUTEN4___S 0 + +#define DBG_CTINOC_CTIOUTEN5 (0x00B950B4) +#define DBG_CTINOC_CTIOUTEN5___RWC QCSR_REG_RW +#define DBG_CTINOC_CTIOUTEN5___POR 0x00000000 +#define DBG_CTINOC_CTIOUTEN5__TRIGOUTEN___POR 0x00 +#define DBG_CTINOC_CTIOUTEN5__TRIGOUTEN___M 0x000000FF +#define DBG_CTINOC_CTIOUTEN5__TRIGOUTEN___S 0 +#define DBG_CTINOC_CTIOUTEN5___M 0x000000FF +#define DBG_CTINOC_CTIOUTEN5___S 0 + +#define DBG_CTINOC_CTIOUTEN6 (0x00B950B8) +#define DBG_CTINOC_CTIOUTEN6___RWC QCSR_REG_RW +#define DBG_CTINOC_CTIOUTEN6___POR 0x00000000 +#define DBG_CTINOC_CTIOUTEN6__TRIGOUTEN___POR 0x00 +#define DBG_CTINOC_CTIOUTEN6__TRIGOUTEN___M 0x000000FF +#define DBG_CTINOC_CTIOUTEN6__TRIGOUTEN___S 0 +#define DBG_CTINOC_CTIOUTEN6___M 0x000000FF +#define DBG_CTINOC_CTIOUTEN6___S 0 + +#define DBG_CTINOC_CTIOUTEN7 (0x00B950BC) +#define DBG_CTINOC_CTIOUTEN7___RWC QCSR_REG_RW +#define DBG_CTINOC_CTIOUTEN7___POR 0x00000000 +#define DBG_CTINOC_CTIOUTEN7__TRIGOUTEN___POR 0x00 +#define DBG_CTINOC_CTIOUTEN7__TRIGOUTEN___M 0x000000FF +#define DBG_CTINOC_CTIOUTEN7__TRIGOUTEN___S 0 +#define DBG_CTINOC_CTIOUTEN7___M 0x000000FF +#define DBG_CTINOC_CTIOUTEN7___S 0 + +#define DBG_CTINOC_CTITRIGINSTATUS (0x00B95130) +#define DBG_CTINOC_CTITRIGINSTATUS___RWC QCSR_REG_RO +#define DBG_CTINOC_CTITRIGINSTATUS__TRIGINSTATUS___M 0x000000FF +#define DBG_CTINOC_CTITRIGINSTATUS__TRIGINSTATUS___S 0 +#define DBG_CTINOC_CTITRIGINSTATUS___M 0x000000FF +#define DBG_CTINOC_CTITRIGINSTATUS___S 0 + +#define DBG_CTINOC_CTITRIGOUTSTATUS (0x00B95134) +#define DBG_CTINOC_CTITRIGOUTSTATUS___RWC QCSR_REG_RO +#define DBG_CTINOC_CTITRIGOUTSTATUS___POR 0x00000000 +#define DBG_CTINOC_CTITRIGOUTSTATUS__TRIGOUTSTATUS___POR 0x00 +#define DBG_CTINOC_CTITRIGOUTSTATUS__TRIGOUTSTATUS___M 0x000000FF +#define DBG_CTINOC_CTITRIGOUTSTATUS__TRIGOUTSTATUS___S 0 +#define DBG_CTINOC_CTITRIGOUTSTATUS___M 0x000000FF +#define DBG_CTINOC_CTITRIGOUTSTATUS___S 0 + +#define DBG_CTINOC_CTICHINSTATUS (0x00B95138) +#define DBG_CTINOC_CTICHINSTATUS___RWC QCSR_REG_RO +#define DBG_CTINOC_CTICHINSTATUS__CTICHINSTATUS___M 0x000000FF +#define DBG_CTINOC_CTICHINSTATUS__CTICHINSTATUS___S 0 +#define DBG_CTINOC_CTICHINSTATUS___M 0x000000FF +#define DBG_CTINOC_CTICHINSTATUS___S 0 + +#define DBG_CTINOC_CTICHOUTSTATUS (0x00B9513C) +#define DBG_CTINOC_CTICHOUTSTATUS___RWC QCSR_REG_RO +#define DBG_CTINOC_CTICHOUTSTATUS___POR 0x00000000 +#define DBG_CTINOC_CTICHOUTSTATUS__CTICHOUTSTATUS___POR 0x00 +#define DBG_CTINOC_CTICHOUTSTATUS__CTICHOUTSTATUS___M 0x000000FF +#define DBG_CTINOC_CTICHOUTSTATUS__CTICHOUTSTATUS___S 0 +#define DBG_CTINOC_CTICHOUTSTATUS___M 0x000000FF +#define DBG_CTINOC_CTICHOUTSTATUS___S 0 + +#define DBG_CTINOC_CTIGATE (0x00B95140) +#define DBG_CTINOC_CTIGATE___RWC QCSR_REG_RW +#define DBG_CTINOC_CTIGATE___POR 0x000000FF +#define DBG_CTINOC_CTIGATE__CTIGATEEN7___POR 0x1 +#define DBG_CTINOC_CTIGATE__CTIGATEEN6___POR 0x1 +#define DBG_CTINOC_CTIGATE__CTIGATEEN5___POR 0x1 +#define DBG_CTINOC_CTIGATE__CTIGATEEN4___POR 0x1 +#define DBG_CTINOC_CTIGATE__CTIGATEEN3___POR 0x1 +#define DBG_CTINOC_CTIGATE__CTIGATEEN2___POR 0x1 +#define DBG_CTINOC_CTIGATE__CTIGATEEN1___POR 0x1 +#define DBG_CTINOC_CTIGATE__CTIGATEEN0___POR 0x1 +#define DBG_CTINOC_CTIGATE__CTIGATEEN7___M 0x00000080 +#define DBG_CTINOC_CTIGATE__CTIGATEEN7___S 7 +#define DBG_CTINOC_CTIGATE__CTIGATEEN6___M 0x00000040 +#define DBG_CTINOC_CTIGATE__CTIGATEEN6___S 6 +#define DBG_CTINOC_CTIGATE__CTIGATEEN5___M 0x00000020 +#define DBG_CTINOC_CTIGATE__CTIGATEEN5___S 5 +#define DBG_CTINOC_CTIGATE__CTIGATEEN4___M 0x00000010 +#define DBG_CTINOC_CTIGATE__CTIGATEEN4___S 4 +#define DBG_CTINOC_CTIGATE__CTIGATEEN3___M 0x00000008 +#define DBG_CTINOC_CTIGATE__CTIGATEEN3___S 3 +#define DBG_CTINOC_CTIGATE__CTIGATEEN2___M 0x00000004 +#define DBG_CTINOC_CTIGATE__CTIGATEEN2___S 2 +#define DBG_CTINOC_CTIGATE__CTIGATEEN1___M 0x00000002 +#define DBG_CTINOC_CTIGATE__CTIGATEEN1___S 1 +#define DBG_CTINOC_CTIGATE__CTIGATEEN0___M 0x00000001 +#define DBG_CTINOC_CTIGATE__CTIGATEEN0___S 0 +#define DBG_CTINOC_CTIGATE___M 0x000000FF +#define DBG_CTINOC_CTIGATE___S 0 + +#define DBG_CTINOC_ASICCTL (0x00B95144) +#define DBG_CTINOC_ASICCTL___RWC QCSR_REG_RW +#define DBG_CTINOC_ASICCTL___POR 0x00000000 +#define DBG_CTINOC_ASICCTL__ASICCTL___POR 0x00000000 +#define DBG_CTINOC_ASICCTL__ASICCTL___M 0xFFFFFFFF +#define DBG_CTINOC_ASICCTL__ASICCTL___S 0 +#define DBG_CTINOC_ASICCTL___M 0xFFFFFFFF +#define DBG_CTINOC_ASICCTL___S 0 + +#define DBG_CTINOC_ITCHINACK (0x00B95EDC) +#define DBG_CTINOC_ITCHINACK___RWC QCSR_REG_WO +#define DBG_CTINOC_ITCHINACK___POR 0x00000000 +#define DBG_CTINOC_ITCHINACK__CTCHINACK___POR 0x00 +#define DBG_CTINOC_ITCHINACK__CTCHINACK___M 0x000000FF +#define DBG_CTINOC_ITCHINACK__CTCHINACK___S 0 +#define DBG_CTINOC_ITCHINACK___M 0x000000FF +#define DBG_CTINOC_ITCHINACK___S 0 + +#define DBG_CTINOC_ITTRIGINACK (0x00B95EE0) +#define DBG_CTINOC_ITTRIGINACK___RWC QCSR_REG_WO +#define DBG_CTINOC_ITTRIGINACK___POR 0x00000000 +#define DBG_CTINOC_ITTRIGINACK__CTTRIGINACK___POR 0x00 +#define DBG_CTINOC_ITTRIGINACK__CTTRIGINACK___M 0x000000FF +#define DBG_CTINOC_ITTRIGINACK__CTTRIGINACK___S 0 +#define DBG_CTINOC_ITTRIGINACK___M 0x000000FF +#define DBG_CTINOC_ITTRIGINACK___S 0 + +#define DBG_CTINOC_ITCHOUT (0x00B95EE4) +#define DBG_CTINOC_ITCHOUT___RWC QCSR_REG_WO +#define DBG_CTINOC_ITCHOUT___POR 0x00000000 +#define DBG_CTINOC_ITCHOUT__CTCHOUT___POR 0x00 +#define DBG_CTINOC_ITCHOUT__CTCHOUT___M 0x000000FF +#define DBG_CTINOC_ITCHOUT__CTCHOUT___S 0 +#define DBG_CTINOC_ITCHOUT___M 0x000000FF +#define DBG_CTINOC_ITCHOUT___S 0 + +#define DBG_CTINOC_ITTRIGOUT (0x00B95EE8) +#define DBG_CTINOC_ITTRIGOUT___RWC QCSR_REG_WO +#define DBG_CTINOC_ITTRIGOUT___POR 0x00000000 +#define DBG_CTINOC_ITTRIGOUT__CTTRIGOUT___POR 0x00 +#define DBG_CTINOC_ITTRIGOUT__CTTRIGOUT___M 0x000000FF +#define DBG_CTINOC_ITTRIGOUT__CTTRIGOUT___S 0 +#define DBG_CTINOC_ITTRIGOUT___M 0x000000FF +#define DBG_CTINOC_ITTRIGOUT___S 0 + +#define DBG_CTINOC_ITCHOUTACK (0x00B95EEC) +#define DBG_CTINOC_ITCHOUTACK___RWC QCSR_REG_RO +#define DBG_CTINOC_ITCHOUTACK___POR 0x00000000 +#define DBG_CTINOC_ITCHOUTACK__CTCHOUTACK___POR 0x00 +#define DBG_CTINOC_ITCHOUTACK__CTCHOUTACK___M 0x000000FF +#define DBG_CTINOC_ITCHOUTACK__CTCHOUTACK___S 0 +#define DBG_CTINOC_ITCHOUTACK___M 0x000000FF +#define DBG_CTINOC_ITCHOUTACK___S 0 + +#define DBG_CTINOC_ITTRIGOUTACK (0x00B95EF0) +#define DBG_CTINOC_ITTRIGOUTACK___RWC QCSR_REG_RO +#define DBG_CTINOC_ITTRIGOUTACK___POR 0x00000000 +#define DBG_CTINOC_ITTRIGOUTACK__CTTRIGOUTACK___POR 0x00 +#define DBG_CTINOC_ITTRIGOUTACK__CTTRIGOUTACK___M 0x000000FF +#define DBG_CTINOC_ITTRIGOUTACK__CTTRIGOUTACK___S 0 +#define DBG_CTINOC_ITTRIGOUTACK___M 0x000000FF +#define DBG_CTINOC_ITTRIGOUTACK___S 0 + +#define DBG_CTINOC_ITCHIN (0x00B95EF4) +#define DBG_CTINOC_ITCHIN___RWC QCSR_REG_RO +#define DBG_CTINOC_ITCHIN___POR 0x00000000 +#define DBG_CTINOC_ITCHIN__CTCHIN___POR 0x00 +#define DBG_CTINOC_ITCHIN__CTCHIN___M 0x000000FF +#define DBG_CTINOC_ITCHIN__CTCHIN___S 0 +#define DBG_CTINOC_ITCHIN___M 0x000000FF +#define DBG_CTINOC_ITCHIN___S 0 + +#define DBG_CTINOC_ITTRIGIN (0x00B95EF8) +#define DBG_CTINOC_ITTRIGIN___RWC QCSR_REG_RO +#define DBG_CTINOC_ITTRIGIN___POR 0x00000000 +#define DBG_CTINOC_ITTRIGIN__CTTRIGIN___POR 0x00 +#define DBG_CTINOC_ITTRIGIN__CTTRIGIN___M 0x000000FF +#define DBG_CTINOC_ITTRIGIN__CTTRIGIN___S 0 +#define DBG_CTINOC_ITTRIGIN___M 0x000000FF +#define DBG_CTINOC_ITTRIGIN___S 0 + +#define DBG_CTINOC_ITCTRL (0x00B95F00) +#define DBG_CTINOC_ITCTRL___RWC QCSR_REG_RW +#define DBG_CTINOC_ITCTRL___POR 0x00000000 +#define DBG_CTINOC_ITCTRL__INTEGRATION_MODE___POR 0x0 +#define DBG_CTINOC_ITCTRL__INTEGRATION_MODE___M 0x00000001 +#define DBG_CTINOC_ITCTRL__INTEGRATION_MODE___S 0 +#define DBG_CTINOC_ITCTRL__INTEGRATION_MODE__FUNCTIONAL_MODE 0x0 +#define DBG_CTINOC_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE 0x1 +#define DBG_CTINOC_ITCTRL___M 0x00000001 +#define DBG_CTINOC_ITCTRL___S 0 + +#define DBG_CTINOC_CLAIMSET (0x00B95FA0) +#define DBG_CTINOC_CLAIMSET___RWC QCSR_REG_RW +#define DBG_CTINOC_CLAIMSET___POR 0x0000000F +#define DBG_CTINOC_CLAIMSET__CLAIMSET___POR 0xF +#define DBG_CTINOC_CLAIMSET__CLAIMSET___M 0x0000000F +#define DBG_CTINOC_CLAIMSET__CLAIMSET___S 0 +#define DBG_CTINOC_CLAIMSET__CLAIMSET__CLAIM_TAG_IMPLEMENTED_BITS 0xF +#define DBG_CTINOC_CLAIMSET___M 0x0000000F +#define DBG_CTINOC_CLAIMSET___S 0 + +#define DBG_CTINOC_CLAIMCLR (0x00B95FA4) +#define DBG_CTINOC_CLAIMCLR___RWC QCSR_REG_RW +#define DBG_CTINOC_CLAIMCLR___POR 0x00000000 +#define DBG_CTINOC_CLAIMCLR__CLAIMCLR___POR 0x0 +#define DBG_CTINOC_CLAIMCLR__CLAIMCLR___M 0x0000000F +#define DBG_CTINOC_CLAIMCLR__CLAIMCLR___S 0 +#define DBG_CTINOC_CLAIMCLR___M 0x0000000F +#define DBG_CTINOC_CLAIMCLR___S 0 + +#define DBG_CTINOC_DEVAFF0 (0x00B95FA8) +#define DBG_CTINOC_DEVAFF0___RWC QCSR_REG_RO +#define DBG_CTINOC_DEVAFF0___POR 0x00000000 +#define DBG_CTINOC_DEVAFF0__VAL___POR 0x00000000 +#define DBG_CTINOC_DEVAFF0__VAL___M 0xFFFFFFFF +#define DBG_CTINOC_DEVAFF0__VAL___S 0 +#define DBG_CTINOC_DEVAFF0___M 0xFFFFFFFF +#define DBG_CTINOC_DEVAFF0___S 0 + +#define DBG_CTINOC_DEVAFF1 (0x00B95FAC) +#define DBG_CTINOC_DEVAFF1___RWC QCSR_REG_RO +#define DBG_CTINOC_DEVAFF1___POR 0x00000000 +#define DBG_CTINOC_DEVAFF1__VAL___POR 0x00000000 +#define DBG_CTINOC_DEVAFF1__VAL___M 0xFFFFFFFF +#define DBG_CTINOC_DEVAFF1__VAL___S 0 +#define DBG_CTINOC_DEVAFF1___M 0xFFFFFFFF +#define DBG_CTINOC_DEVAFF1___S 0 + +#define DBG_CTINOC_LAR (0x00B95FB0) +#define DBG_CTINOC_LAR___RWC QCSR_REG_WO +#define DBG_CTINOC_LAR__ACCESS_W___M 0xFFFFFFFF +#define DBG_CTINOC_LAR__ACCESS_W___S 0 +#define DBG_CTINOC_LAR__ACCESS_W__UNLOCK 0xC5ACCE55 +#define DBG_CTINOC_LAR___M 0xFFFFFFFF +#define DBG_CTINOC_LAR___S 0 + +#define DBG_CTINOC_LSR (0x00B95FB4) +#define DBG_CTINOC_LSR___RWC QCSR_REG_RO +#define DBG_CTINOC_LSR___POR 0x00000003 +#define DBG_CTINOC_LSR__LOCKTYPE___POR 0x0 +#define DBG_CTINOC_LSR__LOCKGRANT___POR 0x1 +#define DBG_CTINOC_LSR__LOCKEXIST___POR 0x1 +#define DBG_CTINOC_LSR__LOCKTYPE___M 0x00000004 +#define DBG_CTINOC_LSR__LOCKTYPE___S 2 +#define DBG_CTINOC_LSR__LOCKTYPE__SIZE_32BIT 0x0 +#define DBG_CTINOC_LSR__LOCKGRANT___M 0x00000002 +#define DBG_CTINOC_LSR__LOCKGRANT___S 1 +#define DBG_CTINOC_LSR__LOCKGRANT__ACCESS_PERMITTED 0x0 +#define DBG_CTINOC_LSR__LOCKGRANT__DEVICE_LOCKED 0x1 +#define DBG_CTINOC_LSR__LOCKEXIST___M 0x00000001 +#define DBG_CTINOC_LSR__LOCKEXIST___S 0 +#define DBG_CTINOC_LSR__LOCKEXIST__LOCK_NOT_PRESENT 0x0 +#define DBG_CTINOC_LSR__LOCKEXIST__LOCK_PRESENT 0x1 +#define DBG_CTINOC_LSR___M 0x00000007 +#define DBG_CTINOC_LSR___S 0 + +#define DBG_CTINOC_AUTHSTATUS (0x00B95FB8) +#define DBG_CTINOC_AUTHSTATUS___RWC QCSR_REG_RO +#define DBG_CTINOC_AUTHSTATUS__SNID___M 0x000000C0 +#define DBG_CTINOC_AUTHSTATUS__SNID___S 6 +#define DBG_CTINOC_AUTHSTATUS__SNID__NOT_IMPLEMENTED 0x0 +#define DBG_CTINOC_AUTHSTATUS__SID___M 0x00000030 +#define DBG_CTINOC_AUTHSTATUS__SID___S 4 +#define DBG_CTINOC_AUTHSTATUS__SID__NOT_IMPLEMENTED 0x0 +#define DBG_CTINOC_AUTHSTATUS__NSNID___M 0x0000000C +#define DBG_CTINOC_AUTHSTATUS__NSNID___S 2 +#define DBG_CTINOC_AUTHSTATUS__NSNID__DISABLED 0x2 +#define DBG_CTINOC_AUTHSTATUS__NSNID__ENABLED 0x3 +#define DBG_CTINOC_AUTHSTATUS__NSID___M 0x00000003 +#define DBG_CTINOC_AUTHSTATUS__NSID___S 0 +#define DBG_CTINOC_AUTHSTATUS__NSID__DISABLED 0x2 +#define DBG_CTINOC_AUTHSTATUS__NSID__ENABLED 0x3 +#define DBG_CTINOC_AUTHSTATUS___M 0x000000FF +#define DBG_CTINOC_AUTHSTATUS___S 0 + +#define DBG_CTINOC_DEVARCH (0x00B95FBC) +#define DBG_CTINOC_DEVARCH___RWC QCSR_REG_RO +#define DBG_CTINOC_DEVARCH___POR 0x8EF00A14 +#define DBG_CTINOC_DEVARCH__ARCHITECT___POR 0x477 +#define DBG_CTINOC_DEVARCH__PRESENT___POR 0x1 +#define DBG_CTINOC_DEVARCH__REVISION___POR 0x0 +#define DBG_CTINOC_DEVARCH__ARCHID___POR 0x0A14 +#define DBG_CTINOC_DEVARCH__ARCHITECT___M 0xFFE00000 +#define DBG_CTINOC_DEVARCH__ARCHITECT___S 21 +#define DBG_CTINOC_DEVARCH__PRESENT___M 0x00100000 +#define DBG_CTINOC_DEVARCH__PRESENT___S 20 +#define DBG_CTINOC_DEVARCH__REVISION___M 0x000F0000 +#define DBG_CTINOC_DEVARCH__REVISION___S 16 +#define DBG_CTINOC_DEVARCH__ARCHID___M 0x0000FFFF +#define DBG_CTINOC_DEVARCH__ARCHID___S 0 +#define DBG_CTINOC_DEVARCH___M 0xFFFFFFFF +#define DBG_CTINOC_DEVARCH___S 0 + +#define DBG_CTINOC_DEVID2 (0x00B95FC0) +#define DBG_CTINOC_DEVID2___RWC QCSR_REG_RO +#define DBG_CTINOC_DEVID2___POR 0x00000000 +#define DBG_CTINOC_DEVID2__IMPLDEF___POR 0x0 +#define DBG_CTINOC_DEVID2__IMPLDEF___M 0x00000001 +#define DBG_CTINOC_DEVID2__IMPLDEF___S 0 +#define DBG_CTINOC_DEVID2___M 0x00000001 +#define DBG_CTINOC_DEVID2___S 0 + +#define DBG_CTINOC_DEVID1 (0x00B95FC4) +#define DBG_CTINOC_DEVID1___RWC QCSR_REG_RO +#define DBG_CTINOC_DEVID1___POR 0x00000000 +#define DBG_CTINOC_DEVID1__IMPLDEF___POR 0x0 +#define DBG_CTINOC_DEVID1__IMPLDEF___M 0x00000001 +#define DBG_CTINOC_DEVID1__IMPLDEF___S 0 +#define DBG_CTINOC_DEVID1___M 0x00000001 +#define DBG_CTINOC_DEVID1___S 0 + +#define DBG_CTINOC_DEVID (0x00B95FC8) +#define DBG_CTINOC_DEVID___RWC QCSR_REG_RO +#define DBG_CTINOC_DEVID___POR 0x00080800 +#define DBG_CTINOC_DEVID__NUMCH___POR 0x8 +#define DBG_CTINOC_DEVID__NUMTRIG___POR 0x8 +#define DBG_CTINOC_DEVID__EXTMUXNUM___POR 0x00 +#define DBG_CTINOC_DEVID__NUMCH___M 0x003F0000 +#define DBG_CTINOC_DEVID__NUMCH___S 16 +#define DBG_CTINOC_DEVID__NUMTRIG___M 0x0000FF00 +#define DBG_CTINOC_DEVID__NUMTRIG___S 8 +#define DBG_CTINOC_DEVID__EXTMUXNUM___M 0x0000001F +#define DBG_CTINOC_DEVID__EXTMUXNUM___S 0 +#define DBG_CTINOC_DEVID___M 0x003FFF1F +#define DBG_CTINOC_DEVID___S 0 + +#define DBG_CTINOC_DEVTYPE (0x00B95FCC) +#define DBG_CTINOC_DEVTYPE___RWC QCSR_REG_RO +#define DBG_CTINOC_DEVTYPE___POR 0x00000014 +#define DBG_CTINOC_DEVTYPE__SUB_TYPE___POR 0x1 +#define DBG_CTINOC_DEVTYPE__MAJOR_TYPE___POR 0x4 +#define DBG_CTINOC_DEVTYPE__SUB_TYPE___M 0x000000F0 +#define DBG_CTINOC_DEVTYPE__SUB_TYPE___S 4 +#define DBG_CTINOC_DEVTYPE__SUB_TYPE__TRIGGER_MATRIX 0x1 +#define DBG_CTINOC_DEVTYPE__MAJOR_TYPE___M 0x0000000F +#define DBG_CTINOC_DEVTYPE__MAJOR_TYPE___S 0 +#define DBG_CTINOC_DEVTYPE__MAJOR_TYPE__DEBUG_CONTROL 0x4 +#define DBG_CTINOC_DEVTYPE___M 0x000000FF +#define DBG_CTINOC_DEVTYPE___S 0 + +#define DBG_CTINOC_PIDR0 (0x00B95FE0) +#define DBG_CTINOC_PIDR0___RWC QCSR_REG_RO +#define DBG_CTINOC_PIDR0___POR 0x00000006 +#define DBG_CTINOC_PIDR0__PART_0___POR 0x06 +#define DBG_CTINOC_PIDR0__PART_0___M 0x000000FF +#define DBG_CTINOC_PIDR0__PART_0___S 0 +#define DBG_CTINOC_PIDR0__PART_0__CTI_PART_NUMBER_7_0 0x06 +#define DBG_CTINOC_PIDR0___M 0x000000FF +#define DBG_CTINOC_PIDR0___S 0 + +#define DBG_CTINOC_PIDR1 (0x00B95FE4) +#define DBG_CTINOC_PIDR1___RWC QCSR_REG_RO +#define DBG_CTINOC_PIDR1___POR 0x000000B9 +#define DBG_CTINOC_PIDR1__DES_0___POR 0xB +#define DBG_CTINOC_PIDR1__PART_1___POR 0x9 +#define DBG_CTINOC_PIDR1__DES_0___M 0x000000F0 +#define DBG_CTINOC_PIDR1__DES_0___S 4 +#define DBG_CTINOC_PIDR1__DES_0__ARM_JEP106_IDENTITY_CODE_3_0 0xB +#define DBG_CTINOC_PIDR1__PART_1___M 0x0000000F +#define DBG_CTINOC_PIDR1__PART_1___S 0 +#define DBG_CTINOC_PIDR1__PART_1__CTI_PART_NUMBER_11_8 0x9 +#define DBG_CTINOC_PIDR1___M 0x000000FF +#define DBG_CTINOC_PIDR1___S 0 + +#define DBG_CTINOC_PIDR2 (0x00B95FE8) +#define DBG_CTINOC_PIDR2___RWC QCSR_REG_RO +#define DBG_CTINOC_PIDR2___POR 0x0000004B +#define DBG_CTINOC_PIDR2__REVISION___POR 0x4 +#define DBG_CTINOC_PIDR2__JEDEC___POR 0x1 +#define DBG_CTINOC_PIDR2__DES_1___POR 0x3 +#define DBG_CTINOC_PIDR2__REVISION___M 0x000000F0 +#define DBG_CTINOC_PIDR2__REVISION___S 4 +#define DBG_CTINOC_PIDR2__REVISION__R0P4 0x4 +#define DBG_CTINOC_PIDR2__REVISION__R0P5 0x5 +#define DBG_CTINOC_PIDR2__JEDEC___M 0x00000008 +#define DBG_CTINOC_PIDR2__JEDEC___S 3 +#define DBG_CTINOC_PIDR2__JEDEC__JEDEC_IDENTITY 0x1 +#define DBG_CTINOC_PIDR2__DES_1___M 0x00000007 +#define DBG_CTINOC_PIDR2__DES_1___S 0 +#define DBG_CTINOC_PIDR2__DES_1__ARM_JEP106_IDENTITY_CODE_6_4 0x3 +#define DBG_CTINOC_PIDR2___M 0x000000FF +#define DBG_CTINOC_PIDR2___S 0 + +#define DBG_CTINOC_PIDR3 (0x00B95FEC) +#define DBG_CTINOC_PIDR3___RWC QCSR_REG_RO +#define DBG_CTINOC_PIDR3___POR 0x00000000 +#define DBG_CTINOC_PIDR3__REVAND___POR 0x0 +#define DBG_CTINOC_PIDR3__CMOD___POR 0x0 +#define DBG_CTINOC_PIDR3__REVAND___M 0x000000F0 +#define DBG_CTINOC_PIDR3__REVAND___S 4 +#define DBG_CTINOC_PIDR3__REVAND__NO_MODIFICATION 0x0 +#define DBG_CTINOC_PIDR3__CMOD___M 0x0000000F +#define DBG_CTINOC_PIDR3__CMOD___S 0 +#define DBG_CTINOC_PIDR3__CMOD__NO_MODIFICATION 0x0 +#define DBG_CTINOC_PIDR3___M 0x000000FF +#define DBG_CTINOC_PIDR3___S 0 + +#define DBG_CTINOC_PIDR4 (0x00B95FD0) +#define DBG_CTINOC_PIDR4___RWC QCSR_REG_RO +#define DBG_CTINOC_PIDR4___POR 0x00000004 +#define DBG_CTINOC_PIDR4__SIZE___POR 0x0 +#define DBG_CTINOC_PIDR4__DES_2___POR 0x4 +#define DBG_CTINOC_PIDR4__SIZE___M 0x000000F0 +#define DBG_CTINOC_PIDR4__SIZE___S 4 +#define DBG_CTINOC_PIDR4__SIZE__SIZE_4KB 0x0 +#define DBG_CTINOC_PIDR4__DES_2___M 0x0000000F +#define DBG_CTINOC_PIDR4__DES_2___S 0 +#define DBG_CTINOC_PIDR4__DES_2__ARM_JEP106_CONTINUATION_CODE 0x4 +#define DBG_CTINOC_PIDR4___M 0x000000FF +#define DBG_CTINOC_PIDR4___S 0 + +#define DBG_CTINOC_PIDR5 (0x00B95FD4) +#define DBG_CTINOC_PIDR5___RWC QCSR_REG_RW +#define DBG_CTINOC_PIDR5__PERIPHID5___M 0xFFFFFFFF +#define DBG_CTINOC_PIDR5__PERIPHID5___S 0 +#define DBG_CTINOC_PIDR5___M 0xFFFFFFFF +#define DBG_CTINOC_PIDR5___S 0 + +#define DBG_CTINOC_PIDR6 (0x00B95FD8) +#define DBG_CTINOC_PIDR6___RWC QCSR_REG_RW +#define DBG_CTINOC_PIDR6__PERIPHID6___M 0xFFFFFFFF +#define DBG_CTINOC_PIDR6__PERIPHID6___S 0 +#define DBG_CTINOC_PIDR6___M 0xFFFFFFFF +#define DBG_CTINOC_PIDR6___S 0 + +#define DBG_CTINOC_PIDR7 (0x00B95FDC) +#define DBG_CTINOC_PIDR7___RWC QCSR_REG_RW +#define DBG_CTINOC_PIDR7__PERIPHID7___M 0xFFFFFFFF +#define DBG_CTINOC_PIDR7__PERIPHID7___S 0 +#define DBG_CTINOC_PIDR7___M 0xFFFFFFFF +#define DBG_CTINOC_PIDR7___S 0 + +#define DBG_CTINOC_CIDR0 (0x00B95FF0) +#define DBG_CTINOC_CIDR0___RWC QCSR_REG_RO +#define DBG_CTINOC_CIDR0___POR 0x0000000D +#define DBG_CTINOC_CIDR0__PRMBL_0___POR 0x0D +#define DBG_CTINOC_CIDR0__PRMBL_0___M 0x000000FF +#define DBG_CTINOC_CIDR0__PRMBL_0___S 0 +#define DBG_CTINOC_CIDR0__PRMBL_0__ID_VALUE_0D 0x0D +#define DBG_CTINOC_CIDR0___M 0x000000FF +#define DBG_CTINOC_CIDR0___S 0 + +#define DBG_CTINOC_CIDR1 (0x00B95FF4) +#define DBG_CTINOC_CIDR1___RWC QCSR_REG_RO +#define DBG_CTINOC_CIDR1___POR 0x00000090 +#define DBG_CTINOC_CIDR1__CLASS___POR 0x9 +#define DBG_CTINOC_CIDR1__PRMBL_1___POR 0x0 +#define DBG_CTINOC_CIDR1__CLASS___M 0x000000F0 +#define DBG_CTINOC_CIDR1__CLASS___S 4 +#define DBG_CTINOC_CIDR1__CLASS__CORESIGHT_COMPONENT 0x9 +#define DBG_CTINOC_CIDR1__PRMBL_1___M 0x0000000F +#define DBG_CTINOC_CIDR1__PRMBL_1___S 0 +#define DBG_CTINOC_CIDR1__PRMBL_1__ID_VALUE_0 0x0 +#define DBG_CTINOC_CIDR1___M 0x000000FF +#define DBG_CTINOC_CIDR1___S 0 + +#define DBG_CTINOC_CIDR2 (0x00B95FF8) +#define DBG_CTINOC_CIDR2___RWC QCSR_REG_RO +#define DBG_CTINOC_CIDR2___POR 0x00000005 +#define DBG_CTINOC_CIDR2__PRMBL_2___POR 0x05 +#define DBG_CTINOC_CIDR2__PRMBL_2___M 0x000000FF +#define DBG_CTINOC_CIDR2__PRMBL_2___S 0 +#define DBG_CTINOC_CIDR2__PRMBL_2__ID_VALUE_05 0x05 +#define DBG_CTINOC_CIDR2___M 0x000000FF +#define DBG_CTINOC_CIDR2___S 0 + +#define DBG_CTINOC_CIDR3 (0x00B95FFC) +#define DBG_CTINOC_CIDR3___RWC QCSR_REG_RO +#define DBG_CTINOC_CIDR3___POR 0x000000B1 +#define DBG_CTINOC_CIDR3__PRMBL_3___POR 0xB1 +#define DBG_CTINOC_CIDR3__PRMBL_3___M 0x000000FF +#define DBG_CTINOC_CIDR3__PRMBL_3___S 0 +#define DBG_CTINOC_CIDR3__PRMBL_3__ID_VALUE_B1 0xB1 +#define DBG_CTINOC_CIDR3___M 0x000000FF +#define DBG_CTINOC_CIDR3___S 0 + +#define DBG_CTIIRQ_CTICONTROL (0x00B96000) +#define DBG_CTIIRQ_CTICONTROL___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTICONTROL___POR 0x00000000 +#define DBG_CTIIRQ_CTICONTROL__GLBEN___POR 0x0 +#define DBG_CTIIRQ_CTICONTROL__GLBEN___M 0x00000001 +#define DBG_CTIIRQ_CTICONTROL__GLBEN___S 0 +#define DBG_CTIIRQ_CTICONTROL__GLBEN__DISABLED 0x0 +#define DBG_CTIIRQ_CTICONTROL__GLBEN__ENABLED 0x1 +#define DBG_CTIIRQ_CTICONTROL___M 0x00000001 +#define DBG_CTIIRQ_CTICONTROL___S 0 + +#define DBG_CTIIRQ_CTIINTACK (0x00B96010) +#define DBG_CTIIRQ_CTIINTACK___RWC QCSR_REG_WO +#define DBG_CTIIRQ_CTIINTACK___POR 0x00000000 +#define DBG_CTIIRQ_CTIINTACK__INTACK___POR 0x00000000 +#define DBG_CTIIRQ_CTIINTACK__INTACK___M 0xFFFFFFFF +#define DBG_CTIIRQ_CTIINTACK__INTACK___S 0 +#define DBG_CTIIRQ_CTIINTACK___M 0xFFFFFFFF +#define DBG_CTIIRQ_CTIINTACK___S 0 + +#define DBG_CTIIRQ_CTIAPPSET (0x00B96014) +#define DBG_CTIIRQ_CTIAPPSET___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIAPPSET___POR 0x00000000 +#define DBG_CTIIRQ_CTIAPPSET__APPSET___POR 0x00 +#define DBG_CTIIRQ_CTIAPPSET__APPSET___M 0x000000FF +#define DBG_CTIIRQ_CTIAPPSET__APPSET___S 0 +#define DBG_CTIIRQ_CTIAPPSET___M 0x000000FF +#define DBG_CTIIRQ_CTIAPPSET___S 0 + +#define DBG_CTIIRQ_CTIAPPCLEAR (0x00B96018) +#define DBG_CTIIRQ_CTIAPPCLEAR___RWC QCSR_REG_WO +#define DBG_CTIIRQ_CTIAPPCLEAR___POR 0x00000000 +#define DBG_CTIIRQ_CTIAPPCLEAR__APPCLEAR___POR 0x00 +#define DBG_CTIIRQ_CTIAPPCLEAR__APPCLEAR___M 0x000000FF +#define DBG_CTIIRQ_CTIAPPCLEAR__APPCLEAR___S 0 +#define DBG_CTIIRQ_CTIAPPCLEAR___M 0x000000FF +#define DBG_CTIIRQ_CTIAPPCLEAR___S 0 + +#define DBG_CTIIRQ_CTIAPPPULSE (0x00B9601C) +#define DBG_CTIIRQ_CTIAPPPULSE___RWC QCSR_REG_WO +#define DBG_CTIIRQ_CTIAPPPULSE___POR 0x00000000 +#define DBG_CTIIRQ_CTIAPPPULSE__APPULSE___POR 0x00 +#define DBG_CTIIRQ_CTIAPPPULSE__APPULSE___M 0x000000FF +#define DBG_CTIIRQ_CTIAPPPULSE__APPULSE___S 0 +#define DBG_CTIIRQ_CTIAPPPULSE___M 0x000000FF +#define DBG_CTIIRQ_CTIAPPPULSE___S 0 + +#define DBG_CTIIRQ_CTIINEN0 (0x00B96020) +#define DBG_CTIIRQ_CTIINEN0___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIINEN0___POR 0x00000000 +#define DBG_CTIIRQ_CTIINEN0__TRIGINEN___POR 0x00 +#define DBG_CTIIRQ_CTIINEN0__TRIGINEN___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN0__TRIGINEN___S 0 +#define DBG_CTIIRQ_CTIINEN0___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN0___S 0 + +#define DBG_CTIIRQ_CTIINEN1 (0x00B96024) +#define DBG_CTIIRQ_CTIINEN1___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIINEN1___POR 0x00000000 +#define DBG_CTIIRQ_CTIINEN1__TRIGINEN___POR 0x00 +#define DBG_CTIIRQ_CTIINEN1__TRIGINEN___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN1__TRIGINEN___S 0 +#define DBG_CTIIRQ_CTIINEN1___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN1___S 0 + +#define DBG_CTIIRQ_CTIINEN2 (0x00B96028) +#define DBG_CTIIRQ_CTIINEN2___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIINEN2___POR 0x00000000 +#define DBG_CTIIRQ_CTIINEN2__TRIGINEN___POR 0x00 +#define DBG_CTIIRQ_CTIINEN2__TRIGINEN___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN2__TRIGINEN___S 0 +#define DBG_CTIIRQ_CTIINEN2___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN2___S 0 + +#define DBG_CTIIRQ_CTIINEN3 (0x00B9602C) +#define DBG_CTIIRQ_CTIINEN3___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIINEN3___POR 0x00000000 +#define DBG_CTIIRQ_CTIINEN3__TRIGINEN___POR 0x00 +#define DBG_CTIIRQ_CTIINEN3__TRIGINEN___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN3__TRIGINEN___S 0 +#define DBG_CTIIRQ_CTIINEN3___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN3___S 0 + +#define DBG_CTIIRQ_CTIINEN4 (0x00B96030) +#define DBG_CTIIRQ_CTIINEN4___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIINEN4___POR 0x00000000 +#define DBG_CTIIRQ_CTIINEN4__TRIGINEN___POR 0x00 +#define DBG_CTIIRQ_CTIINEN4__TRIGINEN___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN4__TRIGINEN___S 0 +#define DBG_CTIIRQ_CTIINEN4___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN4___S 0 + +#define DBG_CTIIRQ_CTIINEN5 (0x00B96034) +#define DBG_CTIIRQ_CTIINEN5___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIINEN5___POR 0x00000000 +#define DBG_CTIIRQ_CTIINEN5__TRIGINEN___POR 0x00 +#define DBG_CTIIRQ_CTIINEN5__TRIGINEN___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN5__TRIGINEN___S 0 +#define DBG_CTIIRQ_CTIINEN5___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN5___S 0 + +#define DBG_CTIIRQ_CTIINEN6 (0x00B96038) +#define DBG_CTIIRQ_CTIINEN6___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIINEN6___POR 0x00000000 +#define DBG_CTIIRQ_CTIINEN6__TRIGINEN___POR 0x00 +#define DBG_CTIIRQ_CTIINEN6__TRIGINEN___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN6__TRIGINEN___S 0 +#define DBG_CTIIRQ_CTIINEN6___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN6___S 0 + +#define DBG_CTIIRQ_CTIINEN7 (0x00B9603C) +#define DBG_CTIIRQ_CTIINEN7___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIINEN7___POR 0x00000000 +#define DBG_CTIIRQ_CTIINEN7__TRIGINEN___POR 0x00 +#define DBG_CTIIRQ_CTIINEN7__TRIGINEN___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN7__TRIGINEN___S 0 +#define DBG_CTIIRQ_CTIINEN7___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN7___S 0 + +#define DBG_CTIIRQ_CTIINEN8 (0x00B96040) +#define DBG_CTIIRQ_CTIINEN8___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIINEN8___POR 0x00000000 +#define DBG_CTIIRQ_CTIINEN8__TRIGINEN___POR 0x00 +#define DBG_CTIIRQ_CTIINEN8__TRIGINEN___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN8__TRIGINEN___S 0 +#define DBG_CTIIRQ_CTIINEN8___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN8___S 0 + +#define DBG_CTIIRQ_CTIINEN9 (0x00B96044) +#define DBG_CTIIRQ_CTIINEN9___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIINEN9___POR 0x00000000 +#define DBG_CTIIRQ_CTIINEN9__TRIGINEN___POR 0x00 +#define DBG_CTIIRQ_CTIINEN9__TRIGINEN___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN9__TRIGINEN___S 0 +#define DBG_CTIIRQ_CTIINEN9___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN9___S 0 + +#define DBG_CTIIRQ_CTIINEN10 (0x00B96048) +#define DBG_CTIIRQ_CTIINEN10___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIINEN10___POR 0x00000000 +#define DBG_CTIIRQ_CTIINEN10__TRIGINEN___POR 0x00 +#define DBG_CTIIRQ_CTIINEN10__TRIGINEN___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN10__TRIGINEN___S 0 +#define DBG_CTIIRQ_CTIINEN10___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN10___S 0 + +#define DBG_CTIIRQ_CTIINEN11 (0x00B9604C) +#define DBG_CTIIRQ_CTIINEN11___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIINEN11___POR 0x00000000 +#define DBG_CTIIRQ_CTIINEN11__TRIGINEN___POR 0x00 +#define DBG_CTIIRQ_CTIINEN11__TRIGINEN___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN11__TRIGINEN___S 0 +#define DBG_CTIIRQ_CTIINEN11___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN11___S 0 + +#define DBG_CTIIRQ_CTIINEN12 (0x00B96050) +#define DBG_CTIIRQ_CTIINEN12___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIINEN12___POR 0x00000000 +#define DBG_CTIIRQ_CTIINEN12__TRIGINEN___POR 0x00 +#define DBG_CTIIRQ_CTIINEN12__TRIGINEN___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN12__TRIGINEN___S 0 +#define DBG_CTIIRQ_CTIINEN12___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN12___S 0 + +#define DBG_CTIIRQ_CTIINEN13 (0x00B96054) +#define DBG_CTIIRQ_CTIINEN13___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIINEN13___POR 0x00000000 +#define DBG_CTIIRQ_CTIINEN13__TRIGINEN___POR 0x00 +#define DBG_CTIIRQ_CTIINEN13__TRIGINEN___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN13__TRIGINEN___S 0 +#define DBG_CTIIRQ_CTIINEN13___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN13___S 0 + +#define DBG_CTIIRQ_CTIINEN14 (0x00B96058) +#define DBG_CTIIRQ_CTIINEN14___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIINEN14___POR 0x00000000 +#define DBG_CTIIRQ_CTIINEN14__TRIGINEN___POR 0x00 +#define DBG_CTIIRQ_CTIINEN14__TRIGINEN___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN14__TRIGINEN___S 0 +#define DBG_CTIIRQ_CTIINEN14___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN14___S 0 + +#define DBG_CTIIRQ_CTIINEN15 (0x00B9605C) +#define DBG_CTIIRQ_CTIINEN15___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIINEN15___POR 0x00000000 +#define DBG_CTIIRQ_CTIINEN15__TRIGINEN___POR 0x00 +#define DBG_CTIIRQ_CTIINEN15__TRIGINEN___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN15__TRIGINEN___S 0 +#define DBG_CTIIRQ_CTIINEN15___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN15___S 0 + +#define DBG_CTIIRQ_CTIINEN16 (0x00B96060) +#define DBG_CTIIRQ_CTIINEN16___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIINEN16___POR 0x00000000 +#define DBG_CTIIRQ_CTIINEN16__TRIGINEN___POR 0x00 +#define DBG_CTIIRQ_CTIINEN16__TRIGINEN___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN16__TRIGINEN___S 0 +#define DBG_CTIIRQ_CTIINEN16___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN16___S 0 + +#define DBG_CTIIRQ_CTIINEN17 (0x00B96064) +#define DBG_CTIIRQ_CTIINEN17___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIINEN17___POR 0x00000000 +#define DBG_CTIIRQ_CTIINEN17__TRIGINEN___POR 0x00 +#define DBG_CTIIRQ_CTIINEN17__TRIGINEN___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN17__TRIGINEN___S 0 +#define DBG_CTIIRQ_CTIINEN17___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN17___S 0 + +#define DBG_CTIIRQ_CTIINEN18 (0x00B96068) +#define DBG_CTIIRQ_CTIINEN18___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIINEN18___POR 0x00000000 +#define DBG_CTIIRQ_CTIINEN18__TRIGINEN___POR 0x00 +#define DBG_CTIIRQ_CTIINEN18__TRIGINEN___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN18__TRIGINEN___S 0 +#define DBG_CTIIRQ_CTIINEN18___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN18___S 0 + +#define DBG_CTIIRQ_CTIINEN19 (0x00B9606C) +#define DBG_CTIIRQ_CTIINEN19___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIINEN19___POR 0x00000000 +#define DBG_CTIIRQ_CTIINEN19__TRIGINEN___POR 0x00 +#define DBG_CTIIRQ_CTIINEN19__TRIGINEN___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN19__TRIGINEN___S 0 +#define DBG_CTIIRQ_CTIINEN19___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN19___S 0 + +#define DBG_CTIIRQ_CTIINEN20 (0x00B96070) +#define DBG_CTIIRQ_CTIINEN20___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIINEN20___POR 0x00000000 +#define DBG_CTIIRQ_CTIINEN20__TRIGINEN___POR 0x00 +#define DBG_CTIIRQ_CTIINEN20__TRIGINEN___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN20__TRIGINEN___S 0 +#define DBG_CTIIRQ_CTIINEN20___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN20___S 0 + +#define DBG_CTIIRQ_CTIINEN21 (0x00B96074) +#define DBG_CTIIRQ_CTIINEN21___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIINEN21___POR 0x00000000 +#define DBG_CTIIRQ_CTIINEN21__TRIGINEN___POR 0x00 +#define DBG_CTIIRQ_CTIINEN21__TRIGINEN___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN21__TRIGINEN___S 0 +#define DBG_CTIIRQ_CTIINEN21___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN21___S 0 + +#define DBG_CTIIRQ_CTIINEN22 (0x00B96078) +#define DBG_CTIIRQ_CTIINEN22___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIINEN22___POR 0x00000000 +#define DBG_CTIIRQ_CTIINEN22__TRIGINEN___POR 0x00 +#define DBG_CTIIRQ_CTIINEN22__TRIGINEN___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN22__TRIGINEN___S 0 +#define DBG_CTIIRQ_CTIINEN22___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN22___S 0 + +#define DBG_CTIIRQ_CTIINEN23 (0x00B9607C) +#define DBG_CTIIRQ_CTIINEN23___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIINEN23___POR 0x00000000 +#define DBG_CTIIRQ_CTIINEN23__TRIGINEN___POR 0x00 +#define DBG_CTIIRQ_CTIINEN23__TRIGINEN___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN23__TRIGINEN___S 0 +#define DBG_CTIIRQ_CTIINEN23___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN23___S 0 + +#define DBG_CTIIRQ_CTIINEN24 (0x00B96080) +#define DBG_CTIIRQ_CTIINEN24___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIINEN24___POR 0x00000000 +#define DBG_CTIIRQ_CTIINEN24__TRIGINEN___POR 0x00 +#define DBG_CTIIRQ_CTIINEN24__TRIGINEN___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN24__TRIGINEN___S 0 +#define DBG_CTIIRQ_CTIINEN24___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN24___S 0 + +#define DBG_CTIIRQ_CTIINEN25 (0x00B96084) +#define DBG_CTIIRQ_CTIINEN25___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIINEN25___POR 0x00000000 +#define DBG_CTIIRQ_CTIINEN25__TRIGINEN___POR 0x00 +#define DBG_CTIIRQ_CTIINEN25__TRIGINEN___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN25__TRIGINEN___S 0 +#define DBG_CTIIRQ_CTIINEN25___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN25___S 0 + +#define DBG_CTIIRQ_CTIINEN26 (0x00B96088) +#define DBG_CTIIRQ_CTIINEN26___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIINEN26___POR 0x00000000 +#define DBG_CTIIRQ_CTIINEN26__TRIGINEN___POR 0x00 +#define DBG_CTIIRQ_CTIINEN26__TRIGINEN___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN26__TRIGINEN___S 0 +#define DBG_CTIIRQ_CTIINEN26___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN26___S 0 + +#define DBG_CTIIRQ_CTIINEN27 (0x00B9608C) +#define DBG_CTIIRQ_CTIINEN27___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIINEN27___POR 0x00000000 +#define DBG_CTIIRQ_CTIINEN27__TRIGINEN___POR 0x00 +#define DBG_CTIIRQ_CTIINEN27__TRIGINEN___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN27__TRIGINEN___S 0 +#define DBG_CTIIRQ_CTIINEN27___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN27___S 0 + +#define DBG_CTIIRQ_CTIINEN28 (0x00B96090) +#define DBG_CTIIRQ_CTIINEN28___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIINEN28___POR 0x00000000 +#define DBG_CTIIRQ_CTIINEN28__TRIGINEN___POR 0x00 +#define DBG_CTIIRQ_CTIINEN28__TRIGINEN___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN28__TRIGINEN___S 0 +#define DBG_CTIIRQ_CTIINEN28___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN28___S 0 + +#define DBG_CTIIRQ_CTIINEN29 (0x00B96094) +#define DBG_CTIIRQ_CTIINEN29___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIINEN29___POR 0x00000000 +#define DBG_CTIIRQ_CTIINEN29__TRIGINEN___POR 0x00 +#define DBG_CTIIRQ_CTIINEN29__TRIGINEN___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN29__TRIGINEN___S 0 +#define DBG_CTIIRQ_CTIINEN29___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN29___S 0 + +#define DBG_CTIIRQ_CTIINEN30 (0x00B96098) +#define DBG_CTIIRQ_CTIINEN30___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIINEN30___POR 0x00000000 +#define DBG_CTIIRQ_CTIINEN30__TRIGINEN___POR 0x00 +#define DBG_CTIIRQ_CTIINEN30__TRIGINEN___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN30__TRIGINEN___S 0 +#define DBG_CTIIRQ_CTIINEN30___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN30___S 0 + +#define DBG_CTIIRQ_CTIINEN31 (0x00B9609C) +#define DBG_CTIIRQ_CTIINEN31___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIINEN31___POR 0x00000000 +#define DBG_CTIIRQ_CTIINEN31__TRIGINEN___POR 0x00 +#define DBG_CTIIRQ_CTIINEN31__TRIGINEN___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN31__TRIGINEN___S 0 +#define DBG_CTIIRQ_CTIINEN31___M 0x000000FF +#define DBG_CTIIRQ_CTIINEN31___S 0 + +#define DBG_CTIIRQ_CTIOUTEN0 (0x00B960A0) +#define DBG_CTIIRQ_CTIOUTEN0___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIOUTEN0___POR 0x00000000 +#define DBG_CTIIRQ_CTIOUTEN0__TRIGOUTEN___POR 0x00 +#define DBG_CTIIRQ_CTIOUTEN0__TRIGOUTEN___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN0__TRIGOUTEN___S 0 +#define DBG_CTIIRQ_CTIOUTEN0___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN0___S 0 + +#define DBG_CTIIRQ_CTIOUTEN1 (0x00B960A4) +#define DBG_CTIIRQ_CTIOUTEN1___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIOUTEN1___POR 0x00000000 +#define DBG_CTIIRQ_CTIOUTEN1__TRIGOUTEN___POR 0x00 +#define DBG_CTIIRQ_CTIOUTEN1__TRIGOUTEN___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN1__TRIGOUTEN___S 0 +#define DBG_CTIIRQ_CTIOUTEN1___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN1___S 0 + +#define DBG_CTIIRQ_CTIOUTEN2 (0x00B960A8) +#define DBG_CTIIRQ_CTIOUTEN2___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIOUTEN2___POR 0x00000000 +#define DBG_CTIIRQ_CTIOUTEN2__TRIGOUTEN___POR 0x00 +#define DBG_CTIIRQ_CTIOUTEN2__TRIGOUTEN___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN2__TRIGOUTEN___S 0 +#define DBG_CTIIRQ_CTIOUTEN2___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN2___S 0 + +#define DBG_CTIIRQ_CTIOUTEN3 (0x00B960AC) +#define DBG_CTIIRQ_CTIOUTEN3___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIOUTEN3___POR 0x00000000 +#define DBG_CTIIRQ_CTIOUTEN3__TRIGOUTEN___POR 0x00 +#define DBG_CTIIRQ_CTIOUTEN3__TRIGOUTEN___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN3__TRIGOUTEN___S 0 +#define DBG_CTIIRQ_CTIOUTEN3___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN3___S 0 + +#define DBG_CTIIRQ_CTIOUTEN4 (0x00B960B0) +#define DBG_CTIIRQ_CTIOUTEN4___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIOUTEN4___POR 0x00000000 +#define DBG_CTIIRQ_CTIOUTEN4__TRIGOUTEN___POR 0x00 +#define DBG_CTIIRQ_CTIOUTEN4__TRIGOUTEN___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN4__TRIGOUTEN___S 0 +#define DBG_CTIIRQ_CTIOUTEN4___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN4___S 0 + +#define DBG_CTIIRQ_CTIOUTEN5 (0x00B960B4) +#define DBG_CTIIRQ_CTIOUTEN5___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIOUTEN5___POR 0x00000000 +#define DBG_CTIIRQ_CTIOUTEN5__TRIGOUTEN___POR 0x00 +#define DBG_CTIIRQ_CTIOUTEN5__TRIGOUTEN___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN5__TRIGOUTEN___S 0 +#define DBG_CTIIRQ_CTIOUTEN5___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN5___S 0 + +#define DBG_CTIIRQ_CTIOUTEN6 (0x00B960B8) +#define DBG_CTIIRQ_CTIOUTEN6___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIOUTEN6___POR 0x00000000 +#define DBG_CTIIRQ_CTIOUTEN6__TRIGOUTEN___POR 0x00 +#define DBG_CTIIRQ_CTIOUTEN6__TRIGOUTEN___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN6__TRIGOUTEN___S 0 +#define DBG_CTIIRQ_CTIOUTEN6___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN6___S 0 + +#define DBG_CTIIRQ_CTIOUTEN7 (0x00B960BC) +#define DBG_CTIIRQ_CTIOUTEN7___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIOUTEN7___POR 0x00000000 +#define DBG_CTIIRQ_CTIOUTEN7__TRIGOUTEN___POR 0x00 +#define DBG_CTIIRQ_CTIOUTEN7__TRIGOUTEN___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN7__TRIGOUTEN___S 0 +#define DBG_CTIIRQ_CTIOUTEN7___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN7___S 0 + +#define DBG_CTIIRQ_CTIOUTEN8 (0x00B960C0) +#define DBG_CTIIRQ_CTIOUTEN8___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIOUTEN8___POR 0x00000000 +#define DBG_CTIIRQ_CTIOUTEN8__TRIGOUTEN___POR 0x00 +#define DBG_CTIIRQ_CTIOUTEN8__TRIGOUTEN___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN8__TRIGOUTEN___S 0 +#define DBG_CTIIRQ_CTIOUTEN8___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN8___S 0 + +#define DBG_CTIIRQ_CTIOUTEN9 (0x00B960C4) +#define DBG_CTIIRQ_CTIOUTEN9___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIOUTEN9___POR 0x00000000 +#define DBG_CTIIRQ_CTIOUTEN9__TRIGOUTEN___POR 0x00 +#define DBG_CTIIRQ_CTIOUTEN9__TRIGOUTEN___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN9__TRIGOUTEN___S 0 +#define DBG_CTIIRQ_CTIOUTEN9___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN9___S 0 + +#define DBG_CTIIRQ_CTIOUTEN10 (0x00B960C8) +#define DBG_CTIIRQ_CTIOUTEN10___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIOUTEN10___POR 0x00000000 +#define DBG_CTIIRQ_CTIOUTEN10__TRIGOUTEN___POR 0x00 +#define DBG_CTIIRQ_CTIOUTEN10__TRIGOUTEN___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN10__TRIGOUTEN___S 0 +#define DBG_CTIIRQ_CTIOUTEN10___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN10___S 0 + +#define DBG_CTIIRQ_CTIOUTEN11 (0x00B960CC) +#define DBG_CTIIRQ_CTIOUTEN11___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIOUTEN11___POR 0x00000000 +#define DBG_CTIIRQ_CTIOUTEN11__TRIGOUTEN___POR 0x00 +#define DBG_CTIIRQ_CTIOUTEN11__TRIGOUTEN___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN11__TRIGOUTEN___S 0 +#define DBG_CTIIRQ_CTIOUTEN11___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN11___S 0 + +#define DBG_CTIIRQ_CTIOUTEN12 (0x00B960D0) +#define DBG_CTIIRQ_CTIOUTEN12___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIOUTEN12___POR 0x00000000 +#define DBG_CTIIRQ_CTIOUTEN12__TRIGOUTEN___POR 0x00 +#define DBG_CTIIRQ_CTIOUTEN12__TRIGOUTEN___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN12__TRIGOUTEN___S 0 +#define DBG_CTIIRQ_CTIOUTEN12___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN12___S 0 + +#define DBG_CTIIRQ_CTIOUTEN13 (0x00B960D4) +#define DBG_CTIIRQ_CTIOUTEN13___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIOUTEN13___POR 0x00000000 +#define DBG_CTIIRQ_CTIOUTEN13__TRIGOUTEN___POR 0x00 +#define DBG_CTIIRQ_CTIOUTEN13__TRIGOUTEN___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN13__TRIGOUTEN___S 0 +#define DBG_CTIIRQ_CTIOUTEN13___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN13___S 0 + +#define DBG_CTIIRQ_CTIOUTEN14 (0x00B960D8) +#define DBG_CTIIRQ_CTIOUTEN14___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIOUTEN14___POR 0x00000000 +#define DBG_CTIIRQ_CTIOUTEN14__TRIGOUTEN___POR 0x00 +#define DBG_CTIIRQ_CTIOUTEN14__TRIGOUTEN___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN14__TRIGOUTEN___S 0 +#define DBG_CTIIRQ_CTIOUTEN14___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN14___S 0 + +#define DBG_CTIIRQ_CTIOUTEN15 (0x00B960DC) +#define DBG_CTIIRQ_CTIOUTEN15___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIOUTEN15___POR 0x00000000 +#define DBG_CTIIRQ_CTIOUTEN15__TRIGOUTEN___POR 0x00 +#define DBG_CTIIRQ_CTIOUTEN15__TRIGOUTEN___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN15__TRIGOUTEN___S 0 +#define DBG_CTIIRQ_CTIOUTEN15___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN15___S 0 + +#define DBG_CTIIRQ_CTIOUTEN16 (0x00B960E0) +#define DBG_CTIIRQ_CTIOUTEN16___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIOUTEN16___POR 0x00000000 +#define DBG_CTIIRQ_CTIOUTEN16__TRIGOUTEN___POR 0x00 +#define DBG_CTIIRQ_CTIOUTEN16__TRIGOUTEN___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN16__TRIGOUTEN___S 0 +#define DBG_CTIIRQ_CTIOUTEN16___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN16___S 0 + +#define DBG_CTIIRQ_CTIOUTEN17 (0x00B960E4) +#define DBG_CTIIRQ_CTIOUTEN17___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIOUTEN17___POR 0x00000000 +#define DBG_CTIIRQ_CTIOUTEN17__TRIGOUTEN___POR 0x00 +#define DBG_CTIIRQ_CTIOUTEN17__TRIGOUTEN___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN17__TRIGOUTEN___S 0 +#define DBG_CTIIRQ_CTIOUTEN17___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN17___S 0 + +#define DBG_CTIIRQ_CTIOUTEN18 (0x00B960E8) +#define DBG_CTIIRQ_CTIOUTEN18___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIOUTEN18___POR 0x00000000 +#define DBG_CTIIRQ_CTIOUTEN18__TRIGOUTEN___POR 0x00 +#define DBG_CTIIRQ_CTIOUTEN18__TRIGOUTEN___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN18__TRIGOUTEN___S 0 +#define DBG_CTIIRQ_CTIOUTEN18___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN18___S 0 + +#define DBG_CTIIRQ_CTIOUTEN19 (0x00B960EC) +#define DBG_CTIIRQ_CTIOUTEN19___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIOUTEN19___POR 0x00000000 +#define DBG_CTIIRQ_CTIOUTEN19__TRIGOUTEN___POR 0x00 +#define DBG_CTIIRQ_CTIOUTEN19__TRIGOUTEN___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN19__TRIGOUTEN___S 0 +#define DBG_CTIIRQ_CTIOUTEN19___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN19___S 0 + +#define DBG_CTIIRQ_CTIOUTEN20 (0x00B960F0) +#define DBG_CTIIRQ_CTIOUTEN20___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIOUTEN20___POR 0x00000000 +#define DBG_CTIIRQ_CTIOUTEN20__TRIGOUTEN___POR 0x00 +#define DBG_CTIIRQ_CTIOUTEN20__TRIGOUTEN___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN20__TRIGOUTEN___S 0 +#define DBG_CTIIRQ_CTIOUTEN20___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN20___S 0 + +#define DBG_CTIIRQ_CTIOUTEN21 (0x00B960F4) +#define DBG_CTIIRQ_CTIOUTEN21___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIOUTEN21___POR 0x00000000 +#define DBG_CTIIRQ_CTIOUTEN21__TRIGOUTEN___POR 0x00 +#define DBG_CTIIRQ_CTIOUTEN21__TRIGOUTEN___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN21__TRIGOUTEN___S 0 +#define DBG_CTIIRQ_CTIOUTEN21___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN21___S 0 + +#define DBG_CTIIRQ_CTIOUTEN22 (0x00B960F8) +#define DBG_CTIIRQ_CTIOUTEN22___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIOUTEN22___POR 0x00000000 +#define DBG_CTIIRQ_CTIOUTEN22__TRIGOUTEN___POR 0x00 +#define DBG_CTIIRQ_CTIOUTEN22__TRIGOUTEN___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN22__TRIGOUTEN___S 0 +#define DBG_CTIIRQ_CTIOUTEN22___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN22___S 0 + +#define DBG_CTIIRQ_CTIOUTEN23 (0x00B960FC) +#define DBG_CTIIRQ_CTIOUTEN23___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIOUTEN23___POR 0x00000000 +#define DBG_CTIIRQ_CTIOUTEN23__TRIGOUTEN___POR 0x00 +#define DBG_CTIIRQ_CTIOUTEN23__TRIGOUTEN___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN23__TRIGOUTEN___S 0 +#define DBG_CTIIRQ_CTIOUTEN23___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN23___S 0 + +#define DBG_CTIIRQ_CTIOUTEN24 (0x00B96100) +#define DBG_CTIIRQ_CTIOUTEN24___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIOUTEN24___POR 0x00000000 +#define DBG_CTIIRQ_CTIOUTEN24__TRIGOUTEN___POR 0x00 +#define DBG_CTIIRQ_CTIOUTEN24__TRIGOUTEN___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN24__TRIGOUTEN___S 0 +#define DBG_CTIIRQ_CTIOUTEN24___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN24___S 0 + +#define DBG_CTIIRQ_CTIOUTEN25 (0x00B96104) +#define DBG_CTIIRQ_CTIOUTEN25___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIOUTEN25___POR 0x00000000 +#define DBG_CTIIRQ_CTIOUTEN25__TRIGOUTEN___POR 0x00 +#define DBG_CTIIRQ_CTIOUTEN25__TRIGOUTEN___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN25__TRIGOUTEN___S 0 +#define DBG_CTIIRQ_CTIOUTEN25___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN25___S 0 + +#define DBG_CTIIRQ_CTIOUTEN26 (0x00B96108) +#define DBG_CTIIRQ_CTIOUTEN26___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIOUTEN26___POR 0x00000000 +#define DBG_CTIIRQ_CTIOUTEN26__TRIGOUTEN___POR 0x00 +#define DBG_CTIIRQ_CTIOUTEN26__TRIGOUTEN___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN26__TRIGOUTEN___S 0 +#define DBG_CTIIRQ_CTIOUTEN26___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN26___S 0 + +#define DBG_CTIIRQ_CTIOUTEN27 (0x00B9610C) +#define DBG_CTIIRQ_CTIOUTEN27___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIOUTEN27___POR 0x00000000 +#define DBG_CTIIRQ_CTIOUTEN27__TRIGOUTEN___POR 0x00 +#define DBG_CTIIRQ_CTIOUTEN27__TRIGOUTEN___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN27__TRIGOUTEN___S 0 +#define DBG_CTIIRQ_CTIOUTEN27___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN27___S 0 + +#define DBG_CTIIRQ_CTIOUTEN28 (0x00B96110) +#define DBG_CTIIRQ_CTIOUTEN28___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIOUTEN28___POR 0x00000000 +#define DBG_CTIIRQ_CTIOUTEN28__TRIGOUTEN___POR 0x00 +#define DBG_CTIIRQ_CTIOUTEN28__TRIGOUTEN___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN28__TRIGOUTEN___S 0 +#define DBG_CTIIRQ_CTIOUTEN28___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN28___S 0 + +#define DBG_CTIIRQ_CTIOUTEN29 (0x00B96114) +#define DBG_CTIIRQ_CTIOUTEN29___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIOUTEN29___POR 0x00000000 +#define DBG_CTIIRQ_CTIOUTEN29__TRIGOUTEN___POR 0x00 +#define DBG_CTIIRQ_CTIOUTEN29__TRIGOUTEN___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN29__TRIGOUTEN___S 0 +#define DBG_CTIIRQ_CTIOUTEN29___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN29___S 0 + +#define DBG_CTIIRQ_CTIOUTEN30 (0x00B96118) +#define DBG_CTIIRQ_CTIOUTEN30___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIOUTEN30___POR 0x00000000 +#define DBG_CTIIRQ_CTIOUTEN30__TRIGOUTEN___POR 0x00 +#define DBG_CTIIRQ_CTIOUTEN30__TRIGOUTEN___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN30__TRIGOUTEN___S 0 +#define DBG_CTIIRQ_CTIOUTEN30___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN30___S 0 + +#define DBG_CTIIRQ_CTIOUTEN31 (0x00B9611C) +#define DBG_CTIIRQ_CTIOUTEN31___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIOUTEN31___POR 0x00000000 +#define DBG_CTIIRQ_CTIOUTEN31__TRIGOUTEN___POR 0x00 +#define DBG_CTIIRQ_CTIOUTEN31__TRIGOUTEN___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN31__TRIGOUTEN___S 0 +#define DBG_CTIIRQ_CTIOUTEN31___M 0x000000FF +#define DBG_CTIIRQ_CTIOUTEN31___S 0 + +#define DBG_CTIIRQ_CTITRIGINSTATUS (0x00B96130) +#define DBG_CTIIRQ_CTITRIGINSTATUS___RWC QCSR_REG_RO +#define DBG_CTIIRQ_CTITRIGINSTATUS__TRIGINSTATUS___M 0xFFFFFFFF +#define DBG_CTIIRQ_CTITRIGINSTATUS__TRIGINSTATUS___S 0 +#define DBG_CTIIRQ_CTITRIGINSTATUS___M 0xFFFFFFFF +#define DBG_CTIIRQ_CTITRIGINSTATUS___S 0 + +#define DBG_CTIIRQ_CTITRIGOUTSTATUS (0x00B96134) +#define DBG_CTIIRQ_CTITRIGOUTSTATUS___RWC QCSR_REG_RO +#define DBG_CTIIRQ_CTITRIGOUTSTATUS___POR 0x00000000 +#define DBG_CTIIRQ_CTITRIGOUTSTATUS__TRIGOUTSTATUS___POR 0x00000000 +#define DBG_CTIIRQ_CTITRIGOUTSTATUS__TRIGOUTSTATUS___M 0xFFFFFFFF +#define DBG_CTIIRQ_CTITRIGOUTSTATUS__TRIGOUTSTATUS___S 0 +#define DBG_CTIIRQ_CTITRIGOUTSTATUS___M 0xFFFFFFFF +#define DBG_CTIIRQ_CTITRIGOUTSTATUS___S 0 + +#define DBG_CTIIRQ_CTICHINSTATUS (0x00B96138) +#define DBG_CTIIRQ_CTICHINSTATUS___RWC QCSR_REG_RO +#define DBG_CTIIRQ_CTICHINSTATUS__CTICHINSTATUS___M 0x000000FF +#define DBG_CTIIRQ_CTICHINSTATUS__CTICHINSTATUS___S 0 +#define DBG_CTIIRQ_CTICHINSTATUS___M 0x000000FF +#define DBG_CTIIRQ_CTICHINSTATUS___S 0 + +#define DBG_CTIIRQ_CTICHOUTSTATUS (0x00B9613C) +#define DBG_CTIIRQ_CTICHOUTSTATUS___RWC QCSR_REG_RO +#define DBG_CTIIRQ_CTICHOUTSTATUS___POR 0x00000000 +#define DBG_CTIIRQ_CTICHOUTSTATUS__CTICHOUTSTATUS___POR 0x00 +#define DBG_CTIIRQ_CTICHOUTSTATUS__CTICHOUTSTATUS___M 0x000000FF +#define DBG_CTIIRQ_CTICHOUTSTATUS__CTICHOUTSTATUS___S 0 +#define DBG_CTIIRQ_CTICHOUTSTATUS___M 0x000000FF +#define DBG_CTIIRQ_CTICHOUTSTATUS___S 0 + +#define DBG_CTIIRQ_CTIGATE (0x00B96140) +#define DBG_CTIIRQ_CTIGATE___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CTIGATE___POR 0x000000FF +#define DBG_CTIIRQ_CTIGATE__CTIGATEEN7___POR 0x1 +#define DBG_CTIIRQ_CTIGATE__CTIGATEEN6___POR 0x1 +#define DBG_CTIIRQ_CTIGATE__CTIGATEEN5___POR 0x1 +#define DBG_CTIIRQ_CTIGATE__CTIGATEEN4___POR 0x1 +#define DBG_CTIIRQ_CTIGATE__CTIGATEEN3___POR 0x1 +#define DBG_CTIIRQ_CTIGATE__CTIGATEEN2___POR 0x1 +#define DBG_CTIIRQ_CTIGATE__CTIGATEEN1___POR 0x1 +#define DBG_CTIIRQ_CTIGATE__CTIGATEEN0___POR 0x1 +#define DBG_CTIIRQ_CTIGATE__CTIGATEEN7___M 0x00000080 +#define DBG_CTIIRQ_CTIGATE__CTIGATEEN7___S 7 +#define DBG_CTIIRQ_CTIGATE__CTIGATEEN6___M 0x00000040 +#define DBG_CTIIRQ_CTIGATE__CTIGATEEN6___S 6 +#define DBG_CTIIRQ_CTIGATE__CTIGATEEN5___M 0x00000020 +#define DBG_CTIIRQ_CTIGATE__CTIGATEEN5___S 5 +#define DBG_CTIIRQ_CTIGATE__CTIGATEEN4___M 0x00000010 +#define DBG_CTIIRQ_CTIGATE__CTIGATEEN4___S 4 +#define DBG_CTIIRQ_CTIGATE__CTIGATEEN3___M 0x00000008 +#define DBG_CTIIRQ_CTIGATE__CTIGATEEN3___S 3 +#define DBG_CTIIRQ_CTIGATE__CTIGATEEN2___M 0x00000004 +#define DBG_CTIIRQ_CTIGATE__CTIGATEEN2___S 2 +#define DBG_CTIIRQ_CTIGATE__CTIGATEEN1___M 0x00000002 +#define DBG_CTIIRQ_CTIGATE__CTIGATEEN1___S 1 +#define DBG_CTIIRQ_CTIGATE__CTIGATEEN0___M 0x00000001 +#define DBG_CTIIRQ_CTIGATE__CTIGATEEN0___S 0 +#define DBG_CTIIRQ_CTIGATE___M 0x000000FF +#define DBG_CTIIRQ_CTIGATE___S 0 + +#define DBG_CTIIRQ_ASICCTL (0x00B96144) +#define DBG_CTIIRQ_ASICCTL___RWC QCSR_REG_RW +#define DBG_CTIIRQ_ASICCTL___POR 0x00000000 +#define DBG_CTIIRQ_ASICCTL__ASICCTL___POR 0x00000000 +#define DBG_CTIIRQ_ASICCTL__ASICCTL___M 0xFFFFFFFF +#define DBG_CTIIRQ_ASICCTL__ASICCTL___S 0 +#define DBG_CTIIRQ_ASICCTL___M 0xFFFFFFFF +#define DBG_CTIIRQ_ASICCTL___S 0 + +#define DBG_CTIIRQ_ITCHINACK (0x00B96EDC) +#define DBG_CTIIRQ_ITCHINACK___RWC QCSR_REG_WO +#define DBG_CTIIRQ_ITCHINACK___POR 0x00000000 +#define DBG_CTIIRQ_ITCHINACK__CTCHINACK___POR 0x00 +#define DBG_CTIIRQ_ITCHINACK__CTCHINACK___M 0x000000FF +#define DBG_CTIIRQ_ITCHINACK__CTCHINACK___S 0 +#define DBG_CTIIRQ_ITCHINACK___M 0x000000FF +#define DBG_CTIIRQ_ITCHINACK___S 0 + +#define DBG_CTIIRQ_ITTRIGINACK (0x00B96EE0) +#define DBG_CTIIRQ_ITTRIGINACK___RWC QCSR_REG_WO +#define DBG_CTIIRQ_ITTRIGINACK___POR 0x00000000 +#define DBG_CTIIRQ_ITTRIGINACK__CTTRIGINACK___POR 0x00000000 +#define DBG_CTIIRQ_ITTRIGINACK__CTTRIGINACK___M 0xFFFFFFFF +#define DBG_CTIIRQ_ITTRIGINACK__CTTRIGINACK___S 0 +#define DBG_CTIIRQ_ITTRIGINACK___M 0xFFFFFFFF +#define DBG_CTIIRQ_ITTRIGINACK___S 0 + +#define DBG_CTIIRQ_ITCHOUT (0x00B96EE4) +#define DBG_CTIIRQ_ITCHOUT___RWC QCSR_REG_WO +#define DBG_CTIIRQ_ITCHOUT___POR 0x00000000 +#define DBG_CTIIRQ_ITCHOUT__CTCHOUT___POR 0x00 +#define DBG_CTIIRQ_ITCHOUT__CTCHOUT___M 0x000000FF +#define DBG_CTIIRQ_ITCHOUT__CTCHOUT___S 0 +#define DBG_CTIIRQ_ITCHOUT___M 0x000000FF +#define DBG_CTIIRQ_ITCHOUT___S 0 + +#define DBG_CTIIRQ_ITTRIGOUT (0x00B96EE8) +#define DBG_CTIIRQ_ITTRIGOUT___RWC QCSR_REG_WO +#define DBG_CTIIRQ_ITTRIGOUT___POR 0x00000000 +#define DBG_CTIIRQ_ITTRIGOUT__CTTRIGOUT___POR 0x00000000 +#define DBG_CTIIRQ_ITTRIGOUT__CTTRIGOUT___M 0xFFFFFFFF +#define DBG_CTIIRQ_ITTRIGOUT__CTTRIGOUT___S 0 +#define DBG_CTIIRQ_ITTRIGOUT___M 0xFFFFFFFF +#define DBG_CTIIRQ_ITTRIGOUT___S 0 + +#define DBG_CTIIRQ_ITCHOUTACK (0x00B96EEC) +#define DBG_CTIIRQ_ITCHOUTACK___RWC QCSR_REG_RO +#define DBG_CTIIRQ_ITCHOUTACK___POR 0x00000000 +#define DBG_CTIIRQ_ITCHOUTACK__CTCHOUTACK___POR 0x00 +#define DBG_CTIIRQ_ITCHOUTACK__CTCHOUTACK___M 0x000000FF +#define DBG_CTIIRQ_ITCHOUTACK__CTCHOUTACK___S 0 +#define DBG_CTIIRQ_ITCHOUTACK___M 0x000000FF +#define DBG_CTIIRQ_ITCHOUTACK___S 0 + +#define DBG_CTIIRQ_ITTRIGOUTACK (0x00B96EF0) +#define DBG_CTIIRQ_ITTRIGOUTACK___RWC QCSR_REG_RO +#define DBG_CTIIRQ_ITTRIGOUTACK___POR 0x00000000 +#define DBG_CTIIRQ_ITTRIGOUTACK__CTTRIGOUTACK___POR 0x00000000 +#define DBG_CTIIRQ_ITTRIGOUTACK__CTTRIGOUTACK___M 0xFFFFFFFF +#define DBG_CTIIRQ_ITTRIGOUTACK__CTTRIGOUTACK___S 0 +#define DBG_CTIIRQ_ITTRIGOUTACK___M 0xFFFFFFFF +#define DBG_CTIIRQ_ITTRIGOUTACK___S 0 + +#define DBG_CTIIRQ_ITCHIN (0x00B96EF4) +#define DBG_CTIIRQ_ITCHIN___RWC QCSR_REG_RO +#define DBG_CTIIRQ_ITCHIN___POR 0x00000000 +#define DBG_CTIIRQ_ITCHIN__CTCHIN___POR 0x00 +#define DBG_CTIIRQ_ITCHIN__CTCHIN___M 0x000000FF +#define DBG_CTIIRQ_ITCHIN__CTCHIN___S 0 +#define DBG_CTIIRQ_ITCHIN___M 0x000000FF +#define DBG_CTIIRQ_ITCHIN___S 0 + +#define DBG_CTIIRQ_ITTRIGIN (0x00B96EF8) +#define DBG_CTIIRQ_ITTRIGIN___RWC QCSR_REG_RO +#define DBG_CTIIRQ_ITTRIGIN___POR 0x00000000 +#define DBG_CTIIRQ_ITTRIGIN__CTTRIGIN___POR 0x00000000 +#define DBG_CTIIRQ_ITTRIGIN__CTTRIGIN___M 0xFFFFFFFF +#define DBG_CTIIRQ_ITTRIGIN__CTTRIGIN___S 0 +#define DBG_CTIIRQ_ITTRIGIN___M 0xFFFFFFFF +#define DBG_CTIIRQ_ITTRIGIN___S 0 + +#define DBG_CTIIRQ_ITCTRL (0x00B96F00) +#define DBG_CTIIRQ_ITCTRL___RWC QCSR_REG_RW +#define DBG_CTIIRQ_ITCTRL___POR 0x00000000 +#define DBG_CTIIRQ_ITCTRL__INTEGRATION_MODE___POR 0x0 +#define DBG_CTIIRQ_ITCTRL__INTEGRATION_MODE___M 0x00000001 +#define DBG_CTIIRQ_ITCTRL__INTEGRATION_MODE___S 0 +#define DBG_CTIIRQ_ITCTRL__INTEGRATION_MODE__FUNCTIONAL_MODE 0x0 +#define DBG_CTIIRQ_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE 0x1 +#define DBG_CTIIRQ_ITCTRL___M 0x00000001 +#define DBG_CTIIRQ_ITCTRL___S 0 + +#define DBG_CTIIRQ_CLAIMSET (0x00B96FA0) +#define DBG_CTIIRQ_CLAIMSET___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CLAIMSET___POR 0x0000000F +#define DBG_CTIIRQ_CLAIMSET__CLAIMSET___POR 0xF +#define DBG_CTIIRQ_CLAIMSET__CLAIMSET___M 0x0000000F +#define DBG_CTIIRQ_CLAIMSET__CLAIMSET___S 0 +#define DBG_CTIIRQ_CLAIMSET__CLAIMSET__CLAIM_TAG_IMPLEMENTED_BITS 0xF +#define DBG_CTIIRQ_CLAIMSET___M 0x0000000F +#define DBG_CTIIRQ_CLAIMSET___S 0 + +#define DBG_CTIIRQ_CLAIMCLR (0x00B96FA4) +#define DBG_CTIIRQ_CLAIMCLR___RWC QCSR_REG_RW +#define DBG_CTIIRQ_CLAIMCLR___POR 0x00000000 +#define DBG_CTIIRQ_CLAIMCLR__CLAIMCLR___POR 0x0 +#define DBG_CTIIRQ_CLAIMCLR__CLAIMCLR___M 0x0000000F +#define DBG_CTIIRQ_CLAIMCLR__CLAIMCLR___S 0 +#define DBG_CTIIRQ_CLAIMCLR___M 0x0000000F +#define DBG_CTIIRQ_CLAIMCLR___S 0 + +#define DBG_CTIIRQ_DEVAFF0 (0x00B96FA8) +#define DBG_CTIIRQ_DEVAFF0___RWC QCSR_REG_RO +#define DBG_CTIIRQ_DEVAFF0___POR 0x00000000 +#define DBG_CTIIRQ_DEVAFF0__VAL___POR 0x00000000 +#define DBG_CTIIRQ_DEVAFF0__VAL___M 0xFFFFFFFF +#define DBG_CTIIRQ_DEVAFF0__VAL___S 0 +#define DBG_CTIIRQ_DEVAFF0___M 0xFFFFFFFF +#define DBG_CTIIRQ_DEVAFF0___S 0 + +#define DBG_CTIIRQ_DEVAFF1 (0x00B96FAC) +#define DBG_CTIIRQ_DEVAFF1___RWC QCSR_REG_RO +#define DBG_CTIIRQ_DEVAFF1___POR 0x00000000 +#define DBG_CTIIRQ_DEVAFF1__VAL___POR 0x00000000 +#define DBG_CTIIRQ_DEVAFF1__VAL___M 0xFFFFFFFF +#define DBG_CTIIRQ_DEVAFF1__VAL___S 0 +#define DBG_CTIIRQ_DEVAFF1___M 0xFFFFFFFF +#define DBG_CTIIRQ_DEVAFF1___S 0 + +#define DBG_CTIIRQ_LAR (0x00B96FB0) +#define DBG_CTIIRQ_LAR___RWC QCSR_REG_WO +#define DBG_CTIIRQ_LAR__ACCESS_W___M 0xFFFFFFFF +#define DBG_CTIIRQ_LAR__ACCESS_W___S 0 +#define DBG_CTIIRQ_LAR__ACCESS_W__UNLOCK 0xC5ACCE55 +#define DBG_CTIIRQ_LAR___M 0xFFFFFFFF +#define DBG_CTIIRQ_LAR___S 0 + +#define DBG_CTIIRQ_LSR (0x00B96FB4) +#define DBG_CTIIRQ_LSR___RWC QCSR_REG_RO +#define DBG_CTIIRQ_LSR___POR 0x00000003 +#define DBG_CTIIRQ_LSR__LOCKTYPE___POR 0x0 +#define DBG_CTIIRQ_LSR__LOCKGRANT___POR 0x1 +#define DBG_CTIIRQ_LSR__LOCKEXIST___POR 0x1 +#define DBG_CTIIRQ_LSR__LOCKTYPE___M 0x00000004 +#define DBG_CTIIRQ_LSR__LOCKTYPE___S 2 +#define DBG_CTIIRQ_LSR__LOCKTYPE__SIZE_32BIT 0x0 +#define DBG_CTIIRQ_LSR__LOCKGRANT___M 0x00000002 +#define DBG_CTIIRQ_LSR__LOCKGRANT___S 1 +#define DBG_CTIIRQ_LSR__LOCKGRANT__ACCESS_PERMITTED 0x0 +#define DBG_CTIIRQ_LSR__LOCKGRANT__DEVICE_LOCKED 0x1 +#define DBG_CTIIRQ_LSR__LOCKEXIST___M 0x00000001 +#define DBG_CTIIRQ_LSR__LOCKEXIST___S 0 +#define DBG_CTIIRQ_LSR__LOCKEXIST__LOCK_NOT_PRESENT 0x0 +#define DBG_CTIIRQ_LSR__LOCKEXIST__LOCK_PRESENT 0x1 +#define DBG_CTIIRQ_LSR___M 0x00000007 +#define DBG_CTIIRQ_LSR___S 0 + +#define DBG_CTIIRQ_AUTHSTATUS (0x00B96FB8) +#define DBG_CTIIRQ_AUTHSTATUS___RWC QCSR_REG_RO +#define DBG_CTIIRQ_AUTHSTATUS__SNID___M 0x000000C0 +#define DBG_CTIIRQ_AUTHSTATUS__SNID___S 6 +#define DBG_CTIIRQ_AUTHSTATUS__SNID__NOT_IMPLEMENTED 0x0 +#define DBG_CTIIRQ_AUTHSTATUS__SID___M 0x00000030 +#define DBG_CTIIRQ_AUTHSTATUS__SID___S 4 +#define DBG_CTIIRQ_AUTHSTATUS__SID__NOT_IMPLEMENTED 0x0 +#define DBG_CTIIRQ_AUTHSTATUS__NSNID___M 0x0000000C +#define DBG_CTIIRQ_AUTHSTATUS__NSNID___S 2 +#define DBG_CTIIRQ_AUTHSTATUS__NSNID__DISABLED 0x2 +#define DBG_CTIIRQ_AUTHSTATUS__NSNID__ENABLED 0x3 +#define DBG_CTIIRQ_AUTHSTATUS__NSID___M 0x00000003 +#define DBG_CTIIRQ_AUTHSTATUS__NSID___S 0 +#define DBG_CTIIRQ_AUTHSTATUS__NSID__DISABLED 0x2 +#define DBG_CTIIRQ_AUTHSTATUS__NSID__ENABLED 0x3 +#define DBG_CTIIRQ_AUTHSTATUS___M 0x000000FF +#define DBG_CTIIRQ_AUTHSTATUS___S 0 + +#define DBG_CTIIRQ_DEVARCH (0x00B96FBC) +#define DBG_CTIIRQ_DEVARCH___RWC QCSR_REG_RO +#define DBG_CTIIRQ_DEVARCH___POR 0x8EF00A14 +#define DBG_CTIIRQ_DEVARCH__ARCHITECT___POR 0x477 +#define DBG_CTIIRQ_DEVARCH__PRESENT___POR 0x1 +#define DBG_CTIIRQ_DEVARCH__REVISION___POR 0x0 +#define DBG_CTIIRQ_DEVARCH__ARCHID___POR 0x0A14 +#define DBG_CTIIRQ_DEVARCH__ARCHITECT___M 0xFFE00000 +#define DBG_CTIIRQ_DEVARCH__ARCHITECT___S 21 +#define DBG_CTIIRQ_DEVARCH__PRESENT___M 0x00100000 +#define DBG_CTIIRQ_DEVARCH__PRESENT___S 20 +#define DBG_CTIIRQ_DEVARCH__REVISION___M 0x000F0000 +#define DBG_CTIIRQ_DEVARCH__REVISION___S 16 +#define DBG_CTIIRQ_DEVARCH__ARCHID___M 0x0000FFFF +#define DBG_CTIIRQ_DEVARCH__ARCHID___S 0 +#define DBG_CTIIRQ_DEVARCH___M 0xFFFFFFFF +#define DBG_CTIIRQ_DEVARCH___S 0 + +#define DBG_CTIIRQ_DEVID2 (0x00B96FC0) +#define DBG_CTIIRQ_DEVID2___RWC QCSR_REG_RO +#define DBG_CTIIRQ_DEVID2___POR 0x00000000 +#define DBG_CTIIRQ_DEVID2__IMPLDEF___POR 0x0 +#define DBG_CTIIRQ_DEVID2__IMPLDEF___M 0x00000001 +#define DBG_CTIIRQ_DEVID2__IMPLDEF___S 0 +#define DBG_CTIIRQ_DEVID2___M 0x00000001 +#define DBG_CTIIRQ_DEVID2___S 0 + +#define DBG_CTIIRQ_DEVID1 (0x00B96FC4) +#define DBG_CTIIRQ_DEVID1___RWC QCSR_REG_RO +#define DBG_CTIIRQ_DEVID1___POR 0x00000000 +#define DBG_CTIIRQ_DEVID1__IMPLDEF___POR 0x0 +#define DBG_CTIIRQ_DEVID1__IMPLDEF___M 0x00000001 +#define DBG_CTIIRQ_DEVID1__IMPLDEF___S 0 +#define DBG_CTIIRQ_DEVID1___M 0x00000001 +#define DBG_CTIIRQ_DEVID1___S 0 + +#define DBG_CTIIRQ_DEVID (0x00B96FC8) +#define DBG_CTIIRQ_DEVID___RWC QCSR_REG_RO +#define DBG_CTIIRQ_DEVID___POR 0x00082000 +#define DBG_CTIIRQ_DEVID__NUMCH___POR 0x8 +#define DBG_CTIIRQ_DEVID__NUMTRIG___POR 0x20 +#define DBG_CTIIRQ_DEVID__EXTMUXNUM___POR 0x00 +#define DBG_CTIIRQ_DEVID__NUMCH___M 0x003F0000 +#define DBG_CTIIRQ_DEVID__NUMCH___S 16 +#define DBG_CTIIRQ_DEVID__NUMTRIG___M 0x0000FF00 +#define DBG_CTIIRQ_DEVID__NUMTRIG___S 8 +#define DBG_CTIIRQ_DEVID__EXTMUXNUM___M 0x0000001F +#define DBG_CTIIRQ_DEVID__EXTMUXNUM___S 0 +#define DBG_CTIIRQ_DEVID___M 0x003FFF1F +#define DBG_CTIIRQ_DEVID___S 0 + +#define DBG_CTIIRQ_DEVTYPE (0x00B96FCC) +#define DBG_CTIIRQ_DEVTYPE___RWC QCSR_REG_RO +#define DBG_CTIIRQ_DEVTYPE___POR 0x00000014 +#define DBG_CTIIRQ_DEVTYPE__SUB_TYPE___POR 0x1 +#define DBG_CTIIRQ_DEVTYPE__MAJOR_TYPE___POR 0x4 +#define DBG_CTIIRQ_DEVTYPE__SUB_TYPE___M 0x000000F0 +#define DBG_CTIIRQ_DEVTYPE__SUB_TYPE___S 4 +#define DBG_CTIIRQ_DEVTYPE__SUB_TYPE__TRIGGER_MATRIX 0x1 +#define DBG_CTIIRQ_DEVTYPE__MAJOR_TYPE___M 0x0000000F +#define DBG_CTIIRQ_DEVTYPE__MAJOR_TYPE___S 0 +#define DBG_CTIIRQ_DEVTYPE__MAJOR_TYPE__DEBUG_CONTROL 0x4 +#define DBG_CTIIRQ_DEVTYPE___M 0x000000FF +#define DBG_CTIIRQ_DEVTYPE___S 0 + +#define DBG_CTIIRQ_PIDR0 (0x00B96FE0) +#define DBG_CTIIRQ_PIDR0___RWC QCSR_REG_RO +#define DBG_CTIIRQ_PIDR0___POR 0x00000006 +#define DBG_CTIIRQ_PIDR0__PART_0___POR 0x06 +#define DBG_CTIIRQ_PIDR0__PART_0___M 0x000000FF +#define DBG_CTIIRQ_PIDR0__PART_0___S 0 +#define DBG_CTIIRQ_PIDR0__PART_0__CTI_PART_NUMBER_7_0 0x06 +#define DBG_CTIIRQ_PIDR0___M 0x000000FF +#define DBG_CTIIRQ_PIDR0___S 0 + +#define DBG_CTIIRQ_PIDR1 (0x00B96FE4) +#define DBG_CTIIRQ_PIDR1___RWC QCSR_REG_RO +#define DBG_CTIIRQ_PIDR1___POR 0x000000B9 +#define DBG_CTIIRQ_PIDR1__DES_0___POR 0xB +#define DBG_CTIIRQ_PIDR1__PART_1___POR 0x9 +#define DBG_CTIIRQ_PIDR1__DES_0___M 0x000000F0 +#define DBG_CTIIRQ_PIDR1__DES_0___S 4 +#define DBG_CTIIRQ_PIDR1__DES_0__ARM_JEP106_IDENTITY_CODE_3_0 0xB +#define DBG_CTIIRQ_PIDR1__PART_1___M 0x0000000F +#define DBG_CTIIRQ_PIDR1__PART_1___S 0 +#define DBG_CTIIRQ_PIDR1__PART_1__CTI_PART_NUMBER_11_8 0x9 +#define DBG_CTIIRQ_PIDR1___M 0x000000FF +#define DBG_CTIIRQ_PIDR1___S 0 + +#define DBG_CTIIRQ_PIDR2 (0x00B96FE8) +#define DBG_CTIIRQ_PIDR2___RWC QCSR_REG_RO +#define DBG_CTIIRQ_PIDR2___POR 0x0000004B +#define DBG_CTIIRQ_PIDR2__REVISION___POR 0x4 +#define DBG_CTIIRQ_PIDR2__JEDEC___POR 0x1 +#define DBG_CTIIRQ_PIDR2__DES_1___POR 0x3 +#define DBG_CTIIRQ_PIDR2__REVISION___M 0x000000F0 +#define DBG_CTIIRQ_PIDR2__REVISION___S 4 +#define DBG_CTIIRQ_PIDR2__REVISION__R0P4 0x4 +#define DBG_CTIIRQ_PIDR2__REVISION__R0P5 0x5 +#define DBG_CTIIRQ_PIDR2__JEDEC___M 0x00000008 +#define DBG_CTIIRQ_PIDR2__JEDEC___S 3 +#define DBG_CTIIRQ_PIDR2__JEDEC__JEDEC_IDENTITY 0x1 +#define DBG_CTIIRQ_PIDR2__DES_1___M 0x00000007 +#define DBG_CTIIRQ_PIDR2__DES_1___S 0 +#define DBG_CTIIRQ_PIDR2__DES_1__ARM_JEP106_IDENTITY_CODE_6_4 0x3 +#define DBG_CTIIRQ_PIDR2___M 0x000000FF +#define DBG_CTIIRQ_PIDR2___S 0 + +#define DBG_CTIIRQ_PIDR3 (0x00B96FEC) +#define DBG_CTIIRQ_PIDR3___RWC QCSR_REG_RO +#define DBG_CTIIRQ_PIDR3___POR 0x00000000 +#define DBG_CTIIRQ_PIDR3__REVAND___POR 0x0 +#define DBG_CTIIRQ_PIDR3__CMOD___POR 0x0 +#define DBG_CTIIRQ_PIDR3__REVAND___M 0x000000F0 +#define DBG_CTIIRQ_PIDR3__REVAND___S 4 +#define DBG_CTIIRQ_PIDR3__REVAND__NO_MODIFICATION 0x0 +#define DBG_CTIIRQ_PIDR3__CMOD___M 0x0000000F +#define DBG_CTIIRQ_PIDR3__CMOD___S 0 +#define DBG_CTIIRQ_PIDR3__CMOD__NO_MODIFICATION 0x0 +#define DBG_CTIIRQ_PIDR3___M 0x000000FF +#define DBG_CTIIRQ_PIDR3___S 0 + +#define DBG_CTIIRQ_PIDR4 (0x00B96FD0) +#define DBG_CTIIRQ_PIDR4___RWC QCSR_REG_RO +#define DBG_CTIIRQ_PIDR4___POR 0x00000004 +#define DBG_CTIIRQ_PIDR4__SIZE___POR 0x0 +#define DBG_CTIIRQ_PIDR4__DES_2___POR 0x4 +#define DBG_CTIIRQ_PIDR4__SIZE___M 0x000000F0 +#define DBG_CTIIRQ_PIDR4__SIZE___S 4 +#define DBG_CTIIRQ_PIDR4__SIZE__SIZE_4KB 0x0 +#define DBG_CTIIRQ_PIDR4__DES_2___M 0x0000000F +#define DBG_CTIIRQ_PIDR4__DES_2___S 0 +#define DBG_CTIIRQ_PIDR4__DES_2__ARM_JEP106_CONTINUATION_CODE 0x4 +#define DBG_CTIIRQ_PIDR4___M 0x000000FF +#define DBG_CTIIRQ_PIDR4___S 0 + +#define DBG_CTIIRQ_PIDR5 (0x00B96FD4) +#define DBG_CTIIRQ_PIDR5___RWC QCSR_REG_RW +#define DBG_CTIIRQ_PIDR5__PERIPHID5___M 0xFFFFFFFF +#define DBG_CTIIRQ_PIDR5__PERIPHID5___S 0 +#define DBG_CTIIRQ_PIDR5___M 0xFFFFFFFF +#define DBG_CTIIRQ_PIDR5___S 0 + +#define DBG_CTIIRQ_PIDR6 (0x00B96FD8) +#define DBG_CTIIRQ_PIDR6___RWC QCSR_REG_RW +#define DBG_CTIIRQ_PIDR6__PERIPHID6___M 0xFFFFFFFF +#define DBG_CTIIRQ_PIDR6__PERIPHID6___S 0 +#define DBG_CTIIRQ_PIDR6___M 0xFFFFFFFF +#define DBG_CTIIRQ_PIDR6___S 0 + +#define DBG_CTIIRQ_PIDR7 (0x00B96FDC) +#define DBG_CTIIRQ_PIDR7___RWC QCSR_REG_RW +#define DBG_CTIIRQ_PIDR7__PERIPHID7___M 0xFFFFFFFF +#define DBG_CTIIRQ_PIDR7__PERIPHID7___S 0 +#define DBG_CTIIRQ_PIDR7___M 0xFFFFFFFF +#define DBG_CTIIRQ_PIDR7___S 0 + +#define DBG_CTIIRQ_CIDR0 (0x00B96FF0) +#define DBG_CTIIRQ_CIDR0___RWC QCSR_REG_RO +#define DBG_CTIIRQ_CIDR0___POR 0x0000000D +#define DBG_CTIIRQ_CIDR0__PRMBL_0___POR 0x0D +#define DBG_CTIIRQ_CIDR0__PRMBL_0___M 0x000000FF +#define DBG_CTIIRQ_CIDR0__PRMBL_0___S 0 +#define DBG_CTIIRQ_CIDR0__PRMBL_0__ID_VALUE_0D 0x0D +#define DBG_CTIIRQ_CIDR0___M 0x000000FF +#define DBG_CTIIRQ_CIDR0___S 0 + +#define DBG_CTIIRQ_CIDR1 (0x00B96FF4) +#define DBG_CTIIRQ_CIDR1___RWC QCSR_REG_RO +#define DBG_CTIIRQ_CIDR1___POR 0x00000090 +#define DBG_CTIIRQ_CIDR1__CLASS___POR 0x9 +#define DBG_CTIIRQ_CIDR1__PRMBL_1___POR 0x0 +#define DBG_CTIIRQ_CIDR1__CLASS___M 0x000000F0 +#define DBG_CTIIRQ_CIDR1__CLASS___S 4 +#define DBG_CTIIRQ_CIDR1__CLASS__CORESIGHT_COMPONENT 0x9 +#define DBG_CTIIRQ_CIDR1__PRMBL_1___M 0x0000000F +#define DBG_CTIIRQ_CIDR1__PRMBL_1___S 0 +#define DBG_CTIIRQ_CIDR1__PRMBL_1__ID_VALUE_0 0x0 +#define DBG_CTIIRQ_CIDR1___M 0x000000FF +#define DBG_CTIIRQ_CIDR1___S 0 + +#define DBG_CTIIRQ_CIDR2 (0x00B96FF8) +#define DBG_CTIIRQ_CIDR2___RWC QCSR_REG_RO +#define DBG_CTIIRQ_CIDR2___POR 0x00000005 +#define DBG_CTIIRQ_CIDR2__PRMBL_2___POR 0x05 +#define DBG_CTIIRQ_CIDR2__PRMBL_2___M 0x000000FF +#define DBG_CTIIRQ_CIDR2__PRMBL_2___S 0 +#define DBG_CTIIRQ_CIDR2__PRMBL_2__ID_VALUE_05 0x05 +#define DBG_CTIIRQ_CIDR2___M 0x000000FF +#define DBG_CTIIRQ_CIDR2___S 0 + +#define DBG_CTIIRQ_CIDR3 (0x00B96FFC) +#define DBG_CTIIRQ_CIDR3___RWC QCSR_REG_RO +#define DBG_CTIIRQ_CIDR3___POR 0x000000B1 +#define DBG_CTIIRQ_CIDR3__PRMBL_3___POR 0xB1 +#define DBG_CTIIRQ_CIDR3__PRMBL_3___M 0x000000FF +#define DBG_CTIIRQ_CIDR3__PRMBL_3___S 0 +#define DBG_CTIIRQ_CIDR3__PRMBL_3__ID_VALUE_B1 0xB1 +#define DBG_CTIIRQ_CIDR3___M 0x000000FF +#define DBG_CTIIRQ_CIDR3___S 0 + +#define DBG_EVENT_MACEVENT_CFG (0x00BB0000) +#define DBG_EVENT_MACEVENT_CFG___RWC QCSR_REG_RW +#define DBG_EVENT_MACEVENT_CFG___POR 0x00003BE3 +#define DBG_EVENT_MACEVENT_CFG__LMAC0_EN___POR 0x1 +#define DBG_EVENT_MACEVENT_CFG__UMAC_EN___POR 0x1 +#define DBG_EVENT_MACEVENT_CFG__ATID___POR 0x5F +#define DBG_EVENT_MACEVENT_CFG__TRANSPORT___POR 0x0 +#define DBG_EVENT_MACEVENT_CFG__TRCCFG___POR 0x0 +#define DBG_EVENT_MACEVENT_CFG__COLTRIG_EN___POR 0x0 +#define DBG_EVENT_MACEVENT_CFG__TSTMP_EN___POR 0x1 +#define DBG_EVENT_MACEVENT_CFG__ENABLE___POR 0x1 +#define DBG_EVENT_MACEVENT_CFG__LMAC0_EN___M 0x00002000 +#define DBG_EVENT_MACEVENT_CFG__LMAC0_EN___S 13 +#define DBG_EVENT_MACEVENT_CFG__UMAC_EN___M 0x00001000 +#define DBG_EVENT_MACEVENT_CFG__UMAC_EN___S 12 +#define DBG_EVENT_MACEVENT_CFG__ATID___M 0x00000FE0 +#define DBG_EVENT_MACEVENT_CFG__ATID___S 5 +#define DBG_EVENT_MACEVENT_CFG__TRANSPORT___M 0x00000010 +#define DBG_EVENT_MACEVENT_CFG__TRANSPORT___S 4 +#define DBG_EVENT_MACEVENT_CFG__TRANSPORT__CMB 0x0 +#define DBG_EVENT_MACEVENT_CFG__TRANSPORT__ATB 0x1 +#define DBG_EVENT_MACEVENT_CFG__TRCCFG___M 0x00000008 +#define DBG_EVENT_MACEVENT_CFG__TRCCFG___S 3 +#define DBG_EVENT_MACEVENT_CFG__TRCCFG__CFG0 0x0 +#define DBG_EVENT_MACEVENT_CFG__TRCCFG__CFG1 0x1 +#define DBG_EVENT_MACEVENT_CFG__COLTRIG_EN___M 0x00000004 +#define DBG_EVENT_MACEVENT_CFG__COLTRIG_EN___S 2 +#define DBG_EVENT_MACEVENT_CFG__TSTMP_EN___M 0x00000002 +#define DBG_EVENT_MACEVENT_CFG__TSTMP_EN___S 1 +#define DBG_EVENT_MACEVENT_CFG__ENABLE___M 0x00000001 +#define DBG_EVENT_MACEVENT_CFG__ENABLE___S 0 +#define DBG_EVENT_MACEVENT_CFG___M 0x00003FFF +#define DBG_EVENT_MACEVENT_CFG___S 0 + +#define DBG_EVENT_MACEVENT_TGU_CFG (0x00BB0004) +#define DBG_EVENT_MACEVENT_TGU_CFG___RWC QCSR_REG_RW +#define DBG_EVENT_MACEVENT_TGU_CFG___POR 0x000000F0 +#define DBG_EVENT_MACEVENT_TGU_CFG__TRIG_COMBOP___POR 0x0 +#define DBG_EVENT_MACEVENT_TGU_CFG__TRIG_POL___POR 0xF +#define DBG_EVENT_MACEVENT_TGU_CFG__TRIG_EN___POR 0x0 +#define DBG_EVENT_MACEVENT_TGU_CFG__TRIG_COMBOP___M 0x00000100 +#define DBG_EVENT_MACEVENT_TGU_CFG__TRIG_COMBOP___S 8 +#define DBG_EVENT_MACEVENT_TGU_CFG__TRIG_POL___M 0x000000F0 +#define DBG_EVENT_MACEVENT_TGU_CFG__TRIG_POL___S 4 +#define DBG_EVENT_MACEVENT_TGU_CFG__TRIG_EN___M 0x0000000F +#define DBG_EVENT_MACEVENT_TGU_CFG__TRIG_EN___S 0 +#define DBG_EVENT_MACEVENT_TGU_CFG___M 0x000001FF +#define DBG_EVENT_MACEVENT_TGU_CFG___S 0 + +#define DBG_EVENT_MACEVENT_MATCH0_DATA (0x00BB0008) +#define DBG_EVENT_MACEVENT_MATCH0_DATA___RWC QCSR_REG_RW +#define DBG_EVENT_MACEVENT_MATCH0_DATA___POR 0x00000000 +#define DBG_EVENT_MACEVENT_MATCH0_DATA__DATA___POR 0x00000000 +#define DBG_EVENT_MACEVENT_MATCH0_DATA__DATA___M 0xFFFFFFFF +#define DBG_EVENT_MACEVENT_MATCH0_DATA__DATA___S 0 +#define DBG_EVENT_MACEVENT_MATCH0_DATA___M 0xFFFFFFFF +#define DBG_EVENT_MACEVENT_MATCH0_DATA___S 0 + +#define DBG_EVENT_MACEVENT_MATCH0_DATAH (0x00BB000C) +#define DBG_EVENT_MACEVENT_MATCH0_DATAH___RWC QCSR_REG_RW +#define DBG_EVENT_MACEVENT_MATCH0_DATAH___POR 0x00000000 +#define DBG_EVENT_MACEVENT_MATCH0_DATAH__DATA_32___POR 0x0 +#define DBG_EVENT_MACEVENT_MATCH0_DATAH__DATA_32___M 0x00000001 +#define DBG_EVENT_MACEVENT_MATCH0_DATAH__DATA_32___S 0 +#define DBG_EVENT_MACEVENT_MATCH0_DATAH___M 0x00000001 +#define DBG_EVENT_MACEVENT_MATCH0_DATAH___S 0 + +#define DBG_EVENT_MACEVENT_MATCH0_MASK (0x00BB0010) +#define DBG_EVENT_MACEVENT_MATCH0_MASK___RWC QCSR_REG_RW +#define DBG_EVENT_MACEVENT_MATCH0_MASK___POR 0xFFFFFFFF +#define DBG_EVENT_MACEVENT_MATCH0_MASK__MASK___POR 0xFFFFFFFF +#define DBG_EVENT_MACEVENT_MATCH0_MASK__MASK___M 0xFFFFFFFF +#define DBG_EVENT_MACEVENT_MATCH0_MASK__MASK___S 0 +#define DBG_EVENT_MACEVENT_MATCH0_MASK___M 0xFFFFFFFF +#define DBG_EVENT_MACEVENT_MATCH0_MASK___S 0 + +#define DBG_EVENT_MACEVENT_MATCH0_MASKH (0x00BB0014) +#define DBG_EVENT_MACEVENT_MATCH0_MASKH___RWC QCSR_REG_RW +#define DBG_EVENT_MACEVENT_MATCH0_MASKH___POR 0x00000001 +#define DBG_EVENT_MACEVENT_MATCH0_MASKH__MASK_32___POR 0x1 +#define DBG_EVENT_MACEVENT_MATCH0_MASKH__MASK_32___M 0x00000001 +#define DBG_EVENT_MACEVENT_MATCH0_MASKH__MASK_32___S 0 +#define DBG_EVENT_MACEVENT_MATCH0_MASKH___M 0x00000001 +#define DBG_EVENT_MACEVENT_MATCH0_MASKH___S 0 + +#define DBG_EVENT_MACEVENT_MATCH1_DATA (0x00BB0018) +#define DBG_EVENT_MACEVENT_MATCH1_DATA___RWC QCSR_REG_RW +#define DBG_EVENT_MACEVENT_MATCH1_DATA___POR 0x00000000 +#define DBG_EVENT_MACEVENT_MATCH1_DATA__DATA___POR 0x00000000 +#define DBG_EVENT_MACEVENT_MATCH1_DATA__DATA___M 0xFFFFFFFF +#define DBG_EVENT_MACEVENT_MATCH1_DATA__DATA___S 0 +#define DBG_EVENT_MACEVENT_MATCH1_DATA___M 0xFFFFFFFF +#define DBG_EVENT_MACEVENT_MATCH1_DATA___S 0 + +#define DBG_EVENT_MACEVENT_MATCH1_DATAH (0x00BB001C) +#define DBG_EVENT_MACEVENT_MATCH1_DATAH___RWC QCSR_REG_RW +#define DBG_EVENT_MACEVENT_MATCH1_DATAH___POR 0x00000000 +#define DBG_EVENT_MACEVENT_MATCH1_DATAH__DATA_32___POR 0x0 +#define DBG_EVENT_MACEVENT_MATCH1_DATAH__DATA_32___M 0x00000001 +#define DBG_EVENT_MACEVENT_MATCH1_DATAH__DATA_32___S 0 +#define DBG_EVENT_MACEVENT_MATCH1_DATAH___M 0x00000001 +#define DBG_EVENT_MACEVENT_MATCH1_DATAH___S 0 + +#define DBG_EVENT_MACEVENT_MATCH1_MASK (0x00BB0020) +#define DBG_EVENT_MACEVENT_MATCH1_MASK___RWC QCSR_REG_RW +#define DBG_EVENT_MACEVENT_MATCH1_MASK___POR 0xFFFFFFFF +#define DBG_EVENT_MACEVENT_MATCH1_MASK__MASK___POR 0xFFFFFFFF +#define DBG_EVENT_MACEVENT_MATCH1_MASK__MASK___M 0xFFFFFFFF +#define DBG_EVENT_MACEVENT_MATCH1_MASK__MASK___S 0 +#define DBG_EVENT_MACEVENT_MATCH1_MASK___M 0xFFFFFFFF +#define DBG_EVENT_MACEVENT_MATCH1_MASK___S 0 + +#define DBG_EVENT_MACEVENT_MATCH1_MASKH (0x00BB0024) +#define DBG_EVENT_MACEVENT_MATCH1_MASKH___RWC QCSR_REG_RW +#define DBG_EVENT_MACEVENT_MATCH1_MASKH___POR 0x00000001 +#define DBG_EVENT_MACEVENT_MATCH1_MASKH__MASK_32___POR 0x1 +#define DBG_EVENT_MACEVENT_MATCH1_MASKH__MASK_32___M 0x00000001 +#define DBG_EVENT_MACEVENT_MATCH1_MASKH__MASK_32___S 0 +#define DBG_EVENT_MACEVENT_MATCH1_MASKH___M 0x00000001 +#define DBG_EVENT_MACEVENT_MATCH1_MASKH___S 0 + +#define DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK (0x00BB0028) +#define DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK___RWC QCSR_REG_RW +#define DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK___POR 0x0000000F +#define DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID3___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID2___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID1___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID0___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID3___M 0x00000008 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID3___S 3 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID3__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID3__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID2___M 0x00000004 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID2___S 2 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID2__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID2__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID1___M 0x00000002 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID1___S 1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID1__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID1__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID0___M 0x00000001 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID0___S 0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID0__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK__SSID0__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK___M 0x0000000F +#define DBG_EVENT_MACEVENT_FILTER_CFG0_SSID_MASK___S 0 + +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK (0x00BB002C) +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK___RWC QCSR_REG_RW +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK___POR 0x0000FFFF +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID15___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID14___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID13___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID12___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID11___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID10___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID9___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID8___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID7___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID6___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID5___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID4___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID3___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID2___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID1___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID0___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID15___M 0x00008000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID15___S 15 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID15__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID15__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID14___M 0x00004000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID14___S 14 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID14__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID14__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID13___M 0x00002000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID13___S 13 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID13__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID13__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID12___M 0x00001000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID12___S 12 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID12__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID12__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID11___M 0x00000800 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID11___S 11 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID11__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID11__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID10___M 0x00000400 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID10___S 10 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID10__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID10__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID9___M 0x00000200 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID9___S 9 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID9__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID9__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID8___M 0x00000100 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID8___S 8 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID8__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID8__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID7___M 0x00000080 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID7___S 7 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID7__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID7__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID6___M 0x00000040 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID6___S 6 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID6__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID6__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID5___M 0x00000020 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID5___S 5 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID5__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID5__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID4___M 0x00000010 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID4___S 4 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID4__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID4__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID3___M 0x00000008 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID3___S 3 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID3__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID3__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID2___M 0x00000004 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID2___S 2 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID2__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID2__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID1___M 0x00000002 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID1___S 1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID1__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID1__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID0___M 0x00000001 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID0___S 0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID0__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK__MODID0__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK___M 0x0000FFFF +#define DBG_EVENT_MACEVENT_FILTER_CFG0_MODID_MASK___S 0 + +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0 (0x00BB0030) +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0___RWC QCSR_REG_RW +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0___POR 0xFFFFFFFF +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID31___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID30___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID29___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID28___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID27___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID26___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID25___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID24___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID23___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID22___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID21___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID20___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID19___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID18___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID17___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID16___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID15___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID14___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID13___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID12___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID11___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID10___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID9___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID8___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID7___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID6___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID5___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID4___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID3___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID2___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID1___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID0___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID31___M 0x80000000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID31___S 31 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID31__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID31__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID30___M 0x40000000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID30___S 30 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID30__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID30__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID29___M 0x20000000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID29___S 29 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID29__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID29__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID28___M 0x10000000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID28___S 28 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID28__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID28__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID27___M 0x08000000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID27___S 27 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID27__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID27__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID26___M 0x04000000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID26___S 26 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID26__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID26__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID25___M 0x02000000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID25___S 25 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID25__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID25__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID24___M 0x01000000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID24___S 24 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID24__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID24__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID23___M 0x00800000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID23___S 23 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID23__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID23__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID22___M 0x00400000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID22___S 22 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID22__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID22__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID21___M 0x00200000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID21___S 21 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID21__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID21__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID20___M 0x00100000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID20___S 20 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID20__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID20__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID19___M 0x00080000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID19___S 19 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID19__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID19__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID18___M 0x00040000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID18___S 18 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID18__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID18__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID17___M 0x00020000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID17___S 17 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID17__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID17__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID16___M 0x00010000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID16___S 16 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID16__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID16__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID15___M 0x00008000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID15___S 15 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID15__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID15__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID14___M 0x00004000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID14___S 14 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID14__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID14__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID13___M 0x00002000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID13___S 13 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID13__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID13__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID12___M 0x00001000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID12___S 12 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID12__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID12__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID11___M 0x00000800 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID11___S 11 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID11__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID11__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID10___M 0x00000400 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID10___S 10 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID10__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID10__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID9___M 0x00000200 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID9___S 9 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID9__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID9__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID8___M 0x00000100 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID8___S 8 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID8__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID8__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID7___M 0x00000080 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID7___S 7 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID7__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID7__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID6___M 0x00000040 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID6___S 6 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID6__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID6__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID5___M 0x00000020 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID5___S 5 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID5__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID5__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID4___M 0x00000010 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID4___S 4 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID4__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID4__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID3___M 0x00000008 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID3___S 3 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID3__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID3__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID2___M 0x00000004 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID2___S 2 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID2__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID2__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID1___M 0x00000002 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID1___S 1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID1__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID1__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID0___M 0x00000001 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID0___S 0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID0__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0__EVENTID0__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0___M 0xFFFFFFFF +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK0___S 0 + +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1 (0x00BB0034) +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1___RWC QCSR_REG_RW +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1___POR 0xFFFFFFFF +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID63___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID62___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID61___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID60___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID59___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID58___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID57___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID56___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID55___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID54___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID53___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID52___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID51___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID50___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID49___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID48___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID47___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID46___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID45___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID44___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID43___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID42___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID41___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID40___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID39___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID38___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID37___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID36___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID35___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID34___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID33___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID32___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID63___M 0x80000000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID63___S 31 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID63__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID63__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID62___M 0x40000000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID62___S 30 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID62__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID62__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID61___M 0x20000000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID61___S 29 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID61__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID61__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID60___M 0x10000000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID60___S 28 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID60__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID60__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID59___M 0x08000000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID59___S 27 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID59__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID59__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID58___M 0x04000000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID58___S 26 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID58__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID58__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID57___M 0x02000000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID57___S 25 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID57__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID57__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID56___M 0x01000000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID56___S 24 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID56__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID56__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID55___M 0x00800000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID55___S 23 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID55__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID55__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID54___M 0x00400000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID54___S 22 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID54__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID54__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID53___M 0x00200000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID53___S 21 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID53__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID53__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID52___M 0x00100000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID52___S 20 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID52__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID52__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID51___M 0x00080000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID51___S 19 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID51__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID51__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID50___M 0x00040000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID50___S 18 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID50__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID50__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID49___M 0x00020000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID49___S 17 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID49__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID49__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID48___M 0x00010000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID48___S 16 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID48__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID48__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID47___M 0x00008000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID47___S 15 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID47__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID47__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID46___M 0x00004000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID46___S 14 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID46__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID46__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID45___M 0x00002000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID45___S 13 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID45__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID45__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID44___M 0x00001000 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID44___S 12 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID44__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID44__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID43___M 0x00000800 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID43___S 11 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID43__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID43__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID42___M 0x00000400 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID42___S 10 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID42__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID42__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID41___M 0x00000200 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID41___S 9 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID41__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID41__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID40___M 0x00000100 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID40___S 8 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID40__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID40__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID39___M 0x00000080 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID39___S 7 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID39__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID39__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID38___M 0x00000040 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID38___S 6 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID38__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID38__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID37___M 0x00000020 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID37___S 5 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID37__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID37__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID36___M 0x00000010 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID36___S 4 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID36__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID36__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID35___M 0x00000008 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID35___S 3 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID35__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID35__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID34___M 0x00000004 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID34___S 2 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID34__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID34__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID33___M 0x00000002 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID33___S 1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID33__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID33__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID32___M 0x00000001 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID32___S 0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID32__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1__EVENTID32__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1___M 0xFFFFFFFF +#define DBG_EVENT_MACEVENT_FILTER_CFG0_EVENTID_MASK1___S 0 + +#define DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK (0x00BB0038) +#define DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK___RWC QCSR_REG_RW +#define DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK___POR 0x0000000F +#define DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID3___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID2___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID1___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID0___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID3___M 0x00000008 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID3___S 3 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID3__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID3__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID2___M 0x00000004 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID2___S 2 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID2__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID2__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID1___M 0x00000002 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID1___S 1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID1__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID1__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID0___M 0x00000001 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID0___S 0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID0__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK__SSID0__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK___M 0x0000000F +#define DBG_EVENT_MACEVENT_FILTER_CFG1_SSID_MASK___S 0 + +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK (0x00BB003C) +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK___RWC QCSR_REG_RW +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK___POR 0x0000FFFF +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID15___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID14___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID13___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID12___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID11___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID10___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID9___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID8___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID7___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID6___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID5___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID4___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID3___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID2___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID1___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID0___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID15___M 0x00008000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID15___S 15 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID15__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID15__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID14___M 0x00004000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID14___S 14 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID14__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID14__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID13___M 0x00002000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID13___S 13 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID13__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID13__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID12___M 0x00001000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID12___S 12 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID12__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID12__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID11___M 0x00000800 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID11___S 11 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID11__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID11__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID10___M 0x00000400 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID10___S 10 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID10__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID10__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID9___M 0x00000200 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID9___S 9 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID9__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID9__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID8___M 0x00000100 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID8___S 8 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID8__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID8__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID7___M 0x00000080 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID7___S 7 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID7__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID7__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID6___M 0x00000040 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID6___S 6 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID6__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID6__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID5___M 0x00000020 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID5___S 5 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID5__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID5__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID4___M 0x00000010 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID4___S 4 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID4__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID4__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID3___M 0x00000008 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID3___S 3 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID3__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID3__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID2___M 0x00000004 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID2___S 2 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID2__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID2__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID1___M 0x00000002 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID1___S 1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID1__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID1__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID0___M 0x00000001 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID0___S 0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID0__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK__MODID0__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK___M 0x0000FFFF +#define DBG_EVENT_MACEVENT_FILTER_CFG1_MODID_MASK___S 0 + +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0 (0x00BB0040) +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0___RWC QCSR_REG_RW +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0___POR 0xFFFFFFFF +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID31___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID30___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID29___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID28___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID27___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID26___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID25___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID24___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID23___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID22___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID21___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID20___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID19___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID18___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID17___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID16___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID15___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID14___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID13___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID12___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID11___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID10___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID9___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID8___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID7___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID6___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID5___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID4___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID3___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID2___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID1___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID0___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID31___M 0x80000000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID31___S 31 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID31__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID31__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID30___M 0x40000000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID30___S 30 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID30__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID30__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID29___M 0x20000000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID29___S 29 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID29__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID29__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID28___M 0x10000000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID28___S 28 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID28__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID28__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID27___M 0x08000000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID27___S 27 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID27__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID27__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID26___M 0x04000000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID26___S 26 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID26__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID26__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID25___M 0x02000000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID25___S 25 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID25__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID25__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID24___M 0x01000000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID24___S 24 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID24__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID24__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID23___M 0x00800000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID23___S 23 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID23__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID23__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID22___M 0x00400000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID22___S 22 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID22__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID22__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID21___M 0x00200000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID21___S 21 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID21__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID21__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID20___M 0x00100000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID20___S 20 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID20__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID20__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID19___M 0x00080000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID19___S 19 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID19__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID19__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID18___M 0x00040000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID18___S 18 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID18__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID18__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID17___M 0x00020000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID17___S 17 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID17__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID17__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID16___M 0x00010000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID16___S 16 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID16__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID16__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID15___M 0x00008000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID15___S 15 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID15__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID15__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID14___M 0x00004000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID14___S 14 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID14__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID14__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID13___M 0x00002000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID13___S 13 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID13__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID13__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID12___M 0x00001000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID12___S 12 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID12__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID12__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID11___M 0x00000800 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID11___S 11 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID11__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID11__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID10___M 0x00000400 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID10___S 10 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID10__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID10__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID9___M 0x00000200 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID9___S 9 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID9__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID9__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID8___M 0x00000100 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID8___S 8 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID8__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID8__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID7___M 0x00000080 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID7___S 7 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID7__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID7__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID6___M 0x00000040 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID6___S 6 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID6__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID6__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID5___M 0x00000020 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID5___S 5 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID5__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID5__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID4___M 0x00000010 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID4___S 4 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID4__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID4__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID3___M 0x00000008 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID3___S 3 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID3__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID3__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID2___M 0x00000004 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID2___S 2 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID2__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID2__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID1___M 0x00000002 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID1___S 1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID1__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID1__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID0___M 0x00000001 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID0___S 0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID0__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0__EVENTID0__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0___M 0xFFFFFFFF +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK0___S 0 + +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1 (0x00BB0044) +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1___RWC QCSR_REG_RW +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1___POR 0xFFFFFFFF +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID63___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID62___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID61___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID60___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID59___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID58___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID57___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID56___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID55___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID54___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID53___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID52___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID51___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID50___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID49___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID48___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID47___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID46___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID45___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID44___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID43___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID42___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID41___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID40___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID39___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID38___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID37___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID36___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID35___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID34___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID33___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID32___POR 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID63___M 0x80000000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID63___S 31 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID63__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID63__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID62___M 0x40000000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID62___S 30 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID62__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID62__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID61___M 0x20000000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID61___S 29 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID61__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID61__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID60___M 0x10000000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID60___S 28 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID60__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID60__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID59___M 0x08000000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID59___S 27 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID59__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID59__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID58___M 0x04000000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID58___S 26 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID58__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID58__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID57___M 0x02000000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID57___S 25 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID57__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID57__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID56___M 0x01000000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID56___S 24 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID56__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID56__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID55___M 0x00800000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID55___S 23 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID55__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID55__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID54___M 0x00400000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID54___S 22 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID54__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID54__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID53___M 0x00200000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID53___S 21 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID53__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID53__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID52___M 0x00100000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID52___S 20 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID52__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID52__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID51___M 0x00080000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID51___S 19 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID51__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID51__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID50___M 0x00040000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID50___S 18 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID50__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID50__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID49___M 0x00020000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID49___S 17 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID49__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID49__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID48___M 0x00010000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID48___S 16 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID48__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID48__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID47___M 0x00008000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID47___S 15 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID47__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID47__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID46___M 0x00004000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID46___S 14 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID46__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID46__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID45___M 0x00002000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID45___S 13 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID45__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID45__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID44___M 0x00001000 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID44___S 12 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID44__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID44__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID43___M 0x00000800 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID43___S 11 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID43__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID43__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID42___M 0x00000400 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID42___S 10 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID42__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID42__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID41___M 0x00000200 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID41___S 9 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID41__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID41__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID40___M 0x00000100 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID40___S 8 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID40__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID40__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID39___M 0x00000080 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID39___S 7 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID39__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID39__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID38___M 0x00000040 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID38___S 6 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID38__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID38__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID37___M 0x00000020 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID37___S 5 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID37__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID37__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID36___M 0x00000010 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID36___S 4 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID36__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID36__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID35___M 0x00000008 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID35___S 3 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID35__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID35__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID34___M 0x00000004 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID34___S 2 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID34__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID34__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID33___M 0x00000002 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID33___S 1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID33__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID33__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID32___M 0x00000001 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID32___S 0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID32__DISABLE 0x0 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1__EVENTID32__ENABLE 0x1 +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1___M 0xFFFFFFFF +#define DBG_EVENT_MACEVENT_FILTER_CFG1_EVENTID_MASK1___S 0 + +#define DBG_EVENT_CS_ITCTL (0x00BB0F00) +#define DBG_EVENT_CS_ITCTL___RWC QCSR_REG_RO +#define DBG_EVENT_CS_ITCTL___POR 0x00000000 +#define DBG_EVENT_CS_ITCTL__RFU___POR 0x00000000 +#define DBG_EVENT_CS_ITCTL__RFU___M 0xFFFFFFFF +#define DBG_EVENT_CS_ITCTL__RFU___S 0 +#define DBG_EVENT_CS_ITCTL___M 0xFFFFFFFF +#define DBG_EVENT_CS_ITCTL___S 0 + +#define DBG_EVENT_CS_CLAIMSET (0x00BB0FA0) +#define DBG_EVENT_CS_CLAIMSET___RWC QCSR_REG_RO +#define DBG_EVENT_CS_CLAIMSET___POR 0x00000000 +#define DBG_EVENT_CS_CLAIMSET__RFU___POR 0x00000000 +#define DBG_EVENT_CS_CLAIMSET__RFU___M 0xFFFFFFFF +#define DBG_EVENT_CS_CLAIMSET__RFU___S 0 +#define DBG_EVENT_CS_CLAIMSET___M 0xFFFFFFFF +#define DBG_EVENT_CS_CLAIMSET___S 0 + +#define DBG_EVENT_CS_CLAIMCLR (0x00BB0FA4) +#define DBG_EVENT_CS_CLAIMCLR___RWC QCSR_REG_RO +#define DBG_EVENT_CS_CLAIMCLR___POR 0x00000000 +#define DBG_EVENT_CS_CLAIMCLR__RFU___POR 0x00000000 +#define DBG_EVENT_CS_CLAIMCLR__RFU___M 0xFFFFFFFF +#define DBG_EVENT_CS_CLAIMCLR__RFU___S 0 +#define DBG_EVENT_CS_CLAIMCLR___M 0xFFFFFFFF +#define DBG_EVENT_CS_CLAIMCLR___S 0 + +#define DBG_EVENT_CS_LOCKACCESS (0x00BB0FB0) +#define DBG_EVENT_CS_LOCKACCESS___RWC QCSR_REG_RO +#define DBG_EVENT_CS_LOCKACCESS___POR 0x00000000 +#define DBG_EVENT_CS_LOCKACCESS__RFU___POR 0x00000000 +#define DBG_EVENT_CS_LOCKACCESS__RFU___M 0xFFFFFFFF +#define DBG_EVENT_CS_LOCKACCESS__RFU___S 0 +#define DBG_EVENT_CS_LOCKACCESS___M 0xFFFFFFFF +#define DBG_EVENT_CS_LOCKACCESS___S 0 + +#define DBG_EVENT_CS_LOCKSTATUS (0x00BB0FB4) +#define DBG_EVENT_CS_LOCKSTATUS___RWC QCSR_REG_RO +#define DBG_EVENT_CS_LOCKSTATUS___POR 0x00000000 +#define DBG_EVENT_CS_LOCKSTATUS__RFU___POR 0x00000000 +#define DBG_EVENT_CS_LOCKSTATUS__RFU___M 0xFFFFFFFF +#define DBG_EVENT_CS_LOCKSTATUS__RFU___S 0 +#define DBG_EVENT_CS_LOCKSTATUS___M 0xFFFFFFFF +#define DBG_EVENT_CS_LOCKSTATUS___S 0 + +#define DBG_EVENT_CS_AUTHSTATUS (0x00BB0FB8) +#define DBG_EVENT_CS_AUTHSTATUS___RWC QCSR_REG_RO +#define DBG_EVENT_CS_AUTHSTATUS__SI___M 0x000000C0 +#define DBG_EVENT_CS_AUTHSTATUS__SI___S 6 +#define DBG_EVENT_CS_AUTHSTATUS__NSI___M 0x00000030 +#define DBG_EVENT_CS_AUTHSTATUS__NSI___S 4 +#define DBG_EVENT_CS_AUTHSTATUS__SNI___M 0x0000000C +#define DBG_EVENT_CS_AUTHSTATUS__SNI___S 2 +#define DBG_EVENT_CS_AUTHSTATUS__NSNI___M 0x00000003 +#define DBG_EVENT_CS_AUTHSTATUS__NSNI___S 0 +#define DBG_EVENT_CS_AUTHSTATUS___M 0x000000FF +#define DBG_EVENT_CS_AUTHSTATUS___S 0 + +#define DBG_EVENT_CS_DEVARCH (0x00BB0FBC) +#define DBG_EVENT_CS_DEVARCH___RWC QCSR_REG_RO +#define DBG_EVENT_CS_DEVARCH___POR 0x0E100000 +#define DBG_EVENT_CS_DEVARCH__JEP106_CONT_CODE___POR 0x0 +#define DBG_EVENT_CS_DEVARCH__JEP106_IDENT_CODE___POR 0x70 +#define DBG_EVENT_CS_DEVARCH__PRESENT___POR 0x1 +#define DBG_EVENT_CS_DEVARCH__REV___POR 0x0 +#define DBG_EVENT_CS_DEVARCH__ARCHID___POR 0x0000 +#define DBG_EVENT_CS_DEVARCH__JEP106_CONT_CODE___M 0xF0000000 +#define DBG_EVENT_CS_DEVARCH__JEP106_CONT_CODE___S 28 +#define DBG_EVENT_CS_DEVARCH__JEP106_IDENT_CODE___M 0x0FE00000 +#define DBG_EVENT_CS_DEVARCH__JEP106_IDENT_CODE___S 21 +#define DBG_EVENT_CS_DEVARCH__PRESENT___M 0x00100000 +#define DBG_EVENT_CS_DEVARCH__PRESENT___S 20 +#define DBG_EVENT_CS_DEVARCH__REV___M 0x000F0000 +#define DBG_EVENT_CS_DEVARCH__REV___S 16 +#define DBG_EVENT_CS_DEVARCH__ARCHID___M 0x0000FFFF +#define DBG_EVENT_CS_DEVARCH__ARCHID___S 0 +#define DBG_EVENT_CS_DEVARCH___M 0xFFFFFFFF +#define DBG_EVENT_CS_DEVARCH___S 0 + +#define DBG_EVENT_CS_DEVICEID (0x00BB0FC8) +#define DBG_EVENT_CS_DEVICEID___RWC QCSR_REG_RO +#define DBG_EVENT_CS_DEVICEID___POR 0x00000000 +#define DBG_EVENT_CS_DEVICEID__RFU___POR 0x000000 +#define DBG_EVENT_CS_DEVICEID__DEVID___POR 0x00 +#define DBG_EVENT_CS_DEVICEID__RFU___M 0xFFFFFF00 +#define DBG_EVENT_CS_DEVICEID__RFU___S 8 +#define DBG_EVENT_CS_DEVICEID__DEVID___M 0x000000FF +#define DBG_EVENT_CS_DEVICEID__DEVID___S 0 +#define DBG_EVENT_CS_DEVICEID___M 0xFFFFFFFF +#define DBG_EVENT_CS_DEVICEID___S 0 + +#define DBG_EVENT_CS_DEVICETYPE (0x00BB0FCC) +#define DBG_EVENT_CS_DEVICETYPE___RWC QCSR_REG_RO +#define DBG_EVENT_CS_DEVICETYPE___POR 0x00000003 +#define DBG_EVENT_CS_DEVICETYPE__RFU___POR 0x000000 +#define DBG_EVENT_CS_DEVICETYPE__SUBTYPE___POR 0x0 +#define DBG_EVENT_CS_DEVICETYPE__MAJTYPE___POR 0x3 +#define DBG_EVENT_CS_DEVICETYPE__RFU___M 0xFFFFFF00 +#define DBG_EVENT_CS_DEVICETYPE__RFU___S 8 +#define DBG_EVENT_CS_DEVICETYPE__SUBTYPE___M 0x000000F0 +#define DBG_EVENT_CS_DEVICETYPE__SUBTYPE___S 4 +#define DBG_EVENT_CS_DEVICETYPE__MAJTYPE___M 0x0000000F +#define DBG_EVENT_CS_DEVICETYPE__MAJTYPE___S 0 +#define DBG_EVENT_CS_DEVICETYPE___M 0xFFFFFFFF +#define DBG_EVENT_CS_DEVICETYPE___S 0 + +#define DBG_EVENT_CS_PERIPHID4 (0x00BB0FD0) +#define DBG_EVENT_CS_PERIPHID4___RWC QCSR_REG_RO +#define DBG_EVENT_CS_PERIPHID4___POR 0x00000000 +#define DBG_EVENT_CS_PERIPHID4__RFU___POR 0x000000 +#define DBG_EVENT_CS_PERIPHID4__FIELD_4KB_COUNT___POR 0x0 +#define DBG_EVENT_CS_PERIPHID4__JEP106_CONTINUATION___POR 0x0 +#define DBG_EVENT_CS_PERIPHID4__RFU___M 0xFFFFFF00 +#define DBG_EVENT_CS_PERIPHID4__RFU___S 8 +#define DBG_EVENT_CS_PERIPHID4__FIELD_4KB_COUNT___M 0x000000F0 +#define DBG_EVENT_CS_PERIPHID4__FIELD_4KB_COUNT___S 4 +#define DBG_EVENT_CS_PERIPHID4__JEP106_CONTINUATION___M 0x0000000F +#define DBG_EVENT_CS_PERIPHID4__JEP106_CONTINUATION___S 0 +#define DBG_EVENT_CS_PERIPHID4___M 0xFFFFFFFF +#define DBG_EVENT_CS_PERIPHID4___S 0 + +#define DBG_EVENT_CS_PERIPHID5 (0x00BB0FD4) +#define DBG_EVENT_CS_PERIPHID5___RWC QCSR_REG_RO +#define DBG_EVENT_CS_PERIPHID5___POR 0x00000000 +#define DBG_EVENT_CS_PERIPHID5__RFU___POR 0x00000000 +#define DBG_EVENT_CS_PERIPHID5__RFU___M 0xFFFFFFFF +#define DBG_EVENT_CS_PERIPHID5__RFU___S 0 +#define DBG_EVENT_CS_PERIPHID5___M 0xFFFFFFFF +#define DBG_EVENT_CS_PERIPHID5___S 0 + +#define DBG_EVENT_CS_PERIPHID6 (0x00BB0FD8) +#define DBG_EVENT_CS_PERIPHID6___RWC QCSR_REG_RO +#define DBG_EVENT_CS_PERIPHID6___POR 0x00000000 +#define DBG_EVENT_CS_PERIPHID6__RFU___POR 0x00000000 +#define DBG_EVENT_CS_PERIPHID6__RFU___M 0xFFFFFFFF +#define DBG_EVENT_CS_PERIPHID6__RFU___S 0 +#define DBG_EVENT_CS_PERIPHID6___M 0xFFFFFFFF +#define DBG_EVENT_CS_PERIPHID6___S 0 + +#define DBG_EVENT_CS_PERIPHID7 (0x00BB0FDC) +#define DBG_EVENT_CS_PERIPHID7___RWC QCSR_REG_RO +#define DBG_EVENT_CS_PERIPHID7___POR 0x00000000 +#define DBG_EVENT_CS_PERIPHID7__RFU___POR 0x00000000 +#define DBG_EVENT_CS_PERIPHID7__RFU___M 0xFFFFFFFF +#define DBG_EVENT_CS_PERIPHID7__RFU___S 0 +#define DBG_EVENT_CS_PERIPHID7___M 0xFFFFFFFF +#define DBG_EVENT_CS_PERIPHID7___S 0 + +#define DBG_EVENT_CS_PERIPHID0 (0x00BB0FE0) +#define DBG_EVENT_CS_PERIPHID0___RWC QCSR_REG_RO +#define DBG_EVENT_CS_PERIPHID0___POR 0x00000000 +#define DBG_EVENT_CS_PERIPHID0__RFU___POR 0x000000 +#define DBG_EVENT_CS_PERIPHID0__PARTNUM_7_0___POR 0x0 +#define DBG_EVENT_CS_PERIPHID0__RFU___M 0xFFFFFF00 +#define DBG_EVENT_CS_PERIPHID0__RFU___S 8 +#define DBG_EVENT_CS_PERIPHID0__PARTNUM_7_0___M 0x000000FF +#define DBG_EVENT_CS_PERIPHID0__PARTNUM_7_0___S 0 +#define DBG_EVENT_CS_PERIPHID0___M 0xFFFFFFFF +#define DBG_EVENT_CS_PERIPHID0___S 0 + +#define DBG_EVENT_CS_PERIPHID1 (0x00BB0FE4) +#define DBG_EVENT_CS_PERIPHID1___RWC QCSR_REG_RO +#define DBG_EVENT_CS_PERIPHID1___POR 0x00000000 +#define DBG_EVENT_CS_PERIPHID1__RFU___POR 0x000000 +#define DBG_EVENT_CS_PERIPHID1__JEP106_ID_3_0___POR 0x0 +#define DBG_EVENT_CS_PERIPHID1__PART_NUM_11_8___POR 0x0 +#define DBG_EVENT_CS_PERIPHID1__RFU___M 0xFFFFFF00 +#define DBG_EVENT_CS_PERIPHID1__RFU___S 8 +#define DBG_EVENT_CS_PERIPHID1__JEP106_ID_3_0___M 0x000000F0 +#define DBG_EVENT_CS_PERIPHID1__JEP106_ID_3_0___S 4 +#define DBG_EVENT_CS_PERIPHID1__PART_NUM_11_8___M 0x0000000F +#define DBG_EVENT_CS_PERIPHID1__PART_NUM_11_8___S 0 +#define DBG_EVENT_CS_PERIPHID1___M 0xFFFFFFFF +#define DBG_EVENT_CS_PERIPHID1___S 0 + +#define DBG_EVENT_CS_PERIPHID2 (0x00BB0FE8) +#define DBG_EVENT_CS_PERIPHID2___RWC QCSR_REG_RO +#define DBG_EVENT_CS_PERIPHID2___POR 0x0000000F +#define DBG_EVENT_CS_PERIPHID2__RFU___POR 0x000000 +#define DBG_EVENT_CS_PERIPHID2__PERIPH_REV___POR 0x0 +#define DBG_EVENT_CS_PERIPHID2__JEP106_ASS___POR 0x1 +#define DBG_EVENT_CS_PERIPHID2__JEP106_ID_6_4___POR 0x7 +#define DBG_EVENT_CS_PERIPHID2__RFU___M 0xFFFFFF00 +#define DBG_EVENT_CS_PERIPHID2__RFU___S 8 +#define DBG_EVENT_CS_PERIPHID2__PERIPH_REV___M 0x000000F0 +#define DBG_EVENT_CS_PERIPHID2__PERIPH_REV___S 4 +#define DBG_EVENT_CS_PERIPHID2__JEP106_ASS___M 0x00000008 +#define DBG_EVENT_CS_PERIPHID2__JEP106_ASS___S 3 +#define DBG_EVENT_CS_PERIPHID2__JEP106_ID_6_4___M 0x00000007 +#define DBG_EVENT_CS_PERIPHID2__JEP106_ID_6_4___S 0 +#define DBG_EVENT_CS_PERIPHID2___M 0xFFFFFFFF +#define DBG_EVENT_CS_PERIPHID2___S 0 + +#define DBG_EVENT_CS_PERIPHID3 (0x00BB0FEC) +#define DBG_EVENT_CS_PERIPHID3___RWC QCSR_REG_RO +#define DBG_EVENT_CS_PERIPHID3___POR 0x00000000 +#define DBG_EVENT_CS_PERIPHID3__RFU___POR 0x000000 +#define DBG_EVENT_CS_PERIPHID3__REV_AND___POR 0x0 +#define DBG_EVENT_CS_PERIPHID3__MODIFIED___POR 0x0 +#define DBG_EVENT_CS_PERIPHID3__RFU___M 0xFFFFFF00 +#define DBG_EVENT_CS_PERIPHID3__RFU___S 8 +#define DBG_EVENT_CS_PERIPHID3__REV_AND___M 0x000000F0 +#define DBG_EVENT_CS_PERIPHID3__REV_AND___S 4 +#define DBG_EVENT_CS_PERIPHID3__MODIFIED___M 0x0000000F +#define DBG_EVENT_CS_PERIPHID3__MODIFIED___S 0 +#define DBG_EVENT_CS_PERIPHID3___M 0xFFFFFFFF +#define DBG_EVENT_CS_PERIPHID3___S 0 + +#define DBG_EVENT_CS_COMPID0 (0x00BB0FF0) +#define DBG_EVENT_CS_COMPID0___RWC QCSR_REG_RO +#define DBG_EVENT_CS_COMPID0___POR 0x0000000D +#define DBG_EVENT_CS_COMPID0__RFU___POR 0x000000 +#define DBG_EVENT_CS_COMPID0__PREAMBLE_7_0___POR 0x0D +#define DBG_EVENT_CS_COMPID0__RFU___M 0xFFFFFF00 +#define DBG_EVENT_CS_COMPID0__RFU___S 8 +#define DBG_EVENT_CS_COMPID0__PREAMBLE_7_0___M 0x000000FF +#define DBG_EVENT_CS_COMPID0__PREAMBLE_7_0___S 0 +#define DBG_EVENT_CS_COMPID0___M 0xFFFFFFFF +#define DBG_EVENT_CS_COMPID0___S 0 + +#define DBG_EVENT_CS_COMPID1 (0x00BB0FF4) +#define DBG_EVENT_CS_COMPID1___RWC QCSR_REG_RO +#define DBG_EVENT_CS_COMPID1___POR 0x00000090 +#define DBG_EVENT_CS_COMPID1__RFU___POR 0x000000 +#define DBG_EVENT_CS_COMPID1__PREAMBLE_15_12___POR 0x9 +#define DBG_EVENT_CS_COMPID1__PREAMBLE_11_8___POR 0x0 +#define DBG_EVENT_CS_COMPID1__RFU___M 0xFFFFFF00 +#define DBG_EVENT_CS_COMPID1__RFU___S 8 +#define DBG_EVENT_CS_COMPID1__PREAMBLE_15_12___M 0x000000F0 +#define DBG_EVENT_CS_COMPID1__PREAMBLE_15_12___S 4 +#define DBG_EVENT_CS_COMPID1__PREAMBLE_11_8___M 0x0000000F +#define DBG_EVENT_CS_COMPID1__PREAMBLE_11_8___S 0 +#define DBG_EVENT_CS_COMPID1___M 0xFFFFFFFF +#define DBG_EVENT_CS_COMPID1___S 0 + +#define DBG_EVENT_CS_COMPID2 (0x00BB0FF8) +#define DBG_EVENT_CS_COMPID2___RWC QCSR_REG_RO +#define DBG_EVENT_CS_COMPID2___POR 0x00000005 +#define DBG_EVENT_CS_COMPID2__RFU___POR 0x000000 +#define DBG_EVENT_CS_COMPID2__PREAMBLE_23_16___POR 0x05 +#define DBG_EVENT_CS_COMPID2__RFU___M 0xFFFFFF00 +#define DBG_EVENT_CS_COMPID2__RFU___S 8 +#define DBG_EVENT_CS_COMPID2__PREAMBLE_23_16___M 0x000000FF +#define DBG_EVENT_CS_COMPID2__PREAMBLE_23_16___S 0 +#define DBG_EVENT_CS_COMPID2___M 0xFFFFFFFF +#define DBG_EVENT_CS_COMPID2___S 0 + +#define DBG_EVENT_CS_COMPID3 (0x00BB0FFC) +#define DBG_EVENT_CS_COMPID3___RWC QCSR_REG_RO +#define DBG_EVENT_CS_COMPID3___POR 0x000000B1 +#define DBG_EVENT_CS_COMPID3__RFU___POR 0x000000 +#define DBG_EVENT_CS_COMPID3__PREAMBLE_31_24___POR 0xB1 +#define DBG_EVENT_CS_COMPID3__RFU___M 0xFFFFFF00 +#define DBG_EVENT_CS_COMPID3__RFU___S 8 +#define DBG_EVENT_CS_COMPID3__PREAMBLE_31_24___M 0x000000FF +#define DBG_EVENT_CS_COMPID3__PREAMBLE_31_24___S 0 +#define DBG_EVENT_CS_COMPID3___M 0xFFFFFFFF +#define DBG_EVENT_CS_COMPID3___S 0 + +#define DBG_EVENTFUN_CTRL_REG (0x00BB1000) +#define DBG_EVENTFUN_CTRL_REG___RWC QCSR_REG_RW +#define DBG_EVENTFUN_CTRL_REG___POR 0x00000300 +#define DBG_EVENTFUN_CTRL_REG__HT___POR 0x3 +#define DBG_EVENTFUN_CTRL_REG__ENS7___POR 0x0 +#define DBG_EVENTFUN_CTRL_REG__ENS6___POR 0x0 +#define DBG_EVENTFUN_CTRL_REG__ENS5___POR 0x0 +#define DBG_EVENTFUN_CTRL_REG__ENS4___POR 0x0 +#define DBG_EVENTFUN_CTRL_REG__ENS3___POR 0x0 +#define DBG_EVENTFUN_CTRL_REG__ENS2___POR 0x0 +#define DBG_EVENTFUN_CTRL_REG__ENS1___POR 0x0 +#define DBG_EVENTFUN_CTRL_REG__ENS0___POR 0x0 +#define DBG_EVENTFUN_CTRL_REG__HT___M 0x00000F00 +#define DBG_EVENTFUN_CTRL_REG__HT___S 8 +#define DBG_EVENTFUN_CTRL_REG__HT__HT_0X0 0x0 +#define DBG_EVENTFUN_CTRL_REG__HT__HT_0X1 0x1 +#define DBG_EVENTFUN_CTRL_REG__HT__HT_0X2 0x2 +#define DBG_EVENTFUN_CTRL_REG__HT__HT_0X3 0x3 +#define DBG_EVENTFUN_CTRL_REG__HT__HT_0X4 0x4 +#define DBG_EVENTFUN_CTRL_REG__HT__HT_0X5 0x5 +#define DBG_EVENTFUN_CTRL_REG__HT__HT_0X6 0x6 +#define DBG_EVENTFUN_CTRL_REG__HT__HT_0X7 0x7 +#define DBG_EVENTFUN_CTRL_REG__HT__HT_0X8 0x8 +#define DBG_EVENTFUN_CTRL_REG__HT__HT_0X9 0x9 +#define DBG_EVENTFUN_CTRL_REG__HT__HT_0XA 0xA +#define DBG_EVENTFUN_CTRL_REG__HT__HT_0XB 0xB +#define DBG_EVENTFUN_CTRL_REG__HT__HT_0XC 0xC +#define DBG_EVENTFUN_CTRL_REG__HT__HT_0XD 0xD +#define DBG_EVENTFUN_CTRL_REG__HT__HT_0XE 0xE +#define DBG_EVENTFUN_CTRL_REG__ENS7___M 0x00000080 +#define DBG_EVENTFUN_CTRL_REG__ENS7___S 7 +#define DBG_EVENTFUN_CTRL_REG__ENS7__ENS7_0 0x0 +#define DBG_EVENTFUN_CTRL_REG__ENS7__ENS7_1 0x1 +#define DBG_EVENTFUN_CTRL_REG__ENS6___M 0x00000040 +#define DBG_EVENTFUN_CTRL_REG__ENS6___S 6 +#define DBG_EVENTFUN_CTRL_REG__ENS6__ENS6_0 0x0 +#define DBG_EVENTFUN_CTRL_REG__ENS6__ENS6_1 0x1 +#define DBG_EVENTFUN_CTRL_REG__ENS5___M 0x00000020 +#define DBG_EVENTFUN_CTRL_REG__ENS5___S 5 +#define DBG_EVENTFUN_CTRL_REG__ENS5__ENS5_0 0x0 +#define DBG_EVENTFUN_CTRL_REG__ENS5__ENS5_1 0x1 +#define DBG_EVENTFUN_CTRL_REG__ENS4___M 0x00000010 +#define DBG_EVENTFUN_CTRL_REG__ENS4___S 4 +#define DBG_EVENTFUN_CTRL_REG__ENS4__ENS4_0 0x0 +#define DBG_EVENTFUN_CTRL_REG__ENS4__ENS4_1 0x1 +#define DBG_EVENTFUN_CTRL_REG__ENS3___M 0x00000008 +#define DBG_EVENTFUN_CTRL_REG__ENS3___S 3 +#define DBG_EVENTFUN_CTRL_REG__ENS3__ENS3_0 0x0 +#define DBG_EVENTFUN_CTRL_REG__ENS3__ENS3_1 0x1 +#define DBG_EVENTFUN_CTRL_REG__ENS2___M 0x00000004 +#define DBG_EVENTFUN_CTRL_REG__ENS2___S 2 +#define DBG_EVENTFUN_CTRL_REG__ENS2__ENS2_0 0x0 +#define DBG_EVENTFUN_CTRL_REG__ENS2__ENS2_1 0x1 +#define DBG_EVENTFUN_CTRL_REG__ENS1___M 0x00000002 +#define DBG_EVENTFUN_CTRL_REG__ENS1___S 1 +#define DBG_EVENTFUN_CTRL_REG__ENS1__ENS1_0 0x0 +#define DBG_EVENTFUN_CTRL_REG__ENS1__ENS1_1 0x1 +#define DBG_EVENTFUN_CTRL_REG__ENS0___M 0x00000001 +#define DBG_EVENTFUN_CTRL_REG__ENS0___S 0 +#define DBG_EVENTFUN_CTRL_REG__ENS0__ENS0_0 0x0 +#define DBG_EVENTFUN_CTRL_REG__ENS0__ENS0_1 0x1 +#define DBG_EVENTFUN_CTRL_REG___M 0x00000FFF +#define DBG_EVENTFUN_CTRL_REG___S 0 + +#define DBG_EVENTFUN_PRIORITY_CTRL_REG (0x00BB1004) +#define DBG_EVENTFUN_PRIORITY_CTRL_REG___RWC QCSR_REG_RW +#define DBG_EVENTFUN_PRIORITY_CTRL_REG___POR 0x00000000 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT7___POR 0x0 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT6___POR 0x0 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT5___POR 0x0 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT4___POR 0x0 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT3___POR 0x0 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT2___POR 0x0 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT1___POR 0x0 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT0___POR 0x0 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT7___M 0x00E00000 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT7___S 21 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_0 0x0 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_1 0x1 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_2 0x2 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_3 0x3 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_4 0x4 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_5 0x5 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_6 0x6 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_7 0x7 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT6___M 0x001C0000 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT6___S 18 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_0 0x0 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_1 0x1 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_2 0x2 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_3 0x3 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_4 0x4 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_5 0x5 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_6 0x6 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_7 0x7 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT5___M 0x00038000 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT5___S 15 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_0 0x0 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_1 0x1 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_2 0x2 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_3 0x3 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_4 0x4 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_5 0x5 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_6 0x6 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_7 0x7 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT4___M 0x00007000 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT4___S 12 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_0 0x0 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_1 0x1 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_2 0x2 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_3 0x3 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_4 0x4 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_5 0x5 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_6 0x6 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_7 0x7 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT3___M 0x00000E00 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT3___S 9 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_0 0x0 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_1 0x1 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_2 0x2 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_3 0x3 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_4 0x4 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_5 0x5 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_6 0x6 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_7 0x7 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT2___M 0x000001C0 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT2___S 6 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_0 0x0 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_1 0x1 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_2 0x2 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_3 0x3 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_4 0x4 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_5 0x5 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_6 0x6 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_7 0x7 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT1___M 0x00000038 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT1___S 3 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_0 0x0 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_1 0x1 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_2 0x2 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_3 0x3 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_4 0x4 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_5 0x5 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_6 0x6 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_7 0x7 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT0___M 0x00000007 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT0___S 0 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_0 0x0 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_1 0x1 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_2 0x2 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_3 0x3 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_4 0x4 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_5 0x5 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_6 0x6 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_7 0x7 +#define DBG_EVENTFUN_PRIORITY_CTRL_REG___M 0x00FFFFFF +#define DBG_EVENTFUN_PRIORITY_CTRL_REG___S 0 + +#define DBG_EVENTFUN_ITATBDATA0 (0x00BB1EEC) +#define DBG_EVENTFUN_ITATBDATA0___RWC QCSR_REG_RW +#define DBG_EVENTFUN_ITATBDATA0___POR 0x00000000 +#define DBG_EVENTFUN_ITATBDATA0__ATDATA31___POR 0x0 +#define DBG_EVENTFUN_ITATBDATA0__ATDATAM23___POR 0x0 +#define DBG_EVENTFUN_ITATBDATA0__ATDATA15___POR 0x0 +#define DBG_EVENTFUN_ITATBDATA0__ATDATA7___POR 0x0 +#define DBG_EVENTFUN_ITATBDATA0__ATDATA0___POR 0x0 +#define DBG_EVENTFUN_ITATBDATA0__ATDATA31___M 0x00000010 +#define DBG_EVENTFUN_ITATBDATA0__ATDATA31___S 4 +#define DBG_EVENTFUN_ITATBDATA0__ATDATA31__ATDATA31_0 0x0 +#define DBG_EVENTFUN_ITATBDATA0__ATDATA31__ATDATA31_1 0x1 +#define DBG_EVENTFUN_ITATBDATA0__ATDATAM23___M 0x00000008 +#define DBG_EVENTFUN_ITATBDATA0__ATDATAM23___S 3 +#define DBG_EVENTFUN_ITATBDATA0__ATDATAM23__ATDATAM23_0 0x0 +#define DBG_EVENTFUN_ITATBDATA0__ATDATAM23__ATDATAM23_1 0x1 +#define DBG_EVENTFUN_ITATBDATA0__ATDATA15___M 0x00000004 +#define DBG_EVENTFUN_ITATBDATA0__ATDATA15___S 2 +#define DBG_EVENTFUN_ITATBDATA0__ATDATA15__ATDATA15_0 0x0 +#define DBG_EVENTFUN_ITATBDATA0__ATDATA15__ATDATA15_1 0x1 +#define DBG_EVENTFUN_ITATBDATA0__ATDATA7___M 0x00000002 +#define DBG_EVENTFUN_ITATBDATA0__ATDATA7___S 1 +#define DBG_EVENTFUN_ITATBDATA0__ATDATA7__ATDATA7_0 0x0 +#define DBG_EVENTFUN_ITATBDATA0__ATDATA7__ATDATA7_1 0x1 +#define DBG_EVENTFUN_ITATBDATA0__ATDATA0___M 0x00000001 +#define DBG_EVENTFUN_ITATBDATA0__ATDATA0___S 0 +#define DBG_EVENTFUN_ITATBDATA0__ATDATA0__ATDATA0_0 0x0 +#define DBG_EVENTFUN_ITATBDATA0__ATDATA0__ATDATA0_1 0x1 +#define DBG_EVENTFUN_ITATBDATA0___M 0x0000001F +#define DBG_EVENTFUN_ITATBDATA0___S 0 + +#define DBG_EVENTFUN_ITATBCTR2 (0x00BB1EF0) +#define DBG_EVENTFUN_ITATBCTR2___RWC QCSR_REG_RW +#define DBG_EVENTFUN_ITATBCTR2___POR 0x00000000 +#define DBG_EVENTFUN_ITATBCTR2__AFVALID___POR 0x0 +#define DBG_EVENTFUN_ITATBCTR2__ATREADY___POR 0x0 +#define DBG_EVENTFUN_ITATBCTR2__AFVALID___M 0x00000002 +#define DBG_EVENTFUN_ITATBCTR2__AFVALID___S 1 +#define DBG_EVENTFUN_ITATBCTR2__AFVALID__AFVALID_0 0x0 +#define DBG_EVENTFUN_ITATBCTR2__AFVALID__AFVALID_1 0x1 +#define DBG_EVENTFUN_ITATBCTR2__ATREADY___M 0x00000001 +#define DBG_EVENTFUN_ITATBCTR2__ATREADY___S 0 +#define DBG_EVENTFUN_ITATBCTR2__ATREADY__ATREADY_0 0x0 +#define DBG_EVENTFUN_ITATBCTR2__ATREADY__ATREADY_1 0x1 +#define DBG_EVENTFUN_ITATBCTR2___M 0x00000003 +#define DBG_EVENTFUN_ITATBCTR2___S 0 + +#define DBG_EVENTFUN_ITATBCTR1 (0x00BB1EF4) +#define DBG_EVENTFUN_ITATBCTR1___RWC QCSR_REG_RW +#define DBG_EVENTFUN_ITATBCTR1__ATID___M 0x0000007F +#define DBG_EVENTFUN_ITATBCTR1__ATID___S 0 +#define DBG_EVENTFUN_ITATBCTR1___M 0x0000007F +#define DBG_EVENTFUN_ITATBCTR1___S 0 + +#define DBG_EVENTFUN_ITATBCTR0 (0x00BB1EF8) +#define DBG_EVENTFUN_ITATBCTR0___RWC QCSR_REG_RW +#define DBG_EVENTFUN_ITATBCTR0___POR 0x00000000 +#define DBG_EVENTFUN_ITATBCTR0__ATBYTES___POR 0x0 +#define DBG_EVENTFUN_ITATBCTR0__AFREADY___POR 0x0 +#define DBG_EVENTFUN_ITATBCTR0__ATVALID___POR 0x0 +#define DBG_EVENTFUN_ITATBCTR0__ATBYTES___M 0x00000300 +#define DBG_EVENTFUN_ITATBCTR0__ATBYTES___S 8 +#define DBG_EVENTFUN_ITATBCTR0__ATBYTES__ATBYTES_0 0x0 +#define DBG_EVENTFUN_ITATBCTR0__ATBYTES__ATBYTES_1 0x1 +#define DBG_EVENTFUN_ITATBCTR0__AFREADY___M 0x00000002 +#define DBG_EVENTFUN_ITATBCTR0__AFREADY___S 1 +#define DBG_EVENTFUN_ITATBCTR0__AFREADY__AFREADY_0 0x0 +#define DBG_EVENTFUN_ITATBCTR0__AFREADY__AFREADY_1 0x1 +#define DBG_EVENTFUN_ITATBCTR0__ATVALID___M 0x00000001 +#define DBG_EVENTFUN_ITATBCTR0__ATVALID___S 0 +#define DBG_EVENTFUN_ITATBCTR0__ATVALID__ATVALID_0 0x0 +#define DBG_EVENTFUN_ITATBCTR0__ATVALID__ATVALID_1 0x1 +#define DBG_EVENTFUN_ITATBCTR0___M 0x00000303 +#define DBG_EVENTFUN_ITATBCTR0___S 0 + +#define DBG_EVENTFUN_ITCTRL (0x00BB1F00) +#define DBG_EVENTFUN_ITCTRL___RWC QCSR_REG_RW +#define DBG_EVENTFUN_ITCTRL___POR 0x00000000 +#define DBG_EVENTFUN_ITCTRL__INTEGRATION_MODE___POR 0x0 +#define DBG_EVENTFUN_ITCTRL__INTEGRATION_MODE___M 0x00000001 +#define DBG_EVENTFUN_ITCTRL__INTEGRATION_MODE___S 0 +#define DBG_EVENTFUN_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE_0 0x0 +#define DBG_EVENTFUN_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE_1 0x1 +#define DBG_EVENTFUN_ITCTRL___M 0x00000001 +#define DBG_EVENTFUN_ITCTRL___S 0 + +#define DBG_EVENTFUN_CLAIMSET (0x00BB1FA0) +#define DBG_EVENTFUN_CLAIMSET___RWC QCSR_REG_RW +#define DBG_EVENTFUN_CLAIMSET___POR 0x0000000F +#define DBG_EVENTFUN_CLAIMSET__CLAIMSET___POR 0xF +#define DBG_EVENTFUN_CLAIMSET__CLAIMSET___M 0x0000000F +#define DBG_EVENTFUN_CLAIMSET__CLAIMSET___S 0 +#define DBG_EVENTFUN_CLAIMSET__CLAIMSET__CLAIMSET_0XF 0xF +#define DBG_EVENTFUN_CLAIMSET___M 0x0000000F +#define DBG_EVENTFUN_CLAIMSET___S 0 + +#define DBG_EVENTFUN_CLAIMCLR (0x00BB1FA4) +#define DBG_EVENTFUN_CLAIMCLR___RWC QCSR_REG_RW +#define DBG_EVENTFUN_CLAIMCLR___POR 0x00000000 +#define DBG_EVENTFUN_CLAIMCLR__CLAIMCLR___POR 0x0 +#define DBG_EVENTFUN_CLAIMCLR__CLAIMCLR___M 0x0000000F +#define DBG_EVENTFUN_CLAIMCLR__CLAIMCLR___S 0 +#define DBG_EVENTFUN_CLAIMCLR___M 0x0000000F +#define DBG_EVENTFUN_CLAIMCLR___S 0 + +#define DBG_EVENTFUN_LOCKACCESS (0x00BB1FB0) +#define DBG_EVENTFUN_LOCKACCESS___RWC QCSR_REG_WO +#define DBG_EVENTFUN_LOCKACCESS__KEY___M 0xFFFFFFFF +#define DBG_EVENTFUN_LOCKACCESS__KEY___S 0 +#define DBG_EVENTFUN_LOCKACCESS__KEY__KEY_0XC5ACCE55 0xC5ACCE55 +#define DBG_EVENTFUN_LOCKACCESS__KEY__KEY_0XDEADBEEF 0xDEADBEEF +#define DBG_EVENTFUN_LOCKACCESS___M 0xFFFFFFFF +#define DBG_EVENTFUN_LOCKACCESS___S 0 + +#define DBG_EVENTFUN_LOCKSTATUS (0x00BB1FB4) +#define DBG_EVENTFUN_LOCKSTATUS___RWC QCSR_REG_RO +#define DBG_EVENTFUN_LOCKSTATUS___POR 0x00000003 +#define DBG_EVENTFUN_LOCKSTATUS__NTT___POR 0x0 +#define DBG_EVENTFUN_LOCKSTATUS__SLK___POR 0x1 +#define DBG_EVENTFUN_LOCKSTATUS__SLI___POR 0x1 +#define DBG_EVENTFUN_LOCKSTATUS__NTT___M 0x00000004 +#define DBG_EVENTFUN_LOCKSTATUS__NTT___S 2 +#define DBG_EVENTFUN_LOCKSTATUS__NTT__NTT_0X0 0x0 +#define DBG_EVENTFUN_LOCKSTATUS__SLK___M 0x00000002 +#define DBG_EVENTFUN_LOCKSTATUS__SLK___S 1 +#define DBG_EVENTFUN_LOCKSTATUS__SLK__SLK_0X0 0x0 +#define DBG_EVENTFUN_LOCKSTATUS__SLK__SLK_0X1 0x1 +#define DBG_EVENTFUN_LOCKSTATUS__SLI___M 0x00000001 +#define DBG_EVENTFUN_LOCKSTATUS__SLI___S 0 +#define DBG_EVENTFUN_LOCKSTATUS__SLI__SLI_0X0 0x0 +#define DBG_EVENTFUN_LOCKSTATUS__SLI__SLI_0X1 0x1 +#define DBG_EVENTFUN_LOCKSTATUS___M 0x00000007 +#define DBG_EVENTFUN_LOCKSTATUS___S 0 + +#define DBG_EVENTFUN_AUTHSTATUS (0x00BB1FB8) +#define DBG_EVENTFUN_AUTHSTATUS___RWC QCSR_REG_RO +#define DBG_EVENTFUN_AUTHSTATUS___POR 0x00000000 +#define DBG_EVENTFUN_AUTHSTATUS__SNID___POR 0x0 +#define DBG_EVENTFUN_AUTHSTATUS__SID___POR 0x0 +#define DBG_EVENTFUN_AUTHSTATUS__NSNID___POR 0x0 +#define DBG_EVENTFUN_AUTHSTATUS__NSID___POR 0x0 +#define DBG_EVENTFUN_AUTHSTATUS__SNID___M 0x000000C0 +#define DBG_EVENTFUN_AUTHSTATUS__SNID___S 6 +#define DBG_EVENTFUN_AUTHSTATUS__SNID__SNID_0X0 0x0 +#define DBG_EVENTFUN_AUTHSTATUS__SID___M 0x00000030 +#define DBG_EVENTFUN_AUTHSTATUS__SID___S 4 +#define DBG_EVENTFUN_AUTHSTATUS__SID__SID_0X0 0x0 +#define DBG_EVENTFUN_AUTHSTATUS__NSNID___M 0x0000000C +#define DBG_EVENTFUN_AUTHSTATUS__NSNID___S 2 +#define DBG_EVENTFUN_AUTHSTATUS__NSNID__NSNID_0X0 0x0 +#define DBG_EVENTFUN_AUTHSTATUS__NSID___M 0x00000003 +#define DBG_EVENTFUN_AUTHSTATUS__NSID___S 0 +#define DBG_EVENTFUN_AUTHSTATUS__NSID__NSID_0X0 0x0 +#define DBG_EVENTFUN_AUTHSTATUS___M 0x000000FF +#define DBG_EVENTFUN_AUTHSTATUS___S 0 + +#define DBG_EVENTFUN_DEVID (0x00BB1FC8) +#define DBG_EVENTFUN_DEVID___RWC QCSR_REG_RO +#define DBG_EVENTFUN_DEVID___POR 0x00000038 +#define DBG_EVENTFUN_DEVID__SCHEME___POR 0x3 +#define DBG_EVENTFUN_DEVID__PORTCOUNT___POR 0x8 +#define DBG_EVENTFUN_DEVID__SCHEME___M 0x000000F0 +#define DBG_EVENTFUN_DEVID__SCHEME___S 4 +#define DBG_EVENTFUN_DEVID__SCHEME__SCHEME_0X3 0x3 +#define DBG_EVENTFUN_DEVID__PORTCOUNT___M 0x0000000F +#define DBG_EVENTFUN_DEVID__PORTCOUNT___S 0 +#define DBG_EVENTFUN_DEVID__PORTCOUNT__PORTCOUNT_0X2 0x2 +#define DBG_EVENTFUN_DEVID__PORTCOUNT__PORTCOUNT_0X3 0x3 +#define DBG_EVENTFUN_DEVID__PORTCOUNT__PORTCOUNT_0X4 0x4 +#define DBG_EVENTFUN_DEVID__PORTCOUNT__PORTCOUNT_0X5 0x5 +#define DBG_EVENTFUN_DEVID__PORTCOUNT__PORTCOUNT_0X6 0x6 +#define DBG_EVENTFUN_DEVID__PORTCOUNT__PORTCOUNT_0X7 0x7 +#define DBG_EVENTFUN_DEVID__PORTCOUNT__PORTCOUNT_0X8 0x8 +#define DBG_EVENTFUN_DEVID___M 0x000000FF +#define DBG_EVENTFUN_DEVID___S 0 + +#define DBG_EVENTFUN_DEVTYPE (0x00BB1FCC) +#define DBG_EVENTFUN_DEVTYPE___RWC QCSR_REG_RO +#define DBG_EVENTFUN_DEVTYPE___POR 0x00000012 +#define DBG_EVENTFUN_DEVTYPE__SUB_TYPE___POR 0x1 +#define DBG_EVENTFUN_DEVTYPE__MAJOR_TYPE___POR 0x2 +#define DBG_EVENTFUN_DEVTYPE__SUB_TYPE___M 0x000000F0 +#define DBG_EVENTFUN_DEVTYPE__SUB_TYPE___S 4 +#define DBG_EVENTFUN_DEVTYPE__SUB_TYPE__SUB_TYPE_0X1 0x1 +#define DBG_EVENTFUN_DEVTYPE__MAJOR_TYPE___M 0x0000000F +#define DBG_EVENTFUN_DEVTYPE__MAJOR_TYPE___S 0 +#define DBG_EVENTFUN_DEVTYPE__MAJOR_TYPE__MAJOR_TYPE_0X2 0x2 +#define DBG_EVENTFUN_DEVTYPE___M 0x000000FF +#define DBG_EVENTFUN_DEVTYPE___S 0 + +#define DBG_EVENTFUN_PIDR0 (0x00BB1FE0) +#define DBG_EVENTFUN_PIDR0___RWC QCSR_REG_RO +#define DBG_EVENTFUN_PIDR0___POR 0x00000008 +#define DBG_EVENTFUN_PIDR0__PART_NUMBER_BITS7TO0___POR 0x08 +#define DBG_EVENTFUN_PIDR0__PART_NUMBER_BITS7TO0___M 0x000000FF +#define DBG_EVENTFUN_PIDR0__PART_NUMBER_BITS7TO0___S 0 +#define DBG_EVENTFUN_PIDR0__PART_NUMBER_BITS7TO0__PART_NUMBER_BITS7TO0_0X08 0x08 +#define DBG_EVENTFUN_PIDR0___M 0x000000FF +#define DBG_EVENTFUN_PIDR0___S 0 + +#define DBG_EVENTFUN_PIDR1 (0x00BB1FE4) +#define DBG_EVENTFUN_PIDR1___RWC QCSR_REG_RO +#define DBG_EVENTFUN_PIDR1___POR 0x000000B9 +#define DBG_EVENTFUN_PIDR1__JEP106_BITS3TO0___POR 0xB +#define DBG_EVENTFUN_PIDR1__PART_NUMBER_BITS11TO8___POR 0x9 +#define DBG_EVENTFUN_PIDR1__JEP106_BITS3TO0___M 0x000000F0 +#define DBG_EVENTFUN_PIDR1__JEP106_BITS3TO0___S 4 +#define DBG_EVENTFUN_PIDR1__JEP106_BITS3TO0__JEP106_BITS3TO0_0XB 0xB +#define DBG_EVENTFUN_PIDR1__PART_NUMBER_BITS11TO8___M 0x0000000F +#define DBG_EVENTFUN_PIDR1__PART_NUMBER_BITS11TO8___S 0 +#define DBG_EVENTFUN_PIDR1__PART_NUMBER_BITS11TO8__PART_NUMBER_BITS11TO8_0X9 0x9 +#define DBG_EVENTFUN_PIDR1___M 0x000000FF +#define DBG_EVENTFUN_PIDR1___S 0 + +#define DBG_EVENTFUN_PIDR2 (0x00BB1FE8) +#define DBG_EVENTFUN_PIDR2___RWC QCSR_REG_RO +#define DBG_EVENTFUN_PIDR2___POR 0x0000003B +#define DBG_EVENTFUN_PIDR2__REVISION___POR 0x3 +#define DBG_EVENTFUN_PIDR2__JEDEC___POR 0x1 +#define DBG_EVENTFUN_PIDR2__JEP106_BITS6TO4___POR 0x3 +#define DBG_EVENTFUN_PIDR2__REVISION___M 0x000000F0 +#define DBG_EVENTFUN_PIDR2__REVISION___S 4 +#define DBG_EVENTFUN_PIDR2__REVISION__REVISION_0X3 0x3 +#define DBG_EVENTFUN_PIDR2__JEDEC___M 0x00000008 +#define DBG_EVENTFUN_PIDR2__JEDEC___S 3 +#define DBG_EVENTFUN_PIDR2__JEDEC__JEDEC_0X1 0x1 +#define DBG_EVENTFUN_PIDR2__JEP106_BITS6TO4___M 0x00000007 +#define DBG_EVENTFUN_PIDR2__JEP106_BITS6TO4___S 0 +#define DBG_EVENTFUN_PIDR2__JEP106_BITS6TO4__JEP106_BITS6TO4_0X3 0x3 +#define DBG_EVENTFUN_PIDR2___M 0x000000FF +#define DBG_EVENTFUN_PIDR2___S 0 + +#define DBG_EVENTFUN_PIDR3 (0x00BB1FEC) +#define DBG_EVENTFUN_PIDR3___RWC QCSR_REG_RO +#define DBG_EVENTFUN_PIDR3___POR 0x00000000 +#define DBG_EVENTFUN_PIDR3__REVAND___POR 0x0 +#define DBG_EVENTFUN_PIDR3__CUSTOMER_MODIFIED___POR 0x0 +#define DBG_EVENTFUN_PIDR3__REVAND___M 0x000000F0 +#define DBG_EVENTFUN_PIDR3__REVAND___S 4 +#define DBG_EVENTFUN_PIDR3__REVAND__REVAND_0X0 0x0 +#define DBG_EVENTFUN_PIDR3__CUSTOMER_MODIFIED___M 0x0000000F +#define DBG_EVENTFUN_PIDR3__CUSTOMER_MODIFIED___S 0 +#define DBG_EVENTFUN_PIDR3__CUSTOMER_MODIFIED__CUSTOMER_MODIFIED_0X0 0x0 +#define DBG_EVENTFUN_PIDR3___M 0x000000FF +#define DBG_EVENTFUN_PIDR3___S 0 + +#define DBG_EVENTFUN_PIDR4 (0x00BB1FD0) +#define DBG_EVENTFUN_PIDR4___RWC QCSR_REG_RO +#define DBG_EVENTFUN_PIDR4___POR 0x00000004 +#define DBG_EVENTFUN_PIDR4__FOURKB_COUNT___POR 0x0 +#define DBG_EVENTFUN_PIDR4__JEP106_CONT___POR 0x4 +#define DBG_EVENTFUN_PIDR4__FOURKB_COUNT___M 0x000000F0 +#define DBG_EVENTFUN_PIDR4__FOURKB_COUNT___S 4 +#define DBG_EVENTFUN_PIDR4__FOURKB_COUNT__FOURKB_COUNT_0X0 0x0 +#define DBG_EVENTFUN_PIDR4__JEP106_CONT___M 0x0000000F +#define DBG_EVENTFUN_PIDR4__JEP106_CONT___S 0 +#define DBG_EVENTFUN_PIDR4__JEP106_CONT__JEP106_CONT_0X4 0x4 +#define DBG_EVENTFUN_PIDR4___M 0x000000FF +#define DBG_EVENTFUN_PIDR4___S 0 + +#define DBG_EVENTFUN_PERIPHID5 (0x00BB1FD4) +#define DBG_EVENTFUN_PERIPHID5___RWC QCSR_REG_RO +#define DBG_EVENTFUN_PERIPHID5___POR 0x00000000 +#define DBG_EVENTFUN_PERIPHID5__PERIPHID5___POR 0x00000000 +#define DBG_EVENTFUN_PERIPHID5__PERIPHID5___M 0xFFFFFFFF +#define DBG_EVENTFUN_PERIPHID5__PERIPHID5___S 0 +#define DBG_EVENTFUN_PERIPHID5___M 0xFFFFFFFF +#define DBG_EVENTFUN_PERIPHID5___S 0 + +#define DBG_EVENTFUN_PERIPHID6 (0x00BB1FD8) +#define DBG_EVENTFUN_PERIPHID6___RWC QCSR_REG_RO +#define DBG_EVENTFUN_PERIPHID6___POR 0x00000000 +#define DBG_EVENTFUN_PERIPHID6__PERIPHID6___POR 0x00000000 +#define DBG_EVENTFUN_PERIPHID6__PERIPHID6___M 0xFFFFFFFF +#define DBG_EVENTFUN_PERIPHID6__PERIPHID6___S 0 +#define DBG_EVENTFUN_PERIPHID6___M 0xFFFFFFFF +#define DBG_EVENTFUN_PERIPHID6___S 0 + +#define DBG_EVENTFUN_PERIPHID7 (0x00BB1FDC) +#define DBG_EVENTFUN_PERIPHID7___RWC QCSR_REG_RO +#define DBG_EVENTFUN_PERIPHID7___POR 0x00000000 +#define DBG_EVENTFUN_PERIPHID7__PERIPHID7___POR 0x00000000 +#define DBG_EVENTFUN_PERIPHID7__PERIPHID7___M 0xFFFFFFFF +#define DBG_EVENTFUN_PERIPHID7__PERIPHID7___S 0 +#define DBG_EVENTFUN_PERIPHID7___M 0xFFFFFFFF +#define DBG_EVENTFUN_PERIPHID7___S 0 + +#define DBG_EVENTFUN_CID0 (0x00BB1FF0) +#define DBG_EVENTFUN_CID0___RWC QCSR_REG_RO +#define DBG_EVENTFUN_CID0___POR 0x0000000D +#define DBG_EVENTFUN_CID0__PREAMBLE___POR 0x0D +#define DBG_EVENTFUN_CID0__PREAMBLE___M 0x000000FF +#define DBG_EVENTFUN_CID0__PREAMBLE___S 0 +#define DBG_EVENTFUN_CID0__PREAMBLE__PREAMBLE_0X0D 0x0D +#define DBG_EVENTFUN_CID0___M 0x000000FF +#define DBG_EVENTFUN_CID0___S 0 + +#define DBG_EVENTFUN_CID1 (0x00BB1FF4) +#define DBG_EVENTFUN_CID1___RWC QCSR_REG_RO +#define DBG_EVENTFUN_CID1___POR 0x00000090 +#define DBG_EVENTFUN_CID1__CLASS___POR 0x9 +#define DBG_EVENTFUN_CID1__PREAMBLE___POR 0x0 +#define DBG_EVENTFUN_CID1__CLASS___M 0x000000F0 +#define DBG_EVENTFUN_CID1__CLASS___S 4 +#define DBG_EVENTFUN_CID1__CLASS__CLASS_0X9 0x9 +#define DBG_EVENTFUN_CID1__PREAMBLE___M 0x0000000F +#define DBG_EVENTFUN_CID1__PREAMBLE___S 0 +#define DBG_EVENTFUN_CID1__PREAMBLE__PREAMBLE_0X0 0x0 +#define DBG_EVENTFUN_CID1___M 0x000000FF +#define DBG_EVENTFUN_CID1___S 0 + +#define DBG_EVENTFUN_CID2 (0x00BB1FF8) +#define DBG_EVENTFUN_CID2___RWC QCSR_REG_RO +#define DBG_EVENTFUN_CID2___POR 0x00000005 +#define DBG_EVENTFUN_CID2__PREAMBLE___POR 0x05 +#define DBG_EVENTFUN_CID2__PREAMBLE___M 0x000000FF +#define DBG_EVENTFUN_CID2__PREAMBLE___S 0 +#define DBG_EVENTFUN_CID2__PREAMBLE__PREAMBLE_0X05 0x05 +#define DBG_EVENTFUN_CID2___M 0x000000FF +#define DBG_EVENTFUN_CID2___S 0 + +#define DBG_EVENTFUN_CID3 (0x00BB1FFC) +#define DBG_EVENTFUN_CID3___RWC QCSR_REG_RO +#define DBG_EVENTFUN_CID3___POR 0x000000B1 +#define DBG_EVENTFUN_CID3__PREAMBLE___POR 0xB1 +#define DBG_EVENTFUN_CID3__PREAMBLE___M 0x000000FF +#define DBG_EVENTFUN_CID3__PREAMBLE___S 0 +#define DBG_EVENTFUN_CID3__PREAMBLE__PREAMBLE_0XB1 0xB1 +#define DBG_EVENTFUN_CID3___M 0x000000FF +#define DBG_EVENTFUN_CID3___S 0 + +#define DBG_TLV_MACTLV_CFG (0x00BB2000) +#define DBG_TLV_MACTLV_CFG___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_CFG___POR 0x00000DE3 +#define DBG_TLV_MACTLV_CFG__LMAC0_EN___POR 0x1 +#define DBG_TLV_MACTLV_CFG__ATID___POR 0x5E +#define DBG_TLV_MACTLV_CFG__TRANSPORT___POR 0x0 +#define DBG_TLV_MACTLV_CFG__COLTRIG_EN___POR 0x0 +#define DBG_TLV_MACTLV_CFG__TSTMP_EN___POR 0x1 +#define DBG_TLV_MACTLV_CFG__ENABLE___POR 0x1 +#define DBG_TLV_MACTLV_CFG__LMAC0_EN___M 0x00000800 +#define DBG_TLV_MACTLV_CFG__LMAC0_EN___S 11 +#define DBG_TLV_MACTLV_CFG__ATID___M 0x000007F0 +#define DBG_TLV_MACTLV_CFG__ATID___S 4 +#define DBG_TLV_MACTLV_CFG__TRANSPORT___M 0x00000008 +#define DBG_TLV_MACTLV_CFG__TRANSPORT___S 3 +#define DBG_TLV_MACTLV_CFG__TRANSPORT__CMB 0x0 +#define DBG_TLV_MACTLV_CFG__TRANSPORT__ATB 0x1 +#define DBG_TLV_MACTLV_CFG__COLTRIG_EN___M 0x00000004 +#define DBG_TLV_MACTLV_CFG__COLTRIG_EN___S 2 +#define DBG_TLV_MACTLV_CFG__TSTMP_EN___M 0x00000002 +#define DBG_TLV_MACTLV_CFG__TSTMP_EN___S 1 +#define DBG_TLV_MACTLV_CFG__ENABLE___M 0x00000001 +#define DBG_TLV_MACTLV_CFG__ENABLE___S 0 +#define DBG_TLV_MACTLV_CFG___M 0x00000FFF +#define DBG_TLV_MACTLV_CFG___S 0 + +#define DBG_TLV_MACTLV_TGU_CFG (0x00BB2004) +#define DBG_TLV_MACTLV_TGU_CFG___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_TGU_CFG___POR 0x000000F0 +#define DBG_TLV_MACTLV_TGU_CFG__TRIG_COMBOP___POR 0x0 +#define DBG_TLV_MACTLV_TGU_CFG__TRIG_POL___POR 0xF +#define DBG_TLV_MACTLV_TGU_CFG__TRIG_EN___POR 0x0 +#define DBG_TLV_MACTLV_TGU_CFG__TRIG_COMBOP___M 0x00000100 +#define DBG_TLV_MACTLV_TGU_CFG__TRIG_COMBOP___S 8 +#define DBG_TLV_MACTLV_TGU_CFG__TRIG_POL___M 0x000000F0 +#define DBG_TLV_MACTLV_TGU_CFG__TRIG_POL___S 4 +#define DBG_TLV_MACTLV_TGU_CFG__TRIG_EN___M 0x0000000F +#define DBG_TLV_MACTLV_TGU_CFG__TRIG_EN___S 0 +#define DBG_TLV_MACTLV_TGU_CFG___M 0x000001FF +#define DBG_TLV_MACTLV_TGU_CFG___S 0 + +#define DBG_TLV_MACTLV_MATCH0_DATA (0x00BB2008) +#define DBG_TLV_MACTLV_MATCH0_DATA___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_MATCH0_DATA___POR 0x00000000 +#define DBG_TLV_MACTLV_MATCH0_DATA__DATA___POR 0x00000000 +#define DBG_TLV_MACTLV_MATCH0_DATA__DATA___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_MATCH0_DATA__DATA___S 0 +#define DBG_TLV_MACTLV_MATCH0_DATA___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_MATCH0_DATA___S 0 + +#define DBG_TLV_MACTLV_MATCH0_DATAH (0x00BB200C) +#define DBG_TLV_MACTLV_MATCH0_DATAH___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_MATCH0_DATAH___POR 0x00000000 +#define DBG_TLV_MACTLV_MATCH0_DATAH__DATA_48_32___POR 0x00000 +#define DBG_TLV_MACTLV_MATCH0_DATAH__DATA_48_32___M 0x0001FFFF +#define DBG_TLV_MACTLV_MATCH0_DATAH__DATA_48_32___S 0 +#define DBG_TLV_MACTLV_MATCH0_DATAH___M 0x0001FFFF +#define DBG_TLV_MACTLV_MATCH0_DATAH___S 0 + +#define DBG_TLV_MACTLV_MATCH0_MASK (0x00BB2010) +#define DBG_TLV_MACTLV_MATCH0_MASK___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_MATCH0_MASK___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_MATCH0_MASK__MASK___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_MATCH0_MASK__MASK___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_MATCH0_MASK__MASK___S 0 +#define DBG_TLV_MACTLV_MATCH0_MASK___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_MATCH0_MASK___S 0 + +#define DBG_TLV_MACTLV_MATCH0_MASKH (0x00BB2014) +#define DBG_TLV_MACTLV_MATCH0_MASKH___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_MATCH0_MASKH___POR 0x0001FFFF +#define DBG_TLV_MACTLV_MATCH0_MASKH__MASK_48_32___POR 0x1FFFF +#define DBG_TLV_MACTLV_MATCH0_MASKH__MASK_48_32___M 0x0001FFFF +#define DBG_TLV_MACTLV_MATCH0_MASKH__MASK_48_32___S 0 +#define DBG_TLV_MACTLV_MATCH0_MASKH___M 0x0001FFFF +#define DBG_TLV_MACTLV_MATCH0_MASKH___S 0 + +#define DBG_TLV_MACTLV_MATCH1_DATA (0x00BB2018) +#define DBG_TLV_MACTLV_MATCH1_DATA___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_MATCH1_DATA___POR 0x00000000 +#define DBG_TLV_MACTLV_MATCH1_DATA__DATA___POR 0x00000000 +#define DBG_TLV_MACTLV_MATCH1_DATA__DATA___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_MATCH1_DATA__DATA___S 0 +#define DBG_TLV_MACTLV_MATCH1_DATA___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_MATCH1_DATA___S 0 + +#define DBG_TLV_MACTLV_MATCH1_DATAH (0x00BB201C) +#define DBG_TLV_MACTLV_MATCH1_DATAH___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_MATCH1_DATAH___POR 0x00000000 +#define DBG_TLV_MACTLV_MATCH1_DATAH__DATA_48_32___POR 0x00000 +#define DBG_TLV_MACTLV_MATCH1_DATAH__DATA_48_32___M 0x0001FFFF +#define DBG_TLV_MACTLV_MATCH1_DATAH__DATA_48_32___S 0 +#define DBG_TLV_MACTLV_MATCH1_DATAH___M 0x0001FFFF +#define DBG_TLV_MACTLV_MATCH1_DATAH___S 0 + +#define DBG_TLV_MACTLV_MATCH1_MASK (0x00BB2020) +#define DBG_TLV_MACTLV_MATCH1_MASK___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_MATCH1_MASK___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_MATCH1_MASK__MASK___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_MATCH1_MASK__MASK___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_MATCH1_MASK__MASK___S 0 +#define DBG_TLV_MACTLV_MATCH1_MASK___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_MATCH1_MASK___S 0 + +#define DBG_TLV_MACTLV_MATCH1_MASKH (0x00BB2024) +#define DBG_TLV_MACTLV_MATCH1_MASKH___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_MATCH1_MASKH___POR 0x0001FFFF +#define DBG_TLV_MACTLV_MATCH1_MASKH__MASK_48_32___POR 0x1FFFF +#define DBG_TLV_MACTLV_MATCH1_MASKH__MASK_48_32___M 0x0001FFFF +#define DBG_TLV_MACTLV_MATCH1_MASKH__MASK_48_32___S 0 +#define DBG_TLV_MACTLV_MATCH1_MASKH___M 0x0001FFFF +#define DBG_TLV_MACTLV_MATCH1_MASKH___S 0 + +#define DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK (0x00BB2028) +#define DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK___POR 0x0000000F +#define DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID3___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID2___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID1___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID0___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID3___M 0x00000008 +#define DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID3___S 3 +#define DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID3__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID3__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID2___M 0x00000004 +#define DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID2___S 2 +#define DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID2__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID2__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID1___M 0x00000002 +#define DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID1___S 1 +#define DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID1__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID1__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID0___M 0x00000001 +#define DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID0___S 0 +#define DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID0__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK__SSID0__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK___M 0x0000000F +#define DBG_TLV_MACTLV_FILTER_CFG_SSID_MASK___S 0 + +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0 (0x00BB2040) +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID31___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID30___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID29___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID28___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID27___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID26___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID25___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID24___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID23___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID22___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID21___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID20___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID19___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID18___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID17___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID16___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID15___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID14___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID13___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID12___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID11___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID10___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID9___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID8___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID7___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID6___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID5___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID4___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID3___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID2___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID1___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID0___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID31___M 0x80000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID31___S 31 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID31__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID31__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID30___M 0x40000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID30___S 30 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID30__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID30__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID29___M 0x20000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID29___S 29 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID29__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID29__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID28___M 0x10000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID28___S 28 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID28__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID28__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID27___M 0x08000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID27___S 27 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID27__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID27__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID26___M 0x04000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID26___S 26 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID26__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID26__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID25___M 0x02000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID25___S 25 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID25__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID25__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID24___M 0x01000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID24___S 24 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID24__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID24__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID23___M 0x00800000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID23___S 23 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID23__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID23__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID22___M 0x00400000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID22___S 22 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID22__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID22__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID21___M 0x00200000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID21___S 21 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID21__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID21__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID20___M 0x00100000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID20___S 20 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID20__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID20__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID19___M 0x00080000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID19___S 19 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID19__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID19__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID18___M 0x00040000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID18___S 18 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID18__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID18__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID17___M 0x00020000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID17___S 17 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID17__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID17__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID16___M 0x00010000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID16___S 16 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID16__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID16__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID15___M 0x00008000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID15___S 15 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID15__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID15__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID14___M 0x00004000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID14___S 14 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID14__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID14__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID13___M 0x00002000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID13___S 13 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID13__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID13__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID12___M 0x00001000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID12___S 12 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID12__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID12__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID11___M 0x00000800 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID11___S 11 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID11__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID11__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID10___M 0x00000400 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID10___S 10 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID10__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID10__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID9___M 0x00000200 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID9___S 9 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID9__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID9__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID8___M 0x00000100 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID8___S 8 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID8__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID8__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID7___M 0x00000080 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID7___S 7 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID7__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID7__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID6___M 0x00000040 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID6___S 6 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID6__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID6__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID5___M 0x00000020 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID5___S 5 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID5__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID5__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID4___M 0x00000010 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID4___S 4 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID4__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID4__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID3___M 0x00000008 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID3___S 3 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID3__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID3__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID2___M 0x00000004 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID2___S 2 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID2__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID2__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID1___M 0x00000002 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID1___S 1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID1__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID1__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID0___M 0x00000001 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID0___S 0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID0__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0__TLVID0__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK0___S 0 + +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1 (0x00BB2044) +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID63___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID62___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID61___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID60___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID59___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID58___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID57___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID56___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID55___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID54___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID53___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID52___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID51___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID50___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID49___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID48___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID47___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID46___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID45___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID44___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID43___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID42___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID41___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID40___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID39___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID38___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID37___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID36___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID35___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID34___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID33___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID32___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID63___M 0x80000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID63___S 31 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID63__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID63__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID62___M 0x40000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID62___S 30 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID62__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID62__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID61___M 0x20000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID61___S 29 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID61__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID61__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID60___M 0x10000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID60___S 28 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID60__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID60__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID59___M 0x08000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID59___S 27 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID59__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID59__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID58___M 0x04000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID58___S 26 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID58__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID58__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID57___M 0x02000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID57___S 25 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID57__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID57__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID56___M 0x01000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID56___S 24 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID56__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID56__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID55___M 0x00800000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID55___S 23 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID55__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID55__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID54___M 0x00400000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID54___S 22 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID54__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID54__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID53___M 0x00200000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID53___S 21 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID53__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID53__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID52___M 0x00100000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID52___S 20 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID52__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID52__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID51___M 0x00080000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID51___S 19 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID51__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID51__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID50___M 0x00040000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID50___S 18 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID50__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID50__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID49___M 0x00020000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID49___S 17 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID49__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID49__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID48___M 0x00010000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID48___S 16 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID48__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID48__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID47___M 0x00008000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID47___S 15 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID47__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID47__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID46___M 0x00004000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID46___S 14 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID46__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID46__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID45___M 0x00002000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID45___S 13 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID45__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID45__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID44___M 0x00001000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID44___S 12 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID44__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID44__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID43___M 0x00000800 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID43___S 11 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID43__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID43__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID42___M 0x00000400 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID42___S 10 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID42__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID42__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID41___M 0x00000200 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID41___S 9 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID41__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID41__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID40___M 0x00000100 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID40___S 8 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID40__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID40__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID39___M 0x00000080 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID39___S 7 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID39__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID39__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID38___M 0x00000040 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID38___S 6 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID38__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID38__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID37___M 0x00000020 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID37___S 5 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID37__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID37__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID36___M 0x00000010 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID36___S 4 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID36__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID36__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID35___M 0x00000008 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID35___S 3 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID35__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID35__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID34___M 0x00000004 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID34___S 2 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID34__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID34__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID33___M 0x00000002 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID33___S 1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID33__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID33__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID32___M 0x00000001 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID32___S 0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID32__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1__TLVID32__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK1___S 0 + +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2 (0x00BB2048) +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID95___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID94___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID93___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID92___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID91___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID90___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID89___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID88___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID87___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID86___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID85___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID84___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID83___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID82___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID81___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID80___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID79___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID78___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID77___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID76___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID75___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID74___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID73___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID72___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID71___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID70___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID69___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID68___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID67___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID66___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID65___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID64___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID95___M 0x80000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID95___S 31 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID95__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID95__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID94___M 0x40000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID94___S 30 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID94__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID94__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID93___M 0x20000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID93___S 29 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID93__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID93__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID92___M 0x10000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID92___S 28 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID92__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID92__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID91___M 0x08000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID91___S 27 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID91__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID91__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID90___M 0x04000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID90___S 26 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID90__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID90__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID89___M 0x02000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID89___S 25 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID89__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID89__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID88___M 0x01000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID88___S 24 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID88__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID88__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID87___M 0x00800000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID87___S 23 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID87__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID87__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID86___M 0x00400000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID86___S 22 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID86__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID86__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID85___M 0x00200000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID85___S 21 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID85__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID85__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID84___M 0x00100000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID84___S 20 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID84__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID84__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID83___M 0x00080000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID83___S 19 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID83__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID83__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID82___M 0x00040000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID82___S 18 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID82__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID82__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID81___M 0x00020000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID81___S 17 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID81__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID81__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID80___M 0x00010000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID80___S 16 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID80__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID80__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID79___M 0x00008000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID79___S 15 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID79__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID79__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID78___M 0x00004000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID78___S 14 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID78__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID78__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID77___M 0x00002000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID77___S 13 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID77__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID77__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID76___M 0x00001000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID76___S 12 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID76__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID76__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID75___M 0x00000800 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID75___S 11 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID75__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID75__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID74___M 0x00000400 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID74___S 10 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID74__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID74__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID73___M 0x00000200 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID73___S 9 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID73__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID73__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID72___M 0x00000100 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID72___S 8 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID72__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID72__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID71___M 0x00000080 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID71___S 7 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID71__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID71__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID70___M 0x00000040 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID70___S 6 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID70__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID70__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID69___M 0x00000020 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID69___S 5 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID69__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID69__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID68___M 0x00000010 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID68___S 4 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID68__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID68__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID67___M 0x00000008 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID67___S 3 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID67__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID67__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID66___M 0x00000004 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID66___S 2 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID66__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID66__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID65___M 0x00000002 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID65___S 1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID65__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID65__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID64___M 0x00000001 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID64___S 0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID64__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2__TLVID64__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK2___S 0 + +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3 (0x00BB204C) +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID127___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID126___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID125___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID124___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID123___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID122___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID121___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID120___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID119___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID118___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID117___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID116___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID115___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID114___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID113___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID112___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID111___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID110___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID109___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID108___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID107___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID106___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID105___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID104___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID103___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID102___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID101___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID100___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID99___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID98___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID97___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID96___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID127___M 0x80000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID127___S 31 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID127__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID127__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID126___M 0x40000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID126___S 30 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID126__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID126__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID125___M 0x20000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID125___S 29 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID125__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID125__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID124___M 0x10000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID124___S 28 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID124__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID124__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID123___M 0x08000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID123___S 27 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID123__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID123__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID122___M 0x04000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID122___S 26 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID122__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID122__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID121___M 0x02000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID121___S 25 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID121__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID121__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID120___M 0x01000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID120___S 24 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID120__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID120__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID119___M 0x00800000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID119___S 23 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID119__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID119__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID118___M 0x00400000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID118___S 22 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID118__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID118__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID117___M 0x00200000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID117___S 21 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID117__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID117__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID116___M 0x00100000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID116___S 20 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID116__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID116__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID115___M 0x00080000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID115___S 19 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID115__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID115__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID114___M 0x00040000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID114___S 18 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID114__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID114__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID113___M 0x00020000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID113___S 17 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID113__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID113__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID112___M 0x00010000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID112___S 16 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID112__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID112__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID111___M 0x00008000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID111___S 15 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID111__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID111__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID110___M 0x00004000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID110___S 14 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID110__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID110__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID109___M 0x00002000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID109___S 13 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID109__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID109__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID108___M 0x00001000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID108___S 12 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID108__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID108__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID107___M 0x00000800 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID107___S 11 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID107__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID107__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID106___M 0x00000400 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID106___S 10 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID106__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID106__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID105___M 0x00000200 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID105___S 9 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID105__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID105__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID104___M 0x00000100 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID104___S 8 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID104__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID104__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID103___M 0x00000080 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID103___S 7 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID103__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID103__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID102___M 0x00000040 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID102___S 6 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID102__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID102__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID101___M 0x00000020 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID101___S 5 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID101__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID101__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID100___M 0x00000010 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID100___S 4 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID100__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID100__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID99___M 0x00000008 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID99___S 3 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID99__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID99__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID98___M 0x00000004 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID98___S 2 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID98__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID98__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID97___M 0x00000002 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID97___S 1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID97__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID97__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID96___M 0x00000001 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID96___S 0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID96__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3__TLVID96__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK3___S 0 + +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4 (0x00BB2050) +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID159___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID158___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID157___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID156___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID155___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID154___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID153___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID152___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID151___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID150___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID149___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID148___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID147___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID146___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID145___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID144___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID143___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID142___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID141___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID140___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID139___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID138___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID137___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID136___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID135___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID134___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID133___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID132___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID131___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID130___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID129___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID128___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID159___M 0x80000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID159___S 31 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID159__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID159__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID158___M 0x40000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID158___S 30 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID158__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID158__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID157___M 0x20000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID157___S 29 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID157__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID157__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID156___M 0x10000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID156___S 28 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID156__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID156__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID155___M 0x08000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID155___S 27 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID155__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID155__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID154___M 0x04000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID154___S 26 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID154__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID154__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID153___M 0x02000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID153___S 25 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID153__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID153__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID152___M 0x01000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID152___S 24 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID152__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID152__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID151___M 0x00800000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID151___S 23 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID151__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID151__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID150___M 0x00400000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID150___S 22 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID150__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID150__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID149___M 0x00200000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID149___S 21 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID149__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID149__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID148___M 0x00100000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID148___S 20 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID148__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID148__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID147___M 0x00080000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID147___S 19 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID147__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID147__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID146___M 0x00040000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID146___S 18 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID146__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID146__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID145___M 0x00020000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID145___S 17 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID145__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID145__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID144___M 0x00010000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID144___S 16 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID144__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID144__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID143___M 0x00008000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID143___S 15 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID143__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID143__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID142___M 0x00004000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID142___S 14 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID142__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID142__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID141___M 0x00002000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID141___S 13 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID141__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID141__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID140___M 0x00001000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID140___S 12 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID140__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID140__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID139___M 0x00000800 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID139___S 11 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID139__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID139__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID138___M 0x00000400 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID138___S 10 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID138__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID138__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID137___M 0x00000200 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID137___S 9 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID137__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID137__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID136___M 0x00000100 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID136___S 8 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID136__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID136__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID135___M 0x00000080 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID135___S 7 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID135__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID135__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID134___M 0x00000040 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID134___S 6 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID134__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID134__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID133___M 0x00000020 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID133___S 5 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID133__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID133__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID132___M 0x00000010 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID132___S 4 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID132__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID132__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID131___M 0x00000008 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID131___S 3 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID131__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID131__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID130___M 0x00000004 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID130___S 2 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID130__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID130__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID129___M 0x00000002 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID129___S 1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID129__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID129__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID128___M 0x00000001 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID128___S 0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID128__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4__TLVID128__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK4___S 0 + +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5 (0x00BB2054) +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID191___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID190___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID189___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID188___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID187___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID186___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID185___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID184___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID183___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID182___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID181___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID180___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID179___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID178___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID177___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID176___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID175___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID174___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID173___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID172___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID171___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID170___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID169___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID168___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID167___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID166___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID165___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID164___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID163___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID162___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID161___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID160___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID191___M 0x80000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID191___S 31 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID191__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID191__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID190___M 0x40000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID190___S 30 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID190__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID190__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID189___M 0x20000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID189___S 29 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID189__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID189__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID188___M 0x10000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID188___S 28 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID188__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID188__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID187___M 0x08000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID187___S 27 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID187__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID187__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID186___M 0x04000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID186___S 26 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID186__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID186__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID185___M 0x02000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID185___S 25 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID185__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID185__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID184___M 0x01000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID184___S 24 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID184__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID184__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID183___M 0x00800000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID183___S 23 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID183__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID183__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID182___M 0x00400000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID182___S 22 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID182__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID182__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID181___M 0x00200000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID181___S 21 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID181__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID181__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID180___M 0x00100000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID180___S 20 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID180__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID180__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID179___M 0x00080000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID179___S 19 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID179__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID179__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID178___M 0x00040000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID178___S 18 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID178__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID178__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID177___M 0x00020000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID177___S 17 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID177__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID177__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID176___M 0x00010000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID176___S 16 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID176__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID176__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID175___M 0x00008000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID175___S 15 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID175__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID175__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID174___M 0x00004000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID174___S 14 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID174__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID174__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID173___M 0x00002000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID173___S 13 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID173__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID173__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID172___M 0x00001000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID172___S 12 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID172__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID172__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID171___M 0x00000800 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID171___S 11 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID171__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID171__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID170___M 0x00000400 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID170___S 10 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID170__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID170__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID169___M 0x00000200 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID169___S 9 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID169__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID169__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID168___M 0x00000100 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID168___S 8 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID168__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID168__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID167___M 0x00000080 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID167___S 7 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID167__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID167__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID166___M 0x00000040 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID166___S 6 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID166__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID166__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID165___M 0x00000020 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID165___S 5 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID165__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID165__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID164___M 0x00000010 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID164___S 4 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID164__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID164__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID163___M 0x00000008 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID163___S 3 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID163__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID163__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID162___M 0x00000004 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID162___S 2 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID162__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID162__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID161___M 0x00000002 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID161___S 1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID161__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID161__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID160___M 0x00000001 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID160___S 0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID160__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5__TLVID160__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK5___S 0 + +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6 (0x00BB2058) +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID223___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID222___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID221___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID220___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID219___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID218___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID217___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID216___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID215___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID214___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID213___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID212___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID211___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID210___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID209___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID208___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID207___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID206___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID205___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID204___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID203___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID202___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID201___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID200___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID199___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID198___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID197___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID196___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID195___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID194___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID193___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID192___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID223___M 0x80000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID223___S 31 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID223__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID223__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID222___M 0x40000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID222___S 30 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID222__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID222__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID221___M 0x20000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID221___S 29 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID221__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID221__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID220___M 0x10000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID220___S 28 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID220__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID220__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID219___M 0x08000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID219___S 27 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID219__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID219__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID218___M 0x04000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID218___S 26 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID218__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID218__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID217___M 0x02000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID217___S 25 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID217__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID217__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID216___M 0x01000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID216___S 24 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID216__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID216__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID215___M 0x00800000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID215___S 23 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID215__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID215__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID214___M 0x00400000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID214___S 22 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID214__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID214__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID213___M 0x00200000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID213___S 21 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID213__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID213__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID212___M 0x00100000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID212___S 20 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID212__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID212__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID211___M 0x00080000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID211___S 19 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID211__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID211__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID210___M 0x00040000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID210___S 18 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID210__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID210__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID209___M 0x00020000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID209___S 17 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID209__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID209__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID208___M 0x00010000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID208___S 16 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID208__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID208__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID207___M 0x00008000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID207___S 15 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID207__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID207__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID206___M 0x00004000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID206___S 14 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID206__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID206__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID205___M 0x00002000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID205___S 13 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID205__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID205__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID204___M 0x00001000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID204___S 12 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID204__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID204__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID203___M 0x00000800 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID203___S 11 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID203__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID203__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID202___M 0x00000400 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID202___S 10 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID202__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID202__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID201___M 0x00000200 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID201___S 9 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID201__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID201__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID200___M 0x00000100 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID200___S 8 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID200__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID200__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID199___M 0x00000080 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID199___S 7 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID199__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID199__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID198___M 0x00000040 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID198___S 6 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID198__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID198__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID197___M 0x00000020 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID197___S 5 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID197__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID197__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID196___M 0x00000010 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID196___S 4 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID196__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID196__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID195___M 0x00000008 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID195___S 3 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID195__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID195__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID194___M 0x00000004 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID194___S 2 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID194__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID194__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID193___M 0x00000002 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID193___S 1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID193__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID193__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID192___M 0x00000001 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID192___S 0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID192__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6__TLVID192__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK6___S 0 + +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7 (0x00BB205C) +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID255___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID254___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID253___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID252___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID251___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID250___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID249___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID248___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID247___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID246___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID245___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID244___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID243___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID242___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID241___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID240___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID239___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID238___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID237___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID236___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID235___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID234___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID233___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID232___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID231___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID230___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID229___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID228___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID227___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID226___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID225___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID224___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID255___M 0x80000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID255___S 31 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID255__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID255__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID254___M 0x40000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID254___S 30 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID254__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID254__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID253___M 0x20000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID253___S 29 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID253__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID253__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID252___M 0x10000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID252___S 28 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID252__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID252__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID251___M 0x08000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID251___S 27 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID251__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID251__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID250___M 0x04000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID250___S 26 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID250__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID250__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID249___M 0x02000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID249___S 25 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID249__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID249__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID248___M 0x01000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID248___S 24 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID248__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID248__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID247___M 0x00800000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID247___S 23 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID247__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID247__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID246___M 0x00400000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID246___S 22 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID246__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID246__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID245___M 0x00200000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID245___S 21 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID245__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID245__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID244___M 0x00100000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID244___S 20 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID244__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID244__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID243___M 0x00080000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID243___S 19 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID243__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID243__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID242___M 0x00040000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID242___S 18 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID242__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID242__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID241___M 0x00020000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID241___S 17 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID241__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID241__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID240___M 0x00010000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID240___S 16 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID240__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID240__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID239___M 0x00008000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID239___S 15 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID239__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID239__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID238___M 0x00004000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID238___S 14 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID238__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID238__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID237___M 0x00002000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID237___S 13 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID237__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID237__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID236___M 0x00001000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID236___S 12 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID236__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID236__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID235___M 0x00000800 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID235___S 11 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID235__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID235__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID234___M 0x00000400 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID234___S 10 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID234__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID234__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID233___M 0x00000200 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID233___S 9 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID233__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID233__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID232___M 0x00000100 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID232___S 8 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID232__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID232__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID231___M 0x00000080 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID231___S 7 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID231__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID231__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID230___M 0x00000040 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID230___S 6 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID230__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID230__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID229___M 0x00000020 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID229___S 5 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID229__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID229__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID228___M 0x00000010 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID228___S 4 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID228__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID228__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID227___M 0x00000008 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID227___S 3 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID227__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID227__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID226___M 0x00000004 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID226___S 2 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID226__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID226__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID225___M 0x00000002 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID225___S 1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID225__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID225__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID224___M 0x00000001 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID224___S 0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID224__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7__TLVID224__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK7___S 0 + +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8 (0x00BB2060) +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID287___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID286___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID285___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID284___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID283___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID282___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID281___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID280___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID279___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID278___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID277___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID276___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID275___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID274___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID273___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID272___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID271___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID270___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID269___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID268___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID267___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID266___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID265___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID264___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID263___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID262___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID261___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID260___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID259___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID258___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID257___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID256___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID287___M 0x80000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID287___S 31 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID287__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID287__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID286___M 0x40000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID286___S 30 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID286__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID286__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID285___M 0x20000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID285___S 29 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID285__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID285__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID284___M 0x10000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID284___S 28 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID284__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID284__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID283___M 0x08000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID283___S 27 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID283__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID283__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID282___M 0x04000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID282___S 26 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID282__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID282__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID281___M 0x02000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID281___S 25 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID281__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID281__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID280___M 0x01000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID280___S 24 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID280__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID280__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID279___M 0x00800000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID279___S 23 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID279__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID279__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID278___M 0x00400000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID278___S 22 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID278__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID278__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID277___M 0x00200000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID277___S 21 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID277__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID277__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID276___M 0x00100000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID276___S 20 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID276__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID276__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID275___M 0x00080000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID275___S 19 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID275__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID275__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID274___M 0x00040000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID274___S 18 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID274__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID274__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID273___M 0x00020000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID273___S 17 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID273__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID273__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID272___M 0x00010000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID272___S 16 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID272__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID272__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID271___M 0x00008000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID271___S 15 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID271__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID271__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID270___M 0x00004000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID270___S 14 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID270__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID270__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID269___M 0x00002000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID269___S 13 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID269__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID269__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID268___M 0x00001000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID268___S 12 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID268__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID268__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID267___M 0x00000800 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID267___S 11 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID267__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID267__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID266___M 0x00000400 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID266___S 10 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID266__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID266__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID265___M 0x00000200 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID265___S 9 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID265__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID265__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID264___M 0x00000100 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID264___S 8 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID264__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID264__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID263___M 0x00000080 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID263___S 7 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID263__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID263__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID262___M 0x00000040 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID262___S 6 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID262__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID262__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID261___M 0x00000020 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID261___S 5 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID261__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID261__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID260___M 0x00000010 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID260___S 4 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID260__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID260__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID259___M 0x00000008 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID259___S 3 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID259__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID259__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID258___M 0x00000004 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID258___S 2 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID258__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID258__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID257___M 0x00000002 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID257___S 1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID257__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID257__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID256___M 0x00000001 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID256___S 0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID256__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8__TLVID256__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK8___S 0 + +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9 (0x00BB2064) +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID319___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID318___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID317___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID316___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID315___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID314___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID313___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID312___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID311___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID310___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID309___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID308___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID307___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID306___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID305___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID304___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID303___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID302___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID301___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID300___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID299___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID298___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID297___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID296___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID295___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID294___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID293___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID292___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID291___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID290___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID289___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID288___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID319___M 0x80000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID319___S 31 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID319__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID319__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID318___M 0x40000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID318___S 30 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID318__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID318__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID317___M 0x20000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID317___S 29 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID317__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID317__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID316___M 0x10000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID316___S 28 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID316__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID316__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID315___M 0x08000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID315___S 27 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID315__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID315__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID314___M 0x04000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID314___S 26 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID314__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID314__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID313___M 0x02000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID313___S 25 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID313__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID313__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID312___M 0x01000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID312___S 24 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID312__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID312__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID311___M 0x00800000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID311___S 23 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID311__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID311__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID310___M 0x00400000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID310___S 22 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID310__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID310__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID309___M 0x00200000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID309___S 21 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID309__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID309__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID308___M 0x00100000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID308___S 20 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID308__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID308__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID307___M 0x00080000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID307___S 19 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID307__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID307__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID306___M 0x00040000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID306___S 18 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID306__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID306__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID305___M 0x00020000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID305___S 17 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID305__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID305__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID304___M 0x00010000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID304___S 16 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID304__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID304__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID303___M 0x00008000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID303___S 15 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID303__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID303__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID302___M 0x00004000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID302___S 14 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID302__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID302__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID301___M 0x00002000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID301___S 13 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID301__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID301__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID300___M 0x00001000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID300___S 12 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID300__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID300__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID299___M 0x00000800 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID299___S 11 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID299__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID299__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID298___M 0x00000400 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID298___S 10 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID298__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID298__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID297___M 0x00000200 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID297___S 9 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID297__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID297__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID296___M 0x00000100 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID296___S 8 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID296__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID296__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID295___M 0x00000080 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID295___S 7 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID295__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID295__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID294___M 0x00000040 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID294___S 6 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID294__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID294__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID293___M 0x00000020 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID293___S 5 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID293__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID293__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID292___M 0x00000010 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID292___S 4 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID292__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID292__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID291___M 0x00000008 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID291___S 3 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID291__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID291__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID290___M 0x00000004 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID290___S 2 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID290__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID290__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID289___M 0x00000002 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID289___S 1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID289__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID289__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID288___M 0x00000001 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID288___S 0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID288__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9__TLVID288__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK9___S 0 + +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10 (0x00BB2068) +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID351___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID350___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID349___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID348___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID347___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID346___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID345___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID344___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID343___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID342___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID341___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID340___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID339___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID338___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID337___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID336___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID335___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID334___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID333___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID332___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID331___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID330___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID329___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID328___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID327___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID326___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID325___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID324___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID323___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID322___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID321___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID320___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID351___M 0x80000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID351___S 31 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID351__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID351__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID350___M 0x40000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID350___S 30 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID350__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID350__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID349___M 0x20000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID349___S 29 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID349__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID349__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID348___M 0x10000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID348___S 28 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID348__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID348__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID347___M 0x08000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID347___S 27 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID347__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID347__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID346___M 0x04000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID346___S 26 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID346__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID346__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID345___M 0x02000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID345___S 25 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID345__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID345__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID344___M 0x01000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID344___S 24 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID344__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID344__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID343___M 0x00800000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID343___S 23 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID343__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID343__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID342___M 0x00400000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID342___S 22 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID342__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID342__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID341___M 0x00200000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID341___S 21 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID341__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID341__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID340___M 0x00100000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID340___S 20 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID340__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID340__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID339___M 0x00080000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID339___S 19 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID339__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID339__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID338___M 0x00040000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID338___S 18 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID338__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID338__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID337___M 0x00020000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID337___S 17 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID337__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID337__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID336___M 0x00010000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID336___S 16 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID336__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID336__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID335___M 0x00008000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID335___S 15 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID335__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID335__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID334___M 0x00004000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID334___S 14 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID334__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID334__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID333___M 0x00002000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID333___S 13 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID333__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID333__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID332___M 0x00001000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID332___S 12 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID332__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID332__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID331___M 0x00000800 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID331___S 11 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID331__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID331__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID330___M 0x00000400 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID330___S 10 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID330__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID330__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID329___M 0x00000200 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID329___S 9 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID329__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID329__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID328___M 0x00000100 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID328___S 8 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID328__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID328__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID327___M 0x00000080 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID327___S 7 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID327__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID327__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID326___M 0x00000040 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID326___S 6 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID326__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID326__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID325___M 0x00000020 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID325___S 5 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID325__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID325__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID324___M 0x00000010 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID324___S 4 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID324__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID324__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID323___M 0x00000008 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID323___S 3 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID323__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID323__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID322___M 0x00000004 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID322___S 2 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID322__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID322__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID321___M 0x00000002 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID321___S 1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID321__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID321__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID320___M 0x00000001 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID320___S 0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID320__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10__TLVID320__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK10___S 0 + +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11 (0x00BB206C) +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID383___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID382___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID381___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID380___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID379___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID378___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID377___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID376___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID375___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID374___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID373___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID372___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID371___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID370___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID369___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID368___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID367___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID366___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID365___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID364___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID363___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID362___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID361___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID360___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID359___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID358___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID357___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID356___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID355___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID354___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID353___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID352___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID383___M 0x80000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID383___S 31 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID383__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID383__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID382___M 0x40000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID382___S 30 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID382__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID382__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID381___M 0x20000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID381___S 29 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID381__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID381__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID380___M 0x10000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID380___S 28 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID380__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID380__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID379___M 0x08000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID379___S 27 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID379__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID379__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID378___M 0x04000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID378___S 26 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID378__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID378__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID377___M 0x02000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID377___S 25 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID377__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID377__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID376___M 0x01000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID376___S 24 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID376__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID376__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID375___M 0x00800000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID375___S 23 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID375__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID375__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID374___M 0x00400000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID374___S 22 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID374__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID374__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID373___M 0x00200000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID373___S 21 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID373__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID373__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID372___M 0x00100000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID372___S 20 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID372__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID372__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID371___M 0x00080000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID371___S 19 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID371__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID371__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID370___M 0x00040000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID370___S 18 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID370__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID370__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID369___M 0x00020000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID369___S 17 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID369__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID369__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID368___M 0x00010000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID368___S 16 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID368__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID368__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID367___M 0x00008000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID367___S 15 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID367__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID367__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID366___M 0x00004000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID366___S 14 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID366__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID366__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID365___M 0x00002000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID365___S 13 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID365__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID365__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID364___M 0x00001000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID364___S 12 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID364__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID364__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID363___M 0x00000800 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID363___S 11 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID363__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID363__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID362___M 0x00000400 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID362___S 10 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID362__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID362__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID361___M 0x00000200 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID361___S 9 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID361__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID361__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID360___M 0x00000100 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID360___S 8 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID360__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID360__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID359___M 0x00000080 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID359___S 7 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID359__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID359__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID358___M 0x00000040 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID358___S 6 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID358__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID358__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID357___M 0x00000020 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID357___S 5 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID357__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID357__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID356___M 0x00000010 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID356___S 4 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID356__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID356__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID355___M 0x00000008 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID355___S 3 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID355__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID355__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID354___M 0x00000004 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID354___S 2 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID354__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID354__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID353___M 0x00000002 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID353___S 1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID353__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID353__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID352___M 0x00000001 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID352___S 0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID352__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11__TLVID352__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK11___S 0 + +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12 (0x00BB2070) +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID415___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID414___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID413___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID412___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID411___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID410___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID409___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID408___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID407___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID406___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID405___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID404___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID403___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID402___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID401___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID400___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID399___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID398___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID397___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID396___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID395___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID394___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID393___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID392___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID391___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID390___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID389___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID388___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID387___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID386___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID385___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID384___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID415___M 0x80000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID415___S 31 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID415__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID415__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID414___M 0x40000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID414___S 30 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID414__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID414__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID413___M 0x20000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID413___S 29 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID413__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID413__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID412___M 0x10000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID412___S 28 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID412__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID412__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID411___M 0x08000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID411___S 27 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID411__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID411__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID410___M 0x04000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID410___S 26 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID410__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID410__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID409___M 0x02000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID409___S 25 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID409__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID409__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID408___M 0x01000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID408___S 24 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID408__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID408__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID407___M 0x00800000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID407___S 23 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID407__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID407__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID406___M 0x00400000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID406___S 22 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID406__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID406__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID405___M 0x00200000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID405___S 21 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID405__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID405__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID404___M 0x00100000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID404___S 20 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID404__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID404__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID403___M 0x00080000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID403___S 19 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID403__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID403__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID402___M 0x00040000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID402___S 18 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID402__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID402__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID401___M 0x00020000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID401___S 17 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID401__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID401__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID400___M 0x00010000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID400___S 16 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID400__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID400__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID399___M 0x00008000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID399___S 15 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID399__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID399__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID398___M 0x00004000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID398___S 14 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID398__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID398__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID397___M 0x00002000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID397___S 13 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID397__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID397__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID396___M 0x00001000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID396___S 12 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID396__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID396__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID395___M 0x00000800 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID395___S 11 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID395__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID395__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID394___M 0x00000400 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID394___S 10 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID394__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID394__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID393___M 0x00000200 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID393___S 9 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID393__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID393__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID392___M 0x00000100 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID392___S 8 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID392__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID392__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID391___M 0x00000080 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID391___S 7 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID391__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID391__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID390___M 0x00000040 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID390___S 6 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID390__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID390__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID389___M 0x00000020 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID389___S 5 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID389__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID389__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID388___M 0x00000010 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID388___S 4 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID388__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID388__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID387___M 0x00000008 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID387___S 3 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID387__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID387__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID386___M 0x00000004 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID386___S 2 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID386__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID386__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID385___M 0x00000002 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID385___S 1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID385__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID385__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID384___M 0x00000001 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID384___S 0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID384__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12__TLVID384__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK12___S 0 + +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13 (0x00BB2074) +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID447___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID446___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID445___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID444___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID443___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID442___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID441___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID440___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID439___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID438___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID437___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID436___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID435___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID434___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID433___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID432___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID431___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID430___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID429___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID428___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID427___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID426___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID425___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID424___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID423___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID422___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID421___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID420___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID419___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID418___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID417___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID416___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID447___M 0x80000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID447___S 31 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID447__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID447__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID446___M 0x40000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID446___S 30 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID446__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID446__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID445___M 0x20000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID445___S 29 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID445__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID445__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID444___M 0x10000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID444___S 28 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID444__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID444__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID443___M 0x08000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID443___S 27 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID443__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID443__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID442___M 0x04000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID442___S 26 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID442__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID442__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID441___M 0x02000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID441___S 25 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID441__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID441__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID440___M 0x01000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID440___S 24 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID440__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID440__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID439___M 0x00800000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID439___S 23 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID439__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID439__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID438___M 0x00400000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID438___S 22 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID438__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID438__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID437___M 0x00200000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID437___S 21 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID437__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID437__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID436___M 0x00100000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID436___S 20 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID436__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID436__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID435___M 0x00080000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID435___S 19 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID435__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID435__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID434___M 0x00040000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID434___S 18 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID434__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID434__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID433___M 0x00020000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID433___S 17 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID433__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID433__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID432___M 0x00010000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID432___S 16 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID432__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID432__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID431___M 0x00008000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID431___S 15 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID431__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID431__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID430___M 0x00004000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID430___S 14 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID430__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID430__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID429___M 0x00002000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID429___S 13 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID429__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID429__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID428___M 0x00001000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID428___S 12 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID428__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID428__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID427___M 0x00000800 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID427___S 11 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID427__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID427__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID426___M 0x00000400 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID426___S 10 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID426__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID426__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID425___M 0x00000200 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID425___S 9 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID425__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID425__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID424___M 0x00000100 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID424___S 8 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID424__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID424__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID423___M 0x00000080 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID423___S 7 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID423__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID423__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID422___M 0x00000040 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID422___S 6 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID422__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID422__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID421___M 0x00000020 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID421___S 5 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID421__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID421__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID420___M 0x00000010 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID420___S 4 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID420__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID420__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID419___M 0x00000008 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID419___S 3 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID419__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID419__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID418___M 0x00000004 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID418___S 2 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID418__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID418__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID417___M 0x00000002 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID417___S 1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID417__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID417__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID416___M 0x00000001 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID416___S 0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID416__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13__TLVID416__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK13___S 0 + +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14 (0x00BB2078) +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID479___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID478___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID477___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID476___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID475___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID474___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID473___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID472___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID471___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID470___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID469___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID468___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID467___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID466___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID465___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID464___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID463___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID462___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID461___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID460___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID459___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID458___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID457___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID456___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID455___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID454___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID453___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID452___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID451___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID450___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID449___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID448___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID479___M 0x80000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID479___S 31 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID479__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID479__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID478___M 0x40000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID478___S 30 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID478__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID478__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID477___M 0x20000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID477___S 29 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID477__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID477__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID476___M 0x10000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID476___S 28 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID476__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID476__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID475___M 0x08000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID475___S 27 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID475__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID475__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID474___M 0x04000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID474___S 26 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID474__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID474__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID473___M 0x02000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID473___S 25 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID473__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID473__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID472___M 0x01000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID472___S 24 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID472__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID472__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID471___M 0x00800000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID471___S 23 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID471__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID471__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID470___M 0x00400000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID470___S 22 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID470__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID470__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID469___M 0x00200000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID469___S 21 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID469__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID469__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID468___M 0x00100000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID468___S 20 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID468__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID468__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID467___M 0x00080000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID467___S 19 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID467__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID467__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID466___M 0x00040000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID466___S 18 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID466__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID466__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID465___M 0x00020000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID465___S 17 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID465__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID465__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID464___M 0x00010000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID464___S 16 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID464__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID464__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID463___M 0x00008000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID463___S 15 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID463__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID463__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID462___M 0x00004000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID462___S 14 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID462__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID462__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID461___M 0x00002000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID461___S 13 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID461__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID461__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID460___M 0x00001000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID460___S 12 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID460__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID460__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID459___M 0x00000800 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID459___S 11 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID459__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID459__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID458___M 0x00000400 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID458___S 10 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID458__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID458__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID457___M 0x00000200 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID457___S 9 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID457__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID457__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID456___M 0x00000100 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID456___S 8 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID456__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID456__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID455___M 0x00000080 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID455___S 7 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID455__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID455__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID454___M 0x00000040 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID454___S 6 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID454__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID454__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID453___M 0x00000020 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID453___S 5 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID453__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID453__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID452___M 0x00000010 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID452___S 4 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID452__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID452__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID451___M 0x00000008 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID451___S 3 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID451__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID451__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID450___M 0x00000004 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID450___S 2 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID450__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID450__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID449___M 0x00000002 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID449___S 1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID449__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID449__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID448___M 0x00000001 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID448___S 0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID448__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14__TLVID448__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK14___S 0 + +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15 (0x00BB207C) +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID511___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID510___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID509___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID508___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID507___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID506___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID505___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID504___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID503___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID502___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID501___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID500___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID499___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID498___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID497___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID496___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID495___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID494___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID493___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID492___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID491___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID490___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID489___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID488___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID487___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID486___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID485___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID484___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID483___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID482___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID481___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID480___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID511___M 0x80000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID511___S 31 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID511__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID511__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID510___M 0x40000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID510___S 30 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID510__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID510__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID509___M 0x20000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID509___S 29 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID509__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID509__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID508___M 0x10000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID508___S 28 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID508__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID508__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID507___M 0x08000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID507___S 27 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID507__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID507__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID506___M 0x04000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID506___S 26 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID506__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID506__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID505___M 0x02000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID505___S 25 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID505__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID505__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID504___M 0x01000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID504___S 24 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID504__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID504__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID503___M 0x00800000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID503___S 23 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID503__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID503__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID502___M 0x00400000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID502___S 22 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID502__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID502__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID501___M 0x00200000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID501___S 21 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID501__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID501__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID500___M 0x00100000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID500___S 20 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID500__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID500__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID499___M 0x00080000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID499___S 19 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID499__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID499__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID498___M 0x00040000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID498___S 18 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID498__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID498__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID497___M 0x00020000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID497___S 17 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID497__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID497__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID496___M 0x00010000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID496___S 16 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID496__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID496__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID495___M 0x00008000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID495___S 15 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID495__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID495__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID494___M 0x00004000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID494___S 14 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID494__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID494__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID493___M 0x00002000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID493___S 13 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID493__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID493__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID492___M 0x00001000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID492___S 12 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID492__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID492__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID491___M 0x00000800 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID491___S 11 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID491__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID491__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID490___M 0x00000400 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID490___S 10 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID490__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID490__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID489___M 0x00000200 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID489___S 9 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID489__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID489__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID488___M 0x00000100 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID488___S 8 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID488__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID488__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID487___M 0x00000080 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID487___S 7 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID487__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID487__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID486___M 0x00000040 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID486___S 6 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID486__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID486__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID485___M 0x00000020 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID485___S 5 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID485__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID485__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID484___M 0x00000010 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID484___S 4 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID484__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID484__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID483___M 0x00000008 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID483___S 3 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID483__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID483__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID482___M 0x00000004 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID482___S 2 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID482__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID482__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID481___M 0x00000002 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID481___S 1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID481__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID481__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID480___M 0x00000001 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID480___S 0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID480__DISABLE 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15__TLVID480__ENABLE 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_MASK15___S 0 + +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0 (0x00BB2080) +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID31___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID30___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID29___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID28___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID27___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID26___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID25___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID24___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID23___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID22___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID21___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID20___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID19___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID18___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID17___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID16___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID15___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID14___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID13___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID12___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID11___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID10___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID9___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID8___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID7___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID6___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID5___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID4___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID3___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID2___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID1___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID0___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID31___M 0x80000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID31___S 31 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID31__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID31__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID30___M 0x40000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID30___S 30 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID30__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID30__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID29___M 0x20000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID29___S 29 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID29__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID29__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID28___M 0x10000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID28___S 28 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID28__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID28__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID27___M 0x08000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID27___S 27 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID27__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID27__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID26___M 0x04000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID26___S 26 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID26__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID26__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID25___M 0x02000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID25___S 25 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID25__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID25__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID24___M 0x01000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID24___S 24 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID24__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID24__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID23___M 0x00800000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID23___S 23 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID23__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID23__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID22___M 0x00400000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID22___S 22 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID22__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID22__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID21___M 0x00200000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID21___S 21 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID21__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID21__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID20___M 0x00100000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID20___S 20 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID20__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID20__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID19___M 0x00080000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID19___S 19 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID19__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID19__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID18___M 0x00040000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID18___S 18 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID18__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID18__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID17___M 0x00020000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID17___S 17 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID17__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID17__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID16___M 0x00010000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID16___S 16 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID16__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID16__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID15___M 0x00008000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID15___S 15 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID15__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID15__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID14___M 0x00004000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID14___S 14 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID14__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID14__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID13___M 0x00002000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID13___S 13 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID13__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID13__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID12___M 0x00001000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID12___S 12 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID12__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID12__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID11___M 0x00000800 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID11___S 11 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID11__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID11__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID10___M 0x00000400 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID10___S 10 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID10__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID10__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID9___M 0x00000200 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID9___S 9 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID9__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID9__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID8___M 0x00000100 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID8___S 8 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID8__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID8__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID7___M 0x00000080 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID7___S 7 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID7__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID7__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID6___M 0x00000040 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID6___S 6 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID6__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID6__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID5___M 0x00000020 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID5___S 5 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID5__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID5__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID4___M 0x00000010 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID4___S 4 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID4__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID4__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID3___M 0x00000008 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID3___S 3 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID3__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID3__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID2___M 0x00000004 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID2___S 2 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID2__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID2__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID1___M 0x00000002 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID1___S 1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID1__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID1__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID0___M 0x00000001 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID0___S 0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID0__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0__TLVID0__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK0___S 0 + +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1 (0x00BB2084) +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID63___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID62___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID61___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID60___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID59___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID58___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID57___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID56___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID55___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID54___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID53___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID52___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID51___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID50___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID49___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID48___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID47___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID46___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID45___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID44___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID43___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID42___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID41___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID40___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID39___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID38___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID37___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID36___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID35___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID34___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID33___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID32___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID63___M 0x80000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID63___S 31 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID63__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID63__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID62___M 0x40000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID62___S 30 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID62__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID62__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID61___M 0x20000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID61___S 29 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID61__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID61__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID60___M 0x10000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID60___S 28 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID60__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID60__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID59___M 0x08000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID59___S 27 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID59__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID59__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID58___M 0x04000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID58___S 26 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID58__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID58__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID57___M 0x02000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID57___S 25 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID57__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID57__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID56___M 0x01000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID56___S 24 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID56__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID56__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID55___M 0x00800000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID55___S 23 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID55__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID55__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID54___M 0x00400000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID54___S 22 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID54__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID54__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID53___M 0x00200000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID53___S 21 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID53__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID53__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID52___M 0x00100000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID52___S 20 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID52__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID52__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID51___M 0x00080000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID51___S 19 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID51__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID51__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID50___M 0x00040000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID50___S 18 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID50__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID50__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID49___M 0x00020000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID49___S 17 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID49__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID49__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID48___M 0x00010000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID48___S 16 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID48__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID48__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID47___M 0x00008000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID47___S 15 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID47__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID47__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID46___M 0x00004000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID46___S 14 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID46__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID46__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID45___M 0x00002000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID45___S 13 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID45__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID45__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID44___M 0x00001000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID44___S 12 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID44__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID44__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID43___M 0x00000800 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID43___S 11 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID43__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID43__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID42___M 0x00000400 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID42___S 10 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID42__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID42__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID41___M 0x00000200 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID41___S 9 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID41__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID41__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID40___M 0x00000100 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID40___S 8 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID40__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID40__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID39___M 0x00000080 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID39___S 7 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID39__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID39__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID38___M 0x00000040 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID38___S 6 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID38__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID38__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID37___M 0x00000020 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID37___S 5 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID37__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID37__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID36___M 0x00000010 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID36___S 4 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID36__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID36__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID35___M 0x00000008 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID35___S 3 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID35__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID35__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID34___M 0x00000004 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID34___S 2 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID34__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID34__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID33___M 0x00000002 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID33___S 1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID33__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID33__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID32___M 0x00000001 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID32___S 0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID32__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1__TLVID32__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK1___S 0 + +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2 (0x00BB2088) +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID95___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID94___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID93___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID92___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID91___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID90___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID89___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID88___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID87___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID86___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID85___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID84___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID83___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID82___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID81___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID80___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID79___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID78___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID77___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID76___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID75___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID74___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID73___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID72___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID71___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID70___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID69___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID68___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID67___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID66___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID65___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID64___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID95___M 0x80000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID95___S 31 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID95__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID95__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID94___M 0x40000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID94___S 30 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID94__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID94__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID93___M 0x20000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID93___S 29 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID93__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID93__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID92___M 0x10000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID92___S 28 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID92__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID92__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID91___M 0x08000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID91___S 27 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID91__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID91__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID90___M 0x04000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID90___S 26 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID90__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID90__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID89___M 0x02000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID89___S 25 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID89__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID89__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID88___M 0x01000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID88___S 24 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID88__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID88__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID87___M 0x00800000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID87___S 23 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID87__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID87__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID86___M 0x00400000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID86___S 22 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID86__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID86__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID85___M 0x00200000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID85___S 21 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID85__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID85__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID84___M 0x00100000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID84___S 20 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID84__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID84__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID83___M 0x00080000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID83___S 19 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID83__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID83__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID82___M 0x00040000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID82___S 18 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID82__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID82__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID81___M 0x00020000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID81___S 17 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID81__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID81__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID80___M 0x00010000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID80___S 16 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID80__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID80__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID79___M 0x00008000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID79___S 15 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID79__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID79__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID78___M 0x00004000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID78___S 14 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID78__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID78__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID77___M 0x00002000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID77___S 13 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID77__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID77__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID76___M 0x00001000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID76___S 12 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID76__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID76__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID75___M 0x00000800 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID75___S 11 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID75__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID75__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID74___M 0x00000400 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID74___S 10 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID74__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID74__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID73___M 0x00000200 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID73___S 9 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID73__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID73__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID72___M 0x00000100 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID72___S 8 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID72__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID72__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID71___M 0x00000080 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID71___S 7 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID71__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID71__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID70___M 0x00000040 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID70___S 6 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID70__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID70__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID69___M 0x00000020 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID69___S 5 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID69__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID69__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID68___M 0x00000010 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID68___S 4 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID68__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID68__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID67___M 0x00000008 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID67___S 3 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID67__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID67__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID66___M 0x00000004 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID66___S 2 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID66__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID66__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID65___M 0x00000002 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID65___S 1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID65__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID65__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID64___M 0x00000001 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID64___S 0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID64__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2__TLVID64__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK2___S 0 + +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3 (0x00BB208C) +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID127___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID126___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID125___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID124___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID123___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID122___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID121___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID120___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID119___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID118___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID117___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID116___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID115___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID114___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID113___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID112___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID111___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID110___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID109___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID108___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID107___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID106___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID105___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID104___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID103___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID102___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID101___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID100___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID99___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID98___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID97___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID96___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID127___M 0x80000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID127___S 31 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID127__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID127__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID126___M 0x40000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID126___S 30 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID126__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID126__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID125___M 0x20000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID125___S 29 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID125__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID125__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID124___M 0x10000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID124___S 28 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID124__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID124__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID123___M 0x08000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID123___S 27 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID123__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID123__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID122___M 0x04000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID122___S 26 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID122__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID122__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID121___M 0x02000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID121___S 25 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID121__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID121__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID120___M 0x01000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID120___S 24 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID120__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID120__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID119___M 0x00800000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID119___S 23 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID119__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID119__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID118___M 0x00400000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID118___S 22 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID118__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID118__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID117___M 0x00200000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID117___S 21 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID117__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID117__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID116___M 0x00100000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID116___S 20 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID116__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID116__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID115___M 0x00080000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID115___S 19 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID115__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID115__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID114___M 0x00040000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID114___S 18 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID114__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID114__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID113___M 0x00020000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID113___S 17 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID113__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID113__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID112___M 0x00010000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID112___S 16 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID112__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID112__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID111___M 0x00008000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID111___S 15 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID111__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID111__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID110___M 0x00004000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID110___S 14 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID110__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID110__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID109___M 0x00002000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID109___S 13 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID109__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID109__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID108___M 0x00001000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID108___S 12 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID108__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID108__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID107___M 0x00000800 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID107___S 11 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID107__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID107__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID106___M 0x00000400 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID106___S 10 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID106__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID106__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID105___M 0x00000200 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID105___S 9 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID105__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID105__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID104___M 0x00000100 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID104___S 8 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID104__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID104__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID103___M 0x00000080 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID103___S 7 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID103__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID103__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID102___M 0x00000040 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID102___S 6 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID102__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID102__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID101___M 0x00000020 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID101___S 5 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID101__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID101__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID100___M 0x00000010 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID100___S 4 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID100__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID100__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID99___M 0x00000008 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID99___S 3 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID99__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID99__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID98___M 0x00000004 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID98___S 2 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID98__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID98__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID97___M 0x00000002 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID97___S 1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID97__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID97__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID96___M 0x00000001 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID96___S 0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID96__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3__TLVID96__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK3___S 0 + +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4 (0x00BB2090) +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID159___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID158___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID157___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID156___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID155___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID154___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID153___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID152___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID151___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID150___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID149___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID148___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID147___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID146___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID145___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID144___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID143___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID142___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID141___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID140___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID139___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID138___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID137___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID136___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID135___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID134___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID133___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID132___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID131___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID130___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID129___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID128___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID159___M 0x80000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID159___S 31 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID159__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID159__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID158___M 0x40000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID158___S 30 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID158__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID158__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID157___M 0x20000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID157___S 29 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID157__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID157__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID156___M 0x10000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID156___S 28 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID156__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID156__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID155___M 0x08000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID155___S 27 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID155__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID155__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID154___M 0x04000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID154___S 26 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID154__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID154__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID153___M 0x02000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID153___S 25 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID153__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID153__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID152___M 0x01000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID152___S 24 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID152__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID152__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID151___M 0x00800000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID151___S 23 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID151__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID151__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID150___M 0x00400000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID150___S 22 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID150__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID150__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID149___M 0x00200000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID149___S 21 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID149__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID149__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID148___M 0x00100000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID148___S 20 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID148__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID148__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID147___M 0x00080000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID147___S 19 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID147__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID147__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID146___M 0x00040000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID146___S 18 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID146__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID146__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID145___M 0x00020000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID145___S 17 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID145__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID145__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID144___M 0x00010000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID144___S 16 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID144__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID144__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID143___M 0x00008000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID143___S 15 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID143__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID143__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID142___M 0x00004000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID142___S 14 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID142__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID142__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID141___M 0x00002000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID141___S 13 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID141__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID141__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID140___M 0x00001000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID140___S 12 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID140__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID140__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID139___M 0x00000800 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID139___S 11 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID139__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID139__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID138___M 0x00000400 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID138___S 10 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID138__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID138__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID137___M 0x00000200 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID137___S 9 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID137__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID137__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID136___M 0x00000100 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID136___S 8 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID136__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID136__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID135___M 0x00000080 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID135___S 7 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID135__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID135__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID134___M 0x00000040 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID134___S 6 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID134__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID134__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID133___M 0x00000020 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID133___S 5 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID133__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID133__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID132___M 0x00000010 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID132___S 4 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID132__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID132__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID131___M 0x00000008 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID131___S 3 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID131__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID131__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID130___M 0x00000004 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID130___S 2 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID130__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID130__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID129___M 0x00000002 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID129___S 1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID129__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID129__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID128___M 0x00000001 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID128___S 0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID128__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4__TLVID128__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK4___S 0 + +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5 (0x00BB2094) +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID191___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID190___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID189___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID188___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID187___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID186___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID185___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID184___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID183___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID182___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID181___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID180___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID179___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID178___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID177___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID176___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID175___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID174___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID173___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID172___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID171___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID170___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID169___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID168___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID167___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID166___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID165___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID164___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID163___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID162___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID161___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID160___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID191___M 0x80000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID191___S 31 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID191__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID191__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID190___M 0x40000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID190___S 30 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID190__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID190__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID189___M 0x20000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID189___S 29 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID189__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID189__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID188___M 0x10000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID188___S 28 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID188__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID188__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID187___M 0x08000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID187___S 27 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID187__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID187__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID186___M 0x04000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID186___S 26 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID186__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID186__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID185___M 0x02000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID185___S 25 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID185__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID185__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID184___M 0x01000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID184___S 24 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID184__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID184__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID183___M 0x00800000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID183___S 23 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID183__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID183__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID182___M 0x00400000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID182___S 22 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID182__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID182__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID181___M 0x00200000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID181___S 21 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID181__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID181__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID180___M 0x00100000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID180___S 20 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID180__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID180__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID179___M 0x00080000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID179___S 19 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID179__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID179__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID178___M 0x00040000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID178___S 18 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID178__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID178__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID177___M 0x00020000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID177___S 17 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID177__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID177__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID176___M 0x00010000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID176___S 16 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID176__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID176__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID175___M 0x00008000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID175___S 15 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID175__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID175__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID174___M 0x00004000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID174___S 14 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID174__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID174__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID173___M 0x00002000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID173___S 13 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID173__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID173__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID172___M 0x00001000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID172___S 12 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID172__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID172__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID171___M 0x00000800 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID171___S 11 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID171__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID171__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID170___M 0x00000400 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID170___S 10 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID170__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID170__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID169___M 0x00000200 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID169___S 9 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID169__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID169__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID168___M 0x00000100 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID168___S 8 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID168__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID168__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID167___M 0x00000080 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID167___S 7 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID167__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID167__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID166___M 0x00000040 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID166___S 6 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID166__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID166__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID165___M 0x00000020 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID165___S 5 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID165__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID165__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID164___M 0x00000010 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID164___S 4 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID164__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID164__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID163___M 0x00000008 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID163___S 3 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID163__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID163__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID162___M 0x00000004 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID162___S 2 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID162__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID162__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID161___M 0x00000002 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID161___S 1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID161__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID161__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID160___M 0x00000001 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID160___S 0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID160__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5__TLVID160__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK5___S 0 + +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6 (0x00BB2098) +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID223___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID222___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID221___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID220___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID219___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID218___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID217___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID216___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID215___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID214___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID213___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID212___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID211___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID210___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID209___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID208___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID207___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID206___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID205___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID204___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID203___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID202___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID201___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID200___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID199___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID198___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID197___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID196___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID195___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID194___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID193___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID192___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID223___M 0x80000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID223___S 31 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID223__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID223__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID222___M 0x40000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID222___S 30 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID222__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID222__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID221___M 0x20000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID221___S 29 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID221__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID221__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID220___M 0x10000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID220___S 28 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID220__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID220__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID219___M 0x08000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID219___S 27 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID219__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID219__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID218___M 0x04000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID218___S 26 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID218__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID218__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID217___M 0x02000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID217___S 25 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID217__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID217__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID216___M 0x01000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID216___S 24 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID216__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID216__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID215___M 0x00800000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID215___S 23 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID215__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID215__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID214___M 0x00400000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID214___S 22 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID214__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID214__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID213___M 0x00200000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID213___S 21 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID213__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID213__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID212___M 0x00100000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID212___S 20 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID212__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID212__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID211___M 0x00080000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID211___S 19 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID211__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID211__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID210___M 0x00040000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID210___S 18 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID210__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID210__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID209___M 0x00020000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID209___S 17 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID209__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID209__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID208___M 0x00010000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID208___S 16 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID208__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID208__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID207___M 0x00008000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID207___S 15 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID207__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID207__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID206___M 0x00004000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID206___S 14 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID206__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID206__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID205___M 0x00002000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID205___S 13 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID205__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID205__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID204___M 0x00001000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID204___S 12 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID204__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID204__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID203___M 0x00000800 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID203___S 11 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID203__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID203__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID202___M 0x00000400 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID202___S 10 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID202__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID202__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID201___M 0x00000200 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID201___S 9 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID201__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID201__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID200___M 0x00000100 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID200___S 8 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID200__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID200__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID199___M 0x00000080 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID199___S 7 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID199__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID199__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID198___M 0x00000040 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID198___S 6 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID198__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID198__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID197___M 0x00000020 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID197___S 5 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID197__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID197__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID196___M 0x00000010 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID196___S 4 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID196__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID196__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID195___M 0x00000008 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID195___S 3 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID195__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID195__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID194___M 0x00000004 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID194___S 2 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID194__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID194__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID193___M 0x00000002 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID193___S 1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID193__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID193__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID192___M 0x00000001 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID192___S 0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID192__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6__TLVID192__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK6___S 0 + +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7 (0x00BB209C) +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID255___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID254___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID253___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID252___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID251___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID250___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID249___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID248___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID247___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID246___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID245___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID244___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID243___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID242___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID241___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID240___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID239___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID238___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID237___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID236___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID235___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID234___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID233___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID232___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID231___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID230___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID229___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID228___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID227___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID226___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID225___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID224___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID255___M 0x80000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID255___S 31 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID255__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID255__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID254___M 0x40000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID254___S 30 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID254__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID254__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID253___M 0x20000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID253___S 29 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID253__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID253__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID252___M 0x10000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID252___S 28 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID252__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID252__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID251___M 0x08000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID251___S 27 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID251__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID251__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID250___M 0x04000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID250___S 26 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID250__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID250__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID249___M 0x02000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID249___S 25 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID249__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID249__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID248___M 0x01000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID248___S 24 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID248__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID248__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID247___M 0x00800000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID247___S 23 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID247__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID247__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID246___M 0x00400000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID246___S 22 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID246__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID246__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID245___M 0x00200000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID245___S 21 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID245__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID245__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID244___M 0x00100000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID244___S 20 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID244__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID244__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID243___M 0x00080000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID243___S 19 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID243__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID243__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID242___M 0x00040000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID242___S 18 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID242__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID242__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID241___M 0x00020000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID241___S 17 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID241__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID241__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID240___M 0x00010000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID240___S 16 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID240__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID240__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID239___M 0x00008000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID239___S 15 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID239__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID239__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID238___M 0x00004000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID238___S 14 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID238__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID238__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID237___M 0x00002000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID237___S 13 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID237__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID237__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID236___M 0x00001000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID236___S 12 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID236__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID236__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID235___M 0x00000800 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID235___S 11 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID235__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID235__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID234___M 0x00000400 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID234___S 10 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID234__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID234__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID233___M 0x00000200 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID233___S 9 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID233__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID233__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID232___M 0x00000100 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID232___S 8 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID232__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID232__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID231___M 0x00000080 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID231___S 7 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID231__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID231__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID230___M 0x00000040 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID230___S 6 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID230__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID230__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID229___M 0x00000020 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID229___S 5 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID229__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID229__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID228___M 0x00000010 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID228___S 4 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID228__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID228__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID227___M 0x00000008 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID227___S 3 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID227__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID227__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID226___M 0x00000004 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID226___S 2 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID226__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID226__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID225___M 0x00000002 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID225___S 1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID225__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID225__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID224___M 0x00000001 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID224___S 0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID224__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7__TLVID224__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK7___S 0 + +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8 (0x00BB20A0) +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID287___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID286___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID285___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID284___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID283___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID282___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID281___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID280___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID279___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID278___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID277___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID276___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID275___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID274___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID273___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID272___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID271___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID270___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID269___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID268___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID267___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID266___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID265___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID264___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID263___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID262___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID261___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID260___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID259___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID258___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID257___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID256___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID287___M 0x80000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID287___S 31 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID287__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID287__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID286___M 0x40000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID286___S 30 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID286__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID286__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID285___M 0x20000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID285___S 29 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID285__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID285__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID284___M 0x10000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID284___S 28 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID284__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID284__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID283___M 0x08000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID283___S 27 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID283__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID283__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID282___M 0x04000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID282___S 26 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID282__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID282__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID281___M 0x02000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID281___S 25 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID281__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID281__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID280___M 0x01000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID280___S 24 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID280__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID280__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID279___M 0x00800000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID279___S 23 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID279__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID279__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID278___M 0x00400000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID278___S 22 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID278__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID278__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID277___M 0x00200000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID277___S 21 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID277__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID277__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID276___M 0x00100000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID276___S 20 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID276__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID276__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID275___M 0x00080000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID275___S 19 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID275__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID275__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID274___M 0x00040000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID274___S 18 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID274__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID274__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID273___M 0x00020000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID273___S 17 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID273__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID273__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID272___M 0x00010000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID272___S 16 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID272__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID272__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID271___M 0x00008000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID271___S 15 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID271__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID271__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID270___M 0x00004000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID270___S 14 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID270__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID270__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID269___M 0x00002000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID269___S 13 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID269__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID269__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID268___M 0x00001000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID268___S 12 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID268__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID268__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID267___M 0x00000800 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID267___S 11 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID267__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID267__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID266___M 0x00000400 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID266___S 10 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID266__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID266__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID265___M 0x00000200 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID265___S 9 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID265__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID265__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID264___M 0x00000100 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID264___S 8 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID264__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID264__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID263___M 0x00000080 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID263___S 7 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID263__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID263__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID262___M 0x00000040 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID262___S 6 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID262__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID262__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID261___M 0x00000020 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID261___S 5 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID261__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID261__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID260___M 0x00000010 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID260___S 4 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID260__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID260__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID259___M 0x00000008 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID259___S 3 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID259__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID259__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID258___M 0x00000004 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID258___S 2 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID258__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID258__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID257___M 0x00000002 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID257___S 1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID257__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID257__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID256___M 0x00000001 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID256___S 0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID256__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8__TLVID256__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK8___S 0 + +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9 (0x00BB20A4) +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID319___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID318___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID317___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID316___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID315___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID314___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID313___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID312___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID311___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID310___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID309___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID308___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID307___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID306___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID305___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID304___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID303___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID302___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID301___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID300___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID299___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID298___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID297___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID296___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID295___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID294___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID293___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID292___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID291___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID290___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID289___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID288___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID319___M 0x80000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID319___S 31 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID319__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID319__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID318___M 0x40000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID318___S 30 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID318__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID318__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID317___M 0x20000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID317___S 29 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID317__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID317__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID316___M 0x10000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID316___S 28 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID316__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID316__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID315___M 0x08000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID315___S 27 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID315__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID315__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID314___M 0x04000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID314___S 26 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID314__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID314__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID313___M 0x02000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID313___S 25 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID313__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID313__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID312___M 0x01000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID312___S 24 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID312__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID312__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID311___M 0x00800000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID311___S 23 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID311__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID311__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID310___M 0x00400000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID310___S 22 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID310__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID310__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID309___M 0x00200000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID309___S 21 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID309__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID309__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID308___M 0x00100000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID308___S 20 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID308__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID308__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID307___M 0x00080000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID307___S 19 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID307__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID307__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID306___M 0x00040000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID306___S 18 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID306__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID306__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID305___M 0x00020000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID305___S 17 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID305__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID305__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID304___M 0x00010000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID304___S 16 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID304__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID304__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID303___M 0x00008000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID303___S 15 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID303__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID303__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID302___M 0x00004000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID302___S 14 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID302__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID302__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID301___M 0x00002000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID301___S 13 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID301__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID301__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID300___M 0x00001000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID300___S 12 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID300__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID300__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID299___M 0x00000800 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID299___S 11 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID299__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID299__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID298___M 0x00000400 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID298___S 10 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID298__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID298__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID297___M 0x00000200 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID297___S 9 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID297__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID297__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID296___M 0x00000100 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID296___S 8 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID296__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID296__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID295___M 0x00000080 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID295___S 7 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID295__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID295__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID294___M 0x00000040 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID294___S 6 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID294__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID294__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID293___M 0x00000020 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID293___S 5 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID293__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID293__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID292___M 0x00000010 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID292___S 4 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID292__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID292__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID291___M 0x00000008 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID291___S 3 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID291__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID291__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID290___M 0x00000004 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID290___S 2 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID290__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID290__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID289___M 0x00000002 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID289___S 1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID289__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID289__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID288___M 0x00000001 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID288___S 0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID288__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9__TLVID288__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK9___S 0 + +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10 (0x00BB20A8) +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID351___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID350___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID349___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID348___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID347___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID346___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID345___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID344___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID343___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID342___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID341___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID340___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID339___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID338___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID337___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID336___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID335___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID334___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID333___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID332___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID331___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID330___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID329___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID328___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID327___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID326___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID325___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID324___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID323___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID322___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID321___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID320___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID351___M 0x80000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID351___S 31 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID351__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID351__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID350___M 0x40000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID350___S 30 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID350__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID350__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID349___M 0x20000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID349___S 29 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID349__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID349__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID348___M 0x10000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID348___S 28 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID348__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID348__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID347___M 0x08000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID347___S 27 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID347__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID347__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID346___M 0x04000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID346___S 26 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID346__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID346__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID345___M 0x02000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID345___S 25 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID345__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID345__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID344___M 0x01000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID344___S 24 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID344__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID344__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID343___M 0x00800000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID343___S 23 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID343__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID343__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID342___M 0x00400000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID342___S 22 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID342__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID342__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID341___M 0x00200000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID341___S 21 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID341__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID341__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID340___M 0x00100000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID340___S 20 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID340__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID340__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID339___M 0x00080000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID339___S 19 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID339__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID339__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID338___M 0x00040000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID338___S 18 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID338__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID338__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID337___M 0x00020000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID337___S 17 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID337__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID337__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID336___M 0x00010000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID336___S 16 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID336__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID336__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID335___M 0x00008000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID335___S 15 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID335__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID335__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID334___M 0x00004000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID334___S 14 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID334__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID334__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID333___M 0x00002000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID333___S 13 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID333__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID333__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID332___M 0x00001000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID332___S 12 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID332__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID332__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID331___M 0x00000800 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID331___S 11 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID331__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID331__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID330___M 0x00000400 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID330___S 10 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID330__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID330__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID329___M 0x00000200 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID329___S 9 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID329__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID329__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID328___M 0x00000100 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID328___S 8 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID328__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID328__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID327___M 0x00000080 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID327___S 7 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID327__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID327__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID326___M 0x00000040 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID326___S 6 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID326__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID326__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID325___M 0x00000020 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID325___S 5 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID325__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID325__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID324___M 0x00000010 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID324___S 4 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID324__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID324__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID323___M 0x00000008 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID323___S 3 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID323__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID323__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID322___M 0x00000004 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID322___S 2 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID322__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID322__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID321___M 0x00000002 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID321___S 1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID321__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID321__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID320___M 0x00000001 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID320___S 0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID320__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10__TLVID320__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK10___S 0 + +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11 (0x00BB20AC) +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID383___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID382___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID381___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID380___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID379___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID378___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID377___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID376___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID375___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID374___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID373___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID372___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID371___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID370___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID369___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID368___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID367___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID366___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID365___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID364___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID363___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID362___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID361___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID360___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID359___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID358___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID357___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID356___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID355___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID354___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID353___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID352___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID383___M 0x80000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID383___S 31 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID383__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID383__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID382___M 0x40000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID382___S 30 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID382__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID382__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID381___M 0x20000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID381___S 29 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID381__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID381__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID380___M 0x10000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID380___S 28 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID380__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID380__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID379___M 0x08000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID379___S 27 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID379__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID379__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID378___M 0x04000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID378___S 26 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID378__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID378__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID377___M 0x02000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID377___S 25 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID377__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID377__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID376___M 0x01000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID376___S 24 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID376__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID376__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID375___M 0x00800000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID375___S 23 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID375__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID375__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID374___M 0x00400000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID374___S 22 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID374__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID374__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID373___M 0x00200000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID373___S 21 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID373__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID373__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID372___M 0x00100000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID372___S 20 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID372__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID372__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID371___M 0x00080000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID371___S 19 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID371__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID371__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID370___M 0x00040000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID370___S 18 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID370__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID370__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID369___M 0x00020000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID369___S 17 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID369__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID369__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID368___M 0x00010000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID368___S 16 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID368__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID368__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID367___M 0x00008000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID367___S 15 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID367__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID367__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID366___M 0x00004000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID366___S 14 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID366__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID366__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID365___M 0x00002000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID365___S 13 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID365__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID365__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID364___M 0x00001000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID364___S 12 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID364__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID364__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID363___M 0x00000800 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID363___S 11 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID363__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID363__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID362___M 0x00000400 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID362___S 10 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID362__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID362__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID361___M 0x00000200 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID361___S 9 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID361__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID361__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID360___M 0x00000100 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID360___S 8 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID360__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID360__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID359___M 0x00000080 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID359___S 7 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID359__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID359__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID358___M 0x00000040 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID358___S 6 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID358__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID358__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID357___M 0x00000020 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID357___S 5 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID357__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID357__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID356___M 0x00000010 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID356___S 4 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID356__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID356__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID355___M 0x00000008 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID355___S 3 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID355__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID355__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID354___M 0x00000004 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID354___S 2 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID354__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID354__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID353___M 0x00000002 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID353___S 1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID353__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID353__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID352___M 0x00000001 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID352___S 0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID352__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11__TLVID352__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK11___S 0 + +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12 (0x00BB20B0) +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID415___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID414___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID413___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID412___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID411___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID410___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID409___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID408___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID407___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID406___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID405___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID404___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID403___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID402___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID401___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID400___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID399___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID398___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID397___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID396___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID395___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID394___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID393___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID392___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID391___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID390___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID389___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID388___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID387___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID386___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID385___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID384___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID415___M 0x80000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID415___S 31 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID415__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID415__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID414___M 0x40000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID414___S 30 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID414__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID414__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID413___M 0x20000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID413___S 29 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID413__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID413__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID412___M 0x10000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID412___S 28 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID412__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID412__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID411___M 0x08000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID411___S 27 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID411__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID411__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID410___M 0x04000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID410___S 26 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID410__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID410__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID409___M 0x02000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID409___S 25 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID409__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID409__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID408___M 0x01000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID408___S 24 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID408__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID408__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID407___M 0x00800000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID407___S 23 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID407__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID407__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID406___M 0x00400000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID406___S 22 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID406__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID406__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID405___M 0x00200000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID405___S 21 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID405__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID405__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID404___M 0x00100000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID404___S 20 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID404__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID404__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID403___M 0x00080000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID403___S 19 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID403__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID403__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID402___M 0x00040000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID402___S 18 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID402__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID402__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID401___M 0x00020000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID401___S 17 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID401__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID401__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID400___M 0x00010000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID400___S 16 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID400__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID400__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID399___M 0x00008000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID399___S 15 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID399__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID399__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID398___M 0x00004000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID398___S 14 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID398__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID398__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID397___M 0x00002000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID397___S 13 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID397__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID397__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID396___M 0x00001000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID396___S 12 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID396__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID396__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID395___M 0x00000800 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID395___S 11 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID395__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID395__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID394___M 0x00000400 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID394___S 10 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID394__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID394__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID393___M 0x00000200 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID393___S 9 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID393__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID393__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID392___M 0x00000100 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID392___S 8 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID392__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID392__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID391___M 0x00000080 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID391___S 7 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID391__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID391__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID390___M 0x00000040 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID390___S 6 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID390__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID390__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID389___M 0x00000020 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID389___S 5 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID389__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID389__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID388___M 0x00000010 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID388___S 4 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID388__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID388__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID387___M 0x00000008 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID387___S 3 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID387__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID387__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID386___M 0x00000004 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID386___S 2 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID386__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID386__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID385___M 0x00000002 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID385___S 1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID385__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID385__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID384___M 0x00000001 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID384___S 0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID384__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12__TLVID384__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK12___S 0 + +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13 (0x00BB20B4) +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID447___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID446___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID445___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID444___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID443___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID442___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID441___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID440___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID439___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID438___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID437___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID436___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID435___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID434___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID433___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID432___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID431___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID430___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID429___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID428___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID427___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID426___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID425___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID424___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID423___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID422___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID421___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID420___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID419___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID418___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID417___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID416___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID447___M 0x80000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID447___S 31 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID447__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID447__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID446___M 0x40000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID446___S 30 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID446__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID446__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID445___M 0x20000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID445___S 29 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID445__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID445__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID444___M 0x10000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID444___S 28 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID444__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID444__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID443___M 0x08000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID443___S 27 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID443__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID443__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID442___M 0x04000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID442___S 26 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID442__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID442__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID441___M 0x02000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID441___S 25 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID441__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID441__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID440___M 0x01000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID440___S 24 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID440__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID440__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID439___M 0x00800000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID439___S 23 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID439__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID439__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID438___M 0x00400000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID438___S 22 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID438__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID438__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID437___M 0x00200000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID437___S 21 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID437__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID437__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID436___M 0x00100000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID436___S 20 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID436__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID436__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID435___M 0x00080000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID435___S 19 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID435__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID435__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID434___M 0x00040000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID434___S 18 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID434__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID434__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID433___M 0x00020000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID433___S 17 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID433__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID433__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID432___M 0x00010000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID432___S 16 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID432__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID432__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID431___M 0x00008000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID431___S 15 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID431__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID431__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID430___M 0x00004000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID430___S 14 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID430__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID430__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID429___M 0x00002000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID429___S 13 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID429__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID429__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID428___M 0x00001000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID428___S 12 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID428__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID428__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID427___M 0x00000800 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID427___S 11 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID427__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID427__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID426___M 0x00000400 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID426___S 10 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID426__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID426__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID425___M 0x00000200 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID425___S 9 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID425__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID425__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID424___M 0x00000100 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID424___S 8 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID424__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID424__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID423___M 0x00000080 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID423___S 7 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID423__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID423__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID422___M 0x00000040 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID422___S 6 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID422__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID422__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID421___M 0x00000020 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID421___S 5 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID421__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID421__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID420___M 0x00000010 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID420___S 4 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID420__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID420__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID419___M 0x00000008 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID419___S 3 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID419__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID419__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID418___M 0x00000004 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID418___S 2 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID418__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID418__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID417___M 0x00000002 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID417___S 1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID417__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID417__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID416___M 0x00000001 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID416___S 0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID416__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13__TLVID416__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK13___S 0 + +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14 (0x00BB20B8) +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID479___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID478___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID477___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID476___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID475___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID474___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID473___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID472___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID471___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID470___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID469___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID468___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID467___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID466___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID465___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID464___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID463___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID462___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID461___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID460___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID459___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID458___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID457___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID456___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID455___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID454___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID453___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID452___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID451___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID450___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID449___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID448___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID479___M 0x80000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID479___S 31 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID479__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID479__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID478___M 0x40000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID478___S 30 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID478__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID478__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID477___M 0x20000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID477___S 29 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID477__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID477__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID476___M 0x10000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID476___S 28 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID476__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID476__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID475___M 0x08000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID475___S 27 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID475__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID475__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID474___M 0x04000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID474___S 26 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID474__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID474__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID473___M 0x02000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID473___S 25 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID473__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID473__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID472___M 0x01000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID472___S 24 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID472__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID472__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID471___M 0x00800000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID471___S 23 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID471__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID471__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID470___M 0x00400000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID470___S 22 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID470__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID470__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID469___M 0x00200000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID469___S 21 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID469__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID469__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID468___M 0x00100000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID468___S 20 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID468__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID468__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID467___M 0x00080000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID467___S 19 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID467__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID467__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID466___M 0x00040000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID466___S 18 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID466__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID466__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID465___M 0x00020000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID465___S 17 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID465__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID465__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID464___M 0x00010000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID464___S 16 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID464__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID464__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID463___M 0x00008000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID463___S 15 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID463__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID463__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID462___M 0x00004000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID462___S 14 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID462__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID462__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID461___M 0x00002000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID461___S 13 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID461__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID461__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID460___M 0x00001000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID460___S 12 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID460__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID460__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID459___M 0x00000800 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID459___S 11 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID459__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID459__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID458___M 0x00000400 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID458___S 10 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID458__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID458__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID457___M 0x00000200 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID457___S 9 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID457__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID457__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID456___M 0x00000100 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID456___S 8 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID456__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID456__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID455___M 0x00000080 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID455___S 7 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID455__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID455__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID454___M 0x00000040 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID454___S 6 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID454__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID454__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID453___M 0x00000020 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID453___S 5 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID453__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID453__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID452___M 0x00000010 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID452___S 4 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID452__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID452__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID451___M 0x00000008 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID451___S 3 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID451__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID451__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID450___M 0x00000004 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID450___S 2 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID450__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID450__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID449___M 0x00000002 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID449___S 1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID449__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID449__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID448___M 0x00000001 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID448___S 0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID448__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14__TLVID448__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK14___S 0 + +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15 (0x00BB20BC) +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15___RWC QCSR_REG_RW +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15___POR 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID511___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID510___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID509___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID508___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID507___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID506___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID505___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID504___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID503___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID502___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID501___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID500___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID499___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID498___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID497___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID496___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID495___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID494___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID493___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID492___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID491___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID490___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID489___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID488___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID487___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID486___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID485___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID484___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID483___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID482___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID481___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID480___POR 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID511___M 0x80000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID511___S 31 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID511__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID511__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID510___M 0x40000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID510___S 30 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID510__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID510__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID509___M 0x20000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID509___S 29 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID509__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID509__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID508___M 0x10000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID508___S 28 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID508__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID508__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID507___M 0x08000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID507___S 27 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID507__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID507__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID506___M 0x04000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID506___S 26 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID506__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID506__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID505___M 0x02000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID505___S 25 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID505__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID505__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID504___M 0x01000000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID504___S 24 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID504__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID504__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID503___M 0x00800000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID503___S 23 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID503__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID503__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID502___M 0x00400000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID502___S 22 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID502__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID502__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID501___M 0x00200000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID501___S 21 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID501__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID501__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID500___M 0x00100000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID500___S 20 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID500__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID500__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID499___M 0x00080000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID499___S 19 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID499__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID499__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID498___M 0x00040000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID498___S 18 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID498__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID498__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID497___M 0x00020000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID497___S 17 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID497__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID497__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID496___M 0x00010000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID496___S 16 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID496__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID496__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID495___M 0x00008000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID495___S 15 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID495__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID495__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID494___M 0x00004000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID494___S 14 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID494__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID494__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID493___M 0x00002000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID493___S 13 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID493__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID493__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID492___M 0x00001000 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID492___S 12 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID492__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID492__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID491___M 0x00000800 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID491___S 11 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID491__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID491__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID490___M 0x00000400 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID490___S 10 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID490__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID490__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID489___M 0x00000200 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID489___S 9 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID489__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID489__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID488___M 0x00000100 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID488___S 8 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID488__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID488__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID487___M 0x00000080 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID487___S 7 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID487__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID487__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID486___M 0x00000040 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID486___S 6 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID486__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID486__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID485___M 0x00000020 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID485___S 5 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID485__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID485__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID484___M 0x00000010 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID484___S 4 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID484__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID484__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID483___M 0x00000008 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID483___S 3 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID483__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID483__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID482___M 0x00000004 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID482___S 2 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID482__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID482__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID481___M 0x00000002 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID481___S 1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID481__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID481__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID480___M 0x00000001 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID480___S 0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID480__HDRPLUSDATA 0x0 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15__TLVID480__HDRONLY 0x1 +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15___M 0xFFFFFFFF +#define DBG_TLV_MACTLV_FILTER_CFG_TLVID_HDRONLY_MASK15___S 0 + +#define DBG_TLV_CS_ITCTL (0x00BB2F00) +#define DBG_TLV_CS_ITCTL___RWC QCSR_REG_RO +#define DBG_TLV_CS_ITCTL___POR 0x00000000 +#define DBG_TLV_CS_ITCTL__RFU___POR 0x00000000 +#define DBG_TLV_CS_ITCTL__RFU___M 0xFFFFFFFF +#define DBG_TLV_CS_ITCTL__RFU___S 0 +#define DBG_TLV_CS_ITCTL___M 0xFFFFFFFF +#define DBG_TLV_CS_ITCTL___S 0 + +#define DBG_TLV_CS_CLAIMSET (0x00BB2FA0) +#define DBG_TLV_CS_CLAIMSET___RWC QCSR_REG_RO +#define DBG_TLV_CS_CLAIMSET___POR 0x00000000 +#define DBG_TLV_CS_CLAIMSET__RFU___POR 0x00000000 +#define DBG_TLV_CS_CLAIMSET__RFU___M 0xFFFFFFFF +#define DBG_TLV_CS_CLAIMSET__RFU___S 0 +#define DBG_TLV_CS_CLAIMSET___M 0xFFFFFFFF +#define DBG_TLV_CS_CLAIMSET___S 0 + +#define DBG_TLV_CS_CLAIMCLR (0x00BB2FA4) +#define DBG_TLV_CS_CLAIMCLR___RWC QCSR_REG_RO +#define DBG_TLV_CS_CLAIMCLR___POR 0x00000000 +#define DBG_TLV_CS_CLAIMCLR__RFU___POR 0x00000000 +#define DBG_TLV_CS_CLAIMCLR__RFU___M 0xFFFFFFFF +#define DBG_TLV_CS_CLAIMCLR__RFU___S 0 +#define DBG_TLV_CS_CLAIMCLR___M 0xFFFFFFFF +#define DBG_TLV_CS_CLAIMCLR___S 0 + +#define DBG_TLV_CS_LOCKACCESS (0x00BB2FB0) +#define DBG_TLV_CS_LOCKACCESS___RWC QCSR_REG_RO +#define DBG_TLV_CS_LOCKACCESS___POR 0x00000000 +#define DBG_TLV_CS_LOCKACCESS__RFU___POR 0x00000000 +#define DBG_TLV_CS_LOCKACCESS__RFU___M 0xFFFFFFFF +#define DBG_TLV_CS_LOCKACCESS__RFU___S 0 +#define DBG_TLV_CS_LOCKACCESS___M 0xFFFFFFFF +#define DBG_TLV_CS_LOCKACCESS___S 0 + +#define DBG_TLV_CS_LOCKSTATUS (0x00BB2FB4) +#define DBG_TLV_CS_LOCKSTATUS___RWC QCSR_REG_RO +#define DBG_TLV_CS_LOCKSTATUS___POR 0x00000000 +#define DBG_TLV_CS_LOCKSTATUS__RFU___POR 0x00000000 +#define DBG_TLV_CS_LOCKSTATUS__RFU___M 0xFFFFFFFF +#define DBG_TLV_CS_LOCKSTATUS__RFU___S 0 +#define DBG_TLV_CS_LOCKSTATUS___M 0xFFFFFFFF +#define DBG_TLV_CS_LOCKSTATUS___S 0 + +#define DBG_TLV_CS_AUTHSTATUS (0x00BB2FB8) +#define DBG_TLV_CS_AUTHSTATUS___RWC QCSR_REG_RO +#define DBG_TLV_CS_AUTHSTATUS__SI___M 0x000000C0 +#define DBG_TLV_CS_AUTHSTATUS__SI___S 6 +#define DBG_TLV_CS_AUTHSTATUS__NSI___M 0x00000030 +#define DBG_TLV_CS_AUTHSTATUS__NSI___S 4 +#define DBG_TLV_CS_AUTHSTATUS__SNI___M 0x0000000C +#define DBG_TLV_CS_AUTHSTATUS__SNI___S 2 +#define DBG_TLV_CS_AUTHSTATUS__NSNI___M 0x00000003 +#define DBG_TLV_CS_AUTHSTATUS__NSNI___S 0 +#define DBG_TLV_CS_AUTHSTATUS___M 0x000000FF +#define DBG_TLV_CS_AUTHSTATUS___S 0 + +#define DBG_TLV_CS_DEVARCH (0x00BB2FBC) +#define DBG_TLV_CS_DEVARCH___RWC QCSR_REG_RO +#define DBG_TLV_CS_DEVARCH___POR 0x0E100000 +#define DBG_TLV_CS_DEVARCH__JEP106_CONT_CODE___POR 0x0 +#define DBG_TLV_CS_DEVARCH__JEP106_IDENT_CODE___POR 0x70 +#define DBG_TLV_CS_DEVARCH__PRESENT___POR 0x1 +#define DBG_TLV_CS_DEVARCH__REV___POR 0x0 +#define DBG_TLV_CS_DEVARCH__ARCHID___POR 0x0000 +#define DBG_TLV_CS_DEVARCH__JEP106_CONT_CODE___M 0xF0000000 +#define DBG_TLV_CS_DEVARCH__JEP106_CONT_CODE___S 28 +#define DBG_TLV_CS_DEVARCH__JEP106_IDENT_CODE___M 0x0FE00000 +#define DBG_TLV_CS_DEVARCH__JEP106_IDENT_CODE___S 21 +#define DBG_TLV_CS_DEVARCH__PRESENT___M 0x00100000 +#define DBG_TLV_CS_DEVARCH__PRESENT___S 20 +#define DBG_TLV_CS_DEVARCH__REV___M 0x000F0000 +#define DBG_TLV_CS_DEVARCH__REV___S 16 +#define DBG_TLV_CS_DEVARCH__ARCHID___M 0x0000FFFF +#define DBG_TLV_CS_DEVARCH__ARCHID___S 0 +#define DBG_TLV_CS_DEVARCH___M 0xFFFFFFFF +#define DBG_TLV_CS_DEVARCH___S 0 + +#define DBG_TLV_CS_DEVICEID (0x00BB2FC8) +#define DBG_TLV_CS_DEVICEID___RWC QCSR_REG_RO +#define DBG_TLV_CS_DEVICEID___POR 0x00000000 +#define DBG_TLV_CS_DEVICEID__RFU___POR 0x000000 +#define DBG_TLV_CS_DEVICEID__DEVID___POR 0x00 +#define DBG_TLV_CS_DEVICEID__RFU___M 0xFFFFFF00 +#define DBG_TLV_CS_DEVICEID__RFU___S 8 +#define DBG_TLV_CS_DEVICEID__DEVID___M 0x000000FF +#define DBG_TLV_CS_DEVICEID__DEVID___S 0 +#define DBG_TLV_CS_DEVICEID___M 0xFFFFFFFF +#define DBG_TLV_CS_DEVICEID___S 0 + +#define DBG_TLV_CS_DEVICETYPE (0x00BB2FCC) +#define DBG_TLV_CS_DEVICETYPE___RWC QCSR_REG_RO +#define DBG_TLV_CS_DEVICETYPE___POR 0x00000003 +#define DBG_TLV_CS_DEVICETYPE__RFU___POR 0x000000 +#define DBG_TLV_CS_DEVICETYPE__SUBTYPE___POR 0x0 +#define DBG_TLV_CS_DEVICETYPE__MAJTYPE___POR 0x3 +#define DBG_TLV_CS_DEVICETYPE__RFU___M 0xFFFFFF00 +#define DBG_TLV_CS_DEVICETYPE__RFU___S 8 +#define DBG_TLV_CS_DEVICETYPE__SUBTYPE___M 0x000000F0 +#define DBG_TLV_CS_DEVICETYPE__SUBTYPE___S 4 +#define DBG_TLV_CS_DEVICETYPE__MAJTYPE___M 0x0000000F +#define DBG_TLV_CS_DEVICETYPE__MAJTYPE___S 0 +#define DBG_TLV_CS_DEVICETYPE___M 0xFFFFFFFF +#define DBG_TLV_CS_DEVICETYPE___S 0 + +#define DBG_TLV_CS_PERIPHID4 (0x00BB2FD0) +#define DBG_TLV_CS_PERIPHID4___RWC QCSR_REG_RO +#define DBG_TLV_CS_PERIPHID4___POR 0x00000000 +#define DBG_TLV_CS_PERIPHID4__RFU___POR 0x000000 +#define DBG_TLV_CS_PERIPHID4__FIELD_4KB_COUNT___POR 0x0 +#define DBG_TLV_CS_PERIPHID4__JEP106_CONTINUATION___POR 0x0 +#define DBG_TLV_CS_PERIPHID4__RFU___M 0xFFFFFF00 +#define DBG_TLV_CS_PERIPHID4__RFU___S 8 +#define DBG_TLV_CS_PERIPHID4__FIELD_4KB_COUNT___M 0x000000F0 +#define DBG_TLV_CS_PERIPHID4__FIELD_4KB_COUNT___S 4 +#define DBG_TLV_CS_PERIPHID4__JEP106_CONTINUATION___M 0x0000000F +#define DBG_TLV_CS_PERIPHID4__JEP106_CONTINUATION___S 0 +#define DBG_TLV_CS_PERIPHID4___M 0xFFFFFFFF +#define DBG_TLV_CS_PERIPHID4___S 0 + +#define DBG_TLV_CS_PERIPHID5 (0x00BB2FD4) +#define DBG_TLV_CS_PERIPHID5___RWC QCSR_REG_RO +#define DBG_TLV_CS_PERIPHID5___POR 0x00000000 +#define DBG_TLV_CS_PERIPHID5__RFU___POR 0x00000000 +#define DBG_TLV_CS_PERIPHID5__RFU___M 0xFFFFFFFF +#define DBG_TLV_CS_PERIPHID5__RFU___S 0 +#define DBG_TLV_CS_PERIPHID5___M 0xFFFFFFFF +#define DBG_TLV_CS_PERIPHID5___S 0 + +#define DBG_TLV_CS_PERIPHID6 (0x00BB2FD8) +#define DBG_TLV_CS_PERIPHID6___RWC QCSR_REG_RO +#define DBG_TLV_CS_PERIPHID6___POR 0x00000000 +#define DBG_TLV_CS_PERIPHID6__RFU___POR 0x00000000 +#define DBG_TLV_CS_PERIPHID6__RFU___M 0xFFFFFFFF +#define DBG_TLV_CS_PERIPHID6__RFU___S 0 +#define DBG_TLV_CS_PERIPHID6___M 0xFFFFFFFF +#define DBG_TLV_CS_PERIPHID6___S 0 + +#define DBG_TLV_CS_PERIPHID7 (0x00BB2FDC) +#define DBG_TLV_CS_PERIPHID7___RWC QCSR_REG_RO +#define DBG_TLV_CS_PERIPHID7___POR 0x00000000 +#define DBG_TLV_CS_PERIPHID7__RFU___POR 0x00000000 +#define DBG_TLV_CS_PERIPHID7__RFU___M 0xFFFFFFFF +#define DBG_TLV_CS_PERIPHID7__RFU___S 0 +#define DBG_TLV_CS_PERIPHID7___M 0xFFFFFFFF +#define DBG_TLV_CS_PERIPHID7___S 0 + +#define DBG_TLV_CS_PERIPHID0 (0x00BB2FE0) +#define DBG_TLV_CS_PERIPHID0___RWC QCSR_REG_RO +#define DBG_TLV_CS_PERIPHID0___POR 0x00000000 +#define DBG_TLV_CS_PERIPHID0__RFU___POR 0x000000 +#define DBG_TLV_CS_PERIPHID0__PARTNUM_7_0___POR 0x0 +#define DBG_TLV_CS_PERIPHID0__RFU___M 0xFFFFFF00 +#define DBG_TLV_CS_PERIPHID0__RFU___S 8 +#define DBG_TLV_CS_PERIPHID0__PARTNUM_7_0___M 0x000000FF +#define DBG_TLV_CS_PERIPHID0__PARTNUM_7_0___S 0 +#define DBG_TLV_CS_PERIPHID0___M 0xFFFFFFFF +#define DBG_TLV_CS_PERIPHID0___S 0 + +#define DBG_TLV_CS_PERIPHID1 (0x00BB2FE4) +#define DBG_TLV_CS_PERIPHID1___RWC QCSR_REG_RO +#define DBG_TLV_CS_PERIPHID1___POR 0x00000000 +#define DBG_TLV_CS_PERIPHID1__RFU___POR 0x000000 +#define DBG_TLV_CS_PERIPHID1__JEP106_ID_3_0___POR 0x0 +#define DBG_TLV_CS_PERIPHID1__PART_NUM_11_8___POR 0x0 +#define DBG_TLV_CS_PERIPHID1__RFU___M 0xFFFFFF00 +#define DBG_TLV_CS_PERIPHID1__RFU___S 8 +#define DBG_TLV_CS_PERIPHID1__JEP106_ID_3_0___M 0x000000F0 +#define DBG_TLV_CS_PERIPHID1__JEP106_ID_3_0___S 4 +#define DBG_TLV_CS_PERIPHID1__PART_NUM_11_8___M 0x0000000F +#define DBG_TLV_CS_PERIPHID1__PART_NUM_11_8___S 0 +#define DBG_TLV_CS_PERIPHID1___M 0xFFFFFFFF +#define DBG_TLV_CS_PERIPHID1___S 0 + +#define DBG_TLV_CS_PERIPHID2 (0x00BB2FE8) +#define DBG_TLV_CS_PERIPHID2___RWC QCSR_REG_RO +#define DBG_TLV_CS_PERIPHID2___POR 0x0000000F +#define DBG_TLV_CS_PERIPHID2__RFU___POR 0x000000 +#define DBG_TLV_CS_PERIPHID2__PERIPH_REV___POR 0x0 +#define DBG_TLV_CS_PERIPHID2__JEP106_ASS___POR 0x1 +#define DBG_TLV_CS_PERIPHID2__JEP106_ID_6_4___POR 0x7 +#define DBG_TLV_CS_PERIPHID2__RFU___M 0xFFFFFF00 +#define DBG_TLV_CS_PERIPHID2__RFU___S 8 +#define DBG_TLV_CS_PERIPHID2__PERIPH_REV___M 0x000000F0 +#define DBG_TLV_CS_PERIPHID2__PERIPH_REV___S 4 +#define DBG_TLV_CS_PERIPHID2__JEP106_ASS___M 0x00000008 +#define DBG_TLV_CS_PERIPHID2__JEP106_ASS___S 3 +#define DBG_TLV_CS_PERIPHID2__JEP106_ID_6_4___M 0x00000007 +#define DBG_TLV_CS_PERIPHID2__JEP106_ID_6_4___S 0 +#define DBG_TLV_CS_PERIPHID2___M 0xFFFFFFFF +#define DBG_TLV_CS_PERIPHID2___S 0 + +#define DBG_TLV_CS_PERIPHID3 (0x00BB2FEC) +#define DBG_TLV_CS_PERIPHID3___RWC QCSR_REG_RO +#define DBG_TLV_CS_PERIPHID3___POR 0x00000000 +#define DBG_TLV_CS_PERIPHID3__RFU___POR 0x000000 +#define DBG_TLV_CS_PERIPHID3__REV_AND___POR 0x0 +#define DBG_TLV_CS_PERIPHID3__MODIFIED___POR 0x0 +#define DBG_TLV_CS_PERIPHID3__RFU___M 0xFFFFFF00 +#define DBG_TLV_CS_PERIPHID3__RFU___S 8 +#define DBG_TLV_CS_PERIPHID3__REV_AND___M 0x000000F0 +#define DBG_TLV_CS_PERIPHID3__REV_AND___S 4 +#define DBG_TLV_CS_PERIPHID3__MODIFIED___M 0x0000000F +#define DBG_TLV_CS_PERIPHID3__MODIFIED___S 0 +#define DBG_TLV_CS_PERIPHID3___M 0xFFFFFFFF +#define DBG_TLV_CS_PERIPHID3___S 0 + +#define DBG_TLV_CS_COMPID0 (0x00BB2FF0) +#define DBG_TLV_CS_COMPID0___RWC QCSR_REG_RO +#define DBG_TLV_CS_COMPID0___POR 0x0000000D +#define DBG_TLV_CS_COMPID0__RFU___POR 0x000000 +#define DBG_TLV_CS_COMPID0__PREAMBLE_7_0___POR 0x0D +#define DBG_TLV_CS_COMPID0__RFU___M 0xFFFFFF00 +#define DBG_TLV_CS_COMPID0__RFU___S 8 +#define DBG_TLV_CS_COMPID0__PREAMBLE_7_0___M 0x000000FF +#define DBG_TLV_CS_COMPID0__PREAMBLE_7_0___S 0 +#define DBG_TLV_CS_COMPID0___M 0xFFFFFFFF +#define DBG_TLV_CS_COMPID0___S 0 + +#define DBG_TLV_CS_COMPID1 (0x00BB2FF4) +#define DBG_TLV_CS_COMPID1___RWC QCSR_REG_RO +#define DBG_TLV_CS_COMPID1___POR 0x00000090 +#define DBG_TLV_CS_COMPID1__RFU___POR 0x000000 +#define DBG_TLV_CS_COMPID1__PREAMBLE_15_12___POR 0x9 +#define DBG_TLV_CS_COMPID1__PREAMBLE_11_8___POR 0x0 +#define DBG_TLV_CS_COMPID1__RFU___M 0xFFFFFF00 +#define DBG_TLV_CS_COMPID1__RFU___S 8 +#define DBG_TLV_CS_COMPID1__PREAMBLE_15_12___M 0x000000F0 +#define DBG_TLV_CS_COMPID1__PREAMBLE_15_12___S 4 +#define DBG_TLV_CS_COMPID1__PREAMBLE_11_8___M 0x0000000F +#define DBG_TLV_CS_COMPID1__PREAMBLE_11_8___S 0 +#define DBG_TLV_CS_COMPID1___M 0xFFFFFFFF +#define DBG_TLV_CS_COMPID1___S 0 + +#define DBG_TLV_CS_COMPID2 (0x00BB2FF8) +#define DBG_TLV_CS_COMPID2___RWC QCSR_REG_RO +#define DBG_TLV_CS_COMPID2___POR 0x00000005 +#define DBG_TLV_CS_COMPID2__RFU___POR 0x000000 +#define DBG_TLV_CS_COMPID2__PREAMBLE_23_16___POR 0x05 +#define DBG_TLV_CS_COMPID2__RFU___M 0xFFFFFF00 +#define DBG_TLV_CS_COMPID2__RFU___S 8 +#define DBG_TLV_CS_COMPID2__PREAMBLE_23_16___M 0x000000FF +#define DBG_TLV_CS_COMPID2__PREAMBLE_23_16___S 0 +#define DBG_TLV_CS_COMPID2___M 0xFFFFFFFF +#define DBG_TLV_CS_COMPID2___S 0 + +#define DBG_TLV_CS_COMPID3 (0x00BB2FFC) +#define DBG_TLV_CS_COMPID3___RWC QCSR_REG_RO +#define DBG_TLV_CS_COMPID3___POR 0x000000B1 +#define DBG_TLV_CS_COMPID3__RFU___POR 0x000000 +#define DBG_TLV_CS_COMPID3__PREAMBLE_31_24___POR 0xB1 +#define DBG_TLV_CS_COMPID3__RFU___M 0xFFFFFF00 +#define DBG_TLV_CS_COMPID3__RFU___S 8 +#define DBG_TLV_CS_COMPID3__PREAMBLE_31_24___M 0x000000FF +#define DBG_TLV_CS_COMPID3__PREAMBLE_31_24___S 0 +#define DBG_TLV_CS_COMPID3___M 0xFFFFFFFF +#define DBG_TLV_CS_COMPID3___S 0 + +#define DBG_TLVFUN_CTRL_REG (0x00BB3000) +#define DBG_TLVFUN_CTRL_REG___RWC QCSR_REG_RW +#define DBG_TLVFUN_CTRL_REG___POR 0x00000300 +#define DBG_TLVFUN_CTRL_REG__HT___POR 0x3 +#define DBG_TLVFUN_CTRL_REG__ENS7___POR 0x0 +#define DBG_TLVFUN_CTRL_REG__ENS6___POR 0x0 +#define DBG_TLVFUN_CTRL_REG__ENS5___POR 0x0 +#define DBG_TLVFUN_CTRL_REG__ENS4___POR 0x0 +#define DBG_TLVFUN_CTRL_REG__ENS3___POR 0x0 +#define DBG_TLVFUN_CTRL_REG__ENS2___POR 0x0 +#define DBG_TLVFUN_CTRL_REG__ENS1___POR 0x0 +#define DBG_TLVFUN_CTRL_REG__ENS0___POR 0x0 +#define DBG_TLVFUN_CTRL_REG__HT___M 0x00000F00 +#define DBG_TLVFUN_CTRL_REG__HT___S 8 +#define DBG_TLVFUN_CTRL_REG__HT__HT_0X0 0x0 +#define DBG_TLVFUN_CTRL_REG__HT__HT_0X1 0x1 +#define DBG_TLVFUN_CTRL_REG__HT__HT_0X2 0x2 +#define DBG_TLVFUN_CTRL_REG__HT__HT_0X3 0x3 +#define DBG_TLVFUN_CTRL_REG__HT__HT_0X4 0x4 +#define DBG_TLVFUN_CTRL_REG__HT__HT_0X5 0x5 +#define DBG_TLVFUN_CTRL_REG__HT__HT_0X6 0x6 +#define DBG_TLVFUN_CTRL_REG__HT__HT_0X7 0x7 +#define DBG_TLVFUN_CTRL_REG__HT__HT_0X8 0x8 +#define DBG_TLVFUN_CTRL_REG__HT__HT_0X9 0x9 +#define DBG_TLVFUN_CTRL_REG__HT__HT_0XA 0xA +#define DBG_TLVFUN_CTRL_REG__HT__HT_0XB 0xB +#define DBG_TLVFUN_CTRL_REG__HT__HT_0XC 0xC +#define DBG_TLVFUN_CTRL_REG__HT__HT_0XD 0xD +#define DBG_TLVFUN_CTRL_REG__HT__HT_0XE 0xE +#define DBG_TLVFUN_CTRL_REG__ENS7___M 0x00000080 +#define DBG_TLVFUN_CTRL_REG__ENS7___S 7 +#define DBG_TLVFUN_CTRL_REG__ENS7__ENS7_0 0x0 +#define DBG_TLVFUN_CTRL_REG__ENS7__ENS7_1 0x1 +#define DBG_TLVFUN_CTRL_REG__ENS6___M 0x00000040 +#define DBG_TLVFUN_CTRL_REG__ENS6___S 6 +#define DBG_TLVFUN_CTRL_REG__ENS6__ENS6_0 0x0 +#define DBG_TLVFUN_CTRL_REG__ENS6__ENS6_1 0x1 +#define DBG_TLVFUN_CTRL_REG__ENS5___M 0x00000020 +#define DBG_TLVFUN_CTRL_REG__ENS5___S 5 +#define DBG_TLVFUN_CTRL_REG__ENS5__ENS5_0 0x0 +#define DBG_TLVFUN_CTRL_REG__ENS5__ENS5_1 0x1 +#define DBG_TLVFUN_CTRL_REG__ENS4___M 0x00000010 +#define DBG_TLVFUN_CTRL_REG__ENS4___S 4 +#define DBG_TLVFUN_CTRL_REG__ENS4__ENS4_0 0x0 +#define DBG_TLVFUN_CTRL_REG__ENS4__ENS4_1 0x1 +#define DBG_TLVFUN_CTRL_REG__ENS3___M 0x00000008 +#define DBG_TLVFUN_CTRL_REG__ENS3___S 3 +#define DBG_TLVFUN_CTRL_REG__ENS3__ENS3_0 0x0 +#define DBG_TLVFUN_CTRL_REG__ENS3__ENS3_1 0x1 +#define DBG_TLVFUN_CTRL_REG__ENS2___M 0x00000004 +#define DBG_TLVFUN_CTRL_REG__ENS2___S 2 +#define DBG_TLVFUN_CTRL_REG__ENS2__ENS2_0 0x0 +#define DBG_TLVFUN_CTRL_REG__ENS2__ENS2_1 0x1 +#define DBG_TLVFUN_CTRL_REG__ENS1___M 0x00000002 +#define DBG_TLVFUN_CTRL_REG__ENS1___S 1 +#define DBG_TLVFUN_CTRL_REG__ENS1__ENS1_0 0x0 +#define DBG_TLVFUN_CTRL_REG__ENS1__ENS1_1 0x1 +#define DBG_TLVFUN_CTRL_REG__ENS0___M 0x00000001 +#define DBG_TLVFUN_CTRL_REG__ENS0___S 0 +#define DBG_TLVFUN_CTRL_REG__ENS0__ENS0_0 0x0 +#define DBG_TLVFUN_CTRL_REG__ENS0__ENS0_1 0x1 +#define DBG_TLVFUN_CTRL_REG___M 0x00000FFF +#define DBG_TLVFUN_CTRL_REG___S 0 + +#define DBG_TLVFUN_PRIORITY_CTRL_REG (0x00BB3004) +#define DBG_TLVFUN_PRIORITY_CTRL_REG___RWC QCSR_REG_RW +#define DBG_TLVFUN_PRIORITY_CTRL_REG___POR 0x00000000 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT7___POR 0x0 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT6___POR 0x0 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT5___POR 0x0 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT4___POR 0x0 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT3___POR 0x0 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT2___POR 0x0 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT1___POR 0x0 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT0___POR 0x0 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT7___M 0x00E00000 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT7___S 21 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_0 0x0 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_1 0x1 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_2 0x2 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_3 0x3 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_4 0x4 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_5 0x5 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_6 0x6 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_7 0x7 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT6___M 0x001C0000 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT6___S 18 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_0 0x0 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_1 0x1 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_2 0x2 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_3 0x3 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_4 0x4 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_5 0x5 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_6 0x6 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_7 0x7 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT5___M 0x00038000 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT5___S 15 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_0 0x0 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_1 0x1 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_2 0x2 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_3 0x3 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_4 0x4 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_5 0x5 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_6 0x6 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_7 0x7 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT4___M 0x00007000 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT4___S 12 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_0 0x0 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_1 0x1 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_2 0x2 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_3 0x3 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_4 0x4 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_5 0x5 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_6 0x6 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_7 0x7 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT3___M 0x00000E00 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT3___S 9 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_0 0x0 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_1 0x1 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_2 0x2 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_3 0x3 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_4 0x4 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_5 0x5 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_6 0x6 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_7 0x7 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT2___M 0x000001C0 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT2___S 6 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_0 0x0 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_1 0x1 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_2 0x2 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_3 0x3 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_4 0x4 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_5 0x5 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_6 0x6 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_7 0x7 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT1___M 0x00000038 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT1___S 3 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_0 0x0 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_1 0x1 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_2 0x2 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_3 0x3 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_4 0x4 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_5 0x5 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_6 0x6 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_7 0x7 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT0___M 0x00000007 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT0___S 0 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_0 0x0 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_1 0x1 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_2 0x2 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_3 0x3 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_4 0x4 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_5 0x5 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_6 0x6 +#define DBG_TLVFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_7 0x7 +#define DBG_TLVFUN_PRIORITY_CTRL_REG___M 0x00FFFFFF +#define DBG_TLVFUN_PRIORITY_CTRL_REG___S 0 + +#define DBG_TLVFUN_ITATBDATA0 (0x00BB3EEC) +#define DBG_TLVFUN_ITATBDATA0___RWC QCSR_REG_RW +#define DBG_TLVFUN_ITATBDATA0___POR 0x00000000 +#define DBG_TLVFUN_ITATBDATA0__ATDATA31___POR 0x0 +#define DBG_TLVFUN_ITATBDATA0__ATDATAM23___POR 0x0 +#define DBG_TLVFUN_ITATBDATA0__ATDATA15___POR 0x0 +#define DBG_TLVFUN_ITATBDATA0__ATDATA7___POR 0x0 +#define DBG_TLVFUN_ITATBDATA0__ATDATA0___POR 0x0 +#define DBG_TLVFUN_ITATBDATA0__ATDATA31___M 0x00000010 +#define DBG_TLVFUN_ITATBDATA0__ATDATA31___S 4 +#define DBG_TLVFUN_ITATBDATA0__ATDATA31__ATDATA31_0 0x0 +#define DBG_TLVFUN_ITATBDATA0__ATDATA31__ATDATA31_1 0x1 +#define DBG_TLVFUN_ITATBDATA0__ATDATAM23___M 0x00000008 +#define DBG_TLVFUN_ITATBDATA0__ATDATAM23___S 3 +#define DBG_TLVFUN_ITATBDATA0__ATDATAM23__ATDATAM23_0 0x0 +#define DBG_TLVFUN_ITATBDATA0__ATDATAM23__ATDATAM23_1 0x1 +#define DBG_TLVFUN_ITATBDATA0__ATDATA15___M 0x00000004 +#define DBG_TLVFUN_ITATBDATA0__ATDATA15___S 2 +#define DBG_TLVFUN_ITATBDATA0__ATDATA15__ATDATA15_0 0x0 +#define DBG_TLVFUN_ITATBDATA0__ATDATA15__ATDATA15_1 0x1 +#define DBG_TLVFUN_ITATBDATA0__ATDATA7___M 0x00000002 +#define DBG_TLVFUN_ITATBDATA0__ATDATA7___S 1 +#define DBG_TLVFUN_ITATBDATA0__ATDATA7__ATDATA7_0 0x0 +#define DBG_TLVFUN_ITATBDATA0__ATDATA7__ATDATA7_1 0x1 +#define DBG_TLVFUN_ITATBDATA0__ATDATA0___M 0x00000001 +#define DBG_TLVFUN_ITATBDATA0__ATDATA0___S 0 +#define DBG_TLVFUN_ITATBDATA0__ATDATA0__ATDATA0_0 0x0 +#define DBG_TLVFUN_ITATBDATA0__ATDATA0__ATDATA0_1 0x1 +#define DBG_TLVFUN_ITATBDATA0___M 0x0000001F +#define DBG_TLVFUN_ITATBDATA0___S 0 + +#define DBG_TLVFUN_ITATBCTR2 (0x00BB3EF0) +#define DBG_TLVFUN_ITATBCTR2___RWC QCSR_REG_RW +#define DBG_TLVFUN_ITATBCTR2___POR 0x00000000 +#define DBG_TLVFUN_ITATBCTR2__AFVALID___POR 0x0 +#define DBG_TLVFUN_ITATBCTR2__ATREADY___POR 0x0 +#define DBG_TLVFUN_ITATBCTR2__AFVALID___M 0x00000002 +#define DBG_TLVFUN_ITATBCTR2__AFVALID___S 1 +#define DBG_TLVFUN_ITATBCTR2__AFVALID__AFVALID_0 0x0 +#define DBG_TLVFUN_ITATBCTR2__AFVALID__AFVALID_1 0x1 +#define DBG_TLVFUN_ITATBCTR2__ATREADY___M 0x00000001 +#define DBG_TLVFUN_ITATBCTR2__ATREADY___S 0 +#define DBG_TLVFUN_ITATBCTR2__ATREADY__ATREADY_0 0x0 +#define DBG_TLVFUN_ITATBCTR2__ATREADY__ATREADY_1 0x1 +#define DBG_TLVFUN_ITATBCTR2___M 0x00000003 +#define DBG_TLVFUN_ITATBCTR2___S 0 + +#define DBG_TLVFUN_ITATBCTR1 (0x00BB3EF4) +#define DBG_TLVFUN_ITATBCTR1___RWC QCSR_REG_RW +#define DBG_TLVFUN_ITATBCTR1__ATID___M 0x0000007F +#define DBG_TLVFUN_ITATBCTR1__ATID___S 0 +#define DBG_TLVFUN_ITATBCTR1___M 0x0000007F +#define DBG_TLVFUN_ITATBCTR1___S 0 + +#define DBG_TLVFUN_ITATBCTR0 (0x00BB3EF8) +#define DBG_TLVFUN_ITATBCTR0___RWC QCSR_REG_RW +#define DBG_TLVFUN_ITATBCTR0___POR 0x00000000 +#define DBG_TLVFUN_ITATBCTR0__ATBYTES___POR 0x0 +#define DBG_TLVFUN_ITATBCTR0__AFREADY___POR 0x0 +#define DBG_TLVFUN_ITATBCTR0__ATVALID___POR 0x0 +#define DBG_TLVFUN_ITATBCTR0__ATBYTES___M 0x00000300 +#define DBG_TLVFUN_ITATBCTR0__ATBYTES___S 8 +#define DBG_TLVFUN_ITATBCTR0__ATBYTES__ATBYTES_0 0x0 +#define DBG_TLVFUN_ITATBCTR0__ATBYTES__ATBYTES_1 0x1 +#define DBG_TLVFUN_ITATBCTR0__AFREADY___M 0x00000002 +#define DBG_TLVFUN_ITATBCTR0__AFREADY___S 1 +#define DBG_TLVFUN_ITATBCTR0__AFREADY__AFREADY_0 0x0 +#define DBG_TLVFUN_ITATBCTR0__AFREADY__AFREADY_1 0x1 +#define DBG_TLVFUN_ITATBCTR0__ATVALID___M 0x00000001 +#define DBG_TLVFUN_ITATBCTR0__ATVALID___S 0 +#define DBG_TLVFUN_ITATBCTR0__ATVALID__ATVALID_0 0x0 +#define DBG_TLVFUN_ITATBCTR0__ATVALID__ATVALID_1 0x1 +#define DBG_TLVFUN_ITATBCTR0___M 0x00000303 +#define DBG_TLVFUN_ITATBCTR0___S 0 + +#define DBG_TLVFUN_ITCTRL (0x00BB3F00) +#define DBG_TLVFUN_ITCTRL___RWC QCSR_REG_RW +#define DBG_TLVFUN_ITCTRL___POR 0x00000000 +#define DBG_TLVFUN_ITCTRL__INTEGRATION_MODE___POR 0x0 +#define DBG_TLVFUN_ITCTRL__INTEGRATION_MODE___M 0x00000001 +#define DBG_TLVFUN_ITCTRL__INTEGRATION_MODE___S 0 +#define DBG_TLVFUN_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE_0 0x0 +#define DBG_TLVFUN_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE_1 0x1 +#define DBG_TLVFUN_ITCTRL___M 0x00000001 +#define DBG_TLVFUN_ITCTRL___S 0 + +#define DBG_TLVFUN_CLAIMSET (0x00BB3FA0) +#define DBG_TLVFUN_CLAIMSET___RWC QCSR_REG_RW +#define DBG_TLVFUN_CLAIMSET___POR 0x0000000F +#define DBG_TLVFUN_CLAIMSET__CLAIMSET___POR 0xF +#define DBG_TLVFUN_CLAIMSET__CLAIMSET___M 0x0000000F +#define DBG_TLVFUN_CLAIMSET__CLAIMSET___S 0 +#define DBG_TLVFUN_CLAIMSET__CLAIMSET__CLAIMSET_0XF 0xF +#define DBG_TLVFUN_CLAIMSET___M 0x0000000F +#define DBG_TLVFUN_CLAIMSET___S 0 + +#define DBG_TLVFUN_CLAIMCLR (0x00BB3FA4) +#define DBG_TLVFUN_CLAIMCLR___RWC QCSR_REG_RW +#define DBG_TLVFUN_CLAIMCLR___POR 0x00000000 +#define DBG_TLVFUN_CLAIMCLR__CLAIMCLR___POR 0x0 +#define DBG_TLVFUN_CLAIMCLR__CLAIMCLR___M 0x0000000F +#define DBG_TLVFUN_CLAIMCLR__CLAIMCLR___S 0 +#define DBG_TLVFUN_CLAIMCLR___M 0x0000000F +#define DBG_TLVFUN_CLAIMCLR___S 0 + +#define DBG_TLVFUN_LOCKACCESS (0x00BB3FB0) +#define DBG_TLVFUN_LOCKACCESS___RWC QCSR_REG_WO +#define DBG_TLVFUN_LOCKACCESS__KEY___M 0xFFFFFFFF +#define DBG_TLVFUN_LOCKACCESS__KEY___S 0 +#define DBG_TLVFUN_LOCKACCESS__KEY__KEY_0XC5ACCE55 0xC5ACCE55 +#define DBG_TLVFUN_LOCKACCESS__KEY__KEY_0XDEADBEEF 0xDEADBEEF +#define DBG_TLVFUN_LOCKACCESS___M 0xFFFFFFFF +#define DBG_TLVFUN_LOCKACCESS___S 0 + +#define DBG_TLVFUN_LOCKSTATUS (0x00BB3FB4) +#define DBG_TLVFUN_LOCKSTATUS___RWC QCSR_REG_RO +#define DBG_TLVFUN_LOCKSTATUS___POR 0x00000003 +#define DBG_TLVFUN_LOCKSTATUS__NTT___POR 0x0 +#define DBG_TLVFUN_LOCKSTATUS__SLK___POR 0x1 +#define DBG_TLVFUN_LOCKSTATUS__SLI___POR 0x1 +#define DBG_TLVFUN_LOCKSTATUS__NTT___M 0x00000004 +#define DBG_TLVFUN_LOCKSTATUS__NTT___S 2 +#define DBG_TLVFUN_LOCKSTATUS__NTT__NTT_0X0 0x0 +#define DBG_TLVFUN_LOCKSTATUS__SLK___M 0x00000002 +#define DBG_TLVFUN_LOCKSTATUS__SLK___S 1 +#define DBG_TLVFUN_LOCKSTATUS__SLK__SLK_0X0 0x0 +#define DBG_TLVFUN_LOCKSTATUS__SLK__SLK_0X1 0x1 +#define DBG_TLVFUN_LOCKSTATUS__SLI___M 0x00000001 +#define DBG_TLVFUN_LOCKSTATUS__SLI___S 0 +#define DBG_TLVFUN_LOCKSTATUS__SLI__SLI_0X0 0x0 +#define DBG_TLVFUN_LOCKSTATUS__SLI__SLI_0X1 0x1 +#define DBG_TLVFUN_LOCKSTATUS___M 0x00000007 +#define DBG_TLVFUN_LOCKSTATUS___S 0 + +#define DBG_TLVFUN_AUTHSTATUS (0x00BB3FB8) +#define DBG_TLVFUN_AUTHSTATUS___RWC QCSR_REG_RO +#define DBG_TLVFUN_AUTHSTATUS___POR 0x00000000 +#define DBG_TLVFUN_AUTHSTATUS__SNID___POR 0x0 +#define DBG_TLVFUN_AUTHSTATUS__SID___POR 0x0 +#define DBG_TLVFUN_AUTHSTATUS__NSNID___POR 0x0 +#define DBG_TLVFUN_AUTHSTATUS__NSID___POR 0x0 +#define DBG_TLVFUN_AUTHSTATUS__SNID___M 0x000000C0 +#define DBG_TLVFUN_AUTHSTATUS__SNID___S 6 +#define DBG_TLVFUN_AUTHSTATUS__SNID__SNID_0X0 0x0 +#define DBG_TLVFUN_AUTHSTATUS__SID___M 0x00000030 +#define DBG_TLVFUN_AUTHSTATUS__SID___S 4 +#define DBG_TLVFUN_AUTHSTATUS__SID__SID_0X0 0x0 +#define DBG_TLVFUN_AUTHSTATUS__NSNID___M 0x0000000C +#define DBG_TLVFUN_AUTHSTATUS__NSNID___S 2 +#define DBG_TLVFUN_AUTHSTATUS__NSNID__NSNID_0X0 0x0 +#define DBG_TLVFUN_AUTHSTATUS__NSID___M 0x00000003 +#define DBG_TLVFUN_AUTHSTATUS__NSID___S 0 +#define DBG_TLVFUN_AUTHSTATUS__NSID__NSID_0X0 0x0 +#define DBG_TLVFUN_AUTHSTATUS___M 0x000000FF +#define DBG_TLVFUN_AUTHSTATUS___S 0 + +#define DBG_TLVFUN_DEVID (0x00BB3FC8) +#define DBG_TLVFUN_DEVID___RWC QCSR_REG_RO +#define DBG_TLVFUN_DEVID___POR 0x00000038 +#define DBG_TLVFUN_DEVID__SCHEME___POR 0x3 +#define DBG_TLVFUN_DEVID__PORTCOUNT___POR 0x8 +#define DBG_TLVFUN_DEVID__SCHEME___M 0x000000F0 +#define DBG_TLVFUN_DEVID__SCHEME___S 4 +#define DBG_TLVFUN_DEVID__SCHEME__SCHEME_0X3 0x3 +#define DBG_TLVFUN_DEVID__PORTCOUNT___M 0x0000000F +#define DBG_TLVFUN_DEVID__PORTCOUNT___S 0 +#define DBG_TLVFUN_DEVID__PORTCOUNT__PORTCOUNT_0X2 0x2 +#define DBG_TLVFUN_DEVID__PORTCOUNT__PORTCOUNT_0X3 0x3 +#define DBG_TLVFUN_DEVID__PORTCOUNT__PORTCOUNT_0X4 0x4 +#define DBG_TLVFUN_DEVID__PORTCOUNT__PORTCOUNT_0X5 0x5 +#define DBG_TLVFUN_DEVID__PORTCOUNT__PORTCOUNT_0X6 0x6 +#define DBG_TLVFUN_DEVID__PORTCOUNT__PORTCOUNT_0X7 0x7 +#define DBG_TLVFUN_DEVID__PORTCOUNT__PORTCOUNT_0X8 0x8 +#define DBG_TLVFUN_DEVID___M 0x000000FF +#define DBG_TLVFUN_DEVID___S 0 + +#define DBG_TLVFUN_DEVTYPE (0x00BB3FCC) +#define DBG_TLVFUN_DEVTYPE___RWC QCSR_REG_RO +#define DBG_TLVFUN_DEVTYPE___POR 0x00000012 +#define DBG_TLVFUN_DEVTYPE__SUB_TYPE___POR 0x1 +#define DBG_TLVFUN_DEVTYPE__MAJOR_TYPE___POR 0x2 +#define DBG_TLVFUN_DEVTYPE__SUB_TYPE___M 0x000000F0 +#define DBG_TLVFUN_DEVTYPE__SUB_TYPE___S 4 +#define DBG_TLVFUN_DEVTYPE__SUB_TYPE__SUB_TYPE_0X1 0x1 +#define DBG_TLVFUN_DEVTYPE__MAJOR_TYPE___M 0x0000000F +#define DBG_TLVFUN_DEVTYPE__MAJOR_TYPE___S 0 +#define DBG_TLVFUN_DEVTYPE__MAJOR_TYPE__MAJOR_TYPE_0X2 0x2 +#define DBG_TLVFUN_DEVTYPE___M 0x000000FF +#define DBG_TLVFUN_DEVTYPE___S 0 + +#define DBG_TLVFUN_PIDR0 (0x00BB3FE0) +#define DBG_TLVFUN_PIDR0___RWC QCSR_REG_RO +#define DBG_TLVFUN_PIDR0___POR 0x00000008 +#define DBG_TLVFUN_PIDR0__PART_NUMBER_BITS7TO0___POR 0x08 +#define DBG_TLVFUN_PIDR0__PART_NUMBER_BITS7TO0___M 0x000000FF +#define DBG_TLVFUN_PIDR0__PART_NUMBER_BITS7TO0___S 0 +#define DBG_TLVFUN_PIDR0__PART_NUMBER_BITS7TO0__PART_NUMBER_BITS7TO0_0X08 0x08 +#define DBG_TLVFUN_PIDR0___M 0x000000FF +#define DBG_TLVFUN_PIDR0___S 0 + +#define DBG_TLVFUN_PIDR1 (0x00BB3FE4) +#define DBG_TLVFUN_PIDR1___RWC QCSR_REG_RO +#define DBG_TLVFUN_PIDR1___POR 0x000000B9 +#define DBG_TLVFUN_PIDR1__JEP106_BITS3TO0___POR 0xB +#define DBG_TLVFUN_PIDR1__PART_NUMBER_BITS11TO8___POR 0x9 +#define DBG_TLVFUN_PIDR1__JEP106_BITS3TO0___M 0x000000F0 +#define DBG_TLVFUN_PIDR1__JEP106_BITS3TO0___S 4 +#define DBG_TLVFUN_PIDR1__JEP106_BITS3TO0__JEP106_BITS3TO0_0XB 0xB +#define DBG_TLVFUN_PIDR1__PART_NUMBER_BITS11TO8___M 0x0000000F +#define DBG_TLVFUN_PIDR1__PART_NUMBER_BITS11TO8___S 0 +#define DBG_TLVFUN_PIDR1__PART_NUMBER_BITS11TO8__PART_NUMBER_BITS11TO8_0X9 0x9 +#define DBG_TLVFUN_PIDR1___M 0x000000FF +#define DBG_TLVFUN_PIDR1___S 0 + +#define DBG_TLVFUN_PIDR2 (0x00BB3FE8) +#define DBG_TLVFUN_PIDR2___RWC QCSR_REG_RO +#define DBG_TLVFUN_PIDR2___POR 0x0000003B +#define DBG_TLVFUN_PIDR2__REVISION___POR 0x3 +#define DBG_TLVFUN_PIDR2__JEDEC___POR 0x1 +#define DBG_TLVFUN_PIDR2__JEP106_BITS6TO4___POR 0x3 +#define DBG_TLVFUN_PIDR2__REVISION___M 0x000000F0 +#define DBG_TLVFUN_PIDR2__REVISION___S 4 +#define DBG_TLVFUN_PIDR2__REVISION__REVISION_0X3 0x3 +#define DBG_TLVFUN_PIDR2__JEDEC___M 0x00000008 +#define DBG_TLVFUN_PIDR2__JEDEC___S 3 +#define DBG_TLVFUN_PIDR2__JEDEC__JEDEC_0X1 0x1 +#define DBG_TLVFUN_PIDR2__JEP106_BITS6TO4___M 0x00000007 +#define DBG_TLVFUN_PIDR2__JEP106_BITS6TO4___S 0 +#define DBG_TLVFUN_PIDR2__JEP106_BITS6TO4__JEP106_BITS6TO4_0X3 0x3 +#define DBG_TLVFUN_PIDR2___M 0x000000FF +#define DBG_TLVFUN_PIDR2___S 0 + +#define DBG_TLVFUN_PIDR3 (0x00BB3FEC) +#define DBG_TLVFUN_PIDR3___RWC QCSR_REG_RO +#define DBG_TLVFUN_PIDR3___POR 0x00000000 +#define DBG_TLVFUN_PIDR3__REVAND___POR 0x0 +#define DBG_TLVFUN_PIDR3__CUSTOMER_MODIFIED___POR 0x0 +#define DBG_TLVFUN_PIDR3__REVAND___M 0x000000F0 +#define DBG_TLVFUN_PIDR3__REVAND___S 4 +#define DBG_TLVFUN_PIDR3__REVAND__REVAND_0X0 0x0 +#define DBG_TLVFUN_PIDR3__CUSTOMER_MODIFIED___M 0x0000000F +#define DBG_TLVFUN_PIDR3__CUSTOMER_MODIFIED___S 0 +#define DBG_TLVFUN_PIDR3__CUSTOMER_MODIFIED__CUSTOMER_MODIFIED_0X0 0x0 +#define DBG_TLVFUN_PIDR3___M 0x000000FF +#define DBG_TLVFUN_PIDR3___S 0 + +#define DBG_TLVFUN_PIDR4 (0x00BB3FD0) +#define DBG_TLVFUN_PIDR4___RWC QCSR_REG_RO +#define DBG_TLVFUN_PIDR4___POR 0x00000004 +#define DBG_TLVFUN_PIDR4__FOURKB_COUNT___POR 0x0 +#define DBG_TLVFUN_PIDR4__JEP106_CONT___POR 0x4 +#define DBG_TLVFUN_PIDR4__FOURKB_COUNT___M 0x000000F0 +#define DBG_TLVFUN_PIDR4__FOURKB_COUNT___S 4 +#define DBG_TLVFUN_PIDR4__FOURKB_COUNT__FOURKB_COUNT_0X0 0x0 +#define DBG_TLVFUN_PIDR4__JEP106_CONT___M 0x0000000F +#define DBG_TLVFUN_PIDR4__JEP106_CONT___S 0 +#define DBG_TLVFUN_PIDR4__JEP106_CONT__JEP106_CONT_0X4 0x4 +#define DBG_TLVFUN_PIDR4___M 0x000000FF +#define DBG_TLVFUN_PIDR4___S 0 + +#define DBG_TLVFUN_PERIPHID5 (0x00BB3FD4) +#define DBG_TLVFUN_PERIPHID5___RWC QCSR_REG_RO +#define DBG_TLVFUN_PERIPHID5___POR 0x00000000 +#define DBG_TLVFUN_PERIPHID5__PERIPHID5___POR 0x00000000 +#define DBG_TLVFUN_PERIPHID5__PERIPHID5___M 0xFFFFFFFF +#define DBG_TLVFUN_PERIPHID5__PERIPHID5___S 0 +#define DBG_TLVFUN_PERIPHID5___M 0xFFFFFFFF +#define DBG_TLVFUN_PERIPHID5___S 0 + +#define DBG_TLVFUN_PERIPHID6 (0x00BB3FD8) +#define DBG_TLVFUN_PERIPHID6___RWC QCSR_REG_RO +#define DBG_TLVFUN_PERIPHID6___POR 0x00000000 +#define DBG_TLVFUN_PERIPHID6__PERIPHID6___POR 0x00000000 +#define DBG_TLVFUN_PERIPHID6__PERIPHID6___M 0xFFFFFFFF +#define DBG_TLVFUN_PERIPHID6__PERIPHID6___S 0 +#define DBG_TLVFUN_PERIPHID6___M 0xFFFFFFFF +#define DBG_TLVFUN_PERIPHID6___S 0 + +#define DBG_TLVFUN_PERIPHID7 (0x00BB3FDC) +#define DBG_TLVFUN_PERIPHID7___RWC QCSR_REG_RO +#define DBG_TLVFUN_PERIPHID7___POR 0x00000000 +#define DBG_TLVFUN_PERIPHID7__PERIPHID7___POR 0x00000000 +#define DBG_TLVFUN_PERIPHID7__PERIPHID7___M 0xFFFFFFFF +#define DBG_TLVFUN_PERIPHID7__PERIPHID7___S 0 +#define DBG_TLVFUN_PERIPHID7___M 0xFFFFFFFF +#define DBG_TLVFUN_PERIPHID7___S 0 + +#define DBG_TLVFUN_CID0 (0x00BB3FF0) +#define DBG_TLVFUN_CID0___RWC QCSR_REG_RO +#define DBG_TLVFUN_CID0___POR 0x0000000D +#define DBG_TLVFUN_CID0__PREAMBLE___POR 0x0D +#define DBG_TLVFUN_CID0__PREAMBLE___M 0x000000FF +#define DBG_TLVFUN_CID0__PREAMBLE___S 0 +#define DBG_TLVFUN_CID0__PREAMBLE__PREAMBLE_0X0D 0x0D +#define DBG_TLVFUN_CID0___M 0x000000FF +#define DBG_TLVFUN_CID0___S 0 + +#define DBG_TLVFUN_CID1 (0x00BB3FF4) +#define DBG_TLVFUN_CID1___RWC QCSR_REG_RO +#define DBG_TLVFUN_CID1___POR 0x00000090 +#define DBG_TLVFUN_CID1__CLASS___POR 0x9 +#define DBG_TLVFUN_CID1__PREAMBLE___POR 0x0 +#define DBG_TLVFUN_CID1__CLASS___M 0x000000F0 +#define DBG_TLVFUN_CID1__CLASS___S 4 +#define DBG_TLVFUN_CID1__CLASS__CLASS_0X9 0x9 +#define DBG_TLVFUN_CID1__PREAMBLE___M 0x0000000F +#define DBG_TLVFUN_CID1__PREAMBLE___S 0 +#define DBG_TLVFUN_CID1__PREAMBLE__PREAMBLE_0X0 0x0 +#define DBG_TLVFUN_CID1___M 0x000000FF +#define DBG_TLVFUN_CID1___S 0 + +#define DBG_TLVFUN_CID2 (0x00BB3FF8) +#define DBG_TLVFUN_CID2___RWC QCSR_REG_RO +#define DBG_TLVFUN_CID2___POR 0x00000005 +#define DBG_TLVFUN_CID2__PREAMBLE___POR 0x05 +#define DBG_TLVFUN_CID2__PREAMBLE___M 0x000000FF +#define DBG_TLVFUN_CID2__PREAMBLE___S 0 +#define DBG_TLVFUN_CID2__PREAMBLE__PREAMBLE_0X05 0x05 +#define DBG_TLVFUN_CID2___M 0x000000FF +#define DBG_TLVFUN_CID2___S 0 + +#define DBG_TLVFUN_CID3 (0x00BB3FFC) +#define DBG_TLVFUN_CID3___RWC QCSR_REG_RO +#define DBG_TLVFUN_CID3___POR 0x000000B1 +#define DBG_TLVFUN_CID3__PREAMBLE___POR 0xB1 +#define DBG_TLVFUN_CID3__PREAMBLE___M 0x000000FF +#define DBG_TLVFUN_CID3__PREAMBLE___S 0 +#define DBG_TLVFUN_CID3__PREAMBLE__PREAMBLE_0XB1 0xB1 +#define DBG_TLVFUN_CID3___M 0x000000FF +#define DBG_TLVFUN_CID3___S 0 + +#define DBG_TBUS_MACTBUS_CFG (0x00BB4000) +#define DBG_TBUS_MACTBUS_CFG___RWC QCSR_REG_RW +#define DBG_TBUS_MACTBUS_CFG___POR 0x00003BA7 +#define DBG_TBUS_MACTBUS_CFG__LMAC0_EN___POR 0x1 +#define DBG_TBUS_MACTBUS_CFG__UMAC_EN___POR 0x1 +#define DBG_TBUS_MACTBUS_CFG__ATID___POR 0x5D +#define DBG_TBUS_MACTBUS_CFG__TRANSPORT___POR 0x0 +#define DBG_TBUS_MACTBUS_CFG__COLTRIG_EN___POR 0x0 +#define DBG_TBUS_MACTBUS_CFG__TSTMP_EN___POR 0x1 +#define DBG_TBUS_MACTBUS_CFG__TRCONCHG___POR 0x1 +#define DBG_TBUS_MACTBUS_CFG__ENABLE___POR 0x1 +#define DBG_TBUS_MACTBUS_CFG__LMAC0_EN___M 0x00002000 +#define DBG_TBUS_MACTBUS_CFG__LMAC0_EN___S 13 +#define DBG_TBUS_MACTBUS_CFG__UMAC_EN___M 0x00001000 +#define DBG_TBUS_MACTBUS_CFG__UMAC_EN___S 12 +#define DBG_TBUS_MACTBUS_CFG__ATID___M 0x00000FE0 +#define DBG_TBUS_MACTBUS_CFG__ATID___S 5 +#define DBG_TBUS_MACTBUS_CFG__TRANSPORT___M 0x00000010 +#define DBG_TBUS_MACTBUS_CFG__TRANSPORT___S 4 +#define DBG_TBUS_MACTBUS_CFG__TRANSPORT__CMB 0x0 +#define DBG_TBUS_MACTBUS_CFG__TRANSPORT__ATB 0x1 +#define DBG_TBUS_MACTBUS_CFG__COLTRIG_EN___M 0x00000008 +#define DBG_TBUS_MACTBUS_CFG__COLTRIG_EN___S 3 +#define DBG_TBUS_MACTBUS_CFG__TSTMP_EN___M 0x00000004 +#define DBG_TBUS_MACTBUS_CFG__TSTMP_EN___S 2 +#define DBG_TBUS_MACTBUS_CFG__TRCONCHG___M 0x00000002 +#define DBG_TBUS_MACTBUS_CFG__TRCONCHG___S 1 +#define DBG_TBUS_MACTBUS_CFG__TRCONCHG__TRACEALL 0x0 +#define DBG_TBUS_MACTBUS_CFG__TRCONCHG__TRACECHG 0x1 +#define DBG_TBUS_MACTBUS_CFG__ENABLE___M 0x00000001 +#define DBG_TBUS_MACTBUS_CFG__ENABLE___S 0 +#define DBG_TBUS_MACTBUS_CFG___M 0x00003FFF +#define DBG_TBUS_MACTBUS_CFG___S 0 + +#define DBG_TBUS_MACTBUS_TGU_CFG (0x00BB4004) +#define DBG_TBUS_MACTBUS_TGU_CFG___RWC QCSR_REG_RW +#define DBG_TBUS_MACTBUS_TGU_CFG___POR 0x000000F0 +#define DBG_TBUS_MACTBUS_TGU_CFG__TRIG_COMBOP___POR 0x0 +#define DBG_TBUS_MACTBUS_TGU_CFG__TRIG_POL___POR 0xF +#define DBG_TBUS_MACTBUS_TGU_CFG__TRIG_EN___POR 0x0 +#define DBG_TBUS_MACTBUS_TGU_CFG__TRIG_COMBOP___M 0x00000100 +#define DBG_TBUS_MACTBUS_TGU_CFG__TRIG_COMBOP___S 8 +#define DBG_TBUS_MACTBUS_TGU_CFG__TRIG_POL___M 0x000000F0 +#define DBG_TBUS_MACTBUS_TGU_CFG__TRIG_POL___S 4 +#define DBG_TBUS_MACTBUS_TGU_CFG__TRIG_EN___M 0x0000000F +#define DBG_TBUS_MACTBUS_TGU_CFG__TRIG_EN___S 0 +#define DBG_TBUS_MACTBUS_TGU_CFG___M 0x000001FF +#define DBG_TBUS_MACTBUS_TGU_CFG___S 0 + +#define DBG_TBUS_MACTBUS_MATCH0_DATA (0x00BB4008) +#define DBG_TBUS_MACTBUS_MATCH0_DATA___RWC QCSR_REG_RW +#define DBG_TBUS_MACTBUS_MATCH0_DATA___POR 0x00000000 +#define DBG_TBUS_MACTBUS_MATCH0_DATA__DATA___POR 0x00000000 +#define DBG_TBUS_MACTBUS_MATCH0_DATA__DATA___M 0xFFFFFFFF +#define DBG_TBUS_MACTBUS_MATCH0_DATA__DATA___S 0 +#define DBG_TBUS_MACTBUS_MATCH0_DATA___M 0xFFFFFFFF +#define DBG_TBUS_MACTBUS_MATCH0_DATA___S 0 + +#define DBG_TBUS_MACTBUS_MATCH0_DATAH (0x00BB400C) +#define DBG_TBUS_MACTBUS_MATCH0_DATAH___RWC QCSR_REG_RW +#define DBG_TBUS_MACTBUS_MATCH0_DATAH___POR 0x00000000 +#define DBG_TBUS_MACTBUS_MATCH0_DATAH__DATA_43_32___POR 0x000 +#define DBG_TBUS_MACTBUS_MATCH0_DATAH__DATA_43_32___M 0x00000FFF +#define DBG_TBUS_MACTBUS_MATCH0_DATAH__DATA_43_32___S 0 +#define DBG_TBUS_MACTBUS_MATCH0_DATAH___M 0x00000FFF +#define DBG_TBUS_MACTBUS_MATCH0_DATAH___S 0 + +#define DBG_TBUS_MACTBUS_MATCH0_MASK (0x00BB4010) +#define DBG_TBUS_MACTBUS_MATCH0_MASK___RWC QCSR_REG_RW +#define DBG_TBUS_MACTBUS_MATCH0_MASK___POR 0xFFFFFFFF +#define DBG_TBUS_MACTBUS_MATCH0_MASK__MASK___POR 0xFFFFFFFF +#define DBG_TBUS_MACTBUS_MATCH0_MASK__MASK___M 0xFFFFFFFF +#define DBG_TBUS_MACTBUS_MATCH0_MASK__MASK___S 0 +#define DBG_TBUS_MACTBUS_MATCH0_MASK___M 0xFFFFFFFF +#define DBG_TBUS_MACTBUS_MATCH0_MASK___S 0 + +#define DBG_TBUS_MACTBUS_MATCH0_MASKH (0x00BB4014) +#define DBG_TBUS_MACTBUS_MATCH0_MASKH___RWC QCSR_REG_RW +#define DBG_TBUS_MACTBUS_MATCH0_MASKH___POR 0x00000FFF +#define DBG_TBUS_MACTBUS_MATCH0_MASKH__MASK_43_32___POR 0xFFF +#define DBG_TBUS_MACTBUS_MATCH0_MASKH__MASK_43_32___M 0x00000FFF +#define DBG_TBUS_MACTBUS_MATCH0_MASKH__MASK_43_32___S 0 +#define DBG_TBUS_MACTBUS_MATCH0_MASKH___M 0x00000FFF +#define DBG_TBUS_MACTBUS_MATCH0_MASKH___S 0 + +#define DBG_TBUS_MACTBUS_MATCH1_DATA (0x00BB4018) +#define DBG_TBUS_MACTBUS_MATCH1_DATA___RWC QCSR_REG_RW +#define DBG_TBUS_MACTBUS_MATCH1_DATA___POR 0x00000000 +#define DBG_TBUS_MACTBUS_MATCH1_DATA__DATA___POR 0x00000000 +#define DBG_TBUS_MACTBUS_MATCH1_DATA__DATA___M 0xFFFFFFFF +#define DBG_TBUS_MACTBUS_MATCH1_DATA__DATA___S 0 +#define DBG_TBUS_MACTBUS_MATCH1_DATA___M 0xFFFFFFFF +#define DBG_TBUS_MACTBUS_MATCH1_DATA___S 0 + +#define DBG_TBUS_MACTBUS_MATCH1_DATAH (0x00BB401C) +#define DBG_TBUS_MACTBUS_MATCH1_DATAH___RWC QCSR_REG_RW +#define DBG_TBUS_MACTBUS_MATCH1_DATAH___POR 0x00000000 +#define DBG_TBUS_MACTBUS_MATCH1_DATAH__DATA_43_32___POR 0x000 +#define DBG_TBUS_MACTBUS_MATCH1_DATAH__DATA_43_32___M 0x00000FFF +#define DBG_TBUS_MACTBUS_MATCH1_DATAH__DATA_43_32___S 0 +#define DBG_TBUS_MACTBUS_MATCH1_DATAH___M 0x00000FFF +#define DBG_TBUS_MACTBUS_MATCH1_DATAH___S 0 + +#define DBG_TBUS_MACTBUS_MATCH1_MASK (0x00BB4020) +#define DBG_TBUS_MACTBUS_MATCH1_MASK___RWC QCSR_REG_RW +#define DBG_TBUS_MACTBUS_MATCH1_MASK___POR 0xFFFFFFFF +#define DBG_TBUS_MACTBUS_MATCH1_MASK__MASK___POR 0xFFFFFFFF +#define DBG_TBUS_MACTBUS_MATCH1_MASK__MASK___M 0xFFFFFFFF +#define DBG_TBUS_MACTBUS_MATCH1_MASK__MASK___S 0 +#define DBG_TBUS_MACTBUS_MATCH1_MASK___M 0xFFFFFFFF +#define DBG_TBUS_MACTBUS_MATCH1_MASK___S 0 + +#define DBG_TBUS_MACTBUS_MATCH1_MASKH (0x00BB4024) +#define DBG_TBUS_MACTBUS_MATCH1_MASKH___RWC QCSR_REG_RW +#define DBG_TBUS_MACTBUS_MATCH1_MASKH___POR 0x00000FFF +#define DBG_TBUS_MACTBUS_MATCH1_MASKH__MASK_43_32___POR 0xFFF +#define DBG_TBUS_MACTBUS_MATCH1_MASKH__MASK_43_32___M 0x00000FFF +#define DBG_TBUS_MACTBUS_MATCH1_MASKH__MASK_43_32___S 0 +#define DBG_TBUS_MACTBUS_MATCH1_MASKH___M 0x00000FFF +#define DBG_TBUS_MACTBUS_MATCH1_MASKH___S 0 + +#define DBG_TBUS_CS_ITCTL (0x00BB4F00) +#define DBG_TBUS_CS_ITCTL___RWC QCSR_REG_RO +#define DBG_TBUS_CS_ITCTL___POR 0x00000000 +#define DBG_TBUS_CS_ITCTL__RFU___POR 0x00000000 +#define DBG_TBUS_CS_ITCTL__RFU___M 0xFFFFFFFF +#define DBG_TBUS_CS_ITCTL__RFU___S 0 +#define DBG_TBUS_CS_ITCTL___M 0xFFFFFFFF +#define DBG_TBUS_CS_ITCTL___S 0 + +#define DBG_TBUS_CS_CLAIMSET (0x00BB4FA0) +#define DBG_TBUS_CS_CLAIMSET___RWC QCSR_REG_RO +#define DBG_TBUS_CS_CLAIMSET___POR 0x00000000 +#define DBG_TBUS_CS_CLAIMSET__RFU___POR 0x00000000 +#define DBG_TBUS_CS_CLAIMSET__RFU___M 0xFFFFFFFF +#define DBG_TBUS_CS_CLAIMSET__RFU___S 0 +#define DBG_TBUS_CS_CLAIMSET___M 0xFFFFFFFF +#define DBG_TBUS_CS_CLAIMSET___S 0 + +#define DBG_TBUS_CS_CLAIMCLR (0x00BB4FA4) +#define DBG_TBUS_CS_CLAIMCLR___RWC QCSR_REG_RO +#define DBG_TBUS_CS_CLAIMCLR___POR 0x00000000 +#define DBG_TBUS_CS_CLAIMCLR__RFU___POR 0x00000000 +#define DBG_TBUS_CS_CLAIMCLR__RFU___M 0xFFFFFFFF +#define DBG_TBUS_CS_CLAIMCLR__RFU___S 0 +#define DBG_TBUS_CS_CLAIMCLR___M 0xFFFFFFFF +#define DBG_TBUS_CS_CLAIMCLR___S 0 + +#define DBG_TBUS_CS_LOCKACCESS (0x00BB4FB0) +#define DBG_TBUS_CS_LOCKACCESS___RWC QCSR_REG_RO +#define DBG_TBUS_CS_LOCKACCESS___POR 0x00000000 +#define DBG_TBUS_CS_LOCKACCESS__RFU___POR 0x00000000 +#define DBG_TBUS_CS_LOCKACCESS__RFU___M 0xFFFFFFFF +#define DBG_TBUS_CS_LOCKACCESS__RFU___S 0 +#define DBG_TBUS_CS_LOCKACCESS___M 0xFFFFFFFF +#define DBG_TBUS_CS_LOCKACCESS___S 0 + +#define DBG_TBUS_CS_LOCKSTATUS (0x00BB4FB4) +#define DBG_TBUS_CS_LOCKSTATUS___RWC QCSR_REG_RO +#define DBG_TBUS_CS_LOCKSTATUS___POR 0x00000000 +#define DBG_TBUS_CS_LOCKSTATUS__RFU___POR 0x00000000 +#define DBG_TBUS_CS_LOCKSTATUS__RFU___M 0xFFFFFFFF +#define DBG_TBUS_CS_LOCKSTATUS__RFU___S 0 +#define DBG_TBUS_CS_LOCKSTATUS___M 0xFFFFFFFF +#define DBG_TBUS_CS_LOCKSTATUS___S 0 + +#define DBG_TBUS_CS_AUTHSTATUS (0x00BB4FB8) +#define DBG_TBUS_CS_AUTHSTATUS___RWC QCSR_REG_RO +#define DBG_TBUS_CS_AUTHSTATUS__SI___M 0x000000C0 +#define DBG_TBUS_CS_AUTHSTATUS__SI___S 6 +#define DBG_TBUS_CS_AUTHSTATUS__NSI___M 0x00000030 +#define DBG_TBUS_CS_AUTHSTATUS__NSI___S 4 +#define DBG_TBUS_CS_AUTHSTATUS__SNI___M 0x0000000C +#define DBG_TBUS_CS_AUTHSTATUS__SNI___S 2 +#define DBG_TBUS_CS_AUTHSTATUS__NSNI___M 0x00000003 +#define DBG_TBUS_CS_AUTHSTATUS__NSNI___S 0 +#define DBG_TBUS_CS_AUTHSTATUS___M 0x000000FF +#define DBG_TBUS_CS_AUTHSTATUS___S 0 + +#define DBG_TBUS_CS_DEVARCH (0x00BB4FBC) +#define DBG_TBUS_CS_DEVARCH___RWC QCSR_REG_RO +#define DBG_TBUS_CS_DEVARCH___POR 0x0E100000 +#define DBG_TBUS_CS_DEVARCH__JEP106_CONT_CODE___POR 0x0 +#define DBG_TBUS_CS_DEVARCH__JEP106_IDENT_CODE___POR 0x70 +#define DBG_TBUS_CS_DEVARCH__PRESENT___POR 0x1 +#define DBG_TBUS_CS_DEVARCH__REV___POR 0x0 +#define DBG_TBUS_CS_DEVARCH__ARCHID___POR 0x0000 +#define DBG_TBUS_CS_DEVARCH__JEP106_CONT_CODE___M 0xF0000000 +#define DBG_TBUS_CS_DEVARCH__JEP106_CONT_CODE___S 28 +#define DBG_TBUS_CS_DEVARCH__JEP106_IDENT_CODE___M 0x0FE00000 +#define DBG_TBUS_CS_DEVARCH__JEP106_IDENT_CODE___S 21 +#define DBG_TBUS_CS_DEVARCH__PRESENT___M 0x00100000 +#define DBG_TBUS_CS_DEVARCH__PRESENT___S 20 +#define DBG_TBUS_CS_DEVARCH__REV___M 0x000F0000 +#define DBG_TBUS_CS_DEVARCH__REV___S 16 +#define DBG_TBUS_CS_DEVARCH__ARCHID___M 0x0000FFFF +#define DBG_TBUS_CS_DEVARCH__ARCHID___S 0 +#define DBG_TBUS_CS_DEVARCH___M 0xFFFFFFFF +#define DBG_TBUS_CS_DEVARCH___S 0 + +#define DBG_TBUS_CS_DEVICEID (0x00BB4FC8) +#define DBG_TBUS_CS_DEVICEID___RWC QCSR_REG_RO +#define DBG_TBUS_CS_DEVICEID___POR 0x00000000 +#define DBG_TBUS_CS_DEVICEID__RFU___POR 0x000000 +#define DBG_TBUS_CS_DEVICEID__DEVID___POR 0x00 +#define DBG_TBUS_CS_DEVICEID__RFU___M 0xFFFFFF00 +#define DBG_TBUS_CS_DEVICEID__RFU___S 8 +#define DBG_TBUS_CS_DEVICEID__DEVID___M 0x000000FF +#define DBG_TBUS_CS_DEVICEID__DEVID___S 0 +#define DBG_TBUS_CS_DEVICEID___M 0xFFFFFFFF +#define DBG_TBUS_CS_DEVICEID___S 0 + +#define DBG_TBUS_CS_DEVICETYPE (0x00BB4FCC) +#define DBG_TBUS_CS_DEVICETYPE___RWC QCSR_REG_RO +#define DBG_TBUS_CS_DEVICETYPE___POR 0x00000003 +#define DBG_TBUS_CS_DEVICETYPE__RFU___POR 0x000000 +#define DBG_TBUS_CS_DEVICETYPE__SUBTYPE___POR 0x0 +#define DBG_TBUS_CS_DEVICETYPE__MAJTYPE___POR 0x3 +#define DBG_TBUS_CS_DEVICETYPE__RFU___M 0xFFFFFF00 +#define DBG_TBUS_CS_DEVICETYPE__RFU___S 8 +#define DBG_TBUS_CS_DEVICETYPE__SUBTYPE___M 0x000000F0 +#define DBG_TBUS_CS_DEVICETYPE__SUBTYPE___S 4 +#define DBG_TBUS_CS_DEVICETYPE__MAJTYPE___M 0x0000000F +#define DBG_TBUS_CS_DEVICETYPE__MAJTYPE___S 0 +#define DBG_TBUS_CS_DEVICETYPE___M 0xFFFFFFFF +#define DBG_TBUS_CS_DEVICETYPE___S 0 + +#define DBG_TBUS_CS_PERIPHID4 (0x00BB4FD0) +#define DBG_TBUS_CS_PERIPHID4___RWC QCSR_REG_RO +#define DBG_TBUS_CS_PERIPHID4___POR 0x00000000 +#define DBG_TBUS_CS_PERIPHID4__RFU___POR 0x000000 +#define DBG_TBUS_CS_PERIPHID4__FIELD_4KB_COUNT___POR 0x0 +#define DBG_TBUS_CS_PERIPHID4__JEP106_CONTINUATION___POR 0x0 +#define DBG_TBUS_CS_PERIPHID4__RFU___M 0xFFFFFF00 +#define DBG_TBUS_CS_PERIPHID4__RFU___S 8 +#define DBG_TBUS_CS_PERIPHID4__FIELD_4KB_COUNT___M 0x000000F0 +#define DBG_TBUS_CS_PERIPHID4__FIELD_4KB_COUNT___S 4 +#define DBG_TBUS_CS_PERIPHID4__JEP106_CONTINUATION___M 0x0000000F +#define DBG_TBUS_CS_PERIPHID4__JEP106_CONTINUATION___S 0 +#define DBG_TBUS_CS_PERIPHID4___M 0xFFFFFFFF +#define DBG_TBUS_CS_PERIPHID4___S 0 + +#define DBG_TBUS_CS_PERIPHID5 (0x00BB4FD4) +#define DBG_TBUS_CS_PERIPHID5___RWC QCSR_REG_RO +#define DBG_TBUS_CS_PERIPHID5___POR 0x00000000 +#define DBG_TBUS_CS_PERIPHID5__RFU___POR 0x00000000 +#define DBG_TBUS_CS_PERIPHID5__RFU___M 0xFFFFFFFF +#define DBG_TBUS_CS_PERIPHID5__RFU___S 0 +#define DBG_TBUS_CS_PERIPHID5___M 0xFFFFFFFF +#define DBG_TBUS_CS_PERIPHID5___S 0 + +#define DBG_TBUS_CS_PERIPHID6 (0x00BB4FD8) +#define DBG_TBUS_CS_PERIPHID6___RWC QCSR_REG_RO +#define DBG_TBUS_CS_PERIPHID6___POR 0x00000000 +#define DBG_TBUS_CS_PERIPHID6__RFU___POR 0x00000000 +#define DBG_TBUS_CS_PERIPHID6__RFU___M 0xFFFFFFFF +#define DBG_TBUS_CS_PERIPHID6__RFU___S 0 +#define DBG_TBUS_CS_PERIPHID6___M 0xFFFFFFFF +#define DBG_TBUS_CS_PERIPHID6___S 0 + +#define DBG_TBUS_CS_PERIPHID7 (0x00BB4FDC) +#define DBG_TBUS_CS_PERIPHID7___RWC QCSR_REG_RO +#define DBG_TBUS_CS_PERIPHID7___POR 0x00000000 +#define DBG_TBUS_CS_PERIPHID7__RFU___POR 0x00000000 +#define DBG_TBUS_CS_PERIPHID7__RFU___M 0xFFFFFFFF +#define DBG_TBUS_CS_PERIPHID7__RFU___S 0 +#define DBG_TBUS_CS_PERIPHID7___M 0xFFFFFFFF +#define DBG_TBUS_CS_PERIPHID7___S 0 + +#define DBG_TBUS_CS_PERIPHID0 (0x00BB4FE0) +#define DBG_TBUS_CS_PERIPHID0___RWC QCSR_REG_RO +#define DBG_TBUS_CS_PERIPHID0___POR 0x00000000 +#define DBG_TBUS_CS_PERIPHID0__RFU___POR 0x000000 +#define DBG_TBUS_CS_PERIPHID0__PARTNUM_7_0___POR 0x0 +#define DBG_TBUS_CS_PERIPHID0__RFU___M 0xFFFFFF00 +#define DBG_TBUS_CS_PERIPHID0__RFU___S 8 +#define DBG_TBUS_CS_PERIPHID0__PARTNUM_7_0___M 0x000000FF +#define DBG_TBUS_CS_PERIPHID0__PARTNUM_7_0___S 0 +#define DBG_TBUS_CS_PERIPHID0___M 0xFFFFFFFF +#define DBG_TBUS_CS_PERIPHID0___S 0 + +#define DBG_TBUS_CS_PERIPHID1 (0x00BB4FE4) +#define DBG_TBUS_CS_PERIPHID1___RWC QCSR_REG_RO +#define DBG_TBUS_CS_PERIPHID1___POR 0x00000000 +#define DBG_TBUS_CS_PERIPHID1__RFU___POR 0x000000 +#define DBG_TBUS_CS_PERIPHID1__JEP106_ID_3_0___POR 0x0 +#define DBG_TBUS_CS_PERIPHID1__PART_NUM_11_8___POR 0x0 +#define DBG_TBUS_CS_PERIPHID1__RFU___M 0xFFFFFF00 +#define DBG_TBUS_CS_PERIPHID1__RFU___S 8 +#define DBG_TBUS_CS_PERIPHID1__JEP106_ID_3_0___M 0x000000F0 +#define DBG_TBUS_CS_PERIPHID1__JEP106_ID_3_0___S 4 +#define DBG_TBUS_CS_PERIPHID1__PART_NUM_11_8___M 0x0000000F +#define DBG_TBUS_CS_PERIPHID1__PART_NUM_11_8___S 0 +#define DBG_TBUS_CS_PERIPHID1___M 0xFFFFFFFF +#define DBG_TBUS_CS_PERIPHID1___S 0 + +#define DBG_TBUS_CS_PERIPHID2 (0x00BB4FE8) +#define DBG_TBUS_CS_PERIPHID2___RWC QCSR_REG_RO +#define DBG_TBUS_CS_PERIPHID2___POR 0x0000000F +#define DBG_TBUS_CS_PERIPHID2__RFU___POR 0x000000 +#define DBG_TBUS_CS_PERIPHID2__PERIPH_REV___POR 0x0 +#define DBG_TBUS_CS_PERIPHID2__JEP106_ASS___POR 0x1 +#define DBG_TBUS_CS_PERIPHID2__JEP106_ID_6_4___POR 0x7 +#define DBG_TBUS_CS_PERIPHID2__RFU___M 0xFFFFFF00 +#define DBG_TBUS_CS_PERIPHID2__RFU___S 8 +#define DBG_TBUS_CS_PERIPHID2__PERIPH_REV___M 0x000000F0 +#define DBG_TBUS_CS_PERIPHID2__PERIPH_REV___S 4 +#define DBG_TBUS_CS_PERIPHID2__JEP106_ASS___M 0x00000008 +#define DBG_TBUS_CS_PERIPHID2__JEP106_ASS___S 3 +#define DBG_TBUS_CS_PERIPHID2__JEP106_ID_6_4___M 0x00000007 +#define DBG_TBUS_CS_PERIPHID2__JEP106_ID_6_4___S 0 +#define DBG_TBUS_CS_PERIPHID2___M 0xFFFFFFFF +#define DBG_TBUS_CS_PERIPHID2___S 0 + +#define DBG_TBUS_CS_PERIPHID3 (0x00BB4FEC) +#define DBG_TBUS_CS_PERIPHID3___RWC QCSR_REG_RO +#define DBG_TBUS_CS_PERIPHID3___POR 0x00000000 +#define DBG_TBUS_CS_PERIPHID3__RFU___POR 0x000000 +#define DBG_TBUS_CS_PERIPHID3__REV_AND___POR 0x0 +#define DBG_TBUS_CS_PERIPHID3__MODIFIED___POR 0x0 +#define DBG_TBUS_CS_PERIPHID3__RFU___M 0xFFFFFF00 +#define DBG_TBUS_CS_PERIPHID3__RFU___S 8 +#define DBG_TBUS_CS_PERIPHID3__REV_AND___M 0x000000F0 +#define DBG_TBUS_CS_PERIPHID3__REV_AND___S 4 +#define DBG_TBUS_CS_PERIPHID3__MODIFIED___M 0x0000000F +#define DBG_TBUS_CS_PERIPHID3__MODIFIED___S 0 +#define DBG_TBUS_CS_PERIPHID3___M 0xFFFFFFFF +#define DBG_TBUS_CS_PERIPHID3___S 0 + +#define DBG_TBUS_CS_COMPID0 (0x00BB4FF0) +#define DBG_TBUS_CS_COMPID0___RWC QCSR_REG_RO +#define DBG_TBUS_CS_COMPID0___POR 0x0000000D +#define DBG_TBUS_CS_COMPID0__RFU___POR 0x000000 +#define DBG_TBUS_CS_COMPID0__PREAMBLE_7_0___POR 0x0D +#define DBG_TBUS_CS_COMPID0__RFU___M 0xFFFFFF00 +#define DBG_TBUS_CS_COMPID0__RFU___S 8 +#define DBG_TBUS_CS_COMPID0__PREAMBLE_7_0___M 0x000000FF +#define DBG_TBUS_CS_COMPID0__PREAMBLE_7_0___S 0 +#define DBG_TBUS_CS_COMPID0___M 0xFFFFFFFF +#define DBG_TBUS_CS_COMPID0___S 0 + +#define DBG_TBUS_CS_COMPID1 (0x00BB4FF4) +#define DBG_TBUS_CS_COMPID1___RWC QCSR_REG_RO +#define DBG_TBUS_CS_COMPID1___POR 0x00000090 +#define DBG_TBUS_CS_COMPID1__RFU___POR 0x000000 +#define DBG_TBUS_CS_COMPID1__PREAMBLE_15_12___POR 0x9 +#define DBG_TBUS_CS_COMPID1__PREAMBLE_11_8___POR 0x0 +#define DBG_TBUS_CS_COMPID1__RFU___M 0xFFFFFF00 +#define DBG_TBUS_CS_COMPID1__RFU___S 8 +#define DBG_TBUS_CS_COMPID1__PREAMBLE_15_12___M 0x000000F0 +#define DBG_TBUS_CS_COMPID1__PREAMBLE_15_12___S 4 +#define DBG_TBUS_CS_COMPID1__PREAMBLE_11_8___M 0x0000000F +#define DBG_TBUS_CS_COMPID1__PREAMBLE_11_8___S 0 +#define DBG_TBUS_CS_COMPID1___M 0xFFFFFFFF +#define DBG_TBUS_CS_COMPID1___S 0 + +#define DBG_TBUS_CS_COMPID2 (0x00BB4FF8) +#define DBG_TBUS_CS_COMPID2___RWC QCSR_REG_RO +#define DBG_TBUS_CS_COMPID2___POR 0x00000005 +#define DBG_TBUS_CS_COMPID2__RFU___POR 0x000000 +#define DBG_TBUS_CS_COMPID2__PREAMBLE_23_16___POR 0x05 +#define DBG_TBUS_CS_COMPID2__RFU___M 0xFFFFFF00 +#define DBG_TBUS_CS_COMPID2__RFU___S 8 +#define DBG_TBUS_CS_COMPID2__PREAMBLE_23_16___M 0x000000FF +#define DBG_TBUS_CS_COMPID2__PREAMBLE_23_16___S 0 +#define DBG_TBUS_CS_COMPID2___M 0xFFFFFFFF +#define DBG_TBUS_CS_COMPID2___S 0 + +#define DBG_TBUS_CS_COMPID3 (0x00BB4FFC) +#define DBG_TBUS_CS_COMPID3___RWC QCSR_REG_RO +#define DBG_TBUS_CS_COMPID3___POR 0x000000B1 +#define DBG_TBUS_CS_COMPID3__RFU___POR 0x000000 +#define DBG_TBUS_CS_COMPID3__PREAMBLE_31_24___POR 0xB1 +#define DBG_TBUS_CS_COMPID3__RFU___M 0xFFFFFF00 +#define DBG_TBUS_CS_COMPID3__RFU___S 8 +#define DBG_TBUS_CS_COMPID3__PREAMBLE_31_24___M 0x000000FF +#define DBG_TBUS_CS_COMPID3__PREAMBLE_31_24___S 0 +#define DBG_TBUS_CS_COMPID3___M 0xFFFFFFFF +#define DBG_TBUS_CS_COMPID3___S 0 + +#define DBG_TBUSFUN_CTRL_REG (0x00BB5000) +#define DBG_TBUSFUN_CTRL_REG___RWC QCSR_REG_RW +#define DBG_TBUSFUN_CTRL_REG___POR 0x00000300 +#define DBG_TBUSFUN_CTRL_REG__HT___POR 0x3 +#define DBG_TBUSFUN_CTRL_REG__ENS7___POR 0x0 +#define DBG_TBUSFUN_CTRL_REG__ENS6___POR 0x0 +#define DBG_TBUSFUN_CTRL_REG__ENS5___POR 0x0 +#define DBG_TBUSFUN_CTRL_REG__ENS4___POR 0x0 +#define DBG_TBUSFUN_CTRL_REG__ENS3___POR 0x0 +#define DBG_TBUSFUN_CTRL_REG__ENS2___POR 0x0 +#define DBG_TBUSFUN_CTRL_REG__ENS1___POR 0x0 +#define DBG_TBUSFUN_CTRL_REG__ENS0___POR 0x0 +#define DBG_TBUSFUN_CTRL_REG__HT___M 0x00000F00 +#define DBG_TBUSFUN_CTRL_REG__HT___S 8 +#define DBG_TBUSFUN_CTRL_REG__HT__HT_0X0 0x0 +#define DBG_TBUSFUN_CTRL_REG__HT__HT_0X1 0x1 +#define DBG_TBUSFUN_CTRL_REG__HT__HT_0X2 0x2 +#define DBG_TBUSFUN_CTRL_REG__HT__HT_0X3 0x3 +#define DBG_TBUSFUN_CTRL_REG__HT__HT_0X4 0x4 +#define DBG_TBUSFUN_CTRL_REG__HT__HT_0X5 0x5 +#define DBG_TBUSFUN_CTRL_REG__HT__HT_0X6 0x6 +#define DBG_TBUSFUN_CTRL_REG__HT__HT_0X7 0x7 +#define DBG_TBUSFUN_CTRL_REG__HT__HT_0X8 0x8 +#define DBG_TBUSFUN_CTRL_REG__HT__HT_0X9 0x9 +#define DBG_TBUSFUN_CTRL_REG__HT__HT_0XA 0xA +#define DBG_TBUSFUN_CTRL_REG__HT__HT_0XB 0xB +#define DBG_TBUSFUN_CTRL_REG__HT__HT_0XC 0xC +#define DBG_TBUSFUN_CTRL_REG__HT__HT_0XD 0xD +#define DBG_TBUSFUN_CTRL_REG__HT__HT_0XE 0xE +#define DBG_TBUSFUN_CTRL_REG__ENS7___M 0x00000080 +#define DBG_TBUSFUN_CTRL_REG__ENS7___S 7 +#define DBG_TBUSFUN_CTRL_REG__ENS7__ENS7_0 0x0 +#define DBG_TBUSFUN_CTRL_REG__ENS7__ENS7_1 0x1 +#define DBG_TBUSFUN_CTRL_REG__ENS6___M 0x00000040 +#define DBG_TBUSFUN_CTRL_REG__ENS6___S 6 +#define DBG_TBUSFUN_CTRL_REG__ENS6__ENS6_0 0x0 +#define DBG_TBUSFUN_CTRL_REG__ENS6__ENS6_1 0x1 +#define DBG_TBUSFUN_CTRL_REG__ENS5___M 0x00000020 +#define DBG_TBUSFUN_CTRL_REG__ENS5___S 5 +#define DBG_TBUSFUN_CTRL_REG__ENS5__ENS5_0 0x0 +#define DBG_TBUSFUN_CTRL_REG__ENS5__ENS5_1 0x1 +#define DBG_TBUSFUN_CTRL_REG__ENS4___M 0x00000010 +#define DBG_TBUSFUN_CTRL_REG__ENS4___S 4 +#define DBG_TBUSFUN_CTRL_REG__ENS4__ENS4_0 0x0 +#define DBG_TBUSFUN_CTRL_REG__ENS4__ENS4_1 0x1 +#define DBG_TBUSFUN_CTRL_REG__ENS3___M 0x00000008 +#define DBG_TBUSFUN_CTRL_REG__ENS3___S 3 +#define DBG_TBUSFUN_CTRL_REG__ENS3__ENS3_0 0x0 +#define DBG_TBUSFUN_CTRL_REG__ENS3__ENS3_1 0x1 +#define DBG_TBUSFUN_CTRL_REG__ENS2___M 0x00000004 +#define DBG_TBUSFUN_CTRL_REG__ENS2___S 2 +#define DBG_TBUSFUN_CTRL_REG__ENS2__ENS2_0 0x0 +#define DBG_TBUSFUN_CTRL_REG__ENS2__ENS2_1 0x1 +#define DBG_TBUSFUN_CTRL_REG__ENS1___M 0x00000002 +#define DBG_TBUSFUN_CTRL_REG__ENS1___S 1 +#define DBG_TBUSFUN_CTRL_REG__ENS1__ENS1_0 0x0 +#define DBG_TBUSFUN_CTRL_REG__ENS1__ENS1_1 0x1 +#define DBG_TBUSFUN_CTRL_REG__ENS0___M 0x00000001 +#define DBG_TBUSFUN_CTRL_REG__ENS0___S 0 +#define DBG_TBUSFUN_CTRL_REG__ENS0__ENS0_0 0x0 +#define DBG_TBUSFUN_CTRL_REG__ENS0__ENS0_1 0x1 +#define DBG_TBUSFUN_CTRL_REG___M 0x00000FFF +#define DBG_TBUSFUN_CTRL_REG___S 0 + +#define DBG_TBUSFUN_PRIORITY_CTRL_REG (0x00BB5004) +#define DBG_TBUSFUN_PRIORITY_CTRL_REG___RWC QCSR_REG_RW +#define DBG_TBUSFUN_PRIORITY_CTRL_REG___POR 0x00000000 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT7___POR 0x0 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT6___POR 0x0 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT5___POR 0x0 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT4___POR 0x0 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT3___POR 0x0 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT2___POR 0x0 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT1___POR 0x0 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT0___POR 0x0 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT7___M 0x00E00000 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT7___S 21 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_0 0x0 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_1 0x1 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_2 0x2 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_3 0x3 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_4 0x4 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_5 0x5 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_6 0x6 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_7 0x7 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT6___M 0x001C0000 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT6___S 18 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_0 0x0 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_1 0x1 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_2 0x2 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_3 0x3 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_4 0x4 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_5 0x5 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_6 0x6 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_7 0x7 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT5___M 0x00038000 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT5___S 15 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_0 0x0 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_1 0x1 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_2 0x2 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_3 0x3 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_4 0x4 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_5 0x5 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_6 0x6 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_7 0x7 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT4___M 0x00007000 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT4___S 12 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_0 0x0 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_1 0x1 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_2 0x2 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_3 0x3 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_4 0x4 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_5 0x5 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_6 0x6 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_7 0x7 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT3___M 0x00000E00 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT3___S 9 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_0 0x0 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_1 0x1 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_2 0x2 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_3 0x3 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_4 0x4 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_5 0x5 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_6 0x6 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_7 0x7 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT2___M 0x000001C0 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT2___S 6 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_0 0x0 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_1 0x1 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_2 0x2 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_3 0x3 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_4 0x4 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_5 0x5 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_6 0x6 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_7 0x7 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT1___M 0x00000038 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT1___S 3 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_0 0x0 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_1 0x1 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_2 0x2 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_3 0x3 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_4 0x4 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_5 0x5 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_6 0x6 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_7 0x7 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT0___M 0x00000007 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT0___S 0 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_0 0x0 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_1 0x1 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_2 0x2 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_3 0x3 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_4 0x4 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_5 0x5 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_6 0x6 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_7 0x7 +#define DBG_TBUSFUN_PRIORITY_CTRL_REG___M 0x00FFFFFF +#define DBG_TBUSFUN_PRIORITY_CTRL_REG___S 0 + +#define DBG_TBUSFUN_ITATBDATA0 (0x00BB5EEC) +#define DBG_TBUSFUN_ITATBDATA0___RWC QCSR_REG_RW +#define DBG_TBUSFUN_ITATBDATA0___POR 0x00000000 +#define DBG_TBUSFUN_ITATBDATA0__ATDATA31___POR 0x0 +#define DBG_TBUSFUN_ITATBDATA0__ATDATAM23___POR 0x0 +#define DBG_TBUSFUN_ITATBDATA0__ATDATA15___POR 0x0 +#define DBG_TBUSFUN_ITATBDATA0__ATDATA7___POR 0x0 +#define DBG_TBUSFUN_ITATBDATA0__ATDATA0___POR 0x0 +#define DBG_TBUSFUN_ITATBDATA0__ATDATA31___M 0x00000010 +#define DBG_TBUSFUN_ITATBDATA0__ATDATA31___S 4 +#define DBG_TBUSFUN_ITATBDATA0__ATDATA31__ATDATA31_0 0x0 +#define DBG_TBUSFUN_ITATBDATA0__ATDATA31__ATDATA31_1 0x1 +#define DBG_TBUSFUN_ITATBDATA0__ATDATAM23___M 0x00000008 +#define DBG_TBUSFUN_ITATBDATA0__ATDATAM23___S 3 +#define DBG_TBUSFUN_ITATBDATA0__ATDATAM23__ATDATAM23_0 0x0 +#define DBG_TBUSFUN_ITATBDATA0__ATDATAM23__ATDATAM23_1 0x1 +#define DBG_TBUSFUN_ITATBDATA0__ATDATA15___M 0x00000004 +#define DBG_TBUSFUN_ITATBDATA0__ATDATA15___S 2 +#define DBG_TBUSFUN_ITATBDATA0__ATDATA15__ATDATA15_0 0x0 +#define DBG_TBUSFUN_ITATBDATA0__ATDATA15__ATDATA15_1 0x1 +#define DBG_TBUSFUN_ITATBDATA0__ATDATA7___M 0x00000002 +#define DBG_TBUSFUN_ITATBDATA0__ATDATA7___S 1 +#define DBG_TBUSFUN_ITATBDATA0__ATDATA7__ATDATA7_0 0x0 +#define DBG_TBUSFUN_ITATBDATA0__ATDATA7__ATDATA7_1 0x1 +#define DBG_TBUSFUN_ITATBDATA0__ATDATA0___M 0x00000001 +#define DBG_TBUSFUN_ITATBDATA0__ATDATA0___S 0 +#define DBG_TBUSFUN_ITATBDATA0__ATDATA0__ATDATA0_0 0x0 +#define DBG_TBUSFUN_ITATBDATA0__ATDATA0__ATDATA0_1 0x1 +#define DBG_TBUSFUN_ITATBDATA0___M 0x0000001F +#define DBG_TBUSFUN_ITATBDATA0___S 0 + +#define DBG_TBUSFUN_ITATBCTR2 (0x00BB5EF0) +#define DBG_TBUSFUN_ITATBCTR2___RWC QCSR_REG_RW +#define DBG_TBUSFUN_ITATBCTR2___POR 0x00000000 +#define DBG_TBUSFUN_ITATBCTR2__AFVALID___POR 0x0 +#define DBG_TBUSFUN_ITATBCTR2__ATREADY___POR 0x0 +#define DBG_TBUSFUN_ITATBCTR2__AFVALID___M 0x00000002 +#define DBG_TBUSFUN_ITATBCTR2__AFVALID___S 1 +#define DBG_TBUSFUN_ITATBCTR2__AFVALID__AFVALID_0 0x0 +#define DBG_TBUSFUN_ITATBCTR2__AFVALID__AFVALID_1 0x1 +#define DBG_TBUSFUN_ITATBCTR2__ATREADY___M 0x00000001 +#define DBG_TBUSFUN_ITATBCTR2__ATREADY___S 0 +#define DBG_TBUSFUN_ITATBCTR2__ATREADY__ATREADY_0 0x0 +#define DBG_TBUSFUN_ITATBCTR2__ATREADY__ATREADY_1 0x1 +#define DBG_TBUSFUN_ITATBCTR2___M 0x00000003 +#define DBG_TBUSFUN_ITATBCTR2___S 0 + +#define DBG_TBUSFUN_ITATBCTR1 (0x00BB5EF4) +#define DBG_TBUSFUN_ITATBCTR1___RWC QCSR_REG_RW +#define DBG_TBUSFUN_ITATBCTR1__ATID___M 0x0000007F +#define DBG_TBUSFUN_ITATBCTR1__ATID___S 0 +#define DBG_TBUSFUN_ITATBCTR1___M 0x0000007F +#define DBG_TBUSFUN_ITATBCTR1___S 0 + +#define DBG_TBUSFUN_ITATBCTR0 (0x00BB5EF8) +#define DBG_TBUSFUN_ITATBCTR0___RWC QCSR_REG_RW +#define DBG_TBUSFUN_ITATBCTR0___POR 0x00000000 +#define DBG_TBUSFUN_ITATBCTR0__ATBYTES___POR 0x0 +#define DBG_TBUSFUN_ITATBCTR0__AFREADY___POR 0x0 +#define DBG_TBUSFUN_ITATBCTR0__ATVALID___POR 0x0 +#define DBG_TBUSFUN_ITATBCTR0__ATBYTES___M 0x00000300 +#define DBG_TBUSFUN_ITATBCTR0__ATBYTES___S 8 +#define DBG_TBUSFUN_ITATBCTR0__ATBYTES__ATBYTES_0 0x0 +#define DBG_TBUSFUN_ITATBCTR0__ATBYTES__ATBYTES_1 0x1 +#define DBG_TBUSFUN_ITATBCTR0__AFREADY___M 0x00000002 +#define DBG_TBUSFUN_ITATBCTR0__AFREADY___S 1 +#define DBG_TBUSFUN_ITATBCTR0__AFREADY__AFREADY_0 0x0 +#define DBG_TBUSFUN_ITATBCTR0__AFREADY__AFREADY_1 0x1 +#define DBG_TBUSFUN_ITATBCTR0__ATVALID___M 0x00000001 +#define DBG_TBUSFUN_ITATBCTR0__ATVALID___S 0 +#define DBG_TBUSFUN_ITATBCTR0__ATVALID__ATVALID_0 0x0 +#define DBG_TBUSFUN_ITATBCTR0__ATVALID__ATVALID_1 0x1 +#define DBG_TBUSFUN_ITATBCTR0___M 0x00000303 +#define DBG_TBUSFUN_ITATBCTR0___S 0 + +#define DBG_TBUSFUN_ITCTRL (0x00BB5F00) +#define DBG_TBUSFUN_ITCTRL___RWC QCSR_REG_RW +#define DBG_TBUSFUN_ITCTRL___POR 0x00000000 +#define DBG_TBUSFUN_ITCTRL__INTEGRATION_MODE___POR 0x0 +#define DBG_TBUSFUN_ITCTRL__INTEGRATION_MODE___M 0x00000001 +#define DBG_TBUSFUN_ITCTRL__INTEGRATION_MODE___S 0 +#define DBG_TBUSFUN_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE_0 0x0 +#define DBG_TBUSFUN_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE_1 0x1 +#define DBG_TBUSFUN_ITCTRL___M 0x00000001 +#define DBG_TBUSFUN_ITCTRL___S 0 + +#define DBG_TBUSFUN_CLAIMSET (0x00BB5FA0) +#define DBG_TBUSFUN_CLAIMSET___RWC QCSR_REG_RW +#define DBG_TBUSFUN_CLAIMSET___POR 0x0000000F +#define DBG_TBUSFUN_CLAIMSET__CLAIMSET___POR 0xF +#define DBG_TBUSFUN_CLAIMSET__CLAIMSET___M 0x0000000F +#define DBG_TBUSFUN_CLAIMSET__CLAIMSET___S 0 +#define DBG_TBUSFUN_CLAIMSET__CLAIMSET__CLAIMSET_0XF 0xF +#define DBG_TBUSFUN_CLAIMSET___M 0x0000000F +#define DBG_TBUSFUN_CLAIMSET___S 0 + +#define DBG_TBUSFUN_CLAIMCLR (0x00BB5FA4) +#define DBG_TBUSFUN_CLAIMCLR___RWC QCSR_REG_RW +#define DBG_TBUSFUN_CLAIMCLR___POR 0x00000000 +#define DBG_TBUSFUN_CLAIMCLR__CLAIMCLR___POR 0x0 +#define DBG_TBUSFUN_CLAIMCLR__CLAIMCLR___M 0x0000000F +#define DBG_TBUSFUN_CLAIMCLR__CLAIMCLR___S 0 +#define DBG_TBUSFUN_CLAIMCLR___M 0x0000000F +#define DBG_TBUSFUN_CLAIMCLR___S 0 + +#define DBG_TBUSFUN_LOCKACCESS (0x00BB5FB0) +#define DBG_TBUSFUN_LOCKACCESS___RWC QCSR_REG_WO +#define DBG_TBUSFUN_LOCKACCESS__KEY___M 0xFFFFFFFF +#define DBG_TBUSFUN_LOCKACCESS__KEY___S 0 +#define DBG_TBUSFUN_LOCKACCESS__KEY__KEY_0XC5ACCE55 0xC5ACCE55 +#define DBG_TBUSFUN_LOCKACCESS__KEY__KEY_0XDEADBEEF 0xDEADBEEF +#define DBG_TBUSFUN_LOCKACCESS___M 0xFFFFFFFF +#define DBG_TBUSFUN_LOCKACCESS___S 0 + +#define DBG_TBUSFUN_LOCKSTATUS (0x00BB5FB4) +#define DBG_TBUSFUN_LOCKSTATUS___RWC QCSR_REG_RO +#define DBG_TBUSFUN_LOCKSTATUS___POR 0x00000003 +#define DBG_TBUSFUN_LOCKSTATUS__NTT___POR 0x0 +#define DBG_TBUSFUN_LOCKSTATUS__SLK___POR 0x1 +#define DBG_TBUSFUN_LOCKSTATUS__SLI___POR 0x1 +#define DBG_TBUSFUN_LOCKSTATUS__NTT___M 0x00000004 +#define DBG_TBUSFUN_LOCKSTATUS__NTT___S 2 +#define DBG_TBUSFUN_LOCKSTATUS__NTT__NTT_0X0 0x0 +#define DBG_TBUSFUN_LOCKSTATUS__SLK___M 0x00000002 +#define DBG_TBUSFUN_LOCKSTATUS__SLK___S 1 +#define DBG_TBUSFUN_LOCKSTATUS__SLK__SLK_0X0 0x0 +#define DBG_TBUSFUN_LOCKSTATUS__SLK__SLK_0X1 0x1 +#define DBG_TBUSFUN_LOCKSTATUS__SLI___M 0x00000001 +#define DBG_TBUSFUN_LOCKSTATUS__SLI___S 0 +#define DBG_TBUSFUN_LOCKSTATUS__SLI__SLI_0X0 0x0 +#define DBG_TBUSFUN_LOCKSTATUS__SLI__SLI_0X1 0x1 +#define DBG_TBUSFUN_LOCKSTATUS___M 0x00000007 +#define DBG_TBUSFUN_LOCKSTATUS___S 0 + +#define DBG_TBUSFUN_AUTHSTATUS (0x00BB5FB8) +#define DBG_TBUSFUN_AUTHSTATUS___RWC QCSR_REG_RO +#define DBG_TBUSFUN_AUTHSTATUS___POR 0x00000000 +#define DBG_TBUSFUN_AUTHSTATUS__SNID___POR 0x0 +#define DBG_TBUSFUN_AUTHSTATUS__SID___POR 0x0 +#define DBG_TBUSFUN_AUTHSTATUS__NSNID___POR 0x0 +#define DBG_TBUSFUN_AUTHSTATUS__NSID___POR 0x0 +#define DBG_TBUSFUN_AUTHSTATUS__SNID___M 0x000000C0 +#define DBG_TBUSFUN_AUTHSTATUS__SNID___S 6 +#define DBG_TBUSFUN_AUTHSTATUS__SNID__SNID_0X0 0x0 +#define DBG_TBUSFUN_AUTHSTATUS__SID___M 0x00000030 +#define DBG_TBUSFUN_AUTHSTATUS__SID___S 4 +#define DBG_TBUSFUN_AUTHSTATUS__SID__SID_0X0 0x0 +#define DBG_TBUSFUN_AUTHSTATUS__NSNID___M 0x0000000C +#define DBG_TBUSFUN_AUTHSTATUS__NSNID___S 2 +#define DBG_TBUSFUN_AUTHSTATUS__NSNID__NSNID_0X0 0x0 +#define DBG_TBUSFUN_AUTHSTATUS__NSID___M 0x00000003 +#define DBG_TBUSFUN_AUTHSTATUS__NSID___S 0 +#define DBG_TBUSFUN_AUTHSTATUS__NSID__NSID_0X0 0x0 +#define DBG_TBUSFUN_AUTHSTATUS___M 0x000000FF +#define DBG_TBUSFUN_AUTHSTATUS___S 0 + +#define DBG_TBUSFUN_DEVID (0x00BB5FC8) +#define DBG_TBUSFUN_DEVID___RWC QCSR_REG_RO +#define DBG_TBUSFUN_DEVID___POR 0x00000038 +#define DBG_TBUSFUN_DEVID__SCHEME___POR 0x3 +#define DBG_TBUSFUN_DEVID__PORTCOUNT___POR 0x8 +#define DBG_TBUSFUN_DEVID__SCHEME___M 0x000000F0 +#define DBG_TBUSFUN_DEVID__SCHEME___S 4 +#define DBG_TBUSFUN_DEVID__SCHEME__SCHEME_0X3 0x3 +#define DBG_TBUSFUN_DEVID__PORTCOUNT___M 0x0000000F +#define DBG_TBUSFUN_DEVID__PORTCOUNT___S 0 +#define DBG_TBUSFUN_DEVID__PORTCOUNT__PORTCOUNT_0X2 0x2 +#define DBG_TBUSFUN_DEVID__PORTCOUNT__PORTCOUNT_0X3 0x3 +#define DBG_TBUSFUN_DEVID__PORTCOUNT__PORTCOUNT_0X4 0x4 +#define DBG_TBUSFUN_DEVID__PORTCOUNT__PORTCOUNT_0X5 0x5 +#define DBG_TBUSFUN_DEVID__PORTCOUNT__PORTCOUNT_0X6 0x6 +#define DBG_TBUSFUN_DEVID__PORTCOUNT__PORTCOUNT_0X7 0x7 +#define DBG_TBUSFUN_DEVID__PORTCOUNT__PORTCOUNT_0X8 0x8 +#define DBG_TBUSFUN_DEVID___M 0x000000FF +#define DBG_TBUSFUN_DEVID___S 0 + +#define DBG_TBUSFUN_DEVTYPE (0x00BB5FCC) +#define DBG_TBUSFUN_DEVTYPE___RWC QCSR_REG_RO +#define DBG_TBUSFUN_DEVTYPE___POR 0x00000012 +#define DBG_TBUSFUN_DEVTYPE__SUB_TYPE___POR 0x1 +#define DBG_TBUSFUN_DEVTYPE__MAJOR_TYPE___POR 0x2 +#define DBG_TBUSFUN_DEVTYPE__SUB_TYPE___M 0x000000F0 +#define DBG_TBUSFUN_DEVTYPE__SUB_TYPE___S 4 +#define DBG_TBUSFUN_DEVTYPE__SUB_TYPE__SUB_TYPE_0X1 0x1 +#define DBG_TBUSFUN_DEVTYPE__MAJOR_TYPE___M 0x0000000F +#define DBG_TBUSFUN_DEVTYPE__MAJOR_TYPE___S 0 +#define DBG_TBUSFUN_DEVTYPE__MAJOR_TYPE__MAJOR_TYPE_0X2 0x2 +#define DBG_TBUSFUN_DEVTYPE___M 0x000000FF +#define DBG_TBUSFUN_DEVTYPE___S 0 + +#define DBG_TBUSFUN_PIDR0 (0x00BB5FE0) +#define DBG_TBUSFUN_PIDR0___RWC QCSR_REG_RO +#define DBG_TBUSFUN_PIDR0___POR 0x00000008 +#define DBG_TBUSFUN_PIDR0__PART_NUMBER_BITS7TO0___POR 0x08 +#define DBG_TBUSFUN_PIDR0__PART_NUMBER_BITS7TO0___M 0x000000FF +#define DBG_TBUSFUN_PIDR0__PART_NUMBER_BITS7TO0___S 0 +#define DBG_TBUSFUN_PIDR0__PART_NUMBER_BITS7TO0__PART_NUMBER_BITS7TO0_0X08 0x08 +#define DBG_TBUSFUN_PIDR0___M 0x000000FF +#define DBG_TBUSFUN_PIDR0___S 0 + +#define DBG_TBUSFUN_PIDR1 (0x00BB5FE4) +#define DBG_TBUSFUN_PIDR1___RWC QCSR_REG_RO +#define DBG_TBUSFUN_PIDR1___POR 0x000000B9 +#define DBG_TBUSFUN_PIDR1__JEP106_BITS3TO0___POR 0xB +#define DBG_TBUSFUN_PIDR1__PART_NUMBER_BITS11TO8___POR 0x9 +#define DBG_TBUSFUN_PIDR1__JEP106_BITS3TO0___M 0x000000F0 +#define DBG_TBUSFUN_PIDR1__JEP106_BITS3TO0___S 4 +#define DBG_TBUSFUN_PIDR1__JEP106_BITS3TO0__JEP106_BITS3TO0_0XB 0xB +#define DBG_TBUSFUN_PIDR1__PART_NUMBER_BITS11TO8___M 0x0000000F +#define DBG_TBUSFUN_PIDR1__PART_NUMBER_BITS11TO8___S 0 +#define DBG_TBUSFUN_PIDR1__PART_NUMBER_BITS11TO8__PART_NUMBER_BITS11TO8_0X9 0x9 +#define DBG_TBUSFUN_PIDR1___M 0x000000FF +#define DBG_TBUSFUN_PIDR1___S 0 + +#define DBG_TBUSFUN_PIDR2 (0x00BB5FE8) +#define DBG_TBUSFUN_PIDR2___RWC QCSR_REG_RO +#define DBG_TBUSFUN_PIDR2___POR 0x0000003B +#define DBG_TBUSFUN_PIDR2__REVISION___POR 0x3 +#define DBG_TBUSFUN_PIDR2__JEDEC___POR 0x1 +#define DBG_TBUSFUN_PIDR2__JEP106_BITS6TO4___POR 0x3 +#define DBG_TBUSFUN_PIDR2__REVISION___M 0x000000F0 +#define DBG_TBUSFUN_PIDR2__REVISION___S 4 +#define DBG_TBUSFUN_PIDR2__REVISION__REVISION_0X3 0x3 +#define DBG_TBUSFUN_PIDR2__JEDEC___M 0x00000008 +#define DBG_TBUSFUN_PIDR2__JEDEC___S 3 +#define DBG_TBUSFUN_PIDR2__JEDEC__JEDEC_0X1 0x1 +#define DBG_TBUSFUN_PIDR2__JEP106_BITS6TO4___M 0x00000007 +#define DBG_TBUSFUN_PIDR2__JEP106_BITS6TO4___S 0 +#define DBG_TBUSFUN_PIDR2__JEP106_BITS6TO4__JEP106_BITS6TO4_0X3 0x3 +#define DBG_TBUSFUN_PIDR2___M 0x000000FF +#define DBG_TBUSFUN_PIDR2___S 0 + +#define DBG_TBUSFUN_PIDR3 (0x00BB5FEC) +#define DBG_TBUSFUN_PIDR3___RWC QCSR_REG_RO +#define DBG_TBUSFUN_PIDR3___POR 0x00000000 +#define DBG_TBUSFUN_PIDR3__REVAND___POR 0x0 +#define DBG_TBUSFUN_PIDR3__CUSTOMER_MODIFIED___POR 0x0 +#define DBG_TBUSFUN_PIDR3__REVAND___M 0x000000F0 +#define DBG_TBUSFUN_PIDR3__REVAND___S 4 +#define DBG_TBUSFUN_PIDR3__REVAND__REVAND_0X0 0x0 +#define DBG_TBUSFUN_PIDR3__CUSTOMER_MODIFIED___M 0x0000000F +#define DBG_TBUSFUN_PIDR3__CUSTOMER_MODIFIED___S 0 +#define DBG_TBUSFUN_PIDR3__CUSTOMER_MODIFIED__CUSTOMER_MODIFIED_0X0 0x0 +#define DBG_TBUSFUN_PIDR3___M 0x000000FF +#define DBG_TBUSFUN_PIDR3___S 0 + +#define DBG_TBUSFUN_PIDR4 (0x00BB5FD0) +#define DBG_TBUSFUN_PIDR4___RWC QCSR_REG_RO +#define DBG_TBUSFUN_PIDR4___POR 0x00000004 +#define DBG_TBUSFUN_PIDR4__FOURKB_COUNT___POR 0x0 +#define DBG_TBUSFUN_PIDR4__JEP106_CONT___POR 0x4 +#define DBG_TBUSFUN_PIDR4__FOURKB_COUNT___M 0x000000F0 +#define DBG_TBUSFUN_PIDR4__FOURKB_COUNT___S 4 +#define DBG_TBUSFUN_PIDR4__FOURKB_COUNT__FOURKB_COUNT_0X0 0x0 +#define DBG_TBUSFUN_PIDR4__JEP106_CONT___M 0x0000000F +#define DBG_TBUSFUN_PIDR4__JEP106_CONT___S 0 +#define DBG_TBUSFUN_PIDR4__JEP106_CONT__JEP106_CONT_0X4 0x4 +#define DBG_TBUSFUN_PIDR4___M 0x000000FF +#define DBG_TBUSFUN_PIDR4___S 0 + +#define DBG_TBUSFUN_PERIPHID5 (0x00BB5FD4) +#define DBG_TBUSFUN_PERIPHID5___RWC QCSR_REG_RO +#define DBG_TBUSFUN_PERIPHID5___POR 0x00000000 +#define DBG_TBUSFUN_PERIPHID5__PERIPHID5___POR 0x00000000 +#define DBG_TBUSFUN_PERIPHID5__PERIPHID5___M 0xFFFFFFFF +#define DBG_TBUSFUN_PERIPHID5__PERIPHID5___S 0 +#define DBG_TBUSFUN_PERIPHID5___M 0xFFFFFFFF +#define DBG_TBUSFUN_PERIPHID5___S 0 + +#define DBG_TBUSFUN_PERIPHID6 (0x00BB5FD8) +#define DBG_TBUSFUN_PERIPHID6___RWC QCSR_REG_RO +#define DBG_TBUSFUN_PERIPHID6___POR 0x00000000 +#define DBG_TBUSFUN_PERIPHID6__PERIPHID6___POR 0x00000000 +#define DBG_TBUSFUN_PERIPHID6__PERIPHID6___M 0xFFFFFFFF +#define DBG_TBUSFUN_PERIPHID6__PERIPHID6___S 0 +#define DBG_TBUSFUN_PERIPHID6___M 0xFFFFFFFF +#define DBG_TBUSFUN_PERIPHID6___S 0 + +#define DBG_TBUSFUN_PERIPHID7 (0x00BB5FDC) +#define DBG_TBUSFUN_PERIPHID7___RWC QCSR_REG_RO +#define DBG_TBUSFUN_PERIPHID7___POR 0x00000000 +#define DBG_TBUSFUN_PERIPHID7__PERIPHID7___POR 0x00000000 +#define DBG_TBUSFUN_PERIPHID7__PERIPHID7___M 0xFFFFFFFF +#define DBG_TBUSFUN_PERIPHID7__PERIPHID7___S 0 +#define DBG_TBUSFUN_PERIPHID7___M 0xFFFFFFFF +#define DBG_TBUSFUN_PERIPHID7___S 0 + +#define DBG_TBUSFUN_CID0 (0x00BB5FF0) +#define DBG_TBUSFUN_CID0___RWC QCSR_REG_RO +#define DBG_TBUSFUN_CID0___POR 0x0000000D +#define DBG_TBUSFUN_CID0__PREAMBLE___POR 0x0D +#define DBG_TBUSFUN_CID0__PREAMBLE___M 0x000000FF +#define DBG_TBUSFUN_CID0__PREAMBLE___S 0 +#define DBG_TBUSFUN_CID0__PREAMBLE__PREAMBLE_0X0D 0x0D +#define DBG_TBUSFUN_CID0___M 0x000000FF +#define DBG_TBUSFUN_CID0___S 0 + +#define DBG_TBUSFUN_CID1 (0x00BB5FF4) +#define DBG_TBUSFUN_CID1___RWC QCSR_REG_RO +#define DBG_TBUSFUN_CID1___POR 0x00000090 +#define DBG_TBUSFUN_CID1__CLASS___POR 0x9 +#define DBG_TBUSFUN_CID1__PREAMBLE___POR 0x0 +#define DBG_TBUSFUN_CID1__CLASS___M 0x000000F0 +#define DBG_TBUSFUN_CID1__CLASS___S 4 +#define DBG_TBUSFUN_CID1__CLASS__CLASS_0X9 0x9 +#define DBG_TBUSFUN_CID1__PREAMBLE___M 0x0000000F +#define DBG_TBUSFUN_CID1__PREAMBLE___S 0 +#define DBG_TBUSFUN_CID1__PREAMBLE__PREAMBLE_0X0 0x0 +#define DBG_TBUSFUN_CID1___M 0x000000FF +#define DBG_TBUSFUN_CID1___S 0 + +#define DBG_TBUSFUN_CID2 (0x00BB5FF8) +#define DBG_TBUSFUN_CID2___RWC QCSR_REG_RO +#define DBG_TBUSFUN_CID2___POR 0x00000005 +#define DBG_TBUSFUN_CID2__PREAMBLE___POR 0x05 +#define DBG_TBUSFUN_CID2__PREAMBLE___M 0x000000FF +#define DBG_TBUSFUN_CID2__PREAMBLE___S 0 +#define DBG_TBUSFUN_CID2__PREAMBLE__PREAMBLE_0X05 0x05 +#define DBG_TBUSFUN_CID2___M 0x000000FF +#define DBG_TBUSFUN_CID2___S 0 + +#define DBG_TBUSFUN_CID3 (0x00BB5FFC) +#define DBG_TBUSFUN_CID3___RWC QCSR_REG_RO +#define DBG_TBUSFUN_CID3___POR 0x000000B1 +#define DBG_TBUSFUN_CID3__PREAMBLE___POR 0xB1 +#define DBG_TBUSFUN_CID3__PREAMBLE___M 0x000000FF +#define DBG_TBUSFUN_CID3__PREAMBLE___S 0 +#define DBG_TBUSFUN_CID3__PREAMBLE__PREAMBLE_0XB1 0xB1 +#define DBG_TBUSFUN_CID3___M 0x000000FF +#define DBG_TBUSFUN_CID3___S 0 + +#define DBG_CTIMAC_CTICONTROL (0x00BB6000) +#define DBG_CTIMAC_CTICONTROL___RWC QCSR_REG_RW +#define DBG_CTIMAC_CTICONTROL___POR 0x00000000 +#define DBG_CTIMAC_CTICONTROL__GLBEN___POR 0x0 +#define DBG_CTIMAC_CTICONTROL__GLBEN___M 0x00000001 +#define DBG_CTIMAC_CTICONTROL__GLBEN___S 0 +#define DBG_CTIMAC_CTICONTROL__GLBEN__DISABLED 0x0 +#define DBG_CTIMAC_CTICONTROL__GLBEN__ENABLED 0x1 +#define DBG_CTIMAC_CTICONTROL___M 0x00000001 +#define DBG_CTIMAC_CTICONTROL___S 0 + +#define DBG_CTIMAC_CTIINTACK (0x00BB6010) +#define DBG_CTIMAC_CTIINTACK___RWC QCSR_REG_WO +#define DBG_CTIMAC_CTIINTACK___POR 0x00000000 +#define DBG_CTIMAC_CTIINTACK__INTACK___POR 0x000 +#define DBG_CTIMAC_CTIINTACK__INTACK___M 0x00000FFF +#define DBG_CTIMAC_CTIINTACK__INTACK___S 0 +#define DBG_CTIMAC_CTIINTACK___M 0x00000FFF +#define DBG_CTIMAC_CTIINTACK___S 0 + +#define DBG_CTIMAC_CTIAPPSET (0x00BB6014) +#define DBG_CTIMAC_CTIAPPSET___RWC QCSR_REG_RW +#define DBG_CTIMAC_CTIAPPSET___POR 0x00000000 +#define DBG_CTIMAC_CTIAPPSET__APPSET___POR 0x00 +#define DBG_CTIMAC_CTIAPPSET__APPSET___M 0x000000FF +#define DBG_CTIMAC_CTIAPPSET__APPSET___S 0 +#define DBG_CTIMAC_CTIAPPSET___M 0x000000FF +#define DBG_CTIMAC_CTIAPPSET___S 0 + +#define DBG_CTIMAC_CTIAPPCLEAR (0x00BB6018) +#define DBG_CTIMAC_CTIAPPCLEAR___RWC QCSR_REG_WO +#define DBG_CTIMAC_CTIAPPCLEAR___POR 0x00000000 +#define DBG_CTIMAC_CTIAPPCLEAR__APPCLEAR___POR 0x00 +#define DBG_CTIMAC_CTIAPPCLEAR__APPCLEAR___M 0x000000FF +#define DBG_CTIMAC_CTIAPPCLEAR__APPCLEAR___S 0 +#define DBG_CTIMAC_CTIAPPCLEAR___M 0x000000FF +#define DBG_CTIMAC_CTIAPPCLEAR___S 0 + +#define DBG_CTIMAC_CTIAPPPULSE (0x00BB601C) +#define DBG_CTIMAC_CTIAPPPULSE___RWC QCSR_REG_WO +#define DBG_CTIMAC_CTIAPPPULSE___POR 0x00000000 +#define DBG_CTIMAC_CTIAPPPULSE__APPULSE___POR 0x00 +#define DBG_CTIMAC_CTIAPPPULSE__APPULSE___M 0x000000FF +#define DBG_CTIMAC_CTIAPPPULSE__APPULSE___S 0 +#define DBG_CTIMAC_CTIAPPPULSE___M 0x000000FF +#define DBG_CTIMAC_CTIAPPPULSE___S 0 + +#define DBG_CTIMAC_CTIINEN0 (0x00BB6020) +#define DBG_CTIMAC_CTIINEN0___RWC QCSR_REG_RW +#define DBG_CTIMAC_CTIINEN0___POR 0x00000000 +#define DBG_CTIMAC_CTIINEN0__TRIGINEN___POR 0x00 +#define DBG_CTIMAC_CTIINEN0__TRIGINEN___M 0x000000FF +#define DBG_CTIMAC_CTIINEN0__TRIGINEN___S 0 +#define DBG_CTIMAC_CTIINEN0___M 0x000000FF +#define DBG_CTIMAC_CTIINEN0___S 0 + +#define DBG_CTIMAC_CTIINEN1 (0x00BB6024) +#define DBG_CTIMAC_CTIINEN1___RWC QCSR_REG_RW +#define DBG_CTIMAC_CTIINEN1___POR 0x00000000 +#define DBG_CTIMAC_CTIINEN1__TRIGINEN___POR 0x00 +#define DBG_CTIMAC_CTIINEN1__TRIGINEN___M 0x000000FF +#define DBG_CTIMAC_CTIINEN1__TRIGINEN___S 0 +#define DBG_CTIMAC_CTIINEN1___M 0x000000FF +#define DBG_CTIMAC_CTIINEN1___S 0 + +#define DBG_CTIMAC_CTIINEN2 (0x00BB6028) +#define DBG_CTIMAC_CTIINEN2___RWC QCSR_REG_RW +#define DBG_CTIMAC_CTIINEN2___POR 0x00000000 +#define DBG_CTIMAC_CTIINEN2__TRIGINEN___POR 0x00 +#define DBG_CTIMAC_CTIINEN2__TRIGINEN___M 0x000000FF +#define DBG_CTIMAC_CTIINEN2__TRIGINEN___S 0 +#define DBG_CTIMAC_CTIINEN2___M 0x000000FF +#define DBG_CTIMAC_CTIINEN2___S 0 + +#define DBG_CTIMAC_CTIINEN3 (0x00BB602C) +#define DBG_CTIMAC_CTIINEN3___RWC QCSR_REG_RW +#define DBG_CTIMAC_CTIINEN3___POR 0x00000000 +#define DBG_CTIMAC_CTIINEN3__TRIGINEN___POR 0x00 +#define DBG_CTIMAC_CTIINEN3__TRIGINEN___M 0x000000FF +#define DBG_CTIMAC_CTIINEN3__TRIGINEN___S 0 +#define DBG_CTIMAC_CTIINEN3___M 0x000000FF +#define DBG_CTIMAC_CTIINEN3___S 0 + +#define DBG_CTIMAC_CTIINEN4 (0x00BB6030) +#define DBG_CTIMAC_CTIINEN4___RWC QCSR_REG_RW +#define DBG_CTIMAC_CTIINEN4___POR 0x00000000 +#define DBG_CTIMAC_CTIINEN4__TRIGINEN___POR 0x00 +#define DBG_CTIMAC_CTIINEN4__TRIGINEN___M 0x000000FF +#define DBG_CTIMAC_CTIINEN4__TRIGINEN___S 0 +#define DBG_CTIMAC_CTIINEN4___M 0x000000FF +#define DBG_CTIMAC_CTIINEN4___S 0 + +#define DBG_CTIMAC_CTIINEN5 (0x00BB6034) +#define DBG_CTIMAC_CTIINEN5___RWC QCSR_REG_RW +#define DBG_CTIMAC_CTIINEN5___POR 0x00000000 +#define DBG_CTIMAC_CTIINEN5__TRIGINEN___POR 0x00 +#define DBG_CTIMAC_CTIINEN5__TRIGINEN___M 0x000000FF +#define DBG_CTIMAC_CTIINEN5__TRIGINEN___S 0 +#define DBG_CTIMAC_CTIINEN5___M 0x000000FF +#define DBG_CTIMAC_CTIINEN5___S 0 + +#define DBG_CTIMAC_CTIINEN6 (0x00BB6038) +#define DBG_CTIMAC_CTIINEN6___RWC QCSR_REG_RW +#define DBG_CTIMAC_CTIINEN6___POR 0x00000000 +#define DBG_CTIMAC_CTIINEN6__TRIGINEN___POR 0x00 +#define DBG_CTIMAC_CTIINEN6__TRIGINEN___M 0x000000FF +#define DBG_CTIMAC_CTIINEN6__TRIGINEN___S 0 +#define DBG_CTIMAC_CTIINEN6___M 0x000000FF +#define DBG_CTIMAC_CTIINEN6___S 0 + +#define DBG_CTIMAC_CTIINEN7 (0x00BB603C) +#define DBG_CTIMAC_CTIINEN7___RWC QCSR_REG_RW +#define DBG_CTIMAC_CTIINEN7___POR 0x00000000 +#define DBG_CTIMAC_CTIINEN7__TRIGINEN___POR 0x00 +#define DBG_CTIMAC_CTIINEN7__TRIGINEN___M 0x000000FF +#define DBG_CTIMAC_CTIINEN7__TRIGINEN___S 0 +#define DBG_CTIMAC_CTIINEN7___M 0x000000FF +#define DBG_CTIMAC_CTIINEN7___S 0 + +#define DBG_CTIMAC_CTIINEN8 (0x00BB6040) +#define DBG_CTIMAC_CTIINEN8___RWC QCSR_REG_RW +#define DBG_CTIMAC_CTIINEN8___POR 0x00000000 +#define DBG_CTIMAC_CTIINEN8__TRIGINEN___POR 0x00 +#define DBG_CTIMAC_CTIINEN8__TRIGINEN___M 0x000000FF +#define DBG_CTIMAC_CTIINEN8__TRIGINEN___S 0 +#define DBG_CTIMAC_CTIINEN8___M 0x000000FF +#define DBG_CTIMAC_CTIINEN8___S 0 + +#define DBG_CTIMAC_CTIINEN9 (0x00BB6044) +#define DBG_CTIMAC_CTIINEN9___RWC QCSR_REG_RW +#define DBG_CTIMAC_CTIINEN9___POR 0x00000000 +#define DBG_CTIMAC_CTIINEN9__TRIGINEN___POR 0x00 +#define DBG_CTIMAC_CTIINEN9__TRIGINEN___M 0x000000FF +#define DBG_CTIMAC_CTIINEN9__TRIGINEN___S 0 +#define DBG_CTIMAC_CTIINEN9___M 0x000000FF +#define DBG_CTIMAC_CTIINEN9___S 0 + +#define DBG_CTIMAC_CTIINEN10 (0x00BB6048) +#define DBG_CTIMAC_CTIINEN10___RWC QCSR_REG_RW +#define DBG_CTIMAC_CTIINEN10___POR 0x00000000 +#define DBG_CTIMAC_CTIINEN10__TRIGINEN___POR 0x00 +#define DBG_CTIMAC_CTIINEN10__TRIGINEN___M 0x000000FF +#define DBG_CTIMAC_CTIINEN10__TRIGINEN___S 0 +#define DBG_CTIMAC_CTIINEN10___M 0x000000FF +#define DBG_CTIMAC_CTIINEN10___S 0 + +#define DBG_CTIMAC_CTIINEN11 (0x00BB604C) +#define DBG_CTIMAC_CTIINEN11___RWC QCSR_REG_RW +#define DBG_CTIMAC_CTIINEN11___POR 0x00000000 +#define DBG_CTIMAC_CTIINEN11__TRIGINEN___POR 0x00 +#define DBG_CTIMAC_CTIINEN11__TRIGINEN___M 0x000000FF +#define DBG_CTIMAC_CTIINEN11__TRIGINEN___S 0 +#define DBG_CTIMAC_CTIINEN11___M 0x000000FF +#define DBG_CTIMAC_CTIINEN11___S 0 + +#define DBG_CTIMAC_CTIOUTEN0 (0x00BB60A0) +#define DBG_CTIMAC_CTIOUTEN0___RWC QCSR_REG_RW +#define DBG_CTIMAC_CTIOUTEN0___POR 0x00000000 +#define DBG_CTIMAC_CTIOUTEN0__TRIGOUTEN___POR 0x00 +#define DBG_CTIMAC_CTIOUTEN0__TRIGOUTEN___M 0x000000FF +#define DBG_CTIMAC_CTIOUTEN0__TRIGOUTEN___S 0 +#define DBG_CTIMAC_CTIOUTEN0___M 0x000000FF +#define DBG_CTIMAC_CTIOUTEN0___S 0 + +#define DBG_CTIMAC_CTIOUTEN1 (0x00BB60A4) +#define DBG_CTIMAC_CTIOUTEN1___RWC QCSR_REG_RW +#define DBG_CTIMAC_CTIOUTEN1___POR 0x00000000 +#define DBG_CTIMAC_CTIOUTEN1__TRIGOUTEN___POR 0x00 +#define DBG_CTIMAC_CTIOUTEN1__TRIGOUTEN___M 0x000000FF +#define DBG_CTIMAC_CTIOUTEN1__TRIGOUTEN___S 0 +#define DBG_CTIMAC_CTIOUTEN1___M 0x000000FF +#define DBG_CTIMAC_CTIOUTEN1___S 0 + +#define DBG_CTIMAC_CTIOUTEN2 (0x00BB60A8) +#define DBG_CTIMAC_CTIOUTEN2___RWC QCSR_REG_RW +#define DBG_CTIMAC_CTIOUTEN2___POR 0x00000000 +#define DBG_CTIMAC_CTIOUTEN2__TRIGOUTEN___POR 0x00 +#define DBG_CTIMAC_CTIOUTEN2__TRIGOUTEN___M 0x000000FF +#define DBG_CTIMAC_CTIOUTEN2__TRIGOUTEN___S 0 +#define DBG_CTIMAC_CTIOUTEN2___M 0x000000FF +#define DBG_CTIMAC_CTIOUTEN2___S 0 + +#define DBG_CTIMAC_CTIOUTEN3 (0x00BB60AC) +#define DBG_CTIMAC_CTIOUTEN3___RWC QCSR_REG_RW +#define DBG_CTIMAC_CTIOUTEN3___POR 0x00000000 +#define DBG_CTIMAC_CTIOUTEN3__TRIGOUTEN___POR 0x00 +#define DBG_CTIMAC_CTIOUTEN3__TRIGOUTEN___M 0x000000FF +#define DBG_CTIMAC_CTIOUTEN3__TRIGOUTEN___S 0 +#define DBG_CTIMAC_CTIOUTEN3___M 0x000000FF +#define DBG_CTIMAC_CTIOUTEN3___S 0 + +#define DBG_CTIMAC_CTIOUTEN4 (0x00BB60B0) +#define DBG_CTIMAC_CTIOUTEN4___RWC QCSR_REG_RW +#define DBG_CTIMAC_CTIOUTEN4___POR 0x00000000 +#define DBG_CTIMAC_CTIOUTEN4__TRIGOUTEN___POR 0x00 +#define DBG_CTIMAC_CTIOUTEN4__TRIGOUTEN___M 0x000000FF +#define DBG_CTIMAC_CTIOUTEN4__TRIGOUTEN___S 0 +#define DBG_CTIMAC_CTIOUTEN4___M 0x000000FF +#define DBG_CTIMAC_CTIOUTEN4___S 0 + +#define DBG_CTIMAC_CTIOUTEN5 (0x00BB60B4) +#define DBG_CTIMAC_CTIOUTEN5___RWC QCSR_REG_RW +#define DBG_CTIMAC_CTIOUTEN5___POR 0x00000000 +#define DBG_CTIMAC_CTIOUTEN5__TRIGOUTEN___POR 0x00 +#define DBG_CTIMAC_CTIOUTEN5__TRIGOUTEN___M 0x000000FF +#define DBG_CTIMAC_CTIOUTEN5__TRIGOUTEN___S 0 +#define DBG_CTIMAC_CTIOUTEN5___M 0x000000FF +#define DBG_CTIMAC_CTIOUTEN5___S 0 + +#define DBG_CTIMAC_CTIOUTEN6 (0x00BB60B8) +#define DBG_CTIMAC_CTIOUTEN6___RWC QCSR_REG_RW +#define DBG_CTIMAC_CTIOUTEN6___POR 0x00000000 +#define DBG_CTIMAC_CTIOUTEN6__TRIGOUTEN___POR 0x00 +#define DBG_CTIMAC_CTIOUTEN6__TRIGOUTEN___M 0x000000FF +#define DBG_CTIMAC_CTIOUTEN6__TRIGOUTEN___S 0 +#define DBG_CTIMAC_CTIOUTEN6___M 0x000000FF +#define DBG_CTIMAC_CTIOUTEN6___S 0 + +#define DBG_CTIMAC_CTIOUTEN7 (0x00BB60BC) +#define DBG_CTIMAC_CTIOUTEN7___RWC QCSR_REG_RW +#define DBG_CTIMAC_CTIOUTEN7___POR 0x00000000 +#define DBG_CTIMAC_CTIOUTEN7__TRIGOUTEN___POR 0x00 +#define DBG_CTIMAC_CTIOUTEN7__TRIGOUTEN___M 0x000000FF +#define DBG_CTIMAC_CTIOUTEN7__TRIGOUTEN___S 0 +#define DBG_CTIMAC_CTIOUTEN7___M 0x000000FF +#define DBG_CTIMAC_CTIOUTEN7___S 0 + +#define DBG_CTIMAC_CTIOUTEN8 (0x00BB60C0) +#define DBG_CTIMAC_CTIOUTEN8___RWC QCSR_REG_RW +#define DBG_CTIMAC_CTIOUTEN8___POR 0x00000000 +#define DBG_CTIMAC_CTIOUTEN8__TRIGOUTEN___POR 0x00 +#define DBG_CTIMAC_CTIOUTEN8__TRIGOUTEN___M 0x000000FF +#define DBG_CTIMAC_CTIOUTEN8__TRIGOUTEN___S 0 +#define DBG_CTIMAC_CTIOUTEN8___M 0x000000FF +#define DBG_CTIMAC_CTIOUTEN8___S 0 + +#define DBG_CTIMAC_CTIOUTEN9 (0x00BB60C4) +#define DBG_CTIMAC_CTIOUTEN9___RWC QCSR_REG_RW +#define DBG_CTIMAC_CTIOUTEN9___POR 0x00000000 +#define DBG_CTIMAC_CTIOUTEN9__TRIGOUTEN___POR 0x00 +#define DBG_CTIMAC_CTIOUTEN9__TRIGOUTEN___M 0x000000FF +#define DBG_CTIMAC_CTIOUTEN9__TRIGOUTEN___S 0 +#define DBG_CTIMAC_CTIOUTEN9___M 0x000000FF +#define DBG_CTIMAC_CTIOUTEN9___S 0 + +#define DBG_CTIMAC_CTIOUTEN10 (0x00BB60C8) +#define DBG_CTIMAC_CTIOUTEN10___RWC QCSR_REG_RW +#define DBG_CTIMAC_CTIOUTEN10___POR 0x00000000 +#define DBG_CTIMAC_CTIOUTEN10__TRIGOUTEN___POR 0x00 +#define DBG_CTIMAC_CTIOUTEN10__TRIGOUTEN___M 0x000000FF +#define DBG_CTIMAC_CTIOUTEN10__TRIGOUTEN___S 0 +#define DBG_CTIMAC_CTIOUTEN10___M 0x000000FF +#define DBG_CTIMAC_CTIOUTEN10___S 0 + +#define DBG_CTIMAC_CTIOUTEN11 (0x00BB60CC) +#define DBG_CTIMAC_CTIOUTEN11___RWC QCSR_REG_RW +#define DBG_CTIMAC_CTIOUTEN11___POR 0x00000000 +#define DBG_CTIMAC_CTIOUTEN11__TRIGOUTEN___POR 0x00 +#define DBG_CTIMAC_CTIOUTEN11__TRIGOUTEN___M 0x000000FF +#define DBG_CTIMAC_CTIOUTEN11__TRIGOUTEN___S 0 +#define DBG_CTIMAC_CTIOUTEN11___M 0x000000FF +#define DBG_CTIMAC_CTIOUTEN11___S 0 + +#define DBG_CTIMAC_CTITRIGINSTATUS (0x00BB6130) +#define DBG_CTIMAC_CTITRIGINSTATUS___RWC QCSR_REG_RO +#define DBG_CTIMAC_CTITRIGINSTATUS__TRIGINSTATUS___M 0x00000FFF +#define DBG_CTIMAC_CTITRIGINSTATUS__TRIGINSTATUS___S 0 +#define DBG_CTIMAC_CTITRIGINSTATUS___M 0x00000FFF +#define DBG_CTIMAC_CTITRIGINSTATUS___S 0 + +#define DBG_CTIMAC_CTITRIGOUTSTATUS (0x00BB6134) +#define DBG_CTIMAC_CTITRIGOUTSTATUS___RWC QCSR_REG_RO +#define DBG_CTIMAC_CTITRIGOUTSTATUS___POR 0x00000000 +#define DBG_CTIMAC_CTITRIGOUTSTATUS__TRIGOUTSTATUS___POR 0x000 +#define DBG_CTIMAC_CTITRIGOUTSTATUS__TRIGOUTSTATUS___M 0x00000FFF +#define DBG_CTIMAC_CTITRIGOUTSTATUS__TRIGOUTSTATUS___S 0 +#define DBG_CTIMAC_CTITRIGOUTSTATUS___M 0x00000FFF +#define DBG_CTIMAC_CTITRIGOUTSTATUS___S 0 + +#define DBG_CTIMAC_CTICHINSTATUS (0x00BB6138) +#define DBG_CTIMAC_CTICHINSTATUS___RWC QCSR_REG_RO +#define DBG_CTIMAC_CTICHINSTATUS__CTICHINSTATUS___M 0x000000FF +#define DBG_CTIMAC_CTICHINSTATUS__CTICHINSTATUS___S 0 +#define DBG_CTIMAC_CTICHINSTATUS___M 0x000000FF +#define DBG_CTIMAC_CTICHINSTATUS___S 0 + +#define DBG_CTIMAC_CTICHOUTSTATUS (0x00BB613C) +#define DBG_CTIMAC_CTICHOUTSTATUS___RWC QCSR_REG_RO +#define DBG_CTIMAC_CTICHOUTSTATUS___POR 0x00000000 +#define DBG_CTIMAC_CTICHOUTSTATUS__CTICHOUTSTATUS___POR 0x00 +#define DBG_CTIMAC_CTICHOUTSTATUS__CTICHOUTSTATUS___M 0x000000FF +#define DBG_CTIMAC_CTICHOUTSTATUS__CTICHOUTSTATUS___S 0 +#define DBG_CTIMAC_CTICHOUTSTATUS___M 0x000000FF +#define DBG_CTIMAC_CTICHOUTSTATUS___S 0 + +#define DBG_CTIMAC_CTIGATE (0x00BB6140) +#define DBG_CTIMAC_CTIGATE___RWC QCSR_REG_RW +#define DBG_CTIMAC_CTIGATE___POR 0x000000FF +#define DBG_CTIMAC_CTIGATE__CTIGATEEN7___POR 0x1 +#define DBG_CTIMAC_CTIGATE__CTIGATEEN6___POR 0x1 +#define DBG_CTIMAC_CTIGATE__CTIGATEEN5___POR 0x1 +#define DBG_CTIMAC_CTIGATE__CTIGATEEN4___POR 0x1 +#define DBG_CTIMAC_CTIGATE__CTIGATEEN3___POR 0x1 +#define DBG_CTIMAC_CTIGATE__CTIGATEEN2___POR 0x1 +#define DBG_CTIMAC_CTIGATE__CTIGATEEN1___POR 0x1 +#define DBG_CTIMAC_CTIGATE__CTIGATEEN0___POR 0x1 +#define DBG_CTIMAC_CTIGATE__CTIGATEEN7___M 0x00000080 +#define DBG_CTIMAC_CTIGATE__CTIGATEEN7___S 7 +#define DBG_CTIMAC_CTIGATE__CTIGATEEN6___M 0x00000040 +#define DBG_CTIMAC_CTIGATE__CTIGATEEN6___S 6 +#define DBG_CTIMAC_CTIGATE__CTIGATEEN5___M 0x00000020 +#define DBG_CTIMAC_CTIGATE__CTIGATEEN5___S 5 +#define DBG_CTIMAC_CTIGATE__CTIGATEEN4___M 0x00000010 +#define DBG_CTIMAC_CTIGATE__CTIGATEEN4___S 4 +#define DBG_CTIMAC_CTIGATE__CTIGATEEN3___M 0x00000008 +#define DBG_CTIMAC_CTIGATE__CTIGATEEN3___S 3 +#define DBG_CTIMAC_CTIGATE__CTIGATEEN2___M 0x00000004 +#define DBG_CTIMAC_CTIGATE__CTIGATEEN2___S 2 +#define DBG_CTIMAC_CTIGATE__CTIGATEEN1___M 0x00000002 +#define DBG_CTIMAC_CTIGATE__CTIGATEEN1___S 1 +#define DBG_CTIMAC_CTIGATE__CTIGATEEN0___M 0x00000001 +#define DBG_CTIMAC_CTIGATE__CTIGATEEN0___S 0 +#define DBG_CTIMAC_CTIGATE___M 0x000000FF +#define DBG_CTIMAC_CTIGATE___S 0 + +#define DBG_CTIMAC_ASICCTL (0x00BB6144) +#define DBG_CTIMAC_ASICCTL___RWC QCSR_REG_RW +#define DBG_CTIMAC_ASICCTL___POR 0x00000000 +#define DBG_CTIMAC_ASICCTL__ASICCTL___POR 0x00000000 +#define DBG_CTIMAC_ASICCTL__ASICCTL___M 0xFFFFFFFF +#define DBG_CTIMAC_ASICCTL__ASICCTL___S 0 +#define DBG_CTIMAC_ASICCTL___M 0xFFFFFFFF +#define DBG_CTIMAC_ASICCTL___S 0 + +#define DBG_CTIMAC_ITCHINACK (0x00BB6EDC) +#define DBG_CTIMAC_ITCHINACK___RWC QCSR_REG_WO +#define DBG_CTIMAC_ITCHINACK___POR 0x00000000 +#define DBG_CTIMAC_ITCHINACK__CTCHINACK___POR 0x00 +#define DBG_CTIMAC_ITCHINACK__CTCHINACK___M 0x000000FF +#define DBG_CTIMAC_ITCHINACK__CTCHINACK___S 0 +#define DBG_CTIMAC_ITCHINACK___M 0x000000FF +#define DBG_CTIMAC_ITCHINACK___S 0 + +#define DBG_CTIMAC_ITTRIGINACK (0x00BB6EE0) +#define DBG_CTIMAC_ITTRIGINACK___RWC QCSR_REG_WO +#define DBG_CTIMAC_ITTRIGINACK___POR 0x00000000 +#define DBG_CTIMAC_ITTRIGINACK__CTTRIGINACK___POR 0x000 +#define DBG_CTIMAC_ITTRIGINACK__CTTRIGINACK___M 0x00000FFF +#define DBG_CTIMAC_ITTRIGINACK__CTTRIGINACK___S 0 +#define DBG_CTIMAC_ITTRIGINACK___M 0x00000FFF +#define DBG_CTIMAC_ITTRIGINACK___S 0 + +#define DBG_CTIMAC_ITCHOUT (0x00BB6EE4) +#define DBG_CTIMAC_ITCHOUT___RWC QCSR_REG_WO +#define DBG_CTIMAC_ITCHOUT___POR 0x00000000 +#define DBG_CTIMAC_ITCHOUT__CTCHOUT___POR 0x00 +#define DBG_CTIMAC_ITCHOUT__CTCHOUT___M 0x000000FF +#define DBG_CTIMAC_ITCHOUT__CTCHOUT___S 0 +#define DBG_CTIMAC_ITCHOUT___M 0x000000FF +#define DBG_CTIMAC_ITCHOUT___S 0 + +#define DBG_CTIMAC_ITTRIGOUT (0x00BB6EE8) +#define DBG_CTIMAC_ITTRIGOUT___RWC QCSR_REG_WO +#define DBG_CTIMAC_ITTRIGOUT___POR 0x00000000 +#define DBG_CTIMAC_ITTRIGOUT__CTTRIGOUT___POR 0x000 +#define DBG_CTIMAC_ITTRIGOUT__CTTRIGOUT___M 0x00000FFF +#define DBG_CTIMAC_ITTRIGOUT__CTTRIGOUT___S 0 +#define DBG_CTIMAC_ITTRIGOUT___M 0x00000FFF +#define DBG_CTIMAC_ITTRIGOUT___S 0 + +#define DBG_CTIMAC_ITCHOUTACK (0x00BB6EEC) +#define DBG_CTIMAC_ITCHOUTACK___RWC QCSR_REG_RO +#define DBG_CTIMAC_ITCHOUTACK___POR 0x00000000 +#define DBG_CTIMAC_ITCHOUTACK__CTCHOUTACK___POR 0x00 +#define DBG_CTIMAC_ITCHOUTACK__CTCHOUTACK___M 0x000000FF +#define DBG_CTIMAC_ITCHOUTACK__CTCHOUTACK___S 0 +#define DBG_CTIMAC_ITCHOUTACK___M 0x000000FF +#define DBG_CTIMAC_ITCHOUTACK___S 0 + +#define DBG_CTIMAC_ITTRIGOUTACK (0x00BB6EF0) +#define DBG_CTIMAC_ITTRIGOUTACK___RWC QCSR_REG_RO +#define DBG_CTIMAC_ITTRIGOUTACK___POR 0x00000000 +#define DBG_CTIMAC_ITTRIGOUTACK__CTTRIGOUTACK___POR 0x000 +#define DBG_CTIMAC_ITTRIGOUTACK__CTTRIGOUTACK___M 0x00000FFF +#define DBG_CTIMAC_ITTRIGOUTACK__CTTRIGOUTACK___S 0 +#define DBG_CTIMAC_ITTRIGOUTACK___M 0x00000FFF +#define DBG_CTIMAC_ITTRIGOUTACK___S 0 + +#define DBG_CTIMAC_ITCHIN (0x00BB6EF4) +#define DBG_CTIMAC_ITCHIN___RWC QCSR_REG_RO +#define DBG_CTIMAC_ITCHIN___POR 0x00000000 +#define DBG_CTIMAC_ITCHIN__CTCHIN___POR 0x00 +#define DBG_CTIMAC_ITCHIN__CTCHIN___M 0x000000FF +#define DBG_CTIMAC_ITCHIN__CTCHIN___S 0 +#define DBG_CTIMAC_ITCHIN___M 0x000000FF +#define DBG_CTIMAC_ITCHIN___S 0 + +#define DBG_CTIMAC_ITTRIGIN (0x00BB6EF8) +#define DBG_CTIMAC_ITTRIGIN___RWC QCSR_REG_RO +#define DBG_CTIMAC_ITTRIGIN___POR 0x00000000 +#define DBG_CTIMAC_ITTRIGIN__CTTRIGIN___POR 0x000 +#define DBG_CTIMAC_ITTRIGIN__CTTRIGIN___M 0x00000FFF +#define DBG_CTIMAC_ITTRIGIN__CTTRIGIN___S 0 +#define DBG_CTIMAC_ITTRIGIN___M 0x00000FFF +#define DBG_CTIMAC_ITTRIGIN___S 0 + +#define DBG_CTIMAC_ITCTRL (0x00BB6F00) +#define DBG_CTIMAC_ITCTRL___RWC QCSR_REG_RW +#define DBG_CTIMAC_ITCTRL___POR 0x00000000 +#define DBG_CTIMAC_ITCTRL__INTEGRATION_MODE___POR 0x0 +#define DBG_CTIMAC_ITCTRL__INTEGRATION_MODE___M 0x00000001 +#define DBG_CTIMAC_ITCTRL__INTEGRATION_MODE___S 0 +#define DBG_CTIMAC_ITCTRL__INTEGRATION_MODE__FUNCTIONAL_MODE 0x0 +#define DBG_CTIMAC_ITCTRL__INTEGRATION_MODE__INTG_MODE 0x1 +#define DBG_CTIMAC_ITCTRL___M 0x00000001 +#define DBG_CTIMAC_ITCTRL___S 0 + +#define DBG_CTIMAC_CLAIMSET (0x00BB6FA0) +#define DBG_CTIMAC_CLAIMSET___RWC QCSR_REG_RW +#define DBG_CTIMAC_CLAIMSET___POR 0x0000000F +#define DBG_CTIMAC_CLAIMSET__CLAIMSET___POR 0xF +#define DBG_CTIMAC_CLAIMSET__CLAIMSET___M 0x0000000F +#define DBG_CTIMAC_CLAIMSET__CLAIMSET___S 0 +#define DBG_CTIMAC_CLAIMSET__CLAIMSET__CLAIM_TAG_IMPLEMENTED_BITS 0xF +#define DBG_CTIMAC_CLAIMSET___M 0x0000000F +#define DBG_CTIMAC_CLAIMSET___S 0 + +#define DBG_CTIMAC_CLAIMCLR (0x00BB6FA4) +#define DBG_CTIMAC_CLAIMCLR___RWC QCSR_REG_RW +#define DBG_CTIMAC_CLAIMCLR___POR 0x00000000 +#define DBG_CTIMAC_CLAIMCLR__CLAIMCLR___POR 0x0 +#define DBG_CTIMAC_CLAIMCLR__CLAIMCLR___M 0x0000000F +#define DBG_CTIMAC_CLAIMCLR__CLAIMCLR___S 0 +#define DBG_CTIMAC_CLAIMCLR___M 0x0000000F +#define DBG_CTIMAC_CLAIMCLR___S 0 + +#define DBG_CTIMAC_DEVAFF0 (0x00BB6FA8) +#define DBG_CTIMAC_DEVAFF0___RWC QCSR_REG_RO +#define DBG_CTIMAC_DEVAFF0___POR 0x00000000 +#define DBG_CTIMAC_DEVAFF0__VAL___POR 0x00000000 +#define DBG_CTIMAC_DEVAFF0__VAL___M 0xFFFFFFFF +#define DBG_CTIMAC_DEVAFF0__VAL___S 0 +#define DBG_CTIMAC_DEVAFF0___M 0xFFFFFFFF +#define DBG_CTIMAC_DEVAFF0___S 0 + +#define DBG_CTIMAC_DEVAFF1 (0x00BB6FAC) +#define DBG_CTIMAC_DEVAFF1___RWC QCSR_REG_RO +#define DBG_CTIMAC_DEVAFF1___POR 0x00000000 +#define DBG_CTIMAC_DEVAFF1__VAL___POR 0x00000000 +#define DBG_CTIMAC_DEVAFF1__VAL___M 0xFFFFFFFF +#define DBG_CTIMAC_DEVAFF1__VAL___S 0 +#define DBG_CTIMAC_DEVAFF1___M 0xFFFFFFFF +#define DBG_CTIMAC_DEVAFF1___S 0 + +#define DBG_CTIMAC_LAR (0x00BB6FB0) +#define DBG_CTIMAC_LAR___RWC QCSR_REG_WO +#define DBG_CTIMAC_LAR__ACCESS_W___M 0xFFFFFFFF +#define DBG_CTIMAC_LAR__ACCESS_W___S 0 +#define DBG_CTIMAC_LAR__ACCESS_W__UNLOCK 0xC5ACCE55 +#define DBG_CTIMAC_LAR___M 0xFFFFFFFF +#define DBG_CTIMAC_LAR___S 0 + +#define DBG_CTIMAC_LSR (0x00BB6FB4) +#define DBG_CTIMAC_LSR___RWC QCSR_REG_RO +#define DBG_CTIMAC_LSR___POR 0x00000003 +#define DBG_CTIMAC_LSR__NTT___POR 0x0 +#define DBG_CTIMAC_LSR__SLK___POR 0x1 +#define DBG_CTIMAC_LSR__SLI___POR 0x1 +#define DBG_CTIMAC_LSR__NTT___M 0x00000004 +#define DBG_CTIMAC_LSR__NTT___S 2 +#define DBG_CTIMAC_LSR__NTT__SIZE_32BIT 0x0 +#define DBG_CTIMAC_LSR__SLK___M 0x00000002 +#define DBG_CTIMAC_LSR__SLK___S 1 +#define DBG_CTIMAC_LSR__SLK__ACCESS_PERMITTED 0x0 +#define DBG_CTIMAC_LSR__SLK__DEVICE_LOCKED 0x1 +#define DBG_CTIMAC_LSR__SLI___M 0x00000001 +#define DBG_CTIMAC_LSR__SLI___S 0 +#define DBG_CTIMAC_LSR__SLI__LOCK_NOT_PRESENT 0x0 +#define DBG_CTIMAC_LSR__SLI__LOCK_PRESENT 0x1 +#define DBG_CTIMAC_LSR___M 0x00000007 +#define DBG_CTIMAC_LSR___S 0 + +#define DBG_CTIMAC_AUTHSTATUS (0x00BB6FB8) +#define DBG_CTIMAC_AUTHSTATUS___RWC QCSR_REG_RO +#define DBG_CTIMAC_AUTHSTATUS__SNID___M 0x000000C0 +#define DBG_CTIMAC_AUTHSTATUS__SNID___S 6 +#define DBG_CTIMAC_AUTHSTATUS__SNID__NOT_IMPLEMENTED 0x0 +#define DBG_CTIMAC_AUTHSTATUS__SID___M 0x00000030 +#define DBG_CTIMAC_AUTHSTATUS__SID___S 4 +#define DBG_CTIMAC_AUTHSTATUS__SID__NOT_IMPLEMENTED 0x0 +#define DBG_CTIMAC_AUTHSTATUS__NSNID___M 0x0000000C +#define DBG_CTIMAC_AUTHSTATUS__NSNID___S 2 +#define DBG_CTIMAC_AUTHSTATUS__NSNID__DISABLED 0x2 +#define DBG_CTIMAC_AUTHSTATUS__NSNID__ENABLED 0x3 +#define DBG_CTIMAC_AUTHSTATUS__NSID___M 0x00000003 +#define DBG_CTIMAC_AUTHSTATUS__NSID___S 0 +#define DBG_CTIMAC_AUTHSTATUS__NSID__DISABLED 0x2 +#define DBG_CTIMAC_AUTHSTATUS__NSID__ENABLED 0x3 +#define DBG_CTIMAC_AUTHSTATUS___M 0x000000FF +#define DBG_CTIMAC_AUTHSTATUS___S 0 + +#define DBG_CTIMAC_DEVARCH (0x00BB6FBC) +#define DBG_CTIMAC_DEVARCH___RWC QCSR_REG_RO +#define DBG_CTIMAC_DEVARCH___POR 0x8EF00A14 +#define DBG_CTIMAC_DEVARCH__ARCHITECT___POR 0x477 +#define DBG_CTIMAC_DEVARCH__PRESENT___POR 0x1 +#define DBG_CTIMAC_DEVARCH__REVISION___POR 0x0 +#define DBG_CTIMAC_DEVARCH__ARCHID___POR 0x0A14 +#define DBG_CTIMAC_DEVARCH__ARCHITECT___M 0xFFE00000 +#define DBG_CTIMAC_DEVARCH__ARCHITECT___S 21 +#define DBG_CTIMAC_DEVARCH__PRESENT___M 0x00100000 +#define DBG_CTIMAC_DEVARCH__PRESENT___S 20 +#define DBG_CTIMAC_DEVARCH__REVISION___M 0x000F0000 +#define DBG_CTIMAC_DEVARCH__REVISION___S 16 +#define DBG_CTIMAC_DEVARCH__ARCHID___M 0x0000FFFF +#define DBG_CTIMAC_DEVARCH__ARCHID___S 0 +#define DBG_CTIMAC_DEVARCH___M 0xFFFFFFFF +#define DBG_CTIMAC_DEVARCH___S 0 + +#define DBG_CTIMAC_DEVID2 (0x00BB6FC0) +#define DBG_CTIMAC_DEVID2___RWC QCSR_REG_RO +#define DBG_CTIMAC_DEVID2___POR 0x00000000 +#define DBG_CTIMAC_DEVID2__IMPLDEF___POR 0x0 +#define DBG_CTIMAC_DEVID2__IMPLDEF___M 0x00000001 +#define DBG_CTIMAC_DEVID2__IMPLDEF___S 0 +#define DBG_CTIMAC_DEVID2___M 0x00000001 +#define DBG_CTIMAC_DEVID2___S 0 + +#define DBG_CTIMAC_DEVID1 (0x00BB6FC4) +#define DBG_CTIMAC_DEVID1___RWC QCSR_REG_RO +#define DBG_CTIMAC_DEVID1___POR 0x00000000 +#define DBG_CTIMAC_DEVID1__IMPLDEF___POR 0x0 +#define DBG_CTIMAC_DEVID1__IMPLDEF___M 0x00000001 +#define DBG_CTIMAC_DEVID1__IMPLDEF___S 0 +#define DBG_CTIMAC_DEVID1___M 0x00000001 +#define DBG_CTIMAC_DEVID1___S 0 + +#define DBG_CTIMAC_DEVID (0x00BB6FC8) +#define DBG_CTIMAC_DEVID___RWC QCSR_REG_RO +#define DBG_CTIMAC_DEVID___POR 0x00080C00 +#define DBG_CTIMAC_DEVID__NUMCH___POR 0x8 +#define DBG_CTIMAC_DEVID__NUMTRIG___POR 0xC +#define DBG_CTIMAC_DEVID__EXTMUXNUM___POR 0x00 +#define DBG_CTIMAC_DEVID__NUMCH___M 0x003F0000 +#define DBG_CTIMAC_DEVID__NUMCH___S 16 +#define DBG_CTIMAC_DEVID__NUMTRIG___M 0x0000FF00 +#define DBG_CTIMAC_DEVID__NUMTRIG___S 8 +#define DBG_CTIMAC_DEVID__EXTMUXNUM___M 0x0000001F +#define DBG_CTIMAC_DEVID__EXTMUXNUM___S 0 +#define DBG_CTIMAC_DEVID___M 0x003FFF1F +#define DBG_CTIMAC_DEVID___S 0 + +#define DBG_CTIMAC_DEVTYPE (0x00BB6FCC) +#define DBG_CTIMAC_DEVTYPE___RWC QCSR_REG_RO +#define DBG_CTIMAC_DEVTYPE___POR 0x00000014 +#define DBG_CTIMAC_DEVTYPE__SUB_TYPE___POR 0x1 +#define DBG_CTIMAC_DEVTYPE__MAJOR_TYPE___POR 0x4 +#define DBG_CTIMAC_DEVTYPE__SUB_TYPE___M 0x000000F0 +#define DBG_CTIMAC_DEVTYPE__SUB_TYPE___S 4 +#define DBG_CTIMAC_DEVTYPE__SUB_TYPE__TRIGGER_MATRIX 0x1 +#define DBG_CTIMAC_DEVTYPE__MAJOR_TYPE___M 0x0000000F +#define DBG_CTIMAC_DEVTYPE__MAJOR_TYPE___S 0 +#define DBG_CTIMAC_DEVTYPE__MAJOR_TYPE__DEBUG_CONTROL 0x4 +#define DBG_CTIMAC_DEVTYPE___M 0x000000FF +#define DBG_CTIMAC_DEVTYPE___S 0 + +#define DBG_CTIMAC_PIDR0 (0x00BB6FE0) +#define DBG_CTIMAC_PIDR0___RWC QCSR_REG_RO +#define DBG_CTIMAC_PIDR0___POR 0x00000006 +#define DBG_CTIMAC_PIDR0__PART_0___POR 0x06 +#define DBG_CTIMAC_PIDR0__PART_0___M 0x000000FF +#define DBG_CTIMAC_PIDR0__PART_0___S 0 +#define DBG_CTIMAC_PIDR0__PART_0__CTI_PART_NUMBER_BITS7TO0 0x06 +#define DBG_CTIMAC_PIDR0___M 0x000000FF +#define DBG_CTIMAC_PIDR0___S 0 + +#define DBG_CTIMAC_PIDR1 (0x00BB6FE4) +#define DBG_CTIMAC_PIDR1___RWC QCSR_REG_RO +#define DBG_CTIMAC_PIDR1___POR 0x000000B9 +#define DBG_CTIMAC_PIDR1__DES_0___POR 0xB +#define DBG_CTIMAC_PIDR1__PART_1___POR 0x9 +#define DBG_CTIMAC_PIDR1__DES_0___M 0x000000F0 +#define DBG_CTIMAC_PIDR1__DES_0___S 4 +#define DBG_CTIMAC_PIDR1__DES_0__ARM_JEP106_IDENTITY_CODE_BITS3TO0 0xB +#define DBG_CTIMAC_PIDR1__PART_1___M 0x0000000F +#define DBG_CTIMAC_PIDR1__PART_1___S 0 +#define DBG_CTIMAC_PIDR1__PART_1__CTI_PART_NUMBER_BITS11TO8 0x9 +#define DBG_CTIMAC_PIDR1___M 0x000000FF +#define DBG_CTIMAC_PIDR1___S 0 + +#define DBG_CTIMAC_PIDR2 (0x00BB6FE8) +#define DBG_CTIMAC_PIDR2___RWC QCSR_REG_RO +#define DBG_CTIMAC_PIDR2___POR 0x0000004B +#define DBG_CTIMAC_PIDR2__REVISION___POR 0x4 +#define DBG_CTIMAC_PIDR2__JEDEC___POR 0x1 +#define DBG_CTIMAC_PIDR2__DES_1___POR 0x3 +#define DBG_CTIMAC_PIDR2__REVISION___M 0x000000F0 +#define DBG_CTIMAC_PIDR2__REVISION___S 4 +#define DBG_CTIMAC_PIDR2__REVISION__R0P5 0x4 +#define DBG_CTIMAC_PIDR2__JEDEC___M 0x00000008 +#define DBG_CTIMAC_PIDR2__JEDEC___S 3 +#define DBG_CTIMAC_PIDR2__JEDEC__JEDEC_IDENTITY 0x1 +#define DBG_CTIMAC_PIDR2__DES_1___M 0x00000007 +#define DBG_CTIMAC_PIDR2__DES_1___S 0 +#define DBG_CTIMAC_PIDR2__DES_1__ARM_JEP106_IDENTITY_CODE_BITS6TO4 0x3 +#define DBG_CTIMAC_PIDR2___M 0x000000FF +#define DBG_CTIMAC_PIDR2___S 0 + +#define DBG_CTIMAC_PIDR3 (0x00BB6FEC) +#define DBG_CTIMAC_PIDR3___RWC QCSR_REG_RO +#define DBG_CTIMAC_PIDR3___POR 0x00000000 +#define DBG_CTIMAC_PIDR3__REVAND___POR 0x0 +#define DBG_CTIMAC_PIDR3__CMOD___POR 0x0 +#define DBG_CTIMAC_PIDR3__REVAND___M 0x000000F0 +#define DBG_CTIMAC_PIDR3__REVAND___S 4 +#define DBG_CTIMAC_PIDR3__REVAND__NO_MODIFICATION 0x0 +#define DBG_CTIMAC_PIDR3__CMOD___M 0x0000000F +#define DBG_CTIMAC_PIDR3__CMOD___S 0 +#define DBG_CTIMAC_PIDR3__CMOD__NO_MODIFICATION 0x0 +#define DBG_CTIMAC_PIDR3___M 0x000000FF +#define DBG_CTIMAC_PIDR3___S 0 + +#define DBG_CTIMAC_PIDR4 (0x00BB6FD0) +#define DBG_CTIMAC_PIDR4___RWC QCSR_REG_RO +#define DBG_CTIMAC_PIDR4___POR 0x00000004 +#define DBG_CTIMAC_PIDR4__SIZE___POR 0x0 +#define DBG_CTIMAC_PIDR4__DES_2___POR 0x4 +#define DBG_CTIMAC_PIDR4__SIZE___M 0x000000F0 +#define DBG_CTIMAC_PIDR4__SIZE___S 4 +#define DBG_CTIMAC_PIDR4__SIZE__SIZE_4KB 0x0 +#define DBG_CTIMAC_PIDR4__DES_2___M 0x0000000F +#define DBG_CTIMAC_PIDR4__DES_2___S 0 +#define DBG_CTIMAC_PIDR4__DES_2__ARM_JEP106_CONTINUATION_CODE 0x4 +#define DBG_CTIMAC_PIDR4___M 0x000000FF +#define DBG_CTIMAC_PIDR4___S 0 + +#define DBG_CTIMAC_PIDR5 (0x00BB6FD4) +#define DBG_CTIMAC_PIDR5___RWC QCSR_REG_RW +#define DBG_CTIMAC_PIDR5__PERIPHID5___M 0xFFFFFFFF +#define DBG_CTIMAC_PIDR5__PERIPHID5___S 0 +#define DBG_CTIMAC_PIDR5___M 0xFFFFFFFF +#define DBG_CTIMAC_PIDR5___S 0 + +#define DBG_CTIMAC_PIDR6 (0x00BB6FD8) +#define DBG_CTIMAC_PIDR6___RWC QCSR_REG_RW +#define DBG_CTIMAC_PIDR6__PERIPHID6___M 0xFFFFFFFF +#define DBG_CTIMAC_PIDR6__PERIPHID6___S 0 +#define DBG_CTIMAC_PIDR6___M 0xFFFFFFFF +#define DBG_CTIMAC_PIDR6___S 0 + +#define DBG_CTIMAC_PIDR7 (0x00BB6FDC) +#define DBG_CTIMAC_PIDR7___RWC QCSR_REG_RW +#define DBG_CTIMAC_PIDR7__PERIPHID7___M 0xFFFFFFFF +#define DBG_CTIMAC_PIDR7__PERIPHID7___S 0 +#define DBG_CTIMAC_PIDR7___M 0xFFFFFFFF +#define DBG_CTIMAC_PIDR7___S 0 + +#define DBG_CTIMAC_CIDR0 (0x00BB6FF0) +#define DBG_CTIMAC_CIDR0___RWC QCSR_REG_RO +#define DBG_CTIMAC_CIDR0___POR 0x0000000D +#define DBG_CTIMAC_CIDR0__PRMBL_0___POR 0x0D +#define DBG_CTIMAC_CIDR0__PRMBL_0___M 0x000000FF +#define DBG_CTIMAC_CIDR0__PRMBL_0___S 0 +#define DBG_CTIMAC_CIDR0__PRMBL_0__ID_VALUE_0D 0x0D +#define DBG_CTIMAC_CIDR0___M 0x000000FF +#define DBG_CTIMAC_CIDR0___S 0 + +#define DBG_CTIMAC_CIDR1 (0x00BB6FF4) +#define DBG_CTIMAC_CIDR1___RWC QCSR_REG_RO +#define DBG_CTIMAC_CIDR1___POR 0x00000090 +#define DBG_CTIMAC_CIDR1__CLASS___POR 0x9 +#define DBG_CTIMAC_CIDR1__PRMBL_1___POR 0x0 +#define DBG_CTIMAC_CIDR1__CLASS___M 0x000000F0 +#define DBG_CTIMAC_CIDR1__CLASS___S 4 +#define DBG_CTIMAC_CIDR1__CLASS__CORESIGHT_COMPONENT 0x9 +#define DBG_CTIMAC_CIDR1__PRMBL_1___M 0x0000000F +#define DBG_CTIMAC_CIDR1__PRMBL_1___S 0 +#define DBG_CTIMAC_CIDR1__PRMBL_1__ID_VALUE_0 0x0 +#define DBG_CTIMAC_CIDR1___M 0x000000FF +#define DBG_CTIMAC_CIDR1___S 0 + +#define DBG_CTIMAC_CIDR2 (0x00BB6FF8) +#define DBG_CTIMAC_CIDR2___RWC QCSR_REG_RO +#define DBG_CTIMAC_CIDR2___POR 0x00000005 +#define DBG_CTIMAC_CIDR2__PRMBL_2___POR 0x05 +#define DBG_CTIMAC_CIDR2__PRMBL_2___M 0x000000FF +#define DBG_CTIMAC_CIDR2__PRMBL_2___S 0 +#define DBG_CTIMAC_CIDR2__PRMBL_2__ID_VALUE_05 0x05 +#define DBG_CTIMAC_CIDR2___M 0x000000FF +#define DBG_CTIMAC_CIDR2___S 0 + +#define DBG_CTIMAC_CIDR3 (0x00BB6FFC) +#define DBG_CTIMAC_CIDR3___RWC QCSR_REG_RO +#define DBG_CTIMAC_CIDR3___POR 0x000000B1 +#define DBG_CTIMAC_CIDR3__PRMBL_3___POR 0xB1 +#define DBG_CTIMAC_CIDR3__PRMBL_3___M 0x000000FF +#define DBG_CTIMAC_CIDR3__PRMBL_3___S 0 +#define DBG_CTIMAC_CIDR3__PRMBL_3__ID_VALUE_B1 0xB1 +#define DBG_CTIMAC_CIDR3___M 0x000000FF +#define DBG_CTIMAC_CIDR3___S 0 + +#define DBG_CFG (0x00BB8000) +#define DBG_CFG___RWC QCSR_REG_RW +#define DBG_CFG___POR 0x00000000 +#define DBG_CFG__TSBIT_VAL___POR 0x00 +#define DBG_CFG__ATBID___POR 0x00 +#define DBG_CFG__TRIG_EN___POR 0x0 +#define DBG_CFG__TSBIT_VAL___M 0x00003F00 +#define DBG_CFG__TSBIT_VAL___S 8 +#define DBG_CFG__ATBID___M 0x000000FE +#define DBG_CFG__ATBID___S 1 +#define DBG_CFG__TRIG_EN___M 0x00000001 +#define DBG_CFG__TRIG_EN___S 0 +#define DBG_CFG___M 0x00003FFF +#define DBG_CFG___S 0 + +#define DBG_SW_INJCT_REQ (0x00BB8004) +#define DBG_SW_INJCT_REQ___RWC QCSR_REG_WO +#define DBG_SW_INJCT_REQ___POR 0x00000000 +#define DBG_SW_INJCT_REQ__REQ___POR 0x0 +#define DBG_SW_INJCT_REQ__REQ___M 0x00000001 +#define DBG_SW_INJCT_REQ__REQ___S 0 +#define DBG_SW_INJCT_REQ__REQ__NOP 0x0 +#define DBG_SW_INJCT_REQ__REQ__INJECT_TIMESTAMP 0x1 +#define DBG_SW_INJCT_REQ___M 0x00000001 +#define DBG_SW_INJCT_REQ___S 0 + +#define DBG_TPDM_DSB_CR (0x00BB9780) +#define DBG_TPDM_DSB_CR___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_CR___POR 0x00000000 +#define DBG_TPDM_DSB_CR__TRIG_TYPE___POR 0x0 +#define DBG_TPDM_DSB_CR__ATBFLOWERR___POR 0x0 +#define DBG_TPDM_DSB_CR__EBITSET___POR 0x0 +#define DBG_TPDM_DSB_CR__HPSEL___POR 0x00 +#define DBG_TPDM_DSB_CR__MODE___POR 0x0 +#define DBG_TPDM_DSB_CR__E___POR 0x0 +#define DBG_TPDM_DSB_CR__TRIG_TYPE___M 0x00001000 +#define DBG_TPDM_DSB_CR__TRIG_TYPE___S 12 +#define DBG_TPDM_DSB_CR__ATBFLOWERR___M 0x00000100 +#define DBG_TPDM_DSB_CR__ATBFLOWERR___S 8 +#define DBG_TPDM_DSB_CR__EBITSET___M 0x00000080 +#define DBG_TPDM_DSB_CR__EBITSET___S 7 +#define DBG_TPDM_DSB_CR__HPSEL___M 0x0000007C +#define DBG_TPDM_DSB_CR__HPSEL___S 2 +#define DBG_TPDM_DSB_CR__MODE___M 0x00000002 +#define DBG_TPDM_DSB_CR__MODE___S 1 +#define DBG_TPDM_DSB_CR__E___M 0x00000001 +#define DBG_TPDM_DSB_CR__E___S 0 +#define DBG_TPDM_DSB_CR___M 0x000011FF +#define DBG_TPDM_DSB_CR___S 0 + +#define DBG_TPDM_DSB_TIER (0x00BB9784) +#define DBG_TPDM_DSB_TIER___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_TIER___POR 0x00000000 +#define DBG_TPDM_DSB_TIER__PATT_TYPE___POR 0x0 +#define DBG_TPDM_DSB_TIER__XTRIG_TSENAB___POR 0x0 +#define DBG_TPDM_DSB_TIER__PATT_TSENAB___POR 0x0 +#define DBG_TPDM_DSB_TIER__PATT_TYPE___M 0x00000004 +#define DBG_TPDM_DSB_TIER__PATT_TYPE___S 2 +#define DBG_TPDM_DSB_TIER__XTRIG_TSENAB___M 0x00000002 +#define DBG_TPDM_DSB_TIER__XTRIG_TSENAB___S 1 +#define DBG_TPDM_DSB_TIER__PATT_TSENAB___M 0x00000001 +#define DBG_TPDM_DSB_TIER__PATT_TSENAB___S 0 +#define DBG_TPDM_DSB_TIER___M 0x00000007 +#define DBG_TPDM_DSB_TIER___S 0 + +#define DBG_TPDM_DSB_TPRn(n) (0x00BB9788+0x4*(n)) +#define DBG_TPDM_DSB_TPRn_nMIN 0 +#define DBG_TPDM_DSB_TPRn_nMAX 6 +#define DBG_TPDM_DSB_TPRn_ELEM 7 +#define DBG_TPDM_DSB_TPRn___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_TPRn___POR 0x00000000 +#define DBG_TPDM_DSB_TPRn__VAL___POR 0x00000000 +#define DBG_TPDM_DSB_TPRn__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_TPRn__VAL___S 0 +#define DBG_TPDM_DSB_TPRn___M 0xFFFFFFFF +#define DBG_TPDM_DSB_TPRn___S 0 +#define DBG_TPDM_DSB_TPR0 (0x00BB9788) +#define DBG_TPDM_DSB_TPR0___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_TPR0__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_TPR0__VAL___S 0 +#define DBG_TPDM_DSB_TPR1 (0x00BB978C) +#define DBG_TPDM_DSB_TPR1___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_TPR1__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_TPR1__VAL___S 0 +#define DBG_TPDM_DSB_TPR2 (0x00BB9790) +#define DBG_TPDM_DSB_TPR2___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_TPR2__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_TPR2__VAL___S 0 +#define DBG_TPDM_DSB_TPR3 (0x00BB9794) +#define DBG_TPDM_DSB_TPR3___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_TPR3__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_TPR3__VAL___S 0 +#define DBG_TPDM_DSB_TPR4 (0x00BB9798) +#define DBG_TPDM_DSB_TPR4___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_TPR4__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_TPR4__VAL___S 0 +#define DBG_TPDM_DSB_TPR5 (0x00BB979C) +#define DBG_TPDM_DSB_TPR5___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_TPR5__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_TPR5__VAL___S 0 +#define DBG_TPDM_DSB_TPR6 (0x00BB97A0) +#define DBG_TPDM_DSB_TPR6___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_TPR6__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_TPR6__VAL___S 0 + +#define DBG_TPDM_DSB_TPRm(m) (0x00BB9788+0x4*(m)) +#define DBG_TPDM_DSB_TPRm_mMIN 7 +#define DBG_TPDM_DSB_TPRm_mMAX 7 +#define DBG_TPDM_DSB_TPRm_ELEM 1 +#define DBG_TPDM_DSB_TPRm___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_TPRm___POR 0x00000000 +#define DBG_TPDM_DSB_TPRm__VAL___POR 0x00000000 +#define DBG_TPDM_DSB_TPRm__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_TPRm__VAL___S 0 +#define DBG_TPDM_DSB_TPRm___M 0xFFFFFFFF +#define DBG_TPDM_DSB_TPRm___S 0 +#define DBG_TPDM_DSB_TPR7 (0x00BB97A4) +#define DBG_TPDM_DSB_TPR7___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_TPR7__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_TPR7__VAL___S 0 + +#define DBG_TPDM_DSB_TPMRn(n) (0x00BB97A8+0x4*(n)) +#define DBG_TPDM_DSB_TPMRn_nMIN 0 +#define DBG_TPDM_DSB_TPMRn_nMAX 6 +#define DBG_TPDM_DSB_TPMRn_ELEM 7 +#define DBG_TPDM_DSB_TPMRn___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_TPMRn___POR 0x00000000 +#define DBG_TPDM_DSB_TPMRn__VAL___POR 0x00000000 +#define DBG_TPDM_DSB_TPMRn__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_TPMRn__VAL___S 0 +#define DBG_TPDM_DSB_TPMRn___M 0xFFFFFFFF +#define DBG_TPDM_DSB_TPMRn___S 0 +#define DBG_TPDM_DSB_TPMR0 (0x00BB97A8) +#define DBG_TPDM_DSB_TPMR0___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_TPMR0__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_TPMR0__VAL___S 0 +#define DBG_TPDM_DSB_TPMR1 (0x00BB97AC) +#define DBG_TPDM_DSB_TPMR1___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_TPMR1__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_TPMR1__VAL___S 0 +#define DBG_TPDM_DSB_TPMR2 (0x00BB97B0) +#define DBG_TPDM_DSB_TPMR2___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_TPMR2__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_TPMR2__VAL___S 0 +#define DBG_TPDM_DSB_TPMR3 (0x00BB97B4) +#define DBG_TPDM_DSB_TPMR3___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_TPMR3__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_TPMR3__VAL___S 0 +#define DBG_TPDM_DSB_TPMR4 (0x00BB97B8) +#define DBG_TPDM_DSB_TPMR4___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_TPMR4__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_TPMR4__VAL___S 0 +#define DBG_TPDM_DSB_TPMR5 (0x00BB97BC) +#define DBG_TPDM_DSB_TPMR5___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_TPMR5__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_TPMR5__VAL___S 0 +#define DBG_TPDM_DSB_TPMR6 (0x00BB97C0) +#define DBG_TPDM_DSB_TPMR6___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_TPMR6__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_TPMR6__VAL___S 0 + +#define DBG_TPDM_DSB_TPMRm(m) (0x00BB97A8+0x4*(m)) +#define DBG_TPDM_DSB_TPMRm_mMIN 7 +#define DBG_TPDM_DSB_TPMRm_mMAX 7 +#define DBG_TPDM_DSB_TPMRm_ELEM 1 +#define DBG_TPDM_DSB_TPMRm___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_TPMRm___POR 0x00000000 +#define DBG_TPDM_DSB_TPMRm__VAL___POR 0x00000000 +#define DBG_TPDM_DSB_TPMRm__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_TPMRm__VAL___S 0 +#define DBG_TPDM_DSB_TPMRm___M 0xFFFFFFFF +#define DBG_TPDM_DSB_TPMRm___S 0 +#define DBG_TPDM_DSB_TPMR7 (0x00BB97C4) +#define DBG_TPDM_DSB_TPMR7___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_TPMR7__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_TPMR7__VAL___S 0 + +#define DBG_TPDM_DSB_XPRn(n) (0x00BB97C8+0x4*(n)) +#define DBG_TPDM_DSB_XPRn_nMIN 0 +#define DBG_TPDM_DSB_XPRn_nMAX 6 +#define DBG_TPDM_DSB_XPRn_ELEM 7 +#define DBG_TPDM_DSB_XPRn___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_XPRn___POR 0x00000000 +#define DBG_TPDM_DSB_XPRn__VAL___POR 0x00000000 +#define DBG_TPDM_DSB_XPRn__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_XPRn__VAL___S 0 +#define DBG_TPDM_DSB_XPRn___M 0xFFFFFFFF +#define DBG_TPDM_DSB_XPRn___S 0 +#define DBG_TPDM_DSB_XPR0 (0x00BB97C8) +#define DBG_TPDM_DSB_XPR0___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_XPR0__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_XPR0__VAL___S 0 +#define DBG_TPDM_DSB_XPR1 (0x00BB97CC) +#define DBG_TPDM_DSB_XPR1___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_XPR1__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_XPR1__VAL___S 0 +#define DBG_TPDM_DSB_XPR2 (0x00BB97D0) +#define DBG_TPDM_DSB_XPR2___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_XPR2__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_XPR2__VAL___S 0 +#define DBG_TPDM_DSB_XPR3 (0x00BB97D4) +#define DBG_TPDM_DSB_XPR3___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_XPR3__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_XPR3__VAL___S 0 +#define DBG_TPDM_DSB_XPR4 (0x00BB97D8) +#define DBG_TPDM_DSB_XPR4___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_XPR4__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_XPR4__VAL___S 0 +#define DBG_TPDM_DSB_XPR5 (0x00BB97DC) +#define DBG_TPDM_DSB_XPR5___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_XPR5__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_XPR5__VAL___S 0 +#define DBG_TPDM_DSB_XPR6 (0x00BB97E0) +#define DBG_TPDM_DSB_XPR6___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_XPR6__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_XPR6__VAL___S 0 + +#define DBG_TPDM_DSB_XPRm(m) (0x00BB97C8+0x4*(m)) +#define DBG_TPDM_DSB_XPRm_mMIN 7 +#define DBG_TPDM_DSB_XPRm_mMAX 7 +#define DBG_TPDM_DSB_XPRm_ELEM 1 +#define DBG_TPDM_DSB_XPRm___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_XPRm___POR 0x00000000 +#define DBG_TPDM_DSB_XPRm__VAL___POR 0x00000000 +#define DBG_TPDM_DSB_XPRm__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_XPRm__VAL___S 0 +#define DBG_TPDM_DSB_XPRm___M 0xFFFFFFFF +#define DBG_TPDM_DSB_XPRm___S 0 +#define DBG_TPDM_DSB_XPR7 (0x00BB97E4) +#define DBG_TPDM_DSB_XPR7___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_XPR7__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_XPR7__VAL___S 0 + +#define DBG_TPDM_DSB_XPMRn(n) (0x00BB97E8+0x4*(n)) +#define DBG_TPDM_DSB_XPMRn_nMIN 0 +#define DBG_TPDM_DSB_XPMRn_nMAX 6 +#define DBG_TPDM_DSB_XPMRn_ELEM 7 +#define DBG_TPDM_DSB_XPMRn___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_XPMRn___POR 0x00000000 +#define DBG_TPDM_DSB_XPMRn__VAL___POR 0x00000000 +#define DBG_TPDM_DSB_XPMRn__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_XPMRn__VAL___S 0 +#define DBG_TPDM_DSB_XPMRn___M 0xFFFFFFFF +#define DBG_TPDM_DSB_XPMRn___S 0 +#define DBG_TPDM_DSB_XPMR0 (0x00BB97E8) +#define DBG_TPDM_DSB_XPMR0___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_XPMR0__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_XPMR0__VAL___S 0 +#define DBG_TPDM_DSB_XPMR1 (0x00BB97EC) +#define DBG_TPDM_DSB_XPMR1___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_XPMR1__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_XPMR1__VAL___S 0 +#define DBG_TPDM_DSB_XPMR2 (0x00BB97F0) +#define DBG_TPDM_DSB_XPMR2___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_XPMR2__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_XPMR2__VAL___S 0 +#define DBG_TPDM_DSB_XPMR3 (0x00BB97F4) +#define DBG_TPDM_DSB_XPMR3___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_XPMR3__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_XPMR3__VAL___S 0 +#define DBG_TPDM_DSB_XPMR4 (0x00BB97F8) +#define DBG_TPDM_DSB_XPMR4___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_XPMR4__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_XPMR4__VAL___S 0 +#define DBG_TPDM_DSB_XPMR5 (0x00BB97FC) +#define DBG_TPDM_DSB_XPMR5___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_XPMR5__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_XPMR5__VAL___S 0 +#define DBG_TPDM_DSB_XPMR6 (0x00BB9800) +#define DBG_TPDM_DSB_XPMR6___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_XPMR6__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_XPMR6__VAL___S 0 + +#define DBG_TPDM_DSB_XPMRm(m) (0x00BB97E8+0x4*(m)) +#define DBG_TPDM_DSB_XPMRm_mMIN 7 +#define DBG_TPDM_DSB_XPMRm_mMAX 7 +#define DBG_TPDM_DSB_XPMRm_ELEM 1 +#define DBG_TPDM_DSB_XPMRm___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_XPMRm___POR 0x00000000 +#define DBG_TPDM_DSB_XPMRm__VAL___POR 0x00000000 +#define DBG_TPDM_DSB_XPMRm__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_XPMRm__VAL___S 0 +#define DBG_TPDM_DSB_XPMRm___M 0xFFFFFFFF +#define DBG_TPDM_DSB_XPMRm___S 0 +#define DBG_TPDM_DSB_XPMR7 (0x00BB9804) +#define DBG_TPDM_DSB_XPMR7___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_XPMR7__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_XPMR7__VAL___S 0 + +#define DBG_TPDM_DSB_EDCRn(n) (0x00BB9808+0x4*(n)) +#define DBG_TPDM_DSB_EDCRn_nMIN 0 +#define DBG_TPDM_DSB_EDCRn_nMAX 14 +#define DBG_TPDM_DSB_EDCRn_ELEM 15 +#define DBG_TPDM_DSB_EDCRn___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_EDCRn___POR 0x00000000 +#define DBG_TPDM_DSB_EDCRn__EDGECONTROL___POR 0x00000000 +#define DBG_TPDM_DSB_EDCRn__EDGECONTROL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_EDCRn__EDGECONTROL___S 0 +#define DBG_TPDM_DSB_EDCRn___M 0xFFFFFFFF +#define DBG_TPDM_DSB_EDCRn___S 0 +#define DBG_TPDM_DSB_EDCR0 (0x00BB9808) +#define DBG_TPDM_DSB_EDCR0___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_EDCR0__EDGECONTROL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_EDCR0__EDGECONTROL___S 0 +#define DBG_TPDM_DSB_EDCR1 (0x00BB980C) +#define DBG_TPDM_DSB_EDCR1___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_EDCR1__EDGECONTROL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_EDCR1__EDGECONTROL___S 0 +#define DBG_TPDM_DSB_EDCR2 (0x00BB9810) +#define DBG_TPDM_DSB_EDCR2___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_EDCR2__EDGECONTROL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_EDCR2__EDGECONTROL___S 0 +#define DBG_TPDM_DSB_EDCR3 (0x00BB9814) +#define DBG_TPDM_DSB_EDCR3___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_EDCR3__EDGECONTROL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_EDCR3__EDGECONTROL___S 0 +#define DBG_TPDM_DSB_EDCR4 (0x00BB9818) +#define DBG_TPDM_DSB_EDCR4___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_EDCR4__EDGECONTROL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_EDCR4__EDGECONTROL___S 0 +#define DBG_TPDM_DSB_EDCR5 (0x00BB981C) +#define DBG_TPDM_DSB_EDCR5___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_EDCR5__EDGECONTROL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_EDCR5__EDGECONTROL___S 0 +#define DBG_TPDM_DSB_EDCR6 (0x00BB9820) +#define DBG_TPDM_DSB_EDCR6___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_EDCR6__EDGECONTROL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_EDCR6__EDGECONTROL___S 0 +#define DBG_TPDM_DSB_EDCR7 (0x00BB9824) +#define DBG_TPDM_DSB_EDCR7___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_EDCR7__EDGECONTROL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_EDCR7__EDGECONTROL___S 0 +#define DBG_TPDM_DSB_EDCR8 (0x00BB9828) +#define DBG_TPDM_DSB_EDCR8___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_EDCR8__EDGECONTROL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_EDCR8__EDGECONTROL___S 0 +#define DBG_TPDM_DSB_EDCR9 (0x00BB982C) +#define DBG_TPDM_DSB_EDCR9___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_EDCR9__EDGECONTROL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_EDCR9__EDGECONTROL___S 0 +#define DBG_TPDM_DSB_EDCR10 (0x00BB9830) +#define DBG_TPDM_DSB_EDCR10___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_EDCR10__EDGECONTROL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_EDCR10__EDGECONTROL___S 0 +#define DBG_TPDM_DSB_EDCR11 (0x00BB9834) +#define DBG_TPDM_DSB_EDCR11___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_EDCR11__EDGECONTROL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_EDCR11__EDGECONTROL___S 0 +#define DBG_TPDM_DSB_EDCR12 (0x00BB9838) +#define DBG_TPDM_DSB_EDCR12___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_EDCR12__EDGECONTROL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_EDCR12__EDGECONTROL___S 0 +#define DBG_TPDM_DSB_EDCR13 (0x00BB983C) +#define DBG_TPDM_DSB_EDCR13___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_EDCR13__EDGECONTROL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_EDCR13__EDGECONTROL___S 0 +#define DBG_TPDM_DSB_EDCR14 (0x00BB9840) +#define DBG_TPDM_DSB_EDCR14___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_EDCR14__EDGECONTROL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_EDCR14__EDGECONTROL___S 0 + +#define DBG_TPDM_DSB_EDCRm(m) (0x00BB9808+0x4*(m)) +#define DBG_TPDM_DSB_EDCRm_mMIN 15 +#define DBG_TPDM_DSB_EDCRm_mMAX 15 +#define DBG_TPDM_DSB_EDCRm_ELEM 1 +#define DBG_TPDM_DSB_EDCRm___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_EDCRm___POR 0x00000000 +#define DBG_TPDM_DSB_EDCRm__EDGECONTROL___POR 0x00000000 +#define DBG_TPDM_DSB_EDCRm__EDGECONTROL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_EDCRm__EDGECONTROL___S 0 +#define DBG_TPDM_DSB_EDCRm___M 0xFFFFFFFF +#define DBG_TPDM_DSB_EDCRm___S 0 +#define DBG_TPDM_DSB_EDCR15 (0x00BB9844) +#define DBG_TPDM_DSB_EDCR15___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_EDCR15__EDGECONTROL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_EDCR15__EDGECONTROL___S 0 + +#define DBG_TPDM_DSB_EDCMRn(n) (0x00BB9848+0x4*(n)) +#define DBG_TPDM_DSB_EDCMRn_nMIN 0 +#define DBG_TPDM_DSB_EDCMRn_nMAX 6 +#define DBG_TPDM_DSB_EDCMRn_ELEM 7 +#define DBG_TPDM_DSB_EDCMRn___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_EDCMRn___POR 0x00000000 +#define DBG_TPDM_DSB_EDCMRn__VAL___POR 0x00000000 +#define DBG_TPDM_DSB_EDCMRn__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_EDCMRn__VAL___S 0 +#define DBG_TPDM_DSB_EDCMRn___M 0xFFFFFFFF +#define DBG_TPDM_DSB_EDCMRn___S 0 +#define DBG_TPDM_DSB_EDCMR0 (0x00BB9848) +#define DBG_TPDM_DSB_EDCMR0___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_EDCMR0__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_EDCMR0__VAL___S 0 +#define DBG_TPDM_DSB_EDCMR1 (0x00BB984C) +#define DBG_TPDM_DSB_EDCMR1___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_EDCMR1__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_EDCMR1__VAL___S 0 +#define DBG_TPDM_DSB_EDCMR2 (0x00BB9850) +#define DBG_TPDM_DSB_EDCMR2___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_EDCMR2__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_EDCMR2__VAL___S 0 +#define DBG_TPDM_DSB_EDCMR3 (0x00BB9854) +#define DBG_TPDM_DSB_EDCMR3___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_EDCMR3__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_EDCMR3__VAL___S 0 +#define DBG_TPDM_DSB_EDCMR4 (0x00BB9858) +#define DBG_TPDM_DSB_EDCMR4___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_EDCMR4__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_EDCMR4__VAL___S 0 +#define DBG_TPDM_DSB_EDCMR5 (0x00BB985C) +#define DBG_TPDM_DSB_EDCMR5___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_EDCMR5__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_EDCMR5__VAL___S 0 +#define DBG_TPDM_DSB_EDCMR6 (0x00BB9860) +#define DBG_TPDM_DSB_EDCMR6___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_EDCMR6__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_EDCMR6__VAL___S 0 + +#define DBG_TPDM_DSB_EDCMRm(m) (0x00BB9848+0x4*(m)) +#define DBG_TPDM_DSB_EDCMRm_mMIN 7 +#define DBG_TPDM_DSB_EDCMRm_mMAX 7 +#define DBG_TPDM_DSB_EDCMRm_ELEM 1 +#define DBG_TPDM_DSB_EDCMRm___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_EDCMRm___POR 0x00000000 +#define DBG_TPDM_DSB_EDCMRm__VAL___POR 0x00000000 +#define DBG_TPDM_DSB_EDCMRm__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_EDCMRm__VAL___S 0 +#define DBG_TPDM_DSB_EDCMRm___M 0xFFFFFFFF +#define DBG_TPDM_DSB_EDCMRm___S 0 +#define DBG_TPDM_DSB_EDCMR7 (0x00BB9864) +#define DBG_TPDM_DSB_EDCMR7___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_EDCMR7__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_EDCMR7__VAL___S 0 + +#define DBG_TPDM_DSB_READCTL (0x00BB9970) +#define DBG_TPDM_DSB_READCTL___RWC QCSR_REG_RW +#define DBG_TPDM_DSB_READCTL___POR 0x00000000 +#define DBG_TPDM_DSB_READCTL__MODE___POR 0x0 +#define DBG_TPDM_DSB_READCTL__SLICESEL___POR 0x0 +#define DBG_TPDM_DSB_READCTL__MODE___M 0x00000008 +#define DBG_TPDM_DSB_READCTL__MODE___S 3 +#define DBG_TPDM_DSB_READCTL__SLICESEL___M 0x00000007 +#define DBG_TPDM_DSB_READCTL__SLICESEL___S 0 +#define DBG_TPDM_DSB_READCTL___M 0x0000000F +#define DBG_TPDM_DSB_READCTL___S 0 + +#define DBG_TPDM_DSB_READVAL (0x00BB9974) +#define DBG_TPDM_DSB_READVAL___RWC QCSR_REG_RO +#define DBG_TPDM_DSB_READVAL___POR 0x00000000 +#define DBG_TPDM_DSB_READVAL__VALUE___POR 0x00000000 +#define DBG_TPDM_DSB_READVAL__VALUE___M 0xFFFFFFFF +#define DBG_TPDM_DSB_READVAL__VALUE___S 0 +#define DBG_TPDM_DSB_READVAL___M 0xFFFFFFFF +#define DBG_TPDM_DSB_READVAL___S 0 + +#define DBG_TPDM_CMB_CR (0x00BB9A00) +#define DBG_TPDM_CMB_CR___RWC QCSR_REG_RW +#define DBG_TPDM_CMB_CR___POR 0x00000000 +#define DBG_TPDM_CMB_CR__ATBFLOWERR___POR 0x0 +#define DBG_TPDM_CMB_CR__EBITSET___POR 0x0 +#define DBG_TPDM_CMB_CR__FLOWCTRL___POR 0x0 +#define DBG_TPDM_CMB_CR__MODE___POR 0x0 +#define DBG_TPDM_CMB_CR__E___POR 0x0 +#define DBG_TPDM_CMB_CR__ATBFLOWERR___M 0x00000080 +#define DBG_TPDM_CMB_CR__ATBFLOWERR___S 7 +#define DBG_TPDM_CMB_CR__EBITSET___M 0x00000040 +#define DBG_TPDM_CMB_CR__EBITSET___S 6 +#define DBG_TPDM_CMB_CR__FLOWCTRL___M 0x00000004 +#define DBG_TPDM_CMB_CR__FLOWCTRL___S 2 +#define DBG_TPDM_CMB_CR__MODE___M 0x00000002 +#define DBG_TPDM_CMB_CR__MODE___S 1 +#define DBG_TPDM_CMB_CR__E___M 0x00000001 +#define DBG_TPDM_CMB_CR__E___S 0 +#define DBG_TPDM_CMB_CR___M 0x000000C7 +#define DBG_TPDM_CMB_CR___S 0 + +#define DBG_TPDM_CMB_TIER (0x00BB9A04) +#define DBG_TPDM_CMB_TIER___RWC QCSR_REG_RW +#define DBG_TPDM_CMB_TIER___POR 0x00000000 +#define DBG_TPDM_CMB_TIER__TS_ALL___POR 0x0 +#define DBG_TPDM_CMB_TIER__XTRIG_TSENAB___POR 0x0 +#define DBG_TPDM_CMB_TIER__PATT_TSENAB___POR 0x0 +#define DBG_TPDM_CMB_TIER__TS_ALL___M 0x00000004 +#define DBG_TPDM_CMB_TIER__TS_ALL___S 2 +#define DBG_TPDM_CMB_TIER__XTRIG_TSENAB___M 0x00000002 +#define DBG_TPDM_CMB_TIER__XTRIG_TSENAB___S 1 +#define DBG_TPDM_CMB_TIER__PATT_TSENAB___M 0x00000001 +#define DBG_TPDM_CMB_TIER__PATT_TSENAB___S 0 +#define DBG_TPDM_CMB_TIER___M 0x00000007 +#define DBG_TPDM_CMB_TIER___S 0 + +#define DBG_TPDM_CMB_TPRn(n) (0x00BB9A08+0x4*(n)) +#define DBG_TPDM_CMB_TPRn_nMIN 0 +#define DBG_TPDM_CMB_TPRn_nMAX 0 +#define DBG_TPDM_CMB_TPRn_ELEM 1 +#define DBG_TPDM_CMB_TPRn___RWC QCSR_REG_RW +#define DBG_TPDM_CMB_TPRn___POR 0x00000000 +#define DBG_TPDM_CMB_TPRn__VAL___POR 0x00000000 +#define DBG_TPDM_CMB_TPRn__VAL___M 0xFFFFFFFF +#define DBG_TPDM_CMB_TPRn__VAL___S 0 +#define DBG_TPDM_CMB_TPRn___M 0xFFFFFFFF +#define DBG_TPDM_CMB_TPRn___S 0 +#define DBG_TPDM_CMB_TPR0 (0x00BB9A08) +#define DBG_TPDM_CMB_TPR0___RWC QCSR_REG_RW +#define DBG_TPDM_CMB_TPR0__VAL___M 0xFFFFFFFF +#define DBG_TPDM_CMB_TPR0__VAL___S 0 + +#define DBG_TPDM_CMB_TPRm(m) (0x00BB9A08+0x4*(m)) +#define DBG_TPDM_CMB_TPRm_mMIN 1 +#define DBG_TPDM_CMB_TPRm_mMAX 1 +#define DBG_TPDM_CMB_TPRm_ELEM 1 +#define DBG_TPDM_CMB_TPRm___RWC QCSR_REG_RW +#define DBG_TPDM_CMB_TPRm___POR 0x00000000 +#define DBG_TPDM_CMB_TPRm__VAL___POR 0x00 +#define DBG_TPDM_CMB_TPRm__VAL___M 0x000000FF +#define DBG_TPDM_CMB_TPRm__VAL___S 0 +#define DBG_TPDM_CMB_TPRm___M 0x000000FF +#define DBG_TPDM_CMB_TPRm___S 0 +#define DBG_TPDM_CMB_TPR1 (0x00BB9A0C) +#define DBG_TPDM_CMB_TPR1___RWC QCSR_REG_RW +#define DBG_TPDM_CMB_TPR1__VAL___M 0x000000FF +#define DBG_TPDM_CMB_TPR1__VAL___S 0 + +#define DBG_TPDM_CMB_TPMRn(n) (0x00BB9A10+0x4*(n)) +#define DBG_TPDM_CMB_TPMRn_nMIN 0 +#define DBG_TPDM_CMB_TPMRn_nMAX 0 +#define DBG_TPDM_CMB_TPMRn_ELEM 1 +#define DBG_TPDM_CMB_TPMRn___RWC QCSR_REG_RW +#define DBG_TPDM_CMB_TPMRn___POR 0x00000000 +#define DBG_TPDM_CMB_TPMRn__VAL___POR 0x00000000 +#define DBG_TPDM_CMB_TPMRn__VAL___M 0xFFFFFFFF +#define DBG_TPDM_CMB_TPMRn__VAL___S 0 +#define DBG_TPDM_CMB_TPMRn___M 0xFFFFFFFF +#define DBG_TPDM_CMB_TPMRn___S 0 +#define DBG_TPDM_CMB_TPMR0 (0x00BB9A10) +#define DBG_TPDM_CMB_TPMR0___RWC QCSR_REG_RW +#define DBG_TPDM_CMB_TPMR0__VAL___M 0xFFFFFFFF +#define DBG_TPDM_CMB_TPMR0__VAL___S 0 + +#define DBG_TPDM_CMB_TPMRm(m) (0x00BB9A10+0x4*(m)) +#define DBG_TPDM_CMB_TPMRm_mMIN 1 +#define DBG_TPDM_CMB_TPMRm_mMAX 1 +#define DBG_TPDM_CMB_TPMRm_ELEM 1 +#define DBG_TPDM_CMB_TPMRm___RWC QCSR_REG_RW +#define DBG_TPDM_CMB_TPMRm___POR 0x00000000 +#define DBG_TPDM_CMB_TPMRm__VAL___POR 0x00 +#define DBG_TPDM_CMB_TPMRm__VAL___M 0x000000FF +#define DBG_TPDM_CMB_TPMRm__VAL___S 0 +#define DBG_TPDM_CMB_TPMRm___M 0x000000FF +#define DBG_TPDM_CMB_TPMRm___S 0 +#define DBG_TPDM_CMB_TPMR1 (0x00BB9A14) +#define DBG_TPDM_CMB_TPMR1___RWC QCSR_REG_RW +#define DBG_TPDM_CMB_TPMR1__VAL___M 0x000000FF +#define DBG_TPDM_CMB_TPMR1__VAL___S 0 + +#define DBG_TPDM_CMB_XPRn(n) (0x00BB9A18+0x4*(n)) +#define DBG_TPDM_CMB_XPRn_nMIN 0 +#define DBG_TPDM_CMB_XPRn_nMAX 0 +#define DBG_TPDM_CMB_XPRn_ELEM 1 +#define DBG_TPDM_CMB_XPRn___RWC QCSR_REG_RW +#define DBG_TPDM_CMB_XPRn___POR 0x00000000 +#define DBG_TPDM_CMB_XPRn__VAL___POR 0x00000000 +#define DBG_TPDM_CMB_XPRn__VAL___M 0xFFFFFFFF +#define DBG_TPDM_CMB_XPRn__VAL___S 0 +#define DBG_TPDM_CMB_XPRn___M 0xFFFFFFFF +#define DBG_TPDM_CMB_XPRn___S 0 +#define DBG_TPDM_CMB_XPR0 (0x00BB9A18) +#define DBG_TPDM_CMB_XPR0___RWC QCSR_REG_RW +#define DBG_TPDM_CMB_XPR0__VAL___M 0xFFFFFFFF +#define DBG_TPDM_CMB_XPR0__VAL___S 0 + +#define DBG_TPDM_CMB_XPRm(m) (0x00BB9A18+0x4*(m)) +#define DBG_TPDM_CMB_XPRm_mMIN 1 +#define DBG_TPDM_CMB_XPRm_mMAX 1 +#define DBG_TPDM_CMB_XPRm_ELEM 1 +#define DBG_TPDM_CMB_XPRm___RWC QCSR_REG_RW +#define DBG_TPDM_CMB_XPRm___POR 0x00000000 +#define DBG_TPDM_CMB_XPRm__VAL___POR 0x00 +#define DBG_TPDM_CMB_XPRm__VAL___M 0x000000FF +#define DBG_TPDM_CMB_XPRm__VAL___S 0 +#define DBG_TPDM_CMB_XPRm___M 0x000000FF +#define DBG_TPDM_CMB_XPRm___S 0 +#define DBG_TPDM_CMB_XPR1 (0x00BB9A1C) +#define DBG_TPDM_CMB_XPR1___RWC QCSR_REG_RW +#define DBG_TPDM_CMB_XPR1__VAL___M 0x000000FF +#define DBG_TPDM_CMB_XPR1__VAL___S 0 + +#define DBG_TPDM_CMB_XPMRn(n) (0x00BB9A20+0x4*(n)) +#define DBG_TPDM_CMB_XPMRn_nMIN 0 +#define DBG_TPDM_CMB_XPMRn_nMAX 0 +#define DBG_TPDM_CMB_XPMRn_ELEM 1 +#define DBG_TPDM_CMB_XPMRn___RWC QCSR_REG_RW +#define DBG_TPDM_CMB_XPMRn___POR 0x00000000 +#define DBG_TPDM_CMB_XPMRn__VAL___POR 0x00000000 +#define DBG_TPDM_CMB_XPMRn__VAL___M 0xFFFFFFFF +#define DBG_TPDM_CMB_XPMRn__VAL___S 0 +#define DBG_TPDM_CMB_XPMRn___M 0xFFFFFFFF +#define DBG_TPDM_CMB_XPMRn___S 0 +#define DBG_TPDM_CMB_XPMR0 (0x00BB9A20) +#define DBG_TPDM_CMB_XPMR0___RWC QCSR_REG_RW +#define DBG_TPDM_CMB_XPMR0__VAL___M 0xFFFFFFFF +#define DBG_TPDM_CMB_XPMR0__VAL___S 0 + +#define DBG_TPDM_CMB_XPMRm(m) (0x00BB9A20+0x4*(m)) +#define DBG_TPDM_CMB_XPMRm_mMIN 1 +#define DBG_TPDM_CMB_XPMRm_mMAX 1 +#define DBG_TPDM_CMB_XPMRm_ELEM 1 +#define DBG_TPDM_CMB_XPMRm___RWC QCSR_REG_RW +#define DBG_TPDM_CMB_XPMRm___POR 0x00000000 +#define DBG_TPDM_CMB_XPMRm__VAL___POR 0x00 +#define DBG_TPDM_CMB_XPMRm__VAL___M 0x000000FF +#define DBG_TPDM_CMB_XPMRm__VAL___S 0 +#define DBG_TPDM_CMB_XPMRm___M 0x000000FF +#define DBG_TPDM_CMB_XPMRm___S 0 +#define DBG_TPDM_CMB_XPMR1 (0x00BB9A24) +#define DBG_TPDM_CMB_XPMR1___RWC QCSR_REG_RW +#define DBG_TPDM_CMB_XPMR1__VAL___M 0x000000FF +#define DBG_TPDM_CMB_XPMR1__VAL___S 0 + +#define DBG_TPDM_CMB_READCTL (0x00BB9A70) +#define DBG_TPDM_CMB_READCTL___RWC QCSR_REG_RW +#define DBG_TPDM_CMB_READCTL___POR 0x00000000 +#define DBG_TPDM_CMB_READCTL__SEL___POR 0x0 +#define DBG_TPDM_CMB_READCTL__SEL___M 0x00000001 +#define DBG_TPDM_CMB_READCTL__SEL___S 0 +#define DBG_TPDM_CMB_READCTL___M 0x00000001 +#define DBG_TPDM_CMB_READCTL___S 0 + +#define DBG_TPDM_CMB_READVAL (0x00BB9A74) +#define DBG_TPDM_CMB_READVAL___RWC QCSR_REG_RO +#define DBG_TPDM_CMB_READVAL___POR 0x00000000 +#define DBG_TPDM_CMB_READVAL__VALUE___POR 0x00000000 +#define DBG_TPDM_CMB_READVAL__VALUE___M 0xFFFFFFFF +#define DBG_TPDM_CMB_READVAL__VALUE___S 0 +#define DBG_TPDM_CMB_READVAL___M 0xFFFFFFFF +#define DBG_TPDM_CMB_READVAL___S 0 + +#define DBG_TPDM_ITATBCNTRL (0x00BB9EF0) +#define DBG_TPDM_ITATBCNTRL___RWC QCSR_REG_RW +#define DBG_TPDM_ITATBCNTRL___POR 0x00000000 +#define DBG_TPDM_ITATBCNTRL__TSREQ___POR 0x0 +#define DBG_TPDM_ITATBCNTRL__ATVALID___POR 0x0 +#define DBG_TPDM_ITATBCNTRL__ATDATAMODE___POR 0x0 +#define DBG_TPDM_ITATBCNTRL__ATBYTES___POR 0x0 +#define DBG_TPDM_ITATBCNTRL__ATDATA___POR 0x00 +#define DBG_TPDM_ITATBCNTRL__ATID___POR 0x00 +#define DBG_TPDM_ITATBCNTRL__TSVAL___POR 0x0 +#define DBG_TPDM_ITATBCNTRL__TSREQ___M 0x80000000 +#define DBG_TPDM_ITATBCNTRL__TSREQ___S 31 +#define DBG_TPDM_ITATBCNTRL__ATVALID___M 0x40000000 +#define DBG_TPDM_ITATBCNTRL__ATVALID___S 30 +#define DBG_TPDM_ITATBCNTRL__ATDATAMODE___M 0x00400000 +#define DBG_TPDM_ITATBCNTRL__ATDATAMODE___S 22 +#define DBG_TPDM_ITATBCNTRL__ATBYTES___M 0x003C0000 +#define DBG_TPDM_ITATBCNTRL__ATBYTES___S 18 +#define DBG_TPDM_ITATBCNTRL__ATDATA___M 0x0003FC00 +#define DBG_TPDM_ITATBCNTRL__ATDATA___S 10 +#define DBG_TPDM_ITATBCNTRL__ATID___M 0x000003F8 +#define DBG_TPDM_ITATBCNTRL__ATID___S 3 +#define DBG_TPDM_ITATBCNTRL__TSVAL___M 0x00000007 +#define DBG_TPDM_ITATBCNTRL__TSVAL___S 0 +#define DBG_TPDM_ITATBCNTRL___M 0xC07FFFFF +#define DBG_TPDM_ITATBCNTRL___S 0 + +#define DBG_TPDM_ITCNTRL (0x00BB9F00) +#define DBG_TPDM_ITCNTRL___RWC QCSR_REG_RW +#define DBG_TPDM_ITCNTRL___POR 0x00000000 +#define DBG_TPDM_ITCNTRL__IME___POR 0x0 +#define DBG_TPDM_ITCNTRL__IME___M 0x00000001 +#define DBG_TPDM_ITCNTRL__IME___S 0 +#define DBG_TPDM_ITCNTRL___M 0x00000001 +#define DBG_TPDM_ITCNTRL___S 0 + +#define DBG_TPDM_CLAIMSET (0x00BB9FA0) +#define DBG_TPDM_CLAIMSET___RWC QCSR_REG_RO +#define DBG_TPDM_CLAIMSET___POR 0x00000000 +#define DBG_TPDM_CLAIMSET__VAL_SET___POR 0x00000000 +#define DBG_TPDM_CLAIMSET__VAL_SET___M 0xFFFFFFFF +#define DBG_TPDM_CLAIMSET__VAL_SET___S 0 +#define DBG_TPDM_CLAIMSET___M 0xFFFFFFFF +#define DBG_TPDM_CLAIMSET___S 0 + +#define DBG_TPDM_CLAIMCLR (0x00BB9FA4) +#define DBG_TPDM_CLAIMCLR___RWC QCSR_REG_RO +#define DBG_TPDM_CLAIMCLR___POR 0x00000000 +#define DBG_TPDM_CLAIMCLR__VAL_CLR___POR 0x00000000 +#define DBG_TPDM_CLAIMCLR__VAL_CLR___M 0xFFFFFFFF +#define DBG_TPDM_CLAIMCLR__VAL_CLR___S 0 +#define DBG_TPDM_CLAIMCLR___M 0xFFFFFFFF +#define DBG_TPDM_CLAIMCLR___S 0 + +#define DBG_TPDM_DEVAFF0 (0x00BB9FA8) +#define DBG_TPDM_DEVAFF0___RWC QCSR_REG_RO +#define DBG_TPDM_DEVAFF0___POR 0x00000000 +#define DBG_TPDM_DEVAFF0__VAL___POR 0x00000000 +#define DBG_TPDM_DEVAFF0__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DEVAFF0__VAL___S 0 +#define DBG_TPDM_DEVAFF0___M 0xFFFFFFFF +#define DBG_TPDM_DEVAFF0___S 0 + +#define DBG_TPDM_DEVAFF1 (0x00BB9FAC) +#define DBG_TPDM_DEVAFF1___RWC QCSR_REG_RO +#define DBG_TPDM_DEVAFF1___POR 0x00000000 +#define DBG_TPDM_DEVAFF1__VAL___POR 0x00000000 +#define DBG_TPDM_DEVAFF1__VAL___M 0xFFFFFFFF +#define DBG_TPDM_DEVAFF1__VAL___S 0 +#define DBG_TPDM_DEVAFF1___M 0xFFFFFFFF +#define DBG_TPDM_DEVAFF1___S 0 + +#define DBG_TPDM_LAR (0x00BB9FB0) +#define DBG_TPDM_LAR___RWC QCSR_REG_WO +#define DBG_TPDM_LAR___POR 0x00000000 +#define DBG_TPDM_LAR__KEY___POR 0x00000000 +#define DBG_TPDM_LAR__KEY___M 0xFFFFFFFF +#define DBG_TPDM_LAR__KEY___S 0 +#define DBG_TPDM_LAR___M 0xFFFFFFFF +#define DBG_TPDM_LAR___S 0 + +#define DBG_TPDM_LSR (0x00BB9FB4) +#define DBG_TPDM_LSR___RWC QCSR_REG_RO +#define DBG_TPDM_LSR___POR 0x00000003 +#define DBG_TPDM_LSR__NTT___POR 0x0 +#define DBG_TPDM_LSR__SLK___POR 0x1 +#define DBG_TPDM_LSR__SLI___POR 0x1 +#define DBG_TPDM_LSR__NTT___M 0x00000004 +#define DBG_TPDM_LSR__NTT___S 2 +#define DBG_TPDM_LSR__SLK___M 0x00000002 +#define DBG_TPDM_LSR__SLK___S 1 +#define DBG_TPDM_LSR__SLI___M 0x00000001 +#define DBG_TPDM_LSR__SLI___S 0 +#define DBG_TPDM_LSR___M 0x00000007 +#define DBG_TPDM_LSR___S 0 + +#define DBG_TPDM_AUTHSTATUS (0x00BB9FB8) +#define DBG_TPDM_AUTHSTATUS___RWC QCSR_REG_RO +#define DBG_TPDM_AUTHSTATUS___POR 0x000000AA +#define DBG_TPDM_AUTHSTATUS__SNID___POR 0x2 +#define DBG_TPDM_AUTHSTATUS__SID___POR 0x2 +#define DBG_TPDM_AUTHSTATUS__NSNID___POR 0x2 +#define DBG_TPDM_AUTHSTATUS__NSID___POR 0x2 +#define DBG_TPDM_AUTHSTATUS__SNID___M 0x000000C0 +#define DBG_TPDM_AUTHSTATUS__SNID___S 6 +#define DBG_TPDM_AUTHSTATUS__SID___M 0x00000030 +#define DBG_TPDM_AUTHSTATUS__SID___S 4 +#define DBG_TPDM_AUTHSTATUS__NSNID___M 0x0000000C +#define DBG_TPDM_AUTHSTATUS__NSNID___S 2 +#define DBG_TPDM_AUTHSTATUS__NSID___M 0x00000003 +#define DBG_TPDM_AUTHSTATUS__NSID___S 0 +#define DBG_TPDM_AUTHSTATUS___M 0x000000FF +#define DBG_TPDM_AUTHSTATUS___S 0 + +#define DBG_TPDM_DEVARCH (0x00BB9FBC) +#define DBG_TPDM_DEVARCH___RWC QCSR_REG_RO +#define DBG_TPDM_DEVARCH___POR 0x0E105CDA +#define DBG_TPDM_DEVARCH__ARCHITECT___POR 0x070 +#define DBG_TPDM_DEVARCH__PRESENT___POR 0x1 +#define DBG_TPDM_DEVARCH__REVISION___POR 0x0 +#define DBG_TPDM_DEVARCH__ARCHID___POR 0x5CDA +#define DBG_TPDM_DEVARCH__ARCHITECT___M 0xFFE00000 +#define DBG_TPDM_DEVARCH__ARCHITECT___S 21 +#define DBG_TPDM_DEVARCH__PRESENT___M 0x00100000 +#define DBG_TPDM_DEVARCH__PRESENT___S 20 +#define DBG_TPDM_DEVARCH__REVISION___M 0x000F0000 +#define DBG_TPDM_DEVARCH__REVISION___S 16 +#define DBG_TPDM_DEVARCH__ARCHID___M 0x0000FFFF +#define DBG_TPDM_DEVARCH__ARCHID___S 0 +#define DBG_TPDM_DEVARCH___M 0xFFFFFFFF +#define DBG_TPDM_DEVARCH___S 0 + +#define DBG_TPDM_DEVID1 (0x00BB9FC4) +#define DBG_TPDM_DEVID1___RWC QCSR_REG_RO +#define DBG_TPDM_DEVID1___POR 0x00000000 +#define DBG_TPDM_DEVID1__CMB_LIVE___POR 0x0 +#define DBG_TPDM_DEVID1__DSB_LIVE___POR 0x0 +#define DBG_TPDM_DEVID1__CMB_LIVE___M 0x80000000 +#define DBG_TPDM_DEVID1__CMB_LIVE___S 31 +#define DBG_TPDM_DEVID1__DSB_LIVE___M 0x40000000 +#define DBG_TPDM_DEVID1__DSB_LIVE___S 30 +#define DBG_TPDM_DEVID1___M 0xC0000000 +#define DBG_TPDM_DEVID1___S 30 + +#define DBG_TPDM_DEVID (0x00BB9FC8) +#define DBG_TPDM_DEVID___RWC QCSR_REG_RO +#define DBG_TPDM_DEVID___POR 0x15000008 +#define DBG_TPDM_DEVID__TC_LVL_TRIG___POR 0x2 +#define DBG_TPDM_DEVID__BC_LVL_TRIG___POR 0x2 +#define DBG_TPDM_DEVID__BC_GANG___POR 0x2 +#define DBG_TPDM_DEVID__CMB_IN___POR 0x2 +#define DBG_TPDM_DEVID__DSB_ELEM___POR 0x0 +#define DBG_TPDM_DEVID__TC_LVL_TRIG___M 0x18000000 +#define DBG_TPDM_DEVID__TC_LVL_TRIG___S 27 +#define DBG_TPDM_DEVID__BC_LVL_TRIG___M 0x06000000 +#define DBG_TPDM_DEVID__BC_LVL_TRIG___S 25 +#define DBG_TPDM_DEVID__BC_GANG___M 0x01800000 +#define DBG_TPDM_DEVID__BC_GANG___S 23 +#define DBG_TPDM_DEVID__CMB_IN___M 0x0000000C +#define DBG_TPDM_DEVID__CMB_IN___S 2 +#define DBG_TPDM_DEVID__DSB_ELEM___M 0x00000002 +#define DBG_TPDM_DEVID__DSB_ELEM___S 1 +#define DBG_TPDM_DEVID___M 0x1F80000E +#define DBG_TPDM_DEVID___S 1 + +#define DBG_TPDM_DEVTYPE (0x00BB9FCC) +#define DBG_TPDM_DEVTYPE___RWC QCSR_REG_RO +#define DBG_TPDM_DEVTYPE___POR 0x00000003 +#define DBG_TPDM_DEVTYPE__SUB___POR 0x0 +#define DBG_TPDM_DEVTYPE__MAJOR___POR 0x3 +#define DBG_TPDM_DEVTYPE__SUB___M 0x000000F0 +#define DBG_TPDM_DEVTYPE__SUB___S 4 +#define DBG_TPDM_DEVTYPE__MAJOR___M 0x0000000F +#define DBG_TPDM_DEVTYPE__MAJOR___S 0 +#define DBG_TPDM_DEVTYPE___M 0x000000FF +#define DBG_TPDM_DEVTYPE___S 0 + +#define DBG_TPDM_PIDR4 (0x00BB9FD0) +#define DBG_TPDM_PIDR4___RWC QCSR_REG_RO +#define DBG_TPDM_PIDR4___POR 0x00000000 +#define DBG_TPDM_PIDR4__SIZE___POR 0x0 +#define DBG_TPDM_PIDR4__DES_2___POR 0x0 +#define DBG_TPDM_PIDR4__SIZE___M 0x000000F0 +#define DBG_TPDM_PIDR4__SIZE___S 4 +#define DBG_TPDM_PIDR4__DES_2___M 0x0000000F +#define DBG_TPDM_PIDR4__DES_2___S 0 +#define DBG_TPDM_PIDR4___M 0x000000FF +#define DBG_TPDM_PIDR4___S 0 + +#define DBG_TPDM_PIDR5 (0x00BB9FD4) +#define DBG_TPDM_PIDR5___RWC QCSR_REG_RO +#define DBG_TPDM_PIDR5___POR 0x00000000 +#define DBG_TPDM_PIDR5__EMPTY___POR 0x00000000 +#define DBG_TPDM_PIDR5__EMPTY___M 0xFFFFFFFF +#define DBG_TPDM_PIDR5__EMPTY___S 0 +#define DBG_TPDM_PIDR5___M 0xFFFFFFFF +#define DBG_TPDM_PIDR5___S 0 + +#define DBG_TPDM_PIDR6 (0x00BB9FD8) +#define DBG_TPDM_PIDR6___RWC QCSR_REG_RO +#define DBG_TPDM_PIDR6___POR 0x00000000 +#define DBG_TPDM_PIDR6__EMPTY___POR 0x00000000 +#define DBG_TPDM_PIDR6__EMPTY___M 0xFFFFFFFF +#define DBG_TPDM_PIDR6__EMPTY___S 0 +#define DBG_TPDM_PIDR6___M 0xFFFFFFFF +#define DBG_TPDM_PIDR6___S 0 + +#define DBG_TPDM_PIDR7 (0x00BB9FDC) +#define DBG_TPDM_PIDR7___RWC QCSR_REG_RO +#define DBG_TPDM_PIDR7___POR 0x00000000 +#define DBG_TPDM_PIDR7__EMPTY___POR 0x00000000 +#define DBG_TPDM_PIDR7__EMPTY___M 0xFFFFFFFF +#define DBG_TPDM_PIDR7__EMPTY___S 0 +#define DBG_TPDM_PIDR7___M 0xFFFFFFFF +#define DBG_TPDM_PIDR7___S 0 + +#define DBG_TPDM_PIDR0 (0x00BB9FE0) +#define DBG_TPDM_PIDR0___RWC QCSR_REG_RO +#define DBG_TPDM_PIDR0___POR 0x00000026 +#define DBG_TPDM_PIDR0__PART_7___POR 0x0 +#define DBG_TPDM_PIDR0__PART_6___POR 0x0 +#define DBG_TPDM_PIDR0__PART_5___POR 0x1 +#define DBG_TPDM_PIDR0__PART_4___POR 0x0 +#define DBG_TPDM_PIDR0__PART_3___POR 0x0 +#define DBG_TPDM_PIDR0__PART_2___POR 0x1 +#define DBG_TPDM_PIDR0__PART_1___POR 0x1 +#define DBG_TPDM_PIDR0__PART_0___POR 0x0 +#define DBG_TPDM_PIDR0__PART_7___M 0x00000080 +#define DBG_TPDM_PIDR0__PART_7___S 7 +#define DBG_TPDM_PIDR0__PART_6___M 0x00000040 +#define DBG_TPDM_PIDR0__PART_6___S 6 +#define DBG_TPDM_PIDR0__PART_5___M 0x00000020 +#define DBG_TPDM_PIDR0__PART_5___S 5 +#define DBG_TPDM_PIDR0__PART_4___M 0x00000010 +#define DBG_TPDM_PIDR0__PART_4___S 4 +#define DBG_TPDM_PIDR0__PART_3___M 0x00000008 +#define DBG_TPDM_PIDR0__PART_3___S 3 +#define DBG_TPDM_PIDR0__PART_2___M 0x00000004 +#define DBG_TPDM_PIDR0__PART_2___S 2 +#define DBG_TPDM_PIDR0__PART_1___M 0x00000002 +#define DBG_TPDM_PIDR0__PART_1___S 1 +#define DBG_TPDM_PIDR0__PART_0___M 0x00000001 +#define DBG_TPDM_PIDR0__PART_0___S 0 +#define DBG_TPDM_PIDR0___M 0x000000FF +#define DBG_TPDM_PIDR0___S 0 + +#define DBG_TPDM_PIDR1 (0x00BB9FE4) +#define DBG_TPDM_PIDR1___RWC QCSR_REG_RO +#define DBG_TPDM_PIDR1___POR 0x0000000E +#define DBG_TPDM_PIDR1__DES_0___POR 0x0 +#define DBG_TPDM_PIDR1__PART_1___POR 0xE +#define DBG_TPDM_PIDR1__DES_0___M 0x000000F0 +#define DBG_TPDM_PIDR1__DES_0___S 4 +#define DBG_TPDM_PIDR1__PART_1___M 0x0000000F +#define DBG_TPDM_PIDR1__PART_1___S 0 +#define DBG_TPDM_PIDR1___M 0x000000FF +#define DBG_TPDM_PIDR1___S 0 + +#define DBG_TPDM_PIDR2 (0x00BB9FE8) +#define DBG_TPDM_PIDR2___RWC QCSR_REG_RO +#define DBG_TPDM_PIDR2___POR 0x00000018 +#define DBG_TPDM_PIDR2__REVISION___POR 0x1 +#define DBG_TPDM_PIDR2__JEDEC___POR 0x1 +#define DBG_TPDM_PIDR2__DES_1___POR 0x0 +#define DBG_TPDM_PIDR2__REVISION___M 0x000000F0 +#define DBG_TPDM_PIDR2__REVISION___S 4 +#define DBG_TPDM_PIDR2__JEDEC___M 0x00000008 +#define DBG_TPDM_PIDR2__JEDEC___S 3 +#define DBG_TPDM_PIDR2__DES_1___M 0x00000007 +#define DBG_TPDM_PIDR2__DES_1___S 0 +#define DBG_TPDM_PIDR2___M 0x000000FF +#define DBG_TPDM_PIDR2___S 0 + +#define DBG_TPDM_PIDR3 (0x00BB9FEC) +#define DBG_TPDM_PIDR3___RWC QCSR_REG_RO +#define DBG_TPDM_PIDR3___POR 0x00000000 +#define DBG_TPDM_PIDR3__REVAND___POR 0x0 +#define DBG_TPDM_PIDR3__CMOD___POR 0x0 +#define DBG_TPDM_PIDR3__REVAND___M 0x000000F0 +#define DBG_TPDM_PIDR3__REVAND___S 4 +#define DBG_TPDM_PIDR3__CMOD___M 0x0000000F +#define DBG_TPDM_PIDR3__CMOD___S 0 +#define DBG_TPDM_PIDR3___M 0x000000FF +#define DBG_TPDM_PIDR3___S 0 + +#define DBG_TPDM_CIDR0 (0x00BB9FF0) +#define DBG_TPDM_CIDR0___RWC QCSR_REG_RO +#define DBG_TPDM_CIDR0___POR 0x0000000D +#define DBG_TPDM_CIDR0__PRMBL_0___POR 0x0D +#define DBG_TPDM_CIDR0__PRMBL_0___M 0x000000FF +#define DBG_TPDM_CIDR0__PRMBL_0___S 0 +#define DBG_TPDM_CIDR0___M 0x000000FF +#define DBG_TPDM_CIDR0___S 0 + +#define DBG_TPDM_CIDR1 (0x00BB9FF4) +#define DBG_TPDM_CIDR1___RWC QCSR_REG_RO +#define DBG_TPDM_CIDR1___POR 0x00000090 +#define DBG_TPDM_CIDR1__CLASS___POR 0x9 +#define DBG_TPDM_CIDR1__PRMBL_1___POR 0x0 +#define DBG_TPDM_CIDR1__CLASS___M 0x000000F0 +#define DBG_TPDM_CIDR1__CLASS___S 4 +#define DBG_TPDM_CIDR1__PRMBL_1___M 0x0000000F +#define DBG_TPDM_CIDR1__PRMBL_1___S 0 +#define DBG_TPDM_CIDR1___M 0x000000FF +#define DBG_TPDM_CIDR1___S 0 + +#define DBG_TPDM_CIDR2 (0x00BB9FF8) +#define DBG_TPDM_CIDR2___RWC QCSR_REG_RO +#define DBG_TPDM_CIDR2___POR 0x00000005 +#define DBG_TPDM_CIDR2__PRMBL_2___POR 0x05 +#define DBG_TPDM_CIDR2__PRMBL_2___M 0x000000FF +#define DBG_TPDM_CIDR2__PRMBL_2___S 0 +#define DBG_TPDM_CIDR2___M 0x000000FF +#define DBG_TPDM_CIDR2___S 0 + +#define DBG_TPDM_CIDR3 (0x00BB9FFC) +#define DBG_TPDM_CIDR3___RWC QCSR_REG_RO +#define DBG_TPDM_CIDR3___POR 0x000000B1 +#define DBG_TPDM_CIDR3__PRMBL_3___POR 0xB1 +#define DBG_TPDM_CIDR3__PRMBL_3___M 0x000000FF +#define DBG_TPDM_CIDR3__PRMBL_3___S 0 +#define DBG_TPDM_CIDR3___M 0x000000FF +#define DBG_TPDM_CIDR3___S 0 + +#define DBG_TPDM_GPRn(n) (0x00BB9000+0x4*(n)) +#define DBG_TPDM_GPRn_nMIN 0 +#define DBG_TPDM_GPRn_nMAX 3 +#define DBG_TPDM_GPRn_ELEM 4 +#define DBG_TPDM_GPRn___RWC QCSR_REG_RW +#define DBG_TPDM_GPRn___POR 0x00000000 +#define DBG_TPDM_GPRn__VAL___POR 0x00000000 +#define DBG_TPDM_GPRn__VAL___M 0xFFFFFFFF +#define DBG_TPDM_GPRn__VAL___S 0 +#define DBG_TPDM_GPRn___M 0xFFFFFFFF +#define DBG_TPDM_GPRn___S 0 +#define DBG_TPDM_GPR0 (0x00BB9000) +#define DBG_TPDM_GPR0___RWC QCSR_REG_RW +#define DBG_TPDM_GPR0__VAL___M 0xFFFFFFFF +#define DBG_TPDM_GPR0__VAL___S 0 +#define DBG_TPDM_GPR1 (0x00BB9004) +#define DBG_TPDM_GPR1___RWC QCSR_REG_RW +#define DBG_TPDM_GPR1__VAL___M 0xFFFFFFFF +#define DBG_TPDM_GPR1__VAL___S 0 +#define DBG_TPDM_GPR2 (0x00BB9008) +#define DBG_TPDM_GPR2___RWC QCSR_REG_RW +#define DBG_TPDM_GPR2__VAL___M 0xFFFFFFFF +#define DBG_TPDM_GPR2__VAL___S 0 +#define DBG_TPDM_GPR3 (0x00BB900C) +#define DBG_TPDM_GPR3___RWC QCSR_REG_RW +#define DBG_TPDM_GPR3__VAL___M 0xFFFFFFFF +#define DBG_TPDM_GPR3__VAL___S 0 + +#define DBG_TPDA_CR (0x00BBA000) +#define DBG_TPDA_CR___RWC QCSR_REG_RW +#define DBG_TPDA_CR___POR 0x00000000 +#define DBG_TPDA_CR__RFU___POR 0x000 +#define DBG_TPDA_CR__AVFREQEN___POR 0x0 +#define DBG_TPDA_CR__CMBCHANMODE___POR 0x0 +#define DBG_TPDA_CR__MID___POR 0x00 +#define DBG_TPDA_CR__ATID___POR 0x00 +#define DBG_TPDA_CR__SRIE___POR 0x0 +#define DBG_TPDA_CR__FLRIE___POR 0x0 +#define DBG_TPDA_CR__FRIE___POR 0x0 +#define DBG_TPDA_CR__FREQTS___POR 0x0 +#define DBG_TPDA_CR__FREQREQ___POR 0x0 +#define DBG_TPDA_CR__FLREQ___POR 0x0 +#define DBG_TPDA_CR__RFU___M 0xFFC00000 +#define DBG_TPDA_CR__RFU___S 22 +#define DBG_TPDA_CR__AVFREQEN___M 0x00200000 +#define DBG_TPDA_CR__AVFREQEN___S 21 +#define DBG_TPDA_CR__CMBCHANMODE___M 0x00100000 +#define DBG_TPDA_CR__CMBCHANMODE___S 20 +#define DBG_TPDA_CR__MID___M 0x000FE000 +#define DBG_TPDA_CR__MID___S 13 +#define DBG_TPDA_CR__ATID___M 0x00001FC0 +#define DBG_TPDA_CR__ATID___S 6 +#define DBG_TPDA_CR__SRIE___M 0x00000020 +#define DBG_TPDA_CR__SRIE___S 5 +#define DBG_TPDA_CR__FLRIE___M 0x00000010 +#define DBG_TPDA_CR__FLRIE___S 4 +#define DBG_TPDA_CR__FRIE___M 0x00000008 +#define DBG_TPDA_CR__FRIE___S 3 +#define DBG_TPDA_CR__FREQTS___M 0x00000004 +#define DBG_TPDA_CR__FREQTS___S 2 +#define DBG_TPDA_CR__FREQREQ___M 0x00000002 +#define DBG_TPDA_CR__FREQREQ___S 1 +#define DBG_TPDA_CR__FLREQ___M 0x00000001 +#define DBG_TPDA_CR__FLREQ___S 0 +#define DBG_TPDA_CR___M 0xFFFFFFFF +#define DBG_TPDA_CR___S 0 + +#define DBG_TPDA_Pn_CR(n) (0x00BBA004+0x4*(n)) +#define DBG_TPDA_Pn_CR_nMIN 0 +#define DBG_TPDA_Pn_CR_nMAX 3 +#define DBG_TPDA_Pn_CR_ELEM 4 +#define DBG_TPDA_Pn_CR___RWC QCSR_REG_RW +#define DBG_TPDA_Pn_CR___POR 0x00000000 +#define DBG_TPDA_Pn_CR__RFU___POR 0x000000 +#define DBG_TPDA_Pn_CR__IMPLDEFESIZE___POR 0x0 +#define DBG_TPDA_Pn_CR__DSBESIZE___POR 0x0 +#define DBG_TPDA_Pn_CR__CMBESIZE___POR 0x0 +#define DBG_TPDA_Pn_CR__TCESIZE___POR 0x0 +#define DBG_TPDA_Pn_CR__BCESIZE___POR 0x0 +#define DBG_TPDA_Pn_CR__HOLD___POR 0x0 +#define DBG_TPDA_Pn_CR__E___POR 0x0 +#define DBG_TPDA_Pn_CR__RFU___M 0xFFFFF800 +#define DBG_TPDA_Pn_CR__RFU___S 11 +#define DBG_TPDA_Pn_CR__IMPLDEFESIZE___M 0x00000600 +#define DBG_TPDA_Pn_CR__IMPLDEFESIZE___S 9 +#define DBG_TPDA_Pn_CR__DSBESIZE___M 0x00000100 +#define DBG_TPDA_Pn_CR__DSBESIZE___S 8 +#define DBG_TPDA_Pn_CR__CMBESIZE___M 0x000000C0 +#define DBG_TPDA_Pn_CR__CMBESIZE___S 6 +#define DBG_TPDA_Pn_CR__TCESIZE___M 0x00000020 +#define DBG_TPDA_Pn_CR__TCESIZE___S 5 +#define DBG_TPDA_Pn_CR__BCESIZE___M 0x00000010 +#define DBG_TPDA_Pn_CR__BCESIZE___S 4 +#define DBG_TPDA_Pn_CR__HOLD___M 0x0000000E +#define DBG_TPDA_Pn_CR__HOLD___S 1 +#define DBG_TPDA_Pn_CR__E___M 0x00000001 +#define DBG_TPDA_Pn_CR__E___S 0 +#define DBG_TPDA_Pn_CR___M 0xFFFFFFFF +#define DBG_TPDA_Pn_CR___S 0 +#define DBG_TPDA_P0_CR (0x00BBA004) +#define DBG_TPDA_P0_CR___RWC QCSR_REG_RW +#define DBG_TPDA_P0_CR__RFU___M 0xFFFFF800 +#define DBG_TPDA_P0_CR__RFU___S 11 +#define DBG_TPDA_P0_CR__IMPLDEFESIZE___M 0x00000600 +#define DBG_TPDA_P0_CR__IMPLDEFESIZE___S 9 +#define DBG_TPDA_P0_CR__DSBESIZE___M 0x00000100 +#define DBG_TPDA_P0_CR__DSBESIZE___S 8 +#define DBG_TPDA_P0_CR__CMBESIZE___M 0x000000C0 +#define DBG_TPDA_P0_CR__CMBESIZE___S 6 +#define DBG_TPDA_P0_CR__TCESIZE___M 0x00000020 +#define DBG_TPDA_P0_CR__TCESIZE___S 5 +#define DBG_TPDA_P0_CR__BCESIZE___M 0x00000010 +#define DBG_TPDA_P0_CR__BCESIZE___S 4 +#define DBG_TPDA_P0_CR__HOLD___M 0x0000000E +#define DBG_TPDA_P0_CR__HOLD___S 1 +#define DBG_TPDA_P0_CR__E___M 0x00000001 +#define DBG_TPDA_P0_CR__E___S 0 +#define DBG_TPDA_P1_CR (0x00BBA008) +#define DBG_TPDA_P1_CR___RWC QCSR_REG_RW +#define DBG_TPDA_P1_CR__RFU___M 0xFFFFF800 +#define DBG_TPDA_P1_CR__RFU___S 11 +#define DBG_TPDA_P1_CR__IMPLDEFESIZE___M 0x00000600 +#define DBG_TPDA_P1_CR__IMPLDEFESIZE___S 9 +#define DBG_TPDA_P1_CR__DSBESIZE___M 0x00000100 +#define DBG_TPDA_P1_CR__DSBESIZE___S 8 +#define DBG_TPDA_P1_CR__CMBESIZE___M 0x000000C0 +#define DBG_TPDA_P1_CR__CMBESIZE___S 6 +#define DBG_TPDA_P1_CR__TCESIZE___M 0x00000020 +#define DBG_TPDA_P1_CR__TCESIZE___S 5 +#define DBG_TPDA_P1_CR__BCESIZE___M 0x00000010 +#define DBG_TPDA_P1_CR__BCESIZE___S 4 +#define DBG_TPDA_P1_CR__HOLD___M 0x0000000E +#define DBG_TPDA_P1_CR__HOLD___S 1 +#define DBG_TPDA_P1_CR__E___M 0x00000001 +#define DBG_TPDA_P1_CR__E___S 0 +#define DBG_TPDA_P2_CR (0x00BBA00C) +#define DBG_TPDA_P2_CR___RWC QCSR_REG_RW +#define DBG_TPDA_P2_CR__RFU___M 0xFFFFF800 +#define DBG_TPDA_P2_CR__RFU___S 11 +#define DBG_TPDA_P2_CR__IMPLDEFESIZE___M 0x00000600 +#define DBG_TPDA_P2_CR__IMPLDEFESIZE___S 9 +#define DBG_TPDA_P2_CR__DSBESIZE___M 0x00000100 +#define DBG_TPDA_P2_CR__DSBESIZE___S 8 +#define DBG_TPDA_P2_CR__CMBESIZE___M 0x000000C0 +#define DBG_TPDA_P2_CR__CMBESIZE___S 6 +#define DBG_TPDA_P2_CR__TCESIZE___M 0x00000020 +#define DBG_TPDA_P2_CR__TCESIZE___S 5 +#define DBG_TPDA_P2_CR__BCESIZE___M 0x00000010 +#define DBG_TPDA_P2_CR__BCESIZE___S 4 +#define DBG_TPDA_P2_CR__HOLD___M 0x0000000E +#define DBG_TPDA_P2_CR__HOLD___S 1 +#define DBG_TPDA_P2_CR__E___M 0x00000001 +#define DBG_TPDA_P2_CR__E___S 0 +#define DBG_TPDA_P3_CR (0x00BBA010) +#define DBG_TPDA_P3_CR___RWC QCSR_REG_RW +#define DBG_TPDA_P3_CR__RFU___M 0xFFFFF800 +#define DBG_TPDA_P3_CR__RFU___S 11 +#define DBG_TPDA_P3_CR__IMPLDEFESIZE___M 0x00000600 +#define DBG_TPDA_P3_CR__IMPLDEFESIZE___S 9 +#define DBG_TPDA_P3_CR__DSBESIZE___M 0x00000100 +#define DBG_TPDA_P3_CR__DSBESIZE___S 8 +#define DBG_TPDA_P3_CR__CMBESIZE___M 0x000000C0 +#define DBG_TPDA_P3_CR__CMBESIZE___S 6 +#define DBG_TPDA_P3_CR__TCESIZE___M 0x00000020 +#define DBG_TPDA_P3_CR__TCESIZE___S 5 +#define DBG_TPDA_P3_CR__BCESIZE___M 0x00000010 +#define DBG_TPDA_P3_CR__BCESIZE___S 4 +#define DBG_TPDA_P3_CR__HOLD___M 0x0000000E +#define DBG_TPDA_P3_CR__HOLD___S 1 +#define DBG_TPDA_P3_CR__E___M 0x00000001 +#define DBG_TPDA_P3_CR__E___S 0 + +#define DBG_TPDA_FPID_CR (0x00BBA084) +#define DBG_TPDA_FPID_CR___RWC QCSR_REG_RW +#define DBG_TPDA_FPID_CR___POR 0x00000000 +#define DBG_TPDA_FPID_CR__CID___POR 0x0000 +#define DBG_TPDA_FPID_CR__MID___POR 0x0000 +#define DBG_TPDA_FPID_CR__CID___M 0xFFFF0000 +#define DBG_TPDA_FPID_CR__CID___S 16 +#define DBG_TPDA_FPID_CR__MID___M 0x0000FFFF +#define DBG_TPDA_FPID_CR__MID___S 0 +#define DBG_TPDA_FPID_CR___M 0xFFFFFFFF +#define DBG_TPDA_FPID_CR___S 0 + +#define DBG_TPDA_FREQREQ_VAL (0x00BBA088) +#define DBG_TPDA_FREQREQ_VAL___RWC QCSR_REG_RW +#define DBG_TPDA_FREQREQ_VAL___POR 0x00000000 +#define DBG_TPDA_FREQREQ_VAL__VAL___POR 0x00000000 +#define DBG_TPDA_FREQREQ_VAL__VAL___M 0xFFFFFFFF +#define DBG_TPDA_FREQREQ_VAL__VAL___S 0 +#define DBG_TPDA_FREQREQ_VAL___M 0xFFFFFFFF +#define DBG_TPDA_FREQREQ_VAL___S 0 + +#define DBG_TPDA_SYNCR (0x00BBA08C) +#define DBG_TPDA_SYNCR___RWC QCSR_REG_RW +#define DBG_TPDA_SYNCR___POR 0x00000000 +#define DBG_TPDA_SYNCR__RFU___POR 0x00000 +#define DBG_TPDA_SYNCR__MODE___POR 0x0 +#define DBG_TPDA_SYNCR__COUNT___POR 0x000 +#define DBG_TPDA_SYNCR__RFU___M 0xFFFFE000 +#define DBG_TPDA_SYNCR__RFU___S 13 +#define DBG_TPDA_SYNCR__MODE___M 0x00001000 +#define DBG_TPDA_SYNCR__MODE___S 12 +#define DBG_TPDA_SYNCR__COUNT___M 0x00000FFF +#define DBG_TPDA_SYNCR__COUNT___S 0 +#define DBG_TPDA_SYNCR___M 0xFFFFFFFF +#define DBG_TPDA_SYNCR___S 0 + +#define DBG_TPDA_FLUSH_CR (0x00BBA090) +#define DBG_TPDA_FLUSH_CR___RWC QCSR_REG_RW +#define DBG_TPDA_FLUSH_CR___POR 0x00000000 +#define DBG_TPDA_FLUSH_CR__REQ___POR 0x00000000 +#define DBG_TPDA_FLUSH_CR__REQ___M 0xFFFFFFFF +#define DBG_TPDA_FLUSH_CR__REQ___S 0 +#define DBG_TPDA_FLUSH_CR___M 0xFFFFFFFF +#define DBG_TPDA_FLUSH_CR___S 0 + +#define DBG_TPDA_FLUSH_SR (0x00BBA094) +#define DBG_TPDA_FLUSH_SR___RWC QCSR_REG_RO +#define DBG_TPDA_FLUSH_SR___POR 0x00000000 +#define DBG_TPDA_FLUSH_SR__FLUSHSTAT___POR 0x00000000 +#define DBG_TPDA_FLUSH_SR__FLUSHSTAT___M 0xFFFFFFFF +#define DBG_TPDA_FLUSH_SR__FLUSHSTAT___S 0 +#define DBG_TPDA_FLUSH_SR___M 0xFFFFFFFF +#define DBG_TPDA_FLUSH_SR___S 0 + +#define DBG_TPDA_FLUSH_ERR (0x00BBA098) +#define DBG_TPDA_FLUSH_ERR___RWC QCSR_REG_RO +#define DBG_TPDA_FLUSH_ERR___POR 0x00000000 +#define DBG_TPDA_FLUSH_ERR__SYNDROME___POR 0x00000000 +#define DBG_TPDA_FLUSH_ERR__SYNDROME___M 0xFFFFFFFF +#define DBG_TPDA_FLUSH_ERR__SYNDROME___S 0 +#define DBG_TPDA_FLUSH_ERR___M 0xFFFFFFFF +#define DBG_TPDA_FLUSH_ERR___S 0 + +#define DBG_TPDA_SPARE (0x00BBAEFC) +#define DBG_TPDA_SPARE___RWC QCSR_REG_RW +#define DBG_TPDA_SPARE___POR 0x00000000 +#define DBG_TPDA_SPARE__RFU___POR 0x00000000 +#define DBG_TPDA_SPARE__LEGACY_TS_MODE_EN___POR 0x0 +#define DBG_TPDA_SPARE__RFU___M 0xFFFFFFFE +#define DBG_TPDA_SPARE__RFU___S 1 +#define DBG_TPDA_SPARE__LEGACY_TS_MODE_EN___M 0x00000001 +#define DBG_TPDA_SPARE__LEGACY_TS_MODE_EN___S 0 +#define DBG_TPDA_SPARE___M 0xFFFFFFFF +#define DBG_TPDA_SPARE___S 0 + +#define DBG_TPDA_ITCTL (0x00BBAF00) +#define DBG_TPDA_ITCTL___RWC QCSR_REG_RO +#define DBG_TPDA_ITCTL___POR 0x00000000 +#define DBG_TPDA_ITCTL__RFU___POR 0x00000000 +#define DBG_TPDA_ITCTL__RFU___M 0xFFFFFFFF +#define DBG_TPDA_ITCTL__RFU___S 0 +#define DBG_TPDA_ITCTL___M 0xFFFFFFFF +#define DBG_TPDA_ITCTL___S 0 + +#define DBG_TPDA_CLAIMSET (0x00BBAFA0) +#define DBG_TPDA_CLAIMSET___RWC QCSR_REG_RO +#define DBG_TPDA_CLAIMSET___POR 0x00000000 +#define DBG_TPDA_CLAIMSET__RFU___POR 0x00000000 +#define DBG_TPDA_CLAIMSET__RFU___M 0xFFFFFFFF +#define DBG_TPDA_CLAIMSET__RFU___S 0 +#define DBG_TPDA_CLAIMSET___M 0xFFFFFFFF +#define DBG_TPDA_CLAIMSET___S 0 + +#define DBG_TPDA_CLAIMCLR (0x00BBAFA4) +#define DBG_TPDA_CLAIMCLR___RWC QCSR_REG_RO +#define DBG_TPDA_CLAIMCLR___POR 0x00000000 +#define DBG_TPDA_CLAIMCLR__RFU___POR 0x00000000 +#define DBG_TPDA_CLAIMCLR__RFU___M 0xFFFFFFFF +#define DBG_TPDA_CLAIMCLR__RFU___S 0 +#define DBG_TPDA_CLAIMCLR___M 0xFFFFFFFF +#define DBG_TPDA_CLAIMCLR___S 0 + +#define DBG_TPDA_DEVAFF0 (0x00BBAFA8) +#define DBG_TPDA_DEVAFF0___RWC QCSR_REG_RO +#define DBG_TPDA_DEVAFF0___POR 0x00000000 +#define DBG_TPDA_DEVAFF0__AFFINITY___POR 0x00000000 +#define DBG_TPDA_DEVAFF0__AFFINITY___M 0xFFFFFFFF +#define DBG_TPDA_DEVAFF0__AFFINITY___S 0 +#define DBG_TPDA_DEVAFF0___M 0xFFFFFFFF +#define DBG_TPDA_DEVAFF0___S 0 + +#define DBG_TPDA_DEVAFF1 (0x00BBAFAC) +#define DBG_TPDA_DEVAFF1___RWC QCSR_REG_RO +#define DBG_TPDA_DEVAFF1___POR 0x00000000 +#define DBG_TPDA_DEVAFF1__AFFINITY___POR 0x00000000 +#define DBG_TPDA_DEVAFF1__AFFINITY___M 0xFFFFFFFF +#define DBG_TPDA_DEVAFF1__AFFINITY___S 0 +#define DBG_TPDA_DEVAFF1___M 0xFFFFFFFF +#define DBG_TPDA_DEVAFF1___S 0 + +#define DBG_TPDA_LOCKACCESS (0x00BBAFB0) +#define DBG_TPDA_LOCKACCESS___RWC QCSR_REG_WO +#define DBG_TPDA_LOCKACCESS__LOCKACCESS___M 0xFFFFFFFF +#define DBG_TPDA_LOCKACCESS__LOCKACCESS___S 0 +#define DBG_TPDA_LOCKACCESS___M 0xFFFFFFFF +#define DBG_TPDA_LOCKACCESS___S 0 + +#define DBG_TPDA_LOCKSTATUS (0x00BBAFB4) +#define DBG_TPDA_LOCKSTATUS___RWC QCSR_REG_RO +#define DBG_TPDA_LOCKSTATUS___POR 0x00000003 +#define DBG_TPDA_LOCKSTATUS__RFU___POR 0x00000000 +#define DBG_TPDA_LOCKSTATUS__FIELD_8_BIT_LOCK___POR 0x0 +#define DBG_TPDA_LOCKSTATUS__ACCESS___POR 0x1 +#define DBG_TPDA_LOCKSTATUS__LOCK_CONTROL___POR 0x1 +#define DBG_TPDA_LOCKSTATUS__RFU___M 0xFFFFFFF8 +#define DBG_TPDA_LOCKSTATUS__RFU___S 3 +#define DBG_TPDA_LOCKSTATUS__FIELD_8_BIT_LOCK___M 0x00000004 +#define DBG_TPDA_LOCKSTATUS__FIELD_8_BIT_LOCK___S 2 +#define DBG_TPDA_LOCKSTATUS__ACCESS___M 0x00000002 +#define DBG_TPDA_LOCKSTATUS__ACCESS___S 1 +#define DBG_TPDA_LOCKSTATUS__ACCESS__LOW 0x0 +#define DBG_TPDA_LOCKSTATUS__ACCESS__HIGH 0x1 +#define DBG_TPDA_LOCKSTATUS__LOCK_CONTROL___M 0x00000001 +#define DBG_TPDA_LOCKSTATUS__LOCK_CONTROL___S 0 +#define DBG_TPDA_LOCKSTATUS___M 0xFFFFFFFF +#define DBG_TPDA_LOCKSTATUS___S 0 + +#define DBG_TPDA_AUTHSTATUS (0x00BBAFB8) +#define DBG_TPDA_AUTHSTATUS___RWC QCSR_REG_RO +#define DBG_TPDA_AUTHSTATUS___POR 0x00000000 +#define DBG_TPDA_AUTHSTATUS__RFU___POR 0x00000000 +#define DBG_TPDA_AUTHSTATUS__RFU___M 0xFFFFFFFF +#define DBG_TPDA_AUTHSTATUS__RFU___S 0 +#define DBG_TPDA_AUTHSTATUS___M 0xFFFFFFFF +#define DBG_TPDA_AUTHSTATUS___S 0 + +#define DBG_TPDA_DEVARCH (0x00BBAFBC) +#define DBG_TPDA_DEVARCH___RWC QCSR_REG_RO +#define DBG_TPDA_DEVARCH__ARCHITECT___M 0xFFE00000 +#define DBG_TPDA_DEVARCH__ARCHITECT___S 21 +#define DBG_TPDA_DEVARCH__PRESENT___M 0x00100000 +#define DBG_TPDA_DEVARCH__PRESENT___S 20 +#define DBG_TPDA_DEVARCH__REVISION___M 0x000F0000 +#define DBG_TPDA_DEVARCH__REVISION___S 16 +#define DBG_TPDA_DEVARCH__ARCHID___M 0x0000FFFF +#define DBG_TPDA_DEVARCH__ARCHID___S 0 +#define DBG_TPDA_DEVARCH___M 0xFFFFFFFF +#define DBG_TPDA_DEVARCH___S 0 + +#define DBG_TPDA_DEVID2 (0x00BBAFC0) +#define DBG_TPDA_DEVID2___RWC QCSR_REG_RO +#define DBG_TPDA_DEVID2___POR 0x00000000 +#define DBG_TPDA_DEVID2__DEVID2___POR 0x00000000 +#define DBG_TPDA_DEVID2__DEVID2___M 0xFFFFFFFF +#define DBG_TPDA_DEVID2__DEVID2___S 0 +#define DBG_TPDA_DEVID2___M 0xFFFFFFFF +#define DBG_TPDA_DEVID2___S 0 + +#define DBG_TPDA_DEVID1 (0x00BBAFC4) +#define DBG_TPDA_DEVID1___RWC QCSR_REG_RO +#define DBG_TPDA_DEVID1___POR 0x00000000 +#define DBG_TPDA_DEVID1__DEVID1___POR 0x00000000 +#define DBG_TPDA_DEVID1__DEVID1___M 0xFFFFFFFF +#define DBG_TPDA_DEVID1__DEVID1___S 0 +#define DBG_TPDA_DEVID1___M 0xFFFFFFFF +#define DBG_TPDA_DEVID1___S 0 + +#define DBG_TPDA_DEVID (0x00BBAFC8) +#define DBG_TPDA_DEVID___RWC QCSR_REG_RO +#define DBG_TPDA_DEVID___POR 0x00000000 +#define DBG_TPDA_DEVID__DEVID___POR 0x00000000 +#define DBG_TPDA_DEVID__DEVID___M 0xFFFFFFFF +#define DBG_TPDA_DEVID__DEVID___S 0 +#define DBG_TPDA_DEVID___M 0xFFFFFFFF +#define DBG_TPDA_DEVID___S 0 + +#define DBG_TPDA_DEVTYPE (0x00BBAFCC) +#define DBG_TPDA_DEVTYPE___RWC QCSR_REG_RO +#define DBG_TPDA_DEVTYPE___POR 0x00000003 +#define DBG_TPDA_DEVTYPE__RFU___POR 0x000000 +#define DBG_TPDA_DEVTYPE__SUBTYPE___POR 0x0 +#define DBG_TPDA_DEVTYPE__MAJTYPE___POR 0x3 +#define DBG_TPDA_DEVTYPE__RFU___M 0xFFFFFF00 +#define DBG_TPDA_DEVTYPE__RFU___S 8 +#define DBG_TPDA_DEVTYPE__SUBTYPE___M 0x000000F0 +#define DBG_TPDA_DEVTYPE__SUBTYPE___S 4 +#define DBG_TPDA_DEVTYPE__MAJTYPE___M 0x0000000F +#define DBG_TPDA_DEVTYPE__MAJTYPE___S 0 +#define DBG_TPDA_DEVTYPE___M 0xFFFFFFFF +#define DBG_TPDA_DEVTYPE___S 0 + +#define DBG_TPDA_PERIPHID4 (0x00BBAFD0) +#define DBG_TPDA_PERIPHID4___RWC QCSR_REG_RO +#define DBG_TPDA_PERIPHID4__RFU___M 0xFFFFFF00 +#define DBG_TPDA_PERIPHID4__RFU___S 8 +#define DBG_TPDA_PERIPHID4__FIELD_4KB_COUNT___M 0x000000F0 +#define DBG_TPDA_PERIPHID4__FIELD_4KB_COUNT___S 4 +#define DBG_TPDA_PERIPHID4__JEP106_CONTINUATION___M 0x0000000F +#define DBG_TPDA_PERIPHID4__JEP106_CONTINUATION___S 0 +#define DBG_TPDA_PERIPHID4___M 0xFFFFFFFF +#define DBG_TPDA_PERIPHID4___S 0 + +#define DBG_TPDA_PERIPHID5 (0x00BBAFD4) +#define DBG_TPDA_PERIPHID5___RWC QCSR_REG_RO +#define DBG_TPDA_PERIPHID5___POR 0x00000000 +#define DBG_TPDA_PERIPHID5__RFU___POR 0x00000000 +#define DBG_TPDA_PERIPHID5__RFU___M 0xFFFFFFFF +#define DBG_TPDA_PERIPHID5__RFU___S 0 +#define DBG_TPDA_PERIPHID5___M 0xFFFFFFFF +#define DBG_TPDA_PERIPHID5___S 0 + +#define DBG_TPDA_PERIPHID6 (0x00BBAFD8) +#define DBG_TPDA_PERIPHID6___RWC QCSR_REG_RO +#define DBG_TPDA_PERIPHID6___POR 0x00000000 +#define DBG_TPDA_PERIPHID6__RFU___POR 0x00000000 +#define DBG_TPDA_PERIPHID6__RFU___M 0xFFFFFFFF +#define DBG_TPDA_PERIPHID6__RFU___S 0 +#define DBG_TPDA_PERIPHID6___M 0xFFFFFFFF +#define DBG_TPDA_PERIPHID6___S 0 + +#define DBG_TPDA_PERIPHID7 (0x00BBAFDC) +#define DBG_TPDA_PERIPHID7___RWC QCSR_REG_RO +#define DBG_TPDA_PERIPHID7___POR 0x00000000 +#define DBG_TPDA_PERIPHID7__RFU___POR 0x00000000 +#define DBG_TPDA_PERIPHID7__RFU___M 0xFFFFFFFF +#define DBG_TPDA_PERIPHID7__RFU___S 0 +#define DBG_TPDA_PERIPHID7___M 0xFFFFFFFF +#define DBG_TPDA_PERIPHID7___S 0 + +#define DBG_TPDA_PERIPHID0 (0x00BBAFE0) +#define DBG_TPDA_PERIPHID0___RWC QCSR_REG_RO +#define DBG_TPDA_PERIPHID0___POR 0x00000003 +#define DBG_TPDA_PERIPHID0__RFU___POR 0x000000 +#define DBG_TPDA_PERIPHID0__PARTNUM___POR 0x03 +#define DBG_TPDA_PERIPHID0__RFU___M 0xFFFFFF00 +#define DBG_TPDA_PERIPHID0__RFU___S 8 +#define DBG_TPDA_PERIPHID0__PARTNUM___M 0x000000FF +#define DBG_TPDA_PERIPHID0__PARTNUM___S 0 +#define DBG_TPDA_PERIPHID0___M 0xFFFFFFFF +#define DBG_TPDA_PERIPHID0___S 0 + +#define DBG_TPDA_PERIPHID1 (0x00BBAFE4) +#define DBG_TPDA_PERIPHID1___RWC QCSR_REG_RO +#define DBG_TPDA_PERIPHID1__RFU___M 0xFFFFFF00 +#define DBG_TPDA_PERIPHID1__RFU___S 8 +#define DBG_TPDA_PERIPHID1__JEP106_IDENTITY_3_0___M 0x000000F0 +#define DBG_TPDA_PERIPHID1__JEP106_IDENTITY_3_0___S 4 +#define DBG_TPDA_PERIPHID1__PARTNUM___M 0x0000000F +#define DBG_TPDA_PERIPHID1__PARTNUM___S 0 +#define DBG_TPDA_PERIPHID1___M 0xFFFFFFFF +#define DBG_TPDA_PERIPHID1___S 0 + +#define DBG_TPDA_PERIPHID2 (0x00BBAFE8) +#define DBG_TPDA_PERIPHID2___RWC QCSR_REG_RO +#define DBG_TPDA_PERIPHID2__RFU___M 0xFFFFFF00 +#define DBG_TPDA_PERIPHID2__RFU___S 8 +#define DBG_TPDA_PERIPHID2__MAJREV___M 0x000000F0 +#define DBG_TPDA_PERIPHID2__MAJREV___S 4 +#define DBG_TPDA_PERIPHID2__JEDEC___M 0x00000008 +#define DBG_TPDA_PERIPHID2__JEDEC___S 3 +#define DBG_TPDA_PERIPHID2__JEP106_IDENTITY_6_4___M 0x00000007 +#define DBG_TPDA_PERIPHID2__JEP106_IDENTITY_6_4___S 0 +#define DBG_TPDA_PERIPHID2___M 0xFFFFFFFF +#define DBG_TPDA_PERIPHID2___S 0 + +#define DBG_TPDA_PERIPHID3 (0x00BBAFEC) +#define DBG_TPDA_PERIPHID3___RWC QCSR_REG_RO +#define DBG_TPDA_PERIPHID3___POR 0x00000000 +#define DBG_TPDA_PERIPHID3__RFU___POR 0x000000 +#define DBG_TPDA_PERIPHID3__REV_AND___POR 0x0 +#define DBG_TPDA_PERIPHID3__CUSTOMER_MODIFIED___POR 0x0 +#define DBG_TPDA_PERIPHID3__RFU___M 0xFFFFFF00 +#define DBG_TPDA_PERIPHID3__RFU___S 8 +#define DBG_TPDA_PERIPHID3__REV_AND___M 0x000000F0 +#define DBG_TPDA_PERIPHID3__REV_AND___S 4 +#define DBG_TPDA_PERIPHID3__CUSTOMER_MODIFIED___M 0x0000000F +#define DBG_TPDA_PERIPHID3__CUSTOMER_MODIFIED___S 0 +#define DBG_TPDA_PERIPHID3___M 0xFFFFFFFF +#define DBG_TPDA_PERIPHID3___S 0 + +#define DBG_TPDA_COMPID0 (0x00BBAFF0) +#define DBG_TPDA_COMPID0___RWC QCSR_REG_RO +#define DBG_TPDA_COMPID0___POR 0x0000000D +#define DBG_TPDA_COMPID0__RFU___POR 0x000000 +#define DBG_TPDA_COMPID0__PREAMBLE_7_0___POR 0x0D +#define DBG_TPDA_COMPID0__RFU___M 0xFFFFFF00 +#define DBG_TPDA_COMPID0__RFU___S 8 +#define DBG_TPDA_COMPID0__PREAMBLE_7_0___M 0x000000FF +#define DBG_TPDA_COMPID0__PREAMBLE_7_0___S 0 +#define DBG_TPDA_COMPID0___M 0xFFFFFFFF +#define DBG_TPDA_COMPID0___S 0 + +#define DBG_TPDA_COMPID1 (0x00BBAFF4) +#define DBG_TPDA_COMPID1___RWC QCSR_REG_RO +#define DBG_TPDA_COMPID1___POR 0x00000090 +#define DBG_TPDA_COMPID1__RFU___POR 0x000000 +#define DBG_TPDA_COMPID1__PREAMBLE_15_12___POR 0x9 +#define DBG_TPDA_COMPID1__PREAMBLE_11_8___POR 0x0 +#define DBG_TPDA_COMPID1__RFU___M 0xFFFFFF00 +#define DBG_TPDA_COMPID1__RFU___S 8 +#define DBG_TPDA_COMPID1__PREAMBLE_15_12___M 0x000000F0 +#define DBG_TPDA_COMPID1__PREAMBLE_15_12___S 4 +#define DBG_TPDA_COMPID1__PREAMBLE_11_8___M 0x0000000F +#define DBG_TPDA_COMPID1__PREAMBLE_11_8___S 0 +#define DBG_TPDA_COMPID1___M 0xFFFFFFFF +#define DBG_TPDA_COMPID1___S 0 + +#define DBG_TPDA_COMPID2 (0x00BBAFF8) +#define DBG_TPDA_COMPID2___RWC QCSR_REG_RO +#define DBG_TPDA_COMPID2___POR 0x00000005 +#define DBG_TPDA_COMPID2__RFU___POR 0x000000 +#define DBG_TPDA_COMPID2__PREAMBLE_23_16___POR 0x05 +#define DBG_TPDA_COMPID2__RFU___M 0xFFFFFF00 +#define DBG_TPDA_COMPID2__RFU___S 8 +#define DBG_TPDA_COMPID2__PREAMBLE_23_16___M 0x000000FF +#define DBG_TPDA_COMPID2__PREAMBLE_23_16___S 0 +#define DBG_TPDA_COMPID2___M 0xFFFFFFFF +#define DBG_TPDA_COMPID2___S 0 + +#define DBG_TPDA_COMPID3 (0x00BBAFFC) +#define DBG_TPDA_COMPID3___RWC QCSR_REG_RO +#define DBG_TPDA_COMPID3___POR 0x000000B1 +#define DBG_TPDA_COMPID3__RFU___POR 0x000000 +#define DBG_TPDA_COMPID3__PREAMBLE_31_24___POR 0xB1 +#define DBG_TPDA_COMPID3__RFU___M 0xFFFFFF00 +#define DBG_TPDA_COMPID3__RFU___S 8 +#define DBG_TPDA_COMPID3__PREAMBLE_31_24___M 0x000000FF +#define DBG_TPDA_COMPID3__PREAMBLE_31_24___S 0 +#define DBG_TPDA_COMPID3___M 0xFFFFFFFF +#define DBG_TPDA_COMPID3___S 0 + +#define DBG_CTRL_REG (0x00BBB000) +#define DBG_CTRL_REG___RWC QCSR_REG_RW +#define DBG_CTRL_REG___POR 0x00000300 +#define DBG_CTRL_REG__HT___POR 0x3 +#define DBG_CTRL_REG__ENS7___POR 0x0 +#define DBG_CTRL_REG__ENS6___POR 0x0 +#define DBG_CTRL_REG__ENS5___POR 0x0 +#define DBG_CTRL_REG__ENS4___POR 0x0 +#define DBG_CTRL_REG__ENS3___POR 0x0 +#define DBG_CTRL_REG__ENS2___POR 0x0 +#define DBG_CTRL_REG__ENS1___POR 0x0 +#define DBG_CTRL_REG__ENS0___POR 0x0 +#define DBG_CTRL_REG__HT___M 0x00000F00 +#define DBG_CTRL_REG__HT___S 8 +#define DBG_CTRL_REG__HT__HT_0X0 0x0 +#define DBG_CTRL_REG__HT__HT_0X1 0x1 +#define DBG_CTRL_REG__HT__HT_0X2 0x2 +#define DBG_CTRL_REG__HT__HT_0X3 0x3 +#define DBG_CTRL_REG__HT__HT_0X4 0x4 +#define DBG_CTRL_REG__HT__HT_0X5 0x5 +#define DBG_CTRL_REG__HT__HT_0X6 0x6 +#define DBG_CTRL_REG__HT__HT_0X7 0x7 +#define DBG_CTRL_REG__HT__HT_0X8 0x8 +#define DBG_CTRL_REG__HT__HT_0X9 0x9 +#define DBG_CTRL_REG__HT__HT_0XA 0xA +#define DBG_CTRL_REG__HT__HT_0XB 0xB +#define DBG_CTRL_REG__HT__HT_0XC 0xC +#define DBG_CTRL_REG__HT__HT_0XD 0xD +#define DBG_CTRL_REG__HT__HT_0XE 0xE +#define DBG_CTRL_REG__ENS7___M 0x00000080 +#define DBG_CTRL_REG__ENS7___S 7 +#define DBG_CTRL_REG__ENS7__ENS7_0 0x0 +#define DBG_CTRL_REG__ENS7__ENS7_1 0x1 +#define DBG_CTRL_REG__ENS6___M 0x00000040 +#define DBG_CTRL_REG__ENS6___S 6 +#define DBG_CTRL_REG__ENS6__ENS6_0 0x0 +#define DBG_CTRL_REG__ENS6__ENS6_1 0x1 +#define DBG_CTRL_REG__ENS5___M 0x00000020 +#define DBG_CTRL_REG__ENS5___S 5 +#define DBG_CTRL_REG__ENS5__ENS5_0 0x0 +#define DBG_CTRL_REG__ENS5__ENS5_1 0x1 +#define DBG_CTRL_REG__ENS4___M 0x00000010 +#define DBG_CTRL_REG__ENS4___S 4 +#define DBG_CTRL_REG__ENS4__ENS4_0 0x0 +#define DBG_CTRL_REG__ENS4__ENS4_1 0x1 +#define DBG_CTRL_REG__ENS3___M 0x00000008 +#define DBG_CTRL_REG__ENS3___S 3 +#define DBG_CTRL_REG__ENS3__ENS3_0 0x0 +#define DBG_CTRL_REG__ENS3__ENS3_1 0x1 +#define DBG_CTRL_REG__ENS2___M 0x00000004 +#define DBG_CTRL_REG__ENS2___S 2 +#define DBG_CTRL_REG__ENS2__ENS2_0 0x0 +#define DBG_CTRL_REG__ENS2__ENS2_1 0x1 +#define DBG_CTRL_REG__ENS1___M 0x00000002 +#define DBG_CTRL_REG__ENS1___S 1 +#define DBG_CTRL_REG__ENS1__ENS1_0 0x0 +#define DBG_CTRL_REG__ENS1__ENS1_1 0x1 +#define DBG_CTRL_REG__ENS0___M 0x00000001 +#define DBG_CTRL_REG__ENS0___S 0 +#define DBG_CTRL_REG__ENS0__ENS0_0 0x0 +#define DBG_CTRL_REG__ENS0__ENS0_1 0x1 +#define DBG_CTRL_REG___M 0x00000FFF +#define DBG_CTRL_REG___S 0 + +#define DBG_PRIORITY_CTRL_REG (0x00BBB004) +#define DBG_PRIORITY_CTRL_REG___RWC QCSR_REG_RW +#define DBG_PRIORITY_CTRL_REG___POR 0x00000000 +#define DBG_PRIORITY_CTRL_REG__PRIPORT7___POR 0x0 +#define DBG_PRIORITY_CTRL_REG__PRIPORT6___POR 0x0 +#define DBG_PRIORITY_CTRL_REG__PRIPORT5___POR 0x0 +#define DBG_PRIORITY_CTRL_REG__PRIPORT4___POR 0x0 +#define DBG_PRIORITY_CTRL_REG__PRIPORT3___POR 0x0 +#define DBG_PRIORITY_CTRL_REG__PRIPORT2___POR 0x0 +#define DBG_PRIORITY_CTRL_REG__PRIPORT1___POR 0x0 +#define DBG_PRIORITY_CTRL_REG__PRIPORT0___POR 0x0 +#define DBG_PRIORITY_CTRL_REG__PRIPORT7___M 0x00E00000 +#define DBG_PRIORITY_CTRL_REG__PRIPORT7___S 21 +#define DBG_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_0 0x0 +#define DBG_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_1 0x1 +#define DBG_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_2 0x2 +#define DBG_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_3 0x3 +#define DBG_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_4 0x4 +#define DBG_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_5 0x5 +#define DBG_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_6 0x6 +#define DBG_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_7 0x7 +#define DBG_PRIORITY_CTRL_REG__PRIPORT6___M 0x001C0000 +#define DBG_PRIORITY_CTRL_REG__PRIPORT6___S 18 +#define DBG_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_0 0x0 +#define DBG_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_1 0x1 +#define DBG_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_2 0x2 +#define DBG_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_3 0x3 +#define DBG_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_4 0x4 +#define DBG_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_5 0x5 +#define DBG_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_6 0x6 +#define DBG_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_7 0x7 +#define DBG_PRIORITY_CTRL_REG__PRIPORT5___M 0x00038000 +#define DBG_PRIORITY_CTRL_REG__PRIPORT5___S 15 +#define DBG_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_0 0x0 +#define DBG_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_1 0x1 +#define DBG_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_2 0x2 +#define DBG_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_3 0x3 +#define DBG_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_4 0x4 +#define DBG_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_5 0x5 +#define DBG_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_6 0x6 +#define DBG_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_7 0x7 +#define DBG_PRIORITY_CTRL_REG__PRIPORT4___M 0x00007000 +#define DBG_PRIORITY_CTRL_REG__PRIPORT4___S 12 +#define DBG_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_0 0x0 +#define DBG_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_1 0x1 +#define DBG_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_2 0x2 +#define DBG_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_3 0x3 +#define DBG_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_4 0x4 +#define DBG_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_5 0x5 +#define DBG_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_6 0x6 +#define DBG_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_7 0x7 +#define DBG_PRIORITY_CTRL_REG__PRIPORT3___M 0x00000E00 +#define DBG_PRIORITY_CTRL_REG__PRIPORT3___S 9 +#define DBG_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_0 0x0 +#define DBG_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_1 0x1 +#define DBG_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_2 0x2 +#define DBG_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_3 0x3 +#define DBG_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_4 0x4 +#define DBG_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_5 0x5 +#define DBG_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_6 0x6 +#define DBG_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_7 0x7 +#define DBG_PRIORITY_CTRL_REG__PRIPORT2___M 0x000001C0 +#define DBG_PRIORITY_CTRL_REG__PRIPORT2___S 6 +#define DBG_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_0 0x0 +#define DBG_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_1 0x1 +#define DBG_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_2 0x2 +#define DBG_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_3 0x3 +#define DBG_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_4 0x4 +#define DBG_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_5 0x5 +#define DBG_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_6 0x6 +#define DBG_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_7 0x7 +#define DBG_PRIORITY_CTRL_REG__PRIPORT1___M 0x00000038 +#define DBG_PRIORITY_CTRL_REG__PRIPORT1___S 3 +#define DBG_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_0 0x0 +#define DBG_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_1 0x1 +#define DBG_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_2 0x2 +#define DBG_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_3 0x3 +#define DBG_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_4 0x4 +#define DBG_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_5 0x5 +#define DBG_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_6 0x6 +#define DBG_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_7 0x7 +#define DBG_PRIORITY_CTRL_REG__PRIPORT0___M 0x00000007 +#define DBG_PRIORITY_CTRL_REG__PRIPORT0___S 0 +#define DBG_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_0 0x0 +#define DBG_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_1 0x1 +#define DBG_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_2 0x2 +#define DBG_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_3 0x3 +#define DBG_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_4 0x4 +#define DBG_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_5 0x5 +#define DBG_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_6 0x6 +#define DBG_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_7 0x7 +#define DBG_PRIORITY_CTRL_REG___M 0x00FFFFFF +#define DBG_PRIORITY_CTRL_REG___S 0 + +#define DBG_ITATBDATA0 (0x00BBBEEC) +#define DBG_ITATBDATA0___RWC QCSR_REG_RW +#define DBG_ITATBDATA0___POR 0x00000000 +#define DBG_ITATBDATA0__ATDATA127___POR 0x0 +#define DBG_ITATBDATA0__ATDATA119___POR 0x0 +#define DBG_ITATBDATA0__ATDATA111___POR 0x0 +#define DBG_ITATBDATA0__ATDATA103___POR 0x0 +#define DBG_ITATBDATA0__ATDATA95___POR 0x0 +#define DBG_ITATBDATA0__ATDATA87___POR 0x0 +#define DBG_ITATBDATA0__ATDATA79___POR 0x0 +#define DBG_ITATBDATA0__ATDATA71___POR 0x0 +#define DBG_ITATBDATA0__ATDATA63___POR 0x0 +#define DBG_ITATBDATA0__ATDATA55___POR 0x0 +#define DBG_ITATBDATA0__ATDATA47___POR 0x0 +#define DBG_ITATBDATA0__ATDATA39___POR 0x0 +#define DBG_ITATBDATA0__ATDATA31___POR 0x0 +#define DBG_ITATBDATA0__ATDATAM23___POR 0x0 +#define DBG_ITATBDATA0__ATDATA15___POR 0x0 +#define DBG_ITATBDATA0__ATDATA7___POR 0x0 +#define DBG_ITATBDATA0__ATDATA0___POR 0x0 +#define DBG_ITATBDATA0__ATDATA127___M 0x00010000 +#define DBG_ITATBDATA0__ATDATA127___S 16 +#define DBG_ITATBDATA0__ATDATA127__ATDATA127_0 0x0 +#define DBG_ITATBDATA0__ATDATA127__ATDATA127_1 0x1 +#define DBG_ITATBDATA0__ATDATA119___M 0x00008000 +#define DBG_ITATBDATA0__ATDATA119___S 15 +#define DBG_ITATBDATA0__ATDATA119__ATDATA119_0 0x0 +#define DBG_ITATBDATA0__ATDATA119__ATDATA119_1 0x1 +#define DBG_ITATBDATA0__ATDATA111___M 0x00004000 +#define DBG_ITATBDATA0__ATDATA111___S 14 +#define DBG_ITATBDATA0__ATDATA111__ATDATA111_0 0x0 +#define DBG_ITATBDATA0__ATDATA111__ATDATA111_1 0x1 +#define DBG_ITATBDATA0__ATDATA103___M 0x00002000 +#define DBG_ITATBDATA0__ATDATA103___S 13 +#define DBG_ITATBDATA0__ATDATA103__ATDATA103_0 0x0 +#define DBG_ITATBDATA0__ATDATA103__ATDATA103_1 0x1 +#define DBG_ITATBDATA0__ATDATA95___M 0x00001000 +#define DBG_ITATBDATA0__ATDATA95___S 12 +#define DBG_ITATBDATA0__ATDATA95__ATDATA95_0 0x0 +#define DBG_ITATBDATA0__ATDATA95__ATDATA95_1 0x1 +#define DBG_ITATBDATA0__ATDATA87___M 0x00000800 +#define DBG_ITATBDATA0__ATDATA87___S 11 +#define DBG_ITATBDATA0__ATDATA87__ATDATA87_0 0x0 +#define DBG_ITATBDATA0__ATDATA87__ATDATA87_1 0x1 +#define DBG_ITATBDATA0__ATDATA79___M 0x00000400 +#define DBG_ITATBDATA0__ATDATA79___S 10 +#define DBG_ITATBDATA0__ATDATA79__ATDATA79_0 0x0 +#define DBG_ITATBDATA0__ATDATA79__ATDATA79_1 0x1 +#define DBG_ITATBDATA0__ATDATA71___M 0x00000200 +#define DBG_ITATBDATA0__ATDATA71___S 9 +#define DBG_ITATBDATA0__ATDATA71__ATDATA71_0 0x0 +#define DBG_ITATBDATA0__ATDATA71__ATDATA71_1 0x1 +#define DBG_ITATBDATA0__ATDATA63___M 0x00000100 +#define DBG_ITATBDATA0__ATDATA63___S 8 +#define DBG_ITATBDATA0__ATDATA63__ATDATA63_0 0x0 +#define DBG_ITATBDATA0__ATDATA63__ATDATA63_1 0x1 +#define DBG_ITATBDATA0__ATDATA55___M 0x00000080 +#define DBG_ITATBDATA0__ATDATA55___S 7 +#define DBG_ITATBDATA0__ATDATA55__ATDATA55_0 0x0 +#define DBG_ITATBDATA0__ATDATA55__ATDATA55_1 0x1 +#define DBG_ITATBDATA0__ATDATA47___M 0x00000040 +#define DBG_ITATBDATA0__ATDATA47___S 6 +#define DBG_ITATBDATA0__ATDATA47__ATDATA47_0 0x0 +#define DBG_ITATBDATA0__ATDATA47__ATDATA47_1 0x1 +#define DBG_ITATBDATA0__ATDATA39___M 0x00000020 +#define DBG_ITATBDATA0__ATDATA39___S 5 +#define DBG_ITATBDATA0__ATDATA39__ATDATA39_0 0x0 +#define DBG_ITATBDATA0__ATDATA39__ATDATA39_1 0x1 +#define DBG_ITATBDATA0__ATDATA31___M 0x00000010 +#define DBG_ITATBDATA0__ATDATA31___S 4 +#define DBG_ITATBDATA0__ATDATA31__ATDATA31_0 0x0 +#define DBG_ITATBDATA0__ATDATA31__ATDATA31_1 0x1 +#define DBG_ITATBDATA0__ATDATAM23___M 0x00000008 +#define DBG_ITATBDATA0__ATDATAM23___S 3 +#define DBG_ITATBDATA0__ATDATAM23__ATDATAM23_0 0x0 +#define DBG_ITATBDATA0__ATDATAM23__ATDATAM23_1 0x1 +#define DBG_ITATBDATA0__ATDATA15___M 0x00000004 +#define DBG_ITATBDATA0__ATDATA15___S 2 +#define DBG_ITATBDATA0__ATDATA15__ATDATA15_0 0x0 +#define DBG_ITATBDATA0__ATDATA15__ATDATA15_1 0x1 +#define DBG_ITATBDATA0__ATDATA7___M 0x00000002 +#define DBG_ITATBDATA0__ATDATA7___S 1 +#define DBG_ITATBDATA0__ATDATA7__ATDATA7_0 0x0 +#define DBG_ITATBDATA0__ATDATA7__ATDATA7_1 0x1 +#define DBG_ITATBDATA0__ATDATA0___M 0x00000001 +#define DBG_ITATBDATA0__ATDATA0___S 0 +#define DBG_ITATBDATA0__ATDATA0__ATDATA0_0 0x0 +#define DBG_ITATBDATA0__ATDATA0__ATDATA0_1 0x1 +#define DBG_ITATBDATA0___M 0x0001FFFF +#define DBG_ITATBDATA0___S 0 + +#define DBG_ITATBCTR2 (0x00BBBEF0) +#define DBG_ITATBCTR2___RWC QCSR_REG_RW +#define DBG_ITATBCTR2___POR 0x00000000 +#define DBG_ITATBCTR2__AFVALID___POR 0x0 +#define DBG_ITATBCTR2__ATREADY___POR 0x0 +#define DBG_ITATBCTR2__AFVALID___M 0x00000002 +#define DBG_ITATBCTR2__AFVALID___S 1 +#define DBG_ITATBCTR2__AFVALID__AFVALID_0 0x0 +#define DBG_ITATBCTR2__AFVALID__AFVALID_1 0x1 +#define DBG_ITATBCTR2__ATREADY___M 0x00000001 +#define DBG_ITATBCTR2__ATREADY___S 0 +#define DBG_ITATBCTR2__ATREADY__ATREADY_0 0x0 +#define DBG_ITATBCTR2__ATREADY__ATREADY_1 0x1 +#define DBG_ITATBCTR2___M 0x00000003 +#define DBG_ITATBCTR2___S 0 + +#define DBG_ITATBCTR1 (0x00BBBEF4) +#define DBG_ITATBCTR1___RWC QCSR_REG_RW +#define DBG_ITATBCTR1__ATID___M 0x0000007F +#define DBG_ITATBCTR1__ATID___S 0 +#define DBG_ITATBCTR1___M 0x0000007F +#define DBG_ITATBCTR1___S 0 + +#define DBG_ITATBCTR0 (0x00BBBEF8) +#define DBG_ITATBCTR0___RWC QCSR_REG_RW +#define DBG_ITATBCTR0___POR 0x00000000 +#define DBG_ITATBCTR0__ATBYTES___POR 0x0 +#define DBG_ITATBCTR0__AFREADY___POR 0x0 +#define DBG_ITATBCTR0__ATVALID___POR 0x0 +#define DBG_ITATBCTR0__ATBYTES___M 0x00000F00 +#define DBG_ITATBCTR0__ATBYTES___S 8 +#define DBG_ITATBCTR0__ATBYTES__ATBYTES_0 0x0 +#define DBG_ITATBCTR0__ATBYTES__ATBYTES_1 0x1 +#define DBG_ITATBCTR0__AFREADY___M 0x00000002 +#define DBG_ITATBCTR0__AFREADY___S 1 +#define DBG_ITATBCTR0__AFREADY__AFREADY_0 0x0 +#define DBG_ITATBCTR0__AFREADY__AFREADY_1 0x1 +#define DBG_ITATBCTR0__ATVALID___M 0x00000001 +#define DBG_ITATBCTR0__ATVALID___S 0 +#define DBG_ITATBCTR0__ATVALID__ATVALID_0 0x0 +#define DBG_ITATBCTR0__ATVALID__ATVALID_1 0x1 +#define DBG_ITATBCTR0___M 0x00000F03 +#define DBG_ITATBCTR0___S 0 + +#define DBG_ITCTRL (0x00BBBF00) +#define DBG_ITCTRL___RWC QCSR_REG_RW +#define DBG_ITCTRL___POR 0x00000000 +#define DBG_ITCTRL__INTEGRATION_MODE___POR 0x0 +#define DBG_ITCTRL__INTEGRATION_MODE___M 0x00000001 +#define DBG_ITCTRL__INTEGRATION_MODE___S 0 +#define DBG_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE_0 0x0 +#define DBG_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE_1 0x1 +#define DBG_ITCTRL___M 0x00000001 +#define DBG_ITCTRL___S 0 + +#define DBG_CLAIMSET (0x00BBBFA0) +#define DBG_CLAIMSET___RWC QCSR_REG_RW +#define DBG_CLAIMSET___POR 0x0000000F +#define DBG_CLAIMSET__CLAIMSET___POR 0xF +#define DBG_CLAIMSET__CLAIMSET___M 0x0000000F +#define DBG_CLAIMSET__CLAIMSET___S 0 +#define DBG_CLAIMSET__CLAIMSET__CLAIMSET_0XF 0xF +#define DBG_CLAIMSET___M 0x0000000F +#define DBG_CLAIMSET___S 0 + +#define DBG_CLAIMCLR (0x00BBBFA4) +#define DBG_CLAIMCLR___RWC QCSR_REG_RW +#define DBG_CLAIMCLR___POR 0x00000000 +#define DBG_CLAIMCLR__CLAIMCLR___POR 0x0 +#define DBG_CLAIMCLR__CLAIMCLR___M 0x0000000F +#define DBG_CLAIMCLR__CLAIMCLR___S 0 +#define DBG_CLAIMCLR___M 0x0000000F +#define DBG_CLAIMCLR___S 0 + +#define DBG_LOCKACCESS (0x00BBBFB0) +#define DBG_LOCKACCESS___RWC QCSR_REG_WO +#define DBG_LOCKACCESS__KEY___M 0xFFFFFFFF +#define DBG_LOCKACCESS__KEY___S 0 +#define DBG_LOCKACCESS__KEY__KEY_0XC5ACCE55 0xC5ACCE55 +#define DBG_LOCKACCESS__KEY__KEY_0XDEADBEEF 0xDEADBEEF +#define DBG_LOCKACCESS___M 0xFFFFFFFF +#define DBG_LOCKACCESS___S 0 + +#define DBG_LOCKSTATUS (0x00BBBFB4) +#define DBG_LOCKSTATUS___RWC QCSR_REG_RO +#define DBG_LOCKSTATUS___POR 0x00000003 +#define DBG_LOCKSTATUS__NTT___POR 0x0 +#define DBG_LOCKSTATUS__SLK___POR 0x1 +#define DBG_LOCKSTATUS__SLI___POR 0x1 +#define DBG_LOCKSTATUS__NTT___M 0x00000004 +#define DBG_LOCKSTATUS__NTT___S 2 +#define DBG_LOCKSTATUS__NTT__NTT_0X0 0x0 +#define DBG_LOCKSTATUS__SLK___M 0x00000002 +#define DBG_LOCKSTATUS__SLK___S 1 +#define DBG_LOCKSTATUS__SLK__SLK_0X0 0x0 +#define DBG_LOCKSTATUS__SLK__SLK_0X1 0x1 +#define DBG_LOCKSTATUS__SLI___M 0x00000001 +#define DBG_LOCKSTATUS__SLI___S 0 +#define DBG_LOCKSTATUS__SLI__SLI_0X0 0x0 +#define DBG_LOCKSTATUS__SLI__SLI_0X1 0x1 +#define DBG_LOCKSTATUS___M 0x00000007 +#define DBG_LOCKSTATUS___S 0 + +#define DBG_AUTHSTATUS (0x00BBBFB8) +#define DBG_AUTHSTATUS___RWC QCSR_REG_RO +#define DBG_AUTHSTATUS___POR 0x00000000 +#define DBG_AUTHSTATUS__SNID___POR 0x0 +#define DBG_AUTHSTATUS__SID___POR 0x0 +#define DBG_AUTHSTATUS__NSNID___POR 0x0 +#define DBG_AUTHSTATUS__NSID___POR 0x0 +#define DBG_AUTHSTATUS__SNID___M 0x000000C0 +#define DBG_AUTHSTATUS__SNID___S 6 +#define DBG_AUTHSTATUS__SNID__SNID_0X0 0x0 +#define DBG_AUTHSTATUS__SID___M 0x00000030 +#define DBG_AUTHSTATUS__SID___S 4 +#define DBG_AUTHSTATUS__SID__SID_0X0 0x0 +#define DBG_AUTHSTATUS__NSNID___M 0x0000000C +#define DBG_AUTHSTATUS__NSNID___S 2 +#define DBG_AUTHSTATUS__NSNID__NSNID_0X0 0x0 +#define DBG_AUTHSTATUS__NSID___M 0x00000003 +#define DBG_AUTHSTATUS__NSID___S 0 +#define DBG_AUTHSTATUS__NSID__NSID_0X0 0x0 +#define DBG_AUTHSTATUS___M 0x000000FF +#define DBG_AUTHSTATUS___S 0 + +#define DBG_DEVID (0x00BBBFC8) +#define DBG_DEVID___RWC QCSR_REG_RO +#define DBG_DEVID___POR 0x00000038 +#define DBG_DEVID__SCHEME___POR 0x3 +#define DBG_DEVID__PORTCOUNT___POR 0x8 +#define DBG_DEVID__SCHEME___M 0x000000F0 +#define DBG_DEVID__SCHEME___S 4 +#define DBG_DEVID__SCHEME__SCHEME_0X3 0x3 +#define DBG_DEVID__PORTCOUNT___M 0x0000000F +#define DBG_DEVID__PORTCOUNT___S 0 +#define DBG_DEVID__PORTCOUNT__PORTCOUNT_0X2 0x2 +#define DBG_DEVID__PORTCOUNT__PORTCOUNT_0X3 0x3 +#define DBG_DEVID__PORTCOUNT__PORTCOUNT_0X4 0x4 +#define DBG_DEVID__PORTCOUNT__PORTCOUNT_0X5 0x5 +#define DBG_DEVID__PORTCOUNT__PORTCOUNT_0X6 0x6 +#define DBG_DEVID__PORTCOUNT__PORTCOUNT_0X7 0x7 +#define DBG_DEVID__PORTCOUNT__PORTCOUNT_0X8 0x8 +#define DBG_DEVID___M 0x000000FF +#define DBG_DEVID___S 0 + +#define DBG_DEVTYPE (0x00BBBFCC) +#define DBG_DEVTYPE___RWC QCSR_REG_RO +#define DBG_DEVTYPE___POR 0x00000012 +#define DBG_DEVTYPE__SUB_TYPE___POR 0x1 +#define DBG_DEVTYPE__MAJOR_TYPE___POR 0x2 +#define DBG_DEVTYPE__SUB_TYPE___M 0x000000F0 +#define DBG_DEVTYPE__SUB_TYPE___S 4 +#define DBG_DEVTYPE__SUB_TYPE__SUB_TYPE_0X1 0x1 +#define DBG_DEVTYPE__MAJOR_TYPE___M 0x0000000F +#define DBG_DEVTYPE__MAJOR_TYPE___S 0 +#define DBG_DEVTYPE__MAJOR_TYPE__MAJOR_TYPE_0X2 0x2 +#define DBG_DEVTYPE___M 0x000000FF +#define DBG_DEVTYPE___S 0 + +#define DBG_PIDR0 (0x00BBBFE0) +#define DBG_PIDR0___RWC QCSR_REG_RO +#define DBG_PIDR0___POR 0x00000008 +#define DBG_PIDR0__PART_NUMBER_BITS7TO0___POR 0x08 +#define DBG_PIDR0__PART_NUMBER_BITS7TO0___M 0x000000FF +#define DBG_PIDR0__PART_NUMBER_BITS7TO0___S 0 +#define DBG_PIDR0__PART_NUMBER_BITS7TO0__PART_NUMBER_BITS7TO0_0X08 0x08 +#define DBG_PIDR0___M 0x000000FF +#define DBG_PIDR0___S 0 + +#define DBG_PIDR1 (0x00BBBFE4) +#define DBG_PIDR1___RWC QCSR_REG_RO +#define DBG_PIDR1___POR 0x000000B9 +#define DBG_PIDR1__JEP106_BITS3TO0___POR 0xB +#define DBG_PIDR1__PART_NUMBER_BITS11TO8___POR 0x9 +#define DBG_PIDR1__JEP106_BITS3TO0___M 0x000000F0 +#define DBG_PIDR1__JEP106_BITS3TO0___S 4 +#define DBG_PIDR1__JEP106_BITS3TO0__JEP106_BITS3TO0_0XB 0xB +#define DBG_PIDR1__PART_NUMBER_BITS11TO8___M 0x0000000F +#define DBG_PIDR1__PART_NUMBER_BITS11TO8___S 0 +#define DBG_PIDR1__PART_NUMBER_BITS11TO8__PART_NUMBER_BITS11TO8_0X9 0x9 +#define DBG_PIDR1___M 0x000000FF +#define DBG_PIDR1___S 0 + +#define DBG_PIDR2 (0x00BBBFE8) +#define DBG_PIDR2___RWC QCSR_REG_RO +#define DBG_PIDR2___POR 0x0000003B +#define DBG_PIDR2__REVISION___POR 0x3 +#define DBG_PIDR2__JEDEC___POR 0x1 +#define DBG_PIDR2__JEP106_BITS6TO4___POR 0x3 +#define DBG_PIDR2__REVISION___M 0x000000F0 +#define DBG_PIDR2__REVISION___S 4 +#define DBG_PIDR2__REVISION__REVISION_0X3 0x3 +#define DBG_PIDR2__JEDEC___M 0x00000008 +#define DBG_PIDR2__JEDEC___S 3 +#define DBG_PIDR2__JEDEC__JEDEC_0X1 0x1 +#define DBG_PIDR2__JEP106_BITS6TO4___M 0x00000007 +#define DBG_PIDR2__JEP106_BITS6TO4___S 0 +#define DBG_PIDR2__JEP106_BITS6TO4__JEP106_BITS6TO4_0X3 0x3 +#define DBG_PIDR2___M 0x000000FF +#define DBG_PIDR2___S 0 + +#define DBG_PIDR3 (0x00BBBFEC) +#define DBG_PIDR3___RWC QCSR_REG_RO +#define DBG_PIDR3___POR 0x00000000 +#define DBG_PIDR3__REVAND___POR 0x0 +#define DBG_PIDR3__CUSTOMER_MODIFIED___POR 0x0 +#define DBG_PIDR3__REVAND___M 0x000000F0 +#define DBG_PIDR3__REVAND___S 4 +#define DBG_PIDR3__REVAND__REVAND_0X0 0x0 +#define DBG_PIDR3__CUSTOMER_MODIFIED___M 0x0000000F +#define DBG_PIDR3__CUSTOMER_MODIFIED___S 0 +#define DBG_PIDR3__CUSTOMER_MODIFIED__CUSTOMER_MODIFIED_0X0 0x0 +#define DBG_PIDR3___M 0x000000FF +#define DBG_PIDR3___S 0 + +#define DBG_PIDR4 (0x00BBBFD0) +#define DBG_PIDR4___RWC QCSR_REG_RO +#define DBG_PIDR4___POR 0x00000004 +#define DBG_PIDR4__FOURKB_COUNT___POR 0x0 +#define DBG_PIDR4__JEP106_CONT___POR 0x4 +#define DBG_PIDR4__FOURKB_COUNT___M 0x000000F0 +#define DBG_PIDR4__FOURKB_COUNT___S 4 +#define DBG_PIDR4__FOURKB_COUNT__FOURKB_COUNT_0X0 0x0 +#define DBG_PIDR4__JEP106_CONT___M 0x0000000F +#define DBG_PIDR4__JEP106_CONT___S 0 +#define DBG_PIDR4__JEP106_CONT__JEP106_CONT_0X4 0x4 +#define DBG_PIDR4___M 0x000000FF +#define DBG_PIDR4___S 0 + +#define DBG_PERIPHID5 (0x00BBBFD4) +#define DBG_PERIPHID5___RWC QCSR_REG_RO +#define DBG_PERIPHID5___POR 0x00000000 +#define DBG_PERIPHID5__PERIPHID5___POR 0x00000000 +#define DBG_PERIPHID5__PERIPHID5___M 0xFFFFFFFF +#define DBG_PERIPHID5__PERIPHID5___S 0 +#define DBG_PERIPHID5___M 0xFFFFFFFF +#define DBG_PERIPHID5___S 0 + +#define DBG_PERIPHID6 (0x00BBBFD8) +#define DBG_PERIPHID6___RWC QCSR_REG_RO +#define DBG_PERIPHID6___POR 0x00000000 +#define DBG_PERIPHID6__PERIPHID6___POR 0x00000000 +#define DBG_PERIPHID6__PERIPHID6___M 0xFFFFFFFF +#define DBG_PERIPHID6__PERIPHID6___S 0 +#define DBG_PERIPHID6___M 0xFFFFFFFF +#define DBG_PERIPHID6___S 0 + +#define DBG_PERIPHID7 (0x00BBBFDC) +#define DBG_PERIPHID7___RWC QCSR_REG_RO +#define DBG_PERIPHID7___POR 0x00000000 +#define DBG_PERIPHID7__PERIPHID7___POR 0x00000000 +#define DBG_PERIPHID7__PERIPHID7___M 0xFFFFFFFF +#define DBG_PERIPHID7__PERIPHID7___S 0 +#define DBG_PERIPHID7___M 0xFFFFFFFF +#define DBG_PERIPHID7___S 0 + +#define DBG_CID0 (0x00BBBFF0) +#define DBG_CID0___RWC QCSR_REG_RO +#define DBG_CID0___POR 0x0000000D +#define DBG_CID0__PREAMBLE___POR 0x0D +#define DBG_CID0__PREAMBLE___M 0x000000FF +#define DBG_CID0__PREAMBLE___S 0 +#define DBG_CID0__PREAMBLE__PREAMBLE_0X0D 0x0D +#define DBG_CID0___M 0x000000FF +#define DBG_CID0___S 0 + +#define DBG_CID1 (0x00BBBFF4) +#define DBG_CID1___RWC QCSR_REG_RO +#define DBG_CID1___POR 0x00000090 +#define DBG_CID1__CLASS___POR 0x9 +#define DBG_CID1__PREAMBLE___POR 0x0 +#define DBG_CID1__CLASS___M 0x000000F0 +#define DBG_CID1__CLASS___S 4 +#define DBG_CID1__CLASS__CLASS_0X9 0x9 +#define DBG_CID1__PREAMBLE___M 0x0000000F +#define DBG_CID1__PREAMBLE___S 0 +#define DBG_CID1__PREAMBLE__PREAMBLE_0X0 0x0 +#define DBG_CID1___M 0x000000FF +#define DBG_CID1___S 0 + +#define DBG_CID2 (0x00BBBFF8) +#define DBG_CID2___RWC QCSR_REG_RO +#define DBG_CID2___POR 0x00000005 +#define DBG_CID2__PREAMBLE___POR 0x05 +#define DBG_CID2__PREAMBLE___M 0x000000FF +#define DBG_CID2__PREAMBLE___S 0 +#define DBG_CID2__PREAMBLE__PREAMBLE_0X05 0x05 +#define DBG_CID2___M 0x000000FF +#define DBG_CID2___S 0 + +#define DBG_CID3 (0x00BBBFFC) +#define DBG_CID3___RWC QCSR_REG_RO +#define DBG_CID3___POR 0x000000B1 +#define DBG_CID3__PREAMBLE___POR 0xB1 +#define DBG_CID3__PREAMBLE___M 0x000000FF +#define DBG_CID3__PREAMBLE___S 0 +#define DBG_CID3__PREAMBLE__PREAMBLE_0XB1 0xB1 +#define DBG_CID3___M 0x000000FF +#define DBG_CID3___S 0 + +#define DBG_TMC_RSZ (0x00BBC004) +#define DBG_TMC_RSZ___RWC QCSR_REG_RO +#define DBG_TMC_RSZ___POR 0x00002000 +#define DBG_TMC_RSZ__RSZ___POR 0x00002000 +#define DBG_TMC_RSZ__RSZ___M 0x7FFFFFFF +#define DBG_TMC_RSZ__RSZ___S 0 +#define DBG_TMC_RSZ___M 0x7FFFFFFF +#define DBG_TMC_RSZ___S 0 + +#define DBG_TMC_STS (0x00BBC00C) +#define DBG_TMC_STS___RWC QCSR_REG_RO +#define DBG_TMC_STS___POR 0x0000000C +#define DBG_TMC_STS__EMPTY___POR 0x0 +#define DBG_TMC_STS__FTEMPTY___POR 0x1 +#define DBG_TMC_STS__TMCREADY___POR 0x1 +#define DBG_TMC_STS__TRIGGERED___POR 0x0 +#define DBG_TMC_STS__FULL___POR 0x0 +#define DBG_TMC_STS__EMPTY___M 0x00000010 +#define DBG_TMC_STS__EMPTY___S 4 +#define DBG_TMC_STS__EMPTY__LOW 0x0 +#define DBG_TMC_STS__EMPTY__HIGH 0x1 +#define DBG_TMC_STS__FTEMPTY___M 0x00000008 +#define DBG_TMC_STS__FTEMPTY___S 3 +#define DBG_TMC_STS__FTEMPTY__LOW 0x0 +#define DBG_TMC_STS__FTEMPTY__HIGH 0x1 +#define DBG_TMC_STS__TMCREADY___M 0x00000004 +#define DBG_TMC_STS__TMCREADY___S 2 +#define DBG_TMC_STS__TMCREADY__LOW 0x0 +#define DBG_TMC_STS__TMCREADY__HIGH 0x1 +#define DBG_TMC_STS__TRIGGERED___M 0x00000002 +#define DBG_TMC_STS__TRIGGERED___S 1 +#define DBG_TMC_STS__TRIGGERED__LOW 0x0 +#define DBG_TMC_STS__TRIGGERED__HIGH 0x1 +#define DBG_TMC_STS__FULL___M 0x00000001 +#define DBG_TMC_STS__FULL___S 0 +#define DBG_TMC_STS__FULL__LOW 0x0 +#define DBG_TMC_STS__FULL__HIGH 0x1 +#define DBG_TMC_STS___M 0x0000001F +#define DBG_TMC_STS___S 0 + +#define DBG_TMC_RRD (0x00BBC010) +#define DBG_TMC_RRD___RWC QCSR_REG_RO +#define DBG_TMC_RRD__RRD___M 0xFFFFFFFF +#define DBG_TMC_RRD__RRD___S 0 +#define DBG_TMC_RRD___M 0xFFFFFFFF +#define DBG_TMC_RRD___S 0 + +#define DBG_TMC_RRP (0x00BBC014) +#define DBG_TMC_RRP___RWC QCSR_REG_RW +#define DBG_TMC_RRP___POR 0x00000000 +#define DBG_TMC_RRP__RRP___POR 0x0000 +#define DBG_TMC_RRP__RRP___M 0x00007FFF +#define DBG_TMC_RRP__RRP___S 0 +#define DBG_TMC_RRP___M 0x00007FFF +#define DBG_TMC_RRP___S 0 + +#define DBG_TMC_RWP (0x00BBC018) +#define DBG_TMC_RWP___RWC QCSR_REG_RW +#define DBG_TMC_RWP___POR 0x00000000 +#define DBG_TMC_RWP__RWP___POR 0x0000 +#define DBG_TMC_RWP__RWP___M 0x00007FFF +#define DBG_TMC_RWP__RWP___S 0 +#define DBG_TMC_RWP___M 0x00007FFF +#define DBG_TMC_RWP___S 0 + +#define DBG_TMC_TRG (0x00BBC01C) +#define DBG_TMC_TRG___RWC QCSR_REG_RW +#define DBG_TMC_TRG___POR 0x00000000 +#define DBG_TMC_TRG__TRG___POR 0x0000 +#define DBG_TMC_TRG__TRG___M 0x00001FFF +#define DBG_TMC_TRG__TRG___S 0 +#define DBG_TMC_TRG___M 0x00001FFF +#define DBG_TMC_TRG___S 0 + +#define DBG_TMC_CTL (0x00BBC020) +#define DBG_TMC_CTL___RWC QCSR_REG_RW +#define DBG_TMC_CTL___POR 0x00000000 +#define DBG_TMC_CTL__TRACECAPTEN___POR 0x0 +#define DBG_TMC_CTL__TRACECAPTEN___M 0x00000001 +#define DBG_TMC_CTL__TRACECAPTEN___S 0 +#define DBG_TMC_CTL__TRACECAPTEN__LOW 0x0 +#define DBG_TMC_CTL__TRACECAPTEN__HIGH 0x1 +#define DBG_TMC_CTL___M 0x00000001 +#define DBG_TMC_CTL___S 0 + +#define DBG_TMC_RWD (0x00BBC024) +#define DBG_TMC_RWD___RWC QCSR_REG_WO +#define DBG_TMC_RWD__RWD___M 0xFFFFFFFF +#define DBG_TMC_RWD__RWD___S 0 +#define DBG_TMC_RWD___M 0xFFFFFFFF +#define DBG_TMC_RWD___S 0 + +#define DBG_TMC_MODE (0x00BBC028) +#define DBG_TMC_MODE___RWC QCSR_REG_RW +#define DBG_TMC_MODE___POR 0x00000000 +#define DBG_TMC_MODE__MODE___POR 0x0 +#define DBG_TMC_MODE__MODE___M 0x00000003 +#define DBG_TMC_MODE__MODE___S 0 +#define DBG_TMC_MODE__MODE__CIRCULAR_BUFFER 0x0 +#define DBG_TMC_MODE__MODE__SW_FIFO 0x1 +#define DBG_TMC_MODE__MODE__HW_FIFO 0x2 +#define DBG_TMC_MODE__MODE__RESERVED 0x3 +#define DBG_TMC_MODE___M 0x00000003 +#define DBG_TMC_MODE___S 0 + +#define DBG_TMC_LBUFLEVEL (0x00BBC02C) +#define DBG_TMC_LBUFLEVEL___RWC QCSR_REG_RO +#define DBG_TMC_LBUFLEVEL___POR 0x00000000 +#define DBG_TMC_LBUFLEVEL__LBUFLEVEL___POR 0x0000 +#define DBG_TMC_LBUFLEVEL__LBUFLEVEL___M 0x00003FFF +#define DBG_TMC_LBUFLEVEL__LBUFLEVEL___S 0 +#define DBG_TMC_LBUFLEVEL___M 0x00003FFF +#define DBG_TMC_LBUFLEVEL___S 0 + +#define DBG_TMC_CBUFLEVEL (0x00BBC030) +#define DBG_TMC_CBUFLEVEL___RWC QCSR_REG_RO +#define DBG_TMC_CBUFLEVEL___POR 0x00000000 +#define DBG_TMC_CBUFLEVEL__CBUFLEVEL___POR 0x0000 +#define DBG_TMC_CBUFLEVEL__CBUFLEVEL___M 0x00003FFF +#define DBG_TMC_CBUFLEVEL__CBUFLEVEL___S 0 +#define DBG_TMC_CBUFLEVEL___M 0x00003FFF +#define DBG_TMC_CBUFLEVEL___S 0 + +#define DBG_TMC_BUFWM (0x00BBC034) +#define DBG_TMC_BUFWM___RWC QCSR_REG_RW +#define DBG_TMC_BUFWM___POR 0x00000000 +#define DBG_TMC_BUFWM__BUFWM___POR 0x0000 +#define DBG_TMC_BUFWM__BUFWM___M 0x00001FFF +#define DBG_TMC_BUFWM__BUFWM___S 0 +#define DBG_TMC_BUFWM___M 0x00001FFF +#define DBG_TMC_BUFWM___S 0 + +#define DBG_TMC_FFSR (0x00BBC300) +#define DBG_TMC_FFSR___RWC QCSR_REG_RO +#define DBG_TMC_FFSR___POR 0x00000002 +#define DBG_TMC_FFSR__FTSTOPPED___POR 0x1 +#define DBG_TMC_FFSR__FLINPROG___POR 0x0 +#define DBG_TMC_FFSR__FTSTOPPED___M 0x00000002 +#define DBG_TMC_FFSR__FTSTOPPED___S 1 +#define DBG_TMC_FFSR__FTSTOPPED__LOW 0x0 +#define DBG_TMC_FFSR__FTSTOPPED__HIGH 0x1 +#define DBG_TMC_FFSR__FLINPROG___M 0x00000001 +#define DBG_TMC_FFSR__FLINPROG___S 0 +#define DBG_TMC_FFSR__FLINPROG__LOW 0x0 +#define DBG_TMC_FFSR__FLINPROG__HIGH 0x1 +#define DBG_TMC_FFSR___M 0x00000003 +#define DBG_TMC_FFSR___S 0 + +#define DBG_TMC_FFCR (0x00BBC304) +#define DBG_TMC_FFCR___RWC QCSR_REG_RW +#define DBG_TMC_FFCR___POR 0x00000000 +#define DBG_TMC_FFCR__DRAINBUFFER___POR 0x0 +#define DBG_TMC_FFCR__STOPONTRIGEVT___POR 0x0 +#define DBG_TMC_FFCR__STOPONFL___POR 0x0 +#define DBG_TMC_FFCR__TRIGONFL___POR 0x0 +#define DBG_TMC_FFCR__TRIGONTRIGEVT___POR 0x0 +#define DBG_TMC_FFCR__TRIGONTRIGIN___POR 0x0 +#define DBG_TMC_FFCR__FLUSHMAN___POR 0x0 +#define DBG_TMC_FFCR__FONTRIGEVT___POR 0x0 +#define DBG_TMC_FFCR__FONFLIN___POR 0x0 +#define DBG_TMC_FFCR__ENTI___POR 0x0 +#define DBG_TMC_FFCR__ENFT___POR 0x0 +#define DBG_TMC_FFCR__DRAINBUFFER___M 0x00004000 +#define DBG_TMC_FFCR__DRAINBUFFER___S 14 +#define DBG_TMC_FFCR__DRAINBUFFER__LOW 0x0 +#define DBG_TMC_FFCR__DRAINBUFFER__HIGH 0x1 +#define DBG_TMC_FFCR__STOPONTRIGEVT___M 0x00002000 +#define DBG_TMC_FFCR__STOPONTRIGEVT___S 13 +#define DBG_TMC_FFCR__STOPONTRIGEVT__LOW 0x0 +#define DBG_TMC_FFCR__STOPONTRIGEVT__HIGH 0x1 +#define DBG_TMC_FFCR__STOPONFL___M 0x00001000 +#define DBG_TMC_FFCR__STOPONFL___S 12 +#define DBG_TMC_FFCR__STOPONFL__LOW 0x0 +#define DBG_TMC_FFCR__STOPONFL__HIGH 0x1 +#define DBG_TMC_FFCR__TRIGONFL___M 0x00000400 +#define DBG_TMC_FFCR__TRIGONFL___S 10 +#define DBG_TMC_FFCR__TRIGONFL__LOW 0x0 +#define DBG_TMC_FFCR__TRIGONFL__HIGH 0x1 +#define DBG_TMC_FFCR__TRIGONTRIGEVT___M 0x00000200 +#define DBG_TMC_FFCR__TRIGONTRIGEVT___S 9 +#define DBG_TMC_FFCR__TRIGONTRIGEVT__LOW 0x0 +#define DBG_TMC_FFCR__TRIGONTRIGEVT__HIGH 0x1 +#define DBG_TMC_FFCR__TRIGONTRIGIN___M 0x00000100 +#define DBG_TMC_FFCR__TRIGONTRIGIN___S 8 +#define DBG_TMC_FFCR__TRIGONTRIGIN__LOW 0x0 +#define DBG_TMC_FFCR__TRIGONTRIGIN__HIGH 0x1 +#define DBG_TMC_FFCR__FLUSHMAN___M 0x00000040 +#define DBG_TMC_FFCR__FLUSHMAN___S 6 +#define DBG_TMC_FFCR__FLUSHMAN__LOW 0x0 +#define DBG_TMC_FFCR__FLUSHMAN__HIGH 0x1 +#define DBG_TMC_FFCR__FONTRIGEVT___M 0x00000020 +#define DBG_TMC_FFCR__FONTRIGEVT___S 5 +#define DBG_TMC_FFCR__FONTRIGEVT__LOW 0x0 +#define DBG_TMC_FFCR__FONTRIGEVT__HIGH 0x1 +#define DBG_TMC_FFCR__FONFLIN___M 0x00000010 +#define DBG_TMC_FFCR__FONFLIN___S 4 +#define DBG_TMC_FFCR__FONFLIN__LOW 0x0 +#define DBG_TMC_FFCR__FONFLIN__HIGH 0x1 +#define DBG_TMC_FFCR__ENTI___M 0x00000002 +#define DBG_TMC_FFCR__ENTI___S 1 +#define DBG_TMC_FFCR__ENTI__TRIGGER_INSERTION_DISABLED 0x0 +#define DBG_TMC_FFCR__ENTI__TRIGGER_INSERTION_ENABLED 0x1 +#define DBG_TMC_FFCR__ENFT___M 0x00000001 +#define DBG_TMC_FFCR__ENFT___S 0 +#define DBG_TMC_FFCR__ENFT__LOW 0x0 +#define DBG_TMC_FFCR__ENFT__HIGH 0x1 +#define DBG_TMC_FFCR___M 0x00007773 +#define DBG_TMC_FFCR___S 0 + +#define DBG_TMC_PSCR (0x00BBC308) +#define DBG_TMC_PSCR___RWC QCSR_REG_RW +#define DBG_TMC_PSCR___POR 0x00000000 +#define DBG_TMC_PSCR__PSCOUNT___POR 0x00 +#define DBG_TMC_PSCR__PSCOUNT___M 0x0000001F +#define DBG_TMC_PSCR__PSCOUNT___S 0 +#define DBG_TMC_PSCR___M 0x0000001F +#define DBG_TMC_PSCR___S 0 + +#define DBG_TMC_ITATBMDATA0 (0x00BBCED0) +#define DBG_TMC_ITATBMDATA0___RWC QCSR_REG_WO +#define DBG_TMC_ITATBMDATA0___POR 0x00000000 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT127___POR 0x0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT119___POR 0x0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT111___POR 0x0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT103___POR 0x0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT95___POR 0x0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT87___POR 0x0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT79___POR 0x0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT71___POR 0x0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT63___POR 0x0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT55___POR 0x0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT47___POR 0x0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT39___POR 0x0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT31___POR 0x0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT23___POR 0x0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT15___POR 0x0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT7___POR 0x0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT0___POR 0x0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT127___M 0x00010000 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT127___S 16 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT127__LOW 0x0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT127__HIGH 0x1 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT119___M 0x00008000 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT119___S 15 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT119__LOW 0x0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT119__HIGH 0x1 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT111___M 0x00004000 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT111___S 14 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT111__LOW 0x0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT111__HIGH 0x1 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT103___M 0x00002000 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT103___S 13 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT103__LOW 0x0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT103__HIGH 0x1 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT95___M 0x00001000 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT95___S 12 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT95__LOW 0x0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT95__HIGH 0x1 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT87___M 0x00000800 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT87___S 11 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT87__LOW 0x0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT87__HIGH 0x1 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT79___M 0x00000400 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT79___S 10 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT79__LOW 0x0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT79__HIGH 0x1 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT71___M 0x00000200 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT71___S 9 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT71__LOW 0x0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT71__HIGH 0x1 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT63___M 0x00000100 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT63___S 8 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT63__LOW 0x0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT63__HIGH 0x1 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT55___M 0x00000080 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT55___S 7 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT55__LOW 0x0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT55__HIGH 0x1 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT47___M 0x00000040 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT47___S 6 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT47__LOW 0x0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT47__HIGH 0x1 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT39___M 0x00000020 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT39___S 5 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT39__LOW 0x0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT39__HIGH 0x1 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT31___M 0x00000010 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT31___S 4 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT31__LOW 0x0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT31__HIGH 0x1 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT23___M 0x00000008 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT23___S 3 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT23__LOW 0x0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT23__HIGH 0x1 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT15___M 0x00000004 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT15___S 2 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT15__LOW 0x0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT15__HIGH 0x1 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT7___M 0x00000002 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT7___S 1 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT7__LOW 0x0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT7__HIGH 0x1 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT0___M 0x00000001 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT0___S 0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT0__LOW 0x0 +#define DBG_TMC_ITATBMDATA0__ATDATAMBIT0__HIGH 0x1 +#define DBG_TMC_ITATBMDATA0___M 0x0001FFFF +#define DBG_TMC_ITATBMDATA0___S 0 + +#define DBG_TMC_ITATBMCTR2 (0x00BBCED4) +#define DBG_TMC_ITATBMCTR2___RWC QCSR_REG_RO +#define DBG_TMC_ITATBMCTR2___POR 0x00000001 +#define DBG_TMC_ITATBMCTR2__SYNCREQM___POR 0x0 +#define DBG_TMC_ITATBMCTR2__AFVALIDM___POR 0x0 +#define DBG_TMC_ITATBMCTR2__ATREADYM___POR 0x1 +#define DBG_TMC_ITATBMCTR2__SYNCREQM___M 0x00000004 +#define DBG_TMC_ITATBMCTR2__SYNCREQM___S 2 +#define DBG_TMC_ITATBMCTR2__SYNCREQM__LOW 0x0 +#define DBG_TMC_ITATBMCTR2__SYNCREQM__HIGH 0x1 +#define DBG_TMC_ITATBMCTR2__AFVALIDM___M 0x00000002 +#define DBG_TMC_ITATBMCTR2__AFVALIDM___S 1 +#define DBG_TMC_ITATBMCTR2__AFVALIDM__LOW 0x0 +#define DBG_TMC_ITATBMCTR2__AFVALIDM__HIGH 0x1 +#define DBG_TMC_ITATBMCTR2__ATREADYM___M 0x00000001 +#define DBG_TMC_ITATBMCTR2__ATREADYM___S 0 +#define DBG_TMC_ITATBMCTR2__ATREADYM__LOW 0x0 +#define DBG_TMC_ITATBMCTR2__ATREADYM__HIGH 0x1 +#define DBG_TMC_ITATBMCTR2___M 0x00000007 +#define DBG_TMC_ITATBMCTR2___S 0 + +#define DBG_TMC_ITATBMCTR1 (0x00BBCED8) +#define DBG_TMC_ITATBMCTR1___RWC QCSR_REG_WO +#define DBG_TMC_ITATBMCTR1___POR 0x00000000 +#define DBG_TMC_ITATBMCTR1__ATIDM___POR 0x00 +#define DBG_TMC_ITATBMCTR1__ATIDM___M 0x0000007F +#define DBG_TMC_ITATBMCTR1__ATIDM___S 0 +#define DBG_TMC_ITATBMCTR1___M 0x0000007F +#define DBG_TMC_ITATBMCTR1___S 0 + +#define DBG_TMC_ITATBMCTR0 (0x00BBCEDC) +#define DBG_TMC_ITATBMCTR0___RWC QCSR_REG_WO +#define DBG_TMC_ITATBMCTR0___POR 0x00000000 +#define DBG_TMC_ITATBMCTR0__ATBYTESM___POR 0x0 +#define DBG_TMC_ITATBMCTR0__AFREADYM___POR 0x0 +#define DBG_TMC_ITATBMCTR0__ATVALIDM___POR 0x0 +#define DBG_TMC_ITATBMCTR0__ATBYTESM___M 0x00000F00 +#define DBG_TMC_ITATBMCTR0__ATBYTESM___S 8 +#define DBG_TMC_ITATBMCTR0__AFREADYM___M 0x00000002 +#define DBG_TMC_ITATBMCTR0__AFREADYM___S 1 +#define DBG_TMC_ITATBMCTR0__AFREADYM__LOW 0x0 +#define DBG_TMC_ITATBMCTR0__AFREADYM__HIGH 0x1 +#define DBG_TMC_ITATBMCTR0__ATVALIDM___M 0x00000001 +#define DBG_TMC_ITATBMCTR0__ATVALIDM___S 0 +#define DBG_TMC_ITATBMCTR0__ATVALIDM__LOW 0x0 +#define DBG_TMC_ITATBMCTR0__ATVALIDM__HIGH 0x1 +#define DBG_TMC_ITATBMCTR0___M 0x00000F03 +#define DBG_TMC_ITATBMCTR0___S 0 + +#define DBG_TMC_ITMISCOP0 (0x00BBCEE0) +#define DBG_TMC_ITMISCOP0___RWC QCSR_REG_WO +#define DBG_TMC_ITMISCOP0___POR 0x00000000 +#define DBG_TMC_ITMISCOP0__FULL___POR 0x0 +#define DBG_TMC_ITMISCOP0__ACQCOMP___POR 0x0 +#define DBG_TMC_ITMISCOP0__FULL___M 0x00000002 +#define DBG_TMC_ITMISCOP0__FULL___S 1 +#define DBG_TMC_ITMISCOP0__FULL__LOW 0x0 +#define DBG_TMC_ITMISCOP0__FULL__HIGH 0x1 +#define DBG_TMC_ITMISCOP0__ACQCOMP___M 0x00000001 +#define DBG_TMC_ITMISCOP0__ACQCOMP___S 0 +#define DBG_TMC_ITMISCOP0__ACQCOMP__LOW 0x0 +#define DBG_TMC_ITMISCOP0__ACQCOMP__HIGH 0x1 +#define DBG_TMC_ITMISCOP0___M 0x00000003 +#define DBG_TMC_ITMISCOP0___S 0 + +#define DBG_TMC_ITTRFLIN (0x00BBCEE8) +#define DBG_TMC_ITTRFLIN___RWC QCSR_REG_RO +#define DBG_TMC_ITTRFLIN___POR 0x00000000 +#define DBG_TMC_ITTRFLIN__FLUSHIN___POR 0x0 +#define DBG_TMC_ITTRFLIN__TRIGIN___POR 0x0 +#define DBG_TMC_ITTRFLIN__FLUSHIN___M 0x00000002 +#define DBG_TMC_ITTRFLIN__FLUSHIN___S 1 +#define DBG_TMC_ITTRFLIN__FLUSHIN__LOW 0x0 +#define DBG_TMC_ITTRFLIN__FLUSHIN__HIGH 0x1 +#define DBG_TMC_ITTRFLIN__TRIGIN___M 0x00000001 +#define DBG_TMC_ITTRFLIN__TRIGIN___S 0 +#define DBG_TMC_ITTRFLIN__TRIGIN__LOW 0x0 +#define DBG_TMC_ITTRFLIN__TRIGIN__HIGH 0x1 +#define DBG_TMC_ITTRFLIN___M 0x00000003 +#define DBG_TMC_ITTRFLIN___S 0 + +#define DBG_TMC_ITATBDATA0 (0x00BBCEEC) +#define DBG_TMC_ITATBDATA0___RWC QCSR_REG_RO +#define DBG_TMC_ITATBDATA0___POR 0x00000000 +#define DBG_TMC_ITATBDATA0__ATDATASBIT127___POR 0x0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT119___POR 0x0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT111___POR 0x0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT103___POR 0x0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT95___POR 0x0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT87___POR 0x0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT79___POR 0x0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT71___POR 0x0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT63___POR 0x0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT55___POR 0x0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT47___POR 0x0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT39___POR 0x0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT31___POR 0x0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT23___POR 0x0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT15___POR 0x0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT7___POR 0x0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT0___POR 0x0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT127___M 0x00010000 +#define DBG_TMC_ITATBDATA0__ATDATASBIT127___S 16 +#define DBG_TMC_ITATBDATA0__ATDATASBIT127__LOW 0x0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT127__HIGH 0x1 +#define DBG_TMC_ITATBDATA0__ATDATASBIT119___M 0x00008000 +#define DBG_TMC_ITATBDATA0__ATDATASBIT119___S 15 +#define DBG_TMC_ITATBDATA0__ATDATASBIT119__LOW 0x0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT119__HIGH 0x1 +#define DBG_TMC_ITATBDATA0__ATDATASBIT111___M 0x00004000 +#define DBG_TMC_ITATBDATA0__ATDATASBIT111___S 14 +#define DBG_TMC_ITATBDATA0__ATDATASBIT111__LOW 0x0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT111__HIGH 0x1 +#define DBG_TMC_ITATBDATA0__ATDATASBIT103___M 0x00002000 +#define DBG_TMC_ITATBDATA0__ATDATASBIT103___S 13 +#define DBG_TMC_ITATBDATA0__ATDATASBIT103__LOW 0x0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT103__HIGH 0x1 +#define DBG_TMC_ITATBDATA0__ATDATASBIT95___M 0x00001000 +#define DBG_TMC_ITATBDATA0__ATDATASBIT95___S 12 +#define DBG_TMC_ITATBDATA0__ATDATASBIT95__LOW 0x0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT95__HIGH 0x1 +#define DBG_TMC_ITATBDATA0__ATDATASBIT87___M 0x00000800 +#define DBG_TMC_ITATBDATA0__ATDATASBIT87___S 11 +#define DBG_TMC_ITATBDATA0__ATDATASBIT87__LOW 0x0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT87__HIGH 0x1 +#define DBG_TMC_ITATBDATA0__ATDATASBIT79___M 0x00000400 +#define DBG_TMC_ITATBDATA0__ATDATASBIT79___S 10 +#define DBG_TMC_ITATBDATA0__ATDATASBIT79__LOW 0x0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT79__HIGH 0x1 +#define DBG_TMC_ITATBDATA0__ATDATASBIT71___M 0x00000200 +#define DBG_TMC_ITATBDATA0__ATDATASBIT71___S 9 +#define DBG_TMC_ITATBDATA0__ATDATASBIT71__LOW 0x0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT71__HIGH 0x1 +#define DBG_TMC_ITATBDATA0__ATDATASBIT63___M 0x00000100 +#define DBG_TMC_ITATBDATA0__ATDATASBIT63___S 8 +#define DBG_TMC_ITATBDATA0__ATDATASBIT63__LOW 0x0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT63__HIGH 0x1 +#define DBG_TMC_ITATBDATA0__ATDATASBIT55___M 0x00000080 +#define DBG_TMC_ITATBDATA0__ATDATASBIT55___S 7 +#define DBG_TMC_ITATBDATA0__ATDATASBIT55__LOW 0x0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT55__HIGH 0x1 +#define DBG_TMC_ITATBDATA0__ATDATASBIT47___M 0x00000040 +#define DBG_TMC_ITATBDATA0__ATDATASBIT47___S 6 +#define DBG_TMC_ITATBDATA0__ATDATASBIT47__LOW 0x0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT47__HIGH 0x1 +#define DBG_TMC_ITATBDATA0__ATDATASBIT39___M 0x00000020 +#define DBG_TMC_ITATBDATA0__ATDATASBIT39___S 5 +#define DBG_TMC_ITATBDATA0__ATDATASBIT39__LOW 0x0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT39__HIGH 0x1 +#define DBG_TMC_ITATBDATA0__ATDATASBIT31___M 0x00000010 +#define DBG_TMC_ITATBDATA0__ATDATASBIT31___S 4 +#define DBG_TMC_ITATBDATA0__ATDATASBIT31__LOW 0x0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT31__HIGH 0x1 +#define DBG_TMC_ITATBDATA0__ATDATASBIT23___M 0x00000008 +#define DBG_TMC_ITATBDATA0__ATDATASBIT23___S 3 +#define DBG_TMC_ITATBDATA0__ATDATASBIT23__LOW 0x0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT23__HIGH 0x1 +#define DBG_TMC_ITATBDATA0__ATDATASBIT15___M 0x00000004 +#define DBG_TMC_ITATBDATA0__ATDATASBIT15___S 2 +#define DBG_TMC_ITATBDATA0__ATDATASBIT15__LOW 0x0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT15__HIGH 0x1 +#define DBG_TMC_ITATBDATA0__ATDATASBIT7___M 0x00000002 +#define DBG_TMC_ITATBDATA0__ATDATASBIT7___S 1 +#define DBG_TMC_ITATBDATA0__ATDATASBIT7__LOW 0x0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT7__HIGH 0x1 +#define DBG_TMC_ITATBDATA0__ATDATASBIT0___M 0x00000001 +#define DBG_TMC_ITATBDATA0__ATDATASBIT0___S 0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT0__LOW 0x0 +#define DBG_TMC_ITATBDATA0__ATDATASBIT0__HIGH 0x1 +#define DBG_TMC_ITATBDATA0___M 0x0001FFFF +#define DBG_TMC_ITATBDATA0___S 0 + +#define DBG_TMC_ITATBCTR2 (0x00BBCEF0) +#define DBG_TMC_ITATBCTR2___RWC QCSR_REG_WO +#define DBG_TMC_ITATBCTR2___POR 0x00000000 +#define DBG_TMC_ITATBCTR2__SYNCREQS___POR 0x0 +#define DBG_TMC_ITATBCTR2__AFVALIDS___POR 0x0 +#define DBG_TMC_ITATBCTR2__ATREADYS___POR 0x0 +#define DBG_TMC_ITATBCTR2__SYNCREQS___M 0x00000004 +#define DBG_TMC_ITATBCTR2__SYNCREQS___S 2 +#define DBG_TMC_ITATBCTR2__SYNCREQS__LOW 0x0 +#define DBG_TMC_ITATBCTR2__SYNCREQS__HIGH 0x1 +#define DBG_TMC_ITATBCTR2__AFVALIDS___M 0x00000002 +#define DBG_TMC_ITATBCTR2__AFVALIDS___S 1 +#define DBG_TMC_ITATBCTR2__AFVALIDS__LOW 0x0 +#define DBG_TMC_ITATBCTR2__AFVALIDS__HIGH 0x1 +#define DBG_TMC_ITATBCTR2__ATREADYS___M 0x00000001 +#define DBG_TMC_ITATBCTR2__ATREADYS___S 0 +#define DBG_TMC_ITATBCTR2__ATREADYS__LOW 0x0 +#define DBG_TMC_ITATBCTR2__ATREADYS__HIGH 0x1 +#define DBG_TMC_ITATBCTR2___M 0x00000007 +#define DBG_TMC_ITATBCTR2___S 0 + +#define DBG_TMC_ITATBCTR1 (0x00BBCEF4) +#define DBG_TMC_ITATBCTR1___RWC QCSR_REG_RO +#define DBG_TMC_ITATBCTR1___POR 0x00000000 +#define DBG_TMC_ITATBCTR1__ATIDS___POR 0x00 +#define DBG_TMC_ITATBCTR1__ATIDS___M 0x0000007F +#define DBG_TMC_ITATBCTR1__ATIDS___S 0 +#define DBG_TMC_ITATBCTR1___M 0x0000007F +#define DBG_TMC_ITATBCTR1___S 0 + +#define DBG_TMC_ITATBCTR0 (0x00BBCEF8) +#define DBG_TMC_ITATBCTR0___RWC QCSR_REG_RO +#define DBG_TMC_ITATBCTR0___POR 0x00000000 +#define DBG_TMC_ITATBCTR0__ATBYTESS___POR 0x0 +#define DBG_TMC_ITATBCTR0__AFREADYS___POR 0x0 +#define DBG_TMC_ITATBCTR0__ATVALIDS___POR 0x0 +#define DBG_TMC_ITATBCTR0__ATBYTESS___M 0x00000F00 +#define DBG_TMC_ITATBCTR0__ATBYTESS___S 8 +#define DBG_TMC_ITATBCTR0__AFREADYS___M 0x00000002 +#define DBG_TMC_ITATBCTR0__AFREADYS___S 1 +#define DBG_TMC_ITATBCTR0__AFREADYS__LOW 0x0 +#define DBG_TMC_ITATBCTR0__AFREADYS__HIGH 0x1 +#define DBG_TMC_ITATBCTR0__ATVALIDS___M 0x00000001 +#define DBG_TMC_ITATBCTR0__ATVALIDS___S 0 +#define DBG_TMC_ITATBCTR0__ATVALIDS__LOW 0x0 +#define DBG_TMC_ITATBCTR0__ATVALIDS__HIGH 0x1 +#define DBG_TMC_ITATBCTR0___M 0x00000F03 +#define DBG_TMC_ITATBCTR0___S 0 + +#define DBG_TMC_ITCTRL (0x00BBCF00) +#define DBG_TMC_ITCTRL___RWC QCSR_REG_RW +#define DBG_TMC_ITCTRL___POR 0x00000000 +#define DBG_TMC_ITCTRL__INTEGRATION_MODE___POR 0x0 +#define DBG_TMC_ITCTRL__INTEGRATION_MODE___M 0x00000001 +#define DBG_TMC_ITCTRL__INTEGRATION_MODE___S 0 +#define DBG_TMC_ITCTRL__INTEGRATION_MODE__FUNCTIONAL_MODE 0x0 +#define DBG_TMC_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE 0x1 +#define DBG_TMC_ITCTRL___M 0x00000001 +#define DBG_TMC_ITCTRL___S 0 + +#define DBG_TMC_CLAIMSET (0x00BBCFA0) +#define DBG_TMC_CLAIMSET___RWC QCSR_REG_RW +#define DBG_TMC_CLAIMSET___POR 0x0000000F +#define DBG_TMC_CLAIMSET__CLAIMSET___POR 0xF +#define DBG_TMC_CLAIMSET__CLAIMSET___M 0x0000000F +#define DBG_TMC_CLAIMSET__CLAIMSET___S 0 +#define DBG_TMC_CLAIMSET__CLAIMSET__CLAIM_TAG_IMPLEMENTED_BITS 0xF +#define DBG_TMC_CLAIMSET___M 0x0000000F +#define DBG_TMC_CLAIMSET___S 0 + +#define DBG_TMC_CLAIMCLR (0x00BBCFA4) +#define DBG_TMC_CLAIMCLR___RWC QCSR_REG_RW +#define DBG_TMC_CLAIMCLR___POR 0x00000000 +#define DBG_TMC_CLAIMCLR__CLAIMCLR___POR 0x0 +#define DBG_TMC_CLAIMCLR__CLAIMCLR___M 0x0000000F +#define DBG_TMC_CLAIMCLR__CLAIMCLR___S 0 +#define DBG_TMC_CLAIMCLR___M 0x0000000F +#define DBG_TMC_CLAIMCLR___S 0 + +#define DBG_TMC_LAR (0x00BBCFB0) +#define DBG_TMC_LAR___RWC QCSR_REG_WO +#define DBG_TMC_LAR__ACCESS_W___M 0xFFFFFFFF +#define DBG_TMC_LAR__ACCESS_W___S 0 +#define DBG_TMC_LAR__ACCESS_W__UNLOCK 0xC5ACCE55 +#define DBG_TMC_LAR___M 0xFFFFFFFF +#define DBG_TMC_LAR___S 0 + +#define DBG_TMC_LSR (0x00BBCFB4) +#define DBG_TMC_LSR___RWC QCSR_REG_RO +#define DBG_TMC_LSR___POR 0x00000003 +#define DBG_TMC_LSR__LOCKTYPE___POR 0x0 +#define DBG_TMC_LSR__LOCKGRANT___POR 0x1 +#define DBG_TMC_LSR__LOCKEXIST___POR 0x1 +#define DBG_TMC_LSR__LOCKTYPE___M 0x00000004 +#define DBG_TMC_LSR__LOCKTYPE___S 2 +#define DBG_TMC_LSR__LOCKTYPE__ENUM_32_BIT 0x0 +#define DBG_TMC_LSR__LOCKGRANT___M 0x00000002 +#define DBG_TMC_LSR__LOCKGRANT___S 1 +#define DBG_TMC_LSR__LOCKGRANT__ACCESS_PERMITTED 0x0 +#define DBG_TMC_LSR__LOCKGRANT__DEVICE_LOCKED 0x1 +#define DBG_TMC_LSR__LOCKEXIST___M 0x00000001 +#define DBG_TMC_LSR__LOCKEXIST___S 0 +#define DBG_TMC_LSR__LOCKEXIST__LOCK_NOT_PRESENT 0x0 +#define DBG_TMC_LSR__LOCKEXIST__LOCK_PRESENT 0x1 +#define DBG_TMC_LSR___M 0x00000007 +#define DBG_TMC_LSR___S 0 + +#define DBG_TMC_AUTHSTATUS (0x00BBCFB8) +#define DBG_TMC_AUTHSTATUS___RWC QCSR_REG_RO +#define DBG_TMC_AUTHSTATUS___POR 0x00000000 +#define DBG_TMC_AUTHSTATUS__SNID___POR 0x0 +#define DBG_TMC_AUTHSTATUS__SID___POR 0x0 +#define DBG_TMC_AUTHSTATUS__NSNID___POR 0x0 +#define DBG_TMC_AUTHSTATUS__NSID___POR 0x0 +#define DBG_TMC_AUTHSTATUS__SNID___M 0x000000C0 +#define DBG_TMC_AUTHSTATUS__SNID___S 6 +#define DBG_TMC_AUTHSTATUS__SNID__ENUM_2_B00 0x0 +#define DBG_TMC_AUTHSTATUS__SID___M 0x00000030 +#define DBG_TMC_AUTHSTATUS__SID___S 4 +#define DBG_TMC_AUTHSTATUS__SID__ENUM_2_B00 0x0 +#define DBG_TMC_AUTHSTATUS__SID__ENUM_2_B10 0x2 +#define DBG_TMC_AUTHSTATUS__SID__ENUM_2_B11 0x3 +#define DBG_TMC_AUTHSTATUS__NSNID___M 0x0000000C +#define DBG_TMC_AUTHSTATUS__NSNID___S 2 +#define DBG_TMC_AUTHSTATUS__NSNID__ENUM_2_B00 0x0 +#define DBG_TMC_AUTHSTATUS__NSID___M 0x00000003 +#define DBG_TMC_AUTHSTATUS__NSID___S 0 +#define DBG_TMC_AUTHSTATUS__NSID__ENUM_2_B00 0x0 +#define DBG_TMC_AUTHSTATUS__NSID__ENUM_2_B10 0x2 +#define DBG_TMC_AUTHSTATUS__NSID__ENUM_2_B11 0x3 +#define DBG_TMC_AUTHSTATUS___M 0x000000FF +#define DBG_TMC_AUTHSTATUS___S 0 + +#define DBG_TMC_DEVID (0x00BBCFC8) +#define DBG_TMC_DEVID___RWC QCSR_REG_RO +#define DBG_TMC_DEVID___POR 0x00000580 +#define DBG_TMC_DEVID__MEMWIDTH___POR 0x5 +#define DBG_TMC_DEVID__CONFIGTYPE___POR 0x2 +#define DBG_TMC_DEVID__CLKSCHEME___POR 0x0 +#define DBG_TMC_DEVID__ATBINPORTCOUNT___POR 0x00 +#define DBG_TMC_DEVID__MEMWIDTH___M 0x00000700 +#define DBG_TMC_DEVID__MEMWIDTH___S 8 +#define DBG_TMC_DEVID__MEMWIDTH__ENUM_32_BITS 0x2 +#define DBG_TMC_DEVID__MEMWIDTH__ENUM_64_BITS 0x3 +#define DBG_TMC_DEVID__MEMWIDTH__ENUM_128_BITS 0x4 +#define DBG_TMC_DEVID__MEMWIDTH__ENUM_256_BITS 0x5 +#define DBG_TMC_DEVID__CONFIGTYPE___M 0x000000C0 +#define DBG_TMC_DEVID__CONFIGTYPE___S 6 +#define DBG_TMC_DEVID__CONFIGTYPE__TMC_CONFIGURED_AS_ETB_EMBEDDED_TRACE_BUFFER 0x0 +#define DBG_TMC_DEVID__CONFIGTYPE__TMC_CONFIGURED_AS_ETR_EMBEDDED_TRACE_ROUTER 0x1 +#define DBG_TMC_DEVID__CONFIGTYPE__TMC_CONFIGURED_AS_ETF_EMBEDDED_TRACE_FIFO 0x2 +#define DBG_TMC_DEVID__CLKSCHEME___M 0x00000020 +#define DBG_TMC_DEVID__CLKSCHEME___S 5 +#define DBG_TMC_DEVID__CLKSCHEME__TMC_RAM_SYNCHRONOUS_TO_CLK 0x0 +#define DBG_TMC_DEVID__ATBINPORTCOUNT___M 0x0000001F +#define DBG_TMC_DEVID__ATBINPORTCOUNT___S 0 +#define DBG_TMC_DEVID__ATBINPORTCOUNT__NO_MULTIPLEXING_PRESENT 0x00 +#define DBG_TMC_DEVID___M 0x000007FF +#define DBG_TMC_DEVID___S 0 + +#define DBG_TMC_DEVTYPE (0x00BBCFCC) +#define DBG_TMC_DEVTYPE___RWC QCSR_REG_RO +#define DBG_TMC_DEVTYPE___POR 0x00000032 +#define DBG_TMC_DEVTYPE__SUB_TYPE___POR 0x3 +#define DBG_TMC_DEVTYPE__MAJOR_TYPE___POR 0x2 +#define DBG_TMC_DEVTYPE__SUB_TYPE___M 0x000000F0 +#define DBG_TMC_DEVTYPE__SUB_TYPE___S 4 +#define DBG_TMC_DEVTYPE__SUB_TYPE__BUFFER 0x2 +#define DBG_TMC_DEVTYPE__SUB_TYPE__FIFO 0x3 +#define DBG_TMC_DEVTYPE__MAJOR_TYPE___M 0x0000000F +#define DBG_TMC_DEVTYPE__MAJOR_TYPE___S 0 +#define DBG_TMC_DEVTYPE__MAJOR_TYPE__TRACE_SINK 0x1 +#define DBG_TMC_DEVTYPE__MAJOR_TYPE__TRACE_LINK 0x2 +#define DBG_TMC_DEVTYPE___M 0x000000FF +#define DBG_TMC_DEVTYPE___S 0 + +#define DBG_TMC_PERIPHID0 (0x00BBCFE0) +#define DBG_TMC_PERIPHID0___RWC QCSR_REG_RO +#define DBG_TMC_PERIPHID0___POR 0x00000061 +#define DBG_TMC_PERIPHID0__PART_NUMBER_BITS7TO0___POR 0x61 +#define DBG_TMC_PERIPHID0__PART_NUMBER_BITS7TO0___M 0x000000FF +#define DBG_TMC_PERIPHID0__PART_NUMBER_BITS7TO0___S 0 +#define DBG_TMC_PERIPHID0__PART_NUMBER_BITS7TO0__CORESIGHT_TMC_PART_NUMBER_7_0 0x61 +#define DBG_TMC_PERIPHID0___M 0x000000FF +#define DBG_TMC_PERIPHID0___S 0 + +#define DBG_TMC_PERIPHID1 (0x00BBCFE4) +#define DBG_TMC_PERIPHID1___RWC QCSR_REG_RO +#define DBG_TMC_PERIPHID1___POR 0x000000B9 +#define DBG_TMC_PERIPHID1__JEP106_BITS3TO0___POR 0xB +#define DBG_TMC_PERIPHID1__PART_NUMBER_BITS11TO8___POR 0x9 +#define DBG_TMC_PERIPHID1__JEP106_BITS3TO0___M 0x000000F0 +#define DBG_TMC_PERIPHID1__JEP106_BITS3TO0___S 4 +#define DBG_TMC_PERIPHID1__JEP106_BITS3TO0__ARM_JEP106_IDENTITY_CODE_7_0 0xB +#define DBG_TMC_PERIPHID1__PART_NUMBER_BITS11TO8___M 0x0000000F +#define DBG_TMC_PERIPHID1__PART_NUMBER_BITS11TO8___S 0 +#define DBG_TMC_PERIPHID1__PART_NUMBER_BITS11TO8__CORESIGHT_TMC_PART_NUMBER_11_8 0x9 +#define DBG_TMC_PERIPHID1___M 0x000000FF +#define DBG_TMC_PERIPHID1___S 0 + +#define DBG_TMC_PERIPHID2 (0x00BBCFE8) +#define DBG_TMC_PERIPHID2___RWC QCSR_REG_RO +#define DBG_TMC_PERIPHID2___POR 0x0000001B +#define DBG_TMC_PERIPHID2__REVISION___POR 0x1 +#define DBG_TMC_PERIPHID2__JEDEC___POR 0x1 +#define DBG_TMC_PERIPHID2__JEP106_BITS6TO4___POR 0x3 +#define DBG_TMC_PERIPHID2__REVISION___M 0x000000F0 +#define DBG_TMC_PERIPHID2__REVISION___S 4 +#define DBG_TMC_PERIPHID2__REVISION__R0P1 0x1 +#define DBG_TMC_PERIPHID2__JEDEC___M 0x00000008 +#define DBG_TMC_PERIPHID2__JEDEC___S 3 +#define DBG_TMC_PERIPHID2__JEDEC__JEDEC_IDENTITY 0x1 +#define DBG_TMC_PERIPHID2__JEP106_BITS6TO4___M 0x00000007 +#define DBG_TMC_PERIPHID2__JEP106_BITS6TO4___S 0 +#define DBG_TMC_PERIPHID2__JEP106_BITS6TO4__ARM_JEP106_IDENTITY_CODE_6_4 0x3 +#define DBG_TMC_PERIPHID2___M 0x000000FF +#define DBG_TMC_PERIPHID2___S 0 + +#define DBG_TMC_PERIPHID3 (0x00BBCFEC) +#define DBG_TMC_PERIPHID3___RWC QCSR_REG_RO +#define DBG_TMC_PERIPHID3___POR 0x00000000 +#define DBG_TMC_PERIPHID3__REVAND___POR 0x0 +#define DBG_TMC_PERIPHID3__CUSTOMER_MODIFIED___POR 0x0 +#define DBG_TMC_PERIPHID3__REVAND___M 0x000000F0 +#define DBG_TMC_PERIPHID3__REVAND___S 4 +#define DBG_TMC_PERIPHID3__REVAND__NO_MODS 0x0 +#define DBG_TMC_PERIPHID3__CUSTOMER_MODIFIED___M 0x0000000F +#define DBG_TMC_PERIPHID3__CUSTOMER_MODIFIED___S 0 +#define DBG_TMC_PERIPHID3__CUSTOMER_MODIFIED__NO_MODS 0x0 +#define DBG_TMC_PERIPHID3___M 0x000000FF +#define DBG_TMC_PERIPHID3___S 0 + +#define DBG_TMC_PERIPHID4 (0x00BBCFD0) +#define DBG_TMC_PERIPHID4___RWC QCSR_REG_RO +#define DBG_TMC_PERIPHID4___POR 0x00000004 +#define DBG_TMC_PERIPHID4__FOURKB_COUNT___POR 0x0 +#define DBG_TMC_PERIPHID4__JEP106_CONT___POR 0x4 +#define DBG_TMC_PERIPHID4__FOURKB_COUNT___M 0x000000F0 +#define DBG_TMC_PERIPHID4__FOURKB_COUNT___S 4 +#define DBG_TMC_PERIPHID4__FOURKB_COUNT__ENUM_4KB 0x0 +#define DBG_TMC_PERIPHID4__JEP106_CONT___M 0x0000000F +#define DBG_TMC_PERIPHID4__JEP106_CONT___S 0 +#define DBG_TMC_PERIPHID4__JEP106_CONT__ARM_JEP106_CONTINUATION_CODE 0x4 +#define DBG_TMC_PERIPHID4___M 0x000000FF +#define DBG_TMC_PERIPHID4___S 0 + +#define DBG_TMC_PERIPHID5 (0x00BBCFD4) +#define DBG_TMC_PERIPHID5___RWC QCSR_REG_RW +#define DBG_TMC_PERIPHID5__PERIPHID5___M 0xFFFFFFFF +#define DBG_TMC_PERIPHID5__PERIPHID5___S 0 +#define DBG_TMC_PERIPHID5___M 0xFFFFFFFF +#define DBG_TMC_PERIPHID5___S 0 + +#define DBG_TMC_PERIPHID6 (0x00BBCFD8) +#define DBG_TMC_PERIPHID6___RWC QCSR_REG_RW +#define DBG_TMC_PERIPHID6__PERIPHID6___M 0xFFFFFFFF +#define DBG_TMC_PERIPHID6__PERIPHID6___S 0 +#define DBG_TMC_PERIPHID6___M 0xFFFFFFFF +#define DBG_TMC_PERIPHID6___S 0 + +#define DBG_TMC_PERIPHID7 (0x00BBCFDC) +#define DBG_TMC_PERIPHID7___RWC QCSR_REG_RW +#define DBG_TMC_PERIPHID7__PERIPHID7___M 0xFFFFFFFF +#define DBG_TMC_PERIPHID7__PERIPHID7___S 0 +#define DBG_TMC_PERIPHID7___M 0xFFFFFFFF +#define DBG_TMC_PERIPHID7___S 0 + +#define DBG_TMC_COMPID0 (0x00BBCFF0) +#define DBG_TMC_COMPID0___RWC QCSR_REG_RO +#define DBG_TMC_COMPID0___POR 0x0000000D +#define DBG_TMC_COMPID0__PREAMBLE___POR 0x0D +#define DBG_TMC_COMPID0__PREAMBLE___M 0x000000FF +#define DBG_TMC_COMPID0__PREAMBLE___S 0 +#define DBG_TMC_COMPID0__PREAMBLE__ENUM_0D 0x0D +#define DBG_TMC_COMPID0___M 0x000000FF +#define DBG_TMC_COMPID0___S 0 + +#define DBG_TMC_COMPID1 (0x00BBCFF4) +#define DBG_TMC_COMPID1___RWC QCSR_REG_RO +#define DBG_TMC_COMPID1___POR 0x00000090 +#define DBG_TMC_COMPID1__CLASS___POR 0x9 +#define DBG_TMC_COMPID1__PREAMBLE___POR 0x0 +#define DBG_TMC_COMPID1__CLASS___M 0x000000F0 +#define DBG_TMC_COMPID1__CLASS___S 4 +#define DBG_TMC_COMPID1__CLASS__CORESIGHT_COMPONENT 0x9 +#define DBG_TMC_COMPID1__PREAMBLE___M 0x0000000F +#define DBG_TMC_COMPID1__PREAMBLE___S 0 +#define DBG_TMC_COMPID1__PREAMBLE__ENUM_0 0x0 +#define DBG_TMC_COMPID1___M 0x000000FF +#define DBG_TMC_COMPID1___S 0 + +#define DBG_TMC_COMPID2 (0x00BBCFF8) +#define DBG_TMC_COMPID2___RWC QCSR_REG_RO +#define DBG_TMC_COMPID2___POR 0x00000005 +#define DBG_TMC_COMPID2__PREAMBLE___POR 0x05 +#define DBG_TMC_COMPID2__PREAMBLE___M 0x000000FF +#define DBG_TMC_COMPID2__PREAMBLE___S 0 +#define DBG_TMC_COMPID2__PREAMBLE__ENUM_05 0x05 +#define DBG_TMC_COMPID2___M 0x000000FF +#define DBG_TMC_COMPID2___S 0 + +#define DBG_TMC_COMPID3 (0x00BBCFFC) +#define DBG_TMC_COMPID3___RWC QCSR_REG_RO +#define DBG_TMC_COMPID3___POR 0x000000B1 +#define DBG_TMC_COMPID3__PREAMBLE___POR 0xB1 +#define DBG_TMC_COMPID3__PREAMBLE___M 0x000000FF +#define DBG_TMC_COMPID3__PREAMBLE___S 0 +#define DBG_TMC_COMPID3__PREAMBLE__B1 0xB1 +#define DBG_TMC_COMPID3___M 0x000000FF +#define DBG_TMC_COMPID3___S 0 + +#define DBG_OUTFUN_CTRL_REG (0x00BBE000) +#define DBG_OUTFUN_CTRL_REG___RWC QCSR_REG_RW +#define DBG_OUTFUN_CTRL_REG___POR 0x00000300 +#define DBG_OUTFUN_CTRL_REG__HT___POR 0x3 +#define DBG_OUTFUN_CTRL_REG__ENS1___POR 0x0 +#define DBG_OUTFUN_CTRL_REG__ENS0___POR 0x0 +#define DBG_OUTFUN_CTRL_REG__HT___M 0x00000F00 +#define DBG_OUTFUN_CTRL_REG__HT___S 8 +#define DBG_OUTFUN_CTRL_REG__HT__HT_0X0 0x0 +#define DBG_OUTFUN_CTRL_REG__HT__HT_0X1 0x1 +#define DBG_OUTFUN_CTRL_REG__HT__HT_0X2 0x2 +#define DBG_OUTFUN_CTRL_REG__HT__HT_0X3 0x3 +#define DBG_OUTFUN_CTRL_REG__HT__HT_0X4 0x4 +#define DBG_OUTFUN_CTRL_REG__HT__HT_0X5 0x5 +#define DBG_OUTFUN_CTRL_REG__HT__HT_0X6 0x6 +#define DBG_OUTFUN_CTRL_REG__HT__HT_0X7 0x7 +#define DBG_OUTFUN_CTRL_REG__HT__HT_0X8 0x8 +#define DBG_OUTFUN_CTRL_REG__HT__HT_0X9 0x9 +#define DBG_OUTFUN_CTRL_REG__HT__HT_0XA 0xA +#define DBG_OUTFUN_CTRL_REG__HT__HT_0XB 0xB +#define DBG_OUTFUN_CTRL_REG__HT__HT_0XC 0xC +#define DBG_OUTFUN_CTRL_REG__HT__HT_0XD 0xD +#define DBG_OUTFUN_CTRL_REG__HT__HT_0XE 0xE +#define DBG_OUTFUN_CTRL_REG__ENS1___M 0x00000002 +#define DBG_OUTFUN_CTRL_REG__ENS1___S 1 +#define DBG_OUTFUN_CTRL_REG__ENS1__ENS1_0 0x0 +#define DBG_OUTFUN_CTRL_REG__ENS1__ENS1_1 0x1 +#define DBG_OUTFUN_CTRL_REG__ENS0___M 0x00000001 +#define DBG_OUTFUN_CTRL_REG__ENS0___S 0 +#define DBG_OUTFUN_CTRL_REG__ENS0__ENS0_0 0x0 +#define DBG_OUTFUN_CTRL_REG__ENS0__ENS0_1 0x1 +#define DBG_OUTFUN_CTRL_REG___M 0x00000F03 +#define DBG_OUTFUN_CTRL_REG___S 0 + +#define DBG_OUTFUN_PRIORITY_CTRL_REG (0x00BBE004) +#define DBG_OUTFUN_PRIORITY_CTRL_REG___RWC QCSR_REG_RW +#define DBG_OUTFUN_PRIORITY_CTRL_REG___POR 0x00000000 +#define DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT1___POR 0x0 +#define DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT0___POR 0x0 +#define DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT1___M 0x00000038 +#define DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT1___S 3 +#define DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_0 0x0 +#define DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_1 0x1 +#define DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_2 0x2 +#define DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_3 0x3 +#define DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_4 0x4 +#define DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_5 0x5 +#define DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_6 0x6 +#define DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_7 0x7 +#define DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT0___M 0x00000007 +#define DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT0___S 0 +#define DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_0 0x0 +#define DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_1 0x1 +#define DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_2 0x2 +#define DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_3 0x3 +#define DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_4 0x4 +#define DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_5 0x5 +#define DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_6 0x6 +#define DBG_OUTFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_7 0x7 +#define DBG_OUTFUN_PRIORITY_CTRL_REG___M 0x0000003F +#define DBG_OUTFUN_PRIORITY_CTRL_REG___S 0 + +#define DBG_OUTFUN_ITATBDATA0 (0x00BBEEEC) +#define DBG_OUTFUN_ITATBDATA0___RWC QCSR_REG_RW +#define DBG_OUTFUN_ITATBDATA0___POR 0x00000000 +#define DBG_OUTFUN_ITATBDATA0__ATDATA127___POR 0x0 +#define DBG_OUTFUN_ITATBDATA0__ATDATA119___POR 0x0 +#define DBG_OUTFUN_ITATBDATA0__ATDATA111___POR 0x0 +#define DBG_OUTFUN_ITATBDATA0__ATDATA103___POR 0x0 +#define DBG_OUTFUN_ITATBDATA0__ATDATA95___POR 0x0 +#define DBG_OUTFUN_ITATBDATA0__ATDATA87___POR 0x0 +#define DBG_OUTFUN_ITATBDATA0__ATDATA79___POR 0x0 +#define DBG_OUTFUN_ITATBDATA0__ATDATA71___POR 0x0 +#define DBG_OUTFUN_ITATBDATA0__ATDATA63___POR 0x0 +#define DBG_OUTFUN_ITATBDATA0__ATDATA55___POR 0x0 +#define DBG_OUTFUN_ITATBDATA0__ATDATA47___POR 0x0 +#define DBG_OUTFUN_ITATBDATA0__ATDATA39___POR 0x0 +#define DBG_OUTFUN_ITATBDATA0__ATDATA31___POR 0x0 +#define DBG_OUTFUN_ITATBDATA0__ATDATAM23___POR 0x0 +#define DBG_OUTFUN_ITATBDATA0__ATDATA15___POR 0x0 +#define DBG_OUTFUN_ITATBDATA0__ATDATA7___POR 0x0 +#define DBG_OUTFUN_ITATBDATA0__ATDATA0___POR 0x0 +#define DBG_OUTFUN_ITATBDATA0__ATDATA127___M 0x00010000 +#define DBG_OUTFUN_ITATBDATA0__ATDATA127___S 16 +#define DBG_OUTFUN_ITATBDATA0__ATDATA127__ATDATA127_0 0x0 +#define DBG_OUTFUN_ITATBDATA0__ATDATA127__ATDATA127_1 0x1 +#define DBG_OUTFUN_ITATBDATA0__ATDATA119___M 0x00008000 +#define DBG_OUTFUN_ITATBDATA0__ATDATA119___S 15 +#define DBG_OUTFUN_ITATBDATA0__ATDATA119__ATDATA119_0 0x0 +#define DBG_OUTFUN_ITATBDATA0__ATDATA119__ATDATA119_1 0x1 +#define DBG_OUTFUN_ITATBDATA0__ATDATA111___M 0x00004000 +#define DBG_OUTFUN_ITATBDATA0__ATDATA111___S 14 +#define DBG_OUTFUN_ITATBDATA0__ATDATA111__ATDATA111_0 0x0 +#define DBG_OUTFUN_ITATBDATA0__ATDATA111__ATDATA111_1 0x1 +#define DBG_OUTFUN_ITATBDATA0__ATDATA103___M 0x00002000 +#define DBG_OUTFUN_ITATBDATA0__ATDATA103___S 13 +#define DBG_OUTFUN_ITATBDATA0__ATDATA103__ATDATA103_0 0x0 +#define DBG_OUTFUN_ITATBDATA0__ATDATA103__ATDATA103_1 0x1 +#define DBG_OUTFUN_ITATBDATA0__ATDATA95___M 0x00001000 +#define DBG_OUTFUN_ITATBDATA0__ATDATA95___S 12 +#define DBG_OUTFUN_ITATBDATA0__ATDATA95__ATDATA95_0 0x0 +#define DBG_OUTFUN_ITATBDATA0__ATDATA95__ATDATA95_1 0x1 +#define DBG_OUTFUN_ITATBDATA0__ATDATA87___M 0x00000800 +#define DBG_OUTFUN_ITATBDATA0__ATDATA87___S 11 +#define DBG_OUTFUN_ITATBDATA0__ATDATA87__ATDATA87_0 0x0 +#define DBG_OUTFUN_ITATBDATA0__ATDATA87__ATDATA87_1 0x1 +#define DBG_OUTFUN_ITATBDATA0__ATDATA79___M 0x00000400 +#define DBG_OUTFUN_ITATBDATA0__ATDATA79___S 10 +#define DBG_OUTFUN_ITATBDATA0__ATDATA79__ATDATA79_0 0x0 +#define DBG_OUTFUN_ITATBDATA0__ATDATA79__ATDATA79_1 0x1 +#define DBG_OUTFUN_ITATBDATA0__ATDATA71___M 0x00000200 +#define DBG_OUTFUN_ITATBDATA0__ATDATA71___S 9 +#define DBG_OUTFUN_ITATBDATA0__ATDATA71__ATDATA71_0 0x0 +#define DBG_OUTFUN_ITATBDATA0__ATDATA71__ATDATA71_1 0x1 +#define DBG_OUTFUN_ITATBDATA0__ATDATA63___M 0x00000100 +#define DBG_OUTFUN_ITATBDATA0__ATDATA63___S 8 +#define DBG_OUTFUN_ITATBDATA0__ATDATA63__ATDATA63_0 0x0 +#define DBG_OUTFUN_ITATBDATA0__ATDATA63__ATDATA63_1 0x1 +#define DBG_OUTFUN_ITATBDATA0__ATDATA55___M 0x00000080 +#define DBG_OUTFUN_ITATBDATA0__ATDATA55___S 7 +#define DBG_OUTFUN_ITATBDATA0__ATDATA55__ATDATA55_0 0x0 +#define DBG_OUTFUN_ITATBDATA0__ATDATA55__ATDATA55_1 0x1 +#define DBG_OUTFUN_ITATBDATA0__ATDATA47___M 0x00000040 +#define DBG_OUTFUN_ITATBDATA0__ATDATA47___S 6 +#define DBG_OUTFUN_ITATBDATA0__ATDATA47__ATDATA47_0 0x0 +#define DBG_OUTFUN_ITATBDATA0__ATDATA47__ATDATA47_1 0x1 +#define DBG_OUTFUN_ITATBDATA0__ATDATA39___M 0x00000020 +#define DBG_OUTFUN_ITATBDATA0__ATDATA39___S 5 +#define DBG_OUTFUN_ITATBDATA0__ATDATA39__ATDATA39_0 0x0 +#define DBG_OUTFUN_ITATBDATA0__ATDATA39__ATDATA39_1 0x1 +#define DBG_OUTFUN_ITATBDATA0__ATDATA31___M 0x00000010 +#define DBG_OUTFUN_ITATBDATA0__ATDATA31___S 4 +#define DBG_OUTFUN_ITATBDATA0__ATDATA31__ATDATA31_0 0x0 +#define DBG_OUTFUN_ITATBDATA0__ATDATA31__ATDATA31_1 0x1 +#define DBG_OUTFUN_ITATBDATA0__ATDATAM23___M 0x00000008 +#define DBG_OUTFUN_ITATBDATA0__ATDATAM23___S 3 +#define DBG_OUTFUN_ITATBDATA0__ATDATAM23__ATDATAM23_0 0x0 +#define DBG_OUTFUN_ITATBDATA0__ATDATAM23__ATDATAM23_1 0x1 +#define DBG_OUTFUN_ITATBDATA0__ATDATA15___M 0x00000004 +#define DBG_OUTFUN_ITATBDATA0__ATDATA15___S 2 +#define DBG_OUTFUN_ITATBDATA0__ATDATA15__ATDATA15_0 0x0 +#define DBG_OUTFUN_ITATBDATA0__ATDATA15__ATDATA15_1 0x1 +#define DBG_OUTFUN_ITATBDATA0__ATDATA7___M 0x00000002 +#define DBG_OUTFUN_ITATBDATA0__ATDATA7___S 1 +#define DBG_OUTFUN_ITATBDATA0__ATDATA7__ATDATA7_0 0x0 +#define DBG_OUTFUN_ITATBDATA0__ATDATA7__ATDATA7_1 0x1 +#define DBG_OUTFUN_ITATBDATA0__ATDATA0___M 0x00000001 +#define DBG_OUTFUN_ITATBDATA0__ATDATA0___S 0 +#define DBG_OUTFUN_ITATBDATA0__ATDATA0__ATDATA0_0 0x0 +#define DBG_OUTFUN_ITATBDATA0__ATDATA0__ATDATA0_1 0x1 +#define DBG_OUTFUN_ITATBDATA0___M 0x0001FFFF +#define DBG_OUTFUN_ITATBDATA0___S 0 + +#define DBG_OUTFUN_ITATBCTR2 (0x00BBEEF0) +#define DBG_OUTFUN_ITATBCTR2___RWC QCSR_REG_RW +#define DBG_OUTFUN_ITATBCTR2___POR 0x00000000 +#define DBG_OUTFUN_ITATBCTR2__AFVALID___POR 0x0 +#define DBG_OUTFUN_ITATBCTR2__ATREADY___POR 0x0 +#define DBG_OUTFUN_ITATBCTR2__AFVALID___M 0x00000002 +#define DBG_OUTFUN_ITATBCTR2__AFVALID___S 1 +#define DBG_OUTFUN_ITATBCTR2__AFVALID__AFVALID_0 0x0 +#define DBG_OUTFUN_ITATBCTR2__AFVALID__AFVALID_1 0x1 +#define DBG_OUTFUN_ITATBCTR2__ATREADY___M 0x00000001 +#define DBG_OUTFUN_ITATBCTR2__ATREADY___S 0 +#define DBG_OUTFUN_ITATBCTR2__ATREADY__ATREADY_0 0x0 +#define DBG_OUTFUN_ITATBCTR2__ATREADY__ATREADY_1 0x1 +#define DBG_OUTFUN_ITATBCTR2___M 0x00000003 +#define DBG_OUTFUN_ITATBCTR2___S 0 + +#define DBG_OUTFUN_ITATBCTR1 (0x00BBEEF4) +#define DBG_OUTFUN_ITATBCTR1___RWC QCSR_REG_RW +#define DBG_OUTFUN_ITATBCTR1__ATID___M 0x0000007F +#define DBG_OUTFUN_ITATBCTR1__ATID___S 0 +#define DBG_OUTFUN_ITATBCTR1___M 0x0000007F +#define DBG_OUTFUN_ITATBCTR1___S 0 + +#define DBG_OUTFUN_ITATBCTR0 (0x00BBEEF8) +#define DBG_OUTFUN_ITATBCTR0___RWC QCSR_REG_RW +#define DBG_OUTFUN_ITATBCTR0___POR 0x00000000 +#define DBG_OUTFUN_ITATBCTR0__ATBYTES___POR 0x0 +#define DBG_OUTFUN_ITATBCTR0__AFREADY___POR 0x0 +#define DBG_OUTFUN_ITATBCTR0__ATVALID___POR 0x0 +#define DBG_OUTFUN_ITATBCTR0__ATBYTES___M 0x00000F00 +#define DBG_OUTFUN_ITATBCTR0__ATBYTES___S 8 +#define DBG_OUTFUN_ITATBCTR0__ATBYTES__ATBYTES_0 0x0 +#define DBG_OUTFUN_ITATBCTR0__ATBYTES__ATBYTES_1 0x1 +#define DBG_OUTFUN_ITATBCTR0__AFREADY___M 0x00000002 +#define DBG_OUTFUN_ITATBCTR0__AFREADY___S 1 +#define DBG_OUTFUN_ITATBCTR0__AFREADY__AFREADY_0 0x0 +#define DBG_OUTFUN_ITATBCTR0__AFREADY__AFREADY_1 0x1 +#define DBG_OUTFUN_ITATBCTR0__ATVALID___M 0x00000001 +#define DBG_OUTFUN_ITATBCTR0__ATVALID___S 0 +#define DBG_OUTFUN_ITATBCTR0__ATVALID__ATVALID_0 0x0 +#define DBG_OUTFUN_ITATBCTR0__ATVALID__ATVALID_1 0x1 +#define DBG_OUTFUN_ITATBCTR0___M 0x00000F03 +#define DBG_OUTFUN_ITATBCTR0___S 0 + +#define DBG_OUTFUN_ITCTRL (0x00BBEF00) +#define DBG_OUTFUN_ITCTRL___RWC QCSR_REG_RW +#define DBG_OUTFUN_ITCTRL___POR 0x00000000 +#define DBG_OUTFUN_ITCTRL__INTEGRATION_MODE___POR 0x0 +#define DBG_OUTFUN_ITCTRL__INTEGRATION_MODE___M 0x00000001 +#define DBG_OUTFUN_ITCTRL__INTEGRATION_MODE___S 0 +#define DBG_OUTFUN_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE_0 0x0 +#define DBG_OUTFUN_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE_1 0x1 +#define DBG_OUTFUN_ITCTRL___M 0x00000001 +#define DBG_OUTFUN_ITCTRL___S 0 + +#define DBG_OUTFUN_CLAIMSET (0x00BBEFA0) +#define DBG_OUTFUN_CLAIMSET___RWC QCSR_REG_RW +#define DBG_OUTFUN_CLAIMSET___POR 0x0000000F +#define DBG_OUTFUN_CLAIMSET__CLAIMSET___POR 0xF +#define DBG_OUTFUN_CLAIMSET__CLAIMSET___M 0x0000000F +#define DBG_OUTFUN_CLAIMSET__CLAIMSET___S 0 +#define DBG_OUTFUN_CLAIMSET__CLAIMSET__CLAIMSET_0XF 0xF +#define DBG_OUTFUN_CLAIMSET___M 0x0000000F +#define DBG_OUTFUN_CLAIMSET___S 0 + +#define DBG_OUTFUN_CLAIMCLR (0x00BBEFA4) +#define DBG_OUTFUN_CLAIMCLR___RWC QCSR_REG_RW +#define DBG_OUTFUN_CLAIMCLR___POR 0x00000000 +#define DBG_OUTFUN_CLAIMCLR__CLAIMCLR___POR 0x0 +#define DBG_OUTFUN_CLAIMCLR__CLAIMCLR___M 0x0000000F +#define DBG_OUTFUN_CLAIMCLR__CLAIMCLR___S 0 +#define DBG_OUTFUN_CLAIMCLR___M 0x0000000F +#define DBG_OUTFUN_CLAIMCLR___S 0 + +#define DBG_OUTFUN_LOCKACCESS (0x00BBEFB0) +#define DBG_OUTFUN_LOCKACCESS___RWC QCSR_REG_WO +#define DBG_OUTFUN_LOCKACCESS__KEY___M 0xFFFFFFFF +#define DBG_OUTFUN_LOCKACCESS__KEY___S 0 +#define DBG_OUTFUN_LOCKACCESS__KEY__KEY_0XC5ACCE55 0xC5ACCE55 +#define DBG_OUTFUN_LOCKACCESS__KEY__KEY_0XDEADBEEF 0xDEADBEEF +#define DBG_OUTFUN_LOCKACCESS___M 0xFFFFFFFF +#define DBG_OUTFUN_LOCKACCESS___S 0 + +#define DBG_OUTFUN_LOCKSTATUS (0x00BBEFB4) +#define DBG_OUTFUN_LOCKSTATUS___RWC QCSR_REG_RO +#define DBG_OUTFUN_LOCKSTATUS___POR 0x00000003 +#define DBG_OUTFUN_LOCKSTATUS__NTT___POR 0x0 +#define DBG_OUTFUN_LOCKSTATUS__SLK___POR 0x1 +#define DBG_OUTFUN_LOCKSTATUS__SLI___POR 0x1 +#define DBG_OUTFUN_LOCKSTATUS__NTT___M 0x00000004 +#define DBG_OUTFUN_LOCKSTATUS__NTT___S 2 +#define DBG_OUTFUN_LOCKSTATUS__NTT__NTT_0X0 0x0 +#define DBG_OUTFUN_LOCKSTATUS__SLK___M 0x00000002 +#define DBG_OUTFUN_LOCKSTATUS__SLK___S 1 +#define DBG_OUTFUN_LOCKSTATUS__SLK__SLK_0X0 0x0 +#define DBG_OUTFUN_LOCKSTATUS__SLK__SLK_0X1 0x1 +#define DBG_OUTFUN_LOCKSTATUS__SLI___M 0x00000001 +#define DBG_OUTFUN_LOCKSTATUS__SLI___S 0 +#define DBG_OUTFUN_LOCKSTATUS__SLI__SLI_0X0 0x0 +#define DBG_OUTFUN_LOCKSTATUS__SLI__SLI_0X1 0x1 +#define DBG_OUTFUN_LOCKSTATUS___M 0x00000007 +#define DBG_OUTFUN_LOCKSTATUS___S 0 + +#define DBG_OUTFUN_AUTHSTATUS (0x00BBEFB8) +#define DBG_OUTFUN_AUTHSTATUS___RWC QCSR_REG_RO +#define DBG_OUTFUN_AUTHSTATUS___POR 0x00000000 +#define DBG_OUTFUN_AUTHSTATUS__SNID___POR 0x0 +#define DBG_OUTFUN_AUTHSTATUS__SID___POR 0x0 +#define DBG_OUTFUN_AUTHSTATUS__NSNID___POR 0x0 +#define DBG_OUTFUN_AUTHSTATUS__NSID___POR 0x0 +#define DBG_OUTFUN_AUTHSTATUS__SNID___M 0x000000C0 +#define DBG_OUTFUN_AUTHSTATUS__SNID___S 6 +#define DBG_OUTFUN_AUTHSTATUS__SNID__SNID_0X0 0x0 +#define DBG_OUTFUN_AUTHSTATUS__SID___M 0x00000030 +#define DBG_OUTFUN_AUTHSTATUS__SID___S 4 +#define DBG_OUTFUN_AUTHSTATUS__SID__SID_0X0 0x0 +#define DBG_OUTFUN_AUTHSTATUS__NSNID___M 0x0000000C +#define DBG_OUTFUN_AUTHSTATUS__NSNID___S 2 +#define DBG_OUTFUN_AUTHSTATUS__NSNID__NSNID_0X0 0x0 +#define DBG_OUTFUN_AUTHSTATUS__NSID___M 0x00000003 +#define DBG_OUTFUN_AUTHSTATUS__NSID___S 0 +#define DBG_OUTFUN_AUTHSTATUS__NSID__NSID_0X0 0x0 +#define DBG_OUTFUN_AUTHSTATUS___M 0x000000FF +#define DBG_OUTFUN_AUTHSTATUS___S 0 + +#define DBG_OUTFUN_DEVID (0x00BBEFC8) +#define DBG_OUTFUN_DEVID___RWC QCSR_REG_RO +#define DBG_OUTFUN_DEVID___POR 0x00000032 +#define DBG_OUTFUN_DEVID__SCHEME___POR 0x3 +#define DBG_OUTFUN_DEVID__PORTCOUNT___POR 0x2 +#define DBG_OUTFUN_DEVID__SCHEME___M 0x000000F0 +#define DBG_OUTFUN_DEVID__SCHEME___S 4 +#define DBG_OUTFUN_DEVID__SCHEME__SCHEME_0X3 0x3 +#define DBG_OUTFUN_DEVID__PORTCOUNT___M 0x0000000F +#define DBG_OUTFUN_DEVID__PORTCOUNT___S 0 +#define DBG_OUTFUN_DEVID__PORTCOUNT__PORTCOUNT_0X2 0x2 +#define DBG_OUTFUN_DEVID__PORTCOUNT__PORTCOUNT_0X3 0x3 +#define DBG_OUTFUN_DEVID__PORTCOUNT__PORTCOUNT_0X4 0x4 +#define DBG_OUTFUN_DEVID__PORTCOUNT__PORTCOUNT_0X5 0x5 +#define DBG_OUTFUN_DEVID__PORTCOUNT__PORTCOUNT_0X6 0x6 +#define DBG_OUTFUN_DEVID__PORTCOUNT__PORTCOUNT_0X7 0x7 +#define DBG_OUTFUN_DEVID__PORTCOUNT__PORTCOUNT_0X8 0x8 +#define DBG_OUTFUN_DEVID___M 0x000000FF +#define DBG_OUTFUN_DEVID___S 0 + +#define DBG_OUTFUN_DEVTYPE (0x00BBEFCC) +#define DBG_OUTFUN_DEVTYPE___RWC QCSR_REG_RO +#define DBG_OUTFUN_DEVTYPE___POR 0x00000012 +#define DBG_OUTFUN_DEVTYPE__SUB_TYPE___POR 0x1 +#define DBG_OUTFUN_DEVTYPE__MAJOR_TYPE___POR 0x2 +#define DBG_OUTFUN_DEVTYPE__SUB_TYPE___M 0x000000F0 +#define DBG_OUTFUN_DEVTYPE__SUB_TYPE___S 4 +#define DBG_OUTFUN_DEVTYPE__SUB_TYPE__SUB_TYPE_0X1 0x1 +#define DBG_OUTFUN_DEVTYPE__MAJOR_TYPE___M 0x0000000F +#define DBG_OUTFUN_DEVTYPE__MAJOR_TYPE___S 0 +#define DBG_OUTFUN_DEVTYPE__MAJOR_TYPE__MAJOR_TYPE_0X2 0x2 +#define DBG_OUTFUN_DEVTYPE___M 0x000000FF +#define DBG_OUTFUN_DEVTYPE___S 0 + +#define DBG_OUTFUN_PIDR0 (0x00BBEFE0) +#define DBG_OUTFUN_PIDR0___RWC QCSR_REG_RO +#define DBG_OUTFUN_PIDR0___POR 0x00000008 +#define DBG_OUTFUN_PIDR0__PART_NUMBER_BITS7TO0___POR 0x08 +#define DBG_OUTFUN_PIDR0__PART_NUMBER_BITS7TO0___M 0x000000FF +#define DBG_OUTFUN_PIDR0__PART_NUMBER_BITS7TO0___S 0 +#define DBG_OUTFUN_PIDR0__PART_NUMBER_BITS7TO0__PART_NUMBER_BITS7TO0_0X08 0x08 +#define DBG_OUTFUN_PIDR0___M 0x000000FF +#define DBG_OUTFUN_PIDR0___S 0 + +#define DBG_OUTFUN_PIDR1 (0x00BBEFE4) +#define DBG_OUTFUN_PIDR1___RWC QCSR_REG_RO +#define DBG_OUTFUN_PIDR1___POR 0x000000B9 +#define DBG_OUTFUN_PIDR1__JEP106_BITS3TO0___POR 0xB +#define DBG_OUTFUN_PIDR1__PART_NUMBER_BITS11TO8___POR 0x9 +#define DBG_OUTFUN_PIDR1__JEP106_BITS3TO0___M 0x000000F0 +#define DBG_OUTFUN_PIDR1__JEP106_BITS3TO0___S 4 +#define DBG_OUTFUN_PIDR1__JEP106_BITS3TO0__JEP106_BITS3TO0_0XB 0xB +#define DBG_OUTFUN_PIDR1__PART_NUMBER_BITS11TO8___M 0x0000000F +#define DBG_OUTFUN_PIDR1__PART_NUMBER_BITS11TO8___S 0 +#define DBG_OUTFUN_PIDR1__PART_NUMBER_BITS11TO8__PART_NUMBER_BITS11TO8_0X9 0x9 +#define DBG_OUTFUN_PIDR1___M 0x000000FF +#define DBG_OUTFUN_PIDR1___S 0 + +#define DBG_OUTFUN_PIDR2 (0x00BBEFE8) +#define DBG_OUTFUN_PIDR2___RWC QCSR_REG_RO +#define DBG_OUTFUN_PIDR2___POR 0x0000003B +#define DBG_OUTFUN_PIDR2__REVISION___POR 0x3 +#define DBG_OUTFUN_PIDR2__JEDEC___POR 0x1 +#define DBG_OUTFUN_PIDR2__JEP106_BITS6TO4___POR 0x3 +#define DBG_OUTFUN_PIDR2__REVISION___M 0x000000F0 +#define DBG_OUTFUN_PIDR2__REVISION___S 4 +#define DBG_OUTFUN_PIDR2__REVISION__REVISION_0X3 0x3 +#define DBG_OUTFUN_PIDR2__JEDEC___M 0x00000008 +#define DBG_OUTFUN_PIDR2__JEDEC___S 3 +#define DBG_OUTFUN_PIDR2__JEDEC__JEDEC_0X1 0x1 +#define DBG_OUTFUN_PIDR2__JEP106_BITS6TO4___M 0x00000007 +#define DBG_OUTFUN_PIDR2__JEP106_BITS6TO4___S 0 +#define DBG_OUTFUN_PIDR2__JEP106_BITS6TO4__JEP106_BITS6TO4_0X3 0x3 +#define DBG_OUTFUN_PIDR2___M 0x000000FF +#define DBG_OUTFUN_PIDR2___S 0 + +#define DBG_OUTFUN_PIDR3 (0x00BBEFEC) +#define DBG_OUTFUN_PIDR3___RWC QCSR_REG_RO +#define DBG_OUTFUN_PIDR3___POR 0x00000000 +#define DBG_OUTFUN_PIDR3__REVAND___POR 0x0 +#define DBG_OUTFUN_PIDR3__CUSTOMER_MODIFIED___POR 0x0 +#define DBG_OUTFUN_PIDR3__REVAND___M 0x000000F0 +#define DBG_OUTFUN_PIDR3__REVAND___S 4 +#define DBG_OUTFUN_PIDR3__REVAND__REVAND_0X0 0x0 +#define DBG_OUTFUN_PIDR3__CUSTOMER_MODIFIED___M 0x0000000F +#define DBG_OUTFUN_PIDR3__CUSTOMER_MODIFIED___S 0 +#define DBG_OUTFUN_PIDR3__CUSTOMER_MODIFIED__CUSTOMER_MODIFIED_0X0 0x0 +#define DBG_OUTFUN_PIDR3___M 0x000000FF +#define DBG_OUTFUN_PIDR3___S 0 + +#define DBG_OUTFUN_PIDR4 (0x00BBEFD0) +#define DBG_OUTFUN_PIDR4___RWC QCSR_REG_RO +#define DBG_OUTFUN_PIDR4___POR 0x00000004 +#define DBG_OUTFUN_PIDR4__FOURKB_COUNT___POR 0x0 +#define DBG_OUTFUN_PIDR4__JEP106_CONT___POR 0x4 +#define DBG_OUTFUN_PIDR4__FOURKB_COUNT___M 0x000000F0 +#define DBG_OUTFUN_PIDR4__FOURKB_COUNT___S 4 +#define DBG_OUTFUN_PIDR4__FOURKB_COUNT__FOURKB_COUNT_0X0 0x0 +#define DBG_OUTFUN_PIDR4__JEP106_CONT___M 0x0000000F +#define DBG_OUTFUN_PIDR4__JEP106_CONT___S 0 +#define DBG_OUTFUN_PIDR4__JEP106_CONT__JEP106_CONT_0X4 0x4 +#define DBG_OUTFUN_PIDR4___M 0x000000FF +#define DBG_OUTFUN_PIDR4___S 0 + +#define DBG_OUTFUN_PERIPHID5 (0x00BBEFD4) +#define DBG_OUTFUN_PERIPHID5___RWC QCSR_REG_RO +#define DBG_OUTFUN_PERIPHID5___POR 0x00000000 +#define DBG_OUTFUN_PERIPHID5__PERIPHID5___POR 0x00000000 +#define DBG_OUTFUN_PERIPHID5__PERIPHID5___M 0xFFFFFFFF +#define DBG_OUTFUN_PERIPHID5__PERIPHID5___S 0 +#define DBG_OUTFUN_PERIPHID5___M 0xFFFFFFFF +#define DBG_OUTFUN_PERIPHID5___S 0 + +#define DBG_OUTFUN_PERIPHID6 (0x00BBEFD8) +#define DBG_OUTFUN_PERIPHID6___RWC QCSR_REG_RO +#define DBG_OUTFUN_PERIPHID6___POR 0x00000000 +#define DBG_OUTFUN_PERIPHID6__PERIPHID6___POR 0x00000000 +#define DBG_OUTFUN_PERIPHID6__PERIPHID6___M 0xFFFFFFFF +#define DBG_OUTFUN_PERIPHID6__PERIPHID6___S 0 +#define DBG_OUTFUN_PERIPHID6___M 0xFFFFFFFF +#define DBG_OUTFUN_PERIPHID6___S 0 + +#define DBG_OUTFUN_PERIPHID7 (0x00BBEFDC) +#define DBG_OUTFUN_PERIPHID7___RWC QCSR_REG_RO +#define DBG_OUTFUN_PERIPHID7___POR 0x00000000 +#define DBG_OUTFUN_PERIPHID7__PERIPHID7___POR 0x00000000 +#define DBG_OUTFUN_PERIPHID7__PERIPHID7___M 0xFFFFFFFF +#define DBG_OUTFUN_PERIPHID7__PERIPHID7___S 0 +#define DBG_OUTFUN_PERIPHID7___M 0xFFFFFFFF +#define DBG_OUTFUN_PERIPHID7___S 0 + +#define DBG_OUTFUN_CID0 (0x00BBEFF0) +#define DBG_OUTFUN_CID0___RWC QCSR_REG_RO +#define DBG_OUTFUN_CID0___POR 0x0000000D +#define DBG_OUTFUN_CID0__PREAMBLE___POR 0x0D +#define DBG_OUTFUN_CID0__PREAMBLE___M 0x000000FF +#define DBG_OUTFUN_CID0__PREAMBLE___S 0 +#define DBG_OUTFUN_CID0__PREAMBLE__PREAMBLE_0X0D 0x0D +#define DBG_OUTFUN_CID0___M 0x000000FF +#define DBG_OUTFUN_CID0___S 0 + +#define DBG_OUTFUN_CID1 (0x00BBEFF4) +#define DBG_OUTFUN_CID1___RWC QCSR_REG_RO +#define DBG_OUTFUN_CID1___POR 0x00000090 +#define DBG_OUTFUN_CID1__CLASS___POR 0x9 +#define DBG_OUTFUN_CID1__PREAMBLE___POR 0x0 +#define DBG_OUTFUN_CID1__CLASS___M 0x000000F0 +#define DBG_OUTFUN_CID1__CLASS___S 4 +#define DBG_OUTFUN_CID1__CLASS__CLASS_0X9 0x9 +#define DBG_OUTFUN_CID1__PREAMBLE___M 0x0000000F +#define DBG_OUTFUN_CID1__PREAMBLE___S 0 +#define DBG_OUTFUN_CID1__PREAMBLE__PREAMBLE_0X0 0x0 +#define DBG_OUTFUN_CID1___M 0x000000FF +#define DBG_OUTFUN_CID1___S 0 + +#define DBG_OUTFUN_CID2 (0x00BBEFF8) +#define DBG_OUTFUN_CID2___RWC QCSR_REG_RO +#define DBG_OUTFUN_CID2___POR 0x00000005 +#define DBG_OUTFUN_CID2__PREAMBLE___POR 0x05 +#define DBG_OUTFUN_CID2__PREAMBLE___M 0x000000FF +#define DBG_OUTFUN_CID2__PREAMBLE___S 0 +#define DBG_OUTFUN_CID2__PREAMBLE__PREAMBLE_0X05 0x05 +#define DBG_OUTFUN_CID2___M 0x000000FF +#define DBG_OUTFUN_CID2___S 0 + +#define DBG_OUTFUN_CID3 (0x00BBEFFC) +#define DBG_OUTFUN_CID3___RWC QCSR_REG_RO +#define DBG_OUTFUN_CID3___POR 0x000000B1 +#define DBG_OUTFUN_CID3__PREAMBLE___POR 0xB1 +#define DBG_OUTFUN_CID3__PREAMBLE___M 0x000000FF +#define DBG_OUTFUN_CID3__PREAMBLE___S 0 +#define DBG_OUTFUN_CID3__PREAMBLE__PREAMBLE_0XB1 0xB1 +#define DBG_OUTFUN_CID3___M 0x000000FF +#define DBG_OUTFUN_CID3___S 0 + +#define DBG_PHYFUN_CTRL_REG (0x00BBF000) +#define DBG_PHYFUN_CTRL_REG___RWC QCSR_REG_RW +#define DBG_PHYFUN_CTRL_REG___POR 0x00000300 +#define DBG_PHYFUN_CTRL_REG__HT___POR 0x3 +#define DBG_PHYFUN_CTRL_REG__ENS1___POR 0x0 +#define DBG_PHYFUN_CTRL_REG__ENS0___POR 0x0 +#define DBG_PHYFUN_CTRL_REG__HT___M 0x00000F00 +#define DBG_PHYFUN_CTRL_REG__HT___S 8 +#define DBG_PHYFUN_CTRL_REG__HT__HT_0X0 0x0 +#define DBG_PHYFUN_CTRL_REG__HT__HT_0X1 0x1 +#define DBG_PHYFUN_CTRL_REG__HT__HT_0X2 0x2 +#define DBG_PHYFUN_CTRL_REG__HT__HT_0X3 0x3 +#define DBG_PHYFUN_CTRL_REG__HT__HT_0X4 0x4 +#define DBG_PHYFUN_CTRL_REG__HT__HT_0X5 0x5 +#define DBG_PHYFUN_CTRL_REG__HT__HT_0X6 0x6 +#define DBG_PHYFUN_CTRL_REG__HT__HT_0X7 0x7 +#define DBG_PHYFUN_CTRL_REG__HT__HT_0X8 0x8 +#define DBG_PHYFUN_CTRL_REG__HT__HT_0X9 0x9 +#define DBG_PHYFUN_CTRL_REG__HT__HT_0XA 0xA +#define DBG_PHYFUN_CTRL_REG__HT__HT_0XB 0xB +#define DBG_PHYFUN_CTRL_REG__HT__HT_0XC 0xC +#define DBG_PHYFUN_CTRL_REG__HT__HT_0XD 0xD +#define DBG_PHYFUN_CTRL_REG__HT__HT_0XE 0xE +#define DBG_PHYFUN_CTRL_REG__ENS1___M 0x00000002 +#define DBG_PHYFUN_CTRL_REG__ENS1___S 1 +#define DBG_PHYFUN_CTRL_REG__ENS1__ENS1_0 0x0 +#define DBG_PHYFUN_CTRL_REG__ENS1__ENS1_1 0x1 +#define DBG_PHYFUN_CTRL_REG__ENS0___M 0x00000001 +#define DBG_PHYFUN_CTRL_REG__ENS0___S 0 +#define DBG_PHYFUN_CTRL_REG__ENS0__ENS0_0 0x0 +#define DBG_PHYFUN_CTRL_REG__ENS0__ENS0_1 0x1 +#define DBG_PHYFUN_CTRL_REG___M 0x00000F03 +#define DBG_PHYFUN_CTRL_REG___S 0 + +#define DBG_PHYFUN_PRIORITY_CTRL_REG (0x00BBF004) +#define DBG_PHYFUN_PRIORITY_CTRL_REG___RWC QCSR_REG_RW +#define DBG_PHYFUN_PRIORITY_CTRL_REG___POR 0x00000000 +#define DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT1___POR 0x0 +#define DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT0___POR 0x0 +#define DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT1___M 0x00000038 +#define DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT1___S 3 +#define DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_0 0x0 +#define DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_1 0x1 +#define DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_2 0x2 +#define DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_3 0x3 +#define DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_4 0x4 +#define DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_5 0x5 +#define DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_6 0x6 +#define DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_7 0x7 +#define DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT0___M 0x00000007 +#define DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT0___S 0 +#define DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_0 0x0 +#define DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_1 0x1 +#define DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_2 0x2 +#define DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_3 0x3 +#define DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_4 0x4 +#define DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_5 0x5 +#define DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_6 0x6 +#define DBG_PHYFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_7 0x7 +#define DBG_PHYFUN_PRIORITY_CTRL_REG___M 0x0000003F +#define DBG_PHYFUN_PRIORITY_CTRL_REG___S 0 + +#define DBG_PHYFUN_ITATBDATA0 (0x00BBFEEC) +#define DBG_PHYFUN_ITATBDATA0___RWC QCSR_REG_RW +#define DBG_PHYFUN_ITATBDATA0___POR 0x00000000 +#define DBG_PHYFUN_ITATBDATA0__ATDATA127___POR 0x0 +#define DBG_PHYFUN_ITATBDATA0__ATDATA119___POR 0x0 +#define DBG_PHYFUN_ITATBDATA0__ATDATA111___POR 0x0 +#define DBG_PHYFUN_ITATBDATA0__ATDATA103___POR 0x0 +#define DBG_PHYFUN_ITATBDATA0__ATDATA95___POR 0x0 +#define DBG_PHYFUN_ITATBDATA0__ATDATA87___POR 0x0 +#define DBG_PHYFUN_ITATBDATA0__ATDATA79___POR 0x0 +#define DBG_PHYFUN_ITATBDATA0__ATDATA71___POR 0x0 +#define DBG_PHYFUN_ITATBDATA0__ATDATA63___POR 0x0 +#define DBG_PHYFUN_ITATBDATA0__ATDATA55___POR 0x0 +#define DBG_PHYFUN_ITATBDATA0__ATDATA47___POR 0x0 +#define DBG_PHYFUN_ITATBDATA0__ATDATA39___POR 0x0 +#define DBG_PHYFUN_ITATBDATA0__ATDATA31___POR 0x0 +#define DBG_PHYFUN_ITATBDATA0__ATDATAM23___POR 0x0 +#define DBG_PHYFUN_ITATBDATA0__ATDATA15___POR 0x0 +#define DBG_PHYFUN_ITATBDATA0__ATDATA7___POR 0x0 +#define DBG_PHYFUN_ITATBDATA0__ATDATA0___POR 0x0 +#define DBG_PHYFUN_ITATBDATA0__ATDATA127___M 0x00010000 +#define DBG_PHYFUN_ITATBDATA0__ATDATA127___S 16 +#define DBG_PHYFUN_ITATBDATA0__ATDATA127__ATDATA127_0 0x0 +#define DBG_PHYFUN_ITATBDATA0__ATDATA127__ATDATA127_1 0x1 +#define DBG_PHYFUN_ITATBDATA0__ATDATA119___M 0x00008000 +#define DBG_PHYFUN_ITATBDATA0__ATDATA119___S 15 +#define DBG_PHYFUN_ITATBDATA0__ATDATA119__ATDATA119_0 0x0 +#define DBG_PHYFUN_ITATBDATA0__ATDATA119__ATDATA119_1 0x1 +#define DBG_PHYFUN_ITATBDATA0__ATDATA111___M 0x00004000 +#define DBG_PHYFUN_ITATBDATA0__ATDATA111___S 14 +#define DBG_PHYFUN_ITATBDATA0__ATDATA111__ATDATA111_0 0x0 +#define DBG_PHYFUN_ITATBDATA0__ATDATA111__ATDATA111_1 0x1 +#define DBG_PHYFUN_ITATBDATA0__ATDATA103___M 0x00002000 +#define DBG_PHYFUN_ITATBDATA0__ATDATA103___S 13 +#define DBG_PHYFUN_ITATBDATA0__ATDATA103__ATDATA103_0 0x0 +#define DBG_PHYFUN_ITATBDATA0__ATDATA103__ATDATA103_1 0x1 +#define DBG_PHYFUN_ITATBDATA0__ATDATA95___M 0x00001000 +#define DBG_PHYFUN_ITATBDATA0__ATDATA95___S 12 +#define DBG_PHYFUN_ITATBDATA0__ATDATA95__ATDATA95_0 0x0 +#define DBG_PHYFUN_ITATBDATA0__ATDATA95__ATDATA95_1 0x1 +#define DBG_PHYFUN_ITATBDATA0__ATDATA87___M 0x00000800 +#define DBG_PHYFUN_ITATBDATA0__ATDATA87___S 11 +#define DBG_PHYFUN_ITATBDATA0__ATDATA87__ATDATA87_0 0x0 +#define DBG_PHYFUN_ITATBDATA0__ATDATA87__ATDATA87_1 0x1 +#define DBG_PHYFUN_ITATBDATA0__ATDATA79___M 0x00000400 +#define DBG_PHYFUN_ITATBDATA0__ATDATA79___S 10 +#define DBG_PHYFUN_ITATBDATA0__ATDATA79__ATDATA79_0 0x0 +#define DBG_PHYFUN_ITATBDATA0__ATDATA79__ATDATA79_1 0x1 +#define DBG_PHYFUN_ITATBDATA0__ATDATA71___M 0x00000200 +#define DBG_PHYFUN_ITATBDATA0__ATDATA71___S 9 +#define DBG_PHYFUN_ITATBDATA0__ATDATA71__ATDATA71_0 0x0 +#define DBG_PHYFUN_ITATBDATA0__ATDATA71__ATDATA71_1 0x1 +#define DBG_PHYFUN_ITATBDATA0__ATDATA63___M 0x00000100 +#define DBG_PHYFUN_ITATBDATA0__ATDATA63___S 8 +#define DBG_PHYFUN_ITATBDATA0__ATDATA63__ATDATA63_0 0x0 +#define DBG_PHYFUN_ITATBDATA0__ATDATA63__ATDATA63_1 0x1 +#define DBG_PHYFUN_ITATBDATA0__ATDATA55___M 0x00000080 +#define DBG_PHYFUN_ITATBDATA0__ATDATA55___S 7 +#define DBG_PHYFUN_ITATBDATA0__ATDATA55__ATDATA55_0 0x0 +#define DBG_PHYFUN_ITATBDATA0__ATDATA55__ATDATA55_1 0x1 +#define DBG_PHYFUN_ITATBDATA0__ATDATA47___M 0x00000040 +#define DBG_PHYFUN_ITATBDATA0__ATDATA47___S 6 +#define DBG_PHYFUN_ITATBDATA0__ATDATA47__ATDATA47_0 0x0 +#define DBG_PHYFUN_ITATBDATA0__ATDATA47__ATDATA47_1 0x1 +#define DBG_PHYFUN_ITATBDATA0__ATDATA39___M 0x00000020 +#define DBG_PHYFUN_ITATBDATA0__ATDATA39___S 5 +#define DBG_PHYFUN_ITATBDATA0__ATDATA39__ATDATA39_0 0x0 +#define DBG_PHYFUN_ITATBDATA0__ATDATA39__ATDATA39_1 0x1 +#define DBG_PHYFUN_ITATBDATA0__ATDATA31___M 0x00000010 +#define DBG_PHYFUN_ITATBDATA0__ATDATA31___S 4 +#define DBG_PHYFUN_ITATBDATA0__ATDATA31__ATDATA31_0 0x0 +#define DBG_PHYFUN_ITATBDATA0__ATDATA31__ATDATA31_1 0x1 +#define DBG_PHYFUN_ITATBDATA0__ATDATAM23___M 0x00000008 +#define DBG_PHYFUN_ITATBDATA0__ATDATAM23___S 3 +#define DBG_PHYFUN_ITATBDATA0__ATDATAM23__ATDATAM23_0 0x0 +#define DBG_PHYFUN_ITATBDATA0__ATDATAM23__ATDATAM23_1 0x1 +#define DBG_PHYFUN_ITATBDATA0__ATDATA15___M 0x00000004 +#define DBG_PHYFUN_ITATBDATA0__ATDATA15___S 2 +#define DBG_PHYFUN_ITATBDATA0__ATDATA15__ATDATA15_0 0x0 +#define DBG_PHYFUN_ITATBDATA0__ATDATA15__ATDATA15_1 0x1 +#define DBG_PHYFUN_ITATBDATA0__ATDATA7___M 0x00000002 +#define DBG_PHYFUN_ITATBDATA0__ATDATA7___S 1 +#define DBG_PHYFUN_ITATBDATA0__ATDATA7__ATDATA7_0 0x0 +#define DBG_PHYFUN_ITATBDATA0__ATDATA7__ATDATA7_1 0x1 +#define DBG_PHYFUN_ITATBDATA0__ATDATA0___M 0x00000001 +#define DBG_PHYFUN_ITATBDATA0__ATDATA0___S 0 +#define DBG_PHYFUN_ITATBDATA0__ATDATA0__ATDATA0_0 0x0 +#define DBG_PHYFUN_ITATBDATA0__ATDATA0__ATDATA0_1 0x1 +#define DBG_PHYFUN_ITATBDATA0___M 0x0001FFFF +#define DBG_PHYFUN_ITATBDATA0___S 0 + +#define DBG_PHYFUN_ITATBCTR2 (0x00BBFEF0) +#define DBG_PHYFUN_ITATBCTR2___RWC QCSR_REG_RW +#define DBG_PHYFUN_ITATBCTR2___POR 0x00000000 +#define DBG_PHYFUN_ITATBCTR2__AFVALID___POR 0x0 +#define DBG_PHYFUN_ITATBCTR2__ATREADY___POR 0x0 +#define DBG_PHYFUN_ITATBCTR2__AFVALID___M 0x00000002 +#define DBG_PHYFUN_ITATBCTR2__AFVALID___S 1 +#define DBG_PHYFUN_ITATBCTR2__AFVALID__AFVALID_0 0x0 +#define DBG_PHYFUN_ITATBCTR2__AFVALID__AFVALID_1 0x1 +#define DBG_PHYFUN_ITATBCTR2__ATREADY___M 0x00000001 +#define DBG_PHYFUN_ITATBCTR2__ATREADY___S 0 +#define DBG_PHYFUN_ITATBCTR2__ATREADY__ATREADY_0 0x0 +#define DBG_PHYFUN_ITATBCTR2__ATREADY__ATREADY_1 0x1 +#define DBG_PHYFUN_ITATBCTR2___M 0x00000003 +#define DBG_PHYFUN_ITATBCTR2___S 0 + +#define DBG_PHYFUN_ITATBCTR1 (0x00BBFEF4) +#define DBG_PHYFUN_ITATBCTR1___RWC QCSR_REG_RW +#define DBG_PHYFUN_ITATBCTR1__ATID___M 0x0000007F +#define DBG_PHYFUN_ITATBCTR1__ATID___S 0 +#define DBG_PHYFUN_ITATBCTR1___M 0x0000007F +#define DBG_PHYFUN_ITATBCTR1___S 0 + +#define DBG_PHYFUN_ITATBCTR0 (0x00BBFEF8) +#define DBG_PHYFUN_ITATBCTR0___RWC QCSR_REG_RW +#define DBG_PHYFUN_ITATBCTR0___POR 0x00000000 +#define DBG_PHYFUN_ITATBCTR0__ATBYTES___POR 0x0 +#define DBG_PHYFUN_ITATBCTR0__AFREADY___POR 0x0 +#define DBG_PHYFUN_ITATBCTR0__ATVALID___POR 0x0 +#define DBG_PHYFUN_ITATBCTR0__ATBYTES___M 0x00000F00 +#define DBG_PHYFUN_ITATBCTR0__ATBYTES___S 8 +#define DBG_PHYFUN_ITATBCTR0__ATBYTES__ATBYTES_0 0x0 +#define DBG_PHYFUN_ITATBCTR0__ATBYTES__ATBYTES_1 0x1 +#define DBG_PHYFUN_ITATBCTR0__AFREADY___M 0x00000002 +#define DBG_PHYFUN_ITATBCTR0__AFREADY___S 1 +#define DBG_PHYFUN_ITATBCTR0__AFREADY__AFREADY_0 0x0 +#define DBG_PHYFUN_ITATBCTR0__AFREADY__AFREADY_1 0x1 +#define DBG_PHYFUN_ITATBCTR0__ATVALID___M 0x00000001 +#define DBG_PHYFUN_ITATBCTR0__ATVALID___S 0 +#define DBG_PHYFUN_ITATBCTR0__ATVALID__ATVALID_0 0x0 +#define DBG_PHYFUN_ITATBCTR0__ATVALID__ATVALID_1 0x1 +#define DBG_PHYFUN_ITATBCTR0___M 0x00000F03 +#define DBG_PHYFUN_ITATBCTR0___S 0 + +#define DBG_PHYFUN_ITCTRL (0x00BBFF00) +#define DBG_PHYFUN_ITCTRL___RWC QCSR_REG_RW +#define DBG_PHYFUN_ITCTRL___POR 0x00000000 +#define DBG_PHYFUN_ITCTRL__INTEGRATION_MODE___POR 0x0 +#define DBG_PHYFUN_ITCTRL__INTEGRATION_MODE___M 0x00000001 +#define DBG_PHYFUN_ITCTRL__INTEGRATION_MODE___S 0 +#define DBG_PHYFUN_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE_0 0x0 +#define DBG_PHYFUN_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE_1 0x1 +#define DBG_PHYFUN_ITCTRL___M 0x00000001 +#define DBG_PHYFUN_ITCTRL___S 0 + +#define DBG_PHYFUN_CLAIMSET (0x00BBFFA0) +#define DBG_PHYFUN_CLAIMSET___RWC QCSR_REG_RW +#define DBG_PHYFUN_CLAIMSET___POR 0x0000000F +#define DBG_PHYFUN_CLAIMSET__CLAIMSET___POR 0xF +#define DBG_PHYFUN_CLAIMSET__CLAIMSET___M 0x0000000F +#define DBG_PHYFUN_CLAIMSET__CLAIMSET___S 0 +#define DBG_PHYFUN_CLAIMSET__CLAIMSET__CLAIMSET_0XF 0xF +#define DBG_PHYFUN_CLAIMSET___M 0x0000000F +#define DBG_PHYFUN_CLAIMSET___S 0 + +#define DBG_PHYFUN_CLAIMCLR (0x00BBFFA4) +#define DBG_PHYFUN_CLAIMCLR___RWC QCSR_REG_RW +#define DBG_PHYFUN_CLAIMCLR___POR 0x00000000 +#define DBG_PHYFUN_CLAIMCLR__CLAIMCLR___POR 0x0 +#define DBG_PHYFUN_CLAIMCLR__CLAIMCLR___M 0x0000000F +#define DBG_PHYFUN_CLAIMCLR__CLAIMCLR___S 0 +#define DBG_PHYFUN_CLAIMCLR___M 0x0000000F +#define DBG_PHYFUN_CLAIMCLR___S 0 + +#define DBG_PHYFUN_LOCKACCESS (0x00BBFFB0) +#define DBG_PHYFUN_LOCKACCESS___RWC QCSR_REG_WO +#define DBG_PHYFUN_LOCKACCESS__KEY___M 0xFFFFFFFF +#define DBG_PHYFUN_LOCKACCESS__KEY___S 0 +#define DBG_PHYFUN_LOCKACCESS__KEY__KEY_0XC5ACCE55 0xC5ACCE55 +#define DBG_PHYFUN_LOCKACCESS__KEY__KEY_0XDEADBEEF 0xDEADBEEF +#define DBG_PHYFUN_LOCKACCESS___M 0xFFFFFFFF +#define DBG_PHYFUN_LOCKACCESS___S 0 + +#define DBG_PHYFUN_LOCKSTATUS (0x00BBFFB4) +#define DBG_PHYFUN_LOCKSTATUS___RWC QCSR_REG_RO +#define DBG_PHYFUN_LOCKSTATUS___POR 0x00000003 +#define DBG_PHYFUN_LOCKSTATUS__NTT___POR 0x0 +#define DBG_PHYFUN_LOCKSTATUS__SLK___POR 0x1 +#define DBG_PHYFUN_LOCKSTATUS__SLI___POR 0x1 +#define DBG_PHYFUN_LOCKSTATUS__NTT___M 0x00000004 +#define DBG_PHYFUN_LOCKSTATUS__NTT___S 2 +#define DBG_PHYFUN_LOCKSTATUS__NTT__NTT_0X0 0x0 +#define DBG_PHYFUN_LOCKSTATUS__SLK___M 0x00000002 +#define DBG_PHYFUN_LOCKSTATUS__SLK___S 1 +#define DBG_PHYFUN_LOCKSTATUS__SLK__SLK_0X0 0x0 +#define DBG_PHYFUN_LOCKSTATUS__SLK__SLK_0X1 0x1 +#define DBG_PHYFUN_LOCKSTATUS__SLI___M 0x00000001 +#define DBG_PHYFUN_LOCKSTATUS__SLI___S 0 +#define DBG_PHYFUN_LOCKSTATUS__SLI__SLI_0X0 0x0 +#define DBG_PHYFUN_LOCKSTATUS__SLI__SLI_0X1 0x1 +#define DBG_PHYFUN_LOCKSTATUS___M 0x00000007 +#define DBG_PHYFUN_LOCKSTATUS___S 0 + +#define DBG_PHYFUN_AUTHSTATUS (0x00BBFFB8) +#define DBG_PHYFUN_AUTHSTATUS___RWC QCSR_REG_RO +#define DBG_PHYFUN_AUTHSTATUS___POR 0x00000000 +#define DBG_PHYFUN_AUTHSTATUS__SNID___POR 0x0 +#define DBG_PHYFUN_AUTHSTATUS__SID___POR 0x0 +#define DBG_PHYFUN_AUTHSTATUS__NSNID___POR 0x0 +#define DBG_PHYFUN_AUTHSTATUS__NSID___POR 0x0 +#define DBG_PHYFUN_AUTHSTATUS__SNID___M 0x000000C0 +#define DBG_PHYFUN_AUTHSTATUS__SNID___S 6 +#define DBG_PHYFUN_AUTHSTATUS__SNID__SNID_0X0 0x0 +#define DBG_PHYFUN_AUTHSTATUS__SID___M 0x00000030 +#define DBG_PHYFUN_AUTHSTATUS__SID___S 4 +#define DBG_PHYFUN_AUTHSTATUS__SID__SID_0X0 0x0 +#define DBG_PHYFUN_AUTHSTATUS__NSNID___M 0x0000000C +#define DBG_PHYFUN_AUTHSTATUS__NSNID___S 2 +#define DBG_PHYFUN_AUTHSTATUS__NSNID__NSNID_0X0 0x0 +#define DBG_PHYFUN_AUTHSTATUS__NSID___M 0x00000003 +#define DBG_PHYFUN_AUTHSTATUS__NSID___S 0 +#define DBG_PHYFUN_AUTHSTATUS__NSID__NSID_0X0 0x0 +#define DBG_PHYFUN_AUTHSTATUS___M 0x000000FF +#define DBG_PHYFUN_AUTHSTATUS___S 0 + +#define DBG_PHYFUN_DEVID (0x00BBFFC8) +#define DBG_PHYFUN_DEVID___RWC QCSR_REG_RO +#define DBG_PHYFUN_DEVID___POR 0x00000032 +#define DBG_PHYFUN_DEVID__SCHEME___POR 0x3 +#define DBG_PHYFUN_DEVID__PORTCOUNT___POR 0x2 +#define DBG_PHYFUN_DEVID__SCHEME___M 0x000000F0 +#define DBG_PHYFUN_DEVID__SCHEME___S 4 +#define DBG_PHYFUN_DEVID__SCHEME__SCHEME_0X3 0x3 +#define DBG_PHYFUN_DEVID__PORTCOUNT___M 0x0000000F +#define DBG_PHYFUN_DEVID__PORTCOUNT___S 0 +#define DBG_PHYFUN_DEVID__PORTCOUNT__PORTCOUNT_0X2 0x2 +#define DBG_PHYFUN_DEVID__PORTCOUNT__PORTCOUNT_0X3 0x3 +#define DBG_PHYFUN_DEVID__PORTCOUNT__PORTCOUNT_0X4 0x4 +#define DBG_PHYFUN_DEVID__PORTCOUNT__PORTCOUNT_0X5 0x5 +#define DBG_PHYFUN_DEVID__PORTCOUNT__PORTCOUNT_0X6 0x6 +#define DBG_PHYFUN_DEVID__PORTCOUNT__PORTCOUNT_0X7 0x7 +#define DBG_PHYFUN_DEVID__PORTCOUNT__PORTCOUNT_0X8 0x8 +#define DBG_PHYFUN_DEVID___M 0x000000FF +#define DBG_PHYFUN_DEVID___S 0 + +#define DBG_PHYFUN_DEVTYPE (0x00BBFFCC) +#define DBG_PHYFUN_DEVTYPE___RWC QCSR_REG_RO +#define DBG_PHYFUN_DEVTYPE___POR 0x00000012 +#define DBG_PHYFUN_DEVTYPE__SUB_TYPE___POR 0x1 +#define DBG_PHYFUN_DEVTYPE__MAJOR_TYPE___POR 0x2 +#define DBG_PHYFUN_DEVTYPE__SUB_TYPE___M 0x000000F0 +#define DBG_PHYFUN_DEVTYPE__SUB_TYPE___S 4 +#define DBG_PHYFUN_DEVTYPE__SUB_TYPE__SUB_TYPE_0X1 0x1 +#define DBG_PHYFUN_DEVTYPE__MAJOR_TYPE___M 0x0000000F +#define DBG_PHYFUN_DEVTYPE__MAJOR_TYPE___S 0 +#define DBG_PHYFUN_DEVTYPE__MAJOR_TYPE__MAJOR_TYPE_0X2 0x2 +#define DBG_PHYFUN_DEVTYPE___M 0x000000FF +#define DBG_PHYFUN_DEVTYPE___S 0 + +#define DBG_PHYFUN_PIDR0 (0x00BBFFE0) +#define DBG_PHYFUN_PIDR0___RWC QCSR_REG_RO +#define DBG_PHYFUN_PIDR0___POR 0x00000008 +#define DBG_PHYFUN_PIDR0__PART_NUMBER_BITS7TO0___POR 0x08 +#define DBG_PHYFUN_PIDR0__PART_NUMBER_BITS7TO0___M 0x000000FF +#define DBG_PHYFUN_PIDR0__PART_NUMBER_BITS7TO0___S 0 +#define DBG_PHYFUN_PIDR0__PART_NUMBER_BITS7TO0__PART_NUMBER_BITS7TO0_0X08 0x08 +#define DBG_PHYFUN_PIDR0___M 0x000000FF +#define DBG_PHYFUN_PIDR0___S 0 + +#define DBG_PHYFUN_PIDR1 (0x00BBFFE4) +#define DBG_PHYFUN_PIDR1___RWC QCSR_REG_RO +#define DBG_PHYFUN_PIDR1___POR 0x000000B9 +#define DBG_PHYFUN_PIDR1__JEP106_BITS3TO0___POR 0xB +#define DBG_PHYFUN_PIDR1__PART_NUMBER_BITS11TO8___POR 0x9 +#define DBG_PHYFUN_PIDR1__JEP106_BITS3TO0___M 0x000000F0 +#define DBG_PHYFUN_PIDR1__JEP106_BITS3TO0___S 4 +#define DBG_PHYFUN_PIDR1__JEP106_BITS3TO0__JEP106_BITS3TO0_0XB 0xB +#define DBG_PHYFUN_PIDR1__PART_NUMBER_BITS11TO8___M 0x0000000F +#define DBG_PHYFUN_PIDR1__PART_NUMBER_BITS11TO8___S 0 +#define DBG_PHYFUN_PIDR1__PART_NUMBER_BITS11TO8__PART_NUMBER_BITS11TO8_0X9 0x9 +#define DBG_PHYFUN_PIDR1___M 0x000000FF +#define DBG_PHYFUN_PIDR1___S 0 + +#define DBG_PHYFUN_PIDR2 (0x00BBFFE8) +#define DBG_PHYFUN_PIDR2___RWC QCSR_REG_RO +#define DBG_PHYFUN_PIDR2___POR 0x0000003B +#define DBG_PHYFUN_PIDR2__REVISION___POR 0x3 +#define DBG_PHYFUN_PIDR2__JEDEC___POR 0x1 +#define DBG_PHYFUN_PIDR2__JEP106_BITS6TO4___POR 0x3 +#define DBG_PHYFUN_PIDR2__REVISION___M 0x000000F0 +#define DBG_PHYFUN_PIDR2__REVISION___S 4 +#define DBG_PHYFUN_PIDR2__REVISION__REVISION_0X3 0x3 +#define DBG_PHYFUN_PIDR2__JEDEC___M 0x00000008 +#define DBG_PHYFUN_PIDR2__JEDEC___S 3 +#define DBG_PHYFUN_PIDR2__JEDEC__JEDEC_0X1 0x1 +#define DBG_PHYFUN_PIDR2__JEP106_BITS6TO4___M 0x00000007 +#define DBG_PHYFUN_PIDR2__JEP106_BITS6TO4___S 0 +#define DBG_PHYFUN_PIDR2__JEP106_BITS6TO4__JEP106_BITS6TO4_0X3 0x3 +#define DBG_PHYFUN_PIDR2___M 0x000000FF +#define DBG_PHYFUN_PIDR2___S 0 + +#define DBG_PHYFUN_PIDR3 (0x00BBFFEC) +#define DBG_PHYFUN_PIDR3___RWC QCSR_REG_RO +#define DBG_PHYFUN_PIDR3___POR 0x00000000 +#define DBG_PHYFUN_PIDR3__REVAND___POR 0x0 +#define DBG_PHYFUN_PIDR3__CUSTOMER_MODIFIED___POR 0x0 +#define DBG_PHYFUN_PIDR3__REVAND___M 0x000000F0 +#define DBG_PHYFUN_PIDR3__REVAND___S 4 +#define DBG_PHYFUN_PIDR3__REVAND__REVAND_0X0 0x0 +#define DBG_PHYFUN_PIDR3__CUSTOMER_MODIFIED___M 0x0000000F +#define DBG_PHYFUN_PIDR3__CUSTOMER_MODIFIED___S 0 +#define DBG_PHYFUN_PIDR3__CUSTOMER_MODIFIED__CUSTOMER_MODIFIED_0X0 0x0 +#define DBG_PHYFUN_PIDR3___M 0x000000FF +#define DBG_PHYFUN_PIDR3___S 0 + +#define DBG_PHYFUN_PIDR4 (0x00BBFFD0) +#define DBG_PHYFUN_PIDR4___RWC QCSR_REG_RO +#define DBG_PHYFUN_PIDR4___POR 0x00000004 +#define DBG_PHYFUN_PIDR4__FOURKB_COUNT___POR 0x0 +#define DBG_PHYFUN_PIDR4__JEP106_CONT___POR 0x4 +#define DBG_PHYFUN_PIDR4__FOURKB_COUNT___M 0x000000F0 +#define DBG_PHYFUN_PIDR4__FOURKB_COUNT___S 4 +#define DBG_PHYFUN_PIDR4__FOURKB_COUNT__FOURKB_COUNT_0X0 0x0 +#define DBG_PHYFUN_PIDR4__JEP106_CONT___M 0x0000000F +#define DBG_PHYFUN_PIDR4__JEP106_CONT___S 0 +#define DBG_PHYFUN_PIDR4__JEP106_CONT__JEP106_CONT_0X4 0x4 +#define DBG_PHYFUN_PIDR4___M 0x000000FF +#define DBG_PHYFUN_PIDR4___S 0 + +#define DBG_PHYFUN_PERIPHID5 (0x00BBFFD4) +#define DBG_PHYFUN_PERIPHID5___RWC QCSR_REG_RO +#define DBG_PHYFUN_PERIPHID5___POR 0x00000000 +#define DBG_PHYFUN_PERIPHID5__PERIPHID5___POR 0x00000000 +#define DBG_PHYFUN_PERIPHID5__PERIPHID5___M 0xFFFFFFFF +#define DBG_PHYFUN_PERIPHID5__PERIPHID5___S 0 +#define DBG_PHYFUN_PERIPHID5___M 0xFFFFFFFF +#define DBG_PHYFUN_PERIPHID5___S 0 + +#define DBG_PHYFUN_PERIPHID6 (0x00BBFFD8) +#define DBG_PHYFUN_PERIPHID6___RWC QCSR_REG_RO +#define DBG_PHYFUN_PERIPHID6___POR 0x00000000 +#define DBG_PHYFUN_PERIPHID6__PERIPHID6___POR 0x00000000 +#define DBG_PHYFUN_PERIPHID6__PERIPHID6___M 0xFFFFFFFF +#define DBG_PHYFUN_PERIPHID6__PERIPHID6___S 0 +#define DBG_PHYFUN_PERIPHID6___M 0xFFFFFFFF +#define DBG_PHYFUN_PERIPHID6___S 0 + +#define DBG_PHYFUN_PERIPHID7 (0x00BBFFDC) +#define DBG_PHYFUN_PERIPHID7___RWC QCSR_REG_RO +#define DBG_PHYFUN_PERIPHID7___POR 0x00000000 +#define DBG_PHYFUN_PERIPHID7__PERIPHID7___POR 0x00000000 +#define DBG_PHYFUN_PERIPHID7__PERIPHID7___M 0xFFFFFFFF +#define DBG_PHYFUN_PERIPHID7__PERIPHID7___S 0 +#define DBG_PHYFUN_PERIPHID7___M 0xFFFFFFFF +#define DBG_PHYFUN_PERIPHID7___S 0 + +#define DBG_PHYFUN_CID0 (0x00BBFFF0) +#define DBG_PHYFUN_CID0___RWC QCSR_REG_RO +#define DBG_PHYFUN_CID0___POR 0x0000000D +#define DBG_PHYFUN_CID0__PREAMBLE___POR 0x0D +#define DBG_PHYFUN_CID0__PREAMBLE___M 0x000000FF +#define DBG_PHYFUN_CID0__PREAMBLE___S 0 +#define DBG_PHYFUN_CID0__PREAMBLE__PREAMBLE_0X0D 0x0D +#define DBG_PHYFUN_CID0___M 0x000000FF +#define DBG_PHYFUN_CID0___S 0 + +#define DBG_PHYFUN_CID1 (0x00BBFFF4) +#define DBG_PHYFUN_CID1___RWC QCSR_REG_RO +#define DBG_PHYFUN_CID1___POR 0x00000090 +#define DBG_PHYFUN_CID1__CLASS___POR 0x9 +#define DBG_PHYFUN_CID1__PREAMBLE___POR 0x0 +#define DBG_PHYFUN_CID1__CLASS___M 0x000000F0 +#define DBG_PHYFUN_CID1__CLASS___S 4 +#define DBG_PHYFUN_CID1__CLASS__CLASS_0X9 0x9 +#define DBG_PHYFUN_CID1__PREAMBLE___M 0x0000000F +#define DBG_PHYFUN_CID1__PREAMBLE___S 0 +#define DBG_PHYFUN_CID1__PREAMBLE__PREAMBLE_0X0 0x0 +#define DBG_PHYFUN_CID1___M 0x000000FF +#define DBG_PHYFUN_CID1___S 0 + +#define DBG_PHYFUN_CID2 (0x00BBFFF8) +#define DBG_PHYFUN_CID2___RWC QCSR_REG_RO +#define DBG_PHYFUN_CID2___POR 0x00000005 +#define DBG_PHYFUN_CID2__PREAMBLE___POR 0x05 +#define DBG_PHYFUN_CID2__PREAMBLE___M 0x000000FF +#define DBG_PHYFUN_CID2__PREAMBLE___S 0 +#define DBG_PHYFUN_CID2__PREAMBLE__PREAMBLE_0X05 0x05 +#define DBG_PHYFUN_CID2___M 0x000000FF +#define DBG_PHYFUN_CID2___S 0 + +#define DBG_PHYFUN_CID3 (0x00BBFFFC) +#define DBG_PHYFUN_CID3___RWC QCSR_REG_RO +#define DBG_PHYFUN_CID3___POR 0x000000B1 +#define DBG_PHYFUN_CID3__PREAMBLE___POR 0xB1 +#define DBG_PHYFUN_CID3__PREAMBLE___M 0x000000FF +#define DBG_PHYFUN_CID3__PREAMBLE___S 0 +#define DBG_PHYFUN_CID3__PREAMBLE__PREAMBLE_0XB1 0xB1 +#define DBG_PHYFUN_CID3___M 0x000000FF +#define DBG_PHYFUN_CID3___S 0 + +#define DBG_OUTDMUX_ATID_EN0 (0x00BC0000) +#define DBG_OUTDMUX_ATID_EN0___RWC QCSR_REG_RW +#define DBG_OUTDMUX_ATID_EN0___POR 0xFFFFFFFF +#define DBG_OUTDMUX_ATID_EN0__ATID31_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID30_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID29_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID28_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID27_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID26_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID25_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID24_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID23_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID22_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID21_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID20_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID19_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID18_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID17_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID16_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID15_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID14_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID13_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID12_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID11_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID10_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID9_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID8_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID7_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID6_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID5_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID4_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID3_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID2_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID1_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID0_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID31_EN___M 0x80000000 +#define DBG_OUTDMUX_ATID_EN0__ATID31_EN___S 31 +#define DBG_OUTDMUX_ATID_EN0__ATID31_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN0__ATID31_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID30_EN___M 0x40000000 +#define DBG_OUTDMUX_ATID_EN0__ATID30_EN___S 30 +#define DBG_OUTDMUX_ATID_EN0__ATID30_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN0__ATID30_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID29_EN___M 0x20000000 +#define DBG_OUTDMUX_ATID_EN0__ATID29_EN___S 29 +#define DBG_OUTDMUX_ATID_EN0__ATID29_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN0__ATID29_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID28_EN___M 0x10000000 +#define DBG_OUTDMUX_ATID_EN0__ATID28_EN___S 28 +#define DBG_OUTDMUX_ATID_EN0__ATID28_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN0__ATID28_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID27_EN___M 0x08000000 +#define DBG_OUTDMUX_ATID_EN0__ATID27_EN___S 27 +#define DBG_OUTDMUX_ATID_EN0__ATID27_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN0__ATID27_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID26_EN___M 0x04000000 +#define DBG_OUTDMUX_ATID_EN0__ATID26_EN___S 26 +#define DBG_OUTDMUX_ATID_EN0__ATID26_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN0__ATID26_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID25_EN___M 0x02000000 +#define DBG_OUTDMUX_ATID_EN0__ATID25_EN___S 25 +#define DBG_OUTDMUX_ATID_EN0__ATID25_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN0__ATID25_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID24_EN___M 0x01000000 +#define DBG_OUTDMUX_ATID_EN0__ATID24_EN___S 24 +#define DBG_OUTDMUX_ATID_EN0__ATID24_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN0__ATID24_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID23_EN___M 0x00800000 +#define DBG_OUTDMUX_ATID_EN0__ATID23_EN___S 23 +#define DBG_OUTDMUX_ATID_EN0__ATID23_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN0__ATID23_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID22_EN___M 0x00400000 +#define DBG_OUTDMUX_ATID_EN0__ATID22_EN___S 22 +#define DBG_OUTDMUX_ATID_EN0__ATID22_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN0__ATID22_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID21_EN___M 0x00200000 +#define DBG_OUTDMUX_ATID_EN0__ATID21_EN___S 21 +#define DBG_OUTDMUX_ATID_EN0__ATID21_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN0__ATID21_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID20_EN___M 0x00100000 +#define DBG_OUTDMUX_ATID_EN0__ATID20_EN___S 20 +#define DBG_OUTDMUX_ATID_EN0__ATID20_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN0__ATID20_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID19_EN___M 0x00080000 +#define DBG_OUTDMUX_ATID_EN0__ATID19_EN___S 19 +#define DBG_OUTDMUX_ATID_EN0__ATID19_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN0__ATID19_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID18_EN___M 0x00040000 +#define DBG_OUTDMUX_ATID_EN0__ATID18_EN___S 18 +#define DBG_OUTDMUX_ATID_EN0__ATID18_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN0__ATID18_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID17_EN___M 0x00020000 +#define DBG_OUTDMUX_ATID_EN0__ATID17_EN___S 17 +#define DBG_OUTDMUX_ATID_EN0__ATID17_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN0__ATID17_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID16_EN___M 0x00010000 +#define DBG_OUTDMUX_ATID_EN0__ATID16_EN___S 16 +#define DBG_OUTDMUX_ATID_EN0__ATID16_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN0__ATID16_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID15_EN___M 0x00008000 +#define DBG_OUTDMUX_ATID_EN0__ATID15_EN___S 15 +#define DBG_OUTDMUX_ATID_EN0__ATID15_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN0__ATID15_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID14_EN___M 0x00004000 +#define DBG_OUTDMUX_ATID_EN0__ATID14_EN___S 14 +#define DBG_OUTDMUX_ATID_EN0__ATID14_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN0__ATID14_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID13_EN___M 0x00002000 +#define DBG_OUTDMUX_ATID_EN0__ATID13_EN___S 13 +#define DBG_OUTDMUX_ATID_EN0__ATID13_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN0__ATID13_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID12_EN___M 0x00001000 +#define DBG_OUTDMUX_ATID_EN0__ATID12_EN___S 12 +#define DBG_OUTDMUX_ATID_EN0__ATID12_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN0__ATID12_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID11_EN___M 0x00000800 +#define DBG_OUTDMUX_ATID_EN0__ATID11_EN___S 11 +#define DBG_OUTDMUX_ATID_EN0__ATID11_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN0__ATID11_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID10_EN___M 0x00000400 +#define DBG_OUTDMUX_ATID_EN0__ATID10_EN___S 10 +#define DBG_OUTDMUX_ATID_EN0__ATID10_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN0__ATID10_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID9_EN___M 0x00000200 +#define DBG_OUTDMUX_ATID_EN0__ATID9_EN___S 9 +#define DBG_OUTDMUX_ATID_EN0__ATID9_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN0__ATID9_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID8_EN___M 0x00000100 +#define DBG_OUTDMUX_ATID_EN0__ATID8_EN___S 8 +#define DBG_OUTDMUX_ATID_EN0__ATID8_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN0__ATID8_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID7_EN___M 0x00000080 +#define DBG_OUTDMUX_ATID_EN0__ATID7_EN___S 7 +#define DBG_OUTDMUX_ATID_EN0__ATID7_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN0__ATID7_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID6_EN___M 0x00000040 +#define DBG_OUTDMUX_ATID_EN0__ATID6_EN___S 6 +#define DBG_OUTDMUX_ATID_EN0__ATID6_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN0__ATID6_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID5_EN___M 0x00000020 +#define DBG_OUTDMUX_ATID_EN0__ATID5_EN___S 5 +#define DBG_OUTDMUX_ATID_EN0__ATID5_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN0__ATID5_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID4_EN___M 0x00000010 +#define DBG_OUTDMUX_ATID_EN0__ATID4_EN___S 4 +#define DBG_OUTDMUX_ATID_EN0__ATID4_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN0__ATID4_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID3_EN___M 0x00000008 +#define DBG_OUTDMUX_ATID_EN0__ATID3_EN___S 3 +#define DBG_OUTDMUX_ATID_EN0__ATID3_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN0__ATID3_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID2_EN___M 0x00000004 +#define DBG_OUTDMUX_ATID_EN0__ATID2_EN___S 2 +#define DBG_OUTDMUX_ATID_EN0__ATID2_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN0__ATID2_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID1_EN___M 0x00000002 +#define DBG_OUTDMUX_ATID_EN0__ATID1_EN___S 1 +#define DBG_OUTDMUX_ATID_EN0__ATID1_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN0__ATID1_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN0__ATID0_EN___M 0x00000001 +#define DBG_OUTDMUX_ATID_EN0__ATID0_EN___S 0 +#define DBG_OUTDMUX_ATID_EN0__ATID0_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN0__ATID0_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN0___M 0xFFFFFFFF +#define DBG_OUTDMUX_ATID_EN0___S 0 + +#define DBG_OUTDMUX_ATID_EN1 (0x00BC0004) +#define DBG_OUTDMUX_ATID_EN1___RWC QCSR_REG_RW +#define DBG_OUTDMUX_ATID_EN1___POR 0xFFFFFFFF +#define DBG_OUTDMUX_ATID_EN1__ATID63_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID62_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID61_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID60_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID59_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID58_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID57_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID56_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID55_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID54_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID53_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID52_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID51_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID50_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID49_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID48_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID47_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID46_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID45_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID44_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID43_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID42_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID41_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID40_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID39_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID38_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID37_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID36_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID35_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID34_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID33_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID32_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID63_EN___M 0x80000000 +#define DBG_OUTDMUX_ATID_EN1__ATID63_EN___S 31 +#define DBG_OUTDMUX_ATID_EN1__ATID63_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN1__ATID63_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID62_EN___M 0x40000000 +#define DBG_OUTDMUX_ATID_EN1__ATID62_EN___S 30 +#define DBG_OUTDMUX_ATID_EN1__ATID62_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN1__ATID62_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID61_EN___M 0x20000000 +#define DBG_OUTDMUX_ATID_EN1__ATID61_EN___S 29 +#define DBG_OUTDMUX_ATID_EN1__ATID61_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN1__ATID61_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID60_EN___M 0x10000000 +#define DBG_OUTDMUX_ATID_EN1__ATID60_EN___S 28 +#define DBG_OUTDMUX_ATID_EN1__ATID60_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN1__ATID60_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID59_EN___M 0x08000000 +#define DBG_OUTDMUX_ATID_EN1__ATID59_EN___S 27 +#define DBG_OUTDMUX_ATID_EN1__ATID59_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN1__ATID59_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID58_EN___M 0x04000000 +#define DBG_OUTDMUX_ATID_EN1__ATID58_EN___S 26 +#define DBG_OUTDMUX_ATID_EN1__ATID58_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN1__ATID58_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID57_EN___M 0x02000000 +#define DBG_OUTDMUX_ATID_EN1__ATID57_EN___S 25 +#define DBG_OUTDMUX_ATID_EN1__ATID57_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN1__ATID57_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID56_EN___M 0x01000000 +#define DBG_OUTDMUX_ATID_EN1__ATID56_EN___S 24 +#define DBG_OUTDMUX_ATID_EN1__ATID56_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN1__ATID56_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID55_EN___M 0x00800000 +#define DBG_OUTDMUX_ATID_EN1__ATID55_EN___S 23 +#define DBG_OUTDMUX_ATID_EN1__ATID55_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN1__ATID55_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID54_EN___M 0x00400000 +#define DBG_OUTDMUX_ATID_EN1__ATID54_EN___S 22 +#define DBG_OUTDMUX_ATID_EN1__ATID54_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN1__ATID54_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID53_EN___M 0x00200000 +#define DBG_OUTDMUX_ATID_EN1__ATID53_EN___S 21 +#define DBG_OUTDMUX_ATID_EN1__ATID53_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN1__ATID53_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID52_EN___M 0x00100000 +#define DBG_OUTDMUX_ATID_EN1__ATID52_EN___S 20 +#define DBG_OUTDMUX_ATID_EN1__ATID52_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN1__ATID52_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID51_EN___M 0x00080000 +#define DBG_OUTDMUX_ATID_EN1__ATID51_EN___S 19 +#define DBG_OUTDMUX_ATID_EN1__ATID51_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN1__ATID51_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID50_EN___M 0x00040000 +#define DBG_OUTDMUX_ATID_EN1__ATID50_EN___S 18 +#define DBG_OUTDMUX_ATID_EN1__ATID50_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN1__ATID50_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID49_EN___M 0x00020000 +#define DBG_OUTDMUX_ATID_EN1__ATID49_EN___S 17 +#define DBG_OUTDMUX_ATID_EN1__ATID49_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN1__ATID49_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID48_EN___M 0x00010000 +#define DBG_OUTDMUX_ATID_EN1__ATID48_EN___S 16 +#define DBG_OUTDMUX_ATID_EN1__ATID48_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN1__ATID48_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID47_EN___M 0x00008000 +#define DBG_OUTDMUX_ATID_EN1__ATID47_EN___S 15 +#define DBG_OUTDMUX_ATID_EN1__ATID47_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN1__ATID47_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID46_EN___M 0x00004000 +#define DBG_OUTDMUX_ATID_EN1__ATID46_EN___S 14 +#define DBG_OUTDMUX_ATID_EN1__ATID46_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN1__ATID46_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID45_EN___M 0x00002000 +#define DBG_OUTDMUX_ATID_EN1__ATID45_EN___S 13 +#define DBG_OUTDMUX_ATID_EN1__ATID45_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN1__ATID45_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID44_EN___M 0x00001000 +#define DBG_OUTDMUX_ATID_EN1__ATID44_EN___S 12 +#define DBG_OUTDMUX_ATID_EN1__ATID44_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN1__ATID44_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID43_EN___M 0x00000800 +#define DBG_OUTDMUX_ATID_EN1__ATID43_EN___S 11 +#define DBG_OUTDMUX_ATID_EN1__ATID43_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN1__ATID43_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID42_EN___M 0x00000400 +#define DBG_OUTDMUX_ATID_EN1__ATID42_EN___S 10 +#define DBG_OUTDMUX_ATID_EN1__ATID42_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN1__ATID42_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID41_EN___M 0x00000200 +#define DBG_OUTDMUX_ATID_EN1__ATID41_EN___S 9 +#define DBG_OUTDMUX_ATID_EN1__ATID41_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN1__ATID41_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID40_EN___M 0x00000100 +#define DBG_OUTDMUX_ATID_EN1__ATID40_EN___S 8 +#define DBG_OUTDMUX_ATID_EN1__ATID40_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN1__ATID40_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID39_EN___M 0x00000080 +#define DBG_OUTDMUX_ATID_EN1__ATID39_EN___S 7 +#define DBG_OUTDMUX_ATID_EN1__ATID39_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN1__ATID39_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID38_EN___M 0x00000040 +#define DBG_OUTDMUX_ATID_EN1__ATID38_EN___S 6 +#define DBG_OUTDMUX_ATID_EN1__ATID38_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN1__ATID38_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID37_EN___M 0x00000020 +#define DBG_OUTDMUX_ATID_EN1__ATID37_EN___S 5 +#define DBG_OUTDMUX_ATID_EN1__ATID37_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN1__ATID37_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID36_EN___M 0x00000010 +#define DBG_OUTDMUX_ATID_EN1__ATID36_EN___S 4 +#define DBG_OUTDMUX_ATID_EN1__ATID36_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN1__ATID36_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID35_EN___M 0x00000008 +#define DBG_OUTDMUX_ATID_EN1__ATID35_EN___S 3 +#define DBG_OUTDMUX_ATID_EN1__ATID35_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN1__ATID35_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID34_EN___M 0x00000004 +#define DBG_OUTDMUX_ATID_EN1__ATID34_EN___S 2 +#define DBG_OUTDMUX_ATID_EN1__ATID34_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN1__ATID34_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID33_EN___M 0x00000002 +#define DBG_OUTDMUX_ATID_EN1__ATID33_EN___S 1 +#define DBG_OUTDMUX_ATID_EN1__ATID33_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN1__ATID33_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN1__ATID32_EN___M 0x00000001 +#define DBG_OUTDMUX_ATID_EN1__ATID32_EN___S 0 +#define DBG_OUTDMUX_ATID_EN1__ATID32_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN1__ATID32_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN1___M 0xFFFFFFFF +#define DBG_OUTDMUX_ATID_EN1___S 0 + +#define DBG_OUTDMUX_ATID_EN2 (0x00BC0008) +#define DBG_OUTDMUX_ATID_EN2___RWC QCSR_REG_RW +#define DBG_OUTDMUX_ATID_EN2___POR 0xFFFFFFFF +#define DBG_OUTDMUX_ATID_EN2__ATID95_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID94_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID93_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID92_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID91_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID90_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID89_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID88_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID87_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID86_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID85_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID84_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID83_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID82_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID81_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID80_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID79_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID78_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID77_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID76_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID75_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID74_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID73_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID72_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID71_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID70_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID69_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID68_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID67_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID66_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID65_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID64_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID95_EN___M 0x80000000 +#define DBG_OUTDMUX_ATID_EN2__ATID95_EN___S 31 +#define DBG_OUTDMUX_ATID_EN2__ATID95_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN2__ATID95_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID94_EN___M 0x40000000 +#define DBG_OUTDMUX_ATID_EN2__ATID94_EN___S 30 +#define DBG_OUTDMUX_ATID_EN2__ATID94_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN2__ATID94_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID93_EN___M 0x20000000 +#define DBG_OUTDMUX_ATID_EN2__ATID93_EN___S 29 +#define DBG_OUTDMUX_ATID_EN2__ATID93_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN2__ATID93_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID92_EN___M 0x10000000 +#define DBG_OUTDMUX_ATID_EN2__ATID92_EN___S 28 +#define DBG_OUTDMUX_ATID_EN2__ATID92_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN2__ATID92_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID91_EN___M 0x08000000 +#define DBG_OUTDMUX_ATID_EN2__ATID91_EN___S 27 +#define DBG_OUTDMUX_ATID_EN2__ATID91_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN2__ATID91_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID90_EN___M 0x04000000 +#define DBG_OUTDMUX_ATID_EN2__ATID90_EN___S 26 +#define DBG_OUTDMUX_ATID_EN2__ATID90_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN2__ATID90_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID89_EN___M 0x02000000 +#define DBG_OUTDMUX_ATID_EN2__ATID89_EN___S 25 +#define DBG_OUTDMUX_ATID_EN2__ATID89_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN2__ATID89_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID88_EN___M 0x01000000 +#define DBG_OUTDMUX_ATID_EN2__ATID88_EN___S 24 +#define DBG_OUTDMUX_ATID_EN2__ATID88_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN2__ATID88_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID87_EN___M 0x00800000 +#define DBG_OUTDMUX_ATID_EN2__ATID87_EN___S 23 +#define DBG_OUTDMUX_ATID_EN2__ATID87_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN2__ATID87_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID86_EN___M 0x00400000 +#define DBG_OUTDMUX_ATID_EN2__ATID86_EN___S 22 +#define DBG_OUTDMUX_ATID_EN2__ATID86_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN2__ATID86_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID85_EN___M 0x00200000 +#define DBG_OUTDMUX_ATID_EN2__ATID85_EN___S 21 +#define DBG_OUTDMUX_ATID_EN2__ATID85_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN2__ATID85_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID84_EN___M 0x00100000 +#define DBG_OUTDMUX_ATID_EN2__ATID84_EN___S 20 +#define DBG_OUTDMUX_ATID_EN2__ATID84_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN2__ATID84_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID83_EN___M 0x00080000 +#define DBG_OUTDMUX_ATID_EN2__ATID83_EN___S 19 +#define DBG_OUTDMUX_ATID_EN2__ATID83_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN2__ATID83_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID82_EN___M 0x00040000 +#define DBG_OUTDMUX_ATID_EN2__ATID82_EN___S 18 +#define DBG_OUTDMUX_ATID_EN2__ATID82_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN2__ATID82_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID81_EN___M 0x00020000 +#define DBG_OUTDMUX_ATID_EN2__ATID81_EN___S 17 +#define DBG_OUTDMUX_ATID_EN2__ATID81_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN2__ATID81_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID80_EN___M 0x00010000 +#define DBG_OUTDMUX_ATID_EN2__ATID80_EN___S 16 +#define DBG_OUTDMUX_ATID_EN2__ATID80_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN2__ATID80_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID79_EN___M 0x00008000 +#define DBG_OUTDMUX_ATID_EN2__ATID79_EN___S 15 +#define DBG_OUTDMUX_ATID_EN2__ATID79_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN2__ATID79_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID78_EN___M 0x00004000 +#define DBG_OUTDMUX_ATID_EN2__ATID78_EN___S 14 +#define DBG_OUTDMUX_ATID_EN2__ATID78_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN2__ATID78_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID77_EN___M 0x00002000 +#define DBG_OUTDMUX_ATID_EN2__ATID77_EN___S 13 +#define DBG_OUTDMUX_ATID_EN2__ATID77_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN2__ATID77_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID76_EN___M 0x00001000 +#define DBG_OUTDMUX_ATID_EN2__ATID76_EN___S 12 +#define DBG_OUTDMUX_ATID_EN2__ATID76_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN2__ATID76_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID75_EN___M 0x00000800 +#define DBG_OUTDMUX_ATID_EN2__ATID75_EN___S 11 +#define DBG_OUTDMUX_ATID_EN2__ATID75_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN2__ATID75_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID74_EN___M 0x00000400 +#define DBG_OUTDMUX_ATID_EN2__ATID74_EN___S 10 +#define DBG_OUTDMUX_ATID_EN2__ATID74_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN2__ATID74_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID73_EN___M 0x00000200 +#define DBG_OUTDMUX_ATID_EN2__ATID73_EN___S 9 +#define DBG_OUTDMUX_ATID_EN2__ATID73_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN2__ATID73_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID72_EN___M 0x00000100 +#define DBG_OUTDMUX_ATID_EN2__ATID72_EN___S 8 +#define DBG_OUTDMUX_ATID_EN2__ATID72_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN2__ATID72_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID71_EN___M 0x00000080 +#define DBG_OUTDMUX_ATID_EN2__ATID71_EN___S 7 +#define DBG_OUTDMUX_ATID_EN2__ATID71_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN2__ATID71_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID70_EN___M 0x00000040 +#define DBG_OUTDMUX_ATID_EN2__ATID70_EN___S 6 +#define DBG_OUTDMUX_ATID_EN2__ATID70_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN2__ATID70_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID69_EN___M 0x00000020 +#define DBG_OUTDMUX_ATID_EN2__ATID69_EN___S 5 +#define DBG_OUTDMUX_ATID_EN2__ATID69_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN2__ATID69_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID68_EN___M 0x00000010 +#define DBG_OUTDMUX_ATID_EN2__ATID68_EN___S 4 +#define DBG_OUTDMUX_ATID_EN2__ATID68_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN2__ATID68_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID67_EN___M 0x00000008 +#define DBG_OUTDMUX_ATID_EN2__ATID67_EN___S 3 +#define DBG_OUTDMUX_ATID_EN2__ATID67_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN2__ATID67_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID66_EN___M 0x00000004 +#define DBG_OUTDMUX_ATID_EN2__ATID66_EN___S 2 +#define DBG_OUTDMUX_ATID_EN2__ATID66_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN2__ATID66_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID65_EN___M 0x00000002 +#define DBG_OUTDMUX_ATID_EN2__ATID65_EN___S 1 +#define DBG_OUTDMUX_ATID_EN2__ATID65_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN2__ATID65_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN2__ATID64_EN___M 0x00000001 +#define DBG_OUTDMUX_ATID_EN2__ATID64_EN___S 0 +#define DBG_OUTDMUX_ATID_EN2__ATID64_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN2__ATID64_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN2___M 0xFFFFFFFF +#define DBG_OUTDMUX_ATID_EN2___S 0 + +#define DBG_OUTDMUX_ATID_EN3 (0x00BC000C) +#define DBG_OUTDMUX_ATID_EN3___RWC QCSR_REG_RW +#define DBG_OUTDMUX_ATID_EN3___POR 0xFFFFFFFF +#define DBG_OUTDMUX_ATID_EN3__ATID127_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID126_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID125_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID124_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID123_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID122_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID121_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID120_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID119_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID118_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID117_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID116_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID115_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID114_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID113_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID112_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID111_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID110_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID109_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID108_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID107_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID106_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID105_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID104_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID103_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID102_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID101_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID100_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID99_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID98_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID97_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID96_EN___POR 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID127_EN___M 0x80000000 +#define DBG_OUTDMUX_ATID_EN3__ATID127_EN___S 31 +#define DBG_OUTDMUX_ATID_EN3__ATID127_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN3__ATID127_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID126_EN___M 0x40000000 +#define DBG_OUTDMUX_ATID_EN3__ATID126_EN___S 30 +#define DBG_OUTDMUX_ATID_EN3__ATID126_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN3__ATID126_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID125_EN___M 0x20000000 +#define DBG_OUTDMUX_ATID_EN3__ATID125_EN___S 29 +#define DBG_OUTDMUX_ATID_EN3__ATID125_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN3__ATID125_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID124_EN___M 0x10000000 +#define DBG_OUTDMUX_ATID_EN3__ATID124_EN___S 28 +#define DBG_OUTDMUX_ATID_EN3__ATID124_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN3__ATID124_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID123_EN___M 0x08000000 +#define DBG_OUTDMUX_ATID_EN3__ATID123_EN___S 27 +#define DBG_OUTDMUX_ATID_EN3__ATID123_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN3__ATID123_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID122_EN___M 0x04000000 +#define DBG_OUTDMUX_ATID_EN3__ATID122_EN___S 26 +#define DBG_OUTDMUX_ATID_EN3__ATID122_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN3__ATID122_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID121_EN___M 0x02000000 +#define DBG_OUTDMUX_ATID_EN3__ATID121_EN___S 25 +#define DBG_OUTDMUX_ATID_EN3__ATID121_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN3__ATID121_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID120_EN___M 0x01000000 +#define DBG_OUTDMUX_ATID_EN3__ATID120_EN___S 24 +#define DBG_OUTDMUX_ATID_EN3__ATID120_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN3__ATID120_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID119_EN___M 0x00800000 +#define DBG_OUTDMUX_ATID_EN3__ATID119_EN___S 23 +#define DBG_OUTDMUX_ATID_EN3__ATID119_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN3__ATID119_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID118_EN___M 0x00400000 +#define DBG_OUTDMUX_ATID_EN3__ATID118_EN___S 22 +#define DBG_OUTDMUX_ATID_EN3__ATID118_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN3__ATID118_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID117_EN___M 0x00200000 +#define DBG_OUTDMUX_ATID_EN3__ATID117_EN___S 21 +#define DBG_OUTDMUX_ATID_EN3__ATID117_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN3__ATID117_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID116_EN___M 0x00100000 +#define DBG_OUTDMUX_ATID_EN3__ATID116_EN___S 20 +#define DBG_OUTDMUX_ATID_EN3__ATID116_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN3__ATID116_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID115_EN___M 0x00080000 +#define DBG_OUTDMUX_ATID_EN3__ATID115_EN___S 19 +#define DBG_OUTDMUX_ATID_EN3__ATID115_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN3__ATID115_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID114_EN___M 0x00040000 +#define DBG_OUTDMUX_ATID_EN3__ATID114_EN___S 18 +#define DBG_OUTDMUX_ATID_EN3__ATID114_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN3__ATID114_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID113_EN___M 0x00020000 +#define DBG_OUTDMUX_ATID_EN3__ATID113_EN___S 17 +#define DBG_OUTDMUX_ATID_EN3__ATID113_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN3__ATID113_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID112_EN___M 0x00010000 +#define DBG_OUTDMUX_ATID_EN3__ATID112_EN___S 16 +#define DBG_OUTDMUX_ATID_EN3__ATID112_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN3__ATID112_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID111_EN___M 0x00008000 +#define DBG_OUTDMUX_ATID_EN3__ATID111_EN___S 15 +#define DBG_OUTDMUX_ATID_EN3__ATID111_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN3__ATID111_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID110_EN___M 0x00004000 +#define DBG_OUTDMUX_ATID_EN3__ATID110_EN___S 14 +#define DBG_OUTDMUX_ATID_EN3__ATID110_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN3__ATID110_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID109_EN___M 0x00002000 +#define DBG_OUTDMUX_ATID_EN3__ATID109_EN___S 13 +#define DBG_OUTDMUX_ATID_EN3__ATID109_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN3__ATID109_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID108_EN___M 0x00001000 +#define DBG_OUTDMUX_ATID_EN3__ATID108_EN___S 12 +#define DBG_OUTDMUX_ATID_EN3__ATID108_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN3__ATID108_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID107_EN___M 0x00000800 +#define DBG_OUTDMUX_ATID_EN3__ATID107_EN___S 11 +#define DBG_OUTDMUX_ATID_EN3__ATID107_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN3__ATID107_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID106_EN___M 0x00000400 +#define DBG_OUTDMUX_ATID_EN3__ATID106_EN___S 10 +#define DBG_OUTDMUX_ATID_EN3__ATID106_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN3__ATID106_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID105_EN___M 0x00000200 +#define DBG_OUTDMUX_ATID_EN3__ATID105_EN___S 9 +#define DBG_OUTDMUX_ATID_EN3__ATID105_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN3__ATID105_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID104_EN___M 0x00000100 +#define DBG_OUTDMUX_ATID_EN3__ATID104_EN___S 8 +#define DBG_OUTDMUX_ATID_EN3__ATID104_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN3__ATID104_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID103_EN___M 0x00000080 +#define DBG_OUTDMUX_ATID_EN3__ATID103_EN___S 7 +#define DBG_OUTDMUX_ATID_EN3__ATID103_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN3__ATID103_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID102_EN___M 0x00000040 +#define DBG_OUTDMUX_ATID_EN3__ATID102_EN___S 6 +#define DBG_OUTDMUX_ATID_EN3__ATID102_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN3__ATID102_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID101_EN___M 0x00000020 +#define DBG_OUTDMUX_ATID_EN3__ATID101_EN___S 5 +#define DBG_OUTDMUX_ATID_EN3__ATID101_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN3__ATID101_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID100_EN___M 0x00000010 +#define DBG_OUTDMUX_ATID_EN3__ATID100_EN___S 4 +#define DBG_OUTDMUX_ATID_EN3__ATID100_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN3__ATID100_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID99_EN___M 0x00000008 +#define DBG_OUTDMUX_ATID_EN3__ATID99_EN___S 3 +#define DBG_OUTDMUX_ATID_EN3__ATID99_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN3__ATID99_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID98_EN___M 0x00000004 +#define DBG_OUTDMUX_ATID_EN3__ATID98_EN___S 2 +#define DBG_OUTDMUX_ATID_EN3__ATID98_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN3__ATID98_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID97_EN___M 0x00000002 +#define DBG_OUTDMUX_ATID_EN3__ATID97_EN___S 1 +#define DBG_OUTDMUX_ATID_EN3__ATID97_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN3__ATID97_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN3__ATID96_EN___M 0x00000001 +#define DBG_OUTDMUX_ATID_EN3__ATID96_EN___S 0 +#define DBG_OUTDMUX_ATID_EN3__ATID96_EN__DISABLE 0x0 +#define DBG_OUTDMUX_ATID_EN3__ATID96_EN__ENABLE 0x1 +#define DBG_OUTDMUX_ATID_EN3___M 0xFFFFFFFF +#define DBG_OUTDMUX_ATID_EN3___S 0 + +#define DBG_OUTDMUX_ATID_SEL0 (0x00BC0010) +#define DBG_OUTDMUX_ATID_SEL0___RWC QCSR_REG_RW +#define DBG_OUTDMUX_ATID_SEL0___POR 0x00000000 +#define DBG_OUTDMUX_ATID_SEL0__ATID31_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID30_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID29_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID28_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID27_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID26_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID25_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID24_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID23_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID22_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID21_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID20_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID19_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID18_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID17_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID16_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID15_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID14_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID13_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID12_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID11_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID10_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID9_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID8_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID7_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID6_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID5_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID4_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID3_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID2_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID1_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID0_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID31_SEL___M 0x80000000 +#define DBG_OUTDMUX_ATID_SEL0__ATID31_SEL___S 31 +#define DBG_OUTDMUX_ATID_SEL0__ATID31_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID31_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL0__ATID30_SEL___M 0x40000000 +#define DBG_OUTDMUX_ATID_SEL0__ATID30_SEL___S 30 +#define DBG_OUTDMUX_ATID_SEL0__ATID30_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID30_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL0__ATID29_SEL___M 0x20000000 +#define DBG_OUTDMUX_ATID_SEL0__ATID29_SEL___S 29 +#define DBG_OUTDMUX_ATID_SEL0__ATID29_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID29_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL0__ATID28_SEL___M 0x10000000 +#define DBG_OUTDMUX_ATID_SEL0__ATID28_SEL___S 28 +#define DBG_OUTDMUX_ATID_SEL0__ATID28_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID28_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL0__ATID27_SEL___M 0x08000000 +#define DBG_OUTDMUX_ATID_SEL0__ATID27_SEL___S 27 +#define DBG_OUTDMUX_ATID_SEL0__ATID27_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID27_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL0__ATID26_SEL___M 0x04000000 +#define DBG_OUTDMUX_ATID_SEL0__ATID26_SEL___S 26 +#define DBG_OUTDMUX_ATID_SEL0__ATID26_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID26_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL0__ATID25_SEL___M 0x02000000 +#define DBG_OUTDMUX_ATID_SEL0__ATID25_SEL___S 25 +#define DBG_OUTDMUX_ATID_SEL0__ATID25_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID25_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL0__ATID24_SEL___M 0x01000000 +#define DBG_OUTDMUX_ATID_SEL0__ATID24_SEL___S 24 +#define DBG_OUTDMUX_ATID_SEL0__ATID24_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID24_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL0__ATID23_SEL___M 0x00800000 +#define DBG_OUTDMUX_ATID_SEL0__ATID23_SEL___S 23 +#define DBG_OUTDMUX_ATID_SEL0__ATID23_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID23_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL0__ATID22_SEL___M 0x00400000 +#define DBG_OUTDMUX_ATID_SEL0__ATID22_SEL___S 22 +#define DBG_OUTDMUX_ATID_SEL0__ATID22_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID22_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL0__ATID21_SEL___M 0x00200000 +#define DBG_OUTDMUX_ATID_SEL0__ATID21_SEL___S 21 +#define DBG_OUTDMUX_ATID_SEL0__ATID21_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID21_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL0__ATID20_SEL___M 0x00100000 +#define DBG_OUTDMUX_ATID_SEL0__ATID20_SEL___S 20 +#define DBG_OUTDMUX_ATID_SEL0__ATID20_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID20_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL0__ATID19_SEL___M 0x00080000 +#define DBG_OUTDMUX_ATID_SEL0__ATID19_SEL___S 19 +#define DBG_OUTDMUX_ATID_SEL0__ATID19_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID19_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL0__ATID18_SEL___M 0x00040000 +#define DBG_OUTDMUX_ATID_SEL0__ATID18_SEL___S 18 +#define DBG_OUTDMUX_ATID_SEL0__ATID18_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID18_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL0__ATID17_SEL___M 0x00020000 +#define DBG_OUTDMUX_ATID_SEL0__ATID17_SEL___S 17 +#define DBG_OUTDMUX_ATID_SEL0__ATID17_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID17_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL0__ATID16_SEL___M 0x00010000 +#define DBG_OUTDMUX_ATID_SEL0__ATID16_SEL___S 16 +#define DBG_OUTDMUX_ATID_SEL0__ATID16_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID16_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL0__ATID15_SEL___M 0x00008000 +#define DBG_OUTDMUX_ATID_SEL0__ATID15_SEL___S 15 +#define DBG_OUTDMUX_ATID_SEL0__ATID15_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID15_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL0__ATID14_SEL___M 0x00004000 +#define DBG_OUTDMUX_ATID_SEL0__ATID14_SEL___S 14 +#define DBG_OUTDMUX_ATID_SEL0__ATID14_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID14_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL0__ATID13_SEL___M 0x00002000 +#define DBG_OUTDMUX_ATID_SEL0__ATID13_SEL___S 13 +#define DBG_OUTDMUX_ATID_SEL0__ATID13_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID13_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL0__ATID12_SEL___M 0x00001000 +#define DBG_OUTDMUX_ATID_SEL0__ATID12_SEL___S 12 +#define DBG_OUTDMUX_ATID_SEL0__ATID12_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID12_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL0__ATID11_SEL___M 0x00000800 +#define DBG_OUTDMUX_ATID_SEL0__ATID11_SEL___S 11 +#define DBG_OUTDMUX_ATID_SEL0__ATID11_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID11_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL0__ATID10_SEL___M 0x00000400 +#define DBG_OUTDMUX_ATID_SEL0__ATID10_SEL___S 10 +#define DBG_OUTDMUX_ATID_SEL0__ATID10_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID10_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL0__ATID9_SEL___M 0x00000200 +#define DBG_OUTDMUX_ATID_SEL0__ATID9_SEL___S 9 +#define DBG_OUTDMUX_ATID_SEL0__ATID9_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID9_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL0__ATID8_SEL___M 0x00000100 +#define DBG_OUTDMUX_ATID_SEL0__ATID8_SEL___S 8 +#define DBG_OUTDMUX_ATID_SEL0__ATID8_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID8_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL0__ATID7_SEL___M 0x00000080 +#define DBG_OUTDMUX_ATID_SEL0__ATID7_SEL___S 7 +#define DBG_OUTDMUX_ATID_SEL0__ATID7_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID7_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL0__ATID6_SEL___M 0x00000040 +#define DBG_OUTDMUX_ATID_SEL0__ATID6_SEL___S 6 +#define DBG_OUTDMUX_ATID_SEL0__ATID6_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID6_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL0__ATID5_SEL___M 0x00000020 +#define DBG_OUTDMUX_ATID_SEL0__ATID5_SEL___S 5 +#define DBG_OUTDMUX_ATID_SEL0__ATID5_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID5_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL0__ATID4_SEL___M 0x00000010 +#define DBG_OUTDMUX_ATID_SEL0__ATID4_SEL___S 4 +#define DBG_OUTDMUX_ATID_SEL0__ATID4_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID4_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL0__ATID3_SEL___M 0x00000008 +#define DBG_OUTDMUX_ATID_SEL0__ATID3_SEL___S 3 +#define DBG_OUTDMUX_ATID_SEL0__ATID3_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID3_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL0__ATID2_SEL___M 0x00000004 +#define DBG_OUTDMUX_ATID_SEL0__ATID2_SEL___S 2 +#define DBG_OUTDMUX_ATID_SEL0__ATID2_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID2_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL0__ATID1_SEL___M 0x00000002 +#define DBG_OUTDMUX_ATID_SEL0__ATID1_SEL___S 1 +#define DBG_OUTDMUX_ATID_SEL0__ATID1_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID1_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL0__ATID0_SEL___M 0x00000001 +#define DBG_OUTDMUX_ATID_SEL0__ATID0_SEL___S 0 +#define DBG_OUTDMUX_ATID_SEL0__ATID0_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL0__ATID0_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL0___M 0xFFFFFFFF +#define DBG_OUTDMUX_ATID_SEL0___S 0 + +#define DBG_OUTDMUX_ATID_SEL1 (0x00BC0014) +#define DBG_OUTDMUX_ATID_SEL1___RWC QCSR_REG_RW +#define DBG_OUTDMUX_ATID_SEL1___POR 0x00000000 +#define DBG_OUTDMUX_ATID_SEL1__ATID63_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID62_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID61_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID60_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID59_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID58_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID57_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID56_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID55_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID54_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID53_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID52_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID51_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID50_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID49_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID48_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID47_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID46_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID45_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID44_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID43_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID42_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID41_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID40_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID39_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID38_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID37_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID36_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID35_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID34_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID33_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID32_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID63_SEL___M 0x80000000 +#define DBG_OUTDMUX_ATID_SEL1__ATID63_SEL___S 31 +#define DBG_OUTDMUX_ATID_SEL1__ATID63_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID63_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL1__ATID62_SEL___M 0x40000000 +#define DBG_OUTDMUX_ATID_SEL1__ATID62_SEL___S 30 +#define DBG_OUTDMUX_ATID_SEL1__ATID62_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID62_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL1__ATID61_SEL___M 0x20000000 +#define DBG_OUTDMUX_ATID_SEL1__ATID61_SEL___S 29 +#define DBG_OUTDMUX_ATID_SEL1__ATID61_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID61_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL1__ATID60_SEL___M 0x10000000 +#define DBG_OUTDMUX_ATID_SEL1__ATID60_SEL___S 28 +#define DBG_OUTDMUX_ATID_SEL1__ATID60_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID60_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL1__ATID59_SEL___M 0x08000000 +#define DBG_OUTDMUX_ATID_SEL1__ATID59_SEL___S 27 +#define DBG_OUTDMUX_ATID_SEL1__ATID59_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID59_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL1__ATID58_SEL___M 0x04000000 +#define DBG_OUTDMUX_ATID_SEL1__ATID58_SEL___S 26 +#define DBG_OUTDMUX_ATID_SEL1__ATID58_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID58_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL1__ATID57_SEL___M 0x02000000 +#define DBG_OUTDMUX_ATID_SEL1__ATID57_SEL___S 25 +#define DBG_OUTDMUX_ATID_SEL1__ATID57_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID57_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL1__ATID56_SEL___M 0x01000000 +#define DBG_OUTDMUX_ATID_SEL1__ATID56_SEL___S 24 +#define DBG_OUTDMUX_ATID_SEL1__ATID56_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID56_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL1__ATID55_SEL___M 0x00800000 +#define DBG_OUTDMUX_ATID_SEL1__ATID55_SEL___S 23 +#define DBG_OUTDMUX_ATID_SEL1__ATID55_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID55_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL1__ATID54_SEL___M 0x00400000 +#define DBG_OUTDMUX_ATID_SEL1__ATID54_SEL___S 22 +#define DBG_OUTDMUX_ATID_SEL1__ATID54_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID54_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL1__ATID53_SEL___M 0x00200000 +#define DBG_OUTDMUX_ATID_SEL1__ATID53_SEL___S 21 +#define DBG_OUTDMUX_ATID_SEL1__ATID53_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID53_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL1__ATID52_SEL___M 0x00100000 +#define DBG_OUTDMUX_ATID_SEL1__ATID52_SEL___S 20 +#define DBG_OUTDMUX_ATID_SEL1__ATID52_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID52_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL1__ATID51_SEL___M 0x00080000 +#define DBG_OUTDMUX_ATID_SEL1__ATID51_SEL___S 19 +#define DBG_OUTDMUX_ATID_SEL1__ATID51_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID51_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL1__ATID50_SEL___M 0x00040000 +#define DBG_OUTDMUX_ATID_SEL1__ATID50_SEL___S 18 +#define DBG_OUTDMUX_ATID_SEL1__ATID50_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID50_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL1__ATID49_SEL___M 0x00020000 +#define DBG_OUTDMUX_ATID_SEL1__ATID49_SEL___S 17 +#define DBG_OUTDMUX_ATID_SEL1__ATID49_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID49_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL1__ATID48_SEL___M 0x00010000 +#define DBG_OUTDMUX_ATID_SEL1__ATID48_SEL___S 16 +#define DBG_OUTDMUX_ATID_SEL1__ATID48_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID48_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL1__ATID47_SEL___M 0x00008000 +#define DBG_OUTDMUX_ATID_SEL1__ATID47_SEL___S 15 +#define DBG_OUTDMUX_ATID_SEL1__ATID47_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID47_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL1__ATID46_SEL___M 0x00004000 +#define DBG_OUTDMUX_ATID_SEL1__ATID46_SEL___S 14 +#define DBG_OUTDMUX_ATID_SEL1__ATID46_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID46_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL1__ATID45_SEL___M 0x00002000 +#define DBG_OUTDMUX_ATID_SEL1__ATID45_SEL___S 13 +#define DBG_OUTDMUX_ATID_SEL1__ATID45_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID45_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL1__ATID44_SEL___M 0x00001000 +#define DBG_OUTDMUX_ATID_SEL1__ATID44_SEL___S 12 +#define DBG_OUTDMUX_ATID_SEL1__ATID44_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID44_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL1__ATID43_SEL___M 0x00000800 +#define DBG_OUTDMUX_ATID_SEL1__ATID43_SEL___S 11 +#define DBG_OUTDMUX_ATID_SEL1__ATID43_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID43_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL1__ATID42_SEL___M 0x00000400 +#define DBG_OUTDMUX_ATID_SEL1__ATID42_SEL___S 10 +#define DBG_OUTDMUX_ATID_SEL1__ATID42_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID42_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL1__ATID41_SEL___M 0x00000200 +#define DBG_OUTDMUX_ATID_SEL1__ATID41_SEL___S 9 +#define DBG_OUTDMUX_ATID_SEL1__ATID41_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID41_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL1__ATID40_SEL___M 0x00000100 +#define DBG_OUTDMUX_ATID_SEL1__ATID40_SEL___S 8 +#define DBG_OUTDMUX_ATID_SEL1__ATID40_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID40_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL1__ATID39_SEL___M 0x00000080 +#define DBG_OUTDMUX_ATID_SEL1__ATID39_SEL___S 7 +#define DBG_OUTDMUX_ATID_SEL1__ATID39_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID39_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL1__ATID38_SEL___M 0x00000040 +#define DBG_OUTDMUX_ATID_SEL1__ATID38_SEL___S 6 +#define DBG_OUTDMUX_ATID_SEL1__ATID38_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID38_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL1__ATID37_SEL___M 0x00000020 +#define DBG_OUTDMUX_ATID_SEL1__ATID37_SEL___S 5 +#define DBG_OUTDMUX_ATID_SEL1__ATID37_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID37_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL1__ATID36_SEL___M 0x00000010 +#define DBG_OUTDMUX_ATID_SEL1__ATID36_SEL___S 4 +#define DBG_OUTDMUX_ATID_SEL1__ATID36_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID36_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL1__ATID35_SEL___M 0x00000008 +#define DBG_OUTDMUX_ATID_SEL1__ATID35_SEL___S 3 +#define DBG_OUTDMUX_ATID_SEL1__ATID35_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID35_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL1__ATID34_SEL___M 0x00000004 +#define DBG_OUTDMUX_ATID_SEL1__ATID34_SEL___S 2 +#define DBG_OUTDMUX_ATID_SEL1__ATID34_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID34_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL1__ATID33_SEL___M 0x00000002 +#define DBG_OUTDMUX_ATID_SEL1__ATID33_SEL___S 1 +#define DBG_OUTDMUX_ATID_SEL1__ATID33_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID33_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL1__ATID32_SEL___M 0x00000001 +#define DBG_OUTDMUX_ATID_SEL1__ATID32_SEL___S 0 +#define DBG_OUTDMUX_ATID_SEL1__ATID32_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL1__ATID32_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL1___M 0xFFFFFFFF +#define DBG_OUTDMUX_ATID_SEL1___S 0 + +#define DBG_OUTDMUX_ATID_SEL2 (0x00BC0018) +#define DBG_OUTDMUX_ATID_SEL2___RWC QCSR_REG_RW +#define DBG_OUTDMUX_ATID_SEL2___POR 0x00000000 +#define DBG_OUTDMUX_ATID_SEL2__ATID95_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID94_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID93_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID92_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID91_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID90_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID89_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID88_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID87_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID86_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID85_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID84_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID83_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID82_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID81_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID80_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID79_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID78_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID77_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID76_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID75_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID74_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID73_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID72_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID71_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID70_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID69_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID68_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID67_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID66_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID65_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID64_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID95_SEL___M 0x80000000 +#define DBG_OUTDMUX_ATID_SEL2__ATID95_SEL___S 31 +#define DBG_OUTDMUX_ATID_SEL2__ATID95_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID95_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL2__ATID94_SEL___M 0x40000000 +#define DBG_OUTDMUX_ATID_SEL2__ATID94_SEL___S 30 +#define DBG_OUTDMUX_ATID_SEL2__ATID94_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID94_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL2__ATID93_SEL___M 0x20000000 +#define DBG_OUTDMUX_ATID_SEL2__ATID93_SEL___S 29 +#define DBG_OUTDMUX_ATID_SEL2__ATID93_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID93_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL2__ATID92_SEL___M 0x10000000 +#define DBG_OUTDMUX_ATID_SEL2__ATID92_SEL___S 28 +#define DBG_OUTDMUX_ATID_SEL2__ATID92_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID92_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL2__ATID91_SEL___M 0x08000000 +#define DBG_OUTDMUX_ATID_SEL2__ATID91_SEL___S 27 +#define DBG_OUTDMUX_ATID_SEL2__ATID91_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID91_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL2__ATID90_SEL___M 0x04000000 +#define DBG_OUTDMUX_ATID_SEL2__ATID90_SEL___S 26 +#define DBG_OUTDMUX_ATID_SEL2__ATID90_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID90_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL2__ATID89_SEL___M 0x02000000 +#define DBG_OUTDMUX_ATID_SEL2__ATID89_SEL___S 25 +#define DBG_OUTDMUX_ATID_SEL2__ATID89_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID89_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL2__ATID88_SEL___M 0x01000000 +#define DBG_OUTDMUX_ATID_SEL2__ATID88_SEL___S 24 +#define DBG_OUTDMUX_ATID_SEL2__ATID88_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID88_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL2__ATID87_SEL___M 0x00800000 +#define DBG_OUTDMUX_ATID_SEL2__ATID87_SEL___S 23 +#define DBG_OUTDMUX_ATID_SEL2__ATID87_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID87_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL2__ATID86_SEL___M 0x00400000 +#define DBG_OUTDMUX_ATID_SEL2__ATID86_SEL___S 22 +#define DBG_OUTDMUX_ATID_SEL2__ATID86_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID86_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL2__ATID85_SEL___M 0x00200000 +#define DBG_OUTDMUX_ATID_SEL2__ATID85_SEL___S 21 +#define DBG_OUTDMUX_ATID_SEL2__ATID85_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID85_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL2__ATID84_SEL___M 0x00100000 +#define DBG_OUTDMUX_ATID_SEL2__ATID84_SEL___S 20 +#define DBG_OUTDMUX_ATID_SEL2__ATID84_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID84_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL2__ATID83_SEL___M 0x00080000 +#define DBG_OUTDMUX_ATID_SEL2__ATID83_SEL___S 19 +#define DBG_OUTDMUX_ATID_SEL2__ATID83_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID83_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL2__ATID82_SEL___M 0x00040000 +#define DBG_OUTDMUX_ATID_SEL2__ATID82_SEL___S 18 +#define DBG_OUTDMUX_ATID_SEL2__ATID82_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID82_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL2__ATID81_SEL___M 0x00020000 +#define DBG_OUTDMUX_ATID_SEL2__ATID81_SEL___S 17 +#define DBG_OUTDMUX_ATID_SEL2__ATID81_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID81_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL2__ATID80_SEL___M 0x00010000 +#define DBG_OUTDMUX_ATID_SEL2__ATID80_SEL___S 16 +#define DBG_OUTDMUX_ATID_SEL2__ATID80_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID80_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL2__ATID79_SEL___M 0x00008000 +#define DBG_OUTDMUX_ATID_SEL2__ATID79_SEL___S 15 +#define DBG_OUTDMUX_ATID_SEL2__ATID79_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID79_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL2__ATID78_SEL___M 0x00004000 +#define DBG_OUTDMUX_ATID_SEL2__ATID78_SEL___S 14 +#define DBG_OUTDMUX_ATID_SEL2__ATID78_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID78_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL2__ATID77_SEL___M 0x00002000 +#define DBG_OUTDMUX_ATID_SEL2__ATID77_SEL___S 13 +#define DBG_OUTDMUX_ATID_SEL2__ATID77_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID77_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL2__ATID76_SEL___M 0x00001000 +#define DBG_OUTDMUX_ATID_SEL2__ATID76_SEL___S 12 +#define DBG_OUTDMUX_ATID_SEL2__ATID76_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID76_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL2__ATID75_SEL___M 0x00000800 +#define DBG_OUTDMUX_ATID_SEL2__ATID75_SEL___S 11 +#define DBG_OUTDMUX_ATID_SEL2__ATID75_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID75_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL2__ATID74_SEL___M 0x00000400 +#define DBG_OUTDMUX_ATID_SEL2__ATID74_SEL___S 10 +#define DBG_OUTDMUX_ATID_SEL2__ATID74_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID74_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL2__ATID73_SEL___M 0x00000200 +#define DBG_OUTDMUX_ATID_SEL2__ATID73_SEL___S 9 +#define DBG_OUTDMUX_ATID_SEL2__ATID73_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID73_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL2__ATID72_SEL___M 0x00000100 +#define DBG_OUTDMUX_ATID_SEL2__ATID72_SEL___S 8 +#define DBG_OUTDMUX_ATID_SEL2__ATID72_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID72_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL2__ATID71_SEL___M 0x00000080 +#define DBG_OUTDMUX_ATID_SEL2__ATID71_SEL___S 7 +#define DBG_OUTDMUX_ATID_SEL2__ATID71_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID71_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL2__ATID70_SEL___M 0x00000040 +#define DBG_OUTDMUX_ATID_SEL2__ATID70_SEL___S 6 +#define DBG_OUTDMUX_ATID_SEL2__ATID70_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID70_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL2__ATID69_SEL___M 0x00000020 +#define DBG_OUTDMUX_ATID_SEL2__ATID69_SEL___S 5 +#define DBG_OUTDMUX_ATID_SEL2__ATID69_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID69_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL2__ATID68_SEL___M 0x00000010 +#define DBG_OUTDMUX_ATID_SEL2__ATID68_SEL___S 4 +#define DBG_OUTDMUX_ATID_SEL2__ATID68_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID68_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL2__ATID67_SEL___M 0x00000008 +#define DBG_OUTDMUX_ATID_SEL2__ATID67_SEL___S 3 +#define DBG_OUTDMUX_ATID_SEL2__ATID67_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID67_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL2__ATID66_SEL___M 0x00000004 +#define DBG_OUTDMUX_ATID_SEL2__ATID66_SEL___S 2 +#define DBG_OUTDMUX_ATID_SEL2__ATID66_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID66_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL2__ATID65_SEL___M 0x00000002 +#define DBG_OUTDMUX_ATID_SEL2__ATID65_SEL___S 1 +#define DBG_OUTDMUX_ATID_SEL2__ATID65_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID65_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL2__ATID64_SEL___M 0x00000001 +#define DBG_OUTDMUX_ATID_SEL2__ATID64_SEL___S 0 +#define DBG_OUTDMUX_ATID_SEL2__ATID64_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL2__ATID64_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL2___M 0xFFFFFFFF +#define DBG_OUTDMUX_ATID_SEL2___S 0 + +#define DBG_OUTDMUX_ATID_SEL3 (0x00BC001C) +#define DBG_OUTDMUX_ATID_SEL3___RWC QCSR_REG_RW +#define DBG_OUTDMUX_ATID_SEL3___POR 0x00000000 +#define DBG_OUTDMUX_ATID_SEL3__ATID127_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID126_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID125_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID124_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID123_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID122_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID121_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID120_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID119_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID118_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID117_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID116_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID115_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID114_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID113_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID112_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID111_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID110_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID109_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID108_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID107_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID106_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID105_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID104_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID103_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID102_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID101_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID100_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID99_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID98_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID97_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID96_SEL___POR 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID127_SEL___M 0x80000000 +#define DBG_OUTDMUX_ATID_SEL3__ATID127_SEL___S 31 +#define DBG_OUTDMUX_ATID_SEL3__ATID127_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID127_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL3__ATID126_SEL___M 0x40000000 +#define DBG_OUTDMUX_ATID_SEL3__ATID126_SEL___S 30 +#define DBG_OUTDMUX_ATID_SEL3__ATID126_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID126_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL3__ATID125_SEL___M 0x20000000 +#define DBG_OUTDMUX_ATID_SEL3__ATID125_SEL___S 29 +#define DBG_OUTDMUX_ATID_SEL3__ATID125_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID125_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL3__ATID124_SEL___M 0x10000000 +#define DBG_OUTDMUX_ATID_SEL3__ATID124_SEL___S 28 +#define DBG_OUTDMUX_ATID_SEL3__ATID124_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID124_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL3__ATID123_SEL___M 0x08000000 +#define DBG_OUTDMUX_ATID_SEL3__ATID123_SEL___S 27 +#define DBG_OUTDMUX_ATID_SEL3__ATID123_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID123_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL3__ATID122_SEL___M 0x04000000 +#define DBG_OUTDMUX_ATID_SEL3__ATID122_SEL___S 26 +#define DBG_OUTDMUX_ATID_SEL3__ATID122_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID122_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL3__ATID121_SEL___M 0x02000000 +#define DBG_OUTDMUX_ATID_SEL3__ATID121_SEL___S 25 +#define DBG_OUTDMUX_ATID_SEL3__ATID121_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID121_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL3__ATID120_SEL___M 0x01000000 +#define DBG_OUTDMUX_ATID_SEL3__ATID120_SEL___S 24 +#define DBG_OUTDMUX_ATID_SEL3__ATID120_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID120_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL3__ATID119_SEL___M 0x00800000 +#define DBG_OUTDMUX_ATID_SEL3__ATID119_SEL___S 23 +#define DBG_OUTDMUX_ATID_SEL3__ATID119_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID119_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL3__ATID118_SEL___M 0x00400000 +#define DBG_OUTDMUX_ATID_SEL3__ATID118_SEL___S 22 +#define DBG_OUTDMUX_ATID_SEL3__ATID118_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID118_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL3__ATID117_SEL___M 0x00200000 +#define DBG_OUTDMUX_ATID_SEL3__ATID117_SEL___S 21 +#define DBG_OUTDMUX_ATID_SEL3__ATID117_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID117_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL3__ATID116_SEL___M 0x00100000 +#define DBG_OUTDMUX_ATID_SEL3__ATID116_SEL___S 20 +#define DBG_OUTDMUX_ATID_SEL3__ATID116_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID116_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL3__ATID115_SEL___M 0x00080000 +#define DBG_OUTDMUX_ATID_SEL3__ATID115_SEL___S 19 +#define DBG_OUTDMUX_ATID_SEL3__ATID115_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID115_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL3__ATID114_SEL___M 0x00040000 +#define DBG_OUTDMUX_ATID_SEL3__ATID114_SEL___S 18 +#define DBG_OUTDMUX_ATID_SEL3__ATID114_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID114_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL3__ATID113_SEL___M 0x00020000 +#define DBG_OUTDMUX_ATID_SEL3__ATID113_SEL___S 17 +#define DBG_OUTDMUX_ATID_SEL3__ATID113_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID113_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL3__ATID112_SEL___M 0x00010000 +#define DBG_OUTDMUX_ATID_SEL3__ATID112_SEL___S 16 +#define DBG_OUTDMUX_ATID_SEL3__ATID112_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID112_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL3__ATID111_SEL___M 0x00008000 +#define DBG_OUTDMUX_ATID_SEL3__ATID111_SEL___S 15 +#define DBG_OUTDMUX_ATID_SEL3__ATID111_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID111_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL3__ATID110_SEL___M 0x00004000 +#define DBG_OUTDMUX_ATID_SEL3__ATID110_SEL___S 14 +#define DBG_OUTDMUX_ATID_SEL3__ATID110_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID110_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL3__ATID109_SEL___M 0x00002000 +#define DBG_OUTDMUX_ATID_SEL3__ATID109_SEL___S 13 +#define DBG_OUTDMUX_ATID_SEL3__ATID109_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID109_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL3__ATID108_SEL___M 0x00001000 +#define DBG_OUTDMUX_ATID_SEL3__ATID108_SEL___S 12 +#define DBG_OUTDMUX_ATID_SEL3__ATID108_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID108_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL3__ATID107_SEL___M 0x00000800 +#define DBG_OUTDMUX_ATID_SEL3__ATID107_SEL___S 11 +#define DBG_OUTDMUX_ATID_SEL3__ATID107_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID107_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL3__ATID106_SEL___M 0x00000400 +#define DBG_OUTDMUX_ATID_SEL3__ATID106_SEL___S 10 +#define DBG_OUTDMUX_ATID_SEL3__ATID106_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID106_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL3__ATID105_SEL___M 0x00000200 +#define DBG_OUTDMUX_ATID_SEL3__ATID105_SEL___S 9 +#define DBG_OUTDMUX_ATID_SEL3__ATID105_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID105_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL3__ATID104_SEL___M 0x00000100 +#define DBG_OUTDMUX_ATID_SEL3__ATID104_SEL___S 8 +#define DBG_OUTDMUX_ATID_SEL3__ATID104_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID104_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL3__ATID103_SEL___M 0x00000080 +#define DBG_OUTDMUX_ATID_SEL3__ATID103_SEL___S 7 +#define DBG_OUTDMUX_ATID_SEL3__ATID103_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID103_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL3__ATID102_SEL___M 0x00000040 +#define DBG_OUTDMUX_ATID_SEL3__ATID102_SEL___S 6 +#define DBG_OUTDMUX_ATID_SEL3__ATID102_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID102_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL3__ATID101_SEL___M 0x00000020 +#define DBG_OUTDMUX_ATID_SEL3__ATID101_SEL___S 5 +#define DBG_OUTDMUX_ATID_SEL3__ATID101_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID101_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL3__ATID100_SEL___M 0x00000010 +#define DBG_OUTDMUX_ATID_SEL3__ATID100_SEL___S 4 +#define DBG_OUTDMUX_ATID_SEL3__ATID100_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID100_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL3__ATID99_SEL___M 0x00000008 +#define DBG_OUTDMUX_ATID_SEL3__ATID99_SEL___S 3 +#define DBG_OUTDMUX_ATID_SEL3__ATID99_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID99_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL3__ATID98_SEL___M 0x00000004 +#define DBG_OUTDMUX_ATID_SEL3__ATID98_SEL___S 2 +#define DBG_OUTDMUX_ATID_SEL3__ATID98_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID98_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL3__ATID97_SEL___M 0x00000002 +#define DBG_OUTDMUX_ATID_SEL3__ATID97_SEL___S 1 +#define DBG_OUTDMUX_ATID_SEL3__ATID97_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID97_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL3__ATID96_SEL___M 0x00000001 +#define DBG_OUTDMUX_ATID_SEL3__ATID96_SEL___S 0 +#define DBG_OUTDMUX_ATID_SEL3__ATID96_SEL__SEL_PORT0 0x0 +#define DBG_OUTDMUX_ATID_SEL3__ATID96_SEL__SEL_PORT1 0x1 +#define DBG_OUTDMUX_ATID_SEL3___M 0xFFFFFFFF +#define DBG_OUTDMUX_ATID_SEL3___S 0 + +#define DBG_CNTRn_CFG(n) (0x00BC1000+0x40*(n)) +#define DBG_CNTRn_CFG_nMIN 0 +#define DBG_CNTRn_CFG_nMAX 3 +#define DBG_CNTRn_CFG_ELEM 4 +#define DBG_CNTRn_CFG___RWC QCSR_REG_RW +#define DBG_CNTRn_CFG___POR 0x00000000 +#define DBG_CNTRn_CFG__CNT_TYPE___POR 0x0 +#define DBG_CNTRn_CFG__ATB_PROBE_SEL___POR 0x00 +#define DBG_CNTRn_CFG__ENABLE___POR 0x0 +#define DBG_CNTRn_CFG__CNT_TYPE___M 0x00000040 +#define DBG_CNTRn_CFG__CNT_TYPE___S 6 +#define DBG_CNTRn_CFG__CNT_TYPE__BYTES 0x0 +#define DBG_CNTRn_CFG__CNT_TYPE__WAIT_CYCLES 0x1 +#define DBG_CNTRn_CFG__ATB_PROBE_SEL___M 0x0000003E +#define DBG_CNTRn_CFG__ATB_PROBE_SEL___S 1 +#define DBG_CNTRn_CFG__ATB_PROBE_SEL__PMM_BDG2TGUFILT 0x00 +#define DBG_CNTRn_CFG__ATB_PROBE_SEL__PMM_CMB_BDG2FUN 0x01 +#define DBG_CNTRn_CFG__ATB_PROBE_SEL__PMM_BDG2FUN 0x02 +#define DBG_CNTRn_CFG__ATB_PROBE_SEL__UMACDBG_BDG2FUN 0x03 +#define DBG_CNTRn_CFG__ATB_PROBE_SEL__PHYA_BDG2TGUFILT 0x04 +#define DBG_CNTRn_CFG__ATB_PROBE_SEL__PHYA_DMUX2CMB 0x05 +#define DBG_CNTRn_CFG__ATB_PROBE_SEL__PHYA_BDG2FUN 0x06 +#define DBG_CNTRn_CFG__ATB_PROBE_SEL__PHYB_BDG2TGUFILT 0x07 +#define DBG_CNTRn_CFG__ATB_PROBE_SEL__PHYB_DMUX2CMB 0x08 +#define DBG_CNTRn_CFG__ATB_PROBE_SEL__PHYB_BDG2FUN 0x09 +#define DBG_CNTRn_CFG__ATB_PROBE_SEL__CPHY_BDG2FUN 0x0A +#define DBG_CNTRn_CFG__ATB_PROBE_SEL__MACEVENT_CMB 0x0B +#define DBG_CNTRn_CFG__ATB_PROBE_SEL__DATDUMPR_CMB 0x0C +#define DBG_CNTRn_CFG__ATB_PROBE_SEL__APBMON_CMB 0x0D +#define DBG_CNTRn_CFG__ATB_PROBE_SEL__SWGEN_CMB 0x0E +#define DBG_CNTRn_CFG__ATB_PROBE_SEL__UPSZ2TPDA 0x0F +#define DBG_CNTRn_CFG__ATB_PROBE_SEL__MACTLV_CMB 0x10 +#define DBG_CNTRn_CFG__ATB_PROBE_SEL__MACTLV_TPDM2TPDA 0x11 +#define DBG_CNTRn_CFG__ATB_PROBE_SEL__MACTBUS_CMB 0x12 +#define DBG_CNTRn_CFG__ATB_PROBE_SEL__MISC_TPDM2TPDA 0x13 +#define DBG_CNTRn_CFG__ATB_PROBE_SEL__TPDA_BDG2FUN 0x14 +#define DBG_CNTRn_CFG__ATB_PROBE_SEL__TSTMP_INJCTR 0x15 +#define DBG_CNTRn_CFG__ATB_PROBE_SEL__MACEVENT_ATB 0x16 +#define DBG_CNTRn_CFG__ATB_PROBE_SEL__MACTLV_ATB 0x17 +#define DBG_CNTRn_CFG__ATB_PROBE_SEL__MACTBUS_ATB 0x18 +#define DBG_CNTRn_CFG__ATB_PROBE_SEL__FUN_MST 0x19 +#define DBG_CNTRn_CFG__ATB_PROBE_SEL__ETB_SLV 0x1A +#define DBG_CNTRn_CFG__ATB_PROBE_SEL__ETB_MST 0x1B +#define DBG_CNTRn_CFG__ATB_PROBE_SEL__ETB_BYPASS 0x1C +#define DBG_CNTRn_CFG__ATB_PROBE_SEL__FIFO2ABDGS 0x1D +#define DBG_CNTRn_CFG__ATB_PROBE_SEL__MISC_FUN2TPDM 0x1E +#define DBG_CNTRn_CFG__ENABLE___M 0x00000001 +#define DBG_CNTRn_CFG__ENABLE___S 0 +#define DBG_CNTRn_CFG___M 0x0000007F +#define DBG_CNTRn_CFG___S 0 +#define DBG_CNTR0_CFG (0x00BC1000) +#define DBG_CNTR0_CFG___RWC QCSR_REG_RW +#define DBG_CNTR0_CFG__CNT_TYPE___M 0x00000040 +#define DBG_CNTR0_CFG__CNT_TYPE___S 6 +#define DBG_CNTR0_CFG__ATB_PROBE_SEL___M 0x0000003E +#define DBG_CNTR0_CFG__ATB_PROBE_SEL___S 1 +#define DBG_CNTR0_CFG__ENABLE___M 0x00000001 +#define DBG_CNTR0_CFG__ENABLE___S 0 +#define DBG_CNTR1_CFG (0x00BC1040) +#define DBG_CNTR1_CFG___RWC QCSR_REG_RW +#define DBG_CNTR1_CFG__CNT_TYPE___M 0x00000040 +#define DBG_CNTR1_CFG__CNT_TYPE___S 6 +#define DBG_CNTR1_CFG__ATB_PROBE_SEL___M 0x0000003E +#define DBG_CNTR1_CFG__ATB_PROBE_SEL___S 1 +#define DBG_CNTR1_CFG__ENABLE___M 0x00000001 +#define DBG_CNTR1_CFG__ENABLE___S 0 +#define DBG_CNTR2_CFG (0x00BC1080) +#define DBG_CNTR2_CFG___RWC QCSR_REG_RW +#define DBG_CNTR2_CFG__CNT_TYPE___M 0x00000040 +#define DBG_CNTR2_CFG__CNT_TYPE___S 6 +#define DBG_CNTR2_CFG__ATB_PROBE_SEL___M 0x0000003E +#define DBG_CNTR2_CFG__ATB_PROBE_SEL___S 1 +#define DBG_CNTR2_CFG__ENABLE___M 0x00000001 +#define DBG_CNTR2_CFG__ENABLE___S 0 +#define DBG_CNTR3_CFG (0x00BC10C0) +#define DBG_CNTR3_CFG___RWC QCSR_REG_RW +#define DBG_CNTR3_CFG__CNT_TYPE___M 0x00000040 +#define DBG_CNTR3_CFG__CNT_TYPE___S 6 +#define DBG_CNTR3_CFG__ATB_PROBE_SEL___M 0x0000003E +#define DBG_CNTR3_CFG__ATB_PROBE_SEL___S 1 +#define DBG_CNTR3_CFG__ENABLE___M 0x00000001 +#define DBG_CNTR3_CFG__ENABLE___S 0 + +#define DBG_CNTRn_ATID_EN0(n) (0x00BC1004+0x40*(n)) +#define DBG_CNTRn_ATID_EN0_nMIN 0 +#define DBG_CNTRn_ATID_EN0_nMAX 3 +#define DBG_CNTRn_ATID_EN0_ELEM 4 +#define DBG_CNTRn_ATID_EN0___RWC QCSR_REG_RW +#define DBG_CNTRn_ATID_EN0___POR 0xFFFFFFFF +#define DBG_CNTRn_ATID_EN0__ATID31_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN0__ATID30_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN0__ATID29_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN0__ATID28_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN0__ATID27_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN0__ATID26_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN0__ATID25_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN0__ATID24_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN0__ATID23_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN0__ATID22_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN0__ATID21_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN0__ATID20_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN0__ATID19_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN0__ATID18_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN0__ATID17_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN0__ATID16_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN0__ATID15_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN0__ATID14_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN0__ATID13_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN0__ATID12_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN0__ATID11_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN0__ATID10_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN0__ATID9_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN0__ATID8_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN0__ATID7_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN0__ATID6_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN0__ATID5_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN0__ATID4_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN0__ATID3_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN0__ATID2_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN0__ATID1_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN0__ATID0_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN0__ATID31_EN___M 0x80000000 +#define DBG_CNTRn_ATID_EN0__ATID31_EN___S 31 +#define DBG_CNTRn_ATID_EN0__ATID31_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN0__ATID31_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN0__ATID30_EN___M 0x40000000 +#define DBG_CNTRn_ATID_EN0__ATID30_EN___S 30 +#define DBG_CNTRn_ATID_EN0__ATID30_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN0__ATID30_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN0__ATID29_EN___M 0x20000000 +#define DBG_CNTRn_ATID_EN0__ATID29_EN___S 29 +#define DBG_CNTRn_ATID_EN0__ATID29_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN0__ATID29_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN0__ATID28_EN___M 0x10000000 +#define DBG_CNTRn_ATID_EN0__ATID28_EN___S 28 +#define DBG_CNTRn_ATID_EN0__ATID28_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN0__ATID28_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN0__ATID27_EN___M 0x08000000 +#define DBG_CNTRn_ATID_EN0__ATID27_EN___S 27 +#define DBG_CNTRn_ATID_EN0__ATID27_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN0__ATID27_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN0__ATID26_EN___M 0x04000000 +#define DBG_CNTRn_ATID_EN0__ATID26_EN___S 26 +#define DBG_CNTRn_ATID_EN0__ATID26_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN0__ATID26_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN0__ATID25_EN___M 0x02000000 +#define DBG_CNTRn_ATID_EN0__ATID25_EN___S 25 +#define DBG_CNTRn_ATID_EN0__ATID25_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN0__ATID25_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN0__ATID24_EN___M 0x01000000 +#define DBG_CNTRn_ATID_EN0__ATID24_EN___S 24 +#define DBG_CNTRn_ATID_EN0__ATID24_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN0__ATID24_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN0__ATID23_EN___M 0x00800000 +#define DBG_CNTRn_ATID_EN0__ATID23_EN___S 23 +#define DBG_CNTRn_ATID_EN0__ATID23_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN0__ATID23_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN0__ATID22_EN___M 0x00400000 +#define DBG_CNTRn_ATID_EN0__ATID22_EN___S 22 +#define DBG_CNTRn_ATID_EN0__ATID22_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN0__ATID22_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN0__ATID21_EN___M 0x00200000 +#define DBG_CNTRn_ATID_EN0__ATID21_EN___S 21 +#define DBG_CNTRn_ATID_EN0__ATID21_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN0__ATID21_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN0__ATID20_EN___M 0x00100000 +#define DBG_CNTRn_ATID_EN0__ATID20_EN___S 20 +#define DBG_CNTRn_ATID_EN0__ATID20_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN0__ATID20_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN0__ATID19_EN___M 0x00080000 +#define DBG_CNTRn_ATID_EN0__ATID19_EN___S 19 +#define DBG_CNTRn_ATID_EN0__ATID19_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN0__ATID19_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN0__ATID18_EN___M 0x00040000 +#define DBG_CNTRn_ATID_EN0__ATID18_EN___S 18 +#define DBG_CNTRn_ATID_EN0__ATID18_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN0__ATID18_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN0__ATID17_EN___M 0x00020000 +#define DBG_CNTRn_ATID_EN0__ATID17_EN___S 17 +#define DBG_CNTRn_ATID_EN0__ATID17_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN0__ATID17_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN0__ATID16_EN___M 0x00010000 +#define DBG_CNTRn_ATID_EN0__ATID16_EN___S 16 +#define DBG_CNTRn_ATID_EN0__ATID16_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN0__ATID16_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN0__ATID15_EN___M 0x00008000 +#define DBG_CNTRn_ATID_EN0__ATID15_EN___S 15 +#define DBG_CNTRn_ATID_EN0__ATID15_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN0__ATID15_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN0__ATID14_EN___M 0x00004000 +#define DBG_CNTRn_ATID_EN0__ATID14_EN___S 14 +#define DBG_CNTRn_ATID_EN0__ATID14_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN0__ATID14_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN0__ATID13_EN___M 0x00002000 +#define DBG_CNTRn_ATID_EN0__ATID13_EN___S 13 +#define DBG_CNTRn_ATID_EN0__ATID13_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN0__ATID13_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN0__ATID12_EN___M 0x00001000 +#define DBG_CNTRn_ATID_EN0__ATID12_EN___S 12 +#define DBG_CNTRn_ATID_EN0__ATID12_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN0__ATID12_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN0__ATID11_EN___M 0x00000800 +#define DBG_CNTRn_ATID_EN0__ATID11_EN___S 11 +#define DBG_CNTRn_ATID_EN0__ATID11_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN0__ATID11_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN0__ATID10_EN___M 0x00000400 +#define DBG_CNTRn_ATID_EN0__ATID10_EN___S 10 +#define DBG_CNTRn_ATID_EN0__ATID10_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN0__ATID10_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN0__ATID9_EN___M 0x00000200 +#define DBG_CNTRn_ATID_EN0__ATID9_EN___S 9 +#define DBG_CNTRn_ATID_EN0__ATID9_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN0__ATID9_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN0__ATID8_EN___M 0x00000100 +#define DBG_CNTRn_ATID_EN0__ATID8_EN___S 8 +#define DBG_CNTRn_ATID_EN0__ATID8_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN0__ATID8_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN0__ATID7_EN___M 0x00000080 +#define DBG_CNTRn_ATID_EN0__ATID7_EN___S 7 +#define DBG_CNTRn_ATID_EN0__ATID7_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN0__ATID7_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN0__ATID6_EN___M 0x00000040 +#define DBG_CNTRn_ATID_EN0__ATID6_EN___S 6 +#define DBG_CNTRn_ATID_EN0__ATID6_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN0__ATID6_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN0__ATID5_EN___M 0x00000020 +#define DBG_CNTRn_ATID_EN0__ATID5_EN___S 5 +#define DBG_CNTRn_ATID_EN0__ATID5_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN0__ATID5_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN0__ATID4_EN___M 0x00000010 +#define DBG_CNTRn_ATID_EN0__ATID4_EN___S 4 +#define DBG_CNTRn_ATID_EN0__ATID4_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN0__ATID4_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN0__ATID3_EN___M 0x00000008 +#define DBG_CNTRn_ATID_EN0__ATID3_EN___S 3 +#define DBG_CNTRn_ATID_EN0__ATID3_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN0__ATID3_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN0__ATID2_EN___M 0x00000004 +#define DBG_CNTRn_ATID_EN0__ATID2_EN___S 2 +#define DBG_CNTRn_ATID_EN0__ATID2_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN0__ATID2_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN0__ATID1_EN___M 0x00000002 +#define DBG_CNTRn_ATID_EN0__ATID1_EN___S 1 +#define DBG_CNTRn_ATID_EN0__ATID1_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN0__ATID1_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN0__ATID0_EN___M 0x00000001 +#define DBG_CNTRn_ATID_EN0__ATID0_EN___S 0 +#define DBG_CNTRn_ATID_EN0__ATID0_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN0__ATID0_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN0___M 0xFFFFFFFF +#define DBG_CNTRn_ATID_EN0___S 0 +#define DBG_CNTR0_ATID_EN0 (0x00BC1004) +#define DBG_CNTR0_ATID_EN0___RWC QCSR_REG_RW +#define DBG_CNTR0_ATID_EN0__ATID31_EN___M 0x80000000 +#define DBG_CNTR0_ATID_EN0__ATID31_EN___S 31 +#define DBG_CNTR0_ATID_EN0__ATID30_EN___M 0x40000000 +#define DBG_CNTR0_ATID_EN0__ATID30_EN___S 30 +#define DBG_CNTR0_ATID_EN0__ATID29_EN___M 0x20000000 +#define DBG_CNTR0_ATID_EN0__ATID29_EN___S 29 +#define DBG_CNTR0_ATID_EN0__ATID28_EN___M 0x10000000 +#define DBG_CNTR0_ATID_EN0__ATID28_EN___S 28 +#define DBG_CNTR0_ATID_EN0__ATID27_EN___M 0x08000000 +#define DBG_CNTR0_ATID_EN0__ATID27_EN___S 27 +#define DBG_CNTR0_ATID_EN0__ATID26_EN___M 0x04000000 +#define DBG_CNTR0_ATID_EN0__ATID26_EN___S 26 +#define DBG_CNTR0_ATID_EN0__ATID25_EN___M 0x02000000 +#define DBG_CNTR0_ATID_EN0__ATID25_EN___S 25 +#define DBG_CNTR0_ATID_EN0__ATID24_EN___M 0x01000000 +#define DBG_CNTR0_ATID_EN0__ATID24_EN___S 24 +#define DBG_CNTR0_ATID_EN0__ATID23_EN___M 0x00800000 +#define DBG_CNTR0_ATID_EN0__ATID23_EN___S 23 +#define DBG_CNTR0_ATID_EN0__ATID22_EN___M 0x00400000 +#define DBG_CNTR0_ATID_EN0__ATID22_EN___S 22 +#define DBG_CNTR0_ATID_EN0__ATID21_EN___M 0x00200000 +#define DBG_CNTR0_ATID_EN0__ATID21_EN___S 21 +#define DBG_CNTR0_ATID_EN0__ATID20_EN___M 0x00100000 +#define DBG_CNTR0_ATID_EN0__ATID20_EN___S 20 +#define DBG_CNTR0_ATID_EN0__ATID19_EN___M 0x00080000 +#define DBG_CNTR0_ATID_EN0__ATID19_EN___S 19 +#define DBG_CNTR0_ATID_EN0__ATID18_EN___M 0x00040000 +#define DBG_CNTR0_ATID_EN0__ATID18_EN___S 18 +#define DBG_CNTR0_ATID_EN0__ATID17_EN___M 0x00020000 +#define DBG_CNTR0_ATID_EN0__ATID17_EN___S 17 +#define DBG_CNTR0_ATID_EN0__ATID16_EN___M 0x00010000 +#define DBG_CNTR0_ATID_EN0__ATID16_EN___S 16 +#define DBG_CNTR0_ATID_EN0__ATID15_EN___M 0x00008000 +#define DBG_CNTR0_ATID_EN0__ATID15_EN___S 15 +#define DBG_CNTR0_ATID_EN0__ATID14_EN___M 0x00004000 +#define DBG_CNTR0_ATID_EN0__ATID14_EN___S 14 +#define DBG_CNTR0_ATID_EN0__ATID13_EN___M 0x00002000 +#define DBG_CNTR0_ATID_EN0__ATID13_EN___S 13 +#define DBG_CNTR0_ATID_EN0__ATID12_EN___M 0x00001000 +#define DBG_CNTR0_ATID_EN0__ATID12_EN___S 12 +#define DBG_CNTR0_ATID_EN0__ATID11_EN___M 0x00000800 +#define DBG_CNTR0_ATID_EN0__ATID11_EN___S 11 +#define DBG_CNTR0_ATID_EN0__ATID10_EN___M 0x00000400 +#define DBG_CNTR0_ATID_EN0__ATID10_EN___S 10 +#define DBG_CNTR0_ATID_EN0__ATID9_EN___M 0x00000200 +#define DBG_CNTR0_ATID_EN0__ATID9_EN___S 9 +#define DBG_CNTR0_ATID_EN0__ATID8_EN___M 0x00000100 +#define DBG_CNTR0_ATID_EN0__ATID8_EN___S 8 +#define DBG_CNTR0_ATID_EN0__ATID7_EN___M 0x00000080 +#define DBG_CNTR0_ATID_EN0__ATID7_EN___S 7 +#define DBG_CNTR0_ATID_EN0__ATID6_EN___M 0x00000040 +#define DBG_CNTR0_ATID_EN0__ATID6_EN___S 6 +#define DBG_CNTR0_ATID_EN0__ATID5_EN___M 0x00000020 +#define DBG_CNTR0_ATID_EN0__ATID5_EN___S 5 +#define DBG_CNTR0_ATID_EN0__ATID4_EN___M 0x00000010 +#define DBG_CNTR0_ATID_EN0__ATID4_EN___S 4 +#define DBG_CNTR0_ATID_EN0__ATID3_EN___M 0x00000008 +#define DBG_CNTR0_ATID_EN0__ATID3_EN___S 3 +#define DBG_CNTR0_ATID_EN0__ATID2_EN___M 0x00000004 +#define DBG_CNTR0_ATID_EN0__ATID2_EN___S 2 +#define DBG_CNTR0_ATID_EN0__ATID1_EN___M 0x00000002 +#define DBG_CNTR0_ATID_EN0__ATID1_EN___S 1 +#define DBG_CNTR0_ATID_EN0__ATID0_EN___M 0x00000001 +#define DBG_CNTR0_ATID_EN0__ATID0_EN___S 0 +#define DBG_CNTR1_ATID_EN0 (0x00BC1044) +#define DBG_CNTR1_ATID_EN0___RWC QCSR_REG_RW +#define DBG_CNTR1_ATID_EN0__ATID31_EN___M 0x80000000 +#define DBG_CNTR1_ATID_EN0__ATID31_EN___S 31 +#define DBG_CNTR1_ATID_EN0__ATID30_EN___M 0x40000000 +#define DBG_CNTR1_ATID_EN0__ATID30_EN___S 30 +#define DBG_CNTR1_ATID_EN0__ATID29_EN___M 0x20000000 +#define DBG_CNTR1_ATID_EN0__ATID29_EN___S 29 +#define DBG_CNTR1_ATID_EN0__ATID28_EN___M 0x10000000 +#define DBG_CNTR1_ATID_EN0__ATID28_EN___S 28 +#define DBG_CNTR1_ATID_EN0__ATID27_EN___M 0x08000000 +#define DBG_CNTR1_ATID_EN0__ATID27_EN___S 27 +#define DBG_CNTR1_ATID_EN0__ATID26_EN___M 0x04000000 +#define DBG_CNTR1_ATID_EN0__ATID26_EN___S 26 +#define DBG_CNTR1_ATID_EN0__ATID25_EN___M 0x02000000 +#define DBG_CNTR1_ATID_EN0__ATID25_EN___S 25 +#define DBG_CNTR1_ATID_EN0__ATID24_EN___M 0x01000000 +#define DBG_CNTR1_ATID_EN0__ATID24_EN___S 24 +#define DBG_CNTR1_ATID_EN0__ATID23_EN___M 0x00800000 +#define DBG_CNTR1_ATID_EN0__ATID23_EN___S 23 +#define DBG_CNTR1_ATID_EN0__ATID22_EN___M 0x00400000 +#define DBG_CNTR1_ATID_EN0__ATID22_EN___S 22 +#define DBG_CNTR1_ATID_EN0__ATID21_EN___M 0x00200000 +#define DBG_CNTR1_ATID_EN0__ATID21_EN___S 21 +#define DBG_CNTR1_ATID_EN0__ATID20_EN___M 0x00100000 +#define DBG_CNTR1_ATID_EN0__ATID20_EN___S 20 +#define DBG_CNTR1_ATID_EN0__ATID19_EN___M 0x00080000 +#define DBG_CNTR1_ATID_EN0__ATID19_EN___S 19 +#define DBG_CNTR1_ATID_EN0__ATID18_EN___M 0x00040000 +#define DBG_CNTR1_ATID_EN0__ATID18_EN___S 18 +#define DBG_CNTR1_ATID_EN0__ATID17_EN___M 0x00020000 +#define DBG_CNTR1_ATID_EN0__ATID17_EN___S 17 +#define DBG_CNTR1_ATID_EN0__ATID16_EN___M 0x00010000 +#define DBG_CNTR1_ATID_EN0__ATID16_EN___S 16 +#define DBG_CNTR1_ATID_EN0__ATID15_EN___M 0x00008000 +#define DBG_CNTR1_ATID_EN0__ATID15_EN___S 15 +#define DBG_CNTR1_ATID_EN0__ATID14_EN___M 0x00004000 +#define DBG_CNTR1_ATID_EN0__ATID14_EN___S 14 +#define DBG_CNTR1_ATID_EN0__ATID13_EN___M 0x00002000 +#define DBG_CNTR1_ATID_EN0__ATID13_EN___S 13 +#define DBG_CNTR1_ATID_EN0__ATID12_EN___M 0x00001000 +#define DBG_CNTR1_ATID_EN0__ATID12_EN___S 12 +#define DBG_CNTR1_ATID_EN0__ATID11_EN___M 0x00000800 +#define DBG_CNTR1_ATID_EN0__ATID11_EN___S 11 +#define DBG_CNTR1_ATID_EN0__ATID10_EN___M 0x00000400 +#define DBG_CNTR1_ATID_EN0__ATID10_EN___S 10 +#define DBG_CNTR1_ATID_EN0__ATID9_EN___M 0x00000200 +#define DBG_CNTR1_ATID_EN0__ATID9_EN___S 9 +#define DBG_CNTR1_ATID_EN0__ATID8_EN___M 0x00000100 +#define DBG_CNTR1_ATID_EN0__ATID8_EN___S 8 +#define DBG_CNTR1_ATID_EN0__ATID7_EN___M 0x00000080 +#define DBG_CNTR1_ATID_EN0__ATID7_EN___S 7 +#define DBG_CNTR1_ATID_EN0__ATID6_EN___M 0x00000040 +#define DBG_CNTR1_ATID_EN0__ATID6_EN___S 6 +#define DBG_CNTR1_ATID_EN0__ATID5_EN___M 0x00000020 +#define DBG_CNTR1_ATID_EN0__ATID5_EN___S 5 +#define DBG_CNTR1_ATID_EN0__ATID4_EN___M 0x00000010 +#define DBG_CNTR1_ATID_EN0__ATID4_EN___S 4 +#define DBG_CNTR1_ATID_EN0__ATID3_EN___M 0x00000008 +#define DBG_CNTR1_ATID_EN0__ATID3_EN___S 3 +#define DBG_CNTR1_ATID_EN0__ATID2_EN___M 0x00000004 +#define DBG_CNTR1_ATID_EN0__ATID2_EN___S 2 +#define DBG_CNTR1_ATID_EN0__ATID1_EN___M 0x00000002 +#define DBG_CNTR1_ATID_EN0__ATID1_EN___S 1 +#define DBG_CNTR1_ATID_EN0__ATID0_EN___M 0x00000001 +#define DBG_CNTR1_ATID_EN0__ATID0_EN___S 0 +#define DBG_CNTR2_ATID_EN0 (0x00BC1084) +#define DBG_CNTR2_ATID_EN0___RWC QCSR_REG_RW +#define DBG_CNTR2_ATID_EN0__ATID31_EN___M 0x80000000 +#define DBG_CNTR2_ATID_EN0__ATID31_EN___S 31 +#define DBG_CNTR2_ATID_EN0__ATID30_EN___M 0x40000000 +#define DBG_CNTR2_ATID_EN0__ATID30_EN___S 30 +#define DBG_CNTR2_ATID_EN0__ATID29_EN___M 0x20000000 +#define DBG_CNTR2_ATID_EN0__ATID29_EN___S 29 +#define DBG_CNTR2_ATID_EN0__ATID28_EN___M 0x10000000 +#define DBG_CNTR2_ATID_EN0__ATID28_EN___S 28 +#define DBG_CNTR2_ATID_EN0__ATID27_EN___M 0x08000000 +#define DBG_CNTR2_ATID_EN0__ATID27_EN___S 27 +#define DBG_CNTR2_ATID_EN0__ATID26_EN___M 0x04000000 +#define DBG_CNTR2_ATID_EN0__ATID26_EN___S 26 +#define DBG_CNTR2_ATID_EN0__ATID25_EN___M 0x02000000 +#define DBG_CNTR2_ATID_EN0__ATID25_EN___S 25 +#define DBG_CNTR2_ATID_EN0__ATID24_EN___M 0x01000000 +#define DBG_CNTR2_ATID_EN0__ATID24_EN___S 24 +#define DBG_CNTR2_ATID_EN0__ATID23_EN___M 0x00800000 +#define DBG_CNTR2_ATID_EN0__ATID23_EN___S 23 +#define DBG_CNTR2_ATID_EN0__ATID22_EN___M 0x00400000 +#define DBG_CNTR2_ATID_EN0__ATID22_EN___S 22 +#define DBG_CNTR2_ATID_EN0__ATID21_EN___M 0x00200000 +#define DBG_CNTR2_ATID_EN0__ATID21_EN___S 21 +#define DBG_CNTR2_ATID_EN0__ATID20_EN___M 0x00100000 +#define DBG_CNTR2_ATID_EN0__ATID20_EN___S 20 +#define DBG_CNTR2_ATID_EN0__ATID19_EN___M 0x00080000 +#define DBG_CNTR2_ATID_EN0__ATID19_EN___S 19 +#define DBG_CNTR2_ATID_EN0__ATID18_EN___M 0x00040000 +#define DBG_CNTR2_ATID_EN0__ATID18_EN___S 18 +#define DBG_CNTR2_ATID_EN0__ATID17_EN___M 0x00020000 +#define DBG_CNTR2_ATID_EN0__ATID17_EN___S 17 +#define DBG_CNTR2_ATID_EN0__ATID16_EN___M 0x00010000 +#define DBG_CNTR2_ATID_EN0__ATID16_EN___S 16 +#define DBG_CNTR2_ATID_EN0__ATID15_EN___M 0x00008000 +#define DBG_CNTR2_ATID_EN0__ATID15_EN___S 15 +#define DBG_CNTR2_ATID_EN0__ATID14_EN___M 0x00004000 +#define DBG_CNTR2_ATID_EN0__ATID14_EN___S 14 +#define DBG_CNTR2_ATID_EN0__ATID13_EN___M 0x00002000 +#define DBG_CNTR2_ATID_EN0__ATID13_EN___S 13 +#define DBG_CNTR2_ATID_EN0__ATID12_EN___M 0x00001000 +#define DBG_CNTR2_ATID_EN0__ATID12_EN___S 12 +#define DBG_CNTR2_ATID_EN0__ATID11_EN___M 0x00000800 +#define DBG_CNTR2_ATID_EN0__ATID11_EN___S 11 +#define DBG_CNTR2_ATID_EN0__ATID10_EN___M 0x00000400 +#define DBG_CNTR2_ATID_EN0__ATID10_EN___S 10 +#define DBG_CNTR2_ATID_EN0__ATID9_EN___M 0x00000200 +#define DBG_CNTR2_ATID_EN0__ATID9_EN___S 9 +#define DBG_CNTR2_ATID_EN0__ATID8_EN___M 0x00000100 +#define DBG_CNTR2_ATID_EN0__ATID8_EN___S 8 +#define DBG_CNTR2_ATID_EN0__ATID7_EN___M 0x00000080 +#define DBG_CNTR2_ATID_EN0__ATID7_EN___S 7 +#define DBG_CNTR2_ATID_EN0__ATID6_EN___M 0x00000040 +#define DBG_CNTR2_ATID_EN0__ATID6_EN___S 6 +#define DBG_CNTR2_ATID_EN0__ATID5_EN___M 0x00000020 +#define DBG_CNTR2_ATID_EN0__ATID5_EN___S 5 +#define DBG_CNTR2_ATID_EN0__ATID4_EN___M 0x00000010 +#define DBG_CNTR2_ATID_EN0__ATID4_EN___S 4 +#define DBG_CNTR2_ATID_EN0__ATID3_EN___M 0x00000008 +#define DBG_CNTR2_ATID_EN0__ATID3_EN___S 3 +#define DBG_CNTR2_ATID_EN0__ATID2_EN___M 0x00000004 +#define DBG_CNTR2_ATID_EN0__ATID2_EN___S 2 +#define DBG_CNTR2_ATID_EN0__ATID1_EN___M 0x00000002 +#define DBG_CNTR2_ATID_EN0__ATID1_EN___S 1 +#define DBG_CNTR2_ATID_EN0__ATID0_EN___M 0x00000001 +#define DBG_CNTR2_ATID_EN0__ATID0_EN___S 0 +#define DBG_CNTR3_ATID_EN0 (0x00BC10C4) +#define DBG_CNTR3_ATID_EN0___RWC QCSR_REG_RW +#define DBG_CNTR3_ATID_EN0__ATID31_EN___M 0x80000000 +#define DBG_CNTR3_ATID_EN0__ATID31_EN___S 31 +#define DBG_CNTR3_ATID_EN0__ATID30_EN___M 0x40000000 +#define DBG_CNTR3_ATID_EN0__ATID30_EN___S 30 +#define DBG_CNTR3_ATID_EN0__ATID29_EN___M 0x20000000 +#define DBG_CNTR3_ATID_EN0__ATID29_EN___S 29 +#define DBG_CNTR3_ATID_EN0__ATID28_EN___M 0x10000000 +#define DBG_CNTR3_ATID_EN0__ATID28_EN___S 28 +#define DBG_CNTR3_ATID_EN0__ATID27_EN___M 0x08000000 +#define DBG_CNTR3_ATID_EN0__ATID27_EN___S 27 +#define DBG_CNTR3_ATID_EN0__ATID26_EN___M 0x04000000 +#define DBG_CNTR3_ATID_EN0__ATID26_EN___S 26 +#define DBG_CNTR3_ATID_EN0__ATID25_EN___M 0x02000000 +#define DBG_CNTR3_ATID_EN0__ATID25_EN___S 25 +#define DBG_CNTR3_ATID_EN0__ATID24_EN___M 0x01000000 +#define DBG_CNTR3_ATID_EN0__ATID24_EN___S 24 +#define DBG_CNTR3_ATID_EN0__ATID23_EN___M 0x00800000 +#define DBG_CNTR3_ATID_EN0__ATID23_EN___S 23 +#define DBG_CNTR3_ATID_EN0__ATID22_EN___M 0x00400000 +#define DBG_CNTR3_ATID_EN0__ATID22_EN___S 22 +#define DBG_CNTR3_ATID_EN0__ATID21_EN___M 0x00200000 +#define DBG_CNTR3_ATID_EN0__ATID21_EN___S 21 +#define DBG_CNTR3_ATID_EN0__ATID20_EN___M 0x00100000 +#define DBG_CNTR3_ATID_EN0__ATID20_EN___S 20 +#define DBG_CNTR3_ATID_EN0__ATID19_EN___M 0x00080000 +#define DBG_CNTR3_ATID_EN0__ATID19_EN___S 19 +#define DBG_CNTR3_ATID_EN0__ATID18_EN___M 0x00040000 +#define DBG_CNTR3_ATID_EN0__ATID18_EN___S 18 +#define DBG_CNTR3_ATID_EN0__ATID17_EN___M 0x00020000 +#define DBG_CNTR3_ATID_EN0__ATID17_EN___S 17 +#define DBG_CNTR3_ATID_EN0__ATID16_EN___M 0x00010000 +#define DBG_CNTR3_ATID_EN0__ATID16_EN___S 16 +#define DBG_CNTR3_ATID_EN0__ATID15_EN___M 0x00008000 +#define DBG_CNTR3_ATID_EN0__ATID15_EN___S 15 +#define DBG_CNTR3_ATID_EN0__ATID14_EN___M 0x00004000 +#define DBG_CNTR3_ATID_EN0__ATID14_EN___S 14 +#define DBG_CNTR3_ATID_EN0__ATID13_EN___M 0x00002000 +#define DBG_CNTR3_ATID_EN0__ATID13_EN___S 13 +#define DBG_CNTR3_ATID_EN0__ATID12_EN___M 0x00001000 +#define DBG_CNTR3_ATID_EN0__ATID12_EN___S 12 +#define DBG_CNTR3_ATID_EN0__ATID11_EN___M 0x00000800 +#define DBG_CNTR3_ATID_EN0__ATID11_EN___S 11 +#define DBG_CNTR3_ATID_EN0__ATID10_EN___M 0x00000400 +#define DBG_CNTR3_ATID_EN0__ATID10_EN___S 10 +#define DBG_CNTR3_ATID_EN0__ATID9_EN___M 0x00000200 +#define DBG_CNTR3_ATID_EN0__ATID9_EN___S 9 +#define DBG_CNTR3_ATID_EN0__ATID8_EN___M 0x00000100 +#define DBG_CNTR3_ATID_EN0__ATID8_EN___S 8 +#define DBG_CNTR3_ATID_EN0__ATID7_EN___M 0x00000080 +#define DBG_CNTR3_ATID_EN0__ATID7_EN___S 7 +#define DBG_CNTR3_ATID_EN0__ATID6_EN___M 0x00000040 +#define DBG_CNTR3_ATID_EN0__ATID6_EN___S 6 +#define DBG_CNTR3_ATID_EN0__ATID5_EN___M 0x00000020 +#define DBG_CNTR3_ATID_EN0__ATID5_EN___S 5 +#define DBG_CNTR3_ATID_EN0__ATID4_EN___M 0x00000010 +#define DBG_CNTR3_ATID_EN0__ATID4_EN___S 4 +#define DBG_CNTR3_ATID_EN0__ATID3_EN___M 0x00000008 +#define DBG_CNTR3_ATID_EN0__ATID3_EN___S 3 +#define DBG_CNTR3_ATID_EN0__ATID2_EN___M 0x00000004 +#define DBG_CNTR3_ATID_EN0__ATID2_EN___S 2 +#define DBG_CNTR3_ATID_EN0__ATID1_EN___M 0x00000002 +#define DBG_CNTR3_ATID_EN0__ATID1_EN___S 1 +#define DBG_CNTR3_ATID_EN0__ATID0_EN___M 0x00000001 +#define DBG_CNTR3_ATID_EN0__ATID0_EN___S 0 + +#define DBG_CNTRn_ATID_EN1(n) (0x00BC1008+0x40*(n)) +#define DBG_CNTRn_ATID_EN1_nMIN 0 +#define DBG_CNTRn_ATID_EN1_nMAX 3 +#define DBG_CNTRn_ATID_EN1_ELEM 4 +#define DBG_CNTRn_ATID_EN1___RWC QCSR_REG_RW +#define DBG_CNTRn_ATID_EN1___POR 0xFFFFFFFF +#define DBG_CNTRn_ATID_EN1__ATID63_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN1__ATID62_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN1__ATID61_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN1__ATID60_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN1__ATID59_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN1__ATID58_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN1__ATID57_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN1__ATID56_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN1__ATID55_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN1__ATID54_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN1__ATID53_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN1__ATID52_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN1__ATID51_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN1__ATID50_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN1__ATID49_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN1__ATID48_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN1__ATID47_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN1__ATID46_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN1__ATID45_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN1__ATID44_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN1__ATID43_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN1__ATID42_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN1__ATID41_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN1__ATID40_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN1__ATID39_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN1__ATID38_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN1__ATID37_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN1__ATID36_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN1__ATID35_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN1__ATID34_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN1__ATID33_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN1__ATID32_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN1__ATID63_EN___M 0x80000000 +#define DBG_CNTRn_ATID_EN1__ATID63_EN___S 31 +#define DBG_CNTRn_ATID_EN1__ATID63_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN1__ATID63_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN1__ATID62_EN___M 0x40000000 +#define DBG_CNTRn_ATID_EN1__ATID62_EN___S 30 +#define DBG_CNTRn_ATID_EN1__ATID62_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN1__ATID62_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN1__ATID61_EN___M 0x20000000 +#define DBG_CNTRn_ATID_EN1__ATID61_EN___S 29 +#define DBG_CNTRn_ATID_EN1__ATID61_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN1__ATID61_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN1__ATID60_EN___M 0x10000000 +#define DBG_CNTRn_ATID_EN1__ATID60_EN___S 28 +#define DBG_CNTRn_ATID_EN1__ATID60_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN1__ATID60_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN1__ATID59_EN___M 0x08000000 +#define DBG_CNTRn_ATID_EN1__ATID59_EN___S 27 +#define DBG_CNTRn_ATID_EN1__ATID59_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN1__ATID59_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN1__ATID58_EN___M 0x04000000 +#define DBG_CNTRn_ATID_EN1__ATID58_EN___S 26 +#define DBG_CNTRn_ATID_EN1__ATID58_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN1__ATID58_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN1__ATID57_EN___M 0x02000000 +#define DBG_CNTRn_ATID_EN1__ATID57_EN___S 25 +#define DBG_CNTRn_ATID_EN1__ATID57_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN1__ATID57_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN1__ATID56_EN___M 0x01000000 +#define DBG_CNTRn_ATID_EN1__ATID56_EN___S 24 +#define DBG_CNTRn_ATID_EN1__ATID56_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN1__ATID56_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN1__ATID55_EN___M 0x00800000 +#define DBG_CNTRn_ATID_EN1__ATID55_EN___S 23 +#define DBG_CNTRn_ATID_EN1__ATID55_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN1__ATID55_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN1__ATID54_EN___M 0x00400000 +#define DBG_CNTRn_ATID_EN1__ATID54_EN___S 22 +#define DBG_CNTRn_ATID_EN1__ATID54_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN1__ATID54_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN1__ATID53_EN___M 0x00200000 +#define DBG_CNTRn_ATID_EN1__ATID53_EN___S 21 +#define DBG_CNTRn_ATID_EN1__ATID53_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN1__ATID53_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN1__ATID52_EN___M 0x00100000 +#define DBG_CNTRn_ATID_EN1__ATID52_EN___S 20 +#define DBG_CNTRn_ATID_EN1__ATID52_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN1__ATID52_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN1__ATID51_EN___M 0x00080000 +#define DBG_CNTRn_ATID_EN1__ATID51_EN___S 19 +#define DBG_CNTRn_ATID_EN1__ATID51_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN1__ATID51_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN1__ATID50_EN___M 0x00040000 +#define DBG_CNTRn_ATID_EN1__ATID50_EN___S 18 +#define DBG_CNTRn_ATID_EN1__ATID50_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN1__ATID50_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN1__ATID49_EN___M 0x00020000 +#define DBG_CNTRn_ATID_EN1__ATID49_EN___S 17 +#define DBG_CNTRn_ATID_EN1__ATID49_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN1__ATID49_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN1__ATID48_EN___M 0x00010000 +#define DBG_CNTRn_ATID_EN1__ATID48_EN___S 16 +#define DBG_CNTRn_ATID_EN1__ATID48_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN1__ATID48_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN1__ATID47_EN___M 0x00008000 +#define DBG_CNTRn_ATID_EN1__ATID47_EN___S 15 +#define DBG_CNTRn_ATID_EN1__ATID47_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN1__ATID47_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN1__ATID46_EN___M 0x00004000 +#define DBG_CNTRn_ATID_EN1__ATID46_EN___S 14 +#define DBG_CNTRn_ATID_EN1__ATID46_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN1__ATID46_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN1__ATID45_EN___M 0x00002000 +#define DBG_CNTRn_ATID_EN1__ATID45_EN___S 13 +#define DBG_CNTRn_ATID_EN1__ATID45_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN1__ATID45_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN1__ATID44_EN___M 0x00001000 +#define DBG_CNTRn_ATID_EN1__ATID44_EN___S 12 +#define DBG_CNTRn_ATID_EN1__ATID44_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN1__ATID44_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN1__ATID43_EN___M 0x00000800 +#define DBG_CNTRn_ATID_EN1__ATID43_EN___S 11 +#define DBG_CNTRn_ATID_EN1__ATID43_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN1__ATID43_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN1__ATID42_EN___M 0x00000400 +#define DBG_CNTRn_ATID_EN1__ATID42_EN___S 10 +#define DBG_CNTRn_ATID_EN1__ATID42_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN1__ATID42_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN1__ATID41_EN___M 0x00000200 +#define DBG_CNTRn_ATID_EN1__ATID41_EN___S 9 +#define DBG_CNTRn_ATID_EN1__ATID41_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN1__ATID41_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN1__ATID40_EN___M 0x00000100 +#define DBG_CNTRn_ATID_EN1__ATID40_EN___S 8 +#define DBG_CNTRn_ATID_EN1__ATID40_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN1__ATID40_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN1__ATID39_EN___M 0x00000080 +#define DBG_CNTRn_ATID_EN1__ATID39_EN___S 7 +#define DBG_CNTRn_ATID_EN1__ATID39_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN1__ATID39_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN1__ATID38_EN___M 0x00000040 +#define DBG_CNTRn_ATID_EN1__ATID38_EN___S 6 +#define DBG_CNTRn_ATID_EN1__ATID38_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN1__ATID38_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN1__ATID37_EN___M 0x00000020 +#define DBG_CNTRn_ATID_EN1__ATID37_EN___S 5 +#define DBG_CNTRn_ATID_EN1__ATID37_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN1__ATID37_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN1__ATID36_EN___M 0x00000010 +#define DBG_CNTRn_ATID_EN1__ATID36_EN___S 4 +#define DBG_CNTRn_ATID_EN1__ATID36_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN1__ATID36_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN1__ATID35_EN___M 0x00000008 +#define DBG_CNTRn_ATID_EN1__ATID35_EN___S 3 +#define DBG_CNTRn_ATID_EN1__ATID35_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN1__ATID35_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN1__ATID34_EN___M 0x00000004 +#define DBG_CNTRn_ATID_EN1__ATID34_EN___S 2 +#define DBG_CNTRn_ATID_EN1__ATID34_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN1__ATID34_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN1__ATID33_EN___M 0x00000002 +#define DBG_CNTRn_ATID_EN1__ATID33_EN___S 1 +#define DBG_CNTRn_ATID_EN1__ATID33_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN1__ATID33_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN1__ATID32_EN___M 0x00000001 +#define DBG_CNTRn_ATID_EN1__ATID32_EN___S 0 +#define DBG_CNTRn_ATID_EN1__ATID32_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN1__ATID32_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN1___M 0xFFFFFFFF +#define DBG_CNTRn_ATID_EN1___S 0 +#define DBG_CNTR0_ATID_EN1 (0x00BC1008) +#define DBG_CNTR0_ATID_EN1___RWC QCSR_REG_RW +#define DBG_CNTR0_ATID_EN1__ATID63_EN___M 0x80000000 +#define DBG_CNTR0_ATID_EN1__ATID63_EN___S 31 +#define DBG_CNTR0_ATID_EN1__ATID62_EN___M 0x40000000 +#define DBG_CNTR0_ATID_EN1__ATID62_EN___S 30 +#define DBG_CNTR0_ATID_EN1__ATID61_EN___M 0x20000000 +#define DBG_CNTR0_ATID_EN1__ATID61_EN___S 29 +#define DBG_CNTR0_ATID_EN1__ATID60_EN___M 0x10000000 +#define DBG_CNTR0_ATID_EN1__ATID60_EN___S 28 +#define DBG_CNTR0_ATID_EN1__ATID59_EN___M 0x08000000 +#define DBG_CNTR0_ATID_EN1__ATID59_EN___S 27 +#define DBG_CNTR0_ATID_EN1__ATID58_EN___M 0x04000000 +#define DBG_CNTR0_ATID_EN1__ATID58_EN___S 26 +#define DBG_CNTR0_ATID_EN1__ATID57_EN___M 0x02000000 +#define DBG_CNTR0_ATID_EN1__ATID57_EN___S 25 +#define DBG_CNTR0_ATID_EN1__ATID56_EN___M 0x01000000 +#define DBG_CNTR0_ATID_EN1__ATID56_EN___S 24 +#define DBG_CNTR0_ATID_EN1__ATID55_EN___M 0x00800000 +#define DBG_CNTR0_ATID_EN1__ATID55_EN___S 23 +#define DBG_CNTR0_ATID_EN1__ATID54_EN___M 0x00400000 +#define DBG_CNTR0_ATID_EN1__ATID54_EN___S 22 +#define DBG_CNTR0_ATID_EN1__ATID53_EN___M 0x00200000 +#define DBG_CNTR0_ATID_EN1__ATID53_EN___S 21 +#define DBG_CNTR0_ATID_EN1__ATID52_EN___M 0x00100000 +#define DBG_CNTR0_ATID_EN1__ATID52_EN___S 20 +#define DBG_CNTR0_ATID_EN1__ATID51_EN___M 0x00080000 +#define DBG_CNTR0_ATID_EN1__ATID51_EN___S 19 +#define DBG_CNTR0_ATID_EN1__ATID50_EN___M 0x00040000 +#define DBG_CNTR0_ATID_EN1__ATID50_EN___S 18 +#define DBG_CNTR0_ATID_EN1__ATID49_EN___M 0x00020000 +#define DBG_CNTR0_ATID_EN1__ATID49_EN___S 17 +#define DBG_CNTR0_ATID_EN1__ATID48_EN___M 0x00010000 +#define DBG_CNTR0_ATID_EN1__ATID48_EN___S 16 +#define DBG_CNTR0_ATID_EN1__ATID47_EN___M 0x00008000 +#define DBG_CNTR0_ATID_EN1__ATID47_EN___S 15 +#define DBG_CNTR0_ATID_EN1__ATID46_EN___M 0x00004000 +#define DBG_CNTR0_ATID_EN1__ATID46_EN___S 14 +#define DBG_CNTR0_ATID_EN1__ATID45_EN___M 0x00002000 +#define DBG_CNTR0_ATID_EN1__ATID45_EN___S 13 +#define DBG_CNTR0_ATID_EN1__ATID44_EN___M 0x00001000 +#define DBG_CNTR0_ATID_EN1__ATID44_EN___S 12 +#define DBG_CNTR0_ATID_EN1__ATID43_EN___M 0x00000800 +#define DBG_CNTR0_ATID_EN1__ATID43_EN___S 11 +#define DBG_CNTR0_ATID_EN1__ATID42_EN___M 0x00000400 +#define DBG_CNTR0_ATID_EN1__ATID42_EN___S 10 +#define DBG_CNTR0_ATID_EN1__ATID41_EN___M 0x00000200 +#define DBG_CNTR0_ATID_EN1__ATID41_EN___S 9 +#define DBG_CNTR0_ATID_EN1__ATID40_EN___M 0x00000100 +#define DBG_CNTR0_ATID_EN1__ATID40_EN___S 8 +#define DBG_CNTR0_ATID_EN1__ATID39_EN___M 0x00000080 +#define DBG_CNTR0_ATID_EN1__ATID39_EN___S 7 +#define DBG_CNTR0_ATID_EN1__ATID38_EN___M 0x00000040 +#define DBG_CNTR0_ATID_EN1__ATID38_EN___S 6 +#define DBG_CNTR0_ATID_EN1__ATID37_EN___M 0x00000020 +#define DBG_CNTR0_ATID_EN1__ATID37_EN___S 5 +#define DBG_CNTR0_ATID_EN1__ATID36_EN___M 0x00000010 +#define DBG_CNTR0_ATID_EN1__ATID36_EN___S 4 +#define DBG_CNTR0_ATID_EN1__ATID35_EN___M 0x00000008 +#define DBG_CNTR0_ATID_EN1__ATID35_EN___S 3 +#define DBG_CNTR0_ATID_EN1__ATID34_EN___M 0x00000004 +#define DBG_CNTR0_ATID_EN1__ATID34_EN___S 2 +#define DBG_CNTR0_ATID_EN1__ATID33_EN___M 0x00000002 +#define DBG_CNTR0_ATID_EN1__ATID33_EN___S 1 +#define DBG_CNTR0_ATID_EN1__ATID32_EN___M 0x00000001 +#define DBG_CNTR0_ATID_EN1__ATID32_EN___S 0 +#define DBG_CNTR1_ATID_EN1 (0x00BC1048) +#define DBG_CNTR1_ATID_EN1___RWC QCSR_REG_RW +#define DBG_CNTR1_ATID_EN1__ATID63_EN___M 0x80000000 +#define DBG_CNTR1_ATID_EN1__ATID63_EN___S 31 +#define DBG_CNTR1_ATID_EN1__ATID62_EN___M 0x40000000 +#define DBG_CNTR1_ATID_EN1__ATID62_EN___S 30 +#define DBG_CNTR1_ATID_EN1__ATID61_EN___M 0x20000000 +#define DBG_CNTR1_ATID_EN1__ATID61_EN___S 29 +#define DBG_CNTR1_ATID_EN1__ATID60_EN___M 0x10000000 +#define DBG_CNTR1_ATID_EN1__ATID60_EN___S 28 +#define DBG_CNTR1_ATID_EN1__ATID59_EN___M 0x08000000 +#define DBG_CNTR1_ATID_EN1__ATID59_EN___S 27 +#define DBG_CNTR1_ATID_EN1__ATID58_EN___M 0x04000000 +#define DBG_CNTR1_ATID_EN1__ATID58_EN___S 26 +#define DBG_CNTR1_ATID_EN1__ATID57_EN___M 0x02000000 +#define DBG_CNTR1_ATID_EN1__ATID57_EN___S 25 +#define DBG_CNTR1_ATID_EN1__ATID56_EN___M 0x01000000 +#define DBG_CNTR1_ATID_EN1__ATID56_EN___S 24 +#define DBG_CNTR1_ATID_EN1__ATID55_EN___M 0x00800000 +#define DBG_CNTR1_ATID_EN1__ATID55_EN___S 23 +#define DBG_CNTR1_ATID_EN1__ATID54_EN___M 0x00400000 +#define DBG_CNTR1_ATID_EN1__ATID54_EN___S 22 +#define DBG_CNTR1_ATID_EN1__ATID53_EN___M 0x00200000 +#define DBG_CNTR1_ATID_EN1__ATID53_EN___S 21 +#define DBG_CNTR1_ATID_EN1__ATID52_EN___M 0x00100000 +#define DBG_CNTR1_ATID_EN1__ATID52_EN___S 20 +#define DBG_CNTR1_ATID_EN1__ATID51_EN___M 0x00080000 +#define DBG_CNTR1_ATID_EN1__ATID51_EN___S 19 +#define DBG_CNTR1_ATID_EN1__ATID50_EN___M 0x00040000 +#define DBG_CNTR1_ATID_EN1__ATID50_EN___S 18 +#define DBG_CNTR1_ATID_EN1__ATID49_EN___M 0x00020000 +#define DBG_CNTR1_ATID_EN1__ATID49_EN___S 17 +#define DBG_CNTR1_ATID_EN1__ATID48_EN___M 0x00010000 +#define DBG_CNTR1_ATID_EN1__ATID48_EN___S 16 +#define DBG_CNTR1_ATID_EN1__ATID47_EN___M 0x00008000 +#define DBG_CNTR1_ATID_EN1__ATID47_EN___S 15 +#define DBG_CNTR1_ATID_EN1__ATID46_EN___M 0x00004000 +#define DBG_CNTR1_ATID_EN1__ATID46_EN___S 14 +#define DBG_CNTR1_ATID_EN1__ATID45_EN___M 0x00002000 +#define DBG_CNTR1_ATID_EN1__ATID45_EN___S 13 +#define DBG_CNTR1_ATID_EN1__ATID44_EN___M 0x00001000 +#define DBG_CNTR1_ATID_EN1__ATID44_EN___S 12 +#define DBG_CNTR1_ATID_EN1__ATID43_EN___M 0x00000800 +#define DBG_CNTR1_ATID_EN1__ATID43_EN___S 11 +#define DBG_CNTR1_ATID_EN1__ATID42_EN___M 0x00000400 +#define DBG_CNTR1_ATID_EN1__ATID42_EN___S 10 +#define DBG_CNTR1_ATID_EN1__ATID41_EN___M 0x00000200 +#define DBG_CNTR1_ATID_EN1__ATID41_EN___S 9 +#define DBG_CNTR1_ATID_EN1__ATID40_EN___M 0x00000100 +#define DBG_CNTR1_ATID_EN1__ATID40_EN___S 8 +#define DBG_CNTR1_ATID_EN1__ATID39_EN___M 0x00000080 +#define DBG_CNTR1_ATID_EN1__ATID39_EN___S 7 +#define DBG_CNTR1_ATID_EN1__ATID38_EN___M 0x00000040 +#define DBG_CNTR1_ATID_EN1__ATID38_EN___S 6 +#define DBG_CNTR1_ATID_EN1__ATID37_EN___M 0x00000020 +#define DBG_CNTR1_ATID_EN1__ATID37_EN___S 5 +#define DBG_CNTR1_ATID_EN1__ATID36_EN___M 0x00000010 +#define DBG_CNTR1_ATID_EN1__ATID36_EN___S 4 +#define DBG_CNTR1_ATID_EN1__ATID35_EN___M 0x00000008 +#define DBG_CNTR1_ATID_EN1__ATID35_EN___S 3 +#define DBG_CNTR1_ATID_EN1__ATID34_EN___M 0x00000004 +#define DBG_CNTR1_ATID_EN1__ATID34_EN___S 2 +#define DBG_CNTR1_ATID_EN1__ATID33_EN___M 0x00000002 +#define DBG_CNTR1_ATID_EN1__ATID33_EN___S 1 +#define DBG_CNTR1_ATID_EN1__ATID32_EN___M 0x00000001 +#define DBG_CNTR1_ATID_EN1__ATID32_EN___S 0 +#define DBG_CNTR2_ATID_EN1 (0x00BC1088) +#define DBG_CNTR2_ATID_EN1___RWC QCSR_REG_RW +#define DBG_CNTR2_ATID_EN1__ATID63_EN___M 0x80000000 +#define DBG_CNTR2_ATID_EN1__ATID63_EN___S 31 +#define DBG_CNTR2_ATID_EN1__ATID62_EN___M 0x40000000 +#define DBG_CNTR2_ATID_EN1__ATID62_EN___S 30 +#define DBG_CNTR2_ATID_EN1__ATID61_EN___M 0x20000000 +#define DBG_CNTR2_ATID_EN1__ATID61_EN___S 29 +#define DBG_CNTR2_ATID_EN1__ATID60_EN___M 0x10000000 +#define DBG_CNTR2_ATID_EN1__ATID60_EN___S 28 +#define DBG_CNTR2_ATID_EN1__ATID59_EN___M 0x08000000 +#define DBG_CNTR2_ATID_EN1__ATID59_EN___S 27 +#define DBG_CNTR2_ATID_EN1__ATID58_EN___M 0x04000000 +#define DBG_CNTR2_ATID_EN1__ATID58_EN___S 26 +#define DBG_CNTR2_ATID_EN1__ATID57_EN___M 0x02000000 +#define DBG_CNTR2_ATID_EN1__ATID57_EN___S 25 +#define DBG_CNTR2_ATID_EN1__ATID56_EN___M 0x01000000 +#define DBG_CNTR2_ATID_EN1__ATID56_EN___S 24 +#define DBG_CNTR2_ATID_EN1__ATID55_EN___M 0x00800000 +#define DBG_CNTR2_ATID_EN1__ATID55_EN___S 23 +#define DBG_CNTR2_ATID_EN1__ATID54_EN___M 0x00400000 +#define DBG_CNTR2_ATID_EN1__ATID54_EN___S 22 +#define DBG_CNTR2_ATID_EN1__ATID53_EN___M 0x00200000 +#define DBG_CNTR2_ATID_EN1__ATID53_EN___S 21 +#define DBG_CNTR2_ATID_EN1__ATID52_EN___M 0x00100000 +#define DBG_CNTR2_ATID_EN1__ATID52_EN___S 20 +#define DBG_CNTR2_ATID_EN1__ATID51_EN___M 0x00080000 +#define DBG_CNTR2_ATID_EN1__ATID51_EN___S 19 +#define DBG_CNTR2_ATID_EN1__ATID50_EN___M 0x00040000 +#define DBG_CNTR2_ATID_EN1__ATID50_EN___S 18 +#define DBG_CNTR2_ATID_EN1__ATID49_EN___M 0x00020000 +#define DBG_CNTR2_ATID_EN1__ATID49_EN___S 17 +#define DBG_CNTR2_ATID_EN1__ATID48_EN___M 0x00010000 +#define DBG_CNTR2_ATID_EN1__ATID48_EN___S 16 +#define DBG_CNTR2_ATID_EN1__ATID47_EN___M 0x00008000 +#define DBG_CNTR2_ATID_EN1__ATID47_EN___S 15 +#define DBG_CNTR2_ATID_EN1__ATID46_EN___M 0x00004000 +#define DBG_CNTR2_ATID_EN1__ATID46_EN___S 14 +#define DBG_CNTR2_ATID_EN1__ATID45_EN___M 0x00002000 +#define DBG_CNTR2_ATID_EN1__ATID45_EN___S 13 +#define DBG_CNTR2_ATID_EN1__ATID44_EN___M 0x00001000 +#define DBG_CNTR2_ATID_EN1__ATID44_EN___S 12 +#define DBG_CNTR2_ATID_EN1__ATID43_EN___M 0x00000800 +#define DBG_CNTR2_ATID_EN1__ATID43_EN___S 11 +#define DBG_CNTR2_ATID_EN1__ATID42_EN___M 0x00000400 +#define DBG_CNTR2_ATID_EN1__ATID42_EN___S 10 +#define DBG_CNTR2_ATID_EN1__ATID41_EN___M 0x00000200 +#define DBG_CNTR2_ATID_EN1__ATID41_EN___S 9 +#define DBG_CNTR2_ATID_EN1__ATID40_EN___M 0x00000100 +#define DBG_CNTR2_ATID_EN1__ATID40_EN___S 8 +#define DBG_CNTR2_ATID_EN1__ATID39_EN___M 0x00000080 +#define DBG_CNTR2_ATID_EN1__ATID39_EN___S 7 +#define DBG_CNTR2_ATID_EN1__ATID38_EN___M 0x00000040 +#define DBG_CNTR2_ATID_EN1__ATID38_EN___S 6 +#define DBG_CNTR2_ATID_EN1__ATID37_EN___M 0x00000020 +#define DBG_CNTR2_ATID_EN1__ATID37_EN___S 5 +#define DBG_CNTR2_ATID_EN1__ATID36_EN___M 0x00000010 +#define DBG_CNTR2_ATID_EN1__ATID36_EN___S 4 +#define DBG_CNTR2_ATID_EN1__ATID35_EN___M 0x00000008 +#define DBG_CNTR2_ATID_EN1__ATID35_EN___S 3 +#define DBG_CNTR2_ATID_EN1__ATID34_EN___M 0x00000004 +#define DBG_CNTR2_ATID_EN1__ATID34_EN___S 2 +#define DBG_CNTR2_ATID_EN1__ATID33_EN___M 0x00000002 +#define DBG_CNTR2_ATID_EN1__ATID33_EN___S 1 +#define DBG_CNTR2_ATID_EN1__ATID32_EN___M 0x00000001 +#define DBG_CNTR2_ATID_EN1__ATID32_EN___S 0 +#define DBG_CNTR3_ATID_EN1 (0x00BC10C8) +#define DBG_CNTR3_ATID_EN1___RWC QCSR_REG_RW +#define DBG_CNTR3_ATID_EN1__ATID63_EN___M 0x80000000 +#define DBG_CNTR3_ATID_EN1__ATID63_EN___S 31 +#define DBG_CNTR3_ATID_EN1__ATID62_EN___M 0x40000000 +#define DBG_CNTR3_ATID_EN1__ATID62_EN___S 30 +#define DBG_CNTR3_ATID_EN1__ATID61_EN___M 0x20000000 +#define DBG_CNTR3_ATID_EN1__ATID61_EN___S 29 +#define DBG_CNTR3_ATID_EN1__ATID60_EN___M 0x10000000 +#define DBG_CNTR3_ATID_EN1__ATID60_EN___S 28 +#define DBG_CNTR3_ATID_EN1__ATID59_EN___M 0x08000000 +#define DBG_CNTR3_ATID_EN1__ATID59_EN___S 27 +#define DBG_CNTR3_ATID_EN1__ATID58_EN___M 0x04000000 +#define DBG_CNTR3_ATID_EN1__ATID58_EN___S 26 +#define DBG_CNTR3_ATID_EN1__ATID57_EN___M 0x02000000 +#define DBG_CNTR3_ATID_EN1__ATID57_EN___S 25 +#define DBG_CNTR3_ATID_EN1__ATID56_EN___M 0x01000000 +#define DBG_CNTR3_ATID_EN1__ATID56_EN___S 24 +#define DBG_CNTR3_ATID_EN1__ATID55_EN___M 0x00800000 +#define DBG_CNTR3_ATID_EN1__ATID55_EN___S 23 +#define DBG_CNTR3_ATID_EN1__ATID54_EN___M 0x00400000 +#define DBG_CNTR3_ATID_EN1__ATID54_EN___S 22 +#define DBG_CNTR3_ATID_EN1__ATID53_EN___M 0x00200000 +#define DBG_CNTR3_ATID_EN1__ATID53_EN___S 21 +#define DBG_CNTR3_ATID_EN1__ATID52_EN___M 0x00100000 +#define DBG_CNTR3_ATID_EN1__ATID52_EN___S 20 +#define DBG_CNTR3_ATID_EN1__ATID51_EN___M 0x00080000 +#define DBG_CNTR3_ATID_EN1__ATID51_EN___S 19 +#define DBG_CNTR3_ATID_EN1__ATID50_EN___M 0x00040000 +#define DBG_CNTR3_ATID_EN1__ATID50_EN___S 18 +#define DBG_CNTR3_ATID_EN1__ATID49_EN___M 0x00020000 +#define DBG_CNTR3_ATID_EN1__ATID49_EN___S 17 +#define DBG_CNTR3_ATID_EN1__ATID48_EN___M 0x00010000 +#define DBG_CNTR3_ATID_EN1__ATID48_EN___S 16 +#define DBG_CNTR3_ATID_EN1__ATID47_EN___M 0x00008000 +#define DBG_CNTR3_ATID_EN1__ATID47_EN___S 15 +#define DBG_CNTR3_ATID_EN1__ATID46_EN___M 0x00004000 +#define DBG_CNTR3_ATID_EN1__ATID46_EN___S 14 +#define DBG_CNTR3_ATID_EN1__ATID45_EN___M 0x00002000 +#define DBG_CNTR3_ATID_EN1__ATID45_EN___S 13 +#define DBG_CNTR3_ATID_EN1__ATID44_EN___M 0x00001000 +#define DBG_CNTR3_ATID_EN1__ATID44_EN___S 12 +#define DBG_CNTR3_ATID_EN1__ATID43_EN___M 0x00000800 +#define DBG_CNTR3_ATID_EN1__ATID43_EN___S 11 +#define DBG_CNTR3_ATID_EN1__ATID42_EN___M 0x00000400 +#define DBG_CNTR3_ATID_EN1__ATID42_EN___S 10 +#define DBG_CNTR3_ATID_EN1__ATID41_EN___M 0x00000200 +#define DBG_CNTR3_ATID_EN1__ATID41_EN___S 9 +#define DBG_CNTR3_ATID_EN1__ATID40_EN___M 0x00000100 +#define DBG_CNTR3_ATID_EN1__ATID40_EN___S 8 +#define DBG_CNTR3_ATID_EN1__ATID39_EN___M 0x00000080 +#define DBG_CNTR3_ATID_EN1__ATID39_EN___S 7 +#define DBG_CNTR3_ATID_EN1__ATID38_EN___M 0x00000040 +#define DBG_CNTR3_ATID_EN1__ATID38_EN___S 6 +#define DBG_CNTR3_ATID_EN1__ATID37_EN___M 0x00000020 +#define DBG_CNTR3_ATID_EN1__ATID37_EN___S 5 +#define DBG_CNTR3_ATID_EN1__ATID36_EN___M 0x00000010 +#define DBG_CNTR3_ATID_EN1__ATID36_EN___S 4 +#define DBG_CNTR3_ATID_EN1__ATID35_EN___M 0x00000008 +#define DBG_CNTR3_ATID_EN1__ATID35_EN___S 3 +#define DBG_CNTR3_ATID_EN1__ATID34_EN___M 0x00000004 +#define DBG_CNTR3_ATID_EN1__ATID34_EN___S 2 +#define DBG_CNTR3_ATID_EN1__ATID33_EN___M 0x00000002 +#define DBG_CNTR3_ATID_EN1__ATID33_EN___S 1 +#define DBG_CNTR3_ATID_EN1__ATID32_EN___M 0x00000001 +#define DBG_CNTR3_ATID_EN1__ATID32_EN___S 0 + +#define DBG_CNTRn_ATID_EN2(n) (0x00BC100C+0x40*(n)) +#define DBG_CNTRn_ATID_EN2_nMIN 0 +#define DBG_CNTRn_ATID_EN2_nMAX 3 +#define DBG_CNTRn_ATID_EN2_ELEM 4 +#define DBG_CNTRn_ATID_EN2___RWC QCSR_REG_RW +#define DBG_CNTRn_ATID_EN2___POR 0xFFFFFFFF +#define DBG_CNTRn_ATID_EN2__ATID95_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN2__ATID94_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN2__ATID93_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN2__ATID92_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN2__ATID91_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN2__ATID90_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN2__ATID89_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN2__ATID88_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN2__ATID87_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN2__ATID86_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN2__ATID85_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN2__ATID84_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN2__ATID83_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN2__ATID82_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN2__ATID81_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN2__ATID80_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN2__ATID79_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN2__ATID78_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN2__ATID77_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN2__ATID76_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN2__ATID75_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN2__ATID74_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN2__ATID73_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN2__ATID72_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN2__ATID71_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN2__ATID70_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN2__ATID69_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN2__ATID68_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN2__ATID67_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN2__ATID66_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN2__ATID65_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN2__ATID64_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN2__ATID95_EN___M 0x80000000 +#define DBG_CNTRn_ATID_EN2__ATID95_EN___S 31 +#define DBG_CNTRn_ATID_EN2__ATID95_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN2__ATID95_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN2__ATID94_EN___M 0x40000000 +#define DBG_CNTRn_ATID_EN2__ATID94_EN___S 30 +#define DBG_CNTRn_ATID_EN2__ATID94_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN2__ATID94_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN2__ATID93_EN___M 0x20000000 +#define DBG_CNTRn_ATID_EN2__ATID93_EN___S 29 +#define DBG_CNTRn_ATID_EN2__ATID93_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN2__ATID93_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN2__ATID92_EN___M 0x10000000 +#define DBG_CNTRn_ATID_EN2__ATID92_EN___S 28 +#define DBG_CNTRn_ATID_EN2__ATID92_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN2__ATID92_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN2__ATID91_EN___M 0x08000000 +#define DBG_CNTRn_ATID_EN2__ATID91_EN___S 27 +#define DBG_CNTRn_ATID_EN2__ATID91_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN2__ATID91_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN2__ATID90_EN___M 0x04000000 +#define DBG_CNTRn_ATID_EN2__ATID90_EN___S 26 +#define DBG_CNTRn_ATID_EN2__ATID90_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN2__ATID90_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN2__ATID89_EN___M 0x02000000 +#define DBG_CNTRn_ATID_EN2__ATID89_EN___S 25 +#define DBG_CNTRn_ATID_EN2__ATID89_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN2__ATID89_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN2__ATID88_EN___M 0x01000000 +#define DBG_CNTRn_ATID_EN2__ATID88_EN___S 24 +#define DBG_CNTRn_ATID_EN2__ATID88_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN2__ATID88_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN2__ATID87_EN___M 0x00800000 +#define DBG_CNTRn_ATID_EN2__ATID87_EN___S 23 +#define DBG_CNTRn_ATID_EN2__ATID87_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN2__ATID87_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN2__ATID86_EN___M 0x00400000 +#define DBG_CNTRn_ATID_EN2__ATID86_EN___S 22 +#define DBG_CNTRn_ATID_EN2__ATID86_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN2__ATID86_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN2__ATID85_EN___M 0x00200000 +#define DBG_CNTRn_ATID_EN2__ATID85_EN___S 21 +#define DBG_CNTRn_ATID_EN2__ATID85_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN2__ATID85_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN2__ATID84_EN___M 0x00100000 +#define DBG_CNTRn_ATID_EN2__ATID84_EN___S 20 +#define DBG_CNTRn_ATID_EN2__ATID84_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN2__ATID84_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN2__ATID83_EN___M 0x00080000 +#define DBG_CNTRn_ATID_EN2__ATID83_EN___S 19 +#define DBG_CNTRn_ATID_EN2__ATID83_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN2__ATID83_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN2__ATID82_EN___M 0x00040000 +#define DBG_CNTRn_ATID_EN2__ATID82_EN___S 18 +#define DBG_CNTRn_ATID_EN2__ATID82_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN2__ATID82_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN2__ATID81_EN___M 0x00020000 +#define DBG_CNTRn_ATID_EN2__ATID81_EN___S 17 +#define DBG_CNTRn_ATID_EN2__ATID81_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN2__ATID81_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN2__ATID80_EN___M 0x00010000 +#define DBG_CNTRn_ATID_EN2__ATID80_EN___S 16 +#define DBG_CNTRn_ATID_EN2__ATID80_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN2__ATID80_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN2__ATID79_EN___M 0x00008000 +#define DBG_CNTRn_ATID_EN2__ATID79_EN___S 15 +#define DBG_CNTRn_ATID_EN2__ATID79_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN2__ATID79_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN2__ATID78_EN___M 0x00004000 +#define DBG_CNTRn_ATID_EN2__ATID78_EN___S 14 +#define DBG_CNTRn_ATID_EN2__ATID78_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN2__ATID78_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN2__ATID77_EN___M 0x00002000 +#define DBG_CNTRn_ATID_EN2__ATID77_EN___S 13 +#define DBG_CNTRn_ATID_EN2__ATID77_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN2__ATID77_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN2__ATID76_EN___M 0x00001000 +#define DBG_CNTRn_ATID_EN2__ATID76_EN___S 12 +#define DBG_CNTRn_ATID_EN2__ATID76_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN2__ATID76_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN2__ATID75_EN___M 0x00000800 +#define DBG_CNTRn_ATID_EN2__ATID75_EN___S 11 +#define DBG_CNTRn_ATID_EN2__ATID75_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN2__ATID75_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN2__ATID74_EN___M 0x00000400 +#define DBG_CNTRn_ATID_EN2__ATID74_EN___S 10 +#define DBG_CNTRn_ATID_EN2__ATID74_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN2__ATID74_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN2__ATID73_EN___M 0x00000200 +#define DBG_CNTRn_ATID_EN2__ATID73_EN___S 9 +#define DBG_CNTRn_ATID_EN2__ATID73_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN2__ATID73_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN2__ATID72_EN___M 0x00000100 +#define DBG_CNTRn_ATID_EN2__ATID72_EN___S 8 +#define DBG_CNTRn_ATID_EN2__ATID72_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN2__ATID72_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN2__ATID71_EN___M 0x00000080 +#define DBG_CNTRn_ATID_EN2__ATID71_EN___S 7 +#define DBG_CNTRn_ATID_EN2__ATID71_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN2__ATID71_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN2__ATID70_EN___M 0x00000040 +#define DBG_CNTRn_ATID_EN2__ATID70_EN___S 6 +#define DBG_CNTRn_ATID_EN2__ATID70_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN2__ATID70_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN2__ATID69_EN___M 0x00000020 +#define DBG_CNTRn_ATID_EN2__ATID69_EN___S 5 +#define DBG_CNTRn_ATID_EN2__ATID69_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN2__ATID69_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN2__ATID68_EN___M 0x00000010 +#define DBG_CNTRn_ATID_EN2__ATID68_EN___S 4 +#define DBG_CNTRn_ATID_EN2__ATID68_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN2__ATID68_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN2__ATID67_EN___M 0x00000008 +#define DBG_CNTRn_ATID_EN2__ATID67_EN___S 3 +#define DBG_CNTRn_ATID_EN2__ATID67_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN2__ATID67_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN2__ATID66_EN___M 0x00000004 +#define DBG_CNTRn_ATID_EN2__ATID66_EN___S 2 +#define DBG_CNTRn_ATID_EN2__ATID66_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN2__ATID66_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN2__ATID65_EN___M 0x00000002 +#define DBG_CNTRn_ATID_EN2__ATID65_EN___S 1 +#define DBG_CNTRn_ATID_EN2__ATID65_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN2__ATID65_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN2__ATID64_EN___M 0x00000001 +#define DBG_CNTRn_ATID_EN2__ATID64_EN___S 0 +#define DBG_CNTRn_ATID_EN2__ATID64_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN2__ATID64_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN2___M 0xFFFFFFFF +#define DBG_CNTRn_ATID_EN2___S 0 +#define DBG_CNTR0_ATID_EN2 (0x00BC100C) +#define DBG_CNTR0_ATID_EN2___RWC QCSR_REG_RW +#define DBG_CNTR0_ATID_EN2__ATID95_EN___M 0x80000000 +#define DBG_CNTR0_ATID_EN2__ATID95_EN___S 31 +#define DBG_CNTR0_ATID_EN2__ATID94_EN___M 0x40000000 +#define DBG_CNTR0_ATID_EN2__ATID94_EN___S 30 +#define DBG_CNTR0_ATID_EN2__ATID93_EN___M 0x20000000 +#define DBG_CNTR0_ATID_EN2__ATID93_EN___S 29 +#define DBG_CNTR0_ATID_EN2__ATID92_EN___M 0x10000000 +#define DBG_CNTR0_ATID_EN2__ATID92_EN___S 28 +#define DBG_CNTR0_ATID_EN2__ATID91_EN___M 0x08000000 +#define DBG_CNTR0_ATID_EN2__ATID91_EN___S 27 +#define DBG_CNTR0_ATID_EN2__ATID90_EN___M 0x04000000 +#define DBG_CNTR0_ATID_EN2__ATID90_EN___S 26 +#define DBG_CNTR0_ATID_EN2__ATID89_EN___M 0x02000000 +#define DBG_CNTR0_ATID_EN2__ATID89_EN___S 25 +#define DBG_CNTR0_ATID_EN2__ATID88_EN___M 0x01000000 +#define DBG_CNTR0_ATID_EN2__ATID88_EN___S 24 +#define DBG_CNTR0_ATID_EN2__ATID87_EN___M 0x00800000 +#define DBG_CNTR0_ATID_EN2__ATID87_EN___S 23 +#define DBG_CNTR0_ATID_EN2__ATID86_EN___M 0x00400000 +#define DBG_CNTR0_ATID_EN2__ATID86_EN___S 22 +#define DBG_CNTR0_ATID_EN2__ATID85_EN___M 0x00200000 +#define DBG_CNTR0_ATID_EN2__ATID85_EN___S 21 +#define DBG_CNTR0_ATID_EN2__ATID84_EN___M 0x00100000 +#define DBG_CNTR0_ATID_EN2__ATID84_EN___S 20 +#define DBG_CNTR0_ATID_EN2__ATID83_EN___M 0x00080000 +#define DBG_CNTR0_ATID_EN2__ATID83_EN___S 19 +#define DBG_CNTR0_ATID_EN2__ATID82_EN___M 0x00040000 +#define DBG_CNTR0_ATID_EN2__ATID82_EN___S 18 +#define DBG_CNTR0_ATID_EN2__ATID81_EN___M 0x00020000 +#define DBG_CNTR0_ATID_EN2__ATID81_EN___S 17 +#define DBG_CNTR0_ATID_EN2__ATID80_EN___M 0x00010000 +#define DBG_CNTR0_ATID_EN2__ATID80_EN___S 16 +#define DBG_CNTR0_ATID_EN2__ATID79_EN___M 0x00008000 +#define DBG_CNTR0_ATID_EN2__ATID79_EN___S 15 +#define DBG_CNTR0_ATID_EN2__ATID78_EN___M 0x00004000 +#define DBG_CNTR0_ATID_EN2__ATID78_EN___S 14 +#define DBG_CNTR0_ATID_EN2__ATID77_EN___M 0x00002000 +#define DBG_CNTR0_ATID_EN2__ATID77_EN___S 13 +#define DBG_CNTR0_ATID_EN2__ATID76_EN___M 0x00001000 +#define DBG_CNTR0_ATID_EN2__ATID76_EN___S 12 +#define DBG_CNTR0_ATID_EN2__ATID75_EN___M 0x00000800 +#define DBG_CNTR0_ATID_EN2__ATID75_EN___S 11 +#define DBG_CNTR0_ATID_EN2__ATID74_EN___M 0x00000400 +#define DBG_CNTR0_ATID_EN2__ATID74_EN___S 10 +#define DBG_CNTR0_ATID_EN2__ATID73_EN___M 0x00000200 +#define DBG_CNTR0_ATID_EN2__ATID73_EN___S 9 +#define DBG_CNTR0_ATID_EN2__ATID72_EN___M 0x00000100 +#define DBG_CNTR0_ATID_EN2__ATID72_EN___S 8 +#define DBG_CNTR0_ATID_EN2__ATID71_EN___M 0x00000080 +#define DBG_CNTR0_ATID_EN2__ATID71_EN___S 7 +#define DBG_CNTR0_ATID_EN2__ATID70_EN___M 0x00000040 +#define DBG_CNTR0_ATID_EN2__ATID70_EN___S 6 +#define DBG_CNTR0_ATID_EN2__ATID69_EN___M 0x00000020 +#define DBG_CNTR0_ATID_EN2__ATID69_EN___S 5 +#define DBG_CNTR0_ATID_EN2__ATID68_EN___M 0x00000010 +#define DBG_CNTR0_ATID_EN2__ATID68_EN___S 4 +#define DBG_CNTR0_ATID_EN2__ATID67_EN___M 0x00000008 +#define DBG_CNTR0_ATID_EN2__ATID67_EN___S 3 +#define DBG_CNTR0_ATID_EN2__ATID66_EN___M 0x00000004 +#define DBG_CNTR0_ATID_EN2__ATID66_EN___S 2 +#define DBG_CNTR0_ATID_EN2__ATID65_EN___M 0x00000002 +#define DBG_CNTR0_ATID_EN2__ATID65_EN___S 1 +#define DBG_CNTR0_ATID_EN2__ATID64_EN___M 0x00000001 +#define DBG_CNTR0_ATID_EN2__ATID64_EN___S 0 +#define DBG_CNTR1_ATID_EN2 (0x00BC104C) +#define DBG_CNTR1_ATID_EN2___RWC QCSR_REG_RW +#define DBG_CNTR1_ATID_EN2__ATID95_EN___M 0x80000000 +#define DBG_CNTR1_ATID_EN2__ATID95_EN___S 31 +#define DBG_CNTR1_ATID_EN2__ATID94_EN___M 0x40000000 +#define DBG_CNTR1_ATID_EN2__ATID94_EN___S 30 +#define DBG_CNTR1_ATID_EN2__ATID93_EN___M 0x20000000 +#define DBG_CNTR1_ATID_EN2__ATID93_EN___S 29 +#define DBG_CNTR1_ATID_EN2__ATID92_EN___M 0x10000000 +#define DBG_CNTR1_ATID_EN2__ATID92_EN___S 28 +#define DBG_CNTR1_ATID_EN2__ATID91_EN___M 0x08000000 +#define DBG_CNTR1_ATID_EN2__ATID91_EN___S 27 +#define DBG_CNTR1_ATID_EN2__ATID90_EN___M 0x04000000 +#define DBG_CNTR1_ATID_EN2__ATID90_EN___S 26 +#define DBG_CNTR1_ATID_EN2__ATID89_EN___M 0x02000000 +#define DBG_CNTR1_ATID_EN2__ATID89_EN___S 25 +#define DBG_CNTR1_ATID_EN2__ATID88_EN___M 0x01000000 +#define DBG_CNTR1_ATID_EN2__ATID88_EN___S 24 +#define DBG_CNTR1_ATID_EN2__ATID87_EN___M 0x00800000 +#define DBG_CNTR1_ATID_EN2__ATID87_EN___S 23 +#define DBG_CNTR1_ATID_EN2__ATID86_EN___M 0x00400000 +#define DBG_CNTR1_ATID_EN2__ATID86_EN___S 22 +#define DBG_CNTR1_ATID_EN2__ATID85_EN___M 0x00200000 +#define DBG_CNTR1_ATID_EN2__ATID85_EN___S 21 +#define DBG_CNTR1_ATID_EN2__ATID84_EN___M 0x00100000 +#define DBG_CNTR1_ATID_EN2__ATID84_EN___S 20 +#define DBG_CNTR1_ATID_EN2__ATID83_EN___M 0x00080000 +#define DBG_CNTR1_ATID_EN2__ATID83_EN___S 19 +#define DBG_CNTR1_ATID_EN2__ATID82_EN___M 0x00040000 +#define DBG_CNTR1_ATID_EN2__ATID82_EN___S 18 +#define DBG_CNTR1_ATID_EN2__ATID81_EN___M 0x00020000 +#define DBG_CNTR1_ATID_EN2__ATID81_EN___S 17 +#define DBG_CNTR1_ATID_EN2__ATID80_EN___M 0x00010000 +#define DBG_CNTR1_ATID_EN2__ATID80_EN___S 16 +#define DBG_CNTR1_ATID_EN2__ATID79_EN___M 0x00008000 +#define DBG_CNTR1_ATID_EN2__ATID79_EN___S 15 +#define DBG_CNTR1_ATID_EN2__ATID78_EN___M 0x00004000 +#define DBG_CNTR1_ATID_EN2__ATID78_EN___S 14 +#define DBG_CNTR1_ATID_EN2__ATID77_EN___M 0x00002000 +#define DBG_CNTR1_ATID_EN2__ATID77_EN___S 13 +#define DBG_CNTR1_ATID_EN2__ATID76_EN___M 0x00001000 +#define DBG_CNTR1_ATID_EN2__ATID76_EN___S 12 +#define DBG_CNTR1_ATID_EN2__ATID75_EN___M 0x00000800 +#define DBG_CNTR1_ATID_EN2__ATID75_EN___S 11 +#define DBG_CNTR1_ATID_EN2__ATID74_EN___M 0x00000400 +#define DBG_CNTR1_ATID_EN2__ATID74_EN___S 10 +#define DBG_CNTR1_ATID_EN2__ATID73_EN___M 0x00000200 +#define DBG_CNTR1_ATID_EN2__ATID73_EN___S 9 +#define DBG_CNTR1_ATID_EN2__ATID72_EN___M 0x00000100 +#define DBG_CNTR1_ATID_EN2__ATID72_EN___S 8 +#define DBG_CNTR1_ATID_EN2__ATID71_EN___M 0x00000080 +#define DBG_CNTR1_ATID_EN2__ATID71_EN___S 7 +#define DBG_CNTR1_ATID_EN2__ATID70_EN___M 0x00000040 +#define DBG_CNTR1_ATID_EN2__ATID70_EN___S 6 +#define DBG_CNTR1_ATID_EN2__ATID69_EN___M 0x00000020 +#define DBG_CNTR1_ATID_EN2__ATID69_EN___S 5 +#define DBG_CNTR1_ATID_EN2__ATID68_EN___M 0x00000010 +#define DBG_CNTR1_ATID_EN2__ATID68_EN___S 4 +#define DBG_CNTR1_ATID_EN2__ATID67_EN___M 0x00000008 +#define DBG_CNTR1_ATID_EN2__ATID67_EN___S 3 +#define DBG_CNTR1_ATID_EN2__ATID66_EN___M 0x00000004 +#define DBG_CNTR1_ATID_EN2__ATID66_EN___S 2 +#define DBG_CNTR1_ATID_EN2__ATID65_EN___M 0x00000002 +#define DBG_CNTR1_ATID_EN2__ATID65_EN___S 1 +#define DBG_CNTR1_ATID_EN2__ATID64_EN___M 0x00000001 +#define DBG_CNTR1_ATID_EN2__ATID64_EN___S 0 +#define DBG_CNTR2_ATID_EN2 (0x00BC108C) +#define DBG_CNTR2_ATID_EN2___RWC QCSR_REG_RW +#define DBG_CNTR2_ATID_EN2__ATID95_EN___M 0x80000000 +#define DBG_CNTR2_ATID_EN2__ATID95_EN___S 31 +#define DBG_CNTR2_ATID_EN2__ATID94_EN___M 0x40000000 +#define DBG_CNTR2_ATID_EN2__ATID94_EN___S 30 +#define DBG_CNTR2_ATID_EN2__ATID93_EN___M 0x20000000 +#define DBG_CNTR2_ATID_EN2__ATID93_EN___S 29 +#define DBG_CNTR2_ATID_EN2__ATID92_EN___M 0x10000000 +#define DBG_CNTR2_ATID_EN2__ATID92_EN___S 28 +#define DBG_CNTR2_ATID_EN2__ATID91_EN___M 0x08000000 +#define DBG_CNTR2_ATID_EN2__ATID91_EN___S 27 +#define DBG_CNTR2_ATID_EN2__ATID90_EN___M 0x04000000 +#define DBG_CNTR2_ATID_EN2__ATID90_EN___S 26 +#define DBG_CNTR2_ATID_EN2__ATID89_EN___M 0x02000000 +#define DBG_CNTR2_ATID_EN2__ATID89_EN___S 25 +#define DBG_CNTR2_ATID_EN2__ATID88_EN___M 0x01000000 +#define DBG_CNTR2_ATID_EN2__ATID88_EN___S 24 +#define DBG_CNTR2_ATID_EN2__ATID87_EN___M 0x00800000 +#define DBG_CNTR2_ATID_EN2__ATID87_EN___S 23 +#define DBG_CNTR2_ATID_EN2__ATID86_EN___M 0x00400000 +#define DBG_CNTR2_ATID_EN2__ATID86_EN___S 22 +#define DBG_CNTR2_ATID_EN2__ATID85_EN___M 0x00200000 +#define DBG_CNTR2_ATID_EN2__ATID85_EN___S 21 +#define DBG_CNTR2_ATID_EN2__ATID84_EN___M 0x00100000 +#define DBG_CNTR2_ATID_EN2__ATID84_EN___S 20 +#define DBG_CNTR2_ATID_EN2__ATID83_EN___M 0x00080000 +#define DBG_CNTR2_ATID_EN2__ATID83_EN___S 19 +#define DBG_CNTR2_ATID_EN2__ATID82_EN___M 0x00040000 +#define DBG_CNTR2_ATID_EN2__ATID82_EN___S 18 +#define DBG_CNTR2_ATID_EN2__ATID81_EN___M 0x00020000 +#define DBG_CNTR2_ATID_EN2__ATID81_EN___S 17 +#define DBG_CNTR2_ATID_EN2__ATID80_EN___M 0x00010000 +#define DBG_CNTR2_ATID_EN2__ATID80_EN___S 16 +#define DBG_CNTR2_ATID_EN2__ATID79_EN___M 0x00008000 +#define DBG_CNTR2_ATID_EN2__ATID79_EN___S 15 +#define DBG_CNTR2_ATID_EN2__ATID78_EN___M 0x00004000 +#define DBG_CNTR2_ATID_EN2__ATID78_EN___S 14 +#define DBG_CNTR2_ATID_EN2__ATID77_EN___M 0x00002000 +#define DBG_CNTR2_ATID_EN2__ATID77_EN___S 13 +#define DBG_CNTR2_ATID_EN2__ATID76_EN___M 0x00001000 +#define DBG_CNTR2_ATID_EN2__ATID76_EN___S 12 +#define DBG_CNTR2_ATID_EN2__ATID75_EN___M 0x00000800 +#define DBG_CNTR2_ATID_EN2__ATID75_EN___S 11 +#define DBG_CNTR2_ATID_EN2__ATID74_EN___M 0x00000400 +#define DBG_CNTR2_ATID_EN2__ATID74_EN___S 10 +#define DBG_CNTR2_ATID_EN2__ATID73_EN___M 0x00000200 +#define DBG_CNTR2_ATID_EN2__ATID73_EN___S 9 +#define DBG_CNTR2_ATID_EN2__ATID72_EN___M 0x00000100 +#define DBG_CNTR2_ATID_EN2__ATID72_EN___S 8 +#define DBG_CNTR2_ATID_EN2__ATID71_EN___M 0x00000080 +#define DBG_CNTR2_ATID_EN2__ATID71_EN___S 7 +#define DBG_CNTR2_ATID_EN2__ATID70_EN___M 0x00000040 +#define DBG_CNTR2_ATID_EN2__ATID70_EN___S 6 +#define DBG_CNTR2_ATID_EN2__ATID69_EN___M 0x00000020 +#define DBG_CNTR2_ATID_EN2__ATID69_EN___S 5 +#define DBG_CNTR2_ATID_EN2__ATID68_EN___M 0x00000010 +#define DBG_CNTR2_ATID_EN2__ATID68_EN___S 4 +#define DBG_CNTR2_ATID_EN2__ATID67_EN___M 0x00000008 +#define DBG_CNTR2_ATID_EN2__ATID67_EN___S 3 +#define DBG_CNTR2_ATID_EN2__ATID66_EN___M 0x00000004 +#define DBG_CNTR2_ATID_EN2__ATID66_EN___S 2 +#define DBG_CNTR2_ATID_EN2__ATID65_EN___M 0x00000002 +#define DBG_CNTR2_ATID_EN2__ATID65_EN___S 1 +#define DBG_CNTR2_ATID_EN2__ATID64_EN___M 0x00000001 +#define DBG_CNTR2_ATID_EN2__ATID64_EN___S 0 +#define DBG_CNTR3_ATID_EN2 (0x00BC10CC) +#define DBG_CNTR3_ATID_EN2___RWC QCSR_REG_RW +#define DBG_CNTR3_ATID_EN2__ATID95_EN___M 0x80000000 +#define DBG_CNTR3_ATID_EN2__ATID95_EN___S 31 +#define DBG_CNTR3_ATID_EN2__ATID94_EN___M 0x40000000 +#define DBG_CNTR3_ATID_EN2__ATID94_EN___S 30 +#define DBG_CNTR3_ATID_EN2__ATID93_EN___M 0x20000000 +#define DBG_CNTR3_ATID_EN2__ATID93_EN___S 29 +#define DBG_CNTR3_ATID_EN2__ATID92_EN___M 0x10000000 +#define DBG_CNTR3_ATID_EN2__ATID92_EN___S 28 +#define DBG_CNTR3_ATID_EN2__ATID91_EN___M 0x08000000 +#define DBG_CNTR3_ATID_EN2__ATID91_EN___S 27 +#define DBG_CNTR3_ATID_EN2__ATID90_EN___M 0x04000000 +#define DBG_CNTR3_ATID_EN2__ATID90_EN___S 26 +#define DBG_CNTR3_ATID_EN2__ATID89_EN___M 0x02000000 +#define DBG_CNTR3_ATID_EN2__ATID89_EN___S 25 +#define DBG_CNTR3_ATID_EN2__ATID88_EN___M 0x01000000 +#define DBG_CNTR3_ATID_EN2__ATID88_EN___S 24 +#define DBG_CNTR3_ATID_EN2__ATID87_EN___M 0x00800000 +#define DBG_CNTR3_ATID_EN2__ATID87_EN___S 23 +#define DBG_CNTR3_ATID_EN2__ATID86_EN___M 0x00400000 +#define DBG_CNTR3_ATID_EN2__ATID86_EN___S 22 +#define DBG_CNTR3_ATID_EN2__ATID85_EN___M 0x00200000 +#define DBG_CNTR3_ATID_EN2__ATID85_EN___S 21 +#define DBG_CNTR3_ATID_EN2__ATID84_EN___M 0x00100000 +#define DBG_CNTR3_ATID_EN2__ATID84_EN___S 20 +#define DBG_CNTR3_ATID_EN2__ATID83_EN___M 0x00080000 +#define DBG_CNTR3_ATID_EN2__ATID83_EN___S 19 +#define DBG_CNTR3_ATID_EN2__ATID82_EN___M 0x00040000 +#define DBG_CNTR3_ATID_EN2__ATID82_EN___S 18 +#define DBG_CNTR3_ATID_EN2__ATID81_EN___M 0x00020000 +#define DBG_CNTR3_ATID_EN2__ATID81_EN___S 17 +#define DBG_CNTR3_ATID_EN2__ATID80_EN___M 0x00010000 +#define DBG_CNTR3_ATID_EN2__ATID80_EN___S 16 +#define DBG_CNTR3_ATID_EN2__ATID79_EN___M 0x00008000 +#define DBG_CNTR3_ATID_EN2__ATID79_EN___S 15 +#define DBG_CNTR3_ATID_EN2__ATID78_EN___M 0x00004000 +#define DBG_CNTR3_ATID_EN2__ATID78_EN___S 14 +#define DBG_CNTR3_ATID_EN2__ATID77_EN___M 0x00002000 +#define DBG_CNTR3_ATID_EN2__ATID77_EN___S 13 +#define DBG_CNTR3_ATID_EN2__ATID76_EN___M 0x00001000 +#define DBG_CNTR3_ATID_EN2__ATID76_EN___S 12 +#define DBG_CNTR3_ATID_EN2__ATID75_EN___M 0x00000800 +#define DBG_CNTR3_ATID_EN2__ATID75_EN___S 11 +#define DBG_CNTR3_ATID_EN2__ATID74_EN___M 0x00000400 +#define DBG_CNTR3_ATID_EN2__ATID74_EN___S 10 +#define DBG_CNTR3_ATID_EN2__ATID73_EN___M 0x00000200 +#define DBG_CNTR3_ATID_EN2__ATID73_EN___S 9 +#define DBG_CNTR3_ATID_EN2__ATID72_EN___M 0x00000100 +#define DBG_CNTR3_ATID_EN2__ATID72_EN___S 8 +#define DBG_CNTR3_ATID_EN2__ATID71_EN___M 0x00000080 +#define DBG_CNTR3_ATID_EN2__ATID71_EN___S 7 +#define DBG_CNTR3_ATID_EN2__ATID70_EN___M 0x00000040 +#define DBG_CNTR3_ATID_EN2__ATID70_EN___S 6 +#define DBG_CNTR3_ATID_EN2__ATID69_EN___M 0x00000020 +#define DBG_CNTR3_ATID_EN2__ATID69_EN___S 5 +#define DBG_CNTR3_ATID_EN2__ATID68_EN___M 0x00000010 +#define DBG_CNTR3_ATID_EN2__ATID68_EN___S 4 +#define DBG_CNTR3_ATID_EN2__ATID67_EN___M 0x00000008 +#define DBG_CNTR3_ATID_EN2__ATID67_EN___S 3 +#define DBG_CNTR3_ATID_EN2__ATID66_EN___M 0x00000004 +#define DBG_CNTR3_ATID_EN2__ATID66_EN___S 2 +#define DBG_CNTR3_ATID_EN2__ATID65_EN___M 0x00000002 +#define DBG_CNTR3_ATID_EN2__ATID65_EN___S 1 +#define DBG_CNTR3_ATID_EN2__ATID64_EN___M 0x00000001 +#define DBG_CNTR3_ATID_EN2__ATID64_EN___S 0 + +#define DBG_CNTRn_ATID_EN3(n) (0x00BC1010+0x40*(n)) +#define DBG_CNTRn_ATID_EN3_nMIN 0 +#define DBG_CNTRn_ATID_EN3_nMAX 3 +#define DBG_CNTRn_ATID_EN3_ELEM 4 +#define DBG_CNTRn_ATID_EN3___RWC QCSR_REG_RW +#define DBG_CNTRn_ATID_EN3___POR 0xFFFFFFFF +#define DBG_CNTRn_ATID_EN3__ATID127_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN3__ATID126_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN3__ATID125_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN3__ATID124_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN3__ATID123_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN3__ATID122_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN3__ATID121_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN3__ATID120_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN3__ATID119_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN3__ATID118_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN3__ATID117_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN3__ATID116_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN3__ATID115_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN3__ATID114_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN3__ATID113_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN3__ATID112_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN3__ATID111_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN3__ATID110_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN3__ATID109_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN3__ATID108_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN3__ATID107_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN3__ATID106_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN3__ATID105_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN3__ATID104_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN3__ATID103_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN3__ATID102_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN3__ATID101_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN3__ATID100_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN3__ATID99_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN3__ATID98_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN3__ATID97_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN3__ATID96_EN___POR 0x1 +#define DBG_CNTRn_ATID_EN3__ATID127_EN___M 0x80000000 +#define DBG_CNTRn_ATID_EN3__ATID127_EN___S 31 +#define DBG_CNTRn_ATID_EN3__ATID127_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN3__ATID127_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN3__ATID126_EN___M 0x40000000 +#define DBG_CNTRn_ATID_EN3__ATID126_EN___S 30 +#define DBG_CNTRn_ATID_EN3__ATID126_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN3__ATID126_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN3__ATID125_EN___M 0x20000000 +#define DBG_CNTRn_ATID_EN3__ATID125_EN___S 29 +#define DBG_CNTRn_ATID_EN3__ATID125_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN3__ATID125_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN3__ATID124_EN___M 0x10000000 +#define DBG_CNTRn_ATID_EN3__ATID124_EN___S 28 +#define DBG_CNTRn_ATID_EN3__ATID124_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN3__ATID124_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN3__ATID123_EN___M 0x08000000 +#define DBG_CNTRn_ATID_EN3__ATID123_EN___S 27 +#define DBG_CNTRn_ATID_EN3__ATID123_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN3__ATID123_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN3__ATID122_EN___M 0x04000000 +#define DBG_CNTRn_ATID_EN3__ATID122_EN___S 26 +#define DBG_CNTRn_ATID_EN3__ATID122_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN3__ATID122_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN3__ATID121_EN___M 0x02000000 +#define DBG_CNTRn_ATID_EN3__ATID121_EN___S 25 +#define DBG_CNTRn_ATID_EN3__ATID121_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN3__ATID121_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN3__ATID120_EN___M 0x01000000 +#define DBG_CNTRn_ATID_EN3__ATID120_EN___S 24 +#define DBG_CNTRn_ATID_EN3__ATID120_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN3__ATID120_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN3__ATID119_EN___M 0x00800000 +#define DBG_CNTRn_ATID_EN3__ATID119_EN___S 23 +#define DBG_CNTRn_ATID_EN3__ATID119_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN3__ATID119_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN3__ATID118_EN___M 0x00400000 +#define DBG_CNTRn_ATID_EN3__ATID118_EN___S 22 +#define DBG_CNTRn_ATID_EN3__ATID118_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN3__ATID118_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN3__ATID117_EN___M 0x00200000 +#define DBG_CNTRn_ATID_EN3__ATID117_EN___S 21 +#define DBG_CNTRn_ATID_EN3__ATID117_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN3__ATID117_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN3__ATID116_EN___M 0x00100000 +#define DBG_CNTRn_ATID_EN3__ATID116_EN___S 20 +#define DBG_CNTRn_ATID_EN3__ATID116_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN3__ATID116_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN3__ATID115_EN___M 0x00080000 +#define DBG_CNTRn_ATID_EN3__ATID115_EN___S 19 +#define DBG_CNTRn_ATID_EN3__ATID115_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN3__ATID115_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN3__ATID114_EN___M 0x00040000 +#define DBG_CNTRn_ATID_EN3__ATID114_EN___S 18 +#define DBG_CNTRn_ATID_EN3__ATID114_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN3__ATID114_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN3__ATID113_EN___M 0x00020000 +#define DBG_CNTRn_ATID_EN3__ATID113_EN___S 17 +#define DBG_CNTRn_ATID_EN3__ATID113_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN3__ATID113_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN3__ATID112_EN___M 0x00010000 +#define DBG_CNTRn_ATID_EN3__ATID112_EN___S 16 +#define DBG_CNTRn_ATID_EN3__ATID112_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN3__ATID112_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN3__ATID111_EN___M 0x00008000 +#define DBG_CNTRn_ATID_EN3__ATID111_EN___S 15 +#define DBG_CNTRn_ATID_EN3__ATID111_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN3__ATID111_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN3__ATID110_EN___M 0x00004000 +#define DBG_CNTRn_ATID_EN3__ATID110_EN___S 14 +#define DBG_CNTRn_ATID_EN3__ATID110_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN3__ATID110_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN3__ATID109_EN___M 0x00002000 +#define DBG_CNTRn_ATID_EN3__ATID109_EN___S 13 +#define DBG_CNTRn_ATID_EN3__ATID109_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN3__ATID109_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN3__ATID108_EN___M 0x00001000 +#define DBG_CNTRn_ATID_EN3__ATID108_EN___S 12 +#define DBG_CNTRn_ATID_EN3__ATID108_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN3__ATID108_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN3__ATID107_EN___M 0x00000800 +#define DBG_CNTRn_ATID_EN3__ATID107_EN___S 11 +#define DBG_CNTRn_ATID_EN3__ATID107_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN3__ATID107_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN3__ATID106_EN___M 0x00000400 +#define DBG_CNTRn_ATID_EN3__ATID106_EN___S 10 +#define DBG_CNTRn_ATID_EN3__ATID106_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN3__ATID106_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN3__ATID105_EN___M 0x00000200 +#define DBG_CNTRn_ATID_EN3__ATID105_EN___S 9 +#define DBG_CNTRn_ATID_EN3__ATID105_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN3__ATID105_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN3__ATID104_EN___M 0x00000100 +#define DBG_CNTRn_ATID_EN3__ATID104_EN___S 8 +#define DBG_CNTRn_ATID_EN3__ATID104_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN3__ATID104_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN3__ATID103_EN___M 0x00000080 +#define DBG_CNTRn_ATID_EN3__ATID103_EN___S 7 +#define DBG_CNTRn_ATID_EN3__ATID103_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN3__ATID103_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN3__ATID102_EN___M 0x00000040 +#define DBG_CNTRn_ATID_EN3__ATID102_EN___S 6 +#define DBG_CNTRn_ATID_EN3__ATID102_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN3__ATID102_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN3__ATID101_EN___M 0x00000020 +#define DBG_CNTRn_ATID_EN3__ATID101_EN___S 5 +#define DBG_CNTRn_ATID_EN3__ATID101_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN3__ATID101_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN3__ATID100_EN___M 0x00000010 +#define DBG_CNTRn_ATID_EN3__ATID100_EN___S 4 +#define DBG_CNTRn_ATID_EN3__ATID100_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN3__ATID100_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN3__ATID99_EN___M 0x00000008 +#define DBG_CNTRn_ATID_EN3__ATID99_EN___S 3 +#define DBG_CNTRn_ATID_EN3__ATID99_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN3__ATID99_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN3__ATID98_EN___M 0x00000004 +#define DBG_CNTRn_ATID_EN3__ATID98_EN___S 2 +#define DBG_CNTRn_ATID_EN3__ATID98_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN3__ATID98_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN3__ATID97_EN___M 0x00000002 +#define DBG_CNTRn_ATID_EN3__ATID97_EN___S 1 +#define DBG_CNTRn_ATID_EN3__ATID97_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN3__ATID97_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN3__ATID96_EN___M 0x00000001 +#define DBG_CNTRn_ATID_EN3__ATID96_EN___S 0 +#define DBG_CNTRn_ATID_EN3__ATID96_EN__DISABLE 0x0 +#define DBG_CNTRn_ATID_EN3__ATID96_EN__ENABLE 0x1 +#define DBG_CNTRn_ATID_EN3___M 0xFFFFFFFF +#define DBG_CNTRn_ATID_EN3___S 0 +#define DBG_CNTR0_ATID_EN3 (0x00BC1010) +#define DBG_CNTR0_ATID_EN3___RWC QCSR_REG_RW +#define DBG_CNTR0_ATID_EN3__ATID127_EN___M 0x80000000 +#define DBG_CNTR0_ATID_EN3__ATID127_EN___S 31 +#define DBG_CNTR0_ATID_EN3__ATID126_EN___M 0x40000000 +#define DBG_CNTR0_ATID_EN3__ATID126_EN___S 30 +#define DBG_CNTR0_ATID_EN3__ATID125_EN___M 0x20000000 +#define DBG_CNTR0_ATID_EN3__ATID125_EN___S 29 +#define DBG_CNTR0_ATID_EN3__ATID124_EN___M 0x10000000 +#define DBG_CNTR0_ATID_EN3__ATID124_EN___S 28 +#define DBG_CNTR0_ATID_EN3__ATID123_EN___M 0x08000000 +#define DBG_CNTR0_ATID_EN3__ATID123_EN___S 27 +#define DBG_CNTR0_ATID_EN3__ATID122_EN___M 0x04000000 +#define DBG_CNTR0_ATID_EN3__ATID122_EN___S 26 +#define DBG_CNTR0_ATID_EN3__ATID121_EN___M 0x02000000 +#define DBG_CNTR0_ATID_EN3__ATID121_EN___S 25 +#define DBG_CNTR0_ATID_EN3__ATID120_EN___M 0x01000000 +#define DBG_CNTR0_ATID_EN3__ATID120_EN___S 24 +#define DBG_CNTR0_ATID_EN3__ATID119_EN___M 0x00800000 +#define DBG_CNTR0_ATID_EN3__ATID119_EN___S 23 +#define DBG_CNTR0_ATID_EN3__ATID118_EN___M 0x00400000 +#define DBG_CNTR0_ATID_EN3__ATID118_EN___S 22 +#define DBG_CNTR0_ATID_EN3__ATID117_EN___M 0x00200000 +#define DBG_CNTR0_ATID_EN3__ATID117_EN___S 21 +#define DBG_CNTR0_ATID_EN3__ATID116_EN___M 0x00100000 +#define DBG_CNTR0_ATID_EN3__ATID116_EN___S 20 +#define DBG_CNTR0_ATID_EN3__ATID115_EN___M 0x00080000 +#define DBG_CNTR0_ATID_EN3__ATID115_EN___S 19 +#define DBG_CNTR0_ATID_EN3__ATID114_EN___M 0x00040000 +#define DBG_CNTR0_ATID_EN3__ATID114_EN___S 18 +#define DBG_CNTR0_ATID_EN3__ATID113_EN___M 0x00020000 +#define DBG_CNTR0_ATID_EN3__ATID113_EN___S 17 +#define DBG_CNTR0_ATID_EN3__ATID112_EN___M 0x00010000 +#define DBG_CNTR0_ATID_EN3__ATID112_EN___S 16 +#define DBG_CNTR0_ATID_EN3__ATID111_EN___M 0x00008000 +#define DBG_CNTR0_ATID_EN3__ATID111_EN___S 15 +#define DBG_CNTR0_ATID_EN3__ATID110_EN___M 0x00004000 +#define DBG_CNTR0_ATID_EN3__ATID110_EN___S 14 +#define DBG_CNTR0_ATID_EN3__ATID109_EN___M 0x00002000 +#define DBG_CNTR0_ATID_EN3__ATID109_EN___S 13 +#define DBG_CNTR0_ATID_EN3__ATID108_EN___M 0x00001000 +#define DBG_CNTR0_ATID_EN3__ATID108_EN___S 12 +#define DBG_CNTR0_ATID_EN3__ATID107_EN___M 0x00000800 +#define DBG_CNTR0_ATID_EN3__ATID107_EN___S 11 +#define DBG_CNTR0_ATID_EN3__ATID106_EN___M 0x00000400 +#define DBG_CNTR0_ATID_EN3__ATID106_EN___S 10 +#define DBG_CNTR0_ATID_EN3__ATID105_EN___M 0x00000200 +#define DBG_CNTR0_ATID_EN3__ATID105_EN___S 9 +#define DBG_CNTR0_ATID_EN3__ATID104_EN___M 0x00000100 +#define DBG_CNTR0_ATID_EN3__ATID104_EN___S 8 +#define DBG_CNTR0_ATID_EN3__ATID103_EN___M 0x00000080 +#define DBG_CNTR0_ATID_EN3__ATID103_EN___S 7 +#define DBG_CNTR0_ATID_EN3__ATID102_EN___M 0x00000040 +#define DBG_CNTR0_ATID_EN3__ATID102_EN___S 6 +#define DBG_CNTR0_ATID_EN3__ATID101_EN___M 0x00000020 +#define DBG_CNTR0_ATID_EN3__ATID101_EN___S 5 +#define DBG_CNTR0_ATID_EN3__ATID100_EN___M 0x00000010 +#define DBG_CNTR0_ATID_EN3__ATID100_EN___S 4 +#define DBG_CNTR0_ATID_EN3__ATID99_EN___M 0x00000008 +#define DBG_CNTR0_ATID_EN3__ATID99_EN___S 3 +#define DBG_CNTR0_ATID_EN3__ATID98_EN___M 0x00000004 +#define DBG_CNTR0_ATID_EN3__ATID98_EN___S 2 +#define DBG_CNTR0_ATID_EN3__ATID97_EN___M 0x00000002 +#define DBG_CNTR0_ATID_EN3__ATID97_EN___S 1 +#define DBG_CNTR0_ATID_EN3__ATID96_EN___M 0x00000001 +#define DBG_CNTR0_ATID_EN3__ATID96_EN___S 0 +#define DBG_CNTR1_ATID_EN3 (0x00BC1050) +#define DBG_CNTR1_ATID_EN3___RWC QCSR_REG_RW +#define DBG_CNTR1_ATID_EN3__ATID127_EN___M 0x80000000 +#define DBG_CNTR1_ATID_EN3__ATID127_EN___S 31 +#define DBG_CNTR1_ATID_EN3__ATID126_EN___M 0x40000000 +#define DBG_CNTR1_ATID_EN3__ATID126_EN___S 30 +#define DBG_CNTR1_ATID_EN3__ATID125_EN___M 0x20000000 +#define DBG_CNTR1_ATID_EN3__ATID125_EN___S 29 +#define DBG_CNTR1_ATID_EN3__ATID124_EN___M 0x10000000 +#define DBG_CNTR1_ATID_EN3__ATID124_EN___S 28 +#define DBG_CNTR1_ATID_EN3__ATID123_EN___M 0x08000000 +#define DBG_CNTR1_ATID_EN3__ATID123_EN___S 27 +#define DBG_CNTR1_ATID_EN3__ATID122_EN___M 0x04000000 +#define DBG_CNTR1_ATID_EN3__ATID122_EN___S 26 +#define DBG_CNTR1_ATID_EN3__ATID121_EN___M 0x02000000 +#define DBG_CNTR1_ATID_EN3__ATID121_EN___S 25 +#define DBG_CNTR1_ATID_EN3__ATID120_EN___M 0x01000000 +#define DBG_CNTR1_ATID_EN3__ATID120_EN___S 24 +#define DBG_CNTR1_ATID_EN3__ATID119_EN___M 0x00800000 +#define DBG_CNTR1_ATID_EN3__ATID119_EN___S 23 +#define DBG_CNTR1_ATID_EN3__ATID118_EN___M 0x00400000 +#define DBG_CNTR1_ATID_EN3__ATID118_EN___S 22 +#define DBG_CNTR1_ATID_EN3__ATID117_EN___M 0x00200000 +#define DBG_CNTR1_ATID_EN3__ATID117_EN___S 21 +#define DBG_CNTR1_ATID_EN3__ATID116_EN___M 0x00100000 +#define DBG_CNTR1_ATID_EN3__ATID116_EN___S 20 +#define DBG_CNTR1_ATID_EN3__ATID115_EN___M 0x00080000 +#define DBG_CNTR1_ATID_EN3__ATID115_EN___S 19 +#define DBG_CNTR1_ATID_EN3__ATID114_EN___M 0x00040000 +#define DBG_CNTR1_ATID_EN3__ATID114_EN___S 18 +#define DBG_CNTR1_ATID_EN3__ATID113_EN___M 0x00020000 +#define DBG_CNTR1_ATID_EN3__ATID113_EN___S 17 +#define DBG_CNTR1_ATID_EN3__ATID112_EN___M 0x00010000 +#define DBG_CNTR1_ATID_EN3__ATID112_EN___S 16 +#define DBG_CNTR1_ATID_EN3__ATID111_EN___M 0x00008000 +#define DBG_CNTR1_ATID_EN3__ATID111_EN___S 15 +#define DBG_CNTR1_ATID_EN3__ATID110_EN___M 0x00004000 +#define DBG_CNTR1_ATID_EN3__ATID110_EN___S 14 +#define DBG_CNTR1_ATID_EN3__ATID109_EN___M 0x00002000 +#define DBG_CNTR1_ATID_EN3__ATID109_EN___S 13 +#define DBG_CNTR1_ATID_EN3__ATID108_EN___M 0x00001000 +#define DBG_CNTR1_ATID_EN3__ATID108_EN___S 12 +#define DBG_CNTR1_ATID_EN3__ATID107_EN___M 0x00000800 +#define DBG_CNTR1_ATID_EN3__ATID107_EN___S 11 +#define DBG_CNTR1_ATID_EN3__ATID106_EN___M 0x00000400 +#define DBG_CNTR1_ATID_EN3__ATID106_EN___S 10 +#define DBG_CNTR1_ATID_EN3__ATID105_EN___M 0x00000200 +#define DBG_CNTR1_ATID_EN3__ATID105_EN___S 9 +#define DBG_CNTR1_ATID_EN3__ATID104_EN___M 0x00000100 +#define DBG_CNTR1_ATID_EN3__ATID104_EN___S 8 +#define DBG_CNTR1_ATID_EN3__ATID103_EN___M 0x00000080 +#define DBG_CNTR1_ATID_EN3__ATID103_EN___S 7 +#define DBG_CNTR1_ATID_EN3__ATID102_EN___M 0x00000040 +#define DBG_CNTR1_ATID_EN3__ATID102_EN___S 6 +#define DBG_CNTR1_ATID_EN3__ATID101_EN___M 0x00000020 +#define DBG_CNTR1_ATID_EN3__ATID101_EN___S 5 +#define DBG_CNTR1_ATID_EN3__ATID100_EN___M 0x00000010 +#define DBG_CNTR1_ATID_EN3__ATID100_EN___S 4 +#define DBG_CNTR1_ATID_EN3__ATID99_EN___M 0x00000008 +#define DBG_CNTR1_ATID_EN3__ATID99_EN___S 3 +#define DBG_CNTR1_ATID_EN3__ATID98_EN___M 0x00000004 +#define DBG_CNTR1_ATID_EN3__ATID98_EN___S 2 +#define DBG_CNTR1_ATID_EN3__ATID97_EN___M 0x00000002 +#define DBG_CNTR1_ATID_EN3__ATID97_EN___S 1 +#define DBG_CNTR1_ATID_EN3__ATID96_EN___M 0x00000001 +#define DBG_CNTR1_ATID_EN3__ATID96_EN___S 0 +#define DBG_CNTR2_ATID_EN3 (0x00BC1090) +#define DBG_CNTR2_ATID_EN3___RWC QCSR_REG_RW +#define DBG_CNTR2_ATID_EN3__ATID127_EN___M 0x80000000 +#define DBG_CNTR2_ATID_EN3__ATID127_EN___S 31 +#define DBG_CNTR2_ATID_EN3__ATID126_EN___M 0x40000000 +#define DBG_CNTR2_ATID_EN3__ATID126_EN___S 30 +#define DBG_CNTR2_ATID_EN3__ATID125_EN___M 0x20000000 +#define DBG_CNTR2_ATID_EN3__ATID125_EN___S 29 +#define DBG_CNTR2_ATID_EN3__ATID124_EN___M 0x10000000 +#define DBG_CNTR2_ATID_EN3__ATID124_EN___S 28 +#define DBG_CNTR2_ATID_EN3__ATID123_EN___M 0x08000000 +#define DBG_CNTR2_ATID_EN3__ATID123_EN___S 27 +#define DBG_CNTR2_ATID_EN3__ATID122_EN___M 0x04000000 +#define DBG_CNTR2_ATID_EN3__ATID122_EN___S 26 +#define DBG_CNTR2_ATID_EN3__ATID121_EN___M 0x02000000 +#define DBG_CNTR2_ATID_EN3__ATID121_EN___S 25 +#define DBG_CNTR2_ATID_EN3__ATID120_EN___M 0x01000000 +#define DBG_CNTR2_ATID_EN3__ATID120_EN___S 24 +#define DBG_CNTR2_ATID_EN3__ATID119_EN___M 0x00800000 +#define DBG_CNTR2_ATID_EN3__ATID119_EN___S 23 +#define DBG_CNTR2_ATID_EN3__ATID118_EN___M 0x00400000 +#define DBG_CNTR2_ATID_EN3__ATID118_EN___S 22 +#define DBG_CNTR2_ATID_EN3__ATID117_EN___M 0x00200000 +#define DBG_CNTR2_ATID_EN3__ATID117_EN___S 21 +#define DBG_CNTR2_ATID_EN3__ATID116_EN___M 0x00100000 +#define DBG_CNTR2_ATID_EN3__ATID116_EN___S 20 +#define DBG_CNTR2_ATID_EN3__ATID115_EN___M 0x00080000 +#define DBG_CNTR2_ATID_EN3__ATID115_EN___S 19 +#define DBG_CNTR2_ATID_EN3__ATID114_EN___M 0x00040000 +#define DBG_CNTR2_ATID_EN3__ATID114_EN___S 18 +#define DBG_CNTR2_ATID_EN3__ATID113_EN___M 0x00020000 +#define DBG_CNTR2_ATID_EN3__ATID113_EN___S 17 +#define DBG_CNTR2_ATID_EN3__ATID112_EN___M 0x00010000 +#define DBG_CNTR2_ATID_EN3__ATID112_EN___S 16 +#define DBG_CNTR2_ATID_EN3__ATID111_EN___M 0x00008000 +#define DBG_CNTR2_ATID_EN3__ATID111_EN___S 15 +#define DBG_CNTR2_ATID_EN3__ATID110_EN___M 0x00004000 +#define DBG_CNTR2_ATID_EN3__ATID110_EN___S 14 +#define DBG_CNTR2_ATID_EN3__ATID109_EN___M 0x00002000 +#define DBG_CNTR2_ATID_EN3__ATID109_EN___S 13 +#define DBG_CNTR2_ATID_EN3__ATID108_EN___M 0x00001000 +#define DBG_CNTR2_ATID_EN3__ATID108_EN___S 12 +#define DBG_CNTR2_ATID_EN3__ATID107_EN___M 0x00000800 +#define DBG_CNTR2_ATID_EN3__ATID107_EN___S 11 +#define DBG_CNTR2_ATID_EN3__ATID106_EN___M 0x00000400 +#define DBG_CNTR2_ATID_EN3__ATID106_EN___S 10 +#define DBG_CNTR2_ATID_EN3__ATID105_EN___M 0x00000200 +#define DBG_CNTR2_ATID_EN3__ATID105_EN___S 9 +#define DBG_CNTR2_ATID_EN3__ATID104_EN___M 0x00000100 +#define DBG_CNTR2_ATID_EN3__ATID104_EN___S 8 +#define DBG_CNTR2_ATID_EN3__ATID103_EN___M 0x00000080 +#define DBG_CNTR2_ATID_EN3__ATID103_EN___S 7 +#define DBG_CNTR2_ATID_EN3__ATID102_EN___M 0x00000040 +#define DBG_CNTR2_ATID_EN3__ATID102_EN___S 6 +#define DBG_CNTR2_ATID_EN3__ATID101_EN___M 0x00000020 +#define DBG_CNTR2_ATID_EN3__ATID101_EN___S 5 +#define DBG_CNTR2_ATID_EN3__ATID100_EN___M 0x00000010 +#define DBG_CNTR2_ATID_EN3__ATID100_EN___S 4 +#define DBG_CNTR2_ATID_EN3__ATID99_EN___M 0x00000008 +#define DBG_CNTR2_ATID_EN3__ATID99_EN___S 3 +#define DBG_CNTR2_ATID_EN3__ATID98_EN___M 0x00000004 +#define DBG_CNTR2_ATID_EN3__ATID98_EN___S 2 +#define DBG_CNTR2_ATID_EN3__ATID97_EN___M 0x00000002 +#define DBG_CNTR2_ATID_EN3__ATID97_EN___S 1 +#define DBG_CNTR2_ATID_EN3__ATID96_EN___M 0x00000001 +#define DBG_CNTR2_ATID_EN3__ATID96_EN___S 0 +#define DBG_CNTR3_ATID_EN3 (0x00BC10D0) +#define DBG_CNTR3_ATID_EN3___RWC QCSR_REG_RW +#define DBG_CNTR3_ATID_EN3__ATID127_EN___M 0x80000000 +#define DBG_CNTR3_ATID_EN3__ATID127_EN___S 31 +#define DBG_CNTR3_ATID_EN3__ATID126_EN___M 0x40000000 +#define DBG_CNTR3_ATID_EN3__ATID126_EN___S 30 +#define DBG_CNTR3_ATID_EN3__ATID125_EN___M 0x20000000 +#define DBG_CNTR3_ATID_EN3__ATID125_EN___S 29 +#define DBG_CNTR3_ATID_EN3__ATID124_EN___M 0x10000000 +#define DBG_CNTR3_ATID_EN3__ATID124_EN___S 28 +#define DBG_CNTR3_ATID_EN3__ATID123_EN___M 0x08000000 +#define DBG_CNTR3_ATID_EN3__ATID123_EN___S 27 +#define DBG_CNTR3_ATID_EN3__ATID122_EN___M 0x04000000 +#define DBG_CNTR3_ATID_EN3__ATID122_EN___S 26 +#define DBG_CNTR3_ATID_EN3__ATID121_EN___M 0x02000000 +#define DBG_CNTR3_ATID_EN3__ATID121_EN___S 25 +#define DBG_CNTR3_ATID_EN3__ATID120_EN___M 0x01000000 +#define DBG_CNTR3_ATID_EN3__ATID120_EN___S 24 +#define DBG_CNTR3_ATID_EN3__ATID119_EN___M 0x00800000 +#define DBG_CNTR3_ATID_EN3__ATID119_EN___S 23 +#define DBG_CNTR3_ATID_EN3__ATID118_EN___M 0x00400000 +#define DBG_CNTR3_ATID_EN3__ATID118_EN___S 22 +#define DBG_CNTR3_ATID_EN3__ATID117_EN___M 0x00200000 +#define DBG_CNTR3_ATID_EN3__ATID117_EN___S 21 +#define DBG_CNTR3_ATID_EN3__ATID116_EN___M 0x00100000 +#define DBG_CNTR3_ATID_EN3__ATID116_EN___S 20 +#define DBG_CNTR3_ATID_EN3__ATID115_EN___M 0x00080000 +#define DBG_CNTR3_ATID_EN3__ATID115_EN___S 19 +#define DBG_CNTR3_ATID_EN3__ATID114_EN___M 0x00040000 +#define DBG_CNTR3_ATID_EN3__ATID114_EN___S 18 +#define DBG_CNTR3_ATID_EN3__ATID113_EN___M 0x00020000 +#define DBG_CNTR3_ATID_EN3__ATID113_EN___S 17 +#define DBG_CNTR3_ATID_EN3__ATID112_EN___M 0x00010000 +#define DBG_CNTR3_ATID_EN3__ATID112_EN___S 16 +#define DBG_CNTR3_ATID_EN3__ATID111_EN___M 0x00008000 +#define DBG_CNTR3_ATID_EN3__ATID111_EN___S 15 +#define DBG_CNTR3_ATID_EN3__ATID110_EN___M 0x00004000 +#define DBG_CNTR3_ATID_EN3__ATID110_EN___S 14 +#define DBG_CNTR3_ATID_EN3__ATID109_EN___M 0x00002000 +#define DBG_CNTR3_ATID_EN3__ATID109_EN___S 13 +#define DBG_CNTR3_ATID_EN3__ATID108_EN___M 0x00001000 +#define DBG_CNTR3_ATID_EN3__ATID108_EN___S 12 +#define DBG_CNTR3_ATID_EN3__ATID107_EN___M 0x00000800 +#define DBG_CNTR3_ATID_EN3__ATID107_EN___S 11 +#define DBG_CNTR3_ATID_EN3__ATID106_EN___M 0x00000400 +#define DBG_CNTR3_ATID_EN3__ATID106_EN___S 10 +#define DBG_CNTR3_ATID_EN3__ATID105_EN___M 0x00000200 +#define DBG_CNTR3_ATID_EN3__ATID105_EN___S 9 +#define DBG_CNTR3_ATID_EN3__ATID104_EN___M 0x00000100 +#define DBG_CNTR3_ATID_EN3__ATID104_EN___S 8 +#define DBG_CNTR3_ATID_EN3__ATID103_EN___M 0x00000080 +#define DBG_CNTR3_ATID_EN3__ATID103_EN___S 7 +#define DBG_CNTR3_ATID_EN3__ATID102_EN___M 0x00000040 +#define DBG_CNTR3_ATID_EN3__ATID102_EN___S 6 +#define DBG_CNTR3_ATID_EN3__ATID101_EN___M 0x00000020 +#define DBG_CNTR3_ATID_EN3__ATID101_EN___S 5 +#define DBG_CNTR3_ATID_EN3__ATID100_EN___M 0x00000010 +#define DBG_CNTR3_ATID_EN3__ATID100_EN___S 4 +#define DBG_CNTR3_ATID_EN3__ATID99_EN___M 0x00000008 +#define DBG_CNTR3_ATID_EN3__ATID99_EN___S 3 +#define DBG_CNTR3_ATID_EN3__ATID98_EN___M 0x00000004 +#define DBG_CNTR3_ATID_EN3__ATID98_EN___S 2 +#define DBG_CNTR3_ATID_EN3__ATID97_EN___M 0x00000002 +#define DBG_CNTR3_ATID_EN3__ATID97_EN___S 1 +#define DBG_CNTR3_ATID_EN3__ATID96_EN___M 0x00000001 +#define DBG_CNTR3_ATID_EN3__ATID96_EN___S 0 + +#define DBG_CNTRn_MATCH_CNT(n) (0x00BC1014+0x40*(n)) +#define DBG_CNTRn_MATCH_CNT_nMIN 0 +#define DBG_CNTRn_MATCH_CNT_nMAX 3 +#define DBG_CNTRn_MATCH_CNT_ELEM 4 +#define DBG_CNTRn_MATCH_CNT___RWC QCSR_REG_RW +#define DBG_CNTRn_MATCH_CNT___POR 0x00000000 +#define DBG_CNTRn_MATCH_CNT__VALUE___POR 0x00000000 +#define DBG_CNTRn_MATCH_CNT__VALUE___M 0xFFFFFFFF +#define DBG_CNTRn_MATCH_CNT__VALUE___S 0 +#define DBG_CNTRn_MATCH_CNT___M 0xFFFFFFFF +#define DBG_CNTRn_MATCH_CNT___S 0 +#define DBG_CNTR0_MATCH_CNT (0x00BC1014) +#define DBG_CNTR0_MATCH_CNT___RWC QCSR_REG_RW +#define DBG_CNTR0_MATCH_CNT__VALUE___M 0xFFFFFFFF +#define DBG_CNTR0_MATCH_CNT__VALUE___S 0 +#define DBG_CNTR1_MATCH_CNT (0x00BC1054) +#define DBG_CNTR1_MATCH_CNT___RWC QCSR_REG_RW +#define DBG_CNTR1_MATCH_CNT__VALUE___M 0xFFFFFFFF +#define DBG_CNTR1_MATCH_CNT__VALUE___S 0 +#define DBG_CNTR2_MATCH_CNT (0x00BC1094) +#define DBG_CNTR2_MATCH_CNT___RWC QCSR_REG_RW +#define DBG_CNTR2_MATCH_CNT__VALUE___M 0xFFFFFFFF +#define DBG_CNTR2_MATCH_CNT__VALUE___S 0 +#define DBG_CNTR3_MATCH_CNT (0x00BC10D4) +#define DBG_CNTR3_MATCH_CNT___RWC QCSR_REG_RW +#define DBG_CNTR3_MATCH_CNT__VALUE___M 0xFFFFFFFF +#define DBG_CNTR3_MATCH_CNT__VALUE___S 0 + +#define DBG_CNTRn_CNT(n) (0x00BC101C+0x40*(n)) +#define DBG_CNTRn_CNT_nMIN 0 +#define DBG_CNTRn_CNT_nMAX 3 +#define DBG_CNTRn_CNT_ELEM 4 +#define DBG_CNTRn_CNT___RWC QCSR_REG_RW +#define DBG_CNTRn_CNT___POR 0x00000000 +#define DBG_CNTRn_CNT__VALUE___POR 0x00000000 +#define DBG_CNTRn_CNT__VALUE___M 0xFFFFFFFF +#define DBG_CNTRn_CNT__VALUE___S 0 +#define DBG_CNTRn_CNT___M 0xFFFFFFFF +#define DBG_CNTRn_CNT___S 0 +#define DBG_CNTR0_CNT (0x00BC101C) +#define DBG_CNTR0_CNT___RWC QCSR_REG_RW +#define DBG_CNTR0_CNT__VALUE___M 0xFFFFFFFF +#define DBG_CNTR0_CNT__VALUE___S 0 +#define DBG_CNTR1_CNT (0x00BC105C) +#define DBG_CNTR1_CNT___RWC QCSR_REG_RW +#define DBG_CNTR1_CNT__VALUE___M 0xFFFFFFFF +#define DBG_CNTR1_CNT__VALUE___S 0 +#define DBG_CNTR2_CNT (0x00BC109C) +#define DBG_CNTR2_CNT___RWC QCSR_REG_RW +#define DBG_CNTR2_CNT__VALUE___M 0xFFFFFFFF +#define DBG_CNTR2_CNT__VALUE___S 0 +#define DBG_CNTR3_CNT (0x00BC10DC) +#define DBG_CNTR3_CNT___RWC QCSR_REG_RW +#define DBG_CNTR3_CNT__VALUE___M 0xFFFFFFFF +#define DBG_CNTR3_CNT__VALUE___S 0 + +#define DBG_CNTRn_START_TSTMP_L(n) (0x00BC1024+0x40*(n)) +#define DBG_CNTRn_START_TSTMP_L_nMIN 0 +#define DBG_CNTRn_START_TSTMP_L_nMAX 3 +#define DBG_CNTRn_START_TSTMP_L_ELEM 4 +#define DBG_CNTRn_START_TSTMP_L___RWC QCSR_REG_RO +#define DBG_CNTRn_START_TSTMP_L___POR 0x00000000 +#define DBG_CNTRn_START_TSTMP_L__TSTMP_31_0___POR 0x00000000 +#define DBG_CNTRn_START_TSTMP_L__TSTMP_31_0___M 0xFFFFFFFF +#define DBG_CNTRn_START_TSTMP_L__TSTMP_31_0___S 0 +#define DBG_CNTRn_START_TSTMP_L___M 0xFFFFFFFF +#define DBG_CNTRn_START_TSTMP_L___S 0 +#define DBG_CNTR0_START_TSTMP_L (0x00BC1024) +#define DBG_CNTR0_START_TSTMP_L___RWC QCSR_REG_RO +#define DBG_CNTR0_START_TSTMP_L__TSTMP_31_0___M 0xFFFFFFFF +#define DBG_CNTR0_START_TSTMP_L__TSTMP_31_0___S 0 +#define DBG_CNTR1_START_TSTMP_L (0x00BC1064) +#define DBG_CNTR1_START_TSTMP_L___RWC QCSR_REG_RO +#define DBG_CNTR1_START_TSTMP_L__TSTMP_31_0___M 0xFFFFFFFF +#define DBG_CNTR1_START_TSTMP_L__TSTMP_31_0___S 0 +#define DBG_CNTR2_START_TSTMP_L (0x00BC10A4) +#define DBG_CNTR2_START_TSTMP_L___RWC QCSR_REG_RO +#define DBG_CNTR2_START_TSTMP_L__TSTMP_31_0___M 0xFFFFFFFF +#define DBG_CNTR2_START_TSTMP_L__TSTMP_31_0___S 0 +#define DBG_CNTR3_START_TSTMP_L (0x00BC10E4) +#define DBG_CNTR3_START_TSTMP_L___RWC QCSR_REG_RO +#define DBG_CNTR3_START_TSTMP_L__TSTMP_31_0___M 0xFFFFFFFF +#define DBG_CNTR3_START_TSTMP_L__TSTMP_31_0___S 0 + +#define DBG_CNTRn_START_TSTMP_H(n) (0x00BC1028+0x40*(n)) +#define DBG_CNTRn_START_TSTMP_H_nMIN 0 +#define DBG_CNTRn_START_TSTMP_H_nMAX 3 +#define DBG_CNTRn_START_TSTMP_H_ELEM 4 +#define DBG_CNTRn_START_TSTMP_H___RWC QCSR_REG_RO +#define DBG_CNTRn_START_TSTMP_H___POR 0x00000000 +#define DBG_CNTRn_START_TSTMP_H__TSTMP_63_32___POR 0x00000000 +#define DBG_CNTRn_START_TSTMP_H__TSTMP_63_32___M 0xFFFFFFFF +#define DBG_CNTRn_START_TSTMP_H__TSTMP_63_32___S 0 +#define DBG_CNTRn_START_TSTMP_H___M 0xFFFFFFFF +#define DBG_CNTRn_START_TSTMP_H___S 0 +#define DBG_CNTR0_START_TSTMP_H (0x00BC1028) +#define DBG_CNTR0_START_TSTMP_H___RWC QCSR_REG_RO +#define DBG_CNTR0_START_TSTMP_H__TSTMP_63_32___M 0xFFFFFFFF +#define DBG_CNTR0_START_TSTMP_H__TSTMP_63_32___S 0 +#define DBG_CNTR1_START_TSTMP_H (0x00BC1068) +#define DBG_CNTR1_START_TSTMP_H___RWC QCSR_REG_RO +#define DBG_CNTR1_START_TSTMP_H__TSTMP_63_32___M 0xFFFFFFFF +#define DBG_CNTR1_START_TSTMP_H__TSTMP_63_32___S 0 +#define DBG_CNTR2_START_TSTMP_H (0x00BC10A8) +#define DBG_CNTR2_START_TSTMP_H___RWC QCSR_REG_RO +#define DBG_CNTR2_START_TSTMP_H__TSTMP_63_32___M 0xFFFFFFFF +#define DBG_CNTR2_START_TSTMP_H__TSTMP_63_32___S 0 +#define DBG_CNTR3_START_TSTMP_H (0x00BC10E8) +#define DBG_CNTR3_START_TSTMP_H___RWC QCSR_REG_RO +#define DBG_CNTR3_START_TSTMP_H__TSTMP_63_32___M 0xFFFFFFFF +#define DBG_CNTR3_START_TSTMP_H__TSTMP_63_32___S 0 + +#define DBG_CNTRn_STOP_TSTMP_L(n) (0x00BC102C+0x40*(n)) +#define DBG_CNTRn_STOP_TSTMP_L_nMIN 0 +#define DBG_CNTRn_STOP_TSTMP_L_nMAX 3 +#define DBG_CNTRn_STOP_TSTMP_L_ELEM 4 +#define DBG_CNTRn_STOP_TSTMP_L___RWC QCSR_REG_RO +#define DBG_CNTRn_STOP_TSTMP_L___POR 0x00000000 +#define DBG_CNTRn_STOP_TSTMP_L__TSTMP_31_0___POR 0x00000000 +#define DBG_CNTRn_STOP_TSTMP_L__TSTMP_31_0___M 0xFFFFFFFF +#define DBG_CNTRn_STOP_TSTMP_L__TSTMP_31_0___S 0 +#define DBG_CNTRn_STOP_TSTMP_L___M 0xFFFFFFFF +#define DBG_CNTRn_STOP_TSTMP_L___S 0 +#define DBG_CNTR0_STOP_TSTMP_L (0x00BC102C) +#define DBG_CNTR0_STOP_TSTMP_L___RWC QCSR_REG_RO +#define DBG_CNTR0_STOP_TSTMP_L__TSTMP_31_0___M 0xFFFFFFFF +#define DBG_CNTR0_STOP_TSTMP_L__TSTMP_31_0___S 0 +#define DBG_CNTR1_STOP_TSTMP_L (0x00BC106C) +#define DBG_CNTR1_STOP_TSTMP_L___RWC QCSR_REG_RO +#define DBG_CNTR1_STOP_TSTMP_L__TSTMP_31_0___M 0xFFFFFFFF +#define DBG_CNTR1_STOP_TSTMP_L__TSTMP_31_0___S 0 +#define DBG_CNTR2_STOP_TSTMP_L (0x00BC10AC) +#define DBG_CNTR2_STOP_TSTMP_L___RWC QCSR_REG_RO +#define DBG_CNTR2_STOP_TSTMP_L__TSTMP_31_0___M 0xFFFFFFFF +#define DBG_CNTR2_STOP_TSTMP_L__TSTMP_31_0___S 0 +#define DBG_CNTR3_STOP_TSTMP_L (0x00BC10EC) +#define DBG_CNTR3_STOP_TSTMP_L___RWC QCSR_REG_RO +#define DBG_CNTR3_STOP_TSTMP_L__TSTMP_31_0___M 0xFFFFFFFF +#define DBG_CNTR3_STOP_TSTMP_L__TSTMP_31_0___S 0 + +#define DBG_CNTRn_STOP_TSTMP_H(n) (0x00BC1030+0x40*(n)) +#define DBG_CNTRn_STOP_TSTMP_H_nMIN 0 +#define DBG_CNTRn_STOP_TSTMP_H_nMAX 3 +#define DBG_CNTRn_STOP_TSTMP_H_ELEM 4 +#define DBG_CNTRn_STOP_TSTMP_H___RWC QCSR_REG_RO +#define DBG_CNTRn_STOP_TSTMP_H___POR 0x00000000 +#define DBG_CNTRn_STOP_TSTMP_H__TSTMP_63_32___POR 0x00000000 +#define DBG_CNTRn_STOP_TSTMP_H__TSTMP_63_32___M 0xFFFFFFFF +#define DBG_CNTRn_STOP_TSTMP_H__TSTMP_63_32___S 0 +#define DBG_CNTRn_STOP_TSTMP_H___M 0xFFFFFFFF +#define DBG_CNTRn_STOP_TSTMP_H___S 0 +#define DBG_CNTR0_STOP_TSTMP_H (0x00BC1030) +#define DBG_CNTR0_STOP_TSTMP_H___RWC QCSR_REG_RO +#define DBG_CNTR0_STOP_TSTMP_H__TSTMP_63_32___M 0xFFFFFFFF +#define DBG_CNTR0_STOP_TSTMP_H__TSTMP_63_32___S 0 +#define DBG_CNTR1_STOP_TSTMP_H (0x00BC1070) +#define DBG_CNTR1_STOP_TSTMP_H___RWC QCSR_REG_RO +#define DBG_CNTR1_STOP_TSTMP_H__TSTMP_63_32___M 0xFFFFFFFF +#define DBG_CNTR1_STOP_TSTMP_H__TSTMP_63_32___S 0 +#define DBG_CNTR2_STOP_TSTMP_H (0x00BC10B0) +#define DBG_CNTR2_STOP_TSTMP_H___RWC QCSR_REG_RO +#define DBG_CNTR2_STOP_TSTMP_H__TSTMP_63_32___M 0xFFFFFFFF +#define DBG_CNTR2_STOP_TSTMP_H__TSTMP_63_32___S 0 +#define DBG_CNTR3_STOP_TSTMP_H (0x00BC10F0) +#define DBG_CNTR3_STOP_TSTMP_H___RWC QCSR_REG_RO +#define DBG_CNTR3_STOP_TSTMP_H__TSTMP_63_32___M 0xFFFFFFFF +#define DBG_CNTR3_STOP_TSTMP_H__TSTMP_63_32___S 0 + +#define DBG_TLV_TPDM_CMB_CR (0x00BC2A00) +#define DBG_TLV_TPDM_CMB_CR___RWC QCSR_REG_RW +#define DBG_TLV_TPDM_CMB_CR___POR 0x00000000 +#define DBG_TLV_TPDM_CMB_CR__ATBFLOWERR___POR 0x0 +#define DBG_TLV_TPDM_CMB_CR__EBITSET___POR 0x0 +#define DBG_TLV_TPDM_CMB_CR__FLOWCTRL___POR 0x0 +#define DBG_TLV_TPDM_CMB_CR__MODE___POR 0x0 +#define DBG_TLV_TPDM_CMB_CR__E___POR 0x0 +#define DBG_TLV_TPDM_CMB_CR__ATBFLOWERR___M 0x00000080 +#define DBG_TLV_TPDM_CMB_CR__ATBFLOWERR___S 7 +#define DBG_TLV_TPDM_CMB_CR__EBITSET___M 0x00000040 +#define DBG_TLV_TPDM_CMB_CR__EBITSET___S 6 +#define DBG_TLV_TPDM_CMB_CR__FLOWCTRL___M 0x00000004 +#define DBG_TLV_TPDM_CMB_CR__FLOWCTRL___S 2 +#define DBG_TLV_TPDM_CMB_CR__MODE___M 0x00000002 +#define DBG_TLV_TPDM_CMB_CR__MODE___S 1 +#define DBG_TLV_TPDM_CMB_CR__E___M 0x00000001 +#define DBG_TLV_TPDM_CMB_CR__E___S 0 +#define DBG_TLV_TPDM_CMB_CR___M 0x000000C7 +#define DBG_TLV_TPDM_CMB_CR___S 0 + +#define DBG_TLV_TPDM_CMB_TIER (0x00BC2A04) +#define DBG_TLV_TPDM_CMB_TIER___RWC QCSR_REG_RW +#define DBG_TLV_TPDM_CMB_TIER___POR 0x00000000 +#define DBG_TLV_TPDM_CMB_TIER__TS_ALL___POR 0x0 +#define DBG_TLV_TPDM_CMB_TIER__XTRIG_TSENAB___POR 0x0 +#define DBG_TLV_TPDM_CMB_TIER__PATT_TSENAB___POR 0x0 +#define DBG_TLV_TPDM_CMB_TIER__TS_ALL___M 0x00000004 +#define DBG_TLV_TPDM_CMB_TIER__TS_ALL___S 2 +#define DBG_TLV_TPDM_CMB_TIER__XTRIG_TSENAB___M 0x00000002 +#define DBG_TLV_TPDM_CMB_TIER__XTRIG_TSENAB___S 1 +#define DBG_TLV_TPDM_CMB_TIER__PATT_TSENAB___M 0x00000001 +#define DBG_TLV_TPDM_CMB_TIER__PATT_TSENAB___S 0 +#define DBG_TLV_TPDM_CMB_TIER___M 0x00000007 +#define DBG_TLV_TPDM_CMB_TIER___S 0 + +#define DBG_TLV_TPDM_CMB_TPRn(n) (0x00BC2A08+0x4*(n)) +#define DBG_TLV_TPDM_CMB_TPRn_nMIN 0 +#define DBG_TLV_TPDM_CMB_TPRn_nMAX 0 +#define DBG_TLV_TPDM_CMB_TPRn_ELEM 1 +#define DBG_TLV_TPDM_CMB_TPRn___RWC QCSR_REG_RW +#define DBG_TLV_TPDM_CMB_TPRn___POR 0x00000000 +#define DBG_TLV_TPDM_CMB_TPRn__VAL___POR 0x00000000 +#define DBG_TLV_TPDM_CMB_TPRn__VAL___M 0xFFFFFFFF +#define DBG_TLV_TPDM_CMB_TPRn__VAL___S 0 +#define DBG_TLV_TPDM_CMB_TPRn___M 0xFFFFFFFF +#define DBG_TLV_TPDM_CMB_TPRn___S 0 +#define DBG_TLV_TPDM_CMB_TPR0 (0x00BC2A08) +#define DBG_TLV_TPDM_CMB_TPR0___RWC QCSR_REG_RW +#define DBG_TLV_TPDM_CMB_TPR0__VAL___M 0xFFFFFFFF +#define DBG_TLV_TPDM_CMB_TPR0__VAL___S 0 + +#define DBG_TLV_TPDM_CMB_TPRm(m) (0x00BC2A08+0x4*(m)) +#define DBG_TLV_TPDM_CMB_TPRm_mMIN 1 +#define DBG_TLV_TPDM_CMB_TPRm_mMAX 1 +#define DBG_TLV_TPDM_CMB_TPRm_ELEM 1 +#define DBG_TLV_TPDM_CMB_TPRm___RWC QCSR_REG_RW +#define DBG_TLV_TPDM_CMB_TPRm___POR 0x00000000 +#define DBG_TLV_TPDM_CMB_TPRm__VAL___POR 0x00000000 +#define DBG_TLV_TPDM_CMB_TPRm__VAL___M 0xFFFFFFFF +#define DBG_TLV_TPDM_CMB_TPRm__VAL___S 0 +#define DBG_TLV_TPDM_CMB_TPRm___M 0xFFFFFFFF +#define DBG_TLV_TPDM_CMB_TPRm___S 0 +#define DBG_TLV_TPDM_CMB_TPR1 (0x00BC2A0C) +#define DBG_TLV_TPDM_CMB_TPR1___RWC QCSR_REG_RW +#define DBG_TLV_TPDM_CMB_TPR1__VAL___M 0xFFFFFFFF +#define DBG_TLV_TPDM_CMB_TPR1__VAL___S 0 + +#define DBG_TLV_TPDM_CMB_TPMRn(n) (0x00BC2A10+0x4*(n)) +#define DBG_TLV_TPDM_CMB_TPMRn_nMIN 0 +#define DBG_TLV_TPDM_CMB_TPMRn_nMAX 0 +#define DBG_TLV_TPDM_CMB_TPMRn_ELEM 1 +#define DBG_TLV_TPDM_CMB_TPMRn___RWC QCSR_REG_RW +#define DBG_TLV_TPDM_CMB_TPMRn___POR 0x00000000 +#define DBG_TLV_TPDM_CMB_TPMRn__VAL___POR 0x00000000 +#define DBG_TLV_TPDM_CMB_TPMRn__VAL___M 0xFFFFFFFF +#define DBG_TLV_TPDM_CMB_TPMRn__VAL___S 0 +#define DBG_TLV_TPDM_CMB_TPMRn___M 0xFFFFFFFF +#define DBG_TLV_TPDM_CMB_TPMRn___S 0 +#define DBG_TLV_TPDM_CMB_TPMR0 (0x00BC2A10) +#define DBG_TLV_TPDM_CMB_TPMR0___RWC QCSR_REG_RW +#define DBG_TLV_TPDM_CMB_TPMR0__VAL___M 0xFFFFFFFF +#define DBG_TLV_TPDM_CMB_TPMR0__VAL___S 0 + +#define DBG_TLV_TPDM_CMB_TPMRm(m) (0x00BC2A10+0x4*(m)) +#define DBG_TLV_TPDM_CMB_TPMRm_mMIN 1 +#define DBG_TLV_TPDM_CMB_TPMRm_mMAX 1 +#define DBG_TLV_TPDM_CMB_TPMRm_ELEM 1 +#define DBG_TLV_TPDM_CMB_TPMRm___RWC QCSR_REG_RW +#define DBG_TLV_TPDM_CMB_TPMRm___POR 0x00000000 +#define DBG_TLV_TPDM_CMB_TPMRm__VAL___POR 0x00000000 +#define DBG_TLV_TPDM_CMB_TPMRm__VAL___M 0xFFFFFFFF +#define DBG_TLV_TPDM_CMB_TPMRm__VAL___S 0 +#define DBG_TLV_TPDM_CMB_TPMRm___M 0xFFFFFFFF +#define DBG_TLV_TPDM_CMB_TPMRm___S 0 +#define DBG_TLV_TPDM_CMB_TPMR1 (0x00BC2A14) +#define DBG_TLV_TPDM_CMB_TPMR1___RWC QCSR_REG_RW +#define DBG_TLV_TPDM_CMB_TPMR1__VAL___M 0xFFFFFFFF +#define DBG_TLV_TPDM_CMB_TPMR1__VAL___S 0 + +#define DBG_TLV_TPDM_CMB_XPRn(n) (0x00BC2A18+0x4*(n)) +#define DBG_TLV_TPDM_CMB_XPRn_nMIN 0 +#define DBG_TLV_TPDM_CMB_XPRn_nMAX 0 +#define DBG_TLV_TPDM_CMB_XPRn_ELEM 1 +#define DBG_TLV_TPDM_CMB_XPRn___RWC QCSR_REG_RW +#define DBG_TLV_TPDM_CMB_XPRn___POR 0x00000000 +#define DBG_TLV_TPDM_CMB_XPRn__VAL___POR 0x00000000 +#define DBG_TLV_TPDM_CMB_XPRn__VAL___M 0xFFFFFFFF +#define DBG_TLV_TPDM_CMB_XPRn__VAL___S 0 +#define DBG_TLV_TPDM_CMB_XPRn___M 0xFFFFFFFF +#define DBG_TLV_TPDM_CMB_XPRn___S 0 +#define DBG_TLV_TPDM_CMB_XPR0 (0x00BC2A18) +#define DBG_TLV_TPDM_CMB_XPR0___RWC QCSR_REG_RW +#define DBG_TLV_TPDM_CMB_XPR0__VAL___M 0xFFFFFFFF +#define DBG_TLV_TPDM_CMB_XPR0__VAL___S 0 + +#define DBG_TLV_TPDM_CMB_XPRm(m) (0x00BC2A18+0x4*(m)) +#define DBG_TLV_TPDM_CMB_XPRm_mMIN 1 +#define DBG_TLV_TPDM_CMB_XPRm_mMAX 1 +#define DBG_TLV_TPDM_CMB_XPRm_ELEM 1 +#define DBG_TLV_TPDM_CMB_XPRm___RWC QCSR_REG_RW +#define DBG_TLV_TPDM_CMB_XPRm___POR 0x00000000 +#define DBG_TLV_TPDM_CMB_XPRm__VAL___POR 0x00000000 +#define DBG_TLV_TPDM_CMB_XPRm__VAL___M 0xFFFFFFFF +#define DBG_TLV_TPDM_CMB_XPRm__VAL___S 0 +#define DBG_TLV_TPDM_CMB_XPRm___M 0xFFFFFFFF +#define DBG_TLV_TPDM_CMB_XPRm___S 0 +#define DBG_TLV_TPDM_CMB_XPR1 (0x00BC2A1C) +#define DBG_TLV_TPDM_CMB_XPR1___RWC QCSR_REG_RW +#define DBG_TLV_TPDM_CMB_XPR1__VAL___M 0xFFFFFFFF +#define DBG_TLV_TPDM_CMB_XPR1__VAL___S 0 + +#define DBG_TLV_TPDM_CMB_XPMRn(n) (0x00BC2A20+0x4*(n)) +#define DBG_TLV_TPDM_CMB_XPMRn_nMIN 0 +#define DBG_TLV_TPDM_CMB_XPMRn_nMAX 0 +#define DBG_TLV_TPDM_CMB_XPMRn_ELEM 1 +#define DBG_TLV_TPDM_CMB_XPMRn___RWC QCSR_REG_RW +#define DBG_TLV_TPDM_CMB_XPMRn___POR 0x00000000 +#define DBG_TLV_TPDM_CMB_XPMRn__VAL___POR 0x00000000 +#define DBG_TLV_TPDM_CMB_XPMRn__VAL___M 0xFFFFFFFF +#define DBG_TLV_TPDM_CMB_XPMRn__VAL___S 0 +#define DBG_TLV_TPDM_CMB_XPMRn___M 0xFFFFFFFF +#define DBG_TLV_TPDM_CMB_XPMRn___S 0 +#define DBG_TLV_TPDM_CMB_XPMR0 (0x00BC2A20) +#define DBG_TLV_TPDM_CMB_XPMR0___RWC QCSR_REG_RW +#define DBG_TLV_TPDM_CMB_XPMR0__VAL___M 0xFFFFFFFF +#define DBG_TLV_TPDM_CMB_XPMR0__VAL___S 0 + +#define DBG_TLV_TPDM_CMB_XPMRm(m) (0x00BC2A20+0x4*(m)) +#define DBG_TLV_TPDM_CMB_XPMRm_mMIN 1 +#define DBG_TLV_TPDM_CMB_XPMRm_mMAX 1 +#define DBG_TLV_TPDM_CMB_XPMRm_ELEM 1 +#define DBG_TLV_TPDM_CMB_XPMRm___RWC QCSR_REG_RW +#define DBG_TLV_TPDM_CMB_XPMRm___POR 0x00000000 +#define DBG_TLV_TPDM_CMB_XPMRm__VAL___POR 0x00000000 +#define DBG_TLV_TPDM_CMB_XPMRm__VAL___M 0xFFFFFFFF +#define DBG_TLV_TPDM_CMB_XPMRm__VAL___S 0 +#define DBG_TLV_TPDM_CMB_XPMRm___M 0xFFFFFFFF +#define DBG_TLV_TPDM_CMB_XPMRm___S 0 +#define DBG_TLV_TPDM_CMB_XPMR1 (0x00BC2A24) +#define DBG_TLV_TPDM_CMB_XPMR1___RWC QCSR_REG_RW +#define DBG_TLV_TPDM_CMB_XPMR1__VAL___M 0xFFFFFFFF +#define DBG_TLV_TPDM_CMB_XPMR1__VAL___S 0 + +#define DBG_TLV_TPDM_CMB_READCTL (0x00BC2A70) +#define DBG_TLV_TPDM_CMB_READCTL___RWC QCSR_REG_RW +#define DBG_TLV_TPDM_CMB_READCTL___POR 0x00000000 +#define DBG_TLV_TPDM_CMB_READCTL__SEL___POR 0x0 +#define DBG_TLV_TPDM_CMB_READCTL__SEL___M 0x00000001 +#define DBG_TLV_TPDM_CMB_READCTL__SEL___S 0 +#define DBG_TLV_TPDM_CMB_READCTL___M 0x00000001 +#define DBG_TLV_TPDM_CMB_READCTL___S 0 + +#define DBG_TLV_TPDM_CMB_READVAL (0x00BC2A74) +#define DBG_TLV_TPDM_CMB_READVAL___RWC QCSR_REG_RO +#define DBG_TLV_TPDM_CMB_READVAL___POR 0x00000000 +#define DBG_TLV_TPDM_CMB_READVAL__VALUE___POR 0x00000000 +#define DBG_TLV_TPDM_CMB_READVAL__VALUE___M 0xFFFFFFFF +#define DBG_TLV_TPDM_CMB_READVAL__VALUE___S 0 +#define DBG_TLV_TPDM_CMB_READVAL___M 0xFFFFFFFF +#define DBG_TLV_TPDM_CMB_READVAL___S 0 + +#define DBG_TLV_TPDM_ITATBCNTRL (0x00BC2EF0) +#define DBG_TLV_TPDM_ITATBCNTRL___RWC QCSR_REG_RW +#define DBG_TLV_TPDM_ITATBCNTRL___POR 0x00000000 +#define DBG_TLV_TPDM_ITATBCNTRL__TSREQ___POR 0x0 +#define DBG_TLV_TPDM_ITATBCNTRL__ATVALID___POR 0x0 +#define DBG_TLV_TPDM_ITATBCNTRL__ATDATAMODE___POR 0x0 +#define DBG_TLV_TPDM_ITATBCNTRL__ATBYTES___POR 0x0 +#define DBG_TLV_TPDM_ITATBCNTRL__ATDATA___POR 0x00 +#define DBG_TLV_TPDM_ITATBCNTRL__ATID___POR 0x00 +#define DBG_TLV_TPDM_ITATBCNTRL__TSVAL___POR 0x0 +#define DBG_TLV_TPDM_ITATBCNTRL__TSREQ___M 0x80000000 +#define DBG_TLV_TPDM_ITATBCNTRL__TSREQ___S 31 +#define DBG_TLV_TPDM_ITATBCNTRL__ATVALID___M 0x40000000 +#define DBG_TLV_TPDM_ITATBCNTRL__ATVALID___S 30 +#define DBG_TLV_TPDM_ITATBCNTRL__ATDATAMODE___M 0x00400000 +#define DBG_TLV_TPDM_ITATBCNTRL__ATDATAMODE___S 22 +#define DBG_TLV_TPDM_ITATBCNTRL__ATBYTES___M 0x003C0000 +#define DBG_TLV_TPDM_ITATBCNTRL__ATBYTES___S 18 +#define DBG_TLV_TPDM_ITATBCNTRL__ATDATA___M 0x0003FC00 +#define DBG_TLV_TPDM_ITATBCNTRL__ATDATA___S 10 +#define DBG_TLV_TPDM_ITATBCNTRL__ATID___M 0x000003F8 +#define DBG_TLV_TPDM_ITATBCNTRL__ATID___S 3 +#define DBG_TLV_TPDM_ITATBCNTRL__TSVAL___M 0x00000007 +#define DBG_TLV_TPDM_ITATBCNTRL__TSVAL___S 0 +#define DBG_TLV_TPDM_ITATBCNTRL___M 0xC07FFFFF +#define DBG_TLV_TPDM_ITATBCNTRL___S 0 + +#define DBG_TLV_TPDM_ITCNTRL (0x00BC2F00) +#define DBG_TLV_TPDM_ITCNTRL___RWC QCSR_REG_RW +#define DBG_TLV_TPDM_ITCNTRL___POR 0x00000000 +#define DBG_TLV_TPDM_ITCNTRL__IME___POR 0x0 +#define DBG_TLV_TPDM_ITCNTRL__IME___M 0x00000001 +#define DBG_TLV_TPDM_ITCNTRL__IME___S 0 +#define DBG_TLV_TPDM_ITCNTRL___M 0x00000001 +#define DBG_TLV_TPDM_ITCNTRL___S 0 + +#define DBG_TLV_TPDM_CLAIMSET (0x00BC2FA0) +#define DBG_TLV_TPDM_CLAIMSET___RWC QCSR_REG_RO +#define DBG_TLV_TPDM_CLAIMSET___POR 0x00000000 +#define DBG_TLV_TPDM_CLAIMSET__VAL_SET___POR 0x00000000 +#define DBG_TLV_TPDM_CLAIMSET__VAL_SET___M 0xFFFFFFFF +#define DBG_TLV_TPDM_CLAIMSET__VAL_SET___S 0 +#define DBG_TLV_TPDM_CLAIMSET___M 0xFFFFFFFF +#define DBG_TLV_TPDM_CLAIMSET___S 0 + +#define DBG_TLV_TPDM_CLAIMCLR (0x00BC2FA4) +#define DBG_TLV_TPDM_CLAIMCLR___RWC QCSR_REG_RO +#define DBG_TLV_TPDM_CLAIMCLR___POR 0x00000000 +#define DBG_TLV_TPDM_CLAIMCLR__VAL_CLR___POR 0x00000000 +#define DBG_TLV_TPDM_CLAIMCLR__VAL_CLR___M 0xFFFFFFFF +#define DBG_TLV_TPDM_CLAIMCLR__VAL_CLR___S 0 +#define DBG_TLV_TPDM_CLAIMCLR___M 0xFFFFFFFF +#define DBG_TLV_TPDM_CLAIMCLR___S 0 + +#define DBG_TLV_TPDM_DEVAFF0 (0x00BC2FA8) +#define DBG_TLV_TPDM_DEVAFF0___RWC QCSR_REG_RO +#define DBG_TLV_TPDM_DEVAFF0___POR 0x00000000 +#define DBG_TLV_TPDM_DEVAFF0__VAL___POR 0x00000000 +#define DBG_TLV_TPDM_DEVAFF0__VAL___M 0xFFFFFFFF +#define DBG_TLV_TPDM_DEVAFF0__VAL___S 0 +#define DBG_TLV_TPDM_DEVAFF0___M 0xFFFFFFFF +#define DBG_TLV_TPDM_DEVAFF0___S 0 + +#define DBG_TLV_TPDM_DEVAFF1 (0x00BC2FAC) +#define DBG_TLV_TPDM_DEVAFF1___RWC QCSR_REG_RO +#define DBG_TLV_TPDM_DEVAFF1___POR 0x00000000 +#define DBG_TLV_TPDM_DEVAFF1__VAL___POR 0x00000000 +#define DBG_TLV_TPDM_DEVAFF1__VAL___M 0xFFFFFFFF +#define DBG_TLV_TPDM_DEVAFF1__VAL___S 0 +#define DBG_TLV_TPDM_DEVAFF1___M 0xFFFFFFFF +#define DBG_TLV_TPDM_DEVAFF1___S 0 + +#define DBG_TLV_TPDM_LAR (0x00BC2FB0) +#define DBG_TLV_TPDM_LAR___RWC QCSR_REG_WO +#define DBG_TLV_TPDM_LAR___POR 0x00000000 +#define DBG_TLV_TPDM_LAR__KEY___POR 0x00000000 +#define DBG_TLV_TPDM_LAR__KEY___M 0xFFFFFFFF +#define DBG_TLV_TPDM_LAR__KEY___S 0 +#define DBG_TLV_TPDM_LAR___M 0xFFFFFFFF +#define DBG_TLV_TPDM_LAR___S 0 + +#define DBG_TLV_TPDM_LSR (0x00BC2FB4) +#define DBG_TLV_TPDM_LSR___RWC QCSR_REG_RO +#define DBG_TLV_TPDM_LSR___POR 0x00000003 +#define DBG_TLV_TPDM_LSR__NTT___POR 0x0 +#define DBG_TLV_TPDM_LSR__SLK___POR 0x1 +#define DBG_TLV_TPDM_LSR__SLI___POR 0x1 +#define DBG_TLV_TPDM_LSR__NTT___M 0x00000004 +#define DBG_TLV_TPDM_LSR__NTT___S 2 +#define DBG_TLV_TPDM_LSR__SLK___M 0x00000002 +#define DBG_TLV_TPDM_LSR__SLK___S 1 +#define DBG_TLV_TPDM_LSR__SLI___M 0x00000001 +#define DBG_TLV_TPDM_LSR__SLI___S 0 +#define DBG_TLV_TPDM_LSR___M 0x00000007 +#define DBG_TLV_TPDM_LSR___S 0 + +#define DBG_TLV_TPDM_AUTHSTATUS (0x00BC2FB8) +#define DBG_TLV_TPDM_AUTHSTATUS___RWC QCSR_REG_RO +#define DBG_TLV_TPDM_AUTHSTATUS___POR 0x000000AA +#define DBG_TLV_TPDM_AUTHSTATUS__SNID___POR 0x2 +#define DBG_TLV_TPDM_AUTHSTATUS__SID___POR 0x2 +#define DBG_TLV_TPDM_AUTHSTATUS__NSNID___POR 0x2 +#define DBG_TLV_TPDM_AUTHSTATUS__NSID___POR 0x2 +#define DBG_TLV_TPDM_AUTHSTATUS__SNID___M 0x000000C0 +#define DBG_TLV_TPDM_AUTHSTATUS__SNID___S 6 +#define DBG_TLV_TPDM_AUTHSTATUS__SID___M 0x00000030 +#define DBG_TLV_TPDM_AUTHSTATUS__SID___S 4 +#define DBG_TLV_TPDM_AUTHSTATUS__NSNID___M 0x0000000C +#define DBG_TLV_TPDM_AUTHSTATUS__NSNID___S 2 +#define DBG_TLV_TPDM_AUTHSTATUS__NSID___M 0x00000003 +#define DBG_TLV_TPDM_AUTHSTATUS__NSID___S 0 +#define DBG_TLV_TPDM_AUTHSTATUS___M 0x000000FF +#define DBG_TLV_TPDM_AUTHSTATUS___S 0 + +#define DBG_TLV_TPDM_DEVARCH (0x00BC2FBC) +#define DBG_TLV_TPDM_DEVARCH___RWC QCSR_REG_RO +#define DBG_TLV_TPDM_DEVARCH___POR 0x0E105CDA +#define DBG_TLV_TPDM_DEVARCH__ARCHITECT___POR 0x070 +#define DBG_TLV_TPDM_DEVARCH__PRESENT___POR 0x1 +#define DBG_TLV_TPDM_DEVARCH__REVISION___POR 0x0 +#define DBG_TLV_TPDM_DEVARCH__ARCHID___POR 0x5CDA +#define DBG_TLV_TPDM_DEVARCH__ARCHITECT___M 0xFFE00000 +#define DBG_TLV_TPDM_DEVARCH__ARCHITECT___S 21 +#define DBG_TLV_TPDM_DEVARCH__PRESENT___M 0x00100000 +#define DBG_TLV_TPDM_DEVARCH__PRESENT___S 20 +#define DBG_TLV_TPDM_DEVARCH__REVISION___M 0x000F0000 +#define DBG_TLV_TPDM_DEVARCH__REVISION___S 16 +#define DBG_TLV_TPDM_DEVARCH__ARCHID___M 0x0000FFFF +#define DBG_TLV_TPDM_DEVARCH__ARCHID___S 0 +#define DBG_TLV_TPDM_DEVARCH___M 0xFFFFFFFF +#define DBG_TLV_TPDM_DEVARCH___S 0 + +#define DBG_TLV_TPDM_DEVID1 (0x00BC2FC4) +#define DBG_TLV_TPDM_DEVID1___RWC QCSR_REG_RO +#define DBG_TLV_TPDM_DEVID1___POR 0x40000000 +#define DBG_TLV_TPDM_DEVID1__CMB_LIVE___POR 0x0 +#define DBG_TLV_TPDM_DEVID1__DSB_LIVE___POR 0x1 +#define DBG_TLV_TPDM_DEVID1__CMB_LIVE___M 0x80000000 +#define DBG_TLV_TPDM_DEVID1__CMB_LIVE___S 31 +#define DBG_TLV_TPDM_DEVID1__DSB_LIVE___M 0x40000000 +#define DBG_TLV_TPDM_DEVID1__DSB_LIVE___S 30 +#define DBG_TLV_TPDM_DEVID1___M 0xC0000000 +#define DBG_TLV_TPDM_DEVID1___S 30 + +#define DBG_TLV_TPDM_DEVID (0x00BC2FC8) +#define DBG_TLV_TPDM_DEVID___RWC QCSR_REG_RO +#define DBG_TLV_TPDM_DEVID___POR 0x15000008 +#define DBG_TLV_TPDM_DEVID__TC_LVL_TRIG___POR 0x2 +#define DBG_TLV_TPDM_DEVID__BC_LVL_TRIG___POR 0x2 +#define DBG_TLV_TPDM_DEVID__BC_GANG___POR 0x2 +#define DBG_TLV_TPDM_DEVID__CMB_IN___POR 0x2 +#define DBG_TLV_TPDM_DEVID__TC_LVL_TRIG___M 0x18000000 +#define DBG_TLV_TPDM_DEVID__TC_LVL_TRIG___S 27 +#define DBG_TLV_TPDM_DEVID__BC_LVL_TRIG___M 0x06000000 +#define DBG_TLV_TPDM_DEVID__BC_LVL_TRIG___S 25 +#define DBG_TLV_TPDM_DEVID__BC_GANG___M 0x01800000 +#define DBG_TLV_TPDM_DEVID__BC_GANG___S 23 +#define DBG_TLV_TPDM_DEVID__CMB_IN___M 0x0000000C +#define DBG_TLV_TPDM_DEVID__CMB_IN___S 2 +#define DBG_TLV_TPDM_DEVID___M 0x1F80000C +#define DBG_TLV_TPDM_DEVID___S 2 + +#define DBG_TLV_TPDM_DEVTYPE (0x00BC2FCC) +#define DBG_TLV_TPDM_DEVTYPE___RWC QCSR_REG_RO +#define DBG_TLV_TPDM_DEVTYPE___POR 0x00000003 +#define DBG_TLV_TPDM_DEVTYPE__SUB___POR 0x0 +#define DBG_TLV_TPDM_DEVTYPE__MAJOR___POR 0x3 +#define DBG_TLV_TPDM_DEVTYPE__SUB___M 0x000000F0 +#define DBG_TLV_TPDM_DEVTYPE__SUB___S 4 +#define DBG_TLV_TPDM_DEVTYPE__MAJOR___M 0x0000000F +#define DBG_TLV_TPDM_DEVTYPE__MAJOR___S 0 +#define DBG_TLV_TPDM_DEVTYPE___M 0x000000FF +#define DBG_TLV_TPDM_DEVTYPE___S 0 + +#define DBG_TLV_TPDM_PIDR4 (0x00BC2FD0) +#define DBG_TLV_TPDM_PIDR4___RWC QCSR_REG_RO +#define DBG_TLV_TPDM_PIDR4___POR 0x00000000 +#define DBG_TLV_TPDM_PIDR4__SIZE___POR 0x0 +#define DBG_TLV_TPDM_PIDR4__DES_2___POR 0x0 +#define DBG_TLV_TPDM_PIDR4__SIZE___M 0x000000F0 +#define DBG_TLV_TPDM_PIDR4__SIZE___S 4 +#define DBG_TLV_TPDM_PIDR4__DES_2___M 0x0000000F +#define DBG_TLV_TPDM_PIDR4__DES_2___S 0 +#define DBG_TLV_TPDM_PIDR4___M 0x000000FF +#define DBG_TLV_TPDM_PIDR4___S 0 + +#define DBG_TLV_TPDM_PIDR5 (0x00BC2FD4) +#define DBG_TLV_TPDM_PIDR5___RWC QCSR_REG_RO +#define DBG_TLV_TPDM_PIDR5___POR 0x00000000 +#define DBG_TLV_TPDM_PIDR5__EMPTY___POR 0x00000000 +#define DBG_TLV_TPDM_PIDR5__EMPTY___M 0xFFFFFFFF +#define DBG_TLV_TPDM_PIDR5__EMPTY___S 0 +#define DBG_TLV_TPDM_PIDR5___M 0xFFFFFFFF +#define DBG_TLV_TPDM_PIDR5___S 0 + +#define DBG_TLV_TPDM_PIDR6 (0x00BC2FD8) +#define DBG_TLV_TPDM_PIDR6___RWC QCSR_REG_RO +#define DBG_TLV_TPDM_PIDR6___POR 0x00000000 +#define DBG_TLV_TPDM_PIDR6__EMPTY___POR 0x00000000 +#define DBG_TLV_TPDM_PIDR6__EMPTY___M 0xFFFFFFFF +#define DBG_TLV_TPDM_PIDR6__EMPTY___S 0 +#define DBG_TLV_TPDM_PIDR6___M 0xFFFFFFFF +#define DBG_TLV_TPDM_PIDR6___S 0 + +#define DBG_TLV_TPDM_PIDR7 (0x00BC2FDC) +#define DBG_TLV_TPDM_PIDR7___RWC QCSR_REG_RO +#define DBG_TLV_TPDM_PIDR7___POR 0x00000000 +#define DBG_TLV_TPDM_PIDR7__EMPTY___POR 0x00000000 +#define DBG_TLV_TPDM_PIDR7__EMPTY___M 0xFFFFFFFF +#define DBG_TLV_TPDM_PIDR7__EMPTY___S 0 +#define DBG_TLV_TPDM_PIDR7___M 0xFFFFFFFF +#define DBG_TLV_TPDM_PIDR7___S 0 + +#define DBG_TLV_TPDM_PIDR0 (0x00BC2FE0) +#define DBG_TLV_TPDM_PIDR0___RWC QCSR_REG_RO +#define DBG_TLV_TPDM_PIDR0___POR 0x00000024 +#define DBG_TLV_TPDM_PIDR0__PART_7___POR 0x0 +#define DBG_TLV_TPDM_PIDR0__PART_6___POR 0x0 +#define DBG_TLV_TPDM_PIDR0__PART_5___POR 0x1 +#define DBG_TLV_TPDM_PIDR0__PART_4___POR 0x0 +#define DBG_TLV_TPDM_PIDR0__PART_3___POR 0x0 +#define DBG_TLV_TPDM_PIDR0__PART_2___POR 0x1 +#define DBG_TLV_TPDM_PIDR0__PART_1___POR 0x0 +#define DBG_TLV_TPDM_PIDR0__PART_0___POR 0x0 +#define DBG_TLV_TPDM_PIDR0__PART_7___M 0x00000080 +#define DBG_TLV_TPDM_PIDR0__PART_7___S 7 +#define DBG_TLV_TPDM_PIDR0__PART_6___M 0x00000040 +#define DBG_TLV_TPDM_PIDR0__PART_6___S 6 +#define DBG_TLV_TPDM_PIDR0__PART_5___M 0x00000020 +#define DBG_TLV_TPDM_PIDR0__PART_5___S 5 +#define DBG_TLV_TPDM_PIDR0__PART_4___M 0x00000010 +#define DBG_TLV_TPDM_PIDR0__PART_4___S 4 +#define DBG_TLV_TPDM_PIDR0__PART_3___M 0x00000008 +#define DBG_TLV_TPDM_PIDR0__PART_3___S 3 +#define DBG_TLV_TPDM_PIDR0__PART_2___M 0x00000004 +#define DBG_TLV_TPDM_PIDR0__PART_2___S 2 +#define DBG_TLV_TPDM_PIDR0__PART_1___M 0x00000002 +#define DBG_TLV_TPDM_PIDR0__PART_1___S 1 +#define DBG_TLV_TPDM_PIDR0__PART_0___M 0x00000001 +#define DBG_TLV_TPDM_PIDR0__PART_0___S 0 +#define DBG_TLV_TPDM_PIDR0___M 0x000000FF +#define DBG_TLV_TPDM_PIDR0___S 0 + +#define DBG_TLV_TPDM_PIDR1 (0x00BC2FE4) +#define DBG_TLV_TPDM_PIDR1___RWC QCSR_REG_RO +#define DBG_TLV_TPDM_PIDR1___POR 0x0000000E +#define DBG_TLV_TPDM_PIDR1__DES_0___POR 0x0 +#define DBG_TLV_TPDM_PIDR1__PART_1___POR 0xE +#define DBG_TLV_TPDM_PIDR1__DES_0___M 0x000000F0 +#define DBG_TLV_TPDM_PIDR1__DES_0___S 4 +#define DBG_TLV_TPDM_PIDR1__PART_1___M 0x0000000F +#define DBG_TLV_TPDM_PIDR1__PART_1___S 0 +#define DBG_TLV_TPDM_PIDR1___M 0x000000FF +#define DBG_TLV_TPDM_PIDR1___S 0 + +#define DBG_TLV_TPDM_PIDR2 (0x00BC2FE8) +#define DBG_TLV_TPDM_PIDR2___RWC QCSR_REG_RO +#define DBG_TLV_TPDM_PIDR2___POR 0x00000018 +#define DBG_TLV_TPDM_PIDR2__REVISION___POR 0x1 +#define DBG_TLV_TPDM_PIDR2__JEDEC___POR 0x1 +#define DBG_TLV_TPDM_PIDR2__DES_1___POR 0x0 +#define DBG_TLV_TPDM_PIDR2__REVISION___M 0x000000F0 +#define DBG_TLV_TPDM_PIDR2__REVISION___S 4 +#define DBG_TLV_TPDM_PIDR2__JEDEC___M 0x00000008 +#define DBG_TLV_TPDM_PIDR2__JEDEC___S 3 +#define DBG_TLV_TPDM_PIDR2__DES_1___M 0x00000007 +#define DBG_TLV_TPDM_PIDR2__DES_1___S 0 +#define DBG_TLV_TPDM_PIDR2___M 0x000000FF +#define DBG_TLV_TPDM_PIDR2___S 0 + +#define DBG_TLV_TPDM_PIDR3 (0x00BC2FEC) +#define DBG_TLV_TPDM_PIDR3___RWC QCSR_REG_RO +#define DBG_TLV_TPDM_PIDR3___POR 0x00000000 +#define DBG_TLV_TPDM_PIDR3__REVAND___POR 0x0 +#define DBG_TLV_TPDM_PIDR3__CMOD___POR 0x0 +#define DBG_TLV_TPDM_PIDR3__REVAND___M 0x000000F0 +#define DBG_TLV_TPDM_PIDR3__REVAND___S 4 +#define DBG_TLV_TPDM_PIDR3__CMOD___M 0x0000000F +#define DBG_TLV_TPDM_PIDR3__CMOD___S 0 +#define DBG_TLV_TPDM_PIDR3___M 0x000000FF +#define DBG_TLV_TPDM_PIDR3___S 0 + +#define DBG_TLV_TPDM_CIDR0 (0x00BC2FF0) +#define DBG_TLV_TPDM_CIDR0___RWC QCSR_REG_RO +#define DBG_TLV_TPDM_CIDR0___POR 0x0000000D +#define DBG_TLV_TPDM_CIDR0__PRMBL_0___POR 0x0D +#define DBG_TLV_TPDM_CIDR0__PRMBL_0___M 0x000000FF +#define DBG_TLV_TPDM_CIDR0__PRMBL_0___S 0 +#define DBG_TLV_TPDM_CIDR0___M 0x000000FF +#define DBG_TLV_TPDM_CIDR0___S 0 + +#define DBG_TLV_TPDM_CIDR1 (0x00BC2FF4) +#define DBG_TLV_TPDM_CIDR1___RWC QCSR_REG_RO +#define DBG_TLV_TPDM_CIDR1___POR 0x00000090 +#define DBG_TLV_TPDM_CIDR1__CLASS___POR 0x9 +#define DBG_TLV_TPDM_CIDR1__PRMBL_1___POR 0x0 +#define DBG_TLV_TPDM_CIDR1__CLASS___M 0x000000F0 +#define DBG_TLV_TPDM_CIDR1__CLASS___S 4 +#define DBG_TLV_TPDM_CIDR1__PRMBL_1___M 0x0000000F +#define DBG_TLV_TPDM_CIDR1__PRMBL_1___S 0 +#define DBG_TLV_TPDM_CIDR1___M 0x000000FF +#define DBG_TLV_TPDM_CIDR1___S 0 + +#define DBG_TLV_TPDM_CIDR2 (0x00BC2FF8) +#define DBG_TLV_TPDM_CIDR2___RWC QCSR_REG_RO +#define DBG_TLV_TPDM_CIDR2___POR 0x00000005 +#define DBG_TLV_TPDM_CIDR2__PRMBL_2___POR 0x05 +#define DBG_TLV_TPDM_CIDR2__PRMBL_2___M 0x000000FF +#define DBG_TLV_TPDM_CIDR2__PRMBL_2___S 0 +#define DBG_TLV_TPDM_CIDR2___M 0x000000FF +#define DBG_TLV_TPDM_CIDR2___S 0 + +#define DBG_TLV_TPDM_CIDR3 (0x00BC2FFC) +#define DBG_TLV_TPDM_CIDR3___RWC QCSR_REG_RO +#define DBG_TLV_TPDM_CIDR3___POR 0x000000B1 +#define DBG_TLV_TPDM_CIDR3__PRMBL_3___POR 0xB1 +#define DBG_TLV_TPDM_CIDR3__PRMBL_3___M 0x000000FF +#define DBG_TLV_TPDM_CIDR3__PRMBL_3___S 0 +#define DBG_TLV_TPDM_CIDR3___M 0x000000FF +#define DBG_TLV_TPDM_CIDR3___S 0 + +#define DBG_TLV_TPDM_GPRn(n) (0x00BC2000+0x4*(n)) +#define DBG_TLV_TPDM_GPRn_nMIN 0 +#define DBG_TLV_TPDM_GPRn_nMAX 2 +#define DBG_TLV_TPDM_GPRn_ELEM 3 +#define DBG_TLV_TPDM_GPRn___RWC QCSR_REG_RW +#define DBG_TLV_TPDM_GPRn___POR 0x00000000 +#define DBG_TLV_TPDM_GPRn__VAL___POR 0x00000000 +#define DBG_TLV_TPDM_GPRn__VAL___M 0xFFFFFFFF +#define DBG_TLV_TPDM_GPRn__VAL___S 0 +#define DBG_TLV_TPDM_GPRn___M 0xFFFFFFFF +#define DBG_TLV_TPDM_GPRn___S 0 +#define DBG_TLV_TPDM_GPR0 (0x00BC2000) +#define DBG_TLV_TPDM_GPR0___RWC QCSR_REG_RW +#define DBG_TLV_TPDM_GPR0__VAL___M 0xFFFFFFFF +#define DBG_TLV_TPDM_GPR0__VAL___S 0 +#define DBG_TLV_TPDM_GPR1 (0x00BC2004) +#define DBG_TLV_TPDM_GPR1___RWC QCSR_REG_RW +#define DBG_TLV_TPDM_GPR1__VAL___M 0xFFFFFFFF +#define DBG_TLV_TPDM_GPR1__VAL___S 0 +#define DBG_TLV_TPDM_GPR2 (0x00BC2008) +#define DBG_TLV_TPDM_GPR2___RWC QCSR_REG_RW +#define DBG_TLV_TPDM_GPR2__VAL___M 0xFFFFFFFF +#define DBG_TLV_TPDM_GPR2__VAL___S 0 + +#define DBG_MISC_TPDM_CMB_CR (0x00BC3A00) +#define DBG_MISC_TPDM_CMB_CR___RWC QCSR_REG_RW +#define DBG_MISC_TPDM_CMB_CR___POR 0x00000000 +#define DBG_MISC_TPDM_CMB_CR__ATBFLOWERR___POR 0x0 +#define DBG_MISC_TPDM_CMB_CR__EBITSET___POR 0x0 +#define DBG_MISC_TPDM_CMB_CR__FLOWCTRL___POR 0x0 +#define DBG_MISC_TPDM_CMB_CR__MODE___POR 0x0 +#define DBG_MISC_TPDM_CMB_CR__E___POR 0x0 +#define DBG_MISC_TPDM_CMB_CR__ATBFLOWERR___M 0x00000080 +#define DBG_MISC_TPDM_CMB_CR__ATBFLOWERR___S 7 +#define DBG_MISC_TPDM_CMB_CR__EBITSET___M 0x00000040 +#define DBG_MISC_TPDM_CMB_CR__EBITSET___S 6 +#define DBG_MISC_TPDM_CMB_CR__FLOWCTRL___M 0x00000004 +#define DBG_MISC_TPDM_CMB_CR__FLOWCTRL___S 2 +#define DBG_MISC_TPDM_CMB_CR__MODE___M 0x00000002 +#define DBG_MISC_TPDM_CMB_CR__MODE___S 1 +#define DBG_MISC_TPDM_CMB_CR__E___M 0x00000001 +#define DBG_MISC_TPDM_CMB_CR__E___S 0 +#define DBG_MISC_TPDM_CMB_CR___M 0x000000C7 +#define DBG_MISC_TPDM_CMB_CR___S 0 + +#define DBG_MISC_TPDM_CMB_TIER (0x00BC3A04) +#define DBG_MISC_TPDM_CMB_TIER___RWC QCSR_REG_RW +#define DBG_MISC_TPDM_CMB_TIER___POR 0x00000000 +#define DBG_MISC_TPDM_CMB_TIER__TS_ALL___POR 0x0 +#define DBG_MISC_TPDM_CMB_TIER__XTRIG_TSENAB___POR 0x0 +#define DBG_MISC_TPDM_CMB_TIER__PATT_TSENAB___POR 0x0 +#define DBG_MISC_TPDM_CMB_TIER__TS_ALL___M 0x00000004 +#define DBG_MISC_TPDM_CMB_TIER__TS_ALL___S 2 +#define DBG_MISC_TPDM_CMB_TIER__XTRIG_TSENAB___M 0x00000002 +#define DBG_MISC_TPDM_CMB_TIER__XTRIG_TSENAB___S 1 +#define DBG_MISC_TPDM_CMB_TIER__PATT_TSENAB___M 0x00000001 +#define DBG_MISC_TPDM_CMB_TIER__PATT_TSENAB___S 0 +#define DBG_MISC_TPDM_CMB_TIER___M 0x00000007 +#define DBG_MISC_TPDM_CMB_TIER___S 0 + +#define DBG_MISC_TPDM_CMB_TPRn(n) (0x00BC3A08+0x4*(n)) +#define DBG_MISC_TPDM_CMB_TPRn_nMIN 0 +#define DBG_MISC_TPDM_CMB_TPRn_nMAX 0 +#define DBG_MISC_TPDM_CMB_TPRn_ELEM 1 +#define DBG_MISC_TPDM_CMB_TPRn___RWC QCSR_REG_RW +#define DBG_MISC_TPDM_CMB_TPRn___POR 0x00000000 +#define DBG_MISC_TPDM_CMB_TPRn__VAL___POR 0x00000000 +#define DBG_MISC_TPDM_CMB_TPRn__VAL___M 0xFFFFFFFF +#define DBG_MISC_TPDM_CMB_TPRn__VAL___S 0 +#define DBG_MISC_TPDM_CMB_TPRn___M 0xFFFFFFFF +#define DBG_MISC_TPDM_CMB_TPRn___S 0 +#define DBG_MISC_TPDM_CMB_TPR0 (0x00BC3A08) +#define DBG_MISC_TPDM_CMB_TPR0___RWC QCSR_REG_RW +#define DBG_MISC_TPDM_CMB_TPR0__VAL___M 0xFFFFFFFF +#define DBG_MISC_TPDM_CMB_TPR0__VAL___S 0 + +#define DBG_MISC_TPDM_CMB_TPRm(m) (0x00BC3A08+0x4*(m)) +#define DBG_MISC_TPDM_CMB_TPRm_mMIN 1 +#define DBG_MISC_TPDM_CMB_TPRm_mMAX 1 +#define DBG_MISC_TPDM_CMB_TPRm_ELEM 1 +#define DBG_MISC_TPDM_CMB_TPRm___RWC QCSR_REG_RW +#define DBG_MISC_TPDM_CMB_TPRm___POR 0x00000000 +#define DBG_MISC_TPDM_CMB_TPRm__VAL___POR 0x00000000 +#define DBG_MISC_TPDM_CMB_TPRm__VAL___M 0xFFFFFFFF +#define DBG_MISC_TPDM_CMB_TPRm__VAL___S 0 +#define DBG_MISC_TPDM_CMB_TPRm___M 0xFFFFFFFF +#define DBG_MISC_TPDM_CMB_TPRm___S 0 +#define DBG_MISC_TPDM_CMB_TPR1 (0x00BC3A0C) +#define DBG_MISC_TPDM_CMB_TPR1___RWC QCSR_REG_RW +#define DBG_MISC_TPDM_CMB_TPR1__VAL___M 0xFFFFFFFF +#define DBG_MISC_TPDM_CMB_TPR1__VAL___S 0 + +#define DBG_MISC_TPDM_CMB_TPMRn(n) (0x00BC3A10+0x4*(n)) +#define DBG_MISC_TPDM_CMB_TPMRn_nMIN 0 +#define DBG_MISC_TPDM_CMB_TPMRn_nMAX 0 +#define DBG_MISC_TPDM_CMB_TPMRn_ELEM 1 +#define DBG_MISC_TPDM_CMB_TPMRn___RWC QCSR_REG_RW +#define DBG_MISC_TPDM_CMB_TPMRn___POR 0x00000000 +#define DBG_MISC_TPDM_CMB_TPMRn__VAL___POR 0x00000000 +#define DBG_MISC_TPDM_CMB_TPMRn__VAL___M 0xFFFFFFFF +#define DBG_MISC_TPDM_CMB_TPMRn__VAL___S 0 +#define DBG_MISC_TPDM_CMB_TPMRn___M 0xFFFFFFFF +#define DBG_MISC_TPDM_CMB_TPMRn___S 0 +#define DBG_MISC_TPDM_CMB_TPMR0 (0x00BC3A10) +#define DBG_MISC_TPDM_CMB_TPMR0___RWC QCSR_REG_RW +#define DBG_MISC_TPDM_CMB_TPMR0__VAL___M 0xFFFFFFFF +#define DBG_MISC_TPDM_CMB_TPMR0__VAL___S 0 + +#define DBG_MISC_TPDM_CMB_TPMRm(m) (0x00BC3A10+0x4*(m)) +#define DBG_MISC_TPDM_CMB_TPMRm_mMIN 1 +#define DBG_MISC_TPDM_CMB_TPMRm_mMAX 1 +#define DBG_MISC_TPDM_CMB_TPMRm_ELEM 1 +#define DBG_MISC_TPDM_CMB_TPMRm___RWC QCSR_REG_RW +#define DBG_MISC_TPDM_CMB_TPMRm___POR 0x00000000 +#define DBG_MISC_TPDM_CMB_TPMRm__VAL___POR 0x00000000 +#define DBG_MISC_TPDM_CMB_TPMRm__VAL___M 0xFFFFFFFF +#define DBG_MISC_TPDM_CMB_TPMRm__VAL___S 0 +#define DBG_MISC_TPDM_CMB_TPMRm___M 0xFFFFFFFF +#define DBG_MISC_TPDM_CMB_TPMRm___S 0 +#define DBG_MISC_TPDM_CMB_TPMR1 (0x00BC3A14) +#define DBG_MISC_TPDM_CMB_TPMR1___RWC QCSR_REG_RW +#define DBG_MISC_TPDM_CMB_TPMR1__VAL___M 0xFFFFFFFF +#define DBG_MISC_TPDM_CMB_TPMR1__VAL___S 0 + +#define DBG_MISC_TPDM_CMB_XPRn(n) (0x00BC3A18+0x4*(n)) +#define DBG_MISC_TPDM_CMB_XPRn_nMIN 0 +#define DBG_MISC_TPDM_CMB_XPRn_nMAX 0 +#define DBG_MISC_TPDM_CMB_XPRn_ELEM 1 +#define DBG_MISC_TPDM_CMB_XPRn___RWC QCSR_REG_RW +#define DBG_MISC_TPDM_CMB_XPRn___POR 0x00000000 +#define DBG_MISC_TPDM_CMB_XPRn__VAL___POR 0x00000000 +#define DBG_MISC_TPDM_CMB_XPRn__VAL___M 0xFFFFFFFF +#define DBG_MISC_TPDM_CMB_XPRn__VAL___S 0 +#define DBG_MISC_TPDM_CMB_XPRn___M 0xFFFFFFFF +#define DBG_MISC_TPDM_CMB_XPRn___S 0 +#define DBG_MISC_TPDM_CMB_XPR0 (0x00BC3A18) +#define DBG_MISC_TPDM_CMB_XPR0___RWC QCSR_REG_RW +#define DBG_MISC_TPDM_CMB_XPR0__VAL___M 0xFFFFFFFF +#define DBG_MISC_TPDM_CMB_XPR0__VAL___S 0 + +#define DBG_MISC_TPDM_CMB_XPRm(m) (0x00BC3A18+0x4*(m)) +#define DBG_MISC_TPDM_CMB_XPRm_mMIN 1 +#define DBG_MISC_TPDM_CMB_XPRm_mMAX 1 +#define DBG_MISC_TPDM_CMB_XPRm_ELEM 1 +#define DBG_MISC_TPDM_CMB_XPRm___RWC QCSR_REG_RW +#define DBG_MISC_TPDM_CMB_XPRm___POR 0x00000000 +#define DBG_MISC_TPDM_CMB_XPRm__VAL___POR 0x00000000 +#define DBG_MISC_TPDM_CMB_XPRm__VAL___M 0xFFFFFFFF +#define DBG_MISC_TPDM_CMB_XPRm__VAL___S 0 +#define DBG_MISC_TPDM_CMB_XPRm___M 0xFFFFFFFF +#define DBG_MISC_TPDM_CMB_XPRm___S 0 +#define DBG_MISC_TPDM_CMB_XPR1 (0x00BC3A1C) +#define DBG_MISC_TPDM_CMB_XPR1___RWC QCSR_REG_RW +#define DBG_MISC_TPDM_CMB_XPR1__VAL___M 0xFFFFFFFF +#define DBG_MISC_TPDM_CMB_XPR1__VAL___S 0 + +#define DBG_MISC_TPDM_CMB_XPMRn(n) (0x00BC3A20+0x4*(n)) +#define DBG_MISC_TPDM_CMB_XPMRn_nMIN 0 +#define DBG_MISC_TPDM_CMB_XPMRn_nMAX 0 +#define DBG_MISC_TPDM_CMB_XPMRn_ELEM 1 +#define DBG_MISC_TPDM_CMB_XPMRn___RWC QCSR_REG_RW +#define DBG_MISC_TPDM_CMB_XPMRn___POR 0x00000000 +#define DBG_MISC_TPDM_CMB_XPMRn__VAL___POR 0x00000000 +#define DBG_MISC_TPDM_CMB_XPMRn__VAL___M 0xFFFFFFFF +#define DBG_MISC_TPDM_CMB_XPMRn__VAL___S 0 +#define DBG_MISC_TPDM_CMB_XPMRn___M 0xFFFFFFFF +#define DBG_MISC_TPDM_CMB_XPMRn___S 0 +#define DBG_MISC_TPDM_CMB_XPMR0 (0x00BC3A20) +#define DBG_MISC_TPDM_CMB_XPMR0___RWC QCSR_REG_RW +#define DBG_MISC_TPDM_CMB_XPMR0__VAL___M 0xFFFFFFFF +#define DBG_MISC_TPDM_CMB_XPMR0__VAL___S 0 + +#define DBG_MISC_TPDM_CMB_XPMRm(m) (0x00BC3A20+0x4*(m)) +#define DBG_MISC_TPDM_CMB_XPMRm_mMIN 1 +#define DBG_MISC_TPDM_CMB_XPMRm_mMAX 1 +#define DBG_MISC_TPDM_CMB_XPMRm_ELEM 1 +#define DBG_MISC_TPDM_CMB_XPMRm___RWC QCSR_REG_RW +#define DBG_MISC_TPDM_CMB_XPMRm___POR 0x00000000 +#define DBG_MISC_TPDM_CMB_XPMRm__VAL___POR 0x00000000 +#define DBG_MISC_TPDM_CMB_XPMRm__VAL___M 0xFFFFFFFF +#define DBG_MISC_TPDM_CMB_XPMRm__VAL___S 0 +#define DBG_MISC_TPDM_CMB_XPMRm___M 0xFFFFFFFF +#define DBG_MISC_TPDM_CMB_XPMRm___S 0 +#define DBG_MISC_TPDM_CMB_XPMR1 (0x00BC3A24) +#define DBG_MISC_TPDM_CMB_XPMR1___RWC QCSR_REG_RW +#define DBG_MISC_TPDM_CMB_XPMR1__VAL___M 0xFFFFFFFF +#define DBG_MISC_TPDM_CMB_XPMR1__VAL___S 0 + +#define DBG_MISC_TPDM_CMB_READCTL (0x00BC3A70) +#define DBG_MISC_TPDM_CMB_READCTL___RWC QCSR_REG_RW +#define DBG_MISC_TPDM_CMB_READCTL___POR 0x00000000 +#define DBG_MISC_TPDM_CMB_READCTL__SEL___POR 0x0 +#define DBG_MISC_TPDM_CMB_READCTL__SEL___M 0x00000001 +#define DBG_MISC_TPDM_CMB_READCTL__SEL___S 0 +#define DBG_MISC_TPDM_CMB_READCTL___M 0x00000001 +#define DBG_MISC_TPDM_CMB_READCTL___S 0 + +#define DBG_MISC_TPDM_CMB_READVAL (0x00BC3A74) +#define DBG_MISC_TPDM_CMB_READVAL___RWC QCSR_REG_RO +#define DBG_MISC_TPDM_CMB_READVAL___POR 0x00000000 +#define DBG_MISC_TPDM_CMB_READVAL__VALUE___POR 0x00000000 +#define DBG_MISC_TPDM_CMB_READVAL__VALUE___M 0xFFFFFFFF +#define DBG_MISC_TPDM_CMB_READVAL__VALUE___S 0 +#define DBG_MISC_TPDM_CMB_READVAL___M 0xFFFFFFFF +#define DBG_MISC_TPDM_CMB_READVAL___S 0 + +#define DBG_MISC_TPDM_ITATBCNTRL (0x00BC3EF0) +#define DBG_MISC_TPDM_ITATBCNTRL___RWC QCSR_REG_RW +#define DBG_MISC_TPDM_ITATBCNTRL___POR 0x00000000 +#define DBG_MISC_TPDM_ITATBCNTRL__TSREQ___POR 0x0 +#define DBG_MISC_TPDM_ITATBCNTRL__ATVALID___POR 0x0 +#define DBG_MISC_TPDM_ITATBCNTRL__ATDATAMODE___POR 0x0 +#define DBG_MISC_TPDM_ITATBCNTRL__ATBYTES___POR 0x0 +#define DBG_MISC_TPDM_ITATBCNTRL__ATDATA___POR 0x00 +#define DBG_MISC_TPDM_ITATBCNTRL__ATID___POR 0x00 +#define DBG_MISC_TPDM_ITATBCNTRL__TSVAL___POR 0x0 +#define DBG_MISC_TPDM_ITATBCNTRL__TSREQ___M 0x80000000 +#define DBG_MISC_TPDM_ITATBCNTRL__TSREQ___S 31 +#define DBG_MISC_TPDM_ITATBCNTRL__ATVALID___M 0x40000000 +#define DBG_MISC_TPDM_ITATBCNTRL__ATVALID___S 30 +#define DBG_MISC_TPDM_ITATBCNTRL__ATDATAMODE___M 0x00400000 +#define DBG_MISC_TPDM_ITATBCNTRL__ATDATAMODE___S 22 +#define DBG_MISC_TPDM_ITATBCNTRL__ATBYTES___M 0x003C0000 +#define DBG_MISC_TPDM_ITATBCNTRL__ATBYTES___S 18 +#define DBG_MISC_TPDM_ITATBCNTRL__ATDATA___M 0x0003FC00 +#define DBG_MISC_TPDM_ITATBCNTRL__ATDATA___S 10 +#define DBG_MISC_TPDM_ITATBCNTRL__ATID___M 0x000003F8 +#define DBG_MISC_TPDM_ITATBCNTRL__ATID___S 3 +#define DBG_MISC_TPDM_ITATBCNTRL__TSVAL___M 0x00000007 +#define DBG_MISC_TPDM_ITATBCNTRL__TSVAL___S 0 +#define DBG_MISC_TPDM_ITATBCNTRL___M 0xC07FFFFF +#define DBG_MISC_TPDM_ITATBCNTRL___S 0 + +#define DBG_MISC_TPDM_ITCNTRL (0x00BC3F00) +#define DBG_MISC_TPDM_ITCNTRL___RWC QCSR_REG_RW +#define DBG_MISC_TPDM_ITCNTRL___POR 0x00000000 +#define DBG_MISC_TPDM_ITCNTRL__IME___POR 0x0 +#define DBG_MISC_TPDM_ITCNTRL__IME___M 0x00000001 +#define DBG_MISC_TPDM_ITCNTRL__IME___S 0 +#define DBG_MISC_TPDM_ITCNTRL___M 0x00000001 +#define DBG_MISC_TPDM_ITCNTRL___S 0 + +#define DBG_MISC_TPDM_CLAIMSET (0x00BC3FA0) +#define DBG_MISC_TPDM_CLAIMSET___RWC QCSR_REG_RO +#define DBG_MISC_TPDM_CLAIMSET___POR 0x00000000 +#define DBG_MISC_TPDM_CLAIMSET__VAL_SET___POR 0x00000000 +#define DBG_MISC_TPDM_CLAIMSET__VAL_SET___M 0xFFFFFFFF +#define DBG_MISC_TPDM_CLAIMSET__VAL_SET___S 0 +#define DBG_MISC_TPDM_CLAIMSET___M 0xFFFFFFFF +#define DBG_MISC_TPDM_CLAIMSET___S 0 + +#define DBG_MISC_TPDM_CLAIMCLR (0x00BC3FA4) +#define DBG_MISC_TPDM_CLAIMCLR___RWC QCSR_REG_RO +#define DBG_MISC_TPDM_CLAIMCLR___POR 0x00000000 +#define DBG_MISC_TPDM_CLAIMCLR__VAL_CLR___POR 0x00000000 +#define DBG_MISC_TPDM_CLAIMCLR__VAL_CLR___M 0xFFFFFFFF +#define DBG_MISC_TPDM_CLAIMCLR__VAL_CLR___S 0 +#define DBG_MISC_TPDM_CLAIMCLR___M 0xFFFFFFFF +#define DBG_MISC_TPDM_CLAIMCLR___S 0 + +#define DBG_MISC_TPDM_DEVAFF0 (0x00BC3FA8) +#define DBG_MISC_TPDM_DEVAFF0___RWC QCSR_REG_RO +#define DBG_MISC_TPDM_DEVAFF0___POR 0x00000000 +#define DBG_MISC_TPDM_DEVAFF0__VAL___POR 0x00000000 +#define DBG_MISC_TPDM_DEVAFF0__VAL___M 0xFFFFFFFF +#define DBG_MISC_TPDM_DEVAFF0__VAL___S 0 +#define DBG_MISC_TPDM_DEVAFF0___M 0xFFFFFFFF +#define DBG_MISC_TPDM_DEVAFF0___S 0 + +#define DBG_MISC_TPDM_DEVAFF1 (0x00BC3FAC) +#define DBG_MISC_TPDM_DEVAFF1___RWC QCSR_REG_RO +#define DBG_MISC_TPDM_DEVAFF1___POR 0x00000000 +#define DBG_MISC_TPDM_DEVAFF1__VAL___POR 0x00000000 +#define DBG_MISC_TPDM_DEVAFF1__VAL___M 0xFFFFFFFF +#define DBG_MISC_TPDM_DEVAFF1__VAL___S 0 +#define DBG_MISC_TPDM_DEVAFF1___M 0xFFFFFFFF +#define DBG_MISC_TPDM_DEVAFF1___S 0 + +#define DBG_MISC_TPDM_LAR (0x00BC3FB0) +#define DBG_MISC_TPDM_LAR___RWC QCSR_REG_WO +#define DBG_MISC_TPDM_LAR___POR 0x00000000 +#define DBG_MISC_TPDM_LAR__KEY___POR 0x00000000 +#define DBG_MISC_TPDM_LAR__KEY___M 0xFFFFFFFF +#define DBG_MISC_TPDM_LAR__KEY___S 0 +#define DBG_MISC_TPDM_LAR___M 0xFFFFFFFF +#define DBG_MISC_TPDM_LAR___S 0 + +#define DBG_MISC_TPDM_LSR (0x00BC3FB4) +#define DBG_MISC_TPDM_LSR___RWC QCSR_REG_RO +#define DBG_MISC_TPDM_LSR___POR 0x00000003 +#define DBG_MISC_TPDM_LSR__NTT___POR 0x0 +#define DBG_MISC_TPDM_LSR__SLK___POR 0x1 +#define DBG_MISC_TPDM_LSR__SLI___POR 0x1 +#define DBG_MISC_TPDM_LSR__NTT___M 0x00000004 +#define DBG_MISC_TPDM_LSR__NTT___S 2 +#define DBG_MISC_TPDM_LSR__SLK___M 0x00000002 +#define DBG_MISC_TPDM_LSR__SLK___S 1 +#define DBG_MISC_TPDM_LSR__SLI___M 0x00000001 +#define DBG_MISC_TPDM_LSR__SLI___S 0 +#define DBG_MISC_TPDM_LSR___M 0x00000007 +#define DBG_MISC_TPDM_LSR___S 0 + +#define DBG_MISC_TPDM_AUTHSTATUS (0x00BC3FB8) +#define DBG_MISC_TPDM_AUTHSTATUS___RWC QCSR_REG_RO +#define DBG_MISC_TPDM_AUTHSTATUS___POR 0x000000AA +#define DBG_MISC_TPDM_AUTHSTATUS__SNID___POR 0x2 +#define DBG_MISC_TPDM_AUTHSTATUS__SID___POR 0x2 +#define DBG_MISC_TPDM_AUTHSTATUS__NSNID___POR 0x2 +#define DBG_MISC_TPDM_AUTHSTATUS__NSID___POR 0x2 +#define DBG_MISC_TPDM_AUTHSTATUS__SNID___M 0x000000C0 +#define DBG_MISC_TPDM_AUTHSTATUS__SNID___S 6 +#define DBG_MISC_TPDM_AUTHSTATUS__SID___M 0x00000030 +#define DBG_MISC_TPDM_AUTHSTATUS__SID___S 4 +#define DBG_MISC_TPDM_AUTHSTATUS__NSNID___M 0x0000000C +#define DBG_MISC_TPDM_AUTHSTATUS__NSNID___S 2 +#define DBG_MISC_TPDM_AUTHSTATUS__NSID___M 0x00000003 +#define DBG_MISC_TPDM_AUTHSTATUS__NSID___S 0 +#define DBG_MISC_TPDM_AUTHSTATUS___M 0x000000FF +#define DBG_MISC_TPDM_AUTHSTATUS___S 0 + +#define DBG_MISC_TPDM_DEVARCH (0x00BC3FBC) +#define DBG_MISC_TPDM_DEVARCH___RWC QCSR_REG_RO +#define DBG_MISC_TPDM_DEVARCH___POR 0x0E105CDA +#define DBG_MISC_TPDM_DEVARCH__ARCHITECT___POR 0x070 +#define DBG_MISC_TPDM_DEVARCH__PRESENT___POR 0x1 +#define DBG_MISC_TPDM_DEVARCH__REVISION___POR 0x0 +#define DBG_MISC_TPDM_DEVARCH__ARCHID___POR 0x5CDA +#define DBG_MISC_TPDM_DEVARCH__ARCHITECT___M 0xFFE00000 +#define DBG_MISC_TPDM_DEVARCH__ARCHITECT___S 21 +#define DBG_MISC_TPDM_DEVARCH__PRESENT___M 0x00100000 +#define DBG_MISC_TPDM_DEVARCH__PRESENT___S 20 +#define DBG_MISC_TPDM_DEVARCH__REVISION___M 0x000F0000 +#define DBG_MISC_TPDM_DEVARCH__REVISION___S 16 +#define DBG_MISC_TPDM_DEVARCH__ARCHID___M 0x0000FFFF +#define DBG_MISC_TPDM_DEVARCH__ARCHID___S 0 +#define DBG_MISC_TPDM_DEVARCH___M 0xFFFFFFFF +#define DBG_MISC_TPDM_DEVARCH___S 0 + +#define DBG_MISC_TPDM_DEVID1 (0x00BC3FC4) +#define DBG_MISC_TPDM_DEVID1___RWC QCSR_REG_RO +#define DBG_MISC_TPDM_DEVID1___POR 0x40000000 +#define DBG_MISC_TPDM_DEVID1__CMB_LIVE___POR 0x0 +#define DBG_MISC_TPDM_DEVID1__DSB_LIVE___POR 0x1 +#define DBG_MISC_TPDM_DEVID1__CMB_LIVE___M 0x80000000 +#define DBG_MISC_TPDM_DEVID1__CMB_LIVE___S 31 +#define DBG_MISC_TPDM_DEVID1__DSB_LIVE___M 0x40000000 +#define DBG_MISC_TPDM_DEVID1__DSB_LIVE___S 30 +#define DBG_MISC_TPDM_DEVID1___M 0xC0000000 +#define DBG_MISC_TPDM_DEVID1___S 30 + +#define DBG_MISC_TPDM_DEVID (0x00BC3FC8) +#define DBG_MISC_TPDM_DEVID___RWC QCSR_REG_RO +#define DBG_MISC_TPDM_DEVID___POR 0x15000008 +#define DBG_MISC_TPDM_DEVID__TC_LVL_TRIG___POR 0x2 +#define DBG_MISC_TPDM_DEVID__BC_LVL_TRIG___POR 0x2 +#define DBG_MISC_TPDM_DEVID__BC_GANG___POR 0x2 +#define DBG_MISC_TPDM_DEVID__CMB_IN___POR 0x2 +#define DBG_MISC_TPDM_DEVID__TC_LVL_TRIG___M 0x18000000 +#define DBG_MISC_TPDM_DEVID__TC_LVL_TRIG___S 27 +#define DBG_MISC_TPDM_DEVID__BC_LVL_TRIG___M 0x06000000 +#define DBG_MISC_TPDM_DEVID__BC_LVL_TRIG___S 25 +#define DBG_MISC_TPDM_DEVID__BC_GANG___M 0x01800000 +#define DBG_MISC_TPDM_DEVID__BC_GANG___S 23 +#define DBG_MISC_TPDM_DEVID__CMB_IN___M 0x0000000C +#define DBG_MISC_TPDM_DEVID__CMB_IN___S 2 +#define DBG_MISC_TPDM_DEVID___M 0x1F80000C +#define DBG_MISC_TPDM_DEVID___S 2 + +#define DBG_MISC_TPDM_DEVTYPE (0x00BC3FCC) +#define DBG_MISC_TPDM_DEVTYPE___RWC QCSR_REG_RO +#define DBG_MISC_TPDM_DEVTYPE___POR 0x00000003 +#define DBG_MISC_TPDM_DEVTYPE__SUB___POR 0x0 +#define DBG_MISC_TPDM_DEVTYPE__MAJOR___POR 0x3 +#define DBG_MISC_TPDM_DEVTYPE__SUB___M 0x000000F0 +#define DBG_MISC_TPDM_DEVTYPE__SUB___S 4 +#define DBG_MISC_TPDM_DEVTYPE__MAJOR___M 0x0000000F +#define DBG_MISC_TPDM_DEVTYPE__MAJOR___S 0 +#define DBG_MISC_TPDM_DEVTYPE___M 0x000000FF +#define DBG_MISC_TPDM_DEVTYPE___S 0 + +#define DBG_MISC_TPDM_PIDR4 (0x00BC3FD0) +#define DBG_MISC_TPDM_PIDR4___RWC QCSR_REG_RO +#define DBG_MISC_TPDM_PIDR4___POR 0x00000000 +#define DBG_MISC_TPDM_PIDR4__SIZE___POR 0x0 +#define DBG_MISC_TPDM_PIDR4__DES_2___POR 0x0 +#define DBG_MISC_TPDM_PIDR4__SIZE___M 0x000000F0 +#define DBG_MISC_TPDM_PIDR4__SIZE___S 4 +#define DBG_MISC_TPDM_PIDR4__DES_2___M 0x0000000F +#define DBG_MISC_TPDM_PIDR4__DES_2___S 0 +#define DBG_MISC_TPDM_PIDR4___M 0x000000FF +#define DBG_MISC_TPDM_PIDR4___S 0 + +#define DBG_MISC_TPDM_PIDR5 (0x00BC3FD4) +#define DBG_MISC_TPDM_PIDR5___RWC QCSR_REG_RO +#define DBG_MISC_TPDM_PIDR5___POR 0x00000000 +#define DBG_MISC_TPDM_PIDR5__EMPTY___POR 0x00000000 +#define DBG_MISC_TPDM_PIDR5__EMPTY___M 0xFFFFFFFF +#define DBG_MISC_TPDM_PIDR5__EMPTY___S 0 +#define DBG_MISC_TPDM_PIDR5___M 0xFFFFFFFF +#define DBG_MISC_TPDM_PIDR5___S 0 + +#define DBG_MISC_TPDM_PIDR6 (0x00BC3FD8) +#define DBG_MISC_TPDM_PIDR6___RWC QCSR_REG_RO +#define DBG_MISC_TPDM_PIDR6___POR 0x00000000 +#define DBG_MISC_TPDM_PIDR6__EMPTY___POR 0x00000000 +#define DBG_MISC_TPDM_PIDR6__EMPTY___M 0xFFFFFFFF +#define DBG_MISC_TPDM_PIDR6__EMPTY___S 0 +#define DBG_MISC_TPDM_PIDR6___M 0xFFFFFFFF +#define DBG_MISC_TPDM_PIDR6___S 0 + +#define DBG_MISC_TPDM_PIDR7 (0x00BC3FDC) +#define DBG_MISC_TPDM_PIDR7___RWC QCSR_REG_RO +#define DBG_MISC_TPDM_PIDR7___POR 0x00000000 +#define DBG_MISC_TPDM_PIDR7__EMPTY___POR 0x00000000 +#define DBG_MISC_TPDM_PIDR7__EMPTY___M 0xFFFFFFFF +#define DBG_MISC_TPDM_PIDR7__EMPTY___S 0 +#define DBG_MISC_TPDM_PIDR7___M 0xFFFFFFFF +#define DBG_MISC_TPDM_PIDR7___S 0 + +#define DBG_MISC_TPDM_PIDR0 (0x00BC3FE0) +#define DBG_MISC_TPDM_PIDR0___RWC QCSR_REG_RO +#define DBG_MISC_TPDM_PIDR0___POR 0x00000024 +#define DBG_MISC_TPDM_PIDR0__PART_7___POR 0x0 +#define DBG_MISC_TPDM_PIDR0__PART_6___POR 0x0 +#define DBG_MISC_TPDM_PIDR0__PART_5___POR 0x1 +#define DBG_MISC_TPDM_PIDR0__PART_4___POR 0x0 +#define DBG_MISC_TPDM_PIDR0__PART_3___POR 0x0 +#define DBG_MISC_TPDM_PIDR0__PART_2___POR 0x1 +#define DBG_MISC_TPDM_PIDR0__PART_1___POR 0x0 +#define DBG_MISC_TPDM_PIDR0__PART_0___POR 0x0 +#define DBG_MISC_TPDM_PIDR0__PART_7___M 0x00000080 +#define DBG_MISC_TPDM_PIDR0__PART_7___S 7 +#define DBG_MISC_TPDM_PIDR0__PART_6___M 0x00000040 +#define DBG_MISC_TPDM_PIDR0__PART_6___S 6 +#define DBG_MISC_TPDM_PIDR0__PART_5___M 0x00000020 +#define DBG_MISC_TPDM_PIDR0__PART_5___S 5 +#define DBG_MISC_TPDM_PIDR0__PART_4___M 0x00000010 +#define DBG_MISC_TPDM_PIDR0__PART_4___S 4 +#define DBG_MISC_TPDM_PIDR0__PART_3___M 0x00000008 +#define DBG_MISC_TPDM_PIDR0__PART_3___S 3 +#define DBG_MISC_TPDM_PIDR0__PART_2___M 0x00000004 +#define DBG_MISC_TPDM_PIDR0__PART_2___S 2 +#define DBG_MISC_TPDM_PIDR0__PART_1___M 0x00000002 +#define DBG_MISC_TPDM_PIDR0__PART_1___S 1 +#define DBG_MISC_TPDM_PIDR0__PART_0___M 0x00000001 +#define DBG_MISC_TPDM_PIDR0__PART_0___S 0 +#define DBG_MISC_TPDM_PIDR0___M 0x000000FF +#define DBG_MISC_TPDM_PIDR0___S 0 + +#define DBG_MISC_TPDM_PIDR1 (0x00BC3FE4) +#define DBG_MISC_TPDM_PIDR1___RWC QCSR_REG_RO +#define DBG_MISC_TPDM_PIDR1___POR 0x0000000E +#define DBG_MISC_TPDM_PIDR1__DES_0___POR 0x0 +#define DBG_MISC_TPDM_PIDR1__PART_1___POR 0xE +#define DBG_MISC_TPDM_PIDR1__DES_0___M 0x000000F0 +#define DBG_MISC_TPDM_PIDR1__DES_0___S 4 +#define DBG_MISC_TPDM_PIDR1__PART_1___M 0x0000000F +#define DBG_MISC_TPDM_PIDR1__PART_1___S 0 +#define DBG_MISC_TPDM_PIDR1___M 0x000000FF +#define DBG_MISC_TPDM_PIDR1___S 0 + +#define DBG_MISC_TPDM_PIDR2 (0x00BC3FE8) +#define DBG_MISC_TPDM_PIDR2___RWC QCSR_REG_RO +#define DBG_MISC_TPDM_PIDR2___POR 0x00000018 +#define DBG_MISC_TPDM_PIDR2__REVISION___POR 0x1 +#define DBG_MISC_TPDM_PIDR2__JEDEC___POR 0x1 +#define DBG_MISC_TPDM_PIDR2__DES_1___POR 0x0 +#define DBG_MISC_TPDM_PIDR2__REVISION___M 0x000000F0 +#define DBG_MISC_TPDM_PIDR2__REVISION___S 4 +#define DBG_MISC_TPDM_PIDR2__JEDEC___M 0x00000008 +#define DBG_MISC_TPDM_PIDR2__JEDEC___S 3 +#define DBG_MISC_TPDM_PIDR2__DES_1___M 0x00000007 +#define DBG_MISC_TPDM_PIDR2__DES_1___S 0 +#define DBG_MISC_TPDM_PIDR2___M 0x000000FF +#define DBG_MISC_TPDM_PIDR2___S 0 + +#define DBG_MISC_TPDM_PIDR3 (0x00BC3FEC) +#define DBG_MISC_TPDM_PIDR3___RWC QCSR_REG_RO +#define DBG_MISC_TPDM_PIDR3___POR 0x00000000 +#define DBG_MISC_TPDM_PIDR3__REVAND___POR 0x0 +#define DBG_MISC_TPDM_PIDR3__CMOD___POR 0x0 +#define DBG_MISC_TPDM_PIDR3__REVAND___M 0x000000F0 +#define DBG_MISC_TPDM_PIDR3__REVAND___S 4 +#define DBG_MISC_TPDM_PIDR3__CMOD___M 0x0000000F +#define DBG_MISC_TPDM_PIDR3__CMOD___S 0 +#define DBG_MISC_TPDM_PIDR3___M 0x000000FF +#define DBG_MISC_TPDM_PIDR3___S 0 + +#define DBG_MISC_TPDM_CIDR0 (0x00BC3FF0) +#define DBG_MISC_TPDM_CIDR0___RWC QCSR_REG_RO +#define DBG_MISC_TPDM_CIDR0___POR 0x0000000D +#define DBG_MISC_TPDM_CIDR0__PRMBL_0___POR 0x0D +#define DBG_MISC_TPDM_CIDR0__PRMBL_0___M 0x000000FF +#define DBG_MISC_TPDM_CIDR0__PRMBL_0___S 0 +#define DBG_MISC_TPDM_CIDR0___M 0x000000FF +#define DBG_MISC_TPDM_CIDR0___S 0 + +#define DBG_MISC_TPDM_CIDR1 (0x00BC3FF4) +#define DBG_MISC_TPDM_CIDR1___RWC QCSR_REG_RO +#define DBG_MISC_TPDM_CIDR1___POR 0x00000090 +#define DBG_MISC_TPDM_CIDR1__CLASS___POR 0x9 +#define DBG_MISC_TPDM_CIDR1__PRMBL_1___POR 0x0 +#define DBG_MISC_TPDM_CIDR1__CLASS___M 0x000000F0 +#define DBG_MISC_TPDM_CIDR1__CLASS___S 4 +#define DBG_MISC_TPDM_CIDR1__PRMBL_1___M 0x0000000F +#define DBG_MISC_TPDM_CIDR1__PRMBL_1___S 0 +#define DBG_MISC_TPDM_CIDR1___M 0x000000FF +#define DBG_MISC_TPDM_CIDR1___S 0 + +#define DBG_MISC_TPDM_CIDR2 (0x00BC3FF8) +#define DBG_MISC_TPDM_CIDR2___RWC QCSR_REG_RO +#define DBG_MISC_TPDM_CIDR2___POR 0x00000005 +#define DBG_MISC_TPDM_CIDR2__PRMBL_2___POR 0x05 +#define DBG_MISC_TPDM_CIDR2__PRMBL_2___M 0x000000FF +#define DBG_MISC_TPDM_CIDR2__PRMBL_2___S 0 +#define DBG_MISC_TPDM_CIDR2___M 0x000000FF +#define DBG_MISC_TPDM_CIDR2___S 0 + +#define DBG_MISC_TPDM_CIDR3 (0x00BC3FFC) +#define DBG_MISC_TPDM_CIDR3___RWC QCSR_REG_RO +#define DBG_MISC_TPDM_CIDR3___POR 0x000000B1 +#define DBG_MISC_TPDM_CIDR3__PRMBL_3___POR 0xB1 +#define DBG_MISC_TPDM_CIDR3__PRMBL_3___M 0x000000FF +#define DBG_MISC_TPDM_CIDR3__PRMBL_3___S 0 +#define DBG_MISC_TPDM_CIDR3___M 0x000000FF +#define DBG_MISC_TPDM_CIDR3___S 0 + +#define DBG_MISC_TPDM_GPRn(n) (0x00BC3000+0x4*(n)) +#define DBG_MISC_TPDM_GPRn_nMIN 0 +#define DBG_MISC_TPDM_GPRn_nMAX 2 +#define DBG_MISC_TPDM_GPRn_ELEM 3 +#define DBG_MISC_TPDM_GPRn___RWC QCSR_REG_RW +#define DBG_MISC_TPDM_GPRn___POR 0x00000000 +#define DBG_MISC_TPDM_GPRn__VAL___POR 0x00000000 +#define DBG_MISC_TPDM_GPRn__VAL___M 0xFFFFFFFF +#define DBG_MISC_TPDM_GPRn__VAL___S 0 +#define DBG_MISC_TPDM_GPRn___M 0xFFFFFFFF +#define DBG_MISC_TPDM_GPRn___S 0 +#define DBG_MISC_TPDM_GPR0 (0x00BC3000) +#define DBG_MISC_TPDM_GPR0___RWC QCSR_REG_RW +#define DBG_MISC_TPDM_GPR0__VAL___M 0xFFFFFFFF +#define DBG_MISC_TPDM_GPR0__VAL___S 0 +#define DBG_MISC_TPDM_GPR1 (0x00BC3004) +#define DBG_MISC_TPDM_GPR1___RWC QCSR_REG_RW +#define DBG_MISC_TPDM_GPR1__VAL___M 0xFFFFFFFF +#define DBG_MISC_TPDM_GPR1__VAL___S 0 +#define DBG_MISC_TPDM_GPR2 (0x00BC3008) +#define DBG_MISC_TPDM_GPR2___RWC QCSR_REG_RW +#define DBG_MISC_TPDM_GPR2__VAL___M 0xFFFFFFFF +#define DBG_MISC_TPDM_GPR2__VAL___S 0 + +#define DBG_TGU_CONTROL (0x00BC4000) +#define DBG_TGU_CONTROL___RWC QCSR_REG_RW +#define DBG_TGU_CONTROL___POR 0x00000000 +#define DBG_TGU_CONTROL__FSM_ENABLE___POR 0x0 +#define DBG_TGU_CONTROL__FSM_ENABLE___M 0x00000001 +#define DBG_TGU_CONTROL__FSM_ENABLE___S 0 +#define DBG_TGU_CONTROL___M 0x00000001 +#define DBG_TGU_CONTROL___S 0 + +#define DBG_TIMER0_STATUS (0x00BC4004) +#define DBG_TIMER0_STATUS___RWC QCSR_REG_RO +#define DBG_TIMER0_STATUS___POR 0x00000000 +#define DBG_TIMER0_STATUS__COUNT___POR 0x0000 +#define DBG_TIMER0_STATUS__COUNT___M 0x0000FFFF +#define DBG_TIMER0_STATUS__COUNT___S 0 +#define DBG_TIMER0_STATUS___M 0x0000FFFF +#define DBG_TIMER0_STATUS___S 0 + +#define DBG_COUNTER0_STATUS (0x00BC400C) +#define DBG_COUNTER0_STATUS___RWC QCSR_REG_RO +#define DBG_COUNTER0_STATUS___POR 0x00000000 +#define DBG_COUNTER0_STATUS__COUNT___POR 0x0000 +#define DBG_COUNTER0_STATUS__COUNT___M 0x0000FFFF +#define DBG_COUNTER0_STATUS__COUNT___S 0 +#define DBG_COUNTER0_STATUS___M 0x0000FFFF +#define DBG_COUNTER0_STATUS___S 0 + +#define DBG_TGU_STATUS (0x00BC4014) +#define DBG_TGU_STATUS___RWC QCSR_REG_RO +#define DBG_TGU_STATUS___POR 0x00000000 +#define DBG_TGU_STATUS__TRIGGERS___POR 0x0 +#define DBG_TGU_STATUS__CURRENT_STEP___POR 0x0 +#define DBG_TGU_STATUS__FSM_STATE___POR 0x0 +#define DBG_TGU_STATUS__TRIGGERS___M 0x00000F00 +#define DBG_TGU_STATUS__TRIGGERS___S 8 +#define DBG_TGU_STATUS__CURRENT_STEP___M 0x0000001C +#define DBG_TGU_STATUS__CURRENT_STEP___S 2 +#define DBG_TGU_STATUS__FSM_STATE___M 0x00000003 +#define DBG_TGU_STATUS__FSM_STATE___S 0 +#define DBG_TGU_STATUS___M 0x00000F1F +#define DBG_TGU_STATUS___S 0 + +#define DBG_TIMER0_COMPARE_STEPn(n) (0x00BC4040+0x1D8*(n)) +#define DBG_TIMER0_COMPARE_STEPn_nMIN 0 +#define DBG_TIMER0_COMPARE_STEPn_nMAX 7 +#define DBG_TIMER0_COMPARE_STEPn_ELEM 8 +#define DBG_TIMER0_COMPARE_STEPn___RWC QCSR_REG_RW +#define DBG_TIMER0_COMPARE_STEPn___POR 0x00000000 +#define DBG_TIMER0_COMPARE_STEPn__COUNT___POR 0x0000 +#define DBG_TIMER0_COMPARE_STEPn__COUNT___M 0x0000FFFF +#define DBG_TIMER0_COMPARE_STEPn__COUNT___S 0 +#define DBG_TIMER0_COMPARE_STEPn___M 0x0000FFFF +#define DBG_TIMER0_COMPARE_STEPn___S 0 +#define DBG_TIMER0_COMPARE_STEP0 (0x00BC4040) +#define DBG_TIMER0_COMPARE_STEP0___RWC QCSR_REG_RW +#define DBG_TIMER0_COMPARE_STEP0__COUNT___M 0x0000FFFF +#define DBG_TIMER0_COMPARE_STEP0__COUNT___S 0 +#define DBG_TIMER0_COMPARE_STEP1 (0x00BC4218) +#define DBG_TIMER0_COMPARE_STEP1___RWC QCSR_REG_RW +#define DBG_TIMER0_COMPARE_STEP1__COUNT___M 0x0000FFFF +#define DBG_TIMER0_COMPARE_STEP1__COUNT___S 0 +#define DBG_TIMER0_COMPARE_STEP2 (0x00BC43F0) +#define DBG_TIMER0_COMPARE_STEP2___RWC QCSR_REG_RW +#define DBG_TIMER0_COMPARE_STEP2__COUNT___M 0x0000FFFF +#define DBG_TIMER0_COMPARE_STEP2__COUNT___S 0 +#define DBG_TIMER0_COMPARE_STEP3 (0x00BC45C8) +#define DBG_TIMER0_COMPARE_STEP3___RWC QCSR_REG_RW +#define DBG_TIMER0_COMPARE_STEP3__COUNT___M 0x0000FFFF +#define DBG_TIMER0_COMPARE_STEP3__COUNT___S 0 +#define DBG_TIMER0_COMPARE_STEP4 (0x00BC47A0) +#define DBG_TIMER0_COMPARE_STEP4___RWC QCSR_REG_RW +#define DBG_TIMER0_COMPARE_STEP4__COUNT___M 0x0000FFFF +#define DBG_TIMER0_COMPARE_STEP4__COUNT___S 0 +#define DBG_TIMER0_COMPARE_STEP5 (0x00BC4978) +#define DBG_TIMER0_COMPARE_STEP5___RWC QCSR_REG_RW +#define DBG_TIMER0_COMPARE_STEP5__COUNT___M 0x0000FFFF +#define DBG_TIMER0_COMPARE_STEP5__COUNT___S 0 +#define DBG_TIMER0_COMPARE_STEP6 (0x00BC4B50) +#define DBG_TIMER0_COMPARE_STEP6___RWC QCSR_REG_RW +#define DBG_TIMER0_COMPARE_STEP6__COUNT___M 0x0000FFFF +#define DBG_TIMER0_COMPARE_STEP6__COUNT___S 0 +#define DBG_TIMER0_COMPARE_STEP7 (0x00BC4D28) +#define DBG_TIMER0_COMPARE_STEP7___RWC QCSR_REG_RW +#define DBG_TIMER0_COMPARE_STEP7__COUNT___M 0x0000FFFF +#define DBG_TIMER0_COMPARE_STEP7__COUNT___S 0 + +#define DBG_COUNTER0_COMPARE_STEPn(n) (0x00BC4048+0x1D8*(n)) +#define DBG_COUNTER0_COMPARE_STEPn_nMIN 0 +#define DBG_COUNTER0_COMPARE_STEPn_nMAX 7 +#define DBG_COUNTER0_COMPARE_STEPn_ELEM 8 +#define DBG_COUNTER0_COMPARE_STEPn___RWC QCSR_REG_RW +#define DBG_COUNTER0_COMPARE_STEPn___POR 0x00000000 +#define DBG_COUNTER0_COMPARE_STEPn__COUNT___POR 0x0000 +#define DBG_COUNTER0_COMPARE_STEPn__COUNT___M 0x0000FFFF +#define DBG_COUNTER0_COMPARE_STEPn__COUNT___S 0 +#define DBG_COUNTER0_COMPARE_STEPn___M 0x0000FFFF +#define DBG_COUNTER0_COMPARE_STEPn___S 0 +#define DBG_COUNTER0_COMPARE_STEP0 (0x00BC4048) +#define DBG_COUNTER0_COMPARE_STEP0___RWC QCSR_REG_RW +#define DBG_COUNTER0_COMPARE_STEP0__COUNT___M 0x0000FFFF +#define DBG_COUNTER0_COMPARE_STEP0__COUNT___S 0 +#define DBG_COUNTER0_COMPARE_STEP1 (0x00BC4220) +#define DBG_COUNTER0_COMPARE_STEP1___RWC QCSR_REG_RW +#define DBG_COUNTER0_COMPARE_STEP1__COUNT___M 0x0000FFFF +#define DBG_COUNTER0_COMPARE_STEP1__COUNT___S 0 +#define DBG_COUNTER0_COMPARE_STEP2 (0x00BC43F8) +#define DBG_COUNTER0_COMPARE_STEP2___RWC QCSR_REG_RW +#define DBG_COUNTER0_COMPARE_STEP2__COUNT___M 0x0000FFFF +#define DBG_COUNTER0_COMPARE_STEP2__COUNT___S 0 +#define DBG_COUNTER0_COMPARE_STEP3 (0x00BC45D0) +#define DBG_COUNTER0_COMPARE_STEP3___RWC QCSR_REG_RW +#define DBG_COUNTER0_COMPARE_STEP3__COUNT___M 0x0000FFFF +#define DBG_COUNTER0_COMPARE_STEP3__COUNT___S 0 +#define DBG_COUNTER0_COMPARE_STEP4 (0x00BC47A8) +#define DBG_COUNTER0_COMPARE_STEP4___RWC QCSR_REG_RW +#define DBG_COUNTER0_COMPARE_STEP4__COUNT___M 0x0000FFFF +#define DBG_COUNTER0_COMPARE_STEP4__COUNT___S 0 +#define DBG_COUNTER0_COMPARE_STEP5 (0x00BC4980) +#define DBG_COUNTER0_COMPARE_STEP5___RWC QCSR_REG_RW +#define DBG_COUNTER0_COMPARE_STEP5__COUNT___M 0x0000FFFF +#define DBG_COUNTER0_COMPARE_STEP5__COUNT___S 0 +#define DBG_COUNTER0_COMPARE_STEP6 (0x00BC4B58) +#define DBG_COUNTER0_COMPARE_STEP6___RWC QCSR_REG_RW +#define DBG_COUNTER0_COMPARE_STEP6__COUNT___M 0x0000FFFF +#define DBG_COUNTER0_COMPARE_STEP6__COUNT___S 0 +#define DBG_COUNTER0_COMPARE_STEP7 (0x00BC4D30) +#define DBG_COUNTER0_COMPARE_STEP7___RWC QCSR_REG_RW +#define DBG_COUNTER0_COMPARE_STEP7__COUNT___M 0x0000FFFF +#define DBG_COUNTER0_COMPARE_STEP7__COUNT___S 0 + +#define DBG_CONDITION_DECODEm_STEPn(m,n) (0x00BC4050+0x4*(m)+0x1D8*(n)) +#define DBG_CONDITION_DECODEm_STEPn_mMIN 0 +#define DBG_CONDITION_DECODEm_STEPn_mMAX 3 +#define DBG_CONDITION_DECODEm_STEPn_nMIN 0 +#define DBG_CONDITION_DECODEm_STEPn_nMAX 7 +#define DBG_CONDITION_DECODEm_STEPn_ELEM 32 +#define DBG_CONDITION_DECODEm_STEPn___RWC QCSR_REG_RW +#define DBG_CONDITION_DECODEm_STEPn___POR 0x00000000 +#define DBG_CONDITION_DECODEm_STEPn__NOT___POR 0x0 +#define DBG_CONDITION_DECODEm_STEPn__BC0_COMP_ACTIVE___POR 0x0 +#define DBG_CONDITION_DECODEm_STEPn__BC0_COMP_HIGH___POR 0x0 +#define DBG_CONDITION_DECODEm_STEPn__TC0_COMP_ACTIVE___POR 0x0 +#define DBG_CONDITION_DECODEm_STEPn__TC0_COMP_HIGH___POR 0x0 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_3_OR_ACTIVE___POR 0x0 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_3_OR_HIGH___POR 0x0 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_3_AND_ACTIVE___POR 0x0 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_3_AND_HIGH___POR 0x0 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_2_OR_ACTIVE___POR 0x0 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_2_OR_HIGH___POR 0x0 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_2_AND_ACTIVE___POR 0x0 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_2_AND_HIGH___POR 0x0 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_1_OR_ACTIVE___POR 0x0 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_1_OR_HIGH___POR 0x0 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_1_AND_ACTIVE___POR 0x0 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_1_AND_HIGH___POR 0x0 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_0_OR_ACTIVE___POR 0x0 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_0_OR_HIGH___POR 0x0 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_0_AND_ACTIVE___POR 0x0 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_0_AND_HIGH___POR 0x0 +#define DBG_CONDITION_DECODEm_STEPn__NOT___M 0x01000000 +#define DBG_CONDITION_DECODEm_STEPn__NOT___S 24 +#define DBG_CONDITION_DECODEm_STEPn__BC0_COMP_ACTIVE___M 0x00200000 +#define DBG_CONDITION_DECODEm_STEPn__BC0_COMP_ACTIVE___S 21 +#define DBG_CONDITION_DECODEm_STEPn__BC0_COMP_HIGH___M 0x00100000 +#define DBG_CONDITION_DECODEm_STEPn__BC0_COMP_HIGH___S 20 +#define DBG_CONDITION_DECODEm_STEPn__TC0_COMP_ACTIVE___M 0x00020000 +#define DBG_CONDITION_DECODEm_STEPn__TC0_COMP_ACTIVE___S 17 +#define DBG_CONDITION_DECODEm_STEPn__TC0_COMP_HIGH___M 0x00010000 +#define DBG_CONDITION_DECODEm_STEPn__TC0_COMP_HIGH___S 16 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_3_OR_ACTIVE___M 0x00008000 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_3_OR_ACTIVE___S 15 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_3_OR_HIGH___M 0x00004000 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_3_OR_HIGH___S 14 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_3_AND_ACTIVE___M 0x00002000 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_3_AND_ACTIVE___S 13 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_3_AND_HIGH___M 0x00001000 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_3_AND_HIGH___S 12 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_2_OR_ACTIVE___M 0x00000800 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_2_OR_ACTIVE___S 11 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_2_OR_HIGH___M 0x00000400 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_2_OR_HIGH___S 10 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_2_AND_ACTIVE___M 0x00000200 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_2_AND_ACTIVE___S 9 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_2_AND_HIGH___M 0x00000100 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_2_AND_HIGH___S 8 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_1_OR_ACTIVE___M 0x00000080 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_1_OR_ACTIVE___S 7 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_1_OR_HIGH___M 0x00000040 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_1_OR_HIGH___S 6 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_1_AND_ACTIVE___M 0x00000020 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_1_AND_ACTIVE___S 5 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_1_AND_HIGH___M 0x00000010 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_1_AND_HIGH___S 4 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_0_OR_ACTIVE___M 0x00000008 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_0_OR_ACTIVE___S 3 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_0_OR_HIGH___M 0x00000004 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_0_OR_HIGH___S 2 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_0_AND_ACTIVE___M 0x00000002 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_0_AND_ACTIVE___S 1 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_0_AND_HIGH___M 0x00000001 +#define DBG_CONDITION_DECODEm_STEPn__GROUP_0_AND_HIGH___S 0 +#define DBG_CONDITION_DECODEm_STEPn___M 0x0133FFFF +#define DBG_CONDITION_DECODEm_STEPn___S 0 +#define DBG_CONDITION_DECODE0_STEP0 (0x00BC4050) +#define DBG_CONDITION_DECODE0_STEP0___RWC QCSR_REG_RW +#define DBG_CONDITION_DECODE0_STEP0__NOT___M 0x01000000 +#define DBG_CONDITION_DECODE0_STEP0__NOT___S 24 +#define DBG_CONDITION_DECODE0_STEP0__BC0_COMP_ACTIVE___M 0x00200000 +#define DBG_CONDITION_DECODE0_STEP0__BC0_COMP_ACTIVE___S 21 +#define DBG_CONDITION_DECODE0_STEP0__BC0_COMP_HIGH___M 0x00100000 +#define DBG_CONDITION_DECODE0_STEP0__BC0_COMP_HIGH___S 20 +#define DBG_CONDITION_DECODE0_STEP0__TC0_COMP_ACTIVE___M 0x00020000 +#define DBG_CONDITION_DECODE0_STEP0__TC0_COMP_ACTIVE___S 17 +#define DBG_CONDITION_DECODE0_STEP0__TC0_COMP_HIGH___M 0x00010000 +#define DBG_CONDITION_DECODE0_STEP0__TC0_COMP_HIGH___S 16 +#define DBG_CONDITION_DECODE0_STEP0__GROUP_3_OR_ACTIVE___M 0x00008000 +#define DBG_CONDITION_DECODE0_STEP0__GROUP_3_OR_ACTIVE___S 15 +#define DBG_CONDITION_DECODE0_STEP0__GROUP_3_OR_HIGH___M 0x00004000 +#define DBG_CONDITION_DECODE0_STEP0__GROUP_3_OR_HIGH___S 14 +#define DBG_CONDITION_DECODE0_STEP0__GROUP_3_AND_ACTIVE___M 0x00002000 +#define DBG_CONDITION_DECODE0_STEP0__GROUP_3_AND_ACTIVE___S 13 +#define DBG_CONDITION_DECODE0_STEP0__GROUP_3_AND_HIGH___M 0x00001000 +#define DBG_CONDITION_DECODE0_STEP0__GROUP_3_AND_HIGH___S 12 +#define DBG_CONDITION_DECODE0_STEP0__GROUP_2_OR_ACTIVE___M 0x00000800 +#define DBG_CONDITION_DECODE0_STEP0__GROUP_2_OR_ACTIVE___S 11 +#define DBG_CONDITION_DECODE0_STEP0__GROUP_2_OR_HIGH___M 0x00000400 +#define DBG_CONDITION_DECODE0_STEP0__GROUP_2_OR_HIGH___S 10 +#define DBG_CONDITION_DECODE0_STEP0__GROUP_2_AND_ACTIVE___M 0x00000200 +#define DBG_CONDITION_DECODE0_STEP0__GROUP_2_AND_ACTIVE___S 9 +#define DBG_CONDITION_DECODE0_STEP0__GROUP_2_AND_HIGH___M 0x00000100 +#define DBG_CONDITION_DECODE0_STEP0__GROUP_2_AND_HIGH___S 8 +#define DBG_CONDITION_DECODE0_STEP0__GROUP_1_OR_ACTIVE___M 0x00000080 +#define DBG_CONDITION_DECODE0_STEP0__GROUP_1_OR_ACTIVE___S 7 +#define DBG_CONDITION_DECODE0_STEP0__GROUP_1_OR_HIGH___M 0x00000040 +#define DBG_CONDITION_DECODE0_STEP0__GROUP_1_OR_HIGH___S 6 +#define DBG_CONDITION_DECODE0_STEP0__GROUP_1_AND_ACTIVE___M 0x00000020 +#define DBG_CONDITION_DECODE0_STEP0__GROUP_1_AND_ACTIVE___S 5 +#define DBG_CONDITION_DECODE0_STEP0__GROUP_1_AND_HIGH___M 0x00000010 +#define DBG_CONDITION_DECODE0_STEP0__GROUP_1_AND_HIGH___S 4 +#define DBG_CONDITION_DECODE0_STEP0__GROUP_0_OR_ACTIVE___M 0x00000008 +#define DBG_CONDITION_DECODE0_STEP0__GROUP_0_OR_ACTIVE___S 3 +#define DBG_CONDITION_DECODE0_STEP0__GROUP_0_OR_HIGH___M 0x00000004 +#define DBG_CONDITION_DECODE0_STEP0__GROUP_0_OR_HIGH___S 2 +#define DBG_CONDITION_DECODE0_STEP0__GROUP_0_AND_ACTIVE___M 0x00000002 +#define DBG_CONDITION_DECODE0_STEP0__GROUP_0_AND_ACTIVE___S 1 +#define DBG_CONDITION_DECODE0_STEP0__GROUP_0_AND_HIGH___M 0x00000001 +#define DBG_CONDITION_DECODE0_STEP0__GROUP_0_AND_HIGH___S 0 +#define DBG_CONDITION_DECODE0_STEP1 (0x00BC4228) +#define DBG_CONDITION_DECODE0_STEP1___RWC QCSR_REG_RW +#define DBG_CONDITION_DECODE0_STEP1__NOT___M 0x01000000 +#define DBG_CONDITION_DECODE0_STEP1__NOT___S 24 +#define DBG_CONDITION_DECODE0_STEP1__BC0_COMP_ACTIVE___M 0x00200000 +#define DBG_CONDITION_DECODE0_STEP1__BC0_COMP_ACTIVE___S 21 +#define DBG_CONDITION_DECODE0_STEP1__BC0_COMP_HIGH___M 0x00100000 +#define DBG_CONDITION_DECODE0_STEP1__BC0_COMP_HIGH___S 20 +#define DBG_CONDITION_DECODE0_STEP1__TC0_COMP_ACTIVE___M 0x00020000 +#define DBG_CONDITION_DECODE0_STEP1__TC0_COMP_ACTIVE___S 17 +#define DBG_CONDITION_DECODE0_STEP1__TC0_COMP_HIGH___M 0x00010000 +#define DBG_CONDITION_DECODE0_STEP1__TC0_COMP_HIGH___S 16 +#define DBG_CONDITION_DECODE0_STEP1__GROUP_3_OR_ACTIVE___M 0x00008000 +#define DBG_CONDITION_DECODE0_STEP1__GROUP_3_OR_ACTIVE___S 15 +#define DBG_CONDITION_DECODE0_STEP1__GROUP_3_OR_HIGH___M 0x00004000 +#define DBG_CONDITION_DECODE0_STEP1__GROUP_3_OR_HIGH___S 14 +#define DBG_CONDITION_DECODE0_STEP1__GROUP_3_AND_ACTIVE___M 0x00002000 +#define DBG_CONDITION_DECODE0_STEP1__GROUP_3_AND_ACTIVE___S 13 +#define DBG_CONDITION_DECODE0_STEP1__GROUP_3_AND_HIGH___M 0x00001000 +#define DBG_CONDITION_DECODE0_STEP1__GROUP_3_AND_HIGH___S 12 +#define DBG_CONDITION_DECODE0_STEP1__GROUP_2_OR_ACTIVE___M 0x00000800 +#define DBG_CONDITION_DECODE0_STEP1__GROUP_2_OR_ACTIVE___S 11 +#define DBG_CONDITION_DECODE0_STEP1__GROUP_2_OR_HIGH___M 0x00000400 +#define DBG_CONDITION_DECODE0_STEP1__GROUP_2_OR_HIGH___S 10 +#define DBG_CONDITION_DECODE0_STEP1__GROUP_2_AND_ACTIVE___M 0x00000200 +#define DBG_CONDITION_DECODE0_STEP1__GROUP_2_AND_ACTIVE___S 9 +#define DBG_CONDITION_DECODE0_STEP1__GROUP_2_AND_HIGH___M 0x00000100 +#define DBG_CONDITION_DECODE0_STEP1__GROUP_2_AND_HIGH___S 8 +#define DBG_CONDITION_DECODE0_STEP1__GROUP_1_OR_ACTIVE___M 0x00000080 +#define DBG_CONDITION_DECODE0_STEP1__GROUP_1_OR_ACTIVE___S 7 +#define DBG_CONDITION_DECODE0_STEP1__GROUP_1_OR_HIGH___M 0x00000040 +#define DBG_CONDITION_DECODE0_STEP1__GROUP_1_OR_HIGH___S 6 +#define DBG_CONDITION_DECODE0_STEP1__GROUP_1_AND_ACTIVE___M 0x00000020 +#define DBG_CONDITION_DECODE0_STEP1__GROUP_1_AND_ACTIVE___S 5 +#define DBG_CONDITION_DECODE0_STEP1__GROUP_1_AND_HIGH___M 0x00000010 +#define DBG_CONDITION_DECODE0_STEP1__GROUP_1_AND_HIGH___S 4 +#define DBG_CONDITION_DECODE0_STEP1__GROUP_0_OR_ACTIVE___M 0x00000008 +#define DBG_CONDITION_DECODE0_STEP1__GROUP_0_OR_ACTIVE___S 3 +#define DBG_CONDITION_DECODE0_STEP1__GROUP_0_OR_HIGH___M 0x00000004 +#define DBG_CONDITION_DECODE0_STEP1__GROUP_0_OR_HIGH___S 2 +#define DBG_CONDITION_DECODE0_STEP1__GROUP_0_AND_ACTIVE___M 0x00000002 +#define DBG_CONDITION_DECODE0_STEP1__GROUP_0_AND_ACTIVE___S 1 +#define DBG_CONDITION_DECODE0_STEP1__GROUP_0_AND_HIGH___M 0x00000001 +#define DBG_CONDITION_DECODE0_STEP1__GROUP_0_AND_HIGH___S 0 +#define DBG_CONDITION_DECODE0_STEP2 (0x00BC4400) +#define DBG_CONDITION_DECODE0_STEP2___RWC QCSR_REG_RW +#define DBG_CONDITION_DECODE0_STEP2__NOT___M 0x01000000 +#define DBG_CONDITION_DECODE0_STEP2__NOT___S 24 +#define DBG_CONDITION_DECODE0_STEP2__BC0_COMP_ACTIVE___M 0x00200000 +#define DBG_CONDITION_DECODE0_STEP2__BC0_COMP_ACTIVE___S 21 +#define DBG_CONDITION_DECODE0_STEP2__BC0_COMP_HIGH___M 0x00100000 +#define DBG_CONDITION_DECODE0_STEP2__BC0_COMP_HIGH___S 20 +#define DBG_CONDITION_DECODE0_STEP2__TC0_COMP_ACTIVE___M 0x00020000 +#define DBG_CONDITION_DECODE0_STEP2__TC0_COMP_ACTIVE___S 17 +#define DBG_CONDITION_DECODE0_STEP2__TC0_COMP_HIGH___M 0x00010000 +#define DBG_CONDITION_DECODE0_STEP2__TC0_COMP_HIGH___S 16 +#define DBG_CONDITION_DECODE0_STEP2__GROUP_3_OR_ACTIVE___M 0x00008000 +#define DBG_CONDITION_DECODE0_STEP2__GROUP_3_OR_ACTIVE___S 15 +#define DBG_CONDITION_DECODE0_STEP2__GROUP_3_OR_HIGH___M 0x00004000 +#define DBG_CONDITION_DECODE0_STEP2__GROUP_3_OR_HIGH___S 14 +#define DBG_CONDITION_DECODE0_STEP2__GROUP_3_AND_ACTIVE___M 0x00002000 +#define DBG_CONDITION_DECODE0_STEP2__GROUP_3_AND_ACTIVE___S 13 +#define DBG_CONDITION_DECODE0_STEP2__GROUP_3_AND_HIGH___M 0x00001000 +#define DBG_CONDITION_DECODE0_STEP2__GROUP_3_AND_HIGH___S 12 +#define DBG_CONDITION_DECODE0_STEP2__GROUP_2_OR_ACTIVE___M 0x00000800 +#define DBG_CONDITION_DECODE0_STEP2__GROUP_2_OR_ACTIVE___S 11 +#define DBG_CONDITION_DECODE0_STEP2__GROUP_2_OR_HIGH___M 0x00000400 +#define DBG_CONDITION_DECODE0_STEP2__GROUP_2_OR_HIGH___S 10 +#define DBG_CONDITION_DECODE0_STEP2__GROUP_2_AND_ACTIVE___M 0x00000200 +#define DBG_CONDITION_DECODE0_STEP2__GROUP_2_AND_ACTIVE___S 9 +#define DBG_CONDITION_DECODE0_STEP2__GROUP_2_AND_HIGH___M 0x00000100 +#define DBG_CONDITION_DECODE0_STEP2__GROUP_2_AND_HIGH___S 8 +#define DBG_CONDITION_DECODE0_STEP2__GROUP_1_OR_ACTIVE___M 0x00000080 +#define DBG_CONDITION_DECODE0_STEP2__GROUP_1_OR_ACTIVE___S 7 +#define DBG_CONDITION_DECODE0_STEP2__GROUP_1_OR_HIGH___M 0x00000040 +#define DBG_CONDITION_DECODE0_STEP2__GROUP_1_OR_HIGH___S 6 +#define DBG_CONDITION_DECODE0_STEP2__GROUP_1_AND_ACTIVE___M 0x00000020 +#define DBG_CONDITION_DECODE0_STEP2__GROUP_1_AND_ACTIVE___S 5 +#define DBG_CONDITION_DECODE0_STEP2__GROUP_1_AND_HIGH___M 0x00000010 +#define DBG_CONDITION_DECODE0_STEP2__GROUP_1_AND_HIGH___S 4 +#define DBG_CONDITION_DECODE0_STEP2__GROUP_0_OR_ACTIVE___M 0x00000008 +#define DBG_CONDITION_DECODE0_STEP2__GROUP_0_OR_ACTIVE___S 3 +#define DBG_CONDITION_DECODE0_STEP2__GROUP_0_OR_HIGH___M 0x00000004 +#define DBG_CONDITION_DECODE0_STEP2__GROUP_0_OR_HIGH___S 2 +#define DBG_CONDITION_DECODE0_STEP2__GROUP_0_AND_ACTIVE___M 0x00000002 +#define DBG_CONDITION_DECODE0_STEP2__GROUP_0_AND_ACTIVE___S 1 +#define DBG_CONDITION_DECODE0_STEP2__GROUP_0_AND_HIGH___M 0x00000001 +#define DBG_CONDITION_DECODE0_STEP2__GROUP_0_AND_HIGH___S 0 +#define DBG_CONDITION_DECODE0_STEP3 (0x00BC45D8) +#define DBG_CONDITION_DECODE0_STEP3___RWC QCSR_REG_RW +#define DBG_CONDITION_DECODE0_STEP3__NOT___M 0x01000000 +#define DBG_CONDITION_DECODE0_STEP3__NOT___S 24 +#define DBG_CONDITION_DECODE0_STEP3__BC0_COMP_ACTIVE___M 0x00200000 +#define DBG_CONDITION_DECODE0_STEP3__BC0_COMP_ACTIVE___S 21 +#define DBG_CONDITION_DECODE0_STEP3__BC0_COMP_HIGH___M 0x00100000 +#define DBG_CONDITION_DECODE0_STEP3__BC0_COMP_HIGH___S 20 +#define DBG_CONDITION_DECODE0_STEP3__TC0_COMP_ACTIVE___M 0x00020000 +#define DBG_CONDITION_DECODE0_STEP3__TC0_COMP_ACTIVE___S 17 +#define DBG_CONDITION_DECODE0_STEP3__TC0_COMP_HIGH___M 0x00010000 +#define DBG_CONDITION_DECODE0_STEP3__TC0_COMP_HIGH___S 16 +#define DBG_CONDITION_DECODE0_STEP3__GROUP_3_OR_ACTIVE___M 0x00008000 +#define DBG_CONDITION_DECODE0_STEP3__GROUP_3_OR_ACTIVE___S 15 +#define DBG_CONDITION_DECODE0_STEP3__GROUP_3_OR_HIGH___M 0x00004000 +#define DBG_CONDITION_DECODE0_STEP3__GROUP_3_OR_HIGH___S 14 +#define DBG_CONDITION_DECODE0_STEP3__GROUP_3_AND_ACTIVE___M 0x00002000 +#define DBG_CONDITION_DECODE0_STEP3__GROUP_3_AND_ACTIVE___S 13 +#define DBG_CONDITION_DECODE0_STEP3__GROUP_3_AND_HIGH___M 0x00001000 +#define DBG_CONDITION_DECODE0_STEP3__GROUP_3_AND_HIGH___S 12 +#define DBG_CONDITION_DECODE0_STEP3__GROUP_2_OR_ACTIVE___M 0x00000800 +#define DBG_CONDITION_DECODE0_STEP3__GROUP_2_OR_ACTIVE___S 11 +#define DBG_CONDITION_DECODE0_STEP3__GROUP_2_OR_HIGH___M 0x00000400 +#define DBG_CONDITION_DECODE0_STEP3__GROUP_2_OR_HIGH___S 10 +#define DBG_CONDITION_DECODE0_STEP3__GROUP_2_AND_ACTIVE___M 0x00000200 +#define DBG_CONDITION_DECODE0_STEP3__GROUP_2_AND_ACTIVE___S 9 +#define DBG_CONDITION_DECODE0_STEP3__GROUP_2_AND_HIGH___M 0x00000100 +#define DBG_CONDITION_DECODE0_STEP3__GROUP_2_AND_HIGH___S 8 +#define DBG_CONDITION_DECODE0_STEP3__GROUP_1_OR_ACTIVE___M 0x00000080 +#define DBG_CONDITION_DECODE0_STEP3__GROUP_1_OR_ACTIVE___S 7 +#define DBG_CONDITION_DECODE0_STEP3__GROUP_1_OR_HIGH___M 0x00000040 +#define DBG_CONDITION_DECODE0_STEP3__GROUP_1_OR_HIGH___S 6 +#define DBG_CONDITION_DECODE0_STEP3__GROUP_1_AND_ACTIVE___M 0x00000020 +#define DBG_CONDITION_DECODE0_STEP3__GROUP_1_AND_ACTIVE___S 5 +#define DBG_CONDITION_DECODE0_STEP3__GROUP_1_AND_HIGH___M 0x00000010 +#define DBG_CONDITION_DECODE0_STEP3__GROUP_1_AND_HIGH___S 4 +#define DBG_CONDITION_DECODE0_STEP3__GROUP_0_OR_ACTIVE___M 0x00000008 +#define DBG_CONDITION_DECODE0_STEP3__GROUP_0_OR_ACTIVE___S 3 +#define DBG_CONDITION_DECODE0_STEP3__GROUP_0_OR_HIGH___M 0x00000004 +#define DBG_CONDITION_DECODE0_STEP3__GROUP_0_OR_HIGH___S 2 +#define DBG_CONDITION_DECODE0_STEP3__GROUP_0_AND_ACTIVE___M 0x00000002 +#define DBG_CONDITION_DECODE0_STEP3__GROUP_0_AND_ACTIVE___S 1 +#define DBG_CONDITION_DECODE0_STEP3__GROUP_0_AND_HIGH___M 0x00000001 +#define DBG_CONDITION_DECODE0_STEP3__GROUP_0_AND_HIGH___S 0 +#define DBG_CONDITION_DECODE0_STEP4 (0x00BC47B0) +#define DBG_CONDITION_DECODE0_STEP4___RWC QCSR_REG_RW +#define DBG_CONDITION_DECODE0_STEP4__NOT___M 0x01000000 +#define DBG_CONDITION_DECODE0_STEP4__NOT___S 24 +#define DBG_CONDITION_DECODE0_STEP4__BC0_COMP_ACTIVE___M 0x00200000 +#define DBG_CONDITION_DECODE0_STEP4__BC0_COMP_ACTIVE___S 21 +#define DBG_CONDITION_DECODE0_STEP4__BC0_COMP_HIGH___M 0x00100000 +#define DBG_CONDITION_DECODE0_STEP4__BC0_COMP_HIGH___S 20 +#define DBG_CONDITION_DECODE0_STEP4__TC0_COMP_ACTIVE___M 0x00020000 +#define DBG_CONDITION_DECODE0_STEP4__TC0_COMP_ACTIVE___S 17 +#define DBG_CONDITION_DECODE0_STEP4__TC0_COMP_HIGH___M 0x00010000 +#define DBG_CONDITION_DECODE0_STEP4__TC0_COMP_HIGH___S 16 +#define DBG_CONDITION_DECODE0_STEP4__GROUP_3_OR_ACTIVE___M 0x00008000 +#define DBG_CONDITION_DECODE0_STEP4__GROUP_3_OR_ACTIVE___S 15 +#define DBG_CONDITION_DECODE0_STEP4__GROUP_3_OR_HIGH___M 0x00004000 +#define DBG_CONDITION_DECODE0_STEP4__GROUP_3_OR_HIGH___S 14 +#define DBG_CONDITION_DECODE0_STEP4__GROUP_3_AND_ACTIVE___M 0x00002000 +#define DBG_CONDITION_DECODE0_STEP4__GROUP_3_AND_ACTIVE___S 13 +#define DBG_CONDITION_DECODE0_STEP4__GROUP_3_AND_HIGH___M 0x00001000 +#define DBG_CONDITION_DECODE0_STEP4__GROUP_3_AND_HIGH___S 12 +#define DBG_CONDITION_DECODE0_STEP4__GROUP_2_OR_ACTIVE___M 0x00000800 +#define DBG_CONDITION_DECODE0_STEP4__GROUP_2_OR_ACTIVE___S 11 +#define DBG_CONDITION_DECODE0_STEP4__GROUP_2_OR_HIGH___M 0x00000400 +#define DBG_CONDITION_DECODE0_STEP4__GROUP_2_OR_HIGH___S 10 +#define DBG_CONDITION_DECODE0_STEP4__GROUP_2_AND_ACTIVE___M 0x00000200 +#define DBG_CONDITION_DECODE0_STEP4__GROUP_2_AND_ACTIVE___S 9 +#define DBG_CONDITION_DECODE0_STEP4__GROUP_2_AND_HIGH___M 0x00000100 +#define DBG_CONDITION_DECODE0_STEP4__GROUP_2_AND_HIGH___S 8 +#define DBG_CONDITION_DECODE0_STEP4__GROUP_1_OR_ACTIVE___M 0x00000080 +#define DBG_CONDITION_DECODE0_STEP4__GROUP_1_OR_ACTIVE___S 7 +#define DBG_CONDITION_DECODE0_STEP4__GROUP_1_OR_HIGH___M 0x00000040 +#define DBG_CONDITION_DECODE0_STEP4__GROUP_1_OR_HIGH___S 6 +#define DBG_CONDITION_DECODE0_STEP4__GROUP_1_AND_ACTIVE___M 0x00000020 +#define DBG_CONDITION_DECODE0_STEP4__GROUP_1_AND_ACTIVE___S 5 +#define DBG_CONDITION_DECODE0_STEP4__GROUP_1_AND_HIGH___M 0x00000010 +#define DBG_CONDITION_DECODE0_STEP4__GROUP_1_AND_HIGH___S 4 +#define DBG_CONDITION_DECODE0_STEP4__GROUP_0_OR_ACTIVE___M 0x00000008 +#define DBG_CONDITION_DECODE0_STEP4__GROUP_0_OR_ACTIVE___S 3 +#define DBG_CONDITION_DECODE0_STEP4__GROUP_0_OR_HIGH___M 0x00000004 +#define DBG_CONDITION_DECODE0_STEP4__GROUP_0_OR_HIGH___S 2 +#define DBG_CONDITION_DECODE0_STEP4__GROUP_0_AND_ACTIVE___M 0x00000002 +#define DBG_CONDITION_DECODE0_STEP4__GROUP_0_AND_ACTIVE___S 1 +#define DBG_CONDITION_DECODE0_STEP4__GROUP_0_AND_HIGH___M 0x00000001 +#define DBG_CONDITION_DECODE0_STEP4__GROUP_0_AND_HIGH___S 0 +#define DBG_CONDITION_DECODE0_STEP5 (0x00BC4988) +#define DBG_CONDITION_DECODE0_STEP5___RWC QCSR_REG_RW +#define DBG_CONDITION_DECODE0_STEP5__NOT___M 0x01000000 +#define DBG_CONDITION_DECODE0_STEP5__NOT___S 24 +#define DBG_CONDITION_DECODE0_STEP5__BC0_COMP_ACTIVE___M 0x00200000 +#define DBG_CONDITION_DECODE0_STEP5__BC0_COMP_ACTIVE___S 21 +#define DBG_CONDITION_DECODE0_STEP5__BC0_COMP_HIGH___M 0x00100000 +#define DBG_CONDITION_DECODE0_STEP5__BC0_COMP_HIGH___S 20 +#define DBG_CONDITION_DECODE0_STEP5__TC0_COMP_ACTIVE___M 0x00020000 +#define DBG_CONDITION_DECODE0_STEP5__TC0_COMP_ACTIVE___S 17 +#define DBG_CONDITION_DECODE0_STEP5__TC0_COMP_HIGH___M 0x00010000 +#define DBG_CONDITION_DECODE0_STEP5__TC0_COMP_HIGH___S 16 +#define DBG_CONDITION_DECODE0_STEP5__GROUP_3_OR_ACTIVE___M 0x00008000 +#define DBG_CONDITION_DECODE0_STEP5__GROUP_3_OR_ACTIVE___S 15 +#define DBG_CONDITION_DECODE0_STEP5__GROUP_3_OR_HIGH___M 0x00004000 +#define DBG_CONDITION_DECODE0_STEP5__GROUP_3_OR_HIGH___S 14 +#define DBG_CONDITION_DECODE0_STEP5__GROUP_3_AND_ACTIVE___M 0x00002000 +#define DBG_CONDITION_DECODE0_STEP5__GROUP_3_AND_ACTIVE___S 13 +#define DBG_CONDITION_DECODE0_STEP5__GROUP_3_AND_HIGH___M 0x00001000 +#define DBG_CONDITION_DECODE0_STEP5__GROUP_3_AND_HIGH___S 12 +#define DBG_CONDITION_DECODE0_STEP5__GROUP_2_OR_ACTIVE___M 0x00000800 +#define DBG_CONDITION_DECODE0_STEP5__GROUP_2_OR_ACTIVE___S 11 +#define DBG_CONDITION_DECODE0_STEP5__GROUP_2_OR_HIGH___M 0x00000400 +#define DBG_CONDITION_DECODE0_STEP5__GROUP_2_OR_HIGH___S 10 +#define DBG_CONDITION_DECODE0_STEP5__GROUP_2_AND_ACTIVE___M 0x00000200 +#define DBG_CONDITION_DECODE0_STEP5__GROUP_2_AND_ACTIVE___S 9 +#define DBG_CONDITION_DECODE0_STEP5__GROUP_2_AND_HIGH___M 0x00000100 +#define DBG_CONDITION_DECODE0_STEP5__GROUP_2_AND_HIGH___S 8 +#define DBG_CONDITION_DECODE0_STEP5__GROUP_1_OR_ACTIVE___M 0x00000080 +#define DBG_CONDITION_DECODE0_STEP5__GROUP_1_OR_ACTIVE___S 7 +#define DBG_CONDITION_DECODE0_STEP5__GROUP_1_OR_HIGH___M 0x00000040 +#define DBG_CONDITION_DECODE0_STEP5__GROUP_1_OR_HIGH___S 6 +#define DBG_CONDITION_DECODE0_STEP5__GROUP_1_AND_ACTIVE___M 0x00000020 +#define DBG_CONDITION_DECODE0_STEP5__GROUP_1_AND_ACTIVE___S 5 +#define DBG_CONDITION_DECODE0_STEP5__GROUP_1_AND_HIGH___M 0x00000010 +#define DBG_CONDITION_DECODE0_STEP5__GROUP_1_AND_HIGH___S 4 +#define DBG_CONDITION_DECODE0_STEP5__GROUP_0_OR_ACTIVE___M 0x00000008 +#define DBG_CONDITION_DECODE0_STEP5__GROUP_0_OR_ACTIVE___S 3 +#define DBG_CONDITION_DECODE0_STEP5__GROUP_0_OR_HIGH___M 0x00000004 +#define DBG_CONDITION_DECODE0_STEP5__GROUP_0_OR_HIGH___S 2 +#define DBG_CONDITION_DECODE0_STEP5__GROUP_0_AND_ACTIVE___M 0x00000002 +#define DBG_CONDITION_DECODE0_STEP5__GROUP_0_AND_ACTIVE___S 1 +#define DBG_CONDITION_DECODE0_STEP5__GROUP_0_AND_HIGH___M 0x00000001 +#define DBG_CONDITION_DECODE0_STEP5__GROUP_0_AND_HIGH___S 0 +#define DBG_CONDITION_DECODE0_STEP6 (0x00BC4B60) +#define DBG_CONDITION_DECODE0_STEP6___RWC QCSR_REG_RW +#define DBG_CONDITION_DECODE0_STEP6__NOT___M 0x01000000 +#define DBG_CONDITION_DECODE0_STEP6__NOT___S 24 +#define DBG_CONDITION_DECODE0_STEP6__BC0_COMP_ACTIVE___M 0x00200000 +#define DBG_CONDITION_DECODE0_STEP6__BC0_COMP_ACTIVE___S 21 +#define DBG_CONDITION_DECODE0_STEP6__BC0_COMP_HIGH___M 0x00100000 +#define DBG_CONDITION_DECODE0_STEP6__BC0_COMP_HIGH___S 20 +#define DBG_CONDITION_DECODE0_STEP6__TC0_COMP_ACTIVE___M 0x00020000 +#define DBG_CONDITION_DECODE0_STEP6__TC0_COMP_ACTIVE___S 17 +#define DBG_CONDITION_DECODE0_STEP6__TC0_COMP_HIGH___M 0x00010000 +#define DBG_CONDITION_DECODE0_STEP6__TC0_COMP_HIGH___S 16 +#define DBG_CONDITION_DECODE0_STEP6__GROUP_3_OR_ACTIVE___M 0x00008000 +#define DBG_CONDITION_DECODE0_STEP6__GROUP_3_OR_ACTIVE___S 15 +#define DBG_CONDITION_DECODE0_STEP6__GROUP_3_OR_HIGH___M 0x00004000 +#define DBG_CONDITION_DECODE0_STEP6__GROUP_3_OR_HIGH___S 14 +#define DBG_CONDITION_DECODE0_STEP6__GROUP_3_AND_ACTIVE___M 0x00002000 +#define DBG_CONDITION_DECODE0_STEP6__GROUP_3_AND_ACTIVE___S 13 +#define DBG_CONDITION_DECODE0_STEP6__GROUP_3_AND_HIGH___M 0x00001000 +#define DBG_CONDITION_DECODE0_STEP6__GROUP_3_AND_HIGH___S 12 +#define DBG_CONDITION_DECODE0_STEP6__GROUP_2_OR_ACTIVE___M 0x00000800 +#define DBG_CONDITION_DECODE0_STEP6__GROUP_2_OR_ACTIVE___S 11 +#define DBG_CONDITION_DECODE0_STEP6__GROUP_2_OR_HIGH___M 0x00000400 +#define DBG_CONDITION_DECODE0_STEP6__GROUP_2_OR_HIGH___S 10 +#define DBG_CONDITION_DECODE0_STEP6__GROUP_2_AND_ACTIVE___M 0x00000200 +#define DBG_CONDITION_DECODE0_STEP6__GROUP_2_AND_ACTIVE___S 9 +#define DBG_CONDITION_DECODE0_STEP6__GROUP_2_AND_HIGH___M 0x00000100 +#define DBG_CONDITION_DECODE0_STEP6__GROUP_2_AND_HIGH___S 8 +#define DBG_CONDITION_DECODE0_STEP6__GROUP_1_OR_ACTIVE___M 0x00000080 +#define DBG_CONDITION_DECODE0_STEP6__GROUP_1_OR_ACTIVE___S 7 +#define DBG_CONDITION_DECODE0_STEP6__GROUP_1_OR_HIGH___M 0x00000040 +#define DBG_CONDITION_DECODE0_STEP6__GROUP_1_OR_HIGH___S 6 +#define DBG_CONDITION_DECODE0_STEP6__GROUP_1_AND_ACTIVE___M 0x00000020 +#define DBG_CONDITION_DECODE0_STEP6__GROUP_1_AND_ACTIVE___S 5 +#define DBG_CONDITION_DECODE0_STEP6__GROUP_1_AND_HIGH___M 0x00000010 +#define DBG_CONDITION_DECODE0_STEP6__GROUP_1_AND_HIGH___S 4 +#define DBG_CONDITION_DECODE0_STEP6__GROUP_0_OR_ACTIVE___M 0x00000008 +#define DBG_CONDITION_DECODE0_STEP6__GROUP_0_OR_ACTIVE___S 3 +#define DBG_CONDITION_DECODE0_STEP6__GROUP_0_OR_HIGH___M 0x00000004 +#define DBG_CONDITION_DECODE0_STEP6__GROUP_0_OR_HIGH___S 2 +#define DBG_CONDITION_DECODE0_STEP6__GROUP_0_AND_ACTIVE___M 0x00000002 +#define DBG_CONDITION_DECODE0_STEP6__GROUP_0_AND_ACTIVE___S 1 +#define DBG_CONDITION_DECODE0_STEP6__GROUP_0_AND_HIGH___M 0x00000001 +#define DBG_CONDITION_DECODE0_STEP6__GROUP_0_AND_HIGH___S 0 +#define DBG_CONDITION_DECODE0_STEP7 (0x00BC4D38) +#define DBG_CONDITION_DECODE0_STEP7___RWC QCSR_REG_RW +#define DBG_CONDITION_DECODE0_STEP7__NOT___M 0x01000000 +#define DBG_CONDITION_DECODE0_STEP7__NOT___S 24 +#define DBG_CONDITION_DECODE0_STEP7__BC0_COMP_ACTIVE___M 0x00200000 +#define DBG_CONDITION_DECODE0_STEP7__BC0_COMP_ACTIVE___S 21 +#define DBG_CONDITION_DECODE0_STEP7__BC0_COMP_HIGH___M 0x00100000 +#define DBG_CONDITION_DECODE0_STEP7__BC0_COMP_HIGH___S 20 +#define DBG_CONDITION_DECODE0_STEP7__TC0_COMP_ACTIVE___M 0x00020000 +#define DBG_CONDITION_DECODE0_STEP7__TC0_COMP_ACTIVE___S 17 +#define DBG_CONDITION_DECODE0_STEP7__TC0_COMP_HIGH___M 0x00010000 +#define DBG_CONDITION_DECODE0_STEP7__TC0_COMP_HIGH___S 16 +#define DBG_CONDITION_DECODE0_STEP7__GROUP_3_OR_ACTIVE___M 0x00008000 +#define DBG_CONDITION_DECODE0_STEP7__GROUP_3_OR_ACTIVE___S 15 +#define DBG_CONDITION_DECODE0_STEP7__GROUP_3_OR_HIGH___M 0x00004000 +#define DBG_CONDITION_DECODE0_STEP7__GROUP_3_OR_HIGH___S 14 +#define DBG_CONDITION_DECODE0_STEP7__GROUP_3_AND_ACTIVE___M 0x00002000 +#define DBG_CONDITION_DECODE0_STEP7__GROUP_3_AND_ACTIVE___S 13 +#define DBG_CONDITION_DECODE0_STEP7__GROUP_3_AND_HIGH___M 0x00001000 +#define DBG_CONDITION_DECODE0_STEP7__GROUP_3_AND_HIGH___S 12 +#define DBG_CONDITION_DECODE0_STEP7__GROUP_2_OR_ACTIVE___M 0x00000800 +#define DBG_CONDITION_DECODE0_STEP7__GROUP_2_OR_ACTIVE___S 11 +#define DBG_CONDITION_DECODE0_STEP7__GROUP_2_OR_HIGH___M 0x00000400 +#define DBG_CONDITION_DECODE0_STEP7__GROUP_2_OR_HIGH___S 10 +#define DBG_CONDITION_DECODE0_STEP7__GROUP_2_AND_ACTIVE___M 0x00000200 +#define DBG_CONDITION_DECODE0_STEP7__GROUP_2_AND_ACTIVE___S 9 +#define DBG_CONDITION_DECODE0_STEP7__GROUP_2_AND_HIGH___M 0x00000100 +#define DBG_CONDITION_DECODE0_STEP7__GROUP_2_AND_HIGH___S 8 +#define DBG_CONDITION_DECODE0_STEP7__GROUP_1_OR_ACTIVE___M 0x00000080 +#define DBG_CONDITION_DECODE0_STEP7__GROUP_1_OR_ACTIVE___S 7 +#define DBG_CONDITION_DECODE0_STEP7__GROUP_1_OR_HIGH___M 0x00000040 +#define DBG_CONDITION_DECODE0_STEP7__GROUP_1_OR_HIGH___S 6 +#define DBG_CONDITION_DECODE0_STEP7__GROUP_1_AND_ACTIVE___M 0x00000020 +#define DBG_CONDITION_DECODE0_STEP7__GROUP_1_AND_ACTIVE___S 5 +#define DBG_CONDITION_DECODE0_STEP7__GROUP_1_AND_HIGH___M 0x00000010 +#define DBG_CONDITION_DECODE0_STEP7__GROUP_1_AND_HIGH___S 4 +#define DBG_CONDITION_DECODE0_STEP7__GROUP_0_OR_ACTIVE___M 0x00000008 +#define DBG_CONDITION_DECODE0_STEP7__GROUP_0_OR_ACTIVE___S 3 +#define DBG_CONDITION_DECODE0_STEP7__GROUP_0_OR_HIGH___M 0x00000004 +#define DBG_CONDITION_DECODE0_STEP7__GROUP_0_OR_HIGH___S 2 +#define DBG_CONDITION_DECODE0_STEP7__GROUP_0_AND_ACTIVE___M 0x00000002 +#define DBG_CONDITION_DECODE0_STEP7__GROUP_0_AND_ACTIVE___S 1 +#define DBG_CONDITION_DECODE0_STEP7__GROUP_0_AND_HIGH___M 0x00000001 +#define DBG_CONDITION_DECODE0_STEP7__GROUP_0_AND_HIGH___S 0 +#define DBG_CONDITION_DECODE1_STEP0 (0x00BC4054) +#define DBG_CONDITION_DECODE1_STEP0___RWC QCSR_REG_RW +#define DBG_CONDITION_DECODE1_STEP0__NOT___M 0x01000000 +#define DBG_CONDITION_DECODE1_STEP0__NOT___S 24 +#define DBG_CONDITION_DECODE1_STEP0__BC0_COMP_ACTIVE___M 0x00200000 +#define DBG_CONDITION_DECODE1_STEP0__BC0_COMP_ACTIVE___S 21 +#define DBG_CONDITION_DECODE1_STEP0__BC0_COMP_HIGH___M 0x00100000 +#define DBG_CONDITION_DECODE1_STEP0__BC0_COMP_HIGH___S 20 +#define DBG_CONDITION_DECODE1_STEP0__TC0_COMP_ACTIVE___M 0x00020000 +#define DBG_CONDITION_DECODE1_STEP0__TC0_COMP_ACTIVE___S 17 +#define DBG_CONDITION_DECODE1_STEP0__TC0_COMP_HIGH___M 0x00010000 +#define DBG_CONDITION_DECODE1_STEP0__TC0_COMP_HIGH___S 16 +#define DBG_CONDITION_DECODE1_STEP0__GROUP_3_OR_ACTIVE___M 0x00008000 +#define DBG_CONDITION_DECODE1_STEP0__GROUP_3_OR_ACTIVE___S 15 +#define DBG_CONDITION_DECODE1_STEP0__GROUP_3_OR_HIGH___M 0x00004000 +#define DBG_CONDITION_DECODE1_STEP0__GROUP_3_OR_HIGH___S 14 +#define DBG_CONDITION_DECODE1_STEP0__GROUP_3_AND_ACTIVE___M 0x00002000 +#define DBG_CONDITION_DECODE1_STEP0__GROUP_3_AND_ACTIVE___S 13 +#define DBG_CONDITION_DECODE1_STEP0__GROUP_3_AND_HIGH___M 0x00001000 +#define DBG_CONDITION_DECODE1_STEP0__GROUP_3_AND_HIGH___S 12 +#define DBG_CONDITION_DECODE1_STEP0__GROUP_2_OR_ACTIVE___M 0x00000800 +#define DBG_CONDITION_DECODE1_STEP0__GROUP_2_OR_ACTIVE___S 11 +#define DBG_CONDITION_DECODE1_STEP0__GROUP_2_OR_HIGH___M 0x00000400 +#define DBG_CONDITION_DECODE1_STEP0__GROUP_2_OR_HIGH___S 10 +#define DBG_CONDITION_DECODE1_STEP0__GROUP_2_AND_ACTIVE___M 0x00000200 +#define DBG_CONDITION_DECODE1_STEP0__GROUP_2_AND_ACTIVE___S 9 +#define DBG_CONDITION_DECODE1_STEP0__GROUP_2_AND_HIGH___M 0x00000100 +#define DBG_CONDITION_DECODE1_STEP0__GROUP_2_AND_HIGH___S 8 +#define DBG_CONDITION_DECODE1_STEP0__GROUP_1_OR_ACTIVE___M 0x00000080 +#define DBG_CONDITION_DECODE1_STEP0__GROUP_1_OR_ACTIVE___S 7 +#define DBG_CONDITION_DECODE1_STEP0__GROUP_1_OR_HIGH___M 0x00000040 +#define DBG_CONDITION_DECODE1_STEP0__GROUP_1_OR_HIGH___S 6 +#define DBG_CONDITION_DECODE1_STEP0__GROUP_1_AND_ACTIVE___M 0x00000020 +#define DBG_CONDITION_DECODE1_STEP0__GROUP_1_AND_ACTIVE___S 5 +#define DBG_CONDITION_DECODE1_STEP0__GROUP_1_AND_HIGH___M 0x00000010 +#define DBG_CONDITION_DECODE1_STEP0__GROUP_1_AND_HIGH___S 4 +#define DBG_CONDITION_DECODE1_STEP0__GROUP_0_OR_ACTIVE___M 0x00000008 +#define DBG_CONDITION_DECODE1_STEP0__GROUP_0_OR_ACTIVE___S 3 +#define DBG_CONDITION_DECODE1_STEP0__GROUP_0_OR_HIGH___M 0x00000004 +#define DBG_CONDITION_DECODE1_STEP0__GROUP_0_OR_HIGH___S 2 +#define DBG_CONDITION_DECODE1_STEP0__GROUP_0_AND_ACTIVE___M 0x00000002 +#define DBG_CONDITION_DECODE1_STEP0__GROUP_0_AND_ACTIVE___S 1 +#define DBG_CONDITION_DECODE1_STEP0__GROUP_0_AND_HIGH___M 0x00000001 +#define DBG_CONDITION_DECODE1_STEP0__GROUP_0_AND_HIGH___S 0 +#define DBG_CONDITION_DECODE1_STEP1 (0x00BC422C) +#define DBG_CONDITION_DECODE1_STEP1___RWC QCSR_REG_RW +#define DBG_CONDITION_DECODE1_STEP1__NOT___M 0x01000000 +#define DBG_CONDITION_DECODE1_STEP1__NOT___S 24 +#define DBG_CONDITION_DECODE1_STEP1__BC0_COMP_ACTIVE___M 0x00200000 +#define DBG_CONDITION_DECODE1_STEP1__BC0_COMP_ACTIVE___S 21 +#define DBG_CONDITION_DECODE1_STEP1__BC0_COMP_HIGH___M 0x00100000 +#define DBG_CONDITION_DECODE1_STEP1__BC0_COMP_HIGH___S 20 +#define DBG_CONDITION_DECODE1_STEP1__TC0_COMP_ACTIVE___M 0x00020000 +#define DBG_CONDITION_DECODE1_STEP1__TC0_COMP_ACTIVE___S 17 +#define DBG_CONDITION_DECODE1_STEP1__TC0_COMP_HIGH___M 0x00010000 +#define DBG_CONDITION_DECODE1_STEP1__TC0_COMP_HIGH___S 16 +#define DBG_CONDITION_DECODE1_STEP1__GROUP_3_OR_ACTIVE___M 0x00008000 +#define DBG_CONDITION_DECODE1_STEP1__GROUP_3_OR_ACTIVE___S 15 +#define DBG_CONDITION_DECODE1_STEP1__GROUP_3_OR_HIGH___M 0x00004000 +#define DBG_CONDITION_DECODE1_STEP1__GROUP_3_OR_HIGH___S 14 +#define DBG_CONDITION_DECODE1_STEP1__GROUP_3_AND_ACTIVE___M 0x00002000 +#define DBG_CONDITION_DECODE1_STEP1__GROUP_3_AND_ACTIVE___S 13 +#define DBG_CONDITION_DECODE1_STEP1__GROUP_3_AND_HIGH___M 0x00001000 +#define DBG_CONDITION_DECODE1_STEP1__GROUP_3_AND_HIGH___S 12 +#define DBG_CONDITION_DECODE1_STEP1__GROUP_2_OR_ACTIVE___M 0x00000800 +#define DBG_CONDITION_DECODE1_STEP1__GROUP_2_OR_ACTIVE___S 11 +#define DBG_CONDITION_DECODE1_STEP1__GROUP_2_OR_HIGH___M 0x00000400 +#define DBG_CONDITION_DECODE1_STEP1__GROUP_2_OR_HIGH___S 10 +#define DBG_CONDITION_DECODE1_STEP1__GROUP_2_AND_ACTIVE___M 0x00000200 +#define DBG_CONDITION_DECODE1_STEP1__GROUP_2_AND_ACTIVE___S 9 +#define DBG_CONDITION_DECODE1_STEP1__GROUP_2_AND_HIGH___M 0x00000100 +#define DBG_CONDITION_DECODE1_STEP1__GROUP_2_AND_HIGH___S 8 +#define DBG_CONDITION_DECODE1_STEP1__GROUP_1_OR_ACTIVE___M 0x00000080 +#define DBG_CONDITION_DECODE1_STEP1__GROUP_1_OR_ACTIVE___S 7 +#define DBG_CONDITION_DECODE1_STEP1__GROUP_1_OR_HIGH___M 0x00000040 +#define DBG_CONDITION_DECODE1_STEP1__GROUP_1_OR_HIGH___S 6 +#define DBG_CONDITION_DECODE1_STEP1__GROUP_1_AND_ACTIVE___M 0x00000020 +#define DBG_CONDITION_DECODE1_STEP1__GROUP_1_AND_ACTIVE___S 5 +#define DBG_CONDITION_DECODE1_STEP1__GROUP_1_AND_HIGH___M 0x00000010 +#define DBG_CONDITION_DECODE1_STEP1__GROUP_1_AND_HIGH___S 4 +#define DBG_CONDITION_DECODE1_STEP1__GROUP_0_OR_ACTIVE___M 0x00000008 +#define DBG_CONDITION_DECODE1_STEP1__GROUP_0_OR_ACTIVE___S 3 +#define DBG_CONDITION_DECODE1_STEP1__GROUP_0_OR_HIGH___M 0x00000004 +#define DBG_CONDITION_DECODE1_STEP1__GROUP_0_OR_HIGH___S 2 +#define DBG_CONDITION_DECODE1_STEP1__GROUP_0_AND_ACTIVE___M 0x00000002 +#define DBG_CONDITION_DECODE1_STEP1__GROUP_0_AND_ACTIVE___S 1 +#define DBG_CONDITION_DECODE1_STEP1__GROUP_0_AND_HIGH___M 0x00000001 +#define DBG_CONDITION_DECODE1_STEP1__GROUP_0_AND_HIGH___S 0 +#define DBG_CONDITION_DECODE1_STEP2 (0x00BC4404) +#define DBG_CONDITION_DECODE1_STEP2___RWC QCSR_REG_RW +#define DBG_CONDITION_DECODE1_STEP2__NOT___M 0x01000000 +#define DBG_CONDITION_DECODE1_STEP2__NOT___S 24 +#define DBG_CONDITION_DECODE1_STEP2__BC0_COMP_ACTIVE___M 0x00200000 +#define DBG_CONDITION_DECODE1_STEP2__BC0_COMP_ACTIVE___S 21 +#define DBG_CONDITION_DECODE1_STEP2__BC0_COMP_HIGH___M 0x00100000 +#define DBG_CONDITION_DECODE1_STEP2__BC0_COMP_HIGH___S 20 +#define DBG_CONDITION_DECODE1_STEP2__TC0_COMP_ACTIVE___M 0x00020000 +#define DBG_CONDITION_DECODE1_STEP2__TC0_COMP_ACTIVE___S 17 +#define DBG_CONDITION_DECODE1_STEP2__TC0_COMP_HIGH___M 0x00010000 +#define DBG_CONDITION_DECODE1_STEP2__TC0_COMP_HIGH___S 16 +#define DBG_CONDITION_DECODE1_STEP2__GROUP_3_OR_ACTIVE___M 0x00008000 +#define DBG_CONDITION_DECODE1_STEP2__GROUP_3_OR_ACTIVE___S 15 +#define DBG_CONDITION_DECODE1_STEP2__GROUP_3_OR_HIGH___M 0x00004000 +#define DBG_CONDITION_DECODE1_STEP2__GROUP_3_OR_HIGH___S 14 +#define DBG_CONDITION_DECODE1_STEP2__GROUP_3_AND_ACTIVE___M 0x00002000 +#define DBG_CONDITION_DECODE1_STEP2__GROUP_3_AND_ACTIVE___S 13 +#define DBG_CONDITION_DECODE1_STEP2__GROUP_3_AND_HIGH___M 0x00001000 +#define DBG_CONDITION_DECODE1_STEP2__GROUP_3_AND_HIGH___S 12 +#define DBG_CONDITION_DECODE1_STEP2__GROUP_2_OR_ACTIVE___M 0x00000800 +#define DBG_CONDITION_DECODE1_STEP2__GROUP_2_OR_ACTIVE___S 11 +#define DBG_CONDITION_DECODE1_STEP2__GROUP_2_OR_HIGH___M 0x00000400 +#define DBG_CONDITION_DECODE1_STEP2__GROUP_2_OR_HIGH___S 10 +#define DBG_CONDITION_DECODE1_STEP2__GROUP_2_AND_ACTIVE___M 0x00000200 +#define DBG_CONDITION_DECODE1_STEP2__GROUP_2_AND_ACTIVE___S 9 +#define DBG_CONDITION_DECODE1_STEP2__GROUP_2_AND_HIGH___M 0x00000100 +#define DBG_CONDITION_DECODE1_STEP2__GROUP_2_AND_HIGH___S 8 +#define DBG_CONDITION_DECODE1_STEP2__GROUP_1_OR_ACTIVE___M 0x00000080 +#define DBG_CONDITION_DECODE1_STEP2__GROUP_1_OR_ACTIVE___S 7 +#define DBG_CONDITION_DECODE1_STEP2__GROUP_1_OR_HIGH___M 0x00000040 +#define DBG_CONDITION_DECODE1_STEP2__GROUP_1_OR_HIGH___S 6 +#define DBG_CONDITION_DECODE1_STEP2__GROUP_1_AND_ACTIVE___M 0x00000020 +#define DBG_CONDITION_DECODE1_STEP2__GROUP_1_AND_ACTIVE___S 5 +#define DBG_CONDITION_DECODE1_STEP2__GROUP_1_AND_HIGH___M 0x00000010 +#define DBG_CONDITION_DECODE1_STEP2__GROUP_1_AND_HIGH___S 4 +#define DBG_CONDITION_DECODE1_STEP2__GROUP_0_OR_ACTIVE___M 0x00000008 +#define DBG_CONDITION_DECODE1_STEP2__GROUP_0_OR_ACTIVE___S 3 +#define DBG_CONDITION_DECODE1_STEP2__GROUP_0_OR_HIGH___M 0x00000004 +#define DBG_CONDITION_DECODE1_STEP2__GROUP_0_OR_HIGH___S 2 +#define DBG_CONDITION_DECODE1_STEP2__GROUP_0_AND_ACTIVE___M 0x00000002 +#define DBG_CONDITION_DECODE1_STEP2__GROUP_0_AND_ACTIVE___S 1 +#define DBG_CONDITION_DECODE1_STEP2__GROUP_0_AND_HIGH___M 0x00000001 +#define DBG_CONDITION_DECODE1_STEP2__GROUP_0_AND_HIGH___S 0 +#define DBG_CONDITION_DECODE1_STEP3 (0x00BC45DC) +#define DBG_CONDITION_DECODE1_STEP3___RWC QCSR_REG_RW +#define DBG_CONDITION_DECODE1_STEP3__NOT___M 0x01000000 +#define DBG_CONDITION_DECODE1_STEP3__NOT___S 24 +#define DBG_CONDITION_DECODE1_STEP3__BC0_COMP_ACTIVE___M 0x00200000 +#define DBG_CONDITION_DECODE1_STEP3__BC0_COMP_ACTIVE___S 21 +#define DBG_CONDITION_DECODE1_STEP3__BC0_COMP_HIGH___M 0x00100000 +#define DBG_CONDITION_DECODE1_STEP3__BC0_COMP_HIGH___S 20 +#define DBG_CONDITION_DECODE1_STEP3__TC0_COMP_ACTIVE___M 0x00020000 +#define DBG_CONDITION_DECODE1_STEP3__TC0_COMP_ACTIVE___S 17 +#define DBG_CONDITION_DECODE1_STEP3__TC0_COMP_HIGH___M 0x00010000 +#define DBG_CONDITION_DECODE1_STEP3__TC0_COMP_HIGH___S 16 +#define DBG_CONDITION_DECODE1_STEP3__GROUP_3_OR_ACTIVE___M 0x00008000 +#define DBG_CONDITION_DECODE1_STEP3__GROUP_3_OR_ACTIVE___S 15 +#define DBG_CONDITION_DECODE1_STEP3__GROUP_3_OR_HIGH___M 0x00004000 +#define DBG_CONDITION_DECODE1_STEP3__GROUP_3_OR_HIGH___S 14 +#define DBG_CONDITION_DECODE1_STEP3__GROUP_3_AND_ACTIVE___M 0x00002000 +#define DBG_CONDITION_DECODE1_STEP3__GROUP_3_AND_ACTIVE___S 13 +#define DBG_CONDITION_DECODE1_STEP3__GROUP_3_AND_HIGH___M 0x00001000 +#define DBG_CONDITION_DECODE1_STEP3__GROUP_3_AND_HIGH___S 12 +#define DBG_CONDITION_DECODE1_STEP3__GROUP_2_OR_ACTIVE___M 0x00000800 +#define DBG_CONDITION_DECODE1_STEP3__GROUP_2_OR_ACTIVE___S 11 +#define DBG_CONDITION_DECODE1_STEP3__GROUP_2_OR_HIGH___M 0x00000400 +#define DBG_CONDITION_DECODE1_STEP3__GROUP_2_OR_HIGH___S 10 +#define DBG_CONDITION_DECODE1_STEP3__GROUP_2_AND_ACTIVE___M 0x00000200 +#define DBG_CONDITION_DECODE1_STEP3__GROUP_2_AND_ACTIVE___S 9 +#define DBG_CONDITION_DECODE1_STEP3__GROUP_2_AND_HIGH___M 0x00000100 +#define DBG_CONDITION_DECODE1_STEP3__GROUP_2_AND_HIGH___S 8 +#define DBG_CONDITION_DECODE1_STEP3__GROUP_1_OR_ACTIVE___M 0x00000080 +#define DBG_CONDITION_DECODE1_STEP3__GROUP_1_OR_ACTIVE___S 7 +#define DBG_CONDITION_DECODE1_STEP3__GROUP_1_OR_HIGH___M 0x00000040 +#define DBG_CONDITION_DECODE1_STEP3__GROUP_1_OR_HIGH___S 6 +#define DBG_CONDITION_DECODE1_STEP3__GROUP_1_AND_ACTIVE___M 0x00000020 +#define DBG_CONDITION_DECODE1_STEP3__GROUP_1_AND_ACTIVE___S 5 +#define DBG_CONDITION_DECODE1_STEP3__GROUP_1_AND_HIGH___M 0x00000010 +#define DBG_CONDITION_DECODE1_STEP3__GROUP_1_AND_HIGH___S 4 +#define DBG_CONDITION_DECODE1_STEP3__GROUP_0_OR_ACTIVE___M 0x00000008 +#define DBG_CONDITION_DECODE1_STEP3__GROUP_0_OR_ACTIVE___S 3 +#define DBG_CONDITION_DECODE1_STEP3__GROUP_0_OR_HIGH___M 0x00000004 +#define DBG_CONDITION_DECODE1_STEP3__GROUP_0_OR_HIGH___S 2 +#define DBG_CONDITION_DECODE1_STEP3__GROUP_0_AND_ACTIVE___M 0x00000002 +#define DBG_CONDITION_DECODE1_STEP3__GROUP_0_AND_ACTIVE___S 1 +#define DBG_CONDITION_DECODE1_STEP3__GROUP_0_AND_HIGH___M 0x00000001 +#define DBG_CONDITION_DECODE1_STEP3__GROUP_0_AND_HIGH___S 0 +#define DBG_CONDITION_DECODE1_STEP4 (0x00BC47B4) +#define DBG_CONDITION_DECODE1_STEP4___RWC QCSR_REG_RW +#define DBG_CONDITION_DECODE1_STEP4__NOT___M 0x01000000 +#define DBG_CONDITION_DECODE1_STEP4__NOT___S 24 +#define DBG_CONDITION_DECODE1_STEP4__BC0_COMP_ACTIVE___M 0x00200000 +#define DBG_CONDITION_DECODE1_STEP4__BC0_COMP_ACTIVE___S 21 +#define DBG_CONDITION_DECODE1_STEP4__BC0_COMP_HIGH___M 0x00100000 +#define DBG_CONDITION_DECODE1_STEP4__BC0_COMP_HIGH___S 20 +#define DBG_CONDITION_DECODE1_STEP4__TC0_COMP_ACTIVE___M 0x00020000 +#define DBG_CONDITION_DECODE1_STEP4__TC0_COMP_ACTIVE___S 17 +#define DBG_CONDITION_DECODE1_STEP4__TC0_COMP_HIGH___M 0x00010000 +#define DBG_CONDITION_DECODE1_STEP4__TC0_COMP_HIGH___S 16 +#define DBG_CONDITION_DECODE1_STEP4__GROUP_3_OR_ACTIVE___M 0x00008000 +#define DBG_CONDITION_DECODE1_STEP4__GROUP_3_OR_ACTIVE___S 15 +#define DBG_CONDITION_DECODE1_STEP4__GROUP_3_OR_HIGH___M 0x00004000 +#define DBG_CONDITION_DECODE1_STEP4__GROUP_3_OR_HIGH___S 14 +#define DBG_CONDITION_DECODE1_STEP4__GROUP_3_AND_ACTIVE___M 0x00002000 +#define DBG_CONDITION_DECODE1_STEP4__GROUP_3_AND_ACTIVE___S 13 +#define DBG_CONDITION_DECODE1_STEP4__GROUP_3_AND_HIGH___M 0x00001000 +#define DBG_CONDITION_DECODE1_STEP4__GROUP_3_AND_HIGH___S 12 +#define DBG_CONDITION_DECODE1_STEP4__GROUP_2_OR_ACTIVE___M 0x00000800 +#define DBG_CONDITION_DECODE1_STEP4__GROUP_2_OR_ACTIVE___S 11 +#define DBG_CONDITION_DECODE1_STEP4__GROUP_2_OR_HIGH___M 0x00000400 +#define DBG_CONDITION_DECODE1_STEP4__GROUP_2_OR_HIGH___S 10 +#define DBG_CONDITION_DECODE1_STEP4__GROUP_2_AND_ACTIVE___M 0x00000200 +#define DBG_CONDITION_DECODE1_STEP4__GROUP_2_AND_ACTIVE___S 9 +#define DBG_CONDITION_DECODE1_STEP4__GROUP_2_AND_HIGH___M 0x00000100 +#define DBG_CONDITION_DECODE1_STEP4__GROUP_2_AND_HIGH___S 8 +#define DBG_CONDITION_DECODE1_STEP4__GROUP_1_OR_ACTIVE___M 0x00000080 +#define DBG_CONDITION_DECODE1_STEP4__GROUP_1_OR_ACTIVE___S 7 +#define DBG_CONDITION_DECODE1_STEP4__GROUP_1_OR_HIGH___M 0x00000040 +#define DBG_CONDITION_DECODE1_STEP4__GROUP_1_OR_HIGH___S 6 +#define DBG_CONDITION_DECODE1_STEP4__GROUP_1_AND_ACTIVE___M 0x00000020 +#define DBG_CONDITION_DECODE1_STEP4__GROUP_1_AND_ACTIVE___S 5 +#define DBG_CONDITION_DECODE1_STEP4__GROUP_1_AND_HIGH___M 0x00000010 +#define DBG_CONDITION_DECODE1_STEP4__GROUP_1_AND_HIGH___S 4 +#define DBG_CONDITION_DECODE1_STEP4__GROUP_0_OR_ACTIVE___M 0x00000008 +#define DBG_CONDITION_DECODE1_STEP4__GROUP_0_OR_ACTIVE___S 3 +#define DBG_CONDITION_DECODE1_STEP4__GROUP_0_OR_HIGH___M 0x00000004 +#define DBG_CONDITION_DECODE1_STEP4__GROUP_0_OR_HIGH___S 2 +#define DBG_CONDITION_DECODE1_STEP4__GROUP_0_AND_ACTIVE___M 0x00000002 +#define DBG_CONDITION_DECODE1_STEP4__GROUP_0_AND_ACTIVE___S 1 +#define DBG_CONDITION_DECODE1_STEP4__GROUP_0_AND_HIGH___M 0x00000001 +#define DBG_CONDITION_DECODE1_STEP4__GROUP_0_AND_HIGH___S 0 +#define DBG_CONDITION_DECODE1_STEP5 (0x00BC498C) +#define DBG_CONDITION_DECODE1_STEP5___RWC QCSR_REG_RW +#define DBG_CONDITION_DECODE1_STEP5__NOT___M 0x01000000 +#define DBG_CONDITION_DECODE1_STEP5__NOT___S 24 +#define DBG_CONDITION_DECODE1_STEP5__BC0_COMP_ACTIVE___M 0x00200000 +#define DBG_CONDITION_DECODE1_STEP5__BC0_COMP_ACTIVE___S 21 +#define DBG_CONDITION_DECODE1_STEP5__BC0_COMP_HIGH___M 0x00100000 +#define DBG_CONDITION_DECODE1_STEP5__BC0_COMP_HIGH___S 20 +#define DBG_CONDITION_DECODE1_STEP5__TC0_COMP_ACTIVE___M 0x00020000 +#define DBG_CONDITION_DECODE1_STEP5__TC0_COMP_ACTIVE___S 17 +#define DBG_CONDITION_DECODE1_STEP5__TC0_COMP_HIGH___M 0x00010000 +#define DBG_CONDITION_DECODE1_STEP5__TC0_COMP_HIGH___S 16 +#define DBG_CONDITION_DECODE1_STEP5__GROUP_3_OR_ACTIVE___M 0x00008000 +#define DBG_CONDITION_DECODE1_STEP5__GROUP_3_OR_ACTIVE___S 15 +#define DBG_CONDITION_DECODE1_STEP5__GROUP_3_OR_HIGH___M 0x00004000 +#define DBG_CONDITION_DECODE1_STEP5__GROUP_3_OR_HIGH___S 14 +#define DBG_CONDITION_DECODE1_STEP5__GROUP_3_AND_ACTIVE___M 0x00002000 +#define DBG_CONDITION_DECODE1_STEP5__GROUP_3_AND_ACTIVE___S 13 +#define DBG_CONDITION_DECODE1_STEP5__GROUP_3_AND_HIGH___M 0x00001000 +#define DBG_CONDITION_DECODE1_STEP5__GROUP_3_AND_HIGH___S 12 +#define DBG_CONDITION_DECODE1_STEP5__GROUP_2_OR_ACTIVE___M 0x00000800 +#define DBG_CONDITION_DECODE1_STEP5__GROUP_2_OR_ACTIVE___S 11 +#define DBG_CONDITION_DECODE1_STEP5__GROUP_2_OR_HIGH___M 0x00000400 +#define DBG_CONDITION_DECODE1_STEP5__GROUP_2_OR_HIGH___S 10 +#define DBG_CONDITION_DECODE1_STEP5__GROUP_2_AND_ACTIVE___M 0x00000200 +#define DBG_CONDITION_DECODE1_STEP5__GROUP_2_AND_ACTIVE___S 9 +#define DBG_CONDITION_DECODE1_STEP5__GROUP_2_AND_HIGH___M 0x00000100 +#define DBG_CONDITION_DECODE1_STEP5__GROUP_2_AND_HIGH___S 8 +#define DBG_CONDITION_DECODE1_STEP5__GROUP_1_OR_ACTIVE___M 0x00000080 +#define DBG_CONDITION_DECODE1_STEP5__GROUP_1_OR_ACTIVE___S 7 +#define DBG_CONDITION_DECODE1_STEP5__GROUP_1_OR_HIGH___M 0x00000040 +#define DBG_CONDITION_DECODE1_STEP5__GROUP_1_OR_HIGH___S 6 +#define DBG_CONDITION_DECODE1_STEP5__GROUP_1_AND_ACTIVE___M 0x00000020 +#define DBG_CONDITION_DECODE1_STEP5__GROUP_1_AND_ACTIVE___S 5 +#define DBG_CONDITION_DECODE1_STEP5__GROUP_1_AND_HIGH___M 0x00000010 +#define DBG_CONDITION_DECODE1_STEP5__GROUP_1_AND_HIGH___S 4 +#define DBG_CONDITION_DECODE1_STEP5__GROUP_0_OR_ACTIVE___M 0x00000008 +#define DBG_CONDITION_DECODE1_STEP5__GROUP_0_OR_ACTIVE___S 3 +#define DBG_CONDITION_DECODE1_STEP5__GROUP_0_OR_HIGH___M 0x00000004 +#define DBG_CONDITION_DECODE1_STEP5__GROUP_0_OR_HIGH___S 2 +#define DBG_CONDITION_DECODE1_STEP5__GROUP_0_AND_ACTIVE___M 0x00000002 +#define DBG_CONDITION_DECODE1_STEP5__GROUP_0_AND_ACTIVE___S 1 +#define DBG_CONDITION_DECODE1_STEP5__GROUP_0_AND_HIGH___M 0x00000001 +#define DBG_CONDITION_DECODE1_STEP5__GROUP_0_AND_HIGH___S 0 +#define DBG_CONDITION_DECODE1_STEP6 (0x00BC4B64) +#define DBG_CONDITION_DECODE1_STEP6___RWC QCSR_REG_RW +#define DBG_CONDITION_DECODE1_STEP6__NOT___M 0x01000000 +#define DBG_CONDITION_DECODE1_STEP6__NOT___S 24 +#define DBG_CONDITION_DECODE1_STEP6__BC0_COMP_ACTIVE___M 0x00200000 +#define DBG_CONDITION_DECODE1_STEP6__BC0_COMP_ACTIVE___S 21 +#define DBG_CONDITION_DECODE1_STEP6__BC0_COMP_HIGH___M 0x00100000 +#define DBG_CONDITION_DECODE1_STEP6__BC0_COMP_HIGH___S 20 +#define DBG_CONDITION_DECODE1_STEP6__TC0_COMP_ACTIVE___M 0x00020000 +#define DBG_CONDITION_DECODE1_STEP6__TC0_COMP_ACTIVE___S 17 +#define DBG_CONDITION_DECODE1_STEP6__TC0_COMP_HIGH___M 0x00010000 +#define DBG_CONDITION_DECODE1_STEP6__TC0_COMP_HIGH___S 16 +#define DBG_CONDITION_DECODE1_STEP6__GROUP_3_OR_ACTIVE___M 0x00008000 +#define DBG_CONDITION_DECODE1_STEP6__GROUP_3_OR_ACTIVE___S 15 +#define DBG_CONDITION_DECODE1_STEP6__GROUP_3_OR_HIGH___M 0x00004000 +#define DBG_CONDITION_DECODE1_STEP6__GROUP_3_OR_HIGH___S 14 +#define DBG_CONDITION_DECODE1_STEP6__GROUP_3_AND_ACTIVE___M 0x00002000 +#define DBG_CONDITION_DECODE1_STEP6__GROUP_3_AND_ACTIVE___S 13 +#define DBG_CONDITION_DECODE1_STEP6__GROUP_3_AND_HIGH___M 0x00001000 +#define DBG_CONDITION_DECODE1_STEP6__GROUP_3_AND_HIGH___S 12 +#define DBG_CONDITION_DECODE1_STEP6__GROUP_2_OR_ACTIVE___M 0x00000800 +#define DBG_CONDITION_DECODE1_STEP6__GROUP_2_OR_ACTIVE___S 11 +#define DBG_CONDITION_DECODE1_STEP6__GROUP_2_OR_HIGH___M 0x00000400 +#define DBG_CONDITION_DECODE1_STEP6__GROUP_2_OR_HIGH___S 10 +#define DBG_CONDITION_DECODE1_STEP6__GROUP_2_AND_ACTIVE___M 0x00000200 +#define DBG_CONDITION_DECODE1_STEP6__GROUP_2_AND_ACTIVE___S 9 +#define DBG_CONDITION_DECODE1_STEP6__GROUP_2_AND_HIGH___M 0x00000100 +#define DBG_CONDITION_DECODE1_STEP6__GROUP_2_AND_HIGH___S 8 +#define DBG_CONDITION_DECODE1_STEP6__GROUP_1_OR_ACTIVE___M 0x00000080 +#define DBG_CONDITION_DECODE1_STEP6__GROUP_1_OR_ACTIVE___S 7 +#define DBG_CONDITION_DECODE1_STEP6__GROUP_1_OR_HIGH___M 0x00000040 +#define DBG_CONDITION_DECODE1_STEP6__GROUP_1_OR_HIGH___S 6 +#define DBG_CONDITION_DECODE1_STEP6__GROUP_1_AND_ACTIVE___M 0x00000020 +#define DBG_CONDITION_DECODE1_STEP6__GROUP_1_AND_ACTIVE___S 5 +#define DBG_CONDITION_DECODE1_STEP6__GROUP_1_AND_HIGH___M 0x00000010 +#define DBG_CONDITION_DECODE1_STEP6__GROUP_1_AND_HIGH___S 4 +#define DBG_CONDITION_DECODE1_STEP6__GROUP_0_OR_ACTIVE___M 0x00000008 +#define DBG_CONDITION_DECODE1_STEP6__GROUP_0_OR_ACTIVE___S 3 +#define DBG_CONDITION_DECODE1_STEP6__GROUP_0_OR_HIGH___M 0x00000004 +#define DBG_CONDITION_DECODE1_STEP6__GROUP_0_OR_HIGH___S 2 +#define DBG_CONDITION_DECODE1_STEP6__GROUP_0_AND_ACTIVE___M 0x00000002 +#define DBG_CONDITION_DECODE1_STEP6__GROUP_0_AND_ACTIVE___S 1 +#define DBG_CONDITION_DECODE1_STEP6__GROUP_0_AND_HIGH___M 0x00000001 +#define DBG_CONDITION_DECODE1_STEP6__GROUP_0_AND_HIGH___S 0 +#define DBG_CONDITION_DECODE1_STEP7 (0x00BC4D3C) +#define DBG_CONDITION_DECODE1_STEP7___RWC QCSR_REG_RW +#define DBG_CONDITION_DECODE1_STEP7__NOT___M 0x01000000 +#define DBG_CONDITION_DECODE1_STEP7__NOT___S 24 +#define DBG_CONDITION_DECODE1_STEP7__BC0_COMP_ACTIVE___M 0x00200000 +#define DBG_CONDITION_DECODE1_STEP7__BC0_COMP_ACTIVE___S 21 +#define DBG_CONDITION_DECODE1_STEP7__BC0_COMP_HIGH___M 0x00100000 +#define DBG_CONDITION_DECODE1_STEP7__BC0_COMP_HIGH___S 20 +#define DBG_CONDITION_DECODE1_STEP7__TC0_COMP_ACTIVE___M 0x00020000 +#define DBG_CONDITION_DECODE1_STEP7__TC0_COMP_ACTIVE___S 17 +#define DBG_CONDITION_DECODE1_STEP7__TC0_COMP_HIGH___M 0x00010000 +#define DBG_CONDITION_DECODE1_STEP7__TC0_COMP_HIGH___S 16 +#define DBG_CONDITION_DECODE1_STEP7__GROUP_3_OR_ACTIVE___M 0x00008000 +#define DBG_CONDITION_DECODE1_STEP7__GROUP_3_OR_ACTIVE___S 15 +#define DBG_CONDITION_DECODE1_STEP7__GROUP_3_OR_HIGH___M 0x00004000 +#define DBG_CONDITION_DECODE1_STEP7__GROUP_3_OR_HIGH___S 14 +#define DBG_CONDITION_DECODE1_STEP7__GROUP_3_AND_ACTIVE___M 0x00002000 +#define DBG_CONDITION_DECODE1_STEP7__GROUP_3_AND_ACTIVE___S 13 +#define DBG_CONDITION_DECODE1_STEP7__GROUP_3_AND_HIGH___M 0x00001000 +#define DBG_CONDITION_DECODE1_STEP7__GROUP_3_AND_HIGH___S 12 +#define DBG_CONDITION_DECODE1_STEP7__GROUP_2_OR_ACTIVE___M 0x00000800 +#define DBG_CONDITION_DECODE1_STEP7__GROUP_2_OR_ACTIVE___S 11 +#define DBG_CONDITION_DECODE1_STEP7__GROUP_2_OR_HIGH___M 0x00000400 +#define DBG_CONDITION_DECODE1_STEP7__GROUP_2_OR_HIGH___S 10 +#define DBG_CONDITION_DECODE1_STEP7__GROUP_2_AND_ACTIVE___M 0x00000200 +#define DBG_CONDITION_DECODE1_STEP7__GROUP_2_AND_ACTIVE___S 9 +#define DBG_CONDITION_DECODE1_STEP7__GROUP_2_AND_HIGH___M 0x00000100 +#define DBG_CONDITION_DECODE1_STEP7__GROUP_2_AND_HIGH___S 8 +#define DBG_CONDITION_DECODE1_STEP7__GROUP_1_OR_ACTIVE___M 0x00000080 +#define DBG_CONDITION_DECODE1_STEP7__GROUP_1_OR_ACTIVE___S 7 +#define DBG_CONDITION_DECODE1_STEP7__GROUP_1_OR_HIGH___M 0x00000040 +#define DBG_CONDITION_DECODE1_STEP7__GROUP_1_OR_HIGH___S 6 +#define DBG_CONDITION_DECODE1_STEP7__GROUP_1_AND_ACTIVE___M 0x00000020 +#define DBG_CONDITION_DECODE1_STEP7__GROUP_1_AND_ACTIVE___S 5 +#define DBG_CONDITION_DECODE1_STEP7__GROUP_1_AND_HIGH___M 0x00000010 +#define DBG_CONDITION_DECODE1_STEP7__GROUP_1_AND_HIGH___S 4 +#define DBG_CONDITION_DECODE1_STEP7__GROUP_0_OR_ACTIVE___M 0x00000008 +#define DBG_CONDITION_DECODE1_STEP7__GROUP_0_OR_ACTIVE___S 3 +#define DBG_CONDITION_DECODE1_STEP7__GROUP_0_OR_HIGH___M 0x00000004 +#define DBG_CONDITION_DECODE1_STEP7__GROUP_0_OR_HIGH___S 2 +#define DBG_CONDITION_DECODE1_STEP7__GROUP_0_AND_ACTIVE___M 0x00000002 +#define DBG_CONDITION_DECODE1_STEP7__GROUP_0_AND_ACTIVE___S 1 +#define DBG_CONDITION_DECODE1_STEP7__GROUP_0_AND_HIGH___M 0x00000001 +#define DBG_CONDITION_DECODE1_STEP7__GROUP_0_AND_HIGH___S 0 +#define DBG_CONDITION_DECODE2_STEP0 (0x00BC4058) +#define DBG_CONDITION_DECODE2_STEP0___RWC QCSR_REG_RW +#define DBG_CONDITION_DECODE2_STEP0__NOT___M 0x01000000 +#define DBG_CONDITION_DECODE2_STEP0__NOT___S 24 +#define DBG_CONDITION_DECODE2_STEP0__BC0_COMP_ACTIVE___M 0x00200000 +#define DBG_CONDITION_DECODE2_STEP0__BC0_COMP_ACTIVE___S 21 +#define DBG_CONDITION_DECODE2_STEP0__BC0_COMP_HIGH___M 0x00100000 +#define DBG_CONDITION_DECODE2_STEP0__BC0_COMP_HIGH___S 20 +#define DBG_CONDITION_DECODE2_STEP0__TC0_COMP_ACTIVE___M 0x00020000 +#define DBG_CONDITION_DECODE2_STEP0__TC0_COMP_ACTIVE___S 17 +#define DBG_CONDITION_DECODE2_STEP0__TC0_COMP_HIGH___M 0x00010000 +#define DBG_CONDITION_DECODE2_STEP0__TC0_COMP_HIGH___S 16 +#define DBG_CONDITION_DECODE2_STEP0__GROUP_3_OR_ACTIVE___M 0x00008000 +#define DBG_CONDITION_DECODE2_STEP0__GROUP_3_OR_ACTIVE___S 15 +#define DBG_CONDITION_DECODE2_STEP0__GROUP_3_OR_HIGH___M 0x00004000 +#define DBG_CONDITION_DECODE2_STEP0__GROUP_3_OR_HIGH___S 14 +#define DBG_CONDITION_DECODE2_STEP0__GROUP_3_AND_ACTIVE___M 0x00002000 +#define DBG_CONDITION_DECODE2_STEP0__GROUP_3_AND_ACTIVE___S 13 +#define DBG_CONDITION_DECODE2_STEP0__GROUP_3_AND_HIGH___M 0x00001000 +#define DBG_CONDITION_DECODE2_STEP0__GROUP_3_AND_HIGH___S 12 +#define DBG_CONDITION_DECODE2_STEP0__GROUP_2_OR_ACTIVE___M 0x00000800 +#define DBG_CONDITION_DECODE2_STEP0__GROUP_2_OR_ACTIVE___S 11 +#define DBG_CONDITION_DECODE2_STEP0__GROUP_2_OR_HIGH___M 0x00000400 +#define DBG_CONDITION_DECODE2_STEP0__GROUP_2_OR_HIGH___S 10 +#define DBG_CONDITION_DECODE2_STEP0__GROUP_2_AND_ACTIVE___M 0x00000200 +#define DBG_CONDITION_DECODE2_STEP0__GROUP_2_AND_ACTIVE___S 9 +#define DBG_CONDITION_DECODE2_STEP0__GROUP_2_AND_HIGH___M 0x00000100 +#define DBG_CONDITION_DECODE2_STEP0__GROUP_2_AND_HIGH___S 8 +#define DBG_CONDITION_DECODE2_STEP0__GROUP_1_OR_ACTIVE___M 0x00000080 +#define DBG_CONDITION_DECODE2_STEP0__GROUP_1_OR_ACTIVE___S 7 +#define DBG_CONDITION_DECODE2_STEP0__GROUP_1_OR_HIGH___M 0x00000040 +#define DBG_CONDITION_DECODE2_STEP0__GROUP_1_OR_HIGH___S 6 +#define DBG_CONDITION_DECODE2_STEP0__GROUP_1_AND_ACTIVE___M 0x00000020 +#define DBG_CONDITION_DECODE2_STEP0__GROUP_1_AND_ACTIVE___S 5 +#define DBG_CONDITION_DECODE2_STEP0__GROUP_1_AND_HIGH___M 0x00000010 +#define DBG_CONDITION_DECODE2_STEP0__GROUP_1_AND_HIGH___S 4 +#define DBG_CONDITION_DECODE2_STEP0__GROUP_0_OR_ACTIVE___M 0x00000008 +#define DBG_CONDITION_DECODE2_STEP0__GROUP_0_OR_ACTIVE___S 3 +#define DBG_CONDITION_DECODE2_STEP0__GROUP_0_OR_HIGH___M 0x00000004 +#define DBG_CONDITION_DECODE2_STEP0__GROUP_0_OR_HIGH___S 2 +#define DBG_CONDITION_DECODE2_STEP0__GROUP_0_AND_ACTIVE___M 0x00000002 +#define DBG_CONDITION_DECODE2_STEP0__GROUP_0_AND_ACTIVE___S 1 +#define DBG_CONDITION_DECODE2_STEP0__GROUP_0_AND_HIGH___M 0x00000001 +#define DBG_CONDITION_DECODE2_STEP0__GROUP_0_AND_HIGH___S 0 +#define DBG_CONDITION_DECODE2_STEP1 (0x00BC4230) +#define DBG_CONDITION_DECODE2_STEP1___RWC QCSR_REG_RW +#define DBG_CONDITION_DECODE2_STEP1__NOT___M 0x01000000 +#define DBG_CONDITION_DECODE2_STEP1__NOT___S 24 +#define DBG_CONDITION_DECODE2_STEP1__BC0_COMP_ACTIVE___M 0x00200000 +#define DBG_CONDITION_DECODE2_STEP1__BC0_COMP_ACTIVE___S 21 +#define DBG_CONDITION_DECODE2_STEP1__BC0_COMP_HIGH___M 0x00100000 +#define DBG_CONDITION_DECODE2_STEP1__BC0_COMP_HIGH___S 20 +#define DBG_CONDITION_DECODE2_STEP1__TC0_COMP_ACTIVE___M 0x00020000 +#define DBG_CONDITION_DECODE2_STEP1__TC0_COMP_ACTIVE___S 17 +#define DBG_CONDITION_DECODE2_STEP1__TC0_COMP_HIGH___M 0x00010000 +#define DBG_CONDITION_DECODE2_STEP1__TC0_COMP_HIGH___S 16 +#define DBG_CONDITION_DECODE2_STEP1__GROUP_3_OR_ACTIVE___M 0x00008000 +#define DBG_CONDITION_DECODE2_STEP1__GROUP_3_OR_ACTIVE___S 15 +#define DBG_CONDITION_DECODE2_STEP1__GROUP_3_OR_HIGH___M 0x00004000 +#define DBG_CONDITION_DECODE2_STEP1__GROUP_3_OR_HIGH___S 14 +#define DBG_CONDITION_DECODE2_STEP1__GROUP_3_AND_ACTIVE___M 0x00002000 +#define DBG_CONDITION_DECODE2_STEP1__GROUP_3_AND_ACTIVE___S 13 +#define DBG_CONDITION_DECODE2_STEP1__GROUP_3_AND_HIGH___M 0x00001000 +#define DBG_CONDITION_DECODE2_STEP1__GROUP_3_AND_HIGH___S 12 +#define DBG_CONDITION_DECODE2_STEP1__GROUP_2_OR_ACTIVE___M 0x00000800 +#define DBG_CONDITION_DECODE2_STEP1__GROUP_2_OR_ACTIVE___S 11 +#define DBG_CONDITION_DECODE2_STEP1__GROUP_2_OR_HIGH___M 0x00000400 +#define DBG_CONDITION_DECODE2_STEP1__GROUP_2_OR_HIGH___S 10 +#define DBG_CONDITION_DECODE2_STEP1__GROUP_2_AND_ACTIVE___M 0x00000200 +#define DBG_CONDITION_DECODE2_STEP1__GROUP_2_AND_ACTIVE___S 9 +#define DBG_CONDITION_DECODE2_STEP1__GROUP_2_AND_HIGH___M 0x00000100 +#define DBG_CONDITION_DECODE2_STEP1__GROUP_2_AND_HIGH___S 8 +#define DBG_CONDITION_DECODE2_STEP1__GROUP_1_OR_ACTIVE___M 0x00000080 +#define DBG_CONDITION_DECODE2_STEP1__GROUP_1_OR_ACTIVE___S 7 +#define DBG_CONDITION_DECODE2_STEP1__GROUP_1_OR_HIGH___M 0x00000040 +#define DBG_CONDITION_DECODE2_STEP1__GROUP_1_OR_HIGH___S 6 +#define DBG_CONDITION_DECODE2_STEP1__GROUP_1_AND_ACTIVE___M 0x00000020 +#define DBG_CONDITION_DECODE2_STEP1__GROUP_1_AND_ACTIVE___S 5 +#define DBG_CONDITION_DECODE2_STEP1__GROUP_1_AND_HIGH___M 0x00000010 +#define DBG_CONDITION_DECODE2_STEP1__GROUP_1_AND_HIGH___S 4 +#define DBG_CONDITION_DECODE2_STEP1__GROUP_0_OR_ACTIVE___M 0x00000008 +#define DBG_CONDITION_DECODE2_STEP1__GROUP_0_OR_ACTIVE___S 3 +#define DBG_CONDITION_DECODE2_STEP1__GROUP_0_OR_HIGH___M 0x00000004 +#define DBG_CONDITION_DECODE2_STEP1__GROUP_0_OR_HIGH___S 2 +#define DBG_CONDITION_DECODE2_STEP1__GROUP_0_AND_ACTIVE___M 0x00000002 +#define DBG_CONDITION_DECODE2_STEP1__GROUP_0_AND_ACTIVE___S 1 +#define DBG_CONDITION_DECODE2_STEP1__GROUP_0_AND_HIGH___M 0x00000001 +#define DBG_CONDITION_DECODE2_STEP1__GROUP_0_AND_HIGH___S 0 +#define DBG_CONDITION_DECODE2_STEP2 (0x00BC4408) +#define DBG_CONDITION_DECODE2_STEP2___RWC QCSR_REG_RW +#define DBG_CONDITION_DECODE2_STEP2__NOT___M 0x01000000 +#define DBG_CONDITION_DECODE2_STEP2__NOT___S 24 +#define DBG_CONDITION_DECODE2_STEP2__BC0_COMP_ACTIVE___M 0x00200000 +#define DBG_CONDITION_DECODE2_STEP2__BC0_COMP_ACTIVE___S 21 +#define DBG_CONDITION_DECODE2_STEP2__BC0_COMP_HIGH___M 0x00100000 +#define DBG_CONDITION_DECODE2_STEP2__BC0_COMP_HIGH___S 20 +#define DBG_CONDITION_DECODE2_STEP2__TC0_COMP_ACTIVE___M 0x00020000 +#define DBG_CONDITION_DECODE2_STEP2__TC0_COMP_ACTIVE___S 17 +#define DBG_CONDITION_DECODE2_STEP2__TC0_COMP_HIGH___M 0x00010000 +#define DBG_CONDITION_DECODE2_STEP2__TC0_COMP_HIGH___S 16 +#define DBG_CONDITION_DECODE2_STEP2__GROUP_3_OR_ACTIVE___M 0x00008000 +#define DBG_CONDITION_DECODE2_STEP2__GROUP_3_OR_ACTIVE___S 15 +#define DBG_CONDITION_DECODE2_STEP2__GROUP_3_OR_HIGH___M 0x00004000 +#define DBG_CONDITION_DECODE2_STEP2__GROUP_3_OR_HIGH___S 14 +#define DBG_CONDITION_DECODE2_STEP2__GROUP_3_AND_ACTIVE___M 0x00002000 +#define DBG_CONDITION_DECODE2_STEP2__GROUP_3_AND_ACTIVE___S 13 +#define DBG_CONDITION_DECODE2_STEP2__GROUP_3_AND_HIGH___M 0x00001000 +#define DBG_CONDITION_DECODE2_STEP2__GROUP_3_AND_HIGH___S 12 +#define DBG_CONDITION_DECODE2_STEP2__GROUP_2_OR_ACTIVE___M 0x00000800 +#define DBG_CONDITION_DECODE2_STEP2__GROUP_2_OR_ACTIVE___S 11 +#define DBG_CONDITION_DECODE2_STEP2__GROUP_2_OR_HIGH___M 0x00000400 +#define DBG_CONDITION_DECODE2_STEP2__GROUP_2_OR_HIGH___S 10 +#define DBG_CONDITION_DECODE2_STEP2__GROUP_2_AND_ACTIVE___M 0x00000200 +#define DBG_CONDITION_DECODE2_STEP2__GROUP_2_AND_ACTIVE___S 9 +#define DBG_CONDITION_DECODE2_STEP2__GROUP_2_AND_HIGH___M 0x00000100 +#define DBG_CONDITION_DECODE2_STEP2__GROUP_2_AND_HIGH___S 8 +#define DBG_CONDITION_DECODE2_STEP2__GROUP_1_OR_ACTIVE___M 0x00000080 +#define DBG_CONDITION_DECODE2_STEP2__GROUP_1_OR_ACTIVE___S 7 +#define DBG_CONDITION_DECODE2_STEP2__GROUP_1_OR_HIGH___M 0x00000040 +#define DBG_CONDITION_DECODE2_STEP2__GROUP_1_OR_HIGH___S 6 +#define DBG_CONDITION_DECODE2_STEP2__GROUP_1_AND_ACTIVE___M 0x00000020 +#define DBG_CONDITION_DECODE2_STEP2__GROUP_1_AND_ACTIVE___S 5 +#define DBG_CONDITION_DECODE2_STEP2__GROUP_1_AND_HIGH___M 0x00000010 +#define DBG_CONDITION_DECODE2_STEP2__GROUP_1_AND_HIGH___S 4 +#define DBG_CONDITION_DECODE2_STEP2__GROUP_0_OR_ACTIVE___M 0x00000008 +#define DBG_CONDITION_DECODE2_STEP2__GROUP_0_OR_ACTIVE___S 3 +#define DBG_CONDITION_DECODE2_STEP2__GROUP_0_OR_HIGH___M 0x00000004 +#define DBG_CONDITION_DECODE2_STEP2__GROUP_0_OR_HIGH___S 2 +#define DBG_CONDITION_DECODE2_STEP2__GROUP_0_AND_ACTIVE___M 0x00000002 +#define DBG_CONDITION_DECODE2_STEP2__GROUP_0_AND_ACTIVE___S 1 +#define DBG_CONDITION_DECODE2_STEP2__GROUP_0_AND_HIGH___M 0x00000001 +#define DBG_CONDITION_DECODE2_STEP2__GROUP_0_AND_HIGH___S 0 +#define DBG_CONDITION_DECODE2_STEP3 (0x00BC45E0) +#define DBG_CONDITION_DECODE2_STEP3___RWC QCSR_REG_RW +#define DBG_CONDITION_DECODE2_STEP3__NOT___M 0x01000000 +#define DBG_CONDITION_DECODE2_STEP3__NOT___S 24 +#define DBG_CONDITION_DECODE2_STEP3__BC0_COMP_ACTIVE___M 0x00200000 +#define DBG_CONDITION_DECODE2_STEP3__BC0_COMP_ACTIVE___S 21 +#define DBG_CONDITION_DECODE2_STEP3__BC0_COMP_HIGH___M 0x00100000 +#define DBG_CONDITION_DECODE2_STEP3__BC0_COMP_HIGH___S 20 +#define DBG_CONDITION_DECODE2_STEP3__TC0_COMP_ACTIVE___M 0x00020000 +#define DBG_CONDITION_DECODE2_STEP3__TC0_COMP_ACTIVE___S 17 +#define DBG_CONDITION_DECODE2_STEP3__TC0_COMP_HIGH___M 0x00010000 +#define DBG_CONDITION_DECODE2_STEP3__TC0_COMP_HIGH___S 16 +#define DBG_CONDITION_DECODE2_STEP3__GROUP_3_OR_ACTIVE___M 0x00008000 +#define DBG_CONDITION_DECODE2_STEP3__GROUP_3_OR_ACTIVE___S 15 +#define DBG_CONDITION_DECODE2_STEP3__GROUP_3_OR_HIGH___M 0x00004000 +#define DBG_CONDITION_DECODE2_STEP3__GROUP_3_OR_HIGH___S 14 +#define DBG_CONDITION_DECODE2_STEP3__GROUP_3_AND_ACTIVE___M 0x00002000 +#define DBG_CONDITION_DECODE2_STEP3__GROUP_3_AND_ACTIVE___S 13 +#define DBG_CONDITION_DECODE2_STEP3__GROUP_3_AND_HIGH___M 0x00001000 +#define DBG_CONDITION_DECODE2_STEP3__GROUP_3_AND_HIGH___S 12 +#define DBG_CONDITION_DECODE2_STEP3__GROUP_2_OR_ACTIVE___M 0x00000800 +#define DBG_CONDITION_DECODE2_STEP3__GROUP_2_OR_ACTIVE___S 11 +#define DBG_CONDITION_DECODE2_STEP3__GROUP_2_OR_HIGH___M 0x00000400 +#define DBG_CONDITION_DECODE2_STEP3__GROUP_2_OR_HIGH___S 10 +#define DBG_CONDITION_DECODE2_STEP3__GROUP_2_AND_ACTIVE___M 0x00000200 +#define DBG_CONDITION_DECODE2_STEP3__GROUP_2_AND_ACTIVE___S 9 +#define DBG_CONDITION_DECODE2_STEP3__GROUP_2_AND_HIGH___M 0x00000100 +#define DBG_CONDITION_DECODE2_STEP3__GROUP_2_AND_HIGH___S 8 +#define DBG_CONDITION_DECODE2_STEP3__GROUP_1_OR_ACTIVE___M 0x00000080 +#define DBG_CONDITION_DECODE2_STEP3__GROUP_1_OR_ACTIVE___S 7 +#define DBG_CONDITION_DECODE2_STEP3__GROUP_1_OR_HIGH___M 0x00000040 +#define DBG_CONDITION_DECODE2_STEP3__GROUP_1_OR_HIGH___S 6 +#define DBG_CONDITION_DECODE2_STEP3__GROUP_1_AND_ACTIVE___M 0x00000020 +#define DBG_CONDITION_DECODE2_STEP3__GROUP_1_AND_ACTIVE___S 5 +#define DBG_CONDITION_DECODE2_STEP3__GROUP_1_AND_HIGH___M 0x00000010 +#define DBG_CONDITION_DECODE2_STEP3__GROUP_1_AND_HIGH___S 4 +#define DBG_CONDITION_DECODE2_STEP3__GROUP_0_OR_ACTIVE___M 0x00000008 +#define DBG_CONDITION_DECODE2_STEP3__GROUP_0_OR_ACTIVE___S 3 +#define DBG_CONDITION_DECODE2_STEP3__GROUP_0_OR_HIGH___M 0x00000004 +#define DBG_CONDITION_DECODE2_STEP3__GROUP_0_OR_HIGH___S 2 +#define DBG_CONDITION_DECODE2_STEP3__GROUP_0_AND_ACTIVE___M 0x00000002 +#define DBG_CONDITION_DECODE2_STEP3__GROUP_0_AND_ACTIVE___S 1 +#define DBG_CONDITION_DECODE2_STEP3__GROUP_0_AND_HIGH___M 0x00000001 +#define DBG_CONDITION_DECODE2_STEP3__GROUP_0_AND_HIGH___S 0 +#define DBG_CONDITION_DECODE2_STEP4 (0x00BC47B8) +#define DBG_CONDITION_DECODE2_STEP4___RWC QCSR_REG_RW +#define DBG_CONDITION_DECODE2_STEP4__NOT___M 0x01000000 +#define DBG_CONDITION_DECODE2_STEP4__NOT___S 24 +#define DBG_CONDITION_DECODE2_STEP4__BC0_COMP_ACTIVE___M 0x00200000 +#define DBG_CONDITION_DECODE2_STEP4__BC0_COMP_ACTIVE___S 21 +#define DBG_CONDITION_DECODE2_STEP4__BC0_COMP_HIGH___M 0x00100000 +#define DBG_CONDITION_DECODE2_STEP4__BC0_COMP_HIGH___S 20 +#define DBG_CONDITION_DECODE2_STEP4__TC0_COMP_ACTIVE___M 0x00020000 +#define DBG_CONDITION_DECODE2_STEP4__TC0_COMP_ACTIVE___S 17 +#define DBG_CONDITION_DECODE2_STEP4__TC0_COMP_HIGH___M 0x00010000 +#define DBG_CONDITION_DECODE2_STEP4__TC0_COMP_HIGH___S 16 +#define DBG_CONDITION_DECODE2_STEP4__GROUP_3_OR_ACTIVE___M 0x00008000 +#define DBG_CONDITION_DECODE2_STEP4__GROUP_3_OR_ACTIVE___S 15 +#define DBG_CONDITION_DECODE2_STEP4__GROUP_3_OR_HIGH___M 0x00004000 +#define DBG_CONDITION_DECODE2_STEP4__GROUP_3_OR_HIGH___S 14 +#define DBG_CONDITION_DECODE2_STEP4__GROUP_3_AND_ACTIVE___M 0x00002000 +#define DBG_CONDITION_DECODE2_STEP4__GROUP_3_AND_ACTIVE___S 13 +#define DBG_CONDITION_DECODE2_STEP4__GROUP_3_AND_HIGH___M 0x00001000 +#define DBG_CONDITION_DECODE2_STEP4__GROUP_3_AND_HIGH___S 12 +#define DBG_CONDITION_DECODE2_STEP4__GROUP_2_OR_ACTIVE___M 0x00000800 +#define DBG_CONDITION_DECODE2_STEP4__GROUP_2_OR_ACTIVE___S 11 +#define DBG_CONDITION_DECODE2_STEP4__GROUP_2_OR_HIGH___M 0x00000400 +#define DBG_CONDITION_DECODE2_STEP4__GROUP_2_OR_HIGH___S 10 +#define DBG_CONDITION_DECODE2_STEP4__GROUP_2_AND_ACTIVE___M 0x00000200 +#define DBG_CONDITION_DECODE2_STEP4__GROUP_2_AND_ACTIVE___S 9 +#define DBG_CONDITION_DECODE2_STEP4__GROUP_2_AND_HIGH___M 0x00000100 +#define DBG_CONDITION_DECODE2_STEP4__GROUP_2_AND_HIGH___S 8 +#define DBG_CONDITION_DECODE2_STEP4__GROUP_1_OR_ACTIVE___M 0x00000080 +#define DBG_CONDITION_DECODE2_STEP4__GROUP_1_OR_ACTIVE___S 7 +#define DBG_CONDITION_DECODE2_STEP4__GROUP_1_OR_HIGH___M 0x00000040 +#define DBG_CONDITION_DECODE2_STEP4__GROUP_1_OR_HIGH___S 6 +#define DBG_CONDITION_DECODE2_STEP4__GROUP_1_AND_ACTIVE___M 0x00000020 +#define DBG_CONDITION_DECODE2_STEP4__GROUP_1_AND_ACTIVE___S 5 +#define DBG_CONDITION_DECODE2_STEP4__GROUP_1_AND_HIGH___M 0x00000010 +#define DBG_CONDITION_DECODE2_STEP4__GROUP_1_AND_HIGH___S 4 +#define DBG_CONDITION_DECODE2_STEP4__GROUP_0_OR_ACTIVE___M 0x00000008 +#define DBG_CONDITION_DECODE2_STEP4__GROUP_0_OR_ACTIVE___S 3 +#define DBG_CONDITION_DECODE2_STEP4__GROUP_0_OR_HIGH___M 0x00000004 +#define DBG_CONDITION_DECODE2_STEP4__GROUP_0_OR_HIGH___S 2 +#define DBG_CONDITION_DECODE2_STEP4__GROUP_0_AND_ACTIVE___M 0x00000002 +#define DBG_CONDITION_DECODE2_STEP4__GROUP_0_AND_ACTIVE___S 1 +#define DBG_CONDITION_DECODE2_STEP4__GROUP_0_AND_HIGH___M 0x00000001 +#define DBG_CONDITION_DECODE2_STEP4__GROUP_0_AND_HIGH___S 0 +#define DBG_CONDITION_DECODE2_STEP5 (0x00BC4990) +#define DBG_CONDITION_DECODE2_STEP5___RWC QCSR_REG_RW +#define DBG_CONDITION_DECODE2_STEP5__NOT___M 0x01000000 +#define DBG_CONDITION_DECODE2_STEP5__NOT___S 24 +#define DBG_CONDITION_DECODE2_STEP5__BC0_COMP_ACTIVE___M 0x00200000 +#define DBG_CONDITION_DECODE2_STEP5__BC0_COMP_ACTIVE___S 21 +#define DBG_CONDITION_DECODE2_STEP5__BC0_COMP_HIGH___M 0x00100000 +#define DBG_CONDITION_DECODE2_STEP5__BC0_COMP_HIGH___S 20 +#define DBG_CONDITION_DECODE2_STEP5__TC0_COMP_ACTIVE___M 0x00020000 +#define DBG_CONDITION_DECODE2_STEP5__TC0_COMP_ACTIVE___S 17 +#define DBG_CONDITION_DECODE2_STEP5__TC0_COMP_HIGH___M 0x00010000 +#define DBG_CONDITION_DECODE2_STEP5__TC0_COMP_HIGH___S 16 +#define DBG_CONDITION_DECODE2_STEP5__GROUP_3_OR_ACTIVE___M 0x00008000 +#define DBG_CONDITION_DECODE2_STEP5__GROUP_3_OR_ACTIVE___S 15 +#define DBG_CONDITION_DECODE2_STEP5__GROUP_3_OR_HIGH___M 0x00004000 +#define DBG_CONDITION_DECODE2_STEP5__GROUP_3_OR_HIGH___S 14 +#define DBG_CONDITION_DECODE2_STEP5__GROUP_3_AND_ACTIVE___M 0x00002000 +#define DBG_CONDITION_DECODE2_STEP5__GROUP_3_AND_ACTIVE___S 13 +#define DBG_CONDITION_DECODE2_STEP5__GROUP_3_AND_HIGH___M 0x00001000 +#define DBG_CONDITION_DECODE2_STEP5__GROUP_3_AND_HIGH___S 12 +#define DBG_CONDITION_DECODE2_STEP5__GROUP_2_OR_ACTIVE___M 0x00000800 +#define DBG_CONDITION_DECODE2_STEP5__GROUP_2_OR_ACTIVE___S 11 +#define DBG_CONDITION_DECODE2_STEP5__GROUP_2_OR_HIGH___M 0x00000400 +#define DBG_CONDITION_DECODE2_STEP5__GROUP_2_OR_HIGH___S 10 +#define DBG_CONDITION_DECODE2_STEP5__GROUP_2_AND_ACTIVE___M 0x00000200 +#define DBG_CONDITION_DECODE2_STEP5__GROUP_2_AND_ACTIVE___S 9 +#define DBG_CONDITION_DECODE2_STEP5__GROUP_2_AND_HIGH___M 0x00000100 +#define DBG_CONDITION_DECODE2_STEP5__GROUP_2_AND_HIGH___S 8 +#define DBG_CONDITION_DECODE2_STEP5__GROUP_1_OR_ACTIVE___M 0x00000080 +#define DBG_CONDITION_DECODE2_STEP5__GROUP_1_OR_ACTIVE___S 7 +#define DBG_CONDITION_DECODE2_STEP5__GROUP_1_OR_HIGH___M 0x00000040 +#define DBG_CONDITION_DECODE2_STEP5__GROUP_1_OR_HIGH___S 6 +#define DBG_CONDITION_DECODE2_STEP5__GROUP_1_AND_ACTIVE___M 0x00000020 +#define DBG_CONDITION_DECODE2_STEP5__GROUP_1_AND_ACTIVE___S 5 +#define DBG_CONDITION_DECODE2_STEP5__GROUP_1_AND_HIGH___M 0x00000010 +#define DBG_CONDITION_DECODE2_STEP5__GROUP_1_AND_HIGH___S 4 +#define DBG_CONDITION_DECODE2_STEP5__GROUP_0_OR_ACTIVE___M 0x00000008 +#define DBG_CONDITION_DECODE2_STEP5__GROUP_0_OR_ACTIVE___S 3 +#define DBG_CONDITION_DECODE2_STEP5__GROUP_0_OR_HIGH___M 0x00000004 +#define DBG_CONDITION_DECODE2_STEP5__GROUP_0_OR_HIGH___S 2 +#define DBG_CONDITION_DECODE2_STEP5__GROUP_0_AND_ACTIVE___M 0x00000002 +#define DBG_CONDITION_DECODE2_STEP5__GROUP_0_AND_ACTIVE___S 1 +#define DBG_CONDITION_DECODE2_STEP5__GROUP_0_AND_HIGH___M 0x00000001 +#define DBG_CONDITION_DECODE2_STEP5__GROUP_0_AND_HIGH___S 0 +#define DBG_CONDITION_DECODE2_STEP6 (0x00BC4B68) +#define DBG_CONDITION_DECODE2_STEP6___RWC QCSR_REG_RW +#define DBG_CONDITION_DECODE2_STEP6__NOT___M 0x01000000 +#define DBG_CONDITION_DECODE2_STEP6__NOT___S 24 +#define DBG_CONDITION_DECODE2_STEP6__BC0_COMP_ACTIVE___M 0x00200000 +#define DBG_CONDITION_DECODE2_STEP6__BC0_COMP_ACTIVE___S 21 +#define DBG_CONDITION_DECODE2_STEP6__BC0_COMP_HIGH___M 0x00100000 +#define DBG_CONDITION_DECODE2_STEP6__BC0_COMP_HIGH___S 20 +#define DBG_CONDITION_DECODE2_STEP6__TC0_COMP_ACTIVE___M 0x00020000 +#define DBG_CONDITION_DECODE2_STEP6__TC0_COMP_ACTIVE___S 17 +#define DBG_CONDITION_DECODE2_STEP6__TC0_COMP_HIGH___M 0x00010000 +#define DBG_CONDITION_DECODE2_STEP6__TC0_COMP_HIGH___S 16 +#define DBG_CONDITION_DECODE2_STEP6__GROUP_3_OR_ACTIVE___M 0x00008000 +#define DBG_CONDITION_DECODE2_STEP6__GROUP_3_OR_ACTIVE___S 15 +#define DBG_CONDITION_DECODE2_STEP6__GROUP_3_OR_HIGH___M 0x00004000 +#define DBG_CONDITION_DECODE2_STEP6__GROUP_3_OR_HIGH___S 14 +#define DBG_CONDITION_DECODE2_STEP6__GROUP_3_AND_ACTIVE___M 0x00002000 +#define DBG_CONDITION_DECODE2_STEP6__GROUP_3_AND_ACTIVE___S 13 +#define DBG_CONDITION_DECODE2_STEP6__GROUP_3_AND_HIGH___M 0x00001000 +#define DBG_CONDITION_DECODE2_STEP6__GROUP_3_AND_HIGH___S 12 +#define DBG_CONDITION_DECODE2_STEP6__GROUP_2_OR_ACTIVE___M 0x00000800 +#define DBG_CONDITION_DECODE2_STEP6__GROUP_2_OR_ACTIVE___S 11 +#define DBG_CONDITION_DECODE2_STEP6__GROUP_2_OR_HIGH___M 0x00000400 +#define DBG_CONDITION_DECODE2_STEP6__GROUP_2_OR_HIGH___S 10 +#define DBG_CONDITION_DECODE2_STEP6__GROUP_2_AND_ACTIVE___M 0x00000200 +#define DBG_CONDITION_DECODE2_STEP6__GROUP_2_AND_ACTIVE___S 9 +#define DBG_CONDITION_DECODE2_STEP6__GROUP_2_AND_HIGH___M 0x00000100 +#define DBG_CONDITION_DECODE2_STEP6__GROUP_2_AND_HIGH___S 8 +#define DBG_CONDITION_DECODE2_STEP6__GROUP_1_OR_ACTIVE___M 0x00000080 +#define DBG_CONDITION_DECODE2_STEP6__GROUP_1_OR_ACTIVE___S 7 +#define DBG_CONDITION_DECODE2_STEP6__GROUP_1_OR_HIGH___M 0x00000040 +#define DBG_CONDITION_DECODE2_STEP6__GROUP_1_OR_HIGH___S 6 +#define DBG_CONDITION_DECODE2_STEP6__GROUP_1_AND_ACTIVE___M 0x00000020 +#define DBG_CONDITION_DECODE2_STEP6__GROUP_1_AND_ACTIVE___S 5 +#define DBG_CONDITION_DECODE2_STEP6__GROUP_1_AND_HIGH___M 0x00000010 +#define DBG_CONDITION_DECODE2_STEP6__GROUP_1_AND_HIGH___S 4 +#define DBG_CONDITION_DECODE2_STEP6__GROUP_0_OR_ACTIVE___M 0x00000008 +#define DBG_CONDITION_DECODE2_STEP6__GROUP_0_OR_ACTIVE___S 3 +#define DBG_CONDITION_DECODE2_STEP6__GROUP_0_OR_HIGH___M 0x00000004 +#define DBG_CONDITION_DECODE2_STEP6__GROUP_0_OR_HIGH___S 2 +#define DBG_CONDITION_DECODE2_STEP6__GROUP_0_AND_ACTIVE___M 0x00000002 +#define DBG_CONDITION_DECODE2_STEP6__GROUP_0_AND_ACTIVE___S 1 +#define DBG_CONDITION_DECODE2_STEP6__GROUP_0_AND_HIGH___M 0x00000001 +#define DBG_CONDITION_DECODE2_STEP6__GROUP_0_AND_HIGH___S 0 +#define DBG_CONDITION_DECODE2_STEP7 (0x00BC4D40) +#define DBG_CONDITION_DECODE2_STEP7___RWC QCSR_REG_RW +#define DBG_CONDITION_DECODE2_STEP7__NOT___M 0x01000000 +#define DBG_CONDITION_DECODE2_STEP7__NOT___S 24 +#define DBG_CONDITION_DECODE2_STEP7__BC0_COMP_ACTIVE___M 0x00200000 +#define DBG_CONDITION_DECODE2_STEP7__BC0_COMP_ACTIVE___S 21 +#define DBG_CONDITION_DECODE2_STEP7__BC0_COMP_HIGH___M 0x00100000 +#define DBG_CONDITION_DECODE2_STEP7__BC0_COMP_HIGH___S 20 +#define DBG_CONDITION_DECODE2_STEP7__TC0_COMP_ACTIVE___M 0x00020000 +#define DBG_CONDITION_DECODE2_STEP7__TC0_COMP_ACTIVE___S 17 +#define DBG_CONDITION_DECODE2_STEP7__TC0_COMP_HIGH___M 0x00010000 +#define DBG_CONDITION_DECODE2_STEP7__TC0_COMP_HIGH___S 16 +#define DBG_CONDITION_DECODE2_STEP7__GROUP_3_OR_ACTIVE___M 0x00008000 +#define DBG_CONDITION_DECODE2_STEP7__GROUP_3_OR_ACTIVE___S 15 +#define DBG_CONDITION_DECODE2_STEP7__GROUP_3_OR_HIGH___M 0x00004000 +#define DBG_CONDITION_DECODE2_STEP7__GROUP_3_OR_HIGH___S 14 +#define DBG_CONDITION_DECODE2_STEP7__GROUP_3_AND_ACTIVE___M 0x00002000 +#define DBG_CONDITION_DECODE2_STEP7__GROUP_3_AND_ACTIVE___S 13 +#define DBG_CONDITION_DECODE2_STEP7__GROUP_3_AND_HIGH___M 0x00001000 +#define DBG_CONDITION_DECODE2_STEP7__GROUP_3_AND_HIGH___S 12 +#define DBG_CONDITION_DECODE2_STEP7__GROUP_2_OR_ACTIVE___M 0x00000800 +#define DBG_CONDITION_DECODE2_STEP7__GROUP_2_OR_ACTIVE___S 11 +#define DBG_CONDITION_DECODE2_STEP7__GROUP_2_OR_HIGH___M 0x00000400 +#define DBG_CONDITION_DECODE2_STEP7__GROUP_2_OR_HIGH___S 10 +#define DBG_CONDITION_DECODE2_STEP7__GROUP_2_AND_ACTIVE___M 0x00000200 +#define DBG_CONDITION_DECODE2_STEP7__GROUP_2_AND_ACTIVE___S 9 +#define DBG_CONDITION_DECODE2_STEP7__GROUP_2_AND_HIGH___M 0x00000100 +#define DBG_CONDITION_DECODE2_STEP7__GROUP_2_AND_HIGH___S 8 +#define DBG_CONDITION_DECODE2_STEP7__GROUP_1_OR_ACTIVE___M 0x00000080 +#define DBG_CONDITION_DECODE2_STEP7__GROUP_1_OR_ACTIVE___S 7 +#define DBG_CONDITION_DECODE2_STEP7__GROUP_1_OR_HIGH___M 0x00000040 +#define DBG_CONDITION_DECODE2_STEP7__GROUP_1_OR_HIGH___S 6 +#define DBG_CONDITION_DECODE2_STEP7__GROUP_1_AND_ACTIVE___M 0x00000020 +#define DBG_CONDITION_DECODE2_STEP7__GROUP_1_AND_ACTIVE___S 5 +#define DBG_CONDITION_DECODE2_STEP7__GROUP_1_AND_HIGH___M 0x00000010 +#define DBG_CONDITION_DECODE2_STEP7__GROUP_1_AND_HIGH___S 4 +#define DBG_CONDITION_DECODE2_STEP7__GROUP_0_OR_ACTIVE___M 0x00000008 +#define DBG_CONDITION_DECODE2_STEP7__GROUP_0_OR_ACTIVE___S 3 +#define DBG_CONDITION_DECODE2_STEP7__GROUP_0_OR_HIGH___M 0x00000004 +#define DBG_CONDITION_DECODE2_STEP7__GROUP_0_OR_HIGH___S 2 +#define DBG_CONDITION_DECODE2_STEP7__GROUP_0_AND_ACTIVE___M 0x00000002 +#define DBG_CONDITION_DECODE2_STEP7__GROUP_0_AND_ACTIVE___S 1 +#define DBG_CONDITION_DECODE2_STEP7__GROUP_0_AND_HIGH___M 0x00000001 +#define DBG_CONDITION_DECODE2_STEP7__GROUP_0_AND_HIGH___S 0 +#define DBG_CONDITION_DECODE3_STEP0 (0x00BC405C) +#define DBG_CONDITION_DECODE3_STEP0___RWC QCSR_REG_RW +#define DBG_CONDITION_DECODE3_STEP0__NOT___M 0x01000000 +#define DBG_CONDITION_DECODE3_STEP0__NOT___S 24 +#define DBG_CONDITION_DECODE3_STEP0__BC0_COMP_ACTIVE___M 0x00200000 +#define DBG_CONDITION_DECODE3_STEP0__BC0_COMP_ACTIVE___S 21 +#define DBG_CONDITION_DECODE3_STEP0__BC0_COMP_HIGH___M 0x00100000 +#define DBG_CONDITION_DECODE3_STEP0__BC0_COMP_HIGH___S 20 +#define DBG_CONDITION_DECODE3_STEP0__TC0_COMP_ACTIVE___M 0x00020000 +#define DBG_CONDITION_DECODE3_STEP0__TC0_COMP_ACTIVE___S 17 +#define DBG_CONDITION_DECODE3_STEP0__TC0_COMP_HIGH___M 0x00010000 +#define DBG_CONDITION_DECODE3_STEP0__TC0_COMP_HIGH___S 16 +#define DBG_CONDITION_DECODE3_STEP0__GROUP_3_OR_ACTIVE___M 0x00008000 +#define DBG_CONDITION_DECODE3_STEP0__GROUP_3_OR_ACTIVE___S 15 +#define DBG_CONDITION_DECODE3_STEP0__GROUP_3_OR_HIGH___M 0x00004000 +#define DBG_CONDITION_DECODE3_STEP0__GROUP_3_OR_HIGH___S 14 +#define DBG_CONDITION_DECODE3_STEP0__GROUP_3_AND_ACTIVE___M 0x00002000 +#define DBG_CONDITION_DECODE3_STEP0__GROUP_3_AND_ACTIVE___S 13 +#define DBG_CONDITION_DECODE3_STEP0__GROUP_3_AND_HIGH___M 0x00001000 +#define DBG_CONDITION_DECODE3_STEP0__GROUP_3_AND_HIGH___S 12 +#define DBG_CONDITION_DECODE3_STEP0__GROUP_2_OR_ACTIVE___M 0x00000800 +#define DBG_CONDITION_DECODE3_STEP0__GROUP_2_OR_ACTIVE___S 11 +#define DBG_CONDITION_DECODE3_STEP0__GROUP_2_OR_HIGH___M 0x00000400 +#define DBG_CONDITION_DECODE3_STEP0__GROUP_2_OR_HIGH___S 10 +#define DBG_CONDITION_DECODE3_STEP0__GROUP_2_AND_ACTIVE___M 0x00000200 +#define DBG_CONDITION_DECODE3_STEP0__GROUP_2_AND_ACTIVE___S 9 +#define DBG_CONDITION_DECODE3_STEP0__GROUP_2_AND_HIGH___M 0x00000100 +#define DBG_CONDITION_DECODE3_STEP0__GROUP_2_AND_HIGH___S 8 +#define DBG_CONDITION_DECODE3_STEP0__GROUP_1_OR_ACTIVE___M 0x00000080 +#define DBG_CONDITION_DECODE3_STEP0__GROUP_1_OR_ACTIVE___S 7 +#define DBG_CONDITION_DECODE3_STEP0__GROUP_1_OR_HIGH___M 0x00000040 +#define DBG_CONDITION_DECODE3_STEP0__GROUP_1_OR_HIGH___S 6 +#define DBG_CONDITION_DECODE3_STEP0__GROUP_1_AND_ACTIVE___M 0x00000020 +#define DBG_CONDITION_DECODE3_STEP0__GROUP_1_AND_ACTIVE___S 5 +#define DBG_CONDITION_DECODE3_STEP0__GROUP_1_AND_HIGH___M 0x00000010 +#define DBG_CONDITION_DECODE3_STEP0__GROUP_1_AND_HIGH___S 4 +#define DBG_CONDITION_DECODE3_STEP0__GROUP_0_OR_ACTIVE___M 0x00000008 +#define DBG_CONDITION_DECODE3_STEP0__GROUP_0_OR_ACTIVE___S 3 +#define DBG_CONDITION_DECODE3_STEP0__GROUP_0_OR_HIGH___M 0x00000004 +#define DBG_CONDITION_DECODE3_STEP0__GROUP_0_OR_HIGH___S 2 +#define DBG_CONDITION_DECODE3_STEP0__GROUP_0_AND_ACTIVE___M 0x00000002 +#define DBG_CONDITION_DECODE3_STEP0__GROUP_0_AND_ACTIVE___S 1 +#define DBG_CONDITION_DECODE3_STEP0__GROUP_0_AND_HIGH___M 0x00000001 +#define DBG_CONDITION_DECODE3_STEP0__GROUP_0_AND_HIGH___S 0 +#define DBG_CONDITION_DECODE3_STEP1 (0x00BC4234) +#define DBG_CONDITION_DECODE3_STEP1___RWC QCSR_REG_RW +#define DBG_CONDITION_DECODE3_STEP1__NOT___M 0x01000000 +#define DBG_CONDITION_DECODE3_STEP1__NOT___S 24 +#define DBG_CONDITION_DECODE3_STEP1__BC0_COMP_ACTIVE___M 0x00200000 +#define DBG_CONDITION_DECODE3_STEP1__BC0_COMP_ACTIVE___S 21 +#define DBG_CONDITION_DECODE3_STEP1__BC0_COMP_HIGH___M 0x00100000 +#define DBG_CONDITION_DECODE3_STEP1__BC0_COMP_HIGH___S 20 +#define DBG_CONDITION_DECODE3_STEP1__TC0_COMP_ACTIVE___M 0x00020000 +#define DBG_CONDITION_DECODE3_STEP1__TC0_COMP_ACTIVE___S 17 +#define DBG_CONDITION_DECODE3_STEP1__TC0_COMP_HIGH___M 0x00010000 +#define DBG_CONDITION_DECODE3_STEP1__TC0_COMP_HIGH___S 16 +#define DBG_CONDITION_DECODE3_STEP1__GROUP_3_OR_ACTIVE___M 0x00008000 +#define DBG_CONDITION_DECODE3_STEP1__GROUP_3_OR_ACTIVE___S 15 +#define DBG_CONDITION_DECODE3_STEP1__GROUP_3_OR_HIGH___M 0x00004000 +#define DBG_CONDITION_DECODE3_STEP1__GROUP_3_OR_HIGH___S 14 +#define DBG_CONDITION_DECODE3_STEP1__GROUP_3_AND_ACTIVE___M 0x00002000 +#define DBG_CONDITION_DECODE3_STEP1__GROUP_3_AND_ACTIVE___S 13 +#define DBG_CONDITION_DECODE3_STEP1__GROUP_3_AND_HIGH___M 0x00001000 +#define DBG_CONDITION_DECODE3_STEP1__GROUP_3_AND_HIGH___S 12 +#define DBG_CONDITION_DECODE3_STEP1__GROUP_2_OR_ACTIVE___M 0x00000800 +#define DBG_CONDITION_DECODE3_STEP1__GROUP_2_OR_ACTIVE___S 11 +#define DBG_CONDITION_DECODE3_STEP1__GROUP_2_OR_HIGH___M 0x00000400 +#define DBG_CONDITION_DECODE3_STEP1__GROUP_2_OR_HIGH___S 10 +#define DBG_CONDITION_DECODE3_STEP1__GROUP_2_AND_ACTIVE___M 0x00000200 +#define DBG_CONDITION_DECODE3_STEP1__GROUP_2_AND_ACTIVE___S 9 +#define DBG_CONDITION_DECODE3_STEP1__GROUP_2_AND_HIGH___M 0x00000100 +#define DBG_CONDITION_DECODE3_STEP1__GROUP_2_AND_HIGH___S 8 +#define DBG_CONDITION_DECODE3_STEP1__GROUP_1_OR_ACTIVE___M 0x00000080 +#define DBG_CONDITION_DECODE3_STEP1__GROUP_1_OR_ACTIVE___S 7 +#define DBG_CONDITION_DECODE3_STEP1__GROUP_1_OR_HIGH___M 0x00000040 +#define DBG_CONDITION_DECODE3_STEP1__GROUP_1_OR_HIGH___S 6 +#define DBG_CONDITION_DECODE3_STEP1__GROUP_1_AND_ACTIVE___M 0x00000020 +#define DBG_CONDITION_DECODE3_STEP1__GROUP_1_AND_ACTIVE___S 5 +#define DBG_CONDITION_DECODE3_STEP1__GROUP_1_AND_HIGH___M 0x00000010 +#define DBG_CONDITION_DECODE3_STEP1__GROUP_1_AND_HIGH___S 4 +#define DBG_CONDITION_DECODE3_STEP1__GROUP_0_OR_ACTIVE___M 0x00000008 +#define DBG_CONDITION_DECODE3_STEP1__GROUP_0_OR_ACTIVE___S 3 +#define DBG_CONDITION_DECODE3_STEP1__GROUP_0_OR_HIGH___M 0x00000004 +#define DBG_CONDITION_DECODE3_STEP1__GROUP_0_OR_HIGH___S 2 +#define DBG_CONDITION_DECODE3_STEP1__GROUP_0_AND_ACTIVE___M 0x00000002 +#define DBG_CONDITION_DECODE3_STEP1__GROUP_0_AND_ACTIVE___S 1 +#define DBG_CONDITION_DECODE3_STEP1__GROUP_0_AND_HIGH___M 0x00000001 +#define DBG_CONDITION_DECODE3_STEP1__GROUP_0_AND_HIGH___S 0 +#define DBG_CONDITION_DECODE3_STEP2 (0x00BC440C) +#define DBG_CONDITION_DECODE3_STEP2___RWC QCSR_REG_RW +#define DBG_CONDITION_DECODE3_STEP2__NOT___M 0x01000000 +#define DBG_CONDITION_DECODE3_STEP2__NOT___S 24 +#define DBG_CONDITION_DECODE3_STEP2__BC0_COMP_ACTIVE___M 0x00200000 +#define DBG_CONDITION_DECODE3_STEP2__BC0_COMP_ACTIVE___S 21 +#define DBG_CONDITION_DECODE3_STEP2__BC0_COMP_HIGH___M 0x00100000 +#define DBG_CONDITION_DECODE3_STEP2__BC0_COMP_HIGH___S 20 +#define DBG_CONDITION_DECODE3_STEP2__TC0_COMP_ACTIVE___M 0x00020000 +#define DBG_CONDITION_DECODE3_STEP2__TC0_COMP_ACTIVE___S 17 +#define DBG_CONDITION_DECODE3_STEP2__TC0_COMP_HIGH___M 0x00010000 +#define DBG_CONDITION_DECODE3_STEP2__TC0_COMP_HIGH___S 16 +#define DBG_CONDITION_DECODE3_STEP2__GROUP_3_OR_ACTIVE___M 0x00008000 +#define DBG_CONDITION_DECODE3_STEP2__GROUP_3_OR_ACTIVE___S 15 +#define DBG_CONDITION_DECODE3_STEP2__GROUP_3_OR_HIGH___M 0x00004000 +#define DBG_CONDITION_DECODE3_STEP2__GROUP_3_OR_HIGH___S 14 +#define DBG_CONDITION_DECODE3_STEP2__GROUP_3_AND_ACTIVE___M 0x00002000 +#define DBG_CONDITION_DECODE3_STEP2__GROUP_3_AND_ACTIVE___S 13 +#define DBG_CONDITION_DECODE3_STEP2__GROUP_3_AND_HIGH___M 0x00001000 +#define DBG_CONDITION_DECODE3_STEP2__GROUP_3_AND_HIGH___S 12 +#define DBG_CONDITION_DECODE3_STEP2__GROUP_2_OR_ACTIVE___M 0x00000800 +#define DBG_CONDITION_DECODE3_STEP2__GROUP_2_OR_ACTIVE___S 11 +#define DBG_CONDITION_DECODE3_STEP2__GROUP_2_OR_HIGH___M 0x00000400 +#define DBG_CONDITION_DECODE3_STEP2__GROUP_2_OR_HIGH___S 10 +#define DBG_CONDITION_DECODE3_STEP2__GROUP_2_AND_ACTIVE___M 0x00000200 +#define DBG_CONDITION_DECODE3_STEP2__GROUP_2_AND_ACTIVE___S 9 +#define DBG_CONDITION_DECODE3_STEP2__GROUP_2_AND_HIGH___M 0x00000100 +#define DBG_CONDITION_DECODE3_STEP2__GROUP_2_AND_HIGH___S 8 +#define DBG_CONDITION_DECODE3_STEP2__GROUP_1_OR_ACTIVE___M 0x00000080 +#define DBG_CONDITION_DECODE3_STEP2__GROUP_1_OR_ACTIVE___S 7 +#define DBG_CONDITION_DECODE3_STEP2__GROUP_1_OR_HIGH___M 0x00000040 +#define DBG_CONDITION_DECODE3_STEP2__GROUP_1_OR_HIGH___S 6 +#define DBG_CONDITION_DECODE3_STEP2__GROUP_1_AND_ACTIVE___M 0x00000020 +#define DBG_CONDITION_DECODE3_STEP2__GROUP_1_AND_ACTIVE___S 5 +#define DBG_CONDITION_DECODE3_STEP2__GROUP_1_AND_HIGH___M 0x00000010 +#define DBG_CONDITION_DECODE3_STEP2__GROUP_1_AND_HIGH___S 4 +#define DBG_CONDITION_DECODE3_STEP2__GROUP_0_OR_ACTIVE___M 0x00000008 +#define DBG_CONDITION_DECODE3_STEP2__GROUP_0_OR_ACTIVE___S 3 +#define DBG_CONDITION_DECODE3_STEP2__GROUP_0_OR_HIGH___M 0x00000004 +#define DBG_CONDITION_DECODE3_STEP2__GROUP_0_OR_HIGH___S 2 +#define DBG_CONDITION_DECODE3_STEP2__GROUP_0_AND_ACTIVE___M 0x00000002 +#define DBG_CONDITION_DECODE3_STEP2__GROUP_0_AND_ACTIVE___S 1 +#define DBG_CONDITION_DECODE3_STEP2__GROUP_0_AND_HIGH___M 0x00000001 +#define DBG_CONDITION_DECODE3_STEP2__GROUP_0_AND_HIGH___S 0 +#define DBG_CONDITION_DECODE3_STEP3 (0x00BC45E4) +#define DBG_CONDITION_DECODE3_STEP3___RWC QCSR_REG_RW +#define DBG_CONDITION_DECODE3_STEP3__NOT___M 0x01000000 +#define DBG_CONDITION_DECODE3_STEP3__NOT___S 24 +#define DBG_CONDITION_DECODE3_STEP3__BC0_COMP_ACTIVE___M 0x00200000 +#define DBG_CONDITION_DECODE3_STEP3__BC0_COMP_ACTIVE___S 21 +#define DBG_CONDITION_DECODE3_STEP3__BC0_COMP_HIGH___M 0x00100000 +#define DBG_CONDITION_DECODE3_STEP3__BC0_COMP_HIGH___S 20 +#define DBG_CONDITION_DECODE3_STEP3__TC0_COMP_ACTIVE___M 0x00020000 +#define DBG_CONDITION_DECODE3_STEP3__TC0_COMP_ACTIVE___S 17 +#define DBG_CONDITION_DECODE3_STEP3__TC0_COMP_HIGH___M 0x00010000 +#define DBG_CONDITION_DECODE3_STEP3__TC0_COMP_HIGH___S 16 +#define DBG_CONDITION_DECODE3_STEP3__GROUP_3_OR_ACTIVE___M 0x00008000 +#define DBG_CONDITION_DECODE3_STEP3__GROUP_3_OR_ACTIVE___S 15 +#define DBG_CONDITION_DECODE3_STEP3__GROUP_3_OR_HIGH___M 0x00004000 +#define DBG_CONDITION_DECODE3_STEP3__GROUP_3_OR_HIGH___S 14 +#define DBG_CONDITION_DECODE3_STEP3__GROUP_3_AND_ACTIVE___M 0x00002000 +#define DBG_CONDITION_DECODE3_STEP3__GROUP_3_AND_ACTIVE___S 13 +#define DBG_CONDITION_DECODE3_STEP3__GROUP_3_AND_HIGH___M 0x00001000 +#define DBG_CONDITION_DECODE3_STEP3__GROUP_3_AND_HIGH___S 12 +#define DBG_CONDITION_DECODE3_STEP3__GROUP_2_OR_ACTIVE___M 0x00000800 +#define DBG_CONDITION_DECODE3_STEP3__GROUP_2_OR_ACTIVE___S 11 +#define DBG_CONDITION_DECODE3_STEP3__GROUP_2_OR_HIGH___M 0x00000400 +#define DBG_CONDITION_DECODE3_STEP3__GROUP_2_OR_HIGH___S 10 +#define DBG_CONDITION_DECODE3_STEP3__GROUP_2_AND_ACTIVE___M 0x00000200 +#define DBG_CONDITION_DECODE3_STEP3__GROUP_2_AND_ACTIVE___S 9 +#define DBG_CONDITION_DECODE3_STEP3__GROUP_2_AND_HIGH___M 0x00000100 +#define DBG_CONDITION_DECODE3_STEP3__GROUP_2_AND_HIGH___S 8 +#define DBG_CONDITION_DECODE3_STEP3__GROUP_1_OR_ACTIVE___M 0x00000080 +#define DBG_CONDITION_DECODE3_STEP3__GROUP_1_OR_ACTIVE___S 7 +#define DBG_CONDITION_DECODE3_STEP3__GROUP_1_OR_HIGH___M 0x00000040 +#define DBG_CONDITION_DECODE3_STEP3__GROUP_1_OR_HIGH___S 6 +#define DBG_CONDITION_DECODE3_STEP3__GROUP_1_AND_ACTIVE___M 0x00000020 +#define DBG_CONDITION_DECODE3_STEP3__GROUP_1_AND_ACTIVE___S 5 +#define DBG_CONDITION_DECODE3_STEP3__GROUP_1_AND_HIGH___M 0x00000010 +#define DBG_CONDITION_DECODE3_STEP3__GROUP_1_AND_HIGH___S 4 +#define DBG_CONDITION_DECODE3_STEP3__GROUP_0_OR_ACTIVE___M 0x00000008 +#define DBG_CONDITION_DECODE3_STEP3__GROUP_0_OR_ACTIVE___S 3 +#define DBG_CONDITION_DECODE3_STEP3__GROUP_0_OR_HIGH___M 0x00000004 +#define DBG_CONDITION_DECODE3_STEP3__GROUP_0_OR_HIGH___S 2 +#define DBG_CONDITION_DECODE3_STEP3__GROUP_0_AND_ACTIVE___M 0x00000002 +#define DBG_CONDITION_DECODE3_STEP3__GROUP_0_AND_ACTIVE___S 1 +#define DBG_CONDITION_DECODE3_STEP3__GROUP_0_AND_HIGH___M 0x00000001 +#define DBG_CONDITION_DECODE3_STEP3__GROUP_0_AND_HIGH___S 0 +#define DBG_CONDITION_DECODE3_STEP4 (0x00BC47BC) +#define DBG_CONDITION_DECODE3_STEP4___RWC QCSR_REG_RW +#define DBG_CONDITION_DECODE3_STEP4__NOT___M 0x01000000 +#define DBG_CONDITION_DECODE3_STEP4__NOT___S 24 +#define DBG_CONDITION_DECODE3_STEP4__BC0_COMP_ACTIVE___M 0x00200000 +#define DBG_CONDITION_DECODE3_STEP4__BC0_COMP_ACTIVE___S 21 +#define DBG_CONDITION_DECODE3_STEP4__BC0_COMP_HIGH___M 0x00100000 +#define DBG_CONDITION_DECODE3_STEP4__BC0_COMP_HIGH___S 20 +#define DBG_CONDITION_DECODE3_STEP4__TC0_COMP_ACTIVE___M 0x00020000 +#define DBG_CONDITION_DECODE3_STEP4__TC0_COMP_ACTIVE___S 17 +#define DBG_CONDITION_DECODE3_STEP4__TC0_COMP_HIGH___M 0x00010000 +#define DBG_CONDITION_DECODE3_STEP4__TC0_COMP_HIGH___S 16 +#define DBG_CONDITION_DECODE3_STEP4__GROUP_3_OR_ACTIVE___M 0x00008000 +#define DBG_CONDITION_DECODE3_STEP4__GROUP_3_OR_ACTIVE___S 15 +#define DBG_CONDITION_DECODE3_STEP4__GROUP_3_OR_HIGH___M 0x00004000 +#define DBG_CONDITION_DECODE3_STEP4__GROUP_3_OR_HIGH___S 14 +#define DBG_CONDITION_DECODE3_STEP4__GROUP_3_AND_ACTIVE___M 0x00002000 +#define DBG_CONDITION_DECODE3_STEP4__GROUP_3_AND_ACTIVE___S 13 +#define DBG_CONDITION_DECODE3_STEP4__GROUP_3_AND_HIGH___M 0x00001000 +#define DBG_CONDITION_DECODE3_STEP4__GROUP_3_AND_HIGH___S 12 +#define DBG_CONDITION_DECODE3_STEP4__GROUP_2_OR_ACTIVE___M 0x00000800 +#define DBG_CONDITION_DECODE3_STEP4__GROUP_2_OR_ACTIVE___S 11 +#define DBG_CONDITION_DECODE3_STEP4__GROUP_2_OR_HIGH___M 0x00000400 +#define DBG_CONDITION_DECODE3_STEP4__GROUP_2_OR_HIGH___S 10 +#define DBG_CONDITION_DECODE3_STEP4__GROUP_2_AND_ACTIVE___M 0x00000200 +#define DBG_CONDITION_DECODE3_STEP4__GROUP_2_AND_ACTIVE___S 9 +#define DBG_CONDITION_DECODE3_STEP4__GROUP_2_AND_HIGH___M 0x00000100 +#define DBG_CONDITION_DECODE3_STEP4__GROUP_2_AND_HIGH___S 8 +#define DBG_CONDITION_DECODE3_STEP4__GROUP_1_OR_ACTIVE___M 0x00000080 +#define DBG_CONDITION_DECODE3_STEP4__GROUP_1_OR_ACTIVE___S 7 +#define DBG_CONDITION_DECODE3_STEP4__GROUP_1_OR_HIGH___M 0x00000040 +#define DBG_CONDITION_DECODE3_STEP4__GROUP_1_OR_HIGH___S 6 +#define DBG_CONDITION_DECODE3_STEP4__GROUP_1_AND_ACTIVE___M 0x00000020 +#define DBG_CONDITION_DECODE3_STEP4__GROUP_1_AND_ACTIVE___S 5 +#define DBG_CONDITION_DECODE3_STEP4__GROUP_1_AND_HIGH___M 0x00000010 +#define DBG_CONDITION_DECODE3_STEP4__GROUP_1_AND_HIGH___S 4 +#define DBG_CONDITION_DECODE3_STEP4__GROUP_0_OR_ACTIVE___M 0x00000008 +#define DBG_CONDITION_DECODE3_STEP4__GROUP_0_OR_ACTIVE___S 3 +#define DBG_CONDITION_DECODE3_STEP4__GROUP_0_OR_HIGH___M 0x00000004 +#define DBG_CONDITION_DECODE3_STEP4__GROUP_0_OR_HIGH___S 2 +#define DBG_CONDITION_DECODE3_STEP4__GROUP_0_AND_ACTIVE___M 0x00000002 +#define DBG_CONDITION_DECODE3_STEP4__GROUP_0_AND_ACTIVE___S 1 +#define DBG_CONDITION_DECODE3_STEP4__GROUP_0_AND_HIGH___M 0x00000001 +#define DBG_CONDITION_DECODE3_STEP4__GROUP_0_AND_HIGH___S 0 +#define DBG_CONDITION_DECODE3_STEP5 (0x00BC4994) +#define DBG_CONDITION_DECODE3_STEP5___RWC QCSR_REG_RW +#define DBG_CONDITION_DECODE3_STEP5__NOT___M 0x01000000 +#define DBG_CONDITION_DECODE3_STEP5__NOT___S 24 +#define DBG_CONDITION_DECODE3_STEP5__BC0_COMP_ACTIVE___M 0x00200000 +#define DBG_CONDITION_DECODE3_STEP5__BC0_COMP_ACTIVE___S 21 +#define DBG_CONDITION_DECODE3_STEP5__BC0_COMP_HIGH___M 0x00100000 +#define DBG_CONDITION_DECODE3_STEP5__BC0_COMP_HIGH___S 20 +#define DBG_CONDITION_DECODE3_STEP5__TC0_COMP_ACTIVE___M 0x00020000 +#define DBG_CONDITION_DECODE3_STEP5__TC0_COMP_ACTIVE___S 17 +#define DBG_CONDITION_DECODE3_STEP5__TC0_COMP_HIGH___M 0x00010000 +#define DBG_CONDITION_DECODE3_STEP5__TC0_COMP_HIGH___S 16 +#define DBG_CONDITION_DECODE3_STEP5__GROUP_3_OR_ACTIVE___M 0x00008000 +#define DBG_CONDITION_DECODE3_STEP5__GROUP_3_OR_ACTIVE___S 15 +#define DBG_CONDITION_DECODE3_STEP5__GROUP_3_OR_HIGH___M 0x00004000 +#define DBG_CONDITION_DECODE3_STEP5__GROUP_3_OR_HIGH___S 14 +#define DBG_CONDITION_DECODE3_STEP5__GROUP_3_AND_ACTIVE___M 0x00002000 +#define DBG_CONDITION_DECODE3_STEP5__GROUP_3_AND_ACTIVE___S 13 +#define DBG_CONDITION_DECODE3_STEP5__GROUP_3_AND_HIGH___M 0x00001000 +#define DBG_CONDITION_DECODE3_STEP5__GROUP_3_AND_HIGH___S 12 +#define DBG_CONDITION_DECODE3_STEP5__GROUP_2_OR_ACTIVE___M 0x00000800 +#define DBG_CONDITION_DECODE3_STEP5__GROUP_2_OR_ACTIVE___S 11 +#define DBG_CONDITION_DECODE3_STEP5__GROUP_2_OR_HIGH___M 0x00000400 +#define DBG_CONDITION_DECODE3_STEP5__GROUP_2_OR_HIGH___S 10 +#define DBG_CONDITION_DECODE3_STEP5__GROUP_2_AND_ACTIVE___M 0x00000200 +#define DBG_CONDITION_DECODE3_STEP5__GROUP_2_AND_ACTIVE___S 9 +#define DBG_CONDITION_DECODE3_STEP5__GROUP_2_AND_HIGH___M 0x00000100 +#define DBG_CONDITION_DECODE3_STEP5__GROUP_2_AND_HIGH___S 8 +#define DBG_CONDITION_DECODE3_STEP5__GROUP_1_OR_ACTIVE___M 0x00000080 +#define DBG_CONDITION_DECODE3_STEP5__GROUP_1_OR_ACTIVE___S 7 +#define DBG_CONDITION_DECODE3_STEP5__GROUP_1_OR_HIGH___M 0x00000040 +#define DBG_CONDITION_DECODE3_STEP5__GROUP_1_OR_HIGH___S 6 +#define DBG_CONDITION_DECODE3_STEP5__GROUP_1_AND_ACTIVE___M 0x00000020 +#define DBG_CONDITION_DECODE3_STEP5__GROUP_1_AND_ACTIVE___S 5 +#define DBG_CONDITION_DECODE3_STEP5__GROUP_1_AND_HIGH___M 0x00000010 +#define DBG_CONDITION_DECODE3_STEP5__GROUP_1_AND_HIGH___S 4 +#define DBG_CONDITION_DECODE3_STEP5__GROUP_0_OR_ACTIVE___M 0x00000008 +#define DBG_CONDITION_DECODE3_STEP5__GROUP_0_OR_ACTIVE___S 3 +#define DBG_CONDITION_DECODE3_STEP5__GROUP_0_OR_HIGH___M 0x00000004 +#define DBG_CONDITION_DECODE3_STEP5__GROUP_0_OR_HIGH___S 2 +#define DBG_CONDITION_DECODE3_STEP5__GROUP_0_AND_ACTIVE___M 0x00000002 +#define DBG_CONDITION_DECODE3_STEP5__GROUP_0_AND_ACTIVE___S 1 +#define DBG_CONDITION_DECODE3_STEP5__GROUP_0_AND_HIGH___M 0x00000001 +#define DBG_CONDITION_DECODE3_STEP5__GROUP_0_AND_HIGH___S 0 +#define DBG_CONDITION_DECODE3_STEP6 (0x00BC4B6C) +#define DBG_CONDITION_DECODE3_STEP6___RWC QCSR_REG_RW +#define DBG_CONDITION_DECODE3_STEP6__NOT___M 0x01000000 +#define DBG_CONDITION_DECODE3_STEP6__NOT___S 24 +#define DBG_CONDITION_DECODE3_STEP6__BC0_COMP_ACTIVE___M 0x00200000 +#define DBG_CONDITION_DECODE3_STEP6__BC0_COMP_ACTIVE___S 21 +#define DBG_CONDITION_DECODE3_STEP6__BC0_COMP_HIGH___M 0x00100000 +#define DBG_CONDITION_DECODE3_STEP6__BC0_COMP_HIGH___S 20 +#define DBG_CONDITION_DECODE3_STEP6__TC0_COMP_ACTIVE___M 0x00020000 +#define DBG_CONDITION_DECODE3_STEP6__TC0_COMP_ACTIVE___S 17 +#define DBG_CONDITION_DECODE3_STEP6__TC0_COMP_HIGH___M 0x00010000 +#define DBG_CONDITION_DECODE3_STEP6__TC0_COMP_HIGH___S 16 +#define DBG_CONDITION_DECODE3_STEP6__GROUP_3_OR_ACTIVE___M 0x00008000 +#define DBG_CONDITION_DECODE3_STEP6__GROUP_3_OR_ACTIVE___S 15 +#define DBG_CONDITION_DECODE3_STEP6__GROUP_3_OR_HIGH___M 0x00004000 +#define DBG_CONDITION_DECODE3_STEP6__GROUP_3_OR_HIGH___S 14 +#define DBG_CONDITION_DECODE3_STEP6__GROUP_3_AND_ACTIVE___M 0x00002000 +#define DBG_CONDITION_DECODE3_STEP6__GROUP_3_AND_ACTIVE___S 13 +#define DBG_CONDITION_DECODE3_STEP6__GROUP_3_AND_HIGH___M 0x00001000 +#define DBG_CONDITION_DECODE3_STEP6__GROUP_3_AND_HIGH___S 12 +#define DBG_CONDITION_DECODE3_STEP6__GROUP_2_OR_ACTIVE___M 0x00000800 +#define DBG_CONDITION_DECODE3_STEP6__GROUP_2_OR_ACTIVE___S 11 +#define DBG_CONDITION_DECODE3_STEP6__GROUP_2_OR_HIGH___M 0x00000400 +#define DBG_CONDITION_DECODE3_STEP6__GROUP_2_OR_HIGH___S 10 +#define DBG_CONDITION_DECODE3_STEP6__GROUP_2_AND_ACTIVE___M 0x00000200 +#define DBG_CONDITION_DECODE3_STEP6__GROUP_2_AND_ACTIVE___S 9 +#define DBG_CONDITION_DECODE3_STEP6__GROUP_2_AND_HIGH___M 0x00000100 +#define DBG_CONDITION_DECODE3_STEP6__GROUP_2_AND_HIGH___S 8 +#define DBG_CONDITION_DECODE3_STEP6__GROUP_1_OR_ACTIVE___M 0x00000080 +#define DBG_CONDITION_DECODE3_STEP6__GROUP_1_OR_ACTIVE___S 7 +#define DBG_CONDITION_DECODE3_STEP6__GROUP_1_OR_HIGH___M 0x00000040 +#define DBG_CONDITION_DECODE3_STEP6__GROUP_1_OR_HIGH___S 6 +#define DBG_CONDITION_DECODE3_STEP6__GROUP_1_AND_ACTIVE___M 0x00000020 +#define DBG_CONDITION_DECODE3_STEP6__GROUP_1_AND_ACTIVE___S 5 +#define DBG_CONDITION_DECODE3_STEP6__GROUP_1_AND_HIGH___M 0x00000010 +#define DBG_CONDITION_DECODE3_STEP6__GROUP_1_AND_HIGH___S 4 +#define DBG_CONDITION_DECODE3_STEP6__GROUP_0_OR_ACTIVE___M 0x00000008 +#define DBG_CONDITION_DECODE3_STEP6__GROUP_0_OR_ACTIVE___S 3 +#define DBG_CONDITION_DECODE3_STEP6__GROUP_0_OR_HIGH___M 0x00000004 +#define DBG_CONDITION_DECODE3_STEP6__GROUP_0_OR_HIGH___S 2 +#define DBG_CONDITION_DECODE3_STEP6__GROUP_0_AND_ACTIVE___M 0x00000002 +#define DBG_CONDITION_DECODE3_STEP6__GROUP_0_AND_ACTIVE___S 1 +#define DBG_CONDITION_DECODE3_STEP6__GROUP_0_AND_HIGH___M 0x00000001 +#define DBG_CONDITION_DECODE3_STEP6__GROUP_0_AND_HIGH___S 0 +#define DBG_CONDITION_DECODE3_STEP7 (0x00BC4D44) +#define DBG_CONDITION_DECODE3_STEP7___RWC QCSR_REG_RW +#define DBG_CONDITION_DECODE3_STEP7__NOT___M 0x01000000 +#define DBG_CONDITION_DECODE3_STEP7__NOT___S 24 +#define DBG_CONDITION_DECODE3_STEP7__BC0_COMP_ACTIVE___M 0x00200000 +#define DBG_CONDITION_DECODE3_STEP7__BC0_COMP_ACTIVE___S 21 +#define DBG_CONDITION_DECODE3_STEP7__BC0_COMP_HIGH___M 0x00100000 +#define DBG_CONDITION_DECODE3_STEP7__BC0_COMP_HIGH___S 20 +#define DBG_CONDITION_DECODE3_STEP7__TC0_COMP_ACTIVE___M 0x00020000 +#define DBG_CONDITION_DECODE3_STEP7__TC0_COMP_ACTIVE___S 17 +#define DBG_CONDITION_DECODE3_STEP7__TC0_COMP_HIGH___M 0x00010000 +#define DBG_CONDITION_DECODE3_STEP7__TC0_COMP_HIGH___S 16 +#define DBG_CONDITION_DECODE3_STEP7__GROUP_3_OR_ACTIVE___M 0x00008000 +#define DBG_CONDITION_DECODE3_STEP7__GROUP_3_OR_ACTIVE___S 15 +#define DBG_CONDITION_DECODE3_STEP7__GROUP_3_OR_HIGH___M 0x00004000 +#define DBG_CONDITION_DECODE3_STEP7__GROUP_3_OR_HIGH___S 14 +#define DBG_CONDITION_DECODE3_STEP7__GROUP_3_AND_ACTIVE___M 0x00002000 +#define DBG_CONDITION_DECODE3_STEP7__GROUP_3_AND_ACTIVE___S 13 +#define DBG_CONDITION_DECODE3_STEP7__GROUP_3_AND_HIGH___M 0x00001000 +#define DBG_CONDITION_DECODE3_STEP7__GROUP_3_AND_HIGH___S 12 +#define DBG_CONDITION_DECODE3_STEP7__GROUP_2_OR_ACTIVE___M 0x00000800 +#define DBG_CONDITION_DECODE3_STEP7__GROUP_2_OR_ACTIVE___S 11 +#define DBG_CONDITION_DECODE3_STEP7__GROUP_2_OR_HIGH___M 0x00000400 +#define DBG_CONDITION_DECODE3_STEP7__GROUP_2_OR_HIGH___S 10 +#define DBG_CONDITION_DECODE3_STEP7__GROUP_2_AND_ACTIVE___M 0x00000200 +#define DBG_CONDITION_DECODE3_STEP7__GROUP_2_AND_ACTIVE___S 9 +#define DBG_CONDITION_DECODE3_STEP7__GROUP_2_AND_HIGH___M 0x00000100 +#define DBG_CONDITION_DECODE3_STEP7__GROUP_2_AND_HIGH___S 8 +#define DBG_CONDITION_DECODE3_STEP7__GROUP_1_OR_ACTIVE___M 0x00000080 +#define DBG_CONDITION_DECODE3_STEP7__GROUP_1_OR_ACTIVE___S 7 +#define DBG_CONDITION_DECODE3_STEP7__GROUP_1_OR_HIGH___M 0x00000040 +#define DBG_CONDITION_DECODE3_STEP7__GROUP_1_OR_HIGH___S 6 +#define DBG_CONDITION_DECODE3_STEP7__GROUP_1_AND_ACTIVE___M 0x00000020 +#define DBG_CONDITION_DECODE3_STEP7__GROUP_1_AND_ACTIVE___S 5 +#define DBG_CONDITION_DECODE3_STEP7__GROUP_1_AND_HIGH___M 0x00000010 +#define DBG_CONDITION_DECODE3_STEP7__GROUP_1_AND_HIGH___S 4 +#define DBG_CONDITION_DECODE3_STEP7__GROUP_0_OR_ACTIVE___M 0x00000008 +#define DBG_CONDITION_DECODE3_STEP7__GROUP_0_OR_ACTIVE___S 3 +#define DBG_CONDITION_DECODE3_STEP7__GROUP_0_OR_HIGH___M 0x00000004 +#define DBG_CONDITION_DECODE3_STEP7__GROUP_0_OR_HIGH___S 2 +#define DBG_CONDITION_DECODE3_STEP7__GROUP_0_AND_ACTIVE___M 0x00000002 +#define DBG_CONDITION_DECODE3_STEP7__GROUP_0_AND_ACTIVE___S 1 +#define DBG_CONDITION_DECODE3_STEP7__GROUP_0_AND_HIGH___M 0x00000001 +#define DBG_CONDITION_DECODE3_STEP7__GROUP_0_AND_HIGH___S 0 + +#define DBG_CONDITION_SELECTm_STEPn(m,n) (0x00BC4060+0x4*(m)+0x1D8*(n)) +#define DBG_CONDITION_SELECTm_STEPn_mMIN 0 +#define DBG_CONDITION_SELECTm_STEPn_mMAX 3 +#define DBG_CONDITION_SELECTm_STEPn_nMIN 0 +#define DBG_CONDITION_SELECTm_STEPn_nMAX 7 +#define DBG_CONDITION_SELECTm_STEPn_ELEM 32 +#define DBG_CONDITION_SELECTm_STEPn___RWC QCSR_REG_RW +#define DBG_CONDITION_SELECTm_STEPn___POR 0x00000000 +#define DBG_CONDITION_SELECTm_STEPn__NEXT_STEP___POR 0x0 +#define DBG_CONDITION_SELECTm_STEPn__TRIGGER___POR 0x0 +#define DBG_CONDITION_SELECTm_STEPn__BC0_INC___POR 0x0 +#define DBG_CONDITION_SELECTm_STEPn__BC0_DEC___POR 0x0 +#define DBG_CONDITION_SELECTm_STEPn__BC0_CLEAR___POR 0x0 +#define DBG_CONDITION_SELECTm_STEPn__TC0_ENABLE___POR 0x0 +#define DBG_CONDITION_SELECTm_STEPn__TC0_PAUSE___POR 0x0 +#define DBG_CONDITION_SELECTm_STEPn__TC0_CLEAR___POR 0x0 +#define DBG_CONDITION_SELECTm_STEPn__DONE___POR 0x0 +#define DBG_CONDITION_SELECTm_STEPn__NEXT_STEP___M 0x000E0000 +#define DBG_CONDITION_SELECTm_STEPn__NEXT_STEP___S 17 +#define DBG_CONDITION_SELECTm_STEPn__TRIGGER___M 0x0001E000 +#define DBG_CONDITION_SELECTm_STEPn__TRIGGER___S 13 +#define DBG_CONDITION_SELECTm_STEPn__BC0_INC___M 0x00000200 +#define DBG_CONDITION_SELECTm_STEPn__BC0_INC___S 9 +#define DBG_CONDITION_SELECTm_STEPn__BC0_DEC___M 0x00000100 +#define DBG_CONDITION_SELECTm_STEPn__BC0_DEC___S 8 +#define DBG_CONDITION_SELECTm_STEPn__BC0_CLEAR___M 0x00000080 +#define DBG_CONDITION_SELECTm_STEPn__BC0_CLEAR___S 7 +#define DBG_CONDITION_SELECTm_STEPn__TC0_ENABLE___M 0x00000008 +#define DBG_CONDITION_SELECTm_STEPn__TC0_ENABLE___S 3 +#define DBG_CONDITION_SELECTm_STEPn__TC0_PAUSE___M 0x00000004 +#define DBG_CONDITION_SELECTm_STEPn__TC0_PAUSE___S 2 +#define DBG_CONDITION_SELECTm_STEPn__TC0_CLEAR___M 0x00000002 +#define DBG_CONDITION_SELECTm_STEPn__TC0_CLEAR___S 1 +#define DBG_CONDITION_SELECTm_STEPn__DONE___M 0x00000001 +#define DBG_CONDITION_SELECTm_STEPn__DONE___S 0 +#define DBG_CONDITION_SELECTm_STEPn___M 0x000FE38F +#define DBG_CONDITION_SELECTm_STEPn___S 0 +#define DBG_CONDITION_SELECT0_STEP0 (0x00BC4060) +#define DBG_CONDITION_SELECT0_STEP0___RWC QCSR_REG_RW +#define DBG_CONDITION_SELECT0_STEP0__NEXT_STEP___M 0x000E0000 +#define DBG_CONDITION_SELECT0_STEP0__NEXT_STEP___S 17 +#define DBG_CONDITION_SELECT0_STEP0__TRIGGER___M 0x0001E000 +#define DBG_CONDITION_SELECT0_STEP0__TRIGGER___S 13 +#define DBG_CONDITION_SELECT0_STEP0__BC0_INC___M 0x00000200 +#define DBG_CONDITION_SELECT0_STEP0__BC0_INC___S 9 +#define DBG_CONDITION_SELECT0_STEP0__BC0_DEC___M 0x00000100 +#define DBG_CONDITION_SELECT0_STEP0__BC0_DEC___S 8 +#define DBG_CONDITION_SELECT0_STEP0__BC0_CLEAR___M 0x00000080 +#define DBG_CONDITION_SELECT0_STEP0__BC0_CLEAR___S 7 +#define DBG_CONDITION_SELECT0_STEP0__TC0_ENABLE___M 0x00000008 +#define DBG_CONDITION_SELECT0_STEP0__TC0_ENABLE___S 3 +#define DBG_CONDITION_SELECT0_STEP0__TC0_PAUSE___M 0x00000004 +#define DBG_CONDITION_SELECT0_STEP0__TC0_PAUSE___S 2 +#define DBG_CONDITION_SELECT0_STEP0__TC0_CLEAR___M 0x00000002 +#define DBG_CONDITION_SELECT0_STEP0__TC0_CLEAR___S 1 +#define DBG_CONDITION_SELECT0_STEP0__DONE___M 0x00000001 +#define DBG_CONDITION_SELECT0_STEP0__DONE___S 0 +#define DBG_CONDITION_SELECT0_STEP1 (0x00BC4238) +#define DBG_CONDITION_SELECT0_STEP1___RWC QCSR_REG_RW +#define DBG_CONDITION_SELECT0_STEP1__NEXT_STEP___M 0x000E0000 +#define DBG_CONDITION_SELECT0_STEP1__NEXT_STEP___S 17 +#define DBG_CONDITION_SELECT0_STEP1__TRIGGER___M 0x0001E000 +#define DBG_CONDITION_SELECT0_STEP1__TRIGGER___S 13 +#define DBG_CONDITION_SELECT0_STEP1__BC0_INC___M 0x00000200 +#define DBG_CONDITION_SELECT0_STEP1__BC0_INC___S 9 +#define DBG_CONDITION_SELECT0_STEP1__BC0_DEC___M 0x00000100 +#define DBG_CONDITION_SELECT0_STEP1__BC0_DEC___S 8 +#define DBG_CONDITION_SELECT0_STEP1__BC0_CLEAR___M 0x00000080 +#define DBG_CONDITION_SELECT0_STEP1__BC0_CLEAR___S 7 +#define DBG_CONDITION_SELECT0_STEP1__TC0_ENABLE___M 0x00000008 +#define DBG_CONDITION_SELECT0_STEP1__TC0_ENABLE___S 3 +#define DBG_CONDITION_SELECT0_STEP1__TC0_PAUSE___M 0x00000004 +#define DBG_CONDITION_SELECT0_STEP1__TC0_PAUSE___S 2 +#define DBG_CONDITION_SELECT0_STEP1__TC0_CLEAR___M 0x00000002 +#define DBG_CONDITION_SELECT0_STEP1__TC0_CLEAR___S 1 +#define DBG_CONDITION_SELECT0_STEP1__DONE___M 0x00000001 +#define DBG_CONDITION_SELECT0_STEP1__DONE___S 0 +#define DBG_CONDITION_SELECT0_STEP2 (0x00BC4410) +#define DBG_CONDITION_SELECT0_STEP2___RWC QCSR_REG_RW +#define DBG_CONDITION_SELECT0_STEP2__NEXT_STEP___M 0x000E0000 +#define DBG_CONDITION_SELECT0_STEP2__NEXT_STEP___S 17 +#define DBG_CONDITION_SELECT0_STEP2__TRIGGER___M 0x0001E000 +#define DBG_CONDITION_SELECT0_STEP2__TRIGGER___S 13 +#define DBG_CONDITION_SELECT0_STEP2__BC0_INC___M 0x00000200 +#define DBG_CONDITION_SELECT0_STEP2__BC0_INC___S 9 +#define DBG_CONDITION_SELECT0_STEP2__BC0_DEC___M 0x00000100 +#define DBG_CONDITION_SELECT0_STEP2__BC0_DEC___S 8 +#define DBG_CONDITION_SELECT0_STEP2__BC0_CLEAR___M 0x00000080 +#define DBG_CONDITION_SELECT0_STEP2__BC0_CLEAR___S 7 +#define DBG_CONDITION_SELECT0_STEP2__TC0_ENABLE___M 0x00000008 +#define DBG_CONDITION_SELECT0_STEP2__TC0_ENABLE___S 3 +#define DBG_CONDITION_SELECT0_STEP2__TC0_PAUSE___M 0x00000004 +#define DBG_CONDITION_SELECT0_STEP2__TC0_PAUSE___S 2 +#define DBG_CONDITION_SELECT0_STEP2__TC0_CLEAR___M 0x00000002 +#define DBG_CONDITION_SELECT0_STEP2__TC0_CLEAR___S 1 +#define DBG_CONDITION_SELECT0_STEP2__DONE___M 0x00000001 +#define DBG_CONDITION_SELECT0_STEP2__DONE___S 0 +#define DBG_CONDITION_SELECT0_STEP3 (0x00BC45E8) +#define DBG_CONDITION_SELECT0_STEP3___RWC QCSR_REG_RW +#define DBG_CONDITION_SELECT0_STEP3__NEXT_STEP___M 0x000E0000 +#define DBG_CONDITION_SELECT0_STEP3__NEXT_STEP___S 17 +#define DBG_CONDITION_SELECT0_STEP3__TRIGGER___M 0x0001E000 +#define DBG_CONDITION_SELECT0_STEP3__TRIGGER___S 13 +#define DBG_CONDITION_SELECT0_STEP3__BC0_INC___M 0x00000200 +#define DBG_CONDITION_SELECT0_STEP3__BC0_INC___S 9 +#define DBG_CONDITION_SELECT0_STEP3__BC0_DEC___M 0x00000100 +#define DBG_CONDITION_SELECT0_STEP3__BC0_DEC___S 8 +#define DBG_CONDITION_SELECT0_STEP3__BC0_CLEAR___M 0x00000080 +#define DBG_CONDITION_SELECT0_STEP3__BC0_CLEAR___S 7 +#define DBG_CONDITION_SELECT0_STEP3__TC0_ENABLE___M 0x00000008 +#define DBG_CONDITION_SELECT0_STEP3__TC0_ENABLE___S 3 +#define DBG_CONDITION_SELECT0_STEP3__TC0_PAUSE___M 0x00000004 +#define DBG_CONDITION_SELECT0_STEP3__TC0_PAUSE___S 2 +#define DBG_CONDITION_SELECT0_STEP3__TC0_CLEAR___M 0x00000002 +#define DBG_CONDITION_SELECT0_STEP3__TC0_CLEAR___S 1 +#define DBG_CONDITION_SELECT0_STEP3__DONE___M 0x00000001 +#define DBG_CONDITION_SELECT0_STEP3__DONE___S 0 +#define DBG_CONDITION_SELECT0_STEP4 (0x00BC47C0) +#define DBG_CONDITION_SELECT0_STEP4___RWC QCSR_REG_RW +#define DBG_CONDITION_SELECT0_STEP4__NEXT_STEP___M 0x000E0000 +#define DBG_CONDITION_SELECT0_STEP4__NEXT_STEP___S 17 +#define DBG_CONDITION_SELECT0_STEP4__TRIGGER___M 0x0001E000 +#define DBG_CONDITION_SELECT0_STEP4__TRIGGER___S 13 +#define DBG_CONDITION_SELECT0_STEP4__BC0_INC___M 0x00000200 +#define DBG_CONDITION_SELECT0_STEP4__BC0_INC___S 9 +#define DBG_CONDITION_SELECT0_STEP4__BC0_DEC___M 0x00000100 +#define DBG_CONDITION_SELECT0_STEP4__BC0_DEC___S 8 +#define DBG_CONDITION_SELECT0_STEP4__BC0_CLEAR___M 0x00000080 +#define DBG_CONDITION_SELECT0_STEP4__BC0_CLEAR___S 7 +#define DBG_CONDITION_SELECT0_STEP4__TC0_ENABLE___M 0x00000008 +#define DBG_CONDITION_SELECT0_STEP4__TC0_ENABLE___S 3 +#define DBG_CONDITION_SELECT0_STEP4__TC0_PAUSE___M 0x00000004 +#define DBG_CONDITION_SELECT0_STEP4__TC0_PAUSE___S 2 +#define DBG_CONDITION_SELECT0_STEP4__TC0_CLEAR___M 0x00000002 +#define DBG_CONDITION_SELECT0_STEP4__TC0_CLEAR___S 1 +#define DBG_CONDITION_SELECT0_STEP4__DONE___M 0x00000001 +#define DBG_CONDITION_SELECT0_STEP4__DONE___S 0 +#define DBG_CONDITION_SELECT0_STEP5 (0x00BC4998) +#define DBG_CONDITION_SELECT0_STEP5___RWC QCSR_REG_RW +#define DBG_CONDITION_SELECT0_STEP5__NEXT_STEP___M 0x000E0000 +#define DBG_CONDITION_SELECT0_STEP5__NEXT_STEP___S 17 +#define DBG_CONDITION_SELECT0_STEP5__TRIGGER___M 0x0001E000 +#define DBG_CONDITION_SELECT0_STEP5__TRIGGER___S 13 +#define DBG_CONDITION_SELECT0_STEP5__BC0_INC___M 0x00000200 +#define DBG_CONDITION_SELECT0_STEP5__BC0_INC___S 9 +#define DBG_CONDITION_SELECT0_STEP5__BC0_DEC___M 0x00000100 +#define DBG_CONDITION_SELECT0_STEP5__BC0_DEC___S 8 +#define DBG_CONDITION_SELECT0_STEP5__BC0_CLEAR___M 0x00000080 +#define DBG_CONDITION_SELECT0_STEP5__BC0_CLEAR___S 7 +#define DBG_CONDITION_SELECT0_STEP5__TC0_ENABLE___M 0x00000008 +#define DBG_CONDITION_SELECT0_STEP5__TC0_ENABLE___S 3 +#define DBG_CONDITION_SELECT0_STEP5__TC0_PAUSE___M 0x00000004 +#define DBG_CONDITION_SELECT0_STEP5__TC0_PAUSE___S 2 +#define DBG_CONDITION_SELECT0_STEP5__TC0_CLEAR___M 0x00000002 +#define DBG_CONDITION_SELECT0_STEP5__TC0_CLEAR___S 1 +#define DBG_CONDITION_SELECT0_STEP5__DONE___M 0x00000001 +#define DBG_CONDITION_SELECT0_STEP5__DONE___S 0 +#define DBG_CONDITION_SELECT0_STEP6 (0x00BC4B70) +#define DBG_CONDITION_SELECT0_STEP6___RWC QCSR_REG_RW +#define DBG_CONDITION_SELECT0_STEP6__NEXT_STEP___M 0x000E0000 +#define DBG_CONDITION_SELECT0_STEP6__NEXT_STEP___S 17 +#define DBG_CONDITION_SELECT0_STEP6__TRIGGER___M 0x0001E000 +#define DBG_CONDITION_SELECT0_STEP6__TRIGGER___S 13 +#define DBG_CONDITION_SELECT0_STEP6__BC0_INC___M 0x00000200 +#define DBG_CONDITION_SELECT0_STEP6__BC0_INC___S 9 +#define DBG_CONDITION_SELECT0_STEP6__BC0_DEC___M 0x00000100 +#define DBG_CONDITION_SELECT0_STEP6__BC0_DEC___S 8 +#define DBG_CONDITION_SELECT0_STEP6__BC0_CLEAR___M 0x00000080 +#define DBG_CONDITION_SELECT0_STEP6__BC0_CLEAR___S 7 +#define DBG_CONDITION_SELECT0_STEP6__TC0_ENABLE___M 0x00000008 +#define DBG_CONDITION_SELECT0_STEP6__TC0_ENABLE___S 3 +#define DBG_CONDITION_SELECT0_STEP6__TC0_PAUSE___M 0x00000004 +#define DBG_CONDITION_SELECT0_STEP6__TC0_PAUSE___S 2 +#define DBG_CONDITION_SELECT0_STEP6__TC0_CLEAR___M 0x00000002 +#define DBG_CONDITION_SELECT0_STEP6__TC0_CLEAR___S 1 +#define DBG_CONDITION_SELECT0_STEP6__DONE___M 0x00000001 +#define DBG_CONDITION_SELECT0_STEP6__DONE___S 0 +#define DBG_CONDITION_SELECT0_STEP7 (0x00BC4D48) +#define DBG_CONDITION_SELECT0_STEP7___RWC QCSR_REG_RW +#define DBG_CONDITION_SELECT0_STEP7__NEXT_STEP___M 0x000E0000 +#define DBG_CONDITION_SELECT0_STEP7__NEXT_STEP___S 17 +#define DBG_CONDITION_SELECT0_STEP7__TRIGGER___M 0x0001E000 +#define DBG_CONDITION_SELECT0_STEP7__TRIGGER___S 13 +#define DBG_CONDITION_SELECT0_STEP7__BC0_INC___M 0x00000200 +#define DBG_CONDITION_SELECT0_STEP7__BC0_INC___S 9 +#define DBG_CONDITION_SELECT0_STEP7__BC0_DEC___M 0x00000100 +#define DBG_CONDITION_SELECT0_STEP7__BC0_DEC___S 8 +#define DBG_CONDITION_SELECT0_STEP7__BC0_CLEAR___M 0x00000080 +#define DBG_CONDITION_SELECT0_STEP7__BC0_CLEAR___S 7 +#define DBG_CONDITION_SELECT0_STEP7__TC0_ENABLE___M 0x00000008 +#define DBG_CONDITION_SELECT0_STEP7__TC0_ENABLE___S 3 +#define DBG_CONDITION_SELECT0_STEP7__TC0_PAUSE___M 0x00000004 +#define DBG_CONDITION_SELECT0_STEP7__TC0_PAUSE___S 2 +#define DBG_CONDITION_SELECT0_STEP7__TC0_CLEAR___M 0x00000002 +#define DBG_CONDITION_SELECT0_STEP7__TC0_CLEAR___S 1 +#define DBG_CONDITION_SELECT0_STEP7__DONE___M 0x00000001 +#define DBG_CONDITION_SELECT0_STEP7__DONE___S 0 +#define DBG_CONDITION_SELECT1_STEP0 (0x00BC4064) +#define DBG_CONDITION_SELECT1_STEP0___RWC QCSR_REG_RW +#define DBG_CONDITION_SELECT1_STEP0__NEXT_STEP___M 0x000E0000 +#define DBG_CONDITION_SELECT1_STEP0__NEXT_STEP___S 17 +#define DBG_CONDITION_SELECT1_STEP0__TRIGGER___M 0x0001E000 +#define DBG_CONDITION_SELECT1_STEP0__TRIGGER___S 13 +#define DBG_CONDITION_SELECT1_STEP0__BC0_INC___M 0x00000200 +#define DBG_CONDITION_SELECT1_STEP0__BC0_INC___S 9 +#define DBG_CONDITION_SELECT1_STEP0__BC0_DEC___M 0x00000100 +#define DBG_CONDITION_SELECT1_STEP0__BC0_DEC___S 8 +#define DBG_CONDITION_SELECT1_STEP0__BC0_CLEAR___M 0x00000080 +#define DBG_CONDITION_SELECT1_STEP0__BC0_CLEAR___S 7 +#define DBG_CONDITION_SELECT1_STEP0__TC0_ENABLE___M 0x00000008 +#define DBG_CONDITION_SELECT1_STEP0__TC0_ENABLE___S 3 +#define DBG_CONDITION_SELECT1_STEP0__TC0_PAUSE___M 0x00000004 +#define DBG_CONDITION_SELECT1_STEP0__TC0_PAUSE___S 2 +#define DBG_CONDITION_SELECT1_STEP0__TC0_CLEAR___M 0x00000002 +#define DBG_CONDITION_SELECT1_STEP0__TC0_CLEAR___S 1 +#define DBG_CONDITION_SELECT1_STEP0__DONE___M 0x00000001 +#define DBG_CONDITION_SELECT1_STEP0__DONE___S 0 +#define DBG_CONDITION_SELECT1_STEP1 (0x00BC423C) +#define DBG_CONDITION_SELECT1_STEP1___RWC QCSR_REG_RW +#define DBG_CONDITION_SELECT1_STEP1__NEXT_STEP___M 0x000E0000 +#define DBG_CONDITION_SELECT1_STEP1__NEXT_STEP___S 17 +#define DBG_CONDITION_SELECT1_STEP1__TRIGGER___M 0x0001E000 +#define DBG_CONDITION_SELECT1_STEP1__TRIGGER___S 13 +#define DBG_CONDITION_SELECT1_STEP1__BC0_INC___M 0x00000200 +#define DBG_CONDITION_SELECT1_STEP1__BC0_INC___S 9 +#define DBG_CONDITION_SELECT1_STEP1__BC0_DEC___M 0x00000100 +#define DBG_CONDITION_SELECT1_STEP1__BC0_DEC___S 8 +#define DBG_CONDITION_SELECT1_STEP1__BC0_CLEAR___M 0x00000080 +#define DBG_CONDITION_SELECT1_STEP1__BC0_CLEAR___S 7 +#define DBG_CONDITION_SELECT1_STEP1__TC0_ENABLE___M 0x00000008 +#define DBG_CONDITION_SELECT1_STEP1__TC0_ENABLE___S 3 +#define DBG_CONDITION_SELECT1_STEP1__TC0_PAUSE___M 0x00000004 +#define DBG_CONDITION_SELECT1_STEP1__TC0_PAUSE___S 2 +#define DBG_CONDITION_SELECT1_STEP1__TC0_CLEAR___M 0x00000002 +#define DBG_CONDITION_SELECT1_STEP1__TC0_CLEAR___S 1 +#define DBG_CONDITION_SELECT1_STEP1__DONE___M 0x00000001 +#define DBG_CONDITION_SELECT1_STEP1__DONE___S 0 +#define DBG_CONDITION_SELECT1_STEP2 (0x00BC4414) +#define DBG_CONDITION_SELECT1_STEP2___RWC QCSR_REG_RW +#define DBG_CONDITION_SELECT1_STEP2__NEXT_STEP___M 0x000E0000 +#define DBG_CONDITION_SELECT1_STEP2__NEXT_STEP___S 17 +#define DBG_CONDITION_SELECT1_STEP2__TRIGGER___M 0x0001E000 +#define DBG_CONDITION_SELECT1_STEP2__TRIGGER___S 13 +#define DBG_CONDITION_SELECT1_STEP2__BC0_INC___M 0x00000200 +#define DBG_CONDITION_SELECT1_STEP2__BC0_INC___S 9 +#define DBG_CONDITION_SELECT1_STEP2__BC0_DEC___M 0x00000100 +#define DBG_CONDITION_SELECT1_STEP2__BC0_DEC___S 8 +#define DBG_CONDITION_SELECT1_STEP2__BC0_CLEAR___M 0x00000080 +#define DBG_CONDITION_SELECT1_STEP2__BC0_CLEAR___S 7 +#define DBG_CONDITION_SELECT1_STEP2__TC0_ENABLE___M 0x00000008 +#define DBG_CONDITION_SELECT1_STEP2__TC0_ENABLE___S 3 +#define DBG_CONDITION_SELECT1_STEP2__TC0_PAUSE___M 0x00000004 +#define DBG_CONDITION_SELECT1_STEP2__TC0_PAUSE___S 2 +#define DBG_CONDITION_SELECT1_STEP2__TC0_CLEAR___M 0x00000002 +#define DBG_CONDITION_SELECT1_STEP2__TC0_CLEAR___S 1 +#define DBG_CONDITION_SELECT1_STEP2__DONE___M 0x00000001 +#define DBG_CONDITION_SELECT1_STEP2__DONE___S 0 +#define DBG_CONDITION_SELECT1_STEP3 (0x00BC45EC) +#define DBG_CONDITION_SELECT1_STEP3___RWC QCSR_REG_RW +#define DBG_CONDITION_SELECT1_STEP3__NEXT_STEP___M 0x000E0000 +#define DBG_CONDITION_SELECT1_STEP3__NEXT_STEP___S 17 +#define DBG_CONDITION_SELECT1_STEP3__TRIGGER___M 0x0001E000 +#define DBG_CONDITION_SELECT1_STEP3__TRIGGER___S 13 +#define DBG_CONDITION_SELECT1_STEP3__BC0_INC___M 0x00000200 +#define DBG_CONDITION_SELECT1_STEP3__BC0_INC___S 9 +#define DBG_CONDITION_SELECT1_STEP3__BC0_DEC___M 0x00000100 +#define DBG_CONDITION_SELECT1_STEP3__BC0_DEC___S 8 +#define DBG_CONDITION_SELECT1_STEP3__BC0_CLEAR___M 0x00000080 +#define DBG_CONDITION_SELECT1_STEP3__BC0_CLEAR___S 7 +#define DBG_CONDITION_SELECT1_STEP3__TC0_ENABLE___M 0x00000008 +#define DBG_CONDITION_SELECT1_STEP3__TC0_ENABLE___S 3 +#define DBG_CONDITION_SELECT1_STEP3__TC0_PAUSE___M 0x00000004 +#define DBG_CONDITION_SELECT1_STEP3__TC0_PAUSE___S 2 +#define DBG_CONDITION_SELECT1_STEP3__TC0_CLEAR___M 0x00000002 +#define DBG_CONDITION_SELECT1_STEP3__TC0_CLEAR___S 1 +#define DBG_CONDITION_SELECT1_STEP3__DONE___M 0x00000001 +#define DBG_CONDITION_SELECT1_STEP3__DONE___S 0 +#define DBG_CONDITION_SELECT1_STEP4 (0x00BC47C4) +#define DBG_CONDITION_SELECT1_STEP4___RWC QCSR_REG_RW +#define DBG_CONDITION_SELECT1_STEP4__NEXT_STEP___M 0x000E0000 +#define DBG_CONDITION_SELECT1_STEP4__NEXT_STEP___S 17 +#define DBG_CONDITION_SELECT1_STEP4__TRIGGER___M 0x0001E000 +#define DBG_CONDITION_SELECT1_STEP4__TRIGGER___S 13 +#define DBG_CONDITION_SELECT1_STEP4__BC0_INC___M 0x00000200 +#define DBG_CONDITION_SELECT1_STEP4__BC0_INC___S 9 +#define DBG_CONDITION_SELECT1_STEP4__BC0_DEC___M 0x00000100 +#define DBG_CONDITION_SELECT1_STEP4__BC0_DEC___S 8 +#define DBG_CONDITION_SELECT1_STEP4__BC0_CLEAR___M 0x00000080 +#define DBG_CONDITION_SELECT1_STEP4__BC0_CLEAR___S 7 +#define DBG_CONDITION_SELECT1_STEP4__TC0_ENABLE___M 0x00000008 +#define DBG_CONDITION_SELECT1_STEP4__TC0_ENABLE___S 3 +#define DBG_CONDITION_SELECT1_STEP4__TC0_PAUSE___M 0x00000004 +#define DBG_CONDITION_SELECT1_STEP4__TC0_PAUSE___S 2 +#define DBG_CONDITION_SELECT1_STEP4__TC0_CLEAR___M 0x00000002 +#define DBG_CONDITION_SELECT1_STEP4__TC0_CLEAR___S 1 +#define DBG_CONDITION_SELECT1_STEP4__DONE___M 0x00000001 +#define DBG_CONDITION_SELECT1_STEP4__DONE___S 0 +#define DBG_CONDITION_SELECT1_STEP5 (0x00BC499C) +#define DBG_CONDITION_SELECT1_STEP5___RWC QCSR_REG_RW +#define DBG_CONDITION_SELECT1_STEP5__NEXT_STEP___M 0x000E0000 +#define DBG_CONDITION_SELECT1_STEP5__NEXT_STEP___S 17 +#define DBG_CONDITION_SELECT1_STEP5__TRIGGER___M 0x0001E000 +#define DBG_CONDITION_SELECT1_STEP5__TRIGGER___S 13 +#define DBG_CONDITION_SELECT1_STEP5__BC0_INC___M 0x00000200 +#define DBG_CONDITION_SELECT1_STEP5__BC0_INC___S 9 +#define DBG_CONDITION_SELECT1_STEP5__BC0_DEC___M 0x00000100 +#define DBG_CONDITION_SELECT1_STEP5__BC0_DEC___S 8 +#define DBG_CONDITION_SELECT1_STEP5__BC0_CLEAR___M 0x00000080 +#define DBG_CONDITION_SELECT1_STEP5__BC0_CLEAR___S 7 +#define DBG_CONDITION_SELECT1_STEP5__TC0_ENABLE___M 0x00000008 +#define DBG_CONDITION_SELECT1_STEP5__TC0_ENABLE___S 3 +#define DBG_CONDITION_SELECT1_STEP5__TC0_PAUSE___M 0x00000004 +#define DBG_CONDITION_SELECT1_STEP5__TC0_PAUSE___S 2 +#define DBG_CONDITION_SELECT1_STEP5__TC0_CLEAR___M 0x00000002 +#define DBG_CONDITION_SELECT1_STEP5__TC0_CLEAR___S 1 +#define DBG_CONDITION_SELECT1_STEP5__DONE___M 0x00000001 +#define DBG_CONDITION_SELECT1_STEP5__DONE___S 0 +#define DBG_CONDITION_SELECT1_STEP6 (0x00BC4B74) +#define DBG_CONDITION_SELECT1_STEP6___RWC QCSR_REG_RW +#define DBG_CONDITION_SELECT1_STEP6__NEXT_STEP___M 0x000E0000 +#define DBG_CONDITION_SELECT1_STEP6__NEXT_STEP___S 17 +#define DBG_CONDITION_SELECT1_STEP6__TRIGGER___M 0x0001E000 +#define DBG_CONDITION_SELECT1_STEP6__TRIGGER___S 13 +#define DBG_CONDITION_SELECT1_STEP6__BC0_INC___M 0x00000200 +#define DBG_CONDITION_SELECT1_STEP6__BC0_INC___S 9 +#define DBG_CONDITION_SELECT1_STEP6__BC0_DEC___M 0x00000100 +#define DBG_CONDITION_SELECT1_STEP6__BC0_DEC___S 8 +#define DBG_CONDITION_SELECT1_STEP6__BC0_CLEAR___M 0x00000080 +#define DBG_CONDITION_SELECT1_STEP6__BC0_CLEAR___S 7 +#define DBG_CONDITION_SELECT1_STEP6__TC0_ENABLE___M 0x00000008 +#define DBG_CONDITION_SELECT1_STEP6__TC0_ENABLE___S 3 +#define DBG_CONDITION_SELECT1_STEP6__TC0_PAUSE___M 0x00000004 +#define DBG_CONDITION_SELECT1_STEP6__TC0_PAUSE___S 2 +#define DBG_CONDITION_SELECT1_STEP6__TC0_CLEAR___M 0x00000002 +#define DBG_CONDITION_SELECT1_STEP6__TC0_CLEAR___S 1 +#define DBG_CONDITION_SELECT1_STEP6__DONE___M 0x00000001 +#define DBG_CONDITION_SELECT1_STEP6__DONE___S 0 +#define DBG_CONDITION_SELECT1_STEP7 (0x00BC4D4C) +#define DBG_CONDITION_SELECT1_STEP7___RWC QCSR_REG_RW +#define DBG_CONDITION_SELECT1_STEP7__NEXT_STEP___M 0x000E0000 +#define DBG_CONDITION_SELECT1_STEP7__NEXT_STEP___S 17 +#define DBG_CONDITION_SELECT1_STEP7__TRIGGER___M 0x0001E000 +#define DBG_CONDITION_SELECT1_STEP7__TRIGGER___S 13 +#define DBG_CONDITION_SELECT1_STEP7__BC0_INC___M 0x00000200 +#define DBG_CONDITION_SELECT1_STEP7__BC0_INC___S 9 +#define DBG_CONDITION_SELECT1_STEP7__BC0_DEC___M 0x00000100 +#define DBG_CONDITION_SELECT1_STEP7__BC0_DEC___S 8 +#define DBG_CONDITION_SELECT1_STEP7__BC0_CLEAR___M 0x00000080 +#define DBG_CONDITION_SELECT1_STEP7__BC0_CLEAR___S 7 +#define DBG_CONDITION_SELECT1_STEP7__TC0_ENABLE___M 0x00000008 +#define DBG_CONDITION_SELECT1_STEP7__TC0_ENABLE___S 3 +#define DBG_CONDITION_SELECT1_STEP7__TC0_PAUSE___M 0x00000004 +#define DBG_CONDITION_SELECT1_STEP7__TC0_PAUSE___S 2 +#define DBG_CONDITION_SELECT1_STEP7__TC0_CLEAR___M 0x00000002 +#define DBG_CONDITION_SELECT1_STEP7__TC0_CLEAR___S 1 +#define DBG_CONDITION_SELECT1_STEP7__DONE___M 0x00000001 +#define DBG_CONDITION_SELECT1_STEP7__DONE___S 0 +#define DBG_CONDITION_SELECT2_STEP0 (0x00BC4068) +#define DBG_CONDITION_SELECT2_STEP0___RWC QCSR_REG_RW +#define DBG_CONDITION_SELECT2_STEP0__NEXT_STEP___M 0x000E0000 +#define DBG_CONDITION_SELECT2_STEP0__NEXT_STEP___S 17 +#define DBG_CONDITION_SELECT2_STEP0__TRIGGER___M 0x0001E000 +#define DBG_CONDITION_SELECT2_STEP0__TRIGGER___S 13 +#define DBG_CONDITION_SELECT2_STEP0__BC0_INC___M 0x00000200 +#define DBG_CONDITION_SELECT2_STEP0__BC0_INC___S 9 +#define DBG_CONDITION_SELECT2_STEP0__BC0_DEC___M 0x00000100 +#define DBG_CONDITION_SELECT2_STEP0__BC0_DEC___S 8 +#define DBG_CONDITION_SELECT2_STEP0__BC0_CLEAR___M 0x00000080 +#define DBG_CONDITION_SELECT2_STEP0__BC0_CLEAR___S 7 +#define DBG_CONDITION_SELECT2_STEP0__TC0_ENABLE___M 0x00000008 +#define DBG_CONDITION_SELECT2_STEP0__TC0_ENABLE___S 3 +#define DBG_CONDITION_SELECT2_STEP0__TC0_PAUSE___M 0x00000004 +#define DBG_CONDITION_SELECT2_STEP0__TC0_PAUSE___S 2 +#define DBG_CONDITION_SELECT2_STEP0__TC0_CLEAR___M 0x00000002 +#define DBG_CONDITION_SELECT2_STEP0__TC0_CLEAR___S 1 +#define DBG_CONDITION_SELECT2_STEP0__DONE___M 0x00000001 +#define DBG_CONDITION_SELECT2_STEP0__DONE___S 0 +#define DBG_CONDITION_SELECT2_STEP1 (0x00BC4240) +#define DBG_CONDITION_SELECT2_STEP1___RWC QCSR_REG_RW +#define DBG_CONDITION_SELECT2_STEP1__NEXT_STEP___M 0x000E0000 +#define DBG_CONDITION_SELECT2_STEP1__NEXT_STEP___S 17 +#define DBG_CONDITION_SELECT2_STEP1__TRIGGER___M 0x0001E000 +#define DBG_CONDITION_SELECT2_STEP1__TRIGGER___S 13 +#define DBG_CONDITION_SELECT2_STEP1__BC0_INC___M 0x00000200 +#define DBG_CONDITION_SELECT2_STEP1__BC0_INC___S 9 +#define DBG_CONDITION_SELECT2_STEP1__BC0_DEC___M 0x00000100 +#define DBG_CONDITION_SELECT2_STEP1__BC0_DEC___S 8 +#define DBG_CONDITION_SELECT2_STEP1__BC0_CLEAR___M 0x00000080 +#define DBG_CONDITION_SELECT2_STEP1__BC0_CLEAR___S 7 +#define DBG_CONDITION_SELECT2_STEP1__TC0_ENABLE___M 0x00000008 +#define DBG_CONDITION_SELECT2_STEP1__TC0_ENABLE___S 3 +#define DBG_CONDITION_SELECT2_STEP1__TC0_PAUSE___M 0x00000004 +#define DBG_CONDITION_SELECT2_STEP1__TC0_PAUSE___S 2 +#define DBG_CONDITION_SELECT2_STEP1__TC0_CLEAR___M 0x00000002 +#define DBG_CONDITION_SELECT2_STEP1__TC0_CLEAR___S 1 +#define DBG_CONDITION_SELECT2_STEP1__DONE___M 0x00000001 +#define DBG_CONDITION_SELECT2_STEP1__DONE___S 0 +#define DBG_CONDITION_SELECT2_STEP2 (0x00BC4418) +#define DBG_CONDITION_SELECT2_STEP2___RWC QCSR_REG_RW +#define DBG_CONDITION_SELECT2_STEP2__NEXT_STEP___M 0x000E0000 +#define DBG_CONDITION_SELECT2_STEP2__NEXT_STEP___S 17 +#define DBG_CONDITION_SELECT2_STEP2__TRIGGER___M 0x0001E000 +#define DBG_CONDITION_SELECT2_STEP2__TRIGGER___S 13 +#define DBG_CONDITION_SELECT2_STEP2__BC0_INC___M 0x00000200 +#define DBG_CONDITION_SELECT2_STEP2__BC0_INC___S 9 +#define DBG_CONDITION_SELECT2_STEP2__BC0_DEC___M 0x00000100 +#define DBG_CONDITION_SELECT2_STEP2__BC0_DEC___S 8 +#define DBG_CONDITION_SELECT2_STEP2__BC0_CLEAR___M 0x00000080 +#define DBG_CONDITION_SELECT2_STEP2__BC0_CLEAR___S 7 +#define DBG_CONDITION_SELECT2_STEP2__TC0_ENABLE___M 0x00000008 +#define DBG_CONDITION_SELECT2_STEP2__TC0_ENABLE___S 3 +#define DBG_CONDITION_SELECT2_STEP2__TC0_PAUSE___M 0x00000004 +#define DBG_CONDITION_SELECT2_STEP2__TC0_PAUSE___S 2 +#define DBG_CONDITION_SELECT2_STEP2__TC0_CLEAR___M 0x00000002 +#define DBG_CONDITION_SELECT2_STEP2__TC0_CLEAR___S 1 +#define DBG_CONDITION_SELECT2_STEP2__DONE___M 0x00000001 +#define DBG_CONDITION_SELECT2_STEP2__DONE___S 0 +#define DBG_CONDITION_SELECT2_STEP3 (0x00BC45F0) +#define DBG_CONDITION_SELECT2_STEP3___RWC QCSR_REG_RW +#define DBG_CONDITION_SELECT2_STEP3__NEXT_STEP___M 0x000E0000 +#define DBG_CONDITION_SELECT2_STEP3__NEXT_STEP___S 17 +#define DBG_CONDITION_SELECT2_STEP3__TRIGGER___M 0x0001E000 +#define DBG_CONDITION_SELECT2_STEP3__TRIGGER___S 13 +#define DBG_CONDITION_SELECT2_STEP3__BC0_INC___M 0x00000200 +#define DBG_CONDITION_SELECT2_STEP3__BC0_INC___S 9 +#define DBG_CONDITION_SELECT2_STEP3__BC0_DEC___M 0x00000100 +#define DBG_CONDITION_SELECT2_STEP3__BC0_DEC___S 8 +#define DBG_CONDITION_SELECT2_STEP3__BC0_CLEAR___M 0x00000080 +#define DBG_CONDITION_SELECT2_STEP3__BC0_CLEAR___S 7 +#define DBG_CONDITION_SELECT2_STEP3__TC0_ENABLE___M 0x00000008 +#define DBG_CONDITION_SELECT2_STEP3__TC0_ENABLE___S 3 +#define DBG_CONDITION_SELECT2_STEP3__TC0_PAUSE___M 0x00000004 +#define DBG_CONDITION_SELECT2_STEP3__TC0_PAUSE___S 2 +#define DBG_CONDITION_SELECT2_STEP3__TC0_CLEAR___M 0x00000002 +#define DBG_CONDITION_SELECT2_STEP3__TC0_CLEAR___S 1 +#define DBG_CONDITION_SELECT2_STEP3__DONE___M 0x00000001 +#define DBG_CONDITION_SELECT2_STEP3__DONE___S 0 +#define DBG_CONDITION_SELECT2_STEP4 (0x00BC47C8) +#define DBG_CONDITION_SELECT2_STEP4___RWC QCSR_REG_RW +#define DBG_CONDITION_SELECT2_STEP4__NEXT_STEP___M 0x000E0000 +#define DBG_CONDITION_SELECT2_STEP4__NEXT_STEP___S 17 +#define DBG_CONDITION_SELECT2_STEP4__TRIGGER___M 0x0001E000 +#define DBG_CONDITION_SELECT2_STEP4__TRIGGER___S 13 +#define DBG_CONDITION_SELECT2_STEP4__BC0_INC___M 0x00000200 +#define DBG_CONDITION_SELECT2_STEP4__BC0_INC___S 9 +#define DBG_CONDITION_SELECT2_STEP4__BC0_DEC___M 0x00000100 +#define DBG_CONDITION_SELECT2_STEP4__BC0_DEC___S 8 +#define DBG_CONDITION_SELECT2_STEP4__BC0_CLEAR___M 0x00000080 +#define DBG_CONDITION_SELECT2_STEP4__BC0_CLEAR___S 7 +#define DBG_CONDITION_SELECT2_STEP4__TC0_ENABLE___M 0x00000008 +#define DBG_CONDITION_SELECT2_STEP4__TC0_ENABLE___S 3 +#define DBG_CONDITION_SELECT2_STEP4__TC0_PAUSE___M 0x00000004 +#define DBG_CONDITION_SELECT2_STEP4__TC0_PAUSE___S 2 +#define DBG_CONDITION_SELECT2_STEP4__TC0_CLEAR___M 0x00000002 +#define DBG_CONDITION_SELECT2_STEP4__TC0_CLEAR___S 1 +#define DBG_CONDITION_SELECT2_STEP4__DONE___M 0x00000001 +#define DBG_CONDITION_SELECT2_STEP4__DONE___S 0 +#define DBG_CONDITION_SELECT2_STEP5 (0x00BC49A0) +#define DBG_CONDITION_SELECT2_STEP5___RWC QCSR_REG_RW +#define DBG_CONDITION_SELECT2_STEP5__NEXT_STEP___M 0x000E0000 +#define DBG_CONDITION_SELECT2_STEP5__NEXT_STEP___S 17 +#define DBG_CONDITION_SELECT2_STEP5__TRIGGER___M 0x0001E000 +#define DBG_CONDITION_SELECT2_STEP5__TRIGGER___S 13 +#define DBG_CONDITION_SELECT2_STEP5__BC0_INC___M 0x00000200 +#define DBG_CONDITION_SELECT2_STEP5__BC0_INC___S 9 +#define DBG_CONDITION_SELECT2_STEP5__BC0_DEC___M 0x00000100 +#define DBG_CONDITION_SELECT2_STEP5__BC0_DEC___S 8 +#define DBG_CONDITION_SELECT2_STEP5__BC0_CLEAR___M 0x00000080 +#define DBG_CONDITION_SELECT2_STEP5__BC0_CLEAR___S 7 +#define DBG_CONDITION_SELECT2_STEP5__TC0_ENABLE___M 0x00000008 +#define DBG_CONDITION_SELECT2_STEP5__TC0_ENABLE___S 3 +#define DBG_CONDITION_SELECT2_STEP5__TC0_PAUSE___M 0x00000004 +#define DBG_CONDITION_SELECT2_STEP5__TC0_PAUSE___S 2 +#define DBG_CONDITION_SELECT2_STEP5__TC0_CLEAR___M 0x00000002 +#define DBG_CONDITION_SELECT2_STEP5__TC0_CLEAR___S 1 +#define DBG_CONDITION_SELECT2_STEP5__DONE___M 0x00000001 +#define DBG_CONDITION_SELECT2_STEP5__DONE___S 0 +#define DBG_CONDITION_SELECT2_STEP6 (0x00BC4B78) +#define DBG_CONDITION_SELECT2_STEP6___RWC QCSR_REG_RW +#define DBG_CONDITION_SELECT2_STEP6__NEXT_STEP___M 0x000E0000 +#define DBG_CONDITION_SELECT2_STEP6__NEXT_STEP___S 17 +#define DBG_CONDITION_SELECT2_STEP6__TRIGGER___M 0x0001E000 +#define DBG_CONDITION_SELECT2_STEP6__TRIGGER___S 13 +#define DBG_CONDITION_SELECT2_STEP6__BC0_INC___M 0x00000200 +#define DBG_CONDITION_SELECT2_STEP6__BC0_INC___S 9 +#define DBG_CONDITION_SELECT2_STEP6__BC0_DEC___M 0x00000100 +#define DBG_CONDITION_SELECT2_STEP6__BC0_DEC___S 8 +#define DBG_CONDITION_SELECT2_STEP6__BC0_CLEAR___M 0x00000080 +#define DBG_CONDITION_SELECT2_STEP6__BC0_CLEAR___S 7 +#define DBG_CONDITION_SELECT2_STEP6__TC0_ENABLE___M 0x00000008 +#define DBG_CONDITION_SELECT2_STEP6__TC0_ENABLE___S 3 +#define DBG_CONDITION_SELECT2_STEP6__TC0_PAUSE___M 0x00000004 +#define DBG_CONDITION_SELECT2_STEP6__TC0_PAUSE___S 2 +#define DBG_CONDITION_SELECT2_STEP6__TC0_CLEAR___M 0x00000002 +#define DBG_CONDITION_SELECT2_STEP6__TC0_CLEAR___S 1 +#define DBG_CONDITION_SELECT2_STEP6__DONE___M 0x00000001 +#define DBG_CONDITION_SELECT2_STEP6__DONE___S 0 +#define DBG_CONDITION_SELECT2_STEP7 (0x00BC4D50) +#define DBG_CONDITION_SELECT2_STEP7___RWC QCSR_REG_RW +#define DBG_CONDITION_SELECT2_STEP7__NEXT_STEP___M 0x000E0000 +#define DBG_CONDITION_SELECT2_STEP7__NEXT_STEP___S 17 +#define DBG_CONDITION_SELECT2_STEP7__TRIGGER___M 0x0001E000 +#define DBG_CONDITION_SELECT2_STEP7__TRIGGER___S 13 +#define DBG_CONDITION_SELECT2_STEP7__BC0_INC___M 0x00000200 +#define DBG_CONDITION_SELECT2_STEP7__BC0_INC___S 9 +#define DBG_CONDITION_SELECT2_STEP7__BC0_DEC___M 0x00000100 +#define DBG_CONDITION_SELECT2_STEP7__BC0_DEC___S 8 +#define DBG_CONDITION_SELECT2_STEP7__BC0_CLEAR___M 0x00000080 +#define DBG_CONDITION_SELECT2_STEP7__BC0_CLEAR___S 7 +#define DBG_CONDITION_SELECT2_STEP7__TC0_ENABLE___M 0x00000008 +#define DBG_CONDITION_SELECT2_STEP7__TC0_ENABLE___S 3 +#define DBG_CONDITION_SELECT2_STEP7__TC0_PAUSE___M 0x00000004 +#define DBG_CONDITION_SELECT2_STEP7__TC0_PAUSE___S 2 +#define DBG_CONDITION_SELECT2_STEP7__TC0_CLEAR___M 0x00000002 +#define DBG_CONDITION_SELECT2_STEP7__TC0_CLEAR___S 1 +#define DBG_CONDITION_SELECT2_STEP7__DONE___M 0x00000001 +#define DBG_CONDITION_SELECT2_STEP7__DONE___S 0 +#define DBG_CONDITION_SELECT3_STEP0 (0x00BC406C) +#define DBG_CONDITION_SELECT3_STEP0___RWC QCSR_REG_RW +#define DBG_CONDITION_SELECT3_STEP0__NEXT_STEP___M 0x000E0000 +#define DBG_CONDITION_SELECT3_STEP0__NEXT_STEP___S 17 +#define DBG_CONDITION_SELECT3_STEP0__TRIGGER___M 0x0001E000 +#define DBG_CONDITION_SELECT3_STEP0__TRIGGER___S 13 +#define DBG_CONDITION_SELECT3_STEP0__BC0_INC___M 0x00000200 +#define DBG_CONDITION_SELECT3_STEP0__BC0_INC___S 9 +#define DBG_CONDITION_SELECT3_STEP0__BC0_DEC___M 0x00000100 +#define DBG_CONDITION_SELECT3_STEP0__BC0_DEC___S 8 +#define DBG_CONDITION_SELECT3_STEP0__BC0_CLEAR___M 0x00000080 +#define DBG_CONDITION_SELECT3_STEP0__BC0_CLEAR___S 7 +#define DBG_CONDITION_SELECT3_STEP0__TC0_ENABLE___M 0x00000008 +#define DBG_CONDITION_SELECT3_STEP0__TC0_ENABLE___S 3 +#define DBG_CONDITION_SELECT3_STEP0__TC0_PAUSE___M 0x00000004 +#define DBG_CONDITION_SELECT3_STEP0__TC0_PAUSE___S 2 +#define DBG_CONDITION_SELECT3_STEP0__TC0_CLEAR___M 0x00000002 +#define DBG_CONDITION_SELECT3_STEP0__TC0_CLEAR___S 1 +#define DBG_CONDITION_SELECT3_STEP0__DONE___M 0x00000001 +#define DBG_CONDITION_SELECT3_STEP0__DONE___S 0 +#define DBG_CONDITION_SELECT3_STEP1 (0x00BC4244) +#define DBG_CONDITION_SELECT3_STEP1___RWC QCSR_REG_RW +#define DBG_CONDITION_SELECT3_STEP1__NEXT_STEP___M 0x000E0000 +#define DBG_CONDITION_SELECT3_STEP1__NEXT_STEP___S 17 +#define DBG_CONDITION_SELECT3_STEP1__TRIGGER___M 0x0001E000 +#define DBG_CONDITION_SELECT3_STEP1__TRIGGER___S 13 +#define DBG_CONDITION_SELECT3_STEP1__BC0_INC___M 0x00000200 +#define DBG_CONDITION_SELECT3_STEP1__BC0_INC___S 9 +#define DBG_CONDITION_SELECT3_STEP1__BC0_DEC___M 0x00000100 +#define DBG_CONDITION_SELECT3_STEP1__BC0_DEC___S 8 +#define DBG_CONDITION_SELECT3_STEP1__BC0_CLEAR___M 0x00000080 +#define DBG_CONDITION_SELECT3_STEP1__BC0_CLEAR___S 7 +#define DBG_CONDITION_SELECT3_STEP1__TC0_ENABLE___M 0x00000008 +#define DBG_CONDITION_SELECT3_STEP1__TC0_ENABLE___S 3 +#define DBG_CONDITION_SELECT3_STEP1__TC0_PAUSE___M 0x00000004 +#define DBG_CONDITION_SELECT3_STEP1__TC0_PAUSE___S 2 +#define DBG_CONDITION_SELECT3_STEP1__TC0_CLEAR___M 0x00000002 +#define DBG_CONDITION_SELECT3_STEP1__TC0_CLEAR___S 1 +#define DBG_CONDITION_SELECT3_STEP1__DONE___M 0x00000001 +#define DBG_CONDITION_SELECT3_STEP1__DONE___S 0 +#define DBG_CONDITION_SELECT3_STEP2 (0x00BC441C) +#define DBG_CONDITION_SELECT3_STEP2___RWC QCSR_REG_RW +#define DBG_CONDITION_SELECT3_STEP2__NEXT_STEP___M 0x000E0000 +#define DBG_CONDITION_SELECT3_STEP2__NEXT_STEP___S 17 +#define DBG_CONDITION_SELECT3_STEP2__TRIGGER___M 0x0001E000 +#define DBG_CONDITION_SELECT3_STEP2__TRIGGER___S 13 +#define DBG_CONDITION_SELECT3_STEP2__BC0_INC___M 0x00000200 +#define DBG_CONDITION_SELECT3_STEP2__BC0_INC___S 9 +#define DBG_CONDITION_SELECT3_STEP2__BC0_DEC___M 0x00000100 +#define DBG_CONDITION_SELECT3_STEP2__BC0_DEC___S 8 +#define DBG_CONDITION_SELECT3_STEP2__BC0_CLEAR___M 0x00000080 +#define DBG_CONDITION_SELECT3_STEP2__BC0_CLEAR___S 7 +#define DBG_CONDITION_SELECT3_STEP2__TC0_ENABLE___M 0x00000008 +#define DBG_CONDITION_SELECT3_STEP2__TC0_ENABLE___S 3 +#define DBG_CONDITION_SELECT3_STEP2__TC0_PAUSE___M 0x00000004 +#define DBG_CONDITION_SELECT3_STEP2__TC0_PAUSE___S 2 +#define DBG_CONDITION_SELECT3_STEP2__TC0_CLEAR___M 0x00000002 +#define DBG_CONDITION_SELECT3_STEP2__TC0_CLEAR___S 1 +#define DBG_CONDITION_SELECT3_STEP2__DONE___M 0x00000001 +#define DBG_CONDITION_SELECT3_STEP2__DONE___S 0 +#define DBG_CONDITION_SELECT3_STEP3 (0x00BC45F4) +#define DBG_CONDITION_SELECT3_STEP3___RWC QCSR_REG_RW +#define DBG_CONDITION_SELECT3_STEP3__NEXT_STEP___M 0x000E0000 +#define DBG_CONDITION_SELECT3_STEP3__NEXT_STEP___S 17 +#define DBG_CONDITION_SELECT3_STEP3__TRIGGER___M 0x0001E000 +#define DBG_CONDITION_SELECT3_STEP3__TRIGGER___S 13 +#define DBG_CONDITION_SELECT3_STEP3__BC0_INC___M 0x00000200 +#define DBG_CONDITION_SELECT3_STEP3__BC0_INC___S 9 +#define DBG_CONDITION_SELECT3_STEP3__BC0_DEC___M 0x00000100 +#define DBG_CONDITION_SELECT3_STEP3__BC0_DEC___S 8 +#define DBG_CONDITION_SELECT3_STEP3__BC0_CLEAR___M 0x00000080 +#define DBG_CONDITION_SELECT3_STEP3__BC0_CLEAR___S 7 +#define DBG_CONDITION_SELECT3_STEP3__TC0_ENABLE___M 0x00000008 +#define DBG_CONDITION_SELECT3_STEP3__TC0_ENABLE___S 3 +#define DBG_CONDITION_SELECT3_STEP3__TC0_PAUSE___M 0x00000004 +#define DBG_CONDITION_SELECT3_STEP3__TC0_PAUSE___S 2 +#define DBG_CONDITION_SELECT3_STEP3__TC0_CLEAR___M 0x00000002 +#define DBG_CONDITION_SELECT3_STEP3__TC0_CLEAR___S 1 +#define DBG_CONDITION_SELECT3_STEP3__DONE___M 0x00000001 +#define DBG_CONDITION_SELECT3_STEP3__DONE___S 0 +#define DBG_CONDITION_SELECT3_STEP4 (0x00BC47CC) +#define DBG_CONDITION_SELECT3_STEP4___RWC QCSR_REG_RW +#define DBG_CONDITION_SELECT3_STEP4__NEXT_STEP___M 0x000E0000 +#define DBG_CONDITION_SELECT3_STEP4__NEXT_STEP___S 17 +#define DBG_CONDITION_SELECT3_STEP4__TRIGGER___M 0x0001E000 +#define DBG_CONDITION_SELECT3_STEP4__TRIGGER___S 13 +#define DBG_CONDITION_SELECT3_STEP4__BC0_INC___M 0x00000200 +#define DBG_CONDITION_SELECT3_STEP4__BC0_INC___S 9 +#define DBG_CONDITION_SELECT3_STEP4__BC0_DEC___M 0x00000100 +#define DBG_CONDITION_SELECT3_STEP4__BC0_DEC___S 8 +#define DBG_CONDITION_SELECT3_STEP4__BC0_CLEAR___M 0x00000080 +#define DBG_CONDITION_SELECT3_STEP4__BC0_CLEAR___S 7 +#define DBG_CONDITION_SELECT3_STEP4__TC0_ENABLE___M 0x00000008 +#define DBG_CONDITION_SELECT3_STEP4__TC0_ENABLE___S 3 +#define DBG_CONDITION_SELECT3_STEP4__TC0_PAUSE___M 0x00000004 +#define DBG_CONDITION_SELECT3_STEP4__TC0_PAUSE___S 2 +#define DBG_CONDITION_SELECT3_STEP4__TC0_CLEAR___M 0x00000002 +#define DBG_CONDITION_SELECT3_STEP4__TC0_CLEAR___S 1 +#define DBG_CONDITION_SELECT3_STEP4__DONE___M 0x00000001 +#define DBG_CONDITION_SELECT3_STEP4__DONE___S 0 +#define DBG_CONDITION_SELECT3_STEP5 (0x00BC49A4) +#define DBG_CONDITION_SELECT3_STEP5___RWC QCSR_REG_RW +#define DBG_CONDITION_SELECT3_STEP5__NEXT_STEP___M 0x000E0000 +#define DBG_CONDITION_SELECT3_STEP5__NEXT_STEP___S 17 +#define DBG_CONDITION_SELECT3_STEP5__TRIGGER___M 0x0001E000 +#define DBG_CONDITION_SELECT3_STEP5__TRIGGER___S 13 +#define DBG_CONDITION_SELECT3_STEP5__BC0_INC___M 0x00000200 +#define DBG_CONDITION_SELECT3_STEP5__BC0_INC___S 9 +#define DBG_CONDITION_SELECT3_STEP5__BC0_DEC___M 0x00000100 +#define DBG_CONDITION_SELECT3_STEP5__BC0_DEC___S 8 +#define DBG_CONDITION_SELECT3_STEP5__BC0_CLEAR___M 0x00000080 +#define DBG_CONDITION_SELECT3_STEP5__BC0_CLEAR___S 7 +#define DBG_CONDITION_SELECT3_STEP5__TC0_ENABLE___M 0x00000008 +#define DBG_CONDITION_SELECT3_STEP5__TC0_ENABLE___S 3 +#define DBG_CONDITION_SELECT3_STEP5__TC0_PAUSE___M 0x00000004 +#define DBG_CONDITION_SELECT3_STEP5__TC0_PAUSE___S 2 +#define DBG_CONDITION_SELECT3_STEP5__TC0_CLEAR___M 0x00000002 +#define DBG_CONDITION_SELECT3_STEP5__TC0_CLEAR___S 1 +#define DBG_CONDITION_SELECT3_STEP5__DONE___M 0x00000001 +#define DBG_CONDITION_SELECT3_STEP5__DONE___S 0 +#define DBG_CONDITION_SELECT3_STEP6 (0x00BC4B7C) +#define DBG_CONDITION_SELECT3_STEP6___RWC QCSR_REG_RW +#define DBG_CONDITION_SELECT3_STEP6__NEXT_STEP___M 0x000E0000 +#define DBG_CONDITION_SELECT3_STEP6__NEXT_STEP___S 17 +#define DBG_CONDITION_SELECT3_STEP6__TRIGGER___M 0x0001E000 +#define DBG_CONDITION_SELECT3_STEP6__TRIGGER___S 13 +#define DBG_CONDITION_SELECT3_STEP6__BC0_INC___M 0x00000200 +#define DBG_CONDITION_SELECT3_STEP6__BC0_INC___S 9 +#define DBG_CONDITION_SELECT3_STEP6__BC0_DEC___M 0x00000100 +#define DBG_CONDITION_SELECT3_STEP6__BC0_DEC___S 8 +#define DBG_CONDITION_SELECT3_STEP6__BC0_CLEAR___M 0x00000080 +#define DBG_CONDITION_SELECT3_STEP6__BC0_CLEAR___S 7 +#define DBG_CONDITION_SELECT3_STEP6__TC0_ENABLE___M 0x00000008 +#define DBG_CONDITION_SELECT3_STEP6__TC0_ENABLE___S 3 +#define DBG_CONDITION_SELECT3_STEP6__TC0_PAUSE___M 0x00000004 +#define DBG_CONDITION_SELECT3_STEP6__TC0_PAUSE___S 2 +#define DBG_CONDITION_SELECT3_STEP6__TC0_CLEAR___M 0x00000002 +#define DBG_CONDITION_SELECT3_STEP6__TC0_CLEAR___S 1 +#define DBG_CONDITION_SELECT3_STEP6__DONE___M 0x00000001 +#define DBG_CONDITION_SELECT3_STEP6__DONE___S 0 +#define DBG_CONDITION_SELECT3_STEP7 (0x00BC4D54) +#define DBG_CONDITION_SELECT3_STEP7___RWC QCSR_REG_RW +#define DBG_CONDITION_SELECT3_STEP7__NEXT_STEP___M 0x000E0000 +#define DBG_CONDITION_SELECT3_STEP7__NEXT_STEP___S 17 +#define DBG_CONDITION_SELECT3_STEP7__TRIGGER___M 0x0001E000 +#define DBG_CONDITION_SELECT3_STEP7__TRIGGER___S 13 +#define DBG_CONDITION_SELECT3_STEP7__BC0_INC___M 0x00000200 +#define DBG_CONDITION_SELECT3_STEP7__BC0_INC___S 9 +#define DBG_CONDITION_SELECT3_STEP7__BC0_DEC___M 0x00000100 +#define DBG_CONDITION_SELECT3_STEP7__BC0_DEC___S 8 +#define DBG_CONDITION_SELECT3_STEP7__BC0_CLEAR___M 0x00000080 +#define DBG_CONDITION_SELECT3_STEP7__BC0_CLEAR___S 7 +#define DBG_CONDITION_SELECT3_STEP7__TC0_ENABLE___M 0x00000008 +#define DBG_CONDITION_SELECT3_STEP7__TC0_ENABLE___S 3 +#define DBG_CONDITION_SELECT3_STEP7__TC0_PAUSE___M 0x00000004 +#define DBG_CONDITION_SELECT3_STEP7__TC0_PAUSE___S 2 +#define DBG_CONDITION_SELECT3_STEP7__TC0_CLEAR___M 0x00000002 +#define DBG_CONDITION_SELECT3_STEP7__TC0_CLEAR___S 1 +#define DBG_CONDITION_SELECT3_STEP7__DONE___M 0x00000001 +#define DBG_CONDITION_SELECT3_STEP7__DONE___S 0 + +#define DBG_DEFAULT_CONDITION_STEPn(n) (0x00BC4070+0x1D8*(n)) +#define DBG_DEFAULT_CONDITION_STEPn_nMIN 0 +#define DBG_DEFAULT_CONDITION_STEPn_nMAX 7 +#define DBG_DEFAULT_CONDITION_STEPn_ELEM 8 +#define DBG_DEFAULT_CONDITION_STEPn___RWC QCSR_REG_RW +#define DBG_DEFAULT_CONDITION_STEPn___POR 0x00000000 +#define DBG_DEFAULT_CONDITION_STEPn__NEXT_STEP___POR 0x0 +#define DBG_DEFAULT_CONDITION_STEPn__TRIGGER___POR 0x0 +#define DBG_DEFAULT_CONDITION_STEPn__BC0_INC___POR 0x0 +#define DBG_DEFAULT_CONDITION_STEPn__BC0_DEC___POR 0x0 +#define DBG_DEFAULT_CONDITION_STEPn__BC0_CLEAR___POR 0x0 +#define DBG_DEFAULT_CONDITION_STEPn__TC0_ENABLE___POR 0x0 +#define DBG_DEFAULT_CONDITION_STEPn__TC0_PAUSE___POR 0x0 +#define DBG_DEFAULT_CONDITION_STEPn__TC0_CLEAR___POR 0x0 +#define DBG_DEFAULT_CONDITION_STEPn__DONE___POR 0x0 +#define DBG_DEFAULT_CONDITION_STEPn__NEXT_STEP___M 0x000E0000 +#define DBG_DEFAULT_CONDITION_STEPn__NEXT_STEP___S 17 +#define DBG_DEFAULT_CONDITION_STEPn__TRIGGER___M 0x0001E000 +#define DBG_DEFAULT_CONDITION_STEPn__TRIGGER___S 13 +#define DBG_DEFAULT_CONDITION_STEPn__BC0_INC___M 0x00000200 +#define DBG_DEFAULT_CONDITION_STEPn__BC0_INC___S 9 +#define DBG_DEFAULT_CONDITION_STEPn__BC0_DEC___M 0x00000100 +#define DBG_DEFAULT_CONDITION_STEPn__BC0_DEC___S 8 +#define DBG_DEFAULT_CONDITION_STEPn__BC0_CLEAR___M 0x00000080 +#define DBG_DEFAULT_CONDITION_STEPn__BC0_CLEAR___S 7 +#define DBG_DEFAULT_CONDITION_STEPn__TC0_ENABLE___M 0x00000008 +#define DBG_DEFAULT_CONDITION_STEPn__TC0_ENABLE___S 3 +#define DBG_DEFAULT_CONDITION_STEPn__TC0_PAUSE___M 0x00000004 +#define DBG_DEFAULT_CONDITION_STEPn__TC0_PAUSE___S 2 +#define DBG_DEFAULT_CONDITION_STEPn__TC0_CLEAR___M 0x00000002 +#define DBG_DEFAULT_CONDITION_STEPn__TC0_CLEAR___S 1 +#define DBG_DEFAULT_CONDITION_STEPn__DONE___M 0x00000001 +#define DBG_DEFAULT_CONDITION_STEPn__DONE___S 0 +#define DBG_DEFAULT_CONDITION_STEPn___M 0x000FE38F +#define DBG_DEFAULT_CONDITION_STEPn___S 0 +#define DBG_DEFAULT_CONDITION_STEP0 (0x00BC4070) +#define DBG_DEFAULT_CONDITION_STEP0___RWC QCSR_REG_RW +#define DBG_DEFAULT_CONDITION_STEP0__NEXT_STEP___M 0x000E0000 +#define DBG_DEFAULT_CONDITION_STEP0__NEXT_STEP___S 17 +#define DBG_DEFAULT_CONDITION_STEP0__TRIGGER___M 0x0001E000 +#define DBG_DEFAULT_CONDITION_STEP0__TRIGGER___S 13 +#define DBG_DEFAULT_CONDITION_STEP0__BC0_INC___M 0x00000200 +#define DBG_DEFAULT_CONDITION_STEP0__BC0_INC___S 9 +#define DBG_DEFAULT_CONDITION_STEP0__BC0_DEC___M 0x00000100 +#define DBG_DEFAULT_CONDITION_STEP0__BC0_DEC___S 8 +#define DBG_DEFAULT_CONDITION_STEP0__BC0_CLEAR___M 0x00000080 +#define DBG_DEFAULT_CONDITION_STEP0__BC0_CLEAR___S 7 +#define DBG_DEFAULT_CONDITION_STEP0__TC0_ENABLE___M 0x00000008 +#define DBG_DEFAULT_CONDITION_STEP0__TC0_ENABLE___S 3 +#define DBG_DEFAULT_CONDITION_STEP0__TC0_PAUSE___M 0x00000004 +#define DBG_DEFAULT_CONDITION_STEP0__TC0_PAUSE___S 2 +#define DBG_DEFAULT_CONDITION_STEP0__TC0_CLEAR___M 0x00000002 +#define DBG_DEFAULT_CONDITION_STEP0__TC0_CLEAR___S 1 +#define DBG_DEFAULT_CONDITION_STEP0__DONE___M 0x00000001 +#define DBG_DEFAULT_CONDITION_STEP0__DONE___S 0 +#define DBG_DEFAULT_CONDITION_STEP1 (0x00BC4248) +#define DBG_DEFAULT_CONDITION_STEP1___RWC QCSR_REG_RW +#define DBG_DEFAULT_CONDITION_STEP1__NEXT_STEP___M 0x000E0000 +#define DBG_DEFAULT_CONDITION_STEP1__NEXT_STEP___S 17 +#define DBG_DEFAULT_CONDITION_STEP1__TRIGGER___M 0x0001E000 +#define DBG_DEFAULT_CONDITION_STEP1__TRIGGER___S 13 +#define DBG_DEFAULT_CONDITION_STEP1__BC0_INC___M 0x00000200 +#define DBG_DEFAULT_CONDITION_STEP1__BC0_INC___S 9 +#define DBG_DEFAULT_CONDITION_STEP1__BC0_DEC___M 0x00000100 +#define DBG_DEFAULT_CONDITION_STEP1__BC0_DEC___S 8 +#define DBG_DEFAULT_CONDITION_STEP1__BC0_CLEAR___M 0x00000080 +#define DBG_DEFAULT_CONDITION_STEP1__BC0_CLEAR___S 7 +#define DBG_DEFAULT_CONDITION_STEP1__TC0_ENABLE___M 0x00000008 +#define DBG_DEFAULT_CONDITION_STEP1__TC0_ENABLE___S 3 +#define DBG_DEFAULT_CONDITION_STEP1__TC0_PAUSE___M 0x00000004 +#define DBG_DEFAULT_CONDITION_STEP1__TC0_PAUSE___S 2 +#define DBG_DEFAULT_CONDITION_STEP1__TC0_CLEAR___M 0x00000002 +#define DBG_DEFAULT_CONDITION_STEP1__TC0_CLEAR___S 1 +#define DBG_DEFAULT_CONDITION_STEP1__DONE___M 0x00000001 +#define DBG_DEFAULT_CONDITION_STEP1__DONE___S 0 +#define DBG_DEFAULT_CONDITION_STEP2 (0x00BC4420) +#define DBG_DEFAULT_CONDITION_STEP2___RWC QCSR_REG_RW +#define DBG_DEFAULT_CONDITION_STEP2__NEXT_STEP___M 0x000E0000 +#define DBG_DEFAULT_CONDITION_STEP2__NEXT_STEP___S 17 +#define DBG_DEFAULT_CONDITION_STEP2__TRIGGER___M 0x0001E000 +#define DBG_DEFAULT_CONDITION_STEP2__TRIGGER___S 13 +#define DBG_DEFAULT_CONDITION_STEP2__BC0_INC___M 0x00000200 +#define DBG_DEFAULT_CONDITION_STEP2__BC0_INC___S 9 +#define DBG_DEFAULT_CONDITION_STEP2__BC0_DEC___M 0x00000100 +#define DBG_DEFAULT_CONDITION_STEP2__BC0_DEC___S 8 +#define DBG_DEFAULT_CONDITION_STEP2__BC0_CLEAR___M 0x00000080 +#define DBG_DEFAULT_CONDITION_STEP2__BC0_CLEAR___S 7 +#define DBG_DEFAULT_CONDITION_STEP2__TC0_ENABLE___M 0x00000008 +#define DBG_DEFAULT_CONDITION_STEP2__TC0_ENABLE___S 3 +#define DBG_DEFAULT_CONDITION_STEP2__TC0_PAUSE___M 0x00000004 +#define DBG_DEFAULT_CONDITION_STEP2__TC0_PAUSE___S 2 +#define DBG_DEFAULT_CONDITION_STEP2__TC0_CLEAR___M 0x00000002 +#define DBG_DEFAULT_CONDITION_STEP2__TC0_CLEAR___S 1 +#define DBG_DEFAULT_CONDITION_STEP2__DONE___M 0x00000001 +#define DBG_DEFAULT_CONDITION_STEP2__DONE___S 0 +#define DBG_DEFAULT_CONDITION_STEP3 (0x00BC45F8) +#define DBG_DEFAULT_CONDITION_STEP3___RWC QCSR_REG_RW +#define DBG_DEFAULT_CONDITION_STEP3__NEXT_STEP___M 0x000E0000 +#define DBG_DEFAULT_CONDITION_STEP3__NEXT_STEP___S 17 +#define DBG_DEFAULT_CONDITION_STEP3__TRIGGER___M 0x0001E000 +#define DBG_DEFAULT_CONDITION_STEP3__TRIGGER___S 13 +#define DBG_DEFAULT_CONDITION_STEP3__BC0_INC___M 0x00000200 +#define DBG_DEFAULT_CONDITION_STEP3__BC0_INC___S 9 +#define DBG_DEFAULT_CONDITION_STEP3__BC0_DEC___M 0x00000100 +#define DBG_DEFAULT_CONDITION_STEP3__BC0_DEC___S 8 +#define DBG_DEFAULT_CONDITION_STEP3__BC0_CLEAR___M 0x00000080 +#define DBG_DEFAULT_CONDITION_STEP3__BC0_CLEAR___S 7 +#define DBG_DEFAULT_CONDITION_STEP3__TC0_ENABLE___M 0x00000008 +#define DBG_DEFAULT_CONDITION_STEP3__TC0_ENABLE___S 3 +#define DBG_DEFAULT_CONDITION_STEP3__TC0_PAUSE___M 0x00000004 +#define DBG_DEFAULT_CONDITION_STEP3__TC0_PAUSE___S 2 +#define DBG_DEFAULT_CONDITION_STEP3__TC0_CLEAR___M 0x00000002 +#define DBG_DEFAULT_CONDITION_STEP3__TC0_CLEAR___S 1 +#define DBG_DEFAULT_CONDITION_STEP3__DONE___M 0x00000001 +#define DBG_DEFAULT_CONDITION_STEP3__DONE___S 0 +#define DBG_DEFAULT_CONDITION_STEP4 (0x00BC47D0) +#define DBG_DEFAULT_CONDITION_STEP4___RWC QCSR_REG_RW +#define DBG_DEFAULT_CONDITION_STEP4__NEXT_STEP___M 0x000E0000 +#define DBG_DEFAULT_CONDITION_STEP4__NEXT_STEP___S 17 +#define DBG_DEFAULT_CONDITION_STEP4__TRIGGER___M 0x0001E000 +#define DBG_DEFAULT_CONDITION_STEP4__TRIGGER___S 13 +#define DBG_DEFAULT_CONDITION_STEP4__BC0_INC___M 0x00000200 +#define DBG_DEFAULT_CONDITION_STEP4__BC0_INC___S 9 +#define DBG_DEFAULT_CONDITION_STEP4__BC0_DEC___M 0x00000100 +#define DBG_DEFAULT_CONDITION_STEP4__BC0_DEC___S 8 +#define DBG_DEFAULT_CONDITION_STEP4__BC0_CLEAR___M 0x00000080 +#define DBG_DEFAULT_CONDITION_STEP4__BC0_CLEAR___S 7 +#define DBG_DEFAULT_CONDITION_STEP4__TC0_ENABLE___M 0x00000008 +#define DBG_DEFAULT_CONDITION_STEP4__TC0_ENABLE___S 3 +#define DBG_DEFAULT_CONDITION_STEP4__TC0_PAUSE___M 0x00000004 +#define DBG_DEFAULT_CONDITION_STEP4__TC0_PAUSE___S 2 +#define DBG_DEFAULT_CONDITION_STEP4__TC0_CLEAR___M 0x00000002 +#define DBG_DEFAULT_CONDITION_STEP4__TC0_CLEAR___S 1 +#define DBG_DEFAULT_CONDITION_STEP4__DONE___M 0x00000001 +#define DBG_DEFAULT_CONDITION_STEP4__DONE___S 0 +#define DBG_DEFAULT_CONDITION_STEP5 (0x00BC49A8) +#define DBG_DEFAULT_CONDITION_STEP5___RWC QCSR_REG_RW +#define DBG_DEFAULT_CONDITION_STEP5__NEXT_STEP___M 0x000E0000 +#define DBG_DEFAULT_CONDITION_STEP5__NEXT_STEP___S 17 +#define DBG_DEFAULT_CONDITION_STEP5__TRIGGER___M 0x0001E000 +#define DBG_DEFAULT_CONDITION_STEP5__TRIGGER___S 13 +#define DBG_DEFAULT_CONDITION_STEP5__BC0_INC___M 0x00000200 +#define DBG_DEFAULT_CONDITION_STEP5__BC0_INC___S 9 +#define DBG_DEFAULT_CONDITION_STEP5__BC0_DEC___M 0x00000100 +#define DBG_DEFAULT_CONDITION_STEP5__BC0_DEC___S 8 +#define DBG_DEFAULT_CONDITION_STEP5__BC0_CLEAR___M 0x00000080 +#define DBG_DEFAULT_CONDITION_STEP5__BC0_CLEAR___S 7 +#define DBG_DEFAULT_CONDITION_STEP5__TC0_ENABLE___M 0x00000008 +#define DBG_DEFAULT_CONDITION_STEP5__TC0_ENABLE___S 3 +#define DBG_DEFAULT_CONDITION_STEP5__TC0_PAUSE___M 0x00000004 +#define DBG_DEFAULT_CONDITION_STEP5__TC0_PAUSE___S 2 +#define DBG_DEFAULT_CONDITION_STEP5__TC0_CLEAR___M 0x00000002 +#define DBG_DEFAULT_CONDITION_STEP5__TC0_CLEAR___S 1 +#define DBG_DEFAULT_CONDITION_STEP5__DONE___M 0x00000001 +#define DBG_DEFAULT_CONDITION_STEP5__DONE___S 0 +#define DBG_DEFAULT_CONDITION_STEP6 (0x00BC4B80) +#define DBG_DEFAULT_CONDITION_STEP6___RWC QCSR_REG_RW +#define DBG_DEFAULT_CONDITION_STEP6__NEXT_STEP___M 0x000E0000 +#define DBG_DEFAULT_CONDITION_STEP6__NEXT_STEP___S 17 +#define DBG_DEFAULT_CONDITION_STEP6__TRIGGER___M 0x0001E000 +#define DBG_DEFAULT_CONDITION_STEP6__TRIGGER___S 13 +#define DBG_DEFAULT_CONDITION_STEP6__BC0_INC___M 0x00000200 +#define DBG_DEFAULT_CONDITION_STEP6__BC0_INC___S 9 +#define DBG_DEFAULT_CONDITION_STEP6__BC0_DEC___M 0x00000100 +#define DBG_DEFAULT_CONDITION_STEP6__BC0_DEC___S 8 +#define DBG_DEFAULT_CONDITION_STEP6__BC0_CLEAR___M 0x00000080 +#define DBG_DEFAULT_CONDITION_STEP6__BC0_CLEAR___S 7 +#define DBG_DEFAULT_CONDITION_STEP6__TC0_ENABLE___M 0x00000008 +#define DBG_DEFAULT_CONDITION_STEP6__TC0_ENABLE___S 3 +#define DBG_DEFAULT_CONDITION_STEP6__TC0_PAUSE___M 0x00000004 +#define DBG_DEFAULT_CONDITION_STEP6__TC0_PAUSE___S 2 +#define DBG_DEFAULT_CONDITION_STEP6__TC0_CLEAR___M 0x00000002 +#define DBG_DEFAULT_CONDITION_STEP6__TC0_CLEAR___S 1 +#define DBG_DEFAULT_CONDITION_STEP6__DONE___M 0x00000001 +#define DBG_DEFAULT_CONDITION_STEP6__DONE___S 0 +#define DBG_DEFAULT_CONDITION_STEP7 (0x00BC4D58) +#define DBG_DEFAULT_CONDITION_STEP7___RWC QCSR_REG_RW +#define DBG_DEFAULT_CONDITION_STEP7__NEXT_STEP___M 0x000E0000 +#define DBG_DEFAULT_CONDITION_STEP7__NEXT_STEP___S 17 +#define DBG_DEFAULT_CONDITION_STEP7__TRIGGER___M 0x0001E000 +#define DBG_DEFAULT_CONDITION_STEP7__TRIGGER___S 13 +#define DBG_DEFAULT_CONDITION_STEP7__BC0_INC___M 0x00000200 +#define DBG_DEFAULT_CONDITION_STEP7__BC0_INC___S 9 +#define DBG_DEFAULT_CONDITION_STEP7__BC0_DEC___M 0x00000100 +#define DBG_DEFAULT_CONDITION_STEP7__BC0_DEC___S 8 +#define DBG_DEFAULT_CONDITION_STEP7__BC0_CLEAR___M 0x00000080 +#define DBG_DEFAULT_CONDITION_STEP7__BC0_CLEAR___S 7 +#define DBG_DEFAULT_CONDITION_STEP7__TC0_ENABLE___M 0x00000008 +#define DBG_DEFAULT_CONDITION_STEP7__TC0_ENABLE___S 3 +#define DBG_DEFAULT_CONDITION_STEP7__TC0_PAUSE___M 0x00000004 +#define DBG_DEFAULT_CONDITION_STEP7__TC0_PAUSE___S 2 +#define DBG_DEFAULT_CONDITION_STEP7__TC0_CLEAR___M 0x00000002 +#define DBG_DEFAULT_CONDITION_STEP7__TC0_CLEAR___S 1 +#define DBG_DEFAULT_CONDITION_STEP7__DONE___M 0x00000001 +#define DBG_DEFAULT_CONDITION_STEP7__DONE___S 0 + +#define DBG_GROUP0_REGm_STEPn(m,n) (0x00BC4074+0x4*(m)+0x1D8*(n)) +#define DBG_GROUP0_REGm_STEPn_mMIN 0 +#define DBG_GROUP0_REGm_STEPn_mMAX 5 +#define DBG_GROUP0_REGm_STEPn_nMIN 0 +#define DBG_GROUP0_REGm_STEPn_nMAX 7 +#define DBG_GROUP0_REGm_STEPn_ELEM 48 +#define DBG_GROUP0_REGm_STEPn___RWC QCSR_REG_RW +#define DBG_GROUP0_REGm_STEPn___POR 0x00000000 +#define DBG_GROUP0_REGm_STEPn__SEL_BIT7_TYPE3___POR 0x0 +#define DBG_GROUP0_REGm_STEPn__SEL_BIT6_TYPE3___POR 0x0 +#define DBG_GROUP0_REGm_STEPn__SEL_BIT5_TYPE3___POR 0x0 +#define DBG_GROUP0_REGm_STEPn__SEL_BIT4_TYPE3___POR 0x0 +#define DBG_GROUP0_REGm_STEPn__SEL_BIT3_TYPE3___POR 0x0 +#define DBG_GROUP0_REGm_STEPn__SEL_BIT2_TYPE3___POR 0x0 +#define DBG_GROUP0_REGm_STEPn__SEL_BIT1_TYPE3___POR 0x0 +#define DBG_GROUP0_REGm_STEPn__SEL_BIT0_TYPE3___POR 0x0 +#define DBG_GROUP0_REGm_STEPn__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REGm_STEPn__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REGm_STEPn__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REGm_STEPn__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REGm_STEPn__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REGm_STEPn__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REGm_STEPn__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REGm_STEPn__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REGm_STEPn__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REGm_STEPn__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REGm_STEPn__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REGm_STEPn__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REGm_STEPn__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REGm_STEPn__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REGm_STEPn__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REGm_STEPn__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REGm_STEPn___M 0x77777777 +#define DBG_GROUP0_REGm_STEPn___S 0 +#define DBG_GROUP0_REG0_STEP0 (0x00BC4074) +#define DBG_GROUP0_REG0_STEP0___RWC QCSR_REG_RW +#define DBG_GROUP0_REG0_STEP0__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG0_STEP0__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG0_STEP0__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG0_STEP0__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG0_STEP0__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG0_STEP0__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG0_STEP0__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG0_STEP0__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG0_STEP0__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG0_STEP0__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG0_STEP0__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG0_STEP0__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG0_STEP0__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG0_STEP0__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG0_STEP0__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG0_STEP0__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG0_STEP1 (0x00BC424C) +#define DBG_GROUP0_REG0_STEP1___RWC QCSR_REG_RW +#define DBG_GROUP0_REG0_STEP1__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG0_STEP1__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG0_STEP1__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG0_STEP1__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG0_STEP1__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG0_STEP1__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG0_STEP1__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG0_STEP1__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG0_STEP1__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG0_STEP1__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG0_STEP1__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG0_STEP1__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG0_STEP1__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG0_STEP1__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG0_STEP1__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG0_STEP1__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG0_STEP2 (0x00BC4424) +#define DBG_GROUP0_REG0_STEP2___RWC QCSR_REG_RW +#define DBG_GROUP0_REG0_STEP2__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG0_STEP2__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG0_STEP2__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG0_STEP2__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG0_STEP2__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG0_STEP2__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG0_STEP2__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG0_STEP2__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG0_STEP2__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG0_STEP2__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG0_STEP2__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG0_STEP2__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG0_STEP2__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG0_STEP2__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG0_STEP2__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG0_STEP2__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG0_STEP3 (0x00BC45FC) +#define DBG_GROUP0_REG0_STEP3___RWC QCSR_REG_RW +#define DBG_GROUP0_REG0_STEP3__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG0_STEP3__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG0_STEP3__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG0_STEP3__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG0_STEP3__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG0_STEP3__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG0_STEP3__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG0_STEP3__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG0_STEP3__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG0_STEP3__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG0_STEP3__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG0_STEP3__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG0_STEP3__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG0_STEP3__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG0_STEP3__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG0_STEP3__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG0_STEP4 (0x00BC47D4) +#define DBG_GROUP0_REG0_STEP4___RWC QCSR_REG_RW +#define DBG_GROUP0_REG0_STEP4__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG0_STEP4__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG0_STEP4__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG0_STEP4__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG0_STEP4__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG0_STEP4__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG0_STEP4__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG0_STEP4__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG0_STEP4__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG0_STEP4__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG0_STEP4__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG0_STEP4__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG0_STEP4__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG0_STEP4__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG0_STEP4__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG0_STEP4__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG0_STEP5 (0x00BC49AC) +#define DBG_GROUP0_REG0_STEP5___RWC QCSR_REG_RW +#define DBG_GROUP0_REG0_STEP5__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG0_STEP5__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG0_STEP5__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG0_STEP5__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG0_STEP5__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG0_STEP5__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG0_STEP5__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG0_STEP5__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG0_STEP5__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG0_STEP5__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG0_STEP5__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG0_STEP5__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG0_STEP5__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG0_STEP5__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG0_STEP5__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG0_STEP5__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG0_STEP6 (0x00BC4B84) +#define DBG_GROUP0_REG0_STEP6___RWC QCSR_REG_RW +#define DBG_GROUP0_REG0_STEP6__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG0_STEP6__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG0_STEP6__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG0_STEP6__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG0_STEP6__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG0_STEP6__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG0_STEP6__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG0_STEP6__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG0_STEP6__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG0_STEP6__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG0_STEP6__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG0_STEP6__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG0_STEP6__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG0_STEP6__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG0_STEP6__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG0_STEP6__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG0_STEP7 (0x00BC4D5C) +#define DBG_GROUP0_REG0_STEP7___RWC QCSR_REG_RW +#define DBG_GROUP0_REG0_STEP7__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG0_STEP7__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG0_STEP7__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG0_STEP7__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG0_STEP7__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG0_STEP7__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG0_STEP7__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG0_STEP7__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG0_STEP7__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG0_STEP7__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG0_STEP7__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG0_STEP7__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG0_STEP7__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG0_STEP7__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG0_STEP7__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG0_STEP7__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG1_STEP0 (0x00BC4078) +#define DBG_GROUP0_REG1_STEP0___RWC QCSR_REG_RW +#define DBG_GROUP0_REG1_STEP0__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG1_STEP0__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG1_STEP0__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG1_STEP0__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG1_STEP0__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG1_STEP0__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG1_STEP0__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG1_STEP0__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG1_STEP0__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG1_STEP0__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG1_STEP0__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG1_STEP0__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG1_STEP0__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG1_STEP0__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG1_STEP0__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG1_STEP0__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG1_STEP1 (0x00BC4250) +#define DBG_GROUP0_REG1_STEP1___RWC QCSR_REG_RW +#define DBG_GROUP0_REG1_STEP1__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG1_STEP1__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG1_STEP1__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG1_STEP1__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG1_STEP1__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG1_STEP1__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG1_STEP1__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG1_STEP1__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG1_STEP1__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG1_STEP1__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG1_STEP1__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG1_STEP1__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG1_STEP1__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG1_STEP1__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG1_STEP1__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG1_STEP1__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG1_STEP2 (0x00BC4428) +#define DBG_GROUP0_REG1_STEP2___RWC QCSR_REG_RW +#define DBG_GROUP0_REG1_STEP2__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG1_STEP2__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG1_STEP2__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG1_STEP2__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG1_STEP2__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG1_STEP2__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG1_STEP2__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG1_STEP2__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG1_STEP2__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG1_STEP2__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG1_STEP2__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG1_STEP2__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG1_STEP2__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG1_STEP2__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG1_STEP2__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG1_STEP2__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG1_STEP3 (0x00BC4600) +#define DBG_GROUP0_REG1_STEP3___RWC QCSR_REG_RW +#define DBG_GROUP0_REG1_STEP3__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG1_STEP3__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG1_STEP3__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG1_STEP3__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG1_STEP3__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG1_STEP3__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG1_STEP3__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG1_STEP3__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG1_STEP3__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG1_STEP3__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG1_STEP3__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG1_STEP3__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG1_STEP3__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG1_STEP3__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG1_STEP3__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG1_STEP3__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG1_STEP4 (0x00BC47D8) +#define DBG_GROUP0_REG1_STEP4___RWC QCSR_REG_RW +#define DBG_GROUP0_REG1_STEP4__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG1_STEP4__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG1_STEP4__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG1_STEP4__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG1_STEP4__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG1_STEP4__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG1_STEP4__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG1_STEP4__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG1_STEP4__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG1_STEP4__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG1_STEP4__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG1_STEP4__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG1_STEP4__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG1_STEP4__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG1_STEP4__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG1_STEP4__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG1_STEP5 (0x00BC49B0) +#define DBG_GROUP0_REG1_STEP5___RWC QCSR_REG_RW +#define DBG_GROUP0_REG1_STEP5__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG1_STEP5__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG1_STEP5__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG1_STEP5__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG1_STEP5__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG1_STEP5__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG1_STEP5__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG1_STEP5__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG1_STEP5__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG1_STEP5__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG1_STEP5__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG1_STEP5__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG1_STEP5__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG1_STEP5__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG1_STEP5__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG1_STEP5__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG1_STEP6 (0x00BC4B88) +#define DBG_GROUP0_REG1_STEP6___RWC QCSR_REG_RW +#define DBG_GROUP0_REG1_STEP6__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG1_STEP6__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG1_STEP6__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG1_STEP6__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG1_STEP6__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG1_STEP6__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG1_STEP6__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG1_STEP6__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG1_STEP6__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG1_STEP6__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG1_STEP6__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG1_STEP6__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG1_STEP6__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG1_STEP6__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG1_STEP6__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG1_STEP6__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG1_STEP7 (0x00BC4D60) +#define DBG_GROUP0_REG1_STEP7___RWC QCSR_REG_RW +#define DBG_GROUP0_REG1_STEP7__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG1_STEP7__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG1_STEP7__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG1_STEP7__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG1_STEP7__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG1_STEP7__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG1_STEP7__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG1_STEP7__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG1_STEP7__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG1_STEP7__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG1_STEP7__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG1_STEP7__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG1_STEP7__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG1_STEP7__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG1_STEP7__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG1_STEP7__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG2_STEP0 (0x00BC407C) +#define DBG_GROUP0_REG2_STEP0___RWC QCSR_REG_RW +#define DBG_GROUP0_REG2_STEP0__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG2_STEP0__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG2_STEP0__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG2_STEP0__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG2_STEP0__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG2_STEP0__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG2_STEP0__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG2_STEP0__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG2_STEP0__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG2_STEP0__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG2_STEP0__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG2_STEP0__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG2_STEP0__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG2_STEP0__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG2_STEP0__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG2_STEP0__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG2_STEP1 (0x00BC4254) +#define DBG_GROUP0_REG2_STEP1___RWC QCSR_REG_RW +#define DBG_GROUP0_REG2_STEP1__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG2_STEP1__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG2_STEP1__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG2_STEP1__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG2_STEP1__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG2_STEP1__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG2_STEP1__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG2_STEP1__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG2_STEP1__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG2_STEP1__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG2_STEP1__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG2_STEP1__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG2_STEP1__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG2_STEP1__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG2_STEP1__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG2_STEP1__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG2_STEP2 (0x00BC442C) +#define DBG_GROUP0_REG2_STEP2___RWC QCSR_REG_RW +#define DBG_GROUP0_REG2_STEP2__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG2_STEP2__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG2_STEP2__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG2_STEP2__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG2_STEP2__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG2_STEP2__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG2_STEP2__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG2_STEP2__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG2_STEP2__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG2_STEP2__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG2_STEP2__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG2_STEP2__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG2_STEP2__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG2_STEP2__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG2_STEP2__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG2_STEP2__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG2_STEP3 (0x00BC4604) +#define DBG_GROUP0_REG2_STEP3___RWC QCSR_REG_RW +#define DBG_GROUP0_REG2_STEP3__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG2_STEP3__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG2_STEP3__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG2_STEP3__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG2_STEP3__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG2_STEP3__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG2_STEP3__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG2_STEP3__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG2_STEP3__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG2_STEP3__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG2_STEP3__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG2_STEP3__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG2_STEP3__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG2_STEP3__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG2_STEP3__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG2_STEP3__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG2_STEP4 (0x00BC47DC) +#define DBG_GROUP0_REG2_STEP4___RWC QCSR_REG_RW +#define DBG_GROUP0_REG2_STEP4__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG2_STEP4__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG2_STEP4__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG2_STEP4__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG2_STEP4__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG2_STEP4__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG2_STEP4__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG2_STEP4__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG2_STEP4__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG2_STEP4__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG2_STEP4__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG2_STEP4__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG2_STEP4__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG2_STEP4__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG2_STEP4__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG2_STEP4__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG2_STEP5 (0x00BC49B4) +#define DBG_GROUP0_REG2_STEP5___RWC QCSR_REG_RW +#define DBG_GROUP0_REG2_STEP5__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG2_STEP5__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG2_STEP5__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG2_STEP5__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG2_STEP5__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG2_STEP5__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG2_STEP5__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG2_STEP5__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG2_STEP5__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG2_STEP5__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG2_STEP5__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG2_STEP5__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG2_STEP5__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG2_STEP5__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG2_STEP5__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG2_STEP5__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG2_STEP6 (0x00BC4B8C) +#define DBG_GROUP0_REG2_STEP6___RWC QCSR_REG_RW +#define DBG_GROUP0_REG2_STEP6__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG2_STEP6__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG2_STEP6__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG2_STEP6__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG2_STEP6__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG2_STEP6__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG2_STEP6__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG2_STEP6__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG2_STEP6__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG2_STEP6__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG2_STEP6__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG2_STEP6__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG2_STEP6__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG2_STEP6__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG2_STEP6__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG2_STEP6__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG2_STEP7 (0x00BC4D64) +#define DBG_GROUP0_REG2_STEP7___RWC QCSR_REG_RW +#define DBG_GROUP0_REG2_STEP7__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG2_STEP7__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG2_STEP7__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG2_STEP7__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG2_STEP7__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG2_STEP7__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG2_STEP7__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG2_STEP7__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG2_STEP7__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG2_STEP7__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG2_STEP7__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG2_STEP7__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG2_STEP7__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG2_STEP7__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG2_STEP7__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG2_STEP7__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG3_STEP0 (0x00BC4080) +#define DBG_GROUP0_REG3_STEP0___RWC QCSR_REG_RW +#define DBG_GROUP0_REG3_STEP0__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG3_STEP0__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG3_STEP0__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG3_STEP0__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG3_STEP0__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG3_STEP0__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG3_STEP0__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG3_STEP0__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG3_STEP0__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG3_STEP0__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG3_STEP0__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG3_STEP0__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG3_STEP0__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG3_STEP0__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG3_STEP0__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG3_STEP0__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG3_STEP1 (0x00BC4258) +#define DBG_GROUP0_REG3_STEP1___RWC QCSR_REG_RW +#define DBG_GROUP0_REG3_STEP1__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG3_STEP1__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG3_STEP1__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG3_STEP1__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG3_STEP1__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG3_STEP1__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG3_STEP1__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG3_STEP1__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG3_STEP1__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG3_STEP1__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG3_STEP1__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG3_STEP1__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG3_STEP1__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG3_STEP1__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG3_STEP1__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG3_STEP1__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG3_STEP2 (0x00BC4430) +#define DBG_GROUP0_REG3_STEP2___RWC QCSR_REG_RW +#define DBG_GROUP0_REG3_STEP2__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG3_STEP2__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG3_STEP2__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG3_STEP2__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG3_STEP2__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG3_STEP2__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG3_STEP2__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG3_STEP2__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG3_STEP2__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG3_STEP2__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG3_STEP2__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG3_STEP2__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG3_STEP2__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG3_STEP2__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG3_STEP2__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG3_STEP2__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG3_STEP3 (0x00BC4608) +#define DBG_GROUP0_REG3_STEP3___RWC QCSR_REG_RW +#define DBG_GROUP0_REG3_STEP3__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG3_STEP3__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG3_STEP3__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG3_STEP3__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG3_STEP3__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG3_STEP3__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG3_STEP3__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG3_STEP3__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG3_STEP3__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG3_STEP3__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG3_STEP3__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG3_STEP3__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG3_STEP3__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG3_STEP3__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG3_STEP3__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG3_STEP3__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG3_STEP4 (0x00BC47E0) +#define DBG_GROUP0_REG3_STEP4___RWC QCSR_REG_RW +#define DBG_GROUP0_REG3_STEP4__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG3_STEP4__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG3_STEP4__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG3_STEP4__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG3_STEP4__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG3_STEP4__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG3_STEP4__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG3_STEP4__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG3_STEP4__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG3_STEP4__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG3_STEP4__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG3_STEP4__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG3_STEP4__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG3_STEP4__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG3_STEP4__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG3_STEP4__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG3_STEP5 (0x00BC49B8) +#define DBG_GROUP0_REG3_STEP5___RWC QCSR_REG_RW +#define DBG_GROUP0_REG3_STEP5__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG3_STEP5__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG3_STEP5__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG3_STEP5__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG3_STEP5__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG3_STEP5__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG3_STEP5__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG3_STEP5__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG3_STEP5__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG3_STEP5__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG3_STEP5__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG3_STEP5__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG3_STEP5__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG3_STEP5__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG3_STEP5__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG3_STEP5__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG3_STEP6 (0x00BC4B90) +#define DBG_GROUP0_REG3_STEP6___RWC QCSR_REG_RW +#define DBG_GROUP0_REG3_STEP6__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG3_STEP6__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG3_STEP6__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG3_STEP6__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG3_STEP6__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG3_STEP6__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG3_STEP6__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG3_STEP6__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG3_STEP6__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG3_STEP6__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG3_STEP6__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG3_STEP6__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG3_STEP6__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG3_STEP6__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG3_STEP6__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG3_STEP6__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG3_STEP7 (0x00BC4D68) +#define DBG_GROUP0_REG3_STEP7___RWC QCSR_REG_RW +#define DBG_GROUP0_REG3_STEP7__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG3_STEP7__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG3_STEP7__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG3_STEP7__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG3_STEP7__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG3_STEP7__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG3_STEP7__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG3_STEP7__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG3_STEP7__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG3_STEP7__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG3_STEP7__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG3_STEP7__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG3_STEP7__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG3_STEP7__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG3_STEP7__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG3_STEP7__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG4_STEP0 (0x00BC4084) +#define DBG_GROUP0_REG4_STEP0___RWC QCSR_REG_RW +#define DBG_GROUP0_REG4_STEP0__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG4_STEP0__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG4_STEP0__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG4_STEP0__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG4_STEP0__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG4_STEP0__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG4_STEP0__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG4_STEP0__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG4_STEP0__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG4_STEP0__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG4_STEP0__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG4_STEP0__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG4_STEP0__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG4_STEP0__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG4_STEP0__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG4_STEP0__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG4_STEP1 (0x00BC425C) +#define DBG_GROUP0_REG4_STEP1___RWC QCSR_REG_RW +#define DBG_GROUP0_REG4_STEP1__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG4_STEP1__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG4_STEP1__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG4_STEP1__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG4_STEP1__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG4_STEP1__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG4_STEP1__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG4_STEP1__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG4_STEP1__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG4_STEP1__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG4_STEP1__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG4_STEP1__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG4_STEP1__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG4_STEP1__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG4_STEP1__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG4_STEP1__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG4_STEP2 (0x00BC4434) +#define DBG_GROUP0_REG4_STEP2___RWC QCSR_REG_RW +#define DBG_GROUP0_REG4_STEP2__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG4_STEP2__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG4_STEP2__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG4_STEP2__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG4_STEP2__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG4_STEP2__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG4_STEP2__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG4_STEP2__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG4_STEP2__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG4_STEP2__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG4_STEP2__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG4_STEP2__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG4_STEP2__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG4_STEP2__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG4_STEP2__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG4_STEP2__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG4_STEP3 (0x00BC460C) +#define DBG_GROUP0_REG4_STEP3___RWC QCSR_REG_RW +#define DBG_GROUP0_REG4_STEP3__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG4_STEP3__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG4_STEP3__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG4_STEP3__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG4_STEP3__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG4_STEP3__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG4_STEP3__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG4_STEP3__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG4_STEP3__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG4_STEP3__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG4_STEP3__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG4_STEP3__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG4_STEP3__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG4_STEP3__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG4_STEP3__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG4_STEP3__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG4_STEP4 (0x00BC47E4) +#define DBG_GROUP0_REG4_STEP4___RWC QCSR_REG_RW +#define DBG_GROUP0_REG4_STEP4__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG4_STEP4__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG4_STEP4__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG4_STEP4__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG4_STEP4__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG4_STEP4__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG4_STEP4__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG4_STEP4__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG4_STEP4__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG4_STEP4__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG4_STEP4__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG4_STEP4__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG4_STEP4__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG4_STEP4__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG4_STEP4__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG4_STEP4__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG4_STEP5 (0x00BC49BC) +#define DBG_GROUP0_REG4_STEP5___RWC QCSR_REG_RW +#define DBG_GROUP0_REG4_STEP5__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG4_STEP5__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG4_STEP5__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG4_STEP5__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG4_STEP5__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG4_STEP5__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG4_STEP5__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG4_STEP5__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG4_STEP5__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG4_STEP5__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG4_STEP5__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG4_STEP5__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG4_STEP5__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG4_STEP5__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG4_STEP5__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG4_STEP5__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG4_STEP6 (0x00BC4B94) +#define DBG_GROUP0_REG4_STEP6___RWC QCSR_REG_RW +#define DBG_GROUP0_REG4_STEP6__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG4_STEP6__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG4_STEP6__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG4_STEP6__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG4_STEP6__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG4_STEP6__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG4_STEP6__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG4_STEP6__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG4_STEP6__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG4_STEP6__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG4_STEP6__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG4_STEP6__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG4_STEP6__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG4_STEP6__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG4_STEP6__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG4_STEP6__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG4_STEP7 (0x00BC4D6C) +#define DBG_GROUP0_REG4_STEP7___RWC QCSR_REG_RW +#define DBG_GROUP0_REG4_STEP7__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG4_STEP7__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG4_STEP7__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG4_STEP7__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG4_STEP7__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG4_STEP7__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG4_STEP7__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG4_STEP7__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG4_STEP7__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG4_STEP7__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG4_STEP7__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG4_STEP7__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG4_STEP7__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG4_STEP7__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG4_STEP7__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG4_STEP7__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG5_STEP0 (0x00BC4088) +#define DBG_GROUP0_REG5_STEP0___RWC QCSR_REG_RW +#define DBG_GROUP0_REG5_STEP0__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG5_STEP0__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG5_STEP0__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG5_STEP0__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG5_STEP0__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG5_STEP0__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG5_STEP0__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG5_STEP0__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG5_STEP0__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG5_STEP0__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG5_STEP0__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG5_STEP0__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG5_STEP0__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG5_STEP0__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG5_STEP0__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG5_STEP0__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG5_STEP1 (0x00BC4260) +#define DBG_GROUP0_REG5_STEP1___RWC QCSR_REG_RW +#define DBG_GROUP0_REG5_STEP1__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG5_STEP1__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG5_STEP1__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG5_STEP1__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG5_STEP1__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG5_STEP1__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG5_STEP1__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG5_STEP1__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG5_STEP1__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG5_STEP1__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG5_STEP1__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG5_STEP1__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG5_STEP1__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG5_STEP1__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG5_STEP1__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG5_STEP1__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG5_STEP2 (0x00BC4438) +#define DBG_GROUP0_REG5_STEP2___RWC QCSR_REG_RW +#define DBG_GROUP0_REG5_STEP2__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG5_STEP2__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG5_STEP2__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG5_STEP2__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG5_STEP2__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG5_STEP2__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG5_STEP2__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG5_STEP2__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG5_STEP2__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG5_STEP2__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG5_STEP2__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG5_STEP2__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG5_STEP2__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG5_STEP2__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG5_STEP2__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG5_STEP2__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG5_STEP3 (0x00BC4610) +#define DBG_GROUP0_REG5_STEP3___RWC QCSR_REG_RW +#define DBG_GROUP0_REG5_STEP3__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG5_STEP3__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG5_STEP3__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG5_STEP3__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG5_STEP3__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG5_STEP3__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG5_STEP3__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG5_STEP3__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG5_STEP3__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG5_STEP3__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG5_STEP3__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG5_STEP3__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG5_STEP3__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG5_STEP3__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG5_STEP3__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG5_STEP3__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG5_STEP4 (0x00BC47E8) +#define DBG_GROUP0_REG5_STEP4___RWC QCSR_REG_RW +#define DBG_GROUP0_REG5_STEP4__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG5_STEP4__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG5_STEP4__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG5_STEP4__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG5_STEP4__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG5_STEP4__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG5_STEP4__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG5_STEP4__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG5_STEP4__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG5_STEP4__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG5_STEP4__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG5_STEP4__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG5_STEP4__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG5_STEP4__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG5_STEP4__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG5_STEP4__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG5_STEP5 (0x00BC49C0) +#define DBG_GROUP0_REG5_STEP5___RWC QCSR_REG_RW +#define DBG_GROUP0_REG5_STEP5__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG5_STEP5__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG5_STEP5__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG5_STEP5__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG5_STEP5__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG5_STEP5__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG5_STEP5__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG5_STEP5__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG5_STEP5__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG5_STEP5__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG5_STEP5__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG5_STEP5__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG5_STEP5__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG5_STEP5__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG5_STEP5__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG5_STEP5__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG5_STEP6 (0x00BC4B98) +#define DBG_GROUP0_REG5_STEP6___RWC QCSR_REG_RW +#define DBG_GROUP0_REG5_STEP6__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG5_STEP6__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG5_STEP6__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG5_STEP6__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG5_STEP6__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG5_STEP6__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG5_STEP6__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG5_STEP6__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG5_STEP6__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG5_STEP6__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG5_STEP6__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG5_STEP6__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG5_STEP6__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG5_STEP6__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG5_STEP6__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG5_STEP6__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REG5_STEP7 (0x00BC4D70) +#define DBG_GROUP0_REG5_STEP7___RWC QCSR_REG_RW +#define DBG_GROUP0_REG5_STEP7__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP0_REG5_STEP7__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP0_REG5_STEP7__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP0_REG5_STEP7__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP0_REG5_STEP7__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP0_REG5_STEP7__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP0_REG5_STEP7__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP0_REG5_STEP7__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP0_REG5_STEP7__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP0_REG5_STEP7__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP0_REG5_STEP7__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP0_REG5_STEP7__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP0_REG5_STEP7__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REG5_STEP7__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REG5_STEP7__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REG5_STEP7__SEL_BIT0_TYPE3___S 0 + +#define DBG_GROUP0_REGN_STEPn(n) (0x00BC408C+0x1D8*(n)) +#define DBG_GROUP0_REGN_STEPn_nMIN 0 +#define DBG_GROUP0_REGN_STEPn_nMAX 7 +#define DBG_GROUP0_REGN_STEPn_ELEM 8 +#define DBG_GROUP0_REGN_STEPn___RWC QCSR_REG_RW +#define DBG_GROUP0_REGN_STEPn___POR 0x00000000 +#define DBG_GROUP0_REGN_STEPn__SEL_BIT1_TYPE3___POR 0x0 +#define DBG_GROUP0_REGN_STEPn__SEL_BIT0_TYPE3___POR 0x0 +#define DBG_GROUP0_REGN_STEPn__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REGN_STEPn__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REGN_STEPn__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REGN_STEPn__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REGN_STEPn___M 0x00000077 +#define DBG_GROUP0_REGN_STEPn___S 0 +#define DBG_GROUP0_REGN_STEP0 (0x00BC408C) +#define DBG_GROUP0_REGN_STEP0___RWC QCSR_REG_RW +#define DBG_GROUP0_REGN_STEP0__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REGN_STEP0__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REGN_STEP0__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REGN_STEP0__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REGN_STEP1 (0x00BC4264) +#define DBG_GROUP0_REGN_STEP1___RWC QCSR_REG_RW +#define DBG_GROUP0_REGN_STEP1__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REGN_STEP1__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REGN_STEP1__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REGN_STEP1__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REGN_STEP2 (0x00BC443C) +#define DBG_GROUP0_REGN_STEP2___RWC QCSR_REG_RW +#define DBG_GROUP0_REGN_STEP2__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REGN_STEP2__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REGN_STEP2__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REGN_STEP2__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REGN_STEP3 (0x00BC4614) +#define DBG_GROUP0_REGN_STEP3___RWC QCSR_REG_RW +#define DBG_GROUP0_REGN_STEP3__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REGN_STEP3__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REGN_STEP3__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REGN_STEP3__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REGN_STEP4 (0x00BC47EC) +#define DBG_GROUP0_REGN_STEP4___RWC QCSR_REG_RW +#define DBG_GROUP0_REGN_STEP4__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REGN_STEP4__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REGN_STEP4__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REGN_STEP4__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REGN_STEP5 (0x00BC49C4) +#define DBG_GROUP0_REGN_STEP5___RWC QCSR_REG_RW +#define DBG_GROUP0_REGN_STEP5__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REGN_STEP5__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REGN_STEP5__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REGN_STEP5__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REGN_STEP6 (0x00BC4B9C) +#define DBG_GROUP0_REGN_STEP6___RWC QCSR_REG_RW +#define DBG_GROUP0_REGN_STEP6__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REGN_STEP6__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REGN_STEP6__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REGN_STEP6__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP0_REGN_STEP7 (0x00BC4D74) +#define DBG_GROUP0_REGN_STEP7___RWC QCSR_REG_RW +#define DBG_GROUP0_REGN_STEP7__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP0_REGN_STEP7__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP0_REGN_STEP7__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP0_REGN_STEP7__SEL_BIT0_TYPE3___S 0 + +#define DBG_GROUP1_REGm_STEPn(m,n) (0x00BC40D4+0x4*(m)+0x1D8*(n)) +#define DBG_GROUP1_REGm_STEPn_mMIN 0 +#define DBG_GROUP1_REGm_STEPn_mMAX 5 +#define DBG_GROUP1_REGm_STEPn_nMIN 0 +#define DBG_GROUP1_REGm_STEPn_nMAX 7 +#define DBG_GROUP1_REGm_STEPn_ELEM 48 +#define DBG_GROUP1_REGm_STEPn___RWC QCSR_REG_RW +#define DBG_GROUP1_REGm_STEPn___POR 0x00000000 +#define DBG_GROUP1_REGm_STEPn__SEL_BIT7_TYPE3___POR 0x0 +#define DBG_GROUP1_REGm_STEPn__SEL_BIT6_TYPE3___POR 0x0 +#define DBG_GROUP1_REGm_STEPn__SEL_BIT5_TYPE3___POR 0x0 +#define DBG_GROUP1_REGm_STEPn__SEL_BIT4_TYPE3___POR 0x0 +#define DBG_GROUP1_REGm_STEPn__SEL_BIT3_TYPE3___POR 0x0 +#define DBG_GROUP1_REGm_STEPn__SEL_BIT2_TYPE3___POR 0x0 +#define DBG_GROUP1_REGm_STEPn__SEL_BIT1_TYPE3___POR 0x0 +#define DBG_GROUP1_REGm_STEPn__SEL_BIT0_TYPE3___POR 0x0 +#define DBG_GROUP1_REGm_STEPn__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REGm_STEPn__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REGm_STEPn__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REGm_STEPn__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REGm_STEPn__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REGm_STEPn__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REGm_STEPn__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REGm_STEPn__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REGm_STEPn__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REGm_STEPn__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REGm_STEPn__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REGm_STEPn__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REGm_STEPn__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REGm_STEPn__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REGm_STEPn__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REGm_STEPn__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REGm_STEPn___M 0x77777777 +#define DBG_GROUP1_REGm_STEPn___S 0 +#define DBG_GROUP1_REG0_STEP0 (0x00BC40D4) +#define DBG_GROUP1_REG0_STEP0___RWC QCSR_REG_RW +#define DBG_GROUP1_REG0_STEP0__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG0_STEP0__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG0_STEP0__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG0_STEP0__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG0_STEP0__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG0_STEP0__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG0_STEP0__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG0_STEP0__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG0_STEP0__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG0_STEP0__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG0_STEP0__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG0_STEP0__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG0_STEP0__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG0_STEP0__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG0_STEP0__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG0_STEP0__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG0_STEP1 (0x00BC42AC) +#define DBG_GROUP1_REG0_STEP1___RWC QCSR_REG_RW +#define DBG_GROUP1_REG0_STEP1__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG0_STEP1__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG0_STEP1__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG0_STEP1__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG0_STEP1__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG0_STEP1__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG0_STEP1__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG0_STEP1__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG0_STEP1__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG0_STEP1__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG0_STEP1__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG0_STEP1__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG0_STEP1__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG0_STEP1__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG0_STEP1__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG0_STEP1__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG0_STEP2 (0x00BC4484) +#define DBG_GROUP1_REG0_STEP2___RWC QCSR_REG_RW +#define DBG_GROUP1_REG0_STEP2__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG0_STEP2__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG0_STEP2__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG0_STEP2__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG0_STEP2__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG0_STEP2__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG0_STEP2__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG0_STEP2__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG0_STEP2__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG0_STEP2__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG0_STEP2__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG0_STEP2__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG0_STEP2__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG0_STEP2__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG0_STEP2__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG0_STEP2__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG0_STEP3 (0x00BC465C) +#define DBG_GROUP1_REG0_STEP3___RWC QCSR_REG_RW +#define DBG_GROUP1_REG0_STEP3__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG0_STEP3__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG0_STEP3__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG0_STEP3__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG0_STEP3__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG0_STEP3__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG0_STEP3__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG0_STEP3__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG0_STEP3__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG0_STEP3__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG0_STEP3__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG0_STEP3__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG0_STEP3__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG0_STEP3__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG0_STEP3__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG0_STEP3__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG0_STEP4 (0x00BC4834) +#define DBG_GROUP1_REG0_STEP4___RWC QCSR_REG_RW +#define DBG_GROUP1_REG0_STEP4__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG0_STEP4__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG0_STEP4__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG0_STEP4__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG0_STEP4__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG0_STEP4__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG0_STEP4__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG0_STEP4__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG0_STEP4__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG0_STEP4__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG0_STEP4__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG0_STEP4__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG0_STEP4__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG0_STEP4__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG0_STEP4__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG0_STEP4__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG0_STEP5 (0x00BC4A0C) +#define DBG_GROUP1_REG0_STEP5___RWC QCSR_REG_RW +#define DBG_GROUP1_REG0_STEP5__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG0_STEP5__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG0_STEP5__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG0_STEP5__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG0_STEP5__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG0_STEP5__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG0_STEP5__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG0_STEP5__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG0_STEP5__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG0_STEP5__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG0_STEP5__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG0_STEP5__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG0_STEP5__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG0_STEP5__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG0_STEP5__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG0_STEP5__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG0_STEP6 (0x00BC4BE4) +#define DBG_GROUP1_REG0_STEP6___RWC QCSR_REG_RW +#define DBG_GROUP1_REG0_STEP6__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG0_STEP6__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG0_STEP6__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG0_STEP6__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG0_STEP6__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG0_STEP6__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG0_STEP6__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG0_STEP6__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG0_STEP6__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG0_STEP6__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG0_STEP6__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG0_STEP6__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG0_STEP6__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG0_STEP6__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG0_STEP6__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG0_STEP6__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG0_STEP7 (0x00BC4DBC) +#define DBG_GROUP1_REG0_STEP7___RWC QCSR_REG_RW +#define DBG_GROUP1_REG0_STEP7__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG0_STEP7__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG0_STEP7__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG0_STEP7__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG0_STEP7__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG0_STEP7__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG0_STEP7__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG0_STEP7__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG0_STEP7__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG0_STEP7__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG0_STEP7__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG0_STEP7__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG0_STEP7__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG0_STEP7__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG0_STEP7__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG0_STEP7__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG1_STEP0 (0x00BC40D8) +#define DBG_GROUP1_REG1_STEP0___RWC QCSR_REG_RW +#define DBG_GROUP1_REG1_STEP0__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG1_STEP0__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG1_STEP0__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG1_STEP0__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG1_STEP0__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG1_STEP0__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG1_STEP0__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG1_STEP0__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG1_STEP0__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG1_STEP0__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG1_STEP0__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG1_STEP0__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG1_STEP0__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG1_STEP0__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG1_STEP0__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG1_STEP0__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG1_STEP1 (0x00BC42B0) +#define DBG_GROUP1_REG1_STEP1___RWC QCSR_REG_RW +#define DBG_GROUP1_REG1_STEP1__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG1_STEP1__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG1_STEP1__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG1_STEP1__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG1_STEP1__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG1_STEP1__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG1_STEP1__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG1_STEP1__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG1_STEP1__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG1_STEP1__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG1_STEP1__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG1_STEP1__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG1_STEP1__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG1_STEP1__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG1_STEP1__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG1_STEP1__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG1_STEP2 (0x00BC4488) +#define DBG_GROUP1_REG1_STEP2___RWC QCSR_REG_RW +#define DBG_GROUP1_REG1_STEP2__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG1_STEP2__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG1_STEP2__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG1_STEP2__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG1_STEP2__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG1_STEP2__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG1_STEP2__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG1_STEP2__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG1_STEP2__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG1_STEP2__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG1_STEP2__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG1_STEP2__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG1_STEP2__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG1_STEP2__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG1_STEP2__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG1_STEP2__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG1_STEP3 (0x00BC4660) +#define DBG_GROUP1_REG1_STEP3___RWC QCSR_REG_RW +#define DBG_GROUP1_REG1_STEP3__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG1_STEP3__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG1_STEP3__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG1_STEP3__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG1_STEP3__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG1_STEP3__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG1_STEP3__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG1_STEP3__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG1_STEP3__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG1_STEP3__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG1_STEP3__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG1_STEP3__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG1_STEP3__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG1_STEP3__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG1_STEP3__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG1_STEP3__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG1_STEP4 (0x00BC4838) +#define DBG_GROUP1_REG1_STEP4___RWC QCSR_REG_RW +#define DBG_GROUP1_REG1_STEP4__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG1_STEP4__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG1_STEP4__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG1_STEP4__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG1_STEP4__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG1_STEP4__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG1_STEP4__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG1_STEP4__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG1_STEP4__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG1_STEP4__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG1_STEP4__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG1_STEP4__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG1_STEP4__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG1_STEP4__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG1_STEP4__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG1_STEP4__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG1_STEP5 (0x00BC4A10) +#define DBG_GROUP1_REG1_STEP5___RWC QCSR_REG_RW +#define DBG_GROUP1_REG1_STEP5__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG1_STEP5__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG1_STEP5__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG1_STEP5__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG1_STEP5__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG1_STEP5__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG1_STEP5__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG1_STEP5__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG1_STEP5__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG1_STEP5__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG1_STEP5__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG1_STEP5__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG1_STEP5__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG1_STEP5__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG1_STEP5__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG1_STEP5__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG1_STEP6 (0x00BC4BE8) +#define DBG_GROUP1_REG1_STEP6___RWC QCSR_REG_RW +#define DBG_GROUP1_REG1_STEP6__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG1_STEP6__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG1_STEP6__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG1_STEP6__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG1_STEP6__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG1_STEP6__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG1_STEP6__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG1_STEP6__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG1_STEP6__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG1_STEP6__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG1_STEP6__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG1_STEP6__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG1_STEP6__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG1_STEP6__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG1_STEP6__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG1_STEP6__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG1_STEP7 (0x00BC4DC0) +#define DBG_GROUP1_REG1_STEP7___RWC QCSR_REG_RW +#define DBG_GROUP1_REG1_STEP7__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG1_STEP7__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG1_STEP7__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG1_STEP7__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG1_STEP7__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG1_STEP7__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG1_STEP7__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG1_STEP7__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG1_STEP7__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG1_STEP7__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG1_STEP7__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG1_STEP7__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG1_STEP7__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG1_STEP7__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG1_STEP7__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG1_STEP7__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG2_STEP0 (0x00BC40DC) +#define DBG_GROUP1_REG2_STEP0___RWC QCSR_REG_RW +#define DBG_GROUP1_REG2_STEP0__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG2_STEP0__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG2_STEP0__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG2_STEP0__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG2_STEP0__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG2_STEP0__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG2_STEP0__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG2_STEP0__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG2_STEP0__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG2_STEP0__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG2_STEP0__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG2_STEP0__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG2_STEP0__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG2_STEP0__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG2_STEP0__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG2_STEP0__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG2_STEP1 (0x00BC42B4) +#define DBG_GROUP1_REG2_STEP1___RWC QCSR_REG_RW +#define DBG_GROUP1_REG2_STEP1__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG2_STEP1__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG2_STEP1__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG2_STEP1__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG2_STEP1__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG2_STEP1__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG2_STEP1__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG2_STEP1__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG2_STEP1__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG2_STEP1__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG2_STEP1__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG2_STEP1__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG2_STEP1__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG2_STEP1__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG2_STEP1__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG2_STEP1__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG2_STEP2 (0x00BC448C) +#define DBG_GROUP1_REG2_STEP2___RWC QCSR_REG_RW +#define DBG_GROUP1_REG2_STEP2__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG2_STEP2__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG2_STEP2__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG2_STEP2__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG2_STEP2__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG2_STEP2__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG2_STEP2__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG2_STEP2__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG2_STEP2__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG2_STEP2__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG2_STEP2__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG2_STEP2__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG2_STEP2__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG2_STEP2__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG2_STEP2__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG2_STEP2__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG2_STEP3 (0x00BC4664) +#define DBG_GROUP1_REG2_STEP3___RWC QCSR_REG_RW +#define DBG_GROUP1_REG2_STEP3__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG2_STEP3__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG2_STEP3__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG2_STEP3__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG2_STEP3__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG2_STEP3__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG2_STEP3__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG2_STEP3__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG2_STEP3__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG2_STEP3__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG2_STEP3__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG2_STEP3__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG2_STEP3__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG2_STEP3__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG2_STEP3__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG2_STEP3__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG2_STEP4 (0x00BC483C) +#define DBG_GROUP1_REG2_STEP4___RWC QCSR_REG_RW +#define DBG_GROUP1_REG2_STEP4__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG2_STEP4__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG2_STEP4__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG2_STEP4__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG2_STEP4__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG2_STEP4__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG2_STEP4__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG2_STEP4__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG2_STEP4__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG2_STEP4__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG2_STEP4__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG2_STEP4__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG2_STEP4__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG2_STEP4__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG2_STEP4__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG2_STEP4__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG2_STEP5 (0x00BC4A14) +#define DBG_GROUP1_REG2_STEP5___RWC QCSR_REG_RW +#define DBG_GROUP1_REG2_STEP5__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG2_STEP5__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG2_STEP5__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG2_STEP5__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG2_STEP5__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG2_STEP5__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG2_STEP5__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG2_STEP5__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG2_STEP5__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG2_STEP5__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG2_STEP5__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG2_STEP5__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG2_STEP5__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG2_STEP5__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG2_STEP5__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG2_STEP5__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG2_STEP6 (0x00BC4BEC) +#define DBG_GROUP1_REG2_STEP6___RWC QCSR_REG_RW +#define DBG_GROUP1_REG2_STEP6__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG2_STEP6__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG2_STEP6__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG2_STEP6__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG2_STEP6__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG2_STEP6__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG2_STEP6__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG2_STEP6__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG2_STEP6__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG2_STEP6__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG2_STEP6__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG2_STEP6__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG2_STEP6__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG2_STEP6__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG2_STEP6__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG2_STEP6__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG2_STEP7 (0x00BC4DC4) +#define DBG_GROUP1_REG2_STEP7___RWC QCSR_REG_RW +#define DBG_GROUP1_REG2_STEP7__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG2_STEP7__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG2_STEP7__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG2_STEP7__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG2_STEP7__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG2_STEP7__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG2_STEP7__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG2_STEP7__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG2_STEP7__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG2_STEP7__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG2_STEP7__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG2_STEP7__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG2_STEP7__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG2_STEP7__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG2_STEP7__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG2_STEP7__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG3_STEP0 (0x00BC40E0) +#define DBG_GROUP1_REG3_STEP0___RWC QCSR_REG_RW +#define DBG_GROUP1_REG3_STEP0__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG3_STEP0__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG3_STEP0__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG3_STEP0__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG3_STEP0__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG3_STEP0__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG3_STEP0__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG3_STEP0__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG3_STEP0__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG3_STEP0__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG3_STEP0__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG3_STEP0__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG3_STEP0__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG3_STEP0__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG3_STEP0__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG3_STEP0__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG3_STEP1 (0x00BC42B8) +#define DBG_GROUP1_REG3_STEP1___RWC QCSR_REG_RW +#define DBG_GROUP1_REG3_STEP1__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG3_STEP1__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG3_STEP1__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG3_STEP1__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG3_STEP1__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG3_STEP1__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG3_STEP1__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG3_STEP1__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG3_STEP1__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG3_STEP1__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG3_STEP1__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG3_STEP1__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG3_STEP1__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG3_STEP1__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG3_STEP1__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG3_STEP1__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG3_STEP2 (0x00BC4490) +#define DBG_GROUP1_REG3_STEP2___RWC QCSR_REG_RW +#define DBG_GROUP1_REG3_STEP2__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG3_STEP2__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG3_STEP2__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG3_STEP2__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG3_STEP2__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG3_STEP2__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG3_STEP2__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG3_STEP2__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG3_STEP2__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG3_STEP2__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG3_STEP2__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG3_STEP2__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG3_STEP2__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG3_STEP2__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG3_STEP2__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG3_STEP2__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG3_STEP3 (0x00BC4668) +#define DBG_GROUP1_REG3_STEP3___RWC QCSR_REG_RW +#define DBG_GROUP1_REG3_STEP3__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG3_STEP3__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG3_STEP3__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG3_STEP3__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG3_STEP3__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG3_STEP3__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG3_STEP3__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG3_STEP3__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG3_STEP3__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG3_STEP3__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG3_STEP3__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG3_STEP3__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG3_STEP3__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG3_STEP3__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG3_STEP3__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG3_STEP3__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG3_STEP4 (0x00BC4840) +#define DBG_GROUP1_REG3_STEP4___RWC QCSR_REG_RW +#define DBG_GROUP1_REG3_STEP4__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG3_STEP4__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG3_STEP4__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG3_STEP4__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG3_STEP4__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG3_STEP4__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG3_STEP4__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG3_STEP4__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG3_STEP4__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG3_STEP4__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG3_STEP4__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG3_STEP4__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG3_STEP4__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG3_STEP4__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG3_STEP4__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG3_STEP4__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG3_STEP5 (0x00BC4A18) +#define DBG_GROUP1_REG3_STEP5___RWC QCSR_REG_RW +#define DBG_GROUP1_REG3_STEP5__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG3_STEP5__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG3_STEP5__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG3_STEP5__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG3_STEP5__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG3_STEP5__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG3_STEP5__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG3_STEP5__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG3_STEP5__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG3_STEP5__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG3_STEP5__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG3_STEP5__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG3_STEP5__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG3_STEP5__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG3_STEP5__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG3_STEP5__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG3_STEP6 (0x00BC4BF0) +#define DBG_GROUP1_REG3_STEP6___RWC QCSR_REG_RW +#define DBG_GROUP1_REG3_STEP6__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG3_STEP6__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG3_STEP6__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG3_STEP6__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG3_STEP6__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG3_STEP6__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG3_STEP6__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG3_STEP6__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG3_STEP6__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG3_STEP6__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG3_STEP6__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG3_STEP6__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG3_STEP6__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG3_STEP6__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG3_STEP6__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG3_STEP6__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG3_STEP7 (0x00BC4DC8) +#define DBG_GROUP1_REG3_STEP7___RWC QCSR_REG_RW +#define DBG_GROUP1_REG3_STEP7__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG3_STEP7__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG3_STEP7__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG3_STEP7__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG3_STEP7__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG3_STEP7__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG3_STEP7__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG3_STEP7__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG3_STEP7__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG3_STEP7__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG3_STEP7__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG3_STEP7__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG3_STEP7__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG3_STEP7__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG3_STEP7__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG3_STEP7__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG4_STEP0 (0x00BC40E4) +#define DBG_GROUP1_REG4_STEP0___RWC QCSR_REG_RW +#define DBG_GROUP1_REG4_STEP0__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG4_STEP0__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG4_STEP0__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG4_STEP0__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG4_STEP0__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG4_STEP0__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG4_STEP0__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG4_STEP0__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG4_STEP0__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG4_STEP0__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG4_STEP0__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG4_STEP0__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG4_STEP0__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG4_STEP0__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG4_STEP0__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG4_STEP0__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG4_STEP1 (0x00BC42BC) +#define DBG_GROUP1_REG4_STEP1___RWC QCSR_REG_RW +#define DBG_GROUP1_REG4_STEP1__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG4_STEP1__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG4_STEP1__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG4_STEP1__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG4_STEP1__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG4_STEP1__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG4_STEP1__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG4_STEP1__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG4_STEP1__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG4_STEP1__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG4_STEP1__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG4_STEP1__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG4_STEP1__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG4_STEP1__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG4_STEP1__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG4_STEP1__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG4_STEP2 (0x00BC4494) +#define DBG_GROUP1_REG4_STEP2___RWC QCSR_REG_RW +#define DBG_GROUP1_REG4_STEP2__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG4_STEP2__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG4_STEP2__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG4_STEP2__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG4_STEP2__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG4_STEP2__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG4_STEP2__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG4_STEP2__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG4_STEP2__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG4_STEP2__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG4_STEP2__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG4_STEP2__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG4_STEP2__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG4_STEP2__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG4_STEP2__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG4_STEP2__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG4_STEP3 (0x00BC466C) +#define DBG_GROUP1_REG4_STEP3___RWC QCSR_REG_RW +#define DBG_GROUP1_REG4_STEP3__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG4_STEP3__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG4_STEP3__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG4_STEP3__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG4_STEP3__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG4_STEP3__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG4_STEP3__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG4_STEP3__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG4_STEP3__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG4_STEP3__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG4_STEP3__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG4_STEP3__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG4_STEP3__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG4_STEP3__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG4_STEP3__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG4_STEP3__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG4_STEP4 (0x00BC4844) +#define DBG_GROUP1_REG4_STEP4___RWC QCSR_REG_RW +#define DBG_GROUP1_REG4_STEP4__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG4_STEP4__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG4_STEP4__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG4_STEP4__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG4_STEP4__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG4_STEP4__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG4_STEP4__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG4_STEP4__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG4_STEP4__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG4_STEP4__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG4_STEP4__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG4_STEP4__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG4_STEP4__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG4_STEP4__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG4_STEP4__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG4_STEP4__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG4_STEP5 (0x00BC4A1C) +#define DBG_GROUP1_REG4_STEP5___RWC QCSR_REG_RW +#define DBG_GROUP1_REG4_STEP5__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG4_STEP5__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG4_STEP5__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG4_STEP5__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG4_STEP5__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG4_STEP5__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG4_STEP5__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG4_STEP5__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG4_STEP5__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG4_STEP5__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG4_STEP5__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG4_STEP5__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG4_STEP5__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG4_STEP5__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG4_STEP5__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG4_STEP5__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG4_STEP6 (0x00BC4BF4) +#define DBG_GROUP1_REG4_STEP6___RWC QCSR_REG_RW +#define DBG_GROUP1_REG4_STEP6__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG4_STEP6__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG4_STEP6__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG4_STEP6__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG4_STEP6__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG4_STEP6__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG4_STEP6__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG4_STEP6__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG4_STEP6__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG4_STEP6__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG4_STEP6__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG4_STEP6__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG4_STEP6__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG4_STEP6__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG4_STEP6__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG4_STEP6__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG4_STEP7 (0x00BC4DCC) +#define DBG_GROUP1_REG4_STEP7___RWC QCSR_REG_RW +#define DBG_GROUP1_REG4_STEP7__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG4_STEP7__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG4_STEP7__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG4_STEP7__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG4_STEP7__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG4_STEP7__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG4_STEP7__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG4_STEP7__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG4_STEP7__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG4_STEP7__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG4_STEP7__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG4_STEP7__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG4_STEP7__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG4_STEP7__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG4_STEP7__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG4_STEP7__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG5_STEP0 (0x00BC40E8) +#define DBG_GROUP1_REG5_STEP0___RWC QCSR_REG_RW +#define DBG_GROUP1_REG5_STEP0__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG5_STEP0__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG5_STEP0__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG5_STEP0__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG5_STEP0__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG5_STEP0__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG5_STEP0__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG5_STEP0__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG5_STEP0__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG5_STEP0__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG5_STEP0__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG5_STEP0__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG5_STEP0__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG5_STEP0__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG5_STEP0__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG5_STEP0__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG5_STEP1 (0x00BC42C0) +#define DBG_GROUP1_REG5_STEP1___RWC QCSR_REG_RW +#define DBG_GROUP1_REG5_STEP1__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG5_STEP1__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG5_STEP1__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG5_STEP1__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG5_STEP1__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG5_STEP1__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG5_STEP1__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG5_STEP1__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG5_STEP1__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG5_STEP1__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG5_STEP1__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG5_STEP1__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG5_STEP1__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG5_STEP1__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG5_STEP1__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG5_STEP1__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG5_STEP2 (0x00BC4498) +#define DBG_GROUP1_REG5_STEP2___RWC QCSR_REG_RW +#define DBG_GROUP1_REG5_STEP2__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG5_STEP2__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG5_STEP2__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG5_STEP2__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG5_STEP2__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG5_STEP2__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG5_STEP2__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG5_STEP2__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG5_STEP2__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG5_STEP2__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG5_STEP2__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG5_STEP2__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG5_STEP2__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG5_STEP2__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG5_STEP2__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG5_STEP2__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG5_STEP3 (0x00BC4670) +#define DBG_GROUP1_REG5_STEP3___RWC QCSR_REG_RW +#define DBG_GROUP1_REG5_STEP3__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG5_STEP3__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG5_STEP3__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG5_STEP3__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG5_STEP3__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG5_STEP3__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG5_STEP3__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG5_STEP3__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG5_STEP3__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG5_STEP3__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG5_STEP3__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG5_STEP3__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG5_STEP3__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG5_STEP3__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG5_STEP3__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG5_STEP3__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG5_STEP4 (0x00BC4848) +#define DBG_GROUP1_REG5_STEP4___RWC QCSR_REG_RW +#define DBG_GROUP1_REG5_STEP4__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG5_STEP4__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG5_STEP4__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG5_STEP4__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG5_STEP4__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG5_STEP4__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG5_STEP4__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG5_STEP4__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG5_STEP4__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG5_STEP4__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG5_STEP4__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG5_STEP4__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG5_STEP4__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG5_STEP4__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG5_STEP4__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG5_STEP4__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG5_STEP5 (0x00BC4A20) +#define DBG_GROUP1_REG5_STEP5___RWC QCSR_REG_RW +#define DBG_GROUP1_REG5_STEP5__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG5_STEP5__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG5_STEP5__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG5_STEP5__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG5_STEP5__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG5_STEP5__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG5_STEP5__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG5_STEP5__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG5_STEP5__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG5_STEP5__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG5_STEP5__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG5_STEP5__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG5_STEP5__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG5_STEP5__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG5_STEP5__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG5_STEP5__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG5_STEP6 (0x00BC4BF8) +#define DBG_GROUP1_REG5_STEP6___RWC QCSR_REG_RW +#define DBG_GROUP1_REG5_STEP6__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG5_STEP6__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG5_STEP6__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG5_STEP6__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG5_STEP6__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG5_STEP6__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG5_STEP6__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG5_STEP6__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG5_STEP6__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG5_STEP6__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG5_STEP6__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG5_STEP6__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG5_STEP6__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG5_STEP6__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG5_STEP6__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG5_STEP6__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REG5_STEP7 (0x00BC4DD0) +#define DBG_GROUP1_REG5_STEP7___RWC QCSR_REG_RW +#define DBG_GROUP1_REG5_STEP7__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP1_REG5_STEP7__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP1_REG5_STEP7__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP1_REG5_STEP7__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP1_REG5_STEP7__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP1_REG5_STEP7__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP1_REG5_STEP7__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP1_REG5_STEP7__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP1_REG5_STEP7__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP1_REG5_STEP7__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP1_REG5_STEP7__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP1_REG5_STEP7__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP1_REG5_STEP7__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REG5_STEP7__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REG5_STEP7__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REG5_STEP7__SEL_BIT0_TYPE3___S 0 + +#define DBG_GROUP1_REGN_STEPn(n) (0x00BC40EC+0x1D8*(n)) +#define DBG_GROUP1_REGN_STEPn_nMIN 0 +#define DBG_GROUP1_REGN_STEPn_nMAX 7 +#define DBG_GROUP1_REGN_STEPn_ELEM 8 +#define DBG_GROUP1_REGN_STEPn___RWC QCSR_REG_RW +#define DBG_GROUP1_REGN_STEPn___POR 0x00000000 +#define DBG_GROUP1_REGN_STEPn__SEL_BIT1_TYPE3___POR 0x0 +#define DBG_GROUP1_REGN_STEPn__SEL_BIT0_TYPE3___POR 0x0 +#define DBG_GROUP1_REGN_STEPn__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REGN_STEPn__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REGN_STEPn__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REGN_STEPn__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REGN_STEPn___M 0x00000077 +#define DBG_GROUP1_REGN_STEPn___S 0 +#define DBG_GROUP1_REGN_STEP0 (0x00BC40EC) +#define DBG_GROUP1_REGN_STEP0___RWC QCSR_REG_RW +#define DBG_GROUP1_REGN_STEP0__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REGN_STEP0__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REGN_STEP0__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REGN_STEP0__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REGN_STEP1 (0x00BC42C4) +#define DBG_GROUP1_REGN_STEP1___RWC QCSR_REG_RW +#define DBG_GROUP1_REGN_STEP1__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REGN_STEP1__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REGN_STEP1__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REGN_STEP1__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REGN_STEP2 (0x00BC449C) +#define DBG_GROUP1_REGN_STEP2___RWC QCSR_REG_RW +#define DBG_GROUP1_REGN_STEP2__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REGN_STEP2__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REGN_STEP2__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REGN_STEP2__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REGN_STEP3 (0x00BC4674) +#define DBG_GROUP1_REGN_STEP3___RWC QCSR_REG_RW +#define DBG_GROUP1_REGN_STEP3__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REGN_STEP3__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REGN_STEP3__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REGN_STEP3__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REGN_STEP4 (0x00BC484C) +#define DBG_GROUP1_REGN_STEP4___RWC QCSR_REG_RW +#define DBG_GROUP1_REGN_STEP4__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REGN_STEP4__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REGN_STEP4__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REGN_STEP4__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REGN_STEP5 (0x00BC4A24) +#define DBG_GROUP1_REGN_STEP5___RWC QCSR_REG_RW +#define DBG_GROUP1_REGN_STEP5__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REGN_STEP5__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REGN_STEP5__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REGN_STEP5__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REGN_STEP6 (0x00BC4BFC) +#define DBG_GROUP1_REGN_STEP6___RWC QCSR_REG_RW +#define DBG_GROUP1_REGN_STEP6__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REGN_STEP6__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REGN_STEP6__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REGN_STEP6__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP1_REGN_STEP7 (0x00BC4DD4) +#define DBG_GROUP1_REGN_STEP7___RWC QCSR_REG_RW +#define DBG_GROUP1_REGN_STEP7__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP1_REGN_STEP7__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP1_REGN_STEP7__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP1_REGN_STEP7__SEL_BIT0_TYPE3___S 0 + +#define DBG_GROUP2_REGm_STEPn(m,n) (0x00BC4134+0x4*(m)+0x1D8*(n)) +#define DBG_GROUP2_REGm_STEPn_mMIN 0 +#define DBG_GROUP2_REGm_STEPn_mMAX 5 +#define DBG_GROUP2_REGm_STEPn_nMIN 0 +#define DBG_GROUP2_REGm_STEPn_nMAX 7 +#define DBG_GROUP2_REGm_STEPn_ELEM 48 +#define DBG_GROUP2_REGm_STEPn___RWC QCSR_REG_RW +#define DBG_GROUP2_REGm_STEPn___POR 0x00000000 +#define DBG_GROUP2_REGm_STEPn__SEL_BIT7_TYPE3___POR 0x0 +#define DBG_GROUP2_REGm_STEPn__SEL_BIT6_TYPE3___POR 0x0 +#define DBG_GROUP2_REGm_STEPn__SEL_BIT5_TYPE3___POR 0x0 +#define DBG_GROUP2_REGm_STEPn__SEL_BIT4_TYPE3___POR 0x0 +#define DBG_GROUP2_REGm_STEPn__SEL_BIT3_TYPE3___POR 0x0 +#define DBG_GROUP2_REGm_STEPn__SEL_BIT2_TYPE3___POR 0x0 +#define DBG_GROUP2_REGm_STEPn__SEL_BIT1_TYPE3___POR 0x0 +#define DBG_GROUP2_REGm_STEPn__SEL_BIT0_TYPE3___POR 0x0 +#define DBG_GROUP2_REGm_STEPn__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REGm_STEPn__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REGm_STEPn__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REGm_STEPn__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REGm_STEPn__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REGm_STEPn__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REGm_STEPn__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REGm_STEPn__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REGm_STEPn__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REGm_STEPn__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REGm_STEPn__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REGm_STEPn__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REGm_STEPn__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REGm_STEPn__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REGm_STEPn__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REGm_STEPn__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REGm_STEPn___M 0x77777777 +#define DBG_GROUP2_REGm_STEPn___S 0 +#define DBG_GROUP2_REG0_STEP0 (0x00BC4134) +#define DBG_GROUP2_REG0_STEP0___RWC QCSR_REG_RW +#define DBG_GROUP2_REG0_STEP0__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG0_STEP0__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG0_STEP0__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG0_STEP0__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG0_STEP0__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG0_STEP0__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG0_STEP0__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG0_STEP0__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG0_STEP0__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG0_STEP0__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG0_STEP0__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG0_STEP0__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG0_STEP0__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG0_STEP0__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG0_STEP0__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG0_STEP0__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG0_STEP1 (0x00BC430C) +#define DBG_GROUP2_REG0_STEP1___RWC QCSR_REG_RW +#define DBG_GROUP2_REG0_STEP1__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG0_STEP1__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG0_STEP1__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG0_STEP1__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG0_STEP1__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG0_STEP1__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG0_STEP1__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG0_STEP1__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG0_STEP1__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG0_STEP1__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG0_STEP1__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG0_STEP1__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG0_STEP1__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG0_STEP1__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG0_STEP1__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG0_STEP1__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG0_STEP2 (0x00BC44E4) +#define DBG_GROUP2_REG0_STEP2___RWC QCSR_REG_RW +#define DBG_GROUP2_REG0_STEP2__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG0_STEP2__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG0_STEP2__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG0_STEP2__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG0_STEP2__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG0_STEP2__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG0_STEP2__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG0_STEP2__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG0_STEP2__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG0_STEP2__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG0_STEP2__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG0_STEP2__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG0_STEP2__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG0_STEP2__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG0_STEP2__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG0_STEP2__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG0_STEP3 (0x00BC46BC) +#define DBG_GROUP2_REG0_STEP3___RWC QCSR_REG_RW +#define DBG_GROUP2_REG0_STEP3__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG0_STEP3__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG0_STEP3__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG0_STEP3__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG0_STEP3__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG0_STEP3__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG0_STEP3__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG0_STEP3__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG0_STEP3__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG0_STEP3__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG0_STEP3__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG0_STEP3__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG0_STEP3__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG0_STEP3__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG0_STEP3__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG0_STEP3__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG0_STEP4 (0x00BC4894) +#define DBG_GROUP2_REG0_STEP4___RWC QCSR_REG_RW +#define DBG_GROUP2_REG0_STEP4__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG0_STEP4__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG0_STEP4__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG0_STEP4__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG0_STEP4__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG0_STEP4__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG0_STEP4__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG0_STEP4__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG0_STEP4__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG0_STEP4__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG0_STEP4__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG0_STEP4__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG0_STEP4__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG0_STEP4__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG0_STEP4__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG0_STEP4__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG0_STEP5 (0x00BC4A6C) +#define DBG_GROUP2_REG0_STEP5___RWC QCSR_REG_RW +#define DBG_GROUP2_REG0_STEP5__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG0_STEP5__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG0_STEP5__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG0_STEP5__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG0_STEP5__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG0_STEP5__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG0_STEP5__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG0_STEP5__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG0_STEP5__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG0_STEP5__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG0_STEP5__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG0_STEP5__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG0_STEP5__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG0_STEP5__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG0_STEP5__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG0_STEP5__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG0_STEP6 (0x00BC4C44) +#define DBG_GROUP2_REG0_STEP6___RWC QCSR_REG_RW +#define DBG_GROUP2_REG0_STEP6__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG0_STEP6__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG0_STEP6__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG0_STEP6__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG0_STEP6__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG0_STEP6__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG0_STEP6__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG0_STEP6__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG0_STEP6__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG0_STEP6__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG0_STEP6__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG0_STEP6__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG0_STEP6__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG0_STEP6__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG0_STEP6__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG0_STEP6__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG0_STEP7 (0x00BC4E1C) +#define DBG_GROUP2_REG0_STEP7___RWC QCSR_REG_RW +#define DBG_GROUP2_REG0_STEP7__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG0_STEP7__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG0_STEP7__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG0_STEP7__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG0_STEP7__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG0_STEP7__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG0_STEP7__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG0_STEP7__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG0_STEP7__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG0_STEP7__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG0_STEP7__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG0_STEP7__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG0_STEP7__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG0_STEP7__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG0_STEP7__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG0_STEP7__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG1_STEP0 (0x00BC4138) +#define DBG_GROUP2_REG1_STEP0___RWC QCSR_REG_RW +#define DBG_GROUP2_REG1_STEP0__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG1_STEP0__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG1_STEP0__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG1_STEP0__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG1_STEP0__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG1_STEP0__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG1_STEP0__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG1_STEP0__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG1_STEP0__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG1_STEP0__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG1_STEP0__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG1_STEP0__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG1_STEP0__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG1_STEP0__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG1_STEP0__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG1_STEP0__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG1_STEP1 (0x00BC4310) +#define DBG_GROUP2_REG1_STEP1___RWC QCSR_REG_RW +#define DBG_GROUP2_REG1_STEP1__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG1_STEP1__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG1_STEP1__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG1_STEP1__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG1_STEP1__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG1_STEP1__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG1_STEP1__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG1_STEP1__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG1_STEP1__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG1_STEP1__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG1_STEP1__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG1_STEP1__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG1_STEP1__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG1_STEP1__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG1_STEP1__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG1_STEP1__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG1_STEP2 (0x00BC44E8) +#define DBG_GROUP2_REG1_STEP2___RWC QCSR_REG_RW +#define DBG_GROUP2_REG1_STEP2__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG1_STEP2__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG1_STEP2__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG1_STEP2__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG1_STEP2__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG1_STEP2__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG1_STEP2__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG1_STEP2__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG1_STEP2__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG1_STEP2__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG1_STEP2__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG1_STEP2__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG1_STEP2__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG1_STEP2__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG1_STEP2__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG1_STEP2__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG1_STEP3 (0x00BC46C0) +#define DBG_GROUP2_REG1_STEP3___RWC QCSR_REG_RW +#define DBG_GROUP2_REG1_STEP3__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG1_STEP3__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG1_STEP3__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG1_STEP3__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG1_STEP3__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG1_STEP3__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG1_STEP3__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG1_STEP3__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG1_STEP3__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG1_STEP3__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG1_STEP3__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG1_STEP3__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG1_STEP3__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG1_STEP3__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG1_STEP3__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG1_STEP3__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG1_STEP4 (0x00BC4898) +#define DBG_GROUP2_REG1_STEP4___RWC QCSR_REG_RW +#define DBG_GROUP2_REG1_STEP4__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG1_STEP4__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG1_STEP4__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG1_STEP4__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG1_STEP4__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG1_STEP4__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG1_STEP4__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG1_STEP4__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG1_STEP4__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG1_STEP4__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG1_STEP4__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG1_STEP4__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG1_STEP4__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG1_STEP4__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG1_STEP4__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG1_STEP4__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG1_STEP5 (0x00BC4A70) +#define DBG_GROUP2_REG1_STEP5___RWC QCSR_REG_RW +#define DBG_GROUP2_REG1_STEP5__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG1_STEP5__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG1_STEP5__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG1_STEP5__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG1_STEP5__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG1_STEP5__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG1_STEP5__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG1_STEP5__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG1_STEP5__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG1_STEP5__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG1_STEP5__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG1_STEP5__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG1_STEP5__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG1_STEP5__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG1_STEP5__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG1_STEP5__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG1_STEP6 (0x00BC4C48) +#define DBG_GROUP2_REG1_STEP6___RWC QCSR_REG_RW +#define DBG_GROUP2_REG1_STEP6__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG1_STEP6__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG1_STEP6__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG1_STEP6__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG1_STEP6__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG1_STEP6__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG1_STEP6__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG1_STEP6__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG1_STEP6__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG1_STEP6__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG1_STEP6__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG1_STEP6__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG1_STEP6__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG1_STEP6__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG1_STEP6__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG1_STEP6__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG1_STEP7 (0x00BC4E20) +#define DBG_GROUP2_REG1_STEP7___RWC QCSR_REG_RW +#define DBG_GROUP2_REG1_STEP7__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG1_STEP7__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG1_STEP7__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG1_STEP7__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG1_STEP7__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG1_STEP7__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG1_STEP7__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG1_STEP7__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG1_STEP7__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG1_STEP7__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG1_STEP7__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG1_STEP7__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG1_STEP7__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG1_STEP7__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG1_STEP7__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG1_STEP7__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG2_STEP0 (0x00BC413C) +#define DBG_GROUP2_REG2_STEP0___RWC QCSR_REG_RW +#define DBG_GROUP2_REG2_STEP0__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG2_STEP0__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG2_STEP0__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG2_STEP0__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG2_STEP0__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG2_STEP0__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG2_STEP0__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG2_STEP0__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG2_STEP0__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG2_STEP0__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG2_STEP0__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG2_STEP0__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG2_STEP0__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG2_STEP0__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG2_STEP0__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG2_STEP0__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG2_STEP1 (0x00BC4314) +#define DBG_GROUP2_REG2_STEP1___RWC QCSR_REG_RW +#define DBG_GROUP2_REG2_STEP1__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG2_STEP1__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG2_STEP1__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG2_STEP1__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG2_STEP1__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG2_STEP1__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG2_STEP1__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG2_STEP1__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG2_STEP1__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG2_STEP1__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG2_STEP1__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG2_STEP1__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG2_STEP1__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG2_STEP1__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG2_STEP1__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG2_STEP1__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG2_STEP2 (0x00BC44EC) +#define DBG_GROUP2_REG2_STEP2___RWC QCSR_REG_RW +#define DBG_GROUP2_REG2_STEP2__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG2_STEP2__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG2_STEP2__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG2_STEP2__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG2_STEP2__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG2_STEP2__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG2_STEP2__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG2_STEP2__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG2_STEP2__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG2_STEP2__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG2_STEP2__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG2_STEP2__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG2_STEP2__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG2_STEP2__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG2_STEP2__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG2_STEP2__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG2_STEP3 (0x00BC46C4) +#define DBG_GROUP2_REG2_STEP3___RWC QCSR_REG_RW +#define DBG_GROUP2_REG2_STEP3__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG2_STEP3__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG2_STEP3__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG2_STEP3__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG2_STEP3__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG2_STEP3__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG2_STEP3__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG2_STEP3__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG2_STEP3__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG2_STEP3__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG2_STEP3__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG2_STEP3__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG2_STEP3__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG2_STEP3__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG2_STEP3__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG2_STEP3__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG2_STEP4 (0x00BC489C) +#define DBG_GROUP2_REG2_STEP4___RWC QCSR_REG_RW +#define DBG_GROUP2_REG2_STEP4__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG2_STEP4__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG2_STEP4__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG2_STEP4__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG2_STEP4__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG2_STEP4__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG2_STEP4__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG2_STEP4__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG2_STEP4__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG2_STEP4__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG2_STEP4__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG2_STEP4__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG2_STEP4__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG2_STEP4__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG2_STEP4__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG2_STEP4__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG2_STEP5 (0x00BC4A74) +#define DBG_GROUP2_REG2_STEP5___RWC QCSR_REG_RW +#define DBG_GROUP2_REG2_STEP5__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG2_STEP5__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG2_STEP5__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG2_STEP5__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG2_STEP5__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG2_STEP5__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG2_STEP5__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG2_STEP5__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG2_STEP5__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG2_STEP5__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG2_STEP5__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG2_STEP5__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG2_STEP5__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG2_STEP5__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG2_STEP5__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG2_STEP5__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG2_STEP6 (0x00BC4C4C) +#define DBG_GROUP2_REG2_STEP6___RWC QCSR_REG_RW +#define DBG_GROUP2_REG2_STEP6__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG2_STEP6__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG2_STEP6__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG2_STEP6__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG2_STEP6__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG2_STEP6__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG2_STEP6__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG2_STEP6__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG2_STEP6__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG2_STEP6__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG2_STEP6__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG2_STEP6__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG2_STEP6__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG2_STEP6__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG2_STEP6__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG2_STEP6__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG2_STEP7 (0x00BC4E24) +#define DBG_GROUP2_REG2_STEP7___RWC QCSR_REG_RW +#define DBG_GROUP2_REG2_STEP7__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG2_STEP7__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG2_STEP7__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG2_STEP7__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG2_STEP7__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG2_STEP7__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG2_STEP7__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG2_STEP7__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG2_STEP7__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG2_STEP7__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG2_STEP7__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG2_STEP7__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG2_STEP7__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG2_STEP7__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG2_STEP7__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG2_STEP7__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG3_STEP0 (0x00BC4140) +#define DBG_GROUP2_REG3_STEP0___RWC QCSR_REG_RW +#define DBG_GROUP2_REG3_STEP0__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG3_STEP0__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG3_STEP0__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG3_STEP0__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG3_STEP0__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG3_STEP0__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG3_STEP0__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG3_STEP0__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG3_STEP0__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG3_STEP0__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG3_STEP0__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG3_STEP0__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG3_STEP0__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG3_STEP0__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG3_STEP0__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG3_STEP0__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG3_STEP1 (0x00BC4318) +#define DBG_GROUP2_REG3_STEP1___RWC QCSR_REG_RW +#define DBG_GROUP2_REG3_STEP1__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG3_STEP1__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG3_STEP1__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG3_STEP1__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG3_STEP1__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG3_STEP1__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG3_STEP1__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG3_STEP1__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG3_STEP1__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG3_STEP1__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG3_STEP1__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG3_STEP1__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG3_STEP1__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG3_STEP1__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG3_STEP1__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG3_STEP1__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG3_STEP2 (0x00BC44F0) +#define DBG_GROUP2_REG3_STEP2___RWC QCSR_REG_RW +#define DBG_GROUP2_REG3_STEP2__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG3_STEP2__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG3_STEP2__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG3_STEP2__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG3_STEP2__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG3_STEP2__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG3_STEP2__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG3_STEP2__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG3_STEP2__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG3_STEP2__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG3_STEP2__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG3_STEP2__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG3_STEP2__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG3_STEP2__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG3_STEP2__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG3_STEP2__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG3_STEP3 (0x00BC46C8) +#define DBG_GROUP2_REG3_STEP3___RWC QCSR_REG_RW +#define DBG_GROUP2_REG3_STEP3__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG3_STEP3__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG3_STEP3__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG3_STEP3__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG3_STEP3__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG3_STEP3__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG3_STEP3__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG3_STEP3__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG3_STEP3__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG3_STEP3__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG3_STEP3__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG3_STEP3__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG3_STEP3__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG3_STEP3__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG3_STEP3__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG3_STEP3__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG3_STEP4 (0x00BC48A0) +#define DBG_GROUP2_REG3_STEP4___RWC QCSR_REG_RW +#define DBG_GROUP2_REG3_STEP4__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG3_STEP4__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG3_STEP4__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG3_STEP4__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG3_STEP4__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG3_STEP4__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG3_STEP4__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG3_STEP4__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG3_STEP4__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG3_STEP4__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG3_STEP4__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG3_STEP4__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG3_STEP4__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG3_STEP4__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG3_STEP4__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG3_STEP4__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG3_STEP5 (0x00BC4A78) +#define DBG_GROUP2_REG3_STEP5___RWC QCSR_REG_RW +#define DBG_GROUP2_REG3_STEP5__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG3_STEP5__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG3_STEP5__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG3_STEP5__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG3_STEP5__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG3_STEP5__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG3_STEP5__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG3_STEP5__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG3_STEP5__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG3_STEP5__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG3_STEP5__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG3_STEP5__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG3_STEP5__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG3_STEP5__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG3_STEP5__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG3_STEP5__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG3_STEP6 (0x00BC4C50) +#define DBG_GROUP2_REG3_STEP6___RWC QCSR_REG_RW +#define DBG_GROUP2_REG3_STEP6__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG3_STEP6__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG3_STEP6__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG3_STEP6__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG3_STEP6__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG3_STEP6__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG3_STEP6__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG3_STEP6__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG3_STEP6__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG3_STEP6__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG3_STEP6__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG3_STEP6__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG3_STEP6__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG3_STEP6__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG3_STEP6__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG3_STEP6__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG3_STEP7 (0x00BC4E28) +#define DBG_GROUP2_REG3_STEP7___RWC QCSR_REG_RW +#define DBG_GROUP2_REG3_STEP7__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG3_STEP7__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG3_STEP7__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG3_STEP7__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG3_STEP7__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG3_STEP7__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG3_STEP7__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG3_STEP7__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG3_STEP7__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG3_STEP7__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG3_STEP7__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG3_STEP7__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG3_STEP7__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG3_STEP7__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG3_STEP7__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG3_STEP7__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG4_STEP0 (0x00BC4144) +#define DBG_GROUP2_REG4_STEP0___RWC QCSR_REG_RW +#define DBG_GROUP2_REG4_STEP0__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG4_STEP0__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG4_STEP0__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG4_STEP0__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG4_STEP0__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG4_STEP0__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG4_STEP0__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG4_STEP0__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG4_STEP0__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG4_STEP0__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG4_STEP0__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG4_STEP0__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG4_STEP0__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG4_STEP0__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG4_STEP0__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG4_STEP0__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG4_STEP1 (0x00BC431C) +#define DBG_GROUP2_REG4_STEP1___RWC QCSR_REG_RW +#define DBG_GROUP2_REG4_STEP1__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG4_STEP1__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG4_STEP1__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG4_STEP1__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG4_STEP1__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG4_STEP1__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG4_STEP1__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG4_STEP1__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG4_STEP1__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG4_STEP1__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG4_STEP1__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG4_STEP1__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG4_STEP1__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG4_STEP1__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG4_STEP1__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG4_STEP1__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG4_STEP2 (0x00BC44F4) +#define DBG_GROUP2_REG4_STEP2___RWC QCSR_REG_RW +#define DBG_GROUP2_REG4_STEP2__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG4_STEP2__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG4_STEP2__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG4_STEP2__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG4_STEP2__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG4_STEP2__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG4_STEP2__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG4_STEP2__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG4_STEP2__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG4_STEP2__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG4_STEP2__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG4_STEP2__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG4_STEP2__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG4_STEP2__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG4_STEP2__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG4_STEP2__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG4_STEP3 (0x00BC46CC) +#define DBG_GROUP2_REG4_STEP3___RWC QCSR_REG_RW +#define DBG_GROUP2_REG4_STEP3__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG4_STEP3__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG4_STEP3__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG4_STEP3__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG4_STEP3__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG4_STEP3__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG4_STEP3__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG4_STEP3__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG4_STEP3__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG4_STEP3__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG4_STEP3__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG4_STEP3__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG4_STEP3__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG4_STEP3__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG4_STEP3__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG4_STEP3__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG4_STEP4 (0x00BC48A4) +#define DBG_GROUP2_REG4_STEP4___RWC QCSR_REG_RW +#define DBG_GROUP2_REG4_STEP4__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG4_STEP4__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG4_STEP4__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG4_STEP4__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG4_STEP4__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG4_STEP4__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG4_STEP4__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG4_STEP4__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG4_STEP4__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG4_STEP4__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG4_STEP4__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG4_STEP4__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG4_STEP4__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG4_STEP4__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG4_STEP4__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG4_STEP4__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG4_STEP5 (0x00BC4A7C) +#define DBG_GROUP2_REG4_STEP5___RWC QCSR_REG_RW +#define DBG_GROUP2_REG4_STEP5__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG4_STEP5__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG4_STEP5__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG4_STEP5__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG4_STEP5__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG4_STEP5__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG4_STEP5__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG4_STEP5__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG4_STEP5__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG4_STEP5__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG4_STEP5__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG4_STEP5__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG4_STEP5__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG4_STEP5__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG4_STEP5__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG4_STEP5__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG4_STEP6 (0x00BC4C54) +#define DBG_GROUP2_REG4_STEP6___RWC QCSR_REG_RW +#define DBG_GROUP2_REG4_STEP6__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG4_STEP6__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG4_STEP6__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG4_STEP6__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG4_STEP6__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG4_STEP6__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG4_STEP6__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG4_STEP6__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG4_STEP6__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG4_STEP6__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG4_STEP6__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG4_STEP6__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG4_STEP6__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG4_STEP6__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG4_STEP6__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG4_STEP6__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG4_STEP7 (0x00BC4E2C) +#define DBG_GROUP2_REG4_STEP7___RWC QCSR_REG_RW +#define DBG_GROUP2_REG4_STEP7__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG4_STEP7__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG4_STEP7__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG4_STEP7__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG4_STEP7__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG4_STEP7__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG4_STEP7__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG4_STEP7__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG4_STEP7__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG4_STEP7__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG4_STEP7__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG4_STEP7__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG4_STEP7__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG4_STEP7__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG4_STEP7__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG4_STEP7__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG5_STEP0 (0x00BC4148) +#define DBG_GROUP2_REG5_STEP0___RWC QCSR_REG_RW +#define DBG_GROUP2_REG5_STEP0__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG5_STEP0__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG5_STEP0__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG5_STEP0__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG5_STEP0__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG5_STEP0__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG5_STEP0__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG5_STEP0__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG5_STEP0__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG5_STEP0__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG5_STEP0__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG5_STEP0__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG5_STEP0__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG5_STEP0__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG5_STEP0__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG5_STEP0__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG5_STEP1 (0x00BC4320) +#define DBG_GROUP2_REG5_STEP1___RWC QCSR_REG_RW +#define DBG_GROUP2_REG5_STEP1__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG5_STEP1__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG5_STEP1__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG5_STEP1__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG5_STEP1__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG5_STEP1__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG5_STEP1__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG5_STEP1__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG5_STEP1__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG5_STEP1__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG5_STEP1__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG5_STEP1__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG5_STEP1__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG5_STEP1__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG5_STEP1__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG5_STEP1__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG5_STEP2 (0x00BC44F8) +#define DBG_GROUP2_REG5_STEP2___RWC QCSR_REG_RW +#define DBG_GROUP2_REG5_STEP2__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG5_STEP2__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG5_STEP2__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG5_STEP2__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG5_STEP2__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG5_STEP2__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG5_STEP2__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG5_STEP2__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG5_STEP2__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG5_STEP2__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG5_STEP2__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG5_STEP2__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG5_STEP2__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG5_STEP2__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG5_STEP2__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG5_STEP2__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG5_STEP3 (0x00BC46D0) +#define DBG_GROUP2_REG5_STEP3___RWC QCSR_REG_RW +#define DBG_GROUP2_REG5_STEP3__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG5_STEP3__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG5_STEP3__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG5_STEP3__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG5_STEP3__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG5_STEP3__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG5_STEP3__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG5_STEP3__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG5_STEP3__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG5_STEP3__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG5_STEP3__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG5_STEP3__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG5_STEP3__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG5_STEP3__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG5_STEP3__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG5_STEP3__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG5_STEP4 (0x00BC48A8) +#define DBG_GROUP2_REG5_STEP4___RWC QCSR_REG_RW +#define DBG_GROUP2_REG5_STEP4__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG5_STEP4__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG5_STEP4__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG5_STEP4__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG5_STEP4__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG5_STEP4__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG5_STEP4__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG5_STEP4__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG5_STEP4__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG5_STEP4__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG5_STEP4__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG5_STEP4__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG5_STEP4__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG5_STEP4__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG5_STEP4__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG5_STEP4__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG5_STEP5 (0x00BC4A80) +#define DBG_GROUP2_REG5_STEP5___RWC QCSR_REG_RW +#define DBG_GROUP2_REG5_STEP5__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG5_STEP5__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG5_STEP5__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG5_STEP5__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG5_STEP5__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG5_STEP5__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG5_STEP5__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG5_STEP5__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG5_STEP5__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG5_STEP5__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG5_STEP5__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG5_STEP5__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG5_STEP5__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG5_STEP5__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG5_STEP5__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG5_STEP5__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG5_STEP6 (0x00BC4C58) +#define DBG_GROUP2_REG5_STEP6___RWC QCSR_REG_RW +#define DBG_GROUP2_REG5_STEP6__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG5_STEP6__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG5_STEP6__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG5_STEP6__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG5_STEP6__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG5_STEP6__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG5_STEP6__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG5_STEP6__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG5_STEP6__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG5_STEP6__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG5_STEP6__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG5_STEP6__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG5_STEP6__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG5_STEP6__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG5_STEP6__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG5_STEP6__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REG5_STEP7 (0x00BC4E30) +#define DBG_GROUP2_REG5_STEP7___RWC QCSR_REG_RW +#define DBG_GROUP2_REG5_STEP7__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP2_REG5_STEP7__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP2_REG5_STEP7__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP2_REG5_STEP7__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP2_REG5_STEP7__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP2_REG5_STEP7__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP2_REG5_STEP7__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP2_REG5_STEP7__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP2_REG5_STEP7__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP2_REG5_STEP7__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP2_REG5_STEP7__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP2_REG5_STEP7__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP2_REG5_STEP7__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REG5_STEP7__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REG5_STEP7__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REG5_STEP7__SEL_BIT0_TYPE3___S 0 + +#define DBG_GROUP2_REGN_STEPn(n) (0x00BC414C+0x1D8*(n)) +#define DBG_GROUP2_REGN_STEPn_nMIN 0 +#define DBG_GROUP2_REGN_STEPn_nMAX 7 +#define DBG_GROUP2_REGN_STEPn_ELEM 8 +#define DBG_GROUP2_REGN_STEPn___RWC QCSR_REG_RW +#define DBG_GROUP2_REGN_STEPn___POR 0x00000000 +#define DBG_GROUP2_REGN_STEPn__SEL_BIT1_TYPE3___POR 0x0 +#define DBG_GROUP2_REGN_STEPn__SEL_BIT0_TYPE3___POR 0x0 +#define DBG_GROUP2_REGN_STEPn__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REGN_STEPn__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REGN_STEPn__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REGN_STEPn__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REGN_STEPn___M 0x00000077 +#define DBG_GROUP2_REGN_STEPn___S 0 +#define DBG_GROUP2_REGN_STEP0 (0x00BC414C) +#define DBG_GROUP2_REGN_STEP0___RWC QCSR_REG_RW +#define DBG_GROUP2_REGN_STEP0__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REGN_STEP0__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REGN_STEP0__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REGN_STEP0__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REGN_STEP1 (0x00BC4324) +#define DBG_GROUP2_REGN_STEP1___RWC QCSR_REG_RW +#define DBG_GROUP2_REGN_STEP1__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REGN_STEP1__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REGN_STEP1__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REGN_STEP1__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REGN_STEP2 (0x00BC44FC) +#define DBG_GROUP2_REGN_STEP2___RWC QCSR_REG_RW +#define DBG_GROUP2_REGN_STEP2__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REGN_STEP2__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REGN_STEP2__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REGN_STEP2__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REGN_STEP3 (0x00BC46D4) +#define DBG_GROUP2_REGN_STEP3___RWC QCSR_REG_RW +#define DBG_GROUP2_REGN_STEP3__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REGN_STEP3__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REGN_STEP3__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REGN_STEP3__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REGN_STEP4 (0x00BC48AC) +#define DBG_GROUP2_REGN_STEP4___RWC QCSR_REG_RW +#define DBG_GROUP2_REGN_STEP4__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REGN_STEP4__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REGN_STEP4__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REGN_STEP4__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REGN_STEP5 (0x00BC4A84) +#define DBG_GROUP2_REGN_STEP5___RWC QCSR_REG_RW +#define DBG_GROUP2_REGN_STEP5__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REGN_STEP5__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REGN_STEP5__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REGN_STEP5__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REGN_STEP6 (0x00BC4C5C) +#define DBG_GROUP2_REGN_STEP6___RWC QCSR_REG_RW +#define DBG_GROUP2_REGN_STEP6__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REGN_STEP6__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REGN_STEP6__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REGN_STEP6__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP2_REGN_STEP7 (0x00BC4E34) +#define DBG_GROUP2_REGN_STEP7___RWC QCSR_REG_RW +#define DBG_GROUP2_REGN_STEP7__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP2_REGN_STEP7__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP2_REGN_STEP7__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP2_REGN_STEP7__SEL_BIT0_TYPE3___S 0 + +#define DBG_GROUP3_REGm_STEPn(m,n) (0x00BC4194+0x4*(m)+0x1D8*(n)) +#define DBG_GROUP3_REGm_STEPn_mMIN 0 +#define DBG_GROUP3_REGm_STEPn_mMAX 5 +#define DBG_GROUP3_REGm_STEPn_nMIN 0 +#define DBG_GROUP3_REGm_STEPn_nMAX 7 +#define DBG_GROUP3_REGm_STEPn_ELEM 48 +#define DBG_GROUP3_REGm_STEPn___RWC QCSR_REG_RW +#define DBG_GROUP3_REGm_STEPn___POR 0x00000000 +#define DBG_GROUP3_REGm_STEPn__SEL_BIT7_TYPE3___POR 0x0 +#define DBG_GROUP3_REGm_STEPn__SEL_BIT6_TYPE3___POR 0x0 +#define DBG_GROUP3_REGm_STEPn__SEL_BIT5_TYPE3___POR 0x0 +#define DBG_GROUP3_REGm_STEPn__SEL_BIT4_TYPE3___POR 0x0 +#define DBG_GROUP3_REGm_STEPn__SEL_BIT3_TYPE3___POR 0x0 +#define DBG_GROUP3_REGm_STEPn__SEL_BIT2_TYPE3___POR 0x0 +#define DBG_GROUP3_REGm_STEPn__SEL_BIT1_TYPE3___POR 0x0 +#define DBG_GROUP3_REGm_STEPn__SEL_BIT0_TYPE3___POR 0x0 +#define DBG_GROUP3_REGm_STEPn__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REGm_STEPn__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REGm_STEPn__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REGm_STEPn__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REGm_STEPn__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REGm_STEPn__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REGm_STEPn__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REGm_STEPn__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REGm_STEPn__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REGm_STEPn__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REGm_STEPn__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REGm_STEPn__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REGm_STEPn__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REGm_STEPn__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REGm_STEPn__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REGm_STEPn__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REGm_STEPn___M 0x77777777 +#define DBG_GROUP3_REGm_STEPn___S 0 +#define DBG_GROUP3_REG0_STEP0 (0x00BC4194) +#define DBG_GROUP3_REG0_STEP0___RWC QCSR_REG_RW +#define DBG_GROUP3_REG0_STEP0__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG0_STEP0__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG0_STEP0__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG0_STEP0__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG0_STEP0__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG0_STEP0__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG0_STEP0__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG0_STEP0__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG0_STEP0__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG0_STEP0__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG0_STEP0__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG0_STEP0__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG0_STEP0__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG0_STEP0__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG0_STEP0__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG0_STEP0__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG0_STEP1 (0x00BC436C) +#define DBG_GROUP3_REG0_STEP1___RWC QCSR_REG_RW +#define DBG_GROUP3_REG0_STEP1__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG0_STEP1__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG0_STEP1__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG0_STEP1__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG0_STEP1__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG0_STEP1__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG0_STEP1__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG0_STEP1__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG0_STEP1__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG0_STEP1__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG0_STEP1__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG0_STEP1__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG0_STEP1__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG0_STEP1__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG0_STEP1__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG0_STEP1__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG0_STEP2 (0x00BC4544) +#define DBG_GROUP3_REG0_STEP2___RWC QCSR_REG_RW +#define DBG_GROUP3_REG0_STEP2__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG0_STEP2__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG0_STEP2__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG0_STEP2__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG0_STEP2__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG0_STEP2__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG0_STEP2__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG0_STEP2__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG0_STEP2__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG0_STEP2__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG0_STEP2__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG0_STEP2__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG0_STEP2__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG0_STEP2__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG0_STEP2__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG0_STEP2__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG0_STEP3 (0x00BC471C) +#define DBG_GROUP3_REG0_STEP3___RWC QCSR_REG_RW +#define DBG_GROUP3_REG0_STEP3__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG0_STEP3__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG0_STEP3__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG0_STEP3__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG0_STEP3__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG0_STEP3__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG0_STEP3__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG0_STEP3__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG0_STEP3__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG0_STEP3__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG0_STEP3__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG0_STEP3__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG0_STEP3__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG0_STEP3__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG0_STEP3__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG0_STEP3__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG0_STEP4 (0x00BC48F4) +#define DBG_GROUP3_REG0_STEP4___RWC QCSR_REG_RW +#define DBG_GROUP3_REG0_STEP4__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG0_STEP4__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG0_STEP4__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG0_STEP4__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG0_STEP4__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG0_STEP4__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG0_STEP4__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG0_STEP4__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG0_STEP4__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG0_STEP4__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG0_STEP4__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG0_STEP4__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG0_STEP4__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG0_STEP4__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG0_STEP4__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG0_STEP4__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG0_STEP5 (0x00BC4ACC) +#define DBG_GROUP3_REG0_STEP5___RWC QCSR_REG_RW +#define DBG_GROUP3_REG0_STEP5__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG0_STEP5__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG0_STEP5__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG0_STEP5__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG0_STEP5__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG0_STEP5__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG0_STEP5__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG0_STEP5__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG0_STEP5__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG0_STEP5__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG0_STEP5__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG0_STEP5__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG0_STEP5__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG0_STEP5__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG0_STEP5__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG0_STEP5__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG0_STEP6 (0x00BC4CA4) +#define DBG_GROUP3_REG0_STEP6___RWC QCSR_REG_RW +#define DBG_GROUP3_REG0_STEP6__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG0_STEP6__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG0_STEP6__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG0_STEP6__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG0_STEP6__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG0_STEP6__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG0_STEP6__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG0_STEP6__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG0_STEP6__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG0_STEP6__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG0_STEP6__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG0_STEP6__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG0_STEP6__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG0_STEP6__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG0_STEP6__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG0_STEP6__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG0_STEP7 (0x00BC4E7C) +#define DBG_GROUP3_REG0_STEP7___RWC QCSR_REG_RW +#define DBG_GROUP3_REG0_STEP7__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG0_STEP7__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG0_STEP7__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG0_STEP7__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG0_STEP7__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG0_STEP7__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG0_STEP7__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG0_STEP7__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG0_STEP7__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG0_STEP7__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG0_STEP7__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG0_STEP7__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG0_STEP7__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG0_STEP7__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG0_STEP7__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG0_STEP7__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG1_STEP0 (0x00BC4198) +#define DBG_GROUP3_REG1_STEP0___RWC QCSR_REG_RW +#define DBG_GROUP3_REG1_STEP0__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG1_STEP0__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG1_STEP0__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG1_STEP0__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG1_STEP0__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG1_STEP0__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG1_STEP0__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG1_STEP0__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG1_STEP0__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG1_STEP0__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG1_STEP0__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG1_STEP0__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG1_STEP0__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG1_STEP0__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG1_STEP0__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG1_STEP0__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG1_STEP1 (0x00BC4370) +#define DBG_GROUP3_REG1_STEP1___RWC QCSR_REG_RW +#define DBG_GROUP3_REG1_STEP1__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG1_STEP1__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG1_STEP1__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG1_STEP1__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG1_STEP1__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG1_STEP1__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG1_STEP1__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG1_STEP1__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG1_STEP1__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG1_STEP1__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG1_STEP1__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG1_STEP1__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG1_STEP1__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG1_STEP1__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG1_STEP1__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG1_STEP1__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG1_STEP2 (0x00BC4548) +#define DBG_GROUP3_REG1_STEP2___RWC QCSR_REG_RW +#define DBG_GROUP3_REG1_STEP2__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG1_STEP2__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG1_STEP2__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG1_STEP2__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG1_STEP2__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG1_STEP2__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG1_STEP2__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG1_STEP2__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG1_STEP2__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG1_STEP2__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG1_STEP2__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG1_STEP2__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG1_STEP2__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG1_STEP2__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG1_STEP2__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG1_STEP2__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG1_STEP3 (0x00BC4720) +#define DBG_GROUP3_REG1_STEP3___RWC QCSR_REG_RW +#define DBG_GROUP3_REG1_STEP3__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG1_STEP3__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG1_STEP3__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG1_STEP3__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG1_STEP3__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG1_STEP3__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG1_STEP3__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG1_STEP3__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG1_STEP3__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG1_STEP3__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG1_STEP3__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG1_STEP3__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG1_STEP3__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG1_STEP3__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG1_STEP3__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG1_STEP3__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG1_STEP4 (0x00BC48F8) +#define DBG_GROUP3_REG1_STEP4___RWC QCSR_REG_RW +#define DBG_GROUP3_REG1_STEP4__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG1_STEP4__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG1_STEP4__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG1_STEP4__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG1_STEP4__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG1_STEP4__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG1_STEP4__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG1_STEP4__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG1_STEP4__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG1_STEP4__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG1_STEP4__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG1_STEP4__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG1_STEP4__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG1_STEP4__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG1_STEP4__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG1_STEP4__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG1_STEP5 (0x00BC4AD0) +#define DBG_GROUP3_REG1_STEP5___RWC QCSR_REG_RW +#define DBG_GROUP3_REG1_STEP5__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG1_STEP5__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG1_STEP5__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG1_STEP5__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG1_STEP5__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG1_STEP5__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG1_STEP5__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG1_STEP5__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG1_STEP5__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG1_STEP5__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG1_STEP5__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG1_STEP5__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG1_STEP5__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG1_STEP5__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG1_STEP5__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG1_STEP5__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG1_STEP6 (0x00BC4CA8) +#define DBG_GROUP3_REG1_STEP6___RWC QCSR_REG_RW +#define DBG_GROUP3_REG1_STEP6__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG1_STEP6__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG1_STEP6__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG1_STEP6__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG1_STEP6__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG1_STEP6__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG1_STEP6__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG1_STEP6__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG1_STEP6__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG1_STEP6__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG1_STEP6__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG1_STEP6__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG1_STEP6__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG1_STEP6__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG1_STEP6__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG1_STEP6__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG1_STEP7 (0x00BC4E80) +#define DBG_GROUP3_REG1_STEP7___RWC QCSR_REG_RW +#define DBG_GROUP3_REG1_STEP7__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG1_STEP7__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG1_STEP7__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG1_STEP7__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG1_STEP7__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG1_STEP7__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG1_STEP7__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG1_STEP7__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG1_STEP7__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG1_STEP7__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG1_STEP7__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG1_STEP7__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG1_STEP7__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG1_STEP7__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG1_STEP7__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG1_STEP7__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG2_STEP0 (0x00BC419C) +#define DBG_GROUP3_REG2_STEP0___RWC QCSR_REG_RW +#define DBG_GROUP3_REG2_STEP0__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG2_STEP0__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG2_STEP0__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG2_STEP0__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG2_STEP0__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG2_STEP0__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG2_STEP0__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG2_STEP0__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG2_STEP0__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG2_STEP0__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG2_STEP0__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG2_STEP0__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG2_STEP0__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG2_STEP0__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG2_STEP0__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG2_STEP0__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG2_STEP1 (0x00BC4374) +#define DBG_GROUP3_REG2_STEP1___RWC QCSR_REG_RW +#define DBG_GROUP3_REG2_STEP1__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG2_STEP1__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG2_STEP1__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG2_STEP1__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG2_STEP1__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG2_STEP1__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG2_STEP1__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG2_STEP1__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG2_STEP1__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG2_STEP1__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG2_STEP1__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG2_STEP1__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG2_STEP1__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG2_STEP1__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG2_STEP1__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG2_STEP1__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG2_STEP2 (0x00BC454C) +#define DBG_GROUP3_REG2_STEP2___RWC QCSR_REG_RW +#define DBG_GROUP3_REG2_STEP2__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG2_STEP2__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG2_STEP2__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG2_STEP2__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG2_STEP2__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG2_STEP2__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG2_STEP2__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG2_STEP2__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG2_STEP2__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG2_STEP2__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG2_STEP2__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG2_STEP2__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG2_STEP2__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG2_STEP2__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG2_STEP2__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG2_STEP2__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG2_STEP3 (0x00BC4724) +#define DBG_GROUP3_REG2_STEP3___RWC QCSR_REG_RW +#define DBG_GROUP3_REG2_STEP3__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG2_STEP3__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG2_STEP3__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG2_STEP3__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG2_STEP3__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG2_STEP3__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG2_STEP3__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG2_STEP3__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG2_STEP3__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG2_STEP3__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG2_STEP3__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG2_STEP3__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG2_STEP3__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG2_STEP3__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG2_STEP3__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG2_STEP3__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG2_STEP4 (0x00BC48FC) +#define DBG_GROUP3_REG2_STEP4___RWC QCSR_REG_RW +#define DBG_GROUP3_REG2_STEP4__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG2_STEP4__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG2_STEP4__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG2_STEP4__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG2_STEP4__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG2_STEP4__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG2_STEP4__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG2_STEP4__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG2_STEP4__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG2_STEP4__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG2_STEP4__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG2_STEP4__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG2_STEP4__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG2_STEP4__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG2_STEP4__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG2_STEP4__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG2_STEP5 (0x00BC4AD4) +#define DBG_GROUP3_REG2_STEP5___RWC QCSR_REG_RW +#define DBG_GROUP3_REG2_STEP5__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG2_STEP5__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG2_STEP5__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG2_STEP5__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG2_STEP5__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG2_STEP5__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG2_STEP5__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG2_STEP5__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG2_STEP5__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG2_STEP5__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG2_STEP5__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG2_STEP5__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG2_STEP5__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG2_STEP5__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG2_STEP5__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG2_STEP5__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG2_STEP6 (0x00BC4CAC) +#define DBG_GROUP3_REG2_STEP6___RWC QCSR_REG_RW +#define DBG_GROUP3_REG2_STEP6__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG2_STEP6__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG2_STEP6__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG2_STEP6__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG2_STEP6__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG2_STEP6__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG2_STEP6__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG2_STEP6__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG2_STEP6__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG2_STEP6__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG2_STEP6__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG2_STEP6__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG2_STEP6__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG2_STEP6__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG2_STEP6__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG2_STEP6__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG2_STEP7 (0x00BC4E84) +#define DBG_GROUP3_REG2_STEP7___RWC QCSR_REG_RW +#define DBG_GROUP3_REG2_STEP7__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG2_STEP7__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG2_STEP7__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG2_STEP7__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG2_STEP7__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG2_STEP7__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG2_STEP7__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG2_STEP7__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG2_STEP7__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG2_STEP7__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG2_STEP7__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG2_STEP7__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG2_STEP7__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG2_STEP7__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG2_STEP7__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG2_STEP7__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG3_STEP0 (0x00BC41A0) +#define DBG_GROUP3_REG3_STEP0___RWC QCSR_REG_RW +#define DBG_GROUP3_REG3_STEP0__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG3_STEP0__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG3_STEP0__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG3_STEP0__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG3_STEP0__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG3_STEP0__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG3_STEP0__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG3_STEP0__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG3_STEP0__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG3_STEP0__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG3_STEP0__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG3_STEP0__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG3_STEP0__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG3_STEP0__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG3_STEP0__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG3_STEP0__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG3_STEP1 (0x00BC4378) +#define DBG_GROUP3_REG3_STEP1___RWC QCSR_REG_RW +#define DBG_GROUP3_REG3_STEP1__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG3_STEP1__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG3_STEP1__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG3_STEP1__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG3_STEP1__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG3_STEP1__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG3_STEP1__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG3_STEP1__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG3_STEP1__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG3_STEP1__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG3_STEP1__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG3_STEP1__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG3_STEP1__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG3_STEP1__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG3_STEP1__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG3_STEP1__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG3_STEP2 (0x00BC4550) +#define DBG_GROUP3_REG3_STEP2___RWC QCSR_REG_RW +#define DBG_GROUP3_REG3_STEP2__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG3_STEP2__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG3_STEP2__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG3_STEP2__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG3_STEP2__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG3_STEP2__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG3_STEP2__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG3_STEP2__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG3_STEP2__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG3_STEP2__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG3_STEP2__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG3_STEP2__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG3_STEP2__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG3_STEP2__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG3_STEP2__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG3_STEP2__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG3_STEP3 (0x00BC4728) +#define DBG_GROUP3_REG3_STEP3___RWC QCSR_REG_RW +#define DBG_GROUP3_REG3_STEP3__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG3_STEP3__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG3_STEP3__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG3_STEP3__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG3_STEP3__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG3_STEP3__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG3_STEP3__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG3_STEP3__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG3_STEP3__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG3_STEP3__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG3_STEP3__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG3_STEP3__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG3_STEP3__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG3_STEP3__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG3_STEP3__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG3_STEP3__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG3_STEP4 (0x00BC4900) +#define DBG_GROUP3_REG3_STEP4___RWC QCSR_REG_RW +#define DBG_GROUP3_REG3_STEP4__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG3_STEP4__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG3_STEP4__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG3_STEP4__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG3_STEP4__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG3_STEP4__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG3_STEP4__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG3_STEP4__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG3_STEP4__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG3_STEP4__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG3_STEP4__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG3_STEP4__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG3_STEP4__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG3_STEP4__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG3_STEP4__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG3_STEP4__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG3_STEP5 (0x00BC4AD8) +#define DBG_GROUP3_REG3_STEP5___RWC QCSR_REG_RW +#define DBG_GROUP3_REG3_STEP5__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG3_STEP5__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG3_STEP5__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG3_STEP5__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG3_STEP5__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG3_STEP5__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG3_STEP5__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG3_STEP5__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG3_STEP5__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG3_STEP5__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG3_STEP5__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG3_STEP5__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG3_STEP5__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG3_STEP5__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG3_STEP5__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG3_STEP5__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG3_STEP6 (0x00BC4CB0) +#define DBG_GROUP3_REG3_STEP6___RWC QCSR_REG_RW +#define DBG_GROUP3_REG3_STEP6__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG3_STEP6__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG3_STEP6__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG3_STEP6__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG3_STEP6__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG3_STEP6__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG3_STEP6__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG3_STEP6__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG3_STEP6__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG3_STEP6__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG3_STEP6__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG3_STEP6__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG3_STEP6__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG3_STEP6__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG3_STEP6__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG3_STEP6__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG3_STEP7 (0x00BC4E88) +#define DBG_GROUP3_REG3_STEP7___RWC QCSR_REG_RW +#define DBG_GROUP3_REG3_STEP7__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG3_STEP7__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG3_STEP7__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG3_STEP7__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG3_STEP7__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG3_STEP7__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG3_STEP7__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG3_STEP7__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG3_STEP7__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG3_STEP7__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG3_STEP7__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG3_STEP7__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG3_STEP7__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG3_STEP7__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG3_STEP7__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG3_STEP7__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG4_STEP0 (0x00BC41A4) +#define DBG_GROUP3_REG4_STEP0___RWC QCSR_REG_RW +#define DBG_GROUP3_REG4_STEP0__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG4_STEP0__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG4_STEP0__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG4_STEP0__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG4_STEP0__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG4_STEP0__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG4_STEP0__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG4_STEP0__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG4_STEP0__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG4_STEP0__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG4_STEP0__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG4_STEP0__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG4_STEP0__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG4_STEP0__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG4_STEP0__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG4_STEP0__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG4_STEP1 (0x00BC437C) +#define DBG_GROUP3_REG4_STEP1___RWC QCSR_REG_RW +#define DBG_GROUP3_REG4_STEP1__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG4_STEP1__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG4_STEP1__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG4_STEP1__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG4_STEP1__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG4_STEP1__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG4_STEP1__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG4_STEP1__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG4_STEP1__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG4_STEP1__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG4_STEP1__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG4_STEP1__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG4_STEP1__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG4_STEP1__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG4_STEP1__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG4_STEP1__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG4_STEP2 (0x00BC4554) +#define DBG_GROUP3_REG4_STEP2___RWC QCSR_REG_RW +#define DBG_GROUP3_REG4_STEP2__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG4_STEP2__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG4_STEP2__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG4_STEP2__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG4_STEP2__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG4_STEP2__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG4_STEP2__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG4_STEP2__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG4_STEP2__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG4_STEP2__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG4_STEP2__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG4_STEP2__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG4_STEP2__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG4_STEP2__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG4_STEP2__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG4_STEP2__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG4_STEP3 (0x00BC472C) +#define DBG_GROUP3_REG4_STEP3___RWC QCSR_REG_RW +#define DBG_GROUP3_REG4_STEP3__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG4_STEP3__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG4_STEP3__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG4_STEP3__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG4_STEP3__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG4_STEP3__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG4_STEP3__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG4_STEP3__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG4_STEP3__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG4_STEP3__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG4_STEP3__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG4_STEP3__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG4_STEP3__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG4_STEP3__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG4_STEP3__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG4_STEP3__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG4_STEP4 (0x00BC4904) +#define DBG_GROUP3_REG4_STEP4___RWC QCSR_REG_RW +#define DBG_GROUP3_REG4_STEP4__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG4_STEP4__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG4_STEP4__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG4_STEP4__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG4_STEP4__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG4_STEP4__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG4_STEP4__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG4_STEP4__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG4_STEP4__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG4_STEP4__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG4_STEP4__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG4_STEP4__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG4_STEP4__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG4_STEP4__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG4_STEP4__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG4_STEP4__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG4_STEP5 (0x00BC4ADC) +#define DBG_GROUP3_REG4_STEP5___RWC QCSR_REG_RW +#define DBG_GROUP3_REG4_STEP5__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG4_STEP5__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG4_STEP5__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG4_STEP5__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG4_STEP5__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG4_STEP5__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG4_STEP5__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG4_STEP5__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG4_STEP5__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG4_STEP5__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG4_STEP5__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG4_STEP5__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG4_STEP5__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG4_STEP5__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG4_STEP5__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG4_STEP5__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG4_STEP6 (0x00BC4CB4) +#define DBG_GROUP3_REG4_STEP6___RWC QCSR_REG_RW +#define DBG_GROUP3_REG4_STEP6__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG4_STEP6__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG4_STEP6__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG4_STEP6__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG4_STEP6__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG4_STEP6__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG4_STEP6__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG4_STEP6__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG4_STEP6__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG4_STEP6__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG4_STEP6__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG4_STEP6__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG4_STEP6__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG4_STEP6__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG4_STEP6__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG4_STEP6__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG4_STEP7 (0x00BC4E8C) +#define DBG_GROUP3_REG4_STEP7___RWC QCSR_REG_RW +#define DBG_GROUP3_REG4_STEP7__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG4_STEP7__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG4_STEP7__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG4_STEP7__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG4_STEP7__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG4_STEP7__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG4_STEP7__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG4_STEP7__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG4_STEP7__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG4_STEP7__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG4_STEP7__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG4_STEP7__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG4_STEP7__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG4_STEP7__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG4_STEP7__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG4_STEP7__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG5_STEP0 (0x00BC41A8) +#define DBG_GROUP3_REG5_STEP0___RWC QCSR_REG_RW +#define DBG_GROUP3_REG5_STEP0__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG5_STEP0__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG5_STEP0__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG5_STEP0__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG5_STEP0__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG5_STEP0__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG5_STEP0__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG5_STEP0__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG5_STEP0__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG5_STEP0__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG5_STEP0__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG5_STEP0__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG5_STEP0__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG5_STEP0__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG5_STEP0__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG5_STEP0__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG5_STEP1 (0x00BC4380) +#define DBG_GROUP3_REG5_STEP1___RWC QCSR_REG_RW +#define DBG_GROUP3_REG5_STEP1__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG5_STEP1__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG5_STEP1__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG5_STEP1__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG5_STEP1__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG5_STEP1__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG5_STEP1__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG5_STEP1__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG5_STEP1__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG5_STEP1__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG5_STEP1__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG5_STEP1__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG5_STEP1__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG5_STEP1__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG5_STEP1__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG5_STEP1__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG5_STEP2 (0x00BC4558) +#define DBG_GROUP3_REG5_STEP2___RWC QCSR_REG_RW +#define DBG_GROUP3_REG5_STEP2__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG5_STEP2__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG5_STEP2__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG5_STEP2__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG5_STEP2__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG5_STEP2__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG5_STEP2__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG5_STEP2__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG5_STEP2__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG5_STEP2__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG5_STEP2__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG5_STEP2__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG5_STEP2__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG5_STEP2__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG5_STEP2__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG5_STEP2__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG5_STEP3 (0x00BC4730) +#define DBG_GROUP3_REG5_STEP3___RWC QCSR_REG_RW +#define DBG_GROUP3_REG5_STEP3__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG5_STEP3__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG5_STEP3__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG5_STEP3__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG5_STEP3__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG5_STEP3__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG5_STEP3__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG5_STEP3__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG5_STEP3__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG5_STEP3__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG5_STEP3__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG5_STEP3__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG5_STEP3__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG5_STEP3__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG5_STEP3__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG5_STEP3__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG5_STEP4 (0x00BC4908) +#define DBG_GROUP3_REG5_STEP4___RWC QCSR_REG_RW +#define DBG_GROUP3_REG5_STEP4__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG5_STEP4__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG5_STEP4__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG5_STEP4__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG5_STEP4__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG5_STEP4__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG5_STEP4__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG5_STEP4__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG5_STEP4__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG5_STEP4__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG5_STEP4__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG5_STEP4__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG5_STEP4__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG5_STEP4__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG5_STEP4__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG5_STEP4__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG5_STEP5 (0x00BC4AE0) +#define DBG_GROUP3_REG5_STEP5___RWC QCSR_REG_RW +#define DBG_GROUP3_REG5_STEP5__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG5_STEP5__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG5_STEP5__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG5_STEP5__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG5_STEP5__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG5_STEP5__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG5_STEP5__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG5_STEP5__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG5_STEP5__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG5_STEP5__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG5_STEP5__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG5_STEP5__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG5_STEP5__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG5_STEP5__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG5_STEP5__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG5_STEP5__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG5_STEP6 (0x00BC4CB8) +#define DBG_GROUP3_REG5_STEP6___RWC QCSR_REG_RW +#define DBG_GROUP3_REG5_STEP6__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG5_STEP6__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG5_STEP6__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG5_STEP6__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG5_STEP6__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG5_STEP6__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG5_STEP6__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG5_STEP6__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG5_STEP6__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG5_STEP6__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG5_STEP6__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG5_STEP6__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG5_STEP6__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG5_STEP6__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG5_STEP6__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG5_STEP6__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REG5_STEP7 (0x00BC4E90) +#define DBG_GROUP3_REG5_STEP7___RWC QCSR_REG_RW +#define DBG_GROUP3_REG5_STEP7__SEL_BIT7_TYPE3___M 0x70000000 +#define DBG_GROUP3_REG5_STEP7__SEL_BIT7_TYPE3___S 28 +#define DBG_GROUP3_REG5_STEP7__SEL_BIT6_TYPE3___M 0x07000000 +#define DBG_GROUP3_REG5_STEP7__SEL_BIT6_TYPE3___S 24 +#define DBG_GROUP3_REG5_STEP7__SEL_BIT5_TYPE3___M 0x00700000 +#define DBG_GROUP3_REG5_STEP7__SEL_BIT5_TYPE3___S 20 +#define DBG_GROUP3_REG5_STEP7__SEL_BIT4_TYPE3___M 0x00070000 +#define DBG_GROUP3_REG5_STEP7__SEL_BIT4_TYPE3___S 16 +#define DBG_GROUP3_REG5_STEP7__SEL_BIT3_TYPE3___M 0x00007000 +#define DBG_GROUP3_REG5_STEP7__SEL_BIT3_TYPE3___S 12 +#define DBG_GROUP3_REG5_STEP7__SEL_BIT2_TYPE3___M 0x00000700 +#define DBG_GROUP3_REG5_STEP7__SEL_BIT2_TYPE3___S 8 +#define DBG_GROUP3_REG5_STEP7__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REG5_STEP7__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REG5_STEP7__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REG5_STEP7__SEL_BIT0_TYPE3___S 0 + +#define DBG_GROUP3_REGN_STEPn(n) (0x00BC41AC+0x1D8*(n)) +#define DBG_GROUP3_REGN_STEPn_nMIN 0 +#define DBG_GROUP3_REGN_STEPn_nMAX 7 +#define DBG_GROUP3_REGN_STEPn_ELEM 8 +#define DBG_GROUP3_REGN_STEPn___RWC QCSR_REG_RW +#define DBG_GROUP3_REGN_STEPn___POR 0x00000000 +#define DBG_GROUP3_REGN_STEPn__SEL_BIT1_TYPE3___POR 0x0 +#define DBG_GROUP3_REGN_STEPn__SEL_BIT0_TYPE3___POR 0x0 +#define DBG_GROUP3_REGN_STEPn__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REGN_STEPn__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REGN_STEPn__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REGN_STEPn__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REGN_STEPn___M 0x00000077 +#define DBG_GROUP3_REGN_STEPn___S 0 +#define DBG_GROUP3_REGN_STEP0 (0x00BC41AC) +#define DBG_GROUP3_REGN_STEP0___RWC QCSR_REG_RW +#define DBG_GROUP3_REGN_STEP0__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REGN_STEP0__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REGN_STEP0__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REGN_STEP0__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REGN_STEP1 (0x00BC4384) +#define DBG_GROUP3_REGN_STEP1___RWC QCSR_REG_RW +#define DBG_GROUP3_REGN_STEP1__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REGN_STEP1__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REGN_STEP1__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REGN_STEP1__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REGN_STEP2 (0x00BC455C) +#define DBG_GROUP3_REGN_STEP2___RWC QCSR_REG_RW +#define DBG_GROUP3_REGN_STEP2__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REGN_STEP2__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REGN_STEP2__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REGN_STEP2__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REGN_STEP3 (0x00BC4734) +#define DBG_GROUP3_REGN_STEP3___RWC QCSR_REG_RW +#define DBG_GROUP3_REGN_STEP3__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REGN_STEP3__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REGN_STEP3__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REGN_STEP3__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REGN_STEP4 (0x00BC490C) +#define DBG_GROUP3_REGN_STEP4___RWC QCSR_REG_RW +#define DBG_GROUP3_REGN_STEP4__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REGN_STEP4__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REGN_STEP4__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REGN_STEP4__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REGN_STEP5 (0x00BC4AE4) +#define DBG_GROUP3_REGN_STEP5___RWC QCSR_REG_RW +#define DBG_GROUP3_REGN_STEP5__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REGN_STEP5__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REGN_STEP5__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REGN_STEP5__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REGN_STEP6 (0x00BC4CBC) +#define DBG_GROUP3_REGN_STEP6___RWC QCSR_REG_RW +#define DBG_GROUP3_REGN_STEP6__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REGN_STEP6__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REGN_STEP6__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REGN_STEP6__SEL_BIT0_TYPE3___S 0 +#define DBG_GROUP3_REGN_STEP7 (0x00BC4E94) +#define DBG_GROUP3_REGN_STEP7___RWC QCSR_REG_RW +#define DBG_GROUP3_REGN_STEP7__SEL_BIT1_TYPE3___M 0x00000070 +#define DBG_GROUP3_REGN_STEP7__SEL_BIT1_TYPE3___S 4 +#define DBG_GROUP3_REGN_STEP7__SEL_BIT0_TYPE3___M 0x00000007 +#define DBG_GROUP3_REGN_STEP7__SEL_BIT0_TYPE3___S 0 + +#define DBG_TGU_ITATBCNTRL (0x00BC4EF0) +#define DBG_TGU_ITATBCNTRL___RWC QCSR_REG_RW +#define DBG_TGU_ITATBCNTRL___POR 0x00000000 +#define DBG_TGU_ITATBCNTRL__TSREQ___POR 0x0 +#define DBG_TGU_ITATBCNTRL__ATVALID___POR 0x0 +#define DBG_TGU_ITATBCNTRL__ATDATAMODE___POR 0x0 +#define DBG_TGU_ITATBCNTRL__ATBYTES___POR 0x0 +#define DBG_TGU_ITATBCNTRL__ATDATA___POR 0x00 +#define DBG_TGU_ITATBCNTRL__ATID___POR 0x00 +#define DBG_TGU_ITATBCNTRL__TSVAL___POR 0x0 +#define DBG_TGU_ITATBCNTRL__TSREQ___M 0x80000000 +#define DBG_TGU_ITATBCNTRL__TSREQ___S 31 +#define DBG_TGU_ITATBCNTRL__ATVALID___M 0x40000000 +#define DBG_TGU_ITATBCNTRL__ATVALID___S 30 +#define DBG_TGU_ITATBCNTRL__ATDATAMODE___M 0x00400000 +#define DBG_TGU_ITATBCNTRL__ATDATAMODE___S 22 +#define DBG_TGU_ITATBCNTRL__ATBYTES___M 0x003C0000 +#define DBG_TGU_ITATBCNTRL__ATBYTES___S 18 +#define DBG_TGU_ITATBCNTRL__ATDATA___M 0x0003FC00 +#define DBG_TGU_ITATBCNTRL__ATDATA___S 10 +#define DBG_TGU_ITATBCNTRL__ATID___M 0x000003F8 +#define DBG_TGU_ITATBCNTRL__ATID___S 3 +#define DBG_TGU_ITATBCNTRL__TSVAL___M 0x00000007 +#define DBG_TGU_ITATBCNTRL__TSVAL___S 0 +#define DBG_TGU_ITATBCNTRL___M 0xC07FFFFF +#define DBG_TGU_ITATBCNTRL___S 0 + +#define DBG_TGU_ITCNTRL (0x00BC4F00) +#define DBG_TGU_ITCNTRL___RWC QCSR_REG_RW +#define DBG_TGU_ITCNTRL___POR 0x00000000 +#define DBG_TGU_ITCNTRL__IME___POR 0x0 +#define DBG_TGU_ITCNTRL__IME___M 0x00000001 +#define DBG_TGU_ITCNTRL__IME___S 0 +#define DBG_TGU_ITCNTRL___M 0x00000001 +#define DBG_TGU_ITCNTRL___S 0 + +#define DBG_TGU_CLAIMSET (0x00BC4FA0) +#define DBG_TGU_CLAIMSET___RWC QCSR_REG_RO +#define DBG_TGU_CLAIMSET___POR 0x00000000 +#define DBG_TGU_CLAIMSET__VAL_SET___POR 0x00000000 +#define DBG_TGU_CLAIMSET__VAL_SET___M 0xFFFFFFFF +#define DBG_TGU_CLAIMSET__VAL_SET___S 0 +#define DBG_TGU_CLAIMSET___M 0xFFFFFFFF +#define DBG_TGU_CLAIMSET___S 0 + +#define DBG_TGU_CLAIMCLR (0x00BC4FA4) +#define DBG_TGU_CLAIMCLR___RWC QCSR_REG_RO +#define DBG_TGU_CLAIMCLR___POR 0x00000000 +#define DBG_TGU_CLAIMCLR__VAL_CLR___POR 0x00000000 +#define DBG_TGU_CLAIMCLR__VAL_CLR___M 0xFFFFFFFF +#define DBG_TGU_CLAIMCLR__VAL_CLR___S 0 +#define DBG_TGU_CLAIMCLR___M 0xFFFFFFFF +#define DBG_TGU_CLAIMCLR___S 0 + +#define DBG_TGU_DEVAFF0 (0x00BC4FA8) +#define DBG_TGU_DEVAFF0___RWC QCSR_REG_RO +#define DBG_TGU_DEVAFF0___POR 0x00000000 +#define DBG_TGU_DEVAFF0__VAL___POR 0x00000000 +#define DBG_TGU_DEVAFF0__VAL___M 0xFFFFFFFF +#define DBG_TGU_DEVAFF0__VAL___S 0 +#define DBG_TGU_DEVAFF0___M 0xFFFFFFFF +#define DBG_TGU_DEVAFF0___S 0 + +#define DBG_TGU_DEVAFF1 (0x00BC4FAC) +#define DBG_TGU_DEVAFF1___RWC QCSR_REG_RO +#define DBG_TGU_DEVAFF1___POR 0x00000000 +#define DBG_TGU_DEVAFF1__VAL___POR 0x00000000 +#define DBG_TGU_DEVAFF1__VAL___M 0xFFFFFFFF +#define DBG_TGU_DEVAFF1__VAL___S 0 +#define DBG_TGU_DEVAFF1___M 0xFFFFFFFF +#define DBG_TGU_DEVAFF1___S 0 + +#define DBG_TGU_LAR (0x00BC4FB0) +#define DBG_TGU_LAR___RWC QCSR_REG_RW +#define DBG_TGU_LAR___POR 0x00000000 +#define DBG_TGU_LAR__KEY___POR 0x00000000 +#define DBG_TGU_LAR__KEY___M 0xFFFFFFFF +#define DBG_TGU_LAR__KEY___S 0 +#define DBG_TGU_LAR___M 0xFFFFFFFF +#define DBG_TGU_LAR___S 0 + +#define DBG_TGU_LSR (0x00BC4FB4) +#define DBG_TGU_LSR___RWC QCSR_REG_RO +#define DBG_TGU_LSR___POR 0x00000003 +#define DBG_TGU_LSR__NTT___POR 0x0 +#define DBG_TGU_LSR__SLK___POR 0x1 +#define DBG_TGU_LSR__SLI___POR 0x1 +#define DBG_TGU_LSR__NTT___M 0x00000004 +#define DBG_TGU_LSR__NTT___S 2 +#define DBG_TGU_LSR__SLK___M 0x00000002 +#define DBG_TGU_LSR__SLK___S 1 +#define DBG_TGU_LSR__SLI___M 0x00000001 +#define DBG_TGU_LSR__SLI___S 0 +#define DBG_TGU_LSR___M 0x00000007 +#define DBG_TGU_LSR___S 0 + +#define DBG_TGU_AUTHSTATUS (0x00BC4FB8) +#define DBG_TGU_AUTHSTATUS___RWC QCSR_REG_RO +#define DBG_TGU_AUTHSTATUS___POR 0x000000AA +#define DBG_TGU_AUTHSTATUS__SNID___POR 0x2 +#define DBG_TGU_AUTHSTATUS__SID___POR 0x2 +#define DBG_TGU_AUTHSTATUS__NSNID___POR 0x2 +#define DBG_TGU_AUTHSTATUS__NSID___POR 0x2 +#define DBG_TGU_AUTHSTATUS__SNID___M 0x000000C0 +#define DBG_TGU_AUTHSTATUS__SNID___S 6 +#define DBG_TGU_AUTHSTATUS__SID___M 0x00000030 +#define DBG_TGU_AUTHSTATUS__SID___S 4 +#define DBG_TGU_AUTHSTATUS__NSNID___M 0x0000000C +#define DBG_TGU_AUTHSTATUS__NSNID___S 2 +#define DBG_TGU_AUTHSTATUS__NSID___M 0x00000003 +#define DBG_TGU_AUTHSTATUS__NSID___S 0 +#define DBG_TGU_AUTHSTATUS___M 0x000000FF +#define DBG_TGU_AUTHSTATUS___S 0 + +#define DBG_TGU_DEVARCH (0x00BC4FBC) +#define DBG_TGU_DEVARCH___RWC QCSR_REG_RO +#define DBG_TGU_DEVARCH___POR 0x0E105CDA +#define DBG_TGU_DEVARCH__ARCHITECT___POR 0x070 +#define DBG_TGU_DEVARCH__PRESENT___POR 0x1 +#define DBG_TGU_DEVARCH__REVISION___POR 0x0 +#define DBG_TGU_DEVARCH__ARCHID___POR 0x5CDA +#define DBG_TGU_DEVARCH__ARCHITECT___M 0xFFE00000 +#define DBG_TGU_DEVARCH__ARCHITECT___S 21 +#define DBG_TGU_DEVARCH__PRESENT___M 0x00100000 +#define DBG_TGU_DEVARCH__PRESENT___S 20 +#define DBG_TGU_DEVARCH__REVISION___M 0x000F0000 +#define DBG_TGU_DEVARCH__REVISION___S 16 +#define DBG_TGU_DEVARCH__ARCHID___M 0x0000FFFF +#define DBG_TGU_DEVARCH__ARCHID___S 0 +#define DBG_TGU_DEVARCH___M 0xFFFFFFFF +#define DBG_TGU_DEVARCH___S 0 + +#define DBG_TGU_DEVID2 (0x00BC4FC0) +#define DBG_TGU_DEVID2___RWC QCSR_REG_RO +#define DBG_TGU_DEVID2___POR 0xFF400400 +#define DBG_TGU_DEVID2__GROUP0_TYPE___POR 0x3 +#define DBG_TGU_DEVID2__GROUP1_TYPE___POR 0x3 +#define DBG_TGU_DEVID2__GROUP2_TYPE___POR 0x3 +#define DBG_TGU_DEVID2__GROUP3_TYPE___POR 0x3 +#define DBG_TGU_DEVID2__WIDTH_TC0___POR 0x10 +#define DBG_TGU_DEVID2__WIDTH_TC1___POR 0x0 +#define DBG_TGU_DEVID2__WIDTH_BC0___POR 0x10 +#define DBG_TGU_DEVID2__WIDTH_BC1___POR 0x0 +#define DBG_TGU_DEVID2__GROUP0_TYPE___M 0xC0000000 +#define DBG_TGU_DEVID2__GROUP0_TYPE___S 30 +#define DBG_TGU_DEVID2__GROUP1_TYPE___M 0x30000000 +#define DBG_TGU_DEVID2__GROUP1_TYPE___S 28 +#define DBG_TGU_DEVID2__GROUP2_TYPE___M 0x0C000000 +#define DBG_TGU_DEVID2__GROUP2_TYPE___S 26 +#define DBG_TGU_DEVID2__GROUP3_TYPE___M 0x03000000 +#define DBG_TGU_DEVID2__GROUP3_TYPE___S 24 +#define DBG_TGU_DEVID2__WIDTH_TC0___M 0x00FC0000 +#define DBG_TGU_DEVID2__WIDTH_TC0___S 18 +#define DBG_TGU_DEVID2__WIDTH_TC1___M 0x0003E000 +#define DBG_TGU_DEVID2__WIDTH_TC1___S 13 +#define DBG_TGU_DEVID2__WIDTH_BC0___M 0x00000FC0 +#define DBG_TGU_DEVID2__WIDTH_BC0___S 6 +#define DBG_TGU_DEVID2__WIDTH_BC1___M 0x0000003F +#define DBG_TGU_DEVID2__WIDTH_BC1___S 0 +#define DBG_TGU_DEVID2___M 0xFFFFEFFF +#define DBG_TGU_DEVID2___S 0 + +#define DBG_TGU_DEVID1 (0x00BC4FC4) +#define DBG_TGU_DEVID1___RWC QCSR_REG_RO +#define DBG_TGU_DEVID1___POR 0x00000000 +#define DBG_TGU_DEVID1__SSC_LSB_GROUP3___POR 0x0 +#define DBG_TGU_DEVID1__SSC_LSB_GROUP2___POR 0x0 +#define DBG_TGU_DEVID1__SSC_LSB_GROUP1___POR 0x0 +#define DBG_TGU_DEVID1__SSC_LSB_GROUP0___POR 0x0 +#define DBG_TGU_DEVID1__SSC_LSB_GROUP3___M 0xFF000000 +#define DBG_TGU_DEVID1__SSC_LSB_GROUP3___S 24 +#define DBG_TGU_DEVID1__SSC_LSB_GROUP2___M 0x00FF0000 +#define DBG_TGU_DEVID1__SSC_LSB_GROUP2___S 16 +#define DBG_TGU_DEVID1__SSC_LSB_GROUP1___M 0x0000FF00 +#define DBG_TGU_DEVID1__SSC_LSB_GROUP1___S 8 +#define DBG_TGU_DEVID1__SSC_LSB_GROUP0___M 0x000000FF +#define DBG_TGU_DEVID1__SSC_LSB_GROUP0___S 0 +#define DBG_TGU_DEVID1___M 0xFFFFFFFF +#define DBG_TGU_DEVID1___S 0 + +#define DBG_TGU_DEVID (0x00BC4FC8) +#define DBG_TGU_DEVID___RWC QCSR_REG_RO +#define DBG_TGU_DEVID___POR 0x0020CA44 +#define DBG_TGU_DEVID__REGISTER_INPUTS_VAL___POR 0x0 +#define DBG_TGU_DEVID__REGISTER_TRIGGER_VAL___POR 0x0 +#define DBG_TGU_DEVID__AXI_WR_CH_VAL___POR 0x0 +#define DBG_TGU_DEVID__ASYNC_APB_VAL___POR 0x1 +#define DBG_TGU_DEVID__TC_CDC_VAL___POR 0x0 +#define DBG_TGU_DEVID__TR_PRESENT_VAL___POR 0x0 +#define DBG_TGU_DEVID__FIRST_TOKEN_VAL___POR 0x0 +#define DBG_TGU_DEVID__NUM_SENSE_INPUTS_VAL___POR 0x32 +#define DBG_TGU_DEVID__NUM_TRIGGERS_VAL___POR 0x4 +#define DBG_TGU_DEVID__NUM_STEPS_VAL___POR 0x8 +#define DBG_TGU_DEVID__NUM_CONDS_VAL___POR 0x4 +#define DBG_TGU_DEVID__REGISTER_INPUTS_VAL___M 0x01000000 +#define DBG_TGU_DEVID__REGISTER_INPUTS_VAL___S 24 +#define DBG_TGU_DEVID__REGISTER_TRIGGER_VAL___M 0x00800000 +#define DBG_TGU_DEVID__REGISTER_TRIGGER_VAL___S 23 +#define DBG_TGU_DEVID__AXI_WR_CH_VAL___M 0x00400000 +#define DBG_TGU_DEVID__AXI_WR_CH_VAL___S 22 +#define DBG_TGU_DEVID__ASYNC_APB_VAL___M 0x00200000 +#define DBG_TGU_DEVID__ASYNC_APB_VAL___S 21 +#define DBG_TGU_DEVID__TC_CDC_VAL___M 0x00100000 +#define DBG_TGU_DEVID__TC_CDC_VAL___S 20 +#define DBG_TGU_DEVID__TR_PRESENT_VAL___M 0x00080000 +#define DBG_TGU_DEVID__TR_PRESENT_VAL___S 19 +#define DBG_TGU_DEVID__FIRST_TOKEN_VAL___M 0x00040000 +#define DBG_TGU_DEVID__FIRST_TOKEN_VAL___S 18 +#define DBG_TGU_DEVID__NUM_SENSE_INPUTS_VAL___M 0x0003FC00 +#define DBG_TGU_DEVID__NUM_SENSE_INPUTS_VAL___S 10 +#define DBG_TGU_DEVID__NUM_TRIGGERS_VAL___M 0x00000380 +#define DBG_TGU_DEVID__NUM_TRIGGERS_VAL___S 7 +#define DBG_TGU_DEVID__NUM_STEPS_VAL___M 0x00000078 +#define DBG_TGU_DEVID__NUM_STEPS_VAL___S 3 +#define DBG_TGU_DEVID__NUM_CONDS_VAL___M 0x00000007 +#define DBG_TGU_DEVID__NUM_CONDS_VAL___S 0 +#define DBG_TGU_DEVID___M 0x01FFFFFF +#define DBG_TGU_DEVID___S 0 + +#define DBG_TGU_PIDR4 (0x00BC4FD0) +#define DBG_TGU_PIDR4___RWC QCSR_REG_RO +#define DBG_TGU_PIDR4___POR 0x00000000 +#define DBG_TGU_PIDR4__SIZE___POR 0x0 +#define DBG_TGU_PIDR4__DES_2___POR 0x0 +#define DBG_TGU_PIDR4__SIZE___M 0x000000F0 +#define DBG_TGU_PIDR4__SIZE___S 4 +#define DBG_TGU_PIDR4__DES_2___M 0x0000000F +#define DBG_TGU_PIDR4__DES_2___S 0 +#define DBG_TGU_PIDR4___M 0x000000FF +#define DBG_TGU_PIDR4___S 0 + +#define DBG_TGU_PIDR5 (0x00BC4FD4) +#define DBG_TGU_PIDR5___RWC QCSR_REG_RO +#define DBG_TGU_PIDR5___POR 0x00000000 +#define DBG_TGU_PIDR5__EMPTY___POR 0x00000000 +#define DBG_TGU_PIDR5__EMPTY___M 0xFFFFFFFF +#define DBG_TGU_PIDR5__EMPTY___S 0 +#define DBG_TGU_PIDR5___M 0xFFFFFFFF +#define DBG_TGU_PIDR5___S 0 + +#define DBG_TGU_PIDR6 (0x00BC4FD8) +#define DBG_TGU_PIDR6___RWC QCSR_REG_RO +#define DBG_TGU_PIDR6___POR 0x00000000 +#define DBG_TGU_PIDR6__EMPTY___POR 0x00000000 +#define DBG_TGU_PIDR6__EMPTY___M 0xFFFFFFFF +#define DBG_TGU_PIDR6__EMPTY___S 0 +#define DBG_TGU_PIDR6___M 0xFFFFFFFF +#define DBG_TGU_PIDR6___S 0 + +#define DBG_TGU_PIDR7 (0x00BC4FDC) +#define DBG_TGU_PIDR7___RWC QCSR_REG_RO +#define DBG_TGU_PIDR7___POR 0x00000000 +#define DBG_TGU_PIDR7__EMPTY___POR 0x00000000 +#define DBG_TGU_PIDR7__EMPTY___M 0xFFFFFFFF +#define DBG_TGU_PIDR7__EMPTY___S 0 +#define DBG_TGU_PIDR7___M 0xFFFFFFFF +#define DBG_TGU_PIDR7___S 0 + +#define DBG_TGU_PIDR0 (0x00BC4FE0) +#define DBG_TGU_PIDR0___RWC QCSR_REG_RO +#define DBG_TGU_PIDR0___POR 0x00000000 +#define DBG_TGU_PIDR0__PART_0___POR 0x00000 +#define DBG_TGU_PIDR0__PART_0___M 0x0007FFFF +#define DBG_TGU_PIDR0__PART_0___S 0 +#define DBG_TGU_PIDR0___M 0x0007FFFF +#define DBG_TGU_PIDR0___S 0 + +#define DBG_TGU_PIDR1 (0x00BC4FE4) +#define DBG_TGU_PIDR1___RWC QCSR_REG_RO +#define DBG_TGU_PIDR1___POR 0x0000000E +#define DBG_TGU_PIDR1__DES_0___POR 0x0 +#define DBG_TGU_PIDR1__PART_1___POR 0xE +#define DBG_TGU_PIDR1__DES_0___M 0x000000F0 +#define DBG_TGU_PIDR1__DES_0___S 4 +#define DBG_TGU_PIDR1__PART_1___M 0x0000000F +#define DBG_TGU_PIDR1__PART_1___S 0 +#define DBG_TGU_PIDR1___M 0x000000FF +#define DBG_TGU_PIDR1___S 0 + +#define DBG_TGU_PIDR2 (0x00BC4FE8) +#define DBG_TGU_PIDR2___RWC QCSR_REG_RO +#define DBG_TGU_PIDR2___POR 0x00000008 +#define DBG_TGU_PIDR2__REVISION___POR 0x0 +#define DBG_TGU_PIDR2__JEDEC___POR 0x1 +#define DBG_TGU_PIDR2__DES_1___POR 0x0 +#define DBG_TGU_PIDR2__REVISION___M 0x000000F0 +#define DBG_TGU_PIDR2__REVISION___S 4 +#define DBG_TGU_PIDR2__JEDEC___M 0x00000008 +#define DBG_TGU_PIDR2__JEDEC___S 3 +#define DBG_TGU_PIDR2__DES_1___M 0x00000007 +#define DBG_TGU_PIDR2__DES_1___S 0 +#define DBG_TGU_PIDR2___M 0x000000FF +#define DBG_TGU_PIDR2___S 0 + +#define DBG_TGU_PIDR3 (0x00BC4FEC) +#define DBG_TGU_PIDR3___RWC QCSR_REG_RO +#define DBG_TGU_PIDR3___POR 0x00000000 +#define DBG_TGU_PIDR3__REVAND___POR 0x0 +#define DBG_TGU_PIDR3__CMOD___POR 0x0 +#define DBG_TGU_PIDR3__REVAND___M 0x000000F0 +#define DBG_TGU_PIDR3__REVAND___S 4 +#define DBG_TGU_PIDR3__CMOD___M 0x0000000F +#define DBG_TGU_PIDR3__CMOD___S 0 +#define DBG_TGU_PIDR3___M 0x000000FF +#define DBG_TGU_PIDR3___S 0 + +#define DBG_TGU_CIDR0 (0x00BC4FF0) +#define DBG_TGU_CIDR0___RWC QCSR_REG_RO +#define DBG_TGU_CIDR0___POR 0x0000000D +#define DBG_TGU_CIDR0__PRMBL_0___POR 0x0D +#define DBG_TGU_CIDR0__PRMBL_0___M 0x000000FF +#define DBG_TGU_CIDR0__PRMBL_0___S 0 +#define DBG_TGU_CIDR0___M 0x000000FF +#define DBG_TGU_CIDR0___S 0 + +#define DBG_TGU_CIDR1 (0x00BC4FF4) +#define DBG_TGU_CIDR1___RWC QCSR_REG_RO +#define DBG_TGU_CIDR1___POR 0x00000090 +#define DBG_TGU_CIDR1__CLASS___POR 0x9 +#define DBG_TGU_CIDR1__PRMBL_1___POR 0x0 +#define DBG_TGU_CIDR1__CLASS___M 0x000000F0 +#define DBG_TGU_CIDR1__CLASS___S 4 +#define DBG_TGU_CIDR1__PRMBL_1___M 0x0000000F +#define DBG_TGU_CIDR1__PRMBL_1___S 0 +#define DBG_TGU_CIDR1___M 0x000000FF +#define DBG_TGU_CIDR1___S 0 + +#define DBG_TGU_CIDR2 (0x00BC4FF8) +#define DBG_TGU_CIDR2___RWC QCSR_REG_RO +#define DBG_TGU_CIDR2___POR 0x00000005 +#define DBG_TGU_CIDR2__PRMBL_2___POR 0x05 +#define DBG_TGU_CIDR2__PRMBL_2___M 0x000000FF +#define DBG_TGU_CIDR2__PRMBL_2___S 0 +#define DBG_TGU_CIDR2___M 0x000000FF +#define DBG_TGU_CIDR2___S 0 + +#define DBG_TGU_CIDR3 (0x00BC4FFC) +#define DBG_TGU_CIDR3___RWC QCSR_REG_RO +#define DBG_TGU_CIDR3___POR 0x000000B1 +#define DBG_TGU_CIDR3__PRMBL_3___POR 0xB1 +#define DBG_TGU_CIDR3__PRMBL_3___M 0x000000FF +#define DBG_TGU_CIDR3__PRMBL_3___S 0 +#define DBG_TGU_CIDR3___M 0x000000FF +#define DBG_TGU_CIDR3___S 0 + +#define DBG_CTITGU_CTICONTROL (0x00BC5000) +#define DBG_CTITGU_CTICONTROL___RWC QCSR_REG_RW +#define DBG_CTITGU_CTICONTROL___POR 0x00000000 +#define DBG_CTITGU_CTICONTROL__GLBEN___POR 0x0 +#define DBG_CTITGU_CTICONTROL__GLBEN___M 0x00000001 +#define DBG_CTITGU_CTICONTROL__GLBEN___S 0 +#define DBG_CTITGU_CTICONTROL__GLBEN__DISABLED 0x0 +#define DBG_CTITGU_CTICONTROL__GLBEN__ENABLED 0x1 +#define DBG_CTITGU_CTICONTROL___M 0x00000001 +#define DBG_CTITGU_CTICONTROL___S 0 + +#define DBG_CTITGU_CTIINTACK (0x00BC5010) +#define DBG_CTITGU_CTIINTACK___RWC QCSR_REG_WO +#define DBG_CTITGU_CTIINTACK___POR 0x00000000 +#define DBG_CTITGU_CTIINTACK__INTACK___POR 0x0 +#define DBG_CTITGU_CTIINTACK__INTACK___M 0x0000000F +#define DBG_CTITGU_CTIINTACK__INTACK___S 0 +#define DBG_CTITGU_CTIINTACK___M 0x0000000F +#define DBG_CTITGU_CTIINTACK___S 0 + +#define DBG_CTITGU_CTIAPPSET (0x00BC5014) +#define DBG_CTITGU_CTIAPPSET___RWC QCSR_REG_RW +#define DBG_CTITGU_CTIAPPSET___POR 0x00000000 +#define DBG_CTITGU_CTIAPPSET__APPSET___POR 0x00 +#define DBG_CTITGU_CTIAPPSET__APPSET___M 0x000000FF +#define DBG_CTITGU_CTIAPPSET__APPSET___S 0 +#define DBG_CTITGU_CTIAPPSET___M 0x000000FF +#define DBG_CTITGU_CTIAPPSET___S 0 + +#define DBG_CTITGU_CTIAPPCLEAR (0x00BC5018) +#define DBG_CTITGU_CTIAPPCLEAR___RWC QCSR_REG_WO +#define DBG_CTITGU_CTIAPPCLEAR___POR 0x00000000 +#define DBG_CTITGU_CTIAPPCLEAR__APPCLEAR___POR 0x00 +#define DBG_CTITGU_CTIAPPCLEAR__APPCLEAR___M 0x000000FF +#define DBG_CTITGU_CTIAPPCLEAR__APPCLEAR___S 0 +#define DBG_CTITGU_CTIAPPCLEAR___M 0x000000FF +#define DBG_CTITGU_CTIAPPCLEAR___S 0 + +#define DBG_CTITGU_CTIAPPPULSE (0x00BC501C) +#define DBG_CTITGU_CTIAPPPULSE___RWC QCSR_REG_WO +#define DBG_CTITGU_CTIAPPPULSE___POR 0x00000000 +#define DBG_CTITGU_CTIAPPPULSE__APPULSE___POR 0x00 +#define DBG_CTITGU_CTIAPPPULSE__APPULSE___M 0x000000FF +#define DBG_CTITGU_CTIAPPPULSE__APPULSE___S 0 +#define DBG_CTITGU_CTIAPPPULSE___M 0x000000FF +#define DBG_CTITGU_CTIAPPPULSE___S 0 + +#define DBG_CTITGU_CTIINEN0 (0x00BC5020) +#define DBG_CTITGU_CTIINEN0___RWC QCSR_REG_RW +#define DBG_CTITGU_CTIINEN0___POR 0x00000000 +#define DBG_CTITGU_CTIINEN0__TRIGINEN___POR 0x00 +#define DBG_CTITGU_CTIINEN0__TRIGINEN___M 0x000000FF +#define DBG_CTITGU_CTIINEN0__TRIGINEN___S 0 +#define DBG_CTITGU_CTIINEN0___M 0x000000FF +#define DBG_CTITGU_CTIINEN0___S 0 + +#define DBG_CTITGU_CTIINEN1 (0x00BC5024) +#define DBG_CTITGU_CTIINEN1___RWC QCSR_REG_RW +#define DBG_CTITGU_CTIINEN1___POR 0x00000000 +#define DBG_CTITGU_CTIINEN1__TRIGINEN___POR 0x00 +#define DBG_CTITGU_CTIINEN1__TRIGINEN___M 0x000000FF +#define DBG_CTITGU_CTIINEN1__TRIGINEN___S 0 +#define DBG_CTITGU_CTIINEN1___M 0x000000FF +#define DBG_CTITGU_CTIINEN1___S 0 + +#define DBG_CTITGU_CTIINEN2 (0x00BC5028) +#define DBG_CTITGU_CTIINEN2___RWC QCSR_REG_RW +#define DBG_CTITGU_CTIINEN2___POR 0x00000000 +#define DBG_CTITGU_CTIINEN2__TRIGINEN___POR 0x00 +#define DBG_CTITGU_CTIINEN2__TRIGINEN___M 0x000000FF +#define DBG_CTITGU_CTIINEN2__TRIGINEN___S 0 +#define DBG_CTITGU_CTIINEN2___M 0x000000FF +#define DBG_CTITGU_CTIINEN2___S 0 + +#define DBG_CTITGU_CTIINEN3 (0x00BC502C) +#define DBG_CTITGU_CTIINEN3___RWC QCSR_REG_RW +#define DBG_CTITGU_CTIINEN3___POR 0x00000000 +#define DBG_CTITGU_CTIINEN3__TRIGINEN___POR 0x00 +#define DBG_CTITGU_CTIINEN3__TRIGINEN___M 0x000000FF +#define DBG_CTITGU_CTIINEN3__TRIGINEN___S 0 +#define DBG_CTITGU_CTIINEN3___M 0x000000FF +#define DBG_CTITGU_CTIINEN3___S 0 + +#define DBG_CTITGU_CTIOUTEN0 (0x00BC50A0) +#define DBG_CTITGU_CTIOUTEN0___RWC QCSR_REG_RW +#define DBG_CTITGU_CTIOUTEN0___POR 0x00000000 +#define DBG_CTITGU_CTIOUTEN0__TRIGOUTEN___POR 0x00 +#define DBG_CTITGU_CTIOUTEN0__TRIGOUTEN___M 0x000000FF +#define DBG_CTITGU_CTIOUTEN0__TRIGOUTEN___S 0 +#define DBG_CTITGU_CTIOUTEN0___M 0x000000FF +#define DBG_CTITGU_CTIOUTEN0___S 0 + +#define DBG_CTITGU_CTIOUTEN1 (0x00BC50A4) +#define DBG_CTITGU_CTIOUTEN1___RWC QCSR_REG_RW +#define DBG_CTITGU_CTIOUTEN1___POR 0x00000000 +#define DBG_CTITGU_CTIOUTEN1__TRIGOUTEN___POR 0x00 +#define DBG_CTITGU_CTIOUTEN1__TRIGOUTEN___M 0x000000FF +#define DBG_CTITGU_CTIOUTEN1__TRIGOUTEN___S 0 +#define DBG_CTITGU_CTIOUTEN1___M 0x000000FF +#define DBG_CTITGU_CTIOUTEN1___S 0 + +#define DBG_CTITGU_CTIOUTEN2 (0x00BC50A8) +#define DBG_CTITGU_CTIOUTEN2___RWC QCSR_REG_RW +#define DBG_CTITGU_CTIOUTEN2___POR 0x00000000 +#define DBG_CTITGU_CTIOUTEN2__TRIGOUTEN___POR 0x00 +#define DBG_CTITGU_CTIOUTEN2__TRIGOUTEN___M 0x000000FF +#define DBG_CTITGU_CTIOUTEN2__TRIGOUTEN___S 0 +#define DBG_CTITGU_CTIOUTEN2___M 0x000000FF +#define DBG_CTITGU_CTIOUTEN2___S 0 + +#define DBG_CTITGU_CTIOUTEN3 (0x00BC50AC) +#define DBG_CTITGU_CTIOUTEN3___RWC QCSR_REG_RW +#define DBG_CTITGU_CTIOUTEN3___POR 0x00000000 +#define DBG_CTITGU_CTIOUTEN3__TRIGOUTEN___POR 0x00 +#define DBG_CTITGU_CTIOUTEN3__TRIGOUTEN___M 0x000000FF +#define DBG_CTITGU_CTIOUTEN3__TRIGOUTEN___S 0 +#define DBG_CTITGU_CTIOUTEN3___M 0x000000FF +#define DBG_CTITGU_CTIOUTEN3___S 0 + +#define DBG_CTITGU_CTITRIGINSTATUS (0x00BC5130) +#define DBG_CTITGU_CTITRIGINSTATUS___RWC QCSR_REG_RO +#define DBG_CTITGU_CTITRIGINSTATUS__TRIGINSTATUS___M 0x0000000F +#define DBG_CTITGU_CTITRIGINSTATUS__TRIGINSTATUS___S 0 +#define DBG_CTITGU_CTITRIGINSTATUS___M 0x0000000F +#define DBG_CTITGU_CTITRIGINSTATUS___S 0 + +#define DBG_CTITGU_CTITRIGOUTSTATUS (0x00BC5134) +#define DBG_CTITGU_CTITRIGOUTSTATUS___RWC QCSR_REG_RO +#define DBG_CTITGU_CTITRIGOUTSTATUS___POR 0x00000000 +#define DBG_CTITGU_CTITRIGOUTSTATUS__TRIGOUTSTATUS___POR 0x0 +#define DBG_CTITGU_CTITRIGOUTSTATUS__TRIGOUTSTATUS___M 0x0000000F +#define DBG_CTITGU_CTITRIGOUTSTATUS__TRIGOUTSTATUS___S 0 +#define DBG_CTITGU_CTITRIGOUTSTATUS___M 0x0000000F +#define DBG_CTITGU_CTITRIGOUTSTATUS___S 0 + +#define DBG_CTITGU_CTICHINSTATUS (0x00BC5138) +#define DBG_CTITGU_CTICHINSTATUS___RWC QCSR_REG_RO +#define DBG_CTITGU_CTICHINSTATUS__CTICHINSTATUS___M 0x000000FF +#define DBG_CTITGU_CTICHINSTATUS__CTICHINSTATUS___S 0 +#define DBG_CTITGU_CTICHINSTATUS___M 0x000000FF +#define DBG_CTITGU_CTICHINSTATUS___S 0 + +#define DBG_CTITGU_CTICHOUTSTATUS (0x00BC513C) +#define DBG_CTITGU_CTICHOUTSTATUS___RWC QCSR_REG_RO +#define DBG_CTITGU_CTICHOUTSTATUS___POR 0x00000000 +#define DBG_CTITGU_CTICHOUTSTATUS__CTICHOUTSTATUS___POR 0x00 +#define DBG_CTITGU_CTICHOUTSTATUS__CTICHOUTSTATUS___M 0x000000FF +#define DBG_CTITGU_CTICHOUTSTATUS__CTICHOUTSTATUS___S 0 +#define DBG_CTITGU_CTICHOUTSTATUS___M 0x000000FF +#define DBG_CTITGU_CTICHOUTSTATUS___S 0 + +#define DBG_CTITGU_CTIGATE (0x00BC5140) +#define DBG_CTITGU_CTIGATE___RWC QCSR_REG_RW +#define DBG_CTITGU_CTIGATE___POR 0x000000FF +#define DBG_CTITGU_CTIGATE__CTIGATEEN7___POR 0x1 +#define DBG_CTITGU_CTIGATE__CTIGATEEN6___POR 0x1 +#define DBG_CTITGU_CTIGATE__CTIGATEEN5___POR 0x1 +#define DBG_CTITGU_CTIGATE__CTIGATEEN4___POR 0x1 +#define DBG_CTITGU_CTIGATE__CTIGATEEN3___POR 0x1 +#define DBG_CTITGU_CTIGATE__CTIGATEEN2___POR 0x1 +#define DBG_CTITGU_CTIGATE__CTIGATEEN1___POR 0x1 +#define DBG_CTITGU_CTIGATE__CTIGATEEN0___POR 0x1 +#define DBG_CTITGU_CTIGATE__CTIGATEEN7___M 0x00000080 +#define DBG_CTITGU_CTIGATE__CTIGATEEN7___S 7 +#define DBG_CTITGU_CTIGATE__CTIGATEEN6___M 0x00000040 +#define DBG_CTITGU_CTIGATE__CTIGATEEN6___S 6 +#define DBG_CTITGU_CTIGATE__CTIGATEEN5___M 0x00000020 +#define DBG_CTITGU_CTIGATE__CTIGATEEN5___S 5 +#define DBG_CTITGU_CTIGATE__CTIGATEEN4___M 0x00000010 +#define DBG_CTITGU_CTIGATE__CTIGATEEN4___S 4 +#define DBG_CTITGU_CTIGATE__CTIGATEEN3___M 0x00000008 +#define DBG_CTITGU_CTIGATE__CTIGATEEN3___S 3 +#define DBG_CTITGU_CTIGATE__CTIGATEEN2___M 0x00000004 +#define DBG_CTITGU_CTIGATE__CTIGATEEN2___S 2 +#define DBG_CTITGU_CTIGATE__CTIGATEEN1___M 0x00000002 +#define DBG_CTITGU_CTIGATE__CTIGATEEN1___S 1 +#define DBG_CTITGU_CTIGATE__CTIGATEEN0___M 0x00000001 +#define DBG_CTITGU_CTIGATE__CTIGATEEN0___S 0 +#define DBG_CTITGU_CTIGATE___M 0x000000FF +#define DBG_CTITGU_CTIGATE___S 0 + +#define DBG_CTITGU_ASICCTL (0x00BC5144) +#define DBG_CTITGU_ASICCTL___RWC QCSR_REG_RW +#define DBG_CTITGU_ASICCTL___POR 0x00000000 +#define DBG_CTITGU_ASICCTL__ASICCTL___POR 0x00000000 +#define DBG_CTITGU_ASICCTL__ASICCTL___M 0xFFFFFFFF +#define DBG_CTITGU_ASICCTL__ASICCTL___S 0 +#define DBG_CTITGU_ASICCTL___M 0xFFFFFFFF +#define DBG_CTITGU_ASICCTL___S 0 + +#define DBG_CTITGU_ITCHINACK (0x00BC5EDC) +#define DBG_CTITGU_ITCHINACK___RWC QCSR_REG_WO +#define DBG_CTITGU_ITCHINACK___POR 0x00000000 +#define DBG_CTITGU_ITCHINACK__CTCHINACK___POR 0x00 +#define DBG_CTITGU_ITCHINACK__CTCHINACK___M 0x000000FF +#define DBG_CTITGU_ITCHINACK__CTCHINACK___S 0 +#define DBG_CTITGU_ITCHINACK___M 0x000000FF +#define DBG_CTITGU_ITCHINACK___S 0 + +#define DBG_CTITGU_ITTRIGINACK (0x00BC5EE0) +#define DBG_CTITGU_ITTRIGINACK___RWC QCSR_REG_WO +#define DBG_CTITGU_ITTRIGINACK___POR 0x00000000 +#define DBG_CTITGU_ITTRIGINACK__CTTRIGINACK___POR 0x0 +#define DBG_CTITGU_ITTRIGINACK__CTTRIGINACK___M 0x0000000F +#define DBG_CTITGU_ITTRIGINACK__CTTRIGINACK___S 0 +#define DBG_CTITGU_ITTRIGINACK___M 0x0000000F +#define DBG_CTITGU_ITTRIGINACK___S 0 + +#define DBG_CTITGU_ITCHOUT (0x00BC5EE4) +#define DBG_CTITGU_ITCHOUT___RWC QCSR_REG_WO +#define DBG_CTITGU_ITCHOUT___POR 0x00000000 +#define DBG_CTITGU_ITCHOUT__CTCHOUT___POR 0x00 +#define DBG_CTITGU_ITCHOUT__CTCHOUT___M 0x000000FF +#define DBG_CTITGU_ITCHOUT__CTCHOUT___S 0 +#define DBG_CTITGU_ITCHOUT___M 0x000000FF +#define DBG_CTITGU_ITCHOUT___S 0 + +#define DBG_CTITGU_ITTRIGOUT (0x00BC5EE8) +#define DBG_CTITGU_ITTRIGOUT___RWC QCSR_REG_WO +#define DBG_CTITGU_ITTRIGOUT___POR 0x00000000 +#define DBG_CTITGU_ITTRIGOUT__CTTRIGOUT___POR 0x0 +#define DBG_CTITGU_ITTRIGOUT__CTTRIGOUT___M 0x0000000F +#define DBG_CTITGU_ITTRIGOUT__CTTRIGOUT___S 0 +#define DBG_CTITGU_ITTRIGOUT___M 0x0000000F +#define DBG_CTITGU_ITTRIGOUT___S 0 + +#define DBG_CTITGU_ITCHOUTACK (0x00BC5EEC) +#define DBG_CTITGU_ITCHOUTACK___RWC QCSR_REG_RO +#define DBG_CTITGU_ITCHOUTACK___POR 0x00000000 +#define DBG_CTITGU_ITCHOUTACK__CTCHOUTACK___POR 0x00 +#define DBG_CTITGU_ITCHOUTACK__CTCHOUTACK___M 0x000000FF +#define DBG_CTITGU_ITCHOUTACK__CTCHOUTACK___S 0 +#define DBG_CTITGU_ITCHOUTACK___M 0x000000FF +#define DBG_CTITGU_ITCHOUTACK___S 0 + +#define DBG_CTITGU_ITTRIGOUTACK (0x00BC5EF0) +#define DBG_CTITGU_ITTRIGOUTACK___RWC QCSR_REG_RO +#define DBG_CTITGU_ITTRIGOUTACK___POR 0x00000000 +#define DBG_CTITGU_ITTRIGOUTACK__CTTRIGOUTACK___POR 0x0 +#define DBG_CTITGU_ITTRIGOUTACK__CTTRIGOUTACK___M 0x0000000F +#define DBG_CTITGU_ITTRIGOUTACK__CTTRIGOUTACK___S 0 +#define DBG_CTITGU_ITTRIGOUTACK___M 0x0000000F +#define DBG_CTITGU_ITTRIGOUTACK___S 0 + +#define DBG_CTITGU_ITCHIN (0x00BC5EF4) +#define DBG_CTITGU_ITCHIN___RWC QCSR_REG_RO +#define DBG_CTITGU_ITCHIN___POR 0x00000000 +#define DBG_CTITGU_ITCHIN__CTCHIN___POR 0x00 +#define DBG_CTITGU_ITCHIN__CTCHIN___M 0x000000FF +#define DBG_CTITGU_ITCHIN__CTCHIN___S 0 +#define DBG_CTITGU_ITCHIN___M 0x000000FF +#define DBG_CTITGU_ITCHIN___S 0 + +#define DBG_CTITGU_ITTRIGIN (0x00BC5EF8) +#define DBG_CTITGU_ITTRIGIN___RWC QCSR_REG_RO +#define DBG_CTITGU_ITTRIGIN___POR 0x00000000 +#define DBG_CTITGU_ITTRIGIN__CTTRIGIN___POR 0x0 +#define DBG_CTITGU_ITTRIGIN__CTTRIGIN___M 0x0000000F +#define DBG_CTITGU_ITTRIGIN__CTTRIGIN___S 0 +#define DBG_CTITGU_ITTRIGIN___M 0x0000000F +#define DBG_CTITGU_ITTRIGIN___S 0 + +#define DBG_CTITGU_ITCTRL (0x00BC5F00) +#define DBG_CTITGU_ITCTRL___RWC QCSR_REG_RW +#define DBG_CTITGU_ITCTRL___POR 0x00000000 +#define DBG_CTITGU_ITCTRL__INTEGRATION_MODE___POR 0x0 +#define DBG_CTITGU_ITCTRL__INTEGRATION_MODE___M 0x00000001 +#define DBG_CTITGU_ITCTRL__INTEGRATION_MODE___S 0 +#define DBG_CTITGU_ITCTRL__INTEGRATION_MODE__FUNCTIONAL_MODE 0x0 +#define DBG_CTITGU_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE 0x1 +#define DBG_CTITGU_ITCTRL___M 0x00000001 +#define DBG_CTITGU_ITCTRL___S 0 + +#define DBG_CTITGU_CLAIMSET (0x00BC5FA0) +#define DBG_CTITGU_CLAIMSET___RWC QCSR_REG_RW +#define DBG_CTITGU_CLAIMSET___POR 0x0000000F +#define DBG_CTITGU_CLAIMSET__CLAIMSET___POR 0xF +#define DBG_CTITGU_CLAIMSET__CLAIMSET___M 0x0000000F +#define DBG_CTITGU_CLAIMSET__CLAIMSET___S 0 +#define DBG_CTITGU_CLAIMSET__CLAIMSET__CLAIM_TAG_IMPLEMENTED_BITS 0xF +#define DBG_CTITGU_CLAIMSET___M 0x0000000F +#define DBG_CTITGU_CLAIMSET___S 0 + +#define DBG_CTITGU_CLAIMCLR (0x00BC5FA4) +#define DBG_CTITGU_CLAIMCLR___RWC QCSR_REG_RW +#define DBG_CTITGU_CLAIMCLR___POR 0x00000000 +#define DBG_CTITGU_CLAIMCLR__CLAIMCLR___POR 0x0 +#define DBG_CTITGU_CLAIMCLR__CLAIMCLR___M 0x0000000F +#define DBG_CTITGU_CLAIMCLR__CLAIMCLR___S 0 +#define DBG_CTITGU_CLAIMCLR___M 0x0000000F +#define DBG_CTITGU_CLAIMCLR___S 0 + +#define DBG_CTITGU_DEVAFF0 (0x00BC5FA8) +#define DBG_CTITGU_DEVAFF0___RWC QCSR_REG_RO +#define DBG_CTITGU_DEVAFF0___POR 0x00000000 +#define DBG_CTITGU_DEVAFF0__VAL___POR 0x00000000 +#define DBG_CTITGU_DEVAFF0__VAL___M 0xFFFFFFFF +#define DBG_CTITGU_DEVAFF0__VAL___S 0 +#define DBG_CTITGU_DEVAFF0___M 0xFFFFFFFF +#define DBG_CTITGU_DEVAFF0___S 0 + +#define DBG_CTITGU_DEVAFF1 (0x00BC5FAC) +#define DBG_CTITGU_DEVAFF1___RWC QCSR_REG_RO +#define DBG_CTITGU_DEVAFF1___POR 0x00000000 +#define DBG_CTITGU_DEVAFF1__VAL___POR 0x00000000 +#define DBG_CTITGU_DEVAFF1__VAL___M 0xFFFFFFFF +#define DBG_CTITGU_DEVAFF1__VAL___S 0 +#define DBG_CTITGU_DEVAFF1___M 0xFFFFFFFF +#define DBG_CTITGU_DEVAFF1___S 0 + +#define DBG_CTITGU_LAR (0x00BC5FB0) +#define DBG_CTITGU_LAR___RWC QCSR_REG_WO +#define DBG_CTITGU_LAR__ACCESS_W___M 0xFFFFFFFF +#define DBG_CTITGU_LAR__ACCESS_W___S 0 +#define DBG_CTITGU_LAR__ACCESS_W__UNLOCK 0xC5ACCE55 +#define DBG_CTITGU_LAR___M 0xFFFFFFFF +#define DBG_CTITGU_LAR___S 0 + +#define DBG_CTITGU_LSR (0x00BC5FB4) +#define DBG_CTITGU_LSR___RWC QCSR_REG_RO +#define DBG_CTITGU_LSR___POR 0x00000003 +#define DBG_CTITGU_LSR__LOCKTYPE___POR 0x0 +#define DBG_CTITGU_LSR__LOCKGRANT___POR 0x1 +#define DBG_CTITGU_LSR__LOCKEXIST___POR 0x1 +#define DBG_CTITGU_LSR__LOCKTYPE___M 0x00000004 +#define DBG_CTITGU_LSR__LOCKTYPE___S 2 +#define DBG_CTITGU_LSR__LOCKTYPE__SIZE_32BIT 0x0 +#define DBG_CTITGU_LSR__LOCKGRANT___M 0x00000002 +#define DBG_CTITGU_LSR__LOCKGRANT___S 1 +#define DBG_CTITGU_LSR__LOCKGRANT__ACCESS_PERMITTED 0x0 +#define DBG_CTITGU_LSR__LOCKGRANT__DEVICE_LOCKED 0x1 +#define DBG_CTITGU_LSR__LOCKEXIST___M 0x00000001 +#define DBG_CTITGU_LSR__LOCKEXIST___S 0 +#define DBG_CTITGU_LSR__LOCKEXIST__LOCK_NOT_PRESENT 0x0 +#define DBG_CTITGU_LSR__LOCKEXIST__LOCK_PRESENT 0x1 +#define DBG_CTITGU_LSR___M 0x00000007 +#define DBG_CTITGU_LSR___S 0 + +#define DBG_CTITGU_AUTHSTATUS (0x00BC5FB8) +#define DBG_CTITGU_AUTHSTATUS___RWC QCSR_REG_RO +#define DBG_CTITGU_AUTHSTATUS__SNID___M 0x000000C0 +#define DBG_CTITGU_AUTHSTATUS__SNID___S 6 +#define DBG_CTITGU_AUTHSTATUS__SNID__NOT_IMPLEMENTED 0x0 +#define DBG_CTITGU_AUTHSTATUS__SID___M 0x00000030 +#define DBG_CTITGU_AUTHSTATUS__SID___S 4 +#define DBG_CTITGU_AUTHSTATUS__SID__NOT_IMPLEMENTED 0x0 +#define DBG_CTITGU_AUTHSTATUS__NSNID___M 0x0000000C +#define DBG_CTITGU_AUTHSTATUS__NSNID___S 2 +#define DBG_CTITGU_AUTHSTATUS__NSNID__DISABLED 0x2 +#define DBG_CTITGU_AUTHSTATUS__NSNID__ENABLED 0x3 +#define DBG_CTITGU_AUTHSTATUS__NSID___M 0x00000003 +#define DBG_CTITGU_AUTHSTATUS__NSID___S 0 +#define DBG_CTITGU_AUTHSTATUS__NSID__DISABLED 0x2 +#define DBG_CTITGU_AUTHSTATUS__NSID__ENABLED 0x3 +#define DBG_CTITGU_AUTHSTATUS___M 0x000000FF +#define DBG_CTITGU_AUTHSTATUS___S 0 + +#define DBG_CTITGU_DEVARCH (0x00BC5FBC) +#define DBG_CTITGU_DEVARCH___RWC QCSR_REG_RO +#define DBG_CTITGU_DEVARCH___POR 0x8EF00A14 +#define DBG_CTITGU_DEVARCH__ARCHITECT___POR 0x477 +#define DBG_CTITGU_DEVARCH__PRESENT___POR 0x1 +#define DBG_CTITGU_DEVARCH__REVISION___POR 0x0 +#define DBG_CTITGU_DEVARCH__ARCHID___POR 0x0A14 +#define DBG_CTITGU_DEVARCH__ARCHITECT___M 0xFFE00000 +#define DBG_CTITGU_DEVARCH__ARCHITECT___S 21 +#define DBG_CTITGU_DEVARCH__PRESENT___M 0x00100000 +#define DBG_CTITGU_DEVARCH__PRESENT___S 20 +#define DBG_CTITGU_DEVARCH__REVISION___M 0x000F0000 +#define DBG_CTITGU_DEVARCH__REVISION___S 16 +#define DBG_CTITGU_DEVARCH__ARCHID___M 0x0000FFFF +#define DBG_CTITGU_DEVARCH__ARCHID___S 0 +#define DBG_CTITGU_DEVARCH___M 0xFFFFFFFF +#define DBG_CTITGU_DEVARCH___S 0 + +#define DBG_CTITGU_DEVID2 (0x00BC5FC0) +#define DBG_CTITGU_DEVID2___RWC QCSR_REG_RO +#define DBG_CTITGU_DEVID2___POR 0x00000000 +#define DBG_CTITGU_DEVID2__IMPLDEF___POR 0x0 +#define DBG_CTITGU_DEVID2__IMPLDEF___M 0x00000001 +#define DBG_CTITGU_DEVID2__IMPLDEF___S 0 +#define DBG_CTITGU_DEVID2___M 0x00000001 +#define DBG_CTITGU_DEVID2___S 0 + +#define DBG_CTITGU_DEVID1 (0x00BC5FC4) +#define DBG_CTITGU_DEVID1___RWC QCSR_REG_RO +#define DBG_CTITGU_DEVID1___POR 0x00000000 +#define DBG_CTITGU_DEVID1__IMPLDEF___POR 0x0 +#define DBG_CTITGU_DEVID1__IMPLDEF___M 0x00000001 +#define DBG_CTITGU_DEVID1__IMPLDEF___S 0 +#define DBG_CTITGU_DEVID1___M 0x00000001 +#define DBG_CTITGU_DEVID1___S 0 + +#define DBG_CTITGU_DEVID (0x00BC5FC8) +#define DBG_CTITGU_DEVID___RWC QCSR_REG_RO +#define DBG_CTITGU_DEVID___POR 0x00080400 +#define DBG_CTITGU_DEVID__NUMCH___POR 0x8 +#define DBG_CTITGU_DEVID__NUMTRIG___POR 0x4 +#define DBG_CTITGU_DEVID__EXTMUXNUM___POR 0x00 +#define DBG_CTITGU_DEVID__NUMCH___M 0x003F0000 +#define DBG_CTITGU_DEVID__NUMCH___S 16 +#define DBG_CTITGU_DEVID__NUMTRIG___M 0x0000FF00 +#define DBG_CTITGU_DEVID__NUMTRIG___S 8 +#define DBG_CTITGU_DEVID__EXTMUXNUM___M 0x0000001F +#define DBG_CTITGU_DEVID__EXTMUXNUM___S 0 +#define DBG_CTITGU_DEVID___M 0x003FFF1F +#define DBG_CTITGU_DEVID___S 0 + +#define DBG_CTITGU_DEVTYPE (0x00BC5FCC) +#define DBG_CTITGU_DEVTYPE___RWC QCSR_REG_RO +#define DBG_CTITGU_DEVTYPE___POR 0x00000014 +#define DBG_CTITGU_DEVTYPE__SUB_TYPE___POR 0x1 +#define DBG_CTITGU_DEVTYPE__MAJOR_TYPE___POR 0x4 +#define DBG_CTITGU_DEVTYPE__SUB_TYPE___M 0x000000F0 +#define DBG_CTITGU_DEVTYPE__SUB_TYPE___S 4 +#define DBG_CTITGU_DEVTYPE__SUB_TYPE__TRIGGER_MATRIX 0x1 +#define DBG_CTITGU_DEVTYPE__MAJOR_TYPE___M 0x0000000F +#define DBG_CTITGU_DEVTYPE__MAJOR_TYPE___S 0 +#define DBG_CTITGU_DEVTYPE__MAJOR_TYPE__DEBUG_CONTROL 0x4 +#define DBG_CTITGU_DEVTYPE___M 0x000000FF +#define DBG_CTITGU_DEVTYPE___S 0 + +#define DBG_CTITGU_PIDR0 (0x00BC5FE0) +#define DBG_CTITGU_PIDR0___RWC QCSR_REG_RO +#define DBG_CTITGU_PIDR0___POR 0x00000006 +#define DBG_CTITGU_PIDR0__PART_0___POR 0x06 +#define DBG_CTITGU_PIDR0__PART_0___M 0x000000FF +#define DBG_CTITGU_PIDR0__PART_0___S 0 +#define DBG_CTITGU_PIDR0__PART_0__CTI_PART_NUMBER_7_0 0x06 +#define DBG_CTITGU_PIDR0___M 0x000000FF +#define DBG_CTITGU_PIDR0___S 0 + +#define DBG_CTITGU_PIDR1 (0x00BC5FE4) +#define DBG_CTITGU_PIDR1___RWC QCSR_REG_RO +#define DBG_CTITGU_PIDR1___POR 0x000000B9 +#define DBG_CTITGU_PIDR1__DES_0___POR 0xB +#define DBG_CTITGU_PIDR1__PART_1___POR 0x9 +#define DBG_CTITGU_PIDR1__DES_0___M 0x000000F0 +#define DBG_CTITGU_PIDR1__DES_0___S 4 +#define DBG_CTITGU_PIDR1__DES_0__ARM_JEP106_IDENTITY_CODE_3_0 0xB +#define DBG_CTITGU_PIDR1__PART_1___M 0x0000000F +#define DBG_CTITGU_PIDR1__PART_1___S 0 +#define DBG_CTITGU_PIDR1__PART_1__CTI_PART_NUMBER_11_8 0x9 +#define DBG_CTITGU_PIDR1___M 0x000000FF +#define DBG_CTITGU_PIDR1___S 0 + +#define DBG_CTITGU_PIDR2 (0x00BC5FE8) +#define DBG_CTITGU_PIDR2___RWC QCSR_REG_RO +#define DBG_CTITGU_PIDR2___POR 0x0000004B +#define DBG_CTITGU_PIDR2__REVISION___POR 0x4 +#define DBG_CTITGU_PIDR2__JEDEC___POR 0x1 +#define DBG_CTITGU_PIDR2__DES_1___POR 0x3 +#define DBG_CTITGU_PIDR2__REVISION___M 0x000000F0 +#define DBG_CTITGU_PIDR2__REVISION___S 4 +#define DBG_CTITGU_PIDR2__REVISION__R0P4 0x4 +#define DBG_CTITGU_PIDR2__REVISION__R0P5 0x5 +#define DBG_CTITGU_PIDR2__JEDEC___M 0x00000008 +#define DBG_CTITGU_PIDR2__JEDEC___S 3 +#define DBG_CTITGU_PIDR2__JEDEC__JEDEC_IDENTITY 0x1 +#define DBG_CTITGU_PIDR2__DES_1___M 0x00000007 +#define DBG_CTITGU_PIDR2__DES_1___S 0 +#define DBG_CTITGU_PIDR2__DES_1__ARM_JEP106_IDENTITY_CODE_6_4 0x3 +#define DBG_CTITGU_PIDR2___M 0x000000FF +#define DBG_CTITGU_PIDR2___S 0 + +#define DBG_CTITGU_PIDR3 (0x00BC5FEC) +#define DBG_CTITGU_PIDR3___RWC QCSR_REG_RO +#define DBG_CTITGU_PIDR3___POR 0x00000000 +#define DBG_CTITGU_PIDR3__REVAND___POR 0x0 +#define DBG_CTITGU_PIDR3__CMOD___POR 0x0 +#define DBG_CTITGU_PIDR3__REVAND___M 0x000000F0 +#define DBG_CTITGU_PIDR3__REVAND___S 4 +#define DBG_CTITGU_PIDR3__REVAND__NO_MODIFICATION 0x0 +#define DBG_CTITGU_PIDR3__CMOD___M 0x0000000F +#define DBG_CTITGU_PIDR3__CMOD___S 0 +#define DBG_CTITGU_PIDR3__CMOD__NO_MODIFICATION 0x0 +#define DBG_CTITGU_PIDR3___M 0x000000FF +#define DBG_CTITGU_PIDR3___S 0 + +#define DBG_CTITGU_PIDR4 (0x00BC5FD0) +#define DBG_CTITGU_PIDR4___RWC QCSR_REG_RO +#define DBG_CTITGU_PIDR4___POR 0x00000004 +#define DBG_CTITGU_PIDR4__SIZE___POR 0x0 +#define DBG_CTITGU_PIDR4__DES_2___POR 0x4 +#define DBG_CTITGU_PIDR4__SIZE___M 0x000000F0 +#define DBG_CTITGU_PIDR4__SIZE___S 4 +#define DBG_CTITGU_PIDR4__SIZE__SIZE_4KB 0x0 +#define DBG_CTITGU_PIDR4__DES_2___M 0x0000000F +#define DBG_CTITGU_PIDR4__DES_2___S 0 +#define DBG_CTITGU_PIDR4__DES_2__ARM_JEP106_CONTINUATION_CODE 0x4 +#define DBG_CTITGU_PIDR4___M 0x000000FF +#define DBG_CTITGU_PIDR4___S 0 + +#define DBG_CTITGU_PIDR5 (0x00BC5FD4) +#define DBG_CTITGU_PIDR5___RWC QCSR_REG_RW +#define DBG_CTITGU_PIDR5__PERIPHID5___M 0xFFFFFFFF +#define DBG_CTITGU_PIDR5__PERIPHID5___S 0 +#define DBG_CTITGU_PIDR5___M 0xFFFFFFFF +#define DBG_CTITGU_PIDR5___S 0 + +#define DBG_CTITGU_PIDR6 (0x00BC5FD8) +#define DBG_CTITGU_PIDR6___RWC QCSR_REG_RW +#define DBG_CTITGU_PIDR6__PERIPHID6___M 0xFFFFFFFF +#define DBG_CTITGU_PIDR6__PERIPHID6___S 0 +#define DBG_CTITGU_PIDR6___M 0xFFFFFFFF +#define DBG_CTITGU_PIDR6___S 0 + +#define DBG_CTITGU_PIDR7 (0x00BC5FDC) +#define DBG_CTITGU_PIDR7___RWC QCSR_REG_RW +#define DBG_CTITGU_PIDR7__PERIPHID7___M 0xFFFFFFFF +#define DBG_CTITGU_PIDR7__PERIPHID7___S 0 +#define DBG_CTITGU_PIDR7___M 0xFFFFFFFF +#define DBG_CTITGU_PIDR7___S 0 + +#define DBG_CTITGU_CIDR0 (0x00BC5FF0) +#define DBG_CTITGU_CIDR0___RWC QCSR_REG_RO +#define DBG_CTITGU_CIDR0___POR 0x0000000D +#define DBG_CTITGU_CIDR0__PRMBL_0___POR 0x0D +#define DBG_CTITGU_CIDR0__PRMBL_0___M 0x000000FF +#define DBG_CTITGU_CIDR0__PRMBL_0___S 0 +#define DBG_CTITGU_CIDR0__PRMBL_0__ID_VALUE_0D 0x0D +#define DBG_CTITGU_CIDR0___M 0x000000FF +#define DBG_CTITGU_CIDR0___S 0 + +#define DBG_CTITGU_CIDR1 (0x00BC5FF4) +#define DBG_CTITGU_CIDR1___RWC QCSR_REG_RO +#define DBG_CTITGU_CIDR1___POR 0x00000090 +#define DBG_CTITGU_CIDR1__CLASS___POR 0x9 +#define DBG_CTITGU_CIDR1__PRMBL_1___POR 0x0 +#define DBG_CTITGU_CIDR1__CLASS___M 0x000000F0 +#define DBG_CTITGU_CIDR1__CLASS___S 4 +#define DBG_CTITGU_CIDR1__CLASS__CORESIGHT_COMPONENT 0x9 +#define DBG_CTITGU_CIDR1__PRMBL_1___M 0x0000000F +#define DBG_CTITGU_CIDR1__PRMBL_1___S 0 +#define DBG_CTITGU_CIDR1__PRMBL_1__ID_VALUE_0 0x0 +#define DBG_CTITGU_CIDR1___M 0x000000FF +#define DBG_CTITGU_CIDR1___S 0 + +#define DBG_CTITGU_CIDR2 (0x00BC5FF8) +#define DBG_CTITGU_CIDR2___RWC QCSR_REG_RO +#define DBG_CTITGU_CIDR2___POR 0x00000005 +#define DBG_CTITGU_CIDR2__PRMBL_2___POR 0x05 +#define DBG_CTITGU_CIDR2__PRMBL_2___M 0x000000FF +#define DBG_CTITGU_CIDR2__PRMBL_2___S 0 +#define DBG_CTITGU_CIDR2__PRMBL_2__ID_VALUE_05 0x05 +#define DBG_CTITGU_CIDR2___M 0x000000FF +#define DBG_CTITGU_CIDR2___S 0 + +#define DBG_CTITGU_CIDR3 (0x00BC5FFC) +#define DBG_CTITGU_CIDR3___RWC QCSR_REG_RO +#define DBG_CTITGU_CIDR3___POR 0x000000B1 +#define DBG_CTITGU_CIDR3__PRMBL_3___POR 0xB1 +#define DBG_CTITGU_CIDR3__PRMBL_3___M 0x000000FF +#define DBG_CTITGU_CIDR3__PRMBL_3___S 0 +#define DBG_CTITGU_CIDR3__PRMBL_3__ID_VALUE_B1 0xB1 +#define DBG_CTITGU_CIDR3___M 0x000000FF +#define DBG_CTITGU_CIDR3___S 0 + +#define DBG_PHYADMUX_ATID_EN0 (0x00BC6000) +#define DBG_PHYADMUX_ATID_EN0___RWC QCSR_REG_RW +#define DBG_PHYADMUX_ATID_EN0___POR 0xFFFFFFFF +#define DBG_PHYADMUX_ATID_EN0__ATID31_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID30_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID29_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID28_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID27_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID26_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID25_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID24_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID23_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID22_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID21_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID20_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID19_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID18_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID17_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID16_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID15_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID14_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID13_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID12_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID11_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID10_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID9_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID8_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID7_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID6_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID5_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID4_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID3_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID2_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID1_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID0_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID31_EN___M 0x80000000 +#define DBG_PHYADMUX_ATID_EN0__ATID31_EN___S 31 +#define DBG_PHYADMUX_ATID_EN0__ATID31_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN0__ATID31_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID30_EN___M 0x40000000 +#define DBG_PHYADMUX_ATID_EN0__ATID30_EN___S 30 +#define DBG_PHYADMUX_ATID_EN0__ATID30_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN0__ATID30_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID29_EN___M 0x20000000 +#define DBG_PHYADMUX_ATID_EN0__ATID29_EN___S 29 +#define DBG_PHYADMUX_ATID_EN0__ATID29_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN0__ATID29_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID28_EN___M 0x10000000 +#define DBG_PHYADMUX_ATID_EN0__ATID28_EN___S 28 +#define DBG_PHYADMUX_ATID_EN0__ATID28_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN0__ATID28_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID27_EN___M 0x08000000 +#define DBG_PHYADMUX_ATID_EN0__ATID27_EN___S 27 +#define DBG_PHYADMUX_ATID_EN0__ATID27_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN0__ATID27_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID26_EN___M 0x04000000 +#define DBG_PHYADMUX_ATID_EN0__ATID26_EN___S 26 +#define DBG_PHYADMUX_ATID_EN0__ATID26_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN0__ATID26_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID25_EN___M 0x02000000 +#define DBG_PHYADMUX_ATID_EN0__ATID25_EN___S 25 +#define DBG_PHYADMUX_ATID_EN0__ATID25_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN0__ATID25_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID24_EN___M 0x01000000 +#define DBG_PHYADMUX_ATID_EN0__ATID24_EN___S 24 +#define DBG_PHYADMUX_ATID_EN0__ATID24_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN0__ATID24_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID23_EN___M 0x00800000 +#define DBG_PHYADMUX_ATID_EN0__ATID23_EN___S 23 +#define DBG_PHYADMUX_ATID_EN0__ATID23_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN0__ATID23_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID22_EN___M 0x00400000 +#define DBG_PHYADMUX_ATID_EN0__ATID22_EN___S 22 +#define DBG_PHYADMUX_ATID_EN0__ATID22_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN0__ATID22_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID21_EN___M 0x00200000 +#define DBG_PHYADMUX_ATID_EN0__ATID21_EN___S 21 +#define DBG_PHYADMUX_ATID_EN0__ATID21_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN0__ATID21_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID20_EN___M 0x00100000 +#define DBG_PHYADMUX_ATID_EN0__ATID20_EN___S 20 +#define DBG_PHYADMUX_ATID_EN0__ATID20_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN0__ATID20_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID19_EN___M 0x00080000 +#define DBG_PHYADMUX_ATID_EN0__ATID19_EN___S 19 +#define DBG_PHYADMUX_ATID_EN0__ATID19_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN0__ATID19_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID18_EN___M 0x00040000 +#define DBG_PHYADMUX_ATID_EN0__ATID18_EN___S 18 +#define DBG_PHYADMUX_ATID_EN0__ATID18_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN0__ATID18_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID17_EN___M 0x00020000 +#define DBG_PHYADMUX_ATID_EN0__ATID17_EN___S 17 +#define DBG_PHYADMUX_ATID_EN0__ATID17_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN0__ATID17_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID16_EN___M 0x00010000 +#define DBG_PHYADMUX_ATID_EN0__ATID16_EN___S 16 +#define DBG_PHYADMUX_ATID_EN0__ATID16_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN0__ATID16_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID15_EN___M 0x00008000 +#define DBG_PHYADMUX_ATID_EN0__ATID15_EN___S 15 +#define DBG_PHYADMUX_ATID_EN0__ATID15_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN0__ATID15_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID14_EN___M 0x00004000 +#define DBG_PHYADMUX_ATID_EN0__ATID14_EN___S 14 +#define DBG_PHYADMUX_ATID_EN0__ATID14_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN0__ATID14_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID13_EN___M 0x00002000 +#define DBG_PHYADMUX_ATID_EN0__ATID13_EN___S 13 +#define DBG_PHYADMUX_ATID_EN0__ATID13_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN0__ATID13_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID12_EN___M 0x00001000 +#define DBG_PHYADMUX_ATID_EN0__ATID12_EN___S 12 +#define DBG_PHYADMUX_ATID_EN0__ATID12_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN0__ATID12_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID11_EN___M 0x00000800 +#define DBG_PHYADMUX_ATID_EN0__ATID11_EN___S 11 +#define DBG_PHYADMUX_ATID_EN0__ATID11_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN0__ATID11_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID10_EN___M 0x00000400 +#define DBG_PHYADMUX_ATID_EN0__ATID10_EN___S 10 +#define DBG_PHYADMUX_ATID_EN0__ATID10_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN0__ATID10_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID9_EN___M 0x00000200 +#define DBG_PHYADMUX_ATID_EN0__ATID9_EN___S 9 +#define DBG_PHYADMUX_ATID_EN0__ATID9_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN0__ATID9_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID8_EN___M 0x00000100 +#define DBG_PHYADMUX_ATID_EN0__ATID8_EN___S 8 +#define DBG_PHYADMUX_ATID_EN0__ATID8_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN0__ATID8_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID7_EN___M 0x00000080 +#define DBG_PHYADMUX_ATID_EN0__ATID7_EN___S 7 +#define DBG_PHYADMUX_ATID_EN0__ATID7_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN0__ATID7_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID6_EN___M 0x00000040 +#define DBG_PHYADMUX_ATID_EN0__ATID6_EN___S 6 +#define DBG_PHYADMUX_ATID_EN0__ATID6_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN0__ATID6_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID5_EN___M 0x00000020 +#define DBG_PHYADMUX_ATID_EN0__ATID5_EN___S 5 +#define DBG_PHYADMUX_ATID_EN0__ATID5_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN0__ATID5_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID4_EN___M 0x00000010 +#define DBG_PHYADMUX_ATID_EN0__ATID4_EN___S 4 +#define DBG_PHYADMUX_ATID_EN0__ATID4_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN0__ATID4_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID3_EN___M 0x00000008 +#define DBG_PHYADMUX_ATID_EN0__ATID3_EN___S 3 +#define DBG_PHYADMUX_ATID_EN0__ATID3_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN0__ATID3_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID2_EN___M 0x00000004 +#define DBG_PHYADMUX_ATID_EN0__ATID2_EN___S 2 +#define DBG_PHYADMUX_ATID_EN0__ATID2_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN0__ATID2_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID1_EN___M 0x00000002 +#define DBG_PHYADMUX_ATID_EN0__ATID1_EN___S 1 +#define DBG_PHYADMUX_ATID_EN0__ATID1_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN0__ATID1_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN0__ATID0_EN___M 0x00000001 +#define DBG_PHYADMUX_ATID_EN0__ATID0_EN___S 0 +#define DBG_PHYADMUX_ATID_EN0__ATID0_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN0__ATID0_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN0___M 0xFFFFFFFF +#define DBG_PHYADMUX_ATID_EN0___S 0 + +#define DBG_PHYADMUX_ATID_EN1 (0x00BC6004) +#define DBG_PHYADMUX_ATID_EN1___RWC QCSR_REG_RW +#define DBG_PHYADMUX_ATID_EN1___POR 0xFFFFFFFF +#define DBG_PHYADMUX_ATID_EN1__ATID63_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID62_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID61_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID60_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID59_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID58_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID57_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID56_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID55_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID54_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID53_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID52_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID51_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID50_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID49_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID48_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID47_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID46_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID45_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID44_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID43_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID42_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID41_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID40_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID39_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID38_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID37_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID36_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID35_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID34_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID33_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID32_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID63_EN___M 0x80000000 +#define DBG_PHYADMUX_ATID_EN1__ATID63_EN___S 31 +#define DBG_PHYADMUX_ATID_EN1__ATID63_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN1__ATID63_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID62_EN___M 0x40000000 +#define DBG_PHYADMUX_ATID_EN1__ATID62_EN___S 30 +#define DBG_PHYADMUX_ATID_EN1__ATID62_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN1__ATID62_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID61_EN___M 0x20000000 +#define DBG_PHYADMUX_ATID_EN1__ATID61_EN___S 29 +#define DBG_PHYADMUX_ATID_EN1__ATID61_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN1__ATID61_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID60_EN___M 0x10000000 +#define DBG_PHYADMUX_ATID_EN1__ATID60_EN___S 28 +#define DBG_PHYADMUX_ATID_EN1__ATID60_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN1__ATID60_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID59_EN___M 0x08000000 +#define DBG_PHYADMUX_ATID_EN1__ATID59_EN___S 27 +#define DBG_PHYADMUX_ATID_EN1__ATID59_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN1__ATID59_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID58_EN___M 0x04000000 +#define DBG_PHYADMUX_ATID_EN1__ATID58_EN___S 26 +#define DBG_PHYADMUX_ATID_EN1__ATID58_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN1__ATID58_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID57_EN___M 0x02000000 +#define DBG_PHYADMUX_ATID_EN1__ATID57_EN___S 25 +#define DBG_PHYADMUX_ATID_EN1__ATID57_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN1__ATID57_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID56_EN___M 0x01000000 +#define DBG_PHYADMUX_ATID_EN1__ATID56_EN___S 24 +#define DBG_PHYADMUX_ATID_EN1__ATID56_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN1__ATID56_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID55_EN___M 0x00800000 +#define DBG_PHYADMUX_ATID_EN1__ATID55_EN___S 23 +#define DBG_PHYADMUX_ATID_EN1__ATID55_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN1__ATID55_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID54_EN___M 0x00400000 +#define DBG_PHYADMUX_ATID_EN1__ATID54_EN___S 22 +#define DBG_PHYADMUX_ATID_EN1__ATID54_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN1__ATID54_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID53_EN___M 0x00200000 +#define DBG_PHYADMUX_ATID_EN1__ATID53_EN___S 21 +#define DBG_PHYADMUX_ATID_EN1__ATID53_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN1__ATID53_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID52_EN___M 0x00100000 +#define DBG_PHYADMUX_ATID_EN1__ATID52_EN___S 20 +#define DBG_PHYADMUX_ATID_EN1__ATID52_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN1__ATID52_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID51_EN___M 0x00080000 +#define DBG_PHYADMUX_ATID_EN1__ATID51_EN___S 19 +#define DBG_PHYADMUX_ATID_EN1__ATID51_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN1__ATID51_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID50_EN___M 0x00040000 +#define DBG_PHYADMUX_ATID_EN1__ATID50_EN___S 18 +#define DBG_PHYADMUX_ATID_EN1__ATID50_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN1__ATID50_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID49_EN___M 0x00020000 +#define DBG_PHYADMUX_ATID_EN1__ATID49_EN___S 17 +#define DBG_PHYADMUX_ATID_EN1__ATID49_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN1__ATID49_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID48_EN___M 0x00010000 +#define DBG_PHYADMUX_ATID_EN1__ATID48_EN___S 16 +#define DBG_PHYADMUX_ATID_EN1__ATID48_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN1__ATID48_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID47_EN___M 0x00008000 +#define DBG_PHYADMUX_ATID_EN1__ATID47_EN___S 15 +#define DBG_PHYADMUX_ATID_EN1__ATID47_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN1__ATID47_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID46_EN___M 0x00004000 +#define DBG_PHYADMUX_ATID_EN1__ATID46_EN___S 14 +#define DBG_PHYADMUX_ATID_EN1__ATID46_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN1__ATID46_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID45_EN___M 0x00002000 +#define DBG_PHYADMUX_ATID_EN1__ATID45_EN___S 13 +#define DBG_PHYADMUX_ATID_EN1__ATID45_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN1__ATID45_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID44_EN___M 0x00001000 +#define DBG_PHYADMUX_ATID_EN1__ATID44_EN___S 12 +#define DBG_PHYADMUX_ATID_EN1__ATID44_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN1__ATID44_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID43_EN___M 0x00000800 +#define DBG_PHYADMUX_ATID_EN1__ATID43_EN___S 11 +#define DBG_PHYADMUX_ATID_EN1__ATID43_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN1__ATID43_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID42_EN___M 0x00000400 +#define DBG_PHYADMUX_ATID_EN1__ATID42_EN___S 10 +#define DBG_PHYADMUX_ATID_EN1__ATID42_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN1__ATID42_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID41_EN___M 0x00000200 +#define DBG_PHYADMUX_ATID_EN1__ATID41_EN___S 9 +#define DBG_PHYADMUX_ATID_EN1__ATID41_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN1__ATID41_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID40_EN___M 0x00000100 +#define DBG_PHYADMUX_ATID_EN1__ATID40_EN___S 8 +#define DBG_PHYADMUX_ATID_EN1__ATID40_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN1__ATID40_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID39_EN___M 0x00000080 +#define DBG_PHYADMUX_ATID_EN1__ATID39_EN___S 7 +#define DBG_PHYADMUX_ATID_EN1__ATID39_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN1__ATID39_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID38_EN___M 0x00000040 +#define DBG_PHYADMUX_ATID_EN1__ATID38_EN___S 6 +#define DBG_PHYADMUX_ATID_EN1__ATID38_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN1__ATID38_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID37_EN___M 0x00000020 +#define DBG_PHYADMUX_ATID_EN1__ATID37_EN___S 5 +#define DBG_PHYADMUX_ATID_EN1__ATID37_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN1__ATID37_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID36_EN___M 0x00000010 +#define DBG_PHYADMUX_ATID_EN1__ATID36_EN___S 4 +#define DBG_PHYADMUX_ATID_EN1__ATID36_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN1__ATID36_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID35_EN___M 0x00000008 +#define DBG_PHYADMUX_ATID_EN1__ATID35_EN___S 3 +#define DBG_PHYADMUX_ATID_EN1__ATID35_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN1__ATID35_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID34_EN___M 0x00000004 +#define DBG_PHYADMUX_ATID_EN1__ATID34_EN___S 2 +#define DBG_PHYADMUX_ATID_EN1__ATID34_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN1__ATID34_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID33_EN___M 0x00000002 +#define DBG_PHYADMUX_ATID_EN1__ATID33_EN___S 1 +#define DBG_PHYADMUX_ATID_EN1__ATID33_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN1__ATID33_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN1__ATID32_EN___M 0x00000001 +#define DBG_PHYADMUX_ATID_EN1__ATID32_EN___S 0 +#define DBG_PHYADMUX_ATID_EN1__ATID32_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN1__ATID32_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN1___M 0xFFFFFFFF +#define DBG_PHYADMUX_ATID_EN1___S 0 + +#define DBG_PHYADMUX_ATID_EN2 (0x00BC6008) +#define DBG_PHYADMUX_ATID_EN2___RWC QCSR_REG_RW +#define DBG_PHYADMUX_ATID_EN2___POR 0xFFFFFFFF +#define DBG_PHYADMUX_ATID_EN2__ATID95_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID94_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID93_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID92_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID91_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID90_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID89_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID88_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID87_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID86_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID85_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID84_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID83_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID82_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID81_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID80_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID79_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID78_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID77_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID76_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID75_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID74_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID73_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID72_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID71_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID70_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID69_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID68_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID67_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID66_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID65_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID64_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID95_EN___M 0x80000000 +#define DBG_PHYADMUX_ATID_EN2__ATID95_EN___S 31 +#define DBG_PHYADMUX_ATID_EN2__ATID95_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN2__ATID95_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID94_EN___M 0x40000000 +#define DBG_PHYADMUX_ATID_EN2__ATID94_EN___S 30 +#define DBG_PHYADMUX_ATID_EN2__ATID94_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN2__ATID94_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID93_EN___M 0x20000000 +#define DBG_PHYADMUX_ATID_EN2__ATID93_EN___S 29 +#define DBG_PHYADMUX_ATID_EN2__ATID93_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN2__ATID93_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID92_EN___M 0x10000000 +#define DBG_PHYADMUX_ATID_EN2__ATID92_EN___S 28 +#define DBG_PHYADMUX_ATID_EN2__ATID92_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN2__ATID92_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID91_EN___M 0x08000000 +#define DBG_PHYADMUX_ATID_EN2__ATID91_EN___S 27 +#define DBG_PHYADMUX_ATID_EN2__ATID91_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN2__ATID91_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID90_EN___M 0x04000000 +#define DBG_PHYADMUX_ATID_EN2__ATID90_EN___S 26 +#define DBG_PHYADMUX_ATID_EN2__ATID90_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN2__ATID90_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID89_EN___M 0x02000000 +#define DBG_PHYADMUX_ATID_EN2__ATID89_EN___S 25 +#define DBG_PHYADMUX_ATID_EN2__ATID89_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN2__ATID89_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID88_EN___M 0x01000000 +#define DBG_PHYADMUX_ATID_EN2__ATID88_EN___S 24 +#define DBG_PHYADMUX_ATID_EN2__ATID88_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN2__ATID88_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID87_EN___M 0x00800000 +#define DBG_PHYADMUX_ATID_EN2__ATID87_EN___S 23 +#define DBG_PHYADMUX_ATID_EN2__ATID87_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN2__ATID87_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID86_EN___M 0x00400000 +#define DBG_PHYADMUX_ATID_EN2__ATID86_EN___S 22 +#define DBG_PHYADMUX_ATID_EN2__ATID86_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN2__ATID86_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID85_EN___M 0x00200000 +#define DBG_PHYADMUX_ATID_EN2__ATID85_EN___S 21 +#define DBG_PHYADMUX_ATID_EN2__ATID85_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN2__ATID85_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID84_EN___M 0x00100000 +#define DBG_PHYADMUX_ATID_EN2__ATID84_EN___S 20 +#define DBG_PHYADMUX_ATID_EN2__ATID84_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN2__ATID84_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID83_EN___M 0x00080000 +#define DBG_PHYADMUX_ATID_EN2__ATID83_EN___S 19 +#define DBG_PHYADMUX_ATID_EN2__ATID83_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN2__ATID83_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID82_EN___M 0x00040000 +#define DBG_PHYADMUX_ATID_EN2__ATID82_EN___S 18 +#define DBG_PHYADMUX_ATID_EN2__ATID82_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN2__ATID82_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID81_EN___M 0x00020000 +#define DBG_PHYADMUX_ATID_EN2__ATID81_EN___S 17 +#define DBG_PHYADMUX_ATID_EN2__ATID81_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN2__ATID81_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID80_EN___M 0x00010000 +#define DBG_PHYADMUX_ATID_EN2__ATID80_EN___S 16 +#define DBG_PHYADMUX_ATID_EN2__ATID80_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN2__ATID80_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID79_EN___M 0x00008000 +#define DBG_PHYADMUX_ATID_EN2__ATID79_EN___S 15 +#define DBG_PHYADMUX_ATID_EN2__ATID79_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN2__ATID79_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID78_EN___M 0x00004000 +#define DBG_PHYADMUX_ATID_EN2__ATID78_EN___S 14 +#define DBG_PHYADMUX_ATID_EN2__ATID78_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN2__ATID78_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID77_EN___M 0x00002000 +#define DBG_PHYADMUX_ATID_EN2__ATID77_EN___S 13 +#define DBG_PHYADMUX_ATID_EN2__ATID77_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN2__ATID77_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID76_EN___M 0x00001000 +#define DBG_PHYADMUX_ATID_EN2__ATID76_EN___S 12 +#define DBG_PHYADMUX_ATID_EN2__ATID76_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN2__ATID76_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID75_EN___M 0x00000800 +#define DBG_PHYADMUX_ATID_EN2__ATID75_EN___S 11 +#define DBG_PHYADMUX_ATID_EN2__ATID75_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN2__ATID75_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID74_EN___M 0x00000400 +#define DBG_PHYADMUX_ATID_EN2__ATID74_EN___S 10 +#define DBG_PHYADMUX_ATID_EN2__ATID74_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN2__ATID74_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID73_EN___M 0x00000200 +#define DBG_PHYADMUX_ATID_EN2__ATID73_EN___S 9 +#define DBG_PHYADMUX_ATID_EN2__ATID73_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN2__ATID73_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID72_EN___M 0x00000100 +#define DBG_PHYADMUX_ATID_EN2__ATID72_EN___S 8 +#define DBG_PHYADMUX_ATID_EN2__ATID72_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN2__ATID72_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID71_EN___M 0x00000080 +#define DBG_PHYADMUX_ATID_EN2__ATID71_EN___S 7 +#define DBG_PHYADMUX_ATID_EN2__ATID71_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN2__ATID71_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID70_EN___M 0x00000040 +#define DBG_PHYADMUX_ATID_EN2__ATID70_EN___S 6 +#define DBG_PHYADMUX_ATID_EN2__ATID70_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN2__ATID70_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID69_EN___M 0x00000020 +#define DBG_PHYADMUX_ATID_EN2__ATID69_EN___S 5 +#define DBG_PHYADMUX_ATID_EN2__ATID69_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN2__ATID69_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID68_EN___M 0x00000010 +#define DBG_PHYADMUX_ATID_EN2__ATID68_EN___S 4 +#define DBG_PHYADMUX_ATID_EN2__ATID68_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN2__ATID68_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID67_EN___M 0x00000008 +#define DBG_PHYADMUX_ATID_EN2__ATID67_EN___S 3 +#define DBG_PHYADMUX_ATID_EN2__ATID67_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN2__ATID67_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID66_EN___M 0x00000004 +#define DBG_PHYADMUX_ATID_EN2__ATID66_EN___S 2 +#define DBG_PHYADMUX_ATID_EN2__ATID66_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN2__ATID66_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID65_EN___M 0x00000002 +#define DBG_PHYADMUX_ATID_EN2__ATID65_EN___S 1 +#define DBG_PHYADMUX_ATID_EN2__ATID65_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN2__ATID65_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN2__ATID64_EN___M 0x00000001 +#define DBG_PHYADMUX_ATID_EN2__ATID64_EN___S 0 +#define DBG_PHYADMUX_ATID_EN2__ATID64_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN2__ATID64_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN2___M 0xFFFFFFFF +#define DBG_PHYADMUX_ATID_EN2___S 0 + +#define DBG_PHYADMUX_ATID_EN3 (0x00BC600C) +#define DBG_PHYADMUX_ATID_EN3___RWC QCSR_REG_RW +#define DBG_PHYADMUX_ATID_EN3___POR 0xFFFFFFFF +#define DBG_PHYADMUX_ATID_EN3__ATID127_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID126_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID125_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID124_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID123_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID122_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID121_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID120_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID119_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID118_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID117_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID116_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID115_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID114_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID113_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID112_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID111_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID110_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID109_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID108_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID107_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID106_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID105_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID104_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID103_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID102_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID101_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID100_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID99_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID98_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID97_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID96_EN___POR 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID127_EN___M 0x80000000 +#define DBG_PHYADMUX_ATID_EN3__ATID127_EN___S 31 +#define DBG_PHYADMUX_ATID_EN3__ATID127_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN3__ATID127_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID126_EN___M 0x40000000 +#define DBG_PHYADMUX_ATID_EN3__ATID126_EN___S 30 +#define DBG_PHYADMUX_ATID_EN3__ATID126_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN3__ATID126_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID125_EN___M 0x20000000 +#define DBG_PHYADMUX_ATID_EN3__ATID125_EN___S 29 +#define DBG_PHYADMUX_ATID_EN3__ATID125_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN3__ATID125_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID124_EN___M 0x10000000 +#define DBG_PHYADMUX_ATID_EN3__ATID124_EN___S 28 +#define DBG_PHYADMUX_ATID_EN3__ATID124_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN3__ATID124_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID123_EN___M 0x08000000 +#define DBG_PHYADMUX_ATID_EN3__ATID123_EN___S 27 +#define DBG_PHYADMUX_ATID_EN3__ATID123_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN3__ATID123_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID122_EN___M 0x04000000 +#define DBG_PHYADMUX_ATID_EN3__ATID122_EN___S 26 +#define DBG_PHYADMUX_ATID_EN3__ATID122_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN3__ATID122_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID121_EN___M 0x02000000 +#define DBG_PHYADMUX_ATID_EN3__ATID121_EN___S 25 +#define DBG_PHYADMUX_ATID_EN3__ATID121_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN3__ATID121_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID120_EN___M 0x01000000 +#define DBG_PHYADMUX_ATID_EN3__ATID120_EN___S 24 +#define DBG_PHYADMUX_ATID_EN3__ATID120_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN3__ATID120_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID119_EN___M 0x00800000 +#define DBG_PHYADMUX_ATID_EN3__ATID119_EN___S 23 +#define DBG_PHYADMUX_ATID_EN3__ATID119_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN3__ATID119_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID118_EN___M 0x00400000 +#define DBG_PHYADMUX_ATID_EN3__ATID118_EN___S 22 +#define DBG_PHYADMUX_ATID_EN3__ATID118_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN3__ATID118_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID117_EN___M 0x00200000 +#define DBG_PHYADMUX_ATID_EN3__ATID117_EN___S 21 +#define DBG_PHYADMUX_ATID_EN3__ATID117_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN3__ATID117_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID116_EN___M 0x00100000 +#define DBG_PHYADMUX_ATID_EN3__ATID116_EN___S 20 +#define DBG_PHYADMUX_ATID_EN3__ATID116_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN3__ATID116_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID115_EN___M 0x00080000 +#define DBG_PHYADMUX_ATID_EN3__ATID115_EN___S 19 +#define DBG_PHYADMUX_ATID_EN3__ATID115_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN3__ATID115_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID114_EN___M 0x00040000 +#define DBG_PHYADMUX_ATID_EN3__ATID114_EN___S 18 +#define DBG_PHYADMUX_ATID_EN3__ATID114_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN3__ATID114_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID113_EN___M 0x00020000 +#define DBG_PHYADMUX_ATID_EN3__ATID113_EN___S 17 +#define DBG_PHYADMUX_ATID_EN3__ATID113_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN3__ATID113_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID112_EN___M 0x00010000 +#define DBG_PHYADMUX_ATID_EN3__ATID112_EN___S 16 +#define DBG_PHYADMUX_ATID_EN3__ATID112_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN3__ATID112_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID111_EN___M 0x00008000 +#define DBG_PHYADMUX_ATID_EN3__ATID111_EN___S 15 +#define DBG_PHYADMUX_ATID_EN3__ATID111_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN3__ATID111_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID110_EN___M 0x00004000 +#define DBG_PHYADMUX_ATID_EN3__ATID110_EN___S 14 +#define DBG_PHYADMUX_ATID_EN3__ATID110_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN3__ATID110_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID109_EN___M 0x00002000 +#define DBG_PHYADMUX_ATID_EN3__ATID109_EN___S 13 +#define DBG_PHYADMUX_ATID_EN3__ATID109_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN3__ATID109_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID108_EN___M 0x00001000 +#define DBG_PHYADMUX_ATID_EN3__ATID108_EN___S 12 +#define DBG_PHYADMUX_ATID_EN3__ATID108_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN3__ATID108_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID107_EN___M 0x00000800 +#define DBG_PHYADMUX_ATID_EN3__ATID107_EN___S 11 +#define DBG_PHYADMUX_ATID_EN3__ATID107_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN3__ATID107_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID106_EN___M 0x00000400 +#define DBG_PHYADMUX_ATID_EN3__ATID106_EN___S 10 +#define DBG_PHYADMUX_ATID_EN3__ATID106_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN3__ATID106_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID105_EN___M 0x00000200 +#define DBG_PHYADMUX_ATID_EN3__ATID105_EN___S 9 +#define DBG_PHYADMUX_ATID_EN3__ATID105_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN3__ATID105_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID104_EN___M 0x00000100 +#define DBG_PHYADMUX_ATID_EN3__ATID104_EN___S 8 +#define DBG_PHYADMUX_ATID_EN3__ATID104_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN3__ATID104_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID103_EN___M 0x00000080 +#define DBG_PHYADMUX_ATID_EN3__ATID103_EN___S 7 +#define DBG_PHYADMUX_ATID_EN3__ATID103_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN3__ATID103_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID102_EN___M 0x00000040 +#define DBG_PHYADMUX_ATID_EN3__ATID102_EN___S 6 +#define DBG_PHYADMUX_ATID_EN3__ATID102_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN3__ATID102_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID101_EN___M 0x00000020 +#define DBG_PHYADMUX_ATID_EN3__ATID101_EN___S 5 +#define DBG_PHYADMUX_ATID_EN3__ATID101_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN3__ATID101_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID100_EN___M 0x00000010 +#define DBG_PHYADMUX_ATID_EN3__ATID100_EN___S 4 +#define DBG_PHYADMUX_ATID_EN3__ATID100_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN3__ATID100_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID99_EN___M 0x00000008 +#define DBG_PHYADMUX_ATID_EN3__ATID99_EN___S 3 +#define DBG_PHYADMUX_ATID_EN3__ATID99_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN3__ATID99_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID98_EN___M 0x00000004 +#define DBG_PHYADMUX_ATID_EN3__ATID98_EN___S 2 +#define DBG_PHYADMUX_ATID_EN3__ATID98_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN3__ATID98_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID97_EN___M 0x00000002 +#define DBG_PHYADMUX_ATID_EN3__ATID97_EN___S 1 +#define DBG_PHYADMUX_ATID_EN3__ATID97_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN3__ATID97_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN3__ATID96_EN___M 0x00000001 +#define DBG_PHYADMUX_ATID_EN3__ATID96_EN___S 0 +#define DBG_PHYADMUX_ATID_EN3__ATID96_EN__DISABLE 0x0 +#define DBG_PHYADMUX_ATID_EN3__ATID96_EN__ENABLE 0x1 +#define DBG_PHYADMUX_ATID_EN3___M 0xFFFFFFFF +#define DBG_PHYADMUX_ATID_EN3___S 0 + +#define DBG_PHYADMUX_ATID_SEL0 (0x00BC6010) +#define DBG_PHYADMUX_ATID_SEL0___RWC QCSR_REG_RW +#define DBG_PHYADMUX_ATID_SEL0___POR 0x00000000 +#define DBG_PHYADMUX_ATID_SEL0__ATID31_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID30_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID29_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID28_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID27_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID26_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID25_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID24_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID23_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID22_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID21_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID20_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID19_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID18_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID17_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID16_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID15_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID14_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID13_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID12_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID11_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID10_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID9_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID8_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID7_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID6_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID5_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID4_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID3_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID2_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID1_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID0_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID31_SEL___M 0x80000000 +#define DBG_PHYADMUX_ATID_SEL0__ATID31_SEL___S 31 +#define DBG_PHYADMUX_ATID_SEL0__ATID31_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID31_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL0__ATID30_SEL___M 0x40000000 +#define DBG_PHYADMUX_ATID_SEL0__ATID30_SEL___S 30 +#define DBG_PHYADMUX_ATID_SEL0__ATID30_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID30_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL0__ATID29_SEL___M 0x20000000 +#define DBG_PHYADMUX_ATID_SEL0__ATID29_SEL___S 29 +#define DBG_PHYADMUX_ATID_SEL0__ATID29_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID29_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL0__ATID28_SEL___M 0x10000000 +#define DBG_PHYADMUX_ATID_SEL0__ATID28_SEL___S 28 +#define DBG_PHYADMUX_ATID_SEL0__ATID28_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID28_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL0__ATID27_SEL___M 0x08000000 +#define DBG_PHYADMUX_ATID_SEL0__ATID27_SEL___S 27 +#define DBG_PHYADMUX_ATID_SEL0__ATID27_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID27_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL0__ATID26_SEL___M 0x04000000 +#define DBG_PHYADMUX_ATID_SEL0__ATID26_SEL___S 26 +#define DBG_PHYADMUX_ATID_SEL0__ATID26_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID26_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL0__ATID25_SEL___M 0x02000000 +#define DBG_PHYADMUX_ATID_SEL0__ATID25_SEL___S 25 +#define DBG_PHYADMUX_ATID_SEL0__ATID25_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID25_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL0__ATID24_SEL___M 0x01000000 +#define DBG_PHYADMUX_ATID_SEL0__ATID24_SEL___S 24 +#define DBG_PHYADMUX_ATID_SEL0__ATID24_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID24_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL0__ATID23_SEL___M 0x00800000 +#define DBG_PHYADMUX_ATID_SEL0__ATID23_SEL___S 23 +#define DBG_PHYADMUX_ATID_SEL0__ATID23_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID23_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL0__ATID22_SEL___M 0x00400000 +#define DBG_PHYADMUX_ATID_SEL0__ATID22_SEL___S 22 +#define DBG_PHYADMUX_ATID_SEL0__ATID22_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID22_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL0__ATID21_SEL___M 0x00200000 +#define DBG_PHYADMUX_ATID_SEL0__ATID21_SEL___S 21 +#define DBG_PHYADMUX_ATID_SEL0__ATID21_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID21_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL0__ATID20_SEL___M 0x00100000 +#define DBG_PHYADMUX_ATID_SEL0__ATID20_SEL___S 20 +#define DBG_PHYADMUX_ATID_SEL0__ATID20_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID20_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL0__ATID19_SEL___M 0x00080000 +#define DBG_PHYADMUX_ATID_SEL0__ATID19_SEL___S 19 +#define DBG_PHYADMUX_ATID_SEL0__ATID19_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID19_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL0__ATID18_SEL___M 0x00040000 +#define DBG_PHYADMUX_ATID_SEL0__ATID18_SEL___S 18 +#define DBG_PHYADMUX_ATID_SEL0__ATID18_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID18_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL0__ATID17_SEL___M 0x00020000 +#define DBG_PHYADMUX_ATID_SEL0__ATID17_SEL___S 17 +#define DBG_PHYADMUX_ATID_SEL0__ATID17_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID17_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL0__ATID16_SEL___M 0x00010000 +#define DBG_PHYADMUX_ATID_SEL0__ATID16_SEL___S 16 +#define DBG_PHYADMUX_ATID_SEL0__ATID16_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID16_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL0__ATID15_SEL___M 0x00008000 +#define DBG_PHYADMUX_ATID_SEL0__ATID15_SEL___S 15 +#define DBG_PHYADMUX_ATID_SEL0__ATID15_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID15_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL0__ATID14_SEL___M 0x00004000 +#define DBG_PHYADMUX_ATID_SEL0__ATID14_SEL___S 14 +#define DBG_PHYADMUX_ATID_SEL0__ATID14_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID14_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL0__ATID13_SEL___M 0x00002000 +#define DBG_PHYADMUX_ATID_SEL0__ATID13_SEL___S 13 +#define DBG_PHYADMUX_ATID_SEL0__ATID13_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID13_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL0__ATID12_SEL___M 0x00001000 +#define DBG_PHYADMUX_ATID_SEL0__ATID12_SEL___S 12 +#define DBG_PHYADMUX_ATID_SEL0__ATID12_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID12_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL0__ATID11_SEL___M 0x00000800 +#define DBG_PHYADMUX_ATID_SEL0__ATID11_SEL___S 11 +#define DBG_PHYADMUX_ATID_SEL0__ATID11_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID11_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL0__ATID10_SEL___M 0x00000400 +#define DBG_PHYADMUX_ATID_SEL0__ATID10_SEL___S 10 +#define DBG_PHYADMUX_ATID_SEL0__ATID10_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID10_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL0__ATID9_SEL___M 0x00000200 +#define DBG_PHYADMUX_ATID_SEL0__ATID9_SEL___S 9 +#define DBG_PHYADMUX_ATID_SEL0__ATID9_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID9_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL0__ATID8_SEL___M 0x00000100 +#define DBG_PHYADMUX_ATID_SEL0__ATID8_SEL___S 8 +#define DBG_PHYADMUX_ATID_SEL0__ATID8_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID8_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL0__ATID7_SEL___M 0x00000080 +#define DBG_PHYADMUX_ATID_SEL0__ATID7_SEL___S 7 +#define DBG_PHYADMUX_ATID_SEL0__ATID7_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID7_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL0__ATID6_SEL___M 0x00000040 +#define DBG_PHYADMUX_ATID_SEL0__ATID6_SEL___S 6 +#define DBG_PHYADMUX_ATID_SEL0__ATID6_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID6_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL0__ATID5_SEL___M 0x00000020 +#define DBG_PHYADMUX_ATID_SEL0__ATID5_SEL___S 5 +#define DBG_PHYADMUX_ATID_SEL0__ATID5_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID5_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL0__ATID4_SEL___M 0x00000010 +#define DBG_PHYADMUX_ATID_SEL0__ATID4_SEL___S 4 +#define DBG_PHYADMUX_ATID_SEL0__ATID4_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID4_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL0__ATID3_SEL___M 0x00000008 +#define DBG_PHYADMUX_ATID_SEL0__ATID3_SEL___S 3 +#define DBG_PHYADMUX_ATID_SEL0__ATID3_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID3_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL0__ATID2_SEL___M 0x00000004 +#define DBG_PHYADMUX_ATID_SEL0__ATID2_SEL___S 2 +#define DBG_PHYADMUX_ATID_SEL0__ATID2_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID2_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL0__ATID1_SEL___M 0x00000002 +#define DBG_PHYADMUX_ATID_SEL0__ATID1_SEL___S 1 +#define DBG_PHYADMUX_ATID_SEL0__ATID1_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID1_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL0__ATID0_SEL___M 0x00000001 +#define DBG_PHYADMUX_ATID_SEL0__ATID0_SEL___S 0 +#define DBG_PHYADMUX_ATID_SEL0__ATID0_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL0__ATID0_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL0___M 0xFFFFFFFF +#define DBG_PHYADMUX_ATID_SEL0___S 0 + +#define DBG_PHYADMUX_ATID_SEL1 (0x00BC6014) +#define DBG_PHYADMUX_ATID_SEL1___RWC QCSR_REG_RW +#define DBG_PHYADMUX_ATID_SEL1___POR 0x00000000 +#define DBG_PHYADMUX_ATID_SEL1__ATID63_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID62_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID61_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID60_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID59_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID58_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID57_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID56_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID55_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID54_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID53_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID52_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID51_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID50_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID49_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID48_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID47_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID46_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID45_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID44_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID43_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID42_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID41_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID40_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID39_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID38_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID37_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID36_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID35_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID34_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID33_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID32_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID63_SEL___M 0x80000000 +#define DBG_PHYADMUX_ATID_SEL1__ATID63_SEL___S 31 +#define DBG_PHYADMUX_ATID_SEL1__ATID63_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID63_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL1__ATID62_SEL___M 0x40000000 +#define DBG_PHYADMUX_ATID_SEL1__ATID62_SEL___S 30 +#define DBG_PHYADMUX_ATID_SEL1__ATID62_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID62_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL1__ATID61_SEL___M 0x20000000 +#define DBG_PHYADMUX_ATID_SEL1__ATID61_SEL___S 29 +#define DBG_PHYADMUX_ATID_SEL1__ATID61_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID61_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL1__ATID60_SEL___M 0x10000000 +#define DBG_PHYADMUX_ATID_SEL1__ATID60_SEL___S 28 +#define DBG_PHYADMUX_ATID_SEL1__ATID60_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID60_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL1__ATID59_SEL___M 0x08000000 +#define DBG_PHYADMUX_ATID_SEL1__ATID59_SEL___S 27 +#define DBG_PHYADMUX_ATID_SEL1__ATID59_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID59_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL1__ATID58_SEL___M 0x04000000 +#define DBG_PHYADMUX_ATID_SEL1__ATID58_SEL___S 26 +#define DBG_PHYADMUX_ATID_SEL1__ATID58_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID58_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL1__ATID57_SEL___M 0x02000000 +#define DBG_PHYADMUX_ATID_SEL1__ATID57_SEL___S 25 +#define DBG_PHYADMUX_ATID_SEL1__ATID57_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID57_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL1__ATID56_SEL___M 0x01000000 +#define DBG_PHYADMUX_ATID_SEL1__ATID56_SEL___S 24 +#define DBG_PHYADMUX_ATID_SEL1__ATID56_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID56_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL1__ATID55_SEL___M 0x00800000 +#define DBG_PHYADMUX_ATID_SEL1__ATID55_SEL___S 23 +#define DBG_PHYADMUX_ATID_SEL1__ATID55_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID55_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL1__ATID54_SEL___M 0x00400000 +#define DBG_PHYADMUX_ATID_SEL1__ATID54_SEL___S 22 +#define DBG_PHYADMUX_ATID_SEL1__ATID54_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID54_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL1__ATID53_SEL___M 0x00200000 +#define DBG_PHYADMUX_ATID_SEL1__ATID53_SEL___S 21 +#define DBG_PHYADMUX_ATID_SEL1__ATID53_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID53_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL1__ATID52_SEL___M 0x00100000 +#define DBG_PHYADMUX_ATID_SEL1__ATID52_SEL___S 20 +#define DBG_PHYADMUX_ATID_SEL1__ATID52_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID52_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL1__ATID51_SEL___M 0x00080000 +#define DBG_PHYADMUX_ATID_SEL1__ATID51_SEL___S 19 +#define DBG_PHYADMUX_ATID_SEL1__ATID51_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID51_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL1__ATID50_SEL___M 0x00040000 +#define DBG_PHYADMUX_ATID_SEL1__ATID50_SEL___S 18 +#define DBG_PHYADMUX_ATID_SEL1__ATID50_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID50_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL1__ATID49_SEL___M 0x00020000 +#define DBG_PHYADMUX_ATID_SEL1__ATID49_SEL___S 17 +#define DBG_PHYADMUX_ATID_SEL1__ATID49_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID49_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL1__ATID48_SEL___M 0x00010000 +#define DBG_PHYADMUX_ATID_SEL1__ATID48_SEL___S 16 +#define DBG_PHYADMUX_ATID_SEL1__ATID48_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID48_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL1__ATID47_SEL___M 0x00008000 +#define DBG_PHYADMUX_ATID_SEL1__ATID47_SEL___S 15 +#define DBG_PHYADMUX_ATID_SEL1__ATID47_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID47_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL1__ATID46_SEL___M 0x00004000 +#define DBG_PHYADMUX_ATID_SEL1__ATID46_SEL___S 14 +#define DBG_PHYADMUX_ATID_SEL1__ATID46_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID46_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL1__ATID45_SEL___M 0x00002000 +#define DBG_PHYADMUX_ATID_SEL1__ATID45_SEL___S 13 +#define DBG_PHYADMUX_ATID_SEL1__ATID45_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID45_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL1__ATID44_SEL___M 0x00001000 +#define DBG_PHYADMUX_ATID_SEL1__ATID44_SEL___S 12 +#define DBG_PHYADMUX_ATID_SEL1__ATID44_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID44_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL1__ATID43_SEL___M 0x00000800 +#define DBG_PHYADMUX_ATID_SEL1__ATID43_SEL___S 11 +#define DBG_PHYADMUX_ATID_SEL1__ATID43_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID43_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL1__ATID42_SEL___M 0x00000400 +#define DBG_PHYADMUX_ATID_SEL1__ATID42_SEL___S 10 +#define DBG_PHYADMUX_ATID_SEL1__ATID42_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID42_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL1__ATID41_SEL___M 0x00000200 +#define DBG_PHYADMUX_ATID_SEL1__ATID41_SEL___S 9 +#define DBG_PHYADMUX_ATID_SEL1__ATID41_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID41_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL1__ATID40_SEL___M 0x00000100 +#define DBG_PHYADMUX_ATID_SEL1__ATID40_SEL___S 8 +#define DBG_PHYADMUX_ATID_SEL1__ATID40_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID40_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL1__ATID39_SEL___M 0x00000080 +#define DBG_PHYADMUX_ATID_SEL1__ATID39_SEL___S 7 +#define DBG_PHYADMUX_ATID_SEL1__ATID39_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID39_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL1__ATID38_SEL___M 0x00000040 +#define DBG_PHYADMUX_ATID_SEL1__ATID38_SEL___S 6 +#define DBG_PHYADMUX_ATID_SEL1__ATID38_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID38_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL1__ATID37_SEL___M 0x00000020 +#define DBG_PHYADMUX_ATID_SEL1__ATID37_SEL___S 5 +#define DBG_PHYADMUX_ATID_SEL1__ATID37_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID37_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL1__ATID36_SEL___M 0x00000010 +#define DBG_PHYADMUX_ATID_SEL1__ATID36_SEL___S 4 +#define DBG_PHYADMUX_ATID_SEL1__ATID36_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID36_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL1__ATID35_SEL___M 0x00000008 +#define DBG_PHYADMUX_ATID_SEL1__ATID35_SEL___S 3 +#define DBG_PHYADMUX_ATID_SEL1__ATID35_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID35_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL1__ATID34_SEL___M 0x00000004 +#define DBG_PHYADMUX_ATID_SEL1__ATID34_SEL___S 2 +#define DBG_PHYADMUX_ATID_SEL1__ATID34_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID34_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL1__ATID33_SEL___M 0x00000002 +#define DBG_PHYADMUX_ATID_SEL1__ATID33_SEL___S 1 +#define DBG_PHYADMUX_ATID_SEL1__ATID33_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID33_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL1__ATID32_SEL___M 0x00000001 +#define DBG_PHYADMUX_ATID_SEL1__ATID32_SEL___S 0 +#define DBG_PHYADMUX_ATID_SEL1__ATID32_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL1__ATID32_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL1___M 0xFFFFFFFF +#define DBG_PHYADMUX_ATID_SEL1___S 0 + +#define DBG_PHYADMUX_ATID_SEL2 (0x00BC6018) +#define DBG_PHYADMUX_ATID_SEL2___RWC QCSR_REG_RW +#define DBG_PHYADMUX_ATID_SEL2___POR 0x00000000 +#define DBG_PHYADMUX_ATID_SEL2__ATID95_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID94_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID93_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID92_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID91_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID90_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID89_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID88_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID87_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID86_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID85_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID84_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID83_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID82_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID81_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID80_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID79_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID78_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID77_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID76_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID75_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID74_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID73_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID72_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID71_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID70_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID69_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID68_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID67_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID66_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID65_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID64_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID95_SEL___M 0x80000000 +#define DBG_PHYADMUX_ATID_SEL2__ATID95_SEL___S 31 +#define DBG_PHYADMUX_ATID_SEL2__ATID95_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID95_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL2__ATID94_SEL___M 0x40000000 +#define DBG_PHYADMUX_ATID_SEL2__ATID94_SEL___S 30 +#define DBG_PHYADMUX_ATID_SEL2__ATID94_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID94_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL2__ATID93_SEL___M 0x20000000 +#define DBG_PHYADMUX_ATID_SEL2__ATID93_SEL___S 29 +#define DBG_PHYADMUX_ATID_SEL2__ATID93_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID93_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL2__ATID92_SEL___M 0x10000000 +#define DBG_PHYADMUX_ATID_SEL2__ATID92_SEL___S 28 +#define DBG_PHYADMUX_ATID_SEL2__ATID92_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID92_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL2__ATID91_SEL___M 0x08000000 +#define DBG_PHYADMUX_ATID_SEL2__ATID91_SEL___S 27 +#define DBG_PHYADMUX_ATID_SEL2__ATID91_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID91_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL2__ATID90_SEL___M 0x04000000 +#define DBG_PHYADMUX_ATID_SEL2__ATID90_SEL___S 26 +#define DBG_PHYADMUX_ATID_SEL2__ATID90_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID90_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL2__ATID89_SEL___M 0x02000000 +#define DBG_PHYADMUX_ATID_SEL2__ATID89_SEL___S 25 +#define DBG_PHYADMUX_ATID_SEL2__ATID89_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID89_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL2__ATID88_SEL___M 0x01000000 +#define DBG_PHYADMUX_ATID_SEL2__ATID88_SEL___S 24 +#define DBG_PHYADMUX_ATID_SEL2__ATID88_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID88_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL2__ATID87_SEL___M 0x00800000 +#define DBG_PHYADMUX_ATID_SEL2__ATID87_SEL___S 23 +#define DBG_PHYADMUX_ATID_SEL2__ATID87_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID87_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL2__ATID86_SEL___M 0x00400000 +#define DBG_PHYADMUX_ATID_SEL2__ATID86_SEL___S 22 +#define DBG_PHYADMUX_ATID_SEL2__ATID86_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID86_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL2__ATID85_SEL___M 0x00200000 +#define DBG_PHYADMUX_ATID_SEL2__ATID85_SEL___S 21 +#define DBG_PHYADMUX_ATID_SEL2__ATID85_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID85_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL2__ATID84_SEL___M 0x00100000 +#define DBG_PHYADMUX_ATID_SEL2__ATID84_SEL___S 20 +#define DBG_PHYADMUX_ATID_SEL2__ATID84_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID84_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL2__ATID83_SEL___M 0x00080000 +#define DBG_PHYADMUX_ATID_SEL2__ATID83_SEL___S 19 +#define DBG_PHYADMUX_ATID_SEL2__ATID83_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID83_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL2__ATID82_SEL___M 0x00040000 +#define DBG_PHYADMUX_ATID_SEL2__ATID82_SEL___S 18 +#define DBG_PHYADMUX_ATID_SEL2__ATID82_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID82_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL2__ATID81_SEL___M 0x00020000 +#define DBG_PHYADMUX_ATID_SEL2__ATID81_SEL___S 17 +#define DBG_PHYADMUX_ATID_SEL2__ATID81_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID81_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL2__ATID80_SEL___M 0x00010000 +#define DBG_PHYADMUX_ATID_SEL2__ATID80_SEL___S 16 +#define DBG_PHYADMUX_ATID_SEL2__ATID80_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID80_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL2__ATID79_SEL___M 0x00008000 +#define DBG_PHYADMUX_ATID_SEL2__ATID79_SEL___S 15 +#define DBG_PHYADMUX_ATID_SEL2__ATID79_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID79_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL2__ATID78_SEL___M 0x00004000 +#define DBG_PHYADMUX_ATID_SEL2__ATID78_SEL___S 14 +#define DBG_PHYADMUX_ATID_SEL2__ATID78_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID78_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL2__ATID77_SEL___M 0x00002000 +#define DBG_PHYADMUX_ATID_SEL2__ATID77_SEL___S 13 +#define DBG_PHYADMUX_ATID_SEL2__ATID77_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID77_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL2__ATID76_SEL___M 0x00001000 +#define DBG_PHYADMUX_ATID_SEL2__ATID76_SEL___S 12 +#define DBG_PHYADMUX_ATID_SEL2__ATID76_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID76_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL2__ATID75_SEL___M 0x00000800 +#define DBG_PHYADMUX_ATID_SEL2__ATID75_SEL___S 11 +#define DBG_PHYADMUX_ATID_SEL2__ATID75_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID75_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL2__ATID74_SEL___M 0x00000400 +#define DBG_PHYADMUX_ATID_SEL2__ATID74_SEL___S 10 +#define DBG_PHYADMUX_ATID_SEL2__ATID74_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID74_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL2__ATID73_SEL___M 0x00000200 +#define DBG_PHYADMUX_ATID_SEL2__ATID73_SEL___S 9 +#define DBG_PHYADMUX_ATID_SEL2__ATID73_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID73_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL2__ATID72_SEL___M 0x00000100 +#define DBG_PHYADMUX_ATID_SEL2__ATID72_SEL___S 8 +#define DBG_PHYADMUX_ATID_SEL2__ATID72_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID72_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL2__ATID71_SEL___M 0x00000080 +#define DBG_PHYADMUX_ATID_SEL2__ATID71_SEL___S 7 +#define DBG_PHYADMUX_ATID_SEL2__ATID71_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID71_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL2__ATID70_SEL___M 0x00000040 +#define DBG_PHYADMUX_ATID_SEL2__ATID70_SEL___S 6 +#define DBG_PHYADMUX_ATID_SEL2__ATID70_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID70_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL2__ATID69_SEL___M 0x00000020 +#define DBG_PHYADMUX_ATID_SEL2__ATID69_SEL___S 5 +#define DBG_PHYADMUX_ATID_SEL2__ATID69_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID69_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL2__ATID68_SEL___M 0x00000010 +#define DBG_PHYADMUX_ATID_SEL2__ATID68_SEL___S 4 +#define DBG_PHYADMUX_ATID_SEL2__ATID68_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID68_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL2__ATID67_SEL___M 0x00000008 +#define DBG_PHYADMUX_ATID_SEL2__ATID67_SEL___S 3 +#define DBG_PHYADMUX_ATID_SEL2__ATID67_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID67_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL2__ATID66_SEL___M 0x00000004 +#define DBG_PHYADMUX_ATID_SEL2__ATID66_SEL___S 2 +#define DBG_PHYADMUX_ATID_SEL2__ATID66_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID66_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL2__ATID65_SEL___M 0x00000002 +#define DBG_PHYADMUX_ATID_SEL2__ATID65_SEL___S 1 +#define DBG_PHYADMUX_ATID_SEL2__ATID65_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID65_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL2__ATID64_SEL___M 0x00000001 +#define DBG_PHYADMUX_ATID_SEL2__ATID64_SEL___S 0 +#define DBG_PHYADMUX_ATID_SEL2__ATID64_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL2__ATID64_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL2___M 0xFFFFFFFF +#define DBG_PHYADMUX_ATID_SEL2___S 0 + +#define DBG_PHYADMUX_ATID_SEL3 (0x00BC601C) +#define DBG_PHYADMUX_ATID_SEL3___RWC QCSR_REG_RW +#define DBG_PHYADMUX_ATID_SEL3___POR 0x00000000 +#define DBG_PHYADMUX_ATID_SEL3__ATID127_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID126_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID125_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID124_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID123_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID122_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID121_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID120_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID119_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID118_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID117_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID116_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID115_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID114_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID113_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID112_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID111_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID110_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID109_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID108_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID107_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID106_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID105_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID104_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID103_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID102_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID101_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID100_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID99_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID98_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID97_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID96_SEL___POR 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID127_SEL___M 0x80000000 +#define DBG_PHYADMUX_ATID_SEL3__ATID127_SEL___S 31 +#define DBG_PHYADMUX_ATID_SEL3__ATID127_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID127_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL3__ATID126_SEL___M 0x40000000 +#define DBG_PHYADMUX_ATID_SEL3__ATID126_SEL___S 30 +#define DBG_PHYADMUX_ATID_SEL3__ATID126_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID126_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL3__ATID125_SEL___M 0x20000000 +#define DBG_PHYADMUX_ATID_SEL3__ATID125_SEL___S 29 +#define DBG_PHYADMUX_ATID_SEL3__ATID125_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID125_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL3__ATID124_SEL___M 0x10000000 +#define DBG_PHYADMUX_ATID_SEL3__ATID124_SEL___S 28 +#define DBG_PHYADMUX_ATID_SEL3__ATID124_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID124_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL3__ATID123_SEL___M 0x08000000 +#define DBG_PHYADMUX_ATID_SEL3__ATID123_SEL___S 27 +#define DBG_PHYADMUX_ATID_SEL3__ATID123_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID123_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL3__ATID122_SEL___M 0x04000000 +#define DBG_PHYADMUX_ATID_SEL3__ATID122_SEL___S 26 +#define DBG_PHYADMUX_ATID_SEL3__ATID122_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID122_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL3__ATID121_SEL___M 0x02000000 +#define DBG_PHYADMUX_ATID_SEL3__ATID121_SEL___S 25 +#define DBG_PHYADMUX_ATID_SEL3__ATID121_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID121_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL3__ATID120_SEL___M 0x01000000 +#define DBG_PHYADMUX_ATID_SEL3__ATID120_SEL___S 24 +#define DBG_PHYADMUX_ATID_SEL3__ATID120_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID120_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL3__ATID119_SEL___M 0x00800000 +#define DBG_PHYADMUX_ATID_SEL3__ATID119_SEL___S 23 +#define DBG_PHYADMUX_ATID_SEL3__ATID119_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID119_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL3__ATID118_SEL___M 0x00400000 +#define DBG_PHYADMUX_ATID_SEL3__ATID118_SEL___S 22 +#define DBG_PHYADMUX_ATID_SEL3__ATID118_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID118_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL3__ATID117_SEL___M 0x00200000 +#define DBG_PHYADMUX_ATID_SEL3__ATID117_SEL___S 21 +#define DBG_PHYADMUX_ATID_SEL3__ATID117_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID117_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL3__ATID116_SEL___M 0x00100000 +#define DBG_PHYADMUX_ATID_SEL3__ATID116_SEL___S 20 +#define DBG_PHYADMUX_ATID_SEL3__ATID116_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID116_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL3__ATID115_SEL___M 0x00080000 +#define DBG_PHYADMUX_ATID_SEL3__ATID115_SEL___S 19 +#define DBG_PHYADMUX_ATID_SEL3__ATID115_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID115_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL3__ATID114_SEL___M 0x00040000 +#define DBG_PHYADMUX_ATID_SEL3__ATID114_SEL___S 18 +#define DBG_PHYADMUX_ATID_SEL3__ATID114_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID114_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL3__ATID113_SEL___M 0x00020000 +#define DBG_PHYADMUX_ATID_SEL3__ATID113_SEL___S 17 +#define DBG_PHYADMUX_ATID_SEL3__ATID113_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID113_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL3__ATID112_SEL___M 0x00010000 +#define DBG_PHYADMUX_ATID_SEL3__ATID112_SEL___S 16 +#define DBG_PHYADMUX_ATID_SEL3__ATID112_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID112_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL3__ATID111_SEL___M 0x00008000 +#define DBG_PHYADMUX_ATID_SEL3__ATID111_SEL___S 15 +#define DBG_PHYADMUX_ATID_SEL3__ATID111_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID111_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL3__ATID110_SEL___M 0x00004000 +#define DBG_PHYADMUX_ATID_SEL3__ATID110_SEL___S 14 +#define DBG_PHYADMUX_ATID_SEL3__ATID110_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID110_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL3__ATID109_SEL___M 0x00002000 +#define DBG_PHYADMUX_ATID_SEL3__ATID109_SEL___S 13 +#define DBG_PHYADMUX_ATID_SEL3__ATID109_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID109_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL3__ATID108_SEL___M 0x00001000 +#define DBG_PHYADMUX_ATID_SEL3__ATID108_SEL___S 12 +#define DBG_PHYADMUX_ATID_SEL3__ATID108_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID108_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL3__ATID107_SEL___M 0x00000800 +#define DBG_PHYADMUX_ATID_SEL3__ATID107_SEL___S 11 +#define DBG_PHYADMUX_ATID_SEL3__ATID107_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID107_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL3__ATID106_SEL___M 0x00000400 +#define DBG_PHYADMUX_ATID_SEL3__ATID106_SEL___S 10 +#define DBG_PHYADMUX_ATID_SEL3__ATID106_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID106_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL3__ATID105_SEL___M 0x00000200 +#define DBG_PHYADMUX_ATID_SEL3__ATID105_SEL___S 9 +#define DBG_PHYADMUX_ATID_SEL3__ATID105_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID105_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL3__ATID104_SEL___M 0x00000100 +#define DBG_PHYADMUX_ATID_SEL3__ATID104_SEL___S 8 +#define DBG_PHYADMUX_ATID_SEL3__ATID104_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID104_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL3__ATID103_SEL___M 0x00000080 +#define DBG_PHYADMUX_ATID_SEL3__ATID103_SEL___S 7 +#define DBG_PHYADMUX_ATID_SEL3__ATID103_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID103_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL3__ATID102_SEL___M 0x00000040 +#define DBG_PHYADMUX_ATID_SEL3__ATID102_SEL___S 6 +#define DBG_PHYADMUX_ATID_SEL3__ATID102_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID102_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL3__ATID101_SEL___M 0x00000020 +#define DBG_PHYADMUX_ATID_SEL3__ATID101_SEL___S 5 +#define DBG_PHYADMUX_ATID_SEL3__ATID101_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID101_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL3__ATID100_SEL___M 0x00000010 +#define DBG_PHYADMUX_ATID_SEL3__ATID100_SEL___S 4 +#define DBG_PHYADMUX_ATID_SEL3__ATID100_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID100_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL3__ATID99_SEL___M 0x00000008 +#define DBG_PHYADMUX_ATID_SEL3__ATID99_SEL___S 3 +#define DBG_PHYADMUX_ATID_SEL3__ATID99_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID99_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL3__ATID98_SEL___M 0x00000004 +#define DBG_PHYADMUX_ATID_SEL3__ATID98_SEL___S 2 +#define DBG_PHYADMUX_ATID_SEL3__ATID98_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID98_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL3__ATID97_SEL___M 0x00000002 +#define DBG_PHYADMUX_ATID_SEL3__ATID97_SEL___S 1 +#define DBG_PHYADMUX_ATID_SEL3__ATID97_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID97_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL3__ATID96_SEL___M 0x00000001 +#define DBG_PHYADMUX_ATID_SEL3__ATID96_SEL___S 0 +#define DBG_PHYADMUX_ATID_SEL3__ATID96_SEL__SEL_PORT0 0x0 +#define DBG_PHYADMUX_ATID_SEL3__ATID96_SEL__SEL_PORT1 0x1 +#define DBG_PHYADMUX_ATID_SEL3___M 0xFFFFFFFF +#define DBG_PHYADMUX_ATID_SEL3___S 0 + +#define DBG_MISCFUN_CTRL_REG (0x00BC8000) +#define DBG_MISCFUN_CTRL_REG___RWC QCSR_REG_RW +#define DBG_MISCFUN_CTRL_REG___POR 0x00000300 +#define DBG_MISCFUN_CTRL_REG__HT___POR 0x3 +#define DBG_MISCFUN_CTRL_REG__ENS7___POR 0x0 +#define DBG_MISCFUN_CTRL_REG__ENS6___POR 0x0 +#define DBG_MISCFUN_CTRL_REG__ENS5___POR 0x0 +#define DBG_MISCFUN_CTRL_REG__ENS4___POR 0x0 +#define DBG_MISCFUN_CTRL_REG__ENS3___POR 0x0 +#define DBG_MISCFUN_CTRL_REG__ENS2___POR 0x0 +#define DBG_MISCFUN_CTRL_REG__ENS1___POR 0x0 +#define DBG_MISCFUN_CTRL_REG__ENS0___POR 0x0 +#define DBG_MISCFUN_CTRL_REG__HT___M 0x00000F00 +#define DBG_MISCFUN_CTRL_REG__HT___S 8 +#define DBG_MISCFUN_CTRL_REG__HT__HT_0X0 0x0 +#define DBG_MISCFUN_CTRL_REG__HT__HT_0X1 0x1 +#define DBG_MISCFUN_CTRL_REG__HT__HT_0X2 0x2 +#define DBG_MISCFUN_CTRL_REG__HT__HT_0X3 0x3 +#define DBG_MISCFUN_CTRL_REG__HT__HT_0X4 0x4 +#define DBG_MISCFUN_CTRL_REG__HT__HT_0X5 0x5 +#define DBG_MISCFUN_CTRL_REG__HT__HT_0X6 0x6 +#define DBG_MISCFUN_CTRL_REG__HT__HT_0X7 0x7 +#define DBG_MISCFUN_CTRL_REG__HT__HT_0X8 0x8 +#define DBG_MISCFUN_CTRL_REG__HT__HT_0X9 0x9 +#define DBG_MISCFUN_CTRL_REG__HT__HT_0XA 0xA +#define DBG_MISCFUN_CTRL_REG__HT__HT_0XB 0xB +#define DBG_MISCFUN_CTRL_REG__HT__HT_0XC 0xC +#define DBG_MISCFUN_CTRL_REG__HT__HT_0XD 0xD +#define DBG_MISCFUN_CTRL_REG__HT__HT_0XE 0xE +#define DBG_MISCFUN_CTRL_REG__ENS7___M 0x00000080 +#define DBG_MISCFUN_CTRL_REG__ENS7___S 7 +#define DBG_MISCFUN_CTRL_REG__ENS7__ENS7_0 0x0 +#define DBG_MISCFUN_CTRL_REG__ENS7__ENS7_1 0x1 +#define DBG_MISCFUN_CTRL_REG__ENS6___M 0x00000040 +#define DBG_MISCFUN_CTRL_REG__ENS6___S 6 +#define DBG_MISCFUN_CTRL_REG__ENS6__ENS6_0 0x0 +#define DBG_MISCFUN_CTRL_REG__ENS6__ENS6_1 0x1 +#define DBG_MISCFUN_CTRL_REG__ENS5___M 0x00000020 +#define DBG_MISCFUN_CTRL_REG__ENS5___S 5 +#define DBG_MISCFUN_CTRL_REG__ENS5__ENS5_0 0x0 +#define DBG_MISCFUN_CTRL_REG__ENS5__ENS5_1 0x1 +#define DBG_MISCFUN_CTRL_REG__ENS4___M 0x00000010 +#define DBG_MISCFUN_CTRL_REG__ENS4___S 4 +#define DBG_MISCFUN_CTRL_REG__ENS4__ENS4_0 0x0 +#define DBG_MISCFUN_CTRL_REG__ENS4__ENS4_1 0x1 +#define DBG_MISCFUN_CTRL_REG__ENS3___M 0x00000008 +#define DBG_MISCFUN_CTRL_REG__ENS3___S 3 +#define DBG_MISCFUN_CTRL_REG__ENS3__ENS3_0 0x0 +#define DBG_MISCFUN_CTRL_REG__ENS3__ENS3_1 0x1 +#define DBG_MISCFUN_CTRL_REG__ENS2___M 0x00000004 +#define DBG_MISCFUN_CTRL_REG__ENS2___S 2 +#define DBG_MISCFUN_CTRL_REG__ENS2__ENS2_0 0x0 +#define DBG_MISCFUN_CTRL_REG__ENS2__ENS2_1 0x1 +#define DBG_MISCFUN_CTRL_REG__ENS1___M 0x00000002 +#define DBG_MISCFUN_CTRL_REG__ENS1___S 1 +#define DBG_MISCFUN_CTRL_REG__ENS1__ENS1_0 0x0 +#define DBG_MISCFUN_CTRL_REG__ENS1__ENS1_1 0x1 +#define DBG_MISCFUN_CTRL_REG__ENS0___M 0x00000001 +#define DBG_MISCFUN_CTRL_REG__ENS0___S 0 +#define DBG_MISCFUN_CTRL_REG__ENS0__ENS0_0 0x0 +#define DBG_MISCFUN_CTRL_REG__ENS0__ENS0_1 0x1 +#define DBG_MISCFUN_CTRL_REG___M 0x00000FFF +#define DBG_MISCFUN_CTRL_REG___S 0 + +#define DBG_MISCFUN_PRIORITY_CTRL_REG (0x00BC8004) +#define DBG_MISCFUN_PRIORITY_CTRL_REG___RWC QCSR_REG_RW +#define DBG_MISCFUN_PRIORITY_CTRL_REG___POR 0x00000000 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT7___POR 0x0 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT6___POR 0x0 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT5___POR 0x0 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT4___POR 0x0 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT3___POR 0x0 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT2___POR 0x0 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT1___POR 0x0 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT0___POR 0x0 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT7___M 0x00E00000 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT7___S 21 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_0 0x0 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_1 0x1 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_2 0x2 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_3 0x3 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_4 0x4 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_5 0x5 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_6 0x6 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_7 0x7 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT6___M 0x001C0000 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT6___S 18 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_0 0x0 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_1 0x1 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_2 0x2 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_3 0x3 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_4 0x4 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_5 0x5 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_6 0x6 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_7 0x7 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT5___M 0x00038000 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT5___S 15 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_0 0x0 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_1 0x1 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_2 0x2 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_3 0x3 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_4 0x4 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_5 0x5 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_6 0x6 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_7 0x7 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT4___M 0x00007000 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT4___S 12 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_0 0x0 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_1 0x1 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_2 0x2 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_3 0x3 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_4 0x4 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_5 0x5 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_6 0x6 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_7 0x7 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT3___M 0x00000E00 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT3___S 9 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_0 0x0 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_1 0x1 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_2 0x2 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_3 0x3 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_4 0x4 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_5 0x5 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_6 0x6 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_7 0x7 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT2___M 0x000001C0 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT2___S 6 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_0 0x0 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_1 0x1 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_2 0x2 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_3 0x3 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_4 0x4 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_5 0x5 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_6 0x6 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_7 0x7 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT1___M 0x00000038 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT1___S 3 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_0 0x0 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_1 0x1 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_2 0x2 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_3 0x3 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_4 0x4 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_5 0x5 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_6 0x6 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_7 0x7 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT0___M 0x00000007 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT0___S 0 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_0 0x0 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_1 0x1 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_2 0x2 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_3 0x3 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_4 0x4 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_5 0x5 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_6 0x6 +#define DBG_MISCFUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_7 0x7 +#define DBG_MISCFUN_PRIORITY_CTRL_REG___M 0x00FFFFFF +#define DBG_MISCFUN_PRIORITY_CTRL_REG___S 0 + +#define DBG_MISCFUN_ITATBDATA0 (0x00BC8EEC) +#define DBG_MISCFUN_ITATBDATA0___RWC QCSR_REG_RW +#define DBG_MISCFUN_ITATBDATA0___POR 0x00000000 +#define DBG_MISCFUN_ITATBDATA0__ATDATA63___POR 0x0 +#define DBG_MISCFUN_ITATBDATA0__ATDATA55___POR 0x0 +#define DBG_MISCFUN_ITATBDATA0__ATDATA47___POR 0x0 +#define DBG_MISCFUN_ITATBDATA0__ATDATA39___POR 0x0 +#define DBG_MISCFUN_ITATBDATA0__ATDATA31___POR 0x0 +#define DBG_MISCFUN_ITATBDATA0__ATDATAM23___POR 0x0 +#define DBG_MISCFUN_ITATBDATA0__ATDATA15___POR 0x0 +#define DBG_MISCFUN_ITATBDATA0__ATDATA7___POR 0x0 +#define DBG_MISCFUN_ITATBDATA0__ATDATA0___POR 0x0 +#define DBG_MISCFUN_ITATBDATA0__ATDATA63___M 0x00000100 +#define DBG_MISCFUN_ITATBDATA0__ATDATA63___S 8 +#define DBG_MISCFUN_ITATBDATA0__ATDATA63__ATDATA63_0 0x0 +#define DBG_MISCFUN_ITATBDATA0__ATDATA63__ATDATA63_1 0x1 +#define DBG_MISCFUN_ITATBDATA0__ATDATA55___M 0x00000080 +#define DBG_MISCFUN_ITATBDATA0__ATDATA55___S 7 +#define DBG_MISCFUN_ITATBDATA0__ATDATA55__ATDATA55_0 0x0 +#define DBG_MISCFUN_ITATBDATA0__ATDATA55__ATDATA55_1 0x1 +#define DBG_MISCFUN_ITATBDATA0__ATDATA47___M 0x00000040 +#define DBG_MISCFUN_ITATBDATA0__ATDATA47___S 6 +#define DBG_MISCFUN_ITATBDATA0__ATDATA47__ATDATA47_0 0x0 +#define DBG_MISCFUN_ITATBDATA0__ATDATA47__ATDATA47_1 0x1 +#define DBG_MISCFUN_ITATBDATA0__ATDATA39___M 0x00000020 +#define DBG_MISCFUN_ITATBDATA0__ATDATA39___S 5 +#define DBG_MISCFUN_ITATBDATA0__ATDATA39__ATDATA39_0 0x0 +#define DBG_MISCFUN_ITATBDATA0__ATDATA39__ATDATA39_1 0x1 +#define DBG_MISCFUN_ITATBDATA0__ATDATA31___M 0x00000010 +#define DBG_MISCFUN_ITATBDATA0__ATDATA31___S 4 +#define DBG_MISCFUN_ITATBDATA0__ATDATA31__ATDATA31_0 0x0 +#define DBG_MISCFUN_ITATBDATA0__ATDATA31__ATDATA31_1 0x1 +#define DBG_MISCFUN_ITATBDATA0__ATDATAM23___M 0x00000008 +#define DBG_MISCFUN_ITATBDATA0__ATDATAM23___S 3 +#define DBG_MISCFUN_ITATBDATA0__ATDATAM23__ATDATAM23_0 0x0 +#define DBG_MISCFUN_ITATBDATA0__ATDATAM23__ATDATAM23_1 0x1 +#define DBG_MISCFUN_ITATBDATA0__ATDATA15___M 0x00000004 +#define DBG_MISCFUN_ITATBDATA0__ATDATA15___S 2 +#define DBG_MISCFUN_ITATBDATA0__ATDATA15__ATDATA15_0 0x0 +#define DBG_MISCFUN_ITATBDATA0__ATDATA15__ATDATA15_1 0x1 +#define DBG_MISCFUN_ITATBDATA0__ATDATA7___M 0x00000002 +#define DBG_MISCFUN_ITATBDATA0__ATDATA7___S 1 +#define DBG_MISCFUN_ITATBDATA0__ATDATA7__ATDATA7_0 0x0 +#define DBG_MISCFUN_ITATBDATA0__ATDATA7__ATDATA7_1 0x1 +#define DBG_MISCFUN_ITATBDATA0__ATDATA0___M 0x00000001 +#define DBG_MISCFUN_ITATBDATA0__ATDATA0___S 0 +#define DBG_MISCFUN_ITATBDATA0__ATDATA0__ATDATA0_0 0x0 +#define DBG_MISCFUN_ITATBDATA0__ATDATA0__ATDATA0_1 0x1 +#define DBG_MISCFUN_ITATBDATA0___M 0x000001FF +#define DBG_MISCFUN_ITATBDATA0___S 0 + +#define DBG_MISCFUN_ITATBCTR2 (0x00BC8EF0) +#define DBG_MISCFUN_ITATBCTR2___RWC QCSR_REG_RW +#define DBG_MISCFUN_ITATBCTR2___POR 0x00000000 +#define DBG_MISCFUN_ITATBCTR2__AFVALID___POR 0x0 +#define DBG_MISCFUN_ITATBCTR2__ATREADY___POR 0x0 +#define DBG_MISCFUN_ITATBCTR2__AFVALID___M 0x00000002 +#define DBG_MISCFUN_ITATBCTR2__AFVALID___S 1 +#define DBG_MISCFUN_ITATBCTR2__AFVALID__AFVALID_0 0x0 +#define DBG_MISCFUN_ITATBCTR2__AFVALID__AFVALID_1 0x1 +#define DBG_MISCFUN_ITATBCTR2__ATREADY___M 0x00000001 +#define DBG_MISCFUN_ITATBCTR2__ATREADY___S 0 +#define DBG_MISCFUN_ITATBCTR2__ATREADY__ATREADY_0 0x0 +#define DBG_MISCFUN_ITATBCTR2__ATREADY__ATREADY_1 0x1 +#define DBG_MISCFUN_ITATBCTR2___M 0x00000003 +#define DBG_MISCFUN_ITATBCTR2___S 0 + +#define DBG_MISCFUN_ITATBCTR1 (0x00BC8EF4) +#define DBG_MISCFUN_ITATBCTR1___RWC QCSR_REG_RW +#define DBG_MISCFUN_ITATBCTR1__ATID___M 0x0000007F +#define DBG_MISCFUN_ITATBCTR1__ATID___S 0 +#define DBG_MISCFUN_ITATBCTR1___M 0x0000007F +#define DBG_MISCFUN_ITATBCTR1___S 0 + +#define DBG_MISCFUN_ITATBCTR0 (0x00BC8EF8) +#define DBG_MISCFUN_ITATBCTR0___RWC QCSR_REG_RW +#define DBG_MISCFUN_ITATBCTR0___POR 0x00000000 +#define DBG_MISCFUN_ITATBCTR0__ATBYTES___POR 0x0 +#define DBG_MISCFUN_ITATBCTR0__AFREADY___POR 0x0 +#define DBG_MISCFUN_ITATBCTR0__ATVALID___POR 0x0 +#define DBG_MISCFUN_ITATBCTR0__ATBYTES___M 0x00000700 +#define DBG_MISCFUN_ITATBCTR0__ATBYTES___S 8 +#define DBG_MISCFUN_ITATBCTR0__ATBYTES__ATBYTES_0 0x0 +#define DBG_MISCFUN_ITATBCTR0__ATBYTES__ATBYTES_1 0x1 +#define DBG_MISCFUN_ITATBCTR0__AFREADY___M 0x00000002 +#define DBG_MISCFUN_ITATBCTR0__AFREADY___S 1 +#define DBG_MISCFUN_ITATBCTR0__AFREADY__AFREADY_0 0x0 +#define DBG_MISCFUN_ITATBCTR0__AFREADY__AFREADY_1 0x1 +#define DBG_MISCFUN_ITATBCTR0__ATVALID___M 0x00000001 +#define DBG_MISCFUN_ITATBCTR0__ATVALID___S 0 +#define DBG_MISCFUN_ITATBCTR0__ATVALID__ATVALID_0 0x0 +#define DBG_MISCFUN_ITATBCTR0__ATVALID__ATVALID_1 0x1 +#define DBG_MISCFUN_ITATBCTR0___M 0x00000703 +#define DBG_MISCFUN_ITATBCTR0___S 0 + +#define DBG_MISCFUN_ITCTRL (0x00BC8F00) +#define DBG_MISCFUN_ITCTRL___RWC QCSR_REG_RW +#define DBG_MISCFUN_ITCTRL___POR 0x00000000 +#define DBG_MISCFUN_ITCTRL__INTEGRATION_MODE___POR 0x0 +#define DBG_MISCFUN_ITCTRL__INTEGRATION_MODE___M 0x00000001 +#define DBG_MISCFUN_ITCTRL__INTEGRATION_MODE___S 0 +#define DBG_MISCFUN_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE_0 0x0 +#define DBG_MISCFUN_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE_1 0x1 +#define DBG_MISCFUN_ITCTRL___M 0x00000001 +#define DBG_MISCFUN_ITCTRL___S 0 + +#define DBG_MISCFUN_CLAIMSET (0x00BC8FA0) +#define DBG_MISCFUN_CLAIMSET___RWC QCSR_REG_RW +#define DBG_MISCFUN_CLAIMSET___POR 0x0000000F +#define DBG_MISCFUN_CLAIMSET__CLAIMSET___POR 0xF +#define DBG_MISCFUN_CLAIMSET__CLAIMSET___M 0x0000000F +#define DBG_MISCFUN_CLAIMSET__CLAIMSET___S 0 +#define DBG_MISCFUN_CLAIMSET__CLAIMSET__CLAIMSET_0XF 0xF +#define DBG_MISCFUN_CLAIMSET___M 0x0000000F +#define DBG_MISCFUN_CLAIMSET___S 0 + +#define DBG_MISCFUN_CLAIMCLR (0x00BC8FA4) +#define DBG_MISCFUN_CLAIMCLR___RWC QCSR_REG_RW +#define DBG_MISCFUN_CLAIMCLR___POR 0x00000000 +#define DBG_MISCFUN_CLAIMCLR__CLAIMCLR___POR 0x0 +#define DBG_MISCFUN_CLAIMCLR__CLAIMCLR___M 0x0000000F +#define DBG_MISCFUN_CLAIMCLR__CLAIMCLR___S 0 +#define DBG_MISCFUN_CLAIMCLR___M 0x0000000F +#define DBG_MISCFUN_CLAIMCLR___S 0 + +#define DBG_MISCFUN_LOCKACCESS (0x00BC8FB0) +#define DBG_MISCFUN_LOCKACCESS___RWC QCSR_REG_WO +#define DBG_MISCFUN_LOCKACCESS__KEY___M 0xFFFFFFFF +#define DBG_MISCFUN_LOCKACCESS__KEY___S 0 +#define DBG_MISCFUN_LOCKACCESS__KEY__KEY_0XC5ACCE55 0xC5ACCE55 +#define DBG_MISCFUN_LOCKACCESS__KEY__KEY_0XDEADBEEF 0xDEADBEEF +#define DBG_MISCFUN_LOCKACCESS___M 0xFFFFFFFF +#define DBG_MISCFUN_LOCKACCESS___S 0 + +#define DBG_MISCFUN_LOCKSTATUS (0x00BC8FB4) +#define DBG_MISCFUN_LOCKSTATUS___RWC QCSR_REG_RO +#define DBG_MISCFUN_LOCKSTATUS___POR 0x00000003 +#define DBG_MISCFUN_LOCKSTATUS__NTT___POR 0x0 +#define DBG_MISCFUN_LOCKSTATUS__SLK___POR 0x1 +#define DBG_MISCFUN_LOCKSTATUS__SLI___POR 0x1 +#define DBG_MISCFUN_LOCKSTATUS__NTT___M 0x00000004 +#define DBG_MISCFUN_LOCKSTATUS__NTT___S 2 +#define DBG_MISCFUN_LOCKSTATUS__NTT__NTT_0X0 0x0 +#define DBG_MISCFUN_LOCKSTATUS__SLK___M 0x00000002 +#define DBG_MISCFUN_LOCKSTATUS__SLK___S 1 +#define DBG_MISCFUN_LOCKSTATUS__SLK__SLK_0X0 0x0 +#define DBG_MISCFUN_LOCKSTATUS__SLK__SLK_0X1 0x1 +#define DBG_MISCFUN_LOCKSTATUS__SLI___M 0x00000001 +#define DBG_MISCFUN_LOCKSTATUS__SLI___S 0 +#define DBG_MISCFUN_LOCKSTATUS__SLI__SLI_0X0 0x0 +#define DBG_MISCFUN_LOCKSTATUS__SLI__SLI_0X1 0x1 +#define DBG_MISCFUN_LOCKSTATUS___M 0x00000007 +#define DBG_MISCFUN_LOCKSTATUS___S 0 + +#define DBG_MISCFUN_AUTHSTATUS (0x00BC8FB8) +#define DBG_MISCFUN_AUTHSTATUS___RWC QCSR_REG_RO +#define DBG_MISCFUN_AUTHSTATUS___POR 0x00000000 +#define DBG_MISCFUN_AUTHSTATUS__SNID___POR 0x0 +#define DBG_MISCFUN_AUTHSTATUS__SID___POR 0x0 +#define DBG_MISCFUN_AUTHSTATUS__NSNID___POR 0x0 +#define DBG_MISCFUN_AUTHSTATUS__NSID___POR 0x0 +#define DBG_MISCFUN_AUTHSTATUS__SNID___M 0x000000C0 +#define DBG_MISCFUN_AUTHSTATUS__SNID___S 6 +#define DBG_MISCFUN_AUTHSTATUS__SNID__SNID_0X0 0x0 +#define DBG_MISCFUN_AUTHSTATUS__SID___M 0x00000030 +#define DBG_MISCFUN_AUTHSTATUS__SID___S 4 +#define DBG_MISCFUN_AUTHSTATUS__SID__SID_0X0 0x0 +#define DBG_MISCFUN_AUTHSTATUS__NSNID___M 0x0000000C +#define DBG_MISCFUN_AUTHSTATUS__NSNID___S 2 +#define DBG_MISCFUN_AUTHSTATUS__NSNID__NSNID_0X0 0x0 +#define DBG_MISCFUN_AUTHSTATUS__NSID___M 0x00000003 +#define DBG_MISCFUN_AUTHSTATUS__NSID___S 0 +#define DBG_MISCFUN_AUTHSTATUS__NSID__NSID_0X0 0x0 +#define DBG_MISCFUN_AUTHSTATUS___M 0x000000FF +#define DBG_MISCFUN_AUTHSTATUS___S 0 + +#define DBG_MISCFUN_DEVID (0x00BC8FC8) +#define DBG_MISCFUN_DEVID___RWC QCSR_REG_RO +#define DBG_MISCFUN_DEVID___POR 0x00000038 +#define DBG_MISCFUN_DEVID__SCHEME___POR 0x3 +#define DBG_MISCFUN_DEVID__PORTCOUNT___POR 0x8 +#define DBG_MISCFUN_DEVID__SCHEME___M 0x000000F0 +#define DBG_MISCFUN_DEVID__SCHEME___S 4 +#define DBG_MISCFUN_DEVID__SCHEME__SCHEME_0X3 0x3 +#define DBG_MISCFUN_DEVID__PORTCOUNT___M 0x0000000F +#define DBG_MISCFUN_DEVID__PORTCOUNT___S 0 +#define DBG_MISCFUN_DEVID__PORTCOUNT__PORTCOUNT_0X2 0x2 +#define DBG_MISCFUN_DEVID__PORTCOUNT__PORTCOUNT_0X3 0x3 +#define DBG_MISCFUN_DEVID__PORTCOUNT__PORTCOUNT_0X4 0x4 +#define DBG_MISCFUN_DEVID__PORTCOUNT__PORTCOUNT_0X5 0x5 +#define DBG_MISCFUN_DEVID__PORTCOUNT__PORTCOUNT_0X6 0x6 +#define DBG_MISCFUN_DEVID__PORTCOUNT__PORTCOUNT_0X7 0x7 +#define DBG_MISCFUN_DEVID__PORTCOUNT__PORTCOUNT_0X8 0x8 +#define DBG_MISCFUN_DEVID___M 0x000000FF +#define DBG_MISCFUN_DEVID___S 0 + +#define DBG_MISCFUN_DEVTYPE (0x00BC8FCC) +#define DBG_MISCFUN_DEVTYPE___RWC QCSR_REG_RO +#define DBG_MISCFUN_DEVTYPE___POR 0x00000012 +#define DBG_MISCFUN_DEVTYPE__SUB_TYPE___POR 0x1 +#define DBG_MISCFUN_DEVTYPE__MAJOR_TYPE___POR 0x2 +#define DBG_MISCFUN_DEVTYPE__SUB_TYPE___M 0x000000F0 +#define DBG_MISCFUN_DEVTYPE__SUB_TYPE___S 4 +#define DBG_MISCFUN_DEVTYPE__SUB_TYPE__SUB_TYPE_0X1 0x1 +#define DBG_MISCFUN_DEVTYPE__MAJOR_TYPE___M 0x0000000F +#define DBG_MISCFUN_DEVTYPE__MAJOR_TYPE___S 0 +#define DBG_MISCFUN_DEVTYPE__MAJOR_TYPE__MAJOR_TYPE_0X2 0x2 +#define DBG_MISCFUN_DEVTYPE___M 0x000000FF +#define DBG_MISCFUN_DEVTYPE___S 0 + +#define DBG_MISCFUN_PIDR0 (0x00BC8FE0) +#define DBG_MISCFUN_PIDR0___RWC QCSR_REG_RO +#define DBG_MISCFUN_PIDR0___POR 0x00000008 +#define DBG_MISCFUN_PIDR0__PART_NUMBER_BITS7TO0___POR 0x08 +#define DBG_MISCFUN_PIDR0__PART_NUMBER_BITS7TO0___M 0x000000FF +#define DBG_MISCFUN_PIDR0__PART_NUMBER_BITS7TO0___S 0 +#define DBG_MISCFUN_PIDR0__PART_NUMBER_BITS7TO0__PART_NUMBER_BITS7TO0_0X08 0x08 +#define DBG_MISCFUN_PIDR0___M 0x000000FF +#define DBG_MISCFUN_PIDR0___S 0 + +#define DBG_MISCFUN_PIDR1 (0x00BC8FE4) +#define DBG_MISCFUN_PIDR1___RWC QCSR_REG_RO +#define DBG_MISCFUN_PIDR1___POR 0x000000B9 +#define DBG_MISCFUN_PIDR1__JEP106_BITS3TO0___POR 0xB +#define DBG_MISCFUN_PIDR1__PART_NUMBER_BITS11TO8___POR 0x9 +#define DBG_MISCFUN_PIDR1__JEP106_BITS3TO0___M 0x000000F0 +#define DBG_MISCFUN_PIDR1__JEP106_BITS3TO0___S 4 +#define DBG_MISCFUN_PIDR1__JEP106_BITS3TO0__JEP106_BITS3TO0_0XB 0xB +#define DBG_MISCFUN_PIDR1__PART_NUMBER_BITS11TO8___M 0x0000000F +#define DBG_MISCFUN_PIDR1__PART_NUMBER_BITS11TO8___S 0 +#define DBG_MISCFUN_PIDR1__PART_NUMBER_BITS11TO8__PART_NUMBER_BITS11TO8_0X9 0x9 +#define DBG_MISCFUN_PIDR1___M 0x000000FF +#define DBG_MISCFUN_PIDR1___S 0 + +#define DBG_MISCFUN_PIDR2 (0x00BC8FE8) +#define DBG_MISCFUN_PIDR2___RWC QCSR_REG_RO +#define DBG_MISCFUN_PIDR2___POR 0x0000003B +#define DBG_MISCFUN_PIDR2__REVISION___POR 0x3 +#define DBG_MISCFUN_PIDR2__JEDEC___POR 0x1 +#define DBG_MISCFUN_PIDR2__JEP106_BITS6TO4___POR 0x3 +#define DBG_MISCFUN_PIDR2__REVISION___M 0x000000F0 +#define DBG_MISCFUN_PIDR2__REVISION___S 4 +#define DBG_MISCFUN_PIDR2__REVISION__REVISION_0X3 0x3 +#define DBG_MISCFUN_PIDR2__JEDEC___M 0x00000008 +#define DBG_MISCFUN_PIDR2__JEDEC___S 3 +#define DBG_MISCFUN_PIDR2__JEDEC__JEDEC_0X1 0x1 +#define DBG_MISCFUN_PIDR2__JEP106_BITS6TO4___M 0x00000007 +#define DBG_MISCFUN_PIDR2__JEP106_BITS6TO4___S 0 +#define DBG_MISCFUN_PIDR2__JEP106_BITS6TO4__JEP106_BITS6TO4_0X3 0x3 +#define DBG_MISCFUN_PIDR2___M 0x000000FF +#define DBG_MISCFUN_PIDR2___S 0 + +#define DBG_MISCFUN_PIDR3 (0x00BC8FEC) +#define DBG_MISCFUN_PIDR3___RWC QCSR_REG_RO +#define DBG_MISCFUN_PIDR3___POR 0x00000000 +#define DBG_MISCFUN_PIDR3__REVAND___POR 0x0 +#define DBG_MISCFUN_PIDR3__CUSTOMER_MODIFIED___POR 0x0 +#define DBG_MISCFUN_PIDR3__REVAND___M 0x000000F0 +#define DBG_MISCFUN_PIDR3__REVAND___S 4 +#define DBG_MISCFUN_PIDR3__REVAND__REVAND_0X0 0x0 +#define DBG_MISCFUN_PIDR3__CUSTOMER_MODIFIED___M 0x0000000F +#define DBG_MISCFUN_PIDR3__CUSTOMER_MODIFIED___S 0 +#define DBG_MISCFUN_PIDR3__CUSTOMER_MODIFIED__CUSTOMER_MODIFIED_0X0 0x0 +#define DBG_MISCFUN_PIDR3___M 0x000000FF +#define DBG_MISCFUN_PIDR3___S 0 + +#define DBG_MISCFUN_PIDR4 (0x00BC8FD0) +#define DBG_MISCFUN_PIDR4___RWC QCSR_REG_RO +#define DBG_MISCFUN_PIDR4___POR 0x00000004 +#define DBG_MISCFUN_PIDR4__FOURKB_COUNT___POR 0x0 +#define DBG_MISCFUN_PIDR4__JEP106_CONT___POR 0x4 +#define DBG_MISCFUN_PIDR4__FOURKB_COUNT___M 0x000000F0 +#define DBG_MISCFUN_PIDR4__FOURKB_COUNT___S 4 +#define DBG_MISCFUN_PIDR4__FOURKB_COUNT__FOURKB_COUNT_0X0 0x0 +#define DBG_MISCFUN_PIDR4__JEP106_CONT___M 0x0000000F +#define DBG_MISCFUN_PIDR4__JEP106_CONT___S 0 +#define DBG_MISCFUN_PIDR4__JEP106_CONT__JEP106_CONT_0X4 0x4 +#define DBG_MISCFUN_PIDR4___M 0x000000FF +#define DBG_MISCFUN_PIDR4___S 0 + +#define DBG_MISCFUN_PERIPHID5 (0x00BC8FD4) +#define DBG_MISCFUN_PERIPHID5___RWC QCSR_REG_RO +#define DBG_MISCFUN_PERIPHID5___POR 0x00000000 +#define DBG_MISCFUN_PERIPHID5__PERIPHID5___POR 0x00000000 +#define DBG_MISCFUN_PERIPHID5__PERIPHID5___M 0xFFFFFFFF +#define DBG_MISCFUN_PERIPHID5__PERIPHID5___S 0 +#define DBG_MISCFUN_PERIPHID5___M 0xFFFFFFFF +#define DBG_MISCFUN_PERIPHID5___S 0 + +#define DBG_MISCFUN_PERIPHID6 (0x00BC8FD8) +#define DBG_MISCFUN_PERIPHID6___RWC QCSR_REG_RO +#define DBG_MISCFUN_PERIPHID6___POR 0x00000000 +#define DBG_MISCFUN_PERIPHID6__PERIPHID6___POR 0x00000000 +#define DBG_MISCFUN_PERIPHID6__PERIPHID6___M 0xFFFFFFFF +#define DBG_MISCFUN_PERIPHID6__PERIPHID6___S 0 +#define DBG_MISCFUN_PERIPHID6___M 0xFFFFFFFF +#define DBG_MISCFUN_PERIPHID6___S 0 + +#define DBG_MISCFUN_PERIPHID7 (0x00BC8FDC) +#define DBG_MISCFUN_PERIPHID7___RWC QCSR_REG_RO +#define DBG_MISCFUN_PERIPHID7___POR 0x00000000 +#define DBG_MISCFUN_PERIPHID7__PERIPHID7___POR 0x00000000 +#define DBG_MISCFUN_PERIPHID7__PERIPHID7___M 0xFFFFFFFF +#define DBG_MISCFUN_PERIPHID7__PERIPHID7___S 0 +#define DBG_MISCFUN_PERIPHID7___M 0xFFFFFFFF +#define DBG_MISCFUN_PERIPHID7___S 0 + +#define DBG_MISCFUN_CID0 (0x00BC8FF0) +#define DBG_MISCFUN_CID0___RWC QCSR_REG_RO +#define DBG_MISCFUN_CID0___POR 0x0000000D +#define DBG_MISCFUN_CID0__PREAMBLE___POR 0x0D +#define DBG_MISCFUN_CID0__PREAMBLE___M 0x000000FF +#define DBG_MISCFUN_CID0__PREAMBLE___S 0 +#define DBG_MISCFUN_CID0__PREAMBLE__PREAMBLE_0X0D 0x0D +#define DBG_MISCFUN_CID0___M 0x000000FF +#define DBG_MISCFUN_CID0___S 0 + +#define DBG_MISCFUN_CID1 (0x00BC8FF4) +#define DBG_MISCFUN_CID1___RWC QCSR_REG_RO +#define DBG_MISCFUN_CID1___POR 0x00000090 +#define DBG_MISCFUN_CID1__CLASS___POR 0x9 +#define DBG_MISCFUN_CID1__PREAMBLE___POR 0x0 +#define DBG_MISCFUN_CID1__CLASS___M 0x000000F0 +#define DBG_MISCFUN_CID1__CLASS___S 4 +#define DBG_MISCFUN_CID1__CLASS__CLASS_0X9 0x9 +#define DBG_MISCFUN_CID1__PREAMBLE___M 0x0000000F +#define DBG_MISCFUN_CID1__PREAMBLE___S 0 +#define DBG_MISCFUN_CID1__PREAMBLE__PREAMBLE_0X0 0x0 +#define DBG_MISCFUN_CID1___M 0x000000FF +#define DBG_MISCFUN_CID1___S 0 + +#define DBG_MISCFUN_CID2 (0x00BC8FF8) +#define DBG_MISCFUN_CID2___RWC QCSR_REG_RO +#define DBG_MISCFUN_CID2___POR 0x00000005 +#define DBG_MISCFUN_CID2__PREAMBLE___POR 0x05 +#define DBG_MISCFUN_CID2__PREAMBLE___M 0x000000FF +#define DBG_MISCFUN_CID2__PREAMBLE___S 0 +#define DBG_MISCFUN_CID2__PREAMBLE__PREAMBLE_0X05 0x05 +#define DBG_MISCFUN_CID2___M 0x000000FF +#define DBG_MISCFUN_CID2___S 0 + +#define DBG_MISCFUN_CID3 (0x00BC8FFC) +#define DBG_MISCFUN_CID3___RWC QCSR_REG_RO +#define DBG_MISCFUN_CID3___POR 0x000000B1 +#define DBG_MISCFUN_CID3__PREAMBLE___POR 0xB1 +#define DBG_MISCFUN_CID3__PREAMBLE___M 0x000000FF +#define DBG_MISCFUN_CID3__PREAMBLE___S 0 +#define DBG_MISCFUN_CID3__PREAMBLE__PREAMBLE_0XB1 0xB1 +#define DBG_MISCFUN_CID3___M 0x000000FF +#define DBG_MISCFUN_CID3___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW (0x00BD0000) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW___POR 0x0001E93B +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW__UNITTYPEID___POR 0x01 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW__UNITCONFID___POR 0xE93B +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW__UNITTYPEID___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW__UNITCONFID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW___M 0x00FFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_HIGH (0x00BD0004) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_HIGH__QNOCID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_HIGH___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW (0x00BD0008) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW___POR 0x00000003 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW__STALLEN___POR 0x1 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW__FAULTEN___POR 0x1 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW__STALLEN___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW__STALLEN___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW__FAULTEN___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW__FAULTEN___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW___M 0x00000003 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRVLD_LOW (0x00BD0010) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRVLD_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRVLD_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRVLD_LOW__ERRVLD___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRVLD_LOW__ERRVLD___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRVLD_LOW__ERRVLD___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRVLD_LOW___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRVLD_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRCLR_LOW (0x00BD0018) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRCLR_LOW___RWC QCSR_REG_WO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRCLR_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRCLR_LOW__ERRCLR___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRCLR_LOW__ERRCLR___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRCLR_LOW__ERRCLR___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRCLR_LOW___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRCLR_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW (0x00BD0020) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ATOPC___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ADDRSPACE___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__TRTYPE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ERRCODE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__OPC___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__NONSECURE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__WORDERROR___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__LOGINFOVLD___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ATOPC___M 0x0F000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ATOPC___S 24 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ADDRSPACE___M 0x003F0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ADDRSPACE___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__TRTYPE___M 0x00007000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__TRTYPE___S 12 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ERRCODE___M 0x00000700 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ERRCODE___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__OPC___M 0x00000070 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__OPC___S 4 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__NONSECURE___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__NONSECURE___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__WORDERROR___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__WORDERROR___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__LOGINFOVLD___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__LOGINFOVLD___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW___M 0x0F3F7777 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH (0x00BD0024) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH__REDIRECT___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH__LEN1___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH__REDIRECT___M 0x00FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH__REDIRECT___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH__LEN1___M 0x000003FF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH__LEN1___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH___M 0x00FF03FF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_LOW (0x00BD0028) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_LOW__PATH___POR 0x0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_LOW__PATH___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_LOW__PATH___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_LOW___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_HIGH (0x00BD002C) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_HIGH___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_HIGH__EXTID___POR 0x00000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_HIGH__EXTID___M 0x0003FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_HIGH__EXTID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_HIGH___M 0x0003FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_LOW (0x00BD0030) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_LOW__ERRLOG2_LSB___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_LOW__ERRLOG2_LSB___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_LOW__ERRLOG2_LSB___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_LOW___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_HIGH (0x00BD0034) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_HIGH___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___POR 0x00000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___M 0x0001FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_HIGH___M 0x0001FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_LOW (0x00BD0038) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_LOW__ERRLOG3_LSB___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_LOW__ERRLOG3_LSB___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_LOW__ERRLOG3_LSB___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_LOW___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_HIGH (0x00BD003C) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_HIGH___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_HIGH___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW (0x00BD0080) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW___POR 0x0001E93B +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW__UNITTYPEID___POR 0x01 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW__UNITCONFID___POR 0xE93B +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW__UNITTYPEID___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW__UNITCONFID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW___M 0x00FFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_HIGH (0x00BD0084) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_HIGH__QNOCID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_HIGH___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW (0x00BD0088) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW___POR 0x00000003 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW__STALLEN___POR 0x1 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW__FAULTEN___POR 0x1 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW__STALLEN___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW__STALLEN___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW__FAULTEN___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW__FAULTEN___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW___M 0x00000003 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRVLD_LOW (0x00BD0090) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRVLD_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRVLD_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRVLD_LOW__ERRVLD___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRVLD_LOW__ERRVLD___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRVLD_LOW__ERRVLD___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRVLD_LOW___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRVLD_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRCLR_LOW (0x00BD0098) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRCLR_LOW___RWC QCSR_REG_WO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRCLR_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRCLR_LOW__ERRCLR___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRCLR_LOW__ERRCLR___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRCLR_LOW__ERRCLR___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRCLR_LOW___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRCLR_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW (0x00BD00A0) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ATOPC___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ADDRSPACE___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__TRTYPE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ERRCODE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__OPC___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__NONSECURE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__WORDERROR___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__LOGINFOVLD___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ATOPC___M 0x0F000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ATOPC___S 24 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ADDRSPACE___M 0x003F0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ADDRSPACE___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__TRTYPE___M 0x00007000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__TRTYPE___S 12 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ERRCODE___M 0x00000700 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ERRCODE___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__OPC___M 0x00000070 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__OPC___S 4 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__NONSECURE___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__NONSECURE___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__WORDERROR___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__WORDERROR___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__LOGINFOVLD___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__LOGINFOVLD___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW___M 0x0F3F7777 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH (0x00BD00A4) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH__REDIRECT___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH__LEN1___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH__REDIRECT___M 0x00FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH__REDIRECT___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH__LEN1___M 0x000003FF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH__LEN1___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH___M 0x00FF03FF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_LOW (0x00BD00A8) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_LOW__PATH___POR 0x0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_LOW__PATH___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_LOW__PATH___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_LOW___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_HIGH (0x00BD00AC) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_HIGH___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_HIGH__EXTID___POR 0x00000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_HIGH__EXTID___M 0x0003FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_HIGH__EXTID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_HIGH___M 0x0003FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_LOW (0x00BD00B0) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_LOW__ERRLOG2_LSB___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_LOW__ERRLOG2_LSB___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_LOW__ERRLOG2_LSB___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_LOW___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_HIGH (0x00BD00B4) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_HIGH___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___POR 0x00000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___M 0x0001FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_HIGH___M 0x0001FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_LOW (0x00BD00B8) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_LOW__ERRLOG3_LSB___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_LOW__ERRLOG3_LSB___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_LOW__ERRLOG3_LSB___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_LOW___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_HIGH (0x00BD00BC) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_HIGH___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_HIGH___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW (0x00BD0100) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW___POR 0x0001E93B +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW__UNITTYPEID___POR 0x01 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW__UNITCONFID___POR 0xE93B +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW__UNITTYPEID___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW__UNITCONFID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW___M 0x00FFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_HIGH (0x00BD0104) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_HIGH__QNOCID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_HIGH___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW (0x00BD0108) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW___POR 0x00000003 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW__STALLEN___POR 0x1 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW__FAULTEN___POR 0x1 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW__STALLEN___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW__STALLEN___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW__FAULTEN___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW__FAULTEN___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW___M 0x00000003 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRVLD_LOW (0x00BD0110) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRVLD_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRVLD_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRVLD_LOW__ERRVLD___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRVLD_LOW__ERRVLD___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRVLD_LOW__ERRVLD___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRVLD_LOW___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRVLD_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRCLR_LOW (0x00BD0118) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRCLR_LOW___RWC QCSR_REG_WO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRCLR_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRCLR_LOW__ERRCLR___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRCLR_LOW__ERRCLR___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRCLR_LOW__ERRCLR___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRCLR_LOW___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRCLR_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW (0x00BD0120) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ATOPC___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ADDRSPACE___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__TRTYPE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ERRCODE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__OPC___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__NONSECURE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__WORDERROR___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__LOGINFOVLD___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ATOPC___M 0x0F000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ATOPC___S 24 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ADDRSPACE___M 0x003F0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ADDRSPACE___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__TRTYPE___M 0x00007000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__TRTYPE___S 12 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ERRCODE___M 0x00000700 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ERRCODE___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__OPC___M 0x00000070 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__OPC___S 4 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__NONSECURE___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__NONSECURE___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__WORDERROR___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__WORDERROR___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__LOGINFOVLD___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__LOGINFOVLD___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW___M 0x0F3F7777 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH (0x00BD0124) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH__REDIRECT___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH__LEN1___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH__REDIRECT___M 0x00FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH__REDIRECT___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH__LEN1___M 0x000003FF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH__LEN1___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH___M 0x00FF03FF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_LOW (0x00BD0128) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_LOW__PATH___POR 0x0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_LOW__PATH___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_LOW__PATH___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_LOW___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_HIGH (0x00BD012C) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_HIGH___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_HIGH__EXTID___POR 0x00000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_HIGH__EXTID___M 0x0003FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_HIGH__EXTID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_HIGH___M 0x0003FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_LOW (0x00BD0130) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_LOW__ERRLOG2_LSB___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_LOW__ERRLOG2_LSB___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_LOW__ERRLOG2_LSB___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_LOW___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_HIGH (0x00BD0134) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_HIGH___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___POR 0x00000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___M 0x0001FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_HIGH___M 0x0001FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_LOW (0x00BD0138) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_LOW__ERRLOG3_LSB___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_LOW__ERRLOG3_LSB___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_LOW__ERRLOG3_LSB___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_LOW___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_HIGH (0x00BD013C) +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_HIGH___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_HIGH___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW (0x00BD0200) +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW___POR 0x000EEC22 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW__UNITTYPEID___POR 0x0E +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW__UNITCONFID___POR 0xEC22 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW__UNITTYPEID___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW__UNITCONFID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW___M 0x00FFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_HIGH (0x00BD0204) +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_HIGH__QNOCID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_HIGH___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW (0x00BD0240) +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__EVENTCOLLECTOR_ALARM___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__QXS_SNOC_TRACE_ALARM___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_PHY_FAULT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_WMAC_FAULT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_FAULT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XS_CMEM___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_WMAC0___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_WBM___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_TQM___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_TCL___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_REO___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIEMOUT_XM_COEX___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_SERVICENIU___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXS_SNOC___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXS_PHYA___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXM_SNOC___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXM_PHYA___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QHS_RET_AHB___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QHM_RET_AHB___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_PM_WCSS_DBG___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__EVENTCOLLECTOR_ALARM___M 0x00800000 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__EVENTCOLLECTOR_ALARM___S 23 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__QXS_SNOC_TRACE_ALARM___M 0x00400000 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__QXS_SNOC_TRACE_ALARM___S 22 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_PHY_FAULT___M 0x00200000 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_PHY_FAULT___S 21 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_WMAC_FAULT___M 0x00100000 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_WMAC_FAULT___S 20 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_FAULT___M 0x00080000 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_FAULT___S 19 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XS_CMEM___M 0x00040000 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XS_CMEM___S 18 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_WMAC0___M 0x00010000 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_WMAC0___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_WBM___M 0x00008000 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_WBM___S 15 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_TQM___M 0x00004000 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_TQM___S 14 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_TCL___M 0x00002000 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_TCL___S 13 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_REO___M 0x00001000 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_REO___S 12 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIEMOUT_XM_COEX___M 0x00000800 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIEMOUT_XM_COEX___S 11 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_SERVICENIU___M 0x00000400 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_SERVICENIU___S 10 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXS_SNOC___M 0x00000100 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXS_SNOC___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXS_PHYA___M 0x00000040 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXS_PHYA___S 6 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXM_SNOC___M 0x00000020 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXM_SNOC___S 5 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXM_PHYA___M 0x00000008 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXM_PHYA___S 3 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QHS_RET_AHB___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QHS_RET_AHB___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QHM_RET_AHB___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QHM_RET_AHB___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_PM_WCSS_DBG___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_PM_WCSS_DBG___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW___M 0x00FDFD6F +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW (0x00BD0248) +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__EVENTCOLLECTOR_ALARM___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__QXS_SNOC_TRACE_ALARM___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_PHY_FAULT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_WMAC_FAULT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_FAULT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XS_CMEM___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_WMAC0___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_WBM___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_TQM___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_TCL___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_REO___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIEMOUT_XM_COEX___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_SERVICENIU___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXS_SNOC___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXS_PHYA___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXM_SNOC___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXM_PHYA___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QHS_RET_AHB___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QHM_RET_AHB___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_PM_WCSS_DBG___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__EVENTCOLLECTOR_ALARM___M 0x00800000 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__EVENTCOLLECTOR_ALARM___S 23 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__QXS_SNOC_TRACE_ALARM___M 0x00400000 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__QXS_SNOC_TRACE_ALARM___S 22 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_PHY_FAULT___M 0x00200000 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_PHY_FAULT___S 21 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_WMAC_FAULT___M 0x00100000 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_WMAC_FAULT___S 20 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_FAULT___M 0x00080000 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_FAULT___S 19 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XS_CMEM___M 0x00040000 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XS_CMEM___S 18 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_WMAC0___M 0x00010000 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_WMAC0___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_WBM___M 0x00008000 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_WBM___S 15 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_TQM___M 0x00004000 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_TQM___S 14 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_TCL___M 0x00002000 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_TCL___S 13 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_REO___M 0x00001000 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_REO___S 12 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIEMOUT_XM_COEX___M 0x00000800 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIEMOUT_XM_COEX___S 11 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_SERVICENIU___M 0x00000400 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_SERVICENIU___S 10 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXS_SNOC___M 0x00000100 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXS_SNOC___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXS_PHYA___M 0x00000040 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXS_PHYA___S 6 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXM_SNOC___M 0x00000020 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXM_SNOC___S 5 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXM_PHYA___M 0x00000008 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXM_PHYA___S 3 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QHS_RET_AHB___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QHS_RET_AHB___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QHM_RET_AHB___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QHM_RET_AHB___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_PM_WCSS_DBG___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_PM_WCSS_DBG___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW___M 0x00FDFD6F +#define DBG_UNOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW (0x00BD0400) +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW___POR 0x000E8DBE +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW__UNITTYPEID___POR 0x0E +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW__UNITCONFID___POR 0x8DBE +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW__UNITTYPEID___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW__UNITCONFID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW___M 0x00FFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_HIGH (0x00BD0404) +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_HIGH__QNOCID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_HIGH___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTCLR0_LOW (0x00BD0480) +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTCLR0_LOW___RWC QCSR_REG_WO +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTCLR0_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTCLR0_LOW__COEX_APB2AXI_XWERR___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTCLR0_LOW__COEX_APB2AXI_XWERR___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTCLR0_LOW__COEX_APB2AXI_XWERR___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTCLR0_LOW___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTCLR0_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSET0_LOW (0x00BD0488) +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSET0_LOW___RWC QCSR_REG_WO +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSET0_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSET0_LOW__COEX_APB2AXI_XWERR___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSET0_LOW__COEX_APB2AXI_XWERR___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSET0_LOW__COEX_APB2AXI_XWERR___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSET0_LOW___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSET0_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSTATUS0_LOW (0x00BD0490) +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSTATUS0_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSTATUS0_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSTATUS0_LOW__COEX_APB2AXI_XWERR___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSTATUS0_LOW__COEX_APB2AXI_XWERR___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSTATUS0_LOW__COEX_APB2AXI_XWERR___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSTATUS0_LOW___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSTATUS0_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW (0x00BD0500) +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW__COEX_APB2AXI_XWSLVERR___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW__COEX_APB2AXI_XWDECERR___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW__COEX_APB2AXI_XWSLVERR___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW__COEX_APB2AXI_XWSLVERR___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW__COEX_APB2AXI_XWDECERR___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW__COEX_APB2AXI_XWDECERR___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW___M 0x00000003 +#define DBG_UNOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW (0x00BD0600) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW___POR 0x0008317D +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW__UNITTYPEID___POR 0x08 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW__UNITCONFID___POR 0x317D +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW__UNITTYPEID___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW__UNITCONFID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW___M 0x00FFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_HIGH (0x00BD0604) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_HIGH__QNOCID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_HIGH___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW (0x00BD0608) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__URGDELAY___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__DFLTPRIORITY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__STOP___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__SHAPEREN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__BWLIMITEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__URGDELAY___M 0x00003F00 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__URGDELAY___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__DFLTPRIORITY___M 0x00000030 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__DFLTPRIORITY___S 4 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__STOP___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__STOP___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__SHAPEREN___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__SHAPEREN___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__BWLIMITEN___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__BWLIMITEN___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW___M 0x00003F37 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW (0x00BD0610) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW___POR 0x00F00000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___POR 0x0F0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW__PENDING___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___M 0x0FFF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW__PENDING___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW__PENDING___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW___M 0x0FFF001F +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW (0x00BD0618) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW__SATURATION___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW__BANDWIDTH___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW__SATURATION___M 0x03FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW__SATURATION___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW__BANDWIDTH___M 0x000007FF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW__BANDWIDTH___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW___M 0x03FF07FF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW (0x00BD0620) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL3___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL2___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL1___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL0___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL3___M 0x0F000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL3___S 24 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL2___M 0x000F0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL2___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL1___M 0x00000F00 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL1___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL0___M 0x0000000F +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL0___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW___M 0x0F0F0F0F +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW (0x00BD0640) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__HIGHPRIORITY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__LOWPRIORITY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__WREN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__RDEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__HIGHPRIORITY___M 0x00003000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__HIGHPRIORITY___S 12 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__LOWPRIORITY___M 0x00000300 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__LOWPRIORITY___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__WREN___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__WREN___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__RDEN___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__RDEN___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW___M 0x00003303 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW (0x00BD0648) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW___POR 0x00800400 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW__SATURATION___POR 0x080 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW__BANDWIDTH___POR 0x400 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW__SATURATION___M 0x03FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW__SATURATION___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW__BANDWIDTH___M 0x000007FF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW__BANDWIDTH___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW___M 0x03FF07FF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW (0x00BD0650) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__HIGHPRIORITY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__LOWPRIORITY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__WREN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__RDEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__HIGHPRIORITY___M 0x00003000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__HIGHPRIORITY___S 12 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__LOWPRIORITY___M 0x00000300 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__LOWPRIORITY___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__WREN___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__WREN___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__RDEN___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__RDEN___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW___M 0x00003303 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW (0x00BD0658) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW___POR 0x00800400 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW__SATURATION___POR 0x080 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW__BANDWIDTH___POR 0x400 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW__SATURATION___M 0x03FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW__SATURATION___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW__BANDWIDTH___M 0x000007FF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW__BANDWIDTH___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW___M 0x03FF07FF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW (0x00BD0700) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW___POR 0x0008FDF1 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW__UNITTYPEID___POR 0x08 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW__UNITCONFID___POR 0xFDF1 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW__UNITTYPEID___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW__UNITCONFID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW___M 0x00FFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_HIGH (0x00BD0704) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_HIGH__QNOCID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_HIGH___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW (0x00BD0708) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__STOP___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__SHAPEREN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__BWLIMITEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__STOP___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__STOP___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__SHAPEREN___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__SHAPEREN___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__BWLIMITEN___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__BWLIMITEN___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW___M 0x00000007 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW (0x00BD0710) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW___POR 0x00F00000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___POR 0x0F0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW__PENDING___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___M 0x0FFF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW__PENDING___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW__PENDING___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW___M 0x0FFF001F +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW (0x00BD0718) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW__SATURATION___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW__BANDWIDTH___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW__SATURATION___M 0x03FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW__SATURATION___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW__BANDWIDTH___M 0x000007FF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW__BANDWIDTH___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW___M 0x03FF07FF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW (0x00BD0720) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL3___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL2___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL1___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL0___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL3___M 0x0F000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL3___S 24 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL2___M 0x000F0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL2___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL1___M 0x00000F00 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL1___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL0___M 0x0000000F +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL0___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW___M 0x0F0F0F0F +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW (0x00BD0780) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW___POR 0x0008FDF1 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW__UNITTYPEID___POR 0x08 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW__UNITCONFID___POR 0xFDF1 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW__UNITTYPEID___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW__UNITCONFID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW___M 0x00FFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_HIGH (0x00BD0784) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_HIGH__QNOCID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_HIGH___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW (0x00BD0788) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__STOP___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__SHAPEREN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__BWLIMITEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__STOP___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__STOP___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__SHAPEREN___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__SHAPEREN___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__BWLIMITEN___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__BWLIMITEN___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW___M 0x00000007 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW (0x00BD0790) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW___POR 0x00F00000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___POR 0x0F0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW__PENDING___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___M 0x0FFF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW__PENDING___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW__PENDING___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW___M 0x0FFF001F +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW (0x00BD0798) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW__SATURATION___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW__BANDWIDTH___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW__SATURATION___M 0x03FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW__SATURATION___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW__BANDWIDTH___M 0x000007FF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW__BANDWIDTH___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW___M 0x03FF07FF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW (0x00BD07A0) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL3___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL2___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL1___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL0___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL3___M 0x0F000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL3___S 24 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL2___M 0x000F0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL2___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL1___M 0x00000F00 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL1___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL0___M 0x0000000F +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL0___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW___M 0x0F0F0F0F +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW (0x00BD0800) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW___POR 0x00087F1D +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW__UNITTYPEID___POR 0x08 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW__UNITCONFID___POR 0x7F1D +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW__UNITTYPEID___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW__UNITCONFID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW___M 0x00FFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_HIGH (0x00BD0804) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_HIGH__QNOCID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_HIGH___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW (0x00BD0808) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__STOP___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__SHAPEREN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__BWLIMITEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__STOP___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__STOP___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__SHAPEREN___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__SHAPEREN___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__BWLIMITEN___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__BWLIMITEN___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW___M 0x00000007 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW (0x00BD0810) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW___POR 0x00F00000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___POR 0x0F0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW__PENDING___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___M 0x0FFF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW__PENDING___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW__PENDING___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW___M 0x0FFF001F +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW (0x00BD0818) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW__SATURATION___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW__BANDWIDTH___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW__SATURATION___M 0x03FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW__SATURATION___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW__BANDWIDTH___M 0x000007FF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW__BANDWIDTH___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW___M 0x03FF07FF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW (0x00BD0820) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL3___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL2___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL1___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL0___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL3___M 0x1F000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL3___S 24 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL2___M 0x001F0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL2___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL1___M 0x00001F00 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL1___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL0___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL0___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW___M 0x1F1F1F1F +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW (0x00BD0880) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW___POR 0x0008FDF1 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW__UNITTYPEID___POR 0x08 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW__UNITCONFID___POR 0xFDF1 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW__UNITTYPEID___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW__UNITCONFID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW___M 0x00FFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_HIGH (0x00BD0884) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_HIGH__QNOCID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_HIGH___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW (0x00BD0888) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__STOP___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__SHAPEREN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__BWLIMITEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__STOP___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__STOP___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__SHAPEREN___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__SHAPEREN___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__BWLIMITEN___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__BWLIMITEN___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW___M 0x00000007 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW (0x00BD0890) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW___POR 0x00F00000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___POR 0x0F0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW__PENDING___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___M 0x0FFF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW__PENDING___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW__PENDING___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW___M 0x0FFF001F +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW (0x00BD0898) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW__SATURATION___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW__BANDWIDTH___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW__SATURATION___M 0x03FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW__SATURATION___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW__BANDWIDTH___M 0x000007FF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW__BANDWIDTH___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW___M 0x03FF07FF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW (0x00BD08A0) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL3___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL2___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL1___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL0___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL3___M 0x0F000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL3___S 24 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL2___M 0x000F0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL2___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL1___M 0x00000F00 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL1___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL0___M 0x0000000F +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL0___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW___M 0x0F0F0F0F +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW (0x00BD0900) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW___POR 0x00081500 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW__UNITTYPEID___POR 0x08 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW__UNITCONFID___POR 0x1500 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW__UNITTYPEID___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW__UNITCONFID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW___M 0x00FFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_HIGH (0x00BD0904) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_HIGH__QNOCID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_HIGH___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW (0x00BD0908) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__URGDELAY___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__DFLTPRIORITY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__STOP___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__SHAPEREN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__BWLIMITEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__URGDELAY___M 0x00003F00 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__URGDELAY___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__DFLTPRIORITY___M 0x00000030 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__DFLTPRIORITY___S 4 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__STOP___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__STOP___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__SHAPEREN___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__SHAPEREN___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__BWLIMITEN___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__BWLIMITEN___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW___M 0x00003F37 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW (0x00BD0910) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW___POR 0x00F00000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___POR 0x0F0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW__PENDING___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___M 0x0FFF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW__PENDING___M 0x0000007F +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW__PENDING___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW___M 0x0FFF007F +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW (0x00BD0918) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW__SATURATION___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW__BANDWIDTH___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW__SATURATION___M 0x03FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW__SATURATION___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW__BANDWIDTH___M 0x000007FF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW__BANDWIDTH___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW___M 0x03FF07FF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW (0x00BD0920) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL3___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL2___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL1___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL0___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL3___M 0x3F000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL3___S 24 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL2___M 0x003F0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL2___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL1___M 0x00003F00 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL1___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL0___M 0x0000003F +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL0___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW___M 0x3F3F3F3F +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW (0x00BD0940) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__HIGHPRIORITY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__LOWPRIORITY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__WREN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__RDEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__HIGHPRIORITY___M 0x00003000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__HIGHPRIORITY___S 12 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__LOWPRIORITY___M 0x00000300 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__LOWPRIORITY___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__WREN___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__WREN___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__RDEN___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__RDEN___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW___M 0x00003303 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW (0x00BD0948) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW___POR 0x00800199 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW__SATURATION___POR 0x080 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW__BANDWIDTH___POR 0x199 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW__SATURATION___M 0x03FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW__SATURATION___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW__BANDWIDTH___M 0x000007FF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW__BANDWIDTH___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW___M 0x03FF07FF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW (0x00BD0950) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__HIGHPRIORITY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__LOWPRIORITY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__WREN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__RDEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__HIGHPRIORITY___M 0x00003000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__HIGHPRIORITY___S 12 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__LOWPRIORITY___M 0x00000300 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__LOWPRIORITY___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__WREN___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__WREN___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__RDEN___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__RDEN___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW___M 0x00003303 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW (0x00BD0958) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW___POR 0x00800199 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW__SATURATION___POR 0x080 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW__BANDWIDTH___POR 0x199 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW__SATURATION___M 0x03FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW__SATURATION___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW__BANDWIDTH___M 0x000007FF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW__BANDWIDTH___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW___M 0x03FF07FF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_LOW (0x00BD1000) +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_LOW___POR 0x000CE93B +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_LOW__UNITTYPEID___POR 0x0C +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_LOW__UNITCONFID___POR 0xE93B +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_LOW__UNITTYPEID___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_LOW__UNITCONFID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_LOW___M 0x00FFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_HIGH (0x00BD1004) +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_HIGH__QNOCID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_HIGH___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_SWID_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_ATBEN_LOW (0x00BD1008) +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_ATBEN_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_ATBEN_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_ATBEN_LOW__ATBEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_ATBEN_LOW__ATBEN___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_ATBEN_LOW__ATBEN___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_ATBEN_LOW___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_ATBEN_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_ATBID_LOW (0x00BD1010) +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_ATBID_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_ATBID_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_ATBID_LOW__ATBID___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_ATBID_LOW__ATBID___M 0x0000007F +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_ATBID_LOW__ATBID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_ATBID_LOW___M 0x0000007F +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_ATBID_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_SYNCOUTPERIOD_LOW (0x00BD1018) +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_SYNCOUTPERIOD_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_SYNCOUTPERIOD_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_SYNCOUTPERIOD_LOW__SYNCOUTPERIOD___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_SYNCOUTPERIOD_LOW__SYNCOUTPERIOD___M 0x000003FF +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_SYNCOUTPERIOD_LOW__SYNCOUTPERIOD___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_SYNCOUTPERIOD_LOW___M 0x000003FF +#define DBG_UNOC_UMAC_NOC_FABRIC_STP_SYNCOUTPERIOD_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW (0x00BD1400) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW___POR 0x0003DBB2 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW__UNITTYPEID___POR 0x03 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW__UNITCONFID___POR 0xDBB2 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW__UNITTYPEID___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW__UNITCONFID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW___M 0x00FFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_HIGH (0x00BD1404) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_HIGH__QNOCID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_HIGH___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW (0x00BD1408) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__SCALEEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__DUMPEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__MODE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___M 0x00000300 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___S 5 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___M 0x00000010 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___S 4 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__SCALEEN___M 0x00000008 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__SCALEEN___S 3 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__DUMPEN___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__DUMPEN___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__MODE___M 0x00000003 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__MODE___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW___M 0x0000033F +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPGO_LOW (0x00BD1410) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPGO_LOW___RWC QCSR_REG_WO +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPGO_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPGO_LOW__DUMPGO___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPGO_LOW__DUMPGO___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPGO_LOW__DUMPGO___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPGO_LOW___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPGO_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPTHR_LOW (0x00BD1418) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPTHR_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPTHR_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPTHR_LOW__DUMPTHR___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPTHR_LOW__DUMPTHR___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPTHR_LOW__DUMPTHR___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPTHR_LOW___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPTHR_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW (0x00BD1420) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW___POR 0x00F00000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__NOMINALFREQ___POR 0x0F0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__OFFSET___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__WIDTH___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__NOMINALFREQ___M 0x0FFF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__NOMINALFREQ___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__OFFSET___M 0x0000FF00 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__OFFSET___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__WIDTH___M 0x000000FF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__WIDTH___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW___M 0x0FFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_LOW (0x00BD1428) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_LOW__LATSUM___POR 0x0000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_LOW__LATSUM___M 0x0FFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_LOW__LATSUM___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_LOW___M 0x0FFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_HIGH (0x00BD142C) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_HIGH___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_HIGH__TRCNT___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_HIGH__TRCNT___M 0x000FFF00 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_HIGH__TRCNT___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_HIGH___M 0x000FFF00 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_HIGH___S 8 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN0_LOW (0x00BD1440) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN0_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN0_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN0_LOW__HISTBIN0___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN0_LOW__HISTBIN0___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN0_LOW__HISTBIN0___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN0_LOW___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN0_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN1_LOW (0x00BD1448) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN1_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN1_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN1_LOW__HISTBIN1___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN1_LOW__HISTBIN1___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN1_LOW__HISTBIN1___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN1_LOW___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN1_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN2_LOW (0x00BD1450) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN2_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN2_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN2_LOW__HISTBIN2___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN2_LOW__HISTBIN2___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN2_LOW__HISTBIN2___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN2_LOW___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN2_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN3_LOW (0x00BD1458) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN3_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN3_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN3_LOW__HISTBIN3___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN3_LOW__HISTBIN3___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN3_LOW__HISTBIN3___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN3_LOW___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN3_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN4_LOW (0x00BD1460) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN4_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN4_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN4_LOW__HISTBIN4___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN4_LOW__HISTBIN4___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN4_LOW__HISTBIN4___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN4_LOW___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN4_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN5_LOW (0x00BD1468) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN5_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN5_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN5_LOW__HISTBIN5___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN5_LOW__HISTBIN5___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN5_LOW__HISTBIN5___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN5_LOW___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN5_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN6_LOW (0x00BD1470) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN6_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN6_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN6_LOW__HISTBIN6___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN6_LOW__HISTBIN6___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN6_LOW__HISTBIN6___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN6_LOW___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN6_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN7_LOW (0x00BD1478) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN7_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN7_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN7_LOW__HISTBIN7___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN7_LOW__HISTBIN7___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN7_LOW__HISTBIN7___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN7_LOW___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN7_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_LATMAX_LOW (0x00BD1480) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_LATMAX_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_LATMAX_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_LATMAX_LOW__LATMAX___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_LATMAX_LOW__LATMAX___M 0x000000FF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_LATMAX_LOW__LATMAX___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_LATMAX_LOW___M 0x000000FF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_LATMAX_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW (0x00BD1520) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___POR 0x000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFC00 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___S 10 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW___M 0xFFFFFC00 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW___S 10 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH (0x00BD1524) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW (0x00BD1528) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___POR 0x000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFC00 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___S 10 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW___M 0xFFFFFC00 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW___S 10 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH (0x00BD152C) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW (0x00BD1538) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__CMEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__WREN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__RDEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___M 0x00000010 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___S 4 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__CMEN___M 0x00000008 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__CMEN___S 3 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__WREN___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__WREN___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__RDEN___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__RDEN___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW (0x00BD1600) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW___POR 0x0003CB09 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW__UNITTYPEID___POR 0x03 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW__UNITCONFID___POR 0xCB09 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW__UNITTYPEID___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW__UNITCONFID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW___M 0x00FFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_HIGH (0x00BD1604) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_HIGH__QNOCID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_HIGH___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW (0x00BD1608) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__SCALEEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__DUMPEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__MODE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___M 0x00000300 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___S 5 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___M 0x00000010 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___S 4 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__SCALEEN___M 0x00000008 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__SCALEEN___S 3 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__DUMPEN___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__DUMPEN___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__MODE___M 0x00000003 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__MODE___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW___M 0x0000033F +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPGO_LOW (0x00BD1610) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPGO_LOW___RWC QCSR_REG_WO +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPGO_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPGO_LOW__DUMPGO___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPGO_LOW__DUMPGO___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPGO_LOW__DUMPGO___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPGO_LOW___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPGO_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPTHR_LOW (0x00BD1618) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPTHR_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPTHR_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPTHR_LOW__DUMPTHR___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPTHR_LOW__DUMPTHR___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPTHR_LOW__DUMPTHR___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPTHR_LOW___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPTHR_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW (0x00BD1620) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW___POR 0x00F00000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__NOMINALFREQ___POR 0x0F0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__OFFSET___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__WIDTH___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__NOMINALFREQ___M 0x0FFF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__NOMINALFREQ___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__OFFSET___M 0x0000FF00 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__OFFSET___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__WIDTH___M 0x000000FF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__WIDTH___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW___M 0x0FFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_LOW (0x00BD1628) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_LOW__LATSUM___POR 0x0000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_LOW__LATSUM___M 0x0FFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_LOW__LATSUM___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_LOW___M 0x0FFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_HIGH (0x00BD162C) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_HIGH___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_HIGH__TRCNT___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_HIGH__TRCNT___M 0x000FFF00 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_HIGH__TRCNT___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_HIGH___M 0x000FFF00 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_HIGH___S 8 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN0_LOW (0x00BD1640) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN0_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN0_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN0_LOW__HISTBIN0___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN0_LOW__HISTBIN0___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN0_LOW__HISTBIN0___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN0_LOW___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN0_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN1_LOW (0x00BD1648) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN1_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN1_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN1_LOW__HISTBIN1___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN1_LOW__HISTBIN1___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN1_LOW__HISTBIN1___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN1_LOW___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN1_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN2_LOW (0x00BD1650) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN2_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN2_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN2_LOW__HISTBIN2___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN2_LOW__HISTBIN2___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN2_LOW__HISTBIN2___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN2_LOW___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN2_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN3_LOW (0x00BD1658) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN3_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN3_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN3_LOW__HISTBIN3___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN3_LOW__HISTBIN3___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN3_LOW__HISTBIN3___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN3_LOW___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN3_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN4_LOW (0x00BD1660) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN4_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN4_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN4_LOW__HISTBIN4___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN4_LOW__HISTBIN4___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN4_LOW__HISTBIN4___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN4_LOW___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN4_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN5_LOW (0x00BD1668) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN5_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN5_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN5_LOW__HISTBIN5___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN5_LOW__HISTBIN5___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN5_LOW__HISTBIN5___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN5_LOW___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN5_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN6_LOW (0x00BD1670) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN6_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN6_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN6_LOW__HISTBIN6___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN6_LOW__HISTBIN6___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN6_LOW__HISTBIN6___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN6_LOW___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN6_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN7_LOW (0x00BD1678) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN7_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN7_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN7_LOW__HISTBIN7___POR 0x000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN7_LOW__HISTBIN7___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN7_LOW__HISTBIN7___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN7_LOW___M 0x00000FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN7_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_LATMAX_LOW (0x00BD1680) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_LATMAX_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_LATMAX_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_LATMAX_LOW__LATMAX___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_LATMAX_LOW__LATMAX___M 0x000000FF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_LATMAX_LOW__LATMAX___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_LATMAX_LOW___M 0x000000FF +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_LATMAX_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_LOW (0x00BD1720) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___POR 0x000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFC00 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___S 10 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_LOW___M 0xFFFFFC00 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_LOW___S 10 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_HIGH (0x00BD1724) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_HIGH___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_HIGH___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_HIGH___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_LOW (0x00BD1728) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___POR 0x000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFC00 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___S 10 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_LOW___M 0xFFFFFC00 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_LOW___S 10 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_HIGH (0x00BD172C) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_HIGH___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_HIGH___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_HIGH___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW (0x00BD1738) +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__CMEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__WREN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__RDEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___M 0x00000010 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___S 4 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__CMEN___M 0x00000008 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__CMEN___S 3 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__WREN___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__WREN___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__RDEN___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__RDEN___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW (0x00BD2000) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW___POR 0x00122752 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW__UNITTYPEID___POR 0x12 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW__UNITCONFID___POR 0x2752 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW__UNITTYPEID___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW__UNITCONFID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW___M 0x00FFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_HIGH (0x00BD2004) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_HIGH__QNOCID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_HIGH___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW (0x00BD2008) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__DUMPFORMAT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__ALARMEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__DUMPEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__GLBEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__IGNORECTITRIGIN0___S 5 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__DUMPFORMAT___M 0x00000008 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__DUMPFORMAT___S 3 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__ALARMEN___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__ALARMEN___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__DUMPEN___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__DUMPEN___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__GLBEN___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__GLBEN___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW___M 0x0000002F +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW (0x00BD2010) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW__PLA___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW__FILTER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW__PLA___M 0x80000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW__PLA___S 31 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW__FILTER___M 0x00000003 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW__FILTER___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW___M 0x80000003 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW (0x00BD2018) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW__PLA___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW__FILTER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW__PLA___M 0x80000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW__PLA___S 31 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW__FILTER___M 0x00000003 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW__FILTER___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW___M 0x80000003 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW (0x00BD2020) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW___RWC QCSR_REG_WO +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW__PLA___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW__FILTER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW__PLA___M 0x80000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW__PLA___S 31 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW__FILTER___M 0x00000003 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW__FILTER___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW___M 0x80000003 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW (0x00BD2028) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW__PLA___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW__FILTER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW__PLA___M 0x80000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW__PLA___S 31 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW__FILTER___M 0x00000003 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW__FILTER___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW___M 0x80000003 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_LOW (0x00BD2120) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___POR 0x0000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFFC0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___S 6 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_LOW___M 0xFFFFFFC0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_LOW___S 6 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH (0x00BD2124) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_LOW (0x00BD2128) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___POR 0x0000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFFC0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___S 6 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_LOW___M 0xFFFFFFC0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_LOW___S 6 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH (0x00BD212C) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW (0x00BD2138) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__ATOMEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__CMEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__EXCLEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__WREN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__RDEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__ATOMEN___M 0x00000010 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__ATOMEN___S 4 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__CMEN___M 0x00000008 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__CMEN___S 3 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__EXCLEN___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__EXCLEN___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__WREN___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__WREN___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__RDEN___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__RDEN___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_LOW (0x00BD2220) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___POR 0x0000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFFC0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___S 6 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_LOW___M 0xFFFFFFC0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_LOW___S 6 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH (0x00BD2224) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_LOW (0x00BD2228) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___POR 0x0000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFFC0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___S 6 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_LOW___M 0xFFFFFFC0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_LOW___S 6 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH (0x00BD222C) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW (0x00BD2238) +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__ATOMEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__CMEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__EXCLEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__WREN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__RDEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__ATOMEN___M 0x00000010 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__ATOMEN___S 4 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__CMEN___M 0x00000008 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__CMEN___S 3 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__EXCLEN___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__EXCLEN___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__WREN___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__WREN___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__RDEN___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__RDEN___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_LOW (0x00BD3000) +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_LOW___POR 0x00023E6C +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_LOW__UNITTYPEID___POR 0x02 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_LOW__UNITCONFID___POR 0x3E6C +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_LOW__UNITTYPEID___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_LOW__UNITCONFID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_LOW___M 0x00FFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_HIGH (0x00BD3004) +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_HIGH__QNOCID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_HIGH___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_SWID_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW (0x00BD3008) +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__DUMPEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__GLBEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__IGNORECTITRIGIN0___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__DUMPEN___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__DUMPEN___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__GLBEN___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__GLBEN___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW___M 0x00000007 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPGO_LOW (0x00BD3010) +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPGO_LOW___RWC QCSR_REG_WO +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPGO_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPGO_LOW__DUMPGO___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPGO_LOW__DUMPGO___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPGO_LOW__DUMPGO___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPGO_LOW___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPGO_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPPERIOD_LOW (0x00BD3018) +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPPERIOD_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPPERIOD_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPPERIOD_LOW__DUMPPERIOD___POR 0x00 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPPERIOD_LOW__DUMPPERIOD___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPPERIOD_LOW__DUMPPERIOD___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPPERIOD_LOW___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPPERIOD_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPTHR_LOW (0x00BD3020) +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPTHR_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPTHR_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPTHR_LOW__DUMPTHR___POR 0x0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPTHR_LOW__DUMPTHR___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPTHR_LOW__DUMPTHR___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPTHR_LOW___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_DUMPTHR_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMMIN_LOW (0x00BD3028) +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMMIN_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMMIN_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMMIN_LOW__ALARMMIN___POR 0x0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMMIN_LOW__ALARMMIN___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMMIN_LOW__ALARMMIN___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMMIN_LOW___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMMIN_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMMAX_LOW (0x00BD3030) +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMMAX_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMMAX_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMMAX_LOW__ALARMMAX___POR 0x0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMMAX_LOW__ALARMMAX___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMMAX_LOW__ALARMMAX___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMMAX_LOW___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMMAX_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMSTATUS_LOW (0x00BD3038) +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMSTATUS_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMSTATUS_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMSTATUS_LOW__ALARMSTATUS___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMSTATUS_LOW__ALARMSTATUS___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMSTATUS_LOW__ALARMSTATUS___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMSTATUS_LOW___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMSTATUS_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMCLR_LOW (0x00BD3040) +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMCLR_LOW___RWC QCSR_REG_WO +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMCLR_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMCLR_LOW__ALARMCLR___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMCLR_LOW__ALARMCLR___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMCLR_LOW__ALARMCLR___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMCLR_LOW___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMCLR_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMEN_LOW (0x00BD3048) +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMEN_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMEN_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMEN_LOW__ALARMEN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMEN_LOW__ALARMEN___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMEN_LOW__ALARMEN___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMEN_LOW___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_ALARMEN_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW (0x00BD3100) +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW___POR 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__ALARMMODE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__DUMPTHREN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__EVENTSRC___POR 0x1F +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__ALARMMODE___M 0x00000600 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__ALARMMODE___S 9 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__DUMPTHREN___M 0x00000100 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__DUMPTHREN___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__EVENTSRC___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__EVENTSRC___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW___M 0x0000071F +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0VAL_LOW (0x00BD3140) +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0VAL_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0VAL_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0VAL_LOW__COUNTER0VAL___POR 0x0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0VAL_LOW__COUNTER0VAL___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0VAL_LOW__COUNTER0VAL___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0VAL_LOW___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER0VAL_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW (0x00BD3180) +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW___POR 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__ALARMMODE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__DUMPTHREN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__EVENTSRC___POR 0x1F +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__ALARMMODE___M 0x00000600 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__ALARMMODE___S 9 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__DUMPTHREN___M 0x00000100 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__DUMPTHREN___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__EVENTSRC___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__EVENTSRC___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW___M 0x0000071F +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1VAL_LOW (0x00BD31C0) +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1VAL_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1VAL_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1VAL_LOW__COUNTER1VAL___POR 0x0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1VAL_LOW__COUNTER1VAL___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1VAL_LOW__COUNTER1VAL___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1VAL_LOW___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER1VAL_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW (0x00BD3200) +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW___POR 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__ALARMMODE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__DUMPTHREN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__EVENTSRC___POR 0x1F +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__ALARMMODE___M 0x00000600 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__ALARMMODE___S 9 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__DUMPTHREN___M 0x00000100 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__DUMPTHREN___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__EVENTSRC___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__EVENTSRC___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW___M 0x0000071F +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2VAL_LOW (0x00BD3240) +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2VAL_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2VAL_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2VAL_LOW__COUNTER2VAL___POR 0x0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2VAL_LOW__COUNTER2VAL___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2VAL_LOW__COUNTER2VAL___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2VAL_LOW___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER2VAL_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW (0x00BD3280) +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW___POR 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__ALARMMODE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__DUMPTHREN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__EVENTSRC___POR 0x1F +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__ALARMMODE___M 0x00000600 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__ALARMMODE___S 9 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__DUMPTHREN___M 0x00000100 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__DUMPTHREN___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__EVENTSRC___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__EVENTSRC___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW___M 0x0000071F +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3VAL_LOW (0x00BD32C0) +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3VAL_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3VAL_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3VAL_LOW__COUNTER3VAL___POR 0x0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3VAL_LOW__COUNTER3VAL___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3VAL_LOW__COUNTER3VAL___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3VAL_LOW___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER3VAL_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW (0x00BD3300) +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW___POR 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__ALARMMODE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__DUMPTHREN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__EVENTSRC___POR 0x1F +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__ALARMMODE___M 0x00000600 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__ALARMMODE___S 9 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__DUMPTHREN___M 0x00000100 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__DUMPTHREN___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__EVENTSRC___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__EVENTSRC___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW___M 0x0000071F +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4VAL_LOW (0x00BD3340) +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4VAL_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4VAL_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4VAL_LOW__COUNTER4VAL___POR 0x0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4VAL_LOW__COUNTER4VAL___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4VAL_LOW__COUNTER4VAL___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4VAL_LOW___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER4VAL_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW (0x00BD3380) +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW___POR 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__ALARMMODE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__DUMPTHREN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__EVENTSRC___POR 0x1F +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__ALARMMODE___M 0x00000600 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__ALARMMODE___S 9 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__DUMPTHREN___M 0x00000100 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__DUMPTHREN___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__EVENTSRC___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__EVENTSRC___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW___M 0x0000071F +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5VAL_LOW (0x00BD33C0) +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5VAL_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5VAL_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5VAL_LOW__COUNTER5VAL___POR 0x0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5VAL_LOW__COUNTER5VAL___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5VAL_LOW__COUNTER5VAL___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5VAL_LOW___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER5VAL_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW (0x00BD3400) +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW___POR 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__ALARMMODE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__DUMPTHREN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__EVENTSRC___POR 0x1F +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__ALARMMODE___M 0x00000600 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__ALARMMODE___S 9 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__DUMPTHREN___M 0x00000100 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__DUMPTHREN___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__EVENTSRC___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__EVENTSRC___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW___M 0x0000071F +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6VAL_LOW (0x00BD3440) +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6VAL_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6VAL_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6VAL_LOW__COUNTER6VAL___POR 0x0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6VAL_LOW__COUNTER6VAL___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6VAL_LOW__COUNTER6VAL___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6VAL_LOW___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER6VAL_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW (0x00BD3480) +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW___RWC QCSR_REG_RW +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW___POR 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__ALARMMODE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__DUMPTHREN___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__EVENTSRC___POR 0x1F +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__ALARMMODE___M 0x00000600 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__ALARMMODE___S 9 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__DUMPTHREN___M 0x00000100 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__DUMPTHREN___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__EVENTSRC___M 0x0000001F +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__EVENTSRC___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW___M 0x0000071F +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7VAL_LOW (0x00BD34C0) +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7VAL_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7VAL_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7VAL_LOW__COUNTER7VAL___POR 0x0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7VAL_LOW__COUNTER7VAL___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7VAL_LOW__COUNTER7VAL___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7VAL_LOW___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_EC_COUNTER7VAL_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW (0x00BD4000) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW___POR 0x000EF0EA +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW__UNITTYPEID___POR 0x0E +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW__UNITCONFID___POR 0xF0EA +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW__UNITTYPEID___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW__UNITCONFID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW___M 0x00FFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_HIGH (0x00BD4004) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_HIGH__QNOCID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_HIGH___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW (0x00BD4100) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__TRPENDING___S 12 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_XFER___S 11 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PXFER___S 10 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PWAIT___S 9 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PBUSY___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_IDLE___S 7 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_BUSY___S 6 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_XFER___S 5 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PXFER___S 4 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PWAIT___S 3 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PBUSY___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_IDLE___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_BUSY___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW___M 0x00001FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW (0x00BD4200) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW___POR 0x000EF0EA +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW__UNITTYPEID___POR 0x0E +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW__UNITCONFID___POR 0xF0EA +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW__UNITTYPEID___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW__UNITCONFID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW___M 0x00FFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_HIGH (0x00BD4204) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_HIGH__QNOCID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_HIGH___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW (0x00BD4300) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__TRPENDING___S 12 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_XFER___S 11 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PXFER___S 10 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PWAIT___S 9 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PBUSY___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_IDLE___S 7 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_BUSY___S 6 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_XFER___S 5 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PXFER___S 4 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PWAIT___S 3 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PBUSY___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_IDLE___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_BUSY___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW___M 0x00001FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW (0x00BD4400) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW___POR 0x000EF0EA +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW__UNITTYPEID___POR 0x0E +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW__UNITCONFID___POR 0xF0EA +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW__UNITTYPEID___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW__UNITCONFID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW___M 0x00FFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_HIGH (0x00BD4404) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_HIGH__QNOCID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_HIGH___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW (0x00BD4500) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__TRPENDING___S 12 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_XFER___S 11 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PXFER___S 10 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PWAIT___S 9 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PBUSY___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_IDLE___S 7 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_BUSY___S 6 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_XFER___S 5 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PXFER___S 4 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PWAIT___S 3 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PBUSY___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_IDLE___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_BUSY___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW___M 0x00001FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW (0x00BD4600) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW___POR 0x000EF0EA +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW__UNITTYPEID___POR 0x0E +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW__UNITCONFID___POR 0xF0EA +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW__UNITTYPEID___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW__UNITCONFID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW___M 0x00FFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_HIGH (0x00BD4604) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_HIGH__QNOCID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_HIGH___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW (0x00BD4700) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__TRPENDING___S 12 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_XFER___S 11 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PXFER___S 10 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PWAIT___S 9 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PBUSY___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_IDLE___S 7 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_BUSY___S 6 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_XFER___S 5 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PXFER___S 4 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PWAIT___S 3 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PBUSY___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_IDLE___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_BUSY___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW___M 0x00001FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW (0x00BD4A00) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW___POR 0x000EF0EA +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW__UNITTYPEID___POR 0x0E +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW__UNITCONFID___POR 0xF0EA +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW__UNITTYPEID___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW__UNITCONFID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW___M 0x00FFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_HIGH (0x00BD4A04) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_HIGH__QNOCID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_HIGH___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW (0x00BD4B00) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__TRPENDING___S 12 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_XFER___S 11 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PXFER___S 10 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PWAIT___S 9 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PBUSY___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_IDLE___S 7 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_BUSY___S 6 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_XFER___S 5 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PXFER___S 4 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PWAIT___S 3 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PBUSY___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_IDLE___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_BUSY___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW___M 0x00001FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW (0x00BD4C00) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW___POR 0x000EF0EA +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW__UNITTYPEID___POR 0x0E +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW__UNITCONFID___POR 0xF0EA +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW__UNITTYPEID___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW__UNITCONFID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW___M 0x00FFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_HIGH (0x00BD4C04) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_HIGH__QNOCID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_HIGH___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW (0x00BD4D00) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__TRPENDING___S 12 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_XFER___S 11 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PXFER___S 10 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PWAIT___S 9 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PBUSY___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_IDLE___S 7 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_BUSY___S 6 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_XFER___S 5 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PXFER___S 4 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PWAIT___S 3 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PBUSY___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_IDLE___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_BUSY___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW___M 0x00001FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW (0x00BD5000) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW___POR 0x000EF0EA +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW__UNITTYPEID___POR 0x0E +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW__UNITCONFID___POR 0xF0EA +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW__UNITTYPEID___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW__UNITCONFID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW___M 0x00FFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_HIGH (0x00BD5004) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_HIGH__QNOCID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_HIGH___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW (0x00BD5100) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__TRPENDING___S 12 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_XFER___S 11 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PXFER___S 10 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PWAIT___S 9 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PBUSY___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_IDLE___S 7 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_BUSY___S 6 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_XFER___S 5 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PXFER___S 4 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PWAIT___S 3 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PBUSY___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_IDLE___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_BUSY___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW___M 0x00001FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW (0x00BD5400) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW___POR 0x000E533C +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW__UNITTYPEID___POR 0x0E +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW__UNITCONFID___POR 0x533C +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW__UNITTYPEID___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW__UNITCONFID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW___M 0x00FFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_HIGH (0x00BD5404) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_HIGH__QNOCID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_HIGH___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW (0x00BD5500) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__COEX_APB2AXI_NOPX___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__COEX_APB2AXI_NOPX___M 0x00002000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__COEX_APB2AXI_NOPX___S 13 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__TRPENDING___S 12 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_XFER___S 11 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PXFER___S 10 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PWAIT___S 9 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PBUSY___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_IDLE___S 7 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_BUSY___S 6 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_XFER___S 5 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PXFER___S 4 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PWAIT___S 3 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PBUSY___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_IDLE___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_BUSY___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW___M 0x00003FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW (0x00BD5600) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW___POR 0x000E4249 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW__UNITTYPEID___POR 0x0E +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW__UNITCONFID___POR 0x4249 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW__UNITTYPEID___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW__UNITCONFID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW___M 0x00FFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_HIGH (0x00BD5604) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_HIGH__QNOCID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_HIGH___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW (0x00BD5700) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWREADY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWVALID___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_5___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_4___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_3___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_2___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_1___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_0___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARREADY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARVALID___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_5___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_4___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_3___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_2___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_1___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_0___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWREADY___M 0x80000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWREADY___S 31 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWVALID___M 0x40000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWVALID___S 30 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_5___M 0x20000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_5___S 29 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_4___M 0x10000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_4___S 28 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_3___M 0x08000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_3___S 27 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_2___M 0x04000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_2___S 26 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_1___M 0x02000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_1___S 25 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_0___M 0x01000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_0___S 24 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARREADY___M 0x00800000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARREADY___S 23 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARVALID___M 0x00400000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARVALID___S 22 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_5___M 0x00200000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_5___S 21 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_4___M 0x00100000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_4___S 20 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_3___M 0x00080000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_3___S 19 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_2___M 0x00040000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_2___S 18 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_1___M 0x00020000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_1___S 17 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_0___M 0x00010000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_0___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__TRPENDING___S 12 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_XFER___S 11 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PXFER___S 10 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PWAIT___S 9 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PBUSY___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_IDLE___S 7 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_BUSY___S 6 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_XFER___S 5 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PXFER___S 4 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PWAIT___S 3 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PBUSY___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_IDLE___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_BUSY___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW___M 0xFFFF1FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH (0x00BD5704) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BREADY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BVALID___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_5___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_4___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_3___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_2___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_1___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_0___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__WREADY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__WVALID___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RREADY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RVALID___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_5___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_4___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_3___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_2___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_1___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_0___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BREADY___M 0x00800000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BREADY___S 23 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BVALID___M 0x00400000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BVALID___S 22 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_5___M 0x00200000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_5___S 21 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_4___M 0x00100000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_4___S 20 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_3___M 0x00080000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_3___S 19 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_2___M 0x00040000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_2___S 18 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_1___M 0x00020000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_1___S 17 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_0___M 0x00010000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_0___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__WREADY___M 0x00008000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__WREADY___S 15 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__WVALID___M 0x00004000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__WVALID___S 14 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RREADY___M 0x00000080 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RREADY___S 7 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RVALID___M 0x00000040 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RVALID___S 6 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_5___M 0x00000020 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_5___S 5 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_4___M 0x00000010 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_4___S 4 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_3___M 0x00000008 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_3___S 3 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_2___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_2___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_1___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_1___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_0___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_0___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH___M 0x00FFC0FF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW (0x00BD5800) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW___POR 0x000E4249 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW__UNITTYPEID___POR 0x0E +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW__UNITCONFID___POR 0x4249 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW__UNITTYPEID___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW__UNITCONFID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW___M 0x00FFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_HIGH (0x00BD5804) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_HIGH__QNOCID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_HIGH___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW (0x00BD5900) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWREADY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWVALID___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_5___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_4___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_3___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_2___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_1___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_0___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARREADY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARVALID___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_5___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_4___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_3___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_2___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_1___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_0___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWREADY___M 0x80000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWREADY___S 31 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWVALID___M 0x40000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWVALID___S 30 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_5___M 0x20000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_5___S 29 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_4___M 0x10000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_4___S 28 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_3___M 0x08000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_3___S 27 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_2___M 0x04000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_2___S 26 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_1___M 0x02000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_1___S 25 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_0___M 0x01000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_0___S 24 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARREADY___M 0x00800000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARREADY___S 23 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARVALID___M 0x00400000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARVALID___S 22 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_5___M 0x00200000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_5___S 21 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_4___M 0x00100000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_4___S 20 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_3___M 0x00080000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_3___S 19 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_2___M 0x00040000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_2___S 18 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_1___M 0x00020000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_1___S 17 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_0___M 0x00010000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_0___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__TRPENDING___S 12 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_XFER___S 11 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PXFER___S 10 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PWAIT___S 9 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PBUSY___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_IDLE___S 7 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_BUSY___S 6 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_XFER___S 5 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PXFER___S 4 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PWAIT___S 3 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PBUSY___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_IDLE___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_BUSY___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW___M 0xFFFF1FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH (0x00BD5904) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BREADY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BVALID___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_5___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_4___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_3___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_2___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_1___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_0___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__WREADY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__WVALID___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RREADY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RVALID___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_5___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_4___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_3___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_2___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_1___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_0___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BREADY___M 0x00800000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BREADY___S 23 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BVALID___M 0x00400000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BVALID___S 22 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_5___M 0x00200000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_5___S 21 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_4___M 0x00100000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_4___S 20 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_3___M 0x00080000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_3___S 19 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_2___M 0x00040000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_2___S 18 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_1___M 0x00020000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_1___S 17 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_0___M 0x00010000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_0___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__WREADY___M 0x00008000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__WREADY___S 15 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__WVALID___M 0x00004000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__WVALID___S 14 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RREADY___M 0x00000080 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RREADY___S 7 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RVALID___M 0x00000040 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RVALID___S 6 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_5___M 0x00000020 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_5___S 5 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_4___M 0x00000010 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_4___S 4 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_3___M 0x00000008 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_3___S 3 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_2___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_2___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_1___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_1___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_0___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_0___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH___M 0x00FFC0FF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW (0x00BD5A00) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW___POR 0x000E4249 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW__UNITTYPEID___POR 0x0E +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW__UNITCONFID___POR 0x4249 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW__UNITTYPEID___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW__UNITCONFID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW___M 0x00FFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_HIGH (0x00BD5A04) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_HIGH__QNOCID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_HIGH___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW (0x00BD5B00) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWREADY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWVALID___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_5___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_4___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_3___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_2___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_1___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_0___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARREADY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARVALID___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_5___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_4___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_3___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_2___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_1___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_0___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWREADY___M 0x80000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWREADY___S 31 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWVALID___M 0x40000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWVALID___S 30 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_5___M 0x20000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_5___S 29 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_4___M 0x10000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_4___S 28 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_3___M 0x08000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_3___S 27 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_2___M 0x04000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_2___S 26 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_1___M 0x02000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_1___S 25 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_0___M 0x01000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_0___S 24 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARREADY___M 0x00800000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARREADY___S 23 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARVALID___M 0x00400000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARVALID___S 22 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_5___M 0x00200000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_5___S 21 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_4___M 0x00100000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_4___S 20 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_3___M 0x00080000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_3___S 19 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_2___M 0x00040000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_2___S 18 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_1___M 0x00020000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_1___S 17 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_0___M 0x00010000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_0___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__TRPENDING___S 12 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_XFER___S 11 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PXFER___S 10 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PWAIT___S 9 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PBUSY___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_IDLE___S 7 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_BUSY___S 6 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_XFER___S 5 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PXFER___S 4 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PWAIT___S 3 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PBUSY___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_IDLE___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_BUSY___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW___M 0xFFFF1FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH (0x00BD5B04) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BREADY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BVALID___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_5___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_4___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_3___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_2___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_1___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_0___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__WREADY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__WVALID___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RREADY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RVALID___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_5___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_4___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_3___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_2___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_1___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_0___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BREADY___M 0x00800000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BREADY___S 23 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BVALID___M 0x00400000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BVALID___S 22 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_5___M 0x00200000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_5___S 21 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_4___M 0x00100000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_4___S 20 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_3___M 0x00080000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_3___S 19 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_2___M 0x00040000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_2___S 18 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_1___M 0x00020000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_1___S 17 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_0___M 0x00010000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_0___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__WREADY___M 0x00008000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__WREADY___S 15 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__WVALID___M 0x00004000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__WVALID___S 14 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RREADY___M 0x00000080 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RREADY___S 7 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RVALID___M 0x00000040 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RVALID___S 6 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_5___M 0x00000020 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_5___S 5 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_4___M 0x00000010 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_4___S 4 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_3___M 0x00000008 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_3___S 3 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_2___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_2___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_1___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_1___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_0___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_0___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH___M 0x00FFC0FF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW (0x00BD5C00) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW___POR 0x000E4249 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW__UNITTYPEID___POR 0x0E +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW__UNITCONFID___POR 0x4249 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW__UNITTYPEID___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW__UNITCONFID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW___M 0x00FFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_HIGH (0x00BD5C04) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_HIGH__QNOCID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_HIGH___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW (0x00BD5D00) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWREADY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWVALID___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_5___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_4___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_3___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_2___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_1___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_0___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARREADY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARVALID___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_5___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_4___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_3___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_2___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_1___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_0___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWREADY___M 0x80000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWREADY___S 31 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWVALID___M 0x40000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWVALID___S 30 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_5___M 0x20000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_5___S 29 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_4___M 0x10000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_4___S 28 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_3___M 0x08000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_3___S 27 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_2___M 0x04000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_2___S 26 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_1___M 0x02000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_1___S 25 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_0___M 0x01000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_0___S 24 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARREADY___M 0x00800000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARREADY___S 23 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARVALID___M 0x00400000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARVALID___S 22 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_5___M 0x00200000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_5___S 21 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_4___M 0x00100000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_4___S 20 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_3___M 0x00080000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_3___S 19 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_2___M 0x00040000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_2___S 18 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_1___M 0x00020000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_1___S 17 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_0___M 0x00010000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_0___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__TRPENDING___S 12 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_XFER___S 11 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PXFER___S 10 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PWAIT___S 9 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PBUSY___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_IDLE___S 7 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_BUSY___S 6 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_XFER___S 5 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PXFER___S 4 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PWAIT___S 3 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PBUSY___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_IDLE___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_BUSY___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW___M 0xFFFF1FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH (0x00BD5D04) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BREADY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BVALID___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_5___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_4___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_3___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_2___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_1___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_0___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__WREADY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__WVALID___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RREADY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RVALID___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_5___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_4___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_3___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_2___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_1___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_0___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BREADY___M 0x00800000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BREADY___S 23 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BVALID___M 0x00400000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BVALID___S 22 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_5___M 0x00200000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_5___S 21 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_4___M 0x00100000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_4___S 20 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_3___M 0x00080000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_3___S 19 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_2___M 0x00040000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_2___S 18 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_1___M 0x00020000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_1___S 17 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_0___M 0x00010000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_0___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__WREADY___M 0x00008000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__WREADY___S 15 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__WVALID___M 0x00004000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__WVALID___S 14 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RREADY___M 0x00000080 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RREADY___S 7 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RVALID___M 0x00000040 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RVALID___S 6 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_5___M 0x00000020 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_5___S 5 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_4___M 0x00000010 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_4___S 4 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_3___M 0x00000008 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_3___S 3 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_2___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_2___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_1___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_1___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_0___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_0___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH___M 0x00FFC0FF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW (0x00BD5E00) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW___POR 0x000E4249 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW__UNITTYPEID___POR 0x0E +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW__UNITCONFID___POR 0x4249 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW__UNITTYPEID___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW__UNITCONFID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW___M 0x00FFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_HIGH (0x00BD5E04) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_HIGH__QNOCID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_HIGH___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW (0x00BD5F00) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWREADY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWVALID___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_5___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_4___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_3___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_2___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_1___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_0___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARREADY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARVALID___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_5___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_4___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_3___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_2___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_1___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_0___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWREADY___M 0x80000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWREADY___S 31 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWVALID___M 0x40000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWVALID___S 30 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_5___M 0x20000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_5___S 29 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_4___M 0x10000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_4___S 28 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_3___M 0x08000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_3___S 27 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_2___M 0x04000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_2___S 26 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_1___M 0x02000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_1___S 25 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_0___M 0x01000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_0___S 24 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARREADY___M 0x00800000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARREADY___S 23 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARVALID___M 0x00400000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARVALID___S 22 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_5___M 0x00200000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_5___S 21 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_4___M 0x00100000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_4___S 20 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_3___M 0x00080000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_3___S 19 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_2___M 0x00040000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_2___S 18 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_1___M 0x00020000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_1___S 17 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_0___M 0x00010000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_0___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__TRPENDING___S 12 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_XFER___S 11 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PXFER___S 10 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PWAIT___S 9 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PBUSY___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_IDLE___S 7 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_BUSY___S 6 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_XFER___S 5 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PXFER___S 4 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PWAIT___S 3 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PBUSY___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_IDLE___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_BUSY___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW___M 0xFFFF1FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH (0x00BD5F04) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BREADY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BVALID___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_5___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_4___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_3___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_2___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_1___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_0___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__WREADY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__WVALID___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RREADY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RVALID___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_5___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_4___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_3___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_2___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_1___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_0___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BREADY___M 0x00800000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BREADY___S 23 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BVALID___M 0x00400000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BVALID___S 22 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_5___M 0x00200000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_5___S 21 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_4___M 0x00100000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_4___S 20 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_3___M 0x00080000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_3___S 19 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_2___M 0x00040000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_2___S 18 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_1___M 0x00020000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_1___S 17 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_0___M 0x00010000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_0___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__WREADY___M 0x00008000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__WREADY___S 15 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__WVALID___M 0x00004000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__WVALID___S 14 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RREADY___M 0x00000080 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RREADY___S 7 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RVALID___M 0x00000040 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RVALID___S 6 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_5___M 0x00000020 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_5___S 5 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_4___M 0x00000010 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_4___S 4 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_3___M 0x00000008 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_3___S 3 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_2___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_2___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_1___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_1___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_0___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_0___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH___M 0x00FFC0FF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW (0x00BD6200) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW___POR 0x000EF0EA +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW__UNITTYPEID___POR 0x0E +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW__UNITCONFID___POR 0xF0EA +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW__UNITTYPEID___S 16 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW__UNITCONFID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW___M 0x00FFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_HIGH (0x00BD6204) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_HIGH__QNOCID___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_HIGH___M 0xFFFFFFFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_HIGH___S 0 + +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW (0x00BD6300) +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW___POR 0x00000000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__TRPENDING___S 12 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_XFER___S 11 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PXFER___S 10 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PWAIT___S 9 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PBUSY___S 8 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_IDLE___S 7 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_BUSY___S 6 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_XFER___S 5 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PXFER___S 4 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PWAIT___S 3 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PBUSY___S 2 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_IDLE___S 1 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_BUSY___S 0 +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW___M 0x00001FFF +#define DBG_UNOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_LOW (0x00BE0000) +#define DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_LOW___POR 0x00021F1B +#define DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_LOW__UNITTYPEID___POR 0x02 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_LOW__UNITCONFID___POR 0x1F1B +#define DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_LOW__UNITTYPEID___S 16 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_LOW__UNITCONFID___S 0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_LOW___M 0x00FFFFFF +#define DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_HIGH (0x00BE0004) +#define DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_HIGH__QNOCID___S 0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_HIGH___M 0xFFFFFFFF +#define DBG_PHYA_PHYA_NOC_EC_PRB0_SWID_HIGH___S 0 + +#define DBG_PHYA_PHYA_NOC_EC_PRB0_MAINCTL_LOW (0x00BE0008) +#define DBG_PHYA_PHYA_NOC_EC_PRB0_MAINCTL_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_EC_PRB0_MAINCTL_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_MAINCTL_LOW__DUMPEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_MAINCTL_LOW__GLBEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000004 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_MAINCTL_LOW__IGNORECTITRIGIN0___S 2 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_MAINCTL_LOW__DUMPEN___M 0x00000002 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_MAINCTL_LOW__DUMPEN___S 1 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_MAINCTL_LOW__GLBEN___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_MAINCTL_LOW__GLBEN___S 0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_MAINCTL_LOW___M 0x00000007 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_MAINCTL_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPGO_LOW (0x00BE0010) +#define DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPGO_LOW___RWC QCSR_REG_WO +#define DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPGO_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPGO_LOW__DUMPGO___POR 0x0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPGO_LOW__DUMPGO___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPGO_LOW__DUMPGO___S 0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPGO_LOW___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPGO_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPPERIOD_LOW (0x00BE0018) +#define DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPPERIOD_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPPERIOD_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPPERIOD_LOW__DUMPPERIOD___POR 0x00 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPPERIOD_LOW__DUMPPERIOD___M 0x0000001F +#define DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPPERIOD_LOW__DUMPPERIOD___S 0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPPERIOD_LOW___M 0x0000001F +#define DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPPERIOD_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPTHR_LOW (0x00BE0020) +#define DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPTHR_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPTHR_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPTHR_LOW__DUMPTHR___POR 0x0000 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPTHR_LOW__DUMPTHR___M 0x0000FFFF +#define DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPTHR_LOW__DUMPTHR___S 0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPTHR_LOW___M 0x0000FFFF +#define DBG_PHYA_PHYA_NOC_EC_PRB0_DUMPTHR_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMMIN_LOW (0x00BE0028) +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMMIN_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMMIN_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMMIN_LOW__ALARMMIN___POR 0x0000 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMMIN_LOW__ALARMMIN___M 0x0000FFFF +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMMIN_LOW__ALARMMIN___S 0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMMIN_LOW___M 0x0000FFFF +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMMIN_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMMAX_LOW (0x00BE0030) +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMMAX_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMMAX_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMMAX_LOW__ALARMMAX___POR 0x0000 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMMAX_LOW__ALARMMAX___M 0x0000FFFF +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMMAX_LOW__ALARMMAX___S 0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMMAX_LOW___M 0x0000FFFF +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMMAX_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMSTATUS_LOW (0x00BE0038) +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMSTATUS_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMSTATUS_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMSTATUS_LOW__ALARMSTATUS___POR 0x0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMSTATUS_LOW__ALARMSTATUS___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMSTATUS_LOW__ALARMSTATUS___S 0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMSTATUS_LOW___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMSTATUS_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMCLR_LOW (0x00BE0040) +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMCLR_LOW___RWC QCSR_REG_WO +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMCLR_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMCLR_LOW__ALARMCLR___POR 0x0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMCLR_LOW__ALARMCLR___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMCLR_LOW__ALARMCLR___S 0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMCLR_LOW___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMCLR_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMEN_LOW (0x00BE0048) +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMEN_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMEN_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMEN_LOW__ALARMEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMEN_LOW__ALARMEN___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMEN_LOW__ALARMEN___S 0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMEN_LOW___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_ALARMEN_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW (0x00BE0100) +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW___POR 0x0000007F +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__ALARMMODE___POR 0x0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__DUMPTHREN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__EVENTSRC___POR 0x7F +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__ALARMMODE___M 0x00000600 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__ALARMMODE___S 9 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__DUMPTHREN___M 0x00000100 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__DUMPTHREN___S 8 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__EVENTSRC___M 0x0000007F +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW__EVENTSRC___S 0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW___M 0x0000077F +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0CTL_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0VAL_LOW (0x00BE0140) +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0VAL_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0VAL_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0VAL_LOW__COUNTER0VAL___POR 0x0000 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0VAL_LOW__COUNTER0VAL___M 0x0000FFFF +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0VAL_LOW__COUNTER0VAL___S 0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0VAL_LOW___M 0x0000FFFF +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER0VAL_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW (0x00BE0180) +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW___POR 0x0000007F +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__ALARMMODE___POR 0x0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__DUMPTHREN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__EVENTSRC___POR 0x7F +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__ALARMMODE___M 0x00000600 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__ALARMMODE___S 9 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__DUMPTHREN___M 0x00000100 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__DUMPTHREN___S 8 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__EVENTSRC___M 0x0000007F +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW__EVENTSRC___S 0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW___M 0x0000077F +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1CTL_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1VAL_LOW (0x00BE01C0) +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1VAL_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1VAL_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1VAL_LOW__COUNTER1VAL___POR 0x0000 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1VAL_LOW__COUNTER1VAL___M 0x0000FFFF +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1VAL_LOW__COUNTER1VAL___S 0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1VAL_LOW___M 0x0000FFFF +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER1VAL_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW (0x00BE0200) +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW___POR 0x0000007F +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__ALARMMODE___POR 0x0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__DUMPTHREN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__EVENTSRC___POR 0x7F +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__ALARMMODE___M 0x00000600 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__ALARMMODE___S 9 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__DUMPTHREN___M 0x00000100 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__DUMPTHREN___S 8 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__EVENTSRC___M 0x0000007F +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW__EVENTSRC___S 0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW___M 0x0000077F +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2CTL_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2VAL_LOW (0x00BE0240) +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2VAL_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2VAL_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2VAL_LOW__COUNTER2VAL___POR 0x0000 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2VAL_LOW__COUNTER2VAL___M 0x0000FFFF +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2VAL_LOW__COUNTER2VAL___S 0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2VAL_LOW___M 0x0000FFFF +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER2VAL_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW (0x00BE0280) +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW___POR 0x0000007F +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__ALARMMODE___POR 0x0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__DUMPTHREN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__EVENTSRC___POR 0x7F +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__ALARMMODE___M 0x00000600 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__ALARMMODE___S 9 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__DUMPTHREN___M 0x00000100 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__DUMPTHREN___S 8 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__EVENTSRC___M 0x0000007F +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW__EVENTSRC___S 0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW___M 0x0000077F +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3CTL_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3VAL_LOW (0x00BE02C0) +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3VAL_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3VAL_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3VAL_LOW__COUNTER3VAL___POR 0x0000 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3VAL_LOW__COUNTER3VAL___M 0x0000FFFF +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3VAL_LOW__COUNTER3VAL___S 0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3VAL_LOW___M 0x0000FFFF +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER3VAL_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW (0x00BE0300) +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW___POR 0x0000007F +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__ALARMMODE___POR 0x0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__DUMPTHREN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__EVENTSRC___POR 0x7F +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__ALARMMODE___M 0x00000600 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__ALARMMODE___S 9 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__DUMPTHREN___M 0x00000100 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__DUMPTHREN___S 8 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__EVENTSRC___M 0x0000007F +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW__EVENTSRC___S 0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW___M 0x0000077F +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4CTL_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4VAL_LOW (0x00BE0340) +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4VAL_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4VAL_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4VAL_LOW__COUNTER4VAL___POR 0x0000 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4VAL_LOW__COUNTER4VAL___M 0x0000FFFF +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4VAL_LOW__COUNTER4VAL___S 0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4VAL_LOW___M 0x0000FFFF +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER4VAL_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW (0x00BE0380) +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW___POR 0x0000007F +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__ALARMMODE___POR 0x0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__DUMPTHREN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__EVENTSRC___POR 0x7F +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__ALARMMODE___M 0x00000600 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__ALARMMODE___S 9 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__DUMPTHREN___M 0x00000100 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__DUMPTHREN___S 8 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__EVENTSRC___M 0x0000007F +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW__EVENTSRC___S 0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW___M 0x0000077F +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5CTL_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5VAL_LOW (0x00BE03C0) +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5VAL_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5VAL_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5VAL_LOW__COUNTER5VAL___POR 0x0000 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5VAL_LOW__COUNTER5VAL___M 0x0000FFFF +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5VAL_LOW__COUNTER5VAL___S 0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5VAL_LOW___M 0x0000FFFF +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER5VAL_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW (0x00BE0400) +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW___POR 0x0000007F +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__ALARMMODE___POR 0x0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__DUMPTHREN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__EVENTSRC___POR 0x7F +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__ALARMMODE___M 0x00000600 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__ALARMMODE___S 9 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__DUMPTHREN___M 0x00000100 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__DUMPTHREN___S 8 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__EVENTSRC___M 0x0000007F +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW__EVENTSRC___S 0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW___M 0x0000077F +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6CTL_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6VAL_LOW (0x00BE0440) +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6VAL_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6VAL_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6VAL_LOW__COUNTER6VAL___POR 0x0000 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6VAL_LOW__COUNTER6VAL___M 0x0000FFFF +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6VAL_LOW__COUNTER6VAL___S 0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6VAL_LOW___M 0x0000FFFF +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER6VAL_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW (0x00BE0480) +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW___POR 0x0000007F +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__ALARMMODE___POR 0x0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__DUMPTHREN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__EVENTSRC___POR 0x7F +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__ALARMMODE___M 0x00000600 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__ALARMMODE___S 9 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__DUMPTHREN___M 0x00000100 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__DUMPTHREN___S 8 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__EVENTSRC___M 0x0000007F +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW__EVENTSRC___S 0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW___M 0x0000077F +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7CTL_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7VAL_LOW (0x00BE04C0) +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7VAL_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7VAL_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7VAL_LOW__COUNTER7VAL___POR 0x0000 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7VAL_LOW__COUNTER7VAL___M 0x0000FFFF +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7VAL_LOW__COUNTER7VAL___S 0 +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7VAL_LOW___M 0x0000FFFF +#define DBG_PHYA_PHYA_NOC_EC_PRB0_COUNTER7VAL_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_LOW (0x00BE1000) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_LOW___POR 0x001237AA +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_LOW__UNITTYPEID___POR 0x12 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_LOW__UNITCONFID___POR 0x37AA +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_LOW__UNITTYPEID___S 16 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_LOW__UNITCONFID___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_LOW___M 0x00FFFFFF +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_HIGH (0x00BE1004) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_HIGH__QNOCID___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_HIGH___M 0xFFFFFFFF +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_SWID_HIGH___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW (0x00BE1008) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__DUMPFORMAT___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__ALARMEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__DUMPEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__GLBEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__IGNORECTITRIGIN0___S 5 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__DUMPFORMAT___M 0x00000008 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__DUMPFORMAT___S 3 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__ALARMEN___M 0x00000004 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__ALARMEN___S 2 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__DUMPEN___M 0x00000002 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__DUMPEN___S 1 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__GLBEN___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW__GLBEN___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW___M 0x0000002F +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_MAINCTL_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW (0x00BE1010) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW__PLA___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW__FILTER___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW__PLA___M 0x80000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW__PLA___S 31 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW__FILTER___M 0x00000003 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW__FILTER___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW___M 0x80000003 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_EN_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW (0x00BE1018) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW__PLA___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW__FILTER___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW__PLA___M 0x80000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW__PLA___S 31 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW__FILTER___M 0x00000003 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW__FILTER___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW___M 0x80000003 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_STATUS_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW (0x00BE1020) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW___RWC QCSR_REG_WO +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW__PLA___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW__FILTER___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW__PLA___M 0x80000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW__PLA___S 31 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW__FILTER___M 0x00000003 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW__FILTER___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW___M 0x80000003 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ALARM_CLR_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ANDINV_LOW (0x00BE1028) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ANDINV_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ANDINV_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ANDINV_LOW__PLA___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ANDINV_LOW__FILTER___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ANDINV_LOW__PLA___M 0x80000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ANDINV_LOW__PLA___S 31 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ANDINV_LOW__FILTER___M 0x00000003 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ANDINV_LOW__FILTER___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ANDINV_LOW___M 0x80000003 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_ANDINV_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_PORTSEL_LOW (0x00BE1030) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_PORTSEL_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_PORTSEL_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_PORTSEL_LOW__PORTSEL___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_PORTSEL_LOW__PORTSEL___M 0x00000007 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_PORTSEL_LOW__PORTSEL___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_PORTSEL_LOW___M 0x00000007 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_PORTSEL_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_LOW (0x00BE1120) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___POR 0x0000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFFC0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___S 6 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_LOW___M 0xFFFFFFC0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_LOW___S 6 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_HIGH (0x00BE1124) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_HIGH___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_HIGH___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000003F +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_HIGH___M 0x0000003F +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MIN_HIGH___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_LOW (0x00BE1128) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___POR 0x0000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFFC0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___S 6 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_LOW___M 0xFFFFFFC0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_LOW___S 6 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_HIGH (0x00BE112C) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_HIGH___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_HIGH___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000003F +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_HIGH___M 0x0000003F +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_ADDR_MAX_HIGH___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW (0x00BE1138) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__ATOMEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__CMEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__EXCLEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__WREN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__RDEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__ATOMEN___M 0x00000010 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__ATOMEN___S 4 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__CMEN___M 0x00000008 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__CMEN___S 3 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__EXCLEN___M 0x00000004 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__EXCLEN___S 2 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__WREN___M 0x00000002 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__WREN___S 1 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__RDEN___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW__RDEN___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW___M 0x0000001F +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_OPCODE_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW (0x00BE1140) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__FAILEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__RSPEEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__ERREN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__REQRSPEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__FAILEN___M 0x00000008 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__FAILEN___S 3 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__RSPEEN___M 0x00000004 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__RSPEEN___S 2 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__ERREN___M 0x00000002 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__ERREN___S 1 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__REQRSPEN___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW__REQRSPEN___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW___M 0x0000000F +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_STATUS_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_BASE_LOW (0x00BE1178) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_BASE_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_BASE_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_BASE_LOW__FILTERS_0_EXTID_BASE___POR 0x000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_BASE_LOW__FILTERS_0_EXTID_BASE___M 0x000003FF +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_BASE_LOW__FILTERS_0_EXTID_BASE___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_BASE_LOW___M 0x000003FF +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_BASE_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_MASK_LOW (0x00BE1180) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_MASK_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_MASK_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_MASK_LOW__FILTERS_0_EXTID_MASK___POR 0x000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_MASK_LOW__FILTERS_0_EXTID_MASK___M 0x000003FF +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_MASK_LOW__FILTERS_0_EXTID_MASK___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_MASK_LOW___M 0x000003FF +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_EXTID_MASK_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_URGENCY_LOW (0x00BE1190) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_URGENCY_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_URGENCY_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_URGENCY_LOW__FILTERS_0_URGENCY___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_URGENCY_LOW__FILTERS_0_URGENCY___M 0x00000003 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_URGENCY_LOW__FILTERS_0_URGENCY___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_URGENCY_LOW___M 0x00000003 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_0_URGENCY_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_LOW (0x00BE1220) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___POR 0x0000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFFC0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___S 6 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_LOW___M 0xFFFFFFC0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_LOW___S 6 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_HIGH (0x00BE1224) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_HIGH___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_HIGH___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000003F +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_HIGH___M 0x0000003F +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MIN_HIGH___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_LOW (0x00BE1228) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___POR 0x0000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFFC0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___S 6 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_LOW___M 0xFFFFFFC0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_LOW___S 6 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_HIGH (0x00BE122C) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_HIGH___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_HIGH___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000003F +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_HIGH___M 0x0000003F +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_ADDR_MAX_HIGH___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW (0x00BE1238) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__ATOMEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__CMEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__EXCLEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__WREN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__RDEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__ATOMEN___M 0x00000010 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__ATOMEN___S 4 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__CMEN___M 0x00000008 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__CMEN___S 3 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__EXCLEN___M 0x00000004 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__EXCLEN___S 2 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__WREN___M 0x00000002 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__WREN___S 1 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__RDEN___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW__RDEN___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW___M 0x0000001F +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_OPCODE_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW (0x00BE1240) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__FAILEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__RSPEEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__ERREN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__REQRSPEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__FAILEN___M 0x00000008 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__FAILEN___S 3 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__RSPEEN___M 0x00000004 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__RSPEEN___S 2 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__ERREN___M 0x00000002 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__ERREN___S 1 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__REQRSPEN___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW__REQRSPEN___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW___M 0x0000000F +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_STATUS_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_BASE_LOW (0x00BE1278) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_BASE_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_BASE_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_BASE_LOW__FILTERS_1_EXTID_BASE___POR 0x000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_BASE_LOW__FILTERS_1_EXTID_BASE___M 0x000003FF +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_BASE_LOW__FILTERS_1_EXTID_BASE___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_BASE_LOW___M 0x000003FF +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_BASE_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_MASK_LOW (0x00BE1280) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_MASK_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_MASK_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_MASK_LOW__FILTERS_1_EXTID_MASK___POR 0x000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_MASK_LOW__FILTERS_1_EXTID_MASK___M 0x000003FF +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_MASK_LOW__FILTERS_1_EXTID_MASK___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_MASK_LOW___M 0x000003FF +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_EXTID_MASK_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_URGENCY_LOW (0x00BE1290) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_URGENCY_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_URGENCY_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_URGENCY_LOW__FILTERS_1_URGENCY___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_URGENCY_LOW__FILTERS_1_URGENCY___M 0x00000003 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_URGENCY_LOW__FILTERS_1_URGENCY___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_URGENCY_LOW___M 0x00000003 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB0_FILTERS_1_URGENCY_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_LOW (0x00BE1400) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_LOW___POR 0x0012C2E1 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_LOW__UNITTYPEID___POR 0x12 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_LOW__UNITCONFID___POR 0xC2E1 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_LOW__UNITTYPEID___S 16 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_LOW__UNITCONFID___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_LOW___M 0x00FFFFFF +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_HIGH (0x00BE1404) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_HIGH__QNOCID___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_HIGH___M 0xFFFFFFFF +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_SWID_HIGH___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW (0x00BE1408) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__DUMPFORMAT___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__ALARMEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__DUMPEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__GLBEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__IGNORECTITRIGIN0___S 5 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__DUMPFORMAT___M 0x00000008 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__DUMPFORMAT___S 3 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__ALARMEN___M 0x00000004 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__ALARMEN___S 2 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__DUMPEN___M 0x00000002 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__DUMPEN___S 1 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__GLBEN___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW__GLBEN___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW___M 0x0000002F +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_MAINCTL_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW (0x00BE1410) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW__PLA___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW__FILTER___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW__PLA___M 0x80000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW__PLA___S 31 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW__FILTER___M 0x00000003 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW__FILTER___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW___M 0x80000003 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_EN_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW (0x00BE1418) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW__PLA___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW__FILTER___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW__PLA___M 0x80000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW__PLA___S 31 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW__FILTER___M 0x00000003 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW__FILTER___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW___M 0x80000003 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_STATUS_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW (0x00BE1420) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW___RWC QCSR_REG_WO +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW__PLA___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW__FILTER___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW__PLA___M 0x80000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW__PLA___S 31 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW__FILTER___M 0x00000003 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW__FILTER___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW___M 0x80000003 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ALARM_CLR_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW (0x00BE1428) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW__PLA___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW__FILTER___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW__PLA___M 0x80000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW__PLA___S 31 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW__FILTER___M 0x00000003 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW__FILTER___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW___M 0x80000003 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_ANDINV_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_PORTSEL_LOW (0x00BE1430) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_PORTSEL_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_PORTSEL_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_PORTSEL_LOW__PORTSEL___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_PORTSEL_LOW__PORTSEL___M 0x00000007 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_PORTSEL_LOW__PORTSEL___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_PORTSEL_LOW___M 0x00000007 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_PORTSEL_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_LOW (0x00BE1520) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___POR 0x0000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFFC0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___S 6 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_LOW___M 0xFFFFFFC0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_LOW___S 6 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_HIGH (0x00BE1524) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_HIGH___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_HIGH___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000003F +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_HIGH___M 0x0000003F +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MIN_HIGH___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_LOW (0x00BE1528) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___POR 0x0000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFFC0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___S 6 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_LOW___M 0xFFFFFFC0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_LOW___S 6 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_HIGH (0x00BE152C) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_HIGH___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_HIGH___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000003F +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_HIGH___M 0x0000003F +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_ADDR_MAX_HIGH___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW (0x00BE1538) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__ATOMEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__CMEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__EXCLEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__WREN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__RDEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__ATOMEN___M 0x00000010 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__ATOMEN___S 4 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__CMEN___M 0x00000008 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__CMEN___S 3 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__EXCLEN___M 0x00000004 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__EXCLEN___S 2 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__WREN___M 0x00000002 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__WREN___S 1 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__RDEN___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW__RDEN___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW___M 0x0000001F +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_OPCODE_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW (0x00BE1540) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__FAILEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__RSPEEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__ERREN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__REQRSPEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__FAILEN___M 0x00000008 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__FAILEN___S 3 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__RSPEEN___M 0x00000004 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__RSPEEN___S 2 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__ERREN___M 0x00000002 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__ERREN___S 1 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__REQRSPEN___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW__REQRSPEN___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW___M 0x0000000F +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_STATUS_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_BASE_LOW (0x00BE1578) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_BASE_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_BASE_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_BASE_LOW__FILTERS_0_EXTID_BASE___POR 0x000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_BASE_LOW__FILTERS_0_EXTID_BASE___M 0x000003FF +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_BASE_LOW__FILTERS_0_EXTID_BASE___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_BASE_LOW___M 0x000003FF +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_BASE_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_MASK_LOW (0x00BE1580) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_MASK_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_MASK_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_MASK_LOW__FILTERS_0_EXTID_MASK___POR 0x000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_MASK_LOW__FILTERS_0_EXTID_MASK___M 0x000003FF +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_MASK_LOW__FILTERS_0_EXTID_MASK___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_MASK_LOW___M 0x000003FF +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_EXTID_MASK_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_URGENCY_LOW (0x00BE1590) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_URGENCY_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_URGENCY_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_URGENCY_LOW__FILTERS_0_URGENCY___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_URGENCY_LOW__FILTERS_0_URGENCY___M 0x00000003 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_URGENCY_LOW__FILTERS_0_URGENCY___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_URGENCY_LOW___M 0x00000003 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_0_URGENCY_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_LOW (0x00BE1620) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___POR 0x0000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFFC0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___S 6 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_LOW___M 0xFFFFFFC0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_LOW___S 6 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_HIGH (0x00BE1624) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_HIGH___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_HIGH___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000003F +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_HIGH___M 0x0000003F +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MIN_HIGH___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_LOW (0x00BE1628) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___POR 0x0000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFFC0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___S 6 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_LOW___M 0xFFFFFFC0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_LOW___S 6 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_HIGH (0x00BE162C) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_HIGH___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_HIGH___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000003F +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_HIGH___M 0x0000003F +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_ADDR_MAX_HIGH___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW (0x00BE1638) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__ATOMEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__CMEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__EXCLEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__WREN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__RDEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__ATOMEN___M 0x00000010 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__ATOMEN___S 4 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__CMEN___M 0x00000008 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__CMEN___S 3 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__EXCLEN___M 0x00000004 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__EXCLEN___S 2 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__WREN___M 0x00000002 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__WREN___S 1 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__RDEN___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW__RDEN___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW___M 0x0000001F +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_OPCODE_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW (0x00BE1640) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__FAILEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__RSPEEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__ERREN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__REQRSPEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__FAILEN___M 0x00000008 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__FAILEN___S 3 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__RSPEEN___M 0x00000004 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__RSPEEN___S 2 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__ERREN___M 0x00000002 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__ERREN___S 1 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__REQRSPEN___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW__REQRSPEN___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW___M 0x0000000F +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_STATUS_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_BASE_LOW (0x00BE1678) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_BASE_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_BASE_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_BASE_LOW__FILTERS_1_EXTID_BASE___POR 0x000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_BASE_LOW__FILTERS_1_EXTID_BASE___M 0x000003FF +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_BASE_LOW__FILTERS_1_EXTID_BASE___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_BASE_LOW___M 0x000003FF +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_BASE_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_MASK_LOW (0x00BE1680) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_MASK_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_MASK_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_MASK_LOW__FILTERS_1_EXTID_MASK___POR 0x000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_MASK_LOW__FILTERS_1_EXTID_MASK___M 0x000003FF +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_MASK_LOW__FILTERS_1_EXTID_MASK___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_MASK_LOW___M 0x000003FF +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_EXTID_MASK_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_URGENCY_LOW (0x00BE1690) +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_URGENCY_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_URGENCY_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_URGENCY_LOW__FILTERS_1_URGENCY___POR 0x0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_URGENCY_LOW__FILTERS_1_URGENCY___M 0x00000003 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_URGENCY_LOW__FILTERS_1_URGENCY___S 0 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_URGENCY_LOW___M 0x00000003 +#define DBG_PHYA_PHYA_NOC_TRACE_PRB_1_FILTERS_1_URGENCY_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW (0x00BE1800) +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW___POR 0x000341AC +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW__UNITTYPEID___POR 0x03 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW__UNITCONFID___POR 0x41AC +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW__UNITTYPEID___S 16 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW__UNITCONFID___S 0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW___M 0x00FFFFFF +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_HIGH (0x00BE1804) +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_HIGH__QNOCID___S 0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_HIGH___M 0xFFFFFFFF +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_SWID_HIGH___S 0 + +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW (0x00BE1808) +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__SCALEEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__DUMPEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__MODE___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___M 0x00000300 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___S 8 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___S 5 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___M 0x00000010 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___S 4 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__SCALEEN___M 0x00000008 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__SCALEEN___S 3 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__DUMPEN___M 0x00000004 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__DUMPEN___S 2 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__MODE___M 0x00000003 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW__MODE___S 0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW___M 0x0000033F +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_MAINCTL_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_DUMPGO_LOW (0x00BE1810) +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_DUMPGO_LOW___RWC QCSR_REG_WO +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_DUMPGO_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_DUMPGO_LOW__DUMPGO___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_DUMPGO_LOW__DUMPGO___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_DUMPGO_LOW__DUMPGO___S 0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_DUMPGO_LOW___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_DUMPGO_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_DUMPTHR_LOW (0x00BE1818) +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_DUMPTHR_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_DUMPTHR_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_DUMPTHR_LOW__DUMPTHR___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_DUMPTHR_LOW__DUMPTHR___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_DUMPTHR_LOW__DUMPTHR___S 0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_DUMPTHR_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_DUMPTHR_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW (0x00BE1820) +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW___POR 0x01400000 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__NOMINALFREQ___POR 0x140 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__OFFSET___POR 0x00 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__WIDTH___POR 0x00 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__NOMINALFREQ___M 0x0FFF0000 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__NOMINALFREQ___S 16 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__OFFSET___M 0x0000FF00 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__OFFSET___S 8 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__WIDTH___M 0x000000FF +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW__WIDTH___S 0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW___M 0x0FFFFFFF +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_BIN_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_LOW (0x00BE1828) +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_LOW__LATSUM___POR 0x0000000 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_LOW__LATSUM___M 0x0FFFFFFF +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_LOW__LATSUM___S 0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_LOW___M 0x0FFFFFFF +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_HIGH (0x00BE182C) +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_HIGH___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_HIGH___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_HIGH__TRCNT___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_HIGH__TRCNT___M 0x000FFF00 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_HIGH__TRCNT___S 8 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_HIGH___M 0x000FFF00 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_AVLATENCY_HIGH___S 8 + +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN0_LOW (0x00BE1840) +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN0_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN0_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN0_LOW__HISTBIN0___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN0_LOW__HISTBIN0___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN0_LOW__HISTBIN0___S 0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN0_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN0_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN1_LOW (0x00BE1848) +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN1_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN1_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN1_LOW__HISTBIN1___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN1_LOW__HISTBIN1___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN1_LOW__HISTBIN1___S 0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN1_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN1_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN2_LOW (0x00BE1850) +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN2_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN2_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN2_LOW__HISTBIN2___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN2_LOW__HISTBIN2___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN2_LOW__HISTBIN2___S 0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN2_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN2_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN3_LOW (0x00BE1858) +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN3_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN3_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN3_LOW__HISTBIN3___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN3_LOW__HISTBIN3___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN3_LOW__HISTBIN3___S 0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN3_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN3_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN4_LOW (0x00BE1860) +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN4_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN4_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN4_LOW__HISTBIN4___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN4_LOW__HISTBIN4___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN4_LOW__HISTBIN4___S 0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN4_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN4_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN5_LOW (0x00BE1868) +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN5_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN5_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN5_LOW__HISTBIN5___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN5_LOW__HISTBIN5___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN5_LOW__HISTBIN5___S 0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN5_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN5_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN6_LOW (0x00BE1870) +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN6_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN6_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN6_LOW__HISTBIN6___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN6_LOW__HISTBIN6___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN6_LOW__HISTBIN6___S 0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN6_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN6_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN7_LOW (0x00BE1878) +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN7_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN7_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN7_LOW__HISTBIN7___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN7_LOW__HISTBIN7___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN7_LOW__HISTBIN7___S 0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN7_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_HISTBIN7_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_LATMAX_LOW (0x00BE1880) +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_LATMAX_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_LATMAX_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_LATMAX_LOW__LATMAX___POR 0x00 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_LATMAX_LOW__LATMAX___M 0x000000FF +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_LATMAX_LOW__LATMAX___S 0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_LATMAX_LOW___M 0x000000FF +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_LATMAX_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MIN_LOW (0x00BE1920) +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MIN_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MIN_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE___POR 0x000000 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE___M 0xFFFFFC00 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE___S 10 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MIN_LOW___M 0xFFFFFC00 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MIN_LOW___S 10 + +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MAX_LOW (0x00BE1928) +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MAX_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MAX_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE___POR 0x000000 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE___M 0xFFFFFC00 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE___S 10 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MAX_LOW___M 0xFFFFFC00 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_ADDR_MAX_LOW___S 10 + +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW (0x00BE1938) +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__CMEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__WREN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__RDEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___M 0x00000010 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___S 4 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__CMEN___M 0x00000008 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__CMEN___S 3 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___M 0x00000004 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___S 2 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__WREN___M 0x00000002 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__WREN___S 1 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__RDEN___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW__RDEN___S 0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW___M 0x0000001F +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_OPCODE_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW (0x00BE1968) +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__SHAREDEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__CACHEDEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__NORMALEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__DEVEEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__DEVNEEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__SHAREDEN___M 0x00000010 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__SHAREDEN___S 4 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__CACHEDEN___M 0x00000008 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__CACHEDEN___S 3 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__NORMALEN___M 0x00000004 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__NORMALEN___S 2 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__DEVEEN___M 0x00000002 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__DEVEEN___S 1 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__DEVNEEN___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW__DEVNEEN___S 0 +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW___M 0x0000001F +#define DBG_PHYA_PHYA_NOC_QHM_M3_TENUREPRB_FILTER_TRTYPE_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW (0x00BE2000) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW___POR 0x00039006 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW__UNITTYPEID___POR 0x03 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW__UNITCONFID___POR 0x9006 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW__UNITTYPEID___S 16 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW__UNITCONFID___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW___M 0x00FFFFFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_HIGH (0x00BE2004) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_HIGH__QNOCID___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_HIGH___M 0xFFFFFFFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_SWID_HIGH___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW (0x00BE2008) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__SCALEEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__DUMPEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__MODE___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___M 0x00000300 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___S 8 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___S 5 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___M 0x00000010 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___S 4 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__SCALEEN___M 0x00000008 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__SCALEEN___S 3 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__DUMPEN___M 0x00000004 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__DUMPEN___S 2 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__MODE___M 0x00000003 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW__MODE___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW___M 0x0000033F +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_MAINCTL_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPGO_LOW (0x00BE2010) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPGO_LOW___RWC QCSR_REG_WO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPGO_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPGO_LOW__DUMPGO___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPGO_LOW__DUMPGO___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPGO_LOW__DUMPGO___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPGO_LOW___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPGO_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPTHR_LOW (0x00BE2018) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPTHR_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPTHR_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPTHR_LOW__DUMPTHR___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPTHR_LOW__DUMPTHR___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPTHR_LOW__DUMPTHR___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPTHR_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_DUMPTHR_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW (0x00BE2020) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW___POR 0x01400000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__NOMINALFREQ___POR 0x140 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__OFFSET___POR 0x00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__WIDTH___POR 0x00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__NOMINALFREQ___M 0x0FFF0000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__NOMINALFREQ___S 16 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__OFFSET___M 0x0000FF00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__OFFSET___S 8 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__WIDTH___M 0x000000FF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW__WIDTH___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW___M 0x0FFFFFFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_BIN_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_LOW (0x00BE2028) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_LOW__LATSUM___POR 0x0000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_LOW__LATSUM___M 0x0FFFFFFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_LOW__LATSUM___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_LOW___M 0x0FFFFFFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_HIGH (0x00BE202C) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_HIGH___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_HIGH___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_HIGH__TRCNT___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_HIGH__TRCNT___M 0x000FFF00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_HIGH__TRCNT___S 8 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_HIGH___M 0x000FFF00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_AVLATENCY_HIGH___S 8 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN0_LOW (0x00BE2040) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN0_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN0_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN0_LOW__HISTBIN0___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN0_LOW__HISTBIN0___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN0_LOW__HISTBIN0___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN0_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN0_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN1_LOW (0x00BE2048) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN1_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN1_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN1_LOW__HISTBIN1___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN1_LOW__HISTBIN1___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN1_LOW__HISTBIN1___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN1_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN1_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN2_LOW (0x00BE2050) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN2_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN2_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN2_LOW__HISTBIN2___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN2_LOW__HISTBIN2___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN2_LOW__HISTBIN2___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN2_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN2_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN3_LOW (0x00BE2058) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN3_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN3_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN3_LOW__HISTBIN3___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN3_LOW__HISTBIN3___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN3_LOW__HISTBIN3___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN3_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN3_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN4_LOW (0x00BE2060) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN4_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN4_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN4_LOW__HISTBIN4___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN4_LOW__HISTBIN4___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN4_LOW__HISTBIN4___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN4_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN4_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN5_LOW (0x00BE2068) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN5_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN5_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN5_LOW__HISTBIN5___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN5_LOW__HISTBIN5___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN5_LOW__HISTBIN5___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN5_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN5_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN6_LOW (0x00BE2070) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN6_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN6_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN6_LOW__HISTBIN6___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN6_LOW__HISTBIN6___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN6_LOW__HISTBIN6___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN6_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN6_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN7_LOW (0x00BE2078) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN7_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN7_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN7_LOW__HISTBIN7___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN7_LOW__HISTBIN7___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN7_LOW__HISTBIN7___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN7_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_HISTBIN7_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_LATMAX_LOW (0x00BE2080) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_LATMAX_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_LATMAX_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_LATMAX_LOW__LATMAX___POR 0x00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_LATMAX_LOW__LATMAX___M 0x000000FF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_LATMAX_LOW__LATMAX___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_LATMAX_LOW___M 0x000000FF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_LATMAX_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_LOW (0x00BE2120) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___POR 0x000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFC00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___S 10 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_LOW___M 0xFFFFFC00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_LOW___S 10 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH (0x00BE2124) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000003F +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH___M 0x0000003F +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_LOW (0x00BE2128) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___POR 0x000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFC00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___S 10 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_LOW___M 0xFFFFFC00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_LOW___S 10 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH (0x00BE212C) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000003F +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH___M 0x0000003F +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW (0x00BE2138) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__CMEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__WREN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__RDEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___M 0x00000010 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___S 4 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__CMEN___M 0x00000008 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__CMEN___S 3 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___M 0x00000004 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___S 2 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__WREN___M 0x00000002 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__WREN___S 1 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__RDEN___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW__RDEN___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW___M 0x0000001F +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_RD_TENUREPRB_FILTER_OPCODE_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW (0x00BE2200) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW___POR 0x00039006 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW__UNITTYPEID___POR 0x03 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW__UNITCONFID___POR 0x9006 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW__UNITTYPEID___S 16 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW__UNITCONFID___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW___M 0x00FFFFFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_HIGH (0x00BE2204) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_HIGH__QNOCID___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_HIGH___M 0xFFFFFFFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_SWID_HIGH___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW (0x00BE2208) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__SCALEEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__DUMPEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__MODE___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___M 0x00000300 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___S 8 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___S 5 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___M 0x00000010 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___S 4 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__SCALEEN___M 0x00000008 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__SCALEEN___S 3 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__DUMPEN___M 0x00000004 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__DUMPEN___S 2 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__MODE___M 0x00000003 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW__MODE___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW___M 0x0000033F +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_MAINCTL_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPGO_LOW (0x00BE2210) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPGO_LOW___RWC QCSR_REG_WO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPGO_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPGO_LOW__DUMPGO___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPGO_LOW__DUMPGO___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPGO_LOW__DUMPGO___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPGO_LOW___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPGO_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPTHR_LOW (0x00BE2218) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPTHR_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPTHR_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPTHR_LOW__DUMPTHR___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPTHR_LOW__DUMPTHR___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPTHR_LOW__DUMPTHR___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPTHR_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_DUMPTHR_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW (0x00BE2220) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW___POR 0x01400000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__NOMINALFREQ___POR 0x140 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__OFFSET___POR 0x00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__WIDTH___POR 0x00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__NOMINALFREQ___M 0x0FFF0000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__NOMINALFREQ___S 16 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__OFFSET___M 0x0000FF00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__OFFSET___S 8 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__WIDTH___M 0x000000FF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW__WIDTH___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW___M 0x0FFFFFFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_BIN_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_LOW (0x00BE2228) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_LOW__LATSUM___POR 0x0000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_LOW__LATSUM___M 0x0FFFFFFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_LOW__LATSUM___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_LOW___M 0x0FFFFFFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_HIGH (0x00BE222C) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_HIGH___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_HIGH___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_HIGH__TRCNT___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_HIGH__TRCNT___M 0x000FFF00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_HIGH__TRCNT___S 8 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_HIGH___M 0x000FFF00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_AVLATENCY_HIGH___S 8 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN0_LOW (0x00BE2240) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN0_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN0_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN0_LOW__HISTBIN0___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN0_LOW__HISTBIN0___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN0_LOW__HISTBIN0___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN0_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN0_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN1_LOW (0x00BE2248) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN1_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN1_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN1_LOW__HISTBIN1___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN1_LOW__HISTBIN1___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN1_LOW__HISTBIN1___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN1_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN1_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN2_LOW (0x00BE2250) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN2_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN2_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN2_LOW__HISTBIN2___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN2_LOW__HISTBIN2___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN2_LOW__HISTBIN2___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN2_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN2_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN3_LOW (0x00BE2258) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN3_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN3_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN3_LOW__HISTBIN3___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN3_LOW__HISTBIN3___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN3_LOW__HISTBIN3___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN3_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN3_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN4_LOW (0x00BE2260) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN4_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN4_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN4_LOW__HISTBIN4___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN4_LOW__HISTBIN4___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN4_LOW__HISTBIN4___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN4_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN4_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN5_LOW (0x00BE2268) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN5_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN5_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN5_LOW__HISTBIN5___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN5_LOW__HISTBIN5___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN5_LOW__HISTBIN5___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN5_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN5_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN6_LOW (0x00BE2270) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN6_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN6_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN6_LOW__HISTBIN6___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN6_LOW__HISTBIN6___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN6_LOW__HISTBIN6___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN6_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN6_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN7_LOW (0x00BE2278) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN7_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN7_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN7_LOW__HISTBIN7___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN7_LOW__HISTBIN7___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN7_LOW__HISTBIN7___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN7_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_HISTBIN7_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_LATMAX_LOW (0x00BE2280) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_LATMAX_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_LATMAX_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_LATMAX_LOW__LATMAX___POR 0x00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_LATMAX_LOW__LATMAX___M 0x000000FF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_LATMAX_LOW__LATMAX___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_LATMAX_LOW___M 0x000000FF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_LATMAX_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_LOW (0x00BE2320) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___POR 0x000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFC00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___S 10 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_LOW___M 0xFFFFFC00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_LOW___S 10 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH (0x00BE2324) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000003F +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH___M 0x0000003F +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_LOW (0x00BE2328) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___POR 0x000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFC00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___S 10 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_LOW___M 0xFFFFFC00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_LOW___S 10 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH (0x00BE232C) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000003F +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH___M 0x0000003F +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW (0x00BE2338) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__CMEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__WREN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__RDEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___M 0x00000010 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___S 4 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__CMEN___M 0x00000008 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__CMEN___S 3 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___M 0x00000004 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___S 2 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__WREN___M 0x00000002 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__WREN___S 1 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__RDEN___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW__RDEN___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW___M 0x0000001F +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_5_WR_TENUREPRB_FILTER_OPCODE_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW (0x00BE2400) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW___POR 0x00039006 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW__UNITTYPEID___POR 0x03 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW__UNITCONFID___POR 0x9006 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW__UNITTYPEID___S 16 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW__UNITCONFID___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW___M 0x00FFFFFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_HIGH (0x00BE2404) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_HIGH__QNOCID___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_HIGH___M 0xFFFFFFFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_SWID_HIGH___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW (0x00BE2408) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__SCALEEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__DUMPEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__MODE___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___M 0x00000300 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___S 8 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___S 5 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___M 0x00000010 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___S 4 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__SCALEEN___M 0x00000008 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__SCALEEN___S 3 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__DUMPEN___M 0x00000004 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__DUMPEN___S 2 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__MODE___M 0x00000003 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW__MODE___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW___M 0x0000033F +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_MAINCTL_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPGO_LOW (0x00BE2410) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPGO_LOW___RWC QCSR_REG_WO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPGO_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPGO_LOW__DUMPGO___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPGO_LOW__DUMPGO___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPGO_LOW__DUMPGO___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPGO_LOW___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPGO_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPTHR_LOW (0x00BE2418) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPTHR_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPTHR_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPTHR_LOW__DUMPTHR___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPTHR_LOW__DUMPTHR___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPTHR_LOW__DUMPTHR___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPTHR_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_DUMPTHR_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW (0x00BE2420) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW___POR 0x01400000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__NOMINALFREQ___POR 0x140 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__OFFSET___POR 0x00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__WIDTH___POR 0x00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__NOMINALFREQ___M 0x0FFF0000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__NOMINALFREQ___S 16 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__OFFSET___M 0x0000FF00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__OFFSET___S 8 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__WIDTH___M 0x000000FF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW__WIDTH___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW___M 0x0FFFFFFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_BIN_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_LOW (0x00BE2428) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_LOW__LATSUM___POR 0x0000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_LOW__LATSUM___M 0x0FFFFFFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_LOW__LATSUM___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_LOW___M 0x0FFFFFFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_HIGH (0x00BE242C) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_HIGH___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_HIGH___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_HIGH__TRCNT___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_HIGH__TRCNT___M 0x000FFF00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_HIGH__TRCNT___S 8 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_HIGH___M 0x000FFF00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_AVLATENCY_HIGH___S 8 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN0_LOW (0x00BE2440) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN0_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN0_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN0_LOW__HISTBIN0___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN0_LOW__HISTBIN0___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN0_LOW__HISTBIN0___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN0_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN0_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN1_LOW (0x00BE2448) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN1_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN1_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN1_LOW__HISTBIN1___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN1_LOW__HISTBIN1___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN1_LOW__HISTBIN1___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN1_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN1_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN2_LOW (0x00BE2450) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN2_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN2_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN2_LOW__HISTBIN2___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN2_LOW__HISTBIN2___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN2_LOW__HISTBIN2___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN2_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN2_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN3_LOW (0x00BE2458) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN3_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN3_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN3_LOW__HISTBIN3___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN3_LOW__HISTBIN3___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN3_LOW__HISTBIN3___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN3_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN3_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN4_LOW (0x00BE2460) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN4_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN4_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN4_LOW__HISTBIN4___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN4_LOW__HISTBIN4___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN4_LOW__HISTBIN4___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN4_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN4_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN5_LOW (0x00BE2468) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN5_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN5_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN5_LOW__HISTBIN5___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN5_LOW__HISTBIN5___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN5_LOW__HISTBIN5___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN5_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN5_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN6_LOW (0x00BE2470) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN6_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN6_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN6_LOW__HISTBIN6___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN6_LOW__HISTBIN6___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN6_LOW__HISTBIN6___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN6_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN6_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN7_LOW (0x00BE2478) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN7_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN7_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN7_LOW__HISTBIN7___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN7_LOW__HISTBIN7___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN7_LOW__HISTBIN7___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN7_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_HISTBIN7_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_LATMAX_LOW (0x00BE2480) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_LATMAX_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_LATMAX_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_LATMAX_LOW__LATMAX___POR 0x00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_LATMAX_LOW__LATMAX___M 0x000000FF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_LATMAX_LOW__LATMAX___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_LATMAX_LOW___M 0x000000FF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_LATMAX_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_LOW (0x00BE2520) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___POR 0x000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFC00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___S 10 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_LOW___M 0xFFFFFC00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_LOW___S 10 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH (0x00BE2524) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000003F +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH___M 0x0000003F +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MIN_HIGH___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_LOW (0x00BE2528) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___POR 0x000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFC00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___S 10 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_LOW___M 0xFFFFFC00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_LOW___S 10 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH (0x00BE252C) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000003F +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH___M 0x0000003F +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_ADDR_MAX_HIGH___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW (0x00BE2538) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__CMEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__WREN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__RDEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___M 0x00000010 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___S 4 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__CMEN___M 0x00000008 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__CMEN___S 3 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___M 0x00000004 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___S 2 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__WREN___M 0x00000002 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__WREN___S 1 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__RDEN___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW__RDEN___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW___M 0x0000001F +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_RD_TENUREPRB_FILTER_OPCODE_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW (0x00BE2600) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW___POR 0x00039006 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW__UNITTYPEID___POR 0x03 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW__UNITCONFID___POR 0x9006 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW__UNITTYPEID___S 16 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW__UNITCONFID___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW___M 0x00FFFFFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_HIGH (0x00BE2604) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_HIGH__QNOCID___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_HIGH___M 0xFFFFFFFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_SWID_HIGH___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW (0x00BE2608) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__SCALEEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__DUMPEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__MODE___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___M 0x00000300 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___S 8 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___S 5 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___M 0x00000010 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___S 4 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__SCALEEN___M 0x00000008 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__SCALEEN___S 3 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__DUMPEN___M 0x00000004 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__DUMPEN___S 2 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__MODE___M 0x00000003 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW__MODE___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW___M 0x0000033F +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_MAINCTL_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPGO_LOW (0x00BE2610) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPGO_LOW___RWC QCSR_REG_WO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPGO_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPGO_LOW__DUMPGO___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPGO_LOW__DUMPGO___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPGO_LOW__DUMPGO___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPGO_LOW___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPGO_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPTHR_LOW (0x00BE2618) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPTHR_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPTHR_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPTHR_LOW__DUMPTHR___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPTHR_LOW__DUMPTHR___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPTHR_LOW__DUMPTHR___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPTHR_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_DUMPTHR_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW (0x00BE2620) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW___POR 0x01400000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__NOMINALFREQ___POR 0x140 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__OFFSET___POR 0x00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__WIDTH___POR 0x00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__NOMINALFREQ___M 0x0FFF0000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__NOMINALFREQ___S 16 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__OFFSET___M 0x0000FF00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__OFFSET___S 8 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__WIDTH___M 0x000000FF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW__WIDTH___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW___M 0x0FFFFFFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_BIN_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_LOW (0x00BE2628) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_LOW__LATSUM___POR 0x0000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_LOW__LATSUM___M 0x0FFFFFFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_LOW__LATSUM___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_LOW___M 0x0FFFFFFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_HIGH (0x00BE262C) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_HIGH___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_HIGH___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_HIGH__TRCNT___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_HIGH__TRCNT___M 0x000FFF00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_HIGH__TRCNT___S 8 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_HIGH___M 0x000FFF00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_AVLATENCY_HIGH___S 8 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN0_LOW (0x00BE2640) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN0_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN0_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN0_LOW__HISTBIN0___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN0_LOW__HISTBIN0___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN0_LOW__HISTBIN0___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN0_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN0_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN1_LOW (0x00BE2648) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN1_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN1_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN1_LOW__HISTBIN1___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN1_LOW__HISTBIN1___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN1_LOW__HISTBIN1___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN1_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN1_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN2_LOW (0x00BE2650) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN2_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN2_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN2_LOW__HISTBIN2___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN2_LOW__HISTBIN2___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN2_LOW__HISTBIN2___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN2_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN2_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN3_LOW (0x00BE2658) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN3_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN3_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN3_LOW__HISTBIN3___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN3_LOW__HISTBIN3___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN3_LOW__HISTBIN3___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN3_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN3_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN4_LOW (0x00BE2660) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN4_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN4_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN4_LOW__HISTBIN4___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN4_LOW__HISTBIN4___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN4_LOW__HISTBIN4___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN4_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN4_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN5_LOW (0x00BE2668) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN5_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN5_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN5_LOW__HISTBIN5___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN5_LOW__HISTBIN5___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN5_LOW__HISTBIN5___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN5_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN5_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN6_LOW (0x00BE2670) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN6_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN6_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN6_LOW__HISTBIN6___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN6_LOW__HISTBIN6___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN6_LOW__HISTBIN6___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN6_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN6_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN7_LOW (0x00BE2678) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN7_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN7_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN7_LOW__HISTBIN7___POR 0x000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN7_LOW__HISTBIN7___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN7_LOW__HISTBIN7___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN7_LOW___M 0x00000FFF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_HISTBIN7_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_LATMAX_LOW (0x00BE2680) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_LATMAX_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_LATMAX_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_LATMAX_LOW__LATMAX___POR 0x00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_LATMAX_LOW__LATMAX___M 0x000000FF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_LATMAX_LOW__LATMAX___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_LATMAX_LOW___M 0x000000FF +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_LATMAX_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_LOW (0x00BE2720) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___POR 0x000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFC00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___S 10 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_LOW___M 0xFFFFFC00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_LOW___S 10 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH (0x00BE2724) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000003F +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH___M 0x0000003F +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MIN_HIGH___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_LOW (0x00BE2728) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___POR 0x000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFC00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___S 10 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_LOW___M 0xFFFFFC00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_LOW___S 10 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH (0x00BE272C) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000003F +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH___M 0x0000003F +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_ADDR_MAX_HIGH___S 0 + +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW (0x00BE2738) +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__CMEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__WREN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__RDEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___M 0x00000010 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___S 4 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__CMEN___M 0x00000008 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__CMEN___S 3 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___M 0x00000004 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___S 2 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__WREN___M 0x00000002 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__WREN___S 1 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__RDEN___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW__RDEN___S 0 +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW___M 0x0000001F +#define DBG_PHYA_PHYA_NOC_QXM_DMAC_6_WR_TENUREPRB_FILTER_OPCODE_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_STP_SWID_LOW (0x00BE2800) +#define DBG_PHYA_PHYA_NOC_STP_SWID_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_STP_SWID_LOW___POR 0x000CE93B +#define DBG_PHYA_PHYA_NOC_STP_SWID_LOW__UNITTYPEID___POR 0x0C +#define DBG_PHYA_PHYA_NOC_STP_SWID_LOW__UNITCONFID___POR 0xE93B +#define DBG_PHYA_PHYA_NOC_STP_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_PHYA_PHYA_NOC_STP_SWID_LOW__UNITTYPEID___S 16 +#define DBG_PHYA_PHYA_NOC_STP_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_PHYA_PHYA_NOC_STP_SWID_LOW__UNITCONFID___S 0 +#define DBG_PHYA_PHYA_NOC_STP_SWID_LOW___M 0x00FFFFFF +#define DBG_PHYA_PHYA_NOC_STP_SWID_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_STP_SWID_HIGH (0x00BE2804) +#define DBG_PHYA_PHYA_NOC_STP_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_STP_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_PHYA_PHYA_NOC_STP_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_PHYA_PHYA_NOC_STP_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_PHYA_PHYA_NOC_STP_SWID_HIGH__QNOCID___S 0 +#define DBG_PHYA_PHYA_NOC_STP_SWID_HIGH___M 0xFFFFFFFF +#define DBG_PHYA_PHYA_NOC_STP_SWID_HIGH___S 0 + +#define DBG_PHYA_PHYA_NOC_STP_ATBEN_LOW (0x00BE2808) +#define DBG_PHYA_PHYA_NOC_STP_ATBEN_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_STP_ATBEN_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_STP_ATBEN_LOW__ATBEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_STP_ATBEN_LOW__ATBEN___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_STP_ATBEN_LOW__ATBEN___S 0 +#define DBG_PHYA_PHYA_NOC_STP_ATBEN_LOW___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_STP_ATBEN_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_STP_ATBID_LOW (0x00BE2810) +#define DBG_PHYA_PHYA_NOC_STP_ATBID_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_STP_ATBID_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_STP_ATBID_LOW__ATBID___POR 0x00 +#define DBG_PHYA_PHYA_NOC_STP_ATBID_LOW__ATBID___M 0x0000007F +#define DBG_PHYA_PHYA_NOC_STP_ATBID_LOW__ATBID___S 0 +#define DBG_PHYA_PHYA_NOC_STP_ATBID_LOW___M 0x0000007F +#define DBG_PHYA_PHYA_NOC_STP_ATBID_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_STP_SYNCOUTPERIOD_LOW (0x00BE2818) +#define DBG_PHYA_PHYA_NOC_STP_SYNCOUTPERIOD_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_STP_SYNCOUTPERIOD_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_STP_SYNCOUTPERIOD_LOW__SYNCOUTPERIOD___POR 0x000 +#define DBG_PHYA_PHYA_NOC_STP_SYNCOUTPERIOD_LOW__SYNCOUTPERIOD___M 0x000003FF +#define DBG_PHYA_PHYA_NOC_STP_SYNCOUTPERIOD_LOW__SYNCOUTPERIOD___S 0 +#define DBG_PHYA_PHYA_NOC_STP_SYNCOUTPERIOD_LOW___M 0x000003FF +#define DBG_PHYA_PHYA_NOC_STP_SYNCOUTPERIOD_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_ERL_SWID_LOW (0x00BE2900) +#define DBG_PHYA_PHYA_NOC_ERL_SWID_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_ERL_SWID_LOW___POR 0x0001E93B +#define DBG_PHYA_PHYA_NOC_ERL_SWID_LOW__UNITTYPEID___POR 0x01 +#define DBG_PHYA_PHYA_NOC_ERL_SWID_LOW__UNITCONFID___POR 0xE93B +#define DBG_PHYA_PHYA_NOC_ERL_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define DBG_PHYA_PHYA_NOC_ERL_SWID_LOW__UNITTYPEID___S 16 +#define DBG_PHYA_PHYA_NOC_ERL_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define DBG_PHYA_PHYA_NOC_ERL_SWID_LOW__UNITCONFID___S 0 +#define DBG_PHYA_PHYA_NOC_ERL_SWID_LOW___M 0x00FFFFFF +#define DBG_PHYA_PHYA_NOC_ERL_SWID_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_ERL_SWID_HIGH (0x00BE2904) +#define DBG_PHYA_PHYA_NOC_ERL_SWID_HIGH___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_ERL_SWID_HIGH___POR 0xA8AF23E2 +#define DBG_PHYA_PHYA_NOC_ERL_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define DBG_PHYA_PHYA_NOC_ERL_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define DBG_PHYA_PHYA_NOC_ERL_SWID_HIGH__QNOCID___S 0 +#define DBG_PHYA_PHYA_NOC_ERL_SWID_HIGH___M 0xFFFFFFFF +#define DBG_PHYA_PHYA_NOC_ERL_SWID_HIGH___S 0 + +#define DBG_PHYA_PHYA_NOC_ERL_MAINCTL_LOW (0x00BE2908) +#define DBG_PHYA_PHYA_NOC_ERL_MAINCTL_LOW___RWC QCSR_REG_RW +#define DBG_PHYA_PHYA_NOC_ERL_MAINCTL_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_ERL_MAINCTL_LOW__STALLEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_ERL_MAINCTL_LOW__FAULTEN___POR 0x0 +#define DBG_PHYA_PHYA_NOC_ERL_MAINCTL_LOW__STALLEN___M 0x00000002 +#define DBG_PHYA_PHYA_NOC_ERL_MAINCTL_LOW__STALLEN___S 1 +#define DBG_PHYA_PHYA_NOC_ERL_MAINCTL_LOW__FAULTEN___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_ERL_MAINCTL_LOW__FAULTEN___S 0 +#define DBG_PHYA_PHYA_NOC_ERL_MAINCTL_LOW___M 0x00000003 +#define DBG_PHYA_PHYA_NOC_ERL_MAINCTL_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_ERL_ERRVLD_LOW (0x00BE2910) +#define DBG_PHYA_PHYA_NOC_ERL_ERRVLD_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_ERL_ERRVLD_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_ERL_ERRVLD_LOW__ERRVLD___POR 0x0 +#define DBG_PHYA_PHYA_NOC_ERL_ERRVLD_LOW__ERRVLD___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_ERL_ERRVLD_LOW__ERRVLD___S 0 +#define DBG_PHYA_PHYA_NOC_ERL_ERRVLD_LOW___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_ERL_ERRVLD_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_ERL_ERRCLR_LOW (0x00BE2918) +#define DBG_PHYA_PHYA_NOC_ERL_ERRCLR_LOW___RWC QCSR_REG_WO +#define DBG_PHYA_PHYA_NOC_ERL_ERRCLR_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_ERL_ERRCLR_LOW__ERRCLR___POR 0x0 +#define DBG_PHYA_PHYA_NOC_ERL_ERRCLR_LOW__ERRCLR___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_ERL_ERRCLR_LOW__ERRCLR___S 0 +#define DBG_PHYA_PHYA_NOC_ERL_ERRCLR_LOW___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_ERL_ERRCLR_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW (0x00BE2920) +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__ATOPC___POR 0x0 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__ADDRSPACE___POR 0x00 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__TRTYPE___POR 0x0 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__ERRCODE___POR 0x0 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__OPC___POR 0x0 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__NONSECURE___POR 0x0 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__WORDERROR___POR 0x0 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__LOGINFOVLD___POR 0x0 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__ATOPC___M 0x0F000000 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__ATOPC___S 24 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__ADDRSPACE___M 0x003F0000 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__ADDRSPACE___S 16 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__TRTYPE___M 0x00007000 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__TRTYPE___S 12 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__ERRCODE___M 0x00000700 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__ERRCODE___S 8 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__OPC___M 0x00000070 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__OPC___S 4 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__NONSECURE___M 0x00000004 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__NONSECURE___S 2 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__WORDERROR___M 0x00000002 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__WORDERROR___S 1 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__LOGINFOVLD___M 0x00000001 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW__LOGINFOVLD___S 0 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW___M 0x0F3F7777 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_HIGH (0x00BE2924) +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_HIGH___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_HIGH___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_HIGH__REDIRECT___POR 0x00 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_HIGH__LEN1___POR 0x000 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_HIGH__REDIRECT___M 0x00FF0000 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_HIGH__REDIRECT___S 16 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_HIGH__LEN1___M 0x000003FF +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_HIGH__LEN1___S 0 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_HIGH___M 0x00FF03FF +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG0_HIGH___S 0 + +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG1_LOW (0x00BE2928) +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG1_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG1_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG1_LOW__PATH___POR 0x0000 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG1_LOW__PATH___M 0x0000FFFF +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG1_LOW__PATH___S 0 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG1_LOW___M 0x0000FFFF +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG1_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG1_HIGH (0x00BE292C) +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG1_HIGH___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG1_HIGH___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG1_HIGH__EXTID___POR 0x00000 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG1_HIGH__EXTID___M 0x0003FFFF +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG1_HIGH__EXTID___S 0 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG1_HIGH___M 0x0003FFFF +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG1_HIGH___S 0 + +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG2_LOW (0x00BE2930) +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG2_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG2_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG2_LOW__ERRLOG2_LSB___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG2_LOW__ERRLOG2_LSB___M 0xFFFFFFFF +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG2_LOW__ERRLOG2_LSB___S 0 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG2_LOW___M 0xFFFFFFFF +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG2_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG2_HIGH (0x00BE2934) +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG2_HIGH___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG2_HIGH___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___POR 0x00000 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___M 0x0001FFFF +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___S 0 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG2_HIGH___M 0x0001FFFF +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG2_HIGH___S 0 + +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG3_LOW (0x00BE2938) +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG3_LOW___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG3_LOW___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG3_LOW__ERRLOG3_LSB___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG3_LOW__ERRLOG3_LSB___M 0xFFFFFFFF +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG3_LOW__ERRLOG3_LSB___S 0 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG3_LOW___M 0xFFFFFFFF +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG3_LOW___S 0 + +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG3_HIGH (0x00BE293C) +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG3_HIGH___RWC QCSR_REG_RO +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG3_HIGH___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___POR 0x00000000 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___M 0xFFFFFFFF +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___S 0 +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG3_HIGH___M 0xFFFFFFFF +#define DBG_PHYA_PHYA_NOC_ERL_ERRLOG3_HIGH___S 0 + +#define DBG_PHYA_FUN_CTRL_REG (0x00BE4000) +#define DBG_PHYA_FUN_CTRL_REG___RWC QCSR_REG_RW +#define DBG_PHYA_FUN_CTRL_REG___POR 0x00000300 +#define DBG_PHYA_FUN_CTRL_REG__HT___POR 0x3 +#define DBG_PHYA_FUN_CTRL_REG__ENS7___POR 0x0 +#define DBG_PHYA_FUN_CTRL_REG__ENS6___POR 0x0 +#define DBG_PHYA_FUN_CTRL_REG__ENS5___POR 0x0 +#define DBG_PHYA_FUN_CTRL_REG__ENS4___POR 0x0 +#define DBG_PHYA_FUN_CTRL_REG__ENS3___POR 0x0 +#define DBG_PHYA_FUN_CTRL_REG__ENS2___POR 0x0 +#define DBG_PHYA_FUN_CTRL_REG__ENS1___POR 0x0 +#define DBG_PHYA_FUN_CTRL_REG__ENS0___POR 0x0 +#define DBG_PHYA_FUN_CTRL_REG__HT___M 0x00000F00 +#define DBG_PHYA_FUN_CTRL_REG__HT___S 8 +#define DBG_PHYA_FUN_CTRL_REG__HT__HT_0X0 0x0 +#define DBG_PHYA_FUN_CTRL_REG__HT__HT_0X1 0x1 +#define DBG_PHYA_FUN_CTRL_REG__HT__HT_0X2 0x2 +#define DBG_PHYA_FUN_CTRL_REG__HT__HT_0X3 0x3 +#define DBG_PHYA_FUN_CTRL_REG__HT__HT_0X4 0x4 +#define DBG_PHYA_FUN_CTRL_REG__HT__HT_0X5 0x5 +#define DBG_PHYA_FUN_CTRL_REG__HT__HT_0X6 0x6 +#define DBG_PHYA_FUN_CTRL_REG__HT__HT_0X7 0x7 +#define DBG_PHYA_FUN_CTRL_REG__HT__HT_0X8 0x8 +#define DBG_PHYA_FUN_CTRL_REG__HT__HT_0X9 0x9 +#define DBG_PHYA_FUN_CTRL_REG__HT__HT_0XA 0xA +#define DBG_PHYA_FUN_CTRL_REG__HT__HT_0XB 0xB +#define DBG_PHYA_FUN_CTRL_REG__HT__HT_0XC 0xC +#define DBG_PHYA_FUN_CTRL_REG__HT__HT_0XD 0xD +#define DBG_PHYA_FUN_CTRL_REG__HT__HT_0XE 0xE +#define DBG_PHYA_FUN_CTRL_REG__ENS7___M 0x00000080 +#define DBG_PHYA_FUN_CTRL_REG__ENS7___S 7 +#define DBG_PHYA_FUN_CTRL_REG__ENS7__ENS7_0 0x0 +#define DBG_PHYA_FUN_CTRL_REG__ENS7__ENS7_1 0x1 +#define DBG_PHYA_FUN_CTRL_REG__ENS6___M 0x00000040 +#define DBG_PHYA_FUN_CTRL_REG__ENS6___S 6 +#define DBG_PHYA_FUN_CTRL_REG__ENS6__ENS6_0 0x0 +#define DBG_PHYA_FUN_CTRL_REG__ENS6__ENS6_1 0x1 +#define DBG_PHYA_FUN_CTRL_REG__ENS5___M 0x00000020 +#define DBG_PHYA_FUN_CTRL_REG__ENS5___S 5 +#define DBG_PHYA_FUN_CTRL_REG__ENS5__ENS5_0 0x0 +#define DBG_PHYA_FUN_CTRL_REG__ENS5__ENS5_1 0x1 +#define DBG_PHYA_FUN_CTRL_REG__ENS4___M 0x00000010 +#define DBG_PHYA_FUN_CTRL_REG__ENS4___S 4 +#define DBG_PHYA_FUN_CTRL_REG__ENS4__ENS4_0 0x0 +#define DBG_PHYA_FUN_CTRL_REG__ENS4__ENS4_1 0x1 +#define DBG_PHYA_FUN_CTRL_REG__ENS3___M 0x00000008 +#define DBG_PHYA_FUN_CTRL_REG__ENS3___S 3 +#define DBG_PHYA_FUN_CTRL_REG__ENS3__ENS3_0 0x0 +#define DBG_PHYA_FUN_CTRL_REG__ENS3__ENS3_1 0x1 +#define DBG_PHYA_FUN_CTRL_REG__ENS2___M 0x00000004 +#define DBG_PHYA_FUN_CTRL_REG__ENS2___S 2 +#define DBG_PHYA_FUN_CTRL_REG__ENS2__ENS2_0 0x0 +#define DBG_PHYA_FUN_CTRL_REG__ENS2__ENS2_1 0x1 +#define DBG_PHYA_FUN_CTRL_REG__ENS1___M 0x00000002 +#define DBG_PHYA_FUN_CTRL_REG__ENS1___S 1 +#define DBG_PHYA_FUN_CTRL_REG__ENS1__ENS1_0 0x0 +#define DBG_PHYA_FUN_CTRL_REG__ENS1__ENS1_1 0x1 +#define DBG_PHYA_FUN_CTRL_REG__ENS0___M 0x00000001 +#define DBG_PHYA_FUN_CTRL_REG__ENS0___S 0 +#define DBG_PHYA_FUN_CTRL_REG__ENS0__ENS0_0 0x0 +#define DBG_PHYA_FUN_CTRL_REG__ENS0__ENS0_1 0x1 +#define DBG_PHYA_FUN_CTRL_REG___M 0x00000FFF +#define DBG_PHYA_FUN_CTRL_REG___S 0 + +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG (0x00BE4004) +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG___RWC QCSR_REG_RW +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG___POR 0x00000000 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT7___POR 0x0 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT6___POR 0x0 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT5___POR 0x0 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT4___POR 0x0 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT3___POR 0x0 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT2___POR 0x0 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT1___POR 0x0 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT0___POR 0x0 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT7___M 0x00E00000 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT7___S 21 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_0 0x0 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_1 0x1 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_2 0x2 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_3 0x3 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_4 0x4 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_5 0x5 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_6 0x6 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT7__PRIPORT7_7 0x7 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT6___M 0x001C0000 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT6___S 18 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_0 0x0 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_1 0x1 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_2 0x2 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_3 0x3 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_4 0x4 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_5 0x5 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_6 0x6 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT6__PRIPORT6_7 0x7 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT5___M 0x00038000 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT5___S 15 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_0 0x0 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_1 0x1 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_2 0x2 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_3 0x3 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_4 0x4 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_5 0x5 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_6 0x6 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT5__PRIPORT5_7 0x7 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT4___M 0x00007000 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT4___S 12 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_0 0x0 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_1 0x1 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_2 0x2 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_3 0x3 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_4 0x4 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_5 0x5 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_6 0x6 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT4__PRIPORT4_7 0x7 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT3___M 0x00000E00 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT3___S 9 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_0 0x0 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_1 0x1 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_2 0x2 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_3 0x3 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_4 0x4 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_5 0x5 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_6 0x6 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT3__PRIPORT3_7 0x7 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT2___M 0x000001C0 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT2___S 6 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_0 0x0 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_1 0x1 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_2 0x2 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_3 0x3 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_4 0x4 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_5 0x5 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_6 0x6 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT2__PRIPORT2_7 0x7 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT1___M 0x00000038 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT1___S 3 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_0 0x0 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_1 0x1 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_2 0x2 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_3 0x3 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_4 0x4 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_5 0x5 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_6 0x6 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT1__PRIPORT1_7 0x7 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT0___M 0x00000007 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT0___S 0 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_0 0x0 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_1 0x1 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_2 0x2 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_3 0x3 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_4 0x4 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_5 0x5 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_6 0x6 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG__PRIPORT0__PRIPORT0_7 0x7 +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG___M 0x00FFFFFF +#define DBG_PHYA_FUN_PRIORITY_CTRL_REG___S 0 + +#define DBG_PHYA_FUN_ITATBDATA0 (0x00BE4EEC) +#define DBG_PHYA_FUN_ITATBDATA0___RWC QCSR_REG_RW +#define DBG_PHYA_FUN_ITATBDATA0___POR 0x00000000 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA63___POR 0x0 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA55___POR 0x0 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA47___POR 0x0 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA39___POR 0x0 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA31___POR 0x0 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATAM23___POR 0x0 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA15___POR 0x0 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA7___POR 0x0 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA0___POR 0x0 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA63___M 0x00000100 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA63___S 8 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA63__ATDATA63_0 0x0 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA63__ATDATA63_1 0x1 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA55___M 0x00000080 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA55___S 7 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA55__ATDATA55_0 0x0 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA55__ATDATA55_1 0x1 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA47___M 0x00000040 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA47___S 6 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA47__ATDATA47_0 0x0 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA47__ATDATA47_1 0x1 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA39___M 0x00000020 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA39___S 5 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA39__ATDATA39_0 0x0 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA39__ATDATA39_1 0x1 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA31___M 0x00000010 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA31___S 4 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA31__ATDATA31_0 0x0 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA31__ATDATA31_1 0x1 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATAM23___M 0x00000008 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATAM23___S 3 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATAM23__ATDATAM23_0 0x0 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATAM23__ATDATAM23_1 0x1 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA15___M 0x00000004 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA15___S 2 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA15__ATDATA15_0 0x0 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA15__ATDATA15_1 0x1 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA7___M 0x00000002 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA7___S 1 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA7__ATDATA7_0 0x0 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA7__ATDATA7_1 0x1 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA0___M 0x00000001 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA0___S 0 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA0__ATDATA0_0 0x0 +#define DBG_PHYA_FUN_ITATBDATA0__ATDATA0__ATDATA0_1 0x1 +#define DBG_PHYA_FUN_ITATBDATA0___M 0x000001FF +#define DBG_PHYA_FUN_ITATBDATA0___S 0 + +#define DBG_PHYA_FUN_ITATBCTR2 (0x00BE4EF0) +#define DBG_PHYA_FUN_ITATBCTR2___RWC QCSR_REG_RW +#define DBG_PHYA_FUN_ITATBCTR2___POR 0x00000000 +#define DBG_PHYA_FUN_ITATBCTR2__AFVALID___POR 0x0 +#define DBG_PHYA_FUN_ITATBCTR2__ATREADY___POR 0x0 +#define DBG_PHYA_FUN_ITATBCTR2__AFVALID___M 0x00000002 +#define DBG_PHYA_FUN_ITATBCTR2__AFVALID___S 1 +#define DBG_PHYA_FUN_ITATBCTR2__AFVALID__AFVALID_0 0x0 +#define DBG_PHYA_FUN_ITATBCTR2__AFVALID__AFVALID_1 0x1 +#define DBG_PHYA_FUN_ITATBCTR2__ATREADY___M 0x00000001 +#define DBG_PHYA_FUN_ITATBCTR2__ATREADY___S 0 +#define DBG_PHYA_FUN_ITATBCTR2__ATREADY__ATREADY_0 0x0 +#define DBG_PHYA_FUN_ITATBCTR2__ATREADY__ATREADY_1 0x1 +#define DBG_PHYA_FUN_ITATBCTR2___M 0x00000003 +#define DBG_PHYA_FUN_ITATBCTR2___S 0 + +#define DBG_PHYA_FUN_ITATBCTR1 (0x00BE4EF4) +#define DBG_PHYA_FUN_ITATBCTR1___RWC QCSR_REG_RW +#define DBG_PHYA_FUN_ITATBCTR1__ATID___M 0x0000007F +#define DBG_PHYA_FUN_ITATBCTR1__ATID___S 0 +#define DBG_PHYA_FUN_ITATBCTR1___M 0x0000007F +#define DBG_PHYA_FUN_ITATBCTR1___S 0 + +#define DBG_PHYA_FUN_ITATBCTR0 (0x00BE4EF8) +#define DBG_PHYA_FUN_ITATBCTR0___RWC QCSR_REG_RW +#define DBG_PHYA_FUN_ITATBCTR0___POR 0x00000000 +#define DBG_PHYA_FUN_ITATBCTR0__ATBYTES___POR 0x0 +#define DBG_PHYA_FUN_ITATBCTR0__AFREADY___POR 0x0 +#define DBG_PHYA_FUN_ITATBCTR0__ATVALID___POR 0x0 +#define DBG_PHYA_FUN_ITATBCTR0__ATBYTES___M 0x00000700 +#define DBG_PHYA_FUN_ITATBCTR0__ATBYTES___S 8 +#define DBG_PHYA_FUN_ITATBCTR0__ATBYTES__ATBYTES_0 0x0 +#define DBG_PHYA_FUN_ITATBCTR0__ATBYTES__ATBYTES_1 0x1 +#define DBG_PHYA_FUN_ITATBCTR0__AFREADY___M 0x00000002 +#define DBG_PHYA_FUN_ITATBCTR0__AFREADY___S 1 +#define DBG_PHYA_FUN_ITATBCTR0__AFREADY__AFREADY_0 0x0 +#define DBG_PHYA_FUN_ITATBCTR0__AFREADY__AFREADY_1 0x1 +#define DBG_PHYA_FUN_ITATBCTR0__ATVALID___M 0x00000001 +#define DBG_PHYA_FUN_ITATBCTR0__ATVALID___S 0 +#define DBG_PHYA_FUN_ITATBCTR0__ATVALID__ATVALID_0 0x0 +#define DBG_PHYA_FUN_ITATBCTR0__ATVALID__ATVALID_1 0x1 +#define DBG_PHYA_FUN_ITATBCTR0___M 0x00000703 +#define DBG_PHYA_FUN_ITATBCTR0___S 0 + +#define DBG_PHYA_FUN_ITCTRL (0x00BE4F00) +#define DBG_PHYA_FUN_ITCTRL___RWC QCSR_REG_RW +#define DBG_PHYA_FUN_ITCTRL___POR 0x00000000 +#define DBG_PHYA_FUN_ITCTRL__INTEGRATION_MODE___POR 0x0 +#define DBG_PHYA_FUN_ITCTRL__INTEGRATION_MODE___M 0x00000001 +#define DBG_PHYA_FUN_ITCTRL__INTEGRATION_MODE___S 0 +#define DBG_PHYA_FUN_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE_0 0x0 +#define DBG_PHYA_FUN_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE_1 0x1 +#define DBG_PHYA_FUN_ITCTRL___M 0x00000001 +#define DBG_PHYA_FUN_ITCTRL___S 0 + +#define DBG_PHYA_FUN_CLAIMSET (0x00BE4FA0) +#define DBG_PHYA_FUN_CLAIMSET___RWC QCSR_REG_RW +#define DBG_PHYA_FUN_CLAIMSET___POR 0x0000000F +#define DBG_PHYA_FUN_CLAIMSET__CLAIMSET___POR 0xF +#define DBG_PHYA_FUN_CLAIMSET__CLAIMSET___M 0x0000000F +#define DBG_PHYA_FUN_CLAIMSET__CLAIMSET___S 0 +#define DBG_PHYA_FUN_CLAIMSET__CLAIMSET__CLAIMSET_0XF 0xF +#define DBG_PHYA_FUN_CLAIMSET___M 0x0000000F +#define DBG_PHYA_FUN_CLAIMSET___S 0 + +#define DBG_PHYA_FUN_CLAIMCLR (0x00BE4FA4) +#define DBG_PHYA_FUN_CLAIMCLR___RWC QCSR_REG_RW +#define DBG_PHYA_FUN_CLAIMCLR___POR 0x00000000 +#define DBG_PHYA_FUN_CLAIMCLR__CLAIMCLR___POR 0x0 +#define DBG_PHYA_FUN_CLAIMCLR__CLAIMCLR___M 0x0000000F +#define DBG_PHYA_FUN_CLAIMCLR__CLAIMCLR___S 0 +#define DBG_PHYA_FUN_CLAIMCLR___M 0x0000000F +#define DBG_PHYA_FUN_CLAIMCLR___S 0 + +#define DBG_PHYA_FUN_LOCKACCESS (0x00BE4FB0) +#define DBG_PHYA_FUN_LOCKACCESS___RWC QCSR_REG_WO +#define DBG_PHYA_FUN_LOCKACCESS__KEY___M 0xFFFFFFFF +#define DBG_PHYA_FUN_LOCKACCESS__KEY___S 0 +#define DBG_PHYA_FUN_LOCKACCESS__KEY__KEY_0XC5ACCE55 0xC5ACCE55 +#define DBG_PHYA_FUN_LOCKACCESS__KEY__KEY_0XDEADBEEF 0xDEADBEEF +#define DBG_PHYA_FUN_LOCKACCESS___M 0xFFFFFFFF +#define DBG_PHYA_FUN_LOCKACCESS___S 0 + +#define DBG_PHYA_FUN_LOCKSTATUS (0x00BE4FB4) +#define DBG_PHYA_FUN_LOCKSTATUS___RWC QCSR_REG_RO +#define DBG_PHYA_FUN_LOCKSTATUS___POR 0x00000003 +#define DBG_PHYA_FUN_LOCKSTATUS__NTT___POR 0x0 +#define DBG_PHYA_FUN_LOCKSTATUS__SLK___POR 0x1 +#define DBG_PHYA_FUN_LOCKSTATUS__SLI___POR 0x1 +#define DBG_PHYA_FUN_LOCKSTATUS__NTT___M 0x00000004 +#define DBG_PHYA_FUN_LOCKSTATUS__NTT___S 2 +#define DBG_PHYA_FUN_LOCKSTATUS__NTT__NTT_0X0 0x0 +#define DBG_PHYA_FUN_LOCKSTATUS__SLK___M 0x00000002 +#define DBG_PHYA_FUN_LOCKSTATUS__SLK___S 1 +#define DBG_PHYA_FUN_LOCKSTATUS__SLK__SLK_0X0 0x0 +#define DBG_PHYA_FUN_LOCKSTATUS__SLK__SLK_0X1 0x1 +#define DBG_PHYA_FUN_LOCKSTATUS__SLI___M 0x00000001 +#define DBG_PHYA_FUN_LOCKSTATUS__SLI___S 0 +#define DBG_PHYA_FUN_LOCKSTATUS__SLI__SLI_0X0 0x0 +#define DBG_PHYA_FUN_LOCKSTATUS__SLI__SLI_0X1 0x1 +#define DBG_PHYA_FUN_LOCKSTATUS___M 0x00000007 +#define DBG_PHYA_FUN_LOCKSTATUS___S 0 + +#define DBG_PHYA_FUN_AUTHSTATUS (0x00BE4FB8) +#define DBG_PHYA_FUN_AUTHSTATUS___RWC QCSR_REG_RO +#define DBG_PHYA_FUN_AUTHSTATUS___POR 0x00000000 +#define DBG_PHYA_FUN_AUTHSTATUS__SNID___POR 0x0 +#define DBG_PHYA_FUN_AUTHSTATUS__SID___POR 0x0 +#define DBG_PHYA_FUN_AUTHSTATUS__NSNID___POR 0x0 +#define DBG_PHYA_FUN_AUTHSTATUS__NSID___POR 0x0 +#define DBG_PHYA_FUN_AUTHSTATUS__SNID___M 0x000000C0 +#define DBG_PHYA_FUN_AUTHSTATUS__SNID___S 6 +#define DBG_PHYA_FUN_AUTHSTATUS__SNID__SNID_0X0 0x0 +#define DBG_PHYA_FUN_AUTHSTATUS__SID___M 0x00000030 +#define DBG_PHYA_FUN_AUTHSTATUS__SID___S 4 +#define DBG_PHYA_FUN_AUTHSTATUS__SID__SID_0X0 0x0 +#define DBG_PHYA_FUN_AUTHSTATUS__NSNID___M 0x0000000C +#define DBG_PHYA_FUN_AUTHSTATUS__NSNID___S 2 +#define DBG_PHYA_FUN_AUTHSTATUS__NSNID__NSNID_0X0 0x0 +#define DBG_PHYA_FUN_AUTHSTATUS__NSID___M 0x00000003 +#define DBG_PHYA_FUN_AUTHSTATUS__NSID___S 0 +#define DBG_PHYA_FUN_AUTHSTATUS__NSID__NSID_0X0 0x0 +#define DBG_PHYA_FUN_AUTHSTATUS___M 0x000000FF +#define DBG_PHYA_FUN_AUTHSTATUS___S 0 + +#define DBG_PHYA_FUN_DEVID (0x00BE4FC8) +#define DBG_PHYA_FUN_DEVID___RWC QCSR_REG_RO +#define DBG_PHYA_FUN_DEVID___POR 0x00000038 +#define DBG_PHYA_FUN_DEVID__SCHEME___POR 0x3 +#define DBG_PHYA_FUN_DEVID__PORTCOUNT___POR 0x8 +#define DBG_PHYA_FUN_DEVID__SCHEME___M 0x000000F0 +#define DBG_PHYA_FUN_DEVID__SCHEME___S 4 +#define DBG_PHYA_FUN_DEVID__SCHEME__SCHEME_0X3 0x3 +#define DBG_PHYA_FUN_DEVID__PORTCOUNT___M 0x0000000F +#define DBG_PHYA_FUN_DEVID__PORTCOUNT___S 0 +#define DBG_PHYA_FUN_DEVID__PORTCOUNT__PORTCOUNT_0X2 0x2 +#define DBG_PHYA_FUN_DEVID__PORTCOUNT__PORTCOUNT_0X3 0x3 +#define DBG_PHYA_FUN_DEVID__PORTCOUNT__PORTCOUNT_0X4 0x4 +#define DBG_PHYA_FUN_DEVID__PORTCOUNT__PORTCOUNT_0X5 0x5 +#define DBG_PHYA_FUN_DEVID__PORTCOUNT__PORTCOUNT_0X6 0x6 +#define DBG_PHYA_FUN_DEVID__PORTCOUNT__PORTCOUNT_0X7 0x7 +#define DBG_PHYA_FUN_DEVID__PORTCOUNT__PORTCOUNT_0X8 0x8 +#define DBG_PHYA_FUN_DEVID___M 0x000000FF +#define DBG_PHYA_FUN_DEVID___S 0 + +#define DBG_PHYA_FUN_DEVTYPE (0x00BE4FCC) +#define DBG_PHYA_FUN_DEVTYPE___RWC QCSR_REG_RO +#define DBG_PHYA_FUN_DEVTYPE___POR 0x00000012 +#define DBG_PHYA_FUN_DEVTYPE__SUB_TYPE___POR 0x1 +#define DBG_PHYA_FUN_DEVTYPE__MAJOR_TYPE___POR 0x2 +#define DBG_PHYA_FUN_DEVTYPE__SUB_TYPE___M 0x000000F0 +#define DBG_PHYA_FUN_DEVTYPE__SUB_TYPE___S 4 +#define DBG_PHYA_FUN_DEVTYPE__SUB_TYPE__SUB_TYPE_0X1 0x1 +#define DBG_PHYA_FUN_DEVTYPE__MAJOR_TYPE___M 0x0000000F +#define DBG_PHYA_FUN_DEVTYPE__MAJOR_TYPE___S 0 +#define DBG_PHYA_FUN_DEVTYPE__MAJOR_TYPE__MAJOR_TYPE_0X2 0x2 +#define DBG_PHYA_FUN_DEVTYPE___M 0x000000FF +#define DBG_PHYA_FUN_DEVTYPE___S 0 + +#define DBG_PHYA_FUN_PIDR0 (0x00BE4FE0) +#define DBG_PHYA_FUN_PIDR0___RWC QCSR_REG_RO +#define DBG_PHYA_FUN_PIDR0___POR 0x00000008 +#define DBG_PHYA_FUN_PIDR0__PART_NUMBER_BITS7TO0___POR 0x08 +#define DBG_PHYA_FUN_PIDR0__PART_NUMBER_BITS7TO0___M 0x000000FF +#define DBG_PHYA_FUN_PIDR0__PART_NUMBER_BITS7TO0___S 0 +#define DBG_PHYA_FUN_PIDR0__PART_NUMBER_BITS7TO0__PART_NUMBER_BITS7TO0_0X08 0x08 +#define DBG_PHYA_FUN_PIDR0___M 0x000000FF +#define DBG_PHYA_FUN_PIDR0___S 0 + +#define DBG_PHYA_FUN_PIDR1 (0x00BE4FE4) +#define DBG_PHYA_FUN_PIDR1___RWC QCSR_REG_RO +#define DBG_PHYA_FUN_PIDR1___POR 0x000000B9 +#define DBG_PHYA_FUN_PIDR1__JEP106_BITS3TO0___POR 0xB +#define DBG_PHYA_FUN_PIDR1__PART_NUMBER_BITS11TO8___POR 0x9 +#define DBG_PHYA_FUN_PIDR1__JEP106_BITS3TO0___M 0x000000F0 +#define DBG_PHYA_FUN_PIDR1__JEP106_BITS3TO0___S 4 +#define DBG_PHYA_FUN_PIDR1__JEP106_BITS3TO0__JEP106_BITS3TO0_0XB 0xB +#define DBG_PHYA_FUN_PIDR1__PART_NUMBER_BITS11TO8___M 0x0000000F +#define DBG_PHYA_FUN_PIDR1__PART_NUMBER_BITS11TO8___S 0 +#define DBG_PHYA_FUN_PIDR1__PART_NUMBER_BITS11TO8__PART_NUMBER_BITS11TO8_0X9 0x9 +#define DBG_PHYA_FUN_PIDR1___M 0x000000FF +#define DBG_PHYA_FUN_PIDR1___S 0 + +#define DBG_PHYA_FUN_PIDR2 (0x00BE4FE8) +#define DBG_PHYA_FUN_PIDR2___RWC QCSR_REG_RO +#define DBG_PHYA_FUN_PIDR2___POR 0x0000003B +#define DBG_PHYA_FUN_PIDR2__REVISION___POR 0x3 +#define DBG_PHYA_FUN_PIDR2__JEDEC___POR 0x1 +#define DBG_PHYA_FUN_PIDR2__JEP106_BITS6TO4___POR 0x3 +#define DBG_PHYA_FUN_PIDR2__REVISION___M 0x000000F0 +#define DBG_PHYA_FUN_PIDR2__REVISION___S 4 +#define DBG_PHYA_FUN_PIDR2__REVISION__REVISION_0X3 0x3 +#define DBG_PHYA_FUN_PIDR2__JEDEC___M 0x00000008 +#define DBG_PHYA_FUN_PIDR2__JEDEC___S 3 +#define DBG_PHYA_FUN_PIDR2__JEDEC__JEDEC_0X1 0x1 +#define DBG_PHYA_FUN_PIDR2__JEP106_BITS6TO4___M 0x00000007 +#define DBG_PHYA_FUN_PIDR2__JEP106_BITS6TO4___S 0 +#define DBG_PHYA_FUN_PIDR2__JEP106_BITS6TO4__JEP106_BITS6TO4_0X3 0x3 +#define DBG_PHYA_FUN_PIDR2___M 0x000000FF +#define DBG_PHYA_FUN_PIDR2___S 0 + +#define DBG_PHYA_FUN_PIDR3 (0x00BE4FEC) +#define DBG_PHYA_FUN_PIDR3___RWC QCSR_REG_RO +#define DBG_PHYA_FUN_PIDR3___POR 0x00000000 +#define DBG_PHYA_FUN_PIDR3__REVAND___POR 0x0 +#define DBG_PHYA_FUN_PIDR3__CUSTOMER_MODIFIED___POR 0x0 +#define DBG_PHYA_FUN_PIDR3__REVAND___M 0x000000F0 +#define DBG_PHYA_FUN_PIDR3__REVAND___S 4 +#define DBG_PHYA_FUN_PIDR3__REVAND__REVAND_0X0 0x0 +#define DBG_PHYA_FUN_PIDR3__CUSTOMER_MODIFIED___M 0x0000000F +#define DBG_PHYA_FUN_PIDR3__CUSTOMER_MODIFIED___S 0 +#define DBG_PHYA_FUN_PIDR3__CUSTOMER_MODIFIED__CUSTOMER_MODIFIED_0X0 0x0 +#define DBG_PHYA_FUN_PIDR3___M 0x000000FF +#define DBG_PHYA_FUN_PIDR3___S 0 + +#define DBG_PHYA_FUN_PIDR4 (0x00BE4FD0) +#define DBG_PHYA_FUN_PIDR4___RWC QCSR_REG_RO +#define DBG_PHYA_FUN_PIDR4___POR 0x00000004 +#define DBG_PHYA_FUN_PIDR4__FOURKB_COUNT___POR 0x0 +#define DBG_PHYA_FUN_PIDR4__JEP106_CONT___POR 0x4 +#define DBG_PHYA_FUN_PIDR4__FOURKB_COUNT___M 0x000000F0 +#define DBG_PHYA_FUN_PIDR4__FOURKB_COUNT___S 4 +#define DBG_PHYA_FUN_PIDR4__FOURKB_COUNT__FOURKB_COUNT_0X0 0x0 +#define DBG_PHYA_FUN_PIDR4__JEP106_CONT___M 0x0000000F +#define DBG_PHYA_FUN_PIDR4__JEP106_CONT___S 0 +#define DBG_PHYA_FUN_PIDR4__JEP106_CONT__JEP106_CONT_0X4 0x4 +#define DBG_PHYA_FUN_PIDR4___M 0x000000FF +#define DBG_PHYA_FUN_PIDR4___S 0 + +#define DBG_PHYA_FUN_PERIPHID5 (0x00BE4FD4) +#define DBG_PHYA_FUN_PERIPHID5___RWC QCSR_REG_RO +#define DBG_PHYA_FUN_PERIPHID5___POR 0x00000000 +#define DBG_PHYA_FUN_PERIPHID5__PERIPHID5___POR 0x00000000 +#define DBG_PHYA_FUN_PERIPHID5__PERIPHID5___M 0xFFFFFFFF +#define DBG_PHYA_FUN_PERIPHID5__PERIPHID5___S 0 +#define DBG_PHYA_FUN_PERIPHID5___M 0xFFFFFFFF +#define DBG_PHYA_FUN_PERIPHID5___S 0 + +#define DBG_PHYA_FUN_PERIPHID6 (0x00BE4FD8) +#define DBG_PHYA_FUN_PERIPHID6___RWC QCSR_REG_RO +#define DBG_PHYA_FUN_PERIPHID6___POR 0x00000000 +#define DBG_PHYA_FUN_PERIPHID6__PERIPHID6___POR 0x00000000 +#define DBG_PHYA_FUN_PERIPHID6__PERIPHID6___M 0xFFFFFFFF +#define DBG_PHYA_FUN_PERIPHID6__PERIPHID6___S 0 +#define DBG_PHYA_FUN_PERIPHID6___M 0xFFFFFFFF +#define DBG_PHYA_FUN_PERIPHID6___S 0 + +#define DBG_PHYA_FUN_PERIPHID7 (0x00BE4FDC) +#define DBG_PHYA_FUN_PERIPHID7___RWC QCSR_REG_RO +#define DBG_PHYA_FUN_PERIPHID7___POR 0x00000000 +#define DBG_PHYA_FUN_PERIPHID7__PERIPHID7___POR 0x00000000 +#define DBG_PHYA_FUN_PERIPHID7__PERIPHID7___M 0xFFFFFFFF +#define DBG_PHYA_FUN_PERIPHID7__PERIPHID7___S 0 +#define DBG_PHYA_FUN_PERIPHID7___M 0xFFFFFFFF +#define DBG_PHYA_FUN_PERIPHID7___S 0 + +#define DBG_PHYA_FUN_CID0 (0x00BE4FF0) +#define DBG_PHYA_FUN_CID0___RWC QCSR_REG_RO +#define DBG_PHYA_FUN_CID0___POR 0x0000000D +#define DBG_PHYA_FUN_CID0__PREAMBLE___POR 0x0D +#define DBG_PHYA_FUN_CID0__PREAMBLE___M 0x000000FF +#define DBG_PHYA_FUN_CID0__PREAMBLE___S 0 +#define DBG_PHYA_FUN_CID0__PREAMBLE__PREAMBLE_0X0D 0x0D +#define DBG_PHYA_FUN_CID0___M 0x000000FF +#define DBG_PHYA_FUN_CID0___S 0 + +#define DBG_PHYA_FUN_CID1 (0x00BE4FF4) +#define DBG_PHYA_FUN_CID1___RWC QCSR_REG_RO +#define DBG_PHYA_FUN_CID1___POR 0x00000090 +#define DBG_PHYA_FUN_CID1__CLASS___POR 0x9 +#define DBG_PHYA_FUN_CID1__PREAMBLE___POR 0x0 +#define DBG_PHYA_FUN_CID1__CLASS___M 0x000000F0 +#define DBG_PHYA_FUN_CID1__CLASS___S 4 +#define DBG_PHYA_FUN_CID1__CLASS__CLASS_0X9 0x9 +#define DBG_PHYA_FUN_CID1__PREAMBLE___M 0x0000000F +#define DBG_PHYA_FUN_CID1__PREAMBLE___S 0 +#define DBG_PHYA_FUN_CID1__PREAMBLE__PREAMBLE_0X0 0x0 +#define DBG_PHYA_FUN_CID1___M 0x000000FF +#define DBG_PHYA_FUN_CID1___S 0 + +#define DBG_PHYA_FUN_CID2 (0x00BE4FF8) +#define DBG_PHYA_FUN_CID2___RWC QCSR_REG_RO +#define DBG_PHYA_FUN_CID2___POR 0x00000005 +#define DBG_PHYA_FUN_CID2__PREAMBLE___POR 0x05 +#define DBG_PHYA_FUN_CID2__PREAMBLE___M 0x000000FF +#define DBG_PHYA_FUN_CID2__PREAMBLE___S 0 +#define DBG_PHYA_FUN_CID2__PREAMBLE__PREAMBLE_0X05 0x05 +#define DBG_PHYA_FUN_CID2___M 0x000000FF +#define DBG_PHYA_FUN_CID2___S 0 + +#define DBG_PHYA_FUN_CID3 (0x00BE4FFC) +#define DBG_PHYA_FUN_CID3___RWC QCSR_REG_RO +#define DBG_PHYA_FUN_CID3___POR 0x000000B1 +#define DBG_PHYA_FUN_CID3__PREAMBLE___POR 0xB1 +#define DBG_PHYA_FUN_CID3__PREAMBLE___M 0x000000FF +#define DBG_PHYA_FUN_CID3__PREAMBLE___S 0 +#define DBG_PHYA_FUN_CID3__PREAMBLE__PREAMBLE_0XB1 0xB1 +#define DBG_PHYA_FUN_CID3___M 0x000000FF +#define DBG_PHYA_FUN_CID3___S 0 + +#define DBG_PHYA_CTI_CTICONTROL (0x00BE5000) +#define DBG_PHYA_CTI_CTICONTROL___RWC QCSR_REG_RW +#define DBG_PHYA_CTI_CTICONTROL___POR 0x00000000 +#define DBG_PHYA_CTI_CTICONTROL__GLBEN___POR 0x0 +#define DBG_PHYA_CTI_CTICONTROL__GLBEN___M 0x00000001 +#define DBG_PHYA_CTI_CTICONTROL__GLBEN___S 0 +#define DBG_PHYA_CTI_CTICONTROL__GLBEN__DISABLED 0x0 +#define DBG_PHYA_CTI_CTICONTROL__GLBEN__ENABLED 0x1 +#define DBG_PHYA_CTI_CTICONTROL___M 0x00000001 +#define DBG_PHYA_CTI_CTICONTROL___S 0 + +#define DBG_PHYA_CTI_CTIINTACK (0x00BE5010) +#define DBG_PHYA_CTI_CTIINTACK___RWC QCSR_REG_WO +#define DBG_PHYA_CTI_CTIINTACK___POR 0x00000000 +#define DBG_PHYA_CTI_CTIINTACK__INTACK___POR 0x000 +#define DBG_PHYA_CTI_CTIINTACK__INTACK___M 0x000003FF +#define DBG_PHYA_CTI_CTIINTACK__INTACK___S 0 +#define DBG_PHYA_CTI_CTIINTACK___M 0x000003FF +#define DBG_PHYA_CTI_CTIINTACK___S 0 + +#define DBG_PHYA_CTI_CTIAPPSET (0x00BE5014) +#define DBG_PHYA_CTI_CTIAPPSET___RWC QCSR_REG_RW +#define DBG_PHYA_CTI_CTIAPPSET___POR 0x00000000 +#define DBG_PHYA_CTI_CTIAPPSET__APPSET___POR 0x00 +#define DBG_PHYA_CTI_CTIAPPSET__APPSET___M 0x000000FF +#define DBG_PHYA_CTI_CTIAPPSET__APPSET___S 0 +#define DBG_PHYA_CTI_CTIAPPSET___M 0x000000FF +#define DBG_PHYA_CTI_CTIAPPSET___S 0 + +#define DBG_PHYA_CTI_CTIAPPCLEAR (0x00BE5018) +#define DBG_PHYA_CTI_CTIAPPCLEAR___RWC QCSR_REG_WO +#define DBG_PHYA_CTI_CTIAPPCLEAR___POR 0x00000000 +#define DBG_PHYA_CTI_CTIAPPCLEAR__APPCLEAR___POR 0x00 +#define DBG_PHYA_CTI_CTIAPPCLEAR__APPCLEAR___M 0x000000FF +#define DBG_PHYA_CTI_CTIAPPCLEAR__APPCLEAR___S 0 +#define DBG_PHYA_CTI_CTIAPPCLEAR___M 0x000000FF +#define DBG_PHYA_CTI_CTIAPPCLEAR___S 0 + +#define DBG_PHYA_CTI_CTIAPPPULSE (0x00BE501C) +#define DBG_PHYA_CTI_CTIAPPPULSE___RWC QCSR_REG_WO +#define DBG_PHYA_CTI_CTIAPPPULSE___POR 0x00000000 +#define DBG_PHYA_CTI_CTIAPPPULSE__APPULSE___POR 0x00 +#define DBG_PHYA_CTI_CTIAPPPULSE__APPULSE___M 0x000000FF +#define DBG_PHYA_CTI_CTIAPPPULSE__APPULSE___S 0 +#define DBG_PHYA_CTI_CTIAPPPULSE___M 0x000000FF +#define DBG_PHYA_CTI_CTIAPPPULSE___S 0 + +#define DBG_PHYA_CTI_CTIINEN0 (0x00BE5020) +#define DBG_PHYA_CTI_CTIINEN0___RWC QCSR_REG_RW +#define DBG_PHYA_CTI_CTIINEN0___POR 0x00000000 +#define DBG_PHYA_CTI_CTIINEN0__TRIGINEN___POR 0x00 +#define DBG_PHYA_CTI_CTIINEN0__TRIGINEN___M 0x000000FF +#define DBG_PHYA_CTI_CTIINEN0__TRIGINEN___S 0 +#define DBG_PHYA_CTI_CTIINEN0___M 0x000000FF +#define DBG_PHYA_CTI_CTIINEN0___S 0 + +#define DBG_PHYA_CTI_CTIINEN1 (0x00BE5024) +#define DBG_PHYA_CTI_CTIINEN1___RWC QCSR_REG_RW +#define DBG_PHYA_CTI_CTIINEN1___POR 0x00000000 +#define DBG_PHYA_CTI_CTIINEN1__TRIGINEN___POR 0x00 +#define DBG_PHYA_CTI_CTIINEN1__TRIGINEN___M 0x000000FF +#define DBG_PHYA_CTI_CTIINEN1__TRIGINEN___S 0 +#define DBG_PHYA_CTI_CTIINEN1___M 0x000000FF +#define DBG_PHYA_CTI_CTIINEN1___S 0 + +#define DBG_PHYA_CTI_CTIINEN2 (0x00BE5028) +#define DBG_PHYA_CTI_CTIINEN2___RWC QCSR_REG_RW +#define DBG_PHYA_CTI_CTIINEN2___POR 0x00000000 +#define DBG_PHYA_CTI_CTIINEN2__TRIGINEN___POR 0x00 +#define DBG_PHYA_CTI_CTIINEN2__TRIGINEN___M 0x000000FF +#define DBG_PHYA_CTI_CTIINEN2__TRIGINEN___S 0 +#define DBG_PHYA_CTI_CTIINEN2___M 0x000000FF +#define DBG_PHYA_CTI_CTIINEN2___S 0 + +#define DBG_PHYA_CTI_CTIINEN3 (0x00BE502C) +#define DBG_PHYA_CTI_CTIINEN3___RWC QCSR_REG_RW +#define DBG_PHYA_CTI_CTIINEN3___POR 0x00000000 +#define DBG_PHYA_CTI_CTIINEN3__TRIGINEN___POR 0x00 +#define DBG_PHYA_CTI_CTIINEN3__TRIGINEN___M 0x000000FF +#define DBG_PHYA_CTI_CTIINEN3__TRIGINEN___S 0 +#define DBG_PHYA_CTI_CTIINEN3___M 0x000000FF +#define DBG_PHYA_CTI_CTIINEN3___S 0 + +#define DBG_PHYA_CTI_CTIINEN4 (0x00BE5030) +#define DBG_PHYA_CTI_CTIINEN4___RWC QCSR_REG_RW +#define DBG_PHYA_CTI_CTIINEN4___POR 0x00000000 +#define DBG_PHYA_CTI_CTIINEN4__TRIGINEN___POR 0x00 +#define DBG_PHYA_CTI_CTIINEN4__TRIGINEN___M 0x000000FF +#define DBG_PHYA_CTI_CTIINEN4__TRIGINEN___S 0 +#define DBG_PHYA_CTI_CTIINEN4___M 0x000000FF +#define DBG_PHYA_CTI_CTIINEN4___S 0 + +#define DBG_PHYA_CTI_CTIINEN5 (0x00BE5034) +#define DBG_PHYA_CTI_CTIINEN5___RWC QCSR_REG_RW +#define DBG_PHYA_CTI_CTIINEN5___POR 0x00000000 +#define DBG_PHYA_CTI_CTIINEN5__TRIGINEN___POR 0x00 +#define DBG_PHYA_CTI_CTIINEN5__TRIGINEN___M 0x000000FF +#define DBG_PHYA_CTI_CTIINEN5__TRIGINEN___S 0 +#define DBG_PHYA_CTI_CTIINEN5___M 0x000000FF +#define DBG_PHYA_CTI_CTIINEN5___S 0 + +#define DBG_PHYA_CTI_CTIINEN6 (0x00BE5038) +#define DBG_PHYA_CTI_CTIINEN6___RWC QCSR_REG_RW +#define DBG_PHYA_CTI_CTIINEN6___POR 0x00000000 +#define DBG_PHYA_CTI_CTIINEN6__TRIGINEN___POR 0x00 +#define DBG_PHYA_CTI_CTIINEN6__TRIGINEN___M 0x000000FF +#define DBG_PHYA_CTI_CTIINEN6__TRIGINEN___S 0 +#define DBG_PHYA_CTI_CTIINEN6___M 0x000000FF +#define DBG_PHYA_CTI_CTIINEN6___S 0 + +#define DBG_PHYA_CTI_CTIINEN7 (0x00BE503C) +#define DBG_PHYA_CTI_CTIINEN7___RWC QCSR_REG_RW +#define DBG_PHYA_CTI_CTIINEN7___POR 0x00000000 +#define DBG_PHYA_CTI_CTIINEN7__TRIGINEN___POR 0x00 +#define DBG_PHYA_CTI_CTIINEN7__TRIGINEN___M 0x000000FF +#define DBG_PHYA_CTI_CTIINEN7__TRIGINEN___S 0 +#define DBG_PHYA_CTI_CTIINEN7___M 0x000000FF +#define DBG_PHYA_CTI_CTIINEN7___S 0 + +#define DBG_PHYA_CTI_CTIINEN8 (0x00BE5040) +#define DBG_PHYA_CTI_CTIINEN8___RWC QCSR_REG_RW +#define DBG_PHYA_CTI_CTIINEN8___POR 0x00000000 +#define DBG_PHYA_CTI_CTIINEN8__TRIGINEN___POR 0x00 +#define DBG_PHYA_CTI_CTIINEN8__TRIGINEN___M 0x000000FF +#define DBG_PHYA_CTI_CTIINEN8__TRIGINEN___S 0 +#define DBG_PHYA_CTI_CTIINEN8___M 0x000000FF +#define DBG_PHYA_CTI_CTIINEN8___S 0 + +#define DBG_PHYA_CTI_CTIINEN9 (0x00BE5044) +#define DBG_PHYA_CTI_CTIINEN9___RWC QCSR_REG_RW +#define DBG_PHYA_CTI_CTIINEN9___POR 0x00000000 +#define DBG_PHYA_CTI_CTIINEN9__TRIGINEN___POR 0x00 +#define DBG_PHYA_CTI_CTIINEN9__TRIGINEN___M 0x000000FF +#define DBG_PHYA_CTI_CTIINEN9__TRIGINEN___S 0 +#define DBG_PHYA_CTI_CTIINEN9___M 0x000000FF +#define DBG_PHYA_CTI_CTIINEN9___S 0 + +#define DBG_PHYA_CTI_CTIOUTEN0 (0x00BE50A0) +#define DBG_PHYA_CTI_CTIOUTEN0___RWC QCSR_REG_RW +#define DBG_PHYA_CTI_CTIOUTEN0___POR 0x00000000 +#define DBG_PHYA_CTI_CTIOUTEN0__TRIGOUTEN___POR 0x00 +#define DBG_PHYA_CTI_CTIOUTEN0__TRIGOUTEN___M 0x000000FF +#define DBG_PHYA_CTI_CTIOUTEN0__TRIGOUTEN___S 0 +#define DBG_PHYA_CTI_CTIOUTEN0___M 0x000000FF +#define DBG_PHYA_CTI_CTIOUTEN0___S 0 + +#define DBG_PHYA_CTI_CTIOUTEN1 (0x00BE50A4) +#define DBG_PHYA_CTI_CTIOUTEN1___RWC QCSR_REG_RW +#define DBG_PHYA_CTI_CTIOUTEN1___POR 0x00000000 +#define DBG_PHYA_CTI_CTIOUTEN1__TRIGOUTEN___POR 0x00 +#define DBG_PHYA_CTI_CTIOUTEN1__TRIGOUTEN___M 0x000000FF +#define DBG_PHYA_CTI_CTIOUTEN1__TRIGOUTEN___S 0 +#define DBG_PHYA_CTI_CTIOUTEN1___M 0x000000FF +#define DBG_PHYA_CTI_CTIOUTEN1___S 0 + +#define DBG_PHYA_CTI_CTIOUTEN2 (0x00BE50A8) +#define DBG_PHYA_CTI_CTIOUTEN2___RWC QCSR_REG_RW +#define DBG_PHYA_CTI_CTIOUTEN2___POR 0x00000000 +#define DBG_PHYA_CTI_CTIOUTEN2__TRIGOUTEN___POR 0x00 +#define DBG_PHYA_CTI_CTIOUTEN2__TRIGOUTEN___M 0x000000FF +#define DBG_PHYA_CTI_CTIOUTEN2__TRIGOUTEN___S 0 +#define DBG_PHYA_CTI_CTIOUTEN2___M 0x000000FF +#define DBG_PHYA_CTI_CTIOUTEN2___S 0 + +#define DBG_PHYA_CTI_CTIOUTEN3 (0x00BE50AC) +#define DBG_PHYA_CTI_CTIOUTEN3___RWC QCSR_REG_RW +#define DBG_PHYA_CTI_CTIOUTEN3___POR 0x00000000 +#define DBG_PHYA_CTI_CTIOUTEN3__TRIGOUTEN___POR 0x00 +#define DBG_PHYA_CTI_CTIOUTEN3__TRIGOUTEN___M 0x000000FF +#define DBG_PHYA_CTI_CTIOUTEN3__TRIGOUTEN___S 0 +#define DBG_PHYA_CTI_CTIOUTEN3___M 0x000000FF +#define DBG_PHYA_CTI_CTIOUTEN3___S 0 + +#define DBG_PHYA_CTI_CTIOUTEN4 (0x00BE50B0) +#define DBG_PHYA_CTI_CTIOUTEN4___RWC QCSR_REG_RW +#define DBG_PHYA_CTI_CTIOUTEN4___POR 0x00000000 +#define DBG_PHYA_CTI_CTIOUTEN4__TRIGOUTEN___POR 0x00 +#define DBG_PHYA_CTI_CTIOUTEN4__TRIGOUTEN___M 0x000000FF +#define DBG_PHYA_CTI_CTIOUTEN4__TRIGOUTEN___S 0 +#define DBG_PHYA_CTI_CTIOUTEN4___M 0x000000FF +#define DBG_PHYA_CTI_CTIOUTEN4___S 0 + +#define DBG_PHYA_CTI_CTIOUTEN5 (0x00BE50B4) +#define DBG_PHYA_CTI_CTIOUTEN5___RWC QCSR_REG_RW +#define DBG_PHYA_CTI_CTIOUTEN5___POR 0x00000000 +#define DBG_PHYA_CTI_CTIOUTEN5__TRIGOUTEN___POR 0x00 +#define DBG_PHYA_CTI_CTIOUTEN5__TRIGOUTEN___M 0x000000FF +#define DBG_PHYA_CTI_CTIOUTEN5__TRIGOUTEN___S 0 +#define DBG_PHYA_CTI_CTIOUTEN5___M 0x000000FF +#define DBG_PHYA_CTI_CTIOUTEN5___S 0 + +#define DBG_PHYA_CTI_CTIOUTEN6 (0x00BE50B8) +#define DBG_PHYA_CTI_CTIOUTEN6___RWC QCSR_REG_RW +#define DBG_PHYA_CTI_CTIOUTEN6___POR 0x00000000 +#define DBG_PHYA_CTI_CTIOUTEN6__TRIGOUTEN___POR 0x00 +#define DBG_PHYA_CTI_CTIOUTEN6__TRIGOUTEN___M 0x000000FF +#define DBG_PHYA_CTI_CTIOUTEN6__TRIGOUTEN___S 0 +#define DBG_PHYA_CTI_CTIOUTEN6___M 0x000000FF +#define DBG_PHYA_CTI_CTIOUTEN6___S 0 + +#define DBG_PHYA_CTI_CTIOUTEN7 (0x00BE50BC) +#define DBG_PHYA_CTI_CTIOUTEN7___RWC QCSR_REG_RW +#define DBG_PHYA_CTI_CTIOUTEN7___POR 0x00000000 +#define DBG_PHYA_CTI_CTIOUTEN7__TRIGOUTEN___POR 0x00 +#define DBG_PHYA_CTI_CTIOUTEN7__TRIGOUTEN___M 0x000000FF +#define DBG_PHYA_CTI_CTIOUTEN7__TRIGOUTEN___S 0 +#define DBG_PHYA_CTI_CTIOUTEN7___M 0x000000FF +#define DBG_PHYA_CTI_CTIOUTEN7___S 0 + +#define DBG_PHYA_CTI_CTIOUTEN8 (0x00BE50C0) +#define DBG_PHYA_CTI_CTIOUTEN8___RWC QCSR_REG_RW +#define DBG_PHYA_CTI_CTIOUTEN8___POR 0x00000000 +#define DBG_PHYA_CTI_CTIOUTEN8__TRIGOUTEN___POR 0x00 +#define DBG_PHYA_CTI_CTIOUTEN8__TRIGOUTEN___M 0x000000FF +#define DBG_PHYA_CTI_CTIOUTEN8__TRIGOUTEN___S 0 +#define DBG_PHYA_CTI_CTIOUTEN8___M 0x000000FF +#define DBG_PHYA_CTI_CTIOUTEN8___S 0 + +#define DBG_PHYA_CTI_CTIOUTEN9 (0x00BE50C4) +#define DBG_PHYA_CTI_CTIOUTEN9___RWC QCSR_REG_RW +#define DBG_PHYA_CTI_CTIOUTEN9___POR 0x00000000 +#define DBG_PHYA_CTI_CTIOUTEN9__TRIGOUTEN___POR 0x00 +#define DBG_PHYA_CTI_CTIOUTEN9__TRIGOUTEN___M 0x000000FF +#define DBG_PHYA_CTI_CTIOUTEN9__TRIGOUTEN___S 0 +#define DBG_PHYA_CTI_CTIOUTEN9___M 0x000000FF +#define DBG_PHYA_CTI_CTIOUTEN9___S 0 + +#define DBG_PHYA_CTI_CTITRIGINSTATUS (0x00BE5130) +#define DBG_PHYA_CTI_CTITRIGINSTATUS___RWC QCSR_REG_RO +#define DBG_PHYA_CTI_CTITRIGINSTATUS__TRIGINSTATUS___M 0x000003FF +#define DBG_PHYA_CTI_CTITRIGINSTATUS__TRIGINSTATUS___S 0 +#define DBG_PHYA_CTI_CTITRIGINSTATUS___M 0x000003FF +#define DBG_PHYA_CTI_CTITRIGINSTATUS___S 0 + +#define DBG_PHYA_CTI_CTITRIGOUTSTATUS (0x00BE5134) +#define DBG_PHYA_CTI_CTITRIGOUTSTATUS___RWC QCSR_REG_RO +#define DBG_PHYA_CTI_CTITRIGOUTSTATUS___POR 0x00000000 +#define DBG_PHYA_CTI_CTITRIGOUTSTATUS__TRIGOUTSTATUS___POR 0x000 +#define DBG_PHYA_CTI_CTITRIGOUTSTATUS__TRIGOUTSTATUS___M 0x000003FF +#define DBG_PHYA_CTI_CTITRIGOUTSTATUS__TRIGOUTSTATUS___S 0 +#define DBG_PHYA_CTI_CTITRIGOUTSTATUS___M 0x000003FF +#define DBG_PHYA_CTI_CTITRIGOUTSTATUS___S 0 + +#define DBG_PHYA_CTI_CTICHINSTATUS (0x00BE5138) +#define DBG_PHYA_CTI_CTICHINSTATUS___RWC QCSR_REG_RO +#define DBG_PHYA_CTI_CTICHINSTATUS__CTICHINSTATUS___M 0x000000FF +#define DBG_PHYA_CTI_CTICHINSTATUS__CTICHINSTATUS___S 0 +#define DBG_PHYA_CTI_CTICHINSTATUS___M 0x000000FF +#define DBG_PHYA_CTI_CTICHINSTATUS___S 0 + +#define DBG_PHYA_CTI_CTICHOUTSTATUS (0x00BE513C) +#define DBG_PHYA_CTI_CTICHOUTSTATUS___RWC QCSR_REG_RO +#define DBG_PHYA_CTI_CTICHOUTSTATUS___POR 0x00000000 +#define DBG_PHYA_CTI_CTICHOUTSTATUS__CTICHOUTSTATUS___POR 0x00 +#define DBG_PHYA_CTI_CTICHOUTSTATUS__CTICHOUTSTATUS___M 0x000000FF +#define DBG_PHYA_CTI_CTICHOUTSTATUS__CTICHOUTSTATUS___S 0 +#define DBG_PHYA_CTI_CTICHOUTSTATUS___M 0x000000FF +#define DBG_PHYA_CTI_CTICHOUTSTATUS___S 0 + +#define DBG_PHYA_CTI_CTIGATE (0x00BE5140) +#define DBG_PHYA_CTI_CTIGATE___RWC QCSR_REG_RW +#define DBG_PHYA_CTI_CTIGATE___POR 0x000000FF +#define DBG_PHYA_CTI_CTIGATE__CTIGATEEN7___POR 0x1 +#define DBG_PHYA_CTI_CTIGATE__CTIGATEEN6___POR 0x1 +#define DBG_PHYA_CTI_CTIGATE__CTIGATEEN5___POR 0x1 +#define DBG_PHYA_CTI_CTIGATE__CTIGATEEN4___POR 0x1 +#define DBG_PHYA_CTI_CTIGATE__CTIGATEEN3___POR 0x1 +#define DBG_PHYA_CTI_CTIGATE__CTIGATEEN2___POR 0x1 +#define DBG_PHYA_CTI_CTIGATE__CTIGATEEN1___POR 0x1 +#define DBG_PHYA_CTI_CTIGATE__CTIGATEEN0___POR 0x1 +#define DBG_PHYA_CTI_CTIGATE__CTIGATEEN7___M 0x00000080 +#define DBG_PHYA_CTI_CTIGATE__CTIGATEEN7___S 7 +#define DBG_PHYA_CTI_CTIGATE__CTIGATEEN6___M 0x00000040 +#define DBG_PHYA_CTI_CTIGATE__CTIGATEEN6___S 6 +#define DBG_PHYA_CTI_CTIGATE__CTIGATEEN5___M 0x00000020 +#define DBG_PHYA_CTI_CTIGATE__CTIGATEEN5___S 5 +#define DBG_PHYA_CTI_CTIGATE__CTIGATEEN4___M 0x00000010 +#define DBG_PHYA_CTI_CTIGATE__CTIGATEEN4___S 4 +#define DBG_PHYA_CTI_CTIGATE__CTIGATEEN3___M 0x00000008 +#define DBG_PHYA_CTI_CTIGATE__CTIGATEEN3___S 3 +#define DBG_PHYA_CTI_CTIGATE__CTIGATEEN2___M 0x00000004 +#define DBG_PHYA_CTI_CTIGATE__CTIGATEEN2___S 2 +#define DBG_PHYA_CTI_CTIGATE__CTIGATEEN1___M 0x00000002 +#define DBG_PHYA_CTI_CTIGATE__CTIGATEEN1___S 1 +#define DBG_PHYA_CTI_CTIGATE__CTIGATEEN0___M 0x00000001 +#define DBG_PHYA_CTI_CTIGATE__CTIGATEEN0___S 0 +#define DBG_PHYA_CTI_CTIGATE___M 0x000000FF +#define DBG_PHYA_CTI_CTIGATE___S 0 + +#define DBG_PHYA_CTI_ASICCTL (0x00BE5144) +#define DBG_PHYA_CTI_ASICCTL___RWC QCSR_REG_RW +#define DBG_PHYA_CTI_ASICCTL___POR 0x00000000 +#define DBG_PHYA_CTI_ASICCTL__ASICCTL___POR 0x00000000 +#define DBG_PHYA_CTI_ASICCTL__ASICCTL___M 0xFFFFFFFF +#define DBG_PHYA_CTI_ASICCTL__ASICCTL___S 0 +#define DBG_PHYA_CTI_ASICCTL___M 0xFFFFFFFF +#define DBG_PHYA_CTI_ASICCTL___S 0 + +#define DBG_PHYA_CTI_ITCHINACK (0x00BE5EDC) +#define DBG_PHYA_CTI_ITCHINACK___RWC QCSR_REG_WO +#define DBG_PHYA_CTI_ITCHINACK___POR 0x00000000 +#define DBG_PHYA_CTI_ITCHINACK__CTCHINACK___POR 0x00 +#define DBG_PHYA_CTI_ITCHINACK__CTCHINACK___M 0x000000FF +#define DBG_PHYA_CTI_ITCHINACK__CTCHINACK___S 0 +#define DBG_PHYA_CTI_ITCHINACK___M 0x000000FF +#define DBG_PHYA_CTI_ITCHINACK___S 0 + +#define DBG_PHYA_CTI_ITTRIGINACK (0x00BE5EE0) +#define DBG_PHYA_CTI_ITTRIGINACK___RWC QCSR_REG_WO +#define DBG_PHYA_CTI_ITTRIGINACK___POR 0x00000000 +#define DBG_PHYA_CTI_ITTRIGINACK__CTTRIGINACK___POR 0x000 +#define DBG_PHYA_CTI_ITTRIGINACK__CTTRIGINACK___M 0x000003FF +#define DBG_PHYA_CTI_ITTRIGINACK__CTTRIGINACK___S 0 +#define DBG_PHYA_CTI_ITTRIGINACK___M 0x000003FF +#define DBG_PHYA_CTI_ITTRIGINACK___S 0 + +#define DBG_PHYA_CTI_ITCHOUT (0x00BE5EE4) +#define DBG_PHYA_CTI_ITCHOUT___RWC QCSR_REG_WO +#define DBG_PHYA_CTI_ITCHOUT___POR 0x00000000 +#define DBG_PHYA_CTI_ITCHOUT__CTCHOUT___POR 0x00 +#define DBG_PHYA_CTI_ITCHOUT__CTCHOUT___M 0x000000FF +#define DBG_PHYA_CTI_ITCHOUT__CTCHOUT___S 0 +#define DBG_PHYA_CTI_ITCHOUT___M 0x000000FF +#define DBG_PHYA_CTI_ITCHOUT___S 0 + +#define DBG_PHYA_CTI_ITTRIGOUT (0x00BE5EE8) +#define DBG_PHYA_CTI_ITTRIGOUT___RWC QCSR_REG_WO +#define DBG_PHYA_CTI_ITTRIGOUT___POR 0x00000000 +#define DBG_PHYA_CTI_ITTRIGOUT__CTTRIGOUT___POR 0x000 +#define DBG_PHYA_CTI_ITTRIGOUT__CTTRIGOUT___M 0x000003FF +#define DBG_PHYA_CTI_ITTRIGOUT__CTTRIGOUT___S 0 +#define DBG_PHYA_CTI_ITTRIGOUT___M 0x000003FF +#define DBG_PHYA_CTI_ITTRIGOUT___S 0 + +#define DBG_PHYA_CTI_ITCHOUTACK (0x00BE5EEC) +#define DBG_PHYA_CTI_ITCHOUTACK___RWC QCSR_REG_RO +#define DBG_PHYA_CTI_ITCHOUTACK___POR 0x00000000 +#define DBG_PHYA_CTI_ITCHOUTACK__CTCHOUTACK___POR 0x00 +#define DBG_PHYA_CTI_ITCHOUTACK__CTCHOUTACK___M 0x000000FF +#define DBG_PHYA_CTI_ITCHOUTACK__CTCHOUTACK___S 0 +#define DBG_PHYA_CTI_ITCHOUTACK___M 0x000000FF +#define DBG_PHYA_CTI_ITCHOUTACK___S 0 + +#define DBG_PHYA_CTI_ITTRIGOUTACK (0x00BE5EF0) +#define DBG_PHYA_CTI_ITTRIGOUTACK___RWC QCSR_REG_RO +#define DBG_PHYA_CTI_ITTRIGOUTACK___POR 0x00000000 +#define DBG_PHYA_CTI_ITTRIGOUTACK__CTTRIGOUTACK___POR 0x000 +#define DBG_PHYA_CTI_ITTRIGOUTACK__CTTRIGOUTACK___M 0x000003FF +#define DBG_PHYA_CTI_ITTRIGOUTACK__CTTRIGOUTACK___S 0 +#define DBG_PHYA_CTI_ITTRIGOUTACK___M 0x000003FF +#define DBG_PHYA_CTI_ITTRIGOUTACK___S 0 + +#define DBG_PHYA_CTI_ITCHIN (0x00BE5EF4) +#define DBG_PHYA_CTI_ITCHIN___RWC QCSR_REG_RO +#define DBG_PHYA_CTI_ITCHIN___POR 0x00000000 +#define DBG_PHYA_CTI_ITCHIN__CTCHIN___POR 0x00 +#define DBG_PHYA_CTI_ITCHIN__CTCHIN___M 0x000000FF +#define DBG_PHYA_CTI_ITCHIN__CTCHIN___S 0 +#define DBG_PHYA_CTI_ITCHIN___M 0x000000FF +#define DBG_PHYA_CTI_ITCHIN___S 0 + +#define DBG_PHYA_CTI_ITTRIGIN (0x00BE5EF8) +#define DBG_PHYA_CTI_ITTRIGIN___RWC QCSR_REG_RO +#define DBG_PHYA_CTI_ITTRIGIN___POR 0x00000000 +#define DBG_PHYA_CTI_ITTRIGIN__CTTRIGIN___POR 0x000 +#define DBG_PHYA_CTI_ITTRIGIN__CTTRIGIN___M 0x000003FF +#define DBG_PHYA_CTI_ITTRIGIN__CTTRIGIN___S 0 +#define DBG_PHYA_CTI_ITTRIGIN___M 0x000003FF +#define DBG_PHYA_CTI_ITTRIGIN___S 0 + +#define DBG_PHYA_CTI_ITCTRL (0x00BE5F00) +#define DBG_PHYA_CTI_ITCTRL___RWC QCSR_REG_RW +#define DBG_PHYA_CTI_ITCTRL___POR 0x00000000 +#define DBG_PHYA_CTI_ITCTRL__INTEGRATION_MODE___POR 0x0 +#define DBG_PHYA_CTI_ITCTRL__INTEGRATION_MODE___M 0x00000001 +#define DBG_PHYA_CTI_ITCTRL__INTEGRATION_MODE___S 0 +#define DBG_PHYA_CTI_ITCTRL__INTEGRATION_MODE__FUNCTIONAL_MODE 0x0 +#define DBG_PHYA_CTI_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE 0x1 +#define DBG_PHYA_CTI_ITCTRL___M 0x00000001 +#define DBG_PHYA_CTI_ITCTRL___S 0 + +#define DBG_PHYA_CTI_CLAIMSET (0x00BE5FA0) +#define DBG_PHYA_CTI_CLAIMSET___RWC QCSR_REG_RW +#define DBG_PHYA_CTI_CLAIMSET___POR 0x0000000F +#define DBG_PHYA_CTI_CLAIMSET__CLAIMSET___POR 0xF +#define DBG_PHYA_CTI_CLAIMSET__CLAIMSET___M 0x0000000F +#define DBG_PHYA_CTI_CLAIMSET__CLAIMSET___S 0 +#define DBG_PHYA_CTI_CLAIMSET__CLAIMSET__CLAIM_TAG_IMPLEMENTED_BITS 0xF +#define DBG_PHYA_CTI_CLAIMSET___M 0x0000000F +#define DBG_PHYA_CTI_CLAIMSET___S 0 + +#define DBG_PHYA_CTI_CLAIMCLR (0x00BE5FA4) +#define DBG_PHYA_CTI_CLAIMCLR___RWC QCSR_REG_RW +#define DBG_PHYA_CTI_CLAIMCLR___POR 0x00000000 +#define DBG_PHYA_CTI_CLAIMCLR__CLAIMCLR___POR 0x0 +#define DBG_PHYA_CTI_CLAIMCLR__CLAIMCLR___M 0x0000000F +#define DBG_PHYA_CTI_CLAIMCLR__CLAIMCLR___S 0 +#define DBG_PHYA_CTI_CLAIMCLR___M 0x0000000F +#define DBG_PHYA_CTI_CLAIMCLR___S 0 + +#define DBG_PHYA_CTI_DEVAFF0 (0x00BE5FA8) +#define DBG_PHYA_CTI_DEVAFF0___RWC QCSR_REG_RO +#define DBG_PHYA_CTI_DEVAFF0___POR 0x00000000 +#define DBG_PHYA_CTI_DEVAFF0__VAL___POR 0x00000000 +#define DBG_PHYA_CTI_DEVAFF0__VAL___M 0xFFFFFFFF +#define DBG_PHYA_CTI_DEVAFF0__VAL___S 0 +#define DBG_PHYA_CTI_DEVAFF0___M 0xFFFFFFFF +#define DBG_PHYA_CTI_DEVAFF0___S 0 + +#define DBG_PHYA_CTI_DEVAFF1 (0x00BE5FAC) +#define DBG_PHYA_CTI_DEVAFF1___RWC QCSR_REG_RO +#define DBG_PHYA_CTI_DEVAFF1___POR 0x00000000 +#define DBG_PHYA_CTI_DEVAFF1__VAL___POR 0x00000000 +#define DBG_PHYA_CTI_DEVAFF1__VAL___M 0xFFFFFFFF +#define DBG_PHYA_CTI_DEVAFF1__VAL___S 0 +#define DBG_PHYA_CTI_DEVAFF1___M 0xFFFFFFFF +#define DBG_PHYA_CTI_DEVAFF1___S 0 + +#define DBG_PHYA_CTI_LAR (0x00BE5FB0) +#define DBG_PHYA_CTI_LAR___RWC QCSR_REG_WO +#define DBG_PHYA_CTI_LAR__ACCESS_W___M 0xFFFFFFFF +#define DBG_PHYA_CTI_LAR__ACCESS_W___S 0 +#define DBG_PHYA_CTI_LAR__ACCESS_W__UNLOCK 0xC5ACCE55 +#define DBG_PHYA_CTI_LAR___M 0xFFFFFFFF +#define DBG_PHYA_CTI_LAR___S 0 + +#define DBG_PHYA_CTI_LSR (0x00BE5FB4) +#define DBG_PHYA_CTI_LSR___RWC QCSR_REG_RO +#define DBG_PHYA_CTI_LSR___POR 0x00000003 +#define DBG_PHYA_CTI_LSR__LOCKTYPE___POR 0x0 +#define DBG_PHYA_CTI_LSR__LOCKGRANT___POR 0x1 +#define DBG_PHYA_CTI_LSR__LOCKEXIST___POR 0x1 +#define DBG_PHYA_CTI_LSR__LOCKTYPE___M 0x00000004 +#define DBG_PHYA_CTI_LSR__LOCKTYPE___S 2 +#define DBG_PHYA_CTI_LSR__LOCKTYPE__SIZE_32BIT 0x0 +#define DBG_PHYA_CTI_LSR__LOCKGRANT___M 0x00000002 +#define DBG_PHYA_CTI_LSR__LOCKGRANT___S 1 +#define DBG_PHYA_CTI_LSR__LOCKGRANT__ACCESS_PERMITTED 0x0 +#define DBG_PHYA_CTI_LSR__LOCKGRANT__DEVICE_LOCKED 0x1 +#define DBG_PHYA_CTI_LSR__LOCKEXIST___M 0x00000001 +#define DBG_PHYA_CTI_LSR__LOCKEXIST___S 0 +#define DBG_PHYA_CTI_LSR__LOCKEXIST__LOCK_NOT_PRESENT 0x0 +#define DBG_PHYA_CTI_LSR__LOCKEXIST__LOCK_PRESENT 0x1 +#define DBG_PHYA_CTI_LSR___M 0x00000007 +#define DBG_PHYA_CTI_LSR___S 0 + +#define DBG_PHYA_CTI_AUTHSTATUS (0x00BE5FB8) +#define DBG_PHYA_CTI_AUTHSTATUS___RWC QCSR_REG_RO +#define DBG_PHYA_CTI_AUTHSTATUS__SNID___M 0x000000C0 +#define DBG_PHYA_CTI_AUTHSTATUS__SNID___S 6 +#define DBG_PHYA_CTI_AUTHSTATUS__SNID__NOT_IMPLEMENTED 0x0 +#define DBG_PHYA_CTI_AUTHSTATUS__SID___M 0x00000030 +#define DBG_PHYA_CTI_AUTHSTATUS__SID___S 4 +#define DBG_PHYA_CTI_AUTHSTATUS__SID__NOT_IMPLEMENTED 0x0 +#define DBG_PHYA_CTI_AUTHSTATUS__NSNID___M 0x0000000C +#define DBG_PHYA_CTI_AUTHSTATUS__NSNID___S 2 +#define DBG_PHYA_CTI_AUTHSTATUS__NSNID__DISABLED 0x2 +#define DBG_PHYA_CTI_AUTHSTATUS__NSNID__ENABLED 0x3 +#define DBG_PHYA_CTI_AUTHSTATUS__NSID___M 0x00000003 +#define DBG_PHYA_CTI_AUTHSTATUS__NSID___S 0 +#define DBG_PHYA_CTI_AUTHSTATUS__NSID__DISABLED 0x2 +#define DBG_PHYA_CTI_AUTHSTATUS__NSID__ENABLED 0x3 +#define DBG_PHYA_CTI_AUTHSTATUS___M 0x000000FF +#define DBG_PHYA_CTI_AUTHSTATUS___S 0 + +#define DBG_PHYA_CTI_DEVARCH (0x00BE5FBC) +#define DBG_PHYA_CTI_DEVARCH___RWC QCSR_REG_RO +#define DBG_PHYA_CTI_DEVARCH___POR 0x8EF00A14 +#define DBG_PHYA_CTI_DEVARCH__ARCHITECT___POR 0x477 +#define DBG_PHYA_CTI_DEVARCH__PRESENT___POR 0x1 +#define DBG_PHYA_CTI_DEVARCH__REVISION___POR 0x0 +#define DBG_PHYA_CTI_DEVARCH__ARCHID___POR 0x0A14 +#define DBG_PHYA_CTI_DEVARCH__ARCHITECT___M 0xFFE00000 +#define DBG_PHYA_CTI_DEVARCH__ARCHITECT___S 21 +#define DBG_PHYA_CTI_DEVARCH__PRESENT___M 0x00100000 +#define DBG_PHYA_CTI_DEVARCH__PRESENT___S 20 +#define DBG_PHYA_CTI_DEVARCH__REVISION___M 0x000F0000 +#define DBG_PHYA_CTI_DEVARCH__REVISION___S 16 +#define DBG_PHYA_CTI_DEVARCH__ARCHID___M 0x0000FFFF +#define DBG_PHYA_CTI_DEVARCH__ARCHID___S 0 +#define DBG_PHYA_CTI_DEVARCH___M 0xFFFFFFFF +#define DBG_PHYA_CTI_DEVARCH___S 0 + +#define DBG_PHYA_CTI_DEVID2 (0x00BE5FC0) +#define DBG_PHYA_CTI_DEVID2___RWC QCSR_REG_RO +#define DBG_PHYA_CTI_DEVID2___POR 0x00000000 +#define DBG_PHYA_CTI_DEVID2__IMPLDEF___POR 0x0 +#define DBG_PHYA_CTI_DEVID2__IMPLDEF___M 0x00000001 +#define DBG_PHYA_CTI_DEVID2__IMPLDEF___S 0 +#define DBG_PHYA_CTI_DEVID2___M 0x00000001 +#define DBG_PHYA_CTI_DEVID2___S 0 + +#define DBG_PHYA_CTI_DEVID1 (0x00BE5FC4) +#define DBG_PHYA_CTI_DEVID1___RWC QCSR_REG_RO +#define DBG_PHYA_CTI_DEVID1___POR 0x00000000 +#define DBG_PHYA_CTI_DEVID1__IMPLDEF___POR 0x0 +#define DBG_PHYA_CTI_DEVID1__IMPLDEF___M 0x00000001 +#define DBG_PHYA_CTI_DEVID1__IMPLDEF___S 0 +#define DBG_PHYA_CTI_DEVID1___M 0x00000001 +#define DBG_PHYA_CTI_DEVID1___S 0 + +#define DBG_PHYA_CTI_DEVID (0x00BE5FC8) +#define DBG_PHYA_CTI_DEVID___RWC QCSR_REG_RO +#define DBG_PHYA_CTI_DEVID___POR 0x00080A00 +#define DBG_PHYA_CTI_DEVID__NUMCH___POR 0x8 +#define DBG_PHYA_CTI_DEVID__NUMTRIG___POR 0xA +#define DBG_PHYA_CTI_DEVID__EXTMUXNUM___POR 0x00 +#define DBG_PHYA_CTI_DEVID__NUMCH___M 0x003F0000 +#define DBG_PHYA_CTI_DEVID__NUMCH___S 16 +#define DBG_PHYA_CTI_DEVID__NUMTRIG___M 0x0000FF00 +#define DBG_PHYA_CTI_DEVID__NUMTRIG___S 8 +#define DBG_PHYA_CTI_DEVID__EXTMUXNUM___M 0x0000001F +#define DBG_PHYA_CTI_DEVID__EXTMUXNUM___S 0 +#define DBG_PHYA_CTI_DEVID___M 0x003FFF1F +#define DBG_PHYA_CTI_DEVID___S 0 + +#define DBG_PHYA_CTI_DEVTYPE (0x00BE5FCC) +#define DBG_PHYA_CTI_DEVTYPE___RWC QCSR_REG_RO +#define DBG_PHYA_CTI_DEVTYPE___POR 0x00000014 +#define DBG_PHYA_CTI_DEVTYPE__SUB_TYPE___POR 0x1 +#define DBG_PHYA_CTI_DEVTYPE__MAJOR_TYPE___POR 0x4 +#define DBG_PHYA_CTI_DEVTYPE__SUB_TYPE___M 0x000000F0 +#define DBG_PHYA_CTI_DEVTYPE__SUB_TYPE___S 4 +#define DBG_PHYA_CTI_DEVTYPE__SUB_TYPE__TRIGGER_MATRIX 0x1 +#define DBG_PHYA_CTI_DEVTYPE__MAJOR_TYPE___M 0x0000000F +#define DBG_PHYA_CTI_DEVTYPE__MAJOR_TYPE___S 0 +#define DBG_PHYA_CTI_DEVTYPE__MAJOR_TYPE__DEBUG_CONTROL 0x4 +#define DBG_PHYA_CTI_DEVTYPE___M 0x000000FF +#define DBG_PHYA_CTI_DEVTYPE___S 0 + +#define DBG_PHYA_CTI_PIDR0 (0x00BE5FE0) +#define DBG_PHYA_CTI_PIDR0___RWC QCSR_REG_RO +#define DBG_PHYA_CTI_PIDR0___POR 0x00000006 +#define DBG_PHYA_CTI_PIDR0__PART_0___POR 0x06 +#define DBG_PHYA_CTI_PIDR0__PART_0___M 0x000000FF +#define DBG_PHYA_CTI_PIDR0__PART_0___S 0 +#define DBG_PHYA_CTI_PIDR0__PART_0__CTI_PART_NUMBER_7_0 0x06 +#define DBG_PHYA_CTI_PIDR0___M 0x000000FF +#define DBG_PHYA_CTI_PIDR0___S 0 + +#define DBG_PHYA_CTI_PIDR1 (0x00BE5FE4) +#define DBG_PHYA_CTI_PIDR1___RWC QCSR_REG_RO +#define DBG_PHYA_CTI_PIDR1___POR 0x000000B9 +#define DBG_PHYA_CTI_PIDR1__DES_0___POR 0xB +#define DBG_PHYA_CTI_PIDR1__PART_1___POR 0x9 +#define DBG_PHYA_CTI_PIDR1__DES_0___M 0x000000F0 +#define DBG_PHYA_CTI_PIDR1__DES_0___S 4 +#define DBG_PHYA_CTI_PIDR1__DES_0__ARM_JEP106_IDENTITY_CODE_3_0 0xB +#define DBG_PHYA_CTI_PIDR1__PART_1___M 0x0000000F +#define DBG_PHYA_CTI_PIDR1__PART_1___S 0 +#define DBG_PHYA_CTI_PIDR1__PART_1__CTI_PART_NUMBER_11_8 0x9 +#define DBG_PHYA_CTI_PIDR1___M 0x000000FF +#define DBG_PHYA_CTI_PIDR1___S 0 + +#define DBG_PHYA_CTI_PIDR2 (0x00BE5FE8) +#define DBG_PHYA_CTI_PIDR2___RWC QCSR_REG_RO +#define DBG_PHYA_CTI_PIDR2___POR 0x0000004B +#define DBG_PHYA_CTI_PIDR2__REVISION___POR 0x4 +#define DBG_PHYA_CTI_PIDR2__JEDEC___POR 0x1 +#define DBG_PHYA_CTI_PIDR2__DES_1___POR 0x3 +#define DBG_PHYA_CTI_PIDR2__REVISION___M 0x000000F0 +#define DBG_PHYA_CTI_PIDR2__REVISION___S 4 +#define DBG_PHYA_CTI_PIDR2__REVISION__R0P4 0x4 +#define DBG_PHYA_CTI_PIDR2__REVISION__R0P5 0x5 +#define DBG_PHYA_CTI_PIDR2__JEDEC___M 0x00000008 +#define DBG_PHYA_CTI_PIDR2__JEDEC___S 3 +#define DBG_PHYA_CTI_PIDR2__JEDEC__JEDEC_IDENTITY 0x1 +#define DBG_PHYA_CTI_PIDR2__DES_1___M 0x00000007 +#define DBG_PHYA_CTI_PIDR2__DES_1___S 0 +#define DBG_PHYA_CTI_PIDR2__DES_1__ARM_JEP106_IDENTITY_CODE_6_4 0x3 +#define DBG_PHYA_CTI_PIDR2___M 0x000000FF +#define DBG_PHYA_CTI_PIDR2___S 0 + +#define DBG_PHYA_CTI_PIDR3 (0x00BE5FEC) +#define DBG_PHYA_CTI_PIDR3___RWC QCSR_REG_RO +#define DBG_PHYA_CTI_PIDR3___POR 0x00000000 +#define DBG_PHYA_CTI_PIDR3__REVAND___POR 0x0 +#define DBG_PHYA_CTI_PIDR3__CMOD___POR 0x0 +#define DBG_PHYA_CTI_PIDR3__REVAND___M 0x000000F0 +#define DBG_PHYA_CTI_PIDR3__REVAND___S 4 +#define DBG_PHYA_CTI_PIDR3__REVAND__NO_MODIFICATION 0x0 +#define DBG_PHYA_CTI_PIDR3__CMOD___M 0x0000000F +#define DBG_PHYA_CTI_PIDR3__CMOD___S 0 +#define DBG_PHYA_CTI_PIDR3__CMOD__NO_MODIFICATION 0x0 +#define DBG_PHYA_CTI_PIDR3___M 0x000000FF +#define DBG_PHYA_CTI_PIDR3___S 0 + +#define DBG_PHYA_CTI_PIDR4 (0x00BE5FD0) +#define DBG_PHYA_CTI_PIDR4___RWC QCSR_REG_RO +#define DBG_PHYA_CTI_PIDR4___POR 0x00000004 +#define DBG_PHYA_CTI_PIDR4__SIZE___POR 0x0 +#define DBG_PHYA_CTI_PIDR4__DES_2___POR 0x4 +#define DBG_PHYA_CTI_PIDR4__SIZE___M 0x000000F0 +#define DBG_PHYA_CTI_PIDR4__SIZE___S 4 +#define DBG_PHYA_CTI_PIDR4__SIZE__SIZE_4KB 0x0 +#define DBG_PHYA_CTI_PIDR4__DES_2___M 0x0000000F +#define DBG_PHYA_CTI_PIDR4__DES_2___S 0 +#define DBG_PHYA_CTI_PIDR4__DES_2__ARM_JEP106_CONTINUATION_CODE 0x4 +#define DBG_PHYA_CTI_PIDR4___M 0x000000FF +#define DBG_PHYA_CTI_PIDR4___S 0 + +#define DBG_PHYA_CTI_PIDR5 (0x00BE5FD4) +#define DBG_PHYA_CTI_PIDR5___RWC QCSR_REG_RW +#define DBG_PHYA_CTI_PIDR5__PERIPHID5___M 0xFFFFFFFF +#define DBG_PHYA_CTI_PIDR5__PERIPHID5___S 0 +#define DBG_PHYA_CTI_PIDR5___M 0xFFFFFFFF +#define DBG_PHYA_CTI_PIDR5___S 0 + +#define DBG_PHYA_CTI_PIDR6 (0x00BE5FD8) +#define DBG_PHYA_CTI_PIDR6___RWC QCSR_REG_RW +#define DBG_PHYA_CTI_PIDR6__PERIPHID6___M 0xFFFFFFFF +#define DBG_PHYA_CTI_PIDR6__PERIPHID6___S 0 +#define DBG_PHYA_CTI_PIDR6___M 0xFFFFFFFF +#define DBG_PHYA_CTI_PIDR6___S 0 + +#define DBG_PHYA_CTI_PIDR7 (0x00BE5FDC) +#define DBG_PHYA_CTI_PIDR7___RWC QCSR_REG_RW +#define DBG_PHYA_CTI_PIDR7__PERIPHID7___M 0xFFFFFFFF +#define DBG_PHYA_CTI_PIDR7__PERIPHID7___S 0 +#define DBG_PHYA_CTI_PIDR7___M 0xFFFFFFFF +#define DBG_PHYA_CTI_PIDR7___S 0 + +#define DBG_PHYA_CTI_CIDR0 (0x00BE5FF0) +#define DBG_PHYA_CTI_CIDR0___RWC QCSR_REG_RO +#define DBG_PHYA_CTI_CIDR0___POR 0x0000000D +#define DBG_PHYA_CTI_CIDR0__PRMBL_0___POR 0x0D +#define DBG_PHYA_CTI_CIDR0__PRMBL_0___M 0x000000FF +#define DBG_PHYA_CTI_CIDR0__PRMBL_0___S 0 +#define DBG_PHYA_CTI_CIDR0__PRMBL_0__ID_VALUE_0D 0x0D +#define DBG_PHYA_CTI_CIDR0___M 0x000000FF +#define DBG_PHYA_CTI_CIDR0___S 0 + +#define DBG_PHYA_CTI_CIDR1 (0x00BE5FF4) +#define DBG_PHYA_CTI_CIDR1___RWC QCSR_REG_RO +#define DBG_PHYA_CTI_CIDR1___POR 0x00000090 +#define DBG_PHYA_CTI_CIDR1__CLASS___POR 0x9 +#define DBG_PHYA_CTI_CIDR1__PRMBL_1___POR 0x0 +#define DBG_PHYA_CTI_CIDR1__CLASS___M 0x000000F0 +#define DBG_PHYA_CTI_CIDR1__CLASS___S 4 +#define DBG_PHYA_CTI_CIDR1__CLASS__CORESIGHT_COMPONENT 0x9 +#define DBG_PHYA_CTI_CIDR1__PRMBL_1___M 0x0000000F +#define DBG_PHYA_CTI_CIDR1__PRMBL_1___S 0 +#define DBG_PHYA_CTI_CIDR1__PRMBL_1__ID_VALUE_0 0x0 +#define DBG_PHYA_CTI_CIDR1___M 0x000000FF +#define DBG_PHYA_CTI_CIDR1___S 0 + +#define DBG_PHYA_CTI_CIDR2 (0x00BE5FF8) +#define DBG_PHYA_CTI_CIDR2___RWC QCSR_REG_RO +#define DBG_PHYA_CTI_CIDR2___POR 0x00000005 +#define DBG_PHYA_CTI_CIDR2__PRMBL_2___POR 0x05 +#define DBG_PHYA_CTI_CIDR2__PRMBL_2___M 0x000000FF +#define DBG_PHYA_CTI_CIDR2__PRMBL_2___S 0 +#define DBG_PHYA_CTI_CIDR2__PRMBL_2__ID_VALUE_05 0x05 +#define DBG_PHYA_CTI_CIDR2___M 0x000000FF +#define DBG_PHYA_CTI_CIDR2___S 0 + +#define DBG_PHYA_CTI_CIDR3 (0x00BE5FFC) +#define DBG_PHYA_CTI_CIDR3___RWC QCSR_REG_RO +#define DBG_PHYA_CTI_CIDR3___POR 0x000000B1 +#define DBG_PHYA_CTI_CIDR3__PRMBL_3___POR 0xB1 +#define DBG_PHYA_CTI_CIDR3__PRMBL_3___M 0x000000FF +#define DBG_PHYA_CTI_CIDR3__PRMBL_3___S 0 +#define DBG_PHYA_CTI_CIDR3__PRMBL_3__ID_VALUE_B1 0xB1 +#define DBG_PHYA_CTI_CIDR3___M 0x000000FF +#define DBG_PHYA_CTI_CIDR3___S 0 + +#define DBG_PHYA_TRC_CFG (0x00BE6000) +#define DBG_PHYA_TRC_CFG___RWC QCSR_REG_RW +#define DBG_PHYA_TRC_CFG___POR 0x00006E03 +#define DBG_PHYA_TRC_CFG__ATID___POR 0x6E +#define DBG_PHYA_TRC_CFG__TSTMPEN___POR 0x1 +#define DBG_PHYA_TRC_CFG__ENABLE___POR 0x1 +#define DBG_PHYA_TRC_CFG__ATID___M 0x00007F00 +#define DBG_PHYA_TRC_CFG__ATID___S 8 +#define DBG_PHYA_TRC_CFG__TSTMPEN___M 0x00000002 +#define DBG_PHYA_TRC_CFG__TSTMPEN___S 1 +#define DBG_PHYA_TRC_CFG__ENABLE___M 0x00000001 +#define DBG_PHYA_TRC_CFG__ENABLE___S 0 +#define DBG_PHYA_TRC_CFG___M 0x00007F03 +#define DBG_PHYA_TRC_CFG___S 0 + +#define DBG_PHYA_ITM_WR_STIMn(n) (0x00BE8000+0x4*(n)) +#define DBG_PHYA_ITM_WR_STIMn_nMIN 0 +#define DBG_PHYA_ITM_WR_STIMn_nMAX 31 +#define DBG_PHYA_ITM_WR_STIMn_ELEM 32 +#define DBG_PHYA_ITM_WR_STIMn___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_WR_STIMn___POR 0x00000000 +#define DBG_PHYA_ITM_WR_STIMn__STIMULUS___POR 0x00000000 +#define DBG_PHYA_ITM_WR_STIMn__STIMULUS___M 0xFFFFFFFF +#define DBG_PHYA_ITM_WR_STIMn__STIMULUS___S 0 +#define DBG_PHYA_ITM_WR_STIMn___M 0xFFFFFFFF +#define DBG_PHYA_ITM_WR_STIMn___S 0 +#define DBG_PHYA_ITM_WR_STIM0 (0x00BE8000) +#define DBG_PHYA_ITM_WR_STIM0___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_WR_STIM0__STIMULUS___M 0xFFFFFFFF +#define DBG_PHYA_ITM_WR_STIM0__STIMULUS___S 0 +#define DBG_PHYA_ITM_WR_STIM1 (0x00BE8004) +#define DBG_PHYA_ITM_WR_STIM1___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_WR_STIM1__STIMULUS___M 0xFFFFFFFF +#define DBG_PHYA_ITM_WR_STIM1__STIMULUS___S 0 +#define DBG_PHYA_ITM_WR_STIM2 (0x00BE8008) +#define DBG_PHYA_ITM_WR_STIM2___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_WR_STIM2__STIMULUS___M 0xFFFFFFFF +#define DBG_PHYA_ITM_WR_STIM2__STIMULUS___S 0 +#define DBG_PHYA_ITM_WR_STIM3 (0x00BE800C) +#define DBG_PHYA_ITM_WR_STIM3___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_WR_STIM3__STIMULUS___M 0xFFFFFFFF +#define DBG_PHYA_ITM_WR_STIM3__STIMULUS___S 0 +#define DBG_PHYA_ITM_WR_STIM4 (0x00BE8010) +#define DBG_PHYA_ITM_WR_STIM4___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_WR_STIM4__STIMULUS___M 0xFFFFFFFF +#define DBG_PHYA_ITM_WR_STIM4__STIMULUS___S 0 +#define DBG_PHYA_ITM_WR_STIM5 (0x00BE8014) +#define DBG_PHYA_ITM_WR_STIM5___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_WR_STIM5__STIMULUS___M 0xFFFFFFFF +#define DBG_PHYA_ITM_WR_STIM5__STIMULUS___S 0 +#define DBG_PHYA_ITM_WR_STIM6 (0x00BE8018) +#define DBG_PHYA_ITM_WR_STIM6___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_WR_STIM6__STIMULUS___M 0xFFFFFFFF +#define DBG_PHYA_ITM_WR_STIM6__STIMULUS___S 0 +#define DBG_PHYA_ITM_WR_STIM7 (0x00BE801C) +#define DBG_PHYA_ITM_WR_STIM7___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_WR_STIM7__STIMULUS___M 0xFFFFFFFF +#define DBG_PHYA_ITM_WR_STIM7__STIMULUS___S 0 +#define DBG_PHYA_ITM_WR_STIM8 (0x00BE8020) +#define DBG_PHYA_ITM_WR_STIM8___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_WR_STIM8__STIMULUS___M 0xFFFFFFFF +#define DBG_PHYA_ITM_WR_STIM8__STIMULUS___S 0 +#define DBG_PHYA_ITM_WR_STIM9 (0x00BE8024) +#define DBG_PHYA_ITM_WR_STIM9___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_WR_STIM9__STIMULUS___M 0xFFFFFFFF +#define DBG_PHYA_ITM_WR_STIM9__STIMULUS___S 0 +#define DBG_PHYA_ITM_WR_STIM10 (0x00BE8028) +#define DBG_PHYA_ITM_WR_STIM10___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_WR_STIM10__STIMULUS___M 0xFFFFFFFF +#define DBG_PHYA_ITM_WR_STIM10__STIMULUS___S 0 +#define DBG_PHYA_ITM_WR_STIM11 (0x00BE802C) +#define DBG_PHYA_ITM_WR_STIM11___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_WR_STIM11__STIMULUS___M 0xFFFFFFFF +#define DBG_PHYA_ITM_WR_STIM11__STIMULUS___S 0 +#define DBG_PHYA_ITM_WR_STIM12 (0x00BE8030) +#define DBG_PHYA_ITM_WR_STIM12___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_WR_STIM12__STIMULUS___M 0xFFFFFFFF +#define DBG_PHYA_ITM_WR_STIM12__STIMULUS___S 0 +#define DBG_PHYA_ITM_WR_STIM13 (0x00BE8034) +#define DBG_PHYA_ITM_WR_STIM13___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_WR_STIM13__STIMULUS___M 0xFFFFFFFF +#define DBG_PHYA_ITM_WR_STIM13__STIMULUS___S 0 +#define DBG_PHYA_ITM_WR_STIM14 (0x00BE8038) +#define DBG_PHYA_ITM_WR_STIM14___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_WR_STIM14__STIMULUS___M 0xFFFFFFFF +#define DBG_PHYA_ITM_WR_STIM14__STIMULUS___S 0 +#define DBG_PHYA_ITM_WR_STIM15 (0x00BE803C) +#define DBG_PHYA_ITM_WR_STIM15___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_WR_STIM15__STIMULUS___M 0xFFFFFFFF +#define DBG_PHYA_ITM_WR_STIM15__STIMULUS___S 0 +#define DBG_PHYA_ITM_WR_STIM16 (0x00BE8040) +#define DBG_PHYA_ITM_WR_STIM16___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_WR_STIM16__STIMULUS___M 0xFFFFFFFF +#define DBG_PHYA_ITM_WR_STIM16__STIMULUS___S 0 +#define DBG_PHYA_ITM_WR_STIM17 (0x00BE8044) +#define DBG_PHYA_ITM_WR_STIM17___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_WR_STIM17__STIMULUS___M 0xFFFFFFFF +#define DBG_PHYA_ITM_WR_STIM17__STIMULUS___S 0 +#define DBG_PHYA_ITM_WR_STIM18 (0x00BE8048) +#define DBG_PHYA_ITM_WR_STIM18___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_WR_STIM18__STIMULUS___M 0xFFFFFFFF +#define DBG_PHYA_ITM_WR_STIM18__STIMULUS___S 0 +#define DBG_PHYA_ITM_WR_STIM19 (0x00BE804C) +#define DBG_PHYA_ITM_WR_STIM19___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_WR_STIM19__STIMULUS___M 0xFFFFFFFF +#define DBG_PHYA_ITM_WR_STIM19__STIMULUS___S 0 +#define DBG_PHYA_ITM_WR_STIM20 (0x00BE8050) +#define DBG_PHYA_ITM_WR_STIM20___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_WR_STIM20__STIMULUS___M 0xFFFFFFFF +#define DBG_PHYA_ITM_WR_STIM20__STIMULUS___S 0 +#define DBG_PHYA_ITM_WR_STIM21 (0x00BE8054) +#define DBG_PHYA_ITM_WR_STIM21___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_WR_STIM21__STIMULUS___M 0xFFFFFFFF +#define DBG_PHYA_ITM_WR_STIM21__STIMULUS___S 0 +#define DBG_PHYA_ITM_WR_STIM22 (0x00BE8058) +#define DBG_PHYA_ITM_WR_STIM22___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_WR_STIM22__STIMULUS___M 0xFFFFFFFF +#define DBG_PHYA_ITM_WR_STIM22__STIMULUS___S 0 +#define DBG_PHYA_ITM_WR_STIM23 (0x00BE805C) +#define DBG_PHYA_ITM_WR_STIM23___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_WR_STIM23__STIMULUS___M 0xFFFFFFFF +#define DBG_PHYA_ITM_WR_STIM23__STIMULUS___S 0 +#define DBG_PHYA_ITM_WR_STIM24 (0x00BE8060) +#define DBG_PHYA_ITM_WR_STIM24___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_WR_STIM24__STIMULUS___M 0xFFFFFFFF +#define DBG_PHYA_ITM_WR_STIM24__STIMULUS___S 0 +#define DBG_PHYA_ITM_WR_STIM25 (0x00BE8064) +#define DBG_PHYA_ITM_WR_STIM25___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_WR_STIM25__STIMULUS___M 0xFFFFFFFF +#define DBG_PHYA_ITM_WR_STIM25__STIMULUS___S 0 +#define DBG_PHYA_ITM_WR_STIM26 (0x00BE8068) +#define DBG_PHYA_ITM_WR_STIM26___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_WR_STIM26__STIMULUS___M 0xFFFFFFFF +#define DBG_PHYA_ITM_WR_STIM26__STIMULUS___S 0 +#define DBG_PHYA_ITM_WR_STIM27 (0x00BE806C) +#define DBG_PHYA_ITM_WR_STIM27___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_WR_STIM27__STIMULUS___M 0xFFFFFFFF +#define DBG_PHYA_ITM_WR_STIM27__STIMULUS___S 0 +#define DBG_PHYA_ITM_WR_STIM28 (0x00BE8070) +#define DBG_PHYA_ITM_WR_STIM28___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_WR_STIM28__STIMULUS___M 0xFFFFFFFF +#define DBG_PHYA_ITM_WR_STIM28__STIMULUS___S 0 +#define DBG_PHYA_ITM_WR_STIM29 (0x00BE8074) +#define DBG_PHYA_ITM_WR_STIM29___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_WR_STIM29__STIMULUS___M 0xFFFFFFFF +#define DBG_PHYA_ITM_WR_STIM29__STIMULUS___S 0 +#define DBG_PHYA_ITM_WR_STIM30 (0x00BE8078) +#define DBG_PHYA_ITM_WR_STIM30___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_WR_STIM30__STIMULUS___M 0xFFFFFFFF +#define DBG_PHYA_ITM_WR_STIM30__STIMULUS___S 0 +#define DBG_PHYA_ITM_WR_STIM31 (0x00BE807C) +#define DBG_PHYA_ITM_WR_STIM31___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_WR_STIM31__STIMULUS___M 0xFFFFFFFF +#define DBG_PHYA_ITM_WR_STIM31__STIMULUS___S 0 + +#define DBG_PHYA_ITM_RD_STIMn(n) (0x00BE8000+0x4*(n)) +#define DBG_PHYA_ITM_RD_STIMn_nMIN 0 +#define DBG_PHYA_ITM_RD_STIMn_nMAX 31 +#define DBG_PHYA_ITM_RD_STIMn_ELEM 32 +#define DBG_PHYA_ITM_RD_STIMn___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_RD_STIMn___POR 0x00000001 +#define DBG_PHYA_ITM_RD_STIMn__FIFOREADY___POR 0x1 +#define DBG_PHYA_ITM_RD_STIMn__FIFOREADY___M 0x00000001 +#define DBG_PHYA_ITM_RD_STIMn__FIFOREADY___S 0 +#define DBG_PHYA_ITM_RD_STIMn__FIFOREADY__FULL 0x0 +#define DBG_PHYA_ITM_RD_STIMn__FIFOREADY__READY 0x1 +#define DBG_PHYA_ITM_RD_STIMn___M 0x00000001 +#define DBG_PHYA_ITM_RD_STIMn___S 0 +#define DBG_PHYA_ITM_RD_STIM0 (0x00BE8000) +#define DBG_PHYA_ITM_RD_STIM0___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_RD_STIM0__FIFOREADY___M 0x00000001 +#define DBG_PHYA_ITM_RD_STIM0__FIFOREADY___S 0 +#define DBG_PHYA_ITM_RD_STIM1 (0x00BE8004) +#define DBG_PHYA_ITM_RD_STIM1___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_RD_STIM1__FIFOREADY___M 0x00000001 +#define DBG_PHYA_ITM_RD_STIM1__FIFOREADY___S 0 +#define DBG_PHYA_ITM_RD_STIM2 (0x00BE8008) +#define DBG_PHYA_ITM_RD_STIM2___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_RD_STIM2__FIFOREADY___M 0x00000001 +#define DBG_PHYA_ITM_RD_STIM2__FIFOREADY___S 0 +#define DBG_PHYA_ITM_RD_STIM3 (0x00BE800C) +#define DBG_PHYA_ITM_RD_STIM3___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_RD_STIM3__FIFOREADY___M 0x00000001 +#define DBG_PHYA_ITM_RD_STIM3__FIFOREADY___S 0 +#define DBG_PHYA_ITM_RD_STIM4 (0x00BE8010) +#define DBG_PHYA_ITM_RD_STIM4___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_RD_STIM4__FIFOREADY___M 0x00000001 +#define DBG_PHYA_ITM_RD_STIM4__FIFOREADY___S 0 +#define DBG_PHYA_ITM_RD_STIM5 (0x00BE8014) +#define DBG_PHYA_ITM_RD_STIM5___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_RD_STIM5__FIFOREADY___M 0x00000001 +#define DBG_PHYA_ITM_RD_STIM5__FIFOREADY___S 0 +#define DBG_PHYA_ITM_RD_STIM6 (0x00BE8018) +#define DBG_PHYA_ITM_RD_STIM6___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_RD_STIM6__FIFOREADY___M 0x00000001 +#define DBG_PHYA_ITM_RD_STIM6__FIFOREADY___S 0 +#define DBG_PHYA_ITM_RD_STIM7 (0x00BE801C) +#define DBG_PHYA_ITM_RD_STIM7___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_RD_STIM7__FIFOREADY___M 0x00000001 +#define DBG_PHYA_ITM_RD_STIM7__FIFOREADY___S 0 +#define DBG_PHYA_ITM_RD_STIM8 (0x00BE8020) +#define DBG_PHYA_ITM_RD_STIM8___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_RD_STIM8__FIFOREADY___M 0x00000001 +#define DBG_PHYA_ITM_RD_STIM8__FIFOREADY___S 0 +#define DBG_PHYA_ITM_RD_STIM9 (0x00BE8024) +#define DBG_PHYA_ITM_RD_STIM9___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_RD_STIM9__FIFOREADY___M 0x00000001 +#define DBG_PHYA_ITM_RD_STIM9__FIFOREADY___S 0 +#define DBG_PHYA_ITM_RD_STIM10 (0x00BE8028) +#define DBG_PHYA_ITM_RD_STIM10___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_RD_STIM10__FIFOREADY___M 0x00000001 +#define DBG_PHYA_ITM_RD_STIM10__FIFOREADY___S 0 +#define DBG_PHYA_ITM_RD_STIM11 (0x00BE802C) +#define DBG_PHYA_ITM_RD_STIM11___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_RD_STIM11__FIFOREADY___M 0x00000001 +#define DBG_PHYA_ITM_RD_STIM11__FIFOREADY___S 0 +#define DBG_PHYA_ITM_RD_STIM12 (0x00BE8030) +#define DBG_PHYA_ITM_RD_STIM12___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_RD_STIM12__FIFOREADY___M 0x00000001 +#define DBG_PHYA_ITM_RD_STIM12__FIFOREADY___S 0 +#define DBG_PHYA_ITM_RD_STIM13 (0x00BE8034) +#define DBG_PHYA_ITM_RD_STIM13___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_RD_STIM13__FIFOREADY___M 0x00000001 +#define DBG_PHYA_ITM_RD_STIM13__FIFOREADY___S 0 +#define DBG_PHYA_ITM_RD_STIM14 (0x00BE8038) +#define DBG_PHYA_ITM_RD_STIM14___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_RD_STIM14__FIFOREADY___M 0x00000001 +#define DBG_PHYA_ITM_RD_STIM14__FIFOREADY___S 0 +#define DBG_PHYA_ITM_RD_STIM15 (0x00BE803C) +#define DBG_PHYA_ITM_RD_STIM15___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_RD_STIM15__FIFOREADY___M 0x00000001 +#define DBG_PHYA_ITM_RD_STIM15__FIFOREADY___S 0 +#define DBG_PHYA_ITM_RD_STIM16 (0x00BE8040) +#define DBG_PHYA_ITM_RD_STIM16___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_RD_STIM16__FIFOREADY___M 0x00000001 +#define DBG_PHYA_ITM_RD_STIM16__FIFOREADY___S 0 +#define DBG_PHYA_ITM_RD_STIM17 (0x00BE8044) +#define DBG_PHYA_ITM_RD_STIM17___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_RD_STIM17__FIFOREADY___M 0x00000001 +#define DBG_PHYA_ITM_RD_STIM17__FIFOREADY___S 0 +#define DBG_PHYA_ITM_RD_STIM18 (0x00BE8048) +#define DBG_PHYA_ITM_RD_STIM18___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_RD_STIM18__FIFOREADY___M 0x00000001 +#define DBG_PHYA_ITM_RD_STIM18__FIFOREADY___S 0 +#define DBG_PHYA_ITM_RD_STIM19 (0x00BE804C) +#define DBG_PHYA_ITM_RD_STIM19___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_RD_STIM19__FIFOREADY___M 0x00000001 +#define DBG_PHYA_ITM_RD_STIM19__FIFOREADY___S 0 +#define DBG_PHYA_ITM_RD_STIM20 (0x00BE8050) +#define DBG_PHYA_ITM_RD_STIM20___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_RD_STIM20__FIFOREADY___M 0x00000001 +#define DBG_PHYA_ITM_RD_STIM20__FIFOREADY___S 0 +#define DBG_PHYA_ITM_RD_STIM21 (0x00BE8054) +#define DBG_PHYA_ITM_RD_STIM21___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_RD_STIM21__FIFOREADY___M 0x00000001 +#define DBG_PHYA_ITM_RD_STIM21__FIFOREADY___S 0 +#define DBG_PHYA_ITM_RD_STIM22 (0x00BE8058) +#define DBG_PHYA_ITM_RD_STIM22___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_RD_STIM22__FIFOREADY___M 0x00000001 +#define DBG_PHYA_ITM_RD_STIM22__FIFOREADY___S 0 +#define DBG_PHYA_ITM_RD_STIM23 (0x00BE805C) +#define DBG_PHYA_ITM_RD_STIM23___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_RD_STIM23__FIFOREADY___M 0x00000001 +#define DBG_PHYA_ITM_RD_STIM23__FIFOREADY___S 0 +#define DBG_PHYA_ITM_RD_STIM24 (0x00BE8060) +#define DBG_PHYA_ITM_RD_STIM24___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_RD_STIM24__FIFOREADY___M 0x00000001 +#define DBG_PHYA_ITM_RD_STIM24__FIFOREADY___S 0 +#define DBG_PHYA_ITM_RD_STIM25 (0x00BE8064) +#define DBG_PHYA_ITM_RD_STIM25___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_RD_STIM25__FIFOREADY___M 0x00000001 +#define DBG_PHYA_ITM_RD_STIM25__FIFOREADY___S 0 +#define DBG_PHYA_ITM_RD_STIM26 (0x00BE8068) +#define DBG_PHYA_ITM_RD_STIM26___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_RD_STIM26__FIFOREADY___M 0x00000001 +#define DBG_PHYA_ITM_RD_STIM26__FIFOREADY___S 0 +#define DBG_PHYA_ITM_RD_STIM27 (0x00BE806C) +#define DBG_PHYA_ITM_RD_STIM27___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_RD_STIM27__FIFOREADY___M 0x00000001 +#define DBG_PHYA_ITM_RD_STIM27__FIFOREADY___S 0 +#define DBG_PHYA_ITM_RD_STIM28 (0x00BE8070) +#define DBG_PHYA_ITM_RD_STIM28___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_RD_STIM28__FIFOREADY___M 0x00000001 +#define DBG_PHYA_ITM_RD_STIM28__FIFOREADY___S 0 +#define DBG_PHYA_ITM_RD_STIM29 (0x00BE8074) +#define DBG_PHYA_ITM_RD_STIM29___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_RD_STIM29__FIFOREADY___M 0x00000001 +#define DBG_PHYA_ITM_RD_STIM29__FIFOREADY___S 0 +#define DBG_PHYA_ITM_RD_STIM30 (0x00BE8078) +#define DBG_PHYA_ITM_RD_STIM30___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_RD_STIM30__FIFOREADY___M 0x00000001 +#define DBG_PHYA_ITM_RD_STIM30__FIFOREADY___S 0 +#define DBG_PHYA_ITM_RD_STIM31 (0x00BE807C) +#define DBG_PHYA_ITM_RD_STIM31___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_RD_STIM31__FIFOREADY___M 0x00000001 +#define DBG_PHYA_ITM_RD_STIM31__FIFOREADY___S 0 + +#define DBG_PHYA_ITM_TER (0x00BE8E00) +#define DBG_PHYA_ITM_TER___RWC QCSR_REG_RW +#define DBG_PHYA_ITM_TER___POR 0x00000000 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN31___POR 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN30___POR 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN29___POR 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN28___POR 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN27___POR 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN26___POR 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN25___POR 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN24___POR 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN23___POR 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN22___POR 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN21___POR 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN20___POR 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN19___POR 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN18___POR 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN17___POR 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN16___POR 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN15___POR 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN14___POR 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN13___POR 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN12___POR 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN11___POR 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN10___POR 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN9___POR 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN8___POR 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN7___POR 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN6___POR 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN5___POR 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN4___POR 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN3___POR 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN2___POR 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN1___POR 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN0___POR 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN31___M 0x80000000 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN31___S 31 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN31__DISABLE 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN31__ENABLE 0x1 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN30___M 0x40000000 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN30___S 30 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN30__DISABLE 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN30__ENABLE 0x1 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN29___M 0x20000000 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN29___S 29 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN29__DISABLE 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN29__ENABLE 0x1 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN28___M 0x10000000 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN28___S 28 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN28__DISABLE 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN28__ENABLE 0x1 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN27___M 0x08000000 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN27___S 27 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN27__DISABLE 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN27__ENABLE 0x1 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN26___M 0x04000000 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN26___S 26 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN26__DISABLE 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN26__ENABLE 0x1 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN25___M 0x02000000 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN25___S 25 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN25__DISABLE 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN25__ENABLE 0x1 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN24___M 0x01000000 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN24___S 24 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN24__DISABLE 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN24__ENABLE 0x1 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN23___M 0x00800000 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN23___S 23 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN23__DISABLE 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN23__ENABLE 0x1 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN22___M 0x00400000 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN22___S 22 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN22__DISABLE 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN22__ENABLE 0x1 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN21___M 0x00200000 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN21___S 21 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN21__DISABLE 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN21__ENABLE 0x1 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN20___M 0x00100000 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN20___S 20 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN20__DISABLE 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN20__ENABLE 0x1 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN19___M 0x00080000 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN19___S 19 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN19__DISABLE 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN19__ENABLE 0x1 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN18___M 0x00040000 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN18___S 18 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN18__DISABLE 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN18__ENABLE 0x1 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN17___M 0x00020000 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN17___S 17 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN17__DISABLE 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN17__ENABLE 0x1 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN16___M 0x00010000 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN16___S 16 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN16__DISABLE 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN16__ENABLE 0x1 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN15___M 0x00008000 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN15___S 15 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN15__DISABLE 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN15__ENABLE 0x1 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN14___M 0x00004000 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN14___S 14 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN14__DISABLE 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN14__ENABLE 0x1 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN13___M 0x00002000 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN13___S 13 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN13__DISABLE 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN13__ENABLE 0x1 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN12___M 0x00001000 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN12___S 12 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN12__DISABLE 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN12__ENABLE 0x1 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN11___M 0x00000800 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN11___S 11 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN11__DISABLE 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN11__ENABLE 0x1 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN10___M 0x00000400 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN10___S 10 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN10__DISABLE 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN10__ENABLE 0x1 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN9___M 0x00000200 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN9___S 9 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN9__DISABLE 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN9__ENABLE 0x1 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN8___M 0x00000100 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN8___S 8 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN8__DISABLE 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN8__ENABLE 0x1 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN7___M 0x00000080 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN7___S 7 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN7__DISABLE 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN7__ENABLE 0x1 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN6___M 0x00000040 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN6___S 6 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN6__DISABLE 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN6__ENABLE 0x1 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN5___M 0x00000020 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN5___S 5 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN5__DISABLE 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN5__ENABLE 0x1 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN4___M 0x00000010 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN4___S 4 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN4__DISABLE 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN4__ENABLE 0x1 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN3___M 0x00000008 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN3___S 3 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN3__DISABLE 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN3__ENABLE 0x1 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN2___M 0x00000004 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN2___S 2 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN2__DISABLE 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN2__ENABLE 0x1 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN1___M 0x00000002 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN1___S 1 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN1__DISABLE 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN1__ENABLE 0x1 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN0___M 0x00000001 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN0___S 0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN0__DISABLE 0x0 +#define DBG_PHYA_ITM_TER__ITM_STIM_EN0__ENABLE 0x1 +#define DBG_PHYA_ITM_TER___M 0xFFFFFFFF +#define DBG_PHYA_ITM_TER___S 0 + +#define DBG_PHYA_ITM_TPR (0x00BE8E40) +#define DBG_PHYA_ITM_TPR___RWC QCSR_REG_RW +#define DBG_PHYA_ITM_TPR___POR 0x00000000 +#define DBG_PHYA_ITM_TPR__PRIVMASK3___POR 0x0 +#define DBG_PHYA_ITM_TPR__PRIVMASK2___POR 0x0 +#define DBG_PHYA_ITM_TPR__PRIVMASK1___POR 0x0 +#define DBG_PHYA_ITM_TPR__PRIVMASK0___POR 0x0 +#define DBG_PHYA_ITM_TPR__PRIVMASK3___M 0x00000008 +#define DBG_PHYA_ITM_TPR__PRIVMASK3___S 3 +#define DBG_PHYA_ITM_TPR__PRIVMASK3__UNPRIVOK 0x0 +#define DBG_PHYA_ITM_TPR__PRIVMASK3__PRIVONLY 0x1 +#define DBG_PHYA_ITM_TPR__PRIVMASK2___M 0x00000004 +#define DBG_PHYA_ITM_TPR__PRIVMASK2___S 2 +#define DBG_PHYA_ITM_TPR__PRIVMASK2__UNPRIVOK 0x0 +#define DBG_PHYA_ITM_TPR__PRIVMASK2__PRIVONLY 0x1 +#define DBG_PHYA_ITM_TPR__PRIVMASK1___M 0x00000002 +#define DBG_PHYA_ITM_TPR__PRIVMASK1___S 1 +#define DBG_PHYA_ITM_TPR__PRIVMASK1__UNPRIVOK 0x0 +#define DBG_PHYA_ITM_TPR__PRIVMASK1__PRIVONLY 0x1 +#define DBG_PHYA_ITM_TPR__PRIVMASK0___M 0x00000001 +#define DBG_PHYA_ITM_TPR__PRIVMASK0___S 0 +#define DBG_PHYA_ITM_TPR__PRIVMASK0__UNPRIVOK 0x0 +#define DBG_PHYA_ITM_TPR__PRIVMASK0__PRIVONLY 0x1 +#define DBG_PHYA_ITM_TPR___M 0x0000000F +#define DBG_PHYA_ITM_TPR___S 0 + +#define DBG_PHYA_ITM_TCR (0x00BE8E80) +#define DBG_PHYA_ITM_TCR___RWC QCSR_REG_RW +#define DBG_PHYA_ITM_TCR___POR 0x00000000 +#define DBG_PHYA_ITM_TCR__BUSY___POR 0x0 +#define DBG_PHYA_ITM_TCR__TRACEBUSID___POR 0x00 +#define DBG_PHYA_ITM_TCR__GTSFREQ___POR 0x0 +#define DBG_PHYA_ITM_TCR__LTSPRESCALE___POR 0x0 +#define DBG_PHYA_ITM_TCR__SWOENA___POR 0x0 +#define DBG_PHYA_ITM_TCR__DWTTXEN___POR 0x0 +#define DBG_PHYA_ITM_TCR__SYNCENA___POR 0x0 +#define DBG_PHYA_ITM_TCR__LTSENA___POR 0x0 +#define DBG_PHYA_ITM_TCR__ITMENA___POR 0x0 +#define DBG_PHYA_ITM_TCR__BUSY___M 0x00800000 +#define DBG_PHYA_ITM_TCR__BUSY___S 23 +#define DBG_PHYA_ITM_TCR__BUSY__IDLE 0x0 +#define DBG_PHYA_ITM_TCR__BUSY__BUSY 0x1 +#define DBG_PHYA_ITM_TCR__TRACEBUSID___M 0x007F0000 +#define DBG_PHYA_ITM_TCR__TRACEBUSID___S 16 +#define DBG_PHYA_ITM_TCR__GTSFREQ___M 0x00000C00 +#define DBG_PHYA_ITM_TCR__GTSFREQ___S 10 +#define DBG_PHYA_ITM_TCR__GTSFREQ__TSDISABLED 0x0 +#define DBG_PHYA_ITM_TCR__GTSFREQ__TSEVERY128CYC 0x1 +#define DBG_PHYA_ITM_TCR__GTSFREQ__TSEVERY8KCYC 0x2 +#define DBG_PHYA_ITM_TCR__GTSFREQ__TSEVERYPKT 0x3 +#define DBG_PHYA_ITM_TCR__LTSPRESCALE___M 0x00000300 +#define DBG_PHYA_ITM_TCR__LTSPRESCALE___S 8 +#define DBG_PHYA_ITM_TCR__LTSPRESCALE__NOPRESCALE 0x0 +#define DBG_PHYA_ITM_TCR__LTSPRESCALE__DIVBY4 0x1 +#define DBG_PHYA_ITM_TCR__LTSPRESCALE__DIVBY16 0x2 +#define DBG_PHYA_ITM_TCR__LTSPRESCALE__DIVBY64 0x3 +#define DBG_PHYA_ITM_TCR__SWOENA___M 0x00000010 +#define DBG_PHYA_ITM_TCR__SWOENA___S 4 +#define DBG_PHYA_ITM_TCR__DWTTXEN___M 0x00000008 +#define DBG_PHYA_ITM_TCR__DWTTXEN___S 3 +#define DBG_PHYA_ITM_TCR__DWTTXEN__DWTDISABLED 0x0 +#define DBG_PHYA_ITM_TCR__DWTTXEN__DWTENABLED 0x1 +#define DBG_PHYA_ITM_TCR__SYNCENA___M 0x00000004 +#define DBG_PHYA_ITM_TCR__SYNCENA___S 2 +#define DBG_PHYA_ITM_TCR__SYNCENA__SYNCPKTDISABLED 0x0 +#define DBG_PHYA_ITM_TCR__SYNCENA__SYNCPKTENABLED 0x1 +#define DBG_PHYA_ITM_TCR__LTSENA___M 0x00000002 +#define DBG_PHYA_ITM_TCR__LTSENA___S 1 +#define DBG_PHYA_ITM_TCR__LTSENA__LOCTSGENDISABLED 0x0 +#define DBG_PHYA_ITM_TCR__LTSENA__LOCTSGENENABLED 0x1 +#define DBG_PHYA_ITM_TCR__ITMENA___M 0x00000001 +#define DBG_PHYA_ITM_TCR__ITMENA___S 0 +#define DBG_PHYA_ITM_TCR__ITMENA__ITMDISABLED 0x0 +#define DBG_PHYA_ITM_TCR__ITMENA__ITMENABLED 0x1 +#define DBG_PHYA_ITM_TCR___M 0x00FF0F1F +#define DBG_PHYA_ITM_TCR___S 0 + +#define DBG_PHYA_ITM_ITATBSTAT (0x00BE8EF0) +#define DBG_PHYA_ITM_ITATBSTAT___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_ITATBSTAT___POR 0x00000001 +#define DBG_PHYA_ITM_ITATBSTAT__ATREADY___POR 0x1 +#define DBG_PHYA_ITM_ITATBSTAT__ATREADY___M 0x00000001 +#define DBG_PHYA_ITM_ITATBSTAT__ATREADY___S 0 +#define DBG_PHYA_ITM_ITATBSTAT___M 0x00000001 +#define DBG_PHYA_ITM_ITATBSTAT___S 0 + +#define DBG_PHYA_ITM_ITATBDRV (0x00BE8EF8) +#define DBG_PHYA_ITM_ITATBDRV___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_ITATBDRV___POR 0x00000000 +#define DBG_PHYA_ITM_ITATBDRV__ATVALID___POR 0x0 +#define DBG_PHYA_ITM_ITATBDRV__ATVALID___M 0x00000001 +#define DBG_PHYA_ITM_ITATBDRV__ATVALID___S 0 +#define DBG_PHYA_ITM_ITATBDRV___M 0x00000001 +#define DBG_PHYA_ITM_ITATBDRV___S 0 + +#define DBG_PHYA_ITM_ITCTRL (0x00BE8F00) +#define DBG_PHYA_ITM_ITCTRL___RWC QCSR_REG_RW +#define DBG_PHYA_ITM_ITCTRL___POR 0x00000000 +#define DBG_PHYA_ITM_ITCTRL__ENABLE___POR 0x0 +#define DBG_PHYA_ITM_ITCTRL__ENABLE___M 0x00000001 +#define DBG_PHYA_ITM_ITCTRL__ENABLE___S 0 +#define DBG_PHYA_ITM_ITCTRL___M 0x00000001 +#define DBG_PHYA_ITM_ITCTRL___S 0 + +#define DBG_PHYA_ITM_LAR (0x00BE8FB0) +#define DBG_PHYA_ITM_LAR___RWC QCSR_REG_WO +#define DBG_PHYA_ITM_LAR___POR 0x00000000 +#define DBG_PHYA_ITM_LAR__KEY___POR 0x00000000 +#define DBG_PHYA_ITM_LAR__KEY___M 0xFFFFFFFF +#define DBG_PHYA_ITM_LAR__KEY___S 0 +#define DBG_PHYA_ITM_LAR__KEY__UNLOCKKEY 0xC5ACCE55 +#define DBG_PHYA_ITM_LAR___M 0xFFFFFFFF +#define DBG_PHYA_ITM_LAR___S 0 + +#define DBG_PHYA_ITM_LSR (0x00BE8FB4) +#define DBG_PHYA_ITM_LSR___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_LSR___POR 0x00000003 +#define DBG_PHYA_ITM_LSR__LOCKED___POR 0x1 +#define DBG_PHYA_ITM_LSR__LOCKINGIMPL___POR 0x1 +#define DBG_PHYA_ITM_LSR__LOCKED___M 0x00000002 +#define DBG_PHYA_ITM_LSR__LOCKED___S 1 +#define DBG_PHYA_ITM_LSR__LOCKED__ITM_UNLOCKED 0x0 +#define DBG_PHYA_ITM_LSR__LOCKED__ITM_LOCKED 0x1 +#define DBG_PHYA_ITM_LSR__LOCKINGIMPL___M 0x00000001 +#define DBG_PHYA_ITM_LSR__LOCKINGIMPL___S 0 +#define DBG_PHYA_ITM_LSR___M 0x00000003 +#define DBG_PHYA_ITM_LSR___S 0 + +#define DBG_PHYA_ITM_PIDR4 (0x00BE8FD0) +#define DBG_PHYA_ITM_PIDR4___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_PIDR4___POR 0x00000004 +#define DBG_PHYA_ITM_PIDR4__FIELD_4KB_COUNT___POR 0x0 +#define DBG_PHYA_ITM_PIDR4__JEP106_CONTINUATION___POR 0x4 +#define DBG_PHYA_ITM_PIDR4__FIELD_4KB_COUNT___M 0x000000F0 +#define DBG_PHYA_ITM_PIDR4__FIELD_4KB_COUNT___S 4 +#define DBG_PHYA_ITM_PIDR4__JEP106_CONTINUATION___M 0x0000000F +#define DBG_PHYA_ITM_PIDR4__JEP106_CONTINUATION___S 0 +#define DBG_PHYA_ITM_PIDR4___M 0x000000FF +#define DBG_PHYA_ITM_PIDR4___S 0 + +#define DBG_PHYA_ITM_PIDR5 (0x00BE8FD4) +#define DBG_PHYA_ITM_PIDR5___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_PIDR5___POR 0x00000000 +#define DBG_PHYA_ITM_PIDR5__PERIPHID5___POR 0x00000000 +#define DBG_PHYA_ITM_PIDR5__PERIPHID5___M 0xFFFFFFFF +#define DBG_PHYA_ITM_PIDR5__PERIPHID5___S 0 +#define DBG_PHYA_ITM_PIDR5___M 0xFFFFFFFF +#define DBG_PHYA_ITM_PIDR5___S 0 + +#define DBG_PHYA_ITM_PIDR6 (0x00BE8FD8) +#define DBG_PHYA_ITM_PIDR6___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_PIDR6___POR 0x00000000 +#define DBG_PHYA_ITM_PIDR6__PERIPHID6___POR 0x00000000 +#define DBG_PHYA_ITM_PIDR6__PERIPHID6___M 0xFFFFFFFF +#define DBG_PHYA_ITM_PIDR6__PERIPHID6___S 0 +#define DBG_PHYA_ITM_PIDR6___M 0xFFFFFFFF +#define DBG_PHYA_ITM_PIDR6___S 0 + +#define DBG_PHYA_ITM_PIDR7 (0x00BE8FDC) +#define DBG_PHYA_ITM_PIDR7___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_PIDR7___POR 0x00000000 +#define DBG_PHYA_ITM_PIDR7__PERIPHID7___POR 0x00000000 +#define DBG_PHYA_ITM_PIDR7__PERIPHID7___M 0xFFFFFFFF +#define DBG_PHYA_ITM_PIDR7__PERIPHID7___S 0 +#define DBG_PHYA_ITM_PIDR7___M 0xFFFFFFFF +#define DBG_PHYA_ITM_PIDR7___S 0 + +#define DBG_PHYA_ITM_PIDR0 (0x00BE8FE0) +#define DBG_PHYA_ITM_PIDR0___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_PIDR0___POR 0x00000001 +#define DBG_PHYA_ITM_PIDR0__PARTNUM_7_0___POR 0x01 +#define DBG_PHYA_ITM_PIDR0__PARTNUM_7_0___M 0x000000FF +#define DBG_PHYA_ITM_PIDR0__PARTNUM_7_0___S 0 +#define DBG_PHYA_ITM_PIDR0___M 0x000000FF +#define DBG_PHYA_ITM_PIDR0___S 0 + +#define DBG_PHYA_ITM_PIDR1 (0x00BE8FE4) +#define DBG_PHYA_ITM_PIDR1___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_PIDR1___POR 0x000000B0 +#define DBG_PHYA_ITM_PIDR1__JEP106_IDENTITY_3_0___POR 0xB +#define DBG_PHYA_ITM_PIDR1__PARTNUM_11_8___POR 0x0 +#define DBG_PHYA_ITM_PIDR1__JEP106_IDENTITY_3_0___M 0x000000F0 +#define DBG_PHYA_ITM_PIDR1__JEP106_IDENTITY_3_0___S 4 +#define DBG_PHYA_ITM_PIDR1__PARTNUM_11_8___M 0x0000000F +#define DBG_PHYA_ITM_PIDR1__PARTNUM_11_8___S 0 +#define DBG_PHYA_ITM_PIDR1___M 0x000000FF +#define DBG_PHYA_ITM_PIDR1___S 0 + +#define DBG_PHYA_ITM_PIDR2 (0x00BE8FE8) +#define DBG_PHYA_ITM_PIDR2___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_PIDR2___POR 0x0000003B +#define DBG_PHYA_ITM_PIDR2__MAJREV___POR 0x3 +#define DBG_PHYA_ITM_PIDR2__JEDEC___POR 0x1 +#define DBG_PHYA_ITM_PIDR2__JEP106_IDENTITY_6_4___POR 0x3 +#define DBG_PHYA_ITM_PIDR2__MAJREV___M 0x000000F0 +#define DBG_PHYA_ITM_PIDR2__MAJREV___S 4 +#define DBG_PHYA_ITM_PIDR2__JEDEC___M 0x00000008 +#define DBG_PHYA_ITM_PIDR2__JEDEC___S 3 +#define DBG_PHYA_ITM_PIDR2__JEP106_IDENTITY_6_4___M 0x00000007 +#define DBG_PHYA_ITM_PIDR2__JEP106_IDENTITY_6_4___S 0 +#define DBG_PHYA_ITM_PIDR2___M 0x000000FF +#define DBG_PHYA_ITM_PIDR2___S 0 + +#define DBG_PHYA_ITM_PIDR3 (0x00BE8FEC) +#define DBG_PHYA_ITM_PIDR3___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_PIDR3___POR 0x00000000 +#define DBG_PHYA_ITM_PIDR3__REV_AND___POR 0x0 +#define DBG_PHYA_ITM_PIDR3__CUSTOMER_MODIFIED___POR 0x0 +#define DBG_PHYA_ITM_PIDR3__REV_AND___M 0x000000F0 +#define DBG_PHYA_ITM_PIDR3__REV_AND___S 4 +#define DBG_PHYA_ITM_PIDR3__CUSTOMER_MODIFIED___M 0x0000000F +#define DBG_PHYA_ITM_PIDR3__CUSTOMER_MODIFIED___S 0 +#define DBG_PHYA_ITM_PIDR3___M 0x000000FF +#define DBG_PHYA_ITM_PIDR3___S 0 + +#define DBG_PHYA_ITM_CIDR0 (0x00BE8FF0) +#define DBG_PHYA_ITM_CIDR0___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_CIDR0___POR 0x0000000D +#define DBG_PHYA_ITM_CIDR0__PREAMBLE_7_0___POR 0x0D +#define DBG_PHYA_ITM_CIDR0__PREAMBLE_7_0___M 0x000000FF +#define DBG_PHYA_ITM_CIDR0__PREAMBLE_7_0___S 0 +#define DBG_PHYA_ITM_CIDR0___M 0x000000FF +#define DBG_PHYA_ITM_CIDR0___S 0 + +#define DBG_PHYA_ITM_CIDR1 (0x00BE8FF4) +#define DBG_PHYA_ITM_CIDR1___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_CIDR1___POR 0x000000E0 +#define DBG_PHYA_ITM_CIDR1__PREAMBLE_15_12___POR 0xE +#define DBG_PHYA_ITM_CIDR1__PREAMBLE_11_8___POR 0x0 +#define DBG_PHYA_ITM_CIDR1__PREAMBLE_15_12___M 0x000000F0 +#define DBG_PHYA_ITM_CIDR1__PREAMBLE_15_12___S 4 +#define DBG_PHYA_ITM_CIDR1__PREAMBLE_11_8___M 0x0000000F +#define DBG_PHYA_ITM_CIDR1__PREAMBLE_11_8___S 0 +#define DBG_PHYA_ITM_CIDR1___M 0x000000FF +#define DBG_PHYA_ITM_CIDR1___S 0 + +#define DBG_PHYA_ITM_CIDR2 (0x00BE8FF8) +#define DBG_PHYA_ITM_CIDR2___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_CIDR2___POR 0x00000005 +#define DBG_PHYA_ITM_CIDR2__PREAMBLE_23_16___POR 0x05 +#define DBG_PHYA_ITM_CIDR2__PREAMBLE_23_16___M 0x000000FF +#define DBG_PHYA_ITM_CIDR2__PREAMBLE_23_16___S 0 +#define DBG_PHYA_ITM_CIDR2___M 0x000000FF +#define DBG_PHYA_ITM_CIDR2___S 0 + +#define DBG_PHYA_ITM_CIDR3 (0x00BE8FFC) +#define DBG_PHYA_ITM_CIDR3___RWC QCSR_REG_RO +#define DBG_PHYA_ITM_CIDR3___POR 0x000000B1 +#define DBG_PHYA_ITM_CIDR3__PREAMBLE_31_24___POR 0xB1 +#define DBG_PHYA_ITM_CIDR3__PREAMBLE_31_24___M 0x000000FF +#define DBG_PHYA_ITM_CIDR3__PREAMBLE_31_24___S 0 +#define DBG_PHYA_ITM_CIDR3___M 0x000000FF +#define DBG_PHYA_ITM_CIDR3___S 0 + +#define DBG_PHYA_DWT_CTRL (0x00BE9000) +#define DBG_PHYA_DWT_CTRL___RWC QCSR_REG_RO +#define DBG_PHYA_DWT_CTRL___POR 0x40000000 +#define DBG_PHYA_DWT_CTRL__NUMCOMP___POR 0x4 +#define DBG_PHYA_DWT_CTRL__NOTRCPKT___POR 0x0 +#define DBG_PHYA_DWT_CTRL__NOEXTTRIG___POR 0x0 +#define DBG_PHYA_DWT_CTRL__NOCYCCNT___POR 0x0 +#define DBG_PHYA_DWT_CTRL__NOPRFCNT___POR 0x0 +#define DBG_PHYA_DWT_CTRL__CYCEVTENA___POR 0x0 +#define DBG_PHYA_DWT_CTRL__FOLDEVTENA___POR 0x0 +#define DBG_PHYA_DWT_CTRL__LSUEVTENA___POR 0x0 +#define DBG_PHYA_DWT_CTRL__SLEEPEVTENA___POR 0x0 +#define DBG_PHYA_DWT_CTRL__EXCEVTENA___POR 0x0 +#define DBG_PHYA_DWT_CTRL__CPIEVTENA___POR 0x0 +#define DBG_PHYA_DWT_CTRL__EXCTRCENA___POR 0x0 +#define DBG_PHYA_DWT_CTRL__PCSAMPLENA___POR 0x0 +#define DBG_PHYA_DWT_CTRL__SYNCTAP___POR 0x0 +#define DBG_PHYA_DWT_CTRL__CYCTAP___POR 0x0 +#define DBG_PHYA_DWT_CTRL__POSTINIT___POR 0x0 +#define DBG_PHYA_DWT_CTRL__POSTPRESET___POR 0x0 +#define DBG_PHYA_DWT_CTRL__CYCCNTENA___POR 0x0 +#define DBG_PHYA_DWT_CTRL__NUMCOMP___M 0xF0000000 +#define DBG_PHYA_DWT_CTRL__NUMCOMP___S 28 +#define DBG_PHYA_DWT_CTRL__NOTRCPKT___M 0x08000000 +#define DBG_PHYA_DWT_CTRL__NOTRCPKT___S 27 +#define DBG_PHYA_DWT_CTRL__NOEXTTRIG___M 0x04000000 +#define DBG_PHYA_DWT_CTRL__NOEXTTRIG___S 26 +#define DBG_PHYA_DWT_CTRL__NOCYCCNT___M 0x02000000 +#define DBG_PHYA_DWT_CTRL__NOCYCCNT___S 25 +#define DBG_PHYA_DWT_CTRL__NOPRFCNT___M 0x01000000 +#define DBG_PHYA_DWT_CTRL__NOPRFCNT___S 24 +#define DBG_PHYA_DWT_CTRL__CYCEVTENA___M 0x00400000 +#define DBG_PHYA_DWT_CTRL__CYCEVTENA___S 22 +#define DBG_PHYA_DWT_CTRL__FOLDEVTENA___M 0x00200000 +#define DBG_PHYA_DWT_CTRL__FOLDEVTENA___S 21 +#define DBG_PHYA_DWT_CTRL__LSUEVTENA___M 0x00100000 +#define DBG_PHYA_DWT_CTRL__LSUEVTENA___S 20 +#define DBG_PHYA_DWT_CTRL__SLEEPEVTENA___M 0x00080000 +#define DBG_PHYA_DWT_CTRL__SLEEPEVTENA___S 19 +#define DBG_PHYA_DWT_CTRL__EXCEVTENA___M 0x00040000 +#define DBG_PHYA_DWT_CTRL__EXCEVTENA___S 18 +#define DBG_PHYA_DWT_CTRL__CPIEVTENA___M 0x00020000 +#define DBG_PHYA_DWT_CTRL__CPIEVTENA___S 17 +#define DBG_PHYA_DWT_CTRL__EXCTRCENA___M 0x00010000 +#define DBG_PHYA_DWT_CTRL__EXCTRCENA___S 16 +#define DBG_PHYA_DWT_CTRL__PCSAMPLENA___M 0x00001000 +#define DBG_PHYA_DWT_CTRL__PCSAMPLENA___S 12 +#define DBG_PHYA_DWT_CTRL__SYNCTAP___M 0x00000C00 +#define DBG_PHYA_DWT_CTRL__SYNCTAP___S 10 +#define DBG_PHYA_DWT_CTRL__CYCTAP___M 0x00000200 +#define DBG_PHYA_DWT_CTRL__CYCTAP___S 9 +#define DBG_PHYA_DWT_CTRL__POSTINIT___M 0x000001E0 +#define DBG_PHYA_DWT_CTRL__POSTINIT___S 5 +#define DBG_PHYA_DWT_CTRL__POSTPRESET___M 0x0000001E +#define DBG_PHYA_DWT_CTRL__POSTPRESET___S 1 +#define DBG_PHYA_DWT_CTRL__CYCCNTENA___M 0x00000001 +#define DBG_PHYA_DWT_CTRL__CYCCNTENA___S 0 +#define DBG_PHYA_DWT_CTRL___M 0xFF7F1FFF +#define DBG_PHYA_DWT_CTRL___S 0 + +#define DBG_PHYA_DWT_CYCCNT (0x00BE9004) +#define DBG_PHYA_DWT_CYCCNT___RWC QCSR_REG_RW +#define DBG_PHYA_DWT_CYCCNT___POR 0x00000000 +#define DBG_PHYA_DWT_CYCCNT__CYCCNT___POR 0x00000000 +#define DBG_PHYA_DWT_CYCCNT__CYCCNT___M 0xFFFFFFFF +#define DBG_PHYA_DWT_CYCCNT__CYCCNT___S 0 +#define DBG_PHYA_DWT_CYCCNT___M 0xFFFFFFFF +#define DBG_PHYA_DWT_CYCCNT___S 0 + +#define DBG_PHYA_DWT_CPICNT (0x00BE9008) +#define DBG_PHYA_DWT_CPICNT___RWC QCSR_REG_RW +#define DBG_PHYA_DWT_CPICNT___POR 0x00000000 +#define DBG_PHYA_DWT_CPICNT__CPICNT___POR 0x00 +#define DBG_PHYA_DWT_CPICNT__CPICNT___M 0x000000FF +#define DBG_PHYA_DWT_CPICNT__CPICNT___S 0 +#define DBG_PHYA_DWT_CPICNT___M 0x000000FF +#define DBG_PHYA_DWT_CPICNT___S 0 + +#define DBG_PHYA_DWT_EXCCNT (0x00BE900C) +#define DBG_PHYA_DWT_EXCCNT___RWC QCSR_REG_RW +#define DBG_PHYA_DWT_EXCCNT___POR 0x00000000 +#define DBG_PHYA_DWT_EXCCNT__EXCCNT___POR 0x00 +#define DBG_PHYA_DWT_EXCCNT__EXCCNT___M 0x000000FF +#define DBG_PHYA_DWT_EXCCNT__EXCCNT___S 0 +#define DBG_PHYA_DWT_EXCCNT___M 0x000000FF +#define DBG_PHYA_DWT_EXCCNT___S 0 + +#define DBG_PHYA_DWT_SLEEPCNT (0x00BE9010) +#define DBG_PHYA_DWT_SLEEPCNT___RWC QCSR_REG_RW +#define DBG_PHYA_DWT_SLEEPCNT___POR 0x00000000 +#define DBG_PHYA_DWT_SLEEPCNT__SLEEPCNT___POR 0x00 +#define DBG_PHYA_DWT_SLEEPCNT__SLEEPCNT___M 0x000000FF +#define DBG_PHYA_DWT_SLEEPCNT__SLEEPCNT___S 0 +#define DBG_PHYA_DWT_SLEEPCNT___M 0x000000FF +#define DBG_PHYA_DWT_SLEEPCNT___S 0 + +#define DBG_PHYA_DWT_LSUCNT (0x00BE9014) +#define DBG_PHYA_DWT_LSUCNT___RWC QCSR_REG_RW +#define DBG_PHYA_DWT_LSUCNT___POR 0x00000000 +#define DBG_PHYA_DWT_LSUCNT__LSUCNT___POR 0x00 +#define DBG_PHYA_DWT_LSUCNT__LSUCNT___M 0x000000FF +#define DBG_PHYA_DWT_LSUCNT__LSUCNT___S 0 +#define DBG_PHYA_DWT_LSUCNT___M 0x000000FF +#define DBG_PHYA_DWT_LSUCNT___S 0 + +#define DBG_PHYA_DWT_FOLDCNT (0x00BE9018) +#define DBG_PHYA_DWT_FOLDCNT___RWC QCSR_REG_RW +#define DBG_PHYA_DWT_FOLDCNT___POR 0x00000000 +#define DBG_PHYA_DWT_FOLDCNT__FOLDCNT___POR 0x00 +#define DBG_PHYA_DWT_FOLDCNT__FOLDCNT___M 0x000000FF +#define DBG_PHYA_DWT_FOLDCNT__FOLDCNT___S 0 +#define DBG_PHYA_DWT_FOLDCNT___M 0x000000FF +#define DBG_PHYA_DWT_FOLDCNT___S 0 + +#define DBG_PHYA_DWT_PCSR (0x00BE901C) +#define DBG_PHYA_DWT_PCSR___RWC QCSR_REG_RO +#define DBG_PHYA_DWT_PCSR___POR 0x00000000 +#define DBG_PHYA_DWT_PCSR__EIASAMPLE___POR 0x00000000 +#define DBG_PHYA_DWT_PCSR__EIASAMPLE___M 0xFFFFFFFF +#define DBG_PHYA_DWT_PCSR__EIASAMPLE___S 0 +#define DBG_PHYA_DWT_PCSR___M 0xFFFFFFFF +#define DBG_PHYA_DWT_PCSR___S 0 + +#define DBG_PHYA_DWT_COMPn(n) (0x00BE9020+0x10*(n)) +#define DBG_PHYA_DWT_COMPn_nMIN 0 +#define DBG_PHYA_DWT_COMPn_nMAX 3 +#define DBG_PHYA_DWT_COMPn_ELEM 4 +#define DBG_PHYA_DWT_COMPn___RWC QCSR_REG_RW +#define DBG_PHYA_DWT_COMPn___POR 0x00000000 +#define DBG_PHYA_DWT_COMPn__COMP___POR 0x00000000 +#define DBG_PHYA_DWT_COMPn__COMP___M 0xFFFFFFFF +#define DBG_PHYA_DWT_COMPn__COMP___S 0 +#define DBG_PHYA_DWT_COMPn___M 0xFFFFFFFF +#define DBG_PHYA_DWT_COMPn___S 0 +#define DBG_PHYA_DWT_COMP0 (0x00BE9020) +#define DBG_PHYA_DWT_COMP0___RWC QCSR_REG_RW +#define DBG_PHYA_DWT_COMP0__COMP___M 0xFFFFFFFF +#define DBG_PHYA_DWT_COMP0__COMP___S 0 +#define DBG_PHYA_DWT_COMP1 (0x00BE9030) +#define DBG_PHYA_DWT_COMP1___RWC QCSR_REG_RW +#define DBG_PHYA_DWT_COMP1__COMP___M 0xFFFFFFFF +#define DBG_PHYA_DWT_COMP1__COMP___S 0 +#define DBG_PHYA_DWT_COMP2 (0x00BE9040) +#define DBG_PHYA_DWT_COMP2___RWC QCSR_REG_RW +#define DBG_PHYA_DWT_COMP2__COMP___M 0xFFFFFFFF +#define DBG_PHYA_DWT_COMP2__COMP___S 0 +#define DBG_PHYA_DWT_COMP3 (0x00BE9050) +#define DBG_PHYA_DWT_COMP3___RWC QCSR_REG_RW +#define DBG_PHYA_DWT_COMP3__COMP___M 0xFFFFFFFF +#define DBG_PHYA_DWT_COMP3__COMP___S 0 + +#define DBG_PHYA_DWT_MASKn(n) (0x00BE9024+0x10*(n)) +#define DBG_PHYA_DWT_MASKn_nMIN 0 +#define DBG_PHYA_DWT_MASKn_nMAX 3 +#define DBG_PHYA_DWT_MASKn_ELEM 4 +#define DBG_PHYA_DWT_MASKn___RWC QCSR_REG_RW +#define DBG_PHYA_DWT_MASKn___POR 0x00000000 +#define DBG_PHYA_DWT_MASKn__MASK___POR 0x00 +#define DBG_PHYA_DWT_MASKn__MASK___M 0x0000001F +#define DBG_PHYA_DWT_MASKn__MASK___S 0 +#define DBG_PHYA_DWT_MASKn___M 0x0000001F +#define DBG_PHYA_DWT_MASKn___S 0 +#define DBG_PHYA_DWT_MASK0 (0x00BE9024) +#define DBG_PHYA_DWT_MASK0___RWC QCSR_REG_RW +#define DBG_PHYA_DWT_MASK0__MASK___M 0x0000001F +#define DBG_PHYA_DWT_MASK0__MASK___S 0 +#define DBG_PHYA_DWT_MASK1 (0x00BE9034) +#define DBG_PHYA_DWT_MASK1___RWC QCSR_REG_RW +#define DBG_PHYA_DWT_MASK1__MASK___M 0x0000001F +#define DBG_PHYA_DWT_MASK1__MASK___S 0 +#define DBG_PHYA_DWT_MASK2 (0x00BE9044) +#define DBG_PHYA_DWT_MASK2___RWC QCSR_REG_RW +#define DBG_PHYA_DWT_MASK2__MASK___M 0x0000001F +#define DBG_PHYA_DWT_MASK2__MASK___S 0 +#define DBG_PHYA_DWT_MASK3 (0x00BE9054) +#define DBG_PHYA_DWT_MASK3___RWC QCSR_REG_RW +#define DBG_PHYA_DWT_MASK3__MASK___M 0x0000001F +#define DBG_PHYA_DWT_MASK3__MASK___S 0 + +#define DBG_PHYA_DWT_FUNCTIONn(n) (0x00BE9028+0x10*(n)) +#define DBG_PHYA_DWT_FUNCTIONn_nMIN 0 +#define DBG_PHYA_DWT_FUNCTIONn_nMAX 3 +#define DBG_PHYA_DWT_FUNCTIONn_ELEM 4 +#define DBG_PHYA_DWT_FUNCTIONn___RWC QCSR_REG_RW +#define DBG_PHYA_DWT_FUNCTIONn___POR 0x00000000 +#define DBG_PHYA_DWT_FUNCTIONn__MATCHED___POR 0x0 +#define DBG_PHYA_DWT_FUNCTIONn__DATAVADDR1___POR 0x0 +#define DBG_PHYA_DWT_FUNCTIONn__DATAVADDR0___POR 0x0 +#define DBG_PHYA_DWT_FUNCTIONn__DATAVSIZE___POR 0x0 +#define DBG_PHYA_DWT_FUNCTIONn__LNK1ENA___POR 0x0 +#define DBG_PHYA_DWT_FUNCTIONn__DATAVMATCH___POR 0x0 +#define DBG_PHYA_DWT_FUNCTIONn__CYCMATCH___POR 0x0 +#define DBG_PHYA_DWT_FUNCTIONn__EMITRANGE___POR 0x0 +#define DBG_PHYA_DWT_FUNCTIONn__FUNCTION___POR 0x0 +#define DBG_PHYA_DWT_FUNCTIONn__MATCHED___M 0x01000000 +#define DBG_PHYA_DWT_FUNCTIONn__MATCHED___S 24 +#define DBG_PHYA_DWT_FUNCTIONn__DATAVADDR1___M 0x000F0000 +#define DBG_PHYA_DWT_FUNCTIONn__DATAVADDR1___S 16 +#define DBG_PHYA_DWT_FUNCTIONn__DATAVADDR0___M 0x0000F000 +#define DBG_PHYA_DWT_FUNCTIONn__DATAVADDR0___S 12 +#define DBG_PHYA_DWT_FUNCTIONn__DATAVSIZE___M 0x00000C00 +#define DBG_PHYA_DWT_FUNCTIONn__DATAVSIZE___S 10 +#define DBG_PHYA_DWT_FUNCTIONn__LNK1ENA___M 0x00000200 +#define DBG_PHYA_DWT_FUNCTIONn__LNK1ENA___S 9 +#define DBG_PHYA_DWT_FUNCTIONn__DATAVMATCH___M 0x00000100 +#define DBG_PHYA_DWT_FUNCTIONn__DATAVMATCH___S 8 +#define DBG_PHYA_DWT_FUNCTIONn__CYCMATCH___M 0x00000080 +#define DBG_PHYA_DWT_FUNCTIONn__CYCMATCH___S 7 +#define DBG_PHYA_DWT_FUNCTIONn__EMITRANGE___M 0x00000020 +#define DBG_PHYA_DWT_FUNCTIONn__EMITRANGE___S 5 +#define DBG_PHYA_DWT_FUNCTIONn__FUNCTION___M 0x0000000F +#define DBG_PHYA_DWT_FUNCTIONn__FUNCTION___S 0 +#define DBG_PHYA_DWT_FUNCTIONn___M 0x010FFFAF +#define DBG_PHYA_DWT_FUNCTIONn___S 0 +#define DBG_PHYA_DWT_FUNCTION0 (0x00BE9028) +#define DBG_PHYA_DWT_FUNCTION0___RWC QCSR_REG_RW +#define DBG_PHYA_DWT_FUNCTION0__MATCHED___M 0x01000000 +#define DBG_PHYA_DWT_FUNCTION0__MATCHED___S 24 +#define DBG_PHYA_DWT_FUNCTION0__DATAVADDR1___M 0x000F0000 +#define DBG_PHYA_DWT_FUNCTION0__DATAVADDR1___S 16 +#define DBG_PHYA_DWT_FUNCTION0__DATAVADDR0___M 0x0000F000 +#define DBG_PHYA_DWT_FUNCTION0__DATAVADDR0___S 12 +#define DBG_PHYA_DWT_FUNCTION0__DATAVSIZE___M 0x00000C00 +#define DBG_PHYA_DWT_FUNCTION0__DATAVSIZE___S 10 +#define DBG_PHYA_DWT_FUNCTION0__LNK1ENA___M 0x00000200 +#define DBG_PHYA_DWT_FUNCTION0__LNK1ENA___S 9 +#define DBG_PHYA_DWT_FUNCTION0__DATAVMATCH___M 0x00000100 +#define DBG_PHYA_DWT_FUNCTION0__DATAVMATCH___S 8 +#define DBG_PHYA_DWT_FUNCTION0__CYCMATCH___M 0x00000080 +#define DBG_PHYA_DWT_FUNCTION0__CYCMATCH___S 7 +#define DBG_PHYA_DWT_FUNCTION0__EMITRANGE___M 0x00000020 +#define DBG_PHYA_DWT_FUNCTION0__EMITRANGE___S 5 +#define DBG_PHYA_DWT_FUNCTION0__FUNCTION___M 0x0000000F +#define DBG_PHYA_DWT_FUNCTION0__FUNCTION___S 0 +#define DBG_PHYA_DWT_FUNCTION1 (0x00BE9038) +#define DBG_PHYA_DWT_FUNCTION1___RWC QCSR_REG_RW +#define DBG_PHYA_DWT_FUNCTION1__MATCHED___M 0x01000000 +#define DBG_PHYA_DWT_FUNCTION1__MATCHED___S 24 +#define DBG_PHYA_DWT_FUNCTION1__DATAVADDR1___M 0x000F0000 +#define DBG_PHYA_DWT_FUNCTION1__DATAVADDR1___S 16 +#define DBG_PHYA_DWT_FUNCTION1__DATAVADDR0___M 0x0000F000 +#define DBG_PHYA_DWT_FUNCTION1__DATAVADDR0___S 12 +#define DBG_PHYA_DWT_FUNCTION1__DATAVSIZE___M 0x00000C00 +#define DBG_PHYA_DWT_FUNCTION1__DATAVSIZE___S 10 +#define DBG_PHYA_DWT_FUNCTION1__LNK1ENA___M 0x00000200 +#define DBG_PHYA_DWT_FUNCTION1__LNK1ENA___S 9 +#define DBG_PHYA_DWT_FUNCTION1__DATAVMATCH___M 0x00000100 +#define DBG_PHYA_DWT_FUNCTION1__DATAVMATCH___S 8 +#define DBG_PHYA_DWT_FUNCTION1__CYCMATCH___M 0x00000080 +#define DBG_PHYA_DWT_FUNCTION1__CYCMATCH___S 7 +#define DBG_PHYA_DWT_FUNCTION1__EMITRANGE___M 0x00000020 +#define DBG_PHYA_DWT_FUNCTION1__EMITRANGE___S 5 +#define DBG_PHYA_DWT_FUNCTION1__FUNCTION___M 0x0000000F +#define DBG_PHYA_DWT_FUNCTION1__FUNCTION___S 0 +#define DBG_PHYA_DWT_FUNCTION2 (0x00BE9048) +#define DBG_PHYA_DWT_FUNCTION2___RWC QCSR_REG_RW +#define DBG_PHYA_DWT_FUNCTION2__MATCHED___M 0x01000000 +#define DBG_PHYA_DWT_FUNCTION2__MATCHED___S 24 +#define DBG_PHYA_DWT_FUNCTION2__DATAVADDR1___M 0x000F0000 +#define DBG_PHYA_DWT_FUNCTION2__DATAVADDR1___S 16 +#define DBG_PHYA_DWT_FUNCTION2__DATAVADDR0___M 0x0000F000 +#define DBG_PHYA_DWT_FUNCTION2__DATAVADDR0___S 12 +#define DBG_PHYA_DWT_FUNCTION2__DATAVSIZE___M 0x00000C00 +#define DBG_PHYA_DWT_FUNCTION2__DATAVSIZE___S 10 +#define DBG_PHYA_DWT_FUNCTION2__LNK1ENA___M 0x00000200 +#define DBG_PHYA_DWT_FUNCTION2__LNK1ENA___S 9 +#define DBG_PHYA_DWT_FUNCTION2__DATAVMATCH___M 0x00000100 +#define DBG_PHYA_DWT_FUNCTION2__DATAVMATCH___S 8 +#define DBG_PHYA_DWT_FUNCTION2__CYCMATCH___M 0x00000080 +#define DBG_PHYA_DWT_FUNCTION2__CYCMATCH___S 7 +#define DBG_PHYA_DWT_FUNCTION2__EMITRANGE___M 0x00000020 +#define DBG_PHYA_DWT_FUNCTION2__EMITRANGE___S 5 +#define DBG_PHYA_DWT_FUNCTION2__FUNCTION___M 0x0000000F +#define DBG_PHYA_DWT_FUNCTION2__FUNCTION___S 0 +#define DBG_PHYA_DWT_FUNCTION3 (0x00BE9058) +#define DBG_PHYA_DWT_FUNCTION3___RWC QCSR_REG_RW +#define DBG_PHYA_DWT_FUNCTION3__MATCHED___M 0x01000000 +#define DBG_PHYA_DWT_FUNCTION3__MATCHED___S 24 +#define DBG_PHYA_DWT_FUNCTION3__DATAVADDR1___M 0x000F0000 +#define DBG_PHYA_DWT_FUNCTION3__DATAVADDR1___S 16 +#define DBG_PHYA_DWT_FUNCTION3__DATAVADDR0___M 0x0000F000 +#define DBG_PHYA_DWT_FUNCTION3__DATAVADDR0___S 12 +#define DBG_PHYA_DWT_FUNCTION3__DATAVSIZE___M 0x00000C00 +#define DBG_PHYA_DWT_FUNCTION3__DATAVSIZE___S 10 +#define DBG_PHYA_DWT_FUNCTION3__LNK1ENA___M 0x00000200 +#define DBG_PHYA_DWT_FUNCTION3__LNK1ENA___S 9 +#define DBG_PHYA_DWT_FUNCTION3__DATAVMATCH___M 0x00000100 +#define DBG_PHYA_DWT_FUNCTION3__DATAVMATCH___S 8 +#define DBG_PHYA_DWT_FUNCTION3__CYCMATCH___M 0x00000080 +#define DBG_PHYA_DWT_FUNCTION3__CYCMATCH___S 7 +#define DBG_PHYA_DWT_FUNCTION3__EMITRANGE___M 0x00000020 +#define DBG_PHYA_DWT_FUNCTION3__EMITRANGE___S 5 +#define DBG_PHYA_DWT_FUNCTION3__FUNCTION___M 0x0000000F +#define DBG_PHYA_DWT_FUNCTION3__FUNCTION___S 0 + +#define DBG_PHYA_DWT_PIDR4 (0x00BE9FD0) +#define DBG_PHYA_DWT_PIDR4___RWC QCSR_REG_RO +#define DBG_PHYA_DWT_PIDR4___POR 0x00000004 +#define DBG_PHYA_DWT_PIDR4__FIELD_4KB_COUNT___POR 0x0 +#define DBG_PHYA_DWT_PIDR4__JEP106_CONTINUATION___POR 0x4 +#define DBG_PHYA_DWT_PIDR4__FIELD_4KB_COUNT___M 0x000000F0 +#define DBG_PHYA_DWT_PIDR4__FIELD_4KB_COUNT___S 4 +#define DBG_PHYA_DWT_PIDR4__JEP106_CONTINUATION___M 0x0000000F +#define DBG_PHYA_DWT_PIDR4__JEP106_CONTINUATION___S 0 +#define DBG_PHYA_DWT_PIDR4___M 0x000000FF +#define DBG_PHYA_DWT_PIDR4___S 0 + +#define DBG_PHYA_DWT_PIDR0 (0x00BE9FE0) +#define DBG_PHYA_DWT_PIDR0___RWC QCSR_REG_RO +#define DBG_PHYA_DWT_PIDR0___POR 0x00000002 +#define DBG_PHYA_DWT_PIDR0__PARTNUM_7_0___POR 0x02 +#define DBG_PHYA_DWT_PIDR0__PARTNUM_7_0___M 0x000000FF +#define DBG_PHYA_DWT_PIDR0__PARTNUM_7_0___S 0 +#define DBG_PHYA_DWT_PIDR0___M 0x000000FF +#define DBG_PHYA_DWT_PIDR0___S 0 + +#define DBG_PHYA_DWT_PIDR1 (0x00BE9FE4) +#define DBG_PHYA_DWT_PIDR1___RWC QCSR_REG_RO +#define DBG_PHYA_DWT_PIDR1___POR 0x000000B0 +#define DBG_PHYA_DWT_PIDR1__JEP106_IDENTITY_3_0___POR 0xB +#define DBG_PHYA_DWT_PIDR1__PARTNUM_11_8___POR 0x0 +#define DBG_PHYA_DWT_PIDR1__JEP106_IDENTITY_3_0___M 0x000000F0 +#define DBG_PHYA_DWT_PIDR1__JEP106_IDENTITY_3_0___S 4 +#define DBG_PHYA_DWT_PIDR1__PARTNUM_11_8___M 0x0000000F +#define DBG_PHYA_DWT_PIDR1__PARTNUM_11_8___S 0 +#define DBG_PHYA_DWT_PIDR1___M 0x000000FF +#define DBG_PHYA_DWT_PIDR1___S 0 + +#define DBG_PHYA_DWT_PIDR2 (0x00BE9FE8) +#define DBG_PHYA_DWT_PIDR2___RWC QCSR_REG_RO +#define DBG_PHYA_DWT_PIDR2___POR 0x0000003B +#define DBG_PHYA_DWT_PIDR2__MAJREV___POR 0x3 +#define DBG_PHYA_DWT_PIDR2__JEDEC___POR 0x1 +#define DBG_PHYA_DWT_PIDR2__JEP106_IDENTITY_6_4___POR 0x3 +#define DBG_PHYA_DWT_PIDR2__MAJREV___M 0x000000F0 +#define DBG_PHYA_DWT_PIDR2__MAJREV___S 4 +#define DBG_PHYA_DWT_PIDR2__JEDEC___M 0x00000008 +#define DBG_PHYA_DWT_PIDR2__JEDEC___S 3 +#define DBG_PHYA_DWT_PIDR2__JEP106_IDENTITY_6_4___M 0x00000007 +#define DBG_PHYA_DWT_PIDR2__JEP106_IDENTITY_6_4___S 0 +#define DBG_PHYA_DWT_PIDR2___M 0x000000FF +#define DBG_PHYA_DWT_PIDR2___S 0 + +#define DBG_PHYA_DWT_PIDR3 (0x00BE9FEC) +#define DBG_PHYA_DWT_PIDR3___RWC QCSR_REG_RO +#define DBG_PHYA_DWT_PIDR3___POR 0x00000000 +#define DBG_PHYA_DWT_PIDR3__REV_AND___POR 0x0 +#define DBG_PHYA_DWT_PIDR3__CUSTOMER_MODIFIED___POR 0x0 +#define DBG_PHYA_DWT_PIDR3__REV_AND___M 0x000000F0 +#define DBG_PHYA_DWT_PIDR3__REV_AND___S 4 +#define DBG_PHYA_DWT_PIDR3__CUSTOMER_MODIFIED___M 0x0000000F +#define DBG_PHYA_DWT_PIDR3__CUSTOMER_MODIFIED___S 0 +#define DBG_PHYA_DWT_PIDR3___M 0x000000FF +#define DBG_PHYA_DWT_PIDR3___S 0 + +#define DBG_PHYA_DWT_CIDR0 (0x00BE9FF0) +#define DBG_PHYA_DWT_CIDR0___RWC QCSR_REG_RO +#define DBG_PHYA_DWT_CIDR0___POR 0x0000000D +#define DBG_PHYA_DWT_CIDR0__PREAMBLE_7_0___POR 0x0D +#define DBG_PHYA_DWT_CIDR0__PREAMBLE_7_0___M 0x000000FF +#define DBG_PHYA_DWT_CIDR0__PREAMBLE_7_0___S 0 +#define DBG_PHYA_DWT_CIDR0___M 0x000000FF +#define DBG_PHYA_DWT_CIDR0___S 0 + +#define DBG_PHYA_DWT_CIDR1 (0x00BE9FF4) +#define DBG_PHYA_DWT_CIDR1___RWC QCSR_REG_RO +#define DBG_PHYA_DWT_CIDR1___POR 0x000000E0 +#define DBG_PHYA_DWT_CIDR1__PREAMBLE_15_12___POR 0xE +#define DBG_PHYA_DWT_CIDR1__PREAMBLE_11_8___POR 0x0 +#define DBG_PHYA_DWT_CIDR1__PREAMBLE_15_12___M 0x000000F0 +#define DBG_PHYA_DWT_CIDR1__PREAMBLE_15_12___S 4 +#define DBG_PHYA_DWT_CIDR1__PREAMBLE_11_8___M 0x0000000F +#define DBG_PHYA_DWT_CIDR1__PREAMBLE_11_8___S 0 +#define DBG_PHYA_DWT_CIDR1___M 0x000000FF +#define DBG_PHYA_DWT_CIDR1___S 0 + +#define DBG_PHYA_DWT_CIDR2 (0x00BE9FF8) +#define DBG_PHYA_DWT_CIDR2___RWC QCSR_REG_RO +#define DBG_PHYA_DWT_CIDR2___POR 0x00000005 +#define DBG_PHYA_DWT_CIDR2__PREAMBLE_23_16___POR 0x05 +#define DBG_PHYA_DWT_CIDR2__PREAMBLE_23_16___M 0x000000FF +#define DBG_PHYA_DWT_CIDR2__PREAMBLE_23_16___S 0 +#define DBG_PHYA_DWT_CIDR2___M 0x000000FF +#define DBG_PHYA_DWT_CIDR2___S 0 + +#define DBG_PHYA_DWT_CIDR3 (0x00BE9FFC) +#define DBG_PHYA_DWT_CIDR3___RWC QCSR_REG_RO +#define DBG_PHYA_DWT_CIDR3___POR 0x000000B1 +#define DBG_PHYA_DWT_CIDR3__PREAMBLE_31_24___POR 0xB1 +#define DBG_PHYA_DWT_CIDR3__PREAMBLE_31_24___M 0x000000FF +#define DBG_PHYA_DWT_CIDR3__PREAMBLE_31_24___S 0 +#define DBG_PHYA_DWT_CIDR3___M 0x000000FF +#define DBG_PHYA_DWT_CIDR3___S 0 + +#define DBG_PHYA_FP_CTRL (0x00BEA000) +#define DBG_PHYA_FP_CTRL___RWC QCSR_REG_RW +#define DBG_PHYA_FP_CTRL___POR 0x00000260 +#define DBG_PHYA_FP_CTRL__REV___POR 0x0 +#define DBG_PHYA_FP_CTRL__NUM_CODE_6_4___POR 0x0 +#define DBG_PHYA_FP_CTRL__NUM_LIT___POR 0x2 +#define DBG_PHYA_FP_CTRL__NUM_CODE_3_0___POR 0x6 +#define DBG_PHYA_FP_CTRL__KEY___POR 0x0 +#define DBG_PHYA_FP_CTRL__ENABLE___POR 0x0 +#define DBG_PHYA_FP_CTRL__REV___M 0xF0000000 +#define DBG_PHYA_FP_CTRL__REV___S 28 +#define DBG_PHYA_FP_CTRL__NUM_CODE_6_4___M 0x00007000 +#define DBG_PHYA_FP_CTRL__NUM_CODE_6_4___S 12 +#define DBG_PHYA_FP_CTRL__NUM_LIT___M 0x00000F00 +#define DBG_PHYA_FP_CTRL__NUM_LIT___S 8 +#define DBG_PHYA_FP_CTRL__NUM_CODE_3_0___M 0x000000F0 +#define DBG_PHYA_FP_CTRL__NUM_CODE_3_0___S 4 +#define DBG_PHYA_FP_CTRL__KEY___M 0x00000002 +#define DBG_PHYA_FP_CTRL__KEY___S 1 +#define DBG_PHYA_FP_CTRL__ENABLE___M 0x00000001 +#define DBG_PHYA_FP_CTRL__ENABLE___S 0 +#define DBG_PHYA_FP_CTRL___M 0xF0007FF3 +#define DBG_PHYA_FP_CTRL___S 0 + +#define DBG_PHYA_FP_REMAP (0x00BEA004) +#define DBG_PHYA_FP_REMAP___RWC QCSR_REG_RW +#define DBG_PHYA_FP_REMAP__RMPSPT___M 0x20000000 +#define DBG_PHYA_FP_REMAP__RMPSPT___S 29 +#define DBG_PHYA_FP_REMAP__RMPSPT__BKPT_ONLY 0x0 +#define DBG_PHYA_FP_REMAP__RMPSPT__REMAP_SUPPORTED 0x1 +#define DBG_PHYA_FP_REMAP__REMAP___M 0x1FFFFFE0 +#define DBG_PHYA_FP_REMAP__REMAP___S 5 +#define DBG_PHYA_FP_REMAP___M 0x3FFFFFE0 +#define DBG_PHYA_FP_REMAP___S 5 + +#define DBG_PHYA_FP_COMPn(n) (0x00BEA008+0x4*(n)) +#define DBG_PHYA_FP_COMPn_nMIN 0 +#define DBG_PHYA_FP_COMPn_nMAX 7 +#define DBG_PHYA_FP_COMPn_ELEM 8 +#define DBG_PHYA_FP_COMPn___RWC QCSR_REG_RW +#define DBG_PHYA_FP_COMPn___POR 0x00000000 +#define DBG_PHYA_FP_COMPn__REPLACE___POR 0x0 +#define DBG_PHYA_FP_COMPn__COMP___POR 0x0000000 +#define DBG_PHYA_FP_COMPn__ENABLE___POR 0x0 +#define DBG_PHYA_FP_COMPn__REPLACE___M 0xC0000000 +#define DBG_PHYA_FP_COMPn__REPLACE___S 30 +#define DBG_PHYA_FP_COMPn__REPLACE__REPLACE 0x0 +#define DBG_PHYA_FP_COMPn__REPLACE__BKPTATZERO 0x1 +#define DBG_PHYA_FP_COMPn__REPLACE__BKPTATZEROANDTWO 0x2 +#define DBG_PHYA_FP_COMPn__REPLACE__BKPTATBOTH 0x3 +#define DBG_PHYA_FP_COMPn__COMP___M 0x1FFFFFFC +#define DBG_PHYA_FP_COMPn__COMP___S 2 +#define DBG_PHYA_FP_COMPn__ENABLE___M 0x00000001 +#define DBG_PHYA_FP_COMPn__ENABLE___S 0 +#define DBG_PHYA_FP_COMPn__ENABLE__COMPDISABLED 0x0 +#define DBG_PHYA_FP_COMPn__ENABLE__COMPENABLED 0x1 +#define DBG_PHYA_FP_COMPn___M 0xDFFFFFFD +#define DBG_PHYA_FP_COMPn___S 0 +#define DBG_PHYA_FP_COMP0 (0x00BEA008) +#define DBG_PHYA_FP_COMP0___RWC QCSR_REG_RW +#define DBG_PHYA_FP_COMP0__REPLACE___M 0xC0000000 +#define DBG_PHYA_FP_COMP0__REPLACE___S 30 +#define DBG_PHYA_FP_COMP0__COMP___M 0x1FFFFFFC +#define DBG_PHYA_FP_COMP0__COMP___S 2 +#define DBG_PHYA_FP_COMP0__ENABLE___M 0x00000001 +#define DBG_PHYA_FP_COMP0__ENABLE___S 0 +#define DBG_PHYA_FP_COMP1 (0x00BEA00C) +#define DBG_PHYA_FP_COMP1___RWC QCSR_REG_RW +#define DBG_PHYA_FP_COMP1__REPLACE___M 0xC0000000 +#define DBG_PHYA_FP_COMP1__REPLACE___S 30 +#define DBG_PHYA_FP_COMP1__COMP___M 0x1FFFFFFC +#define DBG_PHYA_FP_COMP1__COMP___S 2 +#define DBG_PHYA_FP_COMP1__ENABLE___M 0x00000001 +#define DBG_PHYA_FP_COMP1__ENABLE___S 0 +#define DBG_PHYA_FP_COMP2 (0x00BEA010) +#define DBG_PHYA_FP_COMP2___RWC QCSR_REG_RW +#define DBG_PHYA_FP_COMP2__REPLACE___M 0xC0000000 +#define DBG_PHYA_FP_COMP2__REPLACE___S 30 +#define DBG_PHYA_FP_COMP2__COMP___M 0x1FFFFFFC +#define DBG_PHYA_FP_COMP2__COMP___S 2 +#define DBG_PHYA_FP_COMP2__ENABLE___M 0x00000001 +#define DBG_PHYA_FP_COMP2__ENABLE___S 0 +#define DBG_PHYA_FP_COMP3 (0x00BEA014) +#define DBG_PHYA_FP_COMP3___RWC QCSR_REG_RW +#define DBG_PHYA_FP_COMP3__REPLACE___M 0xC0000000 +#define DBG_PHYA_FP_COMP3__REPLACE___S 30 +#define DBG_PHYA_FP_COMP3__COMP___M 0x1FFFFFFC +#define DBG_PHYA_FP_COMP3__COMP___S 2 +#define DBG_PHYA_FP_COMP3__ENABLE___M 0x00000001 +#define DBG_PHYA_FP_COMP3__ENABLE___S 0 +#define DBG_PHYA_FP_COMP4 (0x00BEA018) +#define DBG_PHYA_FP_COMP4___RWC QCSR_REG_RW +#define DBG_PHYA_FP_COMP4__REPLACE___M 0xC0000000 +#define DBG_PHYA_FP_COMP4__REPLACE___S 30 +#define DBG_PHYA_FP_COMP4__COMP___M 0x1FFFFFFC +#define DBG_PHYA_FP_COMP4__COMP___S 2 +#define DBG_PHYA_FP_COMP4__ENABLE___M 0x00000001 +#define DBG_PHYA_FP_COMP4__ENABLE___S 0 +#define DBG_PHYA_FP_COMP5 (0x00BEA01C) +#define DBG_PHYA_FP_COMP5___RWC QCSR_REG_RW +#define DBG_PHYA_FP_COMP5__REPLACE___M 0xC0000000 +#define DBG_PHYA_FP_COMP5__REPLACE___S 30 +#define DBG_PHYA_FP_COMP5__COMP___M 0x1FFFFFFC +#define DBG_PHYA_FP_COMP5__COMP___S 2 +#define DBG_PHYA_FP_COMP5__ENABLE___M 0x00000001 +#define DBG_PHYA_FP_COMP5__ENABLE___S 0 +#define DBG_PHYA_FP_COMP6 (0x00BEA020) +#define DBG_PHYA_FP_COMP6___RWC QCSR_REG_RW +#define DBG_PHYA_FP_COMP6__REPLACE___M 0xC0000000 +#define DBG_PHYA_FP_COMP6__REPLACE___S 30 +#define DBG_PHYA_FP_COMP6__COMP___M 0x1FFFFFFC +#define DBG_PHYA_FP_COMP6__COMP___S 2 +#define DBG_PHYA_FP_COMP6__ENABLE___M 0x00000001 +#define DBG_PHYA_FP_COMP6__ENABLE___S 0 +#define DBG_PHYA_FP_COMP7 (0x00BEA024) +#define DBG_PHYA_FP_COMP7___RWC QCSR_REG_RW +#define DBG_PHYA_FP_COMP7__REPLACE___M 0xC0000000 +#define DBG_PHYA_FP_COMP7__REPLACE___S 30 +#define DBG_PHYA_FP_COMP7__COMP___M 0x1FFFFFFC +#define DBG_PHYA_FP_COMP7__COMP___S 2 +#define DBG_PHYA_FP_COMP7__ENABLE___M 0x00000001 +#define DBG_PHYA_FP_COMP7__ENABLE___S 0 + +#define DBG_PHYA_FP_PIDR4 (0x00BEAFD0) +#define DBG_PHYA_FP_PIDR4___RWC QCSR_REG_RO +#define DBG_PHYA_FP_PIDR4___POR 0x00000004 +#define DBG_PHYA_FP_PIDR4__FIELD_4KB_COUNT___POR 0x0 +#define DBG_PHYA_FP_PIDR4__JEP106_CONTINUATION___POR 0x4 +#define DBG_PHYA_FP_PIDR4__FIELD_4KB_COUNT___M 0x000000F0 +#define DBG_PHYA_FP_PIDR4__FIELD_4KB_COUNT___S 4 +#define DBG_PHYA_FP_PIDR4__JEP106_CONTINUATION___M 0x0000000F +#define DBG_PHYA_FP_PIDR4__JEP106_CONTINUATION___S 0 +#define DBG_PHYA_FP_PIDR4___M 0x000000FF +#define DBG_PHYA_FP_PIDR4___S 0 + +#define DBG_PHYA_FP_PIDR0 (0x00BEAFE0) +#define DBG_PHYA_FP_PIDR0___RWC QCSR_REG_RO +#define DBG_PHYA_FP_PIDR0___POR 0x00000003 +#define DBG_PHYA_FP_PIDR0__PARTNUM_7_0___POR 0x03 +#define DBG_PHYA_FP_PIDR0__PARTNUM_7_0___M 0x000000FF +#define DBG_PHYA_FP_PIDR0__PARTNUM_7_0___S 0 +#define DBG_PHYA_FP_PIDR0___M 0x000000FF +#define DBG_PHYA_FP_PIDR0___S 0 + +#define DBG_PHYA_FP_PIDR1 (0x00BEAFE4) +#define DBG_PHYA_FP_PIDR1___RWC QCSR_REG_RO +#define DBG_PHYA_FP_PIDR1___POR 0x000000B0 +#define DBG_PHYA_FP_PIDR1__JEP106_IDENTITY_3_0___POR 0xB +#define DBG_PHYA_FP_PIDR1__PARTNUM_11_8___POR 0x0 +#define DBG_PHYA_FP_PIDR1__JEP106_IDENTITY_3_0___M 0x000000F0 +#define DBG_PHYA_FP_PIDR1__JEP106_IDENTITY_3_0___S 4 +#define DBG_PHYA_FP_PIDR1__PARTNUM_11_8___M 0x0000000F +#define DBG_PHYA_FP_PIDR1__PARTNUM_11_8___S 0 +#define DBG_PHYA_FP_PIDR1___M 0x000000FF +#define DBG_PHYA_FP_PIDR1___S 0 + +#define DBG_PHYA_FP_PIDR2 (0x00BEAFE8) +#define DBG_PHYA_FP_PIDR2___RWC QCSR_REG_RO +#define DBG_PHYA_FP_PIDR2___POR 0x0000002B +#define DBG_PHYA_FP_PIDR2__MAJREV___POR 0x2 +#define DBG_PHYA_FP_PIDR2__JEDEC___POR 0x1 +#define DBG_PHYA_FP_PIDR2__JEP106_IDENTITY_6_4___POR 0x3 +#define DBG_PHYA_FP_PIDR2__MAJREV___M 0x000000F0 +#define DBG_PHYA_FP_PIDR2__MAJREV___S 4 +#define DBG_PHYA_FP_PIDR2__JEDEC___M 0x00000008 +#define DBG_PHYA_FP_PIDR2__JEDEC___S 3 +#define DBG_PHYA_FP_PIDR2__JEP106_IDENTITY_6_4___M 0x00000007 +#define DBG_PHYA_FP_PIDR2__JEP106_IDENTITY_6_4___S 0 +#define DBG_PHYA_FP_PIDR2___M 0x000000FF +#define DBG_PHYA_FP_PIDR2___S 0 + +#define DBG_PHYA_FP_PIDR3 (0x00BEAFEC) +#define DBG_PHYA_FP_PIDR3___RWC QCSR_REG_RO +#define DBG_PHYA_FP_PIDR3___POR 0x00000000 +#define DBG_PHYA_FP_PIDR3__REV_AND___POR 0x0 +#define DBG_PHYA_FP_PIDR3__CUSTOMER_MODIFIED___POR 0x0 +#define DBG_PHYA_FP_PIDR3__REV_AND___M 0x000000F0 +#define DBG_PHYA_FP_PIDR3__REV_AND___S 4 +#define DBG_PHYA_FP_PIDR3__CUSTOMER_MODIFIED___M 0x0000000F +#define DBG_PHYA_FP_PIDR3__CUSTOMER_MODIFIED___S 0 +#define DBG_PHYA_FP_PIDR3___M 0x000000FF +#define DBG_PHYA_FP_PIDR3___S 0 + +#define DBG_PHYA_FP_CIDR0 (0x00BEAFF0) +#define DBG_PHYA_FP_CIDR0___RWC QCSR_REG_RO +#define DBG_PHYA_FP_CIDR0___POR 0x0000000D +#define DBG_PHYA_FP_CIDR0__PREAMBLE_7_0___POR 0x0D +#define DBG_PHYA_FP_CIDR0__PREAMBLE_7_0___M 0x000000FF +#define DBG_PHYA_FP_CIDR0__PREAMBLE_7_0___S 0 +#define DBG_PHYA_FP_CIDR0___M 0x000000FF +#define DBG_PHYA_FP_CIDR0___S 0 + +#define DBG_PHYA_FP_CIDR1 (0x00BEAFF4) +#define DBG_PHYA_FP_CIDR1___RWC QCSR_REG_RO +#define DBG_PHYA_FP_CIDR1___POR 0x000000E0 +#define DBG_PHYA_FP_CIDR1__PREAMBLE_15_12___POR 0xE +#define DBG_PHYA_FP_CIDR1__PREAMBLE_11_8___POR 0x0 +#define DBG_PHYA_FP_CIDR1__PREAMBLE_15_12___M 0x000000F0 +#define DBG_PHYA_FP_CIDR1__PREAMBLE_15_12___S 4 +#define DBG_PHYA_FP_CIDR1__PREAMBLE_11_8___M 0x0000000F +#define DBG_PHYA_FP_CIDR1__PREAMBLE_11_8___S 0 +#define DBG_PHYA_FP_CIDR1___M 0x000000FF +#define DBG_PHYA_FP_CIDR1___S 0 + +#define DBG_PHYA_FP_CIDR2 (0x00BEAFF8) +#define DBG_PHYA_FP_CIDR2___RWC QCSR_REG_RO +#define DBG_PHYA_FP_CIDR2___POR 0x00000005 +#define DBG_PHYA_FP_CIDR2__PREAMBLE_23_16___POR 0x05 +#define DBG_PHYA_FP_CIDR2__PREAMBLE_23_16___M 0x000000FF +#define DBG_PHYA_FP_CIDR2__PREAMBLE_23_16___S 0 +#define DBG_PHYA_FP_CIDR2___M 0x000000FF +#define DBG_PHYA_FP_CIDR2___S 0 + +#define DBG_PHYA_FP_CIDR3 (0x00BEAFFC) +#define DBG_PHYA_FP_CIDR3___RWC QCSR_REG_RO +#define DBG_PHYA_FP_CIDR3___POR 0x000000B1 +#define DBG_PHYA_FP_CIDR3__PREAMBLE_31_24___POR 0xB1 +#define DBG_PHYA_FP_CIDR3__PREAMBLE_31_24___M 0x000000FF +#define DBG_PHYA_FP_CIDR3__PREAMBLE_31_24___S 0 +#define DBG_PHYA_FP_CIDR3___M 0x000000FF +#define DBG_PHYA_FP_CIDR3___S 0 + +#define DBG_PHYA_SCS_ICTR (0x00BEB004) +#define DBG_PHYA_SCS_ICTR___RWC QCSR_REG_RO +#define DBG_PHYA_SCS_ICTR___POR 0x00000007 +#define DBG_PHYA_SCS_ICTR__INTLINESNUM___POR 0x7 +#define DBG_PHYA_SCS_ICTR__INTLINESNUM___M 0x0000000F +#define DBG_PHYA_SCS_ICTR__INTLINESNUM___S 0 +#define DBG_PHYA_SCS_ICTR___M 0x0000000F +#define DBG_PHYA_SCS_ICTR___S 0 + +#define DBG_PHYA_SCS_ACTLR (0x00BEB008) +#define DBG_PHYA_SCS_ACTLR___RWC QCSR_REG_RW +#define DBG_PHYA_SCS_ACTLR___POR 0x00000000 +#define DBG_PHYA_SCS_ACTLR__DISFOLD___POR 0x0 +#define DBG_PHYA_SCS_ACTLR__DISDEFWBUF___POR 0x0 +#define DBG_PHYA_SCS_ACTLR__DISMCYCINT___POR 0x0 +#define DBG_PHYA_SCS_ACTLR__DISFOLD___M 0x00000004 +#define DBG_PHYA_SCS_ACTLR__DISFOLD___S 2 +#define DBG_PHYA_SCS_ACTLR__DISDEFWBUF___M 0x00000002 +#define DBG_PHYA_SCS_ACTLR__DISDEFWBUF___S 1 +#define DBG_PHYA_SCS_ACTLR__DISMCYCINT___M 0x00000001 +#define DBG_PHYA_SCS_ACTLR__DISMCYCINT___S 0 +#define DBG_PHYA_SCS_ACTLR___M 0x00000007 +#define DBG_PHYA_SCS_ACTLR___S 0 + +#define DBG_PHYA_SCS_STCSR (0x00BEB010) +#define DBG_PHYA_SCS_STCSR___RWC QCSR_REG_RW +#define DBG_PHYA_SCS_STCSR___POR 0x00000004 +#define DBG_PHYA_SCS_STCSR__COUNTFLAG___POR 0x0 +#define DBG_PHYA_SCS_STCSR__CLKSOURCE___POR 0x1 +#define DBG_PHYA_SCS_STCSR__TICKINT___POR 0x0 +#define DBG_PHYA_SCS_STCSR__ENABLE___POR 0x0 +#define DBG_PHYA_SCS_STCSR__COUNTFLAG___M 0x00010000 +#define DBG_PHYA_SCS_STCSR__COUNTFLAG___S 16 +#define DBG_PHYA_SCS_STCSR__CLKSOURCE___M 0x00000004 +#define DBG_PHYA_SCS_STCSR__CLKSOURCE___S 2 +#define DBG_PHYA_SCS_STCSR__CLKSOURCE__EXTERNAL 0x0 +#define DBG_PHYA_SCS_STCSR__CLKSOURCE__CPU_CLK 0x1 +#define DBG_PHYA_SCS_STCSR__TICKINT___M 0x00000002 +#define DBG_PHYA_SCS_STCSR__TICKINT___S 1 +#define DBG_PHYA_SCS_STCSR__ENABLE___M 0x00000001 +#define DBG_PHYA_SCS_STCSR__ENABLE___S 0 +#define DBG_PHYA_SCS_STCSR___M 0x00010007 +#define DBG_PHYA_SCS_STCSR___S 0 + +#define DBG_PHYA_SCS_STRVR (0x00BEB014) +#define DBG_PHYA_SCS_STRVR___RWC QCSR_REG_RW +#define DBG_PHYA_SCS_STRVR___POR 0x00000000 +#define DBG_PHYA_SCS_STRVR__RELOAD___POR 0x000000 +#define DBG_PHYA_SCS_STRVR__RELOAD___M 0x00FFFFFF +#define DBG_PHYA_SCS_STRVR__RELOAD___S 0 +#define DBG_PHYA_SCS_STRVR___M 0x00FFFFFF +#define DBG_PHYA_SCS_STRVR___S 0 + +#define DBG_PHYA_SCS_STCVR (0x00BEB018) +#define DBG_PHYA_SCS_STCVR___RWC QCSR_REG_RW +#define DBG_PHYA_SCS_STCVR___POR 0x00000000 +#define DBG_PHYA_SCS_STCVR__CURRENT___POR 0x000000 +#define DBG_PHYA_SCS_STCVR__CURRENT___M 0x00FFFFFF +#define DBG_PHYA_SCS_STCVR__CURRENT___S 0 +#define DBG_PHYA_SCS_STCVR___M 0x00FFFFFF +#define DBG_PHYA_SCS_STCVR___S 0 + +#define DBG_PHYA_SCS_STCR (0x00BEB01C) +#define DBG_PHYA_SCS_STCR___RWC QCSR_REG_RO +#define DBG_PHYA_SCS_STCR___POR 0x80000000 +#define DBG_PHYA_SCS_STCR__NOREF___POR 0x1 +#define DBG_PHYA_SCS_STCR__SKEW___POR 0x0 +#define DBG_PHYA_SCS_STCR__TENMS___POR 0x000000 +#define DBG_PHYA_SCS_STCR__NOREF___M 0x80000000 +#define DBG_PHYA_SCS_STCR__NOREF___S 31 +#define DBG_PHYA_SCS_STCR__NOREF__REFCLKNOTIMPLEMENTED 0x1 +#define DBG_PHYA_SCS_STCR__SKEW___M 0x40000000 +#define DBG_PHYA_SCS_STCR__SKEW___S 30 +#define DBG_PHYA_SCS_STCR__SKEW__CALVALUEEXACT 0x0 +#define DBG_PHYA_SCS_STCR__TENMS___M 0x00FFFFFF +#define DBG_PHYA_SCS_STCR__TENMS___S 0 +#define DBG_PHYA_SCS_STCR___M 0xC0FFFFFF +#define DBG_PHYA_SCS_STCR___S 0 + +#define DBG_PHYA_SCS_CPUID (0x00BEBD00) +#define DBG_PHYA_SCS_CPUID___RWC QCSR_REG_RO +#define DBG_PHYA_SCS_CPUID___POR 0x412FC231 +#define DBG_PHYA_SCS_CPUID__IMPLEMENTER___POR 0x41 +#define DBG_PHYA_SCS_CPUID__VARIANT___POR 0x2 +#define DBG_PHYA_SCS_CPUID__CONSTANT___POR 0xF +#define DBG_PHYA_SCS_CPUID__PARTNO___POR 0xC23 +#define DBG_PHYA_SCS_CPUID__REVISION___POR 0x1 +#define DBG_PHYA_SCS_CPUID__IMPLEMENTER___M 0xFF000000 +#define DBG_PHYA_SCS_CPUID__IMPLEMENTER___S 24 +#define DBG_PHYA_SCS_CPUID__IMPLEMENTER__ARM 0x41 +#define DBG_PHYA_SCS_CPUID__VARIANT___M 0x00F00000 +#define DBG_PHYA_SCS_CPUID__VARIANT___S 20 +#define DBG_PHYA_SCS_CPUID__CONSTANT___M 0x000F0000 +#define DBG_PHYA_SCS_CPUID__CONSTANT___S 16 +#define DBG_PHYA_SCS_CPUID__PARTNO___M 0x0000FFF0 +#define DBG_PHYA_SCS_CPUID__PARTNO___S 4 +#define DBG_PHYA_SCS_CPUID__PARTNO__CORTEXM3 0xC23 +#define DBG_PHYA_SCS_CPUID__REVISION___M 0x0000000F +#define DBG_PHYA_SCS_CPUID__REVISION___S 0 +#define DBG_PHYA_SCS_CPUID___M 0xFFFFFFFF +#define DBG_PHYA_SCS_CPUID___S 0 + +#define DBG_PHYA_SCS_ICSR (0x00BEBD04) +#define DBG_PHYA_SCS_ICSR___RWC QCSR_REG_RW +#define DBG_PHYA_SCS_ICSR___POR 0x00000000 +#define DBG_PHYA_SCS_ICSR__NMIPENDSET___POR 0x0 +#define DBG_PHYA_SCS_ICSR__PENDSVSET___POR 0x0 +#define DBG_PHYA_SCS_ICSR__PENDSVCLR___POR 0x0 +#define DBG_PHYA_SCS_ICSR__PENDSTSET___POR 0x0 +#define DBG_PHYA_SCS_ICSR__PENDSTCLR___POR 0x0 +#define DBG_PHYA_SCS_ICSR__ISRPREEMPT___POR 0x0 +#define DBG_PHYA_SCS_ICSR__ISRPENDING___POR 0x0 +#define DBG_PHYA_SCS_ICSR__VECTPENDING___POR 0x000 +#define DBG_PHYA_SCS_ICSR__RETTOBASE___POR 0x0 +#define DBG_PHYA_SCS_ICSR__VECTACTIVE___POR 0x000 +#define DBG_PHYA_SCS_ICSR__NMIPENDSET___M 0x80000000 +#define DBG_PHYA_SCS_ICSR__NMIPENDSET___S 31 +#define DBG_PHYA_SCS_ICSR__PENDSVSET___M 0x10000000 +#define DBG_PHYA_SCS_ICSR__PENDSVSET___S 28 +#define DBG_PHYA_SCS_ICSR__PENDSVCLR___M 0x08000000 +#define DBG_PHYA_SCS_ICSR__PENDSVCLR___S 27 +#define DBG_PHYA_SCS_ICSR__PENDSTSET___M 0x04000000 +#define DBG_PHYA_SCS_ICSR__PENDSTSET___S 26 +#define DBG_PHYA_SCS_ICSR__PENDSTCLR___M 0x02000000 +#define DBG_PHYA_SCS_ICSR__PENDSTCLR___S 25 +#define DBG_PHYA_SCS_ICSR__ISRPREEMPT___M 0x00800000 +#define DBG_PHYA_SCS_ICSR__ISRPREEMPT___S 23 +#define DBG_PHYA_SCS_ICSR__ISRPENDING___M 0x00400000 +#define DBG_PHYA_SCS_ICSR__ISRPENDING___S 22 +#define DBG_PHYA_SCS_ICSR__VECTPENDING___M 0x001FF000 +#define DBG_PHYA_SCS_ICSR__VECTPENDING___S 12 +#define DBG_PHYA_SCS_ICSR__RETTOBASE___M 0x00000800 +#define DBG_PHYA_SCS_ICSR__RETTOBASE___S 11 +#define DBG_PHYA_SCS_ICSR__VECTACTIVE___M 0x000001FF +#define DBG_PHYA_SCS_ICSR__VECTACTIVE___S 0 +#define DBG_PHYA_SCS_ICSR___M 0x9EDFF9FF +#define DBG_PHYA_SCS_ICSR___S 0 + +#define DBG_PHYA_SCS_VTOR (0x00BEBD08) +#define DBG_PHYA_SCS_VTOR___RWC QCSR_REG_RW +#define DBG_PHYA_SCS_VTOR___POR 0x00000000 +#define DBG_PHYA_SCS_VTOR__TBLOFF___POR 0x0000000 +#define DBG_PHYA_SCS_VTOR__TBLOFF___M 0xFFFFFF80 +#define DBG_PHYA_SCS_VTOR__TBLOFF___S 7 +#define DBG_PHYA_SCS_VTOR___M 0xFFFFFF80 +#define DBG_PHYA_SCS_VTOR___S 7 + +#define DBG_PHYA_SCS_AIRCR (0x00BEBD0C) +#define DBG_PHYA_SCS_AIRCR___RWC QCSR_REG_RW +#define DBG_PHYA_SCS_AIRCR___POR 0xFA050000 +#define DBG_PHYA_SCS_AIRCR__VECTKEY___POR 0xFA05 +#define DBG_PHYA_SCS_AIRCR__ENDIANESS___POR 0x0 +#define DBG_PHYA_SCS_AIRCR__PRIGROUP___POR 0x0 +#define DBG_PHYA_SCS_AIRCR__SYSRESETREQ___POR 0x0 +#define DBG_PHYA_SCS_AIRCR__VECTCLRACTIVE___POR 0x0 +#define DBG_PHYA_SCS_AIRCR__VECTRESET___POR 0x0 +#define DBG_PHYA_SCS_AIRCR__VECTKEY___M 0xFFFF0000 +#define DBG_PHYA_SCS_AIRCR__VECTKEY___S 16 +#define DBG_PHYA_SCS_AIRCR__ENDIANESS___M 0x00008000 +#define DBG_PHYA_SCS_AIRCR__ENDIANESS___S 15 +#define DBG_PHYA_SCS_AIRCR__ENDIANESS__LITTLE_ENDIAN 0x0 +#define DBG_PHYA_SCS_AIRCR__PRIGROUP___M 0x00000700 +#define DBG_PHYA_SCS_AIRCR__PRIGROUP___S 8 +#define DBG_PHYA_SCS_AIRCR__SYSRESETREQ___M 0x00000004 +#define DBG_PHYA_SCS_AIRCR__SYSRESETREQ___S 2 +#define DBG_PHYA_SCS_AIRCR__VECTCLRACTIVE___M 0x00000002 +#define DBG_PHYA_SCS_AIRCR__VECTCLRACTIVE___S 1 +#define DBG_PHYA_SCS_AIRCR__VECTRESET___M 0x00000001 +#define DBG_PHYA_SCS_AIRCR__VECTRESET___S 0 +#define DBG_PHYA_SCS_AIRCR___M 0xFFFF8707 +#define DBG_PHYA_SCS_AIRCR___S 0 + +#define DBG_PHYA_SCS_SCR (0x00BEBD10) +#define DBG_PHYA_SCS_SCR___RWC QCSR_REG_RW +#define DBG_PHYA_SCS_SCR___POR 0x00000000 +#define DBG_PHYA_SCS_SCR__SEVONPEND___POR 0x0 +#define DBG_PHYA_SCS_SCR__SLEEPDEEP___POR 0x0 +#define DBG_PHYA_SCS_SCR__SLEEPONEXIT___POR 0x0 +#define DBG_PHYA_SCS_SCR__SEVONPEND___M 0x00000010 +#define DBG_PHYA_SCS_SCR__SEVONPEND___S 4 +#define DBG_PHYA_SCS_SCR__SLEEPDEEP___M 0x00000004 +#define DBG_PHYA_SCS_SCR__SLEEPDEEP___S 2 +#define DBG_PHYA_SCS_SCR__SLEEPONEXIT___M 0x00000002 +#define DBG_PHYA_SCS_SCR__SLEEPONEXIT___S 1 +#define DBG_PHYA_SCS_SCR___M 0x00000016 +#define DBG_PHYA_SCS_SCR___S 1 + +#define DBG_PHYA_SCS_CCR (0x00BEBD14) +#define DBG_PHYA_SCS_CCR___RWC QCSR_REG_RW +#define DBG_PHYA_SCS_CCR___POR 0x00000200 +#define DBG_PHYA_SCS_CCR__BP___POR 0x0 +#define DBG_PHYA_SCS_CCR__IC___POR 0x0 +#define DBG_PHYA_SCS_CCR__DC___POR 0x0 +#define DBG_PHYA_SCS_CCR__STKALIGN___POR 0x1 +#define DBG_PHYA_SCS_CCR__BFHFNMIGN___POR 0x0 +#define DBG_PHYA_SCS_CCR__DIV_0_TRP___POR 0x0 +#define DBG_PHYA_SCS_CCR__UNALIGN_TRP___POR 0x0 +#define DBG_PHYA_SCS_CCR__USERSETMPEND___POR 0x0 +#define DBG_PHYA_SCS_CCR__NONBASETHRDENA___POR 0x0 +#define DBG_PHYA_SCS_CCR__BP___M 0x00040000 +#define DBG_PHYA_SCS_CCR__BP___S 18 +#define DBG_PHYA_SCS_CCR__IC___M 0x00020000 +#define DBG_PHYA_SCS_CCR__IC___S 17 +#define DBG_PHYA_SCS_CCR__DC___M 0x00010000 +#define DBG_PHYA_SCS_CCR__DC___S 16 +#define DBG_PHYA_SCS_CCR__STKALIGN___M 0x00000200 +#define DBG_PHYA_SCS_CCR__STKALIGN___S 9 +#define DBG_PHYA_SCS_CCR__BFHFNMIGN___M 0x00000100 +#define DBG_PHYA_SCS_CCR__BFHFNMIGN___S 8 +#define DBG_PHYA_SCS_CCR__DIV_0_TRP___M 0x00000010 +#define DBG_PHYA_SCS_CCR__DIV_0_TRP___S 4 +#define DBG_PHYA_SCS_CCR__UNALIGN_TRP___M 0x00000008 +#define DBG_PHYA_SCS_CCR__UNALIGN_TRP___S 3 +#define DBG_PHYA_SCS_CCR__USERSETMPEND___M 0x00000002 +#define DBG_PHYA_SCS_CCR__USERSETMPEND___S 1 +#define DBG_PHYA_SCS_CCR__NONBASETHRDENA___M 0x00000001 +#define DBG_PHYA_SCS_CCR__NONBASETHRDENA___S 0 +#define DBG_PHYA_SCS_CCR___M 0x0007031B +#define DBG_PHYA_SCS_CCR___S 0 + +#define DBG_PHYA_SCS_SHPR1 (0x00BEBD18) +#define DBG_PHYA_SCS_SHPR1___RWC QCSR_REG_RW +#define DBG_PHYA_SCS_SHPR1___POR 0x00000000 +#define DBG_PHYA_SCS_SHPR1__PRI_7___POR 0x00 +#define DBG_PHYA_SCS_SHPR1__PRI_6___POR 0x00 +#define DBG_PHYA_SCS_SHPR1__PRI_5___POR 0x00 +#define DBG_PHYA_SCS_SHPR1__PRI_4___POR 0x00 +#define DBG_PHYA_SCS_SHPR1__PRI_7___M 0xFF000000 +#define DBG_PHYA_SCS_SHPR1__PRI_7___S 24 +#define DBG_PHYA_SCS_SHPR1__PRI_6___M 0x00FF0000 +#define DBG_PHYA_SCS_SHPR1__PRI_6___S 16 +#define DBG_PHYA_SCS_SHPR1__PRI_5___M 0x0000FF00 +#define DBG_PHYA_SCS_SHPR1__PRI_5___S 8 +#define DBG_PHYA_SCS_SHPR1__PRI_4___M 0x000000FF +#define DBG_PHYA_SCS_SHPR1__PRI_4___S 0 +#define DBG_PHYA_SCS_SHPR1___M 0xFFFFFFFF +#define DBG_PHYA_SCS_SHPR1___S 0 + +#define DBG_PHYA_SCS_SHPR2 (0x00BEBD1C) +#define DBG_PHYA_SCS_SHPR2___RWC QCSR_REG_RW +#define DBG_PHYA_SCS_SHPR2___POR 0x00000000 +#define DBG_PHYA_SCS_SHPR2__PRI_11___POR 0x00 +#define DBG_PHYA_SCS_SHPR2__PRI_10___POR 0x00 +#define DBG_PHYA_SCS_SHPR2__PRI_9___POR 0x00 +#define DBG_PHYA_SCS_SHPR2__PRI_8___POR 0x00 +#define DBG_PHYA_SCS_SHPR2__PRI_11___M 0xFF000000 +#define DBG_PHYA_SCS_SHPR2__PRI_11___S 24 +#define DBG_PHYA_SCS_SHPR2__PRI_10___M 0x00FF0000 +#define DBG_PHYA_SCS_SHPR2__PRI_10___S 16 +#define DBG_PHYA_SCS_SHPR2__PRI_9___M 0x0000FF00 +#define DBG_PHYA_SCS_SHPR2__PRI_9___S 8 +#define DBG_PHYA_SCS_SHPR2__PRI_8___M 0x000000FF +#define DBG_PHYA_SCS_SHPR2__PRI_8___S 0 +#define DBG_PHYA_SCS_SHPR2___M 0xFFFFFFFF +#define DBG_PHYA_SCS_SHPR2___S 0 + +#define DBG_PHYA_SCS_SHPR3 (0x00BEBD20) +#define DBG_PHYA_SCS_SHPR3___RWC QCSR_REG_RW +#define DBG_PHYA_SCS_SHPR3___POR 0x00000000 +#define DBG_PHYA_SCS_SHPR3__PRI_15___POR 0x00 +#define DBG_PHYA_SCS_SHPR3__PRI_14___POR 0x00 +#define DBG_PHYA_SCS_SHPR3__PRI_13___POR 0x00 +#define DBG_PHYA_SCS_SHPR3__PRI_12___POR 0x00 +#define DBG_PHYA_SCS_SHPR3__PRI_15___M 0xFF000000 +#define DBG_PHYA_SCS_SHPR3__PRI_15___S 24 +#define DBG_PHYA_SCS_SHPR3__PRI_14___M 0x00FF0000 +#define DBG_PHYA_SCS_SHPR3__PRI_14___S 16 +#define DBG_PHYA_SCS_SHPR3__PRI_13___M 0x0000FF00 +#define DBG_PHYA_SCS_SHPR3__PRI_13___S 8 +#define DBG_PHYA_SCS_SHPR3__PRI_12___M 0x000000FF +#define DBG_PHYA_SCS_SHPR3__PRI_12___S 0 +#define DBG_PHYA_SCS_SHPR3___M 0xFFFFFFFF +#define DBG_PHYA_SCS_SHPR3___S 0 + +#define DBG_PHYA_SCS_SHCR (0x00BEBD24) +#define DBG_PHYA_SCS_SHCR___RWC QCSR_REG_RW +#define DBG_PHYA_SCS_SHCR___POR 0x00000000 +#define DBG_PHYA_SCS_SHCR__USGFAULTENA___POR 0x0 +#define DBG_PHYA_SCS_SHCR__BUSFAULTENA___POR 0x0 +#define DBG_PHYA_SCS_SHCR__MEMFAULTENA___POR 0x0 +#define DBG_PHYA_SCS_SHCR__SVCALLPENDED___POR 0x0 +#define DBG_PHYA_SCS_SHCR__BUSFAULTPENDED___POR 0x0 +#define DBG_PHYA_SCS_SHCR__MEMFAULTPENDED___POR 0x0 +#define DBG_PHYA_SCS_SHCR__USGFAULTPENDED___POR 0x0 +#define DBG_PHYA_SCS_SHCR__SYSTICKACT___POR 0x0 +#define DBG_PHYA_SCS_SHCR__PENDSVACT___POR 0x0 +#define DBG_PHYA_SCS_SHCR__MONITORACT___POR 0x0 +#define DBG_PHYA_SCS_SHCR__SVCALLACT___POR 0x0 +#define DBG_PHYA_SCS_SHCR__USGFAULTACT___POR 0x0 +#define DBG_PHYA_SCS_SHCR__BUSFAULTACT___POR 0x0 +#define DBG_PHYA_SCS_SHCR__MEMFAULTACT___POR 0x0 +#define DBG_PHYA_SCS_SHCR__USGFAULTENA___M 0x00040000 +#define DBG_PHYA_SCS_SHCR__USGFAULTENA___S 18 +#define DBG_PHYA_SCS_SHCR__BUSFAULTENA___M 0x00020000 +#define DBG_PHYA_SCS_SHCR__BUSFAULTENA___S 17 +#define DBG_PHYA_SCS_SHCR__MEMFAULTENA___M 0x00010000 +#define DBG_PHYA_SCS_SHCR__MEMFAULTENA___S 16 +#define DBG_PHYA_SCS_SHCR__SVCALLPENDED___M 0x00008000 +#define DBG_PHYA_SCS_SHCR__SVCALLPENDED___S 15 +#define DBG_PHYA_SCS_SHCR__BUSFAULTPENDED___M 0x00004000 +#define DBG_PHYA_SCS_SHCR__BUSFAULTPENDED___S 14 +#define DBG_PHYA_SCS_SHCR__MEMFAULTPENDED___M 0x00002000 +#define DBG_PHYA_SCS_SHCR__MEMFAULTPENDED___S 13 +#define DBG_PHYA_SCS_SHCR__USGFAULTPENDED___M 0x00001000 +#define DBG_PHYA_SCS_SHCR__USGFAULTPENDED___S 12 +#define DBG_PHYA_SCS_SHCR__SYSTICKACT___M 0x00000800 +#define DBG_PHYA_SCS_SHCR__SYSTICKACT___S 11 +#define DBG_PHYA_SCS_SHCR__PENDSVACT___M 0x00000400 +#define DBG_PHYA_SCS_SHCR__PENDSVACT___S 10 +#define DBG_PHYA_SCS_SHCR__MONITORACT___M 0x00000200 +#define DBG_PHYA_SCS_SHCR__MONITORACT___S 9 +#define DBG_PHYA_SCS_SHCR__SVCALLACT___M 0x00000080 +#define DBG_PHYA_SCS_SHCR__SVCALLACT___S 7 +#define DBG_PHYA_SCS_SHCR__USGFAULTACT___M 0x00000008 +#define DBG_PHYA_SCS_SHCR__USGFAULTACT___S 3 +#define DBG_PHYA_SCS_SHCR__BUSFAULTACT___M 0x00000002 +#define DBG_PHYA_SCS_SHCR__BUSFAULTACT___S 1 +#define DBG_PHYA_SCS_SHCR__MEMFAULTACT___M 0x00000001 +#define DBG_PHYA_SCS_SHCR__MEMFAULTACT___S 0 +#define DBG_PHYA_SCS_SHCR___M 0x0007FE8B +#define DBG_PHYA_SCS_SHCR___S 0 + +#define DBG_PHYA_SCS_CFSR (0x00BEBD28) +#define DBG_PHYA_SCS_CFSR___RWC QCSR_REG_RW +#define DBG_PHYA_SCS_CFSR___POR 0x00000000 +#define DBG_PHYA_SCS_CFSR__USAGEFAULT___POR 0x0000 +#define DBG_PHYA_SCS_CFSR__BUSFAULT___POR 0x00 +#define DBG_PHYA_SCS_CFSR__MEMMANAGE___POR 0x00 +#define DBG_PHYA_SCS_CFSR__USAGEFAULT___M 0xFFFF0000 +#define DBG_PHYA_SCS_CFSR__USAGEFAULT___S 16 +#define DBG_PHYA_SCS_CFSR__BUSFAULT___M 0x0000FF00 +#define DBG_PHYA_SCS_CFSR__BUSFAULT___S 8 +#define DBG_PHYA_SCS_CFSR__MEMMANAGE___M 0x000000FF +#define DBG_PHYA_SCS_CFSR__MEMMANAGE___S 0 +#define DBG_PHYA_SCS_CFSR___M 0xFFFFFFFF +#define DBG_PHYA_SCS_CFSR___S 0 + +#define DBG_PHYA_SCS_HFSR (0x00BEBD2C) +#define DBG_PHYA_SCS_HFSR___RWC QCSR_REG_RW +#define DBG_PHYA_SCS_HFSR___POR 0x00000000 +#define DBG_PHYA_SCS_HFSR__DEBUGEVT___POR 0x0 +#define DBG_PHYA_SCS_HFSR__FORCED___POR 0x0 +#define DBG_PHYA_SCS_HFSR__VECTTBL___POR 0x0 +#define DBG_PHYA_SCS_HFSR__DEBUGEVT___M 0x80000000 +#define DBG_PHYA_SCS_HFSR__DEBUGEVT___S 31 +#define DBG_PHYA_SCS_HFSR__FORCED___M 0x40000000 +#define DBG_PHYA_SCS_HFSR__FORCED___S 30 +#define DBG_PHYA_SCS_HFSR__VECTTBL___M 0x00000002 +#define DBG_PHYA_SCS_HFSR__VECTTBL___S 1 +#define DBG_PHYA_SCS_HFSR___M 0xC0000002 +#define DBG_PHYA_SCS_HFSR___S 1 + +#define DBG_PHYA_SCS_DFSR (0x00BEBD30) +#define DBG_PHYA_SCS_DFSR___RWC QCSR_REG_RW +#define DBG_PHYA_SCS_DFSR___POR 0x00000000 +#define DBG_PHYA_SCS_DFSR__EXTERNAL___POR 0x0 +#define DBG_PHYA_SCS_DFSR__VCATCH___POR 0x0 +#define DBG_PHYA_SCS_DFSR__DWTTRAP___POR 0x0 +#define DBG_PHYA_SCS_DFSR__BKPT___POR 0x0 +#define DBG_PHYA_SCS_DFSR__HALTED___POR 0x0 +#define DBG_PHYA_SCS_DFSR__EXTERNAL___M 0x00000010 +#define DBG_PHYA_SCS_DFSR__EXTERNAL___S 4 +#define DBG_PHYA_SCS_DFSR__VCATCH___M 0x00000008 +#define DBG_PHYA_SCS_DFSR__VCATCH___S 3 +#define DBG_PHYA_SCS_DFSR__DWTTRAP___M 0x00000004 +#define DBG_PHYA_SCS_DFSR__DWTTRAP___S 2 +#define DBG_PHYA_SCS_DFSR__BKPT___M 0x00000002 +#define DBG_PHYA_SCS_DFSR__BKPT___S 1 +#define DBG_PHYA_SCS_DFSR__HALTED___M 0x00000001 +#define DBG_PHYA_SCS_DFSR__HALTED___S 0 +#define DBG_PHYA_SCS_DFSR___M 0x0000001F +#define DBG_PHYA_SCS_DFSR___S 0 + +#define DBG_PHYA_SCS_MMFAR (0x00BEBD34) +#define DBG_PHYA_SCS_MMFAR___RWC QCSR_REG_RW +#define DBG_PHYA_SCS_MMFAR___POR 0x00000000 +#define DBG_PHYA_SCS_MMFAR__ADDRESS___POR 0x00000000 +#define DBG_PHYA_SCS_MMFAR__ADDRESS___M 0xFFFFFFFF +#define DBG_PHYA_SCS_MMFAR__ADDRESS___S 0 +#define DBG_PHYA_SCS_MMFAR___M 0xFFFFFFFF +#define DBG_PHYA_SCS_MMFAR___S 0 + +#define DBG_PHYA_SCS_BFAR (0x00BEBD38) +#define DBG_PHYA_SCS_BFAR___RWC QCSR_REG_RW +#define DBG_PHYA_SCS_BFAR___POR 0x00000000 +#define DBG_PHYA_SCS_BFAR__ADDRESS___POR 0x00000000 +#define DBG_PHYA_SCS_BFAR__ADDRESS___M 0xFFFFFFFF +#define DBG_PHYA_SCS_BFAR__ADDRESS___S 0 +#define DBG_PHYA_SCS_BFAR___M 0xFFFFFFFF +#define DBG_PHYA_SCS_BFAR___S 0 + +#define DBG_PHYA_SCS_AFSR (0x00BEBD3C) +#define DBG_PHYA_SCS_AFSR___RWC QCSR_REG_RW +#define DBG_PHYA_SCS_AFSR___POR 0x00000000 +#define DBG_PHYA_SCS_AFSR__AUXFAULT___POR 0x00000000 +#define DBG_PHYA_SCS_AFSR__AUXFAULT___M 0xFFFFFFFF +#define DBG_PHYA_SCS_AFSR__AUXFAULT___S 0 +#define DBG_PHYA_SCS_AFSR___M 0xFFFFFFFF +#define DBG_PHYA_SCS_AFSR___S 0 + +#define DBG_PHYA_SCS_ID_PFR0 (0x00BEBD40) +#define DBG_PHYA_SCS_ID_PFR0___RWC QCSR_REG_RO +#define DBG_PHYA_SCS_ID_PFR0___POR 0x00000030 +#define DBG_PHYA_SCS_ID_PFR0__STATE1___POR 0x3 +#define DBG_PHYA_SCS_ID_PFR0__STATE0___POR 0x0 +#define DBG_PHYA_SCS_ID_PFR0__STATE1___M 0x000000F0 +#define DBG_PHYA_SCS_ID_PFR0__STATE1___S 4 +#define DBG_PHYA_SCS_ID_PFR0__STATE1__THUMBSUPPORTED 0x3 +#define DBG_PHYA_SCS_ID_PFR0__STATE0___M 0x0000000F +#define DBG_PHYA_SCS_ID_PFR0__STATE0___S 0 +#define DBG_PHYA_SCS_ID_PFR0__STATE0__ARMINSTCTNSETNOTSUPPORTED 0x0 +#define DBG_PHYA_SCS_ID_PFR0___M 0x000000FF +#define DBG_PHYA_SCS_ID_PFR0___S 0 + +#define DBG_PHYA_SCS_ID_PFR1 (0x00BEBD44) +#define DBG_PHYA_SCS_ID_PFR1___RWC QCSR_REG_RO +#define DBG_PHYA_SCS_ID_PFR1___POR 0x00000200 +#define DBG_PHYA_SCS_ID_PFR1__MPROFILE___POR 0x2 +#define DBG_PHYA_SCS_ID_PFR1__MPROFILE___M 0x00000F00 +#define DBG_PHYA_SCS_ID_PFR1__MPROFILE___S 8 +#define DBG_PHYA_SCS_ID_PFR1__MPROFILE__TWOSTACKSUPPORTED 0x2 +#define DBG_PHYA_SCS_ID_PFR1___M 0x00000F00 +#define DBG_PHYA_SCS_ID_PFR1___S 8 + +#define DBG_PHYA_SCS_ID_DFR0 (0x00BEBD48) +#define DBG_PHYA_SCS_ID_DFR0___RWC QCSR_REG_RO +#define DBG_PHYA_SCS_ID_DFR0___POR 0x00100000 +#define DBG_PHYA_SCS_ID_DFR0__DEBUGMPROFILE___POR 0x1 +#define DBG_PHYA_SCS_ID_DFR0__DEBUGMPROFILE___M 0x00F00000 +#define DBG_PHYA_SCS_ID_DFR0__DEBUGMPROFILE___S 20 +#define DBG_PHYA_SCS_ID_DFR0__DEBUGMPROFILE__DEBUGSUPPORTED 0x1 +#define DBG_PHYA_SCS_ID_DFR0___M 0x00F00000 +#define DBG_PHYA_SCS_ID_DFR0___S 20 + +#define DBG_PHYA_SCS_AFR0 (0x00BEBD4C) +#define DBG_PHYA_SCS_AFR0___RWC QCSR_REG_RO +#define DBG_PHYA_SCS_AFR0___POR 0x00000000 +#define DBG_PHYA_SCS_AFR0__VALUE___POR 0x00000000 +#define DBG_PHYA_SCS_AFR0__VALUE___M 0xFFFFFFFF +#define DBG_PHYA_SCS_AFR0__VALUE___S 0 +#define DBG_PHYA_SCS_AFR0___M 0xFFFFFFFF +#define DBG_PHYA_SCS_AFR0___S 0 + +#define DBG_PHYA_SCS_MMFR0 (0x00BEBD50) +#define DBG_PHYA_SCS_MMFR0___RWC QCSR_REG_RO +#define DBG_PHYA_SCS_MMFR0___POR 0x00100030 +#define DBG_PHYA_SCS_MMFR0__AUXREGS___POR 0x1 +#define DBG_PHYA_SCS_MMFR0__TCMSUPPORT___POR 0x0 +#define DBG_PHYA_SCS_MMFR0__SHAREABILITY___POR 0x0 +#define DBG_PHYA_SCS_MMFR0__OUTERSHAREABILITY___POR 0x0 +#define DBG_PHYA_SCS_MMFR0__PMSA___POR 0x3 +#define DBG_PHYA_SCS_MMFR0__AUXREGS___M 0x00F00000 +#define DBG_PHYA_SCS_MMFR0__AUXREGS___S 20 +#define DBG_PHYA_SCS_MMFR0__AUXREGS__AUXCTRLONLY 0x1 +#define DBG_PHYA_SCS_MMFR0__TCMSUPPORT___M 0x000F0000 +#define DBG_PHYA_SCS_MMFR0__TCMSUPPORT___S 16 +#define DBG_PHYA_SCS_MMFR0__TCMSUPPORT__TCMNOTSUPPORTED 0x0 +#define DBG_PHYA_SCS_MMFR0__SHAREABILITY___M 0x0000F000 +#define DBG_PHYA_SCS_MMFR0__SHAREABILITY___S 12 +#define DBG_PHYA_SCS_MMFR0__SHAREABILITY__ONELEVEL 0x0 +#define DBG_PHYA_SCS_MMFR0__OUTERSHAREABILITY___M 0x00000F00 +#define DBG_PHYA_SCS_MMFR0__OUTERSHAREABILITY___S 8 +#define DBG_PHYA_SCS_MMFR0__OUTERSHAREABILITY__NONCACHEABLE 0x0 +#define DBG_PHYA_SCS_MMFR0__PMSA___M 0x000000F0 +#define DBG_PHYA_SCS_MMFR0__PMSA___S 4 +#define DBG_PHYA_SCS_MMFR0__PMSA__PMSAV7 0x3 +#define DBG_PHYA_SCS_MMFR0___M 0x00FFFFF0 +#define DBG_PHYA_SCS_MMFR0___S 4 + +#define DBG_PHYA_SCS_MMFR1 (0x00BEBD54) +#define DBG_PHYA_SCS_MMFR1___RWC QCSR_REG_RO +#define DBG_PHYA_SCS_MMFR1___POR 0x00000000 +#define DBG_PHYA_SCS_MMFR1__ARMV7MRESERVED___POR 0x00000000 +#define DBG_PHYA_SCS_MMFR1__ARMV7MRESERVED___M 0xFFFFFFFF +#define DBG_PHYA_SCS_MMFR1__ARMV7MRESERVED___S 0 +#define DBG_PHYA_SCS_MMFR1___M 0xFFFFFFFF +#define DBG_PHYA_SCS_MMFR1___S 0 + +#define DBG_PHYA_SCS_MMFR2 (0x00BEBD58) +#define DBG_PHYA_SCS_MMFR2___RWC QCSR_REG_RO +#define DBG_PHYA_SCS_MMFR2___POR 0x01000000 +#define DBG_PHYA_SCS_MMFR2__WFISTALL___POR 0x1 +#define DBG_PHYA_SCS_MMFR2__WFISTALL___M 0x0F000000 +#define DBG_PHYA_SCS_MMFR2__WFISTALL___S 24 +#define DBG_PHYA_SCS_MMFR2__WFISTALL__WFISTALLSUPPORTED 0x1 +#define DBG_PHYA_SCS_MMFR2___M 0x0F000000 +#define DBG_PHYA_SCS_MMFR2___S 24 + +#define DBG_PHYA_SCS_MMFR3 (0x00BEBD5C) +#define DBG_PHYA_SCS_MMFR3___RWC QCSR_REG_RO +#define DBG_PHYA_SCS_MMFR3___POR 0x00000000 +#define DBG_PHYA_SCS_MMFR3__ARMV7MRESERVED___POR 0x00000000 +#define DBG_PHYA_SCS_MMFR3__ARMV7MRESERVED___M 0xFFFFFFFF +#define DBG_PHYA_SCS_MMFR3__ARMV7MRESERVED___S 0 +#define DBG_PHYA_SCS_MMFR3___M 0xFFFFFFFF +#define DBG_PHYA_SCS_MMFR3___S 0 + +#define DBG_PHYA_SCS_ISAR0 (0x00BEBD60) +#define DBG_PHYA_SCS_ISAR0___RWC QCSR_REG_RO +#define DBG_PHYA_SCS_ISAR0___POR 0x01101110 +#define DBG_PHYA_SCS_ISAR0__FIXME___POR 0x01101110 +#define DBG_PHYA_SCS_ISAR0__FIXME___M 0xFFFFFFFF +#define DBG_PHYA_SCS_ISAR0__FIXME___S 0 +#define DBG_PHYA_SCS_ISAR0___M 0xFFFFFFFF +#define DBG_PHYA_SCS_ISAR0___S 0 + +#define DBG_PHYA_SCS_ISAR1 (0x00BEBD64) +#define DBG_PHYA_SCS_ISAR1___RWC QCSR_REG_RO +#define DBG_PHYA_SCS_ISAR1___POR 0x02111000 +#define DBG_PHYA_SCS_ISAR1__FIXME___POR 0x02111000 +#define DBG_PHYA_SCS_ISAR1__FIXME___M 0xFFFFFFFF +#define DBG_PHYA_SCS_ISAR1__FIXME___S 0 +#define DBG_PHYA_SCS_ISAR1___M 0xFFFFFFFF +#define DBG_PHYA_SCS_ISAR1___S 0 + +#define DBG_PHYA_SCS_ISAR2 (0x00BEBD68) +#define DBG_PHYA_SCS_ISAR2___RWC QCSR_REG_RO +#define DBG_PHYA_SCS_ISAR2___POR 0x21112231 +#define DBG_PHYA_SCS_ISAR2__FIXME___POR 0x21112231 +#define DBG_PHYA_SCS_ISAR2__FIXME___M 0xFFFFFFFF +#define DBG_PHYA_SCS_ISAR2__FIXME___S 0 +#define DBG_PHYA_SCS_ISAR2___M 0xFFFFFFFF +#define DBG_PHYA_SCS_ISAR2___S 0 + +#define DBG_PHYA_SCS_ISAR3 (0x00BEBD6C) +#define DBG_PHYA_SCS_ISAR3___RWC QCSR_REG_RO +#define DBG_PHYA_SCS_ISAR3___POR 0x01111110 +#define DBG_PHYA_SCS_ISAR3__FIXME___POR 0x01111110 +#define DBG_PHYA_SCS_ISAR3__FIXME___M 0xFFFFFFFF +#define DBG_PHYA_SCS_ISAR3__FIXME___S 0 +#define DBG_PHYA_SCS_ISAR3___M 0xFFFFFFFF +#define DBG_PHYA_SCS_ISAR3___S 0 + +#define DBG_PHYA_SCS_ISAR4 (0x00BEBD70) +#define DBG_PHYA_SCS_ISAR4___RWC QCSR_REG_RO +#define DBG_PHYA_SCS_ISAR4___POR 0x01310132 +#define DBG_PHYA_SCS_ISAR4__FIXME___POR 0x01310132 +#define DBG_PHYA_SCS_ISAR4__FIXME___M 0xFFFFFFFF +#define DBG_PHYA_SCS_ISAR4__FIXME___S 0 +#define DBG_PHYA_SCS_ISAR4___M 0xFFFFFFFF +#define DBG_PHYA_SCS_ISAR4___S 0 + +#define DBG_PHYA_SCS_CPACR (0x00BEBD88) +#define DBG_PHYA_SCS_CPACR___RWC QCSR_REG_RW +#define DBG_PHYA_SCS_CPACR___POR 0x00000000 +#define DBG_PHYA_SCS_CPACR__CP11___POR 0x0 +#define DBG_PHYA_SCS_CPACR__CP10___POR 0x0 +#define DBG_PHYA_SCS_CPACR__CP7___POR 0x0 +#define DBG_PHYA_SCS_CPACR__CP6___POR 0x0 +#define DBG_PHYA_SCS_CPACR__CP5___POR 0x0 +#define DBG_PHYA_SCS_CPACR__CP4___POR 0x0 +#define DBG_PHYA_SCS_CPACR__CP3___POR 0x0 +#define DBG_PHYA_SCS_CPACR__CP2___POR 0x0 +#define DBG_PHYA_SCS_CPACR__CP1___POR 0x0 +#define DBG_PHYA_SCS_CPACR__CP0___POR 0x0 +#define DBG_PHYA_SCS_CPACR__CP11___M 0x00C00000 +#define DBG_PHYA_SCS_CPACR__CP11___S 22 +#define DBG_PHYA_SCS_CPACR__CP11__NOACCESS 0x0 +#define DBG_PHYA_SCS_CPACR__CP11__PRIVILEGED 0x1 +#define DBG_PHYA_SCS_CPACR__CP11__FULL 0x2 +#define DBG_PHYA_SCS_CPACR__CP10___M 0x00300000 +#define DBG_PHYA_SCS_CPACR__CP10___S 20 +#define DBG_PHYA_SCS_CPACR__CP10__NOACCESS 0x0 +#define DBG_PHYA_SCS_CPACR__CP10__PRIVILEGED 0x1 +#define DBG_PHYA_SCS_CPACR__CP10__FULL 0x2 +#define DBG_PHYA_SCS_CPACR__CP7___M 0x0000C000 +#define DBG_PHYA_SCS_CPACR__CP7___S 14 +#define DBG_PHYA_SCS_CPACR__CP7__NOACCESS 0x0 +#define DBG_PHYA_SCS_CPACR__CP7__PRIVILEGED 0x1 +#define DBG_PHYA_SCS_CPACR__CP7__FULL 0x2 +#define DBG_PHYA_SCS_CPACR__CP6___M 0x00003000 +#define DBG_PHYA_SCS_CPACR__CP6___S 12 +#define DBG_PHYA_SCS_CPACR__CP6__NOACCESS 0x0 +#define DBG_PHYA_SCS_CPACR__CP6__PRIVILEGED 0x1 +#define DBG_PHYA_SCS_CPACR__CP6__FULL 0x2 +#define DBG_PHYA_SCS_CPACR__CP5___M 0x00000C00 +#define DBG_PHYA_SCS_CPACR__CP5___S 10 +#define DBG_PHYA_SCS_CPACR__CP5__NOACCESS 0x0 +#define DBG_PHYA_SCS_CPACR__CP5__PRIVILEGED 0x1 +#define DBG_PHYA_SCS_CPACR__CP5__FULL 0x2 +#define DBG_PHYA_SCS_CPACR__CP4___M 0x00000300 +#define DBG_PHYA_SCS_CPACR__CP4___S 8 +#define DBG_PHYA_SCS_CPACR__CP4__NOACCESS 0x0 +#define DBG_PHYA_SCS_CPACR__CP4__PRIVILEGED 0x1 +#define DBG_PHYA_SCS_CPACR__CP4__FULL 0x2 +#define DBG_PHYA_SCS_CPACR__CP3___M 0x000000C0 +#define DBG_PHYA_SCS_CPACR__CP3___S 6 +#define DBG_PHYA_SCS_CPACR__CP3__NOACCESS 0x0 +#define DBG_PHYA_SCS_CPACR__CP3__PRIVILEGED 0x1 +#define DBG_PHYA_SCS_CPACR__CP3__FULL 0x2 +#define DBG_PHYA_SCS_CPACR__CP2___M 0x00000030 +#define DBG_PHYA_SCS_CPACR__CP2___S 4 +#define DBG_PHYA_SCS_CPACR__CP2__NOACCESS 0x0 +#define DBG_PHYA_SCS_CPACR__CP2__PRIVILEGED 0x1 +#define DBG_PHYA_SCS_CPACR__CP2__FULL 0x2 +#define DBG_PHYA_SCS_CPACR__CP1___M 0x0000000C +#define DBG_PHYA_SCS_CPACR__CP1___S 2 +#define DBG_PHYA_SCS_CPACR__CP1__NOACCESS 0x0 +#define DBG_PHYA_SCS_CPACR__CP1__PRIVILEGED 0x1 +#define DBG_PHYA_SCS_CPACR__CP1__FULL 0x2 +#define DBG_PHYA_SCS_CPACR__CP0___M 0x00000003 +#define DBG_PHYA_SCS_CPACR__CP0___S 0 +#define DBG_PHYA_SCS_CPACR__CP0__NOACCESS 0x0 +#define DBG_PHYA_SCS_CPACR__CP0__PRIVILEGED 0x1 +#define DBG_PHYA_SCS_CPACR__CP0__FULL 0x2 +#define DBG_PHYA_SCS_CPACR___M 0x00F0FFFF +#define DBG_PHYA_SCS_CPACR___S 0 + +#define DBG_PHYA_SCS_DHCSR_WR (0x00BEBDF0) +#define DBG_PHYA_SCS_DHCSR_WR___RWC QCSR_REG_WO +#define DBG_PHYA_SCS_DHCSR_WR___POR 0x00000000 +#define DBG_PHYA_SCS_DHCSR_WR__DBGKEY___POR 0x0000 +#define DBG_PHYA_SCS_DHCSR_WR__C_SNAPSTALL___POR 0x0 +#define DBG_PHYA_SCS_DHCSR_WR__C_MASKINTS___POR 0x0 +#define DBG_PHYA_SCS_DHCSR_WR__C_STEP___POR 0x0 +#define DBG_PHYA_SCS_DHCSR_WR__C_HALT___POR 0x0 +#define DBG_PHYA_SCS_DHCSR_WR__C_DEBUGEN___POR 0x0 +#define DBG_PHYA_SCS_DHCSR_WR__DBGKEY___M 0xFFFF0000 +#define DBG_PHYA_SCS_DHCSR_WR__DBGKEY___S 16 +#define DBG_PHYA_SCS_DHCSR_WR__C_SNAPSTALL___M 0x00000020 +#define DBG_PHYA_SCS_DHCSR_WR__C_SNAPSTALL___S 5 +#define DBG_PHYA_SCS_DHCSR_WR__C_MASKINTS___M 0x00000008 +#define DBG_PHYA_SCS_DHCSR_WR__C_MASKINTS___S 3 +#define DBG_PHYA_SCS_DHCSR_WR__C_STEP___M 0x00000004 +#define DBG_PHYA_SCS_DHCSR_WR__C_STEP___S 2 +#define DBG_PHYA_SCS_DHCSR_WR__C_HALT___M 0x00000002 +#define DBG_PHYA_SCS_DHCSR_WR__C_HALT___S 1 +#define DBG_PHYA_SCS_DHCSR_WR__C_DEBUGEN___M 0x00000001 +#define DBG_PHYA_SCS_DHCSR_WR__C_DEBUGEN___S 0 +#define DBG_PHYA_SCS_DHCSR_WR___M 0xFFFF002F +#define DBG_PHYA_SCS_DHCSR_WR___S 0 + +#define DBG_PHYA_SCS_DHCSR_RD (0x00BEBDF0) +#define DBG_PHYA_SCS_DHCSR_RD___RWC QCSR_REG_RO +#define DBG_PHYA_SCS_DHCSR_RD___POR 0x02010000 +#define DBG_PHYA_SCS_DHCSR_RD__S_RESET_ST___POR 0x1 +#define DBG_PHYA_SCS_DHCSR_RD__S_RETIRE_ST___POR 0x0 +#define DBG_PHYA_SCS_DHCSR_RD__S_LOCKUP___POR 0x0 +#define DBG_PHYA_SCS_DHCSR_RD__S_SLEEP___POR 0x0 +#define DBG_PHYA_SCS_DHCSR_RD__S_HALT___POR 0x0 +#define DBG_PHYA_SCS_DHCSR_RD__S_REGRDY___POR 0x1 +#define DBG_PHYA_SCS_DHCSR_RD__C_SNAPSTALL___POR 0x0 +#define DBG_PHYA_SCS_DHCSR_RD__C_MASKINTS___POR 0x0 +#define DBG_PHYA_SCS_DHCSR_RD__C_STEP___POR 0x0 +#define DBG_PHYA_SCS_DHCSR_RD__C_HALT___POR 0x0 +#define DBG_PHYA_SCS_DHCSR_RD__C_DEBUGEN___POR 0x0 +#define DBG_PHYA_SCS_DHCSR_RD__S_RESET_ST___M 0x02000000 +#define DBG_PHYA_SCS_DHCSR_RD__S_RESET_ST___S 25 +#define DBG_PHYA_SCS_DHCSR_RD__S_RETIRE_ST___M 0x01000000 +#define DBG_PHYA_SCS_DHCSR_RD__S_RETIRE_ST___S 24 +#define DBG_PHYA_SCS_DHCSR_RD__S_LOCKUP___M 0x00080000 +#define DBG_PHYA_SCS_DHCSR_RD__S_LOCKUP___S 19 +#define DBG_PHYA_SCS_DHCSR_RD__S_SLEEP___M 0x00040000 +#define DBG_PHYA_SCS_DHCSR_RD__S_SLEEP___S 18 +#define DBG_PHYA_SCS_DHCSR_RD__S_HALT___M 0x00020000 +#define DBG_PHYA_SCS_DHCSR_RD__S_HALT___S 17 +#define DBG_PHYA_SCS_DHCSR_RD__S_REGRDY___M 0x00010000 +#define DBG_PHYA_SCS_DHCSR_RD__S_REGRDY___S 16 +#define DBG_PHYA_SCS_DHCSR_RD__C_SNAPSTALL___M 0x00000020 +#define DBG_PHYA_SCS_DHCSR_RD__C_SNAPSTALL___S 5 +#define DBG_PHYA_SCS_DHCSR_RD__C_MASKINTS___M 0x00000008 +#define DBG_PHYA_SCS_DHCSR_RD__C_MASKINTS___S 3 +#define DBG_PHYA_SCS_DHCSR_RD__C_STEP___M 0x00000004 +#define DBG_PHYA_SCS_DHCSR_RD__C_STEP___S 2 +#define DBG_PHYA_SCS_DHCSR_RD__C_HALT___M 0x00000002 +#define DBG_PHYA_SCS_DHCSR_RD__C_HALT___S 1 +#define DBG_PHYA_SCS_DHCSR_RD__C_DEBUGEN___M 0x00000001 +#define DBG_PHYA_SCS_DHCSR_RD__C_DEBUGEN___S 0 +#define DBG_PHYA_SCS_DHCSR_RD___M 0x030F002F +#define DBG_PHYA_SCS_DHCSR_RD___S 0 + +#define DBG_PHYA_SCS_DCRSR (0x00BEBDF4) +#define DBG_PHYA_SCS_DCRSR___RWC QCSR_REG_RW +#define DBG_PHYA_SCS_DCRSR___POR 0x00000000 +#define DBG_PHYA_SCS_DCRSR__REGWNR___POR 0x0 +#define DBG_PHYA_SCS_DCRSR__REGSEL___POR 0x00 +#define DBG_PHYA_SCS_DCRSR__REGWNR___M 0x00010000 +#define DBG_PHYA_SCS_DCRSR__REGWNR___S 16 +#define DBG_PHYA_SCS_DCRSR__REGWNR__READ 0x0 +#define DBG_PHYA_SCS_DCRSR__REGWNR__WRITE 0x1 +#define DBG_PHYA_SCS_DCRSR__REGSEL___M 0x0000007F +#define DBG_PHYA_SCS_DCRSR__REGSEL___S 0 +#define DBG_PHYA_SCS_DCRSR__REGSEL__R0 0x00 +#define DBG_PHYA_SCS_DCRSR__REGSEL__R1 0x01 +#define DBG_PHYA_SCS_DCRSR__REGSEL__R2 0x02 +#define DBG_PHYA_SCS_DCRSR__REGSEL__R3 0x03 +#define DBG_PHYA_SCS_DCRSR__REGSEL__R4 0x04 +#define DBG_PHYA_SCS_DCRSR__REGSEL__R5 0x05 +#define DBG_PHYA_SCS_DCRSR__REGSEL__R6 0x06 +#define DBG_PHYA_SCS_DCRSR__REGSEL__R7 0x07 +#define DBG_PHYA_SCS_DCRSR__REGSEL__R8 0x08 +#define DBG_PHYA_SCS_DCRSR__REGSEL__R9 0x09 +#define DBG_PHYA_SCS_DCRSR__REGSEL__R10 0x0A +#define DBG_PHYA_SCS_DCRSR__REGSEL__R11 0x0B +#define DBG_PHYA_SCS_DCRSR__REGSEL__R12 0x0C +#define DBG_PHYA_SCS_DCRSR__REGSEL__SP 0x0D +#define DBG_PHYA_SCS_DCRSR__REGSEL__LR 0x0E +#define DBG_PHYA_SCS_DCRSR__REGSEL__DBGRETADR 0x0F +#define DBG_PHYA_SCS_DCRSR__REGSEL__XPSR 0x10 +#define DBG_PHYA_SCS_DCRSR__REGSEL__MSP 0x11 +#define DBG_PHYA_SCS_DCRSR__REGSEL__PSP 0x12 +#define DBG_PHYA_SCS_DCRSR__REGSEL__MISC 0x14 +#define DBG_PHYA_SCS_DCRSR___M 0x0001007F +#define DBG_PHYA_SCS_DCRSR___S 0 + +#define DBG_PHYA_SCS_DCRDR (0x00BEBDF8) +#define DBG_PHYA_SCS_DCRDR___RWC QCSR_REG_RW +#define DBG_PHYA_SCS_DCRDR___POR 0x00000000 +#define DBG_PHYA_SCS_DCRDR__DBGTMP___POR 0x00000000 +#define DBG_PHYA_SCS_DCRDR__DBGTMP___M 0xFFFFFFFF +#define DBG_PHYA_SCS_DCRDR__DBGTMP___S 0 +#define DBG_PHYA_SCS_DCRDR___M 0xFFFFFFFF +#define DBG_PHYA_SCS_DCRDR___S 0 + +#define DBG_PHYA_SCS_DEMCR (0x00BEBDFC) +#define DBG_PHYA_SCS_DEMCR___RWC QCSR_REG_RW +#define DBG_PHYA_SCS_DEMCR___POR 0x00000000 +#define DBG_PHYA_SCS_DEMCR__TRCENA___POR 0x0 +#define DBG_PHYA_SCS_DEMCR__MON_REQ___POR 0x0 +#define DBG_PHYA_SCS_DEMCR__MON_STEP___POR 0x0 +#define DBG_PHYA_SCS_DEMCR__MON_PEND___POR 0x0 +#define DBG_PHYA_SCS_DEMCR__MON_EN___POR 0x0 +#define DBG_PHYA_SCS_DEMCR__VC_HARDERR___POR 0x0 +#define DBG_PHYA_SCS_DEMCR__VC_INTERR___POR 0x0 +#define DBG_PHYA_SCS_DEMCR__VC_BUSERR___POR 0x0 +#define DBG_PHYA_SCS_DEMCR__VC_STATERR___POR 0x0 +#define DBG_PHYA_SCS_DEMCR__VC_CHKERR___POR 0x0 +#define DBG_PHYA_SCS_DEMCR__VC_NOCPERR___POR 0x0 +#define DBG_PHYA_SCS_DEMCR__VC_MMERR___POR 0x0 +#define DBG_PHYA_SCS_DEMCR__VC_CORERESET___POR 0x0 +#define DBG_PHYA_SCS_DEMCR__TRCENA___M 0x01000000 +#define DBG_PHYA_SCS_DEMCR__TRCENA___S 24 +#define DBG_PHYA_SCS_DEMCR__TRCENA__DWT_ITM_DISABLED 0x0 +#define DBG_PHYA_SCS_DEMCR__TRCENA__DWT_ITM_ENABLED 0x1 +#define DBG_PHYA_SCS_DEMCR__MON_REQ___M 0x00080000 +#define DBG_PHYA_SCS_DEMCR__MON_REQ___S 19 +#define DBG_PHYA_SCS_DEMCR__MON_STEP___M 0x00040000 +#define DBG_PHYA_SCS_DEMCR__MON_STEP___S 18 +#define DBG_PHYA_SCS_DEMCR__MON_PEND___M 0x00020000 +#define DBG_PHYA_SCS_DEMCR__MON_PEND___S 17 +#define DBG_PHYA_SCS_DEMCR__MON_EN___M 0x00010000 +#define DBG_PHYA_SCS_DEMCR__MON_EN___S 16 +#define DBG_PHYA_SCS_DEMCR__VC_HARDERR___M 0x00000400 +#define DBG_PHYA_SCS_DEMCR__VC_HARDERR___S 10 +#define DBG_PHYA_SCS_DEMCR__VC_INTERR___M 0x00000200 +#define DBG_PHYA_SCS_DEMCR__VC_INTERR___S 9 +#define DBG_PHYA_SCS_DEMCR__VC_BUSERR___M 0x00000100 +#define DBG_PHYA_SCS_DEMCR__VC_BUSERR___S 8 +#define DBG_PHYA_SCS_DEMCR__VC_STATERR___M 0x00000080 +#define DBG_PHYA_SCS_DEMCR__VC_STATERR___S 7 +#define DBG_PHYA_SCS_DEMCR__VC_CHKERR___M 0x00000040 +#define DBG_PHYA_SCS_DEMCR__VC_CHKERR___S 6 +#define DBG_PHYA_SCS_DEMCR__VC_NOCPERR___M 0x00000020 +#define DBG_PHYA_SCS_DEMCR__VC_NOCPERR___S 5 +#define DBG_PHYA_SCS_DEMCR__VC_MMERR___M 0x00000010 +#define DBG_PHYA_SCS_DEMCR__VC_MMERR___S 4 +#define DBG_PHYA_SCS_DEMCR__VC_CORERESET___M 0x00000001 +#define DBG_PHYA_SCS_DEMCR__VC_CORERESET___S 0 +#define DBG_PHYA_SCS_DEMCR___M 0x010F07F1 +#define DBG_PHYA_SCS_DEMCR___S 0 + +#define DBG_PHYA_SCS_STIR (0x00BEBF00) +#define DBG_PHYA_SCS_STIR___RWC QCSR_REG_WO +#define DBG_PHYA_SCS_STIR___POR 0x00000000 +#define DBG_PHYA_SCS_STIR__INTID___POR 0x000 +#define DBG_PHYA_SCS_STIR__INTID___M 0x000001FF +#define DBG_PHYA_SCS_STIR__INTID___S 0 +#define DBG_PHYA_SCS_STIR___M 0x000001FF +#define DBG_PHYA_SCS_STIR___S 0 + +#define DBG_PHYA_SCS_PIDR4 (0x00BEBFD0) +#define DBG_PHYA_SCS_PIDR4___RWC QCSR_REG_RO +#define DBG_PHYA_SCS_PIDR4___POR 0x00000004 +#define DBG_PHYA_SCS_PIDR4__FIELD_4KB_COUNT___POR 0x0 +#define DBG_PHYA_SCS_PIDR4__JEP106_CONTINUATION___POR 0x4 +#define DBG_PHYA_SCS_PIDR4__FIELD_4KB_COUNT___M 0x000000F0 +#define DBG_PHYA_SCS_PIDR4__FIELD_4KB_COUNT___S 4 +#define DBG_PHYA_SCS_PIDR4__JEP106_CONTINUATION___M 0x0000000F +#define DBG_PHYA_SCS_PIDR4__JEP106_CONTINUATION___S 0 +#define DBG_PHYA_SCS_PIDR4___M 0x000000FF +#define DBG_PHYA_SCS_PIDR4___S 0 + +#define DBG_PHYA_SCS_PIDR0 (0x00BEBFE0) +#define DBG_PHYA_SCS_PIDR0___RWC QCSR_REG_RO +#define DBG_PHYA_SCS_PIDR0___POR 0x00000000 +#define DBG_PHYA_SCS_PIDR0__PARTNUM_7_0___POR 0x00 +#define DBG_PHYA_SCS_PIDR0__PARTNUM_7_0___M 0x000000FF +#define DBG_PHYA_SCS_PIDR0__PARTNUM_7_0___S 0 +#define DBG_PHYA_SCS_PIDR0___M 0x000000FF +#define DBG_PHYA_SCS_PIDR0___S 0 + +#define DBG_PHYA_SCS_PIDR1 (0x00BEBFE4) +#define DBG_PHYA_SCS_PIDR1___RWC QCSR_REG_RO +#define DBG_PHYA_SCS_PIDR1___POR 0x000000B0 +#define DBG_PHYA_SCS_PIDR1__JEP106_IDENTITY_3_0___POR 0xB +#define DBG_PHYA_SCS_PIDR1__PARTNUM_11_8___POR 0x0 +#define DBG_PHYA_SCS_PIDR1__JEP106_IDENTITY_3_0___M 0x000000F0 +#define DBG_PHYA_SCS_PIDR1__JEP106_IDENTITY_3_0___S 4 +#define DBG_PHYA_SCS_PIDR1__PARTNUM_11_8___M 0x0000000F +#define DBG_PHYA_SCS_PIDR1__PARTNUM_11_8___S 0 +#define DBG_PHYA_SCS_PIDR1___M 0x000000FF +#define DBG_PHYA_SCS_PIDR1___S 0 + +#define DBG_PHYA_SCS_PIDR2 (0x00BEBFE8) +#define DBG_PHYA_SCS_PIDR2___RWC QCSR_REG_RO +#define DBG_PHYA_SCS_PIDR2___POR 0x0000000B +#define DBG_PHYA_SCS_PIDR2__MAJREV___POR 0x0 +#define DBG_PHYA_SCS_PIDR2__JEDEC___POR 0x1 +#define DBG_PHYA_SCS_PIDR2__JEP106_IDENTITY_6_4___POR 0x3 +#define DBG_PHYA_SCS_PIDR2__MAJREV___M 0x000000F0 +#define DBG_PHYA_SCS_PIDR2__MAJREV___S 4 +#define DBG_PHYA_SCS_PIDR2__JEDEC___M 0x00000008 +#define DBG_PHYA_SCS_PIDR2__JEDEC___S 3 +#define DBG_PHYA_SCS_PIDR2__JEP106_IDENTITY_6_4___M 0x00000007 +#define DBG_PHYA_SCS_PIDR2__JEP106_IDENTITY_6_4___S 0 +#define DBG_PHYA_SCS_PIDR2___M 0x000000FF +#define DBG_PHYA_SCS_PIDR2___S 0 + +#define DBG_PHYA_SCS_PIDR3 (0x00BEBFEC) +#define DBG_PHYA_SCS_PIDR3___RWC QCSR_REG_RO +#define DBG_PHYA_SCS_PIDR3___POR 0x00000000 +#define DBG_PHYA_SCS_PIDR3__REV_AND___POR 0x0 +#define DBG_PHYA_SCS_PIDR3__CUSTOMER_MODIFIED___POR 0x0 +#define DBG_PHYA_SCS_PIDR3__REV_AND___M 0x000000F0 +#define DBG_PHYA_SCS_PIDR3__REV_AND___S 4 +#define DBG_PHYA_SCS_PIDR3__CUSTOMER_MODIFIED___M 0x0000000F +#define DBG_PHYA_SCS_PIDR3__CUSTOMER_MODIFIED___S 0 +#define DBG_PHYA_SCS_PIDR3___M 0x000000FF +#define DBG_PHYA_SCS_PIDR3___S 0 + +#define DBG_PHYA_SCS_CIDR0 (0x00BEBFF0) +#define DBG_PHYA_SCS_CIDR0___RWC QCSR_REG_RO +#define DBG_PHYA_SCS_CIDR0___POR 0x0000000D +#define DBG_PHYA_SCS_CIDR0__PREAMBLE_7_0___POR 0x0D +#define DBG_PHYA_SCS_CIDR0__PREAMBLE_7_0___M 0x000000FF +#define DBG_PHYA_SCS_CIDR0__PREAMBLE_7_0___S 0 +#define DBG_PHYA_SCS_CIDR0___M 0x000000FF +#define DBG_PHYA_SCS_CIDR0___S 0 + +#define DBG_PHYA_SCS_CIDR1 (0x00BEBFF4) +#define DBG_PHYA_SCS_CIDR1___RWC QCSR_REG_RO +#define DBG_PHYA_SCS_CIDR1___POR 0x000000E0 +#define DBG_PHYA_SCS_CIDR1__PREAMBLE_15_12___POR 0xE +#define DBG_PHYA_SCS_CIDR1__PREAMBLE_11_8___POR 0x0 +#define DBG_PHYA_SCS_CIDR1__PREAMBLE_15_12___M 0x000000F0 +#define DBG_PHYA_SCS_CIDR1__PREAMBLE_15_12___S 4 +#define DBG_PHYA_SCS_CIDR1__PREAMBLE_11_8___M 0x0000000F +#define DBG_PHYA_SCS_CIDR1__PREAMBLE_11_8___S 0 +#define DBG_PHYA_SCS_CIDR1___M 0x000000FF +#define DBG_PHYA_SCS_CIDR1___S 0 + +#define DBG_PHYA_SCS_CIDR2 (0x00BEBFF8) +#define DBG_PHYA_SCS_CIDR2___RWC QCSR_REG_RO +#define DBG_PHYA_SCS_CIDR2___POR 0x00000005 +#define DBG_PHYA_SCS_CIDR2__PREAMBLE_23_16___POR 0x05 +#define DBG_PHYA_SCS_CIDR2__PREAMBLE_23_16___M 0x000000FF +#define DBG_PHYA_SCS_CIDR2__PREAMBLE_23_16___S 0 +#define DBG_PHYA_SCS_CIDR2___M 0x000000FF +#define DBG_PHYA_SCS_CIDR2___S 0 + +#define DBG_PHYA_SCS_CIDR3 (0x00BEBFFC) +#define DBG_PHYA_SCS_CIDR3___RWC QCSR_REG_RO +#define DBG_PHYA_SCS_CIDR3___POR 0x000000B1 +#define DBG_PHYA_SCS_CIDR3__PREAMBLE_31_24___POR 0xB1 +#define DBG_PHYA_SCS_CIDR3__PREAMBLE_31_24___M 0x000000FF +#define DBG_PHYA_SCS_CIDR3__PREAMBLE_31_24___S 0 +#define DBG_PHYA_SCS_CIDR3___M 0x000000FF +#define DBG_PHYA_SCS_CIDR3___S 0 + +#define DBG_PHYA_ETMCR (0x00BEC000) +#define DBG_PHYA_ETMCR___RWC QCSR_REG_RW +#define DBG_PHYA_ETMCR___POR 0x00000411 +#define DBG_PHYA_ETMCR__TSTMPEN___POR 0x0 +#define DBG_PHYA_ETMCR__ETMENOUTCTRL___POR 0x0 +#define DBG_PHYA_ETMCR__ETMPROGMODEEN___POR 0x1 +#define DBG_PHYA_ETMCR__DBGREQCTRL___POR 0x0 +#define DBG_PHYA_ETMCR__ALLBROUT___POR 0x0 +#define DBG_PHYA_ETMCR__STALLCPU___POR 0x0 +#define DBG_PHYA_ETMCR__PORTSZ___POR 0x1 +#define DBG_PHYA_ETMCR__ETMPWRDWN___POR 0x1 +#define DBG_PHYA_ETMCR__TSTMPEN___M 0x10000000 +#define DBG_PHYA_ETMCR__TSTMPEN___S 28 +#define DBG_PHYA_ETMCR__TSTMPEN__TSTMPOFF 0x0 +#define DBG_PHYA_ETMCR__TSTMPEN__TSTMPON 0x1 +#define DBG_PHYA_ETMCR__ETMENOUTCTRL___M 0x00000800 +#define DBG_PHYA_ETMCR__ETMENOUTCTRL___S 11 +#define DBG_PHYA_ETMCR__ETMENOUTCTRL__ETMENOUTLO 0x0 +#define DBG_PHYA_ETMCR__ETMENOUTCTRL__ETMENOUTHI 0x1 +#define DBG_PHYA_ETMCR__ETMPROGMODEEN___M 0x00000400 +#define DBG_PHYA_ETMCR__ETMPROGMODEEN___S 10 +#define DBG_PHYA_ETMCR__ETMPROGMODEEN__PROGOFFTRACEON 0x0 +#define DBG_PHYA_ETMCR__ETMPROGMODEEN__PROGONTRACEOFF 0x1 +#define DBG_PHYA_ETMCR__DBGREQCTRL___M 0x00000200 +#define DBG_PHYA_ETMCR__DBGREQCTRL___S 9 +#define DBG_PHYA_ETMCR__DBGREQCTRL__DBGREQOUTOFF 0x0 +#define DBG_PHYA_ETMCR__DBGREQCTRL__DBGREQOUTON 0x1 +#define DBG_PHYA_ETMCR__ALLBROUT___M 0x00000100 +#define DBG_PHYA_ETMCR__ALLBROUT___S 8 +#define DBG_PHYA_ETMCR__ALLBROUT__CONDTKNBRONLY 0x0 +#define DBG_PHYA_ETMCR__ALLBROUT__ALLBREN 0x1 +#define DBG_PHYA_ETMCR__STALLCPU___M 0x00000080 +#define DBG_PHYA_ETMCR__STALLCPU___S 7 +#define DBG_PHYA_ETMCR__STALLCPU__STALLOFF 0x0 +#define DBG_PHYA_ETMCR__STALLCPU__STALLON 0x1 +#define DBG_PHYA_ETMCR__PORTSZ___M 0x00000070 +#define DBG_PHYA_ETMCR__PORTSZ___S 4 +#define DBG_PHYA_ETMCR__PORTSZ__DEFAULT 0x1 +#define DBG_PHYA_ETMCR__ETMPWRDWN___M 0x00000001 +#define DBG_PHYA_ETMCR__ETMPWRDWN___S 0 +#define DBG_PHYA_ETMCR__ETMPWRDWN__PWRUP 0x0 +#define DBG_PHYA_ETMCR__ETMPWRDWN__PWRDWN 0x1 +#define DBG_PHYA_ETMCR___M 0x10000FF1 +#define DBG_PHYA_ETMCR___S 0 + +#define DBG_PHYA_ETMCCR (0x00BEC004) +#define DBG_PHYA_ETMCCR___RWC QCSR_REG_RO +#define DBG_PHYA_ETMCCR___POR 0x8C802000 +#define DBG_PHYA_ETMCCR__ETMIDREGPRESENT___POR 0x1 +#define DBG_PHYA_ETMCCR__MEMACCESS___POR 0x1 +#define DBG_PHYA_ETMCCR__STARTSTOPPRESENT___POR 0x1 +#define DBG_PHYA_ETMCCR__NUMCONTEXTIDCOMP___POR 0x0 +#define DBG_PHYA_ETMCCR__FIFOFULLPRESENT___POR 0x1 +#define DBG_PHYA_ETMCCR__NUMEXTOUTPUTS___POR 0x0 +#define DBG_PHYA_ETMCCR__NUMEXTINPUTS___POR 0x0 +#define DBG_PHYA_ETMCCR__SEQPRESENT___POR 0x0 +#define DBG_PHYA_ETMCCR__NUMCNTRS___POR 0x1 +#define DBG_PHYA_ETMCCR__NUMMEMMAPDEC___POR 0x00 +#define DBG_PHYA_ETMCCR__NUMDATACOMP___POR 0x0 +#define DBG_PHYA_ETMCCR__NUMADDRCOMPPAIR___POR 0x0 +#define DBG_PHYA_ETMCCR__ETMIDREGPRESENT___M 0x80000000 +#define DBG_PHYA_ETMCCR__ETMIDREGPRESENT___S 31 +#define DBG_PHYA_ETMCCR__ETMIDREGPRESENT__PRESENT 0x1 +#define DBG_PHYA_ETMCCR__MEMACCESS___M 0x08000000 +#define DBG_PHYA_ETMCCR__MEMACCESS___S 27 +#define DBG_PHYA_ETMCCR__MEMACCESS__SUPPORTED 0x1 +#define DBG_PHYA_ETMCCR__STARTSTOPPRESENT___M 0x04000000 +#define DBG_PHYA_ETMCCR__STARTSTOPPRESENT___S 26 +#define DBG_PHYA_ETMCCR__STARTSTOPPRESENT__PRESENT 0x1 +#define DBG_PHYA_ETMCCR__NUMCONTEXTIDCOMP___M 0x03000000 +#define DBG_PHYA_ETMCCR__NUMCONTEXTIDCOMP___S 24 +#define DBG_PHYA_ETMCCR__NUMCONTEXTIDCOMP__NOTIMPLEMENTED 0x0 +#define DBG_PHYA_ETMCCR__FIFOFULLPRESENT___M 0x00800000 +#define DBG_PHYA_ETMCCR__FIFOFULLPRESENT___S 23 +#define DBG_PHYA_ETMCCR__FIFOFULLPRESENT__FIFOFULLPRESENT 0x1 +#define DBG_PHYA_ETMCCR__NUMEXTOUTPUTS___M 0x00700000 +#define DBG_PHYA_ETMCCR__NUMEXTOUTPUTS___S 20 +#define DBG_PHYA_ETMCCR__NUMEXTOUTPUTS__NOTIMPLEMENTED 0x0 +#define DBG_PHYA_ETMCCR__NUMEXTINPUTS___M 0x000E0000 +#define DBG_PHYA_ETMCCR__NUMEXTINPUTS___S 17 +#define DBG_PHYA_ETMCCR__SEQPRESENT___M 0x00010000 +#define DBG_PHYA_ETMCCR__SEQPRESENT___S 16 +#define DBG_PHYA_ETMCCR__SEQPRESENT__NOTIMPLEMENTED 0x0 +#define DBG_PHYA_ETMCCR__NUMCNTRS___M 0x0000E000 +#define DBG_PHYA_ETMCCR__NUMCNTRS___S 13 +#define DBG_PHYA_ETMCCR__NUMMEMMAPDEC___M 0x00001F00 +#define DBG_PHYA_ETMCCR__NUMMEMMAPDEC___S 8 +#define DBG_PHYA_ETMCCR__NUMMEMMAPDEC__NOTIMPLEMENTED 0x00 +#define DBG_PHYA_ETMCCR__NUMDATACOMP___M 0x000000F0 +#define DBG_PHYA_ETMCCR__NUMDATACOMP___S 4 +#define DBG_PHYA_ETMCCR__NUMDATACOMP__NOTIMPLEMENTED 0x0 +#define DBG_PHYA_ETMCCR__NUMADDRCOMPPAIR___M 0x0000000F +#define DBG_PHYA_ETMCCR__NUMADDRCOMPPAIR___S 0 +#define DBG_PHYA_ETMCCR__NUMADDRCOMPPAIR__NOTIMPLEMENTED 0x0 +#define DBG_PHYA_ETMCCR___M 0x8FFFFFFF +#define DBG_PHYA_ETMCCR___S 0 + +#define DBG_PHYA_ETMTRIGGER (0x00BEC008) +#define DBG_PHYA_ETMTRIGGER___RWC QCSR_REG_RW +#define DBG_PHYA_ETMTRIGGER___POR 0x00000000 +#define DBG_PHYA_ETMTRIGGER__FUNCTION___POR 0x0 +#define DBG_PHYA_ETMTRIGGER__RESOURCEBTYPE___POR 0x0 +#define DBG_PHYA_ETMTRIGGER__RESOURCEBINDEX___POR 0x0 +#define DBG_PHYA_ETMTRIGGER__RESOURCEATYPE___POR 0x0 +#define DBG_PHYA_ETMTRIGGER__RESOURCEAINDEX___POR 0x0 +#define DBG_PHYA_ETMTRIGGER__FUNCTION___M 0x0001C000 +#define DBG_PHYA_ETMTRIGGER__FUNCTION___S 14 +#define DBG_PHYA_ETMTRIGGER__FUNCTION__A 0x0 +#define DBG_PHYA_ETMTRIGGER__FUNCTION__NOTA 0x1 +#define DBG_PHYA_ETMTRIGGER__FUNCTION__A_AND_B 0x2 +#define DBG_PHYA_ETMTRIGGER__FUNCTION__NOTA_AND_B 0x3 +#define DBG_PHYA_ETMTRIGGER__FUNCTION__NOTA_AND_NOTB 0x4 +#define DBG_PHYA_ETMTRIGGER__FUNCTION__A_OR_B 0x5 +#define DBG_PHYA_ETMTRIGGER__FUNCTION__NOTA_OR_B 0x6 +#define DBG_PHYA_ETMTRIGGER__FUNCTION__NOTA_OR_NOTB 0x7 +#define DBG_PHYA_ETMTRIGGER__RESOURCEBTYPE___M 0x00003800 +#define DBG_PHYA_ETMTRIGGER__RESOURCEBTYPE___S 11 +#define DBG_PHYA_ETMTRIGGER__RESOURCEBTYPE__ILLEGAL 0x0 +#define DBG_PHYA_ETMTRIGGER__RESOURCEBTYPE__DWTCOMPINP 0x2 +#define DBG_PHYA_ETMTRIGGER__RESOURCEBTYPE__CNTRZERO 0x4 +#define DBG_PHYA_ETMTRIGGER__RESOURCEBTYPE__MISC1 0x5 +#define DBG_PHYA_ETMTRIGGER__RESOURCEBTYPE__MISC2 0x6 +#define DBG_PHYA_ETMTRIGGER__RESOURCEBINDEX___M 0x00000780 +#define DBG_PHYA_ETMTRIGGER__RESOURCEBINDEX___S 7 +#define DBG_PHYA_ETMTRIGGER__RESOURCEBINDEX__DWTCOMP1 0x0 +#define DBG_PHYA_ETMTRIGGER__RESOURCEBINDEX__DWTCOMP2 0x1 +#define DBG_PHYA_ETMTRIGGER__RESOURCEBINDEX__DWTCOMP3 0x2 +#define DBG_PHYA_ETMTRIGGER__RESOURCEBINDEX__DWTCOMP4 0x3 +#define DBG_PHYA_ETMTRIGGER__RESOURCEBINDEX__CNTR1ATZERO 0x0 +#define DBG_PHYA_ETMTRIGGER__RESOURCEBINDEX__TRCSTARTSTOPRES 0xF +#define DBG_PHYA_ETMTRIGGER__RESOURCEBINDEX__EXTINP1 0x0 +#define DBG_PHYA_ETMTRIGGER__RESOURCEBINDEX__EXTINP2 0x1 +#define DBG_PHYA_ETMTRIGGER__RESOURCEBINDEX__ALWAYSTRUE 0xF +#define DBG_PHYA_ETMTRIGGER__RESOURCEATYPE___M 0x00000070 +#define DBG_PHYA_ETMTRIGGER__RESOURCEATYPE___S 4 +#define DBG_PHYA_ETMTRIGGER__RESOURCEATYPE__ILLEGAL 0x0 +#define DBG_PHYA_ETMTRIGGER__RESOURCEATYPE__DWTCOMPINP 0x2 +#define DBG_PHYA_ETMTRIGGER__RESOURCEATYPE__CNTRZERO 0x4 +#define DBG_PHYA_ETMTRIGGER__RESOURCEATYPE__MISC1 0x5 +#define DBG_PHYA_ETMTRIGGER__RESOURCEATYPE__MISC2 0x6 +#define DBG_PHYA_ETMTRIGGER__RESOURCEAINDEX___M 0x0000000F +#define DBG_PHYA_ETMTRIGGER__RESOURCEAINDEX___S 0 +#define DBG_PHYA_ETMTRIGGER__RESOURCEAINDEX__DWTCOMP1 0x0 +#define DBG_PHYA_ETMTRIGGER__RESOURCEAINDEX__DWTCOMP2 0x1 +#define DBG_PHYA_ETMTRIGGER__RESOURCEAINDEX__DWTCOMP3 0x2 +#define DBG_PHYA_ETMTRIGGER__RESOURCEAINDEX__DWTCOMP4 0x3 +#define DBG_PHYA_ETMTRIGGER__RESOURCEAINDEX__CNTR1ATZERO 0x0 +#define DBG_PHYA_ETMTRIGGER__RESOURCEAINDEX__TRCSTARTSTOPRES 0xF +#define DBG_PHYA_ETMTRIGGER__RESOURCEAINDEX__EXTINP1 0x0 +#define DBG_PHYA_ETMTRIGGER__RESOURCEAINDEX__EXTINP2 0x1 +#define DBG_PHYA_ETMTRIGGER__RESOURCEAINDEX__ALWAYSTRUE 0xF +#define DBG_PHYA_ETMTRIGGER___M 0x0001FFFF +#define DBG_PHYA_ETMTRIGGER___S 0 + +#define DBG_PHYA_ETMSR (0x00BEC010) +#define DBG_PHYA_ETMSR___RWC QCSR_REG_RW +#define DBG_PHYA_ETMSR___POR 0x00000002 +#define DBG_PHYA_ETMSR__TRIGGER___POR 0x0 +#define DBG_PHYA_ETMSR__TRCSTARTSTOPRESSTATUS___POR 0x0 +#define DBG_PHYA_ETMSR__PROGBITSTATUS___POR 0x1 +#define DBG_PHYA_ETMSR__OVFLOW___POR 0x0 +#define DBG_PHYA_ETMSR__TRIGGER___M 0x00000008 +#define DBG_PHYA_ETMSR__TRIGGER___S 3 +#define DBG_PHYA_ETMSR__TRCSTARTSTOPRESSTATUS___M 0x00000004 +#define DBG_PHYA_ETMSR__TRCSTARTSTOPRESSTATUS___S 2 +#define DBG_PHYA_ETMSR__PROGBITSTATUS___M 0x00000002 +#define DBG_PHYA_ETMSR__PROGBITSTATUS___S 1 +#define DBG_PHYA_ETMSR__OVFLOW___M 0x00000001 +#define DBG_PHYA_ETMSR__OVFLOW___S 0 +#define DBG_PHYA_ETMSR___M 0x0000000F +#define DBG_PHYA_ETMSR___S 0 + +#define DBG_PHYA_ETMSCR (0x00BEC014) +#define DBG_PHYA_ETMSCR___RWC QCSR_REG_RO +#define DBG_PHYA_ETMSCR___POR 0x00020D09 +#define DBG_PHYA_ETMSCR__NOFETCHCOMPARISONS___POR 0x1 +#define DBG_PHYA_ETMSCR__NUMCPUSUPPORTED___POR 0x0 +#define DBG_PHYA_ETMSCR__PORTMODESUPPORT___POR 0x1 +#define DBG_PHYA_ETMSCR__PORTSZSUPPORT___POR 0x1 +#define DBG_PHYA_ETMSCR__MAXPORTSZ_3___POR 0x0 +#define DBG_PHYA_ETMSCR__FIFOFULLSUPPORT___POR 0x1 +#define DBG_PHYA_ETMSCR__RSVD___POR 0x1 +#define DBG_PHYA_ETMSCR__MAXPORTSZ_2_0___POR 0x1 +#define DBG_PHYA_ETMSCR__NOFETCHCOMPARISONS___M 0x00020000 +#define DBG_PHYA_ETMSCR__NOFETCHCOMPARISONS___S 17 +#define DBG_PHYA_ETMSCR__NOFETCHCOMPARISONS__FETCHCOMPNOTIMPLEMENTED 0x1 +#define DBG_PHYA_ETMSCR__NUMCPUSUPPORTED___M 0x00007000 +#define DBG_PHYA_ETMSCR__NUMCPUSUPPORTED___S 12 +#define DBG_PHYA_ETMSCR__NUMCPUSUPPORTED__ONECPU 0x0 +#define DBG_PHYA_ETMSCR__PORTMODESUPPORT___M 0x00000800 +#define DBG_PHYA_ETMSCR__PORTMODESUPPORT___S 11 +#define DBG_PHYA_ETMSCR__PORTMODESUPPORT__SUPPORTED 0x1 +#define DBG_PHYA_ETMSCR__PORTSZSUPPORT___M 0x00000400 +#define DBG_PHYA_ETMSCR__PORTSZSUPPORT___S 10 +#define DBG_PHYA_ETMSCR__PORTSZSUPPORT__SUPPORTED 0x1 +#define DBG_PHYA_ETMSCR__MAXPORTSZ_3___M 0x00000200 +#define DBG_PHYA_ETMSCR__MAXPORTSZ_3___S 9 +#define DBG_PHYA_ETMSCR__FIFOFULLSUPPORT___M 0x00000100 +#define DBG_PHYA_ETMSCR__FIFOFULLSUPPORT___S 8 +#define DBG_PHYA_ETMSCR__FIFOFULLSUPPORT__SUPPORTED 0x1 +#define DBG_PHYA_ETMSCR__RSVD___M 0x00000008 +#define DBG_PHYA_ETMSCR__RSVD___S 3 +#define DBG_PHYA_ETMSCR__MAXPORTSZ_2_0___M 0x00000007 +#define DBG_PHYA_ETMSCR__MAXPORTSZ_2_0___S 0 +#define DBG_PHYA_ETMSCR___M 0x00027F0F +#define DBG_PHYA_ETMSCR___S 0 + +#define DBG_PHYA_ETMTEEVR (0x00BEC020) +#define DBG_PHYA_ETMTEEVR___RWC QCSR_REG_RW +#define DBG_PHYA_ETMTEEVR___POR 0x00000000 +#define DBG_PHYA_ETMTEEVR__FUNCTION___POR 0x0 +#define DBG_PHYA_ETMTEEVR__RESOURCEBTYPE___POR 0x0 +#define DBG_PHYA_ETMTEEVR__RESOURCEBINDEX___POR 0x0 +#define DBG_PHYA_ETMTEEVR__RESOURCEATYPE___POR 0x0 +#define DBG_PHYA_ETMTEEVR__RESOURCEAINDEX___POR 0x0 +#define DBG_PHYA_ETMTEEVR__FUNCTION___M 0x0001C000 +#define DBG_PHYA_ETMTEEVR__FUNCTION___S 14 +#define DBG_PHYA_ETMTEEVR__FUNCTION__A 0x0 +#define DBG_PHYA_ETMTEEVR__FUNCTION__NOTA 0x1 +#define DBG_PHYA_ETMTEEVR__FUNCTION__A_AND_B 0x2 +#define DBG_PHYA_ETMTEEVR__FUNCTION__NOTA_AND_B 0x3 +#define DBG_PHYA_ETMTEEVR__FUNCTION__NOTA_AND_NOTB 0x4 +#define DBG_PHYA_ETMTEEVR__FUNCTION__A_OR_B 0x5 +#define DBG_PHYA_ETMTEEVR__FUNCTION__NOTA_OR_B 0x6 +#define DBG_PHYA_ETMTEEVR__FUNCTION__NOTA_OR_NOTB 0x7 +#define DBG_PHYA_ETMTEEVR__RESOURCEBTYPE___M 0x00003800 +#define DBG_PHYA_ETMTEEVR__RESOURCEBTYPE___S 11 +#define DBG_PHYA_ETMTEEVR__RESOURCEBTYPE__ILLEGAL 0x0 +#define DBG_PHYA_ETMTEEVR__RESOURCEBTYPE__DWTCOMPINP 0x2 +#define DBG_PHYA_ETMTEEVR__RESOURCEBTYPE__CNTRZERO 0x4 +#define DBG_PHYA_ETMTEEVR__RESOURCEBTYPE__MISC1 0x5 +#define DBG_PHYA_ETMTEEVR__RESOURCEBTYPE__MISC2 0x6 +#define DBG_PHYA_ETMTEEVR__RESOURCEBINDEX___M 0x00000780 +#define DBG_PHYA_ETMTEEVR__RESOURCEBINDEX___S 7 +#define DBG_PHYA_ETMTEEVR__RESOURCEBINDEX__DWTCOMP1 0x0 +#define DBG_PHYA_ETMTEEVR__RESOURCEBINDEX__DWTCOMP2 0x1 +#define DBG_PHYA_ETMTEEVR__RESOURCEBINDEX__DWTCOMP3 0x2 +#define DBG_PHYA_ETMTEEVR__RESOURCEBINDEX__DWTCOMP4 0x3 +#define DBG_PHYA_ETMTEEVR__RESOURCEBINDEX__CNTR1ATZERO 0x0 +#define DBG_PHYA_ETMTEEVR__RESOURCEBINDEX__TRCSTARTSTOPRES 0xF +#define DBG_PHYA_ETMTEEVR__RESOURCEBINDEX__EXTINP1 0x0 +#define DBG_PHYA_ETMTEEVR__RESOURCEBINDEX__EXTINP2 0x1 +#define DBG_PHYA_ETMTEEVR__RESOURCEBINDEX__ALWAYSTRUE 0xF +#define DBG_PHYA_ETMTEEVR__RESOURCEATYPE___M 0x00000070 +#define DBG_PHYA_ETMTEEVR__RESOURCEATYPE___S 4 +#define DBG_PHYA_ETMTEEVR__RESOURCEATYPE__ILLEGAL 0x0 +#define DBG_PHYA_ETMTEEVR__RESOURCEATYPE__DWTCOMPINP 0x2 +#define DBG_PHYA_ETMTEEVR__RESOURCEATYPE__CNTRZERO 0x4 +#define DBG_PHYA_ETMTEEVR__RESOURCEATYPE__MISC1 0x5 +#define DBG_PHYA_ETMTEEVR__RESOURCEATYPE__MISC2 0x6 +#define DBG_PHYA_ETMTEEVR__RESOURCEAINDEX___M 0x0000000F +#define DBG_PHYA_ETMTEEVR__RESOURCEAINDEX___S 0 +#define DBG_PHYA_ETMTEEVR__RESOURCEAINDEX__DWTCOMP1 0x0 +#define DBG_PHYA_ETMTEEVR__RESOURCEAINDEX__DWTCOMP2 0x1 +#define DBG_PHYA_ETMTEEVR__RESOURCEAINDEX__DWTCOMP3 0x2 +#define DBG_PHYA_ETMTEEVR__RESOURCEAINDEX__DWTCOMP4 0x3 +#define DBG_PHYA_ETMTEEVR__RESOURCEAINDEX__CNTR1ATZERO 0x0 +#define DBG_PHYA_ETMTEEVR__RESOURCEAINDEX__TRCSTARTSTOPRES 0xF +#define DBG_PHYA_ETMTEEVR__RESOURCEAINDEX__EXTINP1 0x0 +#define DBG_PHYA_ETMTEEVR__RESOURCEAINDEX__EXTINP2 0x1 +#define DBG_PHYA_ETMTEEVR__RESOURCEAINDEX__ALWAYSTRUE 0xF +#define DBG_PHYA_ETMTEEVR___M 0x0001FFFF +#define DBG_PHYA_ETMTEEVR___S 0 + +#define DBG_PHYA_ETMTECR1 (0x00BEC024) +#define DBG_PHYA_ETMTECR1___RWC QCSR_REG_RW +#define DBG_PHYA_ETMTECR1___POR 0x00000000 +#define DBG_PHYA_ETMTECR1__TRACECTRLEN___POR 0x0 +#define DBG_PHYA_ETMTECR1__TRACECTRLEN___M 0x02000000 +#define DBG_PHYA_ETMTECR1__TRACECTRLEN___S 25 +#define DBG_PHYA_ETMTECR1__TRACECTRLEN__TRCSTARTSTOPOFF 0x0 +#define DBG_PHYA_ETMTECR1__TRACECTRLEN__TRCSTARSTOPON 0x1 +#define DBG_PHYA_ETMTECR1___M 0x02000000 +#define DBG_PHYA_ETMTECR1___S 25 + +#define DBG_PHYA_ETMFFLR (0x00BEC02C) +#define DBG_PHYA_ETMFFLR___RWC QCSR_REG_RW +#define DBG_PHYA_ETMFFLR___POR 0x00000000 +#define DBG_PHYA_ETMFFLR__NUMBYTESFREE___POR 0x00 +#define DBG_PHYA_ETMFFLR__NUMBYTESFREE___M 0x000000FF +#define DBG_PHYA_ETMFFLR__NUMBYTESFREE___S 0 +#define DBG_PHYA_ETMFFLR___M 0x000000FF +#define DBG_PHYA_ETMFFLR___S 0 + +#define DBG_PHYA_ETMCNTRLDVR1 (0x00BEC140) +#define DBG_PHYA_ETMCNTRLDVR1___RWC QCSR_REG_RW +#define DBG_PHYA_ETMCNTRLDVR1___POR 0x00000000 +#define DBG_PHYA_ETMCNTRLDVR1__INITCOUNT___POR 0x0000 +#define DBG_PHYA_ETMCNTRLDVR1__INITCOUNT___M 0x0000FFFF +#define DBG_PHYA_ETMCNTRLDVR1__INITCOUNT___S 0 +#define DBG_PHYA_ETMCNTRLDVR1___M 0x0000FFFF +#define DBG_PHYA_ETMCNTRLDVR1___S 0 + +#define DBG_PHYA_ETMSYNCFR (0x00BEC1E0) +#define DBG_PHYA_ETMSYNCFR___RWC QCSR_REG_RO +#define DBG_PHYA_ETMSYNCFR___POR 0x00000400 +#define DBG_PHYA_ETMSYNCFR__SYNCCYCLECOUNT___POR 0x400 +#define DBG_PHYA_ETMSYNCFR__SYNCCYCLECOUNT___M 0x00000FFF +#define DBG_PHYA_ETMSYNCFR__SYNCCYCLECOUNT___S 0 +#define DBG_PHYA_ETMSYNCFR___M 0x00000FFF +#define DBG_PHYA_ETMSYNCFR___S 0 + +#define DBG_PHYA_ETMIDR (0x00BEC1E4) +#define DBG_PHYA_ETMIDR___RWC QCSR_REG_RO +#define DBG_PHYA_ETMIDR___POR 0x4114F253 +#define DBG_PHYA_ETMIDR__IMPLEMENTERCODE___POR 0x41 +#define DBG_PHYA_ETMIDR__BRPKTENC___POR 0x1 +#define DBG_PHYA_ETMIDR__SECURITYEXTSUPPORT___POR 0x0 +#define DBG_PHYA_ETMIDR__THUMBISTCNTRACE___POR 0x1 +#define DBG_PHYA_ETMIDR__LOADPCFIRST___POR 0x0 +#define DBG_PHYA_ETMIDR__CPUFAMILY___POR 0xF +#define DBG_PHYA_ETMIDR__MAJORETMARCHREV___POR 0x2 +#define DBG_PHYA_ETMIDR__MINORETMARCHREV___POR 0x5 +#define DBG_PHYA_ETMIDR__IMPLREVISION___POR 0x3 +#define DBG_PHYA_ETMIDR__IMPLEMENTERCODE___M 0xFF000000 +#define DBG_PHYA_ETMIDR__IMPLEMENTERCODE___S 24 +#define DBG_PHYA_ETMIDR__IMPLEMENTERCODE__ARM 0x41 +#define DBG_PHYA_ETMIDR__BRPKTENC___M 0x00100000 +#define DBG_PHYA_ETMIDR__BRPKTENC___S 20 +#define DBG_PHYA_ETMIDR__BRPKTENC__IMPLEMENTED 0x1 +#define DBG_PHYA_ETMIDR__SECURITYEXTSUPPORT___M 0x00080000 +#define DBG_PHYA_ETMIDR__SECURITYEXTSUPPORT___S 19 +#define DBG_PHYA_ETMIDR__SECURITYEXTSUPPORT__ALWAYSASSECURE 0x0 +#define DBG_PHYA_ETMIDR__THUMBISTCNTRACE___M 0x00040000 +#define DBG_PHYA_ETMIDR__THUMBISTCNTRACE___S 18 +#define DBG_PHYA_ETMIDR__THUMBISTCNTRACE__THUMB32BTRACEDASSINGLE 0x1 +#define DBG_PHYA_ETMIDR__LOADPCFIRST___M 0x00010000 +#define DBG_PHYA_ETMIDR__LOADPCFIRST___S 16 +#define DBG_PHYA_ETMIDR__LOADPCFIRST__DATATRCNOTSUPPORTED 0x0 +#define DBG_PHYA_ETMIDR__CPUFAMILY___M 0x0000F000 +#define DBG_PHYA_ETMIDR__CPUFAMILY___S 12 +#define DBG_PHYA_ETMIDR__CPUFAMILY__NOTDEFINED 0xF +#define DBG_PHYA_ETMIDR__MAJORETMARCHREV___M 0x00000F00 +#define DBG_PHYA_ETMIDR__MAJORETMARCHREV___S 8 +#define DBG_PHYA_ETMIDR__MINORETMARCHREV___M 0x000000F0 +#define DBG_PHYA_ETMIDR__MINORETMARCHREV___S 4 +#define DBG_PHYA_ETMIDR__IMPLREVISION___M 0x0000000F +#define DBG_PHYA_ETMIDR__IMPLREVISION___S 0 +#define DBG_PHYA_ETMIDR___M 0xFF1DFFFF +#define DBG_PHYA_ETMIDR___S 0 + +#define DBG_PHYA_ETMCCER (0x00BEC1E8) +#define DBG_PHYA_ETMCCER___RWC QCSR_REG_RO +#define DBG_PHYA_ETMCCER___POR 0x18541800 +#define DBG_PHYA_ETMCCER__TSTMPSZ___POR 0x0 +#define DBG_PHYA_ETMCCER__TSTMPENC___POR 0x1 +#define DBG_PHYA_ETMCCER__REDFUNCTNCTR___POR 0x1 +#define DBG_PHYA_ETMCCER__TSTMPIMPL___POR 0x1 +#define DBG_PHYA_ETMCCER__ETMEIBCRIMPL___POR 0x0 +#define DBG_PHYA_ETMCCER__STARTSTOPUSESWTCHPT___POR 0x1 +#define DBG_PHYA_ETMCCER__NUMEMBICEWTCHPTINP___POR 0x4 +#define DBG_PHYA_ETMCCER__NUMINSTRRES___POR 0x0 +#define DBG_PHYA_ETMCCER__DATAADDRCOMPSUPP___POR 0x1 +#define DBG_PHYA_ETMCCER__REGSREADABLE___POR 0x1 +#define DBG_PHYA_ETMCCER__EXTINPBUSIMPL___POR 0x00 +#define DBG_PHYA_ETMCCER__EXTINPSEL___POR 0x0 +#define DBG_PHYA_ETMCCER__TSTMPSZ___M 0x20000000 +#define DBG_PHYA_ETMCCER__TSTMPSZ___S 29 +#define DBG_PHYA_ETMCCER__TSTMPSZ__SZIS48BIT 0x0 +#define DBG_PHYA_ETMCCER__TSTMPENC___M 0x10000000 +#define DBG_PHYA_ETMCCER__TSTMPENC___S 28 +#define DBG_PHYA_ETMCCER__TSTMPENC__ENCISNATBIN 0x1 +#define DBG_PHYA_ETMCCER__REDFUNCTNCTR___M 0x08000000 +#define DBG_PHYA_ETMCCER__REDFUNCTNCTR___S 27 +#define DBG_PHYA_ETMCCER__REDFUNCTNCTR__CTRISREDFUNCCTR 0x1 +#define DBG_PHYA_ETMCCER__TSTMPIMPL___M 0x00400000 +#define DBG_PHYA_ETMCCER__TSTMPIMPL___S 22 +#define DBG_PHYA_ETMCCER__TSTMPIMPL__TSTMPISIMPL 0x1 +#define DBG_PHYA_ETMCCER__ETMEIBCRIMPL___M 0x00200000 +#define DBG_PHYA_ETMCCER__ETMEIBCRIMPL___S 21 +#define DBG_PHYA_ETMCCER__ETMEIBCRIMPL__ETMEIBCRNOTIMPL 0x0 +#define DBG_PHYA_ETMCCER__STARTSTOPUSESWTCHPT___M 0x00100000 +#define DBG_PHYA_ETMCCER__STARTSTOPUSESWTCHPT___S 20 +#define DBG_PHYA_ETMCCER__STARTSTOPUSESWTCHPT__STARTSTOPUSESWTCHPTYES 0x1 +#define DBG_PHYA_ETMCCER__NUMEMBICEWTCHPTINP___M 0x000F0000 +#define DBG_PHYA_ETMCCER__NUMEMBICEWTCHPTINP___S 16 +#define DBG_PHYA_ETMCCER__NUMINSTRRES___M 0x0000E000 +#define DBG_PHYA_ETMCCER__NUMINSTRRES___S 13 +#define DBG_PHYA_ETMCCER__DATAADDRCOMPSUPP___M 0x00001000 +#define DBG_PHYA_ETMCCER__DATAADDRCOMPSUPP___S 12 +#define DBG_PHYA_ETMCCER__DATAADDRCOMPSUPP__DATAADDRCOMPNOTSUPPORTED 0x0 +#define DBG_PHYA_ETMCCER__REGSREADABLE___M 0x00000800 +#define DBG_PHYA_ETMCCER__REGSREADABLE___S 11 +#define DBG_PHYA_ETMCCER__REGSREADABLE__REGSAREREADABLE 0x1 +#define DBG_PHYA_ETMCCER__EXTINPBUSIMPL___M 0x000007F8 +#define DBG_PHYA_ETMCCER__EXTINPBUSIMPL___S 3 +#define DBG_PHYA_ETMCCER__EXTINPSEL___M 0x00000007 +#define DBG_PHYA_ETMCCER__EXTINPSEL___S 0 +#define DBG_PHYA_ETMCCER___M 0x387FFFFF +#define DBG_PHYA_ETMCCER___S 0 + +#define DBG_PHYA_ETMTESSEICR (0x00BEC1F0) +#define DBG_PHYA_ETMTESSEICR___RWC QCSR_REG_RW +#define DBG_PHYA_ETMTESSEICR___POR 0x00000000 +#define DBG_PHYA_ETMTESSEICR__STOPRESSEL___POR 0x0 +#define DBG_PHYA_ETMTESSEICR__STARTRESSEL___POR 0x00 +#define DBG_PHYA_ETMTESSEICR__STOPRESSEL___M 0x000F0000 +#define DBG_PHYA_ETMTESSEICR__STOPRESSEL___S 16 +#define DBG_PHYA_ETMTESSEICR__STARTRESSEL___M 0x000000FF +#define DBG_PHYA_ETMTESSEICR__STARTRESSEL___S 0 +#define DBG_PHYA_ETMTESSEICR___M 0x000F00FF +#define DBG_PHYA_ETMTESSEICR___S 0 + +#define DBG_PHYA_ETMTSEVR (0x00BEC1F8) +#define DBG_PHYA_ETMTSEVR___RWC QCSR_REG_RW +#define DBG_PHYA_ETMTSEVR___POR 0x00000000 +#define DBG_PHYA_ETMTSEVR__FUNCTION___POR 0x0 +#define DBG_PHYA_ETMTSEVR__RESOURCEBTYPE___POR 0x0 +#define DBG_PHYA_ETMTSEVR__RESOURCEBINDEX___POR 0x0 +#define DBG_PHYA_ETMTSEVR__RESOURCEATYPE___POR 0x0 +#define DBG_PHYA_ETMTSEVR__RESOURCEAINDEX___POR 0x0 +#define DBG_PHYA_ETMTSEVR__FUNCTION___M 0x0001C000 +#define DBG_PHYA_ETMTSEVR__FUNCTION___S 14 +#define DBG_PHYA_ETMTSEVR__FUNCTION__A 0x0 +#define DBG_PHYA_ETMTSEVR__FUNCTION__NOTA 0x1 +#define DBG_PHYA_ETMTSEVR__FUNCTION__A_AND_B 0x2 +#define DBG_PHYA_ETMTSEVR__FUNCTION__NOTA_AND_B 0x3 +#define DBG_PHYA_ETMTSEVR__FUNCTION__NOTA_AND_NOTB 0x4 +#define DBG_PHYA_ETMTSEVR__FUNCTION__A_OR_B 0x5 +#define DBG_PHYA_ETMTSEVR__FUNCTION__NOTA_OR_B 0x6 +#define DBG_PHYA_ETMTSEVR__FUNCTION__NOTA_OR_NOTB 0x7 +#define DBG_PHYA_ETMTSEVR__RESOURCEBTYPE___M 0x00003800 +#define DBG_PHYA_ETMTSEVR__RESOURCEBTYPE___S 11 +#define DBG_PHYA_ETMTSEVR__RESOURCEBTYPE__ILLEGAL 0x0 +#define DBG_PHYA_ETMTSEVR__RESOURCEBTYPE__DWTCOMPINP 0x2 +#define DBG_PHYA_ETMTSEVR__RESOURCEBTYPE__CNTRZERO 0x4 +#define DBG_PHYA_ETMTSEVR__RESOURCEBTYPE__MISC1 0x5 +#define DBG_PHYA_ETMTSEVR__RESOURCEBTYPE__MISC2 0x6 +#define DBG_PHYA_ETMTSEVR__RESOURCEBINDEX___M 0x00000780 +#define DBG_PHYA_ETMTSEVR__RESOURCEBINDEX___S 7 +#define DBG_PHYA_ETMTSEVR__RESOURCEBINDEX__DWTCOMP1 0x0 +#define DBG_PHYA_ETMTSEVR__RESOURCEBINDEX__DWTCOMP2 0x1 +#define DBG_PHYA_ETMTSEVR__RESOURCEBINDEX__DWTCOMP3 0x2 +#define DBG_PHYA_ETMTSEVR__RESOURCEBINDEX__DWTCOMP4 0x3 +#define DBG_PHYA_ETMTSEVR__RESOURCEBINDEX__CNTR1ATZERO 0x0 +#define DBG_PHYA_ETMTSEVR__RESOURCEBINDEX__TRCSTARTSTOPRES 0xF +#define DBG_PHYA_ETMTSEVR__RESOURCEBINDEX__EXTINP1 0x0 +#define DBG_PHYA_ETMTSEVR__RESOURCEBINDEX__EXTINP2 0x1 +#define DBG_PHYA_ETMTSEVR__RESOURCEBINDEX__ALWAYSTRUE 0xF +#define DBG_PHYA_ETMTSEVR__RESOURCEATYPE___M 0x00000070 +#define DBG_PHYA_ETMTSEVR__RESOURCEATYPE___S 4 +#define DBG_PHYA_ETMTSEVR__RESOURCEATYPE__ILLEGAL 0x0 +#define DBG_PHYA_ETMTSEVR__RESOURCEATYPE__DWTCOMPINP 0x2 +#define DBG_PHYA_ETMTSEVR__RESOURCEATYPE__CNTRZERO 0x4 +#define DBG_PHYA_ETMTSEVR__RESOURCEATYPE__MISC1 0x5 +#define DBG_PHYA_ETMTSEVR__RESOURCEATYPE__MISC2 0x6 +#define DBG_PHYA_ETMTSEVR__RESOURCEAINDEX___M 0x0000000F +#define DBG_PHYA_ETMTSEVR__RESOURCEAINDEX___S 0 +#define DBG_PHYA_ETMTSEVR__RESOURCEAINDEX__DWTCOMP1 0x0 +#define DBG_PHYA_ETMTSEVR__RESOURCEAINDEX__DWTCOMP2 0x1 +#define DBG_PHYA_ETMTSEVR__RESOURCEAINDEX__DWTCOMP3 0x2 +#define DBG_PHYA_ETMTSEVR__RESOURCEAINDEX__DWTCOMP4 0x3 +#define DBG_PHYA_ETMTSEVR__RESOURCEAINDEX__CNTR1ATZERO 0x0 +#define DBG_PHYA_ETMTSEVR__RESOURCEAINDEX__TRCSTARTSTOPRES 0xF +#define DBG_PHYA_ETMTSEVR__RESOURCEAINDEX__EXTINP1 0x0 +#define DBG_PHYA_ETMTSEVR__RESOURCEAINDEX__EXTINP2 0x1 +#define DBG_PHYA_ETMTSEVR__RESOURCEAINDEX__ALWAYSTRUE 0xF +#define DBG_PHYA_ETMTSEVR___M 0x0001FFFF +#define DBG_PHYA_ETMTSEVR___S 0 + +#define DBG_PHYA_ETMTRACEIDR (0x00BEC200) +#define DBG_PHYA_ETMTRACEIDR___RWC QCSR_REG_RW +#define DBG_PHYA_ETMTRACEIDR___POR 0x00000000 +#define DBG_PHYA_ETMTRACEIDR__ATBID___POR 0x00 +#define DBG_PHYA_ETMTRACEIDR__ATBID___M 0x0000007F +#define DBG_PHYA_ETMTRACEIDR__ATBID___S 0 +#define DBG_PHYA_ETMTRACEIDR___M 0x0000007F +#define DBG_PHYA_ETMTRACEIDR___S 0 + +#define DBG_PHYA_ETMIDR2 (0x00BEC208) +#define DBG_PHYA_ETMIDR2___RWC QCSR_REG_RO +#define DBG_PHYA_ETMIDR2___POR 0x00000000 +#define DBG_PHYA_ETMIDR2__SWPXFERORDER___POR 0x0 +#define DBG_PHYA_ETMIDR2__RFEXFERORDER___POR 0x0 +#define DBG_PHYA_ETMIDR2__SWPXFERORDER___M 0x00000002 +#define DBG_PHYA_ETMIDR2__SWPXFERORDER___S 1 +#define DBG_PHYA_ETMIDR2__SWPXFERORDER__LOADBEFORESTORE 0x0 +#define DBG_PHYA_ETMIDR2__SWPXFERORDER__STOREBEFORELOAD 0x1 +#define DBG_PHYA_ETMIDR2__RFEXFERORDER___M 0x00000001 +#define DBG_PHYA_ETMIDR2__RFEXFERORDER___S 0 +#define DBG_PHYA_ETMIDR2__RFEXFERORDER__PCBEFORECPSR 0x0 +#define DBG_PHYA_ETMIDR2__RFEXFERORDER__CPSRBEFOREPC 0x1 +#define DBG_PHYA_ETMIDR2___M 0x00000003 +#define DBG_PHYA_ETMIDR2___S 0 + +#define DBG_PHYA_ETMPDSR (0x00BEC314) +#define DBG_PHYA_ETMPDSR___RWC QCSR_REG_RO +#define DBG_PHYA_ETMPDSR___POR 0x00000001 +#define DBG_PHYA_ETMPDSR__ETMPWRDUP___POR 0x1 +#define DBG_PHYA_ETMPDSR__ETMPWRDUP___M 0x00000001 +#define DBG_PHYA_ETMPDSR__ETMPWRDUP___S 0 +#define DBG_PHYA_ETMPDSR___M 0x00000001 +#define DBG_PHYA_ETMPDSR___S 0 + +#define DBG_PHYA_ETM_ITMISCIN (0x00BECEE0) +#define DBG_PHYA_ETM_ITMISCIN___RWC QCSR_REG_RO +#define DBG_PHYA_ETM_ITMISCIN___POR 0x00000000 +#define DBG_PHYA_ETM_ITMISCIN__COREHALT___POR 0x0 +#define DBG_PHYA_ETM_ITMISCIN__EXTIN___POR 0x0 +#define DBG_PHYA_ETM_ITMISCIN__COREHALT___M 0x00000010 +#define DBG_PHYA_ETM_ITMISCIN__COREHALT___S 4 +#define DBG_PHYA_ETM_ITMISCIN__EXTIN___M 0x00000003 +#define DBG_PHYA_ETM_ITMISCIN__EXTIN___S 0 +#define DBG_PHYA_ETM_ITMISCIN___M 0x00000013 +#define DBG_PHYA_ETM_ITMISCIN___S 0 + +#define DBG_PHYA_ETM_ITTRIGOUT (0x00BECEE8) +#define DBG_PHYA_ETM_ITTRIGOUT___RWC QCSR_REG_WO +#define DBG_PHYA_ETM_ITTRIGOUT___POR 0x00000000 +#define DBG_PHYA_ETM_ITTRIGOUT__TRIGOUT___POR 0x0 +#define DBG_PHYA_ETM_ITTRIGOUT__TRIGOUT___M 0x00000001 +#define DBG_PHYA_ETM_ITTRIGOUT__TRIGOUT___S 0 +#define DBG_PHYA_ETM_ITTRIGOUT___M 0x00000001 +#define DBG_PHYA_ETM_ITTRIGOUT___S 0 + +#define DBG_PHYA_ETM_ITATBCTR2 (0x00BECEF0) +#define DBG_PHYA_ETM_ITATBCTR2___RWC QCSR_REG_RO +#define DBG_PHYA_ETM_ITATBCTR2___POR 0x00000001 +#define DBG_PHYA_ETM_ITATBCTR2__ATREADY___POR 0x1 +#define DBG_PHYA_ETM_ITATBCTR2__ATREADY___M 0x00000001 +#define DBG_PHYA_ETM_ITATBCTR2__ATREADY___S 0 +#define DBG_PHYA_ETM_ITATBCTR2___M 0x00000001 +#define DBG_PHYA_ETM_ITATBCTR2___S 0 + +#define DBG_PHYA_ETM_ITATBCTR0 (0x00BECEF8) +#define DBG_PHYA_ETM_ITATBCTR0___RWC QCSR_REG_WO +#define DBG_PHYA_ETM_ITATBCTR0___POR 0x00000000 +#define DBG_PHYA_ETM_ITATBCTR0__ATVALID___POR 0x0 +#define DBG_PHYA_ETM_ITATBCTR0__ATVALID___M 0x00000001 +#define DBG_PHYA_ETM_ITATBCTR0__ATVALID___S 0 +#define DBG_PHYA_ETM_ITATBCTR0___M 0x00000001 +#define DBG_PHYA_ETM_ITATBCTR0___S 0 + +#define DBG_PHYA_ETMITCTRL (0x00BECF00) +#define DBG_PHYA_ETMITCTRL___RWC QCSR_REG_RW +#define DBG_PHYA_ETMITCTRL___POR 0x00000000 +#define DBG_PHYA_ETMITCTRL__ENABLE___POR 0x0 +#define DBG_PHYA_ETMITCTRL__ENABLE___M 0x00000001 +#define DBG_PHYA_ETMITCTRL__ENABLE___S 0 +#define DBG_PHYA_ETMITCTRL___M 0x00000001 +#define DBG_PHYA_ETMITCTRL___S 0 + +#define DBG_PHYA_ETMCLAIMSET (0x00BECFA0) +#define DBG_PHYA_ETMCLAIMSET___RWC QCSR_REG_RW +#define DBG_PHYA_ETMCLAIMSET___POR 0x0000000F +#define DBG_PHYA_ETMCLAIMSET__TAG___POR 0xF +#define DBG_PHYA_ETMCLAIMSET__TAG___M 0x0000000F +#define DBG_PHYA_ETMCLAIMSET__TAG___S 0 +#define DBG_PHYA_ETMCLAIMSET___M 0x0000000F +#define DBG_PHYA_ETMCLAIMSET___S 0 + +#define DBG_PHYA_ETMCLAIMCLR (0x00BECFA4) +#define DBG_PHYA_ETMCLAIMCLR___RWC QCSR_REG_RW +#define DBG_PHYA_ETMCLAIMCLR___POR 0x00000000 +#define DBG_PHYA_ETMCLAIMCLR__TAG___POR 0x00 +#define DBG_PHYA_ETMCLAIMCLR__TAG___M 0x000000FF +#define DBG_PHYA_ETMCLAIMCLR__TAG___S 0 +#define DBG_PHYA_ETMCLAIMCLR___M 0x000000FF +#define DBG_PHYA_ETMCLAIMCLR___S 0 + +#define DBG_PHYA_ETMLAR (0x00BECFB0) +#define DBG_PHYA_ETMLAR___RWC QCSR_REG_RW +#define DBG_PHYA_ETMLAR___POR 0x00000000 +#define DBG_PHYA_ETMLAR__VALUE___POR 0x00000000 +#define DBG_PHYA_ETMLAR__VALUE___M 0xFFFFFFFF +#define DBG_PHYA_ETMLAR__VALUE___S 0 +#define DBG_PHYA_ETMLAR___M 0xFFFFFFFF +#define DBG_PHYA_ETMLAR___S 0 + +#define DBG_PHYA_ETMLSR (0x00BECFB4) +#define DBG_PHYA_ETMLSR___RWC QCSR_REG_RO +#define DBG_PHYA_ETMLSR___POR 0x00000003 +#define DBG_PHYA_ETMLSR__LOCKED___POR 0x1 +#define DBG_PHYA_ETMLSR__LOCKINGIMPL___POR 0x1 +#define DBG_PHYA_ETMLSR__LOCKED___M 0x00000002 +#define DBG_PHYA_ETMLSR__LOCKED___S 1 +#define DBG_PHYA_ETMLSR__LOCKED__ETMUNLOCKED 0x0 +#define DBG_PHYA_ETMLSR__LOCKED__ETMLOCKED 0x1 +#define DBG_PHYA_ETMLSR__LOCKINGIMPL___M 0x00000001 +#define DBG_PHYA_ETMLSR__LOCKINGIMPL___S 0 +#define DBG_PHYA_ETMLSR___M 0x00000003 +#define DBG_PHYA_ETMLSR___S 0 + +#define DBG_PHYA_ETMAUTHSTATUS (0x00BECFB8) +#define DBG_PHYA_ETMAUTHSTATUS___RWC QCSR_REG_RO +#define DBG_PHYA_ETMAUTHSTATUS__SNI___M 0x000000C0 +#define DBG_PHYA_ETMAUTHSTATUS__SNI___S 6 +#define DBG_PHYA_ETMAUTHSTATUS__SI___M 0x00000030 +#define DBG_PHYA_ETMAUTHSTATUS__SI___S 4 +#define DBG_PHYA_ETMAUTHSTATUS__NSNI___M 0x0000000C +#define DBG_PHYA_ETMAUTHSTATUS__NSNI___S 2 +#define DBG_PHYA_ETMAUTHSTATUS__NSI___M 0x00000003 +#define DBG_PHYA_ETMAUTHSTATUS__NSI___S 0 +#define DBG_PHYA_ETMAUTHSTATUS___M 0x000000FF +#define DBG_PHYA_ETMAUTHSTATUS___S 0 + +#define DBG_PHYA_ETMDEVTYPE (0x00BECFCC) +#define DBG_PHYA_ETMDEVTYPE___RWC QCSR_REG_RO +#define DBG_PHYA_ETMDEVTYPE___POR 0x00000013 +#define DBG_PHYA_ETMDEVTYPE__SUBTYPE___POR 0x1 +#define DBG_PHYA_ETMDEVTYPE__MAJTYPE___POR 0x3 +#define DBG_PHYA_ETMDEVTYPE__SUBTYPE___M 0x000000F0 +#define DBG_PHYA_ETMDEVTYPE__SUBTYPE___S 4 +#define DBG_PHYA_ETMDEVTYPE__MAJTYPE___M 0x0000000F +#define DBG_PHYA_ETMDEVTYPE__MAJTYPE___S 0 +#define DBG_PHYA_ETMDEVTYPE___M 0x000000FF +#define DBG_PHYA_ETMDEVTYPE___S 0 + +#define DBG_PHYA_ETMPIDR4 (0x00BECFD0) +#define DBG_PHYA_ETMPIDR4___RWC QCSR_REG_RO +#define DBG_PHYA_ETMPIDR4___POR 0x00000004 +#define DBG_PHYA_ETMPIDR4__FIELD_4KB_COUNT___POR 0x0 +#define DBG_PHYA_ETMPIDR4__JEP106_CONTINUATION___POR 0x4 +#define DBG_PHYA_ETMPIDR4__FIELD_4KB_COUNT___M 0x000000F0 +#define DBG_PHYA_ETMPIDR4__FIELD_4KB_COUNT___S 4 +#define DBG_PHYA_ETMPIDR4__JEP106_CONTINUATION___M 0x0000000F +#define DBG_PHYA_ETMPIDR4__JEP106_CONTINUATION___S 0 +#define DBG_PHYA_ETMPIDR4___M 0x000000FF +#define DBG_PHYA_ETMPIDR4___S 0 + +#define DBG_PHYA_ETMPIDR0 (0x00BECFE0) +#define DBG_PHYA_ETMPIDR0___RWC QCSR_REG_RO +#define DBG_PHYA_ETMPIDR0___POR 0x00000024 +#define DBG_PHYA_ETMPIDR0__PARTNUM_7_0___POR 0x24 +#define DBG_PHYA_ETMPIDR0__PARTNUM_7_0___M 0x000000FF +#define DBG_PHYA_ETMPIDR0__PARTNUM_7_0___S 0 +#define DBG_PHYA_ETMPIDR0___M 0x000000FF +#define DBG_PHYA_ETMPIDR0___S 0 + +#define DBG_PHYA_ETMPIDR1 (0x00BECFE4) +#define DBG_PHYA_ETMPIDR1___RWC QCSR_REG_RO +#define DBG_PHYA_ETMPIDR1___POR 0x000000B9 +#define DBG_PHYA_ETMPIDR1__JEP106_IDENTITY_3_0___POR 0xB +#define DBG_PHYA_ETMPIDR1__PARTNUM_11_8___POR 0x9 +#define DBG_PHYA_ETMPIDR1__JEP106_IDENTITY_3_0___M 0x000000F0 +#define DBG_PHYA_ETMPIDR1__JEP106_IDENTITY_3_0___S 4 +#define DBG_PHYA_ETMPIDR1__PARTNUM_11_8___M 0x0000000F +#define DBG_PHYA_ETMPIDR1__PARTNUM_11_8___S 0 +#define DBG_PHYA_ETMPIDR1___M 0x000000FF +#define DBG_PHYA_ETMPIDR1___S 0 + +#define DBG_PHYA_ETMPIDR2 (0x00BECFE8) +#define DBG_PHYA_ETMPIDR2___RWC QCSR_REG_RO +#define DBG_PHYA_ETMPIDR2___POR 0x0000003B +#define DBG_PHYA_ETMPIDR2__MAJREV___POR 0x3 +#define DBG_PHYA_ETMPIDR2__JEDEC___POR 0x1 +#define DBG_PHYA_ETMPIDR2__JEP106_IDENTITY_6_4___POR 0x3 +#define DBG_PHYA_ETMPIDR2__MAJREV___M 0x000000F0 +#define DBG_PHYA_ETMPIDR2__MAJREV___S 4 +#define DBG_PHYA_ETMPIDR2__JEDEC___M 0x00000008 +#define DBG_PHYA_ETMPIDR2__JEDEC___S 3 +#define DBG_PHYA_ETMPIDR2__JEP106_IDENTITY_6_4___M 0x00000007 +#define DBG_PHYA_ETMPIDR2__JEP106_IDENTITY_6_4___S 0 +#define DBG_PHYA_ETMPIDR2___M 0x000000FF +#define DBG_PHYA_ETMPIDR2___S 0 + +#define DBG_PHYA_ETMPIDR3 (0x00BECFEC) +#define DBG_PHYA_ETMPIDR3___RWC QCSR_REG_RO +#define DBG_PHYA_ETMPIDR3___POR 0x00000000 +#define DBG_PHYA_ETMPIDR3__REV_AND___POR 0x0 +#define DBG_PHYA_ETMPIDR3__CUSTOMER_MODIFIED___POR 0x0 +#define DBG_PHYA_ETMPIDR3__REV_AND___M 0x000000F0 +#define DBG_PHYA_ETMPIDR3__REV_AND___S 4 +#define DBG_PHYA_ETMPIDR3__CUSTOMER_MODIFIED___M 0x0000000F +#define DBG_PHYA_ETMPIDR3__CUSTOMER_MODIFIED___S 0 +#define DBG_PHYA_ETMPIDR3___M 0x000000FF +#define DBG_PHYA_ETMPIDR3___S 0 + +#define DBG_PHYA_ETMCIDR0 (0x00BECFF0) +#define DBG_PHYA_ETMCIDR0___RWC QCSR_REG_RO +#define DBG_PHYA_ETMCIDR0___POR 0x0000000D +#define DBG_PHYA_ETMCIDR0__PREAMBLE_7_0___POR 0x0D +#define DBG_PHYA_ETMCIDR0__PREAMBLE_7_0___M 0x000000FF +#define DBG_PHYA_ETMCIDR0__PREAMBLE_7_0___S 0 +#define DBG_PHYA_ETMCIDR0___M 0x000000FF +#define DBG_PHYA_ETMCIDR0___S 0 + +#define DBG_PHYA_ETMCIDR1 (0x00BECFF4) +#define DBG_PHYA_ETMCIDR1___RWC QCSR_REG_RO +#define DBG_PHYA_ETMCIDR1___POR 0x00000090 +#define DBG_PHYA_ETMCIDR1__PREAMBLE_15_12___POR 0x9 +#define DBG_PHYA_ETMCIDR1__PREAMBLE_11_8___POR 0x0 +#define DBG_PHYA_ETMCIDR1__PREAMBLE_15_12___M 0x000000F0 +#define DBG_PHYA_ETMCIDR1__PREAMBLE_15_12___S 4 +#define DBG_PHYA_ETMCIDR1__PREAMBLE_11_8___M 0x0000000F +#define DBG_PHYA_ETMCIDR1__PREAMBLE_11_8___S 0 +#define DBG_PHYA_ETMCIDR1___M 0x000000FF +#define DBG_PHYA_ETMCIDR1___S 0 + +#define DBG_PHYA_ETMCIDR2 (0x00BECFF8) +#define DBG_PHYA_ETMCIDR2___RWC QCSR_REG_RO +#define DBG_PHYA_ETMCIDR2___POR 0x00000005 +#define DBG_PHYA_ETMCIDR2__PREAMBLE_23_16___POR 0x05 +#define DBG_PHYA_ETMCIDR2__PREAMBLE_23_16___M 0x000000FF +#define DBG_PHYA_ETMCIDR2__PREAMBLE_23_16___S 0 +#define DBG_PHYA_ETMCIDR2___M 0x000000FF +#define DBG_PHYA_ETMCIDR2___S 0 + +#define DBG_PHYA_ETMCIDR3 (0x00BECFFC) +#define DBG_PHYA_ETMCIDR3___RWC QCSR_REG_RO +#define DBG_PHYA_ETMCIDR3___POR 0x000000B1 +#define DBG_PHYA_ETMCIDR3__PREAMBLE_31_24___POR 0xB1 +#define DBG_PHYA_ETMCIDR3__PREAMBLE_31_24___M 0x000000FF +#define DBG_PHYA_ETMCIDR3__PREAMBLE_31_24___S 0 +#define DBG_PHYA_ETMCIDR3___M 0x000000FF +#define DBG_PHYA_ETMCIDR3___S 0 + +#define DBG_PHYA_M3CTI_CTICONTROL (0x00BED000) +#define DBG_PHYA_M3CTI_CTICONTROL___RWC QCSR_REG_RW +#define DBG_PHYA_M3CTI_CTICONTROL___POR 0x00000000 +#define DBG_PHYA_M3CTI_CTICONTROL__GLBEN___POR 0x0 +#define DBG_PHYA_M3CTI_CTICONTROL__GLBEN___M 0x00000001 +#define DBG_PHYA_M3CTI_CTICONTROL__GLBEN___S 0 +#define DBG_PHYA_M3CTI_CTICONTROL__GLBEN__DISABLED 0x0 +#define DBG_PHYA_M3CTI_CTICONTROL__GLBEN__ENABLED 0x1 +#define DBG_PHYA_M3CTI_CTICONTROL___M 0x00000001 +#define DBG_PHYA_M3CTI_CTICONTROL___S 0 + +#define DBG_PHYA_M3CTI_CTIINTACK (0x00BED010) +#define DBG_PHYA_M3CTI_CTIINTACK___RWC QCSR_REG_WO +#define DBG_PHYA_M3CTI_CTIINTACK___POR 0x00000000 +#define DBG_PHYA_M3CTI_CTIINTACK__INTACK___POR 0x00 +#define DBG_PHYA_M3CTI_CTIINTACK__INTACK___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIINTACK__INTACK___S 0 +#define DBG_PHYA_M3CTI_CTIINTACK___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIINTACK___S 0 + +#define DBG_PHYA_M3CTI_CTIAPPSET (0x00BED014) +#define DBG_PHYA_M3CTI_CTIAPPSET___RWC QCSR_REG_RW +#define DBG_PHYA_M3CTI_CTIAPPSET___POR 0x00000000 +#define DBG_PHYA_M3CTI_CTIAPPSET__APPSET___POR 0x00 +#define DBG_PHYA_M3CTI_CTIAPPSET__APPSET___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIAPPSET__APPSET___S 0 +#define DBG_PHYA_M3CTI_CTIAPPSET___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIAPPSET___S 0 + +#define DBG_PHYA_M3CTI_CTIAPPCLEAR (0x00BED018) +#define DBG_PHYA_M3CTI_CTIAPPCLEAR___RWC QCSR_REG_WO +#define DBG_PHYA_M3CTI_CTIAPPCLEAR___POR 0x00000000 +#define DBG_PHYA_M3CTI_CTIAPPCLEAR__APPCLEAR___POR 0x00 +#define DBG_PHYA_M3CTI_CTIAPPCLEAR__APPCLEAR___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIAPPCLEAR__APPCLEAR___S 0 +#define DBG_PHYA_M3CTI_CTIAPPCLEAR___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIAPPCLEAR___S 0 + +#define DBG_PHYA_M3CTI_CTIAPPPULSE (0x00BED01C) +#define DBG_PHYA_M3CTI_CTIAPPPULSE___RWC QCSR_REG_WO +#define DBG_PHYA_M3CTI_CTIAPPPULSE___POR 0x00000000 +#define DBG_PHYA_M3CTI_CTIAPPPULSE__APPULSE___POR 0x00 +#define DBG_PHYA_M3CTI_CTIAPPPULSE__APPULSE___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIAPPPULSE__APPULSE___S 0 +#define DBG_PHYA_M3CTI_CTIAPPPULSE___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIAPPPULSE___S 0 + +#define DBG_PHYA_M3CTI_CTIINEN0 (0x00BED020) +#define DBG_PHYA_M3CTI_CTIINEN0___RWC QCSR_REG_RW +#define DBG_PHYA_M3CTI_CTIINEN0___POR 0x00000000 +#define DBG_PHYA_M3CTI_CTIINEN0__TRIGINEN___POR 0x00 +#define DBG_PHYA_M3CTI_CTIINEN0__TRIGINEN___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIINEN0__TRIGINEN___S 0 +#define DBG_PHYA_M3CTI_CTIINEN0___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIINEN0___S 0 + +#define DBG_PHYA_M3CTI_CTIINEN1 (0x00BED024) +#define DBG_PHYA_M3CTI_CTIINEN1___RWC QCSR_REG_RW +#define DBG_PHYA_M3CTI_CTIINEN1___POR 0x00000000 +#define DBG_PHYA_M3CTI_CTIINEN1__TRIGINEN___POR 0x00 +#define DBG_PHYA_M3CTI_CTIINEN1__TRIGINEN___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIINEN1__TRIGINEN___S 0 +#define DBG_PHYA_M3CTI_CTIINEN1___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIINEN1___S 0 + +#define DBG_PHYA_M3CTI_CTIINEN2 (0x00BED028) +#define DBG_PHYA_M3CTI_CTIINEN2___RWC QCSR_REG_RW +#define DBG_PHYA_M3CTI_CTIINEN2___POR 0x00000000 +#define DBG_PHYA_M3CTI_CTIINEN2__TRIGINEN___POR 0x00 +#define DBG_PHYA_M3CTI_CTIINEN2__TRIGINEN___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIINEN2__TRIGINEN___S 0 +#define DBG_PHYA_M3CTI_CTIINEN2___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIINEN2___S 0 + +#define DBG_PHYA_M3CTI_CTIINEN3 (0x00BED02C) +#define DBG_PHYA_M3CTI_CTIINEN3___RWC QCSR_REG_RW +#define DBG_PHYA_M3CTI_CTIINEN3___POR 0x00000000 +#define DBG_PHYA_M3CTI_CTIINEN3__TRIGINEN___POR 0x00 +#define DBG_PHYA_M3CTI_CTIINEN3__TRIGINEN___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIINEN3__TRIGINEN___S 0 +#define DBG_PHYA_M3CTI_CTIINEN3___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIINEN3___S 0 + +#define DBG_PHYA_M3CTI_CTIINEN4 (0x00BED030) +#define DBG_PHYA_M3CTI_CTIINEN4___RWC QCSR_REG_RW +#define DBG_PHYA_M3CTI_CTIINEN4___POR 0x00000000 +#define DBG_PHYA_M3CTI_CTIINEN4__TRIGINEN___POR 0x00 +#define DBG_PHYA_M3CTI_CTIINEN4__TRIGINEN___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIINEN4__TRIGINEN___S 0 +#define DBG_PHYA_M3CTI_CTIINEN4___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIINEN4___S 0 + +#define DBG_PHYA_M3CTI_CTIINEN5 (0x00BED034) +#define DBG_PHYA_M3CTI_CTIINEN5___RWC QCSR_REG_RW +#define DBG_PHYA_M3CTI_CTIINEN5___POR 0x00000000 +#define DBG_PHYA_M3CTI_CTIINEN5__TRIGINEN___POR 0x00 +#define DBG_PHYA_M3CTI_CTIINEN5__TRIGINEN___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIINEN5__TRIGINEN___S 0 +#define DBG_PHYA_M3CTI_CTIINEN5___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIINEN5___S 0 + +#define DBG_PHYA_M3CTI_CTIINEN6 (0x00BED038) +#define DBG_PHYA_M3CTI_CTIINEN6___RWC QCSR_REG_RW +#define DBG_PHYA_M3CTI_CTIINEN6___POR 0x00000000 +#define DBG_PHYA_M3CTI_CTIINEN6__TRIGINEN___POR 0x00 +#define DBG_PHYA_M3CTI_CTIINEN6__TRIGINEN___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIINEN6__TRIGINEN___S 0 +#define DBG_PHYA_M3CTI_CTIINEN6___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIINEN6___S 0 + +#define DBG_PHYA_M3CTI_CTIINEN7 (0x00BED03C) +#define DBG_PHYA_M3CTI_CTIINEN7___RWC QCSR_REG_RW +#define DBG_PHYA_M3CTI_CTIINEN7___POR 0x00000000 +#define DBG_PHYA_M3CTI_CTIINEN7__TRIGINEN___POR 0x00 +#define DBG_PHYA_M3CTI_CTIINEN7__TRIGINEN___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIINEN7__TRIGINEN___S 0 +#define DBG_PHYA_M3CTI_CTIINEN7___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIINEN7___S 0 + +#define DBG_PHYA_M3CTI_CTIOUTEN0 (0x00BED0A0) +#define DBG_PHYA_M3CTI_CTIOUTEN0___RWC QCSR_REG_RW +#define DBG_PHYA_M3CTI_CTIOUTEN0___POR 0x00000000 +#define DBG_PHYA_M3CTI_CTIOUTEN0__TRIGOUTEN___POR 0x00 +#define DBG_PHYA_M3CTI_CTIOUTEN0__TRIGOUTEN___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIOUTEN0__TRIGOUTEN___S 0 +#define DBG_PHYA_M3CTI_CTIOUTEN0___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIOUTEN0___S 0 + +#define DBG_PHYA_M3CTI_CTIOUTEN1 (0x00BED0A4) +#define DBG_PHYA_M3CTI_CTIOUTEN1___RWC QCSR_REG_RW +#define DBG_PHYA_M3CTI_CTIOUTEN1___POR 0x00000000 +#define DBG_PHYA_M3CTI_CTIOUTEN1__TRIGOUTEN___POR 0x00 +#define DBG_PHYA_M3CTI_CTIOUTEN1__TRIGOUTEN___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIOUTEN1__TRIGOUTEN___S 0 +#define DBG_PHYA_M3CTI_CTIOUTEN1___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIOUTEN1___S 0 + +#define DBG_PHYA_M3CTI_CTIOUTEN2 (0x00BED0A8) +#define DBG_PHYA_M3CTI_CTIOUTEN2___RWC QCSR_REG_RW +#define DBG_PHYA_M3CTI_CTIOUTEN2___POR 0x00000000 +#define DBG_PHYA_M3CTI_CTIOUTEN2__TRIGOUTEN___POR 0x00 +#define DBG_PHYA_M3CTI_CTIOUTEN2__TRIGOUTEN___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIOUTEN2__TRIGOUTEN___S 0 +#define DBG_PHYA_M3CTI_CTIOUTEN2___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIOUTEN2___S 0 + +#define DBG_PHYA_M3CTI_CTIOUTEN3 (0x00BED0AC) +#define DBG_PHYA_M3CTI_CTIOUTEN3___RWC QCSR_REG_RW +#define DBG_PHYA_M3CTI_CTIOUTEN3___POR 0x00000000 +#define DBG_PHYA_M3CTI_CTIOUTEN3__TRIGOUTEN___POR 0x00 +#define DBG_PHYA_M3CTI_CTIOUTEN3__TRIGOUTEN___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIOUTEN3__TRIGOUTEN___S 0 +#define DBG_PHYA_M3CTI_CTIOUTEN3___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIOUTEN3___S 0 + +#define DBG_PHYA_M3CTI_CTIOUTEN4 (0x00BED0B0) +#define DBG_PHYA_M3CTI_CTIOUTEN4___RWC QCSR_REG_RW +#define DBG_PHYA_M3CTI_CTIOUTEN4___POR 0x00000000 +#define DBG_PHYA_M3CTI_CTIOUTEN4__TRIGOUTEN___POR 0x00 +#define DBG_PHYA_M3CTI_CTIOUTEN4__TRIGOUTEN___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIOUTEN4__TRIGOUTEN___S 0 +#define DBG_PHYA_M3CTI_CTIOUTEN4___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIOUTEN4___S 0 + +#define DBG_PHYA_M3CTI_CTIOUTEN5 (0x00BED0B4) +#define DBG_PHYA_M3CTI_CTIOUTEN5___RWC QCSR_REG_RW +#define DBG_PHYA_M3CTI_CTIOUTEN5___POR 0x00000000 +#define DBG_PHYA_M3CTI_CTIOUTEN5__TRIGOUTEN___POR 0x00 +#define DBG_PHYA_M3CTI_CTIOUTEN5__TRIGOUTEN___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIOUTEN5__TRIGOUTEN___S 0 +#define DBG_PHYA_M3CTI_CTIOUTEN5___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIOUTEN5___S 0 + +#define DBG_PHYA_M3CTI_CTIOUTEN6 (0x00BED0B8) +#define DBG_PHYA_M3CTI_CTIOUTEN6___RWC QCSR_REG_RW +#define DBG_PHYA_M3CTI_CTIOUTEN6___POR 0x00000000 +#define DBG_PHYA_M3CTI_CTIOUTEN6__TRIGOUTEN___POR 0x00 +#define DBG_PHYA_M3CTI_CTIOUTEN6__TRIGOUTEN___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIOUTEN6__TRIGOUTEN___S 0 +#define DBG_PHYA_M3CTI_CTIOUTEN6___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIOUTEN6___S 0 + +#define DBG_PHYA_M3CTI_CTIOUTEN7 (0x00BED0BC) +#define DBG_PHYA_M3CTI_CTIOUTEN7___RWC QCSR_REG_RW +#define DBG_PHYA_M3CTI_CTIOUTEN7___POR 0x00000000 +#define DBG_PHYA_M3CTI_CTIOUTEN7__TRIGOUTEN___POR 0x00 +#define DBG_PHYA_M3CTI_CTIOUTEN7__TRIGOUTEN___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIOUTEN7__TRIGOUTEN___S 0 +#define DBG_PHYA_M3CTI_CTIOUTEN7___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIOUTEN7___S 0 + +#define DBG_PHYA_M3CTI_CTITRIGINSTATUS (0x00BED130) +#define DBG_PHYA_M3CTI_CTITRIGINSTATUS___RWC QCSR_REG_RO +#define DBG_PHYA_M3CTI_CTITRIGINSTATUS__TRIGINSTATUS___M 0x000000FF +#define DBG_PHYA_M3CTI_CTITRIGINSTATUS__TRIGINSTATUS___S 0 +#define DBG_PHYA_M3CTI_CTITRIGINSTATUS___M 0x000000FF +#define DBG_PHYA_M3CTI_CTITRIGINSTATUS___S 0 + +#define DBG_PHYA_M3CTI_CTITRIGOUTSTATUS (0x00BED134) +#define DBG_PHYA_M3CTI_CTITRIGOUTSTATUS___RWC QCSR_REG_RO +#define DBG_PHYA_M3CTI_CTITRIGOUTSTATUS___POR 0x00000000 +#define DBG_PHYA_M3CTI_CTITRIGOUTSTATUS__TRIGOUTSTATUS___POR 0x00 +#define DBG_PHYA_M3CTI_CTITRIGOUTSTATUS__TRIGOUTSTATUS___M 0x000000FF +#define DBG_PHYA_M3CTI_CTITRIGOUTSTATUS__TRIGOUTSTATUS___S 0 +#define DBG_PHYA_M3CTI_CTITRIGOUTSTATUS___M 0x000000FF +#define DBG_PHYA_M3CTI_CTITRIGOUTSTATUS___S 0 + +#define DBG_PHYA_M3CTI_CTICHINSTATUS (0x00BED138) +#define DBG_PHYA_M3CTI_CTICHINSTATUS___RWC QCSR_REG_RO +#define DBG_PHYA_M3CTI_CTICHINSTATUS__CTICHINSTATUS___M 0x000000FF +#define DBG_PHYA_M3CTI_CTICHINSTATUS__CTICHINSTATUS___S 0 +#define DBG_PHYA_M3CTI_CTICHINSTATUS___M 0x000000FF +#define DBG_PHYA_M3CTI_CTICHINSTATUS___S 0 + +#define DBG_PHYA_M3CTI_CTICHOUTSTATUS (0x00BED13C) +#define DBG_PHYA_M3CTI_CTICHOUTSTATUS___RWC QCSR_REG_RO +#define DBG_PHYA_M3CTI_CTICHOUTSTATUS___POR 0x00000000 +#define DBG_PHYA_M3CTI_CTICHOUTSTATUS__CTICHOUTSTATUS___POR 0x00 +#define DBG_PHYA_M3CTI_CTICHOUTSTATUS__CTICHOUTSTATUS___M 0x000000FF +#define DBG_PHYA_M3CTI_CTICHOUTSTATUS__CTICHOUTSTATUS___S 0 +#define DBG_PHYA_M3CTI_CTICHOUTSTATUS___M 0x000000FF +#define DBG_PHYA_M3CTI_CTICHOUTSTATUS___S 0 + +#define DBG_PHYA_M3CTI_CTIGATE (0x00BED140) +#define DBG_PHYA_M3CTI_CTIGATE___RWC QCSR_REG_RW +#define DBG_PHYA_M3CTI_CTIGATE___POR 0x000000FF +#define DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN7___POR 0x1 +#define DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN6___POR 0x1 +#define DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN5___POR 0x1 +#define DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN4___POR 0x1 +#define DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN3___POR 0x1 +#define DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN2___POR 0x1 +#define DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN1___POR 0x1 +#define DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN0___POR 0x1 +#define DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN7___M 0x00000080 +#define DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN7___S 7 +#define DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN6___M 0x00000040 +#define DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN6___S 6 +#define DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN5___M 0x00000020 +#define DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN5___S 5 +#define DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN4___M 0x00000010 +#define DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN4___S 4 +#define DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN3___M 0x00000008 +#define DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN3___S 3 +#define DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN2___M 0x00000004 +#define DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN2___S 2 +#define DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN1___M 0x00000002 +#define DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN1___S 1 +#define DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN0___M 0x00000001 +#define DBG_PHYA_M3CTI_CTIGATE__CTIGATEEN0___S 0 +#define DBG_PHYA_M3CTI_CTIGATE___M 0x000000FF +#define DBG_PHYA_M3CTI_CTIGATE___S 0 + +#define DBG_PHYA_M3CTI_ASICCTL (0x00BED144) +#define DBG_PHYA_M3CTI_ASICCTL___RWC QCSR_REG_RW +#define DBG_PHYA_M3CTI_ASICCTL___POR 0x00000000 +#define DBG_PHYA_M3CTI_ASICCTL__ASICCTL___POR 0x00000000 +#define DBG_PHYA_M3CTI_ASICCTL__ASICCTL___M 0xFFFFFFFF +#define DBG_PHYA_M3CTI_ASICCTL__ASICCTL___S 0 +#define DBG_PHYA_M3CTI_ASICCTL___M 0xFFFFFFFF +#define DBG_PHYA_M3CTI_ASICCTL___S 0 + +#define DBG_PHYA_M3CTI_ITCHINACK (0x00BEDEDC) +#define DBG_PHYA_M3CTI_ITCHINACK___RWC QCSR_REG_WO +#define DBG_PHYA_M3CTI_ITCHINACK___POR 0x00000000 +#define DBG_PHYA_M3CTI_ITCHINACK__CTCHINACK___POR 0x00 +#define DBG_PHYA_M3CTI_ITCHINACK__CTCHINACK___M 0x000000FF +#define DBG_PHYA_M3CTI_ITCHINACK__CTCHINACK___S 0 +#define DBG_PHYA_M3CTI_ITCHINACK___M 0x000000FF +#define DBG_PHYA_M3CTI_ITCHINACK___S 0 + +#define DBG_PHYA_M3CTI_ITTRIGINACK (0x00BEDEE0) +#define DBG_PHYA_M3CTI_ITTRIGINACK___RWC QCSR_REG_WO +#define DBG_PHYA_M3CTI_ITTRIGINACK___POR 0x00000000 +#define DBG_PHYA_M3CTI_ITTRIGINACK__CTTRIGINACK___POR 0x00 +#define DBG_PHYA_M3CTI_ITTRIGINACK__CTTRIGINACK___M 0x000000FF +#define DBG_PHYA_M3CTI_ITTRIGINACK__CTTRIGINACK___S 0 +#define DBG_PHYA_M3CTI_ITTRIGINACK___M 0x000000FF +#define DBG_PHYA_M3CTI_ITTRIGINACK___S 0 + +#define DBG_PHYA_M3CTI_ITCHOUT (0x00BEDEE4) +#define DBG_PHYA_M3CTI_ITCHOUT___RWC QCSR_REG_WO +#define DBG_PHYA_M3CTI_ITCHOUT___POR 0x00000000 +#define DBG_PHYA_M3CTI_ITCHOUT__CTCHOUT___POR 0x00 +#define DBG_PHYA_M3CTI_ITCHOUT__CTCHOUT___M 0x000000FF +#define DBG_PHYA_M3CTI_ITCHOUT__CTCHOUT___S 0 +#define DBG_PHYA_M3CTI_ITCHOUT___M 0x000000FF +#define DBG_PHYA_M3CTI_ITCHOUT___S 0 + +#define DBG_PHYA_M3CTI_ITTRIGOUT (0x00BEDEE8) +#define DBG_PHYA_M3CTI_ITTRIGOUT___RWC QCSR_REG_WO +#define DBG_PHYA_M3CTI_ITTRIGOUT___POR 0x00000000 +#define DBG_PHYA_M3CTI_ITTRIGOUT__CTTRIGOUT___POR 0x00 +#define DBG_PHYA_M3CTI_ITTRIGOUT__CTTRIGOUT___M 0x000000FF +#define DBG_PHYA_M3CTI_ITTRIGOUT__CTTRIGOUT___S 0 +#define DBG_PHYA_M3CTI_ITTRIGOUT___M 0x000000FF +#define DBG_PHYA_M3CTI_ITTRIGOUT___S 0 + +#define DBG_PHYA_M3CTI_ITCHOUTACK (0x00BEDEEC) +#define DBG_PHYA_M3CTI_ITCHOUTACK___RWC QCSR_REG_RO +#define DBG_PHYA_M3CTI_ITCHOUTACK___POR 0x00000000 +#define DBG_PHYA_M3CTI_ITCHOUTACK__CTCHOUTACK___POR 0x00 +#define DBG_PHYA_M3CTI_ITCHOUTACK__CTCHOUTACK___M 0x000000FF +#define DBG_PHYA_M3CTI_ITCHOUTACK__CTCHOUTACK___S 0 +#define DBG_PHYA_M3CTI_ITCHOUTACK___M 0x000000FF +#define DBG_PHYA_M3CTI_ITCHOUTACK___S 0 + +#define DBG_PHYA_M3CTI_ITTRIGOUTACK (0x00BEDEF0) +#define DBG_PHYA_M3CTI_ITTRIGOUTACK___RWC QCSR_REG_RO +#define DBG_PHYA_M3CTI_ITTRIGOUTACK___POR 0x00000000 +#define DBG_PHYA_M3CTI_ITTRIGOUTACK__CTTRIGOUTACK___POR 0x00 +#define DBG_PHYA_M3CTI_ITTRIGOUTACK__CTTRIGOUTACK___M 0x000000FF +#define DBG_PHYA_M3CTI_ITTRIGOUTACK__CTTRIGOUTACK___S 0 +#define DBG_PHYA_M3CTI_ITTRIGOUTACK___M 0x000000FF +#define DBG_PHYA_M3CTI_ITTRIGOUTACK___S 0 + +#define DBG_PHYA_M3CTI_ITCHIN (0x00BEDEF4) +#define DBG_PHYA_M3CTI_ITCHIN___RWC QCSR_REG_RO +#define DBG_PHYA_M3CTI_ITCHIN___POR 0x00000000 +#define DBG_PHYA_M3CTI_ITCHIN__CTCHIN___POR 0x00 +#define DBG_PHYA_M3CTI_ITCHIN__CTCHIN___M 0x000000FF +#define DBG_PHYA_M3CTI_ITCHIN__CTCHIN___S 0 +#define DBG_PHYA_M3CTI_ITCHIN___M 0x000000FF +#define DBG_PHYA_M3CTI_ITCHIN___S 0 + +#define DBG_PHYA_M3CTI_ITTRIGIN (0x00BEDEF8) +#define DBG_PHYA_M3CTI_ITTRIGIN___RWC QCSR_REG_RO +#define DBG_PHYA_M3CTI_ITTRIGIN___POR 0x00000000 +#define DBG_PHYA_M3CTI_ITTRIGIN__CTTRIGIN___POR 0x00 +#define DBG_PHYA_M3CTI_ITTRIGIN__CTTRIGIN___M 0x000000FF +#define DBG_PHYA_M3CTI_ITTRIGIN__CTTRIGIN___S 0 +#define DBG_PHYA_M3CTI_ITTRIGIN___M 0x000000FF +#define DBG_PHYA_M3CTI_ITTRIGIN___S 0 + +#define DBG_PHYA_M3CTI_ITCTRL (0x00BEDF00) +#define DBG_PHYA_M3CTI_ITCTRL___RWC QCSR_REG_RW +#define DBG_PHYA_M3CTI_ITCTRL___POR 0x00000000 +#define DBG_PHYA_M3CTI_ITCTRL__INTEGRATION_MODE___POR 0x0 +#define DBG_PHYA_M3CTI_ITCTRL__INTEGRATION_MODE___M 0x00000001 +#define DBG_PHYA_M3CTI_ITCTRL__INTEGRATION_MODE___S 0 +#define DBG_PHYA_M3CTI_ITCTRL__INTEGRATION_MODE__FUNCTIONAL_MODE 0x0 +#define DBG_PHYA_M3CTI_ITCTRL__INTEGRATION_MODE__INTEGRATION_MODE 0x1 +#define DBG_PHYA_M3CTI_ITCTRL___M 0x00000001 +#define DBG_PHYA_M3CTI_ITCTRL___S 0 + +#define DBG_PHYA_M3CTI_CLAIMSET (0x00BEDFA0) +#define DBG_PHYA_M3CTI_CLAIMSET___RWC QCSR_REG_RW +#define DBG_PHYA_M3CTI_CLAIMSET___POR 0x0000000F +#define DBG_PHYA_M3CTI_CLAIMSET__CLAIMSET___POR 0xF +#define DBG_PHYA_M3CTI_CLAIMSET__CLAIMSET___M 0x0000000F +#define DBG_PHYA_M3CTI_CLAIMSET__CLAIMSET___S 0 +#define DBG_PHYA_M3CTI_CLAIMSET__CLAIMSET__CLAIM_TAG_IMPLEMENTED_BITS 0xF +#define DBG_PHYA_M3CTI_CLAIMSET___M 0x0000000F +#define DBG_PHYA_M3CTI_CLAIMSET___S 0 + +#define DBG_PHYA_M3CTI_CLAIMCLR (0x00BEDFA4) +#define DBG_PHYA_M3CTI_CLAIMCLR___RWC QCSR_REG_RW +#define DBG_PHYA_M3CTI_CLAIMCLR___POR 0x00000000 +#define DBG_PHYA_M3CTI_CLAIMCLR__CLAIMCLR___POR 0x0 +#define DBG_PHYA_M3CTI_CLAIMCLR__CLAIMCLR___M 0x0000000F +#define DBG_PHYA_M3CTI_CLAIMCLR__CLAIMCLR___S 0 +#define DBG_PHYA_M3CTI_CLAIMCLR___M 0x0000000F +#define DBG_PHYA_M3CTI_CLAIMCLR___S 0 + +#define DBG_PHYA_M3CTI_DEVAFF0 (0x00BEDFA8) +#define DBG_PHYA_M3CTI_DEVAFF0___RWC QCSR_REG_RO +#define DBG_PHYA_M3CTI_DEVAFF0___POR 0x00000000 +#define DBG_PHYA_M3CTI_DEVAFF0__VAL___POR 0x00000000 +#define DBG_PHYA_M3CTI_DEVAFF0__VAL___M 0xFFFFFFFF +#define DBG_PHYA_M3CTI_DEVAFF0__VAL___S 0 +#define DBG_PHYA_M3CTI_DEVAFF0___M 0xFFFFFFFF +#define DBG_PHYA_M3CTI_DEVAFF0___S 0 + +#define DBG_PHYA_M3CTI_DEVAFF1 (0x00BEDFAC) +#define DBG_PHYA_M3CTI_DEVAFF1___RWC QCSR_REG_RO +#define DBG_PHYA_M3CTI_DEVAFF1___POR 0x00000000 +#define DBG_PHYA_M3CTI_DEVAFF1__VAL___POR 0x00000000 +#define DBG_PHYA_M3CTI_DEVAFF1__VAL___M 0xFFFFFFFF +#define DBG_PHYA_M3CTI_DEVAFF1__VAL___S 0 +#define DBG_PHYA_M3CTI_DEVAFF1___M 0xFFFFFFFF +#define DBG_PHYA_M3CTI_DEVAFF1___S 0 + +#define DBG_PHYA_M3CTI_LAR (0x00BEDFB0) +#define DBG_PHYA_M3CTI_LAR___RWC QCSR_REG_WO +#define DBG_PHYA_M3CTI_LAR__ACCESS_W___M 0xFFFFFFFF +#define DBG_PHYA_M3CTI_LAR__ACCESS_W___S 0 +#define DBG_PHYA_M3CTI_LAR__ACCESS_W__UNLOCK 0xC5ACCE55 +#define DBG_PHYA_M3CTI_LAR___M 0xFFFFFFFF +#define DBG_PHYA_M3CTI_LAR___S 0 + +#define DBG_PHYA_M3CTI_LSR (0x00BEDFB4) +#define DBG_PHYA_M3CTI_LSR___RWC QCSR_REG_RO +#define DBG_PHYA_M3CTI_LSR___POR 0x00000003 +#define DBG_PHYA_M3CTI_LSR__LOCKTYPE___POR 0x0 +#define DBG_PHYA_M3CTI_LSR__LOCKGRANT___POR 0x1 +#define DBG_PHYA_M3CTI_LSR__LOCKEXIST___POR 0x1 +#define DBG_PHYA_M3CTI_LSR__LOCKTYPE___M 0x00000004 +#define DBG_PHYA_M3CTI_LSR__LOCKTYPE___S 2 +#define DBG_PHYA_M3CTI_LSR__LOCKTYPE__SIZE_32BIT 0x0 +#define DBG_PHYA_M3CTI_LSR__LOCKGRANT___M 0x00000002 +#define DBG_PHYA_M3CTI_LSR__LOCKGRANT___S 1 +#define DBG_PHYA_M3CTI_LSR__LOCKGRANT__ACCESS_PERMITTED 0x0 +#define DBG_PHYA_M3CTI_LSR__LOCKGRANT__DEVICE_LOCKED 0x1 +#define DBG_PHYA_M3CTI_LSR__LOCKEXIST___M 0x00000001 +#define DBG_PHYA_M3CTI_LSR__LOCKEXIST___S 0 +#define DBG_PHYA_M3CTI_LSR__LOCKEXIST__LOCK_NOT_PRESENT 0x0 +#define DBG_PHYA_M3CTI_LSR__LOCKEXIST__LOCK_PRESENT 0x1 +#define DBG_PHYA_M3CTI_LSR___M 0x00000007 +#define DBG_PHYA_M3CTI_LSR___S 0 + +#define DBG_PHYA_M3CTI_AUTHSTATUS (0x00BEDFB8) +#define DBG_PHYA_M3CTI_AUTHSTATUS___RWC QCSR_REG_RO +#define DBG_PHYA_M3CTI_AUTHSTATUS__SNID___M 0x000000C0 +#define DBG_PHYA_M3CTI_AUTHSTATUS__SNID___S 6 +#define DBG_PHYA_M3CTI_AUTHSTATUS__SNID__NOT_IMPLEMENTED 0x0 +#define DBG_PHYA_M3CTI_AUTHSTATUS__SID___M 0x00000030 +#define DBG_PHYA_M3CTI_AUTHSTATUS__SID___S 4 +#define DBG_PHYA_M3CTI_AUTHSTATUS__SID__NOT_IMPLEMENTED 0x0 +#define DBG_PHYA_M3CTI_AUTHSTATUS__NSNID___M 0x0000000C +#define DBG_PHYA_M3CTI_AUTHSTATUS__NSNID___S 2 +#define DBG_PHYA_M3CTI_AUTHSTATUS__NSNID__DISABLED 0x2 +#define DBG_PHYA_M3CTI_AUTHSTATUS__NSNID__ENABLED 0x3 +#define DBG_PHYA_M3CTI_AUTHSTATUS__NSID___M 0x00000003 +#define DBG_PHYA_M3CTI_AUTHSTATUS__NSID___S 0 +#define DBG_PHYA_M3CTI_AUTHSTATUS__NSID__DISABLED 0x2 +#define DBG_PHYA_M3CTI_AUTHSTATUS__NSID__ENABLED 0x3 +#define DBG_PHYA_M3CTI_AUTHSTATUS___M 0x000000FF +#define DBG_PHYA_M3CTI_AUTHSTATUS___S 0 + +#define DBG_PHYA_M3CTI_DEVARCH (0x00BEDFBC) +#define DBG_PHYA_M3CTI_DEVARCH___RWC QCSR_REG_RO +#define DBG_PHYA_M3CTI_DEVARCH___POR 0x8EF00A14 +#define DBG_PHYA_M3CTI_DEVARCH__ARCHITECT___POR 0x477 +#define DBG_PHYA_M3CTI_DEVARCH__PRESENT___POR 0x1 +#define DBG_PHYA_M3CTI_DEVARCH__REVISION___POR 0x0 +#define DBG_PHYA_M3CTI_DEVARCH__ARCHID___POR 0x0A14 +#define DBG_PHYA_M3CTI_DEVARCH__ARCHITECT___M 0xFFE00000 +#define DBG_PHYA_M3CTI_DEVARCH__ARCHITECT___S 21 +#define DBG_PHYA_M3CTI_DEVARCH__PRESENT___M 0x00100000 +#define DBG_PHYA_M3CTI_DEVARCH__PRESENT___S 20 +#define DBG_PHYA_M3CTI_DEVARCH__REVISION___M 0x000F0000 +#define DBG_PHYA_M3CTI_DEVARCH__REVISION___S 16 +#define DBG_PHYA_M3CTI_DEVARCH__ARCHID___M 0x0000FFFF +#define DBG_PHYA_M3CTI_DEVARCH__ARCHID___S 0 +#define DBG_PHYA_M3CTI_DEVARCH___M 0xFFFFFFFF +#define DBG_PHYA_M3CTI_DEVARCH___S 0 + +#define DBG_PHYA_M3CTI_DEVID2 (0x00BEDFC0) +#define DBG_PHYA_M3CTI_DEVID2___RWC QCSR_REG_RO +#define DBG_PHYA_M3CTI_DEVID2___POR 0x00000000 +#define DBG_PHYA_M3CTI_DEVID2__IMPLDEF___POR 0x0 +#define DBG_PHYA_M3CTI_DEVID2__IMPLDEF___M 0x00000001 +#define DBG_PHYA_M3CTI_DEVID2__IMPLDEF___S 0 +#define DBG_PHYA_M3CTI_DEVID2___M 0x00000001 +#define DBG_PHYA_M3CTI_DEVID2___S 0 + +#define DBG_PHYA_M3CTI_DEVID1 (0x00BEDFC4) +#define DBG_PHYA_M3CTI_DEVID1___RWC QCSR_REG_RO +#define DBG_PHYA_M3CTI_DEVID1___POR 0x00000000 +#define DBG_PHYA_M3CTI_DEVID1__IMPLDEF___POR 0x0 +#define DBG_PHYA_M3CTI_DEVID1__IMPLDEF___M 0x00000001 +#define DBG_PHYA_M3CTI_DEVID1__IMPLDEF___S 0 +#define DBG_PHYA_M3CTI_DEVID1___M 0x00000001 +#define DBG_PHYA_M3CTI_DEVID1___S 0 + +#define DBG_PHYA_M3CTI_DEVID (0x00BEDFC8) +#define DBG_PHYA_M3CTI_DEVID___RWC QCSR_REG_RO +#define DBG_PHYA_M3CTI_DEVID___POR 0x00080800 +#define DBG_PHYA_M3CTI_DEVID__NUMCH___POR 0x8 +#define DBG_PHYA_M3CTI_DEVID__NUMTRIG___POR 0x8 +#define DBG_PHYA_M3CTI_DEVID__EXTMUXNUM___POR 0x00 +#define DBG_PHYA_M3CTI_DEVID__NUMCH___M 0x003F0000 +#define DBG_PHYA_M3CTI_DEVID__NUMCH___S 16 +#define DBG_PHYA_M3CTI_DEVID__NUMTRIG___M 0x0000FF00 +#define DBG_PHYA_M3CTI_DEVID__NUMTRIG___S 8 +#define DBG_PHYA_M3CTI_DEVID__EXTMUXNUM___M 0x0000001F +#define DBG_PHYA_M3CTI_DEVID__EXTMUXNUM___S 0 +#define DBG_PHYA_M3CTI_DEVID___M 0x003FFF1F +#define DBG_PHYA_M3CTI_DEVID___S 0 + +#define DBG_PHYA_M3CTI_DEVTYPE (0x00BEDFCC) +#define DBG_PHYA_M3CTI_DEVTYPE___RWC QCSR_REG_RO +#define DBG_PHYA_M3CTI_DEVTYPE___POR 0x00000014 +#define DBG_PHYA_M3CTI_DEVTYPE__SUB_TYPE___POR 0x1 +#define DBG_PHYA_M3CTI_DEVTYPE__MAJOR_TYPE___POR 0x4 +#define DBG_PHYA_M3CTI_DEVTYPE__SUB_TYPE___M 0x000000F0 +#define DBG_PHYA_M3CTI_DEVTYPE__SUB_TYPE___S 4 +#define DBG_PHYA_M3CTI_DEVTYPE__SUB_TYPE__TRIGGER_MATRIX 0x1 +#define DBG_PHYA_M3CTI_DEVTYPE__MAJOR_TYPE___M 0x0000000F +#define DBG_PHYA_M3CTI_DEVTYPE__MAJOR_TYPE___S 0 +#define DBG_PHYA_M3CTI_DEVTYPE__MAJOR_TYPE__DEBUG_CONTROL 0x4 +#define DBG_PHYA_M3CTI_DEVTYPE___M 0x000000FF +#define DBG_PHYA_M3CTI_DEVTYPE___S 0 + +#define DBG_PHYA_M3CTI_PIDR0 (0x00BEDFE0) +#define DBG_PHYA_M3CTI_PIDR0___RWC QCSR_REG_RO +#define DBG_PHYA_M3CTI_PIDR0___POR 0x00000006 +#define DBG_PHYA_M3CTI_PIDR0__PART_0___POR 0x06 +#define DBG_PHYA_M3CTI_PIDR0__PART_0___M 0x000000FF +#define DBG_PHYA_M3CTI_PIDR0__PART_0___S 0 +#define DBG_PHYA_M3CTI_PIDR0__PART_0__CTI_PART_NUMBER_7_0 0x06 +#define DBG_PHYA_M3CTI_PIDR0___M 0x000000FF +#define DBG_PHYA_M3CTI_PIDR0___S 0 + +#define DBG_PHYA_M3CTI_PIDR1 (0x00BEDFE4) +#define DBG_PHYA_M3CTI_PIDR1___RWC QCSR_REG_RO +#define DBG_PHYA_M3CTI_PIDR1___POR 0x000000B9 +#define DBG_PHYA_M3CTI_PIDR1__DES_0___POR 0xB +#define DBG_PHYA_M3CTI_PIDR1__PART_1___POR 0x9 +#define DBG_PHYA_M3CTI_PIDR1__DES_0___M 0x000000F0 +#define DBG_PHYA_M3CTI_PIDR1__DES_0___S 4 +#define DBG_PHYA_M3CTI_PIDR1__DES_0__ARM_JEP106_IDENTITY_CODE_3_0 0xB +#define DBG_PHYA_M3CTI_PIDR1__PART_1___M 0x0000000F +#define DBG_PHYA_M3CTI_PIDR1__PART_1___S 0 +#define DBG_PHYA_M3CTI_PIDR1__PART_1__CTI_PART_NUMBER_11_8 0x9 +#define DBG_PHYA_M3CTI_PIDR1___M 0x000000FF +#define DBG_PHYA_M3CTI_PIDR1___S 0 + +#define DBG_PHYA_M3CTI_PIDR2 (0x00BEDFE8) +#define DBG_PHYA_M3CTI_PIDR2___RWC QCSR_REG_RO +#define DBG_PHYA_M3CTI_PIDR2___POR 0x0000004B +#define DBG_PHYA_M3CTI_PIDR2__REVISION___POR 0x4 +#define DBG_PHYA_M3CTI_PIDR2__JEDEC___POR 0x1 +#define DBG_PHYA_M3CTI_PIDR2__DES_1___POR 0x3 +#define DBG_PHYA_M3CTI_PIDR2__REVISION___M 0x000000F0 +#define DBG_PHYA_M3CTI_PIDR2__REVISION___S 4 +#define DBG_PHYA_M3CTI_PIDR2__REVISION__R0P4 0x4 +#define DBG_PHYA_M3CTI_PIDR2__REVISION__R0P5 0x5 +#define DBG_PHYA_M3CTI_PIDR2__JEDEC___M 0x00000008 +#define DBG_PHYA_M3CTI_PIDR2__JEDEC___S 3 +#define DBG_PHYA_M3CTI_PIDR2__JEDEC__JEDEC_IDENTITY 0x1 +#define DBG_PHYA_M3CTI_PIDR2__DES_1___M 0x00000007 +#define DBG_PHYA_M3CTI_PIDR2__DES_1___S 0 +#define DBG_PHYA_M3CTI_PIDR2__DES_1__ARM_JEP106_IDENTITY_CODE_6_4 0x3 +#define DBG_PHYA_M3CTI_PIDR2___M 0x000000FF +#define DBG_PHYA_M3CTI_PIDR2___S 0 + +#define DBG_PHYA_M3CTI_PIDR3 (0x00BEDFEC) +#define DBG_PHYA_M3CTI_PIDR3___RWC QCSR_REG_RO +#define DBG_PHYA_M3CTI_PIDR3___POR 0x00000000 +#define DBG_PHYA_M3CTI_PIDR3__REVAND___POR 0x0 +#define DBG_PHYA_M3CTI_PIDR3__CMOD___POR 0x0 +#define DBG_PHYA_M3CTI_PIDR3__REVAND___M 0x000000F0 +#define DBG_PHYA_M3CTI_PIDR3__REVAND___S 4 +#define DBG_PHYA_M3CTI_PIDR3__REVAND__NO_MODIFICATION 0x0 +#define DBG_PHYA_M3CTI_PIDR3__CMOD___M 0x0000000F +#define DBG_PHYA_M3CTI_PIDR3__CMOD___S 0 +#define DBG_PHYA_M3CTI_PIDR3__CMOD__NO_MODIFICATION 0x0 +#define DBG_PHYA_M3CTI_PIDR3___M 0x000000FF +#define DBG_PHYA_M3CTI_PIDR3___S 0 + +#define DBG_PHYA_M3CTI_PIDR4 (0x00BEDFD0) +#define DBG_PHYA_M3CTI_PIDR4___RWC QCSR_REG_RO +#define DBG_PHYA_M3CTI_PIDR4___POR 0x00000004 +#define DBG_PHYA_M3CTI_PIDR4__SIZE___POR 0x0 +#define DBG_PHYA_M3CTI_PIDR4__DES_2___POR 0x4 +#define DBG_PHYA_M3CTI_PIDR4__SIZE___M 0x000000F0 +#define DBG_PHYA_M3CTI_PIDR4__SIZE___S 4 +#define DBG_PHYA_M3CTI_PIDR4__SIZE__SIZE_4KB 0x0 +#define DBG_PHYA_M3CTI_PIDR4__DES_2___M 0x0000000F +#define DBG_PHYA_M3CTI_PIDR4__DES_2___S 0 +#define DBG_PHYA_M3CTI_PIDR4__DES_2__ARM_JEP106_CONTINUATION_CODE 0x4 +#define DBG_PHYA_M3CTI_PIDR4___M 0x000000FF +#define DBG_PHYA_M3CTI_PIDR4___S 0 + +#define DBG_PHYA_M3CTI_PIDR5 (0x00BEDFD4) +#define DBG_PHYA_M3CTI_PIDR5___RWC QCSR_REG_RW +#define DBG_PHYA_M3CTI_PIDR5__PERIPHID5___M 0xFFFFFFFF +#define DBG_PHYA_M3CTI_PIDR5__PERIPHID5___S 0 +#define DBG_PHYA_M3CTI_PIDR5___M 0xFFFFFFFF +#define DBG_PHYA_M3CTI_PIDR5___S 0 + +#define DBG_PHYA_M3CTI_PIDR6 (0x00BEDFD8) +#define DBG_PHYA_M3CTI_PIDR6___RWC QCSR_REG_RW +#define DBG_PHYA_M3CTI_PIDR6__PERIPHID6___M 0xFFFFFFFF +#define DBG_PHYA_M3CTI_PIDR6__PERIPHID6___S 0 +#define DBG_PHYA_M3CTI_PIDR6___M 0xFFFFFFFF +#define DBG_PHYA_M3CTI_PIDR6___S 0 + +#define DBG_PHYA_M3CTI_PIDR7 (0x00BEDFDC) +#define DBG_PHYA_M3CTI_PIDR7___RWC QCSR_REG_RW +#define DBG_PHYA_M3CTI_PIDR7__PERIPHID7___M 0xFFFFFFFF +#define DBG_PHYA_M3CTI_PIDR7__PERIPHID7___S 0 +#define DBG_PHYA_M3CTI_PIDR7___M 0xFFFFFFFF +#define DBG_PHYA_M3CTI_PIDR7___S 0 + +#define DBG_PHYA_M3CTI_CIDR0 (0x00BEDFF0) +#define DBG_PHYA_M3CTI_CIDR0___RWC QCSR_REG_RO +#define DBG_PHYA_M3CTI_CIDR0___POR 0x0000000D +#define DBG_PHYA_M3CTI_CIDR0__PRMBL_0___POR 0x0D +#define DBG_PHYA_M3CTI_CIDR0__PRMBL_0___M 0x000000FF +#define DBG_PHYA_M3CTI_CIDR0__PRMBL_0___S 0 +#define DBG_PHYA_M3CTI_CIDR0__PRMBL_0__ID_VALUE_0D 0x0D +#define DBG_PHYA_M3CTI_CIDR0___M 0x000000FF +#define DBG_PHYA_M3CTI_CIDR0___S 0 + +#define DBG_PHYA_M3CTI_CIDR1 (0x00BEDFF4) +#define DBG_PHYA_M3CTI_CIDR1___RWC QCSR_REG_RO +#define DBG_PHYA_M3CTI_CIDR1___POR 0x00000090 +#define DBG_PHYA_M3CTI_CIDR1__CLASS___POR 0x9 +#define DBG_PHYA_M3CTI_CIDR1__PRMBL_1___POR 0x0 +#define DBG_PHYA_M3CTI_CIDR1__CLASS___M 0x000000F0 +#define DBG_PHYA_M3CTI_CIDR1__CLASS___S 4 +#define DBG_PHYA_M3CTI_CIDR1__CLASS__CORESIGHT_COMPONENT 0x9 +#define DBG_PHYA_M3CTI_CIDR1__PRMBL_1___M 0x0000000F +#define DBG_PHYA_M3CTI_CIDR1__PRMBL_1___S 0 +#define DBG_PHYA_M3CTI_CIDR1__PRMBL_1__ID_VALUE_0 0x0 +#define DBG_PHYA_M3CTI_CIDR1___M 0x000000FF +#define DBG_PHYA_M3CTI_CIDR1___S 0 + +#define DBG_PHYA_M3CTI_CIDR2 (0x00BEDFF8) +#define DBG_PHYA_M3CTI_CIDR2___RWC QCSR_REG_RO +#define DBG_PHYA_M3CTI_CIDR2___POR 0x00000005 +#define DBG_PHYA_M3CTI_CIDR2__PRMBL_2___POR 0x05 +#define DBG_PHYA_M3CTI_CIDR2__PRMBL_2___M 0x000000FF +#define DBG_PHYA_M3CTI_CIDR2__PRMBL_2___S 0 +#define DBG_PHYA_M3CTI_CIDR2__PRMBL_2__ID_VALUE_05 0x05 +#define DBG_PHYA_M3CTI_CIDR2___M 0x000000FF +#define DBG_PHYA_M3CTI_CIDR2___S 0 + +#define DBG_PHYA_M3CTI_CIDR3 (0x00BEDFFC) +#define DBG_PHYA_M3CTI_CIDR3___RWC QCSR_REG_RO +#define DBG_PHYA_M3CTI_CIDR3___POR 0x000000B1 +#define DBG_PHYA_M3CTI_CIDR3__PRMBL_3___POR 0xB1 +#define DBG_PHYA_M3CTI_CIDR3__PRMBL_3___M 0x000000FF +#define DBG_PHYA_M3CTI_CIDR3__PRMBL_3___S 0 +#define DBG_PHYA_M3CTI_CIDR3__PRMBL_3__ID_VALUE_B1 0xB1 +#define DBG_PHYA_M3CTI_CIDR3___M 0x000000FF +#define DBG_PHYA_M3CTI_CIDR3___S 0 + +#define DBG_PHYA_CPU0_CSW (0x00BEE000) +#define DBG_PHYA_CPU0_CSW___RWC QCSR_REG_RW +#define DBG_PHYA_CPU0_CSW___POR 0x23000040 +#define DBG_PHYA_CPU0_CSW__MASTERTYPE___POR 0x1 +#define DBG_PHYA_CPU0_CSW__HPROT_1___POR 0x1 +#define DBG_PHYA_CPU0_CSW__HPROT_0___POR 0x1 +#define DBG_PHYA_CPU0_CSW__MODE___POR 0x0 +#define DBG_PHYA_CPU0_CSW__TRANSINPROG___POR 0x0 +#define DBG_PHYA_CPU0_CSW__DBGSTATUS___POR 0x1 +#define DBG_PHYA_CPU0_CSW__ADDRINC___POR 0x0 +#define DBG_PHYA_CPU0_CSW__SIZE___POR 0x0 +#define DBG_PHYA_CPU0_CSW__MASTERTYPE___M 0x20000000 +#define DBG_PHYA_CPU0_CSW__MASTERTYPE___S 29 +#define DBG_PHYA_CPU0_CSW__MASTERTYPE__CORE 0x0 +#define DBG_PHYA_CPU0_CSW__MASTERTYPE__DEBUG 0x1 +#define DBG_PHYA_CPU0_CSW__HPROT_1___M 0x02000000 +#define DBG_PHYA_CPU0_CSW__HPROT_1___S 25 +#define DBG_PHYA_CPU0_CSW__HPROT_1__USER 0x0 +#define DBG_PHYA_CPU0_CSW__HPROT_1__PRIVILEGED 0x1 +#define DBG_PHYA_CPU0_CSW__HPROT_0___M 0x01000000 +#define DBG_PHYA_CPU0_CSW__HPROT_0___S 24 +#define DBG_PHYA_CPU0_CSW__HPROT_0__DATA 0x1 +#define DBG_PHYA_CPU0_CSW__MODE___M 0x00000F00 +#define DBG_PHYA_CPU0_CSW__MODE___S 8 +#define DBG_PHYA_CPU0_CSW__MODE__NRMLUPDWN 0x0 +#define DBG_PHYA_CPU0_CSW__TRANSINPROG___M 0x00000080 +#define DBG_PHYA_CPU0_CSW__TRANSINPROG___S 7 +#define DBG_PHYA_CPU0_CSW__TRANSINPROG__AHBIDLE 0x0 +#define DBG_PHYA_CPU0_CSW__TRANSINPROG__AHBBUSY 0x1 +#define DBG_PHYA_CPU0_CSW__DBGSTATUS___M 0x00000040 +#define DBG_PHYA_CPU0_CSW__DBGSTATUS___S 6 +#define DBG_PHYA_CPU0_CSW__DBGSTATUS__AHBXFRDIS 0x0 +#define DBG_PHYA_CPU0_CSW__DBGSTATUS__AHBXFREN 0x1 +#define DBG_PHYA_CPU0_CSW__ADDRINC___M 0x00000030 +#define DBG_PHYA_CPU0_CSW__ADDRINC___S 4 +#define DBG_PHYA_CPU0_CSW__ADDRINC__INCROFF 0x0 +#define DBG_PHYA_CPU0_CSW__ADDRINC__INCRSINGLE 0x1 +#define DBG_PHYA_CPU0_CSW__ADDRINC__INCRPCKD 0x2 +#define DBG_PHYA_CPU0_CSW__SIZE___M 0x00000003 +#define DBG_PHYA_CPU0_CSW__SIZE___S 0 +#define DBG_PHYA_CPU0_CSW__SIZE__SZBYTE 0x0 +#define DBG_PHYA_CPU0_CSW__SIZE__SZWORD 0x1 +#define DBG_PHYA_CPU0_CSW__SIZE__SZDWORD 0x2 +#define DBG_PHYA_CPU0_CSW___M 0x23000FF3 +#define DBG_PHYA_CPU0_CSW___S 0 + +#define DBG_PHYA_CPU0_TAR (0x00BEE004) +#define DBG_PHYA_CPU0_TAR___RWC QCSR_REG_RW +#define DBG_PHYA_CPU0_TAR___POR 0x00000000 +#define DBG_PHYA_CPU0_TAR__ADDR___POR 0x00000000 +#define DBG_PHYA_CPU0_TAR__ADDR___M 0xFFFFFFFF +#define DBG_PHYA_CPU0_TAR__ADDR___S 0 +#define DBG_PHYA_CPU0_TAR___M 0xFFFFFFFF +#define DBG_PHYA_CPU0_TAR___S 0 + +#define DBG_PHYA_CPU0_DRW (0x00BEE00C) +#define DBG_PHYA_CPU0_DRW___RWC QCSR_REG_RW +#define DBG_PHYA_CPU0_DRW___POR 0x00000000 +#define DBG_PHYA_CPU0_DRW__DATA___POR 0x00000000 +#define DBG_PHYA_CPU0_DRW__DATA___M 0xFFFFFFFF +#define DBG_PHYA_CPU0_DRW__DATA___S 0 +#define DBG_PHYA_CPU0_DRW___M 0xFFFFFFFF +#define DBG_PHYA_CPU0_DRW___S 0 + +#define DBG_PHYA_CPU0_BD0 (0x00BEE010) +#define DBG_PHYA_CPU0_BD0___RWC QCSR_REG_RW +#define DBG_PHYA_CPU0_BD0___POR 0x00000000 +#define DBG_PHYA_CPU0_BD0__DATA___POR 0x00000000 +#define DBG_PHYA_CPU0_BD0__DATA___M 0xFFFFFFFF +#define DBG_PHYA_CPU0_BD0__DATA___S 0 +#define DBG_PHYA_CPU0_BD0___M 0xFFFFFFFF +#define DBG_PHYA_CPU0_BD0___S 0 + +#define DBG_PHYA_CPU0_BD1 (0x00BEE014) +#define DBG_PHYA_CPU0_BD1___RWC QCSR_REG_RW +#define DBG_PHYA_CPU0_BD1___POR 0x00000000 +#define DBG_PHYA_CPU0_BD1__DATA___POR 0x00000000 +#define DBG_PHYA_CPU0_BD1__DATA___M 0xFFFFFFFF +#define DBG_PHYA_CPU0_BD1__DATA___S 0 +#define DBG_PHYA_CPU0_BD1___M 0xFFFFFFFF +#define DBG_PHYA_CPU0_BD1___S 0 + +#define DBG_PHYA_CPU0_BD2 (0x00BEE018) +#define DBG_PHYA_CPU0_BD2___RWC QCSR_REG_RW +#define DBG_PHYA_CPU0_BD2___POR 0x00000000 +#define DBG_PHYA_CPU0_BD2__DATA___POR 0x00000000 +#define DBG_PHYA_CPU0_BD2__DATA___M 0xFFFFFFFF +#define DBG_PHYA_CPU0_BD2__DATA___S 0 +#define DBG_PHYA_CPU0_BD2___M 0xFFFFFFFF +#define DBG_PHYA_CPU0_BD2___S 0 + +#define DBG_PHYA_CPU0_BD3 (0x00BEE01C) +#define DBG_PHYA_CPU0_BD3___RWC QCSR_REG_RW +#define DBG_PHYA_CPU0_BD3___POR 0x00000000 +#define DBG_PHYA_CPU0_BD3__DATA___POR 0x00000000 +#define DBG_PHYA_CPU0_BD3__DATA___M 0xFFFFFFFF +#define DBG_PHYA_CPU0_BD3__DATA___S 0 +#define DBG_PHYA_CPU0_BD3___M 0xFFFFFFFF +#define DBG_PHYA_CPU0_BD3___S 0 + +#define DBG_PHYA_CPU0_DBGDRAR_ROMBASE (0x00BEE0F8) +#define DBG_PHYA_CPU0_DBGDRAR_ROMBASE___RWC QCSR_REG_RO +#define DBG_PHYA_CPU0_DBGDRAR_ROMBASE___POR 0xE00FF003 +#define DBG_PHYA_CPU0_DBGDRAR_ROMBASE__BASEADDR___POR 0xE00FF +#define DBG_PHYA_CPU0_DBGDRAR_ROMBASE__FORMAT___POR 0x1 +#define DBG_PHYA_CPU0_DBGDRAR_ROMBASE__ENTRYPRESENT___POR 0x1 +#define DBG_PHYA_CPU0_DBGDRAR_ROMBASE__BASEADDR___M 0xFFFFF000 +#define DBG_PHYA_CPU0_DBGDRAR_ROMBASE__BASEADDR___S 12 +#define DBG_PHYA_CPU0_DBGDRAR_ROMBASE__FORMAT___M 0x00000002 +#define DBG_PHYA_CPU0_DBGDRAR_ROMBASE__FORMAT___S 1 +#define DBG_PHYA_CPU0_DBGDRAR_ROMBASE__ENTRYPRESENT___M 0x00000001 +#define DBG_PHYA_CPU0_DBGDRAR_ROMBASE__ENTRYPRESENT___S 0 +#define DBG_PHYA_CPU0_DBGDRAR_ROMBASE___M 0xFFFFF003 +#define DBG_PHYA_CPU0_DBGDRAR_ROMBASE___S 0 + +#define DBG_PHYA_CPU0_IDR (0x00BEE0FC) +#define DBG_PHYA_CPU0_IDR___RWC QCSR_REG_RO +#define DBG_PHYA_CPU0_IDR___POR 0x24770011 +#define DBG_PHYA_CPU0_IDR__REVISION___POR 0x2 +#define DBG_PHYA_CPU0_IDR__JEDECBANK___POR 0x4 +#define DBG_PHYA_CPU0_IDR__JEDECCODE___POR 0x3B +#define DBG_PHYA_CPU0_IDR__MEMAP___POR 0x1 +#define DBG_PHYA_CPU0_IDR__IDENVAL___POR 0x11 +#define DBG_PHYA_CPU0_IDR__REVISION___M 0xF0000000 +#define DBG_PHYA_CPU0_IDR__REVISION___S 28 +#define DBG_PHYA_CPU0_IDR__JEDECBANK___M 0x0F000000 +#define DBG_PHYA_CPU0_IDR__JEDECBANK___S 24 +#define DBG_PHYA_CPU0_IDR__JEDECCODE___M 0x00FE0000 +#define DBG_PHYA_CPU0_IDR__JEDECCODE___S 17 +#define DBG_PHYA_CPU0_IDR__MEMAP___M 0x00010000 +#define DBG_PHYA_CPU0_IDR__MEMAP___S 16 +#define DBG_PHYA_CPU0_IDR__IDENVAL___M 0x000000FF +#define DBG_PHYA_CPU0_IDR__IDENVAL___S 0 +#define DBG_PHYA_CPU0_IDR___M 0xFFFF00FF +#define DBG_PHYA_CPU0_IDR___S 0 + +#define DBG_ABT_HW_VERSION (0x00C31000) +#define DBG_ABT_HW_VERSION___RWC QCSR_REG_RO +#define DBG_ABT_HW_VERSION___POR 0x10000000 +#define DBG_ABT_HW_VERSION__MAJOR___POR 0x1 +#define DBG_ABT_HW_VERSION__MINOR___POR 0x000 +#define DBG_ABT_HW_VERSION__STEP___POR 0x0000 +#define DBG_ABT_HW_VERSION__MAJOR___M 0xF0000000 +#define DBG_ABT_HW_VERSION__MAJOR___S 28 +#define DBG_ABT_HW_VERSION__MINOR___M 0x0FFF0000 +#define DBG_ABT_HW_VERSION__MINOR___S 16 +#define DBG_ABT_HW_VERSION__STEP___M 0x0000FFFF +#define DBG_ABT_HW_VERSION__STEP___S 0 +#define DBG_ABT_HW_VERSION___M 0xFFFFFFFF +#define DBG_ABT_HW_VERSION___S 0 + +#define DBG_ABT_INST_ID (0x00C31004) +#define DBG_ABT_INST_ID___RWC QCSR_REG_RW +#define DBG_ABT_INST_ID___POR 0x00000000 +#define DBG_ABT_INST_ID__INSTID___POR 0x00000000 +#define DBG_ABT_INST_ID__INSTID___M 0xFFFFFFFF +#define DBG_ABT_INST_ID__INSTID___S 0 +#define DBG_ABT_INST_ID___M 0xFFFFFFFF +#define DBG_ABT_INST_ID___S 0 + +#define DBG_ABT_NUM_SLAVES (0x00C31008) +#define DBG_ABT_NUM_SLAVES___RWC QCSR_REG_RO +#define DBG_ABT_NUM_SLAVES___POR 0x00000008 +#define DBG_ABT_NUM_SLAVES__NUMSLAVES___POR 0x8 +#define DBG_ABT_NUM_SLAVES__NUMSLAVES___M 0x0000003F +#define DBG_ABT_NUM_SLAVES__NUMSLAVES___S 0 +#define DBG_ABT_NUM_SLAVES___M 0x0000003F +#define DBG_ABT_NUM_SLAVES___S 0 + +#define DBG_ABT_TIMER_LOADVAL (0x00C3100C) +#define DBG_ABT_TIMER_LOADVAL___RWC QCSR_REG_RW +#define DBG_ABT_TIMER_LOADVAL___POR 0x000000FF +#define DBG_ABT_TIMER_LOADVAL__LOADVAL___POR 0xFF +#define DBG_ABT_TIMER_LOADVAL__LOADVAL___M 0x000000FF +#define DBG_ABT_TIMER_LOADVAL__LOADVAL___S 0 +#define DBG_ABT_TIMER_LOADVAL___M 0x000000FF +#define DBG_ABT_TIMER_LOADVAL___S 0 + +#define DBG_ABT_TIMER_MODE (0x00C31010) +#define DBG_ABT_TIMER_MODE___RWC QCSR_REG_RW +#define DBG_ABT_TIMER_MODE___POR 0x00000000 +#define DBG_ABT_TIMER_MODE__MODE___POR 0x0 +#define DBG_ABT_TIMER_MODE__MODE___M 0x00000001 +#define DBG_ABT_TIMER_MODE__MODE___S 0 +#define DBG_ABT_TIMER_MODE___M 0x00000001 +#define DBG_ABT_TIMER_MODE___S 0 + +#define DBG_ABT_INTR_STATUS (0x00C31014) +#define DBG_ABT_INTR_STATUS___RWC QCSR_REG_RO +#define DBG_ABT_INTR_STATUS___POR 0x00000000 +#define DBG_ABT_INTR_STATUS__INTRSTATUS___POR 0x0 +#define DBG_ABT_INTR_STATUS__INTRSTATUS___M 0x00000001 +#define DBG_ABT_INTR_STATUS__INTRSTATUS___S 0 +#define DBG_ABT_INTR_STATUS___M 0x00000001 +#define DBG_ABT_INTR_STATUS___S 0 + +#define DBG_ABT_INTR_CLEAR (0x00C31018) +#define DBG_ABT_INTR_CLEAR___RWC QCSR_REG_WO +#define DBG_ABT_INTR_CLEAR___POR 0x00000000 +#define DBG_ABT_INTR_CLEAR__INTRCLEAR___POR 0x0 +#define DBG_ABT_INTR_CLEAR__INTRCLEAR___M 0x00000001 +#define DBG_ABT_INTR_CLEAR__INTRCLEAR___S 0 +#define DBG_ABT_INTR_CLEAR___M 0x00000001 +#define DBG_ABT_INTR_CLEAR___S 0 + +#define DBG_ABT_INTR_ENABLE (0x00C3101C) +#define DBG_ABT_INTR_ENABLE___RWC QCSR_REG_RW +#define DBG_ABT_INTR_ENABLE___POR 0x00000000 +#define DBG_ABT_INTR_ENABLE__INTRENABLE___POR 0x0 +#define DBG_ABT_INTR_ENABLE__INTRENABLE___M 0x00000001 +#define DBG_ABT_INTR_ENABLE__INTRENABLE___S 0 +#define DBG_ABT_INTR_ENABLE___M 0x00000001 +#define DBG_ABT_INTR_ENABLE___S 0 + +#define DBG_ABT_SYND_VALID (0x00C31020) +#define DBG_ABT_SYND_VALID___RWC QCSR_REG_RO +#define DBG_ABT_SYND_VALID___POR 0x00000000 +#define DBG_ABT_SYND_VALID__SYNDVALID___POR 0x0 +#define DBG_ABT_SYND_VALID__SYNDVALID___M 0x00000001 +#define DBG_ABT_SYND_VALID__SYNDVALID___S 0 +#define DBG_ABT_SYND_VALID___M 0x00000001 +#define DBG_ABT_SYND_VALID___S 0 + +#define DBG_ABT_SYND_CLEAR (0x00C31024) +#define DBG_ABT_SYND_CLEAR___RWC QCSR_REG_WO +#define DBG_ABT_SYND_CLEAR___POR 0x00000000 +#define DBG_ABT_SYND_CLEAR__SYNDCLEAR___POR 0x0 +#define DBG_ABT_SYND_CLEAR__SYNDCLEAR___M 0x00000001 +#define DBG_ABT_SYND_CLEAR__SYNDCLEAR___S 0 +#define DBG_ABT_SYND_CLEAR___M 0x00000001 +#define DBG_ABT_SYND_CLEAR___S 0 + +#define DBG_ABT_SYND_ID (0x00C31028) +#define DBG_ABT_SYND_ID___RWC QCSR_REG_RO +#define DBG_ABT_SYND_ID___POR 0x00000000 +#define DBG_ABT_SYND_ID__BID___POR 0x0 +#define DBG_ABT_SYND_ID__PID___POR 0x00 +#define DBG_ABT_SYND_ID__MID___POR 0x00 +#define DBG_ABT_SYND_ID__BID___M 0x0000E000 +#define DBG_ABT_SYND_ID__BID___S 13 +#define DBG_ABT_SYND_ID__PID___M 0x00001F00 +#define DBG_ABT_SYND_ID__PID___S 8 +#define DBG_ABT_SYND_ID__MID___M 0x000000FF +#define DBG_ABT_SYND_ID__MID___S 0 +#define DBG_ABT_SYND_ID___M 0x0000FFFF +#define DBG_ABT_SYND_ID___S 0 + +#define DBG_ABT_SYND_ADDR0 (0x00C3102C) +#define DBG_ABT_SYND_ADDR0___RWC QCSR_REG_RO +#define DBG_ABT_SYND_ADDR0___POR 0x00000000 +#define DBG_ABT_SYND_ADDR0__SYNDADDR0___POR 0x00000000 +#define DBG_ABT_SYND_ADDR0__SYNDADDR0___M 0xFFFFFFFF +#define DBG_ABT_SYND_ADDR0__SYNDADDR0___S 0 +#define DBG_ABT_SYND_ADDR0___M 0xFFFFFFFF +#define DBG_ABT_SYND_ADDR0___S 0 + +#define DBG_ABT_SYND_ADDR1 (0x00C31030) +#define DBG_ABT_SYND_ADDR1___RWC QCSR_REG_RO +#define DBG_ABT_SYND_ADDR1___POR 0x00000000 +#define DBG_ABT_SYND_ADDR1__SYNDADDR1___POR 0x00000000 +#define DBG_ABT_SYND_ADDR1__SYNDADDR1___M 0xFFFFFFFF +#define DBG_ABT_SYND_ADDR1__SYNDADDR1___S 0 +#define DBG_ABT_SYND_ADDR1___M 0xFFFFFFFF +#define DBG_ABT_SYND_ADDR1___S 0 + +#define DBG_ABT_SYND_HREADY (0x00C31034) +#define DBG_ABT_SYND_HREADY___RWC QCSR_REG_RO +#define DBG_ABT_SYND_HREADY___POR 0xFFFFFFFF +#define DBG_ABT_SYND_HREADY__SYNDHREADY___POR 0xFFFFFFFF +#define DBG_ABT_SYND_HREADY__SYNDHREADY___M 0xFFFFFFFF +#define DBG_ABT_SYND_HREADY__SYNDHREADY___S 0 +#define DBG_ABT_SYND_HREADY___M 0xFFFFFFFF +#define DBG_ABT_SYND_HREADY___S 0 + + +#define UMAC_NOC_BASE (0x00140000) + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW (0x00140000) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW___POR 0x0001E93B +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW__UNITTYPEID___POR 0x01 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW__UNITCONFID___POR 0xE93B +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW__UNITTYPEID___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW__UNITCONFID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW___M 0x00FFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_HIGH (0x00140004) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_HIGH___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_HIGH__QNOCID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_HIGH___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_SWID_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW (0x00140008) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW___POR 0x00000003 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW__STALLEN___POR 0x1 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW__FAULTEN___POR 0x1 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW__STALLEN___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW__STALLEN___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW__FAULTEN___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW__FAULTEN___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW___M 0x00000003 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_MAINCTL_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRVLD_LOW (0x00140010) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRVLD_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRVLD_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRVLD_LOW__ERRVLD___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRVLD_LOW__ERRVLD___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRVLD_LOW__ERRVLD___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRVLD_LOW___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRVLD_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRCLR_LOW (0x00140018) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRCLR_LOW___RWC QCSR_REG_WO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRCLR_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRCLR_LOW__ERRCLR___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRCLR_LOW__ERRCLR___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRCLR_LOW__ERRCLR___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRCLR_LOW___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRCLR_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW (0x00140020) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ATOPC___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ADDRSPACE___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__TRTYPE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ERRCODE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__OPC___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__NONSECURE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__WORDERROR___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__LOGINFOVLD___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ATOPC___M 0x0F000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ATOPC___S 24 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ADDRSPACE___M 0x003F0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ADDRSPACE___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__TRTYPE___M 0x00007000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__TRTYPE___S 12 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ERRCODE___M 0x00000700 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__ERRCODE___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__OPC___M 0x00000070 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__OPC___S 4 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__NONSECURE___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__NONSECURE___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__WORDERROR___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__WORDERROR___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__LOGINFOVLD___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW__LOGINFOVLD___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW___M 0x0F3F7777 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH (0x00140024) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH__REDIRECT___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH__LEN1___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH__REDIRECT___M 0x00FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH__REDIRECT___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH__LEN1___M 0x000003FF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH__LEN1___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH___M 0x00FF03FF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG0_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_LOW (0x00140028) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_LOW__PATH___POR 0x0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_LOW__PATH___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_LOW__PATH___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_LOW___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_HIGH (0x0014002C) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_HIGH___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_HIGH__EXTID___POR 0x00000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_HIGH__EXTID___M 0x0003FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_HIGH__EXTID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_HIGH___M 0x0003FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG1_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_LOW (0x00140030) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_LOW__ERRLOG2_LSB___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_LOW__ERRLOG2_LSB___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_LOW__ERRLOG2_LSB___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_LOW___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_HIGH (0x00140034) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_HIGH___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___POR 0x00000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___M 0x0001FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_HIGH___M 0x0001FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG2_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_LOW (0x00140038) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_LOW__ERRLOG3_LSB___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_LOW__ERRLOG3_LSB___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_LOW__ERRLOG3_LSB___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_LOW___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_HIGH (0x0014003C) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_HIGH___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_HIGH___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_ERL_ERRLOG3_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW (0x00140080) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW___POR 0x0001E93B +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW__UNITTYPEID___POR 0x01 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW__UNITCONFID___POR 0xE93B +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW__UNITTYPEID___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW__UNITCONFID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW___M 0x00FFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_HIGH (0x00140084) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_HIGH___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_HIGH__QNOCID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_HIGH___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_SWID_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW (0x00140088) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW___POR 0x00000003 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW__STALLEN___POR 0x1 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW__FAULTEN___POR 0x1 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW__STALLEN___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW__STALLEN___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW__FAULTEN___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW__FAULTEN___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW___M 0x00000003 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_MAINCTL_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRVLD_LOW (0x00140090) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRVLD_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRVLD_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRVLD_LOW__ERRVLD___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRVLD_LOW__ERRVLD___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRVLD_LOW__ERRVLD___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRVLD_LOW___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRVLD_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRCLR_LOW (0x00140098) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRCLR_LOW___RWC QCSR_REG_WO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRCLR_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRCLR_LOW__ERRCLR___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRCLR_LOW__ERRCLR___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRCLR_LOW__ERRCLR___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRCLR_LOW___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRCLR_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW (0x001400A0) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ATOPC___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ADDRSPACE___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__TRTYPE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ERRCODE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__OPC___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__NONSECURE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__WORDERROR___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__LOGINFOVLD___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ATOPC___M 0x0F000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ATOPC___S 24 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ADDRSPACE___M 0x003F0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ADDRSPACE___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__TRTYPE___M 0x00007000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__TRTYPE___S 12 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ERRCODE___M 0x00000700 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__ERRCODE___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__OPC___M 0x00000070 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__OPC___S 4 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__NONSECURE___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__NONSECURE___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__WORDERROR___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__WORDERROR___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__LOGINFOVLD___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW__LOGINFOVLD___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW___M 0x0F3F7777 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH (0x001400A4) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH__REDIRECT___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH__LEN1___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH__REDIRECT___M 0x00FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH__REDIRECT___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH__LEN1___M 0x000003FF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH__LEN1___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH___M 0x00FF03FF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG0_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_LOW (0x001400A8) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_LOW__PATH___POR 0x0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_LOW__PATH___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_LOW__PATH___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_LOW___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_HIGH (0x001400AC) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_HIGH___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_HIGH__EXTID___POR 0x00000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_HIGH__EXTID___M 0x0003FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_HIGH__EXTID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_HIGH___M 0x0003FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG1_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_LOW (0x001400B0) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_LOW__ERRLOG2_LSB___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_LOW__ERRLOG2_LSB___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_LOW__ERRLOG2_LSB___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_LOW___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_HIGH (0x001400B4) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_HIGH___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___POR 0x00000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___M 0x0001FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_HIGH___M 0x0001FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG2_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_LOW (0x001400B8) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_LOW__ERRLOG3_LSB___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_LOW__ERRLOG3_LSB___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_LOW__ERRLOG3_LSB___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_LOW___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_HIGH (0x001400BC) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_HIGH___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_HIGH___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_WMAC_ERL_ERRLOG3_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW (0x00140100) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW___POR 0x0001E93B +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW__UNITTYPEID___POR 0x01 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW__UNITCONFID___POR 0xE93B +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW__UNITTYPEID___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW__UNITCONFID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW___M 0x00FFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_HIGH (0x00140104) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_HIGH___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_HIGH__QNOCID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_HIGH___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_SWID_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW (0x00140108) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW___POR 0x00000003 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW__STALLEN___POR 0x1 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW__FAULTEN___POR 0x1 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW__STALLEN___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW__STALLEN___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW__FAULTEN___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW__FAULTEN___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW___M 0x00000003 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_MAINCTL_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRVLD_LOW (0x00140110) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRVLD_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRVLD_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRVLD_LOW__ERRVLD___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRVLD_LOW__ERRVLD___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRVLD_LOW__ERRVLD___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRVLD_LOW___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRVLD_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRCLR_LOW (0x00140118) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRCLR_LOW___RWC QCSR_REG_WO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRCLR_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRCLR_LOW__ERRCLR___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRCLR_LOW__ERRCLR___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRCLR_LOW__ERRCLR___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRCLR_LOW___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRCLR_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW (0x00140120) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ATOPC___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ADDRSPACE___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__TRTYPE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ERRCODE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__OPC___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__NONSECURE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__WORDERROR___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__LOGINFOVLD___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ATOPC___M 0x0F000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ATOPC___S 24 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ADDRSPACE___M 0x003F0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ADDRSPACE___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__TRTYPE___M 0x00007000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__TRTYPE___S 12 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ERRCODE___M 0x00000700 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__ERRCODE___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__OPC___M 0x00000070 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__OPC___S 4 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__NONSECURE___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__NONSECURE___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__WORDERROR___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__WORDERROR___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__LOGINFOVLD___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW__LOGINFOVLD___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW___M 0x0F3F7777 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH (0x00140124) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH__REDIRECT___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH__LEN1___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH__REDIRECT___M 0x00FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH__REDIRECT___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH__LEN1___M 0x000003FF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH__LEN1___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH___M 0x00FF03FF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG0_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_LOW (0x00140128) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_LOW__PATH___POR 0x0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_LOW__PATH___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_LOW__PATH___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_LOW___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_HIGH (0x0014012C) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_HIGH___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_HIGH__EXTID___POR 0x00000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_HIGH__EXTID___M 0x0003FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_HIGH__EXTID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_HIGH___M 0x0003FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG1_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_LOW (0x00140130) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_LOW__ERRLOG2_LSB___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_LOW__ERRLOG2_LSB___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_LOW__ERRLOG2_LSB___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_LOW___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_HIGH (0x00140134) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_HIGH___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___POR 0x00000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___M 0x0001FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_HIGH__ERRLOG2_MSB___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_HIGH___M 0x0001FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG2_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_LOW (0x00140138) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_LOW__ERRLOG3_LSB___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_LOW__ERRLOG3_LSB___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_LOW__ERRLOG3_LSB___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_LOW___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_HIGH (0x0014013C) +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_HIGH___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_HIGH__ERRLOG3_MSB___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_HIGH___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_ERRORLOGGER_PHY_ERL_ERRLOG3_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW (0x00140200) +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW___POR 0x000EEC22 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW__UNITTYPEID___POR 0x0E +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW__UNITCONFID___POR 0xEC22 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW__UNITTYPEID___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW__UNITCONFID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW___M 0x00FFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_HIGH (0x00140204) +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_HIGH___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_HIGH__QNOCID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_HIGH___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_SWID_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW (0x00140240) +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__EVENTCOLLECTOR_ALARM___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__QXS_SNOC_TRACE_ALARM___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_PHY_FAULT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_WMAC_FAULT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_FAULT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XS_CMEM___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_WMAC0___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_WBM___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_TQM___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_TCL___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_REO___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIEMOUT_XM_COEX___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_SERVICENIU___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXS_SNOC___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXS_PHYA___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXM_SNOC___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXM_PHYA___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QHS_RET_AHB___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QHM_RET_AHB___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_PM_WCSS_DBG___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__EVENTCOLLECTOR_ALARM___M 0x00800000 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__EVENTCOLLECTOR_ALARM___S 23 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__QXS_SNOC_TRACE_ALARM___M 0x00400000 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__QXS_SNOC_TRACE_ALARM___S 22 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_PHY_FAULT___M 0x00200000 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_PHY_FAULT___S 21 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_WMAC_FAULT___M 0x00100000 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_WMAC_FAULT___S 20 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_FAULT___M 0x00080000 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__ERRORLOGGER_FAULT___S 19 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XS_CMEM___M 0x00040000 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XS_CMEM___S 18 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_WMAC0___M 0x00010000 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_WMAC0___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_WBM___M 0x00008000 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_WBM___S 15 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_TQM___M 0x00004000 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_TQM___S 14 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_TCL___M 0x00002000 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_TCL___S 13 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_REO___M 0x00001000 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_XM_REO___S 12 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIEMOUT_XM_COEX___M 0x00000800 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIEMOUT_XM_COEX___S 11 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_SERVICENIU___M 0x00000400 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_SERVICENIU___S 10 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXS_SNOC___M 0x00000100 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXS_SNOC___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXS_PHYA___M 0x00000040 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXS_PHYA___S 6 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXM_SNOC___M 0x00000020 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXM_SNOC___S 5 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXM_PHYA___M 0x00000008 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QXM_PHYA___S 3 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QHS_RET_AHB___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QHS_RET_AHB___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QHM_RET_AHB___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_QHM_RET_AHB___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_PM_WCSS_DBG___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW__TIMEOUT_PM_WCSS_DBG___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW___M 0x00FDFD6F +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINEN0_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW (0x00140248) +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__EVENTCOLLECTOR_ALARM___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__QXS_SNOC_TRACE_ALARM___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_PHY_FAULT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_WMAC_FAULT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_FAULT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XS_CMEM___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_WMAC0___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_WBM___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_TQM___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_TCL___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_REO___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIEMOUT_XM_COEX___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_SERVICENIU___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXS_SNOC___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXS_PHYA___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXM_SNOC___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXM_PHYA___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QHS_RET_AHB___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QHM_RET_AHB___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_PM_WCSS_DBG___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__EVENTCOLLECTOR_ALARM___M 0x00800000 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__EVENTCOLLECTOR_ALARM___S 23 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__QXS_SNOC_TRACE_ALARM___M 0x00400000 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__QXS_SNOC_TRACE_ALARM___S 22 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_PHY_FAULT___M 0x00200000 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_PHY_FAULT___S 21 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_WMAC_FAULT___M 0x00100000 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_WMAC_FAULT___S 20 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_FAULT___M 0x00080000 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__ERRORLOGGER_FAULT___S 19 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XS_CMEM___M 0x00040000 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XS_CMEM___S 18 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_WMAC0___M 0x00010000 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_WMAC0___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_WBM___M 0x00008000 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_WBM___S 15 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_TQM___M 0x00004000 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_TQM___S 14 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_TCL___M 0x00002000 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_TCL___S 13 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_REO___M 0x00001000 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_XM_REO___S 12 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIEMOUT_XM_COEX___M 0x00000800 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIEMOUT_XM_COEX___S 11 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_SERVICENIU___M 0x00000400 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_SERVICENIU___S 10 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXS_SNOC___M 0x00000100 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXS_SNOC___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXS_PHYA___M 0x00000040 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXS_PHYA___S 6 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXM_SNOC___M 0x00000020 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXM_SNOC___S 5 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXM_PHYA___M 0x00000008 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QXM_PHYA___S 3 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QHS_RET_AHB___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QHS_RET_AHB___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QHM_RET_AHB___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_QHM_RET_AHB___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_PM_WCSS_DBG___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW__TIMEOUT_PM_WCSS_DBG___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW___M 0x00FDFD6F +#define UMAC_NOC_UMAC_NOC_FABRIC_SIDEBANDMANAGER_SBM_FAULTINSTATUS0_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW (0x00140400) +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW___POR 0x000E8DBE +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW__UNITTYPEID___POR 0x0E +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW__UNITCONFID___POR 0x8DBE +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW__UNITTYPEID___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW__UNITCONFID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW___M 0x00FFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_HIGH (0x00140404) +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_HIGH___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_HIGH__QNOCID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_HIGH___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SWID_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTCLR0_LOW (0x00140480) +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTCLR0_LOW___RWC QCSR_REG_WO +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTCLR0_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTCLR0_LOW__COEX_APB2AXI_XWERR___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTCLR0_LOW__COEX_APB2AXI_XWERR___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTCLR0_LOW__COEX_APB2AXI_XWERR___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTCLR0_LOW___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTCLR0_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSET0_LOW (0x00140488) +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSET0_LOW___RWC QCSR_REG_WO +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSET0_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSET0_LOW__COEX_APB2AXI_XWERR___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSET0_LOW__COEX_APB2AXI_XWERR___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSET0_LOW__COEX_APB2AXI_XWERR___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSET0_LOW___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSET0_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSTATUS0_LOW (0x00140490) +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSTATUS0_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSTATUS0_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSTATUS0_LOW__COEX_APB2AXI_XWERR___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSTATUS0_LOW__COEX_APB2AXI_XWERR___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSTATUS0_LOW__COEX_APB2AXI_XWERR___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSTATUS0_LOW___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_FLAGOUTSTATUS0_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW (0x00140500) +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW__COEX_APB2AXI_XWSLVERR___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW__COEX_APB2AXI_XWDECERR___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW__COEX_APB2AXI_XWSLVERR___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW__COEX_APB2AXI_XWSLVERR___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW__COEX_APB2AXI_XWDECERR___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW__COEX_APB2AXI_XWDECERR___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW___M 0x00000003 +#define UMAC_NOC_UMAC_NOC_FABRIC_COEX_APB2AXI_CTRL_SBM_SENSEIN0_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW (0x00140600) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW___POR 0x0008317D +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW__UNITTYPEID___POR 0x08 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW__UNITCONFID___POR 0x317D +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW__UNITTYPEID___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW__UNITCONFID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW___M 0x00FFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_HIGH (0x00140604) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_HIGH___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_HIGH__QNOCID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_HIGH___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SWID_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW (0x00140608) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__URGDELAY___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__DFLTPRIORITY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__STOP___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__SHAPEREN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__BWLIMITEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__URGDELAY___M 0x00003F00 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__URGDELAY___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__DFLTPRIORITY___M 0x00000030 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__DFLTPRIORITY___S 4 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__STOP___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__STOP___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__SHAPEREN___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__SHAPEREN___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__BWLIMITEN___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW__BWLIMITEN___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW___M 0x00003F37 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINCTL_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW (0x00140610) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW___POR 0x00F00000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___POR 0x0F0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW__PENDING___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___M 0x0FFF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW__PENDING___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW__PENDING___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW___M 0x0FFF001F +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_MAINSTATUS_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW (0x00140618) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW__SATURATION___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW__BANDWIDTH___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW__SATURATION___M 0x03FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW__SATURATION___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW__BANDWIDTH___M 0x000007FF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW__BANDWIDTH___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW___M 0x03FF07FF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_LIMITBW_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW (0x00140620) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL3___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL2___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL1___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL0___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL3___M 0x0F000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL3___S 24 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL2___M 0x000F0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL2___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL1___M 0x00000F00 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL1___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL0___M 0x0000000F +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW__LVL0___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW___M 0x0F0F0F0F +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_SHAPING_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW (0x00140640) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__HIGHPRIORITY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__LOWPRIORITY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__WREN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__RDEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__HIGHPRIORITY___M 0x00003000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__HIGHPRIORITY___S 12 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__LOWPRIORITY___M 0x00000300 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__LOWPRIORITY___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__WREN___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__WREN___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__RDEN___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW__RDEN___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW___M 0x00003303 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0CTL_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW (0x00140648) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW___POR 0x00800400 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW__SATURATION___POR 0x080 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW__BANDWIDTH___POR 0x400 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW__SATURATION___M 0x03FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW__SATURATION___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW__BANDWIDTH___M 0x000007FF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW__BANDWIDTH___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW___M 0x03FF07FF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL0BW_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW (0x00140650) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__HIGHPRIORITY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__LOWPRIORITY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__WREN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__RDEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__HIGHPRIORITY___M 0x00003000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__HIGHPRIORITY___S 12 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__LOWPRIORITY___M 0x00000300 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__LOWPRIORITY___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__WREN___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__WREN___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__RDEN___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW__RDEN___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW___M 0x00003303 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1CTL_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW (0x00140658) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW___POR 0x00800400 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW__SATURATION___POR 0x080 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW__BANDWIDTH___POR 0x400 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW__SATURATION___M 0x03FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW__SATURATION___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW__BANDWIDTH___M 0x000007FF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW__BANDWIDTH___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW___M 0x03FF07FF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXM_PHYA_QOSGEN_REGUL1BW_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW (0x00140700) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW___POR 0x0008FDF1 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW__UNITTYPEID___POR 0x08 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW__UNITCONFID___POR 0xFDF1 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW__UNITTYPEID___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW__UNITCONFID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW___M 0x00FFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_HIGH (0x00140704) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_HIGH___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_HIGH__QNOCID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_HIGH___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SWID_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW (0x00140708) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__STOP___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__SHAPEREN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__BWLIMITEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__STOP___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__STOP___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__SHAPEREN___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__SHAPEREN___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__BWLIMITEN___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW__BWLIMITEN___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW___M 0x00000007 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINCTL_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW (0x00140710) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW___POR 0x00F00000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___POR 0x0F0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW__PENDING___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___M 0x0FFF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW__PENDING___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW__PENDING___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW___M 0x0FFF001F +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_MAINSTATUS_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW (0x00140718) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW__SATURATION___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW__BANDWIDTH___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW__SATURATION___M 0x03FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW__SATURATION___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW__BANDWIDTH___M 0x000007FF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW__BANDWIDTH___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW___M 0x03FF07FF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_LIMITBW_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW (0x00140720) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL3___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL2___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL1___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL0___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL3___M 0x0F000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL3___S 24 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL2___M 0x000F0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL2___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL1___M 0x00000F00 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL1___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL0___M 0x0000000F +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW__LVL0___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW___M 0x0F0F0F0F +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_REO_QOSGEN_SHAPING_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW (0x00140780) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW___POR 0x0008FDF1 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW__UNITTYPEID___POR 0x08 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW__UNITCONFID___POR 0xFDF1 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW__UNITTYPEID___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW__UNITCONFID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW___M 0x00FFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_HIGH (0x00140784) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_HIGH___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_HIGH__QNOCID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_HIGH___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SWID_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW (0x00140788) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__STOP___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__SHAPEREN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__BWLIMITEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__STOP___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__STOP___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__SHAPEREN___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__SHAPEREN___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__BWLIMITEN___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW__BWLIMITEN___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW___M 0x00000007 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINCTL_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW (0x00140790) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW___POR 0x00F00000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___POR 0x0F0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW__PENDING___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___M 0x0FFF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW__PENDING___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW__PENDING___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW___M 0x0FFF001F +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_MAINSTATUS_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW (0x00140798) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW__SATURATION___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW__BANDWIDTH___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW__SATURATION___M 0x03FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW__SATURATION___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW__BANDWIDTH___M 0x000007FF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW__BANDWIDTH___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW___M 0x03FF07FF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_LIMITBW_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW (0x001407A0) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL3___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL2___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL1___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL0___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL3___M 0x0F000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL3___S 24 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL2___M 0x000F0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL2___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL1___M 0x00000F00 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL1___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL0___M 0x0000000F +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW__LVL0___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW___M 0x0F0F0F0F +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TCL_QOSGEN_SHAPING_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW (0x00140800) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW___POR 0x00087F1D +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW__UNITTYPEID___POR 0x08 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW__UNITCONFID___POR 0x7F1D +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW__UNITTYPEID___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW__UNITCONFID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW___M 0x00FFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_HIGH (0x00140804) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_HIGH___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_HIGH__QNOCID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_HIGH___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SWID_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW (0x00140808) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__STOP___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__SHAPEREN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__BWLIMITEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__STOP___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__STOP___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__SHAPEREN___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__SHAPEREN___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__BWLIMITEN___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW__BWLIMITEN___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW___M 0x00000007 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINCTL_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW (0x00140810) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW___POR 0x00F00000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___POR 0x0F0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW__PENDING___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___M 0x0FFF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW__PENDING___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW__PENDING___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW___M 0x0FFF001F +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_MAINSTATUS_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW (0x00140818) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW__SATURATION___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW__BANDWIDTH___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW__SATURATION___M 0x03FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW__SATURATION___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW__BANDWIDTH___M 0x000007FF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW__BANDWIDTH___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW___M 0x03FF07FF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_LIMITBW_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW (0x00140820) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL3___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL2___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL1___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL0___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL3___M 0x1F000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL3___S 24 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL2___M 0x001F0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL2___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL1___M 0x00001F00 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL1___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL0___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW__LVL0___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW___M 0x1F1F1F1F +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_TQM_QOSGEN_SHAPING_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW (0x00140880) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW___POR 0x0008FDF1 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW__UNITTYPEID___POR 0x08 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW__UNITCONFID___POR 0xFDF1 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW__UNITTYPEID___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW__UNITCONFID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW___M 0x00FFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_HIGH (0x00140884) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_HIGH___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_HIGH__QNOCID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_HIGH___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SWID_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW (0x00140888) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__STOP___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__SHAPEREN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__BWLIMITEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__STOP___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__STOP___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__SHAPEREN___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__SHAPEREN___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__BWLIMITEN___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW__BWLIMITEN___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW___M 0x00000007 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINCTL_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW (0x00140890) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW___POR 0x00F00000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___POR 0x0F0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW__PENDING___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___M 0x0FFF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW__PENDING___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW__PENDING___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW___M 0x0FFF001F +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_MAINSTATUS_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW (0x00140898) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW__SATURATION___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW__BANDWIDTH___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW__SATURATION___M 0x03FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW__SATURATION___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW__BANDWIDTH___M 0x000007FF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW__BANDWIDTH___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW___M 0x03FF07FF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_LIMITBW_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW (0x001408A0) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL3___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL2___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL1___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL0___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL3___M 0x0F000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL3___S 24 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL2___M 0x000F0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL2___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL1___M 0x00000F00 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL1___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL0___M 0x0000000F +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW__LVL0___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW___M 0x0F0F0F0F +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WBM_QOSGEN_SHAPING_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW (0x00140900) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW___POR 0x00081500 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW__UNITTYPEID___POR 0x08 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW__UNITCONFID___POR 0x1500 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW__UNITTYPEID___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW__UNITCONFID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW___M 0x00FFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_HIGH (0x00140904) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_HIGH___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_HIGH__QNOCID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_HIGH___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SWID_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW (0x00140908) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__URGDELAY___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__DFLTPRIORITY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__STOP___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__SHAPEREN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__BWLIMITEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__URGDELAY___M 0x00003F00 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__URGDELAY___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__DFLTPRIORITY___M 0x00000030 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__DFLTPRIORITY___S 4 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__STOP___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__STOP___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__SHAPEREN___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__SHAPEREN___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__BWLIMITEN___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW__BWLIMITEN___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW___M 0x00003F37 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINCTL_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW (0x00140910) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW___POR 0x00F00000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___POR 0x0F0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW__PENDING___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___M 0x0FFF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW__NOMINALFREQ___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW__PENDING___M 0x0000007F +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW__PENDING___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW___M 0x0FFF007F +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_MAINSTATUS_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW (0x00140918) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW__SATURATION___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW__BANDWIDTH___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW__SATURATION___M 0x03FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW__SATURATION___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW__BANDWIDTH___M 0x000007FF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW__BANDWIDTH___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW___M 0x03FF07FF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_LIMITBW_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW (0x00140920) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL3___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL2___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL1___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL0___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL3___M 0x3F000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL3___S 24 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL2___M 0x003F0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL2___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL1___M 0x00003F00 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL1___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL0___M 0x0000003F +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW__LVL0___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW___M 0x3F3F3F3F +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_SHAPING_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW (0x00140940) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__HIGHPRIORITY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__LOWPRIORITY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__WREN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__RDEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__HIGHPRIORITY___M 0x00003000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__HIGHPRIORITY___S 12 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__LOWPRIORITY___M 0x00000300 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__LOWPRIORITY___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__WREN___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__WREN___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__RDEN___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW__RDEN___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW___M 0x00003303 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0CTL_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW (0x00140948) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW___POR 0x00800199 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW__SATURATION___POR 0x080 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW__BANDWIDTH___POR 0x199 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW__SATURATION___M 0x03FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW__SATURATION___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW__BANDWIDTH___M 0x000007FF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW__BANDWIDTH___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW___M 0x03FF07FF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL0BW_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW (0x00140950) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__HIGHPRIORITY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__LOWPRIORITY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__WREN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__RDEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__HIGHPRIORITY___M 0x00003000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__HIGHPRIORITY___S 12 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__LOWPRIORITY___M 0x00000300 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__LOWPRIORITY___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__WREN___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__WREN___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__RDEN___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW__RDEN___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW___M 0x00003303 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1CTL_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW (0x00140958) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW___POR 0x00800199 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW__SATURATION___POR 0x080 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW__BANDWIDTH___POR 0x199 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW__SATURATION___M 0x03FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW__SATURATION___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW__BANDWIDTH___M 0x000007FF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW__BANDWIDTH___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW___M 0x03FF07FF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_QOSGEN_REGUL1BW_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_LOW (0x00141000) +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_LOW___POR 0x000CE93B +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_LOW__UNITTYPEID___POR 0x0C +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_LOW__UNITCONFID___POR 0xE93B +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_LOW__UNITTYPEID___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_LOW__UNITCONFID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_LOW___M 0x00FFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_HIGH (0x00141004) +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_HIGH___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_HIGH__QNOCID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_HIGH___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_SWID_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_ATBEN_LOW (0x00141008) +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_ATBEN_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_ATBEN_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_ATBEN_LOW__ATBEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_ATBEN_LOW__ATBEN___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_ATBEN_LOW__ATBEN___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_ATBEN_LOW___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_ATBEN_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_ATBID_LOW (0x00141010) +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_ATBID_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_ATBID_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_ATBID_LOW__ATBID___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_ATBID_LOW__ATBID___M 0x0000007F +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_ATBID_LOW__ATBID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_ATBID_LOW___M 0x0000007F +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_ATBID_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_SYNCOUTPERIOD_LOW (0x00141018) +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_SYNCOUTPERIOD_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_SYNCOUTPERIOD_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_SYNCOUTPERIOD_LOW__SYNCOUTPERIOD___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_SYNCOUTPERIOD_LOW__SYNCOUTPERIOD___M 0x000003FF +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_SYNCOUTPERIOD_LOW__SYNCOUTPERIOD___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_SYNCOUTPERIOD_LOW___M 0x000003FF +#define UMAC_NOC_UMAC_NOC_FABRIC_STP_SYNCOUTPERIOD_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW (0x00141400) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW___POR 0x0003DBB2 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW__UNITTYPEID___POR 0x03 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW__UNITCONFID___POR 0xDBB2 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW__UNITTYPEID___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW__UNITCONFID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW___M 0x00FFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_HIGH (0x00141404) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_HIGH___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_HIGH__QNOCID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_HIGH___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_SWID_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW (0x00141408) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__SCALEEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__DUMPEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__MODE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___M 0x00000300 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___S 5 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___M 0x00000010 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___S 4 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__SCALEEN___M 0x00000008 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__SCALEEN___S 3 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__DUMPEN___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__DUMPEN___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__MODE___M 0x00000003 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW__MODE___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW___M 0x0000033F +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_MAINCTL_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPGO_LOW (0x00141410) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPGO_LOW___RWC QCSR_REG_WO +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPGO_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPGO_LOW__DUMPGO___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPGO_LOW__DUMPGO___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPGO_LOW__DUMPGO___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPGO_LOW___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPGO_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPTHR_LOW (0x00141418) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPTHR_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPTHR_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPTHR_LOW__DUMPTHR___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPTHR_LOW__DUMPTHR___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPTHR_LOW__DUMPTHR___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPTHR_LOW___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_DUMPTHR_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW (0x00141420) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW___POR 0x00F00000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__NOMINALFREQ___POR 0x0F0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__OFFSET___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__WIDTH___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__NOMINALFREQ___M 0x0FFF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__NOMINALFREQ___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__OFFSET___M 0x0000FF00 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__OFFSET___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__WIDTH___M 0x000000FF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW__WIDTH___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW___M 0x0FFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_BIN_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_LOW (0x00141428) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_LOW__LATSUM___POR 0x0000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_LOW__LATSUM___M 0x0FFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_LOW__LATSUM___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_LOW___M 0x0FFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_HIGH (0x0014142C) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_HIGH___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_HIGH__TRCNT___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_HIGH__TRCNT___M 0x000FFF00 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_HIGH__TRCNT___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_HIGH___M 0x000FFF00 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_AVLATENCY_HIGH___S 8 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN0_LOW (0x00141440) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN0_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN0_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN0_LOW__HISTBIN0___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN0_LOW__HISTBIN0___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN0_LOW__HISTBIN0___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN0_LOW___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN0_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN1_LOW (0x00141448) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN1_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN1_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN1_LOW__HISTBIN1___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN1_LOW__HISTBIN1___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN1_LOW__HISTBIN1___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN1_LOW___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN1_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN2_LOW (0x00141450) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN2_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN2_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN2_LOW__HISTBIN2___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN2_LOW__HISTBIN2___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN2_LOW__HISTBIN2___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN2_LOW___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN2_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN3_LOW (0x00141458) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN3_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN3_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN3_LOW__HISTBIN3___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN3_LOW__HISTBIN3___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN3_LOW__HISTBIN3___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN3_LOW___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN3_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN4_LOW (0x00141460) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN4_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN4_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN4_LOW__HISTBIN4___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN4_LOW__HISTBIN4___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN4_LOW__HISTBIN4___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN4_LOW___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN4_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN5_LOW (0x00141468) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN5_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN5_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN5_LOW__HISTBIN5___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN5_LOW__HISTBIN5___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN5_LOW__HISTBIN5___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN5_LOW___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN5_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN6_LOW (0x00141470) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN6_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN6_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN6_LOW__HISTBIN6___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN6_LOW__HISTBIN6___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN6_LOW__HISTBIN6___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN6_LOW___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN6_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN7_LOW (0x00141478) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN7_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN7_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN7_LOW__HISTBIN7___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN7_LOW__HISTBIN7___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN7_LOW__HISTBIN7___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN7_LOW___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_HISTBIN7_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_LATMAX_LOW (0x00141480) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_LATMAX_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_LATMAX_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_LATMAX_LOW__LATMAX___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_LATMAX_LOW__LATMAX___M 0x000000FF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_LATMAX_LOW__LATMAX___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_LATMAX_LOW___M 0x000000FF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_LATMAX_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW (0x00141520) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___POR 0x000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFC00 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___S 10 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW___M 0xFFFFFC00 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_LOW___S 10 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH (0x00141524) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MIN_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW (0x00141528) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___POR 0x000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFC00 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___S 10 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW___M 0xFFFFFC00 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_LOW___S 10 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH (0x0014152C) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_ADDR_MAX_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW (0x00141538) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__CMEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__WREN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__RDEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___M 0x00000010 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___S 4 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__CMEN___M 0x00000008 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__CMEN___S 3 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__WREN___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__WREN___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__RDEN___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW__RDEN___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TENUREPRB_FILTER_OPCODE_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW (0x00141600) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW___POR 0x0003CB09 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW__UNITTYPEID___POR 0x03 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW__UNITCONFID___POR 0xCB09 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW__UNITTYPEID___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW__UNITCONFID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW___M 0x00FFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_HIGH (0x00141604) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_HIGH___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_HIGH__QNOCID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_HIGH___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_SWID_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW (0x00141608) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__SCALEEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__DUMPEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__MODE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___M 0x00000300 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__HISTPENDLAW___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__IGNORECTITRIGIN0___S 5 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___M 0x00000010 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__CTITRIGOUTEN___S 4 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__SCALEEN___M 0x00000008 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__SCALEEN___S 3 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__DUMPEN___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__DUMPEN___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__MODE___M 0x00000003 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW__MODE___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW___M 0x0000033F +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_MAINCTL_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPGO_LOW (0x00141610) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPGO_LOW___RWC QCSR_REG_WO +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPGO_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPGO_LOW__DUMPGO___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPGO_LOW__DUMPGO___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPGO_LOW__DUMPGO___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPGO_LOW___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPGO_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPTHR_LOW (0x00141618) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPTHR_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPTHR_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPTHR_LOW__DUMPTHR___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPTHR_LOW__DUMPTHR___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPTHR_LOW__DUMPTHR___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPTHR_LOW___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_DUMPTHR_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW (0x00141620) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW___POR 0x00F00000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__NOMINALFREQ___POR 0x0F0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__OFFSET___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__WIDTH___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__NOMINALFREQ___M 0x0FFF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__NOMINALFREQ___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__OFFSET___M 0x0000FF00 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__OFFSET___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__WIDTH___M 0x000000FF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW__WIDTH___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW___M 0x0FFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_BIN_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_LOW (0x00141628) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_LOW__LATSUM___POR 0x0000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_LOW__LATSUM___M 0x0FFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_LOW__LATSUM___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_LOW___M 0x0FFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_HIGH (0x0014162C) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_HIGH___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_HIGH__TRCNT___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_HIGH__TRCNT___M 0x000FFF00 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_HIGH__TRCNT___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_HIGH___M 0x000FFF00 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_AVLATENCY_HIGH___S 8 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN0_LOW (0x00141640) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN0_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN0_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN0_LOW__HISTBIN0___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN0_LOW__HISTBIN0___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN0_LOW__HISTBIN0___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN0_LOW___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN0_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN1_LOW (0x00141648) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN1_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN1_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN1_LOW__HISTBIN1___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN1_LOW__HISTBIN1___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN1_LOW__HISTBIN1___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN1_LOW___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN1_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN2_LOW (0x00141650) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN2_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN2_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN2_LOW__HISTBIN2___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN2_LOW__HISTBIN2___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN2_LOW__HISTBIN2___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN2_LOW___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN2_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN3_LOW (0x00141658) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN3_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN3_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN3_LOW__HISTBIN3___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN3_LOW__HISTBIN3___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN3_LOW__HISTBIN3___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN3_LOW___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN3_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN4_LOW (0x00141660) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN4_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN4_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN4_LOW__HISTBIN4___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN4_LOW__HISTBIN4___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN4_LOW__HISTBIN4___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN4_LOW___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN4_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN5_LOW (0x00141668) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN5_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN5_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN5_LOW__HISTBIN5___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN5_LOW__HISTBIN5___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN5_LOW__HISTBIN5___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN5_LOW___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN5_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN6_LOW (0x00141670) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN6_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN6_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN6_LOW__HISTBIN6___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN6_LOW__HISTBIN6___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN6_LOW__HISTBIN6___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN6_LOW___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN6_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN7_LOW (0x00141678) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN7_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN7_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN7_LOW__HISTBIN7___POR 0x000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN7_LOW__HISTBIN7___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN7_LOW__HISTBIN7___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN7_LOW___M 0x00000FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_HISTBIN7_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_LATMAX_LOW (0x00141680) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_LATMAX_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_LATMAX_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_LATMAX_LOW__LATMAX___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_LATMAX_LOW__LATMAX___M 0x000000FF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_LATMAX_LOW__LATMAX___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_LATMAX_LOW___M 0x000000FF +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_LATMAX_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_LOW (0x00141720) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___POR 0x000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFC00 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_LOW__VALUE_LSB___S 10 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_LOW___M 0xFFFFFC00 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_LOW___S 10 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_HIGH (0x00141724) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_HIGH___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_HIGH___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_HIGH__VALUE_MSB___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_HIGH___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MIN_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_LOW (0x00141728) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___POR 0x000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFC00 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_LOW__VALUE_LSB___S 10 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_LOW___M 0xFFFFFC00 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_LOW___S 10 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_HIGH (0x0014172C) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_HIGH___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_HIGH___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_HIGH__VALUE_MSB___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_HIGH___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_ADDR_MAX_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW (0x00141738) +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__CMEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__WREN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__RDEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___M 0x00000010 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__ATOMEN___S 4 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__CMEN___M 0x00000008 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__CMEN___S 3 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__EXCLEN___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__WREN___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__WREN___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__RDEN___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW__RDEN___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_XM_WMAC0_TENUREPRB_FILTER_OPCODE_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW (0x00142000) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW___POR 0x00122752 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW__UNITTYPEID___POR 0x12 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW__UNITCONFID___POR 0x2752 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW__UNITTYPEID___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW__UNITCONFID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW___M 0x00FFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_HIGH (0x00142004) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_HIGH___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_HIGH__QNOCID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_HIGH___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_SWID_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW (0x00142008) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__DUMPFORMAT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__ALARMEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__DUMPEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__GLBEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000020 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__IGNORECTITRIGIN0___S 5 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__DUMPFORMAT___M 0x00000008 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__DUMPFORMAT___S 3 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__ALARMEN___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__ALARMEN___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__DUMPEN___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__DUMPEN___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__GLBEN___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW__GLBEN___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW___M 0x0000002F +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_MAINCTL_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW (0x00142010) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW__PLA___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW__FILTER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW__PLA___M 0x80000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW__PLA___S 31 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW__FILTER___M 0x00000003 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW__FILTER___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW___M 0x80000003 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_EN_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW (0x00142018) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW__PLA___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW__FILTER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW__PLA___M 0x80000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW__PLA___S 31 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW__FILTER___M 0x00000003 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW__FILTER___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW___M 0x80000003 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_STATUS_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW (0x00142020) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW___RWC QCSR_REG_WO +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW__PLA___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW__FILTER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW__PLA___M 0x80000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW__PLA___S 31 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW__FILTER___M 0x00000003 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW__FILTER___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW___M 0x80000003 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ALARM_CLR_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW (0x00142028) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW__PLA___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW__FILTER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW__PLA___M 0x80000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW__PLA___S 31 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW__FILTER___M 0x00000003 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW__FILTER___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW___M 0x80000003 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_ANDINV_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_LOW (0x00142120) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___POR 0x0000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFFC0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_LOW__VALUE_LSB___S 6 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_LOW___M 0xFFFFFFC0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_LOW___S 6 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH (0x00142124) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH__VALUE_MSB___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MIN_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_LOW (0x00142128) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___POR 0x0000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFFC0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_LOW__VALUE_LSB___S 6 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_LOW___M 0xFFFFFFC0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_LOW___S 6 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH (0x0014212C) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH__VALUE_MSB___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_ADDR_MAX_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW (0x00142138) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__ATOMEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__CMEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__EXCLEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__WREN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__RDEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__ATOMEN___M 0x00000010 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__ATOMEN___S 4 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__CMEN___M 0x00000008 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__CMEN___S 3 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__EXCLEN___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__EXCLEN___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__WREN___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__WREN___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__RDEN___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW__RDEN___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_0_OPCODE_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_LOW (0x00142220) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___POR 0x0000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___M 0xFFFFFFC0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_LOW__VALUE_LSB___S 6 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_LOW___M 0xFFFFFFC0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_LOW___S 6 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH (0x00142224) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH__VALUE_MSB___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MIN_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_LOW (0x00142228) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___POR 0x0000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___M 0xFFFFFFC0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_LOW__VALUE_LSB___S 6 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_LOW___M 0xFFFFFFC0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_LOW___S 6 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH (0x0014222C) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH__VALUE_MSB___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_ADDR_MAX_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW (0x00142238) +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__ATOMEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__CMEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__EXCLEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__WREN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__RDEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__ATOMEN___M 0x00000010 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__ATOMEN___S 4 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__CMEN___M 0x00000008 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__CMEN___S 3 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__EXCLEN___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__EXCLEN___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__WREN___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__WREN___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__RDEN___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW__RDEN___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_QXS_SNOC_TRACEPRB_FILTERS_1_OPCODE_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_LOW (0x00143000) +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_LOW___POR 0x00023E6C +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_LOW__UNITTYPEID___POR 0x02 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_LOW__UNITCONFID___POR 0x3E6C +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_LOW__UNITTYPEID___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_LOW__UNITCONFID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_LOW___M 0x00FFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_HIGH (0x00143004) +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_HIGH___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_HIGH__QNOCID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_HIGH___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_SWID_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW (0x00143008) +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__IGNORECTITRIGIN0___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__DUMPEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__GLBEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__IGNORECTITRIGIN0___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__IGNORECTITRIGIN0___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__DUMPEN___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__DUMPEN___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__GLBEN___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW__GLBEN___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW___M 0x00000007 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_MAINCTL_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPGO_LOW (0x00143010) +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPGO_LOW___RWC QCSR_REG_WO +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPGO_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPGO_LOW__DUMPGO___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPGO_LOW__DUMPGO___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPGO_LOW__DUMPGO___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPGO_LOW___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPGO_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPPERIOD_LOW (0x00143018) +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPPERIOD_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPPERIOD_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPPERIOD_LOW__DUMPPERIOD___POR 0x00 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPPERIOD_LOW__DUMPPERIOD___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPPERIOD_LOW__DUMPPERIOD___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPPERIOD_LOW___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPPERIOD_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPTHR_LOW (0x00143020) +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPTHR_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPTHR_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPTHR_LOW__DUMPTHR___POR 0x0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPTHR_LOW__DUMPTHR___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPTHR_LOW__DUMPTHR___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPTHR_LOW___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_DUMPTHR_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMMIN_LOW (0x00143028) +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMMIN_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMMIN_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMMIN_LOW__ALARMMIN___POR 0x0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMMIN_LOW__ALARMMIN___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMMIN_LOW__ALARMMIN___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMMIN_LOW___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMMIN_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMMAX_LOW (0x00143030) +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMMAX_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMMAX_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMMAX_LOW__ALARMMAX___POR 0x0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMMAX_LOW__ALARMMAX___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMMAX_LOW__ALARMMAX___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMMAX_LOW___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMMAX_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMSTATUS_LOW (0x00143038) +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMSTATUS_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMSTATUS_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMSTATUS_LOW__ALARMSTATUS___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMSTATUS_LOW__ALARMSTATUS___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMSTATUS_LOW__ALARMSTATUS___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMSTATUS_LOW___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMSTATUS_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMCLR_LOW (0x00143040) +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMCLR_LOW___RWC QCSR_REG_WO +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMCLR_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMCLR_LOW__ALARMCLR___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMCLR_LOW__ALARMCLR___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMCLR_LOW__ALARMCLR___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMCLR_LOW___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMCLR_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMEN_LOW (0x00143048) +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMEN_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMEN_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMEN_LOW__ALARMEN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMEN_LOW__ALARMEN___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMEN_LOW__ALARMEN___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMEN_LOW___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_ALARMEN_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW (0x00143100) +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW___POR 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__ALARMMODE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__DUMPTHREN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__EVENTSRC___POR 0x1F +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__ALARMMODE___M 0x00000600 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__ALARMMODE___S 9 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__DUMPTHREN___M 0x00000100 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__DUMPTHREN___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__EVENTSRC___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW__EVENTSRC___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW___M 0x0000071F +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0CTL_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0VAL_LOW (0x00143140) +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0VAL_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0VAL_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0VAL_LOW__COUNTER0VAL___POR 0x0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0VAL_LOW__COUNTER0VAL___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0VAL_LOW__COUNTER0VAL___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0VAL_LOW___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER0VAL_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW (0x00143180) +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW___POR 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__ALARMMODE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__DUMPTHREN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__EVENTSRC___POR 0x1F +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__ALARMMODE___M 0x00000600 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__ALARMMODE___S 9 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__DUMPTHREN___M 0x00000100 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__DUMPTHREN___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__EVENTSRC___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW__EVENTSRC___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW___M 0x0000071F +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1CTL_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1VAL_LOW (0x001431C0) +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1VAL_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1VAL_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1VAL_LOW__COUNTER1VAL___POR 0x0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1VAL_LOW__COUNTER1VAL___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1VAL_LOW__COUNTER1VAL___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1VAL_LOW___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER1VAL_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW (0x00143200) +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW___POR 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__ALARMMODE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__DUMPTHREN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__EVENTSRC___POR 0x1F +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__ALARMMODE___M 0x00000600 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__ALARMMODE___S 9 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__DUMPTHREN___M 0x00000100 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__DUMPTHREN___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__EVENTSRC___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW__EVENTSRC___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW___M 0x0000071F +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2CTL_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2VAL_LOW (0x00143240) +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2VAL_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2VAL_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2VAL_LOW__COUNTER2VAL___POR 0x0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2VAL_LOW__COUNTER2VAL___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2VAL_LOW__COUNTER2VAL___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2VAL_LOW___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER2VAL_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW (0x00143280) +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW___POR 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__ALARMMODE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__DUMPTHREN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__EVENTSRC___POR 0x1F +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__ALARMMODE___M 0x00000600 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__ALARMMODE___S 9 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__DUMPTHREN___M 0x00000100 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__DUMPTHREN___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__EVENTSRC___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW__EVENTSRC___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW___M 0x0000071F +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3CTL_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3VAL_LOW (0x001432C0) +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3VAL_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3VAL_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3VAL_LOW__COUNTER3VAL___POR 0x0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3VAL_LOW__COUNTER3VAL___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3VAL_LOW__COUNTER3VAL___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3VAL_LOW___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER3VAL_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW (0x00143300) +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW___POR 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__ALARMMODE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__DUMPTHREN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__EVENTSRC___POR 0x1F +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__ALARMMODE___M 0x00000600 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__ALARMMODE___S 9 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__DUMPTHREN___M 0x00000100 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__DUMPTHREN___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__EVENTSRC___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW__EVENTSRC___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW___M 0x0000071F +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4CTL_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4VAL_LOW (0x00143340) +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4VAL_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4VAL_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4VAL_LOW__COUNTER4VAL___POR 0x0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4VAL_LOW__COUNTER4VAL___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4VAL_LOW__COUNTER4VAL___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4VAL_LOW___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER4VAL_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW (0x00143380) +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW___POR 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__ALARMMODE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__DUMPTHREN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__EVENTSRC___POR 0x1F +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__ALARMMODE___M 0x00000600 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__ALARMMODE___S 9 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__DUMPTHREN___M 0x00000100 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__DUMPTHREN___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__EVENTSRC___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW__EVENTSRC___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW___M 0x0000071F +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5CTL_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5VAL_LOW (0x001433C0) +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5VAL_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5VAL_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5VAL_LOW__COUNTER5VAL___POR 0x0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5VAL_LOW__COUNTER5VAL___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5VAL_LOW__COUNTER5VAL___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5VAL_LOW___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER5VAL_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW (0x00143400) +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW___POR 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__ALARMMODE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__DUMPTHREN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__EVENTSRC___POR 0x1F +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__ALARMMODE___M 0x00000600 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__ALARMMODE___S 9 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__DUMPTHREN___M 0x00000100 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__DUMPTHREN___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__EVENTSRC___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW__EVENTSRC___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW___M 0x0000071F +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6CTL_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6VAL_LOW (0x00143440) +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6VAL_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6VAL_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6VAL_LOW__COUNTER6VAL___POR 0x0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6VAL_LOW__COUNTER6VAL___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6VAL_LOW__COUNTER6VAL___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6VAL_LOW___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER6VAL_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW (0x00143480) +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW___RWC QCSR_REG_RW +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW___POR 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__ALARMMODE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__DUMPTHREN___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__EVENTSRC___POR 0x1F +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__ALARMMODE___M 0x00000600 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__ALARMMODE___S 9 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__DUMPTHREN___M 0x00000100 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__DUMPTHREN___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__EVENTSRC___M 0x0000001F +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW__EVENTSRC___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW___M 0x0000071F +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7CTL_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7VAL_LOW (0x001434C0) +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7VAL_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7VAL_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7VAL_LOW__COUNTER7VAL___POR 0x0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7VAL_LOW__COUNTER7VAL___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7VAL_LOW__COUNTER7VAL___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7VAL_LOW___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_EC_COUNTER7VAL_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW (0x00144000) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW___POR 0x000EF0EA +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW__UNITTYPEID___POR 0x0E +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW__UNITCONFID___POR 0xF0EA +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW__UNITTYPEID___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW__UNITCONFID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW___M 0x00FFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_HIGH (0x00144004) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_HIGH___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_HIGH__QNOCID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_HIGH___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SWID_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW (0x00144100) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__TRPENDING___S 12 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_XFER___S 11 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PXFER___S 10 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PWAIT___S 9 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_PBUSY___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_IDLE___S 7 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__RSP_BUSY___S 6 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_XFER___S 5 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PXFER___S 4 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PWAIT___S 3 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_PBUSY___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_IDLE___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW__REQ_BUSY___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW___M 0x00001FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_PM_WCSS_DBG_SBM_SENSEIN0_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW (0x00144200) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW___POR 0x000EF0EA +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW__UNITTYPEID___POR 0x0E +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW__UNITCONFID___POR 0xF0EA +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW__UNITTYPEID___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW__UNITCONFID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW___M 0x00FFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_HIGH (0x00144204) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_HIGH___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_HIGH__QNOCID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_HIGH___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SWID_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW (0x00144300) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__TRPENDING___S 12 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_XFER___S 11 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PXFER___S 10 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PWAIT___S 9 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_PBUSY___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_IDLE___S 7 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__RSP_BUSY___S 6 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_XFER___S 5 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PXFER___S 4 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PWAIT___S 3 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_PBUSY___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_IDLE___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW__REQ_BUSY___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW___M 0x00001FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHM_RET_AHB_SBM_SENSEIN0_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW (0x00144400) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW___POR 0x000EF0EA +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW__UNITTYPEID___POR 0x0E +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW__UNITCONFID___POR 0xF0EA +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW__UNITTYPEID___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW__UNITCONFID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW___M 0x00FFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_HIGH (0x00144404) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_HIGH___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_HIGH__QNOCID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_HIGH___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SWID_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW (0x00144500) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__TRPENDING___S 12 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_XFER___S 11 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PXFER___S 10 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PWAIT___S 9 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_PBUSY___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_IDLE___S 7 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__RSP_BUSY___S 6 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_XFER___S 5 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PXFER___S 4 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PWAIT___S 3 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_PBUSY___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_IDLE___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW__REQ_BUSY___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW___M 0x00001FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QHS_RET_AHB_SBM_SENSEIN0_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW (0x00144600) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW___POR 0x000EF0EA +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW__UNITTYPEID___POR 0x0E +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW__UNITCONFID___POR 0xF0EA +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW__UNITTYPEID___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW__UNITCONFID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW___M 0x00FFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_HIGH (0x00144604) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_HIGH___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_HIGH__QNOCID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_HIGH___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SWID_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW (0x00144700) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__TRPENDING___S 12 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_XFER___S 11 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PXFER___S 10 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PWAIT___S 9 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_PBUSY___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_IDLE___S 7 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__RSP_BUSY___S 6 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_XFER___S 5 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PXFER___S 4 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PWAIT___S 3 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_PBUSY___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_IDLE___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW__REQ_BUSY___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW___M 0x00001FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_PHYA_SBM_SENSEIN0_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW (0x00144A00) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW___POR 0x000EF0EA +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW__UNITTYPEID___POR 0x0E +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW__UNITCONFID___POR 0xF0EA +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW__UNITTYPEID___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW__UNITCONFID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW___M 0x00FFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_HIGH (0x00144A04) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_HIGH___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_HIGH__QNOCID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_HIGH___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SWID_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW (0x00144B00) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__TRPENDING___S 12 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_XFER___S 11 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PXFER___S 10 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PWAIT___S 9 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_PBUSY___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_IDLE___S 7 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__RSP_BUSY___S 6 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_XFER___S 5 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PXFER___S 4 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PWAIT___S 3 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_PBUSY___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_IDLE___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW__REQ_BUSY___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW___M 0x00001FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXM_SNOC_SBM_SENSEIN0_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW (0x00144C00) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW___POR 0x000EF0EA +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW__UNITTYPEID___POR 0x0E +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW__UNITCONFID___POR 0xF0EA +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW__UNITTYPEID___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW__UNITCONFID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW___M 0x00FFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_HIGH (0x00144C04) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_HIGH___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_HIGH__QNOCID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_HIGH___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SWID_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW (0x00144D00) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__TRPENDING___S 12 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_XFER___S 11 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PXFER___S 10 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PWAIT___S 9 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_PBUSY___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_IDLE___S 7 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__RSP_BUSY___S 6 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_XFER___S 5 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PXFER___S 4 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PWAIT___S 3 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_PBUSY___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_IDLE___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW__REQ_BUSY___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW___M 0x00001FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_PHYA_SBM_SENSEIN0_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW (0x00145000) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW___POR 0x000EF0EA +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW__UNITTYPEID___POR 0x0E +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW__UNITCONFID___POR 0xF0EA +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW__UNITTYPEID___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW__UNITCONFID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW___M 0x00FFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_HIGH (0x00145004) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_HIGH___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_HIGH__QNOCID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_HIGH___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SWID_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW (0x00145100) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__TRPENDING___S 12 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_XFER___S 11 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PXFER___S 10 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PWAIT___S 9 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_PBUSY___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_IDLE___S 7 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__RSP_BUSY___S 6 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_XFER___S 5 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PXFER___S 4 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PWAIT___S 3 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_PBUSY___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_IDLE___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW__REQ_BUSY___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW___M 0x00001FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_QXS_SNOC_SBM_SENSEIN0_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW (0x00145400) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW___POR 0x000E533C +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW__UNITTYPEID___POR 0x0E +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW__UNITCONFID___POR 0x533C +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW__UNITTYPEID___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW__UNITCONFID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW___M 0x00FFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_HIGH (0x00145404) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_HIGH___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_HIGH__QNOCID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_HIGH___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SWID_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW (0x00145500) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__COEX_APB2AXI_NOPX___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__COEX_APB2AXI_NOPX___M 0x00002000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__COEX_APB2AXI_NOPX___S 13 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__TRPENDING___S 12 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_XFER___S 11 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PXFER___S 10 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PWAIT___S 9 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_PBUSY___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_IDLE___S 7 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__RSP_BUSY___S 6 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_XFER___S 5 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PXFER___S 4 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PWAIT___S 3 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_PBUSY___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_IDLE___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW__REQ_BUSY___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW___M 0x00003FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_COEX_SBM_SENSEIN0_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW (0x00145600) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW___POR 0x000E4249 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW__UNITTYPEID___POR 0x0E +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW__UNITCONFID___POR 0x4249 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW__UNITTYPEID___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW__UNITCONFID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW___M 0x00FFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_HIGH (0x00145604) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_HIGH___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_HIGH__QNOCID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_HIGH___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SWID_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW (0x00145700) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWREADY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWVALID___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_5___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_4___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_3___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_2___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_1___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_0___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARREADY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARVALID___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_5___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_4___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_3___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_2___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_1___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_0___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWREADY___M 0x80000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWREADY___S 31 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWVALID___M 0x40000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWVALID___S 30 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_5___M 0x20000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_5___S 29 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_4___M 0x10000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_4___S 28 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_3___M 0x08000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_3___S 27 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_2___M 0x04000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_2___S 26 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_1___M 0x02000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_1___S 25 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_0___M 0x01000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__AWID_0___S 24 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARREADY___M 0x00800000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARREADY___S 23 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARVALID___M 0x00400000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARVALID___S 22 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_5___M 0x00200000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_5___S 21 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_4___M 0x00100000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_4___S 20 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_3___M 0x00080000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_3___S 19 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_2___M 0x00040000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_2___S 18 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_1___M 0x00020000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_1___S 17 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_0___M 0x00010000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__ARID_0___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__TRPENDING___S 12 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_XFER___S 11 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PXFER___S 10 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PWAIT___S 9 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_PBUSY___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_IDLE___S 7 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__RSP_BUSY___S 6 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_XFER___S 5 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PXFER___S 4 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PWAIT___S 3 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_PBUSY___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_IDLE___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW__REQ_BUSY___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW___M 0xFFFF1FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH (0x00145704) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BREADY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BVALID___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_5___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_4___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_3___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_2___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_1___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_0___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__WREADY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__WVALID___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RREADY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RVALID___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_5___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_4___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_3___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_2___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_1___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_0___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BREADY___M 0x00800000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BREADY___S 23 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BVALID___M 0x00400000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BVALID___S 22 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_5___M 0x00200000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_5___S 21 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_4___M 0x00100000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_4___S 20 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_3___M 0x00080000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_3___S 19 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_2___M 0x00040000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_2___S 18 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_1___M 0x00020000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_1___S 17 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_0___M 0x00010000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__BID_0___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__WREADY___M 0x00008000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__WREADY___S 15 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__WVALID___M 0x00004000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__WVALID___S 14 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RREADY___M 0x00000080 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RREADY___S 7 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RVALID___M 0x00000040 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RVALID___S 6 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_5___M 0x00000020 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_5___S 5 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_4___M 0x00000010 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_4___S 4 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_3___M 0x00000008 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_3___S 3 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_2___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_2___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_1___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_1___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_0___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH__RID_0___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH___M 0x00FFC0FF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_REO_SBM_SENSEIN0_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW (0x00145800) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW___POR 0x000E4249 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW__UNITTYPEID___POR 0x0E +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW__UNITCONFID___POR 0x4249 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW__UNITTYPEID___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW__UNITCONFID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW___M 0x00FFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_HIGH (0x00145804) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_HIGH___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_HIGH__QNOCID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_HIGH___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SWID_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW (0x00145900) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWREADY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWVALID___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_5___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_4___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_3___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_2___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_1___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_0___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARREADY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARVALID___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_5___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_4___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_3___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_2___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_1___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_0___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWREADY___M 0x80000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWREADY___S 31 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWVALID___M 0x40000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWVALID___S 30 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_5___M 0x20000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_5___S 29 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_4___M 0x10000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_4___S 28 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_3___M 0x08000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_3___S 27 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_2___M 0x04000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_2___S 26 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_1___M 0x02000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_1___S 25 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_0___M 0x01000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__AWID_0___S 24 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARREADY___M 0x00800000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARREADY___S 23 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARVALID___M 0x00400000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARVALID___S 22 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_5___M 0x00200000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_5___S 21 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_4___M 0x00100000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_4___S 20 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_3___M 0x00080000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_3___S 19 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_2___M 0x00040000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_2___S 18 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_1___M 0x00020000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_1___S 17 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_0___M 0x00010000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__ARID_0___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__TRPENDING___S 12 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_XFER___S 11 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PXFER___S 10 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PWAIT___S 9 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_PBUSY___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_IDLE___S 7 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__RSP_BUSY___S 6 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_XFER___S 5 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PXFER___S 4 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PWAIT___S 3 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_PBUSY___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_IDLE___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW__REQ_BUSY___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW___M 0xFFFF1FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH (0x00145904) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BREADY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BVALID___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_5___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_4___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_3___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_2___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_1___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_0___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__WREADY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__WVALID___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RREADY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RVALID___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_5___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_4___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_3___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_2___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_1___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_0___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BREADY___M 0x00800000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BREADY___S 23 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BVALID___M 0x00400000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BVALID___S 22 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_5___M 0x00200000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_5___S 21 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_4___M 0x00100000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_4___S 20 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_3___M 0x00080000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_3___S 19 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_2___M 0x00040000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_2___S 18 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_1___M 0x00020000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_1___S 17 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_0___M 0x00010000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__BID_0___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__WREADY___M 0x00008000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__WREADY___S 15 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__WVALID___M 0x00004000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__WVALID___S 14 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RREADY___M 0x00000080 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RREADY___S 7 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RVALID___M 0x00000040 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RVALID___S 6 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_5___M 0x00000020 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_5___S 5 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_4___M 0x00000010 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_4___S 4 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_3___M 0x00000008 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_3___S 3 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_2___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_2___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_1___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_1___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_0___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH__RID_0___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH___M 0x00FFC0FF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TCL_SBM_SENSEIN0_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW (0x00145A00) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW___POR 0x000E4249 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW__UNITTYPEID___POR 0x0E +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW__UNITCONFID___POR 0x4249 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW__UNITTYPEID___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW__UNITCONFID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW___M 0x00FFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_HIGH (0x00145A04) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_HIGH___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_HIGH__QNOCID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_HIGH___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SWID_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW (0x00145B00) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWREADY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWVALID___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_5___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_4___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_3___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_2___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_1___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_0___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARREADY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARVALID___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_5___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_4___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_3___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_2___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_1___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_0___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWREADY___M 0x80000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWREADY___S 31 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWVALID___M 0x40000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWVALID___S 30 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_5___M 0x20000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_5___S 29 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_4___M 0x10000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_4___S 28 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_3___M 0x08000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_3___S 27 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_2___M 0x04000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_2___S 26 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_1___M 0x02000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_1___S 25 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_0___M 0x01000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__AWID_0___S 24 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARREADY___M 0x00800000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARREADY___S 23 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARVALID___M 0x00400000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARVALID___S 22 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_5___M 0x00200000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_5___S 21 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_4___M 0x00100000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_4___S 20 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_3___M 0x00080000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_3___S 19 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_2___M 0x00040000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_2___S 18 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_1___M 0x00020000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_1___S 17 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_0___M 0x00010000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__ARID_0___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__TRPENDING___S 12 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_XFER___S 11 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PXFER___S 10 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PWAIT___S 9 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_PBUSY___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_IDLE___S 7 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__RSP_BUSY___S 6 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_XFER___S 5 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PXFER___S 4 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PWAIT___S 3 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_PBUSY___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_IDLE___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW__REQ_BUSY___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW___M 0xFFFF1FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH (0x00145B04) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BREADY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BVALID___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_5___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_4___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_3___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_2___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_1___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_0___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__WREADY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__WVALID___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RREADY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RVALID___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_5___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_4___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_3___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_2___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_1___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_0___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BREADY___M 0x00800000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BREADY___S 23 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BVALID___M 0x00400000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BVALID___S 22 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_5___M 0x00200000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_5___S 21 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_4___M 0x00100000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_4___S 20 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_3___M 0x00080000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_3___S 19 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_2___M 0x00040000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_2___S 18 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_1___M 0x00020000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_1___S 17 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_0___M 0x00010000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__BID_0___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__WREADY___M 0x00008000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__WREADY___S 15 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__WVALID___M 0x00004000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__WVALID___S 14 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RREADY___M 0x00000080 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RREADY___S 7 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RVALID___M 0x00000040 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RVALID___S 6 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_5___M 0x00000020 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_5___S 5 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_4___M 0x00000010 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_4___S 4 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_3___M 0x00000008 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_3___S 3 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_2___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_2___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_1___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_1___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_0___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH__RID_0___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH___M 0x00FFC0FF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_TQM_SBM_SENSEIN0_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW (0x00145C00) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW___POR 0x000E4249 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW__UNITTYPEID___POR 0x0E +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW__UNITCONFID___POR 0x4249 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW__UNITTYPEID___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW__UNITCONFID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW___M 0x00FFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_HIGH (0x00145C04) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_HIGH___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_HIGH__QNOCID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_HIGH___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SWID_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW (0x00145D00) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWREADY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWVALID___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_5___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_4___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_3___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_2___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_1___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_0___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARREADY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARVALID___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_5___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_4___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_3___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_2___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_1___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_0___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWREADY___M 0x80000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWREADY___S 31 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWVALID___M 0x40000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWVALID___S 30 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_5___M 0x20000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_5___S 29 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_4___M 0x10000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_4___S 28 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_3___M 0x08000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_3___S 27 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_2___M 0x04000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_2___S 26 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_1___M 0x02000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_1___S 25 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_0___M 0x01000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__AWID_0___S 24 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARREADY___M 0x00800000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARREADY___S 23 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARVALID___M 0x00400000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARVALID___S 22 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_5___M 0x00200000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_5___S 21 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_4___M 0x00100000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_4___S 20 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_3___M 0x00080000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_3___S 19 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_2___M 0x00040000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_2___S 18 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_1___M 0x00020000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_1___S 17 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_0___M 0x00010000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__ARID_0___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__TRPENDING___S 12 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_XFER___S 11 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PXFER___S 10 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PWAIT___S 9 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_PBUSY___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_IDLE___S 7 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__RSP_BUSY___S 6 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_XFER___S 5 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PXFER___S 4 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PWAIT___S 3 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_PBUSY___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_IDLE___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW__REQ_BUSY___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW___M 0xFFFF1FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH (0x00145D04) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BREADY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BVALID___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_5___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_4___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_3___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_2___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_1___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_0___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__WREADY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__WVALID___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RREADY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RVALID___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_5___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_4___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_3___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_2___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_1___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_0___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BREADY___M 0x00800000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BREADY___S 23 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BVALID___M 0x00400000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BVALID___S 22 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_5___M 0x00200000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_5___S 21 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_4___M 0x00100000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_4___S 20 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_3___M 0x00080000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_3___S 19 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_2___M 0x00040000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_2___S 18 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_1___M 0x00020000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_1___S 17 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_0___M 0x00010000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__BID_0___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__WREADY___M 0x00008000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__WREADY___S 15 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__WVALID___M 0x00004000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__WVALID___S 14 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RREADY___M 0x00000080 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RREADY___S 7 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RVALID___M 0x00000040 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RVALID___S 6 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_5___M 0x00000020 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_5___S 5 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_4___M 0x00000010 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_4___S 4 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_3___M 0x00000008 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_3___S 3 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_2___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_2___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_1___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_1___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_0___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH__RID_0___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH___M 0x00FFC0FF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WBM_SBM_SENSEIN0_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW (0x00145E00) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW___POR 0x000E4249 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW__UNITTYPEID___POR 0x0E +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW__UNITCONFID___POR 0x4249 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW__UNITTYPEID___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW__UNITCONFID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW___M 0x00FFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_HIGH (0x00145E04) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_HIGH___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_HIGH__QNOCID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_HIGH___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SWID_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW (0x00145F00) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWREADY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWVALID___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_5___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_4___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_3___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_2___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_1___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_0___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARREADY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARVALID___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_5___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_4___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_3___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_2___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_1___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_0___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWREADY___M 0x80000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWREADY___S 31 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWVALID___M 0x40000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWVALID___S 30 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_5___M 0x20000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_5___S 29 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_4___M 0x10000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_4___S 28 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_3___M 0x08000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_3___S 27 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_2___M 0x04000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_2___S 26 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_1___M 0x02000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_1___S 25 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_0___M 0x01000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__AWID_0___S 24 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARREADY___M 0x00800000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARREADY___S 23 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARVALID___M 0x00400000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARVALID___S 22 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_5___M 0x00200000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_5___S 21 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_4___M 0x00100000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_4___S 20 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_3___M 0x00080000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_3___S 19 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_2___M 0x00040000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_2___S 18 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_1___M 0x00020000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_1___S 17 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_0___M 0x00010000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__ARID_0___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__TRPENDING___S 12 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_XFER___S 11 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PXFER___S 10 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PWAIT___S 9 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_PBUSY___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_IDLE___S 7 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__RSP_BUSY___S 6 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_XFER___S 5 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PXFER___S 4 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PWAIT___S 3 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_PBUSY___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_IDLE___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW__REQ_BUSY___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW___M 0xFFFF1FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH (0x00145F04) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BREADY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BVALID___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_5___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_4___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_3___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_2___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_1___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_0___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__WREADY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__WVALID___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RREADY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RVALID___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_5___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_4___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_3___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_2___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_1___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_0___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BREADY___M 0x00800000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BREADY___S 23 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BVALID___M 0x00400000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BVALID___S 22 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_5___M 0x00200000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_5___S 21 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_4___M 0x00100000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_4___S 20 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_3___M 0x00080000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_3___S 19 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_2___M 0x00040000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_2___S 18 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_1___M 0x00020000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_1___S 17 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_0___M 0x00010000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__BID_0___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__WREADY___M 0x00008000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__WREADY___S 15 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__WVALID___M 0x00004000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__WVALID___S 14 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RREADY___M 0x00000080 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RREADY___S 7 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RVALID___M 0x00000040 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RVALID___S 6 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_5___M 0x00000020 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_5___S 5 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_4___M 0x00000010 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_4___S 4 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_3___M 0x00000008 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_3___S 3 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_2___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_2___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_1___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_1___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_0___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH__RID_0___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH___M 0x00FFC0FF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XM_WMAC0_SBM_SENSEIN0_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW (0x00146200) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW___POR 0x000EF0EA +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW__UNITTYPEID___POR 0x0E +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW__UNITCONFID___POR 0xF0EA +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW__UNITTYPEID___M 0x00FF0000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW__UNITTYPEID___S 16 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW__UNITCONFID___M 0x0000FFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW__UNITCONFID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW___M 0x00FFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_LOW___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_HIGH (0x00146204) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_HIGH___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_HIGH___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_HIGH__QNOCID___POR 0xA8AF23E2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_HIGH__QNOCID___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_HIGH__QNOCID___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_HIGH___M 0xFFFFFFFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SWID_HIGH___S 0 + +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW (0x00146300) +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW___RWC QCSR_REG_RO +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW___POR 0x00000000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__TRPENDING___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_XFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PXFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PWAIT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PBUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_IDLE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_BUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_XFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PXFER___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PWAIT___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PBUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_IDLE___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_BUSY___POR 0x0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__TRPENDING___M 0x00001000 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__TRPENDING___S 12 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_XFER___M 0x00000800 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_XFER___S 11 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PXFER___M 0x00000400 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PXFER___S 10 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PWAIT___M 0x00000200 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PWAIT___S 9 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PBUSY___M 0x00000100 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_PBUSY___S 8 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_IDLE___M 0x00000080 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_IDLE___S 7 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_BUSY___M 0x00000040 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__RSP_BUSY___S 6 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_XFER___M 0x00000020 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_XFER___S 5 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PXFER___M 0x00000010 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PXFER___S 4 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PWAIT___M 0x00000008 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PWAIT___S 3 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PBUSY___M 0x00000004 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_PBUSY___S 2 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_IDLE___M 0x00000002 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_IDLE___S 1 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_BUSY___M 0x00000001 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW__REQ_BUSY___S 0 +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW___M 0x00001FFF +#define UMAC_NOC_UMAC_NOC_FABRIC_XFERMONITOR_XS_CMEM_SBM_SENSEIN0_LOW___S 0 + + +#define APB_TSLV_BASE (0x00B40000) + +#define APB_TSLV_ABT_HW_VERSION (0x00B40000) +#define APB_TSLV_ABT_HW_VERSION___RWC QCSR_REG_RO +#define APB_TSLV_ABT_HW_VERSION___POR 0x10000000 +#define APB_TSLV_ABT_HW_VERSION__MAJOR___POR 0x1 +#define APB_TSLV_ABT_HW_VERSION__MINOR___POR 0x000 +#define APB_TSLV_ABT_HW_VERSION__STEP___POR 0x0000 +#define APB_TSLV_ABT_HW_VERSION__MAJOR___M 0xF0000000 +#define APB_TSLV_ABT_HW_VERSION__MAJOR___S 28 +#define APB_TSLV_ABT_HW_VERSION__MINOR___M 0x0FFF0000 +#define APB_TSLV_ABT_HW_VERSION__MINOR___S 16 +#define APB_TSLV_ABT_HW_VERSION__STEP___M 0x0000FFFF +#define APB_TSLV_ABT_HW_VERSION__STEP___S 0 +#define APB_TSLV_ABT_HW_VERSION___M 0xFFFFFFFF +#define APB_TSLV_ABT_HW_VERSION___S 0 + +#define APB_TSLV_ABT_INST_ID (0x00B40004) +#define APB_TSLV_ABT_INST_ID___RWC QCSR_REG_RW +#define APB_TSLV_ABT_INST_ID___POR 0x00000000 +#define APB_TSLV_ABT_INST_ID__INSTID___POR 0x00000000 +#define APB_TSLV_ABT_INST_ID__INSTID___M 0xFFFFFFFF +#define APB_TSLV_ABT_INST_ID__INSTID___S 0 +#define APB_TSLV_ABT_INST_ID___M 0xFFFFFFFF +#define APB_TSLV_ABT_INST_ID___S 0 + +#define APB_TSLV_ABT_NUM_SLAVES (0x00B40008) +#define APB_TSLV_ABT_NUM_SLAVES___RWC QCSR_REG_RO +#define APB_TSLV_ABT_NUM_SLAVES___POR 0x00000009 +#define APB_TSLV_ABT_NUM_SLAVES__NUMSLAVES___POR 0x9 +#define APB_TSLV_ABT_NUM_SLAVES__NUMSLAVES___M 0x0000003F +#define APB_TSLV_ABT_NUM_SLAVES__NUMSLAVES___S 0 +#define APB_TSLV_ABT_NUM_SLAVES___M 0x0000003F +#define APB_TSLV_ABT_NUM_SLAVES___S 0 + +#define APB_TSLV_ABT_TIMER_LOADVAL (0x00B4000C) +#define APB_TSLV_ABT_TIMER_LOADVAL___RWC QCSR_REG_RW +#define APB_TSLV_ABT_TIMER_LOADVAL___POR 0x000000FF +#define APB_TSLV_ABT_TIMER_LOADVAL__LOADVAL___POR 0xFF +#define APB_TSLV_ABT_TIMER_LOADVAL__LOADVAL___M 0x000000FF +#define APB_TSLV_ABT_TIMER_LOADVAL__LOADVAL___S 0 +#define APB_TSLV_ABT_TIMER_LOADVAL___M 0x000000FF +#define APB_TSLV_ABT_TIMER_LOADVAL___S 0 + +#define APB_TSLV_ABT_TIMER_MODE (0x00B40010) +#define APB_TSLV_ABT_TIMER_MODE___RWC QCSR_REG_RW +#define APB_TSLV_ABT_TIMER_MODE___POR 0x00000000 +#define APB_TSLV_ABT_TIMER_MODE__MODE___POR 0x0 +#define APB_TSLV_ABT_TIMER_MODE__MODE___M 0x00000001 +#define APB_TSLV_ABT_TIMER_MODE__MODE___S 0 +#define APB_TSLV_ABT_TIMER_MODE___M 0x00000001 +#define APB_TSLV_ABT_TIMER_MODE___S 0 + +#define APB_TSLV_ABT_INTR_STATUS (0x00B40014) +#define APB_TSLV_ABT_INTR_STATUS___RWC QCSR_REG_RO +#define APB_TSLV_ABT_INTR_STATUS___POR 0x00000000 +#define APB_TSLV_ABT_INTR_STATUS__INTRSTATUS___POR 0x0 +#define APB_TSLV_ABT_INTR_STATUS__INTRSTATUS___M 0x00000001 +#define APB_TSLV_ABT_INTR_STATUS__INTRSTATUS___S 0 +#define APB_TSLV_ABT_INTR_STATUS___M 0x00000001 +#define APB_TSLV_ABT_INTR_STATUS___S 0 + +#define APB_TSLV_ABT_INTR_CLEAR (0x00B40018) +#define APB_TSLV_ABT_INTR_CLEAR___RWC QCSR_REG_WO +#define APB_TSLV_ABT_INTR_CLEAR___POR 0x00000000 +#define APB_TSLV_ABT_INTR_CLEAR__INTRCLEAR___POR 0x0 +#define APB_TSLV_ABT_INTR_CLEAR__INTRCLEAR___M 0x00000001 +#define APB_TSLV_ABT_INTR_CLEAR__INTRCLEAR___S 0 +#define APB_TSLV_ABT_INTR_CLEAR___M 0x00000001 +#define APB_TSLV_ABT_INTR_CLEAR___S 0 + +#define APB_TSLV_ABT_INTR_ENABLE (0x00B4001C) +#define APB_TSLV_ABT_INTR_ENABLE___RWC QCSR_REG_RW +#define APB_TSLV_ABT_INTR_ENABLE___POR 0x00000000 +#define APB_TSLV_ABT_INTR_ENABLE__INTRENABLE___POR 0x0 +#define APB_TSLV_ABT_INTR_ENABLE__INTRENABLE___M 0x00000001 +#define APB_TSLV_ABT_INTR_ENABLE__INTRENABLE___S 0 +#define APB_TSLV_ABT_INTR_ENABLE___M 0x00000001 +#define APB_TSLV_ABT_INTR_ENABLE___S 0 + +#define APB_TSLV_ABT_SYND_VALID (0x00B40020) +#define APB_TSLV_ABT_SYND_VALID___RWC QCSR_REG_RO +#define APB_TSLV_ABT_SYND_VALID___POR 0x00000000 +#define APB_TSLV_ABT_SYND_VALID__SYNDVALID___POR 0x0 +#define APB_TSLV_ABT_SYND_VALID__SYNDVALID___M 0x00000001 +#define APB_TSLV_ABT_SYND_VALID__SYNDVALID___S 0 +#define APB_TSLV_ABT_SYND_VALID___M 0x00000001 +#define APB_TSLV_ABT_SYND_VALID___S 0 + +#define APB_TSLV_ABT_SYND_CLEAR (0x00B40024) +#define APB_TSLV_ABT_SYND_CLEAR___RWC QCSR_REG_WO +#define APB_TSLV_ABT_SYND_CLEAR___POR 0x00000000 +#define APB_TSLV_ABT_SYND_CLEAR__SYNDCLEAR___POR 0x0 +#define APB_TSLV_ABT_SYND_CLEAR__SYNDCLEAR___M 0x00000001 +#define APB_TSLV_ABT_SYND_CLEAR__SYNDCLEAR___S 0 +#define APB_TSLV_ABT_SYND_CLEAR___M 0x00000001 +#define APB_TSLV_ABT_SYND_CLEAR___S 0 + +#define APB_TSLV_ABT_SYND_ID (0x00B40028) +#define APB_TSLV_ABT_SYND_ID___RWC QCSR_REG_RO +#define APB_TSLV_ABT_SYND_ID___POR 0x00000000 +#define APB_TSLV_ABT_SYND_ID__BID___POR 0x0 +#define APB_TSLV_ABT_SYND_ID__PID___POR 0x00 +#define APB_TSLV_ABT_SYND_ID__MID___POR 0x00 +#define APB_TSLV_ABT_SYND_ID__BID___M 0x0000E000 +#define APB_TSLV_ABT_SYND_ID__BID___S 13 +#define APB_TSLV_ABT_SYND_ID__PID___M 0x00001F00 +#define APB_TSLV_ABT_SYND_ID__PID___S 8 +#define APB_TSLV_ABT_SYND_ID__MID___M 0x000000FF +#define APB_TSLV_ABT_SYND_ID__MID___S 0 +#define APB_TSLV_ABT_SYND_ID___M 0x0000FFFF +#define APB_TSLV_ABT_SYND_ID___S 0 + +#define APB_TSLV_ABT_SYND_ADDR0 (0x00B4002C) +#define APB_TSLV_ABT_SYND_ADDR0___RWC QCSR_REG_RO +#define APB_TSLV_ABT_SYND_ADDR0___POR 0x00000000 +#define APB_TSLV_ABT_SYND_ADDR0__SYNDADDR0___POR 0x00000000 +#define APB_TSLV_ABT_SYND_ADDR0__SYNDADDR0___M 0xFFFFFFFF +#define APB_TSLV_ABT_SYND_ADDR0__SYNDADDR0___S 0 +#define APB_TSLV_ABT_SYND_ADDR0___M 0xFFFFFFFF +#define APB_TSLV_ABT_SYND_ADDR0___S 0 + +#define APB_TSLV_ABT_SYND_ADDR1 (0x00B40030) +#define APB_TSLV_ABT_SYND_ADDR1___RWC QCSR_REG_RO +#define APB_TSLV_ABT_SYND_ADDR1___POR 0x00000000 +#define APB_TSLV_ABT_SYND_ADDR1__SYNDADDR1___POR 0x00000000 +#define APB_TSLV_ABT_SYND_ADDR1__SYNDADDR1___M 0xFFFFFFFF +#define APB_TSLV_ABT_SYND_ADDR1__SYNDADDR1___S 0 +#define APB_TSLV_ABT_SYND_ADDR1___M 0xFFFFFFFF +#define APB_TSLV_ABT_SYND_ADDR1___S 0 + +#define APB_TSLV_ABT_SYND_HREADY (0x00B40034) +#define APB_TSLV_ABT_SYND_HREADY___RWC QCSR_REG_RO +#define APB_TSLV_ABT_SYND_HREADY___POR 0xFFFFFFFF +#define APB_TSLV_ABT_SYND_HREADY__SYNDHREADY___POR 0xFFFFFFFF +#define APB_TSLV_ABT_SYND_HREADY__SYNDHREADY___M 0xFFFFFFFF +#define APB_TSLV_ABT_SYND_HREADY__SYNDHREADY___S 0 +#define APB_TSLV_ABT_SYND_HREADY___M 0xFFFFFFFF +#define APB_TSLV_ABT_SYND_HREADY___S 0 + + +#define TOP_CMN_BASE (0x00B50000) + +#define TOP_CMN_WCSS_WCMN_R0_WCSS_CORE_HW_VERSION (0x00B50000) +#define TOP_CMN_WCSS_WCMN_R0_WCSS_CORE_HW_VERSION___RWC QCSR_REG_RO +#define TOP_CMN_WCSS_WCMN_R0_WCSS_CORE_HW_VERSION___POR 0x10000000 +#define TOP_CMN_WCSS_WCMN_R0_WCSS_CORE_HW_VERSION__MAJOR___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_WCSS_CORE_HW_VERSION__MINOR___POR 0x000 +#define TOP_CMN_WCSS_WCMN_R0_WCSS_CORE_HW_VERSION__STEP___POR 0x0000 +#define TOP_CMN_WCSS_WCMN_R0_WCSS_CORE_HW_VERSION__MAJOR___M 0xF0000000 +#define TOP_CMN_WCSS_WCMN_R0_WCSS_CORE_HW_VERSION__MAJOR___S 28 +#define TOP_CMN_WCSS_WCMN_R0_WCSS_CORE_HW_VERSION__MINOR___M 0x0FFF0000 +#define TOP_CMN_WCSS_WCMN_R0_WCSS_CORE_HW_VERSION__MINOR___S 16 +#define TOP_CMN_WCSS_WCMN_R0_WCSS_CORE_HW_VERSION__STEP___M 0x0000FFFF +#define TOP_CMN_WCSS_WCMN_R0_WCSS_CORE_HW_VERSION__STEP___S 0 +#define TOP_CMN_WCSS_WCMN_R0_WCSS_CORE_HW_VERSION___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_WCSS_CORE_HW_VERSION___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_CLK_GEN_CTRL (0x00B50004) +#define TOP_CMN_WCSS_WCMN_R0_CLK_GEN_CTRL___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_CLK_GEN_CTRL___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_CLK_GEN_CTRL__CLK_GEN_CONTROL___POR 0x0000 +#define TOP_CMN_WCSS_WCMN_R0_CLK_GEN_CTRL__CLK_GEN_CONTROL___M 0x0000FFFF +#define TOP_CMN_WCSS_WCMN_R0_CLK_GEN_CTRL__CLK_GEN_CONTROL___S 0 +#define TOP_CMN_WCSS_WCMN_R0_CLK_GEN_CTRL___M 0x0000FFFF +#define TOP_CMN_WCSS_WCMN_R0_CLK_GEN_CTRL___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_TRC_VID (0x00B50010) +#define TOP_CMN_WCSS_WCMN_R0_TRC_VID___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_TRC_VID___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_TRC_VID__PMM_TOP___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_TRC_VID__WCMN___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_TRC_VID__TRCM___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_TRC_VID__WFSS_PMM___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_TRC_VID__MODULE_EN___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_TRC_VID__PMM_TOP___M 0x0001E000 +#define TOP_CMN_WCSS_WCMN_R0_TRC_VID__PMM_TOP___S 13 +#define TOP_CMN_WCSS_WCMN_R0_TRC_VID__WCMN___M 0x00001E00 +#define TOP_CMN_WCSS_WCMN_R0_TRC_VID__WCMN___S 9 +#define TOP_CMN_WCSS_WCMN_R0_TRC_VID__TRCM___M 0x000001E0 +#define TOP_CMN_WCSS_WCMN_R0_TRC_VID__TRCM___S 5 +#define TOP_CMN_WCSS_WCMN_R0_TRC_VID__WFSS_PMM___M 0x0000001E +#define TOP_CMN_WCSS_WCMN_R0_TRC_VID__WFSS_PMM___S 1 +#define TOP_CMN_WCSS_WCMN_R0_TRC_VID__MODULE_EN___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_TRC_VID__MODULE_EN___S 0 +#define TOP_CMN_WCSS_WCMN_R0_TRC_VID___M 0x0001FFFF +#define TOP_CMN_WCSS_WCMN_R0_TRC_VID___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_WCMN_SPARE_REG (0x00B50014) +#define TOP_CMN_WCSS_WCMN_R0_WCMN_SPARE_REG___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_WCMN_SPARE_REG___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_WCMN_SPARE_REG__SPARE_REG___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_WCMN_SPARE_REG__SPARE_REG___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_WCMN_SPARE_REG__SPARE_REG___S 0 +#define TOP_CMN_WCSS_WCMN_R0_WCMN_SPARE_REG___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_WCMN_SPARE_REG___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL (0x00B50018) +#define TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__WCMN_AXIM2_AXIBS_TESTBUS_SEL___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__TOP_MISC_DEBUGBUS_MUX_SEL___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__WCMN_CXC_TESTBUS_MUX_SEL___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__TOP_MISC_EVENTBUS_SEL___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__TOP_MISC_EVENTBUS_BLOCK_MASK___POR 0x00 +#define TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__TOP_MISC_TESTBUS_SEL___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__TESTBUS_SEL___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__WCMN_AXIM2_AXIBS_TESTBUS_SEL___M 0x001C0000 +#define TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__WCMN_AXIM2_AXIBS_TESTBUS_SEL___S 18 +#define TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__TOP_MISC_DEBUGBUS_MUX_SEL___M 0x00030000 +#define TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__TOP_MISC_DEBUGBUS_MUX_SEL___S 16 +#define TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__WCMN_CXC_TESTBUS_MUX_SEL___M 0x00008000 +#define TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__WCMN_CXC_TESTBUS_MUX_SEL___S 15 +#define TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__TOP_MISC_EVENTBUS_SEL___M 0x00007000 +#define TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__TOP_MISC_EVENTBUS_SEL___S 12 +#define TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__TOP_MISC_EVENTBUS_BLOCK_MASK___M 0x00000F80 +#define TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__TOP_MISC_EVENTBUS_BLOCK_MASK___S 7 +#define TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__TOP_MISC_TESTBUS_SEL___M 0x00000070 +#define TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__TOP_MISC_TESTBUS_SEL___S 4 +#define TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__TESTBUS_SEL___M 0x0000000F +#define TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL__TESTBUS_SEL___S 0 +#define TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL___M 0x001FFFFF +#define TOP_CMN_WCSS_WCMN_R0_WCMN_TESTBUS_SEL___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_WCMN_INVALID_APB_ACC_ADR (0x00B5001C) +#define TOP_CMN_WCSS_WCMN_R0_WCMN_INVALID_APB_ACC_ADR___RWC QCSR_REG_RO +#define TOP_CMN_WCSS_WCMN_R0_WCMN_INVALID_APB_ACC_ADR___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_WCMN_INVALID_APB_ACC_ADR__VALUE___POR 0x00000 +#define TOP_CMN_WCSS_WCMN_R0_WCMN_INVALID_APB_ACC_ADR__VALUE___M 0x0001FFFF +#define TOP_CMN_WCSS_WCMN_R0_WCMN_INVALID_APB_ACC_ADR__VALUE___S 0 +#define TOP_CMN_WCSS_WCMN_R0_WCMN_INVALID_APB_ACC_ADR___M 0x0001FFFF +#define TOP_CMN_WCSS_WCMN_R0_WCMN_INVALID_APB_ACC_ADR___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_AHBSS_SPARE (0x00B50030) +#define TOP_CMN_WCSS_WCMN_R0_AHBSS_SPARE___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_AHBSS_SPARE___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_AHBSS_SPARE__SPARE___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_AHBSS_SPARE__SPARE___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_AHBSS_SPARE__SPARE___S 0 +#define TOP_CMN_WCSS_WCMN_R0_AHBSS_SPARE___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_AHBSS_SPARE___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_ON (0x00B50038) +#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_ON___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_ON___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_ON__WMAC1_SFM_FORCE_ON_SLP_RET_N___POR 0x00 +#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_ON__WMAC1_SFM_FORCE_ON_SLP_NRET_N___POR 0x00 +#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_ON__WMAC0_SFM_FORCE_ON_SLP_RET_N___POR 0x00 +#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_ON__WMAC0_SFM_FORCE_ON_SLP_NRET_N___POR 0x00 +#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_ON__WMAC1_SFM_FORCE_ON_SLP_RET_N___M 0xFF000000 +#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_ON__WMAC1_SFM_FORCE_ON_SLP_RET_N___S 24 +#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_ON__WMAC1_SFM_FORCE_ON_SLP_NRET_N___M 0x00FF0000 +#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_ON__WMAC1_SFM_FORCE_ON_SLP_NRET_N___S 16 +#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_ON__WMAC0_SFM_FORCE_ON_SLP_RET_N___M 0x0000FF00 +#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_ON__WMAC0_SFM_FORCE_ON_SLP_RET_N___S 8 +#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_ON__WMAC0_SFM_FORCE_ON_SLP_NRET_N___M 0x000000FF +#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_ON__WMAC0_SFM_FORCE_ON_SLP_NRET_N___S 0 +#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_ON___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_ON___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_OFF (0x00B5003C) +#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_OFF___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_OFF___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_OFF__WMAC1_SFM_FORCE_OFF_SLP_RET_N___POR 0x00 +#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_OFF__WMAC1_SFM_FORCE_OFF_SLP_NRET_N___POR 0x00 +#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_OFF__WMAC0_SFM_FORCE_OFF_SLP_RET_N___POR 0x00 +#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_OFF__WMAC0_SFM_FORCE_OFF_SLP_NRET_N___POR 0x00 +#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_OFF__WMAC1_SFM_FORCE_OFF_SLP_RET_N___M 0xFF000000 +#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_OFF__WMAC1_SFM_FORCE_OFF_SLP_RET_N___S 24 +#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_OFF__WMAC1_SFM_FORCE_OFF_SLP_NRET_N___M 0x00FF0000 +#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_OFF__WMAC1_SFM_FORCE_OFF_SLP_NRET_N___S 16 +#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_OFF__WMAC0_SFM_FORCE_OFF_SLP_RET_N___M 0x0000FF00 +#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_OFF__WMAC0_SFM_FORCE_OFF_SLP_RET_N___S 8 +#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_OFF__WMAC0_SFM_FORCE_OFF_SLP_NRET_N___M 0x000000FF +#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_OFF__WMAC0_SFM_FORCE_OFF_SLP_NRET_N___S 0 +#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_OFF___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_WMAC_SFM_OFF___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_CMEM_SRAM_SLP_ON (0x00B50040) +#define TOP_CMN_WCSS_WCMN_R0_CMEM_SRAM_SLP_ON___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_CMEM_SRAM_SLP_ON___POR 0x0000FFFF +#define TOP_CMN_WCSS_WCMN_R0_CMEM_SRAM_SLP_ON__CPU_MISC_CMEM_SRAM_SLP_RET_N___POR 0x0000 +#define TOP_CMN_WCSS_WCMN_R0_CMEM_SRAM_SLP_ON__CPU_MISC_CMEM_SRAM_SLP_NRET_N___POR 0xFFFF +#define TOP_CMN_WCSS_WCMN_R0_CMEM_SRAM_SLP_ON__CPU_MISC_CMEM_SRAM_SLP_RET_N___M 0xFFFF0000 +#define TOP_CMN_WCSS_WCMN_R0_CMEM_SRAM_SLP_ON__CPU_MISC_CMEM_SRAM_SLP_RET_N___S 16 +#define TOP_CMN_WCSS_WCMN_R0_CMEM_SRAM_SLP_ON__CPU_MISC_CMEM_SRAM_SLP_NRET_N___M 0x0000FFFF +#define TOP_CMN_WCSS_WCMN_R0_CMEM_SRAM_SLP_ON__CPU_MISC_CMEM_SRAM_SLP_NRET_N___S 0 +#define TOP_CMN_WCSS_WCMN_R0_CMEM_SRAM_SLP_ON___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_CMEM_SRAM_SLP_ON___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP (0x00B50044) +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP___POR 0x00002A80 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_PRELOADED_SLP_NRET_N___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_PRELOADED_SLP_RET_N___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PRELOADED_SLP_NRET_N___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PRELOADED_SLP_RET_N___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM3_SLP_NRET_N___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM3_SLP_RET_N___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM2_SLP_NRET_N___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM2_SLP_RET_N___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM1_SLP_NRET_N___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM1_SLP_RET_N___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM0_SLP_NRET_N___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM0_SLP_RET_N___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_RX_SLP_NRET_N___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_RX_SLP_RET_N___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_SLP_NRET_N___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_SLP_RET_N___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_SLP_NRET_N___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_SLP_RET_N___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_PRELOADED_SLP_NRET_N___M 0x00020000 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_PRELOADED_SLP_NRET_N___S 17 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_PRELOADED_SLP_RET_N___M 0x00010000 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_PRELOADED_SLP_RET_N___S 16 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PRELOADED_SLP_NRET_N___M 0x00008000 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PRELOADED_SLP_NRET_N___S 15 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PRELOADED_SLP_RET_N___M 0x00004000 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PRELOADED_SLP_RET_N___S 14 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM3_SLP_NRET_N___M 0x00002000 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM3_SLP_NRET_N___S 13 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM3_SLP_RET_N___M 0x00001000 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM3_SLP_RET_N___S 12 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM2_SLP_NRET_N___M 0x00000800 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM2_SLP_NRET_N___S 11 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM2_SLP_RET_N___M 0x00000400 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM2_SLP_RET_N___S 10 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM1_SLP_NRET_N___M 0x00000200 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM1_SLP_NRET_N___S 9 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM1_SLP_RET_N___M 0x00000100 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM1_SLP_RET_N___S 8 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM0_SLP_NRET_N___M 0x00000080 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM0_SLP_NRET_N___S 7 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM0_SLP_RET_N___M 0x00000040 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_PMEM0_SLP_RET_N___S 6 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_RX_SLP_NRET_N___M 0x00000020 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_RX_SLP_NRET_N___S 5 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_RX_SLP_RET_N___M 0x00000010 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_RX_SLP_RET_N___S 4 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_SLP_NRET_N___M 0x00000008 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_SLP_NRET_N___S 3 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_SLP_RET_N___M 0x00000004 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK320_SLP_RET_N___S 2 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_SLP_NRET_N___M 0x00000002 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_SLP_NRET_N___S 1 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_SLP_RET_N___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP__WFAX_CLK480_SLP_RET_N___S 0 +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP___M 0x0003FFFF +#define TOP_CMN_WCSS_WCMN_R0_PHY_A0_GTAB_SLP___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP (0x00B5004C) +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP___POR 0x00002A80 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_PRELOADED_SLP_NRET_N___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_PRELOADED_SLP_RET_N___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PRELOADED_SLP_NRET_N___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PRELOADED_SLP_RET_N___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM3_SLP_NRET_N___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM3_SLP_RET_N___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM2_SLP_NRET_N___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM2_SLP_RET_N___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM1_SLP_NRET_N___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM1_SLP_RET_N___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM0_SLP_NRET_N___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM0_SLP_RET_N___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_RX_SLP_NRET_N___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_RX_SLP_RET_N___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_SLP_NRET_N___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_SLP_RET_N___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_SLP_NRET_N___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_SLP_RET_N___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_PRELOADED_SLP_NRET_N___M 0x00020000 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_PRELOADED_SLP_NRET_N___S 17 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_PRELOADED_SLP_RET_N___M 0x00010000 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_PRELOADED_SLP_RET_N___S 16 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PRELOADED_SLP_NRET_N___M 0x00008000 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PRELOADED_SLP_NRET_N___S 15 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PRELOADED_SLP_RET_N___M 0x00004000 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PRELOADED_SLP_RET_N___S 14 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM3_SLP_NRET_N___M 0x00002000 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM3_SLP_NRET_N___S 13 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM3_SLP_RET_N___M 0x00001000 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM3_SLP_RET_N___S 12 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM2_SLP_NRET_N___M 0x00000800 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM2_SLP_NRET_N___S 11 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM2_SLP_RET_N___M 0x00000400 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM2_SLP_RET_N___S 10 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM1_SLP_NRET_N___M 0x00000200 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM1_SLP_NRET_N___S 9 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM1_SLP_RET_N___M 0x00000100 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM1_SLP_RET_N___S 8 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM0_SLP_NRET_N___M 0x00000080 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM0_SLP_NRET_N___S 7 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM0_SLP_RET_N___M 0x00000040 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_PMEM0_SLP_RET_N___S 6 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_RX_SLP_NRET_N___M 0x00000020 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_RX_SLP_NRET_N___S 5 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_RX_SLP_RET_N___M 0x00000010 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_RX_SLP_RET_N___S 4 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_SLP_NRET_N___M 0x00000008 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_SLP_NRET_N___S 3 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_SLP_RET_N___M 0x00000004 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK320_SLP_RET_N___S 2 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_SLP_NRET_N___M 0x00000002 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_SLP_NRET_N___S 1 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_SLP_RET_N___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP__WFAX_CLK480_SLP_RET_N___S 0 +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP___M 0x0003FFFF +#define TOP_CMN_WCSS_WCMN_R0_PHY_B_GTAB_SLP___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_WCSS_RTL_VERSION (0x00B50054) +#define TOP_CMN_WCSS_WCMN_R0_WCSS_RTL_VERSION___RWC QCSR_REG_RO +#define TOP_CMN_WCSS_WCMN_R0_WCSS_RTL_VERSION___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_WCSS_RTL_VERSION__WCSS_CORE_RTL_VERSION___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_WCSS_RTL_VERSION__WCSS_CORE_RTL_VERSION___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_WCSS_RTL_VERSION__WCSS_CORE_RTL_VERSION___S 0 +#define TOP_CMN_WCSS_WCMN_R0_WCSS_RTL_VERSION___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_WCSS_RTL_VERSION___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_WCSS_FPGA_VERSION (0x00B50058) +#define TOP_CMN_WCSS_WCMN_R0_WCSS_FPGA_VERSION___RWC QCSR_REG_RO +#define TOP_CMN_WCSS_WCMN_R0_WCSS_FPGA_VERSION___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_WCSS_FPGA_VERSION__WCSS_CORE_FPGA_VERSION___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_WCSS_FPGA_VERSION__WCSS_CORE_FPGA_VERSION___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_WCSS_FPGA_VERSION__WCSS_CORE_FPGA_VERSION___S 0 +#define TOP_CMN_WCSS_WCMN_R0_WCSS_FPGA_VERSION___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_WCSS_FPGA_VERSION___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_PMM_CONFIG (0x00B5005C) +#define TOP_CMN_WCSS_WCMN_R0_PMM_CONFIG___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_PMM_CONFIG___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_PMM_CONFIG__PMM_SOFT_RESET___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_PMM_CONFIG__PMM_DISABLE_CLK_GATING___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_PMM_CONFIG__PMM_SOFT_RESET___M 0x00000002 +#define TOP_CMN_WCSS_WCMN_R0_PMM_CONFIG__PMM_SOFT_RESET___S 1 +#define TOP_CMN_WCSS_WCMN_R0_PMM_CONFIG__PMM_DISABLE_CLK_GATING___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_PMM_CONFIG__PMM_DISABLE_CLK_GATING___S 0 +#define TOP_CMN_WCSS_WCMN_R0_PMM_CONFIG___M 0x00000003 +#define TOP_CMN_WCSS_WCMN_R0_PMM_CONFIG___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_PHY_WARM_RST (0x00B50060) +#define TOP_CMN_WCSS_WCMN_R0_PHY_WARM_RST___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_PHY_WARM_RST___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_PHY_WARM_RST__PHY2_11AC_WARM_RST___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_PHY_WARM_RST__PHY1_11AC_WARM_RST___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_PHY_WARM_RST__PHY2_11AC_WARM_RST___M 0x00000002 +#define TOP_CMN_WCSS_WCMN_R0_PHY_WARM_RST__PHY2_11AC_WARM_RST___S 1 +#define TOP_CMN_WCSS_WCMN_R0_PHY_WARM_RST__PHY1_11AC_WARM_RST___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_PHY_WARM_RST__PHY1_11AC_WARM_RST___S 0 +#define TOP_CMN_WCSS_WCMN_R0_PHY_WARM_RST___M 0x00000003 +#define TOP_CMN_WCSS_WCMN_R0_PHY_WARM_RST___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_WMAC1_CCE_SLP (0x00B5006C) +#define TOP_CMN_WCSS_WCMN_R0_WMAC1_CCE_SLP___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_WMAC1_CCE_SLP___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_WMAC1_CCE_SLP__WMAC1_CCE_SLP_RET_N___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_WMAC1_CCE_SLP__WMAC1_CCE_SLP_NRET_N___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_WMAC1_CCE_SLP__WMAC1_CCE_SLP_RET_N___M 0x00000002 +#define TOP_CMN_WCSS_WCMN_R0_WMAC1_CCE_SLP__WMAC1_CCE_SLP_RET_N___S 1 +#define TOP_CMN_WCSS_WCMN_R0_WMAC1_CCE_SLP__WMAC1_CCE_SLP_NRET_N___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_WMAC1_CCE_SLP__WMAC1_CCE_SLP_NRET_N___S 0 +#define TOP_CMN_WCSS_WCMN_R0_WMAC1_CCE_SLP___M 0x00000003 +#define TOP_CMN_WCSS_WCMN_R0_WMAC1_CCE_SLP___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_WMAC2_CCE_SLP (0x00B50070) +#define TOP_CMN_WCSS_WCMN_R0_WMAC2_CCE_SLP___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_WMAC2_CCE_SLP___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_WMAC2_CCE_SLP__WMAC2_CCE_SLP_RET_N___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_WMAC2_CCE_SLP__WMAC2_CCE_SLP_NRET_N___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_WMAC2_CCE_SLP__WMAC2_CCE_SLP_RET_N___M 0x00000002 +#define TOP_CMN_WCSS_WCMN_R0_WMAC2_CCE_SLP__WMAC2_CCE_SLP_RET_N___S 1 +#define TOP_CMN_WCSS_WCMN_R0_WMAC2_CCE_SLP__WMAC2_CCE_SLP_NRET_N___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_WMAC2_CCE_SLP__WMAC2_CCE_SLP_NRET_N___S 0 +#define TOP_CMN_WCSS_WCMN_R0_WMAC2_CCE_SLP___M 0x00000003 +#define TOP_CMN_WCSS_WCMN_R0_WMAC2_CCE_SLP___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_WAHB_TESTBUS_SEL (0x00B50074) +#define TOP_CMN_WCSS_WCMN_R0_WAHB_TESTBUS_SEL___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_WAHB_TESTBUS_SEL___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_WAHB_TESTBUS_SEL__SEL___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_WAHB_TESTBUS_SEL__SEL___M 0x00000007 +#define TOP_CMN_WCSS_WCMN_R0_WAHB_TESTBUS_SEL__SEL___S 0 +#define TOP_CMN_WCSS_WCMN_R0_WAHB_TESTBUS_SEL___M 0x00000007 +#define TOP_CMN_WCSS_WCMN_R0_WAHB_TESTBUS_SEL___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_PWR_DOWN_ERR (0x00B50078) +#define TOP_CMN_WCSS_WCMN_R0_PWR_DOWN_ERR___RWC QCSR_REG_RO +#define TOP_CMN_WCSS_WCMN_R0_PWR_DOWN_ERR___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_PWR_DOWN_ERR__PADDR___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_PWR_DOWN_ERR__PADDR___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_PWR_DOWN_ERR__PADDR___S 0 +#define TOP_CMN_WCSS_WCMN_R0_PWR_DOWN_ERR___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_PWR_DOWN_ERR___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_PWR_DOWN_ERR_WRITE (0x00B5007C) +#define TOP_CMN_WCSS_WCMN_R0_PWR_DOWN_ERR_WRITE___RWC QCSR_REG_RO +#define TOP_CMN_WCSS_WCMN_R0_PWR_DOWN_ERR_WRITE___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_PWR_DOWN_ERR_WRITE__CMD___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_PWR_DOWN_ERR_WRITE__CMD___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_PWR_DOWN_ERR_WRITE__CMD___S 0 +#define TOP_CMN_WCSS_WCMN_R0_PWR_DOWN_ERR_WRITE___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_PWR_DOWN_ERR_WRITE___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0 (0x00B50080) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0___POR 0x93F33C07 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__UMAC_WCMN_MPSS_Q6_IPC_0___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PHYA0_Q6_IRQ_0___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__WMAC0_WCMN_INTR_1___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__AGGR_POWER_INT_1___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__AGGR_POWER_INT_0___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__I_GPIO_INT_1___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__I_GPIO_INT_0___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PMM_WCMN_FUNC_INT___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PMM_WCMN_WLAN1_LS_DONE_INTR___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_8___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__O_WLAN1_H2S_GRANT_INT___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_7_0___POR 0x01 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__WCSS_MSSQ6_WAKEUP_INTR___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__AGGR_FATAL_ERR___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__UMAC_WCMN_MPSS_Q6_IPC_0___M 0x80000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__UMAC_WCMN_MPSS_Q6_IPC_0___S 31 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PHYA0_Q6_IRQ_0___M 0x10000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PHYA0_Q6_IRQ_0___S 28 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__WMAC0_WCMN_INTR_1___M 0x02000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__WMAC0_WCMN_INTR_1___S 25 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__AGGR_POWER_INT_1___M 0x01000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__AGGR_POWER_INT_1___S 24 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__AGGR_POWER_INT_0___M 0x00800000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__AGGR_POWER_INT_0___S 23 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__I_GPIO_INT_1___M 0x00400000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__I_GPIO_INT_1___S 22 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__I_GPIO_INT_0___M 0x00200000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__I_GPIO_INT_0___S 21 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PMM_WCMN_FUNC_INT___M 0x00100000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PMM_WCMN_FUNC_INT___S 20 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___M 0x00020000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___S 17 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___M 0x00010000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___S 16 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PMM_WCMN_WLAN1_LS_DONE_INTR___M 0x00002000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PMM_WCMN_WLAN1_LS_DONE_INTR___S 13 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___M 0x00001000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___S 12 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_8___M 0x00000800 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_8___S 11 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__O_WLAN1_H2S_GRANT_INT___M 0x00000400 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__O_WLAN1_H2S_GRANT_INT___S 10 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_7_0___M 0x000003FC +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_7_0___S 2 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__WCSS_MSSQ6_WAKEUP_INTR___M 0x00000002 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__WCSS_MSSQ6_WAKEUP_INTR___S 1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__AGGR_FATAL_ERR___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0__AGGR_FATAL_ERR___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0___M 0x93F33FFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_0___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1 (0x00B50084) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1___POR 0x00E07249 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__UMAC_WCMN_MPSS_Q6_IPC_3___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__UMAC_WCMN_MPSS_Q6_IPC_2___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__UMAC_WCMN_MPSS_Q6_IPC_1___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__PHYA0_Q6_IRQ_3___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__PHYA0_Q6_IRQ_2___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__PHYA0_Q6_IRQ_1___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__WMAC0_WCMN_INTR_4___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__WMAC0_WCMN_INTR_0___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__WMAC0_WCMN_INTR_3___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__WMAC0_WCMN_INTR_2___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__UMAC_WCMN_MPSS_Q6_IPC_3___M 0x00800000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__UMAC_WCMN_MPSS_Q6_IPC_3___S 23 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__UMAC_WCMN_MPSS_Q6_IPC_2___M 0x00400000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__UMAC_WCMN_MPSS_Q6_IPC_2___S 22 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__UMAC_WCMN_MPSS_Q6_IPC_1___M 0x00200000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__UMAC_WCMN_MPSS_Q6_IPC_1___S 21 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__PHYA0_Q6_IRQ_3___M 0x00004000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__PHYA0_Q6_IRQ_3___S 14 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__PHYA0_Q6_IRQ_2___M 0x00002000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__PHYA0_Q6_IRQ_2___S 13 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__PHYA0_Q6_IRQ_1___M 0x00001000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__PHYA0_Q6_IRQ_1___S 12 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__WMAC0_WCMN_INTR_4___M 0x00000200 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__WMAC0_WCMN_INTR_4___S 9 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__WMAC0_WCMN_INTR_0___M 0x00000040 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__WMAC0_WCMN_INTR_0___S 6 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__WMAC0_WCMN_INTR_3___M 0x00000008 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__WMAC0_WCMN_INTR_3___S 3 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__WMAC0_WCMN_INTR_2___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1__WMAC0_WCMN_INTR_2___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1___M 0x00E07249 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_1___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2 (0x00B50088) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2___POR 0x0007FFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_6___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_5___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_4___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_3___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_2___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_1___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_0___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_11___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_10___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_9___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_8___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_7___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_6___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_5___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_4___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_3___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_2___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_1___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_0___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_6___M 0x00040000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_6___S 18 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_5___M 0x00020000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_5___S 17 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_4___M 0x00010000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_4___S 16 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_3___M 0x00008000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_3___S 15 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_2___M 0x00004000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_2___S 14 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_1___M 0x00002000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_1___S 13 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_0___M 0x00001000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__UMAC_AGGR_INTR_0___S 12 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_11___M 0x00000800 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_11___S 11 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_10___M 0x00000400 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_10___S 10 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_9___M 0x00000200 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_9___S 9 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_8___M 0x00000100 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_8___S 8 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_7___M 0x00000080 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_7___S 7 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_6___M 0x00000040 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_6___S 6 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_5___M 0x00000020 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_5___S 5 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_4___M 0x00000010 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_4___S 4 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_3___M 0x00000008 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_3___S 3 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_2___M 0x00000004 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_2___S 2 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_1___M 0x00000002 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_1___S 1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_0___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2__CE_INTR_TARGET_P_0___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2___M 0x0007FFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_2___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_3 (0x00B5008C) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_3___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_3___POR 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_3__UMAC_IND_INTR_31_0___POR 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_3__UMAC_IND_INTR_31_0___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_3__UMAC_IND_INTR_31_0___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_3___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_3___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_4 (0x00B50090) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_4___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_4___POR 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_4__UMAC_IND_INTR_63_32___POR 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_4__UMAC_IND_INTR_63_32___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_4__UMAC_IND_INTR_63_32___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_4___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_4___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_5 (0x00B50094) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_5___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_5___POR 0x3FFFFFC3 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_5__NEW_RESV_IN_HASTINGS___POR 0xFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_5__RXDMA_MAC0_1___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_5__RXDMA_MAC0_0___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_5__NEW_RESV_IN_HASTINGS___M 0x3FFFFFC0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_5__NEW_RESV_IN_HASTINGS___S 6 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_5__RXDMA_MAC0_1___M 0x00000002 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_5__RXDMA_MAC0_1___S 1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_5__RXDMA_MAC0_0___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_5__RXDMA_MAC0_0___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_5___M 0x3FFFFFC3 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_5___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0 (0x00B50098) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0___RWC QCSR_REG_WO +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__UMAC_WCMN_MPSS_Q6_IPC_0___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PHYA0_Q6_IRQ_0___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__WMAC0_WCMN_INTR_1___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__AGGR_POWER_INT_1___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__AGGR_POWER_INT_0___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__I_GPIO_INT_1___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__I_GPIO_INT_0___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PMM_WCMN_FUNC_INT___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PMM_WCMN_WLAN1_LS_DONE_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_8___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__O_WLAN1_H2S_GRANT_INT___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_7_0___POR 0x00 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__WCSS_MSSQ6_WAKEUP_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__AGGR_FATAL_ERR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__UMAC_WCMN_MPSS_Q6_IPC_0___M 0x80000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__UMAC_WCMN_MPSS_Q6_IPC_0___S 31 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PHYA0_Q6_IRQ_0___M 0x10000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PHYA0_Q6_IRQ_0___S 28 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__WMAC0_WCMN_INTR_1___M 0x02000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__WMAC0_WCMN_INTR_1___S 25 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__AGGR_POWER_INT_1___M 0x01000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__AGGR_POWER_INT_1___S 24 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__AGGR_POWER_INT_0___M 0x00800000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__AGGR_POWER_INT_0___S 23 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__I_GPIO_INT_1___M 0x00400000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__I_GPIO_INT_1___S 22 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__I_GPIO_INT_0___M 0x00200000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__I_GPIO_INT_0___S 21 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PMM_WCMN_FUNC_INT___M 0x00100000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PMM_WCMN_FUNC_INT___S 20 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___M 0x00020000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___S 17 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___M 0x00010000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___S 16 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PMM_WCMN_WLAN1_LS_DONE_INTR___M 0x00002000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PMM_WCMN_WLAN1_LS_DONE_INTR___S 13 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___M 0x00001000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___S 12 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_8___M 0x00000800 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_8___S 11 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__O_WLAN1_H2S_GRANT_INT___M 0x00000400 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__O_WLAN1_H2S_GRANT_INT___S 10 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_7_0___M 0x000003FC +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_7_0___S 2 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__WCSS_MSSQ6_WAKEUP_INTR___M 0x00000002 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__WCSS_MSSQ6_WAKEUP_INTR___S 1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__AGGR_FATAL_ERR___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0__AGGR_FATAL_ERR___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0___M 0x93F33FFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_0___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1 (0x00B5009C) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1___RWC QCSR_REG_WO +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__UMAC_WCMN_MPSS_Q6_IPC_3___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__UMAC_WCMN_MPSS_Q6_IPC_2___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__UMAC_WCMN_MPSS_Q6_IPC_1___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__PHYA0_Q6_IRQ_3___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__PHYA0_Q6_IRQ_2___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__PHYA0_Q6_IRQ_1___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__WMAC0_WCMN_INTR_4___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__WMAC0_WCMN_INTR_0___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__WMAC0_WCMN_INTR_3___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__WMAC0_WCMN_INTR_2___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__UMAC_WCMN_MPSS_Q6_IPC_3___M 0x00800000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__UMAC_WCMN_MPSS_Q6_IPC_3___S 23 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__UMAC_WCMN_MPSS_Q6_IPC_2___M 0x00400000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__UMAC_WCMN_MPSS_Q6_IPC_2___S 22 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__UMAC_WCMN_MPSS_Q6_IPC_1___M 0x00200000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__UMAC_WCMN_MPSS_Q6_IPC_1___S 21 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__PHYA0_Q6_IRQ_3___M 0x00004000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__PHYA0_Q6_IRQ_3___S 14 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__PHYA0_Q6_IRQ_2___M 0x00002000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__PHYA0_Q6_IRQ_2___S 13 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__PHYA0_Q6_IRQ_1___M 0x00001000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__PHYA0_Q6_IRQ_1___S 12 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__WMAC0_WCMN_INTR_4___M 0x00000200 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__WMAC0_WCMN_INTR_4___S 9 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__WMAC0_WCMN_INTR_0___M 0x00000040 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__WMAC0_WCMN_INTR_0___S 6 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__WMAC0_WCMN_INTR_3___M 0x00000008 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__WMAC0_WCMN_INTR_3___S 3 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__WMAC0_WCMN_INTR_2___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1__WMAC0_WCMN_INTR_2___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1___M 0x00E07249 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_1___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2 (0x00B500A0) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2___RWC QCSR_REG_WO +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_6___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_5___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_4___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_3___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_2___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_1___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_0___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_11___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_10___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_9___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_8___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_7___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_6___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_5___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_4___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_3___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_2___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_1___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_0___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_6___M 0x00040000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_6___S 18 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_5___M 0x00020000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_5___S 17 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_4___M 0x00010000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_4___S 16 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_3___M 0x00008000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_3___S 15 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_2___M 0x00004000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_2___S 14 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_1___M 0x00002000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_1___S 13 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_0___M 0x00001000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__UMAC_AGGR_INTR_0___S 12 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_11___M 0x00000800 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_11___S 11 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_10___M 0x00000400 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_10___S 10 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_9___M 0x00000200 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_9___S 9 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_8___M 0x00000100 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_8___S 8 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_7___M 0x00000080 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_7___S 7 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_6___M 0x00000040 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_6___S 6 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_5___M 0x00000020 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_5___S 5 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_4___M 0x00000010 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_4___S 4 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_3___M 0x00000008 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_3___S 3 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_2___M 0x00000004 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_2___S 2 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_1___M 0x00000002 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_1___S 1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_0___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2__CE_INTR_TARGET_P_0___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2___M 0x0007FFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_2___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_3 (0x00B500A4) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_3___RWC QCSR_REG_WO +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_3___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_3__UMAC_IND_INTR_31_0___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_3__UMAC_IND_INTR_31_0___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_3__UMAC_IND_INTR_31_0___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_3___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_3___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_4 (0x00B500A8) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_4___RWC QCSR_REG_WO +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_4___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_4__UMAC_IND_INTR_63_32___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_4__UMAC_IND_INTR_63_32___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_4__UMAC_IND_INTR_63_32___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_4___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_4___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5 (0x00B500AC) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5___RWC QCSR_REG_WO +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__NEW_RESV_IN_HASTINGS___POR 0x000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC2_1___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC2_0___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC1_1___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC1_0___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC0_1___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC0_0___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__NEW_RESV_IN_HASTINGS___M 0x3FFFFFC0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__NEW_RESV_IN_HASTINGS___S 6 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC2_1___M 0x00000020 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC2_1___S 5 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC2_0___M 0x00000010 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC2_0___S 4 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC1_1___M 0x00000008 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC1_1___S 3 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC1_0___M 0x00000004 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC1_0___S 2 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC0_1___M 0x00000002 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC0_1___S 1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC0_0___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5__RXDMA_MAC0_0___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5___M 0x3FFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_SET_5___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0 (0x00B500B0) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0___RWC QCSR_REG_WO +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PHYA0_Q6_IRQ_0___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__WMAC0_WCMN_INTR_1___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__AGGR_POWER_INT_1___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__AGGR_POWER_INT_0___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__I_GPIO_INT_1___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__I_GPIO_INT_0___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PMM_WCMN_FUNC_INT___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PMM_WCMN_WLAN1_LS_DONE_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_8___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__O_WLAN1_H2S_GRANT_INT___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_7_0___POR 0x00 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__WCSS_MSSQ6_WAKEUP_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__AGGR_FATAL_ERR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PHYA0_Q6_IRQ_0___M 0x10000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PHYA0_Q6_IRQ_0___S 28 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__WMAC0_WCMN_INTR_1___M 0x02000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__WMAC0_WCMN_INTR_1___S 25 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__AGGR_POWER_INT_1___M 0x01000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__AGGR_POWER_INT_1___S 24 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__AGGR_POWER_INT_0___M 0x00800000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__AGGR_POWER_INT_0___S 23 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__I_GPIO_INT_1___M 0x00400000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__I_GPIO_INT_1___S 22 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__I_GPIO_INT_0___M 0x00200000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__I_GPIO_INT_0___S 21 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PMM_WCMN_FUNC_INT___M 0x00100000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PMM_WCMN_FUNC_INT___S 20 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___M 0x00020000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___S 17 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___M 0x00010000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___S 16 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PMM_WCMN_WLAN1_LS_DONE_INTR___M 0x00002000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PMM_WCMN_WLAN1_LS_DONE_INTR___S 13 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___M 0x00001000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___S 12 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_8___M 0x00000800 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_8___S 11 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__O_WLAN1_H2S_GRANT_INT___M 0x00000400 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__O_WLAN1_H2S_GRANT_INT___S 10 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_7_0___M 0x000003FC +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ_7_0___S 2 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__WCSS_MSSQ6_WAKEUP_INTR___M 0x00000002 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__WCSS_MSSQ6_WAKEUP_INTR___S 1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__AGGR_FATAL_ERR___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0__AGGR_FATAL_ERR___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0___M 0x13F33FFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_0___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1 (0x00B500B4) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1___RWC QCSR_REG_WO +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__PHYA0_Q6_IRQ_3___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__PHYA0_Q6_IRQ_2___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__PHYA0_Q6_IRQ_1___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__WMAC0_WCMN_INTR_4___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__WMAC0_WCMN_INTR_0___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__WMAC0_WCMN_INTR_3___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__WMAC0_WCMN_INTR_2___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__PHYA0_Q6_IRQ_3___M 0x00004000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__PHYA0_Q6_IRQ_3___S 14 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__PHYA0_Q6_IRQ_2___M 0x00002000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__PHYA0_Q6_IRQ_2___S 13 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__PHYA0_Q6_IRQ_1___M 0x00001000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__PHYA0_Q6_IRQ_1___S 12 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__WMAC0_WCMN_INTR_4___M 0x00000200 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__WMAC0_WCMN_INTR_4___S 9 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__WMAC0_WCMN_INTR_0___M 0x00000040 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__WMAC0_WCMN_INTR_0___S 6 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__WMAC0_WCMN_INTR_3___M 0x00000008 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__WMAC0_WCMN_INTR_3___S 3 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__WMAC0_WCMN_INTR_2___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1__WMAC0_WCMN_INTR_2___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1___M 0x00007249 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_1___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2 (0x00B500B8) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2___RWC QCSR_REG_WO +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_6___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_5___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_4___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_3___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_2___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_1___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_0___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_11___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_10___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_9___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_8___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_7___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_6___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_5___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_4___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_3___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_2___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_1___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_0___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_6___M 0x00040000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_6___S 18 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_5___M 0x00020000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_5___S 17 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_4___M 0x00010000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_4___S 16 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_3___M 0x00008000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_3___S 15 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_2___M 0x00004000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_2___S 14 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_1___M 0x00002000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_1___S 13 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_0___M 0x00001000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__UMAC_AGGR_INTR_0___S 12 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_11___M 0x00000800 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_11___S 11 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_10___M 0x00000400 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_10___S 10 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_9___M 0x00000200 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_9___S 9 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_8___M 0x00000100 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_8___S 8 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_7___M 0x00000080 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_7___S 7 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_6___M 0x00000040 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_6___S 6 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_5___M 0x00000020 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_5___S 5 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_4___M 0x00000010 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_4___S 4 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_3___M 0x00000008 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_3___S 3 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_2___M 0x00000004 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_2___S 2 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_1___M 0x00000002 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_1___S 1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_0___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2__CE_INTR_TARGET_P_0___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2___M 0x0007FFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_2___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_3 (0x00B500BC) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_3___RWC QCSR_REG_WO +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_3___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_3__UMAC_IND_INTR_31_0___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_3__UMAC_IND_INTR_31_0___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_3__UMAC_IND_INTR_31_0___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_3___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_3___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_4 (0x00B500C0) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_4___RWC QCSR_REG_WO +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_4___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_4__UMAC_IND_INTR_63_32___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_4__UMAC_IND_INTR_63_32___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_4__UMAC_IND_INTR_63_32___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_4___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_4___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5 (0x00B500C4) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5___RWC QCSR_REG_WO +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__NEW_RESV_IN_HASTINGS___POR 0x000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC2_1___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC2_0___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC1_1___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC1_0___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC0_1___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC0_0___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__NEW_RESV_IN_HASTINGS___M 0x3FFFFFC0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__NEW_RESV_IN_HASTINGS___S 6 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC2_1___M 0x00000020 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC2_1___S 5 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC2_0___M 0x00000010 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC2_0___S 4 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC1_1___M 0x00000008 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC1_1___S 3 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC1_0___M 0x00000004 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC1_0___S 2 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC0_1___M 0x00000002 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC0_1___S 1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC0_0___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5__RXDMA_MAC0_0___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5___M 0x3FFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_INTR_ENABLES_CLEAR_5___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE (0x00B500C8) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PMM_WCMN_WLAN1_ERR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PHYB_NOC_WCMN_TIMEOUT_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PHYA_NOC_WCMN_TIMEOUT_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__DBGAPB_TSLV_IRQ___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__I_WCSS_DBG_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_WDOG_TIMEOUT_INTR_P___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_GXI_WDTIMEOUT_INT_P___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_GXI_LAST_WRITE_ERR_INT_P___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_GXI_AXI_WR_ERR_INT_P___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_GXI_AXI_RD_ERR_INT_P___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_CE_ERR_INT___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_APB_WR_TO_RD_ONLY_ADDR_P___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_APB_WR_INVALID_ADDR_P___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_APB_RD_INVALID_ADDR_P___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PMM_WCMN_APB_INVLD_APB_ACCESS_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WCSSDBG_TRIGOUT_MSS_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WCSSDBG_TRIGOUT_APPS_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WCSSDBG_TPDA_GERR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PMM_WSI_ERR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WCSS_RET_ACMT_INT___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WCSS_APB_TSLV_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PMM_WCMN_ERR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__MEM_ERR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CCMN_WCMN_TRC_INTR_P___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__UMAC_NOC_WCMN_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WAHB_APB_TSLV_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WAHB_AHB_TSLV_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PMM_WCMN_WLAN1_ERR_INTR___M 0x40000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PMM_WCMN_WLAN1_ERR_INTR___S 30 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PHYB_NOC_WCMN_TIMEOUT_INTR___M 0x20000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PHYB_NOC_WCMN_TIMEOUT_INTR___S 29 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PHYA_NOC_WCMN_TIMEOUT_INTR___M 0x10000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PHYA_NOC_WCMN_TIMEOUT_INTR___S 28 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__DBGAPB_TSLV_IRQ___M 0x08000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__DBGAPB_TSLV_IRQ___S 27 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__I_WCSS_DBG_INTR___M 0x04000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__I_WCSS_DBG_INTR___S 26 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_WDOG_TIMEOUT_INTR_P___M 0x02000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_WDOG_TIMEOUT_INTR_P___S 25 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_GXI_WDTIMEOUT_INT_P___M 0x01000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_GXI_WDTIMEOUT_INT_P___S 24 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_GXI_LAST_WRITE_ERR_INT_P___M 0x00800000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_GXI_LAST_WRITE_ERR_INT_P___S 23 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_GXI_AXI_WR_ERR_INT_P___M 0x00400000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_GXI_AXI_WR_ERR_INT_P___S 22 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_GXI_AXI_RD_ERR_INT_P___M 0x00200000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_GXI_AXI_RD_ERR_INT_P___S 21 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_CE_ERR_INT___M 0x00100000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_CE_ERR_INT___S 20 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_APB_WR_TO_RD_ONLY_ADDR_P___M 0x00080000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_APB_WR_TO_RD_ONLY_ADDR_P___S 19 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_APB_WR_INVALID_ADDR_P___M 0x00040000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_APB_WR_INVALID_ADDR_P___S 18 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_APB_RD_INVALID_ADDR_P___M 0x00020000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CE_INTR_MISC_HOST_APB_RD_INVALID_ADDR_P___S 17 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PMM_WCMN_APB_INVLD_APB_ACCESS_INTR___M 0x00010000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PMM_WCMN_APB_INVLD_APB_ACCESS_INTR___S 16 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WCSSDBG_TRIGOUT_MSS_INTR___M 0x00008000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WCSSDBG_TRIGOUT_MSS_INTR___S 15 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WCSSDBG_TRIGOUT_APPS_INTR___M 0x00004000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WCSSDBG_TRIGOUT_APPS_INTR___S 14 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WCSSDBG_TPDA_GERR_INTR___M 0x00002000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WCSSDBG_TPDA_GERR_INTR___S 13 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PMM_WSI_ERR_INTR___M 0x00001000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PMM_WSI_ERR_INTR___S 12 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WCSS_RET_ACMT_INT___M 0x00000800 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WCSS_RET_ACMT_INT___S 11 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WCSS_APB_TSLV_INTR___M 0x00000400 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WCSS_APB_TSLV_INTR___S 10 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PMM_WCMN_ERR_INTR___M 0x00000200 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__PMM_WCMN_ERR_INTR___S 9 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__MEM_ERR_INTR___M 0x00000020 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__MEM_ERR_INTR___S 5 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CCMN_WCMN_TRC_INTR_P___M 0x00000010 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__CCMN_WCMN_TRC_INTR_P___S 4 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__UMAC_NOC_WCMN_INTR___M 0x00000008 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__UMAC_NOC_WCMN_INTR___S 3 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WAHB_APB_TSLV_INTR___M 0x00000002 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WAHB_APB_TSLV_INTR___S 1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WAHB_AHB_TSLV_INTR___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE__WAHB_AHB_TSLV_INTR___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE___M 0x7FFFFE3B +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_ENABLE___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS (0x00B500CC) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS___RWC QCSR_REG_RO +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PMM_WCMN_WLAN1_ERR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PHYB_NOC_WCMN_TIMEOUT_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PHYA_NOC_WCMN_TIMEOUT_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__DBGAPB_TSLV_IRQ___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__I_WCSS_DBG_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_WDOG_TIMEOUT_INTR_P___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_GXI_WDTIMEOUT_INT_P___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_GXI_LAST_WRITE_ERR_INT_P___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_GXI_AXI_WR_ERR_INT_P___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_GXI_AXI_RD_ERR_INT_P___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_CE_ERR_INT___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_APB_WR_TO_RD_ONLY_ADDR_P___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_APB_WR_INVALID_ADDR_P___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_APB_RD_INVALID_ADDR_P___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PMM_WCMN_APB_INVLD_APB_ACCESS_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WCSSDBG_TRIGOUT_MSS_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WCSSDBG_TRIGOUT_APPS_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WCSSDBG_TPDA_GERR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PMM_WSI_ERR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WCSS_RET_ACMT_INT___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WCSS_APB_TSLV_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PMM_WCMN_ERR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__MEM_ERR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CCMN_WCMN_TRC_INTR_P___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__UMAC_NOC_WCMN_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WAHB_APB_TSLV_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WAHB_AHB_TSLV_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PMM_WCMN_WLAN1_ERR_INTR___M 0x40000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PMM_WCMN_WLAN1_ERR_INTR___S 30 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PHYB_NOC_WCMN_TIMEOUT_INTR___M 0x20000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PHYB_NOC_WCMN_TIMEOUT_INTR___S 29 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PHYA_NOC_WCMN_TIMEOUT_INTR___M 0x10000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PHYA_NOC_WCMN_TIMEOUT_INTR___S 28 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__DBGAPB_TSLV_IRQ___M 0x08000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__DBGAPB_TSLV_IRQ___S 27 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__I_WCSS_DBG_INTR___M 0x04000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__I_WCSS_DBG_INTR___S 26 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_WDOG_TIMEOUT_INTR_P___M 0x02000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_WDOG_TIMEOUT_INTR_P___S 25 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_GXI_WDTIMEOUT_INT_P___M 0x01000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_GXI_WDTIMEOUT_INT_P___S 24 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_GXI_LAST_WRITE_ERR_INT_P___M 0x00800000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_GXI_LAST_WRITE_ERR_INT_P___S 23 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_GXI_AXI_WR_ERR_INT_P___M 0x00400000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_GXI_AXI_WR_ERR_INT_P___S 22 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_GXI_AXI_RD_ERR_INT_P___M 0x00200000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_GXI_AXI_RD_ERR_INT_P___S 21 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_CE_ERR_INT___M 0x00100000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_CE_ERR_INT___S 20 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_APB_WR_TO_RD_ONLY_ADDR_P___M 0x00080000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_APB_WR_TO_RD_ONLY_ADDR_P___S 19 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_APB_WR_INVALID_ADDR_P___M 0x00040000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_APB_WR_INVALID_ADDR_P___S 18 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_APB_RD_INVALID_ADDR_P___M 0x00020000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CE_INTR_MISC_HOST_APB_RD_INVALID_ADDR_P___S 17 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PMM_WCMN_APB_INVLD_APB_ACCESS_INTR___M 0x00010000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PMM_WCMN_APB_INVLD_APB_ACCESS_INTR___S 16 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WCSSDBG_TRIGOUT_MSS_INTR___M 0x00008000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WCSSDBG_TRIGOUT_MSS_INTR___S 15 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WCSSDBG_TRIGOUT_APPS_INTR___M 0x00004000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WCSSDBG_TRIGOUT_APPS_INTR___S 14 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WCSSDBG_TPDA_GERR_INTR___M 0x00002000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WCSSDBG_TPDA_GERR_INTR___S 13 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PMM_WSI_ERR_INTR___M 0x00001000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PMM_WSI_ERR_INTR___S 12 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WCSS_RET_ACMT_INT___M 0x00000800 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WCSS_RET_ACMT_INT___S 11 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WCSS_APB_TSLV_INTR___M 0x00000400 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WCSS_APB_TSLV_INTR___S 10 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PMM_WCMN_ERR_INTR___M 0x00000200 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__PMM_WCMN_ERR_INTR___S 9 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__MEM_ERR_INTR___M 0x00000020 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__MEM_ERR_INTR___S 5 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CCMN_WCMN_TRC_INTR_P___M 0x00000010 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__CCMN_WCMN_TRC_INTR_P___S 4 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__UMAC_NOC_WCMN_INTR___M 0x00000008 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__UMAC_NOC_WCMN_INTR___S 3 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WAHB_APB_TSLV_INTR___M 0x00000002 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WAHB_APB_TSLV_INTR___S 1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WAHB_AHB_TSLV_INTR___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS__WAHB_AHB_TSLV_INTR___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS___M 0x7FFFFE3B +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_STATUS___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR (0x00B500D0) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR___RWC QCSR_REG_WO +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__PMM_WCMN_WLAN1_ERR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__PHYA_NOC_WCMN_TIMEOUT_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__DBGAPB_TSLV_IRQ___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__I_WCSS_DBG_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_WDOG_TIMEOUT_INTR_P___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_GXI_WDTIMEOUT_INT_P___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_GXI_LAST_WRITE_ERR_INT_P___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_GXI_AXI_WR_ERR_INT_P___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_GXI_AXI_RD_ERR_INT_P___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_CE_ERR_INT___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_APB_WR_TO_RD_ONLY_ADDR_P___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_APB_WR_INVALID_ADDR_P___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_APB_RD_INVALID_ADDR_P___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__PMM_WCMN_APB_INVLD_APB_ACCESS_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSSDBG_TRIGOUT_MSS_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSSDBG_TRIGOUT_APPS_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSSDBG_TPDA_GERR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__PMM_WSI_ERR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSS_RET_ACMT_INT___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSS_APB_TSLV_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__PMM_WCMN_ERR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__MEM_ERR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CCMN_WCMN_TRC_INTR_P___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__UMAC_NOC_WCMN_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSS_ECAHB_TSLV_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WAHB_APB_TSLV_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WAHB_AHB_TSLV_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__PMM_WCMN_WLAN1_ERR_INTR___M 0x40000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__PMM_WCMN_WLAN1_ERR_INTR___S 30 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__PHYA_NOC_WCMN_TIMEOUT_INTR___M 0x10000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__PHYA_NOC_WCMN_TIMEOUT_INTR___S 28 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__DBGAPB_TSLV_IRQ___M 0x08000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__DBGAPB_TSLV_IRQ___S 27 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__I_WCSS_DBG_INTR___M 0x04000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__I_WCSS_DBG_INTR___S 26 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_WDOG_TIMEOUT_INTR_P___M 0x02000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_WDOG_TIMEOUT_INTR_P___S 25 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_GXI_WDTIMEOUT_INT_P___M 0x01000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_GXI_WDTIMEOUT_INT_P___S 24 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_GXI_LAST_WRITE_ERR_INT_P___M 0x00800000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_GXI_LAST_WRITE_ERR_INT_P___S 23 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_GXI_AXI_WR_ERR_INT_P___M 0x00400000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_GXI_AXI_WR_ERR_INT_P___S 22 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_GXI_AXI_RD_ERR_INT_P___M 0x00200000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_GXI_AXI_RD_ERR_INT_P___S 21 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_CE_ERR_INT___M 0x00100000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_CE_ERR_INT___S 20 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_APB_WR_TO_RD_ONLY_ADDR_P___M 0x00080000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_APB_WR_TO_RD_ONLY_ADDR_P___S 19 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_APB_WR_INVALID_ADDR_P___M 0x00040000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_APB_WR_INVALID_ADDR_P___S 18 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_APB_RD_INVALID_ADDR_P___M 0x00020000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CE_INTR_MISC_HOST_APB_RD_INVALID_ADDR_P___S 17 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__PMM_WCMN_APB_INVLD_APB_ACCESS_INTR___M 0x00010000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__PMM_WCMN_APB_INVLD_APB_ACCESS_INTR___S 16 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSSDBG_TRIGOUT_MSS_INTR___M 0x00008000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSSDBG_TRIGOUT_MSS_INTR___S 15 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSSDBG_TRIGOUT_APPS_INTR___M 0x00004000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSSDBG_TRIGOUT_APPS_INTR___S 14 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSSDBG_TPDA_GERR_INTR___M 0x00002000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSSDBG_TPDA_GERR_INTR___S 13 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__PMM_WSI_ERR_INTR___M 0x00001000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__PMM_WSI_ERR_INTR___S 12 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSS_RET_ACMT_INT___M 0x00000800 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSS_RET_ACMT_INT___S 11 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSS_APB_TSLV_INTR___M 0x00000400 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSS_APB_TSLV_INTR___S 10 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__PMM_WCMN_ERR_INTR___M 0x00000200 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__PMM_WCMN_ERR_INTR___S 9 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__MEM_ERR_INTR___M 0x00000020 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__MEM_ERR_INTR___S 5 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CCMN_WCMN_TRC_INTR_P___M 0x00000010 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__CCMN_WCMN_TRC_INTR_P___S 4 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__UMAC_NOC_WCMN_INTR___M 0x00000008 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__UMAC_NOC_WCMN_INTR___S 3 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSS_ECAHB_TSLV_INTR___M 0x00000004 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WCSS_ECAHB_TSLV_INTR___S 2 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WAHB_APB_TSLV_INTR___M 0x00000002 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WAHB_APB_TSLV_INTR___S 1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WAHB_AHB_TSLV_INTR___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR__WAHB_AHB_TSLV_INTR___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR___M 0x5FFFFE3F +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_FATAL_ERR_INTR_CLEAR___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_0 (0x00B500D4) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_0___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_0___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_0__I_WCSS_SW_SLP_TMR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_0__I_WCSS_WLAN1_SLP_TMR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_0__PMH_INT___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_0__APSS_WCSS_WAKEUP_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_0__I_WCSS_SW_SLP_TMR_INTR___M 0x00000040 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_0__I_WCSS_SW_SLP_TMR_INTR___S 6 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_0__I_WCSS_WLAN1_SLP_TMR_INTR___M 0x00000010 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_0__I_WCSS_WLAN1_SLP_TMR_INTR___S 4 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_0__PMH_INT___M 0x00000004 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_0__PMH_INT___S 2 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_0__APSS_WCSS_WAKEUP_INTR___M 0x00000002 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_0__APSS_WCSS_WAKEUP_INTR___S 1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_0___M 0x00000056 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_0___S 1 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1 (0x00B500D8) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__NOC_UMACACCESS_IN_PWR_CLPS_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WLAN1_SW_PHY_OFF_CONFIRM_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__WAHB_PWR_DWN_ACC_ERR_INT___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WLAN1_APS_SW_WLAN_OFF_IS_ERR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WLAN1_APS_SW_ENTER_LS_IS_ERR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WLAN1_APS_DS_REQ_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WLAN1_APS_WLAN_IDLE_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_SR_XO_SETTLE_TIMEOUT_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WL_CMN_PWRDOWN_CHK_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_UMAC_IDLE_CHK_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_SNOC_IDLE_REQ_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WNOC_IDLE_REQ_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_RFACTRL_IDLE_REQ_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_AXIBS_IDLE_CHK_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_CE_IDLE_CHK_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_PHY1_IDLE_WAIT_TO_INT___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WMAC1_IDLE_WAIT_TO_INT___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__NOC_UMACACCESS_IN_PWR_CLPS_INTR___M 0x01000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__NOC_UMACACCESS_IN_PWR_CLPS_INTR___S 24 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WLAN1_SW_PHY_OFF_CONFIRM_TO_INTR___M 0x00400000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WLAN1_SW_PHY_OFF_CONFIRM_TO_INTR___S 22 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__WAHB_PWR_DWN_ACC_ERR_INT___M 0x00200000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__WAHB_PWR_DWN_ACC_ERR_INT___S 21 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WLAN1_APS_SW_WLAN_OFF_IS_ERR_INTR___M 0x00040000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WLAN1_APS_SW_WLAN_OFF_IS_ERR_INTR___S 18 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WLAN1_APS_SW_ENTER_LS_IS_ERR_INTR___M 0x00020000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WLAN1_APS_SW_ENTER_LS_IS_ERR_INTR___S 17 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WLAN1_APS_DS_REQ_TO_INTR___M 0x00004000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WLAN1_APS_DS_REQ_TO_INTR___S 14 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WLAN1_APS_WLAN_IDLE_TO_INTR___M 0x00002000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WLAN1_APS_WLAN_IDLE_TO_INTR___S 13 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_SR_XO_SETTLE_TIMEOUT_INTR___M 0x00001000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_SR_XO_SETTLE_TIMEOUT_INTR___S 12 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WL_CMN_PWRDOWN_CHK_TO_INTR___M 0x00000800 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WL_CMN_PWRDOWN_CHK_TO_INTR___S 11 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_UMAC_IDLE_CHK_TO_INTR___M 0x00000400 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_UMAC_IDLE_CHK_TO_INTR___S 10 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_SNOC_IDLE_REQ_TO_INTR___M 0x00000200 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_SNOC_IDLE_REQ_TO_INTR___S 9 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WNOC_IDLE_REQ_TO_INTR___M 0x00000100 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WNOC_IDLE_REQ_TO_INTR___S 8 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_RFACTRL_IDLE_REQ_TO_INTR___M 0x00000080 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_RFACTRL_IDLE_REQ_TO_INTR___S 7 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_AXIBS_IDLE_CHK_TO_INTR___M 0x00000040 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_AXIBS_IDLE_CHK_TO_INTR___S 6 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_CE_IDLE_CHK_TO_INTR___M 0x00000010 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_CE_IDLE_CHK_TO_INTR___S 4 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_PHY1_IDLE_WAIT_TO_INT___M 0x00000004 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_PHY1_IDLE_WAIT_TO_INT___S 2 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WMAC1_IDLE_WAIT_TO_INT___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1__PMM_WCMN_WMAC1_IDLE_WAIT_TO_INT___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1___M 0x01667FD5 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_ENABLE_SET_1___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_0 (0x00B500DC) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_0___RWC QCSR_REG_RO +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_0___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_0__I_WCSS_SW_SLP_TMR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_0__I_WCSS_WLAN1_SLP_TMR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_0__PMH_INT___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_0__APSS_WCSS_WAKEUP_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_0__I_WCSS_SW_SLP_TMR_INTR___M 0x00000040 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_0__I_WCSS_SW_SLP_TMR_INTR___S 6 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_0__I_WCSS_WLAN1_SLP_TMR_INTR___M 0x00000010 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_0__I_WCSS_WLAN1_SLP_TMR_INTR___S 4 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_0__PMH_INT___M 0x00000004 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_0__PMH_INT___S 2 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_0__APSS_WCSS_WAKEUP_INTR___M 0x00000002 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_0__APSS_WCSS_WAKEUP_INTR___S 1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_0___M 0x00000056 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_0___S 1 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1 (0x00B500E0) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1___RWC QCSR_REG_RO +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__NOC_UMACACCESS_IN_PWR_CLPS_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WLAN1_SW_PHY_OFF_CONFIRM_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__WAHB_PWR_DWN_ACC_ERR_INT___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WLAN1_APS_SW_WLAN_OFF_IS_ERR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WLAN1_APS_SW_ENTER_LS_IS_ERR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WLAN1_APS_DS_REQ_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WLAN1_APS_WLAN_IDLE_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_SR_XO_SETTLE_TIMEOUT_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WL_CMN_PWRDOWN_CHK_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_UMAC_IDLE_CHK_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_SNOC_IDLE_REQ_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WNOC_IDLE_REQ_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_RFACTRL_IDLE_REQ_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_AXIBS_IDLE_CHK_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_CE_IDLE_CHK_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_PHY1_IDLE_WAIT_TO_INT___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WMAC1_IDLE_WAIT_TO_INT___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__NOC_UMACACCESS_IN_PWR_CLPS_INTR___M 0x01000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__NOC_UMACACCESS_IN_PWR_CLPS_INTR___S 24 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WLAN1_SW_PHY_OFF_CONFIRM_TO_INTR___M 0x00400000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WLAN1_SW_PHY_OFF_CONFIRM_TO_INTR___S 22 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__WAHB_PWR_DWN_ACC_ERR_INT___M 0x00200000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__WAHB_PWR_DWN_ACC_ERR_INT___S 21 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WLAN1_APS_SW_WLAN_OFF_IS_ERR_INTR___M 0x00040000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WLAN1_APS_SW_WLAN_OFF_IS_ERR_INTR___S 18 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WLAN1_APS_SW_ENTER_LS_IS_ERR_INTR___M 0x00020000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WLAN1_APS_SW_ENTER_LS_IS_ERR_INTR___S 17 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WLAN1_APS_DS_REQ_TO_INTR___M 0x00004000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WLAN1_APS_DS_REQ_TO_INTR___S 14 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WLAN1_APS_WLAN_IDLE_TO_INTR___M 0x00002000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WLAN1_APS_WLAN_IDLE_TO_INTR___S 13 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_SR_XO_SETTLE_TIMEOUT_INTR___M 0x00001000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_SR_XO_SETTLE_TIMEOUT_INTR___S 12 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WL_CMN_PWRDOWN_CHK_TO_INTR___M 0x00000800 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WL_CMN_PWRDOWN_CHK_TO_INTR___S 11 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_UMAC_IDLE_CHK_TO_INTR___M 0x00000400 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_UMAC_IDLE_CHK_TO_INTR___S 10 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_SNOC_IDLE_REQ_TO_INTR___M 0x00000200 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_SNOC_IDLE_REQ_TO_INTR___S 9 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WNOC_IDLE_REQ_TO_INTR___M 0x00000100 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WNOC_IDLE_REQ_TO_INTR___S 8 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_RFACTRL_IDLE_REQ_TO_INTR___M 0x00000080 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_RFACTRL_IDLE_REQ_TO_INTR___S 7 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_AXIBS_IDLE_CHK_TO_INTR___M 0x00000040 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_AXIBS_IDLE_CHK_TO_INTR___S 6 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_CE_IDLE_CHK_TO_INTR___M 0x00000010 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_CE_IDLE_CHK_TO_INTR___S 4 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_PHY1_IDLE_WAIT_TO_INT___M 0x00000004 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_PHY1_IDLE_WAIT_TO_INT___S 2 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WMAC1_IDLE_WAIT_TO_INT___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1__PMM_WCMN_WMAC1_IDLE_WAIT_TO_INT___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1___M 0x01667FD5 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_STATUS_SET_1___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_0 (0x00B500E4) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_0___RWC QCSR_REG_WO +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_0___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_0__I_WCSS_SW_SLP_TMR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_0__I_WCSS_WLAN1_SLP_TMR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_0__PMH_INT___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_0__APSS_WCSS_WAKEUP_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_0__I_WCSS_SW_SLP_TMR_INTR___M 0x00000040 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_0__I_WCSS_SW_SLP_TMR_INTR___S 6 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_0__I_WCSS_WLAN1_SLP_TMR_INTR___M 0x00000010 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_0__I_WCSS_WLAN1_SLP_TMR_INTR___S 4 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_0__PMH_INT___M 0x00000004 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_0__PMH_INT___S 2 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_0__APSS_WCSS_WAKEUP_INTR___M 0x00000002 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_0__APSS_WCSS_WAKEUP_INTR___S 1 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_0___M 0x00000056 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_0___S 1 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1 (0x00B500E8) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__NOC_UMACACCESS_IN_PWR_CLPS_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WLAN1_SW_PHY_OFF_CONFIRM_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__WAHB_PWR_DWN_ACC_ERR_INT___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WLAN1_APS_SW_WLAN_OFF_IS_ERR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WLAN1_APS_SW_ENTER_LS_IS_ERR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WLAN1_APS_DS_REQ_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WLAN1_APS_WLAN_IDLE_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_SR_XO_SETTLE_TIMEOUT_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WL_CMN_PWRDOWN_CHK_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_UMAC_IDLE_CHK_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_SNOC_IDLE_REQ_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WNOC_IDLE_REQ_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_RFACTRL_IDLE_REQ_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_AXIBS_IDLE_CHK_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_CE_IDLE_CHK_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_PHY1_IDLE_WAIT_TO_INT___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WMAC1_IDLE_WAIT_TO_INT___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__NOC_UMACACCESS_IN_PWR_CLPS_INTR___M 0x01000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__NOC_UMACACCESS_IN_PWR_CLPS_INTR___S 24 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WLAN1_SW_PHY_OFF_CONFIRM_TO_INTR___M 0x00400000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WLAN1_SW_PHY_OFF_CONFIRM_TO_INTR___S 22 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__WAHB_PWR_DWN_ACC_ERR_INT___M 0x00200000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__WAHB_PWR_DWN_ACC_ERR_INT___S 21 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WLAN1_APS_SW_WLAN_OFF_IS_ERR_INTR___M 0x00040000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WLAN1_APS_SW_WLAN_OFF_IS_ERR_INTR___S 18 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WLAN1_APS_SW_ENTER_LS_IS_ERR_INTR___M 0x00020000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WLAN1_APS_SW_ENTER_LS_IS_ERR_INTR___S 17 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WLAN1_APS_DS_REQ_TO_INTR___M 0x00004000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WLAN1_APS_DS_REQ_TO_INTR___S 14 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WLAN1_APS_WLAN_IDLE_TO_INTR___M 0x00002000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WLAN1_APS_WLAN_IDLE_TO_INTR___S 13 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_SR_XO_SETTLE_TIMEOUT_INTR___M 0x00001000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_SR_XO_SETTLE_TIMEOUT_INTR___S 12 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WL_CMN_PWRDOWN_CHK_TO_INTR___M 0x00000800 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WL_CMN_PWRDOWN_CHK_TO_INTR___S 11 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_UMAC_IDLE_CHK_TO_INTR___M 0x00000400 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_UMAC_IDLE_CHK_TO_INTR___S 10 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_SNOC_IDLE_REQ_TO_INTR___M 0x00000200 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_SNOC_IDLE_REQ_TO_INTR___S 9 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WNOC_IDLE_REQ_TO_INTR___M 0x00000100 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WNOC_IDLE_REQ_TO_INTR___S 8 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_RFACTRL_IDLE_REQ_TO_INTR___M 0x00000080 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_RFACTRL_IDLE_REQ_TO_INTR___S 7 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_AXIBS_IDLE_CHK_TO_INTR___M 0x00000040 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_AXIBS_IDLE_CHK_TO_INTR___S 6 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_CE_IDLE_CHK_TO_INTR___M 0x00000010 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_CE_IDLE_CHK_TO_INTR___S 4 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_PHY1_IDLE_WAIT_TO_INT___M 0x00000004 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_PHY1_IDLE_WAIT_TO_INT___S 2 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WMAC1_IDLE_WAIT_TO_INT___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1__PMM_WCMN_WMAC1_IDLE_WAIT_TO_INT___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1___M 0x01667FD5 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_AGGRE_POWER_INTR_CLEAR_SET_1___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_ENABLES (0x00B500EC) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_ENABLES___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_ENABLES___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_ENABLES__SET_0___POR 0x00000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_ENABLES__SET_0___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_ENABLES__SET_0___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_ENABLES___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_ENABLES___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_ENABLES (0x00B500F0) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_ENABLES___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_ENABLES___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_ENABLES__SET_1___POR 0x00000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_ENABLES__SET_1___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_ENABLES__SET_1___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_ENABLES___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_ENABLES___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_ENABLES (0x00B500F4) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_ENABLES___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_ENABLES___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_ENABLES__SET_0___POR 0x00000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_ENABLES__SET_0___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_ENABLES__SET_0___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_ENABLES___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_ENABLES___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_ENABLES (0x00B500F8) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_ENABLES___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_ENABLES___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_ENABLES__SET_1___POR 0x00000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_ENABLES__SET_1___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_ENABLES__SET_1___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_ENABLES___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_ENABLES___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_ENABLES (0x00B500FC) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_ENABLES___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_ENABLES___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_ENABLES__SET_0___POR 0x00000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_ENABLES__SET_0___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_ENABLES__SET_0___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_ENABLES___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_ENABLES___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_ENABLES (0x00B50100) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_ENABLES___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_ENABLES___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_ENABLES__SET_1___POR 0x00000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_ENABLES__SET_1___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_ENABLES__SET_1___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_ENABLES___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_ENABLES___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_STATUS (0x00B50104) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_STATUS___RWC QCSR_REG_RO +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_STATUS___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_STATUS__SET_0___POR 0x00000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_STATUS__SET_0___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_STATUS__SET_0___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_STATUS___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_STATUS___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_STATUS (0x00B50108) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_STATUS___RWC QCSR_REG_RO +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_STATUS___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_STATUS__SET_1___POR 0x00000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_STATUS__SET_1___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_STATUS__SET_1___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_STATUS___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_STATUS___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_STATUS (0x00B5010C) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_STATUS___RWC QCSR_REG_RO +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_STATUS___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_STATUS__SET_0___POR 0x00000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_STATUS__SET_0___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_STATUS__SET_0___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_STATUS___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_STATUS___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_STATUS (0x00B50110) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_STATUS___RWC QCSR_REG_RO +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_STATUS___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_STATUS__SET_1___POR 0x00000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_STATUS__SET_1___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_STATUS__SET_1___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_STATUS___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_STATUS___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_STATUS (0x00B50114) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_STATUS___RWC QCSR_REG_RO +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_STATUS___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_STATUS__SET_0___POR 0x00000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_STATUS__SET_0___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_STATUS__SET_0___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_STATUS___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_STATUS___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_STATUS (0x00B50118) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_STATUS___RWC QCSR_REG_RO +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_STATUS___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_STATUS__SET_1___POR 0x00000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_STATUS__SET_1___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_STATUS__SET_1___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_STATUS___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_STATUS___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_CLEAR (0x00B5011C) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_CLEAR___RWC QCSR_REG_WO +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_CLEAR___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_CLEAR__SET_0___POR 0x00000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_CLEAR__SET_0___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_CLEAR__SET_0___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_CLEAR___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET0_INTR_CLEAR___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_CLEAR (0x00B50120) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_CLEAR___RWC QCSR_REG_WO +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_CLEAR___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_CLEAR__SET_1___POR 0x00000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_CLEAR__SET_1___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_CLEAR__SET_1___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_CLEAR___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC0_SET1_INTR_CLEAR___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_CLEAR (0x00B50124) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_CLEAR___RWC QCSR_REG_WO +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_CLEAR___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_CLEAR__SET_0___POR 0x00000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_CLEAR__SET_0___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_CLEAR__SET_0___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_CLEAR___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET0_INTR_CLEAR___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_CLEAR (0x00B50128) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_CLEAR___RWC QCSR_REG_WO +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_CLEAR___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_CLEAR__SET_1___POR 0x00000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_CLEAR__SET_1___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_CLEAR__SET_1___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_CLEAR___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC1_SET1_INTR_CLEAR___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_CLEAR (0x00B5012C) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_CLEAR___RWC QCSR_REG_WO +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_CLEAR___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_CLEAR__SET_0___POR 0x00000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_CLEAR__SET_0___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_CLEAR__SET_0___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_CLEAR___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET0_INTR_CLEAR___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_CLEAR (0x00B50130) +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_CLEAR___RWC QCSR_REG_WO +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_CLEAR___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_CLEAR__SET_1___POR 0x00000 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_CLEAR__SET_1___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_CLEAR__SET_1___S 0 +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_CLEAR___M 0x000FFFFF +#define TOP_CMN_WCSS_WCMN_R0_QDSP_RXDMA_MAC2_SET1_INTR_CLEAR___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE (0x00B50148) +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE__REGISTER___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE__REGISTER___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE__REGISTER___S 0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS (0x00B5014C) +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS___RWC QCSR_REG_RO +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS__REGISTER___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS__REGISTER___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS__REGISTER___S 0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR (0x00B50150) +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR__REGISTER___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR__REGISTER___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR__REGISTER___S 0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_ENABLE (0x00B50154) +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_ENABLE___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_ENABLE___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_ENABLE__WCMN_PMM_WLAN1_PHYA0_WAKEUP_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_ENABLE__WCMN_PMM_WLAN1_WMAC1_WAKEUP_INTR___POR 0x00 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_ENABLE__WCMN_PMM_WLAN1_WMAC0_WAKEUP_INTR___POR 0x00 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_ENABLE__WCMN_PMM_WLAN1_PHYA0_WAKEUP_INTR___M 0x00078000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_ENABLE__WCMN_PMM_WLAN1_PHYA0_WAKEUP_INTR___S 15 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_ENABLE__WCMN_PMM_WLAN1_WMAC1_WAKEUP_INTR___M 0x000003E0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_ENABLE__WCMN_PMM_WLAN1_WMAC1_WAKEUP_INTR___S 5 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_ENABLE__WCMN_PMM_WLAN1_WMAC0_WAKEUP_INTR___M 0x0000001F +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_ENABLE__WCMN_PMM_WLAN1_WMAC0_WAKEUP_INTR___S 0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_ENABLE___M 0x000783FF +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_ENABLE___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_CLEAR (0x00B50158) +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_CLEAR___RWC QCSR_REG_WO +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_CLEAR___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_CLEAR__WCMN_PMM_WLAN1_PHYA0_WAKEUP_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_CLEAR__WCMN_PMM_WLAN1_WMAC1_WAKEUP_INTR___POR 0x00 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_CLEAR__WCMN_PMM_WLAN1_WMAC0_WAKEUP_INTR___POR 0x00 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_CLEAR__WCMN_PMM_WLAN1_PHYA0_WAKEUP_INTR___M 0x00078000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_CLEAR__WCMN_PMM_WLAN1_PHYA0_WAKEUP_INTR___S 15 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_CLEAR__WCMN_PMM_WLAN1_WMAC1_WAKEUP_INTR___M 0x000003E0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_CLEAR__WCMN_PMM_WLAN1_WMAC1_WAKEUP_INTR___S 5 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_CLEAR__WCMN_PMM_WLAN1_WMAC0_WAKEUP_INTR___M 0x0000001F +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_CLEAR__WCMN_PMM_WLAN1_WMAC0_WAKEUP_INTR___S 0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_CLEAR___M 0x000783FF +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_CLEAR___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_STATUS (0x00B501B0) +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_STATUS___RWC QCSR_REG_RO +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_STATUS___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_STATUS__WCMN_PMM_WLAN1_PHYA0_WAKEUP_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_STATUS__WCMN_PMM_WLAN1_WMAC0_WAKEUP_INTR___POR 0x00 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_STATUS__WCMN_PMM_WLAN1_PHYA0_WAKEUP_INTR___M 0x00078000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_STATUS__WCMN_PMM_WLAN1_PHYA0_WAKEUP_INTR___S 15 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_STATUS__WCMN_PMM_WLAN1_WMAC0_WAKEUP_INTR___M 0x0000001F +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_STATUS__WCMN_PMM_WLAN1_WMAC0_WAKEUP_INTR___S 0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_STATUS___M 0x0007801F +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCMN_PMM_WAKEUP_INTR_STATUS___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_NOC_UMACACCESS_IN_PWR_CLPS (0x00B50200) +#define TOP_CMN_WCSS_WCMN_R0_NOC_UMACACCESS_IN_PWR_CLPS___RWC QCSR_REG_RO +#define TOP_CMN_WCSS_WCMN_R0_NOC_UMACACCESS_IN_PWR_CLPS___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_NOC_UMACACCESS_IN_PWR_CLPS__ADDR___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_NOC_UMACACCESS_IN_PWR_CLPS__ADDR___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_NOC_UMACACCESS_IN_PWR_CLPS__ADDR___S 0 +#define TOP_CMN_WCSS_WCMN_R0_NOC_UMACACCESS_IN_PWR_CLPS___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_NOC_UMACACCESS_IN_PWR_CLPS___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_NOC_UMACACCESS_IN_PWR_CLPS_WRITE (0x00B50204) +#define TOP_CMN_WCSS_WCMN_R0_NOC_UMACACCESS_IN_PWR_CLPS_WRITE___RWC QCSR_REG_RO +#define TOP_CMN_WCSS_WCMN_R0_NOC_UMACACCESS_IN_PWR_CLPS_WRITE___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_NOC_UMACACCESS_IN_PWR_CLPS_WRITE__CMD___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_NOC_UMACACCESS_IN_PWR_CLPS_WRITE__CMD___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_NOC_UMACACCESS_IN_PWR_CLPS_WRITE__CMD___S 0 +#define TOP_CMN_WCSS_WCMN_R0_NOC_UMACACCESS_IN_PWR_CLPS_WRITE___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_NOC_UMACACCESS_IN_PWR_CLPS_WRITE___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_WFSS_PMM_AHB_CLK_CTRL (0x00B5020C) +#define TOP_CMN_WCSS_WCMN_R0_WFSS_PMM_AHB_CLK_CTRL___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_WFSS_PMM_AHB_CLK_CTRL___POR 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_WFSS_PMM_AHB_CLK_CTRL__CLKGATE_DISABLE___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_WFSS_PMM_AHB_CLK_CTRL__CLK_EN___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_WFSS_PMM_AHB_CLK_CTRL__CLKGATE_DISABLE___M 0x00000002 +#define TOP_CMN_WCSS_WCMN_R0_WFSS_PMM_AHB_CLK_CTRL__CLKGATE_DISABLE___S 1 +#define TOP_CMN_WCSS_WCMN_R0_WFSS_PMM_AHB_CLK_CTRL__CLK_EN___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_WFSS_PMM_AHB_CLK_CTRL__CLK_EN___S 0 +#define TOP_CMN_WCSS_WCMN_R0_WFSS_PMM_AHB_CLK_CTRL___M 0x00000003 +#define TOP_CMN_WCSS_WCMN_R0_WFSS_PMM_AHB_CLK_CTRL___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE2 (0x00B50210) +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE2___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE2___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE2__REGISTER___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE2__REGISTER___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE2__REGISTER___S 0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE2___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE2___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE3 (0x00B50214) +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE3___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE3___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE3__REGISTER___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE3__REGISTER___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE3__REGISTER___S 0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE3___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_ENABLE3___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS2 (0x00B50218) +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS2___RWC QCSR_REG_RO +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS2___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS2__REGISTER___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS2__REGISTER___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS2__REGISTER___S 0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS2___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS2___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS3 (0x00B5021C) +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS3___RWC QCSR_REG_RO +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS3___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS3__REGISTER___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS3__REGISTER___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS3__REGISTER___S 0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS3___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_STATUS3___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2 (0x00B50220) +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__SNOC_I_UMAC_NOC_ACC_ERR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__WAHB_PWR_DWN_ACC_ERR_INT___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__DBGAPB_TSLV_IRQ___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__MEM_ERR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PHYA_NOC_WCMN_TIMEOUT_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMH_INT___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_RFACTRL_IDLE_REQ_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_SNOC_IDLE_REQ_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_SR_XO_SETTLE_TIMEOUT_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_UMAC_IDE_CHK_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_APB_INVLD_APB_ACCESS_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_ERR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_APS_DS_REQ_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_APS_SW_ENTER_LS_IS_ERR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_APS_SW_WLAN_OFF_IS_ERR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_APS_WLAN_IDLE_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_ERR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__SNOC_I_UMAC_NOC_ACC_ERR_INTR___M 0x00040000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__SNOC_I_UMAC_NOC_ACC_ERR_INTR___S 18 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__WAHB_PWR_DWN_ACC_ERR_INT___M 0x00020000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__WAHB_PWR_DWN_ACC_ERR_INT___S 17 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__DBGAPB_TSLV_IRQ___M 0x00010000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__DBGAPB_TSLV_IRQ___S 16 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__MEM_ERR_INTR___M 0x00008000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__MEM_ERR_INTR___S 15 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PHYA_NOC_WCMN_TIMEOUT_INTR___M 0x00004000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PHYA_NOC_WCMN_TIMEOUT_INTR___S 14 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMH_INT___M 0x00001000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMH_INT___S 12 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_RFACTRL_IDLE_REQ_TO_INTR___M 0x00000800 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_RFACTRL_IDLE_REQ_TO_INTR___S 11 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_SNOC_IDLE_REQ_TO_INTR___M 0x00000400 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_SNOC_IDLE_REQ_TO_INTR___S 10 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_SR_XO_SETTLE_TIMEOUT_INTR___M 0x00000200 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_SR_XO_SETTLE_TIMEOUT_INTR___S 9 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_UMAC_IDE_CHK_TO_INTR___M 0x00000100 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_UMAC_IDE_CHK_TO_INTR___S 8 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_APB_INVLD_APB_ACCESS_INTR___M 0x00000080 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_APB_INVLD_APB_ACCESS_INTR___S 7 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_ERR_INTR___M 0x00000040 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_ERR_INTR___S 6 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___M 0x00000020 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___S 5 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_APS_DS_REQ_TO_INTR___M 0x00000010 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_APS_DS_REQ_TO_INTR___S 4 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_APS_SW_ENTER_LS_IS_ERR_INTR___M 0x00000008 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_APS_SW_ENTER_LS_IS_ERR_INTR___S 3 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_APS_SW_WLAN_OFF_IS_ERR_INTR___M 0x00000004 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_APS_SW_WLAN_OFF_IS_ERR_INTR___S 2 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_APS_WLAN_IDLE_TO_INTR___M 0x00000002 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_APS_WLAN_IDLE_TO_INTR___S 1 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_ERR_INTR___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2__PMM_WCMN_WLAN1_ERR_INTR___S 0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2___M 0x0007DFFF +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR2___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3 (0x00B50224) +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__WCSS_MSSQ6_WDOG_BITE___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ___POR 0x000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__NOC_UMACACCESS_IN_PWR_CLPS_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__PMM_WCMN_WLAN1_LS_DONE_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__PMM_WL_CMN_PWRDOWN_CHK_TO_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__CE_INTR_MISC_HOST_APB_WR_INVALID_ADDR_P___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__WCSS_RET_ACMT_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__WCSS_MSSQ6_WDOG_BITE___M 0x20000000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__WCSS_MSSQ6_WDOG_BITE___S 29 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ___M 0x1FF00000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ___S 20 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__NOC_UMACACCESS_IN_PWR_CLPS_INTR___M 0x00080000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__NOC_UMACACCESS_IN_PWR_CLPS_INTR___S 19 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__PMM_WCMN_WLAN1_LS_DONE_INTR___M 0x00040000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__PMM_WCMN_WLAN1_LS_DONE_INTR___S 18 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___M 0x00020000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___S 17 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___M 0x00010000 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___S 16 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__PMM_WL_CMN_PWRDOWN_CHK_TO_INTR___M 0x00000040 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__PMM_WL_CMN_PWRDOWN_CHK_TO_INTR___S 6 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__CE_INTR_MISC_HOST_APB_WR_INVALID_ADDR_P___M 0x00000020 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__CE_INTR_MISC_HOST_APB_WR_INVALID_ADDR_P___S 5 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__WCSS_RET_ACMT_INTR___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3__WCSS_RET_ACMT_INTR___S 0 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3___M 0x3FFF0061 +#define TOP_CMN_WCSS_WCMN_R0_AGGR_WCSS_WAKEUP_INTR_CLEAR3___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_MISC_CGC_DISABLE (0x00B50230) +#define TOP_CMN_WCSS_WCMN_R0_MISC_CGC_DISABLE___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_MISC_CGC_DISABLE___POR 0x0000FFFF +#define TOP_CMN_WCSS_WCMN_R0_MISC_CGC_DISABLE__CGC_DISABLE___POR 0x0000FFFF +#define TOP_CMN_WCSS_WCMN_R0_MISC_CGC_DISABLE__CGC_DISABLE___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_MISC_CGC_DISABLE__CGC_DISABLE___S 0 +#define TOP_CMN_WCSS_WCMN_R0_MISC_CGC_DISABLE___M 0xFFFFFFFF +#define TOP_CMN_WCSS_WCMN_R0_MISC_CGC_DISABLE___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS (0x00B5100C) +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS___RWC QCSR_REG_RO +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__PMM_WCMN_WLAN1_LS_DONE_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__O_WLAN1_H2S_GRANT_INT___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__WCSS_MSSQ6_WAKEUP_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__AGGRE_PWR_TIMEOUT_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__AGGRE_PWR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__AGGRE_FATAL_ERR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__PHYA0_Q6_IRQ_3_0___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__WMAC0_WCMN_INTR_4_0___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__WMAC0_HOST_RXDMA_SRNG_INTR_19_0___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__UMAC_AGGR_INTR_6_0___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___M 0x00800000 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___S 23 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___M 0x00400000 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___S 22 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__PMM_WCMN_WLAN1_LS_DONE_INTR___M 0x00080000 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__PMM_WCMN_WLAN1_LS_DONE_INTR___S 19 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___M 0x00040000 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___S 18 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__O_WLAN1_H2S_GRANT_INT___M 0x00010000 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__O_WLAN1_H2S_GRANT_INT___S 16 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ___M 0x00008000 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ___S 15 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__WCSS_MSSQ6_WAKEUP_INTR___M 0x00004000 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__WCSS_MSSQ6_WAKEUP_INTR___S 14 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__AGGRE_PWR_TIMEOUT_INTR___M 0x00002000 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__AGGRE_PWR_TIMEOUT_INTR___S 13 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__AGGRE_PWR_INTR___M 0x00001000 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__AGGRE_PWR_INTR___S 12 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__AGGRE_FATAL_ERR___M 0x00000800 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__AGGRE_FATAL_ERR___S 11 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__PHYA0_Q6_IRQ_3_0___M 0x00000100 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__PHYA0_Q6_IRQ_3_0___S 8 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__WMAC0_WCMN_INTR_4_0___M 0x00000020 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__WMAC0_WCMN_INTR_4_0___S 5 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__WMAC0_HOST_RXDMA_SRNG_INTR_19_0___M 0x00000004 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__WMAC0_HOST_RXDMA_SRNG_INTR_19_0___S 2 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__UMAC_AGGR_INTR_6_0___M 0x00000002 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS__UMAC_AGGR_INTR_6_0___S 1 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS___M 0x00CDF926 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_STATUS___S 1 + +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR (0x00B51010) +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__PMM_WCMN_WLAN1_LS_DONE_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__O_WLAN1_H2S_GRANT_INT___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__WCSS_MSSQ6_WAKEUP_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__AGGRE_PWR_TIMEOUT_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__AGGRE_PWR_INTR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__AGGRE_FATAL_ERR___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__PHYA0_Q6_IRQ_3_0___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__WMAC0_WCMN_INTR_4_0___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__WMAC0_HOST_RXDMA_SRNG_INTR_19_0___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__UMAC_AGGR_INTR_6_0___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__UMAC_WCMN_MPSS_Q6_IPC_3_0___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___M 0x00800000 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__PMM_WCMN_WLAN1_REG_SAVE_ALERT_INTR___S 23 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___M 0x00400000 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__PMM_WCMN_WLAN1_REG_RESTORE_ALERT_INTR___S 22 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__PMM_WCMN_WLAN1_LS_DONE_INTR___M 0x00080000 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__PMM_WCMN_WLAN1_LS_DONE_INTR___S 19 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___M 0x00040000 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__PMM_WCMN_WLAN1_APS_DS_REQ_INTR___S 18 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__O_WLAN1_H2S_GRANT_INT___M 0x00010000 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__O_WLAN1_H2S_GRANT_INT___S 16 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ___M 0x00008000 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__WCSSAON_WCSS_Q6SS_WAKEUP_IRQ___S 15 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__WCSS_MSSQ6_WAKEUP_INTR___M 0x00004000 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__WCSS_MSSQ6_WAKEUP_INTR___S 14 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__AGGRE_PWR_TIMEOUT_INTR___M 0x00002000 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__AGGRE_PWR_TIMEOUT_INTR___S 13 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__AGGRE_PWR_INTR___M 0x00001000 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__AGGRE_PWR_INTR___S 12 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__AGGRE_FATAL_ERR___M 0x00000800 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__AGGRE_FATAL_ERR___S 11 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__PHYA0_Q6_IRQ_3_0___M 0x00000100 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__PHYA0_Q6_IRQ_3_0___S 8 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__WMAC0_WCMN_INTR_4_0___M 0x00000020 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__WMAC0_WCMN_INTR_4_0___S 5 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__WMAC0_HOST_RXDMA_SRNG_INTR_19_0___M 0x00000004 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__WMAC0_HOST_RXDMA_SRNG_INTR_19_0___S 2 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__UMAC_AGGR_INTR_6_0___M 0x00000002 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__UMAC_AGGR_INTR_6_0___S 1 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__UMAC_WCMN_MPSS_Q6_IPC_3_0___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR__UMAC_WCMN_MPSS_Q6_IPC_3_0___S 0 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR___M 0x00CDF927 +#define TOP_CMN_WCSS_WCMN_R0_APPS_AGGRE_INTR_CLEAR___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_Q6_UMAC_NOC_CLK_REQ (0x00B51014) +#define TOP_CMN_WCSS_WCMN_R0_Q6_UMAC_NOC_CLK_REQ___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_Q6_UMAC_NOC_CLK_REQ___POR 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_Q6_UMAC_NOC_CLK_REQ__WCSS_Q6_UMAC_NOC_CLK_REQ___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_Q6_UMAC_NOC_CLK_REQ__WCSS_Q6_UMAC_NOC_CLK_REQ___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_Q6_UMAC_NOC_CLK_REQ__WCSS_Q6_UMAC_NOC_CLK_REQ___S 0 +#define TOP_CMN_WCSS_WCMN_R0_Q6_UMAC_NOC_CLK_REQ___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_Q6_UMAC_NOC_CLK_REQ___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_SPARE_UMAC_NOC_CLK_REQ (0x00B51018) +#define TOP_CMN_WCSS_WCMN_R0_SPARE_UMAC_NOC_CLK_REQ___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_SPARE_UMAC_NOC_CLK_REQ___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_SPARE_UMAC_NOC_CLK_REQ__WCSS_SPARE_UMAC_NOC_CLK_REQ___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_SPARE_UMAC_NOC_CLK_REQ__WCSS_SPARE_UMAC_NOC_CLK_REQ___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_SPARE_UMAC_NOC_CLK_REQ__WCSS_SPARE_UMAC_NOC_CLK_REQ___S 0 +#define TOP_CMN_WCSS_WCMN_R0_SPARE_UMAC_NOC_CLK_REQ___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_SPARE_UMAC_NOC_CLK_REQ___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_Q6_LMAC0_CLK_REQ (0x00B5101C) +#define TOP_CMN_WCSS_WCMN_R0_Q6_LMAC0_CLK_REQ___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_Q6_LMAC0_CLK_REQ___POR 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_Q6_LMAC0_CLK_REQ__WCSS_Q6_MAC0_MAC_CLK_REQ___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_Q6_LMAC0_CLK_REQ__WCSS_Q6_MAC0_MAC_CLK_REQ___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_Q6_LMAC0_CLK_REQ__WCSS_Q6_MAC0_MAC_CLK_REQ___S 0 +#define TOP_CMN_WCSS_WCMN_R0_Q6_LMAC0_CLK_REQ___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_Q6_LMAC0_CLK_REQ___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_PHY_M3_LMAC0_CLK_REQ (0x00B51020) +#define TOP_CMN_WCSS_WCMN_R0_PHY_M3_LMAC0_CLK_REQ___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_PHY_M3_LMAC0_CLK_REQ___POR 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_PHY_M3_LMAC0_CLK_REQ__WCSS_M3_MAC0_MAC_CLK_REQ___POR 0x1 +#define TOP_CMN_WCSS_WCMN_R0_PHY_M3_LMAC0_CLK_REQ__WCSS_M3_MAC0_MAC_CLK_REQ___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_PHY_M3_LMAC0_CLK_REQ__WCSS_M3_MAC0_MAC_CLK_REQ___S 0 +#define TOP_CMN_WCSS_WCMN_R0_PHY_M3_LMAC0_CLK_REQ___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_PHY_M3_LMAC0_CLK_REQ___S 0 + +#define TOP_CMN_WCSS_WCMN_R0_SPARE_LMAC0_CLK_REQ (0x00B51024) +#define TOP_CMN_WCSS_WCMN_R0_SPARE_LMAC0_CLK_REQ___RWC QCSR_REG_RW +#define TOP_CMN_WCSS_WCMN_R0_SPARE_LMAC0_CLK_REQ___POR 0x00000000 +#define TOP_CMN_WCSS_WCMN_R0_SPARE_LMAC0_CLK_REQ__WCSS_SPARE_MAC0_MAC_CLK_REQ___POR 0x0 +#define TOP_CMN_WCSS_WCMN_R0_SPARE_LMAC0_CLK_REQ__WCSS_SPARE_MAC0_MAC_CLK_REQ___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_SPARE_LMAC0_CLK_REQ__WCSS_SPARE_MAC0_MAC_CLK_REQ___S 0 +#define TOP_CMN_WCSS_WCMN_R0_SPARE_LMAC0_CLK_REQ___M 0x00000001 +#define TOP_CMN_WCSS_WCMN_R0_SPARE_LMAC0_CLK_REQ___S 0 + + +#define WCMN_CORE_BASE (0x00B58000) + +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1 (0x00B58000) +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1___POR 0x00000000 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1__REG_31___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1__SW_EVENTBUS_VALID___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1__SW_MODULE_ID___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1__SW_EVENT_ID___POR 0x00 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1__SW_EVENTDATA___POR 0x00000 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1__REG_31___M 0x80000000 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1__REG_31___S 31 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1__SW_EVENTBUS_VALID___M 0x40000000 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1__SW_EVENTBUS_VALID___S 30 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1__SW_MODULE_ID___M 0x3C000000 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1__SW_MODULE_ID___S 26 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1__SW_EVENT_ID___M 0x03F00000 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1__SW_EVENT_ID___S 20 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1__SW_EVENTDATA___M 0x000FFFFF +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1__SW_EVENTDATA___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL1___S 0 + +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2 (0x00B5800C) +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2___POR 0x00000000 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__REG___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__TRC_EVENT_SEL___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__SUB_SYS_TESTBUS_SEL___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__EVENT_BLK_MASK_BIT_1___POR 0x00 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__CPU_MISC_TRC_EVENT_SEL___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__TRC_BUS_MUX_SEL___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__EVENT_BLK_MASK_BIT_2___POR 0x0000 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__REG___M 0xC0000000 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__REG___S 30 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__TRC_EVENT_SEL___M 0x20000000 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__TRC_EVENT_SEL___S 29 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__SUB_SYS_TESTBUS_SEL___M 0x1C000000 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__SUB_SYS_TESTBUS_SEL___S 26 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__EVENT_BLK_MASK_BIT_1___M 0x03FC0000 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__EVENT_BLK_MASK_BIT_1___S 18 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__CPU_MISC_TRC_EVENT_SEL___M 0x00020000 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__CPU_MISC_TRC_EVENT_SEL___S 17 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__TRC_BUS_MUX_SEL___M 0x0001E000 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__TRC_BUS_MUX_SEL___S 13 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__EVENT_BLK_MASK_BIT_2___M 0x00001FFF +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2__EVENT_BLK_MASK_BIT_2___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_CTRL2___S 0 + +#define WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL (0x00B58020) +#define WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL___POR 0x00000001 +#define WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_CONFIGRESET_MCMN___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_CLKGATEDIS_MCMN___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_GLOBAL_CLKGATE_DISABLE___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_ROOT_CLKGATE_DIS_MCMN___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_SOFTRESET_MCMN___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_ROOT_CLOCK_EN_MCMN___POR 0x1 +#define WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_CONFIGRESET_MCMN___M 0x00000020 +#define WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_CONFIGRESET_MCMN___S 5 +#define WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_CLKGATEDIS_MCMN___M 0x00000010 +#define WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_CLKGATEDIS_MCMN___S 4 +#define WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_GLOBAL_CLKGATE_DISABLE___M 0x00000008 +#define WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_GLOBAL_CLKGATE_DISABLE___S 3 +#define WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_ROOT_CLKGATE_DIS_MCMN___M 0x00000004 +#define WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_ROOT_CLKGATE_DIS_MCMN___S 2 +#define WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_SOFTRESET_MCMN___M 0x00000002 +#define WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_SOFTRESET_MCMN___S 1 +#define WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_ROOT_CLOCK_EN_MCMN___M 0x00000001 +#define WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL__WCMN_MRCM_WMAC0_ROOT_CLOCK_EN_MCMN___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL___M 0x0000003F +#define WCMN_CORE_WCMN_CORE_R0_WMAC_CLK_CTRL___S 0 + +#define WCMN_CORE_WCMN_CORE_R0_WCMN_UMAC (0x00B58024) +#define WCMN_CORE_WCMN_CORE_R0_WCMN_UMAC___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WCMN_UMAC___POR 0x00000000 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_UMAC__CTL_SOFT_RESET___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_UMAC__CFG_SOFT_RESET___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_UMAC__CTL_SOFT_RESET___M 0x00000002 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_UMAC__CTL_SOFT_RESET___S 1 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_UMAC__CFG_SOFT_RESET___M 0x00000001 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_UMAC__CFG_SOFT_RESET___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_UMAC___M 0x00000003 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_UMAC___S 0 + +#define WCMN_CORE_WCMN_CORE_R0_WCMN_LMAC (0x00B58028) +#define WCMN_CORE_WCMN_CORE_R0_WCMN_LMAC___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WCMN_LMAC___POR 0x00000000 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_LMAC__MAC0_CTL_SOFT_RESET___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_LMAC__MAC0_CFG_SOFT_RESET___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_LMAC__MAC0_CTL_SOFT_RESET___M 0x00000002 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_LMAC__MAC0_CTL_SOFT_RESET___S 1 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_LMAC__MAC0_CFG_SOFT_RESET___M 0x00000001 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_LMAC__MAC0_CFG_SOFT_RESET___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_LMAC___M 0x00000003 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_LMAC___S 0 + +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL (0x00B5802C) +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL___POR 0x00000000 +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__S_PARE_02___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__PHYA1_RFACTRL_ADC_CLK_RATE___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__PHYA0_RFACTRL_ADC_CLK_RATE___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__S_PARE_01___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__PHYA1_RFACTRL_DAC_CLK_RATE___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__PHYA0_RFACTRL_DAC_CLK_RATE___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__WCMN_PHYA_SBS_MODE___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__S_PARE_00___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__WCMN_PHYA1_WARM_RESET___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__WCMN_PHYA0_WARM_RESET___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__S_PARE_02___M 0x00070000 +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__S_PARE_02___S 16 +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__PHYA1_RFACTRL_ADC_CLK_RATE___M 0x0000E000 +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__PHYA1_RFACTRL_ADC_CLK_RATE___S 13 +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__PHYA0_RFACTRL_ADC_CLK_RATE___M 0x00001C00 +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__PHYA0_RFACTRL_ADC_CLK_RATE___S 10 +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__S_PARE_01___M 0x00000300 +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__S_PARE_01___S 8 +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__PHYA1_RFACTRL_DAC_CLK_RATE___M 0x000000C0 +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__PHYA1_RFACTRL_DAC_CLK_RATE___S 6 +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__PHYA0_RFACTRL_DAC_CLK_RATE___M 0x00000030 +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__PHYA0_RFACTRL_DAC_CLK_RATE___S 4 +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__WCMN_PHYA_SBS_MODE___M 0x00000008 +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__WCMN_PHYA_SBS_MODE___S 3 +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__S_PARE_00___M 0x00000004 +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__S_PARE_00___S 2 +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__WCMN_PHYA1_WARM_RESET___M 0x00000002 +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__WCMN_PHYA1_WARM_RESET___S 1 +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__WCMN_PHYA0_WARM_RESET___M 0x00000001 +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL__WCMN_PHYA0_WARM_RESET___S 0 +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL___M 0x0007FFFF +#define WCMN_CORE_WCMN_CORE_R0_PHY_CTRL___S 0 + +#define WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL (0x00B58034) +#define WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL___POR 0x00000001 +#define WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL__WCMN_CRCM_CLKGATEDIS_CCMN___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL__WCMN_CRCM_CPUMISC_GLOBAL_CLKGATE_DISABLE___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL__WCMN_CRCM_ROOT_CLKGATE_DIS_CCMN___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL__WCMN_CRCM_SOFTRESET_CCMN___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL__WCMN_CRCM_ROOT_CLOCK_EN_CCMN___POR 0x1 +#define WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL__WCMN_CRCM_CLKGATEDIS_CCMN___M 0x00000010 +#define WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL__WCMN_CRCM_CLKGATEDIS_CCMN___S 4 +#define WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL__WCMN_CRCM_CPUMISC_GLOBAL_CLKGATE_DISABLE___M 0x00000008 +#define WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL__WCMN_CRCM_CPUMISC_GLOBAL_CLKGATE_DISABLE___S 3 +#define WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL__WCMN_CRCM_ROOT_CLKGATE_DIS_CCMN___M 0x00000004 +#define WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL__WCMN_CRCM_ROOT_CLKGATE_DIS_CCMN___S 2 +#define WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL__WCMN_CRCM_SOFTRESET_CCMN___M 0x00000002 +#define WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL__WCMN_CRCM_SOFTRESET_CCMN___S 1 +#define WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL__WCMN_CRCM_ROOT_CLOCK_EN_CCMN___M 0x00000001 +#define WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL__WCMN_CRCM_ROOT_CLOCK_EN_CCMN___S 0 +#define WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL___M 0x0000001F +#define WCMN_CORE_WCMN_CORE_R0_HELIUM_TOP_CLK_CTRL___S 0 + +#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_ENABLE (0x00B581B4) +#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_ENABLE___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_ENABLE___POR 0x00000000 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_ENABLE__A1_REG_RESTORE_INTR___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_ENABLE__A1_REG_SAVE_INTR___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_ENABLE__A0_REG_RESTORE_INTR___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_ENABLE__A0_REG_SAVE_INTR___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_ENABLE__A1_REG_RESTORE_INTR___M 0x00000008 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_ENABLE__A1_REG_RESTORE_INTR___S 3 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_ENABLE__A1_REG_SAVE_INTR___M 0x00000004 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_ENABLE__A1_REG_SAVE_INTR___S 2 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_ENABLE__A0_REG_RESTORE_INTR___M 0x00000002 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_ENABLE__A0_REG_RESTORE_INTR___S 1 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_ENABLE__A0_REG_SAVE_INTR___M 0x00000001 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_ENABLE__A0_REG_SAVE_INTR___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_ENABLE___M 0x0000000F +#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_ENABLE___S 0 + +#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_CLEAR (0x00B581BC) +#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_CLEAR___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_CLEAR___POR 0x00000000 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_CLEAR__A1_REG_RESTORE_INTR___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_CLEAR__A1_REG_SAVE_INTR___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_CLEAR__A0_REG_RESTORE_INTR___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_CLEAR__A0_REG_SAVE_INTR___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_CLEAR__A1_REG_RESTORE_INTR___M 0x00000008 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_CLEAR__A1_REG_RESTORE_INTR___S 3 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_CLEAR__A1_REG_SAVE_INTR___M 0x00000004 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_CLEAR__A1_REG_SAVE_INTR___S 2 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_CLEAR__A0_REG_RESTORE_INTR___M 0x00000002 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_CLEAR__A0_REG_RESTORE_INTR___S 1 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_CLEAR__A0_REG_SAVE_INTR___M 0x00000001 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_CLEAR__A0_REG_SAVE_INTR___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_CLEAR___M 0x0000000F +#define WCMN_CORE_WCMN_CORE_R0_WCMN_PHYA_CLEAR___S 0 + +#define WCMN_CORE_WCMN_CORE_R0_WFSS_PMM_RESET (0x00B58208) +#define WCMN_CORE_WCMN_CORE_R0_WFSS_PMM_RESET___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WFSS_PMM_RESET___POR 0x00000003 +#define WCMN_CORE_WCMN_CORE_R0_WFSS_PMM_RESET__GLOBAL_RST_N___POR 0x1 +#define WCMN_CORE_WCMN_CORE_R0_WFSS_PMM_RESET__REG_RST_N___POR 0x1 +#define WCMN_CORE_WCMN_CORE_R0_WFSS_PMM_RESET__GLOBAL_RST_N___M 0x00000002 +#define WCMN_CORE_WCMN_CORE_R0_WFSS_PMM_RESET__GLOBAL_RST_N___S 1 +#define WCMN_CORE_WCMN_CORE_R0_WFSS_PMM_RESET__REG_RST_N___M 0x00000001 +#define WCMN_CORE_WCMN_CORE_R0_WFSS_PMM_RESET__REG_RST_N___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WFSS_PMM_RESET___M 0x00000003 +#define WCMN_CORE_WCMN_CORE_R0_WFSS_PMM_RESET___S 0 + +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_SW_EVENTMASK_IX0 (0x00B58228) +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_SW_EVENTMASK_IX0___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_SW_EVENTMASK_IX0___POR 0x00000000 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_SW_EVENTMASK_IX0__REGISTER___POR 0x00000000 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_SW_EVENTMASK_IX0__REGISTER___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_SW_EVENTMASK_IX0__REGISTER___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_SW_EVENTMASK_IX0___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_SW_EVENTMASK_IX0___S 0 + +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_SW_EVENTMASK_IX1 (0x00B5822C) +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_SW_EVENTMASK_IX1___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_SW_EVENTMASK_IX1___POR 0x00000000 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_SW_EVENTMASK_IX1__REGISTER___POR 0x00000000 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_SW_EVENTMASK_IX1__REGISTER___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_SW_EVENTMASK_IX1__REGISTER___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_SW_EVENTMASK_IX1___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WCMN_CCMN_SW_EVENTMASK_IX1___S 0 + +#define WCMN_CORE_WCMN_CORE_R0_S_PARE_0 (0x00B58230) +#define WCMN_CORE_WCMN_CORE_R0_S_PARE_0___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_S_PARE_0___POR 0x00000000 +#define WCMN_CORE_WCMN_CORE_R0_S_PARE_0__VAL___POR 0x00000000 +#define WCMN_CORE_WCMN_CORE_R0_S_PARE_0__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_S_PARE_0__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_S_PARE_0___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_S_PARE_0___S 0 + +#define WCMN_CORE_WCMN_CORE_R0_S_PARE_1 (0x00B58234) +#define WCMN_CORE_WCMN_CORE_R0_S_PARE_1___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_S_PARE_1___POR 0x00000000 +#define WCMN_CORE_WCMN_CORE_R0_S_PARE_1__VAL___POR 0x00000000 +#define WCMN_CORE_WCMN_CORE_R0_S_PARE_1__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_S_PARE_1__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_S_PARE_1___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_S_PARE_1___S 0 + +#define WCMN_CORE_WCMN_CORE_R0_S_PARE_2 (0x00B58238) +#define WCMN_CORE_WCMN_CORE_R0_S_PARE_2___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_S_PARE_2___POR 0x00000000 +#define WCMN_CORE_WCMN_CORE_R0_S_PARE_2__VAL___POR 0x00000000 +#define WCMN_CORE_WCMN_CORE_R0_S_PARE_2__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_S_PARE_2__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_S_PARE_2___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_S_PARE_2___S 0 + +#define WCMN_CORE_WCMN_CORE_R0_S_PARE_3 (0x00B5823C) +#define WCMN_CORE_WCMN_CORE_R0_S_PARE_3___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_S_PARE_3___POR 0x00000000 +#define WCMN_CORE_WCMN_CORE_R0_S_PARE_3__VAL___POR 0x00000000 +#define WCMN_CORE_WCMN_CORE_R0_S_PARE_3__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_S_PARE_3__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_S_PARE_3___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_S_PARE_3___S 0 + +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_n(n) (0x00B58240+0x4*(n)) +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_n_nMIN 0 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_n_nMAX 31 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_n_ELEM 32 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_n___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_n___POR 0x00000000 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_n__VAL___POR 0x00000000 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_n__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_n__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_n___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_n___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_0 (0x00B58240) +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_0___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_0__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_0__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_1 (0x00B58244) +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_1___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_1__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_1__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_2 (0x00B58248) +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_2___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_2__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_2__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_3 (0x00B5824C) +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_3___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_3__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_3__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_4 (0x00B58250) +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_4___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_4__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_4__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_5 (0x00B58254) +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_5___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_5__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_5__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_6 (0x00B58258) +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_6___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_6__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_6__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_7 (0x00B5825C) +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_7___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_7__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_7__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_8 (0x00B58260) +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_8___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_8__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_8__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_9 (0x00B58264) +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_9___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_9__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_9__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_10 (0x00B58268) +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_10___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_10__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_10__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_11 (0x00B5826C) +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_11___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_11__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_11__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_12 (0x00B58270) +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_12___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_12__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_12__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_13 (0x00B58274) +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_13___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_13__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_13__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_14 (0x00B58278) +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_14___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_14__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_14__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_15 (0x00B5827C) +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_15___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_15__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_15__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_16 (0x00B58280) +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_16___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_16__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_16__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_17 (0x00B58284) +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_17___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_17__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_17__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_18 (0x00B58288) +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_18___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_18__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_18__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_19 (0x00B5828C) +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_19___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_19__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_19__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_20 (0x00B58290) +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_20___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_20__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_20__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_21 (0x00B58294) +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_21___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_21__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_21__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_22 (0x00B58298) +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_22___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_22__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_22__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_23 (0x00B5829C) +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_23___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_23__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_23__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_24 (0x00B582A0) +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_24___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_24__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_24__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_25 (0x00B582A4) +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_25___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_25__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_25__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_26 (0x00B582A8) +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_26___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_26__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_26__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_27 (0x00B582AC) +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_27___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_27__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_27__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_28 (0x00B582B0) +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_28___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_28__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_28__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_29 (0x00B582B4) +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_29___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_29__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_29__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_30 (0x00B582B8) +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_30___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_30__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_30__VAL___S 0 +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_31 (0x00B582BC) +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_31___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_31__VAL___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_WLAN_CONTEXT_REG_31__VAL___S 0 + +#define WCMN_CORE_WCMN_CORE_R0_VI_PHY_SELECT (0x00B582C0) +#define WCMN_CORE_WCMN_CORE_R0_VI_PHY_SELECT___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_VI_PHY_SELECT___POR 0x00000000 +#define WCMN_CORE_WCMN_CORE_R0_VI_PHY_SELECT__WLAN1___POR 0x0 +#define WCMN_CORE_WCMN_CORE_R0_VI_PHY_SELECT__WLAN1___M 0x00000001 +#define WCMN_CORE_WCMN_CORE_R0_VI_PHY_SELECT__WLAN1___S 0 +#define WCMN_CORE_WCMN_CORE_R0_VI_PHY_SELECT___M 0x00000001 +#define WCMN_CORE_WCMN_CORE_R0_VI_PHY_SELECT___S 0 + +#define WCMN_CORE_WCMN_CORE_R0_PMM_SPARE_REG (0x00B58880) +#define WCMN_CORE_WCMN_CORE_R0_PMM_SPARE_REG___RWC QCSR_REG_RW +#define WCMN_CORE_WCMN_CORE_R0_PMM_SPARE_REG___POR 0x00000000 +#define WCMN_CORE_WCMN_CORE_R0_PMM_SPARE_REG__SPARE_REG___POR 0x00000000 +#define WCMN_CORE_WCMN_CORE_R0_PMM_SPARE_REG__SPARE_REG___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_PMM_SPARE_REG__SPARE_REG___S 0 +#define WCMN_CORE_WCMN_CORE_R0_PMM_SPARE_REG___M 0xFFFFFFFF +#define WCMN_CORE_WCMN_CORE_R0_PMM_SPARE_REG___S 0 + + +#define WFSS_PMM_BASE (0x00B60000) + +#define WFSS_PMM_WFSS_PMM_R0_PMM_INVALID_APB_ACC_ADDR (0x00B60000) +#define WFSS_PMM_WFSS_PMM_R0_PMM_INVALID_APB_ACC_ADDR___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R0_PMM_INVALID_APB_ACC_ADDR___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_INVALID_APB_ACC_ADDR__VALUE___POR 0x00000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_INVALID_APB_ACC_ADDR__VALUE___M 0x0001FFFF +#define WFSS_PMM_WFSS_PMM_R0_PMM_INVALID_APB_ACC_ADDR__VALUE___S 0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_INVALID_APB_ACC_ADDR___M 0x0001FFFF +#define WFSS_PMM_WFSS_PMM_R0_PMM_INVALID_APB_ACC_ADDR___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PWRDN_DLY (0x00B60004) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PWRDN_DLY___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PWRDN_DLY___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PWRDN_DLY__VALUE___POR 0x0000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PWRDN_DLY__VALUE___M 0x0000FFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PWRDN_DLY__VALUE___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PWRDN_DLY___M 0x0000FFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PWRDN_DLY___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1 (0x00B60008) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1___POR 0x00000781 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__DIRECT_SYNTH_ON___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__NAP_THRESHOLD___POR 0x0000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__EARLY_WAKE_DURATION___POR 0x0F +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__COEX_DS_EN___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__COEX_LS_EN___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__COEX_NAP_EN___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__MAC_DS_EN___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__MAC_LS_EN___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__MAC_NAP_EN___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__APS_FSM_EN___POR 0x1 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__DIRECT_SYNTH_ON___M 0x80000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__DIRECT_SYNTH_ON___S 31 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__NAP_THRESHOLD___M 0x7FFF8000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__NAP_THRESHOLD___S 15 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__EARLY_WAKE_DURATION___M 0x00007F80 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__EARLY_WAKE_DURATION___S 7 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__COEX_DS_EN___M 0x00000040 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__COEX_DS_EN___S 6 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__COEX_LS_EN___M 0x00000020 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__COEX_LS_EN___S 5 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__COEX_NAP_EN___M 0x00000010 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__COEX_NAP_EN___S 4 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__MAC_DS_EN___M 0x00000008 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__MAC_DS_EN___S 3 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__MAC_LS_EN___M 0x00000004 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__MAC_LS_EN___S 2 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__MAC_NAP_EN___M 0x00000002 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__MAC_NAP_EN___S 1 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__APS_FSM_EN___M 0x00000001 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1__APS_FSM_EN___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG1___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_LS_AND_DS_THRESHOLD (0x00B6000C) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_LS_AND_DS_THRESHOLD___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_LS_AND_DS_THRESHOLD___POR 0x000F00C8 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_LS_AND_DS_THRESHOLD__DS_THRESHOLD___POR 0x0F +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_LS_AND_DS_THRESHOLD__LS_THRESHOLD___POR 0x00C8 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_LS_AND_DS_THRESHOLD__DS_THRESHOLD___M 0x00FF0000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_LS_AND_DS_THRESHOLD__DS_THRESHOLD___S 16 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_LS_AND_DS_THRESHOLD__LS_THRESHOLD___M 0x0000FFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_LS_AND_DS_THRESHOLD__LS_THRESHOLD___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_LS_AND_DS_THRESHOLD___M 0x00FFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_LS_AND_DS_THRESHOLD___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN_PMM_APS_DS_THRESHOLD_CONV_CONSTANT (0x00B60010) +#define WFSS_PMM_WFSS_PMM_R0_WLAN_PMM_APS_DS_THRESHOLD_CONV_CONSTANT___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_WLAN_PMM_APS_DS_THRESHOLD_CONV_CONSTANT___POR 0x000003E8 +#define WFSS_PMM_WFSS_PMM_R0_WLAN_PMM_APS_DS_THRESHOLD_CONV_CONSTANT__VALUE___POR 0x3E8 +#define WFSS_PMM_WFSS_PMM_R0_WLAN_PMM_APS_DS_THRESHOLD_CONV_CONSTANT__VALUE___M 0x000003FF +#define WFSS_PMM_WFSS_PMM_R0_WLAN_PMM_APS_DS_THRESHOLD_CONV_CONSTANT__VALUE___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN_PMM_APS_DS_THRESHOLD_CONV_CONSTANT___M 0x000003FF +#define WFSS_PMM_WFSS_PMM_R0_WLAN_PMM_APS_DS_THRESHOLD_CONV_CONSTANT___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_STATE_MACHINE_DELAYS (0x00B60014) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_STATE_MACHINE_DELAYS___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_STATE_MACHINE_DELAYS___POR 0x0101004E +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_STATE_MACHINE_DELAYS__SW_SYN_SETTLE_TIMER_EN___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_STATE_MACHINE_DELAYS__MIN_IDLE_WAIT_DLY___POR 0x40 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_STATE_MACHINE_DELAYS__PHY_ON_TO_OFF_DLY___POR 0x40 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_STATE_MACHINE_DELAYS__SYNTH_SETTLE_DLY___POR 0x04E +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_STATE_MACHINE_DELAYS__SW_SYN_SETTLE_TIMER_EN___M 0x04000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_STATE_MACHINE_DELAYS__SW_SYN_SETTLE_TIMER_EN___S 26 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_STATE_MACHINE_DELAYS__MIN_IDLE_WAIT_DLY___M 0x03FC0000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_STATE_MACHINE_DELAYS__MIN_IDLE_WAIT_DLY___S 18 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_STATE_MACHINE_DELAYS__PHY_ON_TO_OFF_DLY___M 0x0003FC00 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_STATE_MACHINE_DELAYS__PHY_ON_TO_OFF_DLY___S 10 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_STATE_MACHINE_DELAYS__SYNTH_SETTLE_DLY___M 0x000003FF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_STATE_MACHINE_DELAYS__SYNTH_SETTLE_DLY___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_STATE_MACHINE_DELAYS___M 0x07FFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_STATE_MACHINE_DELAYS___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_IDLE_WAIT_TIMEOUT_DELAY (0x00B60018) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_IDLE_WAIT_TIMEOUT_DELAY___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_IDLE_WAIT_TIMEOUT_DELAY___POR 0x00010019 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_IDLE_WAIT_TIMEOUT_DELAY__USE_IDLE_TO_DLY_IN_US___POR 0x1 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_IDLE_WAIT_TIMEOUT_DELAY__IDLE_WAIT_TIMEOUT_DLY___POR 0x0019 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_IDLE_WAIT_TIMEOUT_DELAY__USE_IDLE_TO_DLY_IN_US___M 0x00010000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_IDLE_WAIT_TIMEOUT_DELAY__USE_IDLE_TO_DLY_IN_US___S 16 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_IDLE_WAIT_TIMEOUT_DELAY__IDLE_WAIT_TIMEOUT_DLY___M 0x0000FFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_IDLE_WAIT_TIMEOUT_DELAY__IDLE_WAIT_TIMEOUT_DLY___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_IDLE_WAIT_TIMEOUT_DELAY___M 0x0001FFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_IDLE_WAIT_TIMEOUT_DELAY___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_SW_ENTER_LS (0x00B6001C) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_SW_ENTER_LS___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_SW_ENTER_LS___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_SW_ENTER_LS__SW_ENTER_LS___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_SW_ENTER_LS__SW_ENTER_LS_ID___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_SW_ENTER_LS__SW_ENTER_LS___M 0x00000008 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_SW_ENTER_LS__SW_ENTER_LS___S 3 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_SW_ENTER_LS__SW_ENTER_LS_ID___M 0x00000007 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_SW_ENTER_LS__SW_ENTER_LS_ID___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_SW_ENTER_LS___M 0x0000000F +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_SW_ENTER_LS___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2 (0x00B60020) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2___POR 0x00001080 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__USE_IDLE_WAIT_TO_AS_IDLE___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__IDLE_WAIT_TO_EN___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__USE_POPSO_ACK_TO_AS_POPSO___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__PHY_OFF_SYNTH_OFF_ACK_WDOG_TO_EN___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_PHY_OFF_WAIT_4_SYNTH_SETTLE___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__WAIT_TO_ENTER_LS_S_IN_DMPS___POR 0x1 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_PHY_ON_STATUS___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_PHY_ON___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_PHY_OFF_STATUS___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_PHY_OFF___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__APS_ADC_CTRL_EN___POR 0x1 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_OVR_PWR_REQ___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_OVR_PWR_REQ_VLD___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__APS_FSM_RESET___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_WAKE_FROM_LS___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__USE_IDLE_WAIT_TO_AS_IDLE___M 0x00020000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__USE_IDLE_WAIT_TO_AS_IDLE___S 17 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__IDLE_WAIT_TO_EN___M 0x00010000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__IDLE_WAIT_TO_EN___S 16 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__USE_POPSO_ACK_TO_AS_POPSO___M 0x00008000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__USE_POPSO_ACK_TO_AS_POPSO___S 15 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__PHY_OFF_SYNTH_OFF_ACK_WDOG_TO_EN___M 0x00004000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__PHY_OFF_SYNTH_OFF_ACK_WDOG_TO_EN___S 14 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_PHY_OFF_WAIT_4_SYNTH_SETTLE___M 0x00002000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_PHY_OFF_WAIT_4_SYNTH_SETTLE___S 13 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__WAIT_TO_ENTER_LS_S_IN_DMPS___M 0x00001000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__WAIT_TO_ENTER_LS_S_IN_DMPS___S 12 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_PHY_ON_STATUS___M 0x00000800 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_PHY_ON_STATUS___S 11 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_PHY_ON___M 0x00000400 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_PHY_ON___S 10 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_PHY_OFF_STATUS___M 0x00000200 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_PHY_OFF_STATUS___S 9 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_PHY_OFF___M 0x00000100 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_PHY_OFF___S 8 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__APS_ADC_CTRL_EN___M 0x00000080 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__APS_ADC_CTRL_EN___S 7 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_OVR_PWR_REQ___M 0x00000070 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_OVR_PWR_REQ___S 4 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_OVR_PWR_REQ_VLD___M 0x00000008 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_OVR_PWR_REQ_VLD___S 3 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__APS_FSM_RESET___M 0x00000004 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__APS_FSM_RESET___S 2 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_WAKE_FROM_LS___M 0x00000002 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2__SW_WAKE_FROM_LS___S 1 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2___M 0x0003FFFE +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG2___S 1 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG3 (0x00B60024) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG3___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG3___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG3__APS_DIS_CGC___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG3__APS_FSM_HOLD_IN_STATE___POR 0x000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG3__APS_DIS_CGC___M 0x00001000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG3__APS_DIS_CGC___S 12 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG3__APS_FSM_HOLD_IN_STATE___M 0x00000FFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG3__APS_FSM_HOLD_IN_STATE___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG3___M 0x00001FFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CFG_REG3___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_DS_DURATION_REMAINING (0x00B60028) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_DS_DURATION_REMAINING___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_DS_DURATION_REMAINING___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_DS_DURATION_REMAINING__DS_DURATION_REMAINING___POR 0x0000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_DS_DURATION_REMAINING__DS_DURATION_REMAINING___M 0x0000FFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_DS_DURATION_REMAINING__DS_DURATION_REMAINING___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_DS_DURATION_REMAINING___M 0x0000FFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_DS_DURATION_REMAINING___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_NAP_COUNTER_HS (0x00B6002C) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_NAP_COUNTER_HS___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_NAP_COUNTER_HS___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_NAP_COUNTER_HS__NAP_CUML_DURN_HS___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_NAP_COUNTER_HS__NAP_CUML_DURN_HS___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_NAP_COUNTER_HS__NAP_CUML_DURN_HS___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_NAP_COUNTER_HS___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_NAP_COUNTER_HS___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_NAP_COUNTER_LS (0x00B60030) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_NAP_COUNTER_LS___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_NAP_COUNTER_LS___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_NAP_COUNTER_LS__NAP_CUML_DURN_LS___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_NAP_COUNTER_LS__NAP_CUML_DURN_LS___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_NAP_COUNTER_LS__NAP_CUML_DURN_LS___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_NAP_COUNTER_LS___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_NAP_COUNTER_LS___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_LIGHT_SLEEP_COUNTER_HS (0x00B60034) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_LIGHT_SLEEP_COUNTER_HS___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_LIGHT_SLEEP_COUNTER_HS___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_LIGHT_SLEEP_COUNTER_HS__LS_CUML_DURN_HS___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_LIGHT_SLEEP_COUNTER_HS__LS_CUML_DURN_HS___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_LIGHT_SLEEP_COUNTER_HS__LS_CUML_DURN_HS___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_LIGHT_SLEEP_COUNTER_HS___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_LIGHT_SLEEP_COUNTER_HS___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_LIGHT_SLEEP_COUNTER_LS (0x00B60038) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_LIGHT_SLEEP_COUNTER_LS___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_LIGHT_SLEEP_COUNTER_LS___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_LIGHT_SLEEP_COUNTER_LS__LS_CUML_DURN_LS___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_LIGHT_SLEEP_COUNTER_LS__LS_CUML_DURN_LS___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_LIGHT_SLEEP_COUNTER_LS__LS_CUML_DURN_LS___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_LIGHT_SLEEP_COUNTER_LS___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_LIGHT_SLEEP_COUNTER_LS___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_DEEP_SLEEP_COUNTER_HS (0x00B6003C) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_DEEP_SLEEP_COUNTER_HS___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_DEEP_SLEEP_COUNTER_HS___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_DEEP_SLEEP_COUNTER_HS__DS_CUML_DURN_HS___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_DEEP_SLEEP_COUNTER_HS__DS_CUML_DURN_HS___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_DEEP_SLEEP_COUNTER_HS__DS_CUML_DURN_HS___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_DEEP_SLEEP_COUNTER_HS___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_DEEP_SLEEP_COUNTER_HS___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_DEEP_SLEEP_COUNTER_LS (0x00B60040) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_DEEP_SLEEP_COUNTER_LS___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_DEEP_SLEEP_COUNTER_LS___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_DEEP_SLEEP_COUNTER_LS__DS_CUML_DURN_LS___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_DEEP_SLEEP_COUNTER_LS__DS_CUML_DURN_LS___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_DEEP_SLEEP_COUNTER_LS__DS_CUML_DURN_LS___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_DEEP_SLEEP_COUNTER_LS___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PMM_APS_CUMULATIVE_DEEP_SLEEP_COUNTER_LS___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG1 (0x00B60044) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG1___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG1___POR 0x00010801 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG1__STATUS___POR 0x00010801 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG1__STATUS___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG1__STATUS___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG1___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG1___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2 (0x00B60048) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2__PWR_REQ_FIFO_LEVEL___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2__DYN_MIMO_PS_ALL___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2__DYN_MIMO_PS_ACTIVE___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2__DS_CNT_DN_TO_CUML_CTR___POR 0x000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2__DS_REQ_CUML_CTR___POR 0x000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2__PWR_REQ_FIFO_LEVEL___M 0x00C00000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2__PWR_REQ_FIFO_LEVEL___S 22 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2__DYN_MIMO_PS_ALL___M 0x00200000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2__DYN_MIMO_PS_ALL___S 21 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2__DYN_MIMO_PS_ACTIVE___M 0x00100000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2__DYN_MIMO_PS_ACTIVE___S 20 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2__DS_CNT_DN_TO_CUML_CTR___M 0x000FFC00 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2__DS_CNT_DN_TO_CUML_CTR___S 10 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2__DS_REQ_CUML_CTR___M 0x000003FF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2__DS_REQ_CUML_CTR___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2___M 0x00FFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG2___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG3 (0x00B6004C) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG3___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG3___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG3__SW_WLAN_OFF_CUML_CTR___POR 0x000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG3__ENTER_LS_H_CUML_CTR___POR 0x000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG3__ENTER_LS_S_CUML_CTR___POR 0x000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG3__SW_WLAN_OFF_CUML_CTR___M 0x3FF00000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG3__SW_WLAN_OFF_CUML_CTR___S 20 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG3__ENTER_LS_H_CUML_CTR___M 0x000FFC00 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG3__ENTER_LS_H_CUML_CTR___S 10 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG3__ENTER_LS_S_CUML_CTR___M 0x000003FF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG3__ENTER_LS_S_CUML_CTR___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG3___M 0x3FFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG3___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4 (0x00B60050) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4__SW_PHY_ON_PENDING___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4__SW_PHY_OFF_PENDING___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4__DS_CNT___POR 0x000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4__LS_CNT___POR 0x000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4__NAP_CNT___POR 0x000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4__SW_PHY_ON_PENDING___M 0x80000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4__SW_PHY_ON_PENDING___S 31 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4__SW_PHY_OFF_PENDING___M 0x40000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4__SW_PHY_OFF_PENDING___S 30 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4__DS_CNT___M 0x3FF00000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4__DS_CNT___S 20 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4__LS_CNT___M 0x000FFC00 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4__LS_CNT___S 10 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4__NAP_CNT___M 0x000003FF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4__NAP_CNT___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_STATUS_REG4___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS1 (0x00B60054) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS1___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS1___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS1__SW_HW_INTF1___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS1__SW_HW_INTF1___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS1__SW_HW_INTF1___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS1___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS1___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS2 (0x00B60058) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS2___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS2___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS2__SW_HW_INTF1___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS2__SW_HW_INTF1___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS2__SW_HW_INTF1___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS2___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS2___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS3 (0x00B6005C) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS3___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS3___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS3__SW_HW_INTF2___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS3__SW_HW_INTF2___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS3__SW_HW_INTF2___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS3___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_SW_HW_INTF_STATUS3___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE (0x00B60060) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__PHY_FSM_STAY_IN_STATE___POR 0x00 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__PHY_FSM_FORCE_INIT___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__PHY_IDLE_HANDSHAKE_FSM_RESET___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__PHY_FORCE_CLR_IDLE_REQ___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__PHY_FORCE_SET_IDLE_REQ___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__WMAC_FSM_STAY_IN_STATE___POR 0x00 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__WMAC_FSM_FORCE_INIT___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__WMAC_IDLE_HANDSHAKE_FSM_RESET___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__WMAC_FORCE_CLR_IDLE_REQ___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__WMAC_FORCE_SET_IDLE_REQ___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__PHY_FSM_STAY_IN_STATE___M 0x0003E000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__PHY_FSM_STAY_IN_STATE___S 13 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__PHY_FSM_FORCE_INIT___M 0x00001000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__PHY_FSM_FORCE_INIT___S 12 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__PHY_IDLE_HANDSHAKE_FSM_RESET___M 0x00000800 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__PHY_IDLE_HANDSHAKE_FSM_RESET___S 11 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__PHY_FORCE_CLR_IDLE_REQ___M 0x00000400 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__PHY_FORCE_CLR_IDLE_REQ___S 10 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__PHY_FORCE_SET_IDLE_REQ___M 0x00000200 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__PHY_FORCE_SET_IDLE_REQ___S 9 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__WMAC_FSM_STAY_IN_STATE___M 0x000001F0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__WMAC_FSM_STAY_IN_STATE___S 4 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__WMAC_FSM_FORCE_INIT___M 0x00000008 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__WMAC_FSM_FORCE_INIT___S 3 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__WMAC_IDLE_HANDSHAKE_FSM_RESET___M 0x00000004 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__WMAC_IDLE_HANDSHAKE_FSM_RESET___S 2 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__WMAC_FORCE_CLR_IDLE_REQ___M 0x00000002 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__WMAC_FORCE_CLR_IDLE_REQ___S 1 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__WMAC_FORCE_SET_IDLE_REQ___M 0x00000001 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE__WMAC_FORCE_SET_IDLE_REQ___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE___M 0x0003FFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_HANDSHAKE___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_GENERAL_DELAY (0x00B60064) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_GENERAL_DELAY___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_GENERAL_DELAY___POR 0x0003FC03 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_GENERAL_DELAY__WAKEUP_INT_TO_POS_DLY___POR 0x0FF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_GENERAL_DELAY__PO_PSO_ACK_WAIT_DLY___POR 0x003 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_GENERAL_DELAY__WAKEUP_INT_TO_POS_DLY___M 0x000FFC00 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_GENERAL_DELAY__WAKEUP_INT_TO_POS_DLY___S 10 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_GENERAL_DELAY__PO_PSO_ACK_WAIT_DLY___M 0x000003FF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_GENERAL_DELAY__PO_PSO_ACK_WAIT_DLY___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_GENERAL_DELAY___M 0x000FFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_GENERAL_DELAY___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_S_PARE_DBG (0x00B60068) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_S_PARE_DBG___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_S_PARE_DBG___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_S_PARE_DBG__VALUE___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_S_PARE_DBG__VALUE___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_S_PARE_DBG__VALUE___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_S_PARE_DBG___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_S_PARE_DBG___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_WLAN_WDOG_DLY (0x00B6006C) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_WLAN_WDOG_DLY___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_WLAN_WDOG_DLY___POR 0x00002000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_WLAN_WDOG_DLY__VALUE___POR 0x02000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_WLAN_WDOG_DLY__VALUE___M 0x000FFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_WLAN_WDOG_DLY__VALUE___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_WLAN_WDOG_DLY___M 0x000FFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_WLAN_WDOG_DLY___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_WDOG_DLY (0x00B60070) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_WDOG_DLY___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_WDOG_DLY___POR 0x00002000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_WDOG_DLY__VALUE___POR 0x02000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_WDOG_DLY__VALUE___M 0x000FFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_WDOG_DLY__VALUE___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_WDOG_DLY___M 0x000FFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_APS_WDOG_DLY___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1A_CFG_REG1 (0x00B60074) +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1A_CFG_REG1___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1A_CFG_REG1___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1A_CFG_REG1__SW_GLOTIM_TO_MAC1A_VLD___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1A_CFG_REG1__SW_WMAC1A_WAKE___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1A_CFG_REG1__SW_WMAC1A_WAKE_EN___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1A_CFG_REG1__SW_GLOTIM_TO_MAC1A_VLD___M 0x00000004 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1A_CFG_REG1__SW_GLOTIM_TO_MAC1A_VLD___S 2 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1A_CFG_REG1__SW_WMAC1A_WAKE___M 0x00000002 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1A_CFG_REG1__SW_WMAC1A_WAKE___S 1 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1A_CFG_REG1__SW_WMAC1A_WAKE_EN___M 0x00000001 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1A_CFG_REG1__SW_WMAC1A_WAKE_EN___S 0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1A_CFG_REG1___M 0x00000007 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1A_CFG_REG1___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN_APS_GENERAL_CFG_REG1 (0x00B60078) +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN_APS_GENERAL_CFG_REG1___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN_APS_GENERAL_CFG_REG1___POR 0x00000010 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN_APS_GENERAL_CFG_REG1__SYNTH_ON_KO_DLY___POR 0x010 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN_APS_GENERAL_CFG_REG1__SYNTH_ON_KO_DLY___M 0x000003FF +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN_APS_GENERAL_CFG_REG1__SYNTH_ON_KO_DLY___S 0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN_APS_GENERAL_CFG_REG1___M 0x000003FF +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN_APS_GENERAL_CFG_REG1___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN (0x00B6007C) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN___POR 0x0000003F +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__DS_MAC_WAKE_PO_TO_EN___POR 0x1 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__FCS_PHY_OFF_ACK_TO_EN___POR 0x1 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__SW_PHY_SYNTH_OFF_ACK_TO_EN___POR 0x1 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__HW_PHY_SYNTH_OFF_ACK_TO_EN___POR 0x1 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__SW_PHY_OFF_ACK_TO_EN___POR 0x1 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__HW_PHY_OFF_ACK_TO_EN___POR 0x1 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__DS_MAC_WAKE_PO_TO_EN___M 0x00000020 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__DS_MAC_WAKE_PO_TO_EN___S 5 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__FCS_PHY_OFF_ACK_TO_EN___M 0x00000010 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__FCS_PHY_OFF_ACK_TO_EN___S 4 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__SW_PHY_SYNTH_OFF_ACK_TO_EN___M 0x00000008 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__SW_PHY_SYNTH_OFF_ACK_TO_EN___S 3 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__HW_PHY_SYNTH_OFF_ACK_TO_EN___M 0x00000004 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__HW_PHY_SYNTH_OFF_ACK_TO_EN___S 2 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__SW_PHY_OFF_ACK_TO_EN___M 0x00000002 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__SW_PHY_OFF_ACK_TO_EN___S 1 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__HW_PHY_OFF_ACK_TO_EN___M 0x00000001 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN__HW_PHY_OFF_ACK_TO_EN___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN___M 0x0000003F +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_PO_PSO_TIMEOUT_EN___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_MAC_WAKE_PHY_OFF_OPEN_LOOP_ACK (0x00B60080) +#define WFSS_PMM_WFSS_PMM_R0_MAC_WAKE_PHY_OFF_OPEN_LOOP_ACK___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_MAC_WAKE_PHY_OFF_OPEN_LOOP_ACK___POR 0x00000334 +#define WFSS_PMM_WFSS_PMM_R0_MAC_WAKE_PHY_OFF_OPEN_LOOP_ACK__WAIT_DLY___POR 0x00334 +#define WFSS_PMM_WFSS_PMM_R0_MAC_WAKE_PHY_OFF_OPEN_LOOP_ACK__WAIT_DLY___M 0x000FFFFF +#define WFSS_PMM_WFSS_PMM_R0_MAC_WAKE_PHY_OFF_OPEN_LOOP_ACK__WAIT_DLY___S 0 +#define WFSS_PMM_WFSS_PMM_R0_MAC_WAKE_PHY_OFF_OPEN_LOOP_ACK___M 0x000FFFFF +#define WFSS_PMM_WFSS_PMM_R0_MAC_WAKE_PHY_OFF_OPEN_LOOP_ACK___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_PMM_IDLE (0x00B60084) +#define WFSS_PMM_WFSS_PMM_R0_PMM_IDLE___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_PMM_IDLE___POR 0x00000005 +#define WFSS_PMM_WFSS_PMM_R0_PMM_IDLE__PMM_IDLE_PRETEND___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_IDLE__IDLE_INTG_DLY___POR 0x05 +#define WFSS_PMM_WFSS_PMM_R0_PMM_IDLE__PMM_IDLE_PRETEND___M 0x00000100 +#define WFSS_PMM_WFSS_PMM_R0_PMM_IDLE__PMM_IDLE_PRETEND___S 8 +#define WFSS_PMM_WFSS_PMM_R0_PMM_IDLE__IDLE_INTG_DLY___M 0x000000FF +#define WFSS_PMM_WFSS_PMM_R0_PMM_IDLE__IDLE_INTG_DLY___S 0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_IDLE___M 0x000001FF +#define WFSS_PMM_WFSS_PMM_R0_PMM_IDLE___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE (0x00B60088) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE___POR 0x00000003 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE__PHY_CSYSREQ_TO_ACK_LOOPBACK_EN___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE__PHY_CSYSACK_OVR_DATA___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE__PHY_CSYSACK_OVR___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE__PHY_CSYSREQ_OVR_DATA___POR 0x1 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE__PHY_CSYSREQ_OVR___POR 0x1 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE__PHY_CSYSREQ_TO_ACK_LOOPBACK_EN___M 0x00000010 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE__PHY_CSYSREQ_TO_ACK_LOOPBACK_EN___S 4 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE__PHY_CSYSACK_OVR_DATA___M 0x00000008 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE__PHY_CSYSACK_OVR_DATA___S 3 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE__PHY_CSYSACK_OVR___M 0x00000004 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE__PHY_CSYSACK_OVR___S 2 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE__PHY_CSYSREQ_OVR_DATA___M 0x00000002 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE__PHY_CSYSREQ_OVR_DATA___S 1 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE__PHY_CSYSREQ_OVR___M 0x00000001 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE__PHY_CSYSREQ_OVR___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE___M 0x0000001F +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TRACER_IDLE_HANDSHAKE___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_H2S (0x00B6008C) +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_H2S___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_H2S___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_H2S__H2S_DISABLE_CLK_GATING___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_H2S__H2S_DISABLE_CLK_GATING___M 0x00000002 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_H2S__H2S_DISABLE_CLK_GATING___S 1 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_H2S___M 0x00000002 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_H2S___S 1 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT (0x00B60090) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT__SKT_DISCACK_LOOPBACK_EN___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT__SKT_DISCACK_OVR_DATA___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT__SKT_DISCACK_OVR_EN___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT__SKT_DISCREQ_OVR_DATA___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT__SKT_DISCREQ_OVR_EN___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT__SKT_DISCACK_LOOPBACK_EN___M 0x00000010 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT__SKT_DISCACK_LOOPBACK_EN___S 4 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT__SKT_DISCACK_OVR_DATA___M 0x00000008 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT__SKT_DISCACK_OVR_DATA___S 3 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT__SKT_DISCACK_OVR_EN___M 0x00000004 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT__SKT_DISCACK_OVR_EN___S 2 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT__SKT_DISCREQ_OVR_DATA___M 0x00000002 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT__SKT_DISCREQ_OVR_DATA___S 1 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT__SKT_DISCREQ_OVR_EN___M 0x00000001 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT__SKT_DISCREQ_OVR_EN___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT___M 0x0000001F +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_UMAC_SKT_DISCONNECT___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG1 (0x00B60098) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG1___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG1___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG1__WLAN1_ADC_CLAMP_DLY___POR 0x0000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG1__WLAN1_ADC_PWRON_DLY___POR 0x0000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG1__WLAN1_ADC_CLAMP_DLY___M 0xFFFF0000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG1__WLAN1_ADC_CLAMP_DLY___S 16 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG1__WLAN1_ADC_PWRON_DLY___M 0x0000FFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG1__WLAN1_ADC_PWRON_DLY___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG1___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG1___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG2 (0x00B6009C) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG2___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG2___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG2__WLAN1_ADC_PWRDN_DLY___POR 0x0000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG2__WLAN1_ADC_CLK_DIS_DLY___POR 0x0000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG2__WLAN1_ADC_PWRDN_DLY___M 0xFFFF0000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG2__WLAN1_ADC_PWRDN_DLY___S 16 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG2__WLAN1_ADC_CLK_DIS_DLY___M 0x0000FFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG2__WLAN1_ADC_CLK_DIS_DLY___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG2___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_ADC_DLY_REG2___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_RRI_SAVE_ADDR (0x00B600A0) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_RRI_SAVE_ADDR___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_RRI_SAVE_ADDR___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_RRI_SAVE_ADDR__WLAN1_RRI_SAVE_ADDR___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_RRI_SAVE_ADDR__WLAN1_RRI_SAVE_ADDR___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_RRI_SAVE_ADDR__WLAN1_RRI_SAVE_ADDR___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_RRI_SAVE_ADDR___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_RRI_SAVE_ADDR___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_RRI_RESTORE_ADDR (0x00B600A4) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_RRI_RESTORE_ADDR___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_RRI_RESTORE_ADDR___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_RRI_RESTORE_ADDR__WLAN1_RRI_RESTORE_ADDR___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_RRI_RESTORE_ADDR__WLAN1_RRI_RESTORE_ADDR___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_RRI_RESTORE_ADDR__WLAN1_RRI_RESTORE_ADDR___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_RRI_RESTORE_ADDR___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_RRI_RESTORE_ADDR___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_H2S (0x00B600A8) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_H2S___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_H2S___POR 0x00000148 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_H2S__WLAN1_H2S_THRESHOLD___POR 0x0A4 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_H2S__WLAN1_H2S_REQ___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_H2S__WLAN1_H2S_THRESHOLD___M 0x000007FE +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_H2S__WLAN1_H2S_THRESHOLD___S 1 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_H2S__WLAN1_H2S_REQ___M 0x00000001 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_H2S__WLAN1_H2S_REQ___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_H2S___M 0x000007FF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_H2S___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_CFG_REG3 (0x00B600AC) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_CFG_REG3___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_CFG_REG3___POR 0x00000028 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_CFG_REG3__CHKN_BIT_CLR_SLP_TMR_INT_EARLY___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_CFG_REG3__PRETEND_MAC_SENT_PHY_OFF___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_CFG_REG3__WAKEUP_BACKOFF_TIME___POR 0x28 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_CFG_REG3__CHKN_BIT_CLR_SLP_TMR_INT_EARLY___M 0x00000200 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_CFG_REG3__CHKN_BIT_CLR_SLP_TMR_INT_EARLY___S 9 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_CFG_REG3__PRETEND_MAC_SENT_PHY_OFF___M 0x00000100 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_CFG_REG3__PRETEND_MAC_SENT_PHY_OFF___S 8 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_CFG_REG3__WAKEUP_BACKOFF_TIME___M 0x000000FF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_CFG_REG3__WAKEUP_BACKOFF_TIME___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_CFG_REG3___M 0x000003FF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_CFG_REG3___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_NEXT_WAKEUP_TIME_U (0x00B600B0) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_NEXT_WAKEUP_TIME_U___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_NEXT_WAKEUP_TIME_U___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_NEXT_WAKEUP_TIME_U__VALUE___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_NEXT_WAKEUP_TIME_U__VALUE___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_NEXT_WAKEUP_TIME_U__VALUE___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_NEXT_WAKEUP_TIME_U___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_NEXT_WAKEUP_TIME_U___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_NEXT_WAKEUP_TIME_L (0x00B600B4) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_NEXT_WAKEUP_TIME_L___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_NEXT_WAKEUP_TIME_L___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_NEXT_WAKEUP_TIME_L__VALUE___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_NEXT_WAKEUP_TIME_L__VALUE___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_NEXT_WAKEUP_TIME_L__VALUE___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_NEXT_WAKEUP_TIME_L___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_NEXT_WAKEUP_TIME_L___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY (0x00B600B8) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__PWR_DWN_AFTER_PHY1_TO___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__PWR_DWN_AFTER_MAC1_TO___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__PHY1_IDLE_STABLE_CHK_EN___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__WMAC1_IDLE_STABLE_CHK_EN___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__PHY1_IDLE_DLY___POR 0x00 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__WMAC1_IDLE_DLY___POR 0x00 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__PWR_DWN_AFTER_PHY1_TO___M 0x00080000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__PWR_DWN_AFTER_PHY1_TO___S 19 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__PWR_DWN_AFTER_MAC1_TO___M 0x00040000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__PWR_DWN_AFTER_MAC1_TO___S 18 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__PHY1_IDLE_STABLE_CHK_EN___M 0x00020000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__PHY1_IDLE_STABLE_CHK_EN___S 17 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__WMAC1_IDLE_STABLE_CHK_EN___M 0x00010000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__WMAC1_IDLE_STABLE_CHK_EN___S 16 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__PHY1_IDLE_DLY___M 0x0000FF00 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__PHY1_IDLE_DLY___S 8 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__WMAC1_IDLE_DLY___M 0x000000FF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY__WMAC1_IDLE_DLY___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY___M 0x000FFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_STABLE_DLY___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_TIMEOUT (0x00B600BC) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_TIMEOUT___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_TIMEOUT___POR 0x00190019 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_TIMEOUT__PHY1_IDLE_WAIT_TIMEOUT_DLY___POR 0x0019 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_TIMEOUT__WMAC1_IDLE_WAIT_TIMEOUT_DLY___POR 0x0019 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_TIMEOUT__PHY1_IDLE_WAIT_TIMEOUT_DLY___M 0xFFFF0000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_TIMEOUT__PHY1_IDLE_WAIT_TIMEOUT_DLY___S 16 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_TIMEOUT__WMAC1_IDLE_WAIT_TIMEOUT_DLY___M 0x0000FFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_TIMEOUT__WMAC1_IDLE_WAIT_TIMEOUT_DLY___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_TIMEOUT___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IDLE_TIMEOUT___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_PMM_CTRL (0x00B600C0) +#define WFSS_PMM_WFSS_PMM_R0_PMM_CTRL___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_PMM_CTRL___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__RFACTRL_DOWN_PRETEND___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__CSS_DOWN_PRETEND___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__CCU_PMM_CLKGATE_DISABLE___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__NO_CPUMISC_SS_CLAMP___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__CCU_PMM_CLKGATE_DIS_OVRD_VAL___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__CCU_PMM_CLKGATE_DIS_OVRD_EN___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__TESTBUS_SEL___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__RFACTRL_DOWN_PRETEND___M 0x00000200 +#define WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__RFACTRL_DOWN_PRETEND___S 9 +#define WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__CSS_DOWN_PRETEND___M 0x00000100 +#define WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__CSS_DOWN_PRETEND___S 8 +#define WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__CCU_PMM_CLKGATE_DISABLE___M 0x00000080 +#define WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__CCU_PMM_CLKGATE_DISABLE___S 7 +#define WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__NO_CPUMISC_SS_CLAMP___M 0x00000040 +#define WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__NO_CPUMISC_SS_CLAMP___S 6 +#define WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__CCU_PMM_CLKGATE_DIS_OVRD_VAL___M 0x00000020 +#define WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__CCU_PMM_CLKGATE_DIS_OVRD_VAL___S 5 +#define WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__CCU_PMM_CLKGATE_DIS_OVRD_EN___M 0x00000010 +#define WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__CCU_PMM_CLKGATE_DIS_OVRD_EN___S 4 +#define WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__TESTBUS_SEL___M 0x0000000F +#define WFSS_PMM_WFSS_PMM_R0_PMM_CTRL__TESTBUS_SEL___S 0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_CTRL___M 0x000003FF +#define WFSS_PMM_WFSS_PMM_R0_PMM_CTRL___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_PMM_SLEEPCLOCK_CONSTANT1 (0x00B600C4) +#define WFSS_PMM_WFSS_PMM_R0_PMM_SLEEPCLOCK_CONSTANT1___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_PMM_SLEEPCLOCK_CONSTANT1___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SLEEPCLOCK_CONSTANT1__US_TO_SLEEPCLOCK_CONSTANT___POR 0x00000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SLEEPCLOCK_CONSTANT1__US_TO_SLEEPCLOCK_CONSTANT___M 0x000FFFFF +#define WFSS_PMM_WFSS_PMM_R0_PMM_SLEEPCLOCK_CONSTANT1__US_TO_SLEEPCLOCK_CONSTANT___S 0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SLEEPCLOCK_CONSTANT1___M 0x000FFFFF +#define WFSS_PMM_WFSS_PMM_R0_PMM_SLEEPCLOCK_CONSTANT1___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_PMM_SLEEPCLOCK_CONSTANT2 (0x00B600C8) +#define WFSS_PMM_WFSS_PMM_R0_PMM_SLEEPCLOCK_CONSTANT2___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_PMM_SLEEPCLOCK_CONSTANT2___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SLEEPCLOCK_CONSTANT2__SLEEPCLK_TO_US_CONSTANT___POR 0x00000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SLEEPCLOCK_CONSTANT2__SLEEPCLK_TO_US_CONSTANT___M 0x000FFFFF +#define WFSS_PMM_WFSS_PMM_R0_PMM_SLEEPCLOCK_CONSTANT2__SLEEPCLK_TO_US_CONSTANT___S 0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SLEEPCLOCK_CONSTANT2___M 0x000FFFFF +#define WFSS_PMM_WFSS_PMM_R0_PMM_SLEEPCLOCK_CONSTANT2___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_GLOTIM_CTRL (0x00B600CC) +#define WFSS_PMM_WFSS_PMM_R0_GLOTIM_CTRL___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_GLOTIM_CTRL___POR 0x00000077 +#define WFSS_PMM_WFSS_PMM_R0_GLOTIM_CTRL__SW_SLEEP_TMR_FORCE_UPDATE___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_GLOTIM_CTRL__SLP_TMR_TO_MAC2_SW_VLD___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_GLOTIM_CTRL__SLP_TMR_TO_MAC1_SW_VLD___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_GLOTIM_CTRL__NOC_CLK_TO_1US_CONST___POR 0x077 +#define WFSS_PMM_WFSS_PMM_R0_GLOTIM_CTRL__SW_SLEEP_TMR_FORCE_UPDATE___M 0x00001000 +#define WFSS_PMM_WFSS_PMM_R0_GLOTIM_CTRL__SW_SLEEP_TMR_FORCE_UPDATE___S 12 +#define WFSS_PMM_WFSS_PMM_R0_GLOTIM_CTRL__SLP_TMR_TO_MAC2_SW_VLD___M 0x00000800 +#define WFSS_PMM_WFSS_PMM_R0_GLOTIM_CTRL__SLP_TMR_TO_MAC2_SW_VLD___S 11 +#define WFSS_PMM_WFSS_PMM_R0_GLOTIM_CTRL__SLP_TMR_TO_MAC1_SW_VLD___M 0x00000400 +#define WFSS_PMM_WFSS_PMM_R0_GLOTIM_CTRL__SLP_TMR_TO_MAC1_SW_VLD___S 10 +#define WFSS_PMM_WFSS_PMM_R0_GLOTIM_CTRL__NOC_CLK_TO_1US_CONST___M 0x000003FF +#define WFSS_PMM_WFSS_PMM_R0_GLOTIM_CTRL__NOC_CLK_TO_1US_CONST___S 0 +#define WFSS_PMM_WFSS_PMM_R0_GLOTIM_CTRL___M 0x00001FFF +#define WFSS_PMM_WFSS_PMM_R0_GLOTIM_CTRL___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_PMM_SPARE_REG (0x00B600D0) +#define WFSS_PMM_WFSS_PMM_R0_PMM_SPARE_REG___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_PMM_SPARE_REG___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SPARE_REG__SPARE_REG___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SPARE_REG__SPARE_REG___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_PMM_SPARE_REG__SPARE_REG___S 0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SPARE_REG___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_PMM_SPARE_REG___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1 (0x00B600D4) +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1___POR 0x00000400 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__RF_ADC1_PWRDN_N_STATUS___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__RF_ADC1_CLAMP_STATUS___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__MAC1_IDLE_STATUS___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__PHY1_IDLE_STATUS___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__REINIT_DONE_PRETEND___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__PHY1_IDLE_TIMEOUT_EN___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__MAC1_IDLE_TIMEOUT_EN___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__NEXT_WAKEUP_TIME_SW_OVR___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__WLAN_ADC_DIGITAL_CLAMP___POR 0x1 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__RFIF_ADC_PWRDN_N___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_DOWN_PRETEND___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_HALTREQ_TO_EN___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_HALTREQ_OVRD___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_HALTREQ___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_FORCE_ON___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_FORCE_IDLE___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_OFF___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__WLAN1_REG_REINIT_IGNORE___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__WLAN1_CLKGATE_DISABLE___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__RF_ADC1_PWRDN_N_STATUS___M 0x80000000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__RF_ADC1_PWRDN_N_STATUS___S 31 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__RF_ADC1_CLAMP_STATUS___M 0x40000000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__RF_ADC1_CLAMP_STATUS___S 30 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__MAC1_IDLE_STATUS___M 0x20000000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__MAC1_IDLE_STATUS___S 29 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__PHY1_IDLE_STATUS___M 0x10000000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__PHY1_IDLE_STATUS___S 28 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__REINIT_DONE_PRETEND___M 0x00004000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__REINIT_DONE_PRETEND___S 14 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__PHY1_IDLE_TIMEOUT_EN___M 0x00002000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__PHY1_IDLE_TIMEOUT_EN___S 13 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__MAC1_IDLE_TIMEOUT_EN___M 0x00001000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__MAC1_IDLE_TIMEOUT_EN___S 12 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__NEXT_WAKEUP_TIME_SW_OVR___M 0x00000800 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__NEXT_WAKEUP_TIME_SW_OVR___S 11 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__WLAN_ADC_DIGITAL_CLAMP___M 0x00000400 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__WLAN_ADC_DIGITAL_CLAMP___S 10 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__RFIF_ADC_PWRDN_N___M 0x00000200 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__RFIF_ADC_PWRDN_N___S 9 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_DOWN_PRETEND___M 0x00000100 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_DOWN_PRETEND___S 8 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_HALTREQ_TO_EN___M 0x00000080 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_HALTREQ_TO_EN___S 7 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_HALTREQ_OVRD___M 0x00000040 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_HALTREQ_OVRD___S 6 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_HALTREQ___M 0x00000020 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_HALTREQ___S 5 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_FORCE_ON___M 0x00000010 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_FORCE_ON___S 4 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_FORCE_IDLE___M 0x00000008 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_FORCE_IDLE___S 3 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_OFF___M 0x00000004 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__SW_WLAN1_OFF___S 2 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__WLAN1_REG_REINIT_IGNORE___M 0x00000002 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__WLAN1_REG_REINIT_IGNORE___S 1 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__WLAN1_CLKGATE_DISABLE___M 0x00000001 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1__WLAN1_CLKGATE_DISABLE___S 0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1___M 0xF0007FFF +#define WFSS_PMM_WFSS_PMM_R0_PMM_WLAN1_CFG_REG1___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_STATUS_REG2 (0x00B600D8) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_STATUS_REG2___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_STATUS_REG2___POR 0x00000001 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_STATUS_REG2__WLAN1_SLP_DELTA_VLD___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_STATUS_REG2__QGIC2_WLAN1_HALTREQ_TO___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_STATUS_REG2__WLAN1_SM___POR 0x0001 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_STATUS_REG2__WLAN1_SLP_DELTA_VLD___M 0x00020000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_STATUS_REG2__WLAN1_SLP_DELTA_VLD___S 17 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_STATUS_REG2__QGIC2_WLAN1_HALTREQ_TO___M 0x00010000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_STATUS_REG2__QGIC2_WLAN1_HALTREQ_TO___S 16 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_STATUS_REG2__WLAN1_SM___M 0x00007FFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_STATUS_REG2__WLAN1_SM___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_STATUS_REG2___M 0x00037FFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_STATUS_REG2___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_SLP_DELTA (0x00B600DC) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_SLP_DELTA___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_SLP_DELTA___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_SLP_DELTA__WLAN1_SLP_DELTA___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_SLP_DELTA__WLAN1_SLP_DELTA___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_SLP_DELTA__WLAN1_SLP_DELTA___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_SLP_DELTA___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_SLP_DELTA___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TSF_SNAPSHOT_LSB (0x00B600E0) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TSF_SNAPSHOT_LSB___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TSF_SNAPSHOT_LSB___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TSF_SNAPSHOT_LSB__WLAN1_TSF_SNAPSHOT_LSB___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TSF_SNAPSHOT_LSB__WLAN1_TSF_SNAPSHOT_LSB___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TSF_SNAPSHOT_LSB__WLAN1_TSF_SNAPSHOT_LSB___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TSF_SNAPSHOT_LSB___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TSF_SNAPSHOT_LSB___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TSF_SNAPSHOT_MSB (0x00B600E4) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TSF_SNAPSHOT_MSB___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TSF_SNAPSHOT_MSB___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TSF_SNAPSHOT_MSB__WLAN1_TSF_SNAPSHOT_MSB___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TSF_SNAPSHOT_MSB__WLAN1_TSF_SNAPSHOT_MSB___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TSF_SNAPSHOT_MSB__WLAN1_TSF_SNAPSHOT_MSB___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TSF_SNAPSHOT_MSB___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_TSF_SNAPSHOT_MSB___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_PMM_CFG (0x00B600E8) +#define WFSS_PMM_WFSS_PMM_R0_PMM_CFG___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_PMM_CFG___POR 0x0000000E +#define WFSS_PMM_WFSS_PMM_R0_PMM_CFG__PCIE_EXIT_L12_PWR_SAVE_MASK___POR 0x1 +#define WFSS_PMM_WFSS_PMM_R0_PMM_CFG__PCIE_ENTER_L12_PWR_SAVE_MASK___POR 0x1 +#define WFSS_PMM_WFSS_PMM_R0_PMM_CFG__PMM_FUNC_INTR_GLOBAL_MASK___POR 0x1 +#define WFSS_PMM_WFSS_PMM_R0_PMM_CFG__PCIE_PWR_SAVE_EN___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_CFG__PCIE_EXIT_L12_PWR_SAVE_MASK___M 0x00000008 +#define WFSS_PMM_WFSS_PMM_R0_PMM_CFG__PCIE_EXIT_L12_PWR_SAVE_MASK___S 3 +#define WFSS_PMM_WFSS_PMM_R0_PMM_CFG__PCIE_ENTER_L12_PWR_SAVE_MASK___M 0x00000004 +#define WFSS_PMM_WFSS_PMM_R0_PMM_CFG__PCIE_ENTER_L12_PWR_SAVE_MASK___S 2 +#define WFSS_PMM_WFSS_PMM_R0_PMM_CFG__PMM_FUNC_INTR_GLOBAL_MASK___M 0x00000002 +#define WFSS_PMM_WFSS_PMM_R0_PMM_CFG__PMM_FUNC_INTR_GLOBAL_MASK___S 1 +#define WFSS_PMM_WFSS_PMM_R0_PMM_CFG__PCIE_PWR_SAVE_EN___M 0x00000001 +#define WFSS_PMM_WFSS_PMM_R0_PMM_CFG__PCIE_PWR_SAVE_EN___S 0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_CFG___M 0x0000000F +#define WFSS_PMM_WFSS_PMM_R0_PMM_CFG___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_PMM_STATUS (0x00B600EC) +#define WFSS_PMM_WFSS_PMM_R0_PMM_STATUS___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_PMM_STATUS___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_STATUS__PCIE_EXIT_L12_PWR_SAVE_REQ_INT___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_STATUS__PCIE_ENTER_L12_PWR_SAVE_REQ_INT___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_STATUS__PCIE_EXIT_L12_PWR_SAVE_REQ_INT___M 0x00000002 +#define WFSS_PMM_WFSS_PMM_R0_PMM_STATUS__PCIE_EXIT_L12_PWR_SAVE_REQ_INT___S 1 +#define WFSS_PMM_WFSS_PMM_R0_PMM_STATUS__PCIE_ENTER_L12_PWR_SAVE_REQ_INT___M 0x00000001 +#define WFSS_PMM_WFSS_PMM_R0_PMM_STATUS__PCIE_ENTER_L12_PWR_SAVE_REQ_INT___S 0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_STATUS___M 0x00000003 +#define WFSS_PMM_WFSS_PMM_R0_PMM_STATUS___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IMITATE_MAC_SENT_PHY_OFF (0x00B600F0) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IMITATE_MAC_SENT_PHY_OFF___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IMITATE_MAC_SENT_PHY_OFF___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IMITATE_MAC_SENT_PHY_OFF__MSPO_SIMULATED_CUML_CTR___POR 0x0000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IMITATE_MAC_SENT_PHY_OFF__MSPO_CUML_CTR_VALUE_TO_INTR_FW___POR 0x00 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IMITATE_MAC_SENT_PHY_OFF__LAST_WAKEUP_HAD_MSPO_TO___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IMITATE_MAC_SENT_PHY_OFF__MAC_SENT_PHY_OFF_TO_CUML_CTR___POR 0x00 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IMITATE_MAC_SENT_PHY_OFF__MSPO_SIMULATED_CUML_CTR___M 0xFFFE0000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IMITATE_MAC_SENT_PHY_OFF__MSPO_SIMULATED_CUML_CTR___S 17 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IMITATE_MAC_SENT_PHY_OFF__MSPO_CUML_CTR_VALUE_TO_INTR_FW___M 0x0001FE00 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IMITATE_MAC_SENT_PHY_OFF__MSPO_CUML_CTR_VALUE_TO_INTR_FW___S 9 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IMITATE_MAC_SENT_PHY_OFF__LAST_WAKEUP_HAD_MSPO_TO___M 0x00000100 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IMITATE_MAC_SENT_PHY_OFF__LAST_WAKEUP_HAD_MSPO_TO___S 8 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IMITATE_MAC_SENT_PHY_OFF__MAC_SENT_PHY_OFF_TO_CUML_CTR___M 0x000000FF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IMITATE_MAC_SENT_PHY_OFF__MAC_SENT_PHY_OFF_TO_CUML_CTR___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IMITATE_MAC_SENT_PHY_OFF___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_IMITATE_MAC_SENT_PHY_OFF___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_DTIM_INTERVAL (0x00B600F4) +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_DTIM_INTERVAL___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_DTIM_INTERVAL___POR 0x00019000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_DTIM_INTERVAL__SUBS_MSPO_TO_AS_MSPO___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_DTIM_INTERVAL__VALUE___POR 0x019000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_DTIM_INTERVAL__SUBS_MSPO_TO_AS_MSPO___M 0x01000000 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_DTIM_INTERVAL__SUBS_MSPO_TO_AS_MSPO___S 24 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_DTIM_INTERVAL__VALUE___M 0x00FFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_DTIM_INTERVAL__VALUE___S 0 +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_DTIM_INTERVAL___M 0x01FFFFFF +#define WFSS_PMM_WFSS_PMM_R0_WLAN1_DTIM_INTERVAL___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_0 (0x00B600F8) +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_0___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_0___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_0__SPARE_REG___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_0__SPARE_REG___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_0__SPARE_REG___S 0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_0___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_0___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_1 (0x00B600FC) +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_1___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_1___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_1__SPARE_REG___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_1__SPARE_REG___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_1__SPARE_REG___S 0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_1___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_1___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_2 (0x00B60100) +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_2___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_2___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_2__SPARE_REG___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_2__SPARE_REG___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_2__SPARE_REG___S 0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_2___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_2___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_3 (0x00B60104) +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_3___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_3___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_3__SPARE_REG___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_3__SPARE_REG___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_3__SPARE_REG___S 0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_3___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_3___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_4 (0x00B60108) +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_4___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_4___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_4__SPARE_REG___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_4__SPARE_REG___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_4__SPARE_REG___S 0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_4___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_4___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_5 (0x00B6010C) +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_5___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_5___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_5__SPARE_REG___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_5__SPARE_REG___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_5__SPARE_REG___S 0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_5___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_5___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_6 (0x00B60110) +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_6___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_6___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_6__SPARE_REG___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_6__SPARE_REG___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_6__SPARE_REG___S 0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_6___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_6___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_7 (0x00B60114) +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_7___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_7___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_7__SPARE_REG___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_7__SPARE_REG___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_7__SPARE_REG___S 0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_7___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_7___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_8 (0x00B60118) +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_8___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_8___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_8__SPARE_REG___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_8__SPARE_REG___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_8__SPARE_REG___S 0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_8___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_8___S 0 + +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_9 (0x00B6011C) +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_9___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_9___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_9__SPARE_REG___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_9__SPARE_REG___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_9__SPARE_REG___S 0 +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_9___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R0_PMM_SW_META_S_PARE_IX_9___S 0 + +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_NAP_OP_DURATION_HISTORY_0 (0x00B62000) +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_NAP_OP_DURATION_HISTORY_0___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_NAP_OP_DURATION_HISTORY_0___POR 0xDEADC0DE +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_NAP_OP_DURATION_HISTORY_0__VALUE___POR 0xDEADC0DE +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_NAP_OP_DURATION_HISTORY_0__VALUE___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_NAP_OP_DURATION_HISTORY_0__VALUE___S 0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_NAP_OP_DURATION_HISTORY_0___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_NAP_OP_DURATION_HISTORY_0___S 0 + +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_NAP_OP_DURATION_HISTORY_1 (0x00B62004) +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_NAP_OP_DURATION_HISTORY_1___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_NAP_OP_DURATION_HISTORY_1___POR 0xDEADC0DE +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_NAP_OP_DURATION_HISTORY_1__VALUE___POR 0xDEADC0DE +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_NAP_OP_DURATION_HISTORY_1__VALUE___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_NAP_OP_DURATION_HISTORY_1__VALUE___S 0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_NAP_OP_DURATION_HISTORY_1___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_NAP_OP_DURATION_HISTORY_1___S 0 + +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_COEX_NAP_OP_DURATION_HISTORY_0 (0x00B62008) +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_COEX_NAP_OP_DURATION_HISTORY_0___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_COEX_NAP_OP_DURATION_HISTORY_0___POR 0xDEADC0DE +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_COEX_NAP_OP_DURATION_HISTORY_0__VALUE___POR 0xDEADC0DE +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_COEX_NAP_OP_DURATION_HISTORY_0__VALUE___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_COEX_NAP_OP_DURATION_HISTORY_0__VALUE___S 0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_COEX_NAP_OP_DURATION_HISTORY_0___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_COEX_NAP_OP_DURATION_HISTORY_0___S 0 + +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_COEX_NAP_OP_DURATION_HISTORY_1 (0x00B6200C) +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_COEX_NAP_OP_DURATION_HISTORY_1___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_COEX_NAP_OP_DURATION_HISTORY_1___POR 0xDEADC0DE +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_COEX_NAP_OP_DURATION_HISTORY_1__VALUE___POR 0xDEADC0DE +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_COEX_NAP_OP_DURATION_HISTORY_1__VALUE___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_COEX_NAP_OP_DURATION_HISTORY_1__VALUE___S 0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_COEX_NAP_OP_DURATION_HISTORY_1___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_COEX_NAP_OP_DURATION_HISTORY_1___S 0 + +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_FROM_MAC_L (0x00B62010) +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_FROM_MAC_L___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_FROM_MAC_L___POR 0xDEADC0DE +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_FROM_MAC_L__VALUE___POR 0xDEADC0DE +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_FROM_MAC_L__VALUE___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_FROM_MAC_L__VALUE___S 0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_FROM_MAC_L___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_FROM_MAC_L___S 0 + +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_FROM_MAC_H (0x00B62014) +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_FROM_MAC_H___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_FROM_MAC_H___POR 0xDEADC0DE +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_FROM_MAC_H__VALUE___POR 0xDEADC0DE +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_FROM_MAC_H__VALUE___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_FROM_MAC_H__VALUE___S 0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_FROM_MAC_H___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_FROM_MAC_H___S 0 + +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_TO_AON_L (0x00B62018) +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_TO_AON_L___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_TO_AON_L___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_TO_AON_L__VALUE___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_TO_AON_L__VALUE___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_TO_AON_L__VALUE___S 0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_TO_AON_L___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_TO_AON_L___S 0 + +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_TO_AON_H (0x00B6201C) +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_TO_AON_H___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_TO_AON_H___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_TO_AON_H__VALUE___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_TO_AON_H__VALUE___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_TO_AON_H__VALUE___S 0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_TO_AON_H___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_NEXT_WAKEUP_TIME_TO_AON_H___S 0 + +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1 (0x00B62020) +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1___POR 0x00000020 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__WLAN_REST_ACK___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__PMM_UPDATED_MAC_TIMER___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__COEX_INIT_DONE___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__PHY_INIT_DONE___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__WMAC_CLK_ON___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__SS_UP_ACK___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__H2S_GRANT_ISSUED___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__AON_TIMER_HAS_EXPIRED___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__PHY_TO_AS_IDLE___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__MAC_TO_AS_IDLE___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__RRI_DONE___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__DYN_MIMO_PS_ACTIVE___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__SKT_DISCACK___POR 0x1 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__PHY_TRACER_IDLE___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__MAC_TRACER_IDLE___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__DIRECT_SYNTH_ON___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__DTIM_PHY_OFF_SENT___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__APS_PHY_OFF_SENT___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__WLAN_REST_ACK___M 0x00020000 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__WLAN_REST_ACK___S 17 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__PMM_UPDATED_MAC_TIMER___M 0x00010000 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__PMM_UPDATED_MAC_TIMER___S 16 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__COEX_INIT_DONE___M 0x00008000 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__COEX_INIT_DONE___S 15 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__PHY_INIT_DONE___M 0x00004000 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__PHY_INIT_DONE___S 14 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__WMAC_CLK_ON___M 0x00002000 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__WMAC_CLK_ON___S 13 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__SS_UP_ACK___M 0x00001000 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__SS_UP_ACK___S 12 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__H2S_GRANT_ISSUED___M 0x00000800 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__H2S_GRANT_ISSUED___S 11 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__AON_TIMER_HAS_EXPIRED___M 0x00000400 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__AON_TIMER_HAS_EXPIRED___S 10 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__PHY_TO_AS_IDLE___M 0x00000200 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__PHY_TO_AS_IDLE___S 9 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__MAC_TO_AS_IDLE___M 0x00000100 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__MAC_TO_AS_IDLE___S 8 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__RRI_DONE___M 0x00000080 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__RRI_DONE___S 7 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__DYN_MIMO_PS_ACTIVE___M 0x00000040 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__DYN_MIMO_PS_ACTIVE___S 6 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__SKT_DISCACK___M 0x00000020 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__SKT_DISCACK___S 5 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__PHY_TRACER_IDLE___M 0x00000010 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__PHY_TRACER_IDLE___S 4 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__MAC_TRACER_IDLE___M 0x00000008 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__MAC_TRACER_IDLE___S 3 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__DIRECT_SYNTH_ON___M 0x00000004 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__DIRECT_SYNTH_ON___S 2 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__DTIM_PHY_OFF_SENT___M 0x00000002 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__DTIM_PHY_OFF_SENT___S 1 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__APS_PHY_OFF_SENT___M 0x00000001 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1__APS_PHY_OFF_SENT___S 0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1___M 0x0003FFFF +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_STATUS_REG1___S 0 + +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_DISABLE_TRANSITION_DBG_CFG1 (0x00B62024) +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_DISABLE_TRANSITION_DBG_CFG1___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_DISABLE_TRANSITION_DBG_CFG1___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_DISABLE_TRANSITION_DBG_CFG1__DISABLE_TRANSITION_ARC___POR 0x000000 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_DISABLE_TRANSITION_DBG_CFG1__DISABLE_TRANSITION_ARC___M 0x00FFFFFF +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_DISABLE_TRANSITION_DBG_CFG1__DISABLE_TRANSITION_ARC___S 0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_DISABLE_TRANSITION_DBG_CFG1___M 0x00FFFFFF +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_DISABLE_TRANSITION_DBG_CFG1___S 0 + +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_DISABLE_TRANSITION_DBG_CFG2 (0x00B62028) +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_DISABLE_TRANSITION_DBG_CFG2___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_DISABLE_TRANSITION_DBG_CFG2___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_DISABLE_TRANSITION_DBG_CFG2__DISABLE_TRANSITION_ARC___POR 0x00 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_DISABLE_TRANSITION_DBG_CFG2__DISABLE_TRANSITION_ARC___M 0x000000FF +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_DISABLE_TRANSITION_DBG_CFG2__DISABLE_TRANSITION_ARC___S 0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_DISABLE_TRANSITION_DBG_CFG2___M 0x000000FF +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_APS_DISABLE_TRANSITION_DBG_CFG2___S 0 + +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL (0x00B6202C) +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_OFF_ENR_ACK___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_ON_ENR_ACK___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_OFF_ENF_ACK___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_ON_ENF_ACK___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_OFF_ENR___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_ON_ENR___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_OFF_ENF___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_ON_ENF___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_OFF_ENR_ACK___M 0x00000080 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_OFF_ENR_ACK___S 7 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_ON_ENR_ACK___M 0x00000040 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_ON_ENR_ACK___S 6 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_OFF_ENF_ACK___M 0x00000020 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_OFF_ENF_ACK___S 5 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_ON_ENF_ACK___M 0x00000010 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_ON_ENF_ACK___S 4 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_OFF_ENR___M 0x00000008 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_OFF_ENR___S 3 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_ON_ENR___M 0x00000004 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_ON_ENR___S 2 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_OFF_ENF___M 0x00000002 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_OFF_ENF___S 1 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_ON_ENF___M 0x00000001 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL__FORCE_ON_ENF___S 0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL___M 0x000000FF +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_POWER_SWITCH_CTL___S 0 + +#define WFSS_PMM_WFSS_PMM_R2_GLOTIM_US_TIMER_L (0x00B62030) +#define WFSS_PMM_WFSS_PMM_R2_GLOTIM_US_TIMER_L___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R2_GLOTIM_US_TIMER_L___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R2_GLOTIM_US_TIMER_L__VALUE___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R2_GLOTIM_US_TIMER_L__VALUE___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R2_GLOTIM_US_TIMER_L__VALUE___S 0 +#define WFSS_PMM_WFSS_PMM_R2_GLOTIM_US_TIMER_L___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R2_GLOTIM_US_TIMER_L___S 0 + +#define WFSS_PMM_WFSS_PMM_R2_GLOTIM_US_TIMER_H (0x00B62034) +#define WFSS_PMM_WFSS_PMM_R2_GLOTIM_US_TIMER_H___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R2_GLOTIM_US_TIMER_H___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R2_GLOTIM_US_TIMER_H__VALUE___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R2_GLOTIM_US_TIMER_H__VALUE___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R2_GLOTIM_US_TIMER_H__VALUE___S 0 +#define WFSS_PMM_WFSS_PMM_R2_GLOTIM_US_TIMER_H___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R2_GLOTIM_US_TIMER_H___S 0 + +#define WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL (0x00B62038) +#define WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_OFF_ENR_ACK___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_ON_ENR_ACK___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_OFF_ENF_ACK___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_ON_ENF_ACK___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_OFF_ENR___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_ON_ENR___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_OFF_ENF___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_ON_ENF___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_OFF_ENR_ACK___M 0x00000080 +#define WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_OFF_ENR_ACK___S 7 +#define WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_ON_ENR_ACK___M 0x00000040 +#define WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_ON_ENR_ACK___S 6 +#define WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_OFF_ENF_ACK___M 0x00000020 +#define WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_OFF_ENF_ACK___S 5 +#define WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_ON_ENF_ACK___M 0x00000010 +#define WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_ON_ENF_ACK___S 4 +#define WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_OFF_ENR___M 0x00000008 +#define WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_OFF_ENR___S 3 +#define WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_ON_ENR___M 0x00000004 +#define WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_ON_ENR___S 2 +#define WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_OFF_ENF___M 0x00000002 +#define WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_OFF_ENF___S 1 +#define WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_ON_ENF___M 0x00000001 +#define WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL__FORCE_ON_ENF___S 0 +#define WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL___M 0x000000FF +#define WFSS_PMM_WFSS_PMM_R2_CSS_POWER_SWITCH_CTL___S 0 + +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR (0x00B6203C) +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__MAX_SIMULATED_MSPO_CNT_MET___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__PWR_SEQ_ERR___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__NEXT_WAKEUP_TIME_COMPUTE_UNDERFLOW___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__DELTA_COMPUTE_UNDERFLOW___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__PO_PSO_ACK_TO___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__APS_WDOG_TO___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__WLAN_WDOG_TO___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__SW_PHY_OFF_ISSUE_ERR___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__ILLEGAL_ARRIVAL_ENTER_LS_S___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__ILLEGAL_ARRIVAL_ENTER_LS_H___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__LATE_ARRIVAL_ENTER_LS_H___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__WAKEUP_INT_2_POS_TO___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__SW_WR_HW_CLR_COLLIDE___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__MAX_SIMULATED_MSPO_CNT_MET___M 0x00001000 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__MAX_SIMULATED_MSPO_CNT_MET___S 12 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__PWR_SEQ_ERR___M 0x00000800 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__PWR_SEQ_ERR___S 11 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__NEXT_WAKEUP_TIME_COMPUTE_UNDERFLOW___M 0x00000400 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__NEXT_WAKEUP_TIME_COMPUTE_UNDERFLOW___S 10 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__DELTA_COMPUTE_UNDERFLOW___M 0x00000200 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__DELTA_COMPUTE_UNDERFLOW___S 9 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__PO_PSO_ACK_TO___M 0x00000100 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__PO_PSO_ACK_TO___S 8 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__APS_WDOG_TO___M 0x00000080 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__APS_WDOG_TO___S 7 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__WLAN_WDOG_TO___M 0x00000040 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__WLAN_WDOG_TO___S 6 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__SW_PHY_OFF_ISSUE_ERR___M 0x00000020 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__SW_PHY_OFF_ISSUE_ERR___S 5 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__ILLEGAL_ARRIVAL_ENTER_LS_S___M 0x00000010 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__ILLEGAL_ARRIVAL_ENTER_LS_S___S 4 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__ILLEGAL_ARRIVAL_ENTER_LS_H___M 0x00000008 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__ILLEGAL_ARRIVAL_ENTER_LS_H___S 3 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__LATE_ARRIVAL_ENTER_LS_H___M 0x00000004 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__LATE_ARRIVAL_ENTER_LS_H___S 2 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__WAKEUP_INT_2_POS_TO___M 0x00000002 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__WAKEUP_INT_2_POS_TO___S 1 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__SW_WR_HW_CLR_COLLIDE___M 0x00000001 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR__SW_WR_HW_CLR_COLLIDE___S 0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR___M 0x00001FFF +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR___S 0 + +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PWR_REQ_HIS_L (0x00B62040) +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PWR_REQ_HIS_L___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PWR_REQ_HIS_L___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PWR_REQ_HIS_L__VALUE___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PWR_REQ_HIS_L__VALUE___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PWR_REQ_HIS_L__VALUE___S 0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PWR_REQ_HIS_L___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PWR_REQ_HIS_L___S 0 + +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PWR_REQ_HIS_H (0x00B62044) +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PWR_REQ_HIS_H___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PWR_REQ_HIS_H___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PWR_REQ_HIS_H__VALUE___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PWR_REQ_HIS_H__VALUE___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PWR_REQ_HIS_H__VALUE___S 0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PWR_REQ_HIS_H___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PWR_REQ_HIS_H___S 0 + +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR_MASK (0x00B62048) +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR_MASK___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR_MASK___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR_MASK__VALUE___POR 0x0000 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR_MASK__VALUE___M 0x00001FFF +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR_MASK__VALUE___S 0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR_MASK___M 0x00001FFF +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR_MASK___S 0 + +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR_GLOBAL_MASK (0x00B6204C) +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR_GLOBAL_MASK___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR_GLOBAL_MASK___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR_GLOBAL_MASK__VALUE___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR_GLOBAL_MASK__VALUE___M 0x00000001 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR_GLOBAL_MASK__VALUE___S 0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR_GLOBAL_MASK___M 0x00000001 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_ERROR_GLOBAL_MASK___S 0 + +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT (0x00B62050) +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__DS_MAC_WAKE_PO_TO___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__FCS_PHY_OFF_ACK_TO___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__SW_PHY_SYNTH_OFF_ACK_TO___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__HW_PHY_SYNTH_OFF_ACK_TO___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__SW_PHY_OFF_ACK_TO___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__HW_PHY_OFF_ACK_TO___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__DS_MAC_WAKE_PO_TO___M 0x00000020 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__DS_MAC_WAKE_PO_TO___S 5 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__FCS_PHY_OFF_ACK_TO___M 0x00000010 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__FCS_PHY_OFF_ACK_TO___S 4 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__SW_PHY_SYNTH_OFF_ACK_TO___M 0x00000008 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__SW_PHY_SYNTH_OFF_ACK_TO___S 3 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__HW_PHY_SYNTH_OFF_ACK_TO___M 0x00000004 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__HW_PHY_SYNTH_OFF_ACK_TO___S 2 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__SW_PHY_OFF_ACK_TO___M 0x00000002 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__SW_PHY_OFF_ACK_TO___S 1 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__HW_PHY_OFF_ACK_TO___M 0x00000001 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT__HW_PHY_OFF_ACK_TO___S 0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT___M 0x0000003F +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PO_PSO_TIMEOUT___S 0 + +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS (0x00B62054) +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__DS_FSM_PHY_OFF_SENT_RECD___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__DS_FSM_IN_MAC_WAKE_STATE___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FCS_PHY_OFF_SENT_ACK___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FCS_PHY_OFF_SENT___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__SW_OVR_PHY_SYNTH_OFF_SENT_ACK___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__SW_OVR_PHY_SYNTH_OFF_SENT___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FSM_PHY_SYNTH_OFF_SENT_ACK___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FSM_PHY_SYNTH_OFF_SENT___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__SW_OVR_PHY_OFF_SENT_ACK___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__SW_OVR_PHY_OFF_SENT___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FSM_PHY_OFF_SENT_ACK___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FSM_PHY_OFF_SENT___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__DS_FSM_PHY_OFF_SENT_RECD___M 0x00000800 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__DS_FSM_PHY_OFF_SENT_RECD___S 11 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__DS_FSM_IN_MAC_WAKE_STATE___M 0x00000400 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__DS_FSM_IN_MAC_WAKE_STATE___S 10 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FCS_PHY_OFF_SENT_ACK___M 0x00000200 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FCS_PHY_OFF_SENT_ACK___S 9 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FCS_PHY_OFF_SENT___M 0x00000100 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FCS_PHY_OFF_SENT___S 8 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__SW_OVR_PHY_SYNTH_OFF_SENT_ACK___M 0x00000080 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__SW_OVR_PHY_SYNTH_OFF_SENT_ACK___S 7 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__SW_OVR_PHY_SYNTH_OFF_SENT___M 0x00000040 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__SW_OVR_PHY_SYNTH_OFF_SENT___S 6 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FSM_PHY_SYNTH_OFF_SENT_ACK___M 0x00000020 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FSM_PHY_SYNTH_OFF_SENT_ACK___S 5 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FSM_PHY_SYNTH_OFF_SENT___M 0x00000010 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FSM_PHY_SYNTH_OFF_SENT___S 4 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__SW_OVR_PHY_OFF_SENT_ACK___M 0x00000008 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__SW_OVR_PHY_OFF_SENT_ACK___S 3 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__SW_OVR_PHY_OFF_SENT___M 0x00000004 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__SW_OVR_PHY_OFF_SENT___S 2 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FSM_PHY_OFF_SENT_ACK___M 0x00000002 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FSM_PHY_OFF_SENT_ACK___S 1 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FSM_PHY_OFF_SENT___M 0x00000001 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS__APS_FSM_PHY_OFF_SENT___S 0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS___M 0x00000FFF +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_PMM_LMAC_HANDSHAKE_STATUS___S 0 + +#define WFSS_PMM_WFSS_PMM_R2_DEBUG_CONTROL (0x00B62058) +#define WFSS_PMM_WFSS_PMM_R2_DEBUG_CONTROL___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R2_DEBUG_CONTROL___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R2_DEBUG_CONTROL__APS_CUML_CTR_EN___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_DEBUG_CONTROL__PWR_N_EVENTBUS_CLK_EN___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_DEBUG_CONTROL__DEBUG_HWSW_INTF_CLK_EN___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_DEBUG_CONTROL__APS_CUML_CTR_EN___M 0x00000004 +#define WFSS_PMM_WFSS_PMM_R2_DEBUG_CONTROL__APS_CUML_CTR_EN___S 2 +#define WFSS_PMM_WFSS_PMM_R2_DEBUG_CONTROL__PWR_N_EVENTBUS_CLK_EN___M 0x00000002 +#define WFSS_PMM_WFSS_PMM_R2_DEBUG_CONTROL__PWR_N_EVENTBUS_CLK_EN___S 1 +#define WFSS_PMM_WFSS_PMM_R2_DEBUG_CONTROL__DEBUG_HWSW_INTF_CLK_EN___M 0x00000001 +#define WFSS_PMM_WFSS_PMM_R2_DEBUG_CONTROL__DEBUG_HWSW_INTF_CLK_EN___S 0 +#define WFSS_PMM_WFSS_PMM_R2_DEBUG_CONTROL___M 0x00000007 +#define WFSS_PMM_WFSS_PMM_R2_DEBUG_CONTROL___S 0 + +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IGNORE_IDLE_ACK_RESP (0x00B6205C) +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IGNORE_IDLE_ACK_RESP___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IGNORE_IDLE_ACK_RESP___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IGNORE_IDLE_ACK_RESP__PHY1_IGNORE_IDLE_RESP___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IGNORE_IDLE_ACK_RESP__PHY1_IGNORE_IDLE_REQ_ACK___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IGNORE_IDLE_ACK_RESP__MAC1_IGNORE_IDLE_RESP___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IGNORE_IDLE_ACK_RESP__MAC1_IGNORE_IDLE_REQ_ACK___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IGNORE_IDLE_ACK_RESP__PHY1_IGNORE_IDLE_RESP___M 0x00000008 +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IGNORE_IDLE_ACK_RESP__PHY1_IGNORE_IDLE_RESP___S 3 +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IGNORE_IDLE_ACK_RESP__PHY1_IGNORE_IDLE_REQ_ACK___M 0x00000004 +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IGNORE_IDLE_ACK_RESP__PHY1_IGNORE_IDLE_REQ_ACK___S 2 +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IGNORE_IDLE_ACK_RESP__MAC1_IGNORE_IDLE_RESP___M 0x00000002 +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IGNORE_IDLE_ACK_RESP__MAC1_IGNORE_IDLE_RESP___S 1 +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IGNORE_IDLE_ACK_RESP__MAC1_IGNORE_IDLE_REQ_ACK___M 0x00000001 +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IGNORE_IDLE_ACK_RESP__MAC1_IGNORE_IDLE_REQ_ACK___S 0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IGNORE_IDLE_ACK_RESP___M 0x0000000F +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IGNORE_IDLE_ACK_RESP___S 0 + +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS (0x00B62060) +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__PHY1_IDLE_RESP___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__PHY1_IDLE_REQ_ACK___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__PHY1_IDLE_REQ___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__MAC1_IDLE_RESP___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__MAC1_IDLE_REQ_ACK___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__MAC1_IDLE_REQ___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__PHY1_IDLE_RESP___M 0x00000020 +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__PHY1_IDLE_RESP___S 5 +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__PHY1_IDLE_REQ_ACK___M 0x00000010 +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__PHY1_IDLE_REQ_ACK___S 4 +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__PHY1_IDLE_REQ___M 0x00000008 +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__PHY1_IDLE_REQ___S 3 +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__MAC1_IDLE_RESP___M 0x00000004 +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__MAC1_IDLE_RESP___S 2 +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__MAC1_IDLE_REQ_ACK___M 0x00000002 +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__MAC1_IDLE_REQ_ACK___S 1 +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__MAC1_IDLE_REQ___M 0x00000001 +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS__MAC1_IDLE_REQ___S 0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS___M 0x0000003F +#define WFSS_PMM_WFSS_PMM_R2_WLAN_IDLE_REQ_ACK_RESP_STATUS___S 0 + +#define WFSS_PMM_WFSS_PMM_R2_EVENT_BUS_MUX_SELECT (0x00B62064) +#define WFSS_PMM_WFSS_PMM_R2_EVENT_BUS_MUX_SELECT___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R2_EVENT_BUS_MUX_SELECT___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R2_EVENT_BUS_MUX_SELECT__WLAN_SEL___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_EVENT_BUS_MUX_SELECT__WLAN1_SEL___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_EVENT_BUS_MUX_SELECT__WLAN_SEL___M 0x00000100 +#define WFSS_PMM_WFSS_PMM_R2_EVENT_BUS_MUX_SELECT__WLAN_SEL___S 8 +#define WFSS_PMM_WFSS_PMM_R2_EVENT_BUS_MUX_SELECT__WLAN1_SEL___M 0x0000000F +#define WFSS_PMM_WFSS_PMM_R2_EVENT_BUS_MUX_SELECT__WLAN1_SEL___S 0 +#define WFSS_PMM_WFSS_PMM_R2_EVENT_BUS_MUX_SELECT___M 0x0000010F +#define WFSS_PMM_WFSS_PMM_R2_EVENT_BUS_MUX_SELECT___S 0 + +#define WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1 (0x00B62068) +#define WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1__S_PARE_01___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1__HONOR_ON_OFF_DLY_IN_APS_FIFO_DISABLE1___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1__AONGTIM_SYNC_DCG_DISABLE___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1__S_PARE_00___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1__WLAN1_H2S_DCG_DISABLE___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1__S_PARE_01___M 0x00000010 +#define WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1__S_PARE_01___S 4 +#define WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1__HONOR_ON_OFF_DLY_IN_APS_FIFO_DISABLE1___M 0x00000008 +#define WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1__HONOR_ON_OFF_DLY_IN_APS_FIFO_DISABLE1___S 3 +#define WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1__AONGTIM_SYNC_DCG_DISABLE___M 0x00000004 +#define WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1__AONGTIM_SYNC_DCG_DISABLE___S 2 +#define WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1__S_PARE_00___M 0x00000002 +#define WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1__S_PARE_00___S 1 +#define WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1__WLAN1_H2S_DCG_DISABLE___M 0x00000001 +#define WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1__WLAN1_H2S_DCG_DISABLE___S 0 +#define WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1___M 0x0000001F +#define WFSS_PMM_WFSS_PMM_R2_PMM_CONTROL_1___S 0 + +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_COEX_REG1 (0x00B6206C) +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_COEX_REG1___RWC QCSR_REG_RO +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_COEX_REG1___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_COEX_REG1__COEX_SLEEP_ACK_ERR___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_COEX_REG1__COEX_SLEEP_ACK_RESULT___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_COEX_REG1__COEX_INIT_RESULT___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_COEX_REG1__COEX_INIT_DONE___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_COEX_REG1__COEX_SLEEP_ACK_ERR___M 0x00000080 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_COEX_REG1__COEX_SLEEP_ACK_ERR___S 7 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_COEX_REG1__COEX_SLEEP_ACK_RESULT___M 0x00000070 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_COEX_REG1__COEX_SLEEP_ACK_RESULT___S 4 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_COEX_REG1__COEX_INIT_RESULT___M 0x0000000E +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_COEX_REG1__COEX_INIT_RESULT___S 1 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_COEX_REG1__COEX_INIT_DONE___M 0x00000001 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_COEX_REG1__COEX_INIT_DONE___S 0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_COEX_REG1___M 0x000000FF +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_COEX_REG1___S 0 + +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2 (0x00B62070) +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_RRI_SAVE_DLY___POR 0x0000 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__SW_WMAC1_WAKE___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__SW_WMAC1_WAKE_EN___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__SW_WLAN1_WAIT_FOR_RESTORE___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_RRI_RESTORE_EN___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_RRI_SAVE_EN___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_SW_DTIM___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_SLEEP_ANNOUNCEMENT_EN___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_COEX_INIT_ERR_IGNORE___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_COEX_INIT_CHECK_EN___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_PWRDN_IGNORE___POR 0x0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_RRI_SAVE_DLY___M 0x03FFFC00 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_RRI_SAVE_DLY___S 10 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__SW_WMAC1_WAKE___M 0x00000200 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__SW_WMAC1_WAKE___S 9 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__SW_WMAC1_WAKE_EN___M 0x00000100 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__SW_WMAC1_WAKE_EN___S 8 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__SW_WLAN1_WAIT_FOR_RESTORE___M 0x00000080 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__SW_WLAN1_WAIT_FOR_RESTORE___S 7 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_RRI_RESTORE_EN___M 0x00000040 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_RRI_RESTORE_EN___S 6 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_RRI_SAVE_EN___M 0x00000020 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_RRI_SAVE_EN___S 5 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_SW_DTIM___M 0x00000010 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_SW_DTIM___S 4 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_SLEEP_ANNOUNCEMENT_EN___M 0x00000008 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_SLEEP_ANNOUNCEMENT_EN___S 3 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_COEX_INIT_ERR_IGNORE___M 0x00000004 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_COEX_INIT_ERR_IGNORE___S 2 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_COEX_INIT_CHECK_EN___M 0x00000002 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_COEX_INIT_CHECK_EN___S 1 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_PWRDN_IGNORE___M 0x00000001 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2__WLAN1_PWRDN_IGNORE___S 0 +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2___M 0x03FFFFFF +#define WFSS_PMM_WFSS_PMM_R2_WLAN1_CFG_REG2___S 0 + +#define WFSS_PMM_WFSS_PMM_R2_PMM_TRC_EVENTMASK_IX_0 (0x00B62074) +#define WFSS_PMM_WFSS_PMM_R2_PMM_TRC_EVENTMASK_IX_0___RWC QCSR_REG_RW +#define WFSS_PMM_WFSS_PMM_R2_PMM_TRC_EVENTMASK_IX_0___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R2_PMM_TRC_EVENTMASK_IX_0__EVENT_MASK___POR 0x00000000 +#define WFSS_PMM_WFSS_PMM_R2_PMM_TRC_EVENTMASK_IX_0__EVENT_MASK___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R2_PMM_TRC_EVENTMASK_IX_0__EVENT_MASK___S 0 +#define WFSS_PMM_WFSS_PMM_R2_PMM_TRC_EVENTMASK_IX_0___M 0xFFFFFFFF +#define WFSS_PMM_WFSS_PMM_R2_PMM_TRC_EVENTMASK_IX_0___S 0 + + +#define PMM_TOP_BASE (0x00B70000) + +#define PMM_TOP_HW_VERSION (0x00B70000) +#define PMM_TOP_HW_VERSION___RWC QCSR_REG_RO +#define PMM_TOP_HW_VERSION___POR 0x50080000 +#define PMM_TOP_HW_VERSION__MAJOR___POR 0x5 +#define PMM_TOP_HW_VERSION__MINOR___POR 0x008 +#define PMM_TOP_HW_VERSION__STEP___POR 0x0000 +#define PMM_TOP_HW_VERSION__MAJOR___M 0xF0000000 +#define PMM_TOP_HW_VERSION__MAJOR___S 28 +#define PMM_TOP_HW_VERSION__MINOR___M 0x0FFF0000 +#define PMM_TOP_HW_VERSION__MINOR___S 16 +#define PMM_TOP_HW_VERSION__STEP___M 0x0000FFFF +#define PMM_TOP_HW_VERSION__STEP___S 0 +#define PMM_TOP_HW_VERSION___M 0xFFFFFFFF +#define PMM_TOP_HW_VERSION___S 0 + +#define PMM_TOP_WCSS_HM_VERSION (0x00B70004) +#define PMM_TOP_WCSS_HM_VERSION___RWC QCSR_REG_RO +#define PMM_TOP_WCSS_HM_VERSION___POR 0x00000000 +#define PMM_TOP_WCSS_HM_VERSION__WCSS_HM_VERSION___POR 0x00000000 +#define PMM_TOP_WCSS_HM_VERSION__WCSS_HM_VERSION___M 0xFFFFFFFF +#define PMM_TOP_WCSS_HM_VERSION__WCSS_HM_VERSION___S 0 +#define PMM_TOP_WCSS_HM_VERSION___M 0xFFFFFFFF +#define PMM_TOP_WCSS_HM_VERSION___S 0 + +#define PMM_TOP_PMM_TOP_VERSION (0x00B70008) +#define PMM_TOP_PMM_TOP_VERSION___RWC QCSR_REG_RO +#define PMM_TOP_PMM_TOP_VERSION___POR 0x00000000 +#define PMM_TOP_PMM_TOP_VERSION__PMM_TOP_VERSION___POR 0x00000000 +#define PMM_TOP_PMM_TOP_VERSION__PMM_TOP_VERSION___M 0xFFFFFFFF +#define PMM_TOP_PMM_TOP_VERSION__PMM_TOP_VERSION___S 0 +#define PMM_TOP_PMM_TOP_VERSION___M 0xFFFFFFFF +#define PMM_TOP_PMM_TOP_VERSION___S 0 + +#define PMM_TOP_CFG (0x00B7000C) +#define PMM_TOP_CFG___RWC QCSR_REG_RW +#define PMM_TOP_CFG___POR 0x00000000 +#define PMM_TOP_CFG__WCSS_LPI_MODE___POR 0x0 +#define PMM_TOP_CFG__RF_XO_MODE___POR 0x0 +#define PMM_TOP_CFG__WARM_BOOT___POR 0x0 +#define PMM_TOP_CFG__WCSS_LPI_MODE___M 0x00000008 +#define PMM_TOP_CFG__WCSS_LPI_MODE___S 3 +#define PMM_TOP_CFG__RF_XO_MODE___M 0x00000006 +#define PMM_TOP_CFG__RF_XO_MODE___S 1 +#define PMM_TOP_CFG__WARM_BOOT___M 0x00000001 +#define PMM_TOP_CFG__WARM_BOOT___S 0 +#define PMM_TOP_CFG___M 0x0000000F +#define PMM_TOP_CFG___S 0 + +#define PMM_TOP_ROOT_CLK_ENABLE (0x00B70010) +#define PMM_TOP_ROOT_CLK_ENABLE___RWC QCSR_REG_RW +#define PMM_TOP_ROOT_CLK_ENABLE___POR 0x00006610 +#define PMM_TOP_ROOT_CLK_ENABLE__AON_DBG_LPO_ROOT_CLK_ENABLE___POR 0x1 +#define PMM_TOP_ROOT_CLK_ENABLE__PMM_TCXO_CLK_ENABLE___POR 0x1 +#define PMM_TOP_ROOT_CLK_ENABLE__PMM_SLP_ROOT_CLK_ENABLE___POR 0x1 +#define PMM_TOP_ROOT_CLK_ENABLE__PMM_XO_ROOT_CLK_ENABLE___POR 0x1 +#define PMM_TOP_ROOT_CLK_ENABLE__AOAHB_ROOT_CLK_ENABLE___POR 0x1 +#define PMM_TOP_ROOT_CLK_ENABLE__AON_DBG_LPO_ROOT_CLK_ENABLE___M 0x00004000 +#define PMM_TOP_ROOT_CLK_ENABLE__AON_DBG_LPO_ROOT_CLK_ENABLE___S 14 +#define PMM_TOP_ROOT_CLK_ENABLE__PMM_TCXO_CLK_ENABLE___M 0x00002000 +#define PMM_TOP_ROOT_CLK_ENABLE__PMM_TCXO_CLK_ENABLE___S 13 +#define PMM_TOP_ROOT_CLK_ENABLE__PMM_SLP_ROOT_CLK_ENABLE___M 0x00000400 +#define PMM_TOP_ROOT_CLK_ENABLE__PMM_SLP_ROOT_CLK_ENABLE___S 10 +#define PMM_TOP_ROOT_CLK_ENABLE__PMM_XO_ROOT_CLK_ENABLE___M 0x00000200 +#define PMM_TOP_ROOT_CLK_ENABLE__PMM_XO_ROOT_CLK_ENABLE___S 9 +#define PMM_TOP_ROOT_CLK_ENABLE__AOAHB_ROOT_CLK_ENABLE___M 0x00000010 +#define PMM_TOP_ROOT_CLK_ENABLE__AOAHB_ROOT_CLK_ENABLE___S 4 +#define PMM_TOP_ROOT_CLK_ENABLE___M 0x00006610 +#define PMM_TOP_ROOT_CLK_ENABLE___S 4 + +#define PMM_TOP_CLKGATE_DISABLE (0x00B70014) +#define PMM_TOP_CLKGATE_DISABLE___RWC QCSR_REG_RW +#define PMM_TOP_CLKGATE_DISABLE___POR 0x00000000 +#define PMM_TOP_CLKGATE_DISABLE__AON_DBG_LPO_CLKGATE_DISABLE___POR 0x0 +#define PMM_TOP_CLKGATE_DISABLE__WCSS_WCSSAON_CLKGATE_DISABLE___POR 0x0 +#define PMM_TOP_CLKGATE_DISABLE__WCMN_STATUS_CLKGATE_DISABLE___POR 0x0 +#define PMM_TOP_CLKGATE_DISABLE__WCMN_REG_CLKGATE_DISABLE___POR 0x0 +#define PMM_TOP_CLKGATE_DISABLE__PMM_CX_CLKGATE_DISABLE___POR 0x0 +#define PMM_TOP_CLKGATE_DISABLE__PMM_WSI_CLKGATE_DISABLE___POR 0x0 +#define PMM_TOP_CLKGATE_DISABLE__PMM_WDOG_CLKGATE_DISABLE___POR 0x0 +#define PMM_TOP_CLKGATE_DISABLE__PMM_XO_CLKGATE_DISABLE___POR 0x0 +#define PMM_TOP_CLKGATE_DISABLE__AON_DBG_LPO_CLKGATE_DISABLE___M 0x00800000 +#define PMM_TOP_CLKGATE_DISABLE__AON_DBG_LPO_CLKGATE_DISABLE___S 23 +#define PMM_TOP_CLKGATE_DISABLE__WCSS_WCSSAON_CLKGATE_DISABLE___M 0x00400000 +#define PMM_TOP_CLKGATE_DISABLE__WCSS_WCSSAON_CLKGATE_DISABLE___S 22 +#define PMM_TOP_CLKGATE_DISABLE__WCMN_STATUS_CLKGATE_DISABLE___M 0x00200000 +#define PMM_TOP_CLKGATE_DISABLE__WCMN_STATUS_CLKGATE_DISABLE___S 21 +#define PMM_TOP_CLKGATE_DISABLE__WCMN_REG_CLKGATE_DISABLE___M 0x00100000 +#define PMM_TOP_CLKGATE_DISABLE__WCMN_REG_CLKGATE_DISABLE___S 20 +#define PMM_TOP_CLKGATE_DISABLE__PMM_CX_CLKGATE_DISABLE___M 0x00008000 +#define PMM_TOP_CLKGATE_DISABLE__PMM_CX_CLKGATE_DISABLE___S 15 +#define PMM_TOP_CLKGATE_DISABLE__PMM_WSI_CLKGATE_DISABLE___M 0x00002000 +#define PMM_TOP_CLKGATE_DISABLE__PMM_WSI_CLKGATE_DISABLE___S 13 +#define PMM_TOP_CLKGATE_DISABLE__PMM_WDOG_CLKGATE_DISABLE___M 0x00001000 +#define PMM_TOP_CLKGATE_DISABLE__PMM_WDOG_CLKGATE_DISABLE___S 12 +#define PMM_TOP_CLKGATE_DISABLE__PMM_XO_CLKGATE_DISABLE___M 0x00000080 +#define PMM_TOP_CLKGATE_DISABLE__PMM_XO_CLKGATE_DISABLE___S 7 +#define PMM_TOP_CLKGATE_DISABLE___M 0x00F0B080 +#define PMM_TOP_CLKGATE_DISABLE___S 7 + +#define PMM_TOP_SOFT_RESET (0x00B70018) +#define PMM_TOP_SOFT_RESET___RWC QCSR_REG_RW +#define PMM_TOP_SOFT_RESET___POR 0x00000000 +#define PMM_TOP_SOFT_RESET__PMM_WSI_SOFT_RESET___POR 0x0 +#define PMM_TOP_SOFT_RESET__PMM_SLP_SOFT_RESET___POR 0x0 +#define PMM_TOP_SOFT_RESET__PMM_TCXO_SOFT_RESET___POR 0x0 +#define PMM_TOP_SOFT_RESET__AOAHB_SOFT_RESET___POR 0x0 +#define PMM_TOP_SOFT_RESET__PMM_WSI_SOFT_RESET___M 0x00002000 +#define PMM_TOP_SOFT_RESET__PMM_WSI_SOFT_RESET___S 13 +#define PMM_TOP_SOFT_RESET__PMM_SLP_SOFT_RESET___M 0x00000200 +#define PMM_TOP_SOFT_RESET__PMM_SLP_SOFT_RESET___S 9 +#define PMM_TOP_SOFT_RESET__PMM_TCXO_SOFT_RESET___M 0x00000100 +#define PMM_TOP_SOFT_RESET__PMM_TCXO_SOFT_RESET___S 8 +#define PMM_TOP_SOFT_RESET__AOAHB_SOFT_RESET___M 0x00000010 +#define PMM_TOP_SOFT_RESET__AOAHB_SOFT_RESET___S 4 +#define PMM_TOP_SOFT_RESET___M 0x00002310 +#define PMM_TOP_SOFT_RESET___S 4 + +#define PMM_TOP_PMU_TESTBUS_CTL (0x00B7001C) +#define PMM_TOP_PMU_TESTBUS_CTL___RWC QCSR_REG_RW +#define PMM_TOP_PMU_TESTBUS_CTL___POR 0x0000000F +#define PMM_TOP_PMU_TESTBUS_CTL__AON_SOC_SR_STATUS_EN___POR 0x0 +#define PMM_TOP_PMU_TESTBUS_CTL__AHB_TESTBUS_SEL___POR 0x0 +#define PMM_TOP_PMU_TESTBUS_CTL__TCXO_TESTBUS_SEL___POR 0xF +#define PMM_TOP_PMU_TESTBUS_CTL__AON_SOC_SR_STATUS_EN___M 0x00000100 +#define PMM_TOP_PMU_TESTBUS_CTL__AON_SOC_SR_STATUS_EN___S 8 +#define PMM_TOP_PMU_TESTBUS_CTL__AHB_TESTBUS_SEL___M 0x000000F0 +#define PMM_TOP_PMU_TESTBUS_CTL__AHB_TESTBUS_SEL___S 4 +#define PMM_TOP_PMU_TESTBUS_CTL__TCXO_TESTBUS_SEL___M 0x0000000F +#define PMM_TOP_PMU_TESTBUS_CTL__TCXO_TESTBUS_SEL___S 0 +#define PMM_TOP_PMU_TESTBUS_CTL___M 0x000001FF +#define PMM_TOP_PMU_TESTBUS_CTL___S 0 + +#define PMM_TOP_PMU_TESTBUS_STS (0x00B70020) +#define PMM_TOP_PMU_TESTBUS_STS___RWC QCSR_REG_RO +#define PMM_TOP_PMU_TESTBUS_STS___POR 0x00000000 +#define PMM_TOP_PMU_TESTBUS_STS__TESTBUS_STS___POR 0x00000000 +#define PMM_TOP_PMU_TESTBUS_STS__TESTBUS_STS___M 0xFFFFFFFF +#define PMM_TOP_PMU_TESTBUS_STS__TESTBUS_STS___S 0 +#define PMM_TOP_PMU_TESTBUS_STS___M 0xFFFFFFFF +#define PMM_TOP_PMU_TESTBUS_STS___S 0 + +#define PMM_TOP_TESTBUS_CTL (0x00B70024) +#define PMM_TOP_TESTBUS_CTL___RWC QCSR_REG_RW +#define PMM_TOP_TESTBUS_CTL___POR 0x00000000 +#define PMM_TOP_TESTBUS_CTL__AOAHB_TESTBUS_ENABLE___POR 0x0 +#define PMM_TOP_TESTBUS_CTL__AOAHB_VITALS_TESTBUS_ENABLE___POR 0x0 +#define PMM_TOP_TESTBUS_CTL__OBS_DBG_CDIV_MAX_COUNT___POR 0x0 +#define PMM_TOP_TESTBUS_CTL__TESTBUS_CTL___POR 0x00000 +#define PMM_TOP_TESTBUS_CTL__AOAHB_TESTBUS_ENABLE___M 0x80000000 +#define PMM_TOP_TESTBUS_CTL__AOAHB_TESTBUS_ENABLE___S 31 +#define PMM_TOP_TESTBUS_CTL__AOAHB_VITALS_TESTBUS_ENABLE___M 0x40000000 +#define PMM_TOP_TESTBUS_CTL__AOAHB_VITALS_TESTBUS_ENABLE___S 30 +#define PMM_TOP_TESTBUS_CTL__OBS_DBG_CDIV_MAX_COUNT___M 0x00700000 +#define PMM_TOP_TESTBUS_CTL__OBS_DBG_CDIV_MAX_COUNT___S 20 +#define PMM_TOP_TESTBUS_CTL__TESTBUS_CTL___M 0x0007FFFF +#define PMM_TOP_TESTBUS_CTL__TESTBUS_CTL___S 0 +#define PMM_TOP_TESTBUS_CTL___M 0xC077FFFF +#define PMM_TOP_TESTBUS_CTL___S 0 + +#define PMM_TOP_TESTBUS_STS (0x00B70028) +#define PMM_TOP_TESTBUS_STS___RWC QCSR_REG_RO +#define PMM_TOP_TESTBUS_STS___POR 0x00000000 +#define PMM_TOP_TESTBUS_STS__TESTBUS_STS___POR 0x00000000 +#define PMM_TOP_TESTBUS_STS__TESTBUS_STS___M 0xFFFFFFFF +#define PMM_TOP_TESTBUS_STS__TESTBUS_STS___S 0 +#define PMM_TOP_TESTBUS_STS___M 0xFFFFFFFF +#define PMM_TOP_TESTBUS_STS___S 0 + +#define PMM_TOP_WDOG1_RESET (0x00B7002C) +#define PMM_TOP_WDOG1_RESET___RWC QCSR_REG_WO +#define PMM_TOP_WDOG1_RESET___POR 0x00000000 +#define PMM_TOP_WDOG1_RESET__WDOG_RESET___POR 0x0 +#define PMM_TOP_WDOG1_RESET__WDOG_RESET___M 0x00000001 +#define PMM_TOP_WDOG1_RESET__WDOG_RESET___S 0 +#define PMM_TOP_WDOG1_RESET___M 0x00000001 +#define PMM_TOP_WDOG1_RESET___S 0 + +#define PMM_TOP_WDOG1_CTL (0x00B70030) +#define PMM_TOP_WDOG1_CTL___RWC QCSR_REG_RW +#define PMM_TOP_WDOG1_CTL___POR 0x00000000 +#define PMM_TOP_WDOG1_CTL__ENABLE___POR 0x0 +#define PMM_TOP_WDOG1_CTL__ENABLE___M 0x00000001 +#define PMM_TOP_WDOG1_CTL__ENABLE___S 0 +#define PMM_TOP_WDOG1_CTL___M 0x00000001 +#define PMM_TOP_WDOG1_CTL___S 0 + +#define PMM_TOP_WDOG1_STATUS (0x00B70034) +#define PMM_TOP_WDOG1_STATUS___RWC QCSR_REG_RW +#define PMM_TOP_WDOG1_STATUS___POR 0x00000000 +#define PMM_TOP_WDOG1_STATUS__WDOG_BITE_ACK___POR 0x0 +#define PMM_TOP_WDOG1_STATUS__WDOG_COUNT___POR 0x00000 +#define PMM_TOP_WDOG1_STATUS__WDOG_EXPIRED_STATUS___POR 0x0 +#define PMM_TOP_WDOG1_STATUS__WDOG_BITE_ACK___M 0x80000000 +#define PMM_TOP_WDOG1_STATUS__WDOG_BITE_ACK___S 31 +#define PMM_TOP_WDOG1_STATUS__WDOG_COUNT___M 0x001FFFFE +#define PMM_TOP_WDOG1_STATUS__WDOG_COUNT___S 1 +#define PMM_TOP_WDOG1_STATUS__WDOG_EXPIRED_STATUS___M 0x00000001 +#define PMM_TOP_WDOG1_STATUS__WDOG_EXPIRED_STATUS___S 0 +#define PMM_TOP_WDOG1_STATUS___M 0x801FFFFF +#define PMM_TOP_WDOG1_STATUS___S 0 + +#define PMM_TOP_WDOG1_BITE_TIME (0x00B70038) +#define PMM_TOP_WDOG1_BITE_TIME___RWC QCSR_REG_RW +#define PMM_TOP_WDOG1_BITE_TIME___POR 0x000FFFFF +#define PMM_TOP_WDOG1_BITE_TIME__DATA___POR 0xFFFFF +#define PMM_TOP_WDOG1_BITE_TIME__DATA___M 0x000FFFFF +#define PMM_TOP_WDOG1_BITE_TIME__DATA___S 0 +#define PMM_TOP_WDOG1_BITE_TIME___M 0x000FFFFF +#define PMM_TOP_WDOG1_BITE_TIME___S 0 + +#define PMM_TOP_WDOG1_TEST_LOAD (0x00B7003C) +#define PMM_TOP_WDOG1_TEST_LOAD___RWC QCSR_REG_WO +#define PMM_TOP_WDOG1_TEST_LOAD___POR 0x00000000 +#define PMM_TOP_WDOG1_TEST_LOAD__LOAD___POR 0x00000000 +#define PMM_TOP_WDOG1_TEST_LOAD__LOAD___M 0xFFFFFFFF +#define PMM_TOP_WDOG1_TEST_LOAD__LOAD___S 0 +#define PMM_TOP_WDOG1_TEST_LOAD___M 0xFFFFFFFF +#define PMM_TOP_WDOG1_TEST_LOAD___S 0 + +#define PMM_TOP_WDOG1_TEST (0x00B70040) +#define PMM_TOP_WDOG1_TEST___RWC QCSR_REG_RW +#define PMM_TOP_WDOG1_TEST___POR 0x00000000 +#define PMM_TOP_WDOG1_TEST__SYNC_STATUS___POR 0x0 +#define PMM_TOP_WDOG1_TEST__LOAD_VALUE___POR 0x00000 +#define PMM_TOP_WDOG1_TEST__SYNC_STATUS___M 0x00100000 +#define PMM_TOP_WDOG1_TEST__SYNC_STATUS___S 20 +#define PMM_TOP_WDOG1_TEST__LOAD_VALUE___M 0x000FFFFF +#define PMM_TOP_WDOG1_TEST__LOAD_VALUE___S 0 +#define PMM_TOP_WDOG1_TEST___M 0x001FFFFF +#define PMM_TOP_WDOG1_TEST___S 0 + +#define PMM_TOP_WDOG2_RESET (0x00B70044) +#define PMM_TOP_WDOG2_RESET___RWC QCSR_REG_WO +#define PMM_TOP_WDOG2_RESET___POR 0x00000000 +#define PMM_TOP_WDOG2_RESET__WDOG_RESET___POR 0x0 +#define PMM_TOP_WDOG2_RESET__WDOG_RESET___M 0x00000001 +#define PMM_TOP_WDOG2_RESET__WDOG_RESET___S 0 +#define PMM_TOP_WDOG2_RESET___M 0x00000001 +#define PMM_TOP_WDOG2_RESET___S 0 + +#define PMM_TOP_WDOG2_CTL (0x00B70048) +#define PMM_TOP_WDOG2_CTL___RWC QCSR_REG_RW +#define PMM_TOP_WDOG2_CTL___POR 0x00000000 +#define PMM_TOP_WDOG2_CTL__ENABLE___POR 0x0 +#define PMM_TOP_WDOG2_CTL__ENABLE___M 0x00000001 +#define PMM_TOP_WDOG2_CTL__ENABLE___S 0 +#define PMM_TOP_WDOG2_CTL___M 0x00000001 +#define PMM_TOP_WDOG2_CTL___S 0 + +#define PMM_TOP_WDOG2_STATUS (0x00B7004C) +#define PMM_TOP_WDOG2_STATUS___RWC QCSR_REG_RW +#define PMM_TOP_WDOG2_STATUS___POR 0x00000000 +#define PMM_TOP_WDOG2_STATUS__WDOG_BITE_ACK___POR 0x0 +#define PMM_TOP_WDOG2_STATUS__WDOG_COUNT___POR 0x00000 +#define PMM_TOP_WDOG2_STATUS__WDOG_EXPIRED_STATUS___POR 0x0 +#define PMM_TOP_WDOG2_STATUS__WDOG_BITE_ACK___M 0x80000000 +#define PMM_TOP_WDOG2_STATUS__WDOG_BITE_ACK___S 31 +#define PMM_TOP_WDOG2_STATUS__WDOG_COUNT___M 0x001FFFFE +#define PMM_TOP_WDOG2_STATUS__WDOG_COUNT___S 1 +#define PMM_TOP_WDOG2_STATUS__WDOG_EXPIRED_STATUS___M 0x00000001 +#define PMM_TOP_WDOG2_STATUS__WDOG_EXPIRED_STATUS___S 0 +#define PMM_TOP_WDOG2_STATUS___M 0x801FFFFF +#define PMM_TOP_WDOG2_STATUS___S 0 + +#define PMM_TOP_WDOG2_BITE_TIME (0x00B70050) +#define PMM_TOP_WDOG2_BITE_TIME___RWC QCSR_REG_RW +#define PMM_TOP_WDOG2_BITE_TIME___POR 0x000FFFFF +#define PMM_TOP_WDOG2_BITE_TIME__DATA___POR 0xFFFFF +#define PMM_TOP_WDOG2_BITE_TIME__DATA___M 0x000FFFFF +#define PMM_TOP_WDOG2_BITE_TIME__DATA___S 0 +#define PMM_TOP_WDOG2_BITE_TIME___M 0x000FFFFF +#define PMM_TOP_WDOG2_BITE_TIME___S 0 + +#define PMM_TOP_WDOG2_TEST_LOAD (0x00B70054) +#define PMM_TOP_WDOG2_TEST_LOAD___RWC QCSR_REG_WO +#define PMM_TOP_WDOG2_TEST_LOAD___POR 0x00000000 +#define PMM_TOP_WDOG2_TEST_LOAD__LOAD___POR 0x00000000 +#define PMM_TOP_WDOG2_TEST_LOAD__LOAD___M 0xFFFFFFFF +#define PMM_TOP_WDOG2_TEST_LOAD__LOAD___S 0 +#define PMM_TOP_WDOG2_TEST_LOAD___M 0xFFFFFFFF +#define PMM_TOP_WDOG2_TEST_LOAD___S 0 + +#define PMM_TOP_WDOG2_TEST (0x00B70058) +#define PMM_TOP_WDOG2_TEST___RWC QCSR_REG_RW +#define PMM_TOP_WDOG2_TEST___POR 0x00000000 +#define PMM_TOP_WDOG2_TEST__SYNC_STATUS___POR 0x0 +#define PMM_TOP_WDOG2_TEST__LOAD_VALUE___POR 0x00000 +#define PMM_TOP_WDOG2_TEST__SYNC_STATUS___M 0x00100000 +#define PMM_TOP_WDOG2_TEST__SYNC_STATUS___S 20 +#define PMM_TOP_WDOG2_TEST__LOAD_VALUE___M 0x000FFFFF +#define PMM_TOP_WDOG2_TEST__LOAD_VALUE___S 0 +#define PMM_TOP_WDOG2_TEST___M 0x001FFFFF +#define PMM_TOP_WDOG2_TEST___S 0 + +#define PMM_TOP_SW_DEBUG (0x00B7005C) +#define PMM_TOP_SW_DEBUG___RWC QCSR_REG_RW +#define PMM_TOP_SW_DEBUG___POR 0xFFFF0040 +#define PMM_TOP_SW_DEBUG__AON_DBG_EVENT_MASK___POR 0xFFFF +#define PMM_TOP_SW_DEBUG__AON_DBG_FIFO_RESET___POR 0x0 +#define PMM_TOP_SW_DEBUG__AON_DBG_CSYSACK_LOOP___POR 0x0 +#define PMM_TOP_SW_DEBUG__AON_FIFO_CIR___POR 0x1 +#define PMM_TOP_SW_DEBUG__AON_DBG_DOWN___POR 0x0 +#define PMM_TOP_SW_DEBUG__NO_PLL_DISABLE___POR 0x0 +#define PMM_TOP_SW_DEBUG__NO_XO_DISABLE___POR 0x0 +#define PMM_TOP_SW_DEBUG__AON_DBG_EVENT_MASK___M 0xFFFF0000 +#define PMM_TOP_SW_DEBUG__AON_DBG_EVENT_MASK___S 16 +#define PMM_TOP_SW_DEBUG__AON_DBG_FIFO_RESET___M 0x00000100 +#define PMM_TOP_SW_DEBUG__AON_DBG_FIFO_RESET___S 8 +#define PMM_TOP_SW_DEBUG__AON_DBG_CSYSACK_LOOP___M 0x00000080 +#define PMM_TOP_SW_DEBUG__AON_DBG_CSYSACK_LOOP___S 7 +#define PMM_TOP_SW_DEBUG__AON_FIFO_CIR___M 0x00000040 +#define PMM_TOP_SW_DEBUG__AON_FIFO_CIR___S 6 +#define PMM_TOP_SW_DEBUG__AON_DBG_DOWN___M 0x00000020 +#define PMM_TOP_SW_DEBUG__AON_DBG_DOWN___S 5 +#define PMM_TOP_SW_DEBUG__NO_PLL_DISABLE___M 0x00000010 +#define PMM_TOP_SW_DEBUG__NO_PLL_DISABLE___S 4 +#define PMM_TOP_SW_DEBUG__NO_XO_DISABLE___M 0x00000008 +#define PMM_TOP_SW_DEBUG__NO_XO_DISABLE___S 3 +#define PMM_TOP_SW_DEBUG___M 0xFFFF01F8 +#define PMM_TOP_SW_DEBUG___S 3 + +#define PMM_TOP_SPARE_IN (0x00B70060) +#define PMM_TOP_SPARE_IN___RWC QCSR_REG_RO +#define PMM_TOP_SPARE_IN___POR 0x00000000 +#define PMM_TOP_SPARE_IN__SPARE_IN___POR 0x00000000 +#define PMM_TOP_SPARE_IN__SPARE_IN___M 0xFFFFFFFF +#define PMM_TOP_SPARE_IN__SPARE_IN___S 0 +#define PMM_TOP_SPARE_IN___M 0xFFFFFFFF +#define PMM_TOP_SPARE_IN___S 0 + +#define PMM_TOP_SPARE_OUT (0x00B70064) +#define PMM_TOP_SPARE_OUT___RWC QCSR_REG_RW +#define PMM_TOP_SPARE_OUT___POR 0x00000000 +#define PMM_TOP_SPARE_OUT__SPARE_OUT___POR 0x00000000 +#define PMM_TOP_SPARE_OUT__SPARE_OUT___M 0xFFFFFFFF +#define PMM_TOP_SPARE_OUT__SPARE_OUT___S 0 +#define PMM_TOP_SPARE_OUT___M 0xFFFFFFFF +#define PMM_TOP_SPARE_OUT___S 0 + +#define PMM_TOP_AON_SPARE (0x00B70068) +#define PMM_TOP_AON_SPARE___RWC QCSR_REG_RW +#define PMM_TOP_AON_SPARE___POR 0x00000000 +#define PMM_TOP_AON_SPARE__AON_SPARE_IN___POR 0x0000 +#define PMM_TOP_AON_SPARE__AON_SPARE_OUT___POR 0x0000 +#define PMM_TOP_AON_SPARE__AON_SPARE_IN___M 0xFFFF0000 +#define PMM_TOP_AON_SPARE__AON_SPARE_IN___S 16 +#define PMM_TOP_AON_SPARE__AON_SPARE_OUT___M 0x0000FFFF +#define PMM_TOP_AON_SPARE__AON_SPARE_OUT___S 0 +#define PMM_TOP_AON_SPARE___M 0xFFFFFFFF +#define PMM_TOP_AON_SPARE___S 0 + +#define PMM_TOP_PMM_CX_TIMER_WAKEUP_THRESH (0x00B7006C) +#define PMM_TOP_PMM_CX_TIMER_WAKEUP_THRESH___RWC QCSR_REG_RW +#define PMM_TOP_PMM_CX_TIMER_WAKEUP_THRESH___POR 0x00000000 +#define PMM_TOP_PMM_CX_TIMER_WAKEUP_THRESH__PMM_CX_TIMER_WAKEUP_THRESH___POR 0x00000000 +#define PMM_TOP_PMM_CX_TIMER_WAKEUP_THRESH__PMM_CX_TIMER_WAKEUP_THRESH___M 0xFFFFFFFF +#define PMM_TOP_PMM_CX_TIMER_WAKEUP_THRESH__PMM_CX_TIMER_WAKEUP_THRESH___S 0 +#define PMM_TOP_PMM_CX_TIMER_WAKEUP_THRESH___M 0xFFFFFFFF +#define PMM_TOP_PMM_CX_TIMER_WAKEUP_THRESH___S 0 + +#define PMM_TOP_XO_SETTLE_TIMER_CSR (0x00B70070) +#define PMM_TOP_XO_SETTLE_TIMER_CSR___RWC QCSR_REG_RW +#define PMM_TOP_XO_SETTLE_TIMER_CSR___POR 0x00000010 +#define PMM_TOP_XO_SETTLE_TIMER_CSR__ENABLE_XO_TOGGLE_CHECK___POR 0x1 +#define PMM_TOP_XO_SETTLE_TIMER_CSR__ENABLE_XO_TOGGLE_CHECK___M 0x00000010 +#define PMM_TOP_XO_SETTLE_TIMER_CSR__ENABLE_XO_TOGGLE_CHECK___S 4 +#define PMM_TOP_XO_SETTLE_TIMER_CSR___M 0x00000010 +#define PMM_TOP_XO_SETTLE_TIMER_CSR___S 4 + +#define PMM_TOP_AON_PWR_DOWN_CNT (0x00B70074) +#define PMM_TOP_AON_PWR_DOWN_CNT___RWC QCSR_REG_RO +#define PMM_TOP_AON_PWR_DOWN_CNT___POR 0x00000000 +#define PMM_TOP_AON_PWR_DOWN_CNT__AON_PWR_DOWN_CNT___POR 0x00000000 +#define PMM_TOP_AON_PWR_DOWN_CNT__AON_PWR_DOWN_CNT___M 0xFFFFFFFF +#define PMM_TOP_AON_PWR_DOWN_CNT__AON_PWR_DOWN_CNT___S 0 +#define PMM_TOP_AON_PWR_DOWN_CNT___M 0xFFFFFFFF +#define PMM_TOP_AON_PWR_DOWN_CNT___S 0 + +#define PMM_TOP_TIMEOUT_SLAVE_CTL (0x00B70078) +#define PMM_TOP_TIMEOUT_SLAVE_CTL___RWC QCSR_REG_RW +#define PMM_TOP_TIMEOUT_SLAVE_CTL___POR 0x00000000 +#define PMM_TOP_TIMEOUT_SLAVE_CTL__TSLV_EN___POR 0x0 +#define PMM_TOP_TIMEOUT_SLAVE_CTL__TSLV_EN___M 0x00000001 +#define PMM_TOP_TIMEOUT_SLAVE_CTL__TSLV_EN___S 0 +#define PMM_TOP_TIMEOUT_SLAVE_CTL___M 0x00000001 +#define PMM_TOP_TIMEOUT_SLAVE_CTL___S 0 + +#define PMM_TOP_TIMEOUT_EXP (0x00B7007C) +#define PMM_TOP_TIMEOUT_EXP___RWC QCSR_REG_RW +#define PMM_TOP_TIMEOUT_EXP___POR 0x0000FFFF +#define PMM_TOP_TIMEOUT_EXP__IDLEREQ_TO_EXP___POR 0xFFFF +#define PMM_TOP_TIMEOUT_EXP__IDLEREQ_TO_EXP___M 0x0000FFFF +#define PMM_TOP_TIMEOUT_EXP__IDLEREQ_TO_EXP___S 0 +#define PMM_TOP_TIMEOUT_EXP___M 0x0000FFFF +#define PMM_TOP_TIMEOUT_EXP___S 0 + +#define PMM_TOP_PMU_CX_CSR (0x00B70080) +#define PMM_TOP_PMU_CX_CSR___RWC QCSR_REG_RW +#define PMM_TOP_PMU_CX_CSR___POR 0x0001010E +#define PMM_TOP_PMU_CX_CSR__PMM_CX_SM___POR 0x0001 +#define PMM_TOP_PMU_CX_CSR__PMM_SS_UP_TIMEOUT___POR 0x0 +#define PMM_TOP_PMU_CX_CSR__GCC_PRE_PREP_CLR___POR 0x0 +#define PMM_TOP_PMU_CX_CSR__SW_PMM_NO_RETENTION___POR 0x0 +#define PMM_TOP_PMU_CX_CSR__PLL_HW_CTL_DISABLE___POR 0x0 +#define PMM_TOP_PMU_CX_CSR__CE_IDLE_CHECK_EN___POR 0x1 +#define PMM_TOP_PMU_CX_CSR__NOC_DISCONNECT_STS___POR 0x0 +#define PMM_TOP_PMU_CX_CSR__NOC_DISCONNECT_DISABLE___POR 0x0 +#define PMM_TOP_PMU_CX_CSR__CSS_HW_CTL___POR 0x0 +#define PMM_TOP_PMU_CX_CSR__SW_FORCE_IDLE___POR 0x0 +#define PMM_TOP_PMU_CX_CSR__AXI_IDLE_CHECK_EN___POR 0x1 +#define PMM_TOP_PMU_CX_CSR__SW_USE_PLL_LOCK_DLY___POR 0x1 +#define PMM_TOP_PMU_CX_CSR__FAST_WAKEUP_EN___POR 0x1 +#define PMM_TOP_PMU_CX_CSR__SW_PMM_CX_EN___POR 0x0 +#define PMM_TOP_PMU_CX_CSR__PMM_CX_SM___M 0x1FFF0000 +#define PMM_TOP_PMU_CX_CSR__PMM_CX_SM___S 16 +#define PMM_TOP_PMU_CX_CSR__PMM_SS_UP_TIMEOUT___M 0x00001000 +#define PMM_TOP_PMU_CX_CSR__PMM_SS_UP_TIMEOUT___S 12 +#define PMM_TOP_PMU_CX_CSR__GCC_PRE_PREP_CLR___M 0x00000800 +#define PMM_TOP_PMU_CX_CSR__GCC_PRE_PREP_CLR___S 11 +#define PMM_TOP_PMU_CX_CSR__SW_PMM_NO_RETENTION___M 0x00000400 +#define PMM_TOP_PMU_CX_CSR__SW_PMM_NO_RETENTION___S 10 +#define PMM_TOP_PMU_CX_CSR__PLL_HW_CTL_DISABLE___M 0x00000200 +#define PMM_TOP_PMU_CX_CSR__PLL_HW_CTL_DISABLE___S 9 +#define PMM_TOP_PMU_CX_CSR__CE_IDLE_CHECK_EN___M 0x00000100 +#define PMM_TOP_PMU_CX_CSR__CE_IDLE_CHECK_EN___S 8 +#define PMM_TOP_PMU_CX_CSR__NOC_DISCONNECT_STS___M 0x00000080 +#define PMM_TOP_PMU_CX_CSR__NOC_DISCONNECT_STS___S 7 +#define PMM_TOP_PMU_CX_CSR__NOC_DISCONNECT_DISABLE___M 0x00000040 +#define PMM_TOP_PMU_CX_CSR__NOC_DISCONNECT_DISABLE___S 6 +#define PMM_TOP_PMU_CX_CSR__CSS_HW_CTL___M 0x00000020 +#define PMM_TOP_PMU_CX_CSR__CSS_HW_CTL___S 5 +#define PMM_TOP_PMU_CX_CSR__SW_FORCE_IDLE___M 0x00000010 +#define PMM_TOP_PMU_CX_CSR__SW_FORCE_IDLE___S 4 +#define PMM_TOP_PMU_CX_CSR__AXI_IDLE_CHECK_EN___M 0x00000008 +#define PMM_TOP_PMU_CX_CSR__AXI_IDLE_CHECK_EN___S 3 +#define PMM_TOP_PMU_CX_CSR__SW_USE_PLL_LOCK_DLY___M 0x00000004 +#define PMM_TOP_PMU_CX_CSR__SW_USE_PLL_LOCK_DLY___S 2 +#define PMM_TOP_PMU_CX_CSR__FAST_WAKEUP_EN___M 0x00000002 +#define PMM_TOP_PMU_CX_CSR__FAST_WAKEUP_EN___S 1 +#define PMM_TOP_PMU_CX_CSR__SW_PMM_CX_EN___M 0x00000001 +#define PMM_TOP_PMU_CX_CSR__SW_PMM_CX_EN___S 0 +#define PMM_TOP_PMU_CX_CSR___M 0x1FFF1FFF +#define PMM_TOP_PMU_CX_CSR___S 0 + +#define PMM_TOP_WAKEUP_TIME1 (0x00B70084) +#define PMM_TOP_WAKEUP_TIME1___RWC QCSR_REG_RO +#define PMM_TOP_WAKEUP_TIME1___POR 0x00000000 +#define PMM_TOP_WAKEUP_TIME1__AON_WAKEUP_TIME1___POR 0x00000000 +#define PMM_TOP_WAKEUP_TIME1__AON_WAKEUP_TIME1___M 0xFFFFFFFF +#define PMM_TOP_WAKEUP_TIME1__AON_WAKEUP_TIME1___S 0 +#define PMM_TOP_WAKEUP_TIME1___M 0xFFFFFFFF +#define PMM_TOP_WAKEUP_TIME1___S 0 + +#define PMM_TOP_WAKEUP_TIME2 (0x00B70088) +#define PMM_TOP_WAKEUP_TIME2___RWC QCSR_REG_RO +#define PMM_TOP_WAKEUP_TIME2___POR 0x00000000 +#define PMM_TOP_WAKEUP_TIME2__AON_WAKEUP_TIME2___POR 0x00000000 +#define PMM_TOP_WAKEUP_TIME2__AON_WAKEUP_TIME2___M 0xFFFFFFFF +#define PMM_TOP_WAKEUP_TIME2__AON_WAKEUP_TIME2___S 0 +#define PMM_TOP_WAKEUP_TIME2___M 0xFFFFFFFF +#define PMM_TOP_WAKEUP_TIME2___S 0 + +#define PMM_TOP_PLL_OUT_DIS_DELAY (0x00B7008C) +#define PMM_TOP_PLL_OUT_DIS_DELAY___RWC QCSR_REG_RW +#define PMM_TOP_PLL_OUT_DIS_DELAY___POR 0x00000690 +#define PMM_TOP_PLL_OUT_DIS_DELAY__PLL_DN_OUT_DIS_TIME___POR 0x0000 +#define PMM_TOP_PLL_OUT_DIS_DELAY__PLL_UP_OUT_DIS_TIME___POR 0x0690 +#define PMM_TOP_PLL_OUT_DIS_DELAY__PLL_DN_OUT_DIS_TIME___M 0xFFFF0000 +#define PMM_TOP_PLL_OUT_DIS_DELAY__PLL_DN_OUT_DIS_TIME___S 16 +#define PMM_TOP_PLL_OUT_DIS_DELAY__PLL_UP_OUT_DIS_TIME___M 0x0000FFFF +#define PMM_TOP_PLL_OUT_DIS_DELAY__PLL_UP_OUT_DIS_TIME___S 0 +#define PMM_TOP_PLL_OUT_DIS_DELAY___M 0xFFFFFFFF +#define PMM_TOP_PLL_OUT_DIS_DELAY___S 0 + +#define PMM_TOP_PLL_LOCK_DIS_DELAY (0x00B70090) +#define PMM_TOP_PLL_LOCK_DIS_DELAY___RWC QCSR_REG_RW +#define PMM_TOP_PLL_LOCK_DIS_DELAY___POR 0x00050019 +#define PMM_TOP_PLL_LOCK_DIS_DELAY__PLL_DISABLE_DLY___POR 0x0005 +#define PMM_TOP_PLL_LOCK_DIS_DELAY__PLL_LOCK_DLY___POR 0x0019 +#define PMM_TOP_PLL_LOCK_DIS_DELAY__PLL_DISABLE_DLY___M 0xFFFF0000 +#define PMM_TOP_PLL_LOCK_DIS_DELAY__PLL_DISABLE_DLY___S 16 +#define PMM_TOP_PLL_LOCK_DIS_DELAY__PLL_LOCK_DLY___M 0x0000FFFF +#define PMM_TOP_PLL_LOCK_DIS_DELAY__PLL_LOCK_DLY___S 0 +#define PMM_TOP_PLL_LOCK_DIS_DELAY___M 0xFFFFFFFF +#define PMM_TOP_PLL_LOCK_DIS_DELAY___S 0 + +#define PMM_TOP_BACKOFF_TIME (0x00B70094) +#define PMM_TOP_BACKOFF_TIME___RWC QCSR_REG_RW +#define PMM_TOP_BACKOFF_TIME___POR 0x00000000 +#define PMM_TOP_BACKOFF_TIME__AON_BACKOFF_TIME___POR 0x00000000 +#define PMM_TOP_BACKOFF_TIME__AON_BACKOFF_TIME___M 0xFFFFFFFF +#define PMM_TOP_BACKOFF_TIME__AON_BACKOFF_TIME___S 0 +#define PMM_TOP_BACKOFF_TIME___M 0xFFFFFFFF +#define PMM_TOP_BACKOFF_TIME___S 0 + +#define PMM_TOP_AON_SM_CTL (0x00B70098) +#define PMM_TOP_AON_SM_CTL___RWC QCSR_REG_RW +#define PMM_TOP_AON_SM_CTL___POR 0x00100008 +#define PMM_TOP_AON_SM_CTL__PMM_AON_SM___POR 0x0010 +#define PMM_TOP_AON_SM_CTL__WAKEUP_LATENCY_CLR___POR 0x0 +#define PMM_TOP_AON_SM_CTL__AON_WAKEUP_SOON_OVRD___POR 0x0 +#define PMM_TOP_AON_SM_CTL__AON_WAKEUP_SOON_CX_OVRD___POR 0x0 +#define PMM_TOP_AON_SM_CTL__AON_PWR_DOWN_CNT_CLR___POR 0x0 +#define PMM_TOP_AON_SM_CTL__AON_FAST_WAKEUP_EN___POR 0x1 +#define PMM_TOP_AON_SM_CTL__AON_NO_RET_MSM___POR 0x0 +#define PMM_TOP_AON_SM_CTL__AON_NO_RETENTION___POR 0x0 +#define PMM_TOP_AON_SM_CTL__PMM_AON_SM___M 0xFFFF0000 +#define PMM_TOP_AON_SM_CTL__PMM_AON_SM___S 16 +#define PMM_TOP_AON_SM_CTL__WAKEUP_LATENCY_CLR___M 0x00000080 +#define PMM_TOP_AON_SM_CTL__WAKEUP_LATENCY_CLR___S 7 +#define PMM_TOP_AON_SM_CTL__AON_WAKEUP_SOON_OVRD___M 0x00000040 +#define PMM_TOP_AON_SM_CTL__AON_WAKEUP_SOON_OVRD___S 6 +#define PMM_TOP_AON_SM_CTL__AON_WAKEUP_SOON_CX_OVRD___M 0x00000020 +#define PMM_TOP_AON_SM_CTL__AON_WAKEUP_SOON_CX_OVRD___S 5 +#define PMM_TOP_AON_SM_CTL__AON_PWR_DOWN_CNT_CLR___M 0x00000010 +#define PMM_TOP_AON_SM_CTL__AON_PWR_DOWN_CNT_CLR___S 4 +#define PMM_TOP_AON_SM_CTL__AON_FAST_WAKEUP_EN___M 0x00000008 +#define PMM_TOP_AON_SM_CTL__AON_FAST_WAKEUP_EN___S 3 +#define PMM_TOP_AON_SM_CTL__AON_NO_RET_MSM___M 0x00000004 +#define PMM_TOP_AON_SM_CTL__AON_NO_RET_MSM___S 2 +#define PMM_TOP_AON_SM_CTL__AON_NO_RETENTION___M 0x00000002 +#define PMM_TOP_AON_SM_CTL__AON_NO_RETENTION___S 1 +#define PMM_TOP_AON_SM_CTL___M 0xFFFF00FE +#define PMM_TOP_AON_SM_CTL___S 1 + +#define PMM_TOP_AON_SLP_TMR_CTL (0x00B7009C) +#define PMM_TOP_AON_SLP_TMR_CTL___RWC QCSR_REG_RW +#define PMM_TOP_AON_SLP_TMR_CTL___POR 0x00000000 +#define PMM_TOP_AON_SLP_TMR_CTL__SYNC_STATUS___POR 0x0 +#define PMM_TOP_AON_SLP_TMR_CTL__AON_TMR_ADD___POR 0x0 +#define PMM_TOP_AON_SLP_TMR_CTL__AON_TMR_LD___POR 0x0 +#define PMM_TOP_AON_SLP_TMR_CTL__AON_TMR_DEC___POR 0x0 +#define PMM_TOP_AON_SLP_TMR_CTL__AON_TMR_EN___POR 0x0 +#define PMM_TOP_AON_SLP_TMR_CTL__SYNC_STATUS___M 0x80000000 +#define PMM_TOP_AON_SLP_TMR_CTL__SYNC_STATUS___S 31 +#define PMM_TOP_AON_SLP_TMR_CTL__AON_TMR_ADD___M 0x00000008 +#define PMM_TOP_AON_SLP_TMR_CTL__AON_TMR_ADD___S 3 +#define PMM_TOP_AON_SLP_TMR_CTL__AON_TMR_LD___M 0x00000004 +#define PMM_TOP_AON_SLP_TMR_CTL__AON_TMR_LD___S 2 +#define PMM_TOP_AON_SLP_TMR_CTL__AON_TMR_DEC___M 0x00000002 +#define PMM_TOP_AON_SLP_TMR_CTL__AON_TMR_DEC___S 1 +#define PMM_TOP_AON_SLP_TMR_CTL__AON_TMR_EN___M 0x00000001 +#define PMM_TOP_AON_SLP_TMR_CTL__AON_TMR_EN___S 0 +#define PMM_TOP_AON_SLP_TMR_CTL___M 0x8000000F +#define PMM_TOP_AON_SLP_TMR_CTL___S 0 + +#define PMM_TOP_AON_SLP_TMR_VAL_WR_LO (0x00B700A0) +#define PMM_TOP_AON_SLP_TMR_VAL_WR_LO___RWC QCSR_REG_RW +#define PMM_TOP_AON_SLP_TMR_VAL_WR_LO___POR 0x00000000 +#define PMM_TOP_AON_SLP_TMR_VAL_WR_LO__AON_SLP_TMR_WR_LO___POR 0x00000000 +#define PMM_TOP_AON_SLP_TMR_VAL_WR_LO__AON_SLP_TMR_WR_LO___M 0xFFFFFFFF +#define PMM_TOP_AON_SLP_TMR_VAL_WR_LO__AON_SLP_TMR_WR_LO___S 0 +#define PMM_TOP_AON_SLP_TMR_VAL_WR_LO___M 0xFFFFFFFF +#define PMM_TOP_AON_SLP_TMR_VAL_WR_LO___S 0 + +#define PMM_TOP_AON_SLP_TMR_VAL_WR_HI (0x00B700A4) +#define PMM_TOP_AON_SLP_TMR_VAL_WR_HI___RWC QCSR_REG_RW +#define PMM_TOP_AON_SLP_TMR_VAL_WR_HI___POR 0x00000000 +#define PMM_TOP_AON_SLP_TMR_VAL_WR_HI__AON_SLP_TMR_WR_HI___POR 0x0000 +#define PMM_TOP_AON_SLP_TMR_VAL_WR_HI__AON_SLP_TMR_WR_HI___M 0x0000FFFF +#define PMM_TOP_AON_SLP_TMR_VAL_WR_HI__AON_SLP_TMR_WR_HI___S 0 +#define PMM_TOP_AON_SLP_TMR_VAL_WR_HI___M 0x0000FFFF +#define PMM_TOP_AON_SLP_TMR_VAL_WR_HI___S 0 + +#define PMM_TOP_AON_SLP_TMR_VAL_LO (0x00B700A8) +#define PMM_TOP_AON_SLP_TMR_VAL_LO___RWC QCSR_REG_RO +#define PMM_TOP_AON_SLP_TMR_VAL_LO___POR 0x00000000 +#define PMM_TOP_AON_SLP_TMR_VAL_LO__AON_SLP_TMR___POR 0x00000000 +#define PMM_TOP_AON_SLP_TMR_VAL_LO__AON_SLP_TMR___M 0xFFFFFFFF +#define PMM_TOP_AON_SLP_TMR_VAL_LO__AON_SLP_TMR___S 0 +#define PMM_TOP_AON_SLP_TMR_VAL_LO___M 0xFFFFFFFF +#define PMM_TOP_AON_SLP_TMR_VAL_LO___S 0 + +#define PMM_TOP_AON_SLP_TMR_VAL_HI (0x00B700AC) +#define PMM_TOP_AON_SLP_TMR_VAL_HI___RWC QCSR_REG_RO +#define PMM_TOP_AON_SLP_TMR_VAL_HI___POR 0x00000000 +#define PMM_TOP_AON_SLP_TMR_VAL_HI__AON_SLP_TMR___POR 0x0000 +#define PMM_TOP_AON_SLP_TMR_VAL_HI__AON_SLP_TMR___M 0x0000FFFF +#define PMM_TOP_AON_SLP_TMR_VAL_HI__AON_SLP_TMR___S 0 +#define PMM_TOP_AON_SLP_TMR_VAL_HI___M 0x0000FFFF +#define PMM_TOP_AON_SLP_TMR_VAL_HI___S 0 + +#define PMM_TOP_AON_SLP_TMR_VAL_G_LO (0x00B700B0) +#define PMM_TOP_AON_SLP_TMR_VAL_G_LO___RWC QCSR_REG_RO +#define PMM_TOP_AON_SLP_TMR_VAL_G_LO___POR 0x00000000 +#define PMM_TOP_AON_SLP_TMR_VAL_G_LO__AON_SLP_TMR___POR 0x00000000 +#define PMM_TOP_AON_SLP_TMR_VAL_G_LO__AON_SLP_TMR___M 0xFFFFFFFF +#define PMM_TOP_AON_SLP_TMR_VAL_G_LO__AON_SLP_TMR___S 0 +#define PMM_TOP_AON_SLP_TMR_VAL_G_LO___M 0xFFFFFFFF +#define PMM_TOP_AON_SLP_TMR_VAL_G_LO___S 0 + +#define PMM_TOP_AON_SLP_TMR_VAL_G_HI (0x00B700B4) +#define PMM_TOP_AON_SLP_TMR_VAL_G_HI___RWC QCSR_REG_RO +#define PMM_TOP_AON_SLP_TMR_VAL_G_HI___POR 0x00000000 +#define PMM_TOP_AON_SLP_TMR_VAL_G_HI__AON_SLP_TMR___POR 0x0000 +#define PMM_TOP_AON_SLP_TMR_VAL_G_HI__AON_SLP_TMR___M 0x0000FFFF +#define PMM_TOP_AON_SLP_TMR_VAL_G_HI__AON_SLP_TMR___S 0 +#define PMM_TOP_AON_SLP_TMR_VAL_G_HI___M 0x0000FFFF +#define PMM_TOP_AON_SLP_TMR_VAL_G_HI___S 0 + +#define PMM_TOP_AON_SWITCHER_DLY (0x00B700B8) +#define PMM_TOP_AON_SWITCHER_DLY___RWC QCSR_REG_RW +#define PMM_TOP_AON_SWITCHER_DLY___POR 0x00000F0E +#define PMM_TOP_AON_SWITCHER_DLY__AON_WRITE_IP___POR 0x0 +#define PMM_TOP_AON_SWITCHER_DLY__AON_PBS_WAIT_DLY___POR 0x0000 +#define PMM_TOP_AON_SWITCHER_DLY__AON_SWITCHER_DLY___POR 0x0F0E +#define PMM_TOP_AON_SWITCHER_DLY__AON_WRITE_IP___M 0x80000000 +#define PMM_TOP_AON_SWITCHER_DLY__AON_WRITE_IP___S 31 +#define PMM_TOP_AON_SWITCHER_DLY__AON_PBS_WAIT_DLY___M 0x7FFF0000 +#define PMM_TOP_AON_SWITCHER_DLY__AON_PBS_WAIT_DLY___S 16 +#define PMM_TOP_AON_SWITCHER_DLY__AON_SWITCHER_DLY___M 0x0000FFFF +#define PMM_TOP_AON_SWITCHER_DLY__AON_SWITCHER_DLY___S 0 +#define PMM_TOP_AON_SWITCHER_DLY___M 0xFFFFFFFF +#define PMM_TOP_AON_SWITCHER_DLY___S 0 + +#define PMM_TOP_AON_TIMER_WAKEUP_THRESH (0x00B700BC) +#define PMM_TOP_AON_TIMER_WAKEUP_THRESH___RWC QCSR_REG_RW +#define PMM_TOP_AON_TIMER_WAKEUP_THRESH___POR 0x00000000 +#define PMM_TOP_AON_TIMER_WAKEUP_THRESH__AON_TIMER_WAKEUP_THRESH___POR 0x00000000 +#define PMM_TOP_AON_TIMER_WAKEUP_THRESH__AON_TIMER_WAKEUP_THRESH___M 0xFFFFFFFF +#define PMM_TOP_AON_TIMER_WAKEUP_THRESH__AON_TIMER_WAKEUP_THRESH___S 0 +#define PMM_TOP_AON_TIMER_WAKEUP_THRESH___M 0xFFFFFFFF +#define PMM_TOP_AON_TIMER_WAKEUP_THRESH___S 0 + +#define PMM_TOP_AON_INT_CLR (0x00B700C0) +#define PMM_TOP_AON_INT_CLR___RWC QCSR_REG_RW +#define PMM_TOP_AON_INT_CLR___POR 0x00000000 +#define PMM_TOP_AON_INT_CLR__AON_INT_CLR___POR 0x0000 +#define PMM_TOP_AON_INT_CLR__AON_INT_CLR___M 0x00001FFF +#define PMM_TOP_AON_INT_CLR__AON_INT_CLR___S 0 +#define PMM_TOP_AON_INT_CLR___M 0x00001FFF +#define PMM_TOP_AON_INT_CLR___S 0 + +#define PMM_TOP_AON_INT_POL (0x00B700C4) +#define PMM_TOP_AON_INT_POL___RWC QCSR_REG_RW +#define PMM_TOP_AON_INT_POL___POR 0x00001FFF +#define PMM_TOP_AON_INT_POL__AON_INT_POL___POR 0x1FFF +#define PMM_TOP_AON_INT_POL__AON_INT_POL___M 0x00001FFF +#define PMM_TOP_AON_INT_POL__AON_INT_POL___S 0 +#define PMM_TOP_AON_INT_POL___M 0x00001FFF +#define PMM_TOP_AON_INT_POL___S 0 + +#define PMM_TOP_AON_INT_POS_EDGE_EN (0x00B700C8) +#define PMM_TOP_AON_INT_POS_EDGE_EN___RWC QCSR_REG_RW +#define PMM_TOP_AON_INT_POS_EDGE_EN___POR 0x00000000 +#define PMM_TOP_AON_INT_POS_EDGE_EN__AON_INT_POS_EDGE_EN___POR 0x0000 +#define PMM_TOP_AON_INT_POS_EDGE_EN__AON_INT_POS_EDGE_EN___M 0x00001FFF +#define PMM_TOP_AON_INT_POS_EDGE_EN__AON_INT_POS_EDGE_EN___S 0 +#define PMM_TOP_AON_INT_POS_EDGE_EN___M 0x00001FFF +#define PMM_TOP_AON_INT_POS_EDGE_EN___S 0 + +#define PMM_TOP_AON_INT_NEG_EDGE_EN (0x00B700CC) +#define PMM_TOP_AON_INT_NEG_EDGE_EN___RWC QCSR_REG_RW +#define PMM_TOP_AON_INT_NEG_EDGE_EN___POR 0x00000000 +#define PMM_TOP_AON_INT_NEG_EDGE_EN__AON_INT_NEG_EDGE_EN___POR 0x0000 +#define PMM_TOP_AON_INT_NEG_EDGE_EN__AON_INT_NEG_EDGE_EN___M 0x00001FFF +#define PMM_TOP_AON_INT_NEG_EDGE_EN__AON_INT_NEG_EDGE_EN___S 0 +#define PMM_TOP_AON_INT_NEG_EDGE_EN___M 0x00001FFF +#define PMM_TOP_AON_INT_NEG_EDGE_EN___S 0 + +#define PMM_TOP_AON_INT_EN (0x00B700D0) +#define PMM_TOP_AON_INT_EN___RWC QCSR_REG_RW +#define PMM_TOP_AON_INT_EN___POR 0x00001FFF +#define PMM_TOP_AON_INT_EN__AON_INT_EN___POR 0x1FFF +#define PMM_TOP_AON_INT_EN__AON_INT_EN___M 0x00001FFF +#define PMM_TOP_AON_INT_EN__AON_INT_EN___S 0 +#define PMM_TOP_AON_INT_EN___M 0x00001FFF +#define PMM_TOP_AON_INT_EN___S 0 + +#define PMM_TOP_AON_INT_ACK_EN (0x00B700D4) +#define PMM_TOP_AON_INT_ACK_EN___RWC QCSR_REG_RW +#define PMM_TOP_AON_INT_ACK_EN___POR 0x00000020 +#define PMM_TOP_AON_INT_ACK_EN__AON_INT_ACK_EN___POR 0x0020 +#define PMM_TOP_AON_INT_ACK_EN__AON_INT_ACK_EN___M 0x00001FFF +#define PMM_TOP_AON_INT_ACK_EN__AON_INT_ACK_EN___S 0 +#define PMM_TOP_AON_INT_ACK_EN___M 0x00001FFF +#define PMM_TOP_AON_INT_ACK_EN___S 0 + +#define PMM_TOP_AON_INT_STICKY_EN (0x00B700D8) +#define PMM_TOP_AON_INT_STICKY_EN___RWC QCSR_REG_RW +#define PMM_TOP_AON_INT_STICKY_EN___POR 0x8000007C +#define PMM_TOP_AON_INT_STICKY_EN__ISR_INT_STICKY_EN___POR 0x1 +#define PMM_TOP_AON_INT_STICKY_EN__AON_INT_STICKY_EN___POR 0x007C +#define PMM_TOP_AON_INT_STICKY_EN__ISR_INT_STICKY_EN___M 0x80000000 +#define PMM_TOP_AON_INT_STICKY_EN__ISR_INT_STICKY_EN___S 31 +#define PMM_TOP_AON_INT_STICKY_EN__AON_INT_STICKY_EN___M 0x00001FFF +#define PMM_TOP_AON_INT_STICKY_EN__AON_INT_STICKY_EN___S 0 +#define PMM_TOP_AON_INT_STICKY_EN___M 0x80001FFF +#define PMM_TOP_AON_INT_STICKY_EN___S 0 + +#define PMM_TOP_AON_INT_STAT (0x00B700DC) +#define PMM_TOP_AON_INT_STAT___RWC QCSR_REG_RO +#define PMM_TOP_AON_INT_STAT___POR 0x00000000 +#define PMM_TOP_AON_INT_STAT__AON_INT_STAT___POR 0x0000 +#define PMM_TOP_AON_INT_STAT__AON_INT_STAT___M 0x00001FFF +#define PMM_TOP_AON_INT_STAT__AON_INT_STAT___S 0 +#define PMM_TOP_AON_INT_STAT___M 0x00001FFF +#define PMM_TOP_AON_INT_STAT___S 0 + +#define PMM_TOP_AON_INT_RAW_STAT (0x00B700E0) +#define PMM_TOP_AON_INT_RAW_STAT___RWC QCSR_REG_RO +#define PMM_TOP_AON_INT_RAW_STAT___POR 0x00000000 +#define PMM_TOP_AON_INT_RAW_STAT__AON_INT_RAW_STAT___POR 0x0000 +#define PMM_TOP_AON_INT_RAW_STAT__AON_INT_RAW_STAT___M 0x00001FFF +#define PMM_TOP_AON_INT_RAW_STAT__AON_INT_RAW_STAT___S 0 +#define PMM_TOP_AON_INT_RAW_STAT___M 0x00001FFF +#define PMM_TOP_AON_INT_RAW_STAT___S 0 + +#define PMM_TOP_WSI_CMD (0x00B700E4) +#define PMM_TOP_WSI_CMD___RWC QCSR_REG_RW +#define PMM_TOP_WSI_CMD___POR 0x00010000 +#define PMM_TOP_WSI_CMD__RF_CMD_IP___POR 0x0 +#define PMM_TOP_WSI_CMD__WSI_ERR_STATUS___POR 0x0 +#define PMM_TOP_WSI_CMD__PMM_WSI_SM___POR 0x001 +#define PMM_TOP_WSI_CMD__DISABLE_WSI_ERROR_CHECKING___POR 0x0 +#define PMM_TOP_WSI_CMD__SW_FORCE_IDLE___POR 0x0 +#define PMM_TOP_WSI_CMD__SW_XO_DIS___POR 0x0 +#define PMM_TOP_WSI_CMD__SW_XO_EN___POR 0x0 +#define PMM_TOP_WSI_CMD__SW_REG_WRITE___POR 0x0 +#define PMM_TOP_WSI_CMD__SW_REG_READ___POR 0x0 +#define PMM_TOP_WSI_CMD__SW_RF_RESET___POR 0x0 +#define PMM_TOP_WSI_CMD__SW_BUS_SYNC___POR 0x0 +#define PMM_TOP_WSI_CMD__SW_USE_PMM_WSI___POR 0x0 +#define PMM_TOP_WSI_CMD__RF_CMD_IP___M 0x80000000 +#define PMM_TOP_WSI_CMD__RF_CMD_IP___S 31 +#define PMM_TOP_WSI_CMD__WSI_ERR_STATUS___M 0x70000000 +#define PMM_TOP_WSI_CMD__WSI_ERR_STATUS___S 28 +#define PMM_TOP_WSI_CMD__PMM_WSI_SM___M 0x01FF0000 +#define PMM_TOP_WSI_CMD__PMM_WSI_SM___S 16 +#define PMM_TOP_WSI_CMD__DISABLE_WSI_ERROR_CHECKING___M 0x00000400 +#define PMM_TOP_WSI_CMD__DISABLE_WSI_ERROR_CHECKING___S 10 +#define PMM_TOP_WSI_CMD__SW_FORCE_IDLE___M 0x00000200 +#define PMM_TOP_WSI_CMD__SW_FORCE_IDLE___S 9 +#define PMM_TOP_WSI_CMD__SW_XO_DIS___M 0x00000100 +#define PMM_TOP_WSI_CMD__SW_XO_DIS___S 8 +#define PMM_TOP_WSI_CMD__SW_XO_EN___M 0x00000080 +#define PMM_TOP_WSI_CMD__SW_XO_EN___S 7 +#define PMM_TOP_WSI_CMD__SW_REG_WRITE___M 0x00000040 +#define PMM_TOP_WSI_CMD__SW_REG_WRITE___S 6 +#define PMM_TOP_WSI_CMD__SW_REG_READ___M 0x00000020 +#define PMM_TOP_WSI_CMD__SW_REG_READ___S 5 +#define PMM_TOP_WSI_CMD__SW_RF_RESET___M 0x00000010 +#define PMM_TOP_WSI_CMD__SW_RF_RESET___S 4 +#define PMM_TOP_WSI_CMD__SW_BUS_SYNC___M 0x00000008 +#define PMM_TOP_WSI_CMD__SW_BUS_SYNC___S 3 +#define PMM_TOP_WSI_CMD__SW_USE_PMM_WSI___M 0x00000004 +#define PMM_TOP_WSI_CMD__SW_USE_PMM_WSI___S 2 +#define PMM_TOP_WSI_CMD___M 0xF1FF07FC +#define PMM_TOP_WSI_CMD___S 2 + +#define PMM_TOP_WSI_MUX_SEL (0x00B700E8) +#define PMM_TOP_WSI_MUX_SEL___RWC QCSR_REG_RW +#define PMM_TOP_WSI_MUX_SEL___POR 0x00000000 +#define PMM_TOP_WSI_MUX_SEL__PHYB_RESERVED___POR 0x0 +#define PMM_TOP_WSI_MUX_SEL__USE_PHYB_WSI1___POR 0x0 +#define PMM_TOP_WSI_MUX_SEL__USE_PHYB_WSI0___POR 0x0 +#define PMM_TOP_WSI_MUX_SEL__PHYA_RESERVED___POR 0x00 +#define PMM_TOP_WSI_MUX_SEL__USE_PHYA_WSI1___POR 0x0 +#define PMM_TOP_WSI_MUX_SEL__USE_PHYA_WSI0___POR 0x0 +#define PMM_TOP_WSI_MUX_SEL__PHYB_RESERVED___M 0x00000C00 +#define PMM_TOP_WSI_MUX_SEL__PHYB_RESERVED___S 10 +#define PMM_TOP_WSI_MUX_SEL__USE_PHYB_WSI1___M 0x00000200 +#define PMM_TOP_WSI_MUX_SEL__USE_PHYB_WSI1___S 9 +#define PMM_TOP_WSI_MUX_SEL__USE_PHYB_WSI0___M 0x00000100 +#define PMM_TOP_WSI_MUX_SEL__USE_PHYB_WSI0___S 8 +#define PMM_TOP_WSI_MUX_SEL__PHYA_RESERVED___M 0x000000FC +#define PMM_TOP_WSI_MUX_SEL__PHYA_RESERVED___S 2 +#define PMM_TOP_WSI_MUX_SEL__USE_PHYA_WSI1___M 0x00000002 +#define PMM_TOP_WSI_MUX_SEL__USE_PHYA_WSI1___S 1 +#define PMM_TOP_WSI_MUX_SEL__USE_PHYA_WSI0___M 0x00000001 +#define PMM_TOP_WSI_MUX_SEL__USE_PHYA_WSI0___S 0 +#define PMM_TOP_WSI_MUX_SEL___M 0x00000FFF +#define PMM_TOP_WSI_MUX_SEL___S 0 + +#define PMM_TOP_WSIM_CTL (0x00B700EC) +#define PMM_TOP_WSIM_CTL___RWC QCSR_REG_RW +#define PMM_TOP_WSIM_CTL___POR 0x00003A00 +#define PMM_TOP_WSIM_CTL__WSI2M_DEBUG_WSI2M_STATE___POR 0x00 +#define PMM_TOP_WSIM_CTL__WSI2M_SYNCH_STATE___POR 0x0 +#define PMM_TOP_WSIM_CTL__WSI2M_SL_ASSERT_ASYNC___POR 0x0 +#define PMM_TOP_WSIM_CTL__WSI2M_SL_ASSERT___POR 0x0 +#define PMM_TOP_WSIM_CTL__WSI2M_DEBUG_RX_DVAL___POR 0x0 +#define PMM_TOP_WSIM_CTL__WSI2M_DEBUG_RX_DATA___POR 0x0 +#define PMM_TOP_WSIM_CTL__WSI2M_RESYNCH_REQ_STB___POR 0x0 +#define PMM_TOP_WSIM_CTL__WSI2M_CFG_RD_ACT___POR 0x0 +#define PMM_TOP_WSIM_CTL__WSI2M_CFG_PREAMBLE_DLY___POR 0x0 +#define PMM_TOP_WSIM_CTL__WSI2M_CFG_RD_DLY___POR 0x3 +#define PMM_TOP_WSIM_CTL__WSI2M_CFG_BP_LIMIT___POR 0xA +#define PMM_TOP_WSIM_CTL__WSI2M_DEBUG_IGNORE_ACK___POR 0x0 +#define PMM_TOP_WSIM_CTL__WSI2M_DEBUG_FORCE_ERROR___POR 0x0 +#define PMM_TOP_WSIM_CTL__WSI2M_CFG_SC_BEFORE_OTHER_CMDS___POR 0x0 +#define PMM_TOP_WSIM_CTL__WSI2M_CFG_SC_BEFORE_ALL_CMDS___POR 0x0 +#define PMM_TOP_WSIM_CTL__WSI2M_CFG_MONITOR_CMD___POR 0x0 +#define PMM_TOP_WSIM_CTL__WSI2M_CFG_DISABLE_WSI___POR 0x0 +#define PMM_TOP_WSIM_CTL__WSI2M_CFG_AUTO_SYNCH_MODE___POR 0x0 +#define PMM_TOP_WSIM_CTL__WSI2M_DEBUG_WSI2M_STATE___M 0x7C000000 +#define PMM_TOP_WSIM_CTL__WSI2M_DEBUG_WSI2M_STATE___S 26 +#define PMM_TOP_WSIM_CTL__WSI2M_SYNCH_STATE___M 0x02000000 +#define PMM_TOP_WSIM_CTL__WSI2M_SYNCH_STATE___S 25 +#define PMM_TOP_WSIM_CTL__WSI2M_SL_ASSERT_ASYNC___M 0x01000000 +#define PMM_TOP_WSIM_CTL__WSI2M_SL_ASSERT_ASYNC___S 24 +#define PMM_TOP_WSIM_CTL__WSI2M_SL_ASSERT___M 0x00800000 +#define PMM_TOP_WSIM_CTL__WSI2M_SL_ASSERT___S 23 +#define PMM_TOP_WSIM_CTL__WSI2M_DEBUG_RX_DVAL___M 0x00400000 +#define PMM_TOP_WSIM_CTL__WSI2M_DEBUG_RX_DVAL___S 22 +#define PMM_TOP_WSIM_CTL__WSI2M_DEBUG_RX_DATA___M 0x00200000 +#define PMM_TOP_WSIM_CTL__WSI2M_DEBUG_RX_DATA___S 21 +#define PMM_TOP_WSIM_CTL__WSI2M_RESYNCH_REQ_STB___M 0x00100000 +#define PMM_TOP_WSIM_CTL__WSI2M_RESYNCH_REQ_STB___S 20 +#define PMM_TOP_WSIM_CTL__WSI2M_CFG_RD_ACT___M 0x000C0000 +#define PMM_TOP_WSIM_CTL__WSI2M_CFG_RD_ACT___S 18 +#define PMM_TOP_WSIM_CTL__WSI2M_CFG_PREAMBLE_DLY___M 0x00030000 +#define PMM_TOP_WSIM_CTL__WSI2M_CFG_PREAMBLE_DLY___S 16 +#define PMM_TOP_WSIM_CTL__WSI2M_CFG_RD_DLY___M 0x0000F000 +#define PMM_TOP_WSIM_CTL__WSI2M_CFG_RD_DLY___S 12 +#define PMM_TOP_WSIM_CTL__WSI2M_CFG_BP_LIMIT___M 0x00000F00 +#define PMM_TOP_WSIM_CTL__WSI2M_CFG_BP_LIMIT___S 8 +#define PMM_TOP_WSIM_CTL__WSI2M_DEBUG_IGNORE_ACK___M 0x00000040 +#define PMM_TOP_WSIM_CTL__WSI2M_DEBUG_IGNORE_ACK___S 6 +#define PMM_TOP_WSIM_CTL__WSI2M_DEBUG_FORCE_ERROR___M 0x00000020 +#define PMM_TOP_WSIM_CTL__WSI2M_DEBUG_FORCE_ERROR___S 5 +#define PMM_TOP_WSIM_CTL__WSI2M_CFG_SC_BEFORE_OTHER_CMDS___M 0x00000010 +#define PMM_TOP_WSIM_CTL__WSI2M_CFG_SC_BEFORE_OTHER_CMDS___S 4 +#define PMM_TOP_WSIM_CTL__WSI2M_CFG_SC_BEFORE_ALL_CMDS___M 0x00000008 +#define PMM_TOP_WSIM_CTL__WSI2M_CFG_SC_BEFORE_ALL_CMDS___S 3 +#define PMM_TOP_WSIM_CTL__WSI2M_CFG_MONITOR_CMD___M 0x00000004 +#define PMM_TOP_WSIM_CTL__WSI2M_CFG_MONITOR_CMD___S 2 +#define PMM_TOP_WSIM_CTL__WSI2M_CFG_DISABLE_WSI___M 0x00000002 +#define PMM_TOP_WSIM_CTL__WSI2M_CFG_DISABLE_WSI___S 1 +#define PMM_TOP_WSIM_CTL__WSI2M_CFG_AUTO_SYNCH_MODE___M 0x00000001 +#define PMM_TOP_WSIM_CTL__WSI2M_CFG_AUTO_SYNCH_MODE___S 0 +#define PMM_TOP_WSIM_CTL___M 0x7FFFFF7F +#define PMM_TOP_WSIM_CTL___S 0 + +#define PMM_TOP_XO_DIS_ADDR (0x00B700F0) +#define PMM_TOP_XO_DIS_ADDR___RWC QCSR_REG_RW +#define PMM_TOP_XO_DIS_ADDR___POR 0x00000000 +#define PMM_TOP_XO_DIS_ADDR__XO_DIS_ADDR___POR 0x0000 +#define PMM_TOP_XO_DIS_ADDR__XO_DIS_ADDR___M 0x0000FFFF +#define PMM_TOP_XO_DIS_ADDR__XO_DIS_ADDR___S 0 +#define PMM_TOP_XO_DIS_ADDR___M 0x0000FFFF +#define PMM_TOP_XO_DIS_ADDR___S 0 + +#define PMM_TOP_XO_DIS_DATA (0x00B700F4) +#define PMM_TOP_XO_DIS_DATA___RWC QCSR_REG_RW +#define PMM_TOP_XO_DIS_DATA___POR 0x00000000 +#define PMM_TOP_XO_DIS_DATA__XO_DIS_DATA___POR 0x00000000 +#define PMM_TOP_XO_DIS_DATA__XO_DIS_DATA___M 0xFFFFFFFF +#define PMM_TOP_XO_DIS_DATA__XO_DIS_DATA___S 0 +#define PMM_TOP_XO_DIS_DATA___M 0xFFFFFFFF +#define PMM_TOP_XO_DIS_DATA___S 0 + +#define PMM_TOP_REG_RW_ADDR (0x00B700F8) +#define PMM_TOP_REG_RW_ADDR___RWC QCSR_REG_RW +#define PMM_TOP_REG_RW_ADDR___POR 0x00000000 +#define PMM_TOP_REG_RW_ADDR__SW_REG_RW_ADDR___POR 0x0000 +#define PMM_TOP_REG_RW_ADDR__SW_REG_RW_ADDR___M 0x0000FFFF +#define PMM_TOP_REG_RW_ADDR__SW_REG_RW_ADDR___S 0 +#define PMM_TOP_REG_RW_ADDR___M 0x0000FFFF +#define PMM_TOP_REG_RW_ADDR___S 0 + +#define PMM_TOP_REG_WRITE_DATA (0x00B700FC) +#define PMM_TOP_REG_WRITE_DATA___RWC QCSR_REG_RW +#define PMM_TOP_REG_WRITE_DATA___POR 0x00000000 +#define PMM_TOP_REG_WRITE_DATA__SW_REG_WR_DATA___POR 0x00000000 +#define PMM_TOP_REG_WRITE_DATA__SW_REG_WR_DATA___M 0xFFFFFFFF +#define PMM_TOP_REG_WRITE_DATA__SW_REG_WR_DATA___S 0 +#define PMM_TOP_REG_WRITE_DATA___M 0xFFFFFFFF +#define PMM_TOP_REG_WRITE_DATA___S 0 + +#define PMM_TOP_REG_READ_DATA (0x00B70100) +#define PMM_TOP_REG_READ_DATA___RWC QCSR_REG_RO +#define PMM_TOP_REG_READ_DATA___POR 0x00000000 +#define PMM_TOP_REG_READ_DATA__SW_REG_RD_DATA___POR 0x00000000 +#define PMM_TOP_REG_READ_DATA__SW_REG_RD_DATA___M 0xFFFFFFFF +#define PMM_TOP_REG_READ_DATA__SW_REG_RD_DATA___S 0 +#define PMM_TOP_REG_READ_DATA___M 0xFFFFFFFF +#define PMM_TOP_REG_READ_DATA___S 0 + +#define PMM_TOP_RF_VAULT_REG_ADDR (0x00B70104) +#define PMM_TOP_RF_VAULT_REG_ADDR___RWC QCSR_REG_RW +#define PMM_TOP_RF_VAULT_REG_ADDR___POR 0x00000000 +#define PMM_TOP_RF_VAULT_REG_ADDR__RF_VAULT_REG_ADDR___POR 0x0000 +#define PMM_TOP_RF_VAULT_REG_ADDR__RF_VAULT_REG_ADDR___M 0x0000FFFF +#define PMM_TOP_RF_VAULT_REG_ADDR__RF_VAULT_REG_ADDR___S 0 +#define PMM_TOP_RF_VAULT_REG_ADDR___M 0x0000FFFF +#define PMM_TOP_RF_VAULT_REG_ADDR___S 0 + +#define PMM_TOP_RF_VAULT_REG_DATA (0x00B70108) +#define PMM_TOP_RF_VAULT_REG_DATA___RWC QCSR_REG_RW +#define PMM_TOP_RF_VAULT_REG_DATA___POR 0x00000000 +#define PMM_TOP_RF_VAULT_REG_DATA__RF_VAULT_REG_DATA___POR 0x00000000 +#define PMM_TOP_RF_VAULT_REG_DATA__RF_VAULT_REG_DATA___M 0xFFFFFFFF +#define PMM_TOP_RF_VAULT_REG_DATA__RF_VAULT_REG_DATA___S 0 +#define PMM_TOP_RF_VAULT_REG_DATA___M 0xFFFFFFFF +#define PMM_TOP_RF_VAULT_REG_DATA___S 0 + +#define PMM_TOP_RF_RESET_ADDR (0x00B7010C) +#define PMM_TOP_RF_RESET_ADDR___RWC QCSR_REG_RW +#define PMM_TOP_RF_RESET_ADDR___POR 0x00000000 +#define PMM_TOP_RF_RESET_ADDR__RF_RESET_ADDR___POR 0x0000 +#define PMM_TOP_RF_RESET_ADDR__RF_RESET_ADDR___M 0x0000FFFF +#define PMM_TOP_RF_RESET_ADDR__RF_RESET_ADDR___S 0 +#define PMM_TOP_RF_RESET_ADDR___M 0x0000FFFF +#define PMM_TOP_RF_RESET_ADDR___S 0 + +#define PMM_TOP_RF_RESET_DATA (0x00B70110) +#define PMM_TOP_RF_RESET_DATA___RWC QCSR_REG_RW +#define PMM_TOP_RF_RESET_DATA___POR 0x00000000 +#define PMM_TOP_RF_RESET_DATA__RF_RESET_DATA___POR 0x00000000 +#define PMM_TOP_RF_RESET_DATA__RF_RESET_DATA___M 0xFFFFFFFF +#define PMM_TOP_RF_RESET_DATA__RF_RESET_DATA___S 0 +#define PMM_TOP_RF_RESET_DATA___M 0xFFFFFFFF +#define PMM_TOP_RF_RESET_DATA___S 0 + +#define PMM_TOP_SW_SCRATCH (0x00B70114) +#define PMM_TOP_SW_SCRATCH___RWC QCSR_REG_RW +#define PMM_TOP_SW_SCRATCH___POR 0x00000000 +#define PMM_TOP_SW_SCRATCH__SCRATCH___POR 0x00000000 +#define PMM_TOP_SW_SCRATCH__SCRATCH___M 0xFFFFFFFF +#define PMM_TOP_SW_SCRATCH__SCRATCH___S 0 +#define PMM_TOP_SW_SCRATCH___M 0xFFFFFFFF +#define PMM_TOP_SW_SCRATCH___S 0 + +#define PMM_TOP_SW_SLP_TMR_CTL (0x00B70118) +#define PMM_TOP_SW_SLP_TMR_CTL___RWC QCSR_REG_RW +#define PMM_TOP_SW_SLP_TMR_CTL___POR 0x00000001 +#define PMM_TOP_SW_SLP_TMR_CTL__SW_SLP_TMR_INT_CLR___POR 0x0 +#define PMM_TOP_SW_SLP_TMR_CTL__SW_SLP_TMR_EN___POR 0x1 +#define PMM_TOP_SW_SLP_TMR_CTL__SW_SLP_TMR_INT_CLR___M 0x00000002 +#define PMM_TOP_SW_SLP_TMR_CTL__SW_SLP_TMR_INT_CLR___S 1 +#define PMM_TOP_SW_SLP_TMR_CTL__SW_SLP_TMR_EN___M 0x00000001 +#define PMM_TOP_SW_SLP_TMR_CTL__SW_SLP_TMR_EN___S 0 +#define PMM_TOP_SW_SLP_TMR_CTL___M 0x00000003 +#define PMM_TOP_SW_SLP_TMR_CTL___S 0 + +#define PMM_TOP_SW_SLP_TMR_STS (0x00B7011C) +#define PMM_TOP_SW_SLP_TMR_STS___RWC QCSR_REG_RO +#define PMM_TOP_SW_SLP_TMR_STS___POR 0x00000000 +#define PMM_TOP_SW_SLP_TMR_STS__SW_SLP_TMR_INT___POR 0x0 +#define PMM_TOP_SW_SLP_TMR_STS__SW_SLP_TMR_INT_RAW___POR 0x0 +#define PMM_TOP_SW_SLP_TMR_STS__SW_SLP_TMR_INT___M 0x00000002 +#define PMM_TOP_SW_SLP_TMR_STS__SW_SLP_TMR_INT___S 1 +#define PMM_TOP_SW_SLP_TMR_STS__SW_SLP_TMR_INT_RAW___M 0x00000001 +#define PMM_TOP_SW_SLP_TMR_STS__SW_SLP_TMR_INT_RAW___S 0 +#define PMM_TOP_SW_SLP_TMR_STS___M 0x00000003 +#define PMM_TOP_SW_SLP_TMR_STS___S 0 + +#define PMM_TOP_SW_SLP_TMR_EXP_LO (0x00B70120) +#define PMM_TOP_SW_SLP_TMR_EXP_LO___RWC QCSR_REG_RW +#define PMM_TOP_SW_SLP_TMR_EXP_LO___POR 0xFFFFFFFF +#define PMM_TOP_SW_SLP_TMR_EXP_LO__SW_SLP_TMR_EXP___POR 0xFFFFFFFF +#define PMM_TOP_SW_SLP_TMR_EXP_LO__SW_SLP_TMR_EXP___M 0xFFFFFFFF +#define PMM_TOP_SW_SLP_TMR_EXP_LO__SW_SLP_TMR_EXP___S 0 +#define PMM_TOP_SW_SLP_TMR_EXP_LO___M 0xFFFFFFFF +#define PMM_TOP_SW_SLP_TMR_EXP_LO___S 0 + +#define PMM_TOP_SW_SLP_TMR_EXP_HI (0x00B70124) +#define PMM_TOP_SW_SLP_TMR_EXP_HI___RWC QCSR_REG_RW +#define PMM_TOP_SW_SLP_TMR_EXP_HI___POR 0x00000000 +#define PMM_TOP_SW_SLP_TMR_EXP_HI__SW_SLP_TMR_EXP___POR 0x0000 +#define PMM_TOP_SW_SLP_TMR_EXP_HI__SW_SLP_TMR_EXP___M 0x0000FFFF +#define PMM_TOP_SW_SLP_TMR_EXP_HI__SW_SLP_TMR_EXP___S 0 +#define PMM_TOP_SW_SLP_TMR_EXP_HI___M 0x0000FFFF +#define PMM_TOP_SW_SLP_TMR_EXP_HI___S 0 + +#define PMM_TOP_COMMON_IDLEREQ_CSR (0x00B70128) +#define PMM_TOP_COMMON_IDLEREQ_CSR___RWC QCSR_REG_RW +#define PMM_TOP_COMMON_IDLEREQ_CSR___POR 0x10000102 +#define PMM_TOP_COMMON_IDLEREQ_CSR__SNOC_PWRDISC_SOCKETCONN___POR 0x1 +#define PMM_TOP_COMMON_IDLEREQ_CSR__WNOC_IDLE___POR 0x0 +#define PMM_TOP_COMMON_IDLEREQ_CSR__WNOC_IDLETACK___POR 0x0 +#define PMM_TOP_COMMON_IDLEREQ_CSR__WNOC_IDLETREQ___POR 0x0 +#define PMM_TOP_COMMON_IDLEREQ_CSR__SW_WNOC_IDLEREQ_CLR___POR 0x0 +#define PMM_TOP_COMMON_IDLEREQ_CSR__SW_WNOC_IDLEREQ_SET___POR 0x0 +#define PMM_TOP_COMMON_IDLEREQ_CSR__SNOC_PWRDISC_SLVRDY___POR 0x1 +#define PMM_TOP_COMMON_IDLEREQ_CSR__ENABLE_WNOC_IDLEREQ___POR 0x1 +#define PMM_TOP_COMMON_IDLEREQ_CSR__SNOC_PWRDISC_SOCKETCONN___M 0x10000000 +#define PMM_TOP_COMMON_IDLEREQ_CSR__SNOC_PWRDISC_SOCKETCONN___S 28 +#define PMM_TOP_COMMON_IDLEREQ_CSR__WNOC_IDLE___M 0x08000000 +#define PMM_TOP_COMMON_IDLEREQ_CSR__WNOC_IDLE___S 27 +#define PMM_TOP_COMMON_IDLEREQ_CSR__WNOC_IDLETACK___M 0x04000000 +#define PMM_TOP_COMMON_IDLEREQ_CSR__WNOC_IDLETACK___S 26 +#define PMM_TOP_COMMON_IDLEREQ_CSR__WNOC_IDLETREQ___M 0x02000000 +#define PMM_TOP_COMMON_IDLEREQ_CSR__WNOC_IDLETREQ___S 25 +#define PMM_TOP_COMMON_IDLEREQ_CSR__SW_WNOC_IDLEREQ_CLR___M 0x00020000 +#define PMM_TOP_COMMON_IDLEREQ_CSR__SW_WNOC_IDLEREQ_CLR___S 17 +#define PMM_TOP_COMMON_IDLEREQ_CSR__SW_WNOC_IDLEREQ_SET___M 0x00010000 +#define PMM_TOP_COMMON_IDLEREQ_CSR__SW_WNOC_IDLEREQ_SET___S 16 +#define PMM_TOP_COMMON_IDLEREQ_CSR__SNOC_PWRDISC_SLVRDY___M 0x00000100 +#define PMM_TOP_COMMON_IDLEREQ_CSR__SNOC_PWRDISC_SLVRDY___S 8 +#define PMM_TOP_COMMON_IDLEREQ_CSR__ENABLE_WNOC_IDLEREQ___M 0x00000002 +#define PMM_TOP_COMMON_IDLEREQ_CSR__ENABLE_WNOC_IDLEREQ___S 1 +#define PMM_TOP_COMMON_IDLEREQ_CSR___M 0x1E030102 +#define PMM_TOP_COMMON_IDLEREQ_CSR___S 1 + +#define PMM_TOP_NAV_BLANK_CTL (0x00B7012C) +#define PMM_TOP_NAV_BLANK_CTL___RWC QCSR_REG_RW +#define PMM_TOP_NAV_BLANK_CTL___POR 0x00000000 +#define PMM_TOP_NAV_BLANK_CTL__NAV_BLANK_5G_SEL___POR 0x0 +#define PMM_TOP_NAV_BLANK_CTL__NAV_BLANK_5G_EN___POR 0x0 +#define PMM_TOP_NAV_BLANK_CTL__NAV_BLANK_2G_SEL___POR 0x0 +#define PMM_TOP_NAV_BLANK_CTL__NAV_BLANK_2G_EN___POR 0x0 +#define PMM_TOP_NAV_BLANK_CTL__NAV_BLANK_5G_SEL___M 0x00000200 +#define PMM_TOP_NAV_BLANK_CTL__NAV_BLANK_5G_SEL___S 9 +#define PMM_TOP_NAV_BLANK_CTL__NAV_BLANK_5G_EN___M 0x00000100 +#define PMM_TOP_NAV_BLANK_CTL__NAV_BLANK_5G_EN___S 8 +#define PMM_TOP_NAV_BLANK_CTL__NAV_BLANK_2G_SEL___M 0x00000002 +#define PMM_TOP_NAV_BLANK_CTL__NAV_BLANK_2G_SEL___S 1 +#define PMM_TOP_NAV_BLANK_CTL__NAV_BLANK_2G_EN___M 0x00000001 +#define PMM_TOP_NAV_BLANK_CTL__NAV_BLANK_2G_EN___S 0 +#define PMM_TOP_NAV_BLANK_CTL___M 0x00000303 +#define PMM_TOP_NAV_BLANK_CTL___S 0 + +#define PMM_TOP_GPIO_PWR_CSR (0x00B70130) +#define PMM_TOP_GPIO_PWR_CSR___RWC QCSR_REG_RW +#define PMM_TOP_GPIO_PWR_CSR___POR 0x00000000 +#define PMM_TOP_GPIO_PWR_CSR__PMM_CX_SLEEP_MSK___POR 0x0 +#define PMM_TOP_GPIO_PWR_CSR__PMM_CX_RESERVED3___POR 0x0 +#define PMM_TOP_GPIO_PWR_CSR__PMM_CX_PLL_DISABLE_MSK___POR 0x0 +#define PMM_TOP_GPIO_PWR_CSR__PMM_CX_RESERVED2___POR 0x0 +#define PMM_TOP_GPIO_PWR_CSR__PMM_CX_DETECT_PLL_LOCK_MSK___POR 0x0 +#define PMM_TOP_GPIO_PWR_CSR__PMM_CX_ENABLE_PLL_MSK___POR 0x0 +#define PMM_TOP_GPIO_PWR_CSR__PMM_CX_RESERVED1___POR 0x0 +#define PMM_TOP_GPIO_PWR_CSR__PMM_CX_GET_WAKEUP_INT_MSK___POR 0x0 +#define PMM_TOP_GPIO_PWR_CSR__USE_COEX_WSI_DATA_EN___POR 0x0 +#define PMM_TOP_GPIO_PWR_CSR__PMM_CX_SLEEP_MSK___M 0x00800000 +#define PMM_TOP_GPIO_PWR_CSR__PMM_CX_SLEEP_MSK___S 23 +#define PMM_TOP_GPIO_PWR_CSR__PMM_CX_RESERVED3___M 0x00400000 +#define PMM_TOP_GPIO_PWR_CSR__PMM_CX_RESERVED3___S 22 +#define PMM_TOP_GPIO_PWR_CSR__PMM_CX_PLL_DISABLE_MSK___M 0x00200000 +#define PMM_TOP_GPIO_PWR_CSR__PMM_CX_PLL_DISABLE_MSK___S 21 +#define PMM_TOP_GPIO_PWR_CSR__PMM_CX_RESERVED2___M 0x00100000 +#define PMM_TOP_GPIO_PWR_CSR__PMM_CX_RESERVED2___S 20 +#define PMM_TOP_GPIO_PWR_CSR__PMM_CX_DETECT_PLL_LOCK_MSK___M 0x00080000 +#define PMM_TOP_GPIO_PWR_CSR__PMM_CX_DETECT_PLL_LOCK_MSK___S 19 +#define PMM_TOP_GPIO_PWR_CSR__PMM_CX_ENABLE_PLL_MSK___M 0x00040000 +#define PMM_TOP_GPIO_PWR_CSR__PMM_CX_ENABLE_PLL_MSK___S 18 +#define PMM_TOP_GPIO_PWR_CSR__PMM_CX_RESERVED1___M 0x00020000 +#define PMM_TOP_GPIO_PWR_CSR__PMM_CX_RESERVED1___S 17 +#define PMM_TOP_GPIO_PWR_CSR__PMM_CX_GET_WAKEUP_INT_MSK___M 0x00010000 +#define PMM_TOP_GPIO_PWR_CSR__PMM_CX_GET_WAKEUP_INT_MSK___S 16 +#define PMM_TOP_GPIO_PWR_CSR__USE_COEX_WSI_DATA_EN___M 0x00000001 +#define PMM_TOP_GPIO_PWR_CSR__USE_COEX_WSI_DATA_EN___S 0 +#define PMM_TOP_GPIO_PWR_CSR___M 0x00FF0001 +#define PMM_TOP_GPIO_PWR_CSR___S 0 + +#define PMM_TOP_DBG_CSR (0x00B70160) +#define PMM_TOP_DBG_CSR___RWC QCSR_REG_RW +#define PMM_TOP_DBG_CSR___POR 0x0000005C +#define PMM_TOP_DBG_CSR__AON_DBG_FIFO_EMPTY_AHB___POR 0x1 +#define PMM_TOP_DBG_CSR__AON_DBG_FIFO_FULL_AHB___POR 0x0 +#define PMM_TOP_DBG_CSR__CSYSACK___POR 0x1 +#define PMM_TOP_DBG_CSR__CACTIVE___POR 0x1 +#define PMM_TOP_DBG_CSR__CSYSREQ___POR 0x1 +#define PMM_TOP_DBG_CSR__SW_CSYSREQ_CLR___POR 0x0 +#define PMM_TOP_DBG_CSR__SW_CSYSREQ_SET___POR 0x0 +#define PMM_TOP_DBG_CSR__AON_DBG_FIFO_EMPTY_AHB___M 0x00000040 +#define PMM_TOP_DBG_CSR__AON_DBG_FIFO_EMPTY_AHB___S 6 +#define PMM_TOP_DBG_CSR__AON_DBG_FIFO_FULL_AHB___M 0x00000020 +#define PMM_TOP_DBG_CSR__AON_DBG_FIFO_FULL_AHB___S 5 +#define PMM_TOP_DBG_CSR__CSYSACK___M 0x00000010 +#define PMM_TOP_DBG_CSR__CSYSACK___S 4 +#define PMM_TOP_DBG_CSR__CACTIVE___M 0x00000008 +#define PMM_TOP_DBG_CSR__CACTIVE___S 3 +#define PMM_TOP_DBG_CSR__CSYSREQ___M 0x00000004 +#define PMM_TOP_DBG_CSR__CSYSREQ___S 2 +#define PMM_TOP_DBG_CSR__SW_CSYSREQ_CLR___M 0x00000002 +#define PMM_TOP_DBG_CSR__SW_CSYSREQ_CLR___S 1 +#define PMM_TOP_DBG_CSR__SW_CSYSREQ_SET___M 0x00000001 +#define PMM_TOP_DBG_CSR__SW_CSYSREQ_SET___S 0 +#define PMM_TOP_DBG_CSR___M 0x0000007F +#define PMM_TOP_DBG_CSR___S 0 + +#define PMM_TOP_PMM_INT_STAT (0x00B70164) +#define PMM_TOP_PMM_INT_STAT___RWC QCSR_REG_RO +#define PMM_TOP_PMM_INT_STAT___POR 0x00000000 +#define PMM_TOP_PMM_INT_STAT__WAKEUP_IRQ_ACK_INTR___POR 0x0 +#define PMM_TOP_PMM_INT_STAT__WAKEUP_IRQ_ACK_INTR___M 0x00000001 +#define PMM_TOP_PMM_INT_STAT__WAKEUP_IRQ_ACK_INTR___S 0 +#define PMM_TOP_PMM_INT_STAT___M 0x00000001 +#define PMM_TOP_PMM_INT_STAT___S 0 + +#define PMM_TOP_PMM_INT_CLR (0x00B70168) +#define PMM_TOP_PMM_INT_CLR___RWC QCSR_REG_WO +#define PMM_TOP_PMM_INT_CLR___POR 0x00000000 +#define PMM_TOP_PMM_INT_CLR__WAKEUP_IRQ_STICKY___POR 0x0 +#define PMM_TOP_PMM_INT_CLR__WAKEUP_IRQ_ACK_INTR_CLR___POR 0x0 +#define PMM_TOP_PMM_INT_CLR__WAKEUP_IRQ_STICKY___M 0x00000002 +#define PMM_TOP_PMM_INT_CLR__WAKEUP_IRQ_STICKY___S 1 +#define PMM_TOP_PMM_INT_CLR__WAKEUP_IRQ_ACK_INTR_CLR___M 0x00000001 +#define PMM_TOP_PMM_INT_CLR__WAKEUP_IRQ_ACK_INTR_CLR___S 0 +#define PMM_TOP_PMM_INT_CLR___M 0x00000003 +#define PMM_TOP_PMM_INT_CLR___S 0 + +#define PMM_TOP_SNOC_IDLEREQ_CSR (0x00B7016C) +#define PMM_TOP_SNOC_IDLEREQ_CSR___RWC QCSR_REG_RW +#define PMM_TOP_SNOC_IDLEREQ_CSR___POR 0x00000000 +#define PMM_TOP_SNOC_IDLEREQ_CSR__WNOC_PMM_IDLE___POR 0x0 +#define PMM_TOP_SNOC_IDLEREQ_CSR__WNOC_PMM_IDLEACK___POR 0x0 +#define PMM_TOP_SNOC_IDLEREQ_CSR__PMM_WNOC_IDLEREQ___POR 0x0 +#define PMM_TOP_SNOC_IDLEREQ_CSR__WNOC_PMM_IDLE___M 0x00000004 +#define PMM_TOP_SNOC_IDLEREQ_CSR__WNOC_PMM_IDLE___S 2 +#define PMM_TOP_SNOC_IDLEREQ_CSR__WNOC_PMM_IDLEACK___M 0x00000002 +#define PMM_TOP_SNOC_IDLEREQ_CSR__WNOC_PMM_IDLEACK___S 1 +#define PMM_TOP_SNOC_IDLEREQ_CSR__PMM_WNOC_IDLEREQ___M 0x00000001 +#define PMM_TOP_SNOC_IDLEREQ_CSR__PMM_WNOC_IDLEREQ___S 0 +#define PMM_TOP_SNOC_IDLEREQ_CSR___M 0x00000007 +#define PMM_TOP_SNOC_IDLEREQ_CSR___S 0 + +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL (0x00B70170) +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL___RWC QCSR_REG_RW +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL___POR 0x00000000 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__SEL_EXTCLK___POR 0x0 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__PLLBYPASS___POR 0x0 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL2_CLKGEN_HW_CTL_DIS___POR 0x0 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL2_CLK_EN___POR 0x0 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL2_CLKGEN_SW_RESET___POR 0x0 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL2_CLK_EN_CLR___POR 0x0 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL2_CLK_EN_SET___POR 0x0 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL1_CLKGEN_HW_CTL_DIS___POR 0x0 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL1_CLK_EN___POR 0x0 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL1_CLKGEN_SW_RESET___POR 0x0 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL1_CLK_EN_CLR___POR 0x0 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL1_CLK_EN_SET___POR 0x0 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__SEL_EXTCLK___M 0x00020000 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__SEL_EXTCLK___S 17 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__PLLBYPASS___M 0x00010000 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__PLLBYPASS___S 16 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL2_CLKGEN_HW_CTL_DIS___M 0x00001000 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL2_CLKGEN_HW_CTL_DIS___S 12 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL2_CLK_EN___M 0x00000800 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL2_CLK_EN___S 11 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL2_CLKGEN_SW_RESET___M 0x00000400 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL2_CLKGEN_SW_RESET___S 10 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL2_CLK_EN_CLR___M 0x00000200 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL2_CLK_EN_CLR___S 9 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL2_CLK_EN_SET___M 0x00000100 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL2_CLK_EN_SET___S 8 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL1_CLKGEN_HW_CTL_DIS___M 0x00000010 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL1_CLKGEN_HW_CTL_DIS___S 4 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL1_CLK_EN___M 0x00000008 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL1_CLK_EN___S 3 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL1_CLKGEN_SW_RESET___M 0x00000004 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL1_CLKGEN_SW_RESET___S 2 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL1_CLK_EN_CLR___M 0x00000002 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL1_CLK_EN_CLR___S 1 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL1_CLK_EN_SET___M 0x00000001 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL__WL1_CLK_EN_SET___S 0 +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL___M 0x00031F1F +#define PMM_TOP_WLAN_TOP_CLKGEN_CTL___S 0 + +#define PMM_TOP_WLAN1_SLP_TMR_CTL (0x00B70180) +#define PMM_TOP_WLAN1_SLP_TMR_CTL___RWC QCSR_REG_RW +#define PMM_TOP_WLAN1_SLP_TMR_CTL___POR 0x00000001 +#define PMM_TOP_WLAN1_SLP_TMR_CTL__WLAN_SLP_TMR_INT_CLR___POR 0x0 +#define PMM_TOP_WLAN1_SLP_TMR_CTL__WLAN_SLP_TMR_EN___POR 0x1 +#define PMM_TOP_WLAN1_SLP_TMR_CTL__WLAN_SLP_TMR_INT_CLR___M 0x00000002 +#define PMM_TOP_WLAN1_SLP_TMR_CTL__WLAN_SLP_TMR_INT_CLR___S 1 +#define PMM_TOP_WLAN1_SLP_TMR_CTL__WLAN_SLP_TMR_EN___M 0x00000001 +#define PMM_TOP_WLAN1_SLP_TMR_CTL__WLAN_SLP_TMR_EN___S 0 +#define PMM_TOP_WLAN1_SLP_TMR_CTL___M 0x00000003 +#define PMM_TOP_WLAN1_SLP_TMR_CTL___S 0 + +#define PMM_TOP_WLAN1_SLP_TMR_STS (0x00B70184) +#define PMM_TOP_WLAN1_SLP_TMR_STS___RWC QCSR_REG_RO +#define PMM_TOP_WLAN1_SLP_TMR_STS___POR 0x00000000 +#define PMM_TOP_WLAN1_SLP_TMR_STS__WLAN_SLP_TMR_INT___POR 0x0 +#define PMM_TOP_WLAN1_SLP_TMR_STS__WLAN_SLP_TMR_INT_RAW___POR 0x0 +#define PMM_TOP_WLAN1_SLP_TMR_STS__WLAN_SLP_TMR_INT___M 0x00000002 +#define PMM_TOP_WLAN1_SLP_TMR_STS__WLAN_SLP_TMR_INT___S 1 +#define PMM_TOP_WLAN1_SLP_TMR_STS__WLAN_SLP_TMR_INT_RAW___M 0x00000001 +#define PMM_TOP_WLAN1_SLP_TMR_STS__WLAN_SLP_TMR_INT_RAW___S 0 +#define PMM_TOP_WLAN1_SLP_TMR_STS___M 0x00000003 +#define PMM_TOP_WLAN1_SLP_TMR_STS___S 0 + +#define PMM_TOP_WLAN1_SLP_TMR_EXP_LO (0x00B70188) +#define PMM_TOP_WLAN1_SLP_TMR_EXP_LO___RWC QCSR_REG_RW +#define PMM_TOP_WLAN1_SLP_TMR_EXP_LO___POR 0xFFFFFFFF +#define PMM_TOP_WLAN1_SLP_TMR_EXP_LO__WLAN_SLP_TMR_EXP___POR 0xFFFFFFFF +#define PMM_TOP_WLAN1_SLP_TMR_EXP_LO__WLAN_SLP_TMR_EXP___M 0xFFFFFFFF +#define PMM_TOP_WLAN1_SLP_TMR_EXP_LO__WLAN_SLP_TMR_EXP___S 0 +#define PMM_TOP_WLAN1_SLP_TMR_EXP_LO___M 0xFFFFFFFF +#define PMM_TOP_WLAN1_SLP_TMR_EXP_LO___S 0 + +#define PMM_TOP_WLAN1_SLP_TMR_EXP_HI (0x00B7018C) +#define PMM_TOP_WLAN1_SLP_TMR_EXP_HI___RWC QCSR_REG_RW +#define PMM_TOP_WLAN1_SLP_TMR_EXP_HI___POR 0x00000000 +#define PMM_TOP_WLAN1_SLP_TMR_EXP_HI__WLAN_SLP_TMR_EXP___POR 0x0000 +#define PMM_TOP_WLAN1_SLP_TMR_EXP_HI__WLAN_SLP_TMR_EXP___M 0x0000FFFF +#define PMM_TOP_WLAN1_SLP_TMR_EXP_HI__WLAN_SLP_TMR_EXP___S 0 +#define PMM_TOP_WLAN1_SLP_TMR_EXP_HI___M 0x0000FFFF +#define PMM_TOP_WLAN1_SLP_TMR_EXP_HI___S 0 + +#define PMM_TOP_WLAN1_GPIO_PWR_MSK (0x00B70190) +#define PMM_TOP_WLAN1_GPIO_PWR_MSK___RWC QCSR_REG_RW +#define PMM_TOP_WLAN1_GPIO_PWR_MSK___POR 0x000000FF +#define PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_RESERVED___POR 0x1 +#define PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_OFF_STS_MSK___POR 0x1 +#define PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_OFF_REQ_MSK___POR 0x1 +#define PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_RX_BEACON_END_MSK___POR 0x1 +#define PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_RX_BEACON_START_MSK___POR 0x1 +#define PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_RRI_DONE_MSK___POR 0x1 +#define PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_START_RRI_MSK___POR 0x1 +#define PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_ENABLE_MSK___POR 0x1 +#define PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_RESERVED___M 0x00000080 +#define PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_RESERVED___S 7 +#define PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_OFF_STS_MSK___M 0x00000040 +#define PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_OFF_STS_MSK___S 6 +#define PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_OFF_REQ_MSK___M 0x00000020 +#define PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_OFF_REQ_MSK___S 5 +#define PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_RX_BEACON_END_MSK___M 0x00000010 +#define PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_RX_BEACON_END_MSK___S 4 +#define PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_RX_BEACON_START_MSK___M 0x00000008 +#define PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_RX_BEACON_START_MSK___S 3 +#define PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_RRI_DONE_MSK___M 0x00000004 +#define PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_RRI_DONE_MSK___S 2 +#define PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_START_RRI_MSK___M 0x00000002 +#define PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_START_RRI_MSK___S 1 +#define PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_ENABLE_MSK___M 0x00000001 +#define PMM_TOP_WLAN1_GPIO_PWR_MSK__PMM_WLAN_ENABLE_MSK___S 0 +#define PMM_TOP_WLAN1_GPIO_PWR_MSK___M 0x000000FF +#define PMM_TOP_WLAN1_GPIO_PWR_MSK___S 0 + +#define PMM_TOP_WLAN2_SLP_TMR_CTL (0x00B7019C) +#define PMM_TOP_WLAN2_SLP_TMR_CTL___RWC QCSR_REG_RW +#define PMM_TOP_WLAN2_SLP_TMR_CTL___POR 0x00000001 +#define PMM_TOP_WLAN2_SLP_TMR_CTL__WLAN_SLP_TMR_INT_CLR___POR 0x0 +#define PMM_TOP_WLAN2_SLP_TMR_CTL__WLAN_SLP_TMR_EN___POR 0x1 +#define PMM_TOP_WLAN2_SLP_TMR_CTL__WLAN_SLP_TMR_INT_CLR___M 0x00000002 +#define PMM_TOP_WLAN2_SLP_TMR_CTL__WLAN_SLP_TMR_INT_CLR___S 1 +#define PMM_TOP_WLAN2_SLP_TMR_CTL__WLAN_SLP_TMR_EN___M 0x00000001 +#define PMM_TOP_WLAN2_SLP_TMR_CTL__WLAN_SLP_TMR_EN___S 0 +#define PMM_TOP_WLAN2_SLP_TMR_CTL___M 0x00000003 +#define PMM_TOP_WLAN2_SLP_TMR_CTL___S 0 + +#define PMM_TOP_WLAN2_SLP_TMR_STS (0x00B701A0) +#define PMM_TOP_WLAN2_SLP_TMR_STS___RWC QCSR_REG_RO +#define PMM_TOP_WLAN2_SLP_TMR_STS___POR 0x00000000 +#define PMM_TOP_WLAN2_SLP_TMR_STS__WLAN_SLP_TMR_INT___POR 0x0 +#define PMM_TOP_WLAN2_SLP_TMR_STS__WLAN_SLP_TMR_INT_RAW___POR 0x0 +#define PMM_TOP_WLAN2_SLP_TMR_STS__WLAN_SLP_TMR_INT___M 0x00000002 +#define PMM_TOP_WLAN2_SLP_TMR_STS__WLAN_SLP_TMR_INT___S 1 +#define PMM_TOP_WLAN2_SLP_TMR_STS__WLAN_SLP_TMR_INT_RAW___M 0x00000001 +#define PMM_TOP_WLAN2_SLP_TMR_STS__WLAN_SLP_TMR_INT_RAW___S 0 +#define PMM_TOP_WLAN2_SLP_TMR_STS___M 0x00000003 +#define PMM_TOP_WLAN2_SLP_TMR_STS___S 0 + +#define PMM_TOP_WLAN2_SLP_TMR_EXP_LO (0x00B701A4) +#define PMM_TOP_WLAN2_SLP_TMR_EXP_LO___RWC QCSR_REG_RW +#define PMM_TOP_WLAN2_SLP_TMR_EXP_LO___POR 0x00000000 +#define PMM_TOP_WLAN2_SLP_TMR_EXP_LO__WLAN_SLP_TMR_EXP___POR 0x00000000 +#define PMM_TOP_WLAN2_SLP_TMR_EXP_LO__WLAN_SLP_TMR_EXP___M 0xFFFFFFFF +#define PMM_TOP_WLAN2_SLP_TMR_EXP_LO__WLAN_SLP_TMR_EXP___S 0 +#define PMM_TOP_WLAN2_SLP_TMR_EXP_LO___M 0xFFFFFFFF +#define PMM_TOP_WLAN2_SLP_TMR_EXP_LO___S 0 + +#define PMM_TOP_WLAN2_SLP_TMR_EXP_HI (0x00B701A8) +#define PMM_TOP_WLAN2_SLP_TMR_EXP_HI___RWC QCSR_REG_RW +#define PMM_TOP_WLAN2_SLP_TMR_EXP_HI___POR 0x00000000 +#define PMM_TOP_WLAN2_SLP_TMR_EXP_HI__WLAN_SLP_TMR_EXP___POR 0x0000 +#define PMM_TOP_WLAN2_SLP_TMR_EXP_HI__WLAN_SLP_TMR_EXP___M 0x0000FFFF +#define PMM_TOP_WLAN2_SLP_TMR_EXP_HI__WLAN_SLP_TMR_EXP___S 0 +#define PMM_TOP_WLAN2_SLP_TMR_EXP_HI___M 0x0000FFFF +#define PMM_TOP_WLAN2_SLP_TMR_EXP_HI___S 0 + +#define PMM_TOP_WLAN2_GPIO_PWR_MSK (0x00B701AC) +#define PMM_TOP_WLAN2_GPIO_PWR_MSK___RWC QCSR_REG_RW +#define PMM_TOP_WLAN2_GPIO_PWR_MSK___POR 0x000000FF +#define PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_RESERVED___POR 0x1 +#define PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_OFF_STS_MSK___POR 0x1 +#define PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_OFF_REQ_MSK___POR 0x1 +#define PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_RX_BEACON_END_MSK___POR 0x1 +#define PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_RX_BEACON_START_MSK___POR 0x1 +#define PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_RRI_DONE_MSK___POR 0x1 +#define PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_START_RRI_MSK___POR 0x1 +#define PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_ENABLE_MSK___POR 0x1 +#define PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_RESERVED___M 0x00000080 +#define PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_RESERVED___S 7 +#define PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_OFF_STS_MSK___M 0x00000040 +#define PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_OFF_STS_MSK___S 6 +#define PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_OFF_REQ_MSK___M 0x00000020 +#define PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_OFF_REQ_MSK___S 5 +#define PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_RX_BEACON_END_MSK___M 0x00000010 +#define PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_RX_BEACON_END_MSK___S 4 +#define PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_RX_BEACON_START_MSK___M 0x00000008 +#define PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_RX_BEACON_START_MSK___S 3 +#define PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_RRI_DONE_MSK___M 0x00000004 +#define PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_RRI_DONE_MSK___S 2 +#define PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_START_RRI_MSK___M 0x00000002 +#define PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_START_RRI_MSK___S 1 +#define PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_ENABLE_MSK___M 0x00000001 +#define PMM_TOP_WLAN2_GPIO_PWR_MSK__PMM_WLAN_ENABLE_MSK___S 0 +#define PMM_TOP_WLAN2_GPIO_PWR_MSK___M 0x000000FF +#define PMM_TOP_WLAN2_GPIO_PWR_MSK___S 0 + +#define PMM_TOP_WCSS_DAC_ACSCAN_960_CMD_RCGR (0x00B701B8) +#define PMM_TOP_WCSS_DAC_ACSCAN_960_CMD_RCGR___RWC QCSR_REG_RW +#define PMM_TOP_WCSS_DAC_ACSCAN_960_CMD_RCGR___POR 0x00000000 +#define PMM_TOP_WCSS_DAC_ACSCAN_960_CMD_RCGR__ROOT_OFF___POR 0x0 +#define PMM_TOP_WCSS_DAC_ACSCAN_960_CMD_RCGR__DIRTY_CFG_RCGR___POR 0x0 +#define PMM_TOP_WCSS_DAC_ACSCAN_960_CMD_RCGR__ROOT_EN___POR 0x0 +#define PMM_TOP_WCSS_DAC_ACSCAN_960_CMD_RCGR__UPDATE___POR 0x0 +#define PMM_TOP_WCSS_DAC_ACSCAN_960_CMD_RCGR__ROOT_OFF___M 0x80000000 +#define PMM_TOP_WCSS_DAC_ACSCAN_960_CMD_RCGR__ROOT_OFF___S 31 +#define PMM_TOP_WCSS_DAC_ACSCAN_960_CMD_RCGR__DIRTY_CFG_RCGR___M 0x00000010 +#define PMM_TOP_WCSS_DAC_ACSCAN_960_CMD_RCGR__DIRTY_CFG_RCGR___S 4 +#define PMM_TOP_WCSS_DAC_ACSCAN_960_CMD_RCGR__ROOT_EN___M 0x00000002 +#define PMM_TOP_WCSS_DAC_ACSCAN_960_CMD_RCGR__ROOT_EN___S 1 +#define PMM_TOP_WCSS_DAC_ACSCAN_960_CMD_RCGR__UPDATE___M 0x00000001 +#define PMM_TOP_WCSS_DAC_ACSCAN_960_CMD_RCGR__UPDATE___S 0 +#define PMM_TOP_WCSS_DAC_ACSCAN_960_CMD_RCGR___M 0x80000013 +#define PMM_TOP_WCSS_DAC_ACSCAN_960_CMD_RCGR___S 0 + +#define PMM_TOP_WCSS_DAC_ACSCAN_960_CFG_RCGR (0x00B701BC) +#define PMM_TOP_WCSS_DAC_ACSCAN_960_CFG_RCGR___RWC QCSR_REG_RW +#define PMM_TOP_WCSS_DAC_ACSCAN_960_CFG_RCGR___POR 0x00000000 +#define PMM_TOP_WCSS_DAC_ACSCAN_960_CFG_RCGR__SRC_SEL___POR 0x0 +#define PMM_TOP_WCSS_DAC_ACSCAN_960_CFG_RCGR__SRC_DIV___POR 0x00 +#define PMM_TOP_WCSS_DAC_ACSCAN_960_CFG_RCGR__SRC_SEL___M 0x00000700 +#define PMM_TOP_WCSS_DAC_ACSCAN_960_CFG_RCGR__SRC_SEL___S 8 +#define PMM_TOP_WCSS_DAC_ACSCAN_960_CFG_RCGR__SRC_DIV___M 0x0000001F +#define PMM_TOP_WCSS_DAC_ACSCAN_960_CFG_RCGR__SRC_DIV___S 0 +#define PMM_TOP_WCSS_DAC_ACSCAN_960_CFG_RCGR___M 0x0000071F +#define PMM_TOP_WCSS_DAC_ACSCAN_960_CFG_RCGR___S 0 + +#define PMM_TOP_WCSS_PLL_TEST_OUT_MUX_SEL (0x00B701C0) +#define PMM_TOP_WCSS_PLL_TEST_OUT_MUX_SEL___RWC QCSR_REG_RW +#define PMM_TOP_WCSS_PLL_TEST_OUT_MUX_SEL___POR 0x00000000 +#define PMM_TOP_WCSS_PLL_TEST_OUT_MUX_SEL__PLL_TEST_OUT_SELECT___POR 0x0 +#define PMM_TOP_WCSS_PLL_TEST_OUT_MUX_SEL__PLL_TEST_OUT_SELECT___M 0x00000001 +#define PMM_TOP_WCSS_PLL_TEST_OUT_MUX_SEL__PLL_TEST_OUT_SELECT___S 0 +#define PMM_TOP_WCSS_PLL_TEST_OUT_MUX_SEL___M 0x00000001 +#define PMM_TOP_WCSS_PLL_TEST_OUT_MUX_SEL___S 0 + +#define PMM_TOP_BB_PLL (0x00B701C4) +#define PMM_TOP_BB_PLL___RWC QCSR_REG_RW +#define PMM_TOP_BB_PLL___POR 0x00000000 +#define PMM_TOP_BB_PLL__PLL_LOCK___POR 0x0 +#define PMM_TOP_BB_PLL__PLL_RAW_CLK_EN___POR 0x0 +#define PMM_TOP_BB_PLL__PLL_RST_L___POR 0x0 +#define PMM_TOP_BB_PLL__PLL_ISO_EN_L___POR 0x0 +#define PMM_TOP_BB_PLL__PLL_LDO_EN___POR 0x0 +#define PMM_TOP_BB_PLL__PLL_ENABLE___POR 0x0 +#define PMM_TOP_BB_PLL__PLL_LOCK___M 0x80000000 +#define PMM_TOP_BB_PLL__PLL_LOCK___S 31 +#define PMM_TOP_BB_PLL__PLL_RAW_CLK_EN___M 0x00000010 +#define PMM_TOP_BB_PLL__PLL_RAW_CLK_EN___S 4 +#define PMM_TOP_BB_PLL__PLL_RST_L___M 0x00000008 +#define PMM_TOP_BB_PLL__PLL_RST_L___S 3 +#define PMM_TOP_BB_PLL__PLL_ISO_EN_L___M 0x00000004 +#define PMM_TOP_BB_PLL__PLL_ISO_EN_L___S 2 +#define PMM_TOP_BB_PLL__PLL_LDO_EN___M 0x00000002 +#define PMM_TOP_BB_PLL__PLL_LDO_EN___S 1 +#define PMM_TOP_BB_PLL__PLL_ENABLE___M 0x00000001 +#define PMM_TOP_BB_PLL__PLL_ENABLE___S 0 +#define PMM_TOP_BB_PLL___M 0x8000001F +#define PMM_TOP_BB_PLL___S 0 + +#define PMM_TOP_HW_EVENT_CTL_0 (0x00B701E0) +#define PMM_TOP_HW_EVENT_CTL_0___RWC QCSR_REG_RW +#define PMM_TOP_HW_EVENT_CTL_0___POR 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_0__HW_EVENT_ENABLE___POR 0x1 +#define PMM_TOP_HW_EVENT_CTL_0__HW_EVENT_SEL___POR 0x0 +#define PMM_TOP_HW_EVENT_CTL_0__HW_EVENT_ENABLE___M 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_0__HW_EVENT_ENABLE___S 31 +#define PMM_TOP_HW_EVENT_CTL_0__HW_EVENT_SEL___M 0x0000000F +#define PMM_TOP_HW_EVENT_CTL_0__HW_EVENT_SEL___S 0 +#define PMM_TOP_HW_EVENT_CTL_0___M 0x8000000F +#define PMM_TOP_HW_EVENT_CTL_0___S 0 + +#define PMM_TOP_HW_EVENT_CTL_1 (0x00B701E4) +#define PMM_TOP_HW_EVENT_CTL_1___RWC QCSR_REG_RW +#define PMM_TOP_HW_EVENT_CTL_1___POR 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_1__HW_EVENT_ENABLE___POR 0x1 +#define PMM_TOP_HW_EVENT_CTL_1__HW_EVENT_SEL___POR 0x0 +#define PMM_TOP_HW_EVENT_CTL_1__HW_EVENT_ENABLE___M 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_1__HW_EVENT_ENABLE___S 31 +#define PMM_TOP_HW_EVENT_CTL_1__HW_EVENT_SEL___M 0x0000000F +#define PMM_TOP_HW_EVENT_CTL_1__HW_EVENT_SEL___S 0 +#define PMM_TOP_HW_EVENT_CTL_1___M 0x8000000F +#define PMM_TOP_HW_EVENT_CTL_1___S 0 + +#define PMM_TOP_HW_EVENT_CTL_2 (0x00B701E8) +#define PMM_TOP_HW_EVENT_CTL_2___RWC QCSR_REG_RW +#define PMM_TOP_HW_EVENT_CTL_2___POR 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_2__HW_EVENT_ENABLE___POR 0x1 +#define PMM_TOP_HW_EVENT_CTL_2__HW_EVENT_SEL___POR 0x0 +#define PMM_TOP_HW_EVENT_CTL_2__HW_EVENT_ENABLE___M 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_2__HW_EVENT_ENABLE___S 31 +#define PMM_TOP_HW_EVENT_CTL_2__HW_EVENT_SEL___M 0x0000000F +#define PMM_TOP_HW_EVENT_CTL_2__HW_EVENT_SEL___S 0 +#define PMM_TOP_HW_EVENT_CTL_2___M 0x8000000F +#define PMM_TOP_HW_EVENT_CTL_2___S 0 + +#define PMM_TOP_HW_EVENT_CTL_3 (0x00B701EC) +#define PMM_TOP_HW_EVENT_CTL_3___RWC QCSR_REG_RW +#define PMM_TOP_HW_EVENT_CTL_3___POR 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_3__HW_EVENT_ENABLE___POR 0x1 +#define PMM_TOP_HW_EVENT_CTL_3__HW_EVENT_SEL___POR 0x0 +#define PMM_TOP_HW_EVENT_CTL_3__HW_EVENT_ENABLE___M 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_3__HW_EVENT_ENABLE___S 31 +#define PMM_TOP_HW_EVENT_CTL_3__HW_EVENT_SEL___M 0x0000000F +#define PMM_TOP_HW_EVENT_CTL_3__HW_EVENT_SEL___S 0 +#define PMM_TOP_HW_EVENT_CTL_3___M 0x8000000F +#define PMM_TOP_HW_EVENT_CTL_3___S 0 + +#define PMM_TOP_HW_EVENT_CTL_4 (0x00B701F0) +#define PMM_TOP_HW_EVENT_CTL_4___RWC QCSR_REG_RW +#define PMM_TOP_HW_EVENT_CTL_4___POR 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_4__HW_EVENT_ENABLE___POR 0x1 +#define PMM_TOP_HW_EVENT_CTL_4__HW_EVENT_SEL___POR 0x0 +#define PMM_TOP_HW_EVENT_CTL_4__HW_EVENT_ENABLE___M 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_4__HW_EVENT_ENABLE___S 31 +#define PMM_TOP_HW_EVENT_CTL_4__HW_EVENT_SEL___M 0x0000000F +#define PMM_TOP_HW_EVENT_CTL_4__HW_EVENT_SEL___S 0 +#define PMM_TOP_HW_EVENT_CTL_4___M 0x8000000F +#define PMM_TOP_HW_EVENT_CTL_4___S 0 + +#define PMM_TOP_HW_EVENT_CTL_5 (0x00B701F4) +#define PMM_TOP_HW_EVENT_CTL_5___RWC QCSR_REG_RW +#define PMM_TOP_HW_EVENT_CTL_5___POR 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_5__HW_EVENT_ENABLE___POR 0x1 +#define PMM_TOP_HW_EVENT_CTL_5__HW_EVENT_SEL___POR 0x0 +#define PMM_TOP_HW_EVENT_CTL_5__HW_EVENT_ENABLE___M 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_5__HW_EVENT_ENABLE___S 31 +#define PMM_TOP_HW_EVENT_CTL_5__HW_EVENT_SEL___M 0x0000000F +#define PMM_TOP_HW_EVENT_CTL_5__HW_EVENT_SEL___S 0 +#define PMM_TOP_HW_EVENT_CTL_5___M 0x8000000F +#define PMM_TOP_HW_EVENT_CTL_5___S 0 + +#define PMM_TOP_HW_EVENT_CTL_6 (0x00B701F8) +#define PMM_TOP_HW_EVENT_CTL_6___RWC QCSR_REG_RW +#define PMM_TOP_HW_EVENT_CTL_6___POR 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_6__HW_EVENT_ENABLE___POR 0x1 +#define PMM_TOP_HW_EVENT_CTL_6__HW_EVENT_SEL___POR 0x0 +#define PMM_TOP_HW_EVENT_CTL_6__HW_EVENT_ENABLE___M 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_6__HW_EVENT_ENABLE___S 31 +#define PMM_TOP_HW_EVENT_CTL_6__HW_EVENT_SEL___M 0x0000000F +#define PMM_TOP_HW_EVENT_CTL_6__HW_EVENT_SEL___S 0 +#define PMM_TOP_HW_EVENT_CTL_6___M 0x8000000F +#define PMM_TOP_HW_EVENT_CTL_6___S 0 + +#define PMM_TOP_HW_EVENT_CTL_7 (0x00B701FC) +#define PMM_TOP_HW_EVENT_CTL_7___RWC QCSR_REG_RW +#define PMM_TOP_HW_EVENT_CTL_7___POR 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_7__HW_EVENT_ENABLE___POR 0x1 +#define PMM_TOP_HW_EVENT_CTL_7__HW_EVENT_SEL___POR 0x0 +#define PMM_TOP_HW_EVENT_CTL_7__HW_EVENT_ENABLE___M 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_7__HW_EVENT_ENABLE___S 31 +#define PMM_TOP_HW_EVENT_CTL_7__HW_EVENT_SEL___M 0x0000000F +#define PMM_TOP_HW_EVENT_CTL_7__HW_EVENT_SEL___S 0 +#define PMM_TOP_HW_EVENT_CTL_7___M 0x8000000F +#define PMM_TOP_HW_EVENT_CTL_7___S 0 + +#define PMM_TOP_HW_EVENT_CTL_8 (0x00B70200) +#define PMM_TOP_HW_EVENT_CTL_8___RWC QCSR_REG_RW +#define PMM_TOP_HW_EVENT_CTL_8___POR 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_8__HW_EVENT_ENABLE___POR 0x1 +#define PMM_TOP_HW_EVENT_CTL_8__HW_EVENT_SEL___POR 0x0 +#define PMM_TOP_HW_EVENT_CTL_8__HW_EVENT_ENABLE___M 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_8__HW_EVENT_ENABLE___S 31 +#define PMM_TOP_HW_EVENT_CTL_8__HW_EVENT_SEL___M 0x0000000F +#define PMM_TOP_HW_EVENT_CTL_8__HW_EVENT_SEL___S 0 +#define PMM_TOP_HW_EVENT_CTL_8___M 0x8000000F +#define PMM_TOP_HW_EVENT_CTL_8___S 0 + +#define PMM_TOP_HW_EVENT_CTL_9 (0x00B70204) +#define PMM_TOP_HW_EVENT_CTL_9___RWC QCSR_REG_RW +#define PMM_TOP_HW_EVENT_CTL_9___POR 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_9__HW_EVENT_ENABLE___POR 0x1 +#define PMM_TOP_HW_EVENT_CTL_9__HW_EVENT_SEL___POR 0x0 +#define PMM_TOP_HW_EVENT_CTL_9__HW_EVENT_ENABLE___M 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_9__HW_EVENT_ENABLE___S 31 +#define PMM_TOP_HW_EVENT_CTL_9__HW_EVENT_SEL___M 0x0000000F +#define PMM_TOP_HW_EVENT_CTL_9__HW_EVENT_SEL___S 0 +#define PMM_TOP_HW_EVENT_CTL_9___M 0x8000000F +#define PMM_TOP_HW_EVENT_CTL_9___S 0 + +#define PMM_TOP_HW_EVENT_CTL_10 (0x00B70208) +#define PMM_TOP_HW_EVENT_CTL_10___RWC QCSR_REG_RW +#define PMM_TOP_HW_EVENT_CTL_10___POR 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_10__HW_EVENT_ENABLE___POR 0x1 +#define PMM_TOP_HW_EVENT_CTL_10__HW_EVENT_SEL___POR 0x0 +#define PMM_TOP_HW_EVENT_CTL_10__HW_EVENT_ENABLE___M 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_10__HW_EVENT_ENABLE___S 31 +#define PMM_TOP_HW_EVENT_CTL_10__HW_EVENT_SEL___M 0x0000000F +#define PMM_TOP_HW_EVENT_CTL_10__HW_EVENT_SEL___S 0 +#define PMM_TOP_HW_EVENT_CTL_10___M 0x8000000F +#define PMM_TOP_HW_EVENT_CTL_10___S 0 + +#define PMM_TOP_HW_EVENT_CTL_11 (0x00B7020C) +#define PMM_TOP_HW_EVENT_CTL_11___RWC QCSR_REG_RW +#define PMM_TOP_HW_EVENT_CTL_11___POR 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_11__HW_EVENT_ENABLE___POR 0x1 +#define PMM_TOP_HW_EVENT_CTL_11__HW_EVENT_SEL___POR 0x0 +#define PMM_TOP_HW_EVENT_CTL_11__HW_EVENT_ENABLE___M 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_11__HW_EVENT_ENABLE___S 31 +#define PMM_TOP_HW_EVENT_CTL_11__HW_EVENT_SEL___M 0x0000000F +#define PMM_TOP_HW_EVENT_CTL_11__HW_EVENT_SEL___S 0 +#define PMM_TOP_HW_EVENT_CTL_11___M 0x8000000F +#define PMM_TOP_HW_EVENT_CTL_11___S 0 + +#define PMM_TOP_HW_EVENT_CTL_12 (0x00B70210) +#define PMM_TOP_HW_EVENT_CTL_12___RWC QCSR_REG_RW +#define PMM_TOP_HW_EVENT_CTL_12___POR 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_12__HW_EVENT_ENABLE___POR 0x1 +#define PMM_TOP_HW_EVENT_CTL_12__HW_EVENT_SEL___POR 0x0 +#define PMM_TOP_HW_EVENT_CTL_12__HW_EVENT_ENABLE___M 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_12__HW_EVENT_ENABLE___S 31 +#define PMM_TOP_HW_EVENT_CTL_12__HW_EVENT_SEL___M 0x0000000F +#define PMM_TOP_HW_EVENT_CTL_12__HW_EVENT_SEL___S 0 +#define PMM_TOP_HW_EVENT_CTL_12___M 0x8000000F +#define PMM_TOP_HW_EVENT_CTL_12___S 0 + +#define PMM_TOP_HW_EVENT_CTL_13 (0x00B70214) +#define PMM_TOP_HW_EVENT_CTL_13___RWC QCSR_REG_RW +#define PMM_TOP_HW_EVENT_CTL_13___POR 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_13__HW_EVENT_ENABLE___POR 0x1 +#define PMM_TOP_HW_EVENT_CTL_13__HW_EVENT_SEL___POR 0x0 +#define PMM_TOP_HW_EVENT_CTL_13__HW_EVENT_ENABLE___M 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_13__HW_EVENT_ENABLE___S 31 +#define PMM_TOP_HW_EVENT_CTL_13__HW_EVENT_SEL___M 0x0000000F +#define PMM_TOP_HW_EVENT_CTL_13__HW_EVENT_SEL___S 0 +#define PMM_TOP_HW_EVENT_CTL_13___M 0x8000000F +#define PMM_TOP_HW_EVENT_CTL_13___S 0 + +#define PMM_TOP_HW_EVENT_CTL_14 (0x00B70218) +#define PMM_TOP_HW_EVENT_CTL_14___RWC QCSR_REG_RW +#define PMM_TOP_HW_EVENT_CTL_14___POR 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_14__HW_EVENT_ENABLE___POR 0x1 +#define PMM_TOP_HW_EVENT_CTL_14__HW_EVENT_SEL___POR 0x0 +#define PMM_TOP_HW_EVENT_CTL_14__HW_EVENT_ENABLE___M 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_14__HW_EVENT_ENABLE___S 31 +#define PMM_TOP_HW_EVENT_CTL_14__HW_EVENT_SEL___M 0x0000000F +#define PMM_TOP_HW_EVENT_CTL_14__HW_EVENT_SEL___S 0 +#define PMM_TOP_HW_EVENT_CTL_14___M 0x8000000F +#define PMM_TOP_HW_EVENT_CTL_14___S 0 + +#define PMM_TOP_HW_EVENT_CTL_15 (0x00B7021C) +#define PMM_TOP_HW_EVENT_CTL_15___RWC QCSR_REG_RW +#define PMM_TOP_HW_EVENT_CTL_15___POR 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_15__HW_EVENT_ENABLE___POR 0x1 +#define PMM_TOP_HW_EVENT_CTL_15__HW_EVENT_SEL___POR 0x0 +#define PMM_TOP_HW_EVENT_CTL_15__HW_EVENT_ENABLE___M 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_15__HW_EVENT_ENABLE___S 31 +#define PMM_TOP_HW_EVENT_CTL_15__HW_EVENT_SEL___M 0x0000000F +#define PMM_TOP_HW_EVENT_CTL_15__HW_EVENT_SEL___S 0 +#define PMM_TOP_HW_EVENT_CTL_15___M 0x8000000F +#define PMM_TOP_HW_EVENT_CTL_15___S 0 + +#define PMM_TOP_HW_EVENT_CTL_16 (0x00B70220) +#define PMM_TOP_HW_EVENT_CTL_16___RWC QCSR_REG_RW +#define PMM_TOP_HW_EVENT_CTL_16___POR 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_16__HW_EVENT_ENABLE___POR 0x1 +#define PMM_TOP_HW_EVENT_CTL_16__HW_EVENT_SEL___POR 0x0 +#define PMM_TOP_HW_EVENT_CTL_16__HW_EVENT_ENABLE___M 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_16__HW_EVENT_ENABLE___S 31 +#define PMM_TOP_HW_EVENT_CTL_16__HW_EVENT_SEL___M 0x0000000F +#define PMM_TOP_HW_EVENT_CTL_16__HW_EVENT_SEL___S 0 +#define PMM_TOP_HW_EVENT_CTL_16___M 0x8000000F +#define PMM_TOP_HW_EVENT_CTL_16___S 0 + +#define PMM_TOP_HW_EVENT_CTL_17 (0x00B70224) +#define PMM_TOP_HW_EVENT_CTL_17___RWC QCSR_REG_RW +#define PMM_TOP_HW_EVENT_CTL_17___POR 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_17__HW_EVENT_ENABLE___POR 0x1 +#define PMM_TOP_HW_EVENT_CTL_17__HW_EVENT_SEL___POR 0x0 +#define PMM_TOP_HW_EVENT_CTL_17__HW_EVENT_ENABLE___M 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_17__HW_EVENT_ENABLE___S 31 +#define PMM_TOP_HW_EVENT_CTL_17__HW_EVENT_SEL___M 0x0000000F +#define PMM_TOP_HW_EVENT_CTL_17__HW_EVENT_SEL___S 0 +#define PMM_TOP_HW_EVENT_CTL_17___M 0x8000000F +#define PMM_TOP_HW_EVENT_CTL_17___S 0 + +#define PMM_TOP_HW_EVENT_CTL_18 (0x00B70228) +#define PMM_TOP_HW_EVENT_CTL_18___RWC QCSR_REG_RW +#define PMM_TOP_HW_EVENT_CTL_18___POR 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_18__HW_EVENT_ENABLE___POR 0x1 +#define PMM_TOP_HW_EVENT_CTL_18__HW_EVENT_SEL___POR 0x0 +#define PMM_TOP_HW_EVENT_CTL_18__HW_EVENT_ENABLE___M 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_18__HW_EVENT_ENABLE___S 31 +#define PMM_TOP_HW_EVENT_CTL_18__HW_EVENT_SEL___M 0x0000000F +#define PMM_TOP_HW_EVENT_CTL_18__HW_EVENT_SEL___S 0 +#define PMM_TOP_HW_EVENT_CTL_18___M 0x8000000F +#define PMM_TOP_HW_EVENT_CTL_18___S 0 + +#define PMM_TOP_HW_EVENT_CTL_19 (0x00B7022C) +#define PMM_TOP_HW_EVENT_CTL_19___RWC QCSR_REG_RW +#define PMM_TOP_HW_EVENT_CTL_19___POR 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_19__HW_EVENT_ENABLE___POR 0x1 +#define PMM_TOP_HW_EVENT_CTL_19__HW_EVENT_SEL___POR 0x0 +#define PMM_TOP_HW_EVENT_CTL_19__HW_EVENT_ENABLE___M 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_19__HW_EVENT_ENABLE___S 31 +#define PMM_TOP_HW_EVENT_CTL_19__HW_EVENT_SEL___M 0x0000000F +#define PMM_TOP_HW_EVENT_CTL_19__HW_EVENT_SEL___S 0 +#define PMM_TOP_HW_EVENT_CTL_19___M 0x8000000F +#define PMM_TOP_HW_EVENT_CTL_19___S 0 + +#define PMM_TOP_HW_EVENT_CTL_20 (0x00B70230) +#define PMM_TOP_HW_EVENT_CTL_20___RWC QCSR_REG_RW +#define PMM_TOP_HW_EVENT_CTL_20___POR 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_20__HW_EVENT_ENABLE___POR 0x1 +#define PMM_TOP_HW_EVENT_CTL_20__HW_EVENT_SEL___POR 0x0 +#define PMM_TOP_HW_EVENT_CTL_20__HW_EVENT_ENABLE___M 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_20__HW_EVENT_ENABLE___S 31 +#define PMM_TOP_HW_EVENT_CTL_20__HW_EVENT_SEL___M 0x0000000F +#define PMM_TOP_HW_EVENT_CTL_20__HW_EVENT_SEL___S 0 +#define PMM_TOP_HW_EVENT_CTL_20___M 0x8000000F +#define PMM_TOP_HW_EVENT_CTL_20___S 0 + +#define PMM_TOP_HW_EVENT_CTL_21 (0x00B70234) +#define PMM_TOP_HW_EVENT_CTL_21___RWC QCSR_REG_RW +#define PMM_TOP_HW_EVENT_CTL_21___POR 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_21__HW_EVENT_ENABLE___POR 0x1 +#define PMM_TOP_HW_EVENT_CTL_21__HW_EVENT_SEL___POR 0x0 +#define PMM_TOP_HW_EVENT_CTL_21__HW_EVENT_ENABLE___M 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_21__HW_EVENT_ENABLE___S 31 +#define PMM_TOP_HW_EVENT_CTL_21__HW_EVENT_SEL___M 0x0000000F +#define PMM_TOP_HW_EVENT_CTL_21__HW_EVENT_SEL___S 0 +#define PMM_TOP_HW_EVENT_CTL_21___M 0x8000000F +#define PMM_TOP_HW_EVENT_CTL_21___S 0 + +#define PMM_TOP_HW_EVENT_CTL_22 (0x00B70238) +#define PMM_TOP_HW_EVENT_CTL_22___RWC QCSR_REG_RW +#define PMM_TOP_HW_EVENT_CTL_22___POR 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_22__HW_EVENT_ENABLE___POR 0x1 +#define PMM_TOP_HW_EVENT_CTL_22__HW_EVENT_SEL___POR 0x0 +#define PMM_TOP_HW_EVENT_CTL_22__HW_EVENT_ENABLE___M 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_22__HW_EVENT_ENABLE___S 31 +#define PMM_TOP_HW_EVENT_CTL_22__HW_EVENT_SEL___M 0x0000000F +#define PMM_TOP_HW_EVENT_CTL_22__HW_EVENT_SEL___S 0 +#define PMM_TOP_HW_EVENT_CTL_22___M 0x8000000F +#define PMM_TOP_HW_EVENT_CTL_22___S 0 + +#define PMM_TOP_HW_EVENT_CTL_23 (0x00B7023C) +#define PMM_TOP_HW_EVENT_CTL_23___RWC QCSR_REG_RW +#define PMM_TOP_HW_EVENT_CTL_23___POR 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_23__HW_EVENT_ENABLE___POR 0x1 +#define PMM_TOP_HW_EVENT_CTL_23__HW_EVENT_SEL___POR 0x0 +#define PMM_TOP_HW_EVENT_CTL_23__HW_EVENT_ENABLE___M 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_23__HW_EVENT_ENABLE___S 31 +#define PMM_TOP_HW_EVENT_CTL_23__HW_EVENT_SEL___M 0x0000000F +#define PMM_TOP_HW_EVENT_CTL_23__HW_EVENT_SEL___S 0 +#define PMM_TOP_HW_EVENT_CTL_23___M 0x8000000F +#define PMM_TOP_HW_EVENT_CTL_23___S 0 + +#define PMM_TOP_HW_EVENT_CTL_24 (0x00B70240) +#define PMM_TOP_HW_EVENT_CTL_24___RWC QCSR_REG_RW +#define PMM_TOP_HW_EVENT_CTL_24___POR 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_24__HW_EVENT_ENABLE___POR 0x1 +#define PMM_TOP_HW_EVENT_CTL_24__HW_EVENT_SEL___POR 0x0 +#define PMM_TOP_HW_EVENT_CTL_24__HW_EVENT_ENABLE___M 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_24__HW_EVENT_ENABLE___S 31 +#define PMM_TOP_HW_EVENT_CTL_24__HW_EVENT_SEL___M 0x0000000F +#define PMM_TOP_HW_EVENT_CTL_24__HW_EVENT_SEL___S 0 +#define PMM_TOP_HW_EVENT_CTL_24___M 0x8000000F +#define PMM_TOP_HW_EVENT_CTL_24___S 0 + +#define PMM_TOP_HW_EVENT_CTL_25 (0x00B70244) +#define PMM_TOP_HW_EVENT_CTL_25___RWC QCSR_REG_RW +#define PMM_TOP_HW_EVENT_CTL_25___POR 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_25__HW_EVENT_ENABLE___POR 0x1 +#define PMM_TOP_HW_EVENT_CTL_25__HW_EVENT_SEL___POR 0x0 +#define PMM_TOP_HW_EVENT_CTL_25__HW_EVENT_ENABLE___M 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_25__HW_EVENT_ENABLE___S 31 +#define PMM_TOP_HW_EVENT_CTL_25__HW_EVENT_SEL___M 0x0000000F +#define PMM_TOP_HW_EVENT_CTL_25__HW_EVENT_SEL___S 0 +#define PMM_TOP_HW_EVENT_CTL_25___M 0x8000000F +#define PMM_TOP_HW_EVENT_CTL_25___S 0 + +#define PMM_TOP_HW_EVENT_CTL_26 (0x00B70248) +#define PMM_TOP_HW_EVENT_CTL_26___RWC QCSR_REG_RW +#define PMM_TOP_HW_EVENT_CTL_26___POR 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_26__HW_EVENT_ENABLE___POR 0x1 +#define PMM_TOP_HW_EVENT_CTL_26__HW_EVENT_SEL___POR 0x0 +#define PMM_TOP_HW_EVENT_CTL_26__HW_EVENT_ENABLE___M 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_26__HW_EVENT_ENABLE___S 31 +#define PMM_TOP_HW_EVENT_CTL_26__HW_EVENT_SEL___M 0x0000000F +#define PMM_TOP_HW_EVENT_CTL_26__HW_EVENT_SEL___S 0 +#define PMM_TOP_HW_EVENT_CTL_26___M 0x8000000F +#define PMM_TOP_HW_EVENT_CTL_26___S 0 + +#define PMM_TOP_HW_EVENT_CTL_27 (0x00B7024C) +#define PMM_TOP_HW_EVENT_CTL_27___RWC QCSR_REG_RW +#define PMM_TOP_HW_EVENT_CTL_27___POR 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_27__HW_EVENT_ENABLE___POR 0x1 +#define PMM_TOP_HW_EVENT_CTL_27__HW_EVENT_SEL___POR 0x0 +#define PMM_TOP_HW_EVENT_CTL_27__HW_EVENT_ENABLE___M 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_27__HW_EVENT_ENABLE___S 31 +#define PMM_TOP_HW_EVENT_CTL_27__HW_EVENT_SEL___M 0x0000000F +#define PMM_TOP_HW_EVENT_CTL_27__HW_EVENT_SEL___S 0 +#define PMM_TOP_HW_EVENT_CTL_27___M 0x8000000F +#define PMM_TOP_HW_EVENT_CTL_27___S 0 + +#define PMM_TOP_HW_EVENT_CTL_28 (0x00B70250) +#define PMM_TOP_HW_EVENT_CTL_28___RWC QCSR_REG_RW +#define PMM_TOP_HW_EVENT_CTL_28___POR 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_28__HW_EVENT_ENABLE___POR 0x1 +#define PMM_TOP_HW_EVENT_CTL_28__HW_EVENT_SEL___POR 0x0 +#define PMM_TOP_HW_EVENT_CTL_28__HW_EVENT_ENABLE___M 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_28__HW_EVENT_ENABLE___S 31 +#define PMM_TOP_HW_EVENT_CTL_28__HW_EVENT_SEL___M 0x0000000F +#define PMM_TOP_HW_EVENT_CTL_28__HW_EVENT_SEL___S 0 +#define PMM_TOP_HW_EVENT_CTL_28___M 0x8000000F +#define PMM_TOP_HW_EVENT_CTL_28___S 0 + +#define PMM_TOP_HW_EVENT_CTL_29 (0x00B70254) +#define PMM_TOP_HW_EVENT_CTL_29___RWC QCSR_REG_RW +#define PMM_TOP_HW_EVENT_CTL_29___POR 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_29__HW_EVENT_ENABLE___POR 0x1 +#define PMM_TOP_HW_EVENT_CTL_29__HW_EVENT_SEL___POR 0x0 +#define PMM_TOP_HW_EVENT_CTL_29__HW_EVENT_ENABLE___M 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_29__HW_EVENT_ENABLE___S 31 +#define PMM_TOP_HW_EVENT_CTL_29__HW_EVENT_SEL___M 0x0000000F +#define PMM_TOP_HW_EVENT_CTL_29__HW_EVENT_SEL___S 0 +#define PMM_TOP_HW_EVENT_CTL_29___M 0x8000000F +#define PMM_TOP_HW_EVENT_CTL_29___S 0 + +#define PMM_TOP_HW_EVENT_CTL_30 (0x00B70258) +#define PMM_TOP_HW_EVENT_CTL_30___RWC QCSR_REG_RW +#define PMM_TOP_HW_EVENT_CTL_30___POR 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_30__HW_EVENT_ENABLE___POR 0x1 +#define PMM_TOP_HW_EVENT_CTL_30__HW_EVENT_SEL___POR 0x0 +#define PMM_TOP_HW_EVENT_CTL_30__HW_EVENT_ENABLE___M 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_30__HW_EVENT_ENABLE___S 31 +#define PMM_TOP_HW_EVENT_CTL_30__HW_EVENT_SEL___M 0x0000000F +#define PMM_TOP_HW_EVENT_CTL_30__HW_EVENT_SEL___S 0 +#define PMM_TOP_HW_EVENT_CTL_30___M 0x8000000F +#define PMM_TOP_HW_EVENT_CTL_30___S 0 + +#define PMM_TOP_HW_EVENT_CTL_31 (0x00B7025C) +#define PMM_TOP_HW_EVENT_CTL_31___RWC QCSR_REG_RW +#define PMM_TOP_HW_EVENT_CTL_31___POR 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_31__HW_EVENT_ENABLE___POR 0x1 +#define PMM_TOP_HW_EVENT_CTL_31__HW_EVENT_SEL___POR 0x0 +#define PMM_TOP_HW_EVENT_CTL_31__HW_EVENT_ENABLE___M 0x80000000 +#define PMM_TOP_HW_EVENT_CTL_31__HW_EVENT_ENABLE___S 31 +#define PMM_TOP_HW_EVENT_CTL_31__HW_EVENT_SEL___M 0x0000000F +#define PMM_TOP_HW_EVENT_CTL_31__HW_EVENT_SEL___S 0 +#define PMM_TOP_HW_EVENT_CTL_31___M 0x8000000F +#define PMM_TOP_HW_EVENT_CTL_31___S 0 + +#define PMM_TOP_LMAC_LPI (0x00B70280) +#define PMM_TOP_LMAC_LPI___RWC QCSR_REG_RW +#define PMM_TOP_LMAC_LPI___POR 0x00000000 +#define PMM_TOP_LMAC_LPI__PMM_LMAC1_LPI_SLV_IFC_CSYSREQ___POR 0x0 +#define PMM_TOP_LMAC_LPI__PMM_LMAC0_LPI_SLV_IFC_CSYSREQ___POR 0x0 +#define PMM_TOP_LMAC_LPI__WLAN2_GDSC_COLLAPSE_EN_AHB___POR 0x0 +#define PMM_TOP_LMAC_LPI__WLAN1_GDSC_COLLAPSE_EN_AHB___POR 0x0 +#define PMM_TOP_LMAC_LPI__DBG_LMAC1_LPI_SLV_IFC_CSYSACK___POR 0x0 +#define PMM_TOP_LMAC_LPI__DBG_LMAC0_LPI_SLV_IFC_CSYSACK___POR 0x0 +#define PMM_TOP_LMAC_LPI__SW_LMAC1_LPI_SLV_IFC_CSYSREQ_CLR___POR 0x0 +#define PMM_TOP_LMAC_LPI__SW_LMAC1_LPI_SLV_IFC_CSYSREQ_SET___POR 0x0 +#define PMM_TOP_LMAC_LPI__SW_LMAC0_LPI_SLV_IFC_CSYSREQ_CLR___POR 0x0 +#define PMM_TOP_LMAC_LPI__SW_LMAC0_LPI_SLV_IFC_CSYSREQ_SET___POR 0x0 +#define PMM_TOP_LMAC_LPI__PMM_LMAC1_LPI_SLV_IFC_CSYSREQ___M 0x00000200 +#define PMM_TOP_LMAC_LPI__PMM_LMAC1_LPI_SLV_IFC_CSYSREQ___S 9 +#define PMM_TOP_LMAC_LPI__PMM_LMAC0_LPI_SLV_IFC_CSYSREQ___M 0x00000100 +#define PMM_TOP_LMAC_LPI__PMM_LMAC0_LPI_SLV_IFC_CSYSREQ___S 8 +#define PMM_TOP_LMAC_LPI__WLAN2_GDSC_COLLAPSE_EN_AHB___M 0x00000080 +#define PMM_TOP_LMAC_LPI__WLAN2_GDSC_COLLAPSE_EN_AHB___S 7 +#define PMM_TOP_LMAC_LPI__WLAN1_GDSC_COLLAPSE_EN_AHB___M 0x00000040 +#define PMM_TOP_LMAC_LPI__WLAN1_GDSC_COLLAPSE_EN_AHB___S 6 +#define PMM_TOP_LMAC_LPI__DBG_LMAC1_LPI_SLV_IFC_CSYSACK___M 0x00000020 +#define PMM_TOP_LMAC_LPI__DBG_LMAC1_LPI_SLV_IFC_CSYSACK___S 5 +#define PMM_TOP_LMAC_LPI__DBG_LMAC0_LPI_SLV_IFC_CSYSACK___M 0x00000010 +#define PMM_TOP_LMAC_LPI__DBG_LMAC0_LPI_SLV_IFC_CSYSACK___S 4 +#define PMM_TOP_LMAC_LPI__SW_LMAC1_LPI_SLV_IFC_CSYSREQ_CLR___M 0x00000008 +#define PMM_TOP_LMAC_LPI__SW_LMAC1_LPI_SLV_IFC_CSYSREQ_CLR___S 3 +#define PMM_TOP_LMAC_LPI__SW_LMAC1_LPI_SLV_IFC_CSYSREQ_SET___M 0x00000004 +#define PMM_TOP_LMAC_LPI__SW_LMAC1_LPI_SLV_IFC_CSYSREQ_SET___S 2 +#define PMM_TOP_LMAC_LPI__SW_LMAC0_LPI_SLV_IFC_CSYSREQ_CLR___M 0x00000002 +#define PMM_TOP_LMAC_LPI__SW_LMAC0_LPI_SLV_IFC_CSYSREQ_CLR___S 1 +#define PMM_TOP_LMAC_LPI__SW_LMAC0_LPI_SLV_IFC_CSYSREQ_SET___M 0x00000001 +#define PMM_TOP_LMAC_LPI__SW_LMAC0_LPI_SLV_IFC_CSYSREQ_SET___S 0 +#define PMM_TOP_LMAC_LPI___M 0x000003FF +#define PMM_TOP_LMAC_LPI___S 0 + +#define PMM_TOP_PMM_WLAN1_XBAR_CONFIG (0x00B70284) +#define PMM_TOP_PMM_WLAN1_XBAR_CONFIG___RWC QCSR_REG_RW +#define PMM_TOP_PMM_WLAN1_XBAR_CONFIG___POR 0x00000000 +#define PMM_TOP_PMM_WLAN1_XBAR_CONFIG__PMM_WLAN1_CHAIN_ENABLE___POR 0x0 +#define PMM_TOP_PMM_WLAN1_XBAR_CONFIG__PMM_WLAN1_CHAIN_ENABLE___M 0x0000000F +#define PMM_TOP_PMM_WLAN1_XBAR_CONFIG__PMM_WLAN1_CHAIN_ENABLE___S 0 +#define PMM_TOP_PMM_WLAN1_XBAR_CONFIG___M 0x0000000F +#define PMM_TOP_PMM_WLAN1_XBAR_CONFIG___S 0 + +#define PMM_TOP_PMM_WLAN2_XBAR_CONFIG (0x00B70288) +#define PMM_TOP_PMM_WLAN2_XBAR_CONFIG___RWC QCSR_REG_RW +#define PMM_TOP_PMM_WLAN2_XBAR_CONFIG___POR 0x00000000 +#define PMM_TOP_PMM_WLAN2_XBAR_CONFIG__PMM_WLAN2_CHAIN_ENABLE___POR 0x0 +#define PMM_TOP_PMM_WLAN2_XBAR_CONFIG__PMM_WLAN2_CHAIN_ENABLE___M 0x0000000F +#define PMM_TOP_PMM_WLAN2_XBAR_CONFIG__PMM_WLAN2_CHAIN_ENABLE___S 0 +#define PMM_TOP_PMM_WLAN2_XBAR_CONFIG___M 0x0000000F +#define PMM_TOP_PMM_WLAN2_XBAR_CONFIG___S 0 + +#define PMM_TOP_SOC_WDOG_TRIG (0x00B7028C) +#define PMM_TOP_SOC_WDOG_TRIG___RWC QCSR_REG_RW +#define PMM_TOP_SOC_WDOG_TRIG___POR 0x00000000 +#define PMM_TOP_SOC_WDOG_TRIG__AON_PMM_CX_XO_SETTLE_TO_MSK___POR 0x0 +#define PMM_TOP_SOC_WDOG_TRIG__AON_WDOG2_BITE_MSK___POR 0x0 +#define PMM_TOP_SOC_WDOG_TRIG__AON_WDOG1_BITE_MSK___POR 0x0 +#define PMM_TOP_SOC_WDOG_TRIG__AON_PMM_CX_XO_SETTLE_TO_MSK___M 0x00000004 +#define PMM_TOP_SOC_WDOG_TRIG__AON_PMM_CX_XO_SETTLE_TO_MSK___S 2 +#define PMM_TOP_SOC_WDOG_TRIG__AON_WDOG2_BITE_MSK___M 0x00000002 +#define PMM_TOP_SOC_WDOG_TRIG__AON_WDOG2_BITE_MSK___S 1 +#define PMM_TOP_SOC_WDOG_TRIG__AON_WDOG1_BITE_MSK___M 0x00000001 +#define PMM_TOP_SOC_WDOG_TRIG__AON_WDOG1_BITE_MSK___S 0 +#define PMM_TOP_SOC_WDOG_TRIG___M 0x00000007 +#define PMM_TOP_SOC_WDOG_TRIG___S 0 + +#define PMM_TOP_ECAHB_ERR_RSP_OVERRIDE (0x00B70290) +#define PMM_TOP_ECAHB_ERR_RSP_OVERRIDE___RWC QCSR_REG_RW +#define PMM_TOP_ECAHB_ERR_RSP_OVERRIDE___POR 0x00000000 +#define PMM_TOP_ECAHB_ERR_RSP_OVERRIDE__WCSS_RET_RSP_MODE___POR 0x0 +#define PMM_TOP_ECAHB_ERR_RSP_OVERRIDE__ECAHB_ERR_RSP_OVERRIDE___POR 0x0 +#define PMM_TOP_ECAHB_ERR_RSP_OVERRIDE__WCSS_RET_RSP_MODE___M 0x80000000 +#define PMM_TOP_ECAHB_ERR_RSP_OVERRIDE__WCSS_RET_RSP_MODE___S 31 +#define PMM_TOP_ECAHB_ERR_RSP_OVERRIDE__ECAHB_ERR_RSP_OVERRIDE___M 0x00000007 +#define PMM_TOP_ECAHB_ERR_RSP_OVERRIDE__ECAHB_ERR_RSP_OVERRIDE___S 0 +#define PMM_TOP_ECAHB_ERR_RSP_OVERRIDE___M 0x80000007 +#define PMM_TOP_ECAHB_ERR_RSP_OVERRIDE___S 0 + +#define PMM_TOP_UMAC_LPI_SLV_IFC (0x00B70294) +#define PMM_TOP_UMAC_LPI_SLV_IFC___RWC QCSR_REG_RW +#define PMM_TOP_UMAC_LPI_SLV_IFC___POR 0x00000801 +#define PMM_TOP_UMAC_LPI_SLV_IFC__PLL_LOCK_TIMER___POR 0x0000 +#define PMM_TOP_UMAC_LPI_SLV_IFC__UMAC_LPI_CSYSACK_NEG_TO___POR 0x0 +#define PMM_TOP_UMAC_LPI_SLV_IFC__UMAC_LPI_CSYSACK_POS_TO___POR 0x0 +#define PMM_TOP_UMAC_LPI_SLV_IFC__CE_IDLE_CHK_TO___POR 0x0 +#define PMM_TOP_UMAC_LPI_SLV_IFC__PMM_UMAC_LPI_SLV_IFC_CSYSREQ___POR 0x1 +#define PMM_TOP_UMAC_LPI_SLV_IFC__DBG_UMAC_NOC_LPI_SLV_IFC_CSYSACK___POR 0x0 +#define PMM_TOP_UMAC_LPI_SLV_IFC__DBG_UMAC_LPI_SLV_IFC_CSYSACK___POR 0x0 +#define PMM_TOP_UMAC_LPI_SLV_IFC__UMAC_NOC_LPI_SLV_IFC_CSYSACK___POR 0x0 +#define PMM_TOP_UMAC_LPI_SLV_IFC__UMAC_LPI_SLV_IFC_CSYSACK___POR 0x0 +#define PMM_TOP_UMAC_LPI_SLV_IFC__SW_CLR_UMAC_LPI_SLV_IFC_CSYSREQ___POR 0x0 +#define PMM_TOP_UMAC_LPI_SLV_IFC__SW_SET_UMAC_LPI_SLV_IFC_CSYSREQ___POR 0x0 +#define PMM_TOP_UMAC_LPI_SLV_IFC__SW_DBG_UMAC_NOC_LPI_CSYSACK_LOOP___POR 0x0 +#define PMM_TOP_UMAC_LPI_SLV_IFC__SW_DBG_UMAC_LPI_CSYSACK_LOOP___POR 0x0 +#define PMM_TOP_UMAC_LPI_SLV_IFC__SW_UMAC_NOC_LPI_CSYSACK_LOOP___POR 0x0 +#define PMM_TOP_UMAC_LPI_SLV_IFC__SW_UMAC_LPI_CSYSACK_LOOP___POR 0x0 +#define PMM_TOP_UMAC_LPI_SLV_IFC__UMAC_LPI_ACK_CHECK_EN___POR 0x1 +#define PMM_TOP_UMAC_LPI_SLV_IFC__PLL_LOCK_TIMER___M 0xFFFF0000 +#define PMM_TOP_UMAC_LPI_SLV_IFC__PLL_LOCK_TIMER___S 16 +#define PMM_TOP_UMAC_LPI_SLV_IFC__UMAC_LPI_CSYSACK_NEG_TO___M 0x00004000 +#define PMM_TOP_UMAC_LPI_SLV_IFC__UMAC_LPI_CSYSACK_NEG_TO___S 14 +#define PMM_TOP_UMAC_LPI_SLV_IFC__UMAC_LPI_CSYSACK_POS_TO___M 0x00002000 +#define PMM_TOP_UMAC_LPI_SLV_IFC__UMAC_LPI_CSYSACK_POS_TO___S 13 +#define PMM_TOP_UMAC_LPI_SLV_IFC__CE_IDLE_CHK_TO___M 0x00001000 +#define PMM_TOP_UMAC_LPI_SLV_IFC__CE_IDLE_CHK_TO___S 12 +#define PMM_TOP_UMAC_LPI_SLV_IFC__PMM_UMAC_LPI_SLV_IFC_CSYSREQ___M 0x00000800 +#define PMM_TOP_UMAC_LPI_SLV_IFC__PMM_UMAC_LPI_SLV_IFC_CSYSREQ___S 11 +#define PMM_TOP_UMAC_LPI_SLV_IFC__DBG_UMAC_NOC_LPI_SLV_IFC_CSYSACK___M 0x00000400 +#define PMM_TOP_UMAC_LPI_SLV_IFC__DBG_UMAC_NOC_LPI_SLV_IFC_CSYSACK___S 10 +#define PMM_TOP_UMAC_LPI_SLV_IFC__DBG_UMAC_LPI_SLV_IFC_CSYSACK___M 0x00000200 +#define PMM_TOP_UMAC_LPI_SLV_IFC__DBG_UMAC_LPI_SLV_IFC_CSYSACK___S 9 +#define PMM_TOP_UMAC_LPI_SLV_IFC__UMAC_NOC_LPI_SLV_IFC_CSYSACK___M 0x00000100 +#define PMM_TOP_UMAC_LPI_SLV_IFC__UMAC_NOC_LPI_SLV_IFC_CSYSACK___S 8 +#define PMM_TOP_UMAC_LPI_SLV_IFC__UMAC_LPI_SLV_IFC_CSYSACK___M 0x00000080 +#define PMM_TOP_UMAC_LPI_SLV_IFC__UMAC_LPI_SLV_IFC_CSYSACK___S 7 +#define PMM_TOP_UMAC_LPI_SLV_IFC__SW_CLR_UMAC_LPI_SLV_IFC_CSYSREQ___M 0x00000040 +#define PMM_TOP_UMAC_LPI_SLV_IFC__SW_CLR_UMAC_LPI_SLV_IFC_CSYSREQ___S 6 +#define PMM_TOP_UMAC_LPI_SLV_IFC__SW_SET_UMAC_LPI_SLV_IFC_CSYSREQ___M 0x00000020 +#define PMM_TOP_UMAC_LPI_SLV_IFC__SW_SET_UMAC_LPI_SLV_IFC_CSYSREQ___S 5 +#define PMM_TOP_UMAC_LPI_SLV_IFC__SW_DBG_UMAC_NOC_LPI_CSYSACK_LOOP___M 0x00000010 +#define PMM_TOP_UMAC_LPI_SLV_IFC__SW_DBG_UMAC_NOC_LPI_CSYSACK_LOOP___S 4 +#define PMM_TOP_UMAC_LPI_SLV_IFC__SW_DBG_UMAC_LPI_CSYSACK_LOOP___M 0x00000008 +#define PMM_TOP_UMAC_LPI_SLV_IFC__SW_DBG_UMAC_LPI_CSYSACK_LOOP___S 3 +#define PMM_TOP_UMAC_LPI_SLV_IFC__SW_UMAC_NOC_LPI_CSYSACK_LOOP___M 0x00000004 +#define PMM_TOP_UMAC_LPI_SLV_IFC__SW_UMAC_NOC_LPI_CSYSACK_LOOP___S 2 +#define PMM_TOP_UMAC_LPI_SLV_IFC__SW_UMAC_LPI_CSYSACK_LOOP___M 0x00000002 +#define PMM_TOP_UMAC_LPI_SLV_IFC__SW_UMAC_LPI_CSYSACK_LOOP___S 1 +#define PMM_TOP_UMAC_LPI_SLV_IFC__UMAC_LPI_ACK_CHECK_EN___M 0x00000001 +#define PMM_TOP_UMAC_LPI_SLV_IFC__UMAC_LPI_ACK_CHECK_EN___S 0 +#define PMM_TOP_UMAC_LPI_SLV_IFC___M 0xFFFF7FFF +#define PMM_TOP_UMAC_LPI_SLV_IFC___S 0 + +#define PMM_TOP_SOC_WAKEUP_LATENCY_MIN (0x00B70298) +#define PMM_TOP_SOC_WAKEUP_LATENCY_MIN___RWC QCSR_REG_RO +#define PMM_TOP_SOC_WAKEUP_LATENCY_MIN___POR 0x00000000 +#define PMM_TOP_SOC_WAKEUP_LATENCY_MIN__SOC_WAKEUP_LATENCY_MIN_VAL___POR 0x00000000 +#define PMM_TOP_SOC_WAKEUP_LATENCY_MIN__SOC_WAKEUP_LATENCY_MIN_VAL___M 0xFFFFFFFF +#define PMM_TOP_SOC_WAKEUP_LATENCY_MIN__SOC_WAKEUP_LATENCY_MIN_VAL___S 0 +#define PMM_TOP_SOC_WAKEUP_LATENCY_MIN___M 0xFFFFFFFF +#define PMM_TOP_SOC_WAKEUP_LATENCY_MIN___S 0 + +#define PMM_TOP_SOC_WAKEUP_LATENCY_MAX (0x00B7029C) +#define PMM_TOP_SOC_WAKEUP_LATENCY_MAX___RWC QCSR_REG_RO +#define PMM_TOP_SOC_WAKEUP_LATENCY_MAX___POR 0x00000000 +#define PMM_TOP_SOC_WAKEUP_LATENCY_MAX__SOC_WAKEUP_LATENCY_MAX_VAL___POR 0x00000000 +#define PMM_TOP_SOC_WAKEUP_LATENCY_MAX__SOC_WAKEUP_LATENCY_MAX_VAL___M 0xFFFFFFFF +#define PMM_TOP_SOC_WAKEUP_LATENCY_MAX__SOC_WAKEUP_LATENCY_MAX_VAL___S 0 +#define PMM_TOP_SOC_WAKEUP_LATENCY_MAX___M 0xFFFFFFFF +#define PMM_TOP_SOC_WAKEUP_LATENCY_MAX___S 0 + +#define PMM_TOP_SOC_WAKEUP_LATENCY_MID (0x00B702A0) +#define PMM_TOP_SOC_WAKEUP_LATENCY_MID___RWC QCSR_REG_RO +#define PMM_TOP_SOC_WAKEUP_LATENCY_MID___POR 0x00000000 +#define PMM_TOP_SOC_WAKEUP_LATENCY_MID__SOC_WAKEUP_LATENCY_MID_VAL___POR 0x00000000 +#define PMM_TOP_SOC_WAKEUP_LATENCY_MID__SOC_WAKEUP_LATENCY_MID_VAL___M 0xFFFFFFFF +#define PMM_TOP_SOC_WAKEUP_LATENCY_MID__SOC_WAKEUP_LATENCY_MID_VAL___S 0 +#define PMM_TOP_SOC_WAKEUP_LATENCY_MID___M 0xFFFFFFFF +#define PMM_TOP_SOC_WAKEUP_LATENCY_MID___S 0 + +#define PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MIN (0x00B702A4) +#define PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MIN___RWC QCSR_REG_RO +#define PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MIN___POR 0xFFFFFFFF +#define PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MIN__PMM_TOP_WAKEUP_LATENCY_MIN_VAL___POR 0xFFFFFFFF +#define PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MIN__PMM_TOP_WAKEUP_LATENCY_MIN_VAL___M 0xFFFFFFFF +#define PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MIN__PMM_TOP_WAKEUP_LATENCY_MIN_VAL___S 0 +#define PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MIN___M 0xFFFFFFFF +#define PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MIN___S 0 + +#define PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MAX (0x00B702A8) +#define PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MAX___RWC QCSR_REG_RO +#define PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MAX___POR 0x00000000 +#define PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MAX__PMM_TOP_WAKEUP_LATENCY_MAX_VAL___POR 0x00000000 +#define PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MAX__PMM_TOP_WAKEUP_LATENCY_MAX_VAL___M 0xFFFFFFFF +#define PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MAX__PMM_TOP_WAKEUP_LATENCY_MAX_VAL___S 0 +#define PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MAX___M 0xFFFFFFFF +#define PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MAX___S 0 + +#define PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MID (0x00B702AC) +#define PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MID___RWC QCSR_REG_RO +#define PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MID___POR 0x00000000 +#define PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MID__PMM_TOP_WAKEUP_LATENCY_MID_VAL___POR 0x00000000 +#define PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MID__PMM_TOP_WAKEUP_LATENCY_MID_VAL___M 0xFFFFFFFF +#define PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MID__PMM_TOP_WAKEUP_LATENCY_MID_VAL___S 0 +#define PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MID___M 0xFFFFFFFF +#define PMM_TOP_PMM_TOP_WAKEUP_LATENCY_MID___S 0 + + +#define RET_AHB_BASE (0x00C90000) + +#define RET_AHB_AHB_PL1 (0x00C90000) +#define RET_AHB_AHB_PL1___RWC QCSR_REG_RW +#define RET_AHB_AHB_PL1___POR 0x00000001 +#define RET_AHB_AHB_PL1__AHB_PL1___POR 0x1 +#define RET_AHB_AHB_PL1__AHB_PL1___M 0x0000000F +#define RET_AHB_AHB_PL1__AHB_PL1___S 0 +#define RET_AHB_AHB_PL1___M 0x0000000F +#define RET_AHB_AHB_PL1___S 0 + +#define RET_AHB_AHB_PL2 (0x00C90004) +#define RET_AHB_AHB_PL2___RWC QCSR_REG_RW +#define RET_AHB_AHB_PL2___POR 0x00000002 +#define RET_AHB_AHB_PL2__AHB_PL2___POR 0x2 +#define RET_AHB_AHB_PL2__AHB_PL2___M 0x0000000F +#define RET_AHB_AHB_PL2__AHB_PL2___S 0 +#define RET_AHB_AHB_PL2___M 0x0000000F +#define RET_AHB_AHB_PL2___S 0 + +#define RET_AHB_AHB_PL3 (0x00C90008) +#define RET_AHB_AHB_PL3___RWC QCSR_REG_RW +#define RET_AHB_AHB_PL3___POR 0x00000001 +#define RET_AHB_AHB_PL3__AHB_PL3___POR 0x1 +#define RET_AHB_AHB_PL3__AHB_PL3___M 0x0000000F +#define RET_AHB_AHB_PL3__AHB_PL3___S 0 +#define RET_AHB_AHB_PL3___M 0x0000000F +#define RET_AHB_AHB_PL3___S 0 + +#define RET_AHB_AHB_DFLT_MASTER (0x00C90048) +#define RET_AHB_AHB_DFLT_MASTER___RWC QCSR_REG_RW +#define RET_AHB_AHB_DFLT_MASTER___POR 0x00000000 +#define RET_AHB_AHB_DFLT_MASTER__AHB_DFLT_MASTER___POR 0x0 +#define RET_AHB_AHB_DFLT_MASTER__AHB_DFLT_MASTER___M 0x0000000F +#define RET_AHB_AHB_DFLT_MASTER__AHB_DFLT_MASTER___S 0 +#define RET_AHB_AHB_DFLT_MASTER___M 0x0000000F +#define RET_AHB_AHB_DFLT_MASTER___S 0 + +#define RET_AHB_AHB_VERSION_ID (0x00C90090) +#define RET_AHB_AHB_VERSION_ID___RWC QCSR_REG_RO +#define RET_AHB_AHB_VERSION_ID___POR 0x3231312A +#define RET_AHB_AHB_VERSION_ID__AHB_VERSION_ID___POR 0x3231312A +#define RET_AHB_AHB_VERSION_ID__AHB_VERSION_ID___M 0xFFFFFFFF +#define RET_AHB_AHB_VERSION_ID__AHB_VERSION_ID___S 0 +#define RET_AHB_AHB_VERSION_ID___M 0xFFFFFFFF +#define RET_AHB_AHB_VERSION_ID___S 0 + + +#define WAHB_TSLV_BASE (0x00CA0000) + +#define WAHB_TSLV_ABT_HW_VERSION (0x00CA0000) +#define WAHB_TSLV_ABT_HW_VERSION___RWC QCSR_REG_RO +#define WAHB_TSLV_ABT_HW_VERSION___POR 0x10000000 +#define WAHB_TSLV_ABT_HW_VERSION__MAJOR___POR 0x1 +#define WAHB_TSLV_ABT_HW_VERSION__MINOR___POR 0x000 +#define WAHB_TSLV_ABT_HW_VERSION__STEP___POR 0x0000 +#define WAHB_TSLV_ABT_HW_VERSION__MAJOR___M 0xF0000000 +#define WAHB_TSLV_ABT_HW_VERSION__MAJOR___S 28 +#define WAHB_TSLV_ABT_HW_VERSION__MINOR___M 0x0FFF0000 +#define WAHB_TSLV_ABT_HW_VERSION__MINOR___S 16 +#define WAHB_TSLV_ABT_HW_VERSION__STEP___M 0x0000FFFF +#define WAHB_TSLV_ABT_HW_VERSION__STEP___S 0 +#define WAHB_TSLV_ABT_HW_VERSION___M 0xFFFFFFFF +#define WAHB_TSLV_ABT_HW_VERSION___S 0 + +#define WAHB_TSLV_ABT_INST_ID (0x00CA0004) +#define WAHB_TSLV_ABT_INST_ID___RWC QCSR_REG_RW +#define WAHB_TSLV_ABT_INST_ID___POR 0x00000000 +#define WAHB_TSLV_ABT_INST_ID__INSTID___POR 0x00000000 +#define WAHB_TSLV_ABT_INST_ID__INSTID___M 0xFFFFFFFF +#define WAHB_TSLV_ABT_INST_ID__INSTID___S 0 +#define WAHB_TSLV_ABT_INST_ID___M 0xFFFFFFFF +#define WAHB_TSLV_ABT_INST_ID___S 0 + +#define WAHB_TSLV_ABT_NUM_SLAVES (0x00CA0008) +#define WAHB_TSLV_ABT_NUM_SLAVES___RWC QCSR_REG_RO +#define WAHB_TSLV_ABT_NUM_SLAVES___POR 0x00000005 +#define WAHB_TSLV_ABT_NUM_SLAVES__NUMSLAVES___POR 0x5 +#define WAHB_TSLV_ABT_NUM_SLAVES__NUMSLAVES___M 0x0000003F +#define WAHB_TSLV_ABT_NUM_SLAVES__NUMSLAVES___S 0 +#define WAHB_TSLV_ABT_NUM_SLAVES___M 0x0000003F +#define WAHB_TSLV_ABT_NUM_SLAVES___S 0 + +#define WAHB_TSLV_ABT_TIMER_LOADVAL (0x00CA000C) +#define WAHB_TSLV_ABT_TIMER_LOADVAL___RWC QCSR_REG_RW +#define WAHB_TSLV_ABT_TIMER_LOADVAL___POR 0x000000FF +#define WAHB_TSLV_ABT_TIMER_LOADVAL__LOADVAL___POR 0xFF +#define WAHB_TSLV_ABT_TIMER_LOADVAL__LOADVAL___M 0x000000FF +#define WAHB_TSLV_ABT_TIMER_LOADVAL__LOADVAL___S 0 +#define WAHB_TSLV_ABT_TIMER_LOADVAL___M 0x000000FF +#define WAHB_TSLV_ABT_TIMER_LOADVAL___S 0 + +#define WAHB_TSLV_ABT_TIMER_MODE (0x00CA0010) +#define WAHB_TSLV_ABT_TIMER_MODE___RWC QCSR_REG_RW +#define WAHB_TSLV_ABT_TIMER_MODE___POR 0x00000000 +#define WAHB_TSLV_ABT_TIMER_MODE__MODE___POR 0x0 +#define WAHB_TSLV_ABT_TIMER_MODE__MODE___M 0x00000001 +#define WAHB_TSLV_ABT_TIMER_MODE__MODE___S 0 +#define WAHB_TSLV_ABT_TIMER_MODE___M 0x00000001 +#define WAHB_TSLV_ABT_TIMER_MODE___S 0 + +#define WAHB_TSLV_ABT_INTR_STATUS (0x00CA0014) +#define WAHB_TSLV_ABT_INTR_STATUS___RWC QCSR_REG_RO +#define WAHB_TSLV_ABT_INTR_STATUS___POR 0x00000000 +#define WAHB_TSLV_ABT_INTR_STATUS__INTRSTATUS___POR 0x0 +#define WAHB_TSLV_ABT_INTR_STATUS__INTRSTATUS___M 0x00000001 +#define WAHB_TSLV_ABT_INTR_STATUS__INTRSTATUS___S 0 +#define WAHB_TSLV_ABT_INTR_STATUS___M 0x00000001 +#define WAHB_TSLV_ABT_INTR_STATUS___S 0 + +#define WAHB_TSLV_ABT_INTR_CLEAR (0x00CA0018) +#define WAHB_TSLV_ABT_INTR_CLEAR___RWC QCSR_REG_WO +#define WAHB_TSLV_ABT_INTR_CLEAR___POR 0x00000000 +#define WAHB_TSLV_ABT_INTR_CLEAR__INTRCLEAR___POR 0x0 +#define WAHB_TSLV_ABT_INTR_CLEAR__INTRCLEAR___M 0x00000001 +#define WAHB_TSLV_ABT_INTR_CLEAR__INTRCLEAR___S 0 +#define WAHB_TSLV_ABT_INTR_CLEAR___M 0x00000001 +#define WAHB_TSLV_ABT_INTR_CLEAR___S 0 + +#define WAHB_TSLV_ABT_INTR_ENABLE (0x00CA001C) +#define WAHB_TSLV_ABT_INTR_ENABLE___RWC QCSR_REG_RW +#define WAHB_TSLV_ABT_INTR_ENABLE___POR 0x00000000 +#define WAHB_TSLV_ABT_INTR_ENABLE__INTRENABLE___POR 0x0 +#define WAHB_TSLV_ABT_INTR_ENABLE__INTRENABLE___M 0x00000001 +#define WAHB_TSLV_ABT_INTR_ENABLE__INTRENABLE___S 0 +#define WAHB_TSLV_ABT_INTR_ENABLE___M 0x00000001 +#define WAHB_TSLV_ABT_INTR_ENABLE___S 0 + +#define WAHB_TSLV_ABT_SYND_VALID (0x00CA0020) +#define WAHB_TSLV_ABT_SYND_VALID___RWC QCSR_REG_RO +#define WAHB_TSLV_ABT_SYND_VALID___POR 0x00000000 +#define WAHB_TSLV_ABT_SYND_VALID__SYNDVALID___POR 0x0 +#define WAHB_TSLV_ABT_SYND_VALID__SYNDVALID___M 0x00000001 +#define WAHB_TSLV_ABT_SYND_VALID__SYNDVALID___S 0 +#define WAHB_TSLV_ABT_SYND_VALID___M 0x00000001 +#define WAHB_TSLV_ABT_SYND_VALID___S 0 + +#define WAHB_TSLV_ABT_SYND_CLEAR (0x00CA0024) +#define WAHB_TSLV_ABT_SYND_CLEAR___RWC QCSR_REG_WO +#define WAHB_TSLV_ABT_SYND_CLEAR___POR 0x00000000 +#define WAHB_TSLV_ABT_SYND_CLEAR__SYNDCLEAR___POR 0x0 +#define WAHB_TSLV_ABT_SYND_CLEAR__SYNDCLEAR___M 0x00000001 +#define WAHB_TSLV_ABT_SYND_CLEAR__SYNDCLEAR___S 0 +#define WAHB_TSLV_ABT_SYND_CLEAR___M 0x00000001 +#define WAHB_TSLV_ABT_SYND_CLEAR___S 0 + +#define WAHB_TSLV_ABT_SYND_ID (0x00CA0028) +#define WAHB_TSLV_ABT_SYND_ID___RWC QCSR_REG_RO +#define WAHB_TSLV_ABT_SYND_ID___POR 0x00000000 +#define WAHB_TSLV_ABT_SYND_ID__BID___POR 0x0 +#define WAHB_TSLV_ABT_SYND_ID__PID___POR 0x00 +#define WAHB_TSLV_ABT_SYND_ID__MID___POR 0x00 +#define WAHB_TSLV_ABT_SYND_ID__BID___M 0x0000E000 +#define WAHB_TSLV_ABT_SYND_ID__BID___S 13 +#define WAHB_TSLV_ABT_SYND_ID__PID___M 0x00001F00 +#define WAHB_TSLV_ABT_SYND_ID__PID___S 8 +#define WAHB_TSLV_ABT_SYND_ID__MID___M 0x000000FF +#define WAHB_TSLV_ABT_SYND_ID__MID___S 0 +#define WAHB_TSLV_ABT_SYND_ID___M 0x0000FFFF +#define WAHB_TSLV_ABT_SYND_ID___S 0 + +#define WAHB_TSLV_ABT_SYND_ADDR0 (0x00CA002C) +#define WAHB_TSLV_ABT_SYND_ADDR0___RWC QCSR_REG_RO +#define WAHB_TSLV_ABT_SYND_ADDR0___POR 0x00000000 +#define WAHB_TSLV_ABT_SYND_ADDR0__SYNDADDR0___POR 0x00000000 +#define WAHB_TSLV_ABT_SYND_ADDR0__SYNDADDR0___M 0xFFFFFFFF +#define WAHB_TSLV_ABT_SYND_ADDR0__SYNDADDR0___S 0 +#define WAHB_TSLV_ABT_SYND_ADDR0___M 0xFFFFFFFF +#define WAHB_TSLV_ABT_SYND_ADDR0___S 0 + +#define WAHB_TSLV_ABT_SYND_ADDR1 (0x00CA0030) +#define WAHB_TSLV_ABT_SYND_ADDR1___RWC QCSR_REG_RO +#define WAHB_TSLV_ABT_SYND_ADDR1___POR 0x00000000 +#define WAHB_TSLV_ABT_SYND_ADDR1__SYNDADDR1___POR 0x00000000 +#define WAHB_TSLV_ABT_SYND_ADDR1__SYNDADDR1___M 0xFFFFFFFF +#define WAHB_TSLV_ABT_SYND_ADDR1__SYNDADDR1___S 0 +#define WAHB_TSLV_ABT_SYND_ADDR1___M 0xFFFFFFFF +#define WAHB_TSLV_ABT_SYND_ADDR1___S 0 + +#define WAHB_TSLV_ABT_SYND_HREADY (0x00CA0034) +#define WAHB_TSLV_ABT_SYND_HREADY___RWC QCSR_REG_RO +#define WAHB_TSLV_ABT_SYND_HREADY___POR 0xFFFFFFFF +#define WAHB_TSLV_ABT_SYND_HREADY__SYNDHREADY___POR 0xFFFFFFFF +#define WAHB_TSLV_ABT_SYND_HREADY__SYNDHREADY___M 0xFFFFFFFF +#define WAHB_TSLV_ABT_SYND_HREADY__SYNDHREADY___S 0 +#define WAHB_TSLV_ABT_SYND_HREADY___M 0xFFFFFFFF +#define WAHB_TSLV_ABT_SYND_HREADY___S 0 + + +#define CC_BASE (0x00CB0000) + +#define CC_WCSS_NOC_CMD_RCGR (0x00CB0040) +#define CC_WCSS_NOC_CMD_RCGR___RWC QCSR_REG_RW +#define CC_WCSS_NOC_CMD_RCGR___POR 0x00000000 +#define CC_WCSS_NOC_CMD_RCGR__ROOT_OFF___POR 0x0 +#define CC_WCSS_NOC_CMD_RCGR__DIRTY_CFG_RCGR___POR 0x0 +#define CC_WCSS_NOC_CMD_RCGR__ROOT_EN___POR 0x0 +#define CC_WCSS_NOC_CMD_RCGR__UPDATE___POR 0x0 +#define CC_WCSS_NOC_CMD_RCGR__ROOT_OFF___M 0x80000000 +#define CC_WCSS_NOC_CMD_RCGR__ROOT_OFF___S 31 +#define CC_WCSS_NOC_CMD_RCGR__DIRTY_CFG_RCGR___M 0x00000010 +#define CC_WCSS_NOC_CMD_RCGR__DIRTY_CFG_RCGR___S 4 +#define CC_WCSS_NOC_CMD_RCGR__ROOT_EN___M 0x00000002 +#define CC_WCSS_NOC_CMD_RCGR__ROOT_EN___S 1 +#define CC_WCSS_NOC_CMD_RCGR__ROOT_EN__DISABLE 0x0 +#define CC_WCSS_NOC_CMD_RCGR__ROOT_EN__ENABLE 0x1 +#define CC_WCSS_NOC_CMD_RCGR__UPDATE___M 0x00000001 +#define CC_WCSS_NOC_CMD_RCGR__UPDATE___S 0 +#define CC_WCSS_NOC_CMD_RCGR__UPDATE__DISABLE 0x0 +#define CC_WCSS_NOC_CMD_RCGR__UPDATE__ENABLE 0x1 +#define CC_WCSS_NOC_CMD_RCGR___M 0x80000013 +#define CC_WCSS_NOC_CMD_RCGR___S 0 + +#define CC_WCSS_NOC_CFG_RCGR (0x00CB0044) +#define CC_WCSS_NOC_CFG_RCGR___RWC QCSR_REG_RW +#define CC_WCSS_NOC_CFG_RCGR___POR 0x00100000 +#define CC_WCSS_NOC_CFG_RCGR__HW_CLK_CONTROL___POR 0x1 +#define CC_WCSS_NOC_CFG_RCGR__RCGLITE_DISABLE___POR 0x0 +#define CC_WCSS_NOC_CFG_RCGR__SRC_SEL___POR 0x0 +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV___POR 0x00 +#define CC_WCSS_NOC_CFG_RCGR__HW_CLK_CONTROL___M 0x00100000 +#define CC_WCSS_NOC_CFG_RCGR__HW_CLK_CONTROL___S 20 +#define CC_WCSS_NOC_CFG_RCGR__HW_CLK_CONTROL__DISABLE 0x0 +#define CC_WCSS_NOC_CFG_RCGR__HW_CLK_CONTROL__ENABLE 0x1 +#define CC_WCSS_NOC_CFG_RCGR__RCGLITE_DISABLE___M 0x00010000 +#define CC_WCSS_NOC_CFG_RCGR__RCGLITE_DISABLE___S 16 +#define CC_WCSS_NOC_CFG_RCGR__RCGLITE_DISABLE__RCGLITE_ENABLED 0x0 +#define CC_WCSS_NOC_CFG_RCGR__RCGLITE_DISABLE__RCGLITE_DISABLED 0x1 +#define CC_WCSS_NOC_CFG_RCGR__SRC_SEL___M 0x00000700 +#define CC_WCSS_NOC_CFG_RCGR__SRC_SEL___S 8 +#define CC_WCSS_NOC_CFG_RCGR__SRC_SEL__SRC0 0x0 +#define CC_WCSS_NOC_CFG_RCGR__SRC_SEL__SRC1 0x1 +#define CC_WCSS_NOC_CFG_RCGR__SRC_SEL__SRC2 0x2 +#define CC_WCSS_NOC_CFG_RCGR__SRC_SEL__SRC3 0x3 +#define CC_WCSS_NOC_CFG_RCGR__SRC_SEL__SRC4 0x4 +#define CC_WCSS_NOC_CFG_RCGR__SRC_SEL__SRC5 0x5 +#define CC_WCSS_NOC_CFG_RCGR__SRC_SEL__SRC6 0x6 +#define CC_WCSS_NOC_CFG_RCGR__SRC_SEL__SRC7 0x7 +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV___M 0x0000001F +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV___S 0 +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV__BYPASS 0x00 +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV1 0x01 +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV1_5 0x02 +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV2 0x03 +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV2_5 0x04 +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV3 0x05 +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV3_5 0x06 +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV4 0x07 +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV4_5 0x08 +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV5 0x09 +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV5_5 0x0A +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV6 0x0B +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV6_5 0x0C +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV7 0x0D +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV7_5 0x0E +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV8 0x0F +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV8_5 0x10 +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV9 0x11 +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV9_5 0x12 +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV10 0x13 +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV10_5 0x14 +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV11 0x15 +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV11_5 0x16 +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV12 0x17 +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV12_5 0x18 +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV13 0x19 +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV13_5 0x1A +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV14 0x1B +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV14_5 0x1C +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV15 0x1D +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV15_5 0x1E +#define CC_WCSS_NOC_CFG_RCGR__SRC_DIV__DIV16 0x1F +#define CC_WCSS_NOC_CFG_RCGR___M 0x0011071F +#define CC_WCSS_NOC_CFG_RCGR___S 0 + +#define CC_WCSS_NOC_AFTERDIV_GFMUX_CDIVR (0x00CB0058) +#define CC_WCSS_NOC_AFTERDIV_GFMUX_CDIVR___RWC QCSR_REG_RW +#define CC_WCSS_NOC_AFTERDIV_GFMUX_CDIVR___POR 0x00000000 +#define CC_WCSS_NOC_AFTERDIV_GFMUX_CDIVR__CLK_DIV___POR 0x0 +#define CC_WCSS_NOC_AFTERDIV_GFMUX_CDIVR__CLK_DIV___M 0x0000000F +#define CC_WCSS_NOC_AFTERDIV_GFMUX_CDIVR__CLK_DIV___S 0 +#define CC_WCSS_NOC_AFTERDIV_GFMUX_CDIVR___M 0x0000000F +#define CC_WCSS_NOC_AFTERDIV_GFMUX_CDIVR___S 0 + +#define CC_WCSS_AHB_CDIVR (0x00CB005C) +#define CC_WCSS_AHB_CDIVR___RWC QCSR_REG_RW +#define CC_WCSS_AHB_CDIVR___POR 0x00000002 +#define CC_WCSS_AHB_CDIVR__CLK_DIV___POR 0x2 +#define CC_WCSS_AHB_CDIVR__CLK_DIV___M 0x0000000F +#define CC_WCSS_AHB_CDIVR__CLK_DIV___S 0 +#define CC_WCSS_AHB_CDIVR___M 0x0000000F +#define CC_WCSS_AHB_CDIVR___S 0 + +#define CC_WCSS_TOP_AXI_CBCR (0x00CB0060) +#define CC_WCSS_TOP_AXI_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_TOP_AXI_CBCR___POR 0x00000001 +#define CC_WCSS_TOP_AXI_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_TOP_AXI_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_TOP_AXI_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_TOP_AXI_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_TOP_AXI_CBCR__CLK_OFF___S 31 +#define CC_WCSS_TOP_AXI_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_TOP_AXI_CBCR__CLK_ARES___S 2 +#define CC_WCSS_TOP_AXI_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_TOP_AXI_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_TOP_AXI_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_TOP_AXI_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_TOP_AXI_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_TOP_AXI_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_TOP_AXI_CBCR___M 0x80000005 +#define CC_WCSS_TOP_AXI_CBCR___S 0 + +#define CC_WCSS_AXIB_AXI_S_CBCR (0x00CB0064) +#define CC_WCSS_AXIB_AXI_S_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_AXIB_AXI_S_CBCR___POR 0x00000001 +#define CC_WCSS_AXIB_AXI_S_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_AXIB_AXI_S_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_AXIB_AXI_S_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_AXIB_AXI_S_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_AXIB_AXI_S_CBCR__CLK_OFF___S 31 +#define CC_WCSS_AXIB_AXI_S_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_AXIB_AXI_S_CBCR__CLK_ARES___S 2 +#define CC_WCSS_AXIB_AXI_S_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_AXIB_AXI_S_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_AXIB_AXI_S_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_AXIB_AXI_S_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_AXIB_AXI_S_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_AXIB_AXI_S_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_AXIB_AXI_S_CBCR___M 0x80000005 +#define CC_WCSS_AXIB_AXI_S_CBCR___S 0 + +#define CC_WCSS_TOP_AHB_CBCR (0x00CB0068) +#define CC_WCSS_TOP_AHB_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_TOP_AHB_CBCR___POR 0x00000001 +#define CC_WCSS_TOP_AHB_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_TOP_AHB_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_TOP_AHB_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_TOP_AHB_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_TOP_AHB_CBCR__CLK_OFF___S 31 +#define CC_WCSS_TOP_AHB_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_TOP_AHB_CBCR__CLK_ARES___S 2 +#define CC_WCSS_TOP_AHB_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_TOP_AHB_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_TOP_AHB_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_TOP_AHB_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_TOP_AHB_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_TOP_AHB_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_TOP_AHB_CBCR___M 0x80000005 +#define CC_WCSS_TOP_AHB_CBCR___S 0 + +#define CC_WCSS_TOP_AHB_TSLV_CBCR (0x00CB006C) +#define CC_WCSS_TOP_AHB_TSLV_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_TOP_AHB_TSLV_CBCR___POR 0x00000001 +#define CC_WCSS_TOP_AHB_TSLV_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_TOP_AHB_TSLV_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_TOP_AHB_TSLV_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_TOP_AHB_TSLV_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_TOP_AHB_TSLV_CBCR__CLK_OFF___S 31 +#define CC_WCSS_TOP_AHB_TSLV_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_TOP_AHB_TSLV_CBCR__CLK_ARES___S 2 +#define CC_WCSS_TOP_AHB_TSLV_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_TOP_AHB_TSLV_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_TOP_AHB_TSLV_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_TOP_AHB_TSLV_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_TOP_AHB_TSLV_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_TOP_AHB_TSLV_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_TOP_AHB_TSLV_CBCR___M 0x80000005 +#define CC_WCSS_TOP_AHB_TSLV_CBCR___S 0 + +#define CC_WCSS_TOP_SLP_CBCR (0x00CB0070) +#define CC_WCSS_TOP_SLP_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_TOP_SLP_CBCR___POR 0x00000001 +#define CC_WCSS_TOP_SLP_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_TOP_SLP_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_TOP_SLP_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_TOP_SLP_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_TOP_SLP_CBCR__CLK_OFF___S 31 +#define CC_WCSS_TOP_SLP_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_TOP_SLP_CBCR__CLK_ARES___S 2 +#define CC_WCSS_TOP_SLP_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_TOP_SLP_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_TOP_SLP_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_TOP_SLP_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_TOP_SLP_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_TOP_SLP_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_TOP_SLP_CBCR___M 0x80000005 +#define CC_WCSS_TOP_SLP_CBCR___S 0 + +#define CC_WCSS_TOP_REF_CBCR (0x00CB0074) +#define CC_WCSS_TOP_REF_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_TOP_REF_CBCR___POR 0x00000001 +#define CC_WCSS_TOP_REF_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_TOP_REF_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_TOP_REF_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_TOP_REF_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_TOP_REF_CBCR__CLK_OFF___S 31 +#define CC_WCSS_TOP_REF_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_TOP_REF_CBCR__CLK_ARES___S 2 +#define CC_WCSS_TOP_REF_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_TOP_REF_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_TOP_REF_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_TOP_REF_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_TOP_REF_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_TOP_REF_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_TOP_REF_CBCR___M 0x80000005 +#define CC_WCSS_TOP_REF_CBCR___S 0 + +#define CC_WCSS_TOP_DBG_GDSC_REF_CBCR (0x00CB0078) +#define CC_WCSS_TOP_DBG_GDSC_REF_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_TOP_DBG_GDSC_REF_CBCR___POR 0x00000001 +#define CC_WCSS_TOP_DBG_GDSC_REF_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_TOP_DBG_GDSC_REF_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_TOP_DBG_GDSC_REF_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_TOP_DBG_GDSC_REF_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_TOP_DBG_GDSC_REF_CBCR__CLK_OFF___S 31 +#define CC_WCSS_TOP_DBG_GDSC_REF_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_TOP_DBG_GDSC_REF_CBCR__CLK_ARES___S 2 +#define CC_WCSS_TOP_DBG_GDSC_REF_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_TOP_DBG_GDSC_REF_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_TOP_DBG_GDSC_REF_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_TOP_DBG_GDSC_REF_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_TOP_DBG_GDSC_REF_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_TOP_DBG_GDSC_REF_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_TOP_DBG_GDSC_REF_CBCR___M 0x80000005 +#define CC_WCSS_TOP_DBG_GDSC_REF_CBCR___S 0 + +#define CC_WCSS_TOP_RESET_DEMET_REF_CDIVR (0x00CB007C) +#define CC_WCSS_TOP_RESET_DEMET_REF_CDIVR___RWC QCSR_REG_RW +#define CC_WCSS_TOP_RESET_DEMET_REF_CDIVR___POR 0x00000003 +#define CC_WCSS_TOP_RESET_DEMET_REF_CDIVR__CLK_DIV___POR 0x3 +#define CC_WCSS_TOP_RESET_DEMET_REF_CDIVR__CLK_DIV___M 0x00000003 +#define CC_WCSS_TOP_RESET_DEMET_REF_CDIVR__CLK_DIV___S 0 +#define CC_WCSS_TOP_RESET_DEMET_REF_CDIVR___M 0x00000003 +#define CC_WCSS_TOP_RESET_DEMET_REF_CDIVR___S 0 + +#define CC_WCSS_TOP_RESET_DEMET_REF_CBCR (0x00CB0080) +#define CC_WCSS_TOP_RESET_DEMET_REF_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_TOP_RESET_DEMET_REF_CBCR___POR 0x00000001 +#define CC_WCSS_TOP_RESET_DEMET_REF_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_TOP_RESET_DEMET_REF_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_TOP_RESET_DEMET_REF_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_TOP_RESET_DEMET_REF_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_TOP_RESET_DEMET_REF_CBCR__CLK_OFF___S 31 +#define CC_WCSS_TOP_RESET_DEMET_REF_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_TOP_RESET_DEMET_REF_CBCR__CLK_ARES___S 2 +#define CC_WCSS_TOP_RESET_DEMET_REF_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_TOP_RESET_DEMET_REF_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_TOP_RESET_DEMET_REF_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_TOP_RESET_DEMET_REF_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_TOP_RESET_DEMET_REF_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_TOP_RESET_DEMET_REF_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_TOP_RESET_DEMET_REF_CBCR___M 0x80000005 +#define CC_WCSS_TOP_RESET_DEMET_REF_CBCR___S 0 + +#define CC_WCSS_PMM_LPO_CBCR (0x00CB0084) +#define CC_WCSS_PMM_LPO_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_PMM_LPO_CBCR___POR 0x00000001 +#define CC_WCSS_PMM_LPO_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_PMM_LPO_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_PMM_LPO_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_PMM_LPO_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_PMM_LPO_CBCR__CLK_OFF___S 31 +#define CC_WCSS_PMM_LPO_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_PMM_LPO_CBCR__CLK_ARES___S 2 +#define CC_WCSS_PMM_LPO_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_PMM_LPO_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_PMM_LPO_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_PMM_LPO_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_PMM_LPO_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_PMM_LPO_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_PMM_LPO_CBCR___M 0x80000005 +#define CC_WCSS_PMM_LPO_CBCR___S 0 + +#define CC_WCSS_WFSS_PMM_CDIVR (0x00CB0088) +#define CC_WCSS_WFSS_PMM_CDIVR___RWC QCSR_REG_RW +#define CC_WCSS_WFSS_PMM_CDIVR___POR 0x00000003 +#define CC_WCSS_WFSS_PMM_CDIVR__CLK_DIV___POR 0x3 +#define CC_WCSS_WFSS_PMM_CDIVR__CLK_DIV___M 0x00000003 +#define CC_WCSS_WFSS_PMM_CDIVR__CLK_DIV___S 0 +#define CC_WCSS_WFSS_PMM_CDIVR___M 0x00000003 +#define CC_WCSS_WFSS_PMM_CDIVR___S 0 + +#define CC_WCSS_WFSS_PMM_CBCR (0x00CB008C) +#define CC_WCSS_WFSS_PMM_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_WFSS_PMM_CBCR___POR 0x00000001 +#define CC_WCSS_WFSS_PMM_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_WFSS_PMM_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_WFSS_PMM_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_WFSS_PMM_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_WFSS_PMM_CBCR__CLK_OFF___S 31 +#define CC_WCSS_WFSS_PMM_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_WFSS_PMM_CBCR__CLK_ARES___S 2 +#define CC_WCSS_WFSS_PMM_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_WFSS_PMM_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_WFSS_PMM_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_WFSS_PMM_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_WFSS_PMM_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_WFSS_PMM_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_WFSS_PMM_CBCR___M 0x80000005 +#define CC_WCSS_WFSS_PMM_CBCR___S 0 + +#define CC_WCSS_WLAN1_BCR (0x00CB0090) +#define CC_WCSS_WLAN1_BCR___RWC QCSR_REG_RW +#define CC_WCSS_WLAN1_BCR___POR 0x00000000 +#define CC_WCSS_WLAN1_BCR__BLK_ARES___POR 0x0 +#define CC_WCSS_WLAN1_BCR__BLK_ARES___M 0x00000001 +#define CC_WCSS_WLAN1_BCR__BLK_ARES___S 0 +#define CC_WCSS_WLAN1_BCR__BLK_ARES__DISABLE 0x0 +#define CC_WCSS_WLAN1_BCR__BLK_ARES__ENABLE 0x1 +#define CC_WCSS_WLAN1_BCR___M 0x00000001 +#define CC_WCSS_WLAN1_BCR___S 0 + +#define CC_WCSS_WLAN1_GDSCR (0x00CB0094) +#define CC_WCSS_WLAN1_GDSCR___RWC QCSR_REG_RW +#define CC_WCSS_WLAN1_GDSCR___POR 0x0022F001 +#define CC_WCSS_WLAN1_GDSCR__PWR_ON___POR 0x0 +#define CC_WCSS_WLAN1_GDSCR__GDSC_STATE___POR 0x0 +#define CC_WCSS_WLAN1_GDSCR__EN_REST_WAIT___POR 0x2 +#define CC_WCSS_WLAN1_GDSCR__EN_FEW_WAIT___POR 0x2 +#define CC_WCSS_WLAN1_GDSCR__CLK_DIS_WAIT___POR 0xF +#define CC_WCSS_WLAN1_GDSCR__RETAIN_FF_ENABLE___POR 0x0 +#define CC_WCSS_WLAN1_GDSCR__RESTORE___POR 0x0 +#define CC_WCSS_WLAN1_GDSCR__SAVE___POR 0x0 +#define CC_WCSS_WLAN1_GDSCR__RETAIN___POR 0x0 +#define CC_WCSS_WLAN1_GDSCR__EN_REST___POR 0x0 +#define CC_WCSS_WLAN1_GDSCR__EN_FEW___POR 0x0 +#define CC_WCSS_WLAN1_GDSCR__CLAMP_IO___POR 0x0 +#define CC_WCSS_WLAN1_GDSCR__CLK_DISABLE___POR 0x0 +#define CC_WCSS_WLAN1_GDSCR__PD_ARES___POR 0x0 +#define CC_WCSS_WLAN1_GDSCR__SW_OVERRIDE___POR 0x0 +#define CC_WCSS_WLAN1_GDSCR__HW_CONTROL___POR 0x0 +#define CC_WCSS_WLAN1_GDSCR__SW_COLLAPSE___POR 0x1 +#define CC_WCSS_WLAN1_GDSCR__PWR_ON___M 0x80000000 +#define CC_WCSS_WLAN1_GDSCR__PWR_ON___S 31 +#define CC_WCSS_WLAN1_GDSCR__GDSC_STATE___M 0x78000000 +#define CC_WCSS_WLAN1_GDSCR__GDSC_STATE___S 27 +#define CC_WCSS_WLAN1_GDSCR__EN_REST_WAIT___M 0x00F00000 +#define CC_WCSS_WLAN1_GDSCR__EN_REST_WAIT___S 20 +#define CC_WCSS_WLAN1_GDSCR__EN_FEW_WAIT___M 0x000F0000 +#define CC_WCSS_WLAN1_GDSCR__EN_FEW_WAIT___S 16 +#define CC_WCSS_WLAN1_GDSCR__CLK_DIS_WAIT___M 0x0000F000 +#define CC_WCSS_WLAN1_GDSCR__CLK_DIS_WAIT___S 12 +#define CC_WCSS_WLAN1_GDSCR__RETAIN_FF_ENABLE___M 0x00000800 +#define CC_WCSS_WLAN1_GDSCR__RETAIN_FF_ENABLE___S 11 +#define CC_WCSS_WLAN1_GDSCR__RETAIN_FF_ENABLE__DISABLE 0x0 +#define CC_WCSS_WLAN1_GDSCR__RETAIN_FF_ENABLE__ENABLE 0x1 +#define CC_WCSS_WLAN1_GDSCR__RESTORE___M 0x00000400 +#define CC_WCSS_WLAN1_GDSCR__RESTORE___S 10 +#define CC_WCSS_WLAN1_GDSCR__RESTORE__DISABLE 0x0 +#define CC_WCSS_WLAN1_GDSCR__RESTORE__ENABLE 0x1 +#define CC_WCSS_WLAN1_GDSCR__SAVE___M 0x00000200 +#define CC_WCSS_WLAN1_GDSCR__SAVE___S 9 +#define CC_WCSS_WLAN1_GDSCR__SAVE__DISABLE 0x0 +#define CC_WCSS_WLAN1_GDSCR__SAVE__ENABLE 0x1 +#define CC_WCSS_WLAN1_GDSCR__RETAIN___M 0x00000100 +#define CC_WCSS_WLAN1_GDSCR__RETAIN___S 8 +#define CC_WCSS_WLAN1_GDSCR__RETAIN__DISABLE 0x0 +#define CC_WCSS_WLAN1_GDSCR__RETAIN__ENABLE 0x1 +#define CC_WCSS_WLAN1_GDSCR__EN_REST___M 0x00000080 +#define CC_WCSS_WLAN1_GDSCR__EN_REST___S 7 +#define CC_WCSS_WLAN1_GDSCR__EN_REST__DISABLE 0x0 +#define CC_WCSS_WLAN1_GDSCR__EN_REST__ENABLE 0x1 +#define CC_WCSS_WLAN1_GDSCR__EN_FEW___M 0x00000040 +#define CC_WCSS_WLAN1_GDSCR__EN_FEW___S 6 +#define CC_WCSS_WLAN1_GDSCR__EN_FEW__DISABLE 0x0 +#define CC_WCSS_WLAN1_GDSCR__EN_FEW__ENABLE 0x1 +#define CC_WCSS_WLAN1_GDSCR__CLAMP_IO___M 0x00000020 +#define CC_WCSS_WLAN1_GDSCR__CLAMP_IO___S 5 +#define CC_WCSS_WLAN1_GDSCR__CLAMP_IO__DISABLE 0x0 +#define CC_WCSS_WLAN1_GDSCR__CLAMP_IO__ENABLE 0x1 +#define CC_WCSS_WLAN1_GDSCR__CLK_DISABLE___M 0x00000010 +#define CC_WCSS_WLAN1_GDSCR__CLK_DISABLE___S 4 +#define CC_WCSS_WLAN1_GDSCR__CLK_DISABLE__CLK_NOT_DISABLE 0x0 +#define CC_WCSS_WLAN1_GDSCR__CLK_DISABLE__CLK_DISABLE 0x1 +#define CC_WCSS_WLAN1_GDSCR__PD_ARES___M 0x00000008 +#define CC_WCSS_WLAN1_GDSCR__PD_ARES___S 3 +#define CC_WCSS_WLAN1_GDSCR__PD_ARES__NO_RESET 0x0 +#define CC_WCSS_WLAN1_GDSCR__PD_ARES__RESET 0x1 +#define CC_WCSS_WLAN1_GDSCR__SW_OVERRIDE___M 0x00000004 +#define CC_WCSS_WLAN1_GDSCR__SW_OVERRIDE___S 2 +#define CC_WCSS_WLAN1_GDSCR__SW_OVERRIDE__DISABLE 0x0 +#define CC_WCSS_WLAN1_GDSCR__SW_OVERRIDE__ENABLE 0x1 +#define CC_WCSS_WLAN1_GDSCR__HW_CONTROL___M 0x00000002 +#define CC_WCSS_WLAN1_GDSCR__HW_CONTROL___S 1 +#define CC_WCSS_WLAN1_GDSCR__HW_CONTROL__DISABLE 0x0 +#define CC_WCSS_WLAN1_GDSCR__HW_CONTROL__ENABLE 0x1 +#define CC_WCSS_WLAN1_GDSCR__SW_COLLAPSE___M 0x00000001 +#define CC_WCSS_WLAN1_GDSCR__SW_COLLAPSE___S 0 +#define CC_WCSS_WLAN1_GDSCR__SW_COLLAPSE__DISABLE 0x0 +#define CC_WCSS_WLAN1_GDSCR__SW_COLLAPSE__ENABLE 0x1 +#define CC_WCSS_WLAN1_GDSCR___M 0xF8FFFFFF +#define CC_WCSS_WLAN1_GDSCR___S 0 + +#define CC_WCSS_WLAN1_CFG_GDSCR (0x00CB0098) +#define CC_WCSS_WLAN1_CFG_GDSCR___RWC QCSR_REG_RW +#define CC_WCSS_WLAN1_CFG_GDSCR___POR 0x00088000 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_SPARE_CTRL_IN___POR 0x0 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_SPARE_CTRL_OUT___POR 0x0 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_PWR_DWN_START___POR 0x0 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_PWR_UP_START___POR 0x0 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_CFG_FSM_STATE_STATUS___POR 0x0 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_MEM_PWR_ACK_STATUS___POR 0x1 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_ENR_ACK_STATUS___POR 0x0 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_ENF_ACK_STATUS___POR 0x0 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_POWER_UP_COMPLETE___POR 0x0 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_POWER_DOWN_COMPLETE___POR 0x1 +#define CC_WCSS_WLAN1_CFG_GDSCR__SOFTWARE_CONTROL_OVERRIDE___POR 0x0 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_HANDSHAKE_DIS___POR 0x0 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_MEM_PERI_FORCE_IN_SW___POR 0x0 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_MEM_CORE_FORCE_IN_SW___POR 0x0 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_PHASE_RESET_EN_SW___POR 0x0 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_PHASE_RESET_DELAY_COUNT_SW___POR 0x0 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_PSCBC_PWR_DWN_SW___POR 0x0 +#define CC_WCSS_WLAN1_CFG_GDSCR__UNCLAMP_IO_SOFTWARE_OVERRIDE___POR 0x0 +#define CC_WCSS_WLAN1_CFG_GDSCR__SAVE_RESTORE_SOFTWARE_OVERRIDE___POR 0x0 +#define CC_WCSS_WLAN1_CFG_GDSCR__CLAMP_IO_SOFTWARE_OVERRIDE___POR 0x0 +#define CC_WCSS_WLAN1_CFG_GDSCR__DISABLE_CLK_SOFTWARE_OVERRIDE___POR 0x0 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_SPARE_CTRL_IN___M 0xF0000000 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_SPARE_CTRL_IN___S 28 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_SPARE_CTRL_OUT___M 0x0C000000 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_SPARE_CTRL_OUT___S 26 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_PWR_DWN_START___M 0x02000000 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_PWR_DWN_START___S 25 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_PWR_UP_START___M 0x01000000 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_PWR_UP_START___S 24 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_CFG_FSM_STATE_STATUS___M 0x00F00000 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_CFG_FSM_STATE_STATUS___S 20 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_MEM_PWR_ACK_STATUS___M 0x00080000 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_MEM_PWR_ACK_STATUS___S 19 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_ENR_ACK_STATUS___M 0x00040000 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_ENR_ACK_STATUS___S 18 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_ENF_ACK_STATUS___M 0x00020000 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_ENF_ACK_STATUS___S 17 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_POWER_UP_COMPLETE___M 0x00010000 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_POWER_UP_COMPLETE___S 16 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_POWER_DOWN_COMPLETE___M 0x00008000 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_POWER_DOWN_COMPLETE___S 15 +#define CC_WCSS_WLAN1_CFG_GDSCR__SOFTWARE_CONTROL_OVERRIDE___M 0x00007800 +#define CC_WCSS_WLAN1_CFG_GDSCR__SOFTWARE_CONTROL_OVERRIDE___S 11 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_HANDSHAKE_DIS___M 0x00000400 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_HANDSHAKE_DIS___S 10 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_MEM_PERI_FORCE_IN_SW___M 0x00000200 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_MEM_PERI_FORCE_IN_SW___S 9 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_MEM_CORE_FORCE_IN_SW___M 0x00000100 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_MEM_CORE_FORCE_IN_SW___S 8 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_PHASE_RESET_EN_SW___M 0x00000080 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_PHASE_RESET_EN_SW___S 7 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_PHASE_RESET_DELAY_COUNT_SW___M 0x00000060 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_PHASE_RESET_DELAY_COUNT_SW___S 5 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_PSCBC_PWR_DWN_SW___M 0x00000010 +#define CC_WCSS_WLAN1_CFG_GDSCR__GDSC_PSCBC_PWR_DWN_SW___S 4 +#define CC_WCSS_WLAN1_CFG_GDSCR__UNCLAMP_IO_SOFTWARE_OVERRIDE___M 0x00000008 +#define CC_WCSS_WLAN1_CFG_GDSCR__UNCLAMP_IO_SOFTWARE_OVERRIDE___S 3 +#define CC_WCSS_WLAN1_CFG_GDSCR__SAVE_RESTORE_SOFTWARE_OVERRIDE___M 0x00000004 +#define CC_WCSS_WLAN1_CFG_GDSCR__SAVE_RESTORE_SOFTWARE_OVERRIDE___S 2 +#define CC_WCSS_WLAN1_CFG_GDSCR__CLAMP_IO_SOFTWARE_OVERRIDE___M 0x00000002 +#define CC_WCSS_WLAN1_CFG_GDSCR__CLAMP_IO_SOFTWARE_OVERRIDE___S 1 +#define CC_WCSS_WLAN1_CFG_GDSCR__DISABLE_CLK_SOFTWARE_OVERRIDE___M 0x00000001 +#define CC_WCSS_WLAN1_CFG_GDSCR__DISABLE_CLK_SOFTWARE_OVERRIDE___S 0 +#define CC_WCSS_WLAN1_CFG_GDSCR___M 0xFFFFFFFF +#define CC_WCSS_WLAN1_CFG_GDSCR___S 0 + +#define CC_WCSS_WLAN1_CFG2_GDSCR (0x00CB009C) +#define CC_WCSS_WLAN1_CFG2_GDSCR___RWC QCSR_REG_RW +#define CC_WCSS_WLAN1_CFG2_GDSCR___POR 0x0000022A +#define CC_WCSS_WLAN1_CFG2_GDSCR__GDSC_CLAMP_MEM_SW___POR 0x0 +#define CC_WCSS_WLAN1_CFG2_GDSCR__DLY_MEM_PWR_UP___POR 0x0 +#define CC_WCSS_WLAN1_CFG2_GDSCR__DLY_DEASSERT_CLAMP_MEM___POR 0x2 +#define CC_WCSS_WLAN1_CFG2_GDSCR__DLY_ASSERT_CLAMP_MEM___POR 0x2 +#define CC_WCSS_WLAN1_CFG2_GDSCR__MEM_PWR_DWN_TIMEOUT___POR 0xA +#define CC_WCSS_WLAN1_CFG2_GDSCR__GDSC_CLAMP_MEM_SW___M 0x00010000 +#define CC_WCSS_WLAN1_CFG2_GDSCR__GDSC_CLAMP_MEM_SW___S 16 +#define CC_WCSS_WLAN1_CFG2_GDSCR__DLY_MEM_PWR_UP___M 0x0000F000 +#define CC_WCSS_WLAN1_CFG2_GDSCR__DLY_MEM_PWR_UP___S 12 +#define CC_WCSS_WLAN1_CFG2_GDSCR__DLY_DEASSERT_CLAMP_MEM___M 0x00000F00 +#define CC_WCSS_WLAN1_CFG2_GDSCR__DLY_DEASSERT_CLAMP_MEM___S 8 +#define CC_WCSS_WLAN1_CFG2_GDSCR__DLY_ASSERT_CLAMP_MEM___M 0x000000F0 +#define CC_WCSS_WLAN1_CFG2_GDSCR__DLY_ASSERT_CLAMP_MEM___S 4 +#define CC_WCSS_WLAN1_CFG2_GDSCR__MEM_PWR_DWN_TIMEOUT___M 0x0000000F +#define CC_WCSS_WLAN1_CFG2_GDSCR__MEM_PWR_DWN_TIMEOUT___S 0 +#define CC_WCSS_WLAN1_CFG2_GDSCR___M 0x0001FFFF +#define CC_WCSS_WLAN1_CFG2_GDSCR___S 0 + +#define CC_WCSS_PHYA_NOC_CBCR (0x00CB00A0) +#define CC_WCSS_PHYA_NOC_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_PHYA_NOC_CBCR___POR 0x80000000 +#define CC_WCSS_PHYA_NOC_CBCR__CLK_OFF___POR 0x1 +#define CC_WCSS_PHYA_NOC_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_PHYA_NOC_CBCR__CLK_ENABLE___POR 0x0 +#define CC_WCSS_PHYA_NOC_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_PHYA_NOC_CBCR__CLK_OFF___S 31 +#define CC_WCSS_PHYA_NOC_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_PHYA_NOC_CBCR__CLK_ARES___S 2 +#define CC_WCSS_PHYA_NOC_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_PHYA_NOC_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_PHYA_NOC_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_PHYA_NOC_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_PHYA_NOC_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_PHYA_NOC_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_PHYA_NOC_CBCR___M 0x80000005 +#define CC_WCSS_PHYA_NOC_CBCR___S 0 + +#define CC_WCSS_PHYA_AHB_CBCR (0x00CB00A4) +#define CC_WCSS_PHYA_AHB_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_PHYA_AHB_CBCR___POR 0x80000000 +#define CC_WCSS_PHYA_AHB_CBCR__CLK_OFF___POR 0x1 +#define CC_WCSS_PHYA_AHB_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_PHYA_AHB_CBCR__CLK_ENABLE___POR 0x0 +#define CC_WCSS_PHYA_AHB_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_PHYA_AHB_CBCR__CLK_OFF___S 31 +#define CC_WCSS_PHYA_AHB_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_PHYA_AHB_CBCR__CLK_ARES___S 2 +#define CC_WCSS_PHYA_AHB_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_PHYA_AHB_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_PHYA_AHB_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_PHYA_AHB_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_PHYA_AHB_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_PHYA_AHB_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_PHYA_AHB_CBCR___M 0x80000005 +#define CC_WCSS_PHYA_AHB_CBCR___S 0 + +#define CC_WCSS_PHYA_DBG_ATB_CBCR (0x00CB00A8) +#define CC_WCSS_PHYA_DBG_ATB_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_PHYA_DBG_ATB_CBCR___POR 0x00000001 +#define CC_WCSS_PHYA_DBG_ATB_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_PHYA_DBG_ATB_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_PHYA_DBG_ATB_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_PHYA_DBG_ATB_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_PHYA_DBG_ATB_CBCR__CLK_OFF___S 31 +#define CC_WCSS_PHYA_DBG_ATB_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_PHYA_DBG_ATB_CBCR__CLK_ARES___S 2 +#define CC_WCSS_PHYA_DBG_ATB_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_PHYA_DBG_ATB_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_PHYA_DBG_ATB_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_PHYA_DBG_ATB_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_PHYA_DBG_ATB_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_PHYA_DBG_ATB_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_PHYA_DBG_ATB_CBCR___M 0x80000005 +#define CC_WCSS_PHYA_DBG_ATB_CBCR___S 0 + +#define CC_WCSS_PHYA_DBG_APB_CBCR (0x00CB00AC) +#define CC_WCSS_PHYA_DBG_APB_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_PHYA_DBG_APB_CBCR___POR 0x00000001 +#define CC_WCSS_PHYA_DBG_APB_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_PHYA_DBG_APB_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_PHYA_DBG_APB_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_PHYA_DBG_APB_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_PHYA_DBG_APB_CBCR__CLK_OFF___S 31 +#define CC_WCSS_PHYA_DBG_APB_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_PHYA_DBG_APB_CBCR__CLK_ARES___S 2 +#define CC_WCSS_PHYA_DBG_APB_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_PHYA_DBG_APB_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_PHYA_DBG_APB_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_PHYA_DBG_APB_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_PHYA_DBG_APB_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_PHYA_DBG_APB_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_PHYA_DBG_APB_CBCR___M 0x80000005 +#define CC_WCSS_PHYA_DBG_APB_CBCR___S 0 + +#define CC_WCSS_PHYA_DBG_DAPBUS_CBCR (0x00CB00B0) +#define CC_WCSS_PHYA_DBG_DAPBUS_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_PHYA_DBG_DAPBUS_CBCR___POR 0x00000001 +#define CC_WCSS_PHYA_DBG_DAPBUS_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_PHYA_DBG_DAPBUS_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_PHYA_DBG_DAPBUS_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_PHYA_DBG_DAPBUS_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_PHYA_DBG_DAPBUS_CBCR__CLK_OFF___S 31 +#define CC_WCSS_PHYA_DBG_DAPBUS_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_PHYA_DBG_DAPBUS_CBCR__CLK_ARES___S 2 +#define CC_WCSS_PHYA_DBG_DAPBUS_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_PHYA_DBG_DAPBUS_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_PHYA_DBG_DAPBUS_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_PHYA_DBG_DAPBUS_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_PHYA_DBG_DAPBUS_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_PHYA_DBG_DAPBUS_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_PHYA_DBG_DAPBUS_CBCR___M 0x80000005 +#define CC_WCSS_PHYA_DBG_DAPBUS_CBCR___S 0 + +#define CC_WCSS_PHYA_DBG_TS_CBCR (0x00CB00B4) +#define CC_WCSS_PHYA_DBG_TS_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_PHYA_DBG_TS_CBCR___POR 0x00000001 +#define CC_WCSS_PHYA_DBG_TS_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_PHYA_DBG_TS_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_PHYA_DBG_TS_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_PHYA_DBG_TS_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_PHYA_DBG_TS_CBCR__CLK_OFF___S 31 +#define CC_WCSS_PHYA_DBG_TS_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_PHYA_DBG_TS_CBCR__CLK_ARES___S 2 +#define CC_WCSS_PHYA_DBG_TS_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_PHYA_DBG_TS_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_PHYA_DBG_TS_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_PHYA_DBG_TS_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_PHYA_DBG_TS_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_PHYA_DBG_TS_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_PHYA_DBG_TS_CBCR___M 0x80000005 +#define CC_WCSS_PHYA_DBG_TS_CBCR___S 0 + +#define CC_WCSS_PHYA_ADC0_CBCR (0x00CB00B8) +#define CC_WCSS_PHYA_ADC0_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_PHYA_ADC0_CBCR___POR 0x80000000 +#define CC_WCSS_PHYA_ADC0_CBCR__CLK_OFF___POR 0x1 +#define CC_WCSS_PHYA_ADC0_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_PHYA_ADC0_CBCR__CLK_ENABLE___POR 0x0 +#define CC_WCSS_PHYA_ADC0_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_PHYA_ADC0_CBCR__CLK_OFF___S 31 +#define CC_WCSS_PHYA_ADC0_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_PHYA_ADC0_CBCR__CLK_ARES___S 2 +#define CC_WCSS_PHYA_ADC0_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_PHYA_ADC0_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_PHYA_ADC0_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_PHYA_ADC0_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_PHYA_ADC0_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_PHYA_ADC0_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_PHYA_ADC0_CBCR___M 0x80000005 +#define CC_WCSS_PHYA_ADC0_CBCR___S 0 + +#define CC_WCSS_PHYA_ADC1_CBCR (0x00CB00BC) +#define CC_WCSS_PHYA_ADC1_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_PHYA_ADC1_CBCR___POR 0x80000000 +#define CC_WCSS_PHYA_ADC1_CBCR__CLK_OFF___POR 0x1 +#define CC_WCSS_PHYA_ADC1_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_PHYA_ADC1_CBCR__CLK_ENABLE___POR 0x0 +#define CC_WCSS_PHYA_ADC1_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_PHYA_ADC1_CBCR__CLK_OFF___S 31 +#define CC_WCSS_PHYA_ADC1_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_PHYA_ADC1_CBCR__CLK_ARES___S 2 +#define CC_WCSS_PHYA_ADC1_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_PHYA_ADC1_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_PHYA_ADC1_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_PHYA_ADC1_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_PHYA_ADC1_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_PHYA_ADC1_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_PHYA_ADC1_CBCR___M 0x80000005 +#define CC_WCSS_PHYA_ADC1_CBCR___S 0 + +#define CC_WCSS_PHYA_480_CBCR (0x00CB00C0) +#define CC_WCSS_PHYA_480_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_PHYA_480_CBCR___POR 0x80000220 +#define CC_WCSS_PHYA_480_CBCR__CLK_OFF___POR 0x1 +#define CC_WCSS_PHYA_480_CBCR__FORCE_MEM_CORE_ON___POR 0x0 +#define CC_WCSS_PHYA_480_CBCR__FORCE_MEM_PERIPH_ON___POR 0x0 +#define CC_WCSS_PHYA_480_CBCR__FORCE_MEM_PERIPH_OFF___POR 0x0 +#define CC_WCSS_PHYA_480_CBCR__WAKEUP___POR 0x2 +#define CC_WCSS_PHYA_480_CBCR__SLEEP___POR 0x2 +#define CC_WCSS_PHYA_480_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_PHYA_480_CBCR__CLK_ENABLE___POR 0x0 +#define CC_WCSS_PHYA_480_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_PHYA_480_CBCR__CLK_OFF___S 31 +#define CC_WCSS_PHYA_480_CBCR__FORCE_MEM_CORE_ON___M 0x00004000 +#define CC_WCSS_PHYA_480_CBCR__FORCE_MEM_CORE_ON___S 14 +#define CC_WCSS_PHYA_480_CBCR__FORCE_MEM_CORE_ON__FORCE_DISABLE 0x0 +#define CC_WCSS_PHYA_480_CBCR__FORCE_MEM_CORE_ON__FORCE_ENABLE 0x1 +#define CC_WCSS_PHYA_480_CBCR__FORCE_MEM_PERIPH_ON___M 0x00002000 +#define CC_WCSS_PHYA_480_CBCR__FORCE_MEM_PERIPH_ON___S 13 +#define CC_WCSS_PHYA_480_CBCR__FORCE_MEM_PERIPH_ON__FORCE_DISABLE 0x0 +#define CC_WCSS_PHYA_480_CBCR__FORCE_MEM_PERIPH_ON__FORCE_ENABLE 0x1 +#define CC_WCSS_PHYA_480_CBCR__FORCE_MEM_PERIPH_OFF___M 0x00001000 +#define CC_WCSS_PHYA_480_CBCR__FORCE_MEM_PERIPH_OFF___S 12 +#define CC_WCSS_PHYA_480_CBCR__FORCE_MEM_PERIPH_OFF__FORCE_DISABLE 0x0 +#define CC_WCSS_PHYA_480_CBCR__FORCE_MEM_PERIPH_OFF__FORCE_ENABLE 0x1 +#define CC_WCSS_PHYA_480_CBCR__WAKEUP___M 0x00000F00 +#define CC_WCSS_PHYA_480_CBCR__WAKEUP___S 8 +#define CC_WCSS_PHYA_480_CBCR__WAKEUP__CLOCK0 0x0 +#define CC_WCSS_PHYA_480_CBCR__WAKEUP__CLOCK1 0x1 +#define CC_WCSS_PHYA_480_CBCR__WAKEUP__CLOCK2 0x2 +#define CC_WCSS_PHYA_480_CBCR__WAKEUP__CLOCK3 0x3 +#define CC_WCSS_PHYA_480_CBCR__WAKEUP__CLOCK4 0x4 +#define CC_WCSS_PHYA_480_CBCR__WAKEUP__CLOCK5 0x5 +#define CC_WCSS_PHYA_480_CBCR__WAKEUP__CLOCK6 0x6 +#define CC_WCSS_PHYA_480_CBCR__WAKEUP__CLOCK7 0x7 +#define CC_WCSS_PHYA_480_CBCR__WAKEUP__CLOCK8 0x8 +#define CC_WCSS_PHYA_480_CBCR__WAKEUP__CLOCK9 0x9 +#define CC_WCSS_PHYA_480_CBCR__WAKEUP__CLOCK10 0xA +#define CC_WCSS_PHYA_480_CBCR__WAKEUP__CLOCK11 0xB +#define CC_WCSS_PHYA_480_CBCR__WAKEUP__CLOCK12 0xC +#define CC_WCSS_PHYA_480_CBCR__WAKEUP__CLOCK13 0xD +#define CC_WCSS_PHYA_480_CBCR__WAKEUP__CLOCK14 0xE +#define CC_WCSS_PHYA_480_CBCR__WAKEUP__CLOCK15 0xF +#define CC_WCSS_PHYA_480_CBCR__SLEEP___M 0x000000F0 +#define CC_WCSS_PHYA_480_CBCR__SLEEP___S 4 +#define CC_WCSS_PHYA_480_CBCR__SLEEP__CLOCK0 0x0 +#define CC_WCSS_PHYA_480_CBCR__SLEEP__CLOCK1 0x1 +#define CC_WCSS_PHYA_480_CBCR__SLEEP__CLOCK2 0x2 +#define CC_WCSS_PHYA_480_CBCR__SLEEP__CLOCK3 0x3 +#define CC_WCSS_PHYA_480_CBCR__SLEEP__CLOCK4 0x4 +#define CC_WCSS_PHYA_480_CBCR__SLEEP__CLOCK5 0x5 +#define CC_WCSS_PHYA_480_CBCR__SLEEP__CLOCK6 0x6 +#define CC_WCSS_PHYA_480_CBCR__SLEEP__CLOCK7 0x7 +#define CC_WCSS_PHYA_480_CBCR__SLEEP__CLOCK8 0x8 +#define CC_WCSS_PHYA_480_CBCR__SLEEP__CLOCK9 0x9 +#define CC_WCSS_PHYA_480_CBCR__SLEEP__CLOCK10 0xA +#define CC_WCSS_PHYA_480_CBCR__SLEEP__CLOCK11 0xB +#define CC_WCSS_PHYA_480_CBCR__SLEEP__CLOCK12 0xC +#define CC_WCSS_PHYA_480_CBCR__SLEEP__CLOCK13 0xD +#define CC_WCSS_PHYA_480_CBCR__SLEEP__CLOCK14 0xE +#define CC_WCSS_PHYA_480_CBCR__SLEEP__CLOCK15 0xF +#define CC_WCSS_PHYA_480_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_PHYA_480_CBCR__CLK_ARES___S 2 +#define CC_WCSS_PHYA_480_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_PHYA_480_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_PHYA_480_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_PHYA_480_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_PHYA_480_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_PHYA_480_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_PHYA_480_CBCR___M 0x80007FF5 +#define CC_WCSS_PHYA_480_CBCR___S 0 + +#define CC_WCSS_PHYA_480_SREGR (0x00CB00C4) +#define CC_WCSS_PHYA_480_SREGR___RWC QCSR_REG_RW +#define CC_WCSS_PHYA_480_SREGR___POR 0x00000000 +#define CC_WCSS_PHYA_480_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___POR 0x00 +#define CC_WCSS_PHYA_480_SREGR__SREG_PSCBC_SPARE_CTRL_IN___POR 0x00 +#define CC_WCSS_PHYA_480_SREGR__RESERVE_BITS15_13___POR 0x0 +#define CC_WCSS_PHYA_480_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___POR 0x0 +#define CC_WCSS_PHYA_480_SREGR__SW_DIV_RATIO_SLP_STG_CLK___POR 0x0 +#define CC_WCSS_PHYA_480_SREGR__FORCE_CLK_ON___POR 0x0 +#define CC_WCSS_PHYA_480_SREGR__SW_RST_SEL_SLP_STG___POR 0x0 +#define CC_WCSS_PHYA_480_SREGR__SW_RST_SLP_STG___POR 0x0 +#define CC_WCSS_PHYA_480_SREGR__SW_CTRL_PWR_DOWN___POR 0x0 +#define CC_WCSS_PHYA_480_SREGR__SW_CLK_EN_SEL_SLP_STG___POR 0x0 +#define CC_WCSS_PHYA_480_SREGR__SW_CLK_EN_SLP_STG___POR 0x0 +#define CC_WCSS_PHYA_480_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___M 0xFF000000 +#define CC_WCSS_PHYA_480_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___S 24 +#define CC_WCSS_PHYA_480_SREGR__SREG_PSCBC_SPARE_CTRL_IN___M 0x00FF0000 +#define CC_WCSS_PHYA_480_SREGR__SREG_PSCBC_SPARE_CTRL_IN___S 16 +#define CC_WCSS_PHYA_480_SREGR__RESERVE_BITS15_13___M 0x0000E000 +#define CC_WCSS_PHYA_480_SREGR__RESERVE_BITS15_13___S 13 +#define CC_WCSS_PHYA_480_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___M 0x00001000 +#define CC_WCSS_PHYA_480_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___S 12 +#define CC_WCSS_PHYA_480_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE__NO_RESET 0x0 +#define CC_WCSS_PHYA_480_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE__RESET 0x1 +#define CC_WCSS_PHYA_480_SREGR__SW_DIV_RATIO_SLP_STG_CLK___M 0x00000300 +#define CC_WCSS_PHYA_480_SREGR__SW_DIV_RATIO_SLP_STG_CLK___S 8 +#define CC_WCSS_PHYA_480_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_1 0x0 +#define CC_WCSS_PHYA_480_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_2 0x1 +#define CC_WCSS_PHYA_480_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_4 0x2 +#define CC_WCSS_PHYA_480_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_8 0x3 +#define CC_WCSS_PHYA_480_SREGR__FORCE_CLK_ON___M 0x00000040 +#define CC_WCSS_PHYA_480_SREGR__FORCE_CLK_ON___S 6 +#define CC_WCSS_PHYA_480_SREGR__FORCE_CLK_ON__NO_FORCE 0x0 +#define CC_WCSS_PHYA_480_SREGR__FORCE_CLK_ON__FORCE_ENABLE 0x1 +#define CC_WCSS_PHYA_480_SREGR__SW_RST_SEL_SLP_STG___M 0x00000020 +#define CC_WCSS_PHYA_480_SREGR__SW_RST_SEL_SLP_STG___S 5 +#define CC_WCSS_PHYA_480_SREGR__SW_RST_SEL_SLP_STG__SELECT_THE_HARDWARE_ARES 0x0 +#define CC_WCSS_PHYA_480_SREGR__SW_RST_SEL_SLP_STG__SELECT_THE_SW_RST_SLP_STG_BIT 0x1 +#define CC_WCSS_PHYA_480_SREGR__SW_RST_SLP_STG___M 0x00000010 +#define CC_WCSS_PHYA_480_SREGR__SW_RST_SLP_STG___S 4 +#define CC_WCSS_PHYA_480_SREGR__SW_RST_SLP_STG__DE_ASSERTION_OF_THE_RESET 0x0 +#define CC_WCSS_PHYA_480_SREGR__SW_RST_SLP_STG__ASSERTION_OF_THE_RESET 0x1 +#define CC_WCSS_PHYA_480_SREGR__SW_CTRL_PWR_DOWN___M 0x00000008 +#define CC_WCSS_PHYA_480_SREGR__SW_CTRL_PWR_DOWN___S 3 +#define CC_WCSS_PHYA_480_SREGR__SW_CTRL_PWR_DOWN__NO_SW_CTRL 0x0 +#define CC_WCSS_PHYA_480_SREGR__SW_CTRL_PWR_DOWN__SW_CTRL 0x1 +#define CC_WCSS_PHYA_480_SREGR__SW_CLK_EN_SEL_SLP_STG___M 0x00000004 +#define CC_WCSS_PHYA_480_SREGR__SW_CLK_EN_SEL_SLP_STG___S 2 +#define CC_WCSS_PHYA_480_SREGR__SW_CLK_EN_SEL_SLP_STG__SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM 0x0 +#define CC_WCSS_PHYA_480_SREGR__SW_CLK_EN_SEL_SLP_STG__SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT 0x1 +#define CC_WCSS_PHYA_480_SREGR__SW_CLK_EN_SLP_STG___M 0x00000002 +#define CC_WCSS_PHYA_480_SREGR__SW_CLK_EN_SLP_STG___S 1 +#define CC_WCSS_PHYA_480_SREGR__SW_CLK_EN_SLP_STG__SLP_STG_CLOCK_DISABLE 0x0 +#define CC_WCSS_PHYA_480_SREGR__SW_CLK_EN_SLP_STG__SLP_STG_CLOCK_ENABLE 0x1 +#define CC_WCSS_PHYA_480_SREGR___M 0xFFFFF37E +#define CC_WCSS_PHYA_480_SREGR___S 1 + +#define CC_WCSS_PHYA_320_CMD_RCGR (0x00CB00C8) +#define CC_WCSS_PHYA_320_CMD_RCGR___RWC QCSR_REG_RW +#define CC_WCSS_PHYA_320_CMD_RCGR___POR 0x80000000 +#define CC_WCSS_PHYA_320_CMD_RCGR__ROOT_OFF___POR 0x1 +#define CC_WCSS_PHYA_320_CMD_RCGR__DIRTY_CFG_RCGR___POR 0x0 +#define CC_WCSS_PHYA_320_CMD_RCGR__ROOT_EN___POR 0x0 +#define CC_WCSS_PHYA_320_CMD_RCGR__UPDATE___POR 0x0 +#define CC_WCSS_PHYA_320_CMD_RCGR__ROOT_OFF___M 0x80000000 +#define CC_WCSS_PHYA_320_CMD_RCGR__ROOT_OFF___S 31 +#define CC_WCSS_PHYA_320_CMD_RCGR__DIRTY_CFG_RCGR___M 0x00000010 +#define CC_WCSS_PHYA_320_CMD_RCGR__DIRTY_CFG_RCGR___S 4 +#define CC_WCSS_PHYA_320_CMD_RCGR__ROOT_EN___M 0x00000002 +#define CC_WCSS_PHYA_320_CMD_RCGR__ROOT_EN___S 1 +#define CC_WCSS_PHYA_320_CMD_RCGR__ROOT_EN__DISABLE 0x0 +#define CC_WCSS_PHYA_320_CMD_RCGR__ROOT_EN__ENABLE 0x1 +#define CC_WCSS_PHYA_320_CMD_RCGR__UPDATE___M 0x00000001 +#define CC_WCSS_PHYA_320_CMD_RCGR__UPDATE___S 0 +#define CC_WCSS_PHYA_320_CMD_RCGR__UPDATE__DISABLE 0x0 +#define CC_WCSS_PHYA_320_CMD_RCGR__UPDATE__ENABLE 0x1 +#define CC_WCSS_PHYA_320_CMD_RCGR___M 0x80000013 +#define CC_WCSS_PHYA_320_CMD_RCGR___S 0 + +#define CC_WCSS_PHYA_320_CFG_RCGR (0x00CB00CC) +#define CC_WCSS_PHYA_320_CFG_RCGR___RWC QCSR_REG_RW +#define CC_WCSS_PHYA_320_CFG_RCGR___POR 0x00100000 +#define CC_WCSS_PHYA_320_CFG_RCGR__HW_CLK_CONTROL___POR 0x1 +#define CC_WCSS_PHYA_320_CFG_RCGR__RCGLITE_DISABLE___POR 0x0 +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_SEL___POR 0x0 +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV___POR 0x00 +#define CC_WCSS_PHYA_320_CFG_RCGR__HW_CLK_CONTROL___M 0x00100000 +#define CC_WCSS_PHYA_320_CFG_RCGR__HW_CLK_CONTROL___S 20 +#define CC_WCSS_PHYA_320_CFG_RCGR__HW_CLK_CONTROL__DISABLE 0x0 +#define CC_WCSS_PHYA_320_CFG_RCGR__HW_CLK_CONTROL__ENABLE 0x1 +#define CC_WCSS_PHYA_320_CFG_RCGR__RCGLITE_DISABLE___M 0x00010000 +#define CC_WCSS_PHYA_320_CFG_RCGR__RCGLITE_DISABLE___S 16 +#define CC_WCSS_PHYA_320_CFG_RCGR__RCGLITE_DISABLE__RCGLITE_ENABLED 0x0 +#define CC_WCSS_PHYA_320_CFG_RCGR__RCGLITE_DISABLE__RCGLITE_DISABLED 0x1 +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_SEL___M 0x00000700 +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_SEL___S 8 +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_SEL__SRC0 0x0 +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_SEL__SRC1 0x1 +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_SEL__SRC2 0x2 +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_SEL__SRC3 0x3 +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_SEL__SRC4 0x4 +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_SEL__SRC5 0x5 +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_SEL__SRC6 0x6 +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_SEL__SRC7 0x7 +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV___M 0x0000001F +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV___S 0 +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__BYPASS 0x00 +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV1 0x01 +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV1_5 0x02 +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV2 0x03 +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV2_5 0x04 +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV3 0x05 +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV3_5 0x06 +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV4 0x07 +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV4_5 0x08 +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV5 0x09 +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV5_5 0x0A +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV6 0x0B +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV6_5 0x0C +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV7 0x0D +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV7_5 0x0E +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV8 0x0F +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV8_5 0x10 +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV9 0x11 +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV9_5 0x12 +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV10 0x13 +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV10_5 0x14 +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV11 0x15 +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV11_5 0x16 +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV12 0x17 +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV12_5 0x18 +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV13 0x19 +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV13_5 0x1A +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV14 0x1B +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV14_5 0x1C +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV15 0x1D +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV15_5 0x1E +#define CC_WCSS_PHYA_320_CFG_RCGR__SRC_DIV__DIV16 0x1F +#define CC_WCSS_PHYA_320_CFG_RCGR___M 0x0011071F +#define CC_WCSS_PHYA_320_CFG_RCGR___S 0 + +#define CC_WCSS_PHYA_320_CBCR (0x00CB00E0) +#define CC_WCSS_PHYA_320_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_PHYA_320_CBCR___POR 0x80000220 +#define CC_WCSS_PHYA_320_CBCR__CLK_OFF___POR 0x1 +#define CC_WCSS_PHYA_320_CBCR__FORCE_MEM_CORE_ON___POR 0x0 +#define CC_WCSS_PHYA_320_CBCR__FORCE_MEM_PERIPH_ON___POR 0x0 +#define CC_WCSS_PHYA_320_CBCR__FORCE_MEM_PERIPH_OFF___POR 0x0 +#define CC_WCSS_PHYA_320_CBCR__WAKEUP___POR 0x2 +#define CC_WCSS_PHYA_320_CBCR__SLEEP___POR 0x2 +#define CC_WCSS_PHYA_320_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_PHYA_320_CBCR__CLK_ENABLE___POR 0x0 +#define CC_WCSS_PHYA_320_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_PHYA_320_CBCR__CLK_OFF___S 31 +#define CC_WCSS_PHYA_320_CBCR__FORCE_MEM_CORE_ON___M 0x00004000 +#define CC_WCSS_PHYA_320_CBCR__FORCE_MEM_CORE_ON___S 14 +#define CC_WCSS_PHYA_320_CBCR__FORCE_MEM_CORE_ON__FORCE_DISABLE 0x0 +#define CC_WCSS_PHYA_320_CBCR__FORCE_MEM_CORE_ON__FORCE_ENABLE 0x1 +#define CC_WCSS_PHYA_320_CBCR__FORCE_MEM_PERIPH_ON___M 0x00002000 +#define CC_WCSS_PHYA_320_CBCR__FORCE_MEM_PERIPH_ON___S 13 +#define CC_WCSS_PHYA_320_CBCR__FORCE_MEM_PERIPH_ON__FORCE_DISABLE 0x0 +#define CC_WCSS_PHYA_320_CBCR__FORCE_MEM_PERIPH_ON__FORCE_ENABLE 0x1 +#define CC_WCSS_PHYA_320_CBCR__FORCE_MEM_PERIPH_OFF___M 0x00001000 +#define CC_WCSS_PHYA_320_CBCR__FORCE_MEM_PERIPH_OFF___S 12 +#define CC_WCSS_PHYA_320_CBCR__FORCE_MEM_PERIPH_OFF__FORCE_DISABLE 0x0 +#define CC_WCSS_PHYA_320_CBCR__FORCE_MEM_PERIPH_OFF__FORCE_ENABLE 0x1 +#define CC_WCSS_PHYA_320_CBCR__WAKEUP___M 0x00000F00 +#define CC_WCSS_PHYA_320_CBCR__WAKEUP___S 8 +#define CC_WCSS_PHYA_320_CBCR__WAKEUP__CLOCK0 0x0 +#define CC_WCSS_PHYA_320_CBCR__WAKEUP__CLOCK1 0x1 +#define CC_WCSS_PHYA_320_CBCR__WAKEUP__CLOCK2 0x2 +#define CC_WCSS_PHYA_320_CBCR__WAKEUP__CLOCK3 0x3 +#define CC_WCSS_PHYA_320_CBCR__WAKEUP__CLOCK4 0x4 +#define CC_WCSS_PHYA_320_CBCR__WAKEUP__CLOCK5 0x5 +#define CC_WCSS_PHYA_320_CBCR__WAKEUP__CLOCK6 0x6 +#define CC_WCSS_PHYA_320_CBCR__WAKEUP__CLOCK7 0x7 +#define CC_WCSS_PHYA_320_CBCR__WAKEUP__CLOCK8 0x8 +#define CC_WCSS_PHYA_320_CBCR__WAKEUP__CLOCK9 0x9 +#define CC_WCSS_PHYA_320_CBCR__WAKEUP__CLOCK10 0xA +#define CC_WCSS_PHYA_320_CBCR__WAKEUP__CLOCK11 0xB +#define CC_WCSS_PHYA_320_CBCR__WAKEUP__CLOCK12 0xC +#define CC_WCSS_PHYA_320_CBCR__WAKEUP__CLOCK13 0xD +#define CC_WCSS_PHYA_320_CBCR__WAKEUP__CLOCK14 0xE +#define CC_WCSS_PHYA_320_CBCR__WAKEUP__CLOCK15 0xF +#define CC_WCSS_PHYA_320_CBCR__SLEEP___M 0x000000F0 +#define CC_WCSS_PHYA_320_CBCR__SLEEP___S 4 +#define CC_WCSS_PHYA_320_CBCR__SLEEP__CLOCK0 0x0 +#define CC_WCSS_PHYA_320_CBCR__SLEEP__CLOCK1 0x1 +#define CC_WCSS_PHYA_320_CBCR__SLEEP__CLOCK2 0x2 +#define CC_WCSS_PHYA_320_CBCR__SLEEP__CLOCK3 0x3 +#define CC_WCSS_PHYA_320_CBCR__SLEEP__CLOCK4 0x4 +#define CC_WCSS_PHYA_320_CBCR__SLEEP__CLOCK5 0x5 +#define CC_WCSS_PHYA_320_CBCR__SLEEP__CLOCK6 0x6 +#define CC_WCSS_PHYA_320_CBCR__SLEEP__CLOCK7 0x7 +#define CC_WCSS_PHYA_320_CBCR__SLEEP__CLOCK8 0x8 +#define CC_WCSS_PHYA_320_CBCR__SLEEP__CLOCK9 0x9 +#define CC_WCSS_PHYA_320_CBCR__SLEEP__CLOCK10 0xA +#define CC_WCSS_PHYA_320_CBCR__SLEEP__CLOCK11 0xB +#define CC_WCSS_PHYA_320_CBCR__SLEEP__CLOCK12 0xC +#define CC_WCSS_PHYA_320_CBCR__SLEEP__CLOCK13 0xD +#define CC_WCSS_PHYA_320_CBCR__SLEEP__CLOCK14 0xE +#define CC_WCSS_PHYA_320_CBCR__SLEEP__CLOCK15 0xF +#define CC_WCSS_PHYA_320_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_PHYA_320_CBCR__CLK_ARES___S 2 +#define CC_WCSS_PHYA_320_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_PHYA_320_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_PHYA_320_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_PHYA_320_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_PHYA_320_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_PHYA_320_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_PHYA_320_CBCR___M 0x80007FF5 +#define CC_WCSS_PHYA_320_CBCR___S 0 + +#define CC_WCSS_PHYA_320_SREGR (0x00CB00E4) +#define CC_WCSS_PHYA_320_SREGR___RWC QCSR_REG_RW +#define CC_WCSS_PHYA_320_SREGR___POR 0x00000000 +#define CC_WCSS_PHYA_320_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___POR 0x00 +#define CC_WCSS_PHYA_320_SREGR__SREG_PSCBC_SPARE_CTRL_IN___POR 0x00 +#define CC_WCSS_PHYA_320_SREGR__RESERVE_BITS15_13___POR 0x0 +#define CC_WCSS_PHYA_320_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___POR 0x0 +#define CC_WCSS_PHYA_320_SREGR__SW_DIV_RATIO_SLP_STG_CLK___POR 0x0 +#define CC_WCSS_PHYA_320_SREGR__FORCE_CLK_ON___POR 0x0 +#define CC_WCSS_PHYA_320_SREGR__SW_RST_SEL_SLP_STG___POR 0x0 +#define CC_WCSS_PHYA_320_SREGR__SW_RST_SLP_STG___POR 0x0 +#define CC_WCSS_PHYA_320_SREGR__SW_CTRL_PWR_DOWN___POR 0x0 +#define CC_WCSS_PHYA_320_SREGR__SW_CLK_EN_SEL_SLP_STG___POR 0x0 +#define CC_WCSS_PHYA_320_SREGR__SW_CLK_EN_SLP_STG___POR 0x0 +#define CC_WCSS_PHYA_320_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___M 0xFF000000 +#define CC_WCSS_PHYA_320_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___S 24 +#define CC_WCSS_PHYA_320_SREGR__SREG_PSCBC_SPARE_CTRL_IN___M 0x00FF0000 +#define CC_WCSS_PHYA_320_SREGR__SREG_PSCBC_SPARE_CTRL_IN___S 16 +#define CC_WCSS_PHYA_320_SREGR__RESERVE_BITS15_13___M 0x0000E000 +#define CC_WCSS_PHYA_320_SREGR__RESERVE_BITS15_13___S 13 +#define CC_WCSS_PHYA_320_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___M 0x00001000 +#define CC_WCSS_PHYA_320_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___S 12 +#define CC_WCSS_PHYA_320_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE__NO_RESET 0x0 +#define CC_WCSS_PHYA_320_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE__RESET 0x1 +#define CC_WCSS_PHYA_320_SREGR__SW_DIV_RATIO_SLP_STG_CLK___M 0x00000300 +#define CC_WCSS_PHYA_320_SREGR__SW_DIV_RATIO_SLP_STG_CLK___S 8 +#define CC_WCSS_PHYA_320_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_1 0x0 +#define CC_WCSS_PHYA_320_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_2 0x1 +#define CC_WCSS_PHYA_320_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_4 0x2 +#define CC_WCSS_PHYA_320_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_8 0x3 +#define CC_WCSS_PHYA_320_SREGR__FORCE_CLK_ON___M 0x00000040 +#define CC_WCSS_PHYA_320_SREGR__FORCE_CLK_ON___S 6 +#define CC_WCSS_PHYA_320_SREGR__FORCE_CLK_ON__NO_FORCE 0x0 +#define CC_WCSS_PHYA_320_SREGR__FORCE_CLK_ON__FORCE_ENABLE 0x1 +#define CC_WCSS_PHYA_320_SREGR__SW_RST_SEL_SLP_STG___M 0x00000020 +#define CC_WCSS_PHYA_320_SREGR__SW_RST_SEL_SLP_STG___S 5 +#define CC_WCSS_PHYA_320_SREGR__SW_RST_SEL_SLP_STG__SELECT_THE_HARDWARE_ARES 0x0 +#define CC_WCSS_PHYA_320_SREGR__SW_RST_SEL_SLP_STG__SELECT_THE_SW_RST_SLP_STG_BIT 0x1 +#define CC_WCSS_PHYA_320_SREGR__SW_RST_SLP_STG___M 0x00000010 +#define CC_WCSS_PHYA_320_SREGR__SW_RST_SLP_STG___S 4 +#define CC_WCSS_PHYA_320_SREGR__SW_RST_SLP_STG__DE_ASSERTION_OF_THE_RESET 0x0 +#define CC_WCSS_PHYA_320_SREGR__SW_RST_SLP_STG__ASSERTION_OF_THE_RESET 0x1 +#define CC_WCSS_PHYA_320_SREGR__SW_CTRL_PWR_DOWN___M 0x00000008 +#define CC_WCSS_PHYA_320_SREGR__SW_CTRL_PWR_DOWN___S 3 +#define CC_WCSS_PHYA_320_SREGR__SW_CTRL_PWR_DOWN__NO_SW_CTRL 0x0 +#define CC_WCSS_PHYA_320_SREGR__SW_CTRL_PWR_DOWN__SW_CTRL 0x1 +#define CC_WCSS_PHYA_320_SREGR__SW_CLK_EN_SEL_SLP_STG___M 0x00000004 +#define CC_WCSS_PHYA_320_SREGR__SW_CLK_EN_SEL_SLP_STG___S 2 +#define CC_WCSS_PHYA_320_SREGR__SW_CLK_EN_SEL_SLP_STG__SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM 0x0 +#define CC_WCSS_PHYA_320_SREGR__SW_CLK_EN_SEL_SLP_STG__SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT 0x1 +#define CC_WCSS_PHYA_320_SREGR__SW_CLK_EN_SLP_STG___M 0x00000002 +#define CC_WCSS_PHYA_320_SREGR__SW_CLK_EN_SLP_STG___S 1 +#define CC_WCSS_PHYA_320_SREGR__SW_CLK_EN_SLP_STG__SLP_STG_CLOCK_DISABLE 0x0 +#define CC_WCSS_PHYA_320_SREGR__SW_CLK_EN_SLP_STG__SLP_STG_CLOCK_ENABLE 0x1 +#define CC_WCSS_PHYA_320_SREGR___M 0xFFFFF37E +#define CC_WCSS_PHYA_320_SREGR___S 1 + +#define CC_WCSS_PHYA_ROBE_CBCR (0x00CB00E8) +#define CC_WCSS_PHYA_ROBE_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_PHYA_ROBE_CBCR___POR 0x80000220 +#define CC_WCSS_PHYA_ROBE_CBCR__CLK_OFF___POR 0x1 +#define CC_WCSS_PHYA_ROBE_CBCR__FORCE_MEM_CORE_ON___POR 0x0 +#define CC_WCSS_PHYA_ROBE_CBCR__FORCE_MEM_PERIPH_ON___POR 0x0 +#define CC_WCSS_PHYA_ROBE_CBCR__FORCE_MEM_PERIPH_OFF___POR 0x0 +#define CC_WCSS_PHYA_ROBE_CBCR__WAKEUP___POR 0x2 +#define CC_WCSS_PHYA_ROBE_CBCR__SLEEP___POR 0x2 +#define CC_WCSS_PHYA_ROBE_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_PHYA_ROBE_CBCR__CLK_ENABLE___POR 0x0 +#define CC_WCSS_PHYA_ROBE_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_PHYA_ROBE_CBCR__CLK_OFF___S 31 +#define CC_WCSS_PHYA_ROBE_CBCR__FORCE_MEM_CORE_ON___M 0x00004000 +#define CC_WCSS_PHYA_ROBE_CBCR__FORCE_MEM_CORE_ON___S 14 +#define CC_WCSS_PHYA_ROBE_CBCR__FORCE_MEM_CORE_ON__FORCE_DISABLE 0x0 +#define CC_WCSS_PHYA_ROBE_CBCR__FORCE_MEM_CORE_ON__FORCE_ENABLE 0x1 +#define CC_WCSS_PHYA_ROBE_CBCR__FORCE_MEM_PERIPH_ON___M 0x00002000 +#define CC_WCSS_PHYA_ROBE_CBCR__FORCE_MEM_PERIPH_ON___S 13 +#define CC_WCSS_PHYA_ROBE_CBCR__FORCE_MEM_PERIPH_ON__FORCE_DISABLE 0x0 +#define CC_WCSS_PHYA_ROBE_CBCR__FORCE_MEM_PERIPH_ON__FORCE_ENABLE 0x1 +#define CC_WCSS_PHYA_ROBE_CBCR__FORCE_MEM_PERIPH_OFF___M 0x00001000 +#define CC_WCSS_PHYA_ROBE_CBCR__FORCE_MEM_PERIPH_OFF___S 12 +#define CC_WCSS_PHYA_ROBE_CBCR__FORCE_MEM_PERIPH_OFF__FORCE_DISABLE 0x0 +#define CC_WCSS_PHYA_ROBE_CBCR__FORCE_MEM_PERIPH_OFF__FORCE_ENABLE 0x1 +#define CC_WCSS_PHYA_ROBE_CBCR__WAKEUP___M 0x00000F00 +#define CC_WCSS_PHYA_ROBE_CBCR__WAKEUP___S 8 +#define CC_WCSS_PHYA_ROBE_CBCR__WAKEUP__CLOCK0 0x0 +#define CC_WCSS_PHYA_ROBE_CBCR__WAKEUP__CLOCK1 0x1 +#define CC_WCSS_PHYA_ROBE_CBCR__WAKEUP__CLOCK2 0x2 +#define CC_WCSS_PHYA_ROBE_CBCR__WAKEUP__CLOCK3 0x3 +#define CC_WCSS_PHYA_ROBE_CBCR__WAKEUP__CLOCK4 0x4 +#define CC_WCSS_PHYA_ROBE_CBCR__WAKEUP__CLOCK5 0x5 +#define CC_WCSS_PHYA_ROBE_CBCR__WAKEUP__CLOCK6 0x6 +#define CC_WCSS_PHYA_ROBE_CBCR__WAKEUP__CLOCK7 0x7 +#define CC_WCSS_PHYA_ROBE_CBCR__WAKEUP__CLOCK8 0x8 +#define CC_WCSS_PHYA_ROBE_CBCR__WAKEUP__CLOCK9 0x9 +#define CC_WCSS_PHYA_ROBE_CBCR__WAKEUP__CLOCK10 0xA +#define CC_WCSS_PHYA_ROBE_CBCR__WAKEUP__CLOCK11 0xB +#define CC_WCSS_PHYA_ROBE_CBCR__WAKEUP__CLOCK12 0xC +#define CC_WCSS_PHYA_ROBE_CBCR__WAKEUP__CLOCK13 0xD +#define CC_WCSS_PHYA_ROBE_CBCR__WAKEUP__CLOCK14 0xE +#define CC_WCSS_PHYA_ROBE_CBCR__WAKEUP__CLOCK15 0xF +#define CC_WCSS_PHYA_ROBE_CBCR__SLEEP___M 0x000000F0 +#define CC_WCSS_PHYA_ROBE_CBCR__SLEEP___S 4 +#define CC_WCSS_PHYA_ROBE_CBCR__SLEEP__CLOCK0 0x0 +#define CC_WCSS_PHYA_ROBE_CBCR__SLEEP__CLOCK1 0x1 +#define CC_WCSS_PHYA_ROBE_CBCR__SLEEP__CLOCK2 0x2 +#define CC_WCSS_PHYA_ROBE_CBCR__SLEEP__CLOCK3 0x3 +#define CC_WCSS_PHYA_ROBE_CBCR__SLEEP__CLOCK4 0x4 +#define CC_WCSS_PHYA_ROBE_CBCR__SLEEP__CLOCK5 0x5 +#define CC_WCSS_PHYA_ROBE_CBCR__SLEEP__CLOCK6 0x6 +#define CC_WCSS_PHYA_ROBE_CBCR__SLEEP__CLOCK7 0x7 +#define CC_WCSS_PHYA_ROBE_CBCR__SLEEP__CLOCK8 0x8 +#define CC_WCSS_PHYA_ROBE_CBCR__SLEEP__CLOCK9 0x9 +#define CC_WCSS_PHYA_ROBE_CBCR__SLEEP__CLOCK10 0xA +#define CC_WCSS_PHYA_ROBE_CBCR__SLEEP__CLOCK11 0xB +#define CC_WCSS_PHYA_ROBE_CBCR__SLEEP__CLOCK12 0xC +#define CC_WCSS_PHYA_ROBE_CBCR__SLEEP__CLOCK13 0xD +#define CC_WCSS_PHYA_ROBE_CBCR__SLEEP__CLOCK14 0xE +#define CC_WCSS_PHYA_ROBE_CBCR__SLEEP__CLOCK15 0xF +#define CC_WCSS_PHYA_ROBE_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_PHYA_ROBE_CBCR__CLK_ARES___S 2 +#define CC_WCSS_PHYA_ROBE_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_PHYA_ROBE_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_PHYA_ROBE_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_PHYA_ROBE_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_PHYA_ROBE_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_PHYA_ROBE_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_PHYA_ROBE_CBCR___M 0x80007FF5 +#define CC_WCSS_PHYA_ROBE_CBCR___S 0 + +#define CC_WCSS_PHYA_ROBE_SREGR (0x00CB00EC) +#define CC_WCSS_PHYA_ROBE_SREGR___RWC QCSR_REG_RW +#define CC_WCSS_PHYA_ROBE_SREGR___POR 0x00000000 +#define CC_WCSS_PHYA_ROBE_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___POR 0x00 +#define CC_WCSS_PHYA_ROBE_SREGR__SREG_PSCBC_SPARE_CTRL_IN___POR 0x00 +#define CC_WCSS_PHYA_ROBE_SREGR__RESERVE_BITS15_13___POR 0x0 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___POR 0x0 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_DIV_RATIO_SLP_STG_CLK___POR 0x0 +#define CC_WCSS_PHYA_ROBE_SREGR__FORCE_CLK_ON___POR 0x0 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_RST_SEL_SLP_STG___POR 0x0 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_RST_SLP_STG___POR 0x0 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_CTRL_PWR_DOWN___POR 0x0 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_CLK_EN_SEL_SLP_STG___POR 0x0 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_CLK_EN_SLP_STG___POR 0x0 +#define CC_WCSS_PHYA_ROBE_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___M 0xFF000000 +#define CC_WCSS_PHYA_ROBE_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___S 24 +#define CC_WCSS_PHYA_ROBE_SREGR__SREG_PSCBC_SPARE_CTRL_IN___M 0x00FF0000 +#define CC_WCSS_PHYA_ROBE_SREGR__SREG_PSCBC_SPARE_CTRL_IN___S 16 +#define CC_WCSS_PHYA_ROBE_SREGR__RESERVE_BITS15_13___M 0x0000E000 +#define CC_WCSS_PHYA_ROBE_SREGR__RESERVE_BITS15_13___S 13 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___M 0x00001000 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___S 12 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE__NO_RESET 0x0 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE__RESET 0x1 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_DIV_RATIO_SLP_STG_CLK___M 0x00000300 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_DIV_RATIO_SLP_STG_CLK___S 8 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_1 0x0 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_2 0x1 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_4 0x2 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_8 0x3 +#define CC_WCSS_PHYA_ROBE_SREGR__FORCE_CLK_ON___M 0x00000040 +#define CC_WCSS_PHYA_ROBE_SREGR__FORCE_CLK_ON___S 6 +#define CC_WCSS_PHYA_ROBE_SREGR__FORCE_CLK_ON__NO_FORCE 0x0 +#define CC_WCSS_PHYA_ROBE_SREGR__FORCE_CLK_ON__FORCE_ENABLE 0x1 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_RST_SEL_SLP_STG___M 0x00000020 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_RST_SEL_SLP_STG___S 5 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_RST_SEL_SLP_STG__SELECT_THE_HARDWARE_ARES 0x0 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_RST_SEL_SLP_STG__SELECT_THE_SW_RST_SLP_STG_BIT 0x1 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_RST_SLP_STG___M 0x00000010 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_RST_SLP_STG___S 4 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_RST_SLP_STG__DE_ASSERTION_OF_THE_RESET 0x0 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_RST_SLP_STG__ASSERTION_OF_THE_RESET 0x1 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_CTRL_PWR_DOWN___M 0x00000008 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_CTRL_PWR_DOWN___S 3 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_CTRL_PWR_DOWN__NO_SW_CTRL 0x0 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_CTRL_PWR_DOWN__SW_CTRL 0x1 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_CLK_EN_SEL_SLP_STG___M 0x00000004 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_CLK_EN_SEL_SLP_STG___S 2 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_CLK_EN_SEL_SLP_STG__SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM 0x0 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_CLK_EN_SEL_SLP_STG__SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT 0x1 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_CLK_EN_SLP_STG___M 0x00000002 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_CLK_EN_SLP_STG___S 1 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_CLK_EN_SLP_STG__SLP_STG_CLOCK_DISABLE 0x0 +#define CC_WCSS_PHYA_ROBE_SREGR__SW_CLK_EN_SLP_STG__SLP_STG_CLOCK_ENABLE 0x1 +#define CC_WCSS_PHYA_ROBE_SREGR___M 0xFFFFF37E +#define CC_WCSS_PHYA_ROBE_SREGR___S 1 + +#define CC_WCSS_MAC0_AHB_CBCR (0x00CB00F0) +#define CC_WCSS_MAC0_AHB_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_MAC0_AHB_CBCR___POR 0x80000000 +#define CC_WCSS_MAC0_AHB_CBCR__CLK_OFF___POR 0x1 +#define CC_WCSS_MAC0_AHB_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_MAC0_AHB_CBCR__CLK_ENABLE___POR 0x0 +#define CC_WCSS_MAC0_AHB_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_MAC0_AHB_CBCR__CLK_OFF___S 31 +#define CC_WCSS_MAC0_AHB_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_MAC0_AHB_CBCR__CLK_ARES___S 2 +#define CC_WCSS_MAC0_AHB_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_MAC0_AHB_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_MAC0_AHB_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_MAC0_AHB_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_MAC0_AHB_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_MAC0_AHB_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_MAC0_AHB_CBCR___M 0x80000005 +#define CC_WCSS_MAC0_AHB_CBCR___S 0 + +#define CC_WCSS_MAC0_MAC_CMD_RCGR (0x00CB00F4) +#define CC_WCSS_MAC0_MAC_CMD_RCGR___RWC QCSR_REG_RW +#define CC_WCSS_MAC0_MAC_CMD_RCGR___POR 0x00000000 +#define CC_WCSS_MAC0_MAC_CMD_RCGR__ROOT_OFF___POR 0x0 +#define CC_WCSS_MAC0_MAC_CMD_RCGR__DIRTY_CFG_RCGR___POR 0x0 +#define CC_WCSS_MAC0_MAC_CMD_RCGR__ROOT_EN___POR 0x0 +#define CC_WCSS_MAC0_MAC_CMD_RCGR__UPDATE___POR 0x0 +#define CC_WCSS_MAC0_MAC_CMD_RCGR__ROOT_OFF___M 0x80000000 +#define CC_WCSS_MAC0_MAC_CMD_RCGR__ROOT_OFF___S 31 +#define CC_WCSS_MAC0_MAC_CMD_RCGR__DIRTY_CFG_RCGR___M 0x00000010 +#define CC_WCSS_MAC0_MAC_CMD_RCGR__DIRTY_CFG_RCGR___S 4 +#define CC_WCSS_MAC0_MAC_CMD_RCGR__ROOT_EN___M 0x00000002 +#define CC_WCSS_MAC0_MAC_CMD_RCGR__ROOT_EN___S 1 +#define CC_WCSS_MAC0_MAC_CMD_RCGR__ROOT_EN__DISABLE 0x0 +#define CC_WCSS_MAC0_MAC_CMD_RCGR__ROOT_EN__ENABLE 0x1 +#define CC_WCSS_MAC0_MAC_CMD_RCGR__UPDATE___M 0x00000001 +#define CC_WCSS_MAC0_MAC_CMD_RCGR__UPDATE___S 0 +#define CC_WCSS_MAC0_MAC_CMD_RCGR__UPDATE__DISABLE 0x0 +#define CC_WCSS_MAC0_MAC_CMD_RCGR__UPDATE__ENABLE 0x1 +#define CC_WCSS_MAC0_MAC_CMD_RCGR___M 0x80000013 +#define CC_WCSS_MAC0_MAC_CMD_RCGR___S 0 + +#define CC_WCSS_MAC0_MAC_CFG_RCGR (0x00CB00F8) +#define CC_WCSS_MAC0_MAC_CFG_RCGR___RWC QCSR_REG_RW +#define CC_WCSS_MAC0_MAC_CFG_RCGR___POR 0x00100000 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__HW_CLK_CONTROL___POR 0x1 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__RCGLITE_DISABLE___POR 0x0 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_SEL___POR 0x0 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV___POR 0x00 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__HW_CLK_CONTROL___M 0x00100000 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__HW_CLK_CONTROL___S 20 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__HW_CLK_CONTROL__DISABLE 0x0 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__HW_CLK_CONTROL__ENABLE 0x1 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__RCGLITE_DISABLE___M 0x00010000 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__RCGLITE_DISABLE___S 16 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__RCGLITE_DISABLE__RCGLITE_ENABLED 0x0 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__RCGLITE_DISABLE__RCGLITE_DISABLED 0x1 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_SEL___M 0x00000700 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_SEL___S 8 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_SEL__SRC0 0x0 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_SEL__SRC1 0x1 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_SEL__SRC2 0x2 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_SEL__SRC3 0x3 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_SEL__SRC4 0x4 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_SEL__SRC5 0x5 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_SEL__SRC6 0x6 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_SEL__SRC7 0x7 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV___M 0x0000001F +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV___S 0 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__BYPASS 0x00 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV1 0x01 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV1_5 0x02 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV2 0x03 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV2_5 0x04 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV3 0x05 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV3_5 0x06 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV4 0x07 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV4_5 0x08 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV5 0x09 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV5_5 0x0A +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV6 0x0B +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV6_5 0x0C +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV7 0x0D +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV7_5 0x0E +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV8 0x0F +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV8_5 0x10 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV9 0x11 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV9_5 0x12 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV10 0x13 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV10_5 0x14 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV11 0x15 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV11_5 0x16 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV12 0x17 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV12_5 0x18 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV13 0x19 +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV13_5 0x1A +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV14 0x1B +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV14_5 0x1C +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV15 0x1D +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV15_5 0x1E +#define CC_WCSS_MAC0_MAC_CFG_RCGR__SRC_DIV__DIV16 0x1F +#define CC_WCSS_MAC0_MAC_CFG_RCGR___M 0x0011071F +#define CC_WCSS_MAC0_MAC_CFG_RCGR___S 0 + +#define CC_WCSS_MAC0_AFTERDIV_MAC_CDIVR (0x00CB010C) +#define CC_WCSS_MAC0_AFTERDIV_MAC_CDIVR___RWC QCSR_REG_RW +#define CC_WCSS_MAC0_AFTERDIV_MAC_CDIVR___POR 0x00000000 +#define CC_WCSS_MAC0_AFTERDIV_MAC_CDIVR__CLK_DIV___POR 0x0 +#define CC_WCSS_MAC0_AFTERDIV_MAC_CDIVR__CLK_DIV___M 0x0000000F +#define CC_WCSS_MAC0_AFTERDIV_MAC_CDIVR__CLK_DIV___S 0 +#define CC_WCSS_MAC0_AFTERDIV_MAC_CDIVR___M 0x0000000F +#define CC_WCSS_MAC0_AFTERDIV_MAC_CDIVR___S 0 + +#define CC_WCSS_MAC0_MAC_CBCR (0x00CB0110) +#define CC_WCSS_MAC0_MAC_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_MAC0_MAC_CBCR___POR 0x80000220 +#define CC_WCSS_MAC0_MAC_CBCR__CLK_OFF___POR 0x1 +#define CC_WCSS_MAC0_MAC_CBCR__FORCE_MEM_CORE_ON___POR 0x0 +#define CC_WCSS_MAC0_MAC_CBCR__FORCE_MEM_PERIPH_ON___POR 0x0 +#define CC_WCSS_MAC0_MAC_CBCR__FORCE_MEM_PERIPH_OFF___POR 0x0 +#define CC_WCSS_MAC0_MAC_CBCR__WAKEUP___POR 0x2 +#define CC_WCSS_MAC0_MAC_CBCR__SLEEP___POR 0x2 +#define CC_WCSS_MAC0_MAC_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_MAC0_MAC_CBCR__CLK_ENABLE___POR 0x0 +#define CC_WCSS_MAC0_MAC_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_MAC0_MAC_CBCR__CLK_OFF___S 31 +#define CC_WCSS_MAC0_MAC_CBCR__FORCE_MEM_CORE_ON___M 0x00004000 +#define CC_WCSS_MAC0_MAC_CBCR__FORCE_MEM_CORE_ON___S 14 +#define CC_WCSS_MAC0_MAC_CBCR__FORCE_MEM_CORE_ON__FORCE_DISABLE 0x0 +#define CC_WCSS_MAC0_MAC_CBCR__FORCE_MEM_CORE_ON__FORCE_ENABLE 0x1 +#define CC_WCSS_MAC0_MAC_CBCR__FORCE_MEM_PERIPH_ON___M 0x00002000 +#define CC_WCSS_MAC0_MAC_CBCR__FORCE_MEM_PERIPH_ON___S 13 +#define CC_WCSS_MAC0_MAC_CBCR__FORCE_MEM_PERIPH_ON__FORCE_DISABLE 0x0 +#define CC_WCSS_MAC0_MAC_CBCR__FORCE_MEM_PERIPH_ON__FORCE_ENABLE 0x1 +#define CC_WCSS_MAC0_MAC_CBCR__FORCE_MEM_PERIPH_OFF___M 0x00001000 +#define CC_WCSS_MAC0_MAC_CBCR__FORCE_MEM_PERIPH_OFF___S 12 +#define CC_WCSS_MAC0_MAC_CBCR__FORCE_MEM_PERIPH_OFF__FORCE_DISABLE 0x0 +#define CC_WCSS_MAC0_MAC_CBCR__FORCE_MEM_PERIPH_OFF__FORCE_ENABLE 0x1 +#define CC_WCSS_MAC0_MAC_CBCR__WAKEUP___M 0x00000F00 +#define CC_WCSS_MAC0_MAC_CBCR__WAKEUP___S 8 +#define CC_WCSS_MAC0_MAC_CBCR__WAKEUP__CLOCK0 0x0 +#define CC_WCSS_MAC0_MAC_CBCR__WAKEUP__CLOCK1 0x1 +#define CC_WCSS_MAC0_MAC_CBCR__WAKEUP__CLOCK2 0x2 +#define CC_WCSS_MAC0_MAC_CBCR__WAKEUP__CLOCK3 0x3 +#define CC_WCSS_MAC0_MAC_CBCR__WAKEUP__CLOCK4 0x4 +#define CC_WCSS_MAC0_MAC_CBCR__WAKEUP__CLOCK5 0x5 +#define CC_WCSS_MAC0_MAC_CBCR__WAKEUP__CLOCK6 0x6 +#define CC_WCSS_MAC0_MAC_CBCR__WAKEUP__CLOCK7 0x7 +#define CC_WCSS_MAC0_MAC_CBCR__WAKEUP__CLOCK8 0x8 +#define CC_WCSS_MAC0_MAC_CBCR__WAKEUP__CLOCK9 0x9 +#define CC_WCSS_MAC0_MAC_CBCR__WAKEUP__CLOCK10 0xA +#define CC_WCSS_MAC0_MAC_CBCR__WAKEUP__CLOCK11 0xB +#define CC_WCSS_MAC0_MAC_CBCR__WAKEUP__CLOCK12 0xC +#define CC_WCSS_MAC0_MAC_CBCR__WAKEUP__CLOCK13 0xD +#define CC_WCSS_MAC0_MAC_CBCR__WAKEUP__CLOCK14 0xE +#define CC_WCSS_MAC0_MAC_CBCR__WAKEUP__CLOCK15 0xF +#define CC_WCSS_MAC0_MAC_CBCR__SLEEP___M 0x000000F0 +#define CC_WCSS_MAC0_MAC_CBCR__SLEEP___S 4 +#define CC_WCSS_MAC0_MAC_CBCR__SLEEP__CLOCK0 0x0 +#define CC_WCSS_MAC0_MAC_CBCR__SLEEP__CLOCK1 0x1 +#define CC_WCSS_MAC0_MAC_CBCR__SLEEP__CLOCK2 0x2 +#define CC_WCSS_MAC0_MAC_CBCR__SLEEP__CLOCK3 0x3 +#define CC_WCSS_MAC0_MAC_CBCR__SLEEP__CLOCK4 0x4 +#define CC_WCSS_MAC0_MAC_CBCR__SLEEP__CLOCK5 0x5 +#define CC_WCSS_MAC0_MAC_CBCR__SLEEP__CLOCK6 0x6 +#define CC_WCSS_MAC0_MAC_CBCR__SLEEP__CLOCK7 0x7 +#define CC_WCSS_MAC0_MAC_CBCR__SLEEP__CLOCK8 0x8 +#define CC_WCSS_MAC0_MAC_CBCR__SLEEP__CLOCK9 0x9 +#define CC_WCSS_MAC0_MAC_CBCR__SLEEP__CLOCK10 0xA +#define CC_WCSS_MAC0_MAC_CBCR__SLEEP__CLOCK11 0xB +#define CC_WCSS_MAC0_MAC_CBCR__SLEEP__CLOCK12 0xC +#define CC_WCSS_MAC0_MAC_CBCR__SLEEP__CLOCK13 0xD +#define CC_WCSS_MAC0_MAC_CBCR__SLEEP__CLOCK14 0xE +#define CC_WCSS_MAC0_MAC_CBCR__SLEEP__CLOCK15 0xF +#define CC_WCSS_MAC0_MAC_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_MAC0_MAC_CBCR__CLK_ARES___S 2 +#define CC_WCSS_MAC0_MAC_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_MAC0_MAC_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_MAC0_MAC_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_MAC0_MAC_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_MAC0_MAC_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_MAC0_MAC_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_MAC0_MAC_CBCR___M 0x80007FF5 +#define CC_WCSS_MAC0_MAC_CBCR___S 0 + +#define CC_WCSS_MAC0_MAC_SREGR (0x00CB0114) +#define CC_WCSS_MAC0_MAC_SREGR___RWC QCSR_REG_RW +#define CC_WCSS_MAC0_MAC_SREGR___POR 0x00000000 +#define CC_WCSS_MAC0_MAC_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___POR 0x00 +#define CC_WCSS_MAC0_MAC_SREGR__SREG_PSCBC_SPARE_CTRL_IN___POR 0x00 +#define CC_WCSS_MAC0_MAC_SREGR__RESERVE_BITS15_13___POR 0x0 +#define CC_WCSS_MAC0_MAC_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___POR 0x0 +#define CC_WCSS_MAC0_MAC_SREGR__SW_DIV_RATIO_SLP_STG_CLK___POR 0x0 +#define CC_WCSS_MAC0_MAC_SREGR__FORCE_CLK_ON___POR 0x0 +#define CC_WCSS_MAC0_MAC_SREGR__SW_RST_SEL_SLP_STG___POR 0x0 +#define CC_WCSS_MAC0_MAC_SREGR__SW_RST_SLP_STG___POR 0x0 +#define CC_WCSS_MAC0_MAC_SREGR__SW_CTRL_PWR_DOWN___POR 0x0 +#define CC_WCSS_MAC0_MAC_SREGR__SW_CLK_EN_SEL_SLP_STG___POR 0x0 +#define CC_WCSS_MAC0_MAC_SREGR__SW_CLK_EN_SLP_STG___POR 0x0 +#define CC_WCSS_MAC0_MAC_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___M 0xFF000000 +#define CC_WCSS_MAC0_MAC_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___S 24 +#define CC_WCSS_MAC0_MAC_SREGR__SREG_PSCBC_SPARE_CTRL_IN___M 0x00FF0000 +#define CC_WCSS_MAC0_MAC_SREGR__SREG_PSCBC_SPARE_CTRL_IN___S 16 +#define CC_WCSS_MAC0_MAC_SREGR__RESERVE_BITS15_13___M 0x0000E000 +#define CC_WCSS_MAC0_MAC_SREGR__RESERVE_BITS15_13___S 13 +#define CC_WCSS_MAC0_MAC_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___M 0x00001000 +#define CC_WCSS_MAC0_MAC_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___S 12 +#define CC_WCSS_MAC0_MAC_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE__NO_RESET 0x0 +#define CC_WCSS_MAC0_MAC_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE__RESET 0x1 +#define CC_WCSS_MAC0_MAC_SREGR__SW_DIV_RATIO_SLP_STG_CLK___M 0x00000300 +#define CC_WCSS_MAC0_MAC_SREGR__SW_DIV_RATIO_SLP_STG_CLK___S 8 +#define CC_WCSS_MAC0_MAC_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_1 0x0 +#define CC_WCSS_MAC0_MAC_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_2 0x1 +#define CC_WCSS_MAC0_MAC_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_4 0x2 +#define CC_WCSS_MAC0_MAC_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_8 0x3 +#define CC_WCSS_MAC0_MAC_SREGR__FORCE_CLK_ON___M 0x00000040 +#define CC_WCSS_MAC0_MAC_SREGR__FORCE_CLK_ON___S 6 +#define CC_WCSS_MAC0_MAC_SREGR__FORCE_CLK_ON__NO_FORCE 0x0 +#define CC_WCSS_MAC0_MAC_SREGR__FORCE_CLK_ON__FORCE_ENABLE 0x1 +#define CC_WCSS_MAC0_MAC_SREGR__SW_RST_SEL_SLP_STG___M 0x00000020 +#define CC_WCSS_MAC0_MAC_SREGR__SW_RST_SEL_SLP_STG___S 5 +#define CC_WCSS_MAC0_MAC_SREGR__SW_RST_SEL_SLP_STG__SELECT_THE_HARDWARE_ARES 0x0 +#define CC_WCSS_MAC0_MAC_SREGR__SW_RST_SEL_SLP_STG__SELECT_THE_SW_RST_SLP_STG_BIT 0x1 +#define CC_WCSS_MAC0_MAC_SREGR__SW_RST_SLP_STG___M 0x00000010 +#define CC_WCSS_MAC0_MAC_SREGR__SW_RST_SLP_STG___S 4 +#define CC_WCSS_MAC0_MAC_SREGR__SW_RST_SLP_STG__DE_ASSERTION_OF_THE_RESET 0x0 +#define CC_WCSS_MAC0_MAC_SREGR__SW_RST_SLP_STG__ASSERTION_OF_THE_RESET 0x1 +#define CC_WCSS_MAC0_MAC_SREGR__SW_CTRL_PWR_DOWN___M 0x00000008 +#define CC_WCSS_MAC0_MAC_SREGR__SW_CTRL_PWR_DOWN___S 3 +#define CC_WCSS_MAC0_MAC_SREGR__SW_CTRL_PWR_DOWN__NO_SW_CTRL 0x0 +#define CC_WCSS_MAC0_MAC_SREGR__SW_CTRL_PWR_DOWN__SW_CTRL 0x1 +#define CC_WCSS_MAC0_MAC_SREGR__SW_CLK_EN_SEL_SLP_STG___M 0x00000004 +#define CC_WCSS_MAC0_MAC_SREGR__SW_CLK_EN_SEL_SLP_STG___S 2 +#define CC_WCSS_MAC0_MAC_SREGR__SW_CLK_EN_SEL_SLP_STG__SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM 0x0 +#define CC_WCSS_MAC0_MAC_SREGR__SW_CLK_EN_SEL_SLP_STG__SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT 0x1 +#define CC_WCSS_MAC0_MAC_SREGR__SW_CLK_EN_SLP_STG___M 0x00000002 +#define CC_WCSS_MAC0_MAC_SREGR__SW_CLK_EN_SLP_STG___S 1 +#define CC_WCSS_MAC0_MAC_SREGR__SW_CLK_EN_SLP_STG__SLP_STG_CLOCK_DISABLE 0x0 +#define CC_WCSS_MAC0_MAC_SREGR__SW_CLK_EN_SLP_STG__SLP_STG_CLOCK_ENABLE 0x1 +#define CC_WCSS_MAC0_MAC_SREGR___M 0xFFFFF37E +#define CC_WCSS_MAC0_MAC_SREGR___S 1 + +#define CC_WCSS_DBG_BCR (0x00CB0118) +#define CC_WCSS_DBG_BCR___RWC QCSR_REG_RW +#define CC_WCSS_DBG_BCR___POR 0x00000000 +#define CC_WCSS_DBG_BCR__BLK_ARES___POR 0x0 +#define CC_WCSS_DBG_BCR__BLK_ARES___M 0x00000001 +#define CC_WCSS_DBG_BCR__BLK_ARES___S 0 +#define CC_WCSS_DBG_BCR__BLK_ARES__DISABLE 0x0 +#define CC_WCSS_DBG_BCR__BLK_ARES__ENABLE 0x1 +#define CC_WCSS_DBG_BCR___M 0x00000001 +#define CC_WCSS_DBG_BCR___S 0 + +#define CC_WCSS_DBG_GDSCR (0x00CB011C) +#define CC_WCSS_DBG_GDSCR___RWC QCSR_REG_RW +#define CC_WCSS_DBG_GDSCR___POR 0xF822F000 +#define CC_WCSS_DBG_GDSCR__PWR_ON___POR 0x1 +#define CC_WCSS_DBG_GDSCR__GDSC_STATE___POR 0xF +#define CC_WCSS_DBG_GDSCR__EN_REST_WAIT___POR 0x2 +#define CC_WCSS_DBG_GDSCR__EN_FEW_WAIT___POR 0x2 +#define CC_WCSS_DBG_GDSCR__CLK_DIS_WAIT___POR 0xF +#define CC_WCSS_DBG_GDSCR__RETAIN_FF_ENABLE___POR 0x0 +#define CC_WCSS_DBG_GDSCR__RESTORE___POR 0x0 +#define CC_WCSS_DBG_GDSCR__SAVE___POR 0x0 +#define CC_WCSS_DBG_GDSCR__RETAIN___POR 0x0 +#define CC_WCSS_DBG_GDSCR__EN_REST___POR 0x0 +#define CC_WCSS_DBG_GDSCR__EN_FEW___POR 0x0 +#define CC_WCSS_DBG_GDSCR__CLAMP_IO___POR 0x0 +#define CC_WCSS_DBG_GDSCR__CLK_DISABLE___POR 0x0 +#define CC_WCSS_DBG_GDSCR__PD_ARES___POR 0x0 +#define CC_WCSS_DBG_GDSCR__SW_OVERRIDE___POR 0x0 +#define CC_WCSS_DBG_GDSCR__HW_CONTROL___POR 0x0 +#define CC_WCSS_DBG_GDSCR__SW_COLLAPSE___POR 0x0 +#define CC_WCSS_DBG_GDSCR__PWR_ON___M 0x80000000 +#define CC_WCSS_DBG_GDSCR__PWR_ON___S 31 +#define CC_WCSS_DBG_GDSCR__GDSC_STATE___M 0x78000000 +#define CC_WCSS_DBG_GDSCR__GDSC_STATE___S 27 +#define CC_WCSS_DBG_GDSCR__EN_REST_WAIT___M 0x00F00000 +#define CC_WCSS_DBG_GDSCR__EN_REST_WAIT___S 20 +#define CC_WCSS_DBG_GDSCR__EN_FEW_WAIT___M 0x000F0000 +#define CC_WCSS_DBG_GDSCR__EN_FEW_WAIT___S 16 +#define CC_WCSS_DBG_GDSCR__CLK_DIS_WAIT___M 0x0000F000 +#define CC_WCSS_DBG_GDSCR__CLK_DIS_WAIT___S 12 +#define CC_WCSS_DBG_GDSCR__RETAIN_FF_ENABLE___M 0x00000800 +#define CC_WCSS_DBG_GDSCR__RETAIN_FF_ENABLE___S 11 +#define CC_WCSS_DBG_GDSCR__RETAIN_FF_ENABLE__DISABLE 0x0 +#define CC_WCSS_DBG_GDSCR__RETAIN_FF_ENABLE__ENABLE 0x1 +#define CC_WCSS_DBG_GDSCR__RESTORE___M 0x00000400 +#define CC_WCSS_DBG_GDSCR__RESTORE___S 10 +#define CC_WCSS_DBG_GDSCR__RESTORE__DISABLE 0x0 +#define CC_WCSS_DBG_GDSCR__RESTORE__ENABLE 0x1 +#define CC_WCSS_DBG_GDSCR__SAVE___M 0x00000200 +#define CC_WCSS_DBG_GDSCR__SAVE___S 9 +#define CC_WCSS_DBG_GDSCR__SAVE__DISABLE 0x0 +#define CC_WCSS_DBG_GDSCR__SAVE__ENABLE 0x1 +#define CC_WCSS_DBG_GDSCR__RETAIN___M 0x00000100 +#define CC_WCSS_DBG_GDSCR__RETAIN___S 8 +#define CC_WCSS_DBG_GDSCR__RETAIN__DISABLE 0x0 +#define CC_WCSS_DBG_GDSCR__RETAIN__ENABLE 0x1 +#define CC_WCSS_DBG_GDSCR__EN_REST___M 0x00000080 +#define CC_WCSS_DBG_GDSCR__EN_REST___S 7 +#define CC_WCSS_DBG_GDSCR__EN_REST__DISABLE 0x0 +#define CC_WCSS_DBG_GDSCR__EN_REST__ENABLE 0x1 +#define CC_WCSS_DBG_GDSCR__EN_FEW___M 0x00000040 +#define CC_WCSS_DBG_GDSCR__EN_FEW___S 6 +#define CC_WCSS_DBG_GDSCR__EN_FEW__DISABLE 0x0 +#define CC_WCSS_DBG_GDSCR__EN_FEW__ENABLE 0x1 +#define CC_WCSS_DBG_GDSCR__CLAMP_IO___M 0x00000020 +#define CC_WCSS_DBG_GDSCR__CLAMP_IO___S 5 +#define CC_WCSS_DBG_GDSCR__CLAMP_IO__DISABLE 0x0 +#define CC_WCSS_DBG_GDSCR__CLAMP_IO__ENABLE 0x1 +#define CC_WCSS_DBG_GDSCR__CLK_DISABLE___M 0x00000010 +#define CC_WCSS_DBG_GDSCR__CLK_DISABLE___S 4 +#define CC_WCSS_DBG_GDSCR__CLK_DISABLE__CLK_NOT_DISABLE 0x0 +#define CC_WCSS_DBG_GDSCR__CLK_DISABLE__CLK_DISABLE 0x1 +#define CC_WCSS_DBG_GDSCR__PD_ARES___M 0x00000008 +#define CC_WCSS_DBG_GDSCR__PD_ARES___S 3 +#define CC_WCSS_DBG_GDSCR__PD_ARES__NO_RESET 0x0 +#define CC_WCSS_DBG_GDSCR__PD_ARES__RESET 0x1 +#define CC_WCSS_DBG_GDSCR__SW_OVERRIDE___M 0x00000004 +#define CC_WCSS_DBG_GDSCR__SW_OVERRIDE___S 2 +#define CC_WCSS_DBG_GDSCR__SW_OVERRIDE__DISABLE 0x0 +#define CC_WCSS_DBG_GDSCR__SW_OVERRIDE__ENABLE 0x1 +#define CC_WCSS_DBG_GDSCR__HW_CONTROL___M 0x00000002 +#define CC_WCSS_DBG_GDSCR__HW_CONTROL___S 1 +#define CC_WCSS_DBG_GDSCR__HW_CONTROL__DISABLE 0x0 +#define CC_WCSS_DBG_GDSCR__HW_CONTROL__ENABLE 0x1 +#define CC_WCSS_DBG_GDSCR__SW_COLLAPSE___M 0x00000001 +#define CC_WCSS_DBG_GDSCR__SW_COLLAPSE___S 0 +#define CC_WCSS_DBG_GDSCR__SW_COLLAPSE__DISABLE 0x0 +#define CC_WCSS_DBG_GDSCR__SW_COLLAPSE__ENABLE 0x1 +#define CC_WCSS_DBG_GDSCR___M 0xF8FFFFFF +#define CC_WCSS_DBG_GDSCR___S 0 + +#define CC_WCSS_DBG_CFG_GDSCR (0x00CB0120) +#define CC_WCSS_DBG_CFG_GDSCR___RWC QCSR_REG_RW +#define CC_WCSS_DBG_CFG_GDSCR___POR 0x00070000 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_SPARE_CTRL_IN___POR 0x0 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_SPARE_CTRL_OUT___POR 0x0 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_PWR_DWN_START___POR 0x0 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_PWR_UP_START___POR 0x0 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_CFG_FSM_STATE_STATUS___POR 0x0 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_MEM_PWR_ACK_STATUS___POR 0x0 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_ENR_ACK_STATUS___POR 0x1 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_ENF_ACK_STATUS___POR 0x1 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_POWER_UP_COMPLETE___POR 0x1 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_POWER_DOWN_COMPLETE___POR 0x0 +#define CC_WCSS_DBG_CFG_GDSCR__SOFTWARE_CONTROL_OVERRIDE___POR 0x0 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_HANDSHAKE_DIS___POR 0x0 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_MEM_PERI_FORCE_IN_SW___POR 0x0 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_MEM_CORE_FORCE_IN_SW___POR 0x0 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_PHASE_RESET_EN_SW___POR 0x0 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_PHASE_RESET_DELAY_COUNT_SW___POR 0x0 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_PSCBC_PWR_DWN_SW___POR 0x0 +#define CC_WCSS_DBG_CFG_GDSCR__UNCLAMP_IO_SOFTWARE_OVERRIDE___POR 0x0 +#define CC_WCSS_DBG_CFG_GDSCR__SAVE_RESTORE_SOFTWARE_OVERRIDE___POR 0x0 +#define CC_WCSS_DBG_CFG_GDSCR__CLAMP_IO_SOFTWARE_OVERRIDE___POR 0x0 +#define CC_WCSS_DBG_CFG_GDSCR__DISABLE_CLK_SOFTWARE_OVERRIDE___POR 0x0 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_SPARE_CTRL_IN___M 0xF0000000 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_SPARE_CTRL_IN___S 28 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_SPARE_CTRL_OUT___M 0x0C000000 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_SPARE_CTRL_OUT___S 26 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_PWR_DWN_START___M 0x02000000 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_PWR_DWN_START___S 25 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_PWR_UP_START___M 0x01000000 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_PWR_UP_START___S 24 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_CFG_FSM_STATE_STATUS___M 0x00F00000 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_CFG_FSM_STATE_STATUS___S 20 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_MEM_PWR_ACK_STATUS___M 0x00080000 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_MEM_PWR_ACK_STATUS___S 19 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_ENR_ACK_STATUS___M 0x00040000 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_ENR_ACK_STATUS___S 18 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_ENF_ACK_STATUS___M 0x00020000 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_ENF_ACK_STATUS___S 17 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_POWER_UP_COMPLETE___M 0x00010000 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_POWER_UP_COMPLETE___S 16 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_POWER_DOWN_COMPLETE___M 0x00008000 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_POWER_DOWN_COMPLETE___S 15 +#define CC_WCSS_DBG_CFG_GDSCR__SOFTWARE_CONTROL_OVERRIDE___M 0x00007800 +#define CC_WCSS_DBG_CFG_GDSCR__SOFTWARE_CONTROL_OVERRIDE___S 11 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_HANDSHAKE_DIS___M 0x00000400 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_HANDSHAKE_DIS___S 10 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_MEM_PERI_FORCE_IN_SW___M 0x00000200 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_MEM_PERI_FORCE_IN_SW___S 9 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_MEM_CORE_FORCE_IN_SW___M 0x00000100 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_MEM_CORE_FORCE_IN_SW___S 8 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_PHASE_RESET_EN_SW___M 0x00000080 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_PHASE_RESET_EN_SW___S 7 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_PHASE_RESET_DELAY_COUNT_SW___M 0x00000060 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_PHASE_RESET_DELAY_COUNT_SW___S 5 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_PSCBC_PWR_DWN_SW___M 0x00000010 +#define CC_WCSS_DBG_CFG_GDSCR__GDSC_PSCBC_PWR_DWN_SW___S 4 +#define CC_WCSS_DBG_CFG_GDSCR__UNCLAMP_IO_SOFTWARE_OVERRIDE___M 0x00000008 +#define CC_WCSS_DBG_CFG_GDSCR__UNCLAMP_IO_SOFTWARE_OVERRIDE___S 3 +#define CC_WCSS_DBG_CFG_GDSCR__SAVE_RESTORE_SOFTWARE_OVERRIDE___M 0x00000004 +#define CC_WCSS_DBG_CFG_GDSCR__SAVE_RESTORE_SOFTWARE_OVERRIDE___S 2 +#define CC_WCSS_DBG_CFG_GDSCR__CLAMP_IO_SOFTWARE_OVERRIDE___M 0x00000002 +#define CC_WCSS_DBG_CFG_GDSCR__CLAMP_IO_SOFTWARE_OVERRIDE___S 1 +#define CC_WCSS_DBG_CFG_GDSCR__DISABLE_CLK_SOFTWARE_OVERRIDE___M 0x00000001 +#define CC_WCSS_DBG_CFG_GDSCR__DISABLE_CLK_SOFTWARE_OVERRIDE___S 0 +#define CC_WCSS_DBG_CFG_GDSCR___M 0xFFFFFFFF +#define CC_WCSS_DBG_CFG_GDSCR___S 0 + +#define CC_WCSS_DBG_CFG2_GDSCR (0x00CB0124) +#define CC_WCSS_DBG_CFG2_GDSCR___RWC QCSR_REG_RW +#define CC_WCSS_DBG_CFG2_GDSCR___POR 0x0000022A +#define CC_WCSS_DBG_CFG2_GDSCR__GDSC_CLAMP_MEM_SW___POR 0x0 +#define CC_WCSS_DBG_CFG2_GDSCR__DLY_MEM_PWR_UP___POR 0x0 +#define CC_WCSS_DBG_CFG2_GDSCR__DLY_DEASSERT_CLAMP_MEM___POR 0x2 +#define CC_WCSS_DBG_CFG2_GDSCR__DLY_ASSERT_CLAMP_MEM___POR 0x2 +#define CC_WCSS_DBG_CFG2_GDSCR__MEM_PWR_DWN_TIMEOUT___POR 0xA +#define CC_WCSS_DBG_CFG2_GDSCR__GDSC_CLAMP_MEM_SW___M 0x00010000 +#define CC_WCSS_DBG_CFG2_GDSCR__GDSC_CLAMP_MEM_SW___S 16 +#define CC_WCSS_DBG_CFG2_GDSCR__DLY_MEM_PWR_UP___M 0x0000F000 +#define CC_WCSS_DBG_CFG2_GDSCR__DLY_MEM_PWR_UP___S 12 +#define CC_WCSS_DBG_CFG2_GDSCR__DLY_DEASSERT_CLAMP_MEM___M 0x00000F00 +#define CC_WCSS_DBG_CFG2_GDSCR__DLY_DEASSERT_CLAMP_MEM___S 8 +#define CC_WCSS_DBG_CFG2_GDSCR__DLY_ASSERT_CLAMP_MEM___M 0x000000F0 +#define CC_WCSS_DBG_CFG2_GDSCR__DLY_ASSERT_CLAMP_MEM___S 4 +#define CC_WCSS_DBG_CFG2_GDSCR__MEM_PWR_DWN_TIMEOUT___M 0x0000000F +#define CC_WCSS_DBG_CFG2_GDSCR__MEM_PWR_DWN_TIMEOUT___S 0 +#define CC_WCSS_DBG_CFG2_GDSCR___M 0x0001FFFF +#define CC_WCSS_DBG_CFG2_GDSCR___S 0 + +#define CC_WCSS_DBG_AHB_CBCR (0x00CB0128) +#define CC_WCSS_DBG_AHB_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_DBG_AHB_CBCR___POR 0x00000001 +#define CC_WCSS_DBG_AHB_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_DBG_AHB_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_DBG_AHB_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_DBG_AHB_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_DBG_AHB_CBCR__CLK_OFF___S 31 +#define CC_WCSS_DBG_AHB_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_DBG_AHB_CBCR__CLK_ARES___S 2 +#define CC_WCSS_DBG_AHB_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_DBG_AHB_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_DBG_AHB_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_DBG_AHB_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_DBG_AHB_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_DBG_AHB_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_DBG_AHB_CBCR___M 0x80000005 +#define CC_WCSS_DBG_AHB_CBCR___S 0 + +#define CC_WCSS_DBG_NOC_CBCR (0x00CB012C) +#define CC_WCSS_DBG_NOC_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_DBG_NOC_CBCR___POR 0x00000001 +#define CC_WCSS_DBG_NOC_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_DBG_NOC_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_DBG_NOC_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_DBG_NOC_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_DBG_NOC_CBCR__CLK_OFF___S 31 +#define CC_WCSS_DBG_NOC_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_DBG_NOC_CBCR__CLK_ARES___S 2 +#define CC_WCSS_DBG_NOC_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_DBG_NOC_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_DBG_NOC_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_DBG_NOC_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_DBG_NOC_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_DBG_NOC_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_DBG_NOC_CBCR___M 0x80000005 +#define CC_WCSS_DBG_NOC_CBCR___S 0 + +#define CC_WCSS_DBG_ATB_CMD_RCGR (0x00CB0130) +#define CC_WCSS_DBG_ATB_CMD_RCGR___RWC QCSR_REG_RW +#define CC_WCSS_DBG_ATB_CMD_RCGR___POR 0x00000000 +#define CC_WCSS_DBG_ATB_CMD_RCGR__ROOT_OFF___POR 0x0 +#define CC_WCSS_DBG_ATB_CMD_RCGR__DIRTY_CFG_RCGR___POR 0x0 +#define CC_WCSS_DBG_ATB_CMD_RCGR__ROOT_EN___POR 0x0 +#define CC_WCSS_DBG_ATB_CMD_RCGR__UPDATE___POR 0x0 +#define CC_WCSS_DBG_ATB_CMD_RCGR__ROOT_OFF___M 0x80000000 +#define CC_WCSS_DBG_ATB_CMD_RCGR__ROOT_OFF___S 31 +#define CC_WCSS_DBG_ATB_CMD_RCGR__DIRTY_CFG_RCGR___M 0x00000010 +#define CC_WCSS_DBG_ATB_CMD_RCGR__DIRTY_CFG_RCGR___S 4 +#define CC_WCSS_DBG_ATB_CMD_RCGR__ROOT_EN___M 0x00000002 +#define CC_WCSS_DBG_ATB_CMD_RCGR__ROOT_EN___S 1 +#define CC_WCSS_DBG_ATB_CMD_RCGR__ROOT_EN__DISABLE 0x0 +#define CC_WCSS_DBG_ATB_CMD_RCGR__ROOT_EN__ENABLE 0x1 +#define CC_WCSS_DBG_ATB_CMD_RCGR__UPDATE___M 0x00000001 +#define CC_WCSS_DBG_ATB_CMD_RCGR__UPDATE___S 0 +#define CC_WCSS_DBG_ATB_CMD_RCGR__UPDATE__DISABLE 0x0 +#define CC_WCSS_DBG_ATB_CMD_RCGR__UPDATE__ENABLE 0x1 +#define CC_WCSS_DBG_ATB_CMD_RCGR___M 0x80000013 +#define CC_WCSS_DBG_ATB_CMD_RCGR___S 0 + +#define CC_WCSS_DBG_ATB_CFG_RCGR (0x00CB0134) +#define CC_WCSS_DBG_ATB_CFG_RCGR___RWC QCSR_REG_RW +#define CC_WCSS_DBG_ATB_CFG_RCGR___POR 0x00100000 +#define CC_WCSS_DBG_ATB_CFG_RCGR__HW_CLK_CONTROL___POR 0x1 +#define CC_WCSS_DBG_ATB_CFG_RCGR__RCGLITE_DISABLE___POR 0x0 +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_SEL___POR 0x0 +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV___POR 0x00 +#define CC_WCSS_DBG_ATB_CFG_RCGR__HW_CLK_CONTROL___M 0x00100000 +#define CC_WCSS_DBG_ATB_CFG_RCGR__HW_CLK_CONTROL___S 20 +#define CC_WCSS_DBG_ATB_CFG_RCGR__HW_CLK_CONTROL__DISABLE 0x0 +#define CC_WCSS_DBG_ATB_CFG_RCGR__HW_CLK_CONTROL__ENABLE 0x1 +#define CC_WCSS_DBG_ATB_CFG_RCGR__RCGLITE_DISABLE___M 0x00010000 +#define CC_WCSS_DBG_ATB_CFG_RCGR__RCGLITE_DISABLE___S 16 +#define CC_WCSS_DBG_ATB_CFG_RCGR__RCGLITE_DISABLE__RCGLITE_ENABLED 0x0 +#define CC_WCSS_DBG_ATB_CFG_RCGR__RCGLITE_DISABLE__RCGLITE_DISABLED 0x1 +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_SEL___M 0x00000700 +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_SEL___S 8 +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_SEL__SRC0 0x0 +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_SEL__SRC1 0x1 +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_SEL__SRC2 0x2 +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_SEL__SRC3 0x3 +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_SEL__SRC4 0x4 +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_SEL__SRC5 0x5 +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_SEL__SRC6 0x6 +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_SEL__SRC7 0x7 +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV___M 0x0000001F +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV___S 0 +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__BYPASS 0x00 +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV1 0x01 +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV1_5 0x02 +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV2 0x03 +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV2_5 0x04 +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV3 0x05 +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV3_5 0x06 +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV4 0x07 +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV4_5 0x08 +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV5 0x09 +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV5_5 0x0A +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV6 0x0B +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV6_5 0x0C +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV7 0x0D +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV7_5 0x0E +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV8 0x0F +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV8_5 0x10 +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV9 0x11 +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV9_5 0x12 +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV10 0x13 +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV10_5 0x14 +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV11 0x15 +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV11_5 0x16 +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV12 0x17 +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV12_5 0x18 +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV13 0x19 +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV13_5 0x1A +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV14 0x1B +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV14_5 0x1C +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV15 0x1D +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV15_5 0x1E +#define CC_WCSS_DBG_ATB_CFG_RCGR__SRC_DIV__DIV16 0x1F +#define CC_WCSS_DBG_ATB_CFG_RCGR___M 0x0011071F +#define CC_WCSS_DBG_ATB_CFG_RCGR___S 0 + +#define CC_WCSS_DBG_AFTERDIV_ATB_CDIVR (0x00CB0148) +#define CC_WCSS_DBG_AFTERDIV_ATB_CDIVR___RWC QCSR_REG_RW +#define CC_WCSS_DBG_AFTERDIV_ATB_CDIVR___POR 0x00000000 +#define CC_WCSS_DBG_AFTERDIV_ATB_CDIVR__CLK_DIV___POR 0x0 +#define CC_WCSS_DBG_AFTERDIV_ATB_CDIVR__CLK_DIV___M 0x0000000F +#define CC_WCSS_DBG_AFTERDIV_ATB_CDIVR__CLK_DIV___S 0 +#define CC_WCSS_DBG_AFTERDIV_ATB_CDIVR___M 0x0000000F +#define CC_WCSS_DBG_AFTERDIV_ATB_CDIVR___S 0 + +#define CC_WCSS_DBG_ATB_CBCR (0x00CB014C) +#define CC_WCSS_DBG_ATB_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_DBG_ATB_CBCR___POR 0x00000221 +#define CC_WCSS_DBG_ATB_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_DBG_ATB_CBCR__FORCE_MEM_CORE_ON___POR 0x0 +#define CC_WCSS_DBG_ATB_CBCR__FORCE_MEM_PERIPH_ON___POR 0x0 +#define CC_WCSS_DBG_ATB_CBCR__FORCE_MEM_PERIPH_OFF___POR 0x0 +#define CC_WCSS_DBG_ATB_CBCR__WAKEUP___POR 0x2 +#define CC_WCSS_DBG_ATB_CBCR__SLEEP___POR 0x2 +#define CC_WCSS_DBG_ATB_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_DBG_ATB_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_DBG_ATB_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_DBG_ATB_CBCR__CLK_OFF___S 31 +#define CC_WCSS_DBG_ATB_CBCR__FORCE_MEM_CORE_ON___M 0x00004000 +#define CC_WCSS_DBG_ATB_CBCR__FORCE_MEM_CORE_ON___S 14 +#define CC_WCSS_DBG_ATB_CBCR__FORCE_MEM_CORE_ON__FORCE_DISABLE 0x0 +#define CC_WCSS_DBG_ATB_CBCR__FORCE_MEM_CORE_ON__FORCE_ENABLE 0x1 +#define CC_WCSS_DBG_ATB_CBCR__FORCE_MEM_PERIPH_ON___M 0x00002000 +#define CC_WCSS_DBG_ATB_CBCR__FORCE_MEM_PERIPH_ON___S 13 +#define CC_WCSS_DBG_ATB_CBCR__FORCE_MEM_PERIPH_ON__FORCE_DISABLE 0x0 +#define CC_WCSS_DBG_ATB_CBCR__FORCE_MEM_PERIPH_ON__FORCE_ENABLE 0x1 +#define CC_WCSS_DBG_ATB_CBCR__FORCE_MEM_PERIPH_OFF___M 0x00001000 +#define CC_WCSS_DBG_ATB_CBCR__FORCE_MEM_PERIPH_OFF___S 12 +#define CC_WCSS_DBG_ATB_CBCR__FORCE_MEM_PERIPH_OFF__FORCE_DISABLE 0x0 +#define CC_WCSS_DBG_ATB_CBCR__FORCE_MEM_PERIPH_OFF__FORCE_ENABLE 0x1 +#define CC_WCSS_DBG_ATB_CBCR__WAKEUP___M 0x00000F00 +#define CC_WCSS_DBG_ATB_CBCR__WAKEUP___S 8 +#define CC_WCSS_DBG_ATB_CBCR__WAKEUP__CLOCK0 0x0 +#define CC_WCSS_DBG_ATB_CBCR__WAKEUP__CLOCK1 0x1 +#define CC_WCSS_DBG_ATB_CBCR__WAKEUP__CLOCK2 0x2 +#define CC_WCSS_DBG_ATB_CBCR__WAKEUP__CLOCK3 0x3 +#define CC_WCSS_DBG_ATB_CBCR__WAKEUP__CLOCK4 0x4 +#define CC_WCSS_DBG_ATB_CBCR__WAKEUP__CLOCK5 0x5 +#define CC_WCSS_DBG_ATB_CBCR__WAKEUP__CLOCK6 0x6 +#define CC_WCSS_DBG_ATB_CBCR__WAKEUP__CLOCK7 0x7 +#define CC_WCSS_DBG_ATB_CBCR__WAKEUP__CLOCK8 0x8 +#define CC_WCSS_DBG_ATB_CBCR__WAKEUP__CLOCK9 0x9 +#define CC_WCSS_DBG_ATB_CBCR__WAKEUP__CLOCK10 0xA +#define CC_WCSS_DBG_ATB_CBCR__WAKEUP__CLOCK11 0xB +#define CC_WCSS_DBG_ATB_CBCR__WAKEUP__CLOCK12 0xC +#define CC_WCSS_DBG_ATB_CBCR__WAKEUP__CLOCK13 0xD +#define CC_WCSS_DBG_ATB_CBCR__WAKEUP__CLOCK14 0xE +#define CC_WCSS_DBG_ATB_CBCR__WAKEUP__CLOCK15 0xF +#define CC_WCSS_DBG_ATB_CBCR__SLEEP___M 0x000000F0 +#define CC_WCSS_DBG_ATB_CBCR__SLEEP___S 4 +#define CC_WCSS_DBG_ATB_CBCR__SLEEP__CLOCK0 0x0 +#define CC_WCSS_DBG_ATB_CBCR__SLEEP__CLOCK1 0x1 +#define CC_WCSS_DBG_ATB_CBCR__SLEEP__CLOCK2 0x2 +#define CC_WCSS_DBG_ATB_CBCR__SLEEP__CLOCK3 0x3 +#define CC_WCSS_DBG_ATB_CBCR__SLEEP__CLOCK4 0x4 +#define CC_WCSS_DBG_ATB_CBCR__SLEEP__CLOCK5 0x5 +#define CC_WCSS_DBG_ATB_CBCR__SLEEP__CLOCK6 0x6 +#define CC_WCSS_DBG_ATB_CBCR__SLEEP__CLOCK7 0x7 +#define CC_WCSS_DBG_ATB_CBCR__SLEEP__CLOCK8 0x8 +#define CC_WCSS_DBG_ATB_CBCR__SLEEP__CLOCK9 0x9 +#define CC_WCSS_DBG_ATB_CBCR__SLEEP__CLOCK10 0xA +#define CC_WCSS_DBG_ATB_CBCR__SLEEP__CLOCK11 0xB +#define CC_WCSS_DBG_ATB_CBCR__SLEEP__CLOCK12 0xC +#define CC_WCSS_DBG_ATB_CBCR__SLEEP__CLOCK13 0xD +#define CC_WCSS_DBG_ATB_CBCR__SLEEP__CLOCK14 0xE +#define CC_WCSS_DBG_ATB_CBCR__SLEEP__CLOCK15 0xF +#define CC_WCSS_DBG_ATB_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_DBG_ATB_CBCR__CLK_ARES___S 2 +#define CC_WCSS_DBG_ATB_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_DBG_ATB_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_DBG_ATB_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_DBG_ATB_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_DBG_ATB_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_DBG_ATB_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_DBG_ATB_CBCR___M 0x80007FF5 +#define CC_WCSS_DBG_ATB_CBCR___S 0 + +#define CC_WCSS_DBG_ATB_SREGR (0x00CB0150) +#define CC_WCSS_DBG_ATB_SREGR___RWC QCSR_REG_RW +#define CC_WCSS_DBG_ATB_SREGR___POR 0x00000000 +#define CC_WCSS_DBG_ATB_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___POR 0x00 +#define CC_WCSS_DBG_ATB_SREGR__SREG_PSCBC_SPARE_CTRL_IN___POR 0x00 +#define CC_WCSS_DBG_ATB_SREGR__RESERVE_BITS15_13___POR 0x0 +#define CC_WCSS_DBG_ATB_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___POR 0x0 +#define CC_WCSS_DBG_ATB_SREGR__SW_DIV_RATIO_SLP_STG_CLK___POR 0x0 +#define CC_WCSS_DBG_ATB_SREGR__FORCE_CLK_ON___POR 0x0 +#define CC_WCSS_DBG_ATB_SREGR__SW_RST_SEL_SLP_STG___POR 0x0 +#define CC_WCSS_DBG_ATB_SREGR__SW_RST_SLP_STG___POR 0x0 +#define CC_WCSS_DBG_ATB_SREGR__SW_CTRL_PWR_DOWN___POR 0x0 +#define CC_WCSS_DBG_ATB_SREGR__SW_CLK_EN_SEL_SLP_STG___POR 0x0 +#define CC_WCSS_DBG_ATB_SREGR__SW_CLK_EN_SLP_STG___POR 0x0 +#define CC_WCSS_DBG_ATB_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___M 0xFF000000 +#define CC_WCSS_DBG_ATB_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___S 24 +#define CC_WCSS_DBG_ATB_SREGR__SREG_PSCBC_SPARE_CTRL_IN___M 0x00FF0000 +#define CC_WCSS_DBG_ATB_SREGR__SREG_PSCBC_SPARE_CTRL_IN___S 16 +#define CC_WCSS_DBG_ATB_SREGR__RESERVE_BITS15_13___M 0x0000E000 +#define CC_WCSS_DBG_ATB_SREGR__RESERVE_BITS15_13___S 13 +#define CC_WCSS_DBG_ATB_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___M 0x00001000 +#define CC_WCSS_DBG_ATB_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___S 12 +#define CC_WCSS_DBG_ATB_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE__NO_RESET 0x0 +#define CC_WCSS_DBG_ATB_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE__RESET 0x1 +#define CC_WCSS_DBG_ATB_SREGR__SW_DIV_RATIO_SLP_STG_CLK___M 0x00000300 +#define CC_WCSS_DBG_ATB_SREGR__SW_DIV_RATIO_SLP_STG_CLK___S 8 +#define CC_WCSS_DBG_ATB_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_1 0x0 +#define CC_WCSS_DBG_ATB_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_2 0x1 +#define CC_WCSS_DBG_ATB_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_4 0x2 +#define CC_WCSS_DBG_ATB_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_8 0x3 +#define CC_WCSS_DBG_ATB_SREGR__FORCE_CLK_ON___M 0x00000040 +#define CC_WCSS_DBG_ATB_SREGR__FORCE_CLK_ON___S 6 +#define CC_WCSS_DBG_ATB_SREGR__FORCE_CLK_ON__NO_FORCE 0x0 +#define CC_WCSS_DBG_ATB_SREGR__FORCE_CLK_ON__FORCE_ENABLE 0x1 +#define CC_WCSS_DBG_ATB_SREGR__SW_RST_SEL_SLP_STG___M 0x00000020 +#define CC_WCSS_DBG_ATB_SREGR__SW_RST_SEL_SLP_STG___S 5 +#define CC_WCSS_DBG_ATB_SREGR__SW_RST_SEL_SLP_STG__SELECT_THE_HARDWARE_ARES 0x0 +#define CC_WCSS_DBG_ATB_SREGR__SW_RST_SEL_SLP_STG__SELECT_THE_SW_RST_SLP_STG_BIT 0x1 +#define CC_WCSS_DBG_ATB_SREGR__SW_RST_SLP_STG___M 0x00000010 +#define CC_WCSS_DBG_ATB_SREGR__SW_RST_SLP_STG___S 4 +#define CC_WCSS_DBG_ATB_SREGR__SW_RST_SLP_STG__DE_ASSERTION_OF_THE_RESET 0x0 +#define CC_WCSS_DBG_ATB_SREGR__SW_RST_SLP_STG__ASSERTION_OF_THE_RESET 0x1 +#define CC_WCSS_DBG_ATB_SREGR__SW_CTRL_PWR_DOWN___M 0x00000008 +#define CC_WCSS_DBG_ATB_SREGR__SW_CTRL_PWR_DOWN___S 3 +#define CC_WCSS_DBG_ATB_SREGR__SW_CTRL_PWR_DOWN__NO_SW_CTRL 0x0 +#define CC_WCSS_DBG_ATB_SREGR__SW_CTRL_PWR_DOWN__SW_CTRL 0x1 +#define CC_WCSS_DBG_ATB_SREGR__SW_CLK_EN_SEL_SLP_STG___M 0x00000004 +#define CC_WCSS_DBG_ATB_SREGR__SW_CLK_EN_SEL_SLP_STG___S 2 +#define CC_WCSS_DBG_ATB_SREGR__SW_CLK_EN_SEL_SLP_STG__SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM 0x0 +#define CC_WCSS_DBG_ATB_SREGR__SW_CLK_EN_SEL_SLP_STG__SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT 0x1 +#define CC_WCSS_DBG_ATB_SREGR__SW_CLK_EN_SLP_STG___M 0x00000002 +#define CC_WCSS_DBG_ATB_SREGR__SW_CLK_EN_SLP_STG___S 1 +#define CC_WCSS_DBG_ATB_SREGR__SW_CLK_EN_SLP_STG__SLP_STG_CLOCK_DISABLE 0x0 +#define CC_WCSS_DBG_ATB_SREGR__SW_CLK_EN_SLP_STG__SLP_STG_CLOCK_ENABLE 0x1 +#define CC_WCSS_DBG_ATB_SREGR___M 0xFFFFF37E +#define CC_WCSS_DBG_ATB_SREGR___S 1 + +#define CC_WCSS_DBG_ATB_BDG_CBCR (0x00CB0154) +#define CC_WCSS_DBG_ATB_BDG_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_DBG_ATB_BDG_CBCR___POR 0x00000001 +#define CC_WCSS_DBG_ATB_BDG_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_DBG_ATB_BDG_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_DBG_ATB_BDG_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_DBG_ATB_BDG_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_DBG_ATB_BDG_CBCR__CLK_OFF___S 31 +#define CC_WCSS_DBG_ATB_BDG_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_DBG_ATB_BDG_CBCR__CLK_ARES___S 2 +#define CC_WCSS_DBG_ATB_BDG_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_DBG_ATB_BDG_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_DBG_ATB_BDG_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_DBG_ATB_BDG_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_DBG_ATB_BDG_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_DBG_ATB_BDG_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_DBG_ATB_BDG_CBCR___M 0x80000005 +#define CC_WCSS_DBG_ATB_BDG_CBCR___S 0 + +#define CC_WCSS_DBG_AFTERDIV_APB_CDIVR (0x00CB0158) +#define CC_WCSS_DBG_AFTERDIV_APB_CDIVR___RWC QCSR_REG_RW +#define CC_WCSS_DBG_AFTERDIV_APB_CDIVR___POR 0x00000003 +#define CC_WCSS_DBG_AFTERDIV_APB_CDIVR__CLK_DIV___POR 0x3 +#define CC_WCSS_DBG_AFTERDIV_APB_CDIVR__CLK_DIV___M 0x0000000F +#define CC_WCSS_DBG_AFTERDIV_APB_CDIVR__CLK_DIV___S 0 +#define CC_WCSS_DBG_AFTERDIV_APB_CDIVR___M 0x0000000F +#define CC_WCSS_DBG_AFTERDIV_APB_CDIVR___S 0 + +#define CC_WCSS_DBG_APB_CBCR (0x00CB015C) +#define CC_WCSS_DBG_APB_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_DBG_APB_CBCR___POR 0x00000001 +#define CC_WCSS_DBG_APB_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_DBG_APB_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_DBG_APB_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_DBG_APB_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_DBG_APB_CBCR__CLK_OFF___S 31 +#define CC_WCSS_DBG_APB_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_DBG_APB_CBCR__CLK_ARES___S 2 +#define CC_WCSS_DBG_APB_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_DBG_APB_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_DBG_APB_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_DBG_APB_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_DBG_APB_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_DBG_APB_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_DBG_APB_CBCR___M 0x80000005 +#define CC_WCSS_DBG_APB_CBCR___S 0 + +#define CC_WCSS_DBG_APB_BDG_CBCR (0x00CB0160) +#define CC_WCSS_DBG_APB_BDG_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_DBG_APB_BDG_CBCR___POR 0x00000001 +#define CC_WCSS_DBG_APB_BDG_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_DBG_APB_BDG_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_DBG_APB_BDG_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_DBG_APB_BDG_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_DBG_APB_BDG_CBCR__CLK_OFF___S 31 +#define CC_WCSS_DBG_APB_BDG_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_DBG_APB_BDG_CBCR__CLK_ARES___S 2 +#define CC_WCSS_DBG_APB_BDG_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_DBG_APB_BDG_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_DBG_APB_BDG_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_DBG_APB_BDG_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_DBG_APB_BDG_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_DBG_APB_BDG_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_DBG_APB_BDG_CBCR___M 0x80000005 +#define CC_WCSS_DBG_APB_BDG_CBCR___S 0 + +#define CC_WCSS_DBG_AFTERDIV_DAPBUS_CDIVR (0x00CB0164) +#define CC_WCSS_DBG_AFTERDIV_DAPBUS_CDIVR___RWC QCSR_REG_RW +#define CC_WCSS_DBG_AFTERDIV_DAPBUS_CDIVR___POR 0x00000003 +#define CC_WCSS_DBG_AFTERDIV_DAPBUS_CDIVR__CLK_DIV___POR 0x3 +#define CC_WCSS_DBG_AFTERDIV_DAPBUS_CDIVR__CLK_DIV___M 0x0000000F +#define CC_WCSS_DBG_AFTERDIV_DAPBUS_CDIVR__CLK_DIV___S 0 +#define CC_WCSS_DBG_AFTERDIV_DAPBUS_CDIVR___M 0x0000000F +#define CC_WCSS_DBG_AFTERDIV_DAPBUS_CDIVR___S 0 + +#define CC_WCSS_DBG_DAPBUS_CBCR (0x00CB0168) +#define CC_WCSS_DBG_DAPBUS_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_DBG_DAPBUS_CBCR___POR 0x00000001 +#define CC_WCSS_DBG_DAPBUS_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_DBG_DAPBUS_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_DBG_DAPBUS_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_DBG_DAPBUS_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_DBG_DAPBUS_CBCR__CLK_OFF___S 31 +#define CC_WCSS_DBG_DAPBUS_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_DBG_DAPBUS_CBCR__CLK_ARES___S 2 +#define CC_WCSS_DBG_DAPBUS_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_DBG_DAPBUS_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_DBG_DAPBUS_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_DBG_DAPBUS_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_DBG_DAPBUS_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_DBG_DAPBUS_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_DBG_DAPBUS_CBCR___M 0x80000005 +#define CC_WCSS_DBG_DAPBUS_CBCR___S 0 + +#define CC_WCSS_DBG_DAPBUS_BDG_CBCR (0x00CB016C) +#define CC_WCSS_DBG_DAPBUS_BDG_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_DBG_DAPBUS_BDG_CBCR___POR 0x00000001 +#define CC_WCSS_DBG_DAPBUS_BDG_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_DBG_DAPBUS_BDG_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_DBG_DAPBUS_BDG_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_DBG_DAPBUS_BDG_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_DBG_DAPBUS_BDG_CBCR__CLK_OFF___S 31 +#define CC_WCSS_DBG_DAPBUS_BDG_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_DBG_DAPBUS_BDG_CBCR__CLK_ARES___S 2 +#define CC_WCSS_DBG_DAPBUS_BDG_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_DBG_DAPBUS_BDG_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_DBG_DAPBUS_BDG_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_DBG_DAPBUS_BDG_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_DBG_DAPBUS_BDG_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_DBG_DAPBUS_BDG_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_DBG_DAPBUS_BDG_CBCR___M 0x80000005 +#define CC_WCSS_DBG_DAPBUS_BDG_CBCR___S 0 + +#define CC_WCSS_DBG_AFTER1STDIV_TS_CDIVR (0x00CB0170) +#define CC_WCSS_DBG_AFTER1STDIV_TS_CDIVR___RWC QCSR_REG_RW +#define CC_WCSS_DBG_AFTER1STDIV_TS_CDIVR___POR 0x00000001 +#define CC_WCSS_DBG_AFTER1STDIV_TS_CDIVR__CLK_DIV___POR 0x1 +#define CC_WCSS_DBG_AFTER1STDIV_TS_CDIVR__CLK_DIV___M 0x0000000F +#define CC_WCSS_DBG_AFTER1STDIV_TS_CDIVR__CLK_DIV___S 0 +#define CC_WCSS_DBG_AFTER1STDIV_TS_CDIVR___M 0x0000000F +#define CC_WCSS_DBG_AFTER1STDIV_TS_CDIVR___S 0 + +#define CC_WCSS_DBG_AFTERDIV_TS_CDIVR (0x00CB0174) +#define CC_WCSS_DBG_AFTERDIV_TS_CDIVR___RWC QCSR_REG_RW +#define CC_WCSS_DBG_AFTERDIV_TS_CDIVR___POR 0x00000000 +#define CC_WCSS_DBG_AFTERDIV_TS_CDIVR__CLK_DIV___POR 0x0 +#define CC_WCSS_DBG_AFTERDIV_TS_CDIVR__CLK_DIV___M 0x0000000F +#define CC_WCSS_DBG_AFTERDIV_TS_CDIVR__CLK_DIV___S 0 +#define CC_WCSS_DBG_AFTERDIV_TS_CDIVR___M 0x0000000F +#define CC_WCSS_DBG_AFTERDIV_TS_CDIVR___S 0 + +#define CC_WCSS_DBG_TS_CBCR (0x00CB0178) +#define CC_WCSS_DBG_TS_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_DBG_TS_CBCR___POR 0x00000001 +#define CC_WCSS_DBG_TS_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_DBG_TS_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_DBG_TS_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_DBG_TS_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_DBG_TS_CBCR__CLK_OFF___S 31 +#define CC_WCSS_DBG_TS_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_DBG_TS_CBCR__CLK_ARES___S 2 +#define CC_WCSS_DBG_TS_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_DBG_TS_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_DBG_TS_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_DBG_TS_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_DBG_TS_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_DBG_TS_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_DBG_TS_CBCR___M 0x80000005 +#define CC_WCSS_DBG_TS_CBCR___S 0 + +#define CC_WCSS_DBG_TS_BDG_CBCR (0x00CB017C) +#define CC_WCSS_DBG_TS_BDG_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_DBG_TS_BDG_CBCR___POR 0x00000001 +#define CC_WCSS_DBG_TS_BDG_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_DBG_TS_BDG_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_DBG_TS_BDG_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_DBG_TS_BDG_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_DBG_TS_BDG_CBCR__CLK_OFF___S 31 +#define CC_WCSS_DBG_TS_BDG_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_DBG_TS_BDG_CBCR__CLK_ARES___S 2 +#define CC_WCSS_DBG_TS_BDG_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_DBG_TS_BDG_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_DBG_TS_BDG_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_DBG_TS_BDG_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_DBG_TS_BDG_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_DBG_TS_BDG_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_DBG_TS_BDG_CBCR___M 0x80000005 +#define CC_WCSS_DBG_TS_BDG_CBCR___S 0 + +#define CC_WCSS_DBG_UMAC_NOC_ATB_SVS_CDIVR (0x00CB0180) +#define CC_WCSS_DBG_UMAC_NOC_ATB_SVS_CDIVR___RWC QCSR_REG_RW +#define CC_WCSS_DBG_UMAC_NOC_ATB_SVS_CDIVR___POR 0x00000001 +#define CC_WCSS_DBG_UMAC_NOC_ATB_SVS_CDIVR__CLK_DIV___POR 0x1 +#define CC_WCSS_DBG_UMAC_NOC_ATB_SVS_CDIVR__CLK_DIV___M 0x0000000F +#define CC_WCSS_DBG_UMAC_NOC_ATB_SVS_CDIVR__CLK_DIV___S 0 +#define CC_WCSS_DBG_UMAC_NOC_ATB_SVS_CDIVR___M 0x0000000F +#define CC_WCSS_DBG_UMAC_NOC_ATB_SVS_CDIVR___S 0 + +#define CC_WCSS_DBG_UMAC_NOC_ATB_CBCR (0x00CB0184) +#define CC_WCSS_DBG_UMAC_NOC_ATB_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_DBG_UMAC_NOC_ATB_CBCR___POR 0x00000001 +#define CC_WCSS_DBG_UMAC_NOC_ATB_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_DBG_UMAC_NOC_ATB_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_DBG_UMAC_NOC_ATB_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_DBG_UMAC_NOC_ATB_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_DBG_UMAC_NOC_ATB_CBCR__CLK_OFF___S 31 +#define CC_WCSS_DBG_UMAC_NOC_ATB_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_DBG_UMAC_NOC_ATB_CBCR__CLK_ARES___S 2 +#define CC_WCSS_DBG_UMAC_NOC_ATB_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_DBG_UMAC_NOC_ATB_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_DBG_UMAC_NOC_ATB_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_DBG_UMAC_NOC_ATB_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_DBG_UMAC_NOC_ATB_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_DBG_UMAC_NOC_ATB_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_DBG_UMAC_NOC_ATB_CBCR___M 0x80000005 +#define CC_WCSS_DBG_UMAC_NOC_ATB_CBCR___S 0 + +#define CC_WCSS_DBG_UMAC_NOC_APB_CBCR (0x00CB0188) +#define CC_WCSS_DBG_UMAC_NOC_APB_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_DBG_UMAC_NOC_APB_CBCR___POR 0x00000001 +#define CC_WCSS_DBG_UMAC_NOC_APB_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_DBG_UMAC_NOC_APB_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_DBG_UMAC_NOC_APB_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_DBG_UMAC_NOC_APB_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_DBG_UMAC_NOC_APB_CBCR__CLK_OFF___S 31 +#define CC_WCSS_DBG_UMAC_NOC_APB_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_DBG_UMAC_NOC_APB_CBCR__CLK_ARES___S 2 +#define CC_WCSS_DBG_UMAC_NOC_APB_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_DBG_UMAC_NOC_APB_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_DBG_UMAC_NOC_APB_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_DBG_UMAC_NOC_APB_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_DBG_UMAC_NOC_APB_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_DBG_UMAC_NOC_APB_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_DBG_UMAC_NOC_APB_CBCR___M 0x80000005 +#define CC_WCSS_DBG_UMAC_NOC_APB_CBCR___S 0 + +#define CC_WCSS_DBG_UMAC_NOC_TS_CBCR (0x00CB018C) +#define CC_WCSS_DBG_UMAC_NOC_TS_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_DBG_UMAC_NOC_TS_CBCR___POR 0x00000001 +#define CC_WCSS_DBG_UMAC_NOC_TS_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_DBG_UMAC_NOC_TS_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_DBG_UMAC_NOC_TS_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_DBG_UMAC_NOC_TS_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_DBG_UMAC_NOC_TS_CBCR__CLK_OFF___S 31 +#define CC_WCSS_DBG_UMAC_NOC_TS_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_DBG_UMAC_NOC_TS_CBCR__CLK_ARES___S 2 +#define CC_WCSS_DBG_UMAC_NOC_TS_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_DBG_UMAC_NOC_TS_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_DBG_UMAC_NOC_TS_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_DBG_UMAC_NOC_TS_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_DBG_UMAC_NOC_TS_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_DBG_UMAC_NOC_TS_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_DBG_UMAC_NOC_TS_CBCR___M 0x80000005 +#define CC_WCSS_DBG_UMAC_NOC_TS_CBCR___S 0 + +#define CC_WCSS_DBG_PHYA_ATB_CBCR (0x00CB0190) +#define CC_WCSS_DBG_PHYA_ATB_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_DBG_PHYA_ATB_CBCR___POR 0x00000001 +#define CC_WCSS_DBG_PHYA_ATB_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_DBG_PHYA_ATB_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_DBG_PHYA_ATB_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_DBG_PHYA_ATB_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_DBG_PHYA_ATB_CBCR__CLK_OFF___S 31 +#define CC_WCSS_DBG_PHYA_ATB_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_DBG_PHYA_ATB_CBCR__CLK_ARES___S 2 +#define CC_WCSS_DBG_PHYA_ATB_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_DBG_PHYA_ATB_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_DBG_PHYA_ATB_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_DBG_PHYA_ATB_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_DBG_PHYA_ATB_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_DBG_PHYA_ATB_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_DBG_PHYA_ATB_CBCR___M 0x80000005 +#define CC_WCSS_DBG_PHYA_ATB_CBCR___S 0 + +#define CC_WCSS_DBG_PHYA_APB_CBCR (0x00CB0194) +#define CC_WCSS_DBG_PHYA_APB_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_DBG_PHYA_APB_CBCR___POR 0x00000001 +#define CC_WCSS_DBG_PHYA_APB_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_DBG_PHYA_APB_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_DBG_PHYA_APB_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_DBG_PHYA_APB_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_DBG_PHYA_APB_CBCR__CLK_OFF___S 31 +#define CC_WCSS_DBG_PHYA_APB_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_DBG_PHYA_APB_CBCR__CLK_ARES___S 2 +#define CC_WCSS_DBG_PHYA_APB_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_DBG_PHYA_APB_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_DBG_PHYA_APB_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_DBG_PHYA_APB_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_DBG_PHYA_APB_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_DBG_PHYA_APB_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_DBG_PHYA_APB_CBCR___M 0x80000005 +#define CC_WCSS_DBG_PHYA_APB_CBCR___S 0 + +#define CC_WCSS_DBG_PHYA_DAPBUS_CBCR (0x00CB0198) +#define CC_WCSS_DBG_PHYA_DAPBUS_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_DBG_PHYA_DAPBUS_CBCR___POR 0x00000001 +#define CC_WCSS_DBG_PHYA_DAPBUS_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_DBG_PHYA_DAPBUS_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_DBG_PHYA_DAPBUS_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_DBG_PHYA_DAPBUS_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_DBG_PHYA_DAPBUS_CBCR__CLK_OFF___S 31 +#define CC_WCSS_DBG_PHYA_DAPBUS_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_DBG_PHYA_DAPBUS_CBCR__CLK_ARES___S 2 +#define CC_WCSS_DBG_PHYA_DAPBUS_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_DBG_PHYA_DAPBUS_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_DBG_PHYA_DAPBUS_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_DBG_PHYA_DAPBUS_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_DBG_PHYA_DAPBUS_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_DBG_PHYA_DAPBUS_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_DBG_PHYA_DAPBUS_CBCR___M 0x80000005 +#define CC_WCSS_DBG_PHYA_DAPBUS_CBCR___S 0 + +#define CC_WCSS_DBG_PHYA_TS_CBCR (0x00CB019C) +#define CC_WCSS_DBG_PHYA_TS_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_DBG_PHYA_TS_CBCR___POR 0x00000001 +#define CC_WCSS_DBG_PHYA_TS_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_DBG_PHYA_TS_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_DBG_PHYA_TS_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_DBG_PHYA_TS_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_DBG_PHYA_TS_CBCR__CLK_OFF___S 31 +#define CC_WCSS_DBG_PHYA_TS_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_DBG_PHYA_TS_CBCR__CLK_ARES___S 2 +#define CC_WCSS_DBG_PHYA_TS_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_DBG_PHYA_TS_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_DBG_PHYA_TS_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_DBG_PHYA_TS_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_DBG_PHYA_TS_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_DBG_PHYA_TS_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_DBG_PHYA_TS_CBCR___M 0x80000005 +#define CC_WCSS_DBG_PHYA_TS_CBCR___S 0 + +#define CC_WCSS_DBG_APB_TIME_CDIVR (0x00CB01A0) +#define CC_WCSS_DBG_APB_TIME_CDIVR___RWC QCSR_REG_RW +#define CC_WCSS_DBG_APB_TIME_CDIVR___POR 0x00000000 +#define CC_WCSS_DBG_APB_TIME_CDIVR__CLK_DIV___POR 0x0 +#define CC_WCSS_DBG_APB_TIME_CDIVR__CLK_DIV___M 0x0000000F +#define CC_WCSS_DBG_APB_TIME_CDIVR__CLK_DIV___S 0 +#define CC_WCSS_DBG_APB_TIME_CDIVR___M 0x0000000F +#define CC_WCSS_DBG_APB_TIME_CDIVR___S 0 + +#define CC_WCSS_DBG_MAC0_MAC_CBCR (0x00CB01A4) +#define CC_WCSS_DBG_MAC0_MAC_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_DBG_MAC0_MAC_CBCR___POR 0x00000001 +#define CC_WCSS_DBG_MAC0_MAC_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_DBG_MAC0_MAC_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_DBG_MAC0_MAC_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_DBG_MAC0_MAC_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_DBG_MAC0_MAC_CBCR__CLK_OFF___S 31 +#define CC_WCSS_DBG_MAC0_MAC_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_DBG_MAC0_MAC_CBCR__CLK_ARES___S 2 +#define CC_WCSS_DBG_MAC0_MAC_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_DBG_MAC0_MAC_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_DBG_MAC0_MAC_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_DBG_MAC0_MAC_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_DBG_MAC0_MAC_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_DBG_MAC0_MAC_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_DBG_MAC0_MAC_CBCR___M 0x80000005 +#define CC_WCSS_DBG_MAC0_MAC_CBCR___S 0 + +#define CC_WCSS_UMAC_BCR (0x00CB01A8) +#define CC_WCSS_UMAC_BCR___RWC QCSR_REG_RW +#define CC_WCSS_UMAC_BCR___POR 0x00000000 +#define CC_WCSS_UMAC_BCR__BLK_ARES___POR 0x0 +#define CC_WCSS_UMAC_BCR__BLK_ARES___M 0x00000001 +#define CC_WCSS_UMAC_BCR__BLK_ARES___S 0 +#define CC_WCSS_UMAC_BCR__BLK_ARES__DISABLE 0x0 +#define CC_WCSS_UMAC_BCR__BLK_ARES__ENABLE 0x1 +#define CC_WCSS_UMAC_BCR___M 0x00000001 +#define CC_WCSS_UMAC_BCR___S 0 + +#define CC_WCSS_UMAC_GDSCR (0x00CB01AC) +#define CC_WCSS_UMAC_GDSCR___RWC QCSR_REG_RW +#define CC_WCSS_UMAC_GDSCR___POR 0xF822F000 +#define CC_WCSS_UMAC_GDSCR__PWR_ON___POR 0x1 +#define CC_WCSS_UMAC_GDSCR__GDSC_STATE___POR 0xF +#define CC_WCSS_UMAC_GDSCR__EN_REST_WAIT___POR 0x2 +#define CC_WCSS_UMAC_GDSCR__EN_FEW_WAIT___POR 0x2 +#define CC_WCSS_UMAC_GDSCR__CLK_DIS_WAIT___POR 0xF +#define CC_WCSS_UMAC_GDSCR__RETAIN_FF_ENABLE___POR 0x0 +#define CC_WCSS_UMAC_GDSCR__RESTORE___POR 0x0 +#define CC_WCSS_UMAC_GDSCR__SAVE___POR 0x0 +#define CC_WCSS_UMAC_GDSCR__RETAIN___POR 0x0 +#define CC_WCSS_UMAC_GDSCR__EN_REST___POR 0x0 +#define CC_WCSS_UMAC_GDSCR__EN_FEW___POR 0x0 +#define CC_WCSS_UMAC_GDSCR__CLAMP_IO___POR 0x0 +#define CC_WCSS_UMAC_GDSCR__CLK_DISABLE___POR 0x0 +#define CC_WCSS_UMAC_GDSCR__PD_ARES___POR 0x0 +#define CC_WCSS_UMAC_GDSCR__SW_OVERRIDE___POR 0x0 +#define CC_WCSS_UMAC_GDSCR__HW_CONTROL___POR 0x0 +#define CC_WCSS_UMAC_GDSCR__SW_COLLAPSE___POR 0x0 +#define CC_WCSS_UMAC_GDSCR__PWR_ON___M 0x80000000 +#define CC_WCSS_UMAC_GDSCR__PWR_ON___S 31 +#define CC_WCSS_UMAC_GDSCR__GDSC_STATE___M 0x78000000 +#define CC_WCSS_UMAC_GDSCR__GDSC_STATE___S 27 +#define CC_WCSS_UMAC_GDSCR__EN_REST_WAIT___M 0x00F00000 +#define CC_WCSS_UMAC_GDSCR__EN_REST_WAIT___S 20 +#define CC_WCSS_UMAC_GDSCR__EN_FEW_WAIT___M 0x000F0000 +#define CC_WCSS_UMAC_GDSCR__EN_FEW_WAIT___S 16 +#define CC_WCSS_UMAC_GDSCR__CLK_DIS_WAIT___M 0x0000F000 +#define CC_WCSS_UMAC_GDSCR__CLK_DIS_WAIT___S 12 +#define CC_WCSS_UMAC_GDSCR__RETAIN_FF_ENABLE___M 0x00000800 +#define CC_WCSS_UMAC_GDSCR__RETAIN_FF_ENABLE___S 11 +#define CC_WCSS_UMAC_GDSCR__RETAIN_FF_ENABLE__DISABLE 0x0 +#define CC_WCSS_UMAC_GDSCR__RETAIN_FF_ENABLE__ENABLE 0x1 +#define CC_WCSS_UMAC_GDSCR__RESTORE___M 0x00000400 +#define CC_WCSS_UMAC_GDSCR__RESTORE___S 10 +#define CC_WCSS_UMAC_GDSCR__RESTORE__DISABLE 0x0 +#define CC_WCSS_UMAC_GDSCR__RESTORE__ENABLE 0x1 +#define CC_WCSS_UMAC_GDSCR__SAVE___M 0x00000200 +#define CC_WCSS_UMAC_GDSCR__SAVE___S 9 +#define CC_WCSS_UMAC_GDSCR__SAVE__DISABLE 0x0 +#define CC_WCSS_UMAC_GDSCR__SAVE__ENABLE 0x1 +#define CC_WCSS_UMAC_GDSCR__RETAIN___M 0x00000100 +#define CC_WCSS_UMAC_GDSCR__RETAIN___S 8 +#define CC_WCSS_UMAC_GDSCR__RETAIN__DISABLE 0x0 +#define CC_WCSS_UMAC_GDSCR__RETAIN__ENABLE 0x1 +#define CC_WCSS_UMAC_GDSCR__EN_REST___M 0x00000080 +#define CC_WCSS_UMAC_GDSCR__EN_REST___S 7 +#define CC_WCSS_UMAC_GDSCR__EN_REST__DISABLE 0x0 +#define CC_WCSS_UMAC_GDSCR__EN_REST__ENABLE 0x1 +#define CC_WCSS_UMAC_GDSCR__EN_FEW___M 0x00000040 +#define CC_WCSS_UMAC_GDSCR__EN_FEW___S 6 +#define CC_WCSS_UMAC_GDSCR__EN_FEW__DISABLE 0x0 +#define CC_WCSS_UMAC_GDSCR__EN_FEW__ENABLE 0x1 +#define CC_WCSS_UMAC_GDSCR__CLAMP_IO___M 0x00000020 +#define CC_WCSS_UMAC_GDSCR__CLAMP_IO___S 5 +#define CC_WCSS_UMAC_GDSCR__CLAMP_IO__DISABLE 0x0 +#define CC_WCSS_UMAC_GDSCR__CLAMP_IO__ENABLE 0x1 +#define CC_WCSS_UMAC_GDSCR__CLK_DISABLE___M 0x00000010 +#define CC_WCSS_UMAC_GDSCR__CLK_DISABLE___S 4 +#define CC_WCSS_UMAC_GDSCR__CLK_DISABLE__CLK_NOT_DISABLE 0x0 +#define CC_WCSS_UMAC_GDSCR__CLK_DISABLE__CLK_DISABLE 0x1 +#define CC_WCSS_UMAC_GDSCR__PD_ARES___M 0x00000008 +#define CC_WCSS_UMAC_GDSCR__PD_ARES___S 3 +#define CC_WCSS_UMAC_GDSCR__PD_ARES__NO_RESET 0x0 +#define CC_WCSS_UMAC_GDSCR__PD_ARES__RESET 0x1 +#define CC_WCSS_UMAC_GDSCR__SW_OVERRIDE___M 0x00000004 +#define CC_WCSS_UMAC_GDSCR__SW_OVERRIDE___S 2 +#define CC_WCSS_UMAC_GDSCR__SW_OVERRIDE__DISABLE 0x0 +#define CC_WCSS_UMAC_GDSCR__SW_OVERRIDE__ENABLE 0x1 +#define CC_WCSS_UMAC_GDSCR__HW_CONTROL___M 0x00000002 +#define CC_WCSS_UMAC_GDSCR__HW_CONTROL___S 1 +#define CC_WCSS_UMAC_GDSCR__HW_CONTROL__DISABLE 0x0 +#define CC_WCSS_UMAC_GDSCR__HW_CONTROL__ENABLE 0x1 +#define CC_WCSS_UMAC_GDSCR__SW_COLLAPSE___M 0x00000001 +#define CC_WCSS_UMAC_GDSCR__SW_COLLAPSE___S 0 +#define CC_WCSS_UMAC_GDSCR__SW_COLLAPSE__DISABLE 0x0 +#define CC_WCSS_UMAC_GDSCR__SW_COLLAPSE__ENABLE 0x1 +#define CC_WCSS_UMAC_GDSCR___M 0xF8FFFFFF +#define CC_WCSS_UMAC_GDSCR___S 0 + +#define CC_WCSS_UMAC_CFG_GDSCR (0x00CB01B0) +#define CC_WCSS_UMAC_CFG_GDSCR___RWC QCSR_REG_RW +#define CC_WCSS_UMAC_CFG_GDSCR___POR 0x00070000 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_SPARE_CTRL_IN___POR 0x0 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_SPARE_CTRL_OUT___POR 0x0 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_PWR_DWN_START___POR 0x0 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_PWR_UP_START___POR 0x0 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_CFG_FSM_STATE_STATUS___POR 0x0 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_MEM_PWR_ACK_STATUS___POR 0x0 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_ENR_ACK_STATUS___POR 0x1 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_ENF_ACK_STATUS___POR 0x1 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_POWER_UP_COMPLETE___POR 0x1 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_POWER_DOWN_COMPLETE___POR 0x0 +#define CC_WCSS_UMAC_CFG_GDSCR__SOFTWARE_CONTROL_OVERRIDE___POR 0x0 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_HANDSHAKE_DIS___POR 0x0 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_MEM_PERI_FORCE_IN_SW___POR 0x0 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_MEM_CORE_FORCE_IN_SW___POR 0x0 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_PHASE_RESET_EN_SW___POR 0x0 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_PHASE_RESET_DELAY_COUNT_SW___POR 0x0 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_PSCBC_PWR_DWN_SW___POR 0x0 +#define CC_WCSS_UMAC_CFG_GDSCR__UNCLAMP_IO_SOFTWARE_OVERRIDE___POR 0x0 +#define CC_WCSS_UMAC_CFG_GDSCR__SAVE_RESTORE_SOFTWARE_OVERRIDE___POR 0x0 +#define CC_WCSS_UMAC_CFG_GDSCR__CLAMP_IO_SOFTWARE_OVERRIDE___POR 0x0 +#define CC_WCSS_UMAC_CFG_GDSCR__DISABLE_CLK_SOFTWARE_OVERRIDE___POR 0x0 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_SPARE_CTRL_IN___M 0xF0000000 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_SPARE_CTRL_IN___S 28 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_SPARE_CTRL_OUT___M 0x0C000000 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_SPARE_CTRL_OUT___S 26 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_PWR_DWN_START___M 0x02000000 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_PWR_DWN_START___S 25 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_PWR_UP_START___M 0x01000000 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_PWR_UP_START___S 24 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_CFG_FSM_STATE_STATUS___M 0x00F00000 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_CFG_FSM_STATE_STATUS___S 20 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_MEM_PWR_ACK_STATUS___M 0x00080000 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_MEM_PWR_ACK_STATUS___S 19 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_ENR_ACK_STATUS___M 0x00040000 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_ENR_ACK_STATUS___S 18 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_ENF_ACK_STATUS___M 0x00020000 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_ENF_ACK_STATUS___S 17 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_POWER_UP_COMPLETE___M 0x00010000 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_POWER_UP_COMPLETE___S 16 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_POWER_DOWN_COMPLETE___M 0x00008000 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_POWER_DOWN_COMPLETE___S 15 +#define CC_WCSS_UMAC_CFG_GDSCR__SOFTWARE_CONTROL_OVERRIDE___M 0x00007800 +#define CC_WCSS_UMAC_CFG_GDSCR__SOFTWARE_CONTROL_OVERRIDE___S 11 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_HANDSHAKE_DIS___M 0x00000400 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_HANDSHAKE_DIS___S 10 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_MEM_PERI_FORCE_IN_SW___M 0x00000200 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_MEM_PERI_FORCE_IN_SW___S 9 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_MEM_CORE_FORCE_IN_SW___M 0x00000100 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_MEM_CORE_FORCE_IN_SW___S 8 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_PHASE_RESET_EN_SW___M 0x00000080 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_PHASE_RESET_EN_SW___S 7 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_PHASE_RESET_DELAY_COUNT_SW___M 0x00000060 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_PHASE_RESET_DELAY_COUNT_SW___S 5 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_PSCBC_PWR_DWN_SW___M 0x00000010 +#define CC_WCSS_UMAC_CFG_GDSCR__GDSC_PSCBC_PWR_DWN_SW___S 4 +#define CC_WCSS_UMAC_CFG_GDSCR__UNCLAMP_IO_SOFTWARE_OVERRIDE___M 0x00000008 +#define CC_WCSS_UMAC_CFG_GDSCR__UNCLAMP_IO_SOFTWARE_OVERRIDE___S 3 +#define CC_WCSS_UMAC_CFG_GDSCR__SAVE_RESTORE_SOFTWARE_OVERRIDE___M 0x00000004 +#define CC_WCSS_UMAC_CFG_GDSCR__SAVE_RESTORE_SOFTWARE_OVERRIDE___S 2 +#define CC_WCSS_UMAC_CFG_GDSCR__CLAMP_IO_SOFTWARE_OVERRIDE___M 0x00000002 +#define CC_WCSS_UMAC_CFG_GDSCR__CLAMP_IO_SOFTWARE_OVERRIDE___S 1 +#define CC_WCSS_UMAC_CFG_GDSCR__DISABLE_CLK_SOFTWARE_OVERRIDE___M 0x00000001 +#define CC_WCSS_UMAC_CFG_GDSCR__DISABLE_CLK_SOFTWARE_OVERRIDE___S 0 +#define CC_WCSS_UMAC_CFG_GDSCR___M 0xFFFFFFFF +#define CC_WCSS_UMAC_CFG_GDSCR___S 0 + +#define CC_WCSS_UMAC_CFG2_GDSCR (0x00CB01B4) +#define CC_WCSS_UMAC_CFG2_GDSCR___RWC QCSR_REG_RW +#define CC_WCSS_UMAC_CFG2_GDSCR___POR 0x0000022A +#define CC_WCSS_UMAC_CFG2_GDSCR__GDSC_CLAMP_MEM_SW___POR 0x0 +#define CC_WCSS_UMAC_CFG2_GDSCR__DLY_MEM_PWR_UP___POR 0x0 +#define CC_WCSS_UMAC_CFG2_GDSCR__DLY_DEASSERT_CLAMP_MEM___POR 0x2 +#define CC_WCSS_UMAC_CFG2_GDSCR__DLY_ASSERT_CLAMP_MEM___POR 0x2 +#define CC_WCSS_UMAC_CFG2_GDSCR__MEM_PWR_DWN_TIMEOUT___POR 0xA +#define CC_WCSS_UMAC_CFG2_GDSCR__GDSC_CLAMP_MEM_SW___M 0x00010000 +#define CC_WCSS_UMAC_CFG2_GDSCR__GDSC_CLAMP_MEM_SW___S 16 +#define CC_WCSS_UMAC_CFG2_GDSCR__DLY_MEM_PWR_UP___M 0x0000F000 +#define CC_WCSS_UMAC_CFG2_GDSCR__DLY_MEM_PWR_UP___S 12 +#define CC_WCSS_UMAC_CFG2_GDSCR__DLY_DEASSERT_CLAMP_MEM___M 0x00000F00 +#define CC_WCSS_UMAC_CFG2_GDSCR__DLY_DEASSERT_CLAMP_MEM___S 8 +#define CC_WCSS_UMAC_CFG2_GDSCR__DLY_ASSERT_CLAMP_MEM___M 0x000000F0 +#define CC_WCSS_UMAC_CFG2_GDSCR__DLY_ASSERT_CLAMP_MEM___S 4 +#define CC_WCSS_UMAC_CFG2_GDSCR__MEM_PWR_DWN_TIMEOUT___M 0x0000000F +#define CC_WCSS_UMAC_CFG2_GDSCR__MEM_PWR_DWN_TIMEOUT___S 0 +#define CC_WCSS_UMAC_CFG2_GDSCR___M 0x0001FFFF +#define CC_WCSS_UMAC_CFG2_GDSCR___S 0 + +#define CC_WCSS_UMAC_NOC_CBCR (0x00CB01B8) +#define CC_WCSS_UMAC_NOC_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_UMAC_NOC_CBCR___POR 0x80000220 +#define CC_WCSS_UMAC_NOC_CBCR__CLK_OFF___POR 0x1 +#define CC_WCSS_UMAC_NOC_CBCR__FORCE_MEM_CORE_ON___POR 0x0 +#define CC_WCSS_UMAC_NOC_CBCR__FORCE_MEM_PERIPH_ON___POR 0x0 +#define CC_WCSS_UMAC_NOC_CBCR__FORCE_MEM_PERIPH_OFF___POR 0x0 +#define CC_WCSS_UMAC_NOC_CBCR__WAKEUP___POR 0x2 +#define CC_WCSS_UMAC_NOC_CBCR__SLEEP___POR 0x2 +#define CC_WCSS_UMAC_NOC_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_UMAC_NOC_CBCR__CLK_ENABLE___POR 0x0 +#define CC_WCSS_UMAC_NOC_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_UMAC_NOC_CBCR__CLK_OFF___S 31 +#define CC_WCSS_UMAC_NOC_CBCR__FORCE_MEM_CORE_ON___M 0x00004000 +#define CC_WCSS_UMAC_NOC_CBCR__FORCE_MEM_CORE_ON___S 14 +#define CC_WCSS_UMAC_NOC_CBCR__FORCE_MEM_CORE_ON__FORCE_DISABLE 0x0 +#define CC_WCSS_UMAC_NOC_CBCR__FORCE_MEM_CORE_ON__FORCE_ENABLE 0x1 +#define CC_WCSS_UMAC_NOC_CBCR__FORCE_MEM_PERIPH_ON___M 0x00002000 +#define CC_WCSS_UMAC_NOC_CBCR__FORCE_MEM_PERIPH_ON___S 13 +#define CC_WCSS_UMAC_NOC_CBCR__FORCE_MEM_PERIPH_ON__FORCE_DISABLE 0x0 +#define CC_WCSS_UMAC_NOC_CBCR__FORCE_MEM_PERIPH_ON__FORCE_ENABLE 0x1 +#define CC_WCSS_UMAC_NOC_CBCR__FORCE_MEM_PERIPH_OFF___M 0x00001000 +#define CC_WCSS_UMAC_NOC_CBCR__FORCE_MEM_PERIPH_OFF___S 12 +#define CC_WCSS_UMAC_NOC_CBCR__FORCE_MEM_PERIPH_OFF__FORCE_DISABLE 0x0 +#define CC_WCSS_UMAC_NOC_CBCR__FORCE_MEM_PERIPH_OFF__FORCE_ENABLE 0x1 +#define CC_WCSS_UMAC_NOC_CBCR__WAKEUP___M 0x00000F00 +#define CC_WCSS_UMAC_NOC_CBCR__WAKEUP___S 8 +#define CC_WCSS_UMAC_NOC_CBCR__WAKEUP__CLOCK0 0x0 +#define CC_WCSS_UMAC_NOC_CBCR__WAKEUP__CLOCK1 0x1 +#define CC_WCSS_UMAC_NOC_CBCR__WAKEUP__CLOCK2 0x2 +#define CC_WCSS_UMAC_NOC_CBCR__WAKEUP__CLOCK3 0x3 +#define CC_WCSS_UMAC_NOC_CBCR__WAKEUP__CLOCK4 0x4 +#define CC_WCSS_UMAC_NOC_CBCR__WAKEUP__CLOCK5 0x5 +#define CC_WCSS_UMAC_NOC_CBCR__WAKEUP__CLOCK6 0x6 +#define CC_WCSS_UMAC_NOC_CBCR__WAKEUP__CLOCK7 0x7 +#define CC_WCSS_UMAC_NOC_CBCR__WAKEUP__CLOCK8 0x8 +#define CC_WCSS_UMAC_NOC_CBCR__WAKEUP__CLOCK9 0x9 +#define CC_WCSS_UMAC_NOC_CBCR__WAKEUP__CLOCK10 0xA +#define CC_WCSS_UMAC_NOC_CBCR__WAKEUP__CLOCK11 0xB +#define CC_WCSS_UMAC_NOC_CBCR__WAKEUP__CLOCK12 0xC +#define CC_WCSS_UMAC_NOC_CBCR__WAKEUP__CLOCK13 0xD +#define CC_WCSS_UMAC_NOC_CBCR__WAKEUP__CLOCK14 0xE +#define CC_WCSS_UMAC_NOC_CBCR__WAKEUP__CLOCK15 0xF +#define CC_WCSS_UMAC_NOC_CBCR__SLEEP___M 0x000000F0 +#define CC_WCSS_UMAC_NOC_CBCR__SLEEP___S 4 +#define CC_WCSS_UMAC_NOC_CBCR__SLEEP__CLOCK0 0x0 +#define CC_WCSS_UMAC_NOC_CBCR__SLEEP__CLOCK1 0x1 +#define CC_WCSS_UMAC_NOC_CBCR__SLEEP__CLOCK2 0x2 +#define CC_WCSS_UMAC_NOC_CBCR__SLEEP__CLOCK3 0x3 +#define CC_WCSS_UMAC_NOC_CBCR__SLEEP__CLOCK4 0x4 +#define CC_WCSS_UMAC_NOC_CBCR__SLEEP__CLOCK5 0x5 +#define CC_WCSS_UMAC_NOC_CBCR__SLEEP__CLOCK6 0x6 +#define CC_WCSS_UMAC_NOC_CBCR__SLEEP__CLOCK7 0x7 +#define CC_WCSS_UMAC_NOC_CBCR__SLEEP__CLOCK8 0x8 +#define CC_WCSS_UMAC_NOC_CBCR__SLEEP__CLOCK9 0x9 +#define CC_WCSS_UMAC_NOC_CBCR__SLEEP__CLOCK10 0xA +#define CC_WCSS_UMAC_NOC_CBCR__SLEEP__CLOCK11 0xB +#define CC_WCSS_UMAC_NOC_CBCR__SLEEP__CLOCK12 0xC +#define CC_WCSS_UMAC_NOC_CBCR__SLEEP__CLOCK13 0xD +#define CC_WCSS_UMAC_NOC_CBCR__SLEEP__CLOCK14 0xE +#define CC_WCSS_UMAC_NOC_CBCR__SLEEP__CLOCK15 0xF +#define CC_WCSS_UMAC_NOC_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_UMAC_NOC_CBCR__CLK_ARES___S 2 +#define CC_WCSS_UMAC_NOC_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_UMAC_NOC_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_UMAC_NOC_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_UMAC_NOC_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_UMAC_NOC_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_UMAC_NOC_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_UMAC_NOC_CBCR___M 0x80007FF5 +#define CC_WCSS_UMAC_NOC_CBCR___S 0 + +#define CC_WCSS_UMAC_NOC_SREGR (0x00CB01BC) +#define CC_WCSS_UMAC_NOC_SREGR___RWC QCSR_REG_RW +#define CC_WCSS_UMAC_NOC_SREGR___POR 0x00000000 +#define CC_WCSS_UMAC_NOC_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___POR 0x00 +#define CC_WCSS_UMAC_NOC_SREGR__SREG_PSCBC_SPARE_CTRL_IN___POR 0x00 +#define CC_WCSS_UMAC_NOC_SREGR__RESERVE_BITS15_13___POR 0x0 +#define CC_WCSS_UMAC_NOC_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___POR 0x0 +#define CC_WCSS_UMAC_NOC_SREGR__SW_DIV_RATIO_SLP_STG_CLK___POR 0x0 +#define CC_WCSS_UMAC_NOC_SREGR__FORCE_CLK_ON___POR 0x0 +#define CC_WCSS_UMAC_NOC_SREGR__SW_RST_SEL_SLP_STG___POR 0x0 +#define CC_WCSS_UMAC_NOC_SREGR__SW_RST_SLP_STG___POR 0x0 +#define CC_WCSS_UMAC_NOC_SREGR__SW_CTRL_PWR_DOWN___POR 0x0 +#define CC_WCSS_UMAC_NOC_SREGR__SW_CLK_EN_SEL_SLP_STG___POR 0x0 +#define CC_WCSS_UMAC_NOC_SREGR__SW_CLK_EN_SLP_STG___POR 0x0 +#define CC_WCSS_UMAC_NOC_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___M 0xFF000000 +#define CC_WCSS_UMAC_NOC_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___S 24 +#define CC_WCSS_UMAC_NOC_SREGR__SREG_PSCBC_SPARE_CTRL_IN___M 0x00FF0000 +#define CC_WCSS_UMAC_NOC_SREGR__SREG_PSCBC_SPARE_CTRL_IN___S 16 +#define CC_WCSS_UMAC_NOC_SREGR__RESERVE_BITS15_13___M 0x0000E000 +#define CC_WCSS_UMAC_NOC_SREGR__RESERVE_BITS15_13___S 13 +#define CC_WCSS_UMAC_NOC_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___M 0x00001000 +#define CC_WCSS_UMAC_NOC_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___S 12 +#define CC_WCSS_UMAC_NOC_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE__NO_RESET 0x0 +#define CC_WCSS_UMAC_NOC_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE__RESET 0x1 +#define CC_WCSS_UMAC_NOC_SREGR__SW_DIV_RATIO_SLP_STG_CLK___M 0x00000300 +#define CC_WCSS_UMAC_NOC_SREGR__SW_DIV_RATIO_SLP_STG_CLK___S 8 +#define CC_WCSS_UMAC_NOC_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_1 0x0 +#define CC_WCSS_UMAC_NOC_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_2 0x1 +#define CC_WCSS_UMAC_NOC_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_4 0x2 +#define CC_WCSS_UMAC_NOC_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_8 0x3 +#define CC_WCSS_UMAC_NOC_SREGR__FORCE_CLK_ON___M 0x00000040 +#define CC_WCSS_UMAC_NOC_SREGR__FORCE_CLK_ON___S 6 +#define CC_WCSS_UMAC_NOC_SREGR__FORCE_CLK_ON__NO_FORCE 0x0 +#define CC_WCSS_UMAC_NOC_SREGR__FORCE_CLK_ON__FORCE_ENABLE 0x1 +#define CC_WCSS_UMAC_NOC_SREGR__SW_RST_SEL_SLP_STG___M 0x00000020 +#define CC_WCSS_UMAC_NOC_SREGR__SW_RST_SEL_SLP_STG___S 5 +#define CC_WCSS_UMAC_NOC_SREGR__SW_RST_SEL_SLP_STG__SELECT_THE_HARDWARE_ARES 0x0 +#define CC_WCSS_UMAC_NOC_SREGR__SW_RST_SEL_SLP_STG__SELECT_THE_SW_RST_SLP_STG_BIT 0x1 +#define CC_WCSS_UMAC_NOC_SREGR__SW_RST_SLP_STG___M 0x00000010 +#define CC_WCSS_UMAC_NOC_SREGR__SW_RST_SLP_STG___S 4 +#define CC_WCSS_UMAC_NOC_SREGR__SW_RST_SLP_STG__DE_ASSERTION_OF_THE_RESET 0x0 +#define CC_WCSS_UMAC_NOC_SREGR__SW_RST_SLP_STG__ASSERTION_OF_THE_RESET 0x1 +#define CC_WCSS_UMAC_NOC_SREGR__SW_CTRL_PWR_DOWN___M 0x00000008 +#define CC_WCSS_UMAC_NOC_SREGR__SW_CTRL_PWR_DOWN___S 3 +#define CC_WCSS_UMAC_NOC_SREGR__SW_CTRL_PWR_DOWN__NO_SW_CTRL 0x0 +#define CC_WCSS_UMAC_NOC_SREGR__SW_CTRL_PWR_DOWN__SW_CTRL 0x1 +#define CC_WCSS_UMAC_NOC_SREGR__SW_CLK_EN_SEL_SLP_STG___M 0x00000004 +#define CC_WCSS_UMAC_NOC_SREGR__SW_CLK_EN_SEL_SLP_STG___S 2 +#define CC_WCSS_UMAC_NOC_SREGR__SW_CLK_EN_SEL_SLP_STG__SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM 0x0 +#define CC_WCSS_UMAC_NOC_SREGR__SW_CLK_EN_SEL_SLP_STG__SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT 0x1 +#define CC_WCSS_UMAC_NOC_SREGR__SW_CLK_EN_SLP_STG___M 0x00000002 +#define CC_WCSS_UMAC_NOC_SREGR__SW_CLK_EN_SLP_STG___S 1 +#define CC_WCSS_UMAC_NOC_SREGR__SW_CLK_EN_SLP_STG__SLP_STG_CLOCK_DISABLE 0x0 +#define CC_WCSS_UMAC_NOC_SREGR__SW_CLK_EN_SLP_STG__SLP_STG_CLOCK_ENABLE 0x1 +#define CC_WCSS_UMAC_NOC_SREGR___M 0xFFFFF37E +#define CC_WCSS_UMAC_NOC_SREGR___S 1 + +#define CC_WCSS_UMAC_AHB_CBCR (0x00CB01C0) +#define CC_WCSS_UMAC_AHB_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_UMAC_AHB_CBCR___POR 0x80000220 +#define CC_WCSS_UMAC_AHB_CBCR__CLK_OFF___POR 0x1 +#define CC_WCSS_UMAC_AHB_CBCR__FORCE_MEM_CORE_ON___POR 0x0 +#define CC_WCSS_UMAC_AHB_CBCR__FORCE_MEM_PERIPH_ON___POR 0x0 +#define CC_WCSS_UMAC_AHB_CBCR__FORCE_MEM_PERIPH_OFF___POR 0x0 +#define CC_WCSS_UMAC_AHB_CBCR__WAKEUP___POR 0x2 +#define CC_WCSS_UMAC_AHB_CBCR__SLEEP___POR 0x2 +#define CC_WCSS_UMAC_AHB_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_UMAC_AHB_CBCR__CLK_ENABLE___POR 0x0 +#define CC_WCSS_UMAC_AHB_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_UMAC_AHB_CBCR__CLK_OFF___S 31 +#define CC_WCSS_UMAC_AHB_CBCR__FORCE_MEM_CORE_ON___M 0x00004000 +#define CC_WCSS_UMAC_AHB_CBCR__FORCE_MEM_CORE_ON___S 14 +#define CC_WCSS_UMAC_AHB_CBCR__FORCE_MEM_CORE_ON__FORCE_DISABLE 0x0 +#define CC_WCSS_UMAC_AHB_CBCR__FORCE_MEM_CORE_ON__FORCE_ENABLE 0x1 +#define CC_WCSS_UMAC_AHB_CBCR__FORCE_MEM_PERIPH_ON___M 0x00002000 +#define CC_WCSS_UMAC_AHB_CBCR__FORCE_MEM_PERIPH_ON___S 13 +#define CC_WCSS_UMAC_AHB_CBCR__FORCE_MEM_PERIPH_ON__FORCE_DISABLE 0x0 +#define CC_WCSS_UMAC_AHB_CBCR__FORCE_MEM_PERIPH_ON__FORCE_ENABLE 0x1 +#define CC_WCSS_UMAC_AHB_CBCR__FORCE_MEM_PERIPH_OFF___M 0x00001000 +#define CC_WCSS_UMAC_AHB_CBCR__FORCE_MEM_PERIPH_OFF___S 12 +#define CC_WCSS_UMAC_AHB_CBCR__FORCE_MEM_PERIPH_OFF__FORCE_DISABLE 0x0 +#define CC_WCSS_UMAC_AHB_CBCR__FORCE_MEM_PERIPH_OFF__FORCE_ENABLE 0x1 +#define CC_WCSS_UMAC_AHB_CBCR__WAKEUP___M 0x00000F00 +#define CC_WCSS_UMAC_AHB_CBCR__WAKEUP___S 8 +#define CC_WCSS_UMAC_AHB_CBCR__WAKEUP__CLOCK0 0x0 +#define CC_WCSS_UMAC_AHB_CBCR__WAKEUP__CLOCK1 0x1 +#define CC_WCSS_UMAC_AHB_CBCR__WAKEUP__CLOCK2 0x2 +#define CC_WCSS_UMAC_AHB_CBCR__WAKEUP__CLOCK3 0x3 +#define CC_WCSS_UMAC_AHB_CBCR__WAKEUP__CLOCK4 0x4 +#define CC_WCSS_UMAC_AHB_CBCR__WAKEUP__CLOCK5 0x5 +#define CC_WCSS_UMAC_AHB_CBCR__WAKEUP__CLOCK6 0x6 +#define CC_WCSS_UMAC_AHB_CBCR__WAKEUP__CLOCK7 0x7 +#define CC_WCSS_UMAC_AHB_CBCR__WAKEUP__CLOCK8 0x8 +#define CC_WCSS_UMAC_AHB_CBCR__WAKEUP__CLOCK9 0x9 +#define CC_WCSS_UMAC_AHB_CBCR__WAKEUP__CLOCK10 0xA +#define CC_WCSS_UMAC_AHB_CBCR__WAKEUP__CLOCK11 0xB +#define CC_WCSS_UMAC_AHB_CBCR__WAKEUP__CLOCK12 0xC +#define CC_WCSS_UMAC_AHB_CBCR__WAKEUP__CLOCK13 0xD +#define CC_WCSS_UMAC_AHB_CBCR__WAKEUP__CLOCK14 0xE +#define CC_WCSS_UMAC_AHB_CBCR__WAKEUP__CLOCK15 0xF +#define CC_WCSS_UMAC_AHB_CBCR__SLEEP___M 0x000000F0 +#define CC_WCSS_UMAC_AHB_CBCR__SLEEP___S 4 +#define CC_WCSS_UMAC_AHB_CBCR__SLEEP__CLOCK0 0x0 +#define CC_WCSS_UMAC_AHB_CBCR__SLEEP__CLOCK1 0x1 +#define CC_WCSS_UMAC_AHB_CBCR__SLEEP__CLOCK2 0x2 +#define CC_WCSS_UMAC_AHB_CBCR__SLEEP__CLOCK3 0x3 +#define CC_WCSS_UMAC_AHB_CBCR__SLEEP__CLOCK4 0x4 +#define CC_WCSS_UMAC_AHB_CBCR__SLEEP__CLOCK5 0x5 +#define CC_WCSS_UMAC_AHB_CBCR__SLEEP__CLOCK6 0x6 +#define CC_WCSS_UMAC_AHB_CBCR__SLEEP__CLOCK7 0x7 +#define CC_WCSS_UMAC_AHB_CBCR__SLEEP__CLOCK8 0x8 +#define CC_WCSS_UMAC_AHB_CBCR__SLEEP__CLOCK9 0x9 +#define CC_WCSS_UMAC_AHB_CBCR__SLEEP__CLOCK10 0xA +#define CC_WCSS_UMAC_AHB_CBCR__SLEEP__CLOCK11 0xB +#define CC_WCSS_UMAC_AHB_CBCR__SLEEP__CLOCK12 0xC +#define CC_WCSS_UMAC_AHB_CBCR__SLEEP__CLOCK13 0xD +#define CC_WCSS_UMAC_AHB_CBCR__SLEEP__CLOCK14 0xE +#define CC_WCSS_UMAC_AHB_CBCR__SLEEP__CLOCK15 0xF +#define CC_WCSS_UMAC_AHB_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_UMAC_AHB_CBCR__CLK_ARES___S 2 +#define CC_WCSS_UMAC_AHB_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_UMAC_AHB_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_UMAC_AHB_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_UMAC_AHB_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_UMAC_AHB_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_UMAC_AHB_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_UMAC_AHB_CBCR___M 0x80007FF5 +#define CC_WCSS_UMAC_AHB_CBCR___S 0 + +#define CC_WCSS_UMAC_AHB_SREGR (0x00CB01C4) +#define CC_WCSS_UMAC_AHB_SREGR___RWC QCSR_REG_RW +#define CC_WCSS_UMAC_AHB_SREGR___POR 0x00000000 +#define CC_WCSS_UMAC_AHB_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___POR 0x00 +#define CC_WCSS_UMAC_AHB_SREGR__SREG_PSCBC_SPARE_CTRL_IN___POR 0x00 +#define CC_WCSS_UMAC_AHB_SREGR__RESERVE_BITS15_13___POR 0x0 +#define CC_WCSS_UMAC_AHB_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___POR 0x0 +#define CC_WCSS_UMAC_AHB_SREGR__SW_DIV_RATIO_SLP_STG_CLK___POR 0x0 +#define CC_WCSS_UMAC_AHB_SREGR__FORCE_CLK_ON___POR 0x0 +#define CC_WCSS_UMAC_AHB_SREGR__SW_RST_SEL_SLP_STG___POR 0x0 +#define CC_WCSS_UMAC_AHB_SREGR__SW_RST_SLP_STG___POR 0x0 +#define CC_WCSS_UMAC_AHB_SREGR__SW_CTRL_PWR_DOWN___POR 0x0 +#define CC_WCSS_UMAC_AHB_SREGR__SW_CLK_EN_SEL_SLP_STG___POR 0x0 +#define CC_WCSS_UMAC_AHB_SREGR__SW_CLK_EN_SLP_STG___POR 0x0 +#define CC_WCSS_UMAC_AHB_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___M 0xFF000000 +#define CC_WCSS_UMAC_AHB_SREGR__SREG_PSCBC_SPARE_CTRL_OUT___S 24 +#define CC_WCSS_UMAC_AHB_SREGR__SREG_PSCBC_SPARE_CTRL_IN___M 0x00FF0000 +#define CC_WCSS_UMAC_AHB_SREGR__SREG_PSCBC_SPARE_CTRL_IN___S 16 +#define CC_WCSS_UMAC_AHB_SREGR__RESERVE_BITS15_13___M 0x0000E000 +#define CC_WCSS_UMAC_AHB_SREGR__RESERVE_BITS15_13___S 13 +#define CC_WCSS_UMAC_AHB_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___M 0x00001000 +#define CC_WCSS_UMAC_AHB_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE___S 12 +#define CC_WCSS_UMAC_AHB_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE__NO_RESET 0x0 +#define CC_WCSS_UMAC_AHB_SREGR__SW_SM_PSCBC_SEQ_IN_OVERRIDE__RESET 0x1 +#define CC_WCSS_UMAC_AHB_SREGR__SW_DIV_RATIO_SLP_STG_CLK___M 0x00000300 +#define CC_WCSS_UMAC_AHB_SREGR__SW_DIV_RATIO_SLP_STG_CLK___S 8 +#define CC_WCSS_UMAC_AHB_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_1 0x0 +#define CC_WCSS_UMAC_AHB_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_2 0x1 +#define CC_WCSS_UMAC_AHB_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_4 0x2 +#define CC_WCSS_UMAC_AHB_SREGR__SW_DIV_RATIO_SLP_STG_CLK__DIV_BY_8 0x3 +#define CC_WCSS_UMAC_AHB_SREGR__FORCE_CLK_ON___M 0x00000040 +#define CC_WCSS_UMAC_AHB_SREGR__FORCE_CLK_ON___S 6 +#define CC_WCSS_UMAC_AHB_SREGR__FORCE_CLK_ON__NO_FORCE 0x0 +#define CC_WCSS_UMAC_AHB_SREGR__FORCE_CLK_ON__FORCE_ENABLE 0x1 +#define CC_WCSS_UMAC_AHB_SREGR__SW_RST_SEL_SLP_STG___M 0x00000020 +#define CC_WCSS_UMAC_AHB_SREGR__SW_RST_SEL_SLP_STG___S 5 +#define CC_WCSS_UMAC_AHB_SREGR__SW_RST_SEL_SLP_STG__SELECT_THE_HARDWARE_ARES 0x0 +#define CC_WCSS_UMAC_AHB_SREGR__SW_RST_SEL_SLP_STG__SELECT_THE_SW_RST_SLP_STG_BIT 0x1 +#define CC_WCSS_UMAC_AHB_SREGR__SW_RST_SLP_STG___M 0x00000010 +#define CC_WCSS_UMAC_AHB_SREGR__SW_RST_SLP_STG___S 4 +#define CC_WCSS_UMAC_AHB_SREGR__SW_RST_SLP_STG__DE_ASSERTION_OF_THE_RESET 0x0 +#define CC_WCSS_UMAC_AHB_SREGR__SW_RST_SLP_STG__ASSERTION_OF_THE_RESET 0x1 +#define CC_WCSS_UMAC_AHB_SREGR__SW_CTRL_PWR_DOWN___M 0x00000008 +#define CC_WCSS_UMAC_AHB_SREGR__SW_CTRL_PWR_DOWN___S 3 +#define CC_WCSS_UMAC_AHB_SREGR__SW_CTRL_PWR_DOWN__NO_SW_CTRL 0x0 +#define CC_WCSS_UMAC_AHB_SREGR__SW_CTRL_PWR_DOWN__SW_CTRL 0x1 +#define CC_WCSS_UMAC_AHB_SREGR__SW_CLK_EN_SEL_SLP_STG___M 0x00000004 +#define CC_WCSS_UMAC_AHB_SREGR__SW_CLK_EN_SEL_SLP_STG___S 2 +#define CC_WCSS_UMAC_AHB_SREGR__SW_CLK_EN_SEL_SLP_STG__SLP_STG_CLK_GATE_CONTROLD_BY_HW_FSM 0x0 +#define CC_WCSS_UMAC_AHB_SREGR__SW_CLK_EN_SEL_SLP_STG__SLP_STG_CLK_GATE_CONTROLD_BY_SW_CLK_EN_SLP_STG_BIT 0x1 +#define CC_WCSS_UMAC_AHB_SREGR__SW_CLK_EN_SLP_STG___M 0x00000002 +#define CC_WCSS_UMAC_AHB_SREGR__SW_CLK_EN_SLP_STG___S 1 +#define CC_WCSS_UMAC_AHB_SREGR__SW_CLK_EN_SLP_STG__SLP_STG_CLOCK_DISABLE 0x0 +#define CC_WCSS_UMAC_AHB_SREGR__SW_CLK_EN_SLP_STG__SLP_STG_CLOCK_ENABLE 0x1 +#define CC_WCSS_UMAC_AHB_SREGR___M 0xFFFFF37E +#define CC_WCSS_UMAC_AHB_SREGR___S 1 + +#define CC_CLK_UMAC_INT_APB_CDIVR (0x00CB01C8) +#define CC_CLK_UMAC_INT_APB_CDIVR___RWC QCSR_REG_RW +#define CC_CLK_UMAC_INT_APB_CDIVR___POR 0x00000001 +#define CC_CLK_UMAC_INT_APB_CDIVR__CLK_DIV___POR 0x1 +#define CC_CLK_UMAC_INT_APB_CDIVR__CLK_DIV___M 0x00000003 +#define CC_CLK_UMAC_INT_APB_CDIVR__CLK_DIV___S 0 +#define CC_CLK_UMAC_INT_APB_CDIVR___M 0x00000003 +#define CC_CLK_UMAC_INT_APB_CDIVR___S 0 + +#define CC_WCSS_UMAC_MAC0_CBCR (0x00CB01CC) +#define CC_WCSS_UMAC_MAC0_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_UMAC_MAC0_CBCR___POR 0x80000000 +#define CC_WCSS_UMAC_MAC0_CBCR__CLK_OFF___POR 0x1 +#define CC_WCSS_UMAC_MAC0_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_UMAC_MAC0_CBCR__CLK_ENABLE___POR 0x0 +#define CC_WCSS_UMAC_MAC0_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_UMAC_MAC0_CBCR__CLK_OFF___S 31 +#define CC_WCSS_UMAC_MAC0_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_UMAC_MAC0_CBCR__CLK_ARES___S 2 +#define CC_WCSS_UMAC_MAC0_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_UMAC_MAC0_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_UMAC_MAC0_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_UMAC_MAC0_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_UMAC_MAC0_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_UMAC_MAC0_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_UMAC_MAC0_CBCR___M 0x80000005 +#define CC_WCSS_UMAC_MAC0_CBCR___S 0 + +#define CC_WCSS_UMAC_NOC_DBG_ATB_CBCR (0x00CB01D0) +#define CC_WCSS_UMAC_NOC_DBG_ATB_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_UMAC_NOC_DBG_ATB_CBCR___POR 0x00000001 +#define CC_WCSS_UMAC_NOC_DBG_ATB_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_UMAC_NOC_DBG_ATB_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_UMAC_NOC_DBG_ATB_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_UMAC_NOC_DBG_ATB_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_UMAC_NOC_DBG_ATB_CBCR__CLK_OFF___S 31 +#define CC_WCSS_UMAC_NOC_DBG_ATB_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_UMAC_NOC_DBG_ATB_CBCR__CLK_ARES___S 2 +#define CC_WCSS_UMAC_NOC_DBG_ATB_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_UMAC_NOC_DBG_ATB_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_UMAC_NOC_DBG_ATB_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_UMAC_NOC_DBG_ATB_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_UMAC_NOC_DBG_ATB_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_UMAC_NOC_DBG_ATB_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_UMAC_NOC_DBG_ATB_CBCR___M 0x80000005 +#define CC_WCSS_UMAC_NOC_DBG_ATB_CBCR___S 0 + +#define CC_WCSS_UMAC_NOC_DBG_APB_CBCR (0x00CB01D4) +#define CC_WCSS_UMAC_NOC_DBG_APB_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_UMAC_NOC_DBG_APB_CBCR___POR 0x00000001 +#define CC_WCSS_UMAC_NOC_DBG_APB_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_UMAC_NOC_DBG_APB_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_UMAC_NOC_DBG_APB_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_UMAC_NOC_DBG_APB_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_UMAC_NOC_DBG_APB_CBCR__CLK_OFF___S 31 +#define CC_WCSS_UMAC_NOC_DBG_APB_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_UMAC_NOC_DBG_APB_CBCR__CLK_ARES___S 2 +#define CC_WCSS_UMAC_NOC_DBG_APB_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_UMAC_NOC_DBG_APB_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_UMAC_NOC_DBG_APB_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_UMAC_NOC_DBG_APB_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_UMAC_NOC_DBG_APB_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_UMAC_NOC_DBG_APB_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_UMAC_NOC_DBG_APB_CBCR___M 0x80000005 +#define CC_WCSS_UMAC_NOC_DBG_APB_CBCR___S 0 + +#define CC_WCSS_UMAC_NOC_DBG_TS_CBCR (0x00CB01D8) +#define CC_WCSS_UMAC_NOC_DBG_TS_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_UMAC_NOC_DBG_TS_CBCR___POR 0x00000001 +#define CC_WCSS_UMAC_NOC_DBG_TS_CBCR__CLK_OFF___POR 0x0 +#define CC_WCSS_UMAC_NOC_DBG_TS_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_UMAC_NOC_DBG_TS_CBCR__CLK_ENABLE___POR 0x1 +#define CC_WCSS_UMAC_NOC_DBG_TS_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_UMAC_NOC_DBG_TS_CBCR__CLK_OFF___S 31 +#define CC_WCSS_UMAC_NOC_DBG_TS_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_UMAC_NOC_DBG_TS_CBCR__CLK_ARES___S 2 +#define CC_WCSS_UMAC_NOC_DBG_TS_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_UMAC_NOC_DBG_TS_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_UMAC_NOC_DBG_TS_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_UMAC_NOC_DBG_TS_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_UMAC_NOC_DBG_TS_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_UMAC_NOC_DBG_TS_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_UMAC_NOC_DBG_TS_CBCR___M 0x80000005 +#define CC_WCSS_UMAC_NOC_DBG_TS_CBCR___S 0 + +#define CC_WCSS_UMAC_WSI_CMD_RCGR (0x00CB01DC) +#define CC_WCSS_UMAC_WSI_CMD_RCGR___RWC QCSR_REG_RW +#define CC_WCSS_UMAC_WSI_CMD_RCGR___POR 0x80000000 +#define CC_WCSS_UMAC_WSI_CMD_RCGR__ROOT_OFF___POR 0x1 +#define CC_WCSS_UMAC_WSI_CMD_RCGR__DIRTY_CFG_RCGR___POR 0x0 +#define CC_WCSS_UMAC_WSI_CMD_RCGR__ROOT_EN___POR 0x0 +#define CC_WCSS_UMAC_WSI_CMD_RCGR__UPDATE___POR 0x0 +#define CC_WCSS_UMAC_WSI_CMD_RCGR__ROOT_OFF___M 0x80000000 +#define CC_WCSS_UMAC_WSI_CMD_RCGR__ROOT_OFF___S 31 +#define CC_WCSS_UMAC_WSI_CMD_RCGR__DIRTY_CFG_RCGR___M 0x00000010 +#define CC_WCSS_UMAC_WSI_CMD_RCGR__DIRTY_CFG_RCGR___S 4 +#define CC_WCSS_UMAC_WSI_CMD_RCGR__ROOT_EN___M 0x00000002 +#define CC_WCSS_UMAC_WSI_CMD_RCGR__ROOT_EN___S 1 +#define CC_WCSS_UMAC_WSI_CMD_RCGR__ROOT_EN__DISABLE 0x0 +#define CC_WCSS_UMAC_WSI_CMD_RCGR__ROOT_EN__ENABLE 0x1 +#define CC_WCSS_UMAC_WSI_CMD_RCGR__UPDATE___M 0x00000001 +#define CC_WCSS_UMAC_WSI_CMD_RCGR__UPDATE___S 0 +#define CC_WCSS_UMAC_WSI_CMD_RCGR__UPDATE__DISABLE 0x0 +#define CC_WCSS_UMAC_WSI_CMD_RCGR__UPDATE__ENABLE 0x1 +#define CC_WCSS_UMAC_WSI_CMD_RCGR___M 0x80000013 +#define CC_WCSS_UMAC_WSI_CMD_RCGR___S 0 + +#define CC_WCSS_UMAC_WSI_CFG_RCGR (0x00CB01E0) +#define CC_WCSS_UMAC_WSI_CFG_RCGR___RWC QCSR_REG_RW +#define CC_WCSS_UMAC_WSI_CFG_RCGR___POR 0x00100000 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__HW_CLK_CONTROL___POR 0x1 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__RCGLITE_DISABLE___POR 0x0 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_SEL___POR 0x0 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV___POR 0x00 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__HW_CLK_CONTROL___M 0x00100000 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__HW_CLK_CONTROL___S 20 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__HW_CLK_CONTROL__DISABLE 0x0 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__HW_CLK_CONTROL__ENABLE 0x1 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__RCGLITE_DISABLE___M 0x00010000 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__RCGLITE_DISABLE___S 16 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__RCGLITE_DISABLE__RCGLITE_ENABLED 0x0 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__RCGLITE_DISABLE__RCGLITE_DISABLED 0x1 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_SEL___M 0x00000700 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_SEL___S 8 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_SEL__SRC0 0x0 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_SEL__SRC1 0x1 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_SEL__SRC2 0x2 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_SEL__SRC3 0x3 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_SEL__SRC4 0x4 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_SEL__SRC5 0x5 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_SEL__SRC6 0x6 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_SEL__SRC7 0x7 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV___M 0x0000001F +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV___S 0 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__BYPASS 0x00 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV1 0x01 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV1_5 0x02 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV2 0x03 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV2_5 0x04 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV3 0x05 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV3_5 0x06 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV4 0x07 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV4_5 0x08 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV5 0x09 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV5_5 0x0A +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV6 0x0B +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV6_5 0x0C +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV7 0x0D +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV7_5 0x0E +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV8 0x0F +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV8_5 0x10 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV9 0x11 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV9_5 0x12 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV10 0x13 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV10_5 0x14 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV11 0x15 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV11_5 0x16 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV12 0x17 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV12_5 0x18 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV13 0x19 +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV13_5 0x1A +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV14 0x1B +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV14_5 0x1C +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV15 0x1D +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV15_5 0x1E +#define CC_WCSS_UMAC_WSI_CFG_RCGR__SRC_DIV__DIV16 0x1F +#define CC_WCSS_UMAC_WSI_CFG_RCGR___M 0x0011071F +#define CC_WCSS_UMAC_WSI_CFG_RCGR___S 0 + +#define CC_WCSS_UMAC_WSI_CBCR (0x00CB01F4) +#define CC_WCSS_UMAC_WSI_CBCR___RWC QCSR_REG_RW +#define CC_WCSS_UMAC_WSI_CBCR___POR 0x80000000 +#define CC_WCSS_UMAC_WSI_CBCR__CLK_OFF___POR 0x1 +#define CC_WCSS_UMAC_WSI_CBCR__CLK_ARES___POR 0x0 +#define CC_WCSS_UMAC_WSI_CBCR__CLK_ENABLE___POR 0x0 +#define CC_WCSS_UMAC_WSI_CBCR__CLK_OFF___M 0x80000000 +#define CC_WCSS_UMAC_WSI_CBCR__CLK_OFF___S 31 +#define CC_WCSS_UMAC_WSI_CBCR__CLK_ARES___M 0x00000004 +#define CC_WCSS_UMAC_WSI_CBCR__CLK_ARES___S 2 +#define CC_WCSS_UMAC_WSI_CBCR__CLK_ARES__NO_RESET 0x0 +#define CC_WCSS_UMAC_WSI_CBCR__CLK_ARES__RESET 0x1 +#define CC_WCSS_UMAC_WSI_CBCR__CLK_ENABLE___M 0x00000001 +#define CC_WCSS_UMAC_WSI_CBCR__CLK_ENABLE___S 0 +#define CC_WCSS_UMAC_WSI_CBCR__CLK_ENABLE__DISABLE 0x0 +#define CC_WCSS_UMAC_WSI_CBCR__CLK_ENABLE__ENABLE 0x1 +#define CC_WCSS_UMAC_WSI_CBCR___M 0x80000005 +#define CC_WCSS_UMAC_WSI_CBCR___S 0 + +#define CC_WCSS_NOC_TIME_CDIVR (0x00CB01F8) +#define CC_WCSS_NOC_TIME_CDIVR___RWC QCSR_REG_RW +#define CC_WCSS_NOC_TIME_CDIVR___POR 0x00000000 +#define CC_WCSS_NOC_TIME_CDIVR__CLK_DIV___POR 0x0 +#define CC_WCSS_NOC_TIME_CDIVR__CLK_DIV___M 0x0000000F +#define CC_WCSS_NOC_TIME_CDIVR__CLK_DIV___S 0 +#define CC_WCSS_NOC_TIME_CDIVR___M 0x0000000F +#define CC_WCSS_NOC_TIME_CDIVR___S 0 + +#define CC_WCSS_DEBUG_CLK (0x00CB1000) +#define CC_WCSS_DEBUG_CLK___RWC QCSR_REG_RW +#define CC_WCSS_DEBUG_CLK___POR 0x00000000 +#define CC_WCSS_DEBUG_CLK__DEBUG_CLK_DIV___POR 0x0 +#define CC_WCSS_DEBUG_CLK__DEBUG_BUS_MUX_SEL___POR 0x000 +#define CC_WCSS_DEBUG_CLK__DEBUG_CLK_DIV___M 0x00007800 +#define CC_WCSS_DEBUG_CLK__DEBUG_CLK_DIV___S 11 +#define CC_WCSS_DEBUG_CLK__DEBUG_BUS_MUX_SEL___M 0x000007FF +#define CC_WCSS_DEBUG_CLK__DEBUG_BUS_MUX_SEL___S 0 +#define CC_WCSS_DEBUG_CLK___M 0x00007FFF +#define CC_WCSS_DEBUG_CLK___S 0 + +#define CC_WCSS_SPARE_CFG (0x00CB1004) +#define CC_WCSS_SPARE_CFG___RWC QCSR_REG_RW +#define CC_WCSS_SPARE_CFG___POR 0x00000000 +#define CC_WCSS_SPARE_CFG__MISC___POR 0x00000000 +#define CC_WCSS_SPARE_CFG__MISC___M 0xFFFFFFFF +#define CC_WCSS_SPARE_CFG__MISC___S 0 +#define CC_WCSS_SPARE_CFG___M 0xFFFFFFFF +#define CC_WCSS_SPARE_CFG___S 0 + +#define CC_WCSS_MISC_WLAN1_GDSC_DEBUG_ARES_OVERRIDE (0x00CB1020) +#define CC_WCSS_MISC_WLAN1_GDSC_DEBUG_ARES_OVERRIDE___RWC QCSR_REG_RW +#define CC_WCSS_MISC_WLAN1_GDSC_DEBUG_ARES_OVERRIDE___POR 0x00000000 +#define CC_WCSS_MISC_WLAN1_GDSC_DEBUG_ARES_OVERRIDE__FORCE_ZERO___POR 0x0 +#define CC_WCSS_MISC_WLAN1_GDSC_DEBUG_ARES_OVERRIDE__FORCE_ZERO___M 0x00000001 +#define CC_WCSS_MISC_WLAN1_GDSC_DEBUG_ARES_OVERRIDE__FORCE_ZERO___S 0 +#define CC_WCSS_MISC_WLAN1_GDSC_DEBUG_ARES_OVERRIDE___M 0x00000001 +#define CC_WCSS_MISC_WLAN1_GDSC_DEBUG_ARES_OVERRIDE___S 0 + +#define CC_WCSS_MISC_POWER_SAVE_CTL (0x00CB1030) +#define CC_WCSS_MISC_POWER_SAVE_CTL___RWC QCSR_REG_RW +#define CC_WCSS_MISC_POWER_SAVE_CTL___POR 0x008000AE +#define CC_WCSS_MISC_POWER_SAVE_CTL__AHB_CLK_POWER_SAVE_WAIT___POR 0x0080 +#define CC_WCSS_MISC_POWER_SAVE_CTL__AHB_CLK_POWR_SAVE_MODE_ON___POR 0x0 +#define CC_WCSS_MISC_POWER_SAVE_CTL__UMAC_DEBUG_CLK_POWER_SAVE_MODE_EN___POR 0x1 +#define CC_WCSS_MISC_POWER_SAVE_CTL__PHYA_DEBUG_CLK_POWER_SAVE_MODE_EN___POR 0x1 +#define CC_WCSS_MISC_POWER_SAVE_CTL__AHB_CLK_POWER_SAVE_MAX_COUNT___POR 0x7 +#define CC_WCSS_MISC_POWER_SAVE_CTL__AHB_CLK_POWER_SAVE_MODE_EN___POR 0x0 +#define CC_WCSS_MISC_POWER_SAVE_CTL__AHB_CLK_POWER_SAVE_WAIT___M 0xFFFF0000 +#define CC_WCSS_MISC_POWER_SAVE_CTL__AHB_CLK_POWER_SAVE_WAIT___S 16 +#define CC_WCSS_MISC_POWER_SAVE_CTL__AHB_CLK_POWR_SAVE_MODE_ON___M 0x00000100 +#define CC_WCSS_MISC_POWER_SAVE_CTL__AHB_CLK_POWR_SAVE_MODE_ON___S 8 +#define CC_WCSS_MISC_POWER_SAVE_CTL__UMAC_DEBUG_CLK_POWER_SAVE_MODE_EN___M 0x00000080 +#define CC_WCSS_MISC_POWER_SAVE_CTL__UMAC_DEBUG_CLK_POWER_SAVE_MODE_EN___S 7 +#define CC_WCSS_MISC_POWER_SAVE_CTL__PHYA_DEBUG_CLK_POWER_SAVE_MODE_EN___M 0x00000020 +#define CC_WCSS_MISC_POWER_SAVE_CTL__PHYA_DEBUG_CLK_POWER_SAVE_MODE_EN___S 5 +#define CC_WCSS_MISC_POWER_SAVE_CTL__AHB_CLK_POWER_SAVE_MAX_COUNT___M 0x0000001E +#define CC_WCSS_MISC_POWER_SAVE_CTL__AHB_CLK_POWER_SAVE_MAX_COUNT___S 1 +#define CC_WCSS_MISC_POWER_SAVE_CTL__AHB_CLK_POWER_SAVE_MODE_EN___M 0x00000001 +#define CC_WCSS_MISC_POWER_SAVE_CTL__AHB_CLK_POWER_SAVE_MODE_EN___S 0 +#define CC_WCSS_MISC_POWER_SAVE_CTL___M 0xFFFF01BF +#define CC_WCSS_MISC_POWER_SAVE_CTL___S 0 + +#define CC_WCSS_MISC_POWER_SAVE_CTL_2 (0x00CB1034) +#define CC_WCSS_MISC_POWER_SAVE_CTL_2___RWC QCSR_REG_RW +#define CC_WCSS_MISC_POWER_SAVE_CTL_2___POR 0x00000404 +#define CC_WCSS_MISC_POWER_SAVE_CTL_2__PHY_AHB_CLK_IDLE_TO_OFF_WAIT___POR 0x04 +#define CC_WCSS_MISC_POWER_SAVE_CTL_2__MAC_AHB_CLK_IDLE_TO_OFF_WAIT___POR 0x04 +#define CC_WCSS_MISC_POWER_SAVE_CTL_2__PHY_AHB_CLK_IDLE_TO_OFF_WAIT___M 0x0000FF00 +#define CC_WCSS_MISC_POWER_SAVE_CTL_2__PHY_AHB_CLK_IDLE_TO_OFF_WAIT___S 8 +#define CC_WCSS_MISC_POWER_SAVE_CTL_2__MAC_AHB_CLK_IDLE_TO_OFF_WAIT___M 0x000000FF +#define CC_WCSS_MISC_POWER_SAVE_CTL_2__MAC_AHB_CLK_IDLE_TO_OFF_WAIT___S 0 +#define CC_WCSS_MISC_POWER_SAVE_CTL_2___M 0x0000FFFF +#define CC_WCSS_MISC_POWER_SAVE_CTL_2___S 0 + +#define CC_WCSS_MISC_DEBUG_ALT_LPO_CLK_CTL (0x00CB1044) +#define CC_WCSS_MISC_DEBUG_ALT_LPO_CLK_CTL___RWC QCSR_REG_RW +#define CC_WCSS_MISC_DEBUG_ALT_LPO_CLK_CTL___POR 0x00000000 +#define CC_WCSS_MISC_DEBUG_ALT_LPO_CLK_CTL__ENABLE___POR 0x0 +#define CC_WCSS_MISC_DEBUG_ALT_LPO_CLK_CTL__ENABLE___M 0x00000001 +#define CC_WCSS_MISC_DEBUG_ALT_LPO_CLK_CTL__ENABLE___S 0 +#define CC_WCSS_MISC_DEBUG_ALT_LPO_CLK_CTL___M 0x00000001 +#define CC_WCSS_MISC_DEBUG_ALT_LPO_CLK_CTL___S 0 + +#define CC_WCSS_UMAC_MEM_INI_CLKGATE_DIS_CTL (0x00CB1048) +#define CC_WCSS_UMAC_MEM_INI_CLKGATE_DIS_CTL___RWC QCSR_REG_RW +#define CC_WCSS_UMAC_MEM_INI_CLKGATE_DIS_CTL___POR 0x00000001 +#define CC_WCSS_UMAC_MEM_INI_CLKGATE_DIS_CTL__ENABLE___POR 0x1 +#define CC_WCSS_UMAC_MEM_INI_CLKGATE_DIS_CTL__ENABLE___M 0x00000001 +#define CC_WCSS_UMAC_MEM_INI_CLKGATE_DIS_CTL__ENABLE___S 0 +#define CC_WCSS_UMAC_MEM_INI_CLKGATE_DIS_CTL___M 0x00000001 +#define CC_WCSS_UMAC_MEM_INI_CLKGATE_DIS_CTL___S 0 + +#define CC_WCSS_PHYA_ROBE_CLK_GFMUX_SEL (0x00CB104C) +#define CC_WCSS_PHYA_ROBE_CLK_GFMUX_SEL___RWC QCSR_REG_RW +#define CC_WCSS_PHYA_ROBE_CLK_GFMUX_SEL___POR 0x00000000 +#define CC_WCSS_PHYA_ROBE_CLK_GFMUX_SEL__SRC_SEL___POR 0x0 +#define CC_WCSS_PHYA_ROBE_CLK_GFMUX_SEL__SRC_SEL___M 0x00000001 +#define CC_WCSS_PHYA_ROBE_CLK_GFMUX_SEL__SRC_SEL___S 0 +#define CC_WCSS_PHYA_ROBE_CLK_GFMUX_SEL__SRC_SEL__CLK_SRC_PHYA_DIGCLK480M 0x0 +#define CC_WCSS_PHYA_ROBE_CLK_GFMUX_SEL__SRC_SEL__CLK_SRR_PLL_MAIN_320M 0x1 +#define CC_WCSS_PHYA_ROBE_CLK_GFMUX_SEL___M 0x00000001 +#define CC_WCSS_PHYA_ROBE_CLK_GFMUX_SEL___S 0 + +#define CC_WCSS_UMAC_NOC_ATB_CLK_GFMUX_SEL (0x00CB1050) +#define CC_WCSS_UMAC_NOC_ATB_CLK_GFMUX_SEL___RWC QCSR_REG_RW +#define CC_WCSS_UMAC_NOC_ATB_CLK_GFMUX_SEL___POR 0x00000000 +#define CC_WCSS_UMAC_NOC_ATB_CLK_GFMUX_SEL__SRC_SEL___POR 0x0 +#define CC_WCSS_UMAC_NOC_ATB_CLK_GFMUX_SEL__SRC_SEL___M 0x00000001 +#define CC_WCSS_UMAC_NOC_ATB_CLK_GFMUX_SEL__SRC_SEL___S 0 +#define CC_WCSS_UMAC_NOC_ATB_CLK_GFMUX_SEL__SRC_SEL__CLK_SRC_NOM_240 0x0 +#define CC_WCSS_UMAC_NOC_ATB_CLK_GFMUX_SEL__SRC_SEL__CLK_SRR_SVS_160 0x1 +#define CC_WCSS_UMAC_NOC_ATB_CLK_GFMUX_SEL___M 0x00000001 +#define CC_WCSS_UMAC_NOC_ATB_CLK_GFMUX_SEL___S 0 + +#define CC_WCSS_CC_DBG_CLK_GATE_CTL (0x00CB106C) +#define CC_WCSS_CC_DBG_CLK_GATE_CTL___RWC QCSR_REG_RW +#define CC_WCSS_CC_DBG_CLK_GATE_CTL___POR 0x00000000 +#define CC_WCSS_CC_DBG_CLK_GATE_CTL__CLK_GATE_DIS___POR 0x00000000 +#define CC_WCSS_CC_DBG_CLK_GATE_CTL__CLK_GATE_DIS___M 0xFFFFFFFF +#define CC_WCSS_CC_DBG_CLK_GATE_CTL__CLK_GATE_DIS___S 0 +#define CC_WCSS_CC_DBG_CLK_GATE_CTL___M 0xFFFFFFFF +#define CC_WCSS_CC_DBG_CLK_GATE_CTL___S 0 + +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR (0x00CB1070) +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR___RWC QCSR_REG_RW +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR___POR 0x00000700 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__CLK_FREQ_TURBO_EXT_DLY___POR 0x07 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__FORCE_CLK_FREQ_HIGH___POR 0x0 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__FORCE_CLK_FREQ_LOW___POR 0x0 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__DBG_CLK_REQ_TURBO_EN___POR 0x0 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__MAC_CLK_REQ_TURBO_EN___POR 0x0 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__DBG_CLK_REQ_EN___POR 0x0 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__MAC_CLK_REQ_EN___POR 0x0 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__DCD_EN___POR 0x0 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__CLK_FREQ_TURBO_EXT_DLY___M 0x0000FF00 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__CLK_FREQ_TURBO_EXT_DLY___S 8 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__FORCE_CLK_FREQ_HIGH___M 0x00000040 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__FORCE_CLK_FREQ_HIGH___S 6 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__FORCE_CLK_FREQ_HIGH__NO_FORCE 0x0 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__FORCE_CLK_FREQ_HIGH__FORCE_HIGH_FREQ 0x1 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__FORCE_CLK_FREQ_LOW___M 0x00000020 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__FORCE_CLK_FREQ_LOW___S 5 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__FORCE_CLK_FREQ_LOW__NO_FORCE 0x0 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__FORCE_CLK_FREQ_LOW__FORCE_LOW_FREQ 0x1 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__DBG_CLK_REQ_TURBO_EN___M 0x00000010 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__DBG_CLK_REQ_TURBO_EN___S 4 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__DBG_CLK_REQ_TURBO_EN__DISABLE 0x0 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__DBG_CLK_REQ_TURBO_EN__ENABLE 0x1 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__MAC_CLK_REQ_TURBO_EN___M 0x00000008 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__MAC_CLK_REQ_TURBO_EN___S 3 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__MAC_CLK_REQ_TURBO_EN__DISABLE 0x0 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__MAC_CLK_REQ_TURBO_EN__ENABLE 0x1 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__DBG_CLK_REQ_EN___M 0x00000004 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__DBG_CLK_REQ_EN___S 2 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__DBG_CLK_REQ_EN__DISABLE 0x0 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__DBG_CLK_REQ_EN__ENABLE 0x1 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__MAC_CLK_REQ_EN___M 0x00000002 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__MAC_CLK_REQ_EN___S 1 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__MAC_CLK_REQ_EN__DISABLE 0x0 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__MAC_CLK_REQ_EN__ENABLE 0x1 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__DCD_EN___M 0x00000001 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__DCD_EN___S 0 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__DCD_EN__DISABLE 0x0 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR__DCD_EN__ENABLE 0x1 +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR___M 0x0000FF7F +#define CC_WCSS_CC_DBG_ATB_CFG1_DCDR___S 0 + +#define CC_WCSS_CC_DBG_ATB_CFG2_DCDR (0x00CB1074) +#define CC_WCSS_CC_DBG_ATB_CFG2_DCDR___RWC QCSR_REG_RW +#define CC_WCSS_CC_DBG_ATB_CFG2_DCDR___POR 0x0050031F +#define CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_HIGH_EXT_DLY___POR 0x0050 +#define CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_HIGH_DIV___POR 0x03 +#define CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_LOW_DIV___POR 0x1F +#define CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_HIGH_EXT_DLY___M 0xFFFF0000 +#define CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_HIGH_EXT_DLY___S 16 +#define CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_HIGH_DIV___M 0x0000FF00 +#define CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_HIGH_DIV___S 8 +#define CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_HIGH_DIV__DIV1 0x00 +#define CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_HIGH_DIV__DIV2 0x01 +#define CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_HIGH_DIV__DIV8 0x07 +#define CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_HIGH_DIV__DIV16 0x0F +#define CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_HIGH_DIV__DIV32 0x1F +#define CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_HIGH_DIV__DIV128 0x7F +#define CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_HIGH_DIV__DIV256 0xFF +#define CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_LOW_DIV___M 0x000000FF +#define CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_LOW_DIV___S 0 +#define CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_LOW_DIV__DIV1 0x00 +#define CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_LOW_DIV__DIV2 0x01 +#define CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_LOW_DIV__DIV8 0x07 +#define CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_LOW_DIV__DIV16 0x0F +#define CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_LOW_DIV__DIV32 0x1F +#define CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_LOW_DIV__DIV128 0x7F +#define CC_WCSS_CC_DBG_ATB_CFG2_DCDR__CLK_FREQ_LOW_DIV__DIV256 0xFF +#define CC_WCSS_CC_DBG_ATB_CFG2_DCDR___M 0xFFFFFFFF +#define CC_WCSS_CC_DBG_ATB_CFG2_DCDR___S 0 + +#define CC_WCSS_CC_UMAC_NOC_CLK_DCGR (0x00CB1078) +#define CC_WCSS_CC_UMAC_NOC_CLK_DCGR___RWC QCSR_REG_RW +#define CC_WCSS_CC_UMAC_NOC_CLK_DCGR___POR 0x00000700 +#define CC_WCSS_CC_UMAC_NOC_CLK_DCGR__DCG_EXT_DLY___POR 0x07 +#define CC_WCSS_CC_UMAC_NOC_CLK_DCGR__DCG_EN___POR 0x0 +#define CC_WCSS_CC_UMAC_NOC_CLK_DCGR__DCG_EXT_DLY___M 0x0000FF00 +#define CC_WCSS_CC_UMAC_NOC_CLK_DCGR__DCG_EXT_DLY___S 8 +#define CC_WCSS_CC_UMAC_NOC_CLK_DCGR__DCG_EN___M 0x00000001 +#define CC_WCSS_CC_UMAC_NOC_CLK_DCGR__DCG_EN___S 0 +#define CC_WCSS_CC_UMAC_NOC_CLK_DCGR__DCG_EN__DISABLE 0x0 +#define CC_WCSS_CC_UMAC_NOC_CLK_DCGR__DCG_EN__ENABLE 0x1 +#define CC_WCSS_CC_UMAC_NOC_CLK_DCGR___M 0x0000FF01 +#define CC_WCSS_CC_UMAC_NOC_CLK_DCGR___S 0 + +#define CC_WCSS_CC_UMAC_NOC_CLK_DCDR (0x00CB107C) +#define CC_WCSS_CC_UMAC_NOC_CLK_DCDR___RWC QCSR_REG_RW +#define CC_WCSS_CC_UMAC_NOC_CLK_DCDR___POR 0x00000300 +#define CC_WCSS_CC_UMAC_NOC_CLK_DCDR__LOW_FREQ_MAX_COUNT___POR 0x3 +#define CC_WCSS_CC_UMAC_NOC_CLK_DCDR__DCD_EN___POR 0x0 +#define CC_WCSS_CC_UMAC_NOC_CLK_DCDR__LOW_FREQ_MAX_COUNT___M 0x00000F00 +#define CC_WCSS_CC_UMAC_NOC_CLK_DCDR__LOW_FREQ_MAX_COUNT___S 8 +#define CC_WCSS_CC_UMAC_NOC_CLK_DCDR__DCD_EN___M 0x00000001 +#define CC_WCSS_CC_UMAC_NOC_CLK_DCDR__DCD_EN___S 0 +#define CC_WCSS_CC_UMAC_NOC_CLK_DCDR__DCD_EN__DISABLE 0x0 +#define CC_WCSS_CC_UMAC_NOC_CLK_DCDR__DCD_EN__ENABLE 0x1 +#define CC_WCSS_CC_UMAC_NOC_CLK_DCDR___M 0x00000F01 +#define CC_WCSS_CC_UMAC_NOC_CLK_DCDR___S 0 + +#define CC_WCSS_CC_MAC0_MAC_CLK_DCGR (0x00CB1080) +#define CC_WCSS_CC_MAC0_MAC_CLK_DCGR___RWC QCSR_REG_RW +#define CC_WCSS_CC_MAC0_MAC_CLK_DCGR___POR 0x00000700 +#define CC_WCSS_CC_MAC0_MAC_CLK_DCGR__DCG_EXT_DLY___POR 0x07 +#define CC_WCSS_CC_MAC0_MAC_CLK_DCGR__DCG_EN___POR 0x0 +#define CC_WCSS_CC_MAC0_MAC_CLK_DCGR__DCG_EXT_DLY___M 0x0000FF00 +#define CC_WCSS_CC_MAC0_MAC_CLK_DCGR__DCG_EXT_DLY___S 8 +#define CC_WCSS_CC_MAC0_MAC_CLK_DCGR__DCG_EN___M 0x00000001 +#define CC_WCSS_CC_MAC0_MAC_CLK_DCGR__DCG_EN___S 0 +#define CC_WCSS_CC_MAC0_MAC_CLK_DCGR__DCG_EN__DISABLE 0x0 +#define CC_WCSS_CC_MAC0_MAC_CLK_DCGR__DCG_EN__ENABLE 0x1 +#define CC_WCSS_CC_MAC0_MAC_CLK_DCGR___M 0x0000FF01 +#define CC_WCSS_CC_MAC0_MAC_CLK_DCGR___S 0 + +#define CC_WCSS_CC_MAC0_MAC_CLK_DCDR (0x00CB1084) +#define CC_WCSS_CC_MAC0_MAC_CLK_DCDR___RWC QCSR_REG_RW +#define CC_WCSS_CC_MAC0_MAC_CLK_DCDR___POR 0x00000300 +#define CC_WCSS_CC_MAC0_MAC_CLK_DCDR__LOW_FREQ_MAX_COUNT___POR 0x3 +#define CC_WCSS_CC_MAC0_MAC_CLK_DCDR__DCD_EN___POR 0x0 +#define CC_WCSS_CC_MAC0_MAC_CLK_DCDR__LOW_FREQ_MAX_COUNT___M 0x00000F00 +#define CC_WCSS_CC_MAC0_MAC_CLK_DCDR__LOW_FREQ_MAX_COUNT___S 8 +#define CC_WCSS_CC_MAC0_MAC_CLK_DCDR__DCD_EN___M 0x00000001 +#define CC_WCSS_CC_MAC0_MAC_CLK_DCDR__DCD_EN___S 0 +#define CC_WCSS_CC_MAC0_MAC_CLK_DCDR__DCD_EN__DISABLE 0x0 +#define CC_WCSS_CC_MAC0_MAC_CLK_DCDR__DCD_EN__ENABLE 0x1 +#define CC_WCSS_CC_MAC0_MAC_CLK_DCDR___M 0x00000F01 +#define CC_WCSS_CC_MAC0_MAC_CLK_DCDR___S 0 + +#define CC_QDSS_STM_EVENT0_CTL_REG (0x00CB2000) +#define CC_QDSS_STM_EVENT0_CTL_REG___RWC QCSR_REG_RW +#define CC_QDSS_STM_EVENT0_CTL_REG___POR 0x00000000 +#define CC_QDSS_STM_EVENT0_CTL_REG__EVENT_ENABLE___POR 0x0 +#define CC_QDSS_STM_EVENT0_CTL_REG__EVENT_MUX_SEL___POR 0x0 +#define CC_QDSS_STM_EVENT0_CTL_REG__EVENT_ENABLE___M 0x80000000 +#define CC_QDSS_STM_EVENT0_CTL_REG__EVENT_ENABLE___S 31 +#define CC_QDSS_STM_EVENT0_CTL_REG__EVENT_ENABLE__DISABLE 0x0 +#define CC_QDSS_STM_EVENT0_CTL_REG__EVENT_ENABLE__ENABLE 0x1 +#define CC_QDSS_STM_EVENT0_CTL_REG__EVENT_MUX_SEL___M 0x00000007 +#define CC_QDSS_STM_EVENT0_CTL_REG__EVENT_MUX_SEL___S 0 +#define CC_QDSS_STM_EVENT0_CTL_REG___M 0x80000007 +#define CC_QDSS_STM_EVENT0_CTL_REG___S 0 + +#define CC_QDSS_STM_EVENT1_CTL_REG (0x00CB2004) +#define CC_QDSS_STM_EVENT1_CTL_REG___RWC QCSR_REG_RW +#define CC_QDSS_STM_EVENT1_CTL_REG___POR 0x00000000 +#define CC_QDSS_STM_EVENT1_CTL_REG__EVENT_ENABLE___POR 0x0 +#define CC_QDSS_STM_EVENT1_CTL_REG__EVENT_MUX_SEL___POR 0x0 +#define CC_QDSS_STM_EVENT1_CTL_REG__EVENT_ENABLE___M 0x80000000 +#define CC_QDSS_STM_EVENT1_CTL_REG__EVENT_ENABLE___S 31 +#define CC_QDSS_STM_EVENT1_CTL_REG__EVENT_ENABLE__DISABLE 0x0 +#define CC_QDSS_STM_EVENT1_CTL_REG__EVENT_ENABLE__ENABLE 0x1 +#define CC_QDSS_STM_EVENT1_CTL_REG__EVENT_MUX_SEL___M 0x00000007 +#define CC_QDSS_STM_EVENT1_CTL_REG__EVENT_MUX_SEL___S 0 +#define CC_QDSS_STM_EVENT1_CTL_REG___M 0x80000007 +#define CC_QDSS_STM_EVENT1_CTL_REG___S 0 + +#define CC_QDSS_STM_EVENT2_CTL_REG (0x00CB2008) +#define CC_QDSS_STM_EVENT2_CTL_REG___RWC QCSR_REG_RW +#define CC_QDSS_STM_EVENT2_CTL_REG___POR 0x00000000 +#define CC_QDSS_STM_EVENT2_CTL_REG__EVENT_ENABLE___POR 0x0 +#define CC_QDSS_STM_EVENT2_CTL_REG__EVENT_MUX_SEL___POR 0x0 +#define CC_QDSS_STM_EVENT2_CTL_REG__EVENT_ENABLE___M 0x80000000 +#define CC_QDSS_STM_EVENT2_CTL_REG__EVENT_ENABLE___S 31 +#define CC_QDSS_STM_EVENT2_CTL_REG__EVENT_ENABLE__DISABLE 0x0 +#define CC_QDSS_STM_EVENT2_CTL_REG__EVENT_ENABLE__ENABLE 0x1 +#define CC_QDSS_STM_EVENT2_CTL_REG__EVENT_MUX_SEL___M 0x00000007 +#define CC_QDSS_STM_EVENT2_CTL_REG__EVENT_MUX_SEL___S 0 +#define CC_QDSS_STM_EVENT2_CTL_REG___M 0x80000007 +#define CC_QDSS_STM_EVENT2_CTL_REG___S 0 + +#define CC_QDSS_STM_EVENT3_CTL_REG (0x00CB200C) +#define CC_QDSS_STM_EVENT3_CTL_REG___RWC QCSR_REG_RW +#define CC_QDSS_STM_EVENT3_CTL_REG___POR 0x00000000 +#define CC_QDSS_STM_EVENT3_CTL_REG__EVENT_ENABLE___POR 0x0 +#define CC_QDSS_STM_EVENT3_CTL_REG__EVENT_MUX_SEL___POR 0x0 +#define CC_QDSS_STM_EVENT3_CTL_REG__EVENT_ENABLE___M 0x80000000 +#define CC_QDSS_STM_EVENT3_CTL_REG__EVENT_ENABLE___S 31 +#define CC_QDSS_STM_EVENT3_CTL_REG__EVENT_ENABLE__DISABLE 0x0 +#define CC_QDSS_STM_EVENT3_CTL_REG__EVENT_ENABLE__ENABLE 0x1 +#define CC_QDSS_STM_EVENT3_CTL_REG__EVENT_MUX_SEL___M 0x00000007 +#define CC_QDSS_STM_EVENT3_CTL_REG__EVENT_MUX_SEL___S 0 +#define CC_QDSS_STM_EVENT3_CTL_REG___M 0x80000007 +#define CC_QDSS_STM_EVENT3_CTL_REG___S 0 + +#define CC_QDSS_STM_EVENT4_CTL_REG (0x00CB2010) +#define CC_QDSS_STM_EVENT4_CTL_REG___RWC QCSR_REG_RW +#define CC_QDSS_STM_EVENT4_CTL_REG___POR 0x00000000 +#define CC_QDSS_STM_EVENT4_CTL_REG__EVENT_ENABLE___POR 0x0 +#define CC_QDSS_STM_EVENT4_CTL_REG__EVENT_MUX_SEL___POR 0x0 +#define CC_QDSS_STM_EVENT4_CTL_REG__EVENT_ENABLE___M 0x80000000 +#define CC_QDSS_STM_EVENT4_CTL_REG__EVENT_ENABLE___S 31 +#define CC_QDSS_STM_EVENT4_CTL_REG__EVENT_ENABLE__DISABLE 0x0 +#define CC_QDSS_STM_EVENT4_CTL_REG__EVENT_ENABLE__ENABLE 0x1 +#define CC_QDSS_STM_EVENT4_CTL_REG__EVENT_MUX_SEL___M 0x00000007 +#define CC_QDSS_STM_EVENT4_CTL_REG__EVENT_MUX_SEL___S 0 +#define CC_QDSS_STM_EVENT4_CTL_REG___M 0x80000007 +#define CC_QDSS_STM_EVENT4_CTL_REG___S 0 + +#define CC_QDSS_STM_EVENT5_CTL_REG (0x00CB2014) +#define CC_QDSS_STM_EVENT5_CTL_REG___RWC QCSR_REG_RW +#define CC_QDSS_STM_EVENT5_CTL_REG___POR 0x00000000 +#define CC_QDSS_STM_EVENT5_CTL_REG__EVENT_ENABLE___POR 0x0 +#define CC_QDSS_STM_EVENT5_CTL_REG__EVENT_MUX_SEL___POR 0x0 +#define CC_QDSS_STM_EVENT5_CTL_REG__EVENT_ENABLE___M 0x80000000 +#define CC_QDSS_STM_EVENT5_CTL_REG__EVENT_ENABLE___S 31 +#define CC_QDSS_STM_EVENT5_CTL_REG__EVENT_ENABLE__DISABLE 0x0 +#define CC_QDSS_STM_EVENT5_CTL_REG__EVENT_ENABLE__ENABLE 0x1 +#define CC_QDSS_STM_EVENT5_CTL_REG__EVENT_MUX_SEL___M 0x00000007 +#define CC_QDSS_STM_EVENT5_CTL_REG__EVENT_MUX_SEL___S 0 +#define CC_QDSS_STM_EVENT5_CTL_REG___M 0x80000007 +#define CC_QDSS_STM_EVENT5_CTL_REG___S 0 + +#define CC_QDSS_STM_EVENT6_CTL_REG (0x00CB2018) +#define CC_QDSS_STM_EVENT6_CTL_REG___RWC QCSR_REG_RW +#define CC_QDSS_STM_EVENT6_CTL_REG___POR 0x00000000 +#define CC_QDSS_STM_EVENT6_CTL_REG__EVENT_ENABLE___POR 0x0 +#define CC_QDSS_STM_EVENT6_CTL_REG__EVENT_MUX_SEL___POR 0x0 +#define CC_QDSS_STM_EVENT6_CTL_REG__EVENT_ENABLE___M 0x80000000 +#define CC_QDSS_STM_EVENT6_CTL_REG__EVENT_ENABLE___S 31 +#define CC_QDSS_STM_EVENT6_CTL_REG__EVENT_ENABLE__DISABLE 0x0 +#define CC_QDSS_STM_EVENT6_CTL_REG__EVENT_ENABLE__ENABLE 0x1 +#define CC_QDSS_STM_EVENT6_CTL_REG__EVENT_MUX_SEL___M 0x00000007 +#define CC_QDSS_STM_EVENT6_CTL_REG__EVENT_MUX_SEL___S 0 +#define CC_QDSS_STM_EVENT6_CTL_REG___M 0x80000007 +#define CC_QDSS_STM_EVENT6_CTL_REG___S 0 + +#define CC_QDSS_STM_EVENT7_CTL_REG (0x00CB201C) +#define CC_QDSS_STM_EVENT7_CTL_REG___RWC QCSR_REG_RW +#define CC_QDSS_STM_EVENT7_CTL_REG___POR 0x00000000 +#define CC_QDSS_STM_EVENT7_CTL_REG__EVENT_ENABLE___POR 0x0 +#define CC_QDSS_STM_EVENT7_CTL_REG__EVENT_MUX_SEL___POR 0x0 +#define CC_QDSS_STM_EVENT7_CTL_REG__EVENT_ENABLE___M 0x80000000 +#define CC_QDSS_STM_EVENT7_CTL_REG__EVENT_ENABLE___S 31 +#define CC_QDSS_STM_EVENT7_CTL_REG__EVENT_ENABLE__DISABLE 0x0 +#define CC_QDSS_STM_EVENT7_CTL_REG__EVENT_ENABLE__ENABLE 0x1 +#define CC_QDSS_STM_EVENT7_CTL_REG__EVENT_MUX_SEL___M 0x00000007 +#define CC_QDSS_STM_EVENT7_CTL_REG__EVENT_MUX_SEL___S 0 +#define CC_QDSS_STM_EVENT7_CTL_REG___M 0x80000007 +#define CC_QDSS_STM_EVENT7_CTL_REG___S 0 + +#define CC_QDSS_STM_EVENT8_CTL_REG (0x00CB2020) +#define CC_QDSS_STM_EVENT8_CTL_REG___RWC QCSR_REG_RW +#define CC_QDSS_STM_EVENT8_CTL_REG___POR 0x00000000 +#define CC_QDSS_STM_EVENT8_CTL_REG__EVENT_ENABLE___POR 0x0 +#define CC_QDSS_STM_EVENT8_CTL_REG__EVENT_MUX_SEL___POR 0x0 +#define CC_QDSS_STM_EVENT8_CTL_REG__EVENT_ENABLE___M 0x80000000 +#define CC_QDSS_STM_EVENT8_CTL_REG__EVENT_ENABLE___S 31 +#define CC_QDSS_STM_EVENT8_CTL_REG__EVENT_ENABLE__DISABLE 0x0 +#define CC_QDSS_STM_EVENT8_CTL_REG__EVENT_ENABLE__ENABLE 0x1 +#define CC_QDSS_STM_EVENT8_CTL_REG__EVENT_MUX_SEL___M 0x00000007 +#define CC_QDSS_STM_EVENT8_CTL_REG__EVENT_MUX_SEL___S 0 +#define CC_QDSS_STM_EVENT8_CTL_REG___M 0x80000007 +#define CC_QDSS_STM_EVENT8_CTL_REG___S 0 + +#define CC_QDSS_STM_EVENT9_CTL_REG (0x00CB2024) +#define CC_QDSS_STM_EVENT9_CTL_REG___RWC QCSR_REG_RW +#define CC_QDSS_STM_EVENT9_CTL_REG___POR 0x00000000 +#define CC_QDSS_STM_EVENT9_CTL_REG__EVENT_ENABLE___POR 0x0 +#define CC_QDSS_STM_EVENT9_CTL_REG__EVENT_MUX_SEL___POR 0x0 +#define CC_QDSS_STM_EVENT9_CTL_REG__EVENT_ENABLE___M 0x80000000 +#define CC_QDSS_STM_EVENT9_CTL_REG__EVENT_ENABLE___S 31 +#define CC_QDSS_STM_EVENT9_CTL_REG__EVENT_ENABLE__DISABLE 0x0 +#define CC_QDSS_STM_EVENT9_CTL_REG__EVENT_ENABLE__ENABLE 0x1 +#define CC_QDSS_STM_EVENT9_CTL_REG__EVENT_MUX_SEL___M 0x00000007 +#define CC_QDSS_STM_EVENT9_CTL_REG__EVENT_MUX_SEL___S 0 +#define CC_QDSS_STM_EVENT9_CTL_REG___M 0x80000007 +#define CC_QDSS_STM_EVENT9_CTL_REG___S 0 + +#define CC_QDSS_STM_EVENT10_CTL_REG (0x00CB2028) +#define CC_QDSS_STM_EVENT10_CTL_REG___RWC QCSR_REG_RW +#define CC_QDSS_STM_EVENT10_CTL_REG___POR 0x00000000 +#define CC_QDSS_STM_EVENT10_CTL_REG__EVENT_ENABLE___POR 0x0 +#define CC_QDSS_STM_EVENT10_CTL_REG__EVENT_MUX_SEL___POR 0x0 +#define CC_QDSS_STM_EVENT10_CTL_REG__EVENT_ENABLE___M 0x80000000 +#define CC_QDSS_STM_EVENT10_CTL_REG__EVENT_ENABLE___S 31 +#define CC_QDSS_STM_EVENT10_CTL_REG__EVENT_ENABLE__DISABLE 0x0 +#define CC_QDSS_STM_EVENT10_CTL_REG__EVENT_ENABLE__ENABLE 0x1 +#define CC_QDSS_STM_EVENT10_CTL_REG__EVENT_MUX_SEL___M 0x00000007 +#define CC_QDSS_STM_EVENT10_CTL_REG__EVENT_MUX_SEL___S 0 +#define CC_QDSS_STM_EVENT10_CTL_REG___M 0x80000007 +#define CC_QDSS_STM_EVENT10_CTL_REG___S 0 + +#define CC_QDSS_STM_EVENT11_CTL_REG (0x00CB202C) +#define CC_QDSS_STM_EVENT11_CTL_REG___RWC QCSR_REG_RW +#define CC_QDSS_STM_EVENT11_CTL_REG___POR 0x00000000 +#define CC_QDSS_STM_EVENT11_CTL_REG__EVENT_ENABLE___POR 0x0 +#define CC_QDSS_STM_EVENT11_CTL_REG__EVENT_MUX_SEL___POR 0x0 +#define CC_QDSS_STM_EVENT11_CTL_REG__EVENT_ENABLE___M 0x80000000 +#define CC_QDSS_STM_EVENT11_CTL_REG__EVENT_ENABLE___S 31 +#define CC_QDSS_STM_EVENT11_CTL_REG__EVENT_ENABLE__DISABLE 0x0 +#define CC_QDSS_STM_EVENT11_CTL_REG__EVENT_ENABLE__ENABLE 0x1 +#define CC_QDSS_STM_EVENT11_CTL_REG__EVENT_MUX_SEL___M 0x00000007 +#define CC_QDSS_STM_EVENT11_CTL_REG__EVENT_MUX_SEL___S 0 +#define CC_QDSS_STM_EVENT11_CTL_REG___M 0x80000007 +#define CC_QDSS_STM_EVENT11_CTL_REG___S 0 + +#define CC_QDSS_STM_EVENT12_CTL_REG (0x00CB2030) +#define CC_QDSS_STM_EVENT12_CTL_REG___RWC QCSR_REG_RW +#define CC_QDSS_STM_EVENT12_CTL_REG___POR 0x00000000 +#define CC_QDSS_STM_EVENT12_CTL_REG__EVENT_ENABLE___POR 0x0 +#define CC_QDSS_STM_EVENT12_CTL_REG__EVENT_MUX_SEL___POR 0x0 +#define CC_QDSS_STM_EVENT12_CTL_REG__EVENT_ENABLE___M 0x80000000 +#define CC_QDSS_STM_EVENT12_CTL_REG__EVENT_ENABLE___S 31 +#define CC_QDSS_STM_EVENT12_CTL_REG__EVENT_ENABLE__DISABLE 0x0 +#define CC_QDSS_STM_EVENT12_CTL_REG__EVENT_ENABLE__ENABLE 0x1 +#define CC_QDSS_STM_EVENT12_CTL_REG__EVENT_MUX_SEL___M 0x00000007 +#define CC_QDSS_STM_EVENT12_CTL_REG__EVENT_MUX_SEL___S 0 +#define CC_QDSS_STM_EVENT12_CTL_REG___M 0x80000007 +#define CC_QDSS_STM_EVENT12_CTL_REG___S 0 + +#define CC_QDSS_STM_EVENT13_CTL_REG (0x00CB2034) +#define CC_QDSS_STM_EVENT13_CTL_REG___RWC QCSR_REG_RW +#define CC_QDSS_STM_EVENT13_CTL_REG___POR 0x00000000 +#define CC_QDSS_STM_EVENT13_CTL_REG__EVENT_ENABLE___POR 0x0 +#define CC_QDSS_STM_EVENT13_CTL_REG__EVENT_MUX_SEL___POR 0x0 +#define CC_QDSS_STM_EVENT13_CTL_REG__EVENT_ENABLE___M 0x80000000 +#define CC_QDSS_STM_EVENT13_CTL_REG__EVENT_ENABLE___S 31 +#define CC_QDSS_STM_EVENT13_CTL_REG__EVENT_ENABLE__DISABLE 0x0 +#define CC_QDSS_STM_EVENT13_CTL_REG__EVENT_ENABLE__ENABLE 0x1 +#define CC_QDSS_STM_EVENT13_CTL_REG__EVENT_MUX_SEL___M 0x00000007 +#define CC_QDSS_STM_EVENT13_CTL_REG__EVENT_MUX_SEL___S 0 +#define CC_QDSS_STM_EVENT13_CTL_REG___M 0x80000007 +#define CC_QDSS_STM_EVENT13_CTL_REG___S 0 + +#define CC_QDSS_STM_EVENT14_CTL_REG (0x00CB2038) +#define CC_QDSS_STM_EVENT14_CTL_REG___RWC QCSR_REG_RW +#define CC_QDSS_STM_EVENT14_CTL_REG___POR 0x00000000 +#define CC_QDSS_STM_EVENT14_CTL_REG__EVENT_ENABLE___POR 0x0 +#define CC_QDSS_STM_EVENT14_CTL_REG__EVENT_MUX_SEL___POR 0x0 +#define CC_QDSS_STM_EVENT14_CTL_REG__EVENT_ENABLE___M 0x80000000 +#define CC_QDSS_STM_EVENT14_CTL_REG__EVENT_ENABLE___S 31 +#define CC_QDSS_STM_EVENT14_CTL_REG__EVENT_ENABLE__DISABLE 0x0 +#define CC_QDSS_STM_EVENT14_CTL_REG__EVENT_ENABLE__ENABLE 0x1 +#define CC_QDSS_STM_EVENT14_CTL_REG__EVENT_MUX_SEL___M 0x00000007 +#define CC_QDSS_STM_EVENT14_CTL_REG__EVENT_MUX_SEL___S 0 +#define CC_QDSS_STM_EVENT14_CTL_REG___M 0x80000007 +#define CC_QDSS_STM_EVENT14_CTL_REG___S 0 + +#define CC_QDSS_STM_EVENT15_CTL_REG (0x00CB203C) +#define CC_QDSS_STM_EVENT15_CTL_REG___RWC QCSR_REG_RW +#define CC_QDSS_STM_EVENT15_CTL_REG___POR 0x00000000 +#define CC_QDSS_STM_EVENT15_CTL_REG__EVENT_ENABLE___POR 0x0 +#define CC_QDSS_STM_EVENT15_CTL_REG__EVENT_MUX_SEL___POR 0x0 +#define CC_QDSS_STM_EVENT15_CTL_REG__EVENT_ENABLE___M 0x80000000 +#define CC_QDSS_STM_EVENT15_CTL_REG__EVENT_ENABLE___S 31 +#define CC_QDSS_STM_EVENT15_CTL_REG__EVENT_ENABLE__DISABLE 0x0 +#define CC_QDSS_STM_EVENT15_CTL_REG__EVENT_ENABLE__ENABLE 0x1 +#define CC_QDSS_STM_EVENT15_CTL_REG__EVENT_MUX_SEL___M 0x00000007 +#define CC_QDSS_STM_EVENT15_CTL_REG__EVENT_MUX_SEL___S 0 +#define CC_QDSS_STM_EVENT15_CTL_REG___M 0x80000007 +#define CC_QDSS_STM_EVENT15_CTL_REG___S 0 + +#define CC_QDSS_STM_EVENT16_CTL_REG (0x00CB2040) +#define CC_QDSS_STM_EVENT16_CTL_REG___RWC QCSR_REG_RW +#define CC_QDSS_STM_EVENT16_CTL_REG___POR 0x00000000 +#define CC_QDSS_STM_EVENT16_CTL_REG__EVENT_ENABLE___POR 0x0 +#define CC_QDSS_STM_EVENT16_CTL_REG__EVENT_MUX_SEL___POR 0x0 +#define CC_QDSS_STM_EVENT16_CTL_REG__EVENT_ENABLE___M 0x80000000 +#define CC_QDSS_STM_EVENT16_CTL_REG__EVENT_ENABLE___S 31 +#define CC_QDSS_STM_EVENT16_CTL_REG__EVENT_ENABLE__DISABLE 0x0 +#define CC_QDSS_STM_EVENT16_CTL_REG__EVENT_ENABLE__ENABLE 0x1 +#define CC_QDSS_STM_EVENT16_CTL_REG__EVENT_MUX_SEL___M 0x00000007 +#define CC_QDSS_STM_EVENT16_CTL_REG__EVENT_MUX_SEL___S 0 +#define CC_QDSS_STM_EVENT16_CTL_REG___M 0x80000007 +#define CC_QDSS_STM_EVENT16_CTL_REG___S 0 + +#define CC_QDSS_STM_EVENT17_CTL_REG (0x00CB2044) +#define CC_QDSS_STM_EVENT17_CTL_REG___RWC QCSR_REG_RW +#define CC_QDSS_STM_EVENT17_CTL_REG___POR 0x00000000 +#define CC_QDSS_STM_EVENT17_CTL_REG__EVENT_ENABLE___POR 0x0 +#define CC_QDSS_STM_EVENT17_CTL_REG__EVENT_MUX_SEL___POR 0x0 +#define CC_QDSS_STM_EVENT17_CTL_REG__EVENT_ENABLE___M 0x80000000 +#define CC_QDSS_STM_EVENT17_CTL_REG__EVENT_ENABLE___S 31 +#define CC_QDSS_STM_EVENT17_CTL_REG__EVENT_ENABLE__DISABLE 0x0 +#define CC_QDSS_STM_EVENT17_CTL_REG__EVENT_ENABLE__ENABLE 0x1 +#define CC_QDSS_STM_EVENT17_CTL_REG__EVENT_MUX_SEL___M 0x00000007 +#define CC_QDSS_STM_EVENT17_CTL_REG__EVENT_MUX_SEL___S 0 +#define CC_QDSS_STM_EVENT17_CTL_REG___M 0x80000007 +#define CC_QDSS_STM_EVENT17_CTL_REG___S 0 + +#define CC_QDSS_STM_EVENT18_CTL_REG (0x00CB2048) +#define CC_QDSS_STM_EVENT18_CTL_REG___RWC QCSR_REG_RW +#define CC_QDSS_STM_EVENT18_CTL_REG___POR 0x00000000 +#define CC_QDSS_STM_EVENT18_CTL_REG__EVENT_ENABLE___POR 0x0 +#define CC_QDSS_STM_EVENT18_CTL_REG__EVENT_MUX_SEL___POR 0x0 +#define CC_QDSS_STM_EVENT18_CTL_REG__EVENT_ENABLE___M 0x80000000 +#define CC_QDSS_STM_EVENT18_CTL_REG__EVENT_ENABLE___S 31 +#define CC_QDSS_STM_EVENT18_CTL_REG__EVENT_ENABLE__DISABLE 0x0 +#define CC_QDSS_STM_EVENT18_CTL_REG__EVENT_ENABLE__ENABLE 0x1 +#define CC_QDSS_STM_EVENT18_CTL_REG__EVENT_MUX_SEL___M 0x00000007 +#define CC_QDSS_STM_EVENT18_CTL_REG__EVENT_MUX_SEL___S 0 +#define CC_QDSS_STM_EVENT18_CTL_REG___M 0x80000007 +#define CC_QDSS_STM_EVENT18_CTL_REG___S 0 + +#define CC_QDSS_STM_EVENT19_CTL_REG (0x00CB204C) +#define CC_QDSS_STM_EVENT19_CTL_REG___RWC QCSR_REG_RW +#define CC_QDSS_STM_EVENT19_CTL_REG___POR 0x00000000 +#define CC_QDSS_STM_EVENT19_CTL_REG__EVENT_ENABLE___POR 0x0 +#define CC_QDSS_STM_EVENT19_CTL_REG__EVENT_MUX_SEL___POR 0x0 +#define CC_QDSS_STM_EVENT19_CTL_REG__EVENT_ENABLE___M 0x80000000 +#define CC_QDSS_STM_EVENT19_CTL_REG__EVENT_ENABLE___S 31 +#define CC_QDSS_STM_EVENT19_CTL_REG__EVENT_ENABLE__DISABLE 0x0 +#define CC_QDSS_STM_EVENT19_CTL_REG__EVENT_ENABLE__ENABLE 0x1 +#define CC_QDSS_STM_EVENT19_CTL_REG__EVENT_MUX_SEL___M 0x00000007 +#define CC_QDSS_STM_EVENT19_CTL_REG__EVENT_MUX_SEL___S 0 +#define CC_QDSS_STM_EVENT19_CTL_REG___M 0x80000007 +#define CC_QDSS_STM_EVENT19_CTL_REG___S 0 + +#define CC_QDSS_STM_EVENT20_CTL_REG (0x00CB2050) +#define CC_QDSS_STM_EVENT20_CTL_REG___RWC QCSR_REG_RW +#define CC_QDSS_STM_EVENT20_CTL_REG___POR 0x00000000 +#define CC_QDSS_STM_EVENT20_CTL_REG__EVENT_ENABLE___POR 0x0 +#define CC_QDSS_STM_EVENT20_CTL_REG__EVENT_MUX_SEL___POR 0x0 +#define CC_QDSS_STM_EVENT20_CTL_REG__EVENT_ENABLE___M 0x80000000 +#define CC_QDSS_STM_EVENT20_CTL_REG__EVENT_ENABLE___S 31 +#define CC_QDSS_STM_EVENT20_CTL_REG__EVENT_ENABLE__DISABLE 0x0 +#define CC_QDSS_STM_EVENT20_CTL_REG__EVENT_ENABLE__ENABLE 0x1 +#define CC_QDSS_STM_EVENT20_CTL_REG__EVENT_MUX_SEL___M 0x00000007 +#define CC_QDSS_STM_EVENT20_CTL_REG__EVENT_MUX_SEL___S 0 +#define CC_QDSS_STM_EVENT20_CTL_REG___M 0x80000007 +#define CC_QDSS_STM_EVENT20_CTL_REG___S 0 + +#define CC_QDSS_STM_EVENT21_CTL_REG (0x00CB2054) +#define CC_QDSS_STM_EVENT21_CTL_REG___RWC QCSR_REG_RW +#define CC_QDSS_STM_EVENT21_CTL_REG___POR 0x00000000 +#define CC_QDSS_STM_EVENT21_CTL_REG__EVENT_ENABLE___POR 0x0 +#define CC_QDSS_STM_EVENT21_CTL_REG__EVENT_MUX_SEL___POR 0x0 +#define CC_QDSS_STM_EVENT21_CTL_REG__EVENT_ENABLE___M 0x80000000 +#define CC_QDSS_STM_EVENT21_CTL_REG__EVENT_ENABLE___S 31 +#define CC_QDSS_STM_EVENT21_CTL_REG__EVENT_ENABLE__DISABLE 0x0 +#define CC_QDSS_STM_EVENT21_CTL_REG__EVENT_ENABLE__ENABLE 0x1 +#define CC_QDSS_STM_EVENT21_CTL_REG__EVENT_MUX_SEL___M 0x00000007 +#define CC_QDSS_STM_EVENT21_CTL_REG__EVENT_MUX_SEL___S 0 +#define CC_QDSS_STM_EVENT21_CTL_REG___M 0x80000007 +#define CC_QDSS_STM_EVENT21_CTL_REG___S 0 + +#define CC_QDSS_STM_EVENT22_CTL_REG (0x00CB2058) +#define CC_QDSS_STM_EVENT22_CTL_REG___RWC QCSR_REG_RW +#define CC_QDSS_STM_EVENT22_CTL_REG___POR 0x00000000 +#define CC_QDSS_STM_EVENT22_CTL_REG__EVENT_ENABLE___POR 0x0 +#define CC_QDSS_STM_EVENT22_CTL_REG__EVENT_MUX_SEL___POR 0x0 +#define CC_QDSS_STM_EVENT22_CTL_REG__EVENT_ENABLE___M 0x80000000 +#define CC_QDSS_STM_EVENT22_CTL_REG__EVENT_ENABLE___S 31 +#define CC_QDSS_STM_EVENT22_CTL_REG__EVENT_ENABLE__DISABLE 0x0 +#define CC_QDSS_STM_EVENT22_CTL_REG__EVENT_ENABLE__ENABLE 0x1 +#define CC_QDSS_STM_EVENT22_CTL_REG__EVENT_MUX_SEL___M 0x00000007 +#define CC_QDSS_STM_EVENT22_CTL_REG__EVENT_MUX_SEL___S 0 +#define CC_QDSS_STM_EVENT22_CTL_REG___M 0x80000007 +#define CC_QDSS_STM_EVENT22_CTL_REG___S 0 + +#define CC_QDSS_STM_EVENT23_CTL_REG (0x00CB205C) +#define CC_QDSS_STM_EVENT23_CTL_REG___RWC QCSR_REG_RW +#define CC_QDSS_STM_EVENT23_CTL_REG___POR 0x00000000 +#define CC_QDSS_STM_EVENT23_CTL_REG__EVENT_ENABLE___POR 0x0 +#define CC_QDSS_STM_EVENT23_CTL_REG__EVENT_MUX_SEL___POR 0x0 +#define CC_QDSS_STM_EVENT23_CTL_REG__EVENT_ENABLE___M 0x80000000 +#define CC_QDSS_STM_EVENT23_CTL_REG__EVENT_ENABLE___S 31 +#define CC_QDSS_STM_EVENT23_CTL_REG__EVENT_ENABLE__DISABLE 0x0 +#define CC_QDSS_STM_EVENT23_CTL_REG__EVENT_ENABLE__ENABLE 0x1 +#define CC_QDSS_STM_EVENT23_CTL_REG__EVENT_MUX_SEL___M 0x00000007 +#define CC_QDSS_STM_EVENT23_CTL_REG__EVENT_MUX_SEL___S 0 +#define CC_QDSS_STM_EVENT23_CTL_REG___M 0x80000007 +#define CC_QDSS_STM_EVENT23_CTL_REG___S 0 + +#define CC_QDSS_STM_EVENT24_CTL_REG (0x00CB2060) +#define CC_QDSS_STM_EVENT24_CTL_REG___RWC QCSR_REG_RW +#define CC_QDSS_STM_EVENT24_CTL_REG___POR 0x00000000 +#define CC_QDSS_STM_EVENT24_CTL_REG__EVENT_ENABLE___POR 0x0 +#define CC_QDSS_STM_EVENT24_CTL_REG__EVENT_MUX_SEL___POR 0x0 +#define CC_QDSS_STM_EVENT24_CTL_REG__EVENT_ENABLE___M 0x80000000 +#define CC_QDSS_STM_EVENT24_CTL_REG__EVENT_ENABLE___S 31 +#define CC_QDSS_STM_EVENT24_CTL_REG__EVENT_ENABLE__DISABLE 0x0 +#define CC_QDSS_STM_EVENT24_CTL_REG__EVENT_ENABLE__ENABLE 0x1 +#define CC_QDSS_STM_EVENT24_CTL_REG__EVENT_MUX_SEL___M 0x00000007 +#define CC_QDSS_STM_EVENT24_CTL_REG__EVENT_MUX_SEL___S 0 +#define CC_QDSS_STM_EVENT24_CTL_REG___M 0x80000007 +#define CC_QDSS_STM_EVENT24_CTL_REG___S 0 + +#define CC_QDSS_STM_EVENT25_CTL_REG (0x00CB2064) +#define CC_QDSS_STM_EVENT25_CTL_REG___RWC QCSR_REG_RW +#define CC_QDSS_STM_EVENT25_CTL_REG___POR 0x00000000 +#define CC_QDSS_STM_EVENT25_CTL_REG__EVENT_ENABLE___POR 0x0 +#define CC_QDSS_STM_EVENT25_CTL_REG__EVENT_MUX_SEL___POR 0x0 +#define CC_QDSS_STM_EVENT25_CTL_REG__EVENT_ENABLE___M 0x80000000 +#define CC_QDSS_STM_EVENT25_CTL_REG__EVENT_ENABLE___S 31 +#define CC_QDSS_STM_EVENT25_CTL_REG__EVENT_ENABLE__DISABLE 0x0 +#define CC_QDSS_STM_EVENT25_CTL_REG__EVENT_ENABLE__ENABLE 0x1 +#define CC_QDSS_STM_EVENT25_CTL_REG__EVENT_MUX_SEL___M 0x00000007 +#define CC_QDSS_STM_EVENT25_CTL_REG__EVENT_MUX_SEL___S 0 +#define CC_QDSS_STM_EVENT25_CTL_REG___M 0x80000007 +#define CC_QDSS_STM_EVENT25_CTL_REG___S 0 + +#define CC_QDSS_STM_EVENT26_CTL_REG (0x00CB2068) +#define CC_QDSS_STM_EVENT26_CTL_REG___RWC QCSR_REG_RW +#define CC_QDSS_STM_EVENT26_CTL_REG___POR 0x00000000 +#define CC_QDSS_STM_EVENT26_CTL_REG__EVENT_ENABLE___POR 0x0 +#define CC_QDSS_STM_EVENT26_CTL_REG__EVENT_MUX_SEL___POR 0x0 +#define CC_QDSS_STM_EVENT26_CTL_REG__EVENT_ENABLE___M 0x80000000 +#define CC_QDSS_STM_EVENT26_CTL_REG__EVENT_ENABLE___S 31 +#define CC_QDSS_STM_EVENT26_CTL_REG__EVENT_ENABLE__DISABLE 0x0 +#define CC_QDSS_STM_EVENT26_CTL_REG__EVENT_ENABLE__ENABLE 0x1 +#define CC_QDSS_STM_EVENT26_CTL_REG__EVENT_MUX_SEL___M 0x00000007 +#define CC_QDSS_STM_EVENT26_CTL_REG__EVENT_MUX_SEL___S 0 +#define CC_QDSS_STM_EVENT26_CTL_REG___M 0x80000007 +#define CC_QDSS_STM_EVENT26_CTL_REG___S 0 + +#define CC_QDSS_STM_EVENT27_CTL_REG (0x00CB206C) +#define CC_QDSS_STM_EVENT27_CTL_REG___RWC QCSR_REG_RW +#define CC_QDSS_STM_EVENT27_CTL_REG___POR 0x00000000 +#define CC_QDSS_STM_EVENT27_CTL_REG__EVENT_ENABLE___POR 0x0 +#define CC_QDSS_STM_EVENT27_CTL_REG__EVENT_MUX_SEL___POR 0x0 +#define CC_QDSS_STM_EVENT27_CTL_REG__EVENT_ENABLE___M 0x80000000 +#define CC_QDSS_STM_EVENT27_CTL_REG__EVENT_ENABLE___S 31 +#define CC_QDSS_STM_EVENT27_CTL_REG__EVENT_ENABLE__DISABLE 0x0 +#define CC_QDSS_STM_EVENT27_CTL_REG__EVENT_ENABLE__ENABLE 0x1 +#define CC_QDSS_STM_EVENT27_CTL_REG__EVENT_MUX_SEL___M 0x00000007 +#define CC_QDSS_STM_EVENT27_CTL_REG__EVENT_MUX_SEL___S 0 +#define CC_QDSS_STM_EVENT27_CTL_REG___M 0x80000007 +#define CC_QDSS_STM_EVENT27_CTL_REG___S 0 + +#define CC_QDSS_STM_EVENT28_CTL_REG (0x00CB2070) +#define CC_QDSS_STM_EVENT28_CTL_REG___RWC QCSR_REG_RW +#define CC_QDSS_STM_EVENT28_CTL_REG___POR 0x00000000 +#define CC_QDSS_STM_EVENT28_CTL_REG__EVENT_ENABLE___POR 0x0 +#define CC_QDSS_STM_EVENT28_CTL_REG__EVENT_MUX_SEL___POR 0x0 +#define CC_QDSS_STM_EVENT28_CTL_REG__EVENT_ENABLE___M 0x80000000 +#define CC_QDSS_STM_EVENT28_CTL_REG__EVENT_ENABLE___S 31 +#define CC_QDSS_STM_EVENT28_CTL_REG__EVENT_ENABLE__DISABLE 0x0 +#define CC_QDSS_STM_EVENT28_CTL_REG__EVENT_ENABLE__ENABLE 0x1 +#define CC_QDSS_STM_EVENT28_CTL_REG__EVENT_MUX_SEL___M 0x00000007 +#define CC_QDSS_STM_EVENT28_CTL_REG__EVENT_MUX_SEL___S 0 +#define CC_QDSS_STM_EVENT28_CTL_REG___M 0x80000007 +#define CC_QDSS_STM_EVENT28_CTL_REG___S 0 + +#define CC_QDSS_STM_EVENT29_CTL_REG (0x00CB2074) +#define CC_QDSS_STM_EVENT29_CTL_REG___RWC QCSR_REG_RW +#define CC_QDSS_STM_EVENT29_CTL_REG___POR 0x00000000 +#define CC_QDSS_STM_EVENT29_CTL_REG__EVENT_ENABLE___POR 0x0 +#define CC_QDSS_STM_EVENT29_CTL_REG__EVENT_MUX_SEL___POR 0x0 +#define CC_QDSS_STM_EVENT29_CTL_REG__EVENT_ENABLE___M 0x80000000 +#define CC_QDSS_STM_EVENT29_CTL_REG__EVENT_ENABLE___S 31 +#define CC_QDSS_STM_EVENT29_CTL_REG__EVENT_ENABLE__DISABLE 0x0 +#define CC_QDSS_STM_EVENT29_CTL_REG__EVENT_ENABLE__ENABLE 0x1 +#define CC_QDSS_STM_EVENT29_CTL_REG__EVENT_MUX_SEL___M 0x00000007 +#define CC_QDSS_STM_EVENT29_CTL_REG__EVENT_MUX_SEL___S 0 +#define CC_QDSS_STM_EVENT29_CTL_REG___M 0x80000007 +#define CC_QDSS_STM_EVENT29_CTL_REG___S 0 + +#define CC_QDSS_STM_EVENT30_CTL_REG (0x00CB2078) +#define CC_QDSS_STM_EVENT30_CTL_REG___RWC QCSR_REG_RW +#define CC_QDSS_STM_EVENT30_CTL_REG___POR 0x00000000 +#define CC_QDSS_STM_EVENT30_CTL_REG__EVENT_ENABLE___POR 0x0 +#define CC_QDSS_STM_EVENT30_CTL_REG__EVENT_MUX_SEL___POR 0x0 +#define CC_QDSS_STM_EVENT30_CTL_REG__EVENT_ENABLE___M 0x80000000 +#define CC_QDSS_STM_EVENT30_CTL_REG__EVENT_ENABLE___S 31 +#define CC_QDSS_STM_EVENT30_CTL_REG__EVENT_ENABLE__DISABLE 0x0 +#define CC_QDSS_STM_EVENT30_CTL_REG__EVENT_ENABLE__ENABLE 0x1 +#define CC_QDSS_STM_EVENT30_CTL_REG__EVENT_MUX_SEL___M 0x00000007 +#define CC_QDSS_STM_EVENT30_CTL_REG__EVENT_MUX_SEL___S 0 +#define CC_QDSS_STM_EVENT30_CTL_REG___M 0x80000007 +#define CC_QDSS_STM_EVENT30_CTL_REG___S 0 + +#define CC_QDSS_STM_EVENT31_CTL_REG (0x00CB207C) +#define CC_QDSS_STM_EVENT31_CTL_REG___RWC QCSR_REG_RW +#define CC_QDSS_STM_EVENT31_CTL_REG___POR 0x00000000 +#define CC_QDSS_STM_EVENT31_CTL_REG__EVENT_ENABLE___POR 0x0 +#define CC_QDSS_STM_EVENT31_CTL_REG__EVENT_MUX_SEL___POR 0x0 +#define CC_QDSS_STM_EVENT31_CTL_REG__EVENT_ENABLE___M 0x80000000 +#define CC_QDSS_STM_EVENT31_CTL_REG__EVENT_ENABLE___S 31 +#define CC_QDSS_STM_EVENT31_CTL_REG__EVENT_ENABLE__DISABLE 0x0 +#define CC_QDSS_STM_EVENT31_CTL_REG__EVENT_ENABLE__ENABLE 0x1 +#define CC_QDSS_STM_EVENT31_CTL_REG__EVENT_MUX_SEL___M 0x00000007 +#define CC_QDSS_STM_EVENT31_CTL_REG__EVENT_MUX_SEL___S 0 +#define CC_QDSS_STM_EVENT31_CTL_REG___M 0x80000007 +#define CC_QDSS_STM_EVENT31_CTL_REG___S 0 + + +#define UMAC_ACMT_BASE (0x00CC0000) + +#define UMAC_ACMT_UMAC_ACMT_CTRL (0x00CC0000) +#define UMAC_ACMT_UMAC_ACMT_CTRL___RWC QCSR_REG_RW +#define UMAC_ACMT_UMAC_ACMT_CTRL___POR 0x00000000 +#define UMAC_ACMT_UMAC_ACMT_CTRL__ENABLE___POR 0x0 +#define UMAC_ACMT_UMAC_ACMT_CTRL__ENABLE___M 0x00000001 +#define UMAC_ACMT_UMAC_ACMT_CTRL__ENABLE___S 0 +#define UMAC_ACMT_UMAC_ACMT_CTRL___M 0x00000001 +#define UMAC_ACMT_UMAC_ACMT_CTRL___S 0 + +#define UMAC_ACMT_UMAC_ACMT_INTR_ENABLE (0x00CC0004) +#define UMAC_ACMT_UMAC_ACMT_INTR_ENABLE___RWC QCSR_REG_RW +#define UMAC_ACMT_UMAC_ACMT_INTR_ENABLE___POR 0x00000000 +#define UMAC_ACMT_UMAC_ACMT_INTR_ENABLE__INTR_EN___POR 0x0 +#define UMAC_ACMT_UMAC_ACMT_INTR_ENABLE__INTR_EN___M 0x00000001 +#define UMAC_ACMT_UMAC_ACMT_INTR_ENABLE__INTR_EN___S 0 +#define UMAC_ACMT_UMAC_ACMT_INTR_ENABLE___M 0x00000001 +#define UMAC_ACMT_UMAC_ACMT_INTR_ENABLE___S 0 + +#define UMAC_ACMT_UMAC_ACMT_INTR_STATUS (0x00CC0008) +#define UMAC_ACMT_UMAC_ACMT_INTR_STATUS___RWC QCSR_REG_RO +#define UMAC_ACMT_UMAC_ACMT_INTR_STATUS___POR 0x00000000 +#define UMAC_ACMT_UMAC_ACMT_INTR_STATUS__VALID___POR 0x0 +#define UMAC_ACMT_UMAC_ACMT_INTR_STATUS__VALID___M 0x00000001 +#define UMAC_ACMT_UMAC_ACMT_INTR_STATUS__VALID___S 0 +#define UMAC_ACMT_UMAC_ACMT_INTR_STATUS___M 0x00000001 +#define UMAC_ACMT_UMAC_ACMT_INTR_STATUS___S 0 + +#define UMAC_ACMT_UMAC_ACMT_INTR_CLEAR (0x00CC000C) +#define UMAC_ACMT_UMAC_ACMT_INTR_CLEAR___RWC QCSR_REG_WO +#define UMAC_ACMT_UMAC_ACMT_INTR_CLEAR___POR 0x00000000 +#define UMAC_ACMT_UMAC_ACMT_INTR_CLEAR__CLR___POR 0x0 +#define UMAC_ACMT_UMAC_ACMT_INTR_CLEAR__CLR___M 0x00000001 +#define UMAC_ACMT_UMAC_ACMT_INTR_CLEAR__CLR___S 0 +#define UMAC_ACMT_UMAC_ACMT_INTR_CLEAR___M 0x00000001 +#define UMAC_ACMT_UMAC_ACMT_INTR_CLEAR___S 0 + +#define UMAC_ACMT_UMAC_ACMT_DEBUG0 (0x00CC0010) +#define UMAC_ACMT_UMAC_ACMT_DEBUG0___RWC QCSR_REG_RO +#define UMAC_ACMT_UMAC_ACMT_DEBUG0___POR 0x00000000 +#define UMAC_ACMT_UMAC_ACMT_DEBUG0__ADDRESS___POR 0x000000 +#define UMAC_ACMT_UMAC_ACMT_DEBUG0__ADDRESS___M 0x00FFFFFF +#define UMAC_ACMT_UMAC_ACMT_DEBUG0__ADDRESS___S 0 +#define UMAC_ACMT_UMAC_ACMT_DEBUG0___M 0x00FFFFFF +#define UMAC_ACMT_UMAC_ACMT_DEBUG0___S 0 + +#define UMAC_ACMT_UMAC_ACMT_DEBUG1 (0x00CC0014) +#define UMAC_ACMT_UMAC_ACMT_DEBUG1___RWC QCSR_REG_RO +#define UMAC_ACMT_UMAC_ACMT_DEBUG1___POR 0x00000000 +#define UMAC_ACMT_UMAC_ACMT_DEBUG1__RW___POR 0x0 +#define UMAC_ACMT_UMAC_ACMT_DEBUG1__RW___M 0x10000000 +#define UMAC_ACMT_UMAC_ACMT_DEBUG1__RW___S 28 +#define UMAC_ACMT_UMAC_ACMT_DEBUG1___M 0x10000000 +#define UMAC_ACMT_UMAC_ACMT_DEBUG1___S 28 + +#define UMAC_ACMT_UMAC_ACMT_CFG (0x00CC001C) +#define UMAC_ACMT_UMAC_ACMT_CFG___RWC QCSR_REG_RO +#define UMAC_ACMT_UMAC_ACMT_CFG___POR 0x00000001 +#define UMAC_ACMT_UMAC_ACMT_CFG__DFLT_PROTECTION___POR 0x0 +#define UMAC_ACMT_UMAC_ACMT_CFG__PROTECTION_MODE___POR 0x1 +#define UMAC_ACMT_UMAC_ACMT_CFG__DFLT_PROTECTION___M 0x00000010 +#define UMAC_ACMT_UMAC_ACMT_CFG__DFLT_PROTECTION___S 4 +#define UMAC_ACMT_UMAC_ACMT_CFG__PROTECTION_MODE___M 0x00000001 +#define UMAC_ACMT_UMAC_ACMT_CFG__PROTECTION_MODE___S 0 +#define UMAC_ACMT_UMAC_ACMT_CFG___M 0x00000011 +#define UMAC_ACMT_UMAC_ACMT_CFG___S 0 + +#define UMAC_ACMT_UMAC_ACMT_NOC_TSLV_CTRL (0x00CC0040) +#define UMAC_ACMT_UMAC_ACMT_NOC_TSLV_CTRL___RWC QCSR_REG_RW +#define UMAC_ACMT_UMAC_ACMT_NOC_TSLV_CTRL___POR 0x00000111 +#define UMAC_ACMT_UMAC_ACMT_NOC_TSLV_CTRL__RET_AHB_FORCE_POSTED_WR___POR 0x1 +#define UMAC_ACMT_UMAC_ACMT_NOC_TSLV_CTRL__RET_AHB_DEVBUFFABLE___POR 0x1 +#define UMAC_ACMT_UMAC_ACMT_NOC_TSLV_CTRL__TIMEOUT_ENABLE___POR 0x1 +#define UMAC_ACMT_UMAC_ACMT_NOC_TSLV_CTRL__RET_AHB_FORCE_POSTED_WR___M 0x00000100 +#define UMAC_ACMT_UMAC_ACMT_NOC_TSLV_CTRL__RET_AHB_FORCE_POSTED_WR___S 8 +#define UMAC_ACMT_UMAC_ACMT_NOC_TSLV_CTRL__RET_AHB_DEVBUFFABLE___M 0x00000010 +#define UMAC_ACMT_UMAC_ACMT_NOC_TSLV_CTRL__RET_AHB_DEVBUFFABLE___S 4 +#define UMAC_ACMT_UMAC_ACMT_NOC_TSLV_CTRL__TIMEOUT_ENABLE___M 0x00000001 +#define UMAC_ACMT_UMAC_ACMT_NOC_TSLV_CTRL__TIMEOUT_ENABLE___S 0 +#define UMAC_ACMT_UMAC_ACMT_NOC_TSLV_CTRL___M 0x00000111 +#define UMAC_ACMT_UMAC_ACMT_NOC_TSLV_CTRL___S 0 + +#define UMAC_ACMT_UMAC_ACMT_NOC_TESTBUS_SEL (0x00CC0044) +#define UMAC_ACMT_UMAC_ACMT_NOC_TESTBUS_SEL___RWC QCSR_REG_RW +#define UMAC_ACMT_UMAC_ACMT_NOC_TESTBUS_SEL___POR 0x00000000 +#define UMAC_ACMT_UMAC_ACMT_NOC_TESTBUS_SEL__TESTBUS_SEL___POR 0x0 +#define UMAC_ACMT_UMAC_ACMT_NOC_TESTBUS_SEL__TESTBUS_SEL___M 0x0000000F +#define UMAC_ACMT_UMAC_ACMT_NOC_TESTBUS_SEL__TESTBUS_SEL___S 0 +#define UMAC_ACMT_UMAC_ACMT_NOC_TESTBUS_SEL___M 0x0000000F +#define UMAC_ACMT_UMAC_ACMT_NOC_TESTBUS_SEL___S 0 + +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE0 (0x00CC0100) +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE0___RWC QCSR_REG_RW +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE0___POR 0x00000000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE0__REGS_SIZE___POR 0x0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE0__REGS_BASE___POR 0x0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE0__REGS_SIZE___M 0x3FFF0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE0__REGS_SIZE___S 16 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE0__REGS_BASE___M 0x00003FFF +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE0__REGS_BASE___S 0 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE0___M 0x3FFF3FFF +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE0___S 0 + +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE1 (0x00CC0104) +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE1___RWC QCSR_REG_RW +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE1___POR 0x00000000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE1__REGS_SIZE___POR 0x0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE1__REGS_BASE___POR 0x0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE1__REGS_SIZE___M 0x3FFF0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE1__REGS_SIZE___S 16 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE1__REGS_BASE___M 0x00003FFF +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE1__REGS_BASE___S 0 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE1___M 0x3FFF3FFF +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE1___S 0 + +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE2 (0x00CC0108) +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE2___RWC QCSR_REG_RW +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE2___POR 0x00000000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE2__REGS_SIZE___POR 0x0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE2__REGS_BASE___POR 0x0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE2__REGS_SIZE___M 0x3FFF0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE2__REGS_SIZE___S 16 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE2__REGS_BASE___M 0x00003FFF +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE2__REGS_BASE___S 0 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE2___M 0x3FFF3FFF +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE2___S 0 + +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE3 (0x00CC010C) +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE3___RWC QCSR_REG_RW +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE3___POR 0x00000000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE3__REGS_SIZE___POR 0x0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE3__REGS_BASE___POR 0x0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE3__REGS_SIZE___M 0x3FFF0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE3__REGS_SIZE___S 16 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE3__REGS_BASE___M 0x00003FFF +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE3__REGS_BASE___S 0 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE3___M 0x3FFF3FFF +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE3___S 0 + +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE4 (0x00CC0110) +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE4___RWC QCSR_REG_RW +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE4___POR 0x00000000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE4__REGS_SIZE___POR 0x0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE4__REGS_BASE___POR 0x0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE4__REGS_SIZE___M 0x3FFF0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE4__REGS_SIZE___S 16 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE4__REGS_BASE___M 0x00003FFF +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE4__REGS_BASE___S 0 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE4___M 0x3FFF3FFF +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE4___S 0 + +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE5 (0x00CC0114) +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE5___RWC QCSR_REG_RW +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE5___POR 0x00000000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE5__REGS_SIZE___POR 0x0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE5__REGS_BASE___POR 0x0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE5__REGS_SIZE___M 0x3FFF0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE5__REGS_SIZE___S 16 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE5__REGS_BASE___M 0x00003FFF +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE5__REGS_BASE___S 0 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE5___M 0x3FFF3FFF +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE5___S 0 + +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE6 (0x00CC0118) +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE6___RWC QCSR_REG_RW +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE6___POR 0x00000000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE6__REGS_SIZE___POR 0x0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE6__REGS_BASE___POR 0x0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE6__REGS_SIZE___M 0x3FFF0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE6__REGS_SIZE___S 16 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE6__REGS_BASE___M 0x00003FFF +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE6__REGS_BASE___S 0 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE6___M 0x3FFF3FFF +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE6___S 0 + +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE7 (0x00CC011C) +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE7___RWC QCSR_REG_RW +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE7___POR 0x00000000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE7__REGS_SIZE___POR 0x0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE7__REGS_BASE___POR 0x0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE7__REGS_SIZE___M 0x3FFF0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE7__REGS_SIZE___S 16 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE7__REGS_BASE___M 0x00003FFF +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE7__REGS_BASE___S 0 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE7___M 0x3FFF3FFF +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE7___S 0 + +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE8 (0x00CC0120) +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE8___RWC QCSR_REG_RW +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE8___POR 0x00000000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE8__REGS_SIZE___POR 0x0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE8__REGS_BASE___POR 0x0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE8__REGS_SIZE___M 0x3FFF0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE8__REGS_SIZE___S 16 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE8__REGS_BASE___M 0x00003FFF +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE8__REGS_BASE___S 0 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE8___M 0x3FFF3FFF +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE8___S 0 + +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE9 (0x00CC0124) +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE9___RWC QCSR_REG_RW +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE9___POR 0x00000000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE9__REGS_SIZE___POR 0x0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE9__REGS_BASE___POR 0x0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE9__REGS_SIZE___M 0x3FFF0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE9__REGS_SIZE___S 16 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE9__REGS_BASE___M 0x00003FFF +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE9__REGS_BASE___S 0 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE9___M 0x3FFF3FFF +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE9___S 0 + +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE10 (0x00CC0128) +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE10___RWC QCSR_REG_RW +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE10___POR 0x00000000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE10__REGS_SIZE___POR 0x0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE10__REGS_BASE___POR 0x0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE10__REGS_SIZE___M 0x3FFF0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE10__REGS_SIZE___S 16 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE10__REGS_BASE___M 0x00003FFF +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE10__REGS_BASE___S 0 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE10___M 0x3FFF3FFF +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE10___S 0 + +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE11 (0x00CC012C) +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE11___RWC QCSR_REG_RW +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE11___POR 0x00000000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE11__REGS_SIZE___POR 0x0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE11__REGS_BASE___POR 0x0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE11__REGS_SIZE___M 0x3FFF0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE11__REGS_SIZE___S 16 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE11__REGS_BASE___M 0x00003FFF +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE11__REGS_BASE___S 0 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE11___M 0x3FFF3FFF +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE11___S 0 + +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE12 (0x00CC0130) +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE12___RWC QCSR_REG_RW +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE12___POR 0x00000000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE12__REGS_SIZE___POR 0x0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE12__REGS_BASE___POR 0x0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE12__REGS_SIZE___M 0x3FFF0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE12__REGS_SIZE___S 16 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE12__REGS_BASE___M 0x00003FFF +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE12__REGS_BASE___S 0 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE12___M 0x3FFF3FFF +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE12___S 0 + +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE13 (0x00CC0134) +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE13___RWC QCSR_REG_RW +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE13___POR 0x00000000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE13__REGS_SIZE___POR 0x0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE13__REGS_BASE___POR 0x0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE13__REGS_SIZE___M 0x3FFF0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE13__REGS_SIZE___S 16 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE13__REGS_BASE___M 0x00003FFF +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE13__REGS_BASE___S 0 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE13___M 0x3FFF3FFF +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE13___S 0 + +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE14 (0x00CC0138) +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE14___RWC QCSR_REG_RW +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE14___POR 0x00000000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE14__REGS_SIZE___POR 0x0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE14__REGS_BASE___POR 0x0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE14__REGS_SIZE___M 0x3FFF0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE14__REGS_SIZE___S 16 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE14__REGS_BASE___M 0x00003FFF +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE14__REGS_BASE___S 0 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE14___M 0x3FFF3FFF +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE14___S 0 + +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE15 (0x00CC013C) +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE15___RWC QCSR_REG_RW +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE15___POR 0x00000000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE15__REGS_SIZE___POR 0x0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE15__REGS_BASE___POR 0x0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE15__REGS_SIZE___M 0x3FFF0000 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE15__REGS_SIZE___S 16 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE15__REGS_BASE___M 0x00003FFF +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE15__REGS_BASE___S 0 +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE15___M 0x3FFF3FFF +#define UMAC_ACMT_UMAC_ACMT_ACC_CTL_TABLE15___S 0 + +////////////////////////////////////////////////////////////////////////// END +#endif diff --git a/drivers/staging/fw-api/hw/qca6750/v1/mac_tcl_reg_seq_hwiobase.h b/drivers/staging/fw-api/hw/qca6750/v1/mac_tcl_reg_seq_hwiobase.h new file mode 100644 index 000000000000..452693294dfb --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/mac_tcl_reg_seq_hwiobase.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/////////////////////////////////////////////////////////////////////////////////////////////// +// +// mac_tcl_reg_seq_hwiobase.h : automatically generated by Autoseq 3.8 11/13/2019 +// User Name:sanjdas +// +// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. +// +/////////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef __MAC_TCL_REG_SEQ_BASE_H__ +#define __MAC_TCL_REG_SEQ_BASE_H__ + +#ifdef SCALE_INCLUDES + #include "HALhwio.h" +#else + #include "msmhwio.h" +#endif + + +#endif + diff --git a/drivers/staging/fw-api/hw/qca6750/v1/mac_tcl_reg_seq_hwioreg.h b/drivers/staging/fw-api/hw/qca6750/v1/mac_tcl_reg_seq_hwioreg.h new file mode 100644 index 000000000000..b4600515f2c7 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/mac_tcl_reg_seq_hwioreg.h @@ -0,0 +1,6468 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/////////////////////////////////////////////////////////////////////////////////////////////// +// +// mac_tcl_reg_seq_hwioreg.h : automatically generated by Autoseq 3.8 11/13/2019 +// User Name:sanjdas +// +// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. +// +/////////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef __MAC_TCL_REG_SEQ_REG_H__ +#define __MAC_TCL_REG_SEQ_REG_H__ + +#include "seq_hwio.h" +#include "mac_tcl_reg_seq_hwiobase.h" +#ifdef SCALE_INCLUDES + #include "HALhwio.h" +#else + #include "msmhwio.h" +#endif + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Register Data for Block MAC_TCL_REG +/////////////////////////////////////////////////////////////////////////////////////////////// + +//// Register TCL_R0_SW2TCL1_RING_CTRL //// + +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x) (x+0x00000000) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_PHYS(x) (x+0x00000000) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK 0x0003ffe0 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_SHFT 5 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CTRL_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 + +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_BMSK 0x00000020 +#define HWIO_TCL_R0_SW2TCL1_RING_CTRL_RNG_PRTY_SHFT 0x5 + +//// Register TCL_R0_SW2TCL2_RING_CTRL //// + +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x) (x+0x00000004) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_PHYS(x) (x+0x00000004) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK 0x0003ffe0 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_SHFT 5 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CTRL_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 + +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_BMSK 0x00000020 +#define HWIO_TCL_R0_SW2TCL2_RING_CTRL_RNG_PRTY_SHFT 0x5 + +//// Register TCL_R0_SW2TCL3_RING_CTRL //// + +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x) (x+0x00000008) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_PHYS(x) (x+0x00000008) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK 0x0003ffe0 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_SHFT 5 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CTRL_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 + +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_BMSK 0x00000020 +#define HWIO_TCL_R0_SW2TCL3_RING_CTRL_RNG_PRTY_SHFT 0x5 + +//// Register TCL_R0_FW2TCL1_RING_CTRL //// + +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x) (x+0x0000000c) +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_PHYS(x) (x+0x0000000c) +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RMSK 0x0003ffe0 +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_SHFT 5 +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CTRL_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 + +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_PRTY_BMSK 0x00000020 +#define HWIO_TCL_R0_FW2TCL1_RING_CTRL_RNG_PRTY_SHFT 0x5 + +//// Register TCL_R0_SW2TCL_CREDIT_RING_CTRL //// + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x) (x+0x00000010) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_PHYS(x) (x+0x00000010) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_RMSK 0x0003ffe0 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_SHFT 5 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_RMSK) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_TIMEOUT_VAL_BMSK 0x0003ffc0 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_TIMEOUT_VAL_SHFT 0x6 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_RNG_PRTY_BMSK 0x00000020 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CTRL_RNG_PRTY_SHFT 0x5 + +//// Register TCL_R0_CONS_RING_CMN_CTRL_REG //// + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x) (x+0x00000014) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PHYS(x) (x+0x00000014) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK 0x001fffff +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SHFT 0 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_RMSK) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), mask) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OUT(x, val) \ + out_dword( HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), val) +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(x), mask, val, HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_INSERT_VLAN_EN_BMSK 0x00100000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_INSERT_VLAN_EN_SHFT 0x14 + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_STOP_META_RD_AT_8B_BDRY_BMSK 0x00080000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_STOP_META_RD_AT_8B_BDRY_SHFT 0x13 + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ENABLE_C9D1_BMSK 0x00040000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ENABLE_C9D1_SHFT 0x12 + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK 0x00020000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT 0x11 + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_EXTN_NUM_BUF_RD_BMSK 0x0001c000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_EXTN_NUM_BUF_RD_SHFT 0xe + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_TCL_IDLE_BMSK 0x00002000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_TCL_IDLE_SHFT 0xd + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CREDIT_RING_HALT_STAT_BMSK 0x00001000 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CREDIT_RING_HALT_STAT_SHFT 0xc + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_STAT_BMSK 0x00000800 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_STAT_SHFT 0xb + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_STAT_BMSK 0x00000400 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_STAT_SHFT 0xa + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_STAT_BMSK 0x00000200 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_STAT_SHFT 0x9 + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_STAT_BMSK 0x00000100 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_STAT_SHFT 0x8 + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CREDIT_RING_HALT_BMSK 0x00000080 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL_CREDIT_RING_HALT_SHFT 0x7 + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_BMSK 0x00000040 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_FW2TCL1_RNG_HALT_SHFT 0x6 + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_BMSK 0x00000020 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL3_RNG_HALT_SHFT 0x5 + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_BMSK 0x00000010 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL2_RNG_HALT_SHFT 0x4 + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_BMSK 0x00000008 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_SW2TCL1_RNG_HALT_SHFT 0x3 + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_HDR_FWD_EN_BMSK 0x00000004 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_HDR_FWD_EN_SHFT 0x2 + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_HDR_LEN_SEL_BMSK 0x00000002 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_MSDU_HDR_LEN_SEL_SHFT 0x1 + +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_CLFY_DIS_BMSK 0x00000001 +#define HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_CLFY_DIS_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_CTRL //// + +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x) (x+0x00000018) +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_PHYS(x) (x+0x00000018) +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_RMSK 0x0000ffff +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_CTRL_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_DROP_NO_DROP_PRIORITY_BMSK 0x0000c000 +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_DROP_NO_DROP_PRIORITY_SHFT 0xe + +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_RING_BMSK 0x00002000 +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_RING_SHFT 0xd + +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_REQUIRED_BMSK 0x00001000 +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TQM_STATUS_REQUIRED_SHFT 0xc + +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff +#define HWIO_TCL_R0_TCL2TQM_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_CTRL //// + +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x) (x+0x0000001c) +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_PHYS(x) (x+0x0000001c) +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_RMSK 0x00000fff +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_CTRL_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff +#define HWIO_TCL_R0_TCL2FW_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_CTRL //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x) (x+0x00000020) +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_PHYS(x) (x+0x00000020) +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_RMSK 0x00000fff +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff +#define HWIO_TCL_R0_TCL_STATUS1_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_CTRL //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x) (x+0x00000024) +#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_PHYS(x) (x+0x00000024) +#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_RMSK 0x00000fff +#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_TIMEOUT_VAL_BMSK 0x00000fff +#define HWIO_TCL_R0_TCL_STATUS2_RING_CTRL_TIMEOUT_VAL_SHFT 0x0 + +//// Register TCL_R0_GEN_CTRL //// + +#define HWIO_TCL_R0_GEN_CTRL_ADDR(x) (x+0x00000028) +#define HWIO_TCL_R0_GEN_CTRL_PHYS(x) (x+0x00000028) +#define HWIO_TCL_R0_GEN_CTRL_RMSK 0xfffff1fb +#define HWIO_TCL_R0_GEN_CTRL_SHFT 0 +#define HWIO_TCL_R0_GEN_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GEN_CTRL_ADDR(x), HWIO_TCL_R0_GEN_CTRL_RMSK) +#define HWIO_TCL_R0_GEN_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GEN_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_GEN_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GEN_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_GEN_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GEN_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_GEN_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GEN_CTRL_WHO_CLASSIFY_INFO_OFFSET_BMSK 0xffff0000 +#define HWIO_TCL_R0_GEN_CTRL_WHO_CLASSIFY_INFO_OFFSET_SHFT 0x10 + +#define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_L4_BMSK 0x00008000 +#define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_L4_SHFT 0xf + +#define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_ESP_BMSK 0x00004000 +#define HWIO_TCL_R0_GEN_CTRL_PROTOCOL_FROM_AH_OR_ESP_SHFT 0xe + +#define HWIO_TCL_R0_GEN_CTRL_FLOW_TOEPLITZ_5_SEL_BMSK 0x00002000 +#define HWIO_TCL_R0_GEN_CTRL_FLOW_TOEPLITZ_5_SEL_SHFT 0xd + +#define HWIO_TCL_R0_GEN_CTRL_CCE_STAT_UP_DIS_BMSK 0x00001000 +#define HWIO_TCL_R0_GEN_CTRL_CCE_STAT_UP_DIS_SHFT 0xc + +#define HWIO_TCL_R0_GEN_CTRL_CCE_UPDATE_DIS_BMSK 0x00000100 +#define HWIO_TCL_R0_GEN_CTRL_CCE_UPDATE_DIS_SHFT 0x8 + +#define HWIO_TCL_R0_GEN_CTRL_FSE_UPDATE_DIS_BMSK 0x00000080 +#define HWIO_TCL_R0_GEN_CTRL_FSE_UPDATE_DIS_SHFT 0x7 + +#define HWIO_TCL_R0_GEN_CTRL_ADDRY_UPDATE_DIS_BMSK 0x00000040 +#define HWIO_TCL_R0_GEN_CTRL_ADDRY_UPDATE_DIS_SHFT 0x6 + +#define HWIO_TCL_R0_GEN_CTRL_ADDRX_UPDATE_DIS_BMSK 0x00000020 +#define HWIO_TCL_R0_GEN_CTRL_ADDRX_UPDATE_DIS_SHFT 0x5 + +#define HWIO_TCL_R0_GEN_CTRL_FSE_EN_BMSK 0x00000010 +#define HWIO_TCL_R0_GEN_CTRL_FSE_EN_SHFT 0x4 + +#define HWIO_TCL_R0_GEN_CTRL_CCE_EN_BMSK 0x00000008 +#define HWIO_TCL_R0_GEN_CTRL_CCE_EN_SHFT 0x3 + +#define HWIO_TCL_R0_GEN_CTRL_TO_FW_BMSK 0x00000002 +#define HWIO_TCL_R0_GEN_CTRL_TO_FW_SHFT 0x1 + +#define HWIO_TCL_R0_GEN_CTRL_EN_11AH_BMSK 0x00000001 +#define HWIO_TCL_R0_GEN_CTRL_EN_11AH_SHFT 0x0 + +//// Register TCL_R0_DSCP_TID_MAP_n //// + +#define HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n) (base+0x2C+0x4*n) +#define HWIO_TCL_R0_DSCP_TID_MAP_n_PHYS(base, n) (base+0x2C+0x4*n) +#define HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK 0xffffffff +#define HWIO_TCL_R0_DSCP_TID_MAP_n_SHFT 0 +#define HWIO_TCL_R0_DSCP_TID_MAP_n_MAXn 287 +#define HWIO_TCL_R0_DSCP_TID_MAP_n_INI(base, n) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n), HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK) +#define HWIO_TCL_R0_DSCP_TID_MAP_n_INMI(base, n, mask) \ + in_dword_masked ( HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n), mask) +#define HWIO_TCL_R0_DSCP_TID_MAP_n_OUTI(base, n, val) \ + out_dword( HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n), val) +#define HWIO_TCL_R0_DSCP_TID_MAP_n_OUTMI(base, n, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR(base, n), mask, val, HWIO_TCL_R0_DSCP_TID_MAP_n_INI(base, n)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_DSCP_TID_MAP_n_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_DSCP_TID_MAP_n_VAL_SHFT 0x0 + +//// Register TCL_R0_PCP_TID_MAP //// + +#define HWIO_TCL_R0_PCP_TID_MAP_ADDR(x) (x+0x000004ac) +#define HWIO_TCL_R0_PCP_TID_MAP_PHYS(x) (x+0x000004ac) +#define HWIO_TCL_R0_PCP_TID_MAP_RMSK 0x00ffffff +#define HWIO_TCL_R0_PCP_TID_MAP_SHFT 0 +#define HWIO_TCL_R0_PCP_TID_MAP_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), HWIO_TCL_R0_PCP_TID_MAP_RMSK) +#define HWIO_TCL_R0_PCP_TID_MAP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), mask) +#define HWIO_TCL_R0_PCP_TID_MAP_OUT(x, val) \ + out_dword( HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), val) +#define HWIO_TCL_R0_PCP_TID_MAP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_PCP_TID_MAP_ADDR(x), mask, val, HWIO_TCL_R0_PCP_TID_MAP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_BMSK 0x00e00000 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT 0x15 + +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_BMSK 0x001c0000 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT 0x12 + +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_BMSK 0x00038000 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT 0xf + +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_BMSK 0x00007000 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT 0xc + +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_BMSK 0x00000e00 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT 0x9 + +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_BMSK 0x000001c0 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT 0x6 + +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_BMSK 0x00000038 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT 0x3 + +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_0_BMSK 0x00000007 +#define HWIO_TCL_R0_PCP_TID_MAP_PCP_0_SHFT 0x0 + +//// Register TCL_R0_ASE_HASH_KEY_31_0 //// + +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x) (x+0x000004b0) +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_PHYS(x) (x+0x000004b0) +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_SHFT 0 +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_31_0_RMSK) +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), mask) +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_OUT(x, val) \ + out_dword( HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), val) +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_31_0_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_31_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ASE_HASH_KEY_31_0_VAL_SHFT 0x0 + +//// Register TCL_R0_ASE_HASH_KEY_63_32 //// + +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x) (x+0x000004b4) +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_PHYS(x) (x+0x000004b4) +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_SHFT 0 +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_63_32_RMSK) +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), mask) +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_OUT(x, val) \ + out_dword( HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), val) +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_63_32_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_63_32_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ASE_HASH_KEY_63_32_VAL_SHFT 0x0 + +//// Register TCL_R0_ASE_HASH_KEY_64 //// + +#define HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x) (x+0x000004b8) +#define HWIO_TCL_R0_ASE_HASH_KEY_64_PHYS(x) (x+0x000004b8) +#define HWIO_TCL_R0_ASE_HASH_KEY_64_RMSK 0x00000001 +#define HWIO_TCL_R0_ASE_HASH_KEY_64_SHFT 0 +#define HWIO_TCL_R0_ASE_HASH_KEY_64_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), HWIO_TCL_R0_ASE_HASH_KEY_64_RMSK) +#define HWIO_TCL_R0_ASE_HASH_KEY_64_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), mask) +#define HWIO_TCL_R0_ASE_HASH_KEY_64_OUT(x, val) \ + out_dword( HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), val) +#define HWIO_TCL_R0_ASE_HASH_KEY_64_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_HASH_KEY_64_ADDR(x), mask, val, HWIO_TCL_R0_ASE_HASH_KEY_64_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_ASE_HASH_KEY_64_VAL_BMSK 0x00000001 +#define HWIO_TCL_R0_ASE_HASH_KEY_64_VAL_SHFT 0x0 + +//// Register TCL_R0_CONFIG_SEARCH_QUEUE //// + +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x) (x+0x000004bc) +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PHYS(x) (x+0x000004bc) +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_RMSK 0x00fffdfc +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_SHFT 2 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_RMSK) +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), mask) +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_OUT(x, val) \ + out_dword( HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), val) +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ADDR(x), mask, val, HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_MSDU_LEN_ERR_TO_FW_EN_BMSK 0x00800000 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_MSDU_LEN_ERR_TO_FW_EN_SHFT 0x17 + +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_M0_FW_SEL_BMSK 0x00700000 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_M0_FW_SEL_SHFT 0x14 + +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ASE_M0_FW_SEL_BMSK 0x000e0000 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_ASE_M0_FW_SEL_SHFT 0x11 + +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_M0_FW_SEL_BMSK 0x0001c000 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_M0_FW_SEL_SHFT 0xe + +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_DROP_BMSK 0x00002000 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_DROP_SHFT 0xd + +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_DROP_BMSK 0x00001000 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_DROP_SHFT 0xc + +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_LOOP_BMSK 0x00000800 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_LOOP_SHFT 0xb + +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_LOOP_BMSK 0x00000400 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_LOOP_SHFT 0xa + +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PRIORITY_BMSK 0x000001c0 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_PRIORITY_SHFT 0x6 + +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_HANDLER_BMSK 0x00000030 +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_CCE_FAIL_HANDLER_SHFT 0x4 + +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_HANDLER_BMSK 0x0000000c +#define HWIO_TCL_R0_CONFIG_SEARCH_QUEUE_FSE_FAIL_HANDLER_SHFT 0x2 + +//// Register TCL_R0_FSE_FAIL_QUEUE_NUM_LOW //// + +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x) (x+0x000004c0) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_PHYS(x) (x+0x000004c0) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_RMSK 0xffffffff +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_SHFT 0 +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_RMSK) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), val) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask, val, HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_LOW_VAL_SHFT 0x0 + +//// Register TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH //// + +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x) (x+0x000004c4) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_PHYS(x) (x+0x000004c4) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_RMSK 0x000000ff +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_SHFT 0 +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_RMSK) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), val) +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_VAL_BMSK 0x000000ff +#define HWIO_TCL_R0_FSE_FAIL_QUEUE_NUM_HIGH_VAL_SHFT 0x0 + +//// Register TCL_R0_CCE_FAIL_QUEUE_NUM_LOW //// + +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x) (x+0x000004c8) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_PHYS(x) (x+0x000004c8) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_RMSK 0xffffffff +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_SHFT 0 +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_RMSK) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_OUT(x, val) \ + out_dword( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), val) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_ADDR(x), mask, val, HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_LOW_VAL_SHFT 0x0 + +//// Register TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH //// + +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x) (x+0x000004cc) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_PHYS(x) (x+0x000004cc) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_RMSK 0x000000ff +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_SHFT 0 +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_RMSK) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_OUT(x, val) \ + out_dword( HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), val) +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_VAL_BMSK 0x000000ff +#define HWIO_TCL_R0_CCE_FAIL_QUEUE_NUM_HIGH_VAL_SHFT 0x0 + +//// Register TCL_R0_CONFIG_SEARCH_METADATA //// + +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x) (x+0x000004d0) +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_PHYS(x) (x+0x000004d0) +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_RMSK 0xffffffff +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_SHFT 0 +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), HWIO_TCL_R0_CONFIG_SEARCH_METADATA_RMSK) +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), mask) +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_OUT(x, val) \ + out_dword( HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), val) +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_CONFIG_SEARCH_METADATA_ADDR(x), mask, val, HWIO_TCL_R0_CONFIG_SEARCH_METADATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_FSE_FAIL_NUM_BMSK 0xffff0000 +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_FSE_FAIL_NUM_SHFT 0x10 + +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_CCE_FAIL_NUM_BMSK 0x0000ffff +#define HWIO_TCL_R0_CONFIG_SEARCH_METADATA_CCE_FAIL_NUM_SHFT 0x0 + +//// Register TCL_R0_TID_MAP_PRTY //// + +#define HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x) (x+0x000004d4) +#define HWIO_TCL_R0_TID_MAP_PRTY_PHYS(x) (x+0x000004d4) +#define HWIO_TCL_R0_TID_MAP_PRTY_RMSK 0x000000ef +#define HWIO_TCL_R0_TID_MAP_PRTY_SHFT 0 +#define HWIO_TCL_R0_TID_MAP_PRTY_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), HWIO_TCL_R0_TID_MAP_PRTY_RMSK) +#define HWIO_TCL_R0_TID_MAP_PRTY_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), mask) +#define HWIO_TCL_R0_TID_MAP_PRTY_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), val) +#define HWIO_TCL_R0_TID_MAP_PRTY_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TID_MAP_PRTY_ADDR(x), mask, val, HWIO_TCL_R0_TID_MAP_PRTY_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TID_MAP_PRTY_TID_DEF_BMSK 0x000000e0 +#define HWIO_TCL_R0_TID_MAP_PRTY_TID_DEF_SHFT 0x5 + +#define HWIO_TCL_R0_TID_MAP_PRTY_VAL_BMSK 0x0000000f +#define HWIO_TCL_R0_TID_MAP_PRTY_VAL_SHFT 0x0 + +//// Register TCL_R0_INVALID_APB_ACC_ADDR //// + +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x) (x+0x000004d8) +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_PHYS(x) (x+0x000004d8) +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_RMSK 0xffffffff +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_SHFT 0 +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), HWIO_TCL_R0_INVALID_APB_ACC_ADDR_RMSK) +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask) +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_OUT(x, val) \ + out_dword( HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), val) +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask, val, HWIO_TCL_R0_INVALID_APB_ACC_ADDR_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_INVALID_APB_ACC_ADDR_VAL_SHFT 0x0 + +//// Register TCL_R0_WATCHDOG //// + +#define HWIO_TCL_R0_WATCHDOG_ADDR(x) (x+0x000004dc) +#define HWIO_TCL_R0_WATCHDOG_PHYS(x) (x+0x000004dc) +#define HWIO_TCL_R0_WATCHDOG_RMSK 0xffffffff +#define HWIO_TCL_R0_WATCHDOG_SHFT 0 +#define HWIO_TCL_R0_WATCHDOG_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_WATCHDOG_ADDR(x), HWIO_TCL_R0_WATCHDOG_RMSK) +#define HWIO_TCL_R0_WATCHDOG_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_WATCHDOG_ADDR(x), mask) +#define HWIO_TCL_R0_WATCHDOG_OUT(x, val) \ + out_dword( HWIO_TCL_R0_WATCHDOG_ADDR(x), val) +#define HWIO_TCL_R0_WATCHDOG_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_WATCHDOG_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_TCL_R0_WATCHDOG_STATUS_SHFT 0x10 + +#define HWIO_TCL_R0_WATCHDOG_LIMIT_BMSK 0x0000ffff +#define HWIO_TCL_R0_WATCHDOG_LIMIT_SHFT 0x0 + +//// Register TCL_R0_LCE_RULE_n //// + +#define HWIO_TCL_R0_LCE_RULE_n_ADDR(base, n) (base+0x4E0+0x4*n) +#define HWIO_TCL_R0_LCE_RULE_n_PHYS(base, n) (base+0x4E0+0x4*n) +#define HWIO_TCL_R0_LCE_RULE_n_RMSK 0x007fffff +#define HWIO_TCL_R0_LCE_RULE_n_SHFT 0 +#define HWIO_TCL_R0_LCE_RULE_n_MAXn 25 +#define HWIO_TCL_R0_LCE_RULE_n_INI(base, n) \ + in_dword_masked ( HWIO_TCL_R0_LCE_RULE_n_ADDR(base, n), HWIO_TCL_R0_LCE_RULE_n_RMSK) +#define HWIO_TCL_R0_LCE_RULE_n_INMI(base, n, mask) \ + in_dword_masked ( HWIO_TCL_R0_LCE_RULE_n_ADDR(base, n), mask) +#define HWIO_TCL_R0_LCE_RULE_n_OUTI(base, n, val) \ + out_dword( HWIO_TCL_R0_LCE_RULE_n_ADDR(base, n), val) +#define HWIO_TCL_R0_LCE_RULE_n_OUTMI(base, n, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_LCE_RULE_n_ADDR(base, n), mask, val, HWIO_TCL_R0_LCE_RULE_n_INI(base, n)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_IP_PROT_BMSK 0x00400000 +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_IP_PROT_SHFT 0x16 + +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_DEST_ADDR_BIT_0_BMSK 0x00200000 +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_DEST_ADDR_BIT_0_SHFT 0x15 + +#define HWIO_TCL_R0_LCE_RULE_n_TCP_OR_UDP_BMSK 0x00180000 +#define HWIO_TCL_R0_LCE_RULE_n_TCP_OR_UDP_SHFT 0x13 + +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_DEST_PORT_BMSK 0x00040000 +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_DEST_PORT_SHFT 0x12 + +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_SRC_PORT_BMSK 0x00020000 +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_SRC_PORT_SHFT 0x11 + +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_L3_TYPE_BMSK 0x00010000 +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_L3_TYPE_SHFT 0x10 + +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_VAL_BMSK 0x0000ffff +#define HWIO_TCL_R0_LCE_RULE_n_MATCH_VAL_SHFT 0x0 + +//// Register TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n //// + +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_ADDR(base, n) (base+0x548+0x4*n) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_PHYS(base, n) (base+0x548+0x4*n) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_RMSK 0xffffffff +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_SHFT 0 +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_MAXn 25 +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_INI(base, n) \ + in_dword_masked ( HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_ADDR(base, n), HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_RMSK) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_INMI(base, n, mask) \ + in_dword_masked ( HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_ADDR(base, n), mask) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_OUTI(base, n, val) \ + out_dword( HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_ADDR(base, n), val) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_OUTMI(base, n, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_ADDR(base, n), mask, val, HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_INI(base, n)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_LSB_n_VAL_SHFT 0x0 + +//// Register TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n //// + +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_ADDR(base, n) (base+0x5B0+0x4*n) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_PHYS(base, n) (base+0x5B0+0x4*n) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_RMSK 0x000000ff +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_SHFT 0 +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_MAXn 25 +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_INI(base, n) \ + in_dword_masked ( HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_ADDR(base, n), HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_RMSK) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_INMI(base, n, mask) \ + in_dword_masked ( HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_ADDR(base, n), mask) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_OUTI(base, n, val) \ + out_dword( HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_ADDR(base, n), val) +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_OUTMI(base, n, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_ADDR(base, n), mask, val, HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_INI(base, n)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_VAL_BMSK 0x000000ff +#define HWIO_TCL_R0_LCE_CLFY_INFO_FLOW_PTR_MSB_n_VAL_SHFT 0x0 + +//// Register TCL_R0_LCE_CLFY_INFO_HANDLER_n //// + +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_ADDR(base, n) (base+0x618+0x4*n) +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_PHYS(base, n) (base+0x618+0x4*n) +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_RMSK 0x003fffff +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_SHFT 0 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_MAXn 25 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_INI(base, n) \ + in_dword_masked ( HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_ADDR(base, n), HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_RMSK) +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_INMI(base, n, mask) \ + in_dword_masked ( HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_ADDR(base, n), mask) +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_OUTI(base, n, val) \ + out_dword( HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_ADDR(base, n), val) +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_OUTMI(base, n, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_ADDR(base, n), mask, val, HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_INI(base, n)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_RULE_HIT_BMSK 0x00200000 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_RULE_HIT_SHFT 0x15 + +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_METADATA_BMSK 0x001fffe0 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_METADATA_SHFT 0x5 + +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_MSDU_DROP_BMSK 0x00000010 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_MSDU_DROP_SHFT 0x4 + +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TO_TQM_IF_M0_FW_BMSK 0x00000008 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TO_TQM_IF_M0_FW_SHFT 0x3 + +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TQM_FLOW_LOOP_HANDLER_BMSK 0x00000004 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TQM_FLOW_LOOP_HANDLER_SHFT 0x2 + +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TQM_FLOW_HANDLER_BMSK 0x00000003 +#define HWIO_TCL_R0_LCE_CLFY_INFO_HANDLER_n_TQM_FLOW_HANDLER_SHFT 0x0 + +//// Register TCL_R0_CLKGATE_DISABLE //// + +#define HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x) (x+0x00000680) +#define HWIO_TCL_R0_CLKGATE_DISABLE_PHYS(x) (x+0x00000680) +#define HWIO_TCL_R0_CLKGATE_DISABLE_RMSK 0xffffffff +#define HWIO_TCL_R0_CLKGATE_DISABLE_SHFT 0 +#define HWIO_TCL_R0_CLKGATE_DISABLE_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_CLKGATE_DISABLE_RMSK) +#define HWIO_TCL_R0_CLKGATE_DISABLE_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), mask) +#define HWIO_TCL_R0_CLKGATE_DISABLE_OUT(x, val) \ + out_dword( HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), val) +#define HWIO_TCL_R0_CLKGATE_DISABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_CLKGATE_DISABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_CLKGATE_DISABLE_CLK_ENS_EXTEND_BMSK 0x80000000 +#define HWIO_TCL_R0_CLKGATE_DISABLE_CLK_ENS_EXTEND_SHFT 0x1f + +#define HWIO_TCL_R0_CLKGATE_DISABLE_CPU_IF_EXTEND_BMSK 0x40000000 +#define HWIO_TCL_R0_CLKGATE_DISABLE_CPU_IF_EXTEND_SHFT 0x1e + +#define HWIO_TCL_R0_CLKGATE_DISABLE_APB_CLK_BMSK 0x20000000 +#define HWIO_TCL_R0_CLKGATE_DISABLE_APB_CLK_SHFT 0x1d + +#define HWIO_TCL_R0_CLKGATE_DISABLE_FSE_BMSK 0x10000000 +#define HWIO_TCL_R0_CLKGATE_DISABLE_FSE_SHFT 0x1c + +#define HWIO_TCL_R0_CLKGATE_DISABLE_CLFY_RES_MEM_BMSK 0x08000000 +#define HWIO_TCL_R0_CLKGATE_DISABLE_CLFY_RES_MEM_SHFT 0x1b + +#define HWIO_TCL_R0_CLKGATE_DISABLE_GSE_CTRL_BMSK 0x04000000 +#define HWIO_TCL_R0_CLKGATE_DISABLE_GSE_CTRL_SHFT 0x1a + +#define HWIO_TCL_R0_CLKGATE_DISABLE_GSE_CCE_RES_BMSK 0x02000000 +#define HWIO_TCL_R0_CLKGATE_DISABLE_GSE_CCE_RES_SHFT 0x19 + +#define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2_STATUS2_PROD_RING_BMSK 0x01000000 +#define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2_STATUS2_PROD_RING_SHFT 0x18 + +#define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2_STATUS1_PROD_RING_BMSK 0x00800000 +#define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2_STATUS1_PROD_RING_SHFT 0x17 + +#define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2FW_PROD_RING_BMSK 0x00400000 +#define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2FW_PROD_RING_SHFT 0x16 + +#define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2TQM_PROD_RING_BMSK 0x00200000 +#define HWIO_TCL_R0_CLKGATE_DISABLE_TCL2TQM_PROD_RING_SHFT 0x15 + +#define HWIO_TCL_R0_CLKGATE_DISABLE_PROD_RING_CTRL_BMSK 0x00100000 +#define HWIO_TCL_R0_CLKGATE_DISABLE_PROD_RING_CTRL_SHFT 0x14 + +#define HWIO_TCL_R0_CLKGATE_DISABLE_TLV_DECODE_BMSK 0x00080000 +#define HWIO_TCL_R0_CLKGATE_DISABLE_TLV_DECODE_SHFT 0x13 + +#define HWIO_TCL_R0_CLKGATE_DISABLE_TLV_GEN_BMSK 0x00040000 +#define HWIO_TCL_R0_CLKGATE_DISABLE_TLV_GEN_SHFT 0x12 + +#define HWIO_TCL_R0_CLKGATE_DISABLE_DATA_FETCH_BMSK 0x00020000 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DATA_FETCH_SHFT 0x11 + +#define HWIO_TCL_R0_CLKGATE_DISABLE_DATA_BUF_BMSK 0x00010000 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DATA_BUF_SHFT 0x10 + +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_BUF_BMSK 0x00008000 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_BUF_SHFT 0xf + +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_BMSK 0x00004000 +#define HWIO_TCL_R0_CLKGATE_DISABLE_DESC_RD_SHFT 0xe + +#define HWIO_TCL_R0_CLKGATE_DISABLE_ASE_BMSK 0x00002000 +#define HWIO_TCL_R0_CLKGATE_DISABLE_ASE_SHFT 0xd + +#define HWIO_TCL_R0_CLKGATE_DISABLE_GXI_BMSK 0x00001000 +#define HWIO_TCL_R0_CLKGATE_DISABLE_GXI_SHFT 0xc + +#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_3_BMSK 0x00000800 +#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_3_SHFT 0xb + +#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_2_BMSK 0x00000400 +#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_2_SHFT 0xa + +#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_1_BMSK 0x00000200 +#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_1_SHFT 0x9 + +#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_0_BMSK 0x00000100 +#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_P_0_SHFT 0x8 + +#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_4_BMSK 0x00000080 +#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_4_SHFT 0x7 + +#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_3_BMSK 0x00000040 +#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_3_SHFT 0x6 + +#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_2_BMSK 0x00000020 +#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_2_SHFT 0x5 + +#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_1_BMSK 0x00000010 +#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_1_SHFT 0x4 + +#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_0_BMSK 0x00000008 +#define HWIO_TCL_R0_CLKGATE_DISABLE_SRNG_C_0_SHFT 0x3 + +#define HWIO_TCL_R0_CLKGATE_DISABLE_TCL_IDLE_REQ_SM_BMSK 0x00000004 +#define HWIO_TCL_R0_CLKGATE_DISABLE_TCL_IDLE_REQ_SM_SHFT 0x2 + +#define HWIO_TCL_R0_CLKGATE_DISABLE_LCE_CCE_BMSK 0x00000002 +#define HWIO_TCL_R0_CLKGATE_DISABLE_LCE_CCE_SHFT 0x1 + +#define HWIO_TCL_R0_CLKGATE_DISABLE_PARSER_BMSK 0x00000001 +#define HWIO_TCL_R0_CLKGATE_DISABLE_PARSER_SHFT 0x0 + +//// Register TCL_R0_CREDIT_COUNT //// + +#define HWIO_TCL_R0_CREDIT_COUNT_ADDR(x) (x+0x00000684) +#define HWIO_TCL_R0_CREDIT_COUNT_PHYS(x) (x+0x00000684) +#define HWIO_TCL_R0_CREDIT_COUNT_RMSK 0x0001ffff +#define HWIO_TCL_R0_CREDIT_COUNT_SHFT 0 +#define HWIO_TCL_R0_CREDIT_COUNT_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_CREDIT_COUNT_ADDR(x), HWIO_TCL_R0_CREDIT_COUNT_RMSK) +#define HWIO_TCL_R0_CREDIT_COUNT_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_CREDIT_COUNT_ADDR(x), mask) +#define HWIO_TCL_R0_CREDIT_COUNT_OUT(x, val) \ + out_dword( HWIO_TCL_R0_CREDIT_COUNT_ADDR(x), val) +#define HWIO_TCL_R0_CREDIT_COUNT_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_CREDIT_COUNT_ADDR(x), mask, val, HWIO_TCL_R0_CREDIT_COUNT_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_CREDIT_COUNT_ENABLE_BMSK 0x00010000 +#define HWIO_TCL_R0_CREDIT_COUNT_ENABLE_SHFT 0x10 + +#define HWIO_TCL_R0_CREDIT_COUNT_VAL_BMSK 0x0000ffff +#define HWIO_TCL_R0_CREDIT_COUNT_VAL_SHFT 0x0 + +//// Register TCL_R0_CURRENT_CREDIT_COUNT //// + +#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_ADDR(x) (x+0x00000688) +#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_PHYS(x) (x+0x00000688) +#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_RMSK 0x0000ffff +#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_SHFT 0 +#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_CURRENT_CREDIT_COUNT_ADDR(x), HWIO_TCL_R0_CURRENT_CREDIT_COUNT_RMSK) +#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_CURRENT_CREDIT_COUNT_ADDR(x), mask) +#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_OUT(x, val) \ + out_dword( HWIO_TCL_R0_CURRENT_CREDIT_COUNT_ADDR(x), val) +#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_CURRENT_CREDIT_COUNT_ADDR(x), mask, val, HWIO_TCL_R0_CURRENT_CREDIT_COUNT_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_VAL_BMSK 0x0000ffff +#define HWIO_TCL_R0_CURRENT_CREDIT_COUNT_VAL_SHFT 0x0 + +//// Register TCL_R0_S_PARE_REGISTER //// + +#define HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x) (x+0x0000068c) +#define HWIO_TCL_R0_S_PARE_REGISTER_PHYS(x) (x+0x0000068c) +#define HWIO_TCL_R0_S_PARE_REGISTER_RMSK 0xffffffff +#define HWIO_TCL_R0_S_PARE_REGISTER_SHFT 0 +#define HWIO_TCL_R0_S_PARE_REGISTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x), HWIO_TCL_R0_S_PARE_REGISTER_RMSK) +#define HWIO_TCL_R0_S_PARE_REGISTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x), mask) +#define HWIO_TCL_R0_S_PARE_REGISTER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x), val) +#define HWIO_TCL_R0_S_PARE_REGISTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_S_PARE_REGISTER_ADDR(x), mask, val, HWIO_TCL_R0_S_PARE_REGISTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_S_PARE_REGISTER_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_S_PARE_REGISTER_VAL_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_BASE_LSB //// + +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x) (x+0x00000690) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_PHYS(x) (x+0x00000690) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_BASE_MSB //// + +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x) (x+0x00000694) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_PHYS(x) (x+0x00000694) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RMSK 0x0fffffff +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_ID //// + +#define HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x) (x+0x00000698) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_PHYS(x) (x+0x00000698) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL1_RING_ID_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_ID_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_STATUS //// + +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x) (x+0x0000069c) +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_PHYS(x) (x+0x0000069c) +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_MISC //// + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x) (x+0x000006a0) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_PHYS(x) (x+0x000006a0) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RMSK 0x003fffff +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MISC_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_TCL_R0_SW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_TP_ADDR_LSB //// + +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x) (x+0x000006ac) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_PHYS(x) (x+0x000006ac) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_TP_ADDR_MSB //// + +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x) (x+0x000006b0) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_PHYS(x) (x+0x000006b0) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000006c0) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000006c0) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000006c4) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000006c4) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS //// + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000006c8) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000006c8) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000006cc) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000006cc) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000006d0) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000006d0) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000006d4) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000006d4) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x0fffffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x0ff00000 +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x14 + +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x000fffff +#define HWIO_TCL_R0_SW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB //// + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000006d8) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000006d8) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB //// + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000006dc) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000006dc) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_MSI1_DATA //// + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x) (x+0x000006e0) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_PHYS(x) (x+0x000006e0) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL1_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET //// + +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000006e4) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000006e4) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_BASE_LSB //// + +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x) (x+0x000006e8) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_PHYS(x) (x+0x000006e8) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_BASE_MSB //// + +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x) (x+0x000006ec) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_PHYS(x) (x+0x000006ec) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RMSK 0x0fffffff +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_ID //// + +#define HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x) (x+0x000006f0) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_PHYS(x) (x+0x000006f0) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL2_RING_ID_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_ID_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL2_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_STATUS //// + +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x) (x+0x000006f4) +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_PHYS(x) (x+0x000006f4) +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_MISC //// + +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x) (x+0x000006f8) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_PHYS(x) (x+0x000006f8) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_RMSK 0x003fffff +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MISC_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_TCL_R0_SW2TCL2_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_TP_ADDR_LSB //// + +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000704) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000704) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_TP_ADDR_MSB //// + +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000708) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000708) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL2_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000718) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000718) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x0000071c) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x0000071c) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS //// + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000720) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000720) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000724) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000724) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000728) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000728) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x0000072c) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x0000072c) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x0fffffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x0ff00000 +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x14 + +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x000fffff +#define HWIO_TCL_R0_SW2TCL2_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB //// + +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000730) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000730) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB //// + +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000734) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000734) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_MSI1_DATA //// + +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x) (x+0x00000738) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_PHYS(x) (x+0x00000738) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL2_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET //// + +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000073c) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000073c) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_BASE_LSB //// + +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x) (x+0x00000740) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_PHYS(x) (x+0x00000740) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_BASE_MSB //// + +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x) (x+0x00000744) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_PHYS(x) (x+0x00000744) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RMSK 0x0fffffff +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL3_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_ID //// + +#define HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x) (x+0x00000748) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_PHYS(x) (x+0x00000748) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL3_RING_ID_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_ID_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL3_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_STATUS //// + +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x) (x+0x0000074c) +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_PHYS(x) (x+0x0000074c) +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL3_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_MISC //// + +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x) (x+0x00000750) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_PHYS(x) (x+0x00000750) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_RMSK 0x003fffff +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MISC_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_TCL_R0_SW2TCL3_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_TP_ADDR_LSB //// + +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x) (x+0x0000075c) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_PHYS(x) (x+0x0000075c) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_TP_ADDR_MSB //// + +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000760) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000760) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL3_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000770) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000770) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000774) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000774) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS //// + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000778) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000778) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000077c) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000077c) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000780) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000780) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000784) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000784) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x0fffffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x0ff00000 +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x14 + +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x000fffff +#define HWIO_TCL_R0_SW2TCL3_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB //// + +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000788) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000788) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB //// + +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x) (x+0x0000078c) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_PHYS(x) (x+0x0000078c) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_MSI1_DATA //// + +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x) (x+0x00000790) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_PHYS(x) (x+0x00000790) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL3_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET //// + +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000794) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000794) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB //// + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x) (x+0x00000798) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_PHYS(x) (x+0x00000798) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB //// + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x) (x+0x0000079c) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_PHYS(x) (x+0x0000079c) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RMSK 0x0fffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CREDIT_RING_ID //// + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x) (x+0x000007a0) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_PHYS(x) (x+0x000007a0) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_RMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_RMSK) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CREDIT_RING_STATUS //// + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_ADDR(x) (x+0x000007a4) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_PHYS(x) (x+0x000007a4) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CREDIT_RING_MISC //// + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x) (x+0x000007a8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_PHYS(x) (x+0x000007a8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_RMSK 0x003fffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_RMSK) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB //// + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x) (x+0x000007b4) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_PHYS(x) (x+0x000007b4) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB //// + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x) (x+0x000007b8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_PHYS(x) (x+0x000007b8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000007c8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000007c8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000007cc) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000007cc) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS //// + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000007d0) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000007d0) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000007d4) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000007d4) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000007d8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000007d8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000007dc) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000007dc) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x0fffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x0ff00000 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x14 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x000fffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB //// + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000007e0) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000007e0) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB //// + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000007e4) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000007e4) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA //// + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x) (x+0x000007e8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_PHYS(x) (x+0x000007e8) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_RMSK) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET //// + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000007ec) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000007ec) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_TCL_R0_SW2TCL_CREDIT_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_BASE_LSB //// + +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x) (x+0x000007f0) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_PHYS(x) (x+0x000007f0) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_BASE_MSB //// + +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x) (x+0x000007f4) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_PHYS(x) (x+0x000007f4) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_FW2TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_ID //// + +#define HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x) (x+0x000007f8) +#define HWIO_TCL_R0_FW2TCL1_RING_ID_PHYS(x) (x+0x000007f8) +#define HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK 0x000000ff +#define HWIO_TCL_R0_FW2TCL1_RING_ID_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_ID_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_ID_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_ID_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_TCL_R0_FW2TCL1_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_STATUS //// + +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x) (x+0x000007fc) +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_PHYS(x) (x+0x000007fc) +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_STATUS_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_TCL_R0_FW2TCL1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_MISC //// + +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x) (x+0x00000800) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_PHYS(x) (x+0x00000800) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_RMSK 0x003fffff +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MISC_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_TCL_R0_FW2TCL1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_TP_ADDR_LSB //// + +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x) (x+0x0000080c) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_PHYS(x) (x+0x0000080c) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_TP_ADDR_MSB //// + +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000810) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000810) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_FW2TCL1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000820) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000820) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000824) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000824) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS //// + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000828) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000828) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x0000082c) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x0000082c) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000830) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000830) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000834) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000834) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R0_FW2TCL1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB //// + +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000838) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000838) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB //// + +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x0000083c) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x0000083c) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_MSI1_DATA //// + +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x) (x+0x00000840) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_PHYS(x) (x+0x00000840) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_FW2TCL1_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET //// + +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000844) +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000844) +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_TCL_R0_FW2TCL1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_BASE_LSB //// + +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x) (x+0x00000848) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_PHYS(x) (x+0x00000848) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_BASE_MSB //// + +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x) (x+0x0000084c) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_PHYS(x) (x+0x0000084c) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL2TQM_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_ID //// + +#define HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x) (x+0x00000850) +#define HWIO_TCL_R0_TCL2TQM_RING_ID_PHYS(x) (x+0x00000850) +#define HWIO_TCL_R0_TCL2TQM_RING_ID_RMSK 0x0000ffff +#define HWIO_TCL_R0_TCL2TQM_RING_ID_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_ID_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_ID_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_ID_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_TCL_R0_TCL2TQM_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_TCL_R0_TCL2TQM_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL2TQM_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_STATUS //// + +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x) (x+0x00000854) +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_PHYS(x) (x+0x00000854) +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_STATUS_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_TCL_R0_TCL2TQM_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_MISC //// + +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x) (x+0x00000858) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_PHYS(x) (x+0x00000858) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_RMSK 0x03ffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_MISC_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOP_CNT_BMSK 0x03c00000 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOP_CNT_SHFT 0x16 + +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_TCL_R0_TCL2TQM_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_HP_ADDR_LSB //// + +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x) (x+0x0000085c) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_PHYS(x) (x+0x0000085c) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_HP_ADDR_MSB //// + +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000860) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000860) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP //// + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x0000086c) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x0000086c) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS //// + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000870) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000870) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000874) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000874) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff +#define HWIO_TCL_R0_TCL2TQM_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB //// + +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000890) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000890) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB //// + +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000894) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000894) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_MSI1_DATA //// + +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x) (x+0x00000898) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_PHYS(x) (x+0x00000898) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2TQM_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET //// + +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000089c) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000089c) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_TCL_R0_TCL2TQM_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_BASE_LSB //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x) (x+0x000008a0) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_PHYS(x) (x+0x000008a0) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_BASE_MSB //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x) (x+0x000008a4) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_PHYS(x) (x+0x000008a4) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_ID //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x) (x+0x000008a8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_PHYS(x) (x+0x000008a8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RMSK 0x0000ffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_ID_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL_STATUS1_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_STATUS //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x) (x+0x000008ac) +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_PHYS(x) (x+0x000008ac) +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_MISC //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x) (x+0x000008b0) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_PHYS(x) (x+0x000008b0) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RMSK 0x03ffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOP_CNT_BMSK 0x03c00000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOP_CNT_SHFT 0x16 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x) (x+0x000008b4) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_PHYS(x) (x+0x000008b4) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x) (x+0x000008b8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_PHYS(x) (x+0x000008b8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000008c4) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000008c4) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000008c8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000008c8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000008cc) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000008cc) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff +#define HWIO_TCL_R0_TCL_STATUS1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000008e8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000008e8) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000008ec) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000008ec) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_MSI1_DATA //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x) (x+0x000008f0) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_PHYS(x) (x+0x000008f0) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET //// + +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000008f4) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000008f4) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_TCL_R0_TCL_STATUS1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_BASE_LSB //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x) (x+0x000008f8) +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_PHYS(x) (x+0x000008f8) +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_BASE_MSB //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x) (x+0x000008fc) +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_PHYS(x) (x+0x000008fc) +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL_STATUS2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_ID //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x) (x+0x00000900) +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_PHYS(x) (x+0x00000900) +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RMSK 0x0000ffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_ID_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL_STATUS2_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_STATUS //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x) (x+0x00000904) +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_PHYS(x) (x+0x00000904) +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_MISC //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x) (x+0x00000908) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_PHYS(x) (x+0x00000908) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RMSK 0x03ffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOP_CNT_BMSK 0x03c00000 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOP_CNT_SHFT 0x16 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x) (x+0x0000090c) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_PHYS(x) (x+0x0000090c) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000910) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000910) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x0000091c) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x0000091c) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000920) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000920) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000924) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000924) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff +#define HWIO_TCL_R0_TCL_STATUS2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000940) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000940) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000944) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000944) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_MSI1_DATA //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x) (x+0x00000948) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_PHYS(x) (x+0x00000948) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET //// + +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x0000094c) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x0000094c) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_TCL_R0_TCL_STATUS2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_BASE_LSB //// + +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x) (x+0x00000950) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_PHYS(x) (x+0x00000950) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_BASE_MSB //// + +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x) (x+0x00000954) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_PHYS(x) (x+0x00000954) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_ID //// + +#define HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x) (x+0x00000958) +#define HWIO_TCL_R0_TCL2FW_RING_ID_PHYS(x) (x+0x00000958) +#define HWIO_TCL_R0_TCL2FW_RING_ID_RMSK 0x0000ffff +#define HWIO_TCL_R0_TCL2FW_RING_ID_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_ID_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_ID_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_ID_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_ID_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_TCL_R0_TCL2FW_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_TCL_R0_TCL2FW_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL2FW_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_STATUS //// + +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x) (x+0x0000095c) +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_PHYS(x) (x+0x0000095c) +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_STATUS_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_TCL_R0_TCL2FW_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_MISC //// + +#define HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x) (x+0x00000960) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_PHYS(x) (x+0x00000960) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_RMSK 0x03ffffff +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_MISC_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MISC_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOP_CNT_BMSK 0x03c00000 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOP_CNT_SHFT 0x16 + +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_TCL_R0_TCL2FW_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_TCL_R0_TCL2FW_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_TCL_R0_TCL2FW_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_TCL_R0_TCL2FW_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_TCL_R0_TCL2FW_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_HP_ADDR_LSB //// + +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000964) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000964) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_HP_ADDR_MSB //// + +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000968) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000968) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP //// + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000974) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000974) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS //// + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000978) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000978) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x0000097c) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x0000097c) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff +#define HWIO_TCL_R0_TCL2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_MSI1_BASE_LSB //// + +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000998) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000998) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_MSI1_BASE_MSB //// + +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR(x) (x+0x0000099c) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_PHYS(x) (x+0x0000099c) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_MSI1_DATA //// + +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_ADDR(x) (x+0x000009a0) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_PHYS(x) (x+0x000009a0) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_TCL2FW_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET //// + +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000009a4) +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000009a4) +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_TCL_R0_TCL2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register TCL_R0_GXI_TESTBUS_LOWER //// + +#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x) (x+0x000009a8) +#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_PHYS(x) (x+0x000009a8) +#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_RMSK 0xffffffff +#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_SHFT 0 +#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), HWIO_TCL_R0_GXI_TESTBUS_LOWER_RMSK) +#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), val) +#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_TCL_R0_GXI_TESTBUS_LOWER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_GXI_TESTBUS_LOWER_VALUE_SHFT 0x0 + +//// Register TCL_R0_GXI_TESTBUS_UPPER //// + +#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x) (x+0x000009ac) +#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_PHYS(x) (x+0x000009ac) +#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_RMSK 0x000000ff +#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_SHFT 0 +#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), HWIO_TCL_R0_GXI_TESTBUS_UPPER_RMSK) +#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), val) +#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_TCL_R0_GXI_TESTBUS_UPPER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_VALUE_BMSK 0x000000ff +#define HWIO_TCL_R0_GXI_TESTBUS_UPPER_VALUE_SHFT 0x0 + +//// Register TCL_R0_GXI_SM_STATES_IX_0 //// + +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x) (x+0x000009b0) +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_PHYS(x) (x+0x000009b0) +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_RMSK 0x00000fff +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SHFT 0 +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), HWIO_TCL_R0_GXI_SM_STATES_IX_0_RMSK) +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), val) +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_TCL_R0_GXI_SM_STATES_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00 +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9 + +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x000001f0 +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 0x4 + +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0x0000000f +#define HWIO_TCL_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0x0 + +//// Register TCL_R0_GXI_END_OF_TEST_CHECK //// + +#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x) (x+0x000009b4) +#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_PHYS(x) (x+0x000009b4) +#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_RMSK 0x00000001 +#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_SHFT 0 +#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_RMSK) +#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), val) +#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 +#define HWIO_TCL_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 + +//// Register TCL_R0_GXI_CLOCK_GATE_DISABLE //// + +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x) (x+0x000009b8) +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_PHYS(x) (x+0x000009b8) +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RMSK 0x80000fff +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_SHFT 0 +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RMSK) +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), val) +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f + +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_SPARE_BMSK 0x00000800 +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_SPARE_SHFT 0xb + +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_BMSK 0x00000400 +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_SHFT 0xa + +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_FIFO_BMSK 0x00000200 +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_FIFO_SHFT 0x9 + +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_BMSK 0x00000100 +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_SHFT 0x8 + +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_BMSK 0x00000080 +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_SHFT 0x7 + +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_BMSK 0x00000040 +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_SHFT 0x6 + +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_BMSK 0x00000020 +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_SHFT 0x5 + +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_BMSK 0x00000010 +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_SHFT 0x4 + +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_BMSK 0x00000008 +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_SHFT 0x3 + +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_BMSK 0x00000004 +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_SHFT 0x2 + +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_CMD_BMSK 0x00000002 +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_RD_CMD_SHFT 0x1 + +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CORE_BMSK 0x00000001 +#define HWIO_TCL_R0_GXI_CLOCK_GATE_DISABLE_CORE_SHFT 0x0 + +//// Register TCL_R0_GXI_GXI_ERR_INTS //// + +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x) (x+0x000009bc) +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_PHYS(x) (x+0x000009bc) +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_RMSK 0x01010101 +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_SHFT 0 +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), HWIO_TCL_R0_GXI_GXI_ERR_INTS_RMSK) +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), val) +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_ERR_INTS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000 +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18 + +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x00010000 +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 0x10 + +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x00000100 +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 0x8 + +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x00000001 +#define HWIO_TCL_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0x0 + +//// Register TCL_R0_GXI_GXI_ERR_STATS //// + +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x) (x+0x000009c0) +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_PHYS(x) (x+0x000009c0) +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_RMSK 0x003f3f3f +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_SHFT 0 +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), HWIO_TCL_R0_GXI_GXI_ERR_STATS_RMSK) +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), val) +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_ERR_STATS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000 +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10 + +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x00003f00 +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 0x8 + +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x0000003f +#define HWIO_TCL_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0x0 + +//// Register TCL_R0_GXI_GXI_DEFAULT_CONTROL //// + +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x) (x+0x000009c4) +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_PHYS(x) (x+0x000009c4) +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_SHFT 0 +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_RMSK) +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), val) +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18 + +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 0x10 + +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00 +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 0x8 + +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f +#define HWIO_TCL_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0x0 + +//// Register TCL_R0_GXI_GXI_REDUCED_CONTROL //// + +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x) (x+0x000009c8) +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_PHYS(x) (x+0x000009c8) +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_SHFT 0 +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_RMSK) +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), val) +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18 + +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 0x10 + +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00 +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 0x8 + +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f +#define HWIO_TCL_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0x0 + +//// Register TCL_R0_GXI_GXI_MISC_CONTROL //// + +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x) (x+0x000009cc) +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_PHYS(x) (x+0x000009cc) +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_RMSK 0x0fffffff +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_SHFT 0 +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_RMSK) +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), val) +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_BMSK 0x08000000 +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_SHFT 0x1b + +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_BMSK 0x04000000 +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_SHFT 0x1a + +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_BMSK 0x02000000 +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_SHFT 0x19 + +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_BMSK 0x01000000 +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_SHFT 0x18 + +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_BMSK 0x00800000 +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_SHFT 0x17 + +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000 +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14 + +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0x000e0000 +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 0x11 + +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00 +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 0x9 + +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 0x1 + +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x00000001 +#define HWIO_TCL_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0x0 + +//// Register TCL_R0_GXI_GXI_WDOG_CONTROL //// + +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x) (x+0x000009d0) +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_PHYS(x) (x+0x000009d0) +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_RMSK 0xffff0001 +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_SHFT 0 +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_RMSK) +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), val) +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10 + +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x00000001 +#define HWIO_TCL_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0x0 + +//// Register TCL_R0_GXI_GXI_WDOG_STATUS //// + +#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x) (x+0x000009d4) +#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_PHYS(x) (x+0x000009d4) +#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_RMSK 0x0000ffff +#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_SHFT 0 +#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_RMSK) +#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), val) +#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff +#define HWIO_TCL_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0 + +//// Register TCL_R0_GXI_GXI_IDLE_COUNTERS //// + +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x) (x+0x000009d8) +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_PHYS(x) (x+0x000009d8) +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_RMSK 0xffffffff +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_SHFT 0 +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_RMSK) +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), val) +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10 + +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0x0000ffff +#define HWIO_TCL_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0x0 + +//// Register TCL_R0_GXI_GXI_RD_LATENCY_CTRL //// + +#define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x) (x+0x000009dc) +#define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_PHYS(x) (x+0x000009dc) +#define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_RMSK 0x000fffff +#define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_SHFT 0 +#define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_RMSK) +#define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0x000e0000 +#define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11 + +#define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x00010000 +#define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10 + +#define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0x0000ffff +#define HWIO_TCL_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0 + +//// Register TCL_R0_GXI_GXI_WR_LATENCY_CTRL //// + +#define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x) (x+0x000009e0) +#define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_PHYS(x) (x+0x000009e0) +#define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_RMSK 0x000fffff +#define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_SHFT 0 +#define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_RMSK) +#define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0x000e0000 +#define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11 + +#define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x00010000 +#define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10 + +#define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0x0000ffff +#define HWIO_TCL_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0 + +//// Register TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0 //// + +#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x) (x+0x000009e4) +#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_PHYS(x) (x+0x000009e4) +#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff +#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_SHFT 0 +#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK) +#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), val) +#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0x0 + +//// Register TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1 //// + +#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x) (x+0x000009e8) +#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_PHYS(x) (x+0x000009e8) +#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff +#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_SHFT 0 +#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK) +#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), val) +#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0x0 + +//// Register TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0 //// + +#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x) (x+0x000009ec) +#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_PHYS(x) (x+0x000009ec) +#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff +#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_SHFT 0 +#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK) +#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), val) +#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0x0 + +//// Register TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1 //// + +#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x) (x+0x000009f0) +#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_PHYS(x) (x+0x000009f0) +#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff +#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_SHFT 0 +#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK) +#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), val) +#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff +#define HWIO_TCL_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0x0 + +//// Register TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL //// + +#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x) (x+0x000009f4) +#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_PHYS(x) (x+0x000009f4) +#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_RMSK 0x00009f9f +#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_SHFT 0 +#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_RMSK) +#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), mask) +#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), val) +#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), mask, val, HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_EN_BMSK 0x00008000 +#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_EN_SHFT 0xf + +#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_CNT_BMSK 0x00001f00 +#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_CNT_SHFT 0x8 + +#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_EN_BMSK 0x00000080 +#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_EN_SHFT 0x7 + +#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_BMSK 0x0000001f +#define HWIO_TCL_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_SHFT 0x0 + +//// Register TCL_R0_ASE_GST_BASE_ADDR_LOW //// + +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x) (x+0x000009f8) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_PHYS(x) (x+0x000009f8) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_SHFT 0 +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_RMSK) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), mask) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_OUT(x, val) \ + out_dword( HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), val) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_VAL_BMSK 0xffffffff +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_LOW_VAL_SHFT 0x0 + +//// Register TCL_R0_ASE_GST_BASE_ADDR_HIGH //// + +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x) (x+0x000009fc) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_PHYS(x) (x+0x000009fc) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_RMSK 0x000000ff +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_SHFT 0 +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_RMSK) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), mask) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_OUT(x, val) \ + out_dword( HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), val) +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_VAL_BMSK 0x000000ff +#define HWIO_TCL_R0_ASE_GST_BASE_ADDR_HIGH_VAL_SHFT 0x0 + +//// Register TCL_R0_ASE_GST_SIZE //// + +#define HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x) (x+0x00000a00) +#define HWIO_TCL_R0_ASE_GST_SIZE_PHYS(x) (x+0x00000a00) +#define HWIO_TCL_R0_ASE_GST_SIZE_RMSK 0x000fffff +#define HWIO_TCL_R0_ASE_GST_SIZE_SHFT 0 +#define HWIO_TCL_R0_ASE_GST_SIZE_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), HWIO_TCL_R0_ASE_GST_SIZE_RMSK) +#define HWIO_TCL_R0_ASE_GST_SIZE_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), mask) +#define HWIO_TCL_R0_ASE_GST_SIZE_OUT(x, val) \ + out_dword( HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), val) +#define HWIO_TCL_R0_ASE_GST_SIZE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_GST_SIZE_ADDR(x), mask, val, HWIO_TCL_R0_ASE_GST_SIZE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_ASE_GST_SIZE_VAL_BMSK 0x000fffff +#define HWIO_TCL_R0_ASE_GST_SIZE_VAL_SHFT 0x0 + +//// Register TCL_R0_ASE_SEARCH_CTRL //// + +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x) (x+0x00000a04) +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_PHYS(x) (x+0x00000a04) +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_RMSK 0xffff3fff +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_SHFT 0 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), HWIO_TCL_R0_ASE_SEARCH_CTRL_RMSK) +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), mask) +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), val) +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_SEARCH_CTRL_ADDR(x), mask, val, HWIO_TCL_R0_ASE_SEARCH_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_TIMEOUT_THRESH_BMSK 0xffff0000 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_TIMEOUT_THRESH_SHFT 0x10 + +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_CMD_READ_BYPASS_EN_BMSK 0x00002000 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_CMD_READ_BYPASS_EN_SHFT 0xd + +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_WRITE_BACK_FIX_EN_BMSK 0x00001000 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_WRITE_BACK_FIX_EN_SHFT 0xc + +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_ONLY_ENTRY_CMD_FIX_EN_BMSK 0x00000800 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_ONLY_ENTRY_CMD_FIX_EN_SHFT 0xb + +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_FAILURES_ENABLE_BMSK 0x00000400 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_FAILURES_ENABLE_SHFT 0xa + +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_DISABLE_BMSK 0x00000200 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_CACHE_DISABLE_SHFT 0x9 + +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_SEARCH_SWAP_BMSK 0x00000100 +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_SEARCH_SWAP_SHFT 0x8 + +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_MAX_SEARCH_BMSK 0x000000ff +#define HWIO_TCL_R0_ASE_SEARCH_CTRL_MAX_SEARCH_SHFT 0x0 + +//// Register TCL_R0_ASE_WATCHDOG //// + +#define HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x) (x+0x00000a08) +#define HWIO_TCL_R0_ASE_WATCHDOG_PHYS(x) (x+0x00000a08) +#define HWIO_TCL_R0_ASE_WATCHDOG_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_WATCHDOG_SHFT 0 +#define HWIO_TCL_R0_ASE_WATCHDOG_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), HWIO_TCL_R0_ASE_WATCHDOG_RMSK) +#define HWIO_TCL_R0_ASE_WATCHDOG_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), mask) +#define HWIO_TCL_R0_ASE_WATCHDOG_OUT(x, val) \ + out_dword( HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), val) +#define HWIO_TCL_R0_ASE_WATCHDOG_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_WATCHDOG_ADDR(x), mask, val, HWIO_TCL_R0_ASE_WATCHDOG_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_ASE_WATCHDOG_STATUS_BMSK 0xffff0000 +#define HWIO_TCL_R0_ASE_WATCHDOG_STATUS_SHFT 0x10 + +#define HWIO_TCL_R0_ASE_WATCHDOG_LIMIT_BMSK 0x0000ffff +#define HWIO_TCL_R0_ASE_WATCHDOG_LIMIT_SHFT 0x0 + +//// Register TCL_R0_ASE_CLKGATE_DISABLE //// + +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x) (x+0x00000a0c) +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_PHYS(x) (x+0x00000a0c) +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_RMSK 0xffffffff +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_SHFT 0 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), HWIO_TCL_R0_ASE_CLKGATE_DISABLE_RMSK) +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), mask) +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_OUT(x, val) \ + out_dword( HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), val) +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_CLKGATE_DISABLE_ADDR(x), mask, val, HWIO_TCL_R0_ASE_CLKGATE_DISABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CLK_EXTEND_BMSK 0x80000000 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CLK_EXTEND_SHFT 0x1f + +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CPU_IF_EXTEND_BMSK 0x40000000 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CPU_IF_EXTEND_SHFT 0x1e + +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_RSRVD_BMSK 0x3ffffe00 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_RSRVD_SHFT 0x9 + +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_TOP_BMSK 0x00000100 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_TOP_SHFT 0x8 + +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CACHE_BMSK 0x00000080 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_CACHE_SHFT 0x7 + +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_SLOTS_ARRAY_HASH_BMSK 0x00000040 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_SLOTS_ARRAY_HASH_SHFT 0x6 + +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_APP_RETURN_BMSK 0x00000020 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_APP_RETURN_SHFT 0x5 + +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP2_BMSK 0x00000010 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP2_SHFT 0x4 + +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP1_BMSK 0x00000008 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_RESP1_SHFT 0x3 + +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS2_BMSK 0x00000004 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS2_SHFT 0x2 + +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS1_BMSK 0x00000002 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_MEM_ISS1_SHFT 0x1 + +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_CTL_BMSK 0x00000001 +#define HWIO_TCL_R0_ASE_CLKGATE_DISABLE_GSE_CTL_SHFT 0x0 + +//// Register TCL_R0_ASE_WRITE_BACK_PENDING //// + +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x) (x+0x00000a10) +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_PHYS(x) (x+0x00000a10) +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_RMSK 0x00000001 +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_SHFT 0 +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_IN(x) \ + in_dword_masked ( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_RMSK) +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), mask) +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_OUT(x, val) \ + out_dword( HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), val) +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_ADDR(x), mask, val, HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_STATUS_BMSK 0x00000001 +#define HWIO_TCL_R0_ASE_WRITE_BACK_PENDING_STATUS_SHFT 0x0 + +//// Register TCL_R1_CACHE_FLUSH //// + +#define HWIO_TCL_R1_CACHE_FLUSH_ADDR(x) (x+0x00001000) +#define HWIO_TCL_R1_CACHE_FLUSH_PHYS(x) (x+0x00001000) +#define HWIO_TCL_R1_CACHE_FLUSH_RMSK 0x00000003 +#define HWIO_TCL_R1_CACHE_FLUSH_SHFT 0 +#define HWIO_TCL_R1_CACHE_FLUSH_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_CACHE_FLUSH_ADDR(x), HWIO_TCL_R1_CACHE_FLUSH_RMSK) +#define HWIO_TCL_R1_CACHE_FLUSH_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_CACHE_FLUSH_ADDR(x), mask) +#define HWIO_TCL_R1_CACHE_FLUSH_OUT(x, val) \ + out_dword( HWIO_TCL_R1_CACHE_FLUSH_ADDR(x), val) +#define HWIO_TCL_R1_CACHE_FLUSH_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_CACHE_FLUSH_ADDR(x), mask, val, HWIO_TCL_R1_CACHE_FLUSH_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_CACHE_FLUSH_STATUS_BMSK 0x00000002 +#define HWIO_TCL_R1_CACHE_FLUSH_STATUS_SHFT 0x1 + +#define HWIO_TCL_R1_CACHE_FLUSH_ENABLE_BMSK 0x00000001 +#define HWIO_TCL_R1_CACHE_FLUSH_ENABLE_SHFT 0x0 + +//// Register TCL_R1_SM_STATES_IX_0 //// + +#define HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x) (x+0x00001004) +#define HWIO_TCL_R1_SM_STATES_IX_0_PHYS(x) (x+0x00001004) +#define HWIO_TCL_R1_SM_STATES_IX_0_RMSK 0x07ffffff +#define HWIO_TCL_R1_SM_STATES_IX_0_SHFT 0 +#define HWIO_TCL_R1_SM_STATES_IX_0_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), HWIO_TCL_R1_SM_STATES_IX_0_RMSK) +#define HWIO_TCL_R1_SM_STATES_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), mask) +#define HWIO_TCL_R1_SM_STATES_IX_0_OUT(x, val) \ + out_dword( HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), val) +#define HWIO_TCL_R1_SM_STATES_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_TCL_R1_SM_STATES_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_BMSK 0x07000000 +#define HWIO_TCL_R1_SM_STATES_IX_0_GSE_CTRL_SHFT 0x18 + +#define HWIO_TCL_R1_SM_STATES_IX_0_TLV_GEN_BMSK 0x00e00000 +#define HWIO_TCL_R1_SM_STATES_IX_0_TLV_GEN_SHFT 0x15 + +#define HWIO_TCL_R1_SM_STATES_IX_0_EXTN_DESC_FETCH_BMSK 0x001c0000 +#define HWIO_TCL_R1_SM_STATES_IX_0_EXTN_DESC_FETCH_SHFT 0x12 + +#define HWIO_TCL_R1_SM_STATES_IX_0_MSDU_FETCH_BMSK 0x00038000 +#define HWIO_TCL_R1_SM_STATES_IX_0_MSDU_FETCH_SHFT 0xf + +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL_CREDIT_RING_BMSK 0x00007000 +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL_CREDIT_RING_SHFT 0xc + +#define HWIO_TCL_R1_SM_STATES_IX_0_FW2TCL1_RING_BMSK 0x00000e00 +#define HWIO_TCL_R1_SM_STATES_IX_0_FW2TCL1_RING_SHFT 0x9 + +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL3_RING_BMSK 0x000001c0 +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL3_RING_SHFT 0x6 + +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL2_RING_BMSK 0x00000038 +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL2_RING_SHFT 0x3 + +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL1_RING_BMSK 0x00000007 +#define HWIO_TCL_R1_SM_STATES_IX_0_SW2TCL1_RING_SHFT 0x0 + +//// Register TCL_R1_SM_STATES_IX_1 //// + +#define HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x) (x+0x00001008) +#define HWIO_TCL_R1_SM_STATES_IX_1_PHYS(x) (x+0x00001008) +#define HWIO_TCL_R1_SM_STATES_IX_1_RMSK 0x0003ffff +#define HWIO_TCL_R1_SM_STATES_IX_1_SHFT 0 +#define HWIO_TCL_R1_SM_STATES_IX_1_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), HWIO_TCL_R1_SM_STATES_IX_1_RMSK) +#define HWIO_TCL_R1_SM_STATES_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), mask) +#define HWIO_TCL_R1_SM_STATES_IX_1_OUT(x, val) \ + out_dword( HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), val) +#define HWIO_TCL_R1_SM_STATES_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_SM_STATES_IX_1_ADDR(x), mask, val, HWIO_TCL_R1_SM_STATES_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_SM_STATES_IX_1_DSCP_TABLE_ACC_BMSK 0x00038000 +#define HWIO_TCL_R1_SM_STATES_IX_1_DSCP_TABLE_ACC_SHFT 0xf + +#define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_BMSK 0x00007000 +#define HWIO_TCL_R1_SM_STATES_IX_1_PROD_CTRL_SHFT 0xc + +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS2_BMSK 0x00000e00 +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS2_SHFT 0x9 + +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS1_BMSK 0x000001c0 +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL_STATUS1_SHFT 0x6 + +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL2FW_BMSK 0x00000038 +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL2FW_SHFT 0x3 + +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL2TQM_BMSK 0x00000007 +#define HWIO_TCL_R1_SM_STATES_IX_1_TCL2TQM_SHFT 0x0 + +//// Register TCL_R1_TESTBUS_CTRL_0 //// + +#define HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x) (x+0x0000100c) +#define HWIO_TCL_R1_TESTBUS_CTRL_0_PHYS(x) (x+0x0000100c) +#define HWIO_TCL_R1_TESTBUS_CTRL_0_RMSK 0x3fffffff +#define HWIO_TCL_R1_TESTBUS_CTRL_0_SHFT 0 +#define HWIO_TCL_R1_TESTBUS_CTRL_0_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), HWIO_TCL_R1_TESTBUS_CTRL_0_RMSK) +#define HWIO_TCL_R1_TESTBUS_CTRL_0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), mask) +#define HWIO_TCL_R1_TESTBUS_CTRL_0_OUT(x, val) \ + out_dword( HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), val) +#define HWIO_TCL_R1_TESTBUS_CTRL_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_CTRL_0_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_CTRL_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_TESTBUS_CTRL_0_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_BMSK 0x20000000 +#define HWIO_TCL_R1_TESTBUS_CTRL_0_HW_ERROR_INTERRUPT_TESTBUS_OVERWRITE_SHFT 0x1d + +#define HWIO_TCL_R1_TESTBUS_CTRL_0_TCL_MAIN_SELECT_BMSK 0x1f800000 +#define HWIO_TCL_R1_TESTBUS_CTRL_0_TCL_MAIN_SELECT_SHFT 0x17 + +#define HWIO_TCL_R1_TESTBUS_CTRL_0_GXI_SELECT_BMSK 0x007c0000 +#define HWIO_TCL_R1_TESTBUS_CTRL_0_GXI_SELECT_SHFT 0x12 + +#define HWIO_TCL_R1_TESTBUS_CTRL_0_FSE_SELECT_BMSK 0x0003c000 +#define HWIO_TCL_R1_TESTBUS_CTRL_0_FSE_SELECT_SHFT 0xe + +#define HWIO_TCL_R1_TESTBUS_CTRL_0_ASE_SELECT_BMSK 0x00003c00 +#define HWIO_TCL_R1_TESTBUS_CTRL_0_ASE_SELECT_SHFT 0xa + +#define HWIO_TCL_R1_TESTBUS_CTRL_0_PARSER_SELECT_BMSK 0x000003e0 +#define HWIO_TCL_R1_TESTBUS_CTRL_0_PARSER_SELECT_SHFT 0x5 + +#define HWIO_TCL_R1_TESTBUS_CTRL_0_CCE_SELECT_BMSK 0x0000001f +#define HWIO_TCL_R1_TESTBUS_CTRL_0_CCE_SELECT_SHFT 0x0 + +//// Register TCL_R1_TESTBUS_LOW //// + +#define HWIO_TCL_R1_TESTBUS_LOW_ADDR(x) (x+0x00001010) +#define HWIO_TCL_R1_TESTBUS_LOW_PHYS(x) (x+0x00001010) +#define HWIO_TCL_R1_TESTBUS_LOW_RMSK 0xffffffff +#define HWIO_TCL_R1_TESTBUS_LOW_SHFT 0 +#define HWIO_TCL_R1_TESTBUS_LOW_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), HWIO_TCL_R1_TESTBUS_LOW_RMSK) +#define HWIO_TCL_R1_TESTBUS_LOW_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), mask) +#define HWIO_TCL_R1_TESTBUS_LOW_OUT(x, val) \ + out_dword( HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), val) +#define HWIO_TCL_R1_TESTBUS_LOW_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_LOW_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_LOW_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_TESTBUS_LOW_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_TESTBUS_LOW_VAL_SHFT 0x0 + +//// Register TCL_R1_TESTBUS_HIGH //// + +#define HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x) (x+0x00001014) +#define HWIO_TCL_R1_TESTBUS_HIGH_PHYS(x) (x+0x00001014) +#define HWIO_TCL_R1_TESTBUS_HIGH_RMSK 0x000000ff +#define HWIO_TCL_R1_TESTBUS_HIGH_SHFT 0 +#define HWIO_TCL_R1_TESTBUS_HIGH_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), HWIO_TCL_R1_TESTBUS_HIGH_RMSK) +#define HWIO_TCL_R1_TESTBUS_HIGH_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), mask) +#define HWIO_TCL_R1_TESTBUS_HIGH_OUT(x, val) \ + out_dword( HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), val) +#define HWIO_TCL_R1_TESTBUS_HIGH_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_TESTBUS_HIGH_ADDR(x), mask, val, HWIO_TCL_R1_TESTBUS_HIGH_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_TESTBUS_HIGH_VAL_BMSK 0x000000ff +#define HWIO_TCL_R1_TESTBUS_HIGH_VAL_SHFT 0x0 + +//// Register TCL_R1_EVENTMASK_IX_0 //// + +#define HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x) (x+0x00001018) +#define HWIO_TCL_R1_EVENTMASK_IX_0_PHYS(x) (x+0x00001018) +#define HWIO_TCL_R1_EVENTMASK_IX_0_RMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_0_SHFT 0 +#define HWIO_TCL_R1_EVENTMASK_IX_0_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_0_RMSK) +#define HWIO_TCL_R1_EVENTMASK_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), mask) +#define HWIO_TCL_R1_EVENTMASK_IX_0_OUT(x, val) \ + out_dword( HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), val) +#define HWIO_TCL_R1_EVENTMASK_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_EVENTMASK_IX_0_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_0_VAL_SHFT 0x0 + +//// Register TCL_R1_EVENTMASK_IX_1 //// + +#define HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x) (x+0x0000101c) +#define HWIO_TCL_R1_EVENTMASK_IX_1_PHYS(x) (x+0x0000101c) +#define HWIO_TCL_R1_EVENTMASK_IX_1_RMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_1_SHFT 0 +#define HWIO_TCL_R1_EVENTMASK_IX_1_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_1_RMSK) +#define HWIO_TCL_R1_EVENTMASK_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), mask) +#define HWIO_TCL_R1_EVENTMASK_IX_1_OUT(x, val) \ + out_dword( HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), val) +#define HWIO_TCL_R1_EVENTMASK_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_EVENTMASK_IX_1_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_1_VAL_SHFT 0x0 + +//// Register TCL_R1_EVENTMASK_IX_2 //// + +#define HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x) (x+0x00001020) +#define HWIO_TCL_R1_EVENTMASK_IX_2_PHYS(x) (x+0x00001020) +#define HWIO_TCL_R1_EVENTMASK_IX_2_RMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_2_SHFT 0 +#define HWIO_TCL_R1_EVENTMASK_IX_2_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_2_RMSK) +#define HWIO_TCL_R1_EVENTMASK_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), mask) +#define HWIO_TCL_R1_EVENTMASK_IX_2_OUT(x, val) \ + out_dword( HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), val) +#define HWIO_TCL_R1_EVENTMASK_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_2_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_EVENTMASK_IX_2_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_2_VAL_SHFT 0x0 + +//// Register TCL_R1_EVENTMASK_IX_3 //// + +#define HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x) (x+0x00001024) +#define HWIO_TCL_R1_EVENTMASK_IX_3_PHYS(x) (x+0x00001024) +#define HWIO_TCL_R1_EVENTMASK_IX_3_RMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_3_SHFT 0 +#define HWIO_TCL_R1_EVENTMASK_IX_3_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), HWIO_TCL_R1_EVENTMASK_IX_3_RMSK) +#define HWIO_TCL_R1_EVENTMASK_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), mask) +#define HWIO_TCL_R1_EVENTMASK_IX_3_OUT(x, val) \ + out_dword( HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), val) +#define HWIO_TCL_R1_EVENTMASK_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_EVENTMASK_IX_3_ADDR(x), mask, val, HWIO_TCL_R1_EVENTMASK_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_EVENTMASK_IX_3_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_EVENTMASK_IX_3_VAL_SHFT 0x0 + +//// Register TCL_R1_REG_ACCESS_EVENT_GEN_CTRL //// + +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) (x+0x00001028) +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) (x+0x00001028) +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_SHFT 0 +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK) +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask) +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, val) \ + out_dword( HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), val) +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask, val, HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 0x11 + +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x0001fffc +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 0x2 + +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x00000002 +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 0x1 + +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x00000001 +#define HWIO_TCL_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0x0 + +//// Register TCL_R1_SPARE_REGISTER //// + +#define HWIO_TCL_R1_SPARE_REGISTER_ADDR(x) (x+0x0000102c) +#define HWIO_TCL_R1_SPARE_REGISTER_PHYS(x) (x+0x0000102c) +#define HWIO_TCL_R1_SPARE_REGISTER_RMSK 0xffffffff +#define HWIO_TCL_R1_SPARE_REGISTER_SHFT 0 +#define HWIO_TCL_R1_SPARE_REGISTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_SPARE_REGISTER_ADDR(x), HWIO_TCL_R1_SPARE_REGISTER_RMSK) +#define HWIO_TCL_R1_SPARE_REGISTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_SPARE_REGISTER_ADDR(x), mask) +#define HWIO_TCL_R1_SPARE_REGISTER_OUT(x, val) \ + out_dword( HWIO_TCL_R1_SPARE_REGISTER_ADDR(x), val) +#define HWIO_TCL_R1_SPARE_REGISTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_SPARE_REGISTER_ADDR(x), mask, val, HWIO_TCL_R1_SPARE_REGISTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_SPARE_REGISTER_TCL_SPARE_FIELD_32_BMSK 0xffffffff +#define HWIO_TCL_R1_SPARE_REGISTER_TCL_SPARE_FIELD_32_SHFT 0x0 + +//// Register TCL_R1_END_OF_TEST_CHECK //// + +#define HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x) (x+0x00001030) +#define HWIO_TCL_R1_END_OF_TEST_CHECK_PHYS(x) (x+0x00001030) +#define HWIO_TCL_R1_END_OF_TEST_CHECK_RMSK 0x00000001 +#define HWIO_TCL_R1_END_OF_TEST_CHECK_SHFT 0 +#define HWIO_TCL_R1_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_END_OF_TEST_CHECK_RMSK) +#define HWIO_TCL_R1_END_OF_TEST_CHECK_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), mask) +#define HWIO_TCL_R1_END_OF_TEST_CHECK_OUT(x, val) \ + out_dword( HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), val) +#define HWIO_TCL_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_END_OF_TEST_CHECK_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 +#define HWIO_TCL_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 + +//// Register TCL_R1_ASE_END_OF_TEST_CHECK //// + +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x) (x+0x00001034) +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_PHYS(x) (x+0x00001034) +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_RMSK 0x00000001 +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_SHFT 0 +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_RMSK) +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), mask) +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_OUT(x, val) \ + out_dword( HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), val) +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 +#define HWIO_TCL_R1_ASE_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 + +//// Register TCL_R1_ASE_DEBUG_CLEAR_COUNTERS //// + +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x) (x+0x00001038) +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_PHYS(x) (x+0x00001038) +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_RMSK 0x00000001 +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_SHFT 0 +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_RMSK) +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask) +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_OUT(x, val) \ + out_dword( HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), val) +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_EN_BMSK 0x00000001 +#define HWIO_TCL_R1_ASE_DEBUG_CLEAR_COUNTERS_EN_SHFT 0x0 + +//// Register TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER //// + +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x) (x+0x0000103c) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_PHYS(x) (x+0x0000103c) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_SHFT 0 +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_RMSK) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), val) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_CACHE_HITS_COUNTER_VAL_SHFT 0x0 + +//// Register TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER //// + +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x) (x+0x00001040) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_PHYS(x) (x+0x00001040) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_SHFT 0 +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_RMSK) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), val) +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_ASE_DEBUG_NUM_SEARCHES_COUNTER_VAL_SHFT 0x0 + +//// Register TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER //// + +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x) (x+0x00001044) +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PHYS(x) (x+0x00001044) +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK 0x000fffff +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_SHFT 0 +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_RMSK) +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), val) +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_BMSK 0x000ffc00 +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_PEAK_SHFT 0xa + +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_BMSK 0x000003ff +#define HWIO_TCL_R1_ASE_DEBUG_CACHE_OCCUPANCY_COUNTER_CURR_SHFT 0x0 + +//// Register TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER //// + +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x) (x+0x00001048) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PHYS(x) (x+0x00001048) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_RMSK 0x03ffffff +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SHFT 0 +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_RMSK) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_OUT(x, val) \ + out_dword( HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), val) +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_ADDR(x), mask, val, HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_BMSK 0x03fffc00 +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_SQUARE_OCCUPANCY_SHFT 0xa + +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_BMSK 0x000003e0 +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_PEAK_NUM_SEARCH_PENDING_SHFT 0x5 + +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_BMSK 0x0000001f +#define HWIO_TCL_R1_ASE_DEBUG_SEARCH_STAT_COUNTER_NUM_SEARCH_PENDING_SHFT 0x0 + +//// Register TCL_R1_ASE_SM_STATES //// + +#define HWIO_TCL_R1_ASE_SM_STATES_ADDR(x) (x+0x0000104c) +#define HWIO_TCL_R1_ASE_SM_STATES_PHYS(x) (x+0x0000104c) +#define HWIO_TCL_R1_ASE_SM_STATES_RMSK 0x003fff0f +#define HWIO_TCL_R1_ASE_SM_STATES_SHFT 0 +#define HWIO_TCL_R1_ASE_SM_STATES_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), HWIO_TCL_R1_ASE_SM_STATES_RMSK) +#define HWIO_TCL_R1_ASE_SM_STATES_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), mask) +#define HWIO_TCL_R1_ASE_SM_STATES_OUT(x, val) \ + out_dword( HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), val) +#define HWIO_TCL_R1_ASE_SM_STATES_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_SM_STATES_ADDR(x), mask, val, HWIO_TCL_R1_ASE_SM_STATES_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_ASE_SM_STATES_GSE_CTRL_STATE_BMSK 0x00300000 +#define HWIO_TCL_R1_ASE_SM_STATES_GSE_CTRL_STATE_SHFT 0x14 + +#define HWIO_TCL_R1_ASE_SM_STATES_CACHE_CHK_STATE_BMSK 0x000c0000 +#define HWIO_TCL_R1_ASE_SM_STATES_CACHE_CHK_STATE_SHFT 0x12 + +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS1_STATE_BMSK 0x00030000 +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS1_STATE_SHFT 0x10 + +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS2_STATE_BMSK 0x0000c000 +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_ISS2_STATE_SHFT 0xe + +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP1_STATE_BMSK 0x00003800 +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP1_STATE_SHFT 0xb + +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP2_STATE_BMSK 0x00000700 +#define HWIO_TCL_R1_ASE_SM_STATES_MEM_RESP2_STATE_SHFT 0x8 + +#define HWIO_TCL_R1_ASE_SM_STATES_APP_RETURN_STATE_BMSK 0x0000000f +#define HWIO_TCL_R1_ASE_SM_STATES_APP_RETURN_STATE_SHFT 0x0 + +//// Register TCL_R1_ASE_CACHE_DEBUG //// + +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x) (x+0x00001050) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_PHYS(x) (x+0x00001050) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_RMSK 0x000003ff +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_SHFT 0 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), HWIO_TCL_R1_ASE_CACHE_DEBUG_RMSK) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), mask) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_OUT(x, val) \ + out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), val) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ADDR(x), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_READ_IDX_BMSK 0x000003ff +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_READ_IDX_SHFT 0x0 + +//// Register TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS //// + +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x) (x+0x00001054) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_PHYS(x) (x+0x00001054) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_RMSK 0x007fffff +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_SHFT 0 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_IN(x) \ + in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_RMSK) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_OUT(x, val) \ + out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), val) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_ADDR(x), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_BMSK 0x007ffff8 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_GST_IDX_SHFT 0x3 + +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_BMSK 0x00000004 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_CACHE_ONLY_SHFT 0x2 + +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_DIRTY_BMSK 0x00000002 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_DIRTY_SHFT 0x1 + +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_VALID_BMSK 0x00000001 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_STATS_VALID_SHFT 0x0 + +//// Register TCL_R1_ASE_CACHE_DEBUG_ENTRY_n //// + +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n) (base+0x1058+0x4*n) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_PHYS(base, n) (base+0x1058+0x4*n) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_RMSK 0xffffffff +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_SHFT 0 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_MAXn 31 +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INI(base, n) \ + in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_RMSK) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INMI(base, n, mask) \ + in_dword_masked ( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_OUTI(base, n, val) \ + out_dword( HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), val) +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_OUTMI(base, n, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_ADDR(base, n), mask, val, HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_INI(base, n)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_VAL_BMSK 0xffffffff +#define HWIO_TCL_R1_ASE_CACHE_DEBUG_ENTRY_n_VAL_SHFT 0x0 + +//// Register TCL_R2_SW2TCL1_RING_HP //// + +#define HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x) (x+0x00002000) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_PHYS(x) (x+0x00002000) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_RMSK 0x000fffff +#define HWIO_TCL_R2_SW2TCL1_RING_HP_SHFT 0 +#define HWIO_TCL_R2_SW2TCL1_RING_HP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL1_RING_HP_RMSK) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), mask) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), val) +#define HWIO_TCL_R2_SW2TCL1_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL1_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_SW2TCL1_RING_HP_HEAD_PTR_BMSK 0x000fffff +#define HWIO_TCL_R2_SW2TCL1_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register TCL_R2_SW2TCL1_RING_TP //// + +#define HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x) (x+0x00002004) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_PHYS(x) (x+0x00002004) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_RMSK 0x000fffff +#define HWIO_TCL_R2_SW2TCL1_RING_TP_SHFT 0 +#define HWIO_TCL_R2_SW2TCL1_RING_TP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL1_RING_TP_RMSK) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), mask) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), val) +#define HWIO_TCL_R2_SW2TCL1_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL1_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_SW2TCL1_RING_TP_TAIL_PTR_BMSK 0x000fffff +#define HWIO_TCL_R2_SW2TCL1_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R2_SW2TCL2_RING_HP //// + +#define HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x) (x+0x00002008) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_PHYS(x) (x+0x00002008) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_RMSK 0x000fffff +#define HWIO_TCL_R2_SW2TCL2_RING_HP_SHFT 0 +#define HWIO_TCL_R2_SW2TCL2_RING_HP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL2_RING_HP_RMSK) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), mask) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), val) +#define HWIO_TCL_R2_SW2TCL2_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL2_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_SW2TCL2_RING_HP_HEAD_PTR_BMSK 0x000fffff +#define HWIO_TCL_R2_SW2TCL2_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register TCL_R2_SW2TCL2_RING_TP //// + +#define HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x) (x+0x0000200c) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_PHYS(x) (x+0x0000200c) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_RMSK 0x000fffff +#define HWIO_TCL_R2_SW2TCL2_RING_TP_SHFT 0 +#define HWIO_TCL_R2_SW2TCL2_RING_TP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL2_RING_TP_RMSK) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), mask) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), val) +#define HWIO_TCL_R2_SW2TCL2_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL2_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL2_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_SW2TCL2_RING_TP_TAIL_PTR_BMSK 0x000fffff +#define HWIO_TCL_R2_SW2TCL2_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R2_SW2TCL3_RING_HP //// + +#define HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x) (x+0x00002010) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_PHYS(x) (x+0x00002010) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_RMSK 0x000fffff +#define HWIO_TCL_R2_SW2TCL3_RING_HP_SHFT 0 +#define HWIO_TCL_R2_SW2TCL3_RING_HP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL3_RING_HP_RMSK) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), mask) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), val) +#define HWIO_TCL_R2_SW2TCL3_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL3_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL3_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_SW2TCL3_RING_HP_HEAD_PTR_BMSK 0x000fffff +#define HWIO_TCL_R2_SW2TCL3_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register TCL_R2_SW2TCL3_RING_TP //// + +#define HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x) (x+0x00002014) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_PHYS(x) (x+0x00002014) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_RMSK 0x000fffff +#define HWIO_TCL_R2_SW2TCL3_RING_TP_SHFT 0 +#define HWIO_TCL_R2_SW2TCL3_RING_TP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL3_RING_TP_RMSK) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), mask) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), val) +#define HWIO_TCL_R2_SW2TCL3_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL3_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL3_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_SW2TCL3_RING_TP_TAIL_PTR_BMSK 0x000fffff +#define HWIO_TCL_R2_SW2TCL3_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R2_SW2TCL_CREDIT_RING_HP //// + +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x) (x+0x00002018) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_PHYS(x) (x+0x00002018) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_RMSK 0x000fffff +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_SHFT 0 +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x), HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_RMSK) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x), mask) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x), val) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_HEAD_PTR_BMSK 0x000fffff +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register TCL_R2_SW2TCL_CREDIT_RING_TP //// + +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x) (x+0x0000201c) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_PHYS(x) (x+0x0000201c) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_RMSK 0x000fffff +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_SHFT 0 +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x), HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_RMSK) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x), mask) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x), val) +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_TAIL_PTR_BMSK 0x000fffff +#define HWIO_TCL_R2_SW2TCL_CREDIT_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R2_FW2TCL1_RING_HP //// + +#define HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x) (x+0x00002020) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_PHYS(x) (x+0x00002020) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_RMSK 0x0000ffff +#define HWIO_TCL_R2_FW2TCL1_RING_HP_SHFT 0 +#define HWIO_TCL_R2_FW2TCL1_RING_HP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), HWIO_TCL_R2_FW2TCL1_RING_HP_RMSK) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), mask) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), val) +#define HWIO_TCL_R2_FW2TCL1_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_FW2TCL1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_FW2TCL1_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_FW2TCL1_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_FW2TCL1_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register TCL_R2_FW2TCL1_RING_TP //// + +#define HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x) (x+0x00002024) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_PHYS(x) (x+0x00002024) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_RMSK 0x0000ffff +#define HWIO_TCL_R2_FW2TCL1_RING_TP_SHFT 0 +#define HWIO_TCL_R2_FW2TCL1_RING_TP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), HWIO_TCL_R2_FW2TCL1_RING_TP_RMSK) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), mask) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), val) +#define HWIO_TCL_R2_FW2TCL1_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_FW2TCL1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_FW2TCL1_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_FW2TCL1_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_FW2TCL1_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R2_TCL2TQM_RING_HP //// + +#define HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x) (x+0x00002028) +#define HWIO_TCL_R2_TCL2TQM_RING_HP_PHYS(x) (x+0x00002028) +#define HWIO_TCL_R2_TCL2TQM_RING_HP_RMSK 0x0000ffff +#define HWIO_TCL_R2_TCL2TQM_RING_HP_SHFT 0 +#define HWIO_TCL_R2_TCL2TQM_RING_HP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), HWIO_TCL_R2_TCL2TQM_RING_HP_RMSK) +#define HWIO_TCL_R2_TCL2TQM_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), mask) +#define HWIO_TCL_R2_TCL2TQM_RING_HP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), val) +#define HWIO_TCL_R2_TCL2TQM_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_TCL2TQM_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2TQM_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_TCL2TQM_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_TCL2TQM_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register TCL_R2_TCL2TQM_RING_TP //// + +#define HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x) (x+0x0000202c) +#define HWIO_TCL_R2_TCL2TQM_RING_TP_PHYS(x) (x+0x0000202c) +#define HWIO_TCL_R2_TCL2TQM_RING_TP_RMSK 0x0000ffff +#define HWIO_TCL_R2_TCL2TQM_RING_TP_SHFT 0 +#define HWIO_TCL_R2_TCL2TQM_RING_TP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), HWIO_TCL_R2_TCL2TQM_RING_TP_RMSK) +#define HWIO_TCL_R2_TCL2TQM_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), mask) +#define HWIO_TCL_R2_TCL2TQM_RING_TP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), val) +#define HWIO_TCL_R2_TCL2TQM_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_TCL2TQM_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2TQM_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_TCL2TQM_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_TCL2TQM_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R2_TCL_STATUS1_RING_HP //// + +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x) (x+0x00002030) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_PHYS(x) (x+0x00002030) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_RMSK 0x0000ffff +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_SHFT 0 +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), HWIO_TCL_R2_TCL_STATUS1_RING_HP_RMSK) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), mask) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), val) +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS1_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_TCL_STATUS1_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register TCL_R2_TCL_STATUS1_RING_TP //// + +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x) (x+0x00002034) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_PHYS(x) (x+0x00002034) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_RMSK 0x0000ffff +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_SHFT 0 +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), HWIO_TCL_R2_TCL_STATUS1_RING_TP_RMSK) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), mask) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), val) +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS1_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS1_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_TCL_STATUS1_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R2_TCL_STATUS2_RING_HP //// + +#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x) (x+0x00002038) +#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_PHYS(x) (x+0x00002038) +#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_RMSK 0x0000ffff +#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_SHFT 0 +#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), HWIO_TCL_R2_TCL_STATUS2_RING_HP_RMSK) +#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), mask) +#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), val) +#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS2_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS2_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_TCL_STATUS2_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register TCL_R2_TCL_STATUS2_RING_TP //// + +#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x) (x+0x0000203c) +#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_PHYS(x) (x+0x0000203c) +#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_RMSK 0x0000ffff +#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_SHFT 0 +#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), HWIO_TCL_R2_TCL_STATUS2_RING_TP_RMSK) +#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), mask) +#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), val) +#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_TCL_STATUS2_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL_STATUS2_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_TCL_STATUS2_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register TCL_R2_TCL2FW_RING_HP //// + +#define HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x) (x+0x00002040) +#define HWIO_TCL_R2_TCL2FW_RING_HP_PHYS(x) (x+0x00002040) +#define HWIO_TCL_R2_TCL2FW_RING_HP_RMSK 0x0000ffff +#define HWIO_TCL_R2_TCL2FW_RING_HP_SHFT 0 +#define HWIO_TCL_R2_TCL2FW_RING_HP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), HWIO_TCL_R2_TCL2FW_RING_HP_RMSK) +#define HWIO_TCL_R2_TCL2FW_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), mask) +#define HWIO_TCL_R2_TCL2FW_RING_HP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), val) +#define HWIO_TCL_R2_TCL2FW_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_TCL2FW_RING_HP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2FW_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_TCL2FW_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_TCL2FW_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register TCL_R2_TCL2FW_RING_TP //// + +#define HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x) (x+0x00002044) +#define HWIO_TCL_R2_TCL2FW_RING_TP_PHYS(x) (x+0x00002044) +#define HWIO_TCL_R2_TCL2FW_RING_TP_RMSK 0x0000ffff +#define HWIO_TCL_R2_TCL2FW_RING_TP_SHFT 0 +#define HWIO_TCL_R2_TCL2FW_RING_TP_IN(x) \ + in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), HWIO_TCL_R2_TCL2FW_RING_TP_RMSK) +#define HWIO_TCL_R2_TCL2FW_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), mask) +#define HWIO_TCL_R2_TCL2FW_RING_TP_OUT(x, val) \ + out_dword( HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), val) +#define HWIO_TCL_R2_TCL2FW_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_TCL_R2_TCL2FW_RING_TP_ADDR(x), mask, val, HWIO_TCL_R2_TCL2FW_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_TCL_R2_TCL2FW_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_TCL_R2_TCL2FW_RING_TP_TAIL_PTR_SHFT 0x0 + + +#endif + diff --git a/drivers/staging/fw-api/hw/qca6750/v1/macrx_abort_request_info.h b/drivers/staging/fw-api/hw/qca6750/v1/macrx_abort_request_info.h new file mode 100644 index 000000000000..ba8e76745b65 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/macrx_abort_request_info.h @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _MACRX_ABORT_REQUEST_INFO_H_ +#define _MACRX_ABORT_REQUEST_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 macrx_abort_reason[7:0], reserved_0[15:8] +// +// ################ END SUMMARY ################# + +#define NUM_OF_WORDS_MACRX_ABORT_REQUEST_INFO 1 + +struct macrx_abort_request_info { + uint16_t macrx_abort_reason : 8, //[7:0] + reserved_0 : 8; //[15:8] +}; + +/* + +macrx_abort_reason + + + + Upon receiving this + abort reason, PHY should stop reception of the current frame + and go back into a search mode + + + + MAC FW + issued an abort for channel switch reasons + + MAC FW + issued an abort power save reasons + + RXPCU is + terminating the current ongoing reception, as the data that + MAC is receiving seems to be all garbage... The PER is too + high, or in case of MU UL, Likely the trigger frame never + got properly received by any of the targeted MU UL devices. + After the abort, PHYRX can resume a normal search mode. + + + + + +reserved_0 + + +*/ + + +/* Description MACRX_ABORT_REQUEST_INFO_0_MACRX_ABORT_REASON + + + + Upon receiving this + abort reason, PHY should stop reception of the current frame + and go back into a search mode + + + + MAC FW + issued an abort for channel switch reasons + + MAC FW + issued an abort power save reasons + + RXPCU is + terminating the current ongoing reception, as the data that + MAC is receiving seems to be all garbage... The PER is too + high, or in case of MU UL, Likely the trigger frame never + got properly received by any of the targeted MU UL devices. + After the abort, PHYRX can resume a normal search mode. + + + + +*/ +#define MACRX_ABORT_REQUEST_INFO_0_MACRX_ABORT_REASON_OFFSET 0x00000000 +#define MACRX_ABORT_REQUEST_INFO_0_MACRX_ABORT_REASON_LSB 0 +#define MACRX_ABORT_REQUEST_INFO_0_MACRX_ABORT_REASON_MASK 0x000000ff + +/* Description MACRX_ABORT_REQUEST_INFO_0_RESERVED_0 + + +*/ +#define MACRX_ABORT_REQUEST_INFO_0_RESERVED_0_OFFSET 0x00000000 +#define MACRX_ABORT_REQUEST_INFO_0_RESERVED_0_LSB 8 +#define MACRX_ABORT_REQUEST_INFO_0_RESERVED_0_MASK 0x0000ff00 + + +#endif // _MACRX_ABORT_REQUEST_INFO_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/phyrx_abort_request_info.h b/drivers/staging/fw-api/hw/qca6750/v1/phyrx_abort_request_info.h new file mode 100644 index 000000000000..e12dad34dbc8 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/phyrx_abort_request_info.h @@ -0,0 +1,420 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _PHYRX_ABORT_REQUEST_INFO_H_ +#define _PHYRX_ABORT_REQUEST_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 phyrx_abort_reason[7:0], phy_enters_nap_state[8], phy_enters_defer_state[9], reserved_0[15:10], receive_duration[31:16] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_PHYRX_ABORT_REQUEST_INFO 1 + +struct phyrx_abort_request_info { + uint32_t phyrx_abort_reason : 8, //[7:0] + phy_enters_nap_state : 1, //[8] + phy_enters_defer_state : 1, //[9] + reserved_0 : 6, //[15:10] + receive_duration : 16; //[31:16] +}; + +/* + +phyrx_abort_reason + + Reception aborted due to + receiving a PHY_OFF TLV + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Should not really be used. If + needed, ask for documentation update + + + + + + + + + + + + + + + +phy_enters_nap_state + + When set, PHY enters PHY NAP state after sending this + abort + + + + Note that nap and defer state are mutually exclusive. + + + + Field put pro-actively in place....usage still to be + agreed upon. + + + +phy_enters_defer_state + + When set, PHY enters PHY defer state after sending this + abort + + + + Note that nap and defer state are mutually exclusive. + + + + Field put pro-actively in place....usage still to be + agreed upon. + + + +reserved_0 + + + +receive_duration + + The remaining receive duration of this PPDU in the + medium (in us). When PHY does not know this duration when + this TLV is generated, the field will be set to 0. + + The timing reference point is the reception by the MAC + of this TLV. The value shall be accurate to within 2us. + + + + In case Phy_enters_nap_state and/or + Phy_enters_defer_state is set, there is a possibility that + MAC PMM can also decide to go into a low(er) power state. + + +*/ + + +/* Description PHYRX_ABORT_REQUEST_INFO_0_PHYRX_ABORT_REASON + + Reception aborted due to + receiving a PHY_OFF TLV + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Should not really be used. If + needed, ask for documentation update + + + + + + + + + + + + + + +*/ +#define PHYRX_ABORT_REQUEST_INFO_0_PHYRX_ABORT_REASON_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_0_PHYRX_ABORT_REASON_LSB 0 +#define PHYRX_ABORT_REQUEST_INFO_0_PHYRX_ABORT_REASON_MASK 0x000000ff + +/* Description PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_NAP_STATE + + When set, PHY enters PHY NAP state after sending this + abort + + + + Note that nap and defer state are mutually exclusive. + + + + Field put pro-actively in place....usage still to be + agreed upon. + + +*/ +#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_NAP_STATE_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_NAP_STATE_LSB 8 +#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_NAP_STATE_MASK 0x00000100 + +/* Description PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_DEFER_STATE + + When set, PHY enters PHY defer state after sending this + abort + + + + Note that nap and defer state are mutually exclusive. + + + + Field put pro-actively in place....usage still to be + agreed upon. + + +*/ +#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_DEFER_STATE_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_DEFER_STATE_LSB 9 +#define PHYRX_ABORT_REQUEST_INFO_0_PHY_ENTERS_DEFER_STATE_MASK 0x00000200 + +/* Description PHYRX_ABORT_REQUEST_INFO_0_RESERVED_0 + + +*/ +#define PHYRX_ABORT_REQUEST_INFO_0_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_0_RESERVED_0_LSB 10 +#define PHYRX_ABORT_REQUEST_INFO_0_RESERVED_0_MASK 0x0000fc00 + +/* Description PHYRX_ABORT_REQUEST_INFO_0_RECEIVE_DURATION + + The remaining receive duration of this PPDU in the + medium (in us). When PHY does not know this duration when + this TLV is generated, the field will be set to 0. + + The timing reference point is the reception by the MAC + of this TLV. The value shall be accurate to within 2us. + + + + In case Phy_enters_nap_state and/or + Phy_enters_defer_state is set, there is a possibility that + MAC PMM can also decide to go into a low(er) power state. + + +*/ +#define PHYRX_ABORT_REQUEST_INFO_0_RECEIVE_DURATION_OFFSET 0x00000000 +#define PHYRX_ABORT_REQUEST_INFO_0_RECEIVE_DURATION_LSB 16 +#define PHYRX_ABORT_REQUEST_INFO_0_RECEIVE_DURATION_MASK 0xffff0000 + + +#endif // _PHYRX_ABORT_REQUEST_INFO_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/phyrx_common_user_info.h b/drivers/staging/fw-api/hw/qca6750/v1/phyrx_common_user_info.h new file mode 100644 index 000000000000..7816fba1722b --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/phyrx_common_user_info.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _PHYRX_COMMON_USER_INFO_H_ +#define _PHYRX_COMMON_USER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 receive_duration[15:0], reserved_0a[31:16] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_PHYRX_COMMON_USER_INFO 1 + +struct phyrx_common_user_info { + uint32_t receive_duration : 16, //[15:0] + reserved_0a : 16; //[31:16] +}; + +/* + +receive_duration + + The remaining receive duration of this PPDU in the + medium (in us). + + The timing reference point is the reception by the MAC + of this TLV. The value shall be accurate to within 2us + + + +reserved_0a + + +*/ + + +/* Description PHYRX_COMMON_USER_INFO_0_RECEIVE_DURATION + + The remaining receive duration of this PPDU in the + medium (in us). + + The timing reference point is the reception by the MAC + of this TLV. The value shall be accurate to within 2us + + +*/ +#define PHYRX_COMMON_USER_INFO_0_RECEIVE_DURATION_OFFSET 0x00000000 +#define PHYRX_COMMON_USER_INFO_0_RECEIVE_DURATION_LSB 0 +#define PHYRX_COMMON_USER_INFO_0_RECEIVE_DURATION_MASK 0x0000ffff + +/* Description PHYRX_COMMON_USER_INFO_0_RESERVED_0A + + +*/ +#define PHYRX_COMMON_USER_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_COMMON_USER_INFO_0_RESERVED_0A_LSB 16 +#define PHYRX_COMMON_USER_INFO_0_RESERVED_0A_MASK 0xffff0000 + + +#endif // _PHYRX_COMMON_USER_INFO_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/phyrx_he_sig_a_mu_dl.h b/drivers/staging/fw-api/hw/qca6750/v1/phyrx_he_sig_a_mu_dl.h new file mode 100644 index 000000000000..a7a608e73b76 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/phyrx_he_sig_a_mu_dl.h @@ -0,0 +1,412 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _PHYRX_HE_SIG_A_MU_DL_H_ +#define _PHYRX_HE_SIG_A_MU_DL_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_mu_dl_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_DL 2 + +struct phyrx_he_sig_a_mu_dl { + struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details; +}; + +/* + +struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details + + See detailed description of the STRUCT +*/ + + + /* EXTERNAL REFERENCE : struct he_sig_a_mu_dl_info phyrx_he_sig_a_mu_dl_info_details */ + + +/* Description PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG + + Differentiates between DL and UL transmission + + + + + + + + NOTE: This is unsupported for HE MU format (including + MU_SU) Tx in Napier and Hastings80. + + +*/ +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000001 + +/* Description PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B + + Indicates the MCS of HE-SIG-B + + +*/ +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x0000000e + +/* Description PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B + + Indicates whether dual sub-carrier modulation is applied + to HE-SIG-B + + + + 0: No DCM for HE_SIG_B + + 1: DCM for HE_SIG_B + + +*/ +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x00000010 + +/* Description PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID + + BSS color ID + + + + Field Used by MAC HW + + +*/ +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000007e0 + +/* Description PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE + + Spatial reuse + + + + For 20MHz one SR field corresponding to entire 20MHz + (other 3 fields indicate identical values) + + For 40MHz two SR fields for each 20MHz (other 2 fields + indicate identical values) + + For 80MHz four SR fields for each 20MHz + + For 160MHz four SR fields for each 40MHz + + +*/ +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00007800 + +/* Description PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW + + Bandwidth of the PPDU. + + + + 20 Mhz + + 40 Mhz + + 80 MHz non-preamble + puncturing mode + + 160 MHz and 80+80 MHz + non-preamble puncturing mode + + for preamble + puncturing in 80 MHz, where in the preamble only the + secondary 20 MHz is punctured + + for + preamble puncturing in 80 MHz, where in the preamble only + one of the two 20 MHz sub-channels in secondary 40 MHz is + punctured. + + for preamble + puncturing in 160 MHz or 80+80 MHz, where in the primary 80 + MHz of the preamble only the secondary 20 MHz is punctured. + + for + preamble puncturing in 160 MHz or 80+80 MHz, where in the + primary 80 MHz of the preamble the primary 40 MHz is + present. + + + + On RX side, Field Used by MAC HW + + +*/ +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x00038000 + +/* Description PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS + + Number of symbols + + + + For OFDMA, the actual number of symbols is 1 larger then + indicated in this field. + + + + For MU-MIMO this is equal to the number of users - 1: + the following encoding is used: + + 1 => 2 users + + 2 => 3 users + + Etc. + + + + +*/ +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x003c0000 + +/* Description PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B + + Indicates the compression mode of HE-SIG-B + + + + 0: Regular [uncomp mode] + + 1: compressed mode (full-BW MU-MIMO only) + + +*/ +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x00400000 + +/* Description PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE + + Indicates the CP and HE-LTF type + + + + 4xLTF + 0.8 us CP + + 2x LTF + 0.8 µs CP + + 2x LTF + 1.6 µs CP + + 4x LTF + 3.2 µs CP + + + + NOTE: for MU no proprietary modes (for now) + + + + +*/ +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x01800000 + +/* Description PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION + + 0: No Doppler support + + 1: Doppler support + + +*/ +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x02000000 + +/* Description PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A + + +*/ +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26 +#define PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0xfc000000 + +/* Description PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION + + Indicates the remaining time in the current TXOP + + + + Field Used by MAC HW + + +*/ +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 0 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f + +/* Description PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A + + Note: spec indicates this shall be set to 1 + + +*/ +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 7 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x00000080 + +/* Description PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS + + Indicates the number of HE-LTF symbols + + + + 0: 1 LTF + + 1: 2 LTFs + + 2: 4 LTFs + + 3: 6 LTFs + + 4: 8 LTFs + + + + +*/ +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 8 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x00000700 + +/* Description PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL + + If LDPC, + + 0: LDPC extra symbol not present + + 1: LDPC extra symbol present + + Else + + Set to 1 + + +*/ +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 11 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000800 + +/* Description PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC + + Indicates whether STBC is applied + + 0: No STBC + + 1: STBC + + +*/ +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 12 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x00001000 + +/* Description PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR + + the packet extension duration of the trigger-based PPDU + response with these two bits indicating the a-factor + + + + + + + + + + + + + + +*/ +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 13 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00006000 + +/* Description PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY + + the packet extension duration of the trigger-based PPDU + response with this bit indicating the PE-Disambiguity + + +*/ +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 15 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00008000 + +/* Description PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC + + CRC for HE-SIG-A contents. + + +*/ +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 16 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f0000 + +/* Description PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL + + +*/ +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 20 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f00000 + +/* Description PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B + + +*/ +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 26 +#define PHYRX_HE_SIG_A_MU_DL_1_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0xfc000000 + + +#endif // _PHYRX_HE_SIG_A_MU_DL_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/phyrx_he_sig_a_mu_ul.h b/drivers/staging/fw-api/hw/qca6750/v1/phyrx_he_sig_a_mu_ul.h new file mode 100644 index 000000000000..7de849819812 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/phyrx_he_sig_a_mu_ul.h @@ -0,0 +1,185 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _PHYRX_HE_SIG_A_MU_UL_H_ +#define _PHYRX_HE_SIG_A_MU_UL_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_mu_ul_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_MU_UL 2 + +struct phyrx_he_sig_a_mu_ul { + struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details; +}; + +/* + +struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details + + See detailed description of the STRUCT +*/ + + + /* EXTERNAL REFERENCE : struct he_sig_a_mu_ul_info phyrx_he_sig_a_mu_ul_info_details */ + + +/* Description PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION + + Indicates whether the transmission is SU PPDU or a + trigger based UL MU PDDU + + + + + + +*/ +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001 + +/* Description PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID + + BSS color ID + + +*/ +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000007e + +/* Description PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE + + Spatial reuse + + + + +*/ +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x007fff80 + +/* Description PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A + + Note: spec indicates this shall be set to 1 + + +*/ +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x00800000 + +/* Description PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW + + Bandwidth of the PPDU. + + + + 20 Mhz + + 40 Mhz + + 80 Mhz + + 160 MHz or 80+80 MHz + + + + On RX side, Field Used by MAC HW + + +*/ +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x03000000 + +/* Description PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B + + +*/ +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26 +#define PHYRX_HE_SIG_A_MU_UL_0_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000 + +/* Description PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION + + Indicates the remaining time in the current TXOP +*/ +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 0 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f + +/* Description PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A + + Set to value indicated in the trigger frame + + +*/ +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 7 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff80 + +/* Description PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC + + CRC for HE-SIG-A contents. + + This CRC may also cover some fields of L-SIG (TBD) + + +*/ +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 16 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f0000 + +/* Description PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL + + BCC encoding (similar to VHT-SIG-A) with 6 tail bits is + used + + +*/ +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 20 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f00000 + +/* Description PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B + + +*/ +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 26 +#define PHYRX_HE_SIG_A_MU_UL_1_PHYRX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0xfc000000 + + +#endif // _PHYRX_HE_SIG_A_MU_UL_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/phyrx_he_sig_a_su.h b/drivers/staging/fw-api/hw/qca6750/v1/phyrx_he_sig_a_su.h new file mode 100644 index 000000000000..b36bfd07324a --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/phyrx_he_sig_a_su.h @@ -0,0 +1,504 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _PHYRX_HE_SIG_A_SU_H_ +#define _PHYRX_HE_SIG_A_SU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_a_su_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct he_sig_a_su_info phyrx_he_sig_a_su_info_details; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_PHYRX_HE_SIG_A_SU 2 + +struct phyrx_he_sig_a_su { + struct he_sig_a_su_info phyrx_he_sig_a_su_info_details; +}; + +/* + +struct he_sig_a_su_info phyrx_he_sig_a_su_info_details + + See detailed description of the STRUCT +*/ + + + /* EXTERNAL REFERENCE : struct he_sig_a_su_info phyrx_he_sig_a_su_info_details */ + + +/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION + + + + + + +*/ +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x00000001 + +/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE + + Indicates whether spatial mapping is changed between + legacy and HE portion of preamble. If not, channel + estimation can include legacy preamble to improve accuracy + + +*/ +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x00000002 + +/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG + + Differentiates between DL and UL transmission + + + + + + + + +*/ +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x00000004 + +/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS + + Indicates the data MCS + + + + Field Used by MAC HW + + +*/ +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x00000078 + +/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM + + + 0: No DCM + + 1:DCM + + +*/ +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x00000080 + +/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID + + BSS color ID + + + + Field Used by MAC HW + + +*/ +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00003f00 + +/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A + + Note: spec indicates this shall be set to 1 + + +*/ +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x00004000 + +/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE + + Spatial reuse + + + + For 20MHz one SR field corresponding to entire 20MHz + (other 3 fields indicate identical values) + + For 40MHz two SR fields for each 20MHz (other 2 fields + indicate identical values) + + For 80MHz four SR fields for each 20MHz + + For 160MHz four SR fields for each 40MHz + + +*/ +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00078000 + +/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW + + Bandwidth of the PPDU. + + + + For HE SU PPDU + + + 20 Mhz + + 40 Mhz + + 80 Mhz + + 160 MHz or 80+80 MHz + + + + For HE Extended Range SU PPDU + + Set to 0 for 242-tone RU + Set to 1 for right 106-tone RU within the primary 20 MHz + + + + On RX side, Field Used by MAC HW + + +*/ +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x00180000 + +/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE + + Indicates the CP and HE-LTF type + + + + 1xLTF + 0.8 us CP (See note for + proprietary mode) + + 2x LTF + 0.8 µs CP (See note + for proprietary mode) + + 2x LTF + 1.6 µs CP (See note + for proprietary mode) + + + + + + When DCM == 0 OR STBC == 0: 4x LTF + 3.2 µs CP + + When DCM == 1 AND STBC == 1: 4x LTF + 0.8 µs CP. Note: + In this scenario, Neither DCM nor STBC is applied to HE data + field. + + (See note for proprietary mode) + + + + NOTE: + + For QCA proprietary mode + + If ( DCM == 1 ) and ( MCS > 0 ) and (STBC == 0) + + 0 = 1xLTF + 0.4 usec + + 1 = 2xLTF + 0.4 usec + + 2~3 = Reserved + + + + +*/ +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x00600000 + +/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS + + + + + For HE SU PPDU + + + + For HE Extended Range PPDU + + +*/ +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x03800000 + +/* Description PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B + + +*/ +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26 +#define PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0xfc000000 + +/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION + + Indicates the remaining time in the current TXOP + + + + Field Used by MAC HW + + +*/ +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 0 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f + +/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING + + Distinguishes between BCC and LDPC coding. + + + + 0: BCC + + 1: LDPC + + +*/ +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 7 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x00000080 + +/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL + + If LDPC, + + 0: LDPC extra symbol not present + + 1: LDPC extra symbol present + + Else + + Set to 1 + + +*/ +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 8 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000100 + +/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC + + Indicates whether STBC is applied + + 0: No STBC + + 1: STBC + + +*/ +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 9 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x00000200 + +/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF + + Indicates whether beamforming is applied + + 0: No beamforming + + 1: beamforming + + +*/ +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 10 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x00000400 + +/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR + + Common trigger info + + + + the packet extension duration of the trigger-based PPDU + response with these two bits indicating the a-factor + + + + + + + + + + + + + + +*/ +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 11 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x00001800 + +/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY + + Common trigger info + + + + the packet extension duration of the trigger-based PPDU + response with this bit indicating the PE-Disambiguity + + +*/ +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 13 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x00002000 + +/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A + + Note: per standard, set to 1 + + +*/ +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 14 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x00004000 + +/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION + + 0: No Doppler support + + 1: Doppler support + + +*/ +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 15 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x00008000 + +/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC + + CRC for HE-SIG-A contents. + + +*/ +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 16 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f0000 + +/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL + + +*/ +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 20 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f00000 + +/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED + + TX side: + + Set to 0 + + + + RX side: + + On RX side, evaluated by MAC HW. This is the only way + for MAC RX to know that this was an HE_SIG_A_SU received in + 'extended' format + + + + + +*/ +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 26 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x04000000 + +/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE + + TX side: + + Set to 0 + + + + RX side: + + Field only contains valid info when dot11ax_su_extended + is set. + + + + On RX side, evaluated by MAC HW. This is the only way + for MAC RX to know what the number of based RUs was in this + extended range reception. It is used by the MAC to determine + the RU size for the response... + + +*/ +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 27 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x78000000 + +/* Description PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP + + TX side: + + Set to 0 + + + + RX side:Valid on RX side only, and looked at by MAC HW + + + + When set, PHY has received (expected) NDP frame + + +*/ +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x00000004 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 31 +#define PHYRX_HE_SIG_A_SU_1_PHYRX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x80000000 + + +#endif // _PHYRX_HE_SIG_A_SU_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/phyrx_he_sig_b1_mu.h b/drivers/staging/fw-api/hw/qca6750/v1/phyrx_he_sig_b1_mu.h new file mode 100644 index 000000000000..d6e649cb7feb --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/phyrx_he_sig_b1_mu.h @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _PHYRX_HE_SIG_B1_MU_H_ +#define _PHYRX_HE_SIG_B1_MU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b1_mu_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_PHYRX_HE_SIG_B1_MU 1 + +struct phyrx_he_sig_b1_mu { + struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details; +}; + +/* + +struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details + + See detailed description of the STRUCT +*/ + + + /* EXTERNAL REFERENCE : struct he_sig_b1_mu_info phyrx_he_sig_b1_mu_info_details */ + + +/* Description PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION + + RU allocation for the user(s) following this common + portion of the SIG + + + + For details, refer to RU_TYPE description + + +*/ +#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0 +#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x000000ff + +/* Description PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0 + + +*/ +#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8 +#define PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0xffffff00 + + +#endif // _PHYRX_HE_SIG_B1_MU_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/phyrx_he_sig_b2_mu.h b/drivers/staging/fw-api/hw/qca6750/v1/phyrx_he_sig_b2_mu.h new file mode 100644 index 000000000000..cb00189e11a5 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/phyrx_he_sig_b2_mu.h @@ -0,0 +1,150 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _PHYRX_HE_SIG_B2_MU_H_ +#define _PHYRX_HE_SIG_B2_MU_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b2_mu_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_MU 1 + +struct phyrx_he_sig_b2_mu { + struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details; +}; + +/* + +struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details + + See detailed description of the STRUCT +*/ + + + /* EXTERNAL REFERENCE : struct he_sig_b2_mu_info phyrx_he_sig_b2_mu_info_details */ + + +/* Description PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID + + Identifies the STA that is addressed. Details of STA ID + are TBD +*/ +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x000007ff + +/* Description PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG + + Number of assigned spatial streams and their + corresponding index. + + Total number of spatial streams assigned for the MU-MIMO + allocation is also signaled. +*/ +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00007800 + +/* Description PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS + + Indicates the data MCS +*/ +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x00078000 + +/* Description PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1 + + +*/ +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x00080000 + +/* Description PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING + + Distinguishes between BCC/LDPC + + + + 0: BCC + + 1: LDPC + + +*/ +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x00100000 + +/* Description PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A + + +*/ +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x1fe00000 + +/* Description PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS + + MAC RX side usage only: + + Needed by RXPCU. Provided by PHY so that RXPCU does not + need to have the RU number decoding logic. + + + + Number of spatial streams for this user + + + + Single spatial stream + + 2 spatial streams + + 3 spatial streams + + 4 spatial streams + + 5 spatial streams + + 6 spatial streams + + 7 spatial streams + + 8 spatial streams +*/ +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 29 +#define PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0xe0000000 + + +#endif // _PHYRX_HE_SIG_B2_MU_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/phyrx_he_sig_b2_ofdma.h b/drivers/staging/fw-api/hw/qca6750/v1/phyrx_he_sig_b2_ofdma.h new file mode 100644 index 000000000000..76b42989433c --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/phyrx_he_sig_b2_ofdma.h @@ -0,0 +1,154 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _PHYRX_HE_SIG_B2_OFDMA_H_ +#define _PHYRX_HE_SIG_B2_OFDMA_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "he_sig_b2_ofdma_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_PHYRX_HE_SIG_B2_OFDMA 1 + +struct phyrx_he_sig_b2_ofdma { + struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details; +}; + +/* + +struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details + + See detailed description of the STRUCT +*/ + + + /* EXTERNAL REFERENCE : struct he_sig_b2_ofdma_info phyrx_he_sig_b2_ofdma_info_details */ + + +/* Description PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID + + Identifies the STA that is addressed. Details of STA ID + are TBD +*/ +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x000007ff + +/* Description PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS + + MAC RX side usage only: + + + + Number of spatial streams for this user + + + + Single spatial stream + + 2 spatial streams + + 3 spatial streams + + 4 spatial streams + + 5 spatial streams + + 6 spatial streams + + 7 spatial streams + + 8 spatial streams +*/ +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x00003800 + +/* Description PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF + + Indicates whether beamforming is applied + + 0: No beamforming + + 1: beamforming + + +*/ +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x00004000 + +/* Description PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS + + Indicates the data MCS +*/ +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x00078000 + +/* Description PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM + + + 0: No DCM + + 1:DCM + + +*/ +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x00080000 + +/* Description PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING + + Distinguishes between BCC/LDPC + + + + 0: BCC + + 1: LDPC + + +*/ +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x00100000 + +/* Description PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0 + + +*/ +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21 +#define PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0xffe00000 + + +#endif // _PHYRX_HE_SIG_B2_OFDMA_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/phyrx_ht_sig.h b/drivers/staging/fw-api/hw/qca6750/v1/phyrx_ht_sig.h new file mode 100644 index 000000000000..d4b14289d7fc --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/phyrx_ht_sig.h @@ -0,0 +1,252 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _PHYRX_HT_SIG_H_ +#define _PHYRX_HT_SIG_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "ht_sig_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct ht_sig_info phyrx_ht_sig_info_details; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_PHYRX_HT_SIG 2 + +struct phyrx_ht_sig { + struct ht_sig_info phyrx_ht_sig_info_details; +}; + +/* + +struct ht_sig_info phyrx_ht_sig_info_details + + See detailed description of the STRUCT +*/ + + + /* EXTERNAL REFERENCE : struct ht_sig_info phyrx_ht_sig_info_details */ + + +/* Description PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS + + Modulation Coding Scheme: + + 0-7 are used for single stream + + 8-15 are used for 2 streams + + 16-23 are used for 3 streams + + 24-31 are used for 4 streams + + 32 is used for duplicate HT20 (unsupported) + + 33-76 is used for unequal modulation (unsupported) + + 77-127 is reserved. + + +*/ +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x00000000 +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_LSB 0 +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_MASK 0x0000007f + +/* Description PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_CBW + + Packet bandwidth: + + + + + + +*/ +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x00000000 +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_CBW_LSB 7 +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_CBW_MASK 0x00000080 + +/* Description PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_LENGTH + + This is the MPDU or A-MPDU length in octets of the PPDU + + +*/ +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8 +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x00ffff00 + +/* Description PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0 + + This field is not part of HT-SIG + + Reserved: Should be set to 0 by the MAC and ignored by + the PHY +*/ +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24 +#define PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0xff000000 + +/* Description PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING + + Field indicates if smoothing is needed + + E_num 0 do_smoothing Unsupported setting: indicates + smoothing is often used for beamforming + + + +*/ +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 0 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x00000001 + +/* Description PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING + + E_num 0 sounding Unsupported setting: indicates + sounding is used + + Indicates no sounding is used + + +*/ +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 1 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x00000002 + +/* Description PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED + + Reserved: Should be set to 1 by the MAC and ignored by + the PHY + + +*/ +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 2 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x00000004 + +/* Description PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION + + Indicates MPDU format + + Indicates A-MPDU format + + +*/ +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 3 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x00000008 + +/* Description PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_STBC + + Indicates no STBC + + Indicates 1 stream STBC + + E_num 2 2_str_stbc Indicates 2 stream STBC + (Unsupported) + + +*/ +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_STBC_LSB 4 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_STBC_MASK 0x00000030 + +/* Description PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING + + Indicates BCC coding + + Indicates LDPC coding + + +*/ +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 6 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x00000040 + +/* Description PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI + + Indicates normal guard + interval + + + +*/ +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 7 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x00000080 + +/* Description PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR + + Number of extension spatial streams: (Used for TxBF) + + No extension spatial streams + + E_num 1 1_ext_sp_str Not supported: 1 extension + spatial streams + + E_num 2 2_ext_sp_str Not supported: 2 extension + spatial streams + + +*/ +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 8 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x00000300 + +/* Description PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_CRC + + The CRC protects the HT-SIG (HT-SIG[0][23:0] and + HT-SIG[1][9:0]. The generator polynomial is G(D) = D8 + D2 + + D + 1. +*/ +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_CRC_LSB 10 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc00 + +/* Description PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL + + The 6 bits of tail is always set to 0 is used to flush + the BCC encoder and decoder. +*/ +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 18 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc0000 + +/* Description PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1 + + This field is not part of HT-SIG: + + Reserved: Should be set to 0 by the MAC and ignored by + the PHY. +*/ +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 24 +#define PHYRX_HT_SIG_1_PHYRX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0xff000000 + + +#endif // _PHYRX_HT_SIG_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/phyrx_l_sig_a.h b/drivers/staging/fw-api/hw/qca6750/v1/phyrx_l_sig_a.h new file mode 100644 index 000000000000..cdaed48e282e --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/phyrx_l_sig_a.h @@ -0,0 +1,186 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _PHYRX_L_SIG_A_H_ +#define _PHYRX_L_SIG_A_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "l_sig_a_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 struct l_sig_a_info phyrx_l_sig_a_info_details; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_PHYRX_L_SIG_A 1 + +struct phyrx_l_sig_a { + struct l_sig_a_info phyrx_l_sig_a_info_details; +}; + +/* + +struct l_sig_a_info phyrx_l_sig_a_info_details + + See detailed description of the STRUCT +*/ + + + /* EXTERNAL REFERENCE : struct l_sig_a_info phyrx_l_sig_a_info_details */ + + +/* Description PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE + + This format is originally defined for OFDM as a 4 bit + field but the 5th bit was added to indicate 11b formatted + frames. In the standard bit [4] is specified as reserved. + For 11b frames this L-SIG is transformed in the PHY into the + 11b preamble format. The following are the rates: + + 64-QAM 2/3 (48 Mbps) + + 16-QAM 1/2 (24 Mbps) + + QPSK 1/2 (12 Mbps) + + BPSK 1/2 (6 Mbps) + + 64-QAM 3/4 (54 Mbps) + + 16-QAM 3/4 (36 Mbps) + + QPSK 1/2 (18 Mbps) + + BPSK 3/4 (9 Mbps) + + +*/ +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_LSB 0 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x0000000f + +/* Description PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED + + Reserved: Should be set to 0 by the MAC and ignored by + the PHY + + +*/ +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x00000010 + +/* Description PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH + + The length indicates the number of octets in this MPDU. + Note that when using mixed mode 11n preamble this length + provides the spoofed length for the PPDU. This length + provides part of the information to derive the actually PPDU + length. For legacy OFDM and 11B frames the maximum length + is + + +*/ +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x0001ffe0 + +/* Description PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PARITY + + 11a/n/ac TX: This field provides even parity over the + first 18 bits of the signal field which means that the sum + of 1s in the signal field will always be even on + + 11a/n/ac RX: this field contains the received parity + field from the L-SIG symbol for the current packet. + + +*/ +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x00020000 + +/* Description PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_TAIL + + The 6 bits of tail is always set to 0 is used to flush + the BCC encoder and decoder. +*/ +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc0000 + +/* Description PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE + + Only used on the RX side. + + Note: This is not really part of L-SIG + + + + Packet type: + + 802.11a PPDU type + + 802.11b PPDU type + + 802.11n Mixed Mode PPDU type + + 802.11ac PPDU type + + 802.11ax PPDU type + + 802.11ba (WUR) PPDU type +*/ +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000 + +/* Description PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING + + Only used on the RX side. + + Note: This is not really part of L-SIG + + + + This indicates that the PHY has captured implicit + sounding. +*/ +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x10000000 + +/* Description PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED + + Reserved: Should be set to 0 by the transmitting MAC and + ignored by the PHY +*/ +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x00000000 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29 +#define PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0xe0000000 + + +#endif // _PHYRX_L_SIG_A_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/phyrx_l_sig_b.h b/drivers/staging/fw-api/hw/qca6750/v1/phyrx_l_sig_b.h new file mode 100644 index 000000000000..d99adce0fe85 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/phyrx_l_sig_b.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _PHYRX_L_SIG_B_H_ +#define _PHYRX_L_SIG_B_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "l_sig_b_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 struct l_sig_b_info phyrx_l_sig_b_info_details; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_PHYRX_L_SIG_B 1 + +struct phyrx_l_sig_b { + struct l_sig_b_info phyrx_l_sig_b_info_details; +}; + +/* + +struct l_sig_b_info phyrx_l_sig_b_info_details + + See detailed description of the STRUCT +*/ + + + /* EXTERNAL REFERENCE : struct l_sig_b_info phyrx_l_sig_b_info_details */ + + +/* Description PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE + + DSSS 1 Mbps long + + DSSS 2 Mbps long + + CCK 5.5 Mbps long + + CCK 11 Mbps long + + DSSS 2 Mbps short + + CCK 5.5 Mbps short + + CCK 11 Mbps short + + +*/ +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x00000000 +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_LSB 0 +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x0000000f + +/* Description PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH + + The length indicates the number of octets in this MPDU. + + +*/ +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x00000000 +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4 +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x0000fff0 + +/* Description PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED + + Reserved: Should be set to 0 by the transmitting MAC and + ignored by the PHY +*/ +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x00000000 +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16 +#define PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0xffff0000 + + +#endif // _PHYRX_L_SIG_B_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/phyrx_other_receive_info_ru_details.h b/drivers/staging/fw-api/hw/qca6750/v1/phyrx_other_receive_info_ru_details.h new file mode 100644 index 000000000000..8fb96265020a --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/phyrx_other_receive_info_ru_details.h @@ -0,0 +1,124 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ +#define _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 ru_details_channel_0[31:0] +// 1 ru_details_channel_1[31:0] +// 2 spare[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS 3 + +struct phyrx_other_receive_info_ru_details { + uint32_t ru_details_channel_0 : 32; //[31:0] + uint32_t ru_details_channel_1 : 32; //[31:0] + uint32_t spare : 32; //[31:0] +}; + +/* + +ru_details_channel_0 + + Ru_allocation from content channel 0 + + [7:0] for 20/40 MHz + + [15:0] for 80 MHz + + [31:0] for 160 MHz + + + +ru_details_channel_1 + + Ru_allocation from content channel 1 + + [7:0] for 40 MHz + + [15:0] for 80 MHz + + [31:0] for 160 MHz + + + +spare + + Extra spare bits added to convey additional information + + +*/ + + +/* Description PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_0_RU_DETAILS_CHANNEL_0 + + Ru_allocation from content channel 0 + + [7:0] for 20/40 MHz + + [15:0] for 80 MHz + + [31:0] for 160 MHz + + +*/ +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_0_RU_DETAILS_CHANNEL_0_OFFSET 0x00000000 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_0_RU_DETAILS_CHANNEL_0_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_0_RU_DETAILS_CHANNEL_0_MASK 0xffffffff + +/* Description PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_1_RU_DETAILS_CHANNEL_1 + + Ru_allocation from content channel 1 + + [7:0] for 40 MHz + + [15:0] for 80 MHz + + [31:0] for 160 MHz + + +*/ +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_1_RU_DETAILS_CHANNEL_1_OFFSET 0x00000004 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_1_RU_DETAILS_CHANNEL_1_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_1_RU_DETAILS_CHANNEL_1_MASK 0xffffffff + +/* Description PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_2_SPARE + + Extra spare bits added to convey additional information + + +*/ +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_2_SPARE_OFFSET 0x00000008 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_2_SPARE_LSB 0 +#define PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_2_SPARE_MASK 0xffffffff + + +#endif // _PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/phyrx_pkt_end.h b/drivers/staging/fw-api/hw/qca6750/v1/phyrx_pkt_end.h new file mode 100644 index 000000000000..398943847df0 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/phyrx_pkt_end.h @@ -0,0 +1,1715 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _PHYRX_PKT_END_H_ +#define _PHYRX_PKT_END_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phyrx_pkt_end_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-32 struct phyrx_pkt_end_info rx_pkt_end_details; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_PHYRX_PKT_END 33 + +struct phyrx_pkt_end { + struct phyrx_pkt_end_info rx_pkt_end_details; +}; + +/* + +struct phyrx_pkt_end_info rx_pkt_end_details + + Overview of the final receive related parameters from + the PHY RX +*/ + + + /* EXTERNAL REFERENCE : struct phyrx_pkt_end_info rx_pkt_end_details */ + + +/* Description PHYRX_PKT_END_0_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP + + When set, PHY RX entered an internal NAP state, as PHY + determined that this reception was not destined to this + device +*/ +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_LSB 0 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_PHY_INTERNAL_NAP_MASK 0x00000001 + +/* Description PHYRX_PKT_END_0_RX_PKT_END_DETAILS_LOCATION_INFO_VALID + + Indicates that the RX_LOCATION_INFO structure later on + in the TLV contains valid info +*/ +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_LSB 1 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_LOCATION_INFO_VALID_MASK 0x00000002 + +/* Description PHYRX_PKT_END_0_RX_PKT_END_DETAILS_TIMING_INFO_VALID + + Indicates that the RX_TIMING_OFFSET_INFO structure later + on in the TLV contains valid info +*/ +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_TIMING_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_TIMING_INFO_VALID_LSB 2 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_TIMING_INFO_VALID_MASK 0x00000004 + +/* Description PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RSSI_INFO_VALID + + Indicates that the RECEIVE_RSSI_INFO structure later on + in the TLV contains valid info +*/ +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RSSI_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RSSI_INFO_VALID_LSB 3 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RSSI_INFO_VALID_MASK 0x00000008 + +/* Description PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RX_FRAME_CORRECTION_NEEDED + + When clear, no action is needed in the MAC. + + + + When set, the falling edge of the rx_frame happened 4us + too late. MAC will need to compensate for this delay in + order to maintain proper SIFS timing and/or not to get + de-slotted. + + + + PHY uses this for very short 11a frames. + + + + When set, PHY will have passed this TLV to the MAC up to + 8 us into the 'real SIFS' time, and thus within 4us from the + falling edge of the rx_frame. + + + + +*/ +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RX_FRAME_CORRECTION_NEEDED_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RX_FRAME_CORRECTION_NEEDED_LSB 4 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RX_FRAME_CORRECTION_NEEDED_MASK 0x00000010 + +/* Description PHYRX_PKT_END_0_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED + + When set, PHY has received the 'frameless frame' . Can + be used in the 'MU-RTS -CTS exchange where CTS reception can + be problematic. + + +*/ +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_LSB 5 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 + +/* Description PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0A + + +*/ +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0A_LSB 6 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0A_MASK 0x00000fc0 + +/* Description PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_INFO_VALID + + When set, the following DL_ofdma_... fields are valid. + + It provides the MAC insight into which RU was allocated + to this device. + + +*/ +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_INFO_VALID_LSB 12 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_INFO_VALID_MASK 0x00001000 + +/* Description PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_START_INDEX + + RU index number to which User is assigned + + RU numbering is over the entire BW, starting from 0 and + in increasing frequency order and not primary-secondary + order + + +*/ +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_START_INDEX_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_START_INDEX_LSB 13 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_START_INDEX_MASK 0x000fe000 + +/* Description PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_WIDTH + + The size of the RU for this user. + + In units of 1 (26 tone) RU + + +*/ +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_WIDTH_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_WIDTH_LSB 20 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_DL_OFDMA_RU_WIDTH_MASK 0x07f00000 + +/* Description PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0B + + +*/ +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0B_LSB 27 +#define PHYRX_PKT_END_0_RX_PKT_END_DETAILS_RESERVED_0B_MASK 0xf8000000 + +/* Description PHYRX_PKT_END_1_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32 + + TODO PHY: cleanup descriptionThe PHY timestamp in the + AMPI of the first rising edge of rx_clear_pri after + TX_PHY_DESC. . This field should set to 0 by the PHY and + should be updated by the AMPI before being forwarded to the + rest of the MAC. This field indicates the lower 32 bits of + the timestamp +*/ +#define PHYRX_PKT_END_1_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 +#define PHYRX_PKT_END_1_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_LSB 0 +#define PHYRX_PKT_END_1_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff + +/* Description PHYRX_PKT_END_2_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32 + + TODO PHY: cleanup description + + The PHY timestamp in the AMPI of the first rising edge + of rx_clear_pri after TX_PHY_DESC. This field should set to + 0 by the PHY and should be updated by the AMPI before being + forwarded to the rest of the MAC. This field indicates the + upper 32 bits of the timestamp +*/ +#define PHYRX_PKT_END_2_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 +#define PHYRX_PKT_END_2_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_LSB 0 +#define PHYRX_PKT_END_2_RX_PKT_END_DETAILS_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff + +/* Description PHYRX_PKT_END_3_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32 + + TODO PHY: cleanup description + + The PHY timestamp in the AMPI of the rising edge of + rx_clear_pri after RX_RSSI_LEGACY. This field should set to + 0 by the PHY and should be updated by the AMPI before being + forwarded to the rest of the MAC. This field indicates the + lower 32 bits of the timestamp +*/ +#define PHYRX_PKT_END_3_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c +#define PHYRX_PKT_END_3_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_LSB 0 +#define PHYRX_PKT_END_3_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff + +/* Description PHYRX_PKT_END_4_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32 + + TODO PHY: cleanup description + + The PHY timestamp in the AMPI of the rising edge of + rx_clear_pri after RX_RSSI_LEGACY. This field should set to + 0 by the PHY and should be updated by the AMPI before being + forwarded to the rest of the MAC. This field indicates the + upper 32 bits of the timestamp +*/ +#define PHYRX_PKT_END_4_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 +#define PHYRX_PKT_END_4_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_LSB 0 +#define PHYRX_PKT_END_4_RX_PKT_END_DETAILS_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff + + /* EXTERNAL REFERENCE : struct rx_location_info rx_location_info_details */ + + +/* Description PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY + + For 20/40/80, this field shows the RTT first arrival + correction value computed from L-LTF on the first selected + Rx chain + + + + For 80+80, this field shows the RTT first arrival + correction value computed from L-LTF on pri80 on the + selected pri80 Rx chain + + + + 16 bits, signed 12.4. 12 bits integer to cover -6.4us to + 6.4us, and 4 bits fraction to cover pri80 and 32x FAC + interpolation + + + + clock unit is 320MHz + + +*/ +#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_OFFSET 0x00000014 +#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_LSB 0 +#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_MASK 0x0000ffff + +/* Description PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80 + + For 20/40/80, this field shows the RTT first arrival + correction value computed from L-LTF on the second selected + Rx chain + + + + For 80+80, this field shows the RTT first arrival + correction value computed from L-LTF on ext80 on the + selected ext80 Rx chain + + + + 16 bits, signed 12.4. 12 bits integer to cover -6.4us to + 6.4us, and 4 bits fraction to cover ext80 and 32x FAC + interpolation + + + + clock unit is 320MHz + + +*/ +#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_OFFSET 0x00000014 +#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_LSB 16 +#define PHYRX_PKT_END_5_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_MASK 0xffff0000 + +/* Description PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT + + For 20/40/80, this field shows the RTT first arrival + correction value computed from (V)HT/HE-LTF on the first + selected Rx chain + + + + For 80+80, this field shows the RTT first arrival + correction value computed from (V)HT/HE-LTF on pri80 on the + selected pri80 Rx chain + + + + 16 bits, signed 12.4. 12 bits integer to cover -6.4us to + 6.4us, and 4 bits fraction to cover pri80 and 32x FAC + interpolation + + + + clock unit is 320MHz + + +*/ +#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_OFFSET 0x00000018 +#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_LSB 0 +#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_MASK 0x0000ffff + +/* Description PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80 + + For 20/40/80, this field shows the RTT first arrival + correction value computed from (V)HT/HE-LTF on the second + selected Rx chain + + + + For 80+80, this field shows the RTT first arrival + correction value computed from (V)HT/HE-LTF on ext80 on the + selected ext80 Rx chain + + + + 16 bits, signed 12.4. 12 bits integer to cover -6.4us to + 6.4us, and 4 bits fraction to cover ext80 and 32x FAC + interpolation + + + + clock unit is 320MHz + + +*/ +#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_OFFSET 0x00000018 +#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_LSB 16 +#define PHYRX_PKT_END_6_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_MASK 0xffff0000 + +/* Description PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS + + Status of rtt_fac_legacy + + + + + + + + +*/ +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_LSB 0 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_MASK 0x00000001 + +/* Description PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS + + Status of rtt_fac_legacy_ext80 + + + + + + + + +*/ +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_LSB 1 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_MASK 0x00000002 + +/* Description PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS + + Status of rtt_fac_vht + + + + + + + + +*/ +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_LSB 2 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_MASK 0x00000004 + +/* Description PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS + + Status of rtt_fac_vht_ext80 + + + + + + + + +*/ +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_LSB 3 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_MASK 0x00000008 + +/* Description PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS + + To support fine SIFS adjustment, need to provide FAC + value @ integer number of 320 MHz clock cycles to MAC.  It + is from L-LTF if it is a Legacy packet and from (V)HT/HE-LTF + if it is a (V)HT/HE packet + + + + 12 bits, signed, no fractional part + + +*/ +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_LSB 4 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_MASK 0x0000fff0 + +/* Description PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS + + Status of rtt_fac_sifs + + 0: not valid + + 1: valid and from L-LTF + + 2: valid and from (V)HT/HE-LTF + + 3: reserved + + +*/ +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_LSB 16 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_MASK 0x00030000 + +/* Description PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS + + Status of channel frequency response dump + + + + + + + + +*/ +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 18 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00040000 + +/* Description PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS + + Status of channel impulse response dump + + + + + + + + +*/ +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 19 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0x00080000 + +/* Description PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE + + Channel dump size.  It shows how many tones in CFR in + one chain, for example, it will show 52 for Legacy20 and 484 + for VHT160 + + + + +*/ +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_LSB 20 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_MASK 0x7ff00000 + +/* Description PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE + + Indicator showing if HW IFFT mode or SW IFFT mode + + + + + + + + +*/ +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000001c +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 31 +#define PHYRX_PKT_END_7_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x80000000 + +/* Description PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS + + Indicate if BTCF is used to capture the timestamps + + + + + + + + +*/ +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_LSB 0 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_MASK 0x00000001 + +/* Description PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE + + Indicate preamble type + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +*/ +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 1 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000003e + +/* Description PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG + + Indicate the bandwidth of L-LTF + + + + + + + + + + + + +*/ +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 6 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x000000c0 + +/* Description PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT + + Indicate the bandwidth of (V)HT/HE-LTF + + + + + + + + + + + + +*/ +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 8 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x00000300 + +/* Description PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE + + Indicate GI (guard interval) type + + + + HE related GI. Can also be used + for HE + + HE related GI. Can also be used + for HE + + HE related GI + + HE related GI + + +*/ +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 10 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000c00 + +/* Description PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE + + Bits 0~4 indicate MCS rate, if Legacy, + + 0: 48 Mbps, + + 1: 24 Mbps, + + 2: 12 Mbps, + + 3: 6 Mbps, + + 4: 54 Mbps, + + 5: 36 Mbps, + + 6: 18 Mbps, + + 7: 9 Mbps, + + + + if HT, 0-7: MCS0-MCS7, + + if VHT, 0-9: MCS0-MCS9, + + + +*/ +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 12 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0x0001f000 + +/* Description PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN + + For 20/40/80, this field shows the first selected Rx + chain that is used in HW IFFT mode + + + + For 80+80, this field shows the selected pri80 Rx chain + that is used in HW IFFT mode + + + + + + + + + + + + + + + + + + + + +*/ +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_LSB 17 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_MASK 0x000e0000 + +/* Description PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80 + + For 20/40/80, this field shows the second selected Rx + chain that is used in HW IFFT mode + + + + For 80+80, this field shows the selected ext80 Rx chain + that is used in HW IFFT mode + + + + + + + + + + + + + + + + + + + + +*/ +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_LSB 20 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_MASK 0x00700000 + +/* Description PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK + + Rx chain mask, each bit is a Rx chain + + 0: the Rx chain is not used + + 1: the Rx chain is used + + Support up to 8 Rx chains + + +*/ +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 23 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x7f800000 + +/* Description PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_3 + + +*/ +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x00000020 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 31 +#define PHYRX_PKT_END_8_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x80000000 + +/* Description PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_START_TS + + RX packet start timestamp + + + + It reports the time the first L-STF ADC sample arrived + at RX antenna + + + + clock unit is 480MHz + + +*/ +#define PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x00000024 +#define PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 0 +#define PHYRX_PKT_END_9_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff + +/* Description PHYRX_PKT_END_10_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_END_TS + + RX packet end timestamp + + + + It reports the time the last symbol's last ADC sample + arrived at RX antenna + + + + clock unit is 480MHz + + +*/ +#define PHYRX_PKT_END_10_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x00000028 +#define PHYRX_PKT_END_10_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 0 +#define PHYRX_PKT_END_10_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff + +/* Description PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START + + The phase of the SFO of the first symbol's first FFT + input sample + + + + 12 bits, signed 6.6. 6 bits integer to cover -66.7ns to + 66.7ns, and 6 bits fraction to provide a resolution of + 0.03ns + + + + clock unit is 480MHz + + +*/ +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_OFFSET 0x0000002c +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_LSB 0 +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_MASK 0x00000fff + +/* Description PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END + + The phase of the SFO of the last symbol's last FFT input + sample + + + + 12 bits, signed 6.6. 6 bits integer to cover -66.7ns to + 66.7ns, and 6 bits fraction to provide a resolution of + 0.03ns + + + + clock unit is 480MHz + + +*/ +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_OFFSET 0x0000002c +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_LSB 12 +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_MASK 0x00fff000 + +/* Description PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8 + + The high 8 bits of the 40 bits pointer pointed to the + external RTT channel information buffer + + + + 8 bits + + +*/ +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000002c +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 24 +#define PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0xff000000 + +/* Description PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32 + + The low 32 bits of the 40 bits pointer pointed to the + external RTT channel information buffer + + + + 32 bits + + +*/ +#define PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000030 +#define PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 +#define PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff + +/* Description PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT + + CFO measurement. Needed for passive locationing + + + + 14 bits, signed 1.13. 13 bits fraction to provide a + resolution of 153 Hz + + + + In units of cycles/800 ns + + +*/ +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x00000034 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x00003fff + +/* Description PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD + + Channel delay spread measurement. Needed for selecting + GI length + + + + 8 bits, unsigned. At 25 ns step. Can represent up to + 6375 ns + + + + In units of cycles @ 40 MHz + + +*/ +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_OFFSET 0x00000034 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_LSB 14 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_MASK 0x003fc000 + +/* Description PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL + + Indicate which timing backoff value is used + + + + + + + + + + + + +*/ +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000034 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 22 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x00c00000 + +/* Description PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_8 + + +*/ +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_8_OFFSET 0x00000034 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_8_LSB 24 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RESERVED_8_MASK 0x7f000000 + +/* Description PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID + + + + + + +*/ +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x00000034 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 31 +#define PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x80000000 + + /* EXTERNAL REFERENCE : struct rx_timing_offset_info rx_timing_offset_info_details */ + + +/* Description PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET + + Cumulative reference frequency error at end of RX + + +*/ +#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000038 +#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0 +#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff + +/* Description PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED + + +*/ +#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x00000038 +#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 12 +#define PHYRX_PKT_END_14_RX_PKT_END_DETAILS_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff000 + + /* EXTERNAL REFERENCE : struct receive_rssi_info post_rssi_info_details */ + + +/* Description PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0 + + RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000003c +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +/* Description PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000003c +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +/* Description PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000003c +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +/* Description PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000003c +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_15_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +/* Description PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000040 +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +/* Description PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000040 +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +/* Description PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000040 +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +/* Description PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000040 +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_16_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +/* Description PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1 + + RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000044 +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +/* Description PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000044 +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +/* Description PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000044 +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +/* Description PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000044 +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_17_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +/* Description PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000048 +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +/* Description PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000048 +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +/* Description PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000048 +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +/* Description PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000048 +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_18_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +/* Description PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2 + + RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000004c +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +/* Description PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000004c +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +/* Description PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000004c +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +/* Description PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000004c +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_19_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +/* Description PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000050 +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +/* Description PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000050 +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +/* Description PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000050 +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +/* Description PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000050 +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_20_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +/* Description PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3 + + RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +/* Description PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +/* Description PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +/* Description PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_21_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +/* Description PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000058 +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +/* Description PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000058 +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +/* Description PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000058 +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +/* Description PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000058 +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_22_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +/* Description PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4 + + RSSI of RX PPDU on chain 4 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000005c +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0 +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff + +/* Description PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000005c +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8 +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00 + +/* Description PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000005c +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16 +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000 + +/* Description PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000005c +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24 +#define PHYRX_PKT_END_23_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000 + +/* Description PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000060 +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0 +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff + +/* Description PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000060 +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8 +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00 + +/* Description PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000060 +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16 +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000 + +/* Description PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000060 +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24 +#define PHYRX_PKT_END_24_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000 + +/* Description PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5 + + RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000064 +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0 +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff + +/* Description PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000064 +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8 +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00 + +/* Description PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000064 +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16 +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000 + +/* Description PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000064 +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24 +#define PHYRX_PKT_END_25_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000 + +/* Description PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000068 +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0 +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff + +/* Description PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000068 +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8 +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00 + +/* Description PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000068 +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16 +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000 + +/* Description PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000068 +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24 +#define PHYRX_PKT_END_26_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000 + +/* Description PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6 + + RSSI of RX PPDU on chain 6 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000006c +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0 +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff + +/* Description PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000006c +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8 +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00 + +/* Description PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000006c +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16 +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000 + +/* Description PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000006c +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24 +#define PHYRX_PKT_END_27_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000 + +/* Description PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000070 +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0 +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff + +/* Description PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000070 +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8 +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00 + +/* Description PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000070 +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16 +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000 + +/* Description PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000070 +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24 +#define PHYRX_PKT_END_28_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000 + +/* Description PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7 + + RSSI of RX PPDU on chain 7 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000074 +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0 +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff + +/* Description PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000074 +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8 +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00 + +/* Description PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000074 +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16 +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000 + +/* Description PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000074 +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24 +#define PHYRX_PKT_END_29_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000 + +/* Description PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000078 +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0 +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff + +/* Description PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000078 +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8 +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00 + +/* Description PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000078 +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16 +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000 + +/* Description PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000078 +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24 +#define PHYRX_PKT_END_30_RX_PKT_END_DETAILS_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000 + +/* Description PHYRX_PKT_END_31_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0 + + Some PHY micro code status that can be put in here. + Details of definition within SW specification + + This field can be used for debugging, FW - SW message + exchange, etc. + + It could for example be a pointer to a DDR memory + location where PHY FW put some debug info. + + +*/ +#define PHYRX_PKT_END_31_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_OFFSET 0x0000007c +#define PHYRX_PKT_END_31_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_LSB 0 +#define PHYRX_PKT_END_31_RX_PKT_END_DETAILS_PHY_SW_STATUS_31_0_MASK 0xffffffff + +/* Description PHYRX_PKT_END_32_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32 + + Some PHY micro code status that can be put in here. + Details of definition within SW specification + + This field can be used for debugging, FW - SW message + exchange, etc. + + It could for example be a pointer to a DDR memory + location where PHY FW put some debug info. + + +*/ +#define PHYRX_PKT_END_32_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_OFFSET 0x00000080 +#define PHYRX_PKT_END_32_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_LSB 0 +#define PHYRX_PKT_END_32_RX_PKT_END_DETAILS_PHY_SW_STATUS_63_32_MASK 0xffffffff + + +#endif // _PHYRX_PKT_END_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/phyrx_pkt_end_info.h b/drivers/staging/fw-api/hw/qca6750/v1/phyrx_pkt_end_info.h new file mode 100644 index 000000000000..bdf00a0b1ea7 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/phyrx_pkt_end_info.h @@ -0,0 +1,1903 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _PHYRX_PKT_END_INFO_H_ +#define _PHYRX_PKT_END_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_location_info.h" +#include "rx_timing_offset_info.h" +#include "receive_rssi_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 phy_internal_nap[0], location_info_valid[1], timing_info_valid[2], rssi_info_valid[3], rx_frame_correction_needed[4], frameless_frame_received[5], reserved_0a[11:6], dl_ofdma_info_valid[12], dl_ofdma_ru_start_index[19:13], dl_ofdma_ru_width[26:20], reserved_0b[31:27] +// 1 phy_timestamp_1_lower_32[31:0] +// 2 phy_timestamp_1_upper_32[31:0] +// 3 phy_timestamp_2_lower_32[31:0] +// 4 phy_timestamp_2_upper_32[31:0] +// 5-13 struct rx_location_info rx_location_info_details; +// 14 struct rx_timing_offset_info rx_timing_offset_info_details; +// 15-30 struct receive_rssi_info post_rssi_info_details; +// 31 phy_sw_status_31_0[31:0] +// 32 phy_sw_status_63_32[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_PHYRX_PKT_END_INFO 33 + +struct phyrx_pkt_end_info { + uint32_t phy_internal_nap : 1, //[0] + location_info_valid : 1, //[1] + timing_info_valid : 1, //[2] + rssi_info_valid : 1, //[3] + rx_frame_correction_needed : 1, //[4] + frameless_frame_received : 1, //[5] + reserved_0a : 6, //[11:6] + dl_ofdma_info_valid : 1, //[12] + dl_ofdma_ru_start_index : 7, //[19:13] + dl_ofdma_ru_width : 7, //[26:20] + reserved_0b : 5; //[31:27] + uint32_t phy_timestamp_1_lower_32 : 32; //[31:0] + uint32_t phy_timestamp_1_upper_32 : 32; //[31:0] + uint32_t phy_timestamp_2_lower_32 : 32; //[31:0] + uint32_t phy_timestamp_2_upper_32 : 32; //[31:0] + struct rx_location_info rx_location_info_details; + struct rx_timing_offset_info rx_timing_offset_info_details; + struct receive_rssi_info post_rssi_info_details; + uint32_t phy_sw_status_31_0 : 32; //[31:0] + uint32_t phy_sw_status_63_32 : 32; //[31:0] +}; + +/* + +phy_internal_nap + + When set, PHY RX entered an internal NAP state, as PHY + determined that this reception was not destined to this + device + +location_info_valid + + Indicates that the RX_LOCATION_INFO structure later on + in the TLV contains valid info + +timing_info_valid + + Indicates that the RX_TIMING_OFFSET_INFO structure later + on in the TLV contains valid info + +rssi_info_valid + + Indicates that the RECEIVE_RSSI_INFO structure later on + in the TLV contains valid info + +rx_frame_correction_needed + + When clear, no action is needed in the MAC. + + + + When set, the falling edge of the rx_frame happened 4us + too late. MAC will need to compensate for this delay in + order to maintain proper SIFS timing and/or not to get + de-slotted. + + + + PHY uses this for very short 11a frames. + + + + When set, PHY will have passed this TLV to the MAC up to + 8 us into the 'real SIFS' time, and thus within 4us from the + falling edge of the rx_frame. + + + + + +frameless_frame_received + + When set, PHY has received the 'frameless frame' . Can + be used in the 'MU-RTS -CTS exchange where CTS reception can + be problematic. + + + +reserved_0a + + + +dl_ofdma_info_valid + + When set, the following DL_ofdma_... fields are valid. + + It provides the MAC insight into which RU was allocated + to this device. + + + +dl_ofdma_ru_start_index + + RU index number to which User is assigned + + RU numbering is over the entire BW, starting from 0 and + in increasing frequency order and not primary-secondary + order + + + +dl_ofdma_ru_width + + The size of the RU for this user. + + In units of 1 (26 tone) RU + + + +reserved_0b + + + +phy_timestamp_1_lower_32 + + TODO PHY: cleanup descriptionThe PHY timestamp in the + AMPI of the first rising edge of rx_clear_pri after + TX_PHY_DESC. . This field should set to 0 by the PHY and + should be updated by the AMPI before being forwarded to the + rest of the MAC. This field indicates the lower 32 bits of + the timestamp + +phy_timestamp_1_upper_32 + + TODO PHY: cleanup description + + The PHY timestamp in the AMPI of the first rising edge + of rx_clear_pri after TX_PHY_DESC. This field should set to + 0 by the PHY and should be updated by the AMPI before being + forwarded to the rest of the MAC. This field indicates the + upper 32 bits of the timestamp + +phy_timestamp_2_lower_32 + + TODO PHY: cleanup description + + The PHY timestamp in the AMPI of the rising edge of + rx_clear_pri after RX_RSSI_LEGACY. This field should set to + 0 by the PHY and should be updated by the AMPI before being + forwarded to the rest of the MAC. This field indicates the + lower 32 bits of the timestamp + +phy_timestamp_2_upper_32 + + TODO PHY: cleanup description + + The PHY timestamp in the AMPI of the rising edge of + rx_clear_pri after RX_RSSI_LEGACY. This field should set to + 0 by the PHY and should be updated by the AMPI before being + forwarded to the rest of the MAC. This field indicates the + upper 32 bits of the timestamp + +struct rx_location_info rx_location_info_details + + Overview of location related info + +struct rx_timing_offset_info rx_timing_offset_info_details + + Overview of timing offset related info + +struct receive_rssi_info post_rssi_info_details + + Overview of the post-RSSI values. + +phy_sw_status_31_0 + + Some PHY micro code status that can be put in here. + Details of definition within SW specification + + This field can be used for debugging, FW - SW message + exchange, etc. + + It could for example be a pointer to a DDR memory + location where PHY FW put some debug info. + + + +phy_sw_status_63_32 + + Some PHY micro code status that can be put in here. + Details of definition within SW specification + + This field can be used for debugging, FW - SW message + exchange, etc. + + It could for example be a pointer to a DDR memory + location where PHY FW put some debug info. + + +*/ + + +/* Description PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP + + When set, PHY RX entered an internal NAP state, as PHY + determined that this reception was not destined to this + device +*/ +#define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_LSB 0 +#define PHYRX_PKT_END_INFO_0_PHY_INTERNAL_NAP_MASK 0x00000001 + +/* Description PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID + + Indicates that the RX_LOCATION_INFO structure later on + in the TLV contains valid info +*/ +#define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_LSB 1 +#define PHYRX_PKT_END_INFO_0_LOCATION_INFO_VALID_MASK 0x00000002 + +/* Description PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID + + Indicates that the RX_TIMING_OFFSET_INFO structure later + on in the TLV contains valid info +*/ +#define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_LSB 2 +#define PHYRX_PKT_END_INFO_0_TIMING_INFO_VALID_MASK 0x00000004 + +/* Description PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID + + Indicates that the RECEIVE_RSSI_INFO structure later on + in the TLV contains valid info +*/ +#define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_LSB 3 +#define PHYRX_PKT_END_INFO_0_RSSI_INFO_VALID_MASK 0x00000008 + +/* Description PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED + + When clear, no action is needed in the MAC. + + + + When set, the falling edge of the rx_frame happened 4us + too late. MAC will need to compensate for this delay in + order to maintain proper SIFS timing and/or not to get + de-slotted. + + + + PHY uses this for very short 11a frames. + + + + When set, PHY will have passed this TLV to the MAC up to + 8 us into the 'real SIFS' time, and thus within 4us from the + falling edge of the rx_frame. + + + + +*/ +#define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_LSB 4 +#define PHYRX_PKT_END_INFO_0_RX_FRAME_CORRECTION_NEEDED_MASK 0x00000010 + +/* Description PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED + + When set, PHY has received the 'frameless frame' . Can + be used in the 'MU-RTS -CTS exchange where CTS reception can + be problematic. + + +*/ +#define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_LSB 5 +#define PHYRX_PKT_END_INFO_0_FRAMELESS_FRAME_RECEIVED_MASK 0x00000020 + +/* Description PHYRX_PKT_END_INFO_0_RESERVED_0A + + +*/ +#define PHYRX_PKT_END_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_RESERVED_0A_LSB 6 +#define PHYRX_PKT_END_INFO_0_RESERVED_0A_MASK 0x00000fc0 + +/* Description PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID + + When set, the following DL_ofdma_... fields are valid. + + It provides the MAC insight into which RU was allocated + to this device. + + +*/ +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_LSB 12 +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_INFO_VALID_MASK 0x00001000 + +/* Description PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX + + RU index number to which User is assigned + + RU numbering is over the entire BW, starting from 0 and + in increasing frequency order and not primary-secondary + order + + +*/ +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_LSB 13 +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_START_INDEX_MASK 0x000fe000 + +/* Description PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH + + The size of the RU for this user. + + In units of 1 (26 tone) RU + + +*/ +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_LSB 20 +#define PHYRX_PKT_END_INFO_0_DL_OFDMA_RU_WIDTH_MASK 0x07f00000 + +/* Description PHYRX_PKT_END_INFO_0_RESERVED_0B + + +*/ +#define PHYRX_PKT_END_INFO_0_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_PKT_END_INFO_0_RESERVED_0B_LSB 27 +#define PHYRX_PKT_END_INFO_0_RESERVED_0B_MASK 0xf8000000 + +/* Description PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32 + + TODO PHY: cleanup descriptionThe PHY timestamp in the + AMPI of the first rising edge of rx_clear_pri after + TX_PHY_DESC. . This field should set to 0 by the PHY and + should be updated by the AMPI before being forwarded to the + rest of the MAC. This field indicates the lower 32 bits of + the timestamp +*/ +#define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_OFFSET 0x00000004 +#define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_LSB 0 +#define PHYRX_PKT_END_INFO_1_PHY_TIMESTAMP_1_LOWER_32_MASK 0xffffffff + +/* Description PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32 + + TODO PHY: cleanup description + + The PHY timestamp in the AMPI of the first rising edge + of rx_clear_pri after TX_PHY_DESC. This field should set to + 0 by the PHY and should be updated by the AMPI before being + forwarded to the rest of the MAC. This field indicates the + upper 32 bits of the timestamp +*/ +#define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_OFFSET 0x00000008 +#define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_LSB 0 +#define PHYRX_PKT_END_INFO_2_PHY_TIMESTAMP_1_UPPER_32_MASK 0xffffffff + +/* Description PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32 + + TODO PHY: cleanup description + + The PHY timestamp in the AMPI of the rising edge of + rx_clear_pri after RX_RSSI_LEGACY. This field should set to + 0 by the PHY and should be updated by the AMPI before being + forwarded to the rest of the MAC. This field indicates the + lower 32 bits of the timestamp +*/ +#define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_OFFSET 0x0000000c +#define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_LSB 0 +#define PHYRX_PKT_END_INFO_3_PHY_TIMESTAMP_2_LOWER_32_MASK 0xffffffff + +/* Description PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32 + + TODO PHY: cleanup description + + The PHY timestamp in the AMPI of the rising edge of + rx_clear_pri after RX_RSSI_LEGACY. This field should set to + 0 by the PHY and should be updated by the AMPI before being + forwarded to the rest of the MAC. This field indicates the + upper 32 bits of the timestamp +*/ +#define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_OFFSET 0x00000010 +#define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_LSB 0 +#define PHYRX_PKT_END_INFO_4_PHY_TIMESTAMP_2_UPPER_32_MASK 0xffffffff + + /* EXTERNAL REFERENCE : struct rx_location_info rx_location_info_details */ + + +/* Description PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY + + For 20/40/80, this field shows the RTT first arrival + correction value computed from L-LTF on the first selected + Rx chain + + + + For 80+80, this field shows the RTT first arrival + correction value computed from L-LTF on pri80 on the + selected pri80 Rx chain + + + + 16 bits, signed 12.4. 12 bits integer to cover -6.4us to + 6.4us, and 4 bits fraction to cover pri80 and 32x FAC + interpolation + + + + clock unit is 320MHz + + +*/ +#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_OFFSET 0x00000014 +#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_LSB 0 +#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_MASK 0x0000ffff + +/* Description PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80 + + For 20/40/80, this field shows the RTT first arrival + correction value computed from L-LTF on the second selected + Rx chain + + + + For 80+80, this field shows the RTT first arrival + correction value computed from L-LTF on ext80 on the + selected ext80 Rx chain + + + + 16 bits, signed 12.4. 12 bits integer to cover -6.4us to + 6.4us, and 4 bits fraction to cover ext80 and 32x FAC + interpolation + + + + clock unit is 320MHz + + +*/ +#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_OFFSET 0x00000014 +#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_LSB 16 +#define PHYRX_PKT_END_INFO_5_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_MASK 0xffff0000 + +/* Description PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT + + For 20/40/80, this field shows the RTT first arrival + correction value computed from (V)HT/HE-LTF on the first + selected Rx chain + + + + For 80+80, this field shows the RTT first arrival + correction value computed from (V)HT/HE-LTF on pri80 on the + selected pri80 Rx chain + + + + 16 bits, signed 12.4. 12 bits integer to cover -6.4us to + 6.4us, and 4 bits fraction to cover pri80 and 32x FAC + interpolation + + + + clock unit is 320MHz + + +*/ +#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_LSB 0 +#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_MASK 0x0000ffff + +/* Description PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80 + + For 20/40/80, this field shows the RTT first arrival + correction value computed from (V)HT/HE-LTF on the second + selected Rx chain + + + + For 80+80, this field shows the RTT first arrival + correction value computed from (V)HT/HE-LTF on ext80 on the + selected ext80 Rx chain + + + + 16 bits, signed 12.4. 12 bits integer to cover -6.4us to + 6.4us, and 4 bits fraction to cover ext80 and 32x FAC + interpolation + + + + clock unit is 320MHz + + +*/ +#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_OFFSET 0x00000018 +#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_LSB 16 +#define PHYRX_PKT_END_INFO_6_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_MASK 0xffff0000 + +/* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS + + Status of rtt_fac_legacy + + + + + + + + +*/ +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_LSB 0 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_STATUS_MASK 0x00000001 + +/* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS + + Status of rtt_fac_legacy_ext80 + + + + + + + + +*/ +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_LSB 1 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_LEGACY_EXT80_STATUS_MASK 0x00000002 + +/* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS + + Status of rtt_fac_vht + + + + + + + + +*/ +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_LSB 2 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_STATUS_MASK 0x00000004 + +/* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS + + Status of rtt_fac_vht_ext80 + + + + + + + + +*/ +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_LSB 3 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_VHT_EXT80_STATUS_MASK 0x00000008 + +/* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS + + To support fine SIFS adjustment, need to provide FAC + value @ integer number of 320 MHz clock cycles to MAC.  It + is from L-LTF if it is a Legacy packet and from (V)HT/HE-LTF + if it is a (V)HT/HE packet + + + + 12 bits, signed, no fractional part + + +*/ +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_LSB 4 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_MASK 0x0000fff0 + +/* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS + + Status of rtt_fac_sifs + + 0: not valid + + 1: valid and from L-LTF + + 2: valid and from (V)HT/HE-LTF + + 3: reserved + + +*/ +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_LSB 16 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_FAC_SIFS_STATUS_MASK 0x00030000 + +/* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS + + Status of channel frequency response dump + + + + + + + + +*/ +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_LSB 18 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CFR_STATUS_MASK 0x00040000 + +/* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS + + Status of channel impulse response dump + + + + + + + + +*/ +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_LSB 19 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CIR_STATUS_MASK 0x00080000 + +/* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE + + Channel dump size.  It shows how many tones in CFR in + one chain, for example, it will show 52 for Legacy20 and 484 + for VHT160 + + + + +*/ +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_LSB 20 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_CHANNEL_DUMP_SIZE_MASK 0x7ff00000 + +/* Description PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE + + Indicator showing if HW IFFT mode or SW IFFT mode + + + + + + + + +*/ +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_OFFSET 0x0000001c +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_LSB 31 +#define PHYRX_PKT_END_INFO_7_RX_LOCATION_INFO_DETAILS_RTT_HW_IFFT_MODE_MASK 0x80000000 + +/* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS + + Indicate if BTCF is used to capture the timestamps + + + + + + + + +*/ +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_LSB 0 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_BTCF_STATUS_MASK 0x00000001 + +/* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE + + Indicate preamble type + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +*/ +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_LSB 1 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PREAMBLE_TYPE_MASK 0x0000003e + +/* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG + + Indicate the bandwidth of L-LTF + + + + + + + + + + + + +*/ +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_LSB 6 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_LEG_MASK 0x000000c0 + +/* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT + + Indicate the bandwidth of (V)HT/HE-LTF + + + + + + + + + + + + +*/ +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_LSB 8 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_PKT_BW_VHT_MASK 0x00000300 + +/* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE + + Indicate GI (guard interval) type + + + + HE related GI. Can also be used + for HE + + HE related GI. Can also be used + for HE + + HE related GI + + HE related GI + + +*/ +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_LSB 10 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_GI_TYPE_MASK 0x00000c00 + +/* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE + + Bits 0~4 indicate MCS rate, if Legacy, + + 0: 48 Mbps, + + 1: 24 Mbps, + + 2: 12 Mbps, + + 3: 6 Mbps, + + 4: 54 Mbps, + + 5: 36 Mbps, + + 6: 18 Mbps, + + 7: 9 Mbps, + + + + if HT, 0-7: MCS0-MCS7, + + if VHT, 0-9: MCS0-MCS9, + + + +*/ +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_LSB 12 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_MCS_RATE_MASK 0x0001f000 + +/* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN + + For 20/40/80, this field shows the first selected Rx + chain that is used in HW IFFT mode + + + + For 80+80, this field shows the selected pri80 Rx chain + that is used in HW IFFT mode + + + + + + + + + + + + + + + + + + + + +*/ +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_LSB 17 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_MASK 0x000e0000 + +/* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80 + + For 20/40/80, this field shows the second selected Rx + chain that is used in HW IFFT mode + + + + For 80+80, this field shows the selected ext80 Rx chain + that is used in HW IFFT mode + + + + + + + + + + + + + + + + + + + + +*/ +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_LSB 20 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_STRONGEST_CHAIN_EXT80_MASK 0x00700000 + +/* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK + + Rx chain mask, each bit is a Rx chain + + 0: the Rx chain is not used + + 1: the Rx chain is used + + Support up to 8 Rx chains + + +*/ +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_LSB 23 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RTT_RX_CHAIN_MASK_MASK 0x7f800000 + +/* Description PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3 + + +*/ +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_OFFSET 0x00000020 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_LSB 31 +#define PHYRX_PKT_END_INFO_8_RX_LOCATION_INFO_DETAILS_RESERVED_3_MASK 0x80000000 + +/* Description PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS + + RX packet start timestamp + + + + It reports the time the first L-STF ADC sample arrived + at RX antenna + + + + clock unit is 480MHz + + +*/ +#define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_OFFSET 0x00000024 +#define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_LSB 0 +#define PHYRX_PKT_END_INFO_9_RX_LOCATION_INFO_DETAILS_RX_START_TS_MASK 0xffffffff + +/* Description PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS + + RX packet end timestamp + + + + It reports the time the last symbol's last ADC sample + arrived at RX antenna + + + + clock unit is 480MHz + + +*/ +#define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_OFFSET 0x00000028 +#define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_LSB 0 +#define PHYRX_PKT_END_INFO_10_RX_LOCATION_INFO_DETAILS_RX_END_TS_MASK 0xffffffff + +/* Description PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START + + The phase of the SFO of the first symbol's first FFT + input sample + + + + 12 bits, signed 6.6. 6 bits integer to cover -66.7ns to + 66.7ns, and 6 bits fraction to provide a resolution of + 0.03ns + + + + clock unit is 480MHz + + +*/ +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_LSB 0 +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_START_MASK 0x00000fff + +/* Description PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END + + The phase of the SFO of the last symbol's last FFT input + sample + + + + 12 bits, signed 6.6. 6 bits integer to cover -66.7ns to + 66.7ns, and 6 bits fraction to provide a resolution of + 0.03ns + + + + clock unit is 480MHz + + +*/ +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_LSB 12 +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_SFO_PHASE_PKT_END_MASK 0x00fff000 + +/* Description PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8 + + The high 8 bits of the 40 bits pointer pointed to the + external RTT channel information buffer + + + + 8 bits + + +*/ +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x0000002c +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 24 +#define PHYRX_PKT_END_INFO_11_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0xff000000 + +/* Description PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32 + + The low 32 bits of the 40 bits pointer pointed to the + external RTT channel information buffer + + + + 32 bits + + +*/ +#define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x00000030 +#define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 +#define PHYRX_PKT_END_INFO_12_RX_LOCATION_INFO_DETAILS_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff + +/* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT + + CFO measurement. Needed for passive locationing + + + + 14 bits, signed 1.13. 13 bits fraction to provide a + resolution of 153 Hz + + + + In units of cycles/800 ns + + +*/ +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_LSB 0 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CFO_MEASUREMENT_MASK 0x00003fff + +/* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD + + Channel delay spread measurement. Needed for selecting + GI length + + + + 8 bits, unsigned. At 25 ns step. Can represent up to + 6375 ns + + + + In units of cycles @ 40 MHz + + +*/ +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_LSB 14 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_CHAN_SPREAD_MASK 0x003fc000 + +/* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL + + Indicate which timing backoff value is used + + + + + + + + + + + + +*/ +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_LSB 22 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RTT_TIMING_BACKOFF_SEL_MASK 0x00c00000 + +/* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8 + + +*/ +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_LSB 24 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RESERVED_8_MASK 0x7f000000 + +/* Description PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID + + + + + + +*/ +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_OFFSET 0x00000034 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_LSB 31 +#define PHYRX_PKT_END_INFO_13_RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID_MASK 0x80000000 + + /* EXTERNAL REFERENCE : struct rx_timing_offset_info rx_timing_offset_info_details */ + + +/* Description PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET + + Cumulative reference frequency error at end of RX + + +*/ +#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_LSB 0 +#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff + +/* Description PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED + + +*/ +#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_OFFSET 0x00000038 +#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_LSB 12 +#define PHYRX_PKT_END_INFO_14_RX_TIMING_OFFSET_INFO_DETAILS_RESERVED_MASK 0xfffff000 + + /* EXTERNAL REFERENCE : struct receive_rssi_info post_rssi_info_details */ + + +/* Description PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0 + + RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +/* Description PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +/* Description PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +/* Description PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000003c +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_15_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +/* Description PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +/* Description PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +/* Description PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +/* Description PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000040 +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define PHYRX_PKT_END_INFO_16_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +/* Description PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1 + + RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +/* Description PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +/* Description PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +/* Description PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000044 +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_17_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +/* Description PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +/* Description PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +/* Description PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +/* Description PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000048 +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define PHYRX_PKT_END_INFO_18_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +/* Description PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2 + + RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +/* Description PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +/* Description PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +/* Description PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000004c +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_19_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +/* Description PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +/* Description PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +/* Description PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +/* Description PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000050 +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define PHYRX_PKT_END_INFO_20_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +/* Description PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3 + + RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +/* Description PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +/* Description PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +/* Description PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000054 +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_21_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +/* Description PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000058 +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +/* Description PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000058 +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +/* Description PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000058 +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +/* Description PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000058 +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define PHYRX_PKT_END_INFO_22_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +/* Description PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4 + + RSSI of RX PPDU on chain 4 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000005c +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0 +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff + +/* Description PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000005c +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8 +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00 + +/* Description PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000005c +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16 +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000 + +/* Description PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000005c +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24 +#define PHYRX_PKT_END_INFO_23_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000 + +/* Description PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000060 +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0 +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff + +/* Description PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000060 +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8 +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00 + +/* Description PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000060 +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16 +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000 + +/* Description PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000060 +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24 +#define PHYRX_PKT_END_INFO_24_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000 + +/* Description PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5 + + RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000064 +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0 +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff + +/* Description PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000064 +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8 +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00 + +/* Description PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000064 +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16 +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000 + +/* Description PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000064 +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24 +#define PHYRX_PKT_END_INFO_25_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000 + +/* Description PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000068 +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0 +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff + +/* Description PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000068 +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8 +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00 + +/* Description PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000068 +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16 +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000 + +/* Description PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000068 +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24 +#define PHYRX_PKT_END_INFO_26_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000 + +/* Description PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6 + + RSSI of RX PPDU on chain 6 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000006c +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0 +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff + +/* Description PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000006c +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8 +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00 + +/* Description PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000006c +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16 +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000 + +/* Description PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000006c +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24 +#define PHYRX_PKT_END_INFO_27_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000 + +/* Description PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000070 +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0 +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff + +/* Description PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000070 +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8 +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00 + +/* Description PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000070 +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16 +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000 + +/* Description PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000070 +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24 +#define PHYRX_PKT_END_INFO_28_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000 + +/* Description PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7 + + RSSI of RX PPDU on chain 7 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000074 +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0 +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff + +/* Description PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000074 +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8 +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00 + +/* Description PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000074 +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16 +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000 + +/* Description PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000074 +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24 +#define PHYRX_PKT_END_INFO_29_POST_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000 + +/* Description PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000078 +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0 +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff + +/* Description PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000078 +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8 +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00 + +/* Description PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000078 +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16 +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000 + +/* Description PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000078 +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24 +#define PHYRX_PKT_END_INFO_30_POST_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000 + +/* Description PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0 + + Some PHY micro code status that can be put in here. + Details of definition within SW specification + + This field can be used for debugging, FW - SW message + exchange, etc. + + It could for example be a pointer to a DDR memory + location where PHY FW put some debug info. + + +*/ +#define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_OFFSET 0x0000007c +#define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_LSB 0 +#define PHYRX_PKT_END_INFO_31_PHY_SW_STATUS_31_0_MASK 0xffffffff + +/* Description PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32 + + Some PHY micro code status that can be put in here. + Details of definition within SW specification + + This field can be used for debugging, FW - SW message + exchange, etc. + + It could for example be a pointer to a DDR memory + location where PHY FW put some debug info. + + +*/ +#define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_OFFSET 0x00000080 +#define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_LSB 0 +#define PHYRX_PKT_END_INFO_32_PHY_SW_STATUS_63_32_MASK 0xffffffff + + +#endif // _PHYRX_PKT_END_INFO_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/phyrx_rssi_legacy.h b/drivers/staging/fw-api/hw/qca6750/v1/phyrx_rssi_legacy.h new file mode 100644 index 000000000000..7ace4f329568 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/phyrx_rssi_legacy.h @@ -0,0 +1,2430 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _PHYRX_RSSI_LEGACY_H_ +#define _PHYRX_RSSI_LEGACY_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "receive_rssi_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 reception_type[3:0], rx_chain_mask_type[4], reserved_0[5], receive_bandwidth[7:6], rx_chain_mask[15:8], phy_ppdu_id[31:16] +// 1 sw_phy_meta_data[31:0] +// 2 ppdu_start_timestamp[31:0] +// 3-18 struct receive_rssi_info pre_rssi_info_details; +// 19-34 struct receive_rssi_info preamble_rssi_info_details; +// 35 pre_rssi_comb[7:0], rssi_comb[15:8], normalized_pre_rssi_comb[23:16], normalized_rssi_comb[31:24] +// 36 rssi_comb_ppdu[7:0], rssi_db_to_dbm_offset[15:8], rssi_for_spatial_reuse[23:16], rssi_for_trigger_resp[31:24] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_PHYRX_RSSI_LEGACY 37 + +struct phyrx_rssi_legacy { + uint32_t reception_type : 4, //[3:0] + rx_chain_mask_type : 1, //[4] + reserved_0 : 1, //[5] + receive_bandwidth : 2, //[7:6] + rx_chain_mask : 8, //[15:8] + phy_ppdu_id : 16; //[31:16] + uint32_t sw_phy_meta_data : 32; //[31:0] + uint32_t ppdu_start_timestamp : 32; //[31:0] + struct receive_rssi_info pre_rssi_info_details; + struct receive_rssi_info preamble_rssi_info_details; + uint32_t pre_rssi_comb : 8, //[7:0] + rssi_comb : 8, //[15:8] + normalized_pre_rssi_comb : 8, //[23:16] + normalized_rssi_comb : 8; //[31:24] + uint32_t rssi_comb_ppdu : 8, //[7:0] + rssi_db_to_dbm_offset : 8, //[15:8] + rssi_for_spatial_reuse : 8, //[23:16] + rssi_for_trigger_resp : 8; //[31:24] +}; + +/* + +reception_type + + This field helps MAC SW determine which field in this + (and following TLVs) will contain valid information. For + example some RSSI info not valid in case of uplink_ofdma.. + + + + In case of UL MU OFDMA or UL MU-MIMO reception + pre-announced by MAC during trigger Tx, e-nums 0 or 1 should + be used. + + + + In case of UL MU OFDMA+MIMO reception, or in case of UL + MU reception when PHY has not been pre-informed, e-num 2 + should be used. + + If this happens, the UL MU frame in the medium is by + definition not for this device. + + As reference, see doc: + + Lithium_mac_phy_interface_hld.docx + + Chapter: 7.15.1: 11ax UL MU Reception TLV sequences when + this device is not targeted. + + + + + + + + + + PHY RX has been + instructed in advance that the upcoming reception is + frameless. This implieas that in advance it is known that + all frames will collide in the medium, and nothing can be + properly decoded... This can happen during the CTS reception + in response to the triggered MU-RTS transmission. + + MAC takes no action when seeing this e_num. For the + frameless reception the indication in pkt_end is the final + one evaluated by the MAC + + + + For the relationship between pkt_type and this field, + see the table at the end of this TLV description. + + + +rx_chain_mask_type + + Indicates if the field rx_chain_mask represents the mask + at start of reception (on which the Rssi_comb value is + based), or the setting used during the remainder of the + reception + + + + 1'b0: rxtd.listen_pri80_mask + + 1'b1: Final receive mask + + + + + +reserved_0 + + + +receive_bandwidth + + Full receive Bandwidth + + + + + + + + + + + + + + + +rx_chain_mask + + The chain mask at the start of the reception of this + frame. + + + + each bit is one antenna + + 0: the chain is NOT used + + 1: the chain is used + + + + Supports up to 8 chains + + + + Used in 11ax TPC calculations for UL OFDMA/MIMO and has + to be in sync with the rssi_comb value as this is also used + by the MAC for the TPC calculations. + + + +phy_ppdu_id + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + + +sw_phy_meta_data + + 32 bit Meta data that SW can program in a 32 bit PHY + register and PHY will insert the value in every + RX_RSSI_LEGACY TLV that it generates. + + SW uses this field to embed among other things some SW + channel info. + +ppdu_start_timestamp + + Timestamp that indicates when the PPDU that contained + this MPDU started on the medium. + + + + Note that PHY will detect the start later, and will have + to derive out of the preamble info when the frame actually + appeared on the medium + + + +struct receive_rssi_info pre_rssi_info_details + + This field is not valid when reception_is_uplink_ofdma + + + + Overview of the pre-RSSI values. That is RSSI values + measured on the medium before this reception started. + +struct receive_rssi_info preamble_rssi_info_details + + This field is not valid when reception_is_uplink_ofdma + + + + Overview of the RSSI values measured during the + pre-amble phase of this reception + +pre_rssi_comb + + Combined pre_rssi of all chains. Based on primary + channel RSSI. + + + + RSSI is reported as 8b signed values. Nominally value is + in dB units above or below the noisefloor(minCCApwr). + + + + The resolution can be: + + 1dB or 0.5dB. This is statically configured within the + PHY and MAC + + + + In case of 1dB, the Range is: + + -128dB to 127dB + + + + In case of 0.5dB, the Range is: + + -64dB to 63.5dB + + + + + +rssi_comb + + Combined rssi of all chains. Based on primary channel + RSSI. + + + + RSSI is reported as 8b signed values. Nominally value is + in dB units above or below the noisefloor(minCCApwr). + + + + The resolution can be: + + 1dB or 0.5dB. This is statically configured within the + PHY and MAC + + + + In case of 1dB, the Range is: + + -128dB to 127dB + + + + In case of 0.5dB, the Range is: + + -64dB to 63.5dB + + + + + +normalized_pre_rssi_comb + + Combined pre_rssi of all chains, but normalized back to + a single chain. This avoids PDG from having to evaluate this + in combination with receive chain mask and perform all kinds + of pre-processing algorithms. + + + + Based on primary channel RSSI. + + + + RSSI is reported as 8b signed values. Nominally value is + in dB units above or below the noisefloor(minCCApwr). + + + + The resolution can be: + + 1dB or 0.5dB. This is statically configured within the + PHY and MAC + + + + In case of 1dB, the Range is: + + -128dB to 127dB + + + + In case of 0.5dB, the Range is: + + -64dB to 63.5dB + + + + + +normalized_rssi_comb + + Combined rssi of all chains, but normalized back to a + single chain. This avoids PDG from having to evaluate this + in combination with receive chain mask and perform all kinds + of pre-processing algorithms. + + + + Based on primary channel RSSI. + + + + RSSI is reported as 8b signed values. Nominally value is + in dB units above or below the noisefloor(minCCApwr). + + + + The resolution can be: + + 1dB or 0.5dB. This is statically configured within the + PHY and MAC + + In case of 1dB, the Range is: + + -128dB to 127dB + + + + In case of 0.5dB, the Range is: + + -64dB to 63.5dB + + + + + +rssi_comb_ppdu + + Combined rssi of all chains, based on active + RUs/subchannels, a.k.a. rssi_pkt_bw_mac + + + + RSSI is reported as 8b signed values. Nominally value is + in dB units above or below the noisefloor(minCCApwr). + + + + The resolution can be: + + 1dB or 0.5dB. This is statically configured within the + PHY and MAC + + + + In case of 1dB, the Range is: + + -128dB to 127dB + + + + In case of 0.5dB, the Range is: + + -64dB to 63.5dB + + + + When packet BW is 20 MHz, + + rssi_comb_ppdu = rssi_comb. + + + + When packet BW > 20 MHz, + + rssi_comb < rssi_comb_ppdu because rssi_comb only + includes power of primary 20 MHz while rssi_comb_ppdu + includes power of active RUs/subchannels. + + + + + +rssi_db_to_dbm_offset + + Offset between 'dB' and 'dBm' values. SW can use this + value to convert RSSI 'dBm' values back to 'dB,' and report + both the values. + + + + When rssi_db_to_dbm_offset = 0, + + all rssi_xxx fields are defined in dB. + + + + When rssi_db_to_dbm_offset is a large negative value, + all rssi_xxx fields are defined in dBm. + + + + + +rssi_for_spatial_reuse + + RSSI to be used by HWSCH for transmit (power) selection + during an SR opportunity, reported as an 8-bit signed value + + + + The resolution can be: + + 1dB or 0.5dB. This is statically configured within the + PHY and MAC + + + + In case of 1dB, the Range is: + + -128dB to 127dB + + + + In case of 0.5dB, the Range is: + + -64dB to 63.5dB + + + + As per 802.11ax draft 3.3 subsubclauses 27.10.2.2/3, for + OBSS PD spatial reuse, the received signal strength level + should be measured from the L-STF or L-LTF (but not L-SIG), + just as measured to indicate CCA. + + + + Also, as per 802.11ax draft 3.3, for OBSS PD spatial + reuse, MAC should compare this value with its programmed + OBSS_PDlevel scaled from 20 MHz to the Rx PPDU bandwidth. + Since MAC does not do this scaling, PHY is instead expected + to normalize the reported RSSI to 20 MHz. + + + + Also as per 802.11ax draft 3.3 subsubclause 27.10.3.2, + for SRP spatial reuse, the received power level should be + measured from the L-STF or L-LTF (but not L-SIG) and + normalized to 20 MHz. + + + +rssi_for_trigger_resp + + RSSI to be used by PDG for transmit (power) selection + during trigger response, reported as an 8-bit signed value + + + + The resolution can be: + + 1dB or 0.5dB. This is statically configured within the + PHY and MAC + + + + In case of 1dB, the Range is: + + -128dB to 127dB + + + + In case of 0.5dB, the Range is: + + -64dB to 63.5dB + + + + As per 802.11ax draft 3.3 subsubclauses 28.3.14.2, for + trigger response, the received power should be measured from + the non-HE portion of the preamble of the PPDU containing + the trigger, normalized to 20 MHz, averaged over the + antennas over which the average pathloss is being computed. + + +*/ + + +/* Description PHYRX_RSSI_LEGACY_0_RECEPTION_TYPE + + This field helps MAC SW determine which field in this + (and following TLVs) will contain valid information. For + example some RSSI info not valid in case of uplink_ofdma.. + + + + In case of UL MU OFDMA or UL MU-MIMO reception + pre-announced by MAC during trigger Tx, e-nums 0 or 1 should + be used. + + + + In case of UL MU OFDMA+MIMO reception, or in case of UL + MU reception when PHY has not been pre-informed, e-num 2 + should be used. + + If this happens, the UL MU frame in the medium is by + definition not for this device. + + As reference, see doc: + + Lithium_mac_phy_interface_hld.docx + + Chapter: 7.15.1: 11ax UL MU Reception TLV sequences when + this device is not targeted. + + + + + + + + + + PHY RX has been + instructed in advance that the upcoming reception is + frameless. This implieas that in advance it is known that + all frames will collide in the medium, and nothing can be + properly decoded... This can happen during the CTS reception + in response to the triggered MU-RTS transmission. + + MAC takes no action when seeing this e_num. For the + frameless reception the indication in pkt_end is the final + one evaluated by the MAC + + + + For the relationship between pkt_type and this field, + see the table at the end of this TLV description. + + +*/ +#define PHYRX_RSSI_LEGACY_0_RECEPTION_TYPE_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_0_RECEPTION_TYPE_LSB 0 +#define PHYRX_RSSI_LEGACY_0_RECEPTION_TYPE_MASK 0x0000000f + +/* Description PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_TYPE + + Indicates if the field rx_chain_mask represents the mask + at start of reception (on which the Rssi_comb value is + based), or the setting used during the remainder of the + reception + + + + 1'b0: rxtd.listen_pri80_mask + + 1'b1: Final receive mask + + + + +*/ +#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_TYPE_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_TYPE_LSB 4 +#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_TYPE_MASK 0x00000010 + +/* Description PHYRX_RSSI_LEGACY_0_RESERVED_0 + + +*/ +#define PHYRX_RSSI_LEGACY_0_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_0_RESERVED_0_LSB 5 +#define PHYRX_RSSI_LEGACY_0_RESERVED_0_MASK 0x00000020 + +/* Description PHYRX_RSSI_LEGACY_0_RECEIVE_BANDWIDTH + + Full receive Bandwidth + + + + + + + + + + + + + + +*/ +#define PHYRX_RSSI_LEGACY_0_RECEIVE_BANDWIDTH_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_0_RECEIVE_BANDWIDTH_LSB 6 +#define PHYRX_RSSI_LEGACY_0_RECEIVE_BANDWIDTH_MASK 0x000000c0 + +/* Description PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK + + The chain mask at the start of the reception of this + frame. + + + + each bit is one antenna + + 0: the chain is NOT used + + 1: the chain is used + + + + Supports up to 8 chains + + + + Used in 11ax TPC calculations for UL OFDMA/MIMO and has + to be in sync with the rssi_comb value as this is also used + by the MAC for the TPC calculations. + + +*/ +#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_LSB 8 +#define PHYRX_RSSI_LEGACY_0_RX_CHAIN_MASK_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_0_PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + +*/ +#define PHYRX_RSSI_LEGACY_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define PHYRX_RSSI_LEGACY_0_PHY_PPDU_ID_LSB 16 +#define PHYRX_RSSI_LEGACY_0_PHY_PPDU_ID_MASK 0xffff0000 + +/* Description PHYRX_RSSI_LEGACY_1_SW_PHY_META_DATA + + 32 bit Meta data that SW can program in a 32 bit PHY + register and PHY will insert the value in every + RX_RSSI_LEGACY TLV that it generates. + + SW uses this field to embed among other things some SW + channel info. +*/ +#define PHYRX_RSSI_LEGACY_1_SW_PHY_META_DATA_OFFSET 0x00000004 +#define PHYRX_RSSI_LEGACY_1_SW_PHY_META_DATA_LSB 0 +#define PHYRX_RSSI_LEGACY_1_SW_PHY_META_DATA_MASK 0xffffffff + +/* Description PHYRX_RSSI_LEGACY_2_PPDU_START_TIMESTAMP + + Timestamp that indicates when the PPDU that contained + this MPDU started on the medium. + + + + Note that PHY will detect the start later, and will have + to derive out of the preamble info when the frame actually + appeared on the medium + + +*/ +#define PHYRX_RSSI_LEGACY_2_PPDU_START_TIMESTAMP_OFFSET 0x00000008 +#define PHYRX_RSSI_LEGACY_2_PPDU_START_TIMESTAMP_LSB 0 +#define PHYRX_RSSI_LEGACY_2_PPDU_START_TIMESTAMP_MASK 0xffffffff + + /* EXTERNAL REFERENCE : struct receive_rssi_info pre_rssi_info_details */ + + +/* Description PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0 + + RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000000c +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +/* Description PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000000c +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000000c +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +/* Description PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000000c +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +/* Description PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000010 +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +/* Description PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000010 +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000010 +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +/* Description PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000010 +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_4_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +/* Description PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1 + + RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000014 +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +/* Description PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000014 +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000014 +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +/* Description PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000014 +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_5_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +/* Description PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000018 +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +/* Description PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000018 +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000018 +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +/* Description PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000018 +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_6_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +/* Description PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2 + + RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000001c +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +/* Description PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000001c +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000001c +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +/* Description PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000001c +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_7_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +/* Description PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000020 +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +/* Description PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000020 +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000020 +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +/* Description PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000020 +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_8_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +/* Description PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3 + + RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000024 +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +/* Description PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000024 +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000024 +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +/* Description PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000024 +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_9_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +/* Description PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000028 +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +/* Description PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000028 +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000028 +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +/* Description PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000028 +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_10_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +/* Description PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4 + + RSSI of RX PPDU on chain 4 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000002c +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0 +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff + +/* Description PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000002c +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8 +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000002c +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16 +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000 + +/* Description PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000002c +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24 +#define PHYRX_RSSI_LEGACY_11_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000 + +/* Description PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000030 +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0 +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff + +/* Description PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000030 +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8 +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000030 +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16 +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000 + +/* Description PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000030 +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24 +#define PHYRX_RSSI_LEGACY_12_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000 + +/* Description PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5 + + RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000034 +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0 +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff + +/* Description PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000034 +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8 +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000034 +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16 +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000 + +/* Description PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000034 +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24 +#define PHYRX_RSSI_LEGACY_13_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000 + +/* Description PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000038 +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0 +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff + +/* Description PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000038 +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8 +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000038 +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16 +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000 + +/* Description PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000038 +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24 +#define PHYRX_RSSI_LEGACY_14_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000 + +/* Description PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6 + + RSSI of RX PPDU on chain 6 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000003c +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0 +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff + +/* Description PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000003c +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8 +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000003c +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16 +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000 + +/* Description PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000003c +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24 +#define PHYRX_RSSI_LEGACY_15_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000 + +/* Description PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000040 +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0 +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff + +/* Description PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000040 +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8 +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000040 +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16 +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000 + +/* Description PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000040 +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24 +#define PHYRX_RSSI_LEGACY_16_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000 + +/* Description PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7 + + RSSI of RX PPDU on chain 7 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000044 +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0 +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff + +/* Description PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000044 +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8 +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000044 +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16 +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000 + +/* Description PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000044 +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24 +#define PHYRX_RSSI_LEGACY_17_PRE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000 + +/* Description PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000048 +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0 +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff + +/* Description PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000048 +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8 +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000048 +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16 +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000 + +/* Description PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000048 +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24 +#define PHYRX_RSSI_LEGACY_18_PRE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000 + + /* EXTERNAL REFERENCE : struct receive_rssi_info preamble_rssi_info_details */ + + +/* Description PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0 + + RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 0x0000004c +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +/* Description PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_OFFSET 0x0000004c +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x0000004c +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +/* Description PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x0000004c +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +/* Description PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000050 +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +/* Description PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000050 +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000050 +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +/* Description PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000050 +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define PHYRX_RSSI_LEGACY_20_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +/* Description PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1 + + RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_OFFSET 0x00000054 +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +/* Description PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_OFFSET 0x00000054 +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000054 +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +/* Description PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000054 +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_21_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +/* Description PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x00000058 +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +/* Description PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x00000058 +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x00000058 +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +/* Description PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x00000058 +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define PHYRX_RSSI_LEGACY_22_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +/* Description PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2 + + RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_OFFSET 0x0000005c +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +/* Description PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_OFFSET 0x0000005c +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x0000005c +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +/* Description PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x0000005c +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_23_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +/* Description PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000060 +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +/* Description PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000060 +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000060 +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +/* Description PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000060 +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define PHYRX_RSSI_LEGACY_24_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +/* Description PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3 + + RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_OFFSET 0x00000064 +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +/* Description PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_OFFSET 0x00000064 +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000064 +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +/* Description PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000064 +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_25_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +/* Description PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x00000068 +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +/* Description PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x00000068 +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x00000068 +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +/* Description PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x00000068 +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define PHYRX_RSSI_LEGACY_26_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +/* Description PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4 + + RSSI of RX PPDU on chain 4 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_OFFSET 0x0000006c +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_LSB 0 +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN4_MASK 0x000000ff + +/* Description PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_OFFSET 0x0000006c +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_LSB 8 +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN4_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x0000006c +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_LSB 16 +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000 + +/* Description PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x0000006c +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_LSB 24 +#define PHYRX_RSSI_LEGACY_27_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000 + +/* Description PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000070 +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_LSB 0 +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff + +/* Description PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000070 +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8 +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000070 +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16 +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000 + +/* Description PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000070 +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_LSB 24 +#define PHYRX_RSSI_LEGACY_28_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000 + +/* Description PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5 + + RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_OFFSET 0x00000074 +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_LSB 0 +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN5_MASK 0x000000ff + +/* Description PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_OFFSET 0x00000074 +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_LSB 8 +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN5_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000074 +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_LSB 16 +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000 + +/* Description PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000074 +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_LSB 24 +#define PHYRX_RSSI_LEGACY_29_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000 + +/* Description PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x00000078 +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_LSB 0 +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff + +/* Description PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x00000078 +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8 +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x00000078 +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16 +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000 + +/* Description PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x00000078 +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_LSB 24 +#define PHYRX_RSSI_LEGACY_30_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000 + +/* Description PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6 + + RSSI of RX PPDU on chain 6 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_OFFSET 0x0000007c +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_LSB 0 +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN6_MASK 0x000000ff + +/* Description PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_OFFSET 0x0000007c +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_LSB 8 +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN6_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x0000007c +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_LSB 16 +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000 + +/* Description PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x0000007c +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_LSB 24 +#define PHYRX_RSSI_LEGACY_31_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000 + +/* Description PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000080 +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_LSB 0 +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff + +/* Description PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000080 +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8 +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000080 +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16 +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000 + +/* Description PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000080 +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_LSB 24 +#define PHYRX_RSSI_LEGACY_32_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000 + +/* Description PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7 + + RSSI of RX PPDU on chain 7 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_OFFSET 0x00000084 +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_LSB 0 +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN7_MASK 0x000000ff + +/* Description PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_OFFSET 0x00000084 +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_LSB 8 +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT20_CHAIN7_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000084 +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_LSB 16 +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000 + +/* Description PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000084 +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_LSB 24 +#define PHYRX_RSSI_LEGACY_33_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000 + +/* Description PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x00000088 +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_LSB 0 +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff + +/* Description PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x00000088 +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8 +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x00000088 +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16 +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000 + +/* Description PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x00000088 +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_LSB 24 +#define PHYRX_RSSI_LEGACY_34_PREAMBLE_RSSI_INFO_DETAILS_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000 + +/* Description PHYRX_RSSI_LEGACY_35_PRE_RSSI_COMB + + Combined pre_rssi of all chains. Based on primary + channel RSSI. + + + + RSSI is reported as 8b signed values. Nominally value is + in dB units above or below the noisefloor(minCCApwr). + + + + The resolution can be: + + 1dB or 0.5dB. This is statically configured within the + PHY and MAC + + + + In case of 1dB, the Range is: + + -128dB to 127dB + + + + In case of 0.5dB, the Range is: + + -64dB to 63.5dB + + + + +*/ +#define PHYRX_RSSI_LEGACY_35_PRE_RSSI_COMB_OFFSET 0x0000008c +#define PHYRX_RSSI_LEGACY_35_PRE_RSSI_COMB_LSB 0 +#define PHYRX_RSSI_LEGACY_35_PRE_RSSI_COMB_MASK 0x000000ff + +/* Description PHYRX_RSSI_LEGACY_35_RSSI_COMB + + Combined rssi of all chains. Based on primary channel + RSSI. + + + + RSSI is reported as 8b signed values. Nominally value is + in dB units above or below the noisefloor(minCCApwr). + + + + The resolution can be: + + 1dB or 0.5dB. This is statically configured within the + PHY and MAC + + + + In case of 1dB, the Range is: + + -128dB to 127dB + + + + In case of 0.5dB, the Range is: + + -64dB to 63.5dB + + + + +*/ +#define PHYRX_RSSI_LEGACY_35_RSSI_COMB_OFFSET 0x0000008c +#define PHYRX_RSSI_LEGACY_35_RSSI_COMB_LSB 8 +#define PHYRX_RSSI_LEGACY_35_RSSI_COMB_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_35_NORMALIZED_PRE_RSSI_COMB + + Combined pre_rssi of all chains, but normalized back to + a single chain. This avoids PDG from having to evaluate this + in combination with receive chain mask and perform all kinds + of pre-processing algorithms. + + + + Based on primary channel RSSI. + + + + RSSI is reported as 8b signed values. Nominally value is + in dB units above or below the noisefloor(minCCApwr). + + + + The resolution can be: + + 1dB or 0.5dB. This is statically configured within the + PHY and MAC + + + + In case of 1dB, the Range is: + + -128dB to 127dB + + + + In case of 0.5dB, the Range is: + + -64dB to 63.5dB + + + + +*/ +#define PHYRX_RSSI_LEGACY_35_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x0000008c +#define PHYRX_RSSI_LEGACY_35_NORMALIZED_PRE_RSSI_COMB_LSB 16 +#define PHYRX_RSSI_LEGACY_35_NORMALIZED_PRE_RSSI_COMB_MASK 0x00ff0000 + +/* Description PHYRX_RSSI_LEGACY_35_NORMALIZED_RSSI_COMB + + Combined rssi of all chains, but normalized back to a + single chain. This avoids PDG from having to evaluate this + in combination with receive chain mask and perform all kinds + of pre-processing algorithms. + + + + Based on primary channel RSSI. + + + + RSSI is reported as 8b signed values. Nominally value is + in dB units above or below the noisefloor(minCCApwr). + + + + The resolution can be: + + 1dB or 0.5dB. This is statically configured within the + PHY and MAC + + In case of 1dB, the Range is: + + -128dB to 127dB + + + + In case of 0.5dB, the Range is: + + -64dB to 63.5dB + + + + +*/ +#define PHYRX_RSSI_LEGACY_35_NORMALIZED_RSSI_COMB_OFFSET 0x0000008c +#define PHYRX_RSSI_LEGACY_35_NORMALIZED_RSSI_COMB_LSB 24 +#define PHYRX_RSSI_LEGACY_35_NORMALIZED_RSSI_COMB_MASK 0xff000000 + +/* Description PHYRX_RSSI_LEGACY_36_RSSI_COMB_PPDU + + Combined rssi of all chains, based on active + RUs/subchannels, a.k.a. rssi_pkt_bw_mac + + + + RSSI is reported as 8b signed values. Nominally value is + in dB units above or below the noisefloor(minCCApwr). + + + + The resolution can be: + + 1dB or 0.5dB. This is statically configured within the + PHY and MAC + + + + In case of 1dB, the Range is: + + -128dB to 127dB + + + + In case of 0.5dB, the Range is: + + -64dB to 63.5dB + + + + When packet BW is 20 MHz, + + rssi_comb_ppdu = rssi_comb. + + + + When packet BW > 20 MHz, + + rssi_comb < rssi_comb_ppdu because rssi_comb only + includes power of primary 20 MHz while rssi_comb_ppdu + includes power of active RUs/subchannels. + + + + +*/ +#define PHYRX_RSSI_LEGACY_36_RSSI_COMB_PPDU_OFFSET 0x00000090 +#define PHYRX_RSSI_LEGACY_36_RSSI_COMB_PPDU_LSB 0 +#define PHYRX_RSSI_LEGACY_36_RSSI_COMB_PPDU_MASK 0x000000ff + +/* Description PHYRX_RSSI_LEGACY_36_RSSI_DB_TO_DBM_OFFSET + + Offset between 'dB' and 'dBm' values. SW can use this + value to convert RSSI 'dBm' values back to 'dB,' and report + both the values. + + + + When rssi_db_to_dbm_offset = 0, + + all rssi_xxx fields are defined in dB. + + + + When rssi_db_to_dbm_offset is a large negative value, + all rssi_xxx fields are defined in dBm. + + + + +*/ +#define PHYRX_RSSI_LEGACY_36_RSSI_DB_TO_DBM_OFFSET_OFFSET 0x00000090 +#define PHYRX_RSSI_LEGACY_36_RSSI_DB_TO_DBM_OFFSET_LSB 8 +#define PHYRX_RSSI_LEGACY_36_RSSI_DB_TO_DBM_OFFSET_MASK 0x0000ff00 + +/* Description PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE + + RSSI to be used by HWSCH for transmit (power) selection + during an SR opportunity, reported as an 8-bit signed value + + + + The resolution can be: + + 1dB or 0.5dB. This is statically configured within the + PHY and MAC + + + + In case of 1dB, the Range is: + + -128dB to 127dB + + + + In case of 0.5dB, the Range is: + + -64dB to 63.5dB + + + + As per 802.11ax draft 3.3 subsubclauses 27.10.2.2/3, for + OBSS PD spatial reuse, the received signal strength level + should be measured from the L-STF or L-LTF (but not L-SIG), + just as measured to indicate CCA. + + + + Also, as per 802.11ax draft 3.3, for OBSS PD spatial + reuse, MAC should compare this value with its programmed + OBSS_PDlevel scaled from 20 MHz to the Rx PPDU bandwidth. + Since MAC does not do this scaling, PHY is instead expected + to normalize the reported RSSI to 20 MHz. + + + + Also as per 802.11ax draft 3.3 subsubclause 27.10.3.2, + for SRP spatial reuse, the received power level should be + measured from the L-STF or L-LTF (but not L-SIG) and + normalized to 20 MHz. + + +*/ +#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE_OFFSET 0x00000090 +#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE_LSB 16 +#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_SPATIAL_REUSE_MASK 0x00ff0000 + +/* Description PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP + + RSSI to be used by PDG for transmit (power) selection + during trigger response, reported as an 8-bit signed value + + + + The resolution can be: + + 1dB or 0.5dB. This is statically configured within the + PHY and MAC + + + + In case of 1dB, the Range is: + + -128dB to 127dB + + + + In case of 0.5dB, the Range is: + + -64dB to 63.5dB + + + + As per 802.11ax draft 3.3 subsubclauses 28.3.14.2, for + trigger response, the received power should be measured from + the non-HE portion of the preamble of the PPDU containing + the trigger, normalized to 20 MHz, averaged over the + antennas over which the average pathloss is being computed. + + +*/ +#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP_OFFSET 0x00000090 +#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP_LSB 24 +#define PHYRX_RSSI_LEGACY_36_RSSI_FOR_TRIGGER_RESP_MASK 0xff000000 + + +#endif // _PHYRX_RSSI_LEGACY_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/phyrx_user_info.h b/drivers/staging/fw-api/hw/qca6750/v1/phyrx_user_info.h new file mode 100644 index 000000000000..04ba0e7eef90 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/phyrx_user_info.h @@ -0,0 +1,337 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _PHYRX_USER_INFO_H_ +#define _PHYRX_USER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "receive_user_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-2 struct receive_user_info receive_user_info_details; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_PHYRX_USER_INFO 3 + +struct phyrx_user_info { + struct receive_user_info receive_user_info_details; +}; + +/* + +struct receive_user_info receive_user_info_details + + Overview of receive parameters that the MAC needs to + prepend to every received MSDU/MPDU. + + + + PHY RX gathers this info for the MAC +*/ + + + /* EXTERNAL REFERENCE : struct receive_user_info receive_user_info_details */ + + +/* Description PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + +*/ +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff + +/* Description PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI + + RSSI for this user + + Frequency domain RSSI measurement for this user. Based + on the channel estimate. + + + + +*/ +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x00000000 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x00ff0000 + +/* Description PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE + + Packet type: + + + + 802.11a PPDU type + + 802.11b PPDU type + + 802.11n Mixed Mode PPDU type + + 802.11ac PPDU type + + 802.11ax PPDU type + + 802.11ba (WUR) PPDU type +*/ +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000 + +/* Description PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC + + When set, use STBC transmission rates +*/ +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x00000000 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x10000000 + +/* Description PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE + + Indicates what type of reception this is. + + Basic SU reception (not + part of OFDMA or MU-MIMO) + + This is related to + DL type of reception + + This is related + to DL type of reception + + This is + related to DL type of reception + + This is related + to UL type of reception + + This is + related to UL type of reception + + This is + related to UL type of reception + + + + +*/ +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x00000000 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29 +#define PHYRX_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0xe0000000 + +/* Description PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS + + For details, refer to MCS_TYPE description + + +*/ +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x00000004 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 0 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000000f + +/* Description PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI + + Field only valid when pkt type is HT, VHT or HE. + + + + Legacy normal GI. Can also be + used for HE + + Legacy short GI. Can also be + used for HE + + HE related GI + + HE related GI + + +*/ +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x00000004 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_LSB 4 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x00000030 + +/* Description PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH + + Full receive Bandwidth + + + + + + + + + + + + + + +*/ +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x00000004 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 6 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x000000c0 + +/* Description PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP + + Bitmap, with each bit indicating if the related spatial + stream is used for this STA + + LSB related to SS 0 + + + + 0: spatial stream not used for this reception + + 1: spatial stream used for this reception + + + + +*/ +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x00000004 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 8 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff00 + +/* Description PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION + + Field only valid in case of OFDMA type receptions (DL + and UL) + + + + Indicates the RU number associated with this user. + + + + In case of reception where the transmission was DL MU + OFDMA, this field provides the RU pattern. Note that fields + ofdma_user_index and ofdma_content_channel are needed to + determine which RU (within a 40 MHz channel) was actually + assigned to this user, but this does not give info on which + 40 MHz channel was assigned to this user. Please refer + DL_ofdma_ru_* in PHYRX_PKT_END_INFO for complete RU info for + this user. + + + + In case of reception where the transmission was UL MU + OFDMA, PHY is recommended to insert the RU start index in + this field. Note that PHY may insert the RU width in + Reserved_2a[6:0]. + + +*/ +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_OFFSET 0x00000004 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_LSB 16 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_MASK 0x00ff0000 + +/* Description PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX + + Field only valid in the of DL MU OFDMA reception + + + + The user number within the RU_allocation. + + + + This is needed for SW to determine the exact RU position + within the reception. + + +*/ +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_OFFSET 0x00000004 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_LSB 24 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_MASK 0x7f000000 + +/* Description PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL + + Field only valid in the of DL MU OFDMA/MIMO reception + + + + In case of DL MU reception, this field indicates the + content channel number where PHY found the RU information + for this user + + + + This is needed for SW to determine the exact RU position + within the reception. + + + + + + + + + + +*/ +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000004 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_LSB 31 +#define PHYRX_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_MASK 0x80000000 + +/* Description PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC + + When set, use LDPC transmission rates were used. + + +*/ +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x00000008 +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 0 +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x00000001 + +/* Description PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH + + In case of UL OFDMA reception, PHY is recommended to + insert the RU width + + In Hastings80: was using Reserved_2a[6:0]. + + +*/ +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_OFFSET 0x00000008 +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_LSB 1 +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_MASK 0x000000fe + +/* Description PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A + + +*/ +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x00000008 +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 8 +#define PHYRX_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0xffffff00 + + +#endif // _PHYRX_USER_INFO_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/phyrx_vht_sig_a.h b/drivers/staging/fw-api/hw/qca6750/v1/phyrx_vht_sig_a.h new file mode 100644 index 000000000000..54374e112ee4 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/phyrx_vht_sig_a.h @@ -0,0 +1,375 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _PHYRX_VHT_SIG_A_H_ +#define _PHYRX_VHT_SIG_A_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "vht_sig_a_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct vht_sig_a_info phyrx_vht_sig_a_info_details; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_PHYRX_VHT_SIG_A 2 + +struct phyrx_vht_sig_a { + struct vht_sig_a_info phyrx_vht_sig_a_info_details; +}; + +/* + +struct vht_sig_a_info phyrx_vht_sig_a_info_details + + See detailed description of the STRUCT +*/ + + + /* EXTERNAL REFERENCE : struct vht_sig_a_info phyrx_vht_sig_a_info_details */ + + +/* Description PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH + + Packet bandwidth + + + + + + + + + + + + + + +*/ +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x00000003 + +/* Description PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0 + + Reserved. Set to 1 by MAC, PHY should ignore + + +*/ +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x00000004 + +/* Description PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC + + Space time block coding: + + Indicates STBC is disabled + + Indicates STBC is enabled on + all streams + + +*/ +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x00000008 + +/* Description PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID + + In a SU VHT PPDU, if the PPDU carries MPDU(s) addressed + to an AP or to a mesh STA, the Group ID field is set to 0, + otherwise it is set to 63. In an NDP PPDU the Group ID is + set according to IEEE 802.11ac_D1.0 Section 9.30.6 + (Transmission of a VHT NDP). For a MU-MIMO PPDU the Group ID + is set as in 802.11ac_D1.0 Section 22.3.11.3 (Group ID). + +*/ +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x000003f0 + +/* Description PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS + + For MU: + + 3 bits/user with maximum of 4 users (user u uses + + vht_sig_a[0][10+3u] - vht_sig_a[0][12+3u]), u = 0, 1, 2, + 3) + + Set to 0 for 0 space time streams + + Set to 1 for 1 space time stream + + Set to 2 for 2 space time streams + + Set to 3 for 3 space time streams + + Set to 4 for 4 space time streams (not supported in Wifi + 3.0) + + Values 5-7 are reserved + + In this field, references to user u should be + interpreted as MU user u. As described in the previous + chapter in this document (see chapter on User number), the + MU user value for a given client is defined for each MU + group that the client participates in. The MU user number is + not related to the internal user number that is used within + the BFer. + + + + + + For SU: + + vht_sig_a[0][12:10] + + Set to 0 for 1 space time stream + + Set to 1 for 2 space time streams + + Set to 2 for 3 space time streams + + Set to 3 for 4 space time streams + + Set to 4 for 5 space time streams + + Set to 5 for 6 space time streams + + Set to 6 for 7 space time streams + + Set to 7 for 8 space time streams + + + + vht_sig_a[0][21:13] + + Partial AID: + + Set to the value of the TXVECTOR parameter PARTIAL_AID. + Partial AID provides an abbreviated indication of the + intended recipient(s) of the frame (see IEEE802.11ac_D1.0 + Section 9.17a (Partial AID in VHT PPDUs)). + + +*/ +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x003ffc00 + +/* Description PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED + + E_num 0 txop_ps_allowed Not supported: If set to by + VHT AP if it allows non-AP VHT STAs in TXOP power save mode + to enter Doze state during a TXOP + + Otherwise + + +*/ +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x00400000 + +/* Description PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B + + Reserved: Should be set to 1 by the MAC and ignored by + the PHY +*/ +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x00800000 + +/* Description PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0 + + This field is not part of HT-SIG: + + Reserved: Should be set to 0 by the MAC and ignored by + the PHY +*/ +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24 +#define PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0xff000000 + +/* Description PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING + + Indicates short guard interval + is not used in the data field + + Indicates short guard interval is + used in the data field + + Indicates short guard + interval is used in the data field and NSYM mod 10 = 9 + + NSYM is defined in IEEE802.11ac_D1.0 Section 22.4.3 + (TXTIME and PSDU_LENGTH calculation). + + +*/ +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 0 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x00000003 + +/* Description PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING + + For an SU PPDU, B2 is set to 0 for BCC, 1 for LDPC For + an MU PPDU, if the MU[0] NSTS field is nonzero(#6773), then + B2 indicates the coding used for user 0; set to 0 for BCC + and 1 for LDPC. If the MU[0] NSTS field is 0, then this + field is reserved and set to 1 +*/ +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 2 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x00000004 + +/* Description PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL + + Set to 1 if the LDPC PPDU encoding process (if an SU + PPDU), or at least one LDPC user's PPDU encoding process (if + an MU PPDU), results in an extra OFDM symbol (or symbols) as + described in 22.3.10.5.4 (LDPC coding) and 22.3.10.5.5 + (Encoding process for MU PPDUs). Set to 0 otherwise. +*/ +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 3 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x00000008 + +/* Description PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS + + For SU: + + Set to 0 for BPSK 1/2 + + Set to 1 for QPSK 1/2 + + Set to 2 for QPSK 3/4 + + Set to 3 for 16-QAM 1/2 + + Set to 4 for 16-QAM 3/4 + + Set to 5 for 64-QAM 2/3 + + Set to 6 for 64-QAM 3/4 + + Set to 7 for 64-QAM 5/6 + + Set to 8 for 256-QAM 3/4 + + Set to 9 for 256-QAM 5/6 + + For MU: + + If NSTS for user 1 is non-zero, then vht_sig_a[1][4] + indicates coding for user 1: set to 0 for BCC, 1 for LDPC. + + If NSTS for user 1 is set to 0, then vht_sig_a[1][4] is + reserved and set to 1. + + If NSTS for user 2 is non-zero, then vht_sig_a[1][5] + indicates coding for user 2: set to 0 for BCC, 1 for LDPC. + + If NSTS for user 2 is set to 0, then vht_sig_a[1][5] is + reserved and set to 1. + + If NSTS for user 3 is non-zero, then vht_sig_a[1][6] + indicates coding for user 3: set to 0 for BCC, 1 for LDPC. + + If NSTS for user 3 is set to 0, then vht_sig_a[1][6] is + reserved and set to 1. + + vht_sig_a[1][7] is reserved and set to 1 + + +*/ +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 4 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f0 + +/* Description PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED + + For SU: + + Set to 1 if a Beamforming steering matrix is applied to + the waveform in an SU transmission as described in + IEEE802.11ac_D1.0 Section 19.3.11.11.2 (Spatial mapping), + set to 0 otherwise. + + For MU: + + Reserved and set to 1 + + +*/ +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 8 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x00000100 + +/* Description PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1 + + Reserved and set to 1. +*/ +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 9 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x00000200 + +/* Description PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC + + CRC calculated as in IEEE802.11ac_D1.0 Section + 19.3.9.4.4 (CRC calculation for HTSIG) with C7 in + vht_sig_a[1][10], etc. +*/ +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 10 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc00 + +/* Description PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL + + Used to terminate the trellis of the convolutional + decoder. Set to 0. +*/ +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 18 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc0000 + +/* Description PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1 + + This field is not part of HT-SIG: + + Reserved: Should be set to 0 by the MAC and ignored by + the PHY +*/ +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x00000004 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 24 +#define PHYRX_VHT_SIG_A_1_PHYRX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0xff000000 + + +#endif // _PHYRX_VHT_SIG_A_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/receive_rssi_info.h b/drivers/staging/fw-api/hw/qca6750/v1/receive_rssi_info.h new file mode 100644 index 000000000000..57ab8a943365 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/receive_rssi_info.h @@ -0,0 +1,1262 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RECEIVE_RSSI_INFO_H_ +#define _RECEIVE_RSSI_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 rssi_pri20_chain0[7:0], rssi_ext20_chain0[15:8], rssi_ext40_low20_chain0[23:16], rssi_ext40_high20_chain0[31:24] +// 1 rssi_ext80_low20_chain0[7:0], rssi_ext80_low_high20_chain0[15:8], rssi_ext80_high_low20_chain0[23:16], rssi_ext80_high20_chain0[31:24] +// 2 rssi_pri20_chain1[7:0], rssi_ext20_chain1[15:8], rssi_ext40_low20_chain1[23:16], rssi_ext40_high20_chain1[31:24] +// 3 rssi_ext80_low20_chain1[7:0], rssi_ext80_low_high20_chain1[15:8], rssi_ext80_high_low20_chain1[23:16], rssi_ext80_high20_chain1[31:24] +// 4 rssi_pri20_chain2[7:0], rssi_ext20_chain2[15:8], rssi_ext40_low20_chain2[23:16], rssi_ext40_high20_chain2[31:24] +// 5 rssi_ext80_low20_chain2[7:0], rssi_ext80_low_high20_chain2[15:8], rssi_ext80_high_low20_chain2[23:16], rssi_ext80_high20_chain2[31:24] +// 6 rssi_pri20_chain3[7:0], rssi_ext20_chain3[15:8], rssi_ext40_low20_chain3[23:16], rssi_ext40_high20_chain3[31:24] +// 7 rssi_ext80_low20_chain3[7:0], rssi_ext80_low_high20_chain3[15:8], rssi_ext80_high_low20_chain3[23:16], rssi_ext80_high20_chain3[31:24] +// 8 rssi_pri20_chain4[7:0], rssi_ext20_chain4[15:8], rssi_ext40_low20_chain4[23:16], rssi_ext40_high20_chain4[31:24] +// 9 rssi_ext80_low20_chain4[7:0], rssi_ext80_low_high20_chain4[15:8], rssi_ext80_high_low20_chain4[23:16], rssi_ext80_high20_chain4[31:24] +// 10 rssi_pri20_chain5[7:0], rssi_ext20_chain5[15:8], rssi_ext40_low20_chain5[23:16], rssi_ext40_high20_chain5[31:24] +// 11 rssi_ext80_low20_chain5[7:0], rssi_ext80_low_high20_chain5[15:8], rssi_ext80_high_low20_chain5[23:16], rssi_ext80_high20_chain5[31:24] +// 12 rssi_pri20_chain6[7:0], rssi_ext20_chain6[15:8], rssi_ext40_low20_chain6[23:16], rssi_ext40_high20_chain6[31:24] +// 13 rssi_ext80_low20_chain6[7:0], rssi_ext80_low_high20_chain6[15:8], rssi_ext80_high_low20_chain6[23:16], rssi_ext80_high20_chain6[31:24] +// 14 rssi_pri20_chain7[7:0], rssi_ext20_chain7[15:8], rssi_ext40_low20_chain7[23:16], rssi_ext40_high20_chain7[31:24] +// 15 rssi_ext80_low20_chain7[7:0], rssi_ext80_low_high20_chain7[15:8], rssi_ext80_high_low20_chain7[23:16], rssi_ext80_high20_chain7[31:24] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RECEIVE_RSSI_INFO 16 + +struct receive_rssi_info { + uint32_t rssi_pri20_chain0 : 8, //[7:0] + rssi_ext20_chain0 : 8, //[15:8] + rssi_ext40_low20_chain0 : 8, //[23:16] + rssi_ext40_high20_chain0 : 8; //[31:24] + uint32_t rssi_ext80_low20_chain0 : 8, //[7:0] + rssi_ext80_low_high20_chain0 : 8, //[15:8] + rssi_ext80_high_low20_chain0 : 8, //[23:16] + rssi_ext80_high20_chain0 : 8; //[31:24] + uint32_t rssi_pri20_chain1 : 8, //[7:0] + rssi_ext20_chain1 : 8, //[15:8] + rssi_ext40_low20_chain1 : 8, //[23:16] + rssi_ext40_high20_chain1 : 8; //[31:24] + uint32_t rssi_ext80_low20_chain1 : 8, //[7:0] + rssi_ext80_low_high20_chain1 : 8, //[15:8] + rssi_ext80_high_low20_chain1 : 8, //[23:16] + rssi_ext80_high20_chain1 : 8; //[31:24] + uint32_t rssi_pri20_chain2 : 8, //[7:0] + rssi_ext20_chain2 : 8, //[15:8] + rssi_ext40_low20_chain2 : 8, //[23:16] + rssi_ext40_high20_chain2 : 8; //[31:24] + uint32_t rssi_ext80_low20_chain2 : 8, //[7:0] + rssi_ext80_low_high20_chain2 : 8, //[15:8] + rssi_ext80_high_low20_chain2 : 8, //[23:16] + rssi_ext80_high20_chain2 : 8; //[31:24] + uint32_t rssi_pri20_chain3 : 8, //[7:0] + rssi_ext20_chain3 : 8, //[15:8] + rssi_ext40_low20_chain3 : 8, //[23:16] + rssi_ext40_high20_chain3 : 8; //[31:24] + uint32_t rssi_ext80_low20_chain3 : 8, //[7:0] + rssi_ext80_low_high20_chain3 : 8, //[15:8] + rssi_ext80_high_low20_chain3 : 8, //[23:16] + rssi_ext80_high20_chain3 : 8; //[31:24] + uint32_t rssi_pri20_chain4 : 8, //[7:0] + rssi_ext20_chain4 : 8, //[15:8] + rssi_ext40_low20_chain4 : 8, //[23:16] + rssi_ext40_high20_chain4 : 8; //[31:24] + uint32_t rssi_ext80_low20_chain4 : 8, //[7:0] + rssi_ext80_low_high20_chain4 : 8, //[15:8] + rssi_ext80_high_low20_chain4 : 8, //[23:16] + rssi_ext80_high20_chain4 : 8; //[31:24] + uint32_t rssi_pri20_chain5 : 8, //[7:0] + rssi_ext20_chain5 : 8, //[15:8] + rssi_ext40_low20_chain5 : 8, //[23:16] + rssi_ext40_high20_chain5 : 8; //[31:24] + uint32_t rssi_ext80_low20_chain5 : 8, //[7:0] + rssi_ext80_low_high20_chain5 : 8, //[15:8] + rssi_ext80_high_low20_chain5 : 8, //[23:16] + rssi_ext80_high20_chain5 : 8; //[31:24] + uint32_t rssi_pri20_chain6 : 8, //[7:0] + rssi_ext20_chain6 : 8, //[15:8] + rssi_ext40_low20_chain6 : 8, //[23:16] + rssi_ext40_high20_chain6 : 8; //[31:24] + uint32_t rssi_ext80_low20_chain6 : 8, //[7:0] + rssi_ext80_low_high20_chain6 : 8, //[15:8] + rssi_ext80_high_low20_chain6 : 8, //[23:16] + rssi_ext80_high20_chain6 : 8; //[31:24] + uint32_t rssi_pri20_chain7 : 8, //[7:0] + rssi_ext20_chain7 : 8, //[15:8] + rssi_ext40_low20_chain7 : 8, //[23:16] + rssi_ext40_high20_chain7 : 8; //[31:24] + uint32_t rssi_ext80_low20_chain7 : 8, //[7:0] + rssi_ext80_low_high20_chain7 : 8, //[15:8] + rssi_ext80_high_low20_chain7 : 8, //[23:16] + rssi_ext80_high20_chain7 : 8; //[31:24] +}; + +/* + +rssi_pri20_chain0 + + RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext20_chain0 + + RSSI of RX PPDU on chain 0 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext40_low20_chain0 + + RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext40_high20_chain0 + + RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext80_low20_chain0 + + RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext80_low_high20_chain0 + + RSSI of RX PPDU on chain 0 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext80_high_low20_chain0 + + RSSI of RX PPDU on chain 0 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext80_high20_chain0 + + RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_pri20_chain1 + + RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext20_chain1 + + RSSI of RX PPDU on chain 1 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext40_low20_chain1 + + RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext40_high20_chain1 + + RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext80_low20_chain1 + + RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext80_low_high20_chain1 + + RSSI of RX PPDU on chain 1 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext80_high_low20_chain1 + + RSSI of RX PPDU on chain 1 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext80_high20_chain1 + + RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_pri20_chain2 + + RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext20_chain2 + + RSSI of RX PPDU on chain 2 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext40_low20_chain2 + + RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext40_high20_chain2 + + RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext80_low20_chain2 + + RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext80_low_high20_chain2 + + RSSI of RX PPDU on chain 2 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext80_high_low20_chain2 + + RSSI of RX PPDU on chain 2 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext80_high20_chain2 + + RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_pri20_chain3 + + RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext20_chain3 + + RSSI of RX PPDU on chain 3 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext40_low20_chain3 + + RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext40_high20_chain3 + + RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext80_low20_chain3 + + RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext80_low_high20_chain3 + + RSSI of RX PPDU on chain 3 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext80_high_low20_chain3 + + RSSI of RX PPDU on chain 3 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext80_high20_chain3 + + RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_pri20_chain4 + + RSSI of RX PPDU on chain 4 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext20_chain4 + + RSSI of RX PPDU on chain 4 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext40_low20_chain4 + + RSSI of RX PPDU on chain 4 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext40_high20_chain4 + + RSSI of RX PPDU on chain 4 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext80_low20_chain4 + + RSSI of RX PPDU on chain 4 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext80_low_high20_chain4 + + RSSI of RX PPDU on chain 4 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext80_high_low20_chain4 + + RSSI of RX PPDU on chain 4 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext80_high20_chain4 + + RSSI of RX PPDU on chain 4 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_pri20_chain5 + + RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext20_chain5 + + RSSI of RX PPDU on chain 5 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext40_low20_chain5 + + RSSI of RX PPDU on chain 5 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext40_high20_chain5 + + RSSI of RX PPDU on chain 5 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext80_low20_chain5 + + RSSI of RX PPDU on chain 5 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext80_low_high20_chain5 + + RSSI of RX PPDU on chain 5 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext80_high_low20_chain5 + + RSSI of RX PPDU on chain 5 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext80_high20_chain5 + + RSSI of RX PPDU on chain 5 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_pri20_chain6 + + RSSI of RX PPDU on chain 6 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext20_chain6 + + RSSI of RX PPDU on chain 6 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext40_low20_chain6 + + RSSI of RX PPDU on chain 6 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext40_high20_chain6 + + RSSI of RX PPDU on chain 6 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext80_low20_chain6 + + RSSI of RX PPDU on chain 6 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext80_low_high20_chain6 + + RSSI of RX PPDU on chain 6 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext80_high_low20_chain6 + + RSSI of RX PPDU on chain 6 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext80_high20_chain6 + + RSSI of RX PPDU on chain 6 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_pri20_chain7 + + RSSI of RX PPDU on chain 7 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext20_chain7 + + RSSI of RX PPDU on chain 7 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext40_low20_chain7 + + RSSI of RX PPDU on chain 7 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext40_high20_chain7 + + RSSI of RX PPDU on chain 7 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext80_low20_chain7 + + RSSI of RX PPDU on chain 7 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext80_low_high20_chain7 + + RSSI of RX PPDU on chain 7 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext80_high_low20_chain7 + + RSSI of RX PPDU on chain 7 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. + +rssi_ext80_high20_chain7 + + RSSI of RX PPDU on chain 7 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ + + +/* Description RECEIVE_RSSI_INFO_0_RSSI_PRI20_CHAIN0 + + RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_0_RSSI_PRI20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_0_RSSI_PRI20_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_0_RSSI_PRI20_CHAIN0_MASK 0x000000ff + +/* Description RECEIVE_RSSI_INFO_0_RSSI_EXT20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_0_RSSI_EXT20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_0_RSSI_EXT20_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_0_RSSI_EXT20_CHAIN0_MASK 0x0000ff00 + +/* Description RECEIVE_RSSI_INFO_0_RSSI_EXT40_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_LOW20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_LOW20_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_LOW20_CHAIN0_MASK 0x00ff0000 + +/* Description RECEIVE_RSSI_INFO_0_RSSI_EXT40_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_HIGH20_CHAIN0_OFFSET 0x00000000 +#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_HIGH20_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_0_RSSI_EXT40_HIGH20_CHAIN0_MASK 0xff000000 + +/* Description RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW20_CHAIN0_LSB 0 +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW20_CHAIN0_MASK 0x000000ff + +/* Description RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW_HIGH20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW_HIGH20_CHAIN0_LSB 8 +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_LOW_HIGH20_CHAIN0_MASK 0x0000ff00 + +/* Description RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH_LOW20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH_LOW20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH_LOW20_CHAIN0_LSB 16 +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH_LOW20_CHAIN0_MASK 0x00ff0000 + +/* Description RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH20_CHAIN0 + + RSSI of RX PPDU on chain 0 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH20_CHAIN0_OFFSET 0x00000004 +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH20_CHAIN0_LSB 24 +#define RECEIVE_RSSI_INFO_1_RSSI_EXT80_HIGH20_CHAIN0_MASK 0xff000000 + +/* Description RECEIVE_RSSI_INFO_2_RSSI_PRI20_CHAIN1 + + RSSI of RX PPDU on chain 1 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_2_RSSI_PRI20_CHAIN1_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_2_RSSI_PRI20_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_2_RSSI_PRI20_CHAIN1_MASK 0x000000ff + +/* Description RECEIVE_RSSI_INFO_2_RSSI_EXT20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_2_RSSI_EXT20_CHAIN1_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_2_RSSI_EXT20_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_2_RSSI_EXT20_CHAIN1_MASK 0x0000ff00 + +/* Description RECEIVE_RSSI_INFO_2_RSSI_EXT40_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_LOW20_CHAIN1_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_LOW20_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_LOW20_CHAIN1_MASK 0x00ff0000 + +/* Description RECEIVE_RSSI_INFO_2_RSSI_EXT40_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_HIGH20_CHAIN1_OFFSET 0x00000008 +#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_HIGH20_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_2_RSSI_EXT40_HIGH20_CHAIN1_MASK 0xff000000 + +/* Description RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW20_CHAIN1_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW20_CHAIN1_LSB 0 +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW20_CHAIN1_MASK 0x000000ff + +/* Description RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW_HIGH20_CHAIN1_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW_HIGH20_CHAIN1_LSB 8 +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_LOW_HIGH20_CHAIN1_MASK 0x0000ff00 + +/* Description RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH_LOW20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH_LOW20_CHAIN1_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH_LOW20_CHAIN1_LSB 16 +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH_LOW20_CHAIN1_MASK 0x00ff0000 + +/* Description RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH20_CHAIN1 + + RSSI of RX PPDU on chain 1 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH20_CHAIN1_OFFSET 0x0000000c +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH20_CHAIN1_LSB 24 +#define RECEIVE_RSSI_INFO_3_RSSI_EXT80_HIGH20_CHAIN1_MASK 0xff000000 + +/* Description RECEIVE_RSSI_INFO_4_RSSI_PRI20_CHAIN2 + + RSSI of RX PPDU on chain 2 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_4_RSSI_PRI20_CHAIN2_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_4_RSSI_PRI20_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_4_RSSI_PRI20_CHAIN2_MASK 0x000000ff + +/* Description RECEIVE_RSSI_INFO_4_RSSI_EXT20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_4_RSSI_EXT20_CHAIN2_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_4_RSSI_EXT20_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_4_RSSI_EXT20_CHAIN2_MASK 0x0000ff00 + +/* Description RECEIVE_RSSI_INFO_4_RSSI_EXT40_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_LOW20_CHAIN2_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_LOW20_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_LOW20_CHAIN2_MASK 0x00ff0000 + +/* Description RECEIVE_RSSI_INFO_4_RSSI_EXT40_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_HIGH20_CHAIN2_OFFSET 0x00000010 +#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_HIGH20_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_4_RSSI_EXT40_HIGH20_CHAIN2_MASK 0xff000000 + +/* Description RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW20_CHAIN2_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW20_CHAIN2_LSB 0 +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW20_CHAIN2_MASK 0x000000ff + +/* Description RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW_HIGH20_CHAIN2_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW_HIGH20_CHAIN2_LSB 8 +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_LOW_HIGH20_CHAIN2_MASK 0x0000ff00 + +/* Description RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH_LOW20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH_LOW20_CHAIN2_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH_LOW20_CHAIN2_LSB 16 +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH_LOW20_CHAIN2_MASK 0x00ff0000 + +/* Description RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH20_CHAIN2 + + RSSI of RX PPDU on chain 2 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH20_CHAIN2_OFFSET 0x00000014 +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH20_CHAIN2_LSB 24 +#define RECEIVE_RSSI_INFO_5_RSSI_EXT80_HIGH20_CHAIN2_MASK 0xff000000 + +/* Description RECEIVE_RSSI_INFO_6_RSSI_PRI20_CHAIN3 + + RSSI of RX PPDU on chain 3 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_6_RSSI_PRI20_CHAIN3_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_6_RSSI_PRI20_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_6_RSSI_PRI20_CHAIN3_MASK 0x000000ff + +/* Description RECEIVE_RSSI_INFO_6_RSSI_EXT20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_6_RSSI_EXT20_CHAIN3_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_6_RSSI_EXT20_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_6_RSSI_EXT20_CHAIN3_MASK 0x0000ff00 + +/* Description RECEIVE_RSSI_INFO_6_RSSI_EXT40_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_LOW20_CHAIN3_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_LOW20_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_LOW20_CHAIN3_MASK 0x00ff0000 + +/* Description RECEIVE_RSSI_INFO_6_RSSI_EXT40_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_HIGH20_CHAIN3_OFFSET 0x00000018 +#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_HIGH20_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_6_RSSI_EXT40_HIGH20_CHAIN3_MASK 0xff000000 + +/* Description RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW20_CHAIN3_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW20_CHAIN3_LSB 0 +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW20_CHAIN3_MASK 0x000000ff + +/* Description RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW_HIGH20_CHAIN3_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW_HIGH20_CHAIN3_LSB 8 +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_LOW_HIGH20_CHAIN3_MASK 0x0000ff00 + +/* Description RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH_LOW20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH_LOW20_CHAIN3_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH_LOW20_CHAIN3_LSB 16 +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH_LOW20_CHAIN3_MASK 0x00ff0000 + +/* Description RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH20_CHAIN3 + + RSSI of RX PPDU on chain 3 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH20_CHAIN3_OFFSET 0x0000001c +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH20_CHAIN3_LSB 24 +#define RECEIVE_RSSI_INFO_7_RSSI_EXT80_HIGH20_CHAIN3_MASK 0xff000000 + +/* Description RECEIVE_RSSI_INFO_8_RSSI_PRI20_CHAIN4 + + RSSI of RX PPDU on chain 4 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_8_RSSI_PRI20_CHAIN4_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_8_RSSI_PRI20_CHAIN4_LSB 0 +#define RECEIVE_RSSI_INFO_8_RSSI_PRI20_CHAIN4_MASK 0x000000ff + +/* Description RECEIVE_RSSI_INFO_8_RSSI_EXT20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_8_RSSI_EXT20_CHAIN4_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_8_RSSI_EXT20_CHAIN4_LSB 8 +#define RECEIVE_RSSI_INFO_8_RSSI_EXT20_CHAIN4_MASK 0x0000ff00 + +/* Description RECEIVE_RSSI_INFO_8_RSSI_EXT40_LOW20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_LOW20_CHAIN4_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_LOW20_CHAIN4_LSB 16 +#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_LOW20_CHAIN4_MASK 0x00ff0000 + +/* Description RECEIVE_RSSI_INFO_8_RSSI_EXT40_HIGH20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_HIGH20_CHAIN4_OFFSET 0x00000020 +#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_HIGH20_CHAIN4_LSB 24 +#define RECEIVE_RSSI_INFO_8_RSSI_EXT40_HIGH20_CHAIN4_MASK 0xff000000 + +/* Description RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW20_CHAIN4_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW20_CHAIN4_LSB 0 +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW20_CHAIN4_MASK 0x000000ff + +/* Description RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW_HIGH20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW_HIGH20_CHAIN4_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW_HIGH20_CHAIN4_LSB 8 +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_LOW_HIGH20_CHAIN4_MASK 0x0000ff00 + +/* Description RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH_LOW20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH_LOW20_CHAIN4_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH_LOW20_CHAIN4_LSB 16 +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH_LOW20_CHAIN4_MASK 0x00ff0000 + +/* Description RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH20_CHAIN4 + + RSSI of RX PPDU on chain 4 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH20_CHAIN4_OFFSET 0x00000024 +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH20_CHAIN4_LSB 24 +#define RECEIVE_RSSI_INFO_9_RSSI_EXT80_HIGH20_CHAIN4_MASK 0xff000000 + +/* Description RECEIVE_RSSI_INFO_10_RSSI_PRI20_CHAIN5 + + RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_10_RSSI_PRI20_CHAIN5_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_10_RSSI_PRI20_CHAIN5_LSB 0 +#define RECEIVE_RSSI_INFO_10_RSSI_PRI20_CHAIN5_MASK 0x000000ff + +/* Description RECEIVE_RSSI_INFO_10_RSSI_EXT20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_10_RSSI_EXT20_CHAIN5_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_10_RSSI_EXT20_CHAIN5_LSB 8 +#define RECEIVE_RSSI_INFO_10_RSSI_EXT20_CHAIN5_MASK 0x0000ff00 + +/* Description RECEIVE_RSSI_INFO_10_RSSI_EXT40_LOW20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_LOW20_CHAIN5_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_LOW20_CHAIN5_LSB 16 +#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_LOW20_CHAIN5_MASK 0x00ff0000 + +/* Description RECEIVE_RSSI_INFO_10_RSSI_EXT40_HIGH20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_HIGH20_CHAIN5_OFFSET 0x00000028 +#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_HIGH20_CHAIN5_LSB 24 +#define RECEIVE_RSSI_INFO_10_RSSI_EXT40_HIGH20_CHAIN5_MASK 0xff000000 + +/* Description RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW20_CHAIN5_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW20_CHAIN5_LSB 0 +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW20_CHAIN5_MASK 0x000000ff + +/* Description RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW_HIGH20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW_HIGH20_CHAIN5_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW_HIGH20_CHAIN5_LSB 8 +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_LOW_HIGH20_CHAIN5_MASK 0x0000ff00 + +/* Description RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH_LOW20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH_LOW20_CHAIN5_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH_LOW20_CHAIN5_LSB 16 +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH_LOW20_CHAIN5_MASK 0x00ff0000 + +/* Description RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH20_CHAIN5 + + RSSI of RX PPDU on chain 5 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH20_CHAIN5_OFFSET 0x0000002c +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH20_CHAIN5_LSB 24 +#define RECEIVE_RSSI_INFO_11_RSSI_EXT80_HIGH20_CHAIN5_MASK 0xff000000 + +/* Description RECEIVE_RSSI_INFO_12_RSSI_PRI20_CHAIN6 + + RSSI of RX PPDU on chain 6 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_12_RSSI_PRI20_CHAIN6_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_12_RSSI_PRI20_CHAIN6_LSB 0 +#define RECEIVE_RSSI_INFO_12_RSSI_PRI20_CHAIN6_MASK 0x000000ff + +/* Description RECEIVE_RSSI_INFO_12_RSSI_EXT20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_12_RSSI_EXT20_CHAIN6_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_12_RSSI_EXT20_CHAIN6_LSB 8 +#define RECEIVE_RSSI_INFO_12_RSSI_EXT20_CHAIN6_MASK 0x0000ff00 + +/* Description RECEIVE_RSSI_INFO_12_RSSI_EXT40_LOW20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_LOW20_CHAIN6_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_LOW20_CHAIN6_LSB 16 +#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_LOW20_CHAIN6_MASK 0x00ff0000 + +/* Description RECEIVE_RSSI_INFO_12_RSSI_EXT40_HIGH20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_HIGH20_CHAIN6_OFFSET 0x00000030 +#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_HIGH20_CHAIN6_LSB 24 +#define RECEIVE_RSSI_INFO_12_RSSI_EXT40_HIGH20_CHAIN6_MASK 0xff000000 + +/* Description RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW20_CHAIN6_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW20_CHAIN6_LSB 0 +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW20_CHAIN6_MASK 0x000000ff + +/* Description RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW_HIGH20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW_HIGH20_CHAIN6_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW_HIGH20_CHAIN6_LSB 8 +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_LOW_HIGH20_CHAIN6_MASK 0x0000ff00 + +/* Description RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH_LOW20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH_LOW20_CHAIN6_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH_LOW20_CHAIN6_LSB 16 +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH_LOW20_CHAIN6_MASK 0x00ff0000 + +/* Description RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH20_CHAIN6 + + RSSI of RX PPDU on chain 6 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH20_CHAIN6_OFFSET 0x00000034 +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH20_CHAIN6_LSB 24 +#define RECEIVE_RSSI_INFO_13_RSSI_EXT80_HIGH20_CHAIN6_MASK 0xff000000 + +/* Description RECEIVE_RSSI_INFO_14_RSSI_PRI20_CHAIN7 + + RSSI of RX PPDU on chain 7 of primary 20 MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_14_RSSI_PRI20_CHAIN7_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_14_RSSI_PRI20_CHAIN7_LSB 0 +#define RECEIVE_RSSI_INFO_14_RSSI_PRI20_CHAIN7_MASK 0x000000ff + +/* Description RECEIVE_RSSI_INFO_14_RSSI_EXT20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_14_RSSI_EXT20_CHAIN7_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_14_RSSI_EXT20_CHAIN7_LSB 8 +#define RECEIVE_RSSI_INFO_14_RSSI_EXT20_CHAIN7_MASK 0x0000ff00 + +/* Description RECEIVE_RSSI_INFO_14_RSSI_EXT40_LOW20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 40, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_LOW20_CHAIN7_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_LOW20_CHAIN7_LSB 16 +#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_LOW20_CHAIN7_MASK 0x00ff0000 + +/* Description RECEIVE_RSSI_INFO_14_RSSI_EXT40_HIGH20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 40, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_HIGH20_CHAIN7_OFFSET 0x00000038 +#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_HIGH20_CHAIN7_LSB 24 +#define RECEIVE_RSSI_INFO_14_RSSI_EXT40_HIGH20_CHAIN7_MASK 0xff000000 + +/* Description RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 80, low 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW20_CHAIN7_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW20_CHAIN7_LSB 0 +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW20_CHAIN7_MASK 0x000000ff + +/* Description RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW_HIGH20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 80, low-high 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW_HIGH20_CHAIN7_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW_HIGH20_CHAIN7_LSB 8 +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_LOW_HIGH20_CHAIN7_MASK 0x0000ff00 + +/* Description RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH_LOW20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 80, high-low 20 + MHz bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH_LOW20_CHAIN7_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH_LOW20_CHAIN7_LSB 16 +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH_LOW20_CHAIN7_MASK 0x00ff0000 + +/* Description RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH20_CHAIN7 + + RSSI of RX PPDU on chain 7 of extension 80, high 20 MHz + bandwidth. + + Value of 0x80 indicates invalid. +*/ +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH20_CHAIN7_OFFSET 0x0000003c +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH20_CHAIN7_LSB 24 +#define RECEIVE_RSSI_INFO_15_RSSI_EXT80_HIGH20_CHAIN7_MASK 0xff000000 + + +#endif // _RECEIVE_RSSI_INFO_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/receive_user_info.h b/drivers/staging/fw-api/hw/qca6750/v1/receive_user_info.h new file mode 100644 index 000000000000..cd9af4ab94f9 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/receive_user_info.h @@ -0,0 +1,556 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RECEIVE_USER_INFO_H_ +#define _RECEIVE_USER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 phy_ppdu_id[15:0], user_rssi[23:16], pkt_type[27:24], stbc[28], reception_type[31:29] +// 1 rate_mcs[3:0], sgi[5:4], receive_bandwidth[7:6], mimo_ss_bitmap[15:8], ofdma_ru_allocation[23:16], ofdma_user_index[30:24], ofdma_content_channel[31] +// 2 ldpc[0], ru_width[7:1], reserved_2a[31:8] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RECEIVE_USER_INFO 3 + +struct receive_user_info { + uint32_t phy_ppdu_id : 16, //[15:0] + user_rssi : 8, //[23:16] + pkt_type : 4, //[27:24] + stbc : 1, //[28] + reception_type : 3; //[31:29] + uint32_t rate_mcs : 4, //[3:0] + sgi : 2, //[5:4] + receive_bandwidth : 2, //[7:6] + mimo_ss_bitmap : 8, //[15:8] + ofdma_ru_allocation : 8, //[23:16] + ofdma_user_index : 7, //[30:24] + ofdma_content_channel : 1; //[31] + uint32_t ldpc : 1, //[0] + ru_width : 7, //[7:1] + reserved_2a : 24; //[31:8] +}; + +/* + +phy_ppdu_id + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + + +user_rssi + + RSSI for this user + + Frequency domain RSSI measurement for this user. Based + on the channel estimate. + + + + + +pkt_type + + Packet type: + + + + 802.11a PPDU type + + 802.11b PPDU type + + 802.11n Mixed Mode PPDU type + + 802.11ac PPDU type + + 802.11ax PPDU type + + 802.11ba (WUR) PPDU type + +stbc + + When set, use STBC transmission rates + +reception_type + + Indicates what type of reception this is. + + Basic SU reception (not + part of OFDMA or MU-MIMO) + + This is related to + DL type of reception + + This is related + to DL type of reception + + This is + related to DL type of reception + + This is related + to UL type of reception + + This is + related to UL type of reception + + This is + related to UL type of reception + + + + + +rate_mcs + + For details, refer to MCS_TYPE description + + + +sgi + + Field only valid when pkt type is HT, VHT or HE. + + + + Legacy normal GI. Can also be + used for HE + + Legacy short GI. Can also be + used for HE + + HE related GI + + HE related GI + + + +receive_bandwidth + + Full receive Bandwidth + + + + + + + + + + + + + + + +mimo_ss_bitmap + + Bitmap, with each bit indicating if the related spatial + stream is used for this STA + + LSB related to SS 0 + + + + 0: spatial stream not used for this reception + + 1: spatial stream used for this reception + + + + + +ofdma_ru_allocation + + Field only valid in case of OFDMA type receptions (DL + and UL) + + + + Indicates the RU number associated with this user. + + + + In case of reception where the transmission was DL MU + OFDMA, this field provides the RU pattern. Note that fields + ofdma_user_index and ofdma_content_channel are needed to + determine which RU (within a 40 MHz channel) was actually + assigned to this user, but this does not give info on which + 40 MHz channel was assigned to this user. Please refer + DL_ofdma_ru_* in PHYRX_PKT_END_INFO for complete RU info for + this user. + + + + In case of reception where the transmission was UL MU + OFDMA, PHY is recommended to insert the RU start index in + this field. Note that PHY may insert the RU width in + Reserved_2a[6:0]. + + + +ofdma_user_index + + Field only valid in the of DL MU OFDMA reception + + + + The user number within the RU_allocation. + + + + This is needed for SW to determine the exact RU position + within the reception. + + + +ofdma_content_channel + + Field only valid in the of DL MU OFDMA/MIMO reception + + + + In case of DL MU reception, this field indicates the + content channel number where PHY found the RU information + for this user + + + + This is needed for SW to determine the exact RU position + within the reception. + + + + + + + + + + + +ldpc + + When set, use LDPC transmission rates were used. + + + +ru_width + + In case of UL OFDMA reception, PHY is recommended to + insert the RU width + + In Hastings80: was using Reserved_2a[6:0]. + + + +reserved_2a + + +*/ + + +/* Description RECEIVE_USER_INFO_0_PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + +*/ +#define RECEIVE_USER_INFO_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_0_PHY_PPDU_ID_LSB 0 +#define RECEIVE_USER_INFO_0_PHY_PPDU_ID_MASK 0x0000ffff + +/* Description RECEIVE_USER_INFO_0_USER_RSSI + + RSSI for this user + + Frequency domain RSSI measurement for this user. Based + on the channel estimate. + + + + +*/ +#define RECEIVE_USER_INFO_0_USER_RSSI_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_0_USER_RSSI_LSB 16 +#define RECEIVE_USER_INFO_0_USER_RSSI_MASK 0x00ff0000 + +/* Description RECEIVE_USER_INFO_0_PKT_TYPE + + Packet type: + + + + 802.11a PPDU type + + 802.11b PPDU type + + 802.11n Mixed Mode PPDU type + + 802.11ac PPDU type + + 802.11ax PPDU type + + 802.11ba (WUR) PPDU type +*/ +#define RECEIVE_USER_INFO_0_PKT_TYPE_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_0_PKT_TYPE_LSB 24 +#define RECEIVE_USER_INFO_0_PKT_TYPE_MASK 0x0f000000 + +/* Description RECEIVE_USER_INFO_0_STBC + + When set, use STBC transmission rates +*/ +#define RECEIVE_USER_INFO_0_STBC_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_0_STBC_LSB 28 +#define RECEIVE_USER_INFO_0_STBC_MASK 0x10000000 + +/* Description RECEIVE_USER_INFO_0_RECEPTION_TYPE + + Indicates what type of reception this is. + + Basic SU reception (not + part of OFDMA or MU-MIMO) + + This is related to + DL type of reception + + This is related + to DL type of reception + + This is + related to DL type of reception + + This is related + to UL type of reception + + This is + related to UL type of reception + + This is + related to UL type of reception + + + + +*/ +#define RECEIVE_USER_INFO_0_RECEPTION_TYPE_OFFSET 0x00000000 +#define RECEIVE_USER_INFO_0_RECEPTION_TYPE_LSB 29 +#define RECEIVE_USER_INFO_0_RECEPTION_TYPE_MASK 0xe0000000 + +/* Description RECEIVE_USER_INFO_1_RATE_MCS + + For details, refer to MCS_TYPE description + + +*/ +#define RECEIVE_USER_INFO_1_RATE_MCS_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_1_RATE_MCS_LSB 0 +#define RECEIVE_USER_INFO_1_RATE_MCS_MASK 0x0000000f + +/* Description RECEIVE_USER_INFO_1_SGI + + Field only valid when pkt type is HT, VHT or HE. + + + + Legacy normal GI. Can also be + used for HE + + Legacy short GI. Can also be + used for HE + + HE related GI + + HE related GI + + +*/ +#define RECEIVE_USER_INFO_1_SGI_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_1_SGI_LSB 4 +#define RECEIVE_USER_INFO_1_SGI_MASK 0x00000030 + +/* Description RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH + + Full receive Bandwidth + + + + + + + + + + + + + + +*/ +#define RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH_LSB 6 +#define RECEIVE_USER_INFO_1_RECEIVE_BANDWIDTH_MASK 0x000000c0 + +/* Description RECEIVE_USER_INFO_1_MIMO_SS_BITMAP + + Bitmap, with each bit indicating if the related spatial + stream is used for this STA + + LSB related to SS 0 + + + + 0: spatial stream not used for this reception + + 1: spatial stream used for this reception + + + + +*/ +#define RECEIVE_USER_INFO_1_MIMO_SS_BITMAP_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_1_MIMO_SS_BITMAP_LSB 8 +#define RECEIVE_USER_INFO_1_MIMO_SS_BITMAP_MASK 0x0000ff00 + +/* Description RECEIVE_USER_INFO_1_OFDMA_RU_ALLOCATION + + Field only valid in case of OFDMA type receptions (DL + and UL) + + + + Indicates the RU number associated with this user. + + + + In case of reception where the transmission was DL MU + OFDMA, this field provides the RU pattern. Note that fields + ofdma_user_index and ofdma_content_channel are needed to + determine which RU (within a 40 MHz channel) was actually + assigned to this user, but this does not give info on which + 40 MHz channel was assigned to this user. Please refer + DL_ofdma_ru_* in PHYRX_PKT_END_INFO for complete RU info for + this user. + + + + In case of reception where the transmission was UL MU + OFDMA, PHY is recommended to insert the RU start index in + this field. Note that PHY may insert the RU width in + Reserved_2a[6:0]. + + +*/ +#define RECEIVE_USER_INFO_1_OFDMA_RU_ALLOCATION_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_1_OFDMA_RU_ALLOCATION_LSB 16 +#define RECEIVE_USER_INFO_1_OFDMA_RU_ALLOCATION_MASK 0x00ff0000 + +/* Description RECEIVE_USER_INFO_1_OFDMA_USER_INDEX + + Field only valid in the of DL MU OFDMA reception + + + + The user number within the RU_allocation. + + + + This is needed for SW to determine the exact RU position + within the reception. + + +*/ +#define RECEIVE_USER_INFO_1_OFDMA_USER_INDEX_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_1_OFDMA_USER_INDEX_LSB 24 +#define RECEIVE_USER_INFO_1_OFDMA_USER_INDEX_MASK 0x7f000000 + +/* Description RECEIVE_USER_INFO_1_OFDMA_CONTENT_CHANNEL + + Field only valid in the of DL MU OFDMA/MIMO reception + + + + In case of DL MU reception, this field indicates the + content channel number where PHY found the RU information + for this user + + + + This is needed for SW to determine the exact RU position + within the reception. + + + + + + + + + + +*/ +#define RECEIVE_USER_INFO_1_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000004 +#define RECEIVE_USER_INFO_1_OFDMA_CONTENT_CHANNEL_LSB 31 +#define RECEIVE_USER_INFO_1_OFDMA_CONTENT_CHANNEL_MASK 0x80000000 + +/* Description RECEIVE_USER_INFO_2_LDPC + + When set, use LDPC transmission rates were used. + + +*/ +#define RECEIVE_USER_INFO_2_LDPC_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_2_LDPC_LSB 0 +#define RECEIVE_USER_INFO_2_LDPC_MASK 0x00000001 + +/* Description RECEIVE_USER_INFO_2_RU_WIDTH + + In case of UL OFDMA reception, PHY is recommended to + insert the RU width + + In Hastings80: was using Reserved_2a[6:0]. + + +*/ +#define RECEIVE_USER_INFO_2_RU_WIDTH_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_2_RU_WIDTH_LSB 1 +#define RECEIVE_USER_INFO_2_RU_WIDTH_MASK 0x000000fe + +/* Description RECEIVE_USER_INFO_2_RESERVED_2A + + +*/ +#define RECEIVE_USER_INFO_2_RESERVED_2A_OFFSET 0x00000008 +#define RECEIVE_USER_INFO_2_RESERVED_2A_LSB 8 +#define RECEIVE_USER_INFO_2_RESERVED_2A_MASK 0xffffff00 + + +#endif // _RECEIVE_USER_INFO_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/reo_descriptor_threshold_reached_status.h b/drivers/staging/fw-api/hw/qca6750/v1/reo_descriptor_threshold_reached_status.h new file mode 100644 index 000000000000..fb05c8134965 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/reo_descriptor_threshold_reached_status.h @@ -0,0 +1,664 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ +#define _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct uniform_reo_status_header status_header; +// 2 threshold_index[1:0], reserved_2[31:2] +// 3 link_descriptor_counter0[23:0], reserved_3[31:24] +// 4 link_descriptor_counter1[23:0], reserved_4[31:24] +// 5 link_descriptor_counter2[23:0], reserved_5[31:24] +// 6 link_descriptor_counter_sum[25:0], reserved_6[31:26] +// 7 reserved_7[31:0] +// 8 reserved_8[31:0] +// 9 reserved_9a[31:0] +// 10 reserved_10a[31:0] +// 11 reserved_11a[31:0] +// 12 reserved_12a[31:0] +// 13 reserved_13a[31:0] +// 14 reserved_14a[31:0] +// 15 reserved_15a[31:0] +// 16 reserved_16a[31:0] +// 17 reserved_17a[31:0] +// 18 reserved_18a[31:0] +// 19 reserved_19a[31:0] +// 20 reserved_20a[31:0] +// 21 reserved_21a[31:0] +// 22 reserved_22a[31:0] +// 23 reserved_23a[31:0] +// 24 reserved_24a[27:0], looping_count[31:28] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS 25 + +struct reo_descriptor_threshold_reached_status { + struct uniform_reo_status_header status_header; + uint32_t threshold_index : 2, //[1:0] + reserved_2 : 30; //[31:2] + uint32_t link_descriptor_counter0 : 24, //[23:0] + reserved_3 : 8; //[31:24] + uint32_t link_descriptor_counter1 : 24, //[23:0] + reserved_4 : 8; //[31:24] + uint32_t link_descriptor_counter2 : 24, //[23:0] + reserved_5 : 8; //[31:24] + uint32_t link_descriptor_counter_sum : 26, //[25:0] + reserved_6 : 6; //[31:26] + uint32_t reserved_7 : 32; //[31:0] + uint32_t reserved_8 : 32; //[31:0] + uint32_t reserved_9a : 32; //[31:0] + uint32_t reserved_10a : 32; //[31:0] + uint32_t reserved_11a : 32; //[31:0] + uint32_t reserved_12a : 32; //[31:0] + uint32_t reserved_13a : 32; //[31:0] + uint32_t reserved_14a : 32; //[31:0] + uint32_t reserved_15a : 32; //[31:0] + uint32_t reserved_16a : 32; //[31:0] + uint32_t reserved_17a : 32; //[31:0] + uint32_t reserved_18a : 32; //[31:0] + uint32_t reserved_19a : 32; //[31:0] + uint32_t reserved_20a : 32; //[31:0] + uint32_t reserved_21a : 32; //[31:0] + uint32_t reserved_22a : 32; //[31:0] + uint32_t reserved_23a : 32; //[31:0] + uint32_t reserved_24a : 28, //[27:0] + looping_count : 4; //[31:28] +}; + +/* + +struct uniform_reo_status_header status_header + + Consumer: SW + + Producer: REO + + + + Details that can link this status with the original + command. It also contains info on how long REO took to + execute this command. + +threshold_index + + The index of the threshold register whose value got + reached + + + + + + + + + + + + + + + +reserved_2 + + + +link_descriptor_counter0 + + Value of this counter at generation of this message + + + +reserved_3 + + + +link_descriptor_counter1 + + Value of this counter at generation of this message + + + +reserved_4 + + + +link_descriptor_counter2 + + Value of this counter at generation of this message + + + +reserved_5 + + + +link_descriptor_counter_sum + + Value of this counter at generation of this message + + + +reserved_6 + + + +reserved_7 + + + +reserved_8 + + + +reserved_9a + + + +reserved_10a + + + +reserved_11a + + + +reserved_12a + + + +reserved_13a + + + +reserved_14a + + + +reserved_15a + + + +reserved_16a + + + +reserved_17a + + + +reserved_18a + + + +reserved_19a + + + +reserved_20a + + + +reserved_21a + + + +reserved_22a + + + +reserved_23a + + + +reserved_24a + + + +looping_count + + A count value that indicates the number of times the + producer of entries into this Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ + + + /* EXTERNAL REFERENCE : struct uniform_reo_status_header status_header */ + + +/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER + + Consumer: SW , DEBUG + + Producer: REO + + + + The value in this field is equal to value of the + 'REO_CMD_Number' field the REO command + + + + This field helps to correlate the statuses with the REO + commands. + + + + +*/ +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME + + Consumer: DEBUG + + Producer: REO + + + + The amount of time REO took to excecute the command. + Note that this time does not include the duration of the + command waiting in the command ring, before the execution + started. + + + + In us. + + + + +*/ +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS + + Consumer: DEBUG + + Producer: REO + + + + Execution status of the command. + + + + Command has + successfully be executed + + Command could not be + executed as the queue or cache was blocked + + Command has encountered + problems when executing, like the queue descriptor not being + valid. None of the status fields in the entire STATUS TLV + are valid. + + Command is NOT executed + because one or more descriptors were blocked. This is SW + programming mistake. + + None of the status fields in the entire STATUS TLV are + valid. + + + + +*/ +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_RESERVED_0A + + +*/ +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_STATUS_HEADER_TIMESTAMP + + Timestamp at the moment that this status report is + written. + + + + +*/ +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX + + The index of the threshold register whose value got + reached + + + + + + + + + + + + + + +*/ +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_OFFSET 0x00000008 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_THRESHOLD_INDEX_MASK 0x00000003 + +/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2 + + +*/ +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_OFFSET 0x00000008 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_LSB 2 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_2_RESERVED_2_MASK 0xfffffffc + +/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0 + + Value of this counter at generation of this message + + +*/ +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_OFFSET 0x0000000c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_LINK_DESCRIPTOR_COUNTER0_MASK 0x00ffffff + +/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3 + + +*/ +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_OFFSET 0x0000000c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_LSB 24 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_3_RESERVED_3_MASK 0xff000000 + +/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1 + + Value of this counter at generation of this message + + +*/ +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_OFFSET 0x00000010 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_LINK_DESCRIPTOR_COUNTER1_MASK 0x00ffffff + +/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4 + + +*/ +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_OFFSET 0x00000010 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_LSB 24 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_4_RESERVED_4_MASK 0xff000000 + +/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2 + + Value of this counter at generation of this message + + +*/ +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_OFFSET 0x00000014 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_LINK_DESCRIPTOR_COUNTER2_MASK 0x00ffffff + +/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5 + + +*/ +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_OFFSET 0x00000014 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_LSB 24 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_5_RESERVED_5_MASK 0xff000000 + +/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM + + Value of this counter at generation of this message + + +*/ +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_OFFSET 0x00000018 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_LINK_DESCRIPTOR_COUNTER_SUM_MASK 0x03ffffff + +/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6 + + +*/ +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_OFFSET 0x00000018 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_LSB 26 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_6_RESERVED_6_MASK 0xfc000000 + +/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7 + + +*/ +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_OFFSET 0x0000001c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_7_RESERVED_7_MASK 0xffffffff + +/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8 + + +*/ +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_OFFSET 0x00000020 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_8_RESERVED_8_MASK 0xffffffff + +/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A + + +*/ +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_OFFSET 0x00000024 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_9_RESERVED_9A_MASK 0xffffffff + +/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A + + +*/ +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_OFFSET 0x00000028 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_10_RESERVED_10A_MASK 0xffffffff + +/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A + + +*/ +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_OFFSET 0x0000002c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_11_RESERVED_11A_MASK 0xffffffff + +/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A + + +*/ +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_OFFSET 0x00000030 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_12_RESERVED_12A_MASK 0xffffffff + +/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A + + +*/ +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_OFFSET 0x00000034 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_13_RESERVED_13A_MASK 0xffffffff + +/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A + + +*/ +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_OFFSET 0x00000038 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_14_RESERVED_14A_MASK 0xffffffff + +/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A + + +*/ +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_OFFSET 0x0000003c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_15_RESERVED_15A_MASK 0xffffffff + +/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A + + +*/ +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_OFFSET 0x00000040 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_16_RESERVED_16A_MASK 0xffffffff + +/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A + + +*/ +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_OFFSET 0x00000044 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_17_RESERVED_17A_MASK 0xffffffff + +/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A + + +*/ +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_OFFSET 0x00000048 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_18_RESERVED_18A_MASK 0xffffffff + +/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A + + +*/ +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_OFFSET 0x0000004c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_19_RESERVED_19A_MASK 0xffffffff + +/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A + + +*/ +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_OFFSET 0x00000050 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_20_RESERVED_20A_MASK 0xffffffff + +/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A + + +*/ +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_OFFSET 0x00000054 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_21_RESERVED_21A_MASK 0xffffffff + +/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A + + +*/ +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_OFFSET 0x00000058 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_22_RESERVED_22A_MASK 0xffffffff + +/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A + + +*/ +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_OFFSET 0x0000005c +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_23_RESERVED_23A_MASK 0xffffffff + +/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A + + +*/ +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_OFFSET 0x00000060 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_LSB 0 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_RESERVED_24A_MASK 0x0fffffff + +/* Description REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT + + A count value that indicates the number of times the + producer of entries into this Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_LSB 28 +#define REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 + + +#endif // _REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/reo_destination_ring.h b/drivers/staging/fw-api/hw/qca6750/v1/reo_destination_ring.h new file mode 100644 index 000000000000..8625bbf723dd --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/reo_destination_ring.h @@ -0,0 +1,1555 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _REO_DESTINATION_RING_H_ +#define _REO_DESTINATION_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#include "rx_mpdu_desc_info.h" +#include "rx_msdu_desc_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct buffer_addr_info buf_or_link_desc_addr_info; +// 2-3 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; +// 4-5 struct rx_msdu_desc_info rx_msdu_desc_info_details; +// 6 rx_reo_queue_desc_addr_31_0[31:0] +// 7 rx_reo_queue_desc_addr_39_32[7:0], reo_dest_buffer_type[8], reo_push_reason[10:9], reo_error_code[15:11], receive_queue_number[31:16] +// 8 soft_reorder_info_valid[0], reorder_opcode[4:1], reorder_slot_index[12:5], mpdu_fragment_number[16:13], captured_msdu_data_size[20:17], sw_exception[21], reserved_8a[31:22] +// 9 reo_destination_struct_signature[31:0] +// 10 reserved_10a[31:0] +// 11 reserved_11a[31:0] +// 12 reserved_12a[31:0] +// 13 reserved_13a[31:0] +// 14 reserved_14a[31:0] +// 15 reserved_15[19:0], ring_id[27:20], looping_count[31:28] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_REO_DESTINATION_RING 16 + +struct reo_destination_ring { + struct buffer_addr_info buf_or_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0] + uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0] + reo_dest_buffer_type : 1, //[8] + reo_push_reason : 2, //[10:9] + reo_error_code : 5, //[15:11] + receive_queue_number : 16; //[31:16] + uint32_t soft_reorder_info_valid : 1, //[0] + reorder_opcode : 4, //[4:1] + reorder_slot_index : 8, //[12:5] + mpdu_fragment_number : 4, //[16:13] + captured_msdu_data_size : 4, //[20:17] + sw_exception : 1, //[21] + reserved_8a : 10; //[31:22] + uint32_t reo_destination_struct_signature: 32; //[31:0] + uint32_t reserved_10a : 32; //[31:0] + uint32_t reserved_11a : 32; //[31:0] + uint32_t reserved_12a : 32; //[31:0] + uint32_t reserved_13a : 32; //[31:0] + uint32_t reserved_14a : 32; //[31:0] + uint32_t reserved_15 : 20, //[19:0] + ring_id : 8, //[27:20] + looping_count : 4; //[31:28] +}; + +/* + +struct buffer_addr_info buf_or_link_desc_addr_info + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + Details of the physical address of the a buffer or MSDU + link descriptor + +struct rx_mpdu_desc_info rx_mpdu_desc_info_details + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + General information related to the MPDU that is passed + on from REO entrance ring to the REO destination ring + +struct rx_msdu_desc_info rx_msdu_desc_info_details + + General information related to the MSDU that is passed + on from RXDMA all the way to to the REO destination ring. + +rx_reo_queue_desc_addr_31_0 + + Consumer: REO + + Producer: RXDMA + + + + Address (lower 32 bits) of the REO queue descriptor. + + + +rx_reo_queue_desc_addr_39_32 + + Consumer: REO + + Producer: RXDMA + + + + Address (upper 8 bits) of the REO queue descriptor. + + + +reo_dest_buffer_type + + Indicates the type of address provided in the + 'Buf_or_link_desc_addr_info' + + + + The address of an MSDU buffer + + The address of the MSDU + link descriptor. + + + + + +reo_push_reason + + Indicates why REO pushed the frame to this exit ring + + + + Reo detected an error an + pushed this frame to this queue + + Reo pushed the frame to + this queue per received routing instructions. No error + within REO was detected + + + + + + + +reo_error_code + + Field only valid when 'Reo_push_reason' set to + 'reo_error_detected'. + + + + Reo queue descriptor + provided in the REO_ENTRANCE ring is set to 0 + + Reo queue descriptor + valid bit is NOT set + + AMPDU frame received without BA + session having been setup. + + Non-BA session, SN equal to + SSN, Retry bit set: duplicate frame + + BA session, duplicate frame + + A normal (management/data + frame) received with 2K jump in SN + + A bar received with 2K jump + in SSN + + A normal (management/data + frame) received with SN falling within the OOR window + + A bar received with SSN falling + within the OOR window + + A bar received without + a BA session + + A bar received with + SSN equal to SN + + PN Check Failed packet. + + Frame is forwarded + as a result of the 'Seq_2k_error_detected_flag' been set in + the REO Queue descriptor + + Frame is forwarded + as a result of the 'pn_error_detected_flag' been set in the + REO Queue descriptor + + Frame is + forwarded as a result of the queue descriptor(address) being + blocked as SW/FW seems to be currently in the process of + making updates to this descriptor... + + + + + +receive_queue_number + + This field in NOT valid (should be set to 0), when + SW_exception is set. + + This field indicates the REO MPDU reorder queue ID from + which this frame originated. This field is populated from a + field with the same name in the RX_REO_QUEUE descriptor. + + + +soft_reorder_info_valid + + This field in NOT valid (should be set to 0), when + SW_exception is set. + + When set, REO has been instructed to not perform the + actual re-ordering of frames for this queue, but just to + insert the reorder opcodes + + + +reorder_opcode + + Field is valid when 'Soft_reorder_info_valid' is set. + This field is always valid for debug purpose as well. + + Details are in the MLD. + + + + + + + + + + + + + + + + + + + + + + the error reason code is in + reo_error_code field. + + + + + + + + + + + + + + + + + +reorder_slot_index + + Field only valid when 'Soft_reorder_info_valid' is set. + + + + TODO: add description + + + + + +mpdu_fragment_number + + Field only valid when Rx_mpdu_desc_info_details. + Fragment_flag is set. + + + + The fragment number from the 802.11 header. + + + + Note that the sequence number is embedded in the field: + Rx_mpdu_desc_info_details. Mpdu_sequence_number + + + + + +captured_msdu_data_size + + The number of following REO_DESTINATION STRUCTs that + have been replaced with msdu_data extracted from the + msdu_buffer and copied into the ring for easy FW/SW access. + + Note that it is possible that these STRUCTs wrap around + the end of the ring. + + Feature supported only in HastingsPrime + + + +sw_exception + + This field has the same setting as the SW_exception + field in the corresponding REO_entrance_ring descriptor. + + When set, the REO entrance descriptor is generated by + FW, and the MPDU was processed in the following way: + + - NO re-order function is needed. + + - MPDU delinking is determined by the setting of + Entrance ring field: SW_excection_mpdu_delink + + - Destination ring selection is based on the setting of + + Feature supported only in HastingsPrime + + + +reserved_8a + + + +reo_destination_struct_signature + + Set to value 0x8888_88888 when msdu capture mode is + enabled for this ring (supported only in HastingsPrime) + + + +reserved_10a + + + +reserved_11a + + + +reserved_12a + + + +reserved_13a + + + +reserved_14a + + + +reserved_15 + + + +ring_id + + The buffer pointer ring ID. + + 0 refers to the IDLE ring + + 1 - N refers to other rings + + + + Helps with debugging when dumping ring contents. + + + +looping_count + + A count value that indicates the number of times the + producer of entries into this Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ + + + /* EXTERNAL REFERENCE : struct buffer_addr_info buf_or_link_desc_addr_info */ + + +/* Description REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define REO_DESTINATION_RING_0_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + +*/ +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define REO_DESTINATION_RING_1_BUF_OR_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + + /* EXTERNAL REFERENCE : struct rx_mpdu_desc_info rx_mpdu_desc_info_details */ + + +/* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + The number of MSDUs within the MPDU + + +*/ +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + +/* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + The field can have two different meanings based on the + setting of field 'BAR_frame': + + + + 'BAR_frame' is NOT set: + + The MPDU sequence number of the received frame. + + + + 'BAR_frame' is set. + + The MPDU Start sequence number from the BAR frame + + +*/ +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00 + +/* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + When set, this MPDU is a fragment and REO should forward + this fragment MPDU to the REO destination ring without any + reorder checks, pn checks or bitmap update. This implies + that REO is forwarding the pointer to the MSDU link + descriptor. The destination ring is coming from a + programmable register setting in REO + + + + +*/ +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000 + +/* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + The retry bit setting from the MPDU header of the + received frame + + +*/ +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000 + +/* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + When set, the MPDU was received as part of an A-MPDU. + + +*/ +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000 + +/* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + When set, the received frame is a BAR frame. After + processing, this frame shall be pushed to SW or deleted. + + +*/ +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000 + +/* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + Copied here by RXDMA from RX_MPDU_END + + When not set, REO will Not perform a PN sequence number + check +*/ +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000 + +/* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID + + When set, OLE found a valid SA entry for all MSDUs in + this MPDU + + +*/ +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000 + +/* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT + + When set, at least 1 MSDU within the MPDU has an + unsuccessful MAC source address search due to the expiration + of the search timer. + + +*/ +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000 + +/* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID + + When set, OLE found a valid DA entry for all MSDUs in + this MPDU + + +*/ +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000 + +/* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC + + Field Only valid if da_is_valid is set + + + + When set, at least one of the DA addresses is a + Multicast or Broadcast address. + + +*/ +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000 + +/* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT + + When set, at least 1 MSDU within the MPDU has an + unsuccessful MAC destination address search due to the + expiration of the search timer. + + +*/ +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000 + +/* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU + + Field only valid when first_msdu_in_mpdu_flag is set. + + + + When set, the contents in the MSDU buffer contains a + 'RAW' MPDU. This 'RAW' MPDU might be spread out over + multiple MSDU buffers. + + +*/ +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 + +/* Description REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG + + The More Fragment bit setting from the MPDU header of + the received frame + + + + +*/ +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31 +#define REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000 + +/* Description REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + + +*/ +#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define REO_DESTINATION_RING_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + + /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ + + +/* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + This is not the first MSDU in + the MPDU. + + This MSDU is the first one in the + MPDU. + + + + +*/ +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +/* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG + + Consumer: WBM/REO/SW/FW + + Producer: RXDMA + + + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + There are more MSDUs linked to + this MSDU that belongs to this MPDU + + this MSDU is the last one in the + MPDU. This setting is only allowed in combination with + 'Msdu_continuation' set to 0. This implies that when an msdu + is spread out over multiple buffers and thus + msdu_continuation is set, only for the very last buffer of + the msdu, can the 'last_msdu_in_mpdu_flag' be set. + + + + When both first_msdu_in_mpdu_flag and + last_msdu_in_mpdu_flag are set, the MPDU that this MSDU + belongs to only contains a single MSDU. + + + + + + +*/ +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +/* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION + + When set, this MSDU buffer was not able to hold the + entire MSDU. The next buffer will therefor contain + additional information related to this MSDU. + + + + +*/ +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +/* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH + + Parsed from RX_MSDU_START TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the First + buffer used by MSDU. + + + + Full MSDU length in bytes after decapsulation. + + + + This field is still valid for MPDU frames without + A-MSDU. It still represents MSDU length after decapsulation + + + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + + +*/ +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +/* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW2 ring + + Reo will push the frame + into the REO2SW3 ring + + Reo will push the frame + into the REO2SW4 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + Reo will push the frame + into the REO2SW5 ring (REO remaps this in chips without + REO2SW5 ring, e.g. Pine) + + Reo will push the frame + into the REO2SW6 ring (REO remaps this in chips without + REO2SW6 ring, e.g. Pine) + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + +*/ +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +/* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + When set, REO shall drop this MSDU and not forward it to + any other ring... + + +*/ +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 + +/* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates that OLE found a valid SA entry for this MSDU + + +*/ +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 + +/* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates an unsuccessful MAC source address search due + to the expiring of the search timer for this MSDU + + +*/ +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 + +/* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates that OLE found a valid DA entry for this MSDU + + +*/ +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 + +/* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC + + Field Only valid if da_is_valid is set + + + + Indicates the DA address was a Multicast of Broadcast + address for this MSDU + + +*/ +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 + +/* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates an unsuccessful MAC destination address search + due to the expiring of the search timer for this MSDU + + +*/ +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 + +/* Description REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A + + +*/ +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000010 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28 +#define REO_DESTINATION_RING_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000 + +/* Description REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A + + +*/ +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000014 +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0 +#define REO_DESTINATION_RING_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff + +/* Description REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0 + + Consumer: REO + + Producer: RXDMA + + + + Address (lower 32 bits) of the REO queue descriptor. + + +*/ +#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000018 +#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_DESTINATION_RING_6_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +/* Description REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32 + + Consumer: REO + + Producer: RXDMA + + + + Address (upper 8 bits) of the REO queue descriptor. + + +*/ +#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x0000001c +#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_DESTINATION_RING_7_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +/* Description REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE + + Indicates the type of address provided in the + 'Buf_or_link_desc_addr_info' + + + + The address of an MSDU buffer + + The address of the MSDU + link descriptor. + + + + +*/ +#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_LSB 8 +#define REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_MASK 0x00000100 + +/* Description REO_DESTINATION_RING_7_REO_PUSH_REASON + + Indicates why REO pushed the frame to this exit ring + + + + Reo detected an error an + pushed this frame to this queue + + Reo pushed the frame to + this queue per received routing instructions. No error + within REO was detected + + + + + + +*/ +#define REO_DESTINATION_RING_7_REO_PUSH_REASON_OFFSET 0x0000001c +#define REO_DESTINATION_RING_7_REO_PUSH_REASON_LSB 9 +#define REO_DESTINATION_RING_7_REO_PUSH_REASON_MASK 0x00000600 + +/* Description REO_DESTINATION_RING_7_REO_ERROR_CODE + + Field only valid when 'Reo_push_reason' set to + 'reo_error_detected'. + + + + Reo queue descriptor + provided in the REO_ENTRANCE ring is set to 0 + + Reo queue descriptor + valid bit is NOT set + + AMPDU frame received without BA + session having been setup. + + Non-BA session, SN equal to + SSN, Retry bit set: duplicate frame + + BA session, duplicate frame + + A normal (management/data + frame) received with 2K jump in SN + + A bar received with 2K jump + in SSN + + A normal (management/data + frame) received with SN falling within the OOR window + + A bar received with SSN falling + within the OOR window + + A bar received without + a BA session + + A bar received with + SSN equal to SN + + PN Check Failed packet. + + Frame is forwarded + as a result of the 'Seq_2k_error_detected_flag' been set in + the REO Queue descriptor + + Frame is forwarded + as a result of the 'pn_error_detected_flag' been set in the + REO Queue descriptor + + Frame is + forwarded as a result of the queue descriptor(address) being + blocked as SW/FW seems to be currently in the process of + making updates to this descriptor... + + + + +*/ +#define REO_DESTINATION_RING_7_REO_ERROR_CODE_OFFSET 0x0000001c +#define REO_DESTINATION_RING_7_REO_ERROR_CODE_LSB 11 +#define REO_DESTINATION_RING_7_REO_ERROR_CODE_MASK 0x0000f800 + +/* Description REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER + + This field in NOT valid (should be set to 0), when + SW_exception is set. + + This field indicates the REO MPDU reorder queue ID from + which this frame originated. This field is populated from a + field with the same name in the RX_REO_QUEUE descriptor. + + +*/ +#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000001c +#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_LSB 16 +#define REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_MASK 0xffff0000 + +/* Description REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID + + This field in NOT valid (should be set to 0), when + SW_exception is set. + + When set, REO has been instructed to not perform the + actual re-ordering of frames for this queue, but just to + insert the reorder opcodes + + +*/ +#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_LSB 0 +#define REO_DESTINATION_RING_8_SOFT_REORDER_INFO_VALID_MASK 0x00000001 + +/* Description REO_DESTINATION_RING_8_REORDER_OPCODE + + Field is valid when 'Soft_reorder_info_valid' is set. + This field is always valid for debug purpose as well. + + Details are in the MLD. + + + + + + + + + + + + + + + + + + + + + + the error reason code is in + reo_error_code field. + + + + + + + + + + + + + + + + +*/ +#define REO_DESTINATION_RING_8_REORDER_OPCODE_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_REORDER_OPCODE_LSB 1 +#define REO_DESTINATION_RING_8_REORDER_OPCODE_MASK 0x0000001e + +/* Description REO_DESTINATION_RING_8_REORDER_SLOT_INDEX + + Field only valid when 'Soft_reorder_info_valid' is set. + + + + TODO: add description + + + + +*/ +#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_LSB 5 +#define REO_DESTINATION_RING_8_REORDER_SLOT_INDEX_MASK 0x00001fe0 + +/* Description REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER + + Field only valid when Rx_mpdu_desc_info_details. + Fragment_flag is set. + + + + The fragment number from the 802.11 header. + + + + Note that the sequence number is embedded in the field: + Rx_mpdu_desc_info_details. Mpdu_sequence_number + + + + +*/ +#define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_LSB 13 +#define REO_DESTINATION_RING_8_MPDU_FRAGMENT_NUMBER_MASK 0x0001e000 + +/* Description REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE + + The number of following REO_DESTINATION STRUCTs that + have been replaced with msdu_data extracted from the + msdu_buffer and copied into the ring for easy FW/SW access. + + Note that it is possible that these STRUCTs wrap around + the end of the ring. + + Feature supported only in HastingsPrime + + +*/ +#define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_LSB 17 +#define REO_DESTINATION_RING_8_CAPTURED_MSDU_DATA_SIZE_MASK 0x001e0000 + +/* Description REO_DESTINATION_RING_8_SW_EXCEPTION + + This field has the same setting as the SW_exception + field in the corresponding REO_entrance_ring descriptor. + + When set, the REO entrance descriptor is generated by + FW, and the MPDU was processed in the following way: + + - NO re-order function is needed. + + - MPDU delinking is determined by the setting of + Entrance ring field: SW_excection_mpdu_delink + + - Destination ring selection is based on the setting of + + Feature supported only in HastingsPrime + + +*/ +#define REO_DESTINATION_RING_8_SW_EXCEPTION_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_SW_EXCEPTION_LSB 21 +#define REO_DESTINATION_RING_8_SW_EXCEPTION_MASK 0x00200000 + +/* Description REO_DESTINATION_RING_8_RESERVED_8A + + +*/ +#define REO_DESTINATION_RING_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_DESTINATION_RING_8_RESERVED_8A_LSB 22 +#define REO_DESTINATION_RING_8_RESERVED_8A_MASK 0xffc00000 + +/* Description REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE + + Set to value 0x8888_88888 when msdu capture mode is + enabled for this ring (supported only in HastingsPrime) + + +*/ +#define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_OFFSET 0x00000024 +#define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_LSB 0 +#define REO_DESTINATION_RING_9_REO_DESTINATION_STRUCT_SIGNATURE_MASK 0xffffffff + +/* Description REO_DESTINATION_RING_10_RESERVED_10A + + +*/ +#define REO_DESTINATION_RING_10_RESERVED_10A_OFFSET 0x00000028 +#define REO_DESTINATION_RING_10_RESERVED_10A_LSB 0 +#define REO_DESTINATION_RING_10_RESERVED_10A_MASK 0xffffffff + +/* Description REO_DESTINATION_RING_11_RESERVED_11A + + +*/ +#define REO_DESTINATION_RING_11_RESERVED_11A_OFFSET 0x0000002c +#define REO_DESTINATION_RING_11_RESERVED_11A_LSB 0 +#define REO_DESTINATION_RING_11_RESERVED_11A_MASK 0xffffffff + +/* Description REO_DESTINATION_RING_12_RESERVED_12A + + +*/ +#define REO_DESTINATION_RING_12_RESERVED_12A_OFFSET 0x00000030 +#define REO_DESTINATION_RING_12_RESERVED_12A_LSB 0 +#define REO_DESTINATION_RING_12_RESERVED_12A_MASK 0xffffffff + +/* Description REO_DESTINATION_RING_13_RESERVED_13A + + +*/ +#define REO_DESTINATION_RING_13_RESERVED_13A_OFFSET 0x00000034 +#define REO_DESTINATION_RING_13_RESERVED_13A_LSB 0 +#define REO_DESTINATION_RING_13_RESERVED_13A_MASK 0xffffffff + +/* Description REO_DESTINATION_RING_14_RESERVED_14A + + +*/ +#define REO_DESTINATION_RING_14_RESERVED_14A_OFFSET 0x00000038 +#define REO_DESTINATION_RING_14_RESERVED_14A_LSB 0 +#define REO_DESTINATION_RING_14_RESERVED_14A_MASK 0xffffffff + +/* Description REO_DESTINATION_RING_15_RESERVED_15 + + +*/ +#define REO_DESTINATION_RING_15_RESERVED_15_OFFSET 0x0000003c +#define REO_DESTINATION_RING_15_RESERVED_15_LSB 0 +#define REO_DESTINATION_RING_15_RESERVED_15_MASK 0x000fffff + +/* Description REO_DESTINATION_RING_15_RING_ID + + The buffer pointer ring ID. + + 0 refers to the IDLE ring + + 1 - N refers to other rings + + + + Helps with debugging when dumping ring contents. + + +*/ +#define REO_DESTINATION_RING_15_RING_ID_OFFSET 0x0000003c +#define REO_DESTINATION_RING_15_RING_ID_LSB 20 +#define REO_DESTINATION_RING_15_RING_ID_MASK 0x0ff00000 + +/* Description REO_DESTINATION_RING_15_LOOPING_COUNT + + A count value that indicates the number of times the + producer of entries into this Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ +#define REO_DESTINATION_RING_15_LOOPING_COUNT_OFFSET 0x0000003c +#define REO_DESTINATION_RING_15_LOOPING_COUNT_LSB 28 +#define REO_DESTINATION_RING_15_LOOPING_COUNT_MASK 0xf0000000 + + +#endif // _REO_DESTINATION_RING_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/reo_entrance_ring.h b/drivers/staging/fw-api/hw/qca6750/v1/reo_entrance_ring.h new file mode 100644 index 000000000000..b2e01efc0f7e --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/reo_entrance_ring.h @@ -0,0 +1,1532 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _REO_ENTRANCE_RING_H_ +#define _REO_ENTRANCE_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_mpdu_details.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-3 struct rx_mpdu_details reo_level_mpdu_frame_info; +// 4 rx_reo_queue_desc_addr_31_0[31:0] +// 5 rx_reo_queue_desc_addr_39_32[7:0], rounded_mpdu_byte_count[21:8], reo_destination_indication[26:22], frameless_bar[27], reserved_5a[31:28] +// 6 rxdma_push_reason[1:0], rxdma_error_code[6:2], mpdu_fragment_number[10:7], sw_exception[11], sw_exception_mpdu_delink[12], sw_exception_destination_ring_valid[13], sw_exception_destination_ring[18:14], reserved_6a[31:19] +// 7 phy_ppdu_id[15:0], reserved_7a[19:16], ring_id[27:20], looping_count[31:28] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_REO_ENTRANCE_RING 8 + +struct reo_entrance_ring { + struct rx_mpdu_details reo_level_mpdu_frame_info; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0] + uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0] + rounded_mpdu_byte_count : 14, //[21:8] + reo_destination_indication : 5, //[26:22] + frameless_bar : 1, //[27] + reserved_5a : 4; //[31:28] + uint32_t rxdma_push_reason : 2, //[1:0] + rxdma_error_code : 5, //[6:2] + mpdu_fragment_number : 4, //[10:7] + sw_exception : 1, //[11] + sw_exception_mpdu_delink : 1, //[12] + sw_exception_destination_ring_valid: 1, //[13] + sw_exception_destination_ring : 5, //[18:14] + reserved_6a : 13; //[31:19] + uint32_t phy_ppdu_id : 16, //[15:0] + reserved_7a : 4, //[19:16] + ring_id : 8, //[27:20] + looping_count : 4; //[31:28] +}; + +/* + +struct rx_mpdu_details reo_level_mpdu_frame_info + + Consumer: REO + + Producer: RXDMA + + + + Details related to the MPDU being pushed into the REO + +rx_reo_queue_desc_addr_31_0 + + Consumer: REO + + Producer: RXDMA + + + + Address (lower 32 bits) of the REO queue descriptor. + + + +rx_reo_queue_desc_addr_39_32 + + Consumer: REO + + Producer: RXDMA + + + + Address (upper 8 bits) of the REO queue descriptor. + + + +rounded_mpdu_byte_count + + An approximation of the number of bytes received in this + MPDU. + + Used to keeps stats on the amount of data flowing + through a queue. + + + +reo_destination_indication + + RXDMA copy the MPDU's first MSDU's destination + indication field here. This is used for REO to be able to + re-route the packet to a different SW destination ring if + the packet is detected as error in REO. + + + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW2 ring + + Reo will push the frame + into the REO2SW3 ring + + Reo will push the frame + into the REO2SW4 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + Reo will push the frame + into the REO2SW5 ring (REO remaps this in chips without + REO2SW5 ring, e.g. Pine) + + Reo will push the frame + into the REO2SW6 ring (REO remaps this in chips without + REO2SW6 ring, e.g. Pine) + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + + +frameless_bar + + When set, this REO entrance ring struct contains BAR + info from a multi TID BAR frame. The original multi TID BAR + frame itself contained all the REO info for the first TID, + but all the subsequent TID info and their linkage to the REO + descriptors is passed down as 'frameless' BAR info. + + + + The only fields valid in this descriptor when this bit + is set are: + + Rx_reo_queue_desc_addr_31_0 + + RX_reo_queue_desc_addr_39_32 + + + + And within the + + Reo_level_mpdu_frame_info: + + Within Rx_mpdu_desc_info_details: + + Mpdu_Sequence_number + + BAR_frame + + Peer_meta_data + + All other fields shall be set to 0 + + + + + +reserved_5a + + + +rxdma_push_reason + + Indicates why rxdma pushed the frame to this ring + + + + This field is ignored by REO. + + + + RXDMA detected an error an + pushed this frame to this queue + + RXDMA pushed the + frame to this queue per received routing instructions. No + error within RXDMA was detected + + RXDMA received an RX_FLUSH. As a + result the MSDU link descriptor might not have the + last_msdu_in_mpdu_flag set, but instead WBM might just see a + NULL pointer in the MSDU link descriptor. This is to be + considered a normal condition for this scenario. + + + + + +rxdma_error_code + + Field only valid when 'rxdma_push_reason' set to + 'rxdma_error_detected'. + + + + This field is ignored by REO. + + + + MPDU frame is not complete + due to a FIFO overflow error in RXPCU. + + MPDU frame is not complete + due to receiving incomplete MPDU from the PHY + + + CRYPTO reported a decryption + error or CRYPTO received an encrypted frame, but did not get + a valid corresponding key id in the peer entry. + + CRYPTO reported a TKIP MIC + error + + CRYPTO reported an + unencrypted frame error when encrypted was expected + + RX OLE reported an MSDU + length error + + RX OLE reported that max + number of MSDUs allowed in an MPDU got exceeded + + RX OLE reported a parsing + error + + RX OLE reported an A-MSDU + parsing error + + RX OLE reported a timeout + during SA search + + RX OLE reported a timeout + during DA search + + RX OLE reported a + timeout during flow search + + RXDMA received a flush + request + + Rx PCU reported A-MSDU + present as well as a fragmented MPDU. A-MSDU defragmentation + is not supported in Lithium SW so this is treated as an + error. + +mpdu_fragment_number + + Field only valid when Reo_level_mpdu_frame_info. + Rx_mpdu_desc_info_details.Fragment_flag is set. + + + + The fragment number from the 802.11 header. + + + + Note that the sequence number is embedded in the field: + Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details. + Mpdu_sequence_number + + + + + +sw_exception + + When not set, REO is performing all its default MPDU + processing operations, + + When set, this REO entrance descriptor is generated by + FW, and should be processed as an exception. This implies: + + NO re-order function is needed. + + MPDU delinking is determined by the setting of field + SW_excection_mpdu_delink + + Destination ring selection is based on the setting of + the field SW_exception_destination_ring_valid + + In the destination ring descriptor set bit: + SW_exception_entry + + Feature supported only in HastingsPrime + + + +sw_exception_mpdu_delink + + Field only valid when SW_exception is set. + + 1'b0: REO should NOT delink the MPDU, and thus pass this + MPDU on to the destination ring as is. This implies that in + the REO_DESTINATION_RING struct field + Buf_or_link_desc_addr_info should point to an MSDU link + descriptor + + 1'b1: REO should perform the normal MPDU delink into + MSDU operations. + + Feature supported only in HastingsPrime + + + +sw_exception_destination_ring_valid + + Field only valid when SW_exception is set. + + 1'b0: REO shall push the MPDU (or delinked MPDU based on + the setting of SW_exception_mpdu_delink) to the destination + ring according to field reo_destination_indication. + + 1'b1: REO shall push the MPDU (or delinked MPDU based on + the setting of SW_exception_mpdu_delink) to the destination + ring according to field SW_exception_destination_ring. + + Feature supported only in HastingsPrime + + + +sw_exception_destination_ring + + Field only valid when fields SW_exception and + SW_exception_destination_ring_valid are set. + + The ID of the ring where REO shall push this frame. + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + Feature supported only in HastingsPrime + + + +reserved_6a + + + +phy_ppdu_id + + A PPDU counter value that PHY increments for every PPDU + received + + The counter value wraps around. Pine RXDMA can be + configured to copy this from the RX_PPDU_START TLV for every + output descriptor. + + + + This field is ignored by REO. + + + + Feature supported only in Pine + + + +reserved_7a + + + +ring_id + + Consumer: SW/REO/DEBUG + + Producer: SRNG (of RXDMA) + + + + For debugging. + + This field is filled in by the SRNG module. + + It help to identify the ring that is being looked + +looping_count + + Consumer: SW/REO/DEBUG + + Producer: SRNG (of RXDMA) + + + + For debugging. + + This field is filled in by the SRNG module. + + + + A count value that indicates the number of times the + producer of entries into this Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ + + + /* EXTERNAL REFERENCE : struct rx_mpdu_details reo_level_mpdu_frame_info */ + + + /* EXTERNAL REFERENCE : struct buffer_addr_info msdu_link_desc_addr_info */ + + +/* Description REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define REO_ENTRANCE_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + +*/ +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define REO_ENTRANCE_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + + /* EXTERNAL REFERENCE : struct rx_mpdu_desc_info rx_mpdu_desc_info_details */ + + +/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + The number of MSDUs within the MPDU + + +*/ +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + +/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + The field can have two different meanings based on the + setting of field 'BAR_frame': + + + + 'BAR_frame' is NOT set: + + The MPDU sequence number of the received frame. + + + + 'BAR_frame' is set. + + The MPDU Start sequence number from the BAR frame + + +*/ +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00 + +/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + When set, this MPDU is a fragment and REO should forward + this fragment MPDU to the REO destination ring without any + reorder checks, pn checks or bitmap update. This implies + that REO is forwarding the pointer to the MSDU link + descriptor. The destination ring is coming from a + programmable register setting in REO + + + + +*/ +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000 + +/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + The retry bit setting from the MPDU header of the + received frame + + +*/ +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000 + +/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + When set, the MPDU was received as part of an A-MPDU. + + +*/ +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000 + +/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + When set, the received frame is a BAR frame. After + processing, this frame shall be pushed to SW or deleted. + + +*/ +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000 + +/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + Copied here by RXDMA from RX_MPDU_END + + When not set, REO will Not perform a PN sequence number + check +*/ +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000 + +/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID + + When set, OLE found a valid SA entry for all MSDUs in + this MPDU + + +*/ +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000 + +/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT + + When set, at least 1 MSDU within the MPDU has an + unsuccessful MAC source address search due to the expiration + of the search timer. + + +*/ +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000 + +/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID + + When set, OLE found a valid DA entry for all MSDUs in + this MPDU + + +*/ +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000 + +/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC + + Field Only valid if da_is_valid is set + + + + When set, at least one of the DA addresses is a + Multicast or Broadcast address. + + +*/ +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000 + +/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT + + When set, at least 1 MSDU within the MPDU has an + unsuccessful MAC destination address search due to the + expiration of the search timer. + + +*/ +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000 + +/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU + + Field only valid when first_msdu_in_mpdu_flag is set. + + + + When set, the contents in the MSDU buffer contains a + 'RAW' MPDU. This 'RAW' MPDU might be spread out over + multiple MSDU buffers. + + +*/ +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 + +/* Description REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG + + The More Fragment bit setting from the MPDU header of + the received frame + + + + +*/ +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31 +#define REO_ENTRANCE_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000 + +/* Description REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + + +*/ +#define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define REO_ENTRANCE_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +/* Description REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0 + + Consumer: REO + + Producer: RXDMA + + + + Address (lower 32 bits) of the REO queue descriptor. + + +*/ +#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000010 +#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +/* Description REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32 + + Consumer: REO + + Producer: RXDMA + + + + Address (upper 8 bits) of the REO queue descriptor. + + +*/ +#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_ENTRANCE_RING_5_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +/* Description REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT + + An approximation of the number of bytes received in this + MPDU. + + Used to keeps stats on the amount of data flowing + through a queue. + + +*/ +#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_LSB 8 +#define REO_ENTRANCE_RING_5_ROUNDED_MPDU_BYTE_COUNT_MASK 0x003fff00 + +/* Description REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION + + RXDMA copy the MPDU's first MSDU's destination + indication field here. This is used for REO to be able to + re-route the packet to a different SW destination ring if + the packet is detected as error in REO. + + + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW2 ring + + Reo will push the frame + into the REO2SW3 ring + + Reo will push the frame + into the REO2SW4 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + Reo will push the frame + into the REO2SW5 ring (REO remaps this in chips without + REO2SW5 ring, e.g. Pine) + + Reo will push the frame + into the REO2SW6 ring (REO remaps this in chips without + REO2SW6 ring, e.g. Pine) + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + +*/ +#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_LSB 22 +#define REO_ENTRANCE_RING_5_REO_DESTINATION_INDICATION_MASK 0x07c00000 + +/* Description REO_ENTRANCE_RING_5_FRAMELESS_BAR + + When set, this REO entrance ring struct contains BAR + info from a multi TID BAR frame. The original multi TID BAR + frame itself contained all the REO info for the first TID, + but all the subsequent TID info and their linkage to the REO + descriptors is passed down as 'frameless' BAR info. + + + + The only fields valid in this descriptor when this bit + is set are: + + Rx_reo_queue_desc_addr_31_0 + + RX_reo_queue_desc_addr_39_32 + + + + And within the + + Reo_level_mpdu_frame_info: + + Within Rx_mpdu_desc_info_details: + + Mpdu_Sequence_number + + BAR_frame + + Peer_meta_data + + All other fields shall be set to 0 + + + + +*/ +#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_LSB 27 +#define REO_ENTRANCE_RING_5_FRAMELESS_BAR_MASK 0x08000000 + +/* Description REO_ENTRANCE_RING_5_RESERVED_5A + + +*/ +#define REO_ENTRANCE_RING_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_ENTRANCE_RING_5_RESERVED_5A_LSB 28 +#define REO_ENTRANCE_RING_5_RESERVED_5A_MASK 0xf0000000 + +/* Description REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON + + Indicates why rxdma pushed the frame to this ring + + + + This field is ignored by REO. + + + + RXDMA detected an error an + pushed this frame to this queue + + RXDMA pushed the + frame to this queue per received routing instructions. No + error within RXDMA was detected + + RXDMA received an RX_FLUSH. As a + result the MSDU link descriptor might not have the + last_msdu_in_mpdu_flag set, but instead WBM might just see a + NULL pointer in the MSDU link descriptor. This is to be + considered a normal condition for this scenario. + + + + +*/ +#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB 0 +#define REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK 0x00000003 + +/* Description REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE + + Field only valid when 'rxdma_push_reason' set to + 'rxdma_error_detected'. + + + + This field is ignored by REO. + + + + MPDU frame is not complete + due to a FIFO overflow error in RXPCU. + + MPDU frame is not complete + due to receiving incomplete MPDU from the PHY + + + CRYPTO reported a decryption + error or CRYPTO received an encrypted frame, but did not get + a valid corresponding key id in the peer entry. + + CRYPTO reported a TKIP MIC + error + + CRYPTO reported an + unencrypted frame error when encrypted was expected + + RX OLE reported an MSDU + length error + + RX OLE reported that max + number of MSDUs allowed in an MPDU got exceeded + + RX OLE reported a parsing + error + + RX OLE reported an A-MSDU + parsing error + + RX OLE reported a timeout + during SA search + + RX OLE reported a timeout + during DA search + + RX OLE reported a + timeout during flow search + + RXDMA received a flush + request + + Rx PCU reported A-MSDU + present as well as a fragmented MPDU. A-MSDU defragmentation + is not supported in Lithium SW so this is treated as an + error. +*/ +#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB 2 +#define REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK 0x0000007c + +/* Description REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER + + Field only valid when Reo_level_mpdu_frame_info. + Rx_mpdu_desc_info_details.Fragment_flag is set. + + + + The fragment number from the 802.11 header. + + + + Note that the sequence number is embedded in the field: + Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details. + Mpdu_sequence_number + + + + +*/ +#define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_LSB 7 +#define REO_ENTRANCE_RING_6_MPDU_FRAGMENT_NUMBER_MASK 0x00000780 + +/* Description REO_ENTRANCE_RING_6_SW_EXCEPTION + + When not set, REO is performing all its default MPDU + processing operations, + + When set, this REO entrance descriptor is generated by + FW, and should be processed as an exception. This implies: + + NO re-order function is needed. + + MPDU delinking is determined by the setting of field + SW_excection_mpdu_delink + + Destination ring selection is based on the setting of + the field SW_exception_destination_ring_valid + + In the destination ring descriptor set bit: + SW_exception_entry + + Feature supported only in HastingsPrime + + +*/ +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_LSB 11 +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_MASK 0x00000800 + +/* Description REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK + + Field only valid when SW_exception is set. + + 1'b0: REO should NOT delink the MPDU, and thus pass this + MPDU on to the destination ring as is. This implies that in + the REO_DESTINATION_RING struct field + Buf_or_link_desc_addr_info should point to an MSDU link + descriptor + + 1'b1: REO should perform the normal MPDU delink into + MSDU operations. + + Feature supported only in HastingsPrime + + +*/ +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_LSB 12 +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_MPDU_DELINK_MASK 0x00001000 + +/* Description REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID + + Field only valid when SW_exception is set. + + 1'b0: REO shall push the MPDU (or delinked MPDU based on + the setting of SW_exception_mpdu_delink) to the destination + ring according to field reo_destination_indication. + + 1'b1: REO shall push the MPDU (or delinked MPDU based on + the setting of SW_exception_mpdu_delink) to the destination + ring according to field SW_exception_destination_ring. + + Feature supported only in HastingsPrime + + +*/ +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_LSB 13 +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_VALID_MASK 0x00002000 + +/* Description REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING + + Field only valid when fields SW_exception and + SW_exception_destination_ring_valid are set. + + The ID of the ring where REO shall push this frame. + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + Feature supported only in HastingsPrime + + +*/ +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_LSB 14 +#define REO_ENTRANCE_RING_6_SW_EXCEPTION_DESTINATION_RING_MASK 0x0007c000 + +/* Description REO_ENTRANCE_RING_6_RESERVED_6A + + +*/ +#define REO_ENTRANCE_RING_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_ENTRANCE_RING_6_RESERVED_6A_LSB 19 +#define REO_ENTRANCE_RING_6_RESERVED_6A_MASK 0xfff80000 + +/* Description REO_ENTRANCE_RING_7_PHY_PPDU_ID + + A PPDU counter value that PHY increments for every PPDU + received + + The counter value wraps around. Pine RXDMA can be + configured to copy this from the RX_PPDU_START TLV for every + output descriptor. + + + + This field is ignored by REO. + + + + Feature supported only in Pine + + +*/ +#define REO_ENTRANCE_RING_7_PHY_PPDU_ID_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_7_PHY_PPDU_ID_LSB 0 +#define REO_ENTRANCE_RING_7_PHY_PPDU_ID_MASK 0x0000ffff + +/* Description REO_ENTRANCE_RING_7_RESERVED_7A + + +*/ +#define REO_ENTRANCE_RING_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_7_RESERVED_7A_LSB 16 +#define REO_ENTRANCE_RING_7_RESERVED_7A_MASK 0x000f0000 + +/* Description REO_ENTRANCE_RING_7_RING_ID + + Consumer: SW/REO/DEBUG + + Producer: SRNG (of RXDMA) + + + + For debugging. + + This field is filled in by the SRNG module. + + It help to identify the ring that is being looked +*/ +#define REO_ENTRANCE_RING_7_RING_ID_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_7_RING_ID_LSB 20 +#define REO_ENTRANCE_RING_7_RING_ID_MASK 0x0ff00000 + +/* Description REO_ENTRANCE_RING_7_LOOPING_COUNT + + Consumer: SW/REO/DEBUG + + Producer: SRNG (of RXDMA) + + + + For debugging. + + This field is filled in by the SRNG module. + + + + A count value that indicates the number of times the + producer of entries into this Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ +#define REO_ENTRANCE_RING_7_LOOPING_COUNT_OFFSET 0x0000001c +#define REO_ENTRANCE_RING_7_LOOPING_COUNT_LSB 28 +#define REO_ENTRANCE_RING_7_LOOPING_COUNT_MASK 0xf0000000 + + +#endif // _REO_ENTRANCE_RING_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/reo_flush_cache.h b/drivers/staging/fw-api/hw/qca6750/v1/reo_flush_cache.h new file mode 100644 index 000000000000..077fd1aee4c6 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/reo_flush_cache.h @@ -0,0 +1,540 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _REO_FLUSH_CACHE_H_ +#define _REO_FLUSH_CACHE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 struct uniform_reo_cmd_header cmd_header; +// 1 flush_addr_31_0[31:0] +// 2 flush_addr_39_32[7:0], forward_all_mpdus_in_queue[8], release_cache_block_index[9], cache_block_resource_index[11:10], flush_without_invalidate[12], block_cache_usage_after_flush[13], flush_entire_cache[14], reserved_2b[31:15] +// 3 reserved_3a[31:0] +// 4 reserved_4a[31:0] +// 5 reserved_5a[31:0] +// 6 reserved_6a[31:0] +// 7 reserved_7a[31:0] +// 8 reserved_8a[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_REO_FLUSH_CACHE 9 + +struct reo_flush_cache { + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_addr_31_0 : 32; //[31:0] + uint32_t flush_addr_39_32 : 8, //[7:0] + forward_all_mpdus_in_queue : 1, //[8] + release_cache_block_index : 1, //[9] + cache_block_resource_index : 2, //[11:10] + flush_without_invalidate : 1, //[12] + block_cache_usage_after_flush : 1, //[13] + flush_entire_cache : 1, //[14] + reserved_2b : 17; //[31:15] + uint32_t reserved_3a : 32; //[31:0] + uint32_t reserved_4a : 32; //[31:0] + uint32_t reserved_5a : 32; //[31:0] + uint32_t reserved_6a : 32; //[31:0] + uint32_t reserved_7a : 32; //[31:0] + uint32_t reserved_8a : 32; //[31:0] +}; + +/* + +struct uniform_reo_cmd_header cmd_header + + Consumer: REO + + Producer: SW + + + + Details for command execution tracking purposes. + +flush_addr_31_0 + + Consumer: REO + + Producer: SW + + + + Address (lower 32 bits) of the descriptor to flush + + + +flush_addr_39_32 + + Consumer: REO + + Producer: SW + + + + Address (upper 8 bits) of the descriptor to flush + + + +forward_all_mpdus_in_queue + + Is only allowed to be set when the flush address + corresponds with a REO descriptor. + + + + When set, REO shall first forward all the MPDUs held in + the indicated re-order queue, before flushing the descriptor + from the cache. + + + +release_cache_block_index + + Field not valid when Flush_entire_cache is set. + + + + If SW has previously used a blocking resource that it + now wants to re-use for this command, this bit shall be set. + It prevents SW from having to send a separate + REO_UNBLOCK_CACHE command. + + + + When set, HW will first release the blocking resource + (indicated in field 'Cache_block_resouce_index') before this + command gets executed. + + If that resource was already unblocked, this will be + considered an error. This command will not be executed, and + an error shall be returned. + + + +cache_block_resource_index + + Field not valid when Flush_entire_cache is set. + + + + Indicates which of the four blocking resources in REO + will be assigned for managing the blocking of this + (descriptor) address + + + +flush_without_invalidate + + Field not valid when Flush_entire_cache is set. + + + + When set, REO shall flush the cache line contents from + the cache, but there is NO need to invalidate the cache line + entry... The contents in the cache can be maintained. This + feature can be used by SW (and DV) to get a current snapshot + of the contents in the cache + + + + + +block_cache_usage_after_flush + + Field not valid when Flush_entire_cache is set. + + + + When set, REO shall block any cache accesses to this + address till explicitly unblocked. + + + + Whenever SW sets this bit, SW shall also set bit + 'Forward_all_mpdus_in_queue' to ensure all packets are + flushed out in order to make sure this queue desc is not in + one of the aging link lists. In case SW does not want to + flush the MPDUs in the queue, see the recipe description + below this TLV definition. + + + + The 'blocking' index to be used for this is indicated in + field 'cache_block_resource_index'. If SW had previously + used this blocking resource and was not freed up yet, SW + shall first unblock that index (by setting bit + Release_cache_block_index) or use an unblock command. + + + + If the resource indicated here was already blocked (and + did not get unblocked in this command), it is considered an + error scenario... + + No flush shall happen. The status for this command shall + indicate error. + + + + + +flush_entire_cache + + When set, the entire cache shall be flushed. The entire + cache will also remain blocked, till the + 'REO_UNBLOCK_COMMAND' is received with bit unblock type set + to unblock_cache. All other fields in this command are to be + ignored. + + + + Note that flushing the entire cache has no changes to + the current settings of the blocking resource settings + + + + + +reserved_2b + + + +reserved_3a + + + +reserved_4a + + + +reserved_5a + + + +reserved_6a + + + +reserved_7a + + + +reserved_8a + + +*/ + + + /* EXTERNAL REFERENCE : struct uniform_reo_cmd_header cmd_header */ + + +/* Description REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER + + Consumer: REO/SW/DEBUG + + Producer: SW + + + + This number can be used by SW to track, identify and + link the created commands with the command statusses + + + + + + +*/ +#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +/* Description REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED + + Consumer: REO + + Producer: SW + + + + REO does not need to generate a status + TLV for the execution of this command + + REO shall generate a status TLV + for the execution of this command + + + + +*/ +#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_FLUSH_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +/* Description REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A + + +*/ +#define REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_FLUSH_CACHE_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +/* Description REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0 + + Consumer: REO + + Producer: SW + + + + Address (lower 32 bits) of the descriptor to flush + + +*/ +#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_OFFSET 0x00000004 +#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_LSB 0 +#define REO_FLUSH_CACHE_1_FLUSH_ADDR_31_0_MASK 0xffffffff + +/* Description REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32 + + Consumer: REO + + Producer: SW + + + + Address (upper 8 bits) of the descriptor to flush + + +*/ +#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_LSB 0 +#define REO_FLUSH_CACHE_2_FLUSH_ADDR_39_32_MASK 0x000000ff + +/* Description REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE + + Is only allowed to be set when the flush address + corresponds with a REO descriptor. + + + + When set, REO shall first forward all the MPDUs held in + the indicated re-order queue, before flushing the descriptor + from the cache. + + +*/ +#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_LSB 8 +#define REO_FLUSH_CACHE_2_FORWARD_ALL_MPDUS_IN_QUEUE_MASK 0x00000100 + +/* Description REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX + + Field not valid when Flush_entire_cache is set. + + + + If SW has previously used a blocking resource that it + now wants to re-use for this command, this bit shall be set. + It prevents SW from having to send a separate + REO_UNBLOCK_CACHE command. + + + + When set, HW will first release the blocking resource + (indicated in field 'Cache_block_resouce_index') before this + command gets executed. + + If that resource was already unblocked, this will be + considered an error. This command will not be executed, and + an error shall be returned. + + +*/ +#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_LSB 9 +#define REO_FLUSH_CACHE_2_RELEASE_CACHE_BLOCK_INDEX_MASK 0x00000200 + +/* Description REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX + + Field not valid when Flush_entire_cache is set. + + + + Indicates which of the four blocking resources in REO + will be assigned for managing the blocking of this + (descriptor) address + + +*/ +#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_LSB 10 +#define REO_FLUSH_CACHE_2_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x00000c00 + +/* Description REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE + + Field not valid when Flush_entire_cache is set. + + + + When set, REO shall flush the cache line contents from + the cache, but there is NO need to invalidate the cache line + entry... The contents in the cache can be maintained. This + feature can be used by SW (and DV) to get a current snapshot + of the contents in the cache + + + + +*/ +#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_LSB 12 +#define REO_FLUSH_CACHE_2_FLUSH_WITHOUT_INVALIDATE_MASK 0x00001000 + +/* Description REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH + + Field not valid when Flush_entire_cache is set. + + + + When set, REO shall block any cache accesses to this + address till explicitly unblocked. + + + + Whenever SW sets this bit, SW shall also set bit + 'Forward_all_mpdus_in_queue' to ensure all packets are + flushed out in order to make sure this queue desc is not in + one of the aging link lists. In case SW does not want to + flush the MPDUs in the queue, see the recipe description + below this TLV definition. + + + + The 'blocking' index to be used for this is indicated in + field 'cache_block_resource_index'. If SW had previously + used this blocking resource and was not freed up yet, SW + shall first unblock that index (by setting bit + Release_cache_block_index) or use an unblock command. + + + + If the resource indicated here was already blocked (and + did not get unblocked in this command), it is considered an + error scenario... + + No flush shall happen. The status for this command shall + indicate error. + + + + +*/ +#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_LSB 13 +#define REO_FLUSH_CACHE_2_BLOCK_CACHE_USAGE_AFTER_FLUSH_MASK 0x00002000 + +/* Description REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE + + When set, the entire cache shall be flushed. The entire + cache will also remain blocked, till the + 'REO_UNBLOCK_COMMAND' is received with bit unblock type set + to unblock_cache. All other fields in this command are to be + ignored. + + + + Note that flushing the entire cache has no changes to + the current settings of the blocking resource settings + + + + +*/ +#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_LSB 14 +#define REO_FLUSH_CACHE_2_FLUSH_ENTIRE_CACHE_MASK 0x00004000 + +/* Description REO_FLUSH_CACHE_2_RESERVED_2B + + +*/ +#define REO_FLUSH_CACHE_2_RESERVED_2B_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_2_RESERVED_2B_LSB 15 +#define REO_FLUSH_CACHE_2_RESERVED_2B_MASK 0xffff8000 + +/* Description REO_FLUSH_CACHE_3_RESERVED_3A + + +*/ +#define REO_FLUSH_CACHE_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_3_RESERVED_3A_LSB 0 +#define REO_FLUSH_CACHE_3_RESERVED_3A_MASK 0xffffffff + +/* Description REO_FLUSH_CACHE_4_RESERVED_4A + + +*/ +#define REO_FLUSH_CACHE_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_FLUSH_CACHE_4_RESERVED_4A_LSB 0 +#define REO_FLUSH_CACHE_4_RESERVED_4A_MASK 0xffffffff + +/* Description REO_FLUSH_CACHE_5_RESERVED_5A + + +*/ +#define REO_FLUSH_CACHE_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_FLUSH_CACHE_5_RESERVED_5A_LSB 0 +#define REO_FLUSH_CACHE_5_RESERVED_5A_MASK 0xffffffff + +/* Description REO_FLUSH_CACHE_6_RESERVED_6A + + +*/ +#define REO_FLUSH_CACHE_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_FLUSH_CACHE_6_RESERVED_6A_LSB 0 +#define REO_FLUSH_CACHE_6_RESERVED_6A_MASK 0xffffffff + +/* Description REO_FLUSH_CACHE_7_RESERVED_7A + + +*/ +#define REO_FLUSH_CACHE_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_FLUSH_CACHE_7_RESERVED_7A_LSB 0 +#define REO_FLUSH_CACHE_7_RESERVED_7A_MASK 0xffffffff + +/* Description REO_FLUSH_CACHE_8_RESERVED_8A + + +*/ +#define REO_FLUSH_CACHE_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_FLUSH_CACHE_8_RESERVED_8A_LSB 0 +#define REO_FLUSH_CACHE_8_RESERVED_8A_MASK 0xffffffff + + +#endif // _REO_FLUSH_CACHE_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/reo_flush_cache_status.h b/drivers/staging/fw-api/hw/qca6750/v1/reo_flush_cache_status.h new file mode 100644 index 000000000000..27a7ff7d5328 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/reo_flush_cache_status.h @@ -0,0 +1,803 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _REO_FLUSH_CACHE_STATUS_H_ +#define _REO_FLUSH_CACHE_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct uniform_reo_status_header status_header; +// 2 error_detected[0], block_error_details[2:1], reserved_2a[7:3], cache_controller_flush_status_hit[8], cache_controller_flush_status_desc_type[11:9], cache_controller_flush_status_client_id[15:12], cache_controller_flush_status_error[17:16], cache_controller_flush_count[25:18], reserved_2b[31:26] +// 3 reserved_3a[31:0] +// 4 reserved_4a[31:0] +// 5 reserved_5a[31:0] +// 6 reserved_6a[31:0] +// 7 reserved_7a[31:0] +// 8 reserved_8a[31:0] +// 9 reserved_9a[31:0] +// 10 reserved_10a[31:0] +// 11 reserved_11a[31:0] +// 12 reserved_12a[31:0] +// 13 reserved_13a[31:0] +// 14 reserved_14a[31:0] +// 15 reserved_15a[31:0] +// 16 reserved_16a[31:0] +// 17 reserved_17a[31:0] +// 18 reserved_18a[31:0] +// 19 reserved_19a[31:0] +// 20 reserved_20a[31:0] +// 21 reserved_21a[31:0] +// 22 reserved_22a[31:0] +// 23 reserved_23a[31:0] +// 24 reserved_24a[27:0], looping_count[31:28] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_REO_FLUSH_CACHE_STATUS 25 + +struct reo_flush_cache_status { + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, //[0] + block_error_details : 2, //[2:1] + reserved_2a : 5, //[7:3] + cache_controller_flush_status_hit: 1, //[8] + cache_controller_flush_status_desc_type: 3, //[11:9] + cache_controller_flush_status_client_id: 4, //[15:12] + cache_controller_flush_status_error: 2, //[17:16] + cache_controller_flush_count : 8, //[25:18] + reserved_2b : 6; //[31:26] + uint32_t reserved_3a : 32; //[31:0] + uint32_t reserved_4a : 32; //[31:0] + uint32_t reserved_5a : 32; //[31:0] + uint32_t reserved_6a : 32; //[31:0] + uint32_t reserved_7a : 32; //[31:0] + uint32_t reserved_8a : 32; //[31:0] + uint32_t reserved_9a : 32; //[31:0] + uint32_t reserved_10a : 32; //[31:0] + uint32_t reserved_11a : 32; //[31:0] + uint32_t reserved_12a : 32; //[31:0] + uint32_t reserved_13a : 32; //[31:0] + uint32_t reserved_14a : 32; //[31:0] + uint32_t reserved_15a : 32; //[31:0] + uint32_t reserved_16a : 32; //[31:0] + uint32_t reserved_17a : 32; //[31:0] + uint32_t reserved_18a : 32; //[31:0] + uint32_t reserved_19a : 32; //[31:0] + uint32_t reserved_20a : 32; //[31:0] + uint32_t reserved_21a : 32; //[31:0] + uint32_t reserved_22a : 32; //[31:0] + uint32_t reserved_23a : 32; //[31:0] + uint32_t reserved_24a : 28, //[27:0] + looping_count : 4; //[31:28] +}; + +/* + +struct uniform_reo_status_header status_header + + Consumer: SW + + Producer: REO + + + + Details that can link this status with the original + command. It also contains info on how long REO took to + execute this command. + +error_detected + + Status for blocking resource handling + + + + 0: No error has been detected while executing this + command + + 1: an error in the blocking resource management was + detected + + See field 'Block_error_details' + +block_error_details + + Field only valid when 'Error_detected' is set. + + 0: no blocking related error found + + 1: blocking resource was already in use + + 2: resource that was asked to be unblocked, was not + blocked + + + +reserved_2a + + + +cache_controller_flush_status_hit + + The status that the cache controller returned for + executing the flush command + + + + descriptor hit + + 1 = hit + + 0 = miss + + + +cache_controller_flush_status_desc_type + + The status that the cache controller returned for + executing the flush command + + Descriptor type + + FLOW_QUEUE_DESCRIPTOR                 + 3'd0 + + + + +cache_controller_flush_status_client_id + + The status that the cache controller returned for + executing the flush command + + + + client ID + + Module who made flush the request + + + + In REO, this is always set to 0 + + + +cache_controller_flush_status_error + + The status that the cache controller returned for + executing the flush command + + + + Error condition + + 2'b00: No error found + + 2'b01: HW IF still busy + + 2'b10: Line is currently locked. Used for the one line + flush command. + + 2'b11: At least one line is currently still locked. Used + for the cache flush command. + + + + + +cache_controller_flush_count + + The number of lines that were actually flushed out. + + + +reserved_2b + + + +reserved_3a + + + +reserved_4a + + + +reserved_5a + + + +reserved_6a + + + +reserved_7a + + + +reserved_8a + + + +reserved_9a + + + +reserved_10a + + + +reserved_11a + + + +reserved_12a + + + +reserved_13a + + + +reserved_14a + + + +reserved_15a + + + +reserved_16a + + + +reserved_17a + + + +reserved_18a + + + +reserved_19a + + + +reserved_20a + + + +reserved_21a + + + +reserved_22a + + + +reserved_23a + + + +reserved_24a + + + +looping_count + + A count value that indicates the number of times the + producer of entries into this Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ + + + /* EXTERNAL REFERENCE : struct uniform_reo_status_header status_header */ + + +/* Description REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER + + Consumer: SW , DEBUG + + Producer: REO + + + + The value in this field is equal to value of the + 'REO_CMD_Number' field the REO command + + + + This field helps to correlate the statuses with the REO + commands. + + + + +*/ +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +/* Description REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME + + Consumer: DEBUG + + Producer: REO + + + + The amount of time REO took to excecute the command. + Note that this time does not include the duration of the + command waiting in the command ring, before the execution + started. + + + + In us. + + + + +*/ +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +/* Description REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS + + Consumer: DEBUG + + Producer: REO + + + + Execution status of the command. + + + + Command has + successfully be executed + + Command could not be + executed as the queue or cache was blocked + + Command has encountered + problems when executing, like the queue descriptor not being + valid. None of the status fields in the entire STATUS TLV + are valid. + + Command is NOT executed + because one or more descriptors were blocked. This is SW + programming mistake. + + None of the status fields in the entire STATUS TLV are + valid. + + + + +*/ +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +/* Description REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A + + +*/ +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_FLUSH_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +/* Description REO_FLUSH_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP + + Timestamp at the moment that this status report is + written. + + + + +*/ +#define REO_FLUSH_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define REO_FLUSH_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_FLUSH_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +/* Description REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED + + Status for blocking resource handling + + + + 0: No error has been detected while executing this + command + + 1: an error in the blocking resource management was + detected + + See field 'Block_error_details' +*/ +#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_LSB 0 +#define REO_FLUSH_CACHE_STATUS_2_ERROR_DETECTED_MASK 0x00000001 + +/* Description REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS + + Field only valid when 'Error_detected' is set. + + 0: no blocking related error found + + 1: blocking resource was already in use + + 2: resource that was asked to be unblocked, was not + blocked + + +*/ +#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_LSB 1 +#define REO_FLUSH_CACHE_STATUS_2_BLOCK_ERROR_DETAILS_MASK 0x00000006 + +/* Description REO_FLUSH_CACHE_STATUS_2_RESERVED_2A + + +*/ +#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_LSB 3 +#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2A_MASK 0x000000f8 + +/* Description REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT + + The status that the cache controller returned for + executing the flush command + + + + descriptor hit + + 1 = hit + + 0 = miss + + +*/ +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_LSB 8 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_HIT_MASK 0x00000100 + +/* Description REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE + + The status that the cache controller returned for + executing the flush command + + Descriptor type + + FLOW_QUEUE_DESCRIPTOR                 + 3'd0 + + + +*/ +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_LSB 9 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_DESC_TYPE_MASK 0x00000e00 + +/* Description REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID + + The status that the cache controller returned for + executing the flush command + + + + client ID + + Module who made flush the request + + + + In REO, this is always set to 0 + + +*/ +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_LSB 12 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_CLIENT_ID_MASK 0x0000f000 + +/* Description REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR + + The status that the cache controller returned for + executing the flush command + + + + Error condition + + 2'b00: No error found + + 2'b01: HW IF still busy + + 2'b10: Line is currently locked. Used for the one line + flush command. + + 2'b11: At least one line is currently still locked. Used + for the cache flush command. + + + + +*/ +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_LSB 16 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_STATUS_ERROR_MASK 0x00030000 + +/* Description REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT + + The number of lines that were actually flushed out. + + +*/ +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_LSB 18 +#define REO_FLUSH_CACHE_STATUS_2_CACHE_CONTROLLER_FLUSH_COUNT_MASK 0x03fc0000 + +/* Description REO_FLUSH_CACHE_STATUS_2_RESERVED_2B + + +*/ +#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_OFFSET 0x00000008 +#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_LSB 26 +#define REO_FLUSH_CACHE_STATUS_2_RESERVED_2B_MASK 0xfc000000 + +/* Description REO_FLUSH_CACHE_STATUS_3_RESERVED_3A + + +*/ +#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_3_RESERVED_3A_MASK 0xffffffff + +/* Description REO_FLUSH_CACHE_STATUS_4_RESERVED_4A + + +*/ +#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_4_RESERVED_4A_MASK 0xffffffff + +/* Description REO_FLUSH_CACHE_STATUS_5_RESERVED_5A + + +*/ +#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_5_RESERVED_5A_MASK 0xffffffff + +/* Description REO_FLUSH_CACHE_STATUS_6_RESERVED_6A + + +*/ +#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_6_RESERVED_6A_MASK 0xffffffff + +/* Description REO_FLUSH_CACHE_STATUS_7_RESERVED_7A + + +*/ +#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_7_RESERVED_7A_MASK 0xffffffff + +/* Description REO_FLUSH_CACHE_STATUS_8_RESERVED_8A + + +*/ +#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_8_RESERVED_8A_MASK 0xffffffff + +/* Description REO_FLUSH_CACHE_STATUS_9_RESERVED_9A + + +*/ +#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_OFFSET 0x00000024 +#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_9_RESERVED_9A_MASK 0xffffffff + +/* Description REO_FLUSH_CACHE_STATUS_10_RESERVED_10A + + +*/ +#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_OFFSET 0x00000028 +#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_10_RESERVED_10A_MASK 0xffffffff + +/* Description REO_FLUSH_CACHE_STATUS_11_RESERVED_11A + + +*/ +#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c +#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_11_RESERVED_11A_MASK 0xffffffff + +/* Description REO_FLUSH_CACHE_STATUS_12_RESERVED_12A + + +*/ +#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_OFFSET 0x00000030 +#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_12_RESERVED_12A_MASK 0xffffffff + +/* Description REO_FLUSH_CACHE_STATUS_13_RESERVED_13A + + +*/ +#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_OFFSET 0x00000034 +#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_13_RESERVED_13A_MASK 0xffffffff + +/* Description REO_FLUSH_CACHE_STATUS_14_RESERVED_14A + + +*/ +#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_OFFSET 0x00000038 +#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_14_RESERVED_14A_MASK 0xffffffff + +/* Description REO_FLUSH_CACHE_STATUS_15_RESERVED_15A + + +*/ +#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c +#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_15_RESERVED_15A_MASK 0xffffffff + +/* Description REO_FLUSH_CACHE_STATUS_16_RESERVED_16A + + +*/ +#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_OFFSET 0x00000040 +#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_16_RESERVED_16A_MASK 0xffffffff + +/* Description REO_FLUSH_CACHE_STATUS_17_RESERVED_17A + + +*/ +#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_OFFSET 0x00000044 +#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_17_RESERVED_17A_MASK 0xffffffff + +/* Description REO_FLUSH_CACHE_STATUS_18_RESERVED_18A + + +*/ +#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_OFFSET 0x00000048 +#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_18_RESERVED_18A_MASK 0xffffffff + +/* Description REO_FLUSH_CACHE_STATUS_19_RESERVED_19A + + +*/ +#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c +#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_19_RESERVED_19A_MASK 0xffffffff + +/* Description REO_FLUSH_CACHE_STATUS_20_RESERVED_20A + + +*/ +#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_OFFSET 0x00000050 +#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_20_RESERVED_20A_MASK 0xffffffff + +/* Description REO_FLUSH_CACHE_STATUS_21_RESERVED_21A + + +*/ +#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_OFFSET 0x00000054 +#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_21_RESERVED_21A_MASK 0xffffffff + +/* Description REO_FLUSH_CACHE_STATUS_22_RESERVED_22A + + +*/ +#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_OFFSET 0x00000058 +#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_22_RESERVED_22A_MASK 0xffffffff + +/* Description REO_FLUSH_CACHE_STATUS_23_RESERVED_23A + + +*/ +#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c +#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_23_RESERVED_23A_MASK 0xffffffff + +/* Description REO_FLUSH_CACHE_STATUS_24_RESERVED_24A + + +*/ +#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_OFFSET 0x00000060 +#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_LSB 0 +#define REO_FLUSH_CACHE_STATUS_24_RESERVED_24A_MASK 0x0fffffff + +/* Description REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT + + A count value that indicates the number of times the + producer of entries into this Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ +#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 +#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_LSB 28 +#define REO_FLUSH_CACHE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 + + +#endif // _REO_FLUSH_CACHE_STATUS_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/reo_flush_queue.h b/drivers/staging/fw-api/hw/qca6750/v1/reo_flush_queue.h new file mode 100644 index 000000000000..885c1a322754 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/reo_flush_queue.h @@ -0,0 +1,357 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _REO_FLUSH_QUEUE_H_ +#define _REO_FLUSH_QUEUE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 struct uniform_reo_cmd_header cmd_header; +// 1 flush_desc_addr_31_0[31:0] +// 2 flush_desc_addr_39_32[7:0], block_desc_addr_usage_after_flush[8], block_resource_index[10:9], invalidate_queue_and_flush[11], reserved_2a[31:12] +// 3 reserved_3a[31:0] +// 4 reserved_4a[31:0] +// 5 reserved_5a[31:0] +// 6 reserved_6a[31:0] +// 7 reserved_7a[31:0] +// 8 reserved_8a[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_REO_FLUSH_QUEUE 9 + +struct reo_flush_queue { + struct uniform_reo_cmd_header cmd_header; + uint32_t flush_desc_addr_31_0 : 32; //[31:0] + uint32_t flush_desc_addr_39_32 : 8, //[7:0] + block_desc_addr_usage_after_flush: 1, //[8] + block_resource_index : 2, //[10:9] + invalidate_queue_and_flush : 1, //[11] + reserved_2a : 20; //[31:12] + uint32_t reserved_3a : 32; //[31:0] + uint32_t reserved_4a : 32; //[31:0] + uint32_t reserved_5a : 32; //[31:0] + uint32_t reserved_6a : 32; //[31:0] + uint32_t reserved_7a : 32; //[31:0] + uint32_t reserved_8a : 32; //[31:0] +}; + +/* + +struct uniform_reo_cmd_header cmd_header + + Consumer: REO + + Producer: SW + + + + Details for command execution tracking purposes. + +flush_desc_addr_31_0 + + Consumer: REO + + Producer: SW + + + + Address (lower 32 bits) of the descriptor to flush + + + +flush_desc_addr_39_32 + + Consumer: REO + + Producer: SW + + + + Address (upper 8 bits) of the descriptor to flush + + + +block_desc_addr_usage_after_flush + + When set, REO shall not re-fetch this address till SW + explicitly unblocked this address + + + + If the blocking resource was already used, this command + shall fail and an error is reported + + + + + +block_resource_index + + Field only valid when 'Block_desc_addr_usage_after_flush + ' is set. + + + + Indicates which of the four blocking resources in REO + will be assigned for managing the blocking of this address. + + + +invalidate_queue_and_flush + + When set, after the queue has been completely flushed, + invalidate the queue by clearing VLD and flush the queue + descriptor from the cache. + + + + + +reserved_2a + + + +reserved_3a + + + +reserved_4a + + + +reserved_5a + + + +reserved_6a + + + +reserved_7a + + + +reserved_8a + + +*/ + + + /* EXTERNAL REFERENCE : struct uniform_reo_cmd_header cmd_header */ + + +/* Description REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER + + Consumer: REO/SW/DEBUG + + Producer: SW + + + + This number can be used by SW to track, identify and + link the created commands with the command statusses + + + + + + +*/ +#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +/* Description REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED + + Consumer: REO + + Producer: SW + + + + REO does not need to generate a status + TLV for the execution of this command + + REO shall generate a status TLV + for the execution of this command + + + + +*/ +#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_FLUSH_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +/* Description REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A + + +*/ +#define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_FLUSH_QUEUE_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +/* Description REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0 + + Consumer: REO + + Producer: SW + + + + Address (lower 32 bits) of the descriptor to flush + + +*/ +#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_OFFSET 0x00000004 +#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_LSB 0 +#define REO_FLUSH_QUEUE_1_FLUSH_DESC_ADDR_31_0_MASK 0xffffffff + +/* Description REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32 + + Consumer: REO + + Producer: SW + + + + Address (upper 8 bits) of the descriptor to flush + + +*/ +#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_LSB 0 +#define REO_FLUSH_QUEUE_2_FLUSH_DESC_ADDR_39_32_MASK 0x000000ff + +/* Description REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH + + When set, REO shall not re-fetch this address till SW + explicitly unblocked this address + + + + If the blocking resource was already used, this command + shall fail and an error is reported + + + + +*/ +#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_LSB 8 +#define REO_FLUSH_QUEUE_2_BLOCK_DESC_ADDR_USAGE_AFTER_FLUSH_MASK 0x00000100 + +/* Description REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX + + Field only valid when 'Block_desc_addr_usage_after_flush + ' is set. + + + + Indicates which of the four blocking resources in REO + will be assigned for managing the blocking of this address. + + +*/ +#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_LSB 9 +#define REO_FLUSH_QUEUE_2_BLOCK_RESOURCE_INDEX_MASK 0x00000600 + +/* Description REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH + + When set, after the queue has been completely flushed, + invalidate the queue by clearing VLD and flush the queue + descriptor from the cache. + + + + +*/ +#define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_LSB 11 +#define REO_FLUSH_QUEUE_2_INVALIDATE_QUEUE_AND_FLUSH_MASK 0x00000800 + +/* Description REO_FLUSH_QUEUE_2_RESERVED_2A + + +*/ +#define REO_FLUSH_QUEUE_2_RESERVED_2A_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_2_RESERVED_2A_LSB 12 +#define REO_FLUSH_QUEUE_2_RESERVED_2A_MASK 0xfffff000 + +/* Description REO_FLUSH_QUEUE_3_RESERVED_3A + + +*/ +#define REO_FLUSH_QUEUE_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_FLUSH_QUEUE_3_RESERVED_3A_LSB 0 +#define REO_FLUSH_QUEUE_3_RESERVED_3A_MASK 0xffffffff + +/* Description REO_FLUSH_QUEUE_4_RESERVED_4A + + +*/ +#define REO_FLUSH_QUEUE_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_FLUSH_QUEUE_4_RESERVED_4A_LSB 0 +#define REO_FLUSH_QUEUE_4_RESERVED_4A_MASK 0xffffffff + +/* Description REO_FLUSH_QUEUE_5_RESERVED_5A + + +*/ +#define REO_FLUSH_QUEUE_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_FLUSH_QUEUE_5_RESERVED_5A_LSB 0 +#define REO_FLUSH_QUEUE_5_RESERVED_5A_MASK 0xffffffff + +/* Description REO_FLUSH_QUEUE_6_RESERVED_6A + + +*/ +#define REO_FLUSH_QUEUE_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_FLUSH_QUEUE_6_RESERVED_6A_LSB 0 +#define REO_FLUSH_QUEUE_6_RESERVED_6A_MASK 0xffffffff + +/* Description REO_FLUSH_QUEUE_7_RESERVED_7A + + +*/ +#define REO_FLUSH_QUEUE_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_FLUSH_QUEUE_7_RESERVED_7A_LSB 0 +#define REO_FLUSH_QUEUE_7_RESERVED_7A_MASK 0xffffffff + +/* Description REO_FLUSH_QUEUE_8_RESERVED_8A + + +*/ +#define REO_FLUSH_QUEUE_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_FLUSH_QUEUE_8_RESERVED_8A_LSB 0 +#define REO_FLUSH_QUEUE_8_RESERVED_8A_MASK 0xffffffff + + +#endif // _REO_FLUSH_QUEUE_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/reo_flush_queue_status.h b/drivers/staging/fw-api/hw/qca6750/v1/reo_flush_queue_status.h new file mode 100644 index 000000000000..0c3dcd65ca8b --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/reo_flush_queue_status.h @@ -0,0 +1,578 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _REO_FLUSH_QUEUE_STATUS_H_ +#define _REO_FLUSH_QUEUE_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct uniform_reo_status_header status_header; +// 2 error_detected[0], reserved_2a[31:1] +// 3 reserved_3a[31:0] +// 4 reserved_4a[31:0] +// 5 reserved_5a[31:0] +// 6 reserved_6a[31:0] +// 7 reserved_7a[31:0] +// 8 reserved_8a[31:0] +// 9 reserved_9a[31:0] +// 10 reserved_10a[31:0] +// 11 reserved_11a[31:0] +// 12 reserved_12a[31:0] +// 13 reserved_13a[31:0] +// 14 reserved_14a[31:0] +// 15 reserved_15a[31:0] +// 16 reserved_16a[31:0] +// 17 reserved_17a[31:0] +// 18 reserved_18a[31:0] +// 19 reserved_19a[31:0] +// 20 reserved_20a[31:0] +// 21 reserved_21a[31:0] +// 22 reserved_22a[31:0] +// 23 reserved_23a[31:0] +// 24 reserved_24a[27:0], looping_count[31:28] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_REO_FLUSH_QUEUE_STATUS 25 + +struct reo_flush_queue_status { + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, //[0] + reserved_2a : 31; //[31:1] + uint32_t reserved_3a : 32; //[31:0] + uint32_t reserved_4a : 32; //[31:0] + uint32_t reserved_5a : 32; //[31:0] + uint32_t reserved_6a : 32; //[31:0] + uint32_t reserved_7a : 32; //[31:0] + uint32_t reserved_8a : 32; //[31:0] + uint32_t reserved_9a : 32; //[31:0] + uint32_t reserved_10a : 32; //[31:0] + uint32_t reserved_11a : 32; //[31:0] + uint32_t reserved_12a : 32; //[31:0] + uint32_t reserved_13a : 32; //[31:0] + uint32_t reserved_14a : 32; //[31:0] + uint32_t reserved_15a : 32; //[31:0] + uint32_t reserved_16a : 32; //[31:0] + uint32_t reserved_17a : 32; //[31:0] + uint32_t reserved_18a : 32; //[31:0] + uint32_t reserved_19a : 32; //[31:0] + uint32_t reserved_20a : 32; //[31:0] + uint32_t reserved_21a : 32; //[31:0] + uint32_t reserved_22a : 32; //[31:0] + uint32_t reserved_23a : 32; //[31:0] + uint32_t reserved_24a : 28, //[27:0] + looping_count : 4; //[31:28] +}; + +/* + +struct uniform_reo_status_header status_header + + Consumer: SW + + Producer: REO + + + + Details that can link this status with the original + command. It also contains info on how long REO took to + execute this command. + +error_detected + + Status of the blocking resource + + 0: No error has been detected while executing this + command + + 1: Error detected: The resource to be used for blocking + was already in use. + +reserved_2a + + + +reserved_3a + + + +reserved_4a + + + +reserved_5a + + + +reserved_6a + + + +reserved_7a + + + +reserved_8a + + + +reserved_9a + + + +reserved_10a + + + +reserved_11a + + + +reserved_12a + + + +reserved_13a + + + +reserved_14a + + + +reserved_15a + + + +reserved_16a + + + +reserved_17a + + + +reserved_18a + + + +reserved_19a + + + +reserved_20a + + + +reserved_21a + + + +reserved_22a + + + +reserved_23a + + + +reserved_24a + + + +looping_count + + A count value that indicates the number of times the + producer of entries into this Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ + + + /* EXTERNAL REFERENCE : struct uniform_reo_status_header status_header */ + + +/* Description REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER + + Consumer: SW , DEBUG + + Producer: REO + + + + The value in this field is equal to value of the + 'REO_CMD_Number' field the REO command + + + + This field helps to correlate the statuses with the REO + commands. + + + + +*/ +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +/* Description REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME + + Consumer: DEBUG + + Producer: REO + + + + The amount of time REO took to excecute the command. + Note that this time does not include the duration of the + command waiting in the command ring, before the execution + started. + + + + In us. + + + + +*/ +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +/* Description REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS + + Consumer: DEBUG + + Producer: REO + + + + Execution status of the command. + + + + Command has + successfully be executed + + Command could not be + executed as the queue or cache was blocked + + Command has encountered + problems when executing, like the queue descriptor not being + valid. None of the status fields in the entire STATUS TLV + are valid. + + Command is NOT executed + because one or more descriptors were blocked. This is SW + programming mistake. + + None of the status fields in the entire STATUS TLV are + valid. + + + + +*/ +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +/* Description REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A + + +*/ +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_FLUSH_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +/* Description REO_FLUSH_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP + + Timestamp at the moment that this status report is + written. + + + + +*/ +#define REO_FLUSH_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define REO_FLUSH_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +/* Description REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED + + Status of the blocking resource + + 0: No error has been detected while executing this + command + + 1: Error detected: The resource to be used for blocking + was already in use. +*/ +#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_2_ERROR_DETECTED_MASK 0x00000001 + +/* Description REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A + + +*/ +#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_OFFSET 0x00000008 +#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_LSB 1 +#define REO_FLUSH_QUEUE_STATUS_2_RESERVED_2A_MASK 0xfffffffe + +/* Description REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A + + +*/ +#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_3_RESERVED_3A_MASK 0xffffffff + +/* Description REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A + + +*/ +#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_4_RESERVED_4A_MASK 0xffffffff + +/* Description REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A + + +*/ +#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_5_RESERVED_5A_MASK 0xffffffff + +/* Description REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A + + +*/ +#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_6_RESERVED_6A_MASK 0xffffffff + +/* Description REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A + + +*/ +#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_7_RESERVED_7A_MASK 0xffffffff + +/* Description REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A + + +*/ +#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_8_RESERVED_8A_MASK 0xffffffff + +/* Description REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A + + +*/ +#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_OFFSET 0x00000024 +#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_9_RESERVED_9A_MASK 0xffffffff + +/* Description REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A + + +*/ +#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_OFFSET 0x00000028 +#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_10_RESERVED_10A_MASK 0xffffffff + +/* Description REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A + + +*/ +#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c +#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_11_RESERVED_11A_MASK 0xffffffff + +/* Description REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A + + +*/ +#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_OFFSET 0x00000030 +#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_12_RESERVED_12A_MASK 0xffffffff + +/* Description REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A + + +*/ +#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_OFFSET 0x00000034 +#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_13_RESERVED_13A_MASK 0xffffffff + +/* Description REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A + + +*/ +#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_OFFSET 0x00000038 +#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_14_RESERVED_14A_MASK 0xffffffff + +/* Description REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A + + +*/ +#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c +#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_15_RESERVED_15A_MASK 0xffffffff + +/* Description REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A + + +*/ +#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_OFFSET 0x00000040 +#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_16_RESERVED_16A_MASK 0xffffffff + +/* Description REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A + + +*/ +#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_OFFSET 0x00000044 +#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_17_RESERVED_17A_MASK 0xffffffff + +/* Description REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A + + +*/ +#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_OFFSET 0x00000048 +#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_18_RESERVED_18A_MASK 0xffffffff + +/* Description REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A + + +*/ +#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c +#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_19_RESERVED_19A_MASK 0xffffffff + +/* Description REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A + + +*/ +#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_OFFSET 0x00000050 +#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_20_RESERVED_20A_MASK 0xffffffff + +/* Description REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A + + +*/ +#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_OFFSET 0x00000054 +#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_21_RESERVED_21A_MASK 0xffffffff + +/* Description REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A + + +*/ +#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_OFFSET 0x00000058 +#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_22_RESERVED_22A_MASK 0xffffffff + +/* Description REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A + + +*/ +#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c +#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_23_RESERVED_23A_MASK 0xffffffff + +/* Description REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A + + +*/ +#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_OFFSET 0x00000060 +#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_LSB 0 +#define REO_FLUSH_QUEUE_STATUS_24_RESERVED_24A_MASK 0x0fffffff + +/* Description REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT + + A count value that indicates the number of times the + producer of entries into this Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ +#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 +#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_LSB 28 +#define REO_FLUSH_QUEUE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 + + +#endif // _REO_FLUSH_QUEUE_STATUS_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/reo_flush_timeout_list.h b/drivers/staging/fw-api/hw/qca6750/v1/reo_flush_timeout_list.h new file mode 100644 index 000000000000..fe045f966b04 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/reo_flush_timeout_list.h @@ -0,0 +1,371 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _REO_FLUSH_TIMEOUT_LIST_H_ +#define _REO_FLUSH_TIMEOUT_LIST_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 struct uniform_reo_cmd_header cmd_header; +// 1 ac_timout_list[1:0], reserved_1[31:2] +// 2 minimum_release_desc_count[15:0], minimum_forward_buf_count[31:16] +// 3 reserved_3a[31:0] +// 4 reserved_4a[31:0] +// 5 reserved_5a[31:0] +// 6 reserved_6a[31:0] +// 7 reserved_7a[31:0] +// 8 reserved_8a[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST 9 + +struct reo_flush_timeout_list { + struct uniform_reo_cmd_header cmd_header; + uint32_t ac_timout_list : 2, //[1:0] + reserved_1 : 30; //[31:2] + uint32_t minimum_release_desc_count : 16, //[15:0] + minimum_forward_buf_count : 16; //[31:16] + uint32_t reserved_3a : 32; //[31:0] + uint32_t reserved_4a : 32; //[31:0] + uint32_t reserved_5a : 32; //[31:0] + uint32_t reserved_6a : 32; //[31:0] + uint32_t reserved_7a : 32; //[31:0] + uint32_t reserved_8a : 32; //[31:0] +}; + +/* + +struct uniform_reo_cmd_header cmd_header + + Consumer: REO + + Producer: SW + + + + Details for command execution tracking purposes. + +ac_timout_list + + Consumer: REO + + Producer: SW + + + + The AC_timeout list to be used for this command + + + +reserved_1 + + + +minimum_release_desc_count + + Consumer: REO + + Producer: SW + + + + The minimum number of link descriptors requested to be + released. If set to 0, only buffer release counts seems to + be important... When set to very high value, likely the + entire timeout list will be exhausted before this count is + reached or maybe this count will not get reached. REO + however will stop here as it can not do anything else. + + + + When both this field and field Minimum_forward_buf_count + are > 0, REO needs to meet both requirements. When both + entries are 0 (which should be a programming error), REO + does not need to do anything. + + + + Note that this includes counts of MPDU link Desc as well + as MSDU link Desc. Where the count of MSDU link Desc is not + known to REO it's approximated by deriving from MSDU count + + + +minimum_forward_buf_count + + Consumer: REO + + Producer: SW + + + + The minimum number of buffer descriptors requested to be + passed on to the REO destination rings. + + + + If set to 0, only descriptor release counts seems to be + important... + + + + When set to very high value, likely the entire timeout + list will be exhausted before this count is reached or maybe + this count will not get reached. REO however will stop here + as it can not do anything else. + + + + Note that REO does not know the exact buffer count. This + can be approximated by using the MSDU_COUNT + + + +reserved_3a + + + +reserved_4a + + + +reserved_5a + + + +reserved_6a + + + +reserved_7a + + + +reserved_8a + + +*/ + + + /* EXTERNAL REFERENCE : struct uniform_reo_cmd_header cmd_header */ + + +/* Description REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_CMD_NUMBER + + Consumer: REO/SW/DEBUG + + Producer: SW + + + + This number can be used by SW to track, identify and + link the created commands with the command statusses + + + + + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +/* Description REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_STATUS_REQUIRED + + Consumer: REO + + Producer: SW + + + + REO does not need to generate a status + TLV for the execution of this command + + REO shall generate a status TLV + for the execution of this command + + + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +/* Description REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_RESERVED_0A + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_FLUSH_TIMEOUT_LIST_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +/* Description REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST + + Consumer: REO + + Producer: SW + + + + The AC_timeout list to be used for this command + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_OFFSET 0x00000004 +#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_1_AC_TIMOUT_LIST_MASK 0x00000003 + +/* Description REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1 + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_OFFSET 0x00000004 +#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_LSB 2 +#define REO_FLUSH_TIMEOUT_LIST_1_RESERVED_1_MASK 0xfffffffc + +/* Description REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT + + Consumer: REO + + Producer: SW + + + + The minimum number of link descriptors requested to be + released. If set to 0, only buffer release counts seems to + be important... When set to very high value, likely the + entire timeout list will be exhausted before this count is + reached or maybe this count will not get reached. REO + however will stop here as it can not do anything else. + + + + When both this field and field Minimum_forward_buf_count + are > 0, REO needs to meet both requirements. When both + entries are 0 (which should be a programming error), REO + does not need to do anything. + + + + Note that this includes counts of MPDU link Desc as well + as MSDU link Desc. Where the count of MSDU link Desc is not + known to REO it's approximated by deriving from MSDU count + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_OFFSET 0x00000008 +#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_RELEASE_DESC_COUNT_MASK 0x0000ffff + +/* Description REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT + + Consumer: REO + + Producer: SW + + + + The minimum number of buffer descriptors requested to be + passed on to the REO destination rings. + + + + If set to 0, only descriptor release counts seems to be + important... + + + + When set to very high value, likely the entire timeout + list will be exhausted before this count is reached or maybe + this count will not get reached. REO however will stop here + as it can not do anything else. + + + + Note that REO does not know the exact buffer count. This + can be approximated by using the MSDU_COUNT + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_OFFSET 0x00000008 +#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_2_MINIMUM_FORWARD_BUF_COUNT_MASK 0xffff0000 + +/* Description REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_3_RESERVED_3A_MASK 0xffffffff + +/* Description REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_4_RESERVED_4A_MASK 0xffffffff + +/* Description REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_5_RESERVED_5A_MASK 0xffffffff + +/* Description REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_6_RESERVED_6A_MASK 0xffffffff + +/* Description REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_7_RESERVED_7A_MASK 0xffffffff + +/* Description REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_8_RESERVED_8A_MASK 0xffffffff + + +#endif // _REO_FLUSH_TIMEOUT_LIST_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/reo_flush_timeout_list_status.h b/drivers/staging/fw-api/hw/qca6750/v1/reo_flush_timeout_list_status.h new file mode 100644 index 000000000000..85c7cf527153 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/reo_flush_timeout_list_status.h @@ -0,0 +1,650 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ +#define _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct uniform_reo_status_header status_header; +// 2 error_detected[0], timout_list_empty[1], reserved_2a[31:2] +// 3 release_desc_count[15:0], forward_buf_count[31:16] +// 4 reserved_4a[31:0] +// 5 reserved_5a[31:0] +// 6 reserved_6a[31:0] +// 7 reserved_7a[31:0] +// 8 reserved_8a[31:0] +// 9 reserved_9a[31:0] +// 10 reserved_10a[31:0] +// 11 reserved_11a[31:0] +// 12 reserved_12a[31:0] +// 13 reserved_13a[31:0] +// 14 reserved_14a[31:0] +// 15 reserved_15a[31:0] +// 16 reserved_16a[31:0] +// 17 reserved_17a[31:0] +// 18 reserved_18a[31:0] +// 19 reserved_19a[31:0] +// 20 reserved_20a[31:0] +// 21 reserved_21a[31:0] +// 22 reserved_22a[31:0] +// 23 reserved_23a[31:0] +// 24 reserved_24a[27:0], looping_count[31:28] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_REO_FLUSH_TIMEOUT_LIST_STATUS 25 + +struct reo_flush_timeout_list_status { + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, //[0] + timout_list_empty : 1, //[1] + reserved_2a : 30; //[31:2] + uint32_t release_desc_count : 16, //[15:0] + forward_buf_count : 16; //[31:16] + uint32_t reserved_4a : 32; //[31:0] + uint32_t reserved_5a : 32; //[31:0] + uint32_t reserved_6a : 32; //[31:0] + uint32_t reserved_7a : 32; //[31:0] + uint32_t reserved_8a : 32; //[31:0] + uint32_t reserved_9a : 32; //[31:0] + uint32_t reserved_10a : 32; //[31:0] + uint32_t reserved_11a : 32; //[31:0] + uint32_t reserved_12a : 32; //[31:0] + uint32_t reserved_13a : 32; //[31:0] + uint32_t reserved_14a : 32; //[31:0] + uint32_t reserved_15a : 32; //[31:0] + uint32_t reserved_16a : 32; //[31:0] + uint32_t reserved_17a : 32; //[31:0] + uint32_t reserved_18a : 32; //[31:0] + uint32_t reserved_19a : 32; //[31:0] + uint32_t reserved_20a : 32; //[31:0] + uint32_t reserved_21a : 32; //[31:0] + uint32_t reserved_22a : 32; //[31:0] + uint32_t reserved_23a : 32; //[31:0] + uint32_t reserved_24a : 28, //[27:0] + looping_count : 4; //[31:28] +}; + +/* + +struct uniform_reo_status_header status_header + + Consumer: SW + + Producer: REO + + + + Details that can link this status with the original + command. It also contains info on how long REO took to + execute this command. + +error_detected + + 0: No error has been detected while executing this + command + + 1: command not properly executed and returned with an + error + + + + NOTE: Current no error is defined, but field is put in + place to avoid data structure changes in future... + +timout_list_empty + + When set, REO has depleted the timeout list and all + entries are gone. + + + +reserved_2a + + + +release_desc_count + + Consumer: REO + + Producer: SW + + + + The number of link descriptors released + + + +forward_buf_count + + Consumer: REO + + Producer: SW + + + + The number of buffers forwarded to the REO destination + rings + + + +reserved_4a + + + +reserved_5a + + + +reserved_6a + + + +reserved_7a + + + +reserved_8a + + + +reserved_9a + + + +reserved_10a + + + +reserved_11a + + + +reserved_12a + + + +reserved_13a + + + +reserved_14a + + + +reserved_15a + + + +reserved_16a + + + +reserved_17a + + + +reserved_18a + + + +reserved_19a + + + +reserved_20a + + + +reserved_21a + + + +reserved_22a + + + +reserved_23a + + + +reserved_24a + + + +looping_count + + A count value that indicates the number of times the + producer of entries into this Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ + + + /* EXTERNAL REFERENCE : struct uniform_reo_status_header status_header */ + + +/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER + + Consumer: SW , DEBUG + + Producer: REO + + + + The value in this field is equal to value of the + 'REO_CMD_Number' field the REO command + + + + This field helps to correlate the statuses with the REO + commands. + + + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME + + Consumer: DEBUG + + Producer: REO + + + + The amount of time REO took to excecute the command. + Note that this time does not include the duration of the + command waiting in the command ring, before the execution + started. + + + + In us. + + + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS + + Consumer: DEBUG + + Producer: REO + + + + Execution status of the command. + + + + Command has + successfully be executed + + Command could not be + executed as the queue or cache was blocked + + Command has encountered + problems when executing, like the queue descriptor not being + valid. None of the status fields in the entire STATUS TLV + are valid. + + Command is NOT executed + because one or more descriptors were blocked. This is SW + programming mistake. + + None of the status fields in the entire STATUS TLV are + valid. + + + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_RESERVED_0A + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_1_STATUS_HEADER_TIMESTAMP + + Timestamp at the moment that this status report is + written. + + + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED + + 0: No error has been detected while executing this + command + + 1: command not properly executed and returned with an + error + + + + NOTE: Current no error is defined, but field is put in + place to avoid data structure changes in future... +*/ +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_ERROR_DETECTED_MASK 0x00000001 + +/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY + + When set, REO has depleted the timeout list and all + entries are gone. + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_OFFSET 0x00000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_LSB 1 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_TIMOUT_LIST_EMPTY_MASK 0x00000002 + +/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_OFFSET 0x00000008 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_LSB 2 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_2_RESERVED_2A_MASK 0xfffffffc + +/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT + + Consumer: REO + + Producer: SW + + + + The number of link descriptors released + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_OFFSET 0x0000000c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_RELEASE_DESC_COUNT_MASK 0x0000ffff + +/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT + + Consumer: REO + + Producer: SW + + + + The number of buffers forwarded to the REO destination + rings + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_OFFSET 0x0000000c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_LSB 16 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_3_FORWARD_BUF_COUNT_MASK 0xffff0000 + +/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_4_RESERVED_4A_MASK 0xffffffff + +/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_5_RESERVED_5A_MASK 0xffffffff + +/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_6_RESERVED_6A_MASK 0xffffffff + +/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_7_RESERVED_7A_MASK 0xffffffff + +/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_8_RESERVED_8A_MASK 0xffffffff + +/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_OFFSET 0x00000024 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_9_RESERVED_9A_MASK 0xffffffff + +/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_OFFSET 0x00000028 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_10_RESERVED_10A_MASK 0xffffffff + +/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_OFFSET 0x0000002c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_11_RESERVED_11A_MASK 0xffffffff + +/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_OFFSET 0x00000030 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_12_RESERVED_12A_MASK 0xffffffff + +/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_OFFSET 0x00000034 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_13_RESERVED_13A_MASK 0xffffffff + +/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_OFFSET 0x00000038 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_14_RESERVED_14A_MASK 0xffffffff + +/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_OFFSET 0x0000003c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_15_RESERVED_15A_MASK 0xffffffff + +/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_OFFSET 0x00000040 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_16_RESERVED_16A_MASK 0xffffffff + +/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_OFFSET 0x00000044 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_17_RESERVED_17A_MASK 0xffffffff + +/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_OFFSET 0x00000048 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_18_RESERVED_18A_MASK 0xffffffff + +/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_OFFSET 0x0000004c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_19_RESERVED_19A_MASK 0xffffffff + +/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_OFFSET 0x00000050 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_20_RESERVED_20A_MASK 0xffffffff + +/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_OFFSET 0x00000054 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_21_RESERVED_21A_MASK 0xffffffff + +/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_OFFSET 0x00000058 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_22_RESERVED_22A_MASK 0xffffffff + +/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_OFFSET 0x0000005c +#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_23_RESERVED_23A_MASK 0xffffffff + +/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_OFFSET 0x00000060 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_LSB 0 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_RESERVED_24A_MASK 0x0fffffff + +/* Description REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT + + A count value that indicates the number of times the + producer of entries into this Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ +#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_LSB 28 +#define REO_FLUSH_TIMEOUT_LIST_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 + + +#endif // _REO_FLUSH_TIMEOUT_LIST_STATUS_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/reo_get_queue_stats.h b/drivers/staging/fw-api/hw/qca6750/v1/reo_get_queue_stats.h new file mode 100644 index 000000000000..a31df45be057 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/reo_get_queue_stats.h @@ -0,0 +1,355 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _REO_GET_QUEUE_STATS_H_ +#define _REO_GET_QUEUE_STATS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 struct uniform_reo_cmd_header cmd_header; +// 1 rx_reo_queue_desc_addr_31_0[31:0] +// 2 rx_reo_queue_desc_addr_39_32[7:0], clear_stats[8], reserved_2a[31:9] +// 3 reserved_3a[31:0] +// 4 reserved_4a[31:0] +// 5 reserved_5a[31:0] +// 6 reserved_6a[31:0] +// 7 reserved_7a[31:0] +// 8 reserved_8a[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS 9 + +struct reo_get_queue_stats { + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0] + uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0] + clear_stats : 1, //[8] + reserved_2a : 23; //[31:9] + uint32_t reserved_3a : 32; //[31:0] + uint32_t reserved_4a : 32; //[31:0] + uint32_t reserved_5a : 32; //[31:0] + uint32_t reserved_6a : 32; //[31:0] + uint32_t reserved_7a : 32; //[31:0] + uint32_t reserved_8a : 32; //[31:0] +}; + +/* + +struct uniform_reo_cmd_header cmd_header + + Consumer: REO + + Producer: SW + + + + Details for command execution tracking purposes. + +rx_reo_queue_desc_addr_31_0 + + Consumer: REO + + Producer: SW + + + + Address (lower 32 bits) of the REO queue descriptor + + + +rx_reo_queue_desc_addr_39_32 + + Consumer: REO + + Producer: SW + + + + Address (upper 8 bits) of the REO queue descriptor + + + +clear_stats + + Clear stat settings.... + + + + Do NOT clear the stats after + generating the status + + Clear the stats after + generating the status. + + + + The stats actually cleared are: + + Timeout_count + + Forward_due_to_bar_count + + Duplicate_count + + Frames_in_order_count + + BAR_received_count + + MPDU_Frames_processed_count + + MSDU_Frames_processed_count + + Total_processed_byte_count + + Late_receive_MPDU_count + + window_jump_2k + + Hole_count + + + +reserved_2a + + + +reserved_3a + + + +reserved_4a + + + +reserved_5a + + + +reserved_6a + + + +reserved_7a + + + +reserved_8a + + +*/ + + + /* EXTERNAL REFERENCE : struct uniform_reo_cmd_header cmd_header */ + + +/* Description REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_CMD_NUMBER + + Consumer: REO/SW/DEBUG + + Producer: SW + + + + This number can be used by SW to track, identify and + link the created commands with the command statusses + + + + + + +*/ +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +/* Description REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_STATUS_REQUIRED + + Consumer: REO + + Producer: SW + + + + REO does not need to generate a status + TLV for the execution of this command + + REO shall generate a status TLV + for the execution of this command + + + + +*/ +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +/* Description REO_GET_QUEUE_STATS_0_CMD_HEADER_RESERVED_0A + + +*/ +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_GET_QUEUE_STATS_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +/* Description REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0 + + Consumer: REO + + Producer: SW + + + + Address (lower 32 bits) of the REO queue descriptor + + +*/ +#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 +#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_GET_QUEUE_STATS_1_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32 + + Consumer: REO + + Producer: SW + + + + Address (upper 8 bits) of the REO queue descriptor + + +*/ +#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_GET_QUEUE_STATS_2_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +/* Description REO_GET_QUEUE_STATS_2_CLEAR_STATS + + Clear stat settings.... + + + + Do NOT clear the stats after + generating the status + + Clear the stats after + generating the status. + + + + The stats actually cleared are: + + Timeout_count + + Forward_due_to_bar_count + + Duplicate_count + + Frames_in_order_count + + BAR_received_count + + MPDU_Frames_processed_count + + MSDU_Frames_processed_count + + Total_processed_byte_count + + Late_receive_MPDU_count + + window_jump_2k + + Hole_count + + +*/ +#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_LSB 8 +#define REO_GET_QUEUE_STATS_2_CLEAR_STATS_MASK 0x00000100 + +/* Description REO_GET_QUEUE_STATS_2_RESERVED_2A + + +*/ +#define REO_GET_QUEUE_STATS_2_RESERVED_2A_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_2_RESERVED_2A_LSB 9 +#define REO_GET_QUEUE_STATS_2_RESERVED_2A_MASK 0xfffffe00 + +/* Description REO_GET_QUEUE_STATS_3_RESERVED_3A + + +*/ +#define REO_GET_QUEUE_STATS_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_GET_QUEUE_STATS_3_RESERVED_3A_LSB 0 +#define REO_GET_QUEUE_STATS_3_RESERVED_3A_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_4_RESERVED_4A + + +*/ +#define REO_GET_QUEUE_STATS_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_GET_QUEUE_STATS_4_RESERVED_4A_LSB 0 +#define REO_GET_QUEUE_STATS_4_RESERVED_4A_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_5_RESERVED_5A + + +*/ +#define REO_GET_QUEUE_STATS_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_GET_QUEUE_STATS_5_RESERVED_5A_LSB 0 +#define REO_GET_QUEUE_STATS_5_RESERVED_5A_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_6_RESERVED_6A + + +*/ +#define REO_GET_QUEUE_STATS_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_GET_QUEUE_STATS_6_RESERVED_6A_LSB 0 +#define REO_GET_QUEUE_STATS_6_RESERVED_6A_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_7_RESERVED_7A + + +*/ +#define REO_GET_QUEUE_STATS_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_GET_QUEUE_STATS_7_RESERVED_7A_LSB 0 +#define REO_GET_QUEUE_STATS_7_RESERVED_7A_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_8_RESERVED_8A + + +*/ +#define REO_GET_QUEUE_STATS_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_GET_QUEUE_STATS_8_RESERVED_8A_LSB 0 +#define REO_GET_QUEUE_STATS_8_RESERVED_8A_MASK 0xffffffff + + +#endif // _REO_GET_QUEUE_STATS_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/reo_get_queue_stats_status.h b/drivers/staging/fw-api/hw/qca6750/v1/reo_get_queue_stats_status.h new file mode 100644 index 000000000000..c45ae43d45f9 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/reo_get_queue_stats_status.h @@ -0,0 +1,972 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _REO_GET_QUEUE_STATS_STATUS_H_ +#define _REO_GET_QUEUE_STATS_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct uniform_reo_status_header status_header; +// 2 ssn[11:0], current_index[19:12], reserved_2[31:20] +// 3 pn_31_0[31:0] +// 4 pn_63_32[31:0] +// 5 pn_95_64[31:0] +// 6 pn_127_96[31:0] +// 7 last_rx_enqueue_timestamp[31:0] +// 8 last_rx_dequeue_timestamp[31:0] +// 9 rx_bitmap_31_0[31:0] +// 10 rx_bitmap_63_32[31:0] +// 11 rx_bitmap_95_64[31:0] +// 12 rx_bitmap_127_96[31:0] +// 13 rx_bitmap_159_128[31:0] +// 14 rx_bitmap_191_160[31:0] +// 15 rx_bitmap_223_192[31:0] +// 16 rx_bitmap_255_224[31:0] +// 17 current_mpdu_count[6:0], current_msdu_count[31:7] +// 18 reserved_18[3:0], timeout_count[9:4], forward_due_to_bar_count[15:10], duplicate_count[31:16] +// 19 frames_in_order_count[23:0], bar_received_count[31:24] +// 20 mpdu_frames_processed_count[31:0] +// 21 msdu_frames_processed_count[31:0] +// 22 total_processed_byte_count[31:0] +// 23 late_receive_mpdu_count[11:0], window_jump_2k[15:12], hole_count[31:16] +// 24 reserved_24a[27:0], looping_count[31:28] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_REO_GET_QUEUE_STATS_STATUS 25 + +struct reo_get_queue_stats_status { + struct uniform_reo_status_header status_header; + uint32_t ssn : 12, //[11:0] + current_index : 8, //[19:12] + reserved_2 : 12; //[31:20] + uint32_t pn_31_0 : 32; //[31:0] + uint32_t pn_63_32 : 32; //[31:0] + uint32_t pn_95_64 : 32; //[31:0] + uint32_t pn_127_96 : 32; //[31:0] + uint32_t last_rx_enqueue_timestamp : 32; //[31:0] + uint32_t last_rx_dequeue_timestamp : 32; //[31:0] + uint32_t rx_bitmap_31_0 : 32; //[31:0] + uint32_t rx_bitmap_63_32 : 32; //[31:0] + uint32_t rx_bitmap_95_64 : 32; //[31:0] + uint32_t rx_bitmap_127_96 : 32; //[31:0] + uint32_t rx_bitmap_159_128 : 32; //[31:0] + uint32_t rx_bitmap_191_160 : 32; //[31:0] + uint32_t rx_bitmap_223_192 : 32; //[31:0] + uint32_t rx_bitmap_255_224 : 32; //[31:0] + uint32_t current_mpdu_count : 7, //[6:0] + current_msdu_count : 25; //[31:7] + uint32_t reserved_18 : 4, //[3:0] + timeout_count : 6, //[9:4] + forward_due_to_bar_count : 6, //[15:10] + duplicate_count : 16; //[31:16] + uint32_t frames_in_order_count : 24, //[23:0] + bar_received_count : 8; //[31:24] + uint32_t mpdu_frames_processed_count : 32; //[31:0] + uint32_t msdu_frames_processed_count : 32; //[31:0] + uint32_t total_processed_byte_count : 32; //[31:0] + uint32_t late_receive_mpdu_count : 12, //[11:0] + window_jump_2k : 4, //[15:12] + hole_count : 16; //[31:16] + uint32_t reserved_24a : 28, //[27:0] + looping_count : 4; //[31:28] +}; + +/* + +struct uniform_reo_status_header status_header + + Consumer: SW + + Producer: REO + + + + Details that can link this status with the original + command. It also contains info on how long REO took to + execute this command. + +ssn + + Starting Sequence number of the session, this changes + whenever window moves. (can be filled by SW then maintained + by REO) + + + +current_index + + Points to last forwarded packet + + + +reserved_2 + + + +pn_31_0 + + + + +pn_63_32 + + Bits [63:32] of the PN number. + + + +pn_95_64 + + Bits [95:64] of the PN number. + + + +pn_127_96 + + Bits [127:96] of the PN number. + + + +last_rx_enqueue_timestamp + + Timestamp of arrival of the last MPDU for this queue + + + +last_rx_dequeue_timestamp + + Timestamp of forwarding an MPDU + + + + If the queue is empty when a frame gets received, this + time shall be initialized to the 'enqueue' timestamp + + + + Used for aging + + + +rx_bitmap_31_0 + + When a bit is set, the corresponding frame is currently + held in the re-order queue. + + The bitmap is Fully managed by HW. + + SW shall init this to 0, and then never ever change it + + + +rx_bitmap_63_32 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_95_64 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_127_96 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_159_128 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_191_160 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_223_192 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_255_224 + + See Rx_bitmap_31_0 description + + + +current_mpdu_count + + The number of MPDUs in the queue. + + + + + +current_msdu_count + + The number of MSDUs in the queue. + + + +reserved_18 + + + +timeout_count + + The number of times that REO started forwarding frames + even though there is a hole in the bitmap. Forwarding reason + is Timeout + + + + The counter saturates and freezes at 0x3F + + + + + +forward_due_to_bar_count + + The number of times that REO started forwarding frames + even though there is a hole in the bitmap. Forwarding reason + is reception of BAR frame. + + + + The counter saturates and freezes at 0x3F + + + + + +duplicate_count + + The number of duplicate frames that have been detected + + + +frames_in_order_count + + The number of frames that have been received in order + (without a hole that prevented them from being forwarded + immediately) + + + + This corresponds to the Reorder opcodes: + + 'FWDCUR' and 'FWD BUF' + + + + + +bar_received_count + + The number of times a BAR frame is received. + + + + This corresponds to the Reorder opcodes with 'DROP' + + + + The counter saturates and freezes at 0xFF + + + +mpdu_frames_processed_count + + The total number of MPDU frames that have been processed + by REO. This includes the duplicates. + + + + + +msdu_frames_processed_count + + The total number of MSDU frames that have been processed + by REO. This includes the duplicates. + + + + + +total_processed_byte_count + + An approximation of the number of bytes received for + this queue. + + + + In 64 byte units + + + +late_receive_mpdu_count + + The number of MPDUs received after the window had + already moved on. The 'late' sequence window is defined as + (Window SSN - 256) - (Window SSN - 1) + + + + This corresponds with Out of order detection in + duplicate detect FSM + + + + The counter saturates and freezes at 0xFFF + + + + + +window_jump_2k + + The number of times the window moved more then 2K + + + + The counter saturates and freezes at 0xF + + + + (Note: field name can not start with number: previous + 2k_window_jump) + + + + + +hole_count + + The number of times a hole was created in the receive + bitmap. + + + + This corresponds to the Reorder opcodes with 'QCUR' + + + + + +reserved_24a + + + +looping_count + + A count value that indicates the number of times the + producer of entries into this Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ + + + /* EXTERNAL REFERENCE : struct uniform_reo_status_header status_header */ + + +/* Description REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER + + Consumer: SW , DEBUG + + Producer: REO + + + + The value in this field is equal to value of the + 'REO_CMD_Number' field the REO command + + + + This field helps to correlate the statuses with the REO + commands. + + + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +/* Description REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME + + Consumer: DEBUG + + Producer: REO + + + + The amount of time REO took to excecute the command. + Note that this time does not include the duration of the + command waiting in the command ring, before the execution + started. + + + + In us. + + + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +/* Description REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS + + Consumer: DEBUG + + Producer: REO + + + + Execution status of the command. + + + + Command has + successfully be executed + + Command could not be + executed as the queue or cache was blocked + + Command has encountered + problems when executing, like the queue descriptor not being + valid. None of the status fields in the entire STATUS TLV + are valid. + + Command is NOT executed + because one or more descriptors were blocked. This is SW + programming mistake. + + None of the status fields in the entire STATUS TLV are + valid. + + + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +/* Description REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_RESERVED_0A + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_GET_QUEUE_STATS_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +/* Description REO_GET_QUEUE_STATS_STATUS_1_STATUS_HEADER_TIMESTAMP + + Timestamp at the moment that this status report is + written. + + + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define REO_GET_QUEUE_STATS_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_2_SSN + + Starting Sequence number of the session, this changes + whenever window moves. (can be filled by SW then maintained + by REO) + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_2_SSN_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_STATUS_2_SSN_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_2_SSN_MASK 0x00000fff + +/* Description REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX + + Points to last forwarded packet + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_LSB 12 +#define REO_GET_QUEUE_STATS_STATUS_2_CURRENT_INDEX_MASK 0x000ff000 + +/* Description REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2 + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_OFFSET 0x00000008 +#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_LSB 20 +#define REO_GET_QUEUE_STATS_STATUS_2_RESERVED_2_MASK 0xfff00000 + +/* Description REO_GET_QUEUE_STATS_STATUS_3_PN_31_0 + + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_OFFSET 0x0000000c +#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_3_PN_31_0_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_4_PN_63_32 + + Bits [63:32] of the PN number. + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_OFFSET 0x00000010 +#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_4_PN_63_32_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_5_PN_95_64 + + Bits [95:64] of the PN number. + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_OFFSET 0x00000014 +#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_5_PN_95_64_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_6_PN_127_96 + + Bits [127:96] of the PN number. + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_OFFSET 0x00000018 +#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_6_PN_127_96_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP + + Timestamp of arrival of the last MPDU for this queue + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x0000001c +#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_7_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP + + Timestamp of forwarding an MPDU + + + + If the queue is empty when a frame gets received, this + time shall be initialized to the 'enqueue' timestamp + + + + Used for aging + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000020 +#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_8_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0 + + When a bit is set, the corresponding frame is currently + held in the re-order queue. + + The bitmap is Fully managed by HW. + + SW shall init this to 0, and then never ever change it + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_OFFSET 0x00000024 +#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_9_RX_BITMAP_31_0_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32 + + See Rx_bitmap_31_0 description + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_OFFSET 0x00000028 +#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_10_RX_BITMAP_63_32_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64 + + See Rx_bitmap_31_0 description + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_OFFSET 0x0000002c +#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_11_RX_BITMAP_95_64_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96 + + See Rx_bitmap_31_0 description + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_OFFSET 0x00000030 +#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_12_RX_BITMAP_127_96_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128 + + See Rx_bitmap_31_0 description + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_OFFSET 0x00000034 +#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_13_RX_BITMAP_159_128_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160 + + See Rx_bitmap_31_0 description + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_OFFSET 0x00000038 +#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_14_RX_BITMAP_191_160_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192 + + See Rx_bitmap_31_0 description + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_OFFSET 0x0000003c +#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_15_RX_BITMAP_223_192_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224 + + See Rx_bitmap_31_0 description + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_OFFSET 0x00000040 +#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_16_RX_BITMAP_255_224_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT + + The number of MPDUs in the queue. + + + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_OFFSET 0x00000044 +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MPDU_COUNT_MASK 0x0000007f + +/* Description REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT + + The number of MSDUs in the queue. + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_OFFSET 0x00000044 +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_LSB 7 +#define REO_GET_QUEUE_STATS_STATUS_17_CURRENT_MSDU_COUNT_MASK 0xffffff80 + +/* Description REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18 + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_OFFSET 0x00000048 +#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_18_RESERVED_18_MASK 0x0000000f + +/* Description REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT + + The number of times that REO started forwarding frames + even though there is a hole in the bitmap. Forwarding reason + is Timeout + + + + The counter saturates and freezes at 0x3F + + + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_OFFSET 0x00000048 +#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_LSB 4 +#define REO_GET_QUEUE_STATS_STATUS_18_TIMEOUT_COUNT_MASK 0x000003f0 + +/* Description REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT + + The number of times that REO started forwarding frames + even though there is a hole in the bitmap. Forwarding reason + is reception of BAR frame. + + + + The counter saturates and freezes at 0x3F + + + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x00000048 +#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_LSB 10 +#define REO_GET_QUEUE_STATS_STATUS_18_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 + +/* Description REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT + + The number of duplicate frames that have been detected + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_OFFSET 0x00000048 +#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_LSB 16 +#define REO_GET_QUEUE_STATS_STATUS_18_DUPLICATE_COUNT_MASK 0xffff0000 + +/* Description REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT + + The number of frames that have been received in order + (without a hole that prevented them from being forwarded + immediately) + + + + This corresponds to the Reorder opcodes: + + 'FWDCUR' and 'FWD BUF' + + + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_OFFSET 0x0000004c +#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_19_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT + + The number of times a BAR frame is received. + + + + This corresponds to the Reorder opcodes with 'DROP' + + + + The counter saturates and freezes at 0xFF + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_OFFSET 0x0000004c +#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_LSB 24 +#define REO_GET_QUEUE_STATS_STATUS_19_BAR_RECEIVED_COUNT_MASK 0xff000000 + +/* Description REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT + + The total number of MPDU frames that have been processed + by REO. This includes the duplicates. + + + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000050 +#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_20_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT + + The total number of MSDU frames that have been processed + by REO. This includes the duplicates. + + + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000054 +#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_21_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT + + An approximation of the number of bytes received for + this queue. + + + + In 64 byte units + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x00000058 +#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_22_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT + + The number of MPDUs received after the window had + already moved on. The 'late' sequence window is defined as + (Window SSN - 256) - (Window SSN - 1) + + + + This corresponds with Out of order detection in + duplicate detect FSM + + + + The counter saturates and freezes at 0xFFF + + + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x0000005c +#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_23_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff + +/* Description REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K + + The number of times the window moved more then 2K + + + + The counter saturates and freezes at 0xF + + + + (Note: field name can not start with number: previous + 2k_window_jump) + + + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_OFFSET 0x0000005c +#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_LSB 12 +#define REO_GET_QUEUE_STATS_STATUS_23_WINDOW_JUMP_2K_MASK 0x0000f000 + +/* Description REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT + + The number of times a hole was created in the receive + bitmap. + + + + This corresponds to the Reorder opcodes with 'QCUR' + + + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_OFFSET 0x0000005c +#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_LSB 16 +#define REO_GET_QUEUE_STATS_STATUS_23_HOLE_COUNT_MASK 0xffff0000 + +/* Description REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_OFFSET 0x00000060 +#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_LSB 0 +#define REO_GET_QUEUE_STATS_STATUS_24_RESERVED_24A_MASK 0x0fffffff + +/* Description REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT + + A count value that indicates the number of times the + producer of entries into this Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ +#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 +#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_LSB 28 +#define REO_GET_QUEUE_STATS_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 + + +#endif // _REO_GET_QUEUE_STATS_STATUS_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/reo_reg_seq_hwiobase.h b/drivers/staging/fw-api/hw/qca6750/v1/reo_reg_seq_hwiobase.h new file mode 100644 index 000000000000..25446f6aeaa7 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/reo_reg_seq_hwiobase.h @@ -0,0 +1,40 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +/////////////////////////////////////////////////////////////////////////////////////////////// +// +// reo_reg_seq_hwiobase.h : automatically generated by Autoseq 3.8 11/13/2019 +// User Name:sanjdas +// +// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. +// +/////////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef __REO_REG_SEQ_BASE_H__ +#define __REO_REG_SEQ_BASE_H__ + +#ifdef SCALE_INCLUDES + #include "HALhwio.h" +#else + #include "msmhwio.h" +#endif + + +#endif + diff --git a/drivers/staging/fw-api/hw/qca6750/v1/reo_reg_seq_hwioreg.h b/drivers/staging/fw-api/hw/qca6750/v1/reo_reg_seq_hwioreg.h new file mode 100644 index 000000000000..2369c0a2ba7a --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/reo_reg_seq_hwioreg.h @@ -0,0 +1,10005 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/////////////////////////////////////////////////////////////////////////////////////////////// +// +// reo_reg_seq_hwioreg.h : automatically generated by Autoseq 3.8 11/13/2019 +// User Name:sanjdas +// +// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. +// +/////////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef __REO_REG_SEQ_REG_H__ +#define __REO_REG_SEQ_REG_H__ + +#include "seq_hwio.h" +#include "reo_reg_seq_hwiobase.h" +#ifdef SCALE_INCLUDES + #include "HALhwio.h" +#else + #include "msmhwio.h" +#endif + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Register Data for Block REO_REG +/////////////////////////////////////////////////////////////////////////////////////////////// + +//// Register REO_R0_GENERAL_ENABLE //// + +#define HWIO_REO_R0_GENERAL_ENABLE_ADDR(x) (x+0x00000000) +#define HWIO_REO_R0_GENERAL_ENABLE_PHYS(x) (x+0x00000000) +#define HWIO_REO_R0_GENERAL_ENABLE_RMSK 0xffffffff +#define HWIO_REO_R0_GENERAL_ENABLE_SHFT 0 +#define HWIO_REO_R0_GENERAL_ENABLE_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), HWIO_REO_R0_GENERAL_ENABLE_RMSK) +#define HWIO_REO_R0_GENERAL_ENABLE_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), mask) +#define HWIO_REO_R0_GENERAL_ENABLE_OUT(x, val) \ + out_dword( HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), val) +#define HWIO_REO_R0_GENERAL_ENABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GENERAL_ENABLE_ADDR(x), mask, val, HWIO_REO_R0_GENERAL_ENABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO1_RING_ENABLE_BMSK 0x80000000 +#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO1_RING_ENABLE_SHFT 0x1f + +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW6_RING_ENABLE_BMSK 0x40000000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW6_RING_ENABLE_SHFT 0x1e + +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW5_RING_ENABLE_BMSK 0x20000000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW5_RING_ENABLE_SHFT 0x1d + +#define HWIO_REO_R0_GENERAL_ENABLE_INVALIDATE_CACHE_FOR_ZERO_VLD_BMSK 0x10000000 +#define HWIO_REO_R0_GENERAL_ENABLE_INVALIDATE_CACHE_FOR_ZERO_VLD_SHFT 0x1c + +#define HWIO_REO_R0_GENERAL_ENABLE_STRUCT_SWAP_DELINK_BMSK 0x08000000 +#define HWIO_REO_R0_GENERAL_ENABLE_STRUCT_SWAP_DELINK_SHFT 0x1b + +#define HWIO_REO_R0_GENERAL_ENABLE_SOFT_REORDER_DEST_RING_BMSK 0x07800000 +#define HWIO_REO_R0_GENERAL_ENABLE_SOFT_REORDER_DEST_RING_SHFT 0x17 + +#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO_RING_ENABLE_BMSK 0x00400000 +#define HWIO_REO_R0_GENERAL_ENABLE_SW2REO_RING_ENABLE_SHFT 0x16 + +#define HWIO_REO_R0_GENERAL_ENABLE_REO_CMD_RING_ENABLE_BMSK 0x00200000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_CMD_RING_ENABLE_SHFT 0x15 + +#define HWIO_REO_R0_GENERAL_ENABLE_REO_STATUS_RING_ENABLE_BMSK 0x00100000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_STATUS_RING_ENABLE_SHFT 0x14 + +#define HWIO_REO_R0_GENERAL_ENABLE_REO_RELEASE_RING_ENABLE_BMSK 0x00080000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_RELEASE_RING_ENABLE_SHFT 0x13 + +#define HWIO_REO_R0_GENERAL_ENABLE_REO2TCL_RING_ENABLE_BMSK 0x00040000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2TCL_RING_ENABLE_SHFT 0x12 + +#define HWIO_REO_R0_GENERAL_ENABLE_REO2FW_RING_ENABLE_BMSK 0x00020000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2FW_RING_ENABLE_SHFT 0x11 + +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW4_RING_ENABLE_BMSK 0x00010000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW4_RING_ENABLE_SHFT 0x10 + +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW3_RING_ENABLE_BMSK 0x00008000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW3_RING_ENABLE_SHFT 0xf + +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW2_RING_ENABLE_BMSK 0x00004000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW2_RING_ENABLE_SHFT 0xe + +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW1_RING_ENABLE_BMSK 0x00002000 +#define HWIO_REO_R0_GENERAL_ENABLE_REO2SW1_RING_ENABLE_SHFT 0xd + +#define HWIO_REO_R0_GENERAL_ENABLE_WBM2REO_LINK_RING_ENABLE_BMSK 0x00001000 +#define HWIO_REO_R0_GENERAL_ENABLE_WBM2REO_LINK_RING_ENABLE_SHFT 0xc + +#define HWIO_REO_R0_GENERAL_ENABLE_RXDMA2REO_RING_ENABLE_BMSK 0x00000e00 +#define HWIO_REO_R0_GENERAL_ENABLE_RXDMA2REO_RING_ENABLE_SHFT 0x9 + +#define HWIO_REO_R0_GENERAL_ENABLE_GLOBAL_PN_CHK_BMSK 0x00000100 +#define HWIO_REO_R0_GENERAL_ENABLE_GLOBAL_PN_CHK_SHFT 0x8 + +#define HWIO_REO_R0_GENERAL_ENABLE_BAR_DEST_RING_BMSK 0x000000f0 +#define HWIO_REO_R0_GENERAL_ENABLE_BAR_DEST_RING_SHFT 0x4 + +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_BMSK 0x00000008 +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_FLUSH_ENABLE_SHFT 0x3 + +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_BMSK 0x00000004 +#define HWIO_REO_R0_GENERAL_ENABLE_AGING_LIST_ENABLE_SHFT 0x2 + +#define HWIO_REO_R0_GENERAL_ENABLE_REO_HWREORDER_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_HWREORDER_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_GENERAL_ENABLE_REO_ENABLE_BMSK 0x00000001 +#define HWIO_REO_R0_GENERAL_ENABLE_REO_ENABLE_SHFT 0x0 + +//// Register REO_R0_DESTINATION_RING_CTRL_IX_0 //// + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x) (x+0x00000004) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_PHYS(x) (x+0x00000004) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_SHFT 0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_RMSK) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), val) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_7_SHFT 0x1c + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_BMSK 0x0f000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_6_SHFT 0x18 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_BMSK 0x00f00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_5_SHFT 0x14 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_BMSK 0x000f0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_4_SHFT 0x10 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_BMSK 0x0000f000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_3_SHFT 0xc + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_BMSK 0x00000f00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_2_SHFT 0x8 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_BMSK 0x000000f0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_1_SHFT 0x4 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_BMSK 0x0000000f +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_0_DEST_RING_MAPPING_0_SHFT 0x0 + +//// Register REO_R0_DESTINATION_RING_CTRL_IX_1 //// + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x) (x+0x00000008) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_PHYS(x) (x+0x00000008) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_SHFT 0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_RMSK) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), val) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_15_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_15_SHFT 0x1c + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_14_BMSK 0x0f000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_14_SHFT 0x18 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_13_BMSK 0x00f00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_13_SHFT 0x14 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_12_BMSK 0x000f0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_12_SHFT 0x10 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_11_BMSK 0x0000f000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_11_SHFT 0xc + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_10_BMSK 0x00000f00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_10_SHFT 0x8 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_9_BMSK 0x000000f0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_9_SHFT 0x4 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_8_BMSK 0x0000000f +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_DEST_RING_MAPPING_8_SHFT 0x0 + +//// Register REO_R0_DESTINATION_RING_CTRL_IX_2 //// + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x) (x+0x0000000c) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_PHYS(x) (x+0x0000000c) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_SHFT 0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_RMSK) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), val) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_23_SHFT 0x1c + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_BMSK 0x0f000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_22_SHFT 0x18 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_BMSK 0x00f00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_21_SHFT 0x14 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_BMSK 0x000f0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_20_SHFT 0x10 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_BMSK 0x0000f000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_19_SHFT 0xc + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_BMSK 0x00000f00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_18_SHFT 0x8 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_BMSK 0x000000f0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_17_SHFT 0x4 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_BMSK 0x0000000f +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_DEST_RING_MAPPING_16_SHFT 0x0 + +//// Register REO_R0_DESTINATION_RING_CTRL_IX_3 //// + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x) (x+0x00000010) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_PHYS(x) (x+0x00000010) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_SHFT 0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_RMSK) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), val) +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_31_SHFT 0x1c + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_BMSK 0x0f000000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_30_SHFT 0x18 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_BMSK 0x00f00000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_29_SHFT 0x14 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_BMSK 0x000f0000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_28_SHFT 0x10 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_BMSK 0x0000f000 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_27_SHFT 0xc + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_BMSK 0x00000f00 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_26_SHFT 0x8 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_BMSK 0x000000f0 +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_25_SHFT 0x4 + +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_BMSK 0x0000000f +#define HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_DEST_RING_MAPPING_24_SHFT 0x0 + +//// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_0 //// + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x) (x+0x00000014) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_PHYS(x) (x+0x00000014) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_SHFT 0 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_RMSK) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), val) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_7_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_7_SHFT 0x1c + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_6_BMSK 0x0f000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_6_SHFT 0x18 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_5_BMSK 0x00f00000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_5_SHFT 0x14 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_4_BMSK 0x000f0000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_4_SHFT 0x10 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_3_BMSK 0x0000f000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_3_SHFT 0xc + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_2_BMSK 0x00000f00 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_2_SHFT 0x8 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_1_BMSK 0x000000f0 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_1_SHFT 0x4 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_BMSK 0x0000000f +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_0_DEST_RING_ALT_MAPPING_0_SHFT 0x0 + +//// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_1 //// + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x) (x+0x00000018) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_PHYS(x) (x+0x00000018) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_SHFT 0 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_RMSK) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), val) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_15_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_15_SHFT 0x1c + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_14_BMSK 0x0f000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_14_SHFT 0x18 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_13_BMSK 0x00f00000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_13_SHFT 0x14 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_12_BMSK 0x000f0000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_12_SHFT 0x10 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_11_BMSK 0x0000f000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_11_SHFT 0xc + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_10_BMSK 0x00000f00 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_10_SHFT 0x8 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_9_BMSK 0x000000f0 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_9_SHFT 0x4 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_8_BMSK 0x0000000f +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_1_DEST_RING_ALT_MAPPING_8_SHFT 0x0 + +//// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_2 //// + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x) (x+0x0000001c) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_PHYS(x) (x+0x0000001c) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_SHFT 0 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_RMSK) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), val) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_23_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_23_SHFT 0x1c + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_22_BMSK 0x0f000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_22_SHFT 0x18 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_21_BMSK 0x00f00000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_21_SHFT 0x14 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_20_BMSK 0x000f0000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_20_SHFT 0x10 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_19_BMSK 0x0000f000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_19_SHFT 0xc + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_18_BMSK 0x00000f00 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_18_SHFT 0x8 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_17_BMSK 0x000000f0 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_17_SHFT 0x4 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_16_BMSK 0x0000000f +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_2_DEST_RING_ALT_MAPPING_16_SHFT 0x0 + +//// Register REO_R0_DESTINATION_RING_ALT_CTRL_IX_3 //// + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x) (x+0x00000020) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_PHYS(x) (x+0x00000020) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_SHFT 0 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_RMSK) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), val) +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_ADDR(x), mask, val, HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_31_BMSK 0xf0000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_31_SHFT 0x1c + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_30_BMSK 0x0f000000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_30_SHFT 0x18 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_29_BMSK 0x00f00000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_29_SHFT 0x14 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_28_BMSK 0x000f0000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_28_SHFT 0x10 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_27_BMSK 0x0000f000 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_27_SHFT 0xc + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_26_BMSK 0x00000f00 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_26_SHFT 0x8 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_25_BMSK 0x000000f0 +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_25_SHFT 0x4 + +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_24_BMSK 0x0000000f +#define HWIO_REO_R0_DESTINATION_RING_ALT_CTRL_IX_3_DEST_RING_ALT_MAPPING_24_SHFT 0x0 + +//// Register REO_R0_TIMESTAMP //// + +#define HWIO_REO_R0_TIMESTAMP_ADDR(x) (x+0x00000024) +#define HWIO_REO_R0_TIMESTAMP_PHYS(x) (x+0x00000024) +#define HWIO_REO_R0_TIMESTAMP_RMSK 0xffffffff +#define HWIO_REO_R0_TIMESTAMP_SHFT 0 +#define HWIO_REO_R0_TIMESTAMP_IN(x) \ + in_dword_masked ( HWIO_REO_R0_TIMESTAMP_ADDR(x), HWIO_REO_R0_TIMESTAMP_RMSK) +#define HWIO_REO_R0_TIMESTAMP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_TIMESTAMP_ADDR(x), mask) +#define HWIO_REO_R0_TIMESTAMP_OUT(x, val) \ + out_dword( HWIO_REO_R0_TIMESTAMP_ADDR(x), val) +#define HWIO_REO_R0_TIMESTAMP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_TIMESTAMP_ADDR(x), mask, val, HWIO_REO_R0_TIMESTAMP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_TIMESTAMP_TIMESTAMP_BMSK 0xffffffff +#define HWIO_REO_R0_TIMESTAMP_TIMESTAMP_SHFT 0x0 + +//// Register REO_R0_ERROR_DESTINATION_MAPPING_IX_0 //// + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x) (x+0x00000028) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_PHYS(x) (x+0x00000028) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_SHFT 0 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_RMSK) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), val) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ADDR(x), mask, val, HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_BMSK 0xf0000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_7_SHFT 0x1c + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_BMSK 0x0f000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_6_SHFT 0x18 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_BMSK 0x00f00000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_5_SHFT 0x14 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_BMSK 0x000f0000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_4_SHFT 0x10 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_BMSK 0x0000f000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_3_SHFT 0xc + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_BMSK 0x00000f00 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_2_SHFT 0x8 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_BMSK 0x000000f0 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_1_SHFT 0x4 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_BMSK 0x0000000f +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_0_ERROR_DESTINATION_RING_0_SHFT 0x0 + +//// Register REO_R0_ERROR_DESTINATION_MAPPING_IX_1 //// + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x) (x+0x0000002c) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_PHYS(x) (x+0x0000002c) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_SHFT 0 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_RMSK) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), val) +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ADDR(x), mask, val, HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_OTHER_BMSK 0xf0000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_OTHER_SHFT 0x1c + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_BMSK 0x0f000000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_14_SHFT 0x18 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_BMSK 0x00f00000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_13_SHFT 0x14 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_BMSK 0x000f0000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_12_SHFT 0x10 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_BMSK 0x0000f000 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_11_SHFT 0xc + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_BMSK 0x00000f00 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_10_SHFT 0x8 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_9_BMSK 0x000000f0 +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_9_SHFT 0x4 + +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_8_BMSK 0x0000000f +#define HWIO_REO_R0_ERROR_DESTINATION_MAPPING_IX_1_ERROR_DESTINATION_RING_8_SHFT 0x0 + +//// Register REO_R0_IDLE_REQ_CTRL //// + +#define HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x) (x+0x00000030) +#define HWIO_REO_R0_IDLE_REQ_CTRL_PHYS(x) (x+0x00000030) +#define HWIO_REO_R0_IDLE_REQ_CTRL_RMSK 0x00000003 +#define HWIO_REO_R0_IDLE_REQ_CTRL_SHFT 0 +#define HWIO_REO_R0_IDLE_REQ_CTRL_IN(x) \ + in_dword_masked ( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), HWIO_REO_R0_IDLE_REQ_CTRL_RMSK) +#define HWIO_REO_R0_IDLE_REQ_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), mask) +#define HWIO_REO_R0_IDLE_REQ_CTRL_OUT(x, val) \ + out_dword( HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), val) +#define HWIO_REO_R0_IDLE_REQ_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_IDLE_REQ_CTRL_ADDR(x), mask, val, HWIO_REO_R0_IDLE_REQ_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_CACHE_BMSK 0x00000002 +#define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_CACHE_SHFT 0x1 + +#define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_AGE_LIST_BMSK 0x00000001 +#define HWIO_REO_R0_IDLE_REQ_CTRL_IDLE_REQ_FLUSH_AGE_LIST_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_BASE_LSB //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x) (x+0x00000034) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_PHYS(x) (x+0x00000034) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_BASE_MSB //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x) (x+0x00000038) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_PHYS(x) (x+0x00000038) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO0_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_ID //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x) (x+0x0000003c) +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_PHYS(x) (x+0x0000003c) +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_RMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_ID_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO0_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_STATUS //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x) (x+0x00000040) +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_PHYS(x) (x+0x00000040) +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_STATUS_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO0_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_MISC //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x) (x+0x00000044) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_PHYS(x) (x+0x00000044) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RMSK 0x003fffff +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MISC_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_RXDMA2REO0_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000050) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000050) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000054) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000054) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO0_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000064) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000064) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000068) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000068) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000006c) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000006c) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000070) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000070) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000074) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000074) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000078) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000078) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO0_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000007c) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000007c) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000080) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000080) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_MSI1_DATA //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x) (x+0x00000084) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_PHYS(x) (x+0x00000084) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_RXDMA2REO0_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000088) +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000088) +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_REO_R0_RXDMA2REO0_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_BASE_LSB //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x) (x+0x0000008c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_PHYS(x) (x+0x0000008c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_BASE_MSB //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x) (x+0x00000090) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_PHYS(x) (x+0x00000090) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_ID //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x) (x+0x00000094) +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_PHYS(x) (x+0x00000094) +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_RMSK 0x000000ff +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_ID_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_STATUS //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x) (x+0x00000098) +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_PHYS(x) (x+0x00000098) +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_MISC //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x) (x+0x0000009c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_PHYS(x) (x+0x0000009c) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RMSK 0x003fffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x) (x+0x000000a8) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_PHYS(x) (x+0x000000a8) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x) (x+0x000000ac) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_PHYS(x) (x+0x000000ac) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_WBM2REO_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000000bc) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000000bc) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000000c0) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000000c0) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000000c4) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000000c4) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000000c8) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000000c8) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000000cc) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000000cc) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000000d0) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000000d0) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000000d4) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000000d4) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000000d8) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000000d8) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_MSI1_DATA //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x) (x+0x000000dc) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_PHYS(x) (x+0x000000dc) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000000e0) +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000000e0) +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_REO_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_BASE_LSB //// + +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x) (x+0x000000e4) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_PHYS(x) (x+0x000000e4) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_BASE_MSB //// + +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x) (x+0x000000e8) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_PHYS(x) (x+0x000000e8) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_ID //// + +#define HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x) (x+0x000000ec) +#define HWIO_REO_R0_REO_CMD_RING_ID_PHYS(x) (x+0x000000ec) +#define HWIO_REO_R0_REO_CMD_RING_ID_RMSK 0x000000ff +#define HWIO_REO_R0_REO_CMD_RING_ID_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), HWIO_REO_R0_REO_CMD_RING_ID_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_REO_CMD_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_STATUS //// + +#define HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x) (x+0x000000f0) +#define HWIO_REO_R0_REO_CMD_RING_STATUS_PHYS(x) (x+0x000000f0) +#define HWIO_REO_R0_REO_CMD_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_STATUS_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_REO_CMD_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_MISC //// + +#define HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x) (x+0x000000f4) +#define HWIO_REO_R0_REO_CMD_RING_MISC_PHYS(x) (x+0x000000f4) +#define HWIO_REO_R0_REO_CMD_RING_MISC_RMSK 0x003fffff +#define HWIO_REO_R0_REO_CMD_RING_MISC_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MISC_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_REO_R0_REO_CMD_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_REO_CMD_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_REO_CMD_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_REO_CMD_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_REO_CMD_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_REO_CMD_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_REO_CMD_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_REO_CMD_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_REO_CMD_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_REO_CMD_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_REO_CMD_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_REO_CMD_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_TP_ADDR_LSB //// + +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000100) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000100) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_TP_ADDR_MSB //// + +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000104) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000104) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO_CMD_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000114) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000114) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000118) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000118) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS //// + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000011c) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000011c) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000120) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000120) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000124) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000124) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000128) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000128) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R0_REO_CMD_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000012c) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000012c) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000130) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000130) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_MSI1_DATA //// + +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x) (x+0x00000134) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_PHYS(x) (x+0x00000134) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO_CMD_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000138) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000138) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_REO_R0_REO_CMD_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_BASE_LSB //// + +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x) (x+0x0000013c) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_PHYS(x) (x+0x0000013c) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_BASE_MSB //// + +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x) (x+0x00000140) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_PHYS(x) (x+0x00000140) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_ID //// + +#define HWIO_REO_R0_SW2REO_RING_ID_ADDR(x) (x+0x00000144) +#define HWIO_REO_R0_SW2REO_RING_ID_PHYS(x) (x+0x00000144) +#define HWIO_REO_R0_SW2REO_RING_ID_RMSK 0x000000ff +#define HWIO_REO_R0_SW2REO_RING_ID_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), HWIO_REO_R0_SW2REO_RING_ID_RMSK) +#define HWIO_REO_R0_SW2REO_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_SW2REO_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_STATUS //// + +#define HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x) (x+0x00000148) +#define HWIO_REO_R0_SW2REO_RING_STATUS_PHYS(x) (x+0x00000148) +#define HWIO_REO_R0_SW2REO_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_STATUS_RMSK) +#define HWIO_REO_R0_SW2REO_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_SW2REO_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_MISC //// + +#define HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x) (x+0x0000014c) +#define HWIO_REO_R0_SW2REO_RING_MISC_PHYS(x) (x+0x0000014c) +#define HWIO_REO_R0_SW2REO_RING_MISC_RMSK 0x003fffff +#define HWIO_REO_R0_SW2REO_RING_MISC_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), HWIO_REO_R0_SW2REO_RING_MISC_RMSK) +#define HWIO_REO_R0_SW2REO_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_REO_R0_SW2REO_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_REO_R0_SW2REO_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_REO_R0_SW2REO_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_SW2REO_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_SW2REO_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_SW2REO_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_SW2REO_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_SW2REO_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_SW2REO_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_SW2REO_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_SW2REO_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_SW2REO_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_SW2REO_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_SW2REO_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_TP_ADDR_LSB //// + +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000158) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000158) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_TP_ADDR_MSB //// + +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x) (x+0x0000015c) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_PHYS(x) (x+0x0000015c) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_SW2REO_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x0000016c) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x0000016c) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000170) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000170) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_CONSUMER_INT_STATUS //// + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000174) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000174) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000178) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000178) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000017c) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000017c) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000180) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000180) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R0_SW2REO_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000184) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000184) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000188) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000188) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_SW2REO_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_MSI1_DATA //// + +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x) (x+0x0000018c) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_PHYS(x) (x+0x0000018c) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_SW2REO_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_SW2REO_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000190) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000190) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_REO_R0_SW2REO_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_SW2REO1_RING_BASE_LSB //// + +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x) (x+0x00000194) +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_PHYS(x) (x+0x00000194) +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_SW2REO1_RING_BASE_MSB //// + +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x) (x+0x00000198) +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_PHYS(x) (x+0x00000198) +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_SW2REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_SW2REO1_RING_ID //// + +#define HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x) (x+0x0000019c) +#define HWIO_REO_R0_SW2REO1_RING_ID_PHYS(x) (x+0x0000019c) +#define HWIO_REO_R0_SW2REO1_RING_ID_RMSK 0x000000ff +#define HWIO_REO_R0_SW2REO1_RING_ID_SHFT 0 +#define HWIO_REO_R0_SW2REO1_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x), HWIO_REO_R0_SW2REO1_RING_ID_RMSK) +#define HWIO_REO_R0_SW2REO1_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO1_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_SW2REO1_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_SW2REO1_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_SW2REO1_RING_STATUS //// + +#define HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x) (x+0x000001a0) +#define HWIO_REO_R0_SW2REO1_RING_STATUS_PHYS(x) (x+0x000001a0) +#define HWIO_REO_R0_SW2REO1_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_SW2REO1_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x), HWIO_REO_R0_SW2REO1_RING_STATUS_RMSK) +#define HWIO_REO_R0_SW2REO1_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO1_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_SW2REO1_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_SW2REO1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_SW2REO1_RING_MISC //// + +#define HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x) (x+0x000001a4) +#define HWIO_REO_R0_SW2REO1_RING_MISC_PHYS(x) (x+0x000001a4) +#define HWIO_REO_R0_SW2REO1_RING_MISC_RMSK 0x003fffff +#define HWIO_REO_R0_SW2REO1_RING_MISC_SHFT 0 +#define HWIO_REO_R0_SW2REO1_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x), HWIO_REO_R0_SW2REO1_RING_MISC_RMSK) +#define HWIO_REO_R0_SW2REO1_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO1_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_SW2REO1_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_REO_R0_SW2REO1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_SW2REO1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_SW2REO1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_SW2REO1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_SW2REO1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_SW2REO1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_SW2REO1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_SW2REO1_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_SW2REO1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_SW2REO1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_SW2REO1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_SW2REO1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_SW2REO1_RING_TP_ADDR_LSB //// + +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x) (x+0x000001b0) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_PHYS(x) (x+0x000001b0) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_SW2REO1_RING_TP_ADDR_MSB //// + +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x) (x+0x000001b4) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_PHYS(x) (x+0x000001b4) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_SW2REO1_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000001c4) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000001c4) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000001c8) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000001c8) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS //// + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000001cc) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000001cc) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000001d0) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000001d0) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000001d4) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000001d4) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000001d8) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000001d8) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R0_SW2REO1_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register REO_R0_SW2REO1_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000001dc) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000001dc) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_SW2REO1_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000001e0) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000001e0) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_SW2REO1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_SW2REO1_RING_MSI1_DATA //// + +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x) (x+0x000001e4) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_PHYS(x) (x+0x000001e4) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_SW2REO1_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000001e8) +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000001e8) +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_REO_R0_SW2REO1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_BASE_LSB //// + +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x) (x+0x000001ec) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_PHYS(x) (x+0x000001ec) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_BASE_MSB //// + +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x) (x+0x000001f0) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_PHYS(x) (x+0x000001f0) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RMSK 0x0fffffff +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_ID //// + +#define HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x) (x+0x000001f4) +#define HWIO_REO_R0_REO2SW1_RING_ID_PHYS(x) (x+0x000001f4) +#define HWIO_REO_R0_REO2SW1_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW1_RING_ID_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW1_RING_ID_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_REO2SW1_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW1_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW1_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_STATUS //// + +#define HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x) (x+0x000001f8) +#define HWIO_REO_R0_REO2SW1_RING_STATUS_PHYS(x) (x+0x000001f8) +#define HWIO_REO_R0_REO2SW1_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW1_RING_STATUS_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW1_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_MISC //// + +#define HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x) (x+0x000001fc) +#define HWIO_REO_R0_REO2SW1_RING_MISC_PHYS(x) (x+0x000001fc) +#define HWIO_REO_R0_REO2SW1_RING_MISC_RMSK 0x03ffffff +#define HWIO_REO_R0_REO2SW1_RING_MISC_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MISC_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_MISC_LOOP_CNT_BMSK 0x03c00000 +#define HWIO_REO_R0_REO2SW1_RING_MISC_LOOP_CNT_SHFT 0x16 + +#define HWIO_REO_R0_REO2SW1_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_REO2SW1_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_REO2SW1_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_REO2SW1_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_REO2SW1_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_REO2SW1_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_REO2SW1_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_REO2SW1_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_REO2SW1_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_REO2SW1_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_REO2SW1_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_REO2SW1_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_HP_ADDR_LSB //// + +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000200) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000200) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_HP_ADDR_MSB //// + +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000204) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000204) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW1_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP //// + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000210) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000210) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS //// + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000214) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000214) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000218) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000218) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff +#define HWIO_REO_R0_REO2SW1_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000234) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000234) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000238) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000238) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_MSI1_DATA //// + +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x) (x+0x0000023c) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_PHYS(x) (x+0x0000023c) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW1_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000240) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000240) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW1_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_BASE_LSB //// + +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x) (x+0x00000244) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_PHYS(x) (x+0x00000244) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_BASE_MSB //// + +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x) (x+0x00000248) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_PHYS(x) (x+0x00000248) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RMSK 0x0fffffff +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW2_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_ID //// + +#define HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x) (x+0x0000024c) +#define HWIO_REO_R0_REO2SW2_RING_ID_PHYS(x) (x+0x0000024c) +#define HWIO_REO_R0_REO2SW2_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW2_RING_ID_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW2_RING_ID_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_REO2SW2_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW2_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW2_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_STATUS //// + +#define HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x) (x+0x00000250) +#define HWIO_REO_R0_REO2SW2_RING_STATUS_PHYS(x) (x+0x00000250) +#define HWIO_REO_R0_REO2SW2_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW2_RING_STATUS_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW2_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_MISC //// + +#define HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x) (x+0x00000254) +#define HWIO_REO_R0_REO2SW2_RING_MISC_PHYS(x) (x+0x00000254) +#define HWIO_REO_R0_REO2SW2_RING_MISC_RMSK 0x03ffffff +#define HWIO_REO_R0_REO2SW2_RING_MISC_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MISC_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_MISC_LOOP_CNT_BMSK 0x03c00000 +#define HWIO_REO_R0_REO2SW2_RING_MISC_LOOP_CNT_SHFT 0x16 + +#define HWIO_REO_R0_REO2SW2_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_REO_R0_REO2SW2_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_REO2SW2_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_REO2SW2_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_REO2SW2_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_REO2SW2_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_REO2SW2_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_REO2SW2_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_REO2SW2_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_REO2SW2_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_REO2SW2_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_REO2SW2_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_REO2SW2_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_HP_ADDR_LSB //// + +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000258) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000258) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_HP_ADDR_MSB //// + +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000025c) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000025c) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW2_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP //// + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000268) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000268) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS //// + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000026c) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000026c) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000270) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000270) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff +#define HWIO_REO_R0_REO2SW2_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000028c) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000028c) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000290) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000290) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_MSI1_DATA //// + +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x) (x+0x00000294) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_PHYS(x) (x+0x00000294) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW2_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000298) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000298) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW2_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_BASE_LSB //// + +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x) (x+0x0000029c) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_PHYS(x) (x+0x0000029c) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_BASE_MSB //// + +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x) (x+0x000002a0) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_PHYS(x) (x+0x000002a0) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RMSK 0x0fffffff +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW3_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_ID //// + +#define HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x) (x+0x000002a4) +#define HWIO_REO_R0_REO2SW3_RING_ID_PHYS(x) (x+0x000002a4) +#define HWIO_REO_R0_REO2SW3_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW3_RING_ID_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW3_RING_ID_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_REO2SW3_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW3_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW3_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_STATUS //// + +#define HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x) (x+0x000002a8) +#define HWIO_REO_R0_REO2SW3_RING_STATUS_PHYS(x) (x+0x000002a8) +#define HWIO_REO_R0_REO2SW3_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW3_RING_STATUS_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW3_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_MISC //// + +#define HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x) (x+0x000002ac) +#define HWIO_REO_R0_REO2SW3_RING_MISC_PHYS(x) (x+0x000002ac) +#define HWIO_REO_R0_REO2SW3_RING_MISC_RMSK 0x03ffffff +#define HWIO_REO_R0_REO2SW3_RING_MISC_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MISC_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_MISC_LOOP_CNT_BMSK 0x03c00000 +#define HWIO_REO_R0_REO2SW3_RING_MISC_LOOP_CNT_SHFT 0x16 + +#define HWIO_REO_R0_REO2SW3_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_REO_R0_REO2SW3_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_REO2SW3_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_REO2SW3_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_REO2SW3_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_REO2SW3_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_REO2SW3_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_REO2SW3_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_REO2SW3_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_REO2SW3_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_REO2SW3_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_REO2SW3_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_REO2SW3_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_HP_ADDR_LSB //// + +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x) (x+0x000002b0) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_PHYS(x) (x+0x000002b0) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_HP_ADDR_MSB //// + +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x) (x+0x000002b4) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_PHYS(x) (x+0x000002b4) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW3_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP //// + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000002c0) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000002c0) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS //// + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000002c4) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000002c4) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000002c8) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000002c8) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff +#define HWIO_REO_R0_REO2SW3_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000002e4) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000002e4) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000002e8) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000002e8) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_MSI1_DATA //// + +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x) (x+0x000002ec) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_PHYS(x) (x+0x000002ec) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW3_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000002f0) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000002f0) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW3_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_BASE_LSB //// + +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x) (x+0x000002f4) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_PHYS(x) (x+0x000002f4) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_BASE_MSB //// + +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x) (x+0x000002f8) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_PHYS(x) (x+0x000002f8) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RMSK 0x0fffffff +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW4_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_ID //// + +#define HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x) (x+0x000002fc) +#define HWIO_REO_R0_REO2SW4_RING_ID_PHYS(x) (x+0x000002fc) +#define HWIO_REO_R0_REO2SW4_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW4_RING_ID_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW4_RING_ID_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_REO2SW4_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW4_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW4_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_STATUS //// + +#define HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x) (x+0x00000300) +#define HWIO_REO_R0_REO2SW4_RING_STATUS_PHYS(x) (x+0x00000300) +#define HWIO_REO_R0_REO2SW4_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW4_RING_STATUS_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW4_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_MISC //// + +#define HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x) (x+0x00000304) +#define HWIO_REO_R0_REO2SW4_RING_MISC_PHYS(x) (x+0x00000304) +#define HWIO_REO_R0_REO2SW4_RING_MISC_RMSK 0x03ffffff +#define HWIO_REO_R0_REO2SW4_RING_MISC_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MISC_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_MISC_LOOP_CNT_BMSK 0x03c00000 +#define HWIO_REO_R0_REO2SW4_RING_MISC_LOOP_CNT_SHFT 0x16 + +#define HWIO_REO_R0_REO2SW4_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_REO_R0_REO2SW4_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_REO2SW4_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_REO2SW4_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_REO2SW4_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_REO2SW4_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_REO2SW4_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_REO2SW4_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_REO2SW4_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_REO2SW4_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_REO2SW4_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_REO2SW4_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_REO2SW4_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_HP_ADDR_LSB //// + +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000308) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000308) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_HP_ADDR_MSB //// + +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000030c) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000030c) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW4_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP //// + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000318) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000318) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS //// + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000031c) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000031c) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000320) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000320) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff +#define HWIO_REO_R0_REO2SW4_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000033c) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000033c) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000340) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000340) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_MSI1_DATA //// + +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x) (x+0x00000344) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_PHYS(x) (x+0x00000344) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW4_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000348) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000348) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW4_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW5_RING_BASE_LSB //// + +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_ADDR(x) (x+0x0000034c) +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_PHYS(x) (x+0x0000034c) +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW5_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW5_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW5_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2SW5_RING_BASE_MSB //// + +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_ADDR(x) (x+0x00000350) +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_PHYS(x) (x+0x00000350) +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_RMSK 0x0fffffff +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW5_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW5_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW5_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW5_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2SW5_RING_ID //// + +#define HWIO_REO_R0_REO2SW5_RING_ID_ADDR(x) (x+0x00000354) +#define HWIO_REO_R0_REO2SW5_RING_ID_PHYS(x) (x+0x00000354) +#define HWIO_REO_R0_REO2SW5_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW5_RING_ID_SHFT 0 +#define HWIO_REO_R0_REO2SW5_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW5_RING_ID_RMSK) +#define HWIO_REO_R0_REO2SW5_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW5_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW5_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_REO2SW5_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW5_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW5_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_REO2SW5_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW5_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW5_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_REO2SW5_RING_STATUS //// + +#define HWIO_REO_R0_REO2SW5_RING_STATUS_ADDR(x) (x+0x00000358) +#define HWIO_REO_R0_REO2SW5_RING_STATUS_PHYS(x) (x+0x00000358) +#define HWIO_REO_R0_REO2SW5_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2SW5_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW5_RING_STATUS_RMSK) +#define HWIO_REO_R0_REO2SW5_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW5_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW5_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2SW5_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW5_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW5_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW5_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW5_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW5_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_REO2SW5_RING_MISC //// + +#define HWIO_REO_R0_REO2SW5_RING_MISC_ADDR(x) (x+0x0000035c) +#define HWIO_REO_R0_REO2SW5_RING_MISC_PHYS(x) (x+0x0000035c) +#define HWIO_REO_R0_REO2SW5_RING_MISC_RMSK 0x03ffffff +#define HWIO_REO_R0_REO2SW5_RING_MISC_SHFT 0 +#define HWIO_REO_R0_REO2SW5_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW5_RING_MISC_RMSK) +#define HWIO_REO_R0_REO2SW5_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW5_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW5_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_REO2SW5_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW5_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW5_RING_MISC_LOOP_CNT_BMSK 0x03c00000 +#define HWIO_REO_R0_REO2SW5_RING_MISC_LOOP_CNT_SHFT 0x16 + +#define HWIO_REO_R0_REO2SW5_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_REO_R0_REO2SW5_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_REO2SW5_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_REO2SW5_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_REO2SW5_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_REO2SW5_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_REO2SW5_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_REO2SW5_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_REO2SW5_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_REO2SW5_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_REO2SW5_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_REO2SW5_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_REO2SW5_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_REO2SW5_RING_HP_ADDR_LSB //// + +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000360) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000360) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2SW5_RING_HP_ADDR_MSB //// + +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000364) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000364) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW5_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP //// + +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000370) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000370) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS //// + +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000374) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000374) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000378) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000378) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff +#define HWIO_REO_R0_REO2SW5_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register REO_R0_REO2SW5_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000394) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000394) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2SW5_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000398) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000398) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW5_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2SW5_RING_MSI1_DATA //// + +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_ADDR(x) (x+0x0000039c) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_PHYS(x) (x+0x0000039c) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW5_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000003a0) +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000003a0) +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW5_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW6_RING_BASE_LSB //// + +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_ADDR(x) (x+0x000003a4) +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_PHYS(x) (x+0x000003a4) +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW6_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW6_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW6_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2SW6_RING_BASE_MSB //// + +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_ADDR(x) (x+0x000003a8) +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_PHYS(x) (x+0x000003a8) +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_RMSK 0x0fffffff +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW6_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW6_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW6_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW6_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2SW6_RING_ID //// + +#define HWIO_REO_R0_REO2SW6_RING_ID_ADDR(x) (x+0x000003ac) +#define HWIO_REO_R0_REO2SW6_RING_ID_PHYS(x) (x+0x000003ac) +#define HWIO_REO_R0_REO2SW6_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW6_RING_ID_SHFT 0 +#define HWIO_REO_R0_REO2SW6_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_ID_ADDR(x), HWIO_REO_R0_REO2SW6_RING_ID_RMSK) +#define HWIO_REO_R0_REO2SW6_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW6_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW6_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_REO2SW6_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2SW6_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW6_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_REO2SW6_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW6_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW6_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_REO2SW6_RING_STATUS //// + +#define HWIO_REO_R0_REO2SW6_RING_STATUS_ADDR(x) (x+0x000003b0) +#define HWIO_REO_R0_REO2SW6_RING_STATUS_PHYS(x) (x+0x000003b0) +#define HWIO_REO_R0_REO2SW6_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2SW6_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2SW6_RING_STATUS_RMSK) +#define HWIO_REO_R0_REO2SW6_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW6_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW6_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2SW6_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW6_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW6_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW6_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW6_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW6_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_REO2SW6_RING_MISC //// + +#define HWIO_REO_R0_REO2SW6_RING_MISC_ADDR(x) (x+0x000003b4) +#define HWIO_REO_R0_REO2SW6_RING_MISC_PHYS(x) (x+0x000003b4) +#define HWIO_REO_R0_REO2SW6_RING_MISC_RMSK 0x03ffffff +#define HWIO_REO_R0_REO2SW6_RING_MISC_SHFT 0 +#define HWIO_REO_R0_REO2SW6_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_MISC_ADDR(x), HWIO_REO_R0_REO2SW6_RING_MISC_RMSK) +#define HWIO_REO_R0_REO2SW6_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW6_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW6_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_REO2SW6_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2SW6_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW6_RING_MISC_LOOP_CNT_BMSK 0x03c00000 +#define HWIO_REO_R0_REO2SW6_RING_MISC_LOOP_CNT_SHFT 0x16 + +#define HWIO_REO_R0_REO2SW6_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_REO_R0_REO2SW6_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_REO2SW6_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_REO2SW6_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_REO2SW6_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_REO2SW6_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_REO2SW6_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_REO2SW6_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_REO2SW6_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_REO2SW6_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_REO2SW6_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_REO2SW6_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_REO2SW6_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_REO2SW6_RING_HP_ADDR_LSB //// + +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_ADDR(x) (x+0x000003b8) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_PHYS(x) (x+0x000003b8) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2SW6_RING_HP_ADDR_MSB //// + +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_ADDR(x) (x+0x000003bc) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_PHYS(x) (x+0x000003bc) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW6_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP //// + +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000003c8) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000003c8) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS //// + +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000003cc) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000003cc) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000003d0) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000003d0) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff +#define HWIO_REO_R0_REO2SW6_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register REO_R0_REO2SW6_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000003ec) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000003ec) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2SW6_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000003f0) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000003f0) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_REO2SW6_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2SW6_RING_MSI1_DATA //// + +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_ADDR(x) (x+0x000003f4) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_PHYS(x) (x+0x000003f4) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2SW6_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000003f8) +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000003f8) +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2SW6_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_BASE_LSB //// + +#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x) (x+0x000003fc) +#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_PHYS(x) (x+0x000003fc) +#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_BASE_MSB //// + +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x) (x+0x00000400) +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_PHYS(x) (x+0x00000400) +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RMSK 0x0fffffff +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_ID //// + +#define HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x) (x+0x00000404) +#define HWIO_REO_R0_REO2TCL_RING_ID_PHYS(x) (x+0x00000404) +#define HWIO_REO_R0_REO2TCL_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2TCL_RING_ID_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), HWIO_REO_R0_REO2TCL_RING_ID_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_REO2TCL_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_REO2TCL_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_REO2TCL_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_STATUS //// + +#define HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x) (x+0x00000408) +#define HWIO_REO_R0_REO2TCL_RING_STATUS_PHYS(x) (x+0x00000408) +#define HWIO_REO_R0_REO2TCL_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2TCL_RING_STATUS_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2TCL_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_MISC //// + +#define HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x) (x+0x0000040c) +#define HWIO_REO_R0_REO2TCL_RING_MISC_PHYS(x) (x+0x0000040c) +#define HWIO_REO_R0_REO2TCL_RING_MISC_RMSK 0x03ffffff +#define HWIO_REO_R0_REO2TCL_RING_MISC_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MISC_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_MISC_LOOP_CNT_BMSK 0x03c00000 +#define HWIO_REO_R0_REO2TCL_RING_MISC_LOOP_CNT_SHFT 0x16 + +#define HWIO_REO_R0_REO2TCL_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_REO_R0_REO2TCL_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_REO_R0_REO2TCL_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_REO_R0_REO2TCL_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_REO2TCL_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_REO2TCL_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_REO2TCL_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_REO2TCL_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_REO2TCL_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_REO2TCL_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_REO2TCL_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_REO2TCL_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_REO2TCL_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_REO2TCL_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_REO2TCL_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_HP_ADDR_LSB //// + +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000410) +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000410) +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_HP_ADDR_MSB //// + +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000414) +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000414) +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2TCL_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP //// + +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000420) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000420) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS //// + +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000424) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000424) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000428) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000428) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff +#define HWIO_REO_R0_REO2TCL_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000444) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000444) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000448) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000448) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_REO2TCL_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_MSI1_DATA //// + +#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x) (x+0x0000044c) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_PHYS(x) (x+0x0000044c) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2TCL_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000450) +#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000450) +#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2TCL_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_BASE_LSB //// + +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x) (x+0x00000454) +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_PHYS(x) (x+0x00000454) +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_BASE_MSB //// + +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x) (x+0x00000458) +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_PHYS(x) (x+0x00000458) +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RMSK 0x0fffffff +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2FW_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_ID //// + +#define HWIO_REO_R0_REO2FW_RING_ID_ADDR(x) (x+0x0000045c) +#define HWIO_REO_R0_REO2FW_RING_ID_PHYS(x) (x+0x0000045c) +#define HWIO_REO_R0_REO2FW_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2FW_RING_ID_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), HWIO_REO_R0_REO2FW_RING_ID_RMSK) +#define HWIO_REO_R0_REO2FW_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_REO2FW_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_REO2FW_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_REO2FW_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_STATUS //// + +#define HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x) (x+0x00000460) +#define HWIO_REO_R0_REO2FW_RING_STATUS_PHYS(x) (x+0x00000460) +#define HWIO_REO_R0_REO2FW_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), HWIO_REO_R0_REO2FW_RING_STATUS_RMSK) +#define HWIO_REO_R0_REO2FW_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2FW_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_MISC //// + +#define HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x) (x+0x00000464) +#define HWIO_REO_R0_REO2FW_RING_MISC_PHYS(x) (x+0x00000464) +#define HWIO_REO_R0_REO2FW_RING_MISC_RMSK 0x03ffffff +#define HWIO_REO_R0_REO2FW_RING_MISC_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), HWIO_REO_R0_REO2FW_RING_MISC_RMSK) +#define HWIO_REO_R0_REO2FW_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_MISC_LOOP_CNT_BMSK 0x03c00000 +#define HWIO_REO_R0_REO2FW_RING_MISC_LOOP_CNT_SHFT 0x16 + +#define HWIO_REO_R0_REO2FW_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_REO_R0_REO2FW_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_REO_R0_REO2FW_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_REO_R0_REO2FW_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_REO2FW_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_REO2FW_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_REO2FW_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_REO2FW_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_REO2FW_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_REO2FW_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_REO2FW_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_REO2FW_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_REO2FW_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_REO2FW_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_REO2FW_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_HP_ADDR_LSB //// + +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000468) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000468) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_HP_ADDR_MSB //// + +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000046c) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000046c) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO2FW_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_PRODUCER_INT_SETUP //// + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000478) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000478) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_PRODUCER_INT_STATUS //// + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000047c) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000047c) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000480) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000480) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff +#define HWIO_REO_R0_REO2FW_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000049c) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000049c) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000004a0) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000004a0) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_REO2FW_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_MSI1_DATA //// + +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x) (x+0x000004a4) +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_PHYS(x) (x+0x000004a4) +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO2FW_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO2FW_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_REO2FW_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000004a8) +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000004a8) +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_REO_R0_REO2FW_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_BASE_LSB //// + +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x000004ac) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x000004ac) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_BASE_MSB //// + +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x000004b0) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x000004b0) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_ID //// + +#define HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x) (x+0x000004b4) +#define HWIO_REO_R0_REO_RELEASE_RING_ID_PHYS(x) (x+0x000004b4) +#define HWIO_REO_R0_REO_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_REO_RELEASE_RING_ID_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_ID_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_REO_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_STATUS //// + +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x) (x+0x000004b8) +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_PHYS(x) (x+0x000004b8) +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_STATUS_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_MISC //// + +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x) (x+0x000004bc) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_PHYS(x) (x+0x000004bc) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_RMSK 0x03ffffff +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_MISC_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x03c00000 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOP_CNT_SHFT 0x16 + +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_HP_ADDR_LSB //// + +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x) (x+0x000004c0) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_PHYS(x) (x+0x000004c0) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_HP_ADDR_MSB //// + +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x) (x+0x000004c4) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_PHYS(x) (x+0x000004c4) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP //// + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000004d0) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000004d0) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS //// + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000004d4) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000004d4) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000004d8) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000004d8) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff +#define HWIO_REO_R0_REO_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000004f4) +#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000004f4) +#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000004f8) +#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000004f8) +#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_MSI1_DATA //// + +#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x000004fc) +#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x000004fc) +#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000500) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000500) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_REO_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_BASE_LSB //// + +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x) (x+0x00000504) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_PHYS(x) (x+0x00000504) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_BASE_MSB //// + +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x) (x+0x00000508) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_PHYS(x) (x+0x00000508) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_ID //// + +#define HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x) (x+0x0000050c) +#define HWIO_REO_R0_REO_STATUS_RING_ID_PHYS(x) (x+0x0000050c) +#define HWIO_REO_R0_REO_STATUS_RING_ID_RMSK 0x0000ffff +#define HWIO_REO_R0_REO_STATUS_RING_ID_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_ID_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_ID_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_ID_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_ID_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_REO_R0_REO_STATUS_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_REO_R0_REO_STATUS_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_REO_R0_REO_STATUS_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_STATUS //// + +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x) (x+0x00000510) +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_PHYS(x) (x+0x00000510) +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_STATUS_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_REO_R0_REO_STATUS_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_MISC //// + +#define HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x) (x+0x00000514) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_PHYS(x) (x+0x00000514) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_RMSK 0x03ffffff +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MISC_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MISC_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOP_CNT_BMSK 0x03c00000 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOP_CNT_SHFT 0x16 + +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_REO_R0_REO_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_REO_R0_REO_STATUS_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_REO_R0_REO_STATUS_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_REO_R0_REO_STATUS_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_REO_STATUS_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_HP_ADDR_LSB //// + +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000518) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000518) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_HP_ADDR_MSB //// + +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000051c) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000051c) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_REO_R0_REO_STATUS_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP //// + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000528) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000528) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS //// + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000052c) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000052c) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000530) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000530) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff +#define HWIO_REO_R0_REO_STATUS_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_MSI1_BASE_LSB //// + +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000054c) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000054c) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_MSI1_BASE_MSB //// + +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000550) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000550) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_MSI1_DATA //// + +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x) (x+0x00000554) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_PHYS(x) (x+0x00000554) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_REO_STATUS_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET //// + +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000558) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000558) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_REO_R0_REO_STATUS_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register REO_R0_WATCHDOG_TIMEOUT //// + +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x) (x+0x0000055c) +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_PHYS(x) (x+0x0000055c) +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_RMSK 0x00003fff +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_SHFT 0 +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_IN(x) \ + in_dword_masked ( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), HWIO_REO_R0_WATCHDOG_TIMEOUT_RMSK) +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), mask) +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_OUT(x, val) \ + out_dword( HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), val) +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_WATCHDOG_TIMEOUT_ADDR(x), mask, val, HWIO_REO_R0_WATCHDOG_TIMEOUT_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_RESOLUTION_UNITS_BMSK 0x00003000 +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_RESOLUTION_UNITS_SHFT 0xc + +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_SRNG_TIMEOUT_BMSK 0x00000fff +#define HWIO_REO_R0_WATCHDOG_TIMEOUT_SRNG_TIMEOUT_SHFT 0x0 + +//// Register REO_R0_INTERRUPT_DATA_CAPTURE_IX_0 //// + +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x) (x+0x00000560) +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_PHYS(x) (x+0x00000560) +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_SHFT 0 +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_RMSK) +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), val) +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ADDR(x), mask, val, HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ERROR_DATA_BMSK 0xffffffff +#define HWIO_REO_R0_INTERRUPT_DATA_CAPTURE_IX_0_ERROR_DATA_SHFT 0x0 + +//// Register REO_R0_AGING_THRESHOLD_IX_0 //// + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x) (x+0x00000564) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_PHYS(x) (x+0x00000564) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_SHFT 0 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_0_RMSK) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), val) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_AGING_THRESHOLD_AC0_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_0_AGING_THRESHOLD_AC0_SHFT 0x0 + +//// Register REO_R0_AGING_THRESHOLD_IX_1 //// + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x) (x+0x00000568) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_PHYS(x) (x+0x00000568) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_SHFT 0 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_1_RMSK) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), val) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_AGING_THRESHOLD_AC1_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_1_AGING_THRESHOLD_AC1_SHFT 0x0 + +//// Register REO_R0_AGING_THRESHOLD_IX_2 //// + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x) (x+0x0000056c) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_PHYS(x) (x+0x0000056c) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_SHFT 0 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_2_RMSK) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), val) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_AGING_THRESHOLD_AC2_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_2_AGING_THRESHOLD_AC2_SHFT 0x0 + +//// Register REO_R0_AGING_THRESHOLD_IX_3 //// + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x) (x+0x00000570) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_PHYS(x) (x+0x00000570) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_SHFT 0 +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), HWIO_REO_R0_AGING_THRESHOLD_IX_3_RMSK) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), val) +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_THRESHOLD_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_AGING_THRESHOLD_AC3_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_THRESHOLD_IX_3_AGING_THRESHOLD_AC3_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_0 //// + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x) (x+0x00000574) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_PHYS(x) (x+0x00000574) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_RMSK) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_0_AGING_HEADPTR_LO_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_0 //// + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x) (x+0x00000578) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_PHYS(x) (x+0x00000578) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_RMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_RMSK) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_0_AGING_HEADPTR_HI_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_0 //// + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x) (x+0x0000057c) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_PHYS(x) (x+0x0000057c) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_RMSK) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_0_AGING_TAILPTR_LO_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_0 //// + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x) (x+0x00000580) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_PHYS(x) (x+0x00000580) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_RMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_RMSK) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_0_AGING_TAILPTR_HI_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_1 //// + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x) (x+0x00000584) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_PHYS(x) (x+0x00000584) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_RMSK) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_1_AGING_HEADPTR_LO_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_1 //// + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x) (x+0x00000588) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_PHYS(x) (x+0x00000588) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_RMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_RMSK) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_1_AGING_HEADPTR_HI_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_1 //// + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x) (x+0x0000058c) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_PHYS(x) (x+0x0000058c) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_RMSK) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_1_AGING_TAILPTR_LO_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_1 //// + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x) (x+0x00000590) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_PHYS(x) (x+0x00000590) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_RMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_RMSK) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_1_AGING_TAILPTR_HI_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_2 //// + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x) (x+0x00000594) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_PHYS(x) (x+0x00000594) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_RMSK) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_2_AGING_HEADPTR_LO_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_2 //// + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x) (x+0x00000598) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_PHYS(x) (x+0x00000598) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_RMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_RMSK) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_2_AGING_HEADPTR_HI_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_2 //// + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x) (x+0x0000059c) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_PHYS(x) (x+0x0000059c) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_RMSK) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_2_AGING_TAILPTR_LO_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_2 //// + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x) (x+0x000005a0) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_PHYS(x) (x+0x000005a0) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_RMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_RMSK) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_2_AGING_TAILPTR_HI_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_HEADPTR_LO_IX_3 //// + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x) (x+0x000005a4) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_PHYS(x) (x+0x000005a4) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_RMSK) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_AGING_HEADPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_LO_IX_3_AGING_HEADPTR_LO_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_HEADPTR_HI_IX_3 //// + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x) (x+0x000005a8) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_PHYS(x) (x+0x000005a8) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_RMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_RMSK) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_AGING_HEADPTR_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_HEADPTR_HI_IX_3_AGING_HEADPTR_HI_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_TAILPTR_LO_IX_3 //// + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x) (x+0x000005ac) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_PHYS(x) (x+0x000005ac) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_RMSK) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_AGING_TAILPTR_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_LO_IX_3_AGING_TAILPTR_LO_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_LINK_TAILPTR_HI_IX_3 //// + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x) (x+0x000005b0) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_PHYS(x) (x+0x000005b0) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_RMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_SHFT 0 +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_RMSK) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), val) +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_AGING_TAILPTR_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_AGING_LINK_TAILPTR_HI_IX_3_AGING_TAILPTR_HI_BITS_SHFT 0x0 + +//// Register REO_R0_AGING_NUM_QUEUES_IX_0 //// + +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x) (x+0x000005b4) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_PHYS(x) (x+0x000005b4) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_RMSK 0x0000ffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_SHFT 0 +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_RMSK) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), val) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_AGING_NUM_QUEUES_AC0_BMSK 0x0000ffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_0_AGING_NUM_QUEUES_AC0_SHFT 0x0 + +//// Register REO_R0_AGING_NUM_QUEUES_IX_1 //// + +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x) (x+0x000005b8) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_PHYS(x) (x+0x000005b8) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_RMSK 0x0000ffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_SHFT 0 +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_RMSK) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), val) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_AGING_NUM_QUEUES_AC1_BMSK 0x0000ffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_1_AGING_NUM_QUEUES_AC1_SHFT 0x0 + +//// Register REO_R0_AGING_NUM_QUEUES_IX_2 //// + +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x) (x+0x000005bc) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_PHYS(x) (x+0x000005bc) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_RMSK 0x0000ffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_SHFT 0 +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_RMSK) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), val) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_AGING_NUM_QUEUES_AC2_BMSK 0x0000ffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_2_AGING_NUM_QUEUES_AC2_SHFT 0x0 + +//// Register REO_R0_AGING_NUM_QUEUES_IX_3 //// + +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x) (x+0x000005c0) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_PHYS(x) (x+0x000005c0) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_RMSK 0x0000ffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_SHFT 0 +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_RMSK) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), val) +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_AGING_NUM_QUEUES_AC3_BMSK 0x0000ffff +#define HWIO_REO_R0_AGING_NUM_QUEUES_IX_3_AGING_NUM_QUEUES_AC3_SHFT 0x0 + +//// Register REO_R0_AGING_TIMESTAMP_IX_0 //// + +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x) (x+0x000005c4) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_PHYS(x) (x+0x000005c4) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_SHFT 0 +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_0_RMSK) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), val) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_AGING_TIMESTAMP_AC0_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_0_AGING_TIMESTAMP_AC0_SHFT 0x0 + +//// Register REO_R0_AGING_TIMESTAMP_IX_1 //// + +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x) (x+0x000005c8) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_PHYS(x) (x+0x000005c8) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_SHFT 0 +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_1_RMSK) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), val) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_AGING_TIMESTAMP_AC1_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_1_AGING_TIMESTAMP_AC1_SHFT 0x0 + +//// Register REO_R0_AGING_TIMESTAMP_IX_2 //// + +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x) (x+0x000005cc) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_PHYS(x) (x+0x000005cc) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_SHFT 0 +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_2_RMSK) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), val) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_AGING_TIMESTAMP_AC2_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_2_AGING_TIMESTAMP_AC2_SHFT 0x0 + +//// Register REO_R0_AGING_TIMESTAMP_IX_3 //// + +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x) (x+0x000005d0) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_PHYS(x) (x+0x000005d0) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_SHFT 0 +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), HWIO_REO_R0_AGING_TIMESTAMP_IX_3_RMSK) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), val) +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_TIMESTAMP_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AGING_TIMESTAMP_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_AGING_TIMESTAMP_AC3_BMSK 0xffffffff +#define HWIO_REO_R0_AGING_TIMESTAMP_IX_3_AGING_TIMESTAMP_AC3_SHFT 0x0 + +//// Register REO_R0_AGING_CONTROL //// + +#define HWIO_REO_R0_AGING_CONTROL_ADDR(x) (x+0x000005d4) +#define HWIO_REO_R0_AGING_CONTROL_PHYS(x) (x+0x000005d4) +#define HWIO_REO_R0_AGING_CONTROL_RMSK 0x0000001f +#define HWIO_REO_R0_AGING_CONTROL_SHFT 0 +#define HWIO_REO_R0_AGING_CONTROL_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AGING_CONTROL_ADDR(x), HWIO_REO_R0_AGING_CONTROL_RMSK) +#define HWIO_REO_R0_AGING_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AGING_CONTROL_ADDR(x), mask) +#define HWIO_REO_R0_AGING_CONTROL_OUT(x, val) \ + out_dword( HWIO_REO_R0_AGING_CONTROL_ADDR(x), val) +#define HWIO_REO_R0_AGING_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AGING_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_AGING_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AGING_CONTROL_PERMPDU_UPDATE_THRESHOLD_BMSK 0x0000001f +#define HWIO_REO_R0_AGING_CONTROL_PERMPDU_UPDATE_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_MISC_CTL //// + +#define HWIO_REO_R0_MISC_CTL_ADDR(x) (x+0x000005d8) +#define HWIO_REO_R0_MISC_CTL_PHYS(x) (x+0x000005d8) +#define HWIO_REO_R0_MISC_CTL_RMSK 0x001fffff +#define HWIO_REO_R0_MISC_CTL_SHFT 0 +#define HWIO_REO_R0_MISC_CTL_IN(x) \ + in_dword_masked ( HWIO_REO_R0_MISC_CTL_ADDR(x), HWIO_REO_R0_MISC_CTL_RMSK) +#define HWIO_REO_R0_MISC_CTL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_MISC_CTL_ADDR(x), mask) +#define HWIO_REO_R0_MISC_CTL_OUT(x, val) \ + out_dword( HWIO_REO_R0_MISC_CTL_ADDR(x), val) +#define HWIO_REO_R0_MISC_CTL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_MISC_CTL_ADDR(x), mask, val, HWIO_REO_R0_MISC_CTL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_BMSK 0x001e0000 +#define HWIO_REO_R0_MISC_CTL_FRAGMENT_DEST_RING_SHFT 0x11 + +#define HWIO_REO_R0_MISC_CTL_CACHE_FLUSH_Q_DESC_ONLY_BMSK 0x00010000 +#define HWIO_REO_R0_MISC_CTL_CACHE_FLUSH_Q_DESC_ONLY_SHFT 0x10 + +#define HWIO_REO_R0_MISC_CTL_MSI_ENABLE_CHK_BIT_BMSK 0x00008000 +#define HWIO_REO_R0_MISC_CTL_MSI_ENABLE_CHK_BIT_SHFT 0xf + +#define HWIO_REO_R0_MISC_CTL_SPARE_CONTROL_BMSK 0x00007fff +#define HWIO_REO_R0_MISC_CTL_SPARE_CONTROL_SHFT 0x0 + +//// Register REO_R0_HIGH_MEMORY_THRESHOLD //// + +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x) (x+0x000005dc) +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_PHYS(x) (x+0x000005dc) +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_RMSK 0xffffffff +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_SHFT 0 +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_IN(x) \ + in_dword_masked ( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_RMSK) +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), mask) +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_OUT(x, val) \ + out_dword( HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), val) +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_ADDR(x), mask, val, HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_HIGH_MEMORY_THRESHOLD_BMSK 0xffffffff +#define HWIO_REO_R0_HIGH_MEMORY_THRESHOLD_HIGH_MEMORY_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_AC_BUFFERS_USED_IX_0 //// + +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x) (x+0x000005e0) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_PHYS(x) (x+0x000005e0) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_SHFT 0 +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_0_RMSK) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), val) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_0_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_BUFFERS_USED_BMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_0_BUFFERS_USED_SHFT 0x0 + +//// Register REO_R0_AC_BUFFERS_USED_IX_1 //// + +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x) (x+0x000005e4) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_PHYS(x) (x+0x000005e4) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_SHFT 0 +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_1_RMSK) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), val) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_1_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_BUFFERS_USED_BMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_1_BUFFERS_USED_SHFT 0x0 + +//// Register REO_R0_AC_BUFFERS_USED_IX_2 //// + +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x) (x+0x000005e8) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_PHYS(x) (x+0x000005e8) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_SHFT 0 +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_2_RMSK) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), val) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_2_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_BUFFERS_USED_BMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_2_BUFFERS_USED_SHFT 0x0 + +//// Register REO_R0_AC_BUFFERS_USED_IX_3 //// + +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x) (x+0x000005ec) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_PHYS(x) (x+0x000005ec) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_SHFT 0 +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), HWIO_REO_R0_AC_BUFFERS_USED_IX_3_RMSK) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), val) +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_AC_BUFFERS_USED_IX_3_ADDR(x), mask, val, HWIO_REO_R0_AC_BUFFERS_USED_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_BUFFERS_USED_BMSK 0xffffffff +#define HWIO_REO_R0_AC_BUFFERS_USED_IX_3_BUFFERS_USED_SHFT 0x0 + +//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0 //// + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x) (x+0x000005f0) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_PHYS(x) (x+0x000005f0) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_RMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_SHFT 0 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_RMSK) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), val) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_THRESHOLD_BMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_0_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1 //// + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x) (x+0x000005f4) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_PHYS(x) (x+0x000005f4) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_RMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_SHFT 0 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_RMSK) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), val) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_THRESHOLD_BMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_1_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2 //// + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x) (x+0x000005f8) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_PHYS(x) (x+0x000005f8) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_RMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_SHFT 0 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_RMSK) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), val) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_THRESHOLD_BMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_IX_2_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL //// + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x) (x+0x000005fc) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_PHYS(x) (x+0x000005fc) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_RMSK 0x03ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_SHFT 0 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_RMSK) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), mask) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_OUT(x, val) \ + out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), val) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_THRESHOLD_BMSK 0x03ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_THRESH_TOTAL_THRESHOLD_SHFT 0x0 + +//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0 //// + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x) (x+0x00000600) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_PHYS(x) (x+0x00000600) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_RMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_SHFT 0 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_RMSK) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), val) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_COUNT_BMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_0_COUNT_SHFT 0x0 + +//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1 //// + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x) (x+0x00000604) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_PHYS(x) (x+0x00000604) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_RMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_SHFT 0 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_RMSK) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), val) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_COUNT_BMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_1_COUNT_SHFT 0x0 + +//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2 //// + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x) (x+0x00000608) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_PHYS(x) (x+0x00000608) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_RMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_SHFT 0 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_RMSK) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), val) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_COUNT_BMSK 0x00ffffff +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_IX_2_COUNT_SHFT 0x0 + +//// Register REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL //// + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x) (x+0x0000060c) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_PHYS(x) (x+0x0000060c) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_RMSK 0x00000001 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_SHFT 0 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_RMSK) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), mask) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_OUT(x, val) \ + out_dword( HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), val) +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ADDR(x), mask, val, HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ENABLE_DESC_THRESH_TLV_BMSK 0x00000001 +#define HWIO_REO_R0_GLOBAL_LINK_DESC_COUNT_CTRL_ENABLE_DESC_THRESH_TLV_SHFT 0x0 + +//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0 //// + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x) (x+0x00000610) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_PHYS(x) (x+0x00000610) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_SHFT 0 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_RMSK) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), val) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDRESS_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_0_ADDRESS_LO_BITS_SHFT 0x0 + +//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0 //// + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x) (x+0x00000614) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_PHYS(x) (x+0x00000614) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_RMSK 0x000000ff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_SHFT 0 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_RMSK) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), val) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDRESS_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_0_ADDRESS_HI_BITS_SHFT 0x0 + +//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1 //// + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x) (x+0x00000618) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_PHYS(x) (x+0x00000618) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_SHFT 0 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_RMSK) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), val) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDRESS_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_1_ADDRESS_LO_BITS_SHFT 0x0 + +//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1 //// + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x) (x+0x0000061c) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_PHYS(x) (x+0x0000061c) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_RMSK 0x000000ff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_SHFT 0 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_RMSK) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), val) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDRESS_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_1_ADDRESS_HI_BITS_SHFT 0x0 + +//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2 //// + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x) (x+0x00000620) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_PHYS(x) (x+0x00000620) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_SHFT 0 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_RMSK) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), val) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDRESS_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_2_ADDRESS_LO_BITS_SHFT 0x0 + +//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2 //// + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x) (x+0x00000624) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_PHYS(x) (x+0x00000624) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_RMSK 0x000000ff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_SHFT 0 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_RMSK) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), val) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDRESS_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_2_ADDRESS_HI_BITS_SHFT 0x0 + +//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3 //// + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x) (x+0x00000628) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_PHYS(x) (x+0x00000628) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_SHFT 0 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_RMSK) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), val) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDRESS_LO_BITS_BMSK 0xffffffff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_LO_IX_3_ADDRESS_LO_BITS_SHFT 0x0 + +//// Register REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3 //// + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x) (x+0x0000062c) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_PHYS(x) (x+0x0000062c) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_RMSK 0x000000ff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_SHFT 0 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_RMSK) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), val) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDRESS_HI_BITS_BMSK 0x000000ff +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_ADDR_HI_IX_3_ADDRESS_HI_BITS_SHFT 0x0 + +//// Register REO_R0_QUEUE_DESC_BLOCK_INFO //// + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x) (x+0x00000630) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_PHYS(x) (x+0x00000630) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_RMSK 0x0000001f +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_SHFT 0 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_IN(x) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_RMSK) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), mask) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_OUT(x, val) \ + out_dword( HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), val) +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDR(x), mask, val, HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ENTIRE_CACHE_BLOCKED_BMSK 0x00000010 +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ENTIRE_CACHE_BLOCKED_SHFT 0x4 + +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDRESS_VALID_BMSK 0x0000000f +#define HWIO_REO_R0_QUEUE_DESC_BLOCK_INFO_ADDRESS_VALID_SHFT 0x0 + +//// Register REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG //// + +#define HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x) (x+0x00000634) +#define HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_PHYS(x) (x+0x00000634) +#define HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_RMSK 0x1fff000f +#define HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_SHFT 0 +#define HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_RMSK) +#define HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), val) +#define HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), mask, val, HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_BMSK 0x1fff0000 +#define HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_BMSK 0x0000000f +#define HWIO_REO_R0_REO2SW1_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_SHFT 0x0 + +//// Register REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG //// + +#define HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x) (x+0x00000638) +#define HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_PHYS(x) (x+0x00000638) +#define HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_RMSK 0x1fff000f +#define HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_SHFT 0 +#define HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_RMSK) +#define HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), val) +#define HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), mask, val, HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_BMSK 0x1fff0000 +#define HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_BMSK 0x0000000f +#define HWIO_REO_R0_REO2SW2_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_SHFT 0x0 + +//// Register REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG //// + +#define HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x) (x+0x0000063c) +#define HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_PHYS(x) (x+0x0000063c) +#define HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_RMSK 0x1fff000f +#define HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_SHFT 0 +#define HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_RMSK) +#define HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), val) +#define HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), mask, val, HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_BMSK 0x1fff0000 +#define HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_BMSK 0x0000000f +#define HWIO_REO_R0_REO2SW3_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_SHFT 0x0 + +//// Register REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG //// + +#define HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x) (x+0x00000640) +#define HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_PHYS(x) (x+0x00000640) +#define HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_RMSK 0x1fff000f +#define HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_SHFT 0 +#define HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_RMSK) +#define HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), val) +#define HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), mask, val, HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_BMSK 0x1fff0000 +#define HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_BMSK 0x0000000f +#define HWIO_REO_R0_REO2SW4_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_SHFT 0x0 + +//// Register REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG //// + +#define HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x) (x+0x00000644) +#define HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_PHYS(x) (x+0x00000644) +#define HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_RMSK 0x1fff000f +#define HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_SHFT 0 +#define HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_RMSK) +#define HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), val) +#define HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), mask, val, HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_BMSK 0x1fff0000 +#define HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_BMSK 0x0000000f +#define HWIO_REO_R0_REO2SW5_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_SHFT 0x0 + +//// Register REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG //// + +#define HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x) (x+0x00000648) +#define HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_PHYS(x) (x+0x00000648) +#define HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_RMSK 0x1fff000f +#define HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_SHFT 0 +#define HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_RMSK) +#define HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), mask) +#define HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), val) +#define HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), mask, val, HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_BMSK 0x1fff0000 +#define HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_SHFT 0x10 + +#define HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_BMSK 0x0000000f +#define HWIO_REO_R0_REO2SW6_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_SHFT 0x0 + +//// Register REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG //// + +#define HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x) (x+0x0000064c) +#define HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_PHYS(x) (x+0x0000064c) +#define HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_RMSK 0x1fff000f +#define HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_SHFT 0 +#define HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_RMSK) +#define HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), mask) +#define HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), val) +#define HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), mask, val, HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_BMSK 0x1fff0000 +#define HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_SHFT 0x10 + +#define HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_BMSK 0x0000000f +#define HWIO_REO_R0_REO2FW_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_SHFT 0x0 + +//// Register REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG //// + +#define HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x) (x+0x00000650) +#define HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_PHYS(x) (x+0x00000650) +#define HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_RMSK 0x1fff000f +#define HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_SHFT 0 +#define HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_IN(x) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_RMSK) +#define HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), mask) +#define HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_OUT(x, val) \ + out_dword( HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), val) +#define HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_ADDR(x), mask, val, HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_BMSK 0x1fff0000 +#define HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_READ_START_OFFSET_SHFT 0x10 + +#define HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_BMSK 0x0000000f +#define HWIO_REO_R0_REO2TCL_MSDU_HEADER_CAPTURE_CONFIG_CAPTURED_MSDU_DATA_SIZE_SHFT 0x0 + +//// Register REO_R0_GXI_TESTBUS_LOWER //// + +#define HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x) (x+0x00000654) +#define HWIO_REO_R0_GXI_TESTBUS_LOWER_PHYS(x) (x+0x00000654) +#define HWIO_REO_R0_GXI_TESTBUS_LOWER_RMSK 0xffffffff +#define HWIO_REO_R0_GXI_TESTBUS_LOWER_SHFT 0 +#define HWIO_REO_R0_GXI_TESTBUS_LOWER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), HWIO_REO_R0_GXI_TESTBUS_LOWER_RMSK) +#define HWIO_REO_R0_GXI_TESTBUS_LOWER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), mask) +#define HWIO_REO_R0_GXI_TESTBUS_LOWER_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), val) +#define HWIO_REO_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_REO_R0_GXI_TESTBUS_LOWER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_TESTBUS_LOWER_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_GXI_TESTBUS_LOWER_VALUE_SHFT 0x0 + +//// Register REO_R0_GXI_TESTBUS_UPPER //// + +#define HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x) (x+0x00000658) +#define HWIO_REO_R0_GXI_TESTBUS_UPPER_PHYS(x) (x+0x00000658) +#define HWIO_REO_R0_GXI_TESTBUS_UPPER_RMSK 0x000000ff +#define HWIO_REO_R0_GXI_TESTBUS_UPPER_SHFT 0 +#define HWIO_REO_R0_GXI_TESTBUS_UPPER_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), HWIO_REO_R0_GXI_TESTBUS_UPPER_RMSK) +#define HWIO_REO_R0_GXI_TESTBUS_UPPER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), mask) +#define HWIO_REO_R0_GXI_TESTBUS_UPPER_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), val) +#define HWIO_REO_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_REO_R0_GXI_TESTBUS_UPPER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_TESTBUS_UPPER_VALUE_BMSK 0x000000ff +#define HWIO_REO_R0_GXI_TESTBUS_UPPER_VALUE_SHFT 0x0 + +//// Register REO_R0_GXI_SM_STATES_IX_0 //// + +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x) (x+0x0000065c) +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_PHYS(x) (x+0x0000065c) +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_RMSK 0x00000fff +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SHFT 0 +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), HWIO_REO_R0_GXI_SM_STATES_IX_0_RMSK) +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), val) +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GXI_SM_STATES_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00 +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9 + +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x000001f0 +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 0x4 + +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0x0000000f +#define HWIO_REO_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0x0 + +//// Register REO_R0_GXI_END_OF_TEST_CHECK //// + +#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x) (x+0x00000660) +#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_PHYS(x) (x+0x00000660) +#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_RMSK 0x00000001 +#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_SHFT 0 +#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R0_GXI_END_OF_TEST_CHECK_RMSK) +#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask) +#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), val) +#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R0_GXI_END_OF_TEST_CHECK_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 +#define HWIO_REO_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 + +//// Register REO_R0_GXI_CLOCK_GATE_DISABLE //// + +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x) (x+0x00000664) +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_PHYS(x) (x+0x00000664) +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RMSK 0x80000fff +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_SHFT 0 +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RMSK) +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask) +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), val) +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f + +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_SPARE_BMSK 0x00000800 +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_SPARE_SHFT 0xb + +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_BMSK 0x00000400 +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_SHFT 0xa + +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_FIFO_BMSK 0x00000200 +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_FIFO_SHFT 0x9 + +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_BMSK 0x00000100 +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_SHFT 0x8 + +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_BMSK 0x00000080 +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_SHFT 0x7 + +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_BMSK 0x00000040 +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_SHFT 0x6 + +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_BMSK 0x00000020 +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_SHFT 0x5 + +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_BMSK 0x00000010 +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_SHFT 0x4 + +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_BMSK 0x00000008 +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_SHFT 0x3 + +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_BMSK 0x00000004 +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_SHFT 0x2 + +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_CMD_BMSK 0x00000002 +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_RD_CMD_SHFT 0x1 + +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CORE_BMSK 0x00000001 +#define HWIO_REO_R0_GXI_CLOCK_GATE_DISABLE_CORE_SHFT 0x0 + +//// Register REO_R0_GXI_GXI_ERR_INTS //// + +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x) (x+0x00000668) +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_PHYS(x) (x+0x00000668) +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_RMSK 0x01010101 +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_SHFT 0 +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), HWIO_REO_R0_GXI_GXI_ERR_INTS_RMSK) +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), mask) +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), val) +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_ERR_INTS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000 +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18 + +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x00010000 +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 0x10 + +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x00000100 +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 0x8 + +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x00000001 +#define HWIO_REO_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0x0 + +//// Register REO_R0_GXI_GXI_ERR_STATS //// + +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x) (x+0x0000066c) +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_PHYS(x) (x+0x0000066c) +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_RMSK 0x003f3f3f +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_SHFT 0 +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), HWIO_REO_R0_GXI_GXI_ERR_STATS_RMSK) +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), mask) +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), val) +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_ERR_STATS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000 +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10 + +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x00003f00 +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 0x8 + +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x0000003f +#define HWIO_REO_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0x0 + +//// Register REO_R0_GXI_GXI_DEFAULT_CONTROL //// + +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x) (x+0x00000670) +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_PHYS(x) (x+0x00000670) +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_SHFT 0 +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_RMSK) +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask) +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), val) +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18 + +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 0x10 + +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00 +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 0x8 + +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f +#define HWIO_REO_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0x0 + +//// Register REO_R0_GXI_GXI_REDUCED_CONTROL //// + +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x) (x+0x00000674) +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_PHYS(x) (x+0x00000674) +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_SHFT 0 +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_RMSK) +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask) +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), val) +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18 + +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 0x10 + +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00 +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 0x8 + +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f +#define HWIO_REO_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0x0 + +//// Register REO_R0_GXI_GXI_MISC_CONTROL //// + +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x) (x+0x00000678) +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_PHYS(x) (x+0x00000678) +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_RMSK 0x0fffffff +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_SHFT 0 +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_MISC_CONTROL_RMSK) +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask) +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), val) +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_MISC_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_BMSK 0x08000000 +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_SHFT 0x1b + +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_BMSK 0x04000000 +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_SHFT 0x1a + +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_BMSK 0x02000000 +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_SHFT 0x19 + +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_BMSK 0x01000000 +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_SHFT 0x18 + +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_BMSK 0x00800000 +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_SHFT 0x17 + +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000 +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14 + +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0x000e0000 +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 0x11 + +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00 +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 0x9 + +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 0x1 + +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x00000001 +#define HWIO_REO_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0x0 + +//// Register REO_R0_GXI_GXI_WDOG_CONTROL //// + +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x) (x+0x0000067c) +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_PHYS(x) (x+0x0000067c) +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_RMSK 0xffff0001 +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_SHFT 0 +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_RMSK) +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask) +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), val) +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10 + +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x00000001 +#define HWIO_REO_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0x0 + +//// Register REO_R0_GXI_GXI_WDOG_STATUS //// + +#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x) (x+0x00000680) +#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_PHYS(x) (x+0x00000680) +#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_RMSK 0x0000ffff +#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_SHFT 0 +#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), HWIO_REO_R0_GXI_GXI_WDOG_STATUS_RMSK) +#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask) +#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), val) +#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WDOG_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff +#define HWIO_REO_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0 + +//// Register REO_R0_GXI_GXI_IDLE_COUNTERS //// + +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x) (x+0x00000684) +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_PHYS(x) (x+0x00000684) +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_RMSK 0xffffffff +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_SHFT 0 +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_RMSK) +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask) +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), val) +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10 + +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0x0000ffff +#define HWIO_REO_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0x0 + +//// Register REO_R0_GXI_GXI_RD_LATENCY_CTRL //// + +#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x) (x+0x00000688) +#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_PHYS(x) (x+0x00000688) +#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_RMSK 0x000fffff +#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_SHFT 0 +#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_RMSK) +#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), mask) +#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), val) +#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0x000e0000 +#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11 + +#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x00010000 +#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10 + +#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0x0000ffff +#define HWIO_REO_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0 + +//// Register REO_R0_GXI_GXI_WR_LATENCY_CTRL //// + +#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x) (x+0x0000068c) +#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_PHYS(x) (x+0x0000068c) +#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_RMSK 0x000fffff +#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_SHFT 0 +#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_RMSK) +#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), mask) +#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), val) +#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0x000e0000 +#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11 + +#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x00010000 +#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10 + +#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0x0000ffff +#define HWIO_REO_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0 + +//// Register REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0 //// + +#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x) (x+0x00000690) +#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_PHYS(x) (x+0x00000690) +#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_SHFT 0 +#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK) +#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), val) +#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0x0 + +//// Register REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1 //// + +#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x) (x+0x00000694) +#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_PHYS(x) (x+0x00000694) +#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_SHFT 0 +#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK) +#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), val) +#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0x0 + +//// Register REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0 //// + +#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x) (x+0x00000698) +#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_PHYS(x) (x+0x00000698) +#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_SHFT 0 +#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK) +#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), val) +#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0x0 + +//// Register REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1 //// + +#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x) (x+0x0000069c) +#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_PHYS(x) (x+0x0000069c) +#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_SHFT 0 +#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK) +#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), val) +#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff +#define HWIO_REO_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0x0 + +//// Register REO_R0_GXI_GXI_AXI_OUTSANDING_CTL //// + +#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x) (x+0x000006a0) +#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_PHYS(x) (x+0x000006a0) +#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RMSK 0x00009f9f +#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_SHFT 0 +#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_IN(x) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RMSK) +#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), mask) +#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_OUT(x, val) \ + out_dword( HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), val) +#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), mask, val, HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_EN_BMSK 0x00008000 +#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_EN_SHFT 0xf + +#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_CNT_BMSK 0x00001f00 +#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_CNT_SHFT 0x8 + +#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_EN_BMSK 0x00000080 +#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_EN_SHFT 0x7 + +#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_BMSK 0x0000001f +#define HWIO_REO_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_SHFT 0x0 + +//// Register REO_R0_CACHE_CTL_CONFIG //// + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x) (x+0x000006a4) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_PHYS(x) (x+0x000006a4) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_RMSK 0xffffffff +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SHFT 0 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_IN(x) \ + in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), HWIO_REO_R0_CACHE_CTL_CONFIG_RMSK) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), mask) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_OUT(x, val) \ + out_dword( HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), val) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONFIG_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_CONFIG_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_DESC_TYPE_SWAP_BMSK 0xff000000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_DESC_TYPE_SWAP_SHFT 0x18 + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_ENABLE_LEGACY_SWAP_BMSK 0x00800000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_ENABLE_LEGACY_SWAP_SHFT 0x17 + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_BMSK 0x00400000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_STRUCT_SWAP_SHFT 0x16 + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_STRUCT_SWAP_BMSK 0x00200000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_STRUCT_SWAP_SHFT 0x15 + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_SECURITY_BMSK 0x00100000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_WRITE_SECURITY_SHFT 0x14 + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_SECURITY_BMSK 0x00080000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_READ_SECURITY_SHFT 0x13 + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_BG_FLUSH_POST_WRITE_BMSK 0x00040000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_BG_FLUSH_POST_WRITE_SHFT 0x12 + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CLIENT_FLUSH_POST_WRITE_BMSK 0x00020000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CLIENT_FLUSH_POST_WRITE_SHFT 0x11 + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_EMPTY_THRESHOLD_BMSK 0x0001fe00 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_EMPTY_THRESHOLD_SHFT 0x9 + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_LINE_USE_NUM_BMSK 0x000001ff +#define HWIO_REO_R0_CACHE_CTL_CONFIG_CACHE_LINE_USE_NUM_SHFT 0x0 + +//// Register REO_R0_CACHE_CTL_CONTROL //// + +#define HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x) (x+0x000006a8) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_PHYS(x) (x+0x000006a8) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_RMSK 0x00000003 +#define HWIO_REO_R0_CACHE_CTL_CONTROL_SHFT 0 +#define HWIO_REO_R0_CACHE_CTL_CONTROL_IN(x) \ + in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), HWIO_REO_R0_CACHE_CTL_CONTROL_RMSK) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), mask) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_OUT(x, val) \ + out_dword( HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), val) +#define HWIO_REO_R0_CACHE_CTL_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONTROL_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_CACHE_CTL_CONTROL_WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH_BMSK 0x00000002 +#define HWIO_REO_R0_CACHE_CTL_CONTROL_WRITE_POSTED_FOR_NON_POSTED_LINE_FLUSH_SHFT 0x1 + +#define HWIO_REO_R0_CACHE_CTL_CONTROL_CACHE_RESET_BMSK 0x00000001 +#define HWIO_REO_R0_CACHE_CTL_CONTROL_CACHE_RESET_SHFT 0x0 + +//// Register REO_R0_CACHE_CTL_CONFIG_SET //// + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x) (x+0x000006ac) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_PHYS(x) (x+0x000006ac) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_RMSK 0x01ffffff +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_SHFT 0 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_IN(x) \ + in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x), HWIO_REO_R0_CACHE_CTL_CONFIG_SET_RMSK) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x), mask) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_OUT(x, val) \ + out_dword( HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x), val) +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_CONFIG_SET_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_CONFIG_SET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_DESC_TYPE_BITMAP_BMSK 0x01fe0000 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_DESC_TYPE_BITMAP_SHFT 0x11 + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_CACHE_EMPTY_THRESHOLD_SET2_BMSK 0x0001fe00 +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_CACHE_EMPTY_THRESHOLD_SET2_SHFT 0x9 + +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_CACHE_LINE_USE_NUM_SET2_BMSK 0x000001ff +#define HWIO_REO_R0_CACHE_CTL_CONFIG_SET_CACHE_LINE_USE_NUM_SET2_SHFT 0x0 + +//// Register REO_R0_CACHE_CTL_SET_SIZE //// + +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x) (x+0x000006b0) +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_PHYS(x) (x+0x000006b0) +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_RMSK 0x000001ff +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_SHFT 0 +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_IN(x) \ + in_dword_masked ( HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x), HWIO_REO_R0_CACHE_CTL_SET_SIZE_RMSK) +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x), mask) +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_OUT(x, val) \ + out_dword( HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x), val) +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_CACHE_CTL_SET_SIZE_ADDR(x), mask, val, HWIO_REO_R0_CACHE_CTL_SET_SIZE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_SET1_SIZE_BMSK 0x000001ff +#define HWIO_REO_R0_CACHE_CTL_SET_SIZE_SET1_SIZE_SHFT 0x0 + +//// Register REO_R0_CLK_GATE_CTRL //// + +#define HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x) (x+0x000006b4) +#define HWIO_REO_R0_CLK_GATE_CTRL_PHYS(x) (x+0x000006b4) +#define HWIO_REO_R0_CLK_GATE_CTRL_RMSK 0x0007ffff +#define HWIO_REO_R0_CLK_GATE_CTRL_SHFT 0 +#define HWIO_REO_R0_CLK_GATE_CTRL_IN(x) \ + in_dword_masked ( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), HWIO_REO_R0_CLK_GATE_CTRL_RMSK) +#define HWIO_REO_R0_CLK_GATE_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), mask) +#define HWIO_REO_R0_CLK_GATE_CTRL_OUT(x, val) \ + out_dword( HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), val) +#define HWIO_REO_R0_CLK_GATE_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_CLK_GATE_CTRL_ADDR(x), mask, val, HWIO_REO_R0_CLK_GATE_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_7_BMSK 0x00040000 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_7_SHFT 0x12 + +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_6_BMSK 0x00020000 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_6_SHFT 0x11 + +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_5_BMSK 0x00010000 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_5_SHFT 0x10 + +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_4_BMSK 0x00008000 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_4_SHFT 0xf + +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_3_BMSK 0x00004000 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_3_SHFT 0xe + +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_2_BMSK 0x00002000 +#define HWIO_REO_R0_CLK_GATE_CTRL_RESERVE_2_SHFT 0xd + +#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SRNG_P_BMSK 0x00001000 +#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SRNG_P_SHFT 0xc + +#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SRNG_C_BMSK 0x00000800 +#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SRNG_C_SHFT 0xb + +#define HWIO_REO_R0_CLK_GATE_CTRL_CLOCK_ENS_EXTEND_BMSK 0x00000400 +#define HWIO_REO_R0_CLK_GATE_CTRL_CLOCK_ENS_EXTEND_SHFT 0xa + +#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_BMSK 0x000003ff +#define HWIO_REO_R0_CLK_GATE_CTRL_REO_CLKGATE_DISABLE_SHFT 0x0 + +//// Register REO_R0_EVENTMASK_IX_0 //// + +#define HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x) (x+0x000006b8) +#define HWIO_REO_R0_EVENTMASK_IX_0_PHYS(x) (x+0x000006b8) +#define HWIO_REO_R0_EVENTMASK_IX_0_RMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_0_SHFT 0 +#define HWIO_REO_R0_EVENTMASK_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_0_RMSK) +#define HWIO_REO_R0_EVENTMASK_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), mask) +#define HWIO_REO_R0_EVENTMASK_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), val) +#define HWIO_REO_R0_EVENTMASK_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_EVENTMASK_IX_0_MASK_BMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_0_MASK_SHFT 0x0 + +//// Register REO_R0_EVENTMASK_IX_1 //// + +#define HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x) (x+0x000006bc) +#define HWIO_REO_R0_EVENTMASK_IX_1_PHYS(x) (x+0x000006bc) +#define HWIO_REO_R0_EVENTMASK_IX_1_RMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_1_SHFT 0 +#define HWIO_REO_R0_EVENTMASK_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_1_RMSK) +#define HWIO_REO_R0_EVENTMASK_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), mask) +#define HWIO_REO_R0_EVENTMASK_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), val) +#define HWIO_REO_R0_EVENTMASK_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_EVENTMASK_IX_1_MASK_BMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_1_MASK_SHFT 0x0 + +//// Register REO_R0_EVENTMASK_IX_2 //// + +#define HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x) (x+0x000006c0) +#define HWIO_REO_R0_EVENTMASK_IX_2_PHYS(x) (x+0x000006c0) +#define HWIO_REO_R0_EVENTMASK_IX_2_RMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_2_SHFT 0 +#define HWIO_REO_R0_EVENTMASK_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_2_RMSK) +#define HWIO_REO_R0_EVENTMASK_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), mask) +#define HWIO_REO_R0_EVENTMASK_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), val) +#define HWIO_REO_R0_EVENTMASK_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_2_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_EVENTMASK_IX_2_MASK_BMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_2_MASK_SHFT 0x0 + +//// Register REO_R0_EVENTMASK_IX_3 //// + +#define HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x) (x+0x000006c4) +#define HWIO_REO_R0_EVENTMASK_IX_3_PHYS(x) (x+0x000006c4) +#define HWIO_REO_R0_EVENTMASK_IX_3_RMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_3_SHFT 0 +#define HWIO_REO_R0_EVENTMASK_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), HWIO_REO_R0_EVENTMASK_IX_3_RMSK) +#define HWIO_REO_R0_EVENTMASK_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), mask) +#define HWIO_REO_R0_EVENTMASK_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), val) +#define HWIO_REO_R0_EVENTMASK_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R0_EVENTMASK_IX_3_ADDR(x), mask, val, HWIO_REO_R0_EVENTMASK_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R0_EVENTMASK_IX_3_MASK_BMSK 0xffffffff +#define HWIO_REO_R0_EVENTMASK_IX_3_MASK_SHFT 0x0 + +//// Register REO_R1_MISC_DEBUG_CTRL //// + +#define HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x) (x+0x00002000) +#define HWIO_REO_R1_MISC_DEBUG_CTRL_PHYS(x) (x+0x00002000) +#define HWIO_REO_R1_MISC_DEBUG_CTRL_RMSK 0xffffffff +#define HWIO_REO_R1_MISC_DEBUG_CTRL_SHFT 0 +#define HWIO_REO_R1_MISC_DEBUG_CTRL_IN(x) \ + in_dword_masked ( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), HWIO_REO_R1_MISC_DEBUG_CTRL_RMSK) +#define HWIO_REO_R1_MISC_DEBUG_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), mask) +#define HWIO_REO_R1_MISC_DEBUG_CTRL_OUT(x, val) \ + out_dword( HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), val) +#define HWIO_REO_R1_MISC_DEBUG_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_MISC_DEBUG_CTRL_ADDR(x), mask, val, HWIO_REO_R1_MISC_DEBUG_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_MISC_DEBUG_CTRL_DISABLE_SW_EXCEPTION_BMSK 0x80000000 +#define HWIO_REO_R1_MISC_DEBUG_CTRL_DISABLE_SW_EXCEPTION_SHFT 0x1f + +#define HWIO_REO_R1_MISC_DEBUG_CTRL_IDLE_REQ_BMSK 0x40000000 +#define HWIO_REO_R1_MISC_DEBUG_CTRL_IDLE_REQ_SHFT 0x1e + +#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_RESUME_THRESH_BMSK 0x3ff00000 +#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_RESUME_THRESH_SHFT 0x14 + +#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_STOP_THRESH_BMSK 0x000ffc00 +#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_STOP_THRESH_SHFT 0xa + +#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_START_THRESH_BMSK 0x000003ff +#define HWIO_REO_R1_MISC_DEBUG_CTRL_CMD_FIFO_START_THRESH_SHFT 0x0 + +//// Register REO_R1_MISC_PERF_DEBUG_CTRL //// + +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x) (x+0x00002004) +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PHYS(x) (x+0x00002004) +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RMSK 0x00ffffff +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_SHFT 0 +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_IN(x) \ + in_dword_masked ( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RMSK) +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), mask) +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_OUT(x, val) \ + out_dword( HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), val) +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_ADDR(x), mask, val, HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RELEASE_RING_ACCUM_DELAY_BMSK 0x00fff000 +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_RELEASE_RING_ACCUM_DELAY_SHFT 0xc + +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PROD_RING_ACCUM_DELAY_BMSK 0x00000fff +#define HWIO_REO_R1_MISC_PERF_DEBUG_CTRL_PROD_RING_ACCUM_DELAY_SHFT 0x0 + +//// Register REO_R1_CACHE_CTL_DEBUG_CONTROL //// + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x) (x+0x00002008) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_PHYS(x) (x+0x00002008) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_RMSK 0x00000fff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_SHFT 0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_IN(x) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_RMSK) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), mask) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_OUT(x, val) \ + out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), val) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_ACK_BMSK 0x00000800 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_ACK_SHFT 0xb + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_BMSK 0x00000400 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_CACHE_CMD_HOLD_SHFT 0xa + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_UPDATE_BMSK 0x00000200 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_UPDATE_SHFT 0x9 + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_SEL_BMSK 0x000001ff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_CONTROL_TAG_TABLE_SEL_SHFT 0x0 + +//// Register REO_R1_CACHE_CTL_DEBUG_HIT_COUNT //// + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x) (x+0x0000200c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_PHYS(x) (x+0x0000200c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_SHFT 0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_IN(x) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_RMSK) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), mask) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUT(x, val) \ + out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), val) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_CACHE_HIT_COUNT_BMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HIT_COUNT_CACHE_HIT_COUNT_SHFT 0x0 + +//// Register REO_R1_CACHE_CTL_DEBUG_MISS_COUNT //// + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x) (x+0x00002010) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_PHYS(x) (x+0x00002010) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_RMSK 0x00ffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_SHFT 0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_IN(x) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_RMSK) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), mask) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUT(x, val) \ + out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), val) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_CACHE_MISS_COUNT_BMSK 0x00ffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_MISS_COUNT_CACHE_MISS_COUNT_SHFT 0x0 + +//// Register REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW //// + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x) (x+0x00002014) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_PHYS(x) (x+0x00002014) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_SHFT 0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_IN(x) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_RMSK) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), mask) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUT(x, val) \ + out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), val) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OVERWRITE_BMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_LOW_OVERWRITE_SHFT 0x0 + +//// Register REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH //// + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x) (x+0x00002018) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_PHYS(x) (x+0x00002018) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_SHFT 0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_IN(x) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_RMSK) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), mask) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUT(x, val) \ + out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), val) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OVERWRITE_BMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_TAG_TABLE_HIGH_OVERWRITE_SHFT 0x0 + +//// Register REO_R1_CACHE_CTL_DEBUG_STM //// + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x) (x+0x0000201c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_PHYS(x) (x+0x0000201c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_RMSK 0x01ffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_SHFT 0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_IN(x) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_STM_RMSK) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), mask) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_OUT(x, val) \ + out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), val) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_STM_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_STM_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_STATE_BMSK 0x01ffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_STM_STATE_SHFT 0x0 + +//// Register REO_R1_CACHE_CTL_DEBUG_LINK_LIST //// + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x) (x+0x00002020) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_PHYS(x) (x+0x00002020) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_RMSK 0x0007ffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_SHFT 0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_IN(x) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_RMSK) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), mask) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_OUT(x, val) \ + out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), val) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_MRU_FLAG_BMSK 0x0007fc00 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_MRU_FLAG_SHFT 0xa + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_LRU_FLAG_BMSK 0x000003ff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST_LRU_FLAG_SHFT 0x0 + +//// Register REO_R1_CACHE_CTL_DEBUG_LINK_LIST1 //// + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x) (x+0x00002024) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_PHYS(x) (x+0x00002024) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_RMSK 0x0007ffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_SHFT 0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_IN(x) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_RMSK) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x), mask) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_OUT(x, val) \ + out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x), val) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_HEAD_FLAG_BMSK 0x0007fc00 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_HEAD_FLAG_SHFT 0xa + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_TAIL_FLAG_BMSK 0x000003ff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST1_TAIL_FLAG_SHFT 0x0 + +//// Register REO_R1_CACHE_CTL_DEBUG_LINK_LIST2 //// + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x) (x+0x00002028) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_PHYS(x) (x+0x00002028) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_RMSK 0x0007ffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_SHFT 0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_IN(x) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_RMSK) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x), mask) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_OUT(x, val) \ + out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x), val) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_MRU_FLAG_SET2_BMSK 0x0007fc00 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_MRU_FLAG_SET2_SHFT 0xa + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_LRU_FLAG_SET2_BMSK 0x000003ff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST2_LRU_FLAG_SET2_SHFT 0x0 + +//// Register REO_R1_CACHE_CTL_DEBUG_LINK_LIST3 //// + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x) (x+0x0000202c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_PHYS(x) (x+0x0000202c) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_RMSK 0x0007ffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_SHFT 0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_IN(x) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_RMSK) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x), mask) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_OUT(x, val) \ + out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x), val) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_HEAD_FLAG_SET2_BMSK 0x0007fc00 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_HEAD_FLAG_SET2_SHFT 0xa + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_TAIL_FLAG_SET2_BMSK 0x000003ff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_LINK_LIST3_TAIL_FLAG_SET2_SHFT 0x0 + +//// Register REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW //// + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x) (x+0x00002030) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_PHYS(x) (x+0x00002030) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_SHFT 0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_IN(x) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_RMSK) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x), mask) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_OUT(x, val) \ + out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x), val) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_VALUE_BMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_LOW_VALUE_SHFT 0x0 + +//// Register REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH //// + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x) (x+0x00002034) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_PHYS(x) (x+0x00002034) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_RMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_SHFT 0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_IN(x) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_RMSK) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x), mask) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_OUT(x, val) \ + out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x), val) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_VALUE_BMSK 0xffffffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_HW_ERR_INFO_HIGH_VALUE_SHFT 0x0 + +//// Register REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER //// + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x) (x+0x00002038) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_PHYS(x) (x+0x00002038) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_RMSK 0x000fffff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SHFT 0 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_IN(x) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_RMSK) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), mask) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_OUT(x, val) \ + out_dword( HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), val) +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET2_BMSK 0x000ffc00 +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET2_SHFT 0xa + +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET1_BMSK 0x000003ff +#define HWIO_REO_R1_CACHE_CTL_DEBUG_EMPTY_LINE_COUNTER_SET1_SHFT 0x0 + +//// Register REO_R1_CACHE_CTL_END_OF_TEST_CHECK //// + +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x) (x+0x0000203c) +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_PHYS(x) (x+0x0000203c) +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_RMSK 0x00000001 +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_SHFT 0 +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_RMSK) +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), mask) +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_OUT(x, val) \ + out_dword( HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), val) +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 +#define HWIO_REO_R1_CACHE_CTL_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 + +//// Register REO_R1_END_OF_TEST_CHECK //// + +#define HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x) (x+0x00002040) +#define HWIO_REO_R1_END_OF_TEST_CHECK_PHYS(x) (x+0x00002040) +#define HWIO_REO_R1_END_OF_TEST_CHECK_RMSK 0x00000001 +#define HWIO_REO_R1_END_OF_TEST_CHECK_SHFT 0 +#define HWIO_REO_R1_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked ( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_REO_R1_END_OF_TEST_CHECK_RMSK) +#define HWIO_REO_R1_END_OF_TEST_CHECK_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), mask) +#define HWIO_REO_R1_END_OF_TEST_CHECK_OUT(x, val) \ + out_dword( HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), val) +#define HWIO_REO_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_REO_R1_END_OF_TEST_CHECK_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 +#define HWIO_REO_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 + +//// Register REO_R1_SM_ALL_IDLE //// + +#define HWIO_REO_R1_SM_ALL_IDLE_ADDR(x) (x+0x00002044) +#define HWIO_REO_R1_SM_ALL_IDLE_PHYS(x) (x+0x00002044) +#define HWIO_REO_R1_SM_ALL_IDLE_RMSK 0x00000007 +#define HWIO_REO_R1_SM_ALL_IDLE_SHFT 0 +#define HWIO_REO_R1_SM_ALL_IDLE_IN(x) \ + in_dword_masked ( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), HWIO_REO_R1_SM_ALL_IDLE_RMSK) +#define HWIO_REO_R1_SM_ALL_IDLE_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), mask) +#define HWIO_REO_R1_SM_ALL_IDLE_OUT(x, val) \ + out_dword( HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), val) +#define HWIO_REO_R1_SM_ALL_IDLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_SM_ALL_IDLE_ADDR(x), mask, val, HWIO_REO_R1_SM_ALL_IDLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_SM_ALL_IDLE_REO_ENTRANCE_RINGS_NOT_EMPTY_BMSK 0x00000004 +#define HWIO_REO_R1_SM_ALL_IDLE_REO_ENTRANCE_RINGS_NOT_EMPTY_SHFT 0x2 + +#define HWIO_REO_R1_SM_ALL_IDLE_REO_IN_IDLE_BMSK 0x00000002 +#define HWIO_REO_R1_SM_ALL_IDLE_REO_IN_IDLE_SHFT 0x1 + +#define HWIO_REO_R1_SM_ALL_IDLE_ALL_STATES_IN_IDLE_BMSK 0x00000001 +#define HWIO_REO_R1_SM_ALL_IDLE_ALL_STATES_IN_IDLE_SHFT 0x0 + +//// Register REO_R1_TESTBUS_CTRL //// + +#define HWIO_REO_R1_TESTBUS_CTRL_ADDR(x) (x+0x00002048) +#define HWIO_REO_R1_TESTBUS_CTRL_PHYS(x) (x+0x00002048) +#define HWIO_REO_R1_TESTBUS_CTRL_RMSK 0x0000007f +#define HWIO_REO_R1_TESTBUS_CTRL_SHFT 0 +#define HWIO_REO_R1_TESTBUS_CTRL_IN(x) \ + in_dword_masked ( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), HWIO_REO_R1_TESTBUS_CTRL_RMSK) +#define HWIO_REO_R1_TESTBUS_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), mask) +#define HWIO_REO_R1_TESTBUS_CTRL_OUT(x, val) \ + out_dword( HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), val) +#define HWIO_REO_R1_TESTBUS_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_TESTBUS_CTRL_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_TESTBUS_CTRL_TESTBUS_SELECT_BMSK 0x0000007f +#define HWIO_REO_R1_TESTBUS_CTRL_TESTBUS_SELECT_SHFT 0x0 + +//// Register REO_R1_TESTBUS_LOWER //// + +#define HWIO_REO_R1_TESTBUS_LOWER_ADDR(x) (x+0x0000204c) +#define HWIO_REO_R1_TESTBUS_LOWER_PHYS(x) (x+0x0000204c) +#define HWIO_REO_R1_TESTBUS_LOWER_RMSK 0xffffffff +#define HWIO_REO_R1_TESTBUS_LOWER_SHFT 0 +#define HWIO_REO_R1_TESTBUS_LOWER_IN(x) \ + in_dword_masked ( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), HWIO_REO_R1_TESTBUS_LOWER_RMSK) +#define HWIO_REO_R1_TESTBUS_LOWER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), mask) +#define HWIO_REO_R1_TESTBUS_LOWER_OUT(x, val) \ + out_dword( HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), val) +#define HWIO_REO_R1_TESTBUS_LOWER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_LOWER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_TESTBUS_LOWER_VALUE_BMSK 0xffffffff +#define HWIO_REO_R1_TESTBUS_LOWER_VALUE_SHFT 0x0 + +//// Register REO_R1_TESTBUS_HIGHER //// + +#define HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x) (x+0x00002050) +#define HWIO_REO_R1_TESTBUS_HIGHER_PHYS(x) (x+0x00002050) +#define HWIO_REO_R1_TESTBUS_HIGHER_RMSK 0x000000ff +#define HWIO_REO_R1_TESTBUS_HIGHER_SHFT 0 +#define HWIO_REO_R1_TESTBUS_HIGHER_IN(x) \ + in_dword_masked ( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), HWIO_REO_R1_TESTBUS_HIGHER_RMSK) +#define HWIO_REO_R1_TESTBUS_HIGHER_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), mask) +#define HWIO_REO_R1_TESTBUS_HIGHER_OUT(x, val) \ + out_dword( HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), val) +#define HWIO_REO_R1_TESTBUS_HIGHER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_TESTBUS_HIGHER_ADDR(x), mask, val, HWIO_REO_R1_TESTBUS_HIGHER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_TESTBUS_HIGHER_VALUE_BMSK 0x000000ff +#define HWIO_REO_R1_TESTBUS_HIGHER_VALUE_SHFT 0x0 + +//// Register REO_R1_SM_STATES_IX_0 //// + +#define HWIO_REO_R1_SM_STATES_IX_0_ADDR(x) (x+0x00002054) +#define HWIO_REO_R1_SM_STATES_IX_0_PHYS(x) (x+0x00002054) +#define HWIO_REO_R1_SM_STATES_IX_0_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_0_SHFT 0 +#define HWIO_REO_R1_SM_STATES_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), HWIO_REO_R1_SM_STATES_IX_0_RMSK) +#define HWIO_REO_R1_SM_STATES_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), mask) +#define HWIO_REO_R1_SM_STATES_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), val) +#define HWIO_REO_R1_SM_STATES_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_SM_STATES_IX_0_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_0_SM_STATE_SHFT 0x0 + +//// Register REO_R1_SM_STATES_IX_1 //// + +#define HWIO_REO_R1_SM_STATES_IX_1_ADDR(x) (x+0x00002058) +#define HWIO_REO_R1_SM_STATES_IX_1_PHYS(x) (x+0x00002058) +#define HWIO_REO_R1_SM_STATES_IX_1_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_1_SHFT 0 +#define HWIO_REO_R1_SM_STATES_IX_1_IN(x) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), HWIO_REO_R1_SM_STATES_IX_1_RMSK) +#define HWIO_REO_R1_SM_STATES_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), mask) +#define HWIO_REO_R1_SM_STATES_IX_1_OUT(x, val) \ + out_dword( HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), val) +#define HWIO_REO_R1_SM_STATES_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_1_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_SM_STATES_IX_1_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_1_SM_STATE_SHFT 0x0 + +//// Register REO_R1_SM_STATES_IX_2 //// + +#define HWIO_REO_R1_SM_STATES_IX_2_ADDR(x) (x+0x0000205c) +#define HWIO_REO_R1_SM_STATES_IX_2_PHYS(x) (x+0x0000205c) +#define HWIO_REO_R1_SM_STATES_IX_2_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_2_SHFT 0 +#define HWIO_REO_R1_SM_STATES_IX_2_IN(x) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), HWIO_REO_R1_SM_STATES_IX_2_RMSK) +#define HWIO_REO_R1_SM_STATES_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), mask) +#define HWIO_REO_R1_SM_STATES_IX_2_OUT(x, val) \ + out_dword( HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), val) +#define HWIO_REO_R1_SM_STATES_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_2_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_SM_STATES_IX_2_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_2_SM_STATE_SHFT 0x0 + +//// Register REO_R1_SM_STATES_IX_3 //// + +#define HWIO_REO_R1_SM_STATES_IX_3_ADDR(x) (x+0x00002060) +#define HWIO_REO_R1_SM_STATES_IX_3_PHYS(x) (x+0x00002060) +#define HWIO_REO_R1_SM_STATES_IX_3_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_3_SHFT 0 +#define HWIO_REO_R1_SM_STATES_IX_3_IN(x) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), HWIO_REO_R1_SM_STATES_IX_3_RMSK) +#define HWIO_REO_R1_SM_STATES_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), mask) +#define HWIO_REO_R1_SM_STATES_IX_3_OUT(x, val) \ + out_dword( HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), val) +#define HWIO_REO_R1_SM_STATES_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_3_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_SM_STATES_IX_3_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_3_SM_STATE_SHFT 0x0 + +//// Register REO_R1_SM_STATES_IX_4 //// + +#define HWIO_REO_R1_SM_STATES_IX_4_ADDR(x) (x+0x00002064) +#define HWIO_REO_R1_SM_STATES_IX_4_PHYS(x) (x+0x00002064) +#define HWIO_REO_R1_SM_STATES_IX_4_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_4_SHFT 0 +#define HWIO_REO_R1_SM_STATES_IX_4_IN(x) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), HWIO_REO_R1_SM_STATES_IX_4_RMSK) +#define HWIO_REO_R1_SM_STATES_IX_4_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), mask) +#define HWIO_REO_R1_SM_STATES_IX_4_OUT(x, val) \ + out_dword( HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), val) +#define HWIO_REO_R1_SM_STATES_IX_4_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_4_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_4_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_SM_STATES_IX_4_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_4_SM_STATE_SHFT 0x0 + +//// Register REO_R1_SM_STATES_IX_5 //// + +#define HWIO_REO_R1_SM_STATES_IX_5_ADDR(x) (x+0x00002068) +#define HWIO_REO_R1_SM_STATES_IX_5_PHYS(x) (x+0x00002068) +#define HWIO_REO_R1_SM_STATES_IX_5_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_5_SHFT 0 +#define HWIO_REO_R1_SM_STATES_IX_5_IN(x) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), HWIO_REO_R1_SM_STATES_IX_5_RMSK) +#define HWIO_REO_R1_SM_STATES_IX_5_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), mask) +#define HWIO_REO_R1_SM_STATES_IX_5_OUT(x, val) \ + out_dword( HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), val) +#define HWIO_REO_R1_SM_STATES_IX_5_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_5_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_5_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_SM_STATES_IX_5_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_5_SM_STATE_SHFT 0x0 + +//// Register REO_R1_SM_STATES_IX_6 //// + +#define HWIO_REO_R1_SM_STATES_IX_6_ADDR(x) (x+0x0000206c) +#define HWIO_REO_R1_SM_STATES_IX_6_PHYS(x) (x+0x0000206c) +#define HWIO_REO_R1_SM_STATES_IX_6_RMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_6_SHFT 0 +#define HWIO_REO_R1_SM_STATES_IX_6_IN(x) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), HWIO_REO_R1_SM_STATES_IX_6_RMSK) +#define HWIO_REO_R1_SM_STATES_IX_6_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), mask) +#define HWIO_REO_R1_SM_STATES_IX_6_OUT(x, val) \ + out_dword( HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), val) +#define HWIO_REO_R1_SM_STATES_IX_6_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_SM_STATES_IX_6_ADDR(x), mask, val, HWIO_REO_R1_SM_STATES_IX_6_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_SM_STATES_IX_6_SM_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_SM_STATES_IX_6_SM_STATE_SHFT 0x0 + +//// Register REO_R1_IDLE_STATES_IX_0 //// + +#define HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x) (x+0x00002070) +#define HWIO_REO_R1_IDLE_STATES_IX_0_PHYS(x) (x+0x00002070) +#define HWIO_REO_R1_IDLE_STATES_IX_0_RMSK 0xffffffff +#define HWIO_REO_R1_IDLE_STATES_IX_0_SHFT 0 +#define HWIO_REO_R1_IDLE_STATES_IX_0_IN(x) \ + in_dword_masked ( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), HWIO_REO_R1_IDLE_STATES_IX_0_RMSK) +#define HWIO_REO_R1_IDLE_STATES_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), mask) +#define HWIO_REO_R1_IDLE_STATES_IX_0_OUT(x, val) \ + out_dword( HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), val) +#define HWIO_REO_R1_IDLE_STATES_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_IDLE_STATES_IX_0_ADDR(x), mask, val, HWIO_REO_R1_IDLE_STATES_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_IDLE_STATES_IX_0_IDLE_STATE_BMSK 0xffffffff +#define HWIO_REO_R1_IDLE_STATES_IX_0_IDLE_STATE_SHFT 0x0 + +//// Register REO_R1_INVALID_APB_ACCESS //// + +#define HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x) (x+0x00002074) +#define HWIO_REO_R1_INVALID_APB_ACCESS_PHYS(x) (x+0x00002074) +#define HWIO_REO_R1_INVALID_APB_ACCESS_RMSK 0x0007ffff +#define HWIO_REO_R1_INVALID_APB_ACCESS_SHFT 0 +#define HWIO_REO_R1_INVALID_APB_ACCESS_IN(x) \ + in_dword_masked ( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), HWIO_REO_R1_INVALID_APB_ACCESS_RMSK) +#define HWIO_REO_R1_INVALID_APB_ACCESS_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), mask) +#define HWIO_REO_R1_INVALID_APB_ACCESS_OUT(x, val) \ + out_dword( HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), val) +#define HWIO_REO_R1_INVALID_APB_ACCESS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R1_INVALID_APB_ACCESS_ADDR(x), mask, val, HWIO_REO_R1_INVALID_APB_ACCESS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_TYPE_BMSK 0x00060000 +#define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_TYPE_SHFT 0x11 + +#define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_ADDR_BMSK 0x0001ffff +#define HWIO_REO_R1_INVALID_APB_ACCESS_ERR_ADDR_SHFT 0x0 + +//// Register REO_R2_RXDMA2REO0_RING_HP //// + +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x) (x+0x00003000) +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_PHYS(x) (x+0x00003000) +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_SHFT 0 +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), HWIO_REO_R2_RXDMA2REO0_RING_HP_RMSK) +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO0_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO0_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_RXDMA2REO0_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_RXDMA2REO0_RING_TP //// + +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x) (x+0x00003004) +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_PHYS(x) (x+0x00003004) +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_SHFT 0 +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), HWIO_REO_R2_RXDMA2REO0_RING_TP_RMSK) +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_RXDMA2REO0_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_RXDMA2REO0_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_RXDMA2REO0_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_WBM2REO_LINK_RING_HP //// + +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x) (x+0x00003008) +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_PHYS(x) (x+0x00003008) +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_SHFT 0 +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), HWIO_REO_R2_WBM2REO_LINK_RING_HP_RMSK) +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_WBM2REO_LINK_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_WBM2REO_LINK_RING_TP //// + +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x) (x+0x0000300c) +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_PHYS(x) (x+0x0000300c) +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_SHFT 0 +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), HWIO_REO_R2_WBM2REO_LINK_RING_TP_RMSK) +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_WBM2REO_LINK_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_REO_CMD_RING_HP //// + +#define HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x) (x+0x00003010) +#define HWIO_REO_R2_REO_CMD_RING_HP_PHYS(x) (x+0x00003010) +#define HWIO_REO_R2_REO_CMD_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO_CMD_RING_HP_SHFT 0 +#define HWIO_REO_R2_REO_CMD_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), HWIO_REO_R2_REO_CMD_RING_HP_RMSK) +#define HWIO_REO_R2_REO_CMD_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_REO_CMD_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_REO_CMD_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO_CMD_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_CMD_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO_CMD_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO_CMD_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_REO_CMD_RING_TP //// + +#define HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x) (x+0x00003014) +#define HWIO_REO_R2_REO_CMD_RING_TP_PHYS(x) (x+0x00003014) +#define HWIO_REO_R2_REO_CMD_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO_CMD_RING_TP_SHFT 0 +#define HWIO_REO_R2_REO_CMD_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), HWIO_REO_R2_REO_CMD_RING_TP_RMSK) +#define HWIO_REO_R2_REO_CMD_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_REO_CMD_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_REO_CMD_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO_CMD_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_CMD_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO_CMD_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO_CMD_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_SW2REO_RING_HP //// + +#define HWIO_REO_R2_SW2REO_RING_HP_ADDR(x) (x+0x00003018) +#define HWIO_REO_R2_SW2REO_RING_HP_PHYS(x) (x+0x00003018) +#define HWIO_REO_R2_SW2REO_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_SW2REO_RING_HP_SHFT 0 +#define HWIO_REO_R2_SW2REO_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), HWIO_REO_R2_SW2REO_RING_HP_RMSK) +#define HWIO_REO_R2_SW2REO_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_SW2REO_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_SW2REO_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_SW2REO_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_SW2REO_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_SW2REO_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_SW2REO_RING_TP //// + +#define HWIO_REO_R2_SW2REO_RING_TP_ADDR(x) (x+0x0000301c) +#define HWIO_REO_R2_SW2REO_RING_TP_PHYS(x) (x+0x0000301c) +#define HWIO_REO_R2_SW2REO_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_SW2REO_RING_TP_SHFT 0 +#define HWIO_REO_R2_SW2REO_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), HWIO_REO_R2_SW2REO_RING_TP_RMSK) +#define HWIO_REO_R2_SW2REO_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_SW2REO_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_SW2REO_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_SW2REO_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_SW2REO_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_SW2REO_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_SW2REO1_RING_HP //// + +#define HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x) (x+0x00003020) +#define HWIO_REO_R2_SW2REO1_RING_HP_PHYS(x) (x+0x00003020) +#define HWIO_REO_R2_SW2REO1_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_SW2REO1_RING_HP_SHFT 0 +#define HWIO_REO_R2_SW2REO1_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x), HWIO_REO_R2_SW2REO1_RING_HP_RMSK) +#define HWIO_REO_R2_SW2REO1_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_SW2REO1_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_SW2REO1_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_SW2REO1_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO1_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_SW2REO1_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_SW2REO1_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_SW2REO1_RING_TP //// + +#define HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x) (x+0x00003024) +#define HWIO_REO_R2_SW2REO1_RING_TP_PHYS(x) (x+0x00003024) +#define HWIO_REO_R2_SW2REO1_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_SW2REO1_RING_TP_SHFT 0 +#define HWIO_REO_R2_SW2REO1_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x), HWIO_REO_R2_SW2REO1_RING_TP_RMSK) +#define HWIO_REO_R2_SW2REO1_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_SW2REO1_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_SW2REO1_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_SW2REO1_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_SW2REO1_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_SW2REO1_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_SW2REO1_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_REO2SW1_RING_HP //// + +#define HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x) (x+0x00003028) +#define HWIO_REO_R2_REO2SW1_RING_HP_PHYS(x) (x+0x00003028) +#define HWIO_REO_R2_REO2SW1_RING_HP_RMSK 0x000fffff +#define HWIO_REO_R2_REO2SW1_RING_HP_SHFT 0 +#define HWIO_REO_R2_REO2SW1_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW1_RING_HP_RMSK) +#define HWIO_REO_R2_REO2SW1_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_REO2SW1_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_REO2SW1_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW1_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW1_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2SW1_RING_HP_HEAD_PTR_BMSK 0x000fffff +#define HWIO_REO_R2_REO2SW1_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_REO2SW1_RING_TP //// + +#define HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x) (x+0x0000302c) +#define HWIO_REO_R2_REO2SW1_RING_TP_PHYS(x) (x+0x0000302c) +#define HWIO_REO_R2_REO2SW1_RING_TP_RMSK 0x000fffff +#define HWIO_REO_R2_REO2SW1_RING_TP_SHFT 0 +#define HWIO_REO_R2_REO2SW1_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW1_RING_TP_RMSK) +#define HWIO_REO_R2_REO2SW1_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_REO2SW1_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_REO2SW1_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW1_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW1_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2SW1_RING_TP_TAIL_PTR_BMSK 0x000fffff +#define HWIO_REO_R2_REO2SW1_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_REO2SW2_RING_HP //// + +#define HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x) (x+0x00003030) +#define HWIO_REO_R2_REO2SW2_RING_HP_PHYS(x) (x+0x00003030) +#define HWIO_REO_R2_REO2SW2_RING_HP_RMSK 0x000fffff +#define HWIO_REO_R2_REO2SW2_RING_HP_SHFT 0 +#define HWIO_REO_R2_REO2SW2_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW2_RING_HP_RMSK) +#define HWIO_REO_R2_REO2SW2_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_REO2SW2_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_REO2SW2_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW2_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW2_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2SW2_RING_HP_HEAD_PTR_BMSK 0x000fffff +#define HWIO_REO_R2_REO2SW2_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_REO2SW2_RING_TP //// + +#define HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x) (x+0x00003034) +#define HWIO_REO_R2_REO2SW2_RING_TP_PHYS(x) (x+0x00003034) +#define HWIO_REO_R2_REO2SW2_RING_TP_RMSK 0x000fffff +#define HWIO_REO_R2_REO2SW2_RING_TP_SHFT 0 +#define HWIO_REO_R2_REO2SW2_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW2_RING_TP_RMSK) +#define HWIO_REO_R2_REO2SW2_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_REO2SW2_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_REO2SW2_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW2_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW2_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2SW2_RING_TP_TAIL_PTR_BMSK 0x000fffff +#define HWIO_REO_R2_REO2SW2_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_REO2SW3_RING_HP //// + +#define HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x) (x+0x00003038) +#define HWIO_REO_R2_REO2SW3_RING_HP_PHYS(x) (x+0x00003038) +#define HWIO_REO_R2_REO2SW3_RING_HP_RMSK 0x000fffff +#define HWIO_REO_R2_REO2SW3_RING_HP_SHFT 0 +#define HWIO_REO_R2_REO2SW3_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW3_RING_HP_RMSK) +#define HWIO_REO_R2_REO2SW3_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_REO2SW3_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_REO2SW3_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW3_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW3_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2SW3_RING_HP_HEAD_PTR_BMSK 0x000fffff +#define HWIO_REO_R2_REO2SW3_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_REO2SW3_RING_TP //// + +#define HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x) (x+0x0000303c) +#define HWIO_REO_R2_REO2SW3_RING_TP_PHYS(x) (x+0x0000303c) +#define HWIO_REO_R2_REO2SW3_RING_TP_RMSK 0x000fffff +#define HWIO_REO_R2_REO2SW3_RING_TP_SHFT 0 +#define HWIO_REO_R2_REO2SW3_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW3_RING_TP_RMSK) +#define HWIO_REO_R2_REO2SW3_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_REO2SW3_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_REO2SW3_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW3_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW3_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2SW3_RING_TP_TAIL_PTR_BMSK 0x000fffff +#define HWIO_REO_R2_REO2SW3_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_REO2SW4_RING_HP //// + +#define HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x) (x+0x00003040) +#define HWIO_REO_R2_REO2SW4_RING_HP_PHYS(x) (x+0x00003040) +#define HWIO_REO_R2_REO2SW4_RING_HP_RMSK 0x000fffff +#define HWIO_REO_R2_REO2SW4_RING_HP_SHFT 0 +#define HWIO_REO_R2_REO2SW4_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW4_RING_HP_RMSK) +#define HWIO_REO_R2_REO2SW4_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_REO2SW4_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_REO2SW4_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW4_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW4_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2SW4_RING_HP_HEAD_PTR_BMSK 0x000fffff +#define HWIO_REO_R2_REO2SW4_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_REO2SW4_RING_TP //// + +#define HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x) (x+0x00003044) +#define HWIO_REO_R2_REO2SW4_RING_TP_PHYS(x) (x+0x00003044) +#define HWIO_REO_R2_REO2SW4_RING_TP_RMSK 0x000fffff +#define HWIO_REO_R2_REO2SW4_RING_TP_SHFT 0 +#define HWIO_REO_R2_REO2SW4_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW4_RING_TP_RMSK) +#define HWIO_REO_R2_REO2SW4_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_REO2SW4_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_REO2SW4_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW4_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW4_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2SW4_RING_TP_TAIL_PTR_BMSK 0x000fffff +#define HWIO_REO_R2_REO2SW4_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_REO2SW5_RING_HP //// + +#define HWIO_REO_R2_REO2SW5_RING_HP_ADDR(x) (x+0x00003048) +#define HWIO_REO_R2_REO2SW5_RING_HP_PHYS(x) (x+0x00003048) +#define HWIO_REO_R2_REO2SW5_RING_HP_RMSK 0x000fffff +#define HWIO_REO_R2_REO2SW5_RING_HP_SHFT 0 +#define HWIO_REO_R2_REO2SW5_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2SW5_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW5_RING_HP_RMSK) +#define HWIO_REO_R2_REO2SW5_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2SW5_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_REO2SW5_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2SW5_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_REO2SW5_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW5_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW5_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2SW5_RING_HP_HEAD_PTR_BMSK 0x000fffff +#define HWIO_REO_R2_REO2SW5_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_REO2SW5_RING_TP //// + +#define HWIO_REO_R2_REO2SW5_RING_TP_ADDR(x) (x+0x0000304c) +#define HWIO_REO_R2_REO2SW5_RING_TP_PHYS(x) (x+0x0000304c) +#define HWIO_REO_R2_REO2SW5_RING_TP_RMSK 0x000fffff +#define HWIO_REO_R2_REO2SW5_RING_TP_SHFT 0 +#define HWIO_REO_R2_REO2SW5_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2SW5_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW5_RING_TP_RMSK) +#define HWIO_REO_R2_REO2SW5_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2SW5_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_REO2SW5_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2SW5_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_REO2SW5_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW5_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW5_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2SW5_RING_TP_TAIL_PTR_BMSK 0x000fffff +#define HWIO_REO_R2_REO2SW5_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_REO2SW6_RING_HP //// + +#define HWIO_REO_R2_REO2SW6_RING_HP_ADDR(x) (x+0x00003050) +#define HWIO_REO_R2_REO2SW6_RING_HP_PHYS(x) (x+0x00003050) +#define HWIO_REO_R2_REO2SW6_RING_HP_RMSK 0x000fffff +#define HWIO_REO_R2_REO2SW6_RING_HP_SHFT 0 +#define HWIO_REO_R2_REO2SW6_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2SW6_RING_HP_ADDR(x), HWIO_REO_R2_REO2SW6_RING_HP_RMSK) +#define HWIO_REO_R2_REO2SW6_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2SW6_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_REO2SW6_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2SW6_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_REO2SW6_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW6_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW6_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2SW6_RING_HP_HEAD_PTR_BMSK 0x000fffff +#define HWIO_REO_R2_REO2SW6_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_REO2SW6_RING_TP //// + +#define HWIO_REO_R2_REO2SW6_RING_TP_ADDR(x) (x+0x00003054) +#define HWIO_REO_R2_REO2SW6_RING_TP_PHYS(x) (x+0x00003054) +#define HWIO_REO_R2_REO2SW6_RING_TP_RMSK 0x000fffff +#define HWIO_REO_R2_REO2SW6_RING_TP_SHFT 0 +#define HWIO_REO_R2_REO2SW6_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2SW6_RING_TP_ADDR(x), HWIO_REO_R2_REO2SW6_RING_TP_RMSK) +#define HWIO_REO_R2_REO2SW6_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2SW6_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_REO2SW6_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2SW6_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_REO2SW6_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2SW6_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2SW6_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2SW6_RING_TP_TAIL_PTR_BMSK 0x000fffff +#define HWIO_REO_R2_REO2SW6_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_REO2TCL_RING_HP //// + +#define HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x) (x+0x00003058) +#define HWIO_REO_R2_REO2TCL_RING_HP_PHYS(x) (x+0x00003058) +#define HWIO_REO_R2_REO2TCL_RING_HP_RMSK 0x000fffff +#define HWIO_REO_R2_REO2TCL_RING_HP_SHFT 0 +#define HWIO_REO_R2_REO2TCL_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), HWIO_REO_R2_REO2TCL_RING_HP_RMSK) +#define HWIO_REO_R2_REO2TCL_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_REO2TCL_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_REO2TCL_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2TCL_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2TCL_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2TCL_RING_HP_HEAD_PTR_BMSK 0x000fffff +#define HWIO_REO_R2_REO2TCL_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_REO2TCL_RING_TP //// + +#define HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x) (x+0x0000305c) +#define HWIO_REO_R2_REO2TCL_RING_TP_PHYS(x) (x+0x0000305c) +#define HWIO_REO_R2_REO2TCL_RING_TP_RMSK 0x000fffff +#define HWIO_REO_R2_REO2TCL_RING_TP_SHFT 0 +#define HWIO_REO_R2_REO2TCL_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), HWIO_REO_R2_REO2TCL_RING_TP_RMSK) +#define HWIO_REO_R2_REO2TCL_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_REO2TCL_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_REO2TCL_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2TCL_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2TCL_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2TCL_RING_TP_TAIL_PTR_BMSK 0x000fffff +#define HWIO_REO_R2_REO2TCL_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_REO2FW_RING_HP //// + +#define HWIO_REO_R2_REO2FW_RING_HP_ADDR(x) (x+0x00003060) +#define HWIO_REO_R2_REO2FW_RING_HP_PHYS(x) (x+0x00003060) +#define HWIO_REO_R2_REO2FW_RING_HP_RMSK 0x000fffff +#define HWIO_REO_R2_REO2FW_RING_HP_SHFT 0 +#define HWIO_REO_R2_REO2FW_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), HWIO_REO_R2_REO2FW_RING_HP_RMSK) +#define HWIO_REO_R2_REO2FW_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_REO2FW_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_REO2FW_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2FW_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO2FW_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2FW_RING_HP_HEAD_PTR_BMSK 0x000fffff +#define HWIO_REO_R2_REO2FW_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_REO2FW_RING_TP //// + +#define HWIO_REO_R2_REO2FW_RING_TP_ADDR(x) (x+0x00003064) +#define HWIO_REO_R2_REO2FW_RING_TP_PHYS(x) (x+0x00003064) +#define HWIO_REO_R2_REO2FW_RING_TP_RMSK 0x000fffff +#define HWIO_REO_R2_REO2FW_RING_TP_SHFT 0 +#define HWIO_REO_R2_REO2FW_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), HWIO_REO_R2_REO2FW_RING_TP_RMSK) +#define HWIO_REO_R2_REO2FW_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_REO2FW_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_REO2FW_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO2FW_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO2FW_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO2FW_RING_TP_TAIL_PTR_BMSK 0x000fffff +#define HWIO_REO_R2_REO2FW_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_REO_RELEASE_RING_HP //// + +#define HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x) (x+0x00003068) +#define HWIO_REO_R2_REO_RELEASE_RING_HP_PHYS(x) (x+0x00003068) +#define HWIO_REO_R2_REO_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO_RELEASE_RING_HP_SHFT 0 +#define HWIO_REO_R2_REO_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), HWIO_REO_R2_REO_RELEASE_RING_HP_RMSK) +#define HWIO_REO_R2_REO_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_REO_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_REO_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_REO_RELEASE_RING_TP //// + +#define HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x) (x+0x0000306c) +#define HWIO_REO_R2_REO_RELEASE_RING_TP_PHYS(x) (x+0x0000306c) +#define HWIO_REO_R2_REO_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO_RELEASE_RING_TP_SHFT 0 +#define HWIO_REO_R2_REO_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), HWIO_REO_R2_REO_RELEASE_RING_TP_RMSK) +#define HWIO_REO_R2_REO_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_REO_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_REO_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register REO_R2_REO_STATUS_RING_HP //// + +#define HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x) (x+0x00003070) +#define HWIO_REO_R2_REO_STATUS_RING_HP_PHYS(x) (x+0x00003070) +#define HWIO_REO_R2_REO_STATUS_RING_HP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO_STATUS_RING_HP_SHFT 0 +#define HWIO_REO_R2_REO_STATUS_RING_HP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), HWIO_REO_R2_REO_STATUS_RING_HP_RMSK) +#define HWIO_REO_R2_REO_STATUS_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), mask) +#define HWIO_REO_R2_REO_STATUS_RING_HP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), val) +#define HWIO_REO_R2_REO_STATUS_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(x), mask, val, HWIO_REO_R2_REO_STATUS_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO_STATUS_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO_STATUS_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register REO_R2_REO_STATUS_RING_TP //// + +#define HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x) (x+0x00003074) +#define HWIO_REO_R2_REO_STATUS_RING_TP_PHYS(x) (x+0x00003074) +#define HWIO_REO_R2_REO_STATUS_RING_TP_RMSK 0x0000ffff +#define HWIO_REO_R2_REO_STATUS_RING_TP_SHFT 0 +#define HWIO_REO_R2_REO_STATUS_RING_TP_IN(x) \ + in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), HWIO_REO_R2_REO_STATUS_RING_TP_RMSK) +#define HWIO_REO_R2_REO_STATUS_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), mask) +#define HWIO_REO_R2_REO_STATUS_RING_TP_OUT(x, val) \ + out_dword( HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), val) +#define HWIO_REO_R2_REO_STATUS_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_REO_R2_REO_STATUS_RING_TP_ADDR(x), mask, val, HWIO_REO_R2_REO_STATUS_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_REO_R2_REO_STATUS_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_REO_R2_REO_STATUS_RING_TP_TAIL_PTR_SHFT 0x0 + + +#endif + diff --git a/drivers/staging/fw-api/hw/qca6750/v1/reo_unblock_cache.h b/drivers/staging/fw-api/hw/qca6750/v1/reo_unblock_cache.h new file mode 100644 index 000000000000..e78764b30607 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/reo_unblock_cache.h @@ -0,0 +1,319 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _REO_UNBLOCK_CACHE_H_ +#define _REO_UNBLOCK_CACHE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 struct uniform_reo_cmd_header cmd_header; +// 1 unblock_type[0], cache_block_resource_index[2:1], reserved_1a[31:3] +// 2 reserved_2a[31:0] +// 3 reserved_3a[31:0] +// 4 reserved_4a[31:0] +// 5 reserved_5a[31:0] +// 6 reserved_6a[31:0] +// 7 reserved_7a[31:0] +// 8 reserved_8a[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE 9 + +struct reo_unblock_cache { + struct uniform_reo_cmd_header cmd_header; + uint32_t unblock_type : 1, //[0] + cache_block_resource_index : 2, //[2:1] + reserved_1a : 29; //[31:3] + uint32_t reserved_2a : 32; //[31:0] + uint32_t reserved_3a : 32; //[31:0] + uint32_t reserved_4a : 32; //[31:0] + uint32_t reserved_5a : 32; //[31:0] + uint32_t reserved_6a : 32; //[31:0] + uint32_t reserved_7a : 32; //[31:0] + uint32_t reserved_8a : 32; //[31:0] +}; + +/* + +struct uniform_reo_cmd_header cmd_header + + Consumer: REO + + Producer: SW + + + + Details for command execution tracking purposes. + +unblock_type + + Unblock type + + + + Unblock a block + resource, whose index is given in field + 'cache_block_resource_index'. + + If the indicated blocking resource is not in use (=> not + blocking an address at the moment), the command status will + indicate an error. + + + + The entire cache usage is + unblocked. + + If the entire cache is not in a blocked mode at the + moment this command is received, the command status will + indicate an error. + + Note that unlocking the entire cache has no changes to + the current settings of the blocking resource settings + + + + + +cache_block_resource_index + + Field not valid when field Unblock_type is set to + unblock_cache. + + + + Indicates which of the four blocking resources in REO + should be released from blocking a (descriptor) address. + + + +reserved_1a + + + +reserved_2a + + + +reserved_3a + + + +reserved_4a + + + +reserved_5a + + + +reserved_6a + + + +reserved_7a + + + +reserved_8a + + +*/ + + + /* EXTERNAL REFERENCE : struct uniform_reo_cmd_header cmd_header */ + + +/* Description REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_CMD_NUMBER + + Consumer: REO/SW/DEBUG + + Producer: SW + + + + This number can be used by SW to track, identify and + link the created commands with the command statusses + + + + + + +*/ +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +/* Description REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED + + Consumer: REO + + Producer: SW + + + + REO does not need to generate a status + TLV for the execution of this command + + REO shall generate a status TLV + for the execution of this command + + + + +*/ +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +/* Description REO_UNBLOCK_CACHE_0_CMD_HEADER_RESERVED_0A + + +*/ +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_UNBLOCK_CACHE_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +/* Description REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE + + Unblock type + + + + Unblock a block + resource, whose index is given in field + 'cache_block_resource_index'. + + If the indicated blocking resource is not in use (=> not + blocking an address at the moment), the command status will + indicate an error. + + + + The entire cache usage is + unblocked. + + If the entire cache is not in a blocked mode at the + moment this command is received, the command status will + indicate an error. + + Note that unlocking the entire cache has no changes to + the current settings of the blocking resource settings + + + + +*/ +#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_LSB 0 +#define REO_UNBLOCK_CACHE_1_UNBLOCK_TYPE_MASK 0x00000001 + +/* Description REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX + + Field not valid when field Unblock_type is set to + unblock_cache. + + + + Indicates which of the four blocking resources in REO + should be released from blocking a (descriptor) address. + + +*/ +#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_LSB 1 +#define REO_UNBLOCK_CACHE_1_CACHE_BLOCK_RESOURCE_INDEX_MASK 0x00000006 + +/* Description REO_UNBLOCK_CACHE_1_RESERVED_1A + + +*/ +#define REO_UNBLOCK_CACHE_1_RESERVED_1A_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_1_RESERVED_1A_LSB 3 +#define REO_UNBLOCK_CACHE_1_RESERVED_1A_MASK 0xfffffff8 + +/* Description REO_UNBLOCK_CACHE_2_RESERVED_2A + + +*/ +#define REO_UNBLOCK_CACHE_2_RESERVED_2A_OFFSET 0x00000008 +#define REO_UNBLOCK_CACHE_2_RESERVED_2A_LSB 0 +#define REO_UNBLOCK_CACHE_2_RESERVED_2A_MASK 0xffffffff + +/* Description REO_UNBLOCK_CACHE_3_RESERVED_3A + + +*/ +#define REO_UNBLOCK_CACHE_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_UNBLOCK_CACHE_3_RESERVED_3A_LSB 0 +#define REO_UNBLOCK_CACHE_3_RESERVED_3A_MASK 0xffffffff + +/* Description REO_UNBLOCK_CACHE_4_RESERVED_4A + + +*/ +#define REO_UNBLOCK_CACHE_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_UNBLOCK_CACHE_4_RESERVED_4A_LSB 0 +#define REO_UNBLOCK_CACHE_4_RESERVED_4A_MASK 0xffffffff + +/* Description REO_UNBLOCK_CACHE_5_RESERVED_5A + + +*/ +#define REO_UNBLOCK_CACHE_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_UNBLOCK_CACHE_5_RESERVED_5A_LSB 0 +#define REO_UNBLOCK_CACHE_5_RESERVED_5A_MASK 0xffffffff + +/* Description REO_UNBLOCK_CACHE_6_RESERVED_6A + + +*/ +#define REO_UNBLOCK_CACHE_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_UNBLOCK_CACHE_6_RESERVED_6A_LSB 0 +#define REO_UNBLOCK_CACHE_6_RESERVED_6A_MASK 0xffffffff + +/* Description REO_UNBLOCK_CACHE_7_RESERVED_7A + + +*/ +#define REO_UNBLOCK_CACHE_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_UNBLOCK_CACHE_7_RESERVED_7A_LSB 0 +#define REO_UNBLOCK_CACHE_7_RESERVED_7A_MASK 0xffffffff + +/* Description REO_UNBLOCK_CACHE_8_RESERVED_8A + + +*/ +#define REO_UNBLOCK_CACHE_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_UNBLOCK_CACHE_8_RESERVED_8A_LSB 0 +#define REO_UNBLOCK_CACHE_8_RESERVED_8A_MASK 0xffffffff + + +#endif // _REO_UNBLOCK_CACHE_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/reo_unblock_cache_status.h b/drivers/staging/fw-api/hw/qca6750/v1/reo_unblock_cache_status.h new file mode 100644 index 000000000000..710ff6084c12 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/reo_unblock_cache_status.h @@ -0,0 +1,623 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _REO_UNBLOCK_CACHE_STATUS_H_ +#define _REO_UNBLOCK_CACHE_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct uniform_reo_status_header status_header; +// 2 error_detected[0], unblock_type[1], reserved_2a[31:2] +// 3 reserved_3a[31:0] +// 4 reserved_4a[31:0] +// 5 reserved_5a[31:0] +// 6 reserved_6a[31:0] +// 7 reserved_7a[31:0] +// 8 reserved_8a[31:0] +// 9 reserved_9a[31:0] +// 10 reserved_10a[31:0] +// 11 reserved_11a[31:0] +// 12 reserved_12a[31:0] +// 13 reserved_13a[31:0] +// 14 reserved_14a[31:0] +// 15 reserved_15a[31:0] +// 16 reserved_16a[31:0] +// 17 reserved_17a[31:0] +// 18 reserved_18a[31:0] +// 19 reserved_19a[31:0] +// 20 reserved_20a[31:0] +// 21 reserved_21a[31:0] +// 22 reserved_22a[31:0] +// 23 reserved_23a[31:0] +// 24 reserved_24a[27:0], looping_count[31:28] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_REO_UNBLOCK_CACHE_STATUS 25 + +struct reo_unblock_cache_status { + struct uniform_reo_status_header status_header; + uint32_t error_detected : 1, //[0] + unblock_type : 1, //[1] + reserved_2a : 30; //[31:2] + uint32_t reserved_3a : 32; //[31:0] + uint32_t reserved_4a : 32; //[31:0] + uint32_t reserved_5a : 32; //[31:0] + uint32_t reserved_6a : 32; //[31:0] + uint32_t reserved_7a : 32; //[31:0] + uint32_t reserved_8a : 32; //[31:0] + uint32_t reserved_9a : 32; //[31:0] + uint32_t reserved_10a : 32; //[31:0] + uint32_t reserved_11a : 32; //[31:0] + uint32_t reserved_12a : 32; //[31:0] + uint32_t reserved_13a : 32; //[31:0] + uint32_t reserved_14a : 32; //[31:0] + uint32_t reserved_15a : 32; //[31:0] + uint32_t reserved_16a : 32; //[31:0] + uint32_t reserved_17a : 32; //[31:0] + uint32_t reserved_18a : 32; //[31:0] + uint32_t reserved_19a : 32; //[31:0] + uint32_t reserved_20a : 32; //[31:0] + uint32_t reserved_21a : 32; //[31:0] + uint32_t reserved_22a : 32; //[31:0] + uint32_t reserved_23a : 32; //[31:0] + uint32_t reserved_24a : 28, //[27:0] + looping_count : 4; //[31:28] +}; + +/* + +struct uniform_reo_status_header status_header + + Consumer: SW + + Producer: REO + + + + Details that can link this status with the original + command. It also contains info on how long REO took to + execute this command. + +error_detected + + Status for blocking resource handling + + + + 0: No error has been detected while executing this + command + + 1: The blocking resource was not in use, and therefor it + could not be 'unblocked' + +unblock_type + + Reference to the type of Unblock command type... + + + + Unblock a blocking + resource + + + + The entire cache usage is + unblock. + + + + + +reserved_2a + + + +reserved_3a + + + +reserved_4a + + + +reserved_5a + + + +reserved_6a + + + +reserved_7a + + + +reserved_8a + + + +reserved_9a + + + +reserved_10a + + + +reserved_11a + + + +reserved_12a + + + +reserved_13a + + + +reserved_14a + + + +reserved_15a + + + +reserved_16a + + + +reserved_17a + + + +reserved_18a + + + +reserved_19a + + + +reserved_20a + + + +reserved_21a + + + +reserved_22a + + + +reserved_23a + + + +reserved_24a + + + +looping_count + + A count value that indicates the number of times the + producer of entries into this Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ + + + /* EXTERNAL REFERENCE : struct uniform_reo_status_header status_header */ + + +/* Description REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER + + Consumer: SW , DEBUG + + Producer: REO + + + + The value in this field is equal to value of the + 'REO_CMD_Number' field the REO command + + + + This field helps to correlate the statuses with the REO + commands. + + + + +*/ +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +/* Description REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME + + Consumer: DEBUG + + Producer: REO + + + + The amount of time REO took to excecute the command. + Note that this time does not include the duration of the + command waiting in the command ring, before the execution + started. + + + + In us. + + + + +*/ +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +/* Description REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS + + Consumer: DEBUG + + Producer: REO + + + + Execution status of the command. + + + + Command has + successfully be executed + + Command could not be + executed as the queue or cache was blocked + + Command has encountered + problems when executing, like the queue descriptor not being + valid. None of the status fields in the entire STATUS TLV + are valid. + + Command is NOT executed + because one or more descriptors were blocked. This is SW + programming mistake. + + None of the status fields in the entire STATUS TLV are + valid. + + + + +*/ +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +/* Description REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A + + +*/ +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_UNBLOCK_CACHE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +/* Description REO_UNBLOCK_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP + + Timestamp at the moment that this status report is + written. + + + + +*/ +#define REO_UNBLOCK_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define REO_UNBLOCK_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +/* Description REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED + + Status for blocking resource handling + + + + 0: No error has been detected while executing this + command + + 1: The blocking resource was not in use, and therefor it + could not be 'unblocked' +*/ +#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_OFFSET 0x00000008 +#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_2_ERROR_DETECTED_MASK 0x00000001 + +/* Description REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE + + Reference to the type of Unblock command type... + + + + Unblock a blocking + resource + + + + The entire cache usage is + unblock. + + + + +*/ +#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_OFFSET 0x00000008 +#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_LSB 1 +#define REO_UNBLOCK_CACHE_STATUS_2_UNBLOCK_TYPE_MASK 0x00000002 + +/* Description REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A + + +*/ +#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_OFFSET 0x00000008 +#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_LSB 2 +#define REO_UNBLOCK_CACHE_STATUS_2_RESERVED_2A_MASK 0xfffffffc + +/* Description REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A + + +*/ +#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_3_RESERVED_3A_MASK 0xffffffff + +/* Description REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A + + +*/ +#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_4_RESERVED_4A_MASK 0xffffffff + +/* Description REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A + + +*/ +#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_5_RESERVED_5A_MASK 0xffffffff + +/* Description REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A + + +*/ +#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_6_RESERVED_6A_MASK 0xffffffff + +/* Description REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A + + +*/ +#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_7_RESERVED_7A_MASK 0xffffffff + +/* Description REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A + + +*/ +#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_8_RESERVED_8A_MASK 0xffffffff + +/* Description REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A + + +*/ +#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_OFFSET 0x00000024 +#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_9_RESERVED_9A_MASK 0xffffffff + +/* Description REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A + + +*/ +#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_OFFSET 0x00000028 +#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_10_RESERVED_10A_MASK 0xffffffff + +/* Description REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A + + +*/ +#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c +#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_11_RESERVED_11A_MASK 0xffffffff + +/* Description REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A + + +*/ +#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_OFFSET 0x00000030 +#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_12_RESERVED_12A_MASK 0xffffffff + +/* Description REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A + + +*/ +#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_OFFSET 0x00000034 +#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_13_RESERVED_13A_MASK 0xffffffff + +/* Description REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A + + +*/ +#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_OFFSET 0x00000038 +#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_14_RESERVED_14A_MASK 0xffffffff + +/* Description REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A + + +*/ +#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c +#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_15_RESERVED_15A_MASK 0xffffffff + +/* Description REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A + + +*/ +#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_OFFSET 0x00000040 +#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_16_RESERVED_16A_MASK 0xffffffff + +/* Description REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A + + +*/ +#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_OFFSET 0x00000044 +#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_17_RESERVED_17A_MASK 0xffffffff + +/* Description REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A + + +*/ +#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_OFFSET 0x00000048 +#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_18_RESERVED_18A_MASK 0xffffffff + +/* Description REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A + + +*/ +#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c +#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_19_RESERVED_19A_MASK 0xffffffff + +/* Description REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A + + +*/ +#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_OFFSET 0x00000050 +#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_20_RESERVED_20A_MASK 0xffffffff + +/* Description REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A + + +*/ +#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_OFFSET 0x00000054 +#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_21_RESERVED_21A_MASK 0xffffffff + +/* Description REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A + + +*/ +#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_OFFSET 0x00000058 +#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_22_RESERVED_22A_MASK 0xffffffff + +/* Description REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A + + +*/ +#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c +#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_23_RESERVED_23A_MASK 0xffffffff + +/* Description REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A + + +*/ +#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_OFFSET 0x00000060 +#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_LSB 0 +#define REO_UNBLOCK_CACHE_STATUS_24_RESERVED_24A_MASK 0x0fffffff + +/* Description REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT + + A count value that indicates the number of times the + producer of entries into this Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ +#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 +#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_LSB 28 +#define REO_UNBLOCK_CACHE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 + + +#endif // _REO_UNBLOCK_CACHE_STATUS_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/reo_update_rx_reo_queue.h b/drivers/staging/fw-api/hw/qca6750/v1/reo_update_rx_reo_queue.h new file mode 100644 index 000000000000..bf0c5d1d97a3 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/reo_update_rx_reo_queue.h @@ -0,0 +1,1677 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _REO_UPDATE_RX_REO_QUEUE_H_ +#define _REO_UPDATE_RX_REO_QUEUE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_cmd_header.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 struct uniform_reo_cmd_header cmd_header; +// 1 rx_reo_queue_desc_addr_31_0[31:0] +// 2 rx_reo_queue_desc_addr_39_32[7:0], update_receive_queue_number[8], update_vld[9], update_associated_link_descriptor_counter[10], update_disable_duplicate_detection[11], update_soft_reorder_enable[12], update_ac[13], update_bar[14], update_rty[15], update_chk_2k_mode[16], update_oor_mode[17], update_ba_window_size[18], update_pn_check_needed[19], update_pn_shall_be_even[20], update_pn_shall_be_uneven[21], update_pn_handling_enable[22], update_pn_size[23], update_ignore_ampdu_flag[24], update_svld[25], update_ssn[26], update_seq_2k_error_detected_flag[27], update_pn_error_detected_flag[28], update_pn_valid[29], update_pn[30], clear_stat_counters[31] +// 3 receive_queue_number[15:0], vld[16], associated_link_descriptor_counter[18:17], disable_duplicate_detection[19], soft_reorder_enable[20], ac[22:21], bar[23], rty[24], chk_2k_mode[25], oor_mode[26], pn_check_needed[27], pn_shall_be_even[28], pn_shall_be_uneven[29], pn_handling_enable[30], ignore_ampdu_flag[31] +// 4 ba_window_size[7:0], pn_size[9:8], svld[10], ssn[22:11], seq_2k_error_detected_flag[23], pn_error_detected_flag[24], pn_valid[25], flush_from_cache[26], reserved_4a[31:27] +// 5 pn_31_0[31:0] +// 6 pn_63_32[31:0] +// 7 pn_95_64[31:0] +// 8 pn_127_96[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE 9 + +struct reo_update_rx_reo_queue { + struct uniform_reo_cmd_header cmd_header; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0] + uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0] + update_receive_queue_number : 1, //[8] + update_vld : 1, //[9] + update_associated_link_descriptor_counter: 1, //[10] + update_disable_duplicate_detection: 1, //[11] + update_soft_reorder_enable : 1, //[12] + update_ac : 1, //[13] + update_bar : 1, //[14] + update_rty : 1, //[15] + update_chk_2k_mode : 1, //[16] + update_oor_mode : 1, //[17] + update_ba_window_size : 1, //[18] + update_pn_check_needed : 1, //[19] + update_pn_shall_be_even : 1, //[20] + update_pn_shall_be_uneven : 1, //[21] + update_pn_handling_enable : 1, //[22] + update_pn_size : 1, //[23] + update_ignore_ampdu_flag : 1, //[24] + update_svld : 1, //[25] + update_ssn : 1, //[26] + update_seq_2k_error_detected_flag: 1, //[27] + update_pn_error_detected_flag : 1, //[28] + update_pn_valid : 1, //[29] + update_pn : 1, //[30] + clear_stat_counters : 1; //[31] + uint32_t receive_queue_number : 16, //[15:0] + vld : 1, //[16] + associated_link_descriptor_counter: 2, //[18:17] + disable_duplicate_detection : 1, //[19] + soft_reorder_enable : 1, //[20] + ac : 2, //[22:21] + bar : 1, //[23] + rty : 1, //[24] + chk_2k_mode : 1, //[25] + oor_mode : 1, //[26] + pn_check_needed : 1, //[27] + pn_shall_be_even : 1, //[28] + pn_shall_be_uneven : 1, //[29] + pn_handling_enable : 1, //[30] + ignore_ampdu_flag : 1; //[31] + uint32_t ba_window_size : 8, //[7:0] + pn_size : 2, //[9:8] + svld : 1, //[10] + ssn : 12, //[22:11] + seq_2k_error_detected_flag : 1, //[23] + pn_error_detected_flag : 1, //[24] + pn_valid : 1, //[25] + flush_from_cache : 1, //[26] + reserved_4a : 5; //[31:27] + uint32_t pn_31_0 : 32; //[31:0] + uint32_t pn_63_32 : 32; //[31:0] + uint32_t pn_95_64 : 32; //[31:0] + uint32_t pn_127_96 : 32; //[31:0] +}; + +/* + +struct uniform_reo_cmd_header cmd_header + + Consumer: REO + + Producer: SW + + + + Details for command execution tracking purposes. + +rx_reo_queue_desc_addr_31_0 + + Consumer: REO + + Producer: SW + + + + Address (lower 32 bits) of the REO queue descriptor + + + +rx_reo_queue_desc_addr_39_32 + + Consumer: REO + + Producer: SW + + + + Address (upper 8 bits) of the REO queue descriptor + + + +update_receive_queue_number + + Consumer: REO + + Producer: SW + + When set, receive_queue_number from this command will be + updated in the descriptor. + + + +update_vld + + Consumer: REO + + Producer: SW + + + + When clear, REO will NOT update the VLD bit setting. For + this setting, SW MUST set the Flush_from_cache bit in this + command. + + + + When set, VLD from this command will be updated in the + descriptor. + + + +update_associated_link_descriptor_counter + + Consumer: REO + + Producer: SW + + When set, Associated_link_descriptor_counter from this + command will be updated in the descriptor. + + + +update_disable_duplicate_detection + + Consumer: REO + + Producer: SW + + When set, Disable_duplicate_detection from this command + will be updated in the descriptor. + + + +update_soft_reorder_enable + + Consumer: REO + + Producer: SW + + When set, Soft_reorder_enable from this command will be + updated in the descriptor. + + + +update_ac + + Consumer: REO + + Producer: SW + + When set, AC from this command will be updated in the + descriptor. + + + +update_bar + + Consumer: REO + + Producer: SW + + When set, BAR from this command will be updated in the + descriptor. + + + +update_rty + + Consumer: REO + + Producer: SW + + When set, RTY from this command will be updated in the + descriptor. + + + +update_chk_2k_mode + + Consumer: REO + + Producer: SW + + When set, Chk_2k_mode from this command will be updated + in the descriptor. + + + +update_oor_mode + + Consumer: REO + + Producer: SW + + When set, OOR_Mode from this command will be updated in + the descriptor. + + + +update_ba_window_size + + Consumer: REO + + Producer: SW + + When set, BA_window_size from this command will be + updated in the descriptor. + + + +update_pn_check_needed + + Consumer: REO + + Producer: SW + + When set, Pn_check_needed from this command will be + updated in the descriptor. + + + +update_pn_shall_be_even + + Consumer: REO + + Producer: SW + + When set, Pn_shall_be_even from this command will be + updated in the descriptor. + + + +update_pn_shall_be_uneven + + Consumer: REO + + Producer: SW + + When set, Pn_shall_be_uneven from this command will be + updated in the descriptor. + + + +update_pn_handling_enable + + Consumer: REO + + Producer: SW + + When set, Pn_handling_enable from this command will be + updated in the descriptor. + + + +update_pn_size + + Consumer: REO + + Producer: SW + + When set, Pn_size from this command will be updated in + the descriptor. + + + +update_ignore_ampdu_flag + + Consumer: REO + + Producer: SW + + When set, Ignore_ampdu_flag from this command will be + updated in the descriptor. + + + +update_svld + + Consumer: REO + + Producer: SW + + When set, Svld from this command will be updated in the + descriptor. + + + +update_ssn + + Consumer: REO + + Producer: SW + + When set, SSN from this command will be updated in the + descriptor. + + + +update_seq_2k_error_detected_flag + + Consumer: REO + + Producer: SW + + When set, Seq_2k_error_detected_flag from this command + will be updated in the descriptor. + + + +update_pn_error_detected_flag + + Consumer: REO + + Producer: SW + + When set, pn_error_detected_flag from this command will + be updated in the descriptor. + + + +update_pn_valid + + Consumer: REO + + Producer: SW + + When set, pn_valid from this command will be updated in + the descriptor. + + + +update_pn + + Consumer: REO + + Producer: SW + + When set, all pn_... fields from this command will be + updated in the descriptor. + + + +clear_stat_counters + + Consumer: REO + + Producer: SW + + When set, REO will clear (=> set to 0) the following + stat counters in the REO_QUEUE_STRUCT + + + + Last_rx_enqueue_TimeStamp + + Last_rx_dequeue_Timestamp + + Rx_bitmap (not a counter, but bitmap is cleared) + + Timeout_count + + Forward_due_to_bar_count + + Duplicate_count + + Frames_in_order_count + + BAR_received_count + + MPDU_Frames_processed_count + + MSDU_Frames_processed_count + + Total_processed_byte_count + + Late_receive_MPDU_count + + window_jump_2k + + Hole_count + + + + + +receive_queue_number + + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + + +vld + + Field only valid when Update_VLD is set + + + + For Update_VLD set and VLD clear, SW MUST set the + Flush_from_cache bit in this command. + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + + +associated_link_descriptor_counter + + Field only valid when + Update_Associated_link_descriptor_counter is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + + +disable_duplicate_detection + + Field only valid when Update_Disable_duplicate_detection + is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + + +soft_reorder_enable + + Field only valid when Update_Soft_reorder_enable is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + + +ac + + Field only valid when Update_AC is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + + +bar + + Field only valid when Update_BAR is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + + +rty + + Field only valid when Update_RTY is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + + +chk_2k_mode + + Field only valid when Update_Chk_2k_Mode is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + + +oor_mode + + Field only valid when Update_OOR_Mode is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + + +pn_check_needed + + Field only valid when Update_Pn_check_needed is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + + +pn_shall_be_even + + Field only valid when Update_Pn_shall_be_even is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + + +pn_shall_be_uneven + + Field only valid when Update_Pn_shall_be_uneven is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + + +pn_handling_enable + + Field only valid when Update_Pn_handling_enable is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + + +ignore_ampdu_flag + + Field only valid when Update_Ignore_ampdu_flag is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + + +ba_window_size + + Field only valid when Update_BA_window_size is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + + +pn_size + + Field only valid when Update_Pn_size is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + + + + + + + + + + + + +svld + + Field only valid when Update_Svld is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + + +ssn + + Field only valid when Update_SSN is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + + +seq_2k_error_detected_flag + + Field only valid when Update_Seq_2k_error_detected_flag + is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + + +pn_error_detected_flag + + Field only valid when Update_pn_error_detected_flag is + set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + + +pn_valid + + Field only valid when Update_pn_valid is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + + +flush_from_cache + + When set, REO shall, after finishing the execution of + this command, flush the related descriptor from the cache. + + + +reserved_4a + + + +pn_31_0 + + Field only valid when Update_Pn is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + + +pn_63_32 + + Field only valid when Update_pn is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + + +pn_95_64 + + Field only valid when Update_pn is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + + +pn_127_96 + + Field only valid when Update_pn is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + +*/ + + + /* EXTERNAL REFERENCE : struct uniform_reo_cmd_header cmd_header */ + + +/* Description REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER + + Consumer: REO/SW/DEBUG + + Producer: SW + + + + This number can be used by SW to track, identify and + link the created commands with the command statusses + + + + + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_CMD_NUMBER_MASK 0x0000ffff + +/* Description REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED + + Consumer: REO + + Producer: SW + + + + REO does not need to generate a status + TLV for the execution of this command + + REO shall generate a status TLV + for the execution of this command + + + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_REO_STATUS_REQUIRED_MASK 0x00010000 + +/* Description REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_RESERVED_0A + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_RESERVED_0A_LSB 17 +#define REO_UPDATE_RX_REO_QUEUE_0_CMD_HEADER_RESERVED_0A_MASK 0xfffe0000 + +/* Description REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0 + + Consumer: REO + + Producer: SW + + + + Address (lower 32 bits) of the REO queue descriptor + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 +#define REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_1_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +/* Description REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32 + + Consumer: REO + + Producer: SW + + + + Address (upper 8 bits) of the REO queue descriptor + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_2_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER + + Consumer: REO + + Producer: SW + + When set, receive_queue_number from this command will be + updated in the descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER_LSB 8 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RECEIVE_QUEUE_NUMBER_MASK 0x00000100 + +/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD + + Consumer: REO + + Producer: SW + + + + When clear, REO will NOT update the VLD bit setting. For + this setting, SW MUST set the Flush_from_cache bit in this + command. + + + + When set, VLD from this command will be updated in the + descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD_LSB 9 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_VLD_MASK 0x00000200 + +/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER + + Consumer: REO + + Producer: SW + + When set, Associated_link_descriptor_counter from this + command will be updated in the descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 10 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000400 + +/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION + + Consumer: REO + + Producer: SW + + When set, Disable_duplicate_detection from this command + will be updated in the descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION_LSB 11 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_DISABLE_DUPLICATE_DETECTION_MASK 0x00000800 + +/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE + + Consumer: REO + + Producer: SW + + When set, Soft_reorder_enable from this command will be + updated in the descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE_LSB 12 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SOFT_REORDER_ENABLE_MASK 0x00001000 + +/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC + + Consumer: REO + + Producer: SW + + When set, AC from this command will be updated in the + descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC_LSB 13 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_AC_MASK 0x00002000 + +/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR + + Consumer: REO + + Producer: SW + + When set, BAR from this command will be updated in the + descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR_LSB 14 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BAR_MASK 0x00004000 + +/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY + + Consumer: REO + + Producer: SW + + When set, RTY from this command will be updated in the + descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY_LSB 15 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_RTY_MASK 0x00008000 + +/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE + + Consumer: REO + + Producer: SW + + When set, Chk_2k_mode from this command will be updated + in the descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_CHK_2K_MODE_MASK 0x00010000 + +/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE + + Consumer: REO + + Producer: SW + + When set, OOR_Mode from this command will be updated in + the descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE_LSB 17 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_OOR_MODE_MASK 0x00020000 + +/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE + + Consumer: REO + + Producer: SW + + When set, BA_window_size from this command will be + updated in the descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE_LSB 18 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_BA_WINDOW_SIZE_MASK 0x00040000 + +/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED + + Consumer: REO + + Producer: SW + + When set, Pn_check_needed from this command will be + updated in the descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED_LSB 19 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_CHECK_NEEDED_MASK 0x00080000 + +/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN + + Consumer: REO + + Producer: SW + + When set, Pn_shall_be_even from this command will be + updated in the descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN_LSB 20 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_EVEN_MASK 0x00100000 + +/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN + + Consumer: REO + + Producer: SW + + When set, Pn_shall_be_uneven from this command will be + updated in the descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN_LSB 21 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SHALL_BE_UNEVEN_MASK 0x00200000 + +/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE + + Consumer: REO + + Producer: SW + + When set, Pn_handling_enable from this command will be + updated in the descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE_LSB 22 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_HANDLING_ENABLE_MASK 0x00400000 + +/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE + + Consumer: REO + + Producer: SW + + When set, Pn_size from this command will be updated in + the descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE_LSB 23 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_SIZE_MASK 0x00800000 + +/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG + + Consumer: REO + + Producer: SW + + When set, Ignore_ampdu_flag from this command will be + updated in the descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG_LSB 24 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_IGNORE_AMPDU_FLAG_MASK 0x01000000 + +/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD + + Consumer: REO + + Producer: SW + + When set, Svld from this command will be updated in the + descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD_LSB 25 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SVLD_MASK 0x02000000 + +/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN + + Consumer: REO + + Producer: SW + + When set, SSN from this command will be updated in the + descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SSN_MASK 0x04000000 + +/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG + + Consumer: REO + + Producer: SW + + When set, Seq_2k_error_detected_flag from this command + will be updated in the descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_LSB 27 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x08000000 + +/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG + + Consumer: REO + + Producer: SW + + When set, pn_error_detected_flag from this command will + be updated in the descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_ERROR_DETECTED_FLAG_MASK 0x10000000 + +/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID + + Consumer: REO + + Producer: SW + + When set, pn_valid from this command will be updated in + the descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID_LSB 29 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_VALID_MASK 0x20000000 + +/* Description REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN + + Consumer: REO + + Producer: SW + + When set, all pn_... fields from this command will be + updated in the descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_LSB 30 +#define REO_UPDATE_RX_REO_QUEUE_2_UPDATE_PN_MASK 0x40000000 + +/* Description REO_UPDATE_RX_REO_QUEUE_2_CLEAR_STAT_COUNTERS + + Consumer: REO + + Producer: SW + + When set, REO will clear (=> set to 0) the following + stat counters in the REO_QUEUE_STRUCT + + + + Last_rx_enqueue_TimeStamp + + Last_rx_dequeue_Timestamp + + Rx_bitmap (not a counter, but bitmap is cleared) + + Timeout_count + + Forward_due_to_bar_count + + Duplicate_count + + Frames_in_order_count + + BAR_received_count + + MPDU_Frames_processed_count + + MSDU_Frames_processed_count + + Total_processed_byte_count + + Late_receive_MPDU_count + + window_jump_2k + + Hole_count + + + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_2_CLEAR_STAT_COUNTERS_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_2_CLEAR_STAT_COUNTERS_LSB 31 +#define REO_UPDATE_RX_REO_QUEUE_2_CLEAR_STAT_COUNTERS_MASK 0x80000000 + +/* Description REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER + + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_3_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff + +/* Description REO_UPDATE_RX_REO_QUEUE_3_VLD + + Field only valid when Update_VLD is set + + + + For Update_VLD set and VLD clear, SW MUST set the + Flush_from_cache bit in this command. + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_3_VLD_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_VLD_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_3_VLD_MASK 0x00010000 + +/* Description REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER + + Field only valid when + Update_Associated_link_descriptor_counter is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 17 +#define REO_UPDATE_RX_REO_QUEUE_3_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00060000 + +/* Description REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION + + Field only valid when Update_Disable_duplicate_detection + is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION_LSB 19 +#define REO_UPDATE_RX_REO_QUEUE_3_DISABLE_DUPLICATE_DETECTION_MASK 0x00080000 + +/* Description REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE + + Field only valid when Update_Soft_reorder_enable is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE_LSB 20 +#define REO_UPDATE_RX_REO_QUEUE_3_SOFT_REORDER_ENABLE_MASK 0x00100000 + +/* Description REO_UPDATE_RX_REO_QUEUE_3_AC + + Field only valid when Update_AC is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_3_AC_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_AC_LSB 21 +#define REO_UPDATE_RX_REO_QUEUE_3_AC_MASK 0x00600000 + +/* Description REO_UPDATE_RX_REO_QUEUE_3_BAR + + Field only valid when Update_BAR is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_3_BAR_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_BAR_LSB 23 +#define REO_UPDATE_RX_REO_QUEUE_3_BAR_MASK 0x00800000 + +/* Description REO_UPDATE_RX_REO_QUEUE_3_RTY + + Field only valid when Update_RTY is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_3_RTY_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_RTY_LSB 24 +#define REO_UPDATE_RX_REO_QUEUE_3_RTY_MASK 0x01000000 + +/* Description REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE + + Field only valid when Update_Chk_2k_Mode is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE_LSB 25 +#define REO_UPDATE_RX_REO_QUEUE_3_CHK_2K_MODE_MASK 0x02000000 + +/* Description REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE + + Field only valid when Update_OOR_Mode is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_3_OOR_MODE_MASK 0x04000000 + +/* Description REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED + + Field only valid when Update_Pn_check_needed is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED_LSB 27 +#define REO_UPDATE_RX_REO_QUEUE_3_PN_CHECK_NEEDED_MASK 0x08000000 + +/* Description REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN + + Field only valid when Update_Pn_shall_be_even is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_EVEN_MASK 0x10000000 + +/* Description REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN + + Field only valid when Update_Pn_shall_be_uneven is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN_LSB 29 +#define REO_UPDATE_RX_REO_QUEUE_3_PN_SHALL_BE_UNEVEN_MASK 0x20000000 + +/* Description REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE + + Field only valid when Update_Pn_handling_enable is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE_LSB 30 +#define REO_UPDATE_RX_REO_QUEUE_3_PN_HANDLING_ENABLE_MASK 0x40000000 + +/* Description REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG + + Field only valid when Update_Ignore_ampdu_flag is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG_LSB 31 +#define REO_UPDATE_RX_REO_QUEUE_3_IGNORE_AMPDU_FLAG_MASK 0x80000000 + +/* Description REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE + + Field only valid when Update_BA_window_size is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_4_BA_WINDOW_SIZE_MASK 0x000000ff + +/* Description REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE + + Field only valid when Update_Pn_size is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + + + + + + + + + + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE_LSB 8 +#define REO_UPDATE_RX_REO_QUEUE_4_PN_SIZE_MASK 0x00000300 + +/* Description REO_UPDATE_RX_REO_QUEUE_4_SVLD + + Field only valid when Update_Svld is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_4_SVLD_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_SVLD_LSB 10 +#define REO_UPDATE_RX_REO_QUEUE_4_SVLD_MASK 0x00000400 + +/* Description REO_UPDATE_RX_REO_QUEUE_4_SSN + + Field only valid when Update_SSN is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_4_SSN_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_SSN_LSB 11 +#define REO_UPDATE_RX_REO_QUEUE_4_SSN_MASK 0x007ff800 + +/* Description REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG + + Field only valid when Update_Seq_2k_error_detected_flag + is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG_LSB 23 +#define REO_UPDATE_RX_REO_QUEUE_4_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00800000 + +/* Description REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG + + Field only valid when Update_pn_error_detected_flag is + set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG_LSB 24 +#define REO_UPDATE_RX_REO_QUEUE_4_PN_ERROR_DETECTED_FLAG_MASK 0x01000000 + +/* Description REO_UPDATE_RX_REO_QUEUE_4_PN_VALID + + Field only valid when Update_pn_valid is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_4_PN_VALID_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_PN_VALID_LSB 25 +#define REO_UPDATE_RX_REO_QUEUE_4_PN_VALID_MASK 0x02000000 + +/* Description REO_UPDATE_RX_REO_QUEUE_4_FLUSH_FROM_CACHE + + When set, REO shall, after finishing the execution of + this command, flush the related descriptor from the cache. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_4_FLUSH_FROM_CACHE_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_FLUSH_FROM_CACHE_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_4_FLUSH_FROM_CACHE_MASK 0x04000000 + +/* Description REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A_LSB 27 +#define REO_UPDATE_RX_REO_QUEUE_4_RESERVED_4A_MASK 0xf8000000 + +/* Description REO_UPDATE_RX_REO_QUEUE_5_PN_31_0 + + Field only valid when Update_Pn is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_5_PN_31_0_OFFSET 0x00000014 +#define REO_UPDATE_RX_REO_QUEUE_5_PN_31_0_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_5_PN_31_0_MASK 0xffffffff + +/* Description REO_UPDATE_RX_REO_QUEUE_6_PN_63_32 + + Field only valid when Update_pn is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_6_PN_63_32_OFFSET 0x00000018 +#define REO_UPDATE_RX_REO_QUEUE_6_PN_63_32_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_6_PN_63_32_MASK 0xffffffff + +/* Description REO_UPDATE_RX_REO_QUEUE_7_PN_95_64 + + Field only valid when Update_pn is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_7_PN_95_64_OFFSET 0x0000001c +#define REO_UPDATE_RX_REO_QUEUE_7_PN_95_64_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_7_PN_95_64_MASK 0xffffffff + +/* Description REO_UPDATE_RX_REO_QUEUE_8_PN_127_96 + + Field only valid when Update_pn is set + + + + Field value to be copied over into the RX_REO_QUEUE + descriptor. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_8_PN_127_96_OFFSET 0x00000020 +#define REO_UPDATE_RX_REO_QUEUE_8_PN_127_96_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_8_PN_127_96_MASK 0xffffffff + + +#endif // _REO_UPDATE_RX_REO_QUEUE_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/reo_update_rx_reo_queue_status.h b/drivers/staging/fw-api/hw/qca6750/v1/reo_update_rx_reo_queue_status.h new file mode 100644 index 000000000000..7296eaa6066a --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/reo_update_rx_reo_queue_status.h @@ -0,0 +1,553 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ +#define _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_reo_status_header.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct uniform_reo_status_header status_header; +// 2 reserved_2a[31:0] +// 3 reserved_3a[31:0] +// 4 reserved_4a[31:0] +// 5 reserved_5a[31:0] +// 6 reserved_6a[31:0] +// 7 reserved_7a[31:0] +// 8 reserved_8a[31:0] +// 9 reserved_9a[31:0] +// 10 reserved_10a[31:0] +// 11 reserved_11a[31:0] +// 12 reserved_12a[31:0] +// 13 reserved_13a[31:0] +// 14 reserved_14a[31:0] +// 15 reserved_15a[31:0] +// 16 reserved_16a[31:0] +// 17 reserved_17a[31:0] +// 18 reserved_18a[31:0] +// 19 reserved_19a[31:0] +// 20 reserved_20a[31:0] +// 21 reserved_21a[31:0] +// 22 reserved_22a[31:0] +// 23 reserved_23a[31:0] +// 24 reserved_24a[27:0], looping_count[31:28] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_REO_UPDATE_RX_REO_QUEUE_STATUS 25 + +struct reo_update_rx_reo_queue_status { + struct uniform_reo_status_header status_header; + uint32_t reserved_2a : 32; //[31:0] + uint32_t reserved_3a : 32; //[31:0] + uint32_t reserved_4a : 32; //[31:0] + uint32_t reserved_5a : 32; //[31:0] + uint32_t reserved_6a : 32; //[31:0] + uint32_t reserved_7a : 32; //[31:0] + uint32_t reserved_8a : 32; //[31:0] + uint32_t reserved_9a : 32; //[31:0] + uint32_t reserved_10a : 32; //[31:0] + uint32_t reserved_11a : 32; //[31:0] + uint32_t reserved_12a : 32; //[31:0] + uint32_t reserved_13a : 32; //[31:0] + uint32_t reserved_14a : 32; //[31:0] + uint32_t reserved_15a : 32; //[31:0] + uint32_t reserved_16a : 32; //[31:0] + uint32_t reserved_17a : 32; //[31:0] + uint32_t reserved_18a : 32; //[31:0] + uint32_t reserved_19a : 32; //[31:0] + uint32_t reserved_20a : 32; //[31:0] + uint32_t reserved_21a : 32; //[31:0] + uint32_t reserved_22a : 32; //[31:0] + uint32_t reserved_23a : 32; //[31:0] + uint32_t reserved_24a : 28, //[27:0] + looping_count : 4; //[31:28] +}; + +/* + +struct uniform_reo_status_header status_header + + Consumer: SW + + Producer: REO + + + + Details that can link this status with the original + command. It also contains info on how long REO took to + execute this command. + +reserved_2a + + + +reserved_3a + + + +reserved_4a + + + +reserved_5a + + + +reserved_6a + + + +reserved_7a + + + +reserved_8a + + + +reserved_9a + + + +reserved_10a + + + +reserved_11a + + + +reserved_12a + + + +reserved_13a + + + +reserved_14a + + + +reserved_15a + + + +reserved_16a + + + +reserved_17a + + + +reserved_18a + + + +reserved_19a + + + +reserved_20a + + + +reserved_21a + + + +reserved_22a + + + +reserved_23a + + + +reserved_24a + + + +looping_count + + A count value that indicates the number of times the + producer of entries into this Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ + + + /* EXTERNAL REFERENCE : struct uniform_reo_status_header status_header */ + + +/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER + + Consumer: SW , DEBUG + + Producer: REO + + + + The value in this field is equal to value of the + 'REO_CMD_Number' field the REO command + + + + This field helps to correlate the statuses with the REO + commands. + + + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_STATUS_NUMBER_MASK 0x0000ffff + +/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME + + Consumer: DEBUG + + Producer: REO + + + + The amount of time REO took to excecute the command. + Note that this time does not include the duration of the + command waiting in the command ring, before the execution + started. + + + + In us. + + + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_LSB 16 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS + + Consumer: DEBUG + + Producer: REO + + + + Execution status of the command. + + + + Command has + successfully be executed + + Command could not be + executed as the queue or cache was blocked + + Command has encountered + problems when executing, like the queue descriptor not being + valid. None of the status fields in the entire STATUS TLV + are valid. + + Command is NOT executed + because one or more descriptors were blocked. This is SW + programming mistake. + + None of the status fields in the entire STATUS TLV are + valid. + + + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_LSB 26 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_0_STATUS_HEADER_RESERVED_0A_MASK 0xf0000000 + +/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP + + Timestamp at the moment that this status report is + written. + + + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_OFFSET 0x00000004 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_1_STATUS_HEADER_TIMESTAMP_MASK 0xffffffff + +/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_OFFSET 0x00000008 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_2_RESERVED_2A_MASK 0xffffffff + +/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_OFFSET 0x0000000c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_3_RESERVED_3A_MASK 0xffffffff + +/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_OFFSET 0x00000010 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_4_RESERVED_4A_MASK 0xffffffff + +/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_OFFSET 0x00000014 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_5_RESERVED_5A_MASK 0xffffffff + +/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_OFFSET 0x00000018 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_6_RESERVED_6A_MASK 0xffffffff + +/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_OFFSET 0x0000001c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_7_RESERVED_7A_MASK 0xffffffff + +/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_OFFSET 0x00000020 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_8_RESERVED_8A_MASK 0xffffffff + +/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_OFFSET 0x00000024 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_9_RESERVED_9A_MASK 0xffffffff + +/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_OFFSET 0x00000028 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_10_RESERVED_10A_MASK 0xffffffff + +/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_OFFSET 0x0000002c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_11_RESERVED_11A_MASK 0xffffffff + +/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_OFFSET 0x00000030 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_12_RESERVED_12A_MASK 0xffffffff + +/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_OFFSET 0x00000034 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_13_RESERVED_13A_MASK 0xffffffff + +/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_OFFSET 0x00000038 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_14_RESERVED_14A_MASK 0xffffffff + +/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_OFFSET 0x0000003c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_15_RESERVED_15A_MASK 0xffffffff + +/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_OFFSET 0x00000040 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_16_RESERVED_16A_MASK 0xffffffff + +/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_OFFSET 0x00000044 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_17_RESERVED_17A_MASK 0xffffffff + +/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_OFFSET 0x00000048 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_18_RESERVED_18A_MASK 0xffffffff + +/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_OFFSET 0x0000004c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_19_RESERVED_19A_MASK 0xffffffff + +/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_OFFSET 0x00000050 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_20_RESERVED_20A_MASK 0xffffffff + +/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_OFFSET 0x00000054 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_21_RESERVED_21A_MASK 0xffffffff + +/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_OFFSET 0x00000058 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_22_RESERVED_22A_MASK 0xffffffff + +/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_OFFSET 0x0000005c +#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_23_RESERVED_23A_MASK 0xffffffff + +/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_OFFSET 0x00000060 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_LSB 0 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_RESERVED_24A_MASK 0x0fffffff + +/* Description REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT + + A count value that indicates the number of times the + producer of entries into this Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ +#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_OFFSET 0x00000060 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_LSB 28 +#define REO_UPDATE_RX_REO_QUEUE_STATUS_24_LOOPING_COUNT_MASK 0xf0000000 + + +#endif // _REO_UPDATE_RX_REO_QUEUE_STATUS_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/rx_attention.h b/drivers/staging/fw-api/hw/qca6750/v1/rx_attention.h new file mode 100644 index 000000000000..509866cf554d --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/rx_attention.h @@ -0,0 +1,1185 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_ATTENTION_H_ +#define _RX_ATTENTION_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16] +// 1 first_mpdu[0], reserved_1a[1], mcast_bcast[2], ast_index_not_found[3], ast_index_timeout[4], power_mgmt[5], non_qos[6], null_data[7], mgmt_type[8], ctrl_type[9], more_data[10], eosp[11], a_msdu_error[12], fragment_flag[13], order[14], cce_match[15], overflow_err[16], msdu_length_err[17], tcp_udp_chksum_fail[18], ip_chksum_fail[19], sa_idx_invalid[20], da_idx_invalid[21], reserved_1b[22], rx_in_tx_decrypt_byp[23], encrypt_required[24], directed[25], buffer_fragment[26], mpdu_length_err[27], tkip_mic_err[28], decrypt_err[29], unencrypted_frame_err[30], fcs_err[31] +// 2 flow_idx_timeout[0], flow_idx_invalid[1], wifi_parser_error[2], amsdu_parser_error[3], sa_idx_timeout[4], da_idx_timeout[5], msdu_limit_error[6], da_is_valid[7], da_is_mcbc[8], sa_is_valid[9], decrypt_status_code[12:10], rx_bitmap_not_updated[13], reserved_2[30:14], msdu_done[31] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_ATTENTION 3 + +struct rx_attention { + uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] + sw_frame_group_id : 7, //[8:2] + reserved_0 : 7, //[15:9] + phy_ppdu_id : 16; //[31:16] + uint32_t first_mpdu : 1, //[0] + reserved_1a : 1, //[1] + mcast_bcast : 1, //[2] + ast_index_not_found : 1, //[3] + ast_index_timeout : 1, //[4] + power_mgmt : 1, //[5] + non_qos : 1, //[6] + null_data : 1, //[7] + mgmt_type : 1, //[8] + ctrl_type : 1, //[9] + more_data : 1, //[10] + eosp : 1, //[11] + a_msdu_error : 1, //[12] + fragment_flag : 1, //[13] + order : 1, //[14] + cce_match : 1, //[15] + overflow_err : 1, //[16] + msdu_length_err : 1, //[17] + tcp_udp_chksum_fail : 1, //[18] + ip_chksum_fail : 1, //[19] + sa_idx_invalid : 1, //[20] + da_idx_invalid : 1, //[21] + reserved_1b : 1, //[22] + rx_in_tx_decrypt_byp : 1, //[23] + encrypt_required : 1, //[24] + directed : 1, //[25] + buffer_fragment : 1, //[26] + mpdu_length_err : 1, //[27] + tkip_mic_err : 1, //[28] + decrypt_err : 1, //[29] + unencrypted_frame_err : 1, //[30] + fcs_err : 1; //[31] + uint32_t flow_idx_timeout : 1, //[0] + flow_idx_invalid : 1, //[1] + wifi_parser_error : 1, //[2] + amsdu_parser_error : 1, //[3] + sa_idx_timeout : 1, //[4] + da_idx_timeout : 1, //[5] + msdu_limit_error : 1, //[6] + da_is_valid : 1, //[7] + da_is_mcbc : 1, //[8] + sa_is_valid : 1, //[9] + decrypt_status_code : 3, //[12:10] + rx_bitmap_not_updated : 1, //[13] + reserved_2 : 17, //[30:14] + msdu_done : 1; //[31] +}; + +/* + +rxpcu_mpdu_filter_in_category + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + + This MPDU passed the normal + frame filter programming of rxpcu + + This MPDU did NOT pass the + regular frame filter and would have been dropped, were it + not for the frame fitting into the 'monitor_client' + category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the + rxpcu_monitor_client filter. It would have been dropped + accept that it did pass the 'monitor_other' category. + + + +sw_frame_group_id + + SW processes frames based on certain classifications. + This field indicates to what sw classification this MPDU is + mapped. + + The classification is given in priority order + + + + + + + + + + + + This includes mpdus + of type Data Null as well as QoS Data Null + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + + + + + + + +reserved_0 + + + +phy_ppdu_id + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + + +first_mpdu + + Indicates the first MSDU of the PPDU. If both + first_mpdu and last_mpdu are set in the MSDU then this is a + not an A-MPDU frame but a stand alone MPDU. Interior MPDU + in an A-MPDU shall have both first_mpdu and last_mpdu bits + set to 0. The PPDU start status will only be valid when + this bit is set. + +reserved_1a + + + +mcast_bcast + + Multicast / broadcast indicator. Only set when the MAC + address 1 bit 0 is set indicating mcast/bcast and the BSSID + matches one of the 4 BSSID registers. Only set when + first_msdu is set. + +ast_index_not_found + + Only valid when first_msdu is set. + + + + Indicates no AST matching entries within the the max + search count. + +ast_index_timeout + + Only valid when first_msdu is set. + + + + Indicates an unsuccessful search in the address seach + table due to timeout. + +power_mgmt + + Power management bit set in the 802.11 header. Only set + when first_msdu is set. + +non_qos + + Set if packet is not a non-QoS data frame. Only set + when first_msdu is set. + +null_data + + Set if frame type indicates either null data or QoS null + data format. Only set when first_msdu is set. + +mgmt_type + + Set if packet is a management packet. Only set when + first_msdu is set. + +ctrl_type + + Set if packet is a control packet. Only set when + first_msdu is set. + +more_data + + Set if more bit in frame control is set. Only set when + first_msdu is set. + +eosp + + Set if the EOSP (end of service period) bit in the QoS + control field is set. Only set when first_msdu is set. + +a_msdu_error + + Set if number of MSDUs in A-MSDU is above a threshold or + if the size of the MSDU is invalid. This receive buffer + will contain all of the remainder of the MSDUs in this MPDU + without decapsulation. + +fragment_flag + + Indicates that this is an 802.11 fragment frame. This + is set when either the more_frag bit is set in the frame + control or the fragment number is not zero. Only set when + first_msdu is set. + +order + + Set if the order bit in the frame control is set. Only + set when first_msdu is set. + +cce_match + + Indicates that this status has a corresponding MSDU that + requires FW processing. The OLE will have classification + ring mask registers which will indicate the ring(s) for + packets and descriptors which need FW attention. + +overflow_err + + RXPCU Receive FIFO ran out of space to receive the full + MPDU. Therefor this MPDU is terminated early and is thus + corrupted. + + + + This MPDU will not be ACKed. + + RXPCU might still be able to correctly receive the + following MPDUs in the PPDU if enough fifo space became + available in time + +msdu_length_err + + Indicates that the MSDU length from the 802.3 + encapsulated length field extends beyond the MPDU boundary + or if the length is less than 14 bytes. + + Merged with original other_msdu_err: Indicates that the + MSDU threshold was exceeded and thus all the rest of the + MSDUs will not be scattered and will not be decasulated but + will be DMA'ed in RAW format as a single MSDU buffer + +tcp_udp_chksum_fail + + Indicates that the computed checksum (tcp_udp_chksum in + 'RX_MSDU_END') did not match the checksum in the TCP/UDP + header. + +ip_chksum_fail + + Indicates that the computed checksum (ip_hdr_chksum in + 'RX_MSDU_END') did not match the checksum in the IP header. + +sa_idx_invalid + + Indicates no matching entry was found in the address + search table for the source MAC address. + +da_idx_invalid + + Indicates no matching entry was found in the address + search table for the destination MAC address. + +reserved_1b + + + +rx_in_tx_decrypt_byp + + Indicates that RX packet is not decrypted as Crypto is + busy with TX packet processing. + +encrypt_required + + Indicates that this data type frame is not encrypted + even if the policy for this MPDU requires encryption as + indicated in the peer entry key type. + +directed + + MPDU is a directed packet which means that the RA + matched our STA addresses. In proxySTA it means that the TA + matched an entry in our address search table with the + corresponding no_ack bit is the address search entry + cleared. + +buffer_fragment + + Indicates that at least one of the rx buffers has been + fragmented. If set the FW should look at the rx_frag_info + descriptor described below. + +mpdu_length_err + + Indicates that the MPDU was pre-maturely terminated + resulting in a truncated MPDU. Don't trust the MPDU length + field. + +tkip_mic_err + + Indicates that the MPDU Michael integrity check failed + +decrypt_err + + Indicates that the MPDU decrypt integrity check failed + or CRYPTO received an encrypted frame, but did not get a + valid corresponding key id in the peer entry. + +unencrypted_frame_err + + Copied here by RX OLE from the RX_MPDU_END TLV + +fcs_err + + Indicates that the MPDU FCS check failed + +flow_idx_timeout + + Indicates an unsuccessful flow search due to the + expiring of the search timer. + + + +flow_idx_invalid + + flow id is not valid + + + +wifi_parser_error + + Indicates that the WiFi frame has one of the following + errors + + o has less than minimum allowed bytes as per standard + + o has incomplete VLAN LLC/SNAP (only for non A-MSDUs) + + + +amsdu_parser_error + + A-MSDU could not be properly de-agregated. + + + +sa_idx_timeout + + Indicates an unsuccessful MAC source address search due + to the expiring of the search timer. + +da_idx_timeout + + Indicates an unsuccessful MAC destination address search + due to the expiring of the search timer. + +msdu_limit_error + + Indicates that the MSDU threshold was exceeded and thus + all the rest of the MSDUs will not be scattered and will not + be decasulated but will be DMA'ed in RAW format as a single + MSDU buffer + +da_is_valid + + Indicates that OLE found a valid DA entry + +da_is_mcbc + + Field Only valid if da_is_valid is set + + + + Indicates the DA address was a Multicast of Broadcast + address. + +sa_is_valid + + Indicates that OLE found a valid SA entry + +decrypt_status_code + + Field provides insight into the decryption performed + + + + Frame had protection enabled and + decrypted properly + + Frame is unprotected + and hence bypassed + + Frame has protection enabled + and could not be properly decrypted due to MIC/ICV mismatch + etc. + + Frame has protection + enabled but the key that was required to decrypt this frame + was not valid + + Frame has + protection enabled but the key that was required to decrypt + this frame was not valid + + Reserved for other indications + + + + + +rx_bitmap_not_updated + + Frame is received, but RXPCU could not update the + receive bitmap due to (temporary) fifo contraints. + + + +reserved_2 + + + +msdu_done + + If set indicates that the RX packet data, RX header + data, RX PPDU start descriptor, RX MPDU start/end + descriptor, RX MSDU start/end descriptors and RX Attention + descriptor are all valid. This bit must be in the last + octet of the descriptor. +*/ + + +/* Description RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + + This MPDU passed the normal + frame filter programming of rxpcu + + This MPDU did NOT pass the + regular frame filter and would have been dropped, were it + not for the frame fitting into the 'monitor_client' + category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the + rxpcu_monitor_client filter. It would have been dropped + accept that it did pass the 'monitor_other' category. + + +*/ +#define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_ATTENTION_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +/* Description RX_ATTENTION_0_SW_FRAME_GROUP_ID + + SW processes frames based on certain classifications. + This field indicates to what sw classification this MPDU is + mapped. + + The classification is given in priority order + + + + + + + + + + + + This includes mpdus + of type Data Null as well as QoS Data Null + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + + + + + + +*/ +#define RX_ATTENTION_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_ATTENTION_0_SW_FRAME_GROUP_ID_LSB 2 +#define RX_ATTENTION_0_SW_FRAME_GROUP_ID_MASK 0x000001fc + +/* Description RX_ATTENTION_0_RESERVED_0 + + +*/ +#define RX_ATTENTION_0_RESERVED_0_OFFSET 0x00000000 +#define RX_ATTENTION_0_RESERVED_0_LSB 9 +#define RX_ATTENTION_0_RESERVED_0_MASK 0x0000fe00 + +/* Description RX_ATTENTION_0_PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + +*/ +#define RX_ATTENTION_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_ATTENTION_0_PHY_PPDU_ID_LSB 16 +#define RX_ATTENTION_0_PHY_PPDU_ID_MASK 0xffff0000 + +/* Description RX_ATTENTION_1_FIRST_MPDU + + Indicates the first MSDU of the PPDU. If both + first_mpdu and last_mpdu are set in the MSDU then this is a + not an A-MPDU frame but a stand alone MPDU. Interior MPDU + in an A-MPDU shall have both first_mpdu and last_mpdu bits + set to 0. The PPDU start status will only be valid when + this bit is set. +*/ +#define RX_ATTENTION_1_FIRST_MPDU_OFFSET 0x00000004 +#define RX_ATTENTION_1_FIRST_MPDU_LSB 0 +#define RX_ATTENTION_1_FIRST_MPDU_MASK 0x00000001 + +/* Description RX_ATTENTION_1_RESERVED_1A + + +*/ +#define RX_ATTENTION_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_ATTENTION_1_RESERVED_1A_LSB 1 +#define RX_ATTENTION_1_RESERVED_1A_MASK 0x00000002 + +/* Description RX_ATTENTION_1_MCAST_BCAST + + Multicast / broadcast indicator. Only set when the MAC + address 1 bit 0 is set indicating mcast/bcast and the BSSID + matches one of the 4 BSSID registers. Only set when + first_msdu is set. +*/ +#define RX_ATTENTION_1_MCAST_BCAST_OFFSET 0x00000004 +#define RX_ATTENTION_1_MCAST_BCAST_LSB 2 +#define RX_ATTENTION_1_MCAST_BCAST_MASK 0x00000004 + +/* Description RX_ATTENTION_1_AST_INDEX_NOT_FOUND + + Only valid when first_msdu is set. + + + + Indicates no AST matching entries within the the max + search count. +*/ +#define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_OFFSET 0x00000004 +#define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_LSB 3 +#define RX_ATTENTION_1_AST_INDEX_NOT_FOUND_MASK 0x00000008 + +/* Description RX_ATTENTION_1_AST_INDEX_TIMEOUT + + Only valid when first_msdu is set. + + + + Indicates an unsuccessful search in the address seach + table due to timeout. +*/ +#define RX_ATTENTION_1_AST_INDEX_TIMEOUT_OFFSET 0x00000004 +#define RX_ATTENTION_1_AST_INDEX_TIMEOUT_LSB 4 +#define RX_ATTENTION_1_AST_INDEX_TIMEOUT_MASK 0x00000010 + +/* Description RX_ATTENTION_1_POWER_MGMT + + Power management bit set in the 802.11 header. Only set + when first_msdu is set. +*/ +#define RX_ATTENTION_1_POWER_MGMT_OFFSET 0x00000004 +#define RX_ATTENTION_1_POWER_MGMT_LSB 5 +#define RX_ATTENTION_1_POWER_MGMT_MASK 0x00000020 + +/* Description RX_ATTENTION_1_NON_QOS + + Set if packet is not a non-QoS data frame. Only set + when first_msdu is set. +*/ +#define RX_ATTENTION_1_NON_QOS_OFFSET 0x00000004 +#define RX_ATTENTION_1_NON_QOS_LSB 6 +#define RX_ATTENTION_1_NON_QOS_MASK 0x00000040 + +/* Description RX_ATTENTION_1_NULL_DATA + + Set if frame type indicates either null data or QoS null + data format. Only set when first_msdu is set. +*/ +#define RX_ATTENTION_1_NULL_DATA_OFFSET 0x00000004 +#define RX_ATTENTION_1_NULL_DATA_LSB 7 +#define RX_ATTENTION_1_NULL_DATA_MASK 0x00000080 + +/* Description RX_ATTENTION_1_MGMT_TYPE + + Set if packet is a management packet. Only set when + first_msdu is set. +*/ +#define RX_ATTENTION_1_MGMT_TYPE_OFFSET 0x00000004 +#define RX_ATTENTION_1_MGMT_TYPE_LSB 8 +#define RX_ATTENTION_1_MGMT_TYPE_MASK 0x00000100 + +/* Description RX_ATTENTION_1_CTRL_TYPE + + Set if packet is a control packet. Only set when + first_msdu is set. +*/ +#define RX_ATTENTION_1_CTRL_TYPE_OFFSET 0x00000004 +#define RX_ATTENTION_1_CTRL_TYPE_LSB 9 +#define RX_ATTENTION_1_CTRL_TYPE_MASK 0x00000200 + +/* Description RX_ATTENTION_1_MORE_DATA + + Set if more bit in frame control is set. Only set when + first_msdu is set. +*/ +#define RX_ATTENTION_1_MORE_DATA_OFFSET 0x00000004 +#define RX_ATTENTION_1_MORE_DATA_LSB 10 +#define RX_ATTENTION_1_MORE_DATA_MASK 0x00000400 + +/* Description RX_ATTENTION_1_EOSP + + Set if the EOSP (end of service period) bit in the QoS + control field is set. Only set when first_msdu is set. +*/ +#define RX_ATTENTION_1_EOSP_OFFSET 0x00000004 +#define RX_ATTENTION_1_EOSP_LSB 11 +#define RX_ATTENTION_1_EOSP_MASK 0x00000800 + +/* Description RX_ATTENTION_1_A_MSDU_ERROR + + Set if number of MSDUs in A-MSDU is above a threshold or + if the size of the MSDU is invalid. This receive buffer + will contain all of the remainder of the MSDUs in this MPDU + without decapsulation. +*/ +#define RX_ATTENTION_1_A_MSDU_ERROR_OFFSET 0x00000004 +#define RX_ATTENTION_1_A_MSDU_ERROR_LSB 12 +#define RX_ATTENTION_1_A_MSDU_ERROR_MASK 0x00001000 + +/* Description RX_ATTENTION_1_FRAGMENT_FLAG + + Indicates that this is an 802.11 fragment frame. This + is set when either the more_frag bit is set in the frame + control or the fragment number is not zero. Only set when + first_msdu is set. +*/ +#define RX_ATTENTION_1_FRAGMENT_FLAG_OFFSET 0x00000004 +#define RX_ATTENTION_1_FRAGMENT_FLAG_LSB 13 +#define RX_ATTENTION_1_FRAGMENT_FLAG_MASK 0x00002000 + +/* Description RX_ATTENTION_1_ORDER + + Set if the order bit in the frame control is set. Only + set when first_msdu is set. +*/ +#define RX_ATTENTION_1_ORDER_OFFSET 0x00000004 +#define RX_ATTENTION_1_ORDER_LSB 14 +#define RX_ATTENTION_1_ORDER_MASK 0x00004000 + +/* Description RX_ATTENTION_1_CCE_MATCH + + Indicates that this status has a corresponding MSDU that + requires FW processing. The OLE will have classification + ring mask registers which will indicate the ring(s) for + packets and descriptors which need FW attention. +*/ +#define RX_ATTENTION_1_CCE_MATCH_OFFSET 0x00000004 +#define RX_ATTENTION_1_CCE_MATCH_LSB 15 +#define RX_ATTENTION_1_CCE_MATCH_MASK 0x00008000 + +/* Description RX_ATTENTION_1_OVERFLOW_ERR + + RXPCU Receive FIFO ran out of space to receive the full + MPDU. Therefor this MPDU is terminated early and is thus + corrupted. + + + + This MPDU will not be ACKed. + + RXPCU might still be able to correctly receive the + following MPDUs in the PPDU if enough fifo space became + available in time +*/ +#define RX_ATTENTION_1_OVERFLOW_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_OVERFLOW_ERR_LSB 16 +#define RX_ATTENTION_1_OVERFLOW_ERR_MASK 0x00010000 + +/* Description RX_ATTENTION_1_MSDU_LENGTH_ERR + + Indicates that the MSDU length from the 802.3 + encapsulated length field extends beyond the MPDU boundary + or if the length is less than 14 bytes. + + Merged with original other_msdu_err: Indicates that the + MSDU threshold was exceeded and thus all the rest of the + MSDUs will not be scattered and will not be decasulated but + will be DMA'ed in RAW format as a single MSDU buffer +*/ +#define RX_ATTENTION_1_MSDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_MSDU_LENGTH_ERR_LSB 17 +#define RX_ATTENTION_1_MSDU_LENGTH_ERR_MASK 0x00020000 + +/* Description RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL + + Indicates that the computed checksum (tcp_udp_chksum in + 'RX_MSDU_END') did not match the checksum in the TCP/UDP + header. +*/ +#define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000004 +#define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_LSB 18 +#define RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_MASK 0x00040000 + +/* Description RX_ATTENTION_1_IP_CHKSUM_FAIL + + Indicates that the computed checksum (ip_hdr_chksum in + 'RX_MSDU_END') did not match the checksum in the IP header. +*/ +#define RX_ATTENTION_1_IP_CHKSUM_FAIL_OFFSET 0x00000004 +#define RX_ATTENTION_1_IP_CHKSUM_FAIL_LSB 19 +#define RX_ATTENTION_1_IP_CHKSUM_FAIL_MASK 0x00080000 + +/* Description RX_ATTENTION_1_SA_IDX_INVALID + + Indicates no matching entry was found in the address + search table for the source MAC address. +*/ +#define RX_ATTENTION_1_SA_IDX_INVALID_OFFSET 0x00000004 +#define RX_ATTENTION_1_SA_IDX_INVALID_LSB 20 +#define RX_ATTENTION_1_SA_IDX_INVALID_MASK 0x00100000 + +/* Description RX_ATTENTION_1_DA_IDX_INVALID + + Indicates no matching entry was found in the address + search table for the destination MAC address. +*/ +#define RX_ATTENTION_1_DA_IDX_INVALID_OFFSET 0x00000004 +#define RX_ATTENTION_1_DA_IDX_INVALID_LSB 21 +#define RX_ATTENTION_1_DA_IDX_INVALID_MASK 0x00200000 + +/* Description RX_ATTENTION_1_RESERVED_1B + + +*/ +#define RX_ATTENTION_1_RESERVED_1B_OFFSET 0x00000004 +#define RX_ATTENTION_1_RESERVED_1B_LSB 22 +#define RX_ATTENTION_1_RESERVED_1B_MASK 0x00400000 + +/* Description RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP + + Indicates that RX packet is not decrypted as Crypto is + busy with TX packet processing. +*/ +#define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004 +#define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_LSB 23 +#define RX_ATTENTION_1_RX_IN_TX_DECRYPT_BYP_MASK 0x00800000 + +/* Description RX_ATTENTION_1_ENCRYPT_REQUIRED + + Indicates that this data type frame is not encrypted + even if the policy for this MPDU requires encryption as + indicated in the peer entry key type. +*/ +#define RX_ATTENTION_1_ENCRYPT_REQUIRED_OFFSET 0x00000004 +#define RX_ATTENTION_1_ENCRYPT_REQUIRED_LSB 24 +#define RX_ATTENTION_1_ENCRYPT_REQUIRED_MASK 0x01000000 + +/* Description RX_ATTENTION_1_DIRECTED + + MPDU is a directed packet which means that the RA + matched our STA addresses. In proxySTA it means that the TA + matched an entry in our address search table with the + corresponding no_ack bit is the address search entry + cleared. +*/ +#define RX_ATTENTION_1_DIRECTED_OFFSET 0x00000004 +#define RX_ATTENTION_1_DIRECTED_LSB 25 +#define RX_ATTENTION_1_DIRECTED_MASK 0x02000000 + +/* Description RX_ATTENTION_1_BUFFER_FRAGMENT + + Indicates that at least one of the rx buffers has been + fragmented. If set the FW should look at the rx_frag_info + descriptor described below. +*/ +#define RX_ATTENTION_1_BUFFER_FRAGMENT_OFFSET 0x00000004 +#define RX_ATTENTION_1_BUFFER_FRAGMENT_LSB 26 +#define RX_ATTENTION_1_BUFFER_FRAGMENT_MASK 0x04000000 + +/* Description RX_ATTENTION_1_MPDU_LENGTH_ERR + + Indicates that the MPDU was pre-maturely terminated + resulting in a truncated MPDU. Don't trust the MPDU length + field. +*/ +#define RX_ATTENTION_1_MPDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_MPDU_LENGTH_ERR_LSB 27 +#define RX_ATTENTION_1_MPDU_LENGTH_ERR_MASK 0x08000000 + +/* Description RX_ATTENTION_1_TKIP_MIC_ERR + + Indicates that the MPDU Michael integrity check failed +*/ +#define RX_ATTENTION_1_TKIP_MIC_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_TKIP_MIC_ERR_LSB 28 +#define RX_ATTENTION_1_TKIP_MIC_ERR_MASK 0x10000000 + +/* Description RX_ATTENTION_1_DECRYPT_ERR + + Indicates that the MPDU decrypt integrity check failed + or CRYPTO received an encrypted frame, but did not get a + valid corresponding key id in the peer entry. +*/ +#define RX_ATTENTION_1_DECRYPT_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_DECRYPT_ERR_LSB 29 +#define RX_ATTENTION_1_DECRYPT_ERR_MASK 0x20000000 + +/* Description RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR + + Copied here by RX OLE from the RX_MPDU_END TLV +*/ +#define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_LSB 30 +#define RX_ATTENTION_1_UNENCRYPTED_FRAME_ERR_MASK 0x40000000 + +/* Description RX_ATTENTION_1_FCS_ERR + + Indicates that the MPDU FCS check failed +*/ +#define RX_ATTENTION_1_FCS_ERR_OFFSET 0x00000004 +#define RX_ATTENTION_1_FCS_ERR_LSB 31 +#define RX_ATTENTION_1_FCS_ERR_MASK 0x80000000 + +/* Description RX_ATTENTION_2_FLOW_IDX_TIMEOUT + + Indicates an unsuccessful flow search due to the + expiring of the search timer. + + +*/ +#define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_LSB 0 +#define RX_ATTENTION_2_FLOW_IDX_TIMEOUT_MASK 0x00000001 + +/* Description RX_ATTENTION_2_FLOW_IDX_INVALID + + flow id is not valid + + +*/ +#define RX_ATTENTION_2_FLOW_IDX_INVALID_OFFSET 0x00000008 +#define RX_ATTENTION_2_FLOW_IDX_INVALID_LSB 1 +#define RX_ATTENTION_2_FLOW_IDX_INVALID_MASK 0x00000002 + +/* Description RX_ATTENTION_2_WIFI_PARSER_ERROR + + Indicates that the WiFi frame has one of the following + errors + + o has less than minimum allowed bytes as per standard + + o has incomplete VLAN LLC/SNAP (only for non A-MSDUs) + + +*/ +#define RX_ATTENTION_2_WIFI_PARSER_ERROR_OFFSET 0x00000008 +#define RX_ATTENTION_2_WIFI_PARSER_ERROR_LSB 2 +#define RX_ATTENTION_2_WIFI_PARSER_ERROR_MASK 0x00000004 + +/* Description RX_ATTENTION_2_AMSDU_PARSER_ERROR + + A-MSDU could not be properly de-agregated. + + +*/ +#define RX_ATTENTION_2_AMSDU_PARSER_ERROR_OFFSET 0x00000008 +#define RX_ATTENTION_2_AMSDU_PARSER_ERROR_LSB 3 +#define RX_ATTENTION_2_AMSDU_PARSER_ERROR_MASK 0x00000008 + +/* Description RX_ATTENTION_2_SA_IDX_TIMEOUT + + Indicates an unsuccessful MAC source address search due + to the expiring of the search timer. +*/ +#define RX_ATTENTION_2_SA_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_ATTENTION_2_SA_IDX_TIMEOUT_LSB 4 +#define RX_ATTENTION_2_SA_IDX_TIMEOUT_MASK 0x00000010 + +/* Description RX_ATTENTION_2_DA_IDX_TIMEOUT + + Indicates an unsuccessful MAC destination address search + due to the expiring of the search timer. +*/ +#define RX_ATTENTION_2_DA_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_ATTENTION_2_DA_IDX_TIMEOUT_LSB 5 +#define RX_ATTENTION_2_DA_IDX_TIMEOUT_MASK 0x00000020 + +/* Description RX_ATTENTION_2_MSDU_LIMIT_ERROR + + Indicates that the MSDU threshold was exceeded and thus + all the rest of the MSDUs will not be scattered and will not + be decasulated but will be DMA'ed in RAW format as a single + MSDU buffer +*/ +#define RX_ATTENTION_2_MSDU_LIMIT_ERROR_OFFSET 0x00000008 +#define RX_ATTENTION_2_MSDU_LIMIT_ERROR_LSB 6 +#define RX_ATTENTION_2_MSDU_LIMIT_ERROR_MASK 0x00000040 + +/* Description RX_ATTENTION_2_DA_IS_VALID + + Indicates that OLE found a valid DA entry +*/ +#define RX_ATTENTION_2_DA_IS_VALID_OFFSET 0x00000008 +#define RX_ATTENTION_2_DA_IS_VALID_LSB 7 +#define RX_ATTENTION_2_DA_IS_VALID_MASK 0x00000080 + +/* Description RX_ATTENTION_2_DA_IS_MCBC + + Field Only valid if da_is_valid is set + + + + Indicates the DA address was a Multicast of Broadcast + address. +*/ +#define RX_ATTENTION_2_DA_IS_MCBC_OFFSET 0x00000008 +#define RX_ATTENTION_2_DA_IS_MCBC_LSB 8 +#define RX_ATTENTION_2_DA_IS_MCBC_MASK 0x00000100 + +/* Description RX_ATTENTION_2_SA_IS_VALID + + Indicates that OLE found a valid SA entry +*/ +#define RX_ATTENTION_2_SA_IS_VALID_OFFSET 0x00000008 +#define RX_ATTENTION_2_SA_IS_VALID_LSB 9 +#define RX_ATTENTION_2_SA_IS_VALID_MASK 0x00000200 + +/* Description RX_ATTENTION_2_DECRYPT_STATUS_CODE + + Field provides insight into the decryption performed + + + + Frame had protection enabled and + decrypted properly + + Frame is unprotected + and hence bypassed + + Frame has protection enabled + and could not be properly decrypted due to MIC/ICV mismatch + etc. + + Frame has protection + enabled but the key that was required to decrypt this frame + was not valid + + Frame has + protection enabled but the key that was required to decrypt + this frame was not valid + + Reserved for other indications + + + + +*/ +#define RX_ATTENTION_2_DECRYPT_STATUS_CODE_OFFSET 0x00000008 +#define RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB 10 +#define RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK 0x00001c00 + +/* Description RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED + + Frame is received, but RXPCU could not update the + receive bitmap due to (temporary) fifo contraints. + + +*/ +#define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000008 +#define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_LSB 13 +#define RX_ATTENTION_2_RX_BITMAP_NOT_UPDATED_MASK 0x00002000 + +/* Description RX_ATTENTION_2_RESERVED_2 + + +*/ +#define RX_ATTENTION_2_RESERVED_2_OFFSET 0x00000008 +#define RX_ATTENTION_2_RESERVED_2_LSB 14 +#define RX_ATTENTION_2_RESERVED_2_MASK 0x7fffc000 + +/* Description RX_ATTENTION_2_MSDU_DONE + + If set indicates that the RX packet data, RX header + data, RX PPDU start descriptor, RX MPDU start/end + descriptor, RX MSDU start/end descriptors and RX Attention + descriptor are all valid. This bit must be in the last + octet of the descriptor. +*/ +#define RX_ATTENTION_2_MSDU_DONE_OFFSET 0x00000008 +#define RX_ATTENTION_2_MSDU_DONE_LSB 31 +#define RX_ATTENTION_2_MSDU_DONE_MASK 0x80000000 + + +#endif // _RX_ATTENTION_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/rx_location_info.h b/drivers/staging/fw-api/hw/qca6750/v1/rx_location_info.h new file mode 100644 index 000000000000..b72341b4a76a --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/rx_location_info.h @@ -0,0 +1,1376 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_LOCATION_INFO_H_ +#define _RX_LOCATION_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 rtt_fac_legacy[15:0], rtt_fac_legacy_ext80[31:16] +// 1 rtt_fac_vht[15:0], rtt_fac_vht_ext80[31:16] +// 2 rtt_fac_legacy_status[0], rtt_fac_legacy_ext80_status[1], rtt_fac_vht_status[2], rtt_fac_vht_ext80_status[3], rtt_fac_sifs[15:4], rtt_fac_sifs_status[17:16], rtt_cfr_status[18], rtt_cir_status[19], rtt_channel_dump_size[30:20], rtt_hw_ifft_mode[31] +// 3 rtt_btcf_status[0], rtt_preamble_type[5:1], rtt_pkt_bw_leg[7:6], rtt_pkt_bw_vht[9:8], rtt_gi_type[11:10], rtt_mcs_rate[16:12], rtt_strongest_chain[19:17], rtt_strongest_chain_ext80[22:20], rtt_rx_chain_mask[30:23], reserved_3[31] +// 4 rx_start_ts[31:0] +// 5 rx_end_ts[31:0] +// 6 sfo_phase_pkt_start[11:0], sfo_phase_pkt_end[23:12], rtt_che_buffer_pointer_high8[31:24] +// 7 rtt_che_buffer_pointer_low32[31:0] +// 8 rtt_cfo_measurement[13:0], rtt_chan_spread[21:14], rtt_timing_backoff_sel[23:22], reserved_8[30:24], rx_location_info_valid[31] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_LOCATION_INFO 9 + +struct rx_location_info { + uint32_t rtt_fac_legacy : 16, //[15:0] + rtt_fac_legacy_ext80 : 16; //[31:16] + uint32_t rtt_fac_vht : 16, //[15:0] + rtt_fac_vht_ext80 : 16; //[31:16] + uint32_t rtt_fac_legacy_status : 1, //[0] + rtt_fac_legacy_ext80_status : 1, //[1] + rtt_fac_vht_status : 1, //[2] + rtt_fac_vht_ext80_status : 1, //[3] + rtt_fac_sifs : 12, //[15:4] + rtt_fac_sifs_status : 2, //[17:16] + rtt_cfr_status : 1, //[18] + rtt_cir_status : 1, //[19] + rtt_channel_dump_size : 11, //[30:20] + rtt_hw_ifft_mode : 1; //[31] + uint32_t rtt_btcf_status : 1, //[0] + rtt_preamble_type : 5, //[5:1] + rtt_pkt_bw_leg : 2, //[7:6] + rtt_pkt_bw_vht : 2, //[9:8] + rtt_gi_type : 2, //[11:10] + rtt_mcs_rate : 5, //[16:12] + rtt_strongest_chain : 3, //[19:17] + rtt_strongest_chain_ext80 : 3, //[22:20] + rtt_rx_chain_mask : 8, //[30:23] + reserved_3 : 1; //[31] + uint32_t rx_start_ts : 32; //[31:0] + uint32_t rx_end_ts : 32; //[31:0] + uint32_t sfo_phase_pkt_start : 12, //[11:0] + sfo_phase_pkt_end : 12, //[23:12] + rtt_che_buffer_pointer_high8 : 8; //[31:24] + uint32_t rtt_che_buffer_pointer_low32 : 32; //[31:0] + uint32_t rtt_cfo_measurement : 14, //[13:0] + rtt_chan_spread : 8, //[21:14] + rtt_timing_backoff_sel : 2, //[23:22] + reserved_8 : 7, //[30:24] + rx_location_info_valid : 1; //[31] +}; + +/* + +rtt_fac_legacy + + For 20/40/80, this field shows the RTT first arrival + correction value computed from L-LTF on the first selected + Rx chain + + + + For 80+80, this field shows the RTT first arrival + correction value computed from L-LTF on pri80 on the + selected pri80 Rx chain + + + + 16 bits, signed 12.4. 12 bits integer to cover -6.4us to + 6.4us, and 4 bits fraction to cover pri80 and 32x FAC + interpolation + + + + clock unit is 320MHz + + + +rtt_fac_legacy_ext80 + + For 20/40/80, this field shows the RTT first arrival + correction value computed from L-LTF on the second selected + Rx chain + + + + For 80+80, this field shows the RTT first arrival + correction value computed from L-LTF on ext80 on the + selected ext80 Rx chain + + + + 16 bits, signed 12.4. 12 bits integer to cover -6.4us to + 6.4us, and 4 bits fraction to cover ext80 and 32x FAC + interpolation + + + + clock unit is 320MHz + + + +rtt_fac_vht + + For 20/40/80, this field shows the RTT first arrival + correction value computed from (V)HT/HE-LTF on the first + selected Rx chain + + + + For 80+80, this field shows the RTT first arrival + correction value computed from (V)HT/HE-LTF on pri80 on the + selected pri80 Rx chain + + + + 16 bits, signed 12.4. 12 bits integer to cover -6.4us to + 6.4us, and 4 bits fraction to cover pri80 and 32x FAC + interpolation + + + + clock unit is 320MHz + + + +rtt_fac_vht_ext80 + + For 20/40/80, this field shows the RTT first arrival + correction value computed from (V)HT/HE-LTF on the second + selected Rx chain + + + + For 80+80, this field shows the RTT first arrival + correction value computed from (V)HT/HE-LTF on ext80 on the + selected ext80 Rx chain + + + + 16 bits, signed 12.4. 12 bits integer to cover -6.4us to + 6.4us, and 4 bits fraction to cover ext80 and 32x FAC + interpolation + + + + clock unit is 320MHz + + + +rtt_fac_legacy_status + + Status of rtt_fac_legacy + + + + + + + + + +rtt_fac_legacy_ext80_status + + Status of rtt_fac_legacy_ext80 + + + + + + + + + +rtt_fac_vht_status + + Status of rtt_fac_vht + + + + + + + + + +rtt_fac_vht_ext80_status + + Status of rtt_fac_vht_ext80 + + + + + + + + + +rtt_fac_sifs + + To support fine SIFS adjustment, need to provide FAC + value @ integer number of 320 MHz clock cycles to MAC.  It + is from L-LTF if it is a Legacy packet and from (V)HT/HE-LTF + if it is a (V)HT/HE packet + + + + 12 bits, signed, no fractional part + + + +rtt_fac_sifs_status + + Status of rtt_fac_sifs + + 0: not valid + + 1: valid and from L-LTF + + 2: valid and from (V)HT/HE-LTF + + 3: reserved + + + +rtt_cfr_status + + Status of channel frequency response dump + + + + + + + + + +rtt_cir_status + + Status of channel impulse response dump + + + + + + + + + +rtt_channel_dump_size + + Channel dump size.  It shows how many tones in CFR in + one chain, for example, it will show 52 for Legacy20 and 484 + for VHT160 + + + + + +rtt_hw_ifft_mode + + Indicator showing if HW IFFT mode or SW IFFT mode + + + + + + + + + +rtt_btcf_status + + Indicate if BTCF is used to capture the timestamps + + + + + + + + + +rtt_preamble_type + + Indicate preamble type + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +rtt_pkt_bw_leg + + Indicate the bandwidth of L-LTF + + + + + + + + + + + + + +rtt_pkt_bw_vht + + Indicate the bandwidth of (V)HT/HE-LTF + + + + + + + + + + + + + +rtt_gi_type + + Indicate GI (guard interval) type + + + + HE related GI. Can also be used + for HE + + HE related GI. Can also be used + for HE + + HE related GI + + HE related GI + + + +rtt_mcs_rate + + Bits 0~4 indicate MCS rate, if Legacy, + + 0: 48 Mbps, + + 1: 24 Mbps, + + 2: 12 Mbps, + + 3: 6 Mbps, + + 4: 54 Mbps, + + 5: 36 Mbps, + + 6: 18 Mbps, + + 7: 9 Mbps, + + + + if HT, 0-7: MCS0-MCS7, + + if VHT, 0-9: MCS0-MCS9, + + + + +rtt_strongest_chain + + For 20/40/80, this field shows the first selected Rx + chain that is used in HW IFFT mode + + + + For 80+80, this field shows the selected pri80 Rx chain + that is used in HW IFFT mode + + + + + + + + + + + + + + + + + + + + + +rtt_strongest_chain_ext80 + + For 20/40/80, this field shows the second selected Rx + chain that is used in HW IFFT mode + + + + For 80+80, this field shows the selected ext80 Rx chain + that is used in HW IFFT mode + + + + + + + + + + + + + + + + + + + + + +rtt_rx_chain_mask + + Rx chain mask, each bit is a Rx chain + + 0: the Rx chain is not used + + 1: the Rx chain is used + + Support up to 8 Rx chains + + + +reserved_3 + + + +rx_start_ts + + RX packet start timestamp + + + + It reports the time the first L-STF ADC sample arrived + at RX antenna + + + + clock unit is 480MHz + + + +rx_end_ts + + RX packet end timestamp + + + + It reports the time the last symbol's last ADC sample + arrived at RX antenna + + + + clock unit is 480MHz + + + +sfo_phase_pkt_start + + The phase of the SFO of the first symbol's first FFT + input sample + + + + 12 bits, signed 6.6. 6 bits integer to cover -66.7ns to + 66.7ns, and 6 bits fraction to provide a resolution of + 0.03ns + + + + clock unit is 480MHz + + + +sfo_phase_pkt_end + + The phase of the SFO of the last symbol's last FFT input + sample + + + + 12 bits, signed 6.6. 6 bits integer to cover -66.7ns to + 66.7ns, and 6 bits fraction to provide a resolution of + 0.03ns + + + + clock unit is 480MHz + + + +rtt_che_buffer_pointer_high8 + + The high 8 bits of the 40 bits pointer pointed to the + external RTT channel information buffer + + + + 8 bits + + + +rtt_che_buffer_pointer_low32 + + The low 32 bits of the 40 bits pointer pointed to the + external RTT channel information buffer + + + + 32 bits + + + +rtt_cfo_measurement + + CFO measurement. Needed for passive locationing + + + + 14 bits, signed 1.13. 13 bits fraction to provide a + resolution of 153 Hz + + + + In units of cycles/800 ns + + + +rtt_chan_spread + + Channel delay spread measurement. Needed for selecting + GI length + + + + 8 bits, unsigned. At 25 ns step. Can represent up to + 6375 ns + + + + In units of cycles @ 40 MHz + + + +rtt_timing_backoff_sel + + Indicate which timing backoff value is used + + + + + + + + + + + + + +reserved_8 + + + +rx_location_info_valid + + + + + + +*/ + + +/* Description RX_LOCATION_INFO_0_RTT_FAC_LEGACY + + For 20/40/80, this field shows the RTT first arrival + correction value computed from L-LTF on the first selected + Rx chain + + + + For 80+80, this field shows the RTT first arrival + correction value computed from L-LTF on pri80 on the + selected pri80 Rx chain + + + + 16 bits, signed 12.4. 12 bits integer to cover -6.4us to + 6.4us, and 4 bits fraction to cover pri80 and 32x FAC + interpolation + + + + clock unit is 320MHz + + +*/ +#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_OFFSET 0x00000000 +#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_LSB 0 +#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_MASK 0x0000ffff + +/* Description RX_LOCATION_INFO_0_RTT_FAC_LEGACY_EXT80 + + For 20/40/80, this field shows the RTT first arrival + correction value computed from L-LTF on the second selected + Rx chain + + + + For 80+80, this field shows the RTT first arrival + correction value computed from L-LTF on ext80 on the + selected ext80 Rx chain + + + + 16 bits, signed 12.4. 12 bits integer to cover -6.4us to + 6.4us, and 4 bits fraction to cover ext80 and 32x FAC + interpolation + + + + clock unit is 320MHz + + +*/ +#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_EXT80_OFFSET 0x00000000 +#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_EXT80_LSB 16 +#define RX_LOCATION_INFO_0_RTT_FAC_LEGACY_EXT80_MASK 0xffff0000 + +/* Description RX_LOCATION_INFO_1_RTT_FAC_VHT + + For 20/40/80, this field shows the RTT first arrival + correction value computed from (V)HT/HE-LTF on the first + selected Rx chain + + + + For 80+80, this field shows the RTT first arrival + correction value computed from (V)HT/HE-LTF on pri80 on the + selected pri80 Rx chain + + + + 16 bits, signed 12.4. 12 bits integer to cover -6.4us to + 6.4us, and 4 bits fraction to cover pri80 and 32x FAC + interpolation + + + + clock unit is 320MHz + + +*/ +#define RX_LOCATION_INFO_1_RTT_FAC_VHT_OFFSET 0x00000004 +#define RX_LOCATION_INFO_1_RTT_FAC_VHT_LSB 0 +#define RX_LOCATION_INFO_1_RTT_FAC_VHT_MASK 0x0000ffff + +/* Description RX_LOCATION_INFO_1_RTT_FAC_VHT_EXT80 + + For 20/40/80, this field shows the RTT first arrival + correction value computed from (V)HT/HE-LTF on the second + selected Rx chain + + + + For 80+80, this field shows the RTT first arrival + correction value computed from (V)HT/HE-LTF on ext80 on the + selected ext80 Rx chain + + + + 16 bits, signed 12.4. 12 bits integer to cover -6.4us to + 6.4us, and 4 bits fraction to cover ext80 and 32x FAC + interpolation + + + + clock unit is 320MHz + + +*/ +#define RX_LOCATION_INFO_1_RTT_FAC_VHT_EXT80_OFFSET 0x00000004 +#define RX_LOCATION_INFO_1_RTT_FAC_VHT_EXT80_LSB 16 +#define RX_LOCATION_INFO_1_RTT_FAC_VHT_EXT80_MASK 0xffff0000 + +/* Description RX_LOCATION_INFO_2_RTT_FAC_LEGACY_STATUS + + Status of rtt_fac_legacy + + + + + + + + +*/ +#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_STATUS_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_STATUS_LSB 0 +#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_STATUS_MASK 0x00000001 + +/* Description RX_LOCATION_INFO_2_RTT_FAC_LEGACY_EXT80_STATUS + + Status of rtt_fac_legacy_ext80 + + + + + + + + +*/ +#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_EXT80_STATUS_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_EXT80_STATUS_LSB 1 +#define RX_LOCATION_INFO_2_RTT_FAC_LEGACY_EXT80_STATUS_MASK 0x00000002 + +/* Description RX_LOCATION_INFO_2_RTT_FAC_VHT_STATUS + + Status of rtt_fac_vht + + + + + + + + +*/ +#define RX_LOCATION_INFO_2_RTT_FAC_VHT_STATUS_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_FAC_VHT_STATUS_LSB 2 +#define RX_LOCATION_INFO_2_RTT_FAC_VHT_STATUS_MASK 0x00000004 + +/* Description RX_LOCATION_INFO_2_RTT_FAC_VHT_EXT80_STATUS + + Status of rtt_fac_vht_ext80 + + + + + + + + +*/ +#define RX_LOCATION_INFO_2_RTT_FAC_VHT_EXT80_STATUS_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_FAC_VHT_EXT80_STATUS_LSB 3 +#define RX_LOCATION_INFO_2_RTT_FAC_VHT_EXT80_STATUS_MASK 0x00000008 + +/* Description RX_LOCATION_INFO_2_RTT_FAC_SIFS + + To support fine SIFS adjustment, need to provide FAC + value @ integer number of 320 MHz clock cycles to MAC.  It + is from L-LTF if it is a Legacy packet and from (V)HT/HE-LTF + if it is a (V)HT/HE packet + + + + 12 bits, signed, no fractional part + + +*/ +#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_LSB 4 +#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_MASK 0x0000fff0 + +/* Description RX_LOCATION_INFO_2_RTT_FAC_SIFS_STATUS + + Status of rtt_fac_sifs + + 0: not valid + + 1: valid and from L-LTF + + 2: valid and from (V)HT/HE-LTF + + 3: reserved + + +*/ +#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_STATUS_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_STATUS_LSB 16 +#define RX_LOCATION_INFO_2_RTT_FAC_SIFS_STATUS_MASK 0x00030000 + +/* Description RX_LOCATION_INFO_2_RTT_CFR_STATUS + + Status of channel frequency response dump + + + + + + + + +*/ +#define RX_LOCATION_INFO_2_RTT_CFR_STATUS_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_CFR_STATUS_LSB 18 +#define RX_LOCATION_INFO_2_RTT_CFR_STATUS_MASK 0x00040000 + +/* Description RX_LOCATION_INFO_2_RTT_CIR_STATUS + + Status of channel impulse response dump + + + + + + + + +*/ +#define RX_LOCATION_INFO_2_RTT_CIR_STATUS_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_CIR_STATUS_LSB 19 +#define RX_LOCATION_INFO_2_RTT_CIR_STATUS_MASK 0x00080000 + +/* Description RX_LOCATION_INFO_2_RTT_CHANNEL_DUMP_SIZE + + Channel dump size.  It shows how many tones in CFR in + one chain, for example, it will show 52 for Legacy20 and 484 + for VHT160 + + + + +*/ +#define RX_LOCATION_INFO_2_RTT_CHANNEL_DUMP_SIZE_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_CHANNEL_DUMP_SIZE_LSB 20 +#define RX_LOCATION_INFO_2_RTT_CHANNEL_DUMP_SIZE_MASK 0x7ff00000 + +/* Description RX_LOCATION_INFO_2_RTT_HW_IFFT_MODE + + Indicator showing if HW IFFT mode or SW IFFT mode + + + + + + + + +*/ +#define RX_LOCATION_INFO_2_RTT_HW_IFFT_MODE_OFFSET 0x00000008 +#define RX_LOCATION_INFO_2_RTT_HW_IFFT_MODE_LSB 31 +#define RX_LOCATION_INFO_2_RTT_HW_IFFT_MODE_MASK 0x80000000 + +/* Description RX_LOCATION_INFO_3_RTT_BTCF_STATUS + + Indicate if BTCF is used to capture the timestamps + + + + + + + + +*/ +#define RX_LOCATION_INFO_3_RTT_BTCF_STATUS_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_BTCF_STATUS_LSB 0 +#define RX_LOCATION_INFO_3_RTT_BTCF_STATUS_MASK 0x00000001 + +/* Description RX_LOCATION_INFO_3_RTT_PREAMBLE_TYPE + + Indicate preamble type + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +*/ +#define RX_LOCATION_INFO_3_RTT_PREAMBLE_TYPE_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_PREAMBLE_TYPE_LSB 1 +#define RX_LOCATION_INFO_3_RTT_PREAMBLE_TYPE_MASK 0x0000003e + +/* Description RX_LOCATION_INFO_3_RTT_PKT_BW_LEG + + Indicate the bandwidth of L-LTF + + + + + + + + + + + + +*/ +#define RX_LOCATION_INFO_3_RTT_PKT_BW_LEG_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_PKT_BW_LEG_LSB 6 +#define RX_LOCATION_INFO_3_RTT_PKT_BW_LEG_MASK 0x000000c0 + +/* Description RX_LOCATION_INFO_3_RTT_PKT_BW_VHT + + Indicate the bandwidth of (V)HT/HE-LTF + + + + + + + + + + + + +*/ +#define RX_LOCATION_INFO_3_RTT_PKT_BW_VHT_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_PKT_BW_VHT_LSB 8 +#define RX_LOCATION_INFO_3_RTT_PKT_BW_VHT_MASK 0x00000300 + +/* Description RX_LOCATION_INFO_3_RTT_GI_TYPE + + Indicate GI (guard interval) type + + + + HE related GI. Can also be used + for HE + + HE related GI. Can also be used + for HE + + HE related GI + + HE related GI + + +*/ +#define RX_LOCATION_INFO_3_RTT_GI_TYPE_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_GI_TYPE_LSB 10 +#define RX_LOCATION_INFO_3_RTT_GI_TYPE_MASK 0x00000c00 + +/* Description RX_LOCATION_INFO_3_RTT_MCS_RATE + + Bits 0~4 indicate MCS rate, if Legacy, + + 0: 48 Mbps, + + 1: 24 Mbps, + + 2: 12 Mbps, + + 3: 6 Mbps, + + 4: 54 Mbps, + + 5: 36 Mbps, + + 6: 18 Mbps, + + 7: 9 Mbps, + + + + if HT, 0-7: MCS0-MCS7, + + if VHT, 0-9: MCS0-MCS9, + + + +*/ +#define RX_LOCATION_INFO_3_RTT_MCS_RATE_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_MCS_RATE_LSB 12 +#define RX_LOCATION_INFO_3_RTT_MCS_RATE_MASK 0x0001f000 + +/* Description RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN + + For 20/40/80, this field shows the first selected Rx + chain that is used in HW IFFT mode + + + + For 80+80, this field shows the selected pri80 Rx chain + that is used in HW IFFT mode + + + + + + + + + + + + + + + + + + + + +*/ +#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_LSB 17 +#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_MASK 0x000e0000 + +/* Description RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_EXT80 + + For 20/40/80, this field shows the second selected Rx + chain that is used in HW IFFT mode + + + + For 80+80, this field shows the selected ext80 Rx chain + that is used in HW IFFT mode + + + + + + + + + + + + + + + + + + + + +*/ +#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_EXT80_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_EXT80_LSB 20 +#define RX_LOCATION_INFO_3_RTT_STRONGEST_CHAIN_EXT80_MASK 0x00700000 + +/* Description RX_LOCATION_INFO_3_RTT_RX_CHAIN_MASK + + Rx chain mask, each bit is a Rx chain + + 0: the Rx chain is not used + + 1: the Rx chain is used + + Support up to 8 Rx chains + + +*/ +#define RX_LOCATION_INFO_3_RTT_RX_CHAIN_MASK_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RTT_RX_CHAIN_MASK_LSB 23 +#define RX_LOCATION_INFO_3_RTT_RX_CHAIN_MASK_MASK 0x7f800000 + +/* Description RX_LOCATION_INFO_3_RESERVED_3 + + +*/ +#define RX_LOCATION_INFO_3_RESERVED_3_OFFSET 0x0000000c +#define RX_LOCATION_INFO_3_RESERVED_3_LSB 31 +#define RX_LOCATION_INFO_3_RESERVED_3_MASK 0x80000000 + +/* Description RX_LOCATION_INFO_4_RX_START_TS + + RX packet start timestamp + + + + It reports the time the first L-STF ADC sample arrived + at RX antenna + + + + clock unit is 480MHz + + +*/ +#define RX_LOCATION_INFO_4_RX_START_TS_OFFSET 0x00000010 +#define RX_LOCATION_INFO_4_RX_START_TS_LSB 0 +#define RX_LOCATION_INFO_4_RX_START_TS_MASK 0xffffffff + +/* Description RX_LOCATION_INFO_5_RX_END_TS + + RX packet end timestamp + + + + It reports the time the last symbol's last ADC sample + arrived at RX antenna + + + + clock unit is 480MHz + + +*/ +#define RX_LOCATION_INFO_5_RX_END_TS_OFFSET 0x00000014 +#define RX_LOCATION_INFO_5_RX_END_TS_LSB 0 +#define RX_LOCATION_INFO_5_RX_END_TS_MASK 0xffffffff + +/* Description RX_LOCATION_INFO_6_SFO_PHASE_PKT_START + + The phase of the SFO of the first symbol's first FFT + input sample + + + + 12 bits, signed 6.6. 6 bits integer to cover -66.7ns to + 66.7ns, and 6 bits fraction to provide a resolution of + 0.03ns + + + + clock unit is 480MHz + + +*/ +#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_START_OFFSET 0x00000018 +#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_START_LSB 0 +#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_START_MASK 0x00000fff + +/* Description RX_LOCATION_INFO_6_SFO_PHASE_PKT_END + + The phase of the SFO of the last symbol's last FFT input + sample + + + + 12 bits, signed 6.6. 6 bits integer to cover -66.7ns to + 66.7ns, and 6 bits fraction to provide a resolution of + 0.03ns + + + + clock unit is 480MHz + + +*/ +#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_END_OFFSET 0x00000018 +#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_END_LSB 12 +#define RX_LOCATION_INFO_6_SFO_PHASE_PKT_END_MASK 0x00fff000 + +/* Description RX_LOCATION_INFO_6_RTT_CHE_BUFFER_POINTER_HIGH8 + + The high 8 bits of the 40 bits pointer pointed to the + external RTT channel information buffer + + + + 8 bits + + +*/ +#define RX_LOCATION_INFO_6_RTT_CHE_BUFFER_POINTER_HIGH8_OFFSET 0x00000018 +#define RX_LOCATION_INFO_6_RTT_CHE_BUFFER_POINTER_HIGH8_LSB 24 +#define RX_LOCATION_INFO_6_RTT_CHE_BUFFER_POINTER_HIGH8_MASK 0xff000000 + +/* Description RX_LOCATION_INFO_7_RTT_CHE_BUFFER_POINTER_LOW32 + + The low 32 bits of the 40 bits pointer pointed to the + external RTT channel information buffer + + + + 32 bits + + +*/ +#define RX_LOCATION_INFO_7_RTT_CHE_BUFFER_POINTER_LOW32_OFFSET 0x0000001c +#define RX_LOCATION_INFO_7_RTT_CHE_BUFFER_POINTER_LOW32_LSB 0 +#define RX_LOCATION_INFO_7_RTT_CHE_BUFFER_POINTER_LOW32_MASK 0xffffffff + +/* Description RX_LOCATION_INFO_8_RTT_CFO_MEASUREMENT + + CFO measurement. Needed for passive locationing + + + + 14 bits, signed 1.13. 13 bits fraction to provide a + resolution of 153 Hz + + + + In units of cycles/800 ns + + +*/ +#define RX_LOCATION_INFO_8_RTT_CFO_MEASUREMENT_OFFSET 0x00000020 +#define RX_LOCATION_INFO_8_RTT_CFO_MEASUREMENT_LSB 0 +#define RX_LOCATION_INFO_8_RTT_CFO_MEASUREMENT_MASK 0x00003fff + +/* Description RX_LOCATION_INFO_8_RTT_CHAN_SPREAD + + Channel delay spread measurement. Needed for selecting + GI length + + + + 8 bits, unsigned. At 25 ns step. Can represent up to + 6375 ns + + + + In units of cycles @ 40 MHz + + +*/ +#define RX_LOCATION_INFO_8_RTT_CHAN_SPREAD_OFFSET 0x00000020 +#define RX_LOCATION_INFO_8_RTT_CHAN_SPREAD_LSB 14 +#define RX_LOCATION_INFO_8_RTT_CHAN_SPREAD_MASK 0x003fc000 + +/* Description RX_LOCATION_INFO_8_RTT_TIMING_BACKOFF_SEL + + Indicate which timing backoff value is used + + + + + + + + + + + + +*/ +#define RX_LOCATION_INFO_8_RTT_TIMING_BACKOFF_SEL_OFFSET 0x00000020 +#define RX_LOCATION_INFO_8_RTT_TIMING_BACKOFF_SEL_LSB 22 +#define RX_LOCATION_INFO_8_RTT_TIMING_BACKOFF_SEL_MASK 0x00c00000 + +/* Description RX_LOCATION_INFO_8_RESERVED_8 + + +*/ +#define RX_LOCATION_INFO_8_RESERVED_8_OFFSET 0x00000020 +#define RX_LOCATION_INFO_8_RESERVED_8_LSB 24 +#define RX_LOCATION_INFO_8_RESERVED_8_MASK 0x7f000000 + +/* Description RX_LOCATION_INFO_8_RX_LOCATION_INFO_VALID + + + + + + +*/ +#define RX_LOCATION_INFO_8_RX_LOCATION_INFO_VALID_OFFSET 0x00000020 +#define RX_LOCATION_INFO_8_RX_LOCATION_INFO_VALID_LSB 31 +#define RX_LOCATION_INFO_8_RX_LOCATION_INFO_VALID_MASK 0x80000000 + + +#endif // _RX_LOCATION_INFO_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/rx_mpdu_desc_info.h b/drivers/staging/fw-api/hw/qca6750/v1/rx_mpdu_desc_info.h new file mode 100644 index 000000000000..a8a6934a2947 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/rx_mpdu_desc_info.h @@ -0,0 +1,475 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_MPDU_DESC_INFO_H_ +#define _RX_MPDU_DESC_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 msdu_count[7:0], mpdu_sequence_number[19:8], fragment_flag[20], mpdu_retry_bit[21], ampdu_flag[22], bar_frame[23], pn_fields_contain_valid_info[24], sa_is_valid[25], sa_idx_timeout[26], da_is_valid[27], da_is_mcbc[28], da_idx_timeout[29], raw_mpdu[30], more_fragment_flag[31] +// 1 peer_meta_data[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_MPDU_DESC_INFO 2 + +struct rx_mpdu_desc_info { + uint32_t msdu_count : 8, //[7:0] + mpdu_sequence_number : 12, //[19:8] + fragment_flag : 1, //[20] + mpdu_retry_bit : 1, //[21] + ampdu_flag : 1, //[22] + bar_frame : 1, //[23] + pn_fields_contain_valid_info : 1, //[24] + sa_is_valid : 1, //[25] + sa_idx_timeout : 1, //[26] + da_is_valid : 1, //[27] + da_is_mcbc : 1, //[28] + da_idx_timeout : 1, //[29] + raw_mpdu : 1, //[30] + more_fragment_flag : 1; //[31] + uint32_t peer_meta_data : 32; //[31:0] +}; + +/* + +msdu_count + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + The number of MSDUs within the MPDU + + + +mpdu_sequence_number + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + The field can have two different meanings based on the + setting of field 'BAR_frame': + + + + 'BAR_frame' is NOT set: + + The MPDU sequence number of the received frame. + + + + 'BAR_frame' is set. + + The MPDU Start sequence number from the BAR frame + + + +fragment_flag + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + When set, this MPDU is a fragment and REO should forward + this fragment MPDU to the REO destination ring without any + reorder checks, pn checks or bitmap update. This implies + that REO is forwarding the pointer to the MSDU link + descriptor. The destination ring is coming from a + programmable register setting in REO + + + + + +mpdu_retry_bit + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + The retry bit setting from the MPDU header of the + received frame + + + +ampdu_flag + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + When set, the MPDU was received as part of an A-MPDU. + + + +bar_frame + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + When set, the received frame is a BAR frame. After + processing, this frame shall be pushed to SW or deleted. + + + +pn_fields_contain_valid_info + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + Copied here by RXDMA from RX_MPDU_END + + When not set, REO will Not perform a PN sequence number + check + +sa_is_valid + + When set, OLE found a valid SA entry for all MSDUs in + this MPDU + + + +sa_idx_timeout + + When set, at least 1 MSDU within the MPDU has an + unsuccessful MAC source address search due to the expiration + of the search timer. + + + +da_is_valid + + When set, OLE found a valid DA entry for all MSDUs in + this MPDU + + + +da_is_mcbc + + Field Only valid if da_is_valid is set + + + + When set, at least one of the DA addresses is a + Multicast or Broadcast address. + + + +da_idx_timeout + + When set, at least 1 MSDU within the MPDU has an + unsuccessful MAC destination address search due to the + expiration of the search timer. + + + +raw_mpdu + + Field only valid when first_msdu_in_mpdu_flag is set. + + + + When set, the contents in the MSDU buffer contains a + 'RAW' MPDU. This 'RAW' MPDU might be spread out over + multiple MSDU buffers. + + + +more_fragment_flag + + The More Fragment bit setting from the MPDU header of + the received frame + + + + + +peer_meta_data + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + + +*/ + + +/* Description RX_MPDU_DESC_INFO_0_MSDU_COUNT + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + The number of MSDUs within the MPDU + + +*/ +#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_LSB 0 +#define RX_MPDU_DESC_INFO_0_MSDU_COUNT_MASK 0x000000ff + +/* Description RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + The field can have two different meanings based on the + setting of field 'BAR_frame': + + + + 'BAR_frame' is NOT set: + + The MPDU sequence number of the received frame. + + + + 'BAR_frame' is set. + + The MPDU Start sequence number from the BAR frame + + +*/ +#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_LSB 8 +#define RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00 + +/* Description RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + When set, this MPDU is a fragment and REO should forward + this fragment MPDU to the REO destination ring without any + reorder checks, pn checks or bitmap update. This implies + that REO is forwarding the pointer to the MSDU link + descriptor. The destination ring is coming from a + programmable register setting in REO + + + + +*/ +#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_LSB 20 +#define RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_MASK 0x00100000 + +/* Description RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + The retry bit setting from the MPDU header of the + received frame + + +*/ +#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_LSB 21 +#define RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_MASK 0x00200000 + +/* Description RX_MPDU_DESC_INFO_0_AMPDU_FLAG + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + When set, the MPDU was received as part of an A-MPDU. + + +*/ +#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_LSB 22 +#define RX_MPDU_DESC_INFO_0_AMPDU_FLAG_MASK 0x00400000 + +/* Description RX_MPDU_DESC_INFO_0_BAR_FRAME + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + When set, the received frame is a BAR frame. After + processing, this frame shall be pushed to SW or deleted. + + +*/ +#define RX_MPDU_DESC_INFO_0_BAR_FRAME_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_BAR_FRAME_LSB 23 +#define RX_MPDU_DESC_INFO_0_BAR_FRAME_MASK 0x00800000 + +/* Description RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + Copied here by RXDMA from RX_MPDU_END + + When not set, REO will Not perform a PN sequence number + check +*/ +#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24 +#define RX_MPDU_DESC_INFO_0_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000 + +/* Description RX_MPDU_DESC_INFO_0_SA_IS_VALID + + When set, OLE found a valid SA entry for all MSDUs in + this MPDU + + +*/ +#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_LSB 25 +#define RX_MPDU_DESC_INFO_0_SA_IS_VALID_MASK 0x02000000 + +/* Description RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT + + When set, at least 1 MSDU within the MPDU has an + unsuccessful MAC source address search due to the expiration + of the search timer. + + +*/ +#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_LSB 26 +#define RX_MPDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK 0x04000000 + +/* Description RX_MPDU_DESC_INFO_0_DA_IS_VALID + + When set, OLE found a valid DA entry for all MSDUs in + this MPDU + + +*/ +#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_LSB 27 +#define RX_MPDU_DESC_INFO_0_DA_IS_VALID_MASK 0x08000000 + +/* Description RX_MPDU_DESC_INFO_0_DA_IS_MCBC + + Field Only valid if da_is_valid is set + + + + When set, at least one of the DA addresses is a + Multicast or Broadcast address. + + +*/ +#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_LSB 28 +#define RX_MPDU_DESC_INFO_0_DA_IS_MCBC_MASK 0x10000000 + +/* Description RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT + + When set, at least 1 MSDU within the MPDU has an + unsuccessful MAC destination address search due to the + expiration of the search timer. + + +*/ +#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_LSB 29 +#define RX_MPDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK 0x20000000 + +/* Description RX_MPDU_DESC_INFO_0_RAW_MPDU + + Field only valid when first_msdu_in_mpdu_flag is set. + + + + When set, the contents in the MSDU buffer contains a + 'RAW' MPDU. This 'RAW' MPDU might be spread out over + multiple MSDU buffers. + + +*/ +#define RX_MPDU_DESC_INFO_0_RAW_MPDU_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_RAW_MPDU_LSB 30 +#define RX_MPDU_DESC_INFO_0_RAW_MPDU_MASK 0x40000000 + +/* Description RX_MPDU_DESC_INFO_0_MORE_FRAGMENT_FLAG + + The More Fragment bit setting from the MPDU header of + the received frame + + + + +*/ +#define RX_MPDU_DESC_INFO_0_MORE_FRAGMENT_FLAG_OFFSET 0x00000000 +#define RX_MPDU_DESC_INFO_0_MORE_FRAGMENT_FLAG_LSB 31 +#define RX_MPDU_DESC_INFO_0_MORE_FRAGMENT_FLAG_MASK 0x80000000 + +/* Description RX_MPDU_DESC_INFO_1_PEER_META_DATA + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + + +*/ +#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_OFFSET 0x00000004 +#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_LSB 0 +#define RX_MPDU_DESC_INFO_1_PEER_META_DATA_MASK 0xffffffff + + +#endif // _RX_MPDU_DESC_INFO_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/rx_mpdu_details.h b/drivers/staging/fw-api/hw/qca6750/v1/rx_mpdu_details.h new file mode 100644 index 000000000000..32860c32ad22 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/rx_mpdu_details.h @@ -0,0 +1,472 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_MPDU_DETAILS_H_ +#define _RX_MPDU_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#include "rx_mpdu_desc_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct buffer_addr_info msdu_link_desc_addr_info; +// 2-3 struct rx_mpdu_desc_info rx_mpdu_desc_info_details; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_MPDU_DETAILS 4 + +struct rx_mpdu_details { + struct buffer_addr_info msdu_link_desc_addr_info; + struct rx_mpdu_desc_info rx_mpdu_desc_info_details; +}; + +/* + +struct buffer_addr_info msdu_link_desc_addr_info + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + Details of the physical address of the MSDU link + descriptor that contains pointers to MSDUs related to this + MPDU + +struct rx_mpdu_desc_info rx_mpdu_desc_info_details + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + General information related to the MPDU that should be +*/ + + + /* EXTERNAL REFERENCE : struct buffer_addr_info msdu_link_desc_addr_info */ + + +/* Description RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_MPDU_DETAILS_0_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + +*/ +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_MPDU_DETAILS_1_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + + /* EXTERNAL REFERENCE : struct rx_mpdu_desc_info rx_mpdu_desc_info_details */ + + +/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + The number of MSDUs within the MPDU + + +*/ +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + +/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + The field can have two different meanings based on the + setting of field 'BAR_frame': + + + + 'BAR_frame' is NOT set: + + The MPDU sequence number of the received frame. + + + + 'BAR_frame' is set. + + The MPDU Start sequence number from the BAR frame + + +*/ +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00 + +/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + When set, this MPDU is a fragment and REO should forward + this fragment MPDU to the REO destination ring without any + reorder checks, pn checks or bitmap update. This implies + that REO is forwarding the pointer to the MSDU link + descriptor. The destination ring is coming from a + programmable register setting in REO + + + + +*/ +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000 + +/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + The retry bit setting from the MPDU header of the + received frame + + +*/ +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000 + +/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + When set, the MPDU was received as part of an A-MPDU. + + +*/ +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000 + +/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + When set, the received frame is a BAR frame. After + processing, this frame shall be pushed to SW or deleted. + + +*/ +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000 + +/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + Copied here by RXDMA from RX_MPDU_END + + When not set, REO will Not perform a PN sequence number + check +*/ +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000 + +/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID + + When set, OLE found a valid SA entry for all MSDUs in + this MPDU + + +*/ +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000 + +/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT + + When set, at least 1 MSDU within the MPDU has an + unsuccessful MAC source address search due to the expiration + of the search timer. + + +*/ +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000 + +/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID + + When set, OLE found a valid DA entry for all MSDUs in + this MPDU + + +*/ +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000 + +/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC + + Field Only valid if da_is_valid is set + + + + When set, at least one of the DA addresses is a + Multicast or Broadcast address. + + +*/ +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000 + +/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT + + When set, at least 1 MSDU within the MPDU has an + unsuccessful MAC destination address search due to the + expiration of the search timer. + + +*/ +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000 + +/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU + + Field only valid when first_msdu_in_mpdu_flag is set. + + + + When set, the contents in the MSDU buffer contains a + 'RAW' MPDU. This 'RAW' MPDU might be spread out over + multiple MSDU buffers. + + +*/ +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 + +/* Description RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG + + The More Fragment bit setting from the MPDU header of + the received frame + + + + +*/ +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31 +#define RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000 + +/* Description RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + + +*/ +#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define RX_MPDU_DETAILS_3_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + + +#endif // _RX_MPDU_DETAILS_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/rx_mpdu_end.h b/drivers/staging/fw-api/hw/qca6750/v1/rx_mpdu_end.h new file mode 100644 index 000000000000..0de60d5db588 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/rx_mpdu_end.h @@ -0,0 +1,762 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_MPDU_END_H_ +#define _RX_MPDU_END_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16] +// 1 reserved_1a[10:0], unsup_ktype_short_frame[11], rx_in_tx_decrypt_byp[12], overflow_err[13], mpdu_length_err[14], tkip_mic_err[15], decrypt_err[16], unencrypted_frame_err[17], pn_fields_contain_valid_info[18], fcs_err[19], msdu_length_err[20], rxdma0_destination_ring[22:21], rxdma1_destination_ring[24:23], decrypt_status_code[27:25], rx_bitmap_not_updated[28], reserved_1b[31:29] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_MPDU_END 2 + +struct rx_mpdu_end { + uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] + sw_frame_group_id : 7, //[8:2] + reserved_0 : 7, //[15:9] + phy_ppdu_id : 16; //[31:16] + uint32_t reserved_1a : 11, //[10:0] + unsup_ktype_short_frame : 1, //[11] + rx_in_tx_decrypt_byp : 1, //[12] + overflow_err : 1, //[13] + mpdu_length_err : 1, //[14] + tkip_mic_err : 1, //[15] + decrypt_err : 1, //[16] + unencrypted_frame_err : 1, //[17] + pn_fields_contain_valid_info : 1, //[18] + fcs_err : 1, //[19] + msdu_length_err : 1, //[20] + rxdma0_destination_ring : 2, //[22:21] + rxdma1_destination_ring : 2, //[24:23] + decrypt_status_code : 3, //[27:25] + rx_bitmap_not_updated : 1, //[28] + reserved_1b : 3; //[31:29] +}; + +/* + +rxpcu_mpdu_filter_in_category + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + + This MPDU passed the normal + frame filter programming of rxpcu + + This MPDU did NOT pass the + regular frame filter and would have been dropped, were it + not for the frame fitting into the 'monitor_client' + category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the + rxpcu_monitor_client filter. It would have been dropped + accept that it did pass the 'monitor_other' category. + + + +sw_frame_group_id + + SW processes frames based on certain classifications. + This field indicates to what sw classification this MPDU is + mapped. + + The classification is given in priority order + + + + + + + + + + + + This includes mpdus + of type Data Null as well as QoS Data Null + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + + + + + + + +reserved_0 + + + +phy_ppdu_id + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + + +reserved_1a + + + +unsup_ktype_short_frame + + This bit will be '1' when WEP or TKIP or WAPI key type + is received for 11ah short frame. Crypto will bypass the + received packet without decryption to RxOLE after setting + this bit. + +rx_in_tx_decrypt_byp + + Indicates that RX packet is not decrypted as Crypto is + busy with TX packet processing. + +overflow_err + + RXPCU Receive FIFO ran out of space to receive the full + MPDU. Therefor this MPDU is terminated early and is thus + corrupted. + + + + This MPDU will not be ACKed. + + RXPCU might still be able to correctly receive the + following MPDUs in the PPDU if enough fifo space became + available in time + +mpdu_length_err + + Set by RXPCU if the expected MPDU length does not + correspond with the actually received number of bytes in the + MPDU. + +tkip_mic_err + + Set by RX CRYPTO when CRYPTO detected a TKIP MIC error + for this MPDU + +decrypt_err + + Set by RX CRYPTO when CRYPTO detected a decrypt error + for this MPDU or CRYPTO received an encrypted frame, but did + not get a valid corresponding key id in the peer entry. + +unencrypted_frame_err + + Set by RX CRYPTO when CRYPTO detected an unencrypted + frame while in the peer entry field + 'All_frames_shall_be_encrypted' is set. + +pn_fields_contain_valid_info + + Set by RX CRYPTO to indicate that there is a valid PN + field present in this MPDU + +fcs_err + + Set by RXPCU when there is an FCS error detected for + this MPDU + + NOTE that when this field is set, all other (error) + field settings should be ignored as modules could have made + wrong decisions based on the corrupted data. + +msdu_length_err + + Set by RXOLE when there is an msdu length error detected + in at least 1 of the MSDUs embedded within the MPDU + +rxdma0_destination_ring + + The ring to which RXDMA0 shall push the frame, assuming + no MPDU level errors are detected. In case of MPDU level + errors, RXDMA0 might change the RXDMA0 destination + + + + RXDMA0 shall push the + frame to the Release ring. Effectively this means the frame + needs to be dropped. + + + + RXDMA0 shall push the frame to + the FW ring + + + + RXDMA0 shall push the frame to + the SW ring + + + + RXDMA0 shall push the frame + to the REO entrance ring + + + + + +rxdma1_destination_ring + + The ring to which RXDMA1 shall push the frame, assuming + no MPDU level errors are detected. In case of MPDU level + errors, RXDMA1 might change the RXDMA destination + + + + RXDMA1 shall push the + frame to the Release ring. Effectively this means the frame + needs to be dropped. + + + + RXDMA1 shall push the frame to + the FW ring + + + + RXDMA1 shall push the frame to + the SW ring + + + + RXDMA1 shall push the frame + to the REO entrance ring + + + + + +decrypt_status_code + + Field provides insight into the decryption performed + + + + Frame had protection enabled and + decrypted properly + + Frame is unprotected + and hence bypassed + + Frame has protection enabled + and could not be properly decrypted due to MIC/ICV mismatch + etc. + + Frame has protection + enabled but the key that was required to decrypt this frame + was not valid + + Frame has + protection enabled but the key that was required to decrypt + this frame was not valid + + Reserved for other indications + + + + + +rx_bitmap_not_updated + + Frame is received, but RXPCU could not update the + receive bitmap due to (temporary) fifo contraints. + + + +reserved_1b + + +*/ + + +/* Description RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + + This MPDU passed the normal + frame filter programming of rxpcu + + This MPDU did NOT pass the + regular frame filter and would have been dropped, were it + not for the frame fitting into the 'monitor_client' + category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the + rxpcu_monitor_client filter. It would have been dropped + accept that it did pass the 'monitor_other' category. + + +*/ +#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MPDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +/* Description RX_MPDU_END_0_SW_FRAME_GROUP_ID + + SW processes frames based on certain classifications. + This field indicates to what sw classification this MPDU is + mapped. + + The classification is given in priority order + + + + + + + + + + + + This includes mpdus + of type Data Null as well as QoS Data Null + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + + + + + + +*/ +#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MPDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc + +/* Description RX_MPDU_END_0_RESERVED_0 + + +*/ +#define RX_MPDU_END_0_RESERVED_0_OFFSET 0x00000000 +#define RX_MPDU_END_0_RESERVED_0_LSB 9 +#define RX_MPDU_END_0_RESERVED_0_MASK 0x0000fe00 + +/* Description RX_MPDU_END_0_PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + +*/ +#define RX_MPDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_MPDU_END_0_PHY_PPDU_ID_LSB 16 +#define RX_MPDU_END_0_PHY_PPDU_ID_MASK 0xffff0000 + +/* Description RX_MPDU_END_1_RESERVED_1A + + +*/ +#define RX_MPDU_END_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_MPDU_END_1_RESERVED_1A_LSB 0 +#define RX_MPDU_END_1_RESERVED_1A_MASK 0x000007ff + +/* Description RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME + + This bit will be '1' when WEP or TKIP or WAPI key type + is received for 11ah short frame. Crypto will bypass the + received packet without decryption to RxOLE after setting + this bit. +*/ +#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_OFFSET 0x00000004 +#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_LSB 11 +#define RX_MPDU_END_1_UNSUP_KTYPE_SHORT_FRAME_MASK 0x00000800 + +/* Description RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP + + Indicates that RX packet is not decrypted as Crypto is + busy with TX packet processing. +*/ +#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET 0x00000004 +#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB 12 +#define RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK 0x00001000 + +/* Description RX_MPDU_END_1_OVERFLOW_ERR + + RXPCU Receive FIFO ran out of space to receive the full + MPDU. Therefor this MPDU is terminated early and is thus + corrupted. + + + + This MPDU will not be ACKed. + + RXPCU might still be able to correctly receive the + following MPDUs in the PPDU if enough fifo space became + available in time +*/ +#define RX_MPDU_END_1_OVERFLOW_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_OVERFLOW_ERR_LSB 13 +#define RX_MPDU_END_1_OVERFLOW_ERR_MASK 0x00002000 + +/* Description RX_MPDU_END_1_MPDU_LENGTH_ERR + + Set by RXPCU if the expected MPDU length does not + correspond with the actually received number of bytes in the + MPDU. +*/ +#define RX_MPDU_END_1_MPDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_MPDU_LENGTH_ERR_LSB 14 +#define RX_MPDU_END_1_MPDU_LENGTH_ERR_MASK 0x00004000 + +/* Description RX_MPDU_END_1_TKIP_MIC_ERR + + Set by RX CRYPTO when CRYPTO detected a TKIP MIC error + for this MPDU +*/ +#define RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_TKIP_MIC_ERR_LSB 15 +#define RX_MPDU_END_1_TKIP_MIC_ERR_MASK 0x00008000 + +/* Description RX_MPDU_END_1_DECRYPT_ERR + + Set by RX CRYPTO when CRYPTO detected a decrypt error + for this MPDU or CRYPTO received an encrypted frame, but did + not get a valid corresponding key id in the peer entry. +*/ +#define RX_MPDU_END_1_DECRYPT_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_DECRYPT_ERR_LSB 16 +#define RX_MPDU_END_1_DECRYPT_ERR_MASK 0x00010000 + +/* Description RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR + + Set by RX CRYPTO when CRYPTO detected an unencrypted + frame while in the peer entry field + 'All_frames_shall_be_encrypted' is set. +*/ +#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_LSB 17 +#define RX_MPDU_END_1_UNENCRYPTED_FRAME_ERR_MASK 0x00020000 + +/* Description RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO + + Set by RX CRYPTO to indicate that there is a valid PN + field present in this MPDU +*/ +#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000004 +#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_LSB 18 +#define RX_MPDU_END_1_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x00040000 + +/* Description RX_MPDU_END_1_FCS_ERR + + Set by RXPCU when there is an FCS error detected for + this MPDU + + NOTE that when this field is set, all other (error) + field settings should be ignored as modules could have made + wrong decisions based on the corrupted data. +*/ +#define RX_MPDU_END_1_FCS_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_FCS_ERR_LSB 19 +#define RX_MPDU_END_1_FCS_ERR_MASK 0x00080000 + +/* Description RX_MPDU_END_1_MSDU_LENGTH_ERR + + Set by RXOLE when there is an msdu length error detected + in at least 1 of the MSDUs embedded within the MPDU +*/ +#define RX_MPDU_END_1_MSDU_LENGTH_ERR_OFFSET 0x00000004 +#define RX_MPDU_END_1_MSDU_LENGTH_ERR_LSB 20 +#define RX_MPDU_END_1_MSDU_LENGTH_ERR_MASK 0x00100000 + +/* Description RX_MPDU_END_1_RXDMA0_DESTINATION_RING + + The ring to which RXDMA0 shall push the frame, assuming + no MPDU level errors are detected. In case of MPDU level + errors, RXDMA0 might change the RXDMA0 destination + + + + RXDMA0 shall push the + frame to the Release ring. Effectively this means the frame + needs to be dropped. + + + + RXDMA0 shall push the frame to + the FW ring + + + + RXDMA0 shall push the frame to + the SW ring + + + + RXDMA0 shall push the frame + to the REO entrance ring + + + + +*/ +#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_OFFSET 0x00000004 +#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_LSB 21 +#define RX_MPDU_END_1_RXDMA0_DESTINATION_RING_MASK 0x00600000 + +/* Description RX_MPDU_END_1_RXDMA1_DESTINATION_RING + + The ring to which RXDMA1 shall push the frame, assuming + no MPDU level errors are detected. In case of MPDU level + errors, RXDMA1 might change the RXDMA destination + + + + RXDMA1 shall push the + frame to the Release ring. Effectively this means the frame + needs to be dropped. + + + + RXDMA1 shall push the frame to + the FW ring + + + + RXDMA1 shall push the frame to + the SW ring + + + + RXDMA1 shall push the frame + to the REO entrance ring + + + + +*/ +#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_OFFSET 0x00000004 +#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_LSB 23 +#define RX_MPDU_END_1_RXDMA1_DESTINATION_RING_MASK 0x01800000 + +/* Description RX_MPDU_END_1_DECRYPT_STATUS_CODE + + Field provides insight into the decryption performed + + + + Frame had protection enabled and + decrypted properly + + Frame is unprotected + and hence bypassed + + Frame has protection enabled + and could not be properly decrypted due to MIC/ICV mismatch + etc. + + Frame has protection + enabled but the key that was required to decrypt this frame + was not valid + + Frame has + protection enabled but the key that was required to decrypt + this frame was not valid + + Reserved for other indications + + + + +*/ +#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_OFFSET 0x00000004 +#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_LSB 25 +#define RX_MPDU_END_1_DECRYPT_STATUS_CODE_MASK 0x0e000000 + +/* Description RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED + + Frame is received, but RXPCU could not update the + receive bitmap due to (temporary) fifo contraints. + + +*/ +#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_OFFSET 0x00000004 +#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_LSB 28 +#define RX_MPDU_END_1_RX_BITMAP_NOT_UPDATED_MASK 0x10000000 + +/* Description RX_MPDU_END_1_RESERVED_1B + + +*/ +#define RX_MPDU_END_1_RESERVED_1B_OFFSET 0x00000004 +#define RX_MPDU_END_1_RESERVED_1B_LSB 29 +#define RX_MPDU_END_1_RESERVED_1B_MASK 0xe0000000 + + +#endif // _RX_MPDU_END_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/rx_mpdu_info.h b/drivers/staging/fw-api/hw/qca6750/v1/rx_mpdu_info.h new file mode 100644 index 000000000000..159d09602572 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/rx_mpdu_info.h @@ -0,0 +1,3392 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_MPDU_INFO_H_ +#define _RX_MPDU_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rxpt_classify_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 struct rxpt_classify_info rxpt_classify_info_details; +// 1 rx_reo_queue_desc_addr_31_0[31:0] +// 2 rx_reo_queue_desc_addr_39_32[7:0], receive_queue_number[23:8], pre_delim_err_warning[24], first_delim_err[25], reserved_2a[31:26] +// 3 pn_31_0[31:0] +// 4 pn_63_32[31:0] +// 5 pn_95_64[31:0] +// 6 pn_127_96[31:0] +// 7 epd_en[0], all_frames_shall_be_encrypted[1], encrypt_type[5:2], wep_key_width_for_variable_key[7:6], mesh_sta[9:8], bssid_hit[10], bssid_number[14:11], tid[18:15], reserved_7a[31:19] +// 8 peer_meta_data[31:0] +// 9 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], ndp_frame[9], phy_err[10], phy_err_during_mpdu_header[11], protocol_version_err[12], ast_based_lookup_valid[13], reserved_9a[15:14], phy_ppdu_id[31:16] +// 10 ast_index[15:0], sw_peer_id[31:16] +// 11 mpdu_frame_control_valid[0], mpdu_duration_valid[1], mac_addr_ad1_valid[2], mac_addr_ad2_valid[3], mac_addr_ad3_valid[4], mac_addr_ad4_valid[5], mpdu_sequence_control_valid[6], mpdu_qos_control_valid[7], mpdu_ht_control_valid[8], frame_encryption_info_valid[9], mpdu_fragment_number[13:10], more_fragment_flag[14], reserved_11a[15], fr_ds[16], to_ds[17], encrypted[18], mpdu_retry[19], mpdu_sequence_number[31:20] +// 12 key_id_octet[7:0], new_peer_entry[8], decrypt_needed[9], decap_type[11:10], rx_insert_vlan_c_tag_padding[12], rx_insert_vlan_s_tag_padding[13], strip_vlan_c_tag_decap[14], strip_vlan_s_tag_decap[15], pre_delim_count[27:16], ampdu_flag[28], bar_frame[29], raw_mpdu[30], reserved_12[31] +// 13 mpdu_length[13:0], first_mpdu[14], mcast_bcast[15], ast_index_not_found[16], ast_index_timeout[17], power_mgmt[18], non_qos[19], null_data[20], mgmt_type[21], ctrl_type[22], more_data[23], eosp[24], fragment_flag[25], order[26], u_apsd_trigger[27], encrypt_required[28], directed[29], amsdu_present[30], reserved_13[31] +// 14 mpdu_frame_control_field[15:0], mpdu_duration_field[31:16] +// 15 mac_addr_ad1_31_0[31:0] +// 16 mac_addr_ad1_47_32[15:0], mac_addr_ad2_15_0[31:16] +// 17 mac_addr_ad2_47_16[31:0] +// 18 mac_addr_ad3_31_0[31:0] +// 19 mac_addr_ad3_47_32[15:0], mpdu_sequence_control_field[31:16] +// 20 mac_addr_ad4_31_0[31:0] +// 21 mac_addr_ad4_47_32[15:0], mpdu_qos_control_field[31:16] +// 22 mpdu_ht_control_field[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_MPDU_INFO 23 + +struct rx_mpdu_info { + struct rxpt_classify_info rxpt_classify_info_details; + uint32_t rx_reo_queue_desc_addr_31_0 : 32; //[31:0] + uint32_t rx_reo_queue_desc_addr_39_32 : 8, //[7:0] + receive_queue_number : 16, //[23:8] + pre_delim_err_warning : 1, //[24] + first_delim_err : 1, //[25] + reserved_2a : 6; //[31:26] + uint32_t pn_31_0 : 32; //[31:0] + uint32_t pn_63_32 : 32; //[31:0] + uint32_t pn_95_64 : 32; //[31:0] + uint32_t pn_127_96 : 32; //[31:0] + uint32_t epd_en : 1, //[0] + all_frames_shall_be_encrypted : 1, //[1] + encrypt_type : 4, //[5:2] + wep_key_width_for_variable_key : 2, //[7:6] + mesh_sta : 2, //[9:8] + bssid_hit : 1, //[10] + bssid_number : 4, //[14:11] + tid : 4, //[18:15] + reserved_7a : 13; //[31:19] + uint32_t peer_meta_data : 32; //[31:0] + uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] + sw_frame_group_id : 7, //[8:2] + ndp_frame : 1, //[9] + phy_err : 1, //[10] + phy_err_during_mpdu_header : 1, //[11] + protocol_version_err : 1, //[12] + ast_based_lookup_valid : 1, //[13] + reserved_9a : 2, //[15:14] + phy_ppdu_id : 16; //[31:16] + uint32_t ast_index : 16, //[15:0] + sw_peer_id : 16; //[31:16] + uint32_t mpdu_frame_control_valid : 1, //[0] + mpdu_duration_valid : 1, //[1] + mac_addr_ad1_valid : 1, //[2] + mac_addr_ad2_valid : 1, //[3] + mac_addr_ad3_valid : 1, //[4] + mac_addr_ad4_valid : 1, //[5] + mpdu_sequence_control_valid : 1, //[6] + mpdu_qos_control_valid : 1, //[7] + mpdu_ht_control_valid : 1, //[8] + frame_encryption_info_valid : 1, //[9] + mpdu_fragment_number : 4, //[13:10] + more_fragment_flag : 1, //[14] + reserved_11a : 1, //[15] + fr_ds : 1, //[16] + to_ds : 1, //[17] + encrypted : 1, //[18] + mpdu_retry : 1, //[19] + mpdu_sequence_number : 12; //[31:20] + uint32_t key_id_octet : 8, //[7:0] + new_peer_entry : 1, //[8] + decrypt_needed : 1, //[9] + decap_type : 2, //[11:10] + rx_insert_vlan_c_tag_padding : 1, //[12] + rx_insert_vlan_s_tag_padding : 1, //[13] + strip_vlan_c_tag_decap : 1, //[14] + strip_vlan_s_tag_decap : 1, //[15] + pre_delim_count : 12, //[27:16] + ampdu_flag : 1, //[28] + bar_frame : 1, //[29] + raw_mpdu : 1, //[30] + reserved_12 : 1; //[31] + uint32_t mpdu_length : 14, //[13:0] + first_mpdu : 1, //[14] + mcast_bcast : 1, //[15] + ast_index_not_found : 1, //[16] + ast_index_timeout : 1, //[17] + power_mgmt : 1, //[18] + non_qos : 1, //[19] + null_data : 1, //[20] + mgmt_type : 1, //[21] + ctrl_type : 1, //[22] + more_data : 1, //[23] + eosp : 1, //[24] + fragment_flag : 1, //[25] + order : 1, //[26] + u_apsd_trigger : 1, //[27] + encrypt_required : 1, //[28] + directed : 1, //[29] + amsdu_present : 1, //[30] + reserved_13 : 1; //[31] + uint32_t mpdu_frame_control_field : 16, //[15:0] + mpdu_duration_field : 16; //[31:16] + uint32_t mac_addr_ad1_31_0 : 32; //[31:0] + uint32_t mac_addr_ad1_47_32 : 16, //[15:0] + mac_addr_ad2_15_0 : 16; //[31:16] + uint32_t mac_addr_ad2_47_16 : 32; //[31:0] + uint32_t mac_addr_ad3_31_0 : 32; //[31:0] + uint32_t mac_addr_ad3_47_32 : 16, //[15:0] + mpdu_sequence_control_field : 16; //[31:16] + uint32_t mac_addr_ad4_31_0 : 32; //[31:0] + uint32_t mac_addr_ad4_47_32 : 16, //[15:0] + mpdu_qos_control_field : 16; //[31:16] + uint32_t mpdu_ht_control_field : 32; //[31:0] +}; + +/* + +struct rxpt_classify_info rxpt_classify_info_details + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + RXOLE related classification info + + + +rx_reo_queue_desc_addr_39_32 + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Address (upper 8 bits) of the REO queue descriptor. + + + + If no Peer entry lookup happened for this frame, the + value wil be set to 0, and the frame shall never be pushed + to REO entrance ring. + + + +receive_queue_number + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Indicates the MPDU queue ID to which this MPDU link + descriptor belongs + + Used for tracking and debugging + + + +pre_delim_err_warning + + Indicates that a delimiter FCS error was found in + between the Previous MPDU and this MPDU. + + + + Note that this is just a warning, and does not mean that + this MPDU is corrupted in any way. If it is, there will be + other errors indicated such as FCS or decrypt errors + + + + In case of ndp or phy_err, this field will indicate at + least one of delimiters located after the last MPDU in the + previous PPDU has been corrupted. + +first_delim_err + + Indicates that the first delimiter had a FCS failure. + Only valid when first_mpdu and first_msdu are set. + + + + +reserved_2a + + + +pn_31_0 + + + + + + WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] + is valid. + + TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, + WEPSeed[1], pn1}. Only pn[47:0] is valid. + + AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, + pn1, pn0}. Only pn[47:0] is valid. + + WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, + pn11, pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, + pn0}. pn[127:0] are valid. + + + + +pn_63_32 + + + + + Bits [63:32] of the PN number. See description for + pn_31_0. + + + + +pn_95_64 + + + + + Bits [95:64] of the PN number. See description for + pn_31_0. + + + + +pn_127_96 + + + + + Bits [127:96] of the PN number. See description for + pn_31_0. + + + + +epd_en + + Field only valid when AST_based_lookup_valid == 1. + + + + + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + If set to one use EPD instead of LPD + + + + + + +all_frames_shall_be_encrypted + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + When set, all frames (data only ?) shall be encrypted. + If not, RX CRYPTO shall set an error flag. + + + +encrypt_type + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Indicates type of decrypt cipher used (as defined in the + peer entry) + + + + WEP 40-bit + + WEP 104-bit + + TKIP without MIC + + WEP 128-bit + + TKIP with MIC + + WAPI + + AES CCMP 128 + + No crypto + + AES CCMP 256 + + AES CCMP 128 + + AES CCMP 256 + + WAPI GCM SM4 + + + + WEP encryption. As for WEP + per keyid the key bit width can vary, the key bit width for + this MPDU will be indicated in field + wep_key_width_for_variable key + + + +wep_key_width_for_variable_key + + Field only valid when key_type is set to + wep_varied_width. + + + + This field indicates the size of the wep key for this + MPDU. + + + + WEP 40-bit + + WEP 104-bit + + WEP 128-bit + + + + + +mesh_sta + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + When set, this is a Mesh (11s) STA. + + + + The interpretation of the A-MSDU 'Length' field in the + MPDU (if any) is decided by the e-numerations below. + + + + + + A-MSDU 'Length' is big endian and + includes the length of Mesh Control. + + A-MSDU 'Length' is big endian and + excludes the length of Mesh Control. + + A-MSDU 'Length' is little endian + and excludes the length of Mesh Control. This is + 802.11s-compliant. + + + +bssid_hit + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + When set, the BSSID of the incoming frame matched one of + the 8 BSSID register values + + + + + +bssid_number + + Field only valid when bssid_hit is set. + + + + This number indicates which one out of the 8 BSSID + register values matched the incoming frame + + + +tid + + Field only valid when mpdu_qos_control_valid is set + + + + The TID field in the QoS control field + + + +reserved_7a + + + +peer_meta_data + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + + + +rxpcu_mpdu_filter_in_category + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + + This MPDU passed the normal + frame filter programming of rxpcu + + This MPDU did NOT pass the + regular frame filter and would have been dropped, were it + not for the frame fitting into the 'monitor_client' + category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the + rxpcu_monitor_client filter. It would have been dropped + accept that it did pass the 'monitor_other' category. + + + + Note: for ndp frame, if it was expected because the + preceding NDPA was filter_pass, the setting + rxpcu_filter_pass will be used. This setting will also be + used for every ndp frame in case Promiscuous mode is + enabled. + + + + In case promiscuous is not enabled, and an NDP is not + preceded by a NPDA filter pass frame, the only other setting + that could appear here for the NDP is rxpcu_monitor_other. + + (rxpcu has a configuration bit specifically for this + scenario) + + + + Note: for + + + +sw_frame_group_id + + SW processes frames based on certain classifications. + This field indicates to what sw classification this MPDU is + mapped. + + The classification is given in priority order + + + + Note: The + corresponding Rxpcu_Mpdu_filter_in_category can be + rxpcu_filter_pass or rxpcu_monitor_other + + + + + + + + This includes mpdus + of type Data Null as well as QoS Data Null + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + Note: The corresponding Rxpcu_Mpdu_filter_in_category + can only be rxpcu_monitor_other + + + + + Note: The corresponding Rxpcu_Mpdu_filter_in_category + can be rxpcu_filter_pass + + + + + +ndp_frame + + When set, the received frame was an NDP frame, and thus + there will be no MPDU data. + + + +phy_err + + When set, a PHY error was received before MAC received + any data, and thus there will be no MPDU data. + + + +phy_err_during_mpdu_header + + When set, a PHY error was received before MAC received + the complete MPDU header which was needed for proper + decoding + + + +protocol_version_err + + Set when RXPCU detected a version error in the Frame + control field + + + +ast_based_lookup_valid + + When set, AST based lookup for this frame has found a + valid result. + + + + Note that for NDP frame this will never be set + + + +reserved_9a + + + +phy_ppdu_id + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + + +ast_index + + This field indicates the index of the AST entry + corresponding to this MPDU. It is provided by the GSE module + instantiated in RXPCU. + + A value of 0xFFFF indicates an invalid AST index, + meaning that No AST entry was found or NO AST search was + performed + + + + In case of ndp or phy_err, this field will be set to + 0xFFFF + + + +sw_peer_id + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + This field indicates a unique peer identifier. It is set + equal to field 'sw_peer_id' from the AST entry + + + + + +mpdu_frame_control_valid + + When set, the field Mpdu_Frame_control_field has valid + information + + + + + + +mpdu_duration_valid + + When set, the field Mpdu_duration_field has valid + information + + + + + + +mac_addr_ad1_valid + + When set, the fields mac_addr_ad1_..... have valid + information + + + + + + +mac_addr_ad2_valid + + When set, the fields mac_addr_ad2_..... have valid + information + + + + + + + + + +mac_addr_ad3_valid + + When set, the fields mac_addr_ad3_..... have valid + information + + + + + + + + + +mac_addr_ad4_valid + + When set, the fields mac_addr_ad4_..... have valid + information + + + + + + + + + +mpdu_sequence_control_valid + + When set, the fields mpdu_sequence_control_field and + mpdu_sequence_number have valid information as well as field + + + + For MPDUs without a sequence control field, this field + will not be set. + + + + + + +mpdu_qos_control_valid + + When set, the field mpdu_qos_control_field has valid + information + + + + For MPDUs without a QoS control field, this field will + not be set. + + + + + + +mpdu_ht_control_valid + + When set, the field mpdu_HT_control_field has valid + information + + + + For MPDUs without a HT control field, this field will + not be set. + + + + + + +frame_encryption_info_valid + + When set, the encryption related info fields, like IV + and PN are valid + + + + For MPDUs that are not encrypted, this will not be set. + + + + + + +mpdu_fragment_number + + Field only valid when Mpdu_sequence_control_valid is set + AND Fragment_flag is set + + + + The fragment number from the 802.11 header + + + + + +more_fragment_flag + + The More Fragment bit setting from the MPDU header of + the received frame + + + + + +reserved_11a + + + +fr_ds + + Field only valid when Mpdu_frame_control_valid is set + + + + Set if the from DS bit is set in the frame control. + + + +to_ds + + Field only valid when Mpdu_frame_control_valid is set + + + + Set if the to DS bit is set in the frame control. + + + +encrypted + + Field only valid when Mpdu_frame_control_valid is set. + + + + Protected bit from the frame control. + + + +mpdu_retry + + Field only valid when Mpdu_frame_control_valid is set. + + + + Retry bit from the frame control. Only valid when + first_msdu is set. + + + +mpdu_sequence_number + + Field only valid when Mpdu_sequence_control_valid is + set. + + + + The sequence number from the 802.11 header. + + + +key_id_octet + + + + + The key ID octet from the IV. + + + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + +new_peer_entry + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Set if new RX_PEER_ENTRY TLV follows. If clear, + RX_PEER_ENTRY doesn't follow so RX DECRYPTION module either + uses old peer entry or not decrypt. + + + +decrypt_needed + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Set if decryption is needed. + + + + Note: + + When RXPCU sets bit 'ast_index_not_found' and/or + ast_index_timeout', RXPCU will also ensure that this bit is + NOT set + + CRYPTO for that reason only needs to evaluate this bit + and non of the other ones. + + + +decap_type + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Used by the OLE during decapsulation. + + + + Indicates the decapsulation that HW will perform: + + + + No encapsulation + + + + Ethernet 2 (DIX) or 802.3 (uses + SNAP/LLC) + + Indicate Ethernet + + + + + +rx_insert_vlan_c_tag_padding + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Insert 4 byte of all zeros as VLAN tag if the rx payload + does not have VLAN. Used during decapsulation. + + + +rx_insert_vlan_s_tag_padding + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Insert 4 byte of all zeros as double VLAN tag if the rx + payload does not have VLAN. Used during + + + +strip_vlan_c_tag_decap + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Strip the VLAN during decapsulation.  Used by the OLE. + + + +strip_vlan_s_tag_decap + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Strip the double VLAN during decapsulation.  Used by + the OLE. + + + +pre_delim_count + + The number of delimiters before this MPDU. + + + + Note that this number is cleared at PPDU start. + + + + If this MPDU is the first received MPDU in the PPDU and + this MPDU gets filtered-in, this field will indicate the + number of delimiters located after the last MPDU in the + previous PPDU. + + + + If this MPDU is located after the first received MPDU in + an PPDU, this field will indicate the number of delimiters + located between the previous MPDU and this MPDU. + + + + In case of ndp or phy_err, this field will indicate the + number of delimiters located after the last MPDU in the + previous PPDU. + + + +ampdu_flag + + When set, received frame was part of an A-MPDU. + + + + + + +bar_frame + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + When set, received frame is a BAR frame + + + +raw_mpdu + + Consumer: SW + + Producer: RXOLE + + + + RXPCU sets this field to 0 and RXOLE overwrites it. + + + + Set to 1 by RXOLE when it has not performed any 802.11 + to Ethernet/Natvie WiFi header conversion on this MPDU. + + + +reserved_12 + + + +mpdu_length + + In case of ndp or phy_err this field will be set to 0 + + + + MPDU length before decapsulation. + + + +first_mpdu + + See definition in RX attention descriptor + + + + In case of ndp or phy_err, this field will be set. Note + however that there will not actually be any data contents in + the MPDU. + + + +mcast_bcast + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +ast_index_not_found + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +ast_index_timeout + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +power_mgmt + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +non_qos + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 1 + + + + See definition in RX attention descriptor + + + +null_data + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +mgmt_type + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +ctrl_type + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +more_data + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +eosp + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +fragment_flag + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +order + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + + + +u_apsd_trigger + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +encrypt_required + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +directed + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + +amsdu_present + + Field only valid when Mpdu_qos_control_valid is set + + + + The 'amsdu_present' bit within the QoS control field of + the MPDU + + + +reserved_13 + + + +mpdu_frame_control_field + + Field only valid when Mpdu_frame_control_valid is set + + + + The frame control field of this received MPDU. + + + + Field only valid when Ndp_frame and phy_err are NOT set + + + + Bytes 0 + 1 of the received MPDU + + + +mpdu_duration_field + + Field only valid when Mpdu_duration_valid is set + + + + The duration field of this received MPDU. + + + +mac_addr_ad1_31_0 + + Field only valid when mac_addr_ad1_valid is set + + + + The Least Significant 4 bytes of the Received Frames MAC + Address AD1 + + + +mac_addr_ad1_47_32 + + Field only valid when mac_addr_ad1_valid is set + + + + The 2 most significant bytes of the Received Frames MAC + Address AD1 + + + +mac_addr_ad2_15_0 + + Field only valid when mac_addr_ad2_valid is set + + + + The Least Significant 2 bytes of the Received Frames MAC + Address AD2 + + + +mac_addr_ad2_47_16 + + Field only valid when mac_addr_ad2_valid is set + + + + The 4 most significant bytes of the Received Frames MAC + Address AD2 + + + +mac_addr_ad3_31_0 + + Field only valid when mac_addr_ad3_valid is set + + + + The Least Significant 4 bytes of the Received Frames MAC + Address AD3 + + + +mac_addr_ad3_47_32 + + Field only valid when mac_addr_ad3_valid is set + + + + The 2 most significant bytes of the Received Frames MAC + Address AD3 + + + +mpdu_sequence_control_field + + + + + The sequence control field of the MPDU + + + +mac_addr_ad4_31_0 + + Field only valid when mac_addr_ad4_valid is set + + + + The Least Significant 4 bytes of the Received Frames MAC + Address AD4 + + + +mac_addr_ad4_47_32 + + Field only valid when mac_addr_ad4_valid is set + + + + The 2 most significant bytes of the Received Frames MAC + Address AD4 + + + +mpdu_qos_control_field + + Field only valid when mpdu_qos_control_valid is set + + + + The sequence control field of the MPDU + + + +mpdu_ht_control_field + + Field only valid when mpdu_qos_control_valid is set + + + + The HT control field of the MPDU + + +*/ + + + /* EXTERNAL REFERENCE : struct rxpt_classify_info rxpt_classify_info_details */ + + +/* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW2 ring + + Reo will push the frame + into the REO2SW3 ring + + Reo will push the frame + into the REO2SW4 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + Reo will push the frame + into the REO2SW5 ring (REO remaps this in chips without + REO2SW5 ring, e.g. Pine) + + Reo will push the frame + into the REO2SW6 ring (REO remaps this in chips without + REO2SW6 ring, e.g. Pine) + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + +*/ +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +/* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB + + If use_flow_id_toeplitz_clfy is set and lmac_peer_id_'sb + is 2'b00, Rx OLE uses a REO desination indicati'n of {1'b1, + hash[3:0]} using the chosen Toeplitz hash from Common Parser + if flow search fails. + + If use_flow_id_toeplitz_clfy is set and lmac_peer_id_msb + 's not 2'b00, Rx OLE uses a REO desination indication of + {lmac_peer_id_msb, hash[2:0]} using the chosen Toeplitz hash + from Common Parser if flow search fails. + + This LMAC/peer-based routing is not supported in + Hastings80 and HastingsPrime. + + +*/ +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 + +/* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY + + Indication to Rx OLE to enable REO destination routing + based on the chosen Toeplitz hash from Common Parser, in + case flow search fails + + +*/ +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 + +/* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA + + Filter pass Unicast data frame (matching + rxpcu_filter_pass and sw_frame_group_Unicast_data) routing + selection + + + + 1'b0: source and destination rings are selected from the + RxOLE register settings for the packet type + + + + 1'b1: source ring and destination ring is selected from + the rxdma0_source_ring_selection and + rxdma0_destination_ring_selection fields in this STRUCT + + +*/ +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 + +/* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA + + Filter pass Multicast data frame (matching + rxpcu_filter_pass and sw_frame_group_Multicast_data) routing + selection + + + + 1'b0: source and destination rings are selected from the + RxOLE register settings for the packet type + + + + 1'b1: source ring and destination ring is selected from + the rxdma0_source_ring_selection and + rxdma0_destination_ring_selection fields in this STRUCT + + +*/ +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 + +/* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000 + + Filter pass BAR frame (matching rxpcu_filter_pass and + sw_frame_group_ctrl_1000) routing selection + + + + 1'b0: source and destination rings are selected from the + RxOLE register settings for the packet type + + + + 1'b1: source ring and destination ring is selected from + the rxdma0_source_ring_selection and + rxdma0_destination_ring_selection fields in this STRUCT + + +*/ +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 + +/* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION + + Field only valid when for the received frame type the + corresponding pkt_selection_fp_... bit is set + + + + The data buffer for + + The data buffer for + this frame shall be sourced by fw2rxdma buffer source ring. + + The data buffer for + this frame shall be sourced by sw2rxdma buffer source ring. + + The frame shall not be written + to any data buffer. + + + + +*/ +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00001800 + +/* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION + + Field only valid when for the received frame type the + corresponding pkt_selection_fp_... bit is set + + + + RXDMA0 shall push the frame + to the Release ring. Effectively this means the frame needs + to be dropped. + + RXDMA0 shall push the frame to + the FW ring. + + RXDMA0 shall push the frame to + the SW ring. + + RXDMA0 shall push the frame to + the REO entrance ring. + + + + +*/ +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 13 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x00006000 + +/* Description RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B + + +*/ +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 15 +#define RX_MPDU_INFO_0_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xffff8000 + +/* Description RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0 + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Address (lower 32 bits) of the REO queue descriptor. + + + + If no Peer entry lookup happened for this frame, the + value wil be set to 0, and the frame shall never be pushed + to REO entrance ring. + + +*/ +#define RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 +#define RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define RX_MPDU_INFO_1_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +/* Description RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32 + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Address (upper 8 bits) of the REO queue descriptor. + + + + If no Peer entry lookup happened for this frame, the + value wil be set to 0, and the frame shall never be pushed + to REO entrance ring. + + +*/ +#define RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define RX_MPDU_INFO_2_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +/* Description RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Indicates the MPDU queue ID to which this MPDU link + descriptor belongs + + Used for tracking and debugging + + +*/ +#define RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER_LSB 8 +#define RX_MPDU_INFO_2_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 + +/* Description RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING + + Indicates that a delimiter FCS error was found in + between the Previous MPDU and this MPDU. + + + + Note that this is just a warning, and does not mean that + this MPDU is corrupted in any way. If it is, there will be + other errors indicated such as FCS or decrypt errors + + + + In case of ndp or phy_err, this field will indicate at + least one of delimiters located after the last MPDU in the + previous PPDU has been corrupted. +*/ +#define RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING_LSB 24 +#define RX_MPDU_INFO_2_PRE_DELIM_ERR_WARNING_MASK 0x01000000 + +/* Description RX_MPDU_INFO_2_FIRST_DELIM_ERR + + Indicates that the first delimiter had a FCS failure. + Only valid when first_mpdu and first_msdu are set. + + + +*/ +#define RX_MPDU_INFO_2_FIRST_DELIM_ERR_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_FIRST_DELIM_ERR_LSB 25 +#define RX_MPDU_INFO_2_FIRST_DELIM_ERR_MASK 0x02000000 + +/* Description RX_MPDU_INFO_2_RESERVED_2A + + +*/ +#define RX_MPDU_INFO_2_RESERVED_2A_OFFSET 0x00000008 +#define RX_MPDU_INFO_2_RESERVED_2A_LSB 26 +#define RX_MPDU_INFO_2_RESERVED_2A_MASK 0xfc000000 + +/* Description RX_MPDU_INFO_3_PN_31_0 + + + + + + WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] + is valid. + + TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, + WEPSeed[1], pn1}. Only pn[47:0] is valid. + + AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, + pn1, pn0}. Only pn[47:0] is valid. + + WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, + pn11, pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, + pn0}. pn[127:0] are valid. + + + +*/ +#define RX_MPDU_INFO_3_PN_31_0_OFFSET 0x0000000c +#define RX_MPDU_INFO_3_PN_31_0_LSB 0 +#define RX_MPDU_INFO_3_PN_31_0_MASK 0xffffffff + +/* Description RX_MPDU_INFO_4_PN_63_32 + + + + + Bits [63:32] of the PN number. See description for + pn_31_0. + + + +*/ +#define RX_MPDU_INFO_4_PN_63_32_OFFSET 0x00000010 +#define RX_MPDU_INFO_4_PN_63_32_LSB 0 +#define RX_MPDU_INFO_4_PN_63_32_MASK 0xffffffff + +/* Description RX_MPDU_INFO_5_PN_95_64 + + + + + Bits [95:64] of the PN number. See description for + pn_31_0. + + + +*/ +#define RX_MPDU_INFO_5_PN_95_64_OFFSET 0x00000014 +#define RX_MPDU_INFO_5_PN_95_64_LSB 0 +#define RX_MPDU_INFO_5_PN_95_64_MASK 0xffffffff + +/* Description RX_MPDU_INFO_6_PN_127_96 + + + + + Bits [127:96] of the PN number. See description for + pn_31_0. + + + +*/ +#define RX_MPDU_INFO_6_PN_127_96_OFFSET 0x00000018 +#define RX_MPDU_INFO_6_PN_127_96_LSB 0 +#define RX_MPDU_INFO_6_PN_127_96_MASK 0xffffffff + +/* Description RX_MPDU_INFO_7_EPD_EN + + Field only valid when AST_based_lookup_valid == 1. + + + + + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + If set to one use EPD instead of LPD + + + + + +*/ +#define RX_MPDU_INFO_7_EPD_EN_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_EPD_EN_LSB 0 +#define RX_MPDU_INFO_7_EPD_EN_MASK 0x00000001 + +/* Description RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + When set, all frames (data only ?) shall be encrypted. + If not, RX CRYPTO shall set an error flag. + + +*/ +#define RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 +#define RX_MPDU_INFO_7_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 + +/* Description RX_MPDU_INFO_7_ENCRYPT_TYPE + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Indicates type of decrypt cipher used (as defined in the + peer entry) + + + + WEP 40-bit + + WEP 104-bit + + TKIP without MIC + + WEP 128-bit + + TKIP with MIC + + WAPI + + AES CCMP 128 + + No crypto + + AES CCMP 256 + + AES CCMP 128 + + AES CCMP 256 + + WAPI GCM SM4 + + + + WEP encryption. As for WEP + per keyid the key bit width can vary, the key bit width for + this MPDU will be indicated in field + wep_key_width_for_variable key + + +*/ +#define RX_MPDU_INFO_7_ENCRYPT_TYPE_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_ENCRYPT_TYPE_LSB 2 +#define RX_MPDU_INFO_7_ENCRYPT_TYPE_MASK 0x0000003c + +/* Description RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY + + Field only valid when key_type is set to + wep_varied_width. + + + + This field indicates the size of the wep key for this + MPDU. + + + + WEP 40-bit + + WEP 104-bit + + WEP 128-bit + + + + +*/ +#define RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 +#define RX_MPDU_INFO_7_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 + +/* Description RX_MPDU_INFO_7_MESH_STA + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + When set, this is a Mesh (11s) STA. + + + + The interpretation of the A-MSDU 'Length' field in the + MPDU (if any) is decided by the e-numerations below. + + + + + + A-MSDU 'Length' is big endian and + includes the length of Mesh Control. + + A-MSDU 'Length' is big endian and + excludes the length of Mesh Control. + + A-MSDU 'Length' is little endian + and excludes the length of Mesh Control. This is + 802.11s-compliant. + + +*/ +#define RX_MPDU_INFO_7_MESH_STA_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_MESH_STA_LSB 8 +#define RX_MPDU_INFO_7_MESH_STA_MASK 0x00000300 + +/* Description RX_MPDU_INFO_7_BSSID_HIT + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + When set, the BSSID of the incoming frame matched one of + the 8 BSSID register values + + + + +*/ +#define RX_MPDU_INFO_7_BSSID_HIT_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_BSSID_HIT_LSB 10 +#define RX_MPDU_INFO_7_BSSID_HIT_MASK 0x00000400 + +/* Description RX_MPDU_INFO_7_BSSID_NUMBER + + Field only valid when bssid_hit is set. + + + + This number indicates which one out of the 8 BSSID + register values matched the incoming frame + + +*/ +#define RX_MPDU_INFO_7_BSSID_NUMBER_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_BSSID_NUMBER_LSB 11 +#define RX_MPDU_INFO_7_BSSID_NUMBER_MASK 0x00007800 + +/* Description RX_MPDU_INFO_7_TID + + Field only valid when mpdu_qos_control_valid is set + + + + The TID field in the QoS control field + + +*/ +#define RX_MPDU_INFO_7_TID_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_TID_LSB 15 +#define RX_MPDU_INFO_7_TID_MASK 0x00078000 + +/* Description RX_MPDU_INFO_7_RESERVED_7A + + +*/ +#define RX_MPDU_INFO_7_RESERVED_7A_OFFSET 0x0000001c +#define RX_MPDU_INFO_7_RESERVED_7A_LSB 19 +#define RX_MPDU_INFO_7_RESERVED_7A_MASK 0xfff80000 + +/* Description RX_MPDU_INFO_8_PEER_META_DATA + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + + +*/ +#define RX_MPDU_INFO_8_PEER_META_DATA_OFFSET 0x00000020 +#define RX_MPDU_INFO_8_PEER_META_DATA_LSB 0 +#define RX_MPDU_INFO_8_PEER_META_DATA_MASK 0xffffffff + +/* Description RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + + This MPDU passed the normal + frame filter programming of rxpcu + + This MPDU did NOT pass the + regular frame filter and would have been dropped, were it + not for the frame fitting into the 'monitor_client' + category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the + rxpcu_monitor_client filter. It would have been dropped + accept that it did pass the 'monitor_other' category. + + + + Note: for ndp frame, if it was expected because the + preceding NDPA was filter_pass, the setting + rxpcu_filter_pass will be used. This setting will also be + used for every ndp frame in case Promiscuous mode is + enabled. + + + + In case promiscuous is not enabled, and an NDP is not + preceded by a NPDA filter pass frame, the only other setting + that could appear here for the NDP is rxpcu_monitor_other. + + (rxpcu has a configuration bit specifically for this + scenario) + + + + Note: for + + +*/ +#define RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MPDU_INFO_9_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +/* Description RX_MPDU_INFO_9_SW_FRAME_GROUP_ID + + SW processes frames based on certain classifications. + This field indicates to what sw classification this MPDU is + mapped. + + The classification is given in priority order + + + + Note: The + corresponding Rxpcu_Mpdu_filter_in_category can be + rxpcu_filter_pass or rxpcu_monitor_other + + + + + + + + This includes mpdus + of type Data Null as well as QoS Data Null + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + Note: The corresponding Rxpcu_Mpdu_filter_in_category + can only be rxpcu_monitor_other + + + + + Note: The corresponding Rxpcu_Mpdu_filter_in_category + can be rxpcu_filter_pass + + + + +*/ +#define RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK 0x000001fc + +/* Description RX_MPDU_INFO_9_NDP_FRAME + + When set, the received frame was an NDP frame, and thus + there will be no MPDU data. + + +*/ +#define RX_MPDU_INFO_9_NDP_FRAME_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_NDP_FRAME_LSB 9 +#define RX_MPDU_INFO_9_NDP_FRAME_MASK 0x00000200 + +/* Description RX_MPDU_INFO_9_PHY_ERR + + When set, a PHY error was received before MAC received + any data, and thus there will be no MPDU data. + + +*/ +#define RX_MPDU_INFO_9_PHY_ERR_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_PHY_ERR_LSB 10 +#define RX_MPDU_INFO_9_PHY_ERR_MASK 0x00000400 + +/* Description RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER + + When set, a PHY error was received before MAC received + the complete MPDU header which was needed for proper + decoding + + +*/ +#define RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER_LSB 11 +#define RX_MPDU_INFO_9_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 + +/* Description RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR + + Set when RXPCU detected a version error in the Frame + control field + + +*/ +#define RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR_LSB 12 +#define RX_MPDU_INFO_9_PROTOCOL_VERSION_ERR_MASK 0x00001000 + +/* Description RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID + + When set, AST based lookup for this frame has found a + valid result. + + + + Note that for NDP frame this will never be set + + +*/ +#define RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID_LSB 13 +#define RX_MPDU_INFO_9_AST_BASED_LOOKUP_VALID_MASK 0x00002000 + +/* Description RX_MPDU_INFO_9_RESERVED_9A + + +*/ +#define RX_MPDU_INFO_9_RESERVED_9A_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_RESERVED_9A_LSB 14 +#define RX_MPDU_INFO_9_RESERVED_9A_MASK 0x0000c000 + +/* Description RX_MPDU_INFO_9_PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + +*/ +#define RX_MPDU_INFO_9_PHY_PPDU_ID_OFFSET 0x00000024 +#define RX_MPDU_INFO_9_PHY_PPDU_ID_LSB 16 +#define RX_MPDU_INFO_9_PHY_PPDU_ID_MASK 0xffff0000 + +/* Description RX_MPDU_INFO_10_AST_INDEX + + This field indicates the index of the AST entry + corresponding to this MPDU. It is provided by the GSE module + instantiated in RXPCU. + + A value of 0xFFFF indicates an invalid AST index, + meaning that No AST entry was found or NO AST search was + performed + + + + In case of ndp or phy_err, this field will be set to + 0xFFFF + + +*/ +#define RX_MPDU_INFO_10_AST_INDEX_OFFSET 0x00000028 +#define RX_MPDU_INFO_10_AST_INDEX_LSB 0 +#define RX_MPDU_INFO_10_AST_INDEX_MASK 0x0000ffff + +/* Description RX_MPDU_INFO_10_SW_PEER_ID + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + This field indicates a unique peer identifier. It is set + equal to field 'sw_peer_id' from the AST entry + + + + +*/ +#define RX_MPDU_INFO_10_SW_PEER_ID_OFFSET 0x00000028 +#define RX_MPDU_INFO_10_SW_PEER_ID_LSB 16 +#define RX_MPDU_INFO_10_SW_PEER_ID_MASK 0xffff0000 + +/* Description RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID + + When set, the field Mpdu_Frame_control_field has valid + information + + + + + +*/ +#define RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_LSB 0 +#define RX_MPDU_INFO_11_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 + +/* Description RX_MPDU_INFO_11_MPDU_DURATION_VALID + + When set, the field Mpdu_duration_field has valid + information + + + + + +*/ +#define RX_MPDU_INFO_11_MPDU_DURATION_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MPDU_DURATION_VALID_LSB 1 +#define RX_MPDU_INFO_11_MPDU_DURATION_VALID_MASK 0x00000002 + +/* Description RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID + + When set, the fields mac_addr_ad1_..... have valid + information + + + + + +*/ +#define RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_LSB 2 +#define RX_MPDU_INFO_11_MAC_ADDR_AD1_VALID_MASK 0x00000004 + +/* Description RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID + + When set, the fields mac_addr_ad2_..... have valid + information + + + + + + + + +*/ +#define RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_LSB 3 +#define RX_MPDU_INFO_11_MAC_ADDR_AD2_VALID_MASK 0x00000008 + +/* Description RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID + + When set, the fields mac_addr_ad3_..... have valid + information + + + + + + + + +*/ +#define RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_LSB 4 +#define RX_MPDU_INFO_11_MAC_ADDR_AD3_VALID_MASK 0x00000010 + +/* Description RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID + + When set, the fields mac_addr_ad4_..... have valid + information + + + + + + + + +*/ +#define RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_LSB 5 +#define RX_MPDU_INFO_11_MAC_ADDR_AD4_VALID_MASK 0x00000020 + +/* Description RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID + + When set, the fields mpdu_sequence_control_field and + mpdu_sequence_number have valid information as well as field + + + + For MPDUs without a sequence control field, this field + will not be set. + + + + + +*/ +#define RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 +#define RX_MPDU_INFO_11_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 + +/* Description RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID + + When set, the field mpdu_qos_control_field has valid + information + + + + For MPDUs without a QoS control field, this field will + not be set. + + + + + +*/ +#define RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB 7 +#define RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 + +/* Description RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID + + When set, the field mpdu_HT_control_field has valid + information + + + + For MPDUs without a HT control field, this field will + not be set. + + + + + +*/ +#define RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID_LSB 8 +#define RX_MPDU_INFO_11_MPDU_HT_CONTROL_VALID_MASK 0x00000100 + +/* Description RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID + + When set, the encryption related info fields, like IV + and PN are valid + + + + For MPDUs that are not encrypted, this will not be set. + + + + + +*/ +#define RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_LSB 9 +#define RX_MPDU_INFO_11_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 + +/* Description RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER + + Field only valid when Mpdu_sequence_control_valid is set + AND Fragment_flag is set + + + + The fragment number from the 802.11 header + + + + +*/ +#define RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER_LSB 10 +#define RX_MPDU_INFO_11_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 + +/* Description RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG + + The More Fragment bit setting from the MPDU header of + the received frame + + + + +*/ +#define RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG_LSB 14 +#define RX_MPDU_INFO_11_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +/* Description RX_MPDU_INFO_11_RESERVED_11A + + +*/ +#define RX_MPDU_INFO_11_RESERVED_11A_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_RESERVED_11A_LSB 15 +#define RX_MPDU_INFO_11_RESERVED_11A_MASK 0x00008000 + +/* Description RX_MPDU_INFO_11_FR_DS + + Field only valid when Mpdu_frame_control_valid is set + + + + Set if the from DS bit is set in the frame control. + + +*/ +#define RX_MPDU_INFO_11_FR_DS_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_FR_DS_LSB 16 +#define RX_MPDU_INFO_11_FR_DS_MASK 0x00010000 + +/* Description RX_MPDU_INFO_11_TO_DS + + Field only valid when Mpdu_frame_control_valid is set + + + + Set if the to DS bit is set in the frame control. + + +*/ +#define RX_MPDU_INFO_11_TO_DS_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_TO_DS_LSB 17 +#define RX_MPDU_INFO_11_TO_DS_MASK 0x00020000 + +/* Description RX_MPDU_INFO_11_ENCRYPTED + + Field only valid when Mpdu_frame_control_valid is set. + + + + Protected bit from the frame control. + + +*/ +#define RX_MPDU_INFO_11_ENCRYPTED_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_ENCRYPTED_LSB 18 +#define RX_MPDU_INFO_11_ENCRYPTED_MASK 0x00040000 + +/* Description RX_MPDU_INFO_11_MPDU_RETRY + + Field only valid when Mpdu_frame_control_valid is set. + + + + Retry bit from the frame control. Only valid when + first_msdu is set. + + +*/ +#define RX_MPDU_INFO_11_MPDU_RETRY_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MPDU_RETRY_LSB 19 +#define RX_MPDU_INFO_11_MPDU_RETRY_MASK 0x00080000 + +/* Description RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER + + Field only valid when Mpdu_sequence_control_valid is + set. + + + + The sequence number from the 802.11 header. + + +*/ +#define RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000002c +#define RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_LSB 20 +#define RX_MPDU_INFO_11_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 + +/* Description RX_MPDU_INFO_12_KEY_ID_OCTET + + + + + The key ID octet from the IV. + + + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + +*/ +#define RX_MPDU_INFO_12_KEY_ID_OCTET_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_KEY_ID_OCTET_LSB 0 +#define RX_MPDU_INFO_12_KEY_ID_OCTET_MASK 0x000000ff + +/* Description RX_MPDU_INFO_12_NEW_PEER_ENTRY + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Set if new RX_PEER_ENTRY TLV follows. If clear, + RX_PEER_ENTRY doesn't follow so RX DECRYPTION module either + uses old peer entry or not decrypt. + + +*/ +#define RX_MPDU_INFO_12_NEW_PEER_ENTRY_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_NEW_PEER_ENTRY_LSB 8 +#define RX_MPDU_INFO_12_NEW_PEER_ENTRY_MASK 0x00000100 + +/* Description RX_MPDU_INFO_12_DECRYPT_NEEDED + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Set if decryption is needed. + + + + Note: + + When RXPCU sets bit 'ast_index_not_found' and/or + ast_index_timeout', RXPCU will also ensure that this bit is + NOT set + + CRYPTO for that reason only needs to evaluate this bit + and non of the other ones. + + +*/ +#define RX_MPDU_INFO_12_DECRYPT_NEEDED_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_DECRYPT_NEEDED_LSB 9 +#define RX_MPDU_INFO_12_DECRYPT_NEEDED_MASK 0x00000200 + +/* Description RX_MPDU_INFO_12_DECAP_TYPE + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Used by the OLE during decapsulation. + + + + Indicates the decapsulation that HW will perform: + + + + No encapsulation + + + + Ethernet 2 (DIX) or 802.3 (uses + SNAP/LLC) + + Indicate Ethernet + + + + +*/ +#define RX_MPDU_INFO_12_DECAP_TYPE_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_DECAP_TYPE_LSB 10 +#define RX_MPDU_INFO_12_DECAP_TYPE_MASK 0x00000c00 + +/* Description RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Insert 4 byte of all zeros as VLAN tag if the rx payload + does not have VLAN. Used during decapsulation. + + +*/ +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 + +/* Description RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Insert 4 byte of all zeros as double VLAN tag if the rx + payload does not have VLAN. Used during + + +*/ +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 +#define RX_MPDU_INFO_12_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 + +/* Description RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Strip the VLAN during decapsulation.  Used by the OLE. + + +*/ +#define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_LSB 14 +#define RX_MPDU_INFO_12_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 + +/* Description RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Strip the double VLAN during decapsulation.  Used by + the OLE. + + +*/ +#define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_LSB 15 +#define RX_MPDU_INFO_12_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 + +/* Description RX_MPDU_INFO_12_PRE_DELIM_COUNT + + The number of delimiters before this MPDU. + + + + Note that this number is cleared at PPDU start. + + + + If this MPDU is the first received MPDU in the PPDU and + this MPDU gets filtered-in, this field will indicate the + number of delimiters located after the last MPDU in the + previous PPDU. + + + + If this MPDU is located after the first received MPDU in + an PPDU, this field will indicate the number of delimiters + located between the previous MPDU and this MPDU. + + + + In case of ndp or phy_err, this field will indicate the + number of delimiters located after the last MPDU in the + previous PPDU. + + +*/ +#define RX_MPDU_INFO_12_PRE_DELIM_COUNT_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_PRE_DELIM_COUNT_LSB 16 +#define RX_MPDU_INFO_12_PRE_DELIM_COUNT_MASK 0x0fff0000 + +/* Description RX_MPDU_INFO_12_AMPDU_FLAG + + When set, received frame was part of an A-MPDU. + + + + + +*/ +#define RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_AMPDU_FLAG_LSB 28 +#define RX_MPDU_INFO_12_AMPDU_FLAG_MASK 0x10000000 + +/* Description RX_MPDU_INFO_12_BAR_FRAME + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + When set, received frame is a BAR frame + + +*/ +#define RX_MPDU_INFO_12_BAR_FRAME_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_BAR_FRAME_LSB 29 +#define RX_MPDU_INFO_12_BAR_FRAME_MASK 0x20000000 + +/* Description RX_MPDU_INFO_12_RAW_MPDU + + Consumer: SW + + Producer: RXOLE + + + + RXPCU sets this field to 0 and RXOLE overwrites it. + + + + Set to 1 by RXOLE when it has not performed any 802.11 + to Ethernet/Natvie WiFi header conversion on this MPDU. + + +*/ +#define RX_MPDU_INFO_12_RAW_MPDU_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_RAW_MPDU_LSB 30 +#define RX_MPDU_INFO_12_RAW_MPDU_MASK 0x40000000 + +/* Description RX_MPDU_INFO_12_RESERVED_12 + + +*/ +#define RX_MPDU_INFO_12_RESERVED_12_OFFSET 0x00000030 +#define RX_MPDU_INFO_12_RESERVED_12_LSB 31 +#define RX_MPDU_INFO_12_RESERVED_12_MASK 0x80000000 + +/* Description RX_MPDU_INFO_13_MPDU_LENGTH + + In case of ndp or phy_err this field will be set to 0 + + + + MPDU length before decapsulation. + + +*/ +#define RX_MPDU_INFO_13_MPDU_LENGTH_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_MPDU_LENGTH_LSB 0 +#define RX_MPDU_INFO_13_MPDU_LENGTH_MASK 0x00003fff + +/* Description RX_MPDU_INFO_13_FIRST_MPDU + + See definition in RX attention descriptor + + + + In case of ndp or phy_err, this field will be set. Note + however that there will not actually be any data contents in + the MPDU. + + +*/ +#define RX_MPDU_INFO_13_FIRST_MPDU_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_FIRST_MPDU_LSB 14 +#define RX_MPDU_INFO_13_FIRST_MPDU_MASK 0x00004000 + +/* Description RX_MPDU_INFO_13_MCAST_BCAST + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_MCAST_BCAST_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_MCAST_BCAST_LSB 15 +#define RX_MPDU_INFO_13_MCAST_BCAST_MASK 0x00008000 + +/* Description RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_LSB 16 +#define RX_MPDU_INFO_13_AST_INDEX_NOT_FOUND_MASK 0x00010000 + +/* Description RX_MPDU_INFO_13_AST_INDEX_TIMEOUT + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_LSB 17 +#define RX_MPDU_INFO_13_AST_INDEX_TIMEOUT_MASK 0x00020000 + +/* Description RX_MPDU_INFO_13_POWER_MGMT + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_POWER_MGMT_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_POWER_MGMT_LSB 18 +#define RX_MPDU_INFO_13_POWER_MGMT_MASK 0x00040000 + +/* Description RX_MPDU_INFO_13_NON_QOS + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 1 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_NON_QOS_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_NON_QOS_LSB 19 +#define RX_MPDU_INFO_13_NON_QOS_MASK 0x00080000 + +/* Description RX_MPDU_INFO_13_NULL_DATA + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_NULL_DATA_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_NULL_DATA_LSB 20 +#define RX_MPDU_INFO_13_NULL_DATA_MASK 0x00100000 + +/* Description RX_MPDU_INFO_13_MGMT_TYPE + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_MGMT_TYPE_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_MGMT_TYPE_LSB 21 +#define RX_MPDU_INFO_13_MGMT_TYPE_MASK 0x00200000 + +/* Description RX_MPDU_INFO_13_CTRL_TYPE + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_CTRL_TYPE_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_CTRL_TYPE_LSB 22 +#define RX_MPDU_INFO_13_CTRL_TYPE_MASK 0x00400000 + +/* Description RX_MPDU_INFO_13_MORE_DATA + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_MORE_DATA_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_MORE_DATA_LSB 23 +#define RX_MPDU_INFO_13_MORE_DATA_MASK 0x00800000 + +/* Description RX_MPDU_INFO_13_EOSP + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_EOSP_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_EOSP_LSB 24 +#define RX_MPDU_INFO_13_EOSP_MASK 0x01000000 + +/* Description RX_MPDU_INFO_13_FRAGMENT_FLAG + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_FRAGMENT_FLAG_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_FRAGMENT_FLAG_LSB 25 +#define RX_MPDU_INFO_13_FRAGMENT_FLAG_MASK 0x02000000 + +/* Description RX_MPDU_INFO_13_ORDER + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + + +*/ +#define RX_MPDU_INFO_13_ORDER_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_ORDER_LSB 26 +#define RX_MPDU_INFO_13_ORDER_MASK 0x04000000 + +/* Description RX_MPDU_INFO_13_U_APSD_TRIGGER + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_U_APSD_TRIGGER_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_U_APSD_TRIGGER_LSB 27 +#define RX_MPDU_INFO_13_U_APSD_TRIGGER_MASK 0x08000000 + +/* Description RX_MPDU_INFO_13_ENCRYPT_REQUIRED + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_LSB 28 +#define RX_MPDU_INFO_13_ENCRYPT_REQUIRED_MASK 0x10000000 + +/* Description RX_MPDU_INFO_13_DIRECTED + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_INFO_13_DIRECTED_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_DIRECTED_LSB 29 +#define RX_MPDU_INFO_13_DIRECTED_MASK 0x20000000 + +/* Description RX_MPDU_INFO_13_AMSDU_PRESENT + + Field only valid when Mpdu_qos_control_valid is set + + + + The 'amsdu_present' bit within the QoS control field of + the MPDU + + +*/ +#define RX_MPDU_INFO_13_AMSDU_PRESENT_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_AMSDU_PRESENT_LSB 30 +#define RX_MPDU_INFO_13_AMSDU_PRESENT_MASK 0x40000000 + +/* Description RX_MPDU_INFO_13_RESERVED_13 + + +*/ +#define RX_MPDU_INFO_13_RESERVED_13_OFFSET 0x00000034 +#define RX_MPDU_INFO_13_RESERVED_13_LSB 31 +#define RX_MPDU_INFO_13_RESERVED_13_MASK 0x80000000 + +/* Description RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD + + Field only valid when Mpdu_frame_control_valid is set + + + + The frame control field of this received MPDU. + + + + Field only valid when Ndp_frame and phy_err are NOT set + + + + Bytes 0 + 1 of the received MPDU + + +*/ +#define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 +#define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB 0 +#define RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff + +/* Description RX_MPDU_INFO_14_MPDU_DURATION_FIELD + + Field only valid when Mpdu_duration_valid is set + + + + The duration field of this received MPDU. + + +*/ +#define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_OFFSET 0x00000038 +#define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_LSB 16 +#define RX_MPDU_INFO_14_MPDU_DURATION_FIELD_MASK 0xffff0000 + +/* Description RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0 + + Field only valid when mac_addr_ad1_valid is set + + + + The Least Significant 4 bytes of the Received Frames MAC + Address AD1 + + +*/ +#define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c +#define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_LSB 0 +#define RX_MPDU_INFO_15_MAC_ADDR_AD1_31_0_MASK 0xffffffff + +/* Description RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32 + + Field only valid when mac_addr_ad1_valid is set + + + + The 2 most significant bytes of the Received Frames MAC + Address AD1 + + +*/ +#define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 +#define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_LSB 0 +#define RX_MPDU_INFO_16_MAC_ADDR_AD1_47_32_MASK 0x0000ffff + +/* Description RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0 + + Field only valid when mac_addr_ad2_valid is set + + + + The Least Significant 2 bytes of the Received Frames MAC + Address AD2 + + +*/ +#define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 +#define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_LSB 16 +#define RX_MPDU_INFO_16_MAC_ADDR_AD2_15_0_MASK 0xffff0000 + +/* Description RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16 + + Field only valid when mac_addr_ad2_valid is set + + + + The 4 most significant bytes of the Received Frames MAC + Address AD2 + + +*/ +#define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 +#define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_LSB 0 +#define RX_MPDU_INFO_17_MAC_ADDR_AD2_47_16_MASK 0xffffffff + +/* Description RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0 + + Field only valid when mac_addr_ad3_valid is set + + + + The Least Significant 4 bytes of the Received Frames MAC + Address AD3 + + +*/ +#define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 +#define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_LSB 0 +#define RX_MPDU_INFO_18_MAC_ADDR_AD3_31_0_MASK 0xffffffff + +/* Description RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32 + + Field only valid when mac_addr_ad3_valid is set + + + + The 2 most significant bytes of the Received Frames MAC + Address AD3 + + +*/ +#define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c +#define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_LSB 0 +#define RX_MPDU_INFO_19_MAC_ADDR_AD3_47_32_MASK 0x0000ffff + +/* Description RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD + + + + + The sequence control field of the MPDU + + +*/ +#define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c +#define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 +#define RX_MPDU_INFO_19_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 + +/* Description RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0 + + Field only valid when mac_addr_ad4_valid is set + + + + The Least Significant 4 bytes of the Received Frames MAC + Address AD4 + + +*/ +#define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 +#define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB 0 +#define RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK 0xffffffff + +/* Description RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32 + + Field only valid when mac_addr_ad4_valid is set + + + + The 2 most significant bytes of the Received Frames MAC + Address AD4 + + +*/ +#define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 +#define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB 0 +#define RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK 0x0000ffff + +/* Description RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD + + Field only valid when mpdu_qos_control_valid is set + + + + The sequence control field of the MPDU + + +*/ +#define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 +#define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_LSB 16 +#define RX_MPDU_INFO_21_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 + +/* Description RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD + + Field only valid when mpdu_qos_control_valid is set + + + + The HT control field of the MPDU + + +*/ +#define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 +#define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_LSB 0 +#define RX_MPDU_INFO_22_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff + + +#endif // _RX_MPDU_INFO_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/rx_mpdu_link_ptr.h b/drivers/staging/fw-api/hw/qca6750/v1/rx_mpdu_link_ptr.h new file mode 100644 index 000000000000..f3864679dbcf --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/rx_mpdu_link_ptr.h @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_MPDU_LINK_PTR_H_ +#define _RX_MPDU_LINK_PTR_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct buffer_addr_info mpdu_link_desc_addr_info; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_MPDU_LINK_PTR 2 + +struct rx_mpdu_link_ptr { + struct buffer_addr_info mpdu_link_desc_addr_info; +}; + +/* + +struct buffer_addr_info mpdu_link_desc_addr_info + + Details of the physical address of an MPDU link + descriptor +*/ + + + /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ + + +/* Description RX_MPDU_LINK_PTR_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_MPDU_LINK_PTR_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define RX_MPDU_LINK_PTR_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_MPDU_LINK_PTR_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + +*/ +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_MPDU_LINK_PTR_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + + +#endif // _RX_MPDU_LINK_PTR_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/rx_mpdu_start.h b/drivers/staging/fw-api/hw/qca6750/v1/rx_mpdu_start.h new file mode 100644 index 000000000000..5a7cca70b880 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/rx_mpdu_start.h @@ -0,0 +1,1981 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_MPDU_START_H_ +#define _RX_MPDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_mpdu_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-22 struct rx_mpdu_info rx_mpdu_info_details; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_MPDU_START 23 + +struct rx_mpdu_start { + struct rx_mpdu_info rx_mpdu_info_details; +}; + +/* + +struct rx_mpdu_info rx_mpdu_info_details + + Structure containing all the MPDU header details that + might be needed for other modules further down the received + path +*/ + + + /* EXTERNAL REFERENCE : struct rx_mpdu_info rx_mpdu_info_details */ + + + /* EXTERNAL REFERENCE : struct rxpt_classify_info rxpt_classify_info_details */ + + +/* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW2 ring + + Reo will push the frame + into the REO2SW3 ring + + Reo will push the frame + into the REO2SW4 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + Reo will push the frame + into the REO2SW5 ring (REO remaps this in chips without + REO2SW5 ring, e.g. Pine) + + Reo will push the frame + into the REO2SW6 ring (REO remaps this in chips without + REO2SW6 ring, e.g. Pine) + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + +*/ +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 0 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x0000001f + +/* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB + + If use_flow_id_toeplitz_clfy is set and lmac_peer_id_'sb + is 2'b00, Rx OLE uses a REO desination indicati'n of {1'b1, + hash[3:0]} using the chosen Toeplitz hash from Common Parser + if flow search fails. + + If use_flow_id_toeplitz_clfy is set and lmac_peer_id_msb + 's not 2'b00, Rx OLE uses a REO desination indication of + {lmac_peer_id_msb, hash[2:0]} using the chosen Toeplitz hash + from Common Parser if flow search fails. + + This LMAC/peer-based routing is not supported in + Hastings80 and HastingsPrime. + + +*/ +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_LSB 5 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_LMAC_PEER_ID_MSB_MASK 0x00000060 + +/* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY + + Indication to Rx OLE to enable REO destination routing + based on the chosen Toeplitz hash from Common Parser, in + case flow search fails + + +*/ +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 + +/* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA + + Filter pass Unicast data frame (matching + rxpcu_filter_pass and sw_frame_group_Unicast_data) routing + selection + + + + 1'b0: source and destination rings are selected from the + RxOLE register settings for the packet type + + + + 1'b1: source ring and destination ring is selected from + the rxdma0_source_ring_selection and + rxdma0_destination_ring_selection fields in this STRUCT + + +*/ +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_LSB 8 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 + +/* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA + + Filter pass Multicast data frame (matching + rxpcu_filter_pass and sw_frame_group_Multicast_data) routing + selection + + + + 1'b0: source and destination rings are selected from the + RxOLE register settings for the packet type + + + + 1'b1: source ring and destination ring is selected from + the rxdma0_source_ring_selection and + rxdma0_destination_ring_selection fields in this STRUCT + + +*/ +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_LSB 9 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 + +/* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000 + + Filter pass BAR frame (matching rxpcu_filter_pass and + sw_frame_group_ctrl_1000) routing selection + + + + 1'b0: source and destination rings are selected from the + RxOLE register settings for the packet type + + + + 1'b1: source ring and destination ring is selected from + the rxdma0_source_ring_selection and + rxdma0_destination_ring_selection fields in this STRUCT + + +*/ +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_LSB 10 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_PKT_SELECTION_FP_1000_MASK 0x00000400 + +/* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION + + Field only valid when for the received frame type the + corresponding pkt_selection_fp_... bit is set + + + + The data buffer for + + The data buffer for + this frame shall be sourced by fw2rxdma buffer source ring. + + The data buffer for + this frame shall be sourced by sw2rxdma buffer source ring. + + The frame shall not be written + to any data buffer. + + + + +*/ +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_LSB 11 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00001800 + +/* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION + + Field only valid when for the received frame type the + corresponding pkt_selection_fp_... bit is set + + + + RXDMA0 shall push the frame + to the Release ring. Effectively this means the frame needs + to be dropped. + + RXDMA0 shall push the frame to + the FW ring. + + RXDMA0 shall push the frame to + the SW ring. + + RXDMA0 shall push the frame to + the REO entrance ring. + + + + +*/ +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_LSB 13 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x00006000 + +/* Description RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B + + +*/ +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_LSB 15 +#define RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPT_CLASSIFY_INFO_DETAILS_RESERVED_0B_MASK 0xffff8000 + +/* Description RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0 + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Address (lower 32 bits) of the REO queue descriptor. + + + + If no Peer entry lookup happened for this frame, the + value wil be set to 0, and the frame shall never be pushed + to REO entrance ring. + + +*/ +#define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET 0x00000004 +#define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_LSB 0 +#define RX_MPDU_START_1_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_31_0_MASK 0xffffffff + +/* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32 + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Address (upper 8 bits) of the REO queue descriptor. + + + + If no Peer entry lookup happened for this frame, the + value wil be set to 0, and the frame shall never be pushed + to REO entrance ring. + + +*/ +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_OFFSET 0x00000008 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_LSB 0 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RX_REO_QUEUE_DESC_ADDR_39_32_MASK 0x000000ff + +/* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Indicates the MPDU queue ID to which this MPDU link + descriptor belongs + + Used for tracking and debugging + + +*/ +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000008 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_LSB 8 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RECEIVE_QUEUE_NUMBER_MASK 0x00ffff00 + +/* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING + + Indicates that a delimiter FCS error was found in + between the Previous MPDU and this MPDU. + + + + Note that this is just a warning, and does not mean that + this MPDU is corrupted in any way. If it is, there will be + other errors indicated such as FCS or decrypt errors + + + + In case of ndp or phy_err, this field will indicate at + least one of delimiters located after the last MPDU in the + previous PPDU has been corrupted. +*/ +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_OFFSET 0x00000008 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_LSB 24 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_PRE_DELIM_ERR_WARNING_MASK 0x01000000 + +/* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR + + Indicates that the first delimiter had a FCS failure. + Only valid when first_mpdu and first_msdu are set. + + + +*/ +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_OFFSET 0x00000008 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_LSB 25 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_FIRST_DELIM_ERR_MASK 0x02000000 + +/* Description RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A + + +*/ +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A_OFFSET 0x00000008 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A_LSB 26 +#define RX_MPDU_START_2_RX_MPDU_INFO_DETAILS_RESERVED_2A_MASK 0xfc000000 + +/* Description RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0 + + + + + + WEP: IV = {key_id_octet, pn2, pn1, pn0}. Only pn[23:0] + is valid. + + TKIP: IV = {pn5, pn4, pn3, pn2, key_id_octet, pn0, + WEPSeed[1], pn1}. Only pn[47:0] is valid. + + AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, + pn1, pn0}. Only pn[47:0] is valid. + + WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, + pn11, pn10, pn9, pn8, pn7, pn6, pn5, pn4, pn3, pn2, pn1, + pn0}. pn[127:0] are valid. + + + +*/ +#define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0_OFFSET 0x0000000c +#define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0_LSB 0 +#define RX_MPDU_START_3_RX_MPDU_INFO_DETAILS_PN_31_0_MASK 0xffffffff + +/* Description RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32 + + + + + Bits [63:32] of the PN number. See description for + pn_31_0. + + + +*/ +#define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32_OFFSET 0x00000010 +#define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32_LSB 0 +#define RX_MPDU_START_4_RX_MPDU_INFO_DETAILS_PN_63_32_MASK 0xffffffff + +/* Description RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64 + + + + + Bits [95:64] of the PN number. See description for + pn_31_0. + + + +*/ +#define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64_OFFSET 0x00000014 +#define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64_LSB 0 +#define RX_MPDU_START_5_RX_MPDU_INFO_DETAILS_PN_95_64_MASK 0xffffffff + +/* Description RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96 + + + + + Bits [127:96] of the PN number. See description for + pn_31_0. + + + +*/ +#define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96_OFFSET 0x00000018 +#define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96_LSB 0 +#define RX_MPDU_START_6_RX_MPDU_INFO_DETAILS_PN_127_96_MASK 0xffffffff + +/* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN + + Field only valid when AST_based_lookup_valid == 1. + + + + + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + If set to one use EPD instead of LPD + + + + + +*/ +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN_LSB 0 +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_EPD_EN_MASK 0x00000001 + +/* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + When set, all frames (data only ?) shall be encrypted. + If not, RX CRYPTO shall set an error flag. + + +*/ +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_LSB 1 +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ALL_FRAMES_SHALL_BE_ENCRYPTED_MASK 0x00000002 + +/* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Indicates type of decrypt cipher used (as defined in the + peer entry) + + + + WEP 40-bit + + WEP 104-bit + + TKIP without MIC + + WEP 128-bit + + TKIP with MIC + + WAPI + + AES CCMP 128 + + No crypto + + AES CCMP 256 + + AES CCMP 128 + + AES CCMP 256 + + WAPI GCM SM4 + + + + WEP encryption. As for WEP + per keyid the key bit width can vary, the key bit width for + this MPDU will be indicated in field + wep_key_width_for_variable key + + +*/ +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_LSB 2 +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_ENCRYPT_TYPE_MASK 0x0000003c + +/* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY + + Field only valid when key_type is set to + wep_varied_width. + + + + This field indicates the size of the wep key for this + MPDU. + + + + WEP 40-bit + + WEP 104-bit + + WEP 128-bit + + + + +*/ +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_LSB 6 +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_WEP_KEY_WIDTH_FOR_VARIABLE_KEY_MASK 0x000000c0 + +/* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_MESH_STA + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + When set, this is a Mesh (11s) STA. + + + + The interpretation of the A-MSDU 'Length' field in the + MPDU (if any) is decided by the e-numerations below. + + + + + + A-MSDU 'Length' is big endian and + includes the length of Mesh Control. + + A-MSDU 'Length' is big endian and + excludes the length of Mesh Control. + + A-MSDU 'Length' is little endian + and excludes the length of Mesh Control. This is + 802.11s-compliant. + + +*/ +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_MESH_STA_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_MESH_STA_LSB 8 +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_MESH_STA_MASK 0x00000300 + +/* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + When set, the BSSID of the incoming frame matched one of + the 8 BSSID register values + + + + +*/ +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT_LSB 10 +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_HIT_MASK 0x00000400 + +/* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER + + Field only valid when bssid_hit is set. + + + + This number indicates which one out of the 8 BSSID + register values matched the incoming frame + + +*/ +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_LSB 11 +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_BSSID_NUMBER_MASK 0x00007800 + +/* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID + + Field only valid when mpdu_qos_control_valid is set + + + + The TID field in the QoS control field + + +*/ +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID_LSB 15 +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_TID_MASK 0x00078000 + +/* Description RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_7A + + +*/ +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_7A_OFFSET 0x0000001c +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_7A_LSB 19 +#define RX_MPDU_START_7_RX_MPDU_INFO_DETAILS_RESERVED_7A_MASK 0xfff80000 + +/* Description RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + + +*/ +#define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_OFFSET 0x00000020 +#define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define RX_MPDU_START_8_RX_MPDU_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + +/* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + + This MPDU passed the normal + frame filter programming of rxpcu + + This MPDU did NOT pass the + regular frame filter and would have been dropped, were it + not for the frame fitting into the 'monitor_client' + category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the + rxpcu_monitor_client filter. It would have been dropped + accept that it did pass the 'monitor_other' category. + + + + Note: for ndp frame, if it was expected because the + preceding NDPA was filter_pass, the setting + rxpcu_filter_pass will be used. This setting will also be + used for every ndp frame in case Promiscuous mode is + enabled. + + + + In case promiscuous is not enabled, and an NDP is not + preceded by a NPDA filter pass frame, the only other setting + that could appear here for the NDP is rxpcu_monitor_other. + + (rxpcu has a configuration bit specifically for this + scenario) + + + + Note: for + + +*/ +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +/* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID + + SW processes frames based on certain classifications. + This field indicates to what sw classification this MPDU is + mapped. + + The classification is given in priority order + + + + Note: The + corresponding Rxpcu_Mpdu_filter_in_category can be + rxpcu_filter_pass or rxpcu_monitor_other + + + + + + + + This includes mpdus + of type Data Null as well as QoS Data Null + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + Note: The corresponding Rxpcu_Mpdu_filter_in_category + can only be rxpcu_monitor_other + + + + + Note: The corresponding Rxpcu_Mpdu_filter_in_category + can be rxpcu_filter_pass + + + + +*/ +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_SW_FRAME_GROUP_ID_MASK 0x000001fc + +/* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME + + When set, the received frame was an NDP frame, and thus + there will be no MPDU data. + + +*/ +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME_LSB 9 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_NDP_FRAME_MASK 0x00000200 + +/* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR + + When set, a PHY error was received before MAC received + any data, and thus there will be no MPDU data. + + +*/ +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_LSB 10 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_MASK 0x00000400 + +/* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER + + When set, a PHY error was received before MAC received + the complete MPDU header which was needed for proper + decoding + + +*/ +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_LSB 11 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_ERR_DURING_MPDU_HEADER_MASK 0x00000800 + +/* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR + + Set when RXPCU detected a version error in the Frame + control field + + +*/ +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_LSB 12 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PROTOCOL_VERSION_ERR_MASK 0x00001000 + +/* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID + + When set, AST based lookup for this frame has found a + valid result. + + + + Note that for NDP frame this will never be set + + +*/ +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_LSB 13 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_AST_BASED_LOOKUP_VALID_MASK 0x00002000 + +/* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_9A + + +*/ +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_9A_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_9A_LSB 14 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RESERVED_9A_MASK 0x0000c000 + +/* Description RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + +*/ +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000024 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_LSB 16 +#define RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_PHY_PPDU_ID_MASK 0xffff0000 + +/* Description RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX + + This field indicates the index of the AST entry + corresponding to this MPDU. It is provided by the GSE module + instantiated in RXPCU. + + A value of 0xFFFF indicates an invalid AST index, + meaning that No AST entry was found or NO AST search was + performed + + + + In case of ndp or phy_err, this field will be set to + 0xFFFF + + +*/ +#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX_OFFSET 0x00000028 +#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX_LSB 0 +#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_AST_INDEX_MASK 0x0000ffff + +/* Description RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + This field indicates a unique peer identifier. It is set + equal to field 'sw_peer_id' from the AST entry + + + + +*/ +#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID_OFFSET 0x00000028 +#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID_LSB 16 +#define RX_MPDU_START_10_RX_MPDU_INFO_DETAILS_SW_PEER_ID_MASK 0xffff0000 + +/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID + + When set, the field Mpdu_Frame_control_field has valid + information + + + + + +*/ +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_LSB 0 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_VALID_MASK 0x00000001 + +/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID + + When set, the field Mpdu_duration_field has valid + information + + + + + +*/ +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_LSB 1 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_DURATION_VALID_MASK 0x00000002 + +/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID + + When set, the fields mac_addr_ad1_..... have valid + information + + + + + +*/ +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_LSB 2 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_VALID_MASK 0x00000004 + +/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID + + When set, the fields mac_addr_ad2_..... have valid + information + + + + + + + + +*/ +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_LSB 3 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_VALID_MASK 0x00000008 + +/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID + + When set, the fields mac_addr_ad3_..... have valid + information + + + + + + + + +*/ +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_LSB 4 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_VALID_MASK 0x00000010 + +/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID + + When set, the fields mac_addr_ad4_..... have valid + information + + + + + + + + +*/ +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_LSB 5 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_VALID_MASK 0x00000020 + +/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID + + When set, the fields mpdu_sequence_control_field and + mpdu_sequence_number have valid information as well as field + + + + For MPDUs without a sequence control field, this field + will not be set. + + + + + +*/ +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_LSB 6 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_VALID_MASK 0x00000040 + +/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID + + When set, the field mpdu_qos_control_field has valid + information + + + + For MPDUs without a QoS control field, this field will + not be set. + + + + + +*/ +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_LSB 7 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_VALID_MASK 0x00000080 + +/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID + + When set, the field mpdu_HT_control_field has valid + information + + + + For MPDUs without a HT control field, this field will + not be set. + + + + + +*/ +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_LSB 8 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_VALID_MASK 0x00000100 + +/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID + + When set, the encryption related info fields, like IV + and PN are valid + + + + For MPDUs that are not encrypted, this will not be set. + + + + + +*/ +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_LSB 9 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FRAME_ENCRYPTION_INFO_VALID_MASK 0x00000200 + +/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER + + Field only valid when Mpdu_sequence_control_valid is set + AND Fragment_flag is set + + + + The fragment number from the 802.11 header + + + + +*/ +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_LSB 10 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_FRAGMENT_NUMBER_MASK 0x00003c00 + +/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG + + The More Fragment bit setting from the MPDU header of + the received frame + + + + +*/ +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 14 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x00004000 + +/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11A + + +*/ +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11A_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11A_LSB 15 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_RESERVED_11A_MASK 0x00008000 + +/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS + + Field only valid when Mpdu_frame_control_valid is set + + + + Set if the from DS bit is set in the frame control. + + +*/ +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS_LSB 16 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_FR_DS_MASK 0x00010000 + +/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS + + Field only valid when Mpdu_frame_control_valid is set + + + + Set if the to DS bit is set in the frame control. + + +*/ +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS_LSB 17 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_TO_DS_MASK 0x00020000 + +/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED + + Field only valid when Mpdu_frame_control_valid is set. + + + + Protected bit from the frame control. + + +*/ +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED_LSB 18 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_ENCRYPTED_MASK 0x00040000 + +/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY + + Field only valid when Mpdu_frame_control_valid is set. + + + + Retry bit from the frame control. Only valid when + first_msdu is set. + + +*/ +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY_LSB 19 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_RETRY_MASK 0x00080000 + +/* Description RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER + + Field only valid when Mpdu_sequence_control_valid is + set. + + + + The sequence number from the 802.11 header. + + +*/ +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000002c +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 20 +#define RX_MPDU_START_11_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0xfff00000 + +/* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET + + + + + The key ID octet from the IV. + + + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + +*/ +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_LSB 0 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_KEY_ID_OCTET_MASK 0x000000ff + +/* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Set if new RX_PEER_ENTRY TLV follows. If clear, + RX_PEER_ENTRY doesn't follow so RX DECRYPTION module either + uses old peer entry or not decrypt. + + +*/ +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_LSB 8 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_NEW_PEER_ENTRY_MASK 0x00000100 + +/* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Set if decryption is needed. + + + + Note: + + When RXPCU sets bit 'ast_index_not_found' and/or + ast_index_timeout', RXPCU will also ensure that this bit is + NOT set + + CRYPTO for that reason only needs to evaluate this bit + and non of the other ones. + + +*/ +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_LSB 9 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECRYPT_NEEDED_MASK 0x00000200 + +/* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Used by the OLE during decapsulation. + + + + Indicates the decapsulation that HW will perform: + + + + No encapsulation + + + + Ethernet 2 (DIX) or 802.3 (uses + SNAP/LLC) + + Indicate Ethernet + + + + +*/ +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_LSB 10 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_DECAP_TYPE_MASK 0x00000c00 + +/* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Insert 4 byte of all zeros as VLAN tag if the rx payload + does not have VLAN. Used during decapsulation. + + +*/ +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_LSB 12 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_C_TAG_PADDING_MASK 0x00001000 + +/* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Insert 4 byte of all zeros as double VLAN tag if the rx + payload does not have VLAN. Used during + + +*/ +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_LSB 13 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RX_INSERT_VLAN_S_TAG_PADDING_MASK 0x00002000 + +/* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Strip the VLAN during decapsulation.  Used by the OLE. + + +*/ +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_LSB 14 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_C_TAG_DECAP_MASK 0x00004000 + +/* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + Strip the double VLAN during decapsulation.  Used by + the OLE. + + +*/ +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_LSB 15 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_STRIP_VLAN_S_TAG_DECAP_MASK 0x00008000 + +/* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT + + The number of delimiters before this MPDU. + + + + Note that this number is cleared at PPDU start. + + + + If this MPDU is the first received MPDU in the PPDU and + this MPDU gets filtered-in, this field will indicate the + number of delimiters located after the last MPDU in the + previous PPDU. + + + + If this MPDU is located after the first received MPDU in + an PPDU, this field will indicate the number of delimiters + located between the previous MPDU and this MPDU. + + + + In case of ndp or phy_err, this field will indicate the + number of delimiters located after the last MPDU in the + previous PPDU. + + +*/ +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_LSB 16 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_PRE_DELIM_COUNT_MASK 0x0fff0000 + +/* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG + + When set, received frame was part of an A-MPDU. + + + + + +*/ +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_LSB 28 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_AMPDU_FLAG_MASK 0x10000000 + +/* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME + + In case of ndp or phy_err or AST_based_lookup_valid == + 0, this field will be set to 0 + + + + When set, received frame is a BAR frame + + +*/ +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_LSB 29 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_BAR_FRAME_MASK 0x20000000 + +/* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU + + Consumer: SW + + Producer: RXOLE + + + + RXPCU sets this field to 0 and RXOLE overwrites it. + + + + Set to 1 by RXOLE when it has not performed any 802.11 + to Ethernet/Natvie WiFi header conversion on this MPDU. + + +*/ +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU_LSB 30 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 + +/* Description RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12 + + +*/ +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_OFFSET 0x00000030 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_LSB 31 +#define RX_MPDU_START_12_RX_MPDU_INFO_DETAILS_RESERVED_12_MASK 0x80000000 + +/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH + + In case of ndp or phy_err this field will be set to 0 + + + + MPDU length before decapsulation. + + +*/ +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_LSB 0 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MPDU_LENGTH_MASK 0x00003fff + +/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU + + See definition in RX attention descriptor + + + + In case of ndp or phy_err, this field will be set. Note + however that there will not actually be any data contents in + the MPDU. + + +*/ +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_LSB 14 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FIRST_MPDU_MASK 0x00004000 + +/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_LSB 15 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MCAST_BCAST_MASK 0x00008000 + +/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_LSB 16 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_NOT_FOUND_MASK 0x00010000 + +/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_LSB 17 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AST_INDEX_TIMEOUT_MASK 0x00020000 + +/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_LSB 18 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_POWER_MGMT_MASK 0x00040000 + +/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 1 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_LSB 19 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NON_QOS_MASK 0x00080000 + +/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_LSB 20 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_NULL_DATA_MASK 0x00100000 + +/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_LSB 21 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MGMT_TYPE_MASK 0x00200000 + +/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_LSB 22 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_CTRL_TYPE_MASK 0x00400000 + +/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_LSB 23 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_MORE_DATA_MASK 0x00800000 + +/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_LSB 24 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_EOSP_MASK 0x01000000 + +/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_LSB 25 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x02000000 + +/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + + + +*/ +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_LSB 26 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ORDER_MASK 0x04000000 + +/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_LSB 27 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_U_APSD_TRIGGER_MASK 0x08000000 + +/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_LSB 28 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_ENCRYPT_REQUIRED_MASK 0x10000000 + +/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED + + In case of ndp or phy_err or Phy_err_during_mpdu_header + this field will be set to 0 + + + + See definition in RX attention descriptor + + +*/ +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_LSB 29 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_DIRECTED_MASK 0x20000000 + +/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT + + Field only valid when Mpdu_qos_control_valid is set + + + + The 'amsdu_present' bit within the QoS control field of + the MPDU + + +*/ +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_LSB 30 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_AMSDU_PRESENT_MASK 0x40000000 + +/* Description RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13 + + +*/ +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_OFFSET 0x00000034 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_LSB 31 +#define RX_MPDU_START_13_RX_MPDU_INFO_DETAILS_RESERVED_13_MASK 0x80000000 + +/* Description RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD + + Field only valid when Mpdu_frame_control_valid is set + + + + The frame control field of this received MPDU. + + + + Field only valid when Ndp_frame and phy_err are NOT set + + + + Bytes 0 + 1 of the received MPDU + + +*/ +#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_OFFSET 0x00000038 +#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_LSB 0 +#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_FRAME_CONTROL_FIELD_MASK 0x0000ffff + +/* Description RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD + + Field only valid when Mpdu_duration_valid is set + + + + The duration field of this received MPDU. + + +*/ +#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_OFFSET 0x00000038 +#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_LSB 16 +#define RX_MPDU_START_14_RX_MPDU_INFO_DETAILS_MPDU_DURATION_FIELD_MASK 0xffff0000 + +/* Description RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0 + + Field only valid when mac_addr_ad1_valid is set + + + + The Least Significant 4 bytes of the Received Frames MAC + Address AD1 + + +*/ +#define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_OFFSET 0x0000003c +#define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_LSB 0 +#define RX_MPDU_START_15_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_31_0_MASK 0xffffffff + +/* Description RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32 + + Field only valid when mac_addr_ad1_valid is set + + + + The 2 most significant bytes of the Received Frames MAC + Address AD1 + + +*/ +#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_OFFSET 0x00000040 +#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_LSB 0 +#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD1_47_32_MASK 0x0000ffff + +/* Description RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0 + + Field only valid when mac_addr_ad2_valid is set + + + + The Least Significant 2 bytes of the Received Frames MAC + Address AD2 + + +*/ +#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_OFFSET 0x00000040 +#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_LSB 16 +#define RX_MPDU_START_16_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_15_0_MASK 0xffff0000 + +/* Description RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16 + + Field only valid when mac_addr_ad2_valid is set + + + + The 4 most significant bytes of the Received Frames MAC + Address AD2 + + +*/ +#define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_OFFSET 0x00000044 +#define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_LSB 0 +#define RX_MPDU_START_17_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD2_47_16_MASK 0xffffffff + +/* Description RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0 + + Field only valid when mac_addr_ad3_valid is set + + + + The Least Significant 4 bytes of the Received Frames MAC + Address AD3 + + +*/ +#define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_OFFSET 0x00000048 +#define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_LSB 0 +#define RX_MPDU_START_18_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_31_0_MASK 0xffffffff + +/* Description RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32 + + Field only valid when mac_addr_ad3_valid is set + + + + The 2 most significant bytes of the Received Frames MAC + Address AD3 + + +*/ +#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_OFFSET 0x0000004c +#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_LSB 0 +#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD3_47_32_MASK 0x0000ffff + +/* Description RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD + + + + + The sequence control field of the MPDU + + +*/ +#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_OFFSET 0x0000004c +#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_LSB 16 +#define RX_MPDU_START_19_RX_MPDU_INFO_DETAILS_MPDU_SEQUENCE_CONTROL_FIELD_MASK 0xffff0000 + +/* Description RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0 + + Field only valid when mac_addr_ad4_valid is set + + + + The Least Significant 4 bytes of the Received Frames MAC + Address AD4 + + +*/ +#define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_OFFSET 0x00000050 +#define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_LSB 0 +#define RX_MPDU_START_20_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_31_0_MASK 0xffffffff + +/* Description RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32 + + Field only valid when mac_addr_ad4_valid is set + + + + The 2 most significant bytes of the Received Frames MAC + Address AD4 + + +*/ +#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_OFFSET 0x00000054 +#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_LSB 0 +#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MAC_ADDR_AD4_47_32_MASK 0x0000ffff + +/* Description RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD + + Field only valid when mpdu_qos_control_valid is set + + + + The sequence control field of the MPDU + + +*/ +#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_OFFSET 0x00000054 +#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_LSB 16 +#define RX_MPDU_START_21_RX_MPDU_INFO_DETAILS_MPDU_QOS_CONTROL_FIELD_MASK 0xffff0000 + +/* Description RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD + + Field only valid when mpdu_qos_control_valid is set + + + + The HT control field of the MPDU + + +*/ +#define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_OFFSET 0x00000058 +#define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_LSB 0 +#define RX_MPDU_START_22_RX_MPDU_INFO_DETAILS_MPDU_HT_CONTROL_FIELD_MASK 0xffffffff + + +#endif // _RX_MPDU_START_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/rx_msdu_desc_info.h b/drivers/staging/fw-api/hw/qca6750/v1/rx_msdu_desc_info.h new file mode 100644 index 000000000000..020df7aa0210 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/rx_msdu_desc_info.h @@ -0,0 +1,629 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_MSDU_DESC_INFO_H_ +#define _RX_MSDU_DESC_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 first_msdu_in_mpdu_flag[0], last_msdu_in_mpdu_flag[1], msdu_continuation[2], msdu_length[16:3], reo_destination_indication[21:17], msdu_drop[22], sa_is_valid[23], sa_idx_timeout[24], da_is_valid[25], da_is_mcbc[26], da_idx_timeout[27], reserved_0a[31:28] +// 1 reserved_1a[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_MSDU_DESC_INFO 2 + +struct rx_msdu_desc_info { + uint32_t first_msdu_in_mpdu_flag : 1, //[0] + last_msdu_in_mpdu_flag : 1, //[1] + msdu_continuation : 1, //[2] + msdu_length : 14, //[16:3] + reo_destination_indication : 5, //[21:17] + msdu_drop : 1, //[22] + sa_is_valid : 1, //[23] + sa_idx_timeout : 1, //[24] + da_is_valid : 1, //[25] + da_is_mcbc : 1, //[26] + da_idx_timeout : 1, //[27] + reserved_0a : 4; //[31:28] + uint32_t reserved_1a : 32; //[31:0] +}; + +/* + +first_msdu_in_mpdu_flag + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + This is not the first MSDU in + the MPDU. + + This MSDU is the first one in the + MPDU. + + + + + +last_msdu_in_mpdu_flag + + Consumer: WBM/REO/SW/FW + + Producer: RXDMA + + + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + There are more MSDUs linked to + this MSDU that belongs to this MPDU + + this MSDU is the last one in the + MPDU. This setting is only allowed in combination with + 'Msdu_continuation' set to 0. This implies that when an msdu + is spread out over multiple buffers and thus + msdu_continuation is set, only for the very last buffer of + the msdu, can the 'last_msdu_in_mpdu_flag' be set. + + + + When both first_msdu_in_mpdu_flag and + last_msdu_in_mpdu_flag are set, the MPDU that this MSDU + belongs to only contains a single MSDU. + + + + + + + +msdu_continuation + + When set, this MSDU buffer was not able to hold the + entire MSDU. The next buffer will therefor contain + additional information related to this MSDU. + + + + + +msdu_length + + Parsed from RX_MSDU_START TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the First + buffer used by MSDU. + + + + Full MSDU length in bytes after decapsulation. + + + + This field is still valid for MPDU frames without + A-MSDU. It still represents MSDU length after decapsulation + + + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + + + +reo_destination_indication + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW2 ring + + Reo will push the frame + into the REO2SW3 ring + + Reo will push the frame + into the REO2SW4 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + Reo will push the frame + into the REO2SW5 ring (REO remaps this in chips without + REO2SW5 ring, e.g. Pine) + + Reo will push the frame + into the REO2SW6 ring (REO remaps this in chips without + REO2SW6 ring, e.g. Pine) + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + + +msdu_drop + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + When set, REO shall drop this MSDU and not forward it to + any other ring... + + + +sa_is_valid + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates that OLE found a valid SA entry for this MSDU + + + +sa_idx_timeout + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates an unsuccessful MAC source address search due + to the expiring of the search timer for this MSDU + + + +da_is_valid + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates that OLE found a valid DA entry for this MSDU + + + +da_is_mcbc + + Field Only valid if da_is_valid is set + + + + Indicates the DA address was a Multicast of Broadcast + address for this MSDU + + + +da_idx_timeout + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates an unsuccessful MAC destination address search + due to the expiring of the search timer for this MSDU + + + +reserved_0a + + + +reserved_1a + + +*/ + + +/* Description RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + This is not the first MSDU in + the MPDU. + + This MSDU is the first one in the + MPDU. + + + + +*/ +#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +/* Description RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG + + Consumer: WBM/REO/SW/FW + + Producer: RXDMA + + + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + There are more MSDUs linked to + this MSDU that belongs to this MPDU + + this MSDU is the last one in the + MPDU. This setting is only allowed in combination with + 'Msdu_continuation' set to 0. This implies that when an msdu + is spread out over multiple buffers and thus + msdu_continuation is set, only for the very last buffer of + the msdu, can the 'last_msdu_in_mpdu_flag' be set. + + + + When both first_msdu_in_mpdu_flag and + last_msdu_in_mpdu_flag are set, the MPDU that this MSDU + belongs to only contains a single MSDU. + + + + + + +*/ +#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +/* Description RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION + + When set, this MSDU buffer was not able to hold the + entire MSDU. The next buffer will therefor contain + additional information related to this MSDU. + + + + +*/ +#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK 0x00000004 + +/* Description RX_MSDU_DESC_INFO_0_MSDU_LENGTH + + Parsed from RX_MSDU_START TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the First + buffer used by MSDU. + + + + Full MSDU length in bytes after decapsulation. + + + + This field is still valid for MPDU frames without + A-MSDU. It still represents MSDU length after decapsulation + + + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + + +*/ +#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_LSB 3 +#define RX_MSDU_DESC_INFO_0_MSDU_LENGTH_MASK 0x0001fff8 + +/* Description RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW2 ring + + Reo will push the frame + into the REO2SW3 ring + + Reo will push the frame + into the REO2SW4 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + Reo will push the frame + into the REO2SW5 ring (REO remaps this in chips without + REO2SW5 ring, e.g. Pine) + + Reo will push the frame + into the REO2SW6 ring (REO remaps this in chips without + REO2SW6 ring, e.g. Pine) + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + +*/ +#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_LSB 17 +#define RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +/* Description RX_MSDU_DESC_INFO_0_MSDU_DROP + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + When set, REO shall drop this MSDU and not forward it to + any other ring... + + +*/ +#define RX_MSDU_DESC_INFO_0_MSDU_DROP_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_MSDU_DROP_LSB 22 +#define RX_MSDU_DESC_INFO_0_MSDU_DROP_MASK 0x00400000 + +/* Description RX_MSDU_DESC_INFO_0_SA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates that OLE found a valid SA entry for this MSDU + + +*/ +#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_LSB 23 +#define RX_MSDU_DESC_INFO_0_SA_IS_VALID_MASK 0x00800000 + +/* Description RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates an unsuccessful MAC source address search due + to the expiring of the search timer for this MSDU + + +*/ +#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_LSB 24 +#define RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK 0x01000000 + +/* Description RX_MSDU_DESC_INFO_0_DA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates that OLE found a valid DA entry for this MSDU + + +*/ +#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_LSB 25 +#define RX_MSDU_DESC_INFO_0_DA_IS_VALID_MASK 0x02000000 + +/* Description RX_MSDU_DESC_INFO_0_DA_IS_MCBC + + Field Only valid if da_is_valid is set + + + + Indicates the DA address was a Multicast of Broadcast + address for this MSDU + + +*/ +#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_LSB 26 +#define RX_MSDU_DESC_INFO_0_DA_IS_MCBC_MASK 0x04000000 + +/* Description RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates an unsuccessful MAC destination address search + due to the expiring of the search timer for this MSDU + + +*/ +#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_LSB 27 +#define RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK 0x08000000 + +/* Description RX_MSDU_DESC_INFO_0_RESERVED_0A + + +*/ +#define RX_MSDU_DESC_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define RX_MSDU_DESC_INFO_0_RESERVED_0A_LSB 28 +#define RX_MSDU_DESC_INFO_0_RESERVED_0A_MASK 0xf0000000 + +/* Description RX_MSDU_DESC_INFO_1_RESERVED_1A + + +*/ +#define RX_MSDU_DESC_INFO_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_MSDU_DESC_INFO_1_RESERVED_1A_LSB 0 +#define RX_MSDU_DESC_INFO_1_RESERVED_1A_MASK 0xffffffff + + +#endif // _RX_MSDU_DESC_INFO_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/rx_msdu_details.h b/drivers/staging/fw-api/hw/qca6750/v1/rx_msdu_details.h new file mode 100644 index 000000000000..dc1a46c08707 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/rx_msdu_details.h @@ -0,0 +1,547 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_MSDU_DETAILS_H_ +#define _RX_MSDU_DETAILS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#include "rx_msdu_desc_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct buffer_addr_info buffer_addr_info_details; +// 2-3 struct rx_msdu_desc_info rx_msdu_desc_info_details; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_MSDU_DETAILS 4 + +struct rx_msdu_details { + struct buffer_addr_info buffer_addr_info_details; + struct rx_msdu_desc_info rx_msdu_desc_info_details; +}; + +/* + +struct buffer_addr_info buffer_addr_info_details + + Consumer: REO/SW + + Producer: RXDMA + + + + Details of the physical address of the buffer containing + an MSDU (or entire MPDU) + +struct rx_msdu_desc_info rx_msdu_desc_info_details + + Consumer: REO/SW + + Producer: RXDMA + + + + General information related to the MSDU that should be + passed on from RXDMA all the way to to the REO destination + ring. +*/ + + + /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */ + + +/* Description RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_DETAILS_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + +*/ +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 +#define RX_MSDU_DETAILS_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 + + /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ + + +/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + This is not the first MSDU in + the MPDU. + + This MSDU is the first one in the + MPDU. + + + + +*/ +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG + + Consumer: WBM/REO/SW/FW + + Producer: RXDMA + + + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + There are more MSDUs linked to + this MSDU that belongs to this MPDU + + this MSDU is the last one in the + MPDU. This setting is only allowed in combination with + 'Msdu_continuation' set to 0. This implies that when an msdu + is spread out over multiple buffers and thus + msdu_continuation is set, only for the very last buffer of + the msdu, can the 'last_msdu_in_mpdu_flag' be set. + + + + When both first_msdu_in_mpdu_flag and + last_msdu_in_mpdu_flag are set, the MPDU that this MSDU + belongs to only contains a single MSDU. + + + + + + +*/ +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION + + When set, this MSDU buffer was not able to hold the + entire MSDU. The next buffer will therefor contain + additional information related to this MSDU. + + + + +*/ +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH + + Parsed from RX_MSDU_START TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the First + buffer used by MSDU. + + + + Full MSDU length in bytes after decapsulation. + + + + This field is still valid for MPDU frames without + A-MSDU. It still represents MSDU length after decapsulation + + + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + + +*/ +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW2 ring + + Reo will push the frame + into the REO2SW3 ring + + Reo will push the frame + into the REO2SW4 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + Reo will push the frame + into the REO2SW5 ring (REO remaps this in chips without + REO2SW5 ring, e.g. Pine) + + Reo will push the frame + into the REO2SW6 ring (REO remaps this in chips without + REO2SW6 ring, e.g. Pine) + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + +*/ +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + When set, REO shall drop this MSDU and not forward it to + any other ring... + + +*/ +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 + +/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates that OLE found a valid SA entry for this MSDU + + +*/ +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 + +/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates an unsuccessful MAC source address search due + to the expiring of the search timer for this MSDU + + +*/ +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 + +/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates that OLE found a valid DA entry for this MSDU + + +*/ +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 + +/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC + + Field Only valid if da_is_valid is set + + + + Indicates the DA address was a Multicast of Broadcast + address for this MSDU + + +*/ +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 + +/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates an unsuccessful MAC destination address search + due to the expiring of the search timer for this MSDU + + +*/ +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 + +/* Description RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A + + +*/ +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000008 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28 +#define RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000 + +/* Description RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A + + +*/ +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000c +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0 +#define RX_MSDU_DETAILS_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff + + +#endif // _RX_MSDU_DETAILS_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/rx_msdu_end.h b/drivers/staging/fw-api/hw/qca6750/v1/rx_msdu_end.h new file mode 100644 index 000000000000..93302914cd64 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/rx_msdu_end.h @@ -0,0 +1,1597 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_MSDU_END_H_ +#define _RX_MSDU_END_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16] +// 1 ip_hdr_chksum[15:0], reported_mpdu_length[29:16], reserved_1a[31:30] +// 2 key_id_octet[7:0], cce_super_rule[13:8], cce_classify_not_done_truncate[14], cce_classify_not_done_cce_dis[15], cumulative_l3_checksum[31:16] +// 3 rule_indication_31_0[31:0] +// 4 rule_indication_63_32[31:0] +// 5 da_offset[5:0], sa_offset[11:6], da_offset_valid[12], sa_offset_valid[13], reserved_5a[15:14], l3_type[31:16] +// 6 ipv6_options_crc[31:0] +// 7 tcp_seq_number[31:0] +// 8 tcp_ack_number[31:0] +// 9 tcp_flag[8:0], lro_eligible[9], reserved_9a[15:10], window_size[31:16] +// 10 tcp_udp_chksum[15:0], sa_idx_timeout[16], da_idx_timeout[17], msdu_limit_error[18], flow_idx_timeout[19], flow_idx_invalid[20], wifi_parser_error[21], amsdu_parser_error[22], sa_is_valid[23], da_is_valid[24], da_is_mcbc[25], l3_header_padding[27:26], first_msdu[28], last_msdu[29], tcp_udp_chksum_fail[30], ip_chksum_fail[31] +// 11 sa_idx[15:0], da_idx_or_sw_peer_id[31:16] +// 12 msdu_drop[0], reo_destination_indication[5:1], flow_idx[25:6], reserved_12a[31:26] +// 13 fse_metadata[31:0] +// 14 cce_metadata[15:0], sa_sw_peer_id[31:16] +// 15 aggregation_count[7:0], flow_aggregation_continuation[8], fisa_timeout[9], reserved_15a[31:10] +// 16 cumulative_l4_checksum[15:0], cumulative_ip_length[31:16] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_MSDU_END 17 + +struct rx_msdu_end { + uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] + sw_frame_group_id : 7, //[8:2] + reserved_0 : 7, //[15:9] + phy_ppdu_id : 16; //[31:16] + uint32_t ip_hdr_chksum : 16, //[15:0] + reported_mpdu_length : 14, //[29:16] + reserved_1a : 2; //[31:30] + uint32_t key_id_octet : 8, //[7:0] + cce_super_rule : 6, //[13:8] + cce_classify_not_done_truncate : 1, //[14] + cce_classify_not_done_cce_dis : 1, //[15] + cumulative_l3_checksum : 16; //[31:16] + uint32_t rule_indication_31_0 : 32; //[31:0] + uint32_t rule_indication_63_32 : 32; //[31:0] + uint32_t da_offset : 6, //[5:0] + sa_offset : 6, //[11:6] + da_offset_valid : 1, //[12] + sa_offset_valid : 1, //[13] + reserved_5a : 2, //[15:14] + l3_type : 16; //[31:16] + uint32_t ipv6_options_crc : 32; //[31:0] + uint32_t tcp_seq_number : 32; //[31:0] + uint32_t tcp_ack_number : 32; //[31:0] + uint32_t tcp_flag : 9, //[8:0] + lro_eligible : 1, //[9] + reserved_9a : 6, //[15:10] + window_size : 16; //[31:16] + uint32_t tcp_udp_chksum : 16, //[15:0] + sa_idx_timeout : 1, //[16] + da_idx_timeout : 1, //[17] + msdu_limit_error : 1, //[18] + flow_idx_timeout : 1, //[19] + flow_idx_invalid : 1, //[20] + wifi_parser_error : 1, //[21] + amsdu_parser_error : 1, //[22] + sa_is_valid : 1, //[23] + da_is_valid : 1, //[24] + da_is_mcbc : 1, //[25] + l3_header_padding : 2, //[27:26] + first_msdu : 1, //[28] + last_msdu : 1, //[29] + tcp_udp_chksum_fail : 1, //[30] + ip_chksum_fail : 1; //[31] + uint32_t sa_idx : 16, //[15:0] + da_idx_or_sw_peer_id : 16; //[31:16] + uint32_t msdu_drop : 1, //[0] + reo_destination_indication : 5, //[5:1] + flow_idx : 20, //[25:6] + reserved_12a : 6; //[31:26] + uint32_t fse_metadata : 32; //[31:0] + uint32_t cce_metadata : 16, //[15:0] + sa_sw_peer_id : 16; //[31:16] + uint32_t aggregation_count : 8, //[7:0] + flow_aggregation_continuation : 1, //[8] + fisa_timeout : 1, //[9] + reserved_15a : 22; //[31:10] + uint32_t cumulative_l4_checksum : 16, //[15:0] + cumulative_ip_length : 16; //[31:16] +}; + +/* + +rxpcu_mpdu_filter_in_category + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + + This MPDU passed the normal + frame filter programming of rxpcu + + This MPDU did NOT pass the + regular frame filter and would have been dropped, were it + not for the frame fitting into the 'monitor_client' + category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the + rxpcu_monitor_client filter. It would have been dropped + accept that it did pass the 'monitor_other' category. + + + +sw_frame_group_id + + SW processes frames based on certain classifications. + This field indicates to what sw classification this MPDU is + mapped. + + The classification is given in priority order + + + + + + + + + + + + This includes mpdus + of type Data Null as well as QoS Data Null + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + + + + + + + +reserved_0 + + + +phy_ppdu_id + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + + +ip_hdr_chksum + + This can include the IP header checksum or the pseudo + header checksum used by TCP/UDP checksum. + + (with the first byte in the MSB and the second byte in + the LSB, i.e. requiring a byte-swap for little-endian FW/SW + w.r.t. the byte order in a packet) + +reported_mpdu_length + + MPDU length before decapsulation. Only valid when + first_msdu is set. This field is taken directly from the + length field of the A-MPDU delimiter or the preamble length + field for non-A-MPDU frames. + +reserved_1a + + + +key_id_octet + + The key ID octet from the IV. Only valid when + first_msdu is set. + +cce_super_rule + + Indicates the super filter rule + +cce_classify_not_done_truncate + + Classification failed due to truncated frame + +cce_classify_not_done_cce_dis + + Classification failed due to CCE global disable + +cumulative_l3_checksum + + FISA: IP header checksum including the total MSDU length + that is part of this flow aggregated so far, reported if + 'RXOLE_R0_FISA_CTRL. CHKSUM_CUM_IP_LEN_EN' is set + + + + Set to zero in chips not supporting FISA, e.g. Pine + + + +rule_indication_31_0 + + Bitmap indicating which of rules 31-0 have matched + +rule_indication_63_32 + + Bitmap indicating which of rules 63-32 have matched + +da_offset + + Offset into MSDU buffer for DA + +sa_offset + + Offset into MSDU buffer for SA + +da_offset_valid + + da_offset field is valid. This will be set to 0 in case + of a dynamic A-MSDU when DA is compressed + +sa_offset_valid + + sa_offset field is valid. This will be set to 0 in case + of a dynamic A-MSDU when SA is compressed + +reserved_5a + + + +l3_type + + The 16-bit type value indicating the type of L3 later + extracted from LLC/SNAP, set to zero if SNAP is not + available + +ipv6_options_crc + + 32 bit CRC computed out of IP v6 extension headers + +tcp_seq_number + + TCP sequence number (as a number assembled from a TCP + packet in big-endian order, i.e. requiring a byte-swap for + little-endian FW/SW w.r.t. the byte order in a packet) + + + + In Pine, if 'RXOLE_R0_MISC_CONFIG. + OVERRIDE_MSDU_END_FIELDS' is set, toeplitz_hash_2_or_4 from + 'RX_MSDU_START' will be reported here: + + Controlled by multiple RxOLE registers for TCP/UDP over + IPv4/IPv6 - Either Toeplitz hash computed over 2-tuple IPv4 + or IPv6 src/dest addresses is reported; or, Toeplitz hash + computed over 4-tuple IPv4 or IPv6 src/dest addresses and + src/dest ports is reported. The Flow_id_toeplitz hash can + also be reported here. Usually the hash reported here is the + one used for hash-based REO routing (see + use_flow_id_toeplitz_clfy in 'RXPT_CLASSIFY_INFO'). + Optionally the 3-tuple Toeplitz hash over IPv4 or IPv6 + src/dest addresses and L4 protocol can be reported here. + + (Unsupported in HastingsPrime) + +tcp_ack_number + + TCP acknowledge number (as a number assembled from a TCP + packet in big-endian order, i.e. requiring a byte-swap for + little-endian FW/SW w.r.t. the byte order in a packet) + + + + In Pine, if 'RXOLE_R0_MISC_CONFIG. + OVERRIDE_MSDU_END_FIELDS' is set, flow_id_toeplitz from + 'RX_MSDU_START' will be reported here: + + Toeplitz hash of 5-tuple {IP source address, IP + destination address, IP source port, IP destination port, L4 + protocol} in case of non-IPSec. In case of IPSec - Toeplitz + hash of 4-tuple {IP source address, IP destination address, + SPI, L4 protocol}. Optionally the 3-tuple Toeplitz hash over + IPv4 or IPv6 src/dest addresses and L4 protocol can be + reported here. + + The relevant Toeplitz key registers are provided in + RxOLE's instance of common parser module. These registers + are separate from the Toeplitz keys used by ASE/FSE modules + inside RxOLE. The actual value will be passed on from common + parser module to RxOLE in one of the WHO_* TLVs. + + (Unsupported in HastingsPrime) + +tcp_flag + + TCP flags + + {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}(with the NS bit + in bit 8 and the FIN bit in bit 0, i.e. in big-endian order, + i.e. requiring a byte-swap for little-endian FW/SW w.r.t. + the byte order in a packet) + +lro_eligible + + Computed out of TCP and IP fields to indicate that this + MSDU is eligible for LRO + +reserved_9a + + NOTE: DO not assign a field... Internally used in + RXOLE.. + + + +window_size + + TCP receive window size (as a number assembled from a + TCP packet in big-endian order, i.e. requiring a byte-swap + for little-endian FW/SW w.r.t. the byte order in a packet) + + + + In Pine, if 'RXOLE_R0_MISC_CONFIG. + OVERRIDE_MSDU_END_FIELDS' is set, msdu_length from + 'RX_MSDU_START' will be reported in the 14 LSBs here: + + MSDU length in bytes after decapsulation. This field is + still valid for MPDU frames without A-MSDU. It still + represents MSDU length after decapsulation. + + (Unsupported in HastingsPrime) + +tcp_udp_chksum + + The value of the computed TCP/UDP checksum. A mode bit + selects whether this checksum is the full checksum or the + partial checksum which does not include the pseudo header. + (with the first byte in the MSB and the second byte in the + LSB, i.e. requiring a byte-swap for little-endian FW/SW + w.r.t. the byte order in a packet) + +sa_idx_timeout + + Indicates an unsuccessful MAC source address search due + to the expiring of the search timer. + +da_idx_timeout + + Indicates an unsuccessful MAC destination address search + due to the expiring of the search timer. + +msdu_limit_error + + Indicates that the MSDU threshold was exceeded and thus + all the rest of the MSDUs will not be scattered and will not + be decapsulated but will be DMA'ed in RAW format as a single + MSDU buffer + +flow_idx_timeout + + Indicates an unsuccessful flow search due to the + expiring of the search timer. + + + +flow_idx_invalid + + flow id is not valid + + + +wifi_parser_error + + Indicates that the WiFi frame has one of the following + errors + + o has less than minimum allowed bytes as per standard + + o has incomplete VLAN LLC/SNAP (only for non A-MSDUs) + + + +amsdu_parser_error + + A-MSDU could not be properly de-agregated. + + + +sa_is_valid + + Indicates that OLE found a valid SA entry + +da_is_valid + + Indicates that OLE found a valid DA entry + +da_is_mcbc + + Field Only valid if da_is_valid is set + + + + Indicates the DA address was a Multicast of Broadcast + address. + +l3_header_padding + + Number of bytes padded to make sure that the L3 header + will always start of a Dword boundary + +first_msdu + + Indicates the first MSDU of A-MSDU. If both first_msdu + and last_msdu are set in the MSDU then this is a + non-aggregated MSDU frame: normal MPDU. Interior MSDU in an + A-MSDU shall have both first_mpdu and last_mpdu bits set to + 0. + +last_msdu + + Indicates the last MSDU of the A-MSDU. MPDU end status + is only valid when last_msdu is set. + +tcp_udp_chksum_fail + + if 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' is + set, tcp_udp_chksum_fail from 'RX_ATTENTION' will be + reported here: + + Indicates that the computed checksum (tcp_udp_chksum) + did not match the checksum in the TCP/UDP header. + + (unsupported in HastingsPrime) + +ip_chksum_fail + + If 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' is + set, ip_chksum_fail from 'RX_MSDU_START' will be reported in + the MSB here: + + Indicates that the computed checksum (ip_hdr_chksum) did + not match the checksum in the IP header. + + (unsupported in HastingsPrime) + +sa_idx + + The offset in the address table which matches the MAC + source address. + +da_idx_or_sw_peer_id + + Based on a register configuration in RXOLE, this field + will contain: + + The offset in the address table which matches the MAC + destination address + + OR: + + sw_peer_id from the address search entry corresponding + to the destination address of the MSDU + +msdu_drop + + When set, REO shall drop this MSDU and not forward it to + any other ring... + + + +reo_destination_indication + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW2 ring + + Reo will push the frame + into the REO2SW3 ring + + Reo will push the frame + into the REO2SW4 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + Reo will push the frame + into the REO2SW5 ring (REO remaps this in chips without + REO2SW5 ring, e.g. Pine) + + Reo will push the frame + into the REO2SW6 ring (REO remaps this in chips without + REO2SW6 ring, e.g. Pine) + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + + +flow_idx + + Flow table index + + + +reserved_12a + + + +fse_metadata + + FSE related meta data: + + + +cce_metadata + + CCE related meta data: + + + +sa_sw_peer_id + + sw_peer_id from the address search entry corresponding + to the source address of the MSDU + + + +aggregation_count + + FISA: Number of MSDU's aggregated so far + + + + Set to zero in chips not supporting FISA, e.g. Pine + + + +flow_aggregation_continuation + + FISA: To indicate that this MSDU can be aggregated with + the previous packet with the same flow id + + + + Set to zero in chips not supporting FISA, e.g. Pine + + + +fisa_timeout + + FISA: To indicate that the aggregation has restarted for + this flow due to timeout + + + + Set to zero in chips not supporting FISA, e.g. Pine + + + +reserved_15a + + + +cumulative_l4_checksum + + FISA: checksum for MSDU's that is part of this flow + aggregated so far + + + + Set to zero in chips not supporting FISA, e.g. Pine + + + +cumulative_ip_length + + FISA: Total MSDU length that is part of this flow + aggregated so far + + + + Set to zero in chips not supporting FISA, e.g. Pine + + +*/ + + +/* Description RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + + This MPDU passed the normal + frame filter programming of rxpcu + + This MPDU did NOT pass the + regular frame filter and would have been dropped, were it + not for the frame fitting into the 'monitor_client' + category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the + rxpcu_monitor_client filter. It would have been dropped + accept that it did pass the 'monitor_other' category. + + +*/ +#define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MSDU_END_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +/* Description RX_MSDU_END_0_SW_FRAME_GROUP_ID + + SW processes frames based on certain classifications. + This field indicates to what sw classification this MPDU is + mapped. + + The classification is given in priority order + + + + + + + + + + + + This includes mpdus + of type Data Null as well as QoS Data Null + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + + + + + + +*/ +#define RX_MSDU_END_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_MSDU_END_0_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MSDU_END_0_SW_FRAME_GROUP_ID_MASK 0x000001fc + +/* Description RX_MSDU_END_0_RESERVED_0 + + +*/ +#define RX_MSDU_END_0_RESERVED_0_OFFSET 0x00000000 +#define RX_MSDU_END_0_RESERVED_0_LSB 9 +#define RX_MSDU_END_0_RESERVED_0_MASK 0x0000fe00 + +/* Description RX_MSDU_END_0_PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + +*/ +#define RX_MSDU_END_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_MSDU_END_0_PHY_PPDU_ID_LSB 16 +#define RX_MSDU_END_0_PHY_PPDU_ID_MASK 0xffff0000 + +/* Description RX_MSDU_END_1_IP_HDR_CHKSUM + + This can include the IP header checksum or the pseudo + header checksum used by TCP/UDP checksum. + + (with the first byte in the MSB and the second byte in + the LSB, i.e. requiring a byte-swap for little-endian FW/SW + w.r.t. the byte order in a packet) +*/ +#define RX_MSDU_END_1_IP_HDR_CHKSUM_OFFSET 0x00000004 +#define RX_MSDU_END_1_IP_HDR_CHKSUM_LSB 0 +#define RX_MSDU_END_1_IP_HDR_CHKSUM_MASK 0x0000ffff + +/* Description RX_MSDU_END_1_REPORTED_MPDU_LENGTH + + MPDU length before decapsulation. Only valid when + first_msdu is set. This field is taken directly from the + length field of the A-MPDU delimiter or the preamble length + field for non-A-MPDU frames. +*/ +#define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_OFFSET 0x00000004 +#define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_LSB 16 +#define RX_MSDU_END_1_REPORTED_MPDU_LENGTH_MASK 0x3fff0000 + +/* Description RX_MSDU_END_1_RESERVED_1A + + +*/ +#define RX_MSDU_END_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_MSDU_END_1_RESERVED_1A_LSB 30 +#define RX_MSDU_END_1_RESERVED_1A_MASK 0xc0000000 + +/* Description RX_MSDU_END_2_KEY_ID_OCTET + + The key ID octet from the IV. Only valid when + first_msdu is set. +*/ +#define RX_MSDU_END_2_KEY_ID_OCTET_OFFSET 0x00000008 +#define RX_MSDU_END_2_KEY_ID_OCTET_LSB 0 +#define RX_MSDU_END_2_KEY_ID_OCTET_MASK 0x000000ff + +/* Description RX_MSDU_END_2_CCE_SUPER_RULE + + Indicates the super filter rule +*/ +#define RX_MSDU_END_2_CCE_SUPER_RULE_OFFSET 0x00000008 +#define RX_MSDU_END_2_CCE_SUPER_RULE_LSB 8 +#define RX_MSDU_END_2_CCE_SUPER_RULE_MASK 0x00003f00 + +/* Description RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE + + Classification failed due to truncated frame +*/ +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_OFFSET 0x00000008 +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_LSB 14 +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_TRUNCATE_MASK 0x00004000 + +/* Description RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS + + Classification failed due to CCE global disable +*/ +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_OFFSET 0x00000008 +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_LSB 15 +#define RX_MSDU_END_2_CCE_CLASSIFY_NOT_DONE_CCE_DIS_MASK 0x00008000 + +/* Description RX_MSDU_END_2_CUMULATIVE_L3_CHECKSUM + + FISA: IP header checksum including the total MSDU length + that is part of this flow aggregated so far, reported if + 'RXOLE_R0_FISA_CTRL. CHKSUM_CUM_IP_LEN_EN' is set + + + + Set to zero in chips not supporting FISA, e.g. Pine + + +*/ +#define RX_MSDU_END_2_CUMULATIVE_L3_CHECKSUM_OFFSET 0x00000008 +#define RX_MSDU_END_2_CUMULATIVE_L3_CHECKSUM_LSB 16 +#define RX_MSDU_END_2_CUMULATIVE_L3_CHECKSUM_MASK 0xffff0000 + +/* Description RX_MSDU_END_3_RULE_INDICATION_31_0 + + Bitmap indicating which of rules 31-0 have matched +*/ +#define RX_MSDU_END_3_RULE_INDICATION_31_0_OFFSET 0x0000000c +#define RX_MSDU_END_3_RULE_INDICATION_31_0_LSB 0 +#define RX_MSDU_END_3_RULE_INDICATION_31_0_MASK 0xffffffff + +/* Description RX_MSDU_END_4_RULE_INDICATION_63_32 + + Bitmap indicating which of rules 63-32 have matched +*/ +#define RX_MSDU_END_4_RULE_INDICATION_63_32_OFFSET 0x00000010 +#define RX_MSDU_END_4_RULE_INDICATION_63_32_LSB 0 +#define RX_MSDU_END_4_RULE_INDICATION_63_32_MASK 0xffffffff + +/* Description RX_MSDU_END_5_DA_OFFSET + + Offset into MSDU buffer for DA +*/ +#define RX_MSDU_END_5_DA_OFFSET_OFFSET 0x00000014 +#define RX_MSDU_END_5_DA_OFFSET_LSB 0 +#define RX_MSDU_END_5_DA_OFFSET_MASK 0x0000003f + +/* Description RX_MSDU_END_5_SA_OFFSET + + Offset into MSDU buffer for SA +*/ +#define RX_MSDU_END_5_SA_OFFSET_OFFSET 0x00000014 +#define RX_MSDU_END_5_SA_OFFSET_LSB 6 +#define RX_MSDU_END_5_SA_OFFSET_MASK 0x00000fc0 + +/* Description RX_MSDU_END_5_DA_OFFSET_VALID + + da_offset field is valid. This will be set to 0 in case + of a dynamic A-MSDU when DA is compressed +*/ +#define RX_MSDU_END_5_DA_OFFSET_VALID_OFFSET 0x00000014 +#define RX_MSDU_END_5_DA_OFFSET_VALID_LSB 12 +#define RX_MSDU_END_5_DA_OFFSET_VALID_MASK 0x00001000 + +/* Description RX_MSDU_END_5_SA_OFFSET_VALID + + sa_offset field is valid. This will be set to 0 in case + of a dynamic A-MSDU when SA is compressed +*/ +#define RX_MSDU_END_5_SA_OFFSET_VALID_OFFSET 0x00000014 +#define RX_MSDU_END_5_SA_OFFSET_VALID_LSB 13 +#define RX_MSDU_END_5_SA_OFFSET_VALID_MASK 0x00002000 + +/* Description RX_MSDU_END_5_RESERVED_5A + + +*/ +#define RX_MSDU_END_5_RESERVED_5A_OFFSET 0x00000014 +#define RX_MSDU_END_5_RESERVED_5A_LSB 14 +#define RX_MSDU_END_5_RESERVED_5A_MASK 0x0000c000 + +/* Description RX_MSDU_END_5_L3_TYPE + + The 16-bit type value indicating the type of L3 later + extracted from LLC/SNAP, set to zero if SNAP is not + available +*/ +#define RX_MSDU_END_5_L3_TYPE_OFFSET 0x00000014 +#define RX_MSDU_END_5_L3_TYPE_LSB 16 +#define RX_MSDU_END_5_L3_TYPE_MASK 0xffff0000 + +/* Description RX_MSDU_END_6_IPV6_OPTIONS_CRC + + 32 bit CRC computed out of IP v6 extension headers +*/ +#define RX_MSDU_END_6_IPV6_OPTIONS_CRC_OFFSET 0x00000018 +#define RX_MSDU_END_6_IPV6_OPTIONS_CRC_LSB 0 +#define RX_MSDU_END_6_IPV6_OPTIONS_CRC_MASK 0xffffffff + +/* Description RX_MSDU_END_7_TCP_SEQ_NUMBER + + TCP sequence number (as a number assembled from a TCP + packet in big-endian order, i.e. requiring a byte-swap for + little-endian FW/SW w.r.t. the byte order in a packet) + + + + In Pine, if 'RXOLE_R0_MISC_CONFIG. + OVERRIDE_MSDU_END_FIELDS' is set, toeplitz_hash_2_or_4 from + 'RX_MSDU_START' will be reported here: + + Controlled by multiple RxOLE registers for TCP/UDP over + IPv4/IPv6 - Either Toeplitz hash computed over 2-tuple IPv4 + or IPv6 src/dest addresses is reported; or, Toeplitz hash + computed over 4-tuple IPv4 or IPv6 src/dest addresses and + src/dest ports is reported. The Flow_id_toeplitz hash can + also be reported here. Usually the hash reported here is the + one used for hash-based REO routing (see + use_flow_id_toeplitz_clfy in 'RXPT_CLASSIFY_INFO'). + Optionally the 3-tuple Toeplitz hash over IPv4 or IPv6 + src/dest addresses and L4 protocol can be reported here. + + (Unsupported in HastingsPrime) +*/ +#define RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET 0x0000001c +#define RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB 0 +#define RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK 0xffffffff + +/* Description RX_MSDU_END_8_TCP_ACK_NUMBER + + TCP acknowledge number (as a number assembled from a TCP + packet in big-endian order, i.e. requiring a byte-swap for + little-endian FW/SW w.r.t. the byte order in a packet) + + + + In Pine, if 'RXOLE_R0_MISC_CONFIG. + OVERRIDE_MSDU_END_FIELDS' is set, flow_id_toeplitz from + 'RX_MSDU_START' will be reported here: + + Toeplitz hash of 5-tuple {IP source address, IP + destination address, IP source port, IP destination port, L4 + protocol} in case of non-IPSec. In case of IPSec - Toeplitz + hash of 4-tuple {IP source address, IP destination address, + SPI, L4 protocol}. Optionally the 3-tuple Toeplitz hash over + IPv4 or IPv6 src/dest addresses and L4 protocol can be + reported here. + + The relevant Toeplitz key registers are provided in + RxOLE's instance of common parser module. These registers + are separate from the Toeplitz keys used by ASE/FSE modules + inside RxOLE. The actual value will be passed on from common + parser module to RxOLE in one of the WHO_* TLVs. + + (Unsupported in HastingsPrime) +*/ +#define RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET 0x00000020 +#define RX_MSDU_END_8_TCP_ACK_NUMBER_LSB 0 +#define RX_MSDU_END_8_TCP_ACK_NUMBER_MASK 0xffffffff + +/* Description RX_MSDU_END_9_TCP_FLAG + + TCP flags + + {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN}(with the NS bit + in bit 8 and the FIN bit in bit 0, i.e. in big-endian order, + i.e. requiring a byte-swap for little-endian FW/SW w.r.t. + the byte order in a packet) +*/ +#define RX_MSDU_END_9_TCP_FLAG_OFFSET 0x00000024 +#define RX_MSDU_END_9_TCP_FLAG_LSB 0 +#define RX_MSDU_END_9_TCP_FLAG_MASK 0x000001ff + +/* Description RX_MSDU_END_9_LRO_ELIGIBLE + + Computed out of TCP and IP fields to indicate that this + MSDU is eligible for LRO +*/ +#define RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET 0x00000024 +#define RX_MSDU_END_9_LRO_ELIGIBLE_LSB 9 +#define RX_MSDU_END_9_LRO_ELIGIBLE_MASK 0x00000200 + +/* Description RX_MSDU_END_9_RESERVED_9A + + NOTE: DO not assign a field... Internally used in + RXOLE.. + + +*/ +#define RX_MSDU_END_9_RESERVED_9A_OFFSET 0x00000024 +#define RX_MSDU_END_9_RESERVED_9A_LSB 10 +#define RX_MSDU_END_9_RESERVED_9A_MASK 0x0000fc00 + +/* Description RX_MSDU_END_9_WINDOW_SIZE + + TCP receive window size (as a number assembled from a + TCP packet in big-endian order, i.e. requiring a byte-swap + for little-endian FW/SW w.r.t. the byte order in a packet) + + + + In Pine, if 'RXOLE_R0_MISC_CONFIG. + OVERRIDE_MSDU_END_FIELDS' is set, msdu_length from + 'RX_MSDU_START' will be reported in the 14 LSBs here: + + MSDU length in bytes after decapsulation. This field is + still valid for MPDU frames without A-MSDU. It still + represents MSDU length after decapsulation. + + (Unsupported in HastingsPrime) +*/ +#define RX_MSDU_END_9_WINDOW_SIZE_OFFSET 0x00000024 +#define RX_MSDU_END_9_WINDOW_SIZE_LSB 16 +#define RX_MSDU_END_9_WINDOW_SIZE_MASK 0xffff0000 + +/* Description RX_MSDU_END_10_TCP_UDP_CHKSUM + + The value of the computed TCP/UDP checksum. A mode bit + selects whether this checksum is the full checksum or the + partial checksum which does not include the pseudo header. + (with the first byte in the MSB and the second byte in the + LSB, i.e. requiring a byte-swap for little-endian FW/SW + w.r.t. the byte order in a packet) +*/ +#define RX_MSDU_END_10_TCP_UDP_CHKSUM_OFFSET 0x00000028 +#define RX_MSDU_END_10_TCP_UDP_CHKSUM_LSB 0 +#define RX_MSDU_END_10_TCP_UDP_CHKSUM_MASK 0x0000ffff + +/* Description RX_MSDU_END_10_SA_IDX_TIMEOUT + + Indicates an unsuccessful MAC source address search due + to the expiring of the search timer. +*/ +#define RX_MSDU_END_10_SA_IDX_TIMEOUT_OFFSET 0x00000028 +#define RX_MSDU_END_10_SA_IDX_TIMEOUT_LSB 16 +#define RX_MSDU_END_10_SA_IDX_TIMEOUT_MASK 0x00010000 + +/* Description RX_MSDU_END_10_DA_IDX_TIMEOUT + + Indicates an unsuccessful MAC destination address search + due to the expiring of the search timer. +*/ +#define RX_MSDU_END_10_DA_IDX_TIMEOUT_OFFSET 0x00000028 +#define RX_MSDU_END_10_DA_IDX_TIMEOUT_LSB 17 +#define RX_MSDU_END_10_DA_IDX_TIMEOUT_MASK 0x00020000 + +/* Description RX_MSDU_END_10_MSDU_LIMIT_ERROR + + Indicates that the MSDU threshold was exceeded and thus + all the rest of the MSDUs will not be scattered and will not + be decapsulated but will be DMA'ed in RAW format as a single + MSDU buffer +*/ +#define RX_MSDU_END_10_MSDU_LIMIT_ERROR_OFFSET 0x00000028 +#define RX_MSDU_END_10_MSDU_LIMIT_ERROR_LSB 18 +#define RX_MSDU_END_10_MSDU_LIMIT_ERROR_MASK 0x00040000 + +/* Description RX_MSDU_END_10_FLOW_IDX_TIMEOUT + + Indicates an unsuccessful flow search due to the + expiring of the search timer. + + +*/ +#define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_OFFSET 0x00000028 +#define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_LSB 19 +#define RX_MSDU_END_10_FLOW_IDX_TIMEOUT_MASK 0x00080000 + +/* Description RX_MSDU_END_10_FLOW_IDX_INVALID + + flow id is not valid + + +*/ +#define RX_MSDU_END_10_FLOW_IDX_INVALID_OFFSET 0x00000028 +#define RX_MSDU_END_10_FLOW_IDX_INVALID_LSB 20 +#define RX_MSDU_END_10_FLOW_IDX_INVALID_MASK 0x00100000 + +/* Description RX_MSDU_END_10_WIFI_PARSER_ERROR + + Indicates that the WiFi frame has one of the following + errors + + o has less than minimum allowed bytes as per standard + + o has incomplete VLAN LLC/SNAP (only for non A-MSDUs) + + +*/ +#define RX_MSDU_END_10_WIFI_PARSER_ERROR_OFFSET 0x00000028 +#define RX_MSDU_END_10_WIFI_PARSER_ERROR_LSB 21 +#define RX_MSDU_END_10_WIFI_PARSER_ERROR_MASK 0x00200000 + +/* Description RX_MSDU_END_10_AMSDU_PARSER_ERROR + + A-MSDU could not be properly de-agregated. + + +*/ +#define RX_MSDU_END_10_AMSDU_PARSER_ERROR_OFFSET 0x00000028 +#define RX_MSDU_END_10_AMSDU_PARSER_ERROR_LSB 22 +#define RX_MSDU_END_10_AMSDU_PARSER_ERROR_MASK 0x00400000 + +/* Description RX_MSDU_END_10_SA_IS_VALID + + Indicates that OLE found a valid SA entry +*/ +#define RX_MSDU_END_10_SA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_END_10_SA_IS_VALID_LSB 23 +#define RX_MSDU_END_10_SA_IS_VALID_MASK 0x00800000 + +/* Description RX_MSDU_END_10_DA_IS_VALID + + Indicates that OLE found a valid DA entry +*/ +#define RX_MSDU_END_10_DA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_END_10_DA_IS_VALID_LSB 24 +#define RX_MSDU_END_10_DA_IS_VALID_MASK 0x01000000 + +/* Description RX_MSDU_END_10_DA_IS_MCBC + + Field Only valid if da_is_valid is set + + + + Indicates the DA address was a Multicast of Broadcast + address. +*/ +#define RX_MSDU_END_10_DA_IS_MCBC_OFFSET 0x00000028 +#define RX_MSDU_END_10_DA_IS_MCBC_LSB 25 +#define RX_MSDU_END_10_DA_IS_MCBC_MASK 0x02000000 + +/* Description RX_MSDU_END_10_L3_HEADER_PADDING + + Number of bytes padded to make sure that the L3 header + will always start of a Dword boundary +*/ +#define RX_MSDU_END_10_L3_HEADER_PADDING_OFFSET 0x00000028 +#define RX_MSDU_END_10_L3_HEADER_PADDING_LSB 26 +#define RX_MSDU_END_10_L3_HEADER_PADDING_MASK 0x0c000000 + +/* Description RX_MSDU_END_10_FIRST_MSDU + + Indicates the first MSDU of A-MSDU. If both first_msdu + and last_msdu are set in the MSDU then this is a + non-aggregated MSDU frame: normal MPDU. Interior MSDU in an + A-MSDU shall have both first_mpdu and last_mpdu bits set to + 0. +*/ +#define RX_MSDU_END_10_FIRST_MSDU_OFFSET 0x00000028 +#define RX_MSDU_END_10_FIRST_MSDU_LSB 28 +#define RX_MSDU_END_10_FIRST_MSDU_MASK 0x10000000 + +/* Description RX_MSDU_END_10_LAST_MSDU + + Indicates the last MSDU of the A-MSDU. MPDU end status + is only valid when last_msdu is set. +*/ +#define RX_MSDU_END_10_LAST_MSDU_OFFSET 0x00000028 +#define RX_MSDU_END_10_LAST_MSDU_LSB 29 +#define RX_MSDU_END_10_LAST_MSDU_MASK 0x20000000 + +/* Description RX_MSDU_END_10_TCP_UDP_CHKSUM_FAIL + + if 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' is + set, tcp_udp_chksum_fail from 'RX_ATTENTION' will be + reported here: + + Indicates that the computed checksum (tcp_udp_chksum) + did not match the checksum in the TCP/UDP header. + + (unsupported in HastingsPrime) +*/ +#define RX_MSDU_END_10_TCP_UDP_CHKSUM_FAIL_OFFSET 0x00000028 +#define RX_MSDU_END_10_TCP_UDP_CHKSUM_FAIL_LSB 30 +#define RX_MSDU_END_10_TCP_UDP_CHKSUM_FAIL_MASK 0x40000000 + +/* Description RX_MSDU_END_10_IP_CHKSUM_FAIL + + If 'RXOLE_R0_MISC_CONFIG. OVERRIDE_MSDU_END_FIELDS' is + set, ip_chksum_fail from 'RX_MSDU_START' will be reported in + the MSB here: + + Indicates that the computed checksum (ip_hdr_chksum) did + not match the checksum in the IP header. + + (unsupported in HastingsPrime) +*/ +#define RX_MSDU_END_10_IP_CHKSUM_FAIL_OFFSET 0x00000028 +#define RX_MSDU_END_10_IP_CHKSUM_FAIL_LSB 31 +#define RX_MSDU_END_10_IP_CHKSUM_FAIL_MASK 0x80000000 + +/* Description RX_MSDU_END_11_SA_IDX + + The offset in the address table which matches the MAC + source address. +*/ +#define RX_MSDU_END_11_SA_IDX_OFFSET 0x0000002c +#define RX_MSDU_END_11_SA_IDX_LSB 0 +#define RX_MSDU_END_11_SA_IDX_MASK 0x0000ffff + +/* Description RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID + + Based on a register configuration in RXOLE, this field + will contain: + + The offset in the address table which matches the MAC + destination address + + OR: + + sw_peer_id from the address search entry corresponding + to the destination address of the MSDU +*/ +#define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_OFFSET 0x0000002c +#define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_LSB 16 +#define RX_MSDU_END_11_DA_IDX_OR_SW_PEER_ID_MASK 0xffff0000 + +/* Description RX_MSDU_END_12_MSDU_DROP + + When set, REO shall drop this MSDU and not forward it to + any other ring... + + +*/ +#define RX_MSDU_END_12_MSDU_DROP_OFFSET 0x00000030 +#define RX_MSDU_END_12_MSDU_DROP_LSB 0 +#define RX_MSDU_END_12_MSDU_DROP_MASK 0x00000001 + +/* Description RX_MSDU_END_12_REO_DESTINATION_INDICATION + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW2 ring + + Reo will push the frame + into the REO2SW3 ring + + Reo will push the frame + into the REO2SW4 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + Reo will push the frame + into the REO2SW5 ring (REO remaps this in chips without + REO2SW5 ring, e.g. Pine) + + Reo will push the frame + into the REO2SW6 ring (REO remaps this in chips without + REO2SW6 ring, e.g. Pine) + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + +*/ +#define RX_MSDU_END_12_REO_DESTINATION_INDICATION_OFFSET 0x00000030 +#define RX_MSDU_END_12_REO_DESTINATION_INDICATION_LSB 1 +#define RX_MSDU_END_12_REO_DESTINATION_INDICATION_MASK 0x0000003e + +/* Description RX_MSDU_END_12_FLOW_IDX + + Flow table index + + +*/ +#define RX_MSDU_END_12_FLOW_IDX_OFFSET 0x00000030 +#define RX_MSDU_END_12_FLOW_IDX_LSB 6 +#define RX_MSDU_END_12_FLOW_IDX_MASK 0x03ffffc0 + +/* Description RX_MSDU_END_12_RESERVED_12A + + +*/ +#define RX_MSDU_END_12_RESERVED_12A_OFFSET 0x00000030 +#define RX_MSDU_END_12_RESERVED_12A_LSB 26 +#define RX_MSDU_END_12_RESERVED_12A_MASK 0xfc000000 + +/* Description RX_MSDU_END_13_FSE_METADATA + + FSE related meta data: + + +*/ +#define RX_MSDU_END_13_FSE_METADATA_OFFSET 0x00000034 +#define RX_MSDU_END_13_FSE_METADATA_LSB 0 +#define RX_MSDU_END_13_FSE_METADATA_MASK 0xffffffff + +/* Description RX_MSDU_END_14_CCE_METADATA + + CCE related meta data: + + +*/ +#define RX_MSDU_END_14_CCE_METADATA_OFFSET 0x00000038 +#define RX_MSDU_END_14_CCE_METADATA_LSB 0 +#define RX_MSDU_END_14_CCE_METADATA_MASK 0x0000ffff + +/* Description RX_MSDU_END_14_SA_SW_PEER_ID + + sw_peer_id from the address search entry corresponding + to the source address of the MSDU + + +*/ +#define RX_MSDU_END_14_SA_SW_PEER_ID_OFFSET 0x00000038 +#define RX_MSDU_END_14_SA_SW_PEER_ID_LSB 16 +#define RX_MSDU_END_14_SA_SW_PEER_ID_MASK 0xffff0000 + +/* Description RX_MSDU_END_15_AGGREGATION_COUNT + + FISA: Number of MSDU's aggregated so far + + + + Set to zero in chips not supporting FISA, e.g. Pine + + +*/ +#define RX_MSDU_END_15_AGGREGATION_COUNT_OFFSET 0x0000003c +#define RX_MSDU_END_15_AGGREGATION_COUNT_LSB 0 +#define RX_MSDU_END_15_AGGREGATION_COUNT_MASK 0x000000ff + +/* Description RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION + + FISA: To indicate that this MSDU can be aggregated with + the previous packet with the same flow id + + + + Set to zero in chips not supporting FISA, e.g. Pine + + +*/ +#define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_OFFSET 0x0000003c +#define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_LSB 8 +#define RX_MSDU_END_15_FLOW_AGGREGATION_CONTINUATION_MASK 0x00000100 + +/* Description RX_MSDU_END_15_FISA_TIMEOUT + + FISA: To indicate that the aggregation has restarted for + this flow due to timeout + + + + Set to zero in chips not supporting FISA, e.g. Pine + + +*/ +#define RX_MSDU_END_15_FISA_TIMEOUT_OFFSET 0x0000003c +#define RX_MSDU_END_15_FISA_TIMEOUT_LSB 9 +#define RX_MSDU_END_15_FISA_TIMEOUT_MASK 0x00000200 + +/* Description RX_MSDU_END_15_RESERVED_15A + + +*/ +#define RX_MSDU_END_15_RESERVED_15A_OFFSET 0x0000003c +#define RX_MSDU_END_15_RESERVED_15A_LSB 10 +#define RX_MSDU_END_15_RESERVED_15A_MASK 0xfffffc00 + +/* Description RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM + + FISA: checksum for MSDU's that is part of this flow + aggregated so far + + + + Set to zero in chips not supporting FISA, e.g. Pine + + +*/ +#define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_OFFSET 0x00000040 +#define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_LSB 0 +#define RX_MSDU_END_16_CUMULATIVE_L4_CHECKSUM_MASK 0x0000ffff + +/* Description RX_MSDU_END_16_CUMULATIVE_IP_LENGTH + + FISA: Total MSDU length that is part of this flow + aggregated so far + + + + Set to zero in chips not supporting FISA, e.g. Pine + + +*/ +#define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_OFFSET 0x00000040 +#define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_LSB 16 +#define RX_MSDU_END_16_CUMULATIVE_IP_LENGTH_MASK 0xffff0000 + + +#endif // _RX_MSDU_END_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/rx_msdu_link.h b/drivers/staging/fw-api/hw/qca6750/v1/rx_msdu_link.h new file mode 100644 index 000000000000..919c8a0b4723 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/rx_msdu_link.h @@ -0,0 +1,3370 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_MSDU_LINK_H_ +#define _RX_MSDU_LINK_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_descriptor_header.h" +#include "buffer_addr_info.h" +#include "rx_msdu_details.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 struct uniform_descriptor_header descriptor_header; +// 1-2 struct buffer_addr_info next_msdu_link_desc_addr_info; +// 3 receive_queue_number[15:0], first_rx_msdu_link_struct[16], reserved_3a[31:17] +// 4 pn_31_0[31:0] +// 5 pn_63_32[31:0] +// 6 pn_95_64[31:0] +// 7 pn_127_96[31:0] +// 8-11 struct rx_msdu_details msdu_0; +// 12-15 struct rx_msdu_details msdu_1; +// 16-19 struct rx_msdu_details msdu_2; +// 20-23 struct rx_msdu_details msdu_3; +// 24-27 struct rx_msdu_details msdu_4; +// 28-31 struct rx_msdu_details msdu_5; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_MSDU_LINK 32 + +struct rx_msdu_link { + struct uniform_descriptor_header descriptor_header; + struct buffer_addr_info next_msdu_link_desc_addr_info; + uint32_t receive_queue_number : 16, //[15:0] + first_rx_msdu_link_struct : 1, //[16] + reserved_3a : 15; //[31:17] + uint32_t pn_31_0 : 32; //[31:0] + uint32_t pn_63_32 : 32; //[31:0] + uint32_t pn_95_64 : 32; //[31:0] + uint32_t pn_127_96 : 32; //[31:0] + struct rx_msdu_details msdu_0; + struct rx_msdu_details msdu_1; + struct rx_msdu_details msdu_2; + struct rx_msdu_details msdu_3; + struct rx_msdu_details msdu_4; + struct rx_msdu_details msdu_5; +}; + +/* + +struct uniform_descriptor_header descriptor_header + + Details about which module owns this struct. + + Note that sub field Buffer_type shall be set to + Receive_MSDU_Link_descriptor + +struct buffer_addr_info next_msdu_link_desc_addr_info + + Details of the physical address of the next MSDU link + descriptor that contains info about additional MSDUs that + are part of this MPDU. + +receive_queue_number + + Indicates the Receive queue to which this MPDU + descriptor belongs + + Used for tracking, finding bugs and debugging. + + + +first_rx_msdu_link_struct + + When set, this RX_MSDU_link descriptor is the first one + in the MSDU link list. Field MSDU_0 points to the very first + MSDU buffer descriptor in the MPDU + + + +reserved_3a + + + +pn_31_0 + + + + + 31-0 bits of the 256-bit packet number bitmap. + + + +pn_63_32 + + + + + 63-32 bits of the 256-bit packet number bitmap. + + + +pn_95_64 + + + + + 95-64 bits of the 256-bit packet number bitmap. + + + +pn_127_96 + + + + + 127-96 bits of the 256-bit packet number bitmap. + + + +struct rx_msdu_details msdu_0 + + When First_RX_MSDU_link_struct is set, this MSDU is the + first in the MPDU + + + + When First_RX_MSDU_link_struct is NOT set, this MSDU + follows the last MSDU in the previous RX_MSDU_link data + structure + +struct rx_msdu_details msdu_1 + + Details of next MSDU in this (MSDU flow) linked list + +struct rx_msdu_details msdu_2 + + Details of next MSDU in this (MSDU flow) linked list + +struct rx_msdu_details msdu_3 + + Details of next MSDU in this (MSDU flow) linked list + +struct rx_msdu_details msdu_4 + + Details of next MSDU in this (MSDU flow) linked list + +struct rx_msdu_details msdu_5 + + Details of next MSDU in this (MSDU flow) linked list +*/ + + + /* EXTERNAL REFERENCE : struct uniform_descriptor_header descriptor_header */ + + +/* Description RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + + + The owner of this data structure: + + Buffer Manager currently owns this + data structure. + + Software of FW currently owns + this data structure. + + Transmit Queue Manager currently owns + this data structure. + + Receive DMA currently owns this + data structure. + + Reorder currently owns this data + structure. + + SWITCH currently owns this data + structure. + + + + +*/ +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + +/* Description RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + + + Field describing what contents format is of this + descriptor + + + + + + + + + + + + + + NOT TO BE USED: + + + + + + + + + + + + + + + + + + + + + + +*/ +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + +/* Description RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A + + +*/ +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 +#define RX_MSDU_LINK_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 + + /* EXTERNAL REFERENCE : struct buffer_addr_info next_msdu_link_desc_addr_info */ + + +/* Description RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000004 +#define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_1_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000008 +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + +*/ +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000008 +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000008 +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_MSDU_LINK_2_NEXT_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +/* Description RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER + + Indicates the Receive queue to which this MPDU + descriptor belongs + + Used for tracking, finding bugs and debugging. + + +*/ +#define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_OFFSET 0x0000000c +#define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_LSB 0 +#define RX_MSDU_LINK_3_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff + +/* Description RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT + + When set, this RX_MSDU_link descriptor is the first one + in the MSDU link list. Field MSDU_0 points to the very first + MSDU buffer descriptor in the MPDU + + +*/ +#define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_OFFSET 0x0000000c +#define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_LSB 16 +#define RX_MSDU_LINK_3_FIRST_RX_MSDU_LINK_STRUCT_MASK 0x00010000 + +/* Description RX_MSDU_LINK_3_RESERVED_3A + + +*/ +#define RX_MSDU_LINK_3_RESERVED_3A_OFFSET 0x0000000c +#define RX_MSDU_LINK_3_RESERVED_3A_LSB 17 +#define RX_MSDU_LINK_3_RESERVED_3A_MASK 0xfffe0000 + +/* Description RX_MSDU_LINK_4_PN_31_0 + + + + + 31-0 bits of the 256-bit packet number bitmap. + + +*/ +#define RX_MSDU_LINK_4_PN_31_0_OFFSET 0x00000010 +#define RX_MSDU_LINK_4_PN_31_0_LSB 0 +#define RX_MSDU_LINK_4_PN_31_0_MASK 0xffffffff + +/* Description RX_MSDU_LINK_5_PN_63_32 + + + + + 63-32 bits of the 256-bit packet number bitmap. + + +*/ +#define RX_MSDU_LINK_5_PN_63_32_OFFSET 0x00000014 +#define RX_MSDU_LINK_5_PN_63_32_LSB 0 +#define RX_MSDU_LINK_5_PN_63_32_MASK 0xffffffff + +/* Description RX_MSDU_LINK_6_PN_95_64 + + + + + 95-64 bits of the 256-bit packet number bitmap. + + +*/ +#define RX_MSDU_LINK_6_PN_95_64_OFFSET 0x00000018 +#define RX_MSDU_LINK_6_PN_95_64_LSB 0 +#define RX_MSDU_LINK_6_PN_95_64_MASK 0xffffffff + +/* Description RX_MSDU_LINK_7_PN_127_96 + + + + + 127-96 bits of the 256-bit packet number bitmap. + + +*/ +#define RX_MSDU_LINK_7_PN_127_96_OFFSET 0x0000001c +#define RX_MSDU_LINK_7_PN_127_96_LSB 0 +#define RX_MSDU_LINK_7_PN_127_96_MASK 0xffffffff + + /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_0 */ + + + /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */ + + +/* Description RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000020 +#define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000024 +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + +*/ +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000024 +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 +#define RX_MSDU_LINK_9_MSDU_0_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 + + /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ + + +/* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + This is not the first MSDU in + the MPDU. + + This MSDU is the first one in the + MPDU. + + + + +*/ +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +/* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG + + Consumer: WBM/REO/SW/FW + + Producer: RXDMA + + + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + There are more MSDUs linked to + this MSDU that belongs to this MPDU + + this MSDU is the last one in the + MPDU. This setting is only allowed in combination with + 'Msdu_continuation' set to 0. This implies that when an msdu + is spread out over multiple buffers and thus + msdu_continuation is set, only for the very last buffer of + the msdu, can the 'last_msdu_in_mpdu_flag' be set. + + + + When both first_msdu_in_mpdu_flag and + last_msdu_in_mpdu_flag are set, the MPDU that this MSDU + belongs to only contains a single MSDU. + + + + + + +*/ +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +/* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION + + When set, this MSDU buffer was not able to hold the + entire MSDU. The next buffer will therefor contain + additional information related to this MSDU. + + + + +*/ +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +/* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH + + Parsed from RX_MSDU_START TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the First + buffer used by MSDU. + + + + Full MSDU length in bytes after decapsulation. + + + + This field is still valid for MPDU frames without + A-MSDU. It still represents MSDU length after decapsulation + + + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + + +*/ +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +/* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW2 ring + + Reo will push the frame + into the REO2SW3 ring + + Reo will push the frame + into the REO2SW4 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + Reo will push the frame + into the REO2SW5 ring (REO remaps this in chips without + REO2SW5 ring, e.g. Pine) + + Reo will push the frame + into the REO2SW6 ring (REO remaps this in chips without + REO2SW6 ring, e.g. Pine) + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + +*/ +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +/* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + When set, REO shall drop this MSDU and not forward it to + any other ring... + + +*/ +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 + +/* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates that OLE found a valid SA entry for this MSDU + + +*/ +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 + +/* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates an unsuccessful MAC source address search due + to the expiring of the search timer for this MSDU + + +*/ +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 + +/* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates that OLE found a valid DA entry for this MSDU + + +*/ +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 + +/* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC + + Field Only valid if da_is_valid is set + + + + Indicates the DA address was a Multicast of Broadcast + address for this MSDU + + +*/ +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 + +/* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates an unsuccessful MAC destination address search + due to the expiring of the search timer for this MSDU + + +*/ +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 + +/* Description RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A + + +*/ +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000028 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28 +#define RX_MSDU_LINK_10_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000 + +/* Description RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A + + +*/ +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000002c +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0 +#define RX_MSDU_LINK_11_MSDU_0_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff + + /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_1 */ + + + /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */ + + +/* Description RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000030 +#define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_12_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000034 +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + +*/ +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000034 +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 +#define RX_MSDU_LINK_13_MSDU_1_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 + + /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ + + +/* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + This is not the first MSDU in + the MPDU. + + This MSDU is the first one in the + MPDU. + + + + +*/ +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +/* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG + + Consumer: WBM/REO/SW/FW + + Producer: RXDMA + + + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + There are more MSDUs linked to + this MSDU that belongs to this MPDU + + this MSDU is the last one in the + MPDU. This setting is only allowed in combination with + 'Msdu_continuation' set to 0. This implies that when an msdu + is spread out over multiple buffers and thus + msdu_continuation is set, only for the very last buffer of + the msdu, can the 'last_msdu_in_mpdu_flag' be set. + + + + When both first_msdu_in_mpdu_flag and + last_msdu_in_mpdu_flag are set, the MPDU that this MSDU + belongs to only contains a single MSDU. + + + + + + +*/ +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +/* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION + + When set, this MSDU buffer was not able to hold the + entire MSDU. The next buffer will therefor contain + additional information related to this MSDU. + + + + +*/ +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +/* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH + + Parsed from RX_MSDU_START TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the First + buffer used by MSDU. + + + + Full MSDU length in bytes after decapsulation. + + + + This field is still valid for MPDU frames without + A-MSDU. It still represents MSDU length after decapsulation + + + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + + +*/ +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +/* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW2 ring + + Reo will push the frame + into the REO2SW3 ring + + Reo will push the frame + into the REO2SW4 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + Reo will push the frame + into the REO2SW5 ring (REO remaps this in chips without + REO2SW5 ring, e.g. Pine) + + Reo will push the frame + into the REO2SW6 ring (REO remaps this in chips without + REO2SW6 ring, e.g. Pine) + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + +*/ +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +/* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + When set, REO shall drop this MSDU and not forward it to + any other ring... + + +*/ +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 + +/* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates that OLE found a valid SA entry for this MSDU + + +*/ +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 + +/* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates an unsuccessful MAC source address search due + to the expiring of the search timer for this MSDU + + +*/ +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 + +/* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates that OLE found a valid DA entry for this MSDU + + +*/ +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 + +/* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC + + Field Only valid if da_is_valid is set + + + + Indicates the DA address was a Multicast of Broadcast + address for this MSDU + + +*/ +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 + +/* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates an unsuccessful MAC destination address search + due to the expiring of the search timer for this MSDU + + +*/ +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 + +/* Description RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A + + +*/ +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000038 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28 +#define RX_MSDU_LINK_14_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000 + +/* Description RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A + + +*/ +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000003c +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0 +#define RX_MSDU_LINK_15_MSDU_1_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff + + /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_2 */ + + + /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */ + + +/* Description RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000040 +#define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_16_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000044 +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + +*/ +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000044 +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 +#define RX_MSDU_LINK_17_MSDU_2_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 + + /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ + + +/* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + This is not the first MSDU in + the MPDU. + + This MSDU is the first one in the + MPDU. + + + + +*/ +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +/* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG + + Consumer: WBM/REO/SW/FW + + Producer: RXDMA + + + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + There are more MSDUs linked to + this MSDU that belongs to this MPDU + + this MSDU is the last one in the + MPDU. This setting is only allowed in combination with + 'Msdu_continuation' set to 0. This implies that when an msdu + is spread out over multiple buffers and thus + msdu_continuation is set, only for the very last buffer of + the msdu, can the 'last_msdu_in_mpdu_flag' be set. + + + + When both first_msdu_in_mpdu_flag and + last_msdu_in_mpdu_flag are set, the MPDU that this MSDU + belongs to only contains a single MSDU. + + + + + + +*/ +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +/* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION + + When set, this MSDU buffer was not able to hold the + entire MSDU. The next buffer will therefor contain + additional information related to this MSDU. + + + + +*/ +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +/* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH + + Parsed from RX_MSDU_START TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the First + buffer used by MSDU. + + + + Full MSDU length in bytes after decapsulation. + + + + This field is still valid for MPDU frames without + A-MSDU. It still represents MSDU length after decapsulation + + + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + + +*/ +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +/* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW2 ring + + Reo will push the frame + into the REO2SW3 ring + + Reo will push the frame + into the REO2SW4 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + Reo will push the frame + into the REO2SW5 ring (REO remaps this in chips without + REO2SW5 ring, e.g. Pine) + + Reo will push the frame + into the REO2SW6 ring (REO remaps this in chips without + REO2SW6 ring, e.g. Pine) + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + +*/ +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +/* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + When set, REO shall drop this MSDU and not forward it to + any other ring... + + +*/ +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 + +/* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates that OLE found a valid SA entry for this MSDU + + +*/ +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 + +/* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates an unsuccessful MAC source address search due + to the expiring of the search timer for this MSDU + + +*/ +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 + +/* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates that OLE found a valid DA entry for this MSDU + + +*/ +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 + +/* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC + + Field Only valid if da_is_valid is set + + + + Indicates the DA address was a Multicast of Broadcast + address for this MSDU + + +*/ +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 + +/* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates an unsuccessful MAC destination address search + due to the expiring of the search timer for this MSDU + + +*/ +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 + +/* Description RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A + + +*/ +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000048 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28 +#define RX_MSDU_LINK_18_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000 + +/* Description RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A + + +*/ +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000004c +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0 +#define RX_MSDU_LINK_19_MSDU_2_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff + + /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_3 */ + + + /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */ + + +/* Description RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000050 +#define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_20_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000054 +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + +*/ +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000054 +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 +#define RX_MSDU_LINK_21_MSDU_3_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 + + /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ + + +/* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + This is not the first MSDU in + the MPDU. + + This MSDU is the first one in the + MPDU. + + + + +*/ +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +/* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG + + Consumer: WBM/REO/SW/FW + + Producer: RXDMA + + + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + There are more MSDUs linked to + this MSDU that belongs to this MPDU + + this MSDU is the last one in the + MPDU. This setting is only allowed in combination with + 'Msdu_continuation' set to 0. This implies that when an msdu + is spread out over multiple buffers and thus + msdu_continuation is set, only for the very last buffer of + the msdu, can the 'last_msdu_in_mpdu_flag' be set. + + + + When both first_msdu_in_mpdu_flag and + last_msdu_in_mpdu_flag are set, the MPDU that this MSDU + belongs to only contains a single MSDU. + + + + + + +*/ +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +/* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION + + When set, this MSDU buffer was not able to hold the + entire MSDU. The next buffer will therefor contain + additional information related to this MSDU. + + + + +*/ +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +/* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH + + Parsed from RX_MSDU_START TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the First + buffer used by MSDU. + + + + Full MSDU length in bytes after decapsulation. + + + + This field is still valid for MPDU frames without + A-MSDU. It still represents MSDU length after decapsulation + + + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + + +*/ +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +/* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW2 ring + + Reo will push the frame + into the REO2SW3 ring + + Reo will push the frame + into the REO2SW4 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + Reo will push the frame + into the REO2SW5 ring (REO remaps this in chips without + REO2SW5 ring, e.g. Pine) + + Reo will push the frame + into the REO2SW6 ring (REO remaps this in chips without + REO2SW6 ring, e.g. Pine) + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + +*/ +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +/* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + When set, REO shall drop this MSDU and not forward it to + any other ring... + + +*/ +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 + +/* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates that OLE found a valid SA entry for this MSDU + + +*/ +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 + +/* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates an unsuccessful MAC source address search due + to the expiring of the search timer for this MSDU + + +*/ +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 + +/* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates that OLE found a valid DA entry for this MSDU + + +*/ +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 + +/* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC + + Field Only valid if da_is_valid is set + + + + Indicates the DA address was a Multicast of Broadcast + address for this MSDU + + +*/ +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 + +/* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates an unsuccessful MAC destination address search + due to the expiring of the search timer for this MSDU + + +*/ +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 + +/* Description RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A + + +*/ +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000058 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28 +#define RX_MSDU_LINK_22_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000 + +/* Description RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A + + +*/ +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000005c +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0 +#define RX_MSDU_LINK_23_MSDU_3_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff + + /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_4 */ + + + /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */ + + +/* Description RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000060 +#define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_24_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000064 +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + +*/ +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000064 +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 +#define RX_MSDU_LINK_25_MSDU_4_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 + + /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ + + +/* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + This is not the first MSDU in + the MPDU. + + This MSDU is the first one in the + MPDU. + + + + +*/ +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +/* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG + + Consumer: WBM/REO/SW/FW + + Producer: RXDMA + + + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + There are more MSDUs linked to + this MSDU that belongs to this MPDU + + this MSDU is the last one in the + MPDU. This setting is only allowed in combination with + 'Msdu_continuation' set to 0. This implies that when an msdu + is spread out over multiple buffers and thus + msdu_continuation is set, only for the very last buffer of + the msdu, can the 'last_msdu_in_mpdu_flag' be set. + + + + When both first_msdu_in_mpdu_flag and + last_msdu_in_mpdu_flag are set, the MPDU that this MSDU + belongs to only contains a single MSDU. + + + + + + +*/ +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +/* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION + + When set, this MSDU buffer was not able to hold the + entire MSDU. The next buffer will therefor contain + additional information related to this MSDU. + + + + +*/ +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +/* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH + + Parsed from RX_MSDU_START TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the First + buffer used by MSDU. + + + + Full MSDU length in bytes after decapsulation. + + + + This field is still valid for MPDU frames without + A-MSDU. It still represents MSDU length after decapsulation + + + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + + +*/ +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +/* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW2 ring + + Reo will push the frame + into the REO2SW3 ring + + Reo will push the frame + into the REO2SW4 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + Reo will push the frame + into the REO2SW5 ring (REO remaps this in chips without + REO2SW5 ring, e.g. Pine) + + Reo will push the frame + into the REO2SW6 ring (REO remaps this in chips without + REO2SW6 ring, e.g. Pine) + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + +*/ +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +/* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + When set, REO shall drop this MSDU and not forward it to + any other ring... + + +*/ +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 + +/* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates that OLE found a valid SA entry for this MSDU + + +*/ +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 + +/* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates an unsuccessful MAC source address search due + to the expiring of the search timer for this MSDU + + +*/ +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 + +/* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates that OLE found a valid DA entry for this MSDU + + +*/ +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 + +/* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC + + Field Only valid if da_is_valid is set + + + + Indicates the DA address was a Multicast of Broadcast + address for this MSDU + + +*/ +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 + +/* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates an unsuccessful MAC destination address search + due to the expiring of the search timer for this MSDU + + +*/ +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 + +/* Description RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A + + +*/ +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000068 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28 +#define RX_MSDU_LINK_26_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000 + +/* Description RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A + + +*/ +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000006c +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0 +#define RX_MSDU_LINK_27_MSDU_4_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff + + /* EXTERNAL REFERENCE : struct rx_msdu_details msdu_5 */ + + + /* EXTERNAL REFERENCE : struct buffer_addr_info buffer_addr_info_details */ + + +/* Description RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000070 +#define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0 +#define RX_MSDU_LINK_28_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000074 +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0 +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + +*/ +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000074 +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 11 +#define RX_MSDU_LINK_29_MSDU_5_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff800 + + /* EXTERNAL REFERENCE : struct rx_msdu_desc_info rx_msdu_desc_info_details */ + + +/* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + This is not the first MSDU in + the MPDU. + + This MSDU is the first one in the + MPDU. + + + + +*/ +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_LSB 0 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_MASK 0x00000001 + +/* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG + + Consumer: WBM/REO/SW/FW + + Producer: RXDMA + + + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + There are more MSDUs linked to + this MSDU that belongs to this MPDU + + this MSDU is the last one in the + MPDU. This setting is only allowed in combination with + 'Msdu_continuation' set to 0. This implies that when an msdu + is spread out over multiple buffers and thus + msdu_continuation is set, only for the very last buffer of + the msdu, can the 'last_msdu_in_mpdu_flag' be set. + + + + When both first_msdu_in_mpdu_flag and + last_msdu_in_mpdu_flag are set, the MPDU that this MSDU + belongs to only contains a single MSDU. + + + + + + +*/ +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_LSB 1 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_LAST_MSDU_IN_MPDU_FLAG_MASK 0x00000002 + +/* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION + + When set, this MSDU buffer was not able to hold the + entire MSDU. The next buffer will therefor contain + additional information related to this MSDU. + + + + +*/ +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB 2 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK 0x00000004 + +/* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH + + Parsed from RX_MSDU_START TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the First + buffer used by MSDU. + + + + Full MSDU length in bytes after decapsulation. + + + + This field is still valid for MPDU frames without + A-MSDU. It still represents MSDU length after decapsulation + + + + Or in case of RAW MPDUs, it indicates the length of the + entire MPDU (without FCS field) + + +*/ +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_LSB 3 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_LENGTH_MASK 0x0001fff8 + +/* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW2 ring + + Reo will push the frame + into the REO2SW3 ring + + Reo will push the frame + into the REO2SW4 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + Reo will push the frame + into the REO2SW5 ring (REO remaps this in chips without + REO2SW5 ring, e.g. Pine) + + Reo will push the frame + into the REO2SW6 ring (REO remaps this in chips without + REO2SW6 ring, e.g. Pine) + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + +*/ +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_LSB 17 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_REO_DESTINATION_INDICATION_MASK 0x003e0000 + +/* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + When set, REO shall drop this MSDU and not forward it to + any other ring... + + +*/ +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_LSB 22 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_MSDU_DROP_MASK 0x00400000 + +/* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates that OLE found a valid SA entry for this MSDU + + +*/ +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 23 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x00800000 + +/* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates an unsuccessful MAC source address search due + to the expiring of the search timer for this MSDU + + +*/ +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 24 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x01000000 + +/* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates that OLE found a valid DA entry for this MSDU + + +*/ +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 25 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x02000000 + +/* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC + + Field Only valid if da_is_valid is set + + + + Indicates the DA address was a Multicast of Broadcast + address for this MSDU + + +*/ +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 26 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x04000000 + +/* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT + + Parsed from RX_MSDU_END TLV . In the case MSDU spans + over multiple buffers, this field will be valid in the Last + buffer used by the MSDU + + + + Indicates an unsuccessful MAC destination address search + due to the expiring of the search timer for this MSDU + + +*/ +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 27 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x08000000 + +/* Description RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A + + +*/ +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_OFFSET 0x00000078 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_LSB 28 +#define RX_MSDU_LINK_30_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_0A_MASK 0xf0000000 + +/* Description RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A + + +*/ +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000007c +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_LSB 0 +#define RX_MSDU_LINK_31_MSDU_5_RX_MSDU_DESC_INFO_DETAILS_RESERVED_1A_MASK 0xffffffff + + +#endif // _RX_MSDU_LINK_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/rx_msdu_start.h b/drivers/staging/fw-api/hw/qca6750/v1/rx_msdu_start.h new file mode 100644 index 000000000000..29ab1a1a9a87 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/rx_msdu_start.h @@ -0,0 +1,1207 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_MSDU_START_H_ +#define _RX_MSDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 rxpcu_mpdu_filter_in_category[1:0], sw_frame_group_id[8:2], reserved_0[15:9], phy_ppdu_id[31:16] +// 1 msdu_length[13:0], reserved_1a[14], ipsec_esp[15], l3_offset[22:16], ipsec_ah[23], l4_offset[31:24] +// 2 msdu_number[7:0], decap_format[9:8], ipv4_proto[10], ipv6_proto[11], tcp_proto[12], udp_proto[13], ip_frag[14], tcp_only_ack[15], da_is_bcast_mcast[16], toeplitz_hash_sel[18:17], ip_fixed_header_valid[19], ip_extn_header_valid[20], tcp_udp_header_valid[21], mesh_control_present[22], ldpc[23], ip4_protocol_ip6_next_header[31:24] +// 3 toeplitz_hash_2_or_4[31:0] +// 4 flow_id_toeplitz[31:0] +// 5 user_rssi[7:0], pkt_type[11:8], stbc[12], sgi[14:13], rate_mcs[18:15], receive_bandwidth[20:19], reception_type[23:21], mimo_ss_bitmap[31:24] +// 6 ppdu_start_timestamp[31:0] +// 7 sw_phy_meta_data[31:0] +// 8 vlan_ctag_ci[15:0], vlan_stag_ci[31:16] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_MSDU_START 9 + +struct rx_msdu_start { + uint32_t rxpcu_mpdu_filter_in_category : 2, //[1:0] + sw_frame_group_id : 7, //[8:2] + reserved_0 : 7, //[15:9] + phy_ppdu_id : 16; //[31:16] + uint32_t msdu_length : 14, //[13:0] + reserved_1a : 1, //[14] + ipsec_esp : 1, //[15] + l3_offset : 7, //[22:16] + ipsec_ah : 1, //[23] + l4_offset : 8; //[31:24] + uint32_t msdu_number : 8, //[7:0] + decap_format : 2, //[9:8] + ipv4_proto : 1, //[10] + ipv6_proto : 1, //[11] + tcp_proto : 1, //[12] + udp_proto : 1, //[13] + ip_frag : 1, //[14] + tcp_only_ack : 1, //[15] + da_is_bcast_mcast : 1, //[16] + toeplitz_hash_sel : 2, //[18:17] + ip_fixed_header_valid : 1, //[19] + ip_extn_header_valid : 1, //[20] + tcp_udp_header_valid : 1, //[21] + mesh_control_present : 1, //[22] + ldpc : 1, //[23] + ip4_protocol_ip6_next_header : 8; //[31:24] + uint32_t toeplitz_hash_2_or_4 : 32; //[31:0] + uint32_t flow_id_toeplitz : 32; //[31:0] + uint32_t user_rssi : 8, //[7:0] + pkt_type : 4, //[11:8] + stbc : 1, //[12] + sgi : 2, //[14:13] + rate_mcs : 4, //[18:15] + receive_bandwidth : 2, //[20:19] + reception_type : 3, //[23:21] + mimo_ss_bitmap : 8; //[31:24] + uint32_t ppdu_start_timestamp : 32; //[31:0] + uint32_t sw_phy_meta_data : 32; //[31:0] + uint32_t vlan_ctag_ci : 16, //[15:0] + vlan_stag_ci : 16; //[31:16] +}; + +/* + +rxpcu_mpdu_filter_in_category + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + + This MPDU passed the normal + frame filter programming of rxpcu + + This MPDU did NOT pass the + regular frame filter and would have been dropped, were it + not for the frame fitting into the 'monitor_client' + category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the + rxpcu_monitor_client filter. It would have been dropped + accept that it did pass the 'monitor_other' category. + + + +sw_frame_group_id + + SW processes frames based on certain classifications. + This field indicates to what sw classification this MPDU is + mapped. + + The classification is given in priority order + + + + + + + + + + + + This includes mpdus + of type Data Null as well as QoS Data Null + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + + + + + + + +reserved_0 + + + +phy_ppdu_id + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + + +msdu_length + + MSDU length in bytes after decapsulation. + + + + This field is still valid for MPDU frames without + +reserved_1a + + + +ipsec_esp + + Set if IPv4/v6 packet is using IPsec ESP + +l3_offset + + Depending upon mode bit, this field either indicates the + L3 offset in bytes from the start of the RX_HEADER or the IP + offset in bytes from the start of the packet after + decapsulation.  The latter is only valid if ipv4_proto or + ipv6_proto is set. + +ipsec_ah + + Set if IPv4/v6 packet is using IPsec AH + +l4_offset + + Depending upon mode bit, this field either indicates the + L4 offset nin bytes from the start of RX_HEADER(only valid + if either ipv4_proto or ipv6_proto is set to 1) or indicates + the offset in bytes to the start of TCP or UDP header from + the start of the IP header after decapsulation(Only valid if + tcp_proto or udp_proto is set).  The value 0 indicates that + the offset is longer than 127 bytes. + +msdu_number + + Indicates the MSDU number within a MPDU. This value is + reset to zero at the start of each MPDU. If the number of + MSDU exceeds 255 this number will wrap using modulo 256. + +decap_format + + Indicates the format after decapsulation: + + + + No encapsulation + + + + Ethernet 2 (DIX) or 802.3 (uses + SNAP/LLC) + + Indicate Ethernet + + + + + +ipv4_proto + + Set if L2 layer indicates IPv4 protocol. + +ipv6_proto + + Set if L2 layer indicates IPv6 protocol. + +tcp_proto + + Set if the ipv4_proto or ipv6_proto are set and the IP + protocol indicates TCP. + +udp_proto + + Set if the ipv4_proto or ipv6_proto are set and the IP + protocol indicates UDP. + +ip_frag + + Indicates that either the IP More frag bit is set or IP + frag number is non-zero. If set indicates that this is a + fragmented IP packet. + +tcp_only_ack + + Set if only the TCP Ack bit is set in the TCP flags and + if the TCP payload is 0. + +da_is_bcast_mcast + + The destination address is broadcast or multicast. + +toeplitz_hash_sel + + Actual choosen Hash. + + + + 0 -> Toeplitz hash of 2-tuple (IP source address, IP + destination address)1 -> Toeplitz hash of 4-tuple (IP source + address, IP destination address, L4 (TCP/UDP) source port, + L4 (TCP/UDP) destination port) + + 2 -> Toeplitz of flow_id + + 3 -> Zero is used + + + +ip_fixed_header_valid + + Fixed 20-byte IPv4 header or 40-byte IPv6 header parsed + fully within first 256 bytes of the packet + +ip_extn_header_valid + + IPv6/IPv6 header, including IPv4 options and + recognizable extension headers parsed fully within first 256 + bytes of the packet + +tcp_udp_header_valid + + Fixed 20-byte TCP (excluding TCP options) or 8-byte UDP + header parsed fully within first 256 bytes of the packet + +mesh_control_present + + When set, this MSDU includes the 'Mesh Control' field + + + +ldpc + + When set, indicates that LDPC coding was used. + + + +ip4_protocol_ip6_next_header + + For IPv4 this is the 8 bit protocol field (when + ipv4_proto is set). For IPv6 this is the 8 bit next_header + field (when ipv6_proto is set). + +toeplitz_hash_2_or_4 + + Controlled by multiple RxOLE registers for TCP/UDP over + IPv4/IPv6 - Either, Toeplitz hash computed over 2-tuple IPv4 + or IPv6 src/dest addresses is reported; or, Toeplitz hash + computed over 4-tuple IPv4 or IPv6 src/dest addresses and + src/dest ports is reported. The Flow_id_toeplitz hash can + also be reported here. Usually the hash reported here is the + one used for hash-based REO routing (see + use_flow_id_toeplitz_clfy in 'RXPT_CLASSIFY_INFO'). + + + + In Pine, optionally the 3-tuple Toeplitz hash over IPv4 + or IPv6 src/dest addresses and L4 protocol can be reported + here. (Unsupported in HastingsPrime) + +flow_id_toeplitz + + Toeplitz hash of 5-tuple + + {IP source address, IP destination address, IP source + port, IP destination port, L4 protocol} in case of + non-IPSec. + + In case of IPSec - Toeplitz hash of 4-tuple + + {IP source address, IP destination address, SPI, L4 + protocol} + + + + In Pine, optionally the 3-tuple Toeplitz hash over IPv4 + or IPv6 src/dest addresses and L4 protocol can be reported + here. (Unsupported in HastingsPrime) + + + + The relevant Toeplitz key registers are provided in + RxOLE's instance of common parser module. These registers + are separate from the Toeplitz keys used by ASE/FSE modules + inside RxOLE.The actual value will be passed on from common + parser module to RxOLE in one of the WHO_* TLVs. + + + +user_rssi + + RSSI for this user + + + +pkt_type + + Packet type: + + 802.11a PPDU type + + 802.11b PPDU type + + 802.11n Mixed Mode PPDU type + + 802.11ac PPDU type + + 802.11ax PPDU type + + 802.11ba (WUR) PPDU type + +stbc + + When set, use STBC transmission rates + +sgi + + Field only valid when pkt type is HT, VHT or HE. + + + + Legacy normal GI. Can also be + used for HE + + Legacy short GI. Can also be + used for HE + + HE related GI + + HE related GI + + + +rate_mcs + + For details, refer to MCS_TYPE description + + Note: This is rate in case of 11a/11b + + + + + +receive_bandwidth + + Full receive Bandwidth + + + + + + + + + + + + + + + +reception_type + + Indicates what type of reception this is. + + Basic SU reception (not + part of OFDMA or MIMO) + + This is related to + DL type of reception + + This is related + to DL type of reception + + This is + related to DL type of reception + + This is related + to UL type of reception + + This is + related to UL type of reception + + This is + related to UL type of reception + + + + + +mimo_ss_bitmap + + Field only valid when Reception_type for the MPDU from + this STA is some form of MIMO reception + + + + Bitmap, with each bit indicating if the related spatial + stream is used for this STA + + LSB related to SS 0 + + + + 0: spatial stream not used for this reception + + 1: spatial stream used for this reception + + + + + +ppdu_start_timestamp + + Timestamp that indicates when the PPDU that contained + this MPDU started on the medium. + + + +sw_phy_meta_data + + SW programmed Meta data provided by the PHY. + + + + Can be used for SW to indicate the channel the device is + on. + + + +vlan_ctag_ci + + 2 bytes of C-VLAN Tag Control Information from + WHO_L2_LLC + +vlan_stag_ci + + 2 bytes of S-VLAN Tag Control Information from + WHO_L2_LLC in case of double VLAN +*/ + + +/* Description RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY + + Field indicates what the reason was that this MPDU frame + was allowed to come into the receive path by RXPCU + + This MPDU passed the normal + frame filter programming of rxpcu + + This MPDU did NOT pass the + regular frame filter and would have been dropped, were it + not for the frame fitting into the 'monitor_client' + category. + + This MPDU did NOT pass the + regular frame filter and also did not pass the + rxpcu_monitor_client filter. It would have been dropped + accept that it did pass the 'monitor_other' category. + + +*/ +#define RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 0x00000000 +#define RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY_LSB 0 +#define RX_MSDU_START_0_RXPCU_MPDU_FILTER_IN_CATEGORY_MASK 0x00000003 + +/* Description RX_MSDU_START_0_SW_FRAME_GROUP_ID + + SW processes frames based on certain classifications. + This field indicates to what sw classification this MPDU is + mapped. + + The classification is given in priority order + + + + + + + + + + + + This includes mpdus + of type Data Null as well as QoS Data Null + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + This covers type 3 + and protocol version != 0 + + + + + + + +*/ +#define RX_MSDU_START_0_SW_FRAME_GROUP_ID_OFFSET 0x00000000 +#define RX_MSDU_START_0_SW_FRAME_GROUP_ID_LSB 2 +#define RX_MSDU_START_0_SW_FRAME_GROUP_ID_MASK 0x000001fc + +/* Description RX_MSDU_START_0_RESERVED_0 + + +*/ +#define RX_MSDU_START_0_RESERVED_0_OFFSET 0x00000000 +#define RX_MSDU_START_0_RESERVED_0_LSB 9 +#define RX_MSDU_START_0_RESERVED_0_MASK 0x0000fe00 + +/* Description RX_MSDU_START_0_PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + +*/ +#define RX_MSDU_START_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_MSDU_START_0_PHY_PPDU_ID_LSB 16 +#define RX_MSDU_START_0_PHY_PPDU_ID_MASK 0xffff0000 + +/* Description RX_MSDU_START_1_MSDU_LENGTH + + MSDU length in bytes after decapsulation. + + + + This field is still valid for MPDU frames without +*/ +#define RX_MSDU_START_1_MSDU_LENGTH_OFFSET 0x00000004 +#define RX_MSDU_START_1_MSDU_LENGTH_LSB 0 +#define RX_MSDU_START_1_MSDU_LENGTH_MASK 0x00003fff + +/* Description RX_MSDU_START_1_RESERVED_1A + + +*/ +#define RX_MSDU_START_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_MSDU_START_1_RESERVED_1A_LSB 14 +#define RX_MSDU_START_1_RESERVED_1A_MASK 0x00004000 + +/* Description RX_MSDU_START_1_IPSEC_ESP + + Set if IPv4/v6 packet is using IPsec ESP +*/ +#define RX_MSDU_START_1_IPSEC_ESP_OFFSET 0x00000004 +#define RX_MSDU_START_1_IPSEC_ESP_LSB 15 +#define RX_MSDU_START_1_IPSEC_ESP_MASK 0x00008000 + +/* Description RX_MSDU_START_1_L3_OFFSET + + Depending upon mode bit, this field either indicates the + L3 offset in bytes from the start of the RX_HEADER or the IP + offset in bytes from the start of the packet after + decapsulation.  The latter is only valid if ipv4_proto or + ipv6_proto is set. +*/ +#define RX_MSDU_START_1_L3_OFFSET_OFFSET 0x00000004 +#define RX_MSDU_START_1_L3_OFFSET_LSB 16 +#define RX_MSDU_START_1_L3_OFFSET_MASK 0x007f0000 + +/* Description RX_MSDU_START_1_IPSEC_AH + + Set if IPv4/v6 packet is using IPsec AH +*/ +#define RX_MSDU_START_1_IPSEC_AH_OFFSET 0x00000004 +#define RX_MSDU_START_1_IPSEC_AH_LSB 23 +#define RX_MSDU_START_1_IPSEC_AH_MASK 0x00800000 + +/* Description RX_MSDU_START_1_L4_OFFSET + + Depending upon mode bit, this field either indicates the + L4 offset nin bytes from the start of RX_HEADER(only valid + if either ipv4_proto or ipv6_proto is set to 1) or indicates + the offset in bytes to the start of TCP or UDP header from + the start of the IP header after decapsulation(Only valid if + tcp_proto or udp_proto is set).  The value 0 indicates that + the offset is longer than 127 bytes. +*/ +#define RX_MSDU_START_1_L4_OFFSET_OFFSET 0x00000004 +#define RX_MSDU_START_1_L4_OFFSET_LSB 24 +#define RX_MSDU_START_1_L4_OFFSET_MASK 0xff000000 + +/* Description RX_MSDU_START_2_MSDU_NUMBER + + Indicates the MSDU number within a MPDU. This value is + reset to zero at the start of each MPDU. If the number of + MSDU exceeds 255 this number will wrap using modulo 256. +*/ +#define RX_MSDU_START_2_MSDU_NUMBER_OFFSET 0x00000008 +#define RX_MSDU_START_2_MSDU_NUMBER_LSB 0 +#define RX_MSDU_START_2_MSDU_NUMBER_MASK 0x000000ff + +/* Description RX_MSDU_START_2_DECAP_FORMAT + + Indicates the format after decapsulation: + + + + No encapsulation + + + + Ethernet 2 (DIX) or 802.3 (uses + SNAP/LLC) + + Indicate Ethernet + + + + +*/ +#define RX_MSDU_START_2_DECAP_FORMAT_OFFSET 0x00000008 +#define RX_MSDU_START_2_DECAP_FORMAT_LSB 8 +#define RX_MSDU_START_2_DECAP_FORMAT_MASK 0x00000300 + +/* Description RX_MSDU_START_2_IPV4_PROTO + + Set if L2 layer indicates IPv4 protocol. +*/ +#define RX_MSDU_START_2_IPV4_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_2_IPV4_PROTO_LSB 10 +#define RX_MSDU_START_2_IPV4_PROTO_MASK 0x00000400 + +/* Description RX_MSDU_START_2_IPV6_PROTO + + Set if L2 layer indicates IPv6 protocol. +*/ +#define RX_MSDU_START_2_IPV6_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_2_IPV6_PROTO_LSB 11 +#define RX_MSDU_START_2_IPV6_PROTO_MASK 0x00000800 + +/* Description RX_MSDU_START_2_TCP_PROTO + + Set if the ipv4_proto or ipv6_proto are set and the IP + protocol indicates TCP. +*/ +#define RX_MSDU_START_2_TCP_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_2_TCP_PROTO_LSB 12 +#define RX_MSDU_START_2_TCP_PROTO_MASK 0x00001000 + +/* Description RX_MSDU_START_2_UDP_PROTO + + Set if the ipv4_proto or ipv6_proto are set and the IP + protocol indicates UDP. +*/ +#define RX_MSDU_START_2_UDP_PROTO_OFFSET 0x00000008 +#define RX_MSDU_START_2_UDP_PROTO_LSB 13 +#define RX_MSDU_START_2_UDP_PROTO_MASK 0x00002000 + +/* Description RX_MSDU_START_2_IP_FRAG + + Indicates that either the IP More frag bit is set or IP + frag number is non-zero. If set indicates that this is a + fragmented IP packet. +*/ +#define RX_MSDU_START_2_IP_FRAG_OFFSET 0x00000008 +#define RX_MSDU_START_2_IP_FRAG_LSB 14 +#define RX_MSDU_START_2_IP_FRAG_MASK 0x00004000 + +/* Description RX_MSDU_START_2_TCP_ONLY_ACK + + Set if only the TCP Ack bit is set in the TCP flags and + if the TCP payload is 0. +*/ +#define RX_MSDU_START_2_TCP_ONLY_ACK_OFFSET 0x00000008 +#define RX_MSDU_START_2_TCP_ONLY_ACK_LSB 15 +#define RX_MSDU_START_2_TCP_ONLY_ACK_MASK 0x00008000 + +/* Description RX_MSDU_START_2_DA_IS_BCAST_MCAST + + The destination address is broadcast or multicast. +*/ +#define RX_MSDU_START_2_DA_IS_BCAST_MCAST_OFFSET 0x00000008 +#define RX_MSDU_START_2_DA_IS_BCAST_MCAST_LSB 16 +#define RX_MSDU_START_2_DA_IS_BCAST_MCAST_MASK 0x00010000 + +/* Description RX_MSDU_START_2_TOEPLITZ_HASH_SEL + + Actual choosen Hash. + + + + 0 -> Toeplitz hash of 2-tuple (IP source address, IP + destination address)1 -> Toeplitz hash of 4-tuple (IP source + address, IP destination address, L4 (TCP/UDP) source port, + L4 (TCP/UDP) destination port) + + 2 -> Toeplitz of flow_id + + 3 -> Zero is used + + +*/ +#define RX_MSDU_START_2_TOEPLITZ_HASH_SEL_OFFSET 0x00000008 +#define RX_MSDU_START_2_TOEPLITZ_HASH_SEL_LSB 17 +#define RX_MSDU_START_2_TOEPLITZ_HASH_SEL_MASK 0x00060000 + +/* Description RX_MSDU_START_2_IP_FIXED_HEADER_VALID + + Fixed 20-byte IPv4 header or 40-byte IPv6 header parsed + fully within first 256 bytes of the packet +*/ +#define RX_MSDU_START_2_IP_FIXED_HEADER_VALID_OFFSET 0x00000008 +#define RX_MSDU_START_2_IP_FIXED_HEADER_VALID_LSB 19 +#define RX_MSDU_START_2_IP_FIXED_HEADER_VALID_MASK 0x00080000 + +/* Description RX_MSDU_START_2_IP_EXTN_HEADER_VALID + + IPv6/IPv6 header, including IPv4 options and + recognizable extension headers parsed fully within first 256 + bytes of the packet +*/ +#define RX_MSDU_START_2_IP_EXTN_HEADER_VALID_OFFSET 0x00000008 +#define RX_MSDU_START_2_IP_EXTN_HEADER_VALID_LSB 20 +#define RX_MSDU_START_2_IP_EXTN_HEADER_VALID_MASK 0x00100000 + +/* Description RX_MSDU_START_2_TCP_UDP_HEADER_VALID + + Fixed 20-byte TCP (excluding TCP options) or 8-byte UDP + header parsed fully within first 256 bytes of the packet +*/ +#define RX_MSDU_START_2_TCP_UDP_HEADER_VALID_OFFSET 0x00000008 +#define RX_MSDU_START_2_TCP_UDP_HEADER_VALID_LSB 21 +#define RX_MSDU_START_2_TCP_UDP_HEADER_VALID_MASK 0x00200000 + +/* Description RX_MSDU_START_2_MESH_CONTROL_PRESENT + + When set, this MSDU includes the 'Mesh Control' field + + +*/ +#define RX_MSDU_START_2_MESH_CONTROL_PRESENT_OFFSET 0x00000008 +#define RX_MSDU_START_2_MESH_CONTROL_PRESENT_LSB 22 +#define RX_MSDU_START_2_MESH_CONTROL_PRESENT_MASK 0x00400000 + +/* Description RX_MSDU_START_2_LDPC + + When set, indicates that LDPC coding was used. + + +*/ +#define RX_MSDU_START_2_LDPC_OFFSET 0x00000008 +#define RX_MSDU_START_2_LDPC_LSB 23 +#define RX_MSDU_START_2_LDPC_MASK 0x00800000 + +/* Description RX_MSDU_START_2_IP4_PROTOCOL_IP6_NEXT_HEADER + + For IPv4 this is the 8 bit protocol field (when + ipv4_proto is set). For IPv6 this is the 8 bit next_header + field (when ipv6_proto is set). +*/ +#define RX_MSDU_START_2_IP4_PROTOCOL_IP6_NEXT_HEADER_OFFSET 0x00000008 +#define RX_MSDU_START_2_IP4_PROTOCOL_IP6_NEXT_HEADER_LSB 24 +#define RX_MSDU_START_2_IP4_PROTOCOL_IP6_NEXT_HEADER_MASK 0xff000000 + +/* Description RX_MSDU_START_3_TOEPLITZ_HASH_2_OR_4 + + Controlled by multiple RxOLE registers for TCP/UDP over + IPv4/IPv6 - Either, Toeplitz hash computed over 2-tuple IPv4 + or IPv6 src/dest addresses is reported; or, Toeplitz hash + computed over 4-tuple IPv4 or IPv6 src/dest addresses and + src/dest ports is reported. The Flow_id_toeplitz hash can + also be reported here. Usually the hash reported here is the + one used for hash-based REO routing (see + use_flow_id_toeplitz_clfy in 'RXPT_CLASSIFY_INFO'). + + + + In Pine, optionally the 3-tuple Toeplitz hash over IPv4 + or IPv6 src/dest addresses and L4 protocol can be reported + here. (Unsupported in HastingsPrime) +*/ +#define RX_MSDU_START_3_TOEPLITZ_HASH_2_OR_4_OFFSET 0x0000000c +#define RX_MSDU_START_3_TOEPLITZ_HASH_2_OR_4_LSB 0 +#define RX_MSDU_START_3_TOEPLITZ_HASH_2_OR_4_MASK 0xffffffff + +/* Description RX_MSDU_START_4_FLOW_ID_TOEPLITZ + + Toeplitz hash of 5-tuple + + {IP source address, IP destination address, IP source + port, IP destination port, L4 protocol} in case of + non-IPSec. + + In case of IPSec - Toeplitz hash of 4-tuple + + {IP source address, IP destination address, SPI, L4 + protocol} + + + + In Pine, optionally the 3-tuple Toeplitz hash over IPv4 + or IPv6 src/dest addresses and L4 protocol can be reported + here. (Unsupported in HastingsPrime) + + + + The relevant Toeplitz key registers are provided in + RxOLE's instance of common parser module. These registers + are separate from the Toeplitz keys used by ASE/FSE modules + inside RxOLE.The actual value will be passed on from common + parser module to RxOLE in one of the WHO_* TLVs. + + +*/ +#define RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET 0x00000010 +#define RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB 0 +#define RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK 0xffffffff + +/* Description RX_MSDU_START_5_USER_RSSI + + RSSI for this user + + +*/ +#define RX_MSDU_START_5_USER_RSSI_OFFSET 0x00000014 +#define RX_MSDU_START_5_USER_RSSI_LSB 0 +#define RX_MSDU_START_5_USER_RSSI_MASK 0x000000ff + +/* Description RX_MSDU_START_5_PKT_TYPE + + Packet type: + + 802.11a PPDU type + + 802.11b PPDU type + + 802.11n Mixed Mode PPDU type + + 802.11ac PPDU type + + 802.11ax PPDU type + + 802.11ba (WUR) PPDU type +*/ +#define RX_MSDU_START_5_PKT_TYPE_OFFSET 0x00000014 +#define RX_MSDU_START_5_PKT_TYPE_LSB 8 +#define RX_MSDU_START_5_PKT_TYPE_MASK 0x00000f00 + +/* Description RX_MSDU_START_5_STBC + + When set, use STBC transmission rates +*/ +#define RX_MSDU_START_5_STBC_OFFSET 0x00000014 +#define RX_MSDU_START_5_STBC_LSB 12 +#define RX_MSDU_START_5_STBC_MASK 0x00001000 + +/* Description RX_MSDU_START_5_SGI + + Field only valid when pkt type is HT, VHT or HE. + + + + Legacy normal GI. Can also be + used for HE + + Legacy short GI. Can also be + used for HE + + HE related GI + + HE related GI + + +*/ +#define RX_MSDU_START_5_SGI_OFFSET 0x00000014 +#define RX_MSDU_START_5_SGI_LSB 13 +#define RX_MSDU_START_5_SGI_MASK 0x00006000 + +/* Description RX_MSDU_START_5_RATE_MCS + + For details, refer to MCS_TYPE description + + Note: This is rate in case of 11a/11b + + + + +*/ +#define RX_MSDU_START_5_RATE_MCS_OFFSET 0x00000014 +#define RX_MSDU_START_5_RATE_MCS_LSB 15 +#define RX_MSDU_START_5_RATE_MCS_MASK 0x00078000 + +/* Description RX_MSDU_START_5_RECEIVE_BANDWIDTH + + Full receive Bandwidth + + + + + + + + + + + + + + +*/ +#define RX_MSDU_START_5_RECEIVE_BANDWIDTH_OFFSET 0x00000014 +#define RX_MSDU_START_5_RECEIVE_BANDWIDTH_LSB 19 +#define RX_MSDU_START_5_RECEIVE_BANDWIDTH_MASK 0x00180000 + +/* Description RX_MSDU_START_5_RECEPTION_TYPE + + Indicates what type of reception this is. + + Basic SU reception (not + part of OFDMA or MIMO) + + This is related to + DL type of reception + + This is related + to DL type of reception + + This is + related to DL type of reception + + This is related + to UL type of reception + + This is + related to UL type of reception + + This is + related to UL type of reception + + + + +*/ +#define RX_MSDU_START_5_RECEPTION_TYPE_OFFSET 0x00000014 +#define RX_MSDU_START_5_RECEPTION_TYPE_LSB 21 +#define RX_MSDU_START_5_RECEPTION_TYPE_MASK 0x00e00000 + +/* Description RX_MSDU_START_5_MIMO_SS_BITMAP + + Field only valid when Reception_type for the MPDU from + this STA is some form of MIMO reception + + + + Bitmap, with each bit indicating if the related spatial + stream is used for this STA + + LSB related to SS 0 + + + + 0: spatial stream not used for this reception + + 1: spatial stream used for this reception + + + + +*/ +#define RX_MSDU_START_5_MIMO_SS_BITMAP_OFFSET 0x00000014 +#define RX_MSDU_START_5_MIMO_SS_BITMAP_LSB 24 +#define RX_MSDU_START_5_MIMO_SS_BITMAP_MASK 0xff000000 + +/* Description RX_MSDU_START_6_PPDU_START_TIMESTAMP + + Timestamp that indicates when the PPDU that contained + this MPDU started on the medium. + + +*/ +#define RX_MSDU_START_6_PPDU_START_TIMESTAMP_OFFSET 0x00000018 +#define RX_MSDU_START_6_PPDU_START_TIMESTAMP_LSB 0 +#define RX_MSDU_START_6_PPDU_START_TIMESTAMP_MASK 0xffffffff + +/* Description RX_MSDU_START_7_SW_PHY_META_DATA + + SW programmed Meta data provided by the PHY. + + + + Can be used for SW to indicate the channel the device is + on. + + +*/ +#define RX_MSDU_START_7_SW_PHY_META_DATA_OFFSET 0x0000001c +#define RX_MSDU_START_7_SW_PHY_META_DATA_LSB 0 +#define RX_MSDU_START_7_SW_PHY_META_DATA_MASK 0xffffffff + +/* Description RX_MSDU_START_8_VLAN_CTAG_CI + + 2 bytes of C-VLAN Tag Control Information from + WHO_L2_LLC +*/ +#define RX_MSDU_START_8_VLAN_CTAG_CI_OFFSET 0x00000020 +#define RX_MSDU_START_8_VLAN_CTAG_CI_LSB 0 +#define RX_MSDU_START_8_VLAN_CTAG_CI_MASK 0x0000ffff + +/* Description RX_MSDU_START_8_VLAN_STAG_CI + + 2 bytes of S-VLAN Tag Control Information from + WHO_L2_LLC in case of double VLAN +*/ +#define RX_MSDU_START_8_VLAN_STAG_CI_OFFSET 0x00000020 +#define RX_MSDU_START_8_VLAN_STAG_CI_LSB 16 +#define RX_MSDU_START_8_VLAN_STAG_CI_MASK 0xffff0000 + + +#endif // _RX_MSDU_START_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/rx_ppdu_end_user_stats.h b/drivers/staging/fw-api/hw/qca6750/v1/rx_ppdu_end_user_stats.h new file mode 100644 index 000000000000..7dd17598723c --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/rx_ppdu_end_user_stats.h @@ -0,0 +1,2157 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_PPDU_END_USER_STATS_H_ +#define _RX_PPDU_END_USER_STATS_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_rxpcu_classification_overview.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 struct rx_rxpcu_classification_overview rxpcu_classification_details; +// 1 sta_full_aid[12:0], mcs[16:13], nss[19:17], ofdma_info_valid[20], dl_ofdma_ru_start_index[27:21], reserved_1a[31:28] +// 2 dl_ofdma_ru_width[6:0], reserved_2a[7], user_receive_quality[15:8], mpdu_cnt_fcs_err[25:16], wbm2rxdma_buf_source_used[26], fw2rxdma_buf_source_used[27], sw2rxdma_buf_source_used[28], reserved_2b[31:29] +// 3 mpdu_cnt_fcs_ok[8:0], frame_control_info_valid[9], qos_control_info_valid[10], ht_control_info_valid[11], data_sequence_control_info_valid[12], ht_control_info_null_valid[13], reserved_3a[15:14], rxdma2reo_ring_used[16], rxdma2fw_ring_used[17], rxdma2sw_ring_used[18], rxdma_release_ring_used[19], ht_control_field_pkt_type[23:20], reserved_3b[31:24] +// 4 ast_index[15:0], frame_control_field[31:16] +// 5 first_data_seq_ctrl[15:0], qos_control_field[31:16] +// 6 ht_control_field[31:0] +// 7 fcs_ok_bitmap_31_0[31:0] +// 8 fcs_ok_bitmap_63_32[31:0] +// 9 udp_msdu_count[15:0], tcp_msdu_count[31:16] +// 10 other_msdu_count[15:0], tcp_ack_msdu_count[31:16] +// 11 sw_response_reference_ptr[31:0] +// 12 received_qos_data_tid_bitmap[15:0], received_qos_data_tid_eosp_bitmap[31:16] +// 13 qosctrl_15_8_tid0[7:0], qosctrl_15_8_tid1[15:8], qosctrl_15_8_tid2[23:16], qosctrl_15_8_tid3[31:24] +// 14 qosctrl_15_8_tid4[7:0], qosctrl_15_8_tid5[15:8], qosctrl_15_8_tid6[23:16], qosctrl_15_8_tid7[31:24] +// 15 qosctrl_15_8_tid8[7:0], qosctrl_15_8_tid9[15:8], qosctrl_15_8_tid10[23:16], qosctrl_15_8_tid11[31:24] +// 16 qosctrl_15_8_tid12[7:0], qosctrl_15_8_tid13[15:8], qosctrl_15_8_tid14[23:16], qosctrl_15_8_tid15[31:24] +// 17 mpdu_ok_byte_count[24:0], ampdu_delim_ok_count_6_0[31:25] +// 18 ampdu_delim_err_count[24:0], ampdu_delim_ok_count_13_7[31:25] +// 19 mpdu_err_byte_count[24:0], ampdu_delim_ok_count_20_14[31:25] +// 20 non_consecutive_delimiter_err[15:0], reserved_20a[31:16] +// 21 ht_control_null_field[31:0] +// 22 sw_response_reference_ptr_ext[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS 23 + +struct rx_ppdu_end_user_stats { + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t sta_full_aid : 13, //[12:0] + mcs : 4, //[16:13] + nss : 3, //[19:17] + ofdma_info_valid : 1, //[20] + dl_ofdma_ru_start_index : 7, //[27:21] + reserved_1a : 4; //[31:28] + uint32_t dl_ofdma_ru_width : 7, //[6:0] + reserved_2a : 1, //[7] + user_receive_quality : 8, //[15:8] + mpdu_cnt_fcs_err : 10, //[25:16] + wbm2rxdma_buf_source_used : 1, //[26] + fw2rxdma_buf_source_used : 1, //[27] + sw2rxdma_buf_source_used : 1, //[28] + reserved_2b : 3; //[31:29] + uint32_t mpdu_cnt_fcs_ok : 9, //[8:0] + frame_control_info_valid : 1, //[9] + qos_control_info_valid : 1, //[10] + ht_control_info_valid : 1, //[11] + data_sequence_control_info_valid: 1, //[12] + ht_control_info_null_valid : 1, //[13] + reserved_3a : 2, //[15:14] + rxdma2reo_ring_used : 1, //[16] + rxdma2fw_ring_used : 1, //[17] + rxdma2sw_ring_used : 1, //[18] + rxdma_release_ring_used : 1, //[19] + ht_control_field_pkt_type : 4, //[23:20] + reserved_3b : 8; //[31:24] + uint32_t ast_index : 16, //[15:0] + frame_control_field : 16; //[31:16] + uint32_t first_data_seq_ctrl : 16, //[15:0] + qos_control_field : 16; //[31:16] + uint32_t ht_control_field : 32; //[31:0] + uint32_t fcs_ok_bitmap_31_0 : 32; //[31:0] + uint32_t fcs_ok_bitmap_63_32 : 32; //[31:0] + uint32_t udp_msdu_count : 16, //[15:0] + tcp_msdu_count : 16; //[31:16] + uint32_t other_msdu_count : 16, //[15:0] + tcp_ack_msdu_count : 16; //[31:16] + uint32_t sw_response_reference_ptr : 32; //[31:0] + uint32_t received_qos_data_tid_bitmap : 16, //[15:0] + received_qos_data_tid_eosp_bitmap: 16; //[31:16] + uint32_t qosctrl_15_8_tid0 : 8, //[7:0] + qosctrl_15_8_tid1 : 8, //[15:8] + qosctrl_15_8_tid2 : 8, //[23:16] + qosctrl_15_8_tid3 : 8; //[31:24] + uint32_t qosctrl_15_8_tid4 : 8, //[7:0] + qosctrl_15_8_tid5 : 8, //[15:8] + qosctrl_15_8_tid6 : 8, //[23:16] + qosctrl_15_8_tid7 : 8; //[31:24] + uint32_t qosctrl_15_8_tid8 : 8, //[7:0] + qosctrl_15_8_tid9 : 8, //[15:8] + qosctrl_15_8_tid10 : 8, //[23:16] + qosctrl_15_8_tid11 : 8; //[31:24] + uint32_t qosctrl_15_8_tid12 : 8, //[7:0] + qosctrl_15_8_tid13 : 8, //[15:8] + qosctrl_15_8_tid14 : 8, //[23:16] + qosctrl_15_8_tid15 : 8; //[31:24] + uint32_t mpdu_ok_byte_count : 25, //[24:0] + ampdu_delim_ok_count_6_0 : 7; //[31:25] + uint32_t ampdu_delim_err_count : 25, //[24:0] + ampdu_delim_ok_count_13_7 : 7; //[31:25] + uint32_t mpdu_err_byte_count : 25, //[24:0] + ampdu_delim_ok_count_20_14 : 7; //[31:25] + uint32_t non_consecutive_delimiter_err : 16, //[15:0] + reserved_20a : 16; //[31:16] + uint32_t ht_control_null_field : 32; //[31:0] + uint32_t sw_response_reference_ptr_ext : 32; //[31:0] +}; + +/* + +struct rx_rxpcu_classification_overview rxpcu_classification_details + + Details related to what RXPCU classification types of + MPDUs have been received + +sta_full_aid + + Consumer: FW + + Producer: RXPCU + + + + The full AID of this station. + + + + + +mcs + + MCS of the received frame + + + + For details, refer to MCS_TYPE description + + Note: This is rate in case of 11a/11b + + + + + +nss + + Number of spatial streams. + + + + NOTE: RXPCU derives this from the 'Mimo_ss_bitmap' + + + + Single spatial stream + + 2 spatial streams + + 3 spatial streams + + 4 spatial streams + + 5 spatial streams + + 6 spatial streams + + 7 spatial streams + + 8 spatial streams + +ofdma_info_valid + + When set, ofdma RU related info in the following fields + is valid + + + +dl_ofdma_ru_start_index + + Field only valid when Ofdma_info_valid is set + + + + RU index number to which User is assigned + + RU numbering is over the entire BW, starting from 0 + + + +reserved_1a + + + +dl_ofdma_ru_width + + The size of the RU for this user. + + In units of 1 (26 tone) RU + + + +reserved_2a + + + +user_receive_quality + + DO NOT USE + + + + Field not populated by MAC HW + + + +mpdu_cnt_fcs_err + + The number of MPDUs received from this STA in this PPDU + with FCS errors + + + +wbm2rxdma_buf_source_used + + Field filled in by RXDMA + + + + When set, RXDMA has used the wbm2rxdma_buf ring as + source for at least one of the frames in this PPDU. + +fw2rxdma_buf_source_used + + Field filled in by RXDMA + + + + When set, RXDMA has used the fw2rxdma_buf ring as source + for at least one of the frames in this PPDU. + +sw2rxdma_buf_source_used + + Field filled in by RXDMA + + + + When set, RXDMA has used the sw2rxdma_buf ring as source + for at least one of the frames in this PPDU. + +reserved_2b + + + +mpdu_cnt_fcs_ok + + The number of MPDUs received from this STA in this PPDU + with correct FCS + + + +frame_control_info_valid + + When set, the frame_control_info field contains valid + information + + + +qos_control_info_valid + + When set, the QoS_control_info field contains valid + information + + + +ht_control_info_valid + + When set, the HT_control_field contains valid + information + + + +data_sequence_control_info_valid + + When set, the First_data_seq_ctrl field contains valid + information + + + +ht_control_info_null_valid + + When set, the HT_control_NULL_field contains valid + information + + + +reserved_3a + + + +rxdma2reo_ring_used + + Field filled in by RXDMA + + + + Set when at least one frame during this PPDU got pushed + to this ring by RXDMA + +rxdma2fw_ring_used + + Field filled in by RXDMA + + + + Set when at least one frame during this PPDU got pushed + to this ring by RXDMA + +rxdma2sw_ring_used + + Field filled in by RXDMA + + + + Set when at least one frame during this PPDU got pushed + to this ring by RXDMA + +rxdma_release_ring_used + + Field filled in by RXDMA + + + + Set when at least one frame during this PPDU got pushed + to this ring by RXDMA + +ht_control_field_pkt_type + + Field only valid when HT_control_info_valid or + HT_control_info_NULL_valid is set. + + + + Indicates what the PHY receive type was for receiving + this frame. Can help determine if the HT_CONTROL field shall + be interpreted as HT/VHT or HE. + + + + NOTE: later on in the 11ax IEEE spec a bit within the HT + control field was introduced that explicitly indicated how + to interpret the HT control field.... As HT, VHT, or HE. + + + + 802.11a PPDU type + + 802.11b PPDU type + + 802.11n Mixed Mode PPDU type + + 802.11ac PPDU type + + 802.11ax PPDU type + + 802.11ba (WUR) PPDU type + +reserved_3b + + + +ast_index + + This field indicates the index of the AST entry + corresponding to this MPDU. It is provided by the GSE module + instantiated in RXPCU. + + A value of 0xFFFF indicates an invalid AST index, + meaning that No AST entry was found or NO AST search was + performed + + + +frame_control_field + + Field only valid when Frame_control_info_valid is set. + + + + Last successfully received Frame_control field of data + frame (excluding Data NULL/ QoS Null) for this user + + Mainly used to track the PM state of the transmitted + device + + + + NOTE: only data frame info is needed, as control and + management frames are already routed to the FW. + + + +first_data_seq_ctrl + + Field only valid when Data_sequence_control_info_valid + is set. + + + + Sequence control field of the first data frame + (excluding Data NULL or QoS Data null) received for this + user with correct FCS + + + + NOTE: only data frame info is needed, as control and + management frames are already routed to the FW. + + + +qos_control_field + + Field only valid when QoS_control_info_valid is set. + + + + Last successfully received QoS_control field of data + frame (excluding Data NULL/ QoS Null) for this user + + + + Note that in case of multi TID, this field can only + reflect the last properly received MPDU, and thus can not + indicate all potentially different TIDs that had been + received earlier. + + + + There are however per TID fields, that will contain + among other things all buffer status info: See + + QoSCtrl_15_8_tid??? + + + +ht_control_field + + Field only valid when HT_control_info_valid is set. + + + + Last successfully received + HT_CONTROL/VHT_CONTROL/HE_CONTROL field of data frames, + excluding QoS Null frames for this user. + + + + NOTE: HT control fields from QoS Null frames are + captured in field HT_control_NULL_field + + + +fcs_ok_bitmap_31_0 + + Bitmap indicates in order of received MPDUs, which MPDUs + had an passing FCS or had an error. + + 1: FCS OK + + 0: FCS error + + + +fcs_ok_bitmap_63_32 + + Bitmap indicates in order of received MPDUs, which MPDUs + had an passing FCS or had an error. + + 1: FCS OK + + 0: FCS error + + + + NOTE: for users 0, 1, 2 and 3, additional bitmap info + (up to 256 bitmap window) is provided in + RX_PPDU_END_USER_STATS_EXT TLV + + + +udp_msdu_count + + Field filled in by RX OLE + + Set to 0 by RXPCU + + + + The number of MSDUs that are part of MPDUs without FCS + error, that contain UDP frames. + + + +tcp_msdu_count + + Field filled in by RX OLE + + Set to 0 by RXPCU + + + + The number of MSDUs that are part of MPDUs without FCS + error, that contain TCP frames. + + + + (Note: This does NOT include TCP-ACK) + + + +other_msdu_count + + Field filled in by RX OLE + + Set to 0 by RXPCU + + + + The number of MSDUs that are part of MPDUs without FCS + error, that contain neither UDP or TCP frames. + + + + Includes Management and control frames. + + + + + +tcp_ack_msdu_count + + Field filled in by RX OLE + + Set to 0 by RXPCU + + + + The number of MSDUs that are part of MPDUs without FCS + error, that contain TCP ack frames. + + + +sw_response_reference_ptr + + Pointer that SW uses to refer back to an expected + response reception. Used for Rate adaptation purposes. + + When a reception occurs that is not tied to an expected + response, this field is set to 0x0. + + + + Note: further on in this TLV there is also the field: + Sw_response_reference_ptr_ext. + + + +received_qos_data_tid_bitmap + + Whenever a frame is received that contains a QoS control + field (that includes QoS Data and/or QoS Null), the bit in + this field that corresponds to the received TID shall be + set. + + ...Bitmap[0] = TID0 + + ...Bitmap[1] = TID1 + + Etc. + + + +received_qos_data_tid_eosp_bitmap + + Field initialized to 0 + + For every QoS Data frame that is correctly received, the + EOSP bit of that frame is copied over into the corresponding + TID related field. + + Note that this implies that the bits here represent the + EOSP bit status for each TID of the last MPDU received for + that TID. + + + + received TID shall be set. + + ...eosp_bitmap[0] = eosp of TID0 + + ...eosp_bitmap[1] = eosp of TID1 + + Etc. + + + +qosctrl_15_8_tid0 + + Field only valid when Received_qos_data_tid_bitmap[0] is + set + + + + QoS control field bits 15-8 of the last properly + received MPDU with a QoS control field embedded, with TID + == 0 + +qosctrl_15_8_tid1 + + Field only valid when Received_qos_data_tid_bitmap[1] is + set + + + + QoS control field bits 15-8 of the last properly + received MPDU with a QoS control field embedded, with TID + == 1 + +qosctrl_15_8_tid2 + + Field only valid when Received_qos_data_tid_bitmap[2] is + set + + + + QoS control field bits 15-8 of the last properly + received MPDU with a QoS control field embedded, with TID + == 2 + +qosctrl_15_8_tid3 + + Field only valid when Received_qos_data_tid_bitmap[3] is + set + + + + QoS control field bits 15-8 of the last properly + received MPDU with a QoS control field embedded, with TID + == 3 + +qosctrl_15_8_tid4 + + Field only valid when Received_qos_data_tid_bitmap[4] is + set + + + + QoS control field bits 15-8 of the last properly + received MPDU with a QoS control field embedded, with TID + == 4 + +qosctrl_15_8_tid5 + + Field only valid when Received_qos_data_tid_bitmap[5] is + set + + + + QoS control field bits 15-8 of the last properly + received MPDU with a QoS control field embedded, with TID + == 5 + +qosctrl_15_8_tid6 + + Field only valid when Received_qos_data_tid_bitmap[6] is + set + + + + QoS control field bits 15-8 of the last properly + received MPDU with a QoS control field embedded, with TID + == 6 + +qosctrl_15_8_tid7 + + Field only valid when Received_qos_data_tid_bitmap[7] is + set + + + + QoS control field bits 15-8 of the last properly + received MPDU with a QoS control field embedded, with TID + == 7 + +qosctrl_15_8_tid8 + + Field only valid when Received_qos_data_tid_bitmap[8] is + set + + + + QoS control field bits 15-8 of the last properly + received MPDU with a QoS control field embedded, with TID + == 8 + +qosctrl_15_8_tid9 + + Field only valid when Received_qos_data_tid_bitmap[9] is + set + + + + QoS control field bits 15-8 of the last properly + received MPDU with a QoS control field embedded, with TID + == 9 + +qosctrl_15_8_tid10 + + Field only valid when Received_qos_data_tid_bitmap[10] + is set + + + + QoS control field bits 15-8 of the last properly + received MPDU with a QoS control field embedded, with TID + == 10 + +qosctrl_15_8_tid11 + + Field only valid when Received_qos_data_tid_bitmap[11] + is set + + + + QoS control field bits 15-8 of the last properly + received MPDU with a QoS control field embedded, with TID + == 11 + +qosctrl_15_8_tid12 + + Field only valid when Received_qos_data_tid_bitmap[12] + is set + + + + QoS control field bits 15-8 of the last properly + received MPDU with a QoS control field embedded, with TID + == 12 + +qosctrl_15_8_tid13 + + Field only valid when Received_qos_data_tid_bitmap[13] + is set + + + + QoS control field bits 15-8 of the last properly + received MPDU with a QoS control field embedded, with TID + == 13 + +qosctrl_15_8_tid14 + + Field only valid when Received_qos_data_tid_bitmap[14] + is set + + + + QoS control field bits 15-8 of the last properly + received MPDU with a QoS control field embedded, with TID + == 14 + +qosctrl_15_8_tid15 + + Field only valid when Received_qos_data_tid_bitmap[15] + is set + + + + QoS control field bits 15-8 of the last properly + received MPDU with a QoS control field embedded, with TID + == 15 + +mpdu_ok_byte_count + + The number of bytes received within an MPDU for this + user with correct FCS. This includes the FCS field + + + + NOTE: + + The sum of the four fields..... + + Mpdu_ok_byte_count + + + mpdu_err_byte_count + + + + .....is the total number of bytes that were received for + this user from the PHY. + + + + + +ampdu_delim_ok_count_6_0 + + Number of AMPDU delimiter received with correct + structure + + LSB 7 bits from this counter + + + + Note that this is a delimiter count and not byte count. + To get to the number of bytes occupied by these delimiters, + multiply this number by 4 + + + + + +ampdu_delim_err_count + + The number of MPDU delimiter errors counted for this + user. + + + + Note that this is a delimiter count and not byte count. + To get to the number of bytes occupied by these delimiters, + multiply this number by 4 + + + +ampdu_delim_ok_count_13_7 + + Number of AMPDU delimiters received with correct + structure + + Bits 13-7 from this counter + + + + Note that this is a delimiter count and not byte count. + To get to the number of bytes occupied by these delimiters, + multiply this number by 4 + + + +mpdu_err_byte_count + + The number of bytes belonging to MPDUs with an FCS + error. This includes the FCS field. + + + + + +ampdu_delim_ok_count_20_14 + + Number of AMPDU delimiters received with correct + structure + + Bits 20-14 from this counter + + + + Note that this is a delimiter count and not byte count. + To get to the number of bytes occupied by these delimiters, + multiply this number by 4 + + + + + +non_consecutive_delimiter_err + + The number of times an MPDU delimiter error is detected + that is not immediately preceded by another MPDU delimiter + also with FCS error. + + + + The counter saturates at 0xFFFF + + + + + +reserved_20a + + + +ht_control_null_field + + + + + Last successfully received + HT_CONTROL/VHT_CONTROL/HE_CONTROL field from QoS Null frame + for this user. + + + +sw_response_reference_ptr_ext + + Extended Pointer info that SW uses to refer back to an + expected response transmission. Used for Rate adaptation + purposes. + + When a reception occurs that is not tied to an expected + response, this field is set to 0x0. + + + + Note: earlier on in this TLV there is also the field: + Sw_response_reference_ptr. + + +*/ + + + /* EXTERNAL REFERENCE : struct rx_rxpcu_classification_overview rxpcu_classification_details */ + + +/* Description RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS + + When set, at least one Filter Pass MPDU has been + received. FCS might or might not have been passing. + + + + For MU UL, in TLVs RX_PPDU_END and + RX_PPDU_END_STATUS_DONE, this field is the OR of all the + users. + + +*/ +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x00000001 + +/* Description RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK + + When set, at least one Filter Pass MPDU has been + received that has a correct FCS. + + + + For MU UL, in TLVs RX_PPDU_END and + RX_PPDU_END_STATUS_DONE, this field is the OR of all the + users. + + + + +*/ +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 + +/* Description RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS + + When set, at least one Monitor Direct MPDU has been + received. FCS might or might not have been passing + + + + For MU UL, in TLVs RX_PPDU_END and + RX_PPDU_END_STATUS_DONE, this field is the OR of all the + users. + + +*/ +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x00000004 + +/* Description RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK + + When set, at least one Monitor Direct MPDU has been + received that has a correct FCS. + + + + For MU UL, in TLVs RX_PPDU_END and + RX_PPDU_END_STATUS_DONE, this field is the OR of all the + users. + + + + +*/ +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 + +/* Description RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS + + When set, at least one Monitor Direct MPDU has been + received. FCS might or might not have been passing. + + + + For MU UL, in TLVs RX_PPDU_END and + RX_PPDU_END_STATUS_DONE, this field is the OR of all the + users. + + +*/ +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x00000010 + +/* Description RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK + + When set, at least one Monitor Direct MPDU has been + received that has a correct FCS. + + + + For MU UL, in TLVs RX_PPDU_END and + RX_PPDU_END_STATUS_DONE, this field is the OR of all the + users. + + +*/ +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 + +/* Description RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED + + When set, PPDU reception was aborted by the PHY + + +*/ +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x00000040 + +/* Description RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0 + + +*/ +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 7 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x0000ff80 + +/* Description RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + +*/ +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 +#define RX_PPDU_END_USER_STATS_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0xffff0000 + +/* Description RX_PPDU_END_USER_STATS_1_STA_FULL_AID + + Consumer: FW + + Producer: RXPCU + + + + The full AID of this station. + + + + +*/ +#define RX_PPDU_END_USER_STATS_1_STA_FULL_AID_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_1_STA_FULL_AID_LSB 0 +#define RX_PPDU_END_USER_STATS_1_STA_FULL_AID_MASK 0x00001fff + +/* Description RX_PPDU_END_USER_STATS_1_MCS + + MCS of the received frame + + + + For details, refer to MCS_TYPE description + + Note: This is rate in case of 11a/11b + + + + +*/ +#define RX_PPDU_END_USER_STATS_1_MCS_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_1_MCS_LSB 13 +#define RX_PPDU_END_USER_STATS_1_MCS_MASK 0x0001e000 + +/* Description RX_PPDU_END_USER_STATS_1_NSS + + Number of spatial streams. + + + + NOTE: RXPCU derives this from the 'Mimo_ss_bitmap' + + + + Single spatial stream + + 2 spatial streams + + 3 spatial streams + + 4 spatial streams + + 5 spatial streams + + 6 spatial streams + + 7 spatial streams + + 8 spatial streams +*/ +#define RX_PPDU_END_USER_STATS_1_NSS_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_1_NSS_LSB 17 +#define RX_PPDU_END_USER_STATS_1_NSS_MASK 0x000e0000 + +/* Description RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID + + When set, ofdma RU related info in the following fields + is valid + + +*/ +#define RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_LSB 20 +#define RX_PPDU_END_USER_STATS_1_OFDMA_INFO_VALID_MASK 0x00100000 + +/* Description RX_PPDU_END_USER_STATS_1_DL_OFDMA_RU_START_INDEX + + Field only valid when Ofdma_info_valid is set + + + + RU index number to which User is assigned + + RU numbering is over the entire BW, starting from 0 + + +*/ +#define RX_PPDU_END_USER_STATS_1_DL_OFDMA_RU_START_INDEX_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_1_DL_OFDMA_RU_START_INDEX_LSB 21 +#define RX_PPDU_END_USER_STATS_1_DL_OFDMA_RU_START_INDEX_MASK 0x0fe00000 + +/* Description RX_PPDU_END_USER_STATS_1_RESERVED_1A + + +*/ +#define RX_PPDU_END_USER_STATS_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_1_RESERVED_1A_LSB 28 +#define RX_PPDU_END_USER_STATS_1_RESERVED_1A_MASK 0xf0000000 + +/* Description RX_PPDU_END_USER_STATS_2_DL_OFDMA_RU_WIDTH + + The size of the RU for this user. + + In units of 1 (26 tone) RU + + +*/ +#define RX_PPDU_END_USER_STATS_2_DL_OFDMA_RU_WIDTH_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_2_DL_OFDMA_RU_WIDTH_LSB 0 +#define RX_PPDU_END_USER_STATS_2_DL_OFDMA_RU_WIDTH_MASK 0x0000007f + +/* Description RX_PPDU_END_USER_STATS_2_RESERVED_2A + + +*/ +#define RX_PPDU_END_USER_STATS_2_RESERVED_2A_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_2_RESERVED_2A_LSB 7 +#define RX_PPDU_END_USER_STATS_2_RESERVED_2A_MASK 0x00000080 + +/* Description RX_PPDU_END_USER_STATS_2_USER_RECEIVE_QUALITY + + DO NOT USE + + + + Field not populated by MAC HW + + +*/ +#define RX_PPDU_END_USER_STATS_2_USER_RECEIVE_QUALITY_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_2_USER_RECEIVE_QUALITY_LSB 8 +#define RX_PPDU_END_USER_STATS_2_USER_RECEIVE_QUALITY_MASK 0x0000ff00 + +/* Description RX_PPDU_END_USER_STATS_2_MPDU_CNT_FCS_ERR + + The number of MPDUs received from this STA in this PPDU + with FCS errors + + +*/ +#define RX_PPDU_END_USER_STATS_2_MPDU_CNT_FCS_ERR_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_2_MPDU_CNT_FCS_ERR_LSB 16 +#define RX_PPDU_END_USER_STATS_2_MPDU_CNT_FCS_ERR_MASK 0x03ff0000 + +/* Description RX_PPDU_END_USER_STATS_2_WBM2RXDMA_BUF_SOURCE_USED + + Field filled in by RXDMA + + + + When set, RXDMA has used the wbm2rxdma_buf ring as + source for at least one of the frames in this PPDU. +*/ +#define RX_PPDU_END_USER_STATS_2_WBM2RXDMA_BUF_SOURCE_USED_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_2_WBM2RXDMA_BUF_SOURCE_USED_LSB 26 +#define RX_PPDU_END_USER_STATS_2_WBM2RXDMA_BUF_SOURCE_USED_MASK 0x04000000 + +/* Description RX_PPDU_END_USER_STATS_2_FW2RXDMA_BUF_SOURCE_USED + + Field filled in by RXDMA + + + + When set, RXDMA has used the fw2rxdma_buf ring as source + for at least one of the frames in this PPDU. +*/ +#define RX_PPDU_END_USER_STATS_2_FW2RXDMA_BUF_SOURCE_USED_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_2_FW2RXDMA_BUF_SOURCE_USED_LSB 27 +#define RX_PPDU_END_USER_STATS_2_FW2RXDMA_BUF_SOURCE_USED_MASK 0x08000000 + +/* Description RX_PPDU_END_USER_STATS_2_SW2RXDMA_BUF_SOURCE_USED + + Field filled in by RXDMA + + + + When set, RXDMA has used the sw2rxdma_buf ring as source + for at least one of the frames in this PPDU. +*/ +#define RX_PPDU_END_USER_STATS_2_SW2RXDMA_BUF_SOURCE_USED_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_2_SW2RXDMA_BUF_SOURCE_USED_LSB 28 +#define RX_PPDU_END_USER_STATS_2_SW2RXDMA_BUF_SOURCE_USED_MASK 0x10000000 + +/* Description RX_PPDU_END_USER_STATS_2_RESERVED_2B + + +*/ +#define RX_PPDU_END_USER_STATS_2_RESERVED_2B_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_2_RESERVED_2B_LSB 29 +#define RX_PPDU_END_USER_STATS_2_RESERVED_2B_MASK 0xe0000000 + +/* Description RX_PPDU_END_USER_STATS_3_MPDU_CNT_FCS_OK + + The number of MPDUs received from this STA in this PPDU + with correct FCS + + +*/ +#define RX_PPDU_END_USER_STATS_3_MPDU_CNT_FCS_OK_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_MPDU_CNT_FCS_OK_LSB 0 +#define RX_PPDU_END_USER_STATS_3_MPDU_CNT_FCS_OK_MASK 0x000001ff + +/* Description RX_PPDU_END_USER_STATS_3_FRAME_CONTROL_INFO_VALID + + When set, the frame_control_info field contains valid + information + + +*/ +#define RX_PPDU_END_USER_STATS_3_FRAME_CONTROL_INFO_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_FRAME_CONTROL_INFO_VALID_LSB 9 +#define RX_PPDU_END_USER_STATS_3_FRAME_CONTROL_INFO_VALID_MASK 0x00000200 + +/* Description RX_PPDU_END_USER_STATS_3_QOS_CONTROL_INFO_VALID + + When set, the QoS_control_info field contains valid + information + + +*/ +#define RX_PPDU_END_USER_STATS_3_QOS_CONTROL_INFO_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_QOS_CONTROL_INFO_VALID_LSB 10 +#define RX_PPDU_END_USER_STATS_3_QOS_CONTROL_INFO_VALID_MASK 0x00000400 + +/* Description RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_VALID + + When set, the HT_control_field contains valid + information + + +*/ +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_VALID_LSB 11 +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_VALID_MASK 0x00000800 + +/* Description RX_PPDU_END_USER_STATS_3_DATA_SEQUENCE_CONTROL_INFO_VALID + + When set, the First_data_seq_ctrl field contains valid + information + + +*/ +#define RX_PPDU_END_USER_STATS_3_DATA_SEQUENCE_CONTROL_INFO_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_DATA_SEQUENCE_CONTROL_INFO_VALID_LSB 12 +#define RX_PPDU_END_USER_STATS_3_DATA_SEQUENCE_CONTROL_INFO_VALID_MASK 0x00001000 + +/* Description RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_NULL_VALID + + When set, the HT_control_NULL_field contains valid + information + + +*/ +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_NULL_VALID_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_NULL_VALID_LSB 13 +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_INFO_NULL_VALID_MASK 0x00002000 + +/* Description RX_PPDU_END_USER_STATS_3_RESERVED_3A + + +*/ +#define RX_PPDU_END_USER_STATS_3_RESERVED_3A_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_RESERVED_3A_LSB 14 +#define RX_PPDU_END_USER_STATS_3_RESERVED_3A_MASK 0x0000c000 + +/* Description RX_PPDU_END_USER_STATS_3_RXDMA2REO_RING_USED + + Field filled in by RXDMA + + + + Set when at least one frame during this PPDU got pushed + to this ring by RXDMA +*/ +#define RX_PPDU_END_USER_STATS_3_RXDMA2REO_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_RXDMA2REO_RING_USED_LSB 16 +#define RX_PPDU_END_USER_STATS_3_RXDMA2REO_RING_USED_MASK 0x00010000 + +/* Description RX_PPDU_END_USER_STATS_3_RXDMA2FW_RING_USED + + Field filled in by RXDMA + + + + Set when at least one frame during this PPDU got pushed + to this ring by RXDMA +*/ +#define RX_PPDU_END_USER_STATS_3_RXDMA2FW_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_RXDMA2FW_RING_USED_LSB 17 +#define RX_PPDU_END_USER_STATS_3_RXDMA2FW_RING_USED_MASK 0x00020000 + +/* Description RX_PPDU_END_USER_STATS_3_RXDMA2SW_RING_USED + + Field filled in by RXDMA + + + + Set when at least one frame during this PPDU got pushed + to this ring by RXDMA +*/ +#define RX_PPDU_END_USER_STATS_3_RXDMA2SW_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_RXDMA2SW_RING_USED_LSB 18 +#define RX_PPDU_END_USER_STATS_3_RXDMA2SW_RING_USED_MASK 0x00040000 + +/* Description RX_PPDU_END_USER_STATS_3_RXDMA_RELEASE_RING_USED + + Field filled in by RXDMA + + + + Set when at least one frame during this PPDU got pushed + to this ring by RXDMA +*/ +#define RX_PPDU_END_USER_STATS_3_RXDMA_RELEASE_RING_USED_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_RXDMA_RELEASE_RING_USED_LSB 19 +#define RX_PPDU_END_USER_STATS_3_RXDMA_RELEASE_RING_USED_MASK 0x00080000 + +/* Description RX_PPDU_END_USER_STATS_3_HT_CONTROL_FIELD_PKT_TYPE + + Field only valid when HT_control_info_valid or + HT_control_info_NULL_valid is set. + + + + Indicates what the PHY receive type was for receiving + this frame. Can help determine if the HT_CONTROL field shall + be interpreted as HT/VHT or HE. + + + + NOTE: later on in the 11ax IEEE spec a bit within the HT + control field was introduced that explicitly indicated how + to interpret the HT control field.... As HT, VHT, or HE. + + + + 802.11a PPDU type + + 802.11b PPDU type + + 802.11n Mixed Mode PPDU type + + 802.11ac PPDU type + + 802.11ax PPDU type + + 802.11ba (WUR) PPDU type +*/ +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_FIELD_PKT_TYPE_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_FIELD_PKT_TYPE_LSB 20 +#define RX_PPDU_END_USER_STATS_3_HT_CONTROL_FIELD_PKT_TYPE_MASK 0x00f00000 + +/* Description RX_PPDU_END_USER_STATS_3_RESERVED_3B + + +*/ +#define RX_PPDU_END_USER_STATS_3_RESERVED_3B_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_3_RESERVED_3B_LSB 24 +#define RX_PPDU_END_USER_STATS_3_RESERVED_3B_MASK 0xff000000 + +/* Description RX_PPDU_END_USER_STATS_4_AST_INDEX + + This field indicates the index of the AST entry + corresponding to this MPDU. It is provided by the GSE module + instantiated in RXPCU. + + A value of 0xFFFF indicates an invalid AST index, + meaning that No AST entry was found or NO AST search was + performed + + +*/ +#define RX_PPDU_END_USER_STATS_4_AST_INDEX_OFFSET 0x00000010 +#define RX_PPDU_END_USER_STATS_4_AST_INDEX_LSB 0 +#define RX_PPDU_END_USER_STATS_4_AST_INDEX_MASK 0x0000ffff + +/* Description RX_PPDU_END_USER_STATS_4_FRAME_CONTROL_FIELD + + Field only valid when Frame_control_info_valid is set. + + + + Last successfully received Frame_control field of data + frame (excluding Data NULL/ QoS Null) for this user + + Mainly used to track the PM state of the transmitted + device + + + + NOTE: only data frame info is needed, as control and + management frames are already routed to the FW. + + +*/ +#define RX_PPDU_END_USER_STATS_4_FRAME_CONTROL_FIELD_OFFSET 0x00000010 +#define RX_PPDU_END_USER_STATS_4_FRAME_CONTROL_FIELD_LSB 16 +#define RX_PPDU_END_USER_STATS_4_FRAME_CONTROL_FIELD_MASK 0xffff0000 + +/* Description RX_PPDU_END_USER_STATS_5_FIRST_DATA_SEQ_CTRL + + Field only valid when Data_sequence_control_info_valid + is set. + + + + Sequence control field of the first data frame + (excluding Data NULL or QoS Data null) received for this + user with correct FCS + + + + NOTE: only data frame info is needed, as control and + management frames are already routed to the FW. + + +*/ +#define RX_PPDU_END_USER_STATS_5_FIRST_DATA_SEQ_CTRL_OFFSET 0x00000014 +#define RX_PPDU_END_USER_STATS_5_FIRST_DATA_SEQ_CTRL_LSB 0 +#define RX_PPDU_END_USER_STATS_5_FIRST_DATA_SEQ_CTRL_MASK 0x0000ffff + +/* Description RX_PPDU_END_USER_STATS_5_QOS_CONTROL_FIELD + + Field only valid when QoS_control_info_valid is set. + + + + Last successfully received QoS_control field of data + frame (excluding Data NULL/ QoS Null) for this user + + + + Note that in case of multi TID, this field can only + reflect the last properly received MPDU, and thus can not + indicate all potentially different TIDs that had been + received earlier. + + + + There are however per TID fields, that will contain + among other things all buffer status info: See + + QoSCtrl_15_8_tid??? + + +*/ +#define RX_PPDU_END_USER_STATS_5_QOS_CONTROL_FIELD_OFFSET 0x00000014 +#define RX_PPDU_END_USER_STATS_5_QOS_CONTROL_FIELD_LSB 16 +#define RX_PPDU_END_USER_STATS_5_QOS_CONTROL_FIELD_MASK 0xffff0000 + +/* Description RX_PPDU_END_USER_STATS_6_HT_CONTROL_FIELD + + Field only valid when HT_control_info_valid is set. + + + + Last successfully received + HT_CONTROL/VHT_CONTROL/HE_CONTROL field of data frames, + excluding QoS Null frames for this user. + + + + NOTE: HT control fields from QoS Null frames are + captured in field HT_control_NULL_field + + +*/ +#define RX_PPDU_END_USER_STATS_6_HT_CONTROL_FIELD_OFFSET 0x00000018 +#define RX_PPDU_END_USER_STATS_6_HT_CONTROL_FIELD_LSB 0 +#define RX_PPDU_END_USER_STATS_6_HT_CONTROL_FIELD_MASK 0xffffffff + +/* Description RX_PPDU_END_USER_STATS_7_FCS_OK_BITMAP_31_0 + + Bitmap indicates in order of received MPDUs, which MPDUs + had an passing FCS or had an error. + + 1: FCS OK + + 0: FCS error + + +*/ +#define RX_PPDU_END_USER_STATS_7_FCS_OK_BITMAP_31_0_OFFSET 0x0000001c +#define RX_PPDU_END_USER_STATS_7_FCS_OK_BITMAP_31_0_LSB 0 +#define RX_PPDU_END_USER_STATS_7_FCS_OK_BITMAP_31_0_MASK 0xffffffff + +/* Description RX_PPDU_END_USER_STATS_8_FCS_OK_BITMAP_63_32 + + Bitmap indicates in order of received MPDUs, which MPDUs + had an passing FCS or had an error. + + 1: FCS OK + + 0: FCS error + + + + NOTE: for users 0, 1, 2 and 3, additional bitmap info + (up to 256 bitmap window) is provided in + RX_PPDU_END_USER_STATS_EXT TLV + + +*/ +#define RX_PPDU_END_USER_STATS_8_FCS_OK_BITMAP_63_32_OFFSET 0x00000020 +#define RX_PPDU_END_USER_STATS_8_FCS_OK_BITMAP_63_32_LSB 0 +#define RX_PPDU_END_USER_STATS_8_FCS_OK_BITMAP_63_32_MASK 0xffffffff + +/* Description RX_PPDU_END_USER_STATS_9_UDP_MSDU_COUNT + + Field filled in by RX OLE + + Set to 0 by RXPCU + + + + The number of MSDUs that are part of MPDUs without FCS + error, that contain UDP frames. + + +*/ +#define RX_PPDU_END_USER_STATS_9_UDP_MSDU_COUNT_OFFSET 0x00000024 +#define RX_PPDU_END_USER_STATS_9_UDP_MSDU_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_9_UDP_MSDU_COUNT_MASK 0x0000ffff + +/* Description RX_PPDU_END_USER_STATS_9_TCP_MSDU_COUNT + + Field filled in by RX OLE + + Set to 0 by RXPCU + + + + The number of MSDUs that are part of MPDUs without FCS + error, that contain TCP frames. + + + + (Note: This does NOT include TCP-ACK) + + +*/ +#define RX_PPDU_END_USER_STATS_9_TCP_MSDU_COUNT_OFFSET 0x00000024 +#define RX_PPDU_END_USER_STATS_9_TCP_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_9_TCP_MSDU_COUNT_MASK 0xffff0000 + +/* Description RX_PPDU_END_USER_STATS_10_OTHER_MSDU_COUNT + + Field filled in by RX OLE + + Set to 0 by RXPCU + + + + The number of MSDUs that are part of MPDUs without FCS + error, that contain neither UDP or TCP frames. + + + + Includes Management and control frames. + + + + +*/ +#define RX_PPDU_END_USER_STATS_10_OTHER_MSDU_COUNT_OFFSET 0x00000028 +#define RX_PPDU_END_USER_STATS_10_OTHER_MSDU_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_10_OTHER_MSDU_COUNT_MASK 0x0000ffff + +/* Description RX_PPDU_END_USER_STATS_10_TCP_ACK_MSDU_COUNT + + Field filled in by RX OLE + + Set to 0 by RXPCU + + + + The number of MSDUs that are part of MPDUs without FCS + error, that contain TCP ack frames. + + +*/ +#define RX_PPDU_END_USER_STATS_10_TCP_ACK_MSDU_COUNT_OFFSET 0x00000028 +#define RX_PPDU_END_USER_STATS_10_TCP_ACK_MSDU_COUNT_LSB 16 +#define RX_PPDU_END_USER_STATS_10_TCP_ACK_MSDU_COUNT_MASK 0xffff0000 + +/* Description RX_PPDU_END_USER_STATS_11_SW_RESPONSE_REFERENCE_PTR + + Pointer that SW uses to refer back to an expected + response reception. Used for Rate adaptation purposes. + + When a reception occurs that is not tied to an expected + response, this field is set to 0x0. + + + + Note: further on in this TLV there is also the field: + Sw_response_reference_ptr_ext. + + +*/ +#define RX_PPDU_END_USER_STATS_11_SW_RESPONSE_REFERENCE_PTR_OFFSET 0x0000002c +#define RX_PPDU_END_USER_STATS_11_SW_RESPONSE_REFERENCE_PTR_LSB 0 +#define RX_PPDU_END_USER_STATS_11_SW_RESPONSE_REFERENCE_PTR_MASK 0xffffffff + +/* Description RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_BITMAP + + Whenever a frame is received that contains a QoS control + field (that includes QoS Data and/or QoS Null), the bit in + this field that corresponds to the received TID shall be + set. + + ...Bitmap[0] = TID0 + + ...Bitmap[1] = TID1 + + Etc. + + +*/ +#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_BITMAP_OFFSET 0x00000030 +#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_BITMAP_LSB 0 +#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_BITMAP_MASK 0x0000ffff + +/* Description RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_EOSP_BITMAP + + Field initialized to 0 + + For every QoS Data frame that is correctly received, the + EOSP bit of that frame is copied over into the corresponding + TID related field. + + Note that this implies that the bits here represent the + EOSP bit status for each TID of the last MPDU received for + that TID. + + + + received TID shall be set. + + ...eosp_bitmap[0] = eosp of TID0 + + ...eosp_bitmap[1] = eosp of TID1 + + Etc. + + +*/ +#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_OFFSET 0x00000030 +#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_LSB 16 +#define RX_PPDU_END_USER_STATS_12_RECEIVED_QOS_DATA_TID_EOSP_BITMAP_MASK 0xffff0000 + +/* Description RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID0 + + Field only valid when Received_qos_data_tid_bitmap[0] is + set + + + + QoS control field bits 15-8 of the last properly + received MPDU with a QoS control field embedded, with TID + == 0 +*/ +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID0_OFFSET 0x00000034 +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID0_LSB 0 +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID0_MASK 0x000000ff + +/* Description RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID1 + + Field only valid when Received_qos_data_tid_bitmap[1] is + set + + + + QoS control field bits 15-8 of the last properly + received MPDU with a QoS control field embedded, with TID + == 1 +*/ +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID1_OFFSET 0x00000034 +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID1_LSB 8 +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID1_MASK 0x0000ff00 + +/* Description RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID2 + + Field only valid when Received_qos_data_tid_bitmap[2] is + set + + + + QoS control field bits 15-8 of the last properly + received MPDU with a QoS control field embedded, with TID + == 2 +*/ +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID2_OFFSET 0x00000034 +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID2_LSB 16 +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID2_MASK 0x00ff0000 + +/* Description RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID3 + + Field only valid when Received_qos_data_tid_bitmap[3] is + set + + + + QoS control field bits 15-8 of the last properly + received MPDU with a QoS control field embedded, with TID + == 3 +*/ +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID3_OFFSET 0x00000034 +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID3_LSB 24 +#define RX_PPDU_END_USER_STATS_13_QOSCTRL_15_8_TID3_MASK 0xff000000 + +/* Description RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID4 + + Field only valid when Received_qos_data_tid_bitmap[4] is + set + + + + QoS control field bits 15-8 of the last properly + received MPDU with a QoS control field embedded, with TID + == 4 +*/ +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID4_OFFSET 0x00000038 +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID4_LSB 0 +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID4_MASK 0x000000ff + +/* Description RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID5 + + Field only valid when Received_qos_data_tid_bitmap[5] is + set + + + + QoS control field bits 15-8 of the last properly + received MPDU with a QoS control field embedded, with TID + == 5 +*/ +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID5_OFFSET 0x00000038 +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID5_LSB 8 +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID5_MASK 0x0000ff00 + +/* Description RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID6 + + Field only valid when Received_qos_data_tid_bitmap[6] is + set + + + + QoS control field bits 15-8 of the last properly + received MPDU with a QoS control field embedded, with TID + == 6 +*/ +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID6_OFFSET 0x00000038 +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID6_LSB 16 +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID6_MASK 0x00ff0000 + +/* Description RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID7 + + Field only valid when Received_qos_data_tid_bitmap[7] is + set + + + + QoS control field bits 15-8 of the last properly + received MPDU with a QoS control field embedded, with TID + == 7 +*/ +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID7_OFFSET 0x00000038 +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID7_LSB 24 +#define RX_PPDU_END_USER_STATS_14_QOSCTRL_15_8_TID7_MASK 0xff000000 + +/* Description RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID8 + + Field only valid when Received_qos_data_tid_bitmap[8] is + set + + + + QoS control field bits 15-8 of the last properly + received MPDU with a QoS control field embedded, with TID + == 8 +*/ +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID8_OFFSET 0x0000003c +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID8_LSB 0 +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID8_MASK 0x000000ff + +/* Description RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID9 + + Field only valid when Received_qos_data_tid_bitmap[9] is + set + + + + QoS control field bits 15-8 of the last properly + received MPDU with a QoS control field embedded, with TID + == 9 +*/ +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID9_OFFSET 0x0000003c +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID9_LSB 8 +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID9_MASK 0x0000ff00 + +/* Description RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID10 + + Field only valid when Received_qos_data_tid_bitmap[10] + is set + + + + QoS control field bits 15-8 of the last properly + received MPDU with a QoS control field embedded, with TID + == 10 +*/ +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID10_OFFSET 0x0000003c +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID10_LSB 16 +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID10_MASK 0x00ff0000 + +/* Description RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID11 + + Field only valid when Received_qos_data_tid_bitmap[11] + is set + + + + QoS control field bits 15-8 of the last properly + received MPDU with a QoS control field embedded, with TID + == 11 +*/ +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID11_OFFSET 0x0000003c +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID11_LSB 24 +#define RX_PPDU_END_USER_STATS_15_QOSCTRL_15_8_TID11_MASK 0xff000000 + +/* Description RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID12 + + Field only valid when Received_qos_data_tid_bitmap[12] + is set + + + + QoS control field bits 15-8 of the last properly + received MPDU with a QoS control field embedded, with TID + == 12 +*/ +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID12_OFFSET 0x00000040 +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID12_LSB 0 +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID12_MASK 0x000000ff + +/* Description RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID13 + + Field only valid when Received_qos_data_tid_bitmap[13] + is set + + + + QoS control field bits 15-8 of the last properly + received MPDU with a QoS control field embedded, with TID + == 13 +*/ +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID13_OFFSET 0x00000040 +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID13_LSB 8 +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID13_MASK 0x0000ff00 + +/* Description RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID14 + + Field only valid when Received_qos_data_tid_bitmap[14] + is set + + + + QoS control field bits 15-8 of the last properly + received MPDU with a QoS control field embedded, with TID + == 14 +*/ +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID14_OFFSET 0x00000040 +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID14_LSB 16 +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID14_MASK 0x00ff0000 + +/* Description RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID15 + + Field only valid when Received_qos_data_tid_bitmap[15] + is set + + + + QoS control field bits 15-8 of the last properly + received MPDU with a QoS control field embedded, with TID + == 15 +*/ +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID15_OFFSET 0x00000040 +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID15_LSB 24 +#define RX_PPDU_END_USER_STATS_16_QOSCTRL_15_8_TID15_MASK 0xff000000 + +/* Description RX_PPDU_END_USER_STATS_17_MPDU_OK_BYTE_COUNT + + The number of bytes received within an MPDU for this + user with correct FCS. This includes the FCS field + + + + NOTE: + + The sum of the four fields..... + + Mpdu_ok_byte_count + + + mpdu_err_byte_count + + + + .....is the total number of bytes that were received for + this user from the PHY. + + + + +*/ +#define RX_PPDU_END_USER_STATS_17_MPDU_OK_BYTE_COUNT_OFFSET 0x00000044 +#define RX_PPDU_END_USER_STATS_17_MPDU_OK_BYTE_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_17_MPDU_OK_BYTE_COUNT_MASK 0x01ffffff + +/* Description RX_PPDU_END_USER_STATS_17_AMPDU_DELIM_OK_COUNT_6_0 + + Number of AMPDU delimiter received with correct + structure + + LSB 7 bits from this counter + + + + Note that this is a delimiter count and not byte count. + To get to the number of bytes occupied by these delimiters, + multiply this number by 4 + + + + +*/ +#define RX_PPDU_END_USER_STATS_17_AMPDU_DELIM_OK_COUNT_6_0_OFFSET 0x00000044 +#define RX_PPDU_END_USER_STATS_17_AMPDU_DELIM_OK_COUNT_6_0_LSB 25 +#define RX_PPDU_END_USER_STATS_17_AMPDU_DELIM_OK_COUNT_6_0_MASK 0xfe000000 + +/* Description RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_ERR_COUNT + + The number of MPDU delimiter errors counted for this + user. + + + + Note that this is a delimiter count and not byte count. + To get to the number of bytes occupied by these delimiters, + multiply this number by 4 + + +*/ +#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_ERR_COUNT_OFFSET 0x00000048 +#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_ERR_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_ERR_COUNT_MASK 0x01ffffff + +/* Description RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_OK_COUNT_13_7 + + Number of AMPDU delimiters received with correct + structure + + Bits 13-7 from this counter + + + + Note that this is a delimiter count and not byte count. + To get to the number of bytes occupied by these delimiters, + multiply this number by 4 + + +*/ +#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_OK_COUNT_13_7_OFFSET 0x00000048 +#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_OK_COUNT_13_7_LSB 25 +#define RX_PPDU_END_USER_STATS_18_AMPDU_DELIM_OK_COUNT_13_7_MASK 0xfe000000 + +/* Description RX_PPDU_END_USER_STATS_19_MPDU_ERR_BYTE_COUNT + + The number of bytes belonging to MPDUs with an FCS + error. This includes the FCS field. + + + + +*/ +#define RX_PPDU_END_USER_STATS_19_MPDU_ERR_BYTE_COUNT_OFFSET 0x0000004c +#define RX_PPDU_END_USER_STATS_19_MPDU_ERR_BYTE_COUNT_LSB 0 +#define RX_PPDU_END_USER_STATS_19_MPDU_ERR_BYTE_COUNT_MASK 0x01ffffff + +/* Description RX_PPDU_END_USER_STATS_19_AMPDU_DELIM_OK_COUNT_20_14 + + Number of AMPDU delimiters received with correct + structure + + Bits 20-14 from this counter + + + + Note that this is a delimiter count and not byte count. + To get to the number of bytes occupied by these delimiters, + multiply this number by 4 + + + + +*/ +#define RX_PPDU_END_USER_STATS_19_AMPDU_DELIM_OK_COUNT_20_14_OFFSET 0x0000004c +#define RX_PPDU_END_USER_STATS_19_AMPDU_DELIM_OK_COUNT_20_14_LSB 25 +#define RX_PPDU_END_USER_STATS_19_AMPDU_DELIM_OK_COUNT_20_14_MASK 0xfe000000 + +/* Description RX_PPDU_END_USER_STATS_20_NON_CONSECUTIVE_DELIMITER_ERR + + The number of times an MPDU delimiter error is detected + that is not immediately preceded by another MPDU delimiter + also with FCS error. + + + + The counter saturates at 0xFFFF + + + + +*/ +#define RX_PPDU_END_USER_STATS_20_NON_CONSECUTIVE_DELIMITER_ERR_OFFSET 0x00000050 +#define RX_PPDU_END_USER_STATS_20_NON_CONSECUTIVE_DELIMITER_ERR_LSB 0 +#define RX_PPDU_END_USER_STATS_20_NON_CONSECUTIVE_DELIMITER_ERR_MASK 0x0000ffff + +/* Description RX_PPDU_END_USER_STATS_20_RESERVED_20A + + +*/ +#define RX_PPDU_END_USER_STATS_20_RESERVED_20A_OFFSET 0x00000050 +#define RX_PPDU_END_USER_STATS_20_RESERVED_20A_LSB 16 +#define RX_PPDU_END_USER_STATS_20_RESERVED_20A_MASK 0xffff0000 + +/* Description RX_PPDU_END_USER_STATS_21_HT_CONTROL_NULL_FIELD + + + + + Last successfully received + HT_CONTROL/VHT_CONTROL/HE_CONTROL field from QoS Null frame + for this user. + + +*/ +#define RX_PPDU_END_USER_STATS_21_HT_CONTROL_NULL_FIELD_OFFSET 0x00000054 +#define RX_PPDU_END_USER_STATS_21_HT_CONTROL_NULL_FIELD_LSB 0 +#define RX_PPDU_END_USER_STATS_21_HT_CONTROL_NULL_FIELD_MASK 0xffffffff + +/* Description RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT + + Extended Pointer info that SW uses to refer back to an + expected response transmission. Used for Rate adaptation + purposes. + + When a reception occurs that is not tied to an expected + response, this field is set to 0x0. + + + + Note: earlier on in this TLV there is also the field: + Sw_response_reference_ptr. + + +*/ +#define RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET 0x00000058 +#define RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_LSB 0 +#define RX_PPDU_END_USER_STATS_22_SW_RESPONSE_REFERENCE_PTR_EXT_MASK 0xffffffff + + +#endif // _RX_PPDU_END_USER_STATS_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/rx_ppdu_end_user_stats_ext.h b/drivers/staging/fw-api/hw/qca6750/v1/rx_ppdu_end_user_stats_ext.h new file mode 100644 index 000000000000..ea2e4545c532 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/rx_ppdu_end_user_stats_ext.h @@ -0,0 +1,360 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_PPDU_END_USER_STATS_EXT_H_ +#define _RX_PPDU_END_USER_STATS_EXT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_rxpcu_classification_overview.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 struct rx_rxpcu_classification_overview rxpcu_classification_details; +// 1 fcs_ok_bitmap_95_64[31:0] +// 2 fcs_ok_bitmap_127_96[31:0] +// 3 fcs_ok_bitmap_159_128[31:0] +// 4 fcs_ok_bitmap_191_160[31:0] +// 5 fcs_ok_bitmap_223_192[31:0] +// 6 fcs_ok_bitmap_255_224[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_PPDU_END_USER_STATS_EXT 7 + +struct rx_ppdu_end_user_stats_ext { + struct rx_rxpcu_classification_overview rxpcu_classification_details; + uint32_t fcs_ok_bitmap_95_64 : 32; //[31:0] + uint32_t fcs_ok_bitmap_127_96 : 32; //[31:0] + uint32_t fcs_ok_bitmap_159_128 : 32; //[31:0] + uint32_t fcs_ok_bitmap_191_160 : 32; //[31:0] + uint32_t fcs_ok_bitmap_223_192 : 32; //[31:0] + uint32_t fcs_ok_bitmap_255_224 : 32; //[31:0] +}; + +/* + +struct rx_rxpcu_classification_overview rxpcu_classification_details + + Details related to what RXPCU classification types of + MPDUs have been received + +fcs_ok_bitmap_95_64 + + Bitmap indicates in order of received MPDUs, which MPDUs + had an passing FCS or had an error. + + 1: FCS OK + + 0: FCS error + + + +fcs_ok_bitmap_127_96 + + Bitmap indicates in order of received MPDUs, which MPDUs + had an passing FCS or had an error. + + 1: FCS OK + + 0: FCS error + + + +fcs_ok_bitmap_159_128 + + Bitmap indicates in order of received MPDUs, which MPDUs + had an passing FCS or had an error. + + 1: FCS OK + + 0: FCS error + + + +fcs_ok_bitmap_191_160 + + Bitmap indicates in order of received MPDUs, which MPDUs + had an passing FCS or had an error. + + 1: FCS OK + + 0: FCS error + + + +fcs_ok_bitmap_223_192 + + Bitmap indicates in order of received MPDUs, which MPDUs + had an passing FCS or had an error. + + 1: FCS OK + + 0: FCS error + + + +fcs_ok_bitmap_255_224 + + Bitmap indicates in order of received MPDUs, which MPDUs + had an passing FCS or had an error. + + 1: FCS OK + + 0: FCS error + + +*/ + + + /* EXTERNAL REFERENCE : struct rx_rxpcu_classification_overview rxpcu_classification_details */ + + +/* Description RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS + + When set, at least one Filter Pass MPDU has been + received. FCS might or might not have been passing. + + + + For MU UL, in TLVs RX_PPDU_END and + RX_PPDU_END_STATUS_DONE, this field is the OR of all the + users. + + +*/ +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_MASK 0x00000001 + +/* Description RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK + + When set, at least one Filter Pass MPDU has been + received that has a correct FCS. + + + + For MU UL, in TLVs RX_PPDU_END and + RX_PPDU_END_STATUS_DONE, this field is the OR of all the + users. + + + + +*/ +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_LSB 1 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 + +/* Description RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS + + When set, at least one Monitor Direct MPDU has been + received. FCS might or might not have been passing + + + + For MU UL, in TLVs RX_PPDU_END and + RX_PPDU_END_STATUS_DONE, this field is the OR of all the + users. + + +*/ +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_LSB 2 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_MASK 0x00000004 + +/* Description RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK + + When set, at least one Monitor Direct MPDU has been + received that has a correct FCS. + + + + For MU UL, in TLVs RX_PPDU_END and + RX_PPDU_END_STATUS_DONE, this field is the OR of all the + users. + + + + +*/ +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 + +/* Description RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS + + When set, at least one Monitor Direct MPDU has been + received. FCS might or might not have been passing. + + + + For MU UL, in TLVs RX_PPDU_END and + RX_PPDU_END_STATUS_DONE, this field is the OR of all the + users. + + +*/ +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_LSB 4 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_MASK 0x00000010 + +/* Description RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK + + When set, at least one Monitor Direct MPDU has been + received that has a correct FCS. + + + + For MU UL, in TLVs RX_PPDU_END and + RX_PPDU_END_STATUS_DONE, this field is the OR of all the + users. + + +*/ +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 + +/* Description RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED + + When set, PPDU reception was aborted by the PHY + + +*/ +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_LSB 6 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHYRX_ABORT_RECEIVED_MASK 0x00000040 + +/* Description RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0 + + +*/ +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_LSB 7 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_RESERVED_0_MASK 0x0000ff80 + +/* Description RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + +*/ +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_LSB 16 +#define RX_PPDU_END_USER_STATS_EXT_0_RXPCU_CLASSIFICATION_DETAILS_PHY_PPDU_ID_MASK 0xffff0000 + +/* Description RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64 + + Bitmap indicates in order of received MPDUs, which MPDUs + had an passing FCS or had an error. + + 1: FCS OK + + 0: FCS error + + +*/ +#define RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64_OFFSET 0x00000004 +#define RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_1_FCS_OK_BITMAP_95_64_MASK 0xffffffff + +/* Description RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96 + + Bitmap indicates in order of received MPDUs, which MPDUs + had an passing FCS or had an error. + + 1: FCS OK + + 0: FCS error + + +*/ +#define RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96_OFFSET 0x00000008 +#define RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_2_FCS_OK_BITMAP_127_96_MASK 0xffffffff + +/* Description RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128 + + Bitmap indicates in order of received MPDUs, which MPDUs + had an passing FCS or had an error. + + 1: FCS OK + + 0: FCS error + + +*/ +#define RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128_OFFSET 0x0000000c +#define RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_3_FCS_OK_BITMAP_159_128_MASK 0xffffffff + +/* Description RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160 + + Bitmap indicates in order of received MPDUs, which MPDUs + had an passing FCS or had an error. + + 1: FCS OK + + 0: FCS error + + +*/ +#define RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160_OFFSET 0x00000010 +#define RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_4_FCS_OK_BITMAP_191_160_MASK 0xffffffff + +/* Description RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192 + + Bitmap indicates in order of received MPDUs, which MPDUs + had an passing FCS or had an error. + + 1: FCS OK + + 0: FCS error + + +*/ +#define RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192_OFFSET 0x00000014 +#define RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_5_FCS_OK_BITMAP_223_192_MASK 0xffffffff + +/* Description RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224 + + Bitmap indicates in order of received MPDUs, which MPDUs + had an passing FCS or had an error. + + 1: FCS OK + + 0: FCS error + + +*/ +#define RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224_OFFSET 0x00000018 +#define RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224_LSB 0 +#define RX_PPDU_END_USER_STATS_EXT_6_FCS_OK_BITMAP_255_224_MASK 0xffffffff + + +#endif // _RX_PPDU_END_USER_STATS_EXT_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/rx_ppdu_start.h b/drivers/staging/fw-api/hw/qca6750/v1/rx_ppdu_start.h new file mode 100644 index 000000000000..9a834e686a6a --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/rx_ppdu_start.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_PPDU_START_H_ +#define _RX_PPDU_START_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 phy_ppdu_id[15:0], reserved_15[31:16] +// 1 sw_phy_meta_data[31:0] +// 2 ppdu_start_timestamp[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_PPDU_START 3 + +struct rx_ppdu_start { + uint32_t phy_ppdu_id : 16, //[15:0] + reserved_15 : 16; //[31:16] + uint32_t sw_phy_meta_data : 32; //[31:0] + uint32_t ppdu_start_timestamp : 32; //[31:0] +}; + +/* + +phy_ppdu_id + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + + +reserved_15 + + Reserved + + + +sw_phy_meta_data + + SW programmed Meta data provided by the PHY. + + + + Can be used for SW to indicate the channel the device is + on. + +ppdu_start_timestamp + + Timestamp that indicates when the PPDU that contained + this MPDU started on the medium. + + + + The timestamp is captured by the PHY and given to the + MAC in PHYRX_RSSI_LEGACY.ppdu_start_timestamp + + +*/ + + +/* Description RX_PPDU_START_0_PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + +*/ +#define RX_PPDU_START_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_PPDU_START_0_PHY_PPDU_ID_LSB 0 +#define RX_PPDU_START_0_PHY_PPDU_ID_MASK 0x0000ffff + +/* Description RX_PPDU_START_0_RESERVED_15 + + Reserved + + +*/ +#define RX_PPDU_START_0_RESERVED_15_OFFSET 0x00000000 +#define RX_PPDU_START_0_RESERVED_15_LSB 16 +#define RX_PPDU_START_0_RESERVED_15_MASK 0xffff0000 + +/* Description RX_PPDU_START_1_SW_PHY_META_DATA + + SW programmed Meta data provided by the PHY. + + + + Can be used for SW to indicate the channel the device is + on. +*/ +#define RX_PPDU_START_1_SW_PHY_META_DATA_OFFSET 0x00000004 +#define RX_PPDU_START_1_SW_PHY_META_DATA_LSB 0 +#define RX_PPDU_START_1_SW_PHY_META_DATA_MASK 0xffffffff + +/* Description RX_PPDU_START_2_PPDU_START_TIMESTAMP + + Timestamp that indicates when the PPDU that contained + this MPDU started on the medium. + + + + The timestamp is captured by the PHY and given to the + MAC in PHYRX_RSSI_LEGACY.ppdu_start_timestamp + + +*/ +#define RX_PPDU_START_2_PPDU_START_TIMESTAMP_OFFSET 0x00000008 +#define RX_PPDU_START_2_PPDU_START_TIMESTAMP_LSB 0 +#define RX_PPDU_START_2_PPDU_START_TIMESTAMP_MASK 0xffffffff + + +#endif // _RX_PPDU_START_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/rx_ppdu_start_user_info.h b/drivers/staging/fw-api/hw/qca6750/v1/rx_ppdu_start_user_info.h new file mode 100644 index 000000000000..ca392ed776b2 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/rx_ppdu_start_user_info.h @@ -0,0 +1,333 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_PPDU_START_USER_INFO_H_ +#define _RX_PPDU_START_USER_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "receive_user_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-2 struct receive_user_info receive_user_info_details; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_PPDU_START_USER_INFO 3 + +struct rx_ppdu_start_user_info { + struct receive_user_info receive_user_info_details; +}; + +/* + +struct receive_user_info receive_user_info_details + + Overview of receive parameters that the MAC needs to + prepend to every received MSDU/MPDU. +*/ + + + /* EXTERNAL REFERENCE : struct receive_user_info receive_user_info_details */ + + +/* Description RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + +*/ +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_LSB 0 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff + +/* Description RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI + + RSSI for this user + + Frequency domain RSSI measurement for this user. Based + on the channel estimate. + + + + +*/ +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_LSB 16 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_USER_RSSI_MASK 0x00ff0000 + +/* Description RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE + + Packet type: + + + + 802.11a PPDU type + + 802.11b PPDU type + + 802.11n Mixed Mode PPDU type + + 802.11ac PPDU type + + 802.11ax PPDU type + + 802.11ba (WUR) PPDU type +*/ +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_LSB 24 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_PKT_TYPE_MASK 0x0f000000 + +/* Description RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC + + When set, use STBC transmission rates +*/ +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_LSB 28 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_STBC_MASK 0x10000000 + +/* Description RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE + + Indicates what type of reception this is. + + Basic SU reception (not + part of OFDMA or MU-MIMO) + + This is related to + DL type of reception + + This is related + to DL type of reception + + This is + related to DL type of reception + + This is related + to UL type of reception + + This is + related to UL type of reception + + This is + related to UL type of reception + + + + +*/ +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_OFFSET 0x00000000 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_LSB 29 +#define RX_PPDU_START_USER_INFO_0_RECEIVE_USER_INFO_DETAILS_RECEPTION_TYPE_MASK 0xe0000000 + +/* Description RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS + + For details, refer to MCS_TYPE description + + +*/ +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_LSB 0 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RATE_MCS_MASK 0x0000000f + +/* Description RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI + + Field only valid when pkt type is HT, VHT or HE. + + + + Legacy normal GI. Can also be + used for HE + + Legacy short GI. Can also be + used for HE + + HE related GI + + HE related GI + + +*/ +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_LSB 4 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_SGI_MASK 0x00000030 + +/* Description RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH + + Full receive Bandwidth + + + + + + + + + + + + + + +*/ +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_LSB 6 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_RECEIVE_BANDWIDTH_MASK 0x000000c0 + +/* Description RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP + + Bitmap, with each bit indicating if the related spatial + stream is used for this STA + + LSB related to SS 0 + + + + 0: spatial stream not used for this reception + + 1: spatial stream used for this reception + + + + +*/ +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_LSB 8 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_MIMO_SS_BITMAP_MASK 0x0000ff00 + +/* Description RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION + + Field only valid in case of OFDMA type receptions (DL + and UL) + + + + Indicates the RU number associated with this user. + + + + In case of reception where the transmission was DL MU + OFDMA, this field provides the RU pattern. Note that fields + ofdma_user_index and ofdma_content_channel are needed to + determine which RU (within a 40 MHz channel) was actually + assigned to this user, but this does not give info on which + 40 MHz channel was assigned to this user. Please refer + DL_ofdma_ru_* in PHYRX_PKT_END_INFO for complete RU info for + this user. + + + + In case of reception where the transmission was UL MU + OFDMA, PHY is recommended to insert the RU start index in + this field. Note that PHY may insert the RU width in + Reserved_2a[6:0]. + + +*/ +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_LSB 16 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_RU_ALLOCATION_MASK 0x00ff0000 + +/* Description RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX + + Field only valid in the of DL MU OFDMA reception + + + + The user number within the RU_allocation. + + + + This is needed for SW to determine the exact RU position + within the reception. + + +*/ +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_LSB 24 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_USER_INDEX_MASK 0x7f000000 + +/* Description RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL + + Field only valid in the of DL MU OFDMA/MIMO reception + + + + In case of DL MU reception, this field indicates the + content channel number where PHY found the RU information + for this user + + + + This is needed for SW to determine the exact RU position + within the reception. + + + + + + + + + + +*/ +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_OFFSET 0x00000004 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_LSB 31 +#define RX_PPDU_START_USER_INFO_1_RECEIVE_USER_INFO_DETAILS_OFDMA_CONTENT_CHANNEL_MASK 0x80000000 + +/* Description RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC + + When set, use LDPC transmission rates were used. + + +*/ +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_LSB 0 +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_LDPC_MASK 0x00000001 + +/* Description RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH + + In case of UL OFDMA reception, PHY is recommended to + insert the RU width + + In Hastings80: was using Reserved_2a[6:0]. + + +*/ +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_LSB 1 +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RU_WIDTH_MASK 0x000000fe + +/* Description RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A + + +*/ +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_OFFSET 0x00000008 +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_LSB 8 +#define RX_PPDU_START_USER_INFO_2_RECEIVE_USER_INFO_DETAILS_RESERVED_2A_MASK 0xffffff00 + + +#endif // _RX_PPDU_START_USER_INFO_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/rx_reo_queue.h b/drivers/staging/fw-api/hw/qca6750/v1/rx_reo_queue.h new file mode 100644 index 000000000000..986c1a86f1f4 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/rx_reo_queue.h @@ -0,0 +1,1756 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_REO_QUEUE_H_ +#define _RX_REO_QUEUE_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_descriptor_header.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 struct uniform_descriptor_header descriptor_header; +// 1 receive_queue_number[15:0], reserved_1b[31:16] +// 2 vld[0], associated_link_descriptor_counter[2:1], disable_duplicate_detection[3], soft_reorder_enable[4], ac[6:5], bar[7], rty[8], chk_2k_mode[9], oor_mode[10], ba_window_size[18:11], pn_check_needed[19], pn_shall_be_even[20], pn_shall_be_uneven[21], pn_handling_enable[22], pn_size[24:23], ignore_ampdu_flag[25], reserved_2b[31:26] +// 3 svld[0], ssn[12:1], current_index[20:13], seq_2k_error_detected_flag[21], pn_error_detected_flag[22], reserved_3a[30:23], pn_valid[31] +// 4 pn_31_0[31:0] +// 5 pn_63_32[31:0] +// 6 pn_95_64[31:0] +// 7 pn_127_96[31:0] +// 8 last_rx_enqueue_timestamp[31:0] +// 9 last_rx_dequeue_timestamp[31:0] +// 10 ptr_to_next_aging_queue_31_0[31:0] +// 11 ptr_to_next_aging_queue_39_32[7:0], reserved_11a[31:8] +// 12 ptr_to_previous_aging_queue_31_0[31:0] +// 13 ptr_to_previous_aging_queue_39_32[7:0], reserved_13a[31:8] +// 14 rx_bitmap_31_0[31:0] +// 15 rx_bitmap_63_32[31:0] +// 16 rx_bitmap_95_64[31:0] +// 17 rx_bitmap_127_96[31:0] +// 18 rx_bitmap_159_128[31:0] +// 19 rx_bitmap_191_160[31:0] +// 20 rx_bitmap_223_192[31:0] +// 21 rx_bitmap_255_224[31:0] +// 22 current_mpdu_count[6:0], current_msdu_count[31:7] +// 23 reserved_23[3:0], timeout_count[9:4], forward_due_to_bar_count[15:10], duplicate_count[31:16] +// 24 frames_in_order_count[23:0], bar_received_count[31:24] +// 25 mpdu_frames_processed_count[31:0] +// 26 msdu_frames_processed_count[31:0] +// 27 total_processed_byte_count[31:0] +// 28 late_receive_mpdu_count[11:0], window_jump_2k[15:12], hole_count[31:16] +// 29 reserved_29[31:0] +// 30 reserved_30[31:0] +// 31 reserved_31[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_REO_QUEUE 32 + +struct rx_reo_queue { + struct uniform_descriptor_header descriptor_header; + uint32_t receive_queue_number : 16, //[15:0] + reserved_1b : 16; //[31:16] + uint32_t vld : 1, //[0] + associated_link_descriptor_counter: 2, //[2:1] + disable_duplicate_detection : 1, //[3] + soft_reorder_enable : 1, //[4] + ac : 2, //[6:5] + bar : 1, //[7] + rty : 1, //[8] + chk_2k_mode : 1, //[9] + oor_mode : 1, //[10] + ba_window_size : 8, //[18:11] + pn_check_needed : 1, //[19] + pn_shall_be_even : 1, //[20] + pn_shall_be_uneven : 1, //[21] + pn_handling_enable : 1, //[22] + pn_size : 2, //[24:23] + ignore_ampdu_flag : 1, //[25] + reserved_2b : 6; //[31:26] + uint32_t svld : 1, //[0] + ssn : 12, //[12:1] + current_index : 8, //[20:13] + seq_2k_error_detected_flag : 1, //[21] + pn_error_detected_flag : 1, //[22] + reserved_3a : 8, //[30:23] + pn_valid : 1; //[31] + uint32_t pn_31_0 : 32; //[31:0] + uint32_t pn_63_32 : 32; //[31:0] + uint32_t pn_95_64 : 32; //[31:0] + uint32_t pn_127_96 : 32; //[31:0] + uint32_t last_rx_enqueue_timestamp : 32; //[31:0] + uint32_t last_rx_dequeue_timestamp : 32; //[31:0] + uint32_t ptr_to_next_aging_queue_31_0 : 32; //[31:0] + uint32_t ptr_to_next_aging_queue_39_32 : 8, //[7:0] + reserved_11a : 24; //[31:8] + uint32_t ptr_to_previous_aging_queue_31_0: 32; //[31:0] + uint32_t ptr_to_previous_aging_queue_39_32: 8, //[7:0] + reserved_13a : 24; //[31:8] + uint32_t rx_bitmap_31_0 : 32; //[31:0] + uint32_t rx_bitmap_63_32 : 32; //[31:0] + uint32_t rx_bitmap_95_64 : 32; //[31:0] + uint32_t rx_bitmap_127_96 : 32; //[31:0] + uint32_t rx_bitmap_159_128 : 32; //[31:0] + uint32_t rx_bitmap_191_160 : 32; //[31:0] + uint32_t rx_bitmap_223_192 : 32; //[31:0] + uint32_t rx_bitmap_255_224 : 32; //[31:0] + uint32_t current_mpdu_count : 7, //[6:0] + current_msdu_count : 25; //[31:7] + uint32_t reserved_23 : 4, //[3:0] + timeout_count : 6, //[9:4] + forward_due_to_bar_count : 6, //[15:10] + duplicate_count : 16; //[31:16] + uint32_t frames_in_order_count : 24, //[23:0] + bar_received_count : 8; //[31:24] + uint32_t mpdu_frames_processed_count : 32; //[31:0] + uint32_t msdu_frames_processed_count : 32; //[31:0] + uint32_t total_processed_byte_count : 32; //[31:0] + uint32_t late_receive_mpdu_count : 12, //[11:0] + window_jump_2k : 4, //[15:12] + hole_count : 16; //[31:16] + uint32_t reserved_29 : 32; //[31:0] + uint32_t reserved_30 : 32; //[31:0] + uint32_t reserved_31 : 32; //[31:0] +}; + +/* + +struct uniform_descriptor_header descriptor_header + + Details about which module owns this struct. + + Note that sub field Buffer_type shall be set to + Receive_REO_queue_descriptor + +receive_queue_number + + Indicates the MPDU queue ID to which this MPDU link + descriptor belongs + + Used for tracking and debugging + + + +reserved_1b + + + +vld + + Valid bit indicating a session is established and the + queue descriptor is valid(Filled by SW) + + + +associated_link_descriptor_counter + + Indicates which of the 3 link descriptor counters shall + be incremented or decremented when link descriptors are + added or removed from this flow queue. + + MSDU link descriptors related with MPDUs stored in the + re-order buffer shall also be included in this count. + + + + + +disable_duplicate_detection + + When set, do not perform any duplicate detection. + + + + + +soft_reorder_enable + + When set, REO has been instructed to not perform the + actual re-ordering of frames for this queue, but just to + insert the reorder opcodes. + + + + Note that this implies that REO is also not going to + perform any MSDU level operations, and the entire MPDU (and + thus pointer to the MSDU link descriptor) will be pushed to + a destination ring that SW has programmed in a SW + programmable configuration register in REO + + + + + +ac + + Indicates which access category the queue descriptor + belongs to(filled by SW) + + + +bar + + Indicates if BAR has been received (mostly used for + debug purpose and this is filled by REO) + + + +rty + + Retry bit is checked if this bit is set. + + + +chk_2k_mode + + Indicates what type of operation is expected from Reo + when the received frame SN falls within the 2K window + + + + See REO MLD document for programming details. + + + +oor_mode + + Out of Order mode: + + Indicates what type of operation is expected when the + received frame falls within the OOR window. + + + + See REO MLD document for programming details. + + + +ba_window_size + + Indicates the negotiated (window size + 1). + + It can go up to Max of 256bits. + + + + A value 255 means 256 bitmap, 63 means 64 bitmap, 0 + (means non-BA session, with window size of 0). The 3 values + here are the main values validated, but other values should + work as well. + + + + A BA window size of 0 (=> one frame entry bitmat), means + that there is NO RX_REO_QUEUE_EXT descriptor following this + RX_REO_QUEUE STRUCT in memory + + + + A BA window size of 1 - 105, means that there is 1 + RX_REO_QUEUE_EXT descriptor directly following this + RX_REO_QUEUE STRUCT in memory. + + + + A BA window size of 106 - 210, means that there are 2 + RX_REO_QUEUE_EXT descriptors directly following this + RX_REO_QUEUE STRUCT in memory + + + + A BA window size of 211 - 256, means that there are 3 + RX_REO_QUEUE_EXT descriptors directly following this + RX_REO_QUEUE STRUCT in memory + + + + + +pn_check_needed + + When set, REO shall perform the PN increment check + + + +pn_shall_be_even + + Field only valid when 'pn_check_needed' is set. + + + + When set, REO shall confirm that the received PN number + is not only incremented, but also always an even number + + + +pn_shall_be_uneven + + Field only valid when 'pn_check_needed' is set. + + + + When set, REO shall confirm that the received PN number + is not only incremented, but also always an uneven number + + + +pn_handling_enable + + Field only valid when 'pn_check_needed' is set. + + + + When set, and REO detected a PN error, HW shall set the + 'pn_error_detected_flag'. + + + +pn_size + + Size of the PN field check. + + Needed for wrap around handling... + + + + + + + + + + + + + +ignore_ampdu_flag + + When set, REO shall ignore the ampdu_flag on the + entrance descriptor for this queue. + + + +reserved_2b + + + +svld + + Sequence number in next field is valid one. It can be + filled by SW if the want to fill in the any negotiated SSN, + otherwise REO will fill the sequence number of first + received packet and set this bit to 1. + + + +ssn + + Starting Sequence number of the session, this changes + whenever window moves. (can be filled by SW then maintained + by REO) + + + +current_index + + Points to last forwarded packet + + + +seq_2k_error_detected_flag + + Set by REO, can only be cleared by SW + + + + When set, REO has detected a 2k error jump in the + sequence number and from that moment forward, all new frames + are forwarded directly to FW, without duplicate detect, + reordering, etc. + + + +pn_error_detected_flag + + Set by REO, can only be cleared by SW + + + + When set, REO has detected a PN error and from that + moment forward, all new frames are forwarded directly to FW, + without duplicate detect, reordering, etc. + + + +reserved_3a + + + +pn_valid + + PN number in next fields are valid. It can be filled by + SW if it wants to fill in the any negotiated SSN, otherwise + REO will fill the pn based on the first received packet and + set this bit to 1. + + + +pn_31_0 + + + + +pn_63_32 + + Bits [63:32] of the PN number. + + + +pn_95_64 + + Bits [95:64] of the PN number. + + + +pn_127_96 + + Bits [127:96] of the PN number. + + + +last_rx_enqueue_timestamp + + This timestamp is updated when an MPDU is received and + accesses this Queue Descriptor. It does not include the + access due to Command TLVs or Aging (which will be updated + in Last_rx_dequeue_timestamp). + + + +last_rx_dequeue_timestamp + + This timestamp is used for Aging. When an MPDU or + multiple MPDUs are forwarded, either due to window movement, + bar, aging or command flush, this timestamp is updated. Also + when the bitmap is all zero and the first time an MPDU is + queued (opcode=QCUR), this timestamp is updated for aging. + + + +ptr_to_next_aging_queue_31_0 + + Address (address bits 31-0)of next RX_REO_QUEUE + descriptor in the 'receive timestamp' ordered list. + + From it the Position of this queue descriptor in the per + AC aging waitlist can be derived. + + Value 0x0 indicates the 'NULL' pointer which implies + that this is the last entry in the list. + + + +ptr_to_next_aging_queue_39_32 + + Address (address bits 39-32)of next RX_REO_QUEUE + descriptor in the 'receive timestamp' ordered list. + + From it the Position of this queue descriptor in the per + AC aging waitlist can be derived. + + Value 0x0 indicates the 'NULL' pointer which implies + that this is the last entry in the list. + + + +reserved_11a + + + +ptr_to_previous_aging_queue_31_0 + + Address (address bits 31-0)of next RX_REO_QUEUE + descriptor in the 'receive timestamp' ordered list. + + From it the Position of this queue descriptor in the per + AC aging waitlist can be derived. + + Value 0x0 indicates the 'NULL' pointer which implies + that this is the first entry in the list. + + + +ptr_to_previous_aging_queue_39_32 + + Address (address bits 39-32)of next RX_REO_QUEUE + descriptor in the 'receive timestamp' ordered list. + + From it the Position of this queue descriptor in the per + AC aging waitlist can be derived. + + Value 0x0 indicates the 'NULL' pointer which implies + that this is the first entry in the list. + + + +reserved_13a + + + +rx_bitmap_31_0 + + When a bit is set, the corresponding frame is currently + held in the re-order queue. + + The bitmap is Fully managed by HW. + + SW shall init this to 0, and then never ever change it + + + +rx_bitmap_63_32 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_95_64 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_127_96 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_159_128 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_191_160 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_223_192 + + See Rx_bitmap_31_0 description + + + +rx_bitmap_255_224 + + See Rx_bitmap_31_0 description + + + +current_mpdu_count + + The number of MPDUs in the queue. + + + + + +current_msdu_count + + The number of MSDUs in the queue. + + + +reserved_23 + + + +timeout_count + + The number of times that REO started forwarding frames + even though there is a hole in the bitmap. Forwarding reason + is Timeout + + + + The counter saturates and freezes at 0x3F + + + + + +forward_due_to_bar_count + + The number of times that REO started forwarding frames + even though there is a hole in the bitmap. Forwarding reason + is reception of BAR frame. + + + + The counter saturates and freezes at 0x3F + + + + + +duplicate_count + + The number of duplicate frames that have been detected + + + +frames_in_order_count + + The number of frames that have been received in order + (without a hole that prevented them from being forwarded + immediately) + + + + This corresponds to the Reorder opcodes: + + 'FWDCUR' and 'FWD BUF' + + + + + +bar_received_count + + The number of times a BAR frame is received. + + + + This corresponds to the Reorder opcodes with 'DROP' + + + + The counter saturates and freezes at 0xFF + + + +mpdu_frames_processed_count + + The total number of MPDU frames that have been processed + by REO. 'Processing' here means that REO has received them + out of the entrance ring, and retrieved the corresponding + RX_REO_QUEUE Descriptor. + + + + Note that this count includes duplicates, frames that + later had errors, etc. + + + + Note that field 'Duplicate_count' indicates how many of + these MPDUs were duplicates. + + + + + +msdu_frames_processed_count + + The total number of MSDU frames that have been processed + by REO. 'Processing' here means that REO has received them + out of the entrance ring, and retrieved the corresponding + RX_REO_QUEUE Descriptor. + + + + Note that this count includes duplicates, frames that + later had errors, etc. + + + + + +total_processed_byte_count + + An approximation of the number of bytes processed for + this queue. + + 'Processing' here means that REO has received them out + of the entrance ring, and retrieved the corresponding + RX_REO_QUEUE Descriptor. + + + + Note that this count includes duplicates, frames that + later had errors, etc. + + + + In 64 byte units + + + +late_receive_mpdu_count + + The number of MPDUs received after the window had + already moved on. The 'late' sequence window is defined as + (Window SSN - 256) - (Window SSN - 1) + + + + This corresponds with Out of order detection in + duplicate detect FSM + + + + The counter saturates and freezes at 0xFFF + + + + + +window_jump_2k + + The number of times the window moved more then 2K + + + + The counter saturates and freezes at 0xF + + + + (Note: field name can not start with number: previous + 2k_window_jump) + + + + + +hole_count + + The number of times a hole was created in the receive + bitmap. + + + + This corresponds to the Reorder opcodes with 'QCUR' + + + + + +reserved_29 + + + +reserved_30 + + + +reserved_31 + + +*/ + + + /* EXTERNAL REFERENCE : struct uniform_descriptor_header descriptor_header */ + + +/* Description RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + + + The owner of this data structure: + + Buffer Manager currently owns this + data structure. + + Software of FW currently owns + this data structure. + + Transmit Queue Manager currently owns + this data structure. + + Receive DMA currently owns this + data structure. + + Reorder currently owns this data + structure. + + SWITCH currently owns this data + structure. + + + + +*/ +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + +/* Description RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + + + Field describing what contents format is of this + descriptor + + + + + + + + + + + + + + NOT TO BE USED: + + + + + + + + + + + + + + + + + + + + + + +*/ +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + +/* Description RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A + + +*/ +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 +#define RX_REO_QUEUE_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 + +/* Description RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER + + Indicates the MPDU queue ID to which this MPDU link + descriptor belongs + + Used for tracking and debugging + + +*/ +#define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_OFFSET 0x00000004 +#define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_LSB 0 +#define RX_REO_QUEUE_1_RECEIVE_QUEUE_NUMBER_MASK 0x0000ffff + +/* Description RX_REO_QUEUE_1_RESERVED_1B + + +*/ +#define RX_REO_QUEUE_1_RESERVED_1B_OFFSET 0x00000004 +#define RX_REO_QUEUE_1_RESERVED_1B_LSB 16 +#define RX_REO_QUEUE_1_RESERVED_1B_MASK 0xffff0000 + +/* Description RX_REO_QUEUE_2_VLD + + Valid bit indicating a session is established and the + queue descriptor is valid(Filled by SW) + + +*/ +#define RX_REO_QUEUE_2_VLD_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_VLD_LSB 0 +#define RX_REO_QUEUE_2_VLD_MASK 0x00000001 + +/* Description RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER + + Indicates which of the 3 link descriptor counters shall + be incremented or decremented when link descriptors are + added or removed from this flow queue. + + MSDU link descriptors related with MPDUs stored in the + re-order buffer shall also be included in this count. + + + + +*/ +#define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_LSB 1 +#define RX_REO_QUEUE_2_ASSOCIATED_LINK_DESCRIPTOR_COUNTER_MASK 0x00000006 + +/* Description RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION + + When set, do not perform any duplicate detection. + + + + +*/ +#define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_LSB 3 +#define RX_REO_QUEUE_2_DISABLE_DUPLICATE_DETECTION_MASK 0x00000008 + +/* Description RX_REO_QUEUE_2_SOFT_REORDER_ENABLE + + When set, REO has been instructed to not perform the + actual re-ordering of frames for this queue, but just to + insert the reorder opcodes. + + + + Note that this implies that REO is also not going to + perform any MSDU level operations, and the entire MPDU (and + thus pointer to the MSDU link descriptor) will be pushed to + a destination ring that SW has programmed in a SW + programmable configuration register in REO + + + + +*/ +#define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_LSB 4 +#define RX_REO_QUEUE_2_SOFT_REORDER_ENABLE_MASK 0x00000010 + +/* Description RX_REO_QUEUE_2_AC + + Indicates which access category the queue descriptor + belongs to(filled by SW) + + +*/ +#define RX_REO_QUEUE_2_AC_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_AC_LSB 5 +#define RX_REO_QUEUE_2_AC_MASK 0x00000060 + +/* Description RX_REO_QUEUE_2_BAR + + Indicates if BAR has been received (mostly used for + debug purpose and this is filled by REO) + + +*/ +#define RX_REO_QUEUE_2_BAR_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_BAR_LSB 7 +#define RX_REO_QUEUE_2_BAR_MASK 0x00000080 + +/* Description RX_REO_QUEUE_2_RTY + + Retry bit is checked if this bit is set. + + +*/ +#define RX_REO_QUEUE_2_RTY_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_RTY_LSB 8 +#define RX_REO_QUEUE_2_RTY_MASK 0x00000100 + +/* Description RX_REO_QUEUE_2_CHK_2K_MODE + + Indicates what type of operation is expected from Reo + when the received frame SN falls within the 2K window + + + + See REO MLD document for programming details. + + +*/ +#define RX_REO_QUEUE_2_CHK_2K_MODE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_CHK_2K_MODE_LSB 9 +#define RX_REO_QUEUE_2_CHK_2K_MODE_MASK 0x00000200 + +/* Description RX_REO_QUEUE_2_OOR_MODE + + Out of Order mode: + + Indicates what type of operation is expected when the + received frame falls within the OOR window. + + + + See REO MLD document for programming details. + + +*/ +#define RX_REO_QUEUE_2_OOR_MODE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_OOR_MODE_LSB 10 +#define RX_REO_QUEUE_2_OOR_MODE_MASK 0x00000400 + +/* Description RX_REO_QUEUE_2_BA_WINDOW_SIZE + + Indicates the negotiated (window size + 1). + + It can go up to Max of 256bits. + + + + A value 255 means 256 bitmap, 63 means 64 bitmap, 0 + (means non-BA session, with window size of 0). The 3 values + here are the main values validated, but other values should + work as well. + + + + A BA window size of 0 (=> one frame entry bitmat), means + that there is NO RX_REO_QUEUE_EXT descriptor following this + RX_REO_QUEUE STRUCT in memory + + + + A BA window size of 1 - 105, means that there is 1 + RX_REO_QUEUE_EXT descriptor directly following this + RX_REO_QUEUE STRUCT in memory. + + + + A BA window size of 106 - 210, means that there are 2 + RX_REO_QUEUE_EXT descriptors directly following this + RX_REO_QUEUE STRUCT in memory + + + + A BA window size of 211 - 256, means that there are 3 + RX_REO_QUEUE_EXT descriptors directly following this + RX_REO_QUEUE STRUCT in memory + + + + +*/ +#define RX_REO_QUEUE_2_BA_WINDOW_SIZE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_BA_WINDOW_SIZE_LSB 11 +#define RX_REO_QUEUE_2_BA_WINDOW_SIZE_MASK 0x0007f800 + +/* Description RX_REO_QUEUE_2_PN_CHECK_NEEDED + + When set, REO shall perform the PN increment check + + +*/ +#define RX_REO_QUEUE_2_PN_CHECK_NEEDED_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_PN_CHECK_NEEDED_LSB 19 +#define RX_REO_QUEUE_2_PN_CHECK_NEEDED_MASK 0x00080000 + +/* Description RX_REO_QUEUE_2_PN_SHALL_BE_EVEN + + Field only valid when 'pn_check_needed' is set. + + + + When set, REO shall confirm that the received PN number + is not only incremented, but also always an even number + + +*/ +#define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_LSB 20 +#define RX_REO_QUEUE_2_PN_SHALL_BE_EVEN_MASK 0x00100000 + +/* Description RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN + + Field only valid when 'pn_check_needed' is set. + + + + When set, REO shall confirm that the received PN number + is not only incremented, but also always an uneven number + + +*/ +#define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_LSB 21 +#define RX_REO_QUEUE_2_PN_SHALL_BE_UNEVEN_MASK 0x00200000 + +/* Description RX_REO_QUEUE_2_PN_HANDLING_ENABLE + + Field only valid when 'pn_check_needed' is set. + + + + When set, and REO detected a PN error, HW shall set the + 'pn_error_detected_flag'. + + +*/ +#define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_LSB 22 +#define RX_REO_QUEUE_2_PN_HANDLING_ENABLE_MASK 0x00400000 + +/* Description RX_REO_QUEUE_2_PN_SIZE + + Size of the PN field check. + + Needed for wrap around handling... + + + + + + + + + + + + +*/ +#define RX_REO_QUEUE_2_PN_SIZE_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_PN_SIZE_LSB 23 +#define RX_REO_QUEUE_2_PN_SIZE_MASK 0x01800000 + +/* Description RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG + + When set, REO shall ignore the ampdu_flag on the + entrance descriptor for this queue. + + +*/ +#define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_LSB 25 +#define RX_REO_QUEUE_2_IGNORE_AMPDU_FLAG_MASK 0x02000000 + +/* Description RX_REO_QUEUE_2_RESERVED_2B + + +*/ +#define RX_REO_QUEUE_2_RESERVED_2B_OFFSET 0x00000008 +#define RX_REO_QUEUE_2_RESERVED_2B_LSB 26 +#define RX_REO_QUEUE_2_RESERVED_2B_MASK 0xfc000000 + +/* Description RX_REO_QUEUE_3_SVLD + + Sequence number in next field is valid one. It can be + filled by SW if the want to fill in the any negotiated SSN, + otherwise REO will fill the sequence number of first + received packet and set this bit to 1. + + +*/ +#define RX_REO_QUEUE_3_SVLD_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_SVLD_LSB 0 +#define RX_REO_QUEUE_3_SVLD_MASK 0x00000001 + +/* Description RX_REO_QUEUE_3_SSN + + Starting Sequence number of the session, this changes + whenever window moves. (can be filled by SW then maintained + by REO) + + +*/ +#define RX_REO_QUEUE_3_SSN_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_SSN_LSB 1 +#define RX_REO_QUEUE_3_SSN_MASK 0x00001ffe + +/* Description RX_REO_QUEUE_3_CURRENT_INDEX + + Points to last forwarded packet + + +*/ +#define RX_REO_QUEUE_3_CURRENT_INDEX_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_CURRENT_INDEX_LSB 13 +#define RX_REO_QUEUE_3_CURRENT_INDEX_MASK 0x001fe000 + +/* Description RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG + + Set by REO, can only be cleared by SW + + + + When set, REO has detected a 2k error jump in the + sequence number and from that moment forward, all new frames + are forwarded directly to FW, without duplicate detect, + reordering, etc. + + +*/ +#define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_LSB 21 +#define RX_REO_QUEUE_3_SEQ_2K_ERROR_DETECTED_FLAG_MASK 0x00200000 + +/* Description RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG + + Set by REO, can only be cleared by SW + + + + When set, REO has detected a PN error and from that + moment forward, all new frames are forwarded directly to FW, + without duplicate detect, reordering, etc. + + +*/ +#define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_LSB 22 +#define RX_REO_QUEUE_3_PN_ERROR_DETECTED_FLAG_MASK 0x00400000 + +/* Description RX_REO_QUEUE_3_RESERVED_3A + + +*/ +#define RX_REO_QUEUE_3_RESERVED_3A_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_RESERVED_3A_LSB 23 +#define RX_REO_QUEUE_3_RESERVED_3A_MASK 0x7f800000 + +/* Description RX_REO_QUEUE_3_PN_VALID + + PN number in next fields are valid. It can be filled by + SW if it wants to fill in the any negotiated SSN, otherwise + REO will fill the pn based on the first received packet and + set this bit to 1. + + +*/ +#define RX_REO_QUEUE_3_PN_VALID_OFFSET 0x0000000c +#define RX_REO_QUEUE_3_PN_VALID_LSB 31 +#define RX_REO_QUEUE_3_PN_VALID_MASK 0x80000000 + +/* Description RX_REO_QUEUE_4_PN_31_0 + + + +*/ +#define RX_REO_QUEUE_4_PN_31_0_OFFSET 0x00000010 +#define RX_REO_QUEUE_4_PN_31_0_LSB 0 +#define RX_REO_QUEUE_4_PN_31_0_MASK 0xffffffff + +/* Description RX_REO_QUEUE_5_PN_63_32 + + Bits [63:32] of the PN number. + + +*/ +#define RX_REO_QUEUE_5_PN_63_32_OFFSET 0x00000014 +#define RX_REO_QUEUE_5_PN_63_32_LSB 0 +#define RX_REO_QUEUE_5_PN_63_32_MASK 0xffffffff + +/* Description RX_REO_QUEUE_6_PN_95_64 + + Bits [95:64] of the PN number. + + +*/ +#define RX_REO_QUEUE_6_PN_95_64_OFFSET 0x00000018 +#define RX_REO_QUEUE_6_PN_95_64_LSB 0 +#define RX_REO_QUEUE_6_PN_95_64_MASK 0xffffffff + +/* Description RX_REO_QUEUE_7_PN_127_96 + + Bits [127:96] of the PN number. + + +*/ +#define RX_REO_QUEUE_7_PN_127_96_OFFSET 0x0000001c +#define RX_REO_QUEUE_7_PN_127_96_LSB 0 +#define RX_REO_QUEUE_7_PN_127_96_MASK 0xffffffff + +/* Description RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP + + This timestamp is updated when an MPDU is received and + accesses this Queue Descriptor. It does not include the + access due to Command TLVs or Aging (which will be updated + in Last_rx_dequeue_timestamp). + + +*/ +#define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_OFFSET 0x00000020 +#define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_LSB 0 +#define RX_REO_QUEUE_8_LAST_RX_ENQUEUE_TIMESTAMP_MASK 0xffffffff + +/* Description RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP + + This timestamp is used for Aging. When an MPDU or + multiple MPDUs are forwarded, either due to window movement, + bar, aging or command flush, this timestamp is updated. Also + when the bitmap is all zero and the first time an MPDU is + queued (opcode=QCUR), this timestamp is updated for aging. + + +*/ +#define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_OFFSET 0x00000024 +#define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_LSB 0 +#define RX_REO_QUEUE_9_LAST_RX_DEQUEUE_TIMESTAMP_MASK 0xffffffff + +/* Description RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0 + + Address (address bits 31-0)of next RX_REO_QUEUE + descriptor in the 'receive timestamp' ordered list. + + From it the Position of this queue descriptor in the per + AC aging waitlist can be derived. + + Value 0x0 indicates the 'NULL' pointer which implies + that this is the last entry in the list. + + +*/ +#define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_OFFSET 0x00000028 +#define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_LSB 0 +#define RX_REO_QUEUE_10_PTR_TO_NEXT_AGING_QUEUE_31_0_MASK 0xffffffff + +/* Description RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32 + + Address (address bits 39-32)of next RX_REO_QUEUE + descriptor in the 'receive timestamp' ordered list. + + From it the Position of this queue descriptor in the per + AC aging waitlist can be derived. + + Value 0x0 indicates the 'NULL' pointer which implies + that this is the last entry in the list. + + +*/ +#define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_OFFSET 0x0000002c +#define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_LSB 0 +#define RX_REO_QUEUE_11_PTR_TO_NEXT_AGING_QUEUE_39_32_MASK 0x000000ff + +/* Description RX_REO_QUEUE_11_RESERVED_11A + + +*/ +#define RX_REO_QUEUE_11_RESERVED_11A_OFFSET 0x0000002c +#define RX_REO_QUEUE_11_RESERVED_11A_LSB 8 +#define RX_REO_QUEUE_11_RESERVED_11A_MASK 0xffffff00 + +/* Description RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0 + + Address (address bits 31-0)of next RX_REO_QUEUE + descriptor in the 'receive timestamp' ordered list. + + From it the Position of this queue descriptor in the per + AC aging waitlist can be derived. + + Value 0x0 indicates the 'NULL' pointer which implies + that this is the first entry in the list. + + +*/ +#define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_OFFSET 0x00000030 +#define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_LSB 0 +#define RX_REO_QUEUE_12_PTR_TO_PREVIOUS_AGING_QUEUE_31_0_MASK 0xffffffff + +/* Description RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32 + + Address (address bits 39-32)of next RX_REO_QUEUE + descriptor in the 'receive timestamp' ordered list. + + From it the Position of this queue descriptor in the per + AC aging waitlist can be derived. + + Value 0x0 indicates the 'NULL' pointer which implies + that this is the first entry in the list. + + +*/ +#define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_OFFSET 0x00000034 +#define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_LSB 0 +#define RX_REO_QUEUE_13_PTR_TO_PREVIOUS_AGING_QUEUE_39_32_MASK 0x000000ff + +/* Description RX_REO_QUEUE_13_RESERVED_13A + + +*/ +#define RX_REO_QUEUE_13_RESERVED_13A_OFFSET 0x00000034 +#define RX_REO_QUEUE_13_RESERVED_13A_LSB 8 +#define RX_REO_QUEUE_13_RESERVED_13A_MASK 0xffffff00 + +/* Description RX_REO_QUEUE_14_RX_BITMAP_31_0 + + When a bit is set, the corresponding frame is currently + held in the re-order queue. + + The bitmap is Fully managed by HW. + + SW shall init this to 0, and then never ever change it + + +*/ +#define RX_REO_QUEUE_14_RX_BITMAP_31_0_OFFSET 0x00000038 +#define RX_REO_QUEUE_14_RX_BITMAP_31_0_LSB 0 +#define RX_REO_QUEUE_14_RX_BITMAP_31_0_MASK 0xffffffff + +/* Description RX_REO_QUEUE_15_RX_BITMAP_63_32 + + See Rx_bitmap_31_0 description + + +*/ +#define RX_REO_QUEUE_15_RX_BITMAP_63_32_OFFSET 0x0000003c +#define RX_REO_QUEUE_15_RX_BITMAP_63_32_LSB 0 +#define RX_REO_QUEUE_15_RX_BITMAP_63_32_MASK 0xffffffff + +/* Description RX_REO_QUEUE_16_RX_BITMAP_95_64 + + See Rx_bitmap_31_0 description + + +*/ +#define RX_REO_QUEUE_16_RX_BITMAP_95_64_OFFSET 0x00000040 +#define RX_REO_QUEUE_16_RX_BITMAP_95_64_LSB 0 +#define RX_REO_QUEUE_16_RX_BITMAP_95_64_MASK 0xffffffff + +/* Description RX_REO_QUEUE_17_RX_BITMAP_127_96 + + See Rx_bitmap_31_0 description + + +*/ +#define RX_REO_QUEUE_17_RX_BITMAP_127_96_OFFSET 0x00000044 +#define RX_REO_QUEUE_17_RX_BITMAP_127_96_LSB 0 +#define RX_REO_QUEUE_17_RX_BITMAP_127_96_MASK 0xffffffff + +/* Description RX_REO_QUEUE_18_RX_BITMAP_159_128 + + See Rx_bitmap_31_0 description + + +*/ +#define RX_REO_QUEUE_18_RX_BITMAP_159_128_OFFSET 0x00000048 +#define RX_REO_QUEUE_18_RX_BITMAP_159_128_LSB 0 +#define RX_REO_QUEUE_18_RX_BITMAP_159_128_MASK 0xffffffff + +/* Description RX_REO_QUEUE_19_RX_BITMAP_191_160 + + See Rx_bitmap_31_0 description + + +*/ +#define RX_REO_QUEUE_19_RX_BITMAP_191_160_OFFSET 0x0000004c +#define RX_REO_QUEUE_19_RX_BITMAP_191_160_LSB 0 +#define RX_REO_QUEUE_19_RX_BITMAP_191_160_MASK 0xffffffff + +/* Description RX_REO_QUEUE_20_RX_BITMAP_223_192 + + See Rx_bitmap_31_0 description + + +*/ +#define RX_REO_QUEUE_20_RX_BITMAP_223_192_OFFSET 0x00000050 +#define RX_REO_QUEUE_20_RX_BITMAP_223_192_LSB 0 +#define RX_REO_QUEUE_20_RX_BITMAP_223_192_MASK 0xffffffff + +/* Description RX_REO_QUEUE_21_RX_BITMAP_255_224 + + See Rx_bitmap_31_0 description + + +*/ +#define RX_REO_QUEUE_21_RX_BITMAP_255_224_OFFSET 0x00000054 +#define RX_REO_QUEUE_21_RX_BITMAP_255_224_LSB 0 +#define RX_REO_QUEUE_21_RX_BITMAP_255_224_MASK 0xffffffff + +/* Description RX_REO_QUEUE_22_CURRENT_MPDU_COUNT + + The number of MPDUs in the queue. + + + + +*/ +#define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_OFFSET 0x00000058 +#define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_LSB 0 +#define RX_REO_QUEUE_22_CURRENT_MPDU_COUNT_MASK 0x0000007f + +/* Description RX_REO_QUEUE_22_CURRENT_MSDU_COUNT + + The number of MSDUs in the queue. + + +*/ +#define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_OFFSET 0x00000058 +#define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_LSB 7 +#define RX_REO_QUEUE_22_CURRENT_MSDU_COUNT_MASK 0xffffff80 + +/* Description RX_REO_QUEUE_23_RESERVED_23 + + +*/ +#define RX_REO_QUEUE_23_RESERVED_23_OFFSET 0x0000005c +#define RX_REO_QUEUE_23_RESERVED_23_LSB 0 +#define RX_REO_QUEUE_23_RESERVED_23_MASK 0x0000000f + +/* Description RX_REO_QUEUE_23_TIMEOUT_COUNT + + The number of times that REO started forwarding frames + even though there is a hole in the bitmap. Forwarding reason + is Timeout + + + + The counter saturates and freezes at 0x3F + + + + +*/ +#define RX_REO_QUEUE_23_TIMEOUT_COUNT_OFFSET 0x0000005c +#define RX_REO_QUEUE_23_TIMEOUT_COUNT_LSB 4 +#define RX_REO_QUEUE_23_TIMEOUT_COUNT_MASK 0x000003f0 + +/* Description RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT + + The number of times that REO started forwarding frames + even though there is a hole in the bitmap. Forwarding reason + is reception of BAR frame. + + + + The counter saturates and freezes at 0x3F + + + + +*/ +#define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_OFFSET 0x0000005c +#define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_LSB 10 +#define RX_REO_QUEUE_23_FORWARD_DUE_TO_BAR_COUNT_MASK 0x0000fc00 + +/* Description RX_REO_QUEUE_23_DUPLICATE_COUNT + + The number of duplicate frames that have been detected + + +*/ +#define RX_REO_QUEUE_23_DUPLICATE_COUNT_OFFSET 0x0000005c +#define RX_REO_QUEUE_23_DUPLICATE_COUNT_LSB 16 +#define RX_REO_QUEUE_23_DUPLICATE_COUNT_MASK 0xffff0000 + +/* Description RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT + + The number of frames that have been received in order + (without a hole that prevented them from being forwarded + immediately) + + + + This corresponds to the Reorder opcodes: + + 'FWDCUR' and 'FWD BUF' + + + + +*/ +#define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_OFFSET 0x00000060 +#define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_LSB 0 +#define RX_REO_QUEUE_24_FRAMES_IN_ORDER_COUNT_MASK 0x00ffffff + +/* Description RX_REO_QUEUE_24_BAR_RECEIVED_COUNT + + The number of times a BAR frame is received. + + + + This corresponds to the Reorder opcodes with 'DROP' + + + + The counter saturates and freezes at 0xFF + + +*/ +#define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_OFFSET 0x00000060 +#define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_LSB 24 +#define RX_REO_QUEUE_24_BAR_RECEIVED_COUNT_MASK 0xff000000 + +/* Description RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT + + The total number of MPDU frames that have been processed + by REO. 'Processing' here means that REO has received them + out of the entrance ring, and retrieved the corresponding + RX_REO_QUEUE Descriptor. + + + + Note that this count includes duplicates, frames that + later had errors, etc. + + + + Note that field 'Duplicate_count' indicates how many of + these MPDUs were duplicates. + + + + +*/ +#define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000064 +#define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define RX_REO_QUEUE_25_MPDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +/* Description RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT + + The total number of MSDU frames that have been processed + by REO. 'Processing' here means that REO has received them + out of the entrance ring, and retrieved the corresponding + RX_REO_QUEUE Descriptor. + + + + Note that this count includes duplicates, frames that + later had errors, etc. + + + + +*/ +#define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_OFFSET 0x00000068 +#define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_LSB 0 +#define RX_REO_QUEUE_26_MSDU_FRAMES_PROCESSED_COUNT_MASK 0xffffffff + +/* Description RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT + + An approximation of the number of bytes processed for + this queue. + + 'Processing' here means that REO has received them out + of the entrance ring, and retrieved the corresponding + RX_REO_QUEUE Descriptor. + + + + Note that this count includes duplicates, frames that + later had errors, etc. + + + + In 64 byte units + + +*/ +#define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_OFFSET 0x0000006c +#define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_LSB 0 +#define RX_REO_QUEUE_27_TOTAL_PROCESSED_BYTE_COUNT_MASK 0xffffffff + +/* Description RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT + + The number of MPDUs received after the window had + already moved on. The 'late' sequence window is defined as + (Window SSN - 256) - (Window SSN - 1) + + + + This corresponds with Out of order detection in + duplicate detect FSM + + + + The counter saturates and freezes at 0xFFF + + + + +*/ +#define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_OFFSET 0x00000070 +#define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_LSB 0 +#define RX_REO_QUEUE_28_LATE_RECEIVE_MPDU_COUNT_MASK 0x00000fff + +/* Description RX_REO_QUEUE_28_WINDOW_JUMP_2K + + The number of times the window moved more then 2K + + + + The counter saturates and freezes at 0xF + + + + (Note: field name can not start with number: previous + 2k_window_jump) + + + + +*/ +#define RX_REO_QUEUE_28_WINDOW_JUMP_2K_OFFSET 0x00000070 +#define RX_REO_QUEUE_28_WINDOW_JUMP_2K_LSB 12 +#define RX_REO_QUEUE_28_WINDOW_JUMP_2K_MASK 0x0000f000 + +/* Description RX_REO_QUEUE_28_HOLE_COUNT + + The number of times a hole was created in the receive + bitmap. + + + + This corresponds to the Reorder opcodes with 'QCUR' + + + + +*/ +#define RX_REO_QUEUE_28_HOLE_COUNT_OFFSET 0x00000070 +#define RX_REO_QUEUE_28_HOLE_COUNT_LSB 16 +#define RX_REO_QUEUE_28_HOLE_COUNT_MASK 0xffff0000 + +/* Description RX_REO_QUEUE_29_RESERVED_29 + + +*/ +#define RX_REO_QUEUE_29_RESERVED_29_OFFSET 0x00000074 +#define RX_REO_QUEUE_29_RESERVED_29_LSB 0 +#define RX_REO_QUEUE_29_RESERVED_29_MASK 0xffffffff + +/* Description RX_REO_QUEUE_30_RESERVED_30 + + +*/ +#define RX_REO_QUEUE_30_RESERVED_30_OFFSET 0x00000078 +#define RX_REO_QUEUE_30_RESERVED_30_LSB 0 +#define RX_REO_QUEUE_30_RESERVED_30_MASK 0xffffffff + +/* Description RX_REO_QUEUE_31_RESERVED_31 + + +*/ +#define RX_REO_QUEUE_31_RESERVED_31_OFFSET 0x0000007c +#define RX_REO_QUEUE_31_RESERVED_31_LSB 0 +#define RX_REO_QUEUE_31_RESERVED_31_MASK 0xffffffff + + +#endif // _RX_REO_QUEUE_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/rx_reo_queue_ext.h b/drivers/staging/fw-api/hw/qca6750/v1/rx_reo_queue_ext.h new file mode 100644 index 000000000000..aaeb28ab75c6 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/rx_reo_queue_ext.h @@ -0,0 +1,2794 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_REO_QUEUE_EXT_H_ +#define _RX_REO_QUEUE_EXT_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "uniform_descriptor_header.h" +#include "rx_mpdu_link_ptr.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 struct uniform_descriptor_header descriptor_header; +// 1 reserved_1a[31:0] +// 2-3 struct rx_mpdu_link_ptr mpdu_link_pointer_0; +// 4-5 struct rx_mpdu_link_ptr mpdu_link_pointer_1; +// 6-7 struct rx_mpdu_link_ptr mpdu_link_pointer_2; +// 8-9 struct rx_mpdu_link_ptr mpdu_link_pointer_3; +// 10-11 struct rx_mpdu_link_ptr mpdu_link_pointer_4; +// 12-13 struct rx_mpdu_link_ptr mpdu_link_pointer_5; +// 14-15 struct rx_mpdu_link_ptr mpdu_link_pointer_6; +// 16-17 struct rx_mpdu_link_ptr mpdu_link_pointer_7; +// 18-19 struct rx_mpdu_link_ptr mpdu_link_pointer_8; +// 20-21 struct rx_mpdu_link_ptr mpdu_link_pointer_9; +// 22-23 struct rx_mpdu_link_ptr mpdu_link_pointer_10; +// 24-25 struct rx_mpdu_link_ptr mpdu_link_pointer_11; +// 26-27 struct rx_mpdu_link_ptr mpdu_link_pointer_12; +// 28-29 struct rx_mpdu_link_ptr mpdu_link_pointer_13; +// 30-31 struct rx_mpdu_link_ptr mpdu_link_pointer_14; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_REO_QUEUE_EXT 32 + +struct rx_reo_queue_ext { + struct uniform_descriptor_header descriptor_header; + uint32_t reserved_1a : 32; //[31:0] + struct rx_mpdu_link_ptr mpdu_link_pointer_0; + struct rx_mpdu_link_ptr mpdu_link_pointer_1; + struct rx_mpdu_link_ptr mpdu_link_pointer_2; + struct rx_mpdu_link_ptr mpdu_link_pointer_3; + struct rx_mpdu_link_ptr mpdu_link_pointer_4; + struct rx_mpdu_link_ptr mpdu_link_pointer_5; + struct rx_mpdu_link_ptr mpdu_link_pointer_6; + struct rx_mpdu_link_ptr mpdu_link_pointer_7; + struct rx_mpdu_link_ptr mpdu_link_pointer_8; + struct rx_mpdu_link_ptr mpdu_link_pointer_9; + struct rx_mpdu_link_ptr mpdu_link_pointer_10; + struct rx_mpdu_link_ptr mpdu_link_pointer_11; + struct rx_mpdu_link_ptr mpdu_link_pointer_12; + struct rx_mpdu_link_ptr mpdu_link_pointer_13; + struct rx_mpdu_link_ptr mpdu_link_pointer_14; +}; + +/* + +struct uniform_descriptor_header descriptor_header + + Details about which module owns this struct. + + Note that sub field Buffer_type shall be set to + Receive_REO_queue_ext_descriptor + +reserved_1a + + + +struct rx_mpdu_link_ptr mpdu_link_pointer_0 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_1 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_2 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_3 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_4 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_5 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_6 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_7 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_8 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_9 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_10 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_11 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_12 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_13 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue + +struct rx_mpdu_link_ptr mpdu_link_pointer_14 + + Consumer: REO + + Producer: REO + + + + Pointer to the next MPDU_link descriptor in the MPDU + queue +*/ + + + /* EXTERNAL REFERENCE : struct uniform_descriptor_header descriptor_header */ + + +/* Description RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + + + The owner of this data structure: + + Buffer Manager currently owns this + data structure. + + Software of FW currently owns + this data structure. + + Transmit Queue Manager currently owns + this data structure. + + Receive DMA currently owns this + data structure. + + Reorder currently owns this data + structure. + + SWITCH currently owns this data + structure. + + + + +*/ +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_LSB 0 +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_OWNER_MASK 0x0000000f + +/* Description RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + + + Field describing what contents format is of this + descriptor + + + + + + + + + + + + + + NOT TO BE USED: + + + + + + + + + + + + + + + + + + + + + + +*/ +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_LSB 4 +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_BUFFER_TYPE_MASK 0x000000f0 + +/* Description RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A + + +*/ +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_OFFSET 0x00000000 +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_LSB 8 +#define RX_REO_QUEUE_EXT_0_DESCRIPTOR_HEADER_RESERVED_0A_MASK 0xffffff00 + +/* Description RX_REO_QUEUE_EXT_1_RESERVED_1A + + +*/ +#define RX_REO_QUEUE_EXT_1_RESERVED_1A_OFFSET 0x00000004 +#define RX_REO_QUEUE_EXT_1_RESERVED_1A_LSB 0 +#define RX_REO_QUEUE_EXT_1_RESERVED_1A_MASK 0xffffffff + + /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_0 */ + + + /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ + + +/* Description RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000008 +#define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_2_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + +*/ +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000000c +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_3_MPDU_LINK_POINTER_0_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + + /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_1 */ + + + /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ + + +/* Description RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010 +#define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_4_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + +*/ +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014 +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_5_MPDU_LINK_POINTER_1_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + + /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_2 */ + + + /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ + + +/* Description RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000018 +#define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_6_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + +*/ +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000001c +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_7_MPDU_LINK_POINTER_2_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + + /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_3 */ + + + /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ + + +/* Description RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000020 +#define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_8_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + +*/ +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000024 +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_9_MPDU_LINK_POINTER_3_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + + /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_4 */ + + + /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ + + +/* Description RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000028 +#define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_10_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + +*/ +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000002c +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_11_MPDU_LINK_POINTER_4_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + + /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_5 */ + + + /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ + + +/* Description RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000030 +#define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_12_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + +*/ +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000034 +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_13_MPDU_LINK_POINTER_5_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + + /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_6 */ + + + /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ + + +/* Description RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000038 +#define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_14_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + +*/ +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000003c +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_15_MPDU_LINK_POINTER_6_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + + /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_7 */ + + + /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ + + +/* Description RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000040 +#define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_16_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + +*/ +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000044 +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_17_MPDU_LINK_POINTER_7_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + + /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_8 */ + + + /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ + + +/* Description RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000048 +#define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_18_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + +*/ +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000004c +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_19_MPDU_LINK_POINTER_8_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + + /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_9 */ + + + /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ + + +/* Description RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000050 +#define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_20_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + +*/ +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000054 +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_21_MPDU_LINK_POINTER_9_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + + /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_10 */ + + + /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ + + +/* Description RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000058 +#define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_22_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + +*/ +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000005c +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_23_MPDU_LINK_POINTER_10_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + + /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_11 */ + + + /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ + + +/* Description RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000060 +#define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_24_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + +*/ +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000064 +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_25_MPDU_LINK_POINTER_11_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + + /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_12 */ + + + /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ + + +/* Description RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000068 +#define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_26_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + +*/ +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000006c +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_27_MPDU_LINK_POINTER_12_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + + /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_13 */ + + + /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ + + +/* Description RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000070 +#define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_28_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + +*/ +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000074 +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_29_MPDU_LINK_POINTER_13_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + + /* EXTERNAL REFERENCE : struct rx_mpdu_link_ptr mpdu_link_pointer_14 */ + + + /* EXTERNAL REFERENCE : struct buffer_addr_info mpdu_link_desc_addr_info */ + + +/* Description RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000078 +#define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define RX_REO_QUEUE_EXT_30_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + +*/ +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x0000007c +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define RX_REO_QUEUE_EXT_31_MPDU_LINK_POINTER_14_MPDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + + +#endif // _RX_REO_QUEUE_EXT_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/rx_rxpcu_classification_overview.h b/drivers/staging/fw-api/hw/qca6750/v1/rx_rxpcu_classification_overview.h new file mode 100644 index 000000000000..1bb9c38f497c --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/rx_rxpcu_classification_overview.h @@ -0,0 +1,290 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ +#define _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 filter_pass_mpdus[0], filter_pass_mpdus_fcs_ok[1], monitor_direct_mpdus[2], monitor_direct_mpdus_fcs_ok[3], monitor_other_mpdus[4], monitor_other_mpdus_fcs_ok[5], phyrx_abort_received[6], reserved_0[15:7], phy_ppdu_id[31:16] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_RXPCU_CLASSIFICATION_OVERVIEW 1 + +struct rx_rxpcu_classification_overview { + uint32_t filter_pass_mpdus : 1, //[0] + filter_pass_mpdus_fcs_ok : 1, //[1] + monitor_direct_mpdus : 1, //[2] + monitor_direct_mpdus_fcs_ok : 1, //[3] + monitor_other_mpdus : 1, //[4] + monitor_other_mpdus_fcs_ok : 1, //[5] + phyrx_abort_received : 1, //[6] + reserved_0 : 9, //[15:7] + phy_ppdu_id : 16; //[31:16] +}; + +/* + +filter_pass_mpdus + + When set, at least one Filter Pass MPDU has been + received. FCS might or might not have been passing. + + + + For MU UL, in TLVs RX_PPDU_END and + RX_PPDU_END_STATUS_DONE, this field is the OR of all the + users. + + + +filter_pass_mpdus_fcs_ok + + When set, at least one Filter Pass MPDU has been + received that has a correct FCS. + + + + For MU UL, in TLVs RX_PPDU_END and + RX_PPDU_END_STATUS_DONE, this field is the OR of all the + users. + + + + + +monitor_direct_mpdus + + When set, at least one Monitor Direct MPDU has been + received. FCS might or might not have been passing + + + + For MU UL, in TLVs RX_PPDU_END and + RX_PPDU_END_STATUS_DONE, this field is the OR of all the + users. + + + +monitor_direct_mpdus_fcs_ok + + When set, at least one Monitor Direct MPDU has been + received that has a correct FCS. + + + + For MU UL, in TLVs RX_PPDU_END and + RX_PPDU_END_STATUS_DONE, this field is the OR of all the + users. + + + + + +monitor_other_mpdus + + When set, at least one Monitor Direct MPDU has been + received. FCS might or might not have been passing. + + + + For MU UL, in TLVs RX_PPDU_END and + RX_PPDU_END_STATUS_DONE, this field is the OR of all the + users. + + + +monitor_other_mpdus_fcs_ok + + When set, at least one Monitor Direct MPDU has been + received that has a correct FCS. + + + + For MU UL, in TLVs RX_PPDU_END and + RX_PPDU_END_STATUS_DONE, this field is the OR of all the + users. + + + +phyrx_abort_received + + When set, PPDU reception was aborted by the PHY + + + +reserved_0 + + + +phy_ppdu_id + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + +*/ + + +/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS + + When set, at least one Filter Pass MPDU has been + received. FCS might or might not have been passing. + + + + For MU UL, in TLVs RX_PPDU_END and + RX_PPDU_END_STATUS_DONE, this field is the OR of all the + users. + + +*/ +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_LSB 0 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_MASK 0x00000001 + +/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK + + When set, at least one Filter Pass MPDU has been + received that has a correct FCS. + + + + For MU UL, in TLVs RX_PPDU_END and + RX_PPDU_END_STATUS_DONE, this field is the OR of all the + users. + + + + +*/ +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_LSB 1 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_FILTER_PASS_MPDUS_FCS_OK_MASK 0x00000002 + +/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS + + When set, at least one Monitor Direct MPDU has been + received. FCS might or might not have been passing + + + + For MU UL, in TLVs RX_PPDU_END and + RX_PPDU_END_STATUS_DONE, this field is the OR of all the + users. + + +*/ +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_LSB 2 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_MASK 0x00000004 + +/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK + + When set, at least one Monitor Direct MPDU has been + received that has a correct FCS. + + + + For MU UL, in TLVs RX_PPDU_END and + RX_PPDU_END_STATUS_DONE, this field is the OR of all the + users. + + + + +*/ +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_LSB 3 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_DIRECT_MPDUS_FCS_OK_MASK 0x00000008 + +/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS + + When set, at least one Monitor Direct MPDU has been + received. FCS might or might not have been passing. + + + + For MU UL, in TLVs RX_PPDU_END and + RX_PPDU_END_STATUS_DONE, this field is the OR of all the + users. + + +*/ +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_LSB 4 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_MASK 0x00000010 + +/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK + + When set, at least one Monitor Direct MPDU has been + received that has a correct FCS. + + + + For MU UL, in TLVs RX_PPDU_END and + RX_PPDU_END_STATUS_DONE, this field is the OR of all the + users. + + +*/ +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_LSB 5 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_MONITOR_OTHER_MPDUS_FCS_OK_MASK 0x00000020 + +/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHYRX_ABORT_RECEIVED + + When set, PPDU reception was aborted by the PHY + + +*/ +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHYRX_ABORT_RECEIVED_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHYRX_ABORT_RECEIVED_LSB 6 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHYRX_ABORT_RECEIVED_MASK 0x00000040 + +/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0 + + +*/ +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_LSB 7 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_RESERVED_0_MASK 0x0000ff80 + +/* Description RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID + + A ppdu counter value that PHY increments for every PPDU + received. The counter value wraps around + + +*/ +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_OFFSET 0x00000000 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_LSB 16 +#define RX_RXPCU_CLASSIFICATION_OVERVIEW_0_PHY_PPDU_ID_MASK 0xffff0000 + + +#endif // _RX_RXPCU_CLASSIFICATION_OVERVIEW_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/rx_timing_offset_info.h b/drivers/staging/fw-api/hw/qca6750/v1/rx_timing_offset_info.h new file mode 100644 index 000000000000..a2147c8649f6 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/rx_timing_offset_info.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RX_TIMING_OFFSET_INFO_H_ +#define _RX_TIMING_OFFSET_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 residual_phase_offset[11:0], reserved[31:12] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RX_TIMING_OFFSET_INFO 1 + +struct rx_timing_offset_info { + uint32_t residual_phase_offset : 12, //[11:0] + reserved : 20; //[31:12] +}; + +/* + +residual_phase_offset + + Cumulative reference frequency error at end of RX + + + +reserved + + +*/ + + +/* Description RX_TIMING_OFFSET_INFO_0_RESIDUAL_PHASE_OFFSET + + Cumulative reference frequency error at end of RX + + +*/ +#define RX_TIMING_OFFSET_INFO_0_RESIDUAL_PHASE_OFFSET_OFFSET 0x00000000 +#define RX_TIMING_OFFSET_INFO_0_RESIDUAL_PHASE_OFFSET_LSB 0 +#define RX_TIMING_OFFSET_INFO_0_RESIDUAL_PHASE_OFFSET_MASK 0x00000fff + +/* Description RX_TIMING_OFFSET_INFO_0_RESERVED + + +*/ +#define RX_TIMING_OFFSET_INFO_0_RESERVED_OFFSET 0x00000000 +#define RX_TIMING_OFFSET_INFO_0_RESERVED_LSB 12 +#define RX_TIMING_OFFSET_INFO_0_RESERVED_MASK 0xfffff000 + + +#endif // _RX_TIMING_OFFSET_INFO_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/rxpcu_ppdu_end_info.h b/drivers/staging/fw-api/hw/qca6750/v1/rxpcu_ppdu_end_info.h new file mode 100644 index 000000000000..63ea3583d9cc --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/rxpcu_ppdu_end_info.h @@ -0,0 +1,1234 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RXPCU_PPDU_END_INFO_H_ +#define _RXPCU_PPDU_END_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "phyrx_abort_request_info.h" +#include "macrx_abort_request_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 wb_timestamp_lower_32[31:0] +// 1 wb_timestamp_upper_32[31:0] +// 2 rx_antenna[23:0], tx_ht_vht_ack[24], unsupported_mu_nc[25], otp_txbf_disable[26], previous_tlv_corrupted[27], phyrx_abort_request_info_valid[28], macrx_abort_request_info_valid[29], reserved[31:30] +// 3 coex_bt_tx_from_start_of_rx[0], coex_bt_tx_after_start_of_rx[1], coex_wan_tx_from_start_of_rx[2], coex_wan_tx_after_start_of_rx[3], coex_wlan_tx_from_start_of_rx[4], coex_wlan_tx_after_start_of_rx[5], mpdu_delimiter_errors_seen[6], ftm_tm[8:7], dialog_token[16:9], follow_up_dialog_token[24:17], bb_captured_channel[25], bb_captured_reason[28:26], bb_captured_timeout[29], reserved_3[31:30] +// 4 before_mpdu_count_passing_fcs[9:0], before_mpdu_count_failing_fcs[19:10], after_mpdu_count_passing_fcs[29:20], reserved_4[31:30] +// 5 after_mpdu_count_failing_fcs[9:0], reserved_5[31:10] +// 6 phy_timestamp_tx_lower_32[31:0] +// 7 phy_timestamp_tx_upper_32[31:0] +// 8 bb_length[15:0], bb_data[16], reserved_8[19:17], first_bt_broadcast_status_details[31:20] +// 9 rx_ppdu_duration[23:0], reserved_9[31:24] +// 10 ast_index[15:0], ast_index_valid[16], reserved_10[19:17], second_bt_broadcast_status_details[31:20] +// 11 struct phyrx_abort_request_info phyrx_abort_request_info_details; +// 12 struct macrx_abort_request_info macrx_abort_request_info_details; +// 13 rx_ppdu_end_marker[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RXPCU_PPDU_END_INFO 14 + +struct rxpcu_ppdu_end_info { + uint32_t wb_timestamp_lower_32 : 32; //[31:0] + uint32_t wb_timestamp_upper_32 : 32; //[31:0] + uint32_t rx_antenna : 24, //[23:0] + tx_ht_vht_ack : 1, //[24] + unsupported_mu_nc : 1, //[25] + otp_txbf_disable : 1, //[26] + previous_tlv_corrupted : 1, //[27] + phyrx_abort_request_info_valid : 1, //[28] + macrx_abort_request_info_valid : 1, //[29] + reserved : 2; //[31:30] + uint32_t coex_bt_tx_from_start_of_rx : 1, //[0] + coex_bt_tx_after_start_of_rx : 1, //[1] + coex_wan_tx_from_start_of_rx : 1, //[2] + coex_wan_tx_after_start_of_rx : 1, //[3] + coex_wlan_tx_from_start_of_rx : 1, //[4] + coex_wlan_tx_after_start_of_rx : 1, //[5] + mpdu_delimiter_errors_seen : 1, //[6] + ftm_tm : 2, //[8:7] + dialog_token : 8, //[16:9] + follow_up_dialog_token : 8, //[24:17] + bb_captured_channel : 1, //[25] + bb_captured_reason : 3, //[28:26] + bb_captured_timeout : 1, //[29] + reserved_3 : 2; //[31:30] + uint32_t before_mpdu_count_passing_fcs : 10, //[9:0] + before_mpdu_count_failing_fcs : 10, //[19:10] + after_mpdu_count_passing_fcs : 10, //[29:20] + reserved_4 : 2; //[31:30] + uint32_t after_mpdu_count_failing_fcs : 10, //[9:0] + reserved_5 : 22; //[31:10] + uint32_t phy_timestamp_tx_lower_32 : 32; //[31:0] + uint32_t phy_timestamp_tx_upper_32 : 32; //[31:0] + uint32_t bb_length : 16, //[15:0] + bb_data : 1, //[16] + reserved_8 : 3, //[19:17] + first_bt_broadcast_status_details: 12; //[31:20] + uint32_t rx_ppdu_duration : 24, //[23:0] + reserved_9 : 8; //[31:24] + uint32_t ast_index : 16, //[15:0] + ast_index_valid : 1, //[16] + reserved_10 : 3, //[19:17] + second_bt_broadcast_status_details: 12; //[31:20] + struct phyrx_abort_request_info phyrx_abort_request_info_details; + struct macrx_abort_request_info macrx_abort_request_info_details; + uint16_t pre_bt_broadcast_status_details : 12, //[27:16] + reserved_12a : 4; //[31:28] + uint32_t rx_ppdu_end_marker : 32; //[31:0] +}; + +/* + +wb_timestamp_lower_32 + + WLAN/BT timestamp is a 1 usec resolution timestamp which + does not get updated based on receive beacon like TSF. The + same rules for capturing tsf_timestamp are used to capture + the wb_timestamp. This field represents the lower 32 bits of + the 64-bit timestamp + +wb_timestamp_upper_32 + + WLAN/BT timestamp is a 1 usec resolution timestamp which + does not get updated based on receive beacon like TSF. The + same rules for capturing tsf_timestamp are used to capture + the wb_timestamp. This field represents the upper 32 bits of + the 64-bit timestamp + +rx_antenna + + Receive antenna value ??? + +tx_ht_vht_ack + + Indicates that a HT or VHT Ack/BA frame was transmitted + in response to this receive packet. + +unsupported_mu_nc + + Set if MU Nc > 2 in received NDPA. + + If this bit is set, even though AID and BSSID are + matched, MAC doesn't send tx_expect_ndp to PHY, because MU + Nc > 2 is not supported in Helium. + +otp_txbf_disable + + Set if either OTP_SUBFEE_DISABLE or OTP_TXBF_DISABLE is + set and if RXPU receives directed NDPA frame. Then, RXPCU + should not send TX_EXPECT_NDP TLV to SW but set this bit to + inform SW. + +previous_tlv_corrupted + + When set, the TLV preceding this RXPCU_END_INFO TLV + within the RX_PPDU_END TLV, is corrupted. Not the entire TLV + was received.... Likely due to an abort scenario... If abort + is to blame, see the abort data datastructure for details. + + + +phyrx_abort_request_info_valid + + When set, the PHY sent an PHYRX_ABORT_REQUEST TLV to + RXPCU. The abort fields embedded in this TLV contain valid + info. + + + +macrx_abort_request_info_valid + + When set, the MAC sent an MACRX_ABORT_REQUEST TLV to + PHYRX. The abort fields embedded in this TLV contain valid + info. + + + +reserved + + + +coex_bt_tx_from_start_of_rx + + Set when BT TX was ongoing when WLAN RX started + +coex_bt_tx_after_start_of_rx + + +coex_wan_tx_from_start_of_rx + + Set when WAN TX was ongoing when WLAN RX started + +coex_wan_tx_after_start_of_rx + + Set when WAN TX started while WLAN RX was already + ongoing + +coex_wlan_tx_from_start_of_rx + + Set when other WLAN TX was ongoing when WLAN RX started + +coex_wlan_tx_after_start_of_rx + + Set when other WLAN TX started while WLAN RX was already + ongoing + +mpdu_delimiter_errors_seen + + When set, MPDU delimiter errors have been detected + during this PPDU reception + +ftm_tm + + Indicate the timestamp is for the FTM or TM frame + + + + 0: non TM or FTM frame + + 1: FTM frame + + 2: TM frame + + 3: reserved + + + +dialog_token + + The dialog token in the FTM or TM frame. Only valid when + the FTM is set. Clear to 254 for a non-FTM frame + + + +follow_up_dialog_token + + The follow up dialog token in the FTM or TM frame. Only + valid when the FTM is set. Clear to 0 for a non-FTM frame, + The follow up dialog token in the FTM frame. Only valid when + the FTM is set. Clear to 255 for a non-FTM frame + +bb_captured_channel + + Set by RXPCU when MACRX_FREEZE_CAPTURE_CHANNEL TLV is + sent to PHY, FW check it to correlate current PPDU TLVs with + uploaded channel information. + + + + + +bb_captured_reason + + Copy capture_reason of MACRX_FREEZE_CAPTURE_CHANNEL TLV + to here for FW usage. Valid when bb_captured_channel or + bb_captured_timeout is set. + + + + This field indicates why the MAC asked to capture the + channel + + + + + + + + + + + + + + + + + +bb_captured_timeout + + Set by RxPCU to indicate channel capture condition is + meet, but MACRX_FREEZE_CAPTURE_CHANNEL is not sent to PHY + due to AST long delay, which means the rx_frame_falling edge + to FREEZE TLV ready time exceed the threshold time defined + by RXPCU register FREEZE_TLV_DELAY_CNT_THRESH. + + Bb_captured_reason is still valid in this case. + + + + + +reserved_3 + + + +before_mpdu_count_passing_fcs + + Number of MPDUs received in this PPDU that passed the + FCS check before the Coex TX started + + + + The counter saturates at 0x3FF. + + + +before_mpdu_count_failing_fcs + + Number of MPDUs received in this PPDU that failed the + FCS check before the Coex TX started + + + + The counter saturates at 0x3FF. + + + +after_mpdu_count_passing_fcs + + Number of MPDUs received in this PPDU that passed the + FCS check after the moment the Coex TX started + + + + (Note: The partially received MPDU when the COEX tx + start event came in falls in the after category) + + + + The counter saturates at 0x3FF. + + + +reserved_4 + + + +after_mpdu_count_failing_fcs + + Number of MPDUs received in this PPDU that failed the + FCS check after the moment the Coex TX started + + + + (Note: The partially received MPDU when the COEX tx + start event came in falls in the after category) + + + + The counter saturates at 0x3FF. + + + +reserved_5 + + + +phy_timestamp_tx_lower_32 + + The PHY timestamp in the AMPI of the most recent rising + edge (TODO: of what ???) after the TX_PHY_DESC.  This field + indicates the lower 32 bits of the timestamp + +phy_timestamp_tx_upper_32 + + The PHY timestamp in the AMPI of the most recent rising + edge (TODO: of what ???) after the TX_PHY_DESC.  This field + indicates the upper 32 bits of the timestamp + +bb_length + + Indicates the number of bytes of baseband information + for PPDUs where the BB descriptor preamble type is 0x80 to + 0xFF which indicates that this is not a normal PPDU but + rather contains baseband debug information. + + TODO: Is this still needed ??? + +bb_data + + Indicates that BB data associated with this PPDU will + exist in the receive buffer. The exact contents of this BB + data can be found by decoding the BB TLV in the buffer + associated with the BB data. See vector_fragment in the + Helium_mac_phy_interface.docx + +reserved_8 + + Reserved: HW should fill with 0, FW should ignore. + +first_bt_broadcast_status_details + + Same contents as field bt_broadcast_status_details for + the first received COEX_STATUS_BROADCAST tlv during this + PPDU reception. + + + + If no COEX_STATUS_BROADCAST tlv is received during this + PPDU reception, this field will be set to 0 + + + + + + For detailed info see doc: TBD + + + +rx_ppdu_duration + + The length of this PPDU reception in us + +reserved_9 + + + +ast_index + + The AST index of the receive Ack/BA. This information + is provided from the TXPCU to the RXPCU for receive Ack/BA + for implicit beamforming. + + + +ast_index_valid + + Indicates that ast_index is valid. Should only be set + for receive Ack/BA where single stream implicit sounding is + captured. + +reserved_10 + + + +second_bt_broadcast_status_details + + Same contents as field bt_broadcast_status_details for + the second received COEX_STATUS_BROADCAST tlv during this + PPDU reception. + + + + If no second COEX_STATUS_BROADCAST tlv is received + during this PPDU reception, this field will be set to 0 + + + + + + For detailed info see doc: TBD + + + +struct phyrx_abort_request_info phyrx_abort_request_info_details + + Field only valid when Phyrx_abort_request_info_valid is + set + + The reason why PHY generated an abort request + +struct macrx_abort_request_info macrx_abort_request_info_details + + Field only valid when macrx_abort_request_info_valid is + set + + The reason why MACRX generated an abort request + +rx_ppdu_end_marker + + Field used by SW to double check that their structure + alignment is in sync with what HW has done. + + +*/ + + +/* Description RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32 + + WLAN/BT timestamp is a 1 usec resolution timestamp which + does not get updated based on receive beacon like TSF. The + same rules for capturing tsf_timestamp are used to capture + the wb_timestamp. This field represents the lower 32 bits of + the 64-bit timestamp +*/ +#define RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32_OFFSET 0x00000000 +#define RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_0_WB_TIMESTAMP_LOWER_32_MASK 0xffffffff + +/* Description RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32 + + WLAN/BT timestamp is a 1 usec resolution timestamp which + does not get updated based on receive beacon like TSF. The + same rules for capturing tsf_timestamp are used to capture + the wb_timestamp. This field represents the upper 32 bits of + the 64-bit timestamp +*/ +#define RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32_OFFSET 0x00000004 +#define RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_1_WB_TIMESTAMP_UPPER_32_MASK 0xffffffff + +/* Description RXPCU_PPDU_END_INFO_2_RX_ANTENNA + + Receive antenna value ??? +*/ +#define RXPCU_PPDU_END_INFO_2_RX_ANTENNA_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_2_RX_ANTENNA_LSB 0 +#define RXPCU_PPDU_END_INFO_2_RX_ANTENNA_MASK 0x00ffffff + +/* Description RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK + + Indicates that a HT or VHT Ack/BA frame was transmitted + in response to this receive packet. +*/ +#define RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK_LSB 24 +#define RXPCU_PPDU_END_INFO_2_TX_HT_VHT_ACK_MASK 0x01000000 + +/* Description RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC + + Set if MU Nc > 2 in received NDPA. + + If this bit is set, even though AID and BSSID are + matched, MAC doesn't send tx_expect_ndp to PHY, because MU + Nc > 2 is not supported in Helium. +*/ +#define RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC_LSB 25 +#define RXPCU_PPDU_END_INFO_2_UNSUPPORTED_MU_NC_MASK 0x02000000 + +/* Description RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE + + Set if either OTP_SUBFEE_DISABLE or OTP_TXBF_DISABLE is + set and if RXPU receives directed NDPA frame. Then, RXPCU + should not send TX_EXPECT_NDP TLV to SW but set this bit to + inform SW. +*/ +#define RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE_LSB 26 +#define RXPCU_PPDU_END_INFO_2_OTP_TXBF_DISABLE_MASK 0x04000000 + +/* Description RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED + + When set, the TLV preceding this RXPCU_END_INFO TLV + within the RX_PPDU_END TLV, is corrupted. Not the entire TLV + was received.... Likely due to an abort scenario... If abort + is to blame, see the abort data datastructure for details. + + +*/ +#define RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED_LSB 27 +#define RXPCU_PPDU_END_INFO_2_PREVIOUS_TLV_CORRUPTED_MASK 0x08000000 + +/* Description RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID + + When set, the PHY sent an PHYRX_ABORT_REQUEST TLV to + RXPCU. The abort fields embedded in this TLV contain valid + info. + + +*/ +#define RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID_LSB 28 +#define RXPCU_PPDU_END_INFO_2_PHYRX_ABORT_REQUEST_INFO_VALID_MASK 0x10000000 + +/* Description RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID + + When set, the MAC sent an MACRX_ABORT_REQUEST TLV to + PHYRX. The abort fields embedded in this TLV contain valid + info. + + +*/ +#define RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID_LSB 29 +#define RXPCU_PPDU_END_INFO_2_MACRX_ABORT_REQUEST_INFO_VALID_MASK 0x20000000 + +/* Description RXPCU_PPDU_END_INFO_2_RESERVED + + +*/ +#define RXPCU_PPDU_END_INFO_2_RESERVED_OFFSET 0x00000008 +#define RXPCU_PPDU_END_INFO_2_RESERVED_LSB 30 +#define RXPCU_PPDU_END_INFO_2_RESERVED_MASK 0xc0000000 + +/* Description RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX + + Set when BT TX was ongoing when WLAN RX started +*/ +#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX_LSB 0 +#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_FROM_START_OF_RX_MASK 0x00000001 + +/* Description RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX + +*/ +#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX_LSB 1 +#define RXPCU_PPDU_END_INFO_3_COEX_BT_TX_AFTER_START_OF_RX_MASK 0x00000002 + +/* Description RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX + + Set when WAN TX was ongoing when WLAN RX started +*/ +#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX_LSB 2 +#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_FROM_START_OF_RX_MASK 0x00000004 + +/* Description RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX + + Set when WAN TX started while WLAN RX was already + ongoing +*/ +#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX_LSB 3 +#define RXPCU_PPDU_END_INFO_3_COEX_WAN_TX_AFTER_START_OF_RX_MASK 0x00000008 + +/* Description RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX + + Set when other WLAN TX was ongoing when WLAN RX started +*/ +#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX_LSB 4 +#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_FROM_START_OF_RX_MASK 0x00000010 + +/* Description RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX + + Set when other WLAN TX started while WLAN RX was already + ongoing +*/ +#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX_LSB 5 +#define RXPCU_PPDU_END_INFO_3_COEX_WLAN_TX_AFTER_START_OF_RX_MASK 0x00000020 + +/* Description RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN + + When set, MPDU delimiter errors have been detected + during this PPDU reception +*/ +#define RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN_LSB 6 +#define RXPCU_PPDU_END_INFO_3_MPDU_DELIMITER_ERRORS_SEEN_MASK 0x00000040 + +/* Description RXPCU_PPDU_END_INFO_3_FTM_TM + + Indicate the timestamp is for the FTM or TM frame + + + + 0: non TM or FTM frame + + 1: FTM frame + + 2: TM frame + + 3: reserved + + +*/ +#define RXPCU_PPDU_END_INFO_3_FTM_TM_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_FTM_TM_LSB 7 +#define RXPCU_PPDU_END_INFO_3_FTM_TM_MASK 0x00000180 + +/* Description RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN + + The dialog token in the FTM or TM frame. Only valid when + the FTM is set. Clear to 254 for a non-FTM frame + + +*/ +#define RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN_LSB 9 +#define RXPCU_PPDU_END_INFO_3_DIALOG_TOKEN_MASK 0x0001fe00 + +/* Description RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN + + The follow up dialog token in the FTM or TM frame. Only + valid when the FTM is set. Clear to 0 for a non-FTM frame, + The follow up dialog token in the FTM frame. Only valid when + the FTM is set. Clear to 255 for a non-FTM frame +*/ +#define RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN_LSB 17 +#define RXPCU_PPDU_END_INFO_3_FOLLOW_UP_DIALOG_TOKEN_MASK 0x01fe0000 + +/* Description RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL + + Set by RXPCU when MACRX_FREEZE_CAPTURE_CHANNEL TLV is + sent to PHY, FW check it to correlate current PPDU TLVs with + uploaded channel information. + + + + +*/ +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL_LSB 25 +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_CHANNEL_MASK 0x02000000 + +/* Description RXPCU_PPDU_END_INFO_3_BB_CAPTURED_REASON + + Copy capture_reason of MACRX_FREEZE_CAPTURE_CHANNEL TLV + to here for FW usage. Valid when bb_captured_channel or + bb_captured_timeout is set. + + + + This field indicates why the MAC asked to capture the + channel + + + + + + + + + + + + + + + + +*/ +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_REASON_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_REASON_LSB 26 +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_REASON_MASK 0x1c000000 + +/* Description RXPCU_PPDU_END_INFO_3_BB_CAPTURED_TIMEOUT + + Set by RxPCU to indicate channel capture condition is + meet, but MACRX_FREEZE_CAPTURE_CHANNEL is not sent to PHY + due to AST long delay, which means the rx_frame_falling edge + to FREEZE TLV ready time exceed the threshold time defined + by RXPCU register FREEZE_TLV_DELAY_CNT_THRESH. + + Bb_captured_reason is still valid in this case. + + + + +*/ +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_TIMEOUT_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_TIMEOUT_LSB 29 +#define RXPCU_PPDU_END_INFO_3_BB_CAPTURED_TIMEOUT_MASK 0x20000000 + +/* Description RXPCU_PPDU_END_INFO_3_RESERVED_3 + + +*/ +#define RXPCU_PPDU_END_INFO_3_RESERVED_3_OFFSET 0x0000000c +#define RXPCU_PPDU_END_INFO_3_RESERVED_3_LSB 30 +#define RXPCU_PPDU_END_INFO_3_RESERVED_3_MASK 0xc0000000 + +/* Description RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS + + Number of MPDUs received in this PPDU that passed the + FCS check before the Coex TX started + + + + The counter saturates at 0x3FF. + + +*/ +#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS_OFFSET 0x00000010 +#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS_LSB 0 +#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_PASSING_FCS_MASK 0x000003ff + +/* Description RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS + + Number of MPDUs received in this PPDU that failed the + FCS check before the Coex TX started + + + + The counter saturates at 0x3FF. + + +*/ +#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS_OFFSET 0x00000010 +#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS_LSB 10 +#define RXPCU_PPDU_END_INFO_4_BEFORE_MPDU_COUNT_FAILING_FCS_MASK 0x000ffc00 + +/* Description RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS + + Number of MPDUs received in this PPDU that passed the + FCS check after the moment the Coex TX started + + + + (Note: The partially received MPDU when the COEX tx + start event came in falls in the after category) + + + + The counter saturates at 0x3FF. + + +*/ +#define RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS_OFFSET 0x00000010 +#define RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS_LSB 20 +#define RXPCU_PPDU_END_INFO_4_AFTER_MPDU_COUNT_PASSING_FCS_MASK 0x3ff00000 + +/* Description RXPCU_PPDU_END_INFO_4_RESERVED_4 + + +*/ +#define RXPCU_PPDU_END_INFO_4_RESERVED_4_OFFSET 0x00000010 +#define RXPCU_PPDU_END_INFO_4_RESERVED_4_LSB 30 +#define RXPCU_PPDU_END_INFO_4_RESERVED_4_MASK 0xc0000000 + +/* Description RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS + + Number of MPDUs received in this PPDU that failed the + FCS check after the moment the Coex TX started + + + + (Note: The partially received MPDU when the COEX tx + start event came in falls in the after category) + + + + The counter saturates at 0x3FF. + + +*/ +#define RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS_OFFSET 0x00000014 +#define RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS_LSB 0 +#define RXPCU_PPDU_END_INFO_5_AFTER_MPDU_COUNT_FAILING_FCS_MASK 0x000003ff + +/* Description RXPCU_PPDU_END_INFO_5_RESERVED_5 + + +*/ +#define RXPCU_PPDU_END_INFO_5_RESERVED_5_OFFSET 0x00000014 +#define RXPCU_PPDU_END_INFO_5_RESERVED_5_LSB 10 +#define RXPCU_PPDU_END_INFO_5_RESERVED_5_MASK 0xfffffc00 + +/* Description RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32 + + The PHY timestamp in the AMPI of the most recent rising + edge (TODO: of what ???) after the TX_PHY_DESC.  This field + indicates the lower 32 bits of the timestamp +*/ +#define RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32_OFFSET 0x00000018 +#define RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_6_PHY_TIMESTAMP_TX_LOWER_32_MASK 0xffffffff + +/* Description RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32 + + The PHY timestamp in the AMPI of the most recent rising + edge (TODO: of what ???) after the TX_PHY_DESC.  This field + indicates the upper 32 bits of the timestamp +*/ +#define RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32_OFFSET 0x0000001c +#define RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32_LSB 0 +#define RXPCU_PPDU_END_INFO_7_PHY_TIMESTAMP_TX_UPPER_32_MASK 0xffffffff + +/* Description RXPCU_PPDU_END_INFO_8_BB_LENGTH + + Indicates the number of bytes of baseband information + for PPDUs where the BB descriptor preamble type is 0x80 to + 0xFF which indicates that this is not a normal PPDU but + rather contains baseband debug information. + + TODO: Is this still needed ??? +*/ +#define RXPCU_PPDU_END_INFO_8_BB_LENGTH_OFFSET 0x00000020 +#define RXPCU_PPDU_END_INFO_8_BB_LENGTH_LSB 0 +#define RXPCU_PPDU_END_INFO_8_BB_LENGTH_MASK 0x0000ffff + +/* Description RXPCU_PPDU_END_INFO_8_BB_DATA + + Indicates that BB data associated with this PPDU will + exist in the receive buffer. The exact contents of this BB + data can be found by decoding the BB TLV in the buffer + associated with the BB data. See vector_fragment in the + Helium_mac_phy_interface.docx +*/ +#define RXPCU_PPDU_END_INFO_8_BB_DATA_OFFSET 0x00000020 +#define RXPCU_PPDU_END_INFO_8_BB_DATA_LSB 16 +#define RXPCU_PPDU_END_INFO_8_BB_DATA_MASK 0x00010000 + +/* Description RXPCU_PPDU_END_INFO_8_RESERVED_8 + + Reserved: HW should fill with 0, FW should ignore. +*/ +#define RXPCU_PPDU_END_INFO_8_RESERVED_8_OFFSET 0x00000020 +#define RXPCU_PPDU_END_INFO_8_RESERVED_8_LSB 17 +#define RXPCU_PPDU_END_INFO_8_RESERVED_8_MASK 0x000e0000 + +/* Description RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS + + Same contents as field bt_broadcast_status_details for + the first received COEX_STATUS_BROADCAST tlv during this + PPDU reception. + + + + If no COEX_STATUS_BROADCAST tlv is received during this + PPDU reception, this field will be set to 0 + + + + + + For detailed info see doc: TBD + + +*/ +#define RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000020 +#define RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 20 +#define RXPCU_PPDU_END_INFO_8_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0xfff00000 + +/* Description RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION + + The length of this PPDU reception in us +*/ +#define RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 0x00000024 +#define RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 0 +#define RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 0x00ffffff + +/* Description RXPCU_PPDU_END_INFO_9_RESERVED_9 + + +*/ +#define RXPCU_PPDU_END_INFO_9_RESERVED_9_OFFSET 0x00000024 +#define RXPCU_PPDU_END_INFO_9_RESERVED_9_LSB 24 +#define RXPCU_PPDU_END_INFO_9_RESERVED_9_MASK 0xff000000 + +/* Description RXPCU_PPDU_END_INFO_10_AST_INDEX + + The AST index of the receive Ack/BA. This information + is provided from the TXPCU to the RXPCU for receive Ack/BA + for implicit beamforming. + + +*/ +#define RXPCU_PPDU_END_INFO_10_AST_INDEX_OFFSET 0x00000028 +#define RXPCU_PPDU_END_INFO_10_AST_INDEX_LSB 0 +#define RXPCU_PPDU_END_INFO_10_AST_INDEX_MASK 0x0000ffff + +/* Description RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID + + Indicates that ast_index is valid. Should only be set + for receive Ack/BA where single stream implicit sounding is + captured. +*/ +#define RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID_OFFSET 0x00000028 +#define RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID_LSB 16 +#define RXPCU_PPDU_END_INFO_10_AST_INDEX_VALID_MASK 0x00010000 + +/* Description RXPCU_PPDU_END_INFO_10_RESERVED_10 + + +*/ +#define RXPCU_PPDU_END_INFO_10_RESERVED_10_OFFSET 0x00000028 +#define RXPCU_PPDU_END_INFO_10_RESERVED_10_LSB 17 +#define RXPCU_PPDU_END_INFO_10_RESERVED_10_MASK 0x000e0000 + +/* Description RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS + + Same contents as field bt_broadcast_status_details for + the second received COEX_STATUS_BROADCAST tlv during this + PPDU reception. + + + + If no second COEX_STATUS_BROADCAST tlv is received + during this PPDU reception, this field will be set to 0 + + + + + + For detailed info see doc: TBD + + +*/ +#define RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000028 +#define RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 20 +#define RXPCU_PPDU_END_INFO_10_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0xfff00000 + + /* EXTERNAL REFERENCE : struct phyrx_abort_request_info phyrx_abort_request_info_details */ + + +/* Description RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON + + Reception aborted due to + receiving a PHY_OFF TLV + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Should not really be used. If + needed, ask for documentation update + + + + + + + + + + + + + + +*/ +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 0 +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000ff + +/* Description RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE + + When set, PHY enters PHY NAP state after sending this + abort + + + + Note that nap and defer state are mutually exclusive. + + + + Field put pro-actively in place....usage still to be + agreed upon. + + +*/ +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_LSB 8 +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_NAP_STATE_MASK 0x00000100 + +/* Description RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE + + When set, PHY enters PHY defer state after sending this + abort + + + + Note that nap and defer state are mutually exclusive. + + + + Field put pro-actively in place....usage still to be + agreed upon. + + +*/ +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_LSB 9 +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHY_ENTERS_DEFER_STATE_MASK 0x00000200 + +/* Description RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0 + + +*/ +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 10 +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000fc00 + +/* Description RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION + + The remaining receive duration of this PPDU in the + medium (in us). When PHY does not know this duration when + this TLV is generated, the field will be set to 0. + + The timing reference point is the reception by the MAC + of this TLV. The value shall be accurate to within 2us. + + + + In case Phy_enters_nap_state and/or + Phy_enters_defer_state is set, there is a possibility that + MAC PMM can also decide to go into a low(er) power state. + + +*/ +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_OFFSET 0x0000002c +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_LSB 16 +#define RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_RECEIVE_DURATION_MASK 0xffff0000 + + /* EXTERNAL REFERENCE : struct macrx_abort_request_info macrx_abort_request_info_details */ + + +/* Description RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON + + + + Upon receiving this + abort reason, PHY should stop reception of the current frame + and go back into a search mode + + + + MAC FW + issued an abort for channel switch reasons + + MAC FW + issued an abort power save reasons + + RXPCU is + terminating the current ongoing reception, as the data that + MAC is receiving seems to be all garbage... The PER is too + high, or in case of MU UL, Likely the trigger frame never + got properly received by any of the targeted MU UL devices. + After the abort, PHYRX can resume a normal search mode. + + + + +*/ +#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_OFFSET 0x00000030 +#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_LSB 0 +#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_MACRX_ABORT_REASON_MASK 0x000000ff + +/* Description RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0 + + +*/ +#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_OFFSET 0x00000030 +#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_LSB 8 +#define RXPCU_PPDU_END_INFO_12_MACRX_ABORT_REQUEST_INFO_DETAILS_RESERVED_0_MASK 0x0000ff00 + +/* Description RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER + + Field used by SW to double check that their structure + alignment is in sync with what HW has done. + + +*/ +#define RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER_OFFSET 0x00000034 +#define RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER_LSB 0 +#define RXPCU_PPDU_END_INFO_13_RX_PPDU_END_MARKER_MASK 0xffffffff + + +#endif // _RXPCU_PPDU_END_INFO_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/rxpt_classify_info.h b/drivers/staging/fw-api/hw/qca6750/v1/rxpt_classify_info.h new file mode 100644 index 000000000000..362cd300a52f --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/rxpt_classify_info.h @@ -0,0 +1,522 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _RXPT_CLASSIFY_INFO_H_ +#define _RXPT_CLASSIFY_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 reo_destination_indication[4:0], lmac_peer_id_msb[6:5], use_flow_id_toeplitz_clfy[7], pkt_selection_fp_ucast_data[8], pkt_selection_fp_mcast_data[9], pkt_selection_fp_1000[10], rxdma0_source_ring_selection[12:11], rxdma0_destination_ring_selection[14:13], reserved_0b[31:15] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_RXPT_CLASSIFY_INFO 1 + +struct rxpt_classify_info { + uint32_t reo_destination_indication : 5, //[4:0] + lmac_peer_id_msb : 2, //[6:5] + use_flow_id_toeplitz_clfy : 1, //[7] + pkt_selection_fp_ucast_data : 1, //[8] + pkt_selection_fp_mcast_data : 1, //[9] + pkt_selection_fp_1000 : 1, //[10] + rxdma0_source_ring_selection : 2, //[12:11] + rxdma0_destination_ring_selection: 2, //[14:13] + reserved_0b : 17; //[31:15] +}; + +/* + +reo_destination_indication + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW2 ring + + Reo will push the frame + into the REO2SW3 ring + + Reo will push the frame + into the REO2SW4 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + Reo will push the frame + into the REO2SW5 ring (REO remaps this in chips without + REO2SW5 ring, e.g. Pine) + + Reo will push the frame + into the REO2SW6 ring (REO remaps this in chips without + REO2SW6 ring, e.g. Pine) + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + + +lmac_peer_id_msb + + If use_flow_id_toeplitz_clfy is set and lmac_peer_id_'sb + is 2'b00, Rx OLE uses a REO desination indicati'n of {1'b1, + hash[3:0]} using the chosen Toeplitz hash from Common Parser + if flow search fails. + + If use_flow_id_toeplitz_clfy is set and lmac_peer_id_msb + 's not 2'b00, Rx OLE uses a REO desination indication of + {lmac_peer_id_msb, hash[2:0]} using the chosen Toeplitz hash + from Common Parser if flow search fails. + + This LMAC/peer-based routing is not supported in + Hastings80 and HastingsPrime. + + + +use_flow_id_toeplitz_clfy + + Indication to Rx OLE to enable REO destination routing + based on the chosen Toeplitz hash from Common Parser, in + case flow search fails + + + +pkt_selection_fp_ucast_data + + Filter pass Unicast data frame (matching + rxpcu_filter_pass and sw_frame_group_Unicast_data) routing + selection + + + + 1'b0: source and destination rings are selected from the + RxOLE register settings for the packet type + + + + 1'b1: source ring and destination ring is selected from + the rxdma0_source_ring_selection and + rxdma0_destination_ring_selection fields in this STRUCT + + + +pkt_selection_fp_mcast_data + + Filter pass Multicast data frame (matching + rxpcu_filter_pass and sw_frame_group_Multicast_data) routing + selection + + + + 1'b0: source and destination rings are selected from the + RxOLE register settings for the packet type + + + + 1'b1: source ring and destination ring is selected from + the rxdma0_source_ring_selection and + rxdma0_destination_ring_selection fields in this STRUCT + + + +pkt_selection_fp_1000 + + Filter pass BAR frame (matching rxpcu_filter_pass and + sw_frame_group_ctrl_1000) routing selection + + + + 1'b0: source and destination rings are selected from the + RxOLE register settings for the packet type + + + + 1'b1: source ring and destination ring is selected from + the rxdma0_source_ring_selection and + rxdma0_destination_ring_selection fields in this STRUCT + + + +rxdma0_source_ring_selection + + Field only valid when for the received frame type the + corresponding pkt_selection_fp_... bit is set + + + + The data buffer for + + The data buffer for + this frame shall be sourced by fw2rxdma buffer source ring. + + The data buffer for + this frame shall be sourced by sw2rxdma buffer source ring. + + The frame shall not be written + to any data buffer. + + + + + +rxdma0_destination_ring_selection + + Field only valid when for the received frame type the + corresponding pkt_selection_fp_... bit is set + + + + RXDMA0 shall push the frame + to the Release ring. Effectively this means the frame needs + to be dropped. + + RXDMA0 shall push the frame to + the FW ring. + + RXDMA0 shall push the frame to + the SW ring. + + RXDMA0 shall push the frame to + the REO entrance ring. + + + + + +reserved_0b + + +*/ + + +/* Description RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION + + The ID of the REO exit ring where the MSDU frame shall + push after (MPDU level) reordering has finished. + + + + Reo will push the frame + into the REO2TCL ring + + Reo will push the frame + into the REO2SW1 ring + + Reo will push the frame + into the REO2SW2 ring + + Reo will push the frame + into the REO2SW3 ring + + Reo will push the frame + into the REO2SW4 ring + + Reo will push the frame + into the REO_release ring + + Reo will push the frame into + the REO2FW ring + + Reo will push the frame + into the REO2SW5 ring (REO remaps this in chips without + REO2SW5 ring, e.g. Pine) + + Reo will push the frame + into the REO2SW6 ring (REO remaps this in chips without + REO2SW6 ring, e.g. Pine) + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + REO remaps this + + + + +*/ +#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_LSB 0 +#define RXPT_CLASSIFY_INFO_0_REO_DESTINATION_INDICATION_MASK 0x0000001f + +/* Description RXPT_CLASSIFY_INFO_0_LMAC_PEER_ID_MSB + + If use_flow_id_toeplitz_clfy is set and lmac_peer_id_'sb + is 2'b00, Rx OLE uses a REO desination indicati'n of {1'b1, + hash[3:0]} using the chosen Toeplitz hash from Common Parser + if flow search fails. + + If use_flow_id_toeplitz_clfy is set and lmac_peer_id_msb + 's not 2'b00, Rx OLE uses a REO desination indication of + {lmac_peer_id_msb, hash[2:0]} using the chosen Toeplitz hash + from Common Parser if flow search fails. + + This LMAC/peer-based routing is not supported in + Hastings80 and HastingsPrime. + + +*/ +#define RXPT_CLASSIFY_INFO_0_LMAC_PEER_ID_MSB_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_LMAC_PEER_ID_MSB_LSB 5 +#define RXPT_CLASSIFY_INFO_0_LMAC_PEER_ID_MSB_MASK 0x00000060 + +/* Description RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY + + Indication to Rx OLE to enable REO destination routing + based on the chosen Toeplitz hash from Common Parser, in + case flow search fails + + +*/ +#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_LSB 7 +#define RXPT_CLASSIFY_INFO_0_USE_FLOW_ID_TOEPLITZ_CLFY_MASK 0x00000080 + +/* Description RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_UCAST_DATA + + Filter pass Unicast data frame (matching + rxpcu_filter_pass and sw_frame_group_Unicast_data) routing + selection + + + + 1'b0: source and destination rings are selected from the + RxOLE register settings for the packet type + + + + 1'b1: source ring and destination ring is selected from + the rxdma0_source_ring_selection and + rxdma0_destination_ring_selection fields in this STRUCT + + +*/ +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_UCAST_DATA_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_UCAST_DATA_LSB 8 +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_UCAST_DATA_MASK 0x00000100 + +/* Description RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_MCAST_DATA + + Filter pass Multicast data frame (matching + rxpcu_filter_pass and sw_frame_group_Multicast_data) routing + selection + + + + 1'b0: source and destination rings are selected from the + RxOLE register settings for the packet type + + + + 1'b1: source ring and destination ring is selected from + the rxdma0_source_ring_selection and + rxdma0_destination_ring_selection fields in this STRUCT + + +*/ +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_MCAST_DATA_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_MCAST_DATA_LSB 9 +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_MCAST_DATA_MASK 0x00000200 + +/* Description RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_1000 + + Filter pass BAR frame (matching rxpcu_filter_pass and + sw_frame_group_ctrl_1000) routing selection + + + + 1'b0: source and destination rings are selected from the + RxOLE register settings for the packet type + + + + 1'b1: source ring and destination ring is selected from + the rxdma0_source_ring_selection and + rxdma0_destination_ring_selection fields in this STRUCT + + +*/ +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_1000_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_1000_LSB 10 +#define RXPT_CLASSIFY_INFO_0_PKT_SELECTION_FP_1000_MASK 0x00000400 + +/* Description RXPT_CLASSIFY_INFO_0_RXDMA0_SOURCE_RING_SELECTION + + Field only valid when for the received frame type the + corresponding pkt_selection_fp_... bit is set + + + + The data buffer for + + The data buffer for + this frame shall be sourced by fw2rxdma buffer source ring. + + The data buffer for + this frame shall be sourced by sw2rxdma buffer source ring. + + The frame shall not be written + to any data buffer. + + + + +*/ +#define RXPT_CLASSIFY_INFO_0_RXDMA0_SOURCE_RING_SELECTION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_RXDMA0_SOURCE_RING_SELECTION_LSB 11 +#define RXPT_CLASSIFY_INFO_0_RXDMA0_SOURCE_RING_SELECTION_MASK 0x00001800 + +/* Description RXPT_CLASSIFY_INFO_0_RXDMA0_DESTINATION_RING_SELECTION + + Field only valid when for the received frame type the + corresponding pkt_selection_fp_... bit is set + + + + RXDMA0 shall push the frame + to the Release ring. Effectively this means the frame needs + to be dropped. + + RXDMA0 shall push the frame to + the FW ring. + + RXDMA0 shall push the frame to + the SW ring. + + RXDMA0 shall push the frame to + the REO entrance ring. + + + + +*/ +#define RXPT_CLASSIFY_INFO_0_RXDMA0_DESTINATION_RING_SELECTION_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_RXDMA0_DESTINATION_RING_SELECTION_LSB 13 +#define RXPT_CLASSIFY_INFO_0_RXDMA0_DESTINATION_RING_SELECTION_MASK 0x00006000 + +/* Description RXPT_CLASSIFY_INFO_0_RESERVED_0B + + +*/ +#define RXPT_CLASSIFY_INFO_0_RESERVED_0B_OFFSET 0x00000000 +#define RXPT_CLASSIFY_INFO_0_RESERVED_0B_LSB 15 +#define RXPT_CLASSIFY_INFO_0_RESERVED_0B_MASK 0xffff8000 + + +#endif // _RXPT_CLASSIFY_INFO_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/seq_hwio.h b/drivers/staging/fw-api/hw/qca6750/v1/seq_hwio.h new file mode 100644 index 000000000000..4bcb9e75116a --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/seq_hwio.h @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/********************************************************************************* + * + * DESCRIPTION + * - This is an extension of standard msmhwio.h to support relative addressing + * scheme used in SCALe auto-generated sequences. + * - The objective of this new addressing scheme is enable the same C function + * definition to be applicable to multiple baseances of the same block. + * - Such code reuse is not feasible with the standard HWIO macros that use a + * absolute addressing scheme. + * - Compared to the standard HWIO macros, the new macros defined here take an + * additional parameter 'baseance offset'. So are the C functions generated + * by SCALe Autoseq from .seq inputs. + * - As such, macros defined in this file must be used with 'seq_msmhwiobase.h', + * 'seq_msmhwioreg.h', and the C codes generated from SCALe Autoseq. + * - Macros defined in this file leverage the lower-level macros from the + * standard 'msmhwio.h', and the two sets of macros are compatible. + * + ********************************************************************************/ + +#ifndef __SEQ_H__ +#define __SEQ_H__ + +#include "HALhwio.h" + + + +/**** Register Ref Read ****/ +#define SEQ_INH(base, regtype, reg) \ + SEQ_##regtype##_INH(base, reg) + +/**** Masked Register Read ****/ +#define SEQ_INMH(base, regtype, reg, mask) \ + SEQ_##regtype##_INMH(base, reg, mask) + + +/**** Ref Reg Field Read ****/ +#define SEQ_INFH(base, regtype, reg, fld) \ + (SEQ_##regtype##_INMH(base, reg, HWIO_FMSK(regtype, fld)) >> HWIO_SHFT(regtype, fld)) + + +/**** Ref Register Write ****/ +#define SEQ_OUTH(base, regtype, reg, val) \ + SEQ_##regtype##_OUTH(base, reg, val) + +/**** Ref Register Masked Write ****/ +#define SEQ_OUTMH(base, regtype, reg, mask, val) \ + SEQ_##regtype##_OUTMH(base, reg, mask, val) + + +/**** Ref Register Field Write ****/ +#define SEQ_OUTFH(base, regtype, reg, fld, val) \ + SEQ_##regtype##_OUTMH(base, reg, HWIO_FMSK(regtype, fld), val << HWIO_SHFT(regtype, fld)) + + +/**** seq_msg() **** + +typedef enum { + DEBUG, + INFO, + WARNING, + ERROR, + FATAL +} SeverityLevel ; + +void seq_msg(SeverityLevel severity, unsigned int msg_id, const char *format_str, ... ); + +*/ + +/************ seq_wait() ************/ + +typedef enum { + SEC, + MS, + US, + NS +} SEQ_TimeUnit; + +extern void seq_wait(uint32 time_value, SEQ_TimeUnit time_unit); + + +/************ seq_poll() ************/ +extern uint32 seq_poll(uint32 reg_offset, uint32 expect_value, uint32 value_mask, uint32 value_shift, uint32 max_poll_cnt); + +#endif /* __SEQ_H__ */ + + + + + + + + + + + + + + + + + + + diff --git a/drivers/staging/fw-api/hw/qca6750/v1/tcl_data_cmd.h b/drivers/staging/fw-api/hw/qca6750/v1/tcl_data_cmd.h new file mode 100644 index 000000000000..0413c1ae79e7 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/tcl_data_cmd.h @@ -0,0 +1,1204 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _TCL_DATA_CMD_H_ +#define _TCL_DATA_CMD_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct buffer_addr_info buf_addr_info; +// 2 buf_or_ext_desc_type[0], epd[1], encap_type[3:2], encrypt_type[7:4], src_buffer_swap[8], link_meta_swap[9], tqm_no_drop[10], reserved_2a[11], search_type[13:12], addrx_en[14], addry_en[15], tcl_cmd_number[31:16] +// 3 data_length[15:0], ipv4_checksum_en[16], udp_over_ipv4_checksum_en[17], udp_over_ipv6_checksum_en[18], tcp_over_ipv4_checksum_en[19], tcp_over_ipv6_checksum_en[20], to_fw[21], reserved_3a[22], packet_offset[31:23] +// 4 buffer_timestamp[18:0], buffer_timestamp_valid[19], reserved_4a[20], hlos_tid_overwrite[21], hlos_tid[25:22], lmac_id[27:26], reserved_4b[31:28] +// 5 dscp_tid_table_num[5:0], search_index[25:6], cache_set_num[29:26], mesh_enable[31:30] +// 6 reserved_6a[19:0], ring_id[27:20], looping_count[31:28] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_TCL_DATA_CMD 7 + +struct tcl_data_cmd { + struct buffer_addr_info buf_addr_info; + uint32_t buf_or_ext_desc_type : 1, //[0] + epd : 1, //[1] + encap_type : 2, //[3:2] + encrypt_type : 4, //[7:4] + src_buffer_swap : 1, //[8] + link_meta_swap : 1, //[9] + tqm_no_drop : 1, //[10] + reserved_2a : 1, //[11] + search_type : 2, //[13:12] + addrx_en : 1, //[14] + addry_en : 1, //[15] + tcl_cmd_number : 16; //[31:16] + uint32_t data_length : 16, //[15:0] + ipv4_checksum_en : 1, //[16] + udp_over_ipv4_checksum_en : 1, //[17] + udp_over_ipv6_checksum_en : 1, //[18] + tcp_over_ipv4_checksum_en : 1, //[19] + tcp_over_ipv6_checksum_en : 1, //[20] + to_fw : 1, //[21] + reserved_3a : 1, //[22] + packet_offset : 9; //[31:23] + uint32_t buffer_timestamp : 19, //[18:0] + buffer_timestamp_valid : 1, //[19] + reserved_4a : 1, //[20] + hlos_tid_overwrite : 1, //[21] + hlos_tid : 4, //[25:22] + lmac_id : 2, //[27:26] + reserved_4b : 4; //[31:28] + uint32_t dscp_tid_table_num : 6, //[5:0] + search_index : 20, //[25:6] + cache_set_num : 4, //[29:26] + mesh_enable : 2; //[31:30] + uint32_t reserved_6a : 20, //[19:0] + ring_id : 8, //[27:20] + looping_count : 4; //[31:28] +}; + +/* + +struct buffer_addr_info buf_addr_info + + Details of the physical address for a single buffer + + It also contains return ownership info as well as some + meta data for SW related to this buffer. + + + + In case of Buf_or_ext_desc_type indicating + 'MSDU_buffer', this address indicates the start of the meta + data that is preceding the actual packet data. + + The start of the actual packet data is provided by + field: Packet_offset + +buf_or_ext_desc_type + + The address points to an MSDU + buffer. + + The address points to an + MSDU link extension descriptor + + < legal all> + +epd + + When this bit is set then input packet is an EPD type + + + +encap_type + + Indicates the encapsulation that HW will perform: + + No encapsulation + + + + Ethernet 2 (DIX) or 802.3 (uses + SNAP/LLC) + + DO NOT USE. Indicate Ethernet + + + + Used by the OLE during encapsulation. + + + +encrypt_type + + Field only valid for encap_type: RAW + + + + Indicates type of decrypt cipher used (as defined in the + peer entry) + + WEP 40-bit + + WEP 104-bit + + TKIP without MIC + + WEP 128-bit + + TKIP with MIC + + WAPI + + AES CCMP 128 + + No crypto + + AES CCMP 256 + + AES CCMP 128 + + AES CCMP 256 + + WAPI GCM SM4 + + + + DO not use... Only for higher + layer modules.. + + + +src_buffer_swap + + Treats source memory (packet buffer) organization as + big-endian. The packets are read and byte swapped. + + 1'b0: Source memory is little endian + + 1'b1: Source memory is big endian + + + +link_meta_swap + + Treats link descriptor and Metadata as big-endian. The + link descriptor/Metadata is read and byte swapped. + + 1'b0: Memory is little endian + + 1'b1: Memory is big endian + + + +tqm_no_drop + + This bit is used to stop TQM from dropping MSDUs while + adding them to MSDU flows1'b1: Do not drop MSDU when any of + the threshold value is met while adding MSDU in a flow1'b1: + Drop MSDU when any of the threshold value is met while + adding MSDU in a flow + + + +reserved_2a + + + +search_type + + Search type select + + + + Address and flow search will use + packet contents + + Address search will + + Flow search will use + 'search_index', and address search will use packet contents + + + +addrx_en + + Address X search enable in ASE + + 1'b0: Search disable + + 1'b1: Search Enable + + + +addry_en + + Address Y search enable in ASE + + 1'b0: Search disable + + 1'b1: Search Enable + + + +tcl_cmd_number + + This number can be used by SW to track, identify and + link the created commands with the command statuses + + + + Is set to the value 'TCL_CMD_Number' of the related + TCL_DATA command + + + +data_length + + Valid Data length in bytes. + + + + MSDU length in case of direct descriptor. + + Length of link extension descriptor in case of Link + extension descriptor. This is used to know the size of + Metadata. + + + +ipv4_checksum_en + + OLE related control + + Enable IPv4 checksum replacement + +udp_over_ipv4_checksum_en + + OLE related control + + Enable UDP over IPv4 checksum replacement. UDP checksum + over IPv4 is optional for TCP/IP stacks. + +udp_over_ipv6_checksum_en + + OLE related control + + Enable UDP over IPv6 checksum replacement. UDP checksum + over IPv6 is mandatory for TCP/IP stacks. + +tcp_over_ipv4_checksum_en + + OLE related control + + Enable TCP checksum over IPv4 replacement + +tcp_over_ipv6_checksum_en + + OLE related control + + Enable TCP checksum over IPv6 replacement + +to_fw + + Forward packet to FW along with classification result. + The packet will not be forward to TQM when this bit is set + + + + 1'b0: Use classification result to forward the packet. + + 1'b1: Override classification result and forward packet + only to FW. + + + +reserved_3a + + + +packet_offset + + Packet offset from Metadata in case of direct buffer + descriptor. This field is valid when Buf_or_ext_desc_type is + reset(= 0). + + + +buffer_timestamp + + Field only valid when 'Buffer_timestamp_valid ' is set. + + + + Frame system entrance timestamp. The timestamp is + related to the global system timer + + + + Generally the first module (SW, TCL or TQM). that sees + this frame and this timestamp field is not valid, shall fill + in this field. + + + + Timestamp in units of 1024 us + +buffer_timestamp_valid + + When set, the Buffer_timestamp field contains valid + info. + +reserved_4a + + + +hlos_tid_overwrite + + When set, TCL shall ignore the IP DSCP and VLAN PCP + fields and use HLOS_TID as the final TID. Otherwise TCL + shall consider the DSCP and PCP fields as well as HLOS_TID + and choose a final TID based on the configured priority + + + +hlos_tid + + HLOS MSDU priority + + + + Field is used when HLOS_TID_overwrite is set. + + + + Field is also used when HLOS_TID_overwrite is not set + and DSCP/PCP is not available in the packet + + + +lmac_id + + TCL uses this LMAC_ID in address search, i.e, while + finding matching entry for the packet in AST corresponding + to given LMAC_ID + + If LMAC ID is all 1s (=> value 3), it indicates wildcard + match for any MAC + + + +reserved_4b + + + +dscp_tid_table_num + + DSCP to TID mapping table number that need to be used + for the MSDU, should be specified using this field + + + +search_index + + The index that will be used for index based address or + flow search. The field is valid when 'search_type' is 1 or + 2. + + + +cache_set_num + + Cache set number that should be used to cache the index + based search results, for address and flow search. This + value should be equal to LSB four bits of the hash value of + match data, in case of search index points to an entry which + may be used in content based search also. The value can be + anything when the entry pointed by search index will not be + used for content based search. + + + +mesh_enable + + If set to a non-zero value: + + * For raw WiFi frames, this indicates transmission to a + mesh STA, enabling the interpretation of the 'Mesh Control + Present' bit (bit 8) of QoS Control (otherwise this bit is + ignored). The interpretation of the A-MSDU 'Length' field is + decided by the e-numerations below. + + * For native WiFi frames, this indicates that a 'Mesh + Control' field is present between the header and the LLC. + The three non-zero values are interchangeable. + + + + + + A-MSDU 'Length' is big endian and + includes the length of Mesh Control. + + A-MSDU 'Length' is big endian and + excludes the length of Mesh Control. + + A-MSDU 'Length' is little endian + and excludes the length of Mesh Control. This is + 802.11s-compliant. + + + +reserved_6a + + + +ring_id + + The buffer pointer ring ID. + + 0 refers to the IDLE ring + + 1 - N refers to other rings + + + + Helps with debugging when dumping ring contents. + + + +looping_count + + A count value that indicates the number of times the + producer of entries into the Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ + + + /* EXTERNAL REFERENCE : struct buffer_addr_info buf_addr_info */ + + +/* Description TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description TCL_DATA_CMD_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + +*/ +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description TCL_DATA_CMD_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define TCL_DATA_CMD_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +/* Description TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE + + The address points to an MSDU + buffer. + + The address points to an + MSDU link extension descriptor + + < legal all> +*/ +#define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 0 +#define TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 0x00000001 + +/* Description TCL_DATA_CMD_2_EPD + + When this bit is set then input packet is an EPD type + + +*/ +#define TCL_DATA_CMD_2_EPD_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_EPD_LSB 1 +#define TCL_DATA_CMD_2_EPD_MASK 0x00000002 + +/* Description TCL_DATA_CMD_2_ENCAP_TYPE + + Indicates the encapsulation that HW will perform: + + No encapsulation + + + + Ethernet 2 (DIX) or 802.3 (uses + SNAP/LLC) + + DO NOT USE. Indicate Ethernet + + + + Used by the OLE during encapsulation. + + +*/ +#define TCL_DATA_CMD_2_ENCAP_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_ENCAP_TYPE_LSB 2 +#define TCL_DATA_CMD_2_ENCAP_TYPE_MASK 0x0000000c + +/* Description TCL_DATA_CMD_2_ENCRYPT_TYPE + + Field only valid for encap_type: RAW + + + + Indicates type of decrypt cipher used (as defined in the + peer entry) + + WEP 40-bit + + WEP 104-bit + + TKIP without MIC + + WEP 128-bit + + TKIP with MIC + + WAPI + + AES CCMP 128 + + No crypto + + AES CCMP 256 + + AES CCMP 128 + + AES CCMP 256 + + WAPI GCM SM4 + + + + DO not use... Only for higher + layer modules.. + + +*/ +#define TCL_DATA_CMD_2_ENCRYPT_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_ENCRYPT_TYPE_LSB 4 +#define TCL_DATA_CMD_2_ENCRYPT_TYPE_MASK 0x000000f0 + +/* Description TCL_DATA_CMD_2_SRC_BUFFER_SWAP + + Treats source memory (packet buffer) organization as + big-endian. The packets are read and byte swapped. + + 1'b0: Source memory is little endian + + 1'b1: Source memory is big endian + + +*/ +#define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_LSB 8 +#define TCL_DATA_CMD_2_SRC_BUFFER_SWAP_MASK 0x00000100 + +/* Description TCL_DATA_CMD_2_LINK_META_SWAP + + Treats link descriptor and Metadata as big-endian. The + link descriptor/Metadata is read and byte swapped. + + 1'b0: Memory is little endian + + 1'b1: Memory is big endian + + +*/ +#define TCL_DATA_CMD_2_LINK_META_SWAP_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_LINK_META_SWAP_LSB 9 +#define TCL_DATA_CMD_2_LINK_META_SWAP_MASK 0x00000200 + +/* Description TCL_DATA_CMD_2_TQM_NO_DROP + + This bit is used to stop TQM from dropping MSDUs while + adding them to MSDU flows1'b1: Do not drop MSDU when any of + the threshold value is met while adding MSDU in a flow1'b1: + Drop MSDU when any of the threshold value is met while + adding MSDU in a flow + + +*/ +#define TCL_DATA_CMD_2_TQM_NO_DROP_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_TQM_NO_DROP_LSB 10 +#define TCL_DATA_CMD_2_TQM_NO_DROP_MASK 0x00000400 + +/* Description TCL_DATA_CMD_2_RESERVED_2A + + +*/ +#define TCL_DATA_CMD_2_RESERVED_2A_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_RESERVED_2A_LSB 11 +#define TCL_DATA_CMD_2_RESERVED_2A_MASK 0x00000800 + +/* Description TCL_DATA_CMD_2_SEARCH_TYPE + + Search type select + + + + Address and flow search will use + packet contents + + Address search will + + Flow search will use + 'search_index', and address search will use packet contents + + +*/ +#define TCL_DATA_CMD_2_SEARCH_TYPE_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_SEARCH_TYPE_LSB 12 +#define TCL_DATA_CMD_2_SEARCH_TYPE_MASK 0x00003000 + +/* Description TCL_DATA_CMD_2_ADDRX_EN + + Address X search enable in ASE + + 1'b0: Search disable + + 1'b1: Search Enable + + +*/ +#define TCL_DATA_CMD_2_ADDRX_EN_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_ADDRX_EN_LSB 14 +#define TCL_DATA_CMD_2_ADDRX_EN_MASK 0x00004000 + +/* Description TCL_DATA_CMD_2_ADDRY_EN + + Address Y search enable in ASE + + 1'b0: Search disable + + 1'b1: Search Enable + + +*/ +#define TCL_DATA_CMD_2_ADDRY_EN_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_ADDRY_EN_LSB 15 +#define TCL_DATA_CMD_2_ADDRY_EN_MASK 0x00008000 + +/* Description TCL_DATA_CMD_2_TCL_CMD_NUMBER + + This number can be used by SW to track, identify and + link the created commands with the command statuses + + + + Is set to the value 'TCL_CMD_Number' of the related + TCL_DATA command + + +*/ +#define TCL_DATA_CMD_2_TCL_CMD_NUMBER_OFFSET 0x00000008 +#define TCL_DATA_CMD_2_TCL_CMD_NUMBER_LSB 16 +#define TCL_DATA_CMD_2_TCL_CMD_NUMBER_MASK 0xffff0000 + +/* Description TCL_DATA_CMD_3_DATA_LENGTH + + Valid Data length in bytes. + + + + MSDU length in case of direct descriptor. + + Length of link extension descriptor in case of Link + extension descriptor. This is used to know the size of + Metadata. + + +*/ +#define TCL_DATA_CMD_3_DATA_LENGTH_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_DATA_LENGTH_LSB 0 +#define TCL_DATA_CMD_3_DATA_LENGTH_MASK 0x0000ffff + +/* Description TCL_DATA_CMD_3_IPV4_CHECKSUM_EN + + OLE related control + + Enable IPv4 checksum replacement +*/ +#define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_LSB 16 +#define TCL_DATA_CMD_3_IPV4_CHECKSUM_EN_MASK 0x00010000 + +/* Description TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN + + OLE related control + + Enable UDP over IPv4 checksum replacement. UDP checksum + over IPv4 is optional for TCP/IP stacks. +*/ +#define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_LSB 17 +#define TCL_DATA_CMD_3_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x00020000 + +/* Description TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN + + OLE related control + + Enable UDP over IPv6 checksum replacement. UDP checksum + over IPv6 is mandatory for TCP/IP stacks. +*/ +#define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_LSB 18 +#define TCL_DATA_CMD_3_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x00040000 + +/* Description TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN + + OLE related control + + Enable TCP checksum over IPv4 replacement +*/ +#define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_LSB 19 +#define TCL_DATA_CMD_3_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x00080000 + +/* Description TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN + + OLE related control + + Enable TCP checksum over IPv6 replacement +*/ +#define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_LSB 20 +#define TCL_DATA_CMD_3_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x00100000 + +/* Description TCL_DATA_CMD_3_TO_FW + + Forward packet to FW along with classification result. + The packet will not be forward to TQM when this bit is set + + + + 1'b0: Use classification result to forward the packet. + + 1'b1: Override classification result and forward packet + only to FW. + + +*/ +#define TCL_DATA_CMD_3_TO_FW_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_TO_FW_LSB 21 +#define TCL_DATA_CMD_3_TO_FW_MASK 0x00200000 + +/* Description TCL_DATA_CMD_3_RESERVED_3A + + +*/ +#define TCL_DATA_CMD_3_RESERVED_3A_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_RESERVED_3A_LSB 22 +#define TCL_DATA_CMD_3_RESERVED_3A_MASK 0x00400000 + +/* Description TCL_DATA_CMD_3_PACKET_OFFSET + + Packet offset from Metadata in case of direct buffer + descriptor. This field is valid when Buf_or_ext_desc_type is + reset(= 0). + + +*/ +#define TCL_DATA_CMD_3_PACKET_OFFSET_OFFSET 0x0000000c +#define TCL_DATA_CMD_3_PACKET_OFFSET_LSB 23 +#define TCL_DATA_CMD_3_PACKET_OFFSET_MASK 0xff800000 + +/* Description TCL_DATA_CMD_4_BUFFER_TIMESTAMP + + Field only valid when 'Buffer_timestamp_valid ' is set. + + + + Frame system entrance timestamp. The timestamp is + related to the global system timer + + + + Generally the first module (SW, TCL or TQM). that sees + this frame and this timestamp field is not valid, shall fill + in this field. + + + + Timestamp in units of 1024 us +*/ +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_LSB 0 +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_MASK 0x0007ffff + +/* Description TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID + + When set, the Buffer_timestamp field contains valid + info. +*/ +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_LSB 19 +#define TCL_DATA_CMD_4_BUFFER_TIMESTAMP_VALID_MASK 0x00080000 + +/* Description TCL_DATA_CMD_4_RESERVED_4A + + +*/ +#define TCL_DATA_CMD_4_RESERVED_4A_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_RESERVED_4A_LSB 20 +#define TCL_DATA_CMD_4_RESERVED_4A_MASK 0x00100000 + +/* Description TCL_DATA_CMD_4_HLOS_TID_OVERWRITE + + When set, TCL shall ignore the IP DSCP and VLAN PCP + fields and use HLOS_TID as the final TID. Otherwise TCL + shall consider the DSCP and PCP fields as well as HLOS_TID + and choose a final TID based on the configured priority + + +*/ +#define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_LSB 21 +#define TCL_DATA_CMD_4_HLOS_TID_OVERWRITE_MASK 0x00200000 + +/* Description TCL_DATA_CMD_4_HLOS_TID + + HLOS MSDU priority + + + + Field is used when HLOS_TID_overwrite is set. + + + + Field is also used when HLOS_TID_overwrite is not set + and DSCP/PCP is not available in the packet + + +*/ +#define TCL_DATA_CMD_4_HLOS_TID_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_HLOS_TID_LSB 22 +#define TCL_DATA_CMD_4_HLOS_TID_MASK 0x03c00000 + +/* Description TCL_DATA_CMD_4_LMAC_ID + + TCL uses this LMAC_ID in address search, i.e, while + finding matching entry for the packet in AST corresponding + to given LMAC_ID + + If LMAC ID is all 1s (=> value 3), it indicates wildcard + match for any MAC + + +*/ +#define TCL_DATA_CMD_4_LMAC_ID_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_LMAC_ID_LSB 26 +#define TCL_DATA_CMD_4_LMAC_ID_MASK 0x0c000000 + +/* Description TCL_DATA_CMD_4_RESERVED_4B + + +*/ +#define TCL_DATA_CMD_4_RESERVED_4B_OFFSET 0x00000010 +#define TCL_DATA_CMD_4_RESERVED_4B_LSB 28 +#define TCL_DATA_CMD_4_RESERVED_4B_MASK 0xf0000000 + +/* Description TCL_DATA_CMD_5_DSCP_TID_TABLE_NUM + + DSCP to TID mapping table number that need to be used + for the MSDU, should be specified using this field + + +*/ +#define TCL_DATA_CMD_5_DSCP_TID_TABLE_NUM_OFFSET 0x00000014 +#define TCL_DATA_CMD_5_DSCP_TID_TABLE_NUM_LSB 0 +#define TCL_DATA_CMD_5_DSCP_TID_TABLE_NUM_MASK 0x0000003f + +/* Description TCL_DATA_CMD_5_SEARCH_INDEX + + The index that will be used for index based address or + flow search. The field is valid when 'search_type' is 1 or + 2. + + +*/ +#define TCL_DATA_CMD_5_SEARCH_INDEX_OFFSET 0x00000014 +#define TCL_DATA_CMD_5_SEARCH_INDEX_LSB 6 +#define TCL_DATA_CMD_5_SEARCH_INDEX_MASK 0x03ffffc0 + +/* Description TCL_DATA_CMD_5_CACHE_SET_NUM + + Cache set number that should be used to cache the index + based search results, for address and flow search. This + value should be equal to LSB four bits of the hash value of + match data, in case of search index points to an entry which + may be used in content based search also. The value can be + anything when the entry pointed by search index will not be + used for content based search. + + +*/ +#define TCL_DATA_CMD_5_CACHE_SET_NUM_OFFSET 0x00000014 +#define TCL_DATA_CMD_5_CACHE_SET_NUM_LSB 26 +#define TCL_DATA_CMD_5_CACHE_SET_NUM_MASK 0x3c000000 + +/* Description TCL_DATA_CMD_5_MESH_ENABLE + + If set to a non-zero value: + + * For raw WiFi frames, this indicates transmission to a + mesh STA, enabling the interpretation of the 'Mesh Control + Present' bit (bit 8) of QoS Control (otherwise this bit is + ignored). The interpretation of the A-MSDU 'Length' field is + decided by the e-numerations below. + + * For native WiFi frames, this indicates that a 'Mesh + Control' field is present between the header and the LLC. + The three non-zero values are interchangeable. + + + + + + A-MSDU 'Length' is big endian and + includes the length of Mesh Control. + + A-MSDU 'Length' is big endian and + excludes the length of Mesh Control. + + A-MSDU 'Length' is little endian + and excludes the length of Mesh Control. This is + 802.11s-compliant. + + +*/ +#define TCL_DATA_CMD_5_MESH_ENABLE_OFFSET 0x00000014 +#define TCL_DATA_CMD_5_MESH_ENABLE_LSB 30 +#define TCL_DATA_CMD_5_MESH_ENABLE_MASK 0xc0000000 + +/* Description TCL_DATA_CMD_6_RESERVED_6A + + +*/ +#define TCL_DATA_CMD_6_RESERVED_6A_OFFSET 0x00000018 +#define TCL_DATA_CMD_6_RESERVED_6A_LSB 0 +#define TCL_DATA_CMD_6_RESERVED_6A_MASK 0x000fffff + +/* Description TCL_DATA_CMD_6_RING_ID + + The buffer pointer ring ID. + + 0 refers to the IDLE ring + + 1 - N refers to other rings + + + + Helps with debugging when dumping ring contents. + + +*/ +#define TCL_DATA_CMD_6_RING_ID_OFFSET 0x00000018 +#define TCL_DATA_CMD_6_RING_ID_LSB 20 +#define TCL_DATA_CMD_6_RING_ID_MASK 0x0ff00000 + +/* Description TCL_DATA_CMD_6_LOOPING_COUNT + + A count value that indicates the number of times the + producer of entries into the Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ +#define TCL_DATA_CMD_6_LOOPING_COUNT_OFFSET 0x00000018 +#define TCL_DATA_CMD_6_LOOPING_COUNT_LSB 28 +#define TCL_DATA_CMD_6_LOOPING_COUNT_MASK 0xf0000000 + + +#endif // _TCL_DATA_CMD_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/tcl_gse_cmd.h b/drivers/staging/fw-api/hw/qca6750/v1/tcl_gse_cmd.h new file mode 100644 index 000000000000..f674fc5bd8bb --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/tcl_gse_cmd.h @@ -0,0 +1,473 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _TCL_GSE_CMD_H_ +#define _TCL_GSE_CMD_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 control_buffer_addr_31_0[31:0] +// 1 control_buffer_addr_39_32[7:0], gse_ctrl[11:8], gse_sel[12], status_destination_ring_id[13], swap[14], index_search_en[15], cache_set_num[19:16], reserved_1a[31:20] +// 2 cmd_meta_data_31_0[31:0] +// 3 cmd_meta_data_63_32[31:0] +// 4 reserved_4a[31:0] +// 5 reserved_5a[31:0] +// 6 reserved_6a[19:0], ring_id[27:20], looping_count[31:28] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_TCL_GSE_CMD 7 + +struct tcl_gse_cmd { + uint32_t control_buffer_addr_31_0 : 32; //[31:0] + uint32_t control_buffer_addr_39_32 : 8, //[7:0] + gse_ctrl : 4, //[11:8] + gse_sel : 1, //[12] + status_destination_ring_id : 1, //[13] + swap : 1, //[14] + index_search_en : 1, //[15] + cache_set_num : 4, //[19:16] + reserved_1a : 12; //[31:20] + uint32_t cmd_meta_data_31_0 : 32; //[31:0] + uint32_t cmd_meta_data_63_32 : 32; //[31:0] + uint32_t reserved_4a : 32; //[31:0] + uint32_t reserved_5a : 32; //[31:0] + uint32_t reserved_6a : 20, //[19:0] + ring_id : 8, //[27:20] + looping_count : 4; //[31:28] +}; + +/* + +control_buffer_addr_31_0 + + Address (lower 32 bits) of a control buffer containing + additional info needed for this command execution. + + + +control_buffer_addr_39_32 + + Address (upper 8 bits) of a control buffer containing + additional info needed for this command execution. + + + +gse_ctrl + + GSE control operations. This includes cache operations + and table entry statistics read/clear operation. + + Report or Read statistics + + Search disable. Report only Hash + + Write Back single entry + + Write Back entire cache entry + + Invalidate single cache entry + + Invalidate entire cache + + Write back and Invalidate + single entry in cache + + write back and invalidate + entire cache + + Clear statistics for single + entry + + + + Rest of the values reserved. + + For all single entry control operations (write back, + Invalidate or both)Statistics will be reported + +gse_sel + + Bit to select the ASE or FSE to do the operation mention + by GSE_ctrl bit + + 0: FSE select + + 1: ASE select + +status_destination_ring_id + + The TCL status ring to which the GSE status needs to be + send. + + + + + + + + + + + +swap + + Bit to enable byte swapping of contents of buffer + + + + + + + +index_search_en + + When this bit is set to 1 control_buffer_addr[19:0] will + be considered as index of the AST or Flow table and GSE + commands will be executed accordingly on the entry pointed + by the index. + + This feature is disabled by setting this bit to 0. + + + + + + + + + +cache_set_num + + Cache set number that should be used to cache the index + based search results, for address and flow search. This + value should be equal to value of cache_set_num for the + index that is issued in TCL_DATA_CMD during search index + based ASE or FSE. This field is valid for index based GSE + commands + + + +reserved_1a + + + +cmd_meta_data_31_0 + + Meta data to be returned in the status descriptor + + + +cmd_meta_data_63_32 + + Meta data to be returned in the status descriptor + + + +reserved_4a + + + +reserved_5a + + + +reserved_6a + + + +ring_id + + Helps with debugging when dumping ring contents. + + + +looping_count + + A count value that indicates the number of times the + producer of entries into the Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ + + +/* Description TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of a control buffer containing + additional info needed for this command execution. + + +*/ +#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_LSB 0 +#define TCL_GSE_CMD_0_CONTROL_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of a control buffer containing + additional info needed for this command execution. + + +*/ +#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_LSB 0 +#define TCL_GSE_CMD_1_CONTROL_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description TCL_GSE_CMD_1_GSE_CTRL + + GSE control operations. This includes cache operations + and table entry statistics read/clear operation. + + Report or Read statistics + + Search disable. Report only Hash + + Write Back single entry + + Write Back entire cache entry + + Invalidate single cache entry + + Invalidate entire cache + + Write back and Invalidate + single entry in cache + + write back and invalidate + entire cache + + Clear statistics for single + entry + + + + Rest of the values reserved. + + For all single entry control operations (write back, + Invalidate or both)Statistics will be reported +*/ +#define TCL_GSE_CMD_1_GSE_CTRL_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_GSE_CTRL_LSB 8 +#define TCL_GSE_CMD_1_GSE_CTRL_MASK 0x00000f00 + +/* Description TCL_GSE_CMD_1_GSE_SEL + + Bit to select the ASE or FSE to do the operation mention + by GSE_ctrl bit + + 0: FSE select + + 1: ASE select +*/ +#define TCL_GSE_CMD_1_GSE_SEL_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_GSE_SEL_LSB 12 +#define TCL_GSE_CMD_1_GSE_SEL_MASK 0x00001000 + +/* Description TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID + + The TCL status ring to which the GSE status needs to be + send. + + + + + + + + + + +*/ +#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_LSB 13 +#define TCL_GSE_CMD_1_STATUS_DESTINATION_RING_ID_MASK 0x00002000 + +/* Description TCL_GSE_CMD_1_SWAP + + Bit to enable byte swapping of contents of buffer + + + + + + +*/ +#define TCL_GSE_CMD_1_SWAP_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_SWAP_LSB 14 +#define TCL_GSE_CMD_1_SWAP_MASK 0x00004000 + +/* Description TCL_GSE_CMD_1_INDEX_SEARCH_EN + + When this bit is set to 1 control_buffer_addr[19:0] will + be considered as index of the AST or Flow table and GSE + commands will be executed accordingly on the entry pointed + by the index. + + This feature is disabled by setting this bit to 0. + + + + + + + + +*/ +#define TCL_GSE_CMD_1_INDEX_SEARCH_EN_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_INDEX_SEARCH_EN_LSB 15 +#define TCL_GSE_CMD_1_INDEX_SEARCH_EN_MASK 0x00008000 + +/* Description TCL_GSE_CMD_1_CACHE_SET_NUM + + Cache set number that should be used to cache the index + based search results, for address and flow search. This + value should be equal to value of cache_set_num for the + index that is issued in TCL_DATA_CMD during search index + based ASE or FSE. This field is valid for index based GSE + commands + + +*/ +#define TCL_GSE_CMD_1_CACHE_SET_NUM_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_CACHE_SET_NUM_LSB 16 +#define TCL_GSE_CMD_1_CACHE_SET_NUM_MASK 0x000f0000 + +/* Description TCL_GSE_CMD_1_RESERVED_1A + + +*/ +#define TCL_GSE_CMD_1_RESERVED_1A_OFFSET 0x00000004 +#define TCL_GSE_CMD_1_RESERVED_1A_LSB 20 +#define TCL_GSE_CMD_1_RESERVED_1A_MASK 0xfff00000 + +/* Description TCL_GSE_CMD_2_CMD_META_DATA_31_0 + + Meta data to be returned in the status descriptor + + +*/ +#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_OFFSET 0x00000008 +#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_LSB 0 +#define TCL_GSE_CMD_2_CMD_META_DATA_31_0_MASK 0xffffffff + +/* Description TCL_GSE_CMD_3_CMD_META_DATA_63_32 + + Meta data to be returned in the status descriptor + + +*/ +#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_OFFSET 0x0000000c +#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_LSB 0 +#define TCL_GSE_CMD_3_CMD_META_DATA_63_32_MASK 0xffffffff + +/* Description TCL_GSE_CMD_4_RESERVED_4A + + +*/ +#define TCL_GSE_CMD_4_RESERVED_4A_OFFSET 0x00000010 +#define TCL_GSE_CMD_4_RESERVED_4A_LSB 0 +#define TCL_GSE_CMD_4_RESERVED_4A_MASK 0xffffffff + +/* Description TCL_GSE_CMD_5_RESERVED_5A + + +*/ +#define TCL_GSE_CMD_5_RESERVED_5A_OFFSET 0x00000014 +#define TCL_GSE_CMD_5_RESERVED_5A_LSB 0 +#define TCL_GSE_CMD_5_RESERVED_5A_MASK 0xffffffff + +/* Description TCL_GSE_CMD_6_RESERVED_6A + + +*/ +#define TCL_GSE_CMD_6_RESERVED_6A_OFFSET 0x00000018 +#define TCL_GSE_CMD_6_RESERVED_6A_LSB 0 +#define TCL_GSE_CMD_6_RESERVED_6A_MASK 0x000fffff + +/* Description TCL_GSE_CMD_6_RING_ID + + Helps with debugging when dumping ring contents. + + +*/ +#define TCL_GSE_CMD_6_RING_ID_OFFSET 0x00000018 +#define TCL_GSE_CMD_6_RING_ID_LSB 20 +#define TCL_GSE_CMD_6_RING_ID_MASK 0x0ff00000 + +/* Description TCL_GSE_CMD_6_LOOPING_COUNT + + A count value that indicates the number of times the + producer of entries into the Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ +#define TCL_GSE_CMD_6_LOOPING_COUNT_OFFSET 0x00000018 +#define TCL_GSE_CMD_6_LOOPING_COUNT_LSB 28 +#define TCL_GSE_CMD_6_LOOPING_COUNT_MASK 0xf0000000 + + +#endif // _TCL_GSE_CMD_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/tcl_status_ring.h b/drivers/staging/fw-api/hw/qca6750/v1/tcl_status_ring.h new file mode 100644 index 000000000000..a5306408bd0c --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/tcl_status_ring.h @@ -0,0 +1,452 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _TCL_STATUS_RING_H_ +#define _TCL_STATUS_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 gse_ctrl[3:0], ase_fse_sel[4], cache_op_res[6:5], index_search_en[7], msdu_cnt_n[31:8] +// 1 msdu_byte_cnt_n[31:0] +// 2 msdu_timestmp_n[31:0] +// 3 cmd_meta_data_31_0[31:0] +// 4 cmd_meta_data_63_32[31:0] +// 5 hash_indx_val[19:0], cache_set_num[23:20], reserved_5a[31:24] +// 6 reserved_6a[31:0] +// 7 reserved_7a[19:0], ring_id[27:20], looping_count[31:28] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_TCL_STATUS_RING 8 + +struct tcl_status_ring { + uint32_t gse_ctrl : 4, //[3:0] + ase_fse_sel : 1, //[4] + cache_op_res : 2, //[6:5] + index_search_en : 1, //[7] + msdu_cnt_n : 24; //[31:8] + uint32_t msdu_byte_cnt_n : 32; //[31:0] + uint32_t msdu_timestmp_n : 32; //[31:0] + uint32_t cmd_meta_data_31_0 : 32; //[31:0] + uint32_t cmd_meta_data_63_32 : 32; //[31:0] + uint32_t hash_indx_val : 20, //[19:0] + cache_set_num : 4, //[23:20] + reserved_5a : 8; //[31:24] + uint32_t reserved_6a : 32; //[31:0] + uint32_t reserved_7a : 20, //[19:0] + ring_id : 8, //[27:20] + looping_count : 4; //[31:28] +}; + +/* + +gse_ctrl + + GSE control operations. This includes cache operations + and table entry statistics read/clear operation. + + Report or Read statistics + + Search disable. Report only Hash + + Write Back single entry + + Write Back entire cache entry + + Invalidate single cache entry + + Invalidate entire cache + + Write back and Invalidate + single entry in cache + + write back and invalidate + entire cache + + Clear statistics for single + entry + + + + Rest of the values reserved. + + For all single entry control operations (write back, + Invalidate or both)Statistics will be reported + +ase_fse_sel + + Search Engine for which operation is done. + + 1'b0: Address Search Engine Result + + 1'b1: Flow Search Engine result + +cache_op_res + + Cache operation result. Following are results of cache + operation. + + Operation successful + + Entry not found in Table + + Timeout Error + + + +index_search_en + + When this bit is set to 1 control_buffer_addr[19:0] will + be considered as index of the AST or Flow table and GSE + commands will be executed accordingly on the entry pointed + by the index. + + This feature is disabled by setting this bit to 0. + + + + + + + + + +msdu_cnt_n + + MSDU count of Entry. Valid when GSE_CTRL is 4'b0111 and + 4'b1000 + +msdu_byte_cnt_n + + MSDU byte count for entry 1. Valid when GSE_CTRL is + 4'b0111 and 4'b1000 + +msdu_timestmp_n + + MSDU timestamp for entry 1. Valid when GSE_CTRL is + 4'b0111 and 4'b1000 + +cmd_meta_data_31_0 + + Meta data from input ring + + + +cmd_meta_data_63_32 + + Meta data from input ring + + + +hash_indx_val + + + Hash value of the entry in table in case of search + failed or search disable. + + + +cache_set_num + + Cache set number copied from TCL_GSE_CMD + +reserved_5a + + + +reserved_6a + + + +reserved_7a + + + +ring_id + + The buffer pointer ring ID. + + + + Helps with debugging when dumping ring contents. + + + +looping_count + + A count value that indicates the number of times the + producer of entries into the Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ + + +/* Description TCL_STATUS_RING_0_GSE_CTRL + + GSE control operations. This includes cache operations + and table entry statistics read/clear operation. + + Report or Read statistics + + Search disable. Report only Hash + + Write Back single entry + + Write Back entire cache entry + + Invalidate single cache entry + + Invalidate entire cache + + Write back and Invalidate + single entry in cache + + write back and invalidate + entire cache + + Clear statistics for single + entry + + + + Rest of the values reserved. + + For all single entry control operations (write back, + Invalidate or both)Statistics will be reported +*/ +#define TCL_STATUS_RING_0_GSE_CTRL_OFFSET 0x00000000 +#define TCL_STATUS_RING_0_GSE_CTRL_LSB 0 +#define TCL_STATUS_RING_0_GSE_CTRL_MASK 0x0000000f + +/* Description TCL_STATUS_RING_0_ASE_FSE_SEL + + Search Engine for which operation is done. + + 1'b0: Address Search Engine Result + + 1'b1: Flow Search Engine result +*/ +#define TCL_STATUS_RING_0_ASE_FSE_SEL_OFFSET 0x00000000 +#define TCL_STATUS_RING_0_ASE_FSE_SEL_LSB 4 +#define TCL_STATUS_RING_0_ASE_FSE_SEL_MASK 0x00000010 + +/* Description TCL_STATUS_RING_0_CACHE_OP_RES + + Cache operation result. Following are results of cache + operation. + + Operation successful + + Entry not found in Table + + Timeout Error + + +*/ +#define TCL_STATUS_RING_0_CACHE_OP_RES_OFFSET 0x00000000 +#define TCL_STATUS_RING_0_CACHE_OP_RES_LSB 5 +#define TCL_STATUS_RING_0_CACHE_OP_RES_MASK 0x00000060 + +/* Description TCL_STATUS_RING_0_INDEX_SEARCH_EN + + When this bit is set to 1 control_buffer_addr[19:0] will + be considered as index of the AST or Flow table and GSE + commands will be executed accordingly on the entry pointed + by the index. + + This feature is disabled by setting this bit to 0. + + + + + + + + +*/ +#define TCL_STATUS_RING_0_INDEX_SEARCH_EN_OFFSET 0x00000000 +#define TCL_STATUS_RING_0_INDEX_SEARCH_EN_LSB 7 +#define TCL_STATUS_RING_0_INDEX_SEARCH_EN_MASK 0x00000080 + +/* Description TCL_STATUS_RING_0_MSDU_CNT_N + + MSDU count of Entry. Valid when GSE_CTRL is 4'b0111 and + 4'b1000 +*/ +#define TCL_STATUS_RING_0_MSDU_CNT_N_OFFSET 0x00000000 +#define TCL_STATUS_RING_0_MSDU_CNT_N_LSB 8 +#define TCL_STATUS_RING_0_MSDU_CNT_N_MASK 0xffffff00 + +/* Description TCL_STATUS_RING_1_MSDU_BYTE_CNT_N + + MSDU byte count for entry 1. Valid when GSE_CTRL is + 4'b0111 and 4'b1000 +*/ +#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_OFFSET 0x00000004 +#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_LSB 0 +#define TCL_STATUS_RING_1_MSDU_BYTE_CNT_N_MASK 0xffffffff + +/* Description TCL_STATUS_RING_2_MSDU_TIMESTMP_N + + MSDU timestamp for entry 1. Valid when GSE_CTRL is + 4'b0111 and 4'b1000 +*/ +#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_OFFSET 0x00000008 +#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_LSB 0 +#define TCL_STATUS_RING_2_MSDU_TIMESTMP_N_MASK 0xffffffff + +/* Description TCL_STATUS_RING_3_CMD_META_DATA_31_0 + + Meta data from input ring + + +*/ +#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_OFFSET 0x0000000c +#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_LSB 0 +#define TCL_STATUS_RING_3_CMD_META_DATA_31_0_MASK 0xffffffff + +/* Description TCL_STATUS_RING_4_CMD_META_DATA_63_32 + + Meta data from input ring + + +*/ +#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_OFFSET 0x00000010 +#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_LSB 0 +#define TCL_STATUS_RING_4_CMD_META_DATA_63_32_MASK 0xffffffff + +/* Description TCL_STATUS_RING_5_HASH_INDX_VAL + + + Hash value of the entry in table in case of search + failed or search disable. + + +*/ +#define TCL_STATUS_RING_5_HASH_INDX_VAL_OFFSET 0x00000014 +#define TCL_STATUS_RING_5_HASH_INDX_VAL_LSB 0 +#define TCL_STATUS_RING_5_HASH_INDX_VAL_MASK 0x000fffff + +/* Description TCL_STATUS_RING_5_CACHE_SET_NUM + + Cache set number copied from TCL_GSE_CMD +*/ +#define TCL_STATUS_RING_5_CACHE_SET_NUM_OFFSET 0x00000014 +#define TCL_STATUS_RING_5_CACHE_SET_NUM_LSB 20 +#define TCL_STATUS_RING_5_CACHE_SET_NUM_MASK 0x00f00000 + +/* Description TCL_STATUS_RING_5_RESERVED_5A + + +*/ +#define TCL_STATUS_RING_5_RESERVED_5A_OFFSET 0x00000014 +#define TCL_STATUS_RING_5_RESERVED_5A_LSB 24 +#define TCL_STATUS_RING_5_RESERVED_5A_MASK 0xff000000 + +/* Description TCL_STATUS_RING_6_RESERVED_6A + + +*/ +#define TCL_STATUS_RING_6_RESERVED_6A_OFFSET 0x00000018 +#define TCL_STATUS_RING_6_RESERVED_6A_LSB 0 +#define TCL_STATUS_RING_6_RESERVED_6A_MASK 0xffffffff + +/* Description TCL_STATUS_RING_7_RESERVED_7A + + +*/ +#define TCL_STATUS_RING_7_RESERVED_7A_OFFSET 0x0000001c +#define TCL_STATUS_RING_7_RESERVED_7A_LSB 0 +#define TCL_STATUS_RING_7_RESERVED_7A_MASK 0x000fffff + +/* Description TCL_STATUS_RING_7_RING_ID + + The buffer pointer ring ID. + + + + Helps with debugging when dumping ring contents. + + +*/ +#define TCL_STATUS_RING_7_RING_ID_OFFSET 0x0000001c +#define TCL_STATUS_RING_7_RING_ID_LSB 20 +#define TCL_STATUS_RING_7_RING_ID_MASK 0x0ff00000 + +/* Description TCL_STATUS_RING_7_LOOPING_COUNT + + A count value that indicates the number of times the + producer of entries into the Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ +#define TCL_STATUS_RING_7_LOOPING_COUNT_OFFSET 0x0000001c +#define TCL_STATUS_RING_7_LOOPING_COUNT_LSB 28 +#define TCL_STATUS_RING_7_LOOPING_COUNT_MASK 0xf0000000 + + +#endif // _TCL_STATUS_RING_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/tlv_hdr.h b/drivers/staging/fw-api/hw/qca6750/v1/tlv_hdr.h new file mode 100644 index 000000000000..0e9f29b705af --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/tlv_hdr.h @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + +#ifndef _TLV_HDR_H_ +#define _TLV_HDR_H_ +#if !defined(__ASSEMBLER__) +#endif + +struct tlv_usr_16_hdr { + volatile uint16_t tlv_cflg_reserved : 1, + tlv_tag : 5, + tlv_len : 4, + tlv_usrid : 6; +}; + +struct tlv_16_hdr { + volatile uint16_t tlv_cflg_reserved : 1, + tlv_tag : 5, + tlv_len : 4, + tlv_reserved : 6; +}; + +struct tlv_usr_32_hdr { + volatile uint32_t tlv_cflg_reserved : 1, + tlv_tag : 9, + tlv_len : 16, + tlv_usrid : 6; +}; + +struct tlv_32_hdr { + volatile uint32_t tlv_cflg_reserved : 1, + tlv_tag : 9, + tlv_len : 16, + tlv_reserved : 6; +}; + +struct tlv_usr_42_hdr { + volatile uint64_t tlv_compression : 1, + tlv_tag : 9, + tlv_len : 16, + tlv_usrid : 6, + tlv_reserved : 10, + pad_42to64_bit : 22; +}; + +struct tlv_42_hdr { + volatile uint64_t tlv_compression : 1, + tlv_tag : 9, + tlv_len : 16, + tlv_reserved : 16, + pad_42to64_bit : 22; +}; + +struct tlv_usr_c_42_hdr { + volatile uint64_t tlv_compression : 1, + tlv_ctag : 3, + tlv_usrid : 6, + tlv_cdata : 32, + pad_42to64_bit : 22; +}; + +#endif diff --git a/drivers/staging/fw-api/hw/qca6750/v1/tlv_tag_def.h b/drivers/staging/fw-api/hw/qca6750/v1/tlv_tag_def.h new file mode 100644 index 000000000000..9f5ed20d54ae --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/tlv_tag_def.h @@ -0,0 +1,517 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/** + * Generated file ... Do not hand edit ... + */ + +#ifndef _TLV_TAG_DEF_ +#define _TLV_TAG_DEF_ + +typedef enum { + + WIFIMACTX_CBF_START_E = 0 /* 0x0 */, + WIFIPHYRX_DATA_E = 1 /* 0x1 */, + WIFIPHYRX_CBF_DATA_RESP_E = 2 /* 0x2 */, + WIFIPHYRX_ABORT_REQUEST_E = 3 /* 0x3 */, + WIFIPHYRX_USER_ABORT_NOTIFICATION_E = 4 /* 0x4 */, + WIFIMACTX_DATA_RESP_E = 5 /* 0x5 */, + WIFIMACTX_CBF_DATA_E = 6 /* 0x6 */, + WIFIMACTX_CBF_DONE_E = 7 /* 0x7 */, + WIFIMACRX_CBF_READ_REQUEST_E = 8 /* 0x8 */, + WIFIMACRX_CBF_DATA_REQUEST_E = 9 /* 0x9 */, + WIFIMACRX_EXPECT_NDP_RECEPTION_E = 10 /* 0xa */, + WIFIMACRX_FREEZE_CAPTURE_CHANNEL_E = 11 /* 0xb */, + WIFIMACRX_NDP_TIMEOUT_E = 12 /* 0xc */, + WIFIMACRX_ABORT_ACK_E = 13 /* 0xd */, + WIFIMACRX_REQ_IMPLICIT_FB_E = 14 /* 0xe */, + WIFIMACRX_CHAIN_MASK_E = 15 /* 0xf */, + WIFIMACRX_NAP_USER_E = 16 /* 0x10 */, + WIFIMACRX_ABORT_REQUEST_E = 17 /* 0x11 */, + WIFIPHYTX_OTHER_TRANSMIT_INFO16_E = 18 /* 0x12 */, + WIFIPHYTX_ABORT_ACK_E = 19 /* 0x13 */, + WIFIPHYTX_ABORT_REQUEST_E = 20 /* 0x14 */, + WIFIPHYTX_PKT_END_E = 21 /* 0x15 */, + WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E = 22 /* 0x16 */, + WIFIPHYTX_REQUEST_CTRL_INFO_E = 23 /* 0x17 */, + WIFIPHYTX_DATA_REQUEST_E = 24 /* 0x18 */, + WIFIPHYTX_BF_CV_LOADING_DONE_E = 25 /* 0x19 */, + WIFIPHYTX_NAP_ACK_E = 26 /* 0x1a */, + WIFIPHYTX_NAP_DONE_E = 27 /* 0x1b */, + WIFIPHYTX_OFF_ACK_E = 28 /* 0x1c */, + WIFIPHYTX_ON_ACK_E = 29 /* 0x1d */, + WIFIPHYTX_SYNTH_OFF_ACK_E = 30 /* 0x1e */, + WIFIPHYTX_DEBUG16_E = 31 /* 0x1f */, + WIFIMACTX_ABORT_REQUEST_E = 32 /* 0x20 */, + WIFIMACTX_ABORT_ACK_E = 33 /* 0x21 */, + WIFIMACTX_PKT_END_E = 34 /* 0x22 */, + WIFIMACTX_PRE_PHY_DESC_E = 35 /* 0x23 */, + WIFIMACTX_BF_PARAMS_COMMON_E = 36 /* 0x24 */, + WIFIMACTX_BF_PARAMS_PER_USER_E = 37 /* 0x25 */, + WIFIMACTX_PREFETCH_CV_E = 38 /* 0x26 */, + WIFIMACTX_USER_DESC_COMMON_E = 39 /* 0x27 */, + WIFIMACTX_USER_DESC_PER_USER_E = 40 /* 0x28 */, + WIFIEXAMPLE_USER_TLV_16_E = 41 /* 0x29 */, + WIFIEXAMPLE_TLV_16_E = 42 /* 0x2a */, + WIFIMACTX_PHY_OFF_E = 43 /* 0x2b */, + WIFIMACTX_PHY_ON_E = 44 /* 0x2c */, + WIFIMACTX_SYNTH_OFF_E = 45 /* 0x2d */, + WIFIMACTX_EXPECT_CBF_COMMON_E = 46 /* 0x2e */, + WIFIMACTX_EXPECT_CBF_PER_USER_E = 47 /* 0x2f */, + WIFIMACTX_PHY_DESC_E = 48 /* 0x30 */, + WIFIMACTX_L_SIG_A_E = 49 /* 0x31 */, + WIFIMACTX_L_SIG_B_E = 50 /* 0x32 */, + WIFIMACTX_HT_SIG_E = 51 /* 0x33 */, + WIFIMACTX_VHT_SIG_A_E = 52 /* 0x34 */, + WIFIMACTX_VHT_SIG_B_SU20_E = 53 /* 0x35 */, + WIFIMACTX_VHT_SIG_B_SU40_E = 54 /* 0x36 */, + WIFIMACTX_VHT_SIG_B_SU80_E = 55 /* 0x37 */, + WIFIMACTX_VHT_SIG_B_SU160_E = 56 /* 0x38 */, + WIFIMACTX_VHT_SIG_B_MU20_E = 57 /* 0x39 */, + WIFIMACTX_VHT_SIG_B_MU40_E = 58 /* 0x3a */, + WIFIMACTX_VHT_SIG_B_MU80_E = 59 /* 0x3b */, + WIFIMACTX_VHT_SIG_B_MU160_E = 60 /* 0x3c */, + WIFIMACTX_SERVICE_E = 61 /* 0x3d */, + WIFIMACTX_HE_SIG_A_SU_E = 62 /* 0x3e */, + WIFIMACTX_HE_SIG_A_MU_DL_E = 63 /* 0x3f */, + WIFIMACTX_HE_SIG_A_MU_UL_E = 64 /* 0x40 */, + WIFIMACTX_HE_SIG_B1_MU_E = 65 /* 0x41 */, + WIFIMACTX_HE_SIG_B2_MU_E = 66 /* 0x42 */, + WIFIMACTX_HE_SIG_B2_OFDMA_E = 67 /* 0x43 */, + WIFIMACTX_DELETE_CV_E = 68 /* 0x44 */, + WIFIMACTX_MU_UPLINK_COMMON_E = 69 /* 0x45 */, + WIFIMACTX_MU_UPLINK_USER_SETUP_E = 70 /* 0x46 */, + WIFIMACTX_OTHER_TRANSMIT_INFO_E = 71 /* 0x47 */, + WIFIMACTX_PHY_NAP_E = 72 /* 0x48 */, + WIFIMACTX_DEBUG_E = 73 /* 0x49 */, + WIFIPHYRX_ABORT_ACK_E = 74 /* 0x4a */, + WIFIPHYRX_GENERATED_CBF_DETAILS_E = 75 /* 0x4b */, + WIFIPHYRX_RSSI_LEGACY_E = 76 /* 0x4c */, + WIFIPHYRX_RSSI_HT_E = 77 /* 0x4d */, + WIFIPHYRX_USER_INFO_E = 78 /* 0x4e */, + WIFIPHYRX_PKT_END_E = 79 /* 0x4f */, + WIFIPHYRX_DEBUG_E = 80 /* 0x50 */, + WIFIPHYRX_CBF_TRANSFER_DONE_E = 81 /* 0x51 */, + WIFIPHYRX_CBF_TRANSFER_ABORT_E = 82 /* 0x52 */, + WIFIPHYRX_L_SIG_A_E = 83 /* 0x53 */, + WIFIPHYRX_L_SIG_B_E = 84 /* 0x54 */, + WIFIPHYRX_HT_SIG_E = 85 /* 0x55 */, + WIFIPHYRX_VHT_SIG_A_E = 86 /* 0x56 */, + WIFIPHYRX_VHT_SIG_B_SU20_E = 87 /* 0x57 */, + WIFIPHYRX_VHT_SIG_B_SU40_E = 88 /* 0x58 */, + WIFIPHYRX_VHT_SIG_B_SU80_E = 89 /* 0x59 */, + WIFIPHYRX_VHT_SIG_B_SU160_E = 90 /* 0x5a */, + WIFIPHYRX_VHT_SIG_B_MU20_E = 91 /* 0x5b */, + WIFIPHYRX_VHT_SIG_B_MU40_E = 92 /* 0x5c */, + WIFIPHYRX_VHT_SIG_B_MU80_E = 93 /* 0x5d */, + WIFIPHYRX_VHT_SIG_B_MU160_E = 94 /* 0x5e */, + WIFIPHYRX_HE_SIG_A_SU_E = 95 /* 0x5f */, + WIFIPHYRX_HE_SIG_A_MU_DL_E = 96 /* 0x60 */, + WIFIPHYRX_HE_SIG_A_MU_UL_E = 97 /* 0x61 */, + WIFIPHYRX_HE_SIG_B1_MU_E = 98 /* 0x62 */, + WIFIPHYRX_HE_SIG_B2_MU_E = 99 /* 0x63 */, + WIFIPHYRX_HE_SIG_B2_OFDMA_E = 100 /* 0x64 */, + WIFIPHYRX_OTHER_RECEIVE_INFO_E = 101 /* 0x65 */, + WIFIPHYRX_COMMON_USER_INFO_E = 102 /* 0x66 */, + WIFIPHYRX_DATA_DONE_E = 103 /* 0x67 */, + WIFIRECEIVE_RSSI_INFO_E = 104 /* 0x68 */, + WIFIRECEIVE_USER_INFO_E = 105 /* 0x69 */, + WIFIMIMO_CONTROL_INFO_E = 106 /* 0x6a */, + WIFIRX_LOCATION_INFO_E = 107 /* 0x6b */, + WIFICOEX_TX_REQ_E = 108 /* 0x6c */, + WIFIDUMMY_E = 109 /* 0x6d */, + WIFIRX_TIMING_OFFSET_INFO_E = 110 /* 0x6e */, + WIFIEXAMPLE_TLV_32_NAME_E = 111 /* 0x6f */, + WIFIMPDU_LIMIT_E = 112 /* 0x70 */, + WIFINA_LENGTH_END_E = 113 /* 0x71 */, + WIFIOLE_BUF_STATUS_E = 114 /* 0x72 */, + WIFIPCU_PPDU_SETUP_DONE_E = 115 /* 0x73 */, + WIFIPCU_PPDU_SETUP_END_E = 116 /* 0x74 */, + WIFIPCU_PPDU_SETUP_INIT_E = 117 /* 0x75 */, + WIFIPCU_PPDU_SETUP_START_E = 118 /* 0x76 */, + WIFIPDG_FES_SETUP_E = 119 /* 0x77 */, + WIFIPDG_RESPONSE_E = 120 /* 0x78 */, + WIFIPDG_TX_REQ_E = 121 /* 0x79 */, + WIFISCH_WAIT_INSTR_E = 122 /* 0x7a */, + WIFISCHEDULER_TLV_E = 123 /* 0x7b */, + WIFITQM_FLOW_EMPTY_STATUS_E = 124 /* 0x7c */, + WIFITQM_FLOW_NOT_EMPTY_STATUS_E = 125 /* 0x7d */, + WIFITQM_GEN_MPDU_LENGTH_LIST_E = 126 /* 0x7e */, + WIFITQM_GEN_MPDU_LENGTH_LIST_STATUS_E = 127 /* 0x7f */, + WIFITQM_GEN_MPDUS_E = 128 /* 0x80 */, + WIFITQM_GEN_MPDUS_STATUS_E = 129 /* 0x81 */, + WIFITQM_REMOVE_MPDU_E = 130 /* 0x82 */, + WIFITQM_REMOVE_MPDU_STATUS_E = 131 /* 0x83 */, + WIFITQM_REMOVE_MSDU_E = 132 /* 0x84 */, + WIFITQM_REMOVE_MSDU_STATUS_E = 133 /* 0x85 */, + WIFITQM_UPDATE_TX_MPDU_COUNT_E = 134 /* 0x86 */, + WIFITQM_WRITE_CMD_E = 135 /* 0x87 */, + WIFIOFDMA_TRIGGER_DETAILS_E = 136 /* 0x88 */, + WIFITX_DATA_E = 137 /* 0x89 */, + WIFITX_FES_SETUP_E = 138 /* 0x8a */, + WIFIRX_PACKET_E = 139 /* 0x8b */, + WIFIEXPECTED_RESPONSE_E = 140 /* 0x8c */, + WIFITX_MPDU_END_E = 141 /* 0x8d */, + WIFITX_MPDU_START_E = 142 /* 0x8e */, + WIFITX_MSDU_END_E = 143 /* 0x8f */, + WIFITX_MSDU_START_E = 144 /* 0x90 */, + WIFITX_SW_MODE_SETUP_E = 145 /* 0x91 */, + WIFITXPCU_BUFFER_STATUS_E = 146 /* 0x92 */, + WIFITXPCU_USER_BUFFER_STATUS_E = 147 /* 0x93 */, + WIFIDATA_TO_TIME_CONFIG_E = 148 /* 0x94 */, + WIFIEXAMPLE_USER_TLV_32_E = 149 /* 0x95 */, + WIFIMPDU_INFO_E = 150 /* 0x96 */, + WIFIPDG_USER_SETUP_E = 151 /* 0x97 */, + WIFITX_11AH_SETUP_E = 152 /* 0x98 */, + WIFIREO_UPDATE_RX_REO_QUEUE_STATUS_E = 153 /* 0x99 */, + WIFITX_PEER_ENTRY_E = 154 /* 0x9a */, + WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E = 155 /* 0x9b */, + WIFIEXAMPLE_STRUCT_NAME_E = 156 /* 0x9c */, + WIFIPCU_PPDU_SETUP_END_INFO_E = 157 /* 0x9d */, + WIFIPPDU_RATE_SETTING_E = 158 /* 0x9e */, + WIFIPROT_RATE_SETTING_E = 159 /* 0x9f */, + WIFIRX_MPDU_DETAILS_E = 160 /* 0xa0 */, + WIFIEXAMPLE_USER_TLV_42_E = 161 /* 0xa1 */, + WIFIRX_MSDU_LINK_E = 162 /* 0xa2 */, + WIFIRX_REO_QUEUE_E = 163 /* 0xa3 */, + WIFIADDR_SEARCH_ENTRY_E = 164 /* 0xa4 */, + WIFISCHEDULER_CMD_E = 165 /* 0xa5 */, + WIFITX_FLUSH_E = 166 /* 0xa6 */, + WIFITQM_ENTRANCE_RING_E = 167 /* 0xa7 */, + WIFITX_DATA_WORD_E = 168 /* 0xa8 */, + WIFITX_MPDU_DETAILS_E = 169 /* 0xa9 */, + WIFITX_MPDU_LINK_E = 170 /* 0xaa */, + WIFITX_MPDU_LINK_PTR_E = 171 /* 0xab */, + WIFITX_MPDU_QUEUE_HEAD_E = 172 /* 0xac */, + WIFITX_MPDU_QUEUE_EXT_E = 173 /* 0xad */, + WIFITX_MPDU_QUEUE_EXT_PTR_E = 174 /* 0xae */, + WIFITX_MSDU_DETAILS_E = 175 /* 0xaf */, + WIFITX_MSDU_EXTENSION_E = 176 /* 0xb0 */, + WIFITX_MSDU_FLOW_E = 177 /* 0xb1 */, + WIFITX_MSDU_LINK_E = 178 /* 0xb2 */, + WIFITX_MSDU_LINK_ENTRY_PTR_E = 179 /* 0xb3 */, + WIFIRESPONSE_RATE_SETTING_E = 180 /* 0xb4 */, + WIFITXPCU_BUFFER_BASICS_E = 181 /* 0xb5 */, + WIFIUNIFORM_DESCRIPTOR_HEADER_E = 182 /* 0xb6 */, + WIFIUNIFORM_TQM_CMD_HEADER_E = 183 /* 0xb7 */, + WIFIUNIFORM_TQM_STATUS_HEADER_E = 184 /* 0xb8 */, + WIFIUSER_RATE_SETTING_E = 185 /* 0xb9 */, + WIFIWBM_BUFFER_RING_E = 186 /* 0xba */, + WIFIWBM_LINK_DESCRIPTOR_RING_E = 187 /* 0xbb */, + WIFIWBM_RELEASE_RING_E = 188 /* 0xbc */, + WIFITX_FLUSH_REQ_E = 189 /* 0xbd */, + WIFIRX_MSDU_DETAILS_E = 190 /* 0xbe */, + WIFITQM_WRITE_CMD_STATUS_E = 191 /* 0xbf */, + WIFITQM_GET_MPDU_QUEUE_STATS_E = 192 /* 0xc0 */, + WIFITQM_GET_MSDU_FLOW_STATS_E = 193 /* 0xc1 */, + WIFIEXAMPLE_USER_CTLV_32_E = 194 /* 0xc2 */, + WIFITX_FES_STATUS_START_E = 195 /* 0xc3 */, + WIFITX_FES_STATUS_USER_PPDU_E = 196 /* 0xc4 */, + WIFITX_FES_STATUS_USER_RESPONSE_E = 197 /* 0xc5 */, + WIFITX_FES_STATUS_END_E = 198 /* 0xc6 */, + WIFIRX_TRIG_INFO_E = 199 /* 0xc7 */, + WIFIRXPCU_TX_SETUP_CLEAR_E = 200 /* 0xc8 */, + WIFIRX_FRAME_BITMAP_REQ_E = 201 /* 0xc9 */, + WIFIRX_FRAME_BITMAP_ACK_E = 202 /* 0xca */, + WIFICOEX_RX_STATUS_E = 203 /* 0xcb */, + WIFIRX_START_PARAM_E = 204 /* 0xcc */, + WIFIRX_PPDU_START_E = 205 /* 0xcd */, + WIFIRX_PPDU_END_E = 206 /* 0xce */, + WIFIRX_MPDU_START_E = 207 /* 0xcf */, + WIFIRX_MPDU_END_E = 208 /* 0xd0 */, + WIFIRX_MSDU_START_E = 209 /* 0xd1 */, + WIFIRX_MSDU_END_E = 210 /* 0xd2 */, + WIFIRX_ATTENTION_E = 211 /* 0xd3 */, + WIFIRECEIVED_RESPONSE_INFO_E = 212 /* 0xd4 */, + WIFIRX_PHY_SLEEP_E = 213 /* 0xd5 */, + WIFIRX_HEADER_E = 214 /* 0xd6 */, + WIFIRX_PEER_ENTRY_E = 215 /* 0xd7 */, + WIFIRX_FLUSH_E = 216 /* 0xd8 */, + WIFIRX_RESPONSE_REQUIRED_INFO_E = 217 /* 0xd9 */, + WIFIRX_FRAMELESS_BAR_DETAILS_E = 218 /* 0xda */, + WIFITQM_GET_MPDU_QUEUE_STATS_STATUS_E = 219 /* 0xdb */, + WIFITQM_GET_MSDU_FLOW_STATS_STATUS_E = 220 /* 0xdc */, + WIFITX_CBF_INFO_E = 221 /* 0xdd */, + WIFIPCU_PPDU_SETUP_USER_E = 222 /* 0xde */, + WIFIRX_MPDU_PCU_START_E = 223 /* 0xdf */, + WIFIRX_PM_INFO_E = 224 /* 0xe0 */, + WIFIRX_USER_PPDU_END_E = 225 /* 0xe1 */, + WIFIRX_PRE_PPDU_START_E = 226 /* 0xe2 */, + WIFIRX_PREAMBLE_E = 227 /* 0xe3 */, + WIFITX_FES_SETUP_COMPLETE_E = 228 /* 0xe4 */, + WIFITX_LAST_MPDU_FETCHED_E = 229 /* 0xe5 */, + WIFITXDMA_STOP_REQUEST_E = 230 /* 0xe6 */, + WIFIRXPCU_SETUP_E = 231 /* 0xe7 */, + WIFIRXPCU_USER_SETUP_E = 232 /* 0xe8 */, + WIFITX_FES_STATUS_ACK_OR_BA_E = 233 /* 0xe9 */, + WIFITQM_ACKED_MPDU_E = 234 /* 0xea */, + WIFICOEX_TX_RESP_E = 235 /* 0xeb */, + WIFICOEX_TX_STATUS_E = 236 /* 0xec */, + WIFIMACTX_COEX_PHY_CTRL_E = 237 /* 0xed */, + WIFICOEX_STATUS_BROADCAST_E = 238 /* 0xee */, + WIFIRESPONSE_START_STATUS_E = 239 /* 0xef */, + WIFIRESPONSE_END_STATUS_E = 240 /* 0xf0 */, + WIFICRYPTO_STATUS_E = 241 /* 0xf1 */, + WIFIRECEIVED_TRIGGER_INFO_E = 242 /* 0xf2 */, + WIFIREO_ENTRANCE_RING_E = 243 /* 0xf3 */, + WIFIRX_MPDU_LINK_E = 244 /* 0xf4 */, + WIFICOEX_TX_STOP_CTRL_E = 245 /* 0xf5 */, + WIFIRX_PPDU_ACK_REPORT_E = 246 /* 0xf6 */, + WIFIRX_PPDU_NO_ACK_REPORT_E = 247 /* 0xf7 */, + WIFISCH_COEX_STATUS_E = 248 /* 0xf8 */, + WIFISCHEDULER_COMMAND_STATUS_E = 249 /* 0xf9 */, + WIFISCHEDULER_RX_PPDU_NO_RESPONSE_STATUS_E = 250 /* 0xfa */, + WIFITX_FES_STATUS_PROT_E = 251 /* 0xfb */, + WIFITX_FES_STATUS_START_PPDU_E = 252 /* 0xfc */, + WIFITX_FES_STATUS_START_PROT_E = 253 /* 0xfd */, + WIFITXPCU_PHYTX_DEBUG32_E = 254 /* 0xfe */, + WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E = 255 /* 0xff */, + WIFITX_MPDU_COUNT_TRANSFER_END_E = 256 /* 0x100 */, + WIFIWHO_ANCHOR_OFFSET_E = 257 /* 0x101 */, + WIFIWHO_ANCHOR_VALUE_E = 258 /* 0x102 */, + WIFIWHO_CCE_INFO_E = 259 /* 0x103 */, + WIFIWHO_COMMIT_E = 260 /* 0x104 */, + WIFIWHO_COMMIT_DONE_E = 261 /* 0x105 */, + WIFIWHO_FLUSH_E = 262 /* 0x106 */, + WIFIWHO_L2_LLC_E = 263 /* 0x107 */, + WIFIWHO_L2_PAYLOAD_E = 264 /* 0x108 */, + WIFIWHO_L3_CHECKSUM_E = 265 /* 0x109 */, + WIFIWHO_L3_INFO_E = 266 /* 0x10a */, + WIFIWHO_L4_CHECKSUM_E = 267 /* 0x10b */, + WIFIWHO_L4_INFO_E = 268 /* 0x10c */, + WIFIWHO_MSDU_E = 269 /* 0x10d */, + WIFIWHO_MSDU_MISC_E = 270 /* 0x10e */, + WIFIWHO_PACKET_DATA_E = 271 /* 0x10f */, + WIFIWHO_PACKET_HDR_E = 272 /* 0x110 */, + WIFIWHO_PPDU_END_E = 273 /* 0x111 */, + WIFIWHO_PPDU_START_E = 274 /* 0x112 */, + WIFIWHO_TSO_E = 275 /* 0x113 */, + WIFIWHO_WMAC_HEADER_PV0_E = 276 /* 0x114 */, + WIFIWHO_WMAC_HEADER_PV1_E = 277 /* 0x115 */, + WIFIWHO_WMAC_IV_E = 278 /* 0x116 */, + WIFIMPDU_INFO_END_E = 279 /* 0x117 */, + WIFIMPDU_INFO_BITMAP_E = 280 /* 0x118 */, + WIFITX_QUEUE_EXTENSION_E = 281 /* 0x119 */, + WIFIRX_PEER_ENTRY_DETAILS_E = 282 /* 0x11a */, + WIFIRX_REO_QUEUE_REFERENCE_E = 283 /* 0x11b */, + WIFIRX_REO_QUEUE_EXT_E = 284 /* 0x11c */, + WIFISCHEDULER_SELFGEN_RESPONSE_STATUS_E = 285 /* 0x11d */, + WIFITQM_UPDATE_TX_MPDU_COUNT_STATUS_E = 286 /* 0x11e */, + WIFITQM_ACKED_MPDU_STATUS_E = 287 /* 0x11f */, + WIFITQM_ADD_MSDU_STATUS_E = 288 /* 0x120 */, + WIFIRX_MPDU_LINK_PTR_E = 289 /* 0x121 */, + WIFIREO_DESTINATION_RING_E = 290 /* 0x122 */, + WIFITQM_LIST_GEN_DONE_E = 291 /* 0x123 */, + WIFIWHO_TERMINATE_E = 292 /* 0x124 */, + WIFITX_LAST_MPDU_END_E = 293 /* 0x125 */, + WIFITX_CV_DATA_E = 294 /* 0x126 */, + WIFITCL_ENTRANCE_FROM_PPE_RING_E = 295 /* 0x127 */, + WIFIPPDU_TX_END_E = 296 /* 0x128 */, + WIFIPROT_TX_END_E = 297 /* 0x129 */, + WIFIPDG_RESPONSE_RATE_SETTING_E = 298 /* 0x12a */, + WIFIMPDU_INFO_GLOBAL_END_E = 299 /* 0x12b */, + WIFITQM_SCH_INSTR_GLOBAL_END_E = 300 /* 0x12c */, + WIFIRX_PPDU_END_USER_STATS_E = 301 /* 0x12d */, + WIFIRX_PPDU_END_USER_STATS_EXT_E = 302 /* 0x12e */, + WIFINO_ACK_REPORT_E = 303 /* 0x12f */, + WIFIACK_REPORT_E = 304 /* 0x130 */, + WIFIUNIFORM_REO_CMD_HEADER_E = 305 /* 0x131 */, + WIFIREO_GET_QUEUE_STATS_E = 306 /* 0x132 */, + WIFIREO_FLUSH_QUEUE_E = 307 /* 0x133 */, + WIFIREO_FLUSH_CACHE_E = 308 /* 0x134 */, + WIFIREO_UNBLOCK_CACHE_E = 309 /* 0x135 */, + WIFIUNIFORM_REO_STATUS_HEADER_E = 310 /* 0x136 */, + WIFIREO_GET_QUEUE_STATS_STATUS_E = 311 /* 0x137 */, + WIFIREO_FLUSH_QUEUE_STATUS_E = 312 /* 0x138 */, + WIFIREO_FLUSH_CACHE_STATUS_E = 313 /* 0x139 */, + WIFIREO_UNBLOCK_CACHE_STATUS_E = 314 /* 0x13a */, + WIFITQM_FLUSH_CACHE_E = 315 /* 0x13b */, + WIFITQM_UNBLOCK_CACHE_E = 316 /* 0x13c */, + WIFITQM_FLUSH_CACHE_STATUS_E = 317 /* 0x13d */, + WIFITQM_UNBLOCK_CACHE_STATUS_E = 318 /* 0x13e */, + WIFIRX_PPDU_END_STATUS_DONE_E = 319 /* 0x13f */, + WIFIRX_STATUS_BUFFER_DONE_E = 320 /* 0x140 */, + WIFIBUFFER_ADDR_INFO_E = 321 /* 0x141 */, + WIFIRX_MSDU_DESC_INFO_E = 322 /* 0x142 */, + WIFIRX_MPDU_DESC_INFO_E = 323 /* 0x143 */, + WIFITCL_DATA_CMD_E = 324 /* 0x144 */, + WIFITCL_GSE_CMD_E = 325 /* 0x145 */, + WIFITCL_EXIT_BASE_E = 326 /* 0x146 */, + WIFITCL_COMPACT_EXIT_RING_E = 327 /* 0x147 */, + WIFITCL_REGULAR_EXIT_RING_E = 328 /* 0x148 */, + WIFITCL_EXTENDED_EXIT_RING_E = 329 /* 0x149 */, + WIFIUPLINK_COMMON_INFO_E = 330 /* 0x14a */, + WIFIUPLINK_USER_SETUP_INFO_E = 331 /* 0x14b */, + WIFITX_DATA_SYNC_E = 332 /* 0x14c */, + WIFIPHYRX_CBF_READ_REQUEST_ACK_E = 333 /* 0x14d */, + WIFITCL_STATUS_RING_E = 334 /* 0x14e */, + WIFITQM_GET_MPDU_HEAD_INFO_E = 335 /* 0x14f */, + WIFITQM_SYNC_CMD_E = 336 /* 0x150 */, + WIFITQM_GET_MPDU_HEAD_INFO_STATUS_E = 337 /* 0x151 */, + WIFITQM_SYNC_CMD_STATUS_E = 338 /* 0x152 */, + WIFITQM_THRESHOLD_DROP_NOTIFICATION_STATUS_E = 339 /* 0x153 */, + WIFITQM_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 340 /* 0x154 */, + WIFIREO_FLUSH_TIMEOUT_LIST_E = 341 /* 0x155 */, + WIFIREO_FLUSH_TIMEOUT_LIST_STATUS_E = 342 /* 0x156 */, + WIFIREO_TO_PPE_RING_E = 343 /* 0x157 */, + WIFIRX_MPDU_INFO_E = 344 /* 0x158 */, + WIFIREO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_E = 345 /* 0x159 */, + WIFISCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS_E = 346 /* 0x15a */, + WIFIEXAMPLE_USER_TLV_32_NAME_E = 347 /* 0x15b */, + WIFIRX_PPDU_START_USER_INFO_E = 348 /* 0x15c */, + WIFIRX_RXPCU_CLASSIFICATION_OVERVIEW_E = 349 /* 0x15d */, + WIFIRX_RING_MASK_E = 350 /* 0x15e */, + WIFIWHO_CLASSIFY_INFO_E = 351 /* 0x15f */, + WIFITXPT_CLASSIFY_INFO_E = 352 /* 0x160 */, + WIFIRXPT_CLASSIFY_INFO_E = 353 /* 0x161 */, + WIFITX_FLOW_SEARCH_ENTRY_E = 354 /* 0x162 */, + WIFIRX_FLOW_SEARCH_ENTRY_E = 355 /* 0x163 */, + WIFIRECEIVED_TRIGGER_INFO_DETAILS_E = 356 /* 0x164 */, + WIFICOEX_MAC_NAP_E = 357 /* 0x165 */, + WIFIMACRX_ABORT_REQUEST_INFO_E = 358 /* 0x166 */, + WIFIMACTX_ABORT_REQUEST_INFO_E = 359 /* 0x167 */, + WIFIPHYRX_ABORT_REQUEST_INFO_E = 360 /* 0x168 */, + WIFIPHYTX_ABORT_REQUEST_INFO_E = 361 /* 0x169 */, + WIFIRXPCU_PPDU_END_INFO_E = 362 /* 0x16a */, + WIFIWHO_MESH_CONTROL_E = 363 /* 0x16b */, + WIFIL_SIG_A_INFO_E = 364 /* 0x16c */, + WIFIL_SIG_B_INFO_E = 365 /* 0x16d */, + WIFIHT_SIG_INFO_E = 366 /* 0x16e */, + WIFIVHT_SIG_A_INFO_E = 367 /* 0x16f */, + WIFIVHT_SIG_B_SU20_INFO_E = 368 /* 0x170 */, + WIFIVHT_SIG_B_SU40_INFO_E = 369 /* 0x171 */, + WIFIVHT_SIG_B_SU80_INFO_E = 370 /* 0x172 */, + WIFIVHT_SIG_B_SU160_INFO_E = 371 /* 0x173 */, + WIFIVHT_SIG_B_MU20_INFO_E = 372 /* 0x174 */, + WIFIVHT_SIG_B_MU40_INFO_E = 373 /* 0x175 */, + WIFIVHT_SIG_B_MU80_INFO_E = 374 /* 0x176 */, + WIFIVHT_SIG_B_MU160_INFO_E = 375 /* 0x177 */, + WIFISERVICE_INFO_E = 376 /* 0x178 */, + WIFIHE_SIG_A_SU_INFO_E = 377 /* 0x179 */, + WIFIHE_SIG_A_MU_DL_INFO_E = 378 /* 0x17a */, + WIFIHE_SIG_A_MU_UL_INFO_E = 379 /* 0x17b */, + WIFIHE_SIG_B1_MU_INFO_E = 380 /* 0x17c */, + WIFIHE_SIG_B2_MU_INFO_E = 381 /* 0x17d */, + WIFIHE_SIG_B2_OFDMA_INFO_E = 382 /* 0x17e */, + WIFIPDG_SW_MODE_BW_START_E = 383 /* 0x17f */, + WIFIPDG_SW_MODE_BW_END_E = 384 /* 0x180 */, + WIFIPDG_WAIT_FOR_MAC_REQUEST_E = 385 /* 0x181 */, + WIFIPDG_WAIT_FOR_PHY_REQUEST_E = 386 /* 0x182 */, + WIFISCHEDULER_END_E = 387 /* 0x183 */, + WIFIPEER_TABLE_ENTRY_E = 388 /* 0x184 */, + WIFISW_PEER_INFO_E = 389 /* 0x185 */, + WIFIRXOLE_CCE_CLASSIFY_INFO_E = 390 /* 0x186 */, + WIFITCL_CCE_CLASSIFY_INFO_E = 391 /* 0x187 */, + WIFIRXOLE_CCE_INFO_E = 392 /* 0x188 */, + WIFITCL_CCE_INFO_E = 393 /* 0x189 */, + WIFITCL_CCE_SUPERRULE_E = 394 /* 0x18a */, + WIFICCE_RULE_E = 395 /* 0x18b */, + WIFIRX_PPDU_START_DROPPED_E = 396 /* 0x18c */, + WIFIRX_PPDU_END_DROPPED_E = 397 /* 0x18d */, + WIFIRX_PPDU_END_STATUS_DONE_DROPPED_E = 398 /* 0x18e */, + WIFIRX_MPDU_START_DROPPED_E = 399 /* 0x18f */, + WIFIRX_MSDU_START_DROPPED_E = 400 /* 0x190 */, + WIFIRX_MSDU_END_DROPPED_E = 401 /* 0x191 */, + WIFIRX_MPDU_END_DROPPED_E = 402 /* 0x192 */, + WIFIRX_ATTENTION_DROPPED_E = 403 /* 0x193 */, + WIFITXPCU_USER_SETUP_E = 404 /* 0x194 */, + WIFIRXPCU_USER_SETUP_EXT_E = 405 /* 0x195 */, + WIFICE_SRC_DESC_E = 406 /* 0x196 */, + WIFICE_STAT_DESC_E = 407 /* 0x197 */, + WIFIRXOLE_CCE_SUPERRULE_E = 408 /* 0x198 */, + WIFITX_RATE_STATS_INFO_E = 409 /* 0x199 */, + WIFICMD_PART_0_END_E = 410 /* 0x19a */, + WIFIMACTX_SYNTH_ON_E = 411 /* 0x19b */, + WIFISCH_CRITICAL_TLV_REFERENCE_E = 412 /* 0x19c */, + WIFITQM_MPDU_GLOBAL_START_E = 413 /* 0x19d */, + WIFIEXAMPLE_TLV_32_E = 414 /* 0x19e */, + WIFITQM_UPDATE_TX_MSDU_FLOW_E = 415 /* 0x19f */, + WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_E = 416 /* 0x1a0 */, + WIFITQM_UPDATE_TX_MSDU_FLOW_STATUS_E = 417 /* 0x1a1 */, + WIFITQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS_E = 418 /* 0x1a2 */, + WIFIREO_UPDATE_RX_REO_QUEUE_E = 419 /* 0x1a3 */, + WIFICE_DST_DESC_E = 420 /* 0x1a4 */, + WIFITQM_MPDU_QUEUE_EMPTY_STATUS_E = 421 /* 0x1a5 */, + WIFITQM_2_SCH_MPDU_AVAILABLE_E = 422 /* 0x1a6 */, + WIFIPDG_TRIG_RESPONSE_E = 423 /* 0x1a7 */, + WIFITRIGGER_RESPONSE_TX_DONE_E = 424 /* 0x1a8 */, + WIFIABORT_FROM_PHYRX_DETAILS_E = 425 /* 0x1a9 */, + WIFISCH_TQM_CMD_WRAPPER_E = 426 /* 0x1aa */, + WIFIMPDUS_AVAILABLE_E = 427 /* 0x1ab */, + WIFIRECEIVED_RESPONSE_INFO_PART2_E = 428 /* 0x1ac */, + WIFIPHYRX_PKT_END_INFO_E = 429 /* 0x1ad */, + WIFIPHYRX_TX_START_TIMING_E = 430 /* 0x1ae */, + WIFITXPCU_PREAMBLE_DONE_E = 431 /* 0x1af */, + WIFINDP_PREAMBLE_DONE_E = 432 /* 0x1b0 */, + WIFISCH_TQM_CMD_WRAPPER_RBO_DROP_E = 433 /* 0x1b1 */, + WIFISCH_TQM_CMD_WRAPPER_CONT_DROP_E = 434 /* 0x1b2 */, + WIFIMACTX_CLEAR_PREV_TX_INFO_E = 435 /* 0x1b3 */, + WIFITX_PUNCTURE_SETUP_E = 436 /* 0x1b4 */, + WIFITX_PUNCTURE_PATTERN_E = 437 /* 0x1b5 */, + WIFIR2R_STATUS_END_E = 438 /* 0x1b6 */, + WIFIMACTX_PREFETCH_CV_COMMON_E = 439 /* 0x1b7 */, + WIFIEND_OF_FLUSH_MARKER_E = 440 /* 0x1b8 */, + WIFIUPLINK_COMMON_INFO_PUNC_E = 441 /* 0x1b9 */, + WIFIMACTX_MU_UPLINK_COMMON_PUNC_E = 442 /* 0x1ba */, + WIFIMACTX_MU_UPLINK_USER_SETUP_PUNC_E = 443 /* 0x1bb */, + WIFIRECEIVED_RESPONSE_USER_7_0_E = 444 /* 0x1bc */, + WIFIRECEIVED_RESPONSE_USER_15_8_E = 445 /* 0x1bd */, + WIFIRECEIVED_RESPONSE_USER_23_16_E = 446 /* 0x1be */, + WIFIRECEIVED_RESPONSE_USER_31_24_E = 447 /* 0x1bf */, + WIFIRECEIVED_RESPONSE_USER_36_32_E = 448 /* 0x1c0 */, + WIFIRECEIVED_RESPONSE_USER_INFO_E = 449 /* 0x1c1 */, + WIFITX_LOOPBACK_SETUP_E = 450 /* 0x1c2 */, + WIFIPHYRX_OTHER_RECEIVE_INFO_RU_DETAILS_E = 451 /* 0x1c3 */, + WIFISCH_WAIT_INSTR_TX_PATH_E = 452 /* 0x1c4 */, + WIFIMACTX_OTHER_TRANSMIT_INFO_TX2TX_E = 453 /* 0x1c5 */, + WIFIMACTX_OTHER_TRANSMIT_INFO_EMUPHY_SETUP_E = 454 /* 0x1c6 */, + WIFIPHYRX_OTHER_RECEIVE_INFO_EVM_DETAILS_E = 455 /* 0x1c7 */, + WIFITX_WUR_DATA_E = 456 /* 0x1c8 */, + WIFIRX_PPDU_END_START_E = 457 /* 0x1c9 */, + WIFIRX_PPDU_END_MIDDLE_E = 458 /* 0x1ca */, + WIFIRX_PPDU_END_LAST_E = 459 /* 0x1cb */, + WIFIRECEIVE_USER_INFO_L1_E = 460 /* 0x1cc */, + WIFIMIMO_CONTROL_INFO_L1_E = 461 /* 0x1cd */, + WIFIMACTX_BACKOFF_BASED_TRANSMISSION_E = 462 /* 0x1ce */, + WIFIMACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX_E = 463 /* 0x1cf */, + WIFISRP_INFO_E = 464 /* 0x1d0 */, + WIFIOBSS_SR_INFO_E = 465 /* 0x1d1 */, + WIFISCHEDULER_SW_MSG_STATUS_E = 466 /* 0x1d2 */, + WIFIHWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT_E = 467 /* 0x1d3 */, + WIFIRXPCU_SETUP_COMPLETE_E = 468 /* 0x1d4 */, + WIFISNOOP_PPDU_START_E = 469 /* 0x1d5 */, + WIFISNOOP_MPDU_USR_DBG_INFO_E = 470 /* 0x1d6 */, + WIFISNOOP_MSDU_USR_DBG_INFO_E = 471 /* 0x1d7 */, + WIFISNOOP_MSDU_USR_DATA_E = 472 /* 0x1d8 */, + WIFISNOOP_MPDU_USR_STAT_INFO_E = 473 /* 0x1d9 */, + WIFISNOOP_PPDU_END_E = 474 /* 0x1da */, + WIFISNOOP_SPARE_E = 475 /* 0x1db */, + WIFIMACTX_PREFETCH_CV_BULK_E = 476 /* 0x1dc */, + WIFIMACTX_PREFETCH_CV_BULK_USER_E = 477 /* 0x1dd */, + WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON_E = 478 /* 0x1de */, + WIFIPHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER_E = 479 /* 0x1df */, + WIFIMACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS_E = 480 /* 0x1e0 */, + WIFISW_MONITOR_RING_E = 481 /* 0x1e1 */, + WIFIPHYRX_OTHER_RECEIVE_INFO_108P_EVM_DETAILS_E = 482 /* 0x1e2 */, + WIFISCH_TLV_WRAPPER_E = 483 /* 0x1e3 */, + WIFISCHEDULER_STATUS_WRAPPER_E = 484 /* 0x1e4 */, + WIFITLV_BASE_E = 511 /* 0x1ff */ + +} tlv_tag_def__e; ///< tlv_tag_def Enum Type + +#endif // _TLV_TAG_DEF_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/tx_msdu_extension.h b/drivers/staging/fw-api/hw/qca6750/v1/tx_msdu_extension.h new file mode 100644 index 000000000000..794b807fcc25 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/tx_msdu_extension.h @@ -0,0 +1,757 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _TX_MSDU_EXTENSION_H_ +#define _TX_MSDU_EXTENSION_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 tso_enable[0], reserved_0a[6:1], tcp_flag[15:7], tcp_flag_mask[24:16], reserved_0b[31:25] +// 1 l2_length[15:0], ip_length[31:16] +// 2 tcp_seq_number[31:0] +// 3 ip_identification[15:0], udp_length[31:16] +// 4 checksum_offset[13:0], partial_checksum_en[14], reserved_4a[15], payload_start_offset[29:16], reserved_4b[31:30] +// 5 payload_end_offset[13:0], reserved_5a[15:14], wds[16], reserved_5b[31:17] +// 6 buf0_ptr_31_0[31:0] +// 7 buf0_ptr_39_32[7:0], reserved_7a[15:8], buf0_len[31:16] +// 8 buf1_ptr_31_0[31:0] +// 9 buf1_ptr_39_32[7:0], reserved_9a[15:8], buf1_len[31:16] +// 10 buf2_ptr_31_0[31:0] +// 11 buf2_ptr_39_32[7:0], reserved_11a[15:8], buf2_len[31:16] +// 12 buf3_ptr_31_0[31:0] +// 13 buf3_ptr_39_32[7:0], reserved_13a[15:8], buf3_len[31:16] +// 14 buf4_ptr_31_0[31:0] +// 15 buf4_ptr_39_32[7:0], reserved_15a[15:8], buf4_len[31:16] +// 16 buf5_ptr_31_0[31:0] +// 17 buf5_ptr_39_32[7:0], reserved_17a[15:8], buf5_len[31:16] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_TX_MSDU_EXTENSION 18 + +struct tx_msdu_extension { + uint32_t tso_enable : 1, //[0] + reserved_0a : 6, //[6:1] + tcp_flag : 9, //[15:7] + tcp_flag_mask : 9, //[24:16] + reserved_0b : 7; //[31:25] + uint32_t l2_length : 16, //[15:0] + ip_length : 16; //[31:16] + uint32_t tcp_seq_number : 32; //[31:0] + uint32_t ip_identification : 16, //[15:0] + udp_length : 16; //[31:16] + uint32_t checksum_offset : 14, //[13:0] + partial_checksum_en : 1, //[14] + reserved_4a : 1, //[15] + payload_start_offset : 14, //[29:16] + reserved_4b : 2; //[31:30] + uint32_t payload_end_offset : 14, //[13:0] + reserved_5a : 2, //[15:14] + wds : 1, //[16] + reserved_5b : 15; //[31:17] + uint32_t buf0_ptr_31_0 : 32; //[31:0] + uint32_t buf0_ptr_39_32 : 8, //[7:0] + reserved_7a : 8, //[15:8] + buf0_len : 16; //[31:16] + uint32_t buf1_ptr_31_0 : 32; //[31:0] + uint32_t buf1_ptr_39_32 : 8, //[7:0] + reserved_9a : 8, //[15:8] + buf1_len : 16; //[31:16] + uint32_t buf2_ptr_31_0 : 32; //[31:0] + uint32_t buf2_ptr_39_32 : 8, //[7:0] + reserved_11a : 8, //[15:8] + buf2_len : 16; //[31:16] + uint32_t buf3_ptr_31_0 : 32; //[31:0] + uint32_t buf3_ptr_39_32 : 8, //[7:0] + reserved_13a : 8, //[15:8] + buf3_len : 16; //[31:16] + uint32_t buf4_ptr_31_0 : 32; //[31:0] + uint32_t buf4_ptr_39_32 : 8, //[7:0] + reserved_15a : 8, //[15:8] + buf4_len : 16; //[31:16] + uint32_t buf5_ptr_31_0 : 32; //[31:0] + uint32_t buf5_ptr_39_32 : 8, //[7:0] + reserved_17a : 8, //[15:8] + buf5_len : 16; //[31:16] +}; + +/* + +tso_enable + + Enable transmit segmentation offload + +reserved_0a + + FW will set to 0, MAC will ignore.  + +tcp_flag + + TCP flags + + {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} + +tcp_flag_mask + + TCP flag mask. Tcp_flag is inserted into the header + based on the mask, if TSO is enabled + +reserved_0b + + FW will set to 0, MAC will ignore.  + +l2_length + + L2 length for the msdu, if TSO is enabled + +ip_length + + IP length for the msdu, if TSO is enabled + +tcp_seq_number + + Tcp_seq_number for the msdu, if TSO is enabled + +ip_identification + + IP_identification for the msdu, if TSO is enabled + +udp_length + + TXDMA is copies this field into MSDU START TLV + +checksum_offset + + The calculated checksum from start offset to end offset + will be added to the checksum at the offset given by this + field + +partial_checksum_en + + Partial Checksum Enable Bit. + + + +reserved_4a + + + +payload_start_offset + + L4 checksum calculations will start fromt this offset + + + +reserved_4b + + + +payload_end_offset + + L4 checksum calculations will end at this offset. + + + +reserved_5a + + + +wds + + If set the current packet is 4-address frame. Required + because an aggregate can include some frames with 3 address + format and other frames with 4 address format. Used by the + OLE during encapsulation. + + Note: there is also global wds tx control in the + TX_PEER_ENTRY + + + +reserved_5b + + + +buf0_ptr_31_0 + + Lower 32 bits of the first buffer pointer + + + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + + +buf0_ptr_39_32 + + Upper 8 bits of the first buffer pointer + +reserved_7a + + + +buf0_len + + Length of the first buffer + +buf1_ptr_31_0 + + Lower 32 bits of the second buffer pointer + + + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + + +buf1_ptr_39_32 + + Upper 8 bits of the second buffer pointer + +reserved_9a + + + +buf1_len + + Length of the second buffer + +buf2_ptr_31_0 + + Lower 32 bits of the third buffer pointer + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + + +buf2_ptr_39_32 + + Upper 8 bits of the third buffer pointer + +reserved_11a + + + +buf2_len + + Length of the third buffer + +buf3_ptr_31_0 + + Lower 32 bits of the fourth buffer pointer + + + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + + +buf3_ptr_39_32 + + Upper 8 bits of the fourth buffer pointer + +reserved_13a + + + +buf3_len + + Length of the fourth buffer + +buf4_ptr_31_0 + + Lower 32 bits of the fifth buffer pointer + + + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + + +buf4_ptr_39_32 + + Upper 8 bits of the fifth buffer pointer + +reserved_15a + + + +buf4_len + + Length of the fifth buffer + +buf5_ptr_31_0 + + Lower 32 bits of the sixth buffer pointer + + + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + + +buf5_ptr_39_32 + + Upper 8 bits of the sixth buffer pointer + +reserved_17a + + + +buf5_len + + Length of the sixth buffer +*/ + + +/* Description TX_MSDU_EXTENSION_0_TSO_ENABLE + + Enable transmit segmentation offload +*/ +#define TX_MSDU_EXTENSION_0_TSO_ENABLE_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_TSO_ENABLE_LSB 0 +#define TX_MSDU_EXTENSION_0_TSO_ENABLE_MASK 0x00000001 + +/* Description TX_MSDU_EXTENSION_0_RESERVED_0A + + FW will set to 0, MAC will ignore.  +*/ +#define TX_MSDU_EXTENSION_0_RESERVED_0A_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_RESERVED_0A_LSB 1 +#define TX_MSDU_EXTENSION_0_RESERVED_0A_MASK 0x0000007e + +/* Description TX_MSDU_EXTENSION_0_TCP_FLAG + + TCP flags + + {NS,CWR,ECE,URG,ACK,PSH, RST ,SYN,FIN} +*/ +#define TX_MSDU_EXTENSION_0_TCP_FLAG_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_TCP_FLAG_LSB 7 +#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK 0x0000ff80 + +/* Description TX_MSDU_EXTENSION_0_TCP_FLAG_MASK + + TCP flag mask. Tcp_flag is inserted into the header + based on the mask, if TSO is enabled +*/ +#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_LSB 16 +#define TX_MSDU_EXTENSION_0_TCP_FLAG_MASK_MASK 0x01ff0000 + +/* Description TX_MSDU_EXTENSION_0_RESERVED_0B + + FW will set to 0, MAC will ignore.  +*/ +#define TX_MSDU_EXTENSION_0_RESERVED_0B_OFFSET 0x00000000 +#define TX_MSDU_EXTENSION_0_RESERVED_0B_LSB 25 +#define TX_MSDU_EXTENSION_0_RESERVED_0B_MASK 0xfe000000 + +/* Description TX_MSDU_EXTENSION_1_L2_LENGTH + + L2 length for the msdu, if TSO is enabled +*/ +#define TX_MSDU_EXTENSION_1_L2_LENGTH_OFFSET 0x00000004 +#define TX_MSDU_EXTENSION_1_L2_LENGTH_LSB 0 +#define TX_MSDU_EXTENSION_1_L2_LENGTH_MASK 0x0000ffff + +/* Description TX_MSDU_EXTENSION_1_IP_LENGTH + + IP length for the msdu, if TSO is enabled +*/ +#define TX_MSDU_EXTENSION_1_IP_LENGTH_OFFSET 0x00000004 +#define TX_MSDU_EXTENSION_1_IP_LENGTH_LSB 16 +#define TX_MSDU_EXTENSION_1_IP_LENGTH_MASK 0xffff0000 + +/* Description TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER + + Tcp_seq_number for the msdu, if TSO is enabled +*/ +#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_OFFSET 0x00000008 +#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_LSB 0 +#define TX_MSDU_EXTENSION_2_TCP_SEQ_NUMBER_MASK 0xffffffff + +/* Description TX_MSDU_EXTENSION_3_IP_IDENTIFICATION + + IP_identification for the msdu, if TSO is enabled +*/ +#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_OFFSET 0x0000000c +#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_LSB 0 +#define TX_MSDU_EXTENSION_3_IP_IDENTIFICATION_MASK 0x0000ffff + +/* Description TX_MSDU_EXTENSION_3_UDP_LENGTH + + TXDMA is copies this field into MSDU START TLV +*/ +#define TX_MSDU_EXTENSION_3_UDP_LENGTH_OFFSET 0x0000000c +#define TX_MSDU_EXTENSION_3_UDP_LENGTH_LSB 16 +#define TX_MSDU_EXTENSION_3_UDP_LENGTH_MASK 0xffff0000 + +/* Description TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET + + The calculated checksum from start offset to end offset + will be added to the checksum at the offset given by this + field +*/ +#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_LSB 0 +#define TX_MSDU_EXTENSION_4_CHECKSUM_OFFSET_MASK 0x00003fff + +/* Description TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN + + Partial Checksum Enable Bit. + + +*/ +#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_LSB 14 +#define TX_MSDU_EXTENSION_4_PARTIAL_CHECKSUM_EN_MASK 0x00004000 + +/* Description TX_MSDU_EXTENSION_4_RESERVED_4A + + +*/ +#define TX_MSDU_EXTENSION_4_RESERVED_4A_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_4_RESERVED_4A_LSB 15 +#define TX_MSDU_EXTENSION_4_RESERVED_4A_MASK 0x00008000 + +/* Description TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET + + L4 checksum calculations will start fromt this offset + + +*/ +#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_LSB 16 +#define TX_MSDU_EXTENSION_4_PAYLOAD_START_OFFSET_MASK 0x3fff0000 + +/* Description TX_MSDU_EXTENSION_4_RESERVED_4B + + +*/ +#define TX_MSDU_EXTENSION_4_RESERVED_4B_OFFSET 0x00000010 +#define TX_MSDU_EXTENSION_4_RESERVED_4B_LSB 30 +#define TX_MSDU_EXTENSION_4_RESERVED_4B_MASK 0xc0000000 + +/* Description TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET + + L4 checksum calculations will end at this offset. + + +*/ +#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_LSB 0 +#define TX_MSDU_EXTENSION_5_PAYLOAD_END_OFFSET_MASK 0x00003fff + +/* Description TX_MSDU_EXTENSION_5_RESERVED_5A + + +*/ +#define TX_MSDU_EXTENSION_5_RESERVED_5A_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_5_RESERVED_5A_LSB 14 +#define TX_MSDU_EXTENSION_5_RESERVED_5A_MASK 0x0000c000 + +/* Description TX_MSDU_EXTENSION_5_WDS + + If set the current packet is 4-address frame. Required + because an aggregate can include some frames with 3 address + format and other frames with 4 address format. Used by the + OLE during encapsulation. + + Note: there is also global wds tx control in the + TX_PEER_ENTRY + + +*/ +#define TX_MSDU_EXTENSION_5_WDS_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_5_WDS_LSB 16 +#define TX_MSDU_EXTENSION_5_WDS_MASK 0x00010000 + +/* Description TX_MSDU_EXTENSION_5_RESERVED_5B + + +*/ +#define TX_MSDU_EXTENSION_5_RESERVED_5B_OFFSET 0x00000014 +#define TX_MSDU_EXTENSION_5_RESERVED_5B_LSB 17 +#define TX_MSDU_EXTENSION_5_RESERVED_5B_MASK 0xfffe0000 + +/* Description TX_MSDU_EXTENSION_6_BUF0_PTR_31_0 + + Lower 32 bits of the first buffer pointer + + + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + +*/ +#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_OFFSET 0x00000018 +#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_6_BUF0_PTR_31_0_MASK 0xffffffff + +/* Description TX_MSDU_EXTENSION_7_BUF0_PTR_39_32 + + Upper 8 bits of the first buffer pointer +*/ +#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_7_BUF0_PTR_39_32_MASK 0x000000ff + +/* Description TX_MSDU_EXTENSION_7_RESERVED_7A + + +*/ +#define TX_MSDU_EXTENSION_7_RESERVED_7A_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_7_RESERVED_7A_LSB 8 +#define TX_MSDU_EXTENSION_7_RESERVED_7A_MASK 0x0000ff00 + +/* Description TX_MSDU_EXTENSION_7_BUF0_LEN + + Length of the first buffer +*/ +#define TX_MSDU_EXTENSION_7_BUF0_LEN_OFFSET 0x0000001c +#define TX_MSDU_EXTENSION_7_BUF0_LEN_LSB 16 +#define TX_MSDU_EXTENSION_7_BUF0_LEN_MASK 0xffff0000 + +/* Description TX_MSDU_EXTENSION_8_BUF1_PTR_31_0 + + Lower 32 bits of the second buffer pointer + + + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + +*/ +#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_OFFSET 0x00000020 +#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_8_BUF1_PTR_31_0_MASK 0xffffffff + +/* Description TX_MSDU_EXTENSION_9_BUF1_PTR_39_32 + + Upper 8 bits of the second buffer pointer +*/ +#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_9_BUF1_PTR_39_32_MASK 0x000000ff + +/* Description TX_MSDU_EXTENSION_9_RESERVED_9A + + +*/ +#define TX_MSDU_EXTENSION_9_RESERVED_9A_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_9_RESERVED_9A_LSB 8 +#define TX_MSDU_EXTENSION_9_RESERVED_9A_MASK 0x0000ff00 + +/* Description TX_MSDU_EXTENSION_9_BUF1_LEN + + Length of the second buffer +*/ +#define TX_MSDU_EXTENSION_9_BUF1_LEN_OFFSET 0x00000024 +#define TX_MSDU_EXTENSION_9_BUF1_LEN_LSB 16 +#define TX_MSDU_EXTENSION_9_BUF1_LEN_MASK 0xffff0000 + +/* Description TX_MSDU_EXTENSION_10_BUF2_PTR_31_0 + + Lower 32 bits of the third buffer pointer + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + +*/ +#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_OFFSET 0x00000028 +#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_10_BUF2_PTR_31_0_MASK 0xffffffff + +/* Description TX_MSDU_EXTENSION_11_BUF2_PTR_39_32 + + Upper 8 bits of the third buffer pointer +*/ +#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_11_BUF2_PTR_39_32_MASK 0x000000ff + +/* Description TX_MSDU_EXTENSION_11_RESERVED_11A + + +*/ +#define TX_MSDU_EXTENSION_11_RESERVED_11A_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_11_RESERVED_11A_LSB 8 +#define TX_MSDU_EXTENSION_11_RESERVED_11A_MASK 0x0000ff00 + +/* Description TX_MSDU_EXTENSION_11_BUF2_LEN + + Length of the third buffer +*/ +#define TX_MSDU_EXTENSION_11_BUF2_LEN_OFFSET 0x0000002c +#define TX_MSDU_EXTENSION_11_BUF2_LEN_LSB 16 +#define TX_MSDU_EXTENSION_11_BUF2_LEN_MASK 0xffff0000 + +/* Description TX_MSDU_EXTENSION_12_BUF3_PTR_31_0 + + Lower 32 bits of the fourth buffer pointer + + + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + +*/ +#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_OFFSET 0x00000030 +#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_12_BUF3_PTR_31_0_MASK 0xffffffff + +/* Description TX_MSDU_EXTENSION_13_BUF3_PTR_39_32 + + Upper 8 bits of the fourth buffer pointer +*/ +#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_13_BUF3_PTR_39_32_MASK 0x000000ff + +/* Description TX_MSDU_EXTENSION_13_RESERVED_13A + + +*/ +#define TX_MSDU_EXTENSION_13_RESERVED_13A_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_13_RESERVED_13A_LSB 8 +#define TX_MSDU_EXTENSION_13_RESERVED_13A_MASK 0x0000ff00 + +/* Description TX_MSDU_EXTENSION_13_BUF3_LEN + + Length of the fourth buffer +*/ +#define TX_MSDU_EXTENSION_13_BUF3_LEN_OFFSET 0x00000034 +#define TX_MSDU_EXTENSION_13_BUF3_LEN_LSB 16 +#define TX_MSDU_EXTENSION_13_BUF3_LEN_MASK 0xffff0000 + +/* Description TX_MSDU_EXTENSION_14_BUF4_PTR_31_0 + + Lower 32 bits of the fifth buffer pointer + + + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + +*/ +#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_OFFSET 0x00000038 +#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_14_BUF4_PTR_31_0_MASK 0xffffffff + +/* Description TX_MSDU_EXTENSION_15_BUF4_PTR_39_32 + + Upper 8 bits of the fifth buffer pointer +*/ +#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_15_BUF4_PTR_39_32_MASK 0x000000ff + +/* Description TX_MSDU_EXTENSION_15_RESERVED_15A + + +*/ +#define TX_MSDU_EXTENSION_15_RESERVED_15A_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_15_RESERVED_15A_LSB 8 +#define TX_MSDU_EXTENSION_15_RESERVED_15A_MASK 0x0000ff00 + +/* Description TX_MSDU_EXTENSION_15_BUF4_LEN + + Length of the fifth buffer +*/ +#define TX_MSDU_EXTENSION_15_BUF4_LEN_OFFSET 0x0000003c +#define TX_MSDU_EXTENSION_15_BUF4_LEN_LSB 16 +#define TX_MSDU_EXTENSION_15_BUF4_LEN_MASK 0xffff0000 + +/* Description TX_MSDU_EXTENSION_16_BUF5_PTR_31_0 + + Lower 32 bits of the sixth buffer pointer + + + + NOTE: SW/FW manages the 'cookie' info related to this + buffer together with the 'cookie' info for this + MSDU_EXTENSION descriptor + + +*/ +#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_OFFSET 0x00000040 +#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_LSB 0 +#define TX_MSDU_EXTENSION_16_BUF5_PTR_31_0_MASK 0xffffffff + +/* Description TX_MSDU_EXTENSION_17_BUF5_PTR_39_32 + + Upper 8 bits of the sixth buffer pointer +*/ +#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_LSB 0 +#define TX_MSDU_EXTENSION_17_BUF5_PTR_39_32_MASK 0x000000ff + +/* Description TX_MSDU_EXTENSION_17_RESERVED_17A + + +*/ +#define TX_MSDU_EXTENSION_17_RESERVED_17A_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_17_RESERVED_17A_LSB 8 +#define TX_MSDU_EXTENSION_17_RESERVED_17A_MASK 0x0000ff00 + +/* Description TX_MSDU_EXTENSION_17_BUF5_LEN + + Length of the sixth buffer +*/ +#define TX_MSDU_EXTENSION_17_BUF5_LEN_OFFSET 0x00000044 +#define TX_MSDU_EXTENSION_17_BUF5_LEN_LSB 16 +#define TX_MSDU_EXTENSION_17_BUF5_LEN_MASK 0xffff0000 + + +#endif // _TX_MSDU_EXTENSION_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/tx_rate_stats_info.h b/drivers/staging/fw-api/hw/qca6750/v1/tx_rate_stats_info.h new file mode 100644 index 000000000000..9ec543409d2b --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/tx_rate_stats_info.h @@ -0,0 +1,473 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _TX_RATE_STATS_INFO_H_ +#define _TX_RATE_STATS_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 tx_rate_stats_info_valid[0], transmit_bw[2:1], transmit_pkt_type[6:3], transmit_stbc[7], transmit_ldpc[8], transmit_sgi[10:9], transmit_mcs[14:11], ofdma_transmission[15], tones_in_ru[27:16], reserved_0a[31:28] +// 1 ppdu_transmission_tsf[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_TX_RATE_STATS_INFO 2 + +struct tx_rate_stats_info { + uint32_t tx_rate_stats_info_valid : 1, //[0] + transmit_bw : 2, //[2:1] + transmit_pkt_type : 4, //[6:3] + transmit_stbc : 1, //[7] + transmit_ldpc : 1, //[8] + transmit_sgi : 2, //[10:9] + transmit_mcs : 4, //[14:11] + ofdma_transmission : 1, //[15] + tones_in_ru : 12, //[27:16] + reserved_0a : 4; //[31:28] + uint32_t ppdu_transmission_tsf : 32; //[31:0] +}; + +/* + +tx_rate_stats_info_valid + + When set all other fields in this STRUCT contain valid + info. + + + + + + +transmit_bw + + Field only valid when Tx_rate_stats_info_valid is set + + + + Indicates the BW of the upcoming transmission that shall + likely start in about 3 -4 us on the medium + + + + + + + + + + + + + + + +transmit_pkt_type + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + The packet type + + 802.11a PPDU type + + 802.11b PPDU type + + 802.11n Mixed Mode PPDU type + + 802.11ac PPDU type + + 802.11ax PPDU type + + 802.11ba (WUR) PPDU type + +transmit_stbc + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + When set, STBC transmission rate was used. + +transmit_ldpc + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + When set, use LDPC transmission rates + +transmit_sgi + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + Legacy normal GI. Can also be + used for HE + + Legacy short GI. Can also be + used for HE + + HE related GI + + HE related GI + + + +transmit_mcs + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + For details, refer to MCS_TYPE description + + + +ofdma_transmission + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + + + Set when the transmission was an OFDMA transmission (DL + or UL). + + + +tones_in_ru + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + The number of tones in the RU used. + + + +reserved_0a + + + +ppdu_transmission_tsf + + Field only valid when Tx_rate_stats_info_valid is set + + + + Based on a HWSCH configuration register setting, this + field either contains: + + + + Lower 32 bits of the TSF, snapshot of this value when + transmission of the PPDU containing the frame finished. + + OR + + Lower 32 bits of the TSF, snapshot of this value when + transmission of the PPDU containing the frame started + + + + +*/ + + +/* Description TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID + + When set all other fields in this STRUCT contain valid + info. + + + + + +*/ +#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_LSB 0 +#define TX_RATE_STATS_INFO_0_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 + +/* Description TX_RATE_STATS_INFO_0_TRANSMIT_BW + + Field only valid when Tx_rate_stats_info_valid is set + + + + Indicates the BW of the upcoming transmission that shall + likely start in about 3 -4 us on the medium + + + + + + + + + + + + + + +*/ +#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_LSB 1 +#define TX_RATE_STATS_INFO_0_TRANSMIT_BW_MASK 0x00000006 + +/* Description TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + The packet type + + 802.11a PPDU type + + 802.11b PPDU type + + 802.11n Mixed Mode PPDU type + + 802.11ac PPDU type + + 802.11ax PPDU type + + 802.11ba (WUR) PPDU type +*/ +#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_LSB 3 +#define TX_RATE_STATS_INFO_0_TRANSMIT_PKT_TYPE_MASK 0x00000078 + +/* Description TX_RATE_STATS_INFO_0_TRANSMIT_STBC + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + When set, STBC transmission rate was used. +*/ +#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_LSB 7 +#define TX_RATE_STATS_INFO_0_TRANSMIT_STBC_MASK 0x00000080 + +/* Description TX_RATE_STATS_INFO_0_TRANSMIT_LDPC + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + When set, use LDPC transmission rates +*/ +#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_LSB 8 +#define TX_RATE_STATS_INFO_0_TRANSMIT_LDPC_MASK 0x00000100 + +/* Description TX_RATE_STATS_INFO_0_TRANSMIT_SGI + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + Legacy normal GI. Can also be + used for HE + + Legacy short GI. Can also be + used for HE + + HE related GI + + HE related GI + + +*/ +#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_LSB 9 +#define TX_RATE_STATS_INFO_0_TRANSMIT_SGI_MASK 0x00000600 + +/* Description TX_RATE_STATS_INFO_0_TRANSMIT_MCS + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + For details, refer to MCS_TYPE description + + +*/ +#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_LSB 11 +#define TX_RATE_STATS_INFO_0_TRANSMIT_MCS_MASK 0x00007800 + +/* Description TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + + + Set when the transmission was an OFDMA transmission (DL + or UL). + + +*/ +#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_LSB 15 +#define TX_RATE_STATS_INFO_0_OFDMA_TRANSMISSION_MASK 0x00008000 + +/* Description TX_RATE_STATS_INFO_0_TONES_IN_RU + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + The number of tones in the RU used. + + +*/ +#define TX_RATE_STATS_INFO_0_TONES_IN_RU_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_TONES_IN_RU_LSB 16 +#define TX_RATE_STATS_INFO_0_TONES_IN_RU_MASK 0x0fff0000 + +/* Description TX_RATE_STATS_INFO_0_RESERVED_0A + + +*/ +#define TX_RATE_STATS_INFO_0_RESERVED_0A_OFFSET 0x00000000 +#define TX_RATE_STATS_INFO_0_RESERVED_0A_LSB 28 +#define TX_RATE_STATS_INFO_0_RESERVED_0A_MASK 0xf0000000 + +/* Description TX_RATE_STATS_INFO_1_PPDU_TRANSMISSION_TSF + + Field only valid when Tx_rate_stats_info_valid is set + + + + Based on a HWSCH configuration register setting, this + field either contains: + + + + Lower 32 bits of the TSF, snapshot of this value when + transmission of the PPDU containing the frame finished. + + OR + + Lower 32 bits of the TSF, snapshot of this value when + transmission of the PPDU containing the frame started + + + + +*/ +#define TX_RATE_STATS_INFO_1_PPDU_TRANSMISSION_TSF_OFFSET 0x00000004 +#define TX_RATE_STATS_INFO_1_PPDU_TRANSMISSION_TSF_LSB 0 +#define TX_RATE_STATS_INFO_1_PPDU_TRANSMISSION_TSF_MASK 0xffffffff + + +#endif // _TX_RATE_STATS_INFO_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/uniform_descriptor_header.h b/drivers/staging/fw-api/hw/qca6750/v1/uniform_descriptor_header.h new file mode 100644 index 000000000000..c8be900ebf0a --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/uniform_descriptor_header.h @@ -0,0 +1,228 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _UNIFORM_DESCRIPTOR_HEADER_H_ +#define _UNIFORM_DESCRIPTOR_HEADER_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 owner[3:0], buffer_type[7:4], reserved_0a[31:8] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_UNIFORM_DESCRIPTOR_HEADER 1 + +struct uniform_descriptor_header { + uint32_t owner : 4, //[3:0] + buffer_type : 4, //[7:4] + reserved_0a : 24; //[31:8] +}; + +/* + +owner + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + + + The owner of this data structure: + + Buffer Manager currently owns this + data structure. + + Software of FW currently owns + this data structure. + + Transmit Queue Manager currently owns + this data structure. + + Receive DMA currently owns this + data structure. + + Reorder currently owns this data + structure. + + SWITCH currently owns this data + structure. + + + + + +buffer_type + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + + + Field describing what contents format is of this + descriptor + + + + + + + + + + + + + + NOT TO BE USED: + + + + + + + + + + + + + + + + + + + + + + + +reserved_0a + + +*/ + + +/* Description UNIFORM_DESCRIPTOR_HEADER_0_OWNER + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + + + The owner of this data structure: + + Buffer Manager currently owns this + data structure. + + Software of FW currently owns + this data structure. + + Transmit Queue Manager currently owns + this data structure. + + Receive DMA currently owns this + data structure. + + Reorder currently owns this data + structure. + + SWITCH currently owns this data + structure. + + + + +*/ +#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_LSB 0 +#define UNIFORM_DESCRIPTOR_HEADER_0_OWNER_MASK 0x0000000f + +/* Description UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE + + Consumer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + Producer: In DEBUG mode: WBM, TQM, TXDMA, RXDMA, REO + + + + Field describing what contents format is of this + descriptor + + + + + + + + + + + + + + NOT TO BE USED: + + + + + + + + + + + + + + + + + + + + + + +*/ +#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_LSB 4 +#define UNIFORM_DESCRIPTOR_HEADER_0_BUFFER_TYPE_MASK 0x000000f0 + +/* Description UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A + + +*/ +#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_LSB 8 +#define UNIFORM_DESCRIPTOR_HEADER_0_RESERVED_0A_MASK 0xffffff00 + + +#endif // _UNIFORM_DESCRIPTOR_HEADER_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/uniform_reo_cmd_header.h b/drivers/staging/fw-api/hw/qca6750/v1/uniform_reo_cmd_header.h new file mode 100644 index 000000000000..35b87afb8324 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/uniform_reo_cmd_header.h @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _UNIFORM_REO_CMD_HEADER_H_ +#define _UNIFORM_REO_CMD_HEADER_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 reo_cmd_number[15:0], reo_status_required[16], reserved_0a[31:17] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_UNIFORM_REO_CMD_HEADER 1 + +struct uniform_reo_cmd_header { + uint32_t reo_cmd_number : 16, //[15:0] + reo_status_required : 1, //[16] + reserved_0a : 15; //[31:17] +}; + +/* + +reo_cmd_number + + Consumer: REO/SW/DEBUG + + Producer: SW + + + + This number can be used by SW to track, identify and + link the created commands with the command statusses + + + + + + + +reo_status_required + + Consumer: REO + + Producer: SW + + + + REO does not need to generate a status + TLV for the execution of this command + + REO shall generate a status TLV + for the execution of this command + + + + + +reserved_0a + + +*/ + + +/* Description UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER + + Consumer: REO/SW/DEBUG + + Producer: SW + + + + This number can be used by SW to track, identify and + link the created commands with the command statusses + + + + + + +*/ +#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_LSB 0 +#define UNIFORM_REO_CMD_HEADER_0_REO_CMD_NUMBER_MASK 0x0000ffff + +/* Description UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED + + Consumer: REO + + Producer: SW + + + + REO does not need to generate a status + TLV for the execution of this command + + REO shall generate a status TLV + for the execution of this command + + + + +*/ +#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_LSB 16 +#define UNIFORM_REO_CMD_HEADER_0_REO_STATUS_REQUIRED_MASK 0x00010000 + +/* Description UNIFORM_REO_CMD_HEADER_0_RESERVED_0A + + +*/ +#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_LSB 17 +#define UNIFORM_REO_CMD_HEADER_0_RESERVED_0A_MASK 0xfffe0000 + + +#endif // _UNIFORM_REO_CMD_HEADER_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/uniform_reo_status_header.h b/drivers/staging/fw-api/hw/qca6750/v1/uniform_reo_status_header.h new file mode 100644 index 000000000000..9c21d752487b --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/uniform_reo_status_header.h @@ -0,0 +1,249 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _UNIFORM_REO_STATUS_HEADER_H_ +#define _UNIFORM_REO_STATUS_HEADER_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 reo_status_number[15:0], cmd_execution_time[25:16], reo_cmd_execution_status[27:26], reserved_0a[31:28] +// 1 timestamp[31:0] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_UNIFORM_REO_STATUS_HEADER 2 + +struct uniform_reo_status_header { + uint32_t reo_status_number : 16, //[15:0] + cmd_execution_time : 10, //[25:16] + reo_cmd_execution_status : 2, //[27:26] + reserved_0a : 4; //[31:28] + uint32_t timestamp : 32; //[31:0] +}; + +/* + +reo_status_number + + Consumer: SW , DEBUG + + Producer: REO + + + + The value in this field is equal to value of the + 'REO_CMD_Number' field the REO command + + + + This field helps to correlate the statuses with the REO + commands. + + + + + +cmd_execution_time + + Consumer: DEBUG + + Producer: REO + + + + The amount of time REO took to excecute the command. + Note that this time does not include the duration of the + command waiting in the command ring, before the execution + started. + + + + In us. + + + + + +reo_cmd_execution_status + + Consumer: DEBUG + + Producer: REO + + + + Execution status of the command. + + + + Command has + successfully be executed + + Command could not be + executed as the queue or cache was blocked + + Command has encountered + problems when executing, like the queue descriptor not being + valid. None of the status fields in the entire STATUS TLV + are valid. + + Command is NOT executed + because one or more descriptors were blocked. This is SW + programming mistake. + + None of the status fields in the entire STATUS TLV are + valid. + + + + + +reserved_0a + + + +timestamp + + Timestamp at the moment that this status report is + written. + + + + +*/ + + +/* Description UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER + + Consumer: SW , DEBUG + + Producer: REO + + + + The value in this field is equal to value of the + 'REO_CMD_Number' field the REO command + + + + This field helps to correlate the statuses with the REO + commands. + + + + +*/ +#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_LSB 0 +#define UNIFORM_REO_STATUS_HEADER_0_REO_STATUS_NUMBER_MASK 0x0000ffff + +/* Description UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME + + Consumer: DEBUG + + Producer: REO + + + + The amount of time REO took to excecute the command. + Note that this time does not include the duration of the + command waiting in the command ring, before the execution + started. + + + + In us. + + + + +*/ +#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_LSB 16 +#define UNIFORM_REO_STATUS_HEADER_0_CMD_EXECUTION_TIME_MASK 0x03ff0000 + +/* Description UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS + + Consumer: DEBUG + + Producer: REO + + + + Execution status of the command. + + + + Command has + successfully be executed + + Command could not be + executed as the queue or cache was blocked + + Command has encountered + problems when executing, like the queue descriptor not being + valid. None of the status fields in the entire STATUS TLV + are valid. + + Command is NOT executed + because one or more descriptors were blocked. This is SW + programming mistake. + + None of the status fields in the entire STATUS TLV are + valid. + + + + +*/ +#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_LSB 26 +#define UNIFORM_REO_STATUS_HEADER_0_REO_CMD_EXECUTION_STATUS_MASK 0x0c000000 + +/* Description UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A + + +*/ +#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_OFFSET 0x00000000 +#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_LSB 28 +#define UNIFORM_REO_STATUS_HEADER_0_RESERVED_0A_MASK 0xf0000000 + +/* Description UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP + + Timestamp at the moment that this status report is + written. + + + + +*/ +#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_OFFSET 0x00000004 +#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_LSB 0 +#define UNIFORM_REO_STATUS_HEADER_1_TIMESTAMP_MASK 0xffffffff + + +#endif // _UNIFORM_REO_STATUS_HEADER_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/vht_sig_a_info.h b/drivers/staging/fw-api/hw/qca6750/v1/vht_sig_a_info.h new file mode 100644 index 000000000000..f3599fe9a8a1 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/vht_sig_a_info.h @@ -0,0 +1,635 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _VHT_SIG_A_INFO_H_ +#define _VHT_SIG_A_INFO_H_ +#if !defined(__ASSEMBLER__) +#endif + + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0 bandwidth[1:0], vhta_reserved_0[2], stbc[3], group_id[9:4], n_sts[21:10], txop_ps_not_allowed[22], vhta_reserved_0b[23], reserved_0[31:24] +// 1 gi_setting[1:0], su_mu_coding[2], ldpc_extra_symbol[3], mcs[7:4], beamformed[8], vhta_reserved_1[9], crc[17:10], tail[23:18], reserved_1[31:24] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_VHT_SIG_A_INFO 2 + +struct vht_sig_a_info { + uint32_t bandwidth : 2, //[1:0] + vhta_reserved_0 : 1, //[2] + stbc : 1, //[3] + group_id : 6, //[9:4] + n_sts : 12, //[21:10] + txop_ps_not_allowed : 1, //[22] + vhta_reserved_0b : 1, //[23] + reserved_0 : 8; //[31:24] + uint32_t gi_setting : 2, //[1:0] + su_mu_coding : 1, //[2] + ldpc_extra_symbol : 1, //[3] + mcs : 4, //[7:4] + beamformed : 1, //[8] + vhta_reserved_1 : 1, //[9] + crc : 8, //[17:10] + tail : 6, //[23:18] + reserved_1 : 8; //[31:24] +}; + +/* + +bandwidth + + Packet bandwidth + + + + + + + + + + + + + + + +vhta_reserved_0 + + Reserved. Set to 1 by MAC, PHY should ignore + + + +stbc + + Space time block coding: + + Indicates STBC is disabled + + Indicates STBC is enabled on + all streams + + + +group_id + + In a SU VHT PPDU, if the PPDU carries MPDU(s) addressed + to an AP or to a mesh STA, the Group ID field is set to 0, + otherwise it is set to 63. In an NDP PPDU the Group ID is + set according to IEEE 802.11ac_D1.0 Section 9.30.6 + (Transmission of a VHT NDP). For a MU-MIMO PPDU the Group ID + is set as in 802.11ac_D1.0 Section 22.3.11.3 (Group ID). + + +n_sts + + For MU: + + 3 bits/user with maximum of 4 users (user u uses + + vht_sig_a[0][10+3u] - vht_sig_a[0][12+3u]), u = 0, 1, 2, + 3) + + Set to 0 for 0 space time streams + + Set to 1 for 1 space time stream + + Set to 2 for 2 space time streams + + Set to 3 for 3 space time streams + + Set to 4 for 4 space time streams (not supported in Wifi + 3.0) + + Values 5-7 are reserved + + In this field, references to user u should be + interpreted as MU user u. As described in the previous + chapter in this document (see chapter on User number), the + MU user value for a given client is defined for each MU + group that the client participates in. The MU user number is + not related to the internal user number that is used within + the BFer. + + + + + + For SU: + + vht_sig_a[0][12:10] + + Set to 0 for 1 space time stream + + Set to 1 for 2 space time streams + + Set to 2 for 3 space time streams + + Set to 3 for 4 space time streams + + Set to 4 for 5 space time streams + + Set to 5 for 6 space time streams + + Set to 6 for 7 space time streams + + Set to 7 for 8 space time streams + + + + vht_sig_a[0][21:13] + + Partial AID: + + Set to the value of the TXVECTOR parameter PARTIAL_AID. + Partial AID provides an abbreviated indication of the + intended recipient(s) of the frame (see IEEE802.11ac_D1.0 + Section 9.17a (Partial AID in VHT PPDUs)). + + + +txop_ps_not_allowed + + E_num 0 txop_ps_allowed Not supported: If set to by + VHT AP if it allows non-AP VHT STAs in TXOP power save mode + to enter Doze state during a TXOP + + Otherwise + + + +vhta_reserved_0b + + Reserved: Should be set to 1 by the MAC and ignored by + the PHY + +reserved_0 + + This field is not part of HT-SIG: + + Reserved: Should be set to 0 by the MAC and ignored by + the PHY + +gi_setting + + Indicates short guard interval + is not used in the data field + + Indicates short guard interval is + used in the data field + + Indicates short guard + interval is used in the data field and NSYM mod 10 = 9 + + NSYM is defined in IEEE802.11ac_D1.0 Section 22.4.3 + (TXTIME and PSDU_LENGTH calculation). + + + +su_mu_coding + + For an SU PPDU, B2 is set to 0 for BCC, 1 for LDPC For + an MU PPDU, if the MU[0] NSTS field is nonzero(#6773), then + B2 indicates the coding used for user 0; set to 0 for BCC + and 1 for LDPC. If the MU[0] NSTS field is 0, then this + field is reserved and set to 1 + +ldpc_extra_symbol + + Set to 1 if the LDPC PPDU encoding process (if an SU + PPDU), or at least one LDPC user's PPDU encoding process (if + an MU PPDU), results in an extra OFDM symbol (or symbols) as + described in 22.3.10.5.4 (LDPC coding) and 22.3.10.5.5 + (Encoding process for MU PPDUs). Set to 0 otherwise. + +mcs + + For SU: + + Set to 0 for BPSK 1/2 + + Set to 1 for QPSK 1/2 + + Set to 2 for QPSK 3/4 + + Set to 3 for 16-QAM 1/2 + + Set to 4 for 16-QAM 3/4 + + Set to 5 for 64-QAM 2/3 + + Set to 6 for 64-QAM 3/4 + + Set to 7 for 64-QAM 5/6 + + Set to 8 for 256-QAM 3/4 + + Set to 9 for 256-QAM 5/6 + + For MU: + + If NSTS for user 1 is non-zero, then vht_sig_a[1][4] + indicates coding for user 1: set to 0 for BCC, 1 for LDPC. + + If NSTS for user 1 is set to 0, then vht_sig_a[1][4] is + reserved and set to 1. + + If NSTS for user 2 is non-zero, then vht_sig_a[1][5] + indicates coding for user 2: set to 0 for BCC, 1 for LDPC. + + If NSTS for user 2 is set to 0, then vht_sig_a[1][5] is + reserved and set to 1. + + If NSTS for user 3 is non-zero, then vht_sig_a[1][6] + indicates coding for user 3: set to 0 for BCC, 1 for LDPC. + + If NSTS for user 3 is set to 0, then vht_sig_a[1][6] is + reserved and set to 1. + + vht_sig_a[1][7] is reserved and set to 1 + + + +beamformed + + For SU: + + Set to 1 if a Beamforming steering matrix is applied to + the waveform in an SU transmission as described in + IEEE802.11ac_D1.0 Section 19.3.11.11.2 (Spatial mapping), + set to 0 otherwise. + + For MU: + + Reserved and set to 1 + + + +vhta_reserved_1 + + Reserved and set to 1. + +crc + + CRC calculated as in IEEE802.11ac_D1.0 Section + 19.3.9.4.4 (CRC calculation for HTSIG) with C7 in + vht_sig_a[1][10], etc. + +tail + + Used to terminate the trellis of the convolutional + decoder. Set to 0. + +reserved_1 + + This field is not part of HT-SIG: + + Reserved: Should be set to 0 by the MAC and ignored by + the PHY +*/ + + +/* Description VHT_SIG_A_INFO_0_BANDWIDTH + + Packet bandwidth + + + + + + + + + + + + + + +*/ +#define VHT_SIG_A_INFO_0_BANDWIDTH_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_0_BANDWIDTH_LSB 0 +#define VHT_SIG_A_INFO_0_BANDWIDTH_MASK 0x00000003 + +/* Description VHT_SIG_A_INFO_0_VHTA_RESERVED_0 + + Reserved. Set to 1 by MAC, PHY should ignore + + +*/ +#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0_LSB 2 +#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0_MASK 0x00000004 + +/* Description VHT_SIG_A_INFO_0_STBC + + Space time block coding: + + Indicates STBC is disabled + + Indicates STBC is enabled on + all streams + + +*/ +#define VHT_SIG_A_INFO_0_STBC_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_0_STBC_LSB 3 +#define VHT_SIG_A_INFO_0_STBC_MASK 0x00000008 + +/* Description VHT_SIG_A_INFO_0_GROUP_ID + + In a SU VHT PPDU, if the PPDU carries MPDU(s) addressed + to an AP or to a mesh STA, the Group ID field is set to 0, + otherwise it is set to 63. In an NDP PPDU the Group ID is + set according to IEEE 802.11ac_D1.0 Section 9.30.6 + (Transmission of a VHT NDP). For a MU-MIMO PPDU the Group ID + is set as in 802.11ac_D1.0 Section 22.3.11.3 (Group ID). + +*/ +#define VHT_SIG_A_INFO_0_GROUP_ID_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_0_GROUP_ID_LSB 4 +#define VHT_SIG_A_INFO_0_GROUP_ID_MASK 0x000003f0 + +/* Description VHT_SIG_A_INFO_0_N_STS + + For MU: + + 3 bits/user with maximum of 4 users (user u uses + + vht_sig_a[0][10+3u] - vht_sig_a[0][12+3u]), u = 0, 1, 2, + 3) + + Set to 0 for 0 space time streams + + Set to 1 for 1 space time stream + + Set to 2 for 2 space time streams + + Set to 3 for 3 space time streams + + Set to 4 for 4 space time streams (not supported in Wifi + 3.0) + + Values 5-7 are reserved + + In this field, references to user u should be + interpreted as MU user u. As described in the previous + chapter in this document (see chapter on User number), the + MU user value for a given client is defined for each MU + group that the client participates in. The MU user number is + not related to the internal user number that is used within + the BFer. + + + + + + For SU: + + vht_sig_a[0][12:10] + + Set to 0 for 1 space time stream + + Set to 1 for 2 space time streams + + Set to 2 for 3 space time streams + + Set to 3 for 4 space time streams + + Set to 4 for 5 space time streams + + Set to 5 for 6 space time streams + + Set to 6 for 7 space time streams + + Set to 7 for 8 space time streams + + + + vht_sig_a[0][21:13] + + Partial AID: + + Set to the value of the TXVECTOR parameter PARTIAL_AID. + Partial AID provides an abbreviated indication of the + intended recipient(s) of the frame (see IEEE802.11ac_D1.0 + Section 9.17a (Partial AID in VHT PPDUs)). + + +*/ +#define VHT_SIG_A_INFO_0_N_STS_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_0_N_STS_LSB 10 +#define VHT_SIG_A_INFO_0_N_STS_MASK 0x003ffc00 + +/* Description VHT_SIG_A_INFO_0_TXOP_PS_NOT_ALLOWED + + E_num 0 txop_ps_allowed Not supported: If set to by + VHT AP if it allows non-AP VHT STAs in TXOP power save mode + to enter Doze state during a TXOP + + Otherwise + + +*/ +#define VHT_SIG_A_INFO_0_TXOP_PS_NOT_ALLOWED_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_0_TXOP_PS_NOT_ALLOWED_LSB 22 +#define VHT_SIG_A_INFO_0_TXOP_PS_NOT_ALLOWED_MASK 0x00400000 + +/* Description VHT_SIG_A_INFO_0_VHTA_RESERVED_0B + + Reserved: Should be set to 1 by the MAC and ignored by + the PHY +*/ +#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0B_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0B_LSB 23 +#define VHT_SIG_A_INFO_0_VHTA_RESERVED_0B_MASK 0x00800000 + +/* Description VHT_SIG_A_INFO_0_RESERVED_0 + + This field is not part of HT-SIG: + + Reserved: Should be set to 0 by the MAC and ignored by + the PHY +*/ +#define VHT_SIG_A_INFO_0_RESERVED_0_OFFSET 0x00000000 +#define VHT_SIG_A_INFO_0_RESERVED_0_LSB 24 +#define VHT_SIG_A_INFO_0_RESERVED_0_MASK 0xff000000 + +/* Description VHT_SIG_A_INFO_1_GI_SETTING + + Indicates short guard interval + is not used in the data field + + Indicates short guard interval is + used in the data field + + Indicates short guard + interval is used in the data field and NSYM mod 10 = 9 + + NSYM is defined in IEEE802.11ac_D1.0 Section 22.4.3 + (TXTIME and PSDU_LENGTH calculation). + + +*/ +#define VHT_SIG_A_INFO_1_GI_SETTING_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_GI_SETTING_LSB 0 +#define VHT_SIG_A_INFO_1_GI_SETTING_MASK 0x00000003 + +/* Description VHT_SIG_A_INFO_1_SU_MU_CODING + + For an SU PPDU, B2 is set to 0 for BCC, 1 for LDPC For + an MU PPDU, if the MU[0] NSTS field is nonzero(#6773), then + B2 indicates the coding used for user 0; set to 0 for BCC + and 1 for LDPC. If the MU[0] NSTS field is 0, then this + field is reserved and set to 1 +*/ +#define VHT_SIG_A_INFO_1_SU_MU_CODING_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_SU_MU_CODING_LSB 2 +#define VHT_SIG_A_INFO_1_SU_MU_CODING_MASK 0x00000004 + +/* Description VHT_SIG_A_INFO_1_LDPC_EXTRA_SYMBOL + + Set to 1 if the LDPC PPDU encoding process (if an SU + PPDU), or at least one LDPC user's PPDU encoding process (if + an MU PPDU), results in an extra OFDM symbol (or symbols) as + described in 22.3.10.5.4 (LDPC coding) and 22.3.10.5.5 + (Encoding process for MU PPDUs). Set to 0 otherwise. +*/ +#define VHT_SIG_A_INFO_1_LDPC_EXTRA_SYMBOL_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_LDPC_EXTRA_SYMBOL_LSB 3 +#define VHT_SIG_A_INFO_1_LDPC_EXTRA_SYMBOL_MASK 0x00000008 + +/* Description VHT_SIG_A_INFO_1_MCS + + For SU: + + Set to 0 for BPSK 1/2 + + Set to 1 for QPSK 1/2 + + Set to 2 for QPSK 3/4 + + Set to 3 for 16-QAM 1/2 + + Set to 4 for 16-QAM 3/4 + + Set to 5 for 64-QAM 2/3 + + Set to 6 for 64-QAM 3/4 + + Set to 7 for 64-QAM 5/6 + + Set to 8 for 256-QAM 3/4 + + Set to 9 for 256-QAM 5/6 + + For MU: + + If NSTS for user 1 is non-zero, then vht_sig_a[1][4] + indicates coding for user 1: set to 0 for BCC, 1 for LDPC. + + If NSTS for user 1 is set to 0, then vht_sig_a[1][4] is + reserved and set to 1. + + If NSTS for user 2 is non-zero, then vht_sig_a[1][5] + indicates coding for user 2: set to 0 for BCC, 1 for LDPC. + + If NSTS for user 2 is set to 0, then vht_sig_a[1][5] is + reserved and set to 1. + + If NSTS for user 3 is non-zero, then vht_sig_a[1][6] + indicates coding for user 3: set to 0 for BCC, 1 for LDPC. + + If NSTS for user 3 is set to 0, then vht_sig_a[1][6] is + reserved and set to 1. + + vht_sig_a[1][7] is reserved and set to 1 + + +*/ +#define VHT_SIG_A_INFO_1_MCS_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_MCS_LSB 4 +#define VHT_SIG_A_INFO_1_MCS_MASK 0x000000f0 + +/* Description VHT_SIG_A_INFO_1_BEAMFORMED + + For SU: + + Set to 1 if a Beamforming steering matrix is applied to + the waveform in an SU transmission as described in + IEEE802.11ac_D1.0 Section 19.3.11.11.2 (Spatial mapping), + set to 0 otherwise. + + For MU: + + Reserved and set to 1 + + +*/ +#define VHT_SIG_A_INFO_1_BEAMFORMED_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_BEAMFORMED_LSB 8 +#define VHT_SIG_A_INFO_1_BEAMFORMED_MASK 0x00000100 + +/* Description VHT_SIG_A_INFO_1_VHTA_RESERVED_1 + + Reserved and set to 1. +*/ +#define VHT_SIG_A_INFO_1_VHTA_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_VHTA_RESERVED_1_LSB 9 +#define VHT_SIG_A_INFO_1_VHTA_RESERVED_1_MASK 0x00000200 + +/* Description VHT_SIG_A_INFO_1_CRC + + CRC calculated as in IEEE802.11ac_D1.0 Section + 19.3.9.4.4 (CRC calculation for HTSIG) with C7 in + vht_sig_a[1][10], etc. +*/ +#define VHT_SIG_A_INFO_1_CRC_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_CRC_LSB 10 +#define VHT_SIG_A_INFO_1_CRC_MASK 0x0003fc00 + +/* Description VHT_SIG_A_INFO_1_TAIL + + Used to terminate the trellis of the convolutional + decoder. Set to 0. +*/ +#define VHT_SIG_A_INFO_1_TAIL_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_TAIL_LSB 18 +#define VHT_SIG_A_INFO_1_TAIL_MASK 0x00fc0000 + +/* Description VHT_SIG_A_INFO_1_RESERVED_1 + + This field is not part of HT-SIG: + + Reserved: Should be set to 0 by the MAC and ignored by + the PHY +*/ +#define VHT_SIG_A_INFO_1_RESERVED_1_OFFSET 0x00000004 +#define VHT_SIG_A_INFO_1_RESERVED_1_LSB 24 +#define VHT_SIG_A_INFO_1_RESERVED_1_MASK 0xff000000 + + +#endif // _VHT_SIG_A_INFO_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/wbm_buffer_ring.h b/drivers/staging/fw-api/hw/qca6750/v1/wbm_buffer_ring.h new file mode 100644 index 000000000000..61a8f4c778cb --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/wbm_buffer_ring.h @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _WBM_BUFFER_RING_H_ +#define _WBM_BUFFER_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct buffer_addr_info buf_addr_info; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_WBM_BUFFER_RING 2 + +struct wbm_buffer_ring { + struct buffer_addr_info buf_addr_info; +}; + +/* + +struct buffer_addr_info buf_addr_info + + Consumer: WBM + + Producer: WBM + + + + Details of the physical address of the buffer + source + buffer owner + some SW meta data. + + All modules getting this buffer address info, shall keep + all the 64 bits of info in this descriptor together and + eventually all 64 bits shall be given back to WMB when the + buffer is released. +*/ + + + /* EXTERNAL REFERENCE : struct buffer_addr_info buf_addr_info */ + + +/* Description WBM_BUFFER_RING_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define WBM_BUFFER_RING_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_BUFFER_RING_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_BUFFER_RING_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description WBM_BUFFER_RING_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description WBM_BUFFER_RING_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + +*/ +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description WBM_BUFFER_RING_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define WBM_BUFFER_RING_1_BUF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + + +#endif // _WBM_BUFFER_RING_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/wbm_link_descriptor_ring.h b/drivers/staging/fw-api/hw/qca6750/v1/wbm_link_descriptor_ring.h new file mode 100644 index 000000000000..cc457fd47249 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/wbm_link_descriptor_ring.h @@ -0,0 +1,224 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _WBM_LINK_DESCRIPTOR_RING_H_ +#define _WBM_LINK_DESCRIPTOR_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct buffer_addr_info desc_addr_info; +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_WBM_LINK_DESCRIPTOR_RING 2 + +struct wbm_link_descriptor_ring { + struct buffer_addr_info desc_addr_info; +}; + +/* + +struct buffer_addr_info desc_addr_info + + Consumer: WBM + + Producer: WBM + + + + Details of the physical address of the buffer + source + buffer owner + some SW meta data + + All modules getting this link descriptor address info, + shall keep all the 64 bits in this descriptor together and + eventually all 64 bits shall be given back to WBM when the + link descriptor is released. +*/ + + + /* EXTERNAL REFERENCE : struct buffer_addr_info desc_addr_info */ + + +/* Description WBM_LINK_DESCRIPTOR_RING_0_DESC_ADDR_INFO_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define WBM_LINK_DESCRIPTOR_RING_0_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_LINK_DESCRIPTOR_RING_0_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_LINK_DESCRIPTOR_RING_0_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + +*/ +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define WBM_LINK_DESCRIPTOR_RING_1_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + + +#endif // _WBM_LINK_DESCRIPTOR_RING_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/wbm_reg_seq_hwiobase.h b/drivers/staging/fw-api/hw/qca6750/v1/wbm_reg_seq_hwiobase.h new file mode 100644 index 000000000000..bb20bcf735c9 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/wbm_reg_seq_hwiobase.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/////////////////////////////////////////////////////////////////////////////////////////////// +// +// wbm_reg_seq_hwiobase.h : automatically generated by Autoseq 3.8 11/13/2019 +// User Name:sanjdas +// +// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. +// +/////////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef __WBM_REG_SEQ_BASE_H__ +#define __WBM_REG_SEQ_BASE_H__ + +#ifdef SCALE_INCLUDES + #include "HALhwio.h" +#else + #include "msmhwio.h" +#endif + + +#endif + diff --git a/drivers/staging/fw-api/hw/qca6750/v1/wbm_reg_seq_hwioreg.h b/drivers/staging/fw-api/hw/qca6750/v1/wbm_reg_seq_hwioreg.h new file mode 100644 index 000000000000..7b1fb0cbc0a0 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/wbm_reg_seq_hwioreg.h @@ -0,0 +1,12237 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/////////////////////////////////////////////////////////////////////////////////////////////// +// +// wbm_reg_seq_hwioreg.h : automatically generated by Autoseq 3.8 11/13/2019 +// User Name:sanjdas +// +// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. +// +/////////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef __WBM_REG_SEQ_REG_H__ +#define __WBM_REG_SEQ_REG_H__ + +#include "seq_hwio.h" +#include "wbm_reg_seq_hwiobase.h" +#ifdef SCALE_INCLUDES + #include "HALhwio.h" +#else + #include "msmhwio.h" +#endif + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Register Data for Block WBM_REG +/////////////////////////////////////////////////////////////////////////////////////////////// + +//// Register WBM_R0_GENERAL_ENABLE //// + +#define HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x) (x+0x00000000) +#define HWIO_WBM_R0_GENERAL_ENABLE_PHYS(x) (x+0x00000000) +#define HWIO_WBM_R0_GENERAL_ENABLE_RMSK 0x000000ff +#define HWIO_WBM_R0_GENERAL_ENABLE_SHFT 0 +#define HWIO_WBM_R0_GENERAL_ENABLE_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x), HWIO_WBM_R0_GENERAL_ENABLE_RMSK) +#define HWIO_WBM_R0_GENERAL_ENABLE_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x), mask) +#define HWIO_WBM_R0_GENERAL_ENABLE_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x), val) +#define HWIO_WBM_R0_GENERAL_ENABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GENERAL_ENABLE_ADDR(x), mask, val, HWIO_WBM_R0_GENERAL_ENABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_DESC_CONTENT_CLEAR_ENABLE_BMSK 0x00000080 +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_DESC_CONTENT_CLEAR_ENABLE_SHFT 0x7 + +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_DESC_BYPASS_DISABLE_BMSK 0x00000040 +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_DESC_BYPASS_DISABLE_SHFT 0x6 + +#define HWIO_WBM_R0_GENERAL_ENABLE_MSDU_BUFFER_BYPASS_DISABLE_BMSK 0x00000020 +#define HWIO_WBM_R0_GENERAL_ENABLE_MSDU_BUFFER_BYPASS_DISABLE_SHFT 0x5 + +#define HWIO_WBM_R0_GENERAL_ENABLE_RELEASE_FUNCTION_ENABLE_BMSK 0x00000010 +#define HWIO_WBM_R0_GENERAL_ENABLE_RELEASE_FUNCTION_ENABLE_SHFT 0x4 + +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_IDLE_LIST_CONSUMER_ENABLE_BMSK 0x00000008 +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_IDLE_LIST_CONSUMER_ENABLE_SHFT 0x3 + +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_IDLE_LIST_PRODUCER_ENABLE_BMSK 0x00000004 +#define HWIO_WBM_R0_GENERAL_ENABLE_LINK_IDLE_LIST_PRODUCER_ENABLE_SHFT 0x2 + +#define HWIO_WBM_R0_GENERAL_ENABLE_BUFFER_IDLE_LIST_CONSUMER_ENABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_GENERAL_ENABLE_BUFFER_IDLE_LIST_CONSUMER_ENABLE_SHFT 0x1 + +#define HWIO_WBM_R0_GENERAL_ENABLE_BUFFER_IDLE_LIST_PRODUCER_ENABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_GENERAL_ENABLE_BUFFER_IDLE_LIST_PRODUCER_ENABLE_SHFT 0x0 + +//// Register WBM_R0_RELEASE_RING_ENABLE //// + +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x) (x+0x00000004) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_PHYS(x) (x+0x00000004) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_RMSK 0x000000ff +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_SHFT 0 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x), HWIO_WBM_R0_RELEASE_RING_ENABLE_RMSK) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x), mask) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x), val) +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RELEASE_RING_ENABLE_ADDR(x), mask, val, HWIO_WBM_R0_RELEASE_RING_ENABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_RXDMA2_RELEASE_RING_ENABLE_BMSK 0x00000080 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_RXDMA2_RELEASE_RING_ENABLE_SHFT 0x7 + +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_RXDMA1_RELEASE_RING_ENABLE_BMSK 0x00000040 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_RXDMA1_RELEASE_RING_ENABLE_SHFT 0x6 + +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_RXDMA0_RELEASE_RING_ENABLE_BMSK 0x00000020 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_RXDMA0_RELEASE_RING_ENABLE_SHFT 0x5 + +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_FW_RELEASE_RING_ENABLE_BMSK 0x00000010 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_FW_RELEASE_RING_ENABLE_SHFT 0x4 + +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_SW_RELEASE_RING_ENABLE_BMSK 0x00000008 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_SW_RELEASE_RING_ENABLE_SHFT 0x3 + +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_REO_RELEASE_RING_ENABLE_BMSK 0x00000004 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_REO_RELEASE_RING_ENABLE_SHFT 0x2 + +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_TQM_RELEASE_RING_ENABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_TQM_RELEASE_RING_ENABLE_SHFT 0x1 + +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_PPE_RELEASE_RING_ENABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_RELEASE_RING_ENABLE_PPE_RELEASE_RING_ENABLE_SHFT 0x0 + +//// Register WBM_R0_MSDU_BUFFER_RING_ENABLE //// + +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x) (x+0x00000008) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_PHYS(x) (x+0x00000008) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_RMSK 0x0000003f +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_SHFT 0 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x), HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_RMSK) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x), mask) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_OUT(x, val) \ + out_dword( HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x), val) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_ADDR(x), mask, val, HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2RXDMA2_BUF_RING_ENABLE_BMSK 0x00000020 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2RXDMA2_BUF_RING_ENABLE_SHFT 0x5 + +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2RXDMA1_BUF_RING_ENABLE_BMSK 0x00000010 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2RXDMA1_BUF_RING_ENABLE_SHFT 0x4 + +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2RXDMA0_BUF_RING_ENABLE_BMSK 0x00000008 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2RXDMA0_BUF_RING_ENABLE_SHFT 0x3 + +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2FW_BUF_RING_ENABLE_BMSK 0x00000004 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2FW_BUF_RING_ENABLE_SHFT 0x2 + +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2SW_BUF_RING_ENABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2SW_BUF_RING_ENABLE_SHFT 0x1 + +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2PPE_BUF_RING_ENABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_ENABLE_WBM2PPE_BUF_RING_ENABLE_SHFT 0x0 + +//// Register WBM_R0_LINK_DESC_RING_ENABLE //// + +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x) (x+0x0000000c) +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_PHYS(x) (x+0x0000000c) +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_RMSK 0x0000007f +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_SHFT 0 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x), HWIO_WBM_R0_LINK_DESC_RING_ENABLE_RMSK) +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x), mask) +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_OUT(x, val) \ + out_dword( HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x), val) +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_LINK_DESC_RING_ENABLE_ADDR(x), mask, val, HWIO_WBM_R0_LINK_DESC_RING_ENABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2RXDMA2_LINK_RING_ENABLE_BMSK 0x00000040 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2RXDMA2_LINK_RING_ENABLE_SHFT 0x6 + +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2RXDMA1_LINK_RING_ENABLE_BMSK 0x00000020 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2RXDMA1_LINK_RING_ENABLE_SHFT 0x5 + +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2RXDMA0_LINK_RING_ENABLE_BMSK 0x00000010 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2RXDMA0_LINK_RING_ENABLE_SHFT 0x4 + +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2FW_LINK_RING_ENABLE_BMSK 0x00000008 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2FW_LINK_RING_ENABLE_SHFT 0x3 + +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2SW_LINK_RING_ENABLE_BMSK 0x00000004 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2SW_LINK_RING_ENABLE_SHFT 0x2 + +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2REO_LINK_RING_ENABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2REO_LINK_RING_ENABLE_SHFT 0x1 + +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2TQM_LINK_RING_ENABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_LINK_DESC_RING_ENABLE_WBM2TQM_LINK_RING_ENABLE_SHFT 0x0 + +//// Register WBM_R0_MISC_RING_ENABLE //// + +#define HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x) (x+0x00000010) +#define HWIO_WBM_R0_MISC_RING_ENABLE_PHYS(x) (x+0x00000010) +#define HWIO_WBM_R0_MISC_RING_ENABLE_RMSK 0x0000003f +#define HWIO_WBM_R0_MISC_RING_ENABLE_SHFT 0 +#define HWIO_WBM_R0_MISC_RING_ENABLE_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x), HWIO_WBM_R0_MISC_RING_ENABLE_RMSK) +#define HWIO_WBM_R0_MISC_RING_ENABLE_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x), mask) +#define HWIO_WBM_R0_MISC_RING_ENABLE_OUT(x, val) \ + out_dword( HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x), val) +#define HWIO_WBM_R0_MISC_RING_ENABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_MISC_RING_ENABLE_ADDR(x), mask, val, HWIO_WBM_R0_MISC_RING_ENABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW4_RELEASE_RING_ENABLE_BMSK 0x00000020 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW4_RELEASE_RING_ENABLE_SHFT 0x5 + +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW3_RELEASE_RING_ENABLE_BMSK 0x00000010 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW3_RELEASE_RING_ENABLE_SHFT 0x4 + +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW2_RELEASE_RING_ENABLE_BMSK 0x00000008 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW2_RELEASE_RING_ENABLE_SHFT 0x3 + +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW1_RELEASE_RING_ENABLE_BMSK 0x00000004 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW1_RELEASE_RING_ENABLE_SHFT 0x2 + +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW0_RELEASE_RING_ENABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2SW0_RELEASE_RING_ENABLE_SHFT 0x1 + +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2FW_RELEASE_RING_ENABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_MISC_RING_ENABLE_WBM2FW_RELEASE_RING_ENABLE_SHFT 0x0 + +//// Register WBM_R0_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x) (x+0x00000014) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_PHYS(x) (x+0x00000014) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_RMSK 0x000000ff +#define HWIO_WBM_R0_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RELEASE_RING_STATUS_RXDMA2_RELEASE_RING_NOT_IDLE_BMSK 0x00000080 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_RXDMA2_RELEASE_RING_NOT_IDLE_SHFT 0x7 + +#define HWIO_WBM_R0_RELEASE_RING_STATUS_RXDMA1_RELEASE_RING_NOT_IDLE_BMSK 0x00000040 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_RXDMA1_RELEASE_RING_NOT_IDLE_SHFT 0x6 + +#define HWIO_WBM_R0_RELEASE_RING_STATUS_RXDMA0_RELEASE_RING_NOT_IDLE_BMSK 0x00000020 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_RXDMA0_RELEASE_RING_NOT_IDLE_SHFT 0x5 + +#define HWIO_WBM_R0_RELEASE_RING_STATUS_FW_RELEASE_RING_NOT_IDLE_BMSK 0x00000010 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_FW_RELEASE_RING_NOT_IDLE_SHFT 0x4 + +#define HWIO_WBM_R0_RELEASE_RING_STATUS_SW_RELEASE_RING_NOT_IDLE_BMSK 0x00000008 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_SW_RELEASE_RING_NOT_IDLE_SHFT 0x3 + +#define HWIO_WBM_R0_RELEASE_RING_STATUS_REO_RELEASE_RING_NOT_IDLE_BMSK 0x00000004 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_REO_RELEASE_RING_NOT_IDLE_SHFT 0x2 + +#define HWIO_WBM_R0_RELEASE_RING_STATUS_TQM_RELEASE_RING_NOT_IDLE_BMSK 0x00000002 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_TQM_RELEASE_RING_NOT_IDLE_SHFT 0x1 + +#define HWIO_WBM_R0_RELEASE_RING_STATUS_PPE_RELEASE_RING_NOT_IDLE_BMSK 0x00000001 +#define HWIO_WBM_R0_RELEASE_RING_STATUS_PPE_RELEASE_RING_NOT_IDLE_SHFT 0x0 + +//// Register WBM_R0_MSDU_BUFFER_RING_STATUS //// + +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x) (x+0x00000018) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_PHYS(x) (x+0x00000018) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_RMSK 0x0000003f +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x), HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_RMSK) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2RXDMA2_BUF_RING_NOT_IDLE_BMSK 0x00000020 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2RXDMA2_BUF_RING_NOT_IDLE_SHFT 0x5 + +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2RXDMA1_BUF_RING_NOT_IDLE_BMSK 0x00000010 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2RXDMA1_BUF_RING_NOT_IDLE_SHFT 0x4 + +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2RXDMA0_BUF_RING_NOT_IDLE_BMSK 0x00000008 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2RXDMA0_BUF_RING_NOT_IDLE_SHFT 0x3 + +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2FW_BUF_RING_NOT_IDLE_BMSK 0x00000004 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2FW_BUF_RING_NOT_IDLE_SHFT 0x2 + +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2SW_BUF_RING_NOT_IDLE_BMSK 0x00000002 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2SW_BUF_RING_NOT_IDLE_SHFT 0x1 + +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2PPE_BUF_RING_NOT_IDLE_BMSK 0x00000001 +#define HWIO_WBM_R0_MSDU_BUFFER_RING_STATUS_WBM2PPE_BUF_RING_NOT_IDLE_SHFT 0x0 + +//// Register WBM_R0_LINK_DESC_RING_STATUS //// + +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x) (x+0x0000001c) +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_PHYS(x) (x+0x0000001c) +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_RMSK 0x0000007f +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x), HWIO_WBM_R0_LINK_DESC_RING_STATUS_RMSK) +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_LINK_DESC_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_LINK_DESC_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2RXDMA2_LINK_RING_NOT_IDLE_BMSK 0x00000040 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2RXDMA2_LINK_RING_NOT_IDLE_SHFT 0x6 + +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2RXDMA1_LINK_RING_NOT_IDLE_BMSK 0x00000020 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2RXDMA1_LINK_RING_NOT_IDLE_SHFT 0x5 + +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2RXDMA0_LINK_RING_NOT_IDLE_BMSK 0x00000010 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2RXDMA0_LINK_RING_NOT_IDLE_SHFT 0x4 + +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2FW_LINK_RING_NOT_IDLE_BMSK 0x00000008 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2FW_LINK_RING_NOT_IDLE_SHFT 0x3 + +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2SW_LINK_RING_NOT_IDLE_BMSK 0x00000004 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2SW_LINK_RING_NOT_IDLE_SHFT 0x2 + +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2REO_LINK_RING_NOT_IDLE_BMSK 0x00000002 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2REO_LINK_RING_NOT_IDLE_SHFT 0x1 + +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2TQM_LINK_RING_NOT_IDLE_BMSK 0x00000001 +#define HWIO_WBM_R0_LINK_DESC_RING_STATUS_WBM2TQM_LINK_RING_NOT_IDLE_SHFT 0x0 + +//// Register WBM_R0_MISC_RING_STATUS //// + +#define HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x) (x+0x00000020) +#define HWIO_WBM_R0_MISC_RING_STATUS_PHYS(x) (x+0x00000020) +#define HWIO_WBM_R0_MISC_RING_STATUS_RMSK 0x000003ff +#define HWIO_WBM_R0_MISC_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_MISC_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x), HWIO_WBM_R0_MISC_RING_STATUS_RMSK) +#define HWIO_WBM_R0_MISC_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_MISC_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_MISC_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_MISC_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_MISC_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_MISC_RING_STATUS_SW4_BUFFER_RING_NOT_IDLE_BMSK 0x00000200 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW4_BUFFER_RING_NOT_IDLE_SHFT 0x9 + +#define HWIO_WBM_R0_MISC_RING_STATUS_SW3_BUFFER_RING_NOT_IDLE_BMSK 0x00000100 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW3_BUFFER_RING_NOT_IDLE_SHFT 0x8 + +#define HWIO_WBM_R0_MISC_RING_STATUS_SW2_BUFFER_RING_NOT_IDLE_BMSK 0x00000080 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW2_BUFFER_RING_NOT_IDLE_SHFT 0x7 + +#define HWIO_WBM_R0_MISC_RING_STATUS_SW1_BUFFER_RING_NOT_IDLE_BMSK 0x00000040 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW1_BUFFER_RING_NOT_IDLE_SHFT 0x6 + +#define HWIO_WBM_R0_MISC_RING_STATUS_SW0_BUFFER_RING_NOT_IDLE_BMSK 0x00000020 +#define HWIO_WBM_R0_MISC_RING_STATUS_SW0_BUFFER_RING_NOT_IDLE_SHFT 0x5 + +#define HWIO_WBM_R0_MISC_RING_STATUS_FW_BUFFER_RING_NOT_IDLE_BMSK 0x00000010 +#define HWIO_WBM_R0_MISC_RING_STATUS_FW_BUFFER_RING_NOT_IDLE_SHFT 0x4 + +#define HWIO_WBM_R0_MISC_RING_STATUS_LINK_IDLE_LIST_CONSUMER_NOT_IDLE_BMSK 0x00000008 +#define HWIO_WBM_R0_MISC_RING_STATUS_LINK_IDLE_LIST_CONSUMER_NOT_IDLE_SHFT 0x3 + +#define HWIO_WBM_R0_MISC_RING_STATUS_LINK_IDLE_LIST_PRODUCER_NOT_IDLE_BMSK 0x00000004 +#define HWIO_WBM_R0_MISC_RING_STATUS_LINK_IDLE_LIST_PRODUCER_NOT_IDLE_SHFT 0x2 + +#define HWIO_WBM_R0_MISC_RING_STATUS_BUFFER_IDLE_LIST_CONSUMER_NOT_IDLE_BMSK 0x00000002 +#define HWIO_WBM_R0_MISC_RING_STATUS_BUFFER_IDLE_LIST_CONSUMER_NOT_IDLE_SHFT 0x1 + +#define HWIO_WBM_R0_MISC_RING_STATUS_BUFFER_IDLE_LIST_PRODUCER_NOT_IDLE_BMSK 0x00000001 +#define HWIO_WBM_R0_MISC_RING_STATUS_BUFFER_IDLE_LIST_PRODUCER_NOT_IDLE_SHFT 0x0 + +//// Register WBM_R0_RELEASE_RING_FLUSH //// + +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x) (x+0x00000024) +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_PHYS(x) (x+0x00000024) +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RMSK 0x00013fff +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_SHFT 0 +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x), HWIO_WBM_R0_RELEASE_RING_FLUSH_RMSK) +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x), mask) +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x), val) +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RELEASE_RING_FLUSH_ADDR(x), mask, val, HWIO_WBM_R0_RELEASE_RING_FLUSH_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_IN_FLUSH_BMSK 0x00010000 +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_IN_FLUSH_SHFT 0x10 + +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_SW_RELEASE_FIFO_FLUSH_BMSK 0x00002000 +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_SW_RELEASE_FIFO_FLUSH_SHFT 0xd + +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_SW_RELEASE_RING_AGE_FLUSH_BMSK 0x00001000 +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_SW_RELEASE_RING_AGE_FLUSH_SHFT 0xc + +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_TIMEOUT_BMSK 0x00000fff +#define HWIO_WBM_R0_RELEASE_RING_FLUSH_RELEASE_RING_AGE_TIMEOUT_SHFT 0x0 + +//// Register WBM_R0_IDLE_STATUS //// + +#define HWIO_WBM_R0_IDLE_STATUS_ADDR(x) (x+0x00000028) +#define HWIO_WBM_R0_IDLE_STATUS_PHYS(x) (x+0x00000028) +#define HWIO_WBM_R0_IDLE_STATUS_RMSK 0x0000ffff +#define HWIO_WBM_R0_IDLE_STATUS_SHFT 0 +#define HWIO_WBM_R0_IDLE_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_IDLE_STATUS_ADDR(x), HWIO_WBM_R0_IDLE_STATUS_RMSK) +#define HWIO_WBM_R0_IDLE_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_IDLE_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_IDLE_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_IDLE_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_IDLE_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_IDLE_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_IDLE_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_IDLE_STATUS_ALL_IN_IDLE_BMSK 0x00008000 +#define HWIO_WBM_R0_IDLE_STATUS_ALL_IN_IDLE_SHFT 0xf + +#define HWIO_WBM_R0_IDLE_STATUS_ALL_APPLICATION_LOGIC_IN_IDLE_BMSK 0x00004000 +#define HWIO_WBM_R0_IDLE_STATUS_ALL_APPLICATION_LOGIC_IN_IDLE_SHFT 0xe + +#define HWIO_WBM_R0_IDLE_STATUS_ALL_CONSUMER_RINGS_IN_IDLE_BMSK 0x00002000 +#define HWIO_WBM_R0_IDLE_STATUS_ALL_CONSUMER_RINGS_IN_IDLE_SHFT 0xd + +#define HWIO_WBM_R0_IDLE_STATUS_ALL_PRODUCER_RINGS_IN_IDLE_BMSK 0x00001000 +#define HWIO_WBM_R0_IDLE_STATUS_ALL_PRODUCER_RINGS_IN_IDLE_SHFT 0xc + +#define HWIO_WBM_R0_IDLE_STATUS_SW4_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x00000800 +#define HWIO_WBM_R0_IDLE_STATUS_SW4_BUFFER_PROD_FIFO_IN_IDLE_SHFT 0xb + +#define HWIO_WBM_R0_IDLE_STATUS_SW3_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x00000400 +#define HWIO_WBM_R0_IDLE_STATUS_SW3_BUFFER_PROD_FIFO_IN_IDLE_SHFT 0xa + +#define HWIO_WBM_R0_IDLE_STATUS_SW2_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x00000200 +#define HWIO_WBM_R0_IDLE_STATUS_SW2_BUFFER_PROD_FIFO_IN_IDLE_SHFT 0x9 + +#define HWIO_WBM_R0_IDLE_STATUS_SW1_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x00000100 +#define HWIO_WBM_R0_IDLE_STATUS_SW1_BUFFER_PROD_FIFO_IN_IDLE_SHFT 0x8 + +#define HWIO_WBM_R0_IDLE_STATUS_SW0_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x00000080 +#define HWIO_WBM_R0_IDLE_STATUS_SW0_BUFFER_PROD_FIFO_IN_IDLE_SHFT 0x7 + +#define HWIO_WBM_R0_IDLE_STATUS_FW_BUFFER_PROD_FIFO_IN_IDLE_BMSK 0x00000040 +#define HWIO_WBM_R0_IDLE_STATUS_FW_BUFFER_PROD_FIFO_IN_IDLE_SHFT 0x6 + +#define HWIO_WBM_R0_IDLE_STATUS_LINK_DESC_ZERO_OUT_FIFO_IN_IDLE_BMSK 0x00000020 +#define HWIO_WBM_R0_IDLE_STATUS_LINK_DESC_ZERO_OUT_FIFO_IN_IDLE_SHFT 0x5 + +#define HWIO_WBM_R0_IDLE_STATUS_LINK_IDLE_LIST_DIST_FIFO_IN_IDLE_BMSK 0x00000010 +#define HWIO_WBM_R0_IDLE_STATUS_LINK_IDLE_LIST_DIST_FIFO_IN_IDLE_SHFT 0x4 + +#define HWIO_WBM_R0_IDLE_STATUS_LINK_IDLE_LIST_PROD_FIFO_IN_IDLE_BMSK 0x00000008 +#define HWIO_WBM_R0_IDLE_STATUS_LINK_IDLE_LIST_PROD_FIFO_IN_IDLE_SHFT 0x3 + +#define HWIO_WBM_R0_IDLE_STATUS_BUFFER_IDLE_LIST_DIST_FIFO_IN_IDLE_BMSK 0x00000004 +#define HWIO_WBM_R0_IDLE_STATUS_BUFFER_IDLE_LIST_DIST_FIFO_IN_IDLE_SHFT 0x2 + +#define HWIO_WBM_R0_IDLE_STATUS_BUFFER_IDLE_LIST_PROD_FIFO_IN_IDLE_BMSK 0x00000002 +#define HWIO_WBM_R0_IDLE_STATUS_BUFFER_IDLE_LIST_PROD_FIFO_IN_IDLE_SHFT 0x1 + +#define HWIO_WBM_R0_IDLE_STATUS_RELEASE_PARSER_FIFO_IN_IDLE_BMSK 0x00000001 +#define HWIO_WBM_R0_IDLE_STATUS_RELEASE_PARSER_FIFO_IN_IDLE_SHFT 0x0 + +//// Register WBM_R0_IDLE_SEQUENCE //// + +#define HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x) (x+0x0000002c) +#define HWIO_WBM_R0_IDLE_SEQUENCE_PHYS(x) (x+0x0000002c) +#define HWIO_WBM_R0_IDLE_SEQUENCE_RMSK 0x0000003f +#define HWIO_WBM_R0_IDLE_SEQUENCE_SHFT 0 +#define HWIO_WBM_R0_IDLE_SEQUENCE_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x), HWIO_WBM_R0_IDLE_SEQUENCE_RMSK) +#define HWIO_WBM_R0_IDLE_SEQUENCE_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x), mask) +#define HWIO_WBM_R0_IDLE_SEQUENCE_OUT(x, val) \ + out_dword( HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x), val) +#define HWIO_WBM_R0_IDLE_SEQUENCE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_IDLE_SEQUENCE_ADDR(x), mask, val, HWIO_WBM_R0_IDLE_SEQUENCE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_IDLE_SEQUENCE_WBM_RELEASE_RING_NOT_EMPTY_BMSK 0x00000020 +#define HWIO_WBM_R0_IDLE_SEQUENCE_WBM_RELEASE_RING_NOT_EMPTY_SHFT 0x5 + +#define HWIO_WBM_R0_IDLE_SEQUENCE_WBM_IN_IDLE_BMSK 0x00000010 +#define HWIO_WBM_R0_IDLE_SEQUENCE_WBM_IN_IDLE_SHFT 0x4 + +#define HWIO_WBM_R0_IDLE_SEQUENCE_IDLE_SEQUENCE_STATE_BMSK 0x0000000f +#define HWIO_WBM_R0_IDLE_SEQUENCE_IDLE_SEQUENCE_STATE_SHFT 0x0 + +//// Register WBM_R0_MSDU_PARSER_CONTROL //// + +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x) (x+0x00000030) +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_PHYS(x) (x+0x00000030) +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_RMSK 0x00000007 +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_SHFT 0 +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x), HWIO_WBM_R0_MSDU_PARSER_CONTROL_RMSK) +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x), mask) +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_OUT(x, val) \ + out_dword( HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x), val) +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_MSDU_PARSER_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_MSDU_PARSER_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_DISABLE_CACHE_2_BMSK 0x00000004 +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_DISABLE_CACHE_2_SHFT 0x2 + +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_2_BMSK 0x00000002 +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_2_SHFT 0x1 + +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_1_BMSK 0x00000001 +#define HWIO_WBM_R0_MSDU_PARSER_CONTROL_FLUSH_CACHE_1_SHFT 0x0 + +//// Register WBM_R0_MSDU_PARSER_STATUS //// + +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x) (x+0x00000034) +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_PHYS(x) (x+0x00000034) +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_RMSK 0x00000fff +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_SHFT 0 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x), HWIO_WBM_R0_MSDU_PARSER_STATUS_RMSK) +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_MSDU_PARSER_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_MSDU_PARSER_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_FLUSH_CACHE_1_DONE_BMSK 0x00000800 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_FLUSH_CACHE_1_DONE_SHFT 0xb + +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_EMPTY_BMSK 0x00000400 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_EMPTY_SHFT 0xa + +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_DELINK_PARSER_STATE_BMSK 0x000003c0 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_DELINK_PARSER_STATE_SHFT 0x6 + +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_IN_IDLE_BMSK 0x00000020 +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_MSDU_PARSER_CMD_FIFO_IN_IDLE_SHFT 0x5 + +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_CACHE_1_STATE_BMSK 0x0000001f +#define HWIO_WBM_R0_MSDU_PARSER_STATUS_CACHE_1_STATE_SHFT 0x0 + +//// Register WBM_R0_MISC_CONTROL //// + +#define HWIO_WBM_R0_MISC_CONTROL_ADDR(x) (x+0x00000038) +#define HWIO_WBM_R0_MISC_CONTROL_PHYS(x) (x+0x00000038) +#define HWIO_WBM_R0_MISC_CONTROL_RMSK 0xffffffff +#define HWIO_WBM_R0_MISC_CONTROL_SHFT 0 +#define HWIO_WBM_R0_MISC_CONTROL_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_MISC_CONTROL_ADDR(x), HWIO_WBM_R0_MISC_CONTROL_RMSK) +#define HWIO_WBM_R0_MISC_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_MISC_CONTROL_ADDR(x), mask) +#define HWIO_WBM_R0_MISC_CONTROL_OUT(x, val) \ + out_dword( HWIO_WBM_R0_MISC_CONTROL_ADDR(x), val) +#define HWIO_WBM_R0_MISC_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_MISC_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_MISC_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_MISC_CONTROL_SPARE_CONTROL_BMSK 0xfffffffc +#define HWIO_WBM_R0_MISC_CONTROL_SPARE_CONTROL_SHFT 0x2 + +#define HWIO_WBM_R0_MISC_CONTROL_GXI_WRITE_STRUCT_SWAP_BMSK 0x00000002 +#define HWIO_WBM_R0_MISC_CONTROL_GXI_WRITE_STRUCT_SWAP_SHFT 0x1 + +#define HWIO_WBM_R0_MISC_CONTROL_GXI_READ_STRUCT_SWAP_BMSK 0x00000001 +#define HWIO_WBM_R0_MISC_CONTROL_GXI_READ_STRUCT_SWAP_SHFT 0x0 + +//// Register WBM_R0_WATCHDOG_TIMEOUT //// + +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x) (x+0x0000003c) +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_PHYS(x) (x+0x0000003c) +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_RMSK 0x00003fff +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_SHFT 0 +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x), HWIO_WBM_R0_WATCHDOG_TIMEOUT_RMSK) +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x), mask) +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x), val) +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WATCHDOG_TIMEOUT_ADDR(x), mask, val, HWIO_WBM_R0_WATCHDOG_TIMEOUT_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_RESOLUTION_UNITS_BMSK 0x00003000 +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_RESOLUTION_UNITS_SHFT 0xc + +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_VALUE_BMSK 0x00000fff +#define HWIO_WBM_R0_WATCHDOG_TIMEOUT_VALUE_SHFT 0x0 + +//// Register WBM_R0_INTERRUPT_DATA_CAPTURE //// + +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x) (x+0x00000040) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_PHYS(x) (x+0x00000040) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_RMSK 0xffffffff +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_SHFT 0 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x), HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_RMSK) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x), mask) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_OUT(x, val) \ + out_dword( HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x), val) +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ADDR(x), mask, val, HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ERROR_OCCURRENCE_BMSK 0x80000000 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ERROR_OCCURRENCE_SHFT 0x1f + +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ERROR_SOURCE_BMSK 0x40000000 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ERROR_SOURCE_SHFT 0x1e + +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ERROR_TYPE_BMSK 0x30000000 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_ERROR_TYPE_SHFT 0x1c + +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_SW_BUFFER_COOKIE_BMSK 0x0fffff00 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_SW_BUFFER_COOKIE_SHFT 0x8 + +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_BM_ACTION_BMSK 0x000000c0 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_BM_ACTION_SHFT 0x6 + +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_BUFFER_DESC_TYPE_BMSK 0x00000038 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_BUFFER_DESC_TYPE_SHFT 0x3 + +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_RETURN_BUFFER_MANAGER_BMSK 0x00000007 +#define HWIO_WBM_R0_INTERRUPT_DATA_CAPTURE_RETURN_BUFFER_MANAGER_SHFT 0x0 + +//// Register WBM_R0_INVALID_APB_ACC_ADDR //// + +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x) (x+0x00000044) +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_PHYS(x) (x+0x00000044) +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_RMSK 0x0007ffff +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_SHFT 0 +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x), HWIO_WBM_R0_INVALID_APB_ACC_ADDR_RMSK) +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask) +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_OUT(x, val) \ + out_dword( HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x), val) +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ADDR(x), mask, val, HWIO_WBM_R0_INVALID_APB_ACC_ADDR_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ERR_TYPE_BMSK 0x00060000 +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ERR_TYPE_SHFT 0x11 + +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ERR_ADDR_BMSK 0x0001ffff +#define HWIO_WBM_R0_INVALID_APB_ACC_ADDR_ERR_ADDR_SHFT 0x0 + +//// Register WBM_R0_IDLE_LIST_CONTROL //// + +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x) (x+0x00000048) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_PHYS(x) (x+0x00000048) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_RMSK 0x000007ff +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SHFT 0 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x), HWIO_WBM_R0_IDLE_LIST_CONTROL_RMSK) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x), mask) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_OUT(x, val) \ + out_dword( HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x), val) +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_IDLE_LIST_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_BMSK 0x000007fc +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_SCATTER_BUFFER_SIZE_SHFT 0x2 + +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_BMSK 0x00000002 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_LINK_DESC_IDLE_LIST_MODE_SHFT 0x1 + +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_BUFFER_IDLE_LIST_MODE_BMSK 0x00000001 +#define HWIO_WBM_R0_IDLE_LIST_CONTROL_BUFFER_IDLE_LIST_MODE_SHFT 0x0 + +//// Register WBM_R0_IDLE_LIST_SIZE //// + +#define HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x) (x+0x0000004c) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_PHYS(x) (x+0x0000004c) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_RMSK 0xffffffff +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SHFT 0 +#define HWIO_WBM_R0_IDLE_LIST_SIZE_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x), HWIO_WBM_R0_IDLE_LIST_SIZE_RMSK) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x), mask) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_OUT(x, val) \ + out_dword( HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x), val) +#define HWIO_WBM_R0_IDLE_LIST_SIZE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR(x), mask, val, HWIO_WBM_R0_IDLE_LIST_SIZE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_BMSK 0xffff0000 +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST_SHFT 0x10 + +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_BMSK 0x0000ffff +#define HWIO_WBM_R0_IDLE_LIST_SIZE_SCATTER_RING_SIZE_OF_IDLE_BUF_LIST_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_BUF_LIST_BASE_LSB //// + +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_ADDR(x) (x+0x00000050) +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_PHYS(x) (x+0x00000050) +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_RMSK) +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_BASE_ADDRESS_31_0_BMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_LSB_BASE_ADDRESS_31_0_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_BUF_LIST_BASE_MSB //// + +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDR(x) (x+0x00000054) +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_PHYS(x) (x+0x00000054) +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_RMSK) +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDRESS_MATCH_TAG_BMSK 0xffffff00 +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_ADDRESS_MATCH_TAG_SHFT 0x8 + +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK 0x000000ff +#define HWIO_WBM_R0_SCATTERED_BUF_LIST_BASE_MSB_BASE_ADDRESS_39_32_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB //// + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x) (x+0x00000058) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_PHYS(x) (x+0x00000058) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_RMSK) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_BASE_ADDRESS_31_0_BMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_BASE_ADDRESS_31_0_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB //// + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x) (x+0x0000005c) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_PHYS(x) (x+0x0000005c) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_RMSK) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_BMSK 0xffffff00 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDRESS_MATCH_TAG_SHFT 0x8 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK 0x000000ff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0 //// + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_ADDR(x) (x+0x00000060) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_PHYS(x) (x+0x00000060) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_RMSK) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_BUFFER_ADDRESS_31_0_BMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX0_BUFFER_ADDRESS_31_0_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1 //// + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_ADDR(x) (x+0x00000064) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_PHYS(x) (x+0x00000064) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_RMSK 0x001fffff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_RMSK) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_BMSK 0x001fff00 +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_SHFT 0x8 + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0x000000ff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0 //// + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x) (x+0x00000068) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_PHYS(x) (x+0x00000068) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_RMSK) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_BUFFER_ADDRESS_31_0_BMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_BUFFER_ADDRESS_31_0_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1 //// + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x) (x+0x0000006c) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_PHYS(x) (x+0x0000006c) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_RMSK 0x001fffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_RMSK) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_BMSK 0x001fff00 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_HEAD_POINTER_OFFSET_SHFT 0x8 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0x000000ff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0 //// + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_ADDR(x) (x+0x00000070) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_PHYS(x) (x+0x00000070) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_RMSK) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_BUFFER_ADDRESS_31_0_BMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX0_BUFFER_ADDRESS_31_0_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1 //// + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_ADDR(x) (x+0x00000074) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_PHYS(x) (x+0x00000074) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_RMSK 0x001fffff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_RMSK) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_BMSK 0x001fff00 +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_SHFT 0x8 + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0x000000ff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0 //// + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x) (x+0x00000078) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_PHYS(x) (x+0x00000078) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_RMSK) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_BUFFER_ADDRESS_31_0_BMSK 0xffffffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_BUFFER_ADDRESS_31_0_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1 //// + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x) (x+0x0000007c) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_PHYS(x) (x+0x0000007c) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_RMSK 0x001fffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_RMSK) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_BMSK 0x001fff00 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_TAIL_POINTER_OFFSET_SHFT 0x8 + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_BMSK 0x000000ff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_BUFFER_ADDRESS_39_32_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_BUF_PTR_HP //// + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_ADDR(x) (x+0x00000080) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_PHYS(x) (x+0x00000080) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_RMSK 0x000fffff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_RMSK) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_SCAT_HEAD_PTR_BMSK 0x000fffff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_HP_SCAT_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_LINK_DESC_PTR_HP //// + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x) (x+0x00000084) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_PHYS(x) (x+0x00000084) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_RMSK 0x000fffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_RMSK) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_SCAT_HEAD_PTR_BMSK 0x000fffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_SCAT_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_BUF_PTR_TP //// + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_ADDR(x) (x+0x00000088) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_PHYS(x) (x+0x00000088) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_RMSK 0x000fffff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_ADDR(x), HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_RMSK) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_SCAT_TAIL_PTR_BMSK 0x000fffff +#define HWIO_WBM_R0_SCATTERED_BUF_PTR_TP_SCAT_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R0_SCATTERED_LINK_DESC_PTR_TP //// + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x) (x+0x0000008c) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_PHYS(x) (x+0x0000008c) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_RMSK 0x000fffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_SHFT 0 +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x), HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_RMSK) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x), mask) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x), val) +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_ADDR(x), mask, val, HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_SCAT_TAIL_PTR_BMSK 0x000fffff +#define HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TP_SCAT_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R0_CLK_GATE_CTRL //// + +#define HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x) (x+0x00000090) +#define HWIO_WBM_R0_CLK_GATE_CTRL_PHYS(x) (x+0x00000090) +#define HWIO_WBM_R0_CLK_GATE_CTRL_RMSK 0x0003ffff +#define HWIO_WBM_R0_CLK_GATE_CTRL_SHFT 0 +#define HWIO_WBM_R0_CLK_GATE_CTRL_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x), HWIO_WBM_R0_CLK_GATE_CTRL_RMSK) +#define HWIO_WBM_R0_CLK_GATE_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x), mask) +#define HWIO_WBM_R0_CLK_GATE_CTRL_OUT(x, val) \ + out_dword( HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x), val) +#define HWIO_WBM_R0_CLK_GATE_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_CLK_GATE_CTRL_ADDR(x), mask, val, HWIO_WBM_R0_CLK_GATE_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_ENS_EXTEND_BMSK 0x00020000 +#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_ENS_EXTEND_SHFT 0x11 + +#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_GATE_DISABLE_APB_BMSK 0x00010000 +#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_GATE_DISABLE_APB_SHFT 0x10 + +#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_GATE_DISABLE_BMSK 0x0000ffff +#define HWIO_WBM_R0_CLK_GATE_CTRL_CLK_GATE_DISABLE_SHFT 0x0 + +//// Register WBM_R0_GXI_TESTBUS_LOWER //// + +#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_ADDR(x) (x+0x00000094) +#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_PHYS(x) (x+0x00000094) +#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_RMSK 0xffffffff +#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_SHFT 0 +#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_TESTBUS_LOWER_ADDR(x), HWIO_WBM_R0_GXI_TESTBUS_LOWER_RMSK) +#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_TESTBUS_LOWER_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_TESTBUS_LOWER_ADDR(x), val) +#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_WBM_R0_GXI_TESTBUS_LOWER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_GXI_TESTBUS_LOWER_VALUE_SHFT 0x0 + +//// Register WBM_R0_GXI_TESTBUS_UPPER //// + +#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_ADDR(x) (x+0x00000098) +#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_PHYS(x) (x+0x00000098) +#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_RMSK 0x000000ff +#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_SHFT 0 +#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_TESTBUS_UPPER_ADDR(x), HWIO_WBM_R0_GXI_TESTBUS_UPPER_RMSK) +#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_TESTBUS_UPPER_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_TESTBUS_UPPER_ADDR(x), val) +#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_TESTBUS_UPPER_ADDR(x), mask, val, HWIO_WBM_R0_GXI_TESTBUS_UPPER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_VALUE_BMSK 0x000000ff +#define HWIO_WBM_R0_GXI_TESTBUS_UPPER_VALUE_SHFT 0x0 + +//// Register WBM_R0_GXI_SM_STATES_IX_0 //// + +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_ADDR(x) (x+0x0000009c) +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_PHYS(x) (x+0x0000009c) +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_RMSK 0x00000fff +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SHFT 0 +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_SM_STATES_IX_0_ADDR(x), HWIO_WBM_R0_GXI_SM_STATES_IX_0_RMSK) +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_SM_STATES_IX_0_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_SM_STATES_IX_0_ADDR(x), val) +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_WBM_R0_GXI_SM_STATES_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_BMSK 0x00000e00 +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SM_STATE_RD_ADDR_SHFT 0x9 + +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_BMSK 0x000001f0 +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_ADDR_SHFT 0x4 + +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_BMSK 0x0000000f +#define HWIO_WBM_R0_GXI_SM_STATES_IX_0_SM_STATE_WR_DATA_SHFT 0x0 + +//// Register WBM_R0_GXI_END_OF_TEST_CHECK //// + +#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_ADDR(x) (x+0x000000a0) +#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_PHYS(x) (x+0x000000a0) +#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_RMSK 0x00000001 +#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_SHFT 0 +#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_ADDR(x), HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_RMSK) +#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_ADDR(x), val) +#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 +#define HWIO_WBM_R0_GXI_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 + +//// Register WBM_R0_GXI_CLOCK_GATE_DISABLE //// + +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x) (x+0x000000a4) +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_PHYS(x) (x+0x000000a4) +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_RMSK 0x80000fff +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_SHFT 0 +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_RMSK) +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), val) +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_ADDR(x), mask, val, HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_BMSK 0x80000000 +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_CLOCK_GATE_EXTEND_SHFT 0x1f + +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_SPARE_BMSK 0x00000800 +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_SPARE_SHFT 0xb + +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_BMSK 0x00000400 +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_WDOG_CTR_SHFT 0xa + +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_RD_FIFO_BMSK 0x00000200 +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_RD_FIFO_SHFT 0x9 + +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_BMSK 0x00000100 +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_FIFO_SHFT 0x8 + +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_BMSK 0x00000080 +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_FIFO_SHFT 0x7 + +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_BMSK 0x00000040 +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_RD_AXI_MAS_SHFT 0x6 + +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_BMSK 0x00000020 +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_AXI_MAS_SHFT 0x5 + +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_BMSK 0x00000010 +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_AXI_MAS_SHFT 0x4 + +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_BMSK 0x00000008 +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_WR_DATA_CMD_SHFT 0x3 + +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_BMSK 0x00000004 +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_WR_ADDR_CMD_SHFT 0x2 + +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_RD_CMD_BMSK 0x00000002 +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_RD_CMD_SHFT 0x1 + +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_CORE_BMSK 0x00000001 +#define HWIO_WBM_R0_GXI_CLOCK_GATE_DISABLE_CORE_SHFT 0x0 + +//// Register WBM_R0_GXI_GXI_ERR_INTS //// + +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_ADDR(x) (x+0x000000a8) +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_PHYS(x) (x+0x000000a8) +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_RMSK 0x01010101 +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_SHFT 0 +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_ERR_INTS_ADDR(x), HWIO_WBM_R0_GXI_GXI_ERR_INTS_RMSK) +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_ERR_INTS_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_GXI_ERR_INTS_ADDR(x), val) +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_ERR_INTS_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_ERR_INTS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_BMSK 0x01000000 +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_WR_LAST_ERR_INT_SHFT 0x18 + +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_BMSK 0x00010000 +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_AXI_WR_ERR_INT_SHFT 0x10 + +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_BMSK 0x00000100 +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_AXI_RD_ERR_INT_SHFT 0x8 + +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_BMSK 0x00000001 +#define HWIO_WBM_R0_GXI_GXI_ERR_INTS_GXI_WDTIMEOUT_INT_SHFT 0x0 + +//// Register WBM_R0_GXI_GXI_ERR_STATS //// + +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_ADDR(x) (x+0x000000ac) +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_PHYS(x) (x+0x000000ac) +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_RMSK 0x003f3f3f +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_SHFT 0 +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_ERR_STATS_ADDR(x), HWIO_WBM_R0_GXI_GXI_ERR_STATS_RMSK) +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_ERR_STATS_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_GXI_ERR_STATS_ADDR(x), val) +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_ERR_STATS_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_ERR_STATS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_BMSK 0x003f0000 +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_AXI_WR_LAST_ERR_PORT_SHFT 0x10 + +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_BMSK 0x00003f00 +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_AXI_WR_ERR_PORT_SHFT 0x8 + +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_BMSK 0x0000003f +#define HWIO_WBM_R0_GXI_GXI_ERR_STATS_AXI_RD_ERR_PORT_SHFT 0x0 + +//// Register WBM_R0_GXI_GXI_DEFAULT_CONTROL //// + +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x) (x+0x000000b0) +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_PHYS(x) (x+0x000000b0) +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_RMSK 0xffff3f3f +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_SHFT 0 +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_RMSK) +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), val) +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_BMSK 0xff000000 +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READ_DATA_SHFT 0x18 + +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITE_DATA_SHFT 0x10 + +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_BMSK 0x00003f00 +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_READS_SHFT 0x8 + +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_BMSK 0x0000003f +#define HWIO_WBM_R0_GXI_GXI_DEFAULT_CONTROL_GXI_DEFAULT_MAX_PENDING_WRITES_SHFT 0x0 + +//// Register WBM_R0_GXI_GXI_REDUCED_CONTROL //// + +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x) (x+0x000000b4) +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_PHYS(x) (x+0x000000b4) +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_RMSK 0xffff3f3f +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_SHFT 0 +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_RMSK) +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), val) +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_BMSK 0xff000000 +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READ_DATA_SHFT 0x18 + +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_BMSK 0x00ff0000 +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITE_DATA_SHFT 0x10 + +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_BMSK 0x00003f00 +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_READS_SHFT 0x8 + +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_BMSK 0x0000003f +#define HWIO_WBM_R0_GXI_GXI_REDUCED_CONTROL_GXI_REDUCED_MAX_PENDING_WRITES_SHFT 0x0 + +//// Register WBM_R0_GXI_GXI_MISC_CONTROL //// + +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_ADDR(x) (x+0x000000b8) +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_PHYS(x) (x+0x000000b8) +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_RMSK 0x0fffffff +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_SHFT 0 +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_ADDR(x), HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_RMSK) +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_ADDR(x), val) +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_BMSK 0x08000000 +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_RD_FLUSH_SHFT 0x1b + +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_BMSK 0x04000000 +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_DELAYED_WR_FLUSH_SHFT 0x1a + +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_BMSK 0x02000000 +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_DISABLE_WR_PREFIL_SHFT 0x19 + +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_BMSK 0x01000000 +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_WR_BOUNDARY_SPLIT_SHFT 0x18 + +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_BMSK 0x00800000 +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_MAX_RD_BOUNDARY_SPLIT_SHFT 0x17 + +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_BMSK 0x00700000 +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_BURST_SIZE_SHFT 0x14 + +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_BMSK 0x000e0000 +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_READ_BURST_SIZE_SHFT 0x11 + +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_BMSK 0x0001fe00 +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_READ_ISSUE_THRESHOLD_SHFT 0x9 + +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_BMSK 0x000001fe +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_WRITE_PREFETCH_THRESHOLD_SHFT 0x1 + +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_BMSK 0x00000001 +#define HWIO_WBM_R0_GXI_GXI_MISC_CONTROL_GXI_CLEAR_STATS_SHFT 0x0 + +//// Register WBM_R0_GXI_GXI_WDOG_CONTROL //// + +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_ADDR(x) (x+0x000000bc) +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_PHYS(x) (x+0x000000bc) +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_RMSK 0xffff0001 +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_SHFT 0 +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_RMSK) +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), val) +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_BMSK 0xffff0000 +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_LIMIT_SHFT 0x10 + +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_GXI_GXI_WDOG_CONTROL_GXI_WDOG_DISABLE_SHFT 0x0 + +//// Register WBM_R0_GXI_GXI_WDOG_STATUS //// + +#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_ADDR(x) (x+0x000000c0) +#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_PHYS(x) (x+0x000000c0) +#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_RMSK 0x0000ffff +#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_SHFT 0 +#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_ADDR(x), HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_RMSK) +#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_BMSK 0x0000ffff +#define HWIO_WBM_R0_GXI_GXI_WDOG_STATUS_GXI_WDOG_STATUS_SHFT 0x0 + +//// Register WBM_R0_GXI_GXI_IDLE_COUNTERS //// + +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x) (x+0x000000c4) +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_PHYS(x) (x+0x000000c4) +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_RMSK 0xffffffff +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_SHFT 0 +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_RMSK) +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), val) +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_BMSK 0xffff0000 +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_GXI_READ_IDLE_CNT_SHFT 0x10 + +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_BMSK 0x0000ffff +#define HWIO_WBM_R0_GXI_GXI_IDLE_COUNTERS_GXI_WRITE_IDLE_CNT_SHFT 0x0 + +//// Register WBM_R0_GXI_GXI_RD_LATENCY_CTRL //// + +#define HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x) (x+0x000000c8) +#define HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_PHYS(x) (x+0x000000c8) +#define HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_RMSK 0x000fffff +#define HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_SHFT 0 +#define HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_RMSK) +#define HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), val) +#define HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0x000e0000 +#define HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11 + +#define HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x00010000 +#define HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10 + +#define HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0x0000ffff +#define HWIO_WBM_R0_GXI_GXI_RD_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0 + +//// Register WBM_R0_GXI_GXI_WR_LATENCY_CTRL //// + +#define HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x) (x+0x000000cc) +#define HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_PHYS(x) (x+0x000000cc) +#define HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_RMSK 0x000fffff +#define HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_SHFT 0 +#define HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_RMSK) +#define HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), val) +#define HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_BMSK 0x000e0000 +#define HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_RANGE_SHFT 0x11 + +#define HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_BMSK 0x00010000 +#define HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_EN_SHFT 0x10 + +#define HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_BMSK 0x0000ffff +#define HWIO_WBM_R0_GXI_GXI_WR_LATENCY_CTRL_AXI_LATENCY_MIN_SHFT 0x0 + +//// Register WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0 //// + +#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x) (x+0x000000d0) +#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_PHYS(x) (x+0x000000d0) +#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff +#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_SHFT 0 +#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_RMSK) +#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), val) +#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0x0 + +//// Register WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1 //// + +#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x) (x+0x000000d4) +#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_PHYS(x) (x+0x000000d4) +#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff +#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_SHFT 0 +#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_RMSK) +#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), val) +#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_GXI_GXI_WR_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0x0 + +//// Register WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0 //// + +#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x) (x+0x000000d8) +#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_PHYS(x) (x+0x000000d8) +#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK 0xffffffff +#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_SHFT 0 +#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_RMSK) +#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), val) +#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_0_VALUE_SHFT 0x0 + +//// Register WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1 //// + +#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x) (x+0x000000dc) +#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_PHYS(x) (x+0x000000dc) +#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK 0xffffffff +#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_SHFT 0 +#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_RMSK) +#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), val) +#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_GXI_GXI_RD_ERR_STALL_DISABLE_IX_1_VALUE_SHFT 0x0 + +//// Register WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL //// + +#define HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x) (x+0x000000e0) +#define HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_PHYS(x) (x+0x000000e0) +#define HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_RMSK 0x00009f9f +#define HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_SHFT 0 +#define HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_RMSK) +#define HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), mask) +#define HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_OUT(x, val) \ + out_dword( HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), val) +#define HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_ADDR(x), mask, val, HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_EN_BMSK 0x00008000 +#define HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_EN_SHFT 0xf + +#define HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_CNT_BMSK 0x00001f00 +#define HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_WR_OVR_CNT_SHFT 0x8 + +#define HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_EN_BMSK 0x00000080 +#define HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_EN_SHFT 0x7 + +#define HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_BMSK 0x0000001f +#define HWIO_WBM_R0_GXI_GXI_AXI_OUTSANDING_CTL_RD_OVR_CNT_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x000000e4) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x000000e4) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x000000e8) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x000000e8) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x) (x+0x000000ec) +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_PHYS(x) (x+0x000000ec) +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_RMSK 0x000000ff +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_PPE_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_ADDR(x) (x+0x000000f0) +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_PHYS(x) (x+0x000000f0) +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x) (x+0x000000f4) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_PHYS(x) (x+0x000000f4) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_RMSK 0x003fffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000100) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000100) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000104) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000104) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_PPE_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000114) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000114) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000118) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000118) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000011c) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000011c) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000120) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000120) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000124) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000124) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000128) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000128) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000012c) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000012c) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000130) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000130) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x00000134) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x00000134) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000138) +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000138) +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_WBM_R0_PPE_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x0000013c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x0000013c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x00000140) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x00000140) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_TQM_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x) (x+0x00000144) +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_PHYS(x) (x+0x00000144) +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_RMSK 0x000000ff +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_TQM_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x) (x+0x00000148) +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_PHYS(x) (x+0x00000148) +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x) (x+0x0000014c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_PHYS(x) (x+0x0000014c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_RMSK 0x003fffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000158) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000158) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x) (x+0x0000015c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_PHYS(x) (x+0x0000015c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_TQM_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x0000016c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x0000016c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000170) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000170) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000174) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000174) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000178) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000178) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000017c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000017c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000180) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000180) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000184) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000184) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000188) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000188) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x0000018c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x0000018c) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000190) +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000190) +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_WBM_R0_TQM_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x00000194) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x00000194) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x00000198) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x00000198) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_REO_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x) (x+0x0000019c) +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_PHYS(x) (x+0x0000019c) +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_RMSK 0x000000ff +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_REO_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x) (x+0x000001a0) +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_PHYS(x) (x+0x000001a0) +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_REO_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x) (x+0x000001a4) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_PHYS(x) (x+0x000001a4) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_RMSK 0x003fffff +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_REO_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x) (x+0x000001b0) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_PHYS(x) (x+0x000001b0) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x) (x+0x000001b4) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_PHYS(x) (x+0x000001b4) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_REO_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000001c4) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000001c4) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000001c8) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000001c8) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000001cc) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000001cc) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000001d0) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000001d0) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000001d4) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000001d4) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000001d8) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000001d8) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R0_REO_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000001dc) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000001dc) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000001e0) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000001e0) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x000001e4) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x000001e4) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_REO_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000001e8) +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000001e8) +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_WBM_R0_REO_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x000001ec) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x000001ec) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x000001f0) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x000001f0) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x) (x+0x000001f4) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_PHYS(x) (x+0x000001f4) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_RMSK 0x000000ff +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_SW_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x) (x+0x000001f8) +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_PHYS(x) (x+0x000001f8) +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_SW_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x) (x+0x000001fc) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_PHYS(x) (x+0x000001fc) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_RMSK 0x003fffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_SW_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000208) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000208) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x) (x+0x0000020c) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_PHYS(x) (x+0x0000020c) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_SW_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x0000021c) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x0000021c) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000220) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000220) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000224) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000224) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000228) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000228) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000022c) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000022c) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000230) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000230) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R0_SW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000234) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000234) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000238) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000238) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x0000023c) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x0000023c) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_SW_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000240) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000240) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_WBM_R0_SW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x00000244) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x00000244) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x00000248) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x00000248) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_FW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x) (x+0x0000024c) +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_PHYS(x) (x+0x0000024c) +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_RMSK 0x000000ff +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_FW_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x) (x+0x00000250) +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_PHYS(x) (x+0x00000250) +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_FW_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x) (x+0x00000254) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_PHYS(x) (x+0x00000254) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_RMSK 0x003fffff +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_FW_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000260) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000260) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000264) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000264) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_FW_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x00000274) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x00000274) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000278) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000278) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x0000027c) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x0000027c) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000280) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000280) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x00000284) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x00000284) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000288) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000288) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R0_FW_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000028c) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000028c) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000290) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000290) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x00000294) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x00000294) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_FW_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000298) +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000298) +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_WBM_R0_FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x0000029c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x0000029c) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x000002a0) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x000002a0) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x) (x+0x000002a4) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_PHYS(x) (x+0x000002a4) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_RMSK 0x000000ff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x) (x+0x000002a8) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_PHYS(x) (x+0x000002a8) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x) (x+0x000002ac) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_PHYS(x) (x+0x000002ac) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_RMSK 0x003fffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x) (x+0x000002b8) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_PHYS(x) (x+0x000002b8) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x) (x+0x000002bc) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_PHYS(x) (x+0x000002bc) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000002cc) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000002cc) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000002d0) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000002d0) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000002d4) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000002d4) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000002d8) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000002d8) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000002dc) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000002dc) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000002e0) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000002e0) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000002e4) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000002e4) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000002e8) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000002e8) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x000002ec) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x000002ec) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000002f0) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000002f0) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_WBM_R0_RXDMA0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_ADDR(x) (x+0x000003a4) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_PHYS(x) (x+0x000003a4) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_ADDR(x) (x+0x000003a8) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_PHYS(x) (x+0x000003a8) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_ID //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ADDR(x) (x+0x000003ac) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_PHYS(x) (x+0x000003ac) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_ADDR(x) (x+0x000003b0) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_PHYS(x) (x+0x000003b0) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_MISC //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_ADDR(x) (x+0x000003b4) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_PHYS(x) (x+0x000003b4) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_RMSK 0x03ffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_LOOP_CNT_BMSK 0x03c00000 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_LOOP_CNT_SHFT 0x16 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_ADDR(x) (x+0x000003b8) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_PHYS(x) (x+0x000003b8) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_ADDR(x) (x+0x000003bc) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_PHYS(x) (x+0x000003bc) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000003c8) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000003c8) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000003cc) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000003cc) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000003d0) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000003d0) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000003ec) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000003ec) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000003f0) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000003f0) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA_ADDR(x) (x+0x000003f4) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA_PHYS(x) (x+0x000003f4) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000003f8) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000003f8) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2PPE_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_ADDR(x) (x+0x000003fc) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_PHYS(x) (x+0x000003fc) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_ADDR(x) (x+0x00000400) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_PHYS(x) (x+0x00000400) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_ID //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ADDR(x) (x+0x00000404) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_PHYS(x) (x+0x00000404) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_ADDR(x) (x+0x00000408) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_PHYS(x) (x+0x00000408) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_MISC //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_ADDR(x) (x+0x0000040c) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_PHYS(x) (x+0x0000040c) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_RMSK 0x03ffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_LOOP_CNT_BMSK 0x03c00000 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_LOOP_CNT_SHFT 0x16 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000410) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000410) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000414) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000414) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000420) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000420) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000424) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000424) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000428) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000428) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000444) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000444) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000448) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000448) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_ADDR(x) (x+0x0000044c) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_PHYS(x) (x+0x0000044c) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000450) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000450) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_ADDR(x) (x+0x00000454) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_PHYS(x) (x+0x00000454) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_ADDR(x) (x+0x00000458) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_PHYS(x) (x+0x00000458) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_ID //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ADDR(x) (x+0x0000045c) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_PHYS(x) (x+0x0000045c) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_ADDR(x) (x+0x00000460) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_PHYS(x) (x+0x00000460) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_MISC //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_ADDR(x) (x+0x00000464) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_PHYS(x) (x+0x00000464) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_RMSK 0x03ffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_LOOP_CNT_BMSK 0x03c00000 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_LOOP_CNT_SHFT 0x16 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000468) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000468) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000046c) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000046c) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000478) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000478) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000047c) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000047c) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000480) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000480) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000049c) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000049c) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000004a0) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000004a0) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_ADDR(x) (x+0x000004a4) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_PHYS(x) (x+0x000004a4) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000004a8) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000004a8) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_ADDR(x) (x+0x000004ac) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_PHYS(x) (x+0x000004ac) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_ADDR(x) (x+0x000004b0) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_PHYS(x) (x+0x000004b0) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_ID //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ADDR(x) (x+0x000004b4) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_PHYS(x) (x+0x000004b4) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_ADDR(x) (x+0x000004b8) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_PHYS(x) (x+0x000004b8) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_MISC //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_ADDR(x) (x+0x000004bc) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_PHYS(x) (x+0x000004bc) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_RMSK 0x03ffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_LOOP_CNT_BMSK 0x03c00000 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_LOOP_CNT_SHFT 0x16 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_ADDR(x) (x+0x000004c0) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_PHYS(x) (x+0x000004c0) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_ADDR(x) (x+0x000004c4) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_PHYS(x) (x+0x000004c4) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000004d0) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000004d0) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000004d4) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000004d4) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000004d8) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000004d8) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000004f4) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000004f4) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000004f8) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000004f8) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA_ADDR(x) (x+0x000004fc) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA_PHYS(x) (x+0x000004fc) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000500) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000500) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA0_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x) (x+0x000005b4) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_PHYS(x) (x+0x000005b4) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x) (x+0x000005b8) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_PHYS(x) (x+0x000005b8) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_ID //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x) (x+0x000005bc) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_PHYS(x) (x+0x000005bc) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x) (x+0x000005c0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_PHYS(x) (x+0x000005c0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_MISC //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x) (x+0x000005c4) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_PHYS(x) (x+0x000005c4) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_RMSK 0x03ffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_LOOP_CNT_BMSK 0x03c00000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_LOOP_CNT_SHFT 0x16 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x) (x+0x000005c8) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_PHYS(x) (x+0x000005c8) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x) (x+0x000005cc) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_PHYS(x) (x+0x000005cc) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000005d8) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000005d8) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000005dc) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000005dc) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000005e0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000005e0) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000005fc) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000005fc) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000600) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000600) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_ADDR(x) (x+0x00000604) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_PHYS(x) (x+0x00000604) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000608) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000608) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2TQM_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x) (x+0x0000060c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_PHYS(x) (x+0x0000060c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x) (x+0x00000610) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_PHYS(x) (x+0x00000610) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_ID //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x) (x+0x00000614) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_PHYS(x) (x+0x00000614) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x) (x+0x00000618) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_PHYS(x) (x+0x00000618) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_MISC //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x) (x+0x0000061c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_PHYS(x) (x+0x0000061c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_RMSK 0x03ffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_LOOP_CNT_BMSK 0x03c00000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_LOOP_CNT_SHFT 0x16 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000620) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000620) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000624) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000624) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000630) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000630) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000634) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000634) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000638) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000638) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000654) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000654) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000658) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000658) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x) (x+0x0000065c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_PHYS(x) (x+0x0000065c) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000660) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000660) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2REO_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x) (x+0x00000664) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_PHYS(x) (x+0x00000664) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x) (x+0x00000668) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_PHYS(x) (x+0x00000668) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_ID //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x) (x+0x0000066c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_PHYS(x) (x+0x0000066c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x) (x+0x00000670) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_PHYS(x) (x+0x00000670) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_MISC //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x) (x+0x00000674) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_PHYS(x) (x+0x00000674) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_RMSK 0x03ffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_LOOP_CNT_BMSK 0x03c00000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_LOOP_CNT_SHFT 0x16 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000678) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000678) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000067c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000067c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000688) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000688) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000068c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000068c) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000690) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000690) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000006ac) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000006ac) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000006b0) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000006b0) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x) (x+0x000006b4) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_PHYS(x) (x+0x000006b4) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000006b8) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000006b8) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x) (x+0x000006bc) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_PHYS(x) (x+0x000006bc) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x) (x+0x000006c0) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_PHYS(x) (x+0x000006c0) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_ID //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x) (x+0x000006c4) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_PHYS(x) (x+0x000006c4) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x) (x+0x000006c8) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_PHYS(x) (x+0x000006c8) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_MISC //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x) (x+0x000006cc) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_PHYS(x) (x+0x000006cc) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_RMSK 0x03ffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_LOOP_CNT_BMSK 0x03c00000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_LOOP_CNT_SHFT 0x16 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x) (x+0x000006d0) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_PHYS(x) (x+0x000006d0) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x) (x+0x000006d4) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_PHYS(x) (x+0x000006d4) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000006e0) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000006e0) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000006e4) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000006e4) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000006e8) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000006e8) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000704) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000704) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000708) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000708) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x) (x+0x0000070c) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_PHYS(x) (x+0x0000070c) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000710) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000710) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x) (x+0x00000714) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_PHYS(x) (x+0x00000714) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x) (x+0x00000718) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_PHYS(x) (x+0x00000718) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_ID //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x) (x+0x0000071c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_PHYS(x) (x+0x0000071c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x) (x+0x00000720) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_PHYS(x) (x+0x00000720) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_MISC //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x) (x+0x00000724) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_PHYS(x) (x+0x00000724) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_RMSK 0x03ffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_LOOP_CNT_BMSK 0x03c00000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_LOOP_CNT_SHFT 0x16 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000728) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000728) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000072c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000072c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000738) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000738) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000073c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000073c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000740) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000740) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000075c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000075c) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000760) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000760) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_ADDR(x) (x+0x00000764) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_PHYS(x) (x+0x00000764) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000768) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000768) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2RXDMA0_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_ADDR(x) (x+0x0000081c) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_PHYS(x) (x+0x0000081c) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_ADDR(x) (x+0x00000820) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_PHYS(x) (x+0x00000820) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_ID //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ADDR(x) (x+0x00000824) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_PHYS(x) (x+0x00000824) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_STATUS //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_ADDR(x) (x+0x00000828) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_PHYS(x) (x+0x00000828) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_MISC //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_ADDR(x) (x+0x0000082c) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_PHYS(x) (x+0x0000082c) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_RMSK 0x03ffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_LOOP_CNT_BMSK 0x03c00000 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_LOOP_CNT_SHFT 0x16 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000830) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000830) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000834) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000834) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000838) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000838) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_ADDR(x) (x+0x0000083c) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_PHYS(x) (x+0x0000083c) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000840) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000840) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000844) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000844) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000848) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000848) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x0000084c) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x0000084c) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x00000850) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x00000850) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x00000854) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x00000854) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x00000858) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x00000858) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x0000085c) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x0000085c) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x00000860) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x00000860) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000864) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000864) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000868) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000868) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA_ADDR(x) (x+0x0000086c) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA_PHYS(x) (x+0x0000086c) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000870) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000870) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_BUF_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x) (x+0x00000874) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_PHYS(x) (x+0x00000874) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x) (x+0x00000878) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_PHYS(x) (x+0x00000878) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_ID //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x) (x+0x0000087c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_PHYS(x) (x+0x0000087c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_STATUS //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x) (x+0x00000880) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_PHYS(x) (x+0x00000880) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_MISC //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x) (x+0x00000884) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_PHYS(x) (x+0x00000884) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RMSK 0x03ffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_LOOP_CNT_BMSK 0x03c00000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_LOOP_CNT_SHFT 0x16 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000888) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000888) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000088c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000088c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x) (x+0x00000890) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_PHYS(x) (x+0x00000890) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_LSB_TAIL_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x) (x+0x00000894) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_PHYS(x) (x+0x00000894) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_TP_ADDR_MSB_TAIL_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000898) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000898) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000089c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000089c) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000008a0) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000008a0) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0 //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x) (x+0x000008a4) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_PHYS(x) (x+0x000008a4) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX0_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1 //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x) (x+0x000008a8) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_PHYS(x) (x+0x000008a8) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_SETUP_IX1_LOW_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x) (x+0x000008ac) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_PHYS(x) (x+0x000008ac) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_CURRENT_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x) (x+0x000008b0) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_PHYS(x) (x+0x000008b0) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK 0x000003ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_BMSK 0x000003ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_EMPTY_COUNTER_RING_EMPTY_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x) (x+0x000008b4) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_PHYS(x) (x+0x000008b4) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK 0x00000007 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_BMSK 0x00000007 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_TIMER_MODE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x) (x+0x000008b8) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_PHYS(x) (x+0x000008b8) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_BMSK 0x00ff0000 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_PREFETCH_COUNT_SHFT 0x10 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_CONSUMER_PREFETCH_STATUS_INTERNAL_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000008bc) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000008bc) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000008c0) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000008c0) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA_ADDR(x) (x+0x000008c4) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA_PHYS(x) (x+0x000008c4) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000008c8) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000008c8) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM_IDLE_LINK_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x000008cc) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x000008cc) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x000008d0) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x000008d0) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RMSK 0x00ffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x00ffff00 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x) (x+0x000008d4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_PHYS(x) (x+0x000008d4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x) (x+0x000008d8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_PHYS(x) (x+0x000008d8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x) (x+0x000008dc) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_PHYS(x) (x+0x000008dc) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_RMSK 0x03ffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x03c00000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_LOOP_CNT_SHFT 0x16 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x) (x+0x000008e0) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_PHYS(x) (x+0x000008e0) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x) (x+0x000008e4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_PHYS(x) (x+0x000008e4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000008f0) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000008f0) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000008f4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000008f4) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000008f8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000008f8) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000914) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000914) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000918) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000918) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x0000091c) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x0000091c) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000920) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000920) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2FW_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x00000924) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x00000924) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x00000928) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x00000928) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RMSK 0x0fffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x) (x+0x0000092c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_PHYS(x) (x+0x0000092c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x) (x+0x00000930) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_PHYS(x) (x+0x00000930) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x) (x+0x00000934) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_PHYS(x) (x+0x00000934) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_RMSK 0x03ffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x03c00000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_LOOP_CNT_SHFT 0x16 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000938) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000938) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x) (x+0x0000093c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_PHYS(x) (x+0x0000093c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000948) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000948) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x0000094c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x0000094c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000950) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000950) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x0000096c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x0000096c) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000970) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000970) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x00000974) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x00000974) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000978) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000978) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW0_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x0000097c) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x0000097c) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x00000980) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x00000980) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RMSK 0x0fffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x) (x+0x00000984) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_PHYS(x) (x+0x00000984) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x) (x+0x00000988) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_PHYS(x) (x+0x00000988) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x) (x+0x0000098c) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_PHYS(x) (x+0x0000098c) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_RMSK 0x03ffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x03c00000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_LOOP_CNT_SHFT 0x16 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000990) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000990) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000994) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000994) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000009a0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000009a0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000009a4) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000009a4) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x000009a8) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x000009a8) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x000009c4) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x000009c4) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x000009c8) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x000009c8) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x000009cc) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x000009cc) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x000009d0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x000009d0) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW1_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x000009d4) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x000009d4) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x000009d8) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x000009d8) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RMSK 0x0fffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x) (x+0x000009dc) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_PHYS(x) (x+0x000009dc) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x) (x+0x000009e0) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_PHYS(x) (x+0x000009e0) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x) (x+0x000009e4) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_PHYS(x) (x+0x000009e4) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_RMSK 0x03ffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x03c00000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_LOOP_CNT_SHFT 0x16 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x) (x+0x000009e8) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_PHYS(x) (x+0x000009e8) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x) (x+0x000009ec) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_PHYS(x) (x+0x000009ec) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x000009f8) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x000009f8) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x000009fc) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x000009fc) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000a00) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000a00) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000a1c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000a1c) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000a20) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000a20) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x00000a24) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x00000a24) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000a28) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000a28) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW2_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x00000a2c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x00000a2c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x00000a30) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x00000a30) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RMSK 0x0fffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x) (x+0x00000a34) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_PHYS(x) (x+0x00000a34) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x) (x+0x00000a38) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_PHYS(x) (x+0x00000a38) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x) (x+0x00000a3c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_PHYS(x) (x+0x00000a3c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_RMSK 0x03ffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x03c00000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_LOOP_CNT_SHFT 0x16 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000a40) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000a40) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000a44) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000a44) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000a50) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000a50) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000a54) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000a54) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000a58) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000a58) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000a74) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000a74) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000a78) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000a78) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x00000a7c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x00000a7c) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000a80) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000a80) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW3_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_ADDR(x) (x+0x00000a84) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_PHYS(x) (x+0x00000a84) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_ADDR(x) (x+0x00000a88) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_PHYS(x) (x+0x00000a88) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_RMSK 0x0fffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK 0x0fffff00 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_BASE_MSB_RING_BASE_ADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW4_RELEASE_RING_ID //// + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ADDR(x) (x+0x00000a8c) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_PHYS(x) (x+0x00000a8c) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_SHFT 0 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ADDR(x), HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_RMSK) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_RING_ID_BMSK 0x0000ff00 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_RING_ID_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ENTRY_SIZE_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_ID_ENTRY_SIZE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW4_RELEASE_RING_STATUS //// + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_ADDR(x) (x+0x00000a90) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_PHYS(x) (x+0x00000a90) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_NUM_AVAIL_WORDS_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_NUM_VALID_WORDS_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_STATUS_NUM_VALID_WORDS_SHFT 0x0 + +//// Register WBM_R0_WBM2SW4_RELEASE_RING_MISC //// + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_ADDR(x) (x+0x00000a94) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_PHYS(x) (x+0x00000a94) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_RMSK 0x03ffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SHFT 0 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_ADDR(x), HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_RMSK) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_LOOP_CNT_BMSK 0x03c00000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_LOOP_CNT_SHFT 0x16 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SPARE_CONTROL_BMSK 0x003fc000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SPARE_CONTROL_SHFT 0xe + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_SM_STATE2_BMSK 0x00003000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_SM_STATE2_SHFT 0xc + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_SM_STATE1_BMSK 0x00000f00 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_SM_STATE1_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_IS_IDLE_BMSK 0x00000080 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_IS_IDLE_SHFT 0x7 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_ENABLE_BMSK 0x00000040 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SRNG_ENABLE_SHFT 0x6 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_BMSK 0x00000020 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_DATA_TLV_SWAP_BIT_SHFT 0x5 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_BMSK 0x00000010 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_HOST_FW_SWAP_BIT_SHFT 0x4 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_MSI_SWAP_BIT_BMSK 0x00000008 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_MSI_SWAP_BIT_SHFT 0x3 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SECURITY_BIT_BMSK 0x00000004 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_SECURITY_BIT_SHFT 0x2 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_LOOPCNT_DISABLE_BMSK 0x00000002 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_LOOPCNT_DISABLE_SHFT 0x1 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_RING_ID_DISABLE_BMSK 0x00000001 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MISC_RING_ID_DISABLE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB //// + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x) (x+0x00000a98) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_PHYS(x) (x+0x00000a98) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_LSB_HEAD_PTR_MEMADDR_LSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB //// + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x) (x+0x00000a9c) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_PHYS(x) (x+0x00000a9c) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_RMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_ADDR_MSB_HEAD_PTR_MEMADDR_MSB_SHFT 0x0 + +//// Register WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP //// + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x) (x+0x00000aa8) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_PHYS(x) (x+0x00000aa8) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_SHFT 0 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_RMSK) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_INTERRUPT_TIMER_THRESHOLD_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_SW_INTERRUPT_MODE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_SETUP_BATCH_COUNTER_THRESHOLD_SHFT 0x0 + +//// Register WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS //// + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x) (x+0x00000aac) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_PHYS(x) (x+0x00000aac) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_SHFT 0 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_RMSK) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_BMSK 0xffff0000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_INTERRUPT_TIMER_VALUE_SHFT 0x10 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_BMSK 0x00008000 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_CURRENT_SW_INT_WIRE_VALUE_SHFT 0xf + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_BMSK 0x00007fff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_INT_STATUS_INTERNAL_BATCH_COUNTER_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER //// + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x) (x+0x00000ab0) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_PHYS(x) (x+0x00000ab0) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK 0x000003ff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_SHFT 0 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_RMSK) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_BMSK 0x000003ff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_PRODUCER_FULL_COUNTER_RING_FULL_COUNTER_SHFT 0x0 + +//// Register WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB //// + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x) (x+0x00000acc) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_PHYS(x) (x+0x00000acc) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_RMSK) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_LSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB //// + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x) (x+0x00000ad0) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_PHYS(x) (x+0x00000ad0) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_RMSK 0x000001ff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_SHFT 0 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_RMSK) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_BMSK 0x00000100 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_MSI1_ENABLE_SHFT 0x8 + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR_BMSK 0x000000ff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_BASE_MSB_ADDR_SHFT 0x0 + +//// Register WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA //// + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x) (x+0x00000ad4) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_PHYS(x) (x+0x00000ad4) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_RMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_SHFT 0 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x), HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_RMSK) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_MSI1_DATA_VALUE_SHFT 0x0 + +//// Register WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET //// + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x) (x+0x00000ad8) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_PHYS(x) (x+0x00000ad8) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_RMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_SHFT 0 +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_IN(x) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_RMSK) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_OUT(x, val) \ + out_dword( HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), val) +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_ADDR(x), mask, val, HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_BMSK 0x0000ffff +#define HWIO_WBM_R0_WBM2SW4_RELEASE_RING_HP_TP_SW_OFFSET_HP_TP_OFFSET_VALUE_SHFT 0x0 + +//// Register WBM_R1_END_OF_TEST_CHECK //// + +#define HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x) (x+0x00002000) +#define HWIO_WBM_R1_END_OF_TEST_CHECK_PHYS(x) (x+0x00002000) +#define HWIO_WBM_R1_END_OF_TEST_CHECK_RMSK 0x00000001 +#define HWIO_WBM_R1_END_OF_TEST_CHECK_SHFT 0 +#define HWIO_WBM_R1_END_OF_TEST_CHECK_IN(x) \ + in_dword_masked ( HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x), HWIO_WBM_R1_END_OF_TEST_CHECK_RMSK) +#define HWIO_WBM_R1_END_OF_TEST_CHECK_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x), mask) +#define HWIO_WBM_R1_END_OF_TEST_CHECK_OUT(x, val) \ + out_dword( HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x), val) +#define HWIO_WBM_R1_END_OF_TEST_CHECK_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R1_END_OF_TEST_CHECK_ADDR(x), mask, val, HWIO_WBM_R1_END_OF_TEST_CHECK_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_BMSK 0x00000001 +#define HWIO_WBM_R1_END_OF_TEST_CHECK_END_OF_TEST_SELF_CHECK_SHFT 0x0 + +//// Register WBM_R1_TESTBUS_CTRL //// + +#define HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x) (x+0x00002004) +#define HWIO_WBM_R1_TESTBUS_CTRL_PHYS(x) (x+0x00002004) +#define HWIO_WBM_R1_TESTBUS_CTRL_RMSK 0x00001f3f +#define HWIO_WBM_R1_TESTBUS_CTRL_SHFT 0 +#define HWIO_WBM_R1_TESTBUS_CTRL_IN(x) \ + in_dword_masked ( HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x), HWIO_WBM_R1_TESTBUS_CTRL_RMSK) +#define HWIO_WBM_R1_TESTBUS_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x), mask) +#define HWIO_WBM_R1_TESTBUS_CTRL_OUT(x, val) \ + out_dword( HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x), val) +#define HWIO_WBM_R1_TESTBUS_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R1_TESTBUS_CTRL_ADDR(x), mask, val, HWIO_WBM_R1_TESTBUS_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R1_TESTBUS_CTRL_SELECT_GXI_BMSK 0x00001f00 +#define HWIO_WBM_R1_TESTBUS_CTRL_SELECT_GXI_SHFT 0x8 + +#define HWIO_WBM_R1_TESTBUS_CTRL_SELECT_WBM_BMSK 0x0000003f +#define HWIO_WBM_R1_TESTBUS_CTRL_SELECT_WBM_SHFT 0x0 + +//// Register WBM_R1_TESTBUS_LOWER //// + +#define HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x) (x+0x00002008) +#define HWIO_WBM_R1_TESTBUS_LOWER_PHYS(x) (x+0x00002008) +#define HWIO_WBM_R1_TESTBUS_LOWER_RMSK 0xffffffff +#define HWIO_WBM_R1_TESTBUS_LOWER_SHFT 0 +#define HWIO_WBM_R1_TESTBUS_LOWER_IN(x) \ + in_dword_masked ( HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x), HWIO_WBM_R1_TESTBUS_LOWER_RMSK) +#define HWIO_WBM_R1_TESTBUS_LOWER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x), mask) +#define HWIO_WBM_R1_TESTBUS_LOWER_OUT(x, val) \ + out_dword( HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x), val) +#define HWIO_WBM_R1_TESTBUS_LOWER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R1_TESTBUS_LOWER_ADDR(x), mask, val, HWIO_WBM_R1_TESTBUS_LOWER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R1_TESTBUS_LOWER_VALUE_BMSK 0xffffffff +#define HWIO_WBM_R1_TESTBUS_LOWER_VALUE_SHFT 0x0 + +//// Register WBM_R1_TESTBUS_HIGHER //// + +#define HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x) (x+0x0000200c) +#define HWIO_WBM_R1_TESTBUS_HIGHER_PHYS(x) (x+0x0000200c) +#define HWIO_WBM_R1_TESTBUS_HIGHER_RMSK 0x000000ff +#define HWIO_WBM_R1_TESTBUS_HIGHER_SHFT 0 +#define HWIO_WBM_R1_TESTBUS_HIGHER_IN(x) \ + in_dword_masked ( HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x), HWIO_WBM_R1_TESTBUS_HIGHER_RMSK) +#define HWIO_WBM_R1_TESTBUS_HIGHER_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x), mask) +#define HWIO_WBM_R1_TESTBUS_HIGHER_OUT(x, val) \ + out_dword( HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x), val) +#define HWIO_WBM_R1_TESTBUS_HIGHER_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R1_TESTBUS_HIGHER_ADDR(x), mask, val, HWIO_WBM_R1_TESTBUS_HIGHER_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R1_TESTBUS_HIGHER_VALUE_BMSK 0x000000ff +#define HWIO_WBM_R1_TESTBUS_HIGHER_VALUE_SHFT 0x0 + +//// Register WBM_R1_SM_STATES_IX_0 //// + +#define HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x) (x+0x00002010) +#define HWIO_WBM_R1_SM_STATES_IX_0_PHYS(x) (x+0x00002010) +#define HWIO_WBM_R1_SM_STATES_IX_0_RMSK 0x7fffffff +#define HWIO_WBM_R1_SM_STATES_IX_0_SHFT 0 +#define HWIO_WBM_R1_SM_STATES_IX_0_IN(x) \ + in_dword_masked ( HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x), HWIO_WBM_R1_SM_STATES_IX_0_RMSK) +#define HWIO_WBM_R1_SM_STATES_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x), mask) +#define HWIO_WBM_R1_SM_STATES_IX_0_OUT(x, val) \ + out_dword( HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x), val) +#define HWIO_WBM_R1_SM_STATES_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R1_SM_STATES_IX_0_ADDR(x), mask, val, HWIO_WBM_R1_SM_STATES_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R1_SM_STATES_IX_0_SW2_BUFFER_P_STATE_BMSK 0x60000000 +#define HWIO_WBM_R1_SM_STATES_IX_0_SW2_BUFFER_P_STATE_SHFT 0x1d + +#define HWIO_WBM_R1_SM_STATES_IX_0_SW1_BUFFER_P_STATE_BMSK 0x18000000 +#define HWIO_WBM_R1_SM_STATES_IX_0_SW1_BUFFER_P_STATE_SHFT 0x1b + +#define HWIO_WBM_R1_SM_STATES_IX_0_SW0_BUFFER_P_STATE_BMSK 0x06000000 +#define HWIO_WBM_R1_SM_STATES_IX_0_SW0_BUFFER_P_STATE_SHFT 0x19 + +#define HWIO_WBM_R1_SM_STATES_IX_0_FW_BUFFER_P_STATE_BMSK 0x01800000 +#define HWIO_WBM_R1_SM_STATES_IX_0_FW_BUFFER_P_STATE_SHFT 0x17 + +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_DIST_P_STATE_BMSK 0x00600000 +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_DIST_P_STATE_SHFT 0x15 + +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_DIST_C_STATE_BMSK 0x00180000 +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_DIST_C_STATE_SHFT 0x13 + +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_DIST_P_STATE_BMSK 0x00060000 +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_DIST_P_STATE_SHFT 0x11 + +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_DIST_C_STATE_BMSK 0x00018000 +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_DIST_C_STATE_SHFT 0xf + +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_IDLE_LIST_PROD_B_STATE_BMSK 0x00007000 +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_IDLE_LIST_PROD_B_STATE_SHFT 0xc + +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_IDLE_LIST_PROD_P_STATE_BMSK 0x00000c00 +#define HWIO_WBM_R1_SM_STATES_IX_0_LINK_IDLE_LIST_PROD_P_STATE_SHFT 0xa + +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_IDLE_LIST_PROD_B_STATE_BMSK 0x00000380 +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_IDLE_LIST_PROD_B_STATE_SHFT 0x7 + +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_IDLE_LIST_PROD_P_STATE_BMSK 0x00000060 +#define HWIO_WBM_R1_SM_STATES_IX_0_BUFFER_IDLE_LIST_PROD_P_STATE_SHFT 0x5 + +#define HWIO_WBM_R1_SM_STATES_IX_0_RLS_REQ_PARSE_P_STATE_BMSK 0x0000001c +#define HWIO_WBM_R1_SM_STATES_IX_0_RLS_REQ_PARSE_P_STATE_SHFT 0x2 + +#define HWIO_WBM_R1_SM_STATES_IX_0_RLS_REQ_PARSE_C_STATE_BMSK 0x00000003 +#define HWIO_WBM_R1_SM_STATES_IX_0_RLS_REQ_PARSE_C_STATE_SHFT 0x0 + +//// Register WBM_R1_SM_STATES_IX_1 //// + +#define HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x) (x+0x00002014) +#define HWIO_WBM_R1_SM_STATES_IX_1_PHYS(x) (x+0x00002014) +#define HWIO_WBM_R1_SM_STATES_IX_1_RMSK 0xffffffff +#define HWIO_WBM_R1_SM_STATES_IX_1_SHFT 0 +#define HWIO_WBM_R1_SM_STATES_IX_1_IN(x) \ + in_dword_masked ( HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x), HWIO_WBM_R1_SM_STATES_IX_1_RMSK) +#define HWIO_WBM_R1_SM_STATES_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x), mask) +#define HWIO_WBM_R1_SM_STATES_IX_1_OUT(x, val) \ + out_dword( HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x), val) +#define HWIO_WBM_R1_SM_STATES_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R1_SM_STATES_IX_1_ADDR(x), mask, val, HWIO_WBM_R1_SM_STATES_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R1_SM_STATES_IX_1_SW4_BUFFER_P_STATE_BMSK 0xc0000000 +#define HWIO_WBM_R1_SM_STATES_IX_1_SW4_BUFFER_P_STATE_SHFT 0x1e + +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_DIST_NULL_PTR_BMSK 0x20000000 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_DIST_NULL_PTR_SHFT 0x1d + +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_DIST_NULL_PTR_BMSK 0x10000000 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_DIST_NULL_PTR_SHFT 0x1c + +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SCAT_SRNG_C_STATE_BMSK 0x0e000000 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SCAT_SRNG_C_STATE_SHFT 0x19 + +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SCAT_SRNG_P_STATE_BMSK 0x01c00000 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SCAT_SRNG_P_STATE_SHFT 0x16 + +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SCAT_SRNG_C_STATE_BMSK 0x00380000 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SCAT_SRNG_C_STATE_SHFT 0x13 + +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SCAT_SRNG_P_STATE_BMSK 0x00070000 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SCAT_SRNG_P_STATE_SHFT 0x10 + +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SRNG_C_STATE_BMSK 0x0000e000 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SRNG_C_STATE_SHFT 0xd + +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SRNG_P_STATE_BMSK 0x00001c00 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_LINK_SRNG_P_STATE_SHFT 0xa + +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SRNG_C_STATE_BMSK 0x00000380 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SRNG_C_STATE_SHFT 0x7 + +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SRNG_P_STATE_BMSK 0x00000070 +#define HWIO_WBM_R1_SM_STATES_IX_1_IDLE_BUF_SRNG_P_STATE_SHFT 0x4 + +#define HWIO_WBM_R1_SM_STATES_IX_1_LINK_ZERO_OUT_STATE_BMSK 0x0000000c +#define HWIO_WBM_R1_SM_STATES_IX_1_LINK_ZERO_OUT_STATE_SHFT 0x2 + +#define HWIO_WBM_R1_SM_STATES_IX_1_SW3_BUFFER_P_STATE_BMSK 0x00000003 +#define HWIO_WBM_R1_SM_STATES_IX_1_SW3_BUFFER_P_STATE_SHFT 0x0 + +//// Register WBM_R1_EVENTMASK_IX_0 //// + +#define HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x) (x+0x00002018) +#define HWIO_WBM_R1_EVENTMASK_IX_0_PHYS(x) (x+0x00002018) +#define HWIO_WBM_R1_EVENTMASK_IX_0_RMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_0_SHFT 0 +#define HWIO_WBM_R1_EVENTMASK_IX_0_IN(x) \ + in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x), HWIO_WBM_R1_EVENTMASK_IX_0_RMSK) +#define HWIO_WBM_R1_EVENTMASK_IX_0_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x), mask) +#define HWIO_WBM_R1_EVENTMASK_IX_0_OUT(x, val) \ + out_dword( HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x), val) +#define HWIO_WBM_R1_EVENTMASK_IX_0_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R1_EVENTMASK_IX_0_ADDR(x), mask, val, HWIO_WBM_R1_EVENTMASK_IX_0_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R1_EVENTMASK_IX_0_MASK_BMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_0_MASK_SHFT 0x0 + +//// Register WBM_R1_EVENTMASK_IX_1 //// + +#define HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x) (x+0x0000201c) +#define HWIO_WBM_R1_EVENTMASK_IX_1_PHYS(x) (x+0x0000201c) +#define HWIO_WBM_R1_EVENTMASK_IX_1_RMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_1_SHFT 0 +#define HWIO_WBM_R1_EVENTMASK_IX_1_IN(x) \ + in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x), HWIO_WBM_R1_EVENTMASK_IX_1_RMSK) +#define HWIO_WBM_R1_EVENTMASK_IX_1_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x), mask) +#define HWIO_WBM_R1_EVENTMASK_IX_1_OUT(x, val) \ + out_dword( HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x), val) +#define HWIO_WBM_R1_EVENTMASK_IX_1_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R1_EVENTMASK_IX_1_ADDR(x), mask, val, HWIO_WBM_R1_EVENTMASK_IX_1_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R1_EVENTMASK_IX_1_MASK_BMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_1_MASK_SHFT 0x0 + +//// Register WBM_R1_EVENTMASK_IX_2 //// + +#define HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x) (x+0x00002020) +#define HWIO_WBM_R1_EVENTMASK_IX_2_PHYS(x) (x+0x00002020) +#define HWIO_WBM_R1_EVENTMASK_IX_2_RMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_2_SHFT 0 +#define HWIO_WBM_R1_EVENTMASK_IX_2_IN(x) \ + in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x), HWIO_WBM_R1_EVENTMASK_IX_2_RMSK) +#define HWIO_WBM_R1_EVENTMASK_IX_2_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x), mask) +#define HWIO_WBM_R1_EVENTMASK_IX_2_OUT(x, val) \ + out_dword( HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x), val) +#define HWIO_WBM_R1_EVENTMASK_IX_2_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R1_EVENTMASK_IX_2_ADDR(x), mask, val, HWIO_WBM_R1_EVENTMASK_IX_2_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R1_EVENTMASK_IX_2_MASK_BMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_2_MASK_SHFT 0x0 + +//// Register WBM_R1_EVENTMASK_IX_3 //// + +#define HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x) (x+0x00002024) +#define HWIO_WBM_R1_EVENTMASK_IX_3_PHYS(x) (x+0x00002024) +#define HWIO_WBM_R1_EVENTMASK_IX_3_RMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_3_SHFT 0 +#define HWIO_WBM_R1_EVENTMASK_IX_3_IN(x) \ + in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x), HWIO_WBM_R1_EVENTMASK_IX_3_RMSK) +#define HWIO_WBM_R1_EVENTMASK_IX_3_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x), mask) +#define HWIO_WBM_R1_EVENTMASK_IX_3_OUT(x, val) \ + out_dword( HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x), val) +#define HWIO_WBM_R1_EVENTMASK_IX_3_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R1_EVENTMASK_IX_3_ADDR(x), mask, val, HWIO_WBM_R1_EVENTMASK_IX_3_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R1_EVENTMASK_IX_3_MASK_BMSK 0xffffffff +#define HWIO_WBM_R1_EVENTMASK_IX_3_MASK_SHFT 0x0 + +//// Register WBM_R1_REG_ACCESS_EVENT_GEN_CTRL //// + +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x) (x+0x00002028) +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_PHYS(x) (x+0x00002028) +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK 0xffffffff +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_SHFT 0 +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x) \ + in_dword_masked ( HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_RMSK) +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask) +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_OUT(x, val) \ + out_dword( HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), val) +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDR(x), mask, val, HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_BMSK 0xfffe0000 +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_END_SHFT 0x11 + +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_BMSK 0x0001fffc +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_ADDRESS_RANGE_START_SHFT 0x2 + +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_BMSK 0x00000002 +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_WRITE_ACCESS_REPORT_ENABLE_SHFT 0x1 + +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_BMSK 0x00000001 +#define HWIO_WBM_R1_REG_ACCESS_EVENT_GEN_CTRL_READ_ACCESS_REPORT_ENABLE_SHFT 0x0 + +//// Register WBM_R2_PPE_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x) (x+0x00003000) +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_PHYS(x) (x+0x00003000) +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_PPE_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_PPE_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_PPE_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_PPE_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x) (x+0x00003004) +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_PHYS(x) (x+0x00003004) +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_PPE_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_PPE_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_PPE_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_PPE_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_TQM_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x) (x+0x00003008) +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_PHYS(x) (x+0x00003008) +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_TQM_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_TQM_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_TQM_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_TQM_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_TQM_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x) (x+0x0000300c) +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_PHYS(x) (x+0x0000300c) +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_TQM_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_TQM_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_TQM_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_TQM_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_REO_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x) (x+0x00003010) +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_PHYS(x) (x+0x00003010) +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_REO_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_REO_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_REO_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_REO_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_REO_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x) (x+0x00003014) +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_PHYS(x) (x+0x00003014) +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_REO_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_REO_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_REO_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_REO_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_SW_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x) (x+0x00003018) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_PHYS(x) (x+0x00003018) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_SW_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_SW_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_SW_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_SW_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x) (x+0x0000301c) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_PHYS(x) (x+0x0000301c) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_SW_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_SW_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_SW_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_SW_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_FW_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x) (x+0x00003020) +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_PHYS(x) (x+0x00003020) +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_FW_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_FW_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_FW_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_FW_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_FW_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x) (x+0x00003024) +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_PHYS(x) (x+0x00003024) +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_FW_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_FW_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_FW_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_FW_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_RXDMA0_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x) (x+0x00003028) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_PHYS(x) (x+0x00003028) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_RXDMA0_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x) (x+0x0000302c) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_PHYS(x) (x+0x0000302c) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_RXDMA0_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2PPE_BUF_RING_HP //// + +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_ADDR(x) (x+0x00003040) +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_PHYS(x) (x+0x00003040) +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2PPE_BUF_RING_TP //// + +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_ADDR(x) (x+0x00003044) +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_PHYS(x) (x+0x00003044) +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2PPE_BUF_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW_BUF_RING_HP //// + +#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_ADDR(x) (x+0x00003048) +#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_PHYS(x) (x+0x00003048) +#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW_BUF_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW_BUF_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW_BUF_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW_BUF_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW_BUF_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW_BUF_RING_TP //// + +#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_ADDR(x) (x+0x0000304c) +#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_PHYS(x) (x+0x0000304c) +#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW_BUF_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW_BUF_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW_BUF_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW_BUF_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW_BUF_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2FW_BUF_RING_HP //// + +#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_ADDR(x) (x+0x00003050) +#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_PHYS(x) (x+0x00003050) +#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2FW_BUF_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_BUF_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2FW_BUF_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_BUF_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_BUF_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2FW_BUF_RING_TP //// + +#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_ADDR(x) (x+0x00003054) +#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_PHYS(x) (x+0x00003054) +#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2FW_BUF_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_BUF_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2FW_BUF_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_BUF_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_BUF_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2RXDMA0_BUF_RING_HP //// + +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_ADDR(x) (x+0x00003058) +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_PHYS(x) (x+0x00003058) +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2RXDMA0_BUF_RING_TP //// + +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_ADDR(x) (x+0x0000305c) +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_PHYS(x) (x+0x0000305c) +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA0_BUF_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2TQM_LINK_RING_HP //// + +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x) (x+0x00003070) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_PHYS(x) (x+0x00003070) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2TQM_LINK_RING_TP //// + +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x) (x+0x00003074) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_PHYS(x) (x+0x00003074) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2TQM_LINK_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2REO_LINK_RING_HP //// + +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x) (x+0x00003078) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_PHYS(x) (x+0x00003078) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2REO_LINK_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2REO_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2REO_LINK_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2REO_LINK_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2REO_LINK_RING_TP //// + +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x) (x+0x0000307c) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_PHYS(x) (x+0x0000307c) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2REO_LINK_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2REO_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2REO_LINK_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2REO_LINK_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW_LINK_RING_HP //// + +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x) (x+0x00003080) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_PHYS(x) (x+0x00003080) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW_LINK_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW_LINK_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW_LINK_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW_LINK_RING_TP //// + +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x) (x+0x00003084) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_PHYS(x) (x+0x00003084) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW_LINK_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW_LINK_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2SW_LINK_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2FW_LINK_RING_HP //// + +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x) (x+0x00003088) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_PHYS(x) (x+0x00003088) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2FW_LINK_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_LINK_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_LINK_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2FW_LINK_RING_TP //// + +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x) (x+0x0000308c) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_PHYS(x) (x+0x0000308c) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2FW_LINK_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_LINK_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_LINK_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2RXDMA0_LINK_RING_HP //// + +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x) (x+0x00003090) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_PHYS(x) (x+0x00003090) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2RXDMA0_LINK_RING_TP //// + +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x) (x+0x00003094) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_PHYS(x) (x+0x00003094) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2RXDMA0_LINK_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM_IDLE_BUF_RING_HP //// + +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_ADDR(x) (x+0x000030a8) +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_PHYS(x) (x+0x000030a8) +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_ADDR(x), HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM_IDLE_BUF_RING_TP //// + +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_ADDR(x) (x+0x000030ac) +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_PHYS(x) (x+0x000030ac) +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_ADDR(x), HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM_IDLE_BUF_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM_IDLE_LINK_RING_HP //// + +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x) (x+0x000030b0) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_PHYS(x) (x+0x000030b0) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x), HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM_IDLE_LINK_RING_TP //// + +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x) (x+0x000030b4) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_PHYS(x) (x+0x000030b4) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x), HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM_IDLE_LINK_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2FW_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x) (x+0x000030b8) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_PHYS(x) (x+0x000030b8) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_HEAD_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2FW_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x) (x+0x000030bc) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_PHYS(x) (x+0x000030bc) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_RMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_TAIL_PTR_BMSK 0x0000ffff +#define HWIO_WBM_R2_WBM2FW_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW0_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x) (x+0x000030c0) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_PHYS(x) (x+0x000030c0) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_RMSK 0x000fffff +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_HEAD_PTR_BMSK 0x000fffff +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW0_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x) (x+0x000030c4) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_PHYS(x) (x+0x000030c4) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_RMSK 0x000fffff +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_TAIL_PTR_BMSK 0x000fffff +#define HWIO_WBM_R2_WBM2SW0_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW1_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x) (x+0x000030c8) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_PHYS(x) (x+0x000030c8) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_RMSK 0x000fffff +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_HEAD_PTR_BMSK 0x000fffff +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW1_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x) (x+0x000030cc) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_PHYS(x) (x+0x000030cc) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_RMSK 0x000fffff +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_TAIL_PTR_BMSK 0x000fffff +#define HWIO_WBM_R2_WBM2SW1_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW2_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x) (x+0x000030d0) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_PHYS(x) (x+0x000030d0) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_RMSK 0x000fffff +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_HEAD_PTR_BMSK 0x000fffff +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW2_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x) (x+0x000030d4) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_PHYS(x) (x+0x000030d4) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_RMSK 0x000fffff +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_TAIL_PTR_BMSK 0x000fffff +#define HWIO_WBM_R2_WBM2SW2_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW3_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x) (x+0x000030d8) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_PHYS(x) (x+0x000030d8) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_RMSK 0x000fffff +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_HEAD_PTR_BMSK 0x000fffff +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW3_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x) (x+0x000030dc) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_PHYS(x) (x+0x000030dc) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_RMSK 0x000fffff +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_TAIL_PTR_BMSK 0x000fffff +#define HWIO_WBM_R2_WBM2SW3_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW4_RELEASE_RING_HP //// + +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_ADDR(x) (x+0x000030e0) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_PHYS(x) (x+0x000030e0) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_RMSK 0x000fffff +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_ADDR(x), HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_RMSK) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_HEAD_PTR_BMSK 0x000fffff +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_HP_HEAD_PTR_SHFT 0x0 + +//// Register WBM_R2_WBM2SW4_RELEASE_RING_TP //// + +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_ADDR(x) (x+0x000030e4) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_PHYS(x) (x+0x000030e4) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_RMSK 0x000fffff +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_SHFT 0 +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_IN(x) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_ADDR(x), HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_RMSK) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_INM(x, mask) \ + in_dword_masked ( HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_ADDR(x), mask) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_OUT(x, val) \ + out_dword( HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_ADDR(x), val) +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_OUTM(x, mask, val) \ + do {\ + HWIO_INTLOCK(); \ + out_dword_masked_ns(HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_ADDR(x), mask, val, HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_IN(x)); \ + HWIO_INTFREE();\ + } while (0) + +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_TAIL_PTR_BMSK 0x000fffff +#define HWIO_WBM_R2_WBM2SW4_RELEASE_RING_TP_TAIL_PTR_SHFT 0x0 + + +#endif + diff --git a/drivers/staging/fw-api/hw/qca6750/v1/wbm_release_ring.h b/drivers/staging/fw-api/hw/qca6750/v1/wbm_release_ring.h new file mode 100644 index 000000000000..cac45d7f4b18 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/wbm_release_ring.h @@ -0,0 +1,2032 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +// +// DO NOT EDIT! This file is automatically generated +// These definitions are tied to a particular hardware layout + + +#ifndef _WBM_RELEASE_RING_H_ +#define _WBM_RELEASE_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "buffer_addr_info.h" +#include "tx_rate_stats_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-1 struct buffer_addr_info released_buff_or_desc_addr_info; +// 2 release_source_module[2:0], bm_action[5:3], buffer_or_desc_type[8:6], first_msdu_index[12:9], tqm_release_reason[16:13], rxdma_push_reason[18:17], rxdma_error_code[23:19], reo_push_reason[25:24], reo_error_code[30:26], wbm_internal_error[31] +// 3 tqm_status_number[23:0], transmit_count[30:24], msdu_continuation[31] +// 4 ack_frame_rssi[7:0], sw_release_details_valid[8], first_msdu[9], last_msdu[10], msdu_part_of_amsdu[11], fw_tx_notify_frame[12], buffer_timestamp[31:13] +// 5-6 struct tx_rate_stats_info tx_rate_stats; +// 7 sw_peer_id[15:0], tid[19:16], ring_id[27:20], looping_count[31:28] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_WBM_RELEASE_RING 8 + +struct wbm_release_ring { + struct buffer_addr_info released_buff_or_desc_addr_info; + uint32_t release_source_module : 3, //[2:0] + bm_action : 3, //[5:3] + buffer_or_desc_type : 3, //[8:6] + first_msdu_index : 4, //[12:9] + tqm_release_reason : 4, //[16:13] + rxdma_push_reason : 2, //[18:17] + rxdma_error_code : 5, //[23:19] + reo_push_reason : 2, //[25:24] + reo_error_code : 5, //[30:26] + wbm_internal_error : 1; //[31] + uint32_t tqm_status_number : 24, //[23:0] + transmit_count : 7, //[30:24] + msdu_continuation : 1; //[31] + uint32_t ack_frame_rssi : 8, //[7:0] + sw_release_details_valid : 1, //[8] + first_msdu : 1, //[9] + last_msdu : 1, //[10] + msdu_part_of_amsdu : 1, //[11] + fw_tx_notify_frame : 1, //[12] + buffer_timestamp : 19; //[31:13] + struct tx_rate_stats_info tx_rate_stats; + uint32_t sw_peer_id : 16, //[15:0] + tid : 4, //[19:16] + ring_id : 8, //[27:20] + looping_count : 4; //[31:28] +}; + +/* + +struct buffer_addr_info released_buff_or_desc_addr_info + + Consumer: WBM/SW/FW + + Producer: SW/TQM/RXDMA/REO/SWITCH + + + + Details of the physical address of the buffer or link + descriptor that is being released. Note that within this + descriptor, WBM will look at the 'owner' of the released + buffer/descriptor and forward it to SW/FW is WBM is not the + owner. + + + + In case of TQM releasing Tx MSDU link descriptors with + Tqm_release_reason set to 'tqm_fw_reason3,' HastingsPrime + WBM can optionally release the MSDU buffers pointed to by + the MSDU link descriptors to FW and override the + tx_rate_stats field, for FW reinjection of these MSDUs + (FR54309). This is not supported in Pine. + +release_source_module + + Indicates which module initiated the release of this + buffer or descriptor + + + + TQM released this buffer or + descriptor + + RXDMA released this buffer + or descriptor + + REO released this buffer or + descriptor + + FW released this buffer or + descriptor + + SW released this buffer or + descriptor + + + +bm_action + + Consumer: WBM/SW/FW + + Producer: SW/TQM/RXDMA/REO/SWITCH + + + + Field only valid when the field return_buffer_manager in + the Released_buff_or_desc_addr_info indicates: + + WBM_IDLE_BUF_LIST or + + WBM_IDLE_DESC_LIST + + + + An MSDU extension descriptor shall never be marked as + + + + Put the buffer or descriptor + back in the idle list. In case of MSDU or MDPU link + descriptor, BM does not need to check to release any + individual MSDU buffers + + + + This BM action can only be + used in combination with buffer_or_desc_type being + msdu_link_descriptor. Field first_msdu_index points out + which MSDU pointer in the MSDU link descriptor is the first + of an MPDU that is released. + + BM shall release all the MSDU buffers linked to this + first MSDU buffer pointer. All related MSDU buffer pointer + entries shall be set to value 0, which represents the 'NULL + pointer. When all MSDU buffer pointers in the MSDU link + descriptor are 'NULL', the MSDU link descriptor itself shall + also be released. + + + + CURRENTLY NOT + IMPLEMENTED.... + + Put the buffer or descriptor back in the idle list. Only + valid in combination with buffer_or_desc_type indicating + MDPU_link_descriptor. + + BM shall release the MPDU link descriptor as well as all + MSDUs that are linked to the MPDUs in this descriptor. + + + + + +buffer_or_desc_type + + Consumer: WBM/SW/FW + + Producer: SW/TQM/RXDMA/REO/SWITCH + + + + Field only valid when WBM is marked as the + return_buffer_manager in the Released_Buffer_address_info + + + + Indicates that type of buffer or descriptor is being + released + + + + The address points to an MSDU + buffer + + The address points to an + TX MSDU link descriptor + + The address points to an + MPDU link descriptor + + The address points to an + MSDU extension descriptor. + + In case BM finds this one in a release ring, it passes + it on to FW... + + The address points to an + TQM queue extension descriptor. WBM should treat this is the + same way as a link descriptor. That is, put the 128 byte + buffer back in the link buffer idle list. + + + + + +first_msdu_index + + Consumer: WBM/SW/FW + + Producer: SW/TQM/RXDMA/REO/SWITCH + + + + Field only valid for the bm_action release_msdu_list. + + + + The index of the first MSDU in an MSDU link descriptor + all belonging to the same MPDU. + + + + + +tqm_release_reason + + Consumer: WBM/SW/FW + + Producer: TQM + + + + Field only valid when Release_source_module is set to + release_source_TQM + + + + (rr = Release Reason) + + frame is removed because an + ACK of BA for it was received + + frame is removed because a + remove command of type Remove_mpdus initiated by SW + + frame is removed because a + remove command of type Remove_transmitted_mpdus initiated by + SW + + frame is removed because a + remove command of type Remove_untransmitted_mpdus initiated + by SW + + frame is removed because a + remove command of type Remove_aged_mpdus or + Remove_aged_msdus initiated by SW + + frame is removed because a + remove command where fw indicated that remove reason is + fw_reason1 + + frame is removed because a + remove command where fw indicated that remove reason is + fw_reason1 + + frame is removed because a + remove command where fw indicated that remove reason is + fw_reason1 + + frame is removed + because a remove command of type + remove_mpdus_and_disable_queue or + remove_msdus_and_disable_flow initiated by SW + + + + + + + + In case of TQM releasing Tx MSDU link descriptors with + Tqm_release_reason set to 'tqm_fw_reason3,' HastingsPrime + WBM can optionally release the MSDU buffers pointed to by + the MSDU link descriptors to FW and override the + tx_rate_stats field, for FW reinjection of these MSDUs + (FR54309). This is not supported in Pine. + +rxdma_push_reason + + Field only valid when Release_source_module is set to + release_source_RXDMA + + + + Indicates why rxdma pushed the frame to this ring + + + + RXDMA detected an error an + pushed this frame to this queue + + RXDMA pushed the + frame to this queue per received routing instructions. No + error within RXDMA was detected + + RXDMA received an RX_FLUSH. As a + result the MSDU link descriptor might not have the + last_msdu_in_mpdu_flag set, but instead WBM might just see a + NULL pointer in the MSDU link descriptor. This is to be + considered a normal condition for this scenario. + + + + + +rxdma_error_code + + Field only valid when 'rxdma_push_reason' set to + 'rxdma_error_detected'. + + + + MPDU frame is not complete + due to a FIFO overflow error in RXPCU. + + MPDU frame is not complete + due to receiving incomplete MPDU from the PHY + + + CRYPTO reported a decryption + error or CRYPTO received an encrypted frame, but did not get + a valid corresponding key id in the peer entry. + + CRYPTO reported a TKIP MIC + error + + CRYPTO reported an + unencrypted frame error when encrypted was expected + + RX OLE reported an MSDU + length error + + RX OLE reported that max + number of MSDUs allowed in an MPDU got exceeded + + RX OLE reported a parsing + error + + RX OLE reported an A-MSDU + parsing error + + RX OLE reported a timeout + during SA search + + RX OLE reported a timeout + during DA search + + RX OLE reported a + timeout during flow search + + RXDMA received a flush + request + + Rx PCU reported A-MSDU + present as well as a fragmented MPDU. A-MSDU defragmentation + is not supported in Lithium SW so this is treated as an + error. + +reo_push_reason + + Field only valid when Release_source_module is set to + release_source_REO + + + + Indicates why REO pushed the frame to this release ring + + + + Reo detected an error an + pushed this frame to this queue + + Reo pushed the frame to + this queue per received routing instructions. No error + within REO was detected + + + + + +reo_error_code + + Field only valid when 'Reo_push_reason' set to + 'reo_error_detected'. + + + + Reo queue descriptor + provided in the REO_ENTRANCE ring is set to 0 + + Reo queue descriptor + valid bit is NOT set + + AMPDU frame received without BA + session having been setup. + + Non-BA session, SN equal to + SSN, Retry bit set: duplicate frame + + BA session, duplicate frame + + A normal (management/data + frame) received with 2K jump in SN + + A bar received with 2K jump + in SSN + + A normal (management/data + frame) received with SN falling within the OOR window + + A bar received with SSN falling + within the OOR window + + A bar received without + a BA session + + A bar received with + SSN equal to SN + + PN Check Failed packet. + + Frame is forwarded + as a result of the 'Seq_2k_error_detected_flag' been set in + the REO Queue descriptor + + Frame is forwarded + as a result of the 'pn_error_detected_flag' been set in the + REO Queue descriptor + + Frame is + forwarded as a result of the queue descriptor(address) being + blocked as SW/FW seems to be currently in the process of + making updates to this descriptor... + + + + + +wbm_internal_error + + Can only be set by WBM. + + + + Is set when WBM got a buffer pointer but the action was + to push it to the idle link descriptor ring or do link + related activity + + OR + + Is set when WBM got a link buffer pointer but the action + was to push it to the buffer descriptor ring + + + + + +tqm_status_number + + Field only valid when Release_source_module is set to + release_source_TQM + + + + The value in this field is equal to value of the + 'TQM_CMD_Number' field the TQM command or the + 'TQM_add_cmd_Number' field from the TQM entrance ring + descriptor + + + + This field helps to correlate the statuses with the TQM + commands. + + + + NOTE that SW could program this number to be equal to + the PPDU_ID number in case direct correlation with the PPDU + ID is desired + + + + + +transmit_count + + Field only valid when Release_source_module is set to + release_source_TQM + + + + The number of times this frame has been transmitted + +msdu_continuation + + FR53947 requests MSDU_continuation reporting for Rx + MSDUs in Pine and HastingsPrime for which + SW_release_details_valid may not be set. + + + +ack_frame_rssi + + This field is only valid when the source is TQM. + + + + If this frame is removed as the result of the reception + of an ACK or BA, this field indicates the RSSI of the + received ACK or BA frame. + + + + When the frame is removed as result of a direct remove + command from the SW, this field is set to 0x0 (which is + never a valid value when real RSSI is available) + + + + + +sw_release_details_valid + + Consumer: SW + + Producer: WBM + + + + When set, some WBM specific release info for SW is + valid. + + This is set when WMB got a 'release_msdu_list' command + from TQM and the return buffer manager is not WMB. WBM will + then de-aggregate all the MSDUs and pass them one at a time + on to the 'buffer owner' + + + + + +first_msdu + + Field only valid when SW_release_details_valid is set. + + + + Consumer: SW + + Producer: WBM + + + + When set, this MSDU is the first MSDU pointed to in the + 'release_msdu_list' command. + + + + FR53947 extends this to Rx MSDUs in Pine and + HastingsPrime for which SW_release_details_valid may not be + set. + + + +last_msdu + + Field only valid when SW_release_details_valid is set. + + + + Consumer: SW + + Producer: WBM + + + + When set, this MSDU is the last MSDU pointed to in the + 'release_msdu_list' command. + + + + FR53947 extends this to Rx MSDUs in Pine and + HastingsPrime for which SW_release_details_valid may not be + set. + + + +msdu_part_of_amsdu + + Field only valid when SW_release_details_valid is set. + + + + Consumer: SW + + Producer: WBM + + + + When set, this MSDU was part of an A-MSDU in MPDU + + + +fw_tx_notify_frame + + Field only valid when SW_release_details_valid is set. + + + + Consumer: SW + + Producer: WBM + + + + This is the FW_tx_notify_frame field from the + + + +buffer_timestamp + + Field only valid when SW_release_details_valid is set. + + + + Consumer: SW + + Producer: WBM + + + + This is the Buffer_timestamp field from the + TX_MSDU_DETAILS for this frame from the MSDU link + descriptor. + + + + Timestamp in units of 1024 µs + + + +struct tx_rate_stats_info tx_rate_stats + + Consumer: TQM + + Producer: SW/SCH(from TXPCU, PDG) + + + + Details for command execution tracking purposes. + + + + In case of TQM releasing Tx MSDU link descriptors with + Tqm_release_reason set to 'tqm_fw_reason3,' HastingsPrime + WBM can optionally release the MSDU buffers pointed to by + the MSDU link descriptors to FW and override the + tx_rate_stats field with words 2 and 3 of the + 'TX_MSDU_DETAILS' structure, for FW reinjection of these + MSDUs (FR54309). This is not supported in Pine. + +sw_peer_id + + Field only valid when Release_source_module is set to + release_source_TQM + + + + 1) Release of msdu buffer due to drop_frame = 1. Flow is + not fetched and hence sw_peer_id and tid = 0 + + buffer_or_desc_type = e_num 0 + MSDU_rel_buffertqm_release_reason = e_num 1 + tqm_rr_rem_cmd_rem + + + + + + 2) Release of msdu buffer due to Flow is not fetched and + hence sw_peer_id and tid = 0 + + buffer_or_desc_type = e_num 0 + MSDU_rel_buffertqm_release_reason = e_num 1 + tqm_rr_rem_cmd_rem + + + + + + 3) Release of msdu link due to remove_mpdu or acked_mpdu + command. + + buffer_or_desc_type = e_num1 + msdu_link_descriptortqm_release_reason can be:e_num 1 + tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx + + e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged + + + + Sw_peer_id from the TX_MSDU_FLOW descriptor or + TX_MPDU_QUEUE descriptor + + + +tid + + Field only valid when Release_source_module is set to + release_source_TQM + + + + 1) Release of msdu buffer due to drop_frame = 1. Flow is + not fetched and hence sw_peer_id and tid = 0 + + buffer_or_desc_type = e_num 0 + MSDU_rel_buffertqm_release_reason = e_num 1 + tqm_rr_rem_cmd_rem + + + + + + 2) Release of msdu buffer due to Flow is not fetched and + hence sw_peer_id and tid = 0 + + buffer_or_desc_type = e_num 0 + MSDU_rel_buffertqm_release_reason = e_num 1 + tqm_rr_rem_cmd_rem + + + + + + 3) Release of msdu link due to remove_mpdu or acked_mpdu + command. + + buffer_or_desc_type = e_num1 + msdu_link_descriptortqm_release_reason can be:e_num 1 + tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx + + e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged + + + + + + This field represents the TID from the TX_MSDU_FLOW + descriptor or TX_MPDU_QUEUE descriptor + + + + + +ring_id + + Consumer: TQM/REO/RXDMA/SW + + Producer: SRNG (of RXDMA) + + + + For debugging. + + This field is filled in by the SRNG module. + + It help to identify the ring that is being looked + +looping_count + + Consumer: WBM/SW/FW + + Producer: SW/TQM/RXDMA/REO/SWITCH + + + + A count value that indicates the number of times the + producer of entries into the Buffer Manager Ring has looped + around the ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ + + + /* EXTERNAL REFERENCE : struct buffer_addr_info released_buff_or_desc_addr_info */ + + +/* Description WBM_RELEASE_RING_0_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define WBM_RELEASE_RING_0_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define WBM_RELEASE_RING_0_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define WBM_RELEASE_RING_0_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + +*/ +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define WBM_RELEASE_RING_1_RELEASED_BUFF_OR_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +/* Description WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE + + Indicates which module initiated the release of this + buffer or descriptor + + + + TQM released this buffer or + descriptor + + RXDMA released this buffer + or descriptor + + REO released this buffer or + descriptor + + FW released this buffer or + descriptor + + SW released this buffer or + descriptor + + +*/ +#define WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_LSB 0 +#define WBM_RELEASE_RING_2_RELEASE_SOURCE_MODULE_MASK 0x00000007 + +/* Description WBM_RELEASE_RING_2_BM_ACTION + + Consumer: WBM/SW/FW + + Producer: SW/TQM/RXDMA/REO/SWITCH + + + + Field only valid when the field return_buffer_manager in + the Released_buff_or_desc_addr_info indicates: + + WBM_IDLE_BUF_LIST or + + WBM_IDLE_DESC_LIST + + + + An MSDU extension descriptor shall never be marked as + + + + Put the buffer or descriptor + back in the idle list. In case of MSDU or MDPU link + descriptor, BM does not need to check to release any + individual MSDU buffers + + + + This BM action can only be + used in combination with buffer_or_desc_type being + msdu_link_descriptor. Field first_msdu_index points out + which MSDU pointer in the MSDU link descriptor is the first + of an MPDU that is released. + + BM shall release all the MSDU buffers linked to this + first MSDU buffer pointer. All related MSDU buffer pointer + entries shall be set to value 0, which represents the 'NULL + pointer. When all MSDU buffer pointers in the MSDU link + descriptor are 'NULL', the MSDU link descriptor itself shall + also be released. + + + + CURRENTLY NOT + IMPLEMENTED.... + + Put the buffer or descriptor back in the idle list. Only + valid in combination with buffer_or_desc_type indicating + MDPU_link_descriptor. + + BM shall release the MPDU link descriptor as well as all + MSDUs that are linked to the MPDUs in this descriptor. + + + + +*/ +#define WBM_RELEASE_RING_2_BM_ACTION_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_BM_ACTION_LSB 3 +#define WBM_RELEASE_RING_2_BM_ACTION_MASK 0x00000038 + +/* Description WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE + + Consumer: WBM/SW/FW + + Producer: SW/TQM/RXDMA/REO/SWITCH + + + + Field only valid when WBM is marked as the + return_buffer_manager in the Released_Buffer_address_info + + + + Indicates that type of buffer or descriptor is being + released + + + + The address points to an MSDU + buffer + + The address points to an + TX MSDU link descriptor + + The address points to an + MPDU link descriptor + + The address points to an + MSDU extension descriptor. + + In case BM finds this one in a release ring, it passes + it on to FW... + + The address points to an + TQM queue extension descriptor. WBM should treat this is the + same way as a link descriptor. That is, put the 128 byte + buffer back in the link buffer idle list. + + + + +*/ +#define WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_LSB 6 +#define WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_MASK 0x000001c0 + +/* Description WBM_RELEASE_RING_2_FIRST_MSDU_INDEX + + Consumer: WBM/SW/FW + + Producer: SW/TQM/RXDMA/REO/SWITCH + + + + Field only valid for the bm_action release_msdu_list. + + + + The index of the first MSDU in an MSDU link descriptor + all belonging to the same MPDU. + + + + +*/ +#define WBM_RELEASE_RING_2_FIRST_MSDU_INDEX_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_FIRST_MSDU_INDEX_LSB 9 +#define WBM_RELEASE_RING_2_FIRST_MSDU_INDEX_MASK 0x00001e00 + +/* Description WBM_RELEASE_RING_2_TQM_RELEASE_REASON + + Consumer: WBM/SW/FW + + Producer: TQM + + + + Field only valid when Release_source_module is set to + release_source_TQM + + + + (rr = Release Reason) + + frame is removed because an + ACK of BA for it was received + + frame is removed because a + remove command of type Remove_mpdus initiated by SW + + frame is removed because a + remove command of type Remove_transmitted_mpdus initiated by + SW + + frame is removed because a + remove command of type Remove_untransmitted_mpdus initiated + by SW + + frame is removed because a + remove command of type Remove_aged_mpdus or + Remove_aged_msdus initiated by SW + + frame is removed because a + remove command where fw indicated that remove reason is + fw_reason1 + + frame is removed because a + remove command where fw indicated that remove reason is + fw_reason1 + + frame is removed because a + remove command where fw indicated that remove reason is + fw_reason1 + + frame is removed + because a remove command of type + remove_mpdus_and_disable_queue or + remove_msdus_and_disable_flow initiated by SW + + + + + + + + In case of TQM releasing Tx MSDU link descriptors with + Tqm_release_reason set to 'tqm_fw_reason3,' HastingsPrime + WBM can optionally release the MSDU buffers pointed to by + the MSDU link descriptors to FW and override the + tx_rate_stats field, for FW reinjection of these MSDUs + (FR54309). This is not supported in Pine. +*/ +#define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_LSB 13 +#define WBM_RELEASE_RING_2_TQM_RELEASE_REASON_MASK 0x0001e000 + +/* Description WBM_RELEASE_RING_2_RXDMA_PUSH_REASON + + Field only valid when Release_source_module is set to + release_source_RXDMA + + + + Indicates why rxdma pushed the frame to this ring + + + + RXDMA detected an error an + pushed this frame to this queue + + RXDMA pushed the + frame to this queue per received routing instructions. No + error within RXDMA was detected + + RXDMA received an RX_FLUSH. As a + result the MSDU link descriptor might not have the + last_msdu_in_mpdu_flag set, but instead WBM might just see a + NULL pointer in the MSDU link descriptor. This is to be + considered a normal condition for this scenario. + + + + +*/ +#define WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_LSB 17 +#define WBM_RELEASE_RING_2_RXDMA_PUSH_REASON_MASK 0x00060000 + +/* Description WBM_RELEASE_RING_2_RXDMA_ERROR_CODE + + Field only valid when 'rxdma_push_reason' set to + 'rxdma_error_detected'. + + + + MPDU frame is not complete + due to a FIFO overflow error in RXPCU. + + MPDU frame is not complete + due to receiving incomplete MPDU from the PHY + + + CRYPTO reported a decryption + error or CRYPTO received an encrypted frame, but did not get + a valid corresponding key id in the peer entry. + + CRYPTO reported a TKIP MIC + error + + CRYPTO reported an + unencrypted frame error when encrypted was expected + + RX OLE reported an MSDU + length error + + RX OLE reported that max + number of MSDUs allowed in an MPDU got exceeded + + RX OLE reported a parsing + error + + RX OLE reported an A-MSDU + parsing error + + RX OLE reported a timeout + during SA search + + RX OLE reported a timeout + during DA search + + RX OLE reported a + timeout during flow search + + RXDMA received a flush + request + + Rx PCU reported A-MSDU + present as well as a fragmented MPDU. A-MSDU defragmentation + is not supported in Lithium SW so this is treated as an + error. +*/ +#define WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_LSB 19 +#define WBM_RELEASE_RING_2_RXDMA_ERROR_CODE_MASK 0x00f80000 + +/* Description WBM_RELEASE_RING_2_REO_PUSH_REASON + + Field only valid when Release_source_module is set to + release_source_REO + + + + Indicates why REO pushed the frame to this release ring + + + + Reo detected an error an + pushed this frame to this queue + + Reo pushed the frame to + this queue per received routing instructions. No error + within REO was detected + + + + +*/ +#define WBM_RELEASE_RING_2_REO_PUSH_REASON_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_REO_PUSH_REASON_LSB 24 +#define WBM_RELEASE_RING_2_REO_PUSH_REASON_MASK 0x03000000 + +/* Description WBM_RELEASE_RING_2_REO_ERROR_CODE + + Field only valid when 'Reo_push_reason' set to + 'reo_error_detected'. + + + + Reo queue descriptor + provided in the REO_ENTRANCE ring is set to 0 + + Reo queue descriptor + valid bit is NOT set + + AMPDU frame received without BA + session having been setup. + + Non-BA session, SN equal to + SSN, Retry bit set: duplicate frame + + BA session, duplicate frame + + A normal (management/data + frame) received with 2K jump in SN + + A bar received with 2K jump + in SSN + + A normal (management/data + frame) received with SN falling within the OOR window + + A bar received with SSN falling + within the OOR window + + A bar received without + a BA session + + A bar received with + SSN equal to SN + + PN Check Failed packet. + + Frame is forwarded + as a result of the 'Seq_2k_error_detected_flag' been set in + the REO Queue descriptor + + Frame is forwarded + as a result of the 'pn_error_detected_flag' been set in the + REO Queue descriptor + + Frame is + forwarded as a result of the queue descriptor(address) being + blocked as SW/FW seems to be currently in the process of + making updates to this descriptor... + + + + +*/ +#define WBM_RELEASE_RING_2_REO_ERROR_CODE_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_REO_ERROR_CODE_LSB 26 +#define WBM_RELEASE_RING_2_REO_ERROR_CODE_MASK 0x7c000000 + +/* Description WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR + + Can only be set by WBM. + + + + Is set when WBM got a buffer pointer but the action was + to push it to the idle link descriptor ring or do link + related activity + + OR + + Is set when WBM got a link buffer pointer but the action + was to push it to the buffer descriptor ring + + + + +*/ +#define WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_OFFSET 0x00000008 +#define WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_LSB 31 +#define WBM_RELEASE_RING_2_WBM_INTERNAL_ERROR_MASK 0x80000000 + +/* Description WBM_RELEASE_RING_3_TQM_STATUS_NUMBER + + Field only valid when Release_source_module is set to + release_source_TQM + + + + The value in this field is equal to value of the + 'TQM_CMD_Number' field the TQM command or the + 'TQM_add_cmd_Number' field from the TQM entrance ring + descriptor + + + + This field helps to correlate the statuses with the TQM + commands. + + + + NOTE that SW could program this number to be equal to + the PPDU_ID number in case direct correlation with the PPDU + ID is desired + + + + +*/ +#define WBM_RELEASE_RING_3_TQM_STATUS_NUMBER_OFFSET 0x0000000c +#define WBM_RELEASE_RING_3_TQM_STATUS_NUMBER_LSB 0 +#define WBM_RELEASE_RING_3_TQM_STATUS_NUMBER_MASK 0x00ffffff + +/* Description WBM_RELEASE_RING_3_TRANSMIT_COUNT + + Field only valid when Release_source_module is set to + release_source_TQM + + + + The number of times this frame has been transmitted +*/ +#define WBM_RELEASE_RING_3_TRANSMIT_COUNT_OFFSET 0x0000000c +#define WBM_RELEASE_RING_3_TRANSMIT_COUNT_LSB 24 +#define WBM_RELEASE_RING_3_TRANSMIT_COUNT_MASK 0x7f000000 + +/* Description WBM_RELEASE_RING_3_MSDU_CONTINUATION + + FR53947 requests MSDU_continuation reporting for Rx + MSDUs in Pine and HastingsPrime for which + SW_release_details_valid may not be set. + + +*/ +#define WBM_RELEASE_RING_3_MSDU_CONTINUATION_OFFSET 0x0000000c +#define WBM_RELEASE_RING_3_MSDU_CONTINUATION_LSB 31 +#define WBM_RELEASE_RING_3_MSDU_CONTINUATION_MASK 0x80000000 + +/* Description WBM_RELEASE_RING_4_ACK_FRAME_RSSI + + This field is only valid when the source is TQM. + + + + If this frame is removed as the result of the reception + of an ACK or BA, this field indicates the RSSI of the + received ACK or BA frame. + + + + When the frame is removed as result of a direct remove + command from the SW, this field is set to 0x0 (which is + never a valid value when real RSSI is available) + + + + +*/ +#define WBM_RELEASE_RING_4_ACK_FRAME_RSSI_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_ACK_FRAME_RSSI_LSB 0 +#define WBM_RELEASE_RING_4_ACK_FRAME_RSSI_MASK 0x000000ff + +/* Description WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID + + Consumer: SW + + Producer: WBM + + + + When set, some WBM specific release info for SW is + valid. + + This is set when WMB got a 'release_msdu_list' command + from TQM and the return buffer manager is not WMB. WBM will + then de-aggregate all the MSDUs and pass them one at a time + on to the 'buffer owner' + + + + +*/ +#define WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID_LSB 8 +#define WBM_RELEASE_RING_4_SW_RELEASE_DETAILS_VALID_MASK 0x00000100 + +/* Description WBM_RELEASE_RING_4_FIRST_MSDU + + Field only valid when SW_release_details_valid is set. + + + + Consumer: SW + + Producer: WBM + + + + When set, this MSDU is the first MSDU pointed to in the + 'release_msdu_list' command. + + + + FR53947 extends this to Rx MSDUs in Pine and + HastingsPrime for which SW_release_details_valid may not be + set. + + +*/ +#define WBM_RELEASE_RING_4_FIRST_MSDU_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_FIRST_MSDU_LSB 9 +#define WBM_RELEASE_RING_4_FIRST_MSDU_MASK 0x00000200 + +/* Description WBM_RELEASE_RING_4_LAST_MSDU + + Field only valid when SW_release_details_valid is set. + + + + Consumer: SW + + Producer: WBM + + + + When set, this MSDU is the last MSDU pointed to in the + 'release_msdu_list' command. + + + + FR53947 extends this to Rx MSDUs in Pine and + HastingsPrime for which SW_release_details_valid may not be + set. + + +*/ +#define WBM_RELEASE_RING_4_LAST_MSDU_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_LAST_MSDU_LSB 10 +#define WBM_RELEASE_RING_4_LAST_MSDU_MASK 0x00000400 + +/* Description WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU + + Field only valid when SW_release_details_valid is set. + + + + Consumer: SW + + Producer: WBM + + + + When set, this MSDU was part of an A-MSDU in MPDU + + +*/ +#define WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU_LSB 11 +#define WBM_RELEASE_RING_4_MSDU_PART_OF_AMSDU_MASK 0x00000800 + +/* Description WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME + + Field only valid when SW_release_details_valid is set. + + + + Consumer: SW + + Producer: WBM + + + + This is the FW_tx_notify_frame field from the + + +*/ +#define WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME_LSB 12 +#define WBM_RELEASE_RING_4_FW_TX_NOTIFY_FRAME_MASK 0x00001000 + +/* Description WBM_RELEASE_RING_4_BUFFER_TIMESTAMP + + Field only valid when SW_release_details_valid is set. + + + + Consumer: SW + + Producer: WBM + + + + This is the Buffer_timestamp field from the + TX_MSDU_DETAILS for this frame from the MSDU link + descriptor. + + + + Timestamp in units of 1024 µs + + +*/ +#define WBM_RELEASE_RING_4_BUFFER_TIMESTAMP_OFFSET 0x00000010 +#define WBM_RELEASE_RING_4_BUFFER_TIMESTAMP_LSB 13 +#define WBM_RELEASE_RING_4_BUFFER_TIMESTAMP_MASK 0xffffe000 + + /* EXTERNAL REFERENCE : struct tx_rate_stats_info tx_rate_stats */ + + +/* Description WBM_RELEASE_RING_5_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID + + When set all other fields in this STRUCT contain valid + info. + + + + + +*/ +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_LSB 0 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TX_RATE_STATS_INFO_VALID_MASK 0x00000001 + +/* Description WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_BW + + Field only valid when Tx_rate_stats_info_valid is set + + + + Indicates the BW of the upcoming transmission that shall + likely start in about 3 -4 us on the medium + + + + + + + + + + + + + + +*/ +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_BW_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_BW_LSB 1 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_BW_MASK 0x00000006 + +/* Description WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_PKT_TYPE + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + The packet type + + 802.11a PPDU type + + 802.11b PPDU type + + 802.11n Mixed Mode PPDU type + + 802.11ac PPDU type + + 802.11ax PPDU type + + 802.11ba (WUR) PPDU type +*/ +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_PKT_TYPE_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_PKT_TYPE_LSB 3 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_PKT_TYPE_MASK 0x00000078 + +/* Description WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_STBC + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + When set, STBC transmission rate was used. +*/ +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_STBC_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_STBC_LSB 7 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_STBC_MASK 0x00000080 + +/* Description WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_LDPC + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + When set, use LDPC transmission rates +*/ +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_LDPC_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_LDPC_LSB 8 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_LDPC_MASK 0x00000100 + +/* Description WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_SGI + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + Legacy normal GI. Can also be + used for HE + + Legacy short GI. Can also be + used for HE + + HE related GI + + HE related GI + + +*/ +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_SGI_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_SGI_LSB 9 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_SGI_MASK 0x00000600 + +/* Description WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_MCS + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + For details, refer to MCS_TYPE description + + +*/ +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_MCS_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_MCS_LSB 11 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TRANSMIT_MCS_MASK 0x00007800 + +/* Description WBM_RELEASE_RING_5_TX_RATE_STATS_OFDMA_TRANSMISSION + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + + + Set when the transmission was an OFDMA transmission (DL + or UL). + + +*/ +#define WBM_RELEASE_RING_5_TX_RATE_STATS_OFDMA_TRANSMISSION_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_OFDMA_TRANSMISSION_LSB 15 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_OFDMA_TRANSMISSION_MASK 0x00008000 + +/* Description WBM_RELEASE_RING_5_TX_RATE_STATS_TONES_IN_RU + + Field only valid when Tx_rate_stats_info_valid is set + + + + Field filled in by PDG. + + Not valid when in SW transmit mode + + + + The number of tones in the RU used. + + +*/ +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TONES_IN_RU_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TONES_IN_RU_LSB 16 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_TONES_IN_RU_MASK 0x0fff0000 + +/* Description WBM_RELEASE_RING_5_TX_RATE_STATS_RESERVED_0A + + +*/ +#define WBM_RELEASE_RING_5_TX_RATE_STATS_RESERVED_0A_OFFSET 0x00000014 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_RESERVED_0A_LSB 28 +#define WBM_RELEASE_RING_5_TX_RATE_STATS_RESERVED_0A_MASK 0xf0000000 + +/* Description WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF + + Field only valid when Tx_rate_stats_info_valid is set + + + + Based on a HWSCH configuration register setting, this + field either contains: + + + + Lower 32 bits of the TSF, snapshot of this value when + transmission of the PPDU containing the frame finished. + + OR + + Lower 32 bits of the TSF, snapshot of this value when + transmission of the PPDU containing the frame started + + + + +*/ +#define WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 0x00000018 +#define WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 0 +#define WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 0xffffffff + +/* Description WBM_RELEASE_RING_7_SW_PEER_ID + + Field only valid when Release_source_module is set to + release_source_TQM + + + + 1) Release of msdu buffer due to drop_frame = 1. Flow is + not fetched and hence sw_peer_id and tid = 0 + + buffer_or_desc_type = e_num 0 + MSDU_rel_buffertqm_release_reason = e_num 1 + tqm_rr_rem_cmd_rem + + + + + + 2) Release of msdu buffer due to Flow is not fetched and + hence sw_peer_id and tid = 0 + + buffer_or_desc_type = e_num 0 + MSDU_rel_buffertqm_release_reason = e_num 1 + tqm_rr_rem_cmd_rem + + + + + + 3) Release of msdu link due to remove_mpdu or acked_mpdu + command. + + buffer_or_desc_type = e_num1 + msdu_link_descriptortqm_release_reason can be:e_num 1 + tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx + + e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged + + + + Sw_peer_id from the TX_MSDU_FLOW descriptor or + TX_MPDU_QUEUE descriptor + + +*/ +#define WBM_RELEASE_RING_7_SW_PEER_ID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_7_SW_PEER_ID_LSB 0 +#define WBM_RELEASE_RING_7_SW_PEER_ID_MASK 0x0000ffff + +/* Description WBM_RELEASE_RING_7_TID + + Field only valid when Release_source_module is set to + release_source_TQM + + + + 1) Release of msdu buffer due to drop_frame = 1. Flow is + not fetched and hence sw_peer_id and tid = 0 + + buffer_or_desc_type = e_num 0 + MSDU_rel_buffertqm_release_reason = e_num 1 + tqm_rr_rem_cmd_rem + + + + + + 2) Release of msdu buffer due to Flow is not fetched and + hence sw_peer_id and tid = 0 + + buffer_or_desc_type = e_num 0 + MSDU_rel_buffertqm_release_reason = e_num 1 + tqm_rr_rem_cmd_rem + + + + + + 3) Release of msdu link due to remove_mpdu or acked_mpdu + command. + + buffer_or_desc_type = e_num1 + msdu_link_descriptortqm_release_reason can be:e_num 1 + tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx + + e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged + + + + + + This field represents the TID from the TX_MSDU_FLOW + descriptor or TX_MPDU_QUEUE descriptor + + + + +*/ +#define WBM_RELEASE_RING_7_TID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_7_TID_LSB 16 +#define WBM_RELEASE_RING_7_TID_MASK 0x000f0000 + +/* Description WBM_RELEASE_RING_7_RING_ID + + Consumer: TQM/REO/RXDMA/SW + + Producer: SRNG (of RXDMA) + + + + For debugging. + + This field is filled in by the SRNG module. + + It help to identify the ring that is being looked +*/ +#define WBM_RELEASE_RING_7_RING_ID_OFFSET 0x0000001c +#define WBM_RELEASE_RING_7_RING_ID_LSB 20 +#define WBM_RELEASE_RING_7_RING_ID_MASK 0x0ff00000 + +/* Description WBM_RELEASE_RING_7_LOOPING_COUNT + + Consumer: WBM/SW/FW + + Producer: SW/TQM/RXDMA/REO/SWITCH + + + + A count value that indicates the number of times the + producer of entries into the Buffer Manager Ring has looped + around the ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ +#define WBM_RELEASE_RING_7_LOOPING_COUNT_OFFSET 0x0000001c +#define WBM_RELEASE_RING_7_LOOPING_COUNT_LSB 28 +#define WBM_RELEASE_RING_7_LOOPING_COUNT_MASK 0xf0000000 + + +#endif // _WBM_RELEASE_RING_H_ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/wcss_seq_hwiobase.h b/drivers/staging/fw-api/hw/qca6750/v1/wcss_seq_hwiobase.h new file mode 100644 index 000000000000..a27a9bf1dac2 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/wcss_seq_hwiobase.h @@ -0,0 +1,847 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/////////////////////////////////////////////////////////////////////////////////////////////// +// +// wcss_seq_hwiobase.h : automatically generated by Autoseq 3.8 11/13/2019 +// User Name:sanjdas +// +// !! WARNING !! DO NOT MANUALLY EDIT THIS FILE. +// +/////////////////////////////////////////////////////////////////////////////////////////////// + +#ifndef __WCSS_SEQ_BASE_H__ +#define __WCSS_SEQ_BASE_H__ + +#ifdef SCALE_INCLUDES + #include "HALhwio.h" +#else + #include "msmhwio.h" +#endif + +#ifndef SOC_WCSS_BASE_ADDR + #if defined(WCSS_BASE) + #if ( WCSS_BASE != 0x0 ) + #error WCSS_BASE incorrectly redefined! + #endif + #endif + + #define SOC_WCSS_BASE_ADDR 0x0 +#else + #if ( SOC_WCSS_BASE_ADDR != 0x0 ) + #error SOC_WCSS_BASE_ADDR incorrectly redefined! + #endif +#endif + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block wcss +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_WCSS_UMAC_NOC_OFFSET 0x00140000 +#define SEQ_WCSS_PHYA_OFFSET 0x00300000 +#define SEQ_WCSS_PHYA_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00300000 +#define SEQ_WCSS_PHYA_WFAX_PCSS_REG_MAP_OFFSET 0x00380000 +#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00380400 +#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00380800 +#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00380c00 +#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00381000 +#define SEQ_WCSS_PHYA_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00381400 +#define SEQ_WCSS_PHYA_WFAX_PCSS_DUAL_TIMER_REG_MAP_OFFSET 0x00381800 +#define SEQ_WCSS_PHYA_WFAX_PCSS_WATCHDOG_REG_MAP_OFFSET 0x00381c00 +#define SEQ_WCSS_PHYA_WFAX_PCSS_XDMAC5_REG_MAP_OFFSET 0x00382c00 +#define SEQ_WCSS_PHYA_WFAX_PCSS_XDMAC6_REG_MAP_OFFSET 0x00383000 +#define SEQ_WCSS_PHYA_WFAX_NOC_REG_MAP_OFFSET 0x00388000 +#define SEQ_WCSS_PHYA_WFAX_TXFD_REG_MAP_OFFSET 0x00390000 +#define SEQ_WCSS_PHYA_WFAX_RXTD_REG_MAP_OFFSET 0x003a0000 +#define SEQ_WCSS_PHYA_WFAX_TXTD_REG_MAP_OFFSET 0x003b0000 +#define SEQ_WCSS_PHYA_WFAX_TXBF_REG_MAP_OFFSET 0x003c0000 +#define SEQ_WCSS_PHYA_WFAX_DEMFRONT_0_REG_MAP_OFFSET 0x00400000 +#define SEQ_WCSS_PHYA_WFAX_PHYRF_REG_MAP_OFFSET 0x00480000 +#define SEQ_WCSS_PHYA_WFAX_ROBE_REG_MAP_OFFSET 0x004b0000 +#define SEQ_WCSS_PHYA_WFAX_DEMFRONT_1_REG_MAP_OFFSET 0x00500000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_OFFSET 0x005c0000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_OFFSET 0x005c0000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_SYSCTRL_OFFSET 0x005cf000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_TLMM_OFFSET 0x005cf400 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x005cf800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_AON_1P8_REG_OFFSET 0x005cfc00 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TLMM_OFFSET 0x005c0000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TRC_OFFSET 0x005c0200 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_COEX_LTE_REG_OFFSET 0x005c5000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_OFFSET 0x005d1000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x005c7000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_SECURITY_CONTROL_CORE_OFFSET 0x005c9b00 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_RAW_FUSE_OFFSET 0x005c7000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_CORR_FUSE_OFFSET 0x005cb000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x005d4000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x005d4000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_XFEM_OFFSET 0x005d4240 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_OFFSET 0x005d42c0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x005d4300 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET 0x005d4400 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_OTP_OFFSET 0x005d4480 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x005d4800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_BTFMPLL_OFFSET 0x005d4c00 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_OFFSET 0x005d5000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x005d5400 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x005d6000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x005d6040 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x005d6100 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x005d6140 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x005d6180 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x005d61c0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x005d6280 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x005d6800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x005d6840 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x005d6900 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x005d6940 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x005d6980 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x005d69c0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x005d6a80 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_BS_OFFSET 0x005d7000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_CLBS_OFFSET 0x005d7040 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_BIST_OFFSET 0x005d7100 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_PC_OFFSET 0x005d7140 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_KVCO_OFFSET 0x005d7180 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_AC_OFFSET 0x005d71c0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_LO_OFFSET 0x005d7280 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x005d7c00 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET 0x005dc000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_MTOP_OFFSET 0x005dc000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXBB_OFFSET 0x005dc800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXFE_CH0_OFFSET 0x005dcc00 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXFE_CH1_OFFSET 0x005dd000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x005de800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_OFFSET 0x005de980 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x005de9c0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_MISC_OFFSET 0x005deac0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXBB_CH0_OFFSET 0x005dec00 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXBB_CH1_OFFSET 0x005dee00 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXFE_CH0_OFFSET 0x005df000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXFE_CH1_OFFSET 0x005df200 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET 0x005dfc00 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x005dfc40 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET 0x005dfc80 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET 0x005dfcc0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x005e0000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET 0x005e0000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x005e1000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x005e1300 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x005e2000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x005e4000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET 0x005e8000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x005e8400 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x005e8800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x005e9000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x005e9300 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x005ea000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_CH0_OFFSET 0x005ea400 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_CH0_OFFSET 0x005ea580 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_CH0_OFFSET 0x005ea5c0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_CH0_OFFSET 0x005ea6c0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_CH0_OFFSET 0x005ea734 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_CH0_OFFSET 0x005ea740 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_CH0_OFFSET 0x005ea800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_CH0_OFFSET 0x005ea840 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_CH0_OFFSET 0x005ea880 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_CH0_OFFSET 0x005ea8c0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_CH0_OFFSET 0x005ea900 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_CH0_OFFSET 0x005ea99c +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x005ec000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH1_OFFSET 0x005f0000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x005f1000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x005f1300 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x005f2000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x005f4000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH1_OFFSET 0x005f8000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x005f8400 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x005f8800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x005f9000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x005f9300 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x005fa000 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_CH1_OFFSET 0x005fa400 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_CH1_OFFSET 0x005fa580 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_CH1_OFFSET 0x005fa5c0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_CH1_OFFSET 0x005fa6c0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_CH1_OFFSET 0x005fa734 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_CH1_OFFSET 0x005fa740 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_CH1_OFFSET 0x005fa800 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_CH1_OFFSET 0x005fa840 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_CH1_OFFSET 0x005fa880 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_CH1_OFFSET 0x005fa8c0 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_CH1_OFFSET 0x005fa900 +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_CH1_OFFSET 0x005fa99c +#define SEQ_WCSS_PHYA_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH1_OFFSET 0x005fc000 +#define SEQ_WCSS_UMAC_OFFSET 0x00a00000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_OFFSET 0x00a20000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00a20000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00a22000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00a24000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00a26000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00a28000 +#define SEQ_WCSS_UMAC_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x00a2a000 +#define SEQ_WCSS_UMAC_MAC_TRACER_REG_OFFSET 0x00a30000 +#define SEQ_WCSS_UMAC_WBM_REG_OFFSET 0x00a34000 +#define SEQ_WCSS_UMAC_REO_REG_OFFSET 0x00a38000 +#define SEQ_WCSS_UMAC_TQM_REG_OFFSET 0x00a3c000 +#define SEQ_WCSS_UMAC_MAC_UMCMN_REG_OFFSET 0x00a40000 +#define SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET 0x00a44000 +#define SEQ_WCSS_UMAC_MAC_CMN_PARSER_CE_REG_OFFSET 0x00a47000 +#define SEQ_WCSS_WMAC0_OFFSET 0x00a80000 +#define SEQ_WCSS_WMAC0_MAC_PDG_REG_OFFSET 0x00a80000 +#define SEQ_WCSS_WMAC0_MAC_TXDMA_REG_OFFSET 0x00a83000 +#define SEQ_WCSS_WMAC0_MAC_RXDMA_REG_OFFSET 0x00a86000 +#define SEQ_WCSS_WMAC0_MAC_MCMN_REG_OFFSET 0x00a89000 +#define SEQ_WCSS_WMAC0_MAC_RXPCU_REG_OFFSET 0x00a8c000 +#define SEQ_WCSS_WMAC0_MAC_TXPCU_REG_OFFSET 0x00a8f000 +#define SEQ_WCSS_WMAC0_MAC_AMPI_REG_OFFSET 0x00a92000 +#define SEQ_WCSS_WMAC0_MAC_RXOLE_REG_OFFSET 0x00a95000 +#define SEQ_WCSS_WMAC0_MAC_RXOLE_PARSER_REG_OFFSET 0x00a98000 +#define SEQ_WCSS_WMAC0_MAC_CCE_REG_OFFSET 0x00a9b000 +#define SEQ_WCSS_WMAC0_MAC_TXOLE_REG_OFFSET 0x00a9e000 +#define SEQ_WCSS_WMAC0_MAC_TXOLE_PARSER_REG_OFFSET 0x00aa1000 +#define SEQ_WCSS_WMAC0_MAC_RRI_REG_OFFSET 0x00aa4000 +#define SEQ_WCSS_WMAC0_MAC_CRYPTO_REG_OFFSET 0x00aa7000 +#define SEQ_WCSS_WMAC0_MAC_HWSCH_REG_OFFSET 0x00aaa000 +#define SEQ_WCSS_WMAC0_MAC_MXI_REG_OFFSET 0x00ab0000 +#define SEQ_WCSS_WMAC0_MAC_SFM_REG_OFFSET 0x00ab3000 +#define SEQ_WCSS_APB_TSLV_OFFSET 0x00b40000 +#define SEQ_WCSS_TOP_CMN_OFFSET 0x00b50000 +#define SEQ_WCSS_WCMN_CORE_OFFSET 0x00b58000 +#define SEQ_WCSS_WFSS_PMM_OFFSET 0x00b60000 +#define SEQ_WCSS_PMM_TOP_OFFSET 0x00b70000 +#define SEQ_WCSS_DBG_OFFSET 0x00b90000 +#define SEQ_WCSS_DBG_WCSS_DBG_DAPROM_OFFSET 0x00b90000 +#define SEQ_WCSS_DBG_CSR_WCSS_DBG_CSR_OFFSET 0x00b91000 +#define SEQ_WCSS_DBG_TSGEN_CXTSGEN_OFFSET 0x00b92000 +#define SEQ_WCSS_DBG_CTIDBG_QC_CTI_32T_8CH_OFFSET 0x00b94000 +#define SEQ_WCSS_DBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00b95000 +#define SEQ_WCSS_DBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00b96000 +#define SEQ_WCSS_DBG_EVENT_MACEVENT_OFFSET 0x00bb0000 +#define SEQ_WCSS_DBG_EVENTFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb1000 +#define SEQ_WCSS_DBG_TLV_MACTLV_OFFSET 0x00bb2000 +#define SEQ_WCSS_DBG_TLVFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb3000 +#define SEQ_WCSS_DBG_TBUS_MACTBUS_OFFSET 0x00bb4000 +#define SEQ_WCSS_DBG_TBUSFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00bb5000 +#define SEQ_WCSS_DBG_CTIMAC_QC_CTI_12T_8CH_OFFSET 0x00bb6000 +#define SEQ_WCSS_DBG_WCSS_DBG_TSTMP_INJCTR_OFFSET 0x00bb8000 +#define SEQ_WCSS_DBG_TPDM_OFFSET 0x00bb9000 +#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00bb9280 +#define SEQ_WCSS_DBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00bb9000 +#define SEQ_WCSS_DBG_TPDA_OFFSET 0x00bba000 +#define SEQ_WCSS_DBG_CXATBFUNNEL_128W8SP_OFFSET 0x00bbb000 +#define SEQ_WCSS_DBG_TMC_CXTMC_F128W32K_OFFSET 0x00bbc000 +#define SEQ_WCSS_DBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET 0x00bbe000 +#define SEQ_WCSS_DBG_PHYFUN_CXATBFUNNEL_128W2SP_OFFSET 0x00bbf000 +#define SEQ_WCSS_DBG_OUTDMUX_ATB_DEMUX_OFFSET 0x00bc0000 +#define SEQ_WCSS_DBG_TRCCNTRS_OFFSET 0x00bc1000 +#define SEQ_WCSS_DBG_TLV_TPDM_ATB128_CMB64_OFFSET 0x00bc2000 +#define SEQ_WCSS_DBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00bc2280 +#define SEQ_WCSS_DBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00bc2000 +#define SEQ_WCSS_DBG_MISC_TPDM_ATB128_CMB64_OFFSET 0x00bc3000 +#define SEQ_WCSS_DBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00bc3280 +#define SEQ_WCSS_DBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00bc3000 +#define SEQ_WCSS_DBG_QC_TGU_APCLK_CSAE4EA8E3_OFFSET 0x00bc4000 +#define SEQ_WCSS_DBG_CTITGU_QC_CTI_4T_8CH_OFFSET 0x00bc5000 +#define SEQ_WCSS_DBG_PHYADMUX_ATB_DEMUX_OFFSET 0x00bc6000 +#define SEQ_WCSS_DBG_MISCFUN_CXATBFUNNEL_64W8SP_OFFSET 0x00bc8000 +#define SEQ_WCSS_DBG_UNOC_UMAC_NOC_OFFSET 0x00bd0000 +#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_OFFSET 0x00be0000 +#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_PHYA_NOC_OFFSET 0x00be0000 +#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00be4000 +#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00be5000 +#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00be6000 +#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_ITM_OFFSET 0x00be8000 +#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_DWT_OFFSET 0x00be9000 +#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_FPB_OFFSET 0x00bea000 +#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_SCS_OFFSET 0x00beb000 +#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_M3_ETM_OFFSET 0x00bec000 +#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x00bed000 +#define SEQ_WCSS_DBG_PHYA_PHYA_DBG_CPU0_M3_AHB_AP_OFFSET 0x00bee000 +#define SEQ_WCSS_DBG_BUS_TIMEOUT_OFFSET 0x00c31000 +#define SEQ_WCSS_RET_AHB_OFFSET 0x00c90000 +#define SEQ_WCSS_WAHB_TSLV_OFFSET 0x00ca0000 +#define SEQ_WCSS_CC_OFFSET 0x00cb0000 +#define SEQ_WCSS_UMAC_ACMT_OFFSET 0x00cc0000 + +#ifdef DEF_RPROC +#define SEQ_WCSS_Q6SS_PUBCSR_OFFSET 0x0cd00000 +#define SEQ_WCSS_Q6SS_PUBCSR_QDSP6SS_PUB_OFFSET 0x0cd00000 +#define SEQ_WCSS_Q6SS_PRIVCSR_OFFSET 0x0cd80000 +#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_CSR_OFFSET 0x0cd80000 +#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_OFFSET 0x0cd90000 +#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_QTMR_AC_OFFSET 0x0cda0000 +#define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F0_OFFSET 0x0cda1000 +#define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F1_OFFSET 0x0cda2000 +#define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F2_OFFSET 0x0cda3000 +#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_OFFSET 0x0cdb0000 +#else +#define SEQ_WCSS_Q6SS_PUBCSR_OFFSET 0x00d00000 +#define SEQ_WCSS_Q6SS_PUBCSR_QDSP6SS_PUB_OFFSET 0x00d00000 +#define SEQ_WCSS_Q6SS_PRIVCSR_OFFSET 0x00d80000 +#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_CSR_OFFSET 0x00d80000 +#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_L2VIC_OFFSET 0x00d90000 +#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_QTMR_AC_OFFSET 0x00da0000 +#define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F0_OFFSET 0x00da1000 +#define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F1_OFFSET 0x00da2000 +#define SEQ_WCSS_Q6SS_PRIVCSR_QTMR_F2_OFFSET 0x00da3000 +#define SEQ_WCSS_Q6SS_PRIVCSR_QDSP6SS_SAW2_OFFSET 0x00db0000 +#endif + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block wfax_top +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_WFAX_TOP_WFAX_PCSS_PDMEM_REG_MAP_OFFSET 0x00000000 +#define SEQ_WFAX_TOP_WFAX_PCSS_REG_MAP_OFFSET 0x00080000 +#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC0_REG_MAP_OFFSET 0x00080400 +#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC1_REG_MAP_OFFSET 0x00080800 +#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC2_REG_MAP_OFFSET 0x00080c00 +#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC3_REG_MAP_OFFSET 0x00081000 +#define SEQ_WFAX_TOP_WFAX_PCSS_DMAC4_REG_MAP_OFFSET 0x00081400 +#define SEQ_WFAX_TOP_WFAX_PCSS_DUAL_TIMER_REG_MAP_OFFSET 0x00081800 +#define SEQ_WFAX_TOP_WFAX_PCSS_WATCHDOG_REG_MAP_OFFSET 0x00081c00 +#define SEQ_WFAX_TOP_WFAX_PCSS_XDMAC5_REG_MAP_OFFSET 0x00082c00 +#define SEQ_WFAX_TOP_WFAX_PCSS_XDMAC6_REG_MAP_OFFSET 0x00083000 +#define SEQ_WFAX_TOP_WFAX_NOC_REG_MAP_OFFSET 0x00088000 +#define SEQ_WFAX_TOP_WFAX_TXFD_REG_MAP_OFFSET 0x00090000 +#define SEQ_WFAX_TOP_WFAX_RXTD_REG_MAP_OFFSET 0x000a0000 +#define SEQ_WFAX_TOP_WFAX_TXTD_REG_MAP_OFFSET 0x000b0000 +#define SEQ_WFAX_TOP_WFAX_TXBF_REG_MAP_OFFSET 0x000c0000 +#define SEQ_WFAX_TOP_WFAX_DEMFRONT_0_REG_MAP_OFFSET 0x00100000 +#define SEQ_WFAX_TOP_WFAX_PHYRF_REG_MAP_OFFSET 0x00180000 +#define SEQ_WFAX_TOP_WFAX_ROBE_REG_MAP_OFFSET 0x001b0000 +#define SEQ_WFAX_TOP_WFAX_DEMFRONT_1_REG_MAP_OFFSET 0x00200000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_OFFSET 0x002c0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_OFFSET 0x002c0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_SYSCTRL_OFFSET 0x002cf000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_TLMM_OFFSET 0x002cf400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x002cf800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_AON_1P8_REG_OFFSET 0x002cfc00 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TLMM_OFFSET 0x002c0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_TRC_OFFSET 0x002c0200 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_HZ_COEX_LTE_REG_OFFSET 0x002c5000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_PMU_OFFSET 0x002d1000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x002c7000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_SECURITY_CONTROL_CORE_OFFSET 0x002c9b00 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_RAW_FUSE_OFFSET 0x002c7000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_CORR_FUSE_OFFSET 0x002cb000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_OFFSET 0x002d4000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_OFFSET 0x002d4000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_XFEM_OFFSET 0x002d4240 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_AON_COEX_OFFSET 0x002d42c0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFFE_M_OFFSET 0x002d4300 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_SHD_OTP_OFFSET 0x002d4400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_RFA_OTP_OFFSET 0x002d4480 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_CLKGEN_OFFSET 0x002d4800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_BTFMPLL_OFFSET 0x002d4c00 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_BBPLL_OFFSET 0x002d5000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x002d5400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x002d6000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x002d6040 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x002d6100 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x002d6140 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x002d6180 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x002d61c0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x002d6280 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x002d6800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x002d6840 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x002d6900 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x002d6940 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x002d6980 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x002d69c0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x002d6a80 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_BS_OFFSET 0x002d7000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_CLBS_OFFSET 0x002d7040 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_BIST_OFFSET 0x002d7100 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_PC_OFFSET 0x002d7140 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_KVCO_OFFSET 0x002d7180 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_AC_OFFSET 0x002d71c0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_WL_SYNTH2_LO_OFFSET 0x002d7280 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x002d7c00 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_OFFSET 0x002dc000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_MTOP_OFFSET 0x002dc000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXBB_OFFSET 0x002dc800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXFE_CH0_OFFSET 0x002dcc00 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_TXFE_CH1_OFFSET 0x002dd000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x002de800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_OFFSET 0x002de980 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x002de9c0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_DAC_MISC_OFFSET 0x002deac0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXBB_CH0_OFFSET 0x002dec00 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXBB_CH1_OFFSET 0x002dee00 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXFE_CH0_OFFSET 0x002df000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_RXFE_CH1_OFFSET 0x002df200 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BS_OFFSET 0x002dfc00 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_BIST_OFFSET 0x002dfc40 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_PC_OFFSET 0x002dfc80 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_BT_BT_SYNTH_AC_OFFSET 0x002dfcc0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_OFFSET 0x002e0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH0_OFFSET 0x002e0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x002e1000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x002e1300 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x002e2000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x002e4000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH0_OFFSET 0x002e8000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH0_OFFSET 0x002e8400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH0_OFFSET 0x002e8800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x002e9000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x002e9300 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x002ea000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_CH0_OFFSET 0x002ea400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_CH0_OFFSET 0x002ea580 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_CH0_OFFSET 0x002ea5c0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_CH0_OFFSET 0x002ea6c0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_CH0_OFFSET 0x002ea734 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_CH0_OFFSET 0x002ea740 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_CH0_OFFSET 0x002ea800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_CH0_OFFSET 0x002ea840 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_CH0_OFFSET 0x002ea880 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_CH0_OFFSET 0x002ea8c0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_CH0_OFFSET 0x002ea900 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_CH0_OFFSET 0x002ea99c +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x002ec000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_2G_CH1_OFFSET 0x002f0000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x002f1000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x002f1300 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x002f2000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x002f4000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MC_5G_CH1_OFFSET 0x002f8000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXBB_CH1_OFFSET 0x002f8400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXBB_CH1_OFFSET 0x002f8800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x002f9000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x002f9300 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x002fa000 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_RBIST_TX_CH1_OFFSET 0x002fa400 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_CH1_OFFSET 0x002fa580 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_DIG_CORRECTION_CH1_OFFSET 0x002fa5c0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_MISC_CH1_OFFSET 0x002fa6c0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_DAC_BBCLKGEN_CH1_OFFSET 0x002fa734 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_CH1_OFFSET 0x002fa740 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_EVEN_CH1_OFFSET 0x002fa800 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_I_ODD_CH1_OFFSET 0x002fa840 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_CH1_OFFSET 0x002fa880 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_Q_ODD_CH1_OFFSET 0x002fa8c0 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_POSTPROC_RO_CH1_OFFSET 0x002fa900 +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_ADC_BBCLKGEN_CH1_OFFSET 0x002fa99c +#define SEQ_WFAX_TOP_WFAX_IRON2G_REG_MAP_RFA_WL_WL_MEM_5G_CH1_OFFSET 0x002fc000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block rfa_from_wsi +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_RFA_FROM_WSI_RFA_SOC_OFFSET 0x00000000 +#define SEQ_RFA_FROM_WSI_RFA_SOC_AO_SYSCTRL_OFFSET 0x0000f000 +#define SEQ_RFA_FROM_WSI_RFA_SOC_AO_TLMM_OFFSET 0x0000f400 +#define SEQ_RFA_FROM_WSI_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x0000f800 +#define SEQ_RFA_FROM_WSI_RFA_SOC_AON_1P8_REG_OFFSET 0x0000fc00 +#define SEQ_RFA_FROM_WSI_RFA_SOC_HZ_TLMM_OFFSET 0x00000000 +#define SEQ_RFA_FROM_WSI_RFA_SOC_HZ_TRC_OFFSET 0x00000200 +#define SEQ_RFA_FROM_WSI_RFA_SOC_HZ_COEX_LTE_REG_OFFSET 0x00005000 +#define SEQ_RFA_FROM_WSI_RFA_SOC_PMU_OFFSET 0x00011000 +#define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x00007000 +#define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_BT_SECURITY_CONTROL_CORE_OFFSET 0x00009b00 +#define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_RAW_FUSE_OFFSET 0x00007000 +#define SEQ_RFA_FROM_WSI_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_CORR_FUSE_OFFSET 0x0000b000 +#define SEQ_RFA_FROM_WSI_RFA_CMN_OFFSET 0x00014000 +#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_OFFSET 0x00014000 +#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_XFEM_OFFSET 0x00014240 +#define SEQ_RFA_FROM_WSI_RFA_CMN_AON_COEX_OFFSET 0x000142c0 +#define SEQ_RFA_FROM_WSI_RFA_CMN_RFFE_M_OFFSET 0x00014300 +#define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_SHD_OTP_OFFSET 0x00014400 +#define SEQ_RFA_FROM_WSI_RFA_CMN_RFA_OTP_OFFSET 0x00014480 +#define SEQ_RFA_FROM_WSI_RFA_CMN_CLKGEN_OFFSET 0x00014800 +#define SEQ_RFA_FROM_WSI_RFA_CMN_BTFMPLL_OFFSET 0x00014c00 +#define SEQ_RFA_FROM_WSI_RFA_CMN_BBPLL_OFFSET 0x00015000 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x00015400 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00016000 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00016040 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00016100 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00016140 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00016180 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x000161c0 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x00016280 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00016800 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00016840 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x00016900 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x00016940 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00016980 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x000169c0 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x00016a80 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_BS_OFFSET 0x00017000 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_CLBS_OFFSET 0x00017040 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_BIST_OFFSET 0x00017100 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_PC_OFFSET 0x00017140 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_KVCO_OFFSET 0x00017180 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_AC_OFFSET 0x000171c0 +#define SEQ_RFA_FROM_WSI_RFA_CMN_WL_SYNTH2_LO_OFFSET 0x00017280 +#define SEQ_RFA_FROM_WSI_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x00017c00 +#define SEQ_RFA_FROM_WSI_RFA_BT_OFFSET 0x0001c000 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_MTOP_OFFSET 0x0001c000 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_TXBB_OFFSET 0x0001c800 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_TXFE_CH0_OFFSET 0x0001cc00 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_TXFE_CH1_OFFSET 0x0001d000 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x0001e800 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_OFFSET 0x0001e980 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x0001e9c0 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_DAC_MISC_OFFSET 0x0001eac0 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_RXBB_CH0_OFFSET 0x0001ec00 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_RXBB_CH1_OFFSET 0x0001ee00 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_RXFE_CH0_OFFSET 0x0001f000 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_RXFE_CH1_OFFSET 0x0001f200 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BS_OFFSET 0x0001fc00 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_BIST_OFFSET 0x0001fc40 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_PC_OFFSET 0x0001fc80 +#define SEQ_RFA_FROM_WSI_RFA_BT_BT_SYNTH_AC_OFFSET 0x0001fcc0 +#define SEQ_RFA_FROM_WSI_RFA_WL_OFFSET 0x00020000 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_2G_CH0_OFFSET 0x00020000 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x00021000 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x00021300 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x00022000 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x00024000 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_5G_CH0_OFFSET 0x00028000 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH0_OFFSET 0x00028400 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH0_OFFSET 0x00028800 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x00029000 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x00029300 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x0002a000 +#define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_TX_CH0_OFFSET 0x0002a400 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_CH0_OFFSET 0x0002a580 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_DIG_CORRECTION_CH0_OFFSET 0x0002a5c0 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_MISC_CH0_OFFSET 0x0002a6c0 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_BBCLKGEN_CH0_OFFSET 0x0002a734 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_CH0_OFFSET 0x0002a740 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_EVEN_CH0_OFFSET 0x0002a800 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_ODD_CH0_OFFSET 0x0002a840 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_CH0_OFFSET 0x0002a880 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_ODD_CH0_OFFSET 0x0002a8c0 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_RO_CH0_OFFSET 0x0002a900 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_BBCLKGEN_CH0_OFFSET 0x0002a99c +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x0002c000 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_2G_CH1_OFFSET 0x00030000 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x00031000 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x00031300 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x00032000 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x00034000 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MC_5G_CH1_OFFSET 0x00038000 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXBB_CH1_OFFSET 0x00038400 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXBB_CH1_OFFSET 0x00038800 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x00039000 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x00039300 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x0003a000 +#define SEQ_RFA_FROM_WSI_RFA_WL_RBIST_TX_CH1_OFFSET 0x0003a400 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_CH1_OFFSET 0x0003a580 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_DIG_CORRECTION_CH1_OFFSET 0x0003a5c0 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_MISC_CH1_OFFSET 0x0003a6c0 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_DAC_BBCLKGEN_CH1_OFFSET 0x0003a734 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_CH1_OFFSET 0x0003a740 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_EVEN_CH1_OFFSET 0x0003a800 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_I_ODD_CH1_OFFSET 0x0003a840 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_CH1_OFFSET 0x0003a880 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_Q_ODD_CH1_OFFSET 0x0003a8c0 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_POSTPROC_RO_CH1_OFFSET 0x0003a900 +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_ADC_BBCLKGEN_CH1_OFFSET 0x0003a99c +#define SEQ_RFA_FROM_WSI_RFA_WL_WL_MEM_5G_CH1_OFFSET 0x0003c000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block rfa_soc +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_RFA_SOC_AO_SYSCTRL_OFFSET 0x0000f000 +#define SEQ_RFA_SOC_AO_TLMM_OFFSET 0x0000f400 +#define SEQ_RFA_SOC_AO_OVERRIDE_REG_OFFSET 0x0000f800 +#define SEQ_RFA_SOC_AON_1P8_REG_OFFSET 0x0000fc00 +#define SEQ_RFA_SOC_HZ_TLMM_OFFSET 0x00000000 +#define SEQ_RFA_SOC_HZ_TRC_OFFSET 0x00000200 +#define SEQ_RFA_SOC_HZ_COEX_LTE_REG_OFFSET 0x00005000 +#define SEQ_RFA_SOC_PMU_OFFSET 0x00011000 +#define SEQ_RFA_SOC_BT_SECURITY_CONTROL_OFFSET 0x00007000 +#define SEQ_RFA_SOC_BT_SECURITY_CONTROL_BT_SECURITY_CONTROL_CORE_OFFSET 0x00009b00 +#define SEQ_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_RAW_FUSE_OFFSET 0x00007000 +#define SEQ_RFA_SOC_BT_SECURITY_CONTROL_BT_QFPROM_CORR_FUSE_OFFSET 0x0000b000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block security_control_bt +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_SECURITY_CONTROL_BT_BT_SECURITY_CONTROL_CORE_OFFSET 0x00002b00 +#define SEQ_SECURITY_CONTROL_BT_BT_QFPROM_RAW_FUSE_OFFSET 0x00000000 +#define SEQ_SECURITY_CONTROL_BT_BT_QFPROM_CORR_FUSE_OFFSET 0x00004000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block rfa_cmn +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_RFA_CMN_AON_OFFSET 0x00000000 +#define SEQ_RFA_CMN_AON_XFEM_OFFSET 0x00000240 +#define SEQ_RFA_CMN_AON_COEX_OFFSET 0x000002c0 +#define SEQ_RFA_CMN_RFFE_M_OFFSET 0x00000300 +#define SEQ_RFA_CMN_RFA_SHD_OTP_OFFSET 0x00000400 +#define SEQ_RFA_CMN_RFA_OTP_OFFSET 0x00000480 +#define SEQ_RFA_CMN_CLKGEN_OFFSET 0x00000800 +#define SEQ_RFA_CMN_BTFMPLL_OFFSET 0x00000c00 +#define SEQ_RFA_CMN_BBPLL_OFFSET 0x00001000 +#define SEQ_RFA_CMN_WL_TOP_CLKGEN_OFFSET 0x00001400 +#define SEQ_RFA_CMN_WL_SYNTH0_BS_OFFSET 0x00002000 +#define SEQ_RFA_CMN_WL_SYNTH0_CLBS_OFFSET 0x00002040 +#define SEQ_RFA_CMN_WL_SYNTH0_BIST_OFFSET 0x00002100 +#define SEQ_RFA_CMN_WL_SYNTH0_PC_OFFSET 0x00002140 +#define SEQ_RFA_CMN_WL_SYNTH0_KVCO_OFFSET 0x00002180 +#define SEQ_RFA_CMN_WL_SYNTH0_AC_OFFSET 0x000021c0 +#define SEQ_RFA_CMN_WL_SYNTH0_LO_OFFSET 0x00002280 +#define SEQ_RFA_CMN_WL_SYNTH1_BS_OFFSET 0x00002800 +#define SEQ_RFA_CMN_WL_SYNTH1_CLBS_OFFSET 0x00002840 +#define SEQ_RFA_CMN_WL_SYNTH1_BIST_OFFSET 0x00002900 +#define SEQ_RFA_CMN_WL_SYNTH1_PC_OFFSET 0x00002940 +#define SEQ_RFA_CMN_WL_SYNTH1_KVCO_OFFSET 0x00002980 +#define SEQ_RFA_CMN_WL_SYNTH1_AC_OFFSET 0x000029c0 +#define SEQ_RFA_CMN_WL_SYNTH1_LO_OFFSET 0x00002a80 +#define SEQ_RFA_CMN_WL_SYNTH2_BS_OFFSET 0x00003000 +#define SEQ_RFA_CMN_WL_SYNTH2_CLBS_OFFSET 0x00003040 +#define SEQ_RFA_CMN_WL_SYNTH2_BIST_OFFSET 0x00003100 +#define SEQ_RFA_CMN_WL_SYNTH2_PC_OFFSET 0x00003140 +#define SEQ_RFA_CMN_WL_SYNTH2_KVCO_OFFSET 0x00003180 +#define SEQ_RFA_CMN_WL_SYNTH2_AC_OFFSET 0x000031c0 +#define SEQ_RFA_CMN_WL_SYNTH2_LO_OFFSET 0x00003280 +#define SEQ_RFA_CMN_HLS_WL_REGFILE_OFFSET 0x00003c00 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block rfa_bt +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_RFA_BT_BT_MTOP_OFFSET 0x00000000 +#define SEQ_RFA_BT_BT_TXBB_OFFSET 0x00000800 +#define SEQ_RFA_BT_BT_TXFE_CH0_OFFSET 0x00000c00 +#define SEQ_RFA_BT_BT_TXFE_CH1_OFFSET 0x00001000 +#define SEQ_RFA_BT_BT_RBIST_TX_BAREBONE_OFFSET 0x00002800 +#define SEQ_RFA_BT_BT_DAC_OFFSET 0x00002980 +#define SEQ_RFA_BT_BT_DAC_DIG_CORRECTION_OFFSET 0x000029c0 +#define SEQ_RFA_BT_BT_DAC_MISC_OFFSET 0x00002ac0 +#define SEQ_RFA_BT_BT_RXBB_CH0_OFFSET 0x00002c00 +#define SEQ_RFA_BT_BT_RXBB_CH1_OFFSET 0x00002e00 +#define SEQ_RFA_BT_BT_RXFE_CH0_OFFSET 0x00003000 +#define SEQ_RFA_BT_BT_RXFE_CH1_OFFSET 0x00003200 +#define SEQ_RFA_BT_BT_SYNTH_BS_OFFSET 0x00003c00 +#define SEQ_RFA_BT_BT_SYNTH_BIST_OFFSET 0x00003c40 +#define SEQ_RFA_BT_BT_SYNTH_PC_OFFSET 0x00003c80 +#define SEQ_RFA_BT_BT_SYNTH_AC_OFFSET 0x00003cc0 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block rfa_wl +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_RFA_WL_WL_MC_2G_CH0_OFFSET 0x00000000 +#define SEQ_RFA_WL_WL_RXFE_2G_CH0_OFFSET 0x00001000 +#define SEQ_RFA_WL_WL_TXFE_2G_CH0_OFFSET 0x00001300 +#define SEQ_RFA_WL_WL_TPC_2G_CH0_OFFSET 0x00002000 +#define SEQ_RFA_WL_WL_MEM_2G_CH0_OFFSET 0x00004000 +#define SEQ_RFA_WL_WL_MC_5G_CH0_OFFSET 0x00008000 +#define SEQ_RFA_WL_WL_RXBB_CH0_OFFSET 0x00008400 +#define SEQ_RFA_WL_WL_TXBB_CH0_OFFSET 0x00008800 +#define SEQ_RFA_WL_WL_RXFE_5G_CH0_OFFSET 0x00009000 +#define SEQ_RFA_WL_WL_TXFE_5G_CH0_OFFSET 0x00009300 +#define SEQ_RFA_WL_WL_TPC_5G_CH0_OFFSET 0x0000a000 +#define SEQ_RFA_WL_RBIST_TX_CH0_OFFSET 0x0000a400 +#define SEQ_RFA_WL_WL_DAC_CH0_OFFSET 0x0000a580 +#define SEQ_RFA_WL_WL_DAC_DIG_CORRECTION_CH0_OFFSET 0x0000a5c0 +#define SEQ_RFA_WL_WL_DAC_MISC_CH0_OFFSET 0x0000a6c0 +#define SEQ_RFA_WL_WL_DAC_BBCLKGEN_CH0_OFFSET 0x0000a734 +#define SEQ_RFA_WL_WL_ADC_CH0_OFFSET 0x0000a740 +#define SEQ_RFA_WL_WL_ADC_POSTPROC_I_EVEN_CH0_OFFSET 0x0000a800 +#define SEQ_RFA_WL_WL_ADC_POSTPROC_I_ODD_CH0_OFFSET 0x0000a840 +#define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_CH0_OFFSET 0x0000a880 +#define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_ODD_CH0_OFFSET 0x0000a8c0 +#define SEQ_RFA_WL_WL_ADC_POSTPROC_RO_CH0_OFFSET 0x0000a900 +#define SEQ_RFA_WL_WL_ADC_BBCLKGEN_CH0_OFFSET 0x0000a99c +#define SEQ_RFA_WL_WL_MEM_5G_CH0_OFFSET 0x0000c000 +#define SEQ_RFA_WL_WL_MC_2G_CH1_OFFSET 0x00010000 +#define SEQ_RFA_WL_WL_RXFE_2G_CH1_OFFSET 0x00011000 +#define SEQ_RFA_WL_WL_TXFE_2G_CH1_OFFSET 0x00011300 +#define SEQ_RFA_WL_WL_TPC_2G_CH1_OFFSET 0x00012000 +#define SEQ_RFA_WL_WL_MEM_2G_CH1_OFFSET 0x00014000 +#define SEQ_RFA_WL_WL_MC_5G_CH1_OFFSET 0x00018000 +#define SEQ_RFA_WL_WL_RXBB_CH1_OFFSET 0x00018400 +#define SEQ_RFA_WL_WL_TXBB_CH1_OFFSET 0x00018800 +#define SEQ_RFA_WL_WL_RXFE_5G_CH1_OFFSET 0x00019000 +#define SEQ_RFA_WL_WL_TXFE_5G_CH1_OFFSET 0x00019300 +#define SEQ_RFA_WL_WL_TPC_5G_CH1_OFFSET 0x0001a000 +#define SEQ_RFA_WL_RBIST_TX_CH1_OFFSET 0x0001a400 +#define SEQ_RFA_WL_WL_DAC_CH1_OFFSET 0x0001a580 +#define SEQ_RFA_WL_WL_DAC_DIG_CORRECTION_CH1_OFFSET 0x0001a5c0 +#define SEQ_RFA_WL_WL_DAC_MISC_CH1_OFFSET 0x0001a6c0 +#define SEQ_RFA_WL_WL_DAC_BBCLKGEN_CH1_OFFSET 0x0001a734 +#define SEQ_RFA_WL_WL_ADC_CH1_OFFSET 0x0001a740 +#define SEQ_RFA_WL_WL_ADC_POSTPROC_I_EVEN_CH1_OFFSET 0x0001a800 +#define SEQ_RFA_WL_WL_ADC_POSTPROC_I_ODD_CH1_OFFSET 0x0001a840 +#define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_EVEN_CH1_OFFSET 0x0001a880 +#define SEQ_RFA_WL_WL_ADC_POSTPROC_Q_ODD_CH1_OFFSET 0x0001a8c0 +#define SEQ_RFA_WL_WL_ADC_POSTPROC_RO_CH1_OFFSET 0x0001a900 +#define SEQ_RFA_WL_WL_ADC_BBCLKGEN_CH1_OFFSET 0x0001a99c +#define SEQ_RFA_WL_WL_MEM_5G_CH1_OFFSET 0x0001c000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block umac_top_reg +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_OFFSET 0x00020000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00020000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00022000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00024000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00026000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00028000 +#define SEQ_UMAC_TOP_REG_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0002a000 +#define SEQ_UMAC_TOP_REG_MAC_TRACER_REG_OFFSET 0x00030000 +#define SEQ_UMAC_TOP_REG_WBM_REG_OFFSET 0x00034000 +#define SEQ_UMAC_TOP_REG_REO_REG_OFFSET 0x00038000 +#define SEQ_UMAC_TOP_REG_TQM_REG_OFFSET 0x0003c000 +#define SEQ_UMAC_TOP_REG_MAC_UMCMN_REG_OFFSET 0x00040000 +#define SEQ_UMAC_TOP_REG_MAC_TCL_REG_OFFSET 0x00044000 +#define SEQ_UMAC_TOP_REG_MAC_CMN_PARSER_CE_REG_OFFSET 0x00047000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block cxc_top_reg +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_CXC_TOP_REG_CXC_BMH_REG_OFFSET 0x00000000 +#define SEQ_CXC_TOP_REG_CXC_LCMH_REG_OFFSET 0x00002000 +#define SEQ_CXC_TOP_REG_CXC_MCIBASIC_REG_OFFSET 0x00004000 +#define SEQ_CXC_TOP_REG_CXC_LMH_REG_OFFSET 0x00006000 +#define SEQ_CXC_TOP_REG_CXC_SMH_REG_OFFSET 0x00008000 +#define SEQ_CXC_TOP_REG_CXC_PMH_REG_OFFSET 0x0000a000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block wmac_top_reg +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_WMAC_TOP_REG_MAC_PDG_REG_OFFSET 0x00000000 +#define SEQ_WMAC_TOP_REG_MAC_TXDMA_REG_OFFSET 0x00003000 +#define SEQ_WMAC_TOP_REG_MAC_RXDMA_REG_OFFSET 0x00006000 +#define SEQ_WMAC_TOP_REG_MAC_MCMN_REG_OFFSET 0x00009000 +#define SEQ_WMAC_TOP_REG_MAC_RXPCU_REG_OFFSET 0x0000c000 +#define SEQ_WMAC_TOP_REG_MAC_TXPCU_REG_OFFSET 0x0000f000 +#define SEQ_WMAC_TOP_REG_MAC_AMPI_REG_OFFSET 0x00012000 +#define SEQ_WMAC_TOP_REG_MAC_RXOLE_REG_OFFSET 0x00015000 +#define SEQ_WMAC_TOP_REG_MAC_RXOLE_PARSER_REG_OFFSET 0x00018000 +#define SEQ_WMAC_TOP_REG_MAC_CCE_REG_OFFSET 0x0001b000 +#define SEQ_WMAC_TOP_REG_MAC_TXOLE_REG_OFFSET 0x0001e000 +#define SEQ_WMAC_TOP_REG_MAC_TXOLE_PARSER_REG_OFFSET 0x00021000 +#define SEQ_WMAC_TOP_REG_MAC_RRI_REG_OFFSET 0x00024000 +#define SEQ_WMAC_TOP_REG_MAC_CRYPTO_REG_OFFSET 0x00027000 +#define SEQ_WMAC_TOP_REG_MAC_HWSCH_REG_OFFSET 0x0002a000 +#define SEQ_WMAC_TOP_REG_MAC_MXI_REG_OFFSET 0x00030000 +#define SEQ_WMAC_TOP_REG_MAC_SFM_REG_OFFSET 0x00033000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block wcssdbg +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_WCSSDBG_WCSS_DBG_DAPROM_OFFSET 0x00000000 +#define SEQ_WCSSDBG_CSR_WCSS_DBG_CSR_OFFSET 0x00001000 +#define SEQ_WCSSDBG_TSGEN_CXTSGEN_OFFSET 0x00002000 +#define SEQ_WCSSDBG_CTIDBG_QC_CTI_32T_8CH_OFFSET 0x00004000 +#define SEQ_WCSSDBG_CTINOC_QC_CTI_8T_8CH_OFFSET 0x00005000 +#define SEQ_WCSSDBG_CTIIRQ_QC_CTI_32T_8CH_OFFSET 0x00006000 +#define SEQ_WCSSDBG_EVENT_MACEVENT_OFFSET 0x00020000 +#define SEQ_WCSSDBG_EVENTFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00021000 +#define SEQ_WCSSDBG_TLV_MACTLV_OFFSET 0x00022000 +#define SEQ_WCSSDBG_TLVFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00023000 +#define SEQ_WCSSDBG_TBUS_MACTBUS_OFFSET 0x00024000 +#define SEQ_WCSSDBG_TBUSFUN_CXATBFUNNEL_32W8SP_OFFSET 0x00025000 +#define SEQ_WCSSDBG_CTIMAC_QC_CTI_12T_8CH_OFFSET 0x00026000 +#define SEQ_WCSSDBG_WCSS_DBG_TSTMP_INJCTR_OFFSET 0x00028000 +#define SEQ_WCSSDBG_TPDM_OFFSET 0x00029000 +#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00029280 +#define SEQ_WCSSDBG_TPDM_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00029000 +#define SEQ_WCSSDBG_TPDA_OFFSET 0x0002a000 +#define SEQ_WCSSDBG_CXATBFUNNEL_128W8SP_OFFSET 0x0002b000 +#define SEQ_WCSSDBG_TMC_CXTMC_F128W32K_OFFSET 0x0002c000 +#define SEQ_WCSSDBG_OUTFUN_CXATBFUNNEL_128W2SP_OFFSET 0x0002e000 +#define SEQ_WCSSDBG_PHYFUN_CXATBFUNNEL_128W2SP_OFFSET 0x0002f000 +#define SEQ_WCSSDBG_OUTDMUX_ATB_DEMUX_OFFSET 0x00030000 +#define SEQ_WCSSDBG_TRCCNTRS_OFFSET 0x00031000 +#define SEQ_WCSSDBG_TLV_TPDM_ATB128_CMB64_OFFSET 0x00032000 +#define SEQ_WCSSDBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00032280 +#define SEQ_WCSSDBG_TLV_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00032000 +#define SEQ_WCSSDBG_MISC_TPDM_ATB128_CMB64_OFFSET 0x00033000 +#define SEQ_WCSSDBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00033280 +#define SEQ_WCSSDBG_MISC_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00033000 +#define SEQ_WCSSDBG_QC_TGU_APCLK_CSAE4EA8E3_OFFSET 0x00034000 +#define SEQ_WCSSDBG_CTITGU_QC_CTI_4T_8CH_OFFSET 0x00035000 +#define SEQ_WCSSDBG_PHYADMUX_ATB_DEMUX_OFFSET 0x00036000 +#define SEQ_WCSSDBG_MISCFUN_CXATBFUNNEL_64W8SP_OFFSET 0x00038000 +#define SEQ_WCSSDBG_UNOC_UMAC_NOC_OFFSET 0x00040000 +#define SEQ_WCSSDBG_PHYA_PHYA_DBG_OFFSET 0x00050000 +#define SEQ_WCSSDBG_PHYA_PHYA_DBG_PHYA_NOC_OFFSET 0x00050000 +#define SEQ_WCSSDBG_PHYA_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00054000 +#define SEQ_WCSSDBG_PHYA_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00055000 +#define SEQ_WCSSDBG_PHYA_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00056000 +#define SEQ_WCSSDBG_PHYA_PHYA_DBG_ITM_OFFSET 0x00058000 +#define SEQ_WCSSDBG_PHYA_PHYA_DBG_DWT_OFFSET 0x00059000 +#define SEQ_WCSSDBG_PHYA_PHYA_DBG_FPB_OFFSET 0x0005a000 +#define SEQ_WCSSDBG_PHYA_PHYA_DBG_SCS_OFFSET 0x0005b000 +#define SEQ_WCSSDBG_PHYA_PHYA_DBG_M3_ETM_OFFSET 0x0005c000 +#define SEQ_WCSSDBG_PHYA_PHYA_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x0005d000 +#define SEQ_WCSSDBG_PHYA_PHYA_DBG_CPU0_M3_AHB_AP_OFFSET 0x0005e000 +#define SEQ_WCSSDBG_BUS_TIMEOUT_OFFSET 0x000a1000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block tpdm_atb64_cmb40_dsb256_csbe6c04f7 +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_SUB_OFFSET 0x00000280 +#define SEQ_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_TPDM_ATB64_CMB40_DSB256_CSBE6C04F7_GPR_OFFSET 0x00000000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block tpdm_atb128_cmb64 +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_SUB_OFFSET 0x00000280 +#define SEQ_TPDM_ATB128_CMB64_TPDM_ATB128_CMB64_GPR_OFFSET 0x00000000 + + +/////////////////////////////////////////////////////////////////////////////////////////////// +// Instance Relative Offsets from Block phya_dbg +/////////////////////////////////////////////////////////////////////////////////////////////// + +#define SEQ_PHYA_DBG_PHYA_NOC_OFFSET 0x00000000 +#define SEQ_PHYA_DBG_FUN_CXATBFUNNEL_64W8SP_OFFSET 0x00004000 +#define SEQ_PHYA_DBG_CTI_QC_CTI_10T_8CH_OFFSET 0x00005000 +#define SEQ_PHYA_DBG_TRC_PHYTRC_CTRL_OFFSET 0x00006000 +#define SEQ_PHYA_DBG_ITM_OFFSET 0x00008000 +#define SEQ_PHYA_DBG_DWT_OFFSET 0x00009000 +#define SEQ_PHYA_DBG_FPB_OFFSET 0x0000a000 +#define SEQ_PHYA_DBG_SCS_OFFSET 0x0000b000 +#define SEQ_PHYA_DBG_M3_ETM_OFFSET 0x0000c000 +#define SEQ_PHYA_DBG_M3CTI_QC_CTI_8T_8CH_OFFSET 0x0000d000 +#define SEQ_PHYA_DBG_CPU0_M3_AHB_AP_OFFSET 0x0000e000 + + +#endif + diff --git a/drivers/staging/fw-api/hw/qca6750/v1/wcss_version.h b/drivers/staging/fw-api/hw/qca6750/v1/wcss_version.h new file mode 100644 index 000000000000..8352a76daac7 --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/wcss_version.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#define WCSS_VERSION 1052 /* E1.5 */ diff --git a/drivers/staging/fw-api/hw/qca6750/v1/wfss_ce_reg_seq_hwioreg.h b/drivers/staging/fw-api/hw/qca6750/v1/wfss_ce_reg_seq_hwioreg.h new file mode 100644 index 000000000000..9c29f2e2110f --- /dev/null +++ b/drivers/staging/fw-api/hw/qca6750/v1/wfss_ce_reg_seq_hwioreg.h @@ -0,0 +1,30 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef __WFSS_CE_REG_SEQ_REG_H__ +#define __WFSS_CE_REG_SEQ_REG_H__ + +#define HOST_SOC_WFSS_CE_REG_BASE (0x01B80000) +#include "hwio.h" + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK \ +HWIO_HOST_SOC_CE_0_DST_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_DEST_MAX_LENGTH_BMSK + +#define HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_CTRL_ADDR(x) (x+0x000000b0) + +#endif diff --git a/drivers/staging/fw-api/hw/qcn9000/sw_monitor_ring.h b/drivers/staging/fw-api/hw/qcn9000/sw_monitor_ring.h new file mode 100644 index 000000000000..c06b0e30f7a4 --- /dev/null +++ b/drivers/staging/fw-api/hw/qcn9000/sw_monitor_ring.h @@ -0,0 +1,1134 @@ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _SW_MONITOR_RING_H_ +#define _SW_MONITOR_RING_H_ +#if !defined(__ASSEMBLER__) +#endif + +#include "rx_mpdu_details.h" +#include "buffer_addr_info.h" + +// ################ START SUMMARY ################# +// +// Dword Fields +// 0-3 struct rx_mpdu_details reo_level_mpdu_frame_info; +// 4-5 struct buffer_addr_info status_buff_addr_info; +// 6 rxdma_push_reason[1:0], rxdma_error_code[6:2], mpdu_fragment_number[10:7], frameless_bar[11], status_buf_count[15:12], end_of_ppdu[16], reserved_6a[31:17] +// 7 phy_ppdu_id[15:0], reserved_7a[19:16], ring_id[27:20], looping_count[31:28] +// +// ################ END SUMMARY ################# + +#define NUM_OF_DWORDS_SW_MONITOR_RING 8 + +struct sw_monitor_ring { + struct rx_mpdu_details reo_level_mpdu_frame_info; + struct buffer_addr_info status_buff_addr_info; + uint32_t rxdma_push_reason : 2, //[1:0] + rxdma_error_code : 5, //[6:2] + mpdu_fragment_number : 4, //[10:7] + frameless_bar : 1, //[11] + status_buf_count : 4, //[15:12] + end_of_ppdu : 1, //[16] + reserved_6a : 15; //[31:17] + uint32_t phy_ppdu_id : 16, //[15:0] + reserved_7a : 4, //[19:16] + ring_id : 8, //[27:20] + looping_count : 4; //[31:28] +}; + +/* + +struct rx_mpdu_details reo_level_mpdu_frame_info + + Consumer: SW + + Producer: RXDMA + + + + Details related to the MPDU being pushed to SW, valid + only if end_of_ppdu is set to 0 + +struct buffer_addr_info status_buff_addr_info + + Consumer: SW + + Producer: RXDMA + + + + Details of the physical address of the first status + buffer used for the PPDU (either the PPDU that included the + MPDU being pushed to SW if end_of_ppdu = 0, or the PPDU + whose end is indicated through end_of_ppdu = 1) + +rxdma_push_reason + + Indicates why RXDMA pushed the frame to this ring + + + + RXDMA detected an error an + pushed this frame to this queue + + RXDMA pushed the + frame to this queue per received routing instructions. No + error within RXDMA was detected + + RXDMA received an RX_FLUSH. As a + result the MSDU link descriptor might not have the + last_msdu_in_mpdu_flag set, but instead WBM might just see a + NULL pointer in the MSDU link descriptor. This is to be + considered a normal condition for this scenario. + + + + + +rxdma_error_code + + Field only valid when rxdma_push_reason is set to + 'rxdma_error_detected.' + + + + MPDU frame is not complete + due to a FIFO overflow error in RXPCU. + + MPDU frame is not complete + due to receiving incomplete MPDU from the PHY + + + CRYPTO reported a decryption + error or CRYPTO received an encrypted frame, but did not get + a valid corresponding key id in the peer entry. + + CRYPTO reported a TKIP MIC + error + + CRYPTO reported an + unencrypted frame error when encrypted was expected + + RX OLE reported an MSDU + length error + + RX OLE reported that max + number of MSDUs allowed in an MPDU got exceeded + + RX OLE reported a parsing + error + + RX OLE reported an A-MSDU + parsing error + + RX OLE reported a timeout + during SA search + + RX OLE reported a timeout + during DA search + + RX OLE reported a + timeout during flow search + + RXDMA received a flush + request + + Rx PCU reported A-MSDU + present as well as a fragmented MPDU. A-MSDU defragmentation + is not supported in Lithium SW so this is treated as an + error. + +mpdu_fragment_number + + Field only valid when Reo_level_mpdu_frame_info. + Rx_mpdu_desc_info_details.Fragment_flag is set and + end_of_ppdu is set to 0. + + + + The fragment number from the 802.11 header. + + + + Note that the sequence number is embedded in the field: + Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details. + Mpdu_sequence_number + + + + + +frameless_bar + + When set, this SW monitor ring struct contains BAR info + from a multi TID BAR frame. The original multi TID BAR frame + itself contained all the REO info for the first TID, but all + the subsequent TID info and their linkage to the REO + descriptors is passed down as 'frameless' BAR info. + + + + The only fields valid in this descriptor when this bit + is within the + + Reo_level_mpdu_frame_info: + + Within Rx_mpdu_desc_info_details: + + Mpdu_Sequence_number + + BAR_frame + + Peer_meta_data + + All other fields shall be set to 0. + + + + + +status_buf_count + + A count of status buffers used so far for the PPDU + (either the PPDU that included the MPDU being pushed to SW + if end_of_ppdu = 0, or the PPDU whose end is indicated + through end_of_ppdu = 1) + +end_of_ppdu + + Pine RXDMA can be configured to generate a separate + 'SW_MONITOR_RING' descriptor at the end of a PPDU (either + through an 'RX_PPDU_END' TLV or through an 'RX_FLUSH') to + demarcate PPDUs. + + + + For such a descriptor, this bit is set to 1 and fields + Reo_level_mpdu_frame_info, mpdu_fragment_number and + Frameless_bar are all set to 0. + + + + Otherwise this bit is set to 0. + +reserved_6a + + + +phy_ppdu_id + + A PPDU counter value that PHY increments for every PPDU + received + + The counter value wraps around. Pine RXDMA can be + configured to copy this from the RX_PPDU_START TLV for every + output descriptor. + + + + + +reserved_7a + + + +ring_id + + Consumer: SW/REO/DEBUG + + Producer: SRNG (of RXDMA) + + + + For debugging. + + This field is filled in by the SRNG module. + + It help to identify the ring that is being looked + +looping_count + + Consumer: SW/REO/DEBUG + + Producer: SRNG (of RXDMA) + + + + For debugging. + + This field is filled in by the SRNG module. + + + + A count value that indicates the number of times the + producer of entries into this Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ + + + /* EXTERNAL REFERENCE : struct rx_mpdu_details reo_level_mpdu_frame_info */ + + + /* EXTERNAL REFERENCE : struct buffer_addr_info msdu_link_desc_addr_info */ + + +/* Description SW_MONITOR_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define SW_MONITOR_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000000 +#define SW_MONITOR_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define SW_MONITOR_RING_0_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000004 +#define SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + +*/ +#define SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000004 +#define SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ +#define SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000004 +#define SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define SW_MONITOR_RING_1_REO_LEVEL_MPDU_FRAME_INFO_MSDU_LINK_DESC_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + + /* EXTERNAL REFERENCE : struct rx_mpdu_desc_info rx_mpdu_desc_info_details */ + + +/* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + The number of MSDUs within the MPDU + + +*/ +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 0x00000008 +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_LSB 0 +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_MASK 0x000000ff + +/* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + The field can have two different meanings based on the + setting of field 'BAR_frame': + + + + 'BAR_frame' is NOT set: + + The MPDU sequence number of the received frame. + + + + 'BAR_frame' is set. + + The MPDU Start sequence number from the BAR frame + + +*/ +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_OFFSET 0x00000008 +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_LSB 8 +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_SEQUENCE_NUMBER_MASK 0x000fff00 + +/* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + When set, this MPDU is a fragment and REO should forward + this fragment MPDU to the REO destination ring without any + reorder checks, pn checks or bitmap update. This implies + that REO is forwarding the pointer to the MSDU link + descriptor. The destination ring is coming from a + programmable register setting in REO + + + + +*/ +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_OFFSET 0x00000008 +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_LSB 20 +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_FRAGMENT_FLAG_MASK 0x00100000 + +/* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + The retry bit setting from the MPDU header of the + received frame + + +*/ +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_OFFSET 0x00000008 +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_LSB 21 +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MPDU_RETRY_BIT_MASK 0x00200000 + +/* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + When set, the MPDU was received as part of an A-MPDU. + + +*/ +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_OFFSET 0x00000008 +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_LSB 22 +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_AMPDU_FLAG_MASK 0x00400000 + +/* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + When set, the received frame is a BAR frame. After + processing, this frame shall be pushed to SW or deleted. + + +*/ +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_OFFSET 0x00000008 +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_LSB 23 +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_BAR_FRAME_MASK 0x00800000 + +/* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO + + Consumer: REO/SW/FW + + Producer: RXDMA + + + + Copied here by RXDMA from RX_MPDU_END + + When not set, REO will Not perform a PN sequence number + check +*/ +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_OFFSET 0x00000008 +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_LSB 24 +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PN_FIELDS_CONTAIN_VALID_INFO_MASK 0x01000000 + +/* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID + + When set, OLE found a valid SA entry for all MSDUs in + this MPDU + + +*/ +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_OFFSET 0x00000008 +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_LSB 25 +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IS_VALID_MASK 0x02000000 + +/* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT + + When set, at least 1 MSDU within the MPDU has an + unsuccessful MAC source address search due to the expiration + of the search timer. + + +*/ +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_OFFSET 0x00000008 +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_LSB 26 +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_SA_IDX_TIMEOUT_MASK 0x04000000 + +/* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID + + When set, OLE found a valid DA entry for all MSDUs in + this MPDU + + +*/ +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_OFFSET 0x00000008 +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_LSB 27 +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_VALID_MASK 0x08000000 + +/* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC + + Field Only valid if da_is_valid is set + + + + When set, at least one of the DA addresses is a + Multicast or Broadcast address. + + +*/ +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_OFFSET 0x00000008 +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_LSB 28 +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IS_MCBC_MASK 0x10000000 + +/* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT + + When set, at least 1 MSDU within the MPDU has an + unsuccessful MAC destination address search due to the + expiration of the search timer. + + +*/ +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_OFFSET 0x00000008 +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_LSB 29 +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_DA_IDX_TIMEOUT_MASK 0x20000000 + +/* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU + + Field only valid when first_msdu_in_mpdu_flag is set. + + + + When set, the contents in the MSDU buffer contains a + 'RAW' MPDU. This 'RAW' MPDU might be spread out over + multiple MSDU buffers. + + +*/ +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_OFFSET 0x00000008 +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_LSB 30 +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_RAW_MPDU_MASK 0x40000000 + +/* Description SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG + + The More Fragment bit setting from the MPDU header of + the received frame + + + + +*/ +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_OFFSET 0x00000008 +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_LSB 31 +#define SW_MONITOR_RING_2_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_MORE_FRAGMENT_FLAG_MASK 0x80000000 + +/* Description SW_MONITOR_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA + + Meta data that SW has programmed in the Peer table entry + of the transmitting STA. + + +*/ +#define SW_MONITOR_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_OFFSET 0x0000000c +#define SW_MONITOR_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_LSB 0 +#define SW_MONITOR_RING_3_REO_LEVEL_MPDU_FRAME_INFO_RX_MPDU_DESC_INFO_DETAILS_PEER_META_DATA_MASK 0xffffffff + + /* EXTERNAL REFERENCE : struct buffer_addr_info status_buff_addr_info */ + + +/* Description SW_MONITOR_RING_4_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0 + + Address (lower 32 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define SW_MONITOR_RING_4_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 0x00000010 +#define SW_MONITOR_RING_4_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0_LSB 0 +#define SW_MONITOR_RING_4_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_31_0_MASK 0xffffffff + +/* Description SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32 + + Address (upper 8 bits) of the MSDU buffer OR + MSDU_EXTENSION descriptor OR Link Descriptor + + + + In case of 'NULL' pointer, this field is set to 0 + + +*/ +#define SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 0x00000014 +#define SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32_LSB 0 +#define SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_BUFFER_ADDR_39_32_MASK 0x000000ff + +/* Description SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER + + Consumer: WBM + + Producer: SW/FW + + + + In case of 'NULL' pointer, this field is set to 0 + + + + Indicates to which buffer manager the buffer OR + MSDU_EXTENSION descriptor OR link descriptor that is being + pointed to shall be returned after the frame has been + processed. It is used by WBM for routing purposes. + + + + This buffer shall be returned + to the WMB buffer idle list + + This buffer shall be + returned to the WMB idle link descriptor idle list + + This buffer shall be returned to the FW + + This buffer shall be returned to the SW, + ring 0 + + This buffer shall be returned to the SW, + ring 1 + + This buffer shall be returned to the SW, + ring 2 + + This buffer shall be returned to the SW, + ring 3 + + This buffer shall be returned to the SW, + ring 4 + + + + +*/ +#define SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER_OFFSET 0x00000014 +#define SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB 8 +#define SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK 0x00000700 + +/* Description SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE + + Cookie field exclusively used by SW. + + + + In case of 'NULL' pointer, this field is set to 0 + + + + HW ignores the contents, accept that it passes the + programmed value on to other descriptors together with the + physical address + + + + Field can be used by SW to for example associate the + buffers physical address with the virtual address + + The bit definitions as used by SW are within SW HLD + specification + + + + NOTE: + + The three most significant bits can have a special + meaning in case this struct is embedded in a TX_MPDU_DETAILS + STRUCT, and field transmit_bw_restriction is set + + + + In case of NON punctured transmission: + + Sw_buffer_cookie[20:19] = 2'b00: 20 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b01: 40 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b10: 80 MHz TX only + + Sw_buffer_cookie[20:19] = 2'b11: 160 MHz TX only + + + + In case of punctured transmission: + + Sw_buffer_cookie[20:18] = 3'b000: pattern 0 only + + Sw_buffer_cookie[20:18] = 3'b001: pattern 1 only + + Sw_buffer_cookie[20:18] = 3'b010: pattern 2 only + + Sw_buffer_cookie[20:18] = 3'b011: pattern 3 only + + Sw_buffer_cookie[20:18] = 3'b100: pattern 4 only + + Sw_buffer_cookie[20:18] = 3'b101: pattern 5 only + + Sw_buffer_cookie[20:18] = 3'b110: pattern 6 only + + Sw_buffer_cookie[20:18] = 3'b111: pattern 7 only + + + + Note: a punctured transmission is indicated by the + presence of TLV TX_PUNCTURE_SETUP embedded in the scheduler + TLV + + + + +*/ +#define SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE_OFFSET 0x00000014 +#define SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE_LSB 11 +#define SW_MONITOR_RING_5_STATUS_BUFF_ADDR_INFO_SW_BUFFER_COOKIE_MASK 0xfffff800 + +/* Description SW_MONITOR_RING_6_RXDMA_PUSH_REASON + + Indicates why RXDMA pushed the frame to this ring + + + + RXDMA detected an error an + pushed this frame to this queue + + RXDMA pushed the + frame to this queue per received routing instructions. No + error within RXDMA was detected + + RXDMA received an RX_FLUSH. As a + result the MSDU link descriptor might not have the + last_msdu_in_mpdu_flag set, but instead WBM might just see a + NULL pointer in the MSDU link descriptor. This is to be + considered a normal condition for this scenario. + + + + +*/ +#define SW_MONITOR_RING_6_RXDMA_PUSH_REASON_OFFSET 0x00000018 +#define SW_MONITOR_RING_6_RXDMA_PUSH_REASON_LSB 0 +#define SW_MONITOR_RING_6_RXDMA_PUSH_REASON_MASK 0x00000003 + +/* Description SW_MONITOR_RING_6_RXDMA_ERROR_CODE + + Field only valid when rxdma_push_reason is set to + 'rxdma_error_detected.' + + + + MPDU frame is not complete + due to a FIFO overflow error in RXPCU. + + MPDU frame is not complete + due to receiving incomplete MPDU from the PHY + + + CRYPTO reported a decryption + error or CRYPTO received an encrypted frame, but did not get + a valid corresponding key id in the peer entry. + + CRYPTO reported a TKIP MIC + error + + CRYPTO reported an + unencrypted frame error when encrypted was expected + + RX OLE reported an MSDU + length error + + RX OLE reported that max + number of MSDUs allowed in an MPDU got exceeded + + RX OLE reported a parsing + error + + RX OLE reported an A-MSDU + parsing error + + RX OLE reported a timeout + during SA search + + RX OLE reported a timeout + during DA search + + RX OLE reported a + timeout during flow search + + RXDMA received a flush + request + + Rx PCU reported A-MSDU + present as well as a fragmented MPDU. A-MSDU defragmentation + is not supported in Lithium SW so this is treated as an + error. +*/ +#define SW_MONITOR_RING_6_RXDMA_ERROR_CODE_OFFSET 0x00000018 +#define SW_MONITOR_RING_6_RXDMA_ERROR_CODE_LSB 2 +#define SW_MONITOR_RING_6_RXDMA_ERROR_CODE_MASK 0x0000007c + +/* Description SW_MONITOR_RING_6_MPDU_FRAGMENT_NUMBER + + Field only valid when Reo_level_mpdu_frame_info. + Rx_mpdu_desc_info_details.Fragment_flag is set and + end_of_ppdu is set to 0. + + + + The fragment number from the 802.11 header. + + + + Note that the sequence number is embedded in the field: + Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details. + Mpdu_sequence_number + + + + +*/ +#define SW_MONITOR_RING_6_MPDU_FRAGMENT_NUMBER_OFFSET 0x00000018 +#define SW_MONITOR_RING_6_MPDU_FRAGMENT_NUMBER_LSB 7 +#define SW_MONITOR_RING_6_MPDU_FRAGMENT_NUMBER_MASK 0x00000780 + +/* Description SW_MONITOR_RING_6_FRAMELESS_BAR + + When set, this SW monitor ring struct contains BAR info + from a multi TID BAR frame. The original multi TID BAR frame + itself contained all the REO info for the first TID, but all + the subsequent TID info and their linkage to the REO + descriptors is passed down as 'frameless' BAR info. + + + + The only fields valid in this descriptor when this bit + is within the + + Reo_level_mpdu_frame_info: + + Within Rx_mpdu_desc_info_details: + + Mpdu_Sequence_number + + BAR_frame + + Peer_meta_data + + All other fields shall be set to 0. + + + + +*/ +#define SW_MONITOR_RING_6_FRAMELESS_BAR_OFFSET 0x00000018 +#define SW_MONITOR_RING_6_FRAMELESS_BAR_LSB 11 +#define SW_MONITOR_RING_6_FRAMELESS_BAR_MASK 0x00000800 + +/* Description SW_MONITOR_RING_6_STATUS_BUF_COUNT + + A count of status buffers used so far for the PPDU + (either the PPDU that included the MPDU being pushed to SW + if end_of_ppdu = 0, or the PPDU whose end is indicated + through end_of_ppdu = 1) +*/ +#define SW_MONITOR_RING_6_STATUS_BUF_COUNT_OFFSET 0x00000018 +#define SW_MONITOR_RING_6_STATUS_BUF_COUNT_LSB 12 +#define SW_MONITOR_RING_6_STATUS_BUF_COUNT_MASK 0x0000f000 + +/* Description SW_MONITOR_RING_6_END_OF_PPDU + + Pine RXDMA can be configured to generate a separate + 'SW_MONITOR_RING' descriptor at the end of a PPDU (either + through an 'RX_PPDU_END' TLV or through an 'RX_FLUSH') to + demarcate PPDUs. + + + + For such a descriptor, this bit is set to 1 and fields + Reo_level_mpdu_frame_info, mpdu_fragment_number and + Frameless_bar are all set to 0. + + + + Otherwise this bit is set to 0. +*/ +#define SW_MONITOR_RING_6_END_OF_PPDU_OFFSET 0x00000018 +#define SW_MONITOR_RING_6_END_OF_PPDU_LSB 16 +#define SW_MONITOR_RING_6_END_OF_PPDU_MASK 0x00010000 + +/* Description SW_MONITOR_RING_6_RESERVED_6A + + +*/ +#define SW_MONITOR_RING_6_RESERVED_6A_OFFSET 0x00000018 +#define SW_MONITOR_RING_6_RESERVED_6A_LSB 17 +#define SW_MONITOR_RING_6_RESERVED_6A_MASK 0xfffe0000 + +/* Description SW_MONITOR_RING_7_PHY_PPDU_ID + + A PPDU counter value that PHY increments for every PPDU + received + + The counter value wraps around. Pine RXDMA can be + configured to copy this from the RX_PPDU_START TLV for every + output descriptor. + + + + +*/ +#define SW_MONITOR_RING_7_PHY_PPDU_ID_OFFSET 0x0000001c +#define SW_MONITOR_RING_7_PHY_PPDU_ID_LSB 0 +#define SW_MONITOR_RING_7_PHY_PPDU_ID_MASK 0x0000ffff + +/* Description SW_MONITOR_RING_7_RESERVED_7A + + +*/ +#define SW_MONITOR_RING_7_RESERVED_7A_OFFSET 0x0000001c +#define SW_MONITOR_RING_7_RESERVED_7A_LSB 16 +#define SW_MONITOR_RING_7_RESERVED_7A_MASK 0x000f0000 + +/* Description SW_MONITOR_RING_7_RING_ID + + Consumer: SW/REO/DEBUG + + Producer: SRNG (of RXDMA) + + + + For debugging. + + This field is filled in by the SRNG module. + + It help to identify the ring that is being looked +*/ +#define SW_MONITOR_RING_7_RING_ID_OFFSET 0x0000001c +#define SW_MONITOR_RING_7_RING_ID_LSB 20 +#define SW_MONITOR_RING_7_RING_ID_MASK 0x0ff00000 + +/* Description SW_MONITOR_RING_7_LOOPING_COUNT + + Consumer: SW/REO/DEBUG + + Producer: SRNG (of RXDMA) + + + + For debugging. + + This field is filled in by the SRNG module. + + + + A count value that indicates the number of times the + producer of entries into this Ring has looped around the + ring. + + At initialization time, this value is set to 0. On the + first loop, this value is set to 1. After the max value is + reached allowed by the number of bits for this field, the + count value continues with 0 again. + + + + In case SW is the consumer of the ring entries, it can + use this field to figure out up to where the producer of + entries has created new entries. This eliminates the need to + check where the head pointer' of the ring is located once + the SW starts processing an interrupt indicating that new + entries have been put into this ring... + + + + Also note that SW if it wants only needs to look at the + LSB bit of this count value. + + +*/ +#define SW_MONITOR_RING_7_LOOPING_COUNT_OFFSET 0x0000001c +#define SW_MONITOR_RING_7_LOOPING_COUNT_LSB 28 +#define SW_MONITOR_RING_7_LOOPING_COUNT_MASK 0xf0000000 + + +#endif // _SW_MONITOR_RING_H_ diff --git a/drivers/staging/qca-wifi-host-cmn/dp/inc/cdp_txrx_cmn_struct.h b/drivers/staging/qca-wifi-host-cmn/dp/inc/cdp_txrx_cmn_struct.h index 5675a74e4131..afdbbf3d9117 100644 --- a/drivers/staging/qca-wifi-host-cmn/dp/inc/cdp_txrx_cmn_struct.h +++ b/drivers/staging/qca-wifi-host-cmn/dp/inc/cdp_txrx_cmn_struct.h @@ -379,6 +379,7 @@ typedef struct ol_osif_vdev_t *ol_osif_vdev_handle; * @wlan_op_mode_sta: STA (client) mode * @wlan_op_mode_monitor: Monitor mode * @wlan_op_mode_ocb: OCB mode + * @wlan_op_mode_nan: NAN mode */ enum wlan_op_mode { wlan_op_mode_unknown, @@ -388,6 +389,7 @@ enum wlan_op_mode { wlan_op_mode_monitor, wlan_op_mode_ocb, wlan_op_mode_ndi, + wlan_op_mode_nan, }; /** diff --git a/drivers/staging/qca-wifi-host-cmn/dp/inc/cdp_txrx_mon.h b/drivers/staging/qca-wifi-host-cmn/dp/inc/cdp_txrx_mon.h index d78cbeba0267..720342fadc3c 100644 --- a/drivers/staging/qca-wifi-host-cmn/dp/inc/cdp_txrx_mon.h +++ b/drivers/staging/qca-wifi-host-cmn/dp/inc/cdp_txrx_mon.h @@ -149,4 +149,144 @@ static inline int cdp_reset_monitor_mode return soc->ops->mon_ops->txrx_reset_monitor_mode(pdev); } + +#ifdef WLAN_FEATURE_PKT_CAPTURE +static inline void +cdp_pktcapture_record_channel( + ol_txrx_soc_handle soc, + uint8_t pdev_id, + int chan_num) +{ + if (!soc || !soc->ops) { + QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, + "%s invalid instance", __func__); + QDF_BUG(0); + return; + } + + if (!soc->ops->pktcapture_ops || + !soc->ops->pktcapture_ops->txrx_pktcapture_record_channel) + return; + + soc->ops->pktcapture_ops->txrx_pktcapture_record_channel(soc, + pdev_id, + chan_num); +} + +static inline void +cdp_set_packet_capture_mode(ol_txrx_soc_handle soc, + uint8_t pdev_id, + uint8_t val) +{ + if (!soc || !soc->ops) { + QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, + "%s invalid instance", __func__); + QDF_BUG(0); + return; + } + + if (!soc->ops->pktcapture_ops || + !soc->ops->pktcapture_ops->txrx_pktcapture_set_mode) + return; + + soc->ops->pktcapture_ops->txrx_pktcapture_set_mode(soc, pdev_id, val); +} + +static inline uint8_t +cdp_get_packet_capture_mode(ol_txrx_soc_handle soc, uint8_t pdev_id) +{ + if (!soc || !soc->ops) { + QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG, + "%s invalid instance", __func__); + QDF_BUG(0); + return 0; + } + + if (!soc->ops->pktcapture_ops || + !soc->ops->pktcapture_ops->txrx_pktcapture_get_mode) + return 0; + + return soc->ops->pktcapture_ops->txrx_pktcapture_get_mode(soc, + pdev_id); +} + +static inline QDF_STATUS +cdp_register_pktcapture_cb( + ol_txrx_soc_handle soc, uint8_t pdev_id, void *ctx, + QDF_STATUS(txrx_pktcapture_cb)(void *, qdf_nbuf_t)) +{ + if (!soc || !soc->ops) { + QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_FATAL, + "%s invalid instance", __func__); + return QDF_STATUS_E_INVAL; + } + + if (!soc->ops->pktcapture_ops || + !soc->ops->pktcapture_ops->txrx_pktcapture_cb_register) + return QDF_STATUS_E_INVAL; + + return soc->ops->pktcapture_ops->txrx_pktcapture_cb_register( + soc, + pdev_id, + ctx, + txrx_pktcapture_cb); +} + +static inline QDF_STATUS +cdp_deregister_pktcapture_cb(ol_txrx_soc_handle soc, uint8_t pdev_id) +{ + if (!soc || !soc->ops) { + QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_FATAL, + "%s invalid instance", __func__); + return QDF_STATUS_E_INVAL; + } + + if (!soc->ops->pktcapture_ops || + !soc->ops->pktcapture_ops->txrx_pktcapture_cb_deregister) + return QDF_STATUS_E_INVAL; + + return soc->ops->pktcapture_ops->txrx_pktcapture_cb_deregister(soc, + pdev_id); +} + +static inline QDF_STATUS +cdp_pktcapture_mgmtpkt_process( + ol_txrx_soc_handle soc, + uint8_t pdev_id, + struct mon_rx_status *txrx_status, + qdf_nbuf_t nbuf, + uint8_t status) +{ + if (!soc || !soc->ops) { + QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_FATAL, + "%s invalid instance", __func__); + return QDF_STATUS_E_INVAL; + } + + if (!soc->ops->pktcapture_ops || + !soc->ops->pktcapture_ops->txrx_pktcapture_mgmtpkt_process) + return QDF_STATUS_E_INVAL; + + return soc->ops->pktcapture_ops->txrx_pktcapture_mgmtpkt_process( + soc, + pdev_id, + txrx_status, + nbuf, + status); +} +#else +static inline uint8_t +cdp_get_packet_capture_mode(ol_txrx_soc_handle soc, uint8_t pdev_id) +{ + return 0; +} + +static inline void +cdp_pktcapture_record_channel(ol_txrx_soc_handle soc, + uint8_t pdev_id, + int chan_num) +{ +} +#endif /* WLAN_FEATURE_PKT_CAPTURE */ + #endif diff --git a/drivers/staging/qca-wifi-host-cmn/dp/inc/cdp_txrx_ops.h b/drivers/staging/qca-wifi-host-cmn/dp/inc/cdp_txrx_ops.h index af6fd6f967da..54cab2998400 100644 --- a/drivers/staging/qca-wifi-host-cmn/dp/inc/cdp_txrx_ops.h +++ b/drivers/staging/qca-wifi-host-cmn/dp/inc/cdp_txrx_ops.h @@ -595,6 +595,40 @@ struct cdp_mon_ops { (struct cdp_pdev *pdev, struct cdp_monitor_filter *filter_val); }; +#ifdef WLAN_FEATURE_PKT_CAPTURE +struct cdp_pktcapture_ops { + void (*txrx_pktcapture_set_mode) + (struct cdp_soc_t *soc, + uint8_t pdev_id, + uint8_t mode); + + uint8_t (*txrx_pktcapture_get_mode) + (struct cdp_soc_t *soc, + uint8_t pdev_id); + + QDF_STATUS (*txrx_pktcapture_cb_register) + (struct cdp_soc_t *soc, + uint8_t pdev_id, + void *context, + QDF_STATUS(cb)(void *, qdf_nbuf_t)); + + QDF_STATUS (*txrx_pktcapture_cb_deregister) + (struct cdp_soc_t *soc, + uint8_t pdev_id); + + QDF_STATUS (*txrx_pktcapture_mgmtpkt_process) + (struct cdp_soc_t *soc, + uint8_t pdev_id, + struct mon_rx_status *txrx_status, + qdf_nbuf_t nbuf, uint8_t status); + + void (*txrx_pktcapture_record_channel) + (struct cdp_soc_t *soc, + uint8_t pdev_id, + int chan_no); +}; +#endif /* #ifdef WLAN_FEATURE_PKT_CAPTURE */ + struct cdp_host_stats_ops { int (*txrx_host_stats_get)(struct cdp_vdev *vdev, struct ol_txrx_stats_req *req); @@ -1154,5 +1188,9 @@ struct cdp_ops { struct cdp_tx_delay_ops *delay_ops; struct cdp_pmf_ops *pmf_ops; #endif /* CONFIG_WIN */ +#ifdef WLAN_FEATURE_PKT_CAPTURE + struct cdp_pktcapture_ops *pktcapture_ops; +#endif + }; #endif diff --git a/drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_internal.h b/drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_internal.h index 4a50b6fe106c..f54fb62f0d88 100644 --- a/drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_internal.h +++ b/drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_internal.h @@ -406,6 +406,9 @@ union ce_desc { * @NAPI_POLL_ENTER: records the start of the napi poll function * @NAPI_COMPLETE: records when interrupts are reenabled * @NAPI_POLL_EXIT: records when the napi poll function returns + * @HIF_RX_DESC_PRE_NBUF_ALLOC: record the packet before nbuf allocation + * @HIF_RX_DESC_PRE_NBUF_MAP: record the packet before nbuf map + * @HIF_RX_DESC_POST_NBUF_MAP: record the packet after nbuf map */ enum hif_ce_event_type { HIF_RX_DESC_POST, @@ -435,6 +438,10 @@ enum hif_ce_event_type { HIF_RX_NBUF_ALLOC_FAILURE = 0x20, HIF_RX_NBUF_MAP_FAILURE, HIF_RX_NBUF_ENQUEUE_FAILURE, + + HIF_RX_DESC_PRE_NBUF_ALLOC, + HIF_RX_DESC_PRE_NBUF_MAP, + HIF_RX_DESC_POST_NBUF_MAP, }; void ce_init_ce_desc_event_log(struct hif_softc *scn, int ce_id, int size); diff --git a/drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_main.c b/drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_main.c index f63194eae3d3..089fc040e6de 100644 --- a/drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_main.c +++ b/drivers/staging/qca-wifi-host-cmn/hif/src/ce/ce_main.c @@ -2099,6 +2099,7 @@ QDF_STATUS hif_post_recv_buffers_for_pipe(struct HIF_CE_pipe_info *pipe_info) struct hif_softc *scn = HIF_GET_SOFTC(pipe_info->HIF_CE_state); QDF_STATUS status; uint32_t bufs_posted = 0; + unsigned int ce_id; buf_sz = pipe_info->buf_sz; if (buf_sz == 0) { @@ -2107,6 +2108,7 @@ QDF_STATUS hif_post_recv_buffers_for_pipe(struct HIF_CE_pipe_info *pipe_info) } ce_hdl = pipe_info->ce_hdl; + ce_id = ((struct CE_state *)ce_hdl)->id; qdf_spin_lock_bh(&pipe_info->recv_bufs_needed_lock); while (atomic_read(&pipe_info->recv_bufs_needed) > 0) { @@ -2116,6 +2118,9 @@ QDF_STATUS hif_post_recv_buffers_for_pipe(struct HIF_CE_pipe_info *pipe_info) atomic_dec(&pipe_info->recv_bufs_needed); qdf_spin_unlock_bh(&pipe_info->recv_bufs_needed_lock); + hif_record_ce_desc_event(scn, ce_id, + HIF_RX_DESC_PRE_NBUF_ALLOC, NULL, NULL, + 0, 0); nbuf = qdf_nbuf_alloc(scn->qdf_dev, buf_sz, 0, 4, false); if (!nbuf) { hif_post_recv_buffers_failure(pipe_info, nbuf, @@ -2125,6 +2130,9 @@ QDF_STATUS hif_post_recv_buffers_for_pipe(struct HIF_CE_pipe_info *pipe_info) return QDF_STATUS_E_NOMEM; } + hif_record_ce_desc_event(scn, ce_id, + HIF_RX_DESC_PRE_NBUF_MAP, NULL, nbuf, + 0, 0); /* * qdf_nbuf_peek_header(nbuf, &data, &unused); * CE_data = dma_map_single(dev, data, buf_sz, ); @@ -2143,7 +2151,9 @@ QDF_STATUS hif_post_recv_buffers_for_pipe(struct HIF_CE_pipe_info *pipe_info) } CE_data = qdf_nbuf_get_frag_paddr(nbuf, 0); - + hif_record_ce_desc_event(scn, ce_id, + HIF_RX_DESC_POST_NBUF_MAP, NULL, nbuf, + 0, 0); qdf_mem_dma_sync_single_for_device(scn->qdf_dev, CE_data, buf_sz, DMA_FROM_DEVICE); status = ce_recv_buf_enqueue(ce_hdl, (void *)nbuf, CE_data); diff --git a/drivers/staging/qca-wifi-host-cmn/os_if/linux/p2p/src/wlan_cfg80211_p2p.c b/drivers/staging/qca-wifi-host-cmn/os_if/linux/p2p/src/wlan_cfg80211_p2p.c index 2694d8a0a7f8..03f8064c665f 100644 --- a/drivers/staging/qca-wifi-host-cmn/os_if/linux/p2p/src/wlan_cfg80211_p2p.c +++ b/drivers/staging/qca-wifi-host-cmn/os_if/linux/p2p/src/wlan_cfg80211_p2p.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -55,10 +55,6 @@ static void wlan_p2p_rx_callback(void *user_data, struct wireless_dev *wdev; uint16_t freq; - cfg80211_debug("user data:%pK, vdev id:%d, rssi:%d, buf:%pK, len:%d", - user_data, rx_frame->vdev_id, rx_frame->rx_rssi, - rx_frame->buf, rx_frame->frame_len); - psoc = user_data; if (!psoc) { cfg80211_err("psoc is null"); @@ -91,8 +87,8 @@ static void wlan_p2p_rx_callback(void *user_data, freq = ieee80211_channel_to_frequency( rx_frame->rx_chan, NL80211_BAND_5GHZ); - cfg80211_debug("Indicate frame over nl80211, vdev id:%d, idx:%d", - rx_frame->vdev_id, wdev->netdev->ifindex); + cfg80211_debug("Indicate frame over nl80211, idx:%d", + wdev->netdev->ifindex); #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 18, 0)) cfg80211_rx_mgmt(wdev, freq, rx_frame->rx_rssi * 100, @@ -129,10 +125,6 @@ static void wlan_p2p_action_tx_cnf_callback(void *user_data, struct wireless_dev *wdev; bool is_success; - cfg80211_debug("user data:%pK, action cookie:%llx, buf:%pK, len:%d, tx status:%d", - user_data, tx_cnf->action_cookie, tx_cnf->buf, - tx_cnf->buf_len, tx_cnf->status); - psoc = user_data; if (!psoc) { cfg80211_err("psoc is null"); diff --git a/drivers/staging/qca-wifi-host-cmn/os_if/linux/qca_vendor.h b/drivers/staging/qca-wifi-host-cmn/os_if/linux/qca_vendor.h index b9bbbf25a09a..c890c7bd0eef 100644 --- a/drivers/staging/qca-wifi-host-cmn/os_if/linux/qca_vendor.h +++ b/drivers/staging/qca-wifi-host-cmn/os_if/linux/qca_vendor.h @@ -334,6 +334,33 @@ * * All the attributes used with this command are defined in * enum qca_wlan_vendor_attr_beacon_reporting_params. + * @QCA_NL80211_VENDOR_SUBCMD_OEM_DATA: This command is used to send OEM data + * binary blobs from application/service to firmware. The attributes + * defined in enum qca_wlan_vendor_attr_oem_data_params are used to + * deliver the parameters. + * @QCA_NL80211_VENDOR_SUBCMD_REQUEST_SAR_LIMITS_EVENT: This acts as an event. + * Host drivers can request the user space entity to set the SAR power + * limits with this event. Accordingly, the user space entity is expected + * to set the SAR power limits. Host drivers can retry this event to the + * user space for the SAR power limits configuration from user space. If + * the driver does not get the SAR power limits from user space for all + * the retried attempts, it can configure a default SAR power limit. + * @QCA_NL80211_VENDOR_SUBCMD_UPDATE_STA_INFO: This acts as a vendor event and + * is used to update the information about the station from the driver to + * userspace. Uses attributes from enum + * qca_wlan_vendor_attr_update_sta_info. + * + * @QCA_NL80211_VENDOR_SUBCMD_DRIVER_DISCONNECT_REASON: This acts as an event. + * The host driver initiates the disconnection for scenarios such as beacon + * miss, NUD failure, peer kick out, etc. The disconnection indication + * through cfg80211_disconnected() expects the reason codes from enum + * ieee80211_reasoncode which does not signify these various reasons why + * the driver has triggered the disconnection. This event will be used to + * send the driver specific reason codes by the host driver to userspace. + * Host drivers should trigger this event and pass the respective reason + * code immediately prior to triggering cfg80211_disconnected(). The + * attributes used with this event are defined in enum + * qca_wlan_vendor_attr_driver_disconnect_reason. */ enum qca_nl80211_vendor_subcmds { @@ -546,6 +573,10 @@ enum qca_nl80211_vendor_subcmds { QCA_NL80211_VENDOR_SUBCMD_PEER_STATS_CACHE_FLUSH = 178, QCA_NL80211_VENDOR_SUBCMD_MPTA_HELPER_CONFIG = 179, QCA_NL80211_VENDOR_SUBCMD_BEACON_REPORTING = 180, + QCA_NL80211_VENDOR_SUBCMD_OEM_DATA = 182, + QCA_NL80211_VENDOR_SUBCMD_GET_SAR_LIMITS_EVENT = 187, + QCA_NL80211_VENDOR_SUBCMD_UPDATE_STA_INFO = 188, + QCA_NL80211_VENDOR_SUBCMD_DRIVER_DISCONNECT_REASON = 189, }; enum qca_wlan_vendor_tos { @@ -669,6 +700,29 @@ enum qca_wlan_vendor_attr_get_station { QCA_WLAN_VENDOR_ATTR_GET_STATION_AFTER_LAST - 1, }; +/** + * enum qca_wlan_vendor_attr_update_sta_info - Defines attributes + * used by QCA_NL80211_VENDOR_SUBCMD_UPDATE_STA_INFO vendor command. + * + * @QCA_WLAN_VENDOR_ATTR_UPDATE_STA_INFO_CONNECT_CHANNELS: Type is NLA_UNSPEC. + * Used in STA mode. This attribute represents the list of channel center + * frequencies in MHz (u32) the station has learnt during the last connection + * or roaming attempt. This information shall not signify the channels for + * an explicit scan request from the user space. Host drivers can update this + * information to the user space in both connected and disconnected state. + * In the disconnected state this information shall signify the channels + * scanned in the last connection/roam attempt that lead to the disconnection. + */ +enum qca_wlan_vendor_attr_update_sta_info { + QCA_WLAN_VENDOR_ATTR_UPDATE_STA_INFO_INVALID = 0, + QCA_WLAN_VENDOR_ATTR_UPDATE_STA_INFO_CONNECT_CHANNELS = 1, + + /* keep last */ + QCA_WLAN_VENDOR_ATTR_UPDATE_STA_INFO_AFTER_LAST, + QCA_WLAN_VENDOR_ATTR_UPDATE_STA_INFO_MAX = + QCA_WLAN_VENDOR_ATTR_UPDATE_STA_INFO_AFTER_LAST - 1, +}; + /** * enum qca_wlan_802_11_mode - dot11 mode * @QCA_WLAN_802_11_MODE_11B: mode B @@ -705,6 +759,8 @@ enum qca_wlan_802_11_mode { * @QCA_WLAN_AUTH_TYPE_WAI_PSK wai psk key * @QCA_WLAN_AUTH_TYPE_CCKM_WPA: cckm wpa key * @QCA_WLAN_AUTH_TYPE_CCKM_RSN: cckm rsn key + * @QCA_WLAN_AUTH_TYPE_FT_SAE: FT sae akm + * @QCA_WLAN_AUTH_TYPE_FT_SUITEB_EAP_SHA384: FT suite B SHA384 */ enum qca_wlan_auth_type { QCA_WLAN_AUTH_TYPE_INVALID, @@ -724,6 +780,8 @@ enum qca_wlan_auth_type { QCA_WLAN_AUTH_TYPE_CCKM_WPA, QCA_WLAN_AUTH_TYPE_CCKM_RSN, QCA_WLAN_AUTH_TYPE_AUTOSWITCH, + QCA_WLAN_AUTH_TYPE_FT_SAE, + QCA_WLAN_AUTH_TYPE_FT_SUITEB_EAP_SHA384, }; /** @@ -782,6 +840,21 @@ enum qca_wlan_auth_type { * @QCA_WLAN_VENDOR_ATTR_GET_STATION_INFO_REMOTE_SGI_ENABLE: * Remote station short GI enable/disable * @QCA_WLAN_VENDOR_ATTR_GET_STATION_INFO_PAD: Attribute type for padding + * @QCA_WLAN_VENDOR_ATTR_GET_STATION_INFO_BEACON_IES: Binary attribute + * containing the raw information elements from Beacon frames. Represents + * the Beacon frames of the current BSS in the connected state. When queried + * in the disconnected state, these IEs correspond to the last connected BSSID. + * @QCA_WLAN_VENDOR_ATTR_GET_STATION_INFO_DRIVER_DISCONNECT_REASON: u32, Driver + * disconnect reason for the last disconnection if the disconnection is + * triggered from the host driver. The values are referred from + * enum qca_disconnect_reason_codes. If the disconnect is from + * peer/userspace this value is QCA_DISCONNECT_REASON_UNSPECIFIED. + * @QCA_WLAN_VENDOR_ATTR_GET_STATION_INFO_ASSOC_REQ_IES: Binary attribute + * Applicable in AP mode only. It contains the raw information elements + * from assoc request frame of the given peer station. User queries with the + * mac address of peer station when it disconnects. Host driver sends + * assoc request frame of the given station. Host driver doesn't provide + * the IEs when the peer station is still in connected state. * @QCA_WLAN_VENDOR_ATTR_GET_STATION_INFO_AFTER_LAST: After last */ enum qca_wlan_vendor_attr_get_station_info { @@ -812,6 +885,20 @@ enum qca_wlan_vendor_attr_get_station_info { #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 7, 0)) QCA_WLAN_VENDOR_ATTR_GET_STATION_INFO_PAD, #endif + QCA_WLAN_VENDOR_ATTR_GET_STATION_INFO_REMOTE_RX_RETRY_COUNT, + QCA_WLAN_VENDOR_ATTR_GET_STATION_INFO_REMOTE_RX_BC_MC_COUNT, + QCA_WLAN_VENDOR_ATTR_GET_STATION_INFO_REMOTE_TX_FAILURE, + QCA_WLAN_VENDOR_ATTR_GET_STATION_INFO_REMOTE_AVG_RSSI_PER_CHAIN, + QCA_WLAN_VENDOR_ATTR_GET_STATION_INFO_REMOTE_TX_RETRY_SUCCEED, + QCA_WLAN_VENDOR_ATTR_GET_STATION_INFO_REMOTE_RX_LAST_PKT_RSSI, + QCA_WLAN_VENDOR_ATTR_GET_STATION_INFO_REMOTE_TX_RETRY, + QCA_WLAN_VENDOR_ATTR_GET_STATION_INFO_REMOTE_TX_RETRY_EXHAUST, + QCA_WLAN_VENDOR_ATTR_GET_STATION_INFO_REMOTE_TX_TOTAL_FW, + QCA_WLAN_VENDOR_ATTR_GET_STATION_INFO_REMOTE_TX_RETRY_FW, + QCA_WLAN_VENDOR_ATTR_GET_STATION_INFO_REMOTE_TX_RETRY_EXHAUST_FW, + QCA_WLAN_VENDOR_ATTR_GET_STATION_INFO_BEACON_IES, + QCA_WLAN_VENDOR_ATTR_GET_STATION_INFO_DRIVER_DISCONNECT_REASON, + QCA_WLAN_VENDOR_ATTR_GET_STATION_INFO_ASSOC_REQ_IES, /* keep last */ QCA_WLAN_VENDOR_ATTR_GET_STATION_INFO_AFTER_LAST, QCA_WLAN_VENDOR_ATTR_GET_STATION_INFO_MAX = @@ -886,6 +973,7 @@ enum qca_wlan_vendor_attr_get_station_info { * @QCA_NL80211_VENDOR_SUBCMD_HANG_REASON_INDEX: hang event reason index * @QCA_NL80211_VENDOR_SUBCMD_WLAN_MAC_INFO_INDEX: MAC mode info index * @QCA_NL80211_VENDOR_SUBCMD_BEACON_REPORTING_INDEX: Beacon reporting index + * @QCA_NL80211_VENDOR_SUBCMD_REQUEST_SAR_LIMITS_INDEX: Request SAR limit index */ enum qca_nl80211_vendor_subcmds_index { @@ -972,6 +1060,9 @@ enum qca_nl80211_vendor_subcmds_index { QCA_NL80211_VENDOR_SUBCMD_THROUGHPUT_CHANGE_EVENT_INDEX, QCA_NL80211_VENDOR_SUBCMD_BEACON_REPORTING_INDEX, QCA_NL80211_VENDOR_SUBCMD_ROAM_INDEX, + QCA_NL80211_VENDOR_SUBCMD_OEM_DATA_INDEX, + QCA_NL80211_VENDOR_SUBCMD_REQUEST_SAR_LIMITS_INDEX, + QCA_NL80211_VENDOR_SUBCMD_UPDATE_STA_INFO_INDEX, }; /** @@ -1334,7 +1425,6 @@ enum qca_wlan_vendor_attr { QCA_WLAN_VENDOR_ATTR_MAX = QCA_WLAN_VENDOR_ATTR_AFTER_LAST - 1 }; -#ifdef FEATURE_WLAN_EXTSCAN enum qca_wlan_vendor_attr_extscan_config_params { QCA_WLAN_VENDOR_ATTR_EXTSCAN_SUBCMD_CONFIG_PARAM_INVALID = 0, @@ -1749,7 +1839,6 @@ enum qca_wlan_vendor_attr_extscan_results { QCA_WLAN_VENDOR_ATTR_EXTSCAN_RESULTS_MAX = QCA_WLAN_VENDOR_ATTR_EXTSCAN_RESULTS_AFTER_LAST - 1, }; -#endif #ifdef WLAN_FEATURE_LINK_LAYER_STATS @@ -3882,6 +3971,26 @@ enum qca_wlan_vendor_attr_config { */ QCA_WLAN_VENDOR_ATTR_CONFIG_GTX = 57, + /* + * Attribute to configure disconnect IEs to the driver. + * This carries an array of unsigned 8-bit characters. + * + * If this is configured, driver shall fill the IEs in disassoc/deauth + * frame. + * These IEs are expected to be considered only for the next + * immediate disconnection (disassoc/deauth frame) originated by + * the DUT, irrespective of the entity (user space/driver/firmware) + * triggering the disconnection. + * The host drivers are not expected to use the IEs set through + * this interface for further disconnections after the first immediate + * disconnection initiated post the configuration. + * If the IEs are also updated through cfg80211 interface (after the + * enhancement to cfg80211_disconnect), host driver is expected to + * take the union of IEs from both of these interfaces and send in + * further disassoc/deauth frames. + */ + QCA_WLAN_VENDOR_ATTR_DISCONNECT_IES = 58, + /* keep last */ QCA_WLAN_VENDOR_ATTR_CONFIG_AFTER_LAST, QCA_WLAN_VENDOR_ATTR_CONFIG_MAX = @@ -3994,6 +4103,104 @@ enum qca_wlan_vendor_attr_offloaded_packets { QCA_WLAN_VENDOR_ATTR_OFFLOADED_PACKETS_AFTER_LAST - 1, }; +/** + * enum qca_disconnect_reason_codes - Specifies driver disconnect reason codes. + * Used when the driver triggers the STA to disconnect from the AP. + * + * @QCA_DISCONNECT_REASON_UNSPECIFIED: The host driver triggered the + * disconnection with the AP due to unspecified reasons. + * + * @QCA_DISCONNECT_REASON_INTERNAL_ROAM_FAILURE: The host driver triggered the + * disconnection with the AP due to a roaming failure. This roaming is triggered + * internally (host driver/firmware). + * + * @QCA_DISCONNECT_REASON_EXTERNAL_ROAM_FAILURE: The driver disconnected from + * the AP when the user/external triggered roaming fails. + * + * @QCA_DISCONNECT_REASON_GATEWAY_REACHABILITY_FAILURE: This reason code is used + * by the host driver whenever gateway reachability failure is detected and the + * driver disconnects with AP. + * + * @QCA_DISCONNECT_REASON_UNSUPPORTED_CHANNEL_CSA: The driver disconnected from + * the AP on a channel switch announcement from it with an unsupported channel. + * + * @QCA_DISCONNECT_REASON_OPER_CHANNEL_DISABLED_INDOOR: On a concurrent AP start + * with indoor channels disabled and if the STA is connected on one of these + * disabled channels, the host driver disconnected the STA with this reason + * code. + * + * @QCA_DISCONNECT_REASON_OPER_CHANNEL_USER_DISABLED: Disconnection due to an + * explicit request from the user to disable the current operating channel. + * + * @QCA_DISCONNECT_REASON_DEVICE_RECOVERY: STA disconnected from the AP due to + * the internal host driver/firmware recovery. + * + * @QCA_DISCONNECT_REASON_KEY_TIMEOUT: The driver triggered the disconnection on + * a timeout for the key installations from the user space. + * + * @QCA_DISCONNECT_REASON_OPER_CHANNEL_BAND_CHANGE: The dDriver disconnected the + * STA on a band change request from the user space to a different band from the + * current operation channel/band. + * + * @QCA_DISCONNECT_REASON_IFACE_DOWN: The STA disconnected from the AP on an + * interface down trigger from the user space. + * + * @QCA_DISCONNECT_REASON_PEER_XRETRY_FAIL: The host driver disconnected the + * STA on getting continuous transmission failures for multiple Data frames. + * + * @QCA_DISCONNECT_REASON_PEER_INACTIVITY: The STA does a keep alive + * notification to the AP by transmitting NULL/G-ARP frames. This disconnection + * represents inactivity from AP on such transmissions. + + * @QCA_DISCONNECT_REASON_SA_QUERY_TIMEOUT: This reason code is used on + * disconnection when SA Query times out (AP does not respond to SA Query). + * + * @QCA_DISCONNECT_REASON_BEACON_MISS_FAILURE: The host driver disconnected the + * STA on missing the beacons continuously from the AP. + * + * @QCA_DISCONNECT_REASON_CHANNEL_SWITCH_FAILURE: Disconnection due to STA not + * able to move to the channel mentioned by the AP in CSA. + * + * @QCA_DISCONNECT_REASON_USER_TRIGGERED: User triggered disconnection. + */ +enum qca_disconnect_reason_codes { + QCA_DISCONNECT_REASON_UNSPECIFIED = 0, + QCA_DISCONNECT_REASON_INTERNAL_ROAM_FAILURE = 1, + QCA_DISCONNECT_REASON_EXTERNAL_ROAM_FAILURE = 2, + QCA_DISCONNECT_REASON_GATEWAY_REACHABILITY_FAILURE = 3, + QCA_DISCONNECT_REASON_UNSUPPORTED_CHANNEL_CSA = 4, + QCA_DISCONNECT_REASON_OPER_CHANNEL_DISABLED_INDOOR = 5, + QCA_DISCONNECT_REASON_OPER_CHANNEL_USER_DISABLED = 6, + QCA_DISCONNECT_REASON_DEVICE_RECOVERY = 7, + QCA_DISCONNECT_REASON_KEY_TIMEOUT = 8, + QCA_DISCONNECT_REASON_OPER_CHANNEL_BAND_CHANGE = 9, + QCA_DISCONNECT_REASON_IFACE_DOWN = 10, + QCA_DISCONNECT_REASON_PEER_XRETRY_FAIL = 11, + QCA_DISCONNECT_REASON_PEER_INACTIVITY = 12, + QCA_DISCONNECT_REASON_SA_QUERY_TIMEOUT = 13, + QCA_DISCONNECT_REASON_BEACON_MISS_FAILURE = 14, + QCA_DISCONNECT_REASON_CHANNEL_SWITCH_FAILURE = 15, + QCA_DISCONNECT_REASON_USER_TRIGGERED = 16, +}; + +/** + * enum qca_wlan_vendor_attr_driver_disconnect_reason - Defines attributes + * used by %QCA_NL80211_VENDOR_SUBCMD_DRIVER_DISCONNECT_REASON vendor command. + * + * @QCA_WLAN_VENDOR_ATTR_DRIVER_DISCONNECT_REASCON_CODE: u32 attribute. + * This attribute represents the driver specific reason codes (local + * driver/firmware initiated reasons for disconnection) defined + * in enum qca_disconnect_reason_codes. + */ +enum qca_wlan_vendor_attr_driver_disconnect_reason { + QCA_WLAN_VENDOR_ATTR_DRIVER_DISCONNECT_REASON_INVALID = 0, + QCA_WLAN_VENDOR_ATTR_DRIVER_DISCONNECT_REASCON_CODE = 1, + + /* keep last */ + QCA_WLAN_VENDOR_ATTR_DRIVER_DISCONNECT_REASON_AFTER_LAST, + QCA_WLAN_VENDOR_ATTR_DRIVER_DISCONNECT_REASON_MAX = + QCA_WLAN_VENDOR_ATTR_DRIVER_DISCONNECT_REASON_AFTER_LAST - 1, +}; #endif /** @@ -7113,4 +7320,22 @@ enum qca_wlan_vendor_attr_beacon_reporting_params { QCA_WLAN_VENDOR_ATTR_BEACON_REPORTING_LAST - 1 }; +/* + * enum qca_wlan_vendor_attr_oem_data_params - Used by the vendor command + * QCA_NL80211_VENDOR_SUBCMD_OEM_DATA. + * + * @QCA_WLAN_VENDOR_ATTR_OEM_DATA_CMD_DATA: The binary blob for the vendor + * command QCA_NL80211_VENDOR_SUBCMD_OEM_DATA are carried through this + * attribute. + * NLA_BINARY attribute, the max size is 1024 bytes. + */ +enum qca_wlan_vendor_attr_oem_data_params { + QCA_WLAN_VENDOR_ATTR_OEM_DATA_INVALID = 0, + QCA_WLAN_VENDOR_ATTR_OEM_DATA_CMD_DATA = 1, + + /* keep last */ + QCA_WLAN_VENDOR_ATTR_OEM_DATA_PARAMS_AFTER_LAST, + QCA_WLAN_VENDOR_ATTR_OEM_DATA_PARAMS_MAX = + QCA_WLAN_VENDOR_ATTR_OEM_DATA_PARAMS_AFTER_LAST - 1 +}; #endif diff --git a/drivers/staging/qca-wifi-host-cmn/os_if/linux/scan/src/wlan_cfg80211_scan.c b/drivers/staging/qca-wifi-host-cmn/os_if/linux/scan/src/wlan_cfg80211_scan.c index d3b73e165e86..31ffffda3a6f 100644 --- a/drivers/staging/qca-wifi-host-cmn/os_if/linux/scan/src/wlan_cfg80211_scan.c +++ b/drivers/staging/qca-wifi-host-cmn/os_if/linux/scan/src/wlan_cfg80211_scan.c @@ -404,10 +404,8 @@ int wlan_cfg80211_sched_scan_start(struct wlan_objmgr_vdev *vdev, status = wlan_abort_scan(pdev, wlan_objmgr_pdev_get_pdev_id(pdev), INVAL_VDEV_ID, INVAL_SCAN_ID, true); - if (QDF_IS_STATUS_ERROR(status)) { - cfg80211_err("aborting the existing scan is unsuccessful"); + if (QDF_IS_STATUS_ERROR(status)) return -EBUSY; - } } req = qdf_mem_malloc(sizeof(*req)); @@ -710,9 +708,7 @@ static QDF_STATUS wlan_scan_request_dequeue( struct pdev_osif_priv *osif_ctx; struct osif_scan_pdev *scan_priv; - cfg80211_debug("Dequeue Scan id: %d", scan_id); - - if ((source == NULL) || (req == NULL)) { + if ((!source) || (!req)) { cfg80211_err("source or request is NULL"); return QDF_STATUS_E_NULL_VALUE; } @@ -758,7 +754,7 @@ static QDF_STATUS wlan_scan_request_dequeue( return QDF_STATUS_SUCCESS; } else { qdf_mutex_release(&scan_priv->scan_req_q_lock); - cfg80211_err("Failed to remove node scan id %d, pending scans %d", + cfg80211_err("Failed to remove scan id %d, pending scans %d", scan_id, qdf_list_size(&scan_priv->scan_req_q)); return status; @@ -767,7 +763,7 @@ static QDF_STATUS wlan_scan_request_dequeue( } while (QDF_STATUS_SUCCESS == qdf_list_peek_next(&scan_priv->scan_req_q, node, &next_node)); qdf_mutex_release(&scan_priv->scan_req_q_lock); - cfg80211_err("Failed to find scan id %d", scan_id); + cfg80211_debug("Failed to find scan id %d", scan_id); return status; } @@ -973,8 +969,8 @@ static void wlan_cfg80211_scan_done_callback( if (!util_is_scan_completed(event, &success)) return; - cfg80211_debug("scan ID = %d vdev id = %d, event type %s(%d) reason = %s(%d)", - scan_id, event->vdev_id, + cfg80211_debug("vdev %d, scan id %d type %s(%d) reason %s(%d)", + event->vdev_id, scan_id, util_scan_get_ev_type_name(event->type), event->type, util_scan_get_ev_reason_name(event->reason), event->reason); @@ -1289,6 +1285,7 @@ int wlan_cfg80211_scan(struct wlan_objmgr_vdev *vdev, bool is_p2p_scan = false; enum wlan_band band; struct net_device *netdev = NULL; + enum QDF_OPMODE opmode; QDF_STATUS qdf_status; psoc = wlan_pdev_get_psoc(pdev); @@ -1296,6 +1293,12 @@ int wlan_cfg80211_scan(struct wlan_objmgr_vdev *vdev, cfg80211_err("Invalid psoc object"); return -EINVAL; } + + opmode = wlan_vdev_mlme_get_opmode(vdev); + + cfg80211_debug("%s(vdev%d): mode %d", request->wdev->netdev->name, + wlan_vdev_get_id(vdev), opmode); + /* Get NL global context from objmgr*/ osif_priv = wlan_pdev_get_ospriv(pdev); if (!osif_priv) { @@ -1309,7 +1312,7 @@ int wlan_cfg80211_scan(struct wlan_objmgr_vdev *vdev, */ if (!wlan_cfg80211_allow_simultaneous_scan(psoc) && !qdf_list_empty(&osif_priv->osif_scan->scan_req_q) && - wlan_vdev_mlme_get_opmode(vdev) != QDF_SAP_MODE) { + opmode != QDF_SAP_MODE) { cfg80211_err("Simultaneous scan disabled, reject scan"); return -EBUSY; } @@ -1352,7 +1355,7 @@ int wlan_cfg80211_scan(struct wlan_objmgr_vdev *vdev, req->scan_req.num_ssids = request->n_ssids; if (req->scan_req.num_ssids > WLAN_SCAN_MAX_NUM_SSID) { - cfg80211_info("number of ssid received %d is greater than MAX %d so copy only MAX nuber of SSIDs", + cfg80211_info("number of ssid %d greater than MAX %d", req->scan_req.num_ssids, WLAN_SCAN_MAX_NUM_SSID); req->scan_req.num_ssids = WLAN_SCAN_MAX_NUM_SSID; @@ -1367,12 +1370,9 @@ int wlan_cfg80211_scan(struct wlan_objmgr_vdev *vdev, qdf_mem_copy(pssid->ssid, &request->ssids[j].ssid[0], pssid->length); - cfg80211_info("SSID number %d: %.*s", j, pssid->length, - pssid->ssid); } } - if (request->ssids || - (wlan_vdev_mlme_get_opmode(vdev) == QDF_P2P_GO_MODE)) + if (request->ssids || (opmode == QDF_P2P_GO_MODE)) req->scan_req.scan_f_passive = false; if (params->half_rate) @@ -1409,8 +1409,6 @@ int wlan_cfg80211_scan(struct wlan_objmgr_vdev *vdev, qdf_set_macaddr_broadcast(&req->scan_req.bssid_list[0]); if (request->n_channels) { - char *chl = qdf_mem_malloc((request->n_channels * 5) + 1); - int len = 0; #ifdef WLAN_POLICY_MGR_ENABLE bool ap_or_go_present = policy_mgr_mode_specific_connection_count( @@ -1418,10 +1416,6 @@ int wlan_cfg80211_scan(struct wlan_objmgr_vdev *vdev, policy_mgr_mode_specific_connection_count( psoc, PM_P2P_GO_MODE, NULL); #endif - if (!chl) { - ret = -ENOMEM; - goto end; - } for (i = 0; i < request->n_channels; i++) { channel = request->channels[i]->hw_value; c_freq = wlan_reg_chan_to_freq(pdev, channel); @@ -1439,8 +1433,6 @@ int wlan_cfg80211_scan(struct wlan_objmgr_vdev *vdev, if (QDF_IS_STATUS_ERROR(qdf_status)) { cfg80211_err("DNBS check failed"); qdf_mem_free(req); - qdf_mem_free(chl); - chl = NULL; ret = -EINVAL; goto end; } @@ -1448,7 +1440,6 @@ int wlan_cfg80211_scan(struct wlan_objmgr_vdev *vdev, continue; } #endif - len += snprintf(chl + len, 5, "%d ", channel); req->scan_req.chan_list.chan[num_chan].freq = c_freq; band = util_scan_scm_freq_to_band(c_freq); if (band == WLAN_BAND_2_4_GHZ) @@ -1461,10 +1452,6 @@ int wlan_cfg80211_scan(struct wlan_objmgr_vdev *vdev, if (num_chan >= WLAN_SCAN_MAX_NUM_CHANNELS) break; } - cfg80211_info("Channel-List: %s", chl); - qdf_mem_free(chl); - chl = NULL; - cfg80211_info("No. of Scan Channels: %d", num_chan); } if (!num_chan) { cfg80211_err("Received zero non-dsrc channels"); @@ -1533,7 +1520,7 @@ int wlan_cfg80211_scan(struct wlan_objmgr_vdev *vdev, qdf_status = ucfg_scan_start(req); if (QDF_IS_STATUS_ERROR(qdf_status)) { - cfg80211_err("ucfg_scan_start returned error %d", qdf_status); + cfg80211_err("scan req failed with error %d", qdf_status); if (qdf_status == QDF_STATUS_E_RESOURCES) cfg80211_err("HO is in progress.So defer the scan by informing busy"); wlan_scan_request_dequeue(pdev, scan_id, &request, @@ -1642,7 +1629,6 @@ QDF_STATUS wlan_abort_scan(struct wlan_objmgr_pdev *pdev, vdev_id, WLAN_OSIF_ID); if (!vdev) { - cfg80211_err("Failed get vdev"); qdf_mem_free(req); return QDF_STATUS_E_INVAL; } @@ -1659,6 +1645,10 @@ QDF_STATUS wlan_abort_scan(struct wlan_objmgr_pdev *pdev, else req->cancel_req.req_type = WLAN_SCAN_CANCEL_VDEV_ALL; + cfg80211_debug("Type %d Vdev %d pdev %d scan id %d sync %d", + req->cancel_req.req_type, req->cancel_req.vdev_id, + req->cancel_req.pdev_id, req->cancel_req.scan_id, sync); + if (sync) status = ucfg_scan_cancel_sync(req); else diff --git a/drivers/staging/qca-wifi-host-cmn/os_if/linux/tdls/src/wlan_cfg80211_tdls.c b/drivers/staging/qca-wifi-host-cmn/os_if/linux/tdls/src/wlan_cfg80211_tdls.c index 161ba2c508a6..763c4ebfdd0e 100644 --- a/drivers/staging/qca-wifi-host-cmn/os_if/linux/tdls/src/wlan_cfg80211_tdls.c +++ b/drivers/staging/qca-wifi-host-cmn/os_if/linux/tdls/src/wlan_cfg80211_tdls.c @@ -107,10 +107,8 @@ void hdd_notify_teardown_tdls_links(struct wlan_objmgr_psoc *psoc) struct wlan_objmgr_vdev *vdev; vdev = ucfg_get_tdls_vdev(psoc, WLAN_OSIF_ID); - if (!vdev) { - cfg80211_err("Unable to get the vdev"); + if (!vdev) return; - } osif_priv = wlan_vdev_get_ospriv(vdev); diff --git a/drivers/staging/qca-wifi-host-cmn/os_if/linux/wlan_osif_request_manager.c b/drivers/staging/qca-wifi-host-cmn/os_if/linux/wlan_osif_request_manager.c index 6943fae1a24f..9251a1997504 100644 --- a/drivers/staging/qca-wifi-host-cmn/os_if/linux/wlan_osif_request_manager.c +++ b/drivers/staging/qca-wifi-host-cmn/os_if/linux/wlan_osif_request_manager.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -101,8 +101,6 @@ struct osif_request *osif_request_alloc(const struct osif_request_params *params request->cookie = cookie++; qdf_list_insert_back(&requests, &request->node); qdf_spin_unlock_bh(&spinlock); - cfg80211_debug("request %pK, cookie %pK, caller %pS", - request, request->cookie, (void *)_RET_IP_); return request; } @@ -132,8 +130,6 @@ struct osif_request *osif_request_get(void *cookie) if (request) request->reference_count++; qdf_spin_unlock_bh(&spinlock); - cfg80211_debug("cookie %pK, request %pK, caller %pS", - cookie, request, (void *)_RET_IP_); return request; } @@ -142,8 +138,6 @@ void osif_request_put(struct osif_request *request) { bool unlinked = false; - cfg80211_debug("request %pK, cookie %pK, caller %pS", - request, request->cookie, (void *)_RET_IP_); qdf_spin_lock_bh(&spinlock); request->reference_count--; if (0 == request->reference_count) { diff --git a/drivers/staging/qca-wifi-host-cmn/qdf/inc/qdf_nbuf.h b/drivers/staging/qca-wifi-host-cmn/qdf/inc/qdf_nbuf.h index f855d7d12b97..c79648bd14de 100644 --- a/drivers/staging/qca-wifi-host-cmn/qdf/inc/qdf_nbuf.h +++ b/drivers/staging/qca-wifi-host-cmn/qdf/inc/qdf_nbuf.h @@ -32,6 +32,7 @@ #include #define IPA_NBUF_OWNER_ID 0xaa55aa55 +#define QDF_NBUF_PKT_TRAC_TYPE_DNS 0x01 #define QDF_NBUF_PKT_TRAC_TYPE_EAPOL 0x02 #define QDF_NBUF_PKT_TRAC_TYPE_DHCP 0x04 #define QDF_NBUF_PKT_TRAC_TYPE_MGMT_ACTION 0x08 @@ -207,6 +208,10 @@ * @he_data5: HE property of received frame * @prev_ppdu_id: ppdu_id in previously received message * @ppdu_id: Id of the PLCP protocol data unit + * @chan_noise_floor: Channel Noise Floor for the pdev + * @tx_status: packet tx status + * @tx_retry_cnt: tx retry count + * @add_rtap_ext: add radio tap extension */ struct mon_rx_status { uint64_t tsft; @@ -273,6 +278,10 @@ struct mon_rx_status { uint32_t ppdu_len; uint32_t prev_ppdu_id; uint32_t ppdu_id; + int16_t chan_noise_floor; + uint8_t tx_status; + uint8_t tx_retry_cnt; + bool add_rtap_ext; }; /* Masks for HE SIG known fields in mon_rx_status structure */ @@ -436,14 +445,15 @@ struct mon_rx_status { #define QDF_MON_STATUS_STA_CODING_KNOWN 0x80 /** - * qdf_proto_type - protocol type + * enum qdf_proto_type - protocol type * @QDF_PROTO_TYPE_DHCP - DHCP * @QDF_PROTO_TYPE_EAPOL - EAPOL * @QDF_PROTO_TYPE_ARP - ARP * @QDF_PROTO_TYPE_MGMT - MGMT * @QDF_PROTO_TYPE_ICMP - ICMP * @QDF_PROTO_TYPE_ICMPv6 - ICMPv6 - * QDF_PROTO_TYPE_EVENT - EVENT + * @QDF_PROTO_TYPE_EVENT - EVENT + * @QDF_PROTO_TYPE_DNS - DNS */ enum qdf_proto_type { QDF_PROTO_TYPE_DHCP, @@ -453,6 +463,7 @@ enum qdf_proto_type { QDF_PROTO_TYPE_ICMP, QDF_PROTO_TYPE_ICMPv6, QDF_PROTO_TYPE_EVENT, + QDF_PROTO_TYPE_DNS, QDF_PROTO_TYPE_MAX }; @@ -488,9 +499,11 @@ enum qdf_proto_type { * @QDF_PROTO_MGMT_DISASSOC - disassoc * @QDF_PROTO_MGMT_AUTH - auth * @QDF_PROTO_MGMT_DEAUTH - deauth - * QDF_ROAM_SYNCH - roam synch indication from fw - * QDF_ROAM_COMPLETE - roam complete cmd to fw - * QDF_ROAM_EVENTID - roam eventid from fw + * @QDF_ROAM_SYNCH - roam synch indication from fw + * @QDF_ROAM_COMPLETE - roam complete cmd to fw + * @QDF_ROAM_EVENTID - roam eventid from fw + * @QDF_PROTO_DNS_QUERY - dns query + * @QDF_PROTO_DNS_RES -dns response */ enum qdf_proto_subtype { QDF_PROTO_INVALID, @@ -527,6 +540,8 @@ enum qdf_proto_subtype { QDF_ROAM_SYNCH, QDF_ROAM_COMPLETE, QDF_ROAM_EVENTID, + QDF_PROTO_DNS_QUERY, + QDF_PROTO_DNS_RES, QDF_PROTO_SUBTYPE_MAX }; diff --git a/drivers/staging/qca-wifi-host-cmn/qdf/inc/qdf_trace.h b/drivers/staging/qca-wifi-host-cmn/qdf/inc/qdf_trace.h index 03c69da15b39..b6c31409bd54 100644 --- a/drivers/staging/qca-wifi-host-cmn/qdf/inc/qdf_trace.h +++ b/drivers/staging/qca-wifi-host-cmn/qdf/inc/qdf_trace.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2014-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -77,6 +77,14 @@ typedef int (qdf_abstract_print)(void *priv, const char *fmt, ...); #define QDF_DEBUG_ERROR 0x20 #define QDF_DEBUG_CFG 0x40 +/* + * Rate limit based on pkt prototype + */ +#define QDF_MAX_DHCP_PKTS_PER_SEC (10) +#define QDF_MAX_EAPOL_PKTS_PER_SEC (10) +#define QDF_MAX_ARP_PKTS_PER_SEC (5) +#define QDF_MAX_DNS_PKTS_PER_SEC (5) +#define QDF_MAX_OTHER_PKTS_PER_SEC (1) /* DP Trace Implementation */ #ifdef CONFIG_DP_TRACE @@ -105,6 +113,7 @@ typedef int (qdf_abstract_print)(void *priv, const char *fmt, ...); #define MAX_QDF_TRACE_RECORDS 4000 #define INVALID_QDF_TRACE_ADDR 0xffffffff #define DEFAULT_QDF_TRACE_DUMP_COUNT 0 +#define QDF_TRACE_DEFAULT_MSDU_ID 0 /* * first parameter to iwpriv command - dump_dp_trace @@ -408,6 +417,9 @@ struct qdf_dp_trace_record_s { * @icmpv6_na: stats for icmpv6 nas * @icmpv6_rs: stats for icmpv6 rss * @icmpv6_ra: stats for icmpv6 ras + * @proto_event_bitmap: defines which protocol to be diag logged. + * refer QDF_NBUF_PKT_TRAC_TYPE_DNS to QDF_NBUF_PKT_TRAC_TYPE_ARP + * for bitmap. */ struct s_qdf_dp_trace_data { uint32_t head; @@ -453,6 +465,7 @@ struct s_qdf_dp_trace_data { u16 icmpv6_na; u16 icmpv6_rs; u16 icmpv6_ra; + uint32_t proto_event_bitmap; }; /** @@ -838,6 +851,35 @@ void qdf_dp_display_event_record(struct qdf_dp_trace_record_s *record, void qdf_dp_trace_record_event(enum QDF_DP_TRACE_ID code, uint8_t vdev_id, uint8_t pdev_id, enum qdf_proto_type type, enum qdf_proto_subtype subtype); + +/** + * qdf_dp_set_proto_event_bitmap() - Set the protocol event bitmap + * @value: proto event bitmap value. + * + * QDF_NBUF_PKT_TRAC_TYPE_DNS 0x01 + * QDF_NBUF_PKT_TRAC_TYPE_EAPOL 0x02 + * QDF_NBUF_PKT_TRAC_TYPE_DHCP 0x04 + * QDF_NBUF_PKT_TRAC_TYPE_ARP 0x10 + * + * Return: none + */ +void qdf_dp_set_proto_event_bitmap(uint32_t value); + +/** + * qdf_dp_log_proto_pkt_info() - Send diag log event + * @sa: source MAC address + * @da: destination MAC address + * @type: pkt type + * @subtype: pkt subtype + * @dir: tx or rx + * @msdu_id: msdu id + * @status: status + * + * Return: none + */ +void qdf_dp_log_proto_pkt_info(uint8_t *sa, uint8_t *da, uint8_t type, + uint8_t subtype, uint8_t dir, uint8_t msdu_id, + uint8_t status); #else static inline bool qdf_dp_trace_log_pkt(uint8_t session_id, struct sk_buff *skb, @@ -916,6 +958,13 @@ void qdf_dp_trace_data_pkt(qdf_nbuf_t nbuf, uint8_t pdev_id, enum qdf_proto_dir dir) { } + +static inline +void qdf_dp_log_proto_pkt_info(uint8_t *sa, uint8_t *da, uint8_t type, + uint8_t subtype, uint8_t dir, uint8_t msdu_id, + uint8_t status) +{ +} #endif void qdf_trace_display(void); diff --git a/drivers/staging/qca-wifi-host-cmn/qdf/inc/qdf_types.h b/drivers/staging/qca-wifi-host-cmn/qdf/inc/qdf_types.h index a9af1d9d5f95..28e3b06d87ff 100644 --- a/drivers/staging/qca-wifi-host-cmn/qdf/inc/qdf_types.h +++ b/drivers/staging/qca-wifi-host-cmn/qdf/inc/qdf_types.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2014-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -355,6 +355,8 @@ typedef bool (*qdf_irqlocked_func_t)(void *); * @QDF_MODULE_ID_CP_STATS: Control Plane Statistics ID * @QDF_MODULE_ID_ACTION_OUI: ACTION OUI module ID * @QDF_MODULE_ID_TARGET: Target module ID + * @QDF_MODULE_ID_FTM_TIME_SYNC: FTM Time sync module ID + * @QDF_MODULE_ID_PKT_CAPTURE: PACKET CAPTURE module ID * @QDF_MODULE_ID_ANY: anything * @QDF_MODULE_ID_MAX: Max place holder module ID */ @@ -460,6 +462,8 @@ typedef enum { QDF_MODULE_ID_CP_STATS, QDF_MODULE_ID_ACTION_OUI, QDF_MODULE_ID_TARGET, + QDF_MODULE_ID_FTM_TIME_SYNC, + QDF_MODULE_ID_PKT_CAPTURE, QDF_MODULE_ID_ANY, QDF_MODULE_ID_MAX, } QDF_MODULE_ID; @@ -521,6 +525,7 @@ typedef enum { * @QDF_BTAMP_MODE: BTAMP mode * @QDF_AHDEMO_MODE: AHDEMO mode * @QDF_TDLS_MODE: TDLS MODE + * @QDF_NAN_DISC_MODE: NAN Discovery device mode * @QDF_MAX_NO_OF_MODE: Max place holder * * These are generic IDs that identify the various roles @@ -542,8 +547,10 @@ enum QDF_OPMODE { QDF_WDS_MODE, QDF_BTAMP_MODE, QDF_AHDEMO_MODE, - QDF_MAX_NO_OF_MODE, QDF_TDLS_MODE, + QDF_NAN_DISC_MODE, + + QDF_MAX_NO_OF_MODE, }; /** @@ -659,15 +666,16 @@ void qdf_vtrace_msg(QDF_MODULE_ID module, QDF_TRACE_LEVEL level, #ifdef WLAN_OPEN_P2P_INTERFACE /* This should match with WLAN_MAX_INTERFACES */ -#define QDF_MAX_CONCURRENCY_PERSONA (4) +#define QDF_MAX_CONCURRENCY_PERSONA (WLAN_MAX_VDEVS) #else -#define QDF_MAX_CONCURRENCY_PERSONA (3) +#define QDF_MAX_CONCURRENCY_PERSONA (WLAN_MAX_VDEVS -1) #endif #define QDF_STA_MASK (1 << QDF_STA_MODE) #define QDF_SAP_MASK (1 << QDF_SAP_MODE) #define QDF_P2P_CLIENT_MASK (1 << QDF_P2P_CLIENT_MODE) #define QDF_P2P_GO_MASK (1 << QDF_P2P_GO_MODE) +#define QDF_MONITOR_MASK (1 << QDF_MONITOR_MODE) #ifdef FEATURE_WLAN_MCC_TO_SCC_SWITCH @@ -1191,4 +1199,20 @@ enum qdf_context_mode { QDF_CONTEXT_TASKLET = 1, }; +/** + * enum qdf_dp_tx_rx_status - TX/RX packet status + * @QDF_TX_RX_STATUS_INVALID: default invalid status + * @QDF_TX_RX_STATUS_OK: successfully sent + acked + * @QDF_TX_RX_STATUS_FW_DISCARD: packet not sent + * @QDF_TX_RX_STATUS_NO_ACK: packet sent but no ack + * @QDF_TX_RX_STATUS_DROP: packet dropped in host + */ +enum qdf_dp_tx_rx_status { + QDF_TX_RX_STATUS_INVALID, + QDF_TX_RX_STATUS_OK, + QDF_TX_RX_STATUS_FW_DISCARD, + QDF_TX_RX_STATUS_NO_ACK, + QDF_TX_RX_STATUS_DROP, +}; + #endif /* __QDF_TYPES_H */ diff --git a/drivers/staging/qca-wifi-host-cmn/qdf/linux/src/qdf_lock.c b/drivers/staging/qca-wifi-host-cmn/qdf/linux/src/qdf_lock.c index 90e1fdd38afa..2bcba863adee 100644 --- a/drivers/staging/qca-wifi-host-cmn/qdf/linux/src/qdf_lock.c +++ b/drivers/staging/qca-wifi-host-cmn/qdf/linux/src/qdf_lock.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2014-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -837,9 +837,6 @@ void qdf_lock_stats_cookie_create(struct lock_stats *stats, qdf_atomic_inc(&lock_cookie_get_failures); count = qdf_atomic_inc_return(&lock_cookie_untracked_num); stats->cookie = (void *) DUMMY_LOCK_COOKIE; - QDF_TRACE(QDF_MODULE_ID_QDF, QDF_TRACE_LEVEL_DEBUG, - "%s: cookie allocation failure, using dummy (%s:%d) count %d", - __func__, func, line, count); return; } diff --git a/drivers/staging/qca-wifi-host-cmn/qdf/linux/src/qdf_mc_timer.c b/drivers/staging/qca-wifi-host-cmn/qdf/linux/src/qdf_mc_timer.c index 57d542b7e212..03daa69e9aa9 100644 --- a/drivers/staging/qca-wifi-host-cmn/qdf/linux/src/qdf_mc_timer.c +++ b/drivers/staging/qca-wifi-host-cmn/qdf/linux/src/qdf_mc_timer.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2014-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -726,17 +726,17 @@ qdf_export_symbol(qdf_mc_timer_start); QDF_STATUS qdf_mc_timer_stop(qdf_mc_timer_t *timer) { /* check for invalid pointer */ - if (NULL == timer) { - QDF_TRACE(QDF_MODULE_ID_QDF, QDF_TRACE_LEVEL_ERROR, - "%s Null timer pointer being passed", __func__); + if (!timer) { + QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_QDF, + "%s Null timer pointer", __func__); QDF_ASSERT(0); return QDF_STATUS_E_INVAL; } /* check if timer refers to an uninitialized object */ if (LINUX_TIMER_COOKIE != timer->platform_info.cookie) { - QDF_TRACE(QDF_MODULE_ID_QDF, QDF_TRACE_LEVEL_ERROR, - "%s: Cannot stop uninitialized timer", __func__); + QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_QDF, + "%s: Cannot stop uninit timer", __func__); QDF_ASSERT(0); return QDF_STATUS_E_INVAL; @@ -747,9 +747,6 @@ QDF_STATUS qdf_mc_timer_stop(qdf_mc_timer_t *timer) if (QDF_TIMER_STATE_RUNNING != timer->state) { qdf_spin_unlock_irqrestore(&timer->platform_info.spinlock); - QDF_TRACE(QDF_MODULE_ID_QDF, QDF_TRACE_LEVEL_INFO_HIGH, - "%s: Cannot stop timer in state = %d", - __func__, timer->state); return QDF_STATUS_SUCCESS; } @@ -769,16 +766,16 @@ QDF_STATUS qdf_mc_timer_stop_sync(qdf_mc_timer_t *timer) { /* check for invalid pointer */ if (!timer) { - QDF_TRACE(QDF_MODULE_ID_QDF, QDF_TRACE_LEVEL_ERROR, - "%s Null timer pointer being passed", __func__); + QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_QDF, + "%s Null timer pointer", __func__); QDF_ASSERT(0); return QDF_STATUS_E_INVAL; } /* check if timer refers to an uninitialized object */ if (LINUX_TIMER_COOKIE != timer->platform_info.cookie) { - QDF_TRACE(QDF_MODULE_ID_QDF, QDF_TRACE_LEVEL_ERROR, - "%s: Cannot stop uninitialized timer", __func__); + QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_QDF, + "%s: Cannot stop uninit timer", __func__); QDF_ASSERT(0); return QDF_STATUS_E_INVAL; @@ -789,9 +786,6 @@ QDF_STATUS qdf_mc_timer_stop_sync(qdf_mc_timer_t *timer) if (QDF_TIMER_STATE_RUNNING != timer->state) { qdf_spin_unlock_irqrestore(&timer->platform_info.spinlock); - QDF_TRACE(QDF_MODULE_ID_QDF, QDF_TRACE_LEVEL_INFO_HIGH, - "%s: Cannot stop timer in state = %d", - __func__, timer->state); return QDF_STATUS_SUCCESS; } diff --git a/drivers/staging/qca-wifi-host-cmn/qdf/linux/src/qdf_mem.c b/drivers/staging/qca-wifi-host-cmn/qdf/linux/src/qdf_mem.c index 453bb3bf4f85..85879b4e4040 100644 --- a/drivers/staging/qca-wifi-host-cmn/qdf/linux/src/qdf_mem.c +++ b/drivers/staging/qca-wifi-host-cmn/qdf/linux/src/qdf_mem.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2014-2019 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -48,15 +48,15 @@ #include #endif -#ifdef MEMORY_DEBUG -#include "qdf_debug_domain.h" -#include - /* Preprocessor Definitions and Constants */ #define QDF_MEM_MAX_MALLOC (4096 * 1024) /* 4 Mega Bytes */ #define QDF_MEM_WARN_THRESHOLD 300 /* ms */ #define QDF_DEBUG_STRING_SIZE 512 +#ifdef MEMORY_DEBUG +#include "qdf_debug_domain.h" +#include + static qdf_list_t qdf_mem_domains[QDF_DEBUG_DOMAIN_COUNT]; static qdf_spinlock_t qdf_mem_list_lock; @@ -1178,6 +1178,11 @@ void *qdf_mem_malloc(size_t size) { void *ptr; + if (!size || size > QDF_MEM_MAX_MALLOC) { + qdf_err("Cannot malloc %zu bytes", size); + return NULL; + } + ptr = qdf_mem_prealloc_get(size); if (ptr) return ptr; diff --git a/drivers/staging/qca-wifi-host-cmn/qdf/linux/src/qdf_nbuf.c b/drivers/staging/qca-wifi-host-cmn/qdf/linux/src/qdf_nbuf.c index ef9bc34474d1..d1722cfee748 100644 --- a/drivers/staging/qca-wifi-host-cmn/qdf/linux/src/qdf_nbuf.c +++ b/drivers/staging/qca-wifi-host-cmn/qdf/linux/src/qdf_nbuf.c @@ -3980,6 +3980,8 @@ qdf_nbuf_update_radiotap_he_mu_other_flags(struct mon_rx_status *rx_status, } #define NORMALIZED_TO_NOISE_FLOOR (-96) +#define IEEE80211_RADIOTAP_TX_STATUS 0 +#define IEEE80211_RADIOTAP_RETRY_COUNT 1 /* This is the length for radiotap, combined length * (Mandatory part struct ieee80211_radiotap_header + RADIOTAP_HEADER_LEN) @@ -3994,6 +3996,11 @@ qdf_nbuf_update_radiotap_he_mu_other_flags(struct mon_rx_status *rx_status, #define RADIOTAP_FIXED_HEADER_LEN 16 #define RADIOTAP_HT_FLAGS_LEN 3 #define RADIOTAP_AMPDU_STATUS_LEN 8 +/* This is Radio Tap Header Extension Length. + * 4 Bytes for Extended it_present bit map + + * 4 bytes padding for alignment + */ +#define RADIOTAP_HEADER_EXT_LEN (2 * sizeof(uint32_t)) #define RADIOTAP_HEADER_LEN (sizeof(struct ieee80211_radiotap_header) + \ RADIOTAP_FIXED_HEADER_LEN + \ RADIOTAP_HT_FLAGS_LEN + \ @@ -4001,7 +4008,8 @@ qdf_nbuf_update_radiotap_he_mu_other_flags(struct mon_rx_status *rx_status, RADIOTAP_AMPDU_STATUS_LEN + \ RADIOTAP_HE_FLAGS_LEN + \ RADIOTAP_HE_MU_FLAGS_LEN + \ - RADIOTAP_HE_MU_OTHER_FLAGS_LEN) + RADIOTAP_HE_MU_OTHER_FLAGS_LEN + \ + RADIOTAP_HEADER_EXT_LEN) #define IEEE80211_RADIOTAP_HE 23 #define IEEE80211_RADIOTAP_HE_MU 24 @@ -4084,6 +4092,14 @@ unsigned int qdf_nbuf_update_radiotap(struct mon_rx_status *rx_status, uint32_t rtap_hdr_len = sizeof(struct ieee80211_radiotap_header); uint32_t rtap_len = rtap_hdr_len; uint8_t length = rtap_len; + uint32_t *rtap_ext = NULL; + + /* Adding Extended Header space */ + if (rx_status->add_rtap_ext) { + rtap_hdr_len += RADIOTAP_HEADER_EXT_LEN; + rtap_len = rtap_hdr_len; + } + length = rtap_len; /* IEEE80211_RADIOTAP_TSFT __le64 microseconds*/ rthdr->it_present = cpu_to_le32(1 << IEEE80211_RADIOTAP_TSFT); @@ -4240,6 +4256,20 @@ unsigned int qdf_nbuf_update_radiotap(struct mon_rx_status *rx_status, } } + /* Add Extension to Radiotap Header & corresponding data */ + if (rx_status->add_rtap_ext) { + rthdr->it_present |= cpu_to_le32(1 << IEEE80211_RADIOTAP_EXT); + rtap_ext = (uint32_t *)&rthdr->it_present; + rtap_ext++; + *rtap_ext = cpu_to_le32(1 << IEEE80211_RADIOTAP_TX_STATUS); + *rtap_ext |= cpu_to_le32(1 << IEEE80211_RADIOTAP_RETRY_COUNT); + + rtap_buf[rtap_len] = rx_status->tx_status; + rtap_len += 1; + rtap_buf[rtap_len] = rx_status->tx_retry_cnt; + rtap_len += 1; + } + rthdr->it_len = cpu_to_le16(rtap_len); if (headroom_sz < rtap_len) { diff --git a/drivers/staging/qca-wifi-host-cmn/qdf/linux/src/qdf_trace.c b/drivers/staging/qca-wifi-host-cmn/qdf/linux/src/qdf_trace.c index e14b56df6c32..8255c154ca10 100644 --- a/drivers/staging/qca-wifi-host-cmn/qdf/linux/src/qdf_trace.c +++ b/drivers/staging/qca-wifi-host-cmn/qdf/linux/src/qdf_trace.c @@ -36,6 +36,7 @@ static int qdf_pidx = -1; #include "qdf_time.h" #include "qdf_mc_timer.h" +#include /* Global qdf print id */ @@ -900,6 +901,18 @@ void qdf_dp_set_proto_bitmap(uint32_t val) } qdf_export_symbol(qdf_dp_set_proto_bitmap); +void qdf_dp_set_proto_event_bitmap(uint32_t value) +{ + g_qdf_dp_trace_data.proto_event_bitmap = value; +} + +qdf_export_symbol(qdf_dp_set_proto_event_bitmap); + +static uint32_t qdf_dp_get_proto_event_bitmap(void) +{ + return g_qdf_dp_trace_data.proto_event_bitmap; +} + /** * qdf_dp_set_no_of_record() - set dp trace no_of_record * @@ -1451,6 +1464,134 @@ static void qdf_dp_add_record(enum QDF_DP_TRACE_ID code, uint8_t pdev_id, QDF_TRACE_DEFAULT_PDEV_ID, info); } +/** + * qdf_get_rate_limit_by_type() - Get the rate limit by pkt type + * @type: packet type + * + * Return: Rate limit value for a particular packet type + */ +static inline +uint8_t qdf_get_rate_limit_by_type(uint8_t type) +{ + switch (type) { + case QDF_PROTO_TYPE_DHCP: + return QDF_MAX_DHCP_PKTS_PER_SEC; + case QDF_PROTO_TYPE_EAPOL: + return QDF_MAX_EAPOL_PKTS_PER_SEC; + case QDF_PROTO_TYPE_ARP: + return QDF_MAX_ARP_PKTS_PER_SEC; + case QDF_PROTO_TYPE_DNS: + return QDF_MAX_DNS_PKTS_PER_SEC; + default: + return QDF_MAX_OTHER_PKTS_PER_SEC; + } +} + +/** + * qdf_get_pkt_type_string() - Get the string based on pkt type + * @subtype: packet type + * + * Return: String based on pkt type + */ +static +uint8_t *qdf_get_pkt_type_string(uint8_t subtype) +{ + switch (subtype) { + case QDF_PROTO_EAPOL_M1: + return "EAPOL-1"; + case QDF_PROTO_EAPOL_M2: + return "EAPOL-2"; + case QDF_PROTO_EAPOL_M3: + return "EAPOL-3"; + case QDF_PROTO_EAPOL_M4: + return "EAPOL-4"; + case QDF_PROTO_DHCP_DISCOVER: + return "DHCP-D"; + case QDF_PROTO_DHCP_REQUEST: + return "DHCP-R"; + case QDF_PROTO_DHCP_OFFER: + return "DHCP-O"; + case QDF_PROTO_DHCP_ACK: + return "DHCP-A"; + case QDF_PROTO_DHCP_NACK: + return "DHCP-NA"; + case QDF_PROTO_ARP_REQ: + return "ARP-RQ"; + case QDF_PROTO_ARP_RES: + return "ARP-RS"; + case QDF_PROTO_DNS_QUERY: + return "DNS_Q"; + case QDF_PROTO_DNS_RES: + return "DNS_RS"; + default: + return "UNKNOWN"; + } +} + +/** + * qdf_get_pkt_status_string() - Get the string based on pkt status + * @status: packet status + * + * Return: String based on pkt status + */ +static +uint8_t *qdf_get_pkt_status_string(uint8_t status) +{ + switch (status) { + case QDF_TX_RX_STATUS_INVALID: + return "inv"; + case QDF_TX_RX_STATUS_OK: + return "succ"; + case QDF_TX_RX_STATUS_FW_DISCARD: + return "disc"; + case QDF_TX_RX_STATUS_NO_ACK: + return "nack"; + case QDF_TX_RX_STATUS_DROP: + return "drop"; + default: + return "unknown"; + } +} + +/** + * qdf_dp_log_proto_pkt_info() - Send diag log with pkt info + * @sa: Source MAC address + * @da: Destination MAC address + * @type: packet type + * @subtype: packet subtype + * @dir: tx or rx + * @msdu_id: MSDU id + * @status: status code + * + * Return: none + */ +void qdf_dp_log_proto_pkt_info(uint8_t *sa, uint8_t *da, uint8_t type, + uint8_t subtype, uint8_t dir, uint8_t msdu_id, + uint8_t status) +{ + uint8_t pkt_rate_limit; + static ulong last_ticks[QDF_PROTO_SUBTYPE_MAX] = {0}; + ulong curr_ticks = jiffies; + + pkt_rate_limit = qdf_get_rate_limit_by_type(type); + + if (!time_after(curr_ticks, last_ticks[subtype] + HZ / pkt_rate_limit)) + return; + + last_ticks[subtype] = curr_ticks; + + if (status == QDF_TX_RX_STATUS_INVALID) + qdf_nofl_info("%s %s: SA:%pM DA:%pM", + qdf_get_pkt_type_string(subtype), dir ? "RX":"TX", + sa, da); + else + qdf_nofl_info("%s %s: SA:%pM DA:%pM msdu_id:%d status: %s", + qdf_get_pkt_type_string(subtype), dir ? "RX":"TX", + sa, da, msdu_id, + qdf_get_pkt_status_string(status)); +} + +qdf_export_symbol(qdf_dp_log_proto_pkt_info); /** * qdf_log_icmpv6_pkt() - log ICMPv6 packet @@ -1569,13 +1710,31 @@ static bool qdf_log_eapol_pkt(uint8_t session_id, struct sk_buff *skb, enum qdf_proto_dir dir, uint8_t pdev_id) { enum qdf_proto_subtype subtype; + uint32_t dp_eap_trace; + uint32_t dp_eap_event; - if ((qdf_dp_get_proto_bitmap() & QDF_NBUF_PKT_TRAC_TYPE_EAPOL) && - ((dir == QDF_TX && QDF_NBUF_CB_PACKET_TYPE_EAPOL == - QDF_NBUF_CB_GET_PACKET_TYPE(skb)) || - (dir == QDF_RX && qdf_nbuf_is_ipv4_eapol_pkt(skb) == true))) { + dp_eap_trace = qdf_dp_get_proto_bitmap() & QDF_NBUF_PKT_TRAC_TYPE_EAPOL; + dp_eap_event = qdf_dp_get_proto_event_bitmap() & + QDF_NBUF_PKT_TRAC_TYPE_EAPOL; + + if (!dp_eap_trace && !dp_eap_event) + return false; + + if (!((dir == QDF_TX && QDF_NBUF_CB_PACKET_TYPE_EAPOL == + QDF_NBUF_CB_GET_PACKET_TYPE(skb)) || + (dir == QDF_RX && qdf_nbuf_is_ipv4_eapol_pkt(skb) == true))) + return false; - subtype = qdf_nbuf_get_eapol_subtype(skb); + subtype = qdf_nbuf_get_eapol_subtype(skb); + + if (dp_eap_event && dir == QDF_RX) + qdf_dp_log_proto_pkt_info(skb->data + QDF_NBUF_SRC_MAC_OFFSET, + skb->data + QDF_NBUF_DEST_MAC_OFFSET, + QDF_PROTO_TYPE_EAPOL, subtype, dir, + QDF_TRACE_DEFAULT_MSDU_ID, + QDF_TX_RX_STATUS_INVALID); + + if (dp_eap_trace) { QDF_NBUF_CB_DP_TRACE_PRINT(skb) = true; if (QDF_TX == dir) QDF_NBUF_CB_TX_DP_TRACE(skb) = 1; @@ -1608,9 +1767,9 @@ static bool qdf_log_eapol_pkt(uint8_t session_id, struct sk_buff *skb, g_qdf_dp_trace_data.eapol_others++; break; } - return true; } - return false; + + return true; } /** @@ -1626,13 +1785,31 @@ static bool qdf_log_dhcp_pkt(uint8_t session_id, struct sk_buff *skb, enum qdf_proto_dir dir, uint8_t pdev_id) { enum qdf_proto_subtype subtype = QDF_PROTO_INVALID; + uint32_t dp_dhcp_trace; + uint32_t dp_dhcp_event; - if ((qdf_dp_get_proto_bitmap() & QDF_NBUF_PKT_TRAC_TYPE_DHCP) && - ((dir == QDF_TX && QDF_NBUF_CB_PACKET_TYPE_DHCP == - QDF_NBUF_CB_GET_PACKET_TYPE(skb)) || - (dir == QDF_RX && qdf_nbuf_is_ipv4_dhcp_pkt(skb) == true))) { + dp_dhcp_trace = qdf_dp_get_proto_bitmap() & QDF_NBUF_PKT_TRAC_TYPE_DHCP; + dp_dhcp_event = qdf_dp_get_proto_event_bitmap() & + QDF_NBUF_PKT_TRAC_TYPE_DHCP; - subtype = qdf_nbuf_get_dhcp_subtype(skb); + if (!dp_dhcp_trace && !dp_dhcp_event) + return false; + + if (!((dir == QDF_TX && QDF_NBUF_CB_PACKET_TYPE_DHCP == + QDF_NBUF_CB_GET_PACKET_TYPE(skb)) || + (dir == QDF_RX && qdf_nbuf_is_ipv4_dhcp_pkt(skb) == true))) + return false; + + subtype = qdf_nbuf_get_dhcp_subtype(skb); + + if (dp_dhcp_event && dir == QDF_RX) + qdf_dp_log_proto_pkt_info(skb->data + QDF_NBUF_SRC_MAC_OFFSET, + skb->data + QDF_NBUF_DEST_MAC_OFFSET, + QDF_PROTO_TYPE_DHCP, subtype, dir, + QDF_TRACE_DEFAULT_MSDU_ID, + QDF_TX_RX_STATUS_INVALID); + + if (dp_dhcp_trace) { QDF_NBUF_CB_DP_TRACE_PRINT(skb) = true; if (QDF_TX == dir) QDF_NBUF_CB_TX_DP_TRACE(skb) = 1; @@ -1668,10 +1845,9 @@ static bool qdf_log_dhcp_pkt(uint8_t session_id, struct sk_buff *skb, g_qdf_dp_trace_data.eapol_others++; break; } - - return true; } - return false; + + return true; } /** @@ -1733,7 +1909,7 @@ static bool qdf_log_arp_pkt(uint8_t session_id, struct sk_buff *skb, bool qdf_dp_trace_log_pkt(uint8_t session_id, struct sk_buff *skb, enum qdf_proto_dir dir, uint8_t pdev_id) { - if (!qdf_dp_get_proto_bitmap()) + if (!qdf_dp_get_proto_bitmap() && !qdf_dp_get_proto_event_bitmap()) return false; if (qdf_log_arp_pkt(session_id, skb, dir, pdev_id)) return true; @@ -1950,6 +2126,82 @@ void qdf_dp_display_ptr_record(struct qdf_dp_trace_record_s *record, } qdf_export_symbol(qdf_dp_display_ptr_record); +static +enum qdf_proto_type qdf_dp_get_pkt_proto_type(qdf_nbuf_t nbuf) +{ + uint8_t pkt_type; + + if (!nbuf) + return QDF_PROTO_TYPE_MAX; + + if (qdf_nbuf_data_is_dns_query(nbuf) || + qdf_nbuf_data_is_dns_response(nbuf)) + return QDF_PROTO_TYPE_DNS; + + pkt_type = QDF_NBUF_CB_GET_PACKET_TYPE(nbuf); + + switch (pkt_type) { + case QDF_NBUF_CB_PACKET_TYPE_EAPOL: + return QDF_PROTO_TYPE_EAPOL; + case QDF_NBUF_CB_PACKET_TYPE_ARP: + return QDF_PROTO_TYPE_ARP; + case QDF_NBUF_CB_PACKET_TYPE_DHCP: + return QDF_PROTO_TYPE_DHCP; + default: + return QDF_PROTO_TYPE_MAX; + } +} + +static +enum qdf_proto_subtype qdf_dp_get_pkt_subtype(qdf_nbuf_t nbuf, + enum qdf_proto_type pkt_type) +{ + switch (pkt_type) { + case QDF_PROTO_TYPE_EAPOL: + return qdf_nbuf_get_eapol_subtype(nbuf); + case QDF_PROTO_TYPE_ARP: + return qdf_nbuf_get_arp_subtype(nbuf); + case QDF_PROTO_TYPE_DHCP: + return qdf_nbuf_get_dhcp_subtype(nbuf); + case QDF_PROTO_TYPE_DNS: + return (qdf_nbuf_data_is_dns_query(nbuf)) ? + QDF_PROTO_DNS_QUERY : QDF_PROTO_DNS_RES; + default: + return QDF_PROTO_INVALID; + } +} + +static +bool qdf_dp_proto_log_enable_check(enum qdf_proto_type pkt_type, + uint16_t status) +{ + if (pkt_type == QDF_PROTO_TYPE_MAX) + return false; + + switch (pkt_type) { + case QDF_PROTO_TYPE_EAPOL: + return qdf_dp_get_proto_event_bitmap() & + QDF_NBUF_PKT_TRAC_TYPE_EAPOL; + case QDF_PROTO_TYPE_DHCP: + return qdf_dp_get_proto_event_bitmap() & + QDF_NBUF_PKT_TRAC_TYPE_DHCP; + case QDF_PROTO_TYPE_ARP: + if (status == QDF_TX_RX_STATUS_OK) + return false; + else + return qdf_dp_get_proto_event_bitmap() & + QDF_NBUF_PKT_TRAC_TYPE_ARP; + case QDF_PROTO_TYPE_DNS: + if (status == QDF_TX_RX_STATUS_OK) + return false; + else + return qdf_dp_get_proto_event_bitmap() & + QDF_NBUF_PKT_TRAC_TYPE_DNS; + default: + return false; + } +} + /** * qdf_dp_trace_ptr() - record dptrace * @code: dptrace code @@ -1967,6 +2219,17 @@ void qdf_dp_trace_ptr(qdf_nbuf_t nbuf, enum QDF_DP_TRACE_ID code, { struct qdf_dp_trace_ptr_buf buf; int buf_size = sizeof(struct qdf_dp_trace_ptr_buf); + enum qdf_proto_type pkt_type; + + pkt_type = qdf_dp_get_pkt_proto_type(nbuf); + if ((code == QDF_DP_TRACE_FREE_PACKET_PTR_RECORD || + code == QDF_DP_TRACE_LI_DP_FREE_PACKET_PTR_RECORD) && + qdf_dp_proto_log_enable_check(pkt_type, status + 1)) + qdf_dp_log_proto_pkt_info(nbuf->data + QDF_NBUF_SRC_MAC_OFFSET, + nbuf->data + QDF_NBUF_DEST_MAC_OFFSET, + pkt_type, + qdf_dp_get_pkt_subtype(nbuf, pkt_type), + QDF_TX, msdu_id, status + 1); if (qdf_dp_enable_check(nbuf, code, QDF_TX) == false) return; @@ -1987,6 +2250,17 @@ void qdf_dp_trace_data_pkt(qdf_nbuf_t nbuf, uint8_t pdev_id, enum qdf_proto_dir dir) { struct qdf_dp_trace_data_buf buf; + enum qdf_proto_type pkt_type; + + pkt_type = qdf_dp_get_pkt_proto_type(nbuf); + if (code == QDF_DP_TRACE_DROP_PACKET_RECORD && + qdf_dp_proto_log_enable_check(pkt_type, QDF_TX_RX_STATUS_DROP)) + qdf_dp_log_proto_pkt_info(nbuf->data + QDF_NBUF_SRC_MAC_OFFSET, + nbuf->data + QDF_NBUF_DEST_MAC_OFFSET, + pkt_type, + qdf_dp_get_pkt_subtype(nbuf, pkt_type), + QDF_TX, msdu_id, + QDF_TX_RX_STATUS_DROP); buf.msdu_id = msdu_id; if (!qdf_dp_enable_check(nbuf, code, dir)) @@ -2801,6 +3075,7 @@ struct category_name_info g_qdf_category_name[MAX_SUPPORTED_CATEGORY] = { [QDF_MODULE_ID_CP_STATS] = {"CP_STATS"}, [QDF_MODULE_ID_ACTION_OUI] = {"action_oui"}, [QDF_MODULE_ID_TARGET] = {"TARGET"}, + [QDF_MODULE_ID_PKT_CAPTURE] = {"pkt_capture"}, [QDF_MODULE_ID_ANY] = {"ANY"}, }; qdf_export_symbol(g_qdf_category_name); @@ -3248,6 +3523,7 @@ static void set_default_trace_levels(struct category_info *cinfo) [QDF_MODULE_ID_ACTION_OUI] = QDF_TRACE_LEVEL_NONE, [QDF_MODULE_ID_CP_STATS] = QDF_TRACE_LEVEL_ERROR, [QDF_MODULE_ID_ANY] = QDF_TRACE_LEVEL_NONE, + [QDF_MODULE_ID_PKT_CAPTURE] = QDF_TRACE_LEVEL_NONE, }; for (i = 0; i < MAX_SUPPORTED_CATEGORY; i++) { diff --git a/drivers/staging/qca-wifi-host-cmn/target_if/cp_stats/src/target_if_mc_cp_stats.c b/drivers/staging/qca-wifi-host-cmn/target_if/cp_stats/src/target_if_mc_cp_stats.c index ee72192752d0..f22a62036bb1 100644 --- a/drivers/staging/qca-wifi-host-cmn/target_if/cp_stats/src/target_if_mc_cp_stats.c +++ b/drivers/staging/qca-wifi-host-cmn/target_if/cp_stats/src/target_if_mc_cp_stats.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -176,10 +176,8 @@ static QDF_STATUS target_if_cp_stats_extract_cca_stats( struct wmi_host_congestion_stats stats = {0}; status = wmi_extract_cca_stats(wmi_hdl, data, &stats); - if (QDF_IS_STATUS_ERROR(status)) { - cp_stats_debug("no congestion stats"); + if (QDF_IS_STATUS_ERROR(status)) return QDF_STATUS_SUCCESS; - } ev->cca_stats = qdf_mem_malloc(sizeof(*ev->cca_stats)); if (!ev->cca_stats) { @@ -187,7 +185,6 @@ static QDF_STATUS target_if_cp_stats_extract_cca_stats( return QDF_STATUS_E_NOMEM; } - ev->cca_stats->vdev_id = stats.vdev_id; ev->cca_stats->congestion = stats.congestion; @@ -295,8 +292,8 @@ static QDF_STATUS target_if_cp_stats_extract_vdev_chain_rssi_stats( for (j = 0; j < MAX_NUM_CHAINS; j++) { dat_snr = rssi_stats.rssi_avg_data[j]; bcn_snr = rssi_stats.rssi_avg_beacon[j]; - cp_stats_err("Chain %d SNR bcn: %d data: %d", j, - bcn_snr, dat_snr); + cp_stats_nofl_debug("Chain %d SNR bcn: %d data: %d", j, + bcn_snr, dat_snr); if (TGT_IS_VALID_SNR(bcn_snr)) ev->vdev_chain_rssi[i].chain_rssi[j] = bcn_snr; else if (TGT_IS_VALID_SNR(dat_snr)) @@ -336,9 +333,17 @@ static QDF_STATUS target_if_cp_stats_extract_event(struct wmi_unified *wmi_hdl, cp_stats_err("stats param extract failed: %d", status); return status; } - cp_stats_debug("num: pdev: %d, vdev: %d, peer: %d, rssi: %d", - stats_param.num_pdev_stats, stats_param.num_vdev_stats, - stats_param.num_peer_stats, stats_param.num_rssi_stats); + cp_stats_nofl_debug("num: pdev: %d, pdev_extd: %d, vdev: %d, peer: %d," + "rssi: %d, bcnflt: %d, channel: %d, bcn: %d, peer_extd2: %d, last_event: %x", + stats_param.num_pdev_stats, + stats_param.num_pdev_ext_stats, + stats_param.num_vdev_stats, + stats_param.num_peer_stats, + stats_param.num_rssi_stats, + stats_param.num_bcnflt_stats, + stats_param.num_chan_stats, + stats_param.num_bcn_stats, + stats_param.num_peer_adv_stats, stats_param.last_event); ev->last_event = stats_param.last_event; status = target_if_cp_stats_extract_pdev_stats(wmi_hdl, &stats_param, diff --git a/drivers/staging/qca-wifi-host-cmn/target_if/nan/src/target_if_nan.c b/drivers/staging/qca-wifi-host-cmn/target_if/nan/src/target_if_nan.c index abb5eec245a9..9522169827d0 100644 --- a/drivers/staging/qca-wifi-host-cmn/target_if/nan/src/target_if_nan.c +++ b/drivers/staging/qca-wifi-host-cmn/target_if/nan/src/target_if_nan.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -68,7 +68,7 @@ static QDF_STATUS target_if_nan_event_flush_cb(struct scheduler_msg *msg) static QDF_STATUS target_if_nan_event_dispatcher(struct scheduler_msg *msg) { - QDF_STATUS status; + QDF_STATUS status = QDF_STATUS_E_INVAL; void *ptr = msg->bodyptr; struct wlan_objmgr_psoc *psoc; struct wlan_objmgr_vdev *vdev = NULL; @@ -122,7 +122,8 @@ static QDF_STATUS target_if_nan_event_dispatcher(struct scheduler_msg *msg) goto free_res; } - status = nan_rx_ops->nan_event_rx(msg); + if (nan_rx_ops->nan_event_rx) + status = nan_rx_ops->nan_event_rx(msg); free_res: if (vdev) wlan_objmgr_vdev_release_ref(vdev, WLAN_NAN_ID); @@ -231,6 +232,42 @@ static int target_if_ndp_initiator_rsp_handler(ol_scn_t scn, uint8_t *data, return 0; } +static int target_if_nan_dmesg_handler(ol_scn_t scn, uint8_t *data, + uint32_t data_len) +{ + QDF_STATUS status; + struct nan_dump_msg msg; + struct wmi_unified *wmi_handle; + struct wlan_objmgr_psoc *psoc; + + psoc = target_if_get_psoc_from_scn_hdl(scn); + if (!psoc) { + target_if_err("psoc is null"); + return -EINVAL; + } + + wmi_handle = get_wmi_unified_hdl_from_psoc(psoc); + if (!wmi_handle) { + target_if_err("wmi_handle is null"); + return -EINVAL; + } + + status = wmi_extract_nan_msg(wmi_handle, data, &msg); + if (QDF_IS_STATUS_ERROR(status)) { + target_if_err("parsing of event failed, %d", status); + return -EINVAL; + } + + if (!msg.msg) { + target_if_err("msg not present %d", msg.data_len); + return -EINVAL; + } + + target_if_info("%s", msg.msg); + + return 0; +} + static int target_if_ndp_ind_handler(ol_scn_t scn, uint8_t *data, uint32_t data_len) { @@ -706,6 +743,15 @@ QDF_STATUS target_if_nan_register_events(struct wlan_objmgr_psoc *psoc) return QDF_STATUS_E_FAILURE; } + ret = wmi_unified_register_event_handler(handle, wmi_nan_dmesg_event_id, + target_if_nan_dmesg_handler, + WMI_RX_UMAC_CTX); + if (ret) { + target_if_err("wmi event registration failed, ret: %d", ret); + target_if_nan_deregister_events(psoc); + return QDF_STATUS_E_FAILURE; + } + ret = wmi_unified_register_event_handler(handle, wmi_ndp_indication_event_id, target_if_ndp_ind_handler, @@ -820,6 +866,13 @@ QDF_STATUS target_if_nan_deregister_events(struct wlan_objmgr_psoc *psoc) status = ret; } + ret = wmi_unified_unregister_event_handler(handle, + wmi_nan_dmesg_event_id); + if (ret) { + target_if_err("wmi event deregistration failed, ret: %d", ret); + status = ret; + } + ret = wmi_unified_unregister_event_handler(handle, wmi_ndp_initiator_rsp_event_id); if (ret) { diff --git a/drivers/staging/qca-wifi-host-cmn/target_if/regulatory/src/target_if_reg.c b/drivers/staging/qca-wifi-host-cmn/target_if/regulatory/src/target_if_reg.c index 6b47a7a0bc06..2e17c650bab1 100644 --- a/drivers/staging/qca-wifi-host-cmn/target_if/regulatory/src/target_if_reg.c +++ b/drivers/staging/qca-wifi-host-cmn/target_if/regulatory/src/target_if_reg.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. * * * Permission to use, copy, modify, and/or distribute this software for @@ -181,7 +181,7 @@ static int tgt_reg_chan_list_update_handler(ol_scn_t handle, qdf_mem_free(reg_info->reg_rules_5g_ptr); qdf_mem_free(reg_info); - target_if_debug("processed reg channel list ret_val %d", ret_val); + TARGET_IF_EXIT(); return ret_val; } @@ -277,7 +277,7 @@ static int tgt_reg_ch_avoid_event_handler(ol_scn_t handle, return -EFAULT; } - target_if_debug("processed CH avoid event"); + TARGET_IF_EXIT(); return 0; } @@ -413,6 +413,29 @@ static QDF_STATUS tgt_if_regulatory_stop_11d_scan( reg_stop_11d_scan_req); } +/** + * tgt_if_regulatory_send_ctl_info() - Sends CTL info to firmware + * @psoc: Pointer to psoc + * @params: Pointer to argument list + * + * Return: QDF_STATUS + */ +static QDF_STATUS +tgt_if_regulatory_send_ctl_info(struct wlan_objmgr_psoc *psoc, + struct reg_ctl_params *params) +{ + wmi_unified_t wmi_handle = get_wmi_unified_hdl_from_psoc(psoc); + + if (!wmi_handle) + return QDF_STATUS_E_FAILURE; + + return wmi_unified_send_regdomain_info_to_fw_cmd(wmi_handle, + params->regd, + params->regd_2g, + params->regd_5g, + params->ctl_2g, + params->ctl_5g); +} QDF_STATUS target_if_register_regulatory_tx_ops(struct wlan_lmac_if_tx_ops *tx_ops) @@ -453,6 +476,8 @@ QDF_STATUS target_if_register_regulatory_tx_ops(struct wlan_lmac_if_tx_ops reg_ops->unregister_ch_avoid_event_handler = tgt_if_regulatory_unregister_ch_avoid_event_handler; + reg_ops->send_ctl_info = tgt_if_regulatory_send_ctl_info; + return QDF_STATUS_SUCCESS; } diff --git a/drivers/staging/qca-wifi-host-cmn/target_if/wifi_pos/src/target_if_wifi_pos.c b/drivers/staging/qca-wifi-host-cmn/target_if/wifi_pos/src/target_if_wifi_pos.c index f9592196e578..ccdf09163a08 100644 --- a/drivers/staging/qca-wifi-host-cmn/target_if/wifi_pos/src/target_if_wifi_pos.c +++ b/drivers/staging/qca-wifi-host-cmn/target_if/wifi_pos/src/target_if_wifi_pos.c @@ -260,7 +260,7 @@ static int wifi_pos_oem_err_rpt_ev_handler(ol_scn_t scn, uint8_t *buf, /** * wifi_pos_oem_data_req() - start OEM data request to target - * @wma_handle: wma handle + * @psoc: the pointer to psoc object manager * @req: start request params * * Return: QDF_STATUS diff --git a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/cmn_defs/inc/wlan_cmn_ieee80211.h b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/cmn_defs/inc/wlan_cmn_ieee80211.h index 66f58c0cd6ba..c10b9d604009 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/cmn_defs/inc/wlan_cmn_ieee80211.h +++ b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/cmn_defs/inc/wlan_cmn_ieee80211.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -66,6 +66,17 @@ #define QCA_OUI 0xf0fd8c #define QCA_OUI_WHC_TYPE 0x00 +#define ADAPTIVE_11R_OUI 0x964000 +#define ADAPTIVE_11R_OUI_TYPE 0x2C + +#define OUI_LENGTH 4 +#define OUI_TYPE_BITS 24 +#define MAX_ADAPTIVE_11R_IE_LEN 8 + +#define SAE_SINGLE_PMK_OUI 0x964000 +#define SAE_SINGLE_PMK_TYPE 0x03 +#define MAX_SAE_SINGLE_PMK_IE_LEN 8 + /* Temporary vendor specific IE for 11n pre-standard interoperability */ #define VENDOR_HT_OUI 0x00904c #define VENDOR_HT_CAP_ID 51 @@ -406,8 +417,10 @@ enum extn_element_ie { #define WLAN_AKM_SHA256_IEEE8021X 0x05 #define WLAN_AKM_SHA256_PSK 0x06 #define WLAN_AKM_SAE 0x08 +#define WLAN_AKM_FT_SAE 0x09 #define WLAN_AKM_SUITEB_EAP_SHA256 0x0B #define WLAN_AKM_SUITEB_EAP_SHA384 0x0C +#define WLAN_AKM_FT_SUITEB_EAP_SHA384 0x0D #define WLAN_AKM_FILS_SHA256 0x0E #define WLAN_AKM_FILS_SHA384 0x0F #define WLAN_AKM_FILS_FT_SHA256 0x10 @@ -1354,6 +1367,36 @@ is_he_op_oui(uint8_t *frm) ((ATH_HE_OP_SUBTYPE << 24) | ATH_HE_OUI)); } +/** + * is_adaptive_11r_oui() - Function to check if vendor IE is ADAPTIVE 11R OUI + * @frm: vendor IE pointer + * + * API to check if vendor IE is ADAPTIVE 11R OUI + * + * Return: true if its ADAPTIVE 11r OUI + */ +static inline bool +is_adaptive_11r_oui(uint8_t *frm) +{ + return (frm[1] > OUI_LENGTH) && (LE_READ_4(frm + 2) == + ((ADAPTIVE_11R_OUI_TYPE << OUI_TYPE_BITS) | ADAPTIVE_11R_OUI)); +} + +/** + * is_sae_single_pmk_oui() - Fun to check if vendor IE is sae single pmk OUI + * @frm: vendor IE pointer + * + * API to check if vendor IE is sae single pmk OUI + * + * Return: true if its sae single pmk OUI + */ +static inline bool +is_sae_single_pmk_oui(uint8_t *frm) +{ + return (frm[1] > OUI_LENGTH) && (LE_READ_4(frm + 2) == + ((SAE_SINGLE_PMK_TYPE << OUI_TYPE_BITS) | SAE_SINGLE_PMK_OUI)); +} + /** * wlan_parse_rsn_ie() - parse rsn ie * @rsn_ie: rsn ie ptr diff --git a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/inc/wlan_cmn.h b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/inc/wlan_cmn.h index 27815073c39e..27ff8919bb7b 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/inc/wlan_cmn.h +++ b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/inc/wlan_cmn.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -250,6 +250,8 @@ * @WLAN_UMAC_COMP_IPA: IPA * @WLAN_UMAC_COMP_CP_STATS: Control Plane Statistics * @WLAN_UMAC_COMP_ACTION_OUI: ACTION OUI + * @WLAN_UMAC_COMP_FTM_TIME_SYNC: WLAN FTM TIMESYNC + * @WLAN_UMAC_COMP_PKT_CAPTURE: Packet capture component * @WLAN_UMAC_COMP_ID_MAX: Maximum components in UMAC * * This id is static. @@ -285,6 +287,8 @@ enum wlan_umac_comp_id { WLAN_UMAC_COMP_IPA = 26, WLAN_UMAC_COMP_CP_STATS = 27, WLAN_UMAC_COMP_ACTION_OUI = 28, + WLAN_UMAC_COMP_FTM_TIME_SYNC = 29, + WLAN_UMAC_COMP_PKT_CAPTURE = 30, WLAN_UMAC_COMP_ID_MAX, }; @@ -301,72 +305,132 @@ typedef enum { } WLAN_DEV_TYPE; /** - * enum wlan_phymode - phy mode - * @WLAN_PHYMODE_AUTO: autoselect - * @WLAN_PHYMODE_11A: 5GHz, OFDM - * @WLAN_PHYMODE_11B: 2GHz, CCK - * @WLAN_PHYMODE_11G: 2GHz, OFDM - * @WLAN_PHYMODE_11NA_HT20: 5Ghz, HT20 - * @WLAN_PHYMODE_11NG_HT20: 2Ghz, HT20 - * @WLAN_PHYMODE_11NA_HT40PLUS: 5Ghz, HT40 (ext ch +1) - * @WLAN_PHYMODE_11NA_HT40MINUS: 5Ghz, HT40 (ext ch -1) - * @WLAN_PHYMODE_11NG_HT40PLUS: 2Ghz, HT40 (ext ch +1) - * @WLAN_PHYMODE_11NG_HT40MINUS: 2Ghz, HT40 (ext ch -1) - * @WLAN_PHYMODE_11NG_HT40: 2Ghz, Auto HT40 - * @WLAN_PHYMODE_11NA_HT40: 5Ghz, Auto HT40 - * @WLAN_PHYMODE_11AC_VHT20: 5Ghz, VHT20 - * @WLAN_PHYMODE_11AC_VHT40PLUS: 5Ghz, VHT40 (Ext ch +1) - * @WLAN_PHYMODE_11AC_VHT40MINUS:5Ghz VHT40 (Ext ch -1) - * @WLAN_PHYMODE_11AC_VHT40: 5Ghz, VHT40 - * @WLAN_PHYMODE_11AC_VHT80: 5Ghz, VHT80 - * @WLAN_PHYMODE_11AC_VHT160: 5Ghz, VHT160 - * @WLAN_PHYMODE_11AC_VHT80_80: 5Ghz, VHT80_80 - * @WLAN_PHYMODE_11AXA_HE20: 5GHz, HE20 - * @WLAN_PHYMODE_11AXG_HE20: 2GHz, HE20 - * @WLAN_PHYMODE_11AXA_HE40PLUS: 5GHz, HE40 (ext ch +1) - * @WLAN_PHYMODE_11AXA_HE40MINUS:5GHz, HE40 (ext ch -1) - * @WLAN_PHYMODE_11AXG_HE40PLUS: 2GHz, HE40 (ext ch +1) - * @WLAN_PHYMODE_11AXG_HE40MINUS:2GHz, HE40 (ext ch -1) - * @WLAN_PHYMODE_11AXA_HE40: 5GHz, HE40 - * @WLAN_PHYMODE_11AXG_HE40: 2GHz, HE40 - * @WLAN_PHYMODE_11AXA_HE80: 5GHz, HE80 - * @WLAN_PHYMODE_11AXA_HE160: 5GHz, HE160 - * @WLAN_PHYMODE_11AXA_HE80_80: 5GHz, HE80_80 + * enum wlan_phymode - phy mode + * @WLAN_PHYMODE_AUTO: autoselect + * @WLAN_PHYMODE_11A: 5GHz, OFDM + * @WLAN_PHYMODE_11B: 2GHz, CCK + * @WLAN_PHYMODE_11G: 2GHz, OFDM + * @WLAN_PHYMODE_11G_ONLY: 2GHz only + * @WLAN_PHYMODE_11NA_HT20: 5Ghz, HT20 + * @WLAN_PHYMODE_11NG_HT20: 2Ghz, HT20 + * @WLAN_PHYMODE_11NA_HT40: 5Ghz, Auto HT40 + * @WLAN_PHYMODE_11NG_HT40PLUS: 2Ghz, HT40 (ext ch +1) + * @WLAN_PHYMODE_11NG_HT40MINUS: 2Ghz, HT40 (ext ch -1) + * @WLAN_PHYMODE_11NG_HT40: 2Ghz, Auto HT40 + * @WLAN_PHYMODE_11AC_VHT20: 5Ghz, VHT20 + * @WLAN_PHYMODE_11AC_VHT20_2G: 2Ghz, VHT20 + * @WLAN_PHYMODE_11AC_VHT40: 5Ghz, VHT40 + * @WLAN_PHYMODE_11AC_VHT40PLUS_2G: 2Ghz, VHT40 (ext ch +1) + * @WLAN_PHYMODE_11AC_VHT40MINUS_2G: 2Ghz, VHT40 (ext ch -1) + * @WLAN_PHYMODE_11AC_VHT40_2G: 2Ghz, VHT40 + * @WLAN_PHYMODE_11AC_VHT80: 5Ghz, VHT80 + * @WLAN_PHYMODE_11AC_VHT80_2G: 2Ghz, VHT80 + * @WLAN_PHYMODE_11AC_VHT160: 5Ghz, VHT160 + * @WLAN_PHYMODE_11AC_VHT80_80: 5Ghz, VHT80_80 + * @WLAN_PHYMODE_11AXA_HE20: 5GHz, HE20 + * @WLAN_PHYMODE_11AXG_HE20: 2GHz, HE20 + * @WLAN_PHYMODE_11AXA_HE40: 5GHz, HE40 + * @WLAN_PHYMODE_11AXG_HE40PLUS: 2GHz, HE40 (ext ch +1) + * @WLAN_PHYMODE_11AXG_HE40MINUS:2GHz, HE40 (ext ch -1) + * @WLAN_PHYMODE_11AXG_HE40: 2GHz, HE40 + * @WLAN_PHYMODE_11AXA_HE80: 5GHz, HE80 + * @WLAN_PHYMODE_11AXG_HE80: 2GHz, HE80 + * @WLAN_PHYMODE_11AXA_HE160: 5GHz, HE160 + * @WLAN_PHYMODE_11AXA_HE80_80: 5GHz, HE80_80 + * @WLAN_PHYMODE_MAX: Max phymode */ enum wlan_phymode { - WLAN_PHYMODE_AUTO = 0, - WLAN_PHYMODE_11A = 1, - WLAN_PHYMODE_11B = 2, - WLAN_PHYMODE_11G = 3, - WLAN_PHYMODE_11NA_HT20 = 4, - WLAN_PHYMODE_11NG_HT20 = 5, - WLAN_PHYMODE_11NA_HT40PLUS = 6, - WLAN_PHYMODE_11NA_HT40MINUS = 7, - WLAN_PHYMODE_11NG_HT40PLUS = 8, - WLAN_PHYMODE_11NG_HT40MINUS = 9, - WLAN_PHYMODE_11NG_HT40 = 10, - WLAN_PHYMODE_11NA_HT40 = 11, - WLAN_PHYMODE_11AC_VHT20 = 12, - WLAN_PHYMODE_11AC_VHT40PLUS = 13, - WLAN_PHYMODE_11AC_VHT40MINUS = 14, - WLAN_PHYMODE_11AC_VHT40 = 15, - WLAN_PHYMODE_11AC_VHT80 = 16, - WLAN_PHYMODE_11AC_VHT160 = 17, - WLAN_PHYMODE_11AC_VHT80_80 = 18, - WLAN_PHYMODE_11AXA_HE20 = 19, - WLAN_PHYMODE_11AXG_HE20 = 20, - WLAN_PHYMODE_11AXA_HE40PLUS = 21, - WLAN_PHYMODE_11AXA_HE40MINUS = 22, - WLAN_PHYMODE_11AXG_HE40PLUS = 23, - WLAN_PHYMODE_11AXG_HE40MINUS = 24, - WLAN_PHYMODE_11AXA_HE40 = 25, - WLAN_PHYMODE_11AXG_HE40 = 26, - WLAN_PHYMODE_11AXA_HE80 = 27, - WLAN_PHYMODE_11AXA_HE160 = 28, - WLAN_PHYMODE_11AXA_HE80_80 = 29, + WLAN_PHYMODE_AUTO = 0, + WLAN_PHYMODE_11A = 1, + WLAN_PHYMODE_11B = 2, + WLAN_PHYMODE_11G = 3, + WLAN_PHYMODE_11G_ONLY = 4, + WLAN_PHYMODE_11NA_HT20 = 5, + WLAN_PHYMODE_11NG_HT20 = 6, + WLAN_PHYMODE_11NA_HT40 = 7, + WLAN_PHYMODE_11NG_HT40PLUS = 8, + WLAN_PHYMODE_11NG_HT40MINUS = 9, + WLAN_PHYMODE_11NG_HT40 = 10, + WLAN_PHYMODE_11AC_VHT20 = 11, + WLAN_PHYMODE_11AC_VHT20_2G = 12, + WLAN_PHYMODE_11AC_VHT40 = 13, + WLAN_PHYMODE_11AC_VHT40PLUS_2G = 14, + WLAN_PHYMODE_11AC_VHT40MINUS_2G = 15, + WLAN_PHYMODE_11AC_VHT40_2G = 16, + WLAN_PHYMODE_11AC_VHT80 = 17, + WLAN_PHYMODE_11AC_VHT80_2G = 18, + WLAN_PHYMODE_11AC_VHT160 = 19, + WLAN_PHYMODE_11AC_VHT80_80 = 20, + WLAN_PHYMODE_11AXA_HE20 = 21, + WLAN_PHYMODE_11AXG_HE20 = 22, + WLAN_PHYMODE_11AXA_HE40 = 23, + WLAN_PHYMODE_11AXG_HE40PLUS = 24, + WLAN_PHYMODE_11AXG_HE40MINUS = 25, + WLAN_PHYMODE_11AXG_HE40 = 26, + WLAN_PHYMODE_11AXA_HE80 = 27, + WLAN_PHYMODE_11AXG_HE80 = 28, + WLAN_PHYMODE_11AXA_HE160 = 29, + WLAN_PHYMODE_11AXA_HE80_80 = 30, + WLAN_PHYMODE_MAX }; -#define WLAN_PHYMODE_MAX (WLAN_PHYMODE_11AXA_HE80_80 + 1) +#define IS_WLAN_PHYMODE_160MHZ(_mode) ({typeof(_mode) mode = (_mode); \ + ((mode) == WLAN_PHYMODE_11AC_VHT80_80) || \ + ((mode) == WLAN_PHYMODE_11AC_VHT160) || \ + ((mode) == WLAN_PHYMODE_11AXA_HE80_80) || \ + ((mode) == WLAN_PHYMODE_11AXA_HE160); }) + +#define IS_WLAN_PHYMODE_80MHZ(_mode) ({typeof(_mode) mode = (_mode); \ + ((mode) == WLAN_PHYMODE_11AC_VHT80) || \ + ((mode) == WLAN_PHYMODE_11AC_VHT80_2G) || \ + ((mode) == WLAN_PHYMODE_11AXA_HE80) || \ + ((mode) == WLAN_PHYMODE_11AXG_HE80); }) + +#define IS_WLAN_PHYMODE_40MHZ(_mode) ({typeof(_mode) mode = (_mode); \ + ((mode) == WLAN_PHYMODE_11NG_HT40) || \ + ((mode) == WLAN_PHYMODE_11NG_HT40PLUS) || \ + ((mode) == WLAN_PHYMODE_11NG_HT40MINUS) || \ + ((mode) == WLAN_PHYMODE_11NA_HT40) || \ + ((mode) == WLAN_PHYMODE_11AC_VHT40) || \ + ((mode) == WLAN_PHYMODE_11AC_VHT40_2G) || \ + ((mode) == WLAN_PHYMODE_11AC_VHT40PLUS_2G) || \ + ((mode) == WLAN_PHYMODE_11AC_VHT40MINUS_2G) || \ + ((mode) == WLAN_PHYMODE_11AXA_HE40) || \ + ((mode) == WLAN_PHYMODE_11AXG_HE40) || \ + ((mode) == WLAN_PHYMODE_11AXG_HE40PLUS) || \ + ((mode) == WLAN_PHYMODE_11AXG_HE40MINUS); }) + +#define IS_WLAN_PHYMODE_HT(_mode) ({typeof(_mode) mode = (_mode); \ + ((mode) == WLAN_PHYMODE_11NA_HT20) || \ + ((mode) == WLAN_PHYMODE_11NG_HT20) || \ + ((mode) == WLAN_PHYMODE_11NA_HT40) || \ + ((mode) == WLAN_PHYMODE_11NG_HT40PLUS) || \ + ((mode) == WLAN_PHYMODE_11NG_HT40MINUS) || \ + ((mode) == WLAN_PHYMODE_11NG_HT40); }) + +#define IS_WLAN_PHYMODE_VHT(_mode) ({typeof(_mode) mode = (_mode); \ + ((mode) == WLAN_PHYMODE_11AC_VHT20) || \ + ((mode) == WLAN_PHYMODE_11AC_VHT20_2G) || \ + ((mode) == WLAN_PHYMODE_11AC_VHT40) || \ + ((mode) == WLAN_PHYMODE_11AC_VHT40PLUS_2G) || \ + ((mode) == WLAN_PHYMODE_11AC_VHT40MINUS_2G) || \ + ((mode) == WLAN_PHYMODE_11AC_VHT40_2G) || \ + ((mode) == WLAN_PHYMODE_11AC_VHT80) || \ + ((mode) == WLAN_PHYMODE_11AC_VHT80_2G) || \ + ((mode) == WLAN_PHYMODE_11AC_VHT160) || \ + ((mode) == WLAN_PHYMODE_11AC_VHT80_80); }) + +#define IS_WLAN_PHYMODE_HE(_mode) ({typeof(_mode) mode = (_mode); \ + ((mode) == WLAN_PHYMODE_11AXA_HE20) || \ + ((mode) == WLAN_PHYMODE_11AXG_HE20) || \ + ((mode) == WLAN_PHYMODE_11AXA_HE40) || \ + ((mode) == WLAN_PHYMODE_11AXG_HE40) || \ + ((mode) == WLAN_PHYMODE_11AXG_HE40PLUS) || \ + ((mode) == WLAN_PHYMODE_11AXG_HE40MINUS) || \ + ((mode) == WLAN_PHYMODE_11AXA_HE80) || \ + ((mode) == WLAN_PHYMODE_11AXG_HE80) || \ + ((mode) == WLAN_PHYMODE_11AXA_HE160) || \ + ((mode) == WLAN_PHYMODE_11AXA_HE80_80); }) /** * enum wlan_phy_ch_width - channel width @@ -499,6 +563,8 @@ enum wlan_pmf_cap { * @WLAN_AUTH_TYPE_OWE: OWE * @WLAN_AUTH_TYPE_SUITEB_EAP_SHA256: EAP SHA256 * @WLAN_AUTH_TYPE_SUITEB_EAP_SHA384: EAP SHA384 + * @WLAN_AUTH_TYPE_FT_SAE: FT SAE + * @WLAN_AUTH_TYPE_FT_SUITEB_EAP_SHA384: FT suiteb SHA384 * @WLAN_AUTH_TYPE_ANY: To match any auth type * @WLAN_NUM_OF_SUPPORT_AUTH_TYPE: Max no of Auth type */ @@ -529,6 +595,8 @@ enum wlan_auth_type { WLAN_AUTH_TYPE_SUITEB_EAP_SHA256, WLAN_AUTH_TYPE_SUITEB_EAP_SHA384, WLAN_AUTH_TYPE_OSEN, + WLAN_AUTH_TYPE_FT_SAE, + WLAN_AUTH_TYPE_FT_SUITEB_EAP_SHA384, WLAN_AUTH_TYPE_ANY, WLAN_NUM_OF_SUPPORT_AUTH_TYPE = WLAN_AUTH_TYPE_ANY, }; diff --git a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/mgmt_txrx/core/src/wlan_mgmt_txrx_main.c b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/mgmt_txrx/core/src/wlan_mgmt_txrx_main.c index 7946a2ccefe6..8d213b2515b1 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/mgmt_txrx/core/src/wlan_mgmt_txrx_main.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/mgmt_txrx/core/src/wlan_mgmt_txrx_main.c @@ -131,8 +131,6 @@ struct mgmt_txrx_desc_elem_t *wlan_mgmt_txrx_desc_get( qdf_spin_unlock_bh(&mgmt_txrx_pdev_ctx->mgmt_desc_pool.desc_pool_lock); - mgmt_txrx_info("retrieved mgmt desc: %pK with desc id: %d", - mgmt_txrx_desc, mgmt_txrx_desc->desc_id); return mgmt_txrx_desc; } @@ -168,6 +166,4 @@ void wlan_mgmt_txrx_desc_put( qdf_spin_unlock_bh(&mgmt_txrx_pdev_ctx->mgmt_desc_pool.desc_pool_lock); - mgmt_txrx_info("put mgmt desc: %pK with desc id: %d into freelist", - desc, desc->desc_id); } diff --git a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/obj_mgr/inc/wlan_objmgr_cmn.h b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/obj_mgr/inc/wlan_objmgr_cmn.h index b3351eb484a1..7958908eee37 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/obj_mgr/inc/wlan_objmgr_cmn.h +++ b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/obj_mgr/inc/wlan_objmgr_cmn.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -223,6 +223,8 @@ typedef void (*wlan_objmgr_peer_status_handler)( * @WLAN_WIFI_POS_TGT_IF_ID: wifi positioning (Target IF) * @WLAN_MLME_OBJ_DEL_ID: Object delete req/resp tracking with FW * @WLAN_ACTION_OUI_ID: action oui operations + * @FTM_TIME_SYNC_ID: ftm time sync operations + * @WLAN_PKT_CAPTURE_ID Packet capture operations * @WLAN_REF_ID_MAX: Max id used to generate ref count tracking array */ /* New value added to the enum must also be reflected in function @@ -273,6 +275,8 @@ typedef enum { WLAN_WIFI_POS_TGT_IF_ID = 41, WLAN_MLME_OBJ_DEL_ID = 42, WLAN_ACTION_OUI_ID = 43, + FTM_TIME_SYNC_ID = 44, + WLAN_PKT_CAPTURE_ID = 45, WLAN_REF_ID_MAX, } wlan_objmgr_ref_dbgid; diff --git a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/obj_mgr/src/wlan_objmgr_debug.c b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/obj_mgr/src/wlan_objmgr_debug.c index 705f0b5b3209..c7f5be1a5215 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/obj_mgr/src/wlan_objmgr_debug.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/obj_mgr/src/wlan_objmgr_debug.c @@ -34,7 +34,7 @@ * The max duration for which a obj can be allowed to remain in L-state * The duration should be higher than the psoc idle timeout. */ -#define LOG_DEL_OBJ_DESTROY_ASSERT_DURATION_SEC 15 +#define LOG_DEL_OBJ_DESTROY_ASSERT_DURATION_SEC 30 #define LOG_DEL_OBJ_LIST_MAX_COUNT (3 + 5 + 48 + 4096) /** diff --git a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/obj_mgr/src/wlan_objmgr_peer_obj.c b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/obj_mgr/src/wlan_objmgr_peer_obj.c index ab8a2ad05812..f882c1a8789c 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/obj_mgr/src/wlan_objmgr_peer_obj.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/obj_mgr/src/wlan_objmgr_peer_obj.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -254,8 +254,8 @@ struct wlan_objmgr_peer *wlan_objmgr_peer_obj_create( return NULL; } - obj_mgr_debug("Created peer " QDF_MAC_ADDR_STR, - QDF_MAC_ADDR_ARRAY(macaddr)); + obj_mgr_debug("Created peer " QDF_MAC_ADDR_STR " type %d", + QDF_MAC_ADDR_ARRAY(macaddr), type); return peer; } diff --git a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/inc/wlan_policy_mgr_api.h b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/inc/wlan_policy_mgr_api.h index de4b0661c33e..76dd3760434e 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/inc/wlan_policy_mgr_api.h +++ b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/inc/wlan_policy_mgr_api.h @@ -64,6 +64,53 @@ typedef const enum policy_mgr_conc_next_action ((channel_select_logic_conc & PM_FW_MODE_STA_P2P_BIT_MASK) >> \ PM_FW_MODE_STA_P2P_BIT_POS) +/** + * enum PM_AP_DFS_MASTER_MODE - AP dfs master mode + * @PM_STA_SAP_ON_DFS_DEFAULT - Disallow STA+SAP SCC on DFS channel + * @PM_STA_SAP_ON_DFS_MASTER_MODE_DISABLED - Allow STA+SAP SCC + * on DFS channel with master mode disabled + * @PM_STA_SAP_ON_DFS_MASTER_MODE_FLEX - enhance + * "PM_STA_SAP_ON_DFS_MASTER_MODE_DISABLED" with below requirement: + * a. Allow single SAP (GO) start on DFS channel. + * b. Allow CAC process on DFS channel in single SAP (GO) mode + * c. Allow DFS radar event process in single SAP (GO) mode + * d. Disallow CAC and radar event process in SAP (GO) + STA mode. + * + * This enum value will be used to set to INI g_sta_sap_scc_on_dfs_chan to + * config the sta+sap on dfs channel behaviour expected by user. + */ +enum PM_AP_DFS_MASTER_MODE { + PM_STA_SAP_ON_DFS_DEFAULT, + PM_STA_SAP_ON_DFS_MASTER_MODE_DISABLED, + PM_STA_SAP_ON_DFS_MASTER_MODE_FLEX, +}; + +/** + * policy_mgr_get_dfs_master_dynamic_enabled() - support dfs master or not + * on AP interafce when STA+SAP(GO) concurrency + * @psoc: pointer to psoc + * @vdev_id: sap vdev id + * + * This API is used to check AP dfs master functionality enabled or not when + * STA+SAP(GO) concurrency. + * If g_sta_sap_scc_on_dfs_chan is non-zero, the STA+SAP(GO) concurrency + * is allowed on DFS channel SCC and the SAP's DFS master functionality + * should be enable/disable according to: + * 1. g_sta_sap_scc_on_dfs_chan is 0: function return true - dfs master + * capability enabled. + * 2. g_sta_sap_scc_on_dfs_chan is 1: function return false - dfs master + * capability disabled. + * 3. g_sta_sap_scc_on_dfs_chan is 2: dfs master capability based on STA on + * 5G or not: + * a. 5G STA active - return false + * b. no 5G STA active -return true + * + * Return: true if dfs master functionality should be enabled. + */ +bool +policy_mgr_get_dfs_master_dynamic_enabled(struct wlan_objmgr_psoc *psoc, + uint8_t vdev_id); + /** * policy_mgr_set_concurrency_mode() - To set concurrency mode * @psoc: PSOC object data @@ -2420,6 +2467,17 @@ bool policy_mgr_is_sta_connected_2g(struct wlan_objmgr_psoc *psoc); void policy_mgr_trim_acs_channel_list(struct wlan_objmgr_psoc *psoc, uint8_t *org_ch_list, uint8_t *org_ch_list_count); +/** + * policy_mgr_scan_trim_5g_chnls_for_dfs_ap() - check if sta scan should skip + * 5g channel when dfs ap is present. + * + * @psoc: pointer to soc + * + * Return: true if sta scan 5g chan should be skipped + */ +bool policy_mgr_scan_trim_5g_chnls_for_dfs_ap(struct wlan_objmgr_psoc *psoc); + + /** * policy_mgr_is_hwmode_set_for_given_chnl() - to check for given channel * if the hw mode is properly set. @@ -2578,6 +2636,19 @@ void policy_mgr_update_user_config_sap_chan( bool policy_mgr_is_sap_restart_required_after_sta_disconnect( struct wlan_objmgr_psoc *psoc, uint8_t *intf_ch); +/** + * policy_mgr_dump_channel_list() - Print channel list + * @len: Length of pcl list + * @pcl_channels: pcl channels list + * @pcl_weight: pcl weight list + * + * + * Return: True or false + */ +bool policy_mgr_dump_channel_list(uint32_t len, + uint8_t *pcl_channels, + uint8_t *pcl_weight); + /** * policy_mgr_is_sta_sap_scc() - check whether SAP is doing SCC with * STA diff --git a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/inc/wlan_policy_mgr_public_struct.h b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/inc/wlan_policy_mgr_public_struct.h index c4080778ae75..8c3924ce5361 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/inc/wlan_policy_mgr_public_struct.h +++ b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/inc/wlan_policy_mgr_public_struct.h @@ -1017,7 +1017,7 @@ struct policy_mgr_user_cfg { bool enable2x2; uint32_t mcc_to_scc_switch_mode; bool sub_20_mhz_enabled; - bool is_sta_sap_scc_allowed_on_dfs_chan; + uint32_t is_sta_sap_scc_allowed_on_dfs_chan; uint32_t channel_select_logic_conc; uint32_t sta_sap_scc_on_lte_coex_chan; uint8_t enable_dfs_master_cap; diff --git a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/src/wlan_policy_mgr_action.c b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/src/wlan_policy_mgr_action.c index 4c5ba6b8725f..84be7987349b 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/src/wlan_policy_mgr_action.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/src/wlan_policy_mgr_action.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -193,7 +193,7 @@ enum policy_mgr_conc_next_action policy_mgr_need_opportunistic_upgrade( } if (policy_mgr_is_hw_dbs_capable(psoc) == false) { - policy_mgr_err("driver isn't dbs capable, no further action needed"); + policy_mgr_rl_debug("driver isn't dbs capable, no further action needed"); goto done; } @@ -513,7 +513,7 @@ QDF_STATUS policy_mgr_current_connections_update(struct wlan_objmgr_psoc *psoc, enum QDF_OPMODE new_conn_mode = QDF_MAX_NO_OF_MODE; if (policy_mgr_is_hw_dbs_capable(psoc) == false) { - policy_mgr_err("driver isn't dbs capable, no further action needed"); + policy_mgr_rl_debug("driver isn't dbs capable, no further action needed"); return QDF_STATUS_E_NOSUPPORT; } if (WLAN_REG_IS_24GHZ_CH(channel)) @@ -615,7 +615,7 @@ QDF_STATUS policy_mgr_next_actions(struct wlan_objmgr_psoc *psoc, struct dbs_nss nss_dbs = {0}; if (policy_mgr_is_hw_dbs_capable(psoc) == false) { - policy_mgr_err("driver isn't dbs capable, no further action needed"); + policy_mgr_rl_debug("driver isn't dbs capable, no further action needed"); return QDF_STATUS_E_NOSUPPORT; } @@ -836,10 +836,8 @@ bool policy_mgr_is_safe_channel(struct wlan_objmgr_psoc *psoc, } - if (pm_ctx->unsafe_channel_count == 0) { - policy_mgr_debug("There are no unsafe channels"); + if (pm_ctx->unsafe_channel_count == 0) return is_safe; - } for (j = 0; j < pm_ctx->unsafe_channel_count; j++) { if (channel == pm_ctx->unsafe_channel_list[j]) { @@ -924,8 +922,8 @@ static void __policy_mgr_check_sta_ap_concurrent_ch_intf(void *data) mcc_to_scc_switch = policy_mgr_mcc_to_scc_switch_mode_in_user_cfg(psoc); - policy_mgr_info("Concurrent open sessions running: %d", - policy_mgr_concurrent_open_sessions_running(psoc)); + policy_mgr_debug("Concurrent open sessions running: %d", + policy_mgr_concurrent_open_sessions_running(psoc)); if (!policy_mgr_is_restart_sap_allowed(psoc, mcc_to_scc_switch)) goto end; @@ -968,8 +966,9 @@ static void __policy_mgr_check_sta_ap_concurrent_ch_intf(void *data) (psoc, vdev_id[i], &channel, &sec_ch); if (status == QDF_STATUS_SUCCESS) { - policy_mgr_info("SAP restarts due to MCC->SCC switch, old chan :%d new chan: %d" - , operating_channel[i], channel); + policy_mgr_debug("SAP restarts due to MCC->SCC switch, old chan :%d new chan: %d", + operating_channel[i], + channel); break; } } @@ -1166,8 +1165,8 @@ void policy_mgr_check_concurrent_intf_and_restart_sap( mcc_to_scc_switch = policy_mgr_mcc_to_scc_switch_mode_in_user_cfg(psoc); - policy_mgr_info("MCC to SCC switch: %d chan: %d", - mcc_to_scc_switch, operating_channel[0]); + policy_mgr_debug("MCC to SCC switch: %d chan: %d", + mcc_to_scc_switch, operating_channel[0]); if (!policy_mgr_is_restart_sap_allowed(psoc, mcc_to_scc_switch)) { policy_mgr_debug( @@ -1199,8 +1198,7 @@ void policy_mgr_check_concurrent_intf_and_restart_sap( policy_mgr_check_sta_ap_concurrent_ch_intf, work_info); qdf_sched_work(0, &pm_ctx->sta_ap_intf_check_work); - policy_mgr_info( - "Checking for Concurrent Change interference"); + policy_mgr_debug("Checking for Concurrent Change interference"); } } } @@ -1430,7 +1428,7 @@ QDF_STATUS policy_mgr_set_hw_mode_on_channel_switch( enum policy_mgr_conc_next_action action; if (!policy_mgr_is_hw_dbs_capable(psoc)) { - policy_mgr_err("PM/DBS is disabled"); + policy_mgr_rl_debug("PM/DBS is disabled"); return status; } @@ -1598,21 +1596,21 @@ enum policy_mgr_hw_mode_change policy_mgr_get_hw_mode_change_from_hw_mode_index( policy_mgr_info("HW param: %x", param); param = pm_ctx->hw_mode.hw_mode_list[hw_mode_index]; if (POLICY_MGR_HW_MODE_DBS_MODE_GET(param)) { - policy_mgr_info("DBS is requested with HW (%d)", + policy_mgr_debug("DBS is requested with HW (%d)", hw_mode_index); value = POLICY_MGR_DBS_IN_PROGRESS; goto ret_value; } if (POLICY_MGR_HW_MODE_SBS_MODE_GET(param)) { - policy_mgr_info("SBS is requested with HW (%d)", + policy_mgr_debug("SBS is requested with HW (%d)", hw_mode_index); value = POLICY_MGR_SBS_IN_PROGRESS; goto ret_value; } value = POLICY_MGR_SMM_IN_PROGRESS; - policy_mgr_info("SMM is requested with HW (%d)", hw_mode_index); + policy_mgr_debug("SMM is requested with HW (%d)", hw_mode_index); ret_value: return value; diff --git a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/src/wlan_policy_mgr_core.c b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/src/wlan_policy_mgr_core.c index a7c0a818eb47..c2b74798b557 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/src/wlan_policy_mgr_core.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/src/wlan_policy_mgr_core.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -658,11 +658,12 @@ void policy_mgr_store_and_del_conn_info(struct wlan_objmgr_psoc *psoc, if (!found_index) { *num_cxn_del = 0; - policy_mgr_err("Mode:%d not available in the conn info", mode); + policy_mgr_debug("Mode:%d not available in the conn info", + mode); } else { *num_cxn_del = found_index; - policy_mgr_err("Mode:%d number of conn %d temp del", - mode, *num_cxn_del); + policy_mgr_debug("Mode:%d number of conn %d temp del", + mode, *num_cxn_del); } /* @@ -835,7 +836,7 @@ void policy_mgr_pdev_set_hw_mode_cb(uint32_t status, POLICY_MGR_HW_MODE_NOT_IN_PROGRESS); if (status != SET_HW_MODE_STATUS_OK) { - policy_mgr_err("Set HW mode failed with status %d", status); + policy_mgr_debug("Set HW mode failed with status %d", status); goto send_done_event; } @@ -1144,7 +1145,7 @@ void policy_mgr_dump_current_concurrency(struct wlan_objmgr_psoc *psoc) case 1: policy_mgr_dump_current_concurrency_one_connection(cc_mode, sizeof(cc_mode)); - policy_mgr_err("%s Standalone", cc_mode); + policy_mgr_debug("%s Standalone", cc_mode); break; case 2: count = policy_mgr_dump_current_concurrency_two_connection( @@ -1159,7 +1160,7 @@ void policy_mgr_dump_current_concurrency(struct wlan_objmgr_psoc *psoc) } else strlcat(cc_mode, " DBS", sizeof(cc_mode)); qdf_mutex_release(&pm_ctx->qdf_conc_list_lock); - policy_mgr_err("%s", cc_mode); + policy_mgr_debug("%s", cc_mode); break; case 3: count = policy_mgr_dump_current_concurrency_three_connection( @@ -1184,10 +1185,10 @@ void policy_mgr_dump_current_concurrency(struct wlan_objmgr_psoc *psoc) policy_mgr_dump_dbs_concurrency(psoc, cc_mode, sizeof(cc_mode)); } - policy_mgr_err("%s", cc_mode); + policy_mgr_debug("%s", cc_mode); break; default: - policy_mgr_err("unexpected num_connections value %d", + policy_mgr_debug("unexpected num_connections value %d", num_connections); break; } @@ -1789,11 +1790,11 @@ void policy_mgr_set_weight_of_dfs_passive_channels_to_zero( (channel_state == CHANNEL_STATE_INVALID)) /* Set weight of inactive channels to 0 */ weight_list[i] = 0; - - policy_mgr_debug("chan[%d] - %d, weight[%d] - %d", - i, pcl_channels[i], i, weight_list[i]); } + policy_mgr_dump_channel_list(orig_channel_count, + pcl_channels, weight_list); + return; } @@ -1868,7 +1869,6 @@ QDF_STATUS policy_mgr_get_channel_list(struct wlan_objmgr_psoc *psoc, */ sta_sap_scc_on_dfs_chan = policy_mgr_is_sta_sap_scc_allowed_on_dfs_chan(psoc); - policy_mgr_debug("sta_sap_scc_on_dfs_chan %u", sta_sap_scc_on_dfs_chan); if ((mode == PM_SAP_MODE) || (mode == PM_P2P_GO_MODE)) { if ((policy_mgr_mode_specific_connection_count(psoc, PM_STA_MODE, @@ -2350,7 +2350,7 @@ bool policy_mgr_allow_new_home_channel(struct wlan_objmgr_psoc *psoc, wlan_reg_is_dfs_ch(pm_ctx->pdev, pm_conc_connection_list[1].chan))) { - policy_mgr_err("Existing DFS connection, new 3-port DFS connection is not allowed"); + policy_mgr_rl_debug("Existing DFS connection, new 3-port DFS connection is not allowed"); status = false; } else if (((pm_conc_connection_list[0].chan != @@ -2364,7 +2364,7 @@ bool policy_mgr_allow_new_home_channel(struct wlan_objmgr_psoc *psoc, pm_conc_connection_list[0].chan) && (channel != pm_conc_connection_list[1].chan)) { - policy_mgr_err("don't allow 3rd home channel on same MAC"); + policy_mgr_rl_debug("don't allow 3rd home channel on same MAC"); status = false; } } else if (((WLAN_REG_IS_24GHZ_CH(channel)) && @@ -2377,7 +2377,7 @@ bool policy_mgr_allow_new_home_channel(struct wlan_objmgr_psoc *psoc, (pm_conc_connection_list[0].chan)) && (WLAN_REG_IS_5GHZ_CH (pm_conc_connection_list[1].chan)))) { - policy_mgr_err("don't allow 3rd home channel on same MAC"); + policy_mgr_rl_debug("don't allow 3rd home channel on same MAC"); status = false; } } @@ -2388,7 +2388,7 @@ bool policy_mgr_allow_new_home_channel(struct wlan_objmgr_psoc *psoc, && wlan_reg_is_dfs_ch(pm_ctx->pdev, pm_conc_connection_list[0].chan)) { - policy_mgr_err("Existing DFS connection, new 2-port DFS connection is not allowed"); + policy_mgr_rl_debug("Existing DFS connection, new 2-port DFS connection is not allowed"); status = false; } qdf_mutex_release(&pm_ctx->qdf_conc_list_lock); @@ -2432,7 +2432,7 @@ bool policy_mgr_is_5g_channel_allowed(struct wlan_objmgr_psoc *psoc, WLAN_REG_IS_5GHZ_CH(channel) && (channel != pm_conc_connection_list[list[index]].chan)) { qdf_mutex_release(&pm_ctx->qdf_conc_list_lock); - policy_mgr_err("don't allow MCC if SAP/GO on DFS channel"); + policy_mgr_rl_debug("don't allow MCC if SAP/GO on DFS channel"); return false; } index++; @@ -2600,7 +2600,7 @@ QDF_STATUS policy_mgr_complete_action(struct wlan_objmgr_psoc *psoc, QDF_STATUS status = QDF_STATUS_E_FAILURE; if (policy_mgr_is_hw_dbs_capable(psoc) == false) { - policy_mgr_err("driver isn't dbs capable, no further action needed"); + policy_mgr_rl_debug("driver isn't dbs capable, no further action needed"); return QDF_STATUS_E_NOSUPPORT; } diff --git a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/src/wlan_policy_mgr_get_set_utils.c b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/src/wlan_policy_mgr_get_set_utils.c index a8984aa3f0c5..d50a712b8ad0 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/src/wlan_policy_mgr_get_set_utils.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/src/wlan_policy_mgr_get_set_utils.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -33,6 +33,7 @@ #include "wlan_objmgr_pdev_obj.h" #include "wlan_objmgr_vdev_obj.h" #include "wlan_reg_services_api.h" +#include "nan_ucfg_api.h" /* invalid channel id. */ #define INVALID_CHANNEL_ID 0 @@ -529,8 +530,6 @@ bool policy_mgr_find_if_fw_supports_dbs(struct wlan_objmgr_psoc *psoc) dbs_support = wmi_service_enabled(wmi_handle, wmi_service_dual_band_simultaneous_support); - policy_mgr_debug("is DBS supported by FW/HW: %s", - dbs_support ? "yes" : "no"); /* The agreement with FW is that: To know if the target is DBS * capable, DBS needs to be supported both in the HW mode list @@ -555,9 +554,7 @@ static bool policy_mgr_find_if_hwlist_has_dbs(struct wlan_objmgr_psoc *psoc) } for (i = 0; i < pm_ctx->num_dbs_hw_modes; i++) { param = pm_ctx->hw_mode.hw_mode_list[i]; - policy_mgr_debug("HW param: %x", param); if (POLICY_MGR_HW_MODE_DBS_MODE_GET(param)) { - policy_mgr_debug("HW (%d) is DBS capable", i); found = 1; break; } @@ -581,9 +578,7 @@ static bool policy_mgr_find_if_hwlist_has_sbs(struct wlan_objmgr_psoc *psoc) } for (i = 0; i < pm_ctx->num_dbs_hw_modes; i++) { param = pm_ctx->hw_mode.hw_mode_list[i]; - policy_mgr_debug("HW param: %x", param); if (POLICY_MGR_HW_MODE_SBS_MODE_GET(param)) { - policy_mgr_debug("HW (%d) is SBS capable", i); found = 1; break; } @@ -596,27 +591,31 @@ static bool policy_mgr_find_if_hwlist_has_sbs(struct wlan_objmgr_psoc *psoc) bool policy_mgr_is_hw_dbs_capable(struct wlan_objmgr_psoc *psoc) { - if (!policy_mgr_is_dbs_enable(psoc)) { - policy_mgr_debug("DBS is disabled"); + if (!policy_mgr_is_dbs_enable(psoc)) + return false; + + if (!policy_mgr_find_if_fw_supports_dbs(psoc)) return false; - } - if (!policy_mgr_find_if_fw_supports_dbs(psoc)) { - policy_mgr_debug("HW mode list has no DBS"); + if (!policy_mgr_find_if_hwlist_has_dbs(psoc)) { + policymgr_nofl_debug("HW mode list has no DBS"); return false; } - return policy_mgr_find_if_hwlist_has_dbs(psoc); + return true; } bool policy_mgr_is_hw_sbs_capable(struct wlan_objmgr_psoc *psoc) { - if (!policy_mgr_find_if_fw_supports_dbs(psoc)) { - policy_mgr_debug("HW mode list has no DBS"); + if (!policy_mgr_find_if_fw_supports_dbs(psoc)) + return false; + + if (!policy_mgr_find_if_hwlist_has_sbs(psoc)) { + policymgr_nofl_debug("HW mode list has no SBS"); return false; } - return policy_mgr_find_if_hwlist_has_sbs(psoc); + return true; } QDF_STATUS policy_mgr_get_dbs_hw_modes(struct wlan_objmgr_psoc *psoc, @@ -632,7 +631,7 @@ QDF_STATUS policy_mgr_get_dbs_hw_modes(struct wlan_objmgr_psoc *psoc, *two_by_two_dbs = false; if (policy_mgr_is_hw_dbs_capable(psoc) == false) { - policy_mgr_err("HW is not DBS capable"); + policy_mgr_rl_debug("HW is not DBS capable"); /* Caller will understand that DBS is disabled */ return QDF_STATUS_SUCCESS; @@ -710,8 +709,6 @@ QDF_STATUS policy_mgr_get_current_hw_mode(struct wlan_objmgr_psoc *psoc, QDF_STATUS status; uint32_t old_hw_index = 0, new_hw_index = 0; - policy_mgr_debug("Get the current hw mode"); - status = policy_mgr_get_old_and_new_hw_index(psoc, &old_hw_index, &new_hw_index); if (QDF_STATUS_SUCCESS != status) { @@ -751,7 +748,7 @@ bool policy_mgr_is_dbs_enable(struct wlan_objmgr_psoc *psoc) struct policy_mgr_psoc_priv_obj *pm_ctx; if (policy_mgr_is_dual_mac_disabled_in_ini(psoc)) { - policy_mgr_debug("DBS is disabled from ini"); + policy_mgr_rl_debug("DBS is disabled from ini"); return false; } @@ -761,10 +758,6 @@ bool policy_mgr_is_dbs_enable(struct wlan_objmgr_psoc *psoc) return false; } - policy_mgr_debug("DBS=%d", - WMI_DBS_FW_MODE_CFG_DBS_GET( - pm_ctx->dual_mac_cfg.cur_fw_mode_config)); - if (WMI_DBS_FW_MODE_CFG_DBS_GET( pm_ctx->dual_mac_cfg.cur_fw_mode_config)) return true; @@ -1024,8 +1017,8 @@ bool policy_mgr_current_concurrency_is_mcc(struct wlan_objmgr_psoc *psoc) } break; default: - policy_mgr_err("unexpected num_connections value %d", - num_connections); + policy_mgr_debug("unexpected num_connections value %d", + num_connections); break; } @@ -1066,9 +1059,9 @@ void policy_mgr_set_concurrency_mode(struct wlan_objmgr_psoc *psoc, break; } - policy_mgr_info("concurrency_mode = 0x%x Number of open sessions for mode %d = %d", - pm_ctx->concurrency_mode, mode, - pm_ctx->no_of_open_sessions[mode]); + policy_mgr_debug("concurrency_mode = 0x%x Number of open sessions for mode %d = %d", + pm_ctx->concurrency_mode, mode, + pm_ctx->no_of_open_sessions[mode]); } /** @@ -1105,7 +1098,7 @@ void policy_mgr_clear_concurrency_mode(struct wlan_objmgr_psoc *psoc, break; } - policy_mgr_info("concurrency_mode = 0x%x Number of open sessions for mode %d = %d", + policy_mgr_debug("concurrency_mode = 0x%x Number of open sessions for mode %d = %d", pm_ctx->concurrency_mode, mode, pm_ctx->no_of_open_sessions[mode]); } @@ -1231,12 +1224,23 @@ QDF_STATUS policy_mgr_decr_active_session(struct wlan_objmgr_psoc *psoc, if (pm_ctx->tdls_cbacks.tdls_notify_decrement_session) pm_ctx->tdls_cbacks.tdls_notify_decrement_session(psoc); /* Enable LRO/GRO if there no concurrency */ - if ((policy_mgr_mode_specific_connection_count(psoc, PM_STA_MODE, NULL) == 1) && - (policy_mgr_mode_specific_connection_count(psoc, PM_SAP_MODE, NULL) == 0) && - (policy_mgr_mode_specific_connection_count(psoc, PM_P2P_CLIENT_MODE, NULL) == - 0) && - (policy_mgr_mode_specific_connection_count(psoc, PM_P2P_GO_MODE, NULL) == 0) && - (policy_mgr_mode_specific_connection_count(psoc, PM_IBSS_MODE, NULL) == 0)) { + if ((policy_mgr_get_connection_count(psoc) == 0) || + ((policy_mgr_mode_specific_connection_count(psoc, + PM_STA_MODE, + NULL) == 1) && + (policy_mgr_mode_specific_connection_count(psoc, + PM_SAP_MODE, + NULL) == 0) && + (policy_mgr_mode_specific_connection_count(psoc, + PM_P2P_CLIENT_MODE, + NULL) == 0) && + (policy_mgr_mode_specific_connection_count(psoc, + PM_P2P_GO_MODE, + NULL) == 0) && + (policy_mgr_mode_specific_connection_count(psoc, + PM_IBSS_MODE, + NULL) == 0) && + !(wlan_nan_is_ndp_peer_active(pm_ctx->pdev)))) { if (pm_ctx->dp_cbacks.hdd_disable_rx_ol_in_concurrency != NULL) pm_ctx->dp_cbacks.hdd_disable_rx_ol_in_concurrency(false); }; @@ -1486,9 +1490,7 @@ uint32_t policy_mgr_get_mode_specific_conn_info(struct wlan_objmgr_psoc *psoc, count = policy_mgr_mode_specific_connection_count( psoc, mode, list); qdf_mutex_acquire(&pm_ctx->qdf_conc_list_lock); - if (count == 0) { - policy_mgr_debug("No mode:[%d] connection", mode); - } else if (count == 1) { + if (count == 1) { *channel = pm_conc_connection_list[list[index]].chan; *vdev_id = pm_conc_connection_list[list[index]].vdev_id; @@ -1500,7 +1502,6 @@ uint32_t policy_mgr_get_mode_specific_conn_info(struct wlan_objmgr_psoc *psoc, vdev_id[index] = pm_conc_connection_list[list[index]].vdev_id; } - policy_mgr_debug("Multiple mode:[%d] connections", mode); } qdf_mutex_release(&pm_ctx->qdf_conc_list_lock); @@ -1582,14 +1583,14 @@ bool policy_mgr_is_concurrency_allowed(struct wlan_objmgr_psoc *psoc, num_connections = policy_mgr_get_connection_count(psoc); if (num_connections && policy_mgr_is_sub_20_mhz_enabled(psoc)) { - policy_mgr_err("dont allow concurrency if Sub 20 MHz is enabled"); + policy_mgr_rl_debug("dont allow concurrency if Sub 20 MHz is enabled"); status = false; goto done; } if (policy_mgr_max_concurrent_connections_reached(psoc)) { - policy_mgr_err("Reached max concurrent connections: %d", - pm_ctx->user_cfg.max_concurrent_active_sessions); + policy_mgr_rl_debug("Reached max concurrent connections: %d", + pm_ctx->user_cfg.max_concurrent_active_sessions); goto done; } @@ -1618,8 +1619,6 @@ bool policy_mgr_is_concurrency_allowed(struct wlan_objmgr_psoc *psoc, sta_sap_scc_on_dfs_chan = policy_mgr_is_sta_sap_scc_allowed_on_dfs_chan(psoc); - policy_mgr_debug("sta_sap_scc_on_dfs_chan %u", - sta_sap_scc_on_dfs_chan); if (!sta_sap_scc_on_dfs_chan && ((mode == PM_P2P_GO_MODE) || (mode == PM_SAP_MODE))) { @@ -1627,7 +1626,7 @@ bool policy_mgr_is_concurrency_allowed(struct wlan_objmgr_psoc *psoc, match = policy_mgr_disallow_mcc(psoc, channel); } if (true == match) { - policy_mgr_err("No MCC, SAP/GO about to come up on DFS channel"); + policy_mgr_rl_debug("No MCC, SAP/GO about to come up on DFS channel"); goto done; } } @@ -1637,7 +1636,7 @@ bool policy_mgr_is_concurrency_allowed(struct wlan_objmgr_psoc *psoc, list); if (mode == PM_STA_MODE && count) { if (count >= 2) { - policy_mgr_err("3rd STA isn't permitted"); + policy_mgr_rl_debug("3rd STA isn't permitted"); goto done; } chan = pm_conc_connection_list[list[0]].chan; @@ -1655,23 +1654,23 @@ bool policy_mgr_is_concurrency_allowed(struct wlan_objmgr_psoc *psoc, if ((PM_IBSS_MODE == mode) && (policy_mgr_mode_specific_connection_count(psoc, PM_IBSS_MODE, list)) && count) { - policy_mgr_err("No 2nd IBSS, we already have STA + IBSS"); + policy_mgr_rl_debug("No 2nd IBSS, we already have STA + IBSS"); goto done; } if ((PM_IBSS_MODE == mode) && (wlan_reg_is_dfs_ch(pm_ctx->pdev, channel)) && count) { - policy_mgr_err("No IBSS + STA SCC/MCC, IBSS is on DFS channel"); + policy_mgr_rl_debug("No IBSS + STA SCC/MCC, IBSS is on DFS channel"); goto done; } if (PM_IBSS_MODE == mode) { if (policy_mgr_is_hw_dbs_capable(psoc) == true) { if (num_connections > 1) { - policy_mgr_err("No IBSS, we have concurrent connections already"); + policy_mgr_rl_debug("No IBSS, we have concurrent connections already"); goto done; } qdf_mutex_acquire(&pm_ctx->qdf_conc_list_lock); if (PM_STA_MODE != pm_conc_connection_list[0].mode) { - policy_mgr_err("No IBSS, we've a non-STA connection"); + policy_mgr_rl_debug("No IBSS, we've a non-STA connection"); qdf_mutex_release(&pm_ctx->qdf_conc_list_lock); goto done; } @@ -1685,12 +1684,12 @@ bool policy_mgr_is_concurrency_allowed(struct wlan_objmgr_psoc *psoc, WLAN_REG_IS_SAME_BAND_CHANNELS( pm_conc_connection_list[0].chan, channel)) { qdf_mutex_release(&pm_ctx->qdf_conc_list_lock); - policy_mgr_err("No IBSS + STA MCC"); + policy_mgr_rl_debug("No IBSS + STA MCC"); goto done; } qdf_mutex_release(&pm_ctx->qdf_conc_list_lock); } else if (num_connections) { - policy_mgr_err("No IBSS, we have one connection already"); + policy_mgr_rl_debug("No IBSS, we have one connection already"); goto done; } } @@ -1698,7 +1697,7 @@ bool policy_mgr_is_concurrency_allowed(struct wlan_objmgr_psoc *psoc, if ((PM_STA_MODE == mode) && (policy_mgr_mode_specific_connection_count(psoc, PM_IBSS_MODE, list)) && count) { - policy_mgr_err("No 2nd STA, we already have STA + IBSS"); + policy_mgr_rl_debug("No 2nd STA, we already have STA + IBSS"); goto done; } @@ -1707,7 +1706,7 @@ bool policy_mgr_is_concurrency_allowed(struct wlan_objmgr_psoc *psoc, PM_IBSS_MODE, list))) { if (policy_mgr_is_hw_dbs_capable(psoc) == true) { if (num_connections > 1) { - policy_mgr_err("No 2nd STA, we already have IBSS concurrency"); + policy_mgr_rl_debug("No 2nd STA, we already have IBSS concurrency"); goto done; } qdf_mutex_acquire(&pm_ctx->qdf_conc_list_lock); @@ -1716,7 +1715,7 @@ bool policy_mgr_is_concurrency_allowed(struct wlan_objmgr_psoc *psoc, pm_conc_connection_list[0].chan)) && (WLAN_REG_IS_5GHZ_CH(channel))) { qdf_mutex_release(&pm_ctx->qdf_conc_list_lock); - policy_mgr_err("No IBSS + STA SCC/MCC, IBSS is on DFS channel"); + policy_mgr_rl_debug("No IBSS + STA SCC/MCC, IBSS is on DFS channel"); goto done; } /* @@ -1733,14 +1732,14 @@ bool policy_mgr_is_concurrency_allowed(struct wlan_objmgr_psoc *psoc, } qdf_mutex_release(&pm_ctx->qdf_conc_list_lock); } else { - policy_mgr_err("No STA, we have IBSS connection already"); + policy_mgr_rl_debug("No STA, we have IBSS connection already"); goto done; } } if (!policy_mgr_allow_sap_go_concurrency(psoc, mode, channel, WLAN_INVALID_VDEV_ID)) { - policy_mgr_err("This concurrency combination is not allowed"); + policy_mgr_rl_debug("This concurrency combination is not allowed"); goto done; } @@ -1753,7 +1752,7 @@ bool policy_mgr_is_concurrency_allowed(struct wlan_objmgr_psoc *psoc, while (index < count) { if (WLAN_REG_IS_SAME_BAND_CHANNELS(channel, pm_conc_connection_list[list[index]].chan)) { - policy_mgr_err("Don't allow P2P GO on same band"); + policy_mgr_rl_debug("Don't allow P2P GO on same band"); qdf_mutex_release(&pm_ctx->qdf_conc_list_lock); goto done; } @@ -1763,7 +1762,7 @@ bool policy_mgr_is_concurrency_allowed(struct wlan_objmgr_psoc *psoc, } if (!policy_mgr_check_privacy_for_new_conn(pm_ctx)) { - policy_mgr_err("Don't allow new conn when wapi security conn existing"); + policy_mgr_rl_debug("Don't allow new conn when wapi security conn existing"); goto done; } @@ -1851,7 +1850,7 @@ uint32_t policy_mgr_get_concurrency_mode(struct wlan_objmgr_psoc *psoc) return QDF_STA_MASK; } - policy_mgr_info("concurrency_mode: 0x%x", + policy_mgr_debug("concurrency_mode: 0x%x", pm_ctx->concurrency_mode); return pm_ctx->concurrency_mode; @@ -2121,7 +2120,7 @@ QDF_STATUS policy_mgr_change_mcc_go_beacon_interval( return QDF_STATUS_E_FAILURE; } - policy_mgr_info("UPDATE Beacon Params"); + policy_mgr_debug("UPDATE Beacon Params"); if (QDF_SAP_MODE == dev_mode) { if (pm_ctx->sme_cbacks.sme_change_mcc_beacon_interval @@ -2666,8 +2665,8 @@ bool policy_mgr_is_dnsc_set(struct wlan_objmgr_vdev *vdev) roffchan = wlan_vdev_mlme_cap_get(vdev, WLAN_VDEV_C_RESTRICT_OFFCHAN); - policy_mgr_debug("Restrict offchannel:%s", - roffchan ? "set" : "clear"); + if (roffchan) + policy_mgr_debug("Restrict offchannel is set"); return roffchan; } @@ -2689,13 +2688,10 @@ QDF_STATUS policy_mgr_is_chan_ok_for_dnbs(struct wlan_objmgr_psoc *psoc, &operating_channel[cc_count], &vdev_id[cc_count], PM_SAP_MODE); - policy_mgr_debug("Number of SAP modes: %d", cc_count); cc_count = cc_count + policy_mgr_get_mode_specific_conn_info(psoc, &operating_channel[cc_count], &vdev_id[cc_count], PM_P2P_GO_MODE); - policy_mgr_debug("Number of beaconing entities (SAP + GO):%d", - cc_count); if (!cc_count) { *ok = true; return QDF_STATUS_SUCCESS; @@ -2755,7 +2751,6 @@ QDF_STATUS policy_mgr_is_chan_ok_for_dnbs(struct wlan_objmgr_psoc *psoc, } wlan_objmgr_vdev_release_ref(vdev, WLAN_POLICY_MGR_ID); } - policy_mgr_debug("chan: %d ok %d", channel, *ok); return QDF_STATUS_SUCCESS; } @@ -2952,6 +2947,95 @@ bool policy_mgr_is_sta_sap_scc_allowed_on_dfs_chan( return status; } +bool +policy_mgr_get_dfs_master_dynamic_enabled( + struct wlan_objmgr_psoc *psoc, uint8_t vdev_id) +{ + struct policy_mgr_psoc_priv_obj *pm_ctx; + bool sta_on_5g = false; + bool sta_on_2g = false; + uint32_t i; + bool enable; + + pm_ctx = policy_mgr_get_context(psoc); + if (!pm_ctx) { + policy_mgr_err("pm_ctx is NULL"); + return true; + } + + if (!pm_ctx->user_cfg.is_sta_sap_scc_allowed_on_dfs_chan) + return true; + if (pm_ctx->user_cfg.is_sta_sap_scc_allowed_on_dfs_chan == + PM_STA_SAP_ON_DFS_MASTER_MODE_DISABLED) + return false; + if (pm_ctx->user_cfg.is_sta_sap_scc_allowed_on_dfs_chan != + PM_STA_SAP_ON_DFS_MASTER_MODE_FLEX) { + policy_mgr_debug("sta_sap_scc_on_dfs_chnl %d unknown", + pm_ctx->user_cfg.is_sta_sap_scc_allowed_on_dfs_chan); + return true; + } + + qdf_mutex_acquire(&pm_ctx->qdf_conc_list_lock); + for (i = 0; i < MAX_NUMBER_OF_CONC_CONNECTIONS; i++) { + if (!((pm_conc_connection_list[i].vdev_id != vdev_id) && + pm_conc_connection_list[i].in_use && + (pm_conc_connection_list[i].mode == PM_STA_MODE || + pm_conc_connection_list[i].mode == PM_P2P_CLIENT_MODE))) + continue; + if (WLAN_REG_IS_5GHZ_CH(pm_conc_connection_list[i].chan)) + sta_on_5g = true; + else + sta_on_2g = true; + } + qdf_mutex_release(&pm_ctx->qdf_conc_list_lock); + + if (policy_mgr_is_hw_dbs_capable(psoc) && !sta_on_5g) + enable = true; + else if (!sta_on_5g && !sta_on_2g) + enable = true; + else + enable = false; + policy_mgr_debug("sta_sap_scc_on_dfs_chnl %d sta_on_2g %d sta_on_5g %d enable %d", + pm_ctx->user_cfg.is_sta_sap_scc_allowed_on_dfs_chan, sta_on_2g, + sta_on_5g, enable); + + return enable; +} + +bool policy_mgr_scan_trim_5g_chnls_for_dfs_ap(struct wlan_objmgr_psoc *psoc) +{ + struct policy_mgr_psoc_priv_obj *pm_ctx; + uint8_t ap_dfs_channel = 0; + + pm_ctx = policy_mgr_get_context(psoc); + if (!pm_ctx) { + policy_mgr_err("Invalid Context"); + return false; + } + + policy_mgr_is_any_dfs_beaconing_session_present( + psoc, &ap_dfs_channel); + if (!ap_dfs_channel) + return false; + /* + * 1) if agile & DFS scans are supportet + * 2) if hardware is DBS capable + * 3) if current hw mode is non-dbs + * if all above 3 conditions are true then don't skip any + * channel from scan list + */ + if (policy_mgr_is_hw_dbs_capable(psoc) && + !policy_mgr_is_current_hwmode_dbs(psoc) && + policy_mgr_get_dbs_plus_agile_scan_config(psoc) && + policy_mgr_get_single_mac_scan_with_dfs_config(psoc)) + return false; + + policy_mgr_debug("scan skip 5g chan due to dfs ap(ch %d) present", + ap_dfs_channel); + + return true; +} + bool policy_mgr_is_sta_connected_2g(struct wlan_objmgr_psoc *psoc) { struct policy_mgr_psoc_priv_obj *pm_ctx; @@ -3153,12 +3237,6 @@ bool policy_mgr_allow_multiple_sta_connections(struct wlan_objmgr_psoc *psoc, wmi_service_sta_plus_sta_support)) return false; - if (second_sta_chan && second_sta_chan != first_sta_chan && - WLAN_REG_IS_SAME_BAND_CHANNELS(second_sta_chan, first_sta_chan)) { - policy_mgr_err("STA+STA MCC isn't permitted"); - return false; - } - return true; } diff --git a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/src/wlan_policy_mgr_i.h b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/src/wlan_policy_mgr_i.h index 90e9c994ccda..faaa796125ad 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/src/wlan_policy_mgr_i.h +++ b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/src/wlan_policy_mgr_i.h @@ -153,6 +153,20 @@ #define policy_mgr_debug(format, args...) \ policy_mgr_logfl(QDF_TRACE_LEVEL_DEBUG, format, ## args) +#define policymgr_nofl_alert(params...) \ + QDF_TRACE_FATAL_NO_FL(QDF_MODULE_ID_POLICY_MGR, params) +#define policymgr_nofl_err(params...) \ + QDF_TRACE_ERROR_NO_FL(QDF_MODULE_ID_POLICY_MGR, params) +#define policymgr_nofl_warn(params...) \ + QDF_TRACE_WARN_NO_FL(QDF_MODULE_ID_POLICY_MGR, params) +#define policymgr_nofl_info(params...) \ + QDF_TRACE_INFO_NO_FL(QDF_MODULE_ID_POLICY_MGR, params) +#define policymgr_nofl_debug(params...) \ + QDF_TRACE_DEBUG_NO_FL(QDF_MODULE_ID_POLICY_MGR, params) + +#define policy_mgr_rl_debug(params...) \ + QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_POLICY_MGR, params) + #define PM_CONC_CONNECTION_LIST_VALID_INDEX(index) \ ((MAX_NUMBER_OF_CONC_CONNECTIONS > index) && \ (pm_conc_connection_list[index].in_use)) diff --git a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/src/wlan_policy_mgr_init_deinit.c b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/src/wlan_policy_mgr_init_deinit.c index 322de079032d..4090646035c8 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/src/wlan_policy_mgr_init_deinit.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/src/wlan_policy_mgr_init_deinit.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -352,7 +352,7 @@ QDF_STATUS policy_mgr_psoc_close(struct wlan_objmgr_psoc *psoc) if (pm_ctx->hw_mode.hw_mode_list) { qdf_mem_free(pm_ctx->hw_mode.hw_mode_list); pm_ctx->hw_mode.hw_mode_list = NULL; - policy_mgr_info("HW list is freed"); + policy_mgr_debug("HW list is freed"); } if (pm_ctx->sta_ap_intf_check_work_info) { diff --git a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/src/wlan_policy_mgr_pcl.c b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/src/wlan_policy_mgr_pcl.c index 8927314d581a..4444f7a0df66 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/src/wlan_policy_mgr_pcl.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/src/wlan_policy_mgr_pcl.c @@ -506,7 +506,10 @@ static QDF_STATUS policy_mgr_pcl_modification_for_sap( uint32_t *len) { QDF_STATUS status = QDF_STATUS_E_FAILURE; - uint32_t i; + bool mandatory_modified_pcl = false; + bool nol_modified_pcl = false; + bool dfs_modified_pcl = false; + bool modified_final_pcl = false; if (policy_mgr_is_sap_mandatory_channel_set(psoc)) { status = policy_mgr_modify_sap_pcl_based_on_mandatory_channel( @@ -516,10 +519,7 @@ static QDF_STATUS policy_mgr_pcl_modification_for_sap( "failed to get mandatory modified pcl for SAP"); return status; } - policy_mgr_debug("mandatory modified pcl len:%d", *len); - for (i = 0; i < *len; i++) - policy_mgr_debug("chan:%d weight:%d", - pcl_channels[i], pcl_weight[i]); + mandatory_modified_pcl = true; } status = policy_mgr_modify_sap_pcl_based_on_nol( @@ -528,10 +528,7 @@ static QDF_STATUS policy_mgr_pcl_modification_for_sap( policy_mgr_err("failed to get nol modified pcl for SAP"); return status; } - policy_mgr_debug("nol modified pcl len:%d", *len); - for (i = 0; i < *len; i++) - policy_mgr_debug("chan:%d weight:%d", - pcl_channels[i], pcl_weight[i]); + nol_modified_pcl = true; status = policy_mgr_modify_sap_pcl_based_on_dfs( psoc, pcl_channels, pcl_weight, len); @@ -539,10 +536,7 @@ static QDF_STATUS policy_mgr_pcl_modification_for_sap( policy_mgr_err("failed to get dfs modified pcl for SAP"); return status; } - policy_mgr_debug("dfs modified pcl len:%d", *len); - for (i = 0; i < *len; i++) - policy_mgr_debug("chan:%d weight:%d", - pcl_channels[i], pcl_weight[i]); + dfs_modified_pcl = true; status = policy_mgr_modify_pcl_based_on_srd (psoc, pcl_channels, pcl_weight, len); @@ -550,10 +544,13 @@ static QDF_STATUS policy_mgr_pcl_modification_for_sap( policy_mgr_err("failed to get srd modified pcl for SAP"); return status; } - policy_mgr_debug("modified final pcl len:%d", *len); - for (i = 0; i < *len; i++) - policy_mgr_debug("chan:%d weight:%d", - pcl_channels[i], pcl_weight[i]); + modified_final_pcl = true; + + policy_mgr_debug(" %d %d %d %d", + mandatory_modified_pcl, + nol_modified_pcl, + dfs_modified_pcl, + modified_final_pcl); return QDF_STATUS_SUCCESS; } @@ -565,7 +562,6 @@ static QDF_STATUS policy_mgr_pcl_modification_for_p2p_go( { QDF_STATUS status = QDF_STATUS_E_FAILURE; struct policy_mgr_psoc_priv_obj *pm_ctx; - uint32_t i; pm_ctx = policy_mgr_get_context(psoc); if (!pm_ctx) { @@ -585,10 +581,8 @@ static QDF_STATUS policy_mgr_pcl_modification_for_p2p_go( policy_mgr_err("failed to get modified pcl for SAP"); return status; } - policy_mgr_debug("modified pcl len:%d", *len); - for (i = 0; i < *len; i++) - policy_mgr_debug("chan:%d weight:%d", - pcl_channels[i], pcl_weight[i]); + + policy_mgr_dump_channel_list(*len, pcl_channels, pcl_weight); return QDF_STATUS_SUCCESS; } @@ -628,10 +622,9 @@ QDF_STATUS policy_mgr_get_pcl(struct wlan_objmgr_psoc *psoc, uint8_t *pcl_weight, uint32_t weight_len) { QDF_STATUS status = QDF_STATUS_E_FAILURE; - uint32_t num_connections = 0, i; + uint32_t num_connections = 0; enum policy_mgr_conc_priority_mode first_index = 0; enum policy_mgr_one_connection_mode second_index = 0; - enum policy_mgr_two_connection_mode third_index = 0; enum policy_mgr_pcl_type pcl = PM_NONE; enum policy_mgr_conc_priority_mode conc_system_pref = 0; struct policy_mgr_psoc_priv_obj *pm_ctx; @@ -696,47 +689,45 @@ QDF_STATUS policy_mgr_get_pcl(struct wlan_objmgr_psoc *psoc, } break; - case 2: - third_index = - policy_mgr_get_third_connection_pcl_table_index(psoc); - if (PM_MAX_TWO_CONNECTION_MODE == third_index) { - policy_mgr_err( - "couldn't find index for 3rd connection pcl table"); - return status; - } - if (policy_mgr_is_hw_dbs_capable(psoc) == true) { - pcl = (*third_connection_pcl_dbs_table) - [third_index][mode][conc_system_pref]; - } else { - pcl = third_connection_pcl_nodbs_table - [third_index][mode][conc_system_pref]; - } - break; +/* + * Disable 3 connection as they are not PORed, take out this code out + * from comments if needed in future. + * case 2: + * third_index = + * policy_mgr_get_third_connection_pcl_table_index(psoc); + * if (PM_MAX_TWO_CONNECTION_MODE == third_index) { + * policy_mgr_err( + * "couldn't find index for 3rd connection pcl table"); + * return status; + * } + * if (policy_mgr_is_hw_dbs_capable(psoc) == true) { + * pcl = (*third_connection_pcl_dbs_table) + * [third_index][mode][conc_system_pref]; + * } else { + * pcl = third_connection_pcl_nodbs_table + * [third_index][mode][conc_system_pref]; + * } + * break; +*/ default: policy_mgr_err("unexpected num_connections value %d", num_connections); + pcl = PM_MAX_PCL_TYPE; break; } - policy_mgr_debug("index1:%d index2:%d index3:%d pcl:%d dbs:%d", - first_index, second_index, third_index, - pcl, policy_mgr_is_hw_dbs_capable(psoc)); - /* once the PCL enum is obtained find out the exact channel list with * help from sme_get_cfg_valid_channels */ + status = policy_mgr_get_channel_list(psoc, pcl, pcl_channels, len, mode, - pcl_weight, weight_len); + pcl_weight, weight_len); if (QDF_IS_STATUS_ERROR(status)) { policy_mgr_err("failed to get channel list:%d", status); return status; } - policy_mgr_debug("pcl len:%d", *len); - for (i = 0; i < *len; i++) { - policy_mgr_debug("chan:%d weight:%d", - pcl_channels[i], pcl_weight[i]); - } + policy_mgr_dump_channel_list(*len, pcl_channels, pcl_weight); policy_mgr_mode_specific_modification_on_pcl( psoc, pcl_channels, pcl_weight, len, mode); @@ -1913,14 +1904,53 @@ uint8_t policy_mgr_get_alternate_channel_for_sap( { uint8_t pcl_channels[QDF_MAX_NUM_CHAN]; uint8_t pcl_weight[QDF_MAX_NUM_CHAN]; - uint8_t channel = 0; uint32_t pcl_len = 0; if (QDF_STATUS_SUCCESS == policy_mgr_get_pcl(psoc, PM_SAP_MODE, &pcl_channels[0], &pcl_len, pcl_weight, QDF_ARRAY_SIZE(pcl_weight))) { - channel = pcl_channels[0]; + if (pcl_len) + return pcl_channels[0]; } - return channel; + return 0; +} + +/* + * Buffer len size to consider the 4 char freq, 3 char weight, 2 char + * for open close brackets and space and a space, Total 10 + */ +#define CHAN_WEIGHT_CHAR_LEN 10 +#define MAX_CHAN_TO_PRINT 39 + +bool policy_mgr_dump_channel_list(uint32_t len, uint8_t *pcl_channels, + uint8_t *pcl_weight) +{ + uint32_t idx, buff_len, num = 0, count = 0; + char *chan_buff = NULL; + + buff_len = (QDF_MIN(len, MAX_CHAN_TO_PRINT) * CHAN_WEIGHT_CHAR_LEN) + 1; + chan_buff = qdf_mem_malloc(buff_len); + if (!chan_buff) + return false; + + policymgr_nofl_debug("Total PCL Chan Freq %d", len); + for (idx = 0; idx < len; idx++) { + num += qdf_scnprintf(chan_buff + num, buff_len - num, " %d[%d]", + pcl_channels[idx], pcl_weight[idx]); + count++; + if (count >= MAX_CHAN_TO_PRINT) { + /* Print the MAX_CHAN_TO_PRINT channels */ + policymgr_nofl_debug("Chan[weight]:%s", chan_buff); + count = 0; + num = 0; + } + } + /* Print any pending channels */ + if (num) + policymgr_nofl_debug("Chan[weight]:%s", chan_buff); + + qdf_mem_free(chan_buff); + + return true; } diff --git a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/src/wlan_policy_mgr_tables_1x1_dbs_i.h b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/src/wlan_policy_mgr_tables_1x1_dbs_i.h index 92501e8872ce..b153d93e1992 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/src/wlan_policy_mgr_tables_1x1_dbs_i.h +++ b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/src/wlan_policy_mgr_tables_1x1_dbs_i.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2017 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2017, 2019 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -207,85 +207,933 @@ pm_second_connection_pcl_dbs_1x1_table = { /** * third_connection_pcl_dbs_table - table which provides PCL for * the 3rd connection, when we have two connections already in - * the system (with DBS supported by HW) + * the system (with DBS supported by HW). For helium that is NON-DBS, + * DBS 1x1, three port concurrency would be disabled, so for every + * combination MAX_PCL_TYPE would be the return value, if in future + * the requirement for 3 port concurrency comes, refer to below table + * for details. + * static pm_dbs_pcl_third_connection_table_type + * pm_third_connection_pcl_dbs_1x1_table = { + * [PM_STA_SAP_SCC_24_1x1] = { + * [PM_STA_MODE] = {PM_5G_SCC_CH, PM_5G_SCC_CH, PM_5G_SCC_CH}, + * [PM_SAP_MODE] = {PM_5G, PM_5G, PM_5G}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = {PM_5G, PM_5G, PM_5G}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_SAP_SCC_24_2x2] = { + * [PM_STA_MODE] = {PM_5G_SCC_CH, PM_5G_SCC_CH, PM_5G_SCC_CH}, + * [PM_SAP_MODE] = {PM_5G, PM_5G, PM_5G}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = {PM_5G, PM_5G, PM_5G}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_SAP_MCC_24_1x1] = { + * [PM_STA_MODE] = {PM_5G_MCC_CH, PM_5G, PM_5G_MCC_CH}, + * [PM_SAP_MODE] = {PM_5G, PM_5G, PM_5G}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = {PM_5G, PM_5G, PM_5G}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_SAP_MCC_24_2x2] = { + * [PM_STA_MODE] = {PM_5G_MCC_CH, PM_5G, PM_5G_MCC_CH}, + * [PM_SAP_MODE] = {PM_5G, PM_5G, PM_5G}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = {PM_5G, PM_5G, PM_5G}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_SAP_SCC_5_1x1] = { + * [PM_STA_MODE] = {PM_SCC_CH_24G, PM_24G_SCC_CH, PM_SCC_CH_24G}, + * [PM_SAP_MODE] = {PM_24G, PM_24G, PM_24G}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = {PM_24G, PM_24G, PM_24G}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_SAP_SCC_5_2x2] = { + * [PM_STA_MODE] = {PM_SCC_CH_24G, PM_24G_SCC_CH, PM_SCC_CH_24G}, + * [PM_SAP_MODE] = {PM_24G, PM_24G, PM_24G}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = {PM_24G, PM_24G, PM_24G}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_SAP_MCC_5_1x1] = { + * [PM_STA_MODE] = {PM_MCC_CH_24G, PM_24G, PM_24G}, + * [PM_SAP_MODE] = {PM_24G, PM_24G, PM_24G}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = {PM_24G, PM_24G, PM_24G}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_SAP_MCC_5_2x2] = { + * [PM_STA_MODE] = {PM_MCC_CH_24G, PM_24G, PM_24G}, + * [PM_SAP_MODE] = {PM_24G, PM_24G, PM_24G}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = {PM_24G, PM_24G, PM_24G}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_SAP_MCC_24_5_1x1] = { + * [PM_STA_MODE] = {PM_MCC_CH_5G, PM_5G, PM_5G}, + * [PM_SAP_MODE] = {PM_24G, PM_24G, PM_24G}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_SAP_MCC_24_5_2x2] = { + * [PM_STA_MODE] = {PM_MCC_CH_5G, PM_5G, PM_5G}, + * [PM_SAP_MODE] = {PM_24G, PM_24G, PM_24G}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_SAP_DBS_1x1] = { + * [PM_STA_MODE] = { + * PM_SCC_ON_5_SCC_ON_24_5G, PM_NONE, PM_SCC_ON_5_SCC_ON_24}, + * [PM_SAP_MODE] = {PM_SCC_ON_5_SCC_ON_24, PM_SCC_ON_5_SCC_ON_24, + * PM_SCC_ON_5_SCC_ON_24}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = {PM_SCC_ON_5_SCC_ON_24, PM_SCC_ON_5_SCC_ON_24, + * PM_SCC_ON_5_SCC_ON_24}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_SAP_SAP_SCC_24_1x1] = { + * [PM_STA_MODE] = {PM_5G_SCC_CH, PM_5G_SCC_CH, PM_5G_SCC_CH}, + * [PM_SAP_MODE] = {PM_5G, PM_5G, PM_5G}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = {PM_5G, PM_5G, PM_5G}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_SAP_SAP_SCC_24_2x2] = { + * [PM_STA_MODE] = {PM_5G_SCC_CH, PM_5G_SCC_CH, PM_5G_SCC_CH}, + * [PM_SAP_MODE] = {PM_5G, PM_5G, PM_5G}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = {PM_5G, PM_5G, PM_5G}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_SAP_SAP_MCC_24_1x1] = { + * [PM_STA_MODE] = {PM_5G, PM_5G, PM_5G}, + * [PM_SAP_MODE] = {PM_5G, PM_5G, PM_5G}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_SAP_SAP_MCC_24_2x2] = { + * [PM_STA_MODE] = {PM_5G, PM_5G, PM_5G}, + * [PM_SAP_MODE] = {PM_5G, PM_5G, PM_5G}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_SAP_SAP_SCC_5_1x1] = { + * [PM_STA_MODE] = {PM_24G_SCC_CH_SBS_CH_5G, PM_24G_SCC_CH, + * PM_24G_SCC_CH_SBS_CH}, + * [PM_SAP_MODE] = {PM_24G, PM_24G, PM_24G}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = {PM_24G, PM_24G, PM_24G}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_SAP_SAP_SCC_5_2x2] = { + * [PM_STA_MODE] = {PM_24G_SCC_CH_SBS_CH_5G, PM_24G_SCC_CH, + * PM_24G_SCC_CH_SBS_CH}, + * [PM_SAP_MODE] = {PM_24G, PM_24G, PM_24G}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = {PM_24G, PM_24G, PM_24G}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_SAP_SAP_MCC_5_1x1] = { + * [PM_STA_MODE] = {PM_24G_SBS_CH_MCC_CH, PM_24G, PM_24G_MCC_CH}, + * [PM_SAP_MODE] = {PM_24G_SBS_CH_MCC_CH, PM_24G, PM_24G_MCC_CH}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_SAP_SAP_MCC_5_2x2] = { + * [PM_STA_MODE] = {PM_24G_SBS_CH_MCC_CH, PM_24G, PM_24G_MCC_CH}, + * [PM_SAP_MODE] = {PM_24G_SBS_CH_MCC_CH, PM_24G, PM_24G_MCC_CH}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_SAP_SAP_MCC_24_5_1x1] = { + * [PM_STA_MODE] = {PM_5G, PM_5G, PM_5G}, + * [PM_SAP_MODE] = {PM_5G, PM_5G, PM_5G}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_SAP_SAP_MCC_24_5_2x2] = { + * [PM_STA_MODE] = {PM_5G, PM_5G, PM_5G}, + * [PM_SAP_MODE] = {PM_5G, PM_5G, PM_5G}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_SAP_SAP_DBS_1x1] = { + * [PM_STA_MODE] = { PM_SCC_ON_5_SCC_ON_24_5G, PM_SCC_ON_5_SCC_ON_24, + * PM_SCC_ON_5_SCC_ON_24}, + * [PM_SAP_MODE] = { PM_SCC_ON_5_SCC_ON_24, PM_SCC_ON_5_SCC_ON_24, + * PM_SCC_ON_5_SCC_ON_24}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = {PM_SCC_ON_5_SCC_ON_24, PM_SCC_ON_5_SCC_ON_24, + * PM_SCC_ON_5_SCC_ON_24}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_GO_SCC_24_1x1] = { + * [PM_STA_MODE] = {PM_5G_SCC_CH, PM_5G_SCC_CH, PM_5G_SCC_CH}, + * [PM_SAP_MODE] = {PM_5G, PM_5G, PM_5G}, + * [PM_P2P_CLIENT_MODE] = {PM_5G_SCC_CH, PM_5G_SCC_CH, PM_5G_SCC_CH}, + * [PM_P2P_GO_MODE] = {PM_5G_SCC_CH, PM_5G_SCC_CH, PM_5G_SCC_CH}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_GO_SCC_24_2x2] = { + * [PM_STA_MODE] = {PM_5G_SCC_CH, PM_5G_SCC_CH, PM_5G_SCC_CH}, + [PM_SAP_MODE] = {PM_5G, PM_5G, PM_5G}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = {PM_5G_SCC_CH, PM_5G_SCC_CH, PM_5G_SCC_CH}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_GO_MCC_24_1x1] = { + * [PM_STA_MODE] = {PM_5G_MCC_CH, PM_5G, PM_5G_MCC_CH}, + * [PM_SAP_MODE] = {PM_5G, PM_5G, PM_5G}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = {PM_5G_MCC_CH, PM_5G, PM_5G_MCC_CH}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_GO_MCC_24_2x2] = { + * [PM_STA_MODE] = {PM_5G_MCC_CH, PM_5G, PM_5G_MCC_CH}, + * [PM_SAP_MODE] = {PM_5G, PM_5G, PM_5G}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = {PM_5G_MCC_CH, PM_5G, PM_5G_MCC_CH}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_GO_SCC_5_1x1] = { + * [PM_STA_MODE] = {PM_SCC_CH_24G, PM_24G_SCC_CH, PM_SCC_CH_24G}, + * [PM_SAP_MODE] = {PM_24G, PM_24G, PM_24G}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = {PM_SCC_CH_24G, PM_24G_SCC_CH, PM_SCC_CH_24G}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_GO_SCC_5_2x2] = { + * [PM_STA_MODE] = {PM_SCC_CH_24G, PM_24G_SCC_CH, PM_SCC_CH_24G}, + * [PM_SAP_MODE] = {PM_24G, PM_24G, PM_24G}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = {PM_SCC_CH_24G, PM_24G_SCC_CH, PM_SCC_CH_24G}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_GO_MCC_5_1x1] = { + * [PM_STA_MODE] = {PM_MCC_CH_24G, PM_24G, PM_24G}, + * [PM_SAP_MODE] = {PM_24G, PM_24G, PM_24G}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = {PM_MCC_CH_24G, PM_24G, PM_24G}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_GO_MCC_5_2x2] = { + * [PM_STA_MODE] = {PM_MCC_CH_24G, PM_24G, PM_24G}, + * [PM_SAP_MODE] = {PM_24G, PM_24G, PM_24G}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = {PM_MCC_CH_24G, PM_24G, PM_24G}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_GO_MCC_24_5_1x1] = { + * [PM_STA_MODE] = {PM_MCC_CH_5G, PM_5G, PM_5G}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = {PM_MCC_CH_24G, PM_24G, PM_24G}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_GO_MCC_24_5_2x2] = { + * [PM_STA_MODE] = {PM_MCC_CH_5G, PM_5G, PM_5G}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = {PM_MCC_CH_24G, PM_24G, PM_24G}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_GO_DBS_1x1] = { + * [PM_STA_MODE] = { + * PM_SCC_ON_5_SCC_ON_24_5G, PM_NONE, PM_SCC_ON_5_SCC_ON_24}, + * [PM_SAP_MODE] = {PM_SCC_ON_5_SCC_ON_24, PM_SCC_ON_5_SCC_ON_24, + * PM_SCC_ON_5_SCC_ON_24}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_SCC_ON_5_SCC_ON_24_5G, PM_NONE, PM_SCC_ON_5_SCC_ON_24}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_CLI_SCC_24_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_CLI_SCC_24_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_CLI_MCC_24_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_CLI_MCC_24_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_CLI_SCC_5_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_CLI_SCC_5_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_CLI_MCC_5_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_CLI_MCC_5_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_CLI_MCC_24_5_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_CLI_MCC_24_5_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_CLI_DBS_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_P2P_CLI_SCC_24_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_P2P_CLI_SCC_24_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_P2P_CLI_MCC_24_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_P2P_CLI_MCC_24_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_P2P_CLI_SCC_5_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_P2P_CLI_SCC_5_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_P2P_CLI_MCC_5_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_P2P_CLI_MCC_5_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_P2P_CLI_MCC_24_5_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_P2P_CLI_MCC_24_5_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_P2P_CLI_DBS_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_SAP_SCC_24_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = {PM_5G, PM_5G, PM_5G}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_SAP_SCC_24_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = {PM_5G, PM_5G, PM_5G}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_SAP_MCC_24_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_SAP_MCC_24_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_SAP_SCC_5_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = {PM_24G, PM_24G, PM_24G}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_SAP_SCC_5_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = {PM_24G, PM_24G, PM_24G}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_SAP_MCC_5_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_SAP_MCC_5_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_SAP_MCC_24_5_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_SAP_MCC_24_5_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_SAP_DBS_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = {PM_SCC_ON_5_SCC_ON_24, PM_SCC_ON_5_SCC_ON_24, + * PM_SCC_ON_5_SCC_ON_24}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_CLI_SAP_SCC_24_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_CLI_SAP_SCC_24_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_CLI_SAP_MCC_24_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_CLI_SAP_MCC_24_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_CLI_SAP_SCC_5_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_CLI_SAP_SCC_5_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_CLI_SAP_MCC_5_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_CLI_SAP_MCC_5_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_CLI_SAP_MCC_24_5_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_CLI_SAP_MCC_24_5_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_CLI_SAP_DBS_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * }; */ static pm_dbs_pcl_third_connection_table_type pm_third_connection_pcl_dbs_1x1_table = { [PM_STA_SAP_SCC_24_1x1] = { - [PM_STA_MODE] = {PM_5G_SCC_CH, PM_5G_SCC_CH, PM_5G_SCC_CH}, - [PM_SAP_MODE] = {PM_5G, PM_5G, PM_5G}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_GO_MODE] = {PM_5G, PM_5G, PM_5G}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_SAP_SCC_24_2x2] = { - [PM_STA_MODE] = {PM_5G_SCC_CH, PM_5G_SCC_CH, PM_5G_SCC_CH}, - [PM_SAP_MODE] = {PM_5G, PM_5G, PM_5G}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_GO_MODE] = {PM_5G, PM_5G, PM_5G}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_SAP_MCC_24_1x1] = { - [PM_STA_MODE] = {PM_5G_MCC_CH, PM_5G, PM_5G_MCC_CH}, - [PM_SAP_MODE] = {PM_5G, PM_5G, PM_5G}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_GO_MODE] = {PM_5G, PM_5G, PM_5G}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_SAP_MCC_24_2x2] = { - [PM_STA_MODE] = {PM_5G_MCC_CH, PM_5G, PM_5G_MCC_CH}, - [PM_SAP_MODE] = {PM_5G, PM_5G, PM_5G}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_GO_MODE] = {PM_5G, PM_5G, PM_5G}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_SAP_SCC_5_1x1] = { - [PM_STA_MODE] = {PM_SCC_CH_24G, PM_24G_SCC_CH, PM_SCC_CH_24G}, - [PM_SAP_MODE] = {PM_24G, PM_24G, PM_24G}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_GO_MODE] = {PM_24G, PM_24G, PM_24G}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_SAP_SCC_5_2x2] = { - [PM_STA_MODE] = {PM_SCC_CH_24G, PM_24G_SCC_CH, PM_SCC_CH_24G}, - [PM_SAP_MODE] = {PM_24G, PM_24G, PM_24G}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_GO_MODE] = {PM_24G, PM_24G, PM_24G}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_SAP_MCC_5_1x1] = { - [PM_STA_MODE] = {PM_MCC_CH_24G, PM_24G, PM_24G}, - [PM_SAP_MODE] = {PM_24G, PM_24G, PM_24G}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_GO_MODE] = {PM_24G, PM_24G, PM_24G}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_SAP_MCC_5_2x2] = { - [PM_STA_MODE] = {PM_MCC_CH_24G, PM_24G, PM_24G}, - [PM_SAP_MODE] = {PM_24G, PM_24G, PM_24G}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_GO_MODE] = {PM_24G, PM_24G, PM_24G}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_SAP_MCC_24_5_1x1] = { - [PM_STA_MODE] = {PM_MCC_CH_5G, PM_5G, PM_5G}, - [PM_SAP_MODE] = {PM_24G, PM_24G, PM_24G}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_GO_MODE] = { @@ -294,8 +1142,8 @@ pm_third_connection_pcl_dbs_1x1_table = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_SAP_MCC_24_5_2x2] = { - [PM_STA_MODE] = {PM_MCC_CH_5G, PM_5G, PM_5G}, - [PM_SAP_MODE] = {PM_24G, PM_24G, PM_24G}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_GO_MODE] = { @@ -305,37 +1153,37 @@ pm_third_connection_pcl_dbs_1x1_table = { [PM_STA_SAP_DBS_1x1] = { [PM_STA_MODE] = { - PM_SCC_ON_5_SCC_ON_24_5G, PM_NONE, PM_SCC_ON_5_SCC_ON_24}, - [PM_SAP_MODE] = {PM_SCC_ON_5_SCC_ON_24, PM_SCC_ON_5_SCC_ON_24, - PM_SCC_ON_5_SCC_ON_24}, + PM_MAX_PCL_TYPE, PM_NONE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, + PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_GO_MODE] = {PM_SCC_ON_5_SCC_ON_24, PM_SCC_ON_5_SCC_ON_24, - PM_SCC_ON_5_SCC_ON_24}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, + PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_SAP_SAP_SCC_24_1x1] = { - [PM_STA_MODE] = {PM_5G_SCC_CH, PM_5G_SCC_CH, PM_5G_SCC_CH}, - [PM_SAP_MODE] = {PM_5G, PM_5G, PM_5G}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_GO_MODE] = {PM_5G, PM_5G, PM_5G}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_SAP_SAP_SCC_24_2x2] = { - [PM_STA_MODE] = {PM_5G_SCC_CH, PM_5G_SCC_CH, PM_5G_SCC_CH}, - [PM_SAP_MODE] = {PM_5G, PM_5G, PM_5G}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_GO_MODE] = {PM_5G, PM_5G, PM_5G}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_SAP_SAP_MCC_24_1x1] = { - [PM_STA_MODE] = {PM_5G, PM_5G, PM_5G}, - [PM_SAP_MODE] = {PM_5G, PM_5G, PM_5G}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_GO_MODE] = { @@ -344,8 +1192,8 @@ pm_third_connection_pcl_dbs_1x1_table = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_SAP_SAP_MCC_24_2x2] = { - [PM_STA_MODE] = {PM_5G, PM_5G, PM_5G}, - [PM_SAP_MODE] = {PM_5G, PM_5G, PM_5G}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_GO_MODE] = { @@ -354,28 +1202,28 @@ pm_third_connection_pcl_dbs_1x1_table = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_SAP_SAP_SCC_5_1x1] = { - [PM_STA_MODE] = {PM_24G_SCC_CH_SBS_CH_5G, PM_24G_SCC_CH, - PM_24G_SCC_CH_SBS_CH}, - [PM_SAP_MODE] = {PM_24G, PM_24G, PM_24G}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, + PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_GO_MODE] = {PM_24G, PM_24G, PM_24G}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_SAP_SAP_SCC_5_2x2] = { - [PM_STA_MODE] = {PM_24G_SCC_CH_SBS_CH_5G, PM_24G_SCC_CH, - PM_24G_SCC_CH_SBS_CH}, - [PM_SAP_MODE] = {PM_24G, PM_24G, PM_24G}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, + PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_GO_MODE] = {PM_24G, PM_24G, PM_24G}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_SAP_SAP_MCC_5_1x1] = { - [PM_STA_MODE] = {PM_24G_SBS_CH_MCC_CH, PM_24G, PM_24G_MCC_CH}, - [PM_SAP_MODE] = {PM_24G_SBS_CH_MCC_CH, PM_24G, PM_24G_MCC_CH}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_GO_MODE] = { @@ -384,8 +1232,8 @@ pm_third_connection_pcl_dbs_1x1_table = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_SAP_SAP_MCC_5_2x2] = { - [PM_STA_MODE] = {PM_24G_SBS_CH_MCC_CH, PM_24G, PM_24G_MCC_CH}, - [PM_SAP_MODE] = {PM_24G_SBS_CH_MCC_CH, PM_24G, PM_24G_MCC_CH}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_GO_MODE] = { @@ -394,8 +1242,8 @@ pm_third_connection_pcl_dbs_1x1_table = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_SAP_SAP_MCC_24_5_1x1] = { - [PM_STA_MODE] = {PM_5G, PM_5G, PM_5G}, - [PM_SAP_MODE] = {PM_5G, PM_5G, PM_5G}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_GO_MODE] = { @@ -404,8 +1252,8 @@ pm_third_connection_pcl_dbs_1x1_table = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_SAP_SAP_MCC_24_5_2x2] = { - [PM_STA_MODE] = {PM_5G, PM_5G, PM_5G}, - [PM_SAP_MODE] = {PM_5G, PM_5G, PM_5G}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_GO_MODE] = { @@ -414,117 +1262,118 @@ pm_third_connection_pcl_dbs_1x1_table = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_SAP_SAP_DBS_1x1] = { - [PM_STA_MODE] = { PM_SCC_ON_5_SCC_ON_24_5G, PM_SCC_ON_5_SCC_ON_24, - PM_SCC_ON_5_SCC_ON_24}, - [PM_SAP_MODE] = { PM_SCC_ON_5_SCC_ON_24, PM_SCC_ON_5_SCC_ON_24, - PM_SCC_ON_5_SCC_ON_24}, + [PM_STA_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, + PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, + PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_GO_MODE] = {PM_SCC_ON_5_SCC_ON_24, PM_SCC_ON_5_SCC_ON_24, - PM_SCC_ON_5_SCC_ON_24}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, + PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_P2P_GO_SCC_24_1x1] = { - [PM_STA_MODE] = {PM_5G_SCC_CH, PM_5G_SCC_CH, PM_5G_SCC_CH}, - [PM_SAP_MODE] = {PM_5G, PM_5G, PM_5G}, - [PM_P2P_CLIENT_MODE] = {PM_5G_SCC_CH, PM_5G_SCC_CH, PM_5G_SCC_CH}, - [PM_P2P_GO_MODE] = {PM_5G_SCC_CH, PM_5G_SCC_CH, PM_5G_SCC_CH}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_CLIENT_MODE] = + {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_P2P_GO_SCC_24_2x2] = { - [PM_STA_MODE] = {PM_5G_SCC_CH, PM_5G_SCC_CH, PM_5G_SCC_CH}, - [PM_SAP_MODE] = {PM_5G, PM_5G, PM_5G}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_GO_MODE] = {PM_5G_SCC_CH, PM_5G_SCC_CH, PM_5G_SCC_CH}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_P2P_GO_MCC_24_1x1] = { - [PM_STA_MODE] = {PM_5G_MCC_CH, PM_5G, PM_5G_MCC_CH}, - [PM_SAP_MODE] = {PM_5G, PM_5G, PM_5G}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_GO_MODE] = {PM_5G_MCC_CH, PM_5G, PM_5G_MCC_CH}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_P2P_GO_MCC_24_2x2] = { - [PM_STA_MODE] = {PM_5G_MCC_CH, PM_5G, PM_5G_MCC_CH}, - [PM_SAP_MODE] = {PM_5G, PM_5G, PM_5G}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_GO_MODE] = {PM_5G_MCC_CH, PM_5G, PM_5G_MCC_CH}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_P2P_GO_SCC_5_1x1] = { - [PM_STA_MODE] = {PM_SCC_CH_24G, PM_24G_SCC_CH, PM_SCC_CH_24G}, - [PM_SAP_MODE] = {PM_24G, PM_24G, PM_24G}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_GO_MODE] = {PM_SCC_CH_24G, PM_24G_SCC_CH, PM_SCC_CH_24G}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_P2P_GO_SCC_5_2x2] = { - [PM_STA_MODE] = {PM_SCC_CH_24G, PM_24G_SCC_CH, PM_SCC_CH_24G}, - [PM_SAP_MODE] = {PM_24G, PM_24G, PM_24G}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_GO_MODE] = {PM_SCC_CH_24G, PM_24G_SCC_CH, PM_SCC_CH_24G}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_P2P_GO_MCC_5_1x1] = { - [PM_STA_MODE] = {PM_MCC_CH_24G, PM_24G, PM_24G}, - [PM_SAP_MODE] = {PM_24G, PM_24G, PM_24G}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_GO_MODE] = {PM_MCC_CH_24G, PM_24G, PM_24G}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_P2P_GO_MCC_5_2x2] = { - [PM_STA_MODE] = {PM_MCC_CH_24G, PM_24G, PM_24G}, - [PM_SAP_MODE] = {PM_24G, PM_24G, PM_24G}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_GO_MODE] = {PM_MCC_CH_24G, PM_24G, PM_24G}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_P2P_GO_MCC_24_5_1x1] = { - [PM_STA_MODE] = {PM_MCC_CH_5G, PM_5G, PM_5G}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_SAP_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_GO_MODE] = {PM_MCC_CH_24G, PM_24G, PM_24G}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_P2P_GO_MCC_24_5_2x2] = { - [PM_STA_MODE] = {PM_MCC_CH_5G, PM_5G, PM_5G}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_SAP_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_GO_MODE] = {PM_MCC_CH_24G, PM_24G, PM_24G}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_P2P_GO_DBS_1x1] = { [PM_STA_MODE] = { - PM_SCC_ON_5_SCC_ON_24_5G, PM_NONE, PM_SCC_ON_5_SCC_ON_24}, - [PM_SAP_MODE] = {PM_SCC_ON_5_SCC_ON_24, PM_SCC_ON_5_SCC_ON_24, - PM_SCC_ON_5_SCC_ON_24}, + PM_MAX_PCL_TYPE, PM_NONE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, + PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_GO_MODE] = { - PM_SCC_ON_5_SCC_ON_24_5G, PM_NONE, PM_SCC_ON_5_SCC_ON_24}, + PM_MAX_PCL_TYPE, PM_NONE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, @@ -795,7 +1644,7 @@ pm_third_connection_pcl_dbs_1x1_table = { [PM_P2P_GO_SAP_SCC_24_1x1] = { [PM_STA_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_SAP_MODE] = {PM_5G, PM_5G, PM_5G}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_GO_MODE] = { @@ -806,7 +1655,7 @@ pm_third_connection_pcl_dbs_1x1_table = { [PM_P2P_GO_SAP_SCC_24_2x2] = { [PM_STA_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_SAP_MODE] = {PM_5G, PM_5G, PM_5G}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_GO_MODE] = { @@ -841,7 +1690,7 @@ pm_third_connection_pcl_dbs_1x1_table = { [PM_P2P_GO_SAP_SCC_5_1x1] = { [PM_STA_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_SAP_MODE] = {PM_24G, PM_24G, PM_24G}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_GO_MODE] = { @@ -852,7 +1701,7 @@ pm_third_connection_pcl_dbs_1x1_table = { [PM_P2P_GO_SAP_SCC_5_2x2] = { [PM_STA_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_SAP_MODE] = {PM_24G, PM_24G, PM_24G}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_GO_MODE] = { @@ -911,8 +1760,8 @@ pm_third_connection_pcl_dbs_1x1_table = { [PM_P2P_GO_SAP_DBS_1x1] = { [PM_STA_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_SAP_MODE] = {PM_SCC_ON_5_SCC_ON_24, PM_SCC_ON_5_SCC_ON_24, - PM_SCC_ON_5_SCC_ON_24}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, + PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_GO_MODE] = { @@ -1054,6 +1903,7 @@ pm_third_connection_pcl_dbs_1x1_table = { }; + /** * next_action_two_connection_table - table which provides next * action while a new connection is coming up, with one diff --git a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/src/wlan_policy_mgr_tables_no_dbs_i.h b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/src/wlan_policy_mgr_tables_no_dbs_i.h index 204185247d07..15ebdd82aa3c 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/src/wlan_policy_mgr_tables_no_dbs_i.h +++ b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/policy_mgr/src/wlan_policy_mgr_tables_no_dbs_i.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2017 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2017, 2019 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -209,14 +209,702 @@ second_connection_pcl_nodbs_table[PM_MAX_ONE_CONNECTION_MODE] /** * third_connection_pcl_nodbs_table - table which provides PCL * for the 3rd connection, when we have two connections already - * in the system (with DBS not supported by HW) + * in the system (with DBS not supported by HW). For helium that is NON-DBS, + * DBS 1x1, three port concurrency would be disabled, so for every + * combination MAX_PCL_TYPE would be the return value, if in future + * the requirement for 3 port concurrency comes, refer to below table + * for details. + * static const enum policy_mgr_pcl_type + * third_connection_pcl_nodbs_table[PM_MAX_TWO_CONNECTION_MODE] + * [PM_MAX_NUM_OF_MODE][PM_MAX_CONC_PRIORITY_MODE] = { + * [PM_STA_SAP_SCC_24_1x1] = { + * [PM_STA_MODE] = {PM_SCC_CH_5G, PM_SCC_CH, PM_SCC_CH}, + * [PM_SAP_MODE] = {PM_SCC_CH_5G, PM_SCC_CH, PM_SCC_CH}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_SAP_SCC_24_2x2] = { + * [PM_STA_MODE] = {PM_SCC_CH_5G, PM_SCC_CH, PM_SCC_CH}, + * [PM_SAP_MODE] = {PM_SCC_CH_5G, PM_SCC_CH, PM_SCC_CH}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_SAP_MCC_24_1x1] = { + * [PM_STA_MODE] = {PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_SAP_MODE] = {PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_SAP_MCC_24_2x2] = { + * [PM_STA_MODE] = {PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_SAP_MODE] = {PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_SAP_SCC_5_1x1] = { + * [PM_STA_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + * [PM_SAP_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_SAP_SCC_5_2x2] = { + * [PM_STA_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + * [PM_SAP_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_SAP_MCC_5_1x1] = { + * [PM_STA_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_SAP_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_SAP_MCC_5_2x2] = { + * [PM_STA_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_SAP_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_SAP_MCC_24_5_1x1] = { + * [PM_STA_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_SAP_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_SAP_MCC_24_5_2x2] = { + * [PM_STA_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_SAP_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_SAP_DBS_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_GO_SCC_24_1x1] = { + * [PM_STA_MODE] = {PM_5G, PM_SCC_CH, PM_SCC_CH}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = {PM_5G, PM_SCC_CH, PM_SCC_CH}, + * [PM_P2P_GO_MODE] = {PM_5G_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_GO_SCC_24_2x2] = { + * [PM_STA_MODE] = {PM_5G, PM_SCC_CH, PM_SCC_CH}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = {PM_5G, PM_SCC_CH, PM_SCC_CH}, + * [PM_P2P_GO_MODE] = {PM_5G_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_GO_MCC_24_1x1] = { + * [PM_STA_MODE] = {PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_P2P_GO_MODE] = { + * PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_GO_MCC_24_2x2] = { + * [PM_STA_MODE] = {PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_P2P_GO_MODE] = { + * PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_GO_SCC_5_1x1] = { + * [PM_STA_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + * [PM_P2P_GO_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_GO_SCC_5_2x2] = { + * [PM_STA_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + * [PM_P2P_GO_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_GO_MCC_5_1x1] = { + * [PM_STA_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_P2P_GO_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_GO_MCC_5_2x2] = { + * [PM_STA_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_P2P_GO_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_GO_MCC_24_5_1x1] = { + * [PM_STA_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_P2P_GO_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_GO_MCC_24_5_2x2] = { + * [PM_STA_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_P2P_GO_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_GO_DBS_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_CLI_SCC_24_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = {PM_5G_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + * [PM_P2P_GO_MODE] = {PM_5G_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_CLI_SCC_24_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = {PM_5G_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + * [PM_P2P_GO_MODE] = {PM_5G_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_CLI_MCC_24_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = {PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_P2P_GO_MODE] = {PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_CLI_MCC_24_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = {PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_P2P_GO_MODE] = {PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_CLI_SCC_5_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + * [PM_P2P_GO_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_CLI_SCC_5_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + * [PM_P2P_GO_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_CLI_MCC_5_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_P2P_GO_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_CLI_MCC_5_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_P2P_GO_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_CLI_MCC_24_5_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_P2P_GO_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_CLI_MCC_24_5_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_P2P_GO_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_STA_P2P_CLI_DBS_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_P2P_CLI_SCC_24_1x1] = { + * [PM_STA_MODE] = {PM_5G, PM_SCC_CH, PM_SCC_CH}, + * [PM_SAP_MODE] = {PM_SCC_CH_5G, PM_SCC_CH, PM_SCC_CH}, + * [PM_P2P_CLIENT_MODE] = {PM_5G, PM_SCC_CH, PM_SCC_CH}, + * [PM_P2P_GO_MODE] = {PM_5G_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_P2P_CLI_SCC_24_2x2] = { + * [PM_STA_MODE] = {PM_5G, PM_SCC_CH, PM_SCC_CH}, + * [PM_SAP_MODE] = {PM_SCC_CH_5G, PM_SCC_CH, PM_SCC_CH}, + * [PM_P2P_CLIENT_MODE] = {PM_5G, PM_SCC_CH, PM_SCC_CH}, + * [PM_P2P_GO_MODE] = {PM_5G_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_P2P_CLI_MCC_24_1x1] = { + * [PM_STA_MODE] = {PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_SAP_MODE] = {PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_P2P_CLIENT_MODE] = { + * PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_P2P_GO_MODE] = { + * PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_P2P_CLI_MCC_24_2x2] = { + * [PM_STA_MODE] = {PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_SAP_MODE] = {PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_P2P_CLIENT_MODE] = { + * PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_P2P_GO_MODE] = { + * PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_P2P_CLI_SCC_5_1x1] = { + * [PM_STA_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + * [PM_SAP_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + * [PM_P2P_CLIENT_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + * [PM_P2P_GO_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_P2P_CLI_SCC_5_2x2] = { + * [PM_STA_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + * [PM_SAP_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + * [PM_P2P_CLIENT_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + * [PM_P2P_GO_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_P2P_CLI_MCC_5_1x1] = { + * [PM_STA_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_SAP_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_P2P_CLIENT_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_P2P_GO_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_P2P_CLI_MCC_5_2x2] = { + * [PM_STA_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_SAP_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_P2P_CLIENT_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_P2P_GO_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_P2P_CLI_MCC_24_5_1x1] = { + * [PM_STA_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_SAP_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_P2P_CLIENT_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_P2P_GO_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_P2P_CLI_MCC_24_5_2x2] = { + * [PM_STA_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_SAP_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_P2P_CLIENT_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_P2P_GO_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_P2P_CLI_DBS_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_SAP_SCC_24_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_SAP_SCC_24_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_SAP_MCC_24_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_SAP_MCC_24_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_SAP_SCC_5_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_SAP_SCC_5_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_SAP_MCC_5_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_SAP_MCC_5_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_SAP_MCC_24_5_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_SAP_MCC_24_5_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_GO_SAP_DBS_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * + * [PM_P2P_CLI_SAP_SCC_24_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_CLI_SAP_SCC_24_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_CLI_SAP_MCC_24_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_CLI_SAP_MCC_24_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_CLI_SAP_SCC_5_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_CLI_SAP_SCC_5_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_CLI_SAP_MCC_5_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_CLI_SAP_MCC_5_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_CLI_SAP_MCC_24_5_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_CLI_SAP_MCC_24_5_2x2] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * + * [PM_P2P_CLI_SAP_DBS_1x1] = { + * [PM_STA_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_SAP_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_CLIENT_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_P2P_GO_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + * [PM_IBSS_MODE] = { + * PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, + * }; */ static const enum policy_mgr_pcl_type third_connection_pcl_nodbs_table[PM_MAX_TWO_CONNECTION_MODE] [PM_MAX_NUM_OF_MODE][PM_MAX_CONC_PRIORITY_MODE] = { [PM_STA_SAP_SCC_24_1x1] = { - [PM_STA_MODE] = {PM_SCC_CH_5G, PM_SCC_CH, PM_SCC_CH}, - [PM_SAP_MODE] = {PM_SCC_CH_5G, PM_SCC_CH, PM_SCC_CH}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_GO_MODE] = { @@ -225,8 +913,8 @@ third_connection_pcl_nodbs_table[PM_MAX_TWO_CONNECTION_MODE] PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_SAP_SCC_24_2x2] = { - [PM_STA_MODE] = {PM_SCC_CH_5G, PM_SCC_CH, PM_SCC_CH}, - [PM_SAP_MODE] = {PM_SCC_CH_5G, PM_SCC_CH, PM_SCC_CH}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_GO_MODE] = { @@ -235,8 +923,8 @@ third_connection_pcl_nodbs_table[PM_MAX_TWO_CONNECTION_MODE] PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_SAP_MCC_24_1x1] = { - [PM_STA_MODE] = {PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, - [PM_SAP_MODE] = {PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_GO_MODE] = { @@ -245,8 +933,8 @@ third_connection_pcl_nodbs_table[PM_MAX_TWO_CONNECTION_MODE] PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_SAP_MCC_24_2x2] = { - [PM_STA_MODE] = {PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, - [PM_SAP_MODE] = {PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_GO_MODE] = { @@ -255,8 +943,8 @@ third_connection_pcl_nodbs_table[PM_MAX_TWO_CONNECTION_MODE] PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_SAP_SCC_5_1x1] = { - [PM_STA_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, - [PM_SAP_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_GO_MODE] = { @@ -265,8 +953,8 @@ third_connection_pcl_nodbs_table[PM_MAX_TWO_CONNECTION_MODE] PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_SAP_SCC_5_2x2] = { - [PM_STA_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, - [PM_SAP_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_GO_MODE] = { @@ -275,8 +963,8 @@ third_connection_pcl_nodbs_table[PM_MAX_TWO_CONNECTION_MODE] PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_SAP_MCC_5_1x1] = { - [PM_STA_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, - [PM_SAP_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_GO_MODE] = { @@ -285,8 +973,8 @@ third_connection_pcl_nodbs_table[PM_MAX_TWO_CONNECTION_MODE] PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_SAP_MCC_5_2x2] = { - [PM_STA_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, - [PM_SAP_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_GO_MODE] = { @@ -295,8 +983,8 @@ third_connection_pcl_nodbs_table[PM_MAX_TWO_CONNECTION_MODE] PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_SAP_MCC_24_5_1x1] = { - [PM_STA_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, - [PM_SAP_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_GO_MODE] = { @@ -305,8 +993,8 @@ third_connection_pcl_nodbs_table[PM_MAX_TWO_CONNECTION_MODE] PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_SAP_MCC_24_5_2x2] = { - [PM_STA_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, - [PM_SAP_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_GO_MODE] = { @@ -327,96 +1015,104 @@ third_connection_pcl_nodbs_table[PM_MAX_TWO_CONNECTION_MODE] PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_P2P_GO_SCC_24_1x1] = { - [PM_STA_MODE] = {PM_5G, PM_SCC_CH, PM_SCC_CH}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_SAP_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_CLIENT_MODE] = {PM_5G, PM_SCC_CH, PM_SCC_CH}, - [PM_P2P_GO_MODE] = {PM_5G_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + [PM_P2P_CLIENT_MODE] = + {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_P2P_GO_SCC_24_2x2] = { - [PM_STA_MODE] = {PM_5G, PM_SCC_CH, PM_SCC_CH}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_SAP_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_CLIENT_MODE] = {PM_5G, PM_SCC_CH, PM_SCC_CH}, - [PM_P2P_GO_MODE] = {PM_5G_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + [PM_P2P_CLIENT_MODE] = + {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_P2P_GO_MCC_24_1x1] = { - [PM_STA_MODE] = {PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_SAP_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { - PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_GO_MODE] = { - PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_P2P_GO_MCC_24_2x2] = { - [PM_STA_MODE] = {PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_SAP_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { - PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_GO_MODE] = { - PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_P2P_GO_SCC_5_1x1] = { - [PM_STA_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_SAP_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_CLIENT_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, - [PM_P2P_GO_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + [PM_P2P_CLIENT_MODE] = + {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_P2P_GO_SCC_5_2x2] = { - [PM_STA_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_SAP_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_CLIENT_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, - [PM_P2P_GO_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + [PM_P2P_CLIENT_MODE] = + {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_P2P_GO_MCC_5_1x1] = { - [PM_STA_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_SAP_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_CLIENT_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, - [PM_P2P_GO_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + [PM_P2P_CLIENT_MODE] = + {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_P2P_GO_MCC_5_2x2] = { - [PM_STA_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_SAP_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_CLIENT_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, - [PM_P2P_GO_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + [PM_P2P_CLIENT_MODE] = + {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_P2P_GO_MCC_24_5_1x1] = { - [PM_STA_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_SAP_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_CLIENT_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, - [PM_P2P_GO_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + [PM_P2P_CLIENT_MODE] = + {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_STA_P2P_GO_MCC_24_5_2x2] = { - [PM_STA_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_SAP_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_CLIENT_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, - [PM_P2P_GO_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + [PM_P2P_CLIENT_MODE] = + {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, @@ -437,8 +1133,9 @@ third_connection_pcl_nodbs_table[PM_MAX_TWO_CONNECTION_MODE] PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_SAP_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_CLIENT_MODE] = {PM_5G_SCC_CH, PM_SCC_CH, PM_SCC_CH}, - [PM_P2P_GO_MODE] = {PM_5G_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + [PM_P2P_CLIENT_MODE] = + {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, @@ -447,8 +1144,9 @@ third_connection_pcl_nodbs_table[PM_MAX_TWO_CONNECTION_MODE] PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_SAP_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_CLIENT_MODE] = {PM_5G_SCC_CH, PM_SCC_CH, PM_SCC_CH}, - [PM_P2P_GO_MODE] = {PM_5G_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + [PM_P2P_CLIENT_MODE] = + {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, @@ -457,8 +1155,9 @@ third_connection_pcl_nodbs_table[PM_MAX_TWO_CONNECTION_MODE] PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_SAP_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_CLIENT_MODE] = {PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, - [PM_P2P_GO_MODE] = {PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + [PM_P2P_CLIENT_MODE] = + {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, @@ -467,8 +1166,9 @@ third_connection_pcl_nodbs_table[PM_MAX_TWO_CONNECTION_MODE] PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_SAP_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_CLIENT_MODE] = {PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, - [PM_P2P_GO_MODE] = {PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + [PM_P2P_CLIENT_MODE] = + {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, @@ -477,8 +1177,9 @@ third_connection_pcl_nodbs_table[PM_MAX_TWO_CONNECTION_MODE] PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_SAP_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_CLIENT_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, - [PM_P2P_GO_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + [PM_P2P_CLIENT_MODE] = + {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, @@ -487,8 +1188,9 @@ third_connection_pcl_nodbs_table[PM_MAX_TWO_CONNECTION_MODE] PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_SAP_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_CLIENT_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, - [PM_P2P_GO_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + [PM_P2P_CLIENT_MODE] = + {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, @@ -497,8 +1199,9 @@ third_connection_pcl_nodbs_table[PM_MAX_TWO_CONNECTION_MODE] PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_SAP_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_CLIENT_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, - [PM_P2P_GO_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + [PM_P2P_CLIENT_MODE] = + {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, @@ -507,8 +1210,9 @@ third_connection_pcl_nodbs_table[PM_MAX_TWO_CONNECTION_MODE] PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_SAP_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_CLIENT_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, - [PM_P2P_GO_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + [PM_P2P_CLIENT_MODE] = + {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, @@ -517,8 +1221,9 @@ third_connection_pcl_nodbs_table[PM_MAX_TWO_CONNECTION_MODE] PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_SAP_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_CLIENT_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, - [PM_P2P_GO_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + [PM_P2P_CLIENT_MODE] = + {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, @@ -527,8 +1232,9 @@ third_connection_pcl_nodbs_table[PM_MAX_TWO_CONNECTION_MODE] PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_SAP_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, - [PM_P2P_CLIENT_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, - [PM_P2P_GO_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + [PM_P2P_CLIENT_MODE] = + {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, @@ -545,86 +1251,94 @@ third_connection_pcl_nodbs_table[PM_MAX_TWO_CONNECTION_MODE] PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_P2P_GO_P2P_CLI_SCC_24_1x1] = { - [PM_STA_MODE] = {PM_5G, PM_SCC_CH, PM_SCC_CH}, - [PM_SAP_MODE] = {PM_SCC_CH_5G, PM_SCC_CH, PM_SCC_CH}, - [PM_P2P_CLIENT_MODE] = {PM_5G, PM_SCC_CH, PM_SCC_CH}, - [PM_P2P_GO_MODE] = {PM_5G_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_CLIENT_MODE] = + {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_P2P_GO_P2P_CLI_SCC_24_2x2] = { - [PM_STA_MODE] = {PM_5G, PM_SCC_CH, PM_SCC_CH}, - [PM_SAP_MODE] = {PM_SCC_CH_5G, PM_SCC_CH, PM_SCC_CH}, - [PM_P2P_CLIENT_MODE] = {PM_5G, PM_SCC_CH, PM_SCC_CH}, - [PM_P2P_GO_MODE] = {PM_5G_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_CLIENT_MODE] = + {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_P2P_GO_P2P_CLI_MCC_24_1x1] = { - [PM_STA_MODE] = {PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, - [PM_SAP_MODE] = {PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { - PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_GO_MODE] = { - PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_P2P_GO_P2P_CLI_MCC_24_2x2] = { - [PM_STA_MODE] = {PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, - [PM_SAP_MODE] = {PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_CLIENT_MODE] = { - PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_P2P_GO_MODE] = { - PM_5G_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_P2P_GO_P2P_CLI_SCC_5_1x1] = { - [PM_STA_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, - [PM_SAP_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, - [PM_P2P_CLIENT_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, - [PM_P2P_GO_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_CLIENT_MODE] = + {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_P2P_GO_P2P_CLI_SCC_5_2x2] = { - [PM_STA_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, - [PM_SAP_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, - [PM_P2P_CLIENT_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, - [PM_P2P_GO_MODE] = {PM_SCC_CH, PM_SCC_CH, PM_SCC_CH}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_CLIENT_MODE] = + {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_P2P_GO_P2P_CLI_MCC_5_1x1] = { - [PM_STA_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, - [PM_SAP_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, - [PM_P2P_CLIENT_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, - [PM_P2P_GO_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_CLIENT_MODE] = + {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_P2P_GO_P2P_CLI_MCC_5_2x2] = { - [PM_STA_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, - [PM_SAP_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, - [PM_P2P_CLIENT_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, - [PM_P2P_GO_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_CLIENT_MODE] = + {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_P2P_GO_P2P_CLI_MCC_24_5_1x1] = { - [PM_STA_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, - [PM_SAP_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, - [PM_P2P_CLIENT_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, - [PM_P2P_GO_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_CLIENT_MODE] = + {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, [PM_P2P_GO_P2P_CLI_MCC_24_5_2x2] = { - [PM_STA_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, - [PM_SAP_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, - [PM_P2P_CLIENT_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, - [PM_P2P_GO_MODE] = {PM_MCC_CH, PM_MCC_CH, PM_MCC_CH}, + [PM_STA_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_SAP_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_CLIENT_MODE] = + {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, + [PM_P2P_GO_MODE] = {PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, @@ -894,7 +1608,6 @@ third_connection_pcl_nodbs_table[PM_MAX_TWO_CONNECTION_MODE] PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE}, [PM_IBSS_MODE] = { PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE, PM_MAX_PCL_TYPE} }, - }; #endif diff --git a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/serialization/inc/wlan_serialization_api.h b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/serialization/inc/wlan_serialization_api.h index 69b33481d7e0..392ecdaf96e8 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/serialization/inc/wlan_serialization_api.h +++ b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/serialization/inc/wlan_serialization_api.h @@ -286,21 +286,6 @@ wlan_serialization_cancel_request( void wlan_serialization_remove_cmd( struct wlan_serialization_queued_cmd_info *cmd); -/** - * wlan_serialization_flush_cmd() - Request to flush command - * @cmd: Command information - * - * This API is used to flush a cmd sitting in the queue. It - * simply flushes the cmd from the queue and does not call - * any callbacks in between. If the request is for active - * queue, and if the active queue becomes empty upon flush, - * then it will pick the next pending cmd and put in the active - * queue before returning. - * - * Return: None - */ -void wlan_serialization_flush_cmd( - struct wlan_serialization_queued_cmd_info *cmd); /** * wlan_serialization_request() - Request to serialize a command * @cmd: Command information @@ -422,17 +407,6 @@ wlan_serialization_vdev_scan_status(struct wlan_objmgr_vdev *vdev); enum wlan_serialization_cmd_status wlan_serialization_pdev_scan_status(struct wlan_objmgr_pdev *pdev); -/** - * wlan_serialization_non_scan_cmd_status() - Return status of pdev non-scan cmd - * @pdev: PDEV Object - * @cmd_id: ID of the command for which the status has to be checked - * - * Return: Status of the command for the corresponding pdev - */ -enum wlan_serialization_cmd_status -wlan_serialization_non_scan_cmd_status(struct wlan_objmgr_pdev *pdev, - enum wlan_serialization_cmd_type cmd_id); - /** * wlan_serialization_is_cmd_present_in_pending_queue() - Return if the command * is already present in pending queue diff --git a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/serialization/inc/wlan_serialization_legacy_api.h b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/serialization/inc/wlan_serialization_legacy_api.h index 051f26053d8e..8967820b992a 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/serialization/inc/wlan_serialization_legacy_api.h +++ b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/serialization/inc/wlan_serialization_legacy_api.h @@ -79,24 +79,7 @@ wlan_serialization_get_pending_list_next_node_using_psoc( struct wlan_objmgr_psoc *psoc, struct wlan_serialization_command *prev_cmd, uint8_t is_cmd_for_pending_scan_queue); -/** - * wlan_serialization_get_active_list_next_node_using_psoc() - Return next - * scan or non-scan pending command from queue - * @psoc: pointer to psoc - * @prev_cmd: previous command given by caller, find next command after this - * @is_cmd_for_active_scan_queue: to find from active scan or non-scan queue - * - * This API finds the first active pdev, and loops through scan or non-scan - * pending queue (based on is_cmd_from_pending_scan_queue flag) and fetches - * next pending command after prev_cmd - * - * Return: pointer to serialization command - */ -struct wlan_serialization_command* -wlan_serialization_get_active_list_next_node_using_psoc( - struct wlan_objmgr_psoc *psoc, - struct wlan_serialization_command *prev_cmd, - uint8_t is_cmd_for_active_scan_queue); + /** * wlan_serialization_get_active_list_count() - Return Active list count * @psoc: pointer to soc diff --git a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/serialization/src/wlan_serialization_api.c b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/serialization/src/wlan_serialization_api.c index 73bb6c4905b1..996142d885f8 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/serialization/src/wlan_serialization_api.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/serialization/src/wlan_serialization_api.c @@ -147,26 +147,19 @@ wlan_serialization_deregister_comp_info_cb(struct wlan_objmgr_psoc *psoc, return QDF_STATUS_SUCCESS; } -enum wlan_serialization_cmd_status -wlan_serialization_non_scan_cmd_status(struct wlan_objmgr_pdev *pdev, - enum wlan_serialization_cmd_type cmd_id) -{ - serialization_enter(); - - return WLAN_SER_CMD_NOT_FOUND; -} - enum wlan_serialization_cmd_status wlan_serialization_cancel_request( struct wlan_serialization_queued_cmd_info *req) { QDF_STATUS status; - serialization_enter(); if (!req) { serialization_err("given request is empty"); return WLAN_SER_CMD_NOT_FOUND; } + serialization_debug("Type %d id %d requestor %d req type %d queue type %d", + req->cmd_type, req->cmd_id, req->requestor, + req->req_type, req->queue_type); status = wlan_serialization_validate_cmd(req->requestor, req->cmd_type); if (status != QDF_STATUS_SUCCESS) { serialization_err("req is not valid"); @@ -181,7 +174,6 @@ void wlan_serialization_remove_cmd( { QDF_STATUS status; - serialization_enter(); if (!cmd) { serialization_err("given request is empty"); QDF_ASSERT(0); @@ -211,16 +203,13 @@ wlan_serialization_request(struct wlan_serialization_command *cmd) struct wlan_objmgr_pdev *pdev = NULL; struct wlan_serialization_command_list *cmd_list = NULL; - serialization_enter(); if (!cmd) { serialization_err("serialization cmd is null"); return WLAN_SER_CMD_DENIED_UNSPECIFIED; } status = wlan_serialization_validate_cmd(cmd->source, cmd->cmd_type); - if (status != QDF_STATUS_SUCCESS) { - serialization_err("cmd is not valid"); + if (QDF_IS_STATUS_ERROR(status)) return WLAN_SER_CMD_DENIED_UNSPECIFIED; - } ser_soc_obj = wlan_serialization_get_psoc_obj(cmd); if (!ser_soc_obj) { @@ -284,19 +273,6 @@ wlan_serialization_vdev_scan_status(struct wlan_objmgr_vdev *vdev) cmd_in_active, cmd_in_pending); } -void wlan_serialization_flush_cmd( - struct wlan_serialization_queued_cmd_info *cmd) -{ - serialization_enter(); - if (!cmd) { - serialization_err("cmd is null, can't flush"); - return; - } - /* TODO: discuss and fill this API later */ - - return; -} - enum wlan_serialization_cmd_status wlan_serialization_pdev_scan_status(struct wlan_objmgr_pdev *pdev) { @@ -359,10 +335,8 @@ wlan_serialization_get_scan_cmd_using_scan_id( break; } if (wlan_serialization_match_cmd_scan_id(nnode, &cmd, scan_id, - vdev, ser_pdev_obj)) { - serialization_debug("Cmd matched with the scan_id"); + vdev, ser_pdev_obj)) break; - } } release_vdev_ref: wlan_objmgr_vdev_release_ref(vdev, WLAN_SERIALIZATION_ID); diff --git a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/serialization/src/wlan_serialization_dequeue.c b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/serialization/src/wlan_serialization_dequeue.c index d602730673a4..10602f21ef39 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/serialization/src/wlan_serialization_dequeue.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/serialization/src/wlan_serialization_dequeue.c @@ -49,16 +49,14 @@ void wlan_serialization_move_pending_to_active( pending_queue = &ser_pdev_obj->pending_scan_list; else pending_queue = &ser_pdev_obj->pending_list; - if (wlan_serialization_list_empty(pending_queue, ser_pdev_obj)) { - serialization_debug("nothing to move from pend to active que"); - serialization_debug("cmd_type - %d", cmd_type); + if (wlan_serialization_list_empty(pending_queue, ser_pdev_obj)) return; - } + list_peek_status = wlan_serialization_peek_front(pending_queue, &nnode, ser_pdev_obj); if (QDF_STATUS_SUCCESS != list_peek_status) { - serialization_err("can't read from pending queue"); - serialization_debug("cmd_type - %d", cmd_type); + serialization_err("can't read from pending queue cmd_type - %d", + cmd_type); return; } cmd_list = qdf_container_of(nnode, @@ -77,7 +75,7 @@ void wlan_serialization_move_pending_to_active( &active_cmd_list); if (WLAN_SER_CMD_ACTIVE != status) { serialization_err("Can't move cmd to activeQ id-%d type-%d", - cmd_list->cmd.cmd_id, cmd_list->cmd.cmd_type); + cmd_list->cmd.cmd_id, cmd_list->cmd.cmd_type); return; } else { /* @@ -91,11 +89,8 @@ void wlan_serialization_move_pending_to_active( */ if (!qdf_atomic_test_and_set_bit(CMD_MARKED_FOR_DELETE, &cmd_list->cmd_in_use)) { - serialization_debug("SER_CMD marked for removal"); wlan_serialization_put_back_to_global_list( pending_queue, ser_pdev_obj, cmd_list); - } else { - serialization_debug("SER_CMD already being deleted"); } wlan_serialization_activate_cmd(active_cmd_list, ser_pdev_obj); @@ -196,18 +191,21 @@ wlan_serialization_remove_all_cmd_from_queue(qdf_list_t *queue, status = WLAN_SER_CMD_NOT_FOUND; break; } - serialization_debug("SER_CMD marked for removal"); + /* * call pending cmd's callback to notify that * it is being removed */ if (cmd_list->cmd.cmd_cb) { /* caller should now do necessary clean up */ + serialization_debug("Cancel command: type %d id %d and Release memory", + cmd_list->cmd.cmd_type, + cmd_list->cmd.cmd_id); cmd_list->cmd.cmd_cb(&cmd_list->cmd, - WLAN_SER_CB_CANCEL_CMD); + WLAN_SER_CB_CANCEL_CMD); /* caller should release the memory */ cmd_list->cmd.cmd_cb(&cmd_list->cmd, - WLAN_SER_CB_RELEASE_MEM_CMD); + WLAN_SER_CB_RELEASE_MEM_CMD); } qdf_status = wlan_serialization_put_back_to_global_list(queue, @@ -278,8 +276,11 @@ static void wlan_serialization_remove_cmd_from_given_queue(qdf_list_t *queue, serialization_debug("SER_CMD already being deleted"); break; } - serialization_debug("SER_CMD marked for removal"); + if (cmd_list->cmd.cmd_cb) { + serialization_debug("Release memory for type %d id %d", + cmd_list->cmd.cmd_type, + cmd_list->cmd.cmd_id); /* caller should release the memory */ cmd_list->cmd.cmd_cb(&cmd_list->cmd, WLAN_SER_CB_RELEASE_MEM_CMD); @@ -337,10 +338,8 @@ wlan_serialization_remove_cmd_from_active_queue(struct wlan_objmgr_psoc *psoc, else queue = &ser_pdev_obj->active_list; - if (wlan_serialization_list_empty(queue, ser_pdev_obj)) { - serialization_err("Empty queue"); + if (wlan_serialization_list_empty(queue, ser_pdev_obj)) return; - } wlan_serialization_remove_cmd_from_given_queue(queue, cmd, ser_pdev_obj); @@ -386,10 +385,9 @@ wlan_serialization_remove_cmd_from_pending_queue(struct wlan_objmgr_psoc *psoc, else queue = &ser_pdev_obj->pending_list; - if (wlan_serialization_list_empty(queue, ser_pdev_obj)) { - serialization_err("Empty queue"); + if (wlan_serialization_list_empty(queue, ser_pdev_obj)) return; - } + wlan_serialization_remove_cmd_from_given_queue(queue, cmd, ser_pdev_obj); @@ -476,8 +474,9 @@ wlan_serialization_dequeue_cmd(struct wlan_serialization_command *cmd, serialization_err("ser_pdev_obj is empty"); return status; } - serialization_debug("command high_priority[%d] cmd_type[%d] cmd_id[%d]", - cmd->is_high_priority, cmd->cmd_type, cmd->cmd_id); + + serialization_debug("Type %d id %d active %d", cmd->cmd_type, + cmd->cmd_id, only_active_cmd); /* * Pass the copy of command, instead of actual command because * wlan_serialization_is_cmd_removed() api cleans the command @@ -503,8 +502,8 @@ wlan_serialization_dequeue_cmd(struct wlan_serialization_command *cmd, ser_pdev_obj); status = WLAN_SER_CMD_IN_ACTIVE_LIST; } else { - serialization_err("cmd_type[%d], cmd_id[%d], vdev[%pK]", - cmd->cmd_type, cmd->cmd_id, cmd->vdev); + serialization_err("cmd_type %d cmd_id %d not removed", + cmd->cmd_type, cmd->cmd_id); /* * if you come here means there is a possibility * that we couldn't find the command in active queue @@ -515,7 +514,6 @@ wlan_serialization_dequeue_cmd(struct wlan_serialization_command *cmd, QDF_ASSERT(0); status = WLAN_SER_CMD_NOT_FOUND; } - serialization_debug("Request to remove only from active queue"); return status; } qdf_mem_copy(&cmd_backup, cmd, @@ -645,7 +643,7 @@ wlan_serialization_find_and_cancel_cmd( QDF_STATUS wlan_serialization_find_and_remove_cmd( struct wlan_serialization_queued_cmd_info *cmd_info) { - struct wlan_serialization_command cmd; + struct wlan_serialization_command cmd ={0}; if (!cmd_info) { serialization_err("Invalid cmd_info"); @@ -657,7 +655,7 @@ QDF_STATUS wlan_serialization_find_and_remove_cmd( cmd.vdev = cmd_info->vdev; if (WLAN_SER_CMD_IN_ACTIVE_LIST != wlan_serialization_dequeue_cmd(&cmd, true)) { - serialization_err("Can't dequeue requested cmd_id[%d] type[%d]", + serialization_err("Can't dequeue requested cmd_id %d type %d", cmd_info->cmd_id, cmd_info->cmd_type); return QDF_STATUS_E_FAILURE; } diff --git a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/serialization/src/wlan_serialization_enqueue.c b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/serialization/src/wlan_serialization_enqueue.c index 0fe75915900e..ac6c667f6607 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/serialization/src/wlan_serialization_enqueue.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/serialization/src/wlan_serialization_enqueue.c @@ -45,8 +45,6 @@ wlan_serialization_add_cmd_to_given_queue(qdf_list_t *queue, serialization_err("Input arguments are not valid"); return WLAN_SER_CMD_DENIED_UNSPECIFIED; } - serialization_debug("add cmd cmd_id-%d type-%d", - cmd->cmd_id, cmd->cmd_type); if ((cmd->cmd_type < WLAN_SER_CMD_NONSCAN) && !wlan_serialization_is_scan_cmd_allowed(psoc, ser_pdev_obj)) { @@ -148,6 +146,9 @@ void wlan_serialization_activate_cmd( */ wlan_serialization_find_and_start_timer(psoc, &cmd_list->cmd); + + serialization_debug("Activate type %d id %d", cmd_list->cmd.cmd_type, + cmd_list->cmd.cmd_id); /* * Remember that serialization module may send * this callback in same context through which it @@ -257,8 +258,10 @@ wlan_serialization_enqueue_cmd(struct wlan_serialization_command *cmd, return status; } - serialization_debug("command high_priority[%d] cmd_type[%d] cmd_id[%d]", - cmd->is_high_priority, cmd->cmd_type, cmd->cmd_id); + serialization_debug("Type %d id %d high_priority %d timeout %d for active %d", + cmd->cmd_type, cmd->cmd_id, cmd->is_high_priority, + cmd->cmd_timeout_duration, is_cmd_for_active_queue); + if (cmd->cmd_type < WLAN_SER_CMD_NONSCAN) { if (is_cmd_for_active_queue) queue = &ser_pdev_obj->active_scan_list; @@ -273,7 +276,8 @@ wlan_serialization_enqueue_cmd(struct wlan_serialization_command *cmd, if (wlan_serialization_is_cmd_present_queue(cmd, is_cmd_for_active_queue)) { - serialization_err("duplicate command, can't enqueue"); + serialization_err("duplicate command Type %d id %d, can't enqueue", + cmd->cmd_type, cmd->cmd_id); return status; } diff --git a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/serialization/src/wlan_serialization_legacy_api.c b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/serialization/src/wlan_serialization_legacy_api.c index 8fe7af6c8987..3df4fc45cdf9 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/serialization/src/wlan_serialization_legacy_api.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/serialization/src/wlan_serialization_legacy_api.c @@ -147,10 +147,8 @@ wlan_serialization_peek_head_active_cmd_using_psoc( queue = &ser_pdev_obj->active_scan_list; else queue = &ser_pdev_obj->active_list; - if (wlan_serialization_list_empty(queue, ser_pdev_obj)) { - serialization_err("Empty Queue"); + if (wlan_serialization_list_empty(queue, ser_pdev_obj)) goto end; - } if (QDF_STATUS_SUCCESS != wlan_serialization_get_cmd_from_queue(queue, &nnode, ser_pdev_obj)) { @@ -161,8 +159,6 @@ wlan_serialization_peek_head_active_cmd_using_psoc( cmd_list = qdf_container_of(nnode, struct wlan_serialization_command_list, node); cmd = &cmd_list->cmd; - serialization_debug("cmd_type[%d], cmd_id[%d]", - cmd_list->cmd.cmd_type, cmd_list->cmd.cmd_id); end: return cmd; @@ -188,10 +184,8 @@ wlan_serialization_peek_head_pending_cmd_using_psoc( queue = &ser_pdev_obj->pending_scan_list; else queue = &ser_pdev_obj->pending_list; - if (wlan_serialization_list_empty(queue, ser_pdev_obj)) { - serialization_err("Empty Queue"); + if (wlan_serialization_list_empty(queue, ser_pdev_obj)) goto end; - } if (QDF_STATUS_SUCCESS != wlan_serialization_get_cmd_from_queue(queue, &nnode, ser_pdev_obj)) { @@ -201,7 +195,7 @@ wlan_serialization_peek_head_pending_cmd_using_psoc( cmd_list = qdf_container_of(nnode, struct wlan_serialization_command_list, node); cmd = &cmd_list->cmd; - serialization_debug("cmd_type[%d] cmd_id[%d]matched", + serialization_debug("cmd_type[%d] cmd_id[%d] matched", cmd_list->cmd.cmd_type, cmd_list->cmd.cmd_id); end: @@ -267,35 +261,6 @@ wlan_serialization_get_list_next_node(qdf_list_t *queue, return ret_cmd; } -struct wlan_serialization_command* -wlan_serialization_get_active_list_next_node_using_psoc( - struct wlan_objmgr_psoc *psoc, - struct wlan_serialization_command *prev_cmd, - uint8_t is_cmd_for_active_scan_queue) -{ - struct wlan_serialization_pdev_priv_obj *ser_pdev_obj; - qdf_list_t *queue; - - if (!prev_cmd) { - serialization_err("invalid prev_cmd"); - return NULL; - } - - ser_pdev_obj = wlan_serialization_get_pdev_priv_obj_using_psoc(psoc); - if (!ser_pdev_obj) { - serialization_err("invalid ser_pdev_obj"); - return NULL; - } - - if (is_cmd_for_active_scan_queue) - queue = &ser_pdev_obj->active_scan_list; - else - queue = &ser_pdev_obj->active_list; - - return wlan_serialization_get_list_next_node(queue, prev_cmd, - ser_pdev_obj); -} - struct wlan_serialization_command* wlan_serialization_get_pending_list_next_node_using_psoc( struct wlan_objmgr_psoc *psoc, diff --git a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/serialization/src/wlan_serialization_utils.c b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/serialization/src/wlan_serialization_utils.c index 3cf29951b3ae..95c0e850305e 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/serialization/src/wlan_serialization_utils.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/cmn_services/serialization/src/wlan_serialization_utils.c @@ -73,7 +73,6 @@ wlan_serialization_put_back_to_global_list(qdf_list_t *queue, serialization_err("can't put command back to global pool"); QDF_ASSERT(0); } - serialization_debug("cmd_id-%d, cmd_type-%d", cmd_id, cmd_type); return status; } @@ -190,7 +189,7 @@ static void wlan_serialization_generic_timer_callback(void *arg) if (cmd->vdev) vdev_id = wlan_vdev_get_id(cmd->vdev); - serialization_err("active cmd timeout for cmd_type[%d] vdev_id[%d]", + serialization_err("Active cmd timeout for cmd_type[%d] vdev_id[%d]", cmd->cmd_type, vdev_id); if (cmd->cmd_cb) @@ -311,10 +310,7 @@ wlan_serialization_find_and_stop_timer(struct wlan_objmgr_psoc *psoc, } wlan_serialization_release_lock(&psoc_ser_obj->timer_lock); - if (QDF_IS_STATUS_SUCCESS(status)) - serialization_debug("Stopped timer for cmd_type %d cmd id %d", - cmd->cmd_type, cmd->cmd_id); - else + if (QDF_IS_STATUS_ERROR(status)) serialization_err("can't find timer for cmd_type %d cmd_id %d", cmd->cmd_type, cmd->cmd_id); return status; @@ -376,8 +372,6 @@ wlan_serialization_find_and_start_timer(struct wlan_objmgr_psoc *psoc, QDF_ASSERT(0); return status; } - serialization_debug("Started timer for cmd: type[%d] id[%d]", - cmd->cmd_type, cmd->cmd_id); } else { serialization_err("Failed to start timer for cmd: type[%d] id[%d]", cmd->cmd_type, cmd->cmd_id); @@ -449,10 +443,8 @@ wlan_serialization_is_active_scan_cmd_allowed(struct wlan_objmgr_pdev *pdev) wlan_objmgr_iterate_obj_list(psoc, WLAN_PDEV_OP, wlan_serialization_active_scan_cmd_count_handler, &count, 1, WLAN_SERIALIZATION_ID); - if (count < ucfg_scan_get_max_active_scans(psoc)) { - serialization_debug("count is [%d]", count); + if (count < ucfg_scan_get_max_active_scans(psoc)) return true; - } return false; } @@ -543,10 +535,8 @@ wlan_serialization_is_scan_cmd_allowed(struct wlan_objmgr_psoc *psoc, QDF_STATUS wlan_serialization_validate_cmdtype( enum wlan_serialization_cmd_type cmd_type) { - serialization_debug("validate cmd_type:%d", cmd_type); - if (cmd_type < 0 || cmd_type >= WLAN_SER_CMD_MAX) { - serialization_err("Invalid cmd or comp passed"); + serialization_err("Invalid cmd %d passed", cmd_type); return QDF_STATUS_E_INVAL; } @@ -557,12 +547,10 @@ QDF_STATUS wlan_serialization_validate_cmd( enum wlan_umac_comp_id comp_id, enum wlan_serialization_cmd_type cmd_type) { - serialization_debug("validate cmd_type:%d, comp_id:%d", - cmd_type, comp_id); - if (cmd_type < 0 || comp_id < 0 || - cmd_type >= WLAN_SER_CMD_MAX || - comp_id >= WLAN_UMAC_COMP_ID_MAX) { - serialization_err("Invalid cmd or comp passed"); + if (cmd_type < 0 || comp_id < 0 || cmd_type >= WLAN_SER_CMD_MAX || + comp_id >= WLAN_UMAC_COMP_ID_MAX) { + serialization_err("Invalid cmd %d or comp %d passed", + cmd_type, comp_id); return QDF_STATUS_E_INVAL; } @@ -646,7 +634,6 @@ bool wlan_serialization_is_cmd_in_vdev_list(struct wlan_objmgr_vdev *vdev, if (!queuelen) { wlan_serialization_release_lock( &ser_pdev_obj->pdev_ser_list_lock); - serialization_debug("queue empty"); return false; } diff --git a/drivers/staging/qca-wifi-host-cmn/umac/cp_stats/dispatcher/inc/wlan_cp_stats_mc_defs.h b/drivers/staging/qca-wifi-host-cmn/umac/cp_stats/dispatcher/inc/wlan_cp_stats_mc_defs.h index 1ee5439b6b48..ff4cba3e84f9 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/cp_stats/dispatcher/inc/wlan_cp_stats_mc_defs.h +++ b/drivers/staging/qca-wifi-host-cmn/umac/cp_stats/dispatcher/inc/wlan_cp_stats_mc_defs.h @@ -175,10 +175,12 @@ struct cca_stats { * struct psoc_mc_cp_stats: psoc specific stats * @pending: details of pending requests * @wow_unspecified_wake_up_count: number of non-wow related wake ups + * @wow_stats: wake_lock stats for vdev */ struct psoc_mc_cp_stats { struct pending_stats_requests pending; uint32_t wow_unspecified_wake_up_count; + struct wake_lock_stats wow_stats; }; /** @@ -223,14 +225,12 @@ struct summary_stats { /** * struct vdev_mc_cp_stats - vdev specific stats - * @wow_stats: wake_lock stats for vdev * @cca: cca stats * @tx_rate_flags: tx rate flags (enum tx_rate_info) * @chain_rssi: chain rssi * @vdev_summary_stats: vdev's summary stats */ struct vdev_mc_cp_stats { - struct wake_lock_stats wow_stats; struct cca_stats cca; uint32_t tx_rate_flags; int8_t chain_rssi[MAX_NUM_CHAINS]; diff --git a/drivers/staging/qca-wifi-host-cmn/umac/cp_stats/dispatcher/inc/wlan_cp_stats_utils_api.h b/drivers/staging/qca-wifi-host-cmn/umac/cp_stats/dispatcher/inc/wlan_cp_stats_utils_api.h index 8bd51b1cdcb7..5c87de8e4738 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/cp_stats/dispatcher/inc/wlan_cp_stats_utils_api.h +++ b/drivers/staging/qca-wifi-host-cmn/umac/cp_stats/dispatcher/inc/wlan_cp_stats_utils_api.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2018,2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -34,7 +34,8 @@ QDF_TRACE_DEBUG(QDF_MODULE_ID_CP_STATS, ## args) #define cp_stats_err(args ...) \ QDF_TRACE_ERROR(QDF_MODULE_ID_CP_STATS, ## args) - +#define cp_stats_nofl_debug(args ...) \ + QDF_TRACE_DEBUG_NO_FL(QDF_MODULE_ID_CP_STATS, ## args) /** * enum wlan_cp_stats_cfg_state - State of Object configuration to * indicate whether object has to be attached/detached in cp stats diff --git a/drivers/staging/qca-wifi-host-cmn/umac/cp_stats/dispatcher/src/wlan_cp_stats_mc_tgt_api.c b/drivers/staging/qca-wifi-host-cmn/umac/cp_stats/dispatcher/src/wlan_cp_stats_mc_tgt_api.c index 085907f21f16..3b83dd31443e 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/cp_stats/dispatcher/src/wlan_cp_stats_mc_tgt_api.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/cp_stats/dispatcher/src/wlan_cp_stats_mc_tgt_api.c @@ -50,10 +50,8 @@ static void tgt_mc_cp_stats_extract_tx_power(struct wlan_objmgr_psoc *psoc, struct pdev_mc_cp_stats *pdev_mc_stats; struct pdev_cp_stats *pdev_cp_stats_priv; - if (!ev->pdev_stats) { - cp_stats_err("no pdev stats"); + if (!ev->pdev_stats) return; - } if (is_station_stats) status = ucfg_mc_cp_stats_get_pending_req(psoc, @@ -117,8 +115,8 @@ static void peer_rssi_iterator(struct wlan_objmgr_pdev *pdev, struct peer_cp_stats *peer_cp_stats_priv; if (WLAN_PEER_SELF == wlan_peer_get_peer_type(peer)) { - cp_stats_err("ignore self peer: %pM", - wlan_peer_get_macaddr(peer)); + cp_stats_debug("ignore self peer: %pM", + wlan_peer_get_macaddr(peer)); return; } @@ -304,9 +302,9 @@ tgt_mc_cp_stats_update_peer_stats(struct wlan_objmgr_psoc *psoc, if (peer_stats->peer_rssi) peer_mc_stats->peer_rssi = peer_stats->peer_rssi; - cp_stats_debug("peer_mac=%pM, tx_rate=%u, rx_rate=%u, peer_rssi=%u", - peer_mc_stats->peer_macaddr, peer_mc_stats->tx_rate, - peer_mc_stats->rx_rate, peer_mc_stats->peer_rssi); + cp_stats_nofl_debug("PEER STATS: peer_mac=%pM, tx_rate=%u, rx_rate=%u, peer_rssi=%d", + peer_mc_stats->peer_macaddr, peer_mc_stats->tx_rate, + peer_mc_stats->rx_rate, peer_mc_stats->peer_rssi); wlan_cp_stats_peer_obj_unlock(peer_cp_stats_priv); end: @@ -340,10 +338,8 @@ static void tgt_mc_cp_stats_extract_peer_stats(struct wlan_objmgr_psoc *psoc, return; } - if (!ev->peer_stats) { - cp_stats_debug("no peer stats"); + if (!ev->peer_stats) goto extd2_stats; - } selected = ev->num_peer_stats; for (i = 0; i < ev->num_peer_stats; i++) { @@ -369,10 +365,9 @@ static void tgt_mc_cp_stats_extract_peer_stats(struct wlan_objmgr_psoc *psoc, extd2_stats: - if (!ev->peer_adv_stats) { - cp_stats_err("no peer_extd2 stats"); + if (!ev->peer_adv_stats) goto complete; - } + selected = ev->num_peer_adv_stats; for (i = 0; i < ev->num_peer_adv_stats; i++) { status = tgt_mc_cp_stats_update_peer_adv_stats( @@ -452,10 +447,8 @@ static void tgt_mc_cp_stats_extract_vdev_summary_stats( struct peer_cp_stats *peer_cp_stats_priv; struct vdev_cp_stats *vdev_cp_stats_priv; - if (!ev->vdev_summary_stats) { - cp_stats_err("no summary stats"); + if (!ev->vdev_summary_stats) return; - } status = ucfg_mc_cp_stats_get_pending_req(psoc, TYPE_STATION_STATS, @@ -471,7 +464,7 @@ static void tgt_mc_cp_stats_extract_vdev_summary_stats( } if (i == ev->num_summary_stats) { - cp_stats_err("vdev_id %d not found", last_req.vdev_id); + cp_stats_debug("vdev_id %d not found", last_req.vdev_id); return; } @@ -530,10 +523,8 @@ static void tgt_mc_cp_stats_extract_vdev_chain_rssi_stats( struct vdev_mc_cp_stats *vdev_mc_stats; struct vdev_cp_stats *vdev_cp_stats_priv; - if (!ev->vdev_chain_rssi) { - cp_stats_err("no vdev chain rssi stats"); + if (!ev->vdev_chain_rssi) return; - } status = ucfg_mc_cp_stats_get_pending_req(psoc, TYPE_STATION_STATS, @@ -549,7 +540,7 @@ static void tgt_mc_cp_stats_extract_vdev_chain_rssi_stats( } if (i == ev->num_chain_rssi_stats) { - cp_stats_err("vdev_id %d not found", last_req.vdev_id); + cp_stats_debug("vdev_id %d not found", last_req.vdev_id); return; } diff --git a/drivers/staging/qca-wifi-host-cmn/umac/cp_stats/dispatcher/src/wlan_cp_stats_mc_ucfg_api.c b/drivers/staging/qca-wifi-host-cmn/umac/cp_stats/dispatcher/src/wlan_cp_stats_mc_ucfg_api.c index ff517bd047f2..7d1543749258 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/cp_stats/dispatcher/src/wlan_cp_stats_mc_ucfg_api.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/cp_stats/dispatcher/src/wlan_cp_stats_mc_ucfg_api.c @@ -115,28 +115,25 @@ QDF_STATUS ucfg_mc_cp_stats_inc_wake_lock_stats_by_protocol( uint8_t vdev_id, enum qdf_proto_subtype protocol) { - struct wlan_objmgr_vdev *vdev; struct wake_lock_stats *stats; - struct vdev_mc_cp_stats *vdev_mc_stats; - struct vdev_cp_stats *vdev_cp_stats_priv; + struct psoc_cp_stats *psoc_cp_stats_priv; + struct psoc_mc_cp_stats *psoc_mc_stats; - vdev = wlan_objmgr_get_vdev_by_id_from_psoc(psoc, vdev_id, - WLAN_CP_STATS_ID); - if (!vdev) { - cp_stats_err("vdev numm for vdev_id: %d", vdev_id); + psoc_cp_stats_priv = wlan_cp_stats_get_psoc_stats_obj(psoc); + if (!psoc_cp_stats_priv) { + cp_stats_err("psoc cp stats object is null"); return QDF_STATUS_E_NULL_VALUE; } - vdev_cp_stats_priv = wlan_cp_stats_get_vdev_stats_obj(vdev); - if (!vdev_cp_stats_priv) { - cp_stats_err("vdev cp stats object is null"); - wlan_objmgr_vdev_release_ref(vdev, WLAN_CP_STATS_ID); + wlan_cp_stats_psoc_obj_lock(psoc_cp_stats_priv); + psoc_mc_stats = psoc_cp_stats_priv->obj_stats; + + if (!psoc_mc_stats) { + cp_stats_err("psoc mc stats is null"); return QDF_STATUS_E_NULL_VALUE; } - wlan_cp_stats_vdev_obj_lock(vdev_cp_stats_priv); - vdev_mc_stats = vdev_cp_stats_priv->vdev_stats; - stats = &vdev_mc_stats->wow_stats; + stats = &psoc_mc_stats->wow_stats; switch (protocol) { case QDF_PROTO_ICMP_REQ: case QDF_PROTO_ICMP_RES: @@ -162,9 +159,8 @@ QDF_STATUS ucfg_mc_cp_stats_inc_wake_lock_stats_by_protocol( default: break; } + wlan_cp_stats_psoc_obj_unlock(psoc_cp_stats_priv); - wlan_cp_stats_vdev_obj_unlock(vdev_cp_stats_priv); - wlan_objmgr_vdev_release_ref(vdev, WLAN_CP_STATS_ID); return QDF_STATUS_SUCCESS; } @@ -172,28 +168,25 @@ QDF_STATUS ucfg_mc_cp_stats_inc_wake_lock_stats_by_dst_addr( struct wlan_objmgr_psoc *psoc, uint8_t vdev_id, uint8_t *dest_mac) { - struct wlan_objmgr_vdev *vdev; + struct psoc_cp_stats *psoc_cp_stats_priv; + struct psoc_mc_cp_stats *psoc_mc_stats; struct wake_lock_stats *stats; - struct vdev_mc_cp_stats *vdev_mc_stats; - struct vdev_cp_stats *vdev_cp_stats_priv; - vdev = wlan_objmgr_get_vdev_by_id_from_psoc(psoc, vdev_id, - WLAN_CP_STATS_ID); - if (!vdev) { - cp_stats_err("vdev numm for vdev_id: %d", vdev_id); + psoc_cp_stats_priv = wlan_cp_stats_get_psoc_stats_obj(psoc); + if (!psoc_cp_stats_priv) { + cp_stats_err("psoc cp stats object is null"); return QDF_STATUS_E_NULL_VALUE; } - vdev_cp_stats_priv = wlan_cp_stats_get_vdev_stats_obj(vdev); - if (!vdev_cp_stats_priv) { - cp_stats_err("vdev cp stats object is null"); - wlan_objmgr_vdev_release_ref(vdev, WLAN_CP_STATS_ID); + wlan_cp_stats_psoc_obj_lock(psoc_cp_stats_priv); + psoc_mc_stats = psoc_cp_stats_priv->obj_stats; + if (!psoc_mc_stats) { + cp_stats_err("psoc mc stats is null"); return QDF_STATUS_E_NULL_VALUE; } - wlan_cp_stats_vdev_obj_lock(vdev_cp_stats_priv); - vdev_mc_stats = vdev_cp_stats_priv->vdev_stats; - stats = &vdev_mc_stats->wow_stats; + stats = &psoc_mc_stats->wow_stats; + switch (*dest_mac) { case QDF_BCAST_MAC_ADDR: stats->bcast_wake_up_count++; @@ -208,9 +201,8 @@ QDF_STATUS ucfg_mc_cp_stats_inc_wake_lock_stats_by_dst_addr( stats->ucast_wake_up_count++; break; } + wlan_cp_stats_psoc_obj_unlock(psoc_cp_stats_priv); - wlan_cp_stats_vdev_obj_unlock(vdev_cp_stats_priv); - wlan_objmgr_vdev_release_ref(vdev, WLAN_CP_STATS_ID); return QDF_STATUS_SUCCESS; } @@ -220,11 +212,8 @@ QDF_STATUS ucfg_mc_cp_stats_inc_wake_lock_stats(struct wlan_objmgr_psoc *psoc, { struct wake_lock_stats *stats; QDF_STATUS status = QDF_STATUS_SUCCESS; - struct wlan_objmgr_vdev *vdev = NULL; struct psoc_mc_cp_stats *psoc_mc_stats; struct psoc_cp_stats *psoc_cp_stats_priv; - struct vdev_mc_cp_stats *vdev_mc_stats; - struct vdev_cp_stats *vdev_cp_stats_priv; psoc_cp_stats_priv = wlan_cp_stats_get_psoc_stats_obj(psoc); if (!psoc_cp_stats_priv) { @@ -232,35 +221,21 @@ QDF_STATUS ucfg_mc_cp_stats_inc_wake_lock_stats(struct wlan_objmgr_psoc *psoc, return QDF_STATUS_E_NULL_VALUE; } - vdev = wlan_objmgr_get_vdev_by_id_from_psoc(psoc, vdev_id, - WLAN_CP_STATS_ID); - if (!vdev) { - cp_stats_err("vdev numm for vdev_id: %d", vdev_id); - return QDF_STATUS_E_NULL_VALUE; - } + wlan_cp_stats_psoc_obj_lock(psoc_cp_stats_priv); - vdev_cp_stats_priv = wlan_cp_stats_get_vdev_stats_obj(vdev); - if (!vdev_cp_stats_priv) { - cp_stats_err("vdev cp stats object is null"); - status = QDF_STATUS_E_NULL_VALUE; - goto release_vdev_ref; + psoc_mc_stats = psoc_cp_stats_priv->obj_stats; + + if (!psoc_mc_stats) { + cp_stats_err("psoc mc stats is null"); + return QDF_STATUS_E_NULL_VALUE; } - wlan_cp_stats_psoc_obj_lock(psoc_cp_stats_priv); - wlan_cp_stats_vdev_obj_lock(vdev_cp_stats_priv); + stats = &psoc_mc_stats->wow_stats; - psoc_mc_stats = psoc_cp_stats_priv->obj_stats; - vdev_mc_stats = vdev_cp_stats_priv->vdev_stats; - stats = &vdev_mc_stats->wow_stats; status = tgt_mc_cp_stats_inc_wake_lock_stats(psoc, reason, stats, &psoc_mc_stats->wow_unspecified_wake_up_count); - wlan_cp_stats_vdev_obj_unlock(vdev_cp_stats_priv); wlan_cp_stats_psoc_obj_unlock(psoc_cp_stats_priv); -release_vdev_ref: - if (vdev) - wlan_objmgr_vdev_release_ref(vdev, WLAN_CP_STATS_ID); - return status; } @@ -276,18 +251,23 @@ static void vdev_iterator(struct wlan_objmgr_psoc *psoc, void *vdev, void *arg) { struct wake_lock_stats *vdev_stats; struct wake_lock_stats *stats = arg; - struct vdev_mc_cp_stats *vdev_mc_stats; - struct vdev_cp_stats *vdev_cp_stats_priv; + struct psoc_cp_stats *psoc_cp_stats_priv; + struct psoc_mc_cp_stats *psoc_mc_stats; - vdev_cp_stats_priv = wlan_cp_stats_get_vdev_stats_obj(vdev); - if (!vdev_cp_stats_priv) { - cp_stats_err("vdev cp stats object is null"); + psoc_cp_stats_priv = wlan_cp_stats_get_psoc_stats_obj(psoc); + if (!psoc_cp_stats_priv) { + cp_stats_err("psoc cp stats object is null"); return; } - wlan_cp_stats_vdev_obj_lock(vdev_cp_stats_priv); - vdev_mc_stats = vdev_cp_stats_priv->vdev_stats; - vdev_stats = &vdev_mc_stats->wow_stats; + psoc_mc_stats = psoc_cp_stats_priv->obj_stats; + if (!psoc_mc_stats) { + cp_stats_err("psoc mc stats is null"); + return; + } + + vdev_stats = &psoc_mc_stats->wow_stats; + stats->ucast_wake_up_count += vdev_stats->ucast_wake_up_count; stats->bcast_wake_up_count += vdev_stats->bcast_wake_up_count; stats->ipv4_mcast_wake_up_count += vdev_stats->ipv4_mcast_wake_up_count; @@ -308,7 +288,6 @@ static void vdev_iterator(struct wlan_objmgr_psoc *psoc, void *vdev, void *arg) vdev_stats->oem_response_wake_up_count; stats->pwr_save_fail_detected += vdev_stats->pwr_save_fail_detected; stats->scan_11d += vdev_stats->scan_11d; - wlan_cp_stats_vdev_obj_unlock(vdev_cp_stats_priv); } QDF_STATUS ucfg_mc_cp_stats_get_psoc_wake_lock_stats( @@ -338,19 +317,36 @@ QDF_STATUS ucfg_mc_cp_stats_get_vdev_wake_lock_stats( struct wlan_objmgr_vdev *vdev, struct wake_lock_stats *stats) { - struct vdev_cp_stats *vdev_cp_stats_priv; - struct vdev_mc_cp_stats *vdev_mc_stats; + struct wlan_objmgr_psoc *psoc; + struct psoc_cp_stats *psoc_cp_stats_priv; + struct psoc_mc_cp_stats *psoc_mc_stats; - vdev_cp_stats_priv = wlan_cp_stats_get_vdev_stats_obj(vdev); - if (!vdev_cp_stats_priv) { - cp_stats_err("vdev cp stats object is null"); + wlan_vdev_obj_lock(vdev); + psoc = wlan_vdev_get_psoc(vdev); + if (!psoc) { + wlan_vdev_obj_unlock(vdev); + cp_stats_err("psoc NULL"); + return QDF_STATUS_E_INVAL; + } + wlan_vdev_obj_unlock(vdev); + + psoc_cp_stats_priv = wlan_cp_stats_get_psoc_stats_obj(psoc); + if (!psoc_cp_stats_priv) { + cp_stats_err("psoc cp stats object is null"); return QDF_STATUS_E_NULL_VALUE; } - wlan_cp_stats_vdev_obj_lock(vdev_cp_stats_priv); - vdev_mc_stats = vdev_cp_stats_priv->vdev_stats; - qdf_mem_copy(stats, &vdev_mc_stats->wow_stats, sizeof(*stats)); - wlan_cp_stats_vdev_obj_unlock(vdev_cp_stats_priv); + wlan_cp_stats_psoc_obj_lock(psoc_cp_stats_priv); + psoc_mc_stats = psoc_cp_stats_priv->obj_stats; + + if (!psoc_mc_stats) { + cp_stats_err("psoc mc stats is null"); + return QDF_STATUS_E_NULL_VALUE; + } + + qdf_mem_copy(stats, &psoc_mc_stats->wow_stats, sizeof(*stats)); + + wlan_cp_stats_psoc_obj_unlock(psoc_cp_stats_priv); return QDF_STATUS_SUCCESS; } diff --git a/drivers/staging/qca-wifi-host-cmn/umac/global_umac_dispatcher/lmac_if/inc/wlan_lmac_if_def.h b/drivers/staging/qca-wifi-host-cmn/umac/global_umac_dispatcher/lmac_if/inc/wlan_lmac_if_def.h index 4b0d62fb9674..f5c0843bee8e 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/global_umac_dispatcher/lmac_if/inc/wlan_lmac_if_def.h +++ b/drivers/staging/qca-wifi-host-cmn/umac/global_umac_dispatcher/lmac_if/inc/wlan_lmac_if_def.h @@ -557,6 +557,9 @@ struct wlan_lmac_if_reg_tx_ops { struct wlan_objmgr_psoc *psoc, void *arg); QDF_STATUS (*unregister_ch_avoid_event_handler)( struct wlan_objmgr_psoc *psoc, void *arg); + + QDF_STATUS (*send_ctl_info)(struct wlan_objmgr_psoc *psoc, + struct reg_ctl_params *params); }; /** diff --git a/drivers/staging/qca-wifi-host-cmn/umac/nan/core/inc/nan_public_structs.h b/drivers/staging/qca-wifi-host-cmn/umac/nan/core/inc/nan_public_structs.h index 7f65d9ee33e9..6c96c652ee95 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/nan/core/inc/nan_public_structs.h +++ b/drivers/staging/qca-wifi-host-cmn/umac/nan/core/inc/nan_public_structs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -40,6 +40,7 @@ struct wlan_objmgr_vdev; #define NAN_PASSPHRASE_MIN_LEN 8 #define NAN_PASSPHRASE_MAX_LEN 63 #define NAN_CH_INFO_MAX_CHANNELS 4 +#define WLAN_WAIT_TIME_NDP_END 2000 /** * enum nan_datapath_msg_type - NDP msg type @@ -543,6 +544,17 @@ struct nan_datapath_confirm_event { uint8_t protocol; }; +/** + * struct nan_datapath_peer_ind - ndp peer indication + * @msg: msg received by FW + * @data_len: data length + * + */ +struct nan_dump_msg { + uint8_t *msg; + uint32_t data_len; +}; + /** * struct nan_datapath_indication_event - create ndp indication on the responder * @vdev: pointer to vdev object diff --git a/drivers/staging/qca-wifi-host-cmn/umac/nan/core/inc/wlan_nan_api.h b/drivers/staging/qca-wifi-host-cmn/umac/nan/core/inc/wlan_nan_api.h index 1498f23c37e1..7adb301cf783 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/nan/core/inc/wlan_nan_api.h +++ b/drivers/staging/qca-wifi-host-cmn/umac/nan/core/inc/wlan_nan_api.h @@ -41,6 +41,15 @@ QDF_STATUS nan_init(void); */ QDF_STATUS nan_deinit(void); +/** +* nan_is_ndp_active: is NAN peer attached to NDI +* @pdev: pointer to pdev object +* +* Return: ndp peer attached or not. +*/ + +bool nan_is_ndp_active(struct wlan_objmgr_pdev *pdev); + /** * nan_psoc_enable: psoc enable API for NANitioning component * @psoc: pointer to PSOC diff --git a/drivers/staging/qca-wifi-host-cmn/umac/nan/core/src/nan_api.c b/drivers/staging/qca-wifi-host-cmn/umac/nan/core/src/nan_api.c index 1e388110c4d1..592dadbb2f96 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/nan/core/src/nan_api.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/nan/core/src/nan_api.c @@ -29,6 +29,7 @@ #include "wlan_objmgr_psoc_obj.h" #include "wlan_objmgr_pdev_obj.h" #include "wlan_objmgr_vdev_obj.h" +#include "nan_ucfg_api.h" static QDF_STATUS nan_psoc_obj_created_notification( struct wlan_objmgr_psoc *psoc, void *arg_list) @@ -85,6 +86,40 @@ static QDF_STATUS nan_psoc_obj_destroyed_notification( return status; } +static void nan_is_ndp_peer_active(struct wlan_objmgr_pdev *pdev, + void *object, + void *arg) +{ + struct wlan_objmgr_vdev *vdev = (struct wlan_objmgr_vdev *)object; + uint8_t *flag = (uint8_t *)arg; + + wlan_vdev_obj_lock(vdev); + + if (wlan_vdev_mlme_get_opmode(vdev) != QDF_NDI_MODE) { + wlan_vdev_obj_unlock(vdev); + return; + } + + if (ucfg_nan_get_active_peers(vdev)) + *flag = true; + + wlan_vdev_obj_unlock(vdev); +} + +bool nan_is_ndp_active(struct wlan_objmgr_pdev *pdev) +{ + bool flag = false; + + if (!pdev) + return QDF_STATUS_E_INVAL; + + wlan_objmgr_pdev_iterate_obj_list(pdev, WLAN_VDEV_OP, + nan_is_ndp_peer_active, + &flag, 0, WLAN_NAN_ID); + + return flag; +} + static QDF_STATUS nan_vdev_obj_created_notification( struct wlan_objmgr_vdev *vdev, void *arg_list) { diff --git a/drivers/staging/qca-wifi-host-cmn/umac/nan/core/src/nan_main.c b/drivers/staging/qca-wifi-host-cmn/umac/nan/core/src/nan_main.c index e759d307c398..0fa7abf286a5 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/nan/core/src/nan_main.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/nan/core/src/nan_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -31,6 +31,7 @@ #include "wlan_objmgr_psoc_obj.h" #include "wlan_objmgr_pdev_obj.h" #include "wlan_objmgr_vdev_obj.h" +#include "wlan_osif_request_manager.h" struct nan_vdev_priv_obj *nan_get_vdev_priv_obj( struct wlan_objmgr_vdev *vdev) @@ -410,6 +411,7 @@ static QDF_STATUS nan_handle_end_ind( { struct wlan_objmgr_psoc *psoc; struct nan_psoc_priv_obj *psoc_nan_obj; + struct osif_request *request; psoc = wlan_vdev_get_psoc(ind->vdev); if (!psoc) { @@ -427,6 +429,13 @@ static QDF_STATUS nan_handle_end_ind( psoc_nan_obj->cb_obj.os_if_event_handler(psoc, ind->vdev, NDP_END_IND, ind); + /* Unblock the NDP_END wait */ + request = osif_request_get(psoc_nan_obj->request_context); + if (request) { + osif_request_complete(request); + osif_request_put(request); + } + return QDF_STATUS_SUCCESS; } diff --git a/drivers/staging/qca-wifi-host-cmn/umac/nan/core/src/nan_main_i.h b/drivers/staging/qca-wifi-host-cmn/umac/nan/core/src/nan_main_i.h index 7d2d770ce37c..562e9649f28a 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/nan/core/src/nan_main_i.h +++ b/drivers/staging/qca-wifi-host-cmn/umac/nan/core/src/nan_main_i.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2017 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2017, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -59,10 +59,12 @@ struct scheduler_msg; * struct nan_psoc_priv_obj - nan private psoc obj * @lock: lock to be acquired before reading or writing to object * @cb_obj: struct contaning callback pointers + * @request_context: NAN context to carry cookie for wait_for_complete */ struct nan_psoc_priv_obj { qdf_spinlock_t lock; struct nan_callbacks cb_obj; + void *request_context; }; /** diff --git a/drivers/staging/qca-wifi-host-cmn/umac/nan/dispatcher/inc/nan_ucfg_api.h b/drivers/staging/qca-wifi-host-cmn/umac/nan/dispatcher/inc/nan_ucfg_api.h index 2c24a483760c..92f2124311ae 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/nan/dispatcher/inc/nan_ucfg_api.h +++ b/drivers/staging/qca-wifi-host-cmn/umac/nan/dispatcher/inc/nan_ucfg_api.h @@ -43,6 +43,22 @@ struct nan_callbacks; QDF_STATUS ucfg_nan_set_ndi_state(struct wlan_objmgr_vdev *vdev, uint32_t state); +#ifdef WLAN_FEATURE_NAN_CONVERGENCE +/** + * wlan_nan_is_ndp_peer_active: check whether ndp peer is active or not + * @pdev: pdev object + * + * Return: ndp peer attached to ndi or not. + */ +bool wlan_nan_is_ndp_peer_active(struct wlan_objmgr_pdev *pdev); +#else +static inline +bool wlan_nan_is_ndp_peer_active(struct wlan_objmgr_pdev *pdev) +{ + return false; +} +#endif /* WLAN_FEATURE_NAN_CONVERGENCE */ + /** * ucfg_nan_get_ndi_state: get ndi state from vdev obj * @vdev: pointer to vdev object diff --git a/drivers/staging/qca-wifi-host-cmn/umac/nan/dispatcher/src/nan_ucfg_api.c b/drivers/staging/qca-wifi-host-cmn/umac/nan/dispatcher/src/nan_ucfg_api.c index 78dca19ce228..20e11776a1ba 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/nan/dispatcher/src/nan_ucfg_api.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/nan/dispatcher/src/nan_ucfg_api.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -27,6 +27,8 @@ #include "wlan_objmgr_psoc_obj.h" #include "wlan_objmgr_pdev_obj.h" #include "wlan_objmgr_vdev_obj.h" +#include "wlan_nan_api.h" +#include "wlan_osif_request_manager.h" struct wlan_objmgr_psoc; struct wlan_objmgr_vdev; @@ -47,6 +49,11 @@ inline QDF_STATUS ucfg_nan_set_ndi_state(struct wlan_objmgr_vdev *vdev, return QDF_STATUS_SUCCESS; } +bool wlan_nan_is_ndp_peer_active(struct wlan_objmgr_pdev *pdev) +{ + return nan_is_ndp_active(pdev); + +} inline enum nan_datapath_state ucfg_nan_get_ndi_state( struct wlan_objmgr_vdev *vdev) { @@ -308,6 +315,13 @@ QDF_STATUS ucfg_nan_req_processor(struct wlan_objmgr_vdev *vdev, uint32_t len; QDF_STATUS status; struct scheduler_msg msg = {0}; + int err; + struct nan_psoc_priv_obj *psoc_obj = NULL; + struct osif_request *request; + static const struct osif_request_params params = { + .priv_size = 0, + .timeout_ms = WLAN_WAIT_TIME_NDP_END, + }; if (!in_req) { nan_alert("req is null"); @@ -323,6 +337,11 @@ QDF_STATUS ucfg_nan_req_processor(struct wlan_objmgr_vdev *vdev, break; case NDP_END_REQ: len = sizeof(struct nan_datapath_end_req); + psoc_obj = nan_get_psoc_priv_obj(wlan_vdev_get_psoc(vdev)); + if (!psoc_obj) { + nan_err("nan psoc priv object is NULL"); + return QDF_STATUS_E_INVAL; + } break; default: nan_err("in correct message req type: %d", req_type); @@ -343,9 +362,31 @@ QDF_STATUS ucfg_nan_req_processor(struct wlan_objmgr_vdev *vdev, if (QDF_IS_STATUS_ERROR(status)) { nan_err("failed to post msg to NAN component, status: %d", status); + return status; } - return status; + if (req_type == NDP_END_REQ) { + /* Wait for NDP_END indication */ + if (!psoc_obj) { + nan_err("nan psoc priv object is NULL"); + return QDF_STATUS_E_INVAL; + } + request = osif_request_alloc(¶ms); + if (!request) { + nan_err("Request allocation failure"); + return QDF_STATUS_E_NOMEM; + } + psoc_obj->request_context = osif_request_cookie(request); + + nan_debug("Wait for NDP END indication"); + err = osif_request_wait_for_response(request); + if (err) + nan_err("NAN request timed out: %d", err); + osif_request_put(request); + psoc_obj->request_context = NULL; + } + + return QDF_STATUS_SUCCESS; } void ucfg_nan_event_handler(struct wlan_objmgr_psoc *psoc, diff --git a/drivers/staging/qca-wifi-host-cmn/umac/p2p/core/src/wlan_p2p_main.c b/drivers/staging/qca-wifi-host-cmn/umac/p2p/core/src/wlan_p2p_main.c index 0b082942da25..2b610b8c9338 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/p2p/core/src/wlan_p2p_main.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/p2p/core/src/wlan_p2p_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -514,10 +514,8 @@ static QDF_STATUS process_peer_for_noa(struct wlan_objmgr_vdev *vdev, } p2p_vdev_obj = wlan_objmgr_vdev_get_comp_private_obj(vdev, WLAN_UMAC_COMP_P2P); - if (!p2p_vdev_obj) { - p2p_err("p2p_vdev_obj:%pK", p2p_vdev_obj); + if (!p2p_vdev_obj) return QDF_STATUS_E_INVAL; - } mode = wlan_vdev_mlme_get_opmode(vdev); peer_type = wlan_peer_get_peer_type(peer); @@ -720,12 +718,6 @@ QDF_STATUS p2p_psoc_object_open(struct wlan_objmgr_psoc *soc) qdf_list_create(&p2p_soc_obj->tx_q_roc, MAX_QUEUE_LENGTH); qdf_list_create(&p2p_soc_obj->tx_q_ack, MAX_QUEUE_LENGTH); - status = qdf_event_create(&p2p_soc_obj->cancel_roc_done); - if (status != QDF_STATUS_SUCCESS) { - p2p_err("failed to create cancel roc done event"); - goto fail_cancel_roc; - } - status = qdf_event_create(&p2p_soc_obj->cleanup_roc_done); if (status != QDF_STATUS_SUCCESS) { p2p_err("failed to create cleanup roc done event"); @@ -750,9 +742,6 @@ QDF_STATUS p2p_psoc_object_open(struct wlan_objmgr_psoc *soc) qdf_event_destroy(&p2p_soc_obj->cleanup_roc_done); fail_cleanup_roc: - qdf_event_destroy(&p2p_soc_obj->cancel_roc_done); - -fail_cancel_roc: qdf_list_destroy(&p2p_soc_obj->tx_q_ack); qdf_list_destroy(&p2p_soc_obj->tx_q_roc); qdf_list_destroy(&p2p_soc_obj->roc_q); @@ -780,7 +769,6 @@ QDF_STATUS p2p_psoc_object_close(struct wlan_objmgr_psoc *soc) qdf_runtime_lock_deinit(&p2p_soc_obj->roc_runtime_lock); qdf_event_destroy(&p2p_soc_obj->cleanup_tx_done); qdf_event_destroy(&p2p_soc_obj->cleanup_roc_done); - qdf_event_destroy(&p2p_soc_obj->cancel_roc_done); qdf_list_destroy(&p2p_soc_obj->tx_q_ack); qdf_list_destroy(&p2p_soc_obj->tx_q_roc); qdf_list_destroy(&p2p_soc_obj->roc_q); @@ -1201,10 +1189,8 @@ void p2p_peer_authorized(struct wlan_objmgr_vdev *vdev, uint8_t *mac_addr) status = process_peer_for_noa(vdev, psoc, peer); wlan_objmgr_peer_release_ref(peer, WLAN_P2P_ID); - if (status != QDF_STATUS_SUCCESS) { - p2p_err("status:%u", status); + if (status != QDF_STATUS_SUCCESS) return; - } p2p_debug("peer is authorized"); } @@ -1281,16 +1267,12 @@ QDF_STATUS p2p_status_connect(struct wlan_objmgr_vdev *vdev) enum QDF_OPMODE mode; p2p_soc_obj = get_p2p_soc_obj_by_vdev(vdev); - if (!p2p_soc_obj) { - p2p_err("P2P soc context is NULL"); + if (!p2p_soc_obj) return QDF_STATUS_E_FAILURE; - } mode = wlan_vdev_mlme_get_opmode(vdev); - if (mode != QDF_P2P_CLIENT_MODE) { - p2p_debug("this is not P2P CLIENT, mode:%d", mode); + if (mode != QDF_P2P_CLIENT_MODE) return QDF_STATUS_SUCCESS; - } p2p_debug("connection status:%d", p2p_soc_obj->connection_status); switch (p2p_soc_obj->connection_status) { @@ -1329,10 +1311,8 @@ QDF_STATUS p2p_status_disconnect(struct wlan_objmgr_vdev *vdev) } mode = wlan_vdev_mlme_get_opmode(vdev); - if (mode != QDF_P2P_CLIENT_MODE) { - p2p_debug("this is not P2P CLIENT, mode:%d", mode); + if (mode != QDF_P2P_CLIENT_MODE) return QDF_STATUS_SUCCESS; - } p2p_debug("connection status:%d", p2p_soc_obj->connection_status); switch (p2p_soc_obj->connection_status) { diff --git a/drivers/staging/qca-wifi-host-cmn/umac/p2p/core/src/wlan_p2p_main.h b/drivers/staging/qca-wifi-host-cmn/umac/p2p/core/src/wlan_p2p_main.h index f1d62df14cb3..5a428bcf93a1 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/p2p/core/src/wlan_p2p_main.h +++ b/drivers/staging/qca-wifi-host-cmn/umac/p2p/core/src/wlan_p2p_main.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -53,6 +53,8 @@ p2p_logl(QDF_TRACE_LEVEL_FATAL, format, ## args) #define p2p_debug_rl(params...) \ QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_P2P, params) +#define p2p_info_rl(params...) \ + QDF_TRACE_INFO_RL(QDF_MODULE_ID_P2P, params) struct scheduler_msg; struct p2p_tx_cnf; @@ -205,7 +207,6 @@ struct p2p_soc_priv_obj { qdf_list_t tx_q_ack; wlan_scan_requester scan_req_id; struct p2p_start_param *start_param; - qdf_event_t cancel_roc_done; qdf_event_t cleanup_roc_done; qdf_event_t cleanup_tx_done; qdf_runtime_lock_t roc_runtime_lock; diff --git a/drivers/staging/qca-wifi-host-cmn/umac/p2p/core/src/wlan_p2p_off_chan_tx.c b/drivers/staging/qca-wifi-host-cmn/umac/p2p/core/src/wlan_p2p_off_chan_tx.c index 7937565aa646..82ac51aa1c13 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/p2p/core/src/wlan_p2p_off_chan_tx.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/p2p/core/src/wlan_p2p_off_chan_tx.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -536,6 +536,11 @@ static QDF_STATUS p2p_populate_mac_header( psoc = tx_ctx->p2p_soc_obj->soc; wh = (struct wlan_frame_hdr *)tx_ctx->buf; + /* + * Remove the WEP bit if already set, p2p_populate_rmf_field will set it + * if required. + */ + wh->i_fc[1] &= ~IEEE80211_FC1_WEP; mac_addr = wh->i_addr1; pdev_id = wlan_get_pdev_id_from_vdev_id(psoc, tx_ctx->vdev_id, WLAN_P2P_ID); @@ -767,7 +772,7 @@ static QDF_STATUS p2p_tx_update_connection_status( if (tx_frame_info->public_action_type != P2P_PUBLIC_ACTION_NOT_SUPPORT) - p2p_info("%s ---> OTA to " QDF_MAC_ADDR_STR, + p2p_debug("%s ---> OTA to " QDF_MAC_ADDR_STR, p2p_get_frame_type_str(tx_frame_info), QDF_MAC_ADDR_ARRAY(mac_to)); @@ -775,13 +780,13 @@ static QDF_STATUS p2p_tx_update_connection_status( P2P_PUBLIC_ACTION_PROV_DIS_REQ) && (p2p_soc_obj->connection_status == P2P_NOT_ACTIVE)) { p2p_soc_obj->connection_status = P2P_GO_NEG_PROCESS; - p2p_info("[P2P State]Inactive state to GO negotiation progress state"); + p2p_debug("[P2P State]Inactive state to GO negotiation progress state"); } else if ((tx_frame_info->public_action_type == P2P_PUBLIC_ACTION_NEG_CNF) && (p2p_soc_obj->connection_status == P2P_GO_NEG_PROCESS)) { p2p_soc_obj->connection_status = P2P_GO_NEG_COMPLETED; - p2p_info("[P2P State]GO nego progress to GO nego completed state"); + p2p_debug("[P2P State]GO nego progress to GO nego completed state"); } return QDF_STATUS_SUCCESS; @@ -1012,9 +1017,8 @@ static QDF_STATUS p2p_mgmt_tx(struct tx_action_context *tx_ctx, tx_ota_comp_cb = tgt_p2p_mgmt_ota_comp_cb; } - p2p_debug("length:%d, vdev_id:%d, chanfreq:%d, no_ack:%d", - mgmt_param.frm_len, mgmt_param.vdev_id, - mgmt_param.chanfreq, tx_ctx->no_ack); + p2p_debug("length:%d, chanfreq:%d", mgmt_param.frm_len, + mgmt_param.chanfreq); tx_ctx->nbuf = packet; @@ -1181,8 +1185,6 @@ static QDF_STATUS p2p_move_tx_context_to_ack_queue( struct tx_action_context *cur_tx_ctx; QDF_STATUS status; - p2p_debug("move tx context to wait for roc queue, %pK", tx_ctx); - cur_tx_ctx = p2p_find_tx_ctx(p2p_soc_obj, (uintptr_t)tx_ctx, &is_roc_q, &is_ack_q); if (cur_tx_ctx) { @@ -1206,8 +1208,6 @@ static QDF_STATUS p2p_move_tx_context_to_ack_queue( &tx_ctx->node); if (status != QDF_STATUS_SUCCESS) p2p_err("Failed to insert off chan tx context to wait ack req queue"); - p2p_debug("insert tx context to wait for ack queue, status:%d", - status); return status; } @@ -1354,18 +1354,38 @@ static QDF_STATUS p2p_remove_tx_context( */ static void p2p_tx_timeout(void *pdata) { - struct tx_action_context *tx_ctx = pdata; + QDF_STATUS status, ret; + qdf_list_node_t *p_node; + struct tx_action_context *tx_ctx; + struct p2p_soc_priv_obj *p2p_soc_obj; p2p_info("pdata:%pK", pdata); - - if (!tx_ctx || !(tx_ctx->p2p_soc_obj)) { - p2p_err("invalid tx context or p2p soc object"); + p2p_soc_obj = (struct p2p_soc_priv_obj *)pdata; + if (!p2p_soc_obj) { + p2p_err("null p2p psoc obj"); return; } - qdf_mc_timer_destroy(&tx_ctx->tx_timer); - p2p_send_tx_conf(tx_ctx, false); - p2p_remove_tx_context(tx_ctx); + status = qdf_list_peek_front(&p2p_soc_obj->tx_q_ack, &p_node); + while (QDF_IS_STATUS_SUCCESS(status)) { + tx_ctx = qdf_container_of(p_node, + struct tx_action_context, node); + status = qdf_list_peek_next(&p2p_soc_obj->tx_q_ack, + p_node, &p_node); + if (QDF_TIMER_STATE_STOPPED == + qdf_mc_timer_get_current_state(&tx_ctx->tx_timer)) { + ret = qdf_list_remove_node(&p2p_soc_obj->tx_q_ack, + &tx_ctx->node); + if (ret == QDF_STATUS_SUCCESS) { + qdf_mc_timer_destroy(&tx_ctx->tx_timer); + p2p_send_tx_conf(tx_ctx, false); + qdf_mem_free(tx_ctx->buf); + qdf_mem_free(tx_ctx); + } else + p2p_err("remove %pK from roc_q fail", + tx_ctx); + } + } } /** @@ -1380,20 +1400,18 @@ static QDF_STATUS p2p_enable_tx_timer(struct tx_action_context *tx_ctx) { QDF_STATUS status; - p2p_debug("tx context:%pK", tx_ctx); - status = qdf_mc_timer_init(&tx_ctx->tx_timer, - QDF_TIMER_TYPE_SW, p2p_tx_timeout, - tx_ctx); + QDF_TIMER_TYPE_SW, p2p_tx_timeout, + tx_ctx->p2p_soc_obj); if (status != QDF_STATUS_SUCCESS) { - p2p_err("failed to init tx timer"); + p2p_err("failed to init tx timer tx_ctx:%pK", tx_ctx); return status; } status = qdf_mc_timer_start(&tx_ctx->tx_timer, - P2P_ACTION_FRAME_TX_TIMEOUT); + P2P_ACTION_FRAME_TX_TIMEOUT); if (status != QDF_STATUS_SUCCESS) - p2p_err("tx timer start failed"); + p2p_err("tx timer start failed tx_ctx:%pK", tx_ctx); return status; } @@ -1477,6 +1495,7 @@ static QDF_STATUS p2p_populate_rmf_field(struct tx_action_context *tx_ctx, uint8_t *frame; uint32_t frame_len; struct p2p_soc_priv_obj *p2p_soc_obj; + uint8_t action_category; p2p_soc_obj = tx_ctx->p2p_soc_obj; @@ -1491,8 +1510,14 @@ static QDF_STATUS p2p_populate_rmf_field(struct tx_action_context *tx_ctx, wh = (struct wlan_frame_hdr *)(*ppbuf); action_hdr = (struct action_frm_hdr *)(*ppbuf + sizeof(*wh)); - if (!is_rmf_mgmt_action_frame(action_hdr->action_category)) { - p2p_debug("non rmf act frame 0x%x cat %x", + /* + * For Action frame which are not handled, the resp is sent back to the + * source without change, except that MSB of the Category set to 1, so + * to get the actual action category we need to ignore the MSB. + */ + action_category = action_hdr->action_category & 0x7f; + if (!is_rmf_mgmt_action_frame(action_category)) { + p2p_debug("non rmf act frame 0x%x category %x", tx_ctx->frame_info.sub_type, action_hdr->action_category); return QDF_STATUS_SUCCESS; @@ -2866,8 +2891,6 @@ QDF_STATUS p2p_process_mgmt_tx_cancel( return QDF_STATUS_SUCCESS; } - p2p_debug("cookie:0x%llx", cancel_tx->cookie); - cur_tx_ctx = p2p_find_tx_ctx(cancel_tx->p2p_soc_obj, cancel_tx->cookie, &is_roc_q, &is_ack_q); if (cur_tx_ctx) { diff --git a/drivers/staging/qca-wifi-host-cmn/umac/p2p/core/src/wlan_p2p_roc.c b/drivers/staging/qca-wifi-host-cmn/umac/p2p/core/src/wlan_p2p_roc.c index 6f138083756b..85eab4a1c93a 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/p2p/core/src/wlan_p2p_roc.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/p2p/core/src/wlan_p2p_roc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -129,8 +129,8 @@ static QDF_STATUS p2p_scan_start(struct p2p_roc_context *roc_ctx) if (req->scan_req.dwell_time_passive > P2P_MAX_ROC_DURATION) req->scan_req.dwell_time_passive = P2P_MAX_ROC_DURATION; } - p2p_debug("FW requested roc duration is:%d for chan: %d", - req->scan_req.dwell_time_passive, roc_ctx->chan); + p2p_debug("FW requested roc duration is:%d", + req->scan_req.dwell_time_passive); status = ucfg_scan_start(req); @@ -227,10 +227,8 @@ static QDF_STATUS p2p_send_roc_event( p2p_evt.chan = roc_ctx->chan; p2p_evt.duration = roc_ctx->duration; - p2p_debug("p2p soc_obj:%pK, roc_ctx:%pK, vdev_id:%d, roc_event:" - "%d, cookie:%llx, chan:%d, duration:%d", p2p_soc_obj, - roc_ctx, p2p_evt.vdev_id, p2p_evt.roc_event, - p2p_evt.cookie, p2p_evt.chan, p2p_evt.duration); + p2p_debug("roc_event: %d, cookie:%llx", p2p_evt.roc_event, + p2p_evt.cookie); start_param->event_cb(start_param->event_cb_data, &p2p_evt); @@ -253,8 +251,9 @@ static QDF_STATUS p2p_destroy_roc_ctx(struct p2p_roc_context *roc_ctx, QDF_STATUS status = QDF_STATUS_SUCCESS; struct p2p_soc_priv_obj *p2p_soc_obj = roc_ctx->p2p_soc_obj; - p2p_debug("p2p_soc_obj:%pK, roc_ctx:%pK, up_layer_event:%d, in_roc_queue:%d", - p2p_soc_obj, roc_ctx, up_layer_event, in_roc_queue); + p2p_debug("p2p_soc_obj:%pK, roc_ctx:%pK, up_layer_event:%d, in_roc_queue:%d, vdev_id:%d, chan:%d, duration:%d", + p2p_soc_obj, roc_ctx, up_layer_event, in_roc_queue, + roc_ctx->vdev_id, roc_ctx->chan, roc_ctx->duration); if (up_layer_event) { if (roc_ctx->roc_state < ROC_STATE_ON_CHAN) @@ -290,14 +289,9 @@ static QDF_STATUS p2p_execute_cancel_roc_req( QDF_STATUS status; struct p2p_soc_priv_obj *p2p_soc_obj = roc_ctx->p2p_soc_obj; - p2p_debug("p2p soc obj:%pK, roc ctx:%pK, vdev_id:%d, scan_id:%d, tx ctx:%pK, chan:%d, phy_mode:%d, duration:%d, roc_type:%d, roc_state:%d", - p2p_soc_obj, roc_ctx, roc_ctx->vdev_id, - roc_ctx->scan_id, roc_ctx->tx_ctx, roc_ctx->chan, - roc_ctx->phy_mode, roc_ctx->duration, - roc_ctx->roc_type, roc_ctx->roc_state); + p2p_debug("p2p execute cancel roc req"); roc_ctx->roc_state = ROC_STATE_CANCEL_IN_PROG; - qdf_event_reset(&p2p_soc_obj->cancel_roc_done); status = qdf_mc_timer_stop_sync(&roc_ctx->roc_timer); if (status != QDF_STATUS_SUCCESS) p2p_err("Failed to stop roc timer, roc %pK", roc_ctx); @@ -309,7 +303,7 @@ static QDF_STATUS p2p_execute_cancel_roc_req( qdf_mc_timer_destroy(&roc_ctx->roc_timer); p2p_mgmt_rx_ops(p2p_soc_obj->soc, false); p2p_destroy_roc_ctx(roc_ctx, true, true); - qdf_event_set(&p2p_soc_obj->cancel_roc_done); + return status; } @@ -457,8 +451,7 @@ static QDF_STATUS p2p_process_scan_start_evt( struct p2p_roc_context *roc_ctx) { roc_ctx->roc_state = ROC_STATE_STARTED; - p2p_debug("scan started, roc ctx:%pK, scan id:%d", - roc_ctx, roc_ctx->scan_id); + p2p_debug("scan started, scan id:%d", roc_ctx->scan_id); return QDF_STATUS_SUCCESS; } @@ -483,11 +476,8 @@ static QDF_STATUS p2p_process_ready_on_channel_evt( p2p_soc_obj = roc_ctx->p2p_soc_obj; roc_ctx->roc_state = ROC_STATE_ON_CHAN; - p2p_debug("p2p soc obj:%pK, roc ctx:%pK, vdev_id:%d, scan_id:%d, tx ctx:%pK, chan:%d, phy_mode:%d, duration:%d, roc_type:%d, roc_state:%d", - p2p_soc_obj, roc_ctx, roc_ctx->vdev_id, - roc_ctx->scan_id, roc_ctx->tx_ctx, roc_ctx->chan, - roc_ctx->phy_mode, roc_ctx->duration, - roc_ctx->roc_type, roc_ctx->roc_state); + p2p_debug("scan_id:%d, roc_state:%d", roc_ctx->scan_id, + roc_ctx->roc_state); status = qdf_mc_timer_start(&roc_ctx->roc_timer, (roc_ctx->duration + P2P_EVENT_PROPAGATE_TIME)); @@ -522,11 +512,7 @@ static QDF_STATUS p2p_process_scan_complete_evt( uint32_t size; struct p2p_soc_priv_obj *p2p_soc_obj = roc_ctx->p2p_soc_obj; - p2p_debug("p2p soc obj:%pK, roc ctx:%pK, vdev_id:%d, scan_id:%d, tx ctx:%pK, chan:%d, phy_mode:%d, duration:%d, roc_type:%d, roc_state:%d", - p2p_soc_obj, roc_ctx, roc_ctx->vdev_id, - roc_ctx->scan_id, roc_ctx->tx_ctx, roc_ctx->chan, - roc_ctx->phy_mode, roc_ctx->duration, - roc_ctx->roc_type, roc_ctx->roc_state); + p2p_debug("vdev_id:%d, scan_id:%d", roc_ctx->vdev_id, roc_ctx->scan_id); /* allow runtime suspend */ qdf_runtime_pm_allow_suspend(&p2p_soc_obj->roc_runtime_lock); @@ -549,7 +535,7 @@ static QDF_STATUS p2p_process_scan_complete_evt( ROC_EVENT_COMPLETED); p2p_destroy_roc_ctx(roc_ctx, false, true); - qdf_event_set(&p2p_soc_obj->cancel_roc_done); + qdf_event_set(&p2p_soc_obj->cleanup_roc_done); size = qdf_list_size(&p2p_soc_obj->roc_q); p2p_debug("P2P roc queue size is %d", status); @@ -749,6 +735,7 @@ QDF_STATUS p2p_process_cleanup_roc_queue( struct p2p_cleanup_param *param) { uint32_t vdev_id; + uint8_t count = 0; QDF_STATUS status, ret; struct p2p_roc_context *roc_ctx; qdf_list_node_t *p_node; @@ -812,14 +799,13 @@ QDF_STATUS p2p_process_cleanup_roc_queue( ROC_STATE_CANCEL_IN_PROG) p2p_execute_cancel_roc_req(roc_ctx); - ret = qdf_wait_single_event( - &p2p_soc_obj->cancel_roc_done, - P2P_WAIT_CANCEL_ROC); - p2p_debug("RoC cancellation done, return:%d", ret); + count++; } } - qdf_event_set(&p2p_soc_obj->cleanup_roc_done); + p2p_debug("count %d", count); + if (!count) + qdf_event_set(&p2p_soc_obj->cleanup_roc_done); return QDF_STATUS_SUCCESS; } @@ -869,15 +855,16 @@ QDF_STATUS p2p_process_cancel_roc_req( curr_roc_ctx = p2p_find_roc_ctx(p2p_soc_obj, cancel_roc_ctx->cookie); - p2p_debug("p2p soc obj:%pK, cookie:%llx, roc ctx:%pK", - p2p_soc_obj, cancel_roc_ctx->cookie, curr_roc_ctx); - if (!curr_roc_ctx) { p2p_debug("Failed to find roc req by cookie, cookie %llx", cancel_roc_ctx->cookie); return QDF_STATUS_E_INVAL; } + p2p_debug("roc ctx:%pK vdev_id:%d, scan_id:%d, roc_type:%d, roc_state:%d", + curr_roc_ctx, curr_roc_ctx->vdev_id, curr_roc_ctx->scan_id, + curr_roc_ctx->roc_type, curr_roc_ctx->roc_state); + if (curr_roc_ctx->roc_state == ROC_STATE_IDLE) { status = p2p_destroy_roc_ctx(curr_roc_ctx, true, true); } else if (curr_roc_ctx->roc_state == diff --git a/drivers/staging/qca-wifi-host-cmn/umac/p2p/dispatcher/src/wlan_p2p_ucfg_api.c b/drivers/staging/qca-wifi-host-cmn/umac/p2p/dispatcher/src/wlan_p2p_ucfg_api.c index 56fe7dba2d72..93d5ae1561b7 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/p2p/dispatcher/src/wlan_p2p_ucfg_api.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/p2p/dispatcher/src/wlan_p2p_ucfg_api.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -199,15 +199,13 @@ QDF_STATUS ucfg_p2p_roc_cancel_req(struct wlan_objmgr_psoc *soc, status = qdf_idr_find(&p2p_soc_obj->p2p_idr, cookie, &roc_ctx); if (QDF_IS_STATUS_ERROR(status)) { - p2p_err("invalid id for cookie 0x%llx", cookie); + p2p_debug("invalid id for cookie 0x%llx", cookie); return QDF_STATUS_E_INVAL; } cancel_roc = qdf_mem_malloc(sizeof(*cancel_roc)); - if (!cancel_roc) { - p2p_err("failed to allocate cancel p2p roc"); + if (!cancel_roc) return QDF_STATUS_E_NOMEM; - } cancel_roc->p2p_soc_obj = p2p_soc_obj; cancel_roc->cookie = (uintptr_t)roc_ctx; @@ -235,7 +233,7 @@ QDF_STATUS ucfg_p2p_cleanup_roc_by_vdev(struct wlan_objmgr_vdev *vdev) p2p_debug("vdev:%pK", vdev); if (!vdev) { - p2p_err("null vdev"); + p2p_debug("null vdev"); return QDF_STATUS_E_INVAL; } @@ -279,7 +277,7 @@ QDF_STATUS ucfg_p2p_cleanup_tx_by_vdev(struct wlan_objmgr_vdev *vdev) struct wlan_objmgr_psoc *psoc; if (!vdev) { - p2p_err("null vdev"); + p2p_debug("null vdev"); return QDF_STATUS_E_INVAL; } diff --git a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_db.c b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_db.c index eb07f980d233..68f98e89ab31 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_db.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_db.c @@ -20,7 +20,7 @@ /** * DOC: reg_db.c * This file implements QCA regulatory database. - * Current implementation conforms to database version 29. + * Current implementation conforms to database version 30. */ #include @@ -267,6 +267,7 @@ enum reg_domain { APL1_ETSIC = 0x55, APL2_WORLD = 0x45, APL2_ETSIC = 0x56, + APL2_ETSID = 0x41, APL4_WORLD = 0x42, APL6_WORLD = 0x5B, APL8_WORLD = 0x5D, @@ -280,10 +281,13 @@ enum reg_domain { APL14_WORLD = 0x57, APL15_WORLD = 0x59, APL16_WORLD = 0x70, + APL16_ETSIC = 0x6D, + APL17_ETSIC = 0xE7, APL17_ETSID = 0xE0, APL19_ETSIC = 0x71, APL20_WORLD = 0xE5, APL23_WORLD = 0xE3, + APL24_ETSIC = 0xE2, MKK3_MKKC = 0x82, MKK5_MKKA = 0x99, @@ -316,7 +320,7 @@ const struct country_code_to_reg_domain g_all_countries[] = { {CTRY_ANDORRA, ETSI3_WORLD, "AD", 40, 160, 0}, {CTRY_ANGUILLA, ETSI1_WORLD, "AI", 40, 160, 0}, {CTRY_ANTIGUA_AND_BARBUDA, ETSI1_WORLD, "AG", 40, 160, 0}, - {CTRY_ARGENTINA, APL16_WORLD, "AR", 40, 160, 0}, + {CTRY_ARGENTINA, APL16_ETSIC, "AR", 40, 160, 0}, {CTRY_ARMENIA, ETSI4_WORLD, "AM", 40, 20, 0}, {CTRY_ARUBA, ETSI1_WORLD, "AW", 40, 160, 0}, {CTRY_AUSTRALIA, FCC6_WORLD, "AU", 40, 160, 0}, @@ -388,7 +392,7 @@ const struct country_code_to_reg_domain g_all_countries[] = { {CTRY_HUNGARY, ETSI1_WORLD, "HU", 40, 160, 0}, {CTRY_ICELAND, ETSI1_WORLD, "IS", 40, 160, 0}, {CTRY_INDIA, APL19_ETSIC, "IN", 40, 160, 0}, - {CTRY_INDONESIA, APL2_ETSIC, "ID", 40, 20, 0}, + {CTRY_INDONESIA, APL2_ETSID, "ID", 40, 80, 0}, {CTRY_IRAQ, ETSI1_WORLD, "IQ", 40, 160, 0}, {CTRY_IRELAND, ETSI1_WORLD, "IE", 40, 160, 0}, {CTRY_ISLE_OF_MAN, ETSI1_WORLD, "IM", 40, 160, 0}, @@ -520,7 +524,7 @@ const struct country_code_to_reg_domain g_all_countries[] = { {CTRY_ANDORRA, ETSI3_WORLD, "AD", 40, 160, 0}, {CTRY_ANGUILLA, ETSI1_WORLD, "AI", 40, 160, 0}, {CTRY_ANTIGUA_AND_BARBUDA, ETSI10_WORLD, "AG", 40, 160, 0}, - {CTRY_ARGENTINA, APL17_ETSID, "AR", 40, 160, 0}, + {CTRY_ARGENTINA, APL17_ETSIC, "AR", 40, 160, 0}, {CTRY_ARMENIA, ETSI4_WORLD, "AM", 40, 20, 0}, {CTRY_ARUBA, ETSI1_WORLD, "AW", 40, 160, 0}, {CTRY_AUSTRALIA, FCC6_WORLD, "AU", 40, 160, 0}, @@ -592,7 +596,7 @@ const struct country_code_to_reg_domain g_all_countries[] = { {CTRY_HUNGARY, ETSI10_WORLD, "HU", 40, 160, 0}, {CTRY_ICELAND, ETSI10_WORLD, "IS", 40, 160, 0}, {CTRY_INDIA, APL15_WORLD, "IN", 40, 160, 0}, - {CTRY_INDONESIA, APL2_ETSIC, "ID", 40, 20, 0}, + {CTRY_INDONESIA, APL2_ETSID, "ID", 40, 80, 0}, {CTRY_IRAQ, ETSI1_WORLD, "IQ", 40, 160, 0}, {CTRY_IRELAND, ETSI10_WORLD, "IE", 40, 160, 0}, {CTRY_ISLE_OF_MAN, ETSI10_WORLD, "IM", 40, 160, 0}, @@ -723,7 +727,7 @@ const struct country_code_to_reg_domain g_all_countries[] = { {CTRY_ANDORRA, ETSI3_WORLD, "AD", 40, 160, 0}, {CTRY_ANGUILLA, ETSI1_WORLD, "AI", 40, 160, 0}, {CTRY_ANTIGUA_AND_BARBUDA, ETSI13_WORLD, "AG", 40, 160, 0}, - {CTRY_ARGENTINA, APL17_ETSID, "AR", 40, 160, 0}, + {CTRY_ARGENTINA, APL17_ETSIC, "AR", 40, 160, 0}, {CTRY_ARMENIA, ETSI4_WORLD, "AM", 40, 20, 0}, {CTRY_ARUBA, ETSI1_WORLD, "AW", 40, 160, 0}, {CTRY_AUSTRALIA, FCC6_WORLD, "AU", 40, 160, 0}, @@ -795,7 +799,7 @@ const struct country_code_to_reg_domain g_all_countries[] = { {CTRY_HUNGARY, ETSI13_WORLD, "HU", 40, 160, 0}, {CTRY_ICELAND, ETSI13_WORLD, "IS", 40, 160, 0}, {CTRY_INDIA, APL19_ETSIC, "IN", 40, 160, 0}, - {CTRY_INDONESIA, APL2_ETSIC, "ID", 40, 20, 0}, + {CTRY_INDONESIA, APL2_ETSID, "ID", 40, 80, 0}, {CTRY_IRAQ, ETSI1_WORLD, "IQ", 40, 160, 0}, {CTRY_IRELAND, ETSI13_WORLD, "IE", 40, 160, 0}, {CTRY_ISLE_OF_MAN, ETSI13_WORLD, "IM", 40, 160, 0}, @@ -931,6 +935,8 @@ enum reg_domains_2g { WORLD_2G_1, WORLD_2G_2, WORLD_2G_3, + + REG_DOMAINS_2G_MAX, }; enum reg_domains_5g { @@ -974,6 +980,7 @@ enum reg_domains_5g { APL19, APL20, APL23, + APL24, MKK3, MKK4, MKK5, @@ -984,8 +991,9 @@ enum reg_domains_5g { MKK17, WORLD_5G_1, WORLD_5G_2, -}; + REG_DOMAINS_5G_MAX, +}; const struct reg_domain_pair g_reg_dmn_pairs[] = { {NULL1_WORLD, NULL1, WORLD}, @@ -1024,6 +1032,7 @@ const struct reg_domain_pair g_reg_dmn_pairs[] = { {APL1_ETSIC, APL1, ETSIC}, {APL2_WORLD, APL2, WORLD}, {APL2_ETSIC, APL2, ETSIC}, + {APL2_ETSID, APL2, ETSID}, {APL4_WORLD, APL4, WORLD}, {APL6_WORLD, APL6, WORLD}, {APL8_WORLD, APL8, WORLD}, @@ -1037,10 +1046,13 @@ const struct reg_domain_pair g_reg_dmn_pairs[] = { {APL14_WORLD, APL14, WORLD}, {APL15_WORLD, APL15, WORLD}, {APL16_WORLD, APL16, WORLD}, + {APL16_ETSIC, APL16, ETSIC}, + {APL17_ETSIC, APL17, ETSIC}, {APL17_ETSID, APL17, ETSID}, {APL19_ETSIC, APL19, ETSIC}, {APL20_WORLD, APL20, WORLD}, {APL23_WORLD, APL23, WORLD}, + {APL24_ETSIC, APL24, ETSIC}, {MKK3_MKKC, MKK3, MKKC}, {MKK5_MKKA, MKK5, MKKA}, @@ -1072,6 +1084,7 @@ enum reg_rules_2g { CHAN_1_13_2, CHAN_1_13_3, CHAN_1_13_4, + CHAN_1_13_5, CHAN_12_12_1, CHAN_12_13_1, CHAN_14_1, @@ -1087,6 +1100,7 @@ const struct regulatory_rule reg_rules_2g[] = { [CHAN_1_13_2] = {2402, 2482, 40, 30, 0}, [CHAN_1_13_3] = {2402, 2482, 40, 36, 0}, [CHAN_1_13_4] = {2402, 2482, 40, 23, 0}, + [CHAN_1_13_5] = {2402, 2482, 20, 20, 0}, [CHAN_12_12_1] = {2457, 2477, 20, 20, REGULATORY_CHAN_NO_IR}, [CHAN_12_13_1] = {2457, 2482, 20, 20, REGULATORY_CHAN_NO_IR}, [CHAN_14_1] = {2474, 2494, 20, 23, REGULATORY_CHAN_NO_OFDM}, @@ -1104,7 +1118,7 @@ const struct regdomain regdomains_2g[] = { CHAN_14_1} }, [MKKC] = {CTL_MKK, DFS_UNINIT_REG, 0, 0, 1, {CHAN_1_13_4} }, [ETSIC] = {CTL_ETSI, DFS_UNINIT_REG, 0, 0, 1, {CHAN_1_13_2} }, - [ETSID] = {CTL_ETSI, DFS_UNINIT_REG, 0, 0, 1, {CHAN_1_13_3} }, + [ETSID] = {CTL_ETSI, DFS_UNINIT_REG, 0, 0, 1, {CHAN_1_13_5} }, [KRRA] = {CTL_KOR, DFS_UNINIT_REG, 0, 0, 1, {CHAN_1_13_4} }, [WORLD_2G_1] = {CTL_NONE, DFS_UNINIT_REG, 0, 0, 1, {CHAN_1_11_2} }, [WORLD_2G_2] = {CTL_NONE, DFS_UNINIT_REG, 0, 0, 2, @@ -1184,6 +1198,8 @@ enum reg_rules_5g { CHAN_5735_5875_5, CHAN_5735_5815_1, CHAN_5735_5815_2, + CHAN_5735_5815_3, + CHAN_5735_5815_4, CHAN_5735_5775_1, CHAN_5835_5855_1, CHAN_5855_5875_1, @@ -1263,6 +1279,8 @@ const struct regulatory_rule reg_rules_5g[] = { [CHAN_5735_5875_5] = {5735, 5875, 80, 20, REGULATORY_CHAN_RADAR}, [CHAN_5735_5815_1] = {5735, 5815, 80, 30, 0}, [CHAN_5735_5815_2] = {5735, 5815, 80, 30, REGULATORY_CHAN_RADAR}, + [CHAN_5735_5815_3] = {5735, 5815, 80, 23, REGULATORY_CHAN_INDOOR_ONLY}, + [CHAN_5735_5815_4] = {5735, 5815, 20, 20, 0}, [CHAN_5735_5775_1] = {5735, 5775, 40, 23, 0}, [CHAN_5835_5855_1] = {5835, 5855, 20, 30, 0}, [CHAN_5855_5875_1] = {5855, 5875, 20, 30, 0}, @@ -1323,43 +1341,40 @@ const struct regdomain regdomains_5g[] = { CHAN_5490_5730_4, CHAN_5735_5835_2} }, - [ETSI1] = {CTL_ETSI, DFS_ETSI_REG, 2, 0, 4, {CHAN_5170_5250_8, + [ETSI1] = {CTL_ETSI, DFS_ETSI_REG, 2, 0, 3, {CHAN_5170_5250_8, CHAN_5250_5330_12, - CHAN_5490_5710_1, - CHAN_5735_5875_4} }, + CHAN_5490_5710_1} }, - [ETSI3] = {CTL_ETSI, DFS_ETSI_REG, 5, 0, 3, {CHAN_5170_5250_2, - CHAN_5250_5330_1, - CHAN_5735_5875_4} }, + [ETSI3] = {CTL_ETSI, DFS_ETSI_REG, 5, 0, 2, {CHAN_5170_5250_2, + CHAN_5250_5330_1} }, - [ETSI4] = {CTL_ETSI, DFS_ETSI_REG, 2, 0, 3, {CHAN_5170_5250_6, - CHAN_5250_5330_3, - CHAN_5735_5875_4} }, + [ETSI4] = {CTL_ETSI, DFS_ETSI_REG, 2, 0, 2, {CHAN_5170_5250_6, + CHAN_5250_5330_3} }, [ETSI8] = {CTL_ETSI, DFS_UNINIT_REG, 20, 0, 4, {CHAN_5170_5250_2, CHAN_5250_5330_5, CHAN_5490_5730_3, - CHAN_5735_5875_4} }, + CHAN_5735_5835_2} }, [ETSI9] = {CTL_ETSI, DFS_ETSI_REG, 20, 0, 4, {CHAN_5170_5250_2, CHAN_5250_5330_1, CHAN_5490_5710_5, - CHAN_5735_5875_4} }, + CHAN_5735_5835_6} }, [ETSI10] = {CTL_ETSI, DFS_ETSI_REG, 10, 0, 4, {CHAN_5170_5250_7, CHAN_5250_5330_14, CHAN_5490_5710_3, - CHAN_5735_5875_4} }, + CHAN_5850_5925_2} }, [ETSI11] = {CTL_ETSI, DFS_ETSI_REG, 10, 0, 4, {CHAN_5170_5250_7, CHAN_5250_5330_14, CHAN_5490_5710_3, - CHAN_5735_5875_4} }, + CHAN_5735_5875_1} }, [ETSI12] = {CTL_ETSI, DFS_ETSI_REG, 2, 0, 4, {CHAN_5170_5250_7, CHAN_5250_5330_14, CHAN_5490_5730_6, - CHAN_5735_5835_4} }, + CHAN_5735_5835_8} }, [ETSI13] = {CTL_ETSI, DFS_ETSI_REG, 2, 0, 4, {CHAN_5170_5250_8, CHAN_5250_5330_12, @@ -1369,16 +1384,16 @@ const struct regdomain regdomains_5g[] = { [ETSI14] = {CTL_ETSI, DFS_ETSI_REG, 2, 0, 4, {CHAN_5170_5250_2, CHAN_5250_5330_1, CHAN_5490_5730_7, - CHAN_5735_5875_4} }, + CHAN_5735_5875_5} }, [ETSI15] = {CTL_ETSI, DFS_ETSI_REG, 2, 0, 4, {CHAN_5170_5250_2, CHAN_5250_5330_1, CHAN_5490_5730_5, - CHAN_5735_5875_4} }, + CHAN_5735_5815_2} }, [APL1] = {CTL_ETSI, DFS_UNINIT_REG, 2, 0, 1, {CHAN_5735_5835_2} }, - [APL2] = {CTL_ETSI, DFS_UNINIT_REG, 2, 0, 1, {CHAN_5735_5815_1} }, + [APL2] = {CTL_ETSI, DFS_UNINIT_REG, 2, 0, 1, {CHAN_5735_5815_4} }, [APL4] = {CTL_ETSI, DFS_UNINIT_REG, 2, 0, 2, {CHAN_5170_5250_2, CHAN_5735_5835_1} }, @@ -1400,7 +1415,7 @@ const struct regdomain regdomains_5g[] = { CHAN_5490_5710_1, CHAN_5735_5815_1} }, - [APL11] = { CTL_ETSI, DFS_ETSI_REG, 2, 0, 4, {CHAN_5170_5250_9, + [APL11] = { CTL_ETSI, DFS_FCC_REG, 2, 0, 4, {CHAN_5170_5250_9, CHAN_5250_5330_13, CHAN_5490_5710_4, CHAN_5735_5875_2} }, @@ -1433,7 +1448,7 @@ const struct regdomain regdomains_5g[] = { CHAN_5650_5730_3, CHAN_5735_5835_7} }, - [APL19] = {CTL_FCC, DFS_ETSI_REG, 2, 0, 4, {CHAN_5170_5250_4, + [APL19] = {CTL_FCC, DFS_FCC_REG, 2, 0, 4, {CHAN_5170_5250_4, CHAN_5250_5330_7, CHAN_5490_5730_1, CHAN_5735_5875_3} }, @@ -1447,6 +1462,10 @@ const struct regdomain regdomains_5g[] = { CHAN_5250_5330_11, CHAN_5735_5835_3} }, + [APL24] = {CTL_ETSI, DFS_ETSI_REG, 2, 0, 3, {CHAN_5170_5250_8, + CHAN_5250_5330_12, + CHAN_5735_5815_3} }, + [MKK3] = {CTL_MKK, DFS_UNINIT_REG, 2, 0, 1, {CHAN_5170_5250_3} }, [MKK5] = {CTL_MKK, DFS_MKK_REG, 2, 0, 3, {CHAN_5170_5250_8, @@ -1475,6 +1494,65 @@ const struct regdomain regdomains_5g[] = { CHAN_5735_5835_5} }, }; +const uint32_t reg_2g_sub_dmn_code[REG_DOMAINS_2G_MAX] = { + [FCCA] = 0x0A10, + [FCCB] = 0x0B90, + [WORLD] = 0x0199, + [MKKA] = 0x0A40, + [MKKC] = 0x0A50, + [ETSIC] = 0x0C30, + [ETSID] = 0x0F30, + [KRRA] = 0x0A60, +}; + +const uint32_t reg_5g_sub_dmn_code[REG_DOMAINS_5G_MAX] = { + [NULL1] = 0x0198, + [FCC1] = 0x0110, + [FCC2] = 0x0120, + [FCC3] = 0x0160, + [FCC4] = 0x0165, + [FCC5] = 0x0510, + [FCC6] = 0x0610, + [FCC8] = 0x0810, + [FCC10] = 0x0B10, + [FCC11] = 0x0B20, + [FCC13] = 0x0B60, + [FCC14] = 0x0B70, + [ETSI1] = 0x0130, + [ETSI3] = 0x0330, + [ETSI4] = 0x0430, + [ETSI8] = 0x0830, + [ETSI9] = 0x0930, + [ETSI10] = 0x0D30, + [ETSI11] = 0x0E30, + [ETSI12] = 0x0E38, + [ETSI13] = 0x0E39, + [ETSI14] = 0x0E40, + [ETSI15] = 0x0E41, + [APL1] = 0x0150, + [APL2] = 0x0250, + [APL4] = 0x0450, + [APL6] = 0x0650, + [APL8] = 0x0850, + [APL9] = 0x0950, + [APL10] = 0x1050, + [APL11] = 0x1150, + [APL12] = 0x1160, + [APL13] = 0x1170, + [APL14] = 0x1180, + [APL15] = 0x1190, + [APL16] = 0x1200, + [APL17] = 0x1210, + [APL23] = 0x1280, + [APL20] = 0x1250, + [APL23] = 0x1280, + [MKK3] = 0x0340, + [MKK5] = 0x0540, + [MKK11] = 0x1140, + [MKK16] = 0x1640, + [MKK17] = 0x1650, +}; + QDF_STATUS reg_get_num_countries(int *num_countries) { *num_countries = QDF_ARRAY_SIZE(g_all_countries); diff --git a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_db.h b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_db.h index 1563bdbfba7c..d83c7d759248 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_db.h +++ b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_db.h @@ -70,6 +70,19 @@ enum dfs_reg { DFS_UNDEF_REG = 0xFFFF, }; +/** enum op_class_table_num + * OP_CLASS_US- Class corresponds to US + * OP_CLASS_EU- Class corresponds to EU + * OP_CLASS_JAPAN- Class corresponds to JAPAN + * OP_CLASS_GLOBAL- Class corresponds to GLOBAL + */ +enum op_class_table_num { + OP_CLASS_US = 1, + OP_CLASS_EU, + OP_CLASS_JAPAN, + OP_CLASS_GLOBAL +}; + /** * struct regulatory_rule * @start_freq: start frequency diff --git a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_db_parser.c b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_db_parser.c index ff23a0e5f963..c40c71b3616b 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_db_parser.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_db_parser.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. * * * Permission to use, copy, modify, and/or distribute this software for @@ -244,8 +244,8 @@ static inline QDF_STATUS reg_get_reginfo_form_country_code_and_regdmn_pair( ant_gain_2g, ant_gain_5g, reg_info); if (err == QDF_STATUS_E_FAILURE) { - reg_err("%s : No rule found for country index = %d regdmn_pair = %d\n", - __func__, country_index, regdmn_pair); + reg_err("No rule found for country index = %d regdmn_pair = %d\n", + country_index, regdmn_pair); return QDF_STATUS_E_FAILURE; } @@ -354,8 +354,8 @@ static inline QDF_STATUS reg_get_reginfo_form_regdmn_pair( err = reg_regrules_assign(dmn_id_2g, dmn_id_5g, ant_gain_2g, ant_gain_5g, reg_info); if (err == QDF_STATUS_E_FAILURE) { - reg_err("%s : No rule found for regdmn_pair = %d\n", - __func__, regdmn_pair); + reg_err("No rule found for regdmn_pair = %d\n", + regdmn_pair); return QDF_STATUS_E_FAILURE; } diff --git a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_db_parser.h b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_db_parser.h index ef4731441f3b..51cbdcb8d059 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_db_parser.h +++ b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_db_parser.h @@ -30,6 +30,8 @@ extern const struct regulatory_rule reg_rules_2g[]; extern const struct regdomain regdomains_2g[]; extern const struct regulatory_rule reg_rules_5g[]; extern const struct regdomain regdomains_5g[]; +extern const uint32_t reg_2g_sub_dmn_code[]; +extern const uint32_t reg_5g_sub_dmn_code[]; QDF_STATUS reg_is_country_code_valid(uint8_t *alpha2); diff --git a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_services.c b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_services.c index 671c9f300a44..c64f69e6eae4 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_services.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_services.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2014-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -1160,8 +1160,6 @@ static void reg_set_5g_channel_params(struct wlan_objmgr_pdev *pdev, * Set channel parameters like center frequency for a bonded channel * state. Also return the maximum bandwidth supported by the channel. */ - - enum phy_ch_width next_lower_bw; enum channel_state chan_state = CHANNEL_STATE_ENABLE; enum channel_state chan_state2 = CHANNEL_STATE_ENABLE; const struct bonded_channel *bonded_chan_ptr = NULL; @@ -1178,11 +1176,8 @@ static void reg_set_5g_channel_params(struct wlan_objmgr_pdev *pdev, else ch_params->ch_width = CH_WIDTH_160MHZ; } - next_lower_bw = ch_params->ch_width; while (ch_params->ch_width != CH_WIDTH_INVALID) { - ch_params->ch_width = next_lower_bw; - next_lower_bw = get_next_lower_bw[ch_params->ch_width]; bonded_chan_ptr = NULL; bonded_chan_ptr2 = NULL; chan_state = reg_get_5g_bonded_channel(pdev, ch, @@ -1202,7 +1197,7 @@ static void reg_set_5g_channel_params(struct wlan_objmgr_pdev *pdev, if ((CHANNEL_STATE_ENABLE != chan_state) && (CHANNEL_STATE_DFS != chan_state)) - continue; + goto update_bw; if (CH_WIDTH_20MHZ >= ch_params->ch_width) { ch_params->sec_ch_offset = NO_SEC_CH; ch_params->center_freq_seg0 = ch; @@ -1213,7 +1208,7 @@ static void reg_set_5g_channel_params(struct wlan_objmgr_pdev *pdev, QDF_ARRAY_SIZE(bonded_chan_40mhz_list), &bonded_chan_ptr2); if (!bonded_chan_ptr || !bonded_chan_ptr2) - continue; + goto update_bw; if (ch == bonded_chan_ptr2->start_ch) ch_params->sec_ch_offset = LOW_PRIMARY_CH; else @@ -1224,6 +1219,8 @@ static void reg_set_5g_channel_params(struct wlan_objmgr_pdev *pdev, bonded_chan_ptr->end_ch)/2; break; } +update_bw: + ch_params->ch_width = get_next_lower_bw[ch_params->ch_width]; } if (CH_WIDTH_160MHZ == ch_params->ch_width) { @@ -1404,7 +1401,7 @@ QDF_STATUS reg_set_default_country(struct wlan_objmgr_psoc *psoc, return QDF_STATUS_E_INVAL; } - reg_info("setting default_country: %s", country); + reg_info("set default_country: %s", country); qdf_mem_copy(psoc_reg->def_country, country, REG_ALPHA2_LEN + 1); @@ -1461,8 +1458,11 @@ QDF_STATUS reg_set_country(struct wlan_objmgr_pdev *pdev, if (!qdf_mem_cmp(psoc_reg->cur_country, country, REG_ALPHA2_LEN)) { - reg_err("country is not different"); - return QDF_STATUS_SUCCESS; + if (psoc_reg->cc_src == SOURCE_USERSPACE || + psoc_reg->cc_src == SOURCE_CORE) { + reg_debug("country is not different"); + return QDF_STATUS_SUCCESS; + } } reg_debug("programming new country:%s to firmware", country); @@ -1535,7 +1535,7 @@ QDF_STATUS reg_set_11d_country(struct wlan_objmgr_pdev *pdev, uint8_t pdev_id; if (!country) { - reg_err("country code is NULL"); + reg_err("Null country code"); return QDF_STATUS_E_INVAL; } @@ -1544,17 +1544,19 @@ QDF_STATUS reg_set_11d_country(struct wlan_objmgr_pdev *pdev, psoc = wlan_pdev_get_psoc(pdev); psoc_reg = reg_get_psoc_obj(psoc); if (!IS_VALID_PSOC_REG_OBJ(psoc_reg)) { - reg_err("psoc reg component is NULL"); + reg_err("Null psoc reg component"); return QDF_STATUS_E_INVAL; } if (!qdf_mem_cmp(psoc_reg->cur_country, country, REG_ALPHA2_LEN)) { - reg_debug("country is not different"); - return QDF_STATUS_SUCCESS; + if (psoc_reg->cc_src == SOURCE_11D) { + reg_debug("same country"); + return QDF_STATUS_SUCCESS; + } } - reg_info("programming new 11d country:%c%c to firmware", + reg_info("set new 11d country:%c%c to fw", country[0], country[1]); qdf_mem_copy(country_code.country, @@ -1586,7 +1588,6 @@ QDF_STATUS reg_reset_country(struct wlan_objmgr_psoc *psoc) return QDF_STATUS_E_INVAL; } - reg_info("re-setting user country to default"); qdf_mem_copy(psoc_reg->cur_country, psoc_reg->def_country, REG_ALPHA2_LEN + 1); @@ -1681,7 +1682,7 @@ QDF_STATUS reg_get_domain_from_country_code(v_REGDOMAIN_t *reg_domain_ptr, *reg_domain_ptr = 0; if (NULL == country_alpha2) { - reg_err("Country code array is NULL"); + reg_err("Country code is NULL"); return QDF_STATUS_E_FAULT; } @@ -1930,21 +1931,56 @@ enum band_info reg_chan_to_band(uint32_t chan_num) return BAND_5G; } -uint16_t reg_dmn_get_chanwidth_from_opclass(uint8_t *country, - uint8_t channel, +/** + * reg_get_class_from_country()- Get Class from country + * @country- Country + * + * Return: class. + */ +static const struct +reg_dmn_op_class_map_t *reg_get_class_from_country(uint8_t *country) +{ + const struct reg_dmn_op_class_map_t *class = NULL; + + reg_debug_rl("Country %c%c 0x%x", country[0], country[1], country[2]); + + switch (country[2]) { + case OP_CLASS_US: + class = us_op_class; + break; + + case OP_CLASS_EU: + class = euro_op_class; + break; + + case OP_CLASS_JAPAN: + class = japan_op_class; + break; + + case OP_CLASS_GLOBAL: + class = global_op_class; + break; + + default: + if (!qdf_mem_cmp(country, "US", 2)) + class = us_op_class; + else if (!qdf_mem_cmp(country, "EU", 2)) + class = euro_op_class; + else if (!qdf_mem_cmp(country, "JP", 2)) + class = japan_op_class; + else + class = global_op_class; + } + return class; +} + +uint16_t reg_dmn_get_chanwidth_from_opclass(uint8_t *country, uint8_t channel, uint8_t opclass) { const struct reg_dmn_op_class_map_t *class; uint16_t i; - if (!qdf_mem_cmp(country, "US", 2)) - class = us_op_class; - else if (!qdf_mem_cmp(country, "EU", 2)) - class = euro_op_class; - else if (!qdf_mem_cmp(country, "JP", 2)) - class = japan_op_class; - else - class = global_op_class; + class = reg_get_class_from_country(country); while (class->op_class) { if (opclass == class->op_class) { @@ -1970,16 +2006,9 @@ uint16_t reg_dmn_get_opclass_from_channel(uint8_t *country, const struct reg_dmn_op_class_map_t *class = NULL; uint16_t i = 0; - if (!qdf_mem_cmp(country, "US", 2)) - class = us_op_class; - else if (!qdf_mem_cmp(country, "EU", 2)) - class = euro_op_class; - else if (!qdf_mem_cmp(country, "JP", 2)) - class = japan_op_class; - else - class = global_op_class; + class = reg_get_class_from_country(country); - while (class->op_class) { + while (class && class->op_class) { if ((offset == class->offset) || (offset == BWALL)) { for (i = 0; (i < REG_MAX_CHANNELS_PER_OPERATING_CLASS && @@ -1994,6 +2023,35 @@ uint16_t reg_dmn_get_opclass_from_channel(uint8_t *country, return 0; } +void reg_dmn_print_channels_in_opclass(uint8_t *country, + uint8_t op_class) +{ + const struct reg_dmn_op_class_map_t *class = NULL; + uint16_t i = 0; + + class = reg_get_class_from_country(country); + if (!class) { + reg_err("class is NULL"); + return; + } + + while (class->op_class) { + if (class->op_class == op_class) { + for (i = 0; + (i < REG_MAX_CHANNELS_PER_OPERATING_CLASS && + class->channels[i]); i++) { + reg_debug("Valid channel(%d) in requested RC(%d)", + class->channels[i], op_class); + } + break; + } + class++; + } + if (!class->op_class) + QDF_TRACE(QDF_MODULE_ID_QDF, QDF_TRACE_LEVEL_ERROR, + "Invalid requested RC (%d)", op_class); +} + uint16_t reg_dmn_set_curr_opclasses(uint8_t num_classes, uint8_t *class) { @@ -2617,10 +2675,8 @@ static void reg_call_chan_change_cbks(struct wlan_objmgr_psoc *psoc, } cur_chan_list = qdf_mem_malloc(NUM_CHANNELS * sizeof(*cur_chan_list)); - if (NULL == cur_chan_list) { - reg_alert("Mem alloc failed for current channel list"); + if (!cur_chan_list) return; - } qdf_mem_copy(cur_chan_list, pdev_priv_obj->cur_chan_list, @@ -2629,10 +2685,8 @@ static void reg_call_chan_change_cbks(struct wlan_objmgr_psoc *psoc, if (psoc_priv_obj->ch_avoid_ind) { avoid_freq_ind = qdf_mem_malloc(sizeof(*avoid_freq_ind)); - if (!avoid_freq_ind) { - reg_alert("Mem alloc failed for avoid freq ind"); + if (!avoid_freq_ind) goto skip_ch_avoid_ind; - } qdf_mem_copy(&avoid_freq_ind->freq_list, &psoc_priv_obj->avoid_freq_list, sizeof(struct ch_avoid_ind_type)); @@ -2754,7 +2808,7 @@ QDF_STATUS reg_send_scheduler_msg_sb(struct wlan_objmgr_psoc *psoc, payload = reg_alloc_and_fill_payload(psoc, pdev); if (payload == NULL) { - reg_err("payload memory alloc failed"); + reg_err("malloc failed"); wlan_objmgr_pdev_release_ref(pdev, WLAN_REGULATORY_SB_ID); wlan_objmgr_psoc_release_ref(psoc, WLAN_REGULATORY_SB_ID); return QDF_STATUS_E_NOMEM; @@ -2770,7 +2824,6 @@ QDF_STATUS reg_send_scheduler_msg_sb(struct wlan_objmgr_psoc *psoc, if (QDF_IS_STATUS_ERROR(status)) { wlan_objmgr_pdev_release_ref(pdev, WLAN_REGULATORY_SB_ID); wlan_objmgr_psoc_release_ref(psoc, WLAN_REGULATORY_SB_ID); - reg_err("scheduler msg posting failed"); qdf_mem_free(payload); } @@ -2799,7 +2852,7 @@ static QDF_STATUS reg_send_scheduler_msg_nb(struct wlan_objmgr_psoc *psoc, payload = reg_alloc_and_fill_payload(psoc, pdev); if (payload == NULL) { - reg_err("payload memory alloc failed"); + reg_err("malloc failed"); wlan_objmgr_pdev_release_ref(pdev, WLAN_REGULATORY_NB_ID); wlan_objmgr_psoc_release_ref(psoc, WLAN_REGULATORY_NB_ID); return QDF_STATUS_E_NOMEM; @@ -2814,7 +2867,6 @@ static QDF_STATUS reg_send_scheduler_msg_nb(struct wlan_objmgr_psoc *psoc, if (QDF_IS_STATUS_ERROR(status)) { wlan_objmgr_pdev_release_ref(pdev, WLAN_REGULATORY_NB_ID); wlan_objmgr_psoc_release_ref(psoc, WLAN_REGULATORY_NB_ID); - reg_err("scheduler msg posting failed"); qdf_mem_free(payload); } @@ -2844,13 +2896,13 @@ static QDF_STATUS reg_send_11d_msg_cbk(struct scheduler_msg *msg) WLAN_UMAC_COMP_REGULATORY); if (!psoc_priv_obj) { - reg_err("psoc priv obj is NULL"); + reg_err("Null psoc priv obj"); goto end; } if (psoc_priv_obj->vdev_id_for_11d_scan == INVALID_VDEV_ID) { psoc_priv_obj->enable_11d_supp = false; - reg_err("No valid vdev for 11d scan command"); + reg_err("Invalid vdev"); goto end; } @@ -2889,10 +2941,8 @@ static QDF_STATUS reg_sched_11d_msg(struct wlan_objmgr_psoc *psoc) status = scheduler_post_message(QDF_MODULE_ID_REGULATORY, QDF_MODULE_ID_REGULATORY, QDF_MODULE_ID_TARGET_IF, &msg); - if (QDF_IS_STATUS_ERROR(status)) { + if (QDF_IS_STATUS_ERROR(status)) wlan_objmgr_psoc_release_ref(psoc, WLAN_REGULATORY_SB_ID); - reg_err("scheduler msg posting failed"); - } return status; } @@ -3007,13 +3057,13 @@ static void reg_run_11d_state_machine(struct wlan_objmgr_psoc *psoc) psoc_priv_obj = wlan_objmgr_psoc_get_comp_private_obj(psoc, WLAN_UMAC_COMP_REGULATORY); if (!psoc_priv_obj) { - reg_err("reg psoc private obj is NULL"); + reg_err("Null reg psoc private obj"); return; } if (psoc_priv_obj->vdev_id_for_11d_scan == INVALID_VDEV_ID) { psoc_priv_obj->enable_11d_supp = false; - reg_err("No valid vdev for 11d scan command"); + reg_err("Invalid vdev"); return; } @@ -3101,14 +3151,14 @@ static QDF_STATUS reg_set_curr_country( country_code.pdev_id = pdev_id; if (!tx_ops || !tx_ops->set_country_code) { - reg_err("No regulatory tx_ops for set_country_code"); + reg_err("No regulatory tx_ops"); status = QDF_STATUS_E_FAULT; goto error; } status = tx_ops->set_country_code(psoc, &country_code); if (QDF_IS_STATUS_ERROR(status)) { - reg_err("Failed to send country code to firmware"); + reg_err("Failed to send country code to fw"); goto error; } @@ -3156,6 +3206,67 @@ reg_ignore_default_country(struct wlan_regulatory_psoc_priv_obj *soc_reg, return true; } +/** + * reg_send_ctl_info() - Sends CTL info to firmware + * @soc_reg: soc private object for regulatory + * @regulatory_info: regualatory info + * @tx_ops: send operations for regulatory component + * + * Return: QDF_STATUS + */ +static QDF_STATUS +reg_send_ctl_info(struct wlan_regulatory_psoc_priv_obj *soc_reg, + struct cur_regulatory_info *regulatory_info, + struct wlan_lmac_if_reg_tx_ops *tx_ops) +{ + struct wlan_objmgr_psoc *psoc = regulatory_info->psoc; + struct reg_ctl_params params = {0}; + QDF_STATUS status; + uint16_t regd_index; + uint32_t index_2g, index_5g; + + if (soc_reg->offload_enabled) + return QDF_STATUS_SUCCESS; + + status = reg_get_rdpair_from_regdmn_id(regulatory_info->reg_dmn_pair, + ®d_index); + if (QDF_IS_STATUS_ERROR(status)) { + reg_err("Failed to get regdomain index for regdomain pair: %x", + regulatory_info->reg_dmn_pair); + return status; + } + + index_2g = g_reg_dmn_pairs[regd_index].dmn_id_2g; + index_5g = g_reg_dmn_pairs[regd_index].dmn_id_5g; + params.ctl_2g = regdomains_2g[index_2g].ctl_val; + params.ctl_5g = regdomains_5g[index_5g].ctl_val; + params.regd_2g = reg_2g_sub_dmn_code[index_2g]; + params.regd_5g = reg_5g_sub_dmn_code[index_5g]; + + if (reg_is_world_ctry_code(regulatory_info->reg_dmn_pair)) + params.regd = regulatory_info->reg_dmn_pair; + else + params.regd = regulatory_info->ctry_code | COUNTRY_ERD_FLAG; + + if (!tx_ops || !tx_ops->send_ctl_info) { + reg_err("No regulatory tx_ops"); + return QDF_STATUS_E_FAULT; + } + + reg_debug("regdomain pair = %u, regdomain index = %u", + regulatory_info->reg_dmn_pair, regd_index); + reg_debug("index_2g = %u, index_5g = %u, ctl_2g = %x, ctl_5g = %x", + index_2g, index_5g, params.ctl_2g, params.ctl_5g); + reg_debug("regd_2g = %x, regd_5g = %x, regd = %x", + params.regd_2g, params.regd_5g, params.regd); + + status = tx_ops->send_ctl_info(psoc, ¶ms); + if (QDF_IS_STATUS_ERROR(status)) + reg_err("Failed to send CTL info to firmware"); + + return status; +} + QDF_STATUS reg_process_master_chan_list(struct cur_regulatory_info *regulat_info) { @@ -3185,6 +3296,10 @@ QDF_STATUS reg_process_master_chan_list(struct cur_regulatory_info tx_ops = reg_get_psoc_tx_ops(psoc); phy_id = regulat_info->phy_id; + status = reg_send_ctl_info(soc_reg, regulat_info, tx_ops); + if (!QDF_IS_STATUS_SUCCESS(status)) + return status; + if (reg_ignore_default_country(soc_reg, regulat_info)) { status = reg_set_curr_country(soc_reg, regulat_info, tx_ops); if (QDF_IS_STATUS_SUCCESS(status)) { @@ -3205,8 +3320,8 @@ QDF_STATUS reg_process_master_chan_list(struct cur_regulatory_info } if (regulat_info->status_code != REG_SET_CC_STATUS_PASS) { - reg_err("Setting country code failed, status code is %d", - regulat_info->status_code); + reg_err("Set country code failed, status code %d", + regulat_info->status_code); pdev = wlan_objmgr_get_pdev_by_id(psoc, phy_id, dbg_id); if (!pdev) { @@ -3397,10 +3512,8 @@ QDF_STATUS wlan_regulatory_psoc_obj_created_notification( uint8_t pdev_cnt; soc_reg_obj = qdf_mem_malloc(sizeof(*soc_reg_obj)); - if (NULL == soc_reg_obj) { - reg_alert("Mem alloc failed for reg psoc priv obj"); + if (!soc_reg_obj) return QDF_STATUS_E_NOMEM; - } soc_reg_obj->offload_enabled = false; soc_reg_obj->psoc_ptr = psoc; @@ -3471,7 +3584,7 @@ QDF_STATUS wlan_regulatory_psoc_obj_destroyed_notification( WLAN_UMAC_COMP_REGULATORY); if (NULL == soc_reg) { - reg_err("reg psoc private obj is NULL"); + reg_err("NULL reg psoc priv obj"); return QDF_STATUS_E_FAULT; } @@ -3485,7 +3598,7 @@ QDF_STATUS wlan_regulatory_psoc_obj_destroyed_notification( if (status != QDF_STATUS_SUCCESS) reg_err("soc_reg private obj detach failed"); - reg_debug("reg psoc obj detached with status %d", status); + reg_debug("reg psoc obj detached"); qdf_mem_free(soc_reg); @@ -3508,7 +3621,7 @@ QDF_STATUS reg_set_band(struct wlan_objmgr_pdev *pdev, } if (pdev_priv_obj->band_capability == band) { - reg_info("band is already set to %d", band); + reg_info("same band %d", band); return QDF_STATUS_SUCCESS; } @@ -3524,7 +3637,7 @@ QDF_STATUS reg_set_band(struct wlan_objmgr_pdev *pdev, return QDF_STATUS_E_INVAL; } - reg_info("setting band_info: %d", band); + reg_info("set band_info: %d", band); pdev_priv_obj->band_capability = band; reg_compute_pdev_current_chan_list(pdev_priv_obj); @@ -3560,7 +3673,7 @@ QDF_STATUS reg_get_band(struct wlan_objmgr_pdev *pdev, return QDF_STATUS_E_INVAL; } - reg_debug("getting band_info: %d", pdev_priv_obj->band_capability); + reg_debug("get band_info: %d", pdev_priv_obj->band_capability); *band = pdev_priv_obj->band_capability; return QDF_STATUS_SUCCESS; @@ -3721,11 +3834,11 @@ QDF_STATUS reg_set_fcc_constraint(struct wlan_objmgr_pdev *pdev, } if (pdev_priv_obj->set_fcc_channel == fcc_constraint) { - reg_info("fcc_constraint is already set to %d", fcc_constraint); + reg_info("same fcc_constraint %d", fcc_constraint); return QDF_STATUS_SUCCESS; } - reg_info("setting set_fcc_channel: %d", fcc_constraint); + reg_info("set set_fcc_channel: %d", fcc_constraint); pdev_priv_obj->set_fcc_channel = fcc_constraint; psoc = wlan_pdev_get_psoc(pdev); @@ -3797,7 +3910,7 @@ QDF_STATUS reg_enable_dfs_channels(struct wlan_objmgr_pdev *pdev, return QDF_STATUS_E_INVAL; } - reg_info("setting dfs_enabled: %d", enable); + reg_info("set dfs_enabled: %d", enable); pdev_priv_obj->dfs_enabled = enable; @@ -3833,10 +3946,8 @@ QDF_STATUS wlan_regulatory_pdev_obj_created_notification( struct reg_rule_info *psoc_reg_rules; pdev_priv_obj = qdf_mem_malloc(sizeof(*pdev_priv_obj)); - if (NULL == pdev_priv_obj) { - reg_alert("Mem alloc failed for pdev priv obj"); + if (!pdev_priv_obj) return QDF_STATUS_E_NOMEM; - } parent_psoc = wlan_pdev_get_psoc(pdev); pdev_id = wlan_objmgr_pdev_get_pdev_id(pdev); @@ -3944,7 +4055,7 @@ QDF_STATUS wlan_regulatory_pdev_obj_destroyed_notification( if (status != QDF_STATUS_SUCCESS) reg_err("reg pdev private obj detach failed"); - reg_debug("reg pdev obj deleted with status %d", status); + reg_debug("reg pdev obj deleted"); qdf_spin_lock_bh(&pdev_priv_obj->reg_rules_lock); reg_reset_reg_rules(&pdev_priv_obj->reg_rules); @@ -4035,7 +4146,7 @@ QDF_STATUS reg_11d_vdev_delete_update(struct wlan_objmgr_vdev *vdev) uint8_t i; if (!vdev) { - reg_err("vdev is NULL"); + reg_err("NULL vdev"); return QDF_STATUS_E_INVAL; } op_mode = wlan_vdev_mlme_get_opmode(vdev); @@ -4048,7 +4159,7 @@ QDF_STATUS reg_11d_vdev_delete_update(struct wlan_objmgr_vdev *vdev) WLAN_UMAC_COMP_REGULATORY); if (!psoc_priv_obj) { - reg_err("reg psoc private obj is NULL"); + reg_err("NULL reg psoc private obj"); return QDF_STATUS_E_FAULT; } @@ -4264,7 +4375,7 @@ bool reg_is_regdb_offloaded(struct wlan_objmgr_psoc *psoc) WLAN_UMAC_COMP_REGULATORY); if (NULL == psoc_priv_obj) { - reg_err("reg psoc private obj is NULL"); + reg_err("NULL reg psoc private obj"); return false; } @@ -4351,7 +4462,7 @@ void reg_register_chan_change_callback(struct wlan_objmgr_psoc *psoc, qdf_spin_unlock_bh(&psoc_priv_obj->cbk_list_lock); if (count == REG_MAX_CHAN_CHANGE_CBKS) - reg_err("callback list is full, could not add the cbk"); + reg_err("callback list is full"); } void reg_unregister_chan_change_callback(struct wlan_objmgr_psoc *psoc, @@ -4414,17 +4525,15 @@ QDF_STATUS reg_program_default_cc(struct wlan_objmgr_pdev *pdev, wlan_objmgr_pdev_get_comp_private_obj(pdev, WLAN_UMAC_COMP_REGULATORY); - if (NULL == pdev_priv_obj) { + if (!pdev_priv_obj) { reg_err("reg soc is NULL"); return QDF_STATUS_E_FAILURE; } reg_info = (struct cur_regulatory_info *)qdf_mem_malloc (sizeof(struct cur_regulatory_info)); - if (reg_info == NULL) { - reg_err("reg info is NULL"); + if (!reg_info) return QDF_STATUS_E_NOMEM; - } psoc = wlan_pdev_get_psoc(pdev); if (!psoc) { @@ -4449,7 +4558,7 @@ QDF_STATUS reg_program_default_cc(struct wlan_objmgr_pdev *pdev, err = reg_get_cur_reginfo(reg_info, country_index, regdmn_pair); if (err == QDF_STATUS_E_FAILURE) { - reg_err("%s : Unable to set country code\n", __func__); + reg_err("Unable to set country code"); qdf_mem_free(reg_info->reg_rules_2g_ptr); qdf_mem_free(reg_info->reg_rules_5g_ptr); qdf_mem_free(reg_info); @@ -4464,7 +4573,7 @@ QDF_STATUS reg_program_default_cc(struct wlan_objmgr_pdev *pdev, err = reg_get_cur_reginfo(reg_info, country_index, regdmn_pair); if (err == QDF_STATUS_E_FAILURE) { - reg_err("%s : Unable to set country code\n", __func__); + reg_err("Unable to set country code"); qdf_mem_free(reg_info->reg_rules_2g_ptr); qdf_mem_free(reg_info->reg_rules_5g_ptr); qdf_mem_free(reg_info); @@ -4559,10 +4668,8 @@ QDF_STATUS reg_program_chan_list(struct wlan_objmgr_pdev *pdev, reg_info = (struct cur_regulatory_info *)qdf_mem_malloc (sizeof(struct cur_regulatory_info)); - if (reg_info == NULL) { - reg_err("reg info is NULL"); + if (!reg_info) return QDF_STATUS_E_NOMEM; - } reg_info->psoc = psoc; reg_info->phy_id = wlan_objmgr_pdev_get_pdev_id(pdev); @@ -4582,7 +4689,7 @@ QDF_STATUS reg_program_chan_list(struct wlan_objmgr_pdev *pdev, err = reg_get_cur_reginfo(reg_info, country_index, regdmn_pair); if (err == QDF_STATUS_E_FAILURE) { - reg_err("%s : Unable to set country code\n", __func__); + reg_err("Unable to set country code"); qdf_mem_free(reg_info->reg_rules_2g_ptr); qdf_mem_free(reg_info->reg_rules_5g_ptr); qdf_mem_free(reg_info); @@ -4607,7 +4714,7 @@ bool reg_is_11d_scan_inprogress(struct wlan_objmgr_psoc *psoc) WLAN_UMAC_COMP_REGULATORY); if (!psoc_priv_obj) { - reg_err("reg psoc private obj is NULL"); + reg_err("NULL reg psoc private obj"); return false; } @@ -4717,21 +4824,15 @@ static QDF_STATUS reg_process_ch_avoid_freq(struct wlan_objmgr_psoc *psoc, } } - reg_debug("number of unsafe channels is %d ", - psoc_priv_obj->unsafe_chan_list.ch_cnt); - - if (!psoc_priv_obj->unsafe_chan_list.ch_cnt) { - reg_debug("No valid ch are present in avoid freq event"); + if (!psoc_priv_obj->unsafe_chan_list.ch_cnt) return QDF_STATUS_SUCCESS; - } for (ch_loop = 0; ch_loop < psoc_priv_obj->unsafe_chan_list.ch_cnt; ch_loop++) { if (ch_loop >= NUM_CHANNELS) break; - reg_debug("channel %d is not safe", - psoc_priv_obj->unsafe_chan_list. - ch_list[ch_loop]); + reg_debug("unsafe chan %d", + psoc_priv_obj->unsafe_chan_list.ch_list[ch_loop]); } return QDF_STATUS_SUCCESS; @@ -4849,7 +4950,7 @@ QDF_STATUS reg_save_new_11d_country(struct wlan_objmgr_psoc *psoc, WLAN_UMAC_COMP_REGULATORY); if (!psoc_priv_obj) { - reg_err("reg psoc private obj is NULL"); + reg_err("NULL reg psoc private obj"); return QDF_STATUS_E_FAILURE; } @@ -4864,7 +4965,7 @@ QDF_STATUS reg_save_new_11d_country(struct wlan_objmgr_psoc *psoc, if (tx_ops->set_country_code) { tx_ops->set_country_code(psoc, &country_code); } else { - reg_err("country set handler is not present"); + reg_err("NULL country set handler"); psoc_priv_obj->new_11d_ctry_pending[pdev_id] = false; return QDF_STATUS_E_FAULT; } @@ -4882,7 +4983,7 @@ bool reg_11d_original_enabled_on_host(struct wlan_objmgr_psoc *psoc) WLAN_UMAC_COMP_REGULATORY); if (NULL == psoc_priv_obj) { - reg_err("reg psoc private obj is NULL"); + reg_err("NULL reg psoc private obj"); return QDF_STATUS_E_FAILURE; } @@ -4898,7 +4999,7 @@ bool reg_11d_enabled_on_host(struct wlan_objmgr_psoc *psoc) WLAN_UMAC_COMP_REGULATORY); if (NULL == psoc_priv_obj) { - reg_err("reg psoc private obj is NULL"); + reg_err("NULL reg psoc private obj"); return QDF_STATUS_E_FAILURE; } diff --git a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_services.h b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_services.h index 480ff9d062e5..1b4440902198 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_services.h +++ b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/core/src/reg_services.h @@ -333,6 +333,16 @@ uint16_t reg_dmn_get_opclass_from_channel(uint8_t *country, uint8_t channel, uint8_t offset); +/** + * reg_dmn_get_opclass_from_channe() - Print channels in op class. + * @country: Country code. + * @opclass: opclass. + * + * Return: Void. + */ +void reg_dmn_print_channels_in_opclass(uint8_t *country, + uint8_t op_class); + uint16_t reg_dmn_set_curr_opclasses(uint8_t num_classes, uint8_t *class); uint16_t reg_dmn_get_curr_opclasses(uint8_t *num_classes, uint8_t *class); diff --git a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/dispatcher/inc/reg_services_public_struct.h b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/dispatcher/inc/reg_services_public_struct.h index a4ab5ac4a964..ef63f4348439 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/dispatcher/inc/reg_services_public_struct.h +++ b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/dispatcher/inc/reg_services_public_struct.h @@ -1017,4 +1017,20 @@ struct avoid_freq_ind_data { struct unsafe_ch_list chan_list; }; +/** + * struct reg_ctl_params - reg ctl and regd info + * @regd: regdomain pair + * @regd_2g: 2g sub domain code + * @regd_5g: 5g sub domain code + * @ctl_2g: 2g ctl info + * @ctl_5g: 5g ctl info + */ +struct reg_ctl_params { + uint32_t regd; + uint16_t regd_2g; + uint16_t regd_5g; + uint8_t ctl_2g; + uint8_t ctl_5g; +}; + #endif diff --git a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/dispatcher/inc/wlan_reg_services_api.h b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/dispatcher/inc/wlan_reg_services_api.h index 10a873c06cc0..42174be1976c 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/dispatcher/inc/wlan_reg_services_api.h +++ b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/dispatcher/inc/wlan_reg_services_api.h @@ -254,6 +254,16 @@ uint16_t wlan_reg_dmn_get_opclass_from_channel(uint8_t *country, uint8_t channel, uint8_t offset); +/** + * wlan_reg_dmn_print_channels_in_opclass() - Print channels in op-class + * @country: country alpha2 + * @opclass: oplcass + * + * Return: void + */ +void wlan_reg_dmn_print_channels_in_opclass(uint8_t *country, + uint8_t opclass); + /** * wlan_reg_dmn_get_chanwidth_from_opclass() - get channel width from * operating class diff --git a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/dispatcher/src/wlan_reg_services_api.c b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/dispatcher/src/wlan_reg_services_api.c index edbb781e5632..8166292c7c30 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/regulatory/dispatcher/src/wlan_reg_services_api.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/regulatory/dispatcher/src/wlan_reg_services_api.c @@ -243,6 +243,12 @@ uint16_t wlan_reg_dmn_get_opclass_from_channel(uint8_t *country, offset); } +void wlan_reg_dmn_print_channels_in_opclass(uint8_t *country, + uint8_t opclass) +{ + reg_dmn_print_channels_in_opclass(country, opclass); +} + uint16_t wlan_reg_dmn_get_chanwidth_from_opclass(uint8_t *country, uint8_t channel, uint8_t opclass) diff --git a/drivers/staging/qca-wifi-host-cmn/umac/scan/core/src/wlan_scan_bss_score.c b/drivers/staging/qca-wifi-host-cmn/umac/scan/core/src/wlan_scan_bss_score.c index 6d7be6112791..68c593daaf29 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/scan/core/src/wlan_scan_bss_score.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/scan/core/src/wlan_scan_bss_score.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -63,6 +63,9 @@ #define SCM_MAX_WEIGHT_OF_PCL_CHANNELS 255 #define SCM_PCL_GROUPS_WEIGHT_DIFFERENCE 20 +/* Congestion threshold (channel load %) to consider band and OCE WAN score */ +#define CONGESTION_THRSHOLD_FOR_BAND_OCE_SCORE 75 + bool scm_is_better_bss(struct scan_default_params *params, struct scan_cache_entry *bss1, struct scan_cache_entry *bss2) @@ -393,20 +396,11 @@ static int32_t scm_calculate_bandwidth_score( cbmode = score_config->cb_mode_5G; } - if (entry->phy_mode == WLAN_PHYMODE_11AC_VHT80_80 || - entry->phy_mode == WLAN_PHYMODE_11AC_VHT160) + if (IS_WLAN_PHYMODE_160MHZ(entry->phy_mode)) ch_width_index = SCM_160MHZ_BW_INDEX; - else if (entry->phy_mode == WLAN_PHYMODE_11AC_VHT80) - ch_width_index = SCM_80MHZ_BW_INDEX; - else if (entry->phy_mode == WLAN_PHYMODE_11NA_HT40PLUS || - entry->phy_mode == WLAN_PHYMODE_11NA_HT40MINUS || - entry->phy_mode == WLAN_PHYMODE_11NG_HT40PLUS || - entry->phy_mode == WLAN_PHYMODE_11NG_HT40MINUS || - entry->phy_mode == WLAN_PHYMODE_11NG_HT40 || - entry->phy_mode == WLAN_PHYMODE_11NA_HT40 || - entry->phy_mode == WLAN_PHYMODE_11AC_VHT40PLUS || - entry->phy_mode == WLAN_PHYMODE_11AC_VHT40MINUS || - entry->phy_mode == WLAN_PHYMODE_11AC_VHT40) + else if (IS_WLAN_PHYMODE_80MHZ(entry->phy_mode)) + ch_width_index = SCM_80MHZ_BW_INDEX; + else if (IS_WLAN_PHYMODE_40MHZ(entry->phy_mode)) ch_width_index = SCM_40MHZ_BW_INDEX; else ch_width_index = SCM_20MHZ_BW_INDEX; @@ -459,24 +453,61 @@ static int32_t scm_get_score_for_index(uint8_t index, index - SCM_SCORE_OFFSET_INDEX_15_12); } +/** + * scm_get_congestion_pct () - Calculate congestion pct from esp/qbss load + * @entry: bss information + * + * Return : congestion pct + */ +static int32_t scm_get_congestion_pct(struct scan_cache_entry *entry) +{ + uint32_t ap_load = 0; + uint32_t est_air_time_percentage = 0; + uint32_t congestion = 0; + + if (entry->air_time_fraction) { + /* Convert 0-255 range to percentage */ + est_air_time_percentage = entry->air_time_fraction * + SCM_MAX_CHANNEL_WEIGHT; + est_air_time_percentage = qdf_do_div(est_air_time_percentage, + SCM_MAX_ESTIMATED_AIR_TIME_FRACTION); + /* + * Calculate channel congestion from estimated air time + * fraction. + */ + congestion = SCM_MAX_CHANNEL_UTILIZATION - + est_air_time_percentage; + } else if (entry->qbss_chan_load) { + ap_load = (entry->qbss_chan_load * BEST_CANDIDATE_MAX_WEIGHT); + /* + * Calculate ap_load in % from qbss channel load from + * 0-255 range + */ + congestion = qdf_do_div(ap_load, MAX_AP_LOAD); + } + + return congestion; +} + /** * scm_calculate_congestion_score () - Calculate congestion score * @entry: bss information * @score_params: bss score params + * @congestion_pct: congestion pct * * Return : congestion score */ static int32_t scm_calculate_congestion_score( struct scan_cache_entry *entry, - struct scoring_config *score_params) + struct scoring_config *score_params, + uint32_t *congestion_pct) { - uint32_t ap_load = 0; - uint32_t est_air_time_percentage = 0; - uint32_t congestion = 0; uint32_t window_size; uint8_t index; int32_t good_rssi_threshold; + *congestion_pct = scm_get_congestion_pct(entry); + if (!score_params->esp_qbss_scoring.num_slot) return 0; @@ -496,40 +527,17 @@ static int32_t scm_calculate_congestion_score( channel_congestion_weightage, &score_params->esp_qbss_scoring); - if (entry->air_time_fraction) { - /* Convert 0-255 range to percentage */ - est_air_time_percentage = - entry->air_time_fraction * - SCM_MAX_CHANNEL_WEIGHT; - est_air_time_percentage = - qdf_do_div(est_air_time_percentage, - SCM_MAX_ESTIMATED_AIR_TIME_FRACTION); - /* - * Calculate channel congestion from estimated air time - * fraction. - */ - congestion = SCM_MAX_CHANNEL_UTILIZATION - - est_air_time_percentage; - } else if (entry->qbss_chan_load) { - ap_load = (entry->qbss_chan_load * - BEST_CANDIDATE_MAX_WEIGHT); - /* - * Calculate ap_load in % from qbss channel load from - * 0-255 range - */ - congestion = qdf_do_div(ap_load, MAX_AP_LOAD); - } else { + if (!*congestion_pct) return score_params->weight_cfg.channel_congestion_weightage * WLAN_GET_SCORE_PERCENTAGE( score_params->esp_qbss_scoring.score_pcnt3_to_0, SCM_SCORE_INDEX_0); - } window_size = BEST_CANDIDATE_MAX_WEIGHT / score_params->esp_qbss_scoring.num_slot; /* Desired values are from 1 to 15, as 0 is for not present. so do +1 */ - index = qdf_do_div(congestion, window_size) + 1; + index = qdf_do_div(*congestion_pct, window_size) + 1; if (index > score_params->esp_qbss_scoring.num_slot) index = score_params->esp_qbss_scoring.num_slot; @@ -678,6 +686,7 @@ int scm_calculate_bss_score(struct wlan_objmgr_psoc *psoc, int32_t band_score = 0; int32_t nss_score = 0; int32_t congestion_score = 0; + int32_t congestion_pct = 0; int32_t oce_wan_score = 0; uint8_t prorated_pcnt; bool is_vht = false; @@ -759,27 +768,39 @@ int scm_calculate_bss_score(struct wlan_objmgr_psoc *psoc, weight_config->beamforming_cap_weightage; score += beamformee_score; + congestion_score = scm_calculate_congestion_score(entry, score_config, + &congestion_pct); + score += congestion_score; /* - * If AP is on 5Ghz channel , extra weigtage is added to BSS score. - * if RSSI is greater tha 5g rssi threshold or fall in same bucket. - * else give weigtage to 2.4 GH. + * Consider OCE WAN score and band preference score only if + * congestion_pct is greater than CONGESTION_THRSHOLD_FOR_BAND_OCE_SCORE */ - if ((entry->rssi_raw > rssi_pref_5g_rssi_thresh) && !same_bucket) { - if (WLAN_CHAN_IS_5GHZ(entry->channel.chan_idx)) + if (congestion_pct < CONGESTION_THRSHOLD_FOR_BAND_OCE_SCORE) { + /* + * If AP is on 5Ghz channel , extra weigtage is added to BSS + * score. if RSSI is greater tha 5g rssi threshold or fall in + * same bucket else give weigtage to 2.4 GH. + */ + if ((entry->rssi_raw > rssi_pref_5g_rssi_thresh) && + !same_bucket) { + if (WLAN_CHAN_IS_5GHZ(entry->channel.chan_idx)) + band_score = + weight_config->chan_band_weightage * + WLAN_GET_SCORE_PERCENTAGE( + score_config->band_weight_per_index, + SCM_BAND_5G_INDEX); + } else if (WLAN_CHAN_IS_2GHZ(entry->channel.chan_idx)) { band_score = weight_config->chan_band_weightage * - WLAN_GET_SCORE_PERCENTAGE( - score_config->band_weight_per_index, - SCM_BAND_5G_INDEX); - } else if (WLAN_CHAN_IS_2GHZ(entry->channel.chan_idx)) { - band_score = weight_config->chan_band_weightage * WLAN_GET_SCORE_PERCENTAGE( score_config->band_weight_per_index, SCM_BAND_2G_INDEX); - } - score += band_score; + } + score += band_score; - congestion_score = scm_calculate_congestion_score(entry, score_config); - score += congestion_score; + oce_wan_score = scm_calculate_oce_wan_score(entry, + score_config); + score += oce_wan_score; + } sta_nss = scm_get_sta_nss(psoc, entry->channel.chan_idx, score_config->vdev_nss_24g, @@ -794,27 +815,25 @@ int scm_calculate_bss_score(struct wlan_objmgr_psoc *psoc, prorated_pcnt, sta_nss); score += nss_score; - oce_wan_score = scm_calculate_oce_wan_score(entry, score_config); - score += oce_wan_score; - - scm_debug("Self Cap: HT %d VHT %d HE %d VHT_24Ghz %d BF cap %d cb_mode_24g %d cb_mode_5G %d NSS %d", - score_config->ht_cap, score_config->vht_cap, - score_config->he_cap, score_config->vht_24G_cap, - score_config->beamformee_cap, score_config->cb_mode_24G, - score_config->cb_mode_5G, sta_nss); - - scm_debug("Candidate (BSSID: %pM Chan %d) Cap:: rssi=%d HT=%d VHT=%d HE %d su beamformer %d phymode=%d air time fraction %d qbss load %d NSS %d", - entry->bssid.bytes, entry->channel.chan_idx, - entry->rssi_raw, util_scan_entry_htcap(entry) ? 1 : 0, - util_scan_entry_vhtcap(entry) ? 1 : 0, - util_scan_entry_hecap(entry) ? 1 : 0, ap_su_beam_former, - entry->phy_mode, entry->air_time_fraction, - entry->qbss_chan_load, entry->nss); - - scm_debug("Candidate Scores : prorated_pcnt %d rssi %d pcl %d ht %d vht %d he %d beamformee %d bw %d band %d congestion %d nss %d oce wan %d TOTAL score %d", - prorated_pcnt, rssi_score, pcl_score, ht_score, vht_score, - he_score, beamformee_score, bandwidth_score, band_score, - congestion_score, nss_score, oce_wan_score, score); + scm_nofl_debug("Self: HT %d VHT %d HE %d VHT_24Ghz %d BF cap %d cb_mode_24g %d cb_mode_5G %d NSS %d", + score_config->ht_cap, score_config->vht_cap, + score_config->he_cap, score_config->vht_24G_cap, + score_config->beamformee_cap, score_config->cb_mode_24G, + score_config->cb_mode_5G, sta_nss); + + scm_nofl_debug("Candidate(%pM chan %d): rssi %d HT %d VHT %d HE %d su bfer %d phy %d air time frac %d qbss %d cong_pct %d NSS %d", + entry->bssid.bytes, entry->channel.chan_idx, + entry->rssi_raw, util_scan_entry_htcap(entry) ? 1 : 0, + util_scan_entry_vhtcap(entry) ? 1 : 0, + util_scan_entry_hecap(entry) ? 1 : 0, ap_su_beam_former, + entry->phy_mode, entry->air_time_fraction, + entry->qbss_chan_load, congestion_pct, entry->nss); + + scm_nofl_debug("Scores: prorated_pcnt %d rssi %d pcl %d ht %d vht %d he %d bfee %d bw %d band %d congestion %d nss %d oce wan %d TOTAL %d", + prorated_pcnt, rssi_score, pcl_score, ht_score, + vht_score, he_score, beamformee_score, bandwidth_score, + band_score, congestion_score, nss_score, oce_wan_score, + score); entry->bss_score = score; return score; diff --git a/drivers/staging/qca-wifi-host-cmn/umac/scan/core/src/wlan_scan_cache_db.c b/drivers/staging/qca-wifi-host-cmn/umac/scan/core/src/wlan_scan_cache_db.c index cc5a1f974de8..56424b913fb3 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/scan/core/src/wlan_scan_cache_db.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/scan/core/src/wlan_scan_cache_db.c @@ -666,6 +666,7 @@ static QDF_STATUS scm_add_update_entry(struct wlan_objmgr_psoc *psoc, QDF_STATUS status; struct scan_dbs *scan_db; struct wlan_scan_obj *scan_obj; + uint8_t security_type; scan_db = wlan_pdev_get_scan_db(psoc, pdev); if (!scan_db) { @@ -694,6 +695,21 @@ static QDF_STATUS scm_add_update_entry(struct wlan_objmgr_psoc *psoc, is_dup_found = scm_find_duplicate(pdev, scan_obj, scan_db, scan_params, &dup_node); + security_type = scan_params->security_type; + + scm_nofl_debug("Received %s: %pM \"%.*s\" chan %d rssi %d tsf_delta %u seq %d phy %d hidden %d mismatch %d %s%s%s%s", + (scan_params->frm_subtype == MGMT_SUBTYPE_PROBE_RESP) ? + "prb rsp" : "bcn", scan_params->bssid.bytes, + scan_params->ssid.length, scan_params->ssid.ssid, + scan_params->channel.chan_idx, scan_params->rssi_raw, + scan_params->tsf_delta, scan_params->seq_num, + scan_params->phy_mode, scan_params->is_hidden_ssid, + scan_params->channel_mismatch, + security_type & SCAN_SECURITY_TYPE_WPA ? "[WPA]" : "", + security_type & SCAN_SECURITY_TYPE_RSN ? "[RSN]" : "", + security_type & SCAN_SECURITY_TYPE_WAPI ? "[WAPI]" : "", + security_type & SCAN_SECURITY_TYPE_WEP ? "[WEP]" : ""); + if (scan_obj->cb.inform_beacon) scan_obj->cb.inform_beacon(pdev, scan_params); @@ -806,23 +822,17 @@ QDF_STATUS scm_handle_bcn_probe(struct scheduler_msg *msg) scan_entry = scan_node->entry; if (scan_obj->drop_bcn_on_chan_mismatch && - scan_entry->channel_mismatch) { - scm_debug("Drop frame, as channel mismatch Received for from BSSID: %pM Seq Num: %d", - scan_entry->bssid.bytes, - scan_entry->seq_num); + scan_entry->channel_mismatch) { + scm_nofl_debug("Drop frame for chan mismatch %pM Seq Num: %d chan %d RSSI %d", + scan_entry->bssid.bytes, + scan_entry->seq_num, + scan_entry->channel.chan_idx, + scan_entry->rssi_raw); util_scan_free_cache_entry(scan_entry); qdf_mem_free(scan_node); continue; } - scm_nofl_debug("Received %s from BSSID: %pM tsf_delta = %u Seq Num: %d ssid:%.*s, rssi: %d channel %d", - (bcn->frm_type == MGMT_SUBTYPE_PROBE_RESP) ? - "Probe Rsp" : "Beacon", scan_entry->bssid.bytes, - scan_entry->tsf_delta, scan_entry->seq_num, - scan_entry->ssid.length, scan_entry->ssid.ssid, - scan_entry->rssi_raw, - scan_entry->channel.chan_idx); - if (scan_obj->cb.update_beacon) scan_obj->cb.update_beacon(pdev, scan_entry); diff --git a/drivers/staging/qca-wifi-host-cmn/umac/scan/core/src/wlan_scan_filter.c b/drivers/staging/qca-wifi-host-cmn/umac/scan/core/src/wlan_scan_filter.c index a32d2c200df0..db535b3c6efb 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/scan/core/src/wlan_scan_filter.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/scan/core/src/wlan_scan_filter.c @@ -382,16 +382,18 @@ scm_is_rsn_mcast_cipher_match(struct wlan_rsn_ie *rsn, * Return: true if RSN security else false */ static bool scm_is_rsn_security(struct scan_filter *filter, - struct scan_cache_entry *db_entry, - struct security_info *security) + struct scan_cache_entry *db_entry, + struct security_info *security) { int i; uint8_t cipher_type; bool match_any_akm, match = false; enum wlan_auth_type neg_auth = WLAN_NUM_OF_SUPPORT_AUTH_TYPE; + enum wlan_auth_type filter_akm; enum wlan_enc_type neg_mccipher = WLAN_ENCRYPT_TYPE_NONE; struct wlan_rsn_ie rsn = {0}; QDF_STATUS status; + bool is_adaptive_11r; if (!security) return false; @@ -425,11 +427,15 @@ static bool scm_is_rsn_security(struct scan_filter *filter, return false; } + is_adaptive_11r = (db_entry->adaptive_11r_ap && + filter->enable_adaptive_11r); + /* Initializing with false as it has true value already */ match = false; for (i = 0; i < filter->num_of_auth; i++) { - if (filter->auth_type[i] == WLAN_AUTH_TYPE_ANY) + filter_akm = filter->auth_type[i]; + if (filter_akm == WLAN_AUTH_TYPE_ANY) match_any_akm = true; else match_any_akm = false; @@ -440,8 +446,8 @@ static bool scm_is_rsn_security(struct scan_filter *filter, if (scm_is_cipher_match(rsn.akm_suites, rsn.akm_suite_count, WLAN_RSN_SEL(WLAN_AKM_FILS_FT_SHA384))) { - if (match_any_akm || (WLAN_AUTH_TYPE_FT_FILS_SHA384 == - filter->auth_type[i])) { + if (match_any_akm || + (filter_akm == WLAN_AUTH_TYPE_FT_FILS_SHA384)) { neg_auth = WLAN_AUTH_TYPE_FT_FILS_SHA384; match = true; break; @@ -450,8 +456,8 @@ static bool scm_is_rsn_security(struct scan_filter *filter, if (scm_is_cipher_match(rsn.akm_suites, rsn.akm_suite_count, WLAN_RSN_SEL(WLAN_AKM_FILS_FT_SHA256))) { - if (match_any_akm || (WLAN_AUTH_TYPE_FT_FILS_SHA256 == - filter->auth_type[i])) { + if (match_any_akm || + (filter_akm == WLAN_AUTH_TYPE_FT_FILS_SHA256)) { neg_auth = WLAN_AUTH_TYPE_FT_FILS_SHA256; match = true; break; @@ -460,8 +466,8 @@ static bool scm_is_rsn_security(struct scan_filter *filter, if (scm_is_cipher_match(rsn.akm_suites, rsn.akm_suite_count, WLAN_RSN_SEL(WLAN_AKM_FILS_SHA384))) { - if (match_any_akm || (WLAN_AUTH_TYPE_FILS_SHA384 == - filter->auth_type[i])) { + if (match_any_akm || + (filter_akm == WLAN_AUTH_TYPE_FILS_SHA384)) { neg_auth = WLAN_AUTH_TYPE_FILS_SHA384; match = true; break; @@ -470,8 +476,8 @@ static bool scm_is_rsn_security(struct scan_filter *filter, if (scm_is_cipher_match(rsn.akm_suites, rsn.akm_suite_count, WLAN_RSN_SEL(WLAN_AKM_FILS_SHA256))) { - if (match_any_akm || (WLAN_AUTH_TYPE_FILS_SHA256 == - filter->auth_type[i])) { + if (match_any_akm || + (filter_akm == WLAN_AUTH_TYPE_FILS_SHA256)) { neg_auth = WLAN_AUTH_TYPE_FILS_SHA256; match = true; break; @@ -481,8 +487,8 @@ static bool scm_is_rsn_security(struct scan_filter *filter, if (scm_is_cipher_match(rsn.akm_suites, rsn.akm_suite_count, WLAN_RSN_SEL(WLAN_AKM_SAE))) { - if (match_any_akm || (WLAN_AUTH_TYPE_SAE == - filter->auth_type[i])) { + if (match_any_akm || + (filter_akm == WLAN_AUTH_TYPE_SAE)) { neg_auth = WLAN_AUTH_TYPE_SAE; match = true; break; @@ -491,8 +497,8 @@ static bool scm_is_rsn_security(struct scan_filter *filter, if (scm_is_cipher_match(rsn.akm_suites, rsn.akm_suite_count, WLAN_RSN_DPP_AKM)) { - if (match_any_akm || (WLAN_AUTH_TYPE_DPP_RSN == - filter->auth_type[i])) { + if (match_any_akm || + (filter_akm == WLAN_AUTH_TYPE_DPP_RSN)) { neg_auth = WLAN_AUTH_TYPE_DPP_RSN; match = true; break; @@ -502,7 +508,7 @@ static bool scm_is_rsn_security(struct scan_filter *filter, rsn.akm_suite_count, WLAN_RSN_OSEN_AKM)) { if (match_any_akm || - WLAN_AUTH_TYPE_OSEN == filter->auth_type[i]) { + (filter_akm == WLAN_AUTH_TYPE_OSEN)) { neg_auth = WLAN_AUTH_TYPE_OSEN; match = true; break; @@ -511,8 +517,8 @@ static bool scm_is_rsn_security(struct scan_filter *filter, if (scm_is_cipher_match(rsn.akm_suites, rsn.akm_suite_count, WLAN_RSN_SEL(WLAN_AKM_OWE))) { - if (match_any_akm || (WLAN_AUTH_TYPE_OWE == - filter->auth_type[i])) { + if (match_any_akm || + (filter_akm == WLAN_AUTH_TYPE_OWE)) { neg_auth = WLAN_AUTH_TYPE_OWE; match = true; break; @@ -521,8 +527,8 @@ static bool scm_is_rsn_security(struct scan_filter *filter, if (scm_is_cipher_match(rsn.akm_suites, rsn.akm_suite_count, WLAN_RSN_SEL(WLAN_AKM_FT_IEEE8021X))) { - if (match_any_akm || (WLAN_AUTH_TYPE_FT_RSN == - filter->auth_type[i])) { + if (match_any_akm || + (filter_akm == WLAN_AUTH_TYPE_FT_RSN)) { neg_auth = WLAN_AUTH_TYPE_FT_RSN; match = true; break; @@ -532,8 +538,8 @@ static bool scm_is_rsn_security(struct scan_filter *filter, if (scm_is_cipher_match(rsn.akm_suites, rsn.akm_suite_count, WLAN_RSN_SEL(WLAN_AKM_FT_PSK))) { - if (match_any_akm || (WLAN_AUTH_TYPE_FT_RSN_PSK == - filter->auth_type[i])) { + if (match_any_akm || + (filter_akm == WLAN_AUTH_TYPE_FT_RSN_PSK)) { neg_auth = WLAN_AUTH_TYPE_FT_RSN_PSK; match = true; break; @@ -543,8 +549,8 @@ static bool scm_is_rsn_security(struct scan_filter *filter, if (scm_is_cipher_match(rsn.akm_suites, rsn.akm_suite_count, WLAN_RSN_CCKM_AKM)) { - if (match_any_akm || (WLAN_AUTH_TYPE_CCKM_RSN == - filter->auth_type[i])) { + if (match_any_akm || + (filter_akm == WLAN_AUTH_TYPE_CCKM_RSN)) { neg_auth = WLAN_AUTH_TYPE_CCKM_RSN; match = true; break; @@ -554,8 +560,15 @@ static bool scm_is_rsn_security(struct scan_filter *filter, if (scm_is_cipher_match(rsn.akm_suites, rsn.akm_suite_count, WLAN_RSN_SEL(WLAN_AKM_IEEE8021X))) { - if (match_any_akm || (WLAN_AUTH_TYPE_RSN == - filter->auth_type[i])) { + if (is_adaptive_11r && + (filter_akm == WLAN_AUTH_TYPE_FT_RSN)) { + neg_auth = WLAN_AUTH_TYPE_FT_RSN; + match = true; + break; + } + + if (match_any_akm || + (WLAN_AUTH_TYPE_RSN == filter_akm)) { neg_auth = WLAN_AUTH_TYPE_RSN; match = true; break; @@ -565,8 +578,15 @@ static bool scm_is_rsn_security(struct scan_filter *filter, if (scm_is_cipher_match(rsn.akm_suites, rsn.akm_suite_count, WLAN_RSN_SEL(WLAN_AKM_PSK))) { - if (match_any_akm || (WLAN_AUTH_TYPE_RSN_PSK == - filter->auth_type[i])) { + if (is_adaptive_11r && + (filter_akm == WLAN_AUTH_TYPE_FT_RSN_PSK)) { + neg_auth = WLAN_AUTH_TYPE_FT_RSN_PSK; + match = true; + break; + } + + if (match_any_akm || + (filter_akm == WLAN_AUTH_TYPE_RSN_PSK)) { neg_auth = WLAN_AUTH_TYPE_RSN_PSK; match = true; break; @@ -576,10 +596,16 @@ static bool scm_is_rsn_security(struct scan_filter *filter, if (scm_is_cipher_match(rsn.akm_suites, rsn.akm_suite_count, WLAN_RSN_SEL(WLAN_AKM_SHA256_PSK))) { - if (match_any_akm || (WLAN_AUTH_TYPE_RSN_PSK_SHA256 == - filter->auth_type[i])) { - neg_auth = - WLAN_AUTH_TYPE_RSN_PSK_SHA256; + if (is_adaptive_11r && + (filter_akm == WLAN_AUTH_TYPE_FT_RSN_PSK)) { + neg_auth = WLAN_AUTH_TYPE_FT_RSN_PSK; + match = true; + break; + } + + if (match_any_akm || + (filter_akm == WLAN_AUTH_TYPE_RSN_PSK_SHA256)) { + neg_auth = WLAN_AUTH_TYPE_RSN_PSK_SHA256; match = true; break; } @@ -588,10 +614,16 @@ static bool scm_is_rsn_security(struct scan_filter *filter, if (scm_is_cipher_match(rsn.akm_suites, rsn.akm_suite_count, WLAN_RSN_SEL(WLAN_AKM_SHA256_IEEE8021X))) { - if (match_any_akm || (WLAN_AUTH_TYPE_RSN_8021X_SHA256 == - filter->auth_type[i])) { - neg_auth = - WLAN_AUTH_TYPE_RSN_8021X_SHA256; + if (is_adaptive_11r && + (filter_akm == WLAN_AUTH_TYPE_FT_RSN)) { + neg_auth = WLAN_AUTH_TYPE_FT_RSN; + match = true; + break; + } + + if (match_any_akm || + (filter_akm == WLAN_AUTH_TYPE_RSN_8021X_SHA256)) { + neg_auth = WLAN_AUTH_TYPE_RSN_8021X_SHA256; match = true; break; } @@ -600,8 +632,7 @@ static bool scm_is_rsn_security(struct scan_filter *filter, rsn.akm_suite_count, WLAN_RSN_SEL(WLAN_AKM_SUITEB_EAP_SHA256))) { if (match_any_akm || - (WLAN_AUTH_TYPE_SUITEB_EAP_SHA256 == - filter->auth_type[i])) { + filter_akm == WLAN_AUTH_TYPE_SUITEB_EAP_SHA256) { neg_auth = WLAN_AUTH_TYPE_SUITEB_EAP_SHA256; match = true; break; @@ -611,13 +642,34 @@ static bool scm_is_rsn_security(struct scan_filter *filter, rsn.akm_suite_count, WLAN_RSN_SEL(WLAN_AKM_SUITEB_EAP_SHA384))) { if (match_any_akm || - (WLAN_AUTH_TYPE_SUITEB_EAP_SHA384 == - filter->auth_type[i])) { + filter_akm == WLAN_AUTH_TYPE_SUITEB_EAP_SHA384) { neg_auth = WLAN_AUTH_TYPE_SUITEB_EAP_SHA384; match = true; break; } } + + if (scm_is_cipher_match(rsn.akm_suites, rsn.akm_suite_count, + WLAN_RSN_SEL(WLAN_AKM_FT_SAE))) { + if (match_any_akm || + filter_akm == WLAN_AUTH_TYPE_FT_SAE) { + neg_auth = WLAN_AUTH_TYPE_FT_SAE; + match = true; + break; + } + } + + if (scm_is_cipher_match(rsn.akm_suites, rsn.akm_suite_count, + WLAN_RSN_SEL( + WLAN_AKM_FT_SUITEB_EAP_SHA384))) { + if (match_any_akm || + (filter_akm == + WLAN_AUTH_TYPE_FT_SUITEB_EAP_SHA384)) { + neg_auth = WLAN_AUTH_TYPE_FT_SUITEB_EAP_SHA384; + match = true; + break; + } + } } if (!match) { @@ -901,8 +953,8 @@ static bool scm_is_wapi_security(struct scan_filter *filter, * Return: true if any security else false */ static bool scm_is_def_security(struct scan_filter *filter, - struct scan_cache_entry *db_entry, - struct security_info *security) + struct scan_cache_entry *db_entry, + struct security_info *security) { /* It is allowed to match anything. Try the more secured ones first. */ @@ -1023,8 +1075,8 @@ static bool scm_is_fils_config_match(struct scan_filter *filter, * Return: true if security match else false */ static bool scm_is_security_match(struct scan_filter *filter, - struct scan_cache_entry *db_entry, - struct security_info *security) + struct scan_cache_entry *db_entry, + struct security_info *security) { int i; bool match = false; @@ -1056,8 +1108,8 @@ static bool scm_is_security_match(struct scan_filter *filter, case WLAN_ENCRYPT_TYPE_AES_GCMP: case WLAN_ENCRYPT_TYPE_AES_GCMP_256: /* First check if there is a RSN match */ - match = scm_is_rsn_security(filter, - db_entry, &local_security); + match = scm_is_rsn_security(filter, db_entry, + &local_security); /* If not RSN, then check WPA match */ if (!match) match = scm_is_wpa_security(filter, @@ -1069,23 +1121,22 @@ static bool scm_is_security_match(struct scan_filter *filter, break; case WLAN_ENCRYPT_TYPE_ANY: default: - match = scm_is_def_security(filter, - db_entry, &local_security); + match = scm_is_def_security(filter, db_entry, + &local_security); break; } } if (match && security) - qdf_mem_copy(security, - &local_security, sizeof(*security)); + qdf_mem_copy(security, &local_security, sizeof(*security)); return match; } bool scm_filter_match(struct wlan_objmgr_psoc *psoc, - struct scan_cache_entry *db_entry, - struct scan_filter *filter, - struct security_info *security) + struct scan_cache_entry *db_entry, + struct scan_filter *filter, + struct security_info *security) { int i; bool match = false; @@ -1169,15 +1220,13 @@ bool scm_filter_match(struct wlan_objmgr_psoc *psoc, /* TODO match phyMode */ if (!filter->ignore_auth_enc_type && - !scm_is_security_match(filter, - db_entry, security)) { + !scm_is_security_match(filter, db_entry, security)) { scm_debug("%pM : Ignore as security profile didn't match", db_entry->bssid.bytes); return false; } - if (!util_is_bss_type_match(filter->bss_type, - db_entry->cap_info)) { + if (!util_is_bss_type_match(filter->bss_type, db_entry->cap_info)) { scm_debug("%pM : Ignore as bss type didn't match cap_info %x bss_type %d", db_entry->bssid.bytes, db_entry->cap_info.value, filter->bss_type); diff --git a/drivers/staging/qca-wifi-host-cmn/umac/scan/core/src/wlan_scan_manager.c b/drivers/staging/qca-wifi-host-cmn/umac/scan/core/src/wlan_scan_manager.c index 4961adff2192..11261c1060f9 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/scan/core/src/wlan_scan_manager.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/scan/core/src/wlan_scan_manager.c @@ -40,8 +40,6 @@ scm_scan_free_scan_request_mem(struct scan_start_request *req) QDF_ASSERT(0); return QDF_STATUS_E_FAILURE; } - scm_debug("freed scan request: 0x%pK, scan_id: %d, requester: %d", - req, req->scan_req.scan_id, req->scan_req.scan_req_id); /* Free vendor(extra) ie */ ie = req->scan_req.extraie.ptr; if (ie) { @@ -149,10 +147,6 @@ static void scm_scan_post_event(struct wlan_objmgr_vdev *vdev, cb_handlers = &(pdev_ev_handler->cb_handlers[0]); requesters = scan->requesters; - scm_debug("vdev: %d, type: %d, reason: %d, freq: %d, req: %d, scanid: %d", - event->vdev_id, event->type, event->reason, event->chan_freq, - event->requester, event->scan_id); - listeners = qdf_mem_malloc_atomic(sizeof(*listeners)); if (!listeners) { scm_warn("couldn't allocate listeners list"); @@ -179,11 +173,8 @@ static void scm_scan_post_event(struct wlan_objmgr_vdev *vdev, qdf_spin_unlock_bh(&scan->lock); /* notify all interested handlers */ - for (i = 0; i < listeners->count; i++) { - scm_debug("func: 0x%pK, arg: 0x%pK", - listeners->cb[i].func, listeners->cb[i].arg); + for (i = 0; i < listeners->count; i++) listeners->cb[i].func(vdev, event, listeners->cb[i].arg); - } qdf_mem_free(listeners); } @@ -313,10 +304,6 @@ scm_scan_serialize_callback(struct wlan_serialization_command *cmd, } req = cmd->umac_cmd; - scm_debug("reason:%d, reqid:%d, scanid:%d, vdevid:%d, vdev:0x%pK", - reason, req->scan_req.scan_req_id, req->scan_req.scan_id, - req->scan_req.vdev_id, req->vdev); - if (!req->vdev) { scm_err("NULL vdev. req:0x%pK, reason:%d\n", req, reason); QDF_ASSERT(0); @@ -369,6 +356,58 @@ scm_scan_serialize_callback(struct wlan_serialization_command *cmd, return status; } +static inline void scm_print_scan_req_info(struct scan_req_params *req) +{ + uint32_t buff_len; + char *chan_buff; + uint32_t len = 0; + uint8_t idx, count = 0; + struct chan_list *chan_lst; +#define MAX_SCAN_FREQ_TO_PRINT 60 + + scm_nofl_debug("Scan start: scan id %d vdev %d Dwell time: act %d pass %d act_2G %d, probe time %d n_probes %d flags %x ext_flag %x events %x policy %d wide_bw %d pri %d", + req->scan_id, req->vdev_id, req->dwell_time_active, + req->dwell_time_passive, req->dwell_time_active_2g, + req->repeat_probe_time, req->n_probes, req->scan_flags, + req->scan_ctrl_flags_ext, req->scan_events, + req->scan_policy_type, req->scan_f_wide_band, + req->scan_priority); + + for (idx = 0; idx < req->num_ssids; idx++) + scm_nofl_debug("SSID[%d]: %.*s", idx, req->ssid[idx].length, + req->ssid[idx].ssid); + + chan_lst = &req->chan_list; + + if (!chan_lst->num_chan) + return; + /* + * Buffer of (num channl * 5) + 1 to consider the 4 char freq and + * 1 space after it for each channel and 1 to end the string with NULL. + */ + buff_len = + (QDF_MIN(MAX_SCAN_FREQ_TO_PRINT, chan_lst->num_chan) * 5) + 1; + chan_buff = qdf_mem_malloc(buff_len); + if (!chan_buff) + return; + scm_nofl_debug("Total freq %d", chan_lst->num_chan); + for (idx = 0; idx < chan_lst->num_chan; idx++) { + len += qdf_scnprintf(chan_buff + len, buff_len - len, "%d ", + chan_lst->chan[idx].freq); + count++; + if (count >= MAX_SCAN_FREQ_TO_PRINT) { + /* Print the MAX_SCAN_FREQ_TO_PRINT channels */ + scm_nofl_debug("Freq list: %s", chan_buff); + len = 0; + count = 0; + } + } + if (len) + scm_nofl_debug("Freq list: %s", chan_buff); + + qdf_mem_free(chan_buff); +} + QDF_STATUS scm_scan_start_req(struct scheduler_msg *msg) { @@ -418,6 +457,8 @@ scm_scan_start_req(struct scheduler_msg *msg) goto err; } + scm_print_scan_req_info(&req->scan_req); + cmd.cmd_type = WLAN_SER_CMD_SCAN; cmd.cmd_id = req->scan_req.scan_id; cmd.cmd_cb = scm_scan_serialize_callback; @@ -431,17 +472,11 @@ scm_scan_start_req(struct scheduler_msg *msg) if (scan_obj->disable_timeout) cmd.cmd_timeout_duration = 0; - scm_debug("req: 0x%pK, reqid: %d, scanid: %d, vdevid: %d", - req, req->scan_req.scan_req_id, req->scan_req.scan_id, - req->scan_req.vdev_id); - qdf_mtrace(QDF_MODULE_ID_SCAN, QDF_MODULE_ID_SERIALIZATION, WLAN_SER_CMD_SCAN, req->vdev->vdev_objmgr.vdev_id, req->scan_req.scan_id); ser_cmd_status = wlan_serialization_request(&cmd); - scm_debug("wlan_serialization_request status:%d", ser_cmd_status); - switch (ser_cmd_status) { case WLAN_SER_CMD_PENDING: /* command moved to pending list.Do nothing */ @@ -449,13 +484,8 @@ scm_scan_start_req(struct scheduler_msg *msg) case WLAN_SER_CMD_ACTIVE: /* command moved to active list. Do nothing */ break; - case WLAN_SER_CMD_DENIED_LIST_FULL: - case WLAN_SER_CMD_DENIED_RULES_FAILED: - case WLAN_SER_CMD_DENIED_UNSPECIFIED: - goto err; default: - QDF_ASSERT(0); - status = QDF_STATUS_E_INVAL; + scm_debug("ser cmd status %d", ser_cmd_status); goto err; } @@ -764,8 +794,7 @@ scm_scan_event_handler(struct scheduler_msg *msg) if (scan_start_req->scan_req.scan_req_id != event->requester) { scm_err("req ID mismatch, scan_req_id:%d, event_req_id:%d", - scan_start_req->scan_req.scan_req_id, - event->requester); + scan_start_req->scan_req.scan_req_id, event->requester); goto exit; } @@ -801,6 +830,7 @@ QDF_STATUS scm_scan_event_flush_callback(struct scheduler_msg *msg) { struct wlan_objmgr_vdev *vdev; struct scan_event_info *event_info; + struct scan_event *event; if (!msg || !msg->bodyptr) { scm_err("msg or msg->bodyptr is NULL"); @@ -809,6 +839,11 @@ QDF_STATUS scm_scan_event_flush_callback(struct scheduler_msg *msg) event_info = msg->bodyptr; vdev = event_info->vdev; + event = &event_info->event; + + scm_debug("Flush scan event vdev %d type %d reason %d freq: %d req %d scanid %d", + event->vdev_id, event->type, event->reason, event->chan_freq, + event->requester, event->scan_id); /* free event info memory */ qdf_mem_free(event_info); diff --git a/drivers/staging/qca-wifi-host-cmn/umac/scan/dispatcher/inc/wlan_scan_public_structs.h b/drivers/staging/qca-wifi-host-cmn/umac/scan/dispatcher/inc/wlan_scan_public_structs.h index e68e1ac80ed2..6a369610f348 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/scan/dispatcher/inc/wlan_scan_public_structs.h +++ b/drivers/staging/qca-wifi-host-cmn/umac/scan/dispatcher/inc/wlan_scan_public_structs.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -157,6 +157,8 @@ struct element_info { * @fils_indication: pointer to FILS indication ie * @esp: pointer to ESP indication ie * @mbo_oce: pointer to mbo/oce indication ie + * @adaptive_11r: pointer to adaptive 11r IE + * @single_pmk: Pionter to sae single pmk IE */ struct ie_list { uint8_t *tim; @@ -203,6 +205,8 @@ struct ie_list { uint8_t *esp; uint8_t *mbo_oce; uint8_t *muedca; + uint8_t *adaptive_11r; + uint8_t *single_pmk; }; enum scan_entry_connection_state { @@ -264,6 +268,11 @@ struct security_info { enum wlan_auth_type auth_type; }; +#define SCAN_SECURITY_TYPE_WEP 0x01 +#define SCAN_SECURITY_TYPE_WPA 0x02 +#define SCAN_SECURITY_TYPE_WAPI 0x04 +#define SCAN_SECURITY_TYPE_RSN 0x08 + /** * struct scan_cache_entry: structure containing scan entry * @frm_subtype: updated from beacon/probe @@ -271,6 +280,7 @@ struct security_info { * @mac_addr: mac address * @ssid: ssid * @is_hidden_ssid: is AP having hidden ssid. + * @security_type: security supported * @seq_num: sequence number * @phy_mode: Phy mode of the AP * @avg_rssi: Average RSSI fof the AP @@ -284,6 +294,7 @@ struct security_info { * @qbss_chan_load: Qbss channel load * @nss: supported NSS information * @is_p2p_ssid: is P2P entry + * @adaptive_11r_ap: flag to check if AP supports adaptive 11r * @scan_entry_time: boottime in microsec when last beacon/probe is received * @rssi_timestamp: boottime in microsec when RSSI was updated * @hidden_ssid_timestamp: boottime in microsec when hidden @@ -308,6 +319,7 @@ struct scan_cache_entry { struct qdf_mac_addr mac_addr; struct wlan_ssid ssid; bool is_hidden_ssid; + uint8_t security_type; uint16_t seq_num; enum wlan_phymode phy_mode; int32_t avg_rssi; @@ -324,6 +336,7 @@ struct scan_cache_entry { uint8_t qbss_chan_load; uint8_t nss; bool is_p2p; + bool adaptive_11r_ap; qdf_time_t scan_entry_time; qdf_time_t rssi_timestamp; qdf_time_t hidden_ssid_timestamp; @@ -506,6 +519,7 @@ struct fils_filter_info { /** * @bss_scoring_required :- flag to bypass scoring filtered results + * @enable_adaptive_11r: flag to check if adaptive 11r ini is enabled * @age_threshold: If set return entry which are newer than the age_threshold * @p2p_results: If only p2p entries is required * @rrm_measurement_filter: For measurement reports.if set, only SSID, BSSID @@ -543,6 +557,7 @@ struct fils_filter_info { */ struct scan_filter { bool bss_scoring_required; + bool enable_adaptive_11r; uint32_t age_threshold; uint32_t p2p_results; uint32_t rrm_measurement_filter; diff --git a/drivers/staging/qca-wifi-host-cmn/umac/scan/dispatcher/inc/wlan_scan_utils_api.h b/drivers/staging/qca-wifi-host-cmn/umac/scan/dispatcher/inc/wlan_scan_utils_api.h index 52b570d5dd33..0106b76023df 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/scan/dispatcher/inc/wlan_scan_utils_api.h +++ b/drivers/staging/qca-wifi-host-cmn/umac/scan/dispatcher/inc/wlan_scan_utils_api.h @@ -653,6 +653,8 @@ util_scan_copy_beacon_data(struct scan_cache_entry *new_entry, old_ptr, new_ptr); ie_lst->esp = conv_ptr(ie_lst->esp, old_ptr, new_ptr); ie_lst->mbo_oce = conv_ptr(ie_lst->mbo_oce, old_ptr, new_ptr); + ie_lst->adaptive_11r = conv_ptr(ie_lst->adaptive_11r, old_ptr, new_ptr); + ie_lst->single_pmk = conv_ptr(ie_lst->single_pmk, old_ptr, new_ptr); return QDF_STATUS_SUCCESS; } @@ -789,6 +791,37 @@ util_scan_entry_rsn(struct scan_cache_entry *scan_entry) return scan_entry->ie_list.rsn; } +/** + * util_scan_entry_adaptive_11r()- function to read adaptive 11r Vendor IE + * @scan_entry: scan entry + * + * API, function to read adaptive 11r IE + * + * Return: apaptive 11r ie or NULL if ie is not present + */ +static inline uint8_t* +util_scan_entry_adaptive_11r(struct scan_cache_entry *scan_entry) +{ + return scan_entry->ie_list.adaptive_11r; +} + +/** + * util_scan_entry_single_pmk()- function to read single pmk Vendor IE + * @scan_entry: scan entry + * + * API, function to read adaptive 11r IE + * + * Return: true if single_pmk ie is present or false if ie is not present + */ +static inline bool +util_scan_entry_single_pmk(struct scan_cache_entry *scan_entry) +{ + if(scan_entry->ie_list.single_pmk) + return true; + + return false; +} + /** * util_scan_get_rsn_len()- function to read rsn IE length if present * @scan_entry: scan entry diff --git a/drivers/staging/qca-wifi-host-cmn/umac/scan/dispatcher/src/wlan_scan_tgt_api.c b/drivers/staging/qca-wifi-host-cmn/umac/scan/dispatcher/src/wlan_scan_tgt_api.c index 009ee387ce86..11598e81c88c 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/scan/dispatcher/src/wlan_scan_tgt_api.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/scan/dispatcher/src/wlan_scan_tgt_api.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -228,9 +228,6 @@ tgt_scan_event_handler(struct wlan_objmgr_psoc *psoc, scm_err("psoc: 0x%pK, event_info: 0x%pK", psoc, event_info); return QDF_STATUS_E_NULL_VALUE; } - scm_debug("vdev: %d, type: %d, reason: %d, freq: %d, req: %d, scanid: %d", - vdev_id, event->type, event->reason, event->chan_freq, - event->requester, event->scan_id); event_info->vdev = wlan_objmgr_get_vdev_by_id_from_psoc(psoc, diff --git a/drivers/staging/qca-wifi-host-cmn/umac/scan/dispatcher/src/wlan_scan_ucfg_api.c b/drivers/staging/qca-wifi-host-cmn/umac/scan/dispatcher/src/wlan_scan_ucfg_api.c index d9f130687d52..6203bcd664c5 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/scan/dispatcher/src/wlan_scan_ucfg_api.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/scan/dispatcher/src/wlan_scan_ucfg_api.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -33,6 +33,7 @@ #include "../../core/src/wlan_scan_main.h" #include "../../core/src/wlan_scan_manager.h" #include "../../core/src/wlan_scan_cache_db.h" +#include"nan_ucfg_api.h" #ifdef WLAN_POWER_MANAGEMENT_OFFLOAD #include #endif @@ -463,7 +464,8 @@ ucfg_scan_update_pno_config(struct pno_def_config *pno, * Return: void */ static void -ucfg_scan_update_dbs_scan_ctrl_ext_flag(struct scan_start_request *req) +ucfg_scan_update_dbs_scan_ctrl_ext_flag(struct scan_start_request *req, + bool is_ndp_active) { struct wlan_objmgr_psoc *psoc; uint32_t scan_dbs_policy = SCAN_DBS_POLICY_DEFAULT; @@ -471,13 +473,17 @@ ucfg_scan_update_dbs_scan_ctrl_ext_flag(struct scan_start_request *req) psoc = wlan_vdev_get_psoc(req->vdev); if (!policy_mgr_is_hw_dbs_capable(psoc)) { - scm_debug("dbs disabled, going for non-dbs scan"); scan_dbs_policy = SCAN_DBS_POLICY_FORCE_NONDBS; goto end; } if (!ucfg_scan_cfg_honour_nl_scan_policy_flags(psoc)) { - scm_debug("nl scan policy flags not honoured, goto end"); + scm_debug_rl("nl scan policy flags not honoured, goto end"); + goto end; + } + + if (is_ndp_active) { + scm_debug("NDP active, go for DBS scan "); goto end; } @@ -497,8 +503,6 @@ ucfg_scan_update_dbs_scan_ctrl_ext_flag(struct scan_start_request *req) req->scan_req.scan_ctrl_flags_ext |= ((scan_dbs_policy << SCAN_FLAG_EXT_DBS_SCAN_POLICY_BIT) & SCAN_FLAG_EXT_DBS_SCAN_POLICY_MASK); - scm_debug("scan_ctrl_flags_ext: 0x%x", - req->scan_req.scan_ctrl_flags_ext); } /** @@ -776,6 +780,46 @@ static void ucfg_scan_req_update_concurrency_params( } } +/** + * scm_scan_chlist_concurrency_modify() - modify chan list to skip 5G if + * required + * @vdev: vdev object + * @req: scan request + * + * Check and skip 5G chan list based on DFS AP present and current hw mode. + * + * Return: void + */ +static inline void scm_scan_chlist_concurrency_modify( + struct wlan_objmgr_vdev *vdev, struct scan_start_request *req) +{ + struct wlan_objmgr_psoc *psoc; + uint32_t i; + uint32_t num_scan_channels; + + psoc = wlan_vdev_get_psoc(vdev); + if (!psoc) + return; + /* do this only for STA and P2P-CLI mode */ + if (!(wlan_vdev_mlme_get_opmode(req->vdev) == QDF_STA_MODE) && + !(wlan_vdev_mlme_get_opmode(req->vdev) == QDF_P2P_CLIENT_MODE)) + return; + if (!policy_mgr_scan_trim_5g_chnls_for_dfs_ap(psoc)) + return; + num_scan_channels = 0; + for (i = 0; i < req->scan_req.chan_list.num_chan; i++) { + if (WLAN_REG_IS_5GHZ_CH_FREQ( + req->scan_req.chan_list.chan[i].freq)) { + continue; + } + req->scan_req.chan_list.chan[num_scan_channels++] = + req->scan_req.chan_list.chan[i]; + } + if (num_scan_channels < req->scan_req.chan_list.num_chan) + scm_debug("5g chan skipped (%d, %d)", + req->scan_req.chan_list.num_chan, num_scan_channels); + req->scan_req.chan_list.num_chan = num_scan_channels; +} #else static inline void ucfg_scan_req_update_concurrency_params( struct wlan_objmgr_vdev *vdev, struct scan_start_request *req, @@ -787,7 +831,11 @@ ucfg_update_passive_dwell_time(struct wlan_objmgr_vdev *vdev, struct scan_start_request *req) {} static inline void ucfg_scan_update_dbs_scan_ctrl_ext_flag( - struct scan_start_request *req) {} + struct scan_start_request *req, bool is_ndp_active) {} +static inline void scm_scan_chlist_concurrency_modify( + struct wlan_objmgr_vdev *vdev, struct scan_start_request *req) +{ +} #endif QDF_STATUS @@ -864,16 +912,26 @@ ucfg_update_channel_list(struct scan_start_request *req, return; for (i = 0; i < req->scan_req.chan_list.num_chan; i++) { - if (wlan_reg_is_dfs_ch(pdev, wlan_reg_freq_to_chan(pdev, - req->scan_req.chan_list. - chan[i].freq))) + uint32_t freq; + uint32_t chan; + + freq = req->scan_req.chan_list.chan[i].freq; + chan = wlan_reg_freq_to_chan(pdev, freq); + + if (wlan_reg_chan_has_dfs_attribute(pdev, chan)) { + scm_nofl_debug("Skip DFS chan %d", chan); continue; + } + req->scan_req.chan_list.chan[num_scan_channels++] = req->scan_req.chan_list.chan[i]; } req->scan_req.chan_list.num_chan = num_scan_channels; + scm_scan_chlist_concurrency_modify(req->vdev, req); } +#define SCM_ACTIVE_DWELL_TIME_NAN 40 + /** * ucfg_scan_req_update_params() - update scan req params depending on modes * and scan type. @@ -890,6 +948,7 @@ ucfg_scan_req_update_params(struct wlan_objmgr_vdev *vdev, struct chan_list *custom_chan_list; struct wlan_objmgr_pdev *pdev; uint8_t pdev_id; + bool is_ndp_active = false; /* Ensure correct number of probes are sent on active channel */ if (!req->scan_req.repeat_probe_time) @@ -969,7 +1028,11 @@ ucfg_scan_req_update_params(struct wlan_objmgr_vdev *vdev, if (!req->scan_req.scan_f_passive) ucfg_update_passive_dwell_time(vdev, req); - ucfg_scan_update_dbs_scan_ctrl_ext_flag(req); + + pdev = wlan_vdev_get_pdev(vdev); + if (wlan_nan_is_ndp_peer_active(pdev)) + is_ndp_active = true; + ucfg_scan_update_dbs_scan_ctrl_ext_flag(req, is_ndp_active); /* * No need to update conncurrency parmas if req is passive scan on @@ -982,13 +1045,22 @@ ucfg_scan_req_update_params(struct wlan_objmgr_vdev *vdev, /* Set wide band flag if enabled. This will cause * phymode TLV being sent to FW. */ - pdev = wlan_vdev_get_pdev(vdev); pdev_id = wlan_objmgr_pdev_get_pdev_id(pdev); if (ucfg_scan_get_wide_band_scan(pdev)) req->scan_req.scan_f_wide_band = true; else req->scan_req.scan_f_wide_band = false; + if (is_ndp_active) { + req->scan_req.dwell_time_active = + QDF_MIN(req->scan_req.dwell_time_active, + SCM_ACTIVE_DWELL_TIME_NAN); + req->scan_req.dwell_time_active_2g = + QDF_MIN(req->scan_req.dwell_time_active_2g, + SCM_ACTIVE_DWELL_TIME_NAN); + scm_debug("NDP active modify dwell time 2ghz %d", + req->scan_req.dwell_time_active_2g); + } /* Overwrite scan channles with custom scan channel * list if configured. */ @@ -1000,13 +1072,6 @@ ucfg_scan_req_update_params(struct wlan_objmgr_vdev *vdev, ucfg_scan_init_chanlist_params(req, 0, NULL, NULL); ucfg_update_channel_list(req, scan_obj); - scm_debug("dwell time: active %d, passive %d, repeat_probe_time %d " - "n_probes %d flags_ext %x, wide_bw_scan: %d", - req->scan_req.dwell_time_active, - req->scan_req.dwell_time_passive, - req->scan_req.repeat_probe_time, req->scan_req.n_probes, - req->scan_req.scan_ctrl_flags_ext, - req->scan_req.scan_f_wide_band); } QDF_STATUS @@ -1016,7 +1081,6 @@ ucfg_scan_start(struct scan_start_request *req) QDF_STATUS status; struct wlan_scan_obj *scan_obj; struct wlan_objmgr_pdev *pdev; - uint8_t idx; if (!req || !req->vdev) { scm_err("req or vdev within req is NULL"); @@ -1045,14 +1109,10 @@ ucfg_scan_start(struct scan_start_request *req) return QDF_STATUS_E_AGAIN; } - scm_debug("reqid: %d, scanid: %d, vdevid: %d", - req->scan_req.scan_req_id, req->scan_req.scan_id, - req->scan_req.vdev_id); - ucfg_scan_req_update_params(req->vdev, req, scan_obj); if (!req->scan_req.chan_list.num_chan) { - scm_err("0 channel to scan, reject scan"); + scm_err("Reject 0 channel Scan"); scm_scan_free_scan_request_mem(req); return QDF_STATUS_E_NULL_VALUE; } @@ -1068,13 +1128,6 @@ ucfg_scan_start(struct scan_start_request *req) return status; } - scm_info("request to scan %d channels", - req->scan_req.chan_list.num_chan); - for (idx = 0; idx < req->scan_req.chan_list.num_chan; idx++) - scm_debug("chan[%d]: freq:%d, phymode:%d", idx, - req->scan_req.chan_list.chan[idx].freq, - req->scan_req.chan_list.chan[idx].phymode); - msg.bodyptr = req; msg.callback = scm_scan_start_req; msg.flush_callback = scm_scan_start_flush_callback; @@ -1184,9 +1237,6 @@ ucfg_scan_cancel(struct scan_cancel_request *req) qdf_mem_free(req); return QDF_STATUS_E_NULL_VALUE; } - scm_debug("reqid: %d, scanid: %d, vdevid: %d, type: %d", - req->cancel_req.requester, req->cancel_req.scan_id, - req->cancel_req.vdev_id, req->cancel_req.req_type); status = wlan_objmgr_vdev_try_get_ref(req->vdev, WLAN_SCAN_ID); if (QDF_IS_STATUS_ERROR(status)) { @@ -1805,28 +1855,23 @@ ucfg_scan_init_chanlist_params(struct scan_start_request *req, reg_chan_list = qdf_mem_malloc_atomic(NUM_CHANNELS * sizeof(struct regulatory_channel)); if (!reg_chan_list) { - scm_err("Couldn't allocate reg_chan_list memory"); status = QDF_STATUS_E_NOMEM; goto end; } scan_freqs = qdf_mem_malloc_atomic(sizeof(uint32_t) * max_chans); if (!scan_freqs) { - scm_err("Couldn't allocate scan_freqs memory"); status = QDF_STATUS_E_NOMEM; goto end; } status = ucfg_reg_get_current_chan_list(pdev, reg_chan_list); - if (QDF_IS_STATUS_ERROR(status)) { - scm_err("Couldn't get current chan list"); + if (QDF_IS_STATUS_ERROR(status)) goto end; - } + status = wlan_reg_get_freq_range(pdev, &low_2g, &high_2g, &low_5g, &high_5g); - if (QDF_IS_STATUS_ERROR(status)) { - scm_err("Couldn't get frequency range"); + if (QDF_IS_STATUS_ERROR(status)) goto end; - } for (idx = 0, num_chans = 0; (idx < NUM_CHANNELS && num_chans < max_chans); idx++) @@ -1847,7 +1892,7 @@ ucfg_scan_init_chanlist_params(struct scan_start_request *req, goto end; } if (!chan_list) { - scm_err("null chan_list while num_chans: %d", num_chans); + scm_info("null chan_list while num_chans: %d", num_chans); status = QDF_STATUS_E_NULL_VALUE; goto end; } @@ -1876,10 +1921,6 @@ ucfg_scan_init_chanlist_params(struct scan_start_request *req, else req->scan_req.chan_list.chan[idx].phymode = SCAN_PHY_MODE_11A; - - scm_debug("chan[%d]: freq:%d, phymode:%d", idx, - req->scan_req.chan_list.chan[idx].freq, - req->scan_req.chan_list.chan[idx].phymode); } end: diff --git a/drivers/staging/qca-wifi-host-cmn/umac/scan/dispatcher/src/wlan_scan_utils_api.c b/drivers/staging/qca-wifi-host-cmn/umac/scan/dispatcher/src/wlan_scan_utils_api.c index a6a031889691..3b07a19081ed 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/scan/dispatcher/src/wlan_scan_utils_api.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/scan/dispatcher/src/wlan_scan_utils_api.c @@ -199,17 +199,16 @@ util_scan_get_phymode_5g(struct scan_cache_entry *scan_params) if (htcap) ht_cap = le16toh(htcap->hc_cap); + if (ht_cap & WLAN_HTCAP_C_CHWIDTH40) + phymode = WLAN_PHYMODE_11NA_HT40; + else + phymode = WLAN_PHYMODE_11NA_HT20; + if (util_scan_entry_vhtcap(scan_params) && vhtop) { switch (vhtop->vht_op_chwidth) { case WLAN_VHTOP_CHWIDTH_2040: - if ((ht_cap & WLAN_HTCAP_C_CHWIDTH40) && - (htinfo->hi_extchoff == - WLAN_HTINFO_EXTOFFSET_ABOVE)) - phymode = WLAN_PHYMODE_11AC_VHT40PLUS; - else if ((ht_cap & WLAN_HTCAP_C_CHWIDTH40) && - (htinfo->hi_extchoff == - WLAN_HTINFO_EXTOFFSET_BELOW)) - phymode = WLAN_PHYMODE_11AC_VHT40MINUS; + if (ht_cap & WLAN_HTCAP_C_CHWIDTH40) + phymode = WLAN_PHYMODE_11AC_VHT40; else phymode = WLAN_PHYMODE_11AC_VHT20; break; @@ -230,16 +229,10 @@ util_scan_get_phymode_5g(struct scan_cache_entry *scan_params) default: scm_err("bad channel: %d", vhtop->vht_op_chwidth); + phymode = WLAN_PHYMODE_11AC_VHT20; break; } - } else if ((ht_cap & WLAN_HTCAP_C_CHWIDTH40) && - (htinfo->hi_extchoff == WLAN_HTINFO_EXTOFFSET_ABOVE)) - phymode = WLAN_PHYMODE_11NA_HT40PLUS; - else if ((ht_cap & WLAN_HTCAP_C_CHWIDTH40) && - (htinfo->hi_extchoff == WLAN_HTINFO_EXTOFFSET_BELOW)) - phymode = WLAN_PHYMODE_11NA_HT40MINUS; - else - phymode = WLAN_PHYMODE_11NA_HT20; + } return phymode; } @@ -288,6 +281,29 @@ util_scan_get_phymode_2g(struct scan_cache_entry *scan_params) } } + /* Check for VHT only if HT cap is present */ + if (!IS_WLAN_PHYMODE_HT(phymode)) + return phymode; + + if (util_scan_entry_vhtcap(scan_params) && vhtop) { + switch (vhtop->vht_op_chwidth) { + case WLAN_VHTOP_CHWIDTH_2040: + if (phymode == WLAN_PHYMODE_11NG_HT40PLUS) + phymode = WLAN_PHYMODE_11AC_VHT40PLUS_2G; + else if (phymode == WLAN_PHYMODE_11NG_HT40MINUS) + phymode = WLAN_PHYMODE_11AC_VHT40MINUS_2G; + else + phymode = WLAN_PHYMODE_11AC_VHT20_2G; + + break; + default: + scm_info("bad vht_op_chwidth: %d", + vhtop->vht_op_chwidth); + phymode = WLAN_PHYMODE_11AC_VHT20_2G; + break; + } + } + return phymode; } @@ -465,6 +481,21 @@ util_scan_parse_vendor_ie(struct scan_cache_entry *scan_params, scan_params->ie_list.bwnss_map = (((uint8_t *)ie) + 8); } else if (is_mbo_oce_oui((uint8_t *)ie)) { scan_params->ie_list.mbo_oce = (uint8_t *)ie; + } else if (is_adaptive_11r_oui((uint8_t *)ie)) { + if (ie->ie_len < OUI_LENGTH || + ie->ie_len > MAX_ADAPTIVE_11R_IE_LEN) + return QDF_STATUS_E_INVAL; + + scan_params->ie_list.adaptive_11r = (uint8_t *)ie + + sizeof(struct ie_header); + } else if (is_sae_single_pmk_oui((uint8_t *)ie)) { + if (ie->ie_len < OUI_LENGTH || + ie->ie_len > MAX_SAE_SINGLE_PMK_IE_LEN) { + scm_debug("Invalid sae single pmk OUI"); + return QDF_STATUS_E_INVAL; + } + scan_params->ie_list.single_pmk = (uint8_t *)ie + + sizeof(struct ie_header); } return QDF_STATUS_SUCCESS; } @@ -827,10 +858,54 @@ static int util_scan_scm_calc_nss_supported_by_ap( return 1; } +#ifdef WLAN_ADAPTIVE_11R +/** + * scm_fill_adaptive_11r_cap() - Check if the AP supports adaptive 11r + * @scan_entry: Pointer to the scan entry + * + * Return: true if adaptive 11r is advertised else false + */ +static void scm_fill_adaptive_11r_cap(struct scan_cache_entry *scan_entry) +{ + uint8_t *ie; + uint8_t data; + bool adaptive_11r; + + ie = util_scan_entry_adaptive_11r(scan_entry); + if (!ie) + return; + + data = *(ie + OUI_LENGTH); + adaptive_11r = (data & 0x1) ? true : false; + + scan_entry->adaptive_11r_ap = adaptive_11r; +} +#else +static void scm_fill_adaptive_11r_cap(struct scan_cache_entry *scan_entry) +{ + scan_entry->adaptive_11r_ap = false; +} +#endif + +static void util_scan_set_security(struct scan_cache_entry *scan_params) +{ + if (util_scan_entry_wpa(scan_params)) + scan_params->security_type |= SCAN_SECURITY_TYPE_WPA; + + if (util_scan_entry_rsn(scan_params)) + scan_params->security_type |= SCAN_SECURITY_TYPE_RSN; + if (util_scan_entry_wapi(scan_params)) + scan_params->security_type |= SCAN_SECURITY_TYPE_WAPI; + + if (!scan_params->security_type && + scan_params->cap_info.wlan_caps.privacy) + scan_params->security_type |= SCAN_SECURITY_TYPE_WEP; +} + qdf_list_t * util_scan_unpack_beacon_frame(struct wlan_objmgr_pdev *pdev, uint8_t *frame, - qdf_size_t frame_len, uint32_t frm_subtype, - struct mgmt_rx_event_params *rx_param) + qdf_size_t frame_len, uint32_t frm_subtype, + struct mgmt_rx_event_params *rx_param) { struct wlan_frame_hdr *hdr; struct wlan_bcn_frame *bcn; @@ -958,6 +1033,9 @@ util_scan_unpack_beacon_frame(struct wlan_objmgr_pdev *pdev, uint8_t *frame, scan_entry->phy_mode = util_scan_get_phymode_2g(scan_entry); scan_entry->nss = util_scan_scm_calc_nss_supported_by_ap(scan_entry); + scm_fill_adaptive_11r_cap(scan_entry); + util_scan_set_security(scan_entry); + util_scan_scm_update_bss_with_esp_data(scan_entry); qbss_load = (struct qbss_load_ie *) util_scan_entry_qbssload(scan_entry); diff --git a/drivers/staging/qca-wifi-host-cmn/umac/tdls/core/src/wlan_tdls_cmds_process.c b/drivers/staging/qca-wifi-host-cmn/umac/tdls/core/src/wlan_tdls_cmds_process.c index 3e3b772e4482..a39954f01c3b 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/tdls/core/src/wlan_tdls_cmds_process.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/tdls/core/src/wlan_tdls_cmds_process.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -530,7 +530,6 @@ tdls_add_peer_serialize_callback(struct wlan_serialization_command *cmd, } req = cmd->umac_cmd; - tdls_debug("reason: %d, req %pK", reason, req); switch (reason) { case WLAN_SER_CB_ACTIVATE_CMD: @@ -760,7 +759,7 @@ int tdls_validate_mgmt_request(struct tdls_action_frame_request *tdls_mgmt_req) } } - tdls_notice("tdls_mgmt" QDF_MAC_ADDR_STR " action %d, dialog_token %d status %d, len = %zu", + tdls_debug("tdls_mgmt" QDF_MAC_ADDR_STR " action %d, dialog_token %d status %d, len = %zu", QDF_MAC_ADDR_ARRAY(tdls_validate->peer_mac), tdls_validate->action_code, tdls_validate->dialog_token, tdls_validate->status_code, tdls_validate->len); @@ -976,7 +975,6 @@ tdls_update_peer_serialize_callback(struct wlan_serialization_command *cmd, } req = cmd->umac_cmd; - tdls_debug("reason: %d, req %pK", reason, req); switch (reason) { case WLAN_SER_CB_ACTIVATE_CMD: @@ -1099,7 +1097,6 @@ tdls_del_peer_serialize_callback(struct wlan_serialization_command *cmd, } req = cmd->umac_cmd; - tdls_debug("reason: %d, req %pK", reason, req); switch (reason) { case WLAN_SER_CB_ACTIVATE_CMD: @@ -1416,10 +1413,10 @@ static QDF_STATUS tdls_add_peer_rsp(struct tdls_add_sta_rsp *rsp) conn_rec[sta_idx].index = sta_idx; qdf_copy_macaddr(&conn_rec[sta_idx].peer_mac, &rsp->peermac); - tdls_warn("TDLS: STA IDX at %d is %d of mac " - QDF_MAC_ADDR_STR, sta_idx, - rsp->sta_id, QDF_MAC_ADDR_ARRAY - (rsp->peermac.bytes)); + tdls_debug("TDLS: STA IDX at %d is %d of mac " + QDF_MAC_ADDR_STR, sta_idx, + rsp->sta_id, QDF_MAC_ADDR_ARRAY + (rsp->peermac.bytes)); break; } } @@ -1501,7 +1498,7 @@ QDF_STATUS tdls_process_del_peer_rsp(struct tdls_del_sta_rsp *rsp) continue; macaddr = rsp->peermac.bytes; - tdls_warn("TDLS: del STA IDX = %x", rsp->sta_id); + tdls_debug("TDLS: del STA IDX = %x", rsp->sta_id); curr_peer = tdls_find_peer(vdev_obj, macaddr); if (curr_peer) { tdls_debug(QDF_MAC_ADDR_STR " status is %d", @@ -1877,9 +1874,9 @@ QDF_STATUS tdls_process_remove_force_peer(struct tdls_oper_request *req) status = QDF_STATUS_E_NULL_VALUE; goto error; } - - tdls_set_peer_link_status(peer, TDLS_LINK_TEARING, - TDLS_LINK_UNSPECIFIED); + if (peer->link_status == TDLS_LINK_CONNECTED) + tdls_set_peer_link_status(peer, TDLS_LINK_TEARING, + TDLS_LINK_UNSPECIFIED); if (soc_obj->tdls_dp_vdev_update) soc_obj->tdls_dp_vdev_update(&soc_obj->soc, diff --git a/drivers/staging/qca-wifi-host-cmn/umac/tdls/core/src/wlan_tdls_ct.c b/drivers/staging/qca-wifi-host-cmn/umac/tdls/core/src/wlan_tdls_ct.c index dc37061dff04..e84edfbebc90 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/tdls/core/src/wlan_tdls_ct.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/tdls/core/src/wlan_tdls_ct.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -770,13 +770,13 @@ static void tdls_ct_process_cap_supported(struct tdls_peer *curr_peer, struct tdls_vdev_priv_obj *tdls_vdev, struct tdls_soc_priv_obj *tdls_soc_obj) { - tdls_debug("tx %d rx %d thr.pkt %d/idle %d rssi %d thr.trig %d/tear %d", - curr_peer->tx_pkt, curr_peer->rx_pkt, - tdls_vdev->threshold_config.tx_packet_n, - tdls_vdev->threshold_config.idle_packet_n, - curr_peer->rssi, - tdls_vdev->threshold_config.rssi_trigger_threshold, - tdls_vdev->threshold_config.rssi_teardown_threshold); + + if (curr_peer->rx_pkt || curr_peer->tx_pkt) + tdls_debug(QDF_MAC_ADDR_STR "link_status %d tdls_support %d tx %d rx %d rssi %d", + QDF_MAC_ADDR_ARRAY(curr_peer->peer_mac.bytes), + curr_peer->link_status, curr_peer->tdls_support, + curr_peer->tx_pkt, curr_peer->rx_pkt, + curr_peer->rssi); switch (curr_peer->link_status) { case TDLS_LINK_IDLE: @@ -816,9 +816,11 @@ static void tdls_ct_process_cap_unknown(struct tdls_peer *curr_peer, (!curr_peer->is_forced_peer)) return; - tdls_debug("threshold tx pkt = %d peer tx_pkt = %d & rx_pkt = %d ", - tdls_vdev->threshold_config.tx_packet_n, curr_peer->tx_pkt, - curr_peer->rx_pkt); + if (curr_peer->rx_pkt || curr_peer->tx_pkt) + tdls_debug(QDF_MAC_ADDR_STR "link_status %d tdls_support %d tx %d rx %d", + QDF_MAC_ADDR_ARRAY(curr_peer->peer_mac.bytes), + curr_peer->link_status, curr_peer->tdls_support, + curr_peer->tx_pkt, curr_peer->rx_pkt); if (!TDLS_IS_LINK_CONNECTED(curr_peer) && ((curr_peer->tx_pkt + curr_peer->rx_pkt) >= @@ -859,10 +861,6 @@ static void tdls_ct_process_peers(struct tdls_peer *curr_peer, struct tdls_vdev_priv_obj *tdls_vdev_obj, struct tdls_soc_priv_obj *tdls_soc_obj) { - tdls_debug(QDF_MAC_ADDR_STR " link_status %d tdls_support %d", - QDF_MAC_ADDR_ARRAY(curr_peer->peer_mac.bytes), - curr_peer->link_status, curr_peer->tdls_support); - switch (curr_peer->tdls_support) { case TDLS_CAP_SUPPORTED: tdls_ct_process_cap_supported(curr_peer, tdls_vdev_obj, @@ -1230,7 +1228,7 @@ void tdls_disable_offchan_and_teardown_links( } if (TDLS_SUPPORT_SUSPENDED >= tdls_soc->tdls_current_mode) { - tdls_notice("TDLS mode %d is disabled OR not suspended now", + tdls_debug("TDLS mode %d is disabled OR not suspended now", tdls_soc->tdls_current_mode); return; } @@ -1240,7 +1238,7 @@ void tdls_disable_offchan_and_teardown_links( tdls_in_progress = true; if (!(connected_tdls_peers || tdls_in_progress)) { - tdls_notice("No TDLS connected/progress peers to delete"); + tdls_debug("No TDLS connected/progress peers to delete"); vdev_id = vdev->vdev_objmgr.vdev_id; if (tdls_soc->set_state_info.set_state_cnt > 0) { tdls_debug("Disable the tdls in FW as second interface is coming up"); diff --git a/drivers/staging/qca-wifi-host-cmn/umac/tdls/core/src/wlan_tdls_main.c b/drivers/staging/qca-wifi-host-cmn/umac/tdls/core/src/wlan_tdls_main.c index 6878914d9b57..262382eaf3bc 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/tdls/core/src/wlan_tdls_main.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/tdls/core/src/wlan_tdls_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -595,36 +595,6 @@ QDF_STATUS tdls_get_vdev_objects(struct wlan_objmgr_vdev *vdev, return QDF_STATUS_SUCCESS; } -/** - * tdls_state_param_setting_dump() - print tdls state & parameters to send to fw - * @info: tdls setting to be sent to fw - * - * Return: void - */ -static void tdls_state_param_setting_dump(struct tdls_info *info) -{ - if (!info) - return; - - tdls_debug("Setting tdls state and param in fw: vdev_id: %d, tdls_state: %d, notification_interval_ms: %d, tx_discovery_threshold: %d, tx_teardown_threshold: %d, rssi_teardown_threshold: %d, rssi_delta: %d, tdls_options: 0x%x, peer_traffic_ind_window: %d, peer_traffic_response_timeout: %d, puapsd_mask: 0x%x, puapsd_inactivity_time: %d, puapsd_rx_frame_threshold: %d, teardown_notification_ms: %d, tdls_peer_kickout_threshold: %d", - info->vdev_id, - info->tdls_state, - info->notification_interval_ms, - info->tx_discovery_threshold, - info->tx_teardown_threshold, - info->rssi_teardown_threshold, - info->rssi_delta, - info->tdls_options, - info->peer_traffic_ind_window, - info->peer_traffic_response_timeout, - info->puapsd_mask, - info->puapsd_inactivity_time, - info->puapsd_rx_frame_threshold, - info->teardown_notification_ms, - info->tdls_peer_kickout_threshold); - -} - QDF_STATUS tdls_set_offchan_mode(struct wlan_objmgr_psoc *psoc, struct tdls_channel_switch_params *param) { @@ -791,7 +761,7 @@ tdls_process_decrement_active_session(struct wlan_objmgr_psoc *psoc) if(!policy_mgr_is_hw_dbs_2x2_capable(psoc) && policy_mgr_is_current_hwmode_dbs(psoc)) { - tdls_err("Current HW mode is 1*1 DBS. Wait for Opportunistic timer to expire to enable TDLS in FW"); + tdls_debug("Current HW mode is 1*1 DBS. Wait for Opportunistic timer to expire to enable TDLS in FW"); return QDF_STATUS_SUCCESS; } tdls_obj_vdev = tdls_get_vdev(psoc, WLAN_TDLS_NB_ID); @@ -914,7 +884,6 @@ void tdls_send_update_to_fw(struct tdls_vdev_priv_obj *tdls_vdev_obj, QDF_STATUS status; uint8_t set_state_cnt; - tdls_debug("Enter"); tdls_feature_flags = tdls_soc_obj->tdls_configs.tdls_feature_flags; if (!TDLS_IS_ENABLED(tdls_feature_flags)) { tdls_debug("TDLS mode is not enabled"); @@ -934,8 +903,6 @@ void tdls_send_update_to_fw(struct tdls_vdev_priv_obj *tdls_vdev_obj, tdls_soc_obj->tdls_current_mode = TDLS_SUPPORT_DISABLED; } else { - tdls_debug("TDLS feature flags from ini %d ", - tdls_feature_flags); if (!TDLS_IS_IMPLICIT_TRIG_ENABLED(tdls_feature_flags)) tdls_soc_obj->tdls_current_mode = TDLS_SUPPORT_EXP_TRIG_ONLY; @@ -1005,8 +972,8 @@ void tdls_send_update_to_fw(struct tdls_vdev_priv_obj *tdls_vdev_obj, tdls_soc_obj->tdls_configs.tdls_idle_timeout; tdls_info_to_fw->tdls_peer_kickout_threshold = tdls_soc_obj->tdls_configs.tdls_peer_kickout_threshold; - - tdls_state_param_setting_dump(tdls_info_to_fw); + tdls_info_to_fw->tdls_discovery_wake_timeout = + tdls_soc_obj->tdls_configs.tdls_discovery_wake_timeout; status = tdls_update_fw_tdls_state(tdls_soc_obj, tdls_info_to_fw); if (QDF_STATUS_SUCCESS != status) @@ -1038,8 +1005,6 @@ tdls_process_sta_connect(struct tdls_sta_notify_params *notify) return QDF_STATUS_E_INVAL; - tdls_debug("Check and update TDLS state"); - if (policy_mgr_get_connection_count(tdls_soc_obj->soc) > 1) { tdls_debug("Concurrent sessions exist, TDLS can't be enabled"); return QDF_STATUS_SUCCESS; @@ -1557,21 +1522,17 @@ void tdls_scan_done_callback(struct tdls_soc_priv_obj *tdls_soc) return; if (TDLS_SUPPORT_DISABLED == tdls_soc->tdls_current_mode) { - tdls_debug("TDLS mode is disabled OR not enabled"); + tdls_debug_rl("TDLS mode is disabled OR not enabled"); return; } /* if tdls was enabled before scan, re-enable tdls mode */ if (TDLS_SUPPORT_IMP_MODE == tdls_soc->tdls_last_mode || TDLS_SUPPORT_EXT_CONTROL == tdls_soc->tdls_last_mode || - TDLS_SUPPORT_EXP_TRIG_ONLY == tdls_soc->tdls_last_mode) { - tdls_debug("revert tdls mode %d", - tdls_soc->tdls_last_mode); - + TDLS_SUPPORT_EXP_TRIG_ONLY == tdls_soc->tdls_last_mode) tdls_set_current_mode(tdls_soc, tdls_soc->tdls_last_mode, false, TDLS_SET_MODE_SOURCE_SCAN); - } } /** diff --git a/drivers/staging/qca-wifi-host-cmn/umac/tdls/core/src/wlan_tdls_mgmt.c b/drivers/staging/qca-wifi-host-cmn/umac/tdls/core/src/wlan_tdls_mgmt.c index 7f96a59d5276..b04a00c39f36 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/tdls/core/src/wlan_tdls_mgmt.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/tdls/core/src/wlan_tdls_mgmt.c @@ -348,9 +348,6 @@ tdls_send_mgmt_serialize_callback(struct wlan_serialization_command *cmd, } req = cmd->umac_cmd; - tdls_debug("reason: %d, vdev_id: %d", - reason, req->vdev_id); - switch (reason) { case WLAN_SER_CB_ACTIVATE_CMD: /* command moved to active list */ diff --git a/drivers/staging/qca-wifi-host-cmn/umac/tdls/dispatcher/inc/wlan_tdls_public_structs.h b/drivers/staging/qca-wifi-host-cmn/umac/tdls/dispatcher/inc/wlan_tdls_public_structs.h index 2dc80875c1f5..76d8498392f8 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/tdls/dispatcher/inc/wlan_tdls_public_structs.h +++ b/drivers/staging/qca-wifi-host-cmn/umac/tdls/dispatcher/inc/wlan_tdls_public_structs.h @@ -437,6 +437,7 @@ enum tdls_feature_bit { * @tdls_pre_off_chan_num: tdls off channel number * @tdls_pre_off_chan_bw: tdls off channel bandwidth * @tdls_peer_kickout_threshold: sta kickout threshold for tdls peer + * @tdls_discovery_wake_timeout: Discovery wake timeout * @delayed_trig_framint: delayed trigger frame interval * @tdls_vdev_nss_2g: tdls NSS setting for 2G band * @tdls_vdev_nss_5g: tdls NSS setting for 5G band @@ -459,6 +460,7 @@ struct tdls_user_config { uint32_t tdls_pre_off_chan_num; uint32_t tdls_pre_off_chan_bw; uint32_t tdls_peer_kickout_threshold; + uint32_t tdls_discovery_wake_timeout; uint32_t delayed_trig_framint; uint8_t tdls_vdev_nss_2g; uint8_t tdls_vdev_nss_5g; @@ -797,6 +799,7 @@ struct tdls_oper_config_force_peer_request { * @teardown_notification_ms: tdls teardown notification interval * @tdls_peer_kickout_threshold: tdls packets threshold * for peer kickout operation + * @tdls_discovery_wake_timeout: Discovery wake timeout */ struct tdls_info { uint32_t vdev_id; @@ -814,6 +817,7 @@ struct tdls_info { uint32_t puapsd_rx_frame_threshold; uint32_t teardown_notification_ms; uint32_t tdls_peer_kickout_threshold; + uint32_t tdls_discovery_wake_timeout; }; /** diff --git a/drivers/staging/qca-wifi-host-cmn/umac/tdls/dispatcher/src/wlan_tdls_ucfg_api.c b/drivers/staging/qca-wifi-host-cmn/umac/tdls/dispatcher/src/wlan_tdls_ucfg_api.c index fd4689003b18..a7207a6fcc46 100644 --- a/drivers/staging/qca-wifi-host-cmn/umac/tdls/dispatcher/src/wlan_tdls_ucfg_api.c +++ b/drivers/staging/qca-wifi-host-cmn/umac/tdls/dispatcher/src/wlan_tdls_ucfg_api.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -249,7 +249,7 @@ QDF_STATUS ucfg_tdls_psoc_enable(struct wlan_objmgr_psoc *psoc) { QDF_STATUS status; - tdls_notice("psoc tdls enable: 0x%pK", psoc); + tdls_debug("psoc tdls enable: 0x%pK", psoc); if (!psoc) { tdls_err("NULL psoc"); return QDF_STATUS_E_FAILURE; @@ -282,7 +282,7 @@ QDF_STATUS ucfg_tdls_psoc_disable(struct wlan_objmgr_psoc *psoc) QDF_STATUS status; struct tdls_soc_priv_obj *soc_obj = NULL; - tdls_notice("psoc tdls disable: 0x%pK", psoc); + tdls_debug("psoc tdls disable: 0x%pK", psoc); if (!psoc) { tdls_err("NULL psoc"); return QDF_STATUS_E_FAILURE; @@ -314,7 +314,7 @@ QDF_STATUS ucfg_tdls_psoc_close(struct wlan_objmgr_psoc *psoc) QDF_STATUS status = QDF_STATUS_SUCCESS; struct tdls_soc_priv_obj *tdls_soc; - tdls_notice("tdls psoc close"); + tdls_debug("tdls psoc close"); tdls_soc = wlan_objmgr_psoc_get_comp_private_obj(psoc, WLAN_UMAC_COMP_TDLS); if (!tdls_soc) { diff --git a/drivers/staging/qca-wifi-host-cmn/utils/fwlog/dbglog_host.c b/drivers/staging/qca-wifi-host-cmn/utils/fwlog/dbglog_host.c index 6e226fe63a9b..ea3c6fc4f75b 100644 --- a/drivers/staging/qca-wifi-host-cmn/utils/fwlog/dbglog_host.c +++ b/drivers/staging/qca-wifi-host-cmn/utils/fwlog/dbglog_host.c @@ -1740,7 +1740,7 @@ send_diag_netlink_data(const uint8_t *buffer, uint32_t len, uint32_t cmd) slot_len = sizeof(*slot) + ATH6KL_FWLOG_PAYLOAD_SIZE + sizeof(radio); - skb_out = nlmsg_new(slot_len, GFP_KERNEL); + skb_out = nlmsg_new(slot_len, GFP_ATOMIC); if (!skb_out) { AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Failed to allocate new skb\n")); diff --git a/drivers/staging/qca-wifi-host-cmn/utils/host_diag_log/inc/host_diag_core_log.h b/drivers/staging/qca-wifi-host-cmn/utils/host_diag_log/inc/host_diag_core_log.h index 4b72f237e92c..70690efa870f 100644 --- a/drivers/staging/qca-wifi-host-cmn/utils/host_diag_log/inc/host_diag_core_log.h +++ b/drivers/staging/qca-wifi-host-cmn/utils/host_diag_log/inc/host_diag_core_log.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2017, 2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2014-2017, 2019-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -284,6 +284,34 @@ struct host_log_cold_boot_cal_data_type { uint8_t cb_cal_data[HOST_LOG_MAX_COLD_BOOT_CAL_DATA_SIZE]; }; +/** + * struct host_event_proto_pkt_info - DP protocol pkt info + * @hdr: Log header + * @version: version + * @type: data pkt type + * @subtype: data pkt subtype + * @dir: tx or rx + * @sa: source MAC address + * @da: destination MAC address + * @msdu_id: MSDU id + * @status: status + * + * Structure containing the protocol data pkt info + * + * LOG_WLAN_DP_PROTO_PKT_INFO_C 0x1A1E + */ +struct host_event_proto_pkt_info { + log_hdr_type hdr; + uint32_t version; + uint8_t type; + uint8_t subtype; + uint8_t dir; + uint8_t sa[QDF_MAC_ADDR_SIZE]; + uint8_t da[QDF_MAC_ADDR_SIZE]; + uint16_t msdu_id; + uint8_t status; +}; + /*------------------------------------------------------------------------- Function declarations and documenation ------------------------------------------------------------------------*/ diff --git a/drivers/staging/qca-wifi-host-cmn/utils/host_diag_log/inc/log_codes.h b/drivers/staging/qca-wifi-host-cmn/utils/host_diag_log/inc/log_codes.h index 9f3fe6c0cf67..10f9f1008523 100644 --- a/drivers/staging/qca-wifi-host-cmn/utils/host_diag_log/inc/log_codes.h +++ b/drivers/staging/qca-wifi-host-cmn/utils/host_diag_log/inc/log_codes.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2014-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -2003,6 +2003,8 @@ #define LOG_WLAN_COLD_BOOT_CAL_DATA_C ((0xA18) + LOG_1X_BASE_C) +#define LOG_WLAN_DP_PROTO_PKT_INFO_C ((0xA1E) + LOG_1X_BASE_C) + /* This is only here for old (pre equipment ID update) logging code */ #define LOG_LAST_C (LOG_1X_LAST_C & 0xFFF) diff --git a/drivers/staging/qca-wifi-host-cmn/utils/logging/src/wlan_logging_sock_svc.c b/drivers/staging/qca-wifi-host-cmn/utils/logging/src/wlan_logging_sock_svc.c index 0df84a413d52..7220ebf08019 100644 --- a/drivers/staging/qca-wifi-host-cmn/utils/logging/src/wlan_logging_sock_svc.c +++ b/drivers/staging/qca-wifi-host-cmn/utils/logging/src/wlan_logging_sock_svc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2014-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -231,8 +231,9 @@ static int wlan_add_user_log_time_stamp(char *tbuf, size_t tbuf_sz, uint64_t ts) qdf_get_time_of_the_day_in_hr_min_sec_usec(time_buf, sizeof(time_buf)); - return scnprintf(tbuf, tbuf_sz, "[%.16s][0x%llx]%s", - current_process_name(), ts, time_buf); + return scnprintf(tbuf, tbuf_sz, "[%.6s][%llu]%s", + current_process_name(), (unsigned long long)ts, + time_buf); } #else static int wlan_add_user_log_time_stamp(char *tbuf, size_t tbuf_sz, uint64_t ts) diff --git a/drivers/staging/qca-wifi-host-cmn/utils/pktlog/include/pktlog_ac.h b/drivers/staging/qca-wifi-host-cmn/utils/pktlog/include/pktlog_ac.h index afa5f3d64d53..5fcc15d41d05 100644 --- a/drivers/staging/qca-wifi-host-cmn/utils/pktlog/include/pktlog_ac.h +++ b/drivers/staging/qca-wifi-host-cmn/utils/pktlog/include/pktlog_ac.h @@ -131,6 +131,9 @@ void pktlog_callback(void *pdev, enum WDI_EVENT event, void *log_data, void pktlog_init(struct hif_opaque_softc *scn); int pktlog_enable(struct hif_opaque_softc *scn, int32_t log_state, bool, uint8_t, uint32_t); +int __pktlog_enable(struct hif_opaque_softc *scn, int32_t log_state, + bool ini_triggered, uint8_t user_triggered, + uint32_t is_iwpriv_command); int pktlog_setsize(struct hif_opaque_softc *scn, int32_t log_state); int pktlog_clearbuff(struct hif_opaque_softc *scn, bool clear_buff); int pktlog_disable(struct hif_opaque_softc *scn); @@ -170,6 +173,14 @@ static inline int pktlog_enable(struct hif_opaque_softc *scn, int32_t log_state, return 0; } +static inline +int __pktlog_enable(struct hif_opaque_softc *scn, int32_t log_state, + bool ini_triggered, uint8_t user_triggered, + uint32_t is_iwpriv_command) +{ + return 0; +} + static inline int pktlog_setsize(struct hif_opaque_softc *scn, int32_t log_state) { diff --git a/drivers/staging/qca-wifi-host-cmn/utils/pktlog/linux_ac.c b/drivers/staging/qca-wifi-host-cmn/utils/pktlog/linux_ac.c index db50aa9b26f7..0bbb9df0ecad 100644 --- a/drivers/staging/qca-wifi-host-cmn/utils/pktlog/linux_ac.c +++ b/drivers/staging/qca-wifi-host-cmn/utils/pktlog/linux_ac.c @@ -511,6 +511,12 @@ static void pktlog_detach(struct hif_opaque_softc *scn) } pl_info = pl_dev->pl_info; + if (!pl_info) { + qdf_print("%s: Invalid pktlog handle", __func__); + ASSERT(0); + return; + } + mutex_lock(&pl_info->pktlog_mutex); remove_proc_entry(WLANDEV_BASENAME, g_pktlog_pde); pktlog_sysctl_unregister(pl_dev); @@ -521,6 +527,7 @@ static void pktlog_detach(struct hif_opaque_softc *scn) pl_dev->tgt_pktlog_alloced = false; } qdf_spin_unlock_bh(&pl_info->log_lock); + mutex_unlock(&pl_info->pktlog_mutex); pktlog_cleanup(pl_info); if (pl_dev) { @@ -534,33 +541,19 @@ static int __pktlog_open(struct inode *i, struct file *f) struct hif_opaque_softc *scn; struct pktlog_dev_t *pl_dev; struct ath_pktlog_info *pl_info; + struct ath_pktlog_info_lnx *pl_info_lnx; int ret = 0; PKTLOG_MOD_INC_USE_COUNT; - pl_info = (struct ath_pktlog_info *) - PDE_DATA(f->f_path.dentry->d_inode); - - if (!pl_info) { - pr_err("%s: pl_info NULL", __func__); - return -EINVAL; - } - - if (pl_info->curr_pkt_state != PKTLOG_OPR_NOT_IN_PROGRESS) { - pr_info("%s: plinfo state (%d) != PKTLOG_OPR_NOT_IN_PROGRESS", - __func__, pl_info->curr_pkt_state); - return -EBUSY; - } if (qdf_is_module_state_transitioning()) { pr_info("%s: module transition in progress", __func__); return -EAGAIN; } - pl_info->curr_pkt_state = PKTLOG_OPR_IN_PROGRESS_READ_START; scn = cds_get_context(QDF_MODULE_ID_HIF); if (!scn) { - pl_info->curr_pkt_state = PKTLOG_OPR_NOT_IN_PROGRESS; - qdf_print("%s: Invalid scn context\n", __func__); + qdf_print("%s: Invalid scn context", __func__); ASSERT(0); return -EINVAL; } @@ -568,12 +561,38 @@ static int __pktlog_open(struct inode *i, struct file *f) pl_dev = get_pktlog_handle(); if (!pl_dev) { - pl_info->curr_pkt_state = PKTLOG_OPR_NOT_IN_PROGRESS; - qdf_print("%s: Invalid pktlog handle\n", __func__); + qdf_print("%s: Invalid pktlog handle", __func__); ASSERT(0); return -ENODEV; } + pl_info = pl_dev->pl_info; + + if (!pl_info) { + qdf_nofl_err("%s: pl_info NULL", __func__); + return -EINVAL; + } + + mutex_lock(&pl_info->pktlog_mutex); + pl_info_lnx = (pl_dev) ? PL_INFO_LNX(pl_dev->pl_info) : + PL_INFO_LNX(g_pktlog_info); + + if (!pl_info_lnx->sysctl_header) { + mutex_unlock(&pl_info->pktlog_mutex); + qdf_print("%s: pktlog sysctl is unergistered.", __func__); + ASSERT(0); + return -EINVAL; + } + + if (pl_info->curr_pkt_state != PKTLOG_OPR_NOT_IN_PROGRESS) { + mutex_unlock(&pl_info->pktlog_mutex); + qdf_print("%s: plinfo state (%d) != PKTLOG_OPR_NOT_IN_PROGRESS", + __func__, pl_info->curr_pkt_state); + return -EBUSY; + } + + pl_info->curr_pkt_state = PKTLOG_OPR_IN_PROGRESS_READ_START; + pl_info->init_saved_state = pl_info->log_state; if (!pl_info->log_state) { /* Pktlog is already disabled. @@ -581,6 +600,7 @@ static int __pktlog_open(struct inode *i, struct file *f) */ pl_info->curr_pkt_state = PKTLOG_OPR_IN_PROGRESS_READ_START_PKTLOG_DISABLED; + mutex_unlock(&pl_info->pktlog_mutex); return ret; } /* Disbable the pktlog internally. */ @@ -588,6 +608,7 @@ static int __pktlog_open(struct inode *i, struct file *f) pl_info->log_state = 0; pl_info->curr_pkt_state = PKTLOG_OPR_IN_PROGRESS_READ_START_PKTLOG_DISABLED; + mutex_unlock(&pl_info->pktlog_mutex); return ret; } @@ -607,16 +628,11 @@ static int __pktlog_release(struct inode *i, struct file *f) struct hif_opaque_softc *scn; struct pktlog_dev_t *pl_dev; struct ath_pktlog_info *pl_info; + struct ath_pktlog_info_lnx *pl_info_lnx; int ret = 0; PKTLOG_MOD_DEC_USE_COUNT; - pl_info = (struct ath_pktlog_info *) - PDE_DATA(f->f_path.dentry->d_inode); - - if (!pl_info) - return -EINVAL; - if (qdf_is_module_state_transitioning()) { pr_info("%s: module transition in progress", __func__); return -EAGAIN; @@ -624,8 +640,7 @@ static int __pktlog_release(struct inode *i, struct file *f) scn = cds_get_context(QDF_MODULE_ID_HIF); if (!scn) { - pl_info->curr_pkt_state = PKTLOG_OPR_NOT_IN_PROGRESS; - qdf_print("%s: Invalid scn context\n", __func__); + qdf_print("%s: Invalid scn context", __func__); ASSERT(0); return -EINVAL; } @@ -633,12 +648,30 @@ static int __pktlog_release(struct inode *i, struct file *f) pl_dev = get_pktlog_handle(); if (!pl_dev) { - pl_info->curr_pkt_state = PKTLOG_OPR_NOT_IN_PROGRESS; - qdf_print("%s: Invalid pktlog handle\n", __func__); + qdf_print("%s: Invalid pktlog handle", __func__); ASSERT(0); return -ENODEV; } + pl_info = pl_dev->pl_info; + + if (!pl_info) { + qdf_print("%s: Invalid pktlog info", __func__); + ASSERT(0); + return -EINVAL; + } + + mutex_lock(&pl_info->pktlog_mutex); + pl_info_lnx = (pl_dev) ? PL_INFO_LNX(pl_dev->pl_info) : + PL_INFO_LNX(g_pktlog_info); + + if (!pl_info_lnx->sysctl_header) { + pl_info->curr_pkt_state = PKTLOG_OPR_NOT_IN_PROGRESS; + mutex_unlock(&pl_info->pktlog_mutex); + qdf_print("%s: pktlog sysctl is unergistered.", __func__); + ASSERT(0); + return -EINVAL; + } pl_info->curr_pkt_state = PKTLOG_OPR_IN_PROGRESS_READ_COMPLETE; /*clear pktlog buffer.*/ pktlog_clearbuff(scn, true); @@ -646,15 +679,16 @@ static int __pktlog_release(struct inode *i, struct file *f) pl_info->init_saved_state = 0; /*Enable pktlog again*/ - ret = pl_dev->pl_funcs->pktlog_enable( + ret = __pktlog_enable( (struct hif_opaque_softc *)scn, pl_info->log_state, cds_is_packet_log_enabled(), 0, 1); + pl_info->curr_pkt_state = PKTLOG_OPR_NOT_IN_PROGRESS; + mutex_unlock(&pl_info->pktlog_mutex); if (ret != 0) - pr_warn("%s: pktlog cannot be enabled. ret value %d\n", - __func__, ret); + qdf_print("%s: pktlog cannot be enabled. ret value %d", + __func__, ret); - pl_info->curr_pkt_state = PKTLOG_OPR_NOT_IN_PROGRESS; return ret; } diff --git a/drivers/staging/qca-wifi-host-cmn/utils/pktlog/pktlog_ac.c b/drivers/staging/qca-wifi-host-cmn/utils/pktlog/pktlog_ac.c index 9a31ad35a3de..ac62504ba48e 100644 --- a/drivers/staging/qca-wifi-host-cmn/utils/pktlog/pktlog_ac.c +++ b/drivers/staging/qca-wifi-host-cmn/utils/pktlog/pktlog_ac.c @@ -473,10 +473,13 @@ int pktlog_disable(struct hif_opaque_softc *scn) return 0; } +#define ONE_MEGABYTE (1024 * 1024) + void pktlog_init(struct hif_opaque_softc *scn) { struct pktlog_dev_t *pl_dev = get_pktlog_handle(); struct ath_pktlog_info *pl_info; + uint32_t buff_size; if (pl_dev == NULL || pl_dev->pl_info == NULL) { qdf_print("pl_dev or pl_info is invalid\n"); @@ -489,7 +492,9 @@ void pktlog_init(struct hif_opaque_softc *scn) PKTLOG_LOCK_INIT(pl_info); mutex_init(&pl_info->pktlog_mutex); - pl_info->buf_size = PKTLOG_DEFAULT_BUFSIZE; + buff_size = cds_get_packet_log_buffer_size() * ONE_MEGABYTE; + + pl_info->buf_size = (buff_size ? buff_size : ONE_MEGABYTE); pl_info->buf = NULL; pl_info->log_state = 0; pl_info->init_saved_state = 0; @@ -518,9 +523,9 @@ void pktlog_init(struct hif_opaque_softc *scn) } } -static int __pktlog_enable(struct hif_opaque_softc *scn, int32_t log_state, - bool ini_triggered, uint8_t user_triggered, - uint32_t is_iwpriv_command) +int __pktlog_enable(struct hif_opaque_softc *scn, int32_t log_state, + bool ini_triggered, uint8_t user_triggered, + uint32_t is_iwpriv_command) { struct pktlog_dev_t *pl_dev; struct ath_pktlog_info *pl_info; @@ -678,14 +683,13 @@ int pktlog_enable(struct hif_opaque_softc *scn, int32_t log_state, return err; } -#define ONE_MEGABYTE (1024 * 1024) -#define MAX_ALLOWED_PKTLOG_SIZE (16 * ONE_MEGABYTE) - static int __pktlog_setsize(struct hif_opaque_softc *scn, int32_t size) { struct pktlog_dev_t *pl_dev; struct ath_pktlog_info *pl_info; struct cdp_pdev *pdev; + uint32_t buff_size; + uint32_t max_allowed_buff_size; pl_dev = get_pktlog_handle(); @@ -715,11 +719,14 @@ static int __pktlog_setsize(struct hif_opaque_softc *scn, int32_t size) pl_info->curr_pkt_state = PKTLOG_OPR_IN_PROGRESS; - if (size < ONE_MEGABYTE || size > MAX_ALLOWED_PKTLOG_SIZE) { + buff_size = cds_get_packet_log_buffer_size() * ONE_MEGABYTE; + max_allowed_buff_size = (buff_size ? buff_size : ONE_MEGABYTE); + + if (size < ONE_MEGABYTE || size > max_allowed_buff_size) { qdf_print("%s: Cannot Set Pktlog Buffer size of %d bytes." "Min required is %d MB and Max allowed is %d MB.\n", __func__, size, (ONE_MEGABYTE/ONE_MEGABYTE), - (MAX_ALLOWED_PKTLOG_SIZE/ONE_MEGABYTE)); + (max_allowed_buff_size / ONE_MEGABYTE)); pl_info->curr_pkt_state = PKTLOG_OPR_NOT_IN_PROGRESS; qdf_print("%s: Invalid requested buff size", __func__); return -EINVAL; diff --git a/drivers/staging/qca-wifi-host-cmn/wmi/inc/wmi_unified_api.h b/drivers/staging/qca-wifi-host-cmn/wmi/inc/wmi_unified_api.h index c88895d52551..b2f94f61a4e1 100644 --- a/drivers/staging/qca-wifi-host-cmn/wmi/inc/wmi_unified_api.h +++ b/drivers/staging/qca-wifi-host-cmn/wmi/inc/wmi_unified_api.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -68,6 +68,10 @@ #include "wlan_ipa_public_struct.h" #endif +#ifdef WLAN_FEATURE_PKT_CAPTURE +#include "wlan_pkt_capture_public_structs.h" +#endif + typedef qdf_nbuf_t wmi_buf_t; #define wmi_buf_data(_buf) qdf_nbuf_data(_buf) @@ -198,7 +202,7 @@ wmi_unified_remove_work(struct wmi_unified *wmi_handle); #ifdef NBUF_MEMORY_DEBUG #define wmi_buf_alloc(h, l) wmi_buf_alloc_debug(h, l, __FILE__, __LINE__) wmi_buf_t -wmi_buf_alloc_debug(wmi_unified_t wmi_handle, uint16_t len, +wmi_buf_alloc_debug(wmi_unified_t wmi_handle, uint32_t len, uint8_t *file_name, uint32_t line_num); #else /** @@ -411,6 +415,65 @@ void *wmi_unified_get_pdev_handle(struct wmi_soc *soc, uint32_t pdev_idx); void wmi_process_fw_event(struct wmi_unified *wmi_handle, wmi_buf_t evt_buf); uint16_t wmi_get_max_msg_len(wmi_unified_t wmi_handle); +/** + * wmi_unified_extract_roam_trigger_stats() - Extract roam trigger related + * stats + * @wmi: wmi handle + * @evt_buf: Pointer to the event buffer + * @trig: Pointer to destination structure to fill data + * @idx: TLV id + * + * Return: QDF_STATUS + */ +QDF_STATUS +wmi_unified_extract_roam_trigger_stats(wmi_unified_t wmi, void *evt_buf, + struct wmi_roam_trigger_info *trig, + uint8_t idx); + +/** + * wmi_unified_extract_roam_scan_stats() - Extract roam scan stats from + * firmware + * @wmi: wmi handle + * @evt_buf: Pointer to the event buffer + * @dst: Pointer to destination structure to fill data + * @idx: TLV id + * @chan_idx: Index of the channel frequency for this roam trigger + * @ap_idx: Index of the candidate AP for this roam trigger + * + * Return: QDF_STATUS + */ +QDF_STATUS +wmi_unified_extract_roam_scan_stats(wmi_unified_t wmi, void *evt_buf, + struct wmi_roam_scan_data *dst, uint8_t idx, + uint8_t chan_idx, uint8_t ap_idx); +/** + * wmi_unified_extract_roam_result_stats() - Extract roam result related stats + * @wmi: wmi handle + * @evt_buf: Pointer to the event buffer + * @dst: Pointer to destination structure to fill data + * @idx: TLV id + * + * Return: QDF_STATUS + */ +QDF_STATUS +wmi_unified_extract_roam_result_stats(wmi_unified_t wmi, void *evt_buf, + struct wmi_roam_result *dst, + uint8_t idx); + +/** + * wmi_unified_extract_roam_11kv_stats() - Extract BTM/Neigh report stats + * @wmi: wmi handle + * @evt_buf: Pointer to the event buffer + * @dst: Pointer to destination structure to fill data + * @idx: TLV id + * @rpt_idx: index of the current channel + * + * Return: QDF_STATUS + */ +QDF_STATUS +wmi_unified_extract_roam_11kv_stats(wmi_unified_t wmi, void *evt_buf, + struct wmi_neighbor_report_data *dst, + uint8_t idx, uint8_t rpt_idx); QDF_STATUS wmi_unified_vdev_create_send(void *wmi_hdl, uint8_t macaddr[IEEE80211_ADDR_LEN], @@ -934,6 +997,26 @@ QDF_STATUS wmi_unified_wow_timer_pattern_cmd(void *wmi_hdl, uint8_t vdev_id, QDF_STATUS wmi_unified_nat_keepalive_en_cmd(void *wmi_hdl, uint8_t vdev_id); +#ifdef WLAN_SEND_DSCP_UP_MAP_TO_FW +/** + * wmi_unified_send_dscp_tid_map_cmd() - Send dscp-to-tid map values cmd + * @wmi_hdl: wmi handle + * @dscp_to_tid_map: array of dscp_tid map values + * + * Send dscp-to-tid map values to FW. + * + * Return: QDF_STATUS + */ +QDF_STATUS +wmi_unified_send_dscp_tid_map_cmd(void *wmi_hdl, uint32_t *dscp_to_tid_map); +#else +static inline QDF_STATUS +wmi_unified_send_dscp_tid_map_cmd(void *wmi_hdl, uint32_t *dscp_to_tid_map) +{ + return QDF_STATUS_SUCCESS; +} +#endif /* WLAN_SEND_DSCP_UP_MAP_TO_FW */ + /** * wmi_unified_set_latency_config_cmd() * @wmi_handle: wmi handle @@ -969,10 +1052,34 @@ QDF_STATUS wmi_unified_oem_dma_ring_cfg(void *wmi_hdl, QDF_STATUS wmi_unified_dbr_ring_cfg(void *wmi_hdl, struct direct_buf_rx_cfg_req *cfg); +/** + * wmi_unified_start_oem_data_cmd() - start oem data request to target + * wmi_unified_start_oem_data_cmd() - start oem data request to target + * @data_len: the length of @data + * @data: the pointer to data buf + * + * This is legacy api for oem data request, using wmi command + * WMI_OEM_REQ_CMDID. + * + * Return: QDF_STATUS_SUCCESS on success and QDF_STATUS_E_FAILURE for failure + */ QDF_STATUS wmi_unified_start_oem_data_cmd(void *wmi_hdl, uint32_t data_len, uint8_t *data); +#ifdef FEATURE_OEM_DATA +/** + * wmi_unified_start_oemv2_data_cmd() - start oem data cmd to target + * @wmi_handle: wmi handle + * @params: oem data params + * + * This is common api for oem data, using wmi command WMI_OEM_DATA_CMDID. + * + * Return: QDF_STATUS_SUCCESS on success and QDF_STATUS_E_FAILURE for failure + */ +QDF_STATUS wmi_unified_start_oemv2_data_cmd(wmi_unified_t wmi_handle, + struct oem_data *params); +#endif QDF_STATUS wmi_unified_dfs_phyerr_filter_offload_en_cmd(void *wmi_hdl, bool dfs_phyerr_filter_offload); @@ -1097,11 +1204,8 @@ QDF_STATUS wmi_unified_send_roam_scan_offload_ap_cmd(void *wmi_hdl, struct ap_profile_params *ap_profile); #endif -QDF_STATUS wmi_unified_roam_scan_offload_scan_period(void *wmi_hdl, - uint32_t scan_period, - uint32_t scan_age, - uint32_t vdev_id, - uint32_t full_roam_scan_period); +QDF_STATUS wmi_unified_roam_scan_offload_scan_period( + void *wmi_hdl, struct roam_scan_period_params *param); QDF_STATUS wmi_unified_roam_scan_offload_chan_list_cmd(void *wmi_hdl, uint8_t chan_count, @@ -2144,6 +2248,16 @@ QDF_STATUS wmi_unified_ndp_end_req_cmd_send(void *wmi_hdl, QDF_STATUS wmi_extract_ndp_initiator_rsp(wmi_unified_t wmi_handle, uint8_t *data, struct nan_datapath_initiator_rsp *rsp); +/** + * wmi_extract_nan_msg - api to extract ndp dmesg buffer to print logs + * @data: event buffer + * @msg: buffer to populate + * + * Return: status of operation + */ +QDF_STATUS wmi_extract_nan_msg(wmi_unified_t wmi_handle, uint8_t *data, + struct nan_dump_msg *msg); + /** * wmi_extract_ndp_ind - api to extract ndp indication struct from even buffer * @wmi_hdl: wmi handle @@ -2231,6 +2345,44 @@ QDF_STATUS wmi_unified_send_btm_config(void *wmi_hdl, QDF_STATUS wmi_unified_send_bss_load_config(void *wmi_hdl, struct wmi_bss_load_config *params); +/** + * wmi_unified_send_disconnect_roam_params() - Send disconnect roam trigger + * parameters to firmware + * @wmi_hdl: wmi handle + * @params: pointer to wmi_disconnect_roam_params + * + * Return: QDF_STATUS + */ +QDF_STATUS +wmi_unified_send_disconnect_roam_params(wmi_unified_t wmi_handle, + struct wmi_disconnect_roam_params *req); + +/** + * wmi_unified_send_idle_roam_params() - Send idle roam trigger params to fw + * @wmi_hdl: wmi handle + * @params: pointer to wmi_idle_roam_params + * + * Return: QDF_STATUS + */ +QDF_STATUS +wmi_unified_send_idle_roam_params(wmi_unified_t wmi_handle, + struct wmi_idle_roam_params *req); + +/** + * wmi_unified_send_roam_preauth_status() - Send roam preauthentication status + * to target. + * @wmi_handle: wmi handle + * @param: Roam auth status params + * + * This function passes preauth status of WPA3 SAE auth to firmware. It is + * called when external_auth_status event is received from userspace. + * + * Return: QDF_STATUS + */ +QDF_STATUS +wmi_unified_send_roam_preauth_status(wmi_unified_t wmi_handle, + struct wmi_roam_auth_status_params *param); + /** * wmi_unified_send_obss_detection_cfg_cmd() - WMI function to send obss * detection configuration to FW. @@ -2464,6 +2616,17 @@ void wmi_process_fw_event_worker_thread_ctx(struct wmi_unified *wmi_handle, QDF_STATUS wmi_unified_send_mws_coex_req_cmd(struct wmi_unified *wmi_handle, uint32_t vdev_id, uint32_t cmd_id); +/** + * wmi_unified_send_idle_trigger_monitor() - send idle trigger monitor command + * @wmi_handle: WMI handle + * @val: idle trigger monitor value - 1 for idle monitor on, 0 for idle monitor + * off + * + * Return: QDF_STATUS_SUCCESS if success, else returns proper error code. + */ +QDF_STATUS +wmi_unified_send_idle_trigger_monitor(wmi_unified_t wmi_handle, uint8_t val); + #ifdef WLAN_FEATURE_ROAM_OFFLOAD /** * wmi_unified_set_roam_triggers() - send roam trigger bitmap @@ -2477,4 +2640,122 @@ QDF_STATUS wmi_unified_send_mws_coex_req_cmd(struct wmi_unified *wmi_handle, QDF_STATUS wmi_unified_set_roam_triggers(wmi_unified_t wmi_handle, struct roam_triggers *triggers); #endif + +/** + * wmi_unified_get_roam_scan_ch_list() - send roam scan channel list get cmd + * @wmi_handle: wmi handle + * @vdev_id: vdev id + * + * This function sends roam scan channel list get command to firmware. + * + * Return: QDF_STATUS_SUCCESS on success and QDF_STATUS_E_FAILURE for failure + */ +QDF_STATUS wmi_unified_get_roam_scan_ch_list(wmi_unified_t wmi_handle, + uint8_t vdev_id); + +#ifdef FEATURE_ANI_LEVEL_REQUEST +/** + * wmi_unified_ani_level_cmd_send() - WMI function to send get ani level cmd + * @wmi_hdl: WMI handle + * @freqs: pointer to list of freqs for which ANI levels are to be fetched + * @num_freqs: number of freqs in the above parameter + * + * Return: QDF_STATUS_SUCCESS if success, else returns proper error code. + */ +QDF_STATUS wmi_unified_ani_level_cmd_send(wmi_unified_t wmi_handle, + uint32_t *freqs, + uint8_t num_freqs); + +/** + * wmi_unified_extract_ani_level() - WMI function to receive ani level cmd + * @wmi_hdl: WMI handle + * @info: pointer to ANI data received from the FW and stored in HOST + * @num_freqs: number of freqs in the above parameter + * + * Return: QDF_STATUS_SUCCESS if success, else returns proper error code. + */ +QDF_STATUS wmi_unified_extract_ani_level(wmi_unified_t wmi_handle, + uint8_t *data, + struct wmi_host_ani_level_event **info, + uint32_t *num_freqs); +#endif /* FEATURE_ANI_LEVEL_REQUEST */ + +#ifdef WLAN_FEATURE_PKT_CAPTURE +/** + * wmi_unified_extract_vdev_mgmt_offload_event() - Extract mgmt offload params + * @wmi: WMI handle + * @evt_buf: Event buffer + * @params: Management offload event params + * + * WMI function to extract management offload event params + * + * Return: QDF_STATUS + */ +QDF_STATUS +wmi_unified_extract_vdev_mgmt_offload_event(wmi_unified_t wmi, void *evt_buf, + struct mgmt_offload_event_params *params); +#endif + +#ifdef FEATURE_WLAN_TIME_SYNC_FTM +/** + * wmi_unified_send_wlan_time_sync_ftm_trigger() - send ftm timesync trigger cmd + * @wmi_handle: wmi handle + * @vdev_id: vdev id + * @burst_mode: mode reg getting time sync relation from FW + * + * This function indicates the FW to trigger wlan time sync using FTM + * + * Return: QDF_STATUS_SUCCESS on success and QDF_STATUS_E_FAILURE for failure + */ +QDF_STATUS +wmi_unified_send_wlan_time_sync_ftm_trigger(wmi_unified_t wmi_handle, + uint32_t vdev_id, + bool burst_mode); + +/** + * wmi_unified_send_wlan_time_sync_qtime() - send ftm time sync qtime cmd. + * @wmi_handle: wmi handle + * @vdev_id: vdev id + * @lpass_ts: audio qtime + * + * This function sends the wmi cmd to FW having audio qtime + * + * Return: QDF_STATUS_SUCCESS on success and QDF_STATUS_E_FAILURE for failure + */ +QDF_STATUS +wmi_unified_send_wlan_time_sync_qtime(wmi_unified_t wmi_handle, + uint32_t vdev_id, uint64_t lpass_ts); + +/** + * wmi_unified_extract_time_sync_ftm_start_stop_params() - extract FTM time sync + * params + * @wmi_handle: wmi handle + * @evt_buf: event buffer + * @param: params received in start stop ftm timesync event + * + * This function extracts the params from ftm timesync start stop event + * + * Return: QDF_STATUS_SUCCESS on success and QDF_STATUS_E_FAILURE for failure + */ +QDF_STATUS +wmi_unified_extract_time_sync_ftm_start_stop_params( + wmi_unified_t wmi_handle, void *evt_buf, + struct ftm_time_sync_start_stop_params *param); + +/** + * wmi_unified_extract_time_sync_ftm_offset() - extract timesync FTM offset + * @wmi_handle: wmi handle + * @evt_buf: event buffer + * @param: params received in ftm timesync offset event + * + * This function extracts the params from ftm timesync offset event + * + * Return: QDF_STATUS_SUCCESS on success and QDF_STATUS_E_FAILURE for failure + */ +QDF_STATUS +wmi_unified_extract_time_sync_ftm_offset(wmi_unified_t wmi_handle, + void *evt_buf, + struct ftm_time_sync_offset *param); +#endif /* FEATURE_WLAN_TIME_SYNC_FTM */ + #endif /* _WMI_UNIFIED_API_H_ */ diff --git a/drivers/staging/qca-wifi-host-cmn/wmi/inc/wmi_unified_param.h b/drivers/staging/qca-wifi-host-cmn/wmi/inc/wmi_unified_param.h index 3977ad486e84..e0397cdfe68a 100644 --- a/drivers/staging/qca-wifi-host-cmn/wmi/inc/wmi_unified_param.h +++ b/drivers/staging/qca-wifi-host-cmn/wmi/inc/wmi_unified_param.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -67,7 +67,7 @@ #ifdef WLAN_FEATURE_ROAM_OFFLOAD #define WMI_BTK_KEY_LEN 32 #define WMI_ROAM_R0KH_ID_MAX_LEN 48 -#define WMI_ROAM_SCAN_PSK_SIZE 32 +#define WMI_ROAM_SCAN_PSK_SIZE 48 #endif #define WMI_NOISE_FLOOR_DBM_DEFAULT (-96) #define WMI_EXTSCAN_MAX_HOTLIST_SSIDS 8 @@ -641,6 +641,20 @@ struct channel_param { uint8_t reg_class_id; }; +#ifdef FEATURE_OEM_DATA +/** + * struct oem_data - oem data to be sent to firmware + * @vdev_id: Unique identifier assigned to the vdev + * @data_len: len of data + * @data: the pointer to the buffer containing data + */ +struct oem_data { + uint8_t vdev_id; + size_t data_len; + uint8_t *data; +}; +#endif + /** * struct vdev_stop_params - vdev stop cmd parameter * @vdev_id: vdev id @@ -1298,6 +1312,7 @@ struct ap_ps_params { /** * struct scan_chan_list_params - scan channel list cmd parameter * @num_scan_chans: no of scan channels + * @@max_bw_support_present: max BW support present * @chan_info: pointer to wmi channel info */ #ifdef CONFIG_MCL @@ -1322,6 +1337,7 @@ typedef struct { struct scan_chan_list_params { uint32_t pdev_id; uint8_t num_scan_chans; + bool max_bw_support_present; wmi_channel_param *chan_info; }; #else @@ -1918,6 +1934,7 @@ typedef struct { #define WMI_FILS_MAX_RIK_LENGTH WMI_FILS_MAX_RRK_LENGTH #define WMI_FILS_MAX_REALM_LENGTH 256 #define WMI_FILS_MAX_USERNAME_LENGTH 16 +#define WMI_FILS_FT_MAX_LEN 48 /** * struct roam_fils_params - Roam FILS params @@ -1930,6 +1947,8 @@ typedef struct { * @rik_length: length of @rik * @realm: realm * @realm_len: length of @realm + * @fils_ft: xx_key for FT-FILS connection + * @fils_ft_len: length of FT-FILS */ struct roam_fils_params { uint8_t username[WMI_FILS_MAX_USERNAME_LENGTH]; @@ -1941,6 +1960,8 @@ struct roam_fils_params { uint32_t rik_length; uint8_t realm[WMI_FILS_MAX_REALM_LENGTH]; uint32_t realm_len; + uint8_t fils_ft[WMI_FILS_FT_MAX_LEN]; + uint8_t fils_ft_len; }; /* struct roam_offload_scan_params - structure @@ -1975,6 +1996,15 @@ struct roam_fils_params { * @roam_fils_params: roam fils params * @rct_validity_timer: duration value for which the entries in * roam candidate table are valid + * @adaptve_11r: Adaptive 11r AP + * @is_sae_same_pmk: Flag to indicate fw whether WLAN_SAE_SINGLE_PMK feature is + * enable or not + * @roam_scan_inactivity_time: inactivity monitoring time in ms for which the + * device is considered to be inactive + * @roam_inactive_data_packet_count: Maximum allowed data packets count during + * roam_scan_inactivity_time. + * @roam_scan_period_after_inactivity: Roam scan period in ms after device is + * in inactive state. */ struct roam_offload_scan_params { uint8_t is_roam_req_valid; @@ -1997,6 +2027,8 @@ struct roam_offload_scan_params { bool fw_okc; bool fw_pmksa_cache; uint32_t rct_validity_timer; + bool is_adaptive_11r; + bool is_sae_same_pmk; #endif uint32_t min_delay_btw_roam_scans; uint32_t roam_trigger_reason_bitmask; @@ -2012,6 +2044,9 @@ struct roam_offload_scan_params { uint32_t assoc_ie_length; uint8_t assoc_ie[MAX_ASSOC_IE_LENGTH]; bool add_fils_tlv; + uint32_t roam_scan_inactivity_time; + uint32_t roam_inactive_data_packet_count; + uint32_t roam_scan_period_after_inactivity; #ifdef WLAN_FEATURE_FILS_SK struct roam_fils_params roam_fils_params; #endif @@ -2204,6 +2239,9 @@ struct param_slot_scoring { * ap over the roam score of the current ap * @roam_trigger_bitmap: bitmap of roam triggers on which roam_score_delta * will be applied + * @vendor_roam_score_algorithm: Preferred algorithm for roam candidate + * selection + * @cand_min_roam_score_delta: candidate min roam score delta value * @rssi_scoring: RSSI scoring information. * @esp_qbss_scoring: ESP/QBSS scoring percentage information * @oce_wan_scoring: OCE WAN metrics percentage information @@ -2226,21 +2264,111 @@ struct scoring_param { uint32_t nss_index_score; uint32_t roam_score_delta; uint32_t roam_trigger_bitmap; + uint32_t vendor_roam_score_algorithm; + uint32_t cand_min_roam_score_delta; struct rssi_scoring rssi_scoring; struct param_slot_scoring esp_qbss_scoring; struct param_slot_scoring oce_wan_scoring; }; +/* + * Currently roam score delta value and min rssi values are sent + * for 2 triggers + */ +#define NUM_OF_ROAM_TRIGGERS 2 +#define IDLE_ROAM_TRIGGER 0 +#define BTM_ROAM_TRIGGER 1 + +#define DEAUTH_MIN_RSSI 0 +#define BMISS_MIN_RSSI 1 + +/** + * enum roam_trigger_reason - Reason for triggering roam + * ROAM_TRIGGER_REASON_NONE: Roam trigger reason none + * ROAM_TRIGGER_REASON_PER: Roam triggered due to packet error + * ROAM_TRIGGER_REASON_BMISS: Roam triggered due to beacon miss + * ROAM_TRIGGER_REASON_LOW_RSSI: Roam triggered due to low RSSI of current + * connected AP. + * ROAM_TRIGGER_REASON_HIGH_RSSI: Roam triggered because sta is connected to + * a AP in 2.4GHz band and a better 5GHz AP is available + * ROAM_TRIGGER_REASON_PERIODIC: Roam triggered as better AP was found during + * periodic roam scan. + * ROAM_TRIGGER_REASON_MAWC: Motion Aided WiFi Connectivity triggered roam. + * ROAM_TRIGGER_REASON_DENSE: Roaming triggered due to dense environment + * detected. + * ROAM_TRIGGER_REASON_BACKGROUND: Roam triggered due to current AP having + * poor rssi and scan candidate found in scan results provided by other + * scan clients. + * ROAM_TRIGGER_REASON_FORCED: Forced roam trigger. + * ROAM_TRIGGER_REASON_BTM: Roam triggered due to AP sent BTM query with + * Disassoc imminent bit set. + * ROAM_TRIGGER_REASON_UNIT_TEST: Roam triggered due to unit test command. + * ROAM_TRIGGER_REASON_BSS_LOAD: Roam triggered due to high channel utilization + * in the current connected channel + * ROAM_TRIGGER_REASON_DEAUTH: Roam triggered due to deauth received from the + * current connected AP. + * ROAM_TRIGGER_REASON_IDLE: Roam triggered due to inactivity of the device. + * ROAM_TRIGGER_REASON_STA_KICKOUT: Roam triggered due to sta kickout event. + * ROAM_TRIGGER_REASON_MAX: Maximum number of roam triggers + */ +enum roam_trigger_reason { + ROAM_TRIGGER_REASON_NONE = 0, + ROAM_TRIGGER_REASON_PER, + ROAM_TRIGGER_REASON_BMISS, + ROAM_TRIGGER_REASON_LOW_RSSI, + ROAM_TRIGGER_REASON_HIGH_RSSI, + ROAM_TRIGGER_REASON_PERIODIC, + ROAM_TRIGGER_REASON_MAWC, + ROAM_TRIGGER_REASON_DENSE, + ROAM_TRIGGER_REASON_BACKGROUND, + ROAM_TRIGGER_REASON_FORCED, + ROAM_TRIGGER_REASON_BTM, + ROAM_TRIGGER_REASON_UNIT_TEST, + ROAM_TRIGGER_REASON_BSS_LOAD, + ROAM_TRIGGER_REASON_DEAUTH, + ROAM_TRIGGER_REASON_IDLE, + ROAM_TRIGGER_REASON_STA_KICKOUT, + ROAM_TRIGGER_REASON_MAX, +}; + +/** + * struct roam_trigger_min_rssi - structure to hold minimum rssi value of + * candidate APs for each roam trigger + * @min_rssi: minimum RSSI of candidate AP for the trigger reason specified in + * trigger_id + * @trigger_reason: Roam trigger reason + */ +struct roam_trigger_min_rssi { + int32_t min_rssi; + enum roam_trigger_reason trigger_reason; +}; + +/** + * struct roam_trigger_score_delta - structure to hold roam score delta value of + * candidate APs for each roam trigger + * @roam_score_delta: delta value in score of the candidate AP for the roam + * trigger mentioned in the trigger_id. + * @trigger_reason: Roam trigger reason + */ +struct roam_trigger_score_delta { + uint32_t roam_score_delta; + enum roam_trigger_reason trigger_reason; +}; + /** * struct ap_profile_params - ap profile params * @vdev_id: vdev id * @profile: ap profile to match candidate * @param: scoring params to short candidate + * @min_rssi_params: Min RSSI values for different roam triggers + * @score_delta_params: Roam score delta values for different triggers */ struct ap_profile_params { uint8_t vdev_id; struct ap_profile profile; struct scoring_param param; + struct roam_trigger_min_rssi min_rssi_params[NUM_OF_ROAM_TRIGGERS]; + struct roam_trigger_score_delta score_delta_param[NUM_OF_ROAM_TRIGGERS]; }; /** @@ -3120,6 +3248,7 @@ struct tdls_peer_state_params { * @teardown_notification_ms: tdls teardown notification interval * @tdls_peer_kickout_threshold: tdls packet threshold for * peer kickout operation + * @tdls_discovery_wake_timeout: Discovery wake timeout */ struct wmi_tdls_params { uint32_t vdev_id; @@ -3137,6 +3266,7 @@ struct wmi_tdls_params { uint32_t puapsd_rx_frame_threshold; uint32_t teardown_notification_ms; uint32_t tdls_peer_kickout_threshold; + uint32_t tdls_discovery_wake_timeout; }; #ifndef CONVERGED_TDLS_ENABLE @@ -3510,6 +3640,8 @@ struct hlp_params { * @cache_id: PMK Cache ID * @cat_flag: whether (bssid) or (ssid,cache_id) is valid * @action_flag: add/delete the entry + * @is_flush_all: FLAG to indicate PMKSA flush. True if PMKSA cache flush is + * needed. */ struct wmi_unified_pmk_cache { uint32_t tlv_header; @@ -3523,6 +3655,7 @@ struct wmi_unified_pmk_cache { uint32_t cache_id; uint32_t cat_flag; uint32_t action_flag; + bool is_flush_all; }; @@ -5395,6 +5528,50 @@ typedef struct { uint32_t rx_duration_us; } wmi_host_chan_stats; +#ifdef FEATURE_WLAN_TIME_SYNC_FTM + +#define FTM_TIME_SYNC_QTIME_PAIR_MAX 32 + +/** + * struct ftm_time_sync_start_stop_param- Get wlan time sync ftm info + * @vdev_id: vdev id + * @timer_interval: periodicity to trigger wlan time sync strobe + * @num_reads: Number of times to trigger wlabn time sync strobe + * @qtime: ref Qtimer value + * @mac_time: ref Mac timer value + */ +struct ftm_time_sync_start_stop_params { + uint32_t vdev_id; + uint32_t timer_interval; + uint32_t num_reads; + uint64_t qtime; + uint64_t mac_time; +}; + +/** + * struct wlan_time_sync_qtime_pair- Get wlan time sync qtime pair value + * @vdev_id: vdev id + * @qtime_master: qtimer value of master + * @qtime_slave: qtimer value of slave + */ +struct wlan_time_sync_qtime_pair { + uint64_t qtime_master; + uint64_t qtime_slave; +}; + +/** + * struct ftm_time_sync_offset- Get ftm time sync offset + * @vdev_id: vdev id + * @num_qtime: number of qtime values received + * @pairs: array of qtime pairs + */ +struct ftm_time_sync_offset { + uint32_t vdev_id; + uint32_t num_qtime; + struct wlan_time_sync_qtime_pair pairs[FTM_TIME_SYNC_QTIME_PAIR_MAX]; +}; +#endif + #define WMI_EVENT_ID_INVALID 0 /** * Host based ENUM IDs for events to abstract target enums for event_id @@ -5560,6 +5737,7 @@ typedef enum { wmi_ndp_responder_rsp_event_id, wmi_ndp_end_indication_event_id, wmi_ndp_end_rsp_event_id, + wmi_nan_dmesg_event_id, wmi_ndl_schedule_update_event_id, wmi_oem_response_event_id, wmi_peer_stats_info_event_id, @@ -5601,6 +5779,17 @@ typedef enum { wmi_vdev_get_mws_coex_idrx_state_eventid, wmi_vdev_get_mws_coex_antenna_sharing_state_eventid, wmi_coex_report_antenna_isolation_event_id, + wmi_get_ani_level_event_id, + wmi_oem_data_event_id, + wmi_roam_auth_offload_event_id, + wmi_mgmt_offload_data_event_id, + wmi_roam_pmkid_request_event_id, +#ifdef FEATURE_WLAN_TIME_SYNC_FTM + wmi_wlan_time_sync_ftm_start_stop_event_id, + wmi_wlan_time_sync_q_master_slave_offset_eventid, +#endif + wmi_roam_stats_event_id, + wmi_roam_scan_chan_list_id, wmi_events_max, } wmi_conv_event_id; @@ -6039,6 +6228,16 @@ typedef enum { wmi_service_sta_plus_sta_support, wmi_service_tx_compl_tsf64, wmi_service_three_way_coex_config_legacy, + wmi_service_wpa3_ft_sae_support, + wmi_service_wpa3_ft_suite_b_support, + wmi_service_ft_fils, + wmi_service_adaptive_11r_support, + wmi_service_sae_roam_support, + wmi_service_owe_roam_support, + wmi_service_nan_vdev, + wmi_service_packet_capture_support, + wmi_service_time_sync_ftm, + wmi_roam_scan_chan_list_to_host_support, wmi_services_max, } wmi_conv_service_ids; #define WMI_SERVICE_UNAVAILABLE 0xFFFF @@ -6158,6 +6357,8 @@ struct wmi_host_fw_abi_ver { * @twt_ap_sta_count: Max no of STA with which TWT sessions can be formed * by the AP * @three_way_coex_config_legacy_en: enable three way coex legacy feature + * @time_sync_ftm: enable ftm based time sync + * @nan_separate_iface_support: Separate iface creation for NAN */ typedef struct { uint32_t num_vdevs; @@ -6204,7 +6405,8 @@ typedef struct { mgmt_comp_evt_bundle_support:1, tx_msdu_new_partition_id_support:1, new_htt_msg_format:1, - peer_unmap_conf_support:1; + peer_unmap_conf_support:1, + pktcapture_support:1; uint32_t iphdr_pad_config; uint32_t qwrap_config:16, @@ -6236,6 +6438,8 @@ typedef struct { uint32_t twt_ap_sta_count; bool tstamp64_en; bool three_way_coex_config_legacy_en; + bool time_sync_ftm; + bool nan_separate_iface_support; } target_resource_config; /** @@ -8116,6 +8320,28 @@ struct wmi_limit_off_chan_param { bool skip_dfs_chans; }; +/** + * struct roam_scan_period_params - Roam scan period parameters + * @vdev_id: Vdev for which the scan period parameters are sent + * @scan_period: Opportunistic scan runs on a timer for scan_period + * @scan_age: Duration after which the scan entries are to be aged out + * @roam_scan_inactivity_time: inactivity monitoring time in ms for which the + * device is considered to be inactive + * @roam_inactive_data_packet_count: Maximum allowed data packets count during + * roam_scan_inactivity_time. + * @roam_scan_period_after_inactivity: Roam scan period in ms after device is + * in inactive state. + */ +struct roam_scan_period_params { + uint32_t vdev_id; + uint32_t scan_period; + uint32_t scan_age; + uint32_t roam_scan_inactivity_time; + uint32_t roam_inactive_data_packet_count; + uint32_t roam_scan_period_after_inactivity; + uint32_t full_scan_period; +}; + /** * struct wmi_mawc_roam_params - Motion Aided wireless connectivity params * @vdev_id: VDEV on which the parameters should be applied @@ -8133,6 +8359,7 @@ struct wmi_mawc_roam_params { uint8_t rssi_stationary_high_adjust; uint8_t rssi_stationary_low_adjust; }; + /** * struct wmi_btm_config - BSS Transition Management offload params * @vdev_id: VDEV on which the parameters should be applied @@ -8140,8 +8367,11 @@ struct wmi_mawc_roam_params { * @btm_solicited_timeout: Timeout value for waiting BTM request * @btm_max_attempt_cnt: Maximum attempt for sending BTM query to ESS * @btm_sticky_time: Stick time after roaming to new AP by BTM + * @btm_query_bitmask: roam trigger reasons to trigger BTM Query * @disassoc_timer_threshold: threshold value till which the firmware can * wait before triggering the roam scan after receiving the disassoc iminent + * @btm_candidate_min_score: Minimum score of the AP to consider it as a + * candidate if the roam trigger is BTM kickout. */ struct wmi_btm_config { uint8_t vdev_id; @@ -8149,18 +8379,78 @@ struct wmi_btm_config { uint32_t btm_solicited_timeout; uint32_t btm_max_attempt_cnt; uint32_t btm_sticky_time; + uint32_t btm_query_bitmask; uint32_t disassoc_timer_threshold; + uint32_t btm_candidate_min_score; }; /** * struct wmi_bss_load_config - BSS load trigger parameters * @vdev_id: VDEV on which the parameters should be applied * @bss_load_threshold: BSS load threshold after which roam scan should trigger + * @bss_load_sample_time: Time duration in milliseconds for which the bss load + * trigger needs to be enabled + * @rssi_threshold_5ghz: RSSI threshold of the current connected AP below which + * roam should be triggered if bss load threshold exceeds the configured value. + * This value is applicable only when we are connected in 5GHz band. + * @rssi_threshold_24ghz: RSSI threshold of the current connected AP below which + * roam should be triggered if bss load threshold exceeds the configured value. + * This value is applicable only when we are connected in 2.4GHz band. */ struct wmi_bss_load_config { uint32_t vdev_id; uint32_t bss_load_threshold; uint32_t bss_load_sample_time; + int32_t rssi_threshold_5ghz; + int32_t rssi_threshold_24ghz; +}; + +/** + * struct wmi_idle_roam_params - Idle roam trigger parameters + * @vdev_id: VDEV on which the parameters should be applied + * @enable: Enable/Disable Idle roaming + * @band: Connected AP band + * @conn_ap_rssi_delta: Rssi change of connected AP in dBm + * @conn_ap_min_rssi: If connected AP rssi is less than min rssi trigger roam + * @inactive_time: Connected AP idle time + * @data_pkt_count: Data packet count allowed during idle time + */ +struct wmi_idle_roam_params { + uint32_t vdev_id; + bool enable; + uint32_t band; + uint32_t conn_ap_rssi_delta; + int32_t conn_ap_min_rssi; + uint32_t inactive_time; + uint32_t data_pkt_count; +}; + +/** + * struct wmi_disconnect_roam_params - Emergency deauth/disconnect roam params + * @vdev_id: VDEV on which the parameters should be applied + * @enable: Enable or disable disconnect roaming. + */ +struct wmi_disconnect_roam_params { + uint32_t vdev_id; + bool enable; +}; + +/** + * struct wmi_roam_auth_status_params - WPA3 roam auth response status + * parameters + * @vdev_id: Vdev on which roam preauth is happening + * @preauth_status: Status of the Auth response. + * IEEE80211_STATUS_SUCCESS(0) for success. Corresponding + * IEEE80211 failure status code for failure. + * + * @bssid: Candidate BSSID + * @pmkid: PMKID derived for the auth + */ +struct wmi_roam_auth_status_params { + uint32_t vdev_id; + uint32_t preauth_status; + struct qdf_mac_addr bssid; + uint8_t pmkid[PMKID_LEN]; }; /** @@ -8662,6 +8952,161 @@ struct wmi_roam_scan_stats_res { /* End of roam scan stats definitions */ +#define MAX_ROAM_CANDIDATE_AP 9 +#define MAX_ROAM_SCAN_CHAN 38 +#define MAX_ROAM_SCAN_STATS_TLV 5 + +/** + * struct wmi_roam_btm_trigger_data - BTM roam trigger related information + * @btm_request_mode: BTM request mode - solicited/unsolicited + * @disassoc_timer: Number of TBTT before AP disassociates the STA in ms + * @validity_interval: Preferred candidate list validity interval in ms + * @candidate_list_count: Number of candidates in BTM request. + * @btm_resp_status: Status code of the BTM response. + */ +struct wmi_roam_btm_trigger_data { + uint32_t btm_request_mode; + uint32_t disassoc_timer; + uint32_t validity_interval; + uint32_t candidate_list_count; + uint32_t btm_resp_status; +}; + +/** + * struct wmi_roam_cu_trigger_data - BSS Load roam trigger parameters + * @cu_load: Connected AP CU load percentage + */ +struct wmi_roam_cu_trigger_data { + uint32_t cu_load; + /* TODO: Add threshold value */ +}; + +/** + * Struct wmi_roam_rssi_trigger_data - RSSI roam trigger related + * parameters + * @threshold: RSSI threshold value in dBm for LOW rssi roam trigger + */ +struct wmi_roam_rssi_trigger_data { + uint32_t threshold; +}; + +/** + * struct wmi_roam_deauth_trigger_data - Deauth roaming trigger related + * parameters + * @type: 1- Deauthentication 2- Disassociation + * @reason: Status code of the Deauth/Disassoc received + */ +struct wmi_roam_deauth_trigger_data { + uint32_t type; + uint32_t reason; +}; + +/** + * struct wmi_roam_candidate_info - Roam scan candidate APs related info + * @timestamp: Host timestamp in millisecs + * @type: 0 - Candidate AP; 1 - Current connected AP. + * @bssid: AP bssid. + * @freq: Channel frquency + * @cu_load: Channel utilization load of the AP. + * @cu_score: Channel Utilization score. + * @rssi: Candidate AP rssi + * @rssi_score: AP RSSI score + * @total_score: Total score of the candidate AP. + * @etp: Estimated throughput value of the AP in Mbps + */ +struct wmi_roam_candidate_info { + uint32_t timestamp; + uint8_t type; + struct qdf_mac_addr bssid; + uint16_t freq; + uint32_t cu_load; + uint32_t cu_score; + uint32_t rssi; + uint32_t rssi_score; + uint32_t total_score; + uint32_t etp; +}; + +/** + * struct wmi_roam_scan_data - Roam scan event details + * @present: Flag to check if the roam scan tlv is present + * @type: 0 - Partial roam scan; 1 - Full roam scan + * @num_ap: Number of candidate APs. + * @num_chan: Number of channels. + * @next_rssi_threshold: Next roam can trigger rssi threshold + * @chan_freq: List of frequencies scanned as part of roam scan + * @ap: List of candidate AP info + */ +struct wmi_roam_scan_data { + bool present; + uint16_t type; + uint16_t num_ap; + uint16_t num_chan; + uint32_t next_rssi_threshold; + uint16_t chan_freq[MAX_ROAM_SCAN_CHAN]; + struct wmi_roam_candidate_info ap[MAX_ROAM_CANDIDATE_AP]; +}; + +/** + * struct wmi_roam_result - Roam result related info. + * @present: Flag to check if the roam result tlv is present + * @timestamp: Host timestamp in millisecs + * @status: 0 - Roaming is success ; 1 - Roaming failed + * @fail_reason: One of WMI_ROAM_FAIL_REASON_ID + */ +struct wmi_roam_result { + bool present; + uint32_t timestamp; + bool status; + uint32_t fail_reason; +}; + +/** + * struct wmi_neighbor_report_data - Neighbor report/BTM request related + * data. + * @present: Flag to check if the roam 11kv tlv is present + * @timestamp: Host timestamp in millisecs + * @req_type: 1 - BTM query ; 2 - 11K neighbor report request + * @req_time: Request timestamp in ms + * @resp_time: Response timestamp in ms + * @freq: Channel frequency in Mhz + */ +struct wmi_neighbor_report_data { + bool present; + uint32_t timestamp; + uint8_t req_type; + uint32_t req_time; + uint32_t resp_time; + uint8_t num_freq; + uint32_t freq[MAX_ROAM_SCAN_CHAN]; +}; + +/** + * struct wmi_roam_trigger_info() - Roam trigger related details + * @present: Flag to check if the roam_trigger_info tlv is present + * @trigger_reason: Roam trigger reason(enum WMI_ROAM_TRIGGER_REASON_ID) + * @trigger_sub_reason: Sub reason for roam trigger if multiple roam scans + * @current_rssi: Connected AP RSSI + * @timestamp: Host timestamp in millisecs when roam scan was triggered + * @btm_trig_data: BTM roam trigger parameters. + * @cu_trig_data: BSS Load roam trigger parameters. + * @rssi_trig_data: RSSI trigger related info. + * @deauth_trig_data: Deauth roam trigger related info + */ +struct wmi_roam_trigger_info { + bool present; + uint32_t trigger_reason; + uint32_t trigger_sub_reason; + uint32_t current_rssi; + uint32_t timestamp; + union { + struct wmi_roam_btm_trigger_data btm_trig_data; + struct wmi_roam_cu_trigger_data cu_trig_data; + struct wmi_roam_rssi_trigger_data rssi_trig_data; + struct wmi_roam_deauth_trigger_data deauth_trig_data; + }; +}; + /** * struct mws_coex_state - Modem Wireless Subsystem(MWS) coex info * @vdev_id : vdev id @@ -8798,41 +9243,6 @@ struct mws_antenna_sharing_info { uint32_t grant_duration; }; -/** - * enum roam_control_trigger_reason - Bitmap of roaming triggers - * - * @ROAM_TRIGGER_REASON_PER: Set if the roam has to be triggered based on - * a bad packet error rates (PER). - * @ROAM_TRIGGER_REASON_BEACON_MISS: Set if the roam has to be triggered - * based on beacon misses from the connected AP. - * @ROAM_TRIGGER_REASON_POOR_RSSI: Set if the roam has to be triggered - * due to poor RSSI of the connected AP. - * @ROAM_TRIGGER_REASON_BETTER_RSSI: Set if the roam has to be triggered - * upon finding a BSSID with a better RSSI than the connected BSSID. - * Here the RSSI of the current BSSID need not be poor. - * @ROAM_TRIGGER_REASON_PERIODIC: Set if the roam has to be triggered - * by triggering a periodic scan to find a better AP to roam. - * @ROAM_TRIGGER_REASON_DENSE: Set if the roam has to be triggered - * when the connected channel environment is too noisy/congested. - * @ROAM_TRIGGER_REASON_BTM: Set if the roam has to be triggered - * when BTM Request frame is received from the connected AP. - * @ROAM_TRIGGER_REASON_BSS_LOAD: Set if the roam has to be triggered - * when the channel utilization is goes above the configured threshold. - * - * Set the corresponding roam trigger reason bit to consider it for roam - * trigger. - */ -enum roam_control_trigger_reason { - ROAM_CONTROL_TRIGGER_REASON_PER = 1 << 0, - ROAM_CONTROL_TRIGGER_REASON_BEACON_MISS = 1 << 1, - ROAM_CONTROL_TRIGGER_REASON_POOR_RSSI = 1 << 2, - ROAM_CONTROL_TRIGGER_REASON_BETTER_RSSI = 1 << 3, - ROAM_CONTROL_TRIGGER_REASON_PERIODIC = 1 << 4, - ROAM_CONTROL_TRIGGER_REASON_DENSE = 1 << 5, - ROAM_CONTROL_TRIGGER_REASON_BTM = 1 << 6, - ROAM_CONTROL_TRIGGER_REASON_BSS_LOAD = 1 << 7, -}; - /** * struct roam_triggers - vendor configured roam triggers * @vdev_id: vdev id @@ -8843,4 +9253,17 @@ struct roam_triggers { uint32_t vdev_id; uint32_t trigger_bitmap; }; + +#ifdef FEATURE_ANI_LEVEL_REQUEST +/* Maximum number of freqs for which ANI level can be requested */ +#define MAX_NUM_FREQS_FOR_ANI_LEVEL 20 + +/* A valid ANI level lies between 0 to 9 */ +#define MAX_ANI_LEVEL 9 + +struct wmi_host_ani_level_event { + uint32_t chan_freq; + uint32_t ani_level; +}; +#endif /* FEATURE_ANI_LEVEL_REQUEST */ #endif /* _WMI_UNIFIED_PARAM_H_ */ diff --git a/drivers/staging/qca-wifi-host-cmn/wmi/inc/wmi_unified_priv.h b/drivers/staging/qca-wifi-host-cmn/wmi/inc/wmi_unified_priv.h index bed34ed05ca8..cd221926944e 100644 --- a/drivers/staging/qca-wifi-host-cmn/wmi/inc/wmi_unified_priv.h +++ b/drivers/staging/qca-wifi-host-cmn/wmi/inc/wmi_unified_priv.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -52,6 +52,10 @@ #include "wmi_unified_twt_param.h" #endif +#ifdef WLAN_FEATURE_PKT_CAPTURE +#include "wlan_pkt_capture_public_structs.h" +#endif + #define WMI_UNIFIED_MAX_EVENT 0x100 #ifdef WMI_INTERFACE_EVENT_LOGGING @@ -371,6 +375,9 @@ QDF_STATUS (*send_modem_power_state_cmd)(wmi_unified_t wmi_handle, QDF_STATUS (*send_set_sta_ps_mode_cmd)(wmi_unified_t wmi_handle, uint32_t vdev_id, uint8_t val); +QDF_STATUS (*send_idle_roam_monitor_cmd)(wmi_unified_t wmi_handle, + uint8_t val); + QDF_STATUS (*send_get_temperature_cmd)(wmi_unified_t wmi_handle); QDF_STATUS (*send_set_p2pgo_oppps_req_cmd)(wmi_unified_t wmi_handle, @@ -536,6 +543,11 @@ QDF_STATUS (*send_start_extscan_cmd)(wmi_unified_t wmi_handle, QDF_STATUS (*send_plm_stop_cmd)(wmi_unified_t wmi_handle, const struct plm_req_params *plm); +#ifdef WLAN_SEND_DSCP_UP_MAP_TO_FW +QDF_STATUS (*send_dscp_tid_map_cmd)(wmi_unified_t wmi_handle, + uint32_t *dscp_to_tid_map); +#endif + QDF_STATUS (*send_wlm_latency_level_cmd)(wmi_unified_t wmi_handle, struct wlm_latency_level_param *param); @@ -701,8 +713,13 @@ QDF_STATUS (*send_dbr_cfg_cmd)(wmi_unified_t wmi_handle, struct direct_buf_rx_cfg_req *cfg); QDF_STATUS (*send_start_oem_data_cmd)(wmi_unified_t wmi_handle, - uint32_t data_len, - uint8_t *data); + uint32_t data_len, + uint8_t *data); + +#ifdef FEATURE_OEM_DATA +QDF_STATUS (*send_start_oemv2_data_cmd)(wmi_unified_t wmi_handle, + struct oem_data *params); +#endif QDF_STATUS (*send_dfs_phyerr_filter_offload_en_cmd)(wmi_unified_t wmi_handle, @@ -821,10 +838,7 @@ QDF_STATUS (*send_roam_scan_offload_cmd)(wmi_unified_t wmi_handle, uint32_t command, uint32_t vdev_id); QDF_STATUS (*send_roam_scan_offload_scan_period_cmd)(wmi_unified_t wmi_handle, - uint32_t scan_period, - uint32_t scan_age, - uint32_t vdev_id, - uint32_t full_scan_period); + struct roam_scan_period_params *params); QDF_STATUS (*send_roam_scan_offload_chan_list_cmd)(wmi_unified_t wmi_handle, uint8_t chan_count, @@ -1613,6 +1627,8 @@ QDF_STATUS (*extract_ndp_initiator_rsp)(wmi_unified_t wmi_handle, uint8_t *data, struct nan_datapath_initiator_rsp *rsp); QDF_STATUS (*extract_ndp_ind)(wmi_unified_t wmi_handle, uint8_t *data, struct nan_datapath_indication_event *ind); +QDF_STATUS (*extract_nan_msg)(uint8_t *data, + struct nan_dump_msg *msg); QDF_STATUS (*extract_ndp_confirm)(wmi_unified_t wmi_handle, uint8_t *data, struct nan_datapath_confirm_event *ev); QDF_STATUS (*extract_ndp_responder_rsp)(wmi_unified_t wmi_handle, @@ -1628,8 +1644,17 @@ QDF_STATUS (*extract_ndp_sch_update)(wmi_unified_t wmi_handle, QDF_STATUS (*send_btm_config)(wmi_unified_t wmi_handle, struct wmi_btm_config *params); +QDF_STATUS (*send_roam_preauth_status)(wmi_unified_t wmi_handle, + struct wmi_roam_auth_status_params *params); + QDF_STATUS (*send_roam_bss_load_config)(wmi_unified_t wmi_handle, struct wmi_bss_load_config *params); +QDF_STATUS (*send_disconnect_roam_params)( + wmi_unified_t wmi_handle, + struct wmi_disconnect_roam_params *req); + +QDF_STATUS (*send_idle_roam_params)(wmi_unified_t wmi_handle, + struct wmi_idle_roam_params *req); QDF_STATUS (*send_obss_detection_cfg_cmd)(wmi_unified_t wmi_handle, struct wmi_obss_detection_cfg_param *obss_cfg_param); @@ -1661,6 +1686,30 @@ QDF_STATUS (*send_offload_11k_cmd)(wmi_unified_t wmi_handle, QDF_STATUS (*send_invoke_neighbor_report_cmd)(wmi_unified_t wmi_handle, struct wmi_invoke_neighbor_report_params *params); +QDF_STATUS +(*extract_roam_trigger_stats)(wmi_unified_t wmi_handle, + void *evt_buf, + struct wmi_roam_trigger_info *trig, + uint8_t idx); + +QDF_STATUS +(*extract_roam_scan_stats)(wmi_unified_t wmi_handle, + void *evt_buf, + struct wmi_roam_scan_data *dst, uint8_t idx, + uint8_t chan_idx, uint8_t ap_idx); + +QDF_STATUS +(*extract_roam_result_stats)(wmi_unified_t wmi_handle, + void *evt_buf, + struct wmi_roam_result *dst, + uint8_t idx); + +QDF_STATUS +(*extract_roam_11kv_stats)(wmi_unified_t wmi_handle, + void *evt_buf, + struct wmi_neighbor_report_data *dst, + uint8_t idx, uint8_t rpt_idx); + void (*wmi_pdev_id_conversion_enable)(wmi_unified_t wmi_handle); void (*send_time_stamp_sync_cmd)(wmi_unified_t wmi_handle); void (*wmi_free_allocated_event)(uint32_t cmd_event_id, @@ -1743,6 +1792,41 @@ QDF_STATUS (*send_mws_coex_status_req_cmd)(wmi_unified_t wmi_handle, QDF_STATUS (*send_set_roam_trigger_cmd)(wmi_unified_t wmi_handle, uint32_t vdev_id, uint32_t trigger_bitmap); +#ifdef FEATURE_ANI_LEVEL_REQUEST +QDF_STATUS (*send_ani_level_cmd)(wmi_unified_t wmi_handle, uint32_t *freqs, + uint8_t num_freqs); + +QDF_STATUS (*extract_ani_level)(uint8_t *evt_buf, + struct wmi_host_ani_level_event **info, + uint32_t *num_freqs); +#endif /* FEATURE_ANI_LEVEL_REQUEST */ + +#ifdef WLAN_FEATURE_PKT_CAPTURE +QDF_STATUS (*extract_vdev_mgmt_offload_event)( + void *handle, + void *event_buf, + struct mgmt_offload_event_params *params); +#endif /* WLAN_FEATURE_PKT_CAPTURE */ + +#ifdef FEATURE_WLAN_TIME_SYNC_FTM +QDF_STATUS (*send_wlan_time_sync_ftm_trigger_cmd)(wmi_unified_t wmi_handle, + uint32_t vdev_id, + bool burst_mode); + +QDF_STATUS (*send_wlan_ts_qtime_cmd)(wmi_unified_t wmi_handle, + uint32_t vdev_id, + uint64_t lpass_ts); + +QDF_STATUS (*extract_time_sync_ftm_start_stop_event)( + wmi_unified_t wmi_hdl, void *evt_buf, + struct ftm_time_sync_start_stop_params *param); + +QDF_STATUS (*extract_time_sync_ftm_offset_event)( + wmi_unified_t wmi_hdl, void *evt_buf, + struct ftm_time_sync_offset *param); +#endif /* FEATURE_WLAN_TIME_SYNC_FTM */ +QDF_STATUS (*send_roam_scan_get_ch_req)(wmi_unified_t wmi_hdl, + uint32_t vdev_id); }; /* Forward declartion for psoc*/ diff --git a/drivers/staging/qca-wifi-host-cmn/wmi/src/wmi_unified.c b/drivers/staging/qca-wifi-host-cmn/wmi/src/wmi_unified.c index 4ffee905bb3d..0cab7a64eef8 100644 --- a/drivers/staging/qca-wifi-host-cmn/wmi/src/wmi_unified.c +++ b/drivers/staging/qca-wifi-host-cmn/wmi/src/wmi_unified.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -1274,8 +1274,8 @@ int wmi_get_host_credits(wmi_unified_t wmi_handle); #ifdef NBUF_MEMORY_DEBUG wmi_buf_t -wmi_buf_alloc_debug(wmi_unified_t wmi_handle, uint16_t len, uint8_t *file_name, - uint32_t line_num) +wmi_buf_alloc_debug(wmi_unified_t wmi_handle, uint32_t len, uint8_t *file_name, + uint32_t line_num) { wmi_buf_t wmi_buf; @@ -1384,7 +1384,7 @@ static uint8_t *wmi_id_to_name(uint32_t wmi_command) #ifdef CONFIG_MCL static inline void wmi_log_cmd_id(uint32_t cmd_id, uint32_t tag) { - WMI_LOGD("Send WMI command:%s command_id:%d htc_tag:%d\n", + WMI_LOGD("Send WMI command:%s command_id:%d htc_tag:%d", wmi_id_to_name(cmd_id), cmd_id, tag); } diff --git a/drivers/staging/qca-wifi-host-cmn/wmi/src/wmi_unified_api.c b/drivers/staging/qca-wifi-host-cmn/wmi/src/wmi_unified_api.c index d3e26153beb9..9ee6ee038f72 100644 --- a/drivers/staging/qca-wifi-host-cmn/wmi/src/wmi_unified_api.c +++ b/drivers/staging/qca-wifi-host-cmn/wmi/src/wmi_unified_api.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -993,6 +993,16 @@ QDF_STATUS wmi_unified_set_sta_ps_mode(void *wmi_hdl, return QDF_STATUS_E_FAILURE; } +QDF_STATUS +wmi_unified_send_idle_trigger_monitor(wmi_unified_t wmi_handle, uint8_t val) +{ + if (wmi_handle->ops->send_idle_roam_monitor_cmd) + return wmi_handle->ops->send_idle_roam_monitor_cmd(wmi_handle, + val); + + return QDF_STATUS_E_FAILURE; +} + /** * wmi_set_mimops() - set MIMO powersave * @wmi_hdl: wmi handle @@ -2157,6 +2167,20 @@ QDF_STATUS wmi_unified_nat_keepalive_en_cmd(void *wmi_hdl, uint8_t vdev_id) return QDF_STATUS_E_FAILURE; } +#ifdef WLAN_SEND_DSCP_UP_MAP_TO_FW +QDF_STATUS +wmi_unified_send_dscp_tid_map_cmd(void *wmi_hdl, uint32_t *dscp_to_tid_map) +{ + wmi_unified_t wmi_handle = (wmi_unified_t) wmi_hdl; + + if (wmi_handle->ops->send_dscp_tid_map_cmd) + return wmi_handle->ops->send_dscp_tid_map_cmd(wmi_handle, + dscp_to_tid_map); + + return QDF_STATUS_E_FAILURE; +} +#endif /* WLAN_SEND_DSCP_UP_MAP_TO_FW */ + QDF_STATUS wmi_unified_wlm_latency_level_cmd(void *wmi_hdl, struct wlm_latency_level_param *param) { @@ -2193,7 +2217,7 @@ QDF_STATUS wmi_unified_oem_dma_ring_cfg(void *wmi_hdl, { wmi_unified_t wmi_handle = (wmi_unified_t) wmi_hdl; - if (wmi_handle->ops->send_start_oem_data_cmd) + if (wmi_handle->ops->send_oem_dma_cfg_cmd) return wmi_handle->ops->send_oem_dma_cfg_cmd(wmi_handle, cfg); return QDF_STATUS_E_FAILURE; @@ -2231,6 +2255,17 @@ QDF_STATUS wmi_unified_start_oem_data_cmd(void *wmi_hdl, return QDF_STATUS_E_FAILURE; } +#ifdef FEATURE_OEM_DATA +QDF_STATUS wmi_unified_start_oemv2_data_cmd(wmi_unified_t wmi_handle, + struct oem_data *params) +{ + if (wmi_handle->ops->send_start_oemv2_data_cmd) + return wmi_handle->ops->send_start_oemv2_data_cmd(wmi_handle, + params); + return QDF_STATUS_E_FAILURE; +} +#endif + /** * wmi_unified_dfs_phyerr_filter_offload_en_cmd() - enable dfs phyerr filter * @wmi_handle: wmi handle @@ -3044,31 +3079,25 @@ QDF_STATUS wmi_unified_send_roam_scan_offload_ap_cmd(void *wmi_hdl, return QDF_STATUS_E_FAILURE; } #endif + /** * wmi_unified_roam_scan_offload_scan_period() - set roam offload scan period * @wmi_handle: wmi handle - * @scan_period: scan period - * @scan_age: scan age - * @vdev_id: vdev id - * @full_scan_period: Full scan period is the idle period in seconds - * between two successive full channel roam scans. + * @param: pointer to roam scan period params to be sent to fw * * Send WMI_ROAM_SCAN_PERIOD parameters to fw. * * Return: QDF_STATUS_SUCCESS on success and QDF_STATUS_E_FAILURE for failure */ -QDF_STATUS wmi_unified_roam_scan_offload_scan_period(void *wmi_hdl, - uint32_t scan_period, - uint32_t scan_age, - uint32_t vdev_id, - uint32_t full_scan_period) +QDF_STATUS +wmi_unified_roam_scan_offload_scan_period(void *wmi_hdl, + struct roam_scan_period_params *param) { wmi_unified_t wmi_handle = (wmi_unified_t) wmi_hdl; if (wmi_handle->ops->send_roam_scan_offload_scan_period_cmd) - return wmi_handle->ops->send_roam_scan_offload_scan_period_cmd(wmi_handle, - scan_period, scan_age, vdev_id, - full_scan_period); + return wmi_handle->ops->send_roam_scan_offload_scan_period_cmd( + wmi_handle, param); return QDF_STATUS_E_FAILURE; } @@ -7278,6 +7307,16 @@ QDF_STATUS wmi_extract_ndp_initiator_rsp(wmi_unified_t wmi_handle, return QDF_STATUS_E_FAILURE; } +QDF_STATUS wmi_extract_nan_msg(wmi_unified_t wmi_handle, + uint8_t *data, + struct nan_dump_msg *msg) +{ + if (wmi_handle->ops->extract_nan_msg) + return wmi_handle->ops->extract_nan_msg(data, msg); + + return QDF_STATUS_E_FAILURE; +} + QDF_STATUS wmi_extract_ndp_ind(wmi_unified_t wmi_handle, uint8_t *data, struct nan_datapath_indication_event *ind) { @@ -7362,6 +7401,36 @@ QDF_STATUS wmi_unified_send_bss_load_config(void *wmi_hdl, return QDF_STATUS_E_FAILURE; } +QDF_STATUS +wmi_unified_send_disconnect_roam_params(wmi_unified_t wmi_handle, + struct wmi_disconnect_roam_params *req) +{ + if (wmi_handle->ops->send_disconnect_roam_params) + return wmi_handle->ops->send_disconnect_roam_params(wmi_handle, + req); + return QDF_STATUS_E_FAILURE; +} + +QDF_STATUS +wmi_unified_send_idle_roam_params(wmi_unified_t wmi_handle, + struct wmi_idle_roam_params *req) +{ + if (wmi_handle->ops->send_idle_roam_params) + return wmi_handle->ops->send_idle_roam_params(wmi_handle, + req); + return QDF_STATUS_E_FAILURE; +} + +QDF_STATUS +wmi_unified_send_roam_preauth_status(wmi_unified_t wmi_handle, + struct wmi_roam_auth_status_params *params) +{ + if (wmi_handle->ops->send_roam_preauth_status) + return wmi_handle->ops->send_roam_preauth_status(wmi_handle, + params); + return QDF_STATUS_E_FAILURE; +} + QDF_STATUS wmi_unified_send_obss_detection_cfg_cmd(void *wmi_hdl, struct wmi_obss_detection_cfg_param *obss_cfg_param) { @@ -7423,6 +7492,16 @@ QDF_STATUS wmi_unified_set_roam_triggers(wmi_unified_t wmi_handle, } #endif +QDF_STATUS wmi_unified_get_roam_scan_ch_list(wmi_unified_t wmi_handle, + uint8_t vdev_id) +{ + if (wmi_handle->ops->send_roam_scan_get_ch_req) + return wmi_handle->ops->send_roam_scan_get_ch_req(wmi_handle, + vdev_id); + + return QDF_STATUS_E_FAILURE; +} + #ifdef WLAN_SUPPORT_GREEN_AP QDF_STATUS wmi_extract_green_ap_egap_status_info( void *wmi_hdl, uint8_t *evt_buf, @@ -7565,3 +7644,138 @@ QDF_STATUS wmi_unified_send_mws_coex_req_cmd(struct wmi_unified *wmi_handle, return QDF_STATUS_E_FAILURE; } + +#ifdef FEATURE_ANI_LEVEL_REQUEST +QDF_STATUS wmi_unified_ani_level_cmd_send(wmi_unified_t wmi_handle, + uint32_t *freqs, + uint8_t num_freqs) +{ + if (wmi_handle->ops->send_ani_level_cmd) + return wmi_handle->ops->send_ani_level_cmd(wmi_handle, freqs, + num_freqs); + + return QDF_STATUS_E_FAILURE; +} + +QDF_STATUS wmi_unified_extract_ani_level(wmi_unified_t wmi_handle, + uint8_t *data, + struct wmi_host_ani_level_event **info, + uint32_t *num_channels) +{ + if (wmi_handle->ops->extract_ani_level) + return wmi_handle->ops->extract_ani_level(data, info, + num_channels); + + return QDF_STATUS_E_FAILURE; +} +#endif /* FEATURE_ANI_LEVEL_REQUEST */ + +#ifdef FEATURE_WLAN_TIME_SYNC_FTM +QDF_STATUS wmi_unified_send_wlan_time_sync_ftm_trigger(wmi_unified_t wmi_handle, + uint32_t vdev_id, + bool burst_mode) +{ + if (wmi_handle->ops->send_wlan_time_sync_ftm_trigger_cmd) + return wmi_handle->ops->send_wlan_time_sync_ftm_trigger_cmd + (wmi_handle, vdev_id, burst_mode); + + return QDF_STATUS_E_FAILURE; +} + +QDF_STATUS wmi_unified_send_wlan_time_sync_qtime(wmi_unified_t wmi_handle, + uint32_t vdev_id, + uint64_t lpass_ts) +{ + if (wmi_handle->ops->send_wlan_ts_qtime_cmd) + return wmi_handle->ops->send_wlan_ts_qtime_cmd(wmi_handle, + vdev_id, lpass_ts); + + return QDF_STATUS_E_FAILURE; +} + +QDF_STATUS wmi_unified_extract_time_sync_ftm_start_stop_params( + wmi_unified_t wmi_handle, void *evt_buf, + struct ftm_time_sync_start_stop_params *param) +{ + if (wmi_handle->ops->extract_time_sync_ftm_start_stop_event) + return + wmi_handle->ops->extract_time_sync_ftm_start_stop_event( + wmi_handle, evt_buf, param); + + return QDF_STATUS_E_FAILURE; +} + +QDF_STATUS wmi_unified_extract_time_sync_ftm_offset( + wmi_unified_t wmi_handle, void *evt_buf, + struct ftm_time_sync_offset *param) +{ + if (wmi_handle->ops->extract_time_sync_ftm_offset_event) + return + wmi_handle->ops->extract_time_sync_ftm_offset_event( + wmi_handle, evt_buf, param); + + return QDF_STATUS_E_FAILURE; +} +#endif /* FEATURE_WLAN_TIME_SYNC_FTM */ + +QDF_STATUS +wmi_unified_extract_roam_trigger_stats(wmi_unified_t wmi, + void *evt_buf, + struct wmi_roam_trigger_info *trig, + uint8_t idx) +{ + if (wmi->ops->extract_roam_trigger_stats) + return wmi->ops->extract_roam_trigger_stats(wmi, evt_buf, trig, + idx); + + return QDF_STATUS_E_FAILURE; +} + +QDF_STATUS +wmi_unified_extract_roam_scan_stats(wmi_unified_t wmi, void *evt_buf, + struct wmi_roam_scan_data *dst, uint8_t idx, + uint8_t chan_idx, uint8_t ap_idx) +{ + if (wmi->ops->extract_roam_scan_stats) + return wmi->ops->extract_roam_scan_stats(wmi, evt_buf, dst, + idx, chan_idx, ap_idx); + + return QDF_STATUS_E_FAILURE; +} + +#ifdef WLAN_FEATURE_PKT_CAPTURE +QDF_STATUS +wmi_unified_extract_vdev_mgmt_offload_event( + wmi_unified_t wmi, void *evt_buf, + struct mgmt_offload_event_params *params) +{ + if (wmi->ops->extract_vdev_mgmt_offload_event) + return wmi->ops->extract_vdev_mgmt_offload_event(wmi, evt_buf, + params); + + return QDF_STATUS_E_FAILURE; +} +#endif /* WLAN_FEATURE_PKT_CAPTURE */ + +QDF_STATUS +wmi_unified_extract_roam_result_stats(wmi_unified_t wmi, void *buf, + struct wmi_roam_result *dst, + uint8_t idx) +{ + if (wmi->ops->extract_roam_result_stats) + return wmi->ops->extract_roam_result_stats(wmi, buf, dst, idx); + + return QDF_STATUS_E_FAILURE; +} + +QDF_STATUS +wmi_unified_extract_roam_11kv_stats(wmi_unified_t wmi, void *evt_buf, + struct wmi_neighbor_report_data *dst, + uint8_t idx, uint8_t rpt_idx) +{ + if (wmi->ops->extract_roam_11kv_stats) + return wmi->ops->extract_roam_11kv_stats(wmi, evt_buf, dst, idx, + rpt_idx); + + return QDF_STATUS_E_FAILURE; +} diff --git a/drivers/staging/qca-wifi-host-cmn/wmi/src/wmi_unified_tlv.c b/drivers/staging/qca-wifi-host-cmn/wmi/src/wmi_unified_tlv.c index b2aec178e968..c2a17294d475 100644 --- a/drivers/staging/qca-wifi-host-cmn/wmi/src/wmi_unified_tlv.c +++ b/drivers/staging/qca-wifi-host-cmn/wmi/src/wmi_unified_tlv.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -2914,8 +2914,6 @@ static QDF_STATUS send_scan_start_cmd_tlv(wmi_unified_t wmi_handle, cmd->n_probes = params->n_probes; cmd->scan_ctrl_flags_ext = params->scan_ctrl_flags_ext; - WMI_LOGD("scan_ctrl_flags_ext = %x", cmd->scan_ctrl_flags_ext); - if (params->scan_random.randomize) wmi_copy_scan_random_mac(params->scan_random.mac_addr, params->scan_random.mac_mask, @@ -3112,9 +3110,10 @@ static QDF_STATUS send_scan_chan_list_cmd_tlv(wmi_unified_t wmi_handle, WMITLV_GET_STRUCT_TLVLEN (wmi_scan_chan_list_cmd_fixed_param)); - WMI_LOGD("no of channels = %d, len = %d", chan_list->num_scan_chans, len); - cmd->num_scan_chans = chan_list->num_scan_chans; + if (chan_list->max_bw_support_present) + cmd->flags |= CHANNEL_MAX_BANDWIDTH_VALID; + WMITLV_SET_HDR((buf_ptr + sizeof(wmi_scan_chan_list_cmd_fixed_param)), WMITLV_TAG_ARRAY_STRUC, sizeof(wmi_channel) * chan_list->num_scan_chans); @@ -3134,7 +3133,6 @@ static QDF_STATUS send_scan_chan_list_cmd_tlv(wmi_unified_t wmi_handle, chan_info->info = tchan_info->info; chan_info->reg_info_1 = tchan_info->reg_info_1; chan_info->reg_info_2 = tchan_info->reg_info_2; - WMI_LOGD("chan[%d] = %u", i, chan_info->mhz); /*TODO: Set WMI_SET_CHANNEL_MIN_POWER */ /*TODO: Set WMI_SET_CHANNEL_ANTENNA_MAX */ @@ -3565,7 +3563,43 @@ static QDF_STATUS send_set_sta_ps_mode_cmd_tlv(wmi_unified_t wmi_handle, wmi_buf_free(buf); return QDF_STATUS_E_FAILURE; } - return 0; + return QDF_STATUS_SUCCESS; +} + +/** + * send_idle_roam_monitor_cmd_tlv() - send idle monitor command to fw + * @wmi_handle: wmi handle + * @vdev_id: vdev id + * + * Return: QDF_STATUS_SUCCESS for success or error code. + */ +static QDF_STATUS send_idle_roam_monitor_cmd_tlv(wmi_unified_t wmi_handle, + uint8_t val) +{ + wmi_idle_trigger_monitor_cmd_fixed_param *cmd; + wmi_buf_t buf; + size_t len = sizeof(*cmd); + + buf = wmi_buf_alloc(wmi_handle, len); + if (!buf) + return QDF_STATUS_E_NOMEM; + + cmd = (wmi_idle_trigger_monitor_cmd_fixed_param *)wmi_buf_data(buf); + WMITLV_SET_HDR(&cmd->tlv_header, + WMITLV_TAG_STRUC_wmi_idle_trigger_monitor_cmd_fixed_param, + WMITLV_GET_STRUCT_TLVLEN(wmi_idle_trigger_monitor_cmd_fixed_param)); + + cmd->idle_trigger_monitor = (val ? WMI_IDLE_TRIGGER_MONITOR_ON : + WMI_IDLE_TRIGGER_MONITOR_OFF); + + WMI_LOGD("val:%d", cmd->idle_trigger_monitor); + + if (wmi_unified_cmd_send(wmi_handle, buf, len, + WMI_IDLE_TRIGGER_MONITOR_CMDID)) { + wmi_buf_free(buf); + return QDF_STATUS_E_FAILURE; + } + return QDF_STATUS_SUCCESS; } /** @@ -6411,6 +6445,32 @@ static inline uint8_t *wmi_add_fils_tlv(wmi_unified_t wmi_handle, return buf_ptr; } #endif + +#ifdef WLAN_FEATURE_ROAM_OFFLOAD + /** + * wmi_fill_sae_single_pmk_param() - Fill sae single pmk flag to indicate fw to + * use same PMKID for WPA3 SAE roaming. + * @params: roam request param + * @roam_offload_11i: pointer to 11i params + * + * Return: None + */ +static inline void +wmi_fill_sae_single_pmk_param(struct roam_offload_scan_params *params, + wmi_roam_11i_offload_tlv_param *roam_offload_11i) + { + if (params->is_sae_same_pmk) + roam_offload_11i->flags |= + 1 << WMI_ROAM_OFFLOAD_FLAG_SAE_SAME_PMKID; +} +#else +static inline void +wmi_fill_sae_single_pmk_param(struct roam_offload_scan_params *params, + wmi_roam_11i_offload_tlv_param *roam_offload_11i) +{ +} +#endif + /** * send_roam_scan_offload_mode_cmd_tlv() - send roam scan mode request to fw * @wmi_handle: wmi handle @@ -6452,7 +6512,7 @@ static QDF_STATUS send_roam_scan_offload_mode_cmd_tlv(wmi_unified_t wmi_handle, #endif /* WLAN_FEATURE_ROAM_OFFLOAD */ sizeof(wmi_start_scan_cmd_fixed_param); #ifdef WLAN_FEATURE_ROAM_OFFLOAD - WMI_LOGD("auth_mode = %d", auth_mode); + wmi_debug("auth_mode = %d", auth_mode); if (roam_req->is_roam_req_valid && roam_req->roam_offload_enabled) { len += sizeof(wmi_roam_offload_tlv_param); @@ -6494,8 +6554,6 @@ static QDF_STATUS send_roam_scan_offload_mode_cmd_tlv(wmi_unified_t wmi_handle, if (roam_req->is_roam_req_valid) WMI_LOGD("%s : roam offload = %d", __func__, roam_req->roam_offload_enabled); - else - WMI_LOGD("%s : roam_req is NULL", __func__); len += (4 * WMI_TLV_HDR_SIZE); } if (roam_req->is_roam_req_valid && @@ -6653,6 +6711,8 @@ static QDF_STATUS send_roam_scan_offload_mode_cmd_tlv(wmi_unified_t wmi_handle, roam_req->mdid.mdie_present; roam_offload_11r->mdid = roam_req->mdid.mobility_domain; + roam_offload_11r->adaptive_11r = + roam_req->is_adaptive_11r; if (auth_mode == WMI_AUTH_OPEN) { /* If FT-Open ensure pmk length and r0khid len are zero */ @@ -6682,8 +6742,7 @@ static QDF_STATUS send_roam_scan_offload_mode_cmd_tlv(wmi_unified_t wmi_handle, roam_offload_11i = (wmi_roam_11i_offload_tlv_param *) buf_ptr; - if (roam_req->roam_key_mgmt_offload_enabled && - roam_req->fw_okc) { + if (roam_req->fw_okc) { WMI_SET_ROAM_OFFLOAD_OKC_ENABLED (roam_offload_11i->flags); WMI_LOGI("LFR3:OKC enabled"); @@ -6692,8 +6751,7 @@ static QDF_STATUS send_roam_scan_offload_mode_cmd_tlv(wmi_unified_t wmi_handle, (roam_offload_11i->flags); WMI_LOGI("LFR3:OKC disabled"); } - if (roam_req->roam_key_mgmt_offload_enabled && - roam_req->fw_pmksa_cache) { + if (roam_req->fw_pmksa_cache) { WMI_SET_ROAM_OFFLOAD_PMK_CACHE_ENABLED (roam_offload_11i->flags); WMI_LOGI("LFR3:PMKSA caching enabled"); @@ -6703,10 +6761,18 @@ static QDF_STATUS send_roam_scan_offload_mode_cmd_tlv(wmi_unified_t wmi_handle, WMI_LOGI("LFR3:PMKSA caching disabled"); } + wmi_fill_sae_single_pmk_param(roam_req, + roam_offload_11i); + + roam_offload_11i->pmk_len = roam_req->pmk_len > + ROAM_OFFLOAD_PMK_BYTES ? + ROAM_OFFLOAD_PMK_BYTES : + roam_req->pmk_len; + qdf_mem_copy(roam_offload_11i->pmk, roam_req->psk_pmk, - sizeof(roam_req->psk_pmk)); - roam_offload_11i->pmk_len = roam_req->pmk_len; + roam_offload_11i->pmk_len); + WMITLV_SET_HDR(&roam_offload_11i->tlv_header, WMITLV_TAG_STRUC_wmi_roam_11i_offload_tlv_param, WMITLV_GET_STRUCT_TLVLEN @@ -8644,6 +8710,52 @@ static QDF_STATUS send_fw_profiling_cmd_tlv(wmi_unified_t wmi_handle, return 0; } +#ifdef WLAN_SEND_DSCP_UP_MAP_TO_FW +/** + * send_dscp_tid_map_cmd_tlv() - send dscp to tid map cmd to fw + * @wmi_handle: wmi handle + * @dscp_to_tid_map: array of dscp to tid map values + * + * Send WMI_PDEV_SET_DSCP_TID_MAP_CMDID to fw. + * + * Return: QDF_STATUS + */ +static QDF_STATUS +send_dscp_tid_map_cmd_tlv(wmi_unified_t wmi_handle, + uint32_t *dscp_to_tid_map) +{ + QDF_STATUS status; + wmi_pdev_set_dscp_tid_map_cmd_fixed_param *cmd; + wmi_buf_t buf; + uint16_t len = sizeof(*cmd); + + buf = wmi_buf_alloc(wmi_handle, len); + if (!buf) { + WMI_LOGE("%s: Failed to allocate wmi buffer", __func__); + return QDF_STATUS_E_NOMEM; + } + + cmd = (wmi_pdev_set_dscp_tid_map_cmd_fixed_param *)wmi_buf_data(buf); + WMITLV_SET_HDR( + &cmd->tlv_header, + WMITLV_TAG_STRUC_wmi_pdev_set_dscp_tid_map_cmd_fixed_param, + WMITLV_GET_STRUCT_TLVLEN + (wmi_pdev_set_dscp_tid_map_cmd_fixed_param)); + cmd->reserved0 = WMI_PDEV_ID_SOC; + qdf_mem_copy(&cmd->dscp_to_tid_map, dscp_to_tid_map, + sizeof(uint32_t) * WMI_DSCP_MAP_MAX); + + status = wmi_unified_cmd_send(wmi_handle, buf, len, + WMI_PDEV_SET_DSCP_TID_MAP_CMDID); + if (status) { + WMI_LOGE("Failed to send dscp_up_map_to_fw %d", status); + wmi_buf_free(buf); + } + + return status; +} +#endif /* WLAN_SEND_DSCP_UP_MAP_TO_FW */ + static QDF_STATUS send_wlm_latency_level_cmd_tlv(wmi_unified_t wmi_handle, struct wlm_latency_level_param *params) { @@ -8960,7 +9072,8 @@ static QDF_STATUS send_stop_11d_scan_cmd_tlv(wmi_unified_t wmi_handle, /** * send_start_oem_data_cmd_tlv() - start OEM data request to target * @wmi_handle: wmi handle - * @startOemDataReq: start request params + * @data_len: the length of @data + * @data: the pointer to data buf * * Return: CDF status */ @@ -9002,6 +9115,68 @@ static QDF_STATUS send_start_oem_data_cmd_tlv(wmi_unified_t wmi_handle, return ret; } +#ifdef FEATURE_OEM_DATA +/** + * send_start_oemv2_data_cmd_tlv() - start OEM data to target + * @wmi_handle: wmi handle + * @oem_data: the pointer to oem data + * + * Return: QDF status + */ +static QDF_STATUS send_start_oemv2_data_cmd_tlv(wmi_unified_t wmi_handle, + struct oem_data *oem_data) +{ + QDF_STATUS ret; + wmi_oem_data_cmd_fixed_param *cmd; + wmi_buf_t buf; + uint16_t len = sizeof(*cmd); + uint16_t oem_data_len_aligned; + uint8_t *buf_ptr; + + if (!oem_data || !oem_data->data) { + wmi_err_rl("oem data is not valid"); + return QDF_STATUS_E_FAILURE; + } + oem_data_len_aligned = roundup(oem_data->data_len, sizeof(uint32_t)); + if (oem_data_len_aligned < oem_data->data_len) { + wmi_err_rl("integer overflow while rounding up data_len"); + return QDF_STATUS_E_FAILURE; + } + + if (oem_data_len_aligned > WMI_SVC_MSG_MAX_SIZE - WMI_TLV_HDR_SIZE) { + wmi_err_rl("wmi_max_msg_size overflow for given data_len"); + return QDF_STATUS_E_FAILURE; + } + + len += WMI_TLV_HDR_SIZE + oem_data_len_aligned; + buf = wmi_buf_alloc(wmi_handle, len); + if (!buf) + return QDF_STATUS_E_NOMEM; + + buf_ptr = (uint8_t *)wmi_buf_data(buf); + cmd = (wmi_oem_data_cmd_fixed_param *)buf_ptr; + WMITLV_SET_HDR(&cmd->tlv_header, + WMITLV_TAG_STRUC_wmi_oem_data_cmd_fixed_param, + WMITLV_GET_STRUCT_TLVLEN(wmi_oem_data_cmd_fixed_param)); + + cmd->vdev_id = oem_data->vdev_id; + cmd->data_len = oem_data->data_len; + buf_ptr += sizeof(*cmd); + WMITLV_SET_HDR(buf_ptr, WMITLV_TAG_ARRAY_BYTE, oem_data_len_aligned); + buf_ptr += WMI_TLV_HDR_SIZE; + qdf_mem_copy(buf_ptr, oem_data->data, oem_data->data_len); + + wmi_mtrace(WMI_OEM_DATA_CMDID, NO_SESSION, 0); + ret = wmi_unified_cmd_send(wmi_handle, buf, len, WMI_OEM_DATA_CMDID); + if (QDF_IS_STATUS_ERROR(ret)) { + wmi_err_rl("Failed with ret = %d", ret); + wmi_buf_free(buf); + } + + return ret; +} +#endif + /** * send_dfs_phyerr_filter_offload_en_cmd_tlv() - enable dfs phyerr filter * @wmi_handle: wmi handle @@ -10214,6 +10389,11 @@ static QDF_STATUS send_regdomain_info_to_fw_cmd_tlv(wmi_unified_t wmi_handle, cmd->conformance_test_limit_2G = ctl2G; cmd->conformance_test_limit_5G = ctl5G; + wmi_debug("regd = %x, regd_2g = %x, regd_5g = %x, ctl_2g = %x, ctl_5g = %x", + cmd->reg_domain, cmd->reg_domain_2G, cmd->reg_domain_5G, + cmd->conformance_test_limit_2G, + cmd->conformance_test_limit_5G); + wmi_mtrace(WMI_PDEV_SET_REGDOMAIN_CMDID, NO_SESSION, 0); if (wmi_unified_cmd_send(wmi_handle, buf, len, WMI_PDEV_SET_REGDOMAIN_CMDID)) { @@ -10411,8 +10591,10 @@ static QDF_STATUS send_update_fw_tdls_state_cmd_tlv(wmi_unified_t wmi_handle, wmi_tdls->teardown_notification_ms; cmd->tdls_peer_kickout_threshold = wmi_tdls->tdls_peer_kickout_threshold; + cmd->tdls_discovery_wake_timeout = + wmi_tdls->tdls_discovery_wake_timeout; - WMI_LOGD("%s: tdls_state: %d, state: %d, " + wmi_debug("vdev %d tdls_state: %d, state: %d, " "notification_interval_ms: %d, " "tx_discovery_threshold: %d, " "tx_teardown_threshold: %d, " @@ -10425,8 +10607,9 @@ static QDF_STATUS send_update_fw_tdls_state_cmd_tlv(wmi_unified_t wmi_handle, "tdls_puapsd_inactivity_time: %d, " "tdls_puapsd_rx_frame_threshold: %d, " "teardown_notification_ms: %d, " - "tdls_peer_kickout_threshold: %d", - __func__, tdls_state, cmd->state, + "tdls_peer_kickout_threshold: %d, " + "tdls_discovery_wake_timeout: %d", + wmi_tdls->vdev_id, tdls_state, cmd->state, cmd->notification_interval_ms, cmd->tx_discovery_threshold, cmd->tx_teardown_threshold, @@ -10439,7 +10622,8 @@ static QDF_STATUS send_update_fw_tdls_state_cmd_tlv(wmi_unified_t wmi_handle, cmd->tdls_puapsd_inactivity_time_ms, cmd->tdls_puapsd_rx_frame_threshold, cmd->teardown_notification_ms, - cmd->tdls_peer_kickout_threshold); + cmd->tdls_peer_kickout_threshold, + cmd->tdls_discovery_wake_timeout); wmi_mtrace(WMI_TDLS_SET_STATE_CMDID, cmd->vdev_id, 0); if (wmi_unified_cmd_send(wmi_handle, wmi_buf, len, @@ -10448,7 +10632,6 @@ static QDF_STATUS send_update_fw_tdls_state_cmd_tlv(wmi_unified_t wmi_handle, wmi_buf_free(wmi_buf); return QDF_STATUS_E_FAILURE; } - WMI_LOGD("%s: vdev_id %d", __func__, wmi_tdls->vdev_id); return QDF_STATUS_SUCCESS; } @@ -13023,6 +13206,17 @@ void wmi_copy_resource_config(wmi_resource_config *resource_cfg, WMI_RSRC_CFG_FLAG_THREE_WAY_COEX_CONFIG_LEGACY_SUPPORT_SET( resource_cfg->flag1, 1); + if (tgt_res_cfg->pktcapture_support) + WMI_RSRC_CFG_FLAG_PACKET_CAPTURE_SUPPORT_SET( + resource_cfg->flag1, 1); + + if (tgt_res_cfg->time_sync_ftm) + WMI_RSRC_CFG_FLAG_AUDIO_SYNC_SUPPORT_SET(resource_cfg->flag1, + 1); + WMI_RSRC_CFG_HOST_SERVICE_FLAG_NAN_IFACE_SUPPORT_SET( + resource_cfg->host_service_flags, + tgt_res_cfg->nan_separate_iface_support); + wmi_copy_twt_resource_config(resource_cfg, tgt_res_cfg); } @@ -13565,17 +13759,13 @@ static QDF_STATUS send_pdev_set_pcl_cmd_tlv(wmi_unified_t wmi_handle, cmd->pdev_id = wmi_handle->ops->convert_pdev_id_host_to_target( WMI_HOST_PDEV_ID_SOC); cmd->num_chan = chan_len; - WMI_LOGD("%s: Total chan (PCL) len:%d", __func__, cmd->num_chan); - buf_ptr += sizeof(wmi_pdev_set_pcl_cmd_fixed_param); WMITLV_SET_HDR(buf_ptr, WMITLV_TAG_ARRAY_UINT32, (chan_len * sizeof(uint32_t))); cmd_args = (uint32_t *) (buf_ptr + WMI_TLV_HDR_SIZE); - for (i = 0; i < chan_len ; i++) { + for (i = 0; i < chan_len ; i++) cmd_args[i] = msg->weighed_valid_list[i]; - WMI_LOGD("%s: chan:%d weight:%d", __func__, - msg->saved_chan_list[i], cmd_args[i]); - } + wmi_mtrace(WMI_PDEV_SET_PCL_CMDID, NO_SESSION, 0); if (wmi_unified_cmd_send(wmi_handle, buf, len, WMI_PDEV_SET_PCL_CMDID)) { @@ -14749,8 +14939,8 @@ QDF_STATUS send_gtk_offload_cmd_tlv(wmi_unified_t wmi_handle, uint8_t vdev_id, cmd->flags = gtk_offload_opcode; /* Copy the keys and replay counter */ - qdf_mem_copy(cmd->KCK, params->kck, PMO_KCK_LEN); - qdf_mem_copy(cmd->KEK, params->kek, PMO_KEK_LEN_LEGACY); + qdf_mem_copy(cmd->KCK, params->kck, sizeof(cmd->KCK)); + qdf_mem_copy(cmd->KEK, params->kek, sizeof(cmd->KEK)); qdf_mem_copy(cmd->replay_counter, ¶ms->replay_counter, GTK_REPLAY_COUNTER_BYTES); } else { @@ -15602,7 +15792,6 @@ static QDF_STATUS send_roam_invoke_cmd_tlv(wmi_unified_t wmi_handle, cmd->flags |= (1 << WMI_ROAM_INVOKE_FLAG_REPORT_FAILURE); if (roaminvoke->is_same_bssid) cmd->flags |= (1 << WMI_ROAM_INVOKE_FLAG_NO_NULL_FRAME_TO_AP); - WMI_LOGD(FL("is_same_bssid flag: %d"), roaminvoke->is_same_bssid); if (roaminvoke->frame_len) { cmd->roam_scan_mode = WMI_ROAM_INVOKE_SCAN_MODE_SKIP; @@ -15648,15 +15837,11 @@ static QDF_STATUS send_roam_invoke_cmd_tlv(wmi_unified_t wmi_handle, roaminvoke->frame_buf, roaminvoke->frame_len); - WMI_LOGD(FL("bcn/prb_rsp frame, length: %d"), roaminvoke->frame_len); - QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_WMI, QDF_TRACE_LEVEL_DEBUG, - buf_ptr + WMI_TLV_HDR_SIZE, - roaminvoke->frame_len); - WMI_LOGD(FL("flag:%d, MODE scn:%d, ap:%d, dly:%d, n_ch:%d, n_bssid:%d"), + WMI_LOGD(FL("flag:%d, MODE scn:%d, ap:%d, dly:%d, n_ch:%d, n_bssid:%d is_same_bssid:%d BSSID: %pM, channel: %d"), cmd->flags, cmd->roam_scan_mode, - cmd->roam_ap_sel_mode, cmd->roam_delay, - cmd->num_chan, cmd->num_bssid); - WMI_LOGD(FL("BSSID: %pM, channel: %d"), roaminvoke->bssid, ch_hz); + cmd->roam_ap_sel_mode, cmd->roam_delay, cmd->num_chan, + cmd->num_bssid, roaminvoke->is_same_bssid, + roaminvoke->bssid, ch_hz); wmi_mtrace(WMI_ROAM_INVOKE_CMDID, cmd->vdev_id, 0); if (wmi_unified_cmd_send(wmi_handle, wmi_buf, len, @@ -15722,29 +15907,85 @@ static QDF_STATUS send_roam_scan_offload_cmd_tlv(wmi_unified_t wmi_handle, return status; } +/** + * convert_roam_trigger_reason() - Function to convert unified Roam trigger + * enum to TLV specific WMI_ROAM_TRIGGER_REASON_ID + * @reason: Roam trigger reason + * + * Return: WMI_ROAM_TRIGGER_REASON_ID + */ +static WMI_ROAM_TRIGGER_REASON_ID +convert_roam_trigger_reason(enum roam_trigger_reason trigger_reason) +{ + switch (trigger_reason) { + case ROAM_TRIGGER_REASON_NONE: + return WMI_ROAM_TRIGGER_REASON_NONE; + case ROAM_TRIGGER_REASON_PER: + return WMI_ROAM_TRIGGER_REASON_PER; + case ROAM_TRIGGER_REASON_BMISS: + return WMI_ROAM_TRIGGER_REASON_BMISS; + case ROAM_TRIGGER_REASON_LOW_RSSI: + return WMI_ROAM_TRIGGER_REASON_LOW_RSSI; + case ROAM_TRIGGER_REASON_HIGH_RSSI: + return WMI_ROAM_TRIGGER_REASON_HIGH_RSSI; + case ROAM_TRIGGER_REASON_PERIODIC: + return WMI_ROAM_TRIGGER_REASON_PERIODIC; + case ROAM_TRIGGER_REASON_MAWC: + return WMI_ROAM_TRIGGER_REASON_MAWC; + case ROAM_TRIGGER_REASON_DENSE: + return WMI_ROAM_TRIGGER_REASON_DENSE; + case ROAM_TRIGGER_REASON_BACKGROUND: + return WMI_ROAM_TRIGGER_REASON_BACKGROUND; + case ROAM_TRIGGER_REASON_FORCED: + return WMI_ROAM_TRIGGER_REASON_FORCED; + case ROAM_TRIGGER_REASON_BTM: + return WMI_ROAM_TRIGGER_REASON_BTM; + case ROAM_TRIGGER_REASON_UNIT_TEST: + return WMI_ROAM_TRIGGER_REASON_UNIT_TEST; + case ROAM_TRIGGER_REASON_BSS_LOAD: + return WMI_ROAM_TRIGGER_REASON_BSS_LOAD; + case ROAM_TRIGGER_REASON_DEAUTH: + return WMI_ROAM_TRIGGER_REASON_DEAUTH; + case ROAM_TRIGGER_REASON_IDLE: + return WMI_ROAM_TRIGGER_REASON_IDLE; + case ROAM_TRIGGER_REASON_MAX: + return WMI_ROAM_TRIGGER_REASON_MAX; + default: + return WMI_ROAM_TRIGGER_REASON_NONE; + } +} + /** * send_roam_scan_offload_ap_profile_cmd_tlv() - set roam ap profile in fw * @wmi_handle: wmi handle * @ap_profile_p: ap profile - * @vdev_id: vdev id * * Send WMI_ROAM_AP_PROFILE to firmware * - * Return: CDF status + * Return: QDF status */ -static QDF_STATUS send_roam_scan_offload_ap_profile_cmd_tlv(wmi_unified_t wmi_handle, - struct ap_profile_params *ap_profile) +static QDF_STATUS +send_roam_scan_offload_ap_profile_cmd_tlv(wmi_unified_t wmi_handle, + struct ap_profile_params *ap_profile) { wmi_buf_t buf = NULL; QDF_STATUS status; - int len; + size_t len; uint8_t *buf_ptr; wmi_roam_ap_profile_fixed_param *roam_ap_profile_fp; wmi_roam_cnd_scoring_param *score_param; wmi_ap_profile *profile; + wmi_roam_score_delta_param *score_delta_param; + wmi_roam_cnd_min_rssi_param *min_rssi_param; + enum roam_trigger_reason trig_reason; len = sizeof(wmi_roam_ap_profile_fixed_param) + sizeof(wmi_ap_profile); len += sizeof(*score_param); + len += WMI_TLV_HDR_SIZE; + len += NUM_OF_ROAM_TRIGGERS * sizeof(*score_delta_param); + len += WMI_TLV_HDR_SIZE; + len += NUM_OF_ROAM_TRIGGERS * sizeof(*min_rssi_param); + buf = wmi_buf_alloc(wmi_handle, len); if (!buf) { WMI_LOGE("%s : wmi_buf_alloc failed", __func__); @@ -15778,7 +16019,7 @@ static QDF_STATUS send_roam_scan_offload_ap_profile_cmd_tlv(wmi_unified_t wmi_ha ap_profile->profile.rsn_mcastmgmtcipherset; profile->rssi_abs_thresh = ap_profile->profile.rssi_abs_thresh; - WMI_LOGD("AP profile: flags %x rssi_threshold %d ssid:%.*s authmode %d uc cipher %d mc cipher %d mc mgmt cipher %d rssi abs thresh %d", + WMI_LOGD("AP PROFILE: flags %x rssi_threshold %d ssid:%.*s authmode %d uc cipher %d mc cipher %d mc mgmt cipher %d rssi abs thresh %d", profile->flags, profile->rssi_threshold, profile->ssid.ssid_len, ap_profile->profile.ssid.mac_ssid, profile->rsn_authmode, profile->rsn_ucastcipherset, @@ -15807,8 +16048,10 @@ static QDF_STATUS send_roam_scan_offload_ap_profile_cmd_tlv(wmi_unified_t wmi_ha score_param->pcl_weightage_pcnt = ap_profile->param.pcl_weightage; score_param->oce_wan_weightage_pcnt = ap_profile->param.oce_wan_weightage; + score_param->vendor_roam_score_algorithm_id = + ap_profile->param.vendor_roam_score_algorithm; - WMI_LOGD("Score params weightage: disable_bitmap %x rssi %d ht %d vht %d he %d BW %d band %d NSS %d ESP %d BF %d PCL %d OCE WAN %d", + WMI_LOGD("Score params weightage: disable_bitmap %x rssi %d ht %d vht %d he %d BW %d band %d NSS %d ESP %d BF %d PCL %d OCE WAN %d roam score algo %d", score_param->disable_bitmap, score_param->rssi_weightage_pcnt, score_param->ht_weightage_pcnt, score_param->vht_weightage_pcnt, @@ -15818,7 +16061,8 @@ static QDF_STATUS send_roam_scan_offload_ap_profile_cmd_tlv(wmi_unified_t wmi_ha score_param->esp_qbss_weightage_pcnt, score_param->beamforming_weightage_pcnt, score_param->pcl_weightage_pcnt, - score_param->oce_wan_weightage_pcnt); + score_param->oce_wan_weightage_pcnt, + score_param->vendor_roam_score_algorithm_id); score_param->bw_scoring.score_pcnt = ap_profile->param.bw_index_score; score_param->band_scoring.score_pcnt = @@ -15898,9 +16142,69 @@ static QDF_STATUS send_roam_scan_offload_ap_profile_cmd_tlv(wmi_unified_t wmi_ha score_param->roam_score_delta_pcnt = ap_profile->param.roam_score_delta; score_param->roam_score_delta_mask = ap_profile->param.roam_trigger_bitmap; - WMI_LOGD("Roam score delta:%d Roam_trigger_bitmap:%x", + score_param->candidate_min_roam_score_delta = + ap_profile->param.cand_min_roam_score_delta; + WMI_LOGD("Roam score delta:%d Roam_trigger_bitmap:%x cand min score delta = %d", score_param->roam_score_delta_pcnt, - score_param->roam_score_delta_mask); + score_param->roam_score_delta_mask, + score_param->candidate_min_roam_score_delta); + + buf_ptr += sizeof(*score_param); + WMITLV_SET_HDR(buf_ptr, WMITLV_TAG_ARRAY_STRUC, + (NUM_OF_ROAM_TRIGGERS * sizeof(*score_delta_param))); + buf_ptr += WMI_TLV_HDR_SIZE; + + score_delta_param = (wmi_roam_score_delta_param *)buf_ptr; + WMITLV_SET_HDR(&score_delta_param->tlv_header, + WMITLV_TAG_STRUC_wmi_roam_score_delta_param, + WMITLV_GET_STRUCT_TLVLEN(wmi_roam_score_delta_param)); + trig_reason = + ap_profile->score_delta_param[IDLE_ROAM_TRIGGER].trigger_reason; + score_delta_param->roam_trigger_reason = + convert_roam_trigger_reason(trig_reason); + score_delta_param->roam_score_delta = + ap_profile->score_delta_param[IDLE_ROAM_TRIGGER].roam_score_delta; + + buf_ptr += sizeof(*score_delta_param); + score_delta_param = (wmi_roam_score_delta_param *)buf_ptr; + WMITLV_SET_HDR(&score_delta_param->tlv_header, + WMITLV_TAG_STRUC_wmi_roam_score_delta_param, + WMITLV_GET_STRUCT_TLVLEN(wmi_roam_score_delta_param)); + trig_reason = + ap_profile->score_delta_param[BTM_ROAM_TRIGGER].trigger_reason; + score_delta_param->roam_trigger_reason = + convert_roam_trigger_reason(trig_reason); + score_delta_param->roam_score_delta = + ap_profile->score_delta_param[BTM_ROAM_TRIGGER].roam_score_delta; + + buf_ptr += sizeof(*score_delta_param); + WMITLV_SET_HDR(buf_ptr, WMITLV_TAG_ARRAY_STRUC, + (NUM_OF_ROAM_TRIGGERS * sizeof(*min_rssi_param))); + buf_ptr += WMI_TLV_HDR_SIZE; + + min_rssi_param = (wmi_roam_cnd_min_rssi_param *)buf_ptr; + WMITLV_SET_HDR(&min_rssi_param->tlv_header, + WMITLV_TAG_STRUC_wmi_roam_cnd_min_rssi_param, + WMITLV_GET_STRUCT_TLVLEN(wmi_roam_cnd_min_rssi_param)); + + trig_reason = + ap_profile->min_rssi_params[DEAUTH_MIN_RSSI].trigger_reason; + min_rssi_param->roam_trigger_reason = + convert_roam_trigger_reason(trig_reason); + min_rssi_param->candidate_min_rssi = + ap_profile->min_rssi_params[DEAUTH_MIN_RSSI].min_rssi; + + buf_ptr += sizeof(*min_rssi_param); + min_rssi_param = (wmi_roam_cnd_min_rssi_param *)buf_ptr; + WMITLV_SET_HDR(&min_rssi_param->tlv_header, + WMITLV_TAG_STRUC_wmi_roam_cnd_min_rssi_param, + WMITLV_GET_STRUCT_TLVLEN(wmi_roam_cnd_min_rssi_param)); + trig_reason = + ap_profile->min_rssi_params[BMISS_MIN_RSSI].trigger_reason; + min_rssi_param->roam_trigger_reason = + convert_roam_trigger_reason(trig_reason); + min_rssi_param->candidate_min_rssi = + ap_profile->min_rssi_params[BMISS_MIN_RSSI].min_rssi; wmi_mtrace(WMI_ROAM_AP_PROFILE, NO_SESSION, 0); status = wmi_unified_cmd_send(wmi_handle, buf, @@ -15911,29 +16215,22 @@ static QDF_STATUS send_roam_scan_offload_ap_profile_cmd_tlv(wmi_unified_t wmi_ha wmi_buf_free(buf); } - WMI_LOGD("WMI --> WMI_ROAM_AP_PROFILE and other parameters"); - return status; } /** * send_roam_scan_offload_scan_period_cmd_tlv() - set roam offload scan period * @wmi_handle: wmi handle - * @scan_period: scan period - * @scan_age: scan age - * @vdev_id: vdev id - * @full_scan_period: Full scan period is the idle period in seconds - * between two successive full channel roam scans. + * @param: roam scan parameters to be sent to firmware * * Send WMI_ROAM_SCAN_PERIOD parameters to fw. * * Return: CDF status */ -static QDF_STATUS send_roam_scan_offload_scan_period_cmd_tlv(wmi_unified_t wmi_handle, - uint32_t scan_period, - uint32_t scan_age, - uint32_t vdev_id, - uint32_t full_scan_period) +static QDF_STATUS +send_roam_scan_offload_scan_period_cmd_tlv( + wmi_unified_t wmi_handle, + struct roam_scan_period_params *param) { QDF_STATUS status; wmi_buf_t buf = NULL; @@ -15956,32 +16253,40 @@ static QDF_STATUS send_roam_scan_offload_scan_period_cmd_tlv(wmi_unified_t wmi_h WMITLV_GET_STRUCT_TLVLEN (wmi_roam_scan_period_fixed_param)); /* fill in scan period values */ - scan_period_fp->vdev_id = vdev_id; - scan_period_fp->roam_scan_period = scan_period; - scan_period_fp->roam_scan_age = scan_age; - + scan_period_fp->vdev_id = param->vdev_id; + scan_period_fp->roam_scan_period = param->scan_period; /* 20 seconds */ + scan_period_fp->roam_scan_age = param->scan_age; + + scan_period_fp->inactivity_time_period = + param->roam_scan_inactivity_time; + scan_period_fp->roam_inactive_count = + param->roam_inactive_data_packet_count; + scan_period_fp->roam_scan_period_after_inactivity = + param->roam_scan_period_after_inactivity; /* Firmware expects the full scan preriod in msec whereas host * provides the same in seconds. * Convert it to msec and send to firmware */ - scan_period_fp->roam_full_scan_period = full_scan_period * 1000; + scan_period_fp->roam_full_scan_period = param->full_scan_period * 1000; + + WMI_LOGD("%s: roam_scan_period=%d, roam_scan_age=%d full_scan_period= %u", + __func__, scan_period_fp->roam_scan_period, + scan_period_fp->roam_scan_age, + scan_period_fp->roam_full_scan_period); + WMI_LOGD("%s: inactiviy period:%d inactive count:%d period after inactivity:%d", + __func__, scan_period_fp->inactivity_time_period, + scan_period_fp->roam_inactive_count, + scan_period_fp->roam_scan_period_after_inactivity); wmi_mtrace(WMI_ROAM_SCAN_PERIOD, NO_SESSION, 0); status = wmi_unified_cmd_send(wmi_handle, buf, len, WMI_ROAM_SCAN_PERIOD); if (QDF_IS_STATUS_ERROR(status)) { - WMI_LOGE("wmi_unified_cmd_send WMI_ROAM_SCAN_PERIOD returned Error %d", - status); - goto error; + wmi_buf_free(buf); + return status; } - WMI_LOGI("%s: WMI --> WMI_ROAM_SCAN_PERIOD roam_scan_period=%d, roam_scan_age=%d, full_scan_period= %u", - __func__, scan_period, scan_age, full_scan_period); return QDF_STATUS_SUCCESS; -error: - wmi_buf_free(buf); - - return status; } /** @@ -16009,11 +16314,6 @@ static QDF_STATUS send_roam_scan_offload_chan_list_cmd_tlv(wmi_unified_t wmi_han wmi_roam_chan_list_fixed_param *chan_list_fp; uint32_t *roam_chan_list_array; - if (chan_count == 0) { - WMI_LOGD("%s : invalid number of channels %d", __func__, - chan_count); - return QDF_STATUS_E_EMPTY; - } /* Channel list is a table of 2 TLV's */ list_tlv_len = WMI_TLV_HDR_SIZE + chan_count * sizeof(uint32_t); len = sizeof(wmi_roam_chan_list_fixed_param) + list_tlv_len; @@ -16031,7 +16331,7 @@ static QDF_STATUS send_roam_scan_offload_chan_list_cmd_tlv(wmi_unified_t wmi_han (wmi_roam_chan_list_fixed_param)); chan_list_fp->vdev_id = vdev_id; chan_list_fp->num_chan = chan_count; - if (chan_count > 0 && list_type == WMI_CHANNEL_LIST_STATIC) { + if (list_type == WMI_CHANNEL_LIST_STATIC) { /* external app is controlling channel list */ chan_list_fp->chan_list_type = WMI_ROAM_SCAN_CHAN_LIST_TYPE_STATIC; @@ -16045,12 +16345,9 @@ static QDF_STATUS send_roam_scan_offload_chan_list_cmd_tlv(wmi_unified_t wmi_han WMITLV_SET_HDR(buf_ptr, WMITLV_TAG_ARRAY_UINT32, (chan_list_fp->num_chan * sizeof(uint32_t))); roam_chan_list_array = (uint32_t *) (buf_ptr + WMI_TLV_HDR_SIZE); - WMI_LOGD("%s: %d channels = ", __func__, chan_list_fp->num_chan); for (i = 0; ((i < chan_list_fp->num_chan) && - (i < WMI_ROAM_MAX_CHANNELS)); i++) { + (i < WMI_ROAM_MAX_CHANNELS)); i++) roam_chan_list_array[i] = chan_list[i]; - WMI_LOGD("%d,", roam_chan_list_array[i]); - } wmi_mtrace(WMI_ROAM_CHAN_LIST, NO_SESSION, 0); status = wmi_unified_cmd_send(wmi_handle, buf, @@ -16189,9 +16486,9 @@ static QDF_STATUS send_roam_scan_offload_rssi_change_cmd_tlv(wmi_unified_t wmi_h goto error; } - WMI_LOGD(FL("roam_scan_rssi_change_thresh=%d, bcn_rssi_weight=%d"), - rssi_change_thresh, bcn_rssi_weight); - WMI_LOGD(FL("hirssi_delay_btw_scans=%d"), hirssi_delay_btw_scans); + wmi_debug("roam_scan_rssi_change_thresh %d, bcn_rssi_weight %dhirssi_delay_btw_scans %d", + rssi_change_thresh, bcn_rssi_weight, hirssi_delay_btw_scans); + return QDF_STATUS_SUCCESS; error: wmi_buf_free(buf); @@ -17162,6 +17459,29 @@ static QDF_STATUS extract_ndp_initiator_rsp_tlv(wmi_unified_t wmi_handle, return QDF_STATUS_SUCCESS; } +#define MAX_NAN_MSG_LEN 200 + +static QDF_STATUS extract_nan_msg_tlv(uint8_t *data, + struct nan_dump_msg *msg) +{ + WMI_NAN_DMESG_EVENTID_param_tlvs *event; + wmi_nan_dmesg_event_fixed_param *fixed_params; + + event = (WMI_NAN_DMESG_EVENTID_param_tlvs *)data; + fixed_params = (wmi_nan_dmesg_event_fixed_param *)event->fixed_param; + if (!fixed_params->msg_len || + fixed_params->msg_len > MAX_NAN_MSG_LEN || + fixed_params->msg_len > event->num_msg) + return QDF_STATUS_E_FAILURE; + + msg->data_len = fixed_params->msg_len; + msg->msg = event->msg; + + msg->msg[fixed_params->msg_len - 1] = (uint8_t)'\0'; + + return QDF_STATUS_SUCCESS; +} + static QDF_STATUS extract_ndp_ind_tlv(wmi_unified_t wmi_handle, uint8_t *data, struct nan_datapath_indication_event *rsp) { @@ -18808,10 +19128,8 @@ static QDF_STATUS extract_swba_tim_info_tlv(wmi_unified_t wmi_handle, wmi_tim_info *tim_info_ev; param_buf = (WMI_HOST_SWBA_EVENTID_param_tlvs *) evt_buf; - if (!param_buf) { - WMI_LOGE("Invalid swba event buffer"); + if (!param_buf) return QDF_STATUS_E_INVAL; - } tim_info_ev = ¶m_buf->tim_info[idx]; @@ -21802,7 +22120,10 @@ static QDF_STATUS send_set_del_pmkid_cache_cmd_tlv(wmi_unified_t wmi_handle, wmi_pmk_cache *pmksa; uint32_t len = sizeof(*cmd); - if (pmk_info->pmk_len) + if (!pmk_info) + return QDF_STATUS_E_INVAL; + + if (!pmk_info->is_flush_all) len += WMI_TLV_HDR_SIZE + sizeof(*pmksa); buf = wmi_buf_alloc(wmi_handle, len); @@ -21822,8 +22143,8 @@ static QDF_STATUS send_set_del_pmkid_cache_cmd_tlv(wmi_unified_t wmi_handle, cmd->vdev_id = pmk_info->session_id; - /* If pmk_info->pmk_len is 0, this is a flush request */ - if (!pmk_info->pmk_len) { + /* If pmk_info->is_flush_all is true, this is a flush request */ + if (pmk_info->is_flush_all) { cmd->op_flag = WMI_PMK_CACHE_OP_FLAG_FLUSH_ALL; cmd->num_cache = 0; goto send_cmd; @@ -21966,7 +22287,9 @@ static QDF_STATUS send_btm_config_cmd_tlv(wmi_unified_t wmi_handle, cmd->max_attempt_cnt = params->btm_max_attempt_cnt; cmd->solicited_timeout_ms = params->btm_solicited_timeout; cmd->stick_time_seconds = params->btm_sticky_time; + cmd->btm_bitmap = params->btm_query_bitmask; cmd->disassoc_timer_threshold = params->disassoc_timer_threshold; + cmd->btm_candidate_min_score = params->btm_candidate_min_score; wmi_mtrace(WMI_ROAM_BTM_CONFIG_CMDID, cmd->vdev_id, 0); if (wmi_unified_cmd_send(wmi_handle, buf, len, @@ -22012,6 +22335,13 @@ send_roam_bss_load_config_tlv(wmi_unified_t wmi_handle, cmd->vdev_id = params->vdev_id; cmd->bss_load_threshold = params->bss_load_threshold; cmd->monitor_time_window = params->bss_load_sample_time; + cmd->rssi_2g_threshold = params->rssi_threshold_24ghz; + cmd->rssi_5g_threshold = params->rssi_threshold_5ghz; + + WMI_LOGD("%s: vdev:%d bss_load_thres:%d monitor_time:%d rssi_2g:%d rssi_5g:%d", + __func__, cmd->vdev_id, cmd->bss_load_threshold, + cmd->monitor_time_window, cmd->rssi_2g_threshold, + cmd->rssi_5g_threshold); wmi_mtrace(WMI_ROAM_BSS_LOAD_CONFIG_CMDID, cmd->vdev_id, 0); if (wmi_unified_cmd_send(wmi_handle, buf, len, @@ -22025,49 +22355,46 @@ send_roam_bss_load_config_tlv(wmi_unified_t wmi_handle, return QDF_STATUS_SUCCESS; } +#ifdef WLAN_FEATURE_ROAM_OFFLOAD /** - * send_obss_detection_cfg_cmd_tlv() - send obss detection - * configurations to firmware. + * send_disconnect_roam_params_tlv() - send disconnect roam trigger parameters * @wmi_handle: wmi handle - * @obss_cfg_param: obss detection configurations + * @disconnect_roam: pointer to wmi_disconnect_roam_params which carries the + * disconnect_roam_trigger parameters from CSR * - * Send WMI_SAP_OBSS_DETECTION_CFG_CMDID parameters to fw. + * This function sends the disconnect roam trigger parameters to fw. * - * Return: QDF_STATUS + * Return: QDF status */ -static QDF_STATUS send_obss_detection_cfg_cmd_tlv(wmi_unified_t wmi_handle, - struct wmi_obss_detection_cfg_param *obss_cfg_param) +static QDF_STATUS +send_disconnect_roam_params_tlv(wmi_unified_t wmi_handle, + struct wmi_disconnect_roam_params *req) { + wmi_roam_deauth_config_cmd_fixed_param *cmd; wmi_buf_t buf; - wmi_sap_obss_detection_cfg_cmd_fixed_param *cmd; - uint8_t len = sizeof(wmi_sap_obss_detection_cfg_cmd_fixed_param); + uint32_t len; + len = sizeof(*cmd); buf = wmi_buf_alloc(wmi_handle, len); - if (!buf) { - WMI_LOGE("%s: Failed to allocate wmi buffer", __func__); + if (!buf) return QDF_STATUS_E_NOMEM; - } - cmd = (wmi_sap_obss_detection_cfg_cmd_fixed_param *)wmi_buf_data(buf); - WMITLV_SET_HDR(&cmd->tlv_header, - WMITLV_TAG_STRUC_wmi_sap_obss_detection_cfg_cmd_fixed_param, - WMITLV_GET_STRUCT_TLVLEN - (wmi_sap_obss_detection_cfg_cmd_fixed_param)); + cmd = (wmi_roam_deauth_config_cmd_fixed_param *)wmi_buf_data(buf); + WMITLV_SET_HDR( + &cmd->tlv_header, + WMITLV_TAG_STRUC_wmi_roam_deauth_config_cmd_fixed_param, + WMITLV_GET_STRUCT_TLVLEN(wmi_roam_deauth_config_cmd_fixed_param)); - cmd->vdev_id = obss_cfg_param->vdev_id; - cmd->detect_period_ms = obss_cfg_param->obss_detect_period_ms; - cmd->b_ap_detect_mode = obss_cfg_param->obss_11b_ap_detect_mode; - cmd->b_sta_detect_mode = obss_cfg_param->obss_11b_sta_detect_mode; - cmd->g_ap_detect_mode = obss_cfg_param->obss_11g_ap_detect_mode; - cmd->a_detect_mode = obss_cfg_param->obss_11a_detect_mode; - cmd->ht_legacy_detect_mode = obss_cfg_param->obss_ht_legacy_detect_mode; - cmd->ht_mixed_detect_mode = obss_cfg_param->obss_ht_mixed_detect_mode; - cmd->ht_20mhz_detect_mode = obss_cfg_param->obss_ht_20mhz_detect_mode; + cmd->vdev_id = req->vdev_id; + cmd->enable = req->enable; + WMI_LOGD("%s: Send WMI_ROAM_DEAUTH_CONFIG vdev_id:%d enable:%d", + __func__, cmd->vdev_id, cmd->enable); - wmi_mtrace(WMI_SAP_OBSS_DETECTION_CFG_CMDID, cmd->vdev_id, 0); + wmi_mtrace(WMI_ROAM_DEAUTH_CONFIG_CMDID, cmd->vdev_id, 0); if (wmi_unified_cmd_send(wmi_handle, buf, len, - WMI_SAP_OBSS_DETECTION_CFG_CMDID)) { - WMI_LOGE("Failed to send WMI_SAP_OBSS_DETECTION_CFG_CMDID"); + WMI_ROAM_DEAUTH_CONFIG_CMDID)) { + WMI_LOGE("%s: failed to send WMI_ROAM_DEAUTH_CONFIG_CMDID", + __func__); wmi_buf_free(buf); return QDF_STATUS_E_FAILURE; } @@ -22076,40 +22403,219 @@ static QDF_STATUS send_obss_detection_cfg_cmd_tlv(wmi_unified_t wmi_handle, } /** - * extract_obss_detection_info_tlv() - Extract obss detection info - * received from firmware. - * @evt_buf: pointer to event buffer - * @obss_detection: Pointer to hold obss detection info + * send_idle_roam_params_tlv() - send idle roam trigger parameters + * @wmi_handle: wmi handle + * @idle_roam_params: pointer to wmi_idle_roam_params which carries the + * idle roam parameters from CSR * - * Return: QDF_STATUS + * This function sends the idle roam trigger parameters to fw. + * + * Return: QDF status */ -static QDF_STATUS extract_obss_detection_info_tlv(uint8_t *evt_buf, - struct wmi_obss_detect_info - *obss_detection) +static QDF_STATUS +send_idle_roam_params_tlv(wmi_unified_t wmi_handle, + struct wmi_idle_roam_params *idle_roam_params) { - WMI_SAP_OBSS_DETECTION_REPORT_EVENTID_param_tlvs *param_buf; - wmi_sap_obss_detection_info_evt_fixed_param *fix_param; + wmi_roam_idle_config_cmd_fixed_param *cmd; + wmi_buf_t buf; + uint32_t len; - if (!obss_detection) { - WMI_LOGE("%s: Invalid obss_detection event buffer", __func__); - return QDF_STATUS_E_INVAL; - } + len = sizeof(*cmd); + buf = wmi_buf_alloc(wmi_handle, len); + if (!buf) + return QDF_STATUS_E_NOMEM; - param_buf = (WMI_SAP_OBSS_DETECTION_REPORT_EVENTID_param_tlvs *)evt_buf; - if (!param_buf) { - WMI_LOGE("%s: Invalid evt_buf", __func__); - return QDF_STATUS_E_INVAL; + cmd = (wmi_roam_idle_config_cmd_fixed_param *)wmi_buf_data(buf); + WMITLV_SET_HDR( + &cmd->tlv_header, + WMITLV_TAG_STRUC_wmi_roam_idle_config_cmd_fixed_param, + WMITLV_GET_STRUCT_TLVLEN(wmi_roam_idle_config_cmd_fixed_param)); + + cmd->vdev_id = idle_roam_params->vdev_id; + cmd->enable = idle_roam_params->enable; + cmd->band = idle_roam_params->band; + cmd->rssi_delta = idle_roam_params->conn_ap_rssi_delta; + cmd->min_rssi = idle_roam_params->conn_ap_min_rssi; + cmd->idle_time = idle_roam_params->inactive_time; + cmd->data_packet_count = idle_roam_params->data_pkt_count; + WMI_LOGD("%s: Send WMI_ROAM_IDLE_CONFIG_CMDID vdev_id:%d enable:%d", + __func__, cmd->vdev_id, cmd->enable); + WMI_LOGD("%s: band:%d rssi_delta:%d min_rssi:%d idle_time:%d data_pkt:%d", + __func__, cmd->band, cmd->rssi_delta, cmd->min_rssi, + cmd->idle_time, cmd->data_packet_count); + wmi_mtrace(WMI_ROAM_IDLE_CONFIG_CMDID, cmd->vdev_id, 0); + if (wmi_unified_cmd_send(wmi_handle, buf, len, + WMI_ROAM_IDLE_CONFIG_CMDID)) { + WMI_LOGE("%s: failed to send WMI_ROAM_IDLE_CONFIG_CMDID", + __func__); + wmi_buf_free(buf); + return QDF_STATUS_E_FAILURE; } - fix_param = param_buf->fixed_param; - obss_detection->vdev_id = fix_param->vdev_id; - obss_detection->matched_detection_masks = - fix_param->matched_detection_masks; - WMI_MAC_ADDR_TO_CHAR_ARRAY(&fix_param->matched_bssid_addr, - &obss_detection->matched_bssid_addr[0]); - switch (fix_param->reason) { - case WMI_SAP_OBSS_DETECTION_EVENT_REASON_NOT_SUPPORT: - obss_detection->reason = OBSS_OFFLOAD_DETECTION_DISABLED; + return QDF_STATUS_SUCCESS; +} + +/** + * send_roam_preauth_status_tlv() - send roam pre-authentication status + * @wmi_handle: wmi handle + * @params: pre-auth status params + * + * This function sends the roam pre-authentication status for WPA3 SAE + * pre-auth to target. + * + * Return: QDF status + */ +static QDF_STATUS +send_roam_preauth_status_tlv(wmi_unified_t wmi_handle, + struct wmi_roam_auth_status_params *params) +{ + wmi_roam_preauth_status_cmd_fixed_param *cmd; + wmi_buf_t buf; + uint32_t len; + uint8_t *buf_ptr; + + len = sizeof(*cmd) + WMI_TLV_HDR_SIZE + PMKID_LEN; + buf = wmi_buf_alloc(wmi_handle, len); + if (!buf) + return QDF_STATUS_E_NOMEM; + + buf_ptr = (uint8_t *)wmi_buf_data(buf); + cmd = (wmi_roam_preauth_status_cmd_fixed_param *)buf_ptr; + WMITLV_SET_HDR( + &cmd->tlv_header, + WMITLV_TAG_STRUC_wmi_roam_preauth_status_cmd_fixed_param, + WMITLV_GET_STRUCT_TLVLEN(wmi_roam_preauth_status_cmd_fixed_param)); + + cmd->vdev_id = params->vdev_id; + cmd->preauth_status = params->preauth_status; + WMI_CHAR_ARRAY_TO_MAC_ADDR(params->bssid.bytes, + &cmd->candidate_ap_bssid); + + buf_ptr += sizeof(wmi_roam_preauth_status_cmd_fixed_param); + WMITLV_SET_HDR(buf_ptr, WMITLV_TAG_ARRAY_BYTE, PMKID_LEN); + buf_ptr += WMI_TLV_HDR_SIZE; + + qdf_mem_copy(buf_ptr, params->pmkid, PMKID_LEN); + WMI_LOGD("%s: vdev_id:%d status:%d bssid:%pM", __func__, cmd->vdev_id, + cmd->preauth_status, params->bssid.bytes); + + wmi_mtrace(WMI_ROAM_PREAUTH_STATUS_CMDID, cmd->vdev_id, 0); + if (wmi_unified_cmd_send(wmi_handle, buf, len, + WMI_ROAM_PREAUTH_STATUS_CMDID)) { + wmi_buf_free(buf); + return QDF_STATUS_E_FAILURE; + } + + return QDF_STATUS_SUCCESS; +} +#else +static inline QDF_STATUS +send_disconnect_roam_params_tlv(wmi_unified_t wmi_handle, + struct wmi_disconnect_roam_params *req) +{ + return QDF_STATUS_E_FAILURE; +} + +static inline QDF_STATUS +send_idle_roam_params_tlv(wmi_unified_t wmi_handle, + struct wmi_idle_roam_params *idle_roam_params) +{ + return QDF_STATUS_E_FAILURE; +} + +static inline QDF_STATUS +send_roam_preauth_status_tlv(wmi_unified_t wmi_handle, + struct wmi_roam_auth_status_params *params) +{ + return QDF_STATUS_E_FAILURE; +} +#endif + +/** + * send_obss_detection_cfg_cmd_tlv() - send obss detection + * configurations to firmware. + * @wmi_handle: wmi handle + * @obss_cfg_param: obss detection configurations + * + * Send WMI_SAP_OBSS_DETECTION_CFG_CMDID parameters to fw. + * + * Return: QDF_STATUS + */ +static QDF_STATUS send_obss_detection_cfg_cmd_tlv(wmi_unified_t wmi_handle, + struct wmi_obss_detection_cfg_param *obss_cfg_param) +{ + wmi_buf_t buf; + wmi_sap_obss_detection_cfg_cmd_fixed_param *cmd; + uint8_t len = sizeof(wmi_sap_obss_detection_cfg_cmd_fixed_param); + + buf = wmi_buf_alloc(wmi_handle, len); + if (!buf) { + WMI_LOGE("%s: Failed to allocate wmi buffer", __func__); + return QDF_STATUS_E_NOMEM; + } + + cmd = (wmi_sap_obss_detection_cfg_cmd_fixed_param *)wmi_buf_data(buf); + WMITLV_SET_HDR(&cmd->tlv_header, + WMITLV_TAG_STRUC_wmi_sap_obss_detection_cfg_cmd_fixed_param, + WMITLV_GET_STRUCT_TLVLEN + (wmi_sap_obss_detection_cfg_cmd_fixed_param)); + + cmd->vdev_id = obss_cfg_param->vdev_id; + cmd->detect_period_ms = obss_cfg_param->obss_detect_period_ms; + cmd->b_ap_detect_mode = obss_cfg_param->obss_11b_ap_detect_mode; + cmd->b_sta_detect_mode = obss_cfg_param->obss_11b_sta_detect_mode; + cmd->g_ap_detect_mode = obss_cfg_param->obss_11g_ap_detect_mode; + cmd->a_detect_mode = obss_cfg_param->obss_11a_detect_mode; + cmd->ht_legacy_detect_mode = obss_cfg_param->obss_ht_legacy_detect_mode; + cmd->ht_mixed_detect_mode = obss_cfg_param->obss_ht_mixed_detect_mode; + cmd->ht_20mhz_detect_mode = obss_cfg_param->obss_ht_20mhz_detect_mode; + + wmi_mtrace(WMI_SAP_OBSS_DETECTION_CFG_CMDID, cmd->vdev_id, 0); + if (wmi_unified_cmd_send(wmi_handle, buf, len, + WMI_SAP_OBSS_DETECTION_CFG_CMDID)) { + WMI_LOGE("Failed to send WMI_SAP_OBSS_DETECTION_CFG_CMDID"); + wmi_buf_free(buf); + return QDF_STATUS_E_FAILURE; + } + + return QDF_STATUS_SUCCESS; +} + +/** + * extract_obss_detection_info_tlv() - Extract obss detection info + * received from firmware. + * @evt_buf: pointer to event buffer + * @obss_detection: Pointer to hold obss detection info + * + * Return: QDF_STATUS + */ +static QDF_STATUS extract_obss_detection_info_tlv(uint8_t *evt_buf, + struct wmi_obss_detect_info + *obss_detection) +{ + WMI_SAP_OBSS_DETECTION_REPORT_EVENTID_param_tlvs *param_buf; + wmi_sap_obss_detection_info_evt_fixed_param *fix_param; + + if (!obss_detection) { + WMI_LOGE("%s: Invalid obss_detection event buffer", __func__); + return QDF_STATUS_E_INVAL; + } + + param_buf = (WMI_SAP_OBSS_DETECTION_REPORT_EVENTID_param_tlvs *)evt_buf; + if (!param_buf) { + WMI_LOGE("%s: Invalid evt_buf", __func__); + return QDF_STATUS_E_INVAL; + } + + fix_param = param_buf->fixed_param; + obss_detection->vdev_id = fix_param->vdev_id; + obss_detection->matched_detection_masks = + fix_param->matched_detection_masks; + WMI_MAC_ADDR_TO_CHAR_ARRAY(&fix_param->matched_bssid_addr, + &obss_detection->matched_bssid_addr[0]); + switch (fix_param->reason) { + case WMI_SAP_OBSS_DETECTION_EVENT_REASON_NOT_SUPPORT: + obss_detection->reason = OBSS_OFFLOAD_DETECTION_DISABLED; break; case WMI_SAP_OBSS_DETECTION_EVENT_REASON_PRESENT_NOTIFY: obss_detection->reason = OBSS_OFFLOAD_DETECTION_PRESENT; @@ -22401,34 +22907,58 @@ convert_control_roam_trigger_reason_bitmap(uint32_t trigger_reason_bitmap) /* Enable the complete trigger bitmap when all bits are set in * the control config bitmap */ - all_bitmap = (ROAM_CONTROL_TRIGGER_REASON_BSS_LOAD << 1) - 1; + all_bitmap = BIT(ROAM_TRIGGER_REASON_MAX) - 1; if (trigger_reason_bitmap == all_bitmap) - return (BIT(WMI_ROAM_TRIGGER_REASON_MAX) - 1); + return BIT(WMI_ROAM_TRIGGER_EXT_REASON_MAX) - 1; + + if (trigger_reason_bitmap & BIT(ROAM_TRIGGER_REASON_NONE)) + fw_trigger_bitmap |= BIT(WMI_ROAM_TRIGGER_REASON_NONE); - if (trigger_reason_bitmap & ROAM_CONTROL_TRIGGER_REASON_PER) + if (trigger_reason_bitmap & BIT(ROAM_TRIGGER_REASON_PER)) fw_trigger_bitmap |= BIT(WMI_ROAM_TRIGGER_REASON_PER); - if (trigger_reason_bitmap & ROAM_CONTROL_TRIGGER_REASON_BEACON_MISS) - fw_trigger_bitmap |= BIT(WMI_ROAM_TRIGGER_REASON_BMISS); + if (trigger_reason_bitmap & BIT(ROAM_TRIGGER_REASON_BMISS)) + fw_trigger_bitmap |= BIT(WMI_ROAM_TRIGGER_REASON_BMISS); + + if (trigger_reason_bitmap & BIT(ROAM_TRIGGER_REASON_LOW_RSSI)) + fw_trigger_bitmap |= BIT(WMI_ROAM_TRIGGER_REASON_LOW_RSSI); - if (trigger_reason_bitmap & ROAM_CONTROL_TRIGGER_REASON_POOR_RSSI) - fw_trigger_bitmap |= BIT(WMI_ROAM_TRIGGER_REASON_LOW_RSSI); + if (trigger_reason_bitmap & BIT(ROAM_TRIGGER_REASON_HIGH_RSSI)) + fw_trigger_bitmap |= BIT(WMI_ROAM_TRIGGER_REASON_HIGH_RSSI); - if (trigger_reason_bitmap & ROAM_CONTROL_TRIGGER_REASON_BETTER_RSSI) - fw_trigger_bitmap |= BIT(WMI_ROAM_TRIGGER_REASON_HIGH_RSSI); + if (trigger_reason_bitmap & BIT(ROAM_TRIGGER_REASON_PERIODIC)) + fw_trigger_bitmap |= BIT(WMI_ROAM_TRIGGER_REASON_PERIODIC); - if (trigger_reason_bitmap & ROAM_CONTROL_TRIGGER_REASON_PERIODIC) - fw_trigger_bitmap |= BIT(WMI_ROAM_TRIGGER_REASON_PERIODIC); + if (trigger_reason_bitmap & BIT(ROAM_TRIGGER_REASON_MAWC)) + fw_trigger_bitmap |= BIT(WMI_ROAM_TRIGGER_REASON_MAWC); - if (trigger_reason_bitmap & ROAM_CONTROL_TRIGGER_REASON_DENSE) - fw_trigger_bitmap |= BIT(WMI_ROAM_TRIGGER_REASON_DENSE); + if (trigger_reason_bitmap & BIT(ROAM_TRIGGER_REASON_DENSE)) + fw_trigger_bitmap |= BIT(WMI_ROAM_TRIGGER_REASON_DENSE); - if (trigger_reason_bitmap & ROAM_CONTROL_TRIGGER_REASON_BTM) + if (trigger_reason_bitmap & BIT(ROAM_TRIGGER_REASON_BACKGROUND)) + fw_trigger_bitmap |= BIT(WMI_ROAM_TRIGGER_REASON_BACKGROUND); + + if (trigger_reason_bitmap & BIT(ROAM_TRIGGER_REASON_FORCED)) + fw_trigger_bitmap |= BIT(WMI_ROAM_TRIGGER_REASON_FORCED); + + if (trigger_reason_bitmap & BIT(ROAM_TRIGGER_REASON_BTM)) fw_trigger_bitmap |= BIT(WMI_ROAM_TRIGGER_REASON_BTM); - if (trigger_reason_bitmap & ROAM_CONTROL_TRIGGER_REASON_BSS_LOAD) + if (trigger_reason_bitmap & BIT(ROAM_TRIGGER_REASON_UNIT_TEST)) + fw_trigger_bitmap |= BIT(WMI_ROAM_TRIGGER_REASON_UNIT_TEST); + + if (trigger_reason_bitmap & BIT(ROAM_TRIGGER_REASON_BSS_LOAD)) fw_trigger_bitmap |= BIT(WMI_ROAM_TRIGGER_REASON_BSS_LOAD); + if (trigger_reason_bitmap & BIT(ROAM_TRIGGER_REASON_DEAUTH)) + fw_trigger_bitmap |= BIT(WMI_ROAM_TRIGGER_REASON_DEAUTH); + + if (trigger_reason_bitmap & BIT(ROAM_TRIGGER_REASON_IDLE)) + fw_trigger_bitmap |= BIT(WMI_ROAM_TRIGGER_REASON_IDLE); + + if (trigger_reason_bitmap & BIT(ROAM_TRIGGER_REASON_STA_KICKOUT)) + fw_trigger_bitmap |= BIT(WMI_ROAM_TRIGGER_REASON_STA_KICKOUT); + return fw_trigger_bitmap; } @@ -22495,6 +23025,39 @@ static QDF_STATUS send_set_roam_trigger_cmd_tlv(wmi_unified_t wmi_handle, return ret; } +static QDF_STATUS send_roam_scan_get_ch_req_tlv(wmi_unified_t wmi_handle, + uint32_t vdev_id) +{ + wmi_buf_t buf; + wmi_roam_get_scan_channel_list_cmd_fixed_param *cmd; + uint16_t len = sizeof(*cmd); + int ret; + + buf = wmi_buf_alloc(wmi_handle, len); + if (!buf) { + WMI_LOGE("%s: Failed to allocate wmi buffer", __func__); + return QDF_STATUS_E_NOMEM; + } + + cmd = (wmi_roam_get_scan_channel_list_cmd_fixed_param *) + wmi_buf_data(buf); + WMITLV_SET_HDR(&cmd->tlv_header, + WMITLV_TAG_STRUC_wmi_roam_get_scan_channel_list_cmd_fixed_param, + WMITLV_GET_STRUCT_TLVLEN + (wmi_roam_get_scan_channel_list_cmd_fixed_param)); + cmd->vdev_id = vdev_id; + wmi_mtrace(WMI_ROAM_GET_SCAN_CHANNEL_LIST_CMDID, vdev_id, 0); + ret = wmi_unified_cmd_send(wmi_handle, buf, len, + WMI_ROAM_GET_SCAN_CHANNEL_LIST_CMDID); + if (QDF_IS_STATUS_ERROR(ret)) { + WMI_LOGE("Failed to send get roam scan channels request = %d", + ret); + wmi_buf_free(buf); + } + + return ret; +} + /** * send_offload_11k_cmd_tlv() - send wmi cmd with 11k offload params * @wmi_handle: wmi handler @@ -23020,6 +23583,564 @@ static QDF_STATUS send_mws_coex_status_req_cmd_tlv(wmi_unified_t wmi_handle, } #endif +#ifdef FEATURE_ANI_LEVEL_REQUEST +static QDF_STATUS send_ani_level_cmd_tlv(wmi_unified_t wmi_handle, + uint32_t *freqs, + uint8_t num_freqs) +{ + wmi_buf_t buf; + wmi_get_channel_ani_cmd_fixed_param *cmd; + QDF_STATUS ret; + uint32_t len; + A_UINT32 *chan_list; + uint8_t i, *buf_ptr; + + len = sizeof(wmi_get_channel_ani_cmd_fixed_param) + + WMI_TLV_HDR_SIZE + + num_freqs * sizeof(A_UINT32); + + buf = wmi_buf_alloc(wmi_handle, len); + if (!buf) + return QDF_STATUS_E_FAILURE; + + buf_ptr = (uint8_t *)wmi_buf_data(buf); + cmd = (wmi_get_channel_ani_cmd_fixed_param *)buf_ptr; + WMITLV_SET_HDR(&cmd->tlv_header, + WMITLV_TAG_STRUC_wmi_get_channel_ani_cmd_fixed_param, + WMITLV_GET_STRUCT_TLVLEN( + wmi_get_channel_ani_cmd_fixed_param)); + + buf_ptr += sizeof(wmi_get_channel_ani_cmd_fixed_param); + WMITLV_SET_HDR(buf_ptr, WMITLV_TAG_ARRAY_UINT32, + (num_freqs * sizeof(A_UINT32))); + + chan_list = (A_UINT32 *)(buf_ptr + WMI_TLV_HDR_SIZE); + for (i = 0; i < num_freqs; i++) { + chan_list[i] = freqs[i]; + WMI_LOGD("Requesting ANI for channel[%d]", chan_list[i]); + } + + ret = wmi_unified_cmd_send(wmi_handle, buf, len, + WMI_GET_CHANNEL_ANI_CMDID); + + if (QDF_IS_STATUS_ERROR(ret)) { + WMI_LOGE("WMI_GET_CHANNEL_ANI_CMDID send error %d", ret); + wmi_buf_free(buf); + } + + return ret; +} + +static QDF_STATUS extract_ani_level_tlv(uint8_t *evt_buf, + struct wmi_host_ani_level_event **info, + uint32_t *num_freqs) +{ + WMI_GET_CHANNEL_ANI_EVENTID_param_tlvs *param_buf; + wmi_get_channel_ani_event_fixed_param *fixed_param; + wmi_channel_ani_info_tlv_param *tlv_params; + uint8_t *buf_ptr, i; + + param_buf = (WMI_GET_CHANNEL_ANI_EVENTID_param_tlvs *)evt_buf; + if (!param_buf) { + wmi_err("Invalid ani level event buffer"); + return QDF_STATUS_E_INVAL; + } + + fixed_param = + (wmi_get_channel_ani_event_fixed_param *)param_buf->fixed_param; + if (!fixed_param) { + wmi_err("Invalid fixed param"); + return QDF_STATUS_E_INVAL; + } + + buf_ptr = (uint8_t *)fixed_param; + buf_ptr += sizeof(wmi_get_channel_ani_event_fixed_param); + buf_ptr += WMI_TLV_HDR_SIZE; + + *num_freqs = param_buf->num_ani_info; + if (*num_freqs > MAX_NUM_FREQS_FOR_ANI_LEVEL) { + wmi_err("Invalid number of freqs received"); + return QDF_STATUS_E_INVAL; + } + + *info = qdf_mem_malloc(*num_freqs * + sizeof(struct wmi_host_ani_level_event)); + if (!(*info)) + return QDF_STATUS_E_NOMEM; + + tlv_params = (wmi_channel_ani_info_tlv_param *)buf_ptr; + for (i = 0; i < param_buf->num_ani_info; i++) { + (*info)[i].ani_level = tlv_params->ani_level; + (*info)[i].chan_freq = tlv_params->chan_freq; + tlv_params++; + } + + return QDF_STATUS_SUCCESS; +} +#endif /* FEATURE_ANI_LEVEL_REQUEST */ + +#ifdef WLAN_FEATURE_PKT_CAPTURE +static QDF_STATUS +extract_vdev_mgmt_offload_event_tlv(void *handle, void *evt_buf, + struct mgmt_offload_event_params *params) +{ + WMI_VDEV_MGMT_OFFLOAD_EVENTID_param_tlvs *param_tlvs; + wmi_mgmt_hdr *hdr; + + param_tlvs = (WMI_VDEV_MGMT_OFFLOAD_EVENTID_param_tlvs *)evt_buf; + if (!param_tlvs) + return QDF_STATUS_E_INVAL; + + hdr = param_tlvs->fixed_param; + if (!hdr) + return QDF_STATUS_E_INVAL; + + if (hdr->buf_len > param_tlvs->num_bufp) + return QDF_STATUS_E_INVAL; + + params->tsf_l32 = hdr->tsf_l32; + params->chan_freq = hdr->chan_freq; + params->rate_kbps = hdr->rate_kbps; + params->rssi = hdr->rssi; + params->buf_len = hdr->buf_len; + params->tx_status = hdr->tx_status; + params->buf = param_tlvs->bufp; + params->tx_retry_cnt = hdr->tx_retry_cnt; + return QDF_STATUS_SUCCESS; +} +#endif /* WLAN_FEATURE_PKT_CAPTURE */ + +#ifdef FEATURE_WLAN_TIME_SYNC_FTM +/** + * send_wlan_ts_ftm_trigger_cmd_tlv(): send wlan time sync cmd to FW + * + * @wmi: wmi handle + * @vdev_id: vdev id + * @burst_mode: Indicates whether relation derived using FTM is needed for + * each FTM frame or only aggregated result is required. + * + * Send WMI_AUDIO_SYNC_TRIGGER_CMDID to FW. + * + * Return: QDF_STATUS + */ +static QDF_STATUS send_wlan_ts_ftm_trigger_cmd_tlv(wmi_unified_t wmi, + uint32_t vdev_id, + bool burst_mode) +{ + wmi_audio_sync_trigger_cmd_fixed_param *cmd; + wmi_buf_t buf; + int32_t len = sizeof(*cmd); + + buf = wmi_buf_alloc(wmi, len); + if (!buf) { + WMI_LOGP("%s: wmi_buf_alloc failed", __func__); + return QDF_STATUS_E_NOMEM; + } + cmd = (wmi_audio_sync_trigger_cmd_fixed_param *)wmi_buf_data(buf); + WMITLV_SET_HDR(&cmd->tlv_header, + WMITLV_TAG_STRUC_wmi_audio_sync_trigger_cmd_fixed_param, + WMITLV_GET_STRUCT_TLVLEN(wmi_audio_sync_trigger_cmd_fixed_param)); + cmd->vdev_id = vdev_id; + cmd->agg_relation = burst_mode ? false : true; + if (wmi_unified_cmd_send(wmi, buf, len, WMI_VDEV_AUDIO_SYNC_TRIGGER_CMDID)) { + WMI_LOGE("%s: failed to send audio sync trigger cmd", __func__); + wmi_buf_free(buf); + return QDF_STATUS_E_FAILURE; + } + + return QDF_STATUS_SUCCESS; +} + +static QDF_STATUS send_wlan_ts_qtime_cmd_tlv(wmi_unified_t wmi, + uint32_t vdev_id, + uint64_t lpass_ts) +{ + wmi_audio_sync_qtimer_cmd_fixed_param *cmd; + wmi_buf_t buf; + int32_t len = sizeof(*cmd); + + buf = wmi_buf_alloc(wmi, len); + if (!buf) { + WMI_LOGP("%s: wmi_buf_alloc failed", __func__); + return QDF_STATUS_E_NOMEM; + } + cmd = (wmi_audio_sync_qtimer_cmd_fixed_param *)wmi_buf_data(buf); + WMITLV_SET_HDR(&cmd->tlv_header, + WMITLV_TAG_STRUC_wmi_audio_sync_qtimer_cmd_fixed_param, + WMITLV_GET_STRUCT_TLVLEN(wmi_audio_sync_qtimer_cmd_fixed_param)); + cmd->vdev_id = vdev_id; + cmd->qtimer_u32 = (uint32_t)((lpass_ts & 0xffffffff00000000LL) >> 32); + cmd->qtimer_l32 = (uint32_t)(lpass_ts & 0xffffffffLL); + + if (wmi_unified_cmd_send(wmi, buf, len, WMI_VDEV_AUDIO_SYNC_QTIMER_CMDID)) { + WMI_LOGP("%s: Failed to send audio qtime command", __func__); + wmi_buf_free(buf); + return QDF_STATUS_E_FAILURE; + } + + return QDF_STATUS_SUCCESS; +} + +static QDF_STATUS extract_time_sync_ftm_start_stop_event_tlv( + wmi_unified_t wmi, void *buf, + struct ftm_time_sync_start_stop_params *param) +{ + WMI_VDEV_AUDIO_SYNC_START_STOP_EVENTID_param_tlvs *param_buf; + wmi_audio_sync_start_stop_event_fixed_param *resp_event; + + param_buf = (WMI_VDEV_AUDIO_SYNC_START_STOP_EVENTID_param_tlvs *)buf; + if (!param_buf) { + WMI_LOGE("Invalid audio sync start stop event buffer"); + return QDF_STATUS_E_FAILURE; + } + + resp_event = param_buf->fixed_param; + if (!resp_event) { + WMI_LOGE("Invalid audio sync start stop fixed param buffer"); + return QDF_STATUS_E_FAILURE; + } + + param->vdev_id = resp_event->vdev_id; + param->timer_interval = resp_event->periodicity; + param->num_reads = resp_event->reads_needed; + param->qtime = ((uint64_t)resp_event->qtimer_u32 << 32) | + resp_event->qtimer_l32; + param->mac_time = ((uint64_t)resp_event->mac_timer_u32 << 32) | + resp_event->mac_timer_l32; + + WMI_LOGI("%s: FTM time sync time_interval %d, num_reads %d", __func__, + param->timer_interval, param->num_reads); + + return QDF_STATUS_SUCCESS; +} + +static QDF_STATUS +extract_time_sync_ftm_offset_event_tlv(wmi_unified_t wmi, void *buf, + struct ftm_time_sync_offset *param) +{ + WMI_VDEV_AUDIO_SYNC_Q_MASTER_SLAVE_OFFSET_EVENTID_param_tlvs *param_buf; + wmi_audio_sync_q_master_slave_offset_event_fixed_param *resp_event; + wmi_audio_sync_q_master_slave_times *q_pair; + int iter; + + param_buf = + (WMI_VDEV_AUDIO_SYNC_Q_MASTER_SLAVE_OFFSET_EVENTID_param_tlvs *)buf; + if (!param_buf) { + WMI_LOGE("Invalid timesync ftm offset event buffer"); + return QDF_STATUS_E_FAILURE; + } + + resp_event = param_buf->fixed_param; + if (!resp_event) { + WMI_LOGE("Invalid timesync ftm offset fixed param buffer"); + return QDF_STATUS_E_FAILURE; + } + + param->vdev_id = resp_event->vdev_id; + param->num_qtime = param_buf->num_audio_sync_q_master_slave_times; + q_pair = param_buf->audio_sync_q_master_slave_times; + if (!q_pair) { + WMI_LOGE("Invalid q_master_slave_times buffer"); + return QDF_STATUS_E_FAILURE; + } + + for (iter = 0; iter < param->num_qtime; iter++) { + param->pairs[iter].qtime_master = ( + (uint64_t)q_pair[iter].qmaster_u32 << 32) | + q_pair[iter].qmaster_l32; + param->pairs[iter].qtime_slave = ( + (uint64_t)q_pair[iter].qslave_u32 << 32) | + q_pair[iter].qslave_l32; + } + return QDF_STATUS_SUCCESS; +} +#endif /* FEATURE_WLAN_TIME_SYNC_FTM */ + +#ifdef WLAN_FEATURE_ROAM_OFFLOAD +/** + * extract_roam_trigger_stats_tlv() - Extract the Roam trigger stats + * from the WMI_ROAM_STATS_EVENTID + * @wmi_handle: wmi handle + * @evt_buf: Pointer to the event buffer + * @trig: Pointer to destination structure to fill data + * @idx: TLV id + */ +static QDF_STATUS +extract_roam_trigger_stats_tlv(wmi_unified_t wmi_handle, void *evt_buf, + struct wmi_roam_trigger_info *trig, uint8_t idx) +{ + WMI_ROAM_STATS_EVENTID_param_tlvs *param_buf; + wmi_roam_trigger_reason *src_data = NULL; + + param_buf = (WMI_ROAM_STATS_EVENTID_param_tlvs *)evt_buf; + if (!param_buf || !param_buf->roam_trigger_reason) + return QDF_STATUS_E_FAILURE; + + src_data = ¶m_buf->roam_trigger_reason[idx]; + + trig->present = true; + trig->trigger_reason = src_data->trigger_reason; + trig->trigger_sub_reason = src_data->trigger_sub_reason; + trig->current_rssi = src_data->current_rssi; + trig->timestamp = src_data->timestamp; + + switch (trig->trigger_reason) { + case WMI_ROAM_TRIGGER_REASON_PER: + case WMI_ROAM_TRIGGER_REASON_BMISS: + case WMI_ROAM_TRIGGER_REASON_HIGH_RSSI: + case WMI_ROAM_TRIGGER_REASON_PERIODIC: + case WMI_ROAM_TRIGGER_REASON_MAWC: + case WMI_ROAM_TRIGGER_REASON_DENSE: + case WMI_ROAM_TRIGGER_REASON_BACKGROUND: + case WMI_ROAM_TRIGGER_REASON_IDLE: + case WMI_ROAM_TRIGGER_REASON_FORCED: + case WMI_ROAM_TRIGGER_REASON_UNIT_TEST: + return QDF_STATUS_SUCCESS; + + case WMI_ROAM_TRIGGER_REASON_BTM: + trig->btm_trig_data.btm_request_mode = + src_data->btm_request_mode; + trig->btm_trig_data.disassoc_timer = + src_data->disassoc_imminent_timer; + trig->btm_trig_data.validity_interval = + src_data->validity_internal; + trig->btm_trig_data.candidate_list_count = + src_data->candidate_list_count; + trig->btm_trig_data.btm_resp_status = + src_data->btm_response_status_code; + return QDF_STATUS_SUCCESS; + + case WMI_ROAM_TRIGGER_REASON_BSS_LOAD: + trig->cu_trig_data.cu_load = src_data->cu_load; + return QDF_STATUS_SUCCESS; + + case WMI_ROAM_TRIGGER_REASON_DEAUTH: + trig->deauth_trig_data.type = src_data->deauth_type; + trig->deauth_trig_data.reason = src_data->deauth_reason; + return QDF_STATUS_SUCCESS; + + case WMI_ROAM_TRIGGER_REASON_LOW_RSSI: + trig->rssi_trig_data.threshold = src_data->roam_rssi_threshold; + return QDF_STATUS_SUCCESS; + default: + return QDF_STATUS_SUCCESS; + } + + return QDF_STATUS_SUCCESS; +} + +/** + * extract_roam_scan_ap_stats_tlv() - Extract the Roam trigger stats + * from the WMI_ROAM_STATS_EVENTID + * @wmi_handle: wmi handle + * @evt_buf: Pointer to the event buffer + * @dst: Pointer to destination structure to fill data + * @ap_idx: TLV index for this roam scan + * @num_cand: number of candidates list in the roam scan + */ +static QDF_STATUS +extract_roam_scan_ap_stats_tlv(wmi_unified_t wmi_handle, void *evt_buf, + struct wmi_roam_candidate_info *dst, + uint8_t ap_idx, uint16_t num_cand) +{ + WMI_ROAM_STATS_EVENTID_param_tlvs *param_buf; + wmi_roam_ap_info *src = NULL; + uint8_t i; + + param_buf = (WMI_ROAM_STATS_EVENTID_param_tlvs *)evt_buf; + if (!param_buf) + return QDF_STATUS_E_FAILURE; + + src = ¶m_buf->roam_ap_info[ap_idx]; + + for (i = 0; i < num_cand; i++) { + WMI_MAC_ADDR_TO_CHAR_ARRAY(&src->bssid, dst->bssid.bytes); + dst->type = src->candidate_type; + dst->freq = src->channel; + dst->etp = src->etp; + dst->rssi = src->rssi; + dst->rssi_score = src->rssi_score; + dst->cu_load = src->cu_load; + dst->cu_score = src->cu_score; + dst->total_score = src->total_score; + dst->timestamp = src->timestamp; + + src++; + dst++; + } + + return QDF_STATUS_SUCCESS; +} + +/** + * extract_roam_scan_stats_tlv() - Extract the Roam trigger stats + * from the WMI_ROAM_STATS_EVENTID + * @wmi_handle: wmi handle + * @evt_buf: Pointer to the event buffer + * @dst: Pointer to destination structure to fill data + * @idx: TLV id + * @chan_idx: Index of the channel tlv for the current roam trigger + * @ap_idx: Index of the candidate AP TLV for the current roam trigger + */ +static QDF_STATUS +extract_roam_scan_stats_tlv(wmi_unified_t wmi_handle, void *evt_buf, + struct wmi_roam_scan_data *dst, uint8_t idx, + uint8_t chan_idx, uint8_t ap_idx) +{ + + WMI_ROAM_STATS_EVENTID_param_tlvs *param_buf; + wmi_roam_scan_info *src_data = NULL; + wmi_roam_scan_channel_info *src_chan = NULL; + QDF_STATUS status; + uint8_t i; + + param_buf = (WMI_ROAM_STATS_EVENTID_param_tlvs *)evt_buf; + if (!param_buf || !param_buf->roam_scan_info) + return QDF_STATUS_E_FAILURE; + + src_data = ¶m_buf->roam_scan_info[idx]; + + dst->present = true; + dst->type = src_data->roam_scan_type; + dst->num_chan = src_data->roam_scan_channel_count; + dst->next_rssi_threshold = src_data->next_rssi_trigger_threshold; + + /* Read the channel data only for dst->type is 0 (partial scan) */ + if (dst->num_chan && !dst->type) { + if (dst->num_chan > MAX_ROAM_SCAN_CHAN) + dst->num_chan = MAX_ROAM_SCAN_CHAN; + + src_chan = ¶m_buf->roam_scan_chan_info[chan_idx]; + for (i = 0; i < dst->num_chan; i++) { + dst->chan_freq[i] = src_chan->channel; + src_chan++; + } + } + + if (!src_data->roam_ap_count) + return QDF_STATUS_SUCCESS; + + dst->num_ap = src_data->roam_ap_count; + if (dst->num_ap > MAX_ROAM_CANDIDATE_AP) + dst->num_ap = MAX_ROAM_CANDIDATE_AP; + + status = extract_roam_scan_ap_stats_tlv(wmi_handle, evt_buf, dst->ap, + ap_idx, dst->num_ap); + if (QDF_IS_STATUS_ERROR(status)) { + WMI_LOGE("Extract candidate stats for tlv[%d] failed", idx); + return status; + } + + return QDF_STATUS_SUCCESS; +} + +/** + * extract_roam_scan_stats_tlv() - Extract the Roam trigger stats + * from the WMI_ROAM_STATS_EVENTID + * @wmi_handle: wmi handle + * @evt_buf: Pointer to the event buffer + * @dst: Pointer to destination structure to fill data + * @idx: TLV id + */ +static QDF_STATUS +extract_roam_result_stats_tlv(wmi_unified_t wmi_handle, void *evt_buf, + struct wmi_roam_result *dst, uint8_t idx) +{ + WMI_ROAM_STATS_EVENTID_param_tlvs *param_buf; + wmi_roam_result *src_data = NULL; + + param_buf = (WMI_ROAM_STATS_EVENTID_param_tlvs *)evt_buf; + if (!param_buf || !param_buf->roam_result) + return QDF_STATUS_E_FAILURE; + + src_data = ¶m_buf->roam_result[idx]; + + dst->present = true; + dst->status = src_data->roam_status ? false : true; + dst->timestamp = src_data->timestamp; + dst->fail_reason = src_data->roam_fail_reason; + + return QDF_STATUS_SUCCESS; +} + +/** + * extract_roam_11kv_stats_tlv() - Extract the Roam trigger stats + * from the WMI_ROAM_STATS_EVENTID + * @wmi_handle: wmi handle + * @evt_buf: Pointer to the event buffer + * @dst: Pointer to destination structure to fill data + * @idx: TLV id + * @rpt_idx: Neighbor report Channel index + */ +static QDF_STATUS +extract_roam_11kv_stats_tlv(wmi_unified_t wmi_handle, void *evt_buf, + struct wmi_neighbor_report_data *dst, + uint8_t idx, uint8_t rpt_idx) +{ + WMI_ROAM_STATS_EVENTID_param_tlvs *param_buf; + wmi_roam_neighbor_report_info *src_data = NULL; + wmi_roam_neighbor_report_channel_info *src_freq = NULL; + uint8_t i; + + param_buf = (WMI_ROAM_STATS_EVENTID_param_tlvs *)evt_buf; + if (!param_buf || !param_buf->roam_neighbor_report_info) + return QDF_STATUS_E_FAILURE; + + src_data = ¶m_buf->roam_neighbor_report_info[idx]; + + dst->present = true; + dst->req_type = src_data->request_type; + dst->num_freq = src_data->neighbor_report_channel_count; + dst->req_time = src_data->neighbor_report_request_timestamp; + dst->resp_time = src_data->neighbor_report_response_timestamp; + + if (!dst->num_freq) + return QDF_STATUS_SUCCESS; + + src_freq = ¶m_buf->roam_neighbor_report_chan_info[rpt_idx]; + if (dst->num_freq > MAX_ROAM_SCAN_CHAN) + dst->num_freq = MAX_ROAM_SCAN_CHAN; + + for (i = 0; i < dst->num_freq; i++) { + dst->freq[i] = src_freq->channel; + src_freq++; + } + + return QDF_STATUS_SUCCESS; +} + +#else +static inline QDF_STATUS +extract_roam_trigger_stats_tlv(wmi_unified_t wmi_handle, void *evt_buf, + struct wmi_roam_trigger_info *trig, uint8_t idx) +{ + return QDF_STATUS_E_NOSUPPORT; +} + +static inline QDF_STATUS +extract_roam_result_stats_tlv(wmi_unified_t wmi_handle, void *evt_buf, + struct wmi_roam_result *dst, uint8_t idx) +{ + return QDF_STATUS_E_NOSUPPORT; +} + +static QDF_STATUS +extract_roam_11kv_stats_tlv(wmi_unified_t wmi_handle, void *evt_buf, + struct wmi_neighbor_report_data *dst, + uint8_t idx, uint8_t rpt_idx) +{ + return QDF_STATUS_E_NOSUPPORT; +} + +static QDF_STATUS +extract_roam_scan_stats_tlv(wmi_unified_t wmi_handle, void *evt_buf, + struct wmi_roam_scan_data *dst, uint8_t idx, + uint8_t chan_idx, uint8_t ap_idx) +{ + return QDF_STATUS_E_NOSUPPORT; +} +#endif + struct wmi_ops tlv_ops = { .send_vdev_create_cmd = send_vdev_create_cmd_tlv, .send_vdev_delete_cmd = send_vdev_delete_cmd_tlv, @@ -23073,6 +24194,7 @@ struct wmi_ops tlv_ops = { .send_offchan_data_tx_cmd = send_offchan_data_tx_cmd_tlv, .send_modem_power_state_cmd = send_modem_power_state_cmd_tlv, .send_set_sta_ps_mode_cmd = send_set_sta_ps_mode_cmd_tlv, + .send_idle_roam_monitor_cmd = send_idle_roam_monitor_cmd_tlv, .send_set_sta_uapsd_auto_trig_cmd = send_set_sta_uapsd_auto_trig_cmd_tlv, .send_get_temperature_cmd = send_get_temperature_cmd_tlv, @@ -23195,8 +24317,14 @@ struct wmi_ops tlv_ops = { .send_fw_profiling_cmd = send_fw_profiling_cmd_tlv, .send_csa_offload_enable_cmd = send_csa_offload_enable_cmd_tlv, .send_nat_keepalive_en_cmd = send_nat_keepalive_en_cmd_tlv, +#ifdef WLAN_SEND_DSCP_UP_MAP_TO_FW + .send_dscp_tid_map_cmd = send_dscp_tid_map_cmd_tlv, +#endif .send_wlm_latency_level_cmd = send_wlm_latency_level_cmd_tlv, .send_start_oem_data_cmd = send_start_oem_data_cmd_tlv, +#ifdef FEATURE_OEM_DATA + .send_start_oemv2_data_cmd = send_start_oemv2_data_cmd_tlv, +#endif #ifdef WLAN_FEATURE_CIF_CFR .send_oem_dma_cfg_cmd = send_oem_dma_cfg_cmd_tlv, #endif @@ -23489,6 +24617,7 @@ struct wmi_ops tlv_ops = { .send_ndp_end_req_cmd = nan_ndp_end_req_tlv, .extract_ndp_initiator_rsp = extract_ndp_initiator_rsp_tlv, .extract_ndp_ind = extract_ndp_ind_tlv, + .extract_nan_msg = extract_nan_msg_tlv, .extract_ndp_confirm = extract_ndp_confirm_tlv, .extract_ndp_responder_rsp = extract_ndp_responder_rsp_tlv, .extract_ndp_end_rsp = extract_ndp_end_rsp_tlv, @@ -23497,6 +24626,9 @@ struct wmi_ops tlv_ops = { #endif .send_btm_config = send_btm_config_cmd_tlv, .send_roam_bss_load_config = send_roam_bss_load_config_tlv, + .send_idle_roam_params = send_idle_roam_params_tlv, + .send_disconnect_roam_params = send_disconnect_roam_params_tlv, + .send_roam_preauth_status = send_roam_preauth_status_tlv, .send_obss_detection_cfg_cmd = send_obss_detection_cfg_cmd_tlv, .extract_obss_detection_info = extract_obss_detection_info_tlv, #ifdef WLAN_SUPPORT_FILS @@ -23527,6 +24659,28 @@ struct wmi_ops tlv_ops = { .send_mws_coex_status_req_cmd = send_mws_coex_status_req_cmd_tlv, #endif .send_set_roam_trigger_cmd = send_set_roam_trigger_cmd_tlv, +#ifdef FEATURE_ANI_LEVEL_REQUEST + .send_ani_level_cmd = send_ani_level_cmd_tlv, + .extract_ani_level = extract_ani_level_tlv, +#endif /* FEATURE_ANI_LEVEL_REQUEST */ + +#ifdef WLAN_FEATURE_PKT_CAPTURE + .extract_vdev_mgmt_offload_event = extract_vdev_mgmt_offload_event_tlv, +#endif /* WLAN_FEATURE_PKT_CAPTURE */ +#ifdef FEATURE_WLAN_TIME_SYNC_FTM + .send_wlan_time_sync_ftm_trigger_cmd = send_wlan_ts_ftm_trigger_cmd_tlv, + .send_wlan_ts_qtime_cmd = send_wlan_ts_qtime_cmd_tlv, + .extract_time_sync_ftm_start_stop_event = + extract_time_sync_ftm_start_stop_event_tlv, + .extract_time_sync_ftm_offset_event = + extract_time_sync_ftm_offset_event_tlv, +#endif /* FEATURE_WLAN_TIME_SYNC_FTM */ + + .extract_roam_trigger_stats = extract_roam_trigger_stats_tlv, + .extract_roam_scan_stats = extract_roam_scan_stats_tlv, + .extract_roam_result_stats = extract_roam_result_stats_tlv, + .extract_roam_11kv_stats = extract_roam_11kv_stats_tlv, + .send_roam_scan_get_ch_req = send_roam_scan_get_ch_req_tlv, }; /** @@ -23843,6 +24997,26 @@ static void populate_tlv_events_id(uint32_t *event_ids) #endif event_ids[wmi_coex_report_antenna_isolation_event_id] = WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID; + event_ids[wmi_get_ani_level_event_id] = WMI_GET_CHANNEL_ANI_EVENTID; + event_ids[wmi_oem_data_event_id] = WMI_OEM_DATA_EVENTID; + event_ids[wmi_roam_auth_offload_event_id] = + WMI_ROAM_PREAUTH_START_EVENTID; + event_ids[wmi_mgmt_offload_data_event_id] = + WMI_VDEV_MGMT_OFFLOAD_EVENTID; + event_ids[wmi_nan_dmesg_event_id] = + WMI_NAN_DMESG_EVENTID; + event_ids[wmi_roam_pmkid_request_event_id] = + WMI_ROAM_PMKID_REQUEST_EVENTID; +#ifdef FEATURE_WLAN_TIME_SYNC_FTM + event_ids[wmi_wlan_time_sync_ftm_start_stop_event_id] = + WMI_VDEV_AUDIO_SYNC_START_STOP_EVENTID; + event_ids[wmi_wlan_time_sync_q_master_slave_offset_eventid] = + WMI_VDEV_AUDIO_SYNC_Q_MASTER_SLAVE_OFFSET_EVENTID; +#endif + event_ids[wmi_roam_stats_event_id] = WMI_ROAM_STATS_EVENTID; + event_ids[wmi_roam_scan_chan_list_id] = + WMI_ROAM_SCAN_CHANNEL_LIST_EVENTID; + } /** @@ -24079,6 +25253,25 @@ static void populate_tlv_service(uint32_t *wmi_service) WMI_SERVICE_TX_COMPL_TSF64; wmi_service[wmi_service_three_way_coex_config_legacy] = WMI_SERVICE_THREE_WAY_COEX_CONFIG_LEGACY; + wmi_service[wmi_service_wpa3_ft_sae_support] = + WMI_SERVICE_WPA3_FT_SAE_SUPPORT; + wmi_service[wmi_service_wpa3_ft_suite_b_support] = + WMI_SERVICE_WPA3_FT_SUITE_B_SUPPORT; + wmi_service[wmi_service_ft_fils] = + WMI_SERVICE_WPA3_FT_FILS; + wmi_service[wmi_service_adaptive_11r_support] = + WMI_SERVICE_ADAPTIVE_11R_ROAM; + wmi_service[wmi_service_sae_roam_support] = + WMI_SERVICE_WPA3_SAE_ROAM_SUPPORT; + wmi_service[wmi_service_owe_roam_support] = + WMI_SERVICE_WPA3_OWE_ROAM_SUPPORT; + wmi_service[wmi_service_nan_vdev] = WMI_SERVICE_NAN_VDEV_SUPPORT; + wmi_service[wmi_service_packet_capture_support] = + WMI_SERVICE_PACKET_CAPTURE_SUPPORT; + wmi_service[wmi_service_time_sync_ftm] = + WMI_SERVICE_AUDIO_SYNC_SUPPORT; + wmi_service[wmi_roam_scan_chan_list_to_host_support] = + WMI_SERVICE_ROAM_SCAN_CHANNEL_LIST_TO_HOST_SUPPORT; } #ifndef CONFIG_MCL diff --git a/drivers/staging/qcacld-3.0/Kbuild b/drivers/staging/qcacld-3.0/Kbuild index 5cfc2d2f724d..f7e82ffb3fee 100644 --- a/drivers/staging/qcacld-3.0/Kbuild +++ b/drivers/staging/qcacld-3.0/Kbuild @@ -193,6 +193,13 @@ ifeq ($(CONFIG_QCACLD_FEATURE_HW_CAPABILITY), y) HDD_OBJS += $(HDD_SRC_DIR)/wlan_hdd_hw_capability.o endif +ifeq ($(CONFIG_FEATURE_WLAN_TIME_SYNC_FTM), y) +HDD_OBJS += $(HDD_SRC_DIR)/wlan_hdd_ftm_time_sync.o +endif + +#Flag to enable SAR Safety Feature +cppflags-$(CONFIG_SAR_SAFETY_FEATURE) += -DSAR_SAFETY_FEATURE + ########### HOST DIAG LOG ########### HOST_DIAG_LOG_DIR := $(WLAN_COMMON_ROOT)/utils/host_diag_log @@ -773,6 +780,36 @@ ACTION_OUI_OBJS := $(ACTION_OUI_DIR)/core/src/wlan_action_oui_main.o \ $(ACTION_OUI_DIR)/dispatcher/src/wlan_action_oui_ucfg_api.o endif +######## PACKET CAPTURE ######## + +PKT_CAPTURE_DIR := components/pkt_capture +PKT_CAPTURE_TARGET_IF_DIR := components/target_if/pkt_capture/ +PKT_CAPTURE_INC := -I$(WLAN_ROOT)/$(PKT_CAPTURE_DIR)/core/inc \ + -I$(WLAN_ROOT)/$(PKT_CAPTURE_DIR)/dispatcher/inc \ + -I$(WLAN_ROOT)/$(PKT_CAPTURE_TARGET_IF_DIR)/inc + +ifeq ($(CONFIG_WLAN_FEATURE_PKT_CAPTURE), y) +PKT_CAPTURE_OBJS := $(PKT_CAPTURE_DIR)/core/src/wlan_pkt_capture_main.o \ + $(PKT_CAPTURE_DIR)/core/src/wlan_pkt_capture_mon_thread.o \ + $(PKT_CAPTURE_DIR)/dispatcher/src/wlan_pkt_capture_ucfg_api.o \ + $(PKT_CAPTURE_DIR)/core/src/wlan_pkt_capture_mgmt_txrx.o \ + $(PKT_CAPTURE_DIR)/core/src/wlan_pkt_capture_data_txrx.o \ + $(PKT_CAPTURE_DIR)/dispatcher/src/wlan_pkt_capture_ucfg_api.o \ + $(PKT_CAPTURE_TARGET_IF_DIR)/src/target_if_pkt_capture.o +endif + +########## FTM TIME SYNC ########## + +FTM_TIME_SYNC_DIR := components/ftm_time_sync +FTM_TIME_SYNC_INC := -I$(WLAN_ROOT)/$(FTM_TIME_SYNC_DIR)/core/inc \ + -I$(WLAN_ROOT)/$(FTM_TIME_SYNC_DIR)/dispatcher/inc + +ifeq ($(CONFIG_FEATURE_WLAN_TIME_SYNC_FTM), y) +FTM_TIME_SYNC_OBJS := $(FTM_TIME_SYNC_DIR)/core/src/ftm_time_sync_main.o \ + $(FTM_TIME_SYNC_DIR)/dispatcher/src/ftm_time_sync_ucfg_api.o \ + $(FTM_TIME_SYNC_DIR)/dispatcher/src/wlan_ftm_time_sync_tgt_api.o +endif + ########## CLD TARGET_IF ####### CLD_TARGET_IF_DIR := components/target_if @@ -813,6 +850,11 @@ CLD_TARGET_IF_INC += -I$(WLAN_ROOT)/$(CLD_TARGET_IF_DIR)/action_oui/inc CLD_TARGET_IF_OBJ += $(CLD_TARGET_IF_DIR)/action_oui/src/target_if_action_oui.o endif +ifeq ($(CONFIG_FEATURE_WLAN_TIME_SYNC_FTM), y) +CLD_TARGET_IF_INC += -I$(WLAN_ROOT)/$(CLD_TARGET_IF_DIR)/ftm_time_sync/inc +CLD_TARGET_IF_OBJ += $(CLD_TARGET_IF_DIR)/ftm_time_sync/src/target_if_ftm_time_sync.o +endif + ############## UMAC P2P ########### P2P_DIR := umac/p2p P2P_CORE_DIR := $(P2P_DIR)/core @@ -1470,6 +1512,8 @@ endif INCS += $(DISA_INC) INCS += $(ACTION_OUI_INC) +INCS += $(PKT_CAPTURE_INC) +INCS += $(FTM_TIME_SYNC_INC) INCS += $(UMAC_DISP_INC) INCS += $(UMAC_SCAN_INC) @@ -1562,6 +1606,14 @@ ifeq ($(CONFIG_WLAN_FEATURE_ACTION_OUI), y) OBJS += $(ACTION_OUI_OBJS) endif +ifeq ($(CONFIG_WLAN_FEATURE_PKT_CAPTURE), y) +OBJS += $(PKT_CAPTURE_OBJS) +endif + +ifeq ($(CONFIG_FEATURE_WLAN_TIME_SYNC_FTM), y) +OBJS += $(FTM_TIME_SYNC_OBJS) +endif + OBJS += $(UMAC_DISP_OBJS) OBJS += $(UMAC_SCAN_OBJS) OBJS += $(UMAC_COMMON_OBJS) @@ -1581,6 +1633,7 @@ ccflags-y += $(INCS) cppflags-y += -DANI_OS_TYPE_ANDROID=6 \ -Wall\ + -Werror\ -D__linux__ cppflags-$(CONFIG_PTT_SOCK_SVC_ENABLE) += -DPTT_SOCK_SVC_ENABLE @@ -1623,6 +1676,7 @@ cppflags-$(CONFIG_CP_STATS) += -DQCA_SUPPORT_CP_STATS cppflags-$(CONFIG_FEATURE_MEMDUMP_ENABLE) += -DWLAN_FEATURE_MEMDUMP_ENABLE cppflags-$(CONFIG_FEATURE_FW_LOG_PARSING) += -DFEATURE_FW_LOG_PARSING cppflags-$(CONFIG_WLAN_RECORD_RX_PADDR) += -DHIF_RECORD_RX_PADDR +cppflags-$(CONFIG_FEATURE_OEM_DATA) += -DFEATURE_OEM_DATA ifeq ($(CONFIG_CNSS), y) ifeq ($(CONFIG_CNSS_SDIO), y) @@ -2024,6 +2078,10 @@ cppflags-$(CONFIG_NAN_CONVERGENCE) += -DWLAN_FEATURE_NAN_CONVERGENCE cppflags-$(CONFIG_FEATURE_WLAN_D0WOW) += -DFEATURE_WLAN_D0WOW +cppflags-$(CONFIG_WLAN_FEATURE_PKT_CAPTURE) += -DWLAN_FEATURE_PKT_CAPTURE + +cppflags-$(CONFIG_FEATURE_WLAN_TIME_SYNC_FTM) += -DFEATURE_WLAN_TIME_SYNC_FTM + cppflags-$(CONFIG_QCA_WIFI_NAPIER_EMULATION) += -DQCA_WIFI_NAPIER_EMULATION cppflags-$(CONFIG_SHADOW_V2) += -DCONFIG_SHADOW_V2 cppflags-$(CONFIG_QCA6290_HEADERS_DEF) += -DQCA6290_HEADERS_DEF @@ -2045,17 +2103,23 @@ endif cppflags-$(CONFIG_WLAN_FEATURE_11AX) += -DWLAN_FEATURE_11AX cppflags-$(CONFIG_WLAN_FEATURE_11AX) += -DWLAN_FEATURE_11AX_BSS_COLOR +#Enable support to get ANI value +ifeq ($(CONFIG_ANI_LEVEL_REQUEST), y) +cppflags-y += -DFEATURE_ANI_LEVEL_REQUEST +endif + # Dummy flag for WIN/MCL converged data path compilation cppflags-y += -DDP_PRINT_ENABLE=0 cppflags-y += -DATH_SUPPORT_WRAP=0 cppflags-y += -DQCA_HOST2FW_RXBUF_RING +cppflags-y += -DHIF_CE_HISTORY_MAX=8192 #endof dummy flags # Enable lock of serialization component to avoid race condition issues cppflags-y += -DWLAN_CMD_SERIALIZATION_LOCKING ccflags-$(CONFIG_ENABLE_SIZE_OPTIMIZE) += -Os - +ccflags-$(CONFIG_WLAN_FEATURE_ETHTOOL) += -DWLAN_FEATURE_ETHTOOL # DFS component cppflags-y += -DWLAN_DFS_STATIC_MEM_ALLOC cppflags-$(CONFIG_WLAN_DFS_MASTER_ENABLE) += -DQCA_MCL_DFS_SUPPORT @@ -2077,6 +2141,12 @@ cppflags-$(CONFIG_ENABLE_SMMU_S1_TRANSLATION) += -DENABLE_SMMU_S1_TRANSLATION #Flag to enable/disable MTRACE feature cppflags-$(CONFIG_ENABLE_MTRACE_LOG) += -DENABLE_MTRACE_LOG +#Flag to enable/disable Adaptive 11r feature +cppflags-$(CONFIG_ADAPTIVE_11R) += -DWLAN_ADAPTIVE_11R + +#Flag to enable/disable sae single pmk feature feature +cppflags-$(CONFIG_SAE_SINGLE_PMK) += -DWLAN_SAE_SINGLE_PMK + #Flag to enable NUD tracking cppflags-$(CONFIG_WLAN_NUD_TRACKING) += -DWLAN_NUD_TRACKING @@ -2095,6 +2165,9 @@ cppflags-$(CONFIG_QCACLD_FEATURE_MPTA_HELPER) += -DFEATURE_MPTA_HELPER #Flag to enable get hw capability cppflags-$(CONFIG_QCACLD_FEATURE_HW_CAPABILITY) += -DFEATURE_HW_CAPABILITY +cppflags-$(CONFIG_WLAN_CUSTOM_DSCP_UP_MAP) += -DWLAN_CUSTOM_DSCP_UP_MAP +cppflags-$(CONFIG_WLAN_SEND_DSCP_UP_MAP_TO_FW) += -DWLAN_SEND_DSCP_UP_MAP_TO_FW + ifdef CONFIG_SCHED_HISTORY_SIZE ccflags-y += -DWLAN_SCHED_HISTORY_SIZE=$(CONFIG_SCHED_HISTORY_SIZE) endif @@ -2128,6 +2201,9 @@ ifdef CONFIG_TGT_NUM_MSDU_DESC ccflags-y += -DCFG_TGT_NUM_MSDU_DESC=$(CONFIG_TGT_NUM_MSDU_DESC) endif +CONFIG_WLAN_MAX_VDEVS ?= 6 +ccflags-y += -DWLAN_MAX_VDEVS=$(CONFIG_WLAN_MAX_VDEVS) + KBUILD_CPPFLAGS += $(cppflags-y) # Currently, for versions of gcc which support it, the kernel Makefile diff --git a/drivers/staging/qcacld-3.0/components/action_oui/core/src/wlan_action_oui_parse.c b/drivers/staging/qcacld-3.0/components/action_oui/core/src/wlan_action_oui_parse.c index 347efc35c763..4a59a79001a7 100644 --- a/drivers/staging/qcacld-3.0/components/action_oui/core/src/wlan_action_oui_parse.c +++ b/drivers/staging/qcacld-3.0/components/action_oui/core/src/wlan_action_oui_parse.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -848,16 +848,12 @@ check_for_vendor_ap_capabilities(struct action_oui_extension *extension, } } - if (extension->info_mask & ACTION_OUI_INFO_AP_CAPABILITY_BAND) { - if ((*extension->capability & - ACTION_OUI_CAPABILITY_2G_BAND_MASK) && - !attr->enable_2g) - return false; - if ((*extension->capability & - ACTION_CAPABILITY_5G_BAND_MASK) && - !attr->enable_5g) - return false; - } + if (extension->info_mask & ACTION_OUI_INFO_AP_CAPABILITY_BAND && + ((attr->enable_5g && + !(*extension->capability & ACTION_CAPABILITY_5G_BAND_MASK)) || + (attr->enable_2g && + !(*extension->capability & ACTION_OUI_CAPABILITY_2G_BAND_MASK)))) + return false; return true; } @@ -901,7 +897,6 @@ action_oui_search(struct action_oui_psoc_priv *psoc_priv, qdf_mutex_acquire(&oui_priv->extension_lock); if (qdf_list_empty(extension_list)) { qdf_mutex_release(&oui_priv->extension_lock); - action_oui_debug("OUI List Empty"); return false; } @@ -917,44 +912,25 @@ action_oui_search(struct action_oui_psoc_priv *psoc_priv, * to other checks skipping the OUI and vendor data checks */ - if (!(extension->info_mask & ACTION_OUI_INFO_OUI)) { - action_oui_debug("Wildcard OUI found"); + if (!(extension->info_mask & ACTION_OUI_INFO_OUI)) wildcard_oui = true; - } oui_ptr = action_oui_get_oui_ptr(extension, attr); - if (!oui_ptr && !wildcard_oui) { - action_oui_debug("No matching IE found for OUI"); - QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_PE, - QDF_TRACE_LEVEL_DEBUG, - extension->oui, - extension->oui_length); + if (!oui_ptr && !wildcard_oui) goto next; - } - - action_oui_debug("IE found for OUI"); - QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_PE, - QDF_TRACE_LEVEL_DEBUG, - extension->oui, - extension->oui_length); if (extension->data_length && !wildcard_oui && - !check_for_vendor_oui_data(extension, oui_ptr)) { - action_oui_debug("Vendor IE Data mismatch"); + !check_for_vendor_oui_data(extension, oui_ptr)) goto next; - } + if ((extension->info_mask & ACTION_OUI_INFO_MAC_ADDRESS) && - !check_for_vendor_ap_mac(extension, attr)) { - action_oui_debug("Vendor IE MAC Mismatch"); + !check_for_vendor_ap_mac(extension, attr)) goto next; - } - if (!check_for_vendor_ap_capabilities(extension, attr)) { - action_oui_debug("Vendor IE capabilties mismatch"); + if (!check_for_vendor_ap_capabilities(extension, attr)) goto next; - } action_oui_debug("Vendor AP/STA found for OUI"); QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_PE, QDF_TRACE_LEVEL_DEBUG, diff --git a/drivers/staging/qcacld-3.0/components/action_oui/dispatcher/inc/wlan_action_oui_public_struct.h b/drivers/staging/qcacld-3.0/components/action_oui/dispatcher/inc/wlan_action_oui_public_struct.h index 817c1836e0be..09e8ec4477aa 100644 --- a/drivers/staging/qcacld-3.0/components/action_oui/dispatcher/inc/wlan_action_oui_public_struct.h +++ b/drivers/staging/qcacld-3.0/components/action_oui/dispatcher/inc/wlan_action_oui_public_struct.h @@ -88,6 +88,7 @@ * @ACTION_OUI_SWITCH_TO_11N_MODE: connect in 11n * @ACTION_OUI_CONNECT_1X1_WITH_1_CHAIN: connect in 1x1 & disable diversity gain * @ACTION_OUI_DISABLE_AGGRESSIVE_TX: disable aggressive TX in firmware + * @ACTION_OUI_DISABLE_AGGRESSIVE_EDCA: disable aggressive EDCA with the ap * @ACTION_OUI_MAXIMUM_ID: maximun number of action oui types */ enum action_oui_id { @@ -98,6 +99,7 @@ enum action_oui_id { ACTION_OUI_SWITCH_TO_11N_MODE = 4, ACTION_OUI_CONNECT_1X1_WITH_1_CHAIN = 5, ACTION_OUI_DISABLE_AGGRESSIVE_TX = 6, + ACTION_OUI_DISABLE_AGGRESSIVE_EDCA = 7, ACTION_OUI_MAXIMUM_ID }; diff --git a/drivers/staging/qcacld-3.0/components/action_oui/dispatcher/src/wlan_action_oui_ucfg_api.c b/drivers/staging/qcacld-3.0/components/action_oui/dispatcher/src/wlan_action_oui_ucfg_api.c index f6d31f9191da..4346a4fa6b4e 100644 --- a/drivers/staging/qcacld-3.0/components/action_oui/dispatcher/src/wlan_action_oui_ucfg_api.c +++ b/drivers/staging/qcacld-3.0/components/action_oui/dispatcher/src/wlan_action_oui_ucfg_api.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -141,8 +141,6 @@ QDF_STATUS ucfg_action_oui_send(struct wlan_objmgr_psoc *psoc) QDF_STATUS status = QDF_STATUS_E_INVAL; uint32_t id; - ACTION_OUI_ENTER(); - if (!psoc) { action_oui_err("psoc is NULL"); goto exit; @@ -161,7 +159,7 @@ QDF_STATUS ucfg_action_oui_send(struct wlan_objmgr_psoc *psoc) } exit: - ACTION_OUI_EXIT(); + return status; } @@ -172,8 +170,6 @@ bool ucfg_action_oui_search(struct wlan_objmgr_psoc *psoc, struct action_oui_psoc_priv *psoc_priv; bool found = false; - ACTION_OUI_ENTER(); - if (!psoc || !attr) { action_oui_err("Invalid psoc or search attrs"); goto exit; @@ -191,10 +187,8 @@ bool ucfg_action_oui_search(struct wlan_objmgr_psoc *psoc, } found = action_oui_search(psoc_priv, attr, action_id); - if (found) - action_oui_debug("Search Successful"); exit: - ACTION_OUI_EXIT(); + return found; } diff --git a/drivers/staging/qcacld-3.0/components/ftm_time_sync/core/inc/ftm_time_sync_main.h b/drivers/staging/qcacld-3.0/components/ftm_time_sync/core/inc/ftm_time_sync_main.h new file mode 100644 index 000000000000..a5d60cf74171 --- /dev/null +++ b/drivers/staging/qcacld-3.0/components/ftm_time_sync/core/inc/ftm_time_sync_main.h @@ -0,0 +1,184 @@ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +/** + * DOC: Declare private API which shall be used internally only + * in ftm_time_sync component. This file shall include prototypes of + * various notification handlers and logging functions. + * + * Note: This API should be never accessed out of ftm_time_sync component. + */ + +#ifndef _FTM_TIME_SYNC_MAIN_H_ +#define _FTM_TIME_SYNC_MAIN_H_ + +#include +#include +#include "ftm_time_sync_priv.h" +#include "ftm_time_sync_objmgr.h" + +#define ftm_time_sync_log(level, args...) \ + QDF_TRACE(QDF_MODULE_ID_FTM_TIME_SYNC, level, ## args) + +#define ftm_time_sync_logfl(level, format, args...) \ + ftm_time_sync_log(level, FL(format), ## args) + +#define ftm_time_sync_fatal(format, args...) \ + ftm_time_sync_logfl(QDF_TRACE_LEVEL_FATAL, format, ## args) +#define ftm_time_sync_err(format, args...) \ + ftm_time_sync_logfl(QDF_TRACE_LEVEL_ERROR, format, ## args) +#define ftm_time_sync_warn(format, args...) \ + ftm_time_sync_logfl(QDF_TRACE_LEVEL_WARN, format, ## args) +#define ftm_time_sync_info(format, args...) \ + ftm_time_sync_logfl(QDF_TRACE_LEVEL_INFO, format, ## args) +#define ftm_time_sync_debug(format, args...) \ + ftm_time_sync_logfl(QDF_TRACE_LEVEL_DEBUG, format, ## args) + +#define FTM_TIME_SYNC_ENTER() ftm_time_sync_debug("enter") +#define FTM_TIME_SYNC_EXIT() ftm_time_sync_debug("exit") + +/** + * ftm_time_sync_vdev_create_notification() - Handler for vdev create notify. + * @vdev: vdev which is going to be created by objmgr + * @arg: argument for notification handler + * + * Allocate and attach vdev private object. + * + * Return: QDF_STATUS + */ +QDF_STATUS ftm_time_sync_vdev_create_notification(struct wlan_objmgr_vdev *vdev, + void *arg); + +/** + * ftm_time_sync_vdev_destroy_notification() - Handler for vdev destroy notify. + * @vdev: vdev which is going to be destroyed by objmgr + * @arg: argument for notification handler + * + * Deallocate and detach vdev private object. + * + * Return QDF_STATUS + */ +QDF_STATUS +ftm_time_sync_vdev_destroy_notification(struct wlan_objmgr_vdev *vdev, + void *arg); + +/** + * ftm_time_sync_psoc_create_notification() - Handler for psoc create notify. + * @psoc: psoc which is going to be created by objmgr + * @arg: argument for notification handler + * + * Allocate and attach psoc private object. + * + * Return: QDF_STATUS + */ +QDF_STATUS +ftm_time_sync_psoc_create_notification(struct wlan_objmgr_psoc *psoc, + void *arg); + +/** + * ftm_time_sync_psoc_destroy_notification() - Handler for psoc destroy notify. + * @psoc: psoc which is going to be destroyed by objmgr + * @arg: argument for notification handler + * + * Deallocate and detach psoc private object. + * + * Return: QDF_STATUS + */ +QDF_STATUS +ftm_time_sync_psoc_destroy_notification(struct wlan_objmgr_psoc *psoc, + void *arg); + +QDF_STATUS ftm_time_sync_psoc_config(struct wlan_objmgr_psoc *psoc, + struct ftm_time_sync_cfg *cfg); +/** + * ftm_time_sync_is_enable() - Function to advertise feature is enabled or not + * @psoc: psoc context + * + * This function advertises whether the feature is enabled or not. + * + * Return: true if enable, false if disable + */ +bool ftm_time_sync_is_enable(struct wlan_objmgr_psoc *psoc); + +/** + * ftm_time_sync_set_enable() - Handler to enable the feature + * @psoc: psoc context + * @value: value to be set + * + * This function is used to enable the ftm time sync feature. + * The feature is enabled iff both ini and wmi service is advertised by + * firmware. + * + * Return: None + */ +void ftm_time_sync_set_enable(struct wlan_objmgr_psoc *psoc, bool value); + +/** + * ftm_time_sync_get_mode() - API to get the ftm time sync mode + * @psoc: psoc context + * + * Return: enum ftm_time_sync_mode + */ +enum ftm_time_sync_mode ftm_time_sync_get_mode(struct wlan_objmgr_psoc *psoc); + +/** + * ftm_time_sync_get_role() - API to get the ftm time sync role + * @psoc: psoc context + * + * Return: enum ftm_time_sync_role + */ +enum ftm_time_sync_role ftm_time_sync_get_role(struct wlan_objmgr_psoc *psoc); + +/** + * ftm_time_sync_send_trigger() - Handler for sending trigger cmd to FW + * @vdev: vdev for which FTM time_sync trigger cmd to be send + * + * This function sends the ftm trigger cmd to target. + * + * Return: QDF_STATUS + */ +QDF_STATUS ftm_time_sync_send_trigger(struct wlan_objmgr_vdev *vdev); + +/** + * ftm_time_sync_stop() - Handler for stopping the FTM time sync + * @vdev: vdev for which FTM time_sync feature to be stopped + * + * This function stops the ftm time sync functionality. + * + * Return: QDF_STATUS + */ +QDF_STATUS ftm_time_sync_stop(struct wlan_objmgr_vdev *vdev); + +/** + * ftm_time_sync_show() - Handler to print the offset derived + * @vdev: vdev for which offset is to be shown + * @buf: buffer in which the values to be printed + * + * Return: the number of bytes written in buf + */ +ssize_t ftm_time_sync_show(struct wlan_objmgr_vdev *vdev, char *buf); + +/** + * ftm_time_sync_update_bssid() - Update the bssid info + * @vdev: vdev context + * @bssid: bssid of connected AP + * + * Return: None + */ +void ftm_time_sync_update_bssid(struct wlan_objmgr_vdev *vdev, + struct qdf_mac_addr bssid); + +#endif /* end of _FTM_TIME_SYNC_MAIN_H_ */ diff --git a/drivers/staging/qcacld-3.0/components/ftm_time_sync/core/inc/ftm_time_sync_objmgr.h b/drivers/staging/qcacld-3.0/components/ftm_time_sync/core/inc/ftm_time_sync_objmgr.h new file mode 100644 index 000000000000..4b77c6e4f146 --- /dev/null +++ b/drivers/staging/qcacld-3.0/components/ftm_time_sync/core/inc/ftm_time_sync_objmgr.h @@ -0,0 +1,126 @@ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +/** + * DOC: This file contains various object manager related wrappers and helpers + */ + +#ifndef _FTM_TIME_SYNC_OBJMGR_H +#define _FTM_TIME_SYNC_OBJMGR_H + +#include "wlan_cmn.h" +#include "wlan_objmgr_cmn.h" +#include "wlan_objmgr_vdev_obj.h" +#include "wlan_objmgr_global_obj.h" + +/** + * ftm_time_sync_vdev_get_ref() - Wrapper to increment ftm_time_sync ref count + * @vdev: vdev object + * + * Wrapper for ftm_time_sync to increment ref count after checking valid + * object state. + * + * Return: SUCCESS/FAILURE + */ +static inline +QDF_STATUS ftm_time_sync_vdev_get_ref(struct wlan_objmgr_vdev *vdev) +{ + return wlan_objmgr_vdev_try_get_ref(vdev, FTM_TIME_SYNC_ID); +} + +/** + * ftm_time_sync_vdev_put_ref() - Wrapper to decrement ftm_time_sync ref count + * @vdev: vdev object + * + * Wrapper for ftm_time_sync to decrement ref count of vdev. + * + * Return: SUCCESS/FAILURE + */ +static inline +void ftm_time_sync_vdev_put_ref(struct wlan_objmgr_vdev *vdev) +{ + return wlan_objmgr_vdev_release_ref(vdev, FTM_TIME_SYNC_ID); +} + +/** + * ftm_time_sync_vdev_get_priv() - Wrapper to retrieve vdev priv obj + * @vdev: vdev pointer + * + * Wrapper for ftm_time_sync to get vdev private object pointer. + * + * Return: Private object of vdev + */ +static inline struct ftm_time_sync_vdev_priv * +ftm_time_sync_vdev_get_priv(struct wlan_objmgr_vdev *vdev) +{ + struct ftm_time_sync_vdev_priv *vdev_priv; + + vdev_priv = wlan_objmgr_vdev_get_comp_private_obj( + vdev, WLAN_UMAC_COMP_FTM_TIME_SYNC); + QDF_BUG(vdev_priv); + + return vdev_priv; +} + +/** + * ftm_time_sync_psoc_get_ref() - Wrapper to increment ftm_time sync ref count + * @psoc: psoc object + * + * Wrapper for ftm time sync to increment ref count after checking valid + * object state. + * + * Return: QDF_STATUS + */ +static inline +QDF_STATUS ftm_time_sync_psoc_get_ref(struct wlan_objmgr_psoc *psoc) +{ + return wlan_objmgr_psoc_try_get_ref(psoc, FTM_TIME_SYNC_ID); +} + +/** + * ftm_time_sync_psoc_put_ref() - Wrapper to decrement ftm time sync ref count + * @psoc: psoc object + * + * Wrapper for ftm time sync to decrement ref count of psoc. + * + * Return: None + */ +static inline +void ftm_time_sync_psoc_put_ref(struct wlan_objmgr_psoc *psoc) +{ + wlan_objmgr_psoc_release_ref(psoc, FTM_TIME_SYNC_ID); +} + +/** + * ftm_time_sync_psoc_get_priv() - Wrapper to retrieve psoc priv obj + * @psoc: psoc pointer + * + * Wrapper for ftm time sync to get psoc private object pointer. + * + * Return: ftm time sync psoc private object + */ +static inline struct ftm_time_sync_psoc_priv * +ftm_time_sync_psoc_get_priv(struct wlan_objmgr_psoc *psoc) +{ + struct ftm_time_sync_psoc_priv *psoc_priv; + + psoc_priv = wlan_objmgr_psoc_get_comp_private_obj( + psoc, WLAN_UMAC_COMP_FTM_TIME_SYNC); + QDF_BUG(psoc_priv); + + return psoc_priv; +} +#endif /* _FTM_TIME_SYNC_OBJMGR_H */ diff --git a/drivers/staging/qcacld-3.0/components/ftm_time_sync/core/inc/ftm_time_sync_priv.h b/drivers/staging/qcacld-3.0/components/ftm_time_sync/core/inc/ftm_time_sync_priv.h new file mode 100644 index 000000000000..850e92a789f4 --- /dev/null +++ b/drivers/staging/qcacld-3.0/components/ftm_time_sync/core/inc/ftm_time_sync_priv.h @@ -0,0 +1,96 @@ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +/** + * DOC: Declare private API which shall be used internally only + * in ftm_time_sync component. This file shall include prototypes of + * ftm_time_sync parsing and send logic. + * + * Note: This API should be never accessed out of ftm_time_sync component. + */ + +#ifndef _FTM_TIME_SYNC_PRIV_STRUCT_H_ +#define _FTM_TIME_SYNC_PRIV_STRUCT_H_ + +#include +#include +#include "ftm_time_sync_objmgr.h" +#include "wlan_ftm_time_sync_public_struct.h" + +#define WLAN_FTM_TIME_SYNC_PAIR_MAX 32 + +/** + * struct wlan_time_sync_pair - wlan time sync pair + * @qtime_master: master qtime + * @qtime_slave: slave qtime + */ +struct wlan_time_sync_pair { + uint64_t qtime_master; + uint64_t qtime_slave; +}; + +/** + * struct ftm_time_sync_vdev_priv - Private object to be stored in vdev + * @qtime_ref: qtime ref + * @mac_ref: mac time ref + * @time_pair: array of master/slave qtime pair + */ + +struct ftm_time_sync_priv { + uint64_t qtime_ref; + uint64_t mac_ref; + struct wlan_time_sync_pair time_pair[WLAN_FTM_TIME_SYNC_PAIR_MAX]; +}; + +/** + * struct ftm_time_sync_psoc_priv - Private object to be stored in psoc + * @psoc: pointer to psoc object + * @cfg_param: INI config param for ftm time sync + */ +struct ftm_time_sync_psoc_priv { + struct wlan_objmgr_psoc *psoc; + struct ftm_time_sync_cfg cfg_param; +}; + +/** + * struct ftm_time_sync_vdev_priv - Private object to be stored in vdev + * @vdev: pointer to vdev object + * @ftm_ts_priv: time sync private struct + * @rx_ops: rx operations for ftm time sync + * @tx_ops: tx operations for ftm time sync + * @ftm_time_sync_mutex: mutex to access ftm time sync priv members + * @ftm_time_sync_work: work to capture audio qtime and send it to FW + * @time_sync_interval: interval between two qtime capture + * @num_qtime_pair: number of qmaster and qslave pair derived + * @num_reads: number of times the qtime to be captured + * @valid: send qtime to FW only if this is true + * @bssid: bssid of connected AP + */ +struct ftm_time_sync_vdev_priv { + struct wlan_objmgr_vdev *vdev; + struct ftm_time_sync_priv ftm_ts_priv; + struct wlan_ftm_time_sync_rx_ops rx_ops; + struct wlan_ftm_time_sync_tx_ops tx_ops; + qdf_mutex_t ftm_time_sync_mutex; + qdf_delayed_work_t ftm_time_sync_work; + uint32_t time_sync_interval; + int num_qtime_pair; + int num_reads; + bool valid; + struct qdf_mac_addr bssid; +}; + +#endif /* End of _FTM_TIME_SYNC_PRIV_STRUCT_H_ */ diff --git a/drivers/staging/qcacld-3.0/components/ftm_time_sync/core/src/ftm_time_sync_main.c b/drivers/staging/qcacld-3.0/components/ftm_time_sync/core/src/ftm_time_sync_main.c new file mode 100644 index 000000000000..064e0de25115 --- /dev/null +++ b/drivers/staging/qcacld-3.0/components/ftm_time_sync/core/src/ftm_time_sync_main.c @@ -0,0 +1,429 @@ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +/** + * DOC: Implement various notification handlers which are accessed + * internally in ftm_time_sync component only. + */ + +#include "ftm_time_sync_main.h" +#include "target_if_ftm_time_sync.h" +#include "wlan_objmgr_vdev_obj.h" +#include + +void ftm_time_sync_set_enable(struct wlan_objmgr_psoc *psoc, bool value) +{ + struct ftm_time_sync_psoc_priv *psoc_priv; + + if (!psoc) { + ftm_time_sync_err("psoc is NULL"); + return; + } + + psoc_priv = ftm_time_sync_psoc_get_priv(psoc); + if (!psoc_priv) { + ftm_time_sync_err("psoc priv is NULL"); + return; + } + + psoc_priv->cfg_param.enable &= value; +} + +bool ftm_time_sync_is_enable(struct wlan_objmgr_psoc *psoc) +{ + struct ftm_time_sync_psoc_priv *psoc_priv; + + if (!psoc) { + ftm_time_sync_err("psoc is NULL"); + return false; + } + + psoc_priv = ftm_time_sync_psoc_get_priv(psoc); + if (!psoc_priv) { + ftm_time_sync_err("psoc priv is NULL"); + return false; + } + + return psoc_priv->cfg_param.enable; +} + +QDF_STATUS ftm_time_sync_psoc_config(struct wlan_objmgr_psoc *psoc, + struct ftm_time_sync_cfg *cfg) +{ + struct ftm_time_sync_psoc_priv *psoc_priv; + + if (!psoc) { + ftm_time_sync_err("psoc is NULL"); + return QDF_STATUS_E_FAILURE; + } + + psoc_priv = ftm_time_sync_psoc_get_priv(psoc); + if (!psoc_priv) { + ftm_time_sync_err("psoc priv is NULL"); + return QDF_STATUS_E_FAILURE; + } + + psoc_priv->cfg_param.enable = cfg->enable; + psoc_priv->cfg_param.role = cfg->role; + psoc_priv->cfg_param.mode = cfg->mode; + + return QDF_STATUS_SUCCESS; +} + +enum ftm_time_sync_mode ftm_time_sync_get_mode(struct wlan_objmgr_psoc *psoc) +{ + struct ftm_time_sync_psoc_priv *psoc_priv; + + if (!psoc) { + ftm_time_sync_err("psoc is NULL"); + return FTM_TIMESYNC_AGGREGATED_MODE; + } + + psoc_priv = ftm_time_sync_psoc_get_priv(psoc); + if (!psoc_priv) { + ftm_time_sync_err("psoc priv is NULL"); + return FTM_TIMESYNC_AGGREGATED_MODE; + } + + return psoc_priv->cfg_param.mode; +} + +enum ftm_time_sync_role ftm_time_sync_get_role(struct wlan_objmgr_psoc *psoc) +{ + struct ftm_time_sync_psoc_priv *psoc_priv; + + if (!psoc) { + ftm_time_sync_err("psoc is NULL"); + return FTM_TIMESYNC_SLAVE_ROLE; + } + + psoc_priv = ftm_time_sync_psoc_get_priv(psoc); + if (!psoc_priv) { + ftm_time_sync_err("psoc priv is NULL"); + return FTM_TIMESYNC_SLAVE_ROLE; + } + + return psoc_priv->cfg_param.role; +} + +static void ftm_time_sync_work_handler(void *arg) +{ + struct ftm_time_sync_vdev_priv *vdev_priv = arg; + struct wlan_objmgr_psoc *psoc; + qdf_device_t qdf_dev; + QDF_STATUS status; + uint8_t vdev_id; + uint64_t lpass_ts; + + if (!vdev_priv) { + ftm_time_sync_err("ftm vdev priv is Null"); + return; + } + + psoc = wlan_vdev_get_psoc(vdev_priv->vdev); + if (!psoc) { + ftm_time_sync_err("Failed to get psoc"); + return; + } + + vdev_id = wlan_vdev_get_id(vdev_priv->vdev); + + qdf_dev = wlan_psoc_get_qdf_dev(psoc); + pld_get_audio_wlan_timestamp(qdf_dev->dev, PLD_TRIGGER_NEGATIVE_EDGE, + &lpass_ts); + + qdf_mutex_acquire(&vdev_priv->ftm_time_sync_mutex); + + if (vdev_priv->num_reads) { + vdev_priv->num_reads--; + qdf_mutex_release(&vdev_priv->ftm_time_sync_mutex); + qdf_sched_delayed_work(&vdev_priv->ftm_time_sync_work, + vdev_priv->time_sync_interval); + } else { + qdf_mutex_release(&vdev_priv->ftm_time_sync_mutex); + } + + if (vdev_priv->valid) { + status = vdev_priv->tx_ops.ftm_time_sync_send_qtime( + psoc, vdev_id, lpass_ts); + if (status != QDF_STATUS_SUCCESS) + ftm_time_sync_err("send_ftm_time_sync_qtime failed %d", + status); + vdev_priv->valid = false; + } else { + vdev_priv->valid = true; + } +} + +QDF_STATUS +ftm_time_sync_vdev_create_notification(struct wlan_objmgr_vdev *vdev, void *arg) +{ + struct ftm_time_sync_vdev_priv *vdev_priv; + struct wlan_objmgr_psoc *psoc; + QDF_STATUS status; + + psoc = wlan_vdev_get_psoc(vdev); + if (!psoc) { + ftm_time_sync_err("Failed to get psoc"); + return QDF_STATUS_E_INVAL; + } + + if (!ftm_time_sync_is_enable(psoc)) + return QDF_STATUS_SUCCESS; + + vdev_priv = qdf_mem_malloc(sizeof(*vdev_priv)); + if (!vdev_priv) { + status = QDF_STATUS_E_NOMEM; + goto exit; + } + + status = wlan_objmgr_vdev_component_obj_attach( + vdev, WLAN_UMAC_COMP_FTM_TIME_SYNC, + (void *)vdev_priv, QDF_STATUS_SUCCESS); + if (QDF_IS_STATUS_ERROR(status)) { + ftm_time_sync_err("Failed to attach priv with vdev"); + goto free_vdev_priv; + } + + vdev_priv->vdev = vdev; + + qdf_create_delayed_work(&vdev_priv->ftm_time_sync_work, + ftm_time_sync_work_handler, vdev_priv); + + qdf_mutex_create(&vdev_priv->ftm_time_sync_mutex); + + target_if_ftm_time_sync_register_tx_ops(&vdev_priv->tx_ops); + target_if_ftm_time_sync_register_rx_ops(&vdev_priv->rx_ops); + + vdev_priv->rx_ops.ftm_time_sync_register_start_stop(psoc); + vdev_priv->rx_ops.ftm_time_sync_regiser_master_slave_offset(psoc); + + vdev_priv->valid = true; + + goto exit; + +free_vdev_priv: + qdf_mem_free(vdev_priv); + status = QDF_STATUS_E_INVAL; +exit: + return status; +} + +static QDF_STATUS +ftm_time_sync_deregister_wmi_events(struct wlan_objmgr_vdev *vdev) +{ + struct wlan_objmgr_psoc *psoc; + QDF_STATUS status; + + psoc = wlan_vdev_get_psoc(vdev); + if (!psoc) { + ftm_time_sync_err("Failed to get psoc"); + return QDF_STATUS_E_INVAL; + } + + status = target_if_ftm_time_sync_unregister_ev_handlers(psoc); + return status; +} + +QDF_STATUS +ftm_time_sync_vdev_destroy_notification(struct wlan_objmgr_vdev *vdev, + void *arg) +{ + struct ftm_time_sync_vdev_priv *vdev_priv = NULL; + struct wlan_objmgr_psoc *psoc; + QDF_STATUS status = QDF_STATUS_E_FAILURE; + + psoc = wlan_vdev_get_psoc(vdev); + if (!psoc) { + ftm_time_sync_err("Failed to get psoc"); + return QDF_STATUS_E_INVAL; + } + + if (!ftm_time_sync_is_enable(psoc)) + return QDF_STATUS_SUCCESS; + + vdev_priv = ftm_time_sync_vdev_get_priv(vdev); + if (!vdev_priv) { + ftm_time_sync_err("vdev priv is NULL"); + goto exit; + } + + qdf_mutex_destroy(&vdev_priv->ftm_time_sync_mutex); + qdf_cancel_delayed_work(&vdev_priv->ftm_time_sync_work); + + ftm_time_sync_deregister_wmi_events(vdev); + + status = wlan_objmgr_vdev_component_obj_detach( + vdev, WLAN_UMAC_COMP_FTM_TIME_SYNC, + (void *)vdev_priv); + if (QDF_IS_STATUS_ERROR(status)) + ftm_time_sync_err("Failed to detach priv with vdev"); + + qdf_mem_free(vdev_priv); + vdev_priv = NULL; + +exit: + return status; +} + +QDF_STATUS +ftm_time_sync_psoc_create_notification(struct wlan_objmgr_psoc *psoc, void *arg) +{ + struct ftm_time_sync_psoc_priv *psoc_priv; + QDF_STATUS status; + + psoc_priv = qdf_mem_malloc(sizeof(*psoc_priv)); + if (!psoc_priv) + return QDF_STATUS_E_NOMEM; + + status = wlan_objmgr_psoc_component_obj_attach( + psoc, WLAN_UMAC_COMP_FTM_TIME_SYNC, + psoc_priv, QDF_STATUS_SUCCESS); + if (QDF_IS_STATUS_ERROR(status)) { + ftm_time_sync_err("Failed to attach psoc component obj"); + goto free_psoc_priv; + } + + psoc_priv->psoc = psoc; + + return status; + +free_psoc_priv: + qdf_mem_free(psoc_priv); + return status; +} + +QDF_STATUS +ftm_time_sync_psoc_destroy_notification(struct wlan_objmgr_psoc *psoc, + void *arg) +{ + struct ftm_time_sync_psoc_priv *psoc_priv; + QDF_STATUS status; + + psoc_priv = ftm_time_sync_psoc_get_priv(psoc); + if (!psoc_priv) { + ftm_time_sync_err("psoc priv is NULL"); + return QDF_STATUS_E_FAILURE; + } + + status = wlan_objmgr_psoc_component_obj_detach( + psoc, WLAN_UMAC_COMP_FTM_TIME_SYNC, + psoc_priv); + if (QDF_IS_STATUS_ERROR(status)) { + ftm_time_sync_err("Failed to detach psoc component obj"); + return status; + } + + qdf_mem_free(psoc_priv); + return status; +} + +QDF_STATUS ftm_time_sync_send_trigger(struct wlan_objmgr_vdev *vdev) +{ + struct ftm_time_sync_vdev_priv *vdev_priv; + struct wlan_objmgr_psoc *psoc; + enum ftm_time_sync_mode mode; + uint8_t vdev_id; + QDF_STATUS status; + + psoc = wlan_vdev_get_psoc(vdev); + if (!psoc) { + ftm_time_sync_err("Failed to get psoc"); + return QDF_STATUS_E_INVAL; + } + + vdev_priv = ftm_time_sync_vdev_get_priv(vdev); + if (!vdev_priv) { + ftm_time_sync_err("Failed to get ftm time sync vdev_priv"); + return QDF_STATUS_E_INVAL; + } + + vdev_id = wlan_vdev_get_id(vdev_priv->vdev); + mode = ftm_time_sync_get_mode(psoc); + + status = vdev_priv->tx_ops.ftm_time_sync_send_trigger(psoc, + vdev_id, mode); + if (QDF_IS_STATUS_ERROR(status)) + ftm_time_sync_err("send_ftm_time_sync_trigger failed %d", + status); + + return QDF_STATUS_SUCCESS; +} + +QDF_STATUS ftm_time_sync_stop(struct wlan_objmgr_vdev *vdev) +{ + struct ftm_time_sync_vdev_priv *vdev_priv; + int iter; + + vdev_priv = ftm_time_sync_vdev_get_priv(vdev); + if (!vdev_priv) { + ftm_time_sync_err("Failed to get ftm time sync vdev_priv"); + return QDF_STATUS_E_INVAL; + } + + qdf_cancel_delayed_work(&vdev_priv->ftm_time_sync_work); + + for (iter = 0; iter < vdev_priv->num_qtime_pair; iter++) { + vdev_priv->ftm_ts_priv.time_pair[iter].qtime_master = 0; + vdev_priv->ftm_ts_priv.time_pair[iter].qtime_slave = 0; + } + + vdev_priv->num_qtime_pair = 0; + + return QDF_STATUS_SUCCESS; +} + +ssize_t ftm_time_sync_show(struct wlan_objmgr_vdev *vdev, char *buf) +{ + struct ftm_time_sync_vdev_priv *vdev_priv; + uint64_t q_master, q_slave; + ssize_t size = 0; + int iter; + + vdev_priv = ftm_time_sync_vdev_get_priv(vdev); + if (!vdev_priv) { + ftm_time_sync_debug("Failed to get ftm time sync vdev_priv"); + return 0; + } + + size = qdf_scnprintf(buf, PAGE_SIZE, "%s %pM\n", "BSSID", vdev_priv->bssid.bytes); + + for (iter = 0; iter < vdev_priv->num_qtime_pair; iter++) { + q_master = vdev_priv->ftm_ts_priv.time_pair[iter].qtime_master; + q_slave = vdev_priv->ftm_ts_priv.time_pair[iter].qtime_slave; + + size += qdf_scnprintf(buf + size, PAGE_SIZE, + "%s %llu %s %llu %s %lld\n", + "Qtime_master", q_master, "Qtime_slave", + q_slave, "Offset", q_slave > q_master ? + q_slave - q_master : q_master - q_slave); + } + return size; +} + +void ftm_time_sync_update_bssid(struct wlan_objmgr_vdev *vdev, + struct qdf_mac_addr bssid) +{ + struct ftm_time_sync_vdev_priv *vdev_priv; + + vdev_priv = ftm_time_sync_vdev_get_priv(vdev); + if (!vdev_priv) { + ftm_time_sync_debug("Failed to get ftm time sync vdev_priv"); + return; + } + + vdev_priv->bssid = bssid; +} diff --git a/drivers/staging/qcacld-3.0/components/ftm_time_sync/dispatcher/inc/ftm_time_sync_ucfg_api.h b/drivers/staging/qcacld-3.0/components/ftm_time_sync/dispatcher/inc/ftm_time_sync_ucfg_api.h new file mode 100644 index 000000000000..7d41260f18b7 --- /dev/null +++ b/drivers/staging/qcacld-3.0/components/ftm_time_sync/dispatcher/inc/ftm_time_sync_ucfg_api.h @@ -0,0 +1,165 @@ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +/** + * DOC: Declare public API related to the ftm time_sync called by north bound + * HDD/OSIF/LIM + */ + +#ifndef _FTM_TIME_SYNC_UCFG_API_H_ +#define _FTM_TIME_SYNC_UCFG_API_H_ + +#include +#include +#include "wlan_ftm_time_sync_public_struct.h" +#include "ftm_time_sync_objmgr.h" + +#ifdef FEATURE_WLAN_TIME_SYNC_FTM + +/** + * ucfg_ftm_time_sync_init() - FTM time sync component initialization. + * + * This function initializes the ftm time sync component and registers + * the handlers which are invoked on vdev creation. + * + * Return: For successful registration - QDF_STATUS_SUCCESS, + * else QDF_STATUS error codes. + */ +QDF_STATUS ucfg_ftm_time_sync_init(void); + +/** + * ucfg_ftm_time_sync_deinit() - FTM time sync component deinit. + * + * This function deinits ftm time sync component. + * + * Return: None + */ +void ucfg_ftm_time_sync_deinit(void); + +QDF_STATUS ucfg_ftm_time_sync_psoc_config(struct wlan_objmgr_psoc *psoc, + struct ftm_time_sync_cfg *cfg); + +/** + * ucfg_is_ftm_time_sync_enable() - FTM time sync feature enable/disable + * @psoc: psoc context + * + * This function advertises whether the ftm time sync feature is enabled or not + * + * Return: true if enable else false + */ +bool ucfg_is_ftm_time_sync_enable(struct wlan_objmgr_psoc *psoc); + +/** + * ucfg_ftm_time_sync_set_enable() - FTM time sync feature set enable/disable + * @psoc: psoc context + * @value: value to be set + * + * This function enables/disables the feature. + * + * Return: None + */ +void ucfg_ftm_time_sync_set_enable(struct wlan_objmgr_psoc *psoc, bool value); + +/** + * ucfg_ftm_time_sync_update_sta_connect_state() - Handler for STA state change + * @vdev: STA vdev + * @state: connected/disconnected state + * @bssid: bssid of connected AP + * + * This function triggers the FTM time sync feature in case of connection and + * stops the ftm sync feature in case of disconnection. + * + * Return: None + */ +void +ucfg_ftm_time_sync_update_sta_connect_state(struct wlan_objmgr_vdev *vdev, + enum ftm_time_sync_sta_state state, + struct qdf_mac_addr bssid); + +/** + * ucfg_ftm_time_sync_update_bss_state() - Handler to notify bss start/stop + * @vdev: SAP vdev + * @ap_state: BSS start/stop state + * + * This function triggers the FTM time sync feature in case of bss start and + * stops the ftm sync feature in case of bss stop. + * + * Return: None. + */ +void ucfg_ftm_time_sync_update_bss_state(struct wlan_objmgr_vdev *vdev, + enum ftm_time_sync_bss_state ap_state); + +/** + * ucfg_ftm_time_sync_show() - Show the ftm time sync offset values derived + * @vdev: vdev context + * @buf: buffer in which the values to be written + * + * This function prints the offset values derived after ftm time sync + * between the qtime of STA(slave) and connected SAP(master). + * + * Return: number of bytes written in buffer + */ +ssize_t ucfg_ftm_time_sync_show(struct wlan_objmgr_vdev *vdev, char *buf); +#else + +static inline +QDF_STATUS ucfg_ftm_time_sync_init(void) +{ + return QDF_STATUS_SUCCESS; +} + +static inline +void ucfg_ftm_time_sync_deinit(void) +{ +} + +static inline +QDF_STATUS ucfg_ftm_time_sync_psoc_config(struct wlan_objmgr_psoc *psoc, + struct ftm_time_sync_cfg *cfg) +{ + return QDF_STATUS_SUCCESS; +} + +static inline +bool ucfg_is_ftm_time_sync_enable(struct wlan_objmgr_psoc *psoc) +{ + return false; +} + +static inline +void ucfg_ftm_time_sync_set_enable(struct wlan_objmgr_psoc *psoc, bool value) +{ +} + +static inline void +ucfg_ftm_time_sync_update_sta_connect_state(struct wlan_objmgr_vdev *vdev, + enum ftm_time_sync_sta_state state) +{ +} + +static inline void +ucfg_ftm_time_sync_update_bss_state(struct wlan_objmgr_vdev *vdev, + enum ftm_time_sync_bss_state ap_state) +{ +} + +static inline +ssize_t ucfg_ftm_time_sync_show(struct wlan_objmgr_vdev *vdev, char *buf) +{ + return 0; +} +#endif /* FEATURE_WLAN_TIME_SYNC_FTM */ +#endif /* _FTM_TIME_SYNC_UCFG_API_H_ */ diff --git a/drivers/staging/qcacld-3.0/components/ftm_time_sync/dispatcher/inc/wlan_ftm_time_sync_public_struct.h b/drivers/staging/qcacld-3.0/components/ftm_time_sync/dispatcher/inc/wlan_ftm_time_sync_public_struct.h new file mode 100644 index 000000000000..19b03d4cfc79 --- /dev/null +++ b/drivers/staging/qcacld-3.0/components/ftm_time_sync/dispatcher/inc/wlan_ftm_time_sync_public_struct.h @@ -0,0 +1,112 @@ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +/** + * DOC: Declare various struct, macros which are used for obj mgmt in ftm time + * sync. + * + * Note: This file shall not contain public API's prototype/declarations. + * + */ + +#ifndef _WLAN_TIME_SYNC_FTM_PUBLIC_STRUCT_H_ +#define _WLAN_TIME_SYNC_FTM_PUBLIC_STRUCT_H_ + +struct wlan_objmgr_psoc; + +/** + * enum ftm_time_sync_mode - ftm time sync modes + * @FTM_TIMESYNC_AGGREGATED_MODE: Ftm time sync aggregated mode + * Only one aggregated offset is provided + * @FTM_TIMESYNC_BURST_MODE: Ftm time sync burst mode, offset for each FTM + * frame is provided + */ +enum ftm_time_sync_mode { + FTM_TIMESYNC_AGGREGATED_MODE, + FTM_TIMESYNC_BURST_MODE, +}; + +/** + * enum ftm_time_sync_role - ftm time sync role + * @FTM_TIMESYNC_SLAVE_ROLE: Slave/STA role + * @FTM_TIMESYNC_MASTER_ROLE: Master/SAP role + */ +enum ftm_time_sync_role { + FTM_TIMESYNC_SLAVE_ROLE, + FTM_TIMESYNC_MASTER_ROLE, +}; + +/** + * struct ftm_time_sync_cfg - Cfg ini param for FTM time sync + * @enable: FTM time_sync feature enable/disable + * @mode: Aggregated/burst mode applicable iff enable = 1 + * @role: Slave/Master Role applicable iff enable = 1 + */ +struct ftm_time_sync_cfg { + bool enable; + enum ftm_time_sync_mode mode; + enum ftm_time_sync_role role; +}; + +/** + * enum ftm_time_sync_sta_state - ftm time sync sta states + * @FTM_TIME_SYNC_STA_CONNECTED: STA connected to AP + * @FTM_TIME_SYNC_STA_DISCONNECTED: STA disconnected + */ +enum ftm_time_sync_sta_state { + FTM_TIME_SYNC_STA_CONNECTED, + FTM_TIME_SYNC_STA_DISCONNECTED, +}; + +/** + * enum ftm_time_sync_bss_state - ftm time sync bss states + * @FTM_TIME_SYNC_BSS_STARTED: BSS started + * @FTM_TIME_SYNC_BSS_STOPPED: BSS stopped + */ +enum ftm_time_sync_bss_state { + FTM_TIME_SYNC_BSS_STARTED, + FTM_TIME_SYNC_BSS_STOPPED, +}; + +/** + * struct wlan_ftm_time_sync_tx_ops - structure of tx operation function + * pointers for ftm time_sync component + * @ftm_time_sync_send_qtime: send qtime wmi cmd to FW + * @ftm_time_sync_send_trigger: send ftm time sync trigger cmd + * + */ +struct wlan_ftm_time_sync_tx_ops { + QDF_STATUS (*ftm_time_sync_send_qtime)(struct wlan_objmgr_psoc *psoc, + uint32_t vdev_id, + uint64_t lpass_ts); + QDF_STATUS (*ftm_time_sync_send_trigger)(struct wlan_objmgr_psoc *psoc, + uint32_t vdev_id, bool mode); +}; + +/** + * struct wlan_ftm_time_sync_rx_ops - structure of rx operation function + * pointers for ftm time_sync component + * @ftm_time_sync_register_start_stop: register ftm time_sync start stop event + * @ftm_time_sync_regiser_master_slave_offset: register master slave qtime + * offset event + */ +struct wlan_ftm_time_sync_rx_ops { + QDF_STATUS (*ftm_time_sync_register_start_stop) + (struct wlan_objmgr_psoc *psoc); + QDF_STATUS (*ftm_time_sync_regiser_master_slave_offset) + (struct wlan_objmgr_psoc *psoc); +}; +#endif /*_WLAN_TIME_SYNC_FTM_PUBLIC_STRUCT_H_ */ diff --git a/drivers/staging/qcacld-3.0/components/ftm_time_sync/dispatcher/inc/wlan_ftm_time_sync_tgt_api.h b/drivers/staging/qcacld-3.0/components/ftm_time_sync/dispatcher/inc/wlan_ftm_time_sync_tgt_api.h new file mode 100644 index 000000000000..17f4c5707427 --- /dev/null +++ b/drivers/staging/qcacld-3.0/components/ftm_time_sync/dispatcher/inc/wlan_ftm_time_sync_tgt_api.h @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +/** + * DOC: Declares public API for ftm time sync to interact with target/WMI + */ + +#ifndef _WLAN_FTM_TIME_SYNC_TGT_API_H_ +#define _WLAN_FTM_TIME_SYNC_TGT_API_H_ + +#include + +struct wlan_objmgr_psoc; +struct ftm_time_sync_start_stop_params; +struct ftm_time_sync_offset; + +/** + * tgt_ftm_ts_start_stop_evt() - receive start/stop ftm event + * from target if + * @psoc: objmgr psoc object + * @param: start/stop parameters + * + * Return: QDF_STATUS + */ +QDF_STATUS +tgt_ftm_ts_start_stop_evt(struct wlan_objmgr_psoc *psoc, + struct ftm_time_sync_start_stop_params *param); + +/** + * tgt_ftm_ts_offset_evt() - receive offset ftm event from target if + * @psoc: objmgr psoc object + * @param: offset parameters + * + * Return: QDF_STATUS + */ +QDF_STATUS tgt_ftm_ts_offset_evt(struct wlan_objmgr_psoc *psoc, + struct ftm_time_sync_offset *param); + +#endif /*_WLAN_FTM_TIME_SYNC_TGT_API_H_ */ diff --git a/drivers/staging/qcacld-3.0/components/ftm_time_sync/dispatcher/src/ftm_time_sync_ucfg_api.c b/drivers/staging/qcacld-3.0/components/ftm_time_sync/dispatcher/src/ftm_time_sync_ucfg_api.c new file mode 100644 index 000000000000..277bf916219c --- /dev/null +++ b/drivers/staging/qcacld-3.0/components/ftm_time_sync/dispatcher/src/ftm_time_sync_ucfg_api.c @@ -0,0 +1,182 @@ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +/** + * DOC: Public API implementation of ftm time_sync called by north bound iface. + */ + +#include "ftm_time_sync_ucfg_api.h" +#include "ftm_time_sync_main.h" +#include + +QDF_STATUS ucfg_ftm_time_sync_init(void) +{ + QDF_STATUS status; + + status = wlan_objmgr_register_psoc_create_handler( + WLAN_UMAC_COMP_FTM_TIME_SYNC, + ftm_time_sync_psoc_create_notification, + NULL); + if (QDF_IS_STATUS_ERROR(status)) { + ftm_time_sync_err("Failed to register psoc create handler"); + return status; + } + + status = wlan_objmgr_register_psoc_destroy_handler( + WLAN_UMAC_COMP_FTM_TIME_SYNC, + ftm_time_sync_psoc_destroy_notification, + NULL); + if (QDF_IS_STATUS_ERROR(status)) { + ftm_time_sync_err("Failed to register psoc delete handler"); + goto fail_destroy_psoc; + } + + status = wlan_objmgr_register_vdev_create_handler( + WLAN_UMAC_COMP_FTM_TIME_SYNC, + ftm_time_sync_vdev_create_notification, NULL); + if (QDF_IS_STATUS_ERROR(status)) { + ftm_time_sync_err("Failed to register vdev create handler"); + goto fail_create_vdev; + } + + status = wlan_objmgr_register_vdev_destroy_handler( + WLAN_UMAC_COMP_FTM_TIME_SYNC, + ftm_time_sync_vdev_destroy_notification, NULL); + if (QDF_IS_STATUS_ERROR(status)) { + ftm_time_sync_err("Failed to register vdev destroy handler"); + goto fail_destroy_vdev; + } + return status; + +fail_destroy_vdev: + wlan_objmgr_unregister_vdev_create_handler( + WLAN_UMAC_COMP_FTM_TIME_SYNC, + ftm_time_sync_vdev_create_notification, NULL); + +fail_create_vdev: + wlan_objmgr_unregister_psoc_destroy_handler( + WLAN_UMAC_COMP_FTM_TIME_SYNC, + ftm_time_sync_psoc_destroy_notification, NULL); + +fail_destroy_psoc: + wlan_objmgr_unregister_psoc_create_handler( + WLAN_UMAC_COMP_FTM_TIME_SYNC, + ftm_time_sync_psoc_create_notification, NULL); + + return status; +} + +void ucfg_ftm_time_sync_deinit(void) +{ + QDF_STATUS status; + + status = wlan_objmgr_unregister_vdev_destroy_handler( + WLAN_UMAC_COMP_FTM_TIME_SYNC, + ftm_time_sync_vdev_destroy_notification, + NULL); + if (QDF_IS_STATUS_ERROR(status)) + ftm_time_sync_err("Failed to unregister vdev delete handler"); + + status = wlan_objmgr_unregister_vdev_create_handler( + WLAN_UMAC_COMP_FTM_TIME_SYNC, + ftm_time_sync_vdev_create_notification, NULL); + if (!QDF_IS_STATUS_ERROR(status)) + ftm_time_sync_err("Failed to unregister vdev create handler"); + + status = wlan_objmgr_unregister_psoc_destroy_handler( + WLAN_UMAC_COMP_FTM_TIME_SYNC, + ftm_time_sync_psoc_destroy_notification, + NULL); + if (QDF_IS_STATUS_ERROR(status)) + ftm_time_sync_err("Failed to unregister psoc destroy handler"); + + status = wlan_objmgr_unregister_psoc_create_handler( + WLAN_UMAC_COMP_FTM_TIME_SYNC, + ftm_time_sync_psoc_create_notification, + NULL); + if (QDF_IS_STATUS_ERROR(status)) + ftm_time_sync_err("Failed to unregister psoc create handler"); +} + +QDF_STATUS ucfg_ftm_time_sync_psoc_config(struct wlan_objmgr_psoc *psoc, + struct ftm_time_sync_cfg *cfg) +{ + return ftm_time_sync_psoc_config(psoc, cfg); +} + +bool ucfg_is_ftm_time_sync_enable(struct wlan_objmgr_psoc *psoc) +{ + return ftm_time_sync_is_enable(psoc); +} + +void ucfg_ftm_time_sync_set_enable(struct wlan_objmgr_psoc *psoc, bool enable) +{ + return ftm_time_sync_set_enable(psoc, enable); +} + +void ucfg_ftm_time_sync_update_sta_connect_state( + struct wlan_objmgr_vdev *vdev, + enum ftm_time_sync_sta_state sta_state, + struct qdf_mac_addr bssid) +{ + struct wlan_objmgr_psoc *psoc; + enum ftm_time_sync_role role; + + psoc = wlan_vdev_get_psoc(vdev); + if (!psoc) { + ftm_time_sync_err("Failed to get psoc"); + return; + } + + role = ftm_time_sync_get_role(psoc); + if (role == FTM_TIMESYNC_SLAVE_ROLE) { + if (sta_state == FTM_TIME_SYNC_STA_CONNECTED) + ftm_time_sync_send_trigger(vdev); + else + ftm_time_sync_stop(vdev); + + ftm_time_sync_update_bssid(vdev, bssid); + } +} + +void ucfg_ftm_time_sync_update_bss_state(struct wlan_objmgr_vdev *vdev, + enum ftm_time_sync_bss_state ap_state) +{ + struct wlan_objmgr_psoc *psoc; + enum ftm_time_sync_role role; + + psoc = wlan_vdev_get_psoc(vdev); + if (!psoc) { + ftm_time_sync_err("Failed to get psoc"); + return; + } + + if (!ftm_time_sync_is_enable(psoc)) + return; + + role = ftm_time_sync_get_role(psoc); + if (role == FTM_TIMESYNC_MASTER_ROLE) { + if (ap_state == FTM_TIME_SYNC_BSS_STARTED) + ftm_time_sync_send_trigger(vdev); + else + ftm_time_sync_stop(vdev); + } +} + +ssize_t ucfg_ftm_time_sync_show(struct wlan_objmgr_vdev *vdev, char *buf) +{ + return ftm_time_sync_show(vdev, buf); +} diff --git a/drivers/staging/qcacld-3.0/components/ftm_time_sync/dispatcher/src/wlan_ftm_time_sync_tgt_api.c b/drivers/staging/qcacld-3.0/components/ftm_time_sync/dispatcher/src/wlan_ftm_time_sync_tgt_api.c new file mode 100644 index 000000000000..10a9cec6819d --- /dev/null +++ b/drivers/staging/qcacld-3.0/components/ftm_time_sync/dispatcher/src/wlan_ftm_time_sync_tgt_api.c @@ -0,0 +1,103 @@ +/* + *Copyright (c) 2020, The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +/** + * DOC: Implements public API for ftm time sync to interact with target/WMI + */ + +#include "wlan_ftm_time_sync_tgt_api.h" +#include "ftm_time_sync_main.h" +#include "wlan_ftm_time_sync_public_struct.h" +#include + +QDF_STATUS +tgt_ftm_ts_start_stop_evt(struct wlan_objmgr_psoc *psoc, + struct ftm_time_sync_start_stop_params *param) +{ + struct wlan_objmgr_vdev *vdev; + struct ftm_time_sync_vdev_priv *vdev_priv; + uint8_t vdev_id; + + vdev_id = param->vdev_id; + + vdev = wlan_objmgr_get_vdev_by_id_from_psoc(psoc, vdev_id, + FTM_TIME_SYNC_ID); + if (!vdev) { + ftm_time_sync_err("failed to get vdev"); + return QDF_STATUS_E_FAILURE; + } + + vdev_priv = ftm_time_sync_vdev_get_priv(vdev); + + qdf_mutex_acquire(&vdev_priv->ftm_time_sync_mutex); + + vdev_priv->time_sync_interval = param->timer_interval; + vdev_priv->num_reads = param->num_reads * 2; + + if (vdev_priv->num_reads && vdev_priv->time_sync_interval) { + vdev_priv->num_reads--; + qdf_mutex_release(&vdev_priv->ftm_time_sync_mutex); + qdf_sched_delayed_work(&vdev_priv->ftm_time_sync_work, + param->timer_interval); + } else if (vdev_priv->time_sync_interval == 0) { + qdf_mutex_release(&vdev_priv->ftm_time_sync_mutex); + vdev_priv->ftm_ts_priv.qtime_ref = param->qtime; + vdev_priv->ftm_ts_priv.mac_ref = param->mac_time; + qdf_cancel_delayed_work(&vdev_priv->ftm_time_sync_work); + } else { + qdf_mutex_release(&vdev_priv->ftm_time_sync_mutex); + } + + ftm_time_sync_vdev_put_ref(vdev); + + return QDF_STATUS_SUCCESS; +} + +QDF_STATUS tgt_ftm_ts_offset_evt(struct wlan_objmgr_psoc *psoc, + struct ftm_time_sync_offset *param) +{ + struct ftm_time_sync_vdev_priv *vdev_priv; + struct wlan_objmgr_vdev *vdev; + uint8_t vdev_id; + int iter; + + vdev_id = param->vdev_id; + + vdev = wlan_objmgr_get_vdev_by_id_from_psoc(psoc, vdev_id, + FTM_TIME_SYNC_ID); + if (!vdev) { + ftm_time_sync_err("failed to get vdev"); + return QDF_STATUS_E_FAILURE; + } + + vdev_priv = ftm_time_sync_vdev_get_priv(vdev); + + vdev_priv->num_qtime_pair = param->num_qtime < + FTM_TIME_SYNC_QTIME_PAIR_MAX ? param->num_qtime : + FTM_TIME_SYNC_QTIME_PAIR_MAX; + + for (iter = 0; iter < vdev_priv->num_qtime_pair; iter++) { + vdev_priv->ftm_ts_priv.time_pair[iter].qtime_master = + param->pairs[iter].qtime_master; + vdev_priv->ftm_ts_priv.time_pair[iter].qtime_slave = + param->pairs[iter].qtime_slave; + } + + ftm_time_sync_vdev_put_ref(vdev); + + return QDF_STATUS_SUCCESS; +} + diff --git a/drivers/staging/qcacld-3.0/components/ipa/core/src/wlan_ipa_core.c b/drivers/staging/qcacld-3.0/components/ipa/core/src/wlan_ipa_core.c index 2db32b488427..a7ab5b05575b 100644 --- a/drivers/staging/qcacld-3.0/components/ipa/core/src/wlan_ipa_core.c +++ b/drivers/staging/qcacld-3.0/components/ipa/core/src/wlan_ipa_core.c @@ -243,9 +243,10 @@ static void wlan_ipa_send_pkt_to_tl( qdf_spin_lock_bh(&ipa_ctx->q_lock); /* get free Tx desc and assign ipa_tx_desc pointer */ - if (qdf_list_remove_front(&ipa_ctx->tx_desc_list, - (qdf_list_node_t **)&tx_desc) == - QDF_STATUS_SUCCESS) { + if (ipa_ctx->tx_desc_list.count && + qdf_list_remove_front(&ipa_ctx->tx_desc_list, + (qdf_list_node_t **)&tx_desc) == + QDF_STATUS_SUCCESS) { tx_desc->ipa_tx_desc_ptr = ipa_tx_desc; ipa_ctx->stats.num_tx_desc_q_cnt++; qdf_spin_unlock_bh(&ipa_ctx->q_lock); @@ -301,26 +302,39 @@ static inline bool wlan_ipa_wdi_is_smmu_enabled(struct wlan_ipa_priv *ipa_ctx, return ipa_ctx->is_smmu_enabled && qdf_mem_smmu_s1_enabled(osdev); } -static inline QDF_STATUS wlan_ipa_wdi_setup(struct wlan_ipa_priv *ipa_ctx, - qdf_device_t osdev) +static inline QDF_STATUS +wlan_ipa_wdi_setup(struct wlan_ipa_priv *ipa_ctx, + qdf_device_t osdev) { - qdf_ipa_sys_connect_params_t sys_in[WLAN_IPA_MAX_IFACE]; + qdf_ipa_sys_connect_params_t *sys_in = NULL; int i; + QDF_STATUS qdf_status = QDF_STATUS_SUCCESS; + + sys_in = qdf_mem_malloc(sizeof(*sys_in) * WLAN_IPA_MAX_IFACE); + if (!sys_in) { + ipa_err("sys_in allocation failed"); + return QDF_STATUS_E_NOMEM; + } for (i = 0; i < WLAN_IPA_MAX_IFACE; i++) - qdf_mem_copy(&sys_in[i], + qdf_mem_copy(sys_in + i, &ipa_ctx->sys_pipe[i].ipa_sys_params, sizeof(qdf_ipa_sys_connect_params_t)); - return cdp_ipa_setup(ipa_ctx->dp_soc, ipa_ctx->dp_pdev, - wlan_ipa_i2w_cb, wlan_ipa_w2i_cb, - wlan_ipa_wdi_meter_notifier_cb, - ipa_ctx->config->desc_size, - ipa_ctx, wlan_ipa_is_rm_enabled(ipa_ctx->config), - &ipa_ctx->tx_pipe_handle, - &ipa_ctx->rx_pipe_handle, - wlan_ipa_wdi_is_smmu_enabled(ipa_ctx, osdev), - sys_in); + qdf_status = cdp_ipa_setup(ipa_ctx->dp_soc, ipa_ctx->dp_pdev, + wlan_ipa_i2w_cb, wlan_ipa_w2i_cb, + wlan_ipa_wdi_meter_notifier_cb, + ipa_ctx->config->desc_size, + ipa_ctx, + wlan_ipa_is_rm_enabled(ipa_ctx->config), + &ipa_ctx->tx_pipe_handle, + &ipa_ctx->rx_pipe_handle, + wlan_ipa_wdi_is_smmu_enabled(ipa_ctx, osdev), + sys_in); + + qdf_mem_free(sys_in); + + return qdf_status; } #ifdef FEATURE_METERING @@ -1040,7 +1054,7 @@ QDF_STATUS wlan_ipa_uc_disable_pipes(struct wlan_ipa_priv *ipa_ctx) ipa_debug("enter"); if (ipa_ctx->ipa_pipes_down) { - ipa_warn("IPA WDI Pipes are already deactivated"); + ipa_info("IPA WDI Pipes are already deactivated"); goto end; } @@ -1112,7 +1126,7 @@ static bool wlan_ipa_uc_find_add_assoc_sta(struct wlan_ipa_priv *ipa_ctx, } } if (!sta_add && !sta_found) { - ipa_err("STA ID %d does not exist, cannot delete", sta_id); + ipa_info("STA ID %d does not exist, cannot delete", sta_id); return sta_found; } if (!sta_add) { @@ -1219,8 +1233,16 @@ static QDF_STATUS wlan_ipa_setup_iface(struct wlan_ipa_priv *ipa_ctx, if (device_mode == QDF_SAP_MODE) { for (i = 0; i < WLAN_IPA_MAX_IFACE; i++) { iface_context = &(ipa_ctx->iface_context[i]); - if (iface_context->dev == net_dev) - return QDF_STATUS_SUCCESS; + if (iface_context->dev == net_dev) { + if (iface_context->device_mode == + device_mode) + return QDF_STATUS_SUCCESS; + + ipa_err("Obsolete iface %u found, device_mode %u, will remove it.", + i, + iface_context->device_mode); + wlan_ipa_cleanup_iface(iface_context); + } } } @@ -1556,12 +1578,12 @@ static QDF_STATUS __wlan_ipa_wlan_evt(qdf_netdev_t net_dev, uint8_t device_mode, type == QDF_IPA_AP_DISCONNECT) { for (i = 0; i < WLAN_IPA_MAX_IFACE; i++) { iface_ctx = &ipa_ctx->iface_context[i]; - - if (iface_ctx->dev == net_dev) + if (iface_ctx->dev == net_dev) { + wlan_ipa_cleanup_iface( + iface_ctx); break; + } } - if (iface_ctx) - wlan_ipa_cleanup_iface(iface_ctx); } return QDF_STATUS_SUCCESS; @@ -1657,8 +1679,9 @@ static QDF_STATUS __wlan_ipa_wlan_evt(qdf_netdev_t net_dev, uint8_t device_mode, struct wlan_ipa_iface_context *iface; qdf_mutex_release(&ipa_ctx->event_lock); - ipa_err("%s: Evt: %d, STA already disconnected", - msg_ex->name, QDF_IPA_MSG_META_MSG_TYPE(&meta)); + ipa_info("%s: Evt: %d, STA already disconnected", + msg_ex->name, + QDF_IPA_MSG_META_MSG_TYPE(&meta)); iface = wlan_ipa_get_iface(ipa_ctx, QDF_STA_MODE); if (iface && (iface->dev == net_dev)) @@ -1753,12 +1776,11 @@ static QDF_STATUS __wlan_ipa_wlan_evt(qdf_netdev_t net_dev, uint8_t device_mode, for (i = 0; i < WLAN_IPA_MAX_IFACE; i++) { iface_ctx = &ipa_ctx->iface_context[i]; - - if (iface_ctx->dev == net_dev) + if (iface_ctx->dev == net_dev) { + wlan_ipa_cleanup_iface(iface_ctx); break; + } } - if (i < WLAN_IPA_MAX_IFACE) - wlan_ipa_cleanup_iface(iface_ctx); qdf_mutex_release(&ipa_ctx->event_lock); break; @@ -1810,6 +1832,7 @@ static QDF_STATUS __wlan_ipa_wlan_evt(qdf_netdev_t net_dev, uint8_t device_mode, return status; } + ipa_info("first sap client connected"); } ipa_ctx->sap_num_connected_sta++; @@ -1848,7 +1871,7 @@ static QDF_STATUS __wlan_ipa_wlan_evt(qdf_netdev_t net_dev, uint8_t device_mode, } ipa_ctx->stats.num_send_msg++; - ipa_info("sap_num_connected_sta=%d", + ipa_debug("sap_num_connected_sta=%d", ipa_ctx->sap_num_connected_sta); return QDF_STATUS_SUCCESS; @@ -1863,17 +1886,17 @@ static QDF_STATUS __wlan_ipa_wlan_evt(qdf_netdev_t net_dev, uint8_t device_mode, qdf_mutex_acquire(&ipa_ctx->event_lock); if (!ipa_ctx->sap_num_connected_sta) { qdf_mutex_release(&ipa_ctx->event_lock); - ipa_err("%s: Evt: %d, Client already disconnected", - msg_ex->name, - QDF_IPA_MSG_META_MSG_TYPE(&meta)); + ipa_debug("%s: Evt: %d, Client already disconnected", + msg_ex->name, + QDF_IPA_MSG_META_MSG_TYPE(&meta)); return QDF_STATUS_SUCCESS; } if (!wlan_ipa_uc_find_add_assoc_sta(ipa_ctx, false, sta_id, mac_addr)) { qdf_mutex_release(&ipa_ctx->event_lock); - ipa_err("%s: STA ID %d NOT found, not valid", - msg_ex->name, sta_id); + ipa_debug("%s: STA ID %d NOT found, not valid", + msg_ex->name, sta_id); return QDF_STATUS_SUCCESS; } @@ -1896,6 +1919,7 @@ static QDF_STATUS __wlan_ipa_wlan_evt(qdf_netdev_t net_dev, uint8_t device_mode, } else { wlan_ipa_uc_handle_last_discon(ipa_ctx); } + ipa_info("last sap client disconnected"); } if (wlan_ipa_uc_sta_is_enabled(ipa_ctx->config) && @@ -1911,8 +1935,8 @@ static QDF_STATUS __wlan_ipa_wlan_evt(qdf_netdev_t net_dev, uint8_t device_mode, qdf_mutex_release(&ipa_ctx->event_lock); } - ipa_info("sap_num_connected_sta=%d", - ipa_ctx->sap_num_connected_sta); + ipa_debug("sap_num_connected_sta=%d", + ipa_ctx->sap_num_connected_sta); break; default: @@ -2079,8 +2103,9 @@ static inline void wlan_ipa_free_tx_desc_list(struct wlan_ipa_priv *ipa_ctx) qdf_ipa_rx_data_t *ipa_tx_desc; qdf_list_node_t *node; - while (qdf_list_remove_front(&ipa_ctx->tx_desc_list, &node) == - QDF_STATUS_SUCCESS) { + while (ipa_ctx->tx_desc_list.count && + qdf_list_remove_front(&ipa_ctx->tx_desc_list, &node) == + QDF_STATUS_SUCCESS) { tmp_desc = qdf_container_of(node, struct wlan_ipa_tx_desc, node); @@ -2445,27 +2470,33 @@ QDF_STATUS wlan_ipa_setup(struct wlan_ipa_priv *ipa_ctx, ipa_ctx->ipa_pipes_down = true; ipa_ctx->pipes_down_in_progress = false; ipa_ctx->wdi_enabled = false; - /* Setup IPA system pipes */ - if (wlan_ipa_uc_sta_is_enabled(ipa_ctx->config)) { - ret = wlan_ipa_setup_sys_pipe(ipa_ctx); - if (ret) - goto fail_create_sys_pipe; - - qdf_create_work(0, &ipa_ctx->mcc_work, - wlan_ipa_mcc_work_handler, ipa_ctx); - } status = wlan_ipa_wdi_init(ipa_ctx); - if (status == QDF_STATUS_E_BUSY) - status = wlan_ipa_uc_send_wdi_control_msg(false); - if (status != QDF_STATUS_SUCCESS) { + if (status == QDF_STATUS_SUCCESS) { + /* Setup IPA system pipes */ + if (wlan_ipa_uc_sta_is_enabled(ipa_ctx->config)) { + ret = wlan_ipa_setup_sys_pipe(ipa_ctx); + if (ret) + goto ipa_wdi_destroy; + + qdf_create_work(0, &ipa_ctx->mcc_work, + wlan_ipa_mcc_work_handler, + ipa_ctx); + } + } else if (status == QDF_STATUS_E_BUSY) { + ret = wlan_ipa_uc_send_wdi_control_msg(false); + if (ret) { + ipa_err("IPA WDI msg send failed: ret=%d", ret); + goto ipa_wdi_destroy; + } + } else { ipa_err("IPA WDI init failed: ret=%d", status); - goto fail_create_sys_pipe; + goto ipa_wdi_destroy; } } else { ret = wlan_ipa_setup_sys_pipe(ipa_ctx); if (ret) - goto fail_create_sys_pipe; + goto ipa_wdi_destroy; } qdf_event_create(&ipa_ctx->ipa_resource_comp); @@ -2474,7 +2505,7 @@ QDF_STATUS wlan_ipa_setup(struct wlan_ipa_priv *ipa_ctx, return QDF_STATUS_SUCCESS; -fail_create_sys_pipe: +ipa_wdi_destroy: wlan_ipa_wdi_destroy_rm(ipa_ctx); fail_setup_rm: @@ -2624,6 +2655,18 @@ static void wlan_ipa_uc_loaded_handler(struct wlan_ipa_priv *ipa_ctx) ipa_err("qdf_dev is null"); return; } + + if (wlan_ipa_uc_sta_is_enabled(ipa_ctx->config)) { + /* Setup IPA system pipes */ + status = wlan_ipa_setup_sys_pipe(ipa_ctx); + if (status) { + ipa_err("Fail to setup sys pipes (status=%d)", status); + return; + } + qdf_create_work(0, &ipa_ctx->mcc_work, + wlan_ipa_mcc_work_handler, ipa_ctx); + } + /* Connect pipe */ status = wlan_ipa_wdi_setup(ipa_ctx, qdf_dev); if (status) { @@ -3033,12 +3076,11 @@ void wlan_ipa_cleanup_dev_iface(struct wlan_ipa_priv *ipa_ctx, for (i = 0; i < WLAN_IPA_MAX_IFACE; i++) { iface_ctx = &ipa_ctx->iface_context[i]; - if (iface_ctx->dev == net_dev) + if (iface_ctx->dev == net_dev) { + wlan_ipa_cleanup_iface(iface_ctx); break; + } } - - if (iface_ctx) - wlan_ipa_cleanup_iface(iface_ctx); } void wlan_ipa_uc_ssr_cleanup(struct wlan_ipa_priv *ipa_ctx) diff --git a/drivers/staging/qcacld-3.0/components/ipa/core/src/wlan_ipa_stats.c b/drivers/staging/qcacld-3.0/components/ipa/core/src/wlan_ipa_stats.c index 468def3d4468..a8dfb379c07f 100644 --- a/drivers/staging/qcacld-3.0/components/ipa/core/src/wlan_ipa_stats.c +++ b/drivers/staging/qcacld-3.0/components/ipa/core/src/wlan_ipa_stats.c @@ -941,6 +941,9 @@ static void __wlan_ipa_wdi_meter_notifier_cb(qdf_ipa_wdi_meter_evt_type_t evt, ipa_ctx->ipa_quota_rsp.success; } break; + + default: + break; } } diff --git a/drivers/staging/qcacld-3.0/components/mlme/core/inc/wlan_mlme_main.h b/drivers/staging/qcacld-3.0/components/mlme/core/inc/wlan_mlme_main.h index 9b69c61d6536..094a8004f385 100644 --- a/drivers/staging/qcacld-3.0/components/mlme/core/inc/wlan_mlme_main.h +++ b/drivers/staging/qcacld-3.0/components/mlme/core/inc/wlan_mlme_main.h @@ -32,14 +32,43 @@ #define mlme_info(params...) QDF_TRACE_INFO(QDF_MODULE_ID_MLME, params) #define mlme_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_MLME, params) +/** + * struct wlan_ies - Generic WLAN Information Element(s) format + * @len: Total length of the IEs + * @data: IE data + */ +struct wlan_ies { + uint16_t len; + uint8_t *data; +}; + +/** + * struct wlan_disconnect_info - WLAN Disconnection Information + * @self_discon_ies: Disconnect IEs to be sent in deauth/disassoc frames + * originated from driver + * @peer_discon_ies: Disconnect IEs received in deauth/disassoc frames from peer + * @discon_reason: Disconnect reason as per enum eSirMacReasonCodes + * @from_ap: True if the disconnection is initiated from AP + */ +struct wlan_disconnect_info { + struct wlan_ies self_discon_ies; + struct wlan_ies peer_discon_ies; + uint32_t discon_reason; + bool from_ap; +}; + /** * struct peer_mlme_priv_obj - peer MLME component object * @ucast_key_cipher: unicast crypto type. * @is_pmf_enabled: True if PMF is enabled + * @last_assoc_received_time: last assoc received time + * @last_disassoc_deauth_received_time: last disassoc/deauth received time */ struct peer_mlme_priv_obj { uint32_t ucast_key_cipher; bool is_pmf_enabled; + qdf_time_t last_assoc_received_time; + qdf_time_t last_disassoc_deauth_received_time; }; /** @@ -47,11 +76,15 @@ struct peer_mlme_priv_obj { * @dynamic_cfg: current configuration of nss, chains for vdev. * @ini_cfg: Max configuration of nss, chains supported for vdev. * @sta_dynamic_oce_value: Dyanmic oce flags value for sta + * @follow_ap_edca: if true, it is forced to follow the AP's edca + * @disconnect_info: Disconnection information */ struct vdev_mlme_priv_obj { struct mlme_nss_chains dynamic_cfg; struct mlme_nss_chains ini_cfg; uint8_t sta_dynamic_oce_value; + bool follow_ap_edca; + struct wlan_disconnect_info disconnect_info; }; @@ -220,4 +253,90 @@ void mlme_set_peer_pmf_status(struct wlan_objmgr_peer *peer, * Return: Value of is_pmf_enabled; True if PMF is enabled by peer */ bool mlme_get_peer_pmf_status(struct wlan_objmgr_peer *peer); + +/** + * mlme_set_self_disconnect_ies() - Set diconnect IEs configured from userspace + * @vdev: vdev pointer + * @ie: pointer for disconnect IEs + * + * Return: None + */ +void mlme_set_self_disconnect_ies(struct wlan_objmgr_vdev *vdev, + struct wlan_ies *ie); + +/** + * mlme_free_self_disconnect_ies() - Free the self diconnect IEs + * @vdev: vdev pointer + * + * Return: None + */ +void mlme_free_self_disconnect_ies(struct wlan_objmgr_vdev *vdev); + +/** + * mlme_get_self_disconnect_ies() - Get diconnect IEs from vdev object + * @vdev: vdev pointer + * + * Return: Returns a pointer to the self disconnect IEs present in vdev object + */ +struct wlan_ies *mlme_get_self_disconnect_ies(struct wlan_objmgr_vdev *vdev); + +/** + * mlme_set_peer_disconnect_ies() - Cache disconnect IEs received from peer + * @vdev: vdev pointer + * @ie: pointer for disconnect IEs + * + * Return: None + */ +void mlme_set_peer_disconnect_ies(struct wlan_objmgr_vdev *vdev, + struct wlan_ies *ie); + +/** + * mlme_free_peer_disconnect_ies() - Free the peer diconnect IEs + * @vdev: vdev pointer + * + * Return: None + */ +void mlme_free_peer_disconnect_ies(struct wlan_objmgr_vdev *vdev); + +/** + * mlme_get_peer_disconnect_ies() - Get diconnect IEs from vdev object + * @vdev: vdev pointer + * + * Return: Returns a pointer to the peer disconnect IEs present in vdev object + */ +struct wlan_ies *mlme_get_peer_disconnect_ies(struct wlan_objmgr_vdev *vdev); + +/** + * mlme_set_discon_reason_n_from_ap() - set disconnect reason and from ap flag + * @psoc: PSOC pointer + * @vdev_id: vdev id + * @from_ap: True if the disconnect is initiated from peer. + * False otherwise. + * @reason_code: The disconnect code received from peer or internally generated. + * + * Set the reason code and from_ap. + * + * Return: void + */ +void mlme_set_discon_reason_n_from_ap(struct wlan_objmgr_psoc *psoc, + uint8_t vdev_id, bool from_ap, + uint32_t reason_code); + +/** + * mlme_get_discon_reason_n_from_ap() - Get disconnect reason and from ap flag + * @psoc: PSOC pointer + * @vdev_id: vdev id + * @from_ap: Get the from_ap cached through mlme_set_discon_reason_n_from_ap + * and copy to this buffer. + * @reason_code: Get the reason_code cached through + * mlme_set_discon_reason_n_from_ap and copy to this buffer. + * + * Copy the contents of from_ap and reason_code to given buffers. + * + * Return: void + */ +void mlme_get_discon_reason_n_from_ap(struct wlan_objmgr_psoc *psoc, + uint8_t vdev_id, bool *from_ap, + uint32_t *reason_code); + #endif diff --git a/drivers/staging/qcacld-3.0/components/mlme/core/src/wlan_mlme_main.c b/drivers/staging/qcacld-3.0/components/mlme/core/src/wlan_mlme_main.c index 12be8728086b..8a8f83941c97 100644 --- a/drivers/staging/qcacld-3.0/components/mlme/core/src/wlan_mlme_main.c +++ b/drivers/staging/qcacld-3.0/components/mlme/core/src/wlan_mlme_main.c @@ -193,6 +193,8 @@ mlme_vdev_object_destroyed_notification(struct wlan_objmgr_vdev *vdev, return QDF_STATUS_E_FAILURE; } + mlme_free_self_disconnect_ies(vdev); + mlme_free_peer_disconnect_ies(vdev); status = wlan_objmgr_vdev_component_obj_detach(vdev, WLAN_UMAC_COMP_MLME, vdev_mlme); @@ -328,3 +330,185 @@ bool mlme_get_peer_pmf_status(struct wlan_objmgr_peer *peer) return peer_priv->is_pmf_enabled; } + +void mlme_set_self_disconnect_ies(struct wlan_objmgr_vdev *vdev, + struct wlan_ies *ie) +{ + struct vdev_mlme_priv_obj *vdev_mlme; + + if (!ie || !ie->len || !ie->data) { + mlme_debug("disocnnect IEs are NULL"); + return; + } + + vdev_mlme = wlan_vdev_mlme_get_priv_obj(vdev); + if (!vdev_mlme) { + mlme_err("vdev component object is NULL"); + return; + } + + if (vdev_mlme->disconnect_info.self_discon_ies.data) { + qdf_mem_free(vdev_mlme->disconnect_info.self_discon_ies.data); + vdev_mlme->disconnect_info.self_discon_ies.len = 0; + } + + vdev_mlme->disconnect_info.self_discon_ies.data = qdf_mem_malloc(ie->len); + if (!vdev_mlme->disconnect_info.self_discon_ies.data) + return; + + qdf_mem_copy(vdev_mlme->disconnect_info.self_discon_ies.data, ie->data, ie->len); + vdev_mlme->disconnect_info.self_discon_ies.len = ie->len; + + mlme_debug("Self disconnect IEs"); + QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_MLME, QDF_TRACE_LEVEL_DEBUG, + vdev_mlme->disconnect_info.self_discon_ies.data, + vdev_mlme->disconnect_info.self_discon_ies.len); +} + +void mlme_free_self_disconnect_ies(struct wlan_objmgr_vdev *vdev) +{ + struct vdev_mlme_priv_obj *vdev_mlme; + + vdev_mlme = wlan_vdev_mlme_get_priv_obj(vdev); + if (!vdev_mlme) { + mlme_err("vdev component object is NULL"); + return; + } + + if (vdev_mlme->disconnect_info.self_discon_ies.data) { + qdf_mem_free(vdev_mlme->disconnect_info.self_discon_ies.data); + vdev_mlme->disconnect_info.self_discon_ies.data = NULL; + vdev_mlme->disconnect_info.self_discon_ies.len = 0; + } +} + +struct wlan_ies *mlme_get_self_disconnect_ies(struct wlan_objmgr_vdev *vdev) +{ + struct vdev_mlme_priv_obj *vdev_mlme; + + vdev_mlme = wlan_vdev_mlme_get_priv_obj(vdev); + if (!vdev_mlme) { + mlme_err("vdev component object is NULL"); + return NULL; + } + + return &vdev_mlme->disconnect_info.self_discon_ies; +} + +void mlme_set_peer_disconnect_ies(struct wlan_objmgr_vdev *vdev, + struct wlan_ies *ie) +{ + struct vdev_mlme_priv_obj *vdev_mlme; + + if (!ie || !ie->len || !ie->data) { + mlme_debug("disocnnect IEs are NULL"); + return; + } + + vdev_mlme = wlan_vdev_mlme_get_priv_obj(vdev); + if (!vdev_mlme) { + mlme_err("vdev component object is NULL"); + return; + } + + if (vdev_mlme->disconnect_info.peer_discon_ies.data) { + qdf_mem_free(vdev_mlme->disconnect_info.peer_discon_ies.data); + vdev_mlme->disconnect_info.peer_discon_ies.len = 0; + } + + vdev_mlme->disconnect_info.peer_discon_ies.data = qdf_mem_malloc(ie->len); + if (!vdev_mlme->disconnect_info.peer_discon_ies.data) + return; + + qdf_mem_copy(vdev_mlme->disconnect_info.peer_discon_ies.data, ie->data, ie->len); + vdev_mlme->disconnect_info.peer_discon_ies.len = ie->len; + + mlme_debug("peer disconnect IEs"); + QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_MLME, QDF_TRACE_LEVEL_DEBUG, + vdev_mlme->disconnect_info.peer_discon_ies.data, + vdev_mlme->disconnect_info.peer_discon_ies.len); +} + +void mlme_free_peer_disconnect_ies(struct wlan_objmgr_vdev *vdev) +{ + struct vdev_mlme_priv_obj *vdev_mlme; + + vdev_mlme = wlan_vdev_mlme_get_priv_obj(vdev); + if (!vdev_mlme) { + mlme_err("vdev component object is NULL"); + return; + } + + if (vdev_mlme->disconnect_info.peer_discon_ies.data) { + qdf_mem_free(vdev_mlme->disconnect_info.peer_discon_ies.data); + vdev_mlme->disconnect_info.peer_discon_ies.data = NULL; + vdev_mlme->disconnect_info.peer_discon_ies.len = 0; + } +} + +struct wlan_ies *mlme_get_peer_disconnect_ies(struct wlan_objmgr_vdev *vdev) +{ + struct vdev_mlme_priv_obj *vdev_mlme; + + vdev_mlme = wlan_vdev_mlme_get_priv_obj(vdev); + if (!vdev_mlme) { + mlme_err("vdev component object is NULL"); + return NULL; + } + + return &vdev_mlme->disconnect_info.peer_discon_ies; +} + +void mlme_set_discon_reason_n_from_ap(struct wlan_objmgr_psoc *psoc, + uint8_t vdev_id, bool from_ap, + uint32_t reason_code) +{ + struct wlan_objmgr_vdev *vdev; + struct vdev_mlme_priv_obj *vdev_mlme; + + if (!psoc) + return; + + vdev = wlan_objmgr_get_vdev_by_id_from_psoc(psoc, vdev_id, + WLAN_LEGACY_MAC_ID); + if (!vdev) + return; + vdev_mlme = wlan_vdev_mlme_get_priv_obj(vdev); + if (!vdev_mlme) { + mlme_err("vdev component object is NULL"); + wlan_objmgr_vdev_release_ref(vdev, WLAN_LEGACY_MAC_ID); + return; + } + + vdev_mlme->disconnect_info.from_ap = from_ap; + vdev_mlme->disconnect_info.discon_reason = reason_code; + wlan_objmgr_vdev_release_ref(vdev, WLAN_LEGACY_MAC_ID); +} + +void mlme_get_discon_reason_n_from_ap(struct wlan_objmgr_psoc *psoc, + uint8_t vdev_id, bool *from_ap, + uint32_t *reason_code) +{ + struct wlan_objmgr_vdev *vdev; + struct vdev_mlme_priv_obj *vdev_mlme; + + if (!psoc) + return; + + vdev = wlan_objmgr_get_vdev_by_id_from_psoc(psoc, vdev_id, + WLAN_LEGACY_MAC_ID); + if (!vdev) + return; + vdev_mlme = wlan_vdev_mlme_get_priv_obj(vdev); + if (!vdev_mlme) { + mlme_err("vdev component object is NULL"); + wlan_objmgr_vdev_release_ref(vdev, WLAN_LEGACY_MAC_ID); + return; + } + + *from_ap = vdev_mlme->disconnect_info.from_ap; + *reason_code = vdev_mlme->disconnect_info.discon_reason; + vdev_mlme->disconnect_info.from_ap = false; + vdev_mlme->disconnect_info.discon_reason = 0; + wlan_objmgr_vdev_release_ref(vdev, WLAN_LEGACY_MAC_ID); +} diff --git a/drivers/staging/qcacld-3.0/components/mlme/dispatcher/inc/wlan_mlme_ucfg_api.h b/drivers/staging/qcacld-3.0/components/mlme/dispatcher/inc/wlan_mlme_ucfg_api.h index 17472ec8212b..c6d9aa41af2f 100644 --- a/drivers/staging/qcacld-3.0/components/mlme/dispatcher/inc/wlan_mlme_ucfg_api.h +++ b/drivers/staging/qcacld-3.0/components/mlme/dispatcher/inc/wlan_mlme_ucfg_api.h @@ -102,4 +102,24 @@ void ucfg_mlme_update_oce_flags(struct wlan_objmgr_pdev *pdev, void ucfg_mlme_force_objmgr_vdev_peer_cleanup(uint8_t vdev_id); +/** + * ucfg_mlme_get_discon_reason_n_from_ap() - Get disconnect reason and from ap + * @psoc: PSOC pointer + * @vdev_id: vdev id + * @from_ap: Get the from_ap cached through mlme_set_discon_reason_n_from_ap + * and copy to this buffer. + * @reason_code: Get the reason_code cached through + * mlme_set_discon_reason_n_from_ap and copy to this buffer. + * + * Fetch the contents of from_ap and reason_codes. + * + * Return: void + */ +static inline void +ucfg_mlme_get_discon_reason_n_from_ap(struct wlan_objmgr_psoc *psoc, + uint8_t vdev_id, bool *from_ap, + uint32_t *reason_code) +{ + mlme_get_discon_reason_n_from_ap(psoc, vdev_id, from_ap, reason_code); +} #endif /* _WLAN_MLME_UCFG_API_H_ */ diff --git a/drivers/staging/qcacld-3.0/components/pkt_capture/core/inc/wlan_pkt_capture_data_txrx.h b/drivers/staging/qcacld-3.0/components/pkt_capture/core/inc/wlan_pkt_capture_data_txrx.h new file mode 100644 index 000000000000..f2ebbeced315 --- /dev/null +++ b/drivers/staging/qcacld-3.0/components/pkt_capture/core/inc/wlan_pkt_capture_data_txrx.h @@ -0,0 +1,166 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/** + * DOC: Declare private API which shall be used internally only + * in pkt_capture component. This file shall include prototypes of + * pkt_capture data tx and data rx. + * + * Note: This API should be never accessed out of pkt_capture component. + */ + +#ifndef _WLAN_PKT_CAPTURE_DATA_TXRX_H_ +#define _WLAN_PKT_CAPTURE_DATA_TXRX_H_ + +#include "cdp_txrx_cmn_struct.h" +#include +#include + +#define SHORT_PREAMBLE 1 +#define LONG_PREAMBLE 0 +/** + * pkt_capture_data_process_type - data pkt types to process + * for packet capture mode + * @TXRX_PROCESS_TYPE_DATA_RX: process RX packets (normal rx + offloaded rx) + * @TXRX_PROCESS_TYPE_DATA_TX: process TX packets (ofloaded tx) + * @TXRX_PROCESS_TYPE_DATA_TX_COMPL: process TX compl packets (normal tx) + */ +enum pkt_capture_data_process_type { + TXRX_PROCESS_TYPE_DATA_RX, + TXRX_PROCESS_TYPE_DATA_TX, + TXRX_PROCESS_TYPE_DATA_TX_COMPL, +}; + +#define TXRX_PKTCAPTURE_PKT_FORMAT_8023 0 +#define TXRX_PKTCAPTURE_PKT_FORMAT_80211 1 + +/** + * pkt_capture_datapkt_process() - process data tx and rx packets + * for pkt capture mode. (normal tx/rx + offloaded tx/rx) + * @vdev_id: vdev id for which packet is captured + * @mon_buf_list: netbuf list + * @type: data process type + * @tid: tid number + * @status: Tx status + * @pkt_format: Frame format + * @bssid: bssid + * @pdev: pdev handle + * @tx_retry_cnt: tx retry count + * + * Return: none + */ +void pkt_capture_datapkt_process( + uint8_t vdev_id, + qdf_nbuf_t mon_buf_list, + enum pkt_capture_data_process_type type, + uint8_t tid, uint8_t status, bool pktformat, + uint8_t *bssid, htt_pdev_handle pdev, + uint8_t tx_retry_cnt); +/** + * pkt_capture_msdu_process_pkts() - process data rx pkts + * @bssid: bssid + * @head_msdu: pointer to head msdu + * @vdev_id: vdev_id + * @pdev: pdev handle + * + * Return: none + */ +void pkt_capture_msdu_process_pkts( + uint8_t *bssid, + qdf_nbuf_t head_msdu, + uint8_t vdev_id, + htt_pdev_handle pdev); + +/** + * pkt_capture_rx_in_order_drop_offload_pkt() - drop offload packets + * @head_msdu: pointer to head msdu + * + * Return: none + */ +void pkt_capture_rx_in_order_drop_offload_pkt(qdf_nbuf_t head_msdu); + +/** + * pkt_capture_rx_in_order_offloaded_pkt() - check offloaded data pkt or not + * @rx_ind_msg: rx_ind_msg + * + * Return: false if it is not an offload packet + * true if it is offload packet + */ +bool pkt_capture_rx_in_order_offloaded_pkt(qdf_nbuf_t rx_ind_msg); + +/** + * pkt_capture_offload_deliver_indication_handler() - Handle offload data pkts + * @msg: offload netbuf msg + * @vdev_id: vdev id + * @bssid: bssid + * @pdev: pdev handle + * + * Return: none + */ +void pkt_capture_offload_deliver_indication_handler( + void *msg, uint8_t vdev_id, + uint8_t *bssid, htt_pdev_handle pdev); + +/** + * pkt_capture_tx_hdr_elem_t - tx packets header struture to + * be used to update radiotap header for packet capture mode + * @timestamp: timestamp + * @preamble: preamble + * @mcs: MCS + * @rate: rate + * @rssi_comb: rssi in dBm + * @nss: if nss 1 means 1ss and 2 means 2ss + * @bw: BW (0=>20MHz, 1=>40MHz, 2=>80MHz, 3=>160MHz) + * @stbc: STBC + * @sgi: SGI + * @ldpc: LDPC + * @beamformed: beamformed + * @dir: direction rx: 0 and tx: 1 + * @status: tx status + * @tx_retry_cnt: tx retry count + */ +struct pkt_capture_tx_hdr_elem_t { + uint32_t timestamp; + uint8_t preamble; + uint8_t mcs; + uint8_t rate; + uint8_t rssi_comb; + uint8_t nss; + uint8_t bw; + bool stbc; + bool sgi; + bool ldpc; + bool beamformed; + bool dir; /* rx:0 , tx:1 */ + uint8_t status; /* tx status */ + uint8_t tx_retry_cnt; +}; + +/** + * pkt_capture_tx_get_txcomplete_data_hdr() - extract Tx data hdr from Tx + * completion for pkt capture mode + * @msg_word: Tx completion htt msg + * @num_msdus: number of msdus + * + * Return: tx data hdr information + */ +struct htt_tx_data_hdr_information *pkt_capture_tx_get_txcomplete_data_hdr( + uint32_t *msg_word, + int num_msdus); + +#endif /* End of _WLAN_PKT_CAPTURE_DATA_TXRX_H_ */ diff --git a/drivers/staging/qcacld-3.0/components/pkt_capture/core/inc/wlan_pkt_capture_main.h b/drivers/staging/qcacld-3.0/components/pkt_capture/core/inc/wlan_pkt_capture_main.h new file mode 100644 index 000000000000..5b8a94ca6011 --- /dev/null +++ b/drivers/staging/qcacld-3.0/components/pkt_capture/core/inc/wlan_pkt_capture_main.h @@ -0,0 +1,197 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/** + * DOC: Declare private API which shall be used internally only + * in pkt_capture component. This file shall include prototypes of + * various notification handlers and logging functions. + * + * Note: This API should be never accessed out of pkt_capture component. + */ + +#ifndef _WLAN_PKT_CAPTURE_MAIN_H_ +#define _WLAN_PKT_CAPTURE_MAIN_H_ + +#include +#include "wlan_pkt_capture_priv.h" +#include "wlan_pkt_capture_objmgr.h" +#include "wlan_objmgr_vdev_obj.h" + +#define pkt_capture_log(level, args...) \ + QDF_TRACE(QDF_MODULE_ID_PKT_CAPTURE, level, ## args) + +#define pkt_capture_logfl(level, format, args...) \ + pkt_capture_log(level, FL(format), ## args) + +#define pkt_capture_fatal(format, args...) \ + pkt_capture_logfl(QDF_TRACE_LEVEL_FATAL, format, ## args) +#define pkt_capture_err(format, args...) \ + pkt_capture_logfl(QDF_TRACE_LEVEL_ERROR, format, ## args) +#define pkt_capture_warn(format, args...) \ + pkt_capture_logfl(QDF_TRACE_LEVEL_WARN, format, ## args) +#define pkt_capture_info(format, args...) \ + pkt_capture_logfl(QDF_TRACE_LEVEL_INFO, format, ## args) +#define pkt_capture_debug(format, args...) \ + pkt_capture_logfl(QDF_TRACE_LEVEL_DEBUG, format, ## args) + +#define PKT_CAPTURE_ENTER() pkt_capture_debug("enter") +#define PKT_CAPTURE_EXIT() pkt_capture_debug("exit") + +#define NORMALIZED_TO_NOISE_FLOOR (-96) +/** + * enum pkt_capture_tx_status - packet capture tx status + * @pktcapture_tx_status_ok: successfully sent + acked + * @pktcapture_tx_status_discard: discard - not sent + * @pktcapture_tx_status_no_ack: no_ack - sent, but no ack + * + * This enum has tx status types for packet capture mode + */ +enum pkt_capture_tx_status { + pkt_capture_tx_status_ok, + pkt_capture_tx_status_discard, + pkt_capture_tx_status_no_ack, +}; + +/** + * pkt_capture_get_vdev() - Get pkt capture objmgr vdev. + * + * Return: pkt capture objmgr vdev + */ +struct wlan_objmgr_vdev *pkt_capture_get_vdev(void); + +/** + * pkt_capture_vdev_create_notification() - Handler for vdev create notify. + * @vdev: vdev which is going to be created by objmgr + * @arg: argument for notification handler. + * + * Allocate and attach vdev private object. + * + * Return: QDF_STATUS + */ +QDF_STATUS +pkt_capture_vdev_create_notification(struct wlan_objmgr_vdev *vdev, void *arg); + +/** + * pkt_capture_vdev_destroy_notification() - Handler for vdev destroy notify. + * @vdev: vdev which is going to be destroyed by objmgr + * @arg: argument for notification handler. + * + * Deallocate and detach vdev private object. + * + * Return: QDF_STATUS + */ +QDF_STATUS +pkt_capture_vdev_destroy_notification(struct wlan_objmgr_vdev *vdev, void *arg); + +/** + * pkt_capture_get_mode() - get packet capture mode + * @psoc: pointer to psoc object + * + * Return: enum pkt_capture_mode + */ +enum pkt_capture_mode pkt_capture_get_mode(struct wlan_objmgr_psoc *psoc); + +/** + * pkt_capture_psoc_create_notification() - Handler for psoc create notify. + * @psoc: psoc which is going to be created by objmgr + * @arg: argument for notification handler. + * + * Allocate and attach psoc private object. + * + * Return: QDF_STATUS + */ +QDF_STATUS +pkt_capture_psoc_create_notification(struct wlan_objmgr_psoc *psoc, void *arg); + +/** + * pkt_capture_psoc_destroy_notification() - Handler for psoc destroy notify. + * @psoc: psoc which is going to be destroyed by objmgr + * @arg: argument for notification handler. + * + * Deallocate and detach psoc private object. + * + * Return: QDF_STATUS + */ +QDF_STATUS +pkt_capture_psoc_destroy_notification(struct wlan_objmgr_psoc *psoc, void *arg); + +/** + * ucfg_pkt_capture_psoc_config(): API to update the psoc user configurations + * @psoc: objmgr psoc handle + * @cfg: packet capture psoc configurations + * + * Return: QDF_STATUS + */ +QDF_STATUS pkt_capture_psoc_config(struct wlan_objmgr_psoc *psoc, + struct pkt_capture_cfg *cfg); + +/** + * pkt_capture_register_callbacks - Register packet capture callbacks + * @vdev: pointer to wlan vdev object manager + * @mon_cb: callback to call + * @context: callback context + * + * Return: QDF_STATUS + */ +QDF_STATUS +pkt_capture_register_callbacks(struct wlan_objmgr_vdev *vdev, + QDF_STATUS (*mon_cb)(void *, qdf_nbuf_t), + void *context); + +/** + * pkt_capture_deregister_callbacks - De-register packet capture callbacks + * @vdev: pointer to wlan vdev object manager + * + * Return: QDF_STATUS + */ +QDF_STATUS pkt_capture_deregister_callbacks(struct wlan_objmgr_vdev *vdev); + +/** + * pkt_capture_set_pktcap_mode - Set packet capture mode + * @psoc: pointer to psoc object + * @mode: mode to be set + * + * Return: None + */ +void pkt_capture_set_pktcap_mode(struct wlan_objmgr_psoc *psoc, + enum pkt_capture_mode mode); + +/** + * pkt_capture_get_pktcap_mode - Get packet capture mode + * + * Return: enum pkt_capture_mode + */ +enum pkt_capture_mode +pkt_capture_get_pktcap_mode(void); + +/** + * pkt_capture_drop_nbuf_list() - drop an nbuf list + * @buf_list: buffer list to be dropepd + * + * Return: number of buffers dropped + */ +uint32_t pkt_capture_drop_nbuf_list(qdf_nbuf_t buf_list); + +/** + * pkt_capture_record_channel() - Update Channel Information + * for packet capture mode + * + * Return: None + */ +void pkt_capture_record_channel(void); +#endif /* end of _WLAN_PKT_CAPTURE_MAIN_H_ */ diff --git a/drivers/staging/qcacld-3.0/components/pkt_capture/core/inc/wlan_pkt_capture_mgmt_txrx.h b/drivers/staging/qcacld-3.0/components/pkt_capture/core/inc/wlan_pkt_capture_mgmt_txrx.h new file mode 100644 index 000000000000..f456107b9f0c --- /dev/null +++ b/drivers/staging/qcacld-3.0/components/pkt_capture/core/inc/wlan_pkt_capture_mgmt_txrx.h @@ -0,0 +1,104 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/** + * DOC: Declare mgmt txrx APIs which shall be used internally only + * in pkt_capture component. + * Note: These APIs should be never accessed out of pkt_capture component. + */ + +#ifndef _WLAN_PKT_CAPTURE_MGMT_TXRX_H_ +#define _WLAN_PKT_CAPTURE_MGMT_TXRX_H_ + +#include "wlan_pkt_capture_public_structs.h" + +#define PKTCAPTURE_PKT_FORMAT_8023 (0) +#define PKTCAPTURE_PKT_FORMAT_80211 (1) +#define WLAN_INVALID_TID (31) +#define RESERVE_BYTES (100) +#define RATE_LIMIT (16) +#define INVALID_RSSI_FOR_TX (-128) + +/** + * pkt_capture_process_mgmt_tx_data() - process management tx packets + * @pdev: pointer to pdev object + * @params: management offload event params + * @nbuf: netbuf + * @status: status + * + * Return: QDF_STATUS + */ +QDF_STATUS +pkt_capture_process_mgmt_tx_data(struct wlan_objmgr_pdev *pdev, + struct mgmt_offload_event_params *params, + qdf_nbuf_t nbuf, + uint8_t status); +/** + * pkt_capture_mgmt_tx() - process mgmt tx completion + * for pkt capture mode + * @pdev: pointer to pdev object + * @nbuf: netbuf + * @chan_freq: channel freq + * @preamble_type: preamble_type + * + * Return: none + */ +void pkt_capture_mgmt_tx(struct wlan_objmgr_pdev *pdev, + qdf_nbuf_t nbuf, + uint16_t chan_freq, + uint8_t preamble_type); + +/** + * pkt_capture_mgmt_tx_completion() - process mgmt tx completion + * for pkt capture mode + * @pdev: pointer to pdev object + * @desc_id: desc_id + * @status: status + * @params: management offload event params + * + * Return: none + */ +void +pkt_capture_mgmt_tx_completion(struct wlan_objmgr_pdev *pdev, + uint32_t desc_id, + uint32_t status, + struct mgmt_offload_event_params *params); + +/** + * pkt_capture_mgmt_rx_ops() - Register packet capture mgmt rx ops + * @psoc: psoc context + * @is_register: register if true, unregister if false + * + * This funciton registers or deregisters rx callback + * to mgmt txrx component. + * + * Return: QDF_STATUS + */ +QDF_STATUS pkt_capture_mgmt_rx_ops(struct wlan_objmgr_psoc *psoc, + bool is_register); + +/** + * pkt_capture_mgmt_status_map() - map Tx status for MGMT packets + * with packet capture Tx status + * @status: Tx status + * + * Return: pkt_capture_tx_status enum + */ +enum pkt_capture_tx_status +pkt_capture_mgmt_status_map(uint8_t status); +#endif diff --git a/drivers/staging/qcacld-3.0/components/pkt_capture/core/inc/wlan_pkt_capture_mon_thread.h b/drivers/staging/qcacld-3.0/components/pkt_capture/core/inc/wlan_pkt_capture_mon_thread.h new file mode 100644 index 000000000000..77221daf8b07 --- /dev/null +++ b/drivers/staging/qcacld-3.0/components/pkt_capture/core/inc/wlan_pkt_capture_mon_thread.h @@ -0,0 +1,217 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/** + * DOC: Declare APIs which shall be used for monitor thread access. + */ + +#ifndef _WLAN_PKT_CAPTURE_MON_THREAD_H_ +#define _WLAN_PKT_CAPTURE_MON_THREAD_H_ + +#include "wlan_pkt_capture_main.h" + +#define PKT_CAPTURE_RX_POST_EVENT 0x01 +#define PKT_CAPTURE_RX_SUSPEND_EVENT 0x02 +#define PKT_CAPTURE_RX_SHUTDOWN_EVENT 0x04 + +/* + * Maximum number of packets to be allocated for + * Packet Capture Monitor thread. + */ +#define MAX_MON_PKT_SIZE 4000 + +/* timeout in msec to wait for mon thread to suspend */ +#define PKT_CAPTURE_SUSPEND_TIMEOUT 200 + +typedef void (*pkt_capture_mon_thread_cb)( + void *context, void *ppdev, void *monpkt, + uint8_t vdev_id, uint8_t tid, + uint8_t status, bool pkt_format, + uint8_t *bssid, + uint8_t tx_retry_cnt); + +/* + * struct pkt_capture_mon_pkt - mon packet wrapper for mon data from TXRX + * @list: List for storing mon packets + * @context: Callback context + * @pdev: pointer to pdev handle + * @monpkt: Mon skb + * @vdev_id: Vdev id to which this packet is destined + * @tid: Tid of mon packet + * @status: Tx packet status + * @pkt_format: Mon packet format, 0 = 802.3 format , 1 = 802.11 format + * @bssid: bssid + * @tx_retry_cnt: tx retry count + * @callback: Mon callback + */ +struct pkt_capture_mon_pkt { + struct list_head list; + void *context; + void *pdev; + void *monpkt; + uint8_t vdev_id; + uint8_t tid; + uint8_t status; + bool pkt_format; + uint8_t bssid[QDF_MAC_ADDR_SIZE]; + uint8_t tx_retry_cnt; + pkt_capture_mon_thread_cb callback; +}; + +/** + * struct pkt_capture_mon_context - packet capture mon thread context + * @mon_thread_lock: MON thread lock + * @mon_thread: MON thread handle + * @mon_start_event: Handle of Event for MON thread to signal startup + * @suspend_mon_event: Completion to suspend packet capture MON thread + * @resume_mon_event: Completion to resume packet capture MON thread + * @mon_shutdown: Completion for packet capture MON thread shutdown + * @mon_wait_queue: Waitq for packet capture MON thread + * @mon_event_flag: Mon event flag + * @mon_thread_queue: MON buffer queue + * @mon_queue_lock: Spinlock to synchronize between tasklet and thread + * @mon_pkt_freeq_lock: Lock to synchronize free buffer queue access + * @mon_pkt_freeq: Free message queue for packet capture MON processing + * @is_mon_thread_suspended: flag to check mon thread suspended or not + */ +struct pkt_capture_mon_context { + /* MON thread lock */ + spinlock_t mon_thread_lock; + struct task_struct *mon_thread; + struct completion mon_start_event; + struct completion suspend_mon_event; + struct completion resume_mon_event; + struct completion mon_shutdown; + wait_queue_head_t mon_wait_queue; + unsigned long mon_event_flag; + struct list_head mon_thread_queue; + + /* Spinlock to synchronize between tasklet and thread */ + spinlock_t mon_queue_lock; + + /* Lock to synchronize free buffer queue access */ + spinlock_t mon_pkt_freeq_lock; + + struct list_head mon_pkt_freeq; + bool is_mon_thread_suspended; +}; + +/** + * pkt_capture_suspend_mon_thread() - suspend packet capture mon thread + * vdev: pointer to vdev object manager + * + * Return: 0 on success, -EINVAL on failure + */ +int pkt_capture_suspend_mon_thread(struct wlan_objmgr_vdev *vdev); + +/** + * pkt_capture_resume_mon_thread() - resume packet capture mon thread + * vdev: pointer to vdev object manager + * + * Resume packet capture MON thread by completing RX thread resume event. + * + * Return: None + */ +void pkt_capture_resume_mon_thread(struct wlan_objmgr_vdev *vdev); + +/** + * pkt_capture_drop_monpkt() - API to drop pending mon packets + * mon_ctx: pointer to packet capture mon context + * + * This api drops all the pending packets in the queue. + * + * Return: None + */ +void pkt_capture_drop_monpkt(struct pkt_capture_mon_context *mon_ctx); + +/** + * pkt_capture_indicate_monpkt() - API to Indicate rx data packet + * @vdev: pointer to vdev object manager + * @pkt: MON pkt pointer containing to mon data message buffer + * + * Return: None + */ +void pkt_capture_indicate_monpkt(struct wlan_objmgr_vdev *vdev, + struct pkt_capture_mon_pkt *pkt); + +/** + * pkt_capture_wakeup_mon_thread() - wakeup packet capture mon thread + * @vdev: pointer to vdev object + * + * This api wake up pkt_capture_mon_thread() to process pkt. + * + * Return: None + */ +void pkt_capture_wakeup_mon_thread(struct wlan_objmgr_vdev *vdev); + +/** + * pkt_capture_close_mon_thread() - close packet capture MON thread + * @mon_ctx: pointer to packet capture mon context + * + * This api closes packet capture MON thread. + * + * Return: None + */ +void pkt_capture_close_mon_thread(struct pkt_capture_mon_context *mon_ctx); + +/** + * pkt_capture_open_mon_thread() - open packet capture MON thread + * @mon_ctx: pointer to packet capture mon context + * + * This api opens the packet capture MON thread. + * + * Return: QDF_STATUS + */ +QDF_STATUS +pkt_capture_open_mon_thread(struct pkt_capture_mon_context *mon_ctx); + +/** + * pkt_capture_alloc_mon_thread() - alloc resources for + * packet capture MON thread + * @mon_ctx: pointer to packet capture mon context + * + * This api alloc resources for packet capture MON thread. + * + * Return: QDF_STATUS + */ +QDF_STATUS +pkt_capture_alloc_mon_thread(struct pkt_capture_mon_context *mon_ctx); + +/** + * pkt_capture_alloc_mon_pkt() - API to return next available mon packet + * @vdev: pointer to vdev object manager + * + * This api returns next available mon packet buffer used for mon data + * processing. + * + * Return: Pointer to pkt_capture_mon_pkt + */ +struct pkt_capture_mon_pkt * +pkt_capture_alloc_mon_pkt(struct wlan_objmgr_vdev *vdev); + +/** + * pkt_capture_free_mon_pkt_freeq() - free mon packet free queue + * @mon_ctx: pointer to packet capture mon context + * + * This API does mem free of the buffers available in free mon packet + * queue which is used for mon Data processing. + * + * Return: None + */ +void pkt_capture_free_mon_pkt_freeq(struct pkt_capture_mon_context *mon_ctx); +#endif /* _WLAN_PKT_CAPTURE_MON_THREAD_H_ */ diff --git a/drivers/staging/qcacld-3.0/components/pkt_capture/core/inc/wlan_pkt_capture_objmgr.h b/drivers/staging/qcacld-3.0/components/pkt_capture/core/inc/wlan_pkt_capture_objmgr.h new file mode 100644 index 000000000000..4da27aed72f2 --- /dev/null +++ b/drivers/staging/qcacld-3.0/components/pkt_capture/core/inc/wlan_pkt_capture_objmgr.h @@ -0,0 +1,129 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/** + * DOC: This file contains various object manager related wrappers and helpers + */ + +#ifndef _WLAN_PKT_CAPTURE_OBJMGR_H +#define _WLAN_PKT_CAPTURE_OBJMGR_H + +#include "wlan_cmn.h" +#include "wlan_objmgr_cmn.h" +#include "wlan_objmgr_vdev_obj.h" +#include "wlan_objmgr_global_obj.h" + +/** + * pkt_capture_vdev_get_ref() - Wrapper to increment pkt_capture ref count + * @vdev: vdev object + * + * Wrapper for pkt_capture to increment ref count after checking valid + * object state. + * + * Return: SUCCESS/FAILURE + */ +static inline +QDF_STATUS pkt_capture_vdev_get_ref(struct wlan_objmgr_vdev *vdev) +{ + return wlan_objmgr_vdev_try_get_ref(vdev, WLAN_PKT_CAPTURE_ID); +} + +/** + * pkt_capture_vdev_put_ref() - Wrapper to decrement pkt_capture ref count + * @vdev: vdev object + * + * Wrapper for pkt_capture to decrement ref count of vdev. + * + * Return: SUCCESS/FAILURE + */ +static inline +void pkt_capture_vdev_put_ref(struct wlan_objmgr_vdev *vdev) +{ + wlan_objmgr_vdev_release_ref(vdev, WLAN_PKT_CAPTURE_ID); +} + +/** + * pkt_capture_vdev_get_priv() - Wrapper to retrieve vdev priv obj + * @vdev: vdev pointer + * + * Wrapper for pkt_capture to get vdev private object pointer. + * + * Return: Private object of vdev + */ +static inline struct pkt_capture_vdev_priv * +pkt_capture_vdev_get_priv(struct wlan_objmgr_vdev *vdev) +{ + struct pkt_capture_vdev_priv *vdev_priv; + + vdev_priv = wlan_objmgr_vdev_get_comp_private_obj( + vdev, + WLAN_UMAC_COMP_PKT_CAPTURE); + QDF_BUG(vdev_priv); + + return vdev_priv; +} + +/** + * pkt_capture_psoc_get_ref() - Wrapper to increment pkt_capture ref count + * @psoc: psoc object + * + * Wrapper for pkt_capture to increment ref count after checking valid + * object state. + * + * Return: QDF_STATUS + */ +static inline +QDF_STATUS pkt_capture_psoc_get_ref(struct wlan_objmgr_psoc *psoc) +{ + return wlan_objmgr_psoc_try_get_ref(psoc, WLAN_PKT_CAPTURE_ID); +} + +/** + * pkt_capture_psoc_put_ref() - Wrapper to decrement pkt_capture ref count + * @psoc: psoc object + * + * Wrapper for pkt_capture to decrement ref count of psoc. + * + * Return: None + */ +static inline +void pkt_capture_psoc_put_ref(struct wlan_objmgr_psoc *psoc) +{ + wlan_objmgr_psoc_release_ref(psoc, WLAN_PKT_CAPTURE_ID); +} + +/** + * pkt_capture_psoc_get_priv(): Wrapper to retrieve psoc priv obj + * @psoc: psoc pointer + * + * Wrapper for pkt_capture to get psoc private object pointer. + * + * Return: pkt_capture psoc private object + */ +static inline struct pkt_psoc_priv * +pkt_capture_psoc_get_priv(struct wlan_objmgr_psoc *psoc) +{ + struct pkt_psoc_priv *psoc_priv; + + psoc_priv = wlan_objmgr_psoc_get_comp_private_obj(psoc, + WLAN_UMAC_COMP_PKT_CAPTURE); + QDF_BUG(psoc_priv); + + return psoc_priv; +} +#endif /* _WLAN_PKT_CAPTURE_OBJMGR_H */ diff --git a/drivers/staging/qcacld-3.0/components/pkt_capture/core/inc/wlan_pkt_capture_priv.h b/drivers/staging/qcacld-3.0/components/pkt_capture/core/inc/wlan_pkt_capture_priv.h new file mode 100644 index 000000000000..e23cd4dfe672 --- /dev/null +++ b/drivers/staging/qcacld-3.0/components/pkt_capture/core/inc/wlan_pkt_capture_priv.h @@ -0,0 +1,97 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/** + * DOC: Declare private API which shall be used internally only + * in pkt_capture component. This file shall include prototypes of + * pkt_capture parsing and send logic. + * + * Note: This API should be never accessed out of pkt_capture component. + */ + +#ifndef _WLAN_PKT_CAPTURE_PRIV_STRUCT_H_ +#define _WLAN_PKT_CAPTURE_PRIV_STRUCT_H_ + +#include "wlan_pkt_capture_objmgr.h" +#include "wlan_pkt_capture_public_structs.h" +#include "wlan_pkt_capture_mon_thread.h" + +/** + * struct wlan_pkt_capture_tx_ops - structure of tx operation function + * pointers for packet capture component + * @pkt_capture_send_mode: send packet capture mode + * + */ +struct wlan_pkt_capture_tx_ops { + QDF_STATUS (*pkt_capture_send_mode)(struct wlan_objmgr_psoc *psoc, + uint8_t vdev_id, + enum pkt_capture_mode mode); +}; + +/** + * struct wlan_pkt_capture_rx_ops - structure of rx operation function + * pointers for packet capture component + * @pkt_capture_register_mgmt_data_offload_event: register mgmt offload event + */ +struct wlan_pkt_capture_rx_ops { + QDF_STATUS (*pkt_capture_register_mgmt_data_offload_event) + (struct wlan_objmgr_psoc *psoc); +}; + +/** + * struct pkt_capture_cb_context - packet capture callback context + * @mon_cb: monitor callback function pointer + * @mon_ctx: monitor callback context + * @pkt_capture_mode: packet capture mode + */ +struct pkt_capture_cb_context { + QDF_STATUS (*mon_cb)(void *, qdf_nbuf_t); + void *mon_ctx; + enum pkt_capture_mode pkt_capture_mode; +}; + +/** + * struct pkt_capture_vdev_priv - Private object to be stored in vdev + * @vdev: pointer to vdev object + * @mon_ctx: pointer to packet capture mon context + * @cb_ctx: pointer to packet capture mon callback context + * @rx_ops: rx ops + * @tx_ops: tx ops + * @is_ops_registered: is tx and rx ops registered + */ +struct pkt_capture_vdev_priv { + struct wlan_objmgr_vdev *vdev; + struct pkt_capture_mon_context *mon_ctx; + struct pkt_capture_cb_context *cb_ctx; + struct wlan_pkt_capture_rx_ops rx_ops; + struct wlan_pkt_capture_tx_ops tx_ops; + bool is_ops_registered; +}; + +/** + * struct pkt_psoc_priv - Private object to be stored in psoc + * @psoc: pointer to psoc object + * @cfg_param: INI config params for packet capture + * @cb_obj: struct contaning callback pointers + */ +struct pkt_psoc_priv { + struct wlan_objmgr_psoc *psoc; + struct pkt_capture_cfg cfg_param; + struct pkt_capture_callbacks cb_obj; +}; +#endif /* End of _WLAN_PKT_CAPTURE_PRIV_STRUCT_H_ */ diff --git a/drivers/staging/qcacld-3.0/components/pkt_capture/core/src/wlan_pkt_capture_data_txrx.c b/drivers/staging/qcacld-3.0/components/pkt_capture/core/src/wlan_pkt_capture_data_txrx.c new file mode 100644 index 000000000000..364d92636c09 --- /dev/null +++ b/drivers/staging/qcacld-3.0/components/pkt_capture/core/src/wlan_pkt_capture_data_txrx.c @@ -0,0 +1,881 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/** + * DOC: Implement various notification handlers which are accessed + * internally in pkt_capture component only. + */ + +#include +#include +#include +#include +#include +#include +#include + +#define RESERVE_BYTES (100) + +/** + * pkt_capture_txrx_status_map() - map Tx status for data packets + * with packet capture Tx status + * @status: Tx status + * + * Return: pkt_capture_tx_status enum + */ +static enum pkt_capture_tx_status +pkt_capture_txrx_status_map(uint8_t status) +{ + enum pkt_capture_tx_status tx_status; + + switch (status) { + case htt_tx_status_ok: + tx_status = pkt_capture_tx_status_ok; + break; + case htt_tx_status_no_ack: + tx_status = pkt_capture_tx_status_no_ack; + break; + default: + tx_status = pkt_capture_tx_status_discard; + break; + } + + return tx_status; +} + +/** + * pkt_capture_get_tx_rate() - get tx rate for tx packet + * @preamble_type: preamble type + * @rate: rate code + * @preamble: preamble + * + * Return: rate + */ +static unsigned char pkt_capture_get_tx_rate( + uint8_t preamble_type, + uint8_t rate, + uint8_t *preamble) +{ + char ret = 0x0; + *preamble = LONG_PREAMBLE; + + if (preamble_type == 0) { + switch (rate) { + case 0x0: + ret = 0x60; + break; + case 0x1: + ret = 0x30; + break; + case 0x2: + ret = 0x18; + break; + case 0x3: + ret = 0x0c; + break; + case 0x4: + ret = 0x6c; + break; + case 0x5: + ret = 0x48; + break; + case 0x6: + ret = 0x24; + break; + case 0x7: + ret = 0x12; + break; + default: + break; + } + } else if (preamble_type == 1) { + switch (rate) { + case 0x0: + ret = 0x16; + *preamble = LONG_PREAMBLE; + case 0x1: + ret = 0xB; + *preamble = LONG_PREAMBLE; + break; + case 0x2: + ret = 0x4; + *preamble = LONG_PREAMBLE; + break; + case 0x3: + ret = 0x2; + *preamble = LONG_PREAMBLE; + break; + case 0x4: + ret = 0x16; + *preamble = SHORT_PREAMBLE; + break; + case 0x5: + ret = 0xB; + *preamble = SHORT_PREAMBLE; + break; + case 0x6: + ret = 0x4; + *preamble = SHORT_PREAMBLE; + break; + default: + break; + } + } else { + qdf_print("Invalid rate info\n"); + } + return ret; +} + +/** + * pkt_capture_tx_get_phy_info() - get phy info for tx packets for pkt + * capture mode(normal tx + offloaded tx) to prepare radiotap header + * @pktcapture_hdr: tx data header + * @tx_status: tx status to be updated with phy info + * + * Return: none + */ +static void pkt_capture_tx_get_phy_info( + struct pkt_capture_tx_hdr_elem_t *pktcapture_hdr, + struct mon_rx_status *tx_status) +{ + uint8_t preamble = 0; + uint8_t preamble_type = pktcapture_hdr->preamble; + uint8_t mcs = 0, bw = 0; + uint16_t vht_flags = 0, ht_flags = 0; + + switch (preamble_type) { + case 0x0: + case 0x1: + /* legacy */ + tx_status->rate = pkt_capture_get_tx_rate( + preamble_type, + pktcapture_hdr->rate, + &preamble); + break; + case 0x2: + ht_flags = 1; + bw = pktcapture_hdr->bw; + if (pktcapture_hdr->nss == 2) + mcs = 8 + pktcapture_hdr->mcs; + else + mcs = pktcapture_hdr->mcs; + break; + case 0x3: + vht_flags = 1; + bw = pktcapture_hdr->bw; + mcs = pktcapture_hdr->mcs; + + /* fallthrough */ + default: + break; + } + + tx_status->mcs = mcs; + tx_status->bw = bw; + tx_status->nr_ant = pktcapture_hdr->nss; + tx_status->is_stbc = pktcapture_hdr->stbc; + tx_status->sgi = pktcapture_hdr->sgi; + tx_status->ldpc = pktcapture_hdr->ldpc; + tx_status->beamformed = pktcapture_hdr->beamformed; + tx_status->vht_flag_values3[0] = mcs << 0x4 | (pktcapture_hdr->nss + 1); + tx_status->ht_flags = ht_flags; + tx_status->vht_flags = vht_flags; + tx_status->rtap_flags |= ((preamble == 1) ? BIT(1) : 0); + if (bw == 0) + tx_status->vht_flag_values2 = 0; + else if (bw == 1) + tx_status->vht_flag_values2 = 1; + else if (bw == 2) + tx_status->vht_flag_values2 = 4; +} + +/** + * pkt_capture_update_tx_status() - tx status for tx packets, for + * pkt capture mode(normal tx + offloaded tx) to prepare radiotap header + * @pdev: device handler + * @tx_status: tx status to be updated + * @mon_hdr: tx data header + * + * Return: none + */ +static void +pkt_capture_update_tx_status( + htt_pdev_handle pdev, + struct mon_rx_status *tx_status, + struct pkt_capture_tx_hdr_elem_t *pktcapture_hdr) +{ + struct mon_channel *ch_info = &pdev->mon_ch_info; + uint16_t channel_flags = 0; + + tx_status->tsft = (u_int64_t)(pktcapture_hdr->timestamp); + tx_status->chan_freq = ch_info->ch_freq; + tx_status->chan_num = ch_info->ch_num; + + pkt_capture_tx_get_phy_info(pktcapture_hdr, tx_status); + + if (pktcapture_hdr->preamble == 0) + channel_flags |= IEEE80211_CHAN_OFDM; + else if (pktcapture_hdr->preamble == 1) + channel_flags |= IEEE80211_CHAN_CCK; + + channel_flags |= + (WLAN_REG_CHAN_TO_BAND(ch_info->ch_num) == BAND_2G ? + IEEE80211_CHAN_2GHZ : IEEE80211_CHAN_5GHZ); + + tx_status->chan_flags = channel_flags; + tx_status->ant_signal_db = pktcapture_hdr->rssi_comb; + tx_status->rssi_comb = pktcapture_hdr->rssi_comb; + tx_status->tx_status = pktcapture_hdr->status; + tx_status->tx_retry_cnt = pktcapture_hdr->tx_retry_cnt; + tx_status->add_rtap_ext = true; +} + +/** + * pkt_capture_rx_convert8023to80211() - convert 802.3 packet to 802.11 + * format from rx desc + * @bssid: bssid + * @msdu: netbuf + * @desc: rx desc + * + * Return: none + */ +static void +pkt_capture_rx_convert8023to80211(uint8_t *bssid, qdf_nbuf_t msdu, void *desc) +{ + struct ethernet_hdr_t *eth_hdr; + struct llc_snap_hdr_t *llc_hdr; + struct ieee80211_frame *wh; + uint8_t hdsize, new_hdsize; + struct ieee80211_qoscntl *qos_cntl; + uint16_t seq_no; + uint8_t localbuf[sizeof(struct ieee80211_qosframe_htc_addr4) + + sizeof(struct llc_snap_hdr_t)]; + const uint8_t ethernet_II_llc_snap_header_prefix[] = { + 0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00 }; + uint16_t ether_type; + + struct htt_host_rx_desc_base *rx_desc = desc; + + eth_hdr = (struct ethernet_hdr_t *)qdf_nbuf_data(msdu); + hdsize = sizeof(struct ethernet_hdr_t); + wh = (struct ieee80211_frame *)localbuf; + + wh->i_fc[0] = IEEE80211_FC0_VERSION_0 | IEEE80211_FC0_TYPE_DATA; + *(uint16_t *)wh->i_dur = 0; + + new_hdsize = 0; + + /* DA , BSSID , SA */ + qdf_mem_copy(wh->i_addr1, eth_hdr->dest_addr, + QDF_MAC_ADDR_SIZE); + qdf_mem_copy(wh->i_addr2, bssid, + QDF_MAC_ADDR_SIZE); + qdf_mem_copy(wh->i_addr3, eth_hdr->src_addr, + QDF_MAC_ADDR_SIZE); + + wh->i_fc[1] = IEEE80211_FC1_DIR_FROMDS; + + if (rx_desc->attention.more_data) + wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA; + + if (rx_desc->attention.power_mgmt) + wh->i_fc[1] |= IEEE80211_FC1_PWR_MGT; + + if (rx_desc->attention.fragment) + wh->i_fc[1] |= IEEE80211_FC1_MORE_FRAG; + + if (rx_desc->attention.order) + wh->i_fc[1] |= IEEE80211_FC1_ORDER; + + if (rx_desc->mpdu_start.retry) + wh->i_fc[1] |= IEEE80211_FC1_RETRY; + + seq_no = rx_desc->mpdu_start.seq_num; + seq_no = (seq_no << IEEE80211_SEQ_SEQ_SHIFT) & IEEE80211_SEQ_SEQ_MASK; + qdf_mem_copy(wh->i_seq, &seq_no, sizeof(seq_no)); + + new_hdsize = sizeof(struct ieee80211_frame); + + if (rx_desc->attention.non_qos == 0) { + qos_cntl = + (struct ieee80211_qoscntl *)(localbuf + new_hdsize); + qos_cntl->i_qos[0] = + (rx_desc->mpdu_start.tid & IEEE80211_QOS_TID); + wh->i_fc[0] |= QDF_IEEE80211_FC0_SUBTYPE_QOS; + + qos_cntl->i_qos[1] = 0; + new_hdsize += sizeof(struct ieee80211_qoscntl); + } + + /* + * Prepare llc Header + */ + llc_hdr = (struct llc_snap_hdr_t *)(localbuf + new_hdsize); + ether_type = (eth_hdr->ethertype[0] << 8) | + (eth_hdr->ethertype[1]); + if (ether_type >= ETH_P_802_3_MIN) { + qdf_mem_copy(llc_hdr, + ethernet_II_llc_snap_header_prefix, + sizeof + (ethernet_II_llc_snap_header_prefix)); + if (ether_type == ETHERTYPE_AARP || + ether_type == ETHERTYPE_IPX) { + llc_hdr->org_code[2] = + BTEP_SNAP_ORGCODE_2; + /* 0xf8; bridge tunnel header */ + } + llc_hdr->ethertype[0] = eth_hdr->ethertype[0]; + llc_hdr->ethertype[1] = eth_hdr->ethertype[1]; + new_hdsize += sizeof(struct llc_snap_hdr_t); + } + + /* + * Remove 802.3 Header by adjusting the head + */ + qdf_nbuf_pull_head(msdu, hdsize); + + /* + * Adjust the head and prepare 802.11 Header + */ + qdf_nbuf_push_head(msdu, new_hdsize); + qdf_mem_copy(qdf_nbuf_data(msdu), localbuf, new_hdsize); +} + +void pkt_capture_rx_in_order_drop_offload_pkt(qdf_nbuf_t head_msdu) +{ + while (head_msdu) { + qdf_nbuf_t msdu = head_msdu; + + head_msdu = qdf_nbuf_next(head_msdu); + qdf_nbuf_free(msdu); + } +} + +bool pkt_capture_rx_in_order_offloaded_pkt(qdf_nbuf_t rx_ind_msg) +{ + uint32_t *msg_word; + + msg_word = (uint32_t *)qdf_nbuf_data(rx_ind_msg); + + /* check if it is for offloaded data pkt */ + return HTT_RX_IN_ORD_PADDR_IND_PKT_CAPTURE_MODE_IS_MONITOR_SET + (*(msg_word + 1)); +} + +void pkt_capture_msdu_process_pkts( + uint8_t *bssid, + qdf_nbuf_t head_msdu, + uint8_t vdev_id, htt_pdev_handle pdev) +{ + qdf_nbuf_t loop_msdu, pktcapture_msdu; + qdf_nbuf_t msdu, prev = NULL; + + pktcapture_msdu = NULL; + loop_msdu = head_msdu; + while (loop_msdu) { + msdu = qdf_nbuf_copy(loop_msdu); + + if (msdu) { + qdf_nbuf_push_head(msdu, + HTT_RX_STD_DESC_RESERVATION); + qdf_nbuf_set_next(msdu, NULL); + + if (!(pktcapture_msdu)) { + pktcapture_msdu = msdu; + prev = msdu; + } else { + qdf_nbuf_set_next(prev, msdu); + prev = msdu; + } + } + loop_msdu = qdf_nbuf_next(loop_msdu); + } + + if (!pktcapture_msdu) + return; + + pkt_capture_datapkt_process( + vdev_id, pktcapture_msdu, + TXRX_PROCESS_TYPE_DATA_RX, 0, 0, + TXRX_PKTCAPTURE_PKT_FORMAT_8023, + bssid, pdev, 0); +} + +/** + * pkt_capture_rx_data_cb(): callback to process data rx packets + * for pkt capture mode. (normal rx + offloaded rx) + * @context: objmgr vdev + * @ppdev: device handler + * @nbuf_list: netbuf list + * @vdev_id: vdev id for which packet is captured + * @tid: tid number + * @status: Tx status + * @pkt_format: Frame format + * @bssid: bssid + * @tx_retry_cnt: tx retry count + * + * Return: none + */ +static void +pkt_capture_rx_data_cb( + void *context, void *ppdev, void *nbuf_list, + uint8_t vdev_id, uint8_t tid, + uint8_t status, bool pkt_format, + uint8_t *bssid, uint8_t tx_retry_cnt) +{ + struct pkt_capture_vdev_priv *vdev_priv; + qdf_nbuf_t buf_list = (qdf_nbuf_t)nbuf_list; + struct wlan_objmgr_vdev *vdev = context; + htt_pdev_handle pdev = ppdev; + struct pkt_capture_cb_context *cb_ctx; + qdf_nbuf_t msdu, next_buf; + uint8_t drop_count; + struct htt_host_rx_desc_base *rx_desc; + struct mon_rx_status rx_status = {0}; + uint32_t headroom; + static uint8_t preamble_type; + static uint32_t vht_sig_a_1; + static uint32_t vht_sig_a_2; + + vdev_priv = pkt_capture_vdev_get_priv(vdev); + if (qdf_unlikely(!vdev)) + goto free_buf; + + cb_ctx = vdev_priv->cb_ctx; + if (!cb_ctx || !cb_ctx->mon_cb || !cb_ctx->mon_ctx) + goto free_buf; + + msdu = buf_list; + while (msdu) { + struct ethernet_hdr_t *eth_hdr; + + next_buf = qdf_nbuf_queue_next(msdu); + qdf_nbuf_set_next(msdu, NULL); /* Add NULL terminator */ + + rx_desc = htt_rx_desc(msdu); + + /* + * Only the first mpdu has valid preamble type, so use it + * till the last mpdu is reached + */ + if (rx_desc->attention.first_mpdu) { + preamble_type = rx_desc->ppdu_start.preamble_type; + if (preamble_type == 8 || preamble_type == 9 || + preamble_type == 0x0c || preamble_type == 0x0d) { + vht_sig_a_1 = VHT_SIG_A_1(rx_desc); + vht_sig_a_2 = VHT_SIG_A_2(rx_desc); + } + } else { + rx_desc->ppdu_start.preamble_type = preamble_type; + if (preamble_type == 8 || preamble_type == 9 || + preamble_type == 0x0c || preamble_type == 0x0d) { + VHT_SIG_A_1(rx_desc) = vht_sig_a_1; + VHT_SIG_A_2(rx_desc) = vht_sig_a_2; + } + } + + if (rx_desc->attention.last_mpdu) { + preamble_type = 0; + vht_sig_a_1 = 0; + vht_sig_a_2 = 0; + } + + qdf_nbuf_pull_head(msdu, HTT_RX_STD_DESC_RESERVATION); + + /* + * Get the channel info and update the rx status + */ + + /* need to update this to fill rx_status*/ + htt_rx_mon_get_rx_status(pdev, rx_desc, &rx_status); + rx_status.chan_noise_floor = NORMALIZED_TO_NOISE_FLOOR; + rx_status.tx_status = status; + rx_status.tx_retry_cnt = tx_retry_cnt; + rx_status.add_rtap_ext = true; + + /* clear IEEE80211_RADIOTAP_F_FCS flag*/ + rx_status.rtap_flags &= ~(BIT(4)); + rx_status.rtap_flags &= ~(BIT(2)); + + /* + * convert 802.3 header format into 802.11 format + */ + if (vdev_id == HTT_INVALID_VDEV) { + eth_hdr = (struct ethernet_hdr_t *)qdf_nbuf_data(msdu); + qdf_mem_copy(bssid, eth_hdr->src_addr, + QDF_MAC_ADDR_SIZE); + } + + pkt_capture_rx_convert8023to80211(bssid, msdu, rx_desc); + + /* + * Calculate the headroom and adjust head + * to prepare radiotap header. + */ + headroom = qdf_nbuf_headroom(msdu); + qdf_nbuf_update_radiotap(&rx_status, msdu, headroom); + + if (QDF_STATUS_SUCCESS != + cb_ctx->mon_cb(cb_ctx->mon_ctx, msdu)) { + pkt_capture_err("Frame Rx to HDD failed"); + qdf_nbuf_free(msdu); + } + msdu = next_buf; + } + + return; + +free_buf: + drop_count = pkt_capture_drop_nbuf_list(buf_list); +} + +/** + * pkt_capture_tx_data_cb() - process data tx and rx packets + * for pkt capture mode. (normal tx/rx + offloaded tx/rx) + * @vdev_id: vdev id for which packet is captured + * @mon_buf_list: netbuf list + * @type: data process type + * @tid: tid number + * @status: Tx status + * @pktformat: Frame format + * @bssid: bssid + * @pdev: pdev handle + * @tx_retry_cnt: tx retry count + * + * Return: none + */ +static void +pkt_capture_tx_data_cb( + void *context, void *ppdev, void *nbuf_list, uint8_t vdev_id, + uint8_t tid, uint8_t status, bool pkt_format, + uint8_t *bssid, uint8_t tx_retry_cnt) +{ + qdf_nbuf_t msdu, next_buf; + struct pkt_capture_vdev_priv *vdev_priv; + struct wlan_objmgr_vdev *vdev = context; + htt_pdev_handle pdev = ppdev; + struct pkt_capture_cb_context *cb_ctx; + uint8_t drop_count; + struct htt_tx_data_hdr_information *cmpl_desc = NULL; + struct pkt_capture_tx_hdr_elem_t pktcapture_hdr = {0}; + struct ethernet_hdr_t *eth_hdr; + struct llc_snap_hdr_t *llc_hdr; + struct ieee80211_frame *wh; + uint8_t hdsize, new_hdsize; + struct ieee80211_qoscntl *qos_cntl; + uint16_t ether_type; + uint32_t headroom; + uint16_t seq_no, fc_ctrl; + struct mon_rx_status tx_status = {0}; + uint8_t localbuf[sizeof(struct ieee80211_qosframe_htc_addr4) + + sizeof(struct llc_snap_hdr_t)]; + const uint8_t ethernet_II_llc_snap_header_prefix[] = { + 0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00 }; + + vdev_priv = pkt_capture_vdev_get_priv(vdev); + if (qdf_unlikely(!vdev)) + goto free_buf; + + cb_ctx = vdev_priv->cb_ctx; + if (!cb_ctx || !cb_ctx->mon_cb || !cb_ctx->mon_ctx) + goto free_buf; + + msdu = nbuf_list; + while (msdu) { + next_buf = qdf_nbuf_queue_next(msdu); + qdf_nbuf_set_next(msdu, NULL); /* Add NULL terminator */ + + cmpl_desc = (struct htt_tx_data_hdr_information *) + (qdf_nbuf_data(msdu)); + + pktcapture_hdr.timestamp = cmpl_desc->phy_timestamp_l32; + pktcapture_hdr.preamble = cmpl_desc->preamble; + pktcapture_hdr.mcs = cmpl_desc->mcs; + pktcapture_hdr.bw = cmpl_desc->bw; + pktcapture_hdr.nss = cmpl_desc->nss; + pktcapture_hdr.rssi_comb = cmpl_desc->rssi; + pktcapture_hdr.rate = cmpl_desc->rate; + pktcapture_hdr.stbc = cmpl_desc->stbc; + pktcapture_hdr.sgi = cmpl_desc->sgi; + pktcapture_hdr.ldpc = cmpl_desc->ldpc; + pktcapture_hdr.beamformed = cmpl_desc->beamformed; + pktcapture_hdr.status = status; + pktcapture_hdr.tx_retry_cnt = tx_retry_cnt; + + qdf_nbuf_pull_head( + msdu, + sizeof(struct htt_tx_data_hdr_information)); + + if (pkt_format == TXRX_PKTCAPTURE_PKT_FORMAT_8023) { + eth_hdr = (struct ethernet_hdr_t *)qdf_nbuf_data(msdu); + hdsize = sizeof(struct ethernet_hdr_t); + wh = (struct ieee80211_frame *)localbuf; + + *(uint16_t *)wh->i_dur = 0; + + new_hdsize = 0; + + if (vdev_id == HTT_INVALID_VDEV) + qdf_mem_copy(bssid, eth_hdr->dest_addr, + QDF_MAC_ADDR_SIZE); + + /* BSSID , SA , DA */ + qdf_mem_copy(wh->i_addr1, bssid, + QDF_MAC_ADDR_SIZE); + qdf_mem_copy(wh->i_addr2, eth_hdr->src_addr, + QDF_MAC_ADDR_SIZE); + qdf_mem_copy(wh->i_addr3, eth_hdr->dest_addr, + QDF_MAC_ADDR_SIZE); + + seq_no = cmpl_desc->seqno; + seq_no = (seq_no << IEEE80211_SEQ_SEQ_SHIFT) & + IEEE80211_SEQ_SEQ_MASK; + fc_ctrl = cmpl_desc->framectrl; + qdf_mem_copy(wh->i_fc, &fc_ctrl, sizeof(fc_ctrl)); + qdf_mem_copy(wh->i_seq, &seq_no, sizeof(seq_no)); + + wh->i_fc[1] &= ~IEEE80211_FC1_WEP; + + new_hdsize = sizeof(struct ieee80211_frame); + + if (wh->i_fc[0] & QDF_IEEE80211_FC0_SUBTYPE_QOS) { + qos_cntl = (struct ieee80211_qoscntl *) + (localbuf + new_hdsize); + qos_cntl->i_qos[0] = + (tid & IEEE80211_QOS_TID); + qos_cntl->i_qos[1] = 0; + new_hdsize += sizeof(struct ieee80211_qoscntl); + } + /* + * Prepare llc Header + */ + llc_hdr = (struct llc_snap_hdr_t *) + (localbuf + new_hdsize); + ether_type = (eth_hdr->ethertype[0] << 8) | + (eth_hdr->ethertype[1]); + if (ether_type >= ETH_P_802_3_MIN) { + qdf_mem_copy( + llc_hdr, + ethernet_II_llc_snap_header_prefix, + sizeof + (ethernet_II_llc_snap_header_prefix)); + if (ether_type == ETHERTYPE_AARP || + ether_type == ETHERTYPE_IPX) { + llc_hdr->org_code[2] = + BTEP_SNAP_ORGCODE_2; + /* 0xf8; bridge tunnel header */ + } + llc_hdr->ethertype[0] = eth_hdr->ethertype[0]; + llc_hdr->ethertype[1] = eth_hdr->ethertype[1]; + new_hdsize += sizeof(struct llc_snap_hdr_t); + } + + /* + * Remove 802.3 Header by adjusting the head + */ + qdf_nbuf_pull_head(msdu, hdsize); + + /* + * Adjust the head and prepare 802.11 Header + */ + qdf_nbuf_push_head(msdu, new_hdsize); + qdf_mem_copy(qdf_nbuf_data(msdu), localbuf, new_hdsize); + } + + pkt_capture_update_tx_status( + pdev, + &tx_status, + &pktcapture_hdr); + /* + * Calculate the headroom and adjust head + * to prepare radiotap header. + */ + headroom = qdf_nbuf_headroom(msdu); + qdf_nbuf_update_radiotap(&tx_status, msdu, headroom); + + if (QDF_STATUS_SUCCESS != + cb_ctx->mon_cb(cb_ctx->mon_ctx, msdu)) { + pkt_capture_err("Frame Tx to HDD failed"); + qdf_nbuf_free(msdu); + } + + msdu = next_buf; + } + return; + +free_buf: + drop_count = pkt_capture_drop_nbuf_list(nbuf_list); +} + +void pkt_capture_datapkt_process( + uint8_t vdev_id, + qdf_nbuf_t mon_buf_list, + enum pkt_capture_data_process_type type, + uint8_t tid, uint8_t status, bool pkt_format, + uint8_t *bssid, htt_pdev_handle pdev, + uint8_t tx_retry_cnt) +{ + uint8_t drop_count; + struct pkt_capture_mon_pkt *pkt; + pkt_capture_mon_thread_cb callback = NULL; + struct wlan_objmgr_vdev *vdev; + + status = pkt_capture_txrx_status_map(status); + vdev = pkt_capture_get_vdev(); + if (!vdev) + goto drop_rx_buf; + + pkt = pkt_capture_alloc_mon_pkt(vdev); + if (!pkt) + goto drop_rx_buf; + + switch (type) { + case TXRX_PROCESS_TYPE_DATA_RX: + callback = pkt_capture_rx_data_cb; + break; + case TXRX_PROCESS_TYPE_DATA_TX: + case TXRX_PROCESS_TYPE_DATA_TX_COMPL: + callback = pkt_capture_tx_data_cb; + break; + default: + return; + } + + pkt->callback = callback; + pkt->context = (void *)vdev; + pkt->pdev = (void *)pdev; + pkt->monpkt = (void *)mon_buf_list; + pkt->vdev_id = vdev_id; + pkt->tid = tid; + pkt->status = status; + pkt->pkt_format = pkt_format; + qdf_mem_copy(pkt->bssid, bssid, QDF_MAC_ADDR_SIZE); + pkt->tx_retry_cnt = tx_retry_cnt; + pkt_capture_indicate_monpkt(vdev, pkt); + return; + +drop_rx_buf: + drop_count = pkt_capture_drop_nbuf_list(mon_buf_list); +} + +struct htt_tx_data_hdr_information *pkt_capture_tx_get_txcomplete_data_hdr( + uint32_t *msg_word, + int num_msdus) +{ + int offset_dwords; + u_int32_t has_tx_tsf; + u_int32_t has_retry; + u_int32_t has_ack_rssi; + u_int32_t has_tx_tsf64; + u_int32_t has_tx_compl_payload; + struct htt_tx_compl_ind_append_retries *retry_list = NULL; + struct htt_tx_data_hdr_information *txcomplete_data_hrd_list = NULL; + + has_tx_compl_payload = HTT_TX_COMPL_IND_APPEND4_GET(*msg_word); + if (num_msdus <= 0 || !has_tx_compl_payload) + return NULL; + + offset_dwords = 1 + ((num_msdus + 1) >> 1); + + has_retry = HTT_TX_COMPL_IND_APPEND_GET(*msg_word); + if (has_retry) { + int retry_index = 0; + int width_for_each_retry = + (sizeof(struct htt_tx_compl_ind_append_retries) + + 3) >> 2; + + retry_list = (struct htt_tx_compl_ind_append_retries *) + (msg_word + offset_dwords); + while (retry_list) { + if (retry_list[retry_index++].flag == 0) + break; + } + offset_dwords += retry_index * width_for_each_retry; + } + has_tx_tsf = HTT_TX_COMPL_IND_APPEND1_GET(*msg_word); + if (has_tx_tsf) { + int width_for_each_tsf = + (sizeof(struct htt_tx_compl_ind_append_tx_tstamp)) >> 2; + offset_dwords += width_for_each_tsf * num_msdus; + } + + has_ack_rssi = HTT_TX_COMPL_IND_APPEND2_GET(*msg_word); + if (has_ack_rssi) + offset_dwords += ((num_msdus + 1) >> 1); + + has_tx_tsf64 = HTT_TX_COMPL_IND_APPEND3_GET(*msg_word); + if (has_tx_tsf64) + offset_dwords += (num_msdus << 1); + + txcomplete_data_hrd_list = (struct htt_tx_data_hdr_information *) + (msg_word + offset_dwords); + + return txcomplete_data_hrd_list; +} + +void pkt_capture_offload_deliver_indication_handler( + void *msg, uint8_t vdev_id, + uint8_t *bssid, htt_pdev_handle pdev) +{ + int nbuf_len; + qdf_nbuf_t netbuf; + uint8_t status; + uint8_t tid = 0; + bool pkt_format; + u_int32_t *msg_word = (u_int32_t *)msg; + u_int8_t *buf = (u_int8_t *)msg; + struct htt_tx_data_hdr_information *txhdr; + struct htt_tx_offload_deliver_ind_hdr_t *offload_deliver_msg; + + offload_deliver_msg = (struct htt_tx_offload_deliver_ind_hdr_t *)msg; + + txhdr = (struct htt_tx_data_hdr_information *) + (msg_word + 1); + + nbuf_len = offload_deliver_msg->tx_mpdu_bytes; + + netbuf = qdf_nbuf_alloc(NULL, + roundup(nbuf_len + RESERVE_BYTES, 4), + RESERVE_BYTES, 4, false); + + if (!netbuf) + return; + + qdf_nbuf_put_tail(netbuf, nbuf_len); + + qdf_mem_copy(qdf_nbuf_data(netbuf), + buf + sizeof(struct htt_tx_offload_deliver_ind_hdr_t), + nbuf_len); + + qdf_nbuf_push_head( + netbuf, + sizeof(struct htt_tx_data_hdr_information)); + + qdf_mem_copy(qdf_nbuf_data(netbuf), txhdr, + sizeof(struct htt_tx_data_hdr_information)); + + status = offload_deliver_msg->status; + pkt_format = offload_deliver_msg->format; + tid = offload_deliver_msg->tid_num; + + pkt_capture_datapkt_process( + vdev_id, + netbuf, TXRX_PROCESS_TYPE_DATA_TX, + tid, status, pkt_format, bssid, pdev, + offload_deliver_msg->tx_retry_cnt); +} diff --git a/drivers/staging/qcacld-3.0/components/pkt_capture/core/src/wlan_pkt_capture_main.c b/drivers/staging/qcacld-3.0/components/pkt_capture/core/src/wlan_pkt_capture_main.c new file mode 100644 index 000000000000..5b3747b68b46 --- /dev/null +++ b/drivers/staging/qcacld-3.0/components/pkt_capture/core/src/wlan_pkt_capture_main.c @@ -0,0 +1,467 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/** + * DOC: Implement various notification handlers which are accessed + * internally in pkt_capture component only. + */ + +#include "wlan_pkt_capture_main.h" +#include "wlan_pkt_capture_mon_thread.h" +#include "wlan_pkt_capture_mgmt_txrx.h" +#include "target_if_pkt_capture.h" +#include "cdp_txrx_ctrl.h" +#include "cds_utils.h" +#include "cdp_txrx_mon.h" + +static struct wlan_objmgr_vdev *gp_pkt_capture_vdev; + +struct wlan_objmgr_vdev *pkt_capture_get_vdev(void) +{ + return gp_pkt_capture_vdev; +} + +enum pkt_capture_mode pkt_capture_get_mode(struct wlan_objmgr_psoc *psoc) +{ + struct pkt_psoc_priv *psoc_priv; + + if (!psoc) { + pkt_capture_err("psoc is NULL"); + return PACKET_CAPTURE_MODE_DISABLE; + } + + psoc_priv = pkt_capture_psoc_get_priv(psoc); + if (!psoc_priv) { + pkt_capture_err("psoc_priv is NULL"); + return PACKET_CAPTURE_MODE_DISABLE; + } + + return psoc_priv->cfg_param.pkt_capture_mode; +} + +QDF_STATUS +pkt_capture_register_callbacks(struct wlan_objmgr_vdev *vdev, + QDF_STATUS (*mon_cb)(void *, qdf_nbuf_t), + void *context) +{ + struct pkt_capture_vdev_priv *vdev_priv; + QDF_STATUS status; + + if (!vdev) { + pkt_capture_err("vdev is NULL"); + return QDF_STATUS_E_INVAL; + } + + vdev_priv = pkt_capture_vdev_get_priv(vdev); + if (!vdev_priv) { + pkt_capture_err("vdev priv is NULL"); + return QDF_STATUS_E_INVAL; + } + + vdev_priv->cb_ctx->mon_cb = mon_cb; + vdev_priv->cb_ctx->mon_ctx = context; + + status = pkt_capture_mgmt_rx_ops(wlan_vdev_get_psoc(vdev), true); + if (QDF_IS_STATUS_ERROR(status)) { + pkt_capture_err("Failed to register pkt capture mgmt rx ops"); + return status; + } + + target_if_pkt_capture_register_tx_ops(&vdev_priv->tx_ops); + target_if_pkt_capture_register_rx_ops(&vdev_priv->rx_ops); + + return QDF_STATUS_SUCCESS; +} + +QDF_STATUS pkt_capture_deregister_callbacks(struct wlan_objmgr_vdev *vdev) +{ + struct pkt_capture_vdev_priv *vdev_priv; + QDF_STATUS status; + + if (!vdev) { + pkt_capture_err("vdev is NULL"); + return QDF_STATUS_E_INVAL; + } + + vdev_priv = pkt_capture_vdev_get_priv(vdev); + if (!vdev_priv) { + pkt_capture_err("vdev priv is NULL"); + return QDF_STATUS_E_INVAL; + } + + status = pkt_capture_mgmt_rx_ops(wlan_vdev_get_psoc(vdev), false); + if (QDF_IS_STATUS_ERROR(status)) + pkt_capture_err("Failed to unregister pkt capture mgmt rx ops"); + + vdev_priv->cb_ctx->mon_cb = NULL; + vdev_priv->cb_ctx->mon_ctx = NULL; + + return QDF_STATUS_SUCCESS; +} + +void pkt_capture_set_pktcap_mode(struct wlan_objmgr_psoc *psoc, + enum pkt_capture_mode mode) +{ + struct pkt_capture_vdev_priv *vdev_priv; + struct wlan_objmgr_vdev *vdev; + + if (!psoc) { + pkt_capture_err("psoc is NULL"); + return; + } + + vdev = wlan_objmgr_get_vdev_by_opmode_from_psoc(psoc, + QDF_STA_MODE, + WLAN_PKT_CAPTURE_ID); + if (!vdev) { + pkt_capture_err("vdev is NULL"); + return; + } + + vdev_priv = pkt_capture_vdev_get_priv(vdev); + if (vdev_priv) + vdev_priv->cb_ctx->pkt_capture_mode = mode; + else + pkt_capture_err("vdev_priv is NULL"); + + wlan_objmgr_vdev_release_ref(vdev, WLAN_PKT_CAPTURE_ID); +} + +enum pkt_capture_mode +pkt_capture_get_pktcap_mode(void) +{ + enum pkt_capture_mode mode = PACKET_CAPTURE_MODE_DISABLE; + struct pkt_capture_vdev_priv *vdev_priv; + struct wlan_objmgr_vdev *vdev; + struct wlan_objmgr_psoc *psoc; + + if (!gp_pkt_capture_vdev) { + pkt_capture_err("gp_pkt_capture_vdev is NULL"); + return PACKET_CAPTURE_MODE_DISABLE; + } + + psoc = wlan_vdev_get_psoc(gp_pkt_capture_vdev); + + + if (!psoc) { + pkt_capture_err("psoc is NULL"); + return 0; + } + + if (!pkt_capture_get_mode(psoc)) + return 0; + + vdev = wlan_objmgr_get_vdev_by_opmode_from_psoc(psoc, + QDF_STA_MODE, + WLAN_PKT_CAPTURE_ID); + if (!vdev) { + pkt_capture_err("vdev is NULL"); + return 0; + } + + vdev_priv = pkt_capture_vdev_get_priv(vdev); + if (!vdev_priv) + pkt_capture_err("vdev_priv is NULL"); + else + mode = vdev_priv->cb_ctx->pkt_capture_mode; + + wlan_objmgr_vdev_release_ref(vdev, WLAN_PKT_CAPTURE_ID); + return mode; +} + +/** + * pkt_capture_callback_ctx_create() - Create packet capture callback context + * @vdev_priv: pointer to packet capture vdev priv obj + * + * Return: QDF_STATUS + */ +static QDF_STATUS +pkt_capture_callback_ctx_create(struct pkt_capture_vdev_priv *vdev_priv) +{ + struct pkt_capture_cb_context *cb_ctx; + + cb_ctx = qdf_mem_malloc(sizeof(*cb_ctx)); + if (!cb_ctx) { + pkt_capture_err("MON context create failed"); + return QDF_STATUS_E_NOMEM; + } + + vdev_priv->cb_ctx = cb_ctx; + + return QDF_STATUS_SUCCESS; +} + +/** + * pkt_capture_callback_ctx_destroy() - Destroy packet capture callback context + * @vdev_priv: pointer to packet capture vdev priv obj + * + * Return: None + */ +static void +pkt_capture_callback_ctx_destroy(struct pkt_capture_vdev_priv *vdev_priv) +{ + qdf_mem_free(vdev_priv->cb_ctx); +} + +/** + * pkt_capture_mon_context_create() - Create packet capture mon context + * @vdev_priv: pointer to packet capture vdev priv obj + * + * This function allocates memory for packet capture mon context + * + * Return: QDF_STATUS + */ +static QDF_STATUS +pkt_capture_mon_context_create(struct pkt_capture_vdev_priv *vdev_priv) +{ + struct pkt_capture_mon_context *mon_context; + + mon_context = qdf_mem_malloc(sizeof(*mon_context)); + if (!mon_context) { + pkt_capture_err("MON context create failed"); + return QDF_STATUS_E_NOMEM; + } + + vdev_priv->mon_ctx = mon_context; + + return QDF_STATUS_SUCCESS; +} + +/** + * pkt_capture_mon_context_destroy() - Destroy packet capture mon context + * @vdev_priv: pointer to packet capture vdev priv obj + * + * Free packet capture mon context + * + * Return: None + */ +static void +pkt_capture_mon_context_destroy(struct pkt_capture_vdev_priv *vdev_priv) +{ + qdf_mem_free(vdev_priv->mon_ctx); +} + +uint32_t pkt_capture_drop_nbuf_list(qdf_nbuf_t buf_list) +{ + qdf_nbuf_t buf, next_buf; + uint32_t num_dropped = 0; + + buf = buf_list; + while (buf) { + QDF_NBUF_CB_RX_PEER_CACHED_FRM(buf) = 1; + next_buf = qdf_nbuf_queue_next(buf); + qdf_nbuf_free(buf); + buf = next_buf; + num_dropped++; + } + return num_dropped; +} + +QDF_STATUS pkt_capture_psoc_config(struct wlan_objmgr_psoc *psoc, + struct pkt_capture_cfg *cfg) +{ + struct pkt_psoc_priv *psoc_priv; + + if (!psoc) { + pkt_capture_err("psoc is NULL"); + return QDF_STATUS_E_FAILURE; + } + + psoc_priv = pkt_capture_psoc_get_priv(psoc); + if (!psoc_priv) { + pkt_capture_err("psoc_priv is NULL"); + return QDF_STATUS_E_FAILURE; + } + + memcpy(&psoc_priv->cfg_param, cfg, sizeof(*cfg)); + return QDF_STATUS_SUCCESS; +} + +QDF_STATUS +pkt_capture_vdev_create_notification(struct wlan_objmgr_vdev *vdev, void *arg) +{ + struct pkt_capture_mon_context *mon_ctx; + struct pkt_capture_vdev_priv *vdev_priv; + QDF_STATUS status; + + if ((wlan_vdev_mlme_get_opmode(vdev) != QDF_STA_MODE) || + !pkt_capture_get_mode(wlan_vdev_get_psoc(vdev))) + return QDF_STATUS_SUCCESS; + + vdev_priv = qdf_mem_malloc(sizeof(*vdev_priv)); + if (!vdev_priv) + return QDF_STATUS_E_NOMEM; + + status = wlan_objmgr_vdev_component_obj_attach( + vdev, + WLAN_UMAC_COMP_PKT_CAPTURE, + vdev_priv, QDF_STATUS_SUCCESS); + if (QDF_IS_STATUS_ERROR(status)) { + pkt_capture_err("Failed to attach vdev component obj"); + goto free_vdev_priv; + } + + vdev_priv->vdev = vdev; + gp_pkt_capture_vdev = vdev; + + status = pkt_capture_callback_ctx_create(vdev_priv); + if (!QDF_IS_STATUS_SUCCESS(status)) { + pkt_capture_err("Failed to create callback context"); + goto detach_vdev_priv; + } + + status = pkt_capture_mon_context_create(vdev_priv); + if (QDF_IS_STATUS_ERROR(status)) { + pkt_capture_err("Failed to create mon context"); + goto destroy_pkt_capture_cb_context; + } + + mon_ctx = vdev_priv->mon_ctx; + + status = pkt_capture_alloc_mon_thread(mon_ctx); + if (QDF_IS_STATUS_ERROR(status)) { + pkt_capture_err("Failed to alloc mon thread"); + goto destroy_mon_context; + } + + status = pkt_capture_open_mon_thread(mon_ctx); + if (QDF_IS_STATUS_ERROR(status)) { + pkt_capture_err("Failed to open mon thread"); + goto open_mon_thread_fail; + } + return status; + +open_mon_thread_fail: + pkt_capture_free_mon_pkt_freeq(mon_ctx); +destroy_mon_context: + pkt_capture_mon_context_destroy(vdev_priv); +destroy_pkt_capture_cb_context: + pkt_capture_callback_ctx_destroy(vdev_priv); +detach_vdev_priv: + wlan_objmgr_vdev_component_obj_detach(vdev, + WLAN_UMAC_COMP_PKT_CAPTURE, + vdev_priv); +free_vdev_priv: + qdf_mem_free(vdev_priv); + return status; +} + +QDF_STATUS +pkt_capture_vdev_destroy_notification(struct wlan_objmgr_vdev *vdev, void *arg) +{ + struct pkt_capture_vdev_priv *vdev_priv; + QDF_STATUS status; + + if ((wlan_vdev_mlme_get_opmode(vdev) != QDF_STA_MODE) || + !pkt_capture_get_mode(wlan_vdev_get_psoc(vdev))) + return QDF_STATUS_SUCCESS; + + vdev_priv = pkt_capture_vdev_get_priv(vdev); + if (!vdev_priv) { + pkt_capture_err("vdev priv is NULL"); + return QDF_STATUS_E_FAILURE; + } + + status = wlan_objmgr_vdev_component_obj_detach( + vdev, + WLAN_UMAC_COMP_PKT_CAPTURE, + vdev_priv); + if (QDF_IS_STATUS_ERROR(status)) + pkt_capture_err("Failed to detach vdev component obj"); + + pkt_capture_close_mon_thread(vdev_priv->mon_ctx); + pkt_capture_mon_context_destroy(vdev_priv); + pkt_capture_callback_ctx_destroy(vdev_priv); + qdf_mem_free(vdev_priv); + gp_pkt_capture_vdev = NULL; + return status; +} + +QDF_STATUS +pkt_capture_psoc_create_notification(struct wlan_objmgr_psoc *psoc, void *arg) +{ + struct pkt_psoc_priv *psoc_priv; + QDF_STATUS status; + + psoc_priv = qdf_mem_malloc(sizeof(*psoc_priv)); + if (!psoc_priv) + return QDF_STATUS_E_NOMEM; + + status = wlan_objmgr_psoc_component_obj_attach(psoc, + WLAN_UMAC_COMP_PKT_CAPTURE, + psoc_priv, QDF_STATUS_SUCCESS); + if (QDF_IS_STATUS_ERROR(status)) { + pkt_capture_err("Failed to attach psoc component obj"); + goto free_psoc_priv; + } + + psoc_priv->psoc = psoc; + + return status; + +free_psoc_priv: + qdf_mem_free(psoc_priv); + return status; +} + +QDF_STATUS +pkt_capture_psoc_destroy_notification(struct wlan_objmgr_psoc *psoc, void *arg) +{ + struct pkt_psoc_priv *psoc_priv; + QDF_STATUS status; + + psoc_priv = pkt_capture_psoc_get_priv(psoc); + if (!psoc_priv) { + pkt_capture_err("psoc priv is NULL"); + return QDF_STATUS_E_FAILURE; + } + + status = wlan_objmgr_psoc_component_obj_detach(psoc, + WLAN_UMAC_COMP_PKT_CAPTURE, + psoc_priv); + if (QDF_IS_STATUS_ERROR(status)) { + pkt_capture_err("Failed to detach psoc component obj"); + return status; + } + + qdf_mem_free(psoc_priv); + return status; +} + +void pkt_capture_record_channel(void) +{ + struct wlan_objmgr_pdev *pdev = wlan_vdev_get_pdev(gp_pkt_capture_vdev); + void *soc = cds_get_context(QDF_MODULE_ID_SOC); + uint32_t chan; + uint32_t ch_freq; + struct wlan_objmgr_psoc *psoc; + struct wlan_channel *des_chan; + + if (!gp_pkt_capture_vdev) { + pkt_capture_err("gp_pkt_capture_vdev is NULL"); + return; + } + + psoc = wlan_vdev_get_psoc(gp_pkt_capture_vdev); + + des_chan = gp_pkt_capture_vdev->vdev_mlme.des_chan; + ch_freq = des_chan->ch_freq; + chan = cds_freq_to_chan(ch_freq); + cdp_pktcapture_record_channel(soc, wlan_objmgr_pdev_get_pdev_id(pdev), + chan); +} diff --git a/drivers/staging/qcacld-3.0/components/pkt_capture/core/src/wlan_pkt_capture_mgmt_txrx.c b/drivers/staging/qcacld-3.0/components/pkt_capture/core/src/wlan_pkt_capture_mgmt_txrx.c new file mode 100644 index 000000000000..be2325a3b08e --- /dev/null +++ b/drivers/staging/qcacld-3.0/components/pkt_capture/core/src/wlan_pkt_capture_mgmt_txrx.c @@ -0,0 +1,467 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/** + * DOC: Implement mgmt txrx APIs which shall be used internally only + * in pkt_capture component. + * Note: These APIs should be never accessed out of pkt_capture component. + */ + +#include "wlan_pkt_capture_main.h" +#include "wlan_pkt_capture_priv.h" +#include "wlan_pkt_capture_mgmt_txrx.h" +#include "wlan_mlme_main.h" +#include "wlan_lmac_if_api.h" +#include "wlan_mgmt_txrx_utils_api.h" +#include "wlan_utility.h" +#include "wlan_reg_services_api.h" +#include "cds_ieee80211_common.h" +#include "wmi_unified.h" + +enum pkt_capture_tx_status +pkt_capture_mgmt_status_map(uint8_t status) +{ + enum pkt_capture_tx_status tx_status; + + switch (status) { + case WMI_MGMT_TX_COMP_TYPE_COMPLETE_OK: + tx_status = pkt_capture_tx_status_ok; + break; + case WMI_MGMT_TX_COMP_TYPE_COMPLETE_NO_ACK: + tx_status = pkt_capture_tx_status_no_ack; + break; + default: + tx_status = pkt_capture_tx_status_discard; + break; + } + + return tx_status; +} + +/** + * pkt_capture_mgmtpkt_cb() - callback to process management packets + * for pkt capture mode + * @context: vdev handler + * @nbuf_list: netbuf list + * @vdev_id: vdev id for which packet is captured + * @tid: tid number + * @status: Tx status + * @pkt_format: Frame format + * @tx_retry_cnt: tx retry count + * + * Return: none + */ +static void +pkt_capture_mgmtpkt_cb(void *context, void *ppdev, void *nbuf_list, + uint8_t vdev_id, uint8_t tid, uint8_t status, + bool pkt_format, uint8_t *bssid, uint8_t tx_retry_cnt) +{ + struct pkt_capture_vdev_priv *vdev_priv; + struct wlan_objmgr_psoc *psoc = context; + struct pkt_capture_cb_context *cb_ctx; + struct wlan_objmgr_vdev *vdev; + qdf_nbuf_t msdu, next_buf; + uint32_t drop_count; + + vdev = wlan_objmgr_get_vdev_by_opmode_from_psoc(psoc, + QDF_STA_MODE, + WLAN_PKT_CAPTURE_ID); + if (!vdev) { + pkt_capture_err("vdev is NULL"); + goto free_buf; + } + + vdev_priv = pkt_capture_vdev_get_priv(vdev); + if (!vdev_priv) { + pkt_capture_err("packet capture vdev priv is NULL"); + goto release_vdev_ref; + } + + cb_ctx = vdev_priv->cb_ctx; + if (!cb_ctx || !cb_ctx->mon_cb || !cb_ctx->mon_ctx) { + pkt_capture_err("mon cb params are NULL"); + goto release_vdev_ref; + } + + msdu = nbuf_list; + while (msdu) { + next_buf = qdf_nbuf_queue_next(msdu); + qdf_nbuf_set_next(msdu, NULL); /* Add NULL terminator */ + if (QDF_STATUS_SUCCESS != + cb_ctx->mon_cb(cb_ctx->mon_ctx, msdu)) { + pkt_capture_err("Frame Rx to HDD failed"); + qdf_nbuf_free(msdu); + } + msdu = next_buf; + } + + wlan_objmgr_vdev_release_ref(vdev, WLAN_PKT_CAPTURE_ID); + return; + +release_vdev_ref: + wlan_objmgr_vdev_release_ref(vdev, WLAN_PKT_CAPTURE_ID); +free_buf: + drop_count = pkt_capture_drop_nbuf_list(nbuf_list); + pkt_capture_debug("Dropped frames %u", drop_count); +} + +/** + * pkt_capture_mgmtpkt_process() - process management packets + * for pkt capture mode + * @psoc: pointer to psoc object + * @txrx_status: mon_rx_status to update radiotap header + * @nbuf: netbuf + * @status: Tx status + * + * Return: QDF_STATUS Enumeration + */ +static QDF_STATUS +pkt_capture_mgmtpkt_process(struct wlan_objmgr_psoc *psoc, + struct mon_rx_status *txrx_status, + qdf_nbuf_t nbuf, uint8_t status) +{ + struct wlan_objmgr_vdev *vdev; + struct pkt_capture_mon_pkt *pkt; + uint32_t headroom; + + vdev = wlan_objmgr_get_vdev_by_opmode_from_psoc(psoc, + QDF_STA_MODE, + WLAN_PKT_CAPTURE_ID); + if (!vdev) { + pkt_capture_err("vdev is NULL"); + return QDF_STATUS_E_FAILURE; + } + + /* + * Calculate the headroom and adjust head to prepare radiotap header + */ + headroom = qdf_nbuf_headroom(nbuf); + qdf_nbuf_update_radiotap(txrx_status, nbuf, headroom); + + pkt = pkt_capture_alloc_mon_pkt(vdev); + if (!pkt) { + wlan_objmgr_vdev_release_ref(vdev, WLAN_PKT_CAPTURE_ID); + return QDF_STATUS_E_FAILURE; + } + + pkt->callback = pkt_capture_mgmtpkt_cb; + pkt->context = psoc; + pkt->monpkt = nbuf; + pkt->vdev_id = WLAN_INVALID_VDEV_ID; + pkt->tid = WLAN_INVALID_TID; + pkt->status = status; + pkt->pkt_format = PKTCAPTURE_PKT_FORMAT_80211; + pkt_capture_indicate_monpkt(vdev, pkt); + + wlan_objmgr_vdev_release_ref(vdev, WLAN_PKT_CAPTURE_ID); + return QDF_STATUS_SUCCESS; +} + +QDF_STATUS +pkt_capture_process_mgmt_tx_data(struct wlan_objmgr_pdev *pdev, + struct mgmt_offload_event_params *params, + qdf_nbuf_t nbuf, + uint8_t status) +{ + struct mon_rx_status txrx_status = {0}; + struct pkt_psoc_priv *psoc_priv; + struct wlan_objmgr_vdev *vdev; + struct wlan_objmgr_psoc *psoc; + uint16_t channel_flags = 0; + struct ieee80211_frame *wh; + uint8_t sub_type; + uint8_t mgt_type, vdev_id; + int rmf_enabled; + + psoc = wlan_pdev_get_psoc(pdev); + if (!psoc) + return QDF_STATUS_E_FAILURE; + + psoc_priv = pkt_capture_psoc_get_priv(psoc); + if (!psoc_priv) { + pkt_capture_err("psoc priv is NULL"); + return QDF_STATUS_E_FAILURE; + } + + wh = (struct ieee80211_frame *)qdf_nbuf_data(nbuf); + + vdev = wlan_objmgr_get_vdev_by_macaddr_from_pdev(pdev, + wh->i_addr2, + WLAN_PKT_CAPTURE_ID); + if (!vdev) { + pkt_capture_err("vdev is NULL"); + return QDF_STATUS_E_FAILURE; + } + vdev_id = wlan_vdev_get_id(vdev); + wlan_objmgr_vdev_release_ref(vdev, WLAN_PKT_CAPTURE_ID); + + rmf_enabled = psoc_priv->cb_obj.get_rmf_status(vdev_id); + if (rmf_enabled < 0) { + pkt_capture_err("unable to get rmf status"); + return QDF_STATUS_E_FAILURE; + } + + mgt_type = (wh)->i_fc[0] & IEEE80211_FC0_TYPE_MASK; + sub_type = (wh)->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK; + + if (rmf_enabled && + (mgt_type == IEEE80211_FC0_TYPE_MGT) && + (sub_type == MGMT_SUBTYPE_DISASSOC || + sub_type == MGMT_SUBTYPE_DEAUTH || + sub_type == MGMT_SUBTYPE_ACTION)) { + uint8_t *orig_hdr; + uint8_t mic_len, hdr_len, pdev_id; + + if (!QDF_IS_ADDR_BROADCAST(wh->i_addr1) && + !IEEE80211_IS_MULTICAST(wh->i_addr1)) { + if ((wh)->i_fc[1] & IEEE80211_FC1_WEP) { + orig_hdr = (uint8_t *)qdf_nbuf_data(nbuf); + pdev_id = wlan_objmgr_pdev_get_pdev_id(pdev); + status = mlme_get_peer_mic_len(psoc, pdev_id, + wh->i_addr1, + &mic_len, + &hdr_len); + if (QDF_IS_STATUS_ERROR(status)) { + pkt_capture_err("Fail to get mic hdr"); + return QDF_STATUS_E_FAILURE; + } + + /* Strip privacy headers (and trailer) + * for a received frame + */ + qdf_mem_move(orig_hdr + + hdr_len, wh, + sizeof(*wh)); + qdf_nbuf_pull_head(nbuf, + hdr_len); + qdf_nbuf_trim_tail(nbuf, mic_len); + } + } else { + qdf_nbuf_trim_tail(nbuf, IEEE80211_MMIE_LEN); + } + } + + txrx_status.tsft = (u_int64_t)params->tsf_l32; + txrx_status.chan_num = wlan_freq_to_chan(params->chan_freq); + txrx_status.chan_freq = params->chan_freq; + /* params->rate is in Kbps, convert into Mbps */ + txrx_status.rate = (params->rate_kbps / 1000); + if (params->rssi == INVALID_RSSI_FOR_TX) + /* RSSI -128 is invalid rssi for TX, make it 0 here, + * will be normalized during radiotap updation + */ + txrx_status.ant_signal_db = 0; + else + txrx_status.ant_signal_db = params->rssi; + + txrx_status.rssi_comb = txrx_status.ant_signal_db; + txrx_status.nr_ant = 1; + txrx_status.rtap_flags |= + ((txrx_status.rate == 6 /* Mbps */) ? BIT(1) : 0); + channel_flags |= + ((txrx_status.rate == 6 /* Mbps */) ? + IEEE80211_CHAN_OFDM : IEEE80211_CHAN_CCK); + channel_flags |= + (WLAN_REG_CHAN_TO_BAND(txrx_status.chan_num) == BAND_2G ? + IEEE80211_CHAN_2GHZ : IEEE80211_CHAN_5GHZ); + txrx_status.chan_flags = channel_flags; + txrx_status.rate = ((txrx_status.rate == 6 /* Mbps */) ? 0x0c : 0x02); + txrx_status.tx_status = status; + txrx_status.tx_retry_cnt = params->tx_retry_cnt; + txrx_status.add_rtap_ext = true; + + wh = (struct ieee80211_frame *)qdf_nbuf_data(nbuf); + wh->i_fc[1] &= ~IEEE80211_FC1_WEP; + + return pkt_capture_mgmtpkt_process(psoc, &txrx_status, + nbuf, status); +} + +void pkt_capture_mgmt_tx(struct wlan_objmgr_pdev *pdev, + qdf_nbuf_t nbuf, + uint16_t chan_freq, + uint8_t preamble_type) +{ + qdf_nbuf_t wbuf; + int nbuf_len; + struct mgmt_offload_event_params params = {0}; + + if (!pdev) { + pkt_capture_err("pdev is NULL"); + return; + } + + nbuf_len = qdf_nbuf_len(nbuf); + wbuf = qdf_nbuf_alloc(NULL, roundup(nbuf_len + RESERVE_BYTES, 4), + RESERVE_BYTES, 4, false); + if (!wbuf) { + pkt_capture_err("Failed to allocate wbuf for mgmt len(%u)", + nbuf_len); + return; + } + + qdf_nbuf_put_tail(wbuf, nbuf_len); + qdf_mem_copy(qdf_nbuf_data(wbuf), qdf_nbuf_data(nbuf), nbuf_len); + + params.chan_freq = chan_freq; + /* + * Filling Tpc in rssi field. + * As Tpc is not available, filling with default value of tpc + */ + params.rssi = 0; + /* Assigning the local timestamp as TSF timestamp is not available*/ + params.tsf_l32 = (uint32_t)jiffies; + + if (preamble_type == (1 << WMI_RATE_PREAMBLE_CCK)) + params.rate_kbps = 1000; /* Rate is 1 Mbps for CCK */ + else + params.rate_kbps = 6000; /* Rate is 6 Mbps for OFDM */ + + /* + * The mgmt tx packet is send to mon interface before tx completion. + * we do not have status for this packet, using magic number(0xFF) + * as status for mgmt tx packet + */ + if (QDF_STATUS_SUCCESS != + pkt_capture_process_mgmt_tx_data(pdev, ¶ms, wbuf, 0xFF)) + qdf_nbuf_free(wbuf); +} + +void +pkt_capture_mgmt_tx_completion(struct wlan_objmgr_pdev *pdev, + uint32_t desc_id, + uint32_t status, + struct mgmt_offload_event_params *params) +{ + qdf_nbuf_t wbuf, nbuf; + int nbuf_len; + + if (!pdev) { + pkt_capture_err("pdev is NULL"); + return; + } + + nbuf = mgmt_txrx_get_nbuf(pdev, desc_id); + if (!nbuf) + return; + + nbuf_len = qdf_nbuf_len(nbuf); + wbuf = qdf_nbuf_alloc(NULL, roundup(nbuf_len + RESERVE_BYTES, 4), + RESERVE_BYTES, 4, false); + if (!wbuf) { + pkt_capture_err("Failed to allocate wbuf for mgmt len(%u)", + nbuf_len); + return; + } + + qdf_nbuf_put_tail(wbuf, nbuf_len); + qdf_mem_copy(qdf_nbuf_data(wbuf), qdf_nbuf_data(nbuf), nbuf_len); + + if (QDF_STATUS_SUCCESS != + pkt_capture_process_mgmt_tx_data( + pdev, params, wbuf, + pkt_capture_mgmt_status_map(status))) + qdf_nbuf_free(wbuf); +} + +/** + * process_pktcapture_mgmt_rx_data_cb() - process management rx packets + * @rx_params: mgmt rx event params + * @wbuf: netbuf + * + * Return: none + */ +static QDF_STATUS +pkt_capture_mgmt_rx_data_cb(struct wlan_objmgr_psoc *psoc, + struct wlan_objmgr_peer *peer, + qdf_nbuf_t wbuf, + struct mgmt_rx_event_params *rx_params, + enum mgmt_frame_type frm_type) +{ + struct mon_rx_status txrx_status = {0}; + uint16_t channel_flags = 0; + struct ieee80211_frame *wh; + qdf_nbuf_t nbuf; + int buf_len; + + if (!(pkt_capture_get_pktcap_mode() & PACKET_CAPTURE_MODE_MGMT_ONLY)) + return QDF_STATUS_E_FAILURE; + + buf_len = qdf_nbuf_len(wbuf); + nbuf = qdf_nbuf_alloc(NULL, roundup( + buf_len + RESERVE_BYTES, 4), + RESERVE_BYTES, 4, false); + if (!nbuf) + return QDF_STATUS_E_FAILURE; + + qdf_nbuf_put_tail(nbuf, buf_len); + qdf_mem_copy(qdf_nbuf_data(nbuf), qdf_nbuf_data(wbuf), buf_len); + + txrx_status.tsft = (u_int64_t)rx_params->tsf_delta; + txrx_status.chan_num = rx_params->channel; + txrx_status.chan_freq = wlan_chan_to_freq(txrx_status.chan_num); + /* rx_params->rate is in Kbps, convert into Mbps */ + txrx_status.rate = (rx_params->rate / 1000); + txrx_status.ant_signal_db = rx_params->snr; + txrx_status.rssi_comb = rx_params->snr; + txrx_status.chan_noise_floor = NORMALIZED_TO_NOISE_FLOOR; + txrx_status.nr_ant = 1; + txrx_status.rtap_flags |= + ((txrx_status.rate == 6 /* Mbps */) ? BIT(1) : 0); + channel_flags |= + ((txrx_status.rate == 6 /* Mbps */) ? + IEEE80211_CHAN_OFDM : IEEE80211_CHAN_CCK); + channel_flags |= + (WLAN_REG_CHAN_TO_BAND(txrx_status.chan_num) == BAND_2G ? + IEEE80211_CHAN_2GHZ : IEEE80211_CHAN_5GHZ); + txrx_status.chan_flags = channel_flags; + txrx_status.rate = ((txrx_status.rate == 6 /* Mbps */) ? 0x0c : 0x02); + txrx_status.add_rtap_ext = true; + + wh = (struct ieee80211_frame *)qdf_nbuf_data(nbuf); + wh->i_fc[1] &= ~IEEE80211_FC1_WEP; + + if (QDF_STATUS_SUCCESS != + pkt_capture_mgmtpkt_process(psoc, &txrx_status, nbuf, 0)) + qdf_nbuf_free(nbuf); + + return QDF_STATUS_SUCCESS; +} + +QDF_STATUS pkt_capture_mgmt_rx_ops(struct wlan_objmgr_psoc *psoc, + bool is_register) +{ + struct mgmt_txrx_mgmt_frame_cb_info frm_cb_info; + QDF_STATUS status; + int num_of_entries; + + frm_cb_info.frm_type = MGMT_FRAME_TYPE_ALL; + frm_cb_info.mgmt_rx_cb = pkt_capture_mgmt_rx_data_cb; + num_of_entries = 1; + + if (is_register) + status = wlan_mgmt_txrx_register_rx_cb( + psoc, WLAN_UMAC_COMP_PKT_CAPTURE, + &frm_cb_info, num_of_entries); + else + status = wlan_mgmt_txrx_deregister_rx_cb( + psoc, WLAN_UMAC_COMP_PKT_CAPTURE, + &frm_cb_info, num_of_entries); + + return status; +} diff --git a/drivers/staging/qcacld-3.0/components/pkt_capture/core/src/wlan_pkt_capture_mon_thread.c b/drivers/staging/qcacld-3.0/components/pkt_capture/core/src/wlan_pkt_capture_mon_thread.c new file mode 100644 index 000000000000..136fcf5f418e --- /dev/null +++ b/drivers/staging/qcacld-3.0/components/pkt_capture/core/src/wlan_pkt_capture_mon_thread.c @@ -0,0 +1,461 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/** + * DOC: Define internal APIs related to the packet capture component + */ + +#include "wlan_pkt_capture_priv.h" +#include + +void pkt_capture_free_mon_pkt_freeq(struct pkt_capture_mon_context *mon_ctx) +{ + struct pkt_capture_mon_pkt *pkt; + + spin_lock_bh(&mon_ctx->mon_pkt_freeq_lock); + while (!list_empty(&mon_ctx->mon_pkt_freeq)) { + pkt = list_entry((&mon_ctx->mon_pkt_freeq)->next, + typeof(*pkt), list); + list_del(&pkt->list); + spin_unlock_bh(&mon_ctx->mon_pkt_freeq_lock); + qdf_mem_free(pkt); + spin_lock_bh(&mon_ctx->mon_pkt_freeq_lock); + } + spin_unlock_bh(&mon_ctx->mon_pkt_freeq_lock); +} + +/** + * pkt_capture_alloc_mon_pkt_freeq() - Function to allocate free buffer queue + * @mon_ctx: pointer to packet capture mon context + * + * This API allocates MAX_MON_PKT_SIZE number of mon packets + * which are used for mon data processing. + * + * Return: QDF_STATUS + */ +static QDF_STATUS +pkt_capture_alloc_mon_pkt_freeq(struct pkt_capture_mon_context *mon_ctx) +{ + struct pkt_capture_mon_pkt *pkt, *tmp; + int i; + + for (i = 0; i < MAX_MON_PKT_SIZE; i++) { + pkt = qdf_mem_malloc(sizeof(*pkt)); + if (!pkt) { + pkt_capture_err("mon packet freeq allocation fail"); + goto free; + } + spin_lock_bh(&mon_ctx->mon_pkt_freeq_lock); + list_add_tail(&pkt->list, + &mon_ctx->mon_pkt_freeq); + spin_unlock_bh(&mon_ctx->mon_pkt_freeq_lock); + } + + return QDF_STATUS_SUCCESS; +free: + spin_lock_bh(&mon_ctx->mon_pkt_freeq_lock); + list_for_each_entry_safe(pkt, tmp, + &mon_ctx->mon_pkt_freeq, + list) { + list_del(&pkt->list); + spin_unlock_bh(&mon_ctx->mon_pkt_freeq_lock); + qdf_mem_free(pkt); + spin_lock_bh(&mon_ctx->mon_pkt_freeq_lock); + } + spin_unlock_bh(&mon_ctx->mon_pkt_freeq_lock); + + return QDF_STATUS_E_NOMEM; +} + +/** + * pkt_capture_free_mon_pkt() - api to release mon packet to the freeq + * @mon_ctx: Pointer to packet capture mon context + * @pkt: MON packet buffer to be returned to free queue. + * + * This api returns the mon packet used for mon data to the free queue + * + * Return: None + */ +static void +pkt_capture_free_mon_pkt(struct pkt_capture_mon_context *mon_ctx, + struct pkt_capture_mon_pkt *pkt) +{ + memset(pkt, 0, sizeof(*pkt)); + spin_lock_bh(&mon_ctx->mon_pkt_freeq_lock); + list_add_tail(&pkt->list, &mon_ctx->mon_pkt_freeq); + spin_unlock_bh(&mon_ctx->mon_pkt_freeq_lock); +} + +struct pkt_capture_mon_pkt * +pkt_capture_alloc_mon_pkt(struct wlan_objmgr_vdev *vdev) +{ + struct pkt_capture_vdev_priv *vdev_priv; + struct pkt_capture_mon_context *mon_ctx; + struct pkt_capture_mon_pkt *pkt; + + if (!vdev) { + pkt_capture_err("vdev is NULL"); + return NULL; + } + + vdev_priv = pkt_capture_vdev_get_priv(vdev); + if (!vdev_priv) { + pkt_capture_err("packet capture vdev priv is NULL"); + return NULL; + } + + mon_ctx = vdev_priv->mon_ctx; + if (!mon_ctx) { + pkt_capture_err("packet capture mon context is NULL"); + return NULL; + } + + spin_lock_bh(&mon_ctx->mon_pkt_freeq_lock); + if (list_empty(&mon_ctx->mon_pkt_freeq)) { + spin_unlock_bh(&mon_ctx->mon_pkt_freeq_lock); + return NULL; + } + + pkt = list_first_entry(&mon_ctx->mon_pkt_freeq, + struct pkt_capture_mon_pkt, list); + list_del(&pkt->list); + spin_unlock_bh(&mon_ctx->mon_pkt_freeq_lock); + + return pkt; +} + +void pkt_capture_indicate_monpkt(struct wlan_objmgr_vdev *vdev, + struct pkt_capture_mon_pkt *pkt) +{ + struct pkt_capture_vdev_priv *vdev_priv; + struct pkt_capture_mon_context *mon_ctx; + + if (!vdev) { + pkt_capture_err("vdev is NULL"); + return; + } + + vdev_priv = pkt_capture_vdev_get_priv(vdev); + if (!vdev_priv) { + pkt_capture_err("packet capture vdev priv is NULL"); + return; + } + mon_ctx = vdev_priv->mon_ctx; + + spin_lock_bh(&mon_ctx->mon_queue_lock); + list_add_tail(&pkt->list, &mon_ctx->mon_thread_queue); + spin_unlock_bh(&mon_ctx->mon_queue_lock); + set_bit(PKT_CAPTURE_RX_POST_EVENT, &mon_ctx->mon_event_flag); + wake_up_interruptible(&mon_ctx->mon_wait_queue); +} + +void pkt_capture_wakeup_mon_thread(struct wlan_objmgr_vdev *vdev) +{ + struct pkt_capture_vdev_priv *vdev_priv; + struct pkt_capture_mon_context *mon_ctx; + + if (!vdev) { + pkt_capture_err("vdev is NULL"); + return; + } + + vdev_priv = pkt_capture_vdev_get_priv(vdev); + if (!vdev_priv) { + pkt_capture_err("packet capture vdev priv is NULL"); + return; + } + mon_ctx = vdev_priv->mon_ctx; + + set_bit(PKT_CAPTURE_RX_POST_EVENT, &mon_ctx->mon_event_flag); + wake_up_interruptible(&mon_ctx->mon_wait_queue); +} + +/** + * pkt_capture_process_from_queue() - function to process pending mon packets + * @mon_ctx: Pointer to packet capture mon context + * + * This api traverses the pending buffer list and calling the callback. + * This callback would essentially send the packet to HDD. + * + * Return: None + */ +static void +pkt_capture_process_from_queue(struct pkt_capture_mon_context *mon_ctx) +{ + struct pkt_capture_mon_pkt *pkt; + uint8_t vdev_id; + uint8_t tid; + + spin_lock_bh(&mon_ctx->mon_queue_lock); + while (!list_empty(&mon_ctx->mon_thread_queue)) { + pkt = list_first_entry(&mon_ctx->mon_thread_queue, + struct pkt_capture_mon_pkt, list); + list_del(&pkt->list); + spin_unlock_bh(&mon_ctx->mon_queue_lock); + vdev_id = pkt->vdev_id; + tid = pkt->tid; + pkt->callback(pkt->context, pkt->pdev, pkt->monpkt, vdev_id, + tid, pkt->status, pkt->pkt_format, pkt->bssid, + pkt->tx_retry_cnt); + pkt_capture_free_mon_pkt(mon_ctx, pkt); + spin_lock_bh(&mon_ctx->mon_queue_lock); + } + spin_unlock_bh(&mon_ctx->mon_queue_lock); +} + +/** + * pkt_capture_mon_thread() - packet capture mon thread + * @arg: Pointer to vdev object manager + * + * This api is the thread handler for mon Data packet processing. + * + * Return: thread exit code + */ +static int pkt_capture_mon_thread(void *arg) +{ + struct pkt_capture_mon_context *mon_ctx; + unsigned long pref_cpu = 0; + bool shutdown = false; + int status, i; + + if (!arg) { + pkt_capture_err("Bad Args passed to mon thread"); + return 0; + } + mon_ctx = (struct pkt_capture_mon_context *)arg; + set_user_nice(current, -1); +#ifdef MSM_PLATFORM + set_wake_up_idle(true); +#endif + + /** + * Find the available cpu core other than cpu 0 and + * bind the thread + */ + for_each_online_cpu(i) { + if (i == 0) + continue; + pref_cpu = i; + break; + } + + set_cpus_allowed_ptr(current, cpumask_of(pref_cpu)); + + complete(&mon_ctx->mon_start_event); + + while (!shutdown) { + status = + wait_event_interruptible(mon_ctx->mon_wait_queue, + test_bit(PKT_CAPTURE_RX_POST_EVENT, + &mon_ctx->mon_event_flag) || + test_bit(PKT_CAPTURE_RX_SUSPEND_EVENT, + &mon_ctx->mon_event_flag)); + if (status == -ERESTARTSYS) + break; + + clear_bit(PKT_CAPTURE_RX_POST_EVENT, + &mon_ctx->mon_event_flag); + while (true) { + if (test_bit(PKT_CAPTURE_RX_SHUTDOWN_EVENT, + &mon_ctx->mon_event_flag)) { + clear_bit(PKT_CAPTURE_RX_SHUTDOWN_EVENT, + &mon_ctx->mon_event_flag); + if (test_bit( + PKT_CAPTURE_RX_SUSPEND_EVENT, + &mon_ctx->mon_event_flag)) { + clear_bit(PKT_CAPTURE_RX_SUSPEND_EVENT, + &mon_ctx->mon_event_flag); + complete(&mon_ctx->suspend_mon_event); + } + pkt_capture_info("Shutting down pktcap thread"); + shutdown = true; + break; + } + pkt_capture_process_from_queue(mon_ctx); + + if (test_bit(PKT_CAPTURE_RX_SUSPEND_EVENT, + &mon_ctx->mon_event_flag)) { + clear_bit(PKT_CAPTURE_RX_SUSPEND_EVENT, + &mon_ctx->mon_event_flag); + spin_lock(&mon_ctx->mon_thread_lock); + INIT_COMPLETION(mon_ctx->resume_mon_event); + complete(&mon_ctx->suspend_mon_event); + spin_unlock(&mon_ctx->mon_thread_lock); + wait_for_completion_interruptible + (&mon_ctx->resume_mon_event); + } + break; + } + } + pkt_capture_debug("Exiting packet capture mon thread"); + complete_and_exit(&mon_ctx->mon_shutdown, 0); + + return 0; +} + +void pkt_capture_close_mon_thread(struct pkt_capture_mon_context *mon_ctx) +{ + if (!mon_ctx->mon_thread) + return; + + /* Shut down Tlshim Rx thread */ + set_bit(PKT_CAPTURE_RX_SHUTDOWN_EVENT, + &mon_ctx->mon_event_flag); + set_bit(PKT_CAPTURE_RX_POST_EVENT, + &mon_ctx->mon_event_flag); + wake_up_interruptible(&mon_ctx->mon_wait_queue); + wait_for_completion(&mon_ctx->mon_shutdown); + mon_ctx->mon_thread = NULL; + pkt_capture_drop_monpkt(mon_ctx); + pkt_capture_free_mon_pkt_freeq(mon_ctx); +} + +QDF_STATUS +pkt_capture_open_mon_thread(struct pkt_capture_mon_context *mon_ctx) +{ + mon_ctx->mon_thread = kthread_create(pkt_capture_mon_thread, + mon_ctx, + "pkt_capture_mon_thread"); + + if (IS_ERR(mon_ctx->mon_thread)) { + pkt_capture_fatal("Could not Create packet capture mon thread"); + return QDF_STATUS_E_FAILURE; + } + wake_up_process(mon_ctx->mon_thread); + pkt_capture_debug("packet capture MON thread Created"); + + wait_for_completion_interruptible(&mon_ctx->mon_start_event); + pkt_capture_debug("packet capture MON Thread has started"); + + return QDF_STATUS_SUCCESS; +} + +void pkt_capture_drop_monpkt(struct pkt_capture_mon_context *mon_ctx) +{ + struct pkt_capture_mon_pkt *pkt, *tmp; + struct list_head local_list; + qdf_nbuf_t buf, next_buf; + + INIT_LIST_HEAD(&local_list); + spin_lock_bh(&mon_ctx->mon_queue_lock); + if (list_empty(&mon_ctx->mon_thread_queue)) { + spin_unlock_bh(&mon_ctx->mon_queue_lock); + return; + } + list_for_each_entry_safe(pkt, tmp, + &mon_ctx->mon_thread_queue, + list) + list_move_tail(&pkt->list, &local_list); + + spin_unlock_bh(&mon_ctx->mon_queue_lock); + + list_for_each_entry_safe(pkt, tmp, &local_list, list) { + list_del(&pkt->list); + buf = pkt->monpkt; + while (buf) { + next_buf = qdf_nbuf_queue_next(buf); + qdf_nbuf_free(buf); + buf = next_buf; + } + pkt_capture_free_mon_pkt(mon_ctx, pkt); + } +} + +int pkt_capture_suspend_mon_thread(struct wlan_objmgr_vdev *vdev) +{ + struct pkt_capture_vdev_priv *vdev_priv; + struct pkt_capture_mon_context *mon_ctx; + int rc; + + if (!vdev) { + pkt_capture_err("vdev is NULL"); + return -EINVAL; + } + + vdev_priv = pkt_capture_vdev_get_priv(vdev); + if (!vdev_priv) { + pkt_capture_err("packet capture vdev priv is NULL"); + return -EINVAL; + } + mon_ctx = vdev_priv->mon_ctx; + if (!mon_ctx) { + pkt_capture_err("packet capture mon context is NULL"); + return -EINVAL; + } + + set_bit(PKT_CAPTURE_RX_SUSPEND_EVENT, + &mon_ctx->mon_event_flag); + wake_up_interruptible(&mon_ctx->mon_wait_queue); + rc = wait_for_completion_timeout( + &mon_ctx->suspend_mon_event, + msecs_to_jiffies(PKT_CAPTURE_SUSPEND_TIMEOUT)); + if (!rc) { + clear_bit(PKT_CAPTURE_RX_SUSPEND_EVENT, + &mon_ctx->mon_event_flag); + pkt_capture_err("Failed to suspend packet capture mon thread"); + return -EINVAL; + } + mon_ctx->is_mon_thread_suspended = true; + + return 0; +} + +void pkt_capture_resume_mon_thread(struct wlan_objmgr_vdev *vdev) +{ + struct pkt_capture_vdev_priv *vdev_priv; + struct pkt_capture_mon_context *mon_ctx; + + if (!vdev) { + pkt_capture_err("vdev is NULL"); + return; + } + + vdev_priv = pkt_capture_vdev_get_priv(vdev); + if (!vdev_priv) { + pkt_capture_err("packet capture vdev priv is NULL"); + return; + } + mon_ctx = vdev_priv->mon_ctx; + if (!mon_ctx) { + pkt_capture_err("packet capture mon context is NULL"); + return; + } + + if (mon_ctx->is_mon_thread_suspended) + complete(&mon_ctx->resume_mon_event); +} + +QDF_STATUS +pkt_capture_alloc_mon_thread(struct pkt_capture_mon_context *mon_ctx) +{ + spin_lock_init(&mon_ctx->mon_thread_lock); + init_waitqueue_head(&mon_ctx->mon_wait_queue); + init_completion(&mon_ctx->mon_start_event); + init_completion(&mon_ctx->suspend_mon_event); + init_completion(&mon_ctx->resume_mon_event); + init_completion(&mon_ctx->mon_shutdown); + mon_ctx->mon_event_flag = 0; + spin_lock_init(&mon_ctx->mon_queue_lock); + spin_lock_init(&mon_ctx->mon_pkt_freeq_lock); + INIT_LIST_HEAD(&mon_ctx->mon_thread_queue); + spin_lock_bh(&mon_ctx->mon_pkt_freeq_lock); + INIT_LIST_HEAD(&mon_ctx->mon_pkt_freeq); + spin_unlock_bh(&mon_ctx->mon_pkt_freeq_lock); + + return pkt_capture_alloc_mon_pkt_freeq(mon_ctx); +} diff --git a/drivers/staging/qcacld-3.0/components/pkt_capture/dispatcher/inc/wlan_pkt_capture_public_structs.h b/drivers/staging/qcacld-3.0/components/pkt_capture/dispatcher/inc/wlan_pkt_capture_public_structs.h new file mode 100644 index 000000000000..4203462dc908 --- /dev/null +++ b/drivers/staging/qcacld-3.0/components/pkt_capture/dispatcher/inc/wlan_pkt_capture_public_structs.h @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +#ifndef _WLAN_PKT_CAPTURE_PUBLIC_STRUCTS_H_ +#define _WLAN_PKT_CAPTURE_PUBLIC_STRUCTS_H_ + +/** + * enum pkt_capture_mode - packet capture modes + * @PACKET_CAPTURE_MODE_DISABLE: packet capture mode disable + * @PACKET_CAPTURE_MODE_MGMT_ONLY: capture mgmt packets only + * @PACKET_CAPTURE_MODE_DATA_ONLY: capture data packets only + * @PACKET_CAPTURE_MODE_DATA_MGMT: capture both data and mgmt packets + */ +enum pkt_capture_mode { + PACKET_CAPTURE_MODE_DISABLE = 0, + PACKET_CAPTURE_MODE_MGMT_ONLY, + PACKET_CAPTURE_MODE_DATA_ONLY, + PACKET_CAPTURE_MODE_DATA_MGMT, +}; + +/** + * struct pkt_capture_cfg - packet capture cfg to store ini values + * @pkt_capture_mode: packet capture mode + */ +struct pkt_capture_cfg { + enum pkt_capture_mode pkt_capture_mode; +}; + +/** + * struct mgmt_offload_event_params - Management offload event params + * @tsf_l32: The lower 32 bits of the TSF + * @chan_freq: channel frequency in MHz + * @rate_kbps: Rate kbps + * @rssi: combined RSSI, i.e. the sum of the snr + noise floor (dBm units) + * @buf_len: length of the frame in bytes + * @tx_status: 0: xmit ok + * 1: excessive retries + * 2: blocked by tx filtering + * 4: fifo underrun + * 8: swabort + * @buf: management frame buffer + * @tx_retry_cnt: tx retry count + */ +struct mgmt_offload_event_params { + uint32_t tsf_l32; + uint32_t chan_freq; + uint32_t rate_kbps; + uint32_t rssi; + uint32_t buf_len; + uint32_t tx_status; + uint8_t *buf; + uint8_t tx_retry_cnt; +}; + +/** + * struct pkt_capture_callbacks - callbacks to non-converged driver + * @get_rmf_status: callback to get rmf status + */ +struct pkt_capture_callbacks { + int (*get_rmf_status)(uint8_t vdev_id); +}; +#endif /* _WLAN_PKT_CAPTURE_PUBLIC_STRUCTS_H_ */ diff --git a/drivers/staging/qcacld-3.0/components/pkt_capture/dispatcher/inc/wlan_pkt_capture_ucfg_api.h b/drivers/staging/qcacld-3.0/components/pkt_capture/dispatcher/inc/wlan_pkt_capture_ucfg_api.h new file mode 100644 index 000000000000..972f32a56ce4 --- /dev/null +++ b/drivers/staging/qcacld-3.0/components/pkt_capture/dispatcher/inc/wlan_pkt_capture_ucfg_api.h @@ -0,0 +1,423 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/** + * DOC: Declare public API related to the pkt_capture called by north bound + * HDD/OSIF/LIM + */ + +#ifndef _WLAN_PKT_CAPTURE_UCFG_API_H_ +#define _WLAN_PKT_CAPTURE_UCFG_API_H_ + +#include +#include +#include "wlan_pkt_capture_objmgr.h" +#include "wlan_pkt_capture_public_structs.h" +#include "wlan_pkt_capture_mon_thread.h" +#include "wmi_unified.h" +#include "wmi_unified_param.h" +#include +#include "wlan_pkt_capture_data_txrx.h" +#include + +#ifdef WLAN_FEATURE_PKT_CAPTURE +/** + * ucfg_pkt_capture_init() - Packet capture component initialization. + * + * This function gets called when packet capture initializing. + * + * Return: QDF_STATUS + */ +QDF_STATUS ucfg_pkt_capture_init(void); + +/** + * ucfg_pkt_capture_deinit() - Packet capture component de-init. + * + * This function gets called when packet capture de-init. + * + * Return: None + */ +void ucfg_pkt_capture_deinit(void); + +/** + * ucfg_pkt_capture_get_mode() - get packet capture mode + * @psoc: objmgr psoc handle + * + * Return: enum pkt_capture_mode + */ +enum pkt_capture_mode ucfg_pkt_capture_get_mode(struct wlan_objmgr_psoc *psoc); + +/** + * ucfg_pkt_capture_psoc_config(): API to update the psoc user configurations + * @psoc: objmgr psoc handle + * @cfg: packet capture psoc configurations + * + * Return: QDF_STATUS + */ +QDF_STATUS ucfg_pkt_capture_psoc_config(struct wlan_objmgr_psoc *psoc, + struct pkt_capture_cfg *cfg); + +/** + * ucfg_pkt_capture_suspend_mon_thread() - suspend packet capture mon thread + * vdev: pointer to vdev object manager + * + * Return: 0 on success, -EINVAL on failure + */ +int ucfg_pkt_capture_suspend_mon_thread(struct wlan_objmgr_vdev *vdev); + +/** + * ucfg_pkt_capture_resume_mon_thread() - resume packet capture mon thread + * vdev: pointer to vdev object manager + * + * Resume packet capture MON thread by completing RX thread resume event + * + * Return: None + */ +void ucfg_pkt_capture_resume_mon_thread(struct wlan_objmgr_vdev *vdev); + +/** + * ucfg_pkt_capture_register_callbacks - Register packet capture callbacks + * @vdev: pointer to wlan vdev object manager + * mon_cb: callback to call + * context: callback context + * + * Return: QDF_STATUS + */ +QDF_STATUS +ucfg_pkt_capture_register_callbacks(struct wlan_objmgr_vdev *vdev, + QDF_STATUS (*mon_cb)(void *, qdf_nbuf_t), + void *context); + +/** + * ucfg_pkt_capture_deregister_callbacks - De-register packet capture callbacks + * @vdev: pointer to wlan vdev object manager + * + * Return: QDF_STATUS + */ +QDF_STATUS +ucfg_pkt_capture_deregister_callbacks(struct wlan_objmgr_vdev *vdev); + +/** + * ucfg_pkt_capturee_set_pktcap_mode - Set packet capture mode + * @psoc: pointer to psoc object + * @mode: mode to be set + * + * Return: None + */ +void ucfg_pkt_capture_set_pktcap_mode(struct wlan_objmgr_psoc *psoc, + enum pkt_capture_mode val); + +/** + * ucfg_pkt_capture_get_pktcap_mode - Get packet capture mode + * + * Return: enum pkt_capture_mode + */ +enum pkt_capture_mode +ucfg_pkt_capture_get_pktcap_mode(void); + +/** + * ucfg_pkt_capture_process_mgmt_tx_data() - process management tx packets + * @pdev: pointer to pdev object + * @params: management offload event params + * @nbuf: netbuf + * @status: status + * + * Return: QDF_STATUS + */ +QDF_STATUS +ucfg_pkt_capture_process_mgmt_tx_data(struct wlan_objmgr_pdev *pdev, + struct mgmt_offload_event_params *params, + qdf_nbuf_t nbuf, + uint8_t status); + +/** + * ucfg_pkt_capture_mgmt_tx() - process mgmt tx completion + * for pkt capture mode + * @pdev: pointer to pdev object + * @nbuf: netbuf + * @chan_freq: channel freq + * @preamble_type: preamble_type + * + * Return: none + */ +void +ucfg_pkt_capture_mgmt_tx(struct wlan_objmgr_pdev *pdev, + qdf_nbuf_t nbuf, + uint16_t chan_freq, + uint8_t preamble_type); + +/** + * ucfg_pkt_capture_mgmt_tx_completion() - process mgmt tx completion + * for pkt capture mode + * @pdev: pointer to pdev object + * @desc_id: desc_id + * @status: status + * @params: management offload event params + * + * Return: none + */ +void +ucfg_pkt_capture_mgmt_tx_completion( + struct wlan_objmgr_pdev *pdev, + uint32_t desc_id, + uint32_t status, + struct mgmt_offload_event_params *params); + +/** + * ucfg_pkt_capture_enable_ops - Enable packet capture tx and rx ops handlers + * @wlan_objmgr_vdev: wlan vdev object manager + * + * Return: 0 on success, -EINVAL on failure + */ +int ucfg_pkt_capture_enable_ops(struct wlan_objmgr_vdev *vdev); + +/** + * ucfg_pkt_capture_rx_msdu_process() - process data rx pkts + * @bssid: bssid + * @head_msdu: pointer to head msdu + * @vdev_id: vdev_id + * @pdev: pdev handle + * + * Return: none + */ +void ucfg_pkt_capture_rx_msdu_process( + uint8_t *bssid, + qdf_nbuf_t head_msdu, + uint8_t vdev_id, htt_pdev_handle pdev); + +/** + * ucfg_pkt_capture_rx_offloaded_pkt() - check offloaded data pkt or not + * @rx_ind_msg: rx_ind_msg + * + * Return: 0 not an offload pkt + * 1 offload pkt + */ +bool ucfg_pkt_capture_rx_offloaded_pkt(qdf_nbuf_t rx_ind_msg); + +/** + * ucfg_pkt_capture_rx_drop_offload_pkt() - drop offload packets + * @head_msdu: pointer to head msdu + * + * Return: none + */ +void ucfg_pkt_capture_rx_drop_offload_pkt(qdf_nbuf_t head_msdu); + +/** + * ucfg_pkt_capture_offload_deliver_indication_handler() - Handle offload + * data pkts + * @msg: offload netbuf msg + * @vdev_id: vdev id + * @bssid: bssid + * @pdev: pdev handle + * + * Return: none + */ +void ucfg_pkt_capture_offload_deliver_indication_handler( + void *msg, uint8_t vdev_id, + uint8_t *bssid, htt_pdev_handle pdev); + +/** + * ucfg_pkt_capture_tx_get_txcomplete_data_hdr() - extract Tx data hdr from Tx + * completion for pkt capture mode + * @msg_word: Tx completion htt msg + * @num_msdus: number of msdus + * + * Return: tx data hdr information + */ +struct htt_tx_data_hdr_information *ucfg_pkt_capture_tx_get_txcomplete_data_hdr( + uint32_t *msg_word, + int num_msdus); + +/** + * ucfg_pkt_capture_tx_completion_process() - process data tx packets + * @vdev_id: vdev id for which packet is captured + * @mon_buf_list: netbuf list + * @type: data process type + * @tid: tid number + * @status: Tx status + * @pktformat: Frame format + * @bssid: bssid + * @pdev: pdev handle + * @tx_retry_cnt: tx retry count + * + * Return: none + */ +void ucfg_pkt_capture_tx_completion_process( + uint8_t vdev_id, + qdf_nbuf_t mon_buf_list, + enum pkt_capture_data_process_type type, + uint8_t tid, uint8_t status, bool pkt_format, + uint8_t *bssid, htt_pdev_handle pdev, + uint8_t tx_retry_cnt); + +/** + * ucfg_pkt_capture_record_channel() - Update Channel Information + * for packet capture mode + * + * Return: None + */ +void ucfg_pkt_capture_record_channel(void); + +/** + * ucfg_pkt_capture_register_callbacks - ucfg API to register WMA callbacks + * @psoc - pointer to psoc object + * @cb_obj - Pointer to packet capture callback structure + * + * Return: status of operation + */ +int +ucfg_pkt_capture_register_wma_callbacks(struct wlan_objmgr_psoc *psoc, + struct pkt_capture_callbacks *cb_obj); +#else +static inline +QDF_STATUS ucfg_pkt_capture_init(void) +{ + return QDF_STATUS_SUCCESS; +} + +static inline +void ucfg_pkt_capture_deinit(void) +{ +} + +static inline +enum pkt_capture_mode ucfg_pkt_capture_get_mode(struct wlan_objmgr_psoc *psoc) +{ + return PACKET_CAPTURE_MODE_DISABLE; +} + +static inline QDF_STATUS +ucfg_pkt_capture_psoc_config(struct wlan_objmgr_psoc *psoc, + struct pkt_capture_cfg *cfg) +{ + return QDF_STATUS_SUCCESS; +} + +static inline +void ucfg_pkt_capture_resume_mon_thread(struct wlan_objmgr_vdev *vdev) +{ +} + +static inline +int ucfg_pkt_capture_suspend_mon_thread(struct wlan_objmgr_vdev *vdev) +{ + return 0; +} + +static inline QDF_STATUS +ucfg_pkt_capture_register_callbacks(struct wlan_objmgr_vdev *vdev, + QDF_STATUS (*mon_cb)(void *, qdf_nbuf_t), + void *context) +{ + return QDF_STATUS_SUCCESS; +} + +static inline +QDF_STATUS ucfg_pkt_capture_deregister_callbacks(struct wlan_objmgr_vdev *vdev) +{ + return QDF_STATUS_SUCCESS; +} + +static inline +void ucfg_pkt_capture_set_pktcap_mode(struct wlan_objmgr_psoc *psoc, + uint8_t val) +{ +} + +static inline enum pkt_capture_mode +ucfg_pkt_capture_get_pktcap_mode(void) +{ + return PACKET_CAPTURE_MODE_DISABLE; +} + +static inline QDF_STATUS +ucfg_pkt_capture_process_mgmt_tx_data( + struct mgmt_offload_event_params *params, + qdf_nbuf_t nbuf, + uint8_t status) +{ + return 0; +} + +static inline void +ucfg_pkt_capture_mgmt_tx(struct wlan_objmgr_pdev *pdev, + qdf_nbuf_t nbuf, + uint16_t chan_freq, + uint8_t preamble_type) +{ +} + +static inline void +ucfg_pkt_capture_mgmt_tx_completion(struct wlan_objmgr_pdev *pdev, + uint32_t desc_id, + uint32_t status, + struct mgmt_offload_event_params *params) +{ +} + +static inline void +ucfg_pkt_capture_offload_deliver_indication_handler( + void *msg, uint8_t vdev_id, + uint8_t *bssid, htt_pdev_handle pdev) +{ +} + +static inline +struct htt_tx_data_hdr_information *ucfg_pkt_capture_tx_get_txcomplete_data_hdr( + uint32_t *msg_word, + int num_msdus) +{ + return NULL; +} + +static inline void +ucfg_pkt_capture_rx_msdu_process( + uint8_t *bssid, + qdf_nbuf_t head_msdu, + uint8_t vdev_id, htt_pdev_handle pdev) +{ +} + +static inline bool +ucfg_pkt_capture_rx_offloaded_pkt(qdf_nbuf_t rx_ind_msg) +{ + return false; +} + +static inline void +ucfg_pkt_capture_rx_drop_offload_pkt(qdf_nbuf_t head_msdu) +{ +} + +static inline void +ucfg_pkt_capture_tx_completion_process( + uint8_t vdev_id, + qdf_nbuf_t mon_buf_list, + enum pkt_capture_data_process_type type, + uint8_t tid, uint8_t status, bool pkt_format, + uint8_t *bssid, htt_pdev_handle pdev, + uint8_t tx_retry_cnt) +{ +} + +static inline void +ucfg_pkt_capture_record_channel(void) +{ +} +#endif /* WLAN_FEATURE_PKT_CAPTURE */ +#endif /* _WLAN_PKT_CAPTURE_UCFG_API_H_ */ diff --git a/drivers/staging/qcacld-3.0/components/pkt_capture/dispatcher/src/wlan_pkt_capture_ucfg_api.c b/drivers/staging/qcacld-3.0/components/pkt_capture/dispatcher/src/wlan_pkt_capture_ucfg_api.c new file mode 100644 index 000000000000..0841f8796c59 --- /dev/null +++ b/drivers/staging/qcacld-3.0/components/pkt_capture/dispatcher/src/wlan_pkt_capture_ucfg_api.c @@ -0,0 +1,362 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/** + * DOC: Public API implementation of pkt_capture called by north bound HDD/OSIF. + */ + +#include "wlan_pkt_capture_objmgr.h" +#include "wlan_pkt_capture_main.h" +#include "wlan_pkt_capture_ucfg_api.h" +#include "wlan_pkt_capture_mon_thread.h" +#include "wlan_pkt_capture_mgmt_txrx.h" +#include "target_if_pkt_capture.h" +#include "wlan_pkt_capture_data_txrx.h" + +enum pkt_capture_mode ucfg_pkt_capture_get_mode(struct wlan_objmgr_psoc *psoc) +{ + return pkt_capture_get_mode(psoc); +} + +/** + * ucfg_pkt_capture_register_callbacks - Register packet capture callbacks + * @vdev: pointer to wlan vdev object manager + * mon_cb: callback to call + * context: callback context + * + * Return: 0 in case of success, invalid in case of failure. + */ +QDF_STATUS +ucfg_pkt_capture_register_callbacks(struct wlan_objmgr_vdev *vdev, + QDF_STATUS (*mon_cb)(void *, qdf_nbuf_t), + void *context) +{ + return pkt_capture_register_callbacks(vdev, mon_cb, context); +} + +/** + * ucfg_pkt_capture_deregister_callbacks - De-register packet capture callbacks + * @vdev: pointer to wlan vdev object manager + * + * Return: 0 in case of success, invalid in case of failure. + */ +QDF_STATUS ucfg_pkt_capture_deregister_callbacks(struct wlan_objmgr_vdev *vdev) +{ + return pkt_capture_deregister_callbacks(vdev); +} + +/** + * ucfg_pkt_capture_set_pktcap_mode - Set packet capture mode + * @psoc: pointer to psoc object + * @mode: mode to be set + * + * Return: None + */ +void ucfg_pkt_capture_set_pktcap_mode(struct wlan_objmgr_psoc *psoc, + enum pkt_capture_mode mode) +{ + pkt_capture_set_pktcap_mode(psoc, mode); +} + +/** + * ucfg_pkt_capture_get_pktcap_mode - Get packet capture mode + * + * Return: enum pkt_capture_mode + */ +enum pkt_capture_mode +ucfg_pkt_capture_get_pktcap_mode(void) +{ + return pkt_capture_get_pktcap_mode(); +} + +/** + * ucfg_pkt_capture_init() - Packet capture component initialization. + * + * This function gets called when packet capture initializing. + * + * Return: QDF_STATUS_SUCCESS - in case of success. + */ +QDF_STATUS ucfg_pkt_capture_init(void) +{ + QDF_STATUS status; + + status = wlan_objmgr_register_psoc_create_handler( + WLAN_UMAC_COMP_PKT_CAPTURE, + pkt_capture_psoc_create_notification, + NULL); + if (QDF_IS_STATUS_ERROR(status)) { + pkt_capture_err("Failed to register psoc create handler"); + return status; + } + + status = wlan_objmgr_register_psoc_destroy_handler( + WLAN_UMAC_COMP_PKT_CAPTURE, + pkt_capture_psoc_destroy_notification, + NULL); + if (QDF_IS_STATUS_ERROR(status)) { + pkt_capture_err("Failed to register psoc delete handler"); + goto fail_destroy_psoc; + } + + status = wlan_objmgr_register_vdev_create_handler( + WLAN_UMAC_COMP_PKT_CAPTURE, + pkt_capture_vdev_create_notification, NULL); + if (QDF_IS_STATUS_ERROR(status)) { + pkt_capture_err("Failed to register vdev create handler"); + goto fail_create_vdev; + } + + status = wlan_objmgr_register_vdev_destroy_handler( + WLAN_UMAC_COMP_PKT_CAPTURE, + pkt_capture_vdev_destroy_notification, NULL); + if (QDF_IS_STATUS_ERROR(status)) { + pkt_capture_err("Failed to register vdev destroy handler"); + goto fail_destroy_vdev; + } + return status; + +fail_destroy_vdev: + wlan_objmgr_unregister_vdev_create_handler(WLAN_UMAC_COMP_PKT_CAPTURE, + pkt_capture_vdev_create_notification, NULL); + +fail_create_vdev: + wlan_objmgr_unregister_psoc_destroy_handler(WLAN_UMAC_COMP_PKT_CAPTURE, + pkt_capture_psoc_destroy_notification, NULL); + +fail_destroy_psoc: + wlan_objmgr_unregister_psoc_create_handler(WLAN_UMAC_COMP_PKT_CAPTURE, + pkt_capture_psoc_create_notification, NULL); + + return status; +} + +void ucfg_pkt_capture_deinit(void) +{ + QDF_STATUS status; + + status = wlan_objmgr_unregister_vdev_destroy_handler( + WLAN_UMAC_COMP_PKT_CAPTURE, + pkt_capture_vdev_destroy_notification, + NULL); + if (QDF_IS_STATUS_ERROR(status)) + pkt_capture_err("Failed to unregister vdev destroy handler"); + + status = wlan_objmgr_unregister_vdev_create_handler( + WLAN_UMAC_COMP_PKT_CAPTURE, + pkt_capture_vdev_create_notification, NULL); + if (QDF_IS_STATUS_ERROR(status)) + pkt_capture_err("Failed to unregister vdev create handler"); + + status = wlan_objmgr_unregister_psoc_destroy_handler( + WLAN_UMAC_COMP_PKT_CAPTURE, + pkt_capture_psoc_destroy_notification, + NULL); + if (QDF_IS_STATUS_ERROR(status)) + pkt_capture_err("Failed to unregister psoc destroy handler"); + + status = wlan_objmgr_unregister_psoc_create_handler( + WLAN_UMAC_COMP_PKT_CAPTURE, + pkt_capture_psoc_create_notification, + NULL); + if (QDF_IS_STATUS_ERROR(status)) + pkt_capture_err("Failed to unregister psoc create handler"); +} + +QDF_STATUS ucfg_pkt_capture_psoc_config(struct wlan_objmgr_psoc *psoc, + struct pkt_capture_cfg *psoc_cfg) +{ + return pkt_capture_psoc_config(psoc, psoc_cfg); +} + +int ucfg_pkt_capture_suspend_mon_thread(struct wlan_objmgr_vdev *vdev) +{ + return pkt_capture_suspend_mon_thread(vdev); +} + +void ucfg_pkt_capture_resume_mon_thread(struct wlan_objmgr_vdev *vdev) +{ + pkt_capture_resume_mon_thread(vdev); +} + +/** + * ucfg_process_pktcapture_mgmt_tx_data() - process management tx packets + * @pdev: pointer to pdev object + * @params: management offload event params + * @nbuf: netbuf + * @status: status + * + * Return: QDF_STATUS + */ +QDF_STATUS +ucfg_pkt_capture_process_mgmt_tx_data(struct wlan_objmgr_pdev *pdev, + struct mgmt_offload_event_params *params, + qdf_nbuf_t nbuf, + uint8_t status) +{ + return pkt_capture_process_mgmt_tx_data( + pdev, params, nbuf, + pkt_capture_mgmt_status_map(status)); +} + +void +ucfg_pkt_capture_mgmt_tx(struct wlan_objmgr_pdev *pdev, + qdf_nbuf_t nbuf, + uint16_t chan_freq, + uint8_t preamble_type) +{ + pkt_capture_mgmt_tx(pdev, nbuf, chan_freq, preamble_type); +} + +/** + * ucfg_process_pktcapture_mgmt_tx_completion(): process mgmt tx completion + * for pkt capture mode + * @pdev: pointer to pdev object + * @desc_id: desc_id + * @status: status + * @params: management offload event params + * + * Return: none + */ +void +ucfg_pkt_capture_mgmt_tx_completion(struct wlan_objmgr_pdev *pdev, + uint32_t desc_id, + uint32_t status, + struct mgmt_offload_event_params *params) +{ + pkt_capture_mgmt_tx_completion(pdev, desc_id, status, params); +} + +int ucfg_pkt_capture_enable_ops(struct wlan_objmgr_vdev *vdev) +{ + struct pkt_capture_vdev_priv *vdev_priv; + struct wlan_pkt_capture_rx_ops *rx_ops; + struct wlan_pkt_capture_tx_ops *tx_ops; + struct wlan_objmgr_psoc *psoc; + enum pkt_capture_mode mode; + QDF_STATUS status; + int ret; + + if (!vdev) + return -EINVAL; + + psoc = wlan_vdev_get_psoc(vdev); + if (!psoc) + return -EINVAL; + + vdev_priv = pkt_capture_vdev_get_priv(vdev); + if (!vdev_priv) { + pkt_capture_err("vdev_priv got NULL"); + return -EINVAL; + } + + if (vdev_priv->is_ops_registered) + return 0; + + rx_ops = &vdev_priv->rx_ops; + tx_ops = &vdev_priv->tx_ops; + + status = rx_ops->pkt_capture_register_mgmt_data_offload_event(psoc); + if (QDF_IS_STATUS_ERROR(status)) { + pkt_capture_err("Unable to register mgmt offload handler"); + return -EINVAL; + } + + mode = pkt_capture_get_mode(psoc); + ret = tx_ops->pkt_capture_send_mode(psoc, + vdev->vdev_objmgr.vdev_id, + mode); + if (ret) { + pkt_capture_err("Unable to send packet capture mode to fw"); + return ret; + } + vdev_priv->is_ops_registered = true; + + return 0; +} + +void ucfg_pkt_capture_rx_msdu_process( + uint8_t *bssid, + qdf_nbuf_t head_msdu, + uint8_t vdev_id, htt_pdev_handle pdev) +{ + pkt_capture_msdu_process_pkts(bssid, head_msdu, + vdev_id, pdev); +} + +bool ucfg_pkt_capture_rx_offloaded_pkt(qdf_nbuf_t rx_ind_msg) +{ + return pkt_capture_rx_in_order_offloaded_pkt(rx_ind_msg); +} + +void ucfg_pkt_capture_rx_drop_offload_pkt(qdf_nbuf_t head_msdu) +{ + pkt_capture_rx_in_order_drop_offload_pkt(head_msdu); +} + +void +ucfg_pkt_capture_offload_deliver_indication_handler( + void *msg, uint8_t vdev_id, + uint8_t *bssid, htt_pdev_handle pdev) +{ + pkt_capture_offload_deliver_indication_handler(msg, vdev_id, + bssid, pdev); +} + +struct htt_tx_data_hdr_information *ucfg_pkt_capture_tx_get_txcomplete_data_hdr( + uint32_t *msg_word, + int num_msdus) +{ + return pkt_capture_tx_get_txcomplete_data_hdr(msg_word, num_msdus); +} + +void +ucfg_pkt_capture_tx_completion_process( + uint8_t vdev_id, + qdf_nbuf_t mon_buf_list, + enum pkt_capture_data_process_type type, + uint8_t tid, uint8_t status, bool pkt_format, + uint8_t *bssid, htt_pdev_handle pdev, + uint8_t tx_retry_cnt) +{ + pkt_capture_datapkt_process( + vdev_id, + mon_buf_list, TXRX_PROCESS_TYPE_DATA_TX_COMPL, + tid, status, pkt_format, bssid, pdev, + tx_retry_cnt); +} + +void ucfg_pkt_capture_record_channel(void) +{ + pkt_capture_record_channel(); +} + +int +ucfg_pkt_capture_register_wma_callbacks(struct wlan_objmgr_psoc *psoc, + struct pkt_capture_callbacks *cb_obj) +{ + struct pkt_psoc_priv *psoc_priv = pkt_capture_psoc_get_priv(psoc); + + if (!psoc_priv) { + pkt_capture_err("psoc priv is NULL"); + return -EINVAL; + } + + psoc_priv->cb_obj.get_rmf_status = cb_obj->get_rmf_status; + + return 0; +} diff --git a/drivers/staging/qcacld-3.0/components/pmo/core/inc/wlan_pmo_arp.h b/drivers/staging/qcacld-3.0/components/pmo/core/inc/wlan_pmo_arp.h index d577cd2b8d3e..f5035b4fcc92 100644 --- a/drivers/staging/qcacld-3.0/components/pmo/core/inc/wlan_pmo_arp.h +++ b/drivers/staging/qcacld-3.0/components/pmo/core/inc/wlan_pmo_arp.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -36,6 +36,18 @@ */ QDF_STATUS pmo_core_cache_arp_offload_req(struct pmo_arp_req *arp_req); +/** + * pmo_core_arp_check_offload(): API to check if arp offload cache/send is req + * @psoc: objmgr psoc handle + * @trigger: trigger reason + * @vdev_id: vdev id + * + * Return QDF_STATUS_SUCCESS -in case of success else return error + */ +QDF_STATUS pmo_core_arp_check_offload(struct wlan_objmgr_psoc *psoc, + enum pmo_offload_trigger trigger, + uint8_t vdev_id); + /** * pmo_core_flush_arp_offload_req() - API to flush arp req from pmo vdev ctx * @vdev: objmgr vdev diff --git a/drivers/staging/qcacld-3.0/components/pmo/core/inc/wlan_pmo_ns.h b/drivers/staging/qcacld-3.0/components/pmo/core/inc/wlan_pmo_ns.h index 26662dd74969..c53d4c67bf20 100644 --- a/drivers/staging/qcacld-3.0/components/pmo/core/inc/wlan_pmo_ns.h +++ b/drivers/staging/qcacld-3.0/components/pmo/core/inc/wlan_pmo_ns.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -37,6 +37,18 @@ */ QDF_STATUS pmo_core_cache_ns_offload_req(struct pmo_ns_req *ns_req); +/** + * pmo_core_ns_check_offload() - API to check if offload cache/send is required + * @psoc: objmgr psoc handle + * @trigger: trigger reason enable ns offload + * @vdev_id: vdev id + * + * Return:QDF_STATUS_SUCCESS in case of success else return error + */ +QDF_STATUS pmo_core_ns_check_offload(struct wlan_objmgr_psoc *psoc, + enum pmo_offload_trigger trigger, + uint8_t vdev_id); + /** * pmo_core_flush_ns_offload_req() - API to flush ns req from pmo vdev priv ctx * @vdev: vdev objmgr handle diff --git a/drivers/staging/qcacld-3.0/components/pmo/core/src/wlan_pmo_arp.c b/drivers/staging/qcacld-3.0/components/pmo/core/src/wlan_pmo_arp.c index b143e952a4ab..186a46fe678c 100644 --- a/drivers/staging/qcacld-3.0/components/pmo/core/src/wlan_pmo_arp.c +++ b/drivers/staging/qcacld-3.0/components/pmo/core/src/wlan_pmo_arp.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -34,8 +34,6 @@ static QDF_STATUS pmo_core_cache_arp_in_vdev_priv( int index; struct qdf_mac_addr peer_bssid; - pmo_enter(); - vdev_ctx = pmo_vdev_get_priv(vdev); request = qdf_mem_malloc(sizeof(*request)); @@ -76,7 +74,6 @@ static QDF_STATUS pmo_core_cache_arp_in_vdev_priv( qdf_mem_free(request); exit_with_status: - pmo_exit(); return status; } @@ -111,8 +108,6 @@ pmo_core_do_enable_arp_offload(struct wlan_objmgr_vdev *vdev, struct pmo_psoc_priv_obj *psoc_ctx; struct pmo_vdev_priv_obj *vdev_ctx; - pmo_enter(); - vdev_ctx = pmo_vdev_get_priv(vdev); psoc_ctx = vdev_ctx->pmo_psoc_ctx; @@ -134,12 +129,6 @@ pmo_core_do_enable_arp_offload(struct wlan_objmgr_vdev *vdev, status = pmo_tgt_enable_arp_offload_req(vdev, vdev_id); break; case pmo_apps_suspend: - if (psoc_ctx->psoc_cfg.active_mode_offload) { - pmo_debug("active offload is enabled, skip in mode %d", - trigger); - status = QDF_STATUS_SUCCESS; - goto out; - } /* enable arp when active offload is false (apps suspend) */ status = pmo_tgt_enable_arp_offload_req(vdev, vdev_id); break; @@ -149,7 +138,6 @@ pmo_core_do_enable_arp_offload(struct wlan_objmgr_vdev *vdev, break; } out: - pmo_exit(); return status; } @@ -174,12 +162,6 @@ static QDF_STATUS pmo_core_do_disable_arp_offload(struct wlan_objmgr_vdev *vdev, switch (trigger) { case pmo_apps_resume: - if (psoc_ctx->psoc_cfg.active_mode_offload) { - pmo_debug("active offload is enabled, skip in mode: %d", - trigger); - status = QDF_STATUS_SUCCESS; - goto out; - } /* disable arp on apps resume when active offload is disable */ status = pmo_tgt_disable_arp_offload_req(vdev, vdev_id); break; @@ -222,12 +204,62 @@ static QDF_STATUS pmo_core_arp_offload_sanity( return QDF_STATUS_SUCCESS; } +QDF_STATUS pmo_core_arp_check_offload(struct wlan_objmgr_psoc *psoc, + enum pmo_offload_trigger trigger, + uint8_t vdev_id) +{ + QDF_STATUS status = QDF_STATUS_SUCCESS; + struct pmo_psoc_priv_obj *psoc_ctx; + struct pmo_vdev_priv_obj *vdev_ctx; + struct wlan_objmgr_vdev *vdev; + bool active_offload_cond, is_applied_cond; + enum QDF_OPMODE opmode; + + vdev = pmo_psoc_get_vdev(psoc, vdev_id); + if (!vdev) { + pmo_err("vdev is NULL"); + status = QDF_STATUS_E_INVAL; + goto out; + } + + status = pmo_vdev_get_ref(vdev); + if (QDF_IS_STATUS_ERROR(status)) + goto out; + + opmode = pmo_get_vdev_opmode(vdev); + if (opmode == QDF_NDI_MODE) { + pmo_debug("ARP offload is not supported in NaN mode"); + pmo_vdev_put_ref(vdev); + return QDF_STATUS_E_INVAL; + } + + vdev_ctx = pmo_vdev_get_priv(vdev); + psoc_ctx = vdev_ctx->pmo_psoc_ctx; + + if (trigger == pmo_apps_suspend || trigger == pmo_apps_resume) { + active_offload_cond = psoc_ctx->psoc_cfg.active_mode_offload; + + qdf_spin_lock_bh(&vdev_ctx->pmo_vdev_lock); + is_applied_cond = vdev_ctx->vdev_arp_req.enable && + vdev_ctx->vdev_arp_req.is_offload_applied; + qdf_spin_unlock_bh(&vdev_ctx->pmo_vdev_lock); + + if (active_offload_cond && is_applied_cond) { + pmo_debug("active offload is enabled and offload already sent"); + pmo_vdev_put_ref(vdev); + return QDF_STATUS_E_INVAL; + } + } + pmo_vdev_put_ref(vdev); +out: + return status; +} + QDF_STATUS pmo_core_cache_arp_offload_req(struct pmo_arp_req *arp_req) { QDF_STATUS status; struct wlan_objmgr_vdev *vdev; - pmo_enter(); if (!arp_req) { pmo_err("arp_req is NULL"); status = QDF_STATUS_E_INVAL; @@ -262,7 +294,6 @@ QDF_STATUS pmo_core_cache_arp_offload_req(struct pmo_arp_req *arp_req) dec_ref: pmo_vdev_put_ref(vdev); out: - pmo_exit(); return status; } @@ -305,7 +336,6 @@ QDF_STATUS pmo_core_enable_arp_offload_in_fwr(struct wlan_objmgr_vdev *vdev, QDF_STATUS status; uint8_t vdev_id; - pmo_enter(); if (!vdev) { pmo_err("vdev is NULL"); status = QDF_STATUS_E_NULL_VALUE; @@ -328,8 +358,7 @@ QDF_STATUS pmo_core_enable_arp_offload_in_fwr(struct wlan_objmgr_vdev *vdev, put_ref: pmo_vdev_put_ref(vdev); -out: - pmo_exit(); +out:; return status; } @@ -340,7 +369,6 @@ QDF_STATUS pmo_core_disable_arp_offload_in_fwr(struct wlan_objmgr_vdev *vdev, QDF_STATUS status; uint8_t vdev_id; - pmo_enter(); if (!vdev) { pmo_err("vdev is NULL"); status = QDF_STATUS_E_NULL_VALUE; @@ -363,7 +391,6 @@ QDF_STATUS pmo_core_disable_arp_offload_in_fwr(struct wlan_objmgr_vdev *vdev, def_ref: pmo_vdev_put_ref(vdev); out: - pmo_exit(); return status; } diff --git a/drivers/staging/qcacld-3.0/components/pmo/core/src/wlan_pmo_mc_addr_filtering.c b/drivers/staging/qcacld-3.0/components/pmo/core/src/wlan_pmo_mc_addr_filtering.c index facdec0ff9f9..16a28e192770 100644 --- a/drivers/staging/qcacld-3.0/components/pmo/core/src/wlan_pmo_mc_addr_filtering.c +++ b/drivers/staging/qcacld-3.0/components/pmo/core/src/wlan_pmo_mc_addr_filtering.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -46,7 +46,6 @@ static void pmo_core_fill_mc_list(struct pmo_vdev_priv_obj **vdev_ctx, qdf_spin_unlock_bh(&temp_ctx->pmo_vdev_lock); for (i = 0; i < ip->count; i++) { - pmo_debug("%pM", ip->mc_addr[i].bytes); /* * Skip following addresses: * 1)IPv6 router solicitation address @@ -71,8 +70,7 @@ static void pmo_core_fill_mc_list(struct pmo_vdev_priv_obj **vdev_ctx, qdf_mem_copy(&op_list->mc_addr[j].bytes, ip->mc_addr[i].bytes, QDF_MAC_ADDR_SIZE); qdf_spin_unlock_bh(&temp_ctx->pmo_vdev_lock); - pmo_debug("Index = %d, mlist[%pM]", - j, op_list->mc_addr[i].bytes); + pmo_debug("Index = %d, mac[%pM]", j, op_list->mc_addr[i].bytes); j++; } } @@ -108,8 +106,6 @@ QDF_STATUS pmo_core_enhanced_mc_filter_enable(struct wlan_objmgr_vdev *vdev) { QDF_STATUS status; - pmo_enter(); - status = pmo_vdev_get_ref(vdev); if (QDF_IS_STATUS_ERROR(status)) goto exit_with_status; @@ -119,7 +115,6 @@ QDF_STATUS pmo_core_enhanced_mc_filter_enable(struct wlan_objmgr_vdev *vdev) pmo_vdev_put_ref(vdev); exit_with_status: - pmo_exit(); return status; } @@ -231,7 +226,7 @@ static QDF_STATUS pmo_core_do_disable_mc_addr_list( /* validate filter is applied before clearing in fwr */ if (!vdev_ctx->vdev_mc_list_req.is_filter_applied) { qdf_spin_unlock_bh(&vdev_ctx->pmo_vdev_lock); - pmo_err("mc filter is not applied in fwr"); + pmo_debug("mc filter is not applied in fwr"); status = QDF_STATUS_E_INVAL; goto out; } @@ -241,7 +236,7 @@ static QDF_STATUS pmo_core_do_disable_mc_addr_list( status = pmo_core_clear_mc_filter_req(vdev, op_mc_list_req); if (status != QDF_STATUS_SUCCESS) { - pmo_err("cannot apply mc filter request"); + pmo_debug("cannot apply mc filter request"); status = QDF_STATUS_E_INVAL; goto out; } @@ -400,7 +395,6 @@ QDF_STATUS pmo_core_flush_mc_addr_list(struct wlan_objmgr_psoc *psoc, struct wlan_objmgr_vdev *vdev; QDF_STATUS status = QDF_STATUS_SUCCESS; - pmo_enter(); if (!psoc) { pmo_err("psoc is NULL"); status = QDF_STATUS_E_NULL_VALUE; @@ -433,7 +427,6 @@ QDF_STATUS pmo_core_flush_mc_addr_list(struct wlan_objmgr_psoc *psoc, dec_ref: pmo_vdev_put_ref(vdev); out: - pmo_exit(); return status; } diff --git a/drivers/staging/qcacld-3.0/components/pmo/core/src/wlan_pmo_ns.c b/drivers/staging/qcacld-3.0/components/pmo/core/src/wlan_pmo_ns.c index 1ddb187d1a62..4b29a652e810 100644 --- a/drivers/staging/qcacld-3.0/components/pmo/core/src/wlan_pmo_ns.c +++ b/drivers/staging/qcacld-3.0/components/pmo/core/src/wlan_pmo_ns.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -169,11 +169,6 @@ static QDF_STATUS pmo_core_do_enable_ns_offload(struct wlan_objmgr_vdev *vdev, status = pmo_tgt_enable_ns_offload_req(vdev, vdev_id); break; case pmo_apps_suspend: - if (psoc_ctx->psoc_cfg.active_mode_offload) { - pmo_debug("active offload is enabled, skip in mode: %d", - trigger); - goto out; - } /* enable arp when active offload is false (apps suspend) */ status = pmo_tgt_enable_ns_offload_req(vdev, vdev_id); break; @@ -210,12 +205,6 @@ static QDF_STATUS pmo_core_do_disable_ns_offload(struct wlan_objmgr_vdev *vdev, status = pmo_tgt_disable_ns_offload_req(vdev, vdev_id); break; case pmo_apps_resume: - if (psoc_ctx->psoc_cfg.active_mode_offload) { - pmo_debug("active offload is enabled, skip in mode: %d", - trigger); - goto out; - } - /* config arp/ns when active offload is disable */ status = pmo_tgt_disable_ns_offload_req(vdev, vdev_id); break; default: @@ -258,8 +247,60 @@ static QDF_STATUS pmo_core_ns_offload_sanity(struct wlan_objmgr_vdev *vdev) return QDF_STATUS_SUCCESS; } -QDF_STATUS pmo_core_cache_ns_offload_req( - struct pmo_ns_req *ns_req) +QDF_STATUS pmo_core_ns_check_offload(struct wlan_objmgr_psoc *psoc, + enum pmo_offload_trigger trigger, + uint8_t vdev_id) +{ + QDF_STATUS status = QDF_STATUS_SUCCESS; + struct pmo_psoc_priv_obj *psoc_ctx; + struct pmo_vdev_priv_obj *vdev_ctx; + struct wlan_objmgr_vdev *vdev; + bool active_offload_cond, is_applied_cond; + enum QDF_OPMODE opmode; + + pmo_enter(); + + vdev = pmo_psoc_get_vdev(psoc, vdev_id); + if (!vdev) { + pmo_err("vdev is NULL"); + status = QDF_STATUS_E_INVAL; + goto out; + } + + status = pmo_vdev_get_ref(vdev); + if (QDF_IS_STATUS_ERROR(status)) + goto out; + + opmode = pmo_get_vdev_opmode(vdev); + if (opmode == QDF_NDI_MODE) { + pmo_debug("NS offload not supported in NaN mode"); + pmo_vdev_put_ref(vdev); + return QDF_STATUS_E_INVAL; + } + + vdev_ctx = pmo_vdev_get_priv(vdev); + psoc_ctx = vdev_ctx->pmo_psoc_ctx; + + if (trigger == pmo_apps_suspend || trigger == pmo_apps_resume) { + active_offload_cond = psoc_ctx->psoc_cfg.active_mode_offload; + + qdf_spin_lock_bh(&vdev_ctx->pmo_vdev_lock); + is_applied_cond = vdev_ctx->vdev_ns_req.enable && + vdev_ctx->vdev_ns_req.is_offload_applied; + qdf_spin_unlock_bh(&vdev_ctx->pmo_vdev_lock); + + if (active_offload_cond && is_applied_cond) { + pmo_debug("active offload is enabled and offload already sent"); + pmo_vdev_put_ref(vdev); + return QDF_STATUS_E_INVAL; + } + } + pmo_vdev_put_ref(vdev); +out: + return status; +} + +QDF_STATUS pmo_core_cache_ns_offload_req(struct pmo_ns_req *ns_req) { QDF_STATUS status; struct wlan_objmgr_vdev *vdev; diff --git a/drivers/staging/qcacld-3.0/components/pmo/core/src/wlan_pmo_static_config.c b/drivers/staging/qcacld-3.0/components/pmo/core/src/wlan_pmo_static_config.c index 5187e211a706..29a59a6dca10 100644 --- a/drivers/staging/qcacld-3.0/components/pmo/core/src/wlan_pmo_static_config.c +++ b/drivers/staging/qcacld-3.0/components/pmo/core/src/wlan_pmo_static_config.c @@ -332,7 +332,8 @@ void pmo_register_wow_default_patterns(struct wlan_objmgr_vdev *vdev) } vdev_opmode = pmo_get_vdev_opmode(vdev); - if (vdev_opmode == QDF_MAX_NO_OF_MODE) { + if (vdev_opmode == QDF_MAX_NO_OF_MODE || + vdev_opmode == QDF_NAN_DISC_MODE) { pmo_err("Invalid vdev opmode %d", vdev_id); return; } diff --git a/drivers/staging/qcacld-3.0/components/pmo/core/src/wlan_pmo_suspend_resume.c b/drivers/staging/qcacld-3.0/components/pmo/core/src/wlan_pmo_suspend_resume.c index 7f7e12672379..bf0d32ed5d37 100644 --- a/drivers/staging/qcacld-3.0/components/pmo/core/src/wlan_pmo_suspend_resume.c +++ b/drivers/staging/qcacld-3.0/components/pmo/core/src/wlan_pmo_suspend_resume.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -479,18 +479,10 @@ QDF_STATUS pmo_core_psoc_user_space_suspend_req(struct wlan_objmgr_psoc *psoc, goto out; } - /* Suspend all components before sending target suspend command */ - status = pmo_suspend_all_components(psoc, type); - if (status != QDF_STATUS_SUCCESS) { - pmo_err("Failed to suspend all component"); - goto dec_psoc_ref; - } - status = pmo_core_psoc_configure_suspend(psoc); if (status != QDF_STATUS_SUCCESS) pmo_err("Failed to configure suspend"); -dec_psoc_ref: pmo_psoc_put_ref(psoc); out: pmo_exit(); @@ -657,18 +649,10 @@ QDF_STATUS pmo_core_psoc_user_space_resume_req(struct wlan_objmgr_psoc *psoc, goto out; } - /* Resume all components */ - status = pmo_resume_all_components(psoc, type); - if (status != QDF_STATUS_SUCCESS) { - pmo_err("Failed to resume all the components"); - goto dec_psoc_ref; - } - status = pmo_core_psoc_configure_resume(psoc); if (status != QDF_STATUS_SUCCESS) pmo_err("Failed to configure resume"); -dec_psoc_ref: pmo_psoc_put_ref(psoc); out: pmo_exit(); diff --git a/drivers/staging/qcacld-3.0/components/pmo/core/src/wlan_pmo_wow.c b/drivers/staging/qcacld-3.0/components/pmo/core/src/wlan_pmo_wow.c index d3c5d362ac68..4e55025a05c9 100644 --- a/drivers/staging/qcacld-3.0/components/pmo/core/src/wlan_pmo_wow.c +++ b/drivers/staging/qcacld-3.0/components/pmo/core/src/wlan_pmo_wow.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -49,7 +49,6 @@ QDF_STATUS pmo_core_del_wow_pattern(struct wlan_objmgr_vdev *vdev) uint8_t pattern_count; struct pmo_vdev_priv_obj *vdev_ctx; - pmo_enter(); status = pmo_vdev_get_ref(vdev); if (QDF_IS_STATUS_ERROR(status)) goto out; @@ -67,7 +66,6 @@ QDF_STATUS pmo_core_del_wow_pattern(struct wlan_objmgr_vdev *vdev) pmo_vdev_put_ref(vdev); out: - pmo_exit(); return status; } @@ -420,6 +418,16 @@ void pmo_set_sta_wow_bitmask(uint32_t *bitmask, uint32_t wow_bitmap_size) pmo_set_wow_event_bitmap(WOW_11D_SCAN_EVENT, wow_bitmap_size, bitmask); + /* + * WPA3 roaming offloads SAE authentication to wpa_supplicant + * Firmware will send WMI_ROAM_PREAUTH_STATUS_CMDID + */ + pmo_set_wow_event_bitmap(WOW_ROAM_PREAUTH_START_EVENT, + wow_bitmap_size, + bitmask); + pmo_set_wow_event_bitmap(WOW_ROAM_PMKID_REQUEST_EVENT, + wow_bitmap_size, + bitmask); } void pmo_set_sap_wow_bitmask(uint32_t *bitmask, uint32_t wow_bitmap_size) diff --git a/drivers/staging/qcacld-3.0/components/pmo/dispatcher/inc/wlan_pmo_gtk_public_struct.h b/drivers/staging/qcacld-3.0/components/pmo/dispatcher/inc/wlan_pmo_gtk_public_struct.h index 9112d466640e..41482d9779c3 100644 --- a/drivers/staging/qcacld-3.0/components/pmo/dispatcher/inc/wlan_pmo_gtk_public_struct.h +++ b/drivers/staging/qcacld-3.0/components/pmo/dispatcher/inc/wlan_pmo_gtk_public_struct.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -30,9 +30,8 @@ #define PMO_GTK_OFFLOAD_ENABLE 0 #define PMO_GTK_OFFLOAD_DISABLE 1 -#define PMO_KEK_LEN_LEGACY 16 #define PMO_KEK_LEN 64 -#define PMO_KCK_LEN 16 +#define PMO_KCK_LEN 32 #define PMO_REPLAY_COUNTER_LEN 8 #define PMO_MAC_MAX_KEY_LENGTH 32 #define PMO_IGTK_PN_SIZE 6 @@ -41,6 +40,7 @@ * struct pmo_gtk_req - pmo gtk request * @flags: optional flags * @kck: Key confirmation key + * @kck_len: Key confirmation key length * @kek: key encryption key * @kek_len: KEK Length * @replay_counter: replay_counter @@ -50,6 +50,7 @@ struct pmo_gtk_req { uint32_t flags; uint8_t kck[PMO_KCK_LEN]; + uint8_t kck_len; uint8_t kek[PMO_KEK_LEN]; uint32_t kek_len; uint64_t replay_counter; diff --git a/drivers/staging/qcacld-3.0/components/pmo/dispatcher/inc/wlan_pmo_obj_mgmt_public_struct.h b/drivers/staging/qcacld-3.0/components/pmo/dispatcher/inc/wlan_pmo_obj_mgmt_public_struct.h index 6cb2b1d25f83..73894693a7d6 100644 --- a/drivers/staging/qcacld-3.0/components/pmo/dispatcher/inc/wlan_pmo_obj_mgmt_public_struct.h +++ b/drivers/staging/qcacld-3.0/components/pmo/dispatcher/inc/wlan_pmo_obj_mgmt_public_struct.h @@ -116,6 +116,8 @@ typedef int (*pmo_pld_auto_resume_cb)(void); * @psoc_send_target_resume_req: fp to send target resume request * @psoc_send_d0wow_enable_req: fp to send D0 WOW enable request * @psoc_send_d0wow_disable_req: fp to send D0 WOW disable request + * @psoc_send_idle_roam_suspend_mode: fp to send suspend mode for + * idle roam trigger to firmware. */ struct wlan_pmo_tx_ops { QDF_STATUS (*send_arp_offload_req)(struct wlan_objmgr_vdev *vdev, @@ -214,6 +216,8 @@ struct wlan_pmo_tx_ops { struct wlan_objmgr_psoc *psoc); QDF_STATUS (*psoc_send_d0wow_disable_req)( struct wlan_objmgr_psoc *psoc); + QDF_STATUS (*psoc_send_idle_roam_suspend_mode)( + struct wlan_objmgr_psoc *psoc, uint8_t val); }; diff --git a/drivers/staging/qcacld-3.0/components/pmo/dispatcher/inc/wlan_pmo_tgt_api.h b/drivers/staging/qcacld-3.0/components/pmo/dispatcher/inc/wlan_pmo_tgt_api.h index c265b9b3bf92..c9b8fec2f848 100644 --- a/drivers/staging/qcacld-3.0/components/pmo/dispatcher/inc/wlan_pmo_tgt_api.h +++ b/drivers/staging/qcacld-3.0/components/pmo/dispatcher/inc/wlan_pmo_tgt_api.h @@ -434,4 +434,15 @@ QDF_STATUS pmo_tgt_psoc_send_host_wakeup_ind(struct wlan_objmgr_psoc *psoc); */ QDF_STATUS pmo_tgt_psoc_send_target_resume_req(struct wlan_objmgr_psoc *psoc); +/** + * pmo_tgt_psoc_send_idle_roam_monitor() - Send idle roam set suspend mode + * command to firmware + * @psoc: objmgr psoc + * @val: Set suspend mode value + * + * Return: QDF_STATUS_SUCCESS on success else error code + */ +QDF_STATUS pmo_tgt_psoc_send_idle_roam_monitor(struct wlan_objmgr_psoc *psoc, + uint8_t val); + #endif /* end of _WLAN_PMO_TGT_API_H_ */ diff --git a/drivers/staging/qcacld-3.0/components/pmo/dispatcher/inc/wlan_pmo_ucfg_api.h b/drivers/staging/qcacld-3.0/components/pmo/dispatcher/inc/wlan_pmo_ucfg_api.h index 54774b88076a..c415c70de100 100644 --- a/drivers/staging/qcacld-3.0/components/pmo/dispatcher/inc/wlan_pmo_ucfg_api.h +++ b/drivers/staging/qcacld-3.0/components/pmo/dispatcher/inc/wlan_pmo_ucfg_api.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -151,6 +151,18 @@ void pmo_ucfg_disable_wakeup_event(struct wlan_objmgr_psoc *psoc, QDF_STATUS pmo_ucfg_cache_arp_offload_req(struct pmo_arp_req *arp_req); /** + * ucfg_pmo_check_arp_offload(): API to check if arp offload cache/send is req + * @psoc: objmgr psoc handle + * @trigger: trigger reason + * @vdev_id: vdev_id + * + * Return QDF_STATUS -in case of success else return error + */ +QDF_STATUS ucfg_pmo_check_arp_offload(struct wlan_objmgr_psoc *psoc, + enum pmo_offload_trigger trigger, + uint8_t vdev_id); + +/* * pmo_ucfg_flush_arp_offload_req(): API to flush arp req from pmo vdev priv ctx * @vdev: objmgr vdev param * @@ -201,6 +213,18 @@ pmo_ucfg_get_arp_offload_params(struct wlan_objmgr_vdev *vdev, QDF_STATUS pmo_ucfg_cache_ns_offload_req(struct pmo_ns_req *ns_req); /** + * ucfg_pmo_ns_offload_check(): API to check if offload cache/send is required + * @psoc: pbjmgr psoc handle + * @trigger: trigger reason to enable ns offload + * @vdev_id: vdev id + * + * Return QDF_STATUS -in case of success else return error + */ +QDF_STATUS ucfg_pmo_ns_offload_check(struct wlan_objmgr_psoc *psoc, + enum pmo_offload_trigger trigger, + uint8_t vdev_id); + +/* * pmo_ucfg_flush_ns_offload_req(): API to flush ns req from pmo vdev priv ctx * @vdev: vdev ojbmgr handle * @@ -554,6 +578,31 @@ QDF_STATUS pmo_ucfg_psoc_user_space_suspend_req(struct wlan_objmgr_psoc *psoc, QDF_STATUS pmo_ucfg_psoc_user_space_resume_req(struct wlan_objmgr_psoc *psoc, enum qdf_suspend_type type); +/** + * ucfg_pmo_suspend_all_components() - Suspend all components + * @psoc: objmgr psoc handle + * @type: type of suspend + * + * Suspend all components registered to pmo + * + * Return: QDF status + */ + +QDF_STATUS ucfg_pmo_suspend_all_components(struct wlan_objmgr_psoc *psoc, + enum qdf_suspend_type type); + +/** + * ucfg_pmo_resume_all_components() - Resume all components + * @psoc: objmgr psoc handle + * @type: type of suspend from which resume needed + * + * Resume all components registered to pmo + * + * Return: QDF status + */ +QDF_STATUS ucfg_pmo_resume_all_components(struct wlan_objmgr_psoc *psoc, + enum qdf_suspend_type type); + /** * pmo_ucfg_psoc_bus_suspend_req(): handles bus suspend for psoc * @psoc: objmgr psoc @@ -697,6 +746,18 @@ QDF_STATUS pmo_ucfg_config_listen_interval(struct wlan_objmgr_vdev *vdev, */ QDF_STATUS pmo_ucfg_config_modulated_dtim(struct wlan_objmgr_vdev *vdev, uint32_t mod_dtim); +/** + * ucfg_pmo_tgt_psoc_send_idle_roam_suspend_mode() - Send suspend mode to + * firmware + * @psoc: pointer to psoc object + * @val: Set suspend mode on/off sent from userspace + * + * Return: QDF_STATUS_SUCCESS if suspend mode is sent to fw else return + * corresponding QDF_STATUS failure code. + */ +QDF_STATUS +ucfg_pmo_tgt_psoc_send_idle_roam_suspend_mode(struct wlan_objmgr_psoc *psoc, + uint8_t val); #else static inline uint32_t ucfg_pmo_get_apf_instruction_size(struct wlan_objmgr_psoc *psoc) @@ -780,6 +841,14 @@ pmo_ucfg_cache_arp_offload_req(struct pmo_arp_req *arp_req) return QDF_STATUS_SUCCESS; } +static inline +QDF_STATUS ucfg_pmo_check_arp_offload(struct wlan_objmgr_psoc *psoc, + enum pmo_offload_trigger trigger, + uint8_t vdev_id) +{ + return QDF_STATUS_SUCCESS; +} + static inline QDF_STATUS pmo_ucfg_flush_arp_offload_req(struct wlan_objmgr_vdev *vdev) { @@ -815,6 +884,13 @@ pmo_ucfg_cache_ns_offload_req(struct pmo_ns_req *ns_req) return QDF_STATUS_SUCCESS; } +QDF_STATUS ucfg_pmo_ns_offload_check(struct wlan_objmgr_psoc *psoc, + enum pmo_offload_trigger trigger, + uint8_t vdev_id) +{ + return QDF_STATUS_SUCCESS; +} + static inline QDF_STATUS pmo_ucfg_flush_ns_offload_req(struct wlan_objmgr_vdev *vdev) { @@ -1035,6 +1111,20 @@ pmo_ucfg_psoc_user_space_resume_req( return QDF_STATUS_SUCCESS; } +static inline QDF_STATUS +ucfg_pmo_suspend_all_components(struct wlan_objmgr_psoc *psoc, + enum qdf_suspend_type type) +{ + return QDF_STATUS_SUCCESS; +} + +static inline QDF_STATUS +ucfg_pmo_resume_all_components(struct wlan_objmgr_psoc *psoc, + enum qdf_suspend_type type) +{ + return QDF_STATUS_SUCCESS; +} + static inline QDF_STATUS pmo_ucfg_psoc_bus_suspend_req( struct wlan_objmgr_psoc *psoc, @@ -1165,6 +1255,13 @@ pmo_ucfg_config_modulated_dtim(struct wlan_objmgr_vdev *vdev, { return QDF_STATUS_SUCCESS; } + +static inline QDF_STATUS +ucfg_pmo_tgt_psoc_send_idle_roam_suspend_mode(struct wlan_objmgr_psoc *psoc, + uint8_t val) +{ + return QDF_STATUS_SUCCESS; +} #endif /* WLAN_POWER_MANAGEMENT_OFFLOAD */ #endif /* end of _WLAN_PMO_UCFG_API_H_ */ diff --git a/drivers/staging/qcacld-3.0/components/pmo/dispatcher/src/wlan_pmo_obj_mgmt_api.c b/drivers/staging/qcacld-3.0/components/pmo/dispatcher/src/wlan_pmo_obj_mgmt_api.c index cd0f7cf2f4b7..9b99821beaa7 100644 --- a/drivers/staging/qcacld-3.0/components/pmo/dispatcher/src/wlan_pmo_obj_mgmt_api.c +++ b/drivers/staging/qcacld-3.0/components/pmo/dispatcher/src/wlan_pmo_obj_mgmt_api.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -302,8 +302,6 @@ QDF_STATUS pmo_vdev_object_destroyed_notification( struct pmo_vdev_priv_obj *vdev_ctx = NULL; QDF_STATUS status = QDF_STATUS_SUCCESS; - pmo_enter(); - vdev_ctx = pmo_vdev_get_priv(vdev); status = wlan_objmgr_vdev_component_obj_detach(vdev, @@ -315,8 +313,6 @@ QDF_STATUS pmo_vdev_object_destroyed_notification( qdf_spinlock_destroy(&vdev_ctx->pmo_vdev_lock); qdf_mem_free(vdev_ctx); - pmo_exit(); - return status; } diff --git a/drivers/staging/qcacld-3.0/components/pmo/dispatcher/src/wlan_pmo_tgt_arp.c b/drivers/staging/qcacld-3.0/components/pmo/dispatcher/src/wlan_pmo_tgt_arp.c index 50734d91be96..4f0419a81674 100644 --- a/drivers/staging/qcacld-3.0/components/pmo/dispatcher/src/wlan_pmo_tgt_arp.c +++ b/drivers/staging/qcacld-3.0/components/pmo/dispatcher/src/wlan_pmo_tgt_arp.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -36,8 +36,6 @@ QDF_STATUS pmo_tgt_enable_arp_offload_req(struct wlan_objmgr_vdev *vdev, QDF_STATUS status; struct wlan_pmo_tx_ops pmo_tx_ops; - pmo_enter(); - vdev_ctx = pmo_vdev_get_priv(vdev); psoc = pmo_vdev_get_psoc(vdev); @@ -96,7 +94,6 @@ QDF_STATUS pmo_tgt_enable_arp_offload_req(struct wlan_objmgr_vdev *vdev, qdf_mem_free(arp_offload_req); if (ns_offload_req) qdf_mem_free(ns_offload_req); - pmo_exit(); return status; } diff --git a/drivers/staging/qcacld-3.0/components/pmo/dispatcher/src/wlan_pmo_tgt_gtk.c b/drivers/staging/qcacld-3.0/components/pmo/dispatcher/src/wlan_pmo_tgt_gtk.c index 18132ea905f7..d88c60b3745e 100644 --- a/drivers/staging/qcacld-3.0/components/pmo/dispatcher/src/wlan_pmo_tgt_gtk.c +++ b/drivers/staging/qcacld-3.0/components/pmo/dispatcher/src/wlan_pmo_tgt_gtk.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -63,9 +63,9 @@ QDF_STATUS pmo_tgt_send_gtk_offload_req(struct wlan_objmgr_vdev *vdev, if (gtk_req->flags == PMO_GTK_OFFLOAD_ENABLE) { qdf_atomic_set(&vdev_ctx->gtk_err_enable, true); qdf_mem_copy(op_gtk_req->kck, gtk_req->kck, - PMO_KCK_LEN); + gtk_req->kck_len); qdf_mem_copy(op_gtk_req->kek, gtk_req->kek, - PMO_KEK_LEN); + PMO_KEK_LEN); qdf_mem_copy(&op_gtk_req->replay_counter, >k_req->replay_counter, PMO_REPLAY_COUNTER_LEN); } else { diff --git a/drivers/staging/qcacld-3.0/components/pmo/dispatcher/src/wlan_pmo_tgt_static_config.c b/drivers/staging/qcacld-3.0/components/pmo/dispatcher/src/wlan_pmo_tgt_static_config.c index 99d1b97109d3..04e63775e49a 100644 --- a/drivers/staging/qcacld-3.0/components/pmo/dispatcher/src/wlan_pmo_tgt_static_config.c +++ b/drivers/staging/qcacld-3.0/components/pmo/dispatcher/src/wlan_pmo_tgt_static_config.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -33,7 +33,6 @@ QDF_STATUS pmo_tgt_send_enhance_multicast_offload_req( struct wlan_objmgr_psoc *psoc; struct wlan_pmo_tx_ops pmo_tx_ops; - pmo_enter(); psoc = pmo_vdev_get_psoc(vdev); pmo_tx_ops = GET_PMO_TX_OPS_FROM_PSOC(psoc); @@ -47,7 +46,6 @@ QDF_STATUS pmo_tgt_send_enhance_multicast_offload_req( if (status != QDF_STATUS_SUCCESS) pmo_err("Failed to config enhance multicast offload"); out: - pmo_exit(); return status; } diff --git a/drivers/staging/qcacld-3.0/components/pmo/dispatcher/src/wlan_pmo_tgt_suspend_resume.c b/drivers/staging/qcacld-3.0/components/pmo/dispatcher/src/wlan_pmo_tgt_suspend_resume.c index c54a778a7a7f..3e89261ba49d 100644 --- a/drivers/staging/qcacld-3.0/components/pmo/dispatcher/src/wlan_pmo_tgt_suspend_resume.c +++ b/drivers/staging/qcacld-3.0/components/pmo/dispatcher/src/wlan_pmo_tgt_suspend_resume.c @@ -237,3 +237,15 @@ QDF_STATUS pmo_tgt_psoc_send_target_resume_req(struct wlan_objmgr_psoc *psoc) return pmo_tx_ops.psoc_send_target_resume_req(psoc); } +QDF_STATUS pmo_tgt_psoc_send_idle_roam_monitor(struct wlan_objmgr_psoc *psoc, + uint8_t val) +{ + struct wlan_pmo_tx_ops pmo_tx_ops; + + pmo_tx_ops = GET_PMO_TX_OPS_FROM_PSOC(psoc); + if (!pmo_tx_ops.psoc_send_idle_roam_suspend_mode) { + pmo_err("NULL fp"); + return QDF_STATUS_E_NULL_VALUE; + } + return pmo_tx_ops.psoc_send_idle_roam_suspend_mode(psoc, val); +} diff --git a/drivers/staging/qcacld-3.0/components/pmo/dispatcher/src/wlan_pmo_tgt_wow.c b/drivers/staging/qcacld-3.0/components/pmo/dispatcher/src/wlan_pmo_tgt_wow.c index d527be03f54b..312cfd883730 100644 --- a/drivers/staging/qcacld-3.0/components/pmo/dispatcher/src/wlan_pmo_tgt_wow.c +++ b/drivers/staging/qcacld-3.0/components/pmo/dispatcher/src/wlan_pmo_tgt_wow.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -34,8 +34,6 @@ QDF_STATUS pmo_tgt_enable_wow_wakeup_event( struct wlan_pmo_tx_ops pmo_tx_ops; int vdev_id; - pmo_enter(); - psoc = pmo_vdev_get_psoc(vdev); vdev_id = pmo_vdev_get_id(vdev); @@ -53,7 +51,6 @@ QDF_STATUS pmo_tgt_enable_wow_wakeup_event( if (status != QDF_STATUS_SUCCESS) pmo_err("Failed to enable wow wakeup event"); out: - pmo_exit(); return status; } @@ -102,7 +99,6 @@ QDF_STATUS pmo_tgt_send_wow_patterns_to_fw( struct wlan_objmgr_psoc *psoc; struct wlan_pmo_tx_ops pmo_tx_ops; - pmo_enter(); psoc = pmo_vdev_get_psoc(vdev); vdev_ctx = pmo_vdev_get_priv(vdev); @@ -127,7 +123,6 @@ QDF_STATUS pmo_tgt_send_wow_patterns_to_fw( if (user) pmo_increment_wow_user_ptrn(vdev_ctx); out: - pmo_exit(); return status; } @@ -141,7 +136,6 @@ QDF_STATUS pmo_tgt_del_wow_pattern( struct wlan_objmgr_psoc *psoc; struct wlan_pmo_tx_ops pmo_tx_ops; - pmo_enter(); psoc = pmo_vdev_get_psoc(vdev); vdev_ctx = pmo_vdev_get_priv(vdev); @@ -160,7 +154,6 @@ QDF_STATUS pmo_tgt_del_wow_pattern( if (user) pmo_decrement_wow_user_ptrn(vdev_ctx); out: - pmo_exit(); return status; } diff --git a/drivers/staging/qcacld-3.0/components/pmo/dispatcher/src/wlan_pmo_ucfg_api.c b/drivers/staging/qcacld-3.0/components/pmo/dispatcher/src/wlan_pmo_ucfg_api.c index a8251e0e9adf..69dfcf9aafc3 100644 --- a/drivers/staging/qcacld-3.0/components/pmo/dispatcher/src/wlan_pmo_ucfg_api.c +++ b/drivers/staging/qcacld-3.0/components/pmo/dispatcher/src/wlan_pmo_ucfg_api.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -120,6 +120,13 @@ QDF_STATUS pmo_ucfg_cache_arp_offload_req(struct pmo_arp_req *arp_req) return pmo_core_cache_arp_offload_req(arp_req); } +QDF_STATUS ucfg_pmo_check_arp_offload(struct wlan_objmgr_psoc *psoc, + enum pmo_offload_trigger trigger, + uint8_t vdev_id) +{ + return pmo_core_arp_check_offload(psoc, trigger, vdev_id); +} + QDF_STATUS pmo_ucfg_flush_arp_offload_req(struct wlan_objmgr_vdev *vdev) { return pmo_core_flush_arp_offload_req(vdev); @@ -149,6 +156,13 @@ QDF_STATUS pmo_ucfg_cache_ns_offload_req(struct pmo_ns_req *ns_req) return pmo_core_cache_ns_offload_req(ns_req); } +QDF_STATUS ucfg_pmo_ns_offload_check(struct wlan_objmgr_psoc *psoc, + enum pmo_offload_trigger trigger, + uint8_t vdev_id) +{ + return pmo_core_ns_check_offload(psoc, trigger, vdev_id); +} + QDF_STATUS pmo_ucfg_flush_ns_offload_req(struct wlan_objmgr_vdev *vdev) { return pmo_core_flush_ns_offload_req(vdev); @@ -383,6 +397,18 @@ QDF_STATUS pmo_ucfg_add_wow_user_pattern(struct wlan_objmgr_vdev *vdev, return pmo_core_add_wow_user_pattern(vdev, ptrn); } +QDF_STATUS ucfg_pmo_suspend_all_components(struct wlan_objmgr_psoc *psoc, + enum qdf_suspend_type type) +{ + return pmo_suspend_all_components(psoc, type); +} + +QDF_STATUS ucfg_pmo_resume_all_components(struct wlan_objmgr_psoc *psoc, + enum qdf_suspend_type type) +{ + return pmo_resume_all_components(psoc, type); +} + QDF_STATUS ucfg_pmo_del_wow_pattern(struct wlan_objmgr_vdev *vdev) { @@ -448,3 +474,9 @@ QDF_STATUS pmo_ucfg_config_modulated_dtim(struct wlan_objmgr_vdev *vdev, return pmo_core_config_modulated_dtim(vdev, mod_dtim); } +QDF_STATUS +ucfg_pmo_tgt_psoc_send_idle_roam_suspend_mode(struct wlan_objmgr_psoc *psoc, + uint8_t val) +{ + return pmo_tgt_psoc_send_idle_roam_monitor(psoc, val); +} diff --git a/drivers/staging/qcacld-3.0/components/target_if/ftm_time_sync/inc/target_if_ftm_time_sync.h b/drivers/staging/qcacld-3.0/components/target_if/ftm_time_sync/inc/target_if_ftm_time_sync.h new file mode 100644 index 000000000000..05fe3fdcd12f --- /dev/null +++ b/drivers/staging/qcacld-3.0/components/target_if/ftm_time_sync/inc/target_if_ftm_time_sync.h @@ -0,0 +1,59 @@ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +/** + * DOC: Declare various api/struct which shall be used + * by FTM time sync component for wmi cmd (tx path) and + * event (rx) handling. + */ + +#ifndef _TARGET_IF_FTM_TIME_SYNC_H_ +#define _TARGET_IF_FTM_TIME_SYNC_H_ + +#include +#include +#include "wlan_ftm_time_sync_public_struct.h" + +/** + * target_if_ftm_time_sync_register_rx_ops() - Register FTM TIME SYNC component + * RX ops + * @rx_ops: FTM time sync component reception ops + * + * Return: None + */ +void target_if_ftm_time_sync_register_rx_ops(struct wlan_ftm_time_sync_rx_ops + *rx_ops); + +/** + * target_if_ftm_time_sync_register_tx_ops() - Register FTM TIME SYNC component + * TX OPS + * @tx_ops: FTM time sync component transmit ops + * + * Return: None + */ +void target_if_ftm_time_sync_register_tx_ops(struct wlan_ftm_time_sync_tx_ops + *tx_ops); + +/** + * target_if_ftm_time_sync_unregister_ev_handlers() - Unregister wmi events + * handlers + * @psoc: psoc context + * + * Return: QDF_STATUS + */ +QDF_STATUS +target_if_ftm_time_sync_unregister_ev_handlers(struct wlan_objmgr_psoc *psoc); +#endif /*_TARGET_IF_FTM_TIME_SYNC_H_ */ diff --git a/drivers/staging/qcacld-3.0/components/target_if/ftm_time_sync/src/target_if_ftm_time_sync.c b/drivers/staging/qcacld-3.0/components/target_if/ftm_time_sync/src/target_if_ftm_time_sync.c new file mode 100644 index 000000000000..33194e6b77b5 --- /dev/null +++ b/drivers/staging/qcacld-3.0/components/target_if/ftm_time_sync/src/target_if_ftm_time_sync.c @@ -0,0 +1,239 @@ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +/** + * DOC: Target interface file for ftm time sync component to + * Implement api's which shall be used by ftm time sync component + * in target_if internally. + */ + +#include "target_if.h" +#include "target_if_ftm_time_sync.h" +#include "wlan_ftm_time_sync_public_struct.h" +#include "wlan_ftm_time_sync_tgt_api.h" +#include +#include + +static QDF_STATUS +target_if_ftm_time_sync_send_qtime(struct wlan_objmgr_psoc *psoc, + uint32_t vdev_id, uint64_t lpass_ts) +{ + wmi_unified_t wmi_hdl; + + wmi_hdl = get_wmi_unified_hdl_from_psoc(psoc); + if (!wmi_hdl) + return QDF_STATUS_E_FAILURE; + + return wmi_unified_send_wlan_time_sync_qtime(wmi_hdl, vdev_id, + lpass_ts); +} + +static QDF_STATUS +target_if_ftm_time_sync_send_trigger(struct wlan_objmgr_psoc *psoc, + uint32_t vdev_id, bool mode) +{ + wmi_unified_t wmi_hdl; + + wmi_hdl = get_wmi_unified_hdl_from_psoc(psoc); + if (!wmi_hdl) + return QDF_STATUS_E_FAILURE; + + return wmi_unified_send_wlan_time_sync_ftm_trigger(wmi_hdl, vdev_id, + mode); +} + +static int +target_if_time_sync_ftm_start_stop_event_handler(ol_scn_t scn_handle, + uint8_t *data, uint32_t len) +{ + struct ftm_time_sync_start_stop_params param; + struct wlan_objmgr_psoc *psoc; + wmi_unified_t wmi_handle; + + if (!data) { + target_if_err("%s: invalid pointer", __func__); + return -EINVAL; + } + + psoc = target_if_get_psoc_from_scn_hdl(scn_handle); + if (!psoc) { + target_if_err("psoc ptr is NULL"); + return -EINVAL; + } + + wmi_handle = get_wmi_unified_hdl_from_psoc(psoc); + if (!wmi_handle) { + target_if_err("Invalid wmi handle"); + return -EINVAL; + } + + if (wmi_unified_extract_time_sync_ftm_start_stop_params( + wmi_handle, data, ¶m) != QDF_STATUS_SUCCESS) { + target_if_err("Extraction of time sync ftm start stop failed"); + return -EINVAL; + } + + tgt_ftm_ts_start_stop_evt(psoc, ¶m); + + return 0; +} + +static QDF_STATUS +target_if_ftm_time_sync_start_stop_event(struct wlan_objmgr_psoc *psoc) +{ + QDF_STATUS status; + wmi_unified_t wmi_handle; + + wmi_handle = get_wmi_unified_hdl_from_psoc(psoc); + if (!wmi_handle) { + target_if_err("Invalid wmi handle"); + return QDF_STATUS_E_INVAL; + } + + status = wmi_unified_register_event_handler( + wmi_handle, wmi_wlan_time_sync_ftm_start_stop_event_id, + target_if_time_sync_ftm_start_stop_event_handler, + WMA_RX_SERIALIZER_CTX); + if (status) { + target_if_err("Ftm time_sync start stop event register failed"); + return QDF_STATUS_E_FAILURE; + } + + return status; +} + +static int +target_if_time_sync_master_slave_offset_event_handler(ol_scn_t scn_handle, + uint8_t *data, + uint32_t len) +{ + struct ftm_time_sync_offset param; + struct wlan_objmgr_psoc *psoc; + wmi_unified_t wmi_handle; + + if (!data) { + target_if_err("%s: invalid pointer", __func__); + return -EINVAL; + } + + psoc = target_if_get_psoc_from_scn_hdl(scn_handle); + if (!psoc) { + target_if_err("psoc ptr is NULL"); + return -EINVAL; + } + + wmi_handle = get_wmi_unified_hdl_from_psoc(psoc); + if (!wmi_handle) { + target_if_err("Invalid wmi handle"); + return -EINVAL; + } + + if (wmi_unified_extract_time_sync_ftm_offset( + wmi_handle, data, ¶m) != QDF_STATUS_SUCCESS) { + target_if_err("time_sync ftm offset param extraction failed"); + return -EINVAL; + } + + tgt_ftm_ts_offset_evt(psoc, ¶m); + + return 0; +} + +static QDF_STATUS +target_if_ftm_time_sync_master_slave_offset(struct wlan_objmgr_psoc *psoc) +{ + QDF_STATUS status; + wmi_unified_t wmi_handle; + + wmi_handle = get_wmi_unified_hdl_from_psoc(psoc); + if (!wmi_handle) { + target_if_err("Invalid wmi handle"); + return QDF_STATUS_E_INVAL; + } + + status = wmi_unified_register_event_handler( + wmi_handle, + wmi_wlan_time_sync_q_master_slave_offset_eventid, + target_if_time_sync_master_slave_offset_event_handler, + WMA_RX_SERIALIZER_CTX); + if (status) { + target_if_err("Ftm time_sync offset event register failed"); + return QDF_STATUS_E_FAILURE; + } + + return status; +} + +QDF_STATUS +target_if_ftm_time_sync_unregister_ev_handlers(struct wlan_objmgr_psoc *psoc) +{ + wmi_unified_t wmi_handle; + int ret, status = 0; + + wmi_handle = get_wmi_unified_hdl_from_psoc(psoc); + if (!wmi_handle) { + target_if_err("Invalid wmi handle"); + return QDF_STATUS_E_INVAL; + } + + ret = wmi_unified_unregister_event( + wmi_handle, + wmi_wlan_time_sync_ftm_start_stop_event_id); + if (ret) { + target_if_err("failed to unregister time sync start/stop evt"); + status = ret; + } + + ret = wmi_unified_unregister_event( + wmi_handle, + wmi_wlan_time_sync_q_master_slave_offset_eventid); + if (ret) { + target_if_err("failed to unregister time sync offset evt"); + status = ret; + } + + if (status) + return QDF_STATUS_E_FAILURE; + else + return QDF_STATUS_SUCCESS; +} + +void target_if_ftm_time_sync_register_rx_ops( + struct wlan_ftm_time_sync_rx_ops *rx_ops) +{ + if (!rx_ops) { + target_if_err("FTM time_sync rx_ops is null"); + return; + } + + rx_ops->ftm_time_sync_register_start_stop = + target_if_ftm_time_sync_start_stop_event; + rx_ops->ftm_time_sync_regiser_master_slave_offset = + target_if_ftm_time_sync_master_slave_offset; +} + +void target_if_ftm_time_sync_register_tx_ops( + struct wlan_ftm_time_sync_tx_ops *tx_ops) +{ + if (!tx_ops) { + target_if_err("FTM time_sync tx_ops is null"); + return; + } + + tx_ops->ftm_time_sync_send_qtime = target_if_ftm_time_sync_send_qtime; + tx_ops->ftm_time_sync_send_trigger = + target_if_ftm_time_sync_send_trigger; +} diff --git a/drivers/staging/qcacld-3.0/components/target_if/pkt_capture/inc/target_if_pkt_capture.h b/drivers/staging/qcacld-3.0/components/target_if/pkt_capture/inc/target_if_pkt_capture.h new file mode 100644 index 000000000000..10ded23c9568 --- /dev/null +++ b/drivers/staging/qcacld-3.0/components/target_if/pkt_capture/inc/target_if_pkt_capture.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/** + * DOC: Declare various api/struct which shall be used + * by packet capture component for wmi cmd (tx path) and + * event (rx) handling. + */ + +#ifndef _TARGET_IF_PKT_CAPTURE_H_ +#define _TARGET_IF_PKT_CAPTURE_H_ + +#include +#include +#include +#include +#include +#include + +/** + * target_if_pkt_capture_register_rx_ops() - Register packet capture RX ops + * @rx_ops: packet capture component reception ops + * Return: None + */ +void +target_if_pkt_capture_register_rx_ops(struct wlan_pkt_capture_rx_ops *rx_ops); + +/** + * target_if_pkt_capture_register_tx_ops() - Register packet capture TX ops + * @tx_ops: pkt capture component transmit ops + * + * Return: None + */ +void target_if_pkt_capture_register_tx_ops(struct wlan_pkt_capture_tx_ops + *tx_ops); +#endif /* _TARGET_IF_PKT_CAPTURE_H_ */ diff --git a/drivers/staging/qcacld-3.0/components/target_if/pkt_capture/src/target_if_pkt_capture.c b/drivers/staging/qcacld-3.0/components/target_if/pkt_capture/src/target_if_pkt_capture.c new file mode 100644 index 000000000000..eeee59cbb872 --- /dev/null +++ b/drivers/staging/qcacld-3.0/components/target_if/pkt_capture/src/target_if_pkt_capture.c @@ -0,0 +1,220 @@ +/* + * Copyright (c) 2020 The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for + * any purpose with or without fee is hereby granted, provided that the + * above copyright notice and this permission notice appear in all + * copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL + * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE + * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL + * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR + * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + */ + +/** + * DOC: Target interface file for pkt_capture component to + * Implement api's which shall be used by pkt_capture component + * in target_if internally. + */ + +#include +#include +#include +#include + +/** + * target_if_set_packet_capture_mode() - set packet capture mode + * @psoc: pointer to psoc object + * @vdev_id: vdev id + * @mode: mode to set + * + * Return: QDF_STATUS + */ +static QDF_STATUS +target_if_set_packet_capture_mode(struct wlan_objmgr_psoc *psoc, + uint8_t vdev_id, + enum pkt_capture_mode mode) +{ + wmi_unified_t wmi_handle = lmac_get_wmi_unified_hdl(psoc); + QDF_STATUS status = QDF_STATUS_E_FAILURE; + + if (!wmi_handle) { + target_if_err("Invalid wmi handle"); + return QDF_STATUS_E_INVAL; + } + + target_if_debug("psoc:%pK, vdev_id:%d mode:%d", + psoc, vdev_id, mode); + + if (mode != PACKET_CAPTURE_MODE_DISABLE) { + struct vdev_set_params param; + + param.if_id = vdev_id; + param.param_id = WMI_VDEV_PARAM_PACKET_CAPTURE_MODE; + param.param_value = (uint32_t)mode; + + status = wmi_unified_vdev_set_param_send(wmi_handle, ¶m); + if (QDF_IS_STATUS_SUCCESS(status)) + ucfg_pkt_capture_set_pktcap_mode(psoc, mode); + else + pkt_capture_err("failed to set packet capture mode"); + } + return status; +} + +/** + * target_if_mgmt_offload_data_event_handler() - offload event handler + * @handle: scn handle + * @data: mgmt data + * @data_len: data length + * + * Process management offload frame. + * + * Return: 0 for success or error code + */ +static int +target_if_mgmt_offload_data_event_handler(void *handle, uint8_t *data, + uint32_t data_len) +{ + static uint8_t limit_prints_invalid_len = RATE_LIMIT - 1; + struct mgmt_offload_event_params params; + struct wmi_unified *wmi_handle; + struct wlan_objmgr_psoc *psoc; + struct wlan_objmgr_pdev *pdev; + QDF_STATUS status; + qdf_nbuf_t wbuf; + + psoc = target_if_get_psoc_from_scn_hdl(handle); + if (!psoc) { + pkt_capture_err("psoc is NULL"); + return -EINVAL; + } + + wmi_handle = get_wmi_unified_hdl_from_psoc(psoc); + if (!wmi_handle) { + target_if_err("Invalid WMI handle"); + return -EINVAL; + } + + pdev = target_if_get_pdev_from_scn_hdl(handle); + if (!pdev) { + pkt_capture_err("pdev is NULL"); + return -EINVAL; + } + + if (!(ucfg_pkt_capture_get_pktcap_mode() & + PKT_CAPTURE_MODE_MGMT_ONLY)) + return -EINVAL; + + status = wmi_unified_extract_vdev_mgmt_offload_event(wmi_handle, data, + ¶ms); + if (QDF_IS_STATUS_ERROR(status)) { + pkt_capture_err("Extract mgmt offload event failed"); + return -EINVAL; + } + + if (!params.buf) { + pkt_capture_err("Mgmt offload buf is NULL"); + return -EINVAL; + } + + if (params.buf_len < sizeof(struct ieee80211_hdr_3addr) || + params.buf_len > data_len) { + limit_prints_invalid_len++; + if (limit_prints_invalid_len == RATE_LIMIT) { + pkt_capture_debug( + "Invalid mgmt packet, data_len %u, params.buf_len %u", + data_len, params.buf_len); + limit_prints_invalid_len = 0; + } + return -EINVAL; + } + + wbuf = qdf_nbuf_alloc(NULL, + roundup(params.buf_len + RESERVE_BYTES, 4), + RESERVE_BYTES, 4, false); + if (!wbuf) { + pkt_capture_err("Failed to allocate wbuf for mgmt pkt len(%u)", + params.buf_len); + return -ENOMEM; + } + + qdf_nbuf_put_tail(wbuf, params.buf_len); + qdf_nbuf_set_protocol(wbuf, ETH_P_CONTROL); + qdf_mem_copy(qdf_nbuf_data(wbuf), params.buf, params.buf_len); + + status = params.tx_status; + if (QDF_STATUS_SUCCESS != + ucfg_pkt_capture_process_mgmt_tx_data(pdev, ¶ms, + wbuf, status)) + qdf_nbuf_free(wbuf); + + return 0; +} + +/** + * target_if_register_mgmt_data_offload_event() - Register mgmt data offload + * event handler + * @psoc: wlan psoc object + * + * Return: QDF_STATUS + */ +static QDF_STATUS +target_if_register_mgmt_data_offload_event(struct wlan_objmgr_psoc *psoc) +{ + wmi_unified_t wmi_handle; + + PKT_CAPTURE_ENTER(); + + if (!psoc) { + pkt_capture_err("psoc got NULL"); + return QDF_STATUS_E_FAILURE; + } + wmi_handle = get_wmi_unified_hdl_from_psoc(psoc); + + if (ucfg_pkt_capture_get_mode(psoc) && + wmi_service_enabled(wmi_handle, + wmi_service_packet_capture_support)) { + uint8_t status; + + status = wmi_unified_register_event_handler( + wmi_handle, + wmi_mgmt_offload_data_event_id, + target_if_mgmt_offload_data_event_handler, + WMI_RX_WORK_CTX); + if (status) { + pkt_capture_err("Failed to register MGMT offload handler"); + return QDF_STATUS_E_FAILURE; + } + } + PKT_CAPTURE_ENTER(); + return QDF_STATUS_SUCCESS; +} + +void +target_if_pkt_capture_register_rx_ops(struct wlan_pkt_capture_rx_ops *rx_ops) +{ + if (!rx_ops) { + target_if_err("packet capture rx_ops is null"); + return; + } + + rx_ops->pkt_capture_register_mgmt_data_offload_event = + target_if_register_mgmt_data_offload_event; +} + +void +target_if_pkt_capture_register_tx_ops(struct wlan_pkt_capture_tx_ops *tx_ops) +{ + if (!tx_ops) { + target_if_err("packet capture tx_ops is null"); + return; + } + + tx_ops->pkt_capture_send_mode = target_if_set_packet_capture_mode; +} diff --git a/drivers/staging/qcacld-3.0/components/target_if/pmo/inc/target_if_pmo.h b/drivers/staging/qcacld-3.0/components/target_if/pmo/inc/target_if_pmo.h index d5b772c21549..525d93fb29ea 100644 --- a/drivers/staging/qcacld-3.0/components/target_if/pmo/inc/target_if_pmo.h +++ b/drivers/staging/qcacld-3.0/components/target_if/pmo/inc/target_if_pmo.h @@ -450,6 +450,17 @@ QDF_STATUS target_if_pmo_psoc_send_d0wow_enable_req( QDF_STATUS target_if_pmo_psoc_send_d0wow_disable_req( struct wlan_objmgr_psoc *psoc); +/** + * target_if_pmo_psoc_send_idle_monitor_cmd() - send screen status to firmware + * @psoc: objmgr psoc + * @val: Idle monitor value + * + * Return: QDF_STATUS_SUCCESS on success else error code + */ +QDF_STATUS +target_if_pmo_psoc_send_idle_monitor_cmd(struct wlan_objmgr_psoc *psoc, + uint8_t val); + /** * target_if_pmo_register_tx_ops() - Register PMO component TX OPS * @tx_ops: PMO if transmit ops diff --git a/drivers/staging/qcacld-3.0/components/target_if/pmo/src/target_if_pmo_main.c b/drivers/staging/qcacld-3.0/components/target_if/pmo/src/target_if_pmo_main.c index 834f88f68829..dccdc8d528b7 100644 --- a/drivers/staging/qcacld-3.0/components/target_if/pmo/src/target_if_pmo_main.c +++ b/drivers/staging/qcacld-3.0/components/target_if/pmo/src/target_if_pmo_main.c @@ -108,5 +108,7 @@ void target_if_pmo_register_tx_ops(struct wlan_pmo_tx_ops *pmo_tx_ops) pmo_tx_ops->send_clear_pkt_filter = target_if_pmo_clear_pkt_filter_req; + pmo_tx_ops->psoc_send_idle_roam_suspend_mode = + target_if_pmo_psoc_send_idle_monitor_cmd; } diff --git a/drivers/staging/qcacld-3.0/components/target_if/pmo/src/target_if_pmo_suspend_resume.c b/drivers/staging/qcacld-3.0/components/target_if/pmo/src/target_if_pmo_suspend_resume.c index 52f9720c373b..75479458e169 100644 --- a/drivers/staging/qcacld-3.0/components/target_if/pmo/src/target_if_pmo_suspend_resume.c +++ b/drivers/staging/qcacld-3.0/components/target_if/pmo/src/target_if_pmo_suspend_resume.c @@ -290,6 +290,21 @@ QDF_STATUS target_if_pmo_psoc_send_target_resume_req( return wmi_unified_resume_send(wmi_handle, TGT_WILDCARD_PDEV_ID); } +QDF_STATUS +target_if_pmo_psoc_send_idle_monitor_cmd(struct wlan_objmgr_psoc *psoc, + uint8_t val) +{ + wmi_unified_t wmi_handle; + + wmi_handle = get_wmi_unified_hdl_from_psoc(psoc); + if (!wmi_handle) { + target_if_err("Invalid wmi handle"); + return QDF_STATUS_E_INVAL; + } + + return wmi_unified_send_idle_trigger_monitor(wmi_handle, val); +} + #ifdef FEATURE_WLAN_D0WOW QDF_STATUS target_if_pmo_psoc_send_d0wow_enable_req( struct wlan_objmgr_psoc *psoc) diff --git a/drivers/staging/qcacld-3.0/configs/default_defconfig b/drivers/staging/qcacld-3.0/configs/default_defconfig index d9102a03176d..b6628b735406 100644 --- a/drivers/staging/qcacld-3.0/configs/default_defconfig +++ b/drivers/staging/qcacld-3.0/configs/default_defconfig @@ -18,6 +18,7 @@ endif ifdef CONFIG_ICNSS CONFIG_ROME_IF = snoc + CONFIG_QCA_WIFI_SDIO := n endif ifeq (y,$(findstring y,$(CONFIG_CNSS) $(CONFIG_CNSS2))) @@ -34,6 +35,7 @@ ifeq ($(CONFIG_ICNSS), y) CONFIG_HELIUMPLUS := y CONFIG_64BIT_PADDR := y CONFIG_FEATURE_TSO := y + CONFIG_FEATURE_TSO_DEBUG := y ifeq ($(CONFIG_INET_LRO), y) CONFIG_WLAN_LRO := y else @@ -114,14 +116,6 @@ ifeq ($(CONFIG_ARCH_MSM8998), y) CONFIG_QCACLD_FEATURE_METERING := y endif -ifeq ($(CONFIG_ARCH_SDM660), y) -CONFIG_QCACLD_FEATURE_METERING := y -endif - -ifeq ($(CONFIG_ARCH_SDM630), y) -CONFIG_QCACLD_FEATURE_METERING := y -endif - ifeq ($(CONFIG_ARCH_SDM845), y) CONFIG_QCACLD_FEATURE_METERING := y endif @@ -130,11 +124,7 @@ ifeq ($(CONFIG_ARCH_SM8150), y) CONFIG_QCACLD_FEATURE_METERING := y endif -ifeq ($(CONFIG_ARCH_SDM670), y) -CONFIG_QCACLD_FEATURE_METERING := y -endif - -ifeq ($(CONFIG_ARCH_SM6150), y) +ifeq ($(CONFIG_HELIUMPLUS), y) CONFIG_QCACLD_FEATURE_METERING := y endif @@ -144,6 +134,12 @@ CONFIG_QCOM_VOWIFI_11R := y #Flag to enable disable ACTION OUI feature CONFIG_WLAN_FEATURE_ACTION_OUI := y +#Flag to enable Adaptive 11r feature +CONFIG_ADAPTIVE_11R := y + +#Flag to enable sae single pmk feature +CONFIG_SAE_SINGLE_PMK := y + #Flag to enable FILS Feature (11ai) CONFIG_WLAN_FEATURE_FILS := y ifneq ($(CONFIG_QCA_CLD_WLAN),) @@ -303,6 +299,7 @@ CONFIG_DP_INTR_POLL_BASED := y CONFIG_TX_PER_PDEV_DESC_POOL := y CONFIG_DP_TRACE := y CONFIG_FEATURE_TSO := y +CONFIG_TSO_DEBUG_LOG_ENABLE := y CONFIG_DP_LFR := y CONFIG_HTT_PADDR64 := y CONFIG_RX_OL := y @@ -368,6 +365,7 @@ CONFIG_WLAN_LOG_FATAL := y CONFIG_WLAN_LOG_ERROR := y CONFIG_WLAN_LOG_WARN := y CONFIG_WLAN_LOG_INFO := y +CONFIG_WLAN_LOG_DEBUG := y #Enable OL debug and wmi unified functions CONFIG_ATH_PERF_PWR_OFFLOAD := y @@ -439,6 +437,12 @@ CONFIG_ATH_SUPPORT_FLOWMAC_MODULE := n #Enable spectral support CONFIG_ATH_SUPPORT_SPECTRAL := n +#Customize DSCP_to-UP map based on RFC8325 +ifeq ($(CONFIG_HELIUMPLUS), y) +CONFIG_WLAN_CUSTOM_DSCP_UP_MAP := y +CONFIG_WLAN_SEND_DSCP_UP_MAP_TO_FW := y +endif + #Enable WDI Event support ifeq ($(CONFIG_REMOVE_PKT_LOG), y) CONFIG_WDI_EVENT_ENABLE := n @@ -490,33 +494,15 @@ CONFIG_ENABLE_SMMU_S1_TRANSLATION := y endif endif -ifeq ($(CONFIG_ARCH_SDMMAGPIE), y) -ifeq ($(CONFIG_IPA_OFFLOAD), y) -CONFIG_ENABLE_SMMU_S1_TRANSLATION := y -endif -endif - -ifeq ($(CONFIG_ARCH_LITO), y) -ifeq ($(CONFIG_IPA_OFFLOAD), y) -CONFIG_ENABLE_SMMU_S1_TRANSLATION := y -endif -endif - -ifeq ($(CONFIG_ARCH_ATOLL), y) +ifeq ($(CONFIG_HELIUMPLUS), y) +ifneq ($(CONFIG_ARCH_SDM630), y) +ifneq ($(CONFIG_ARCH_SDM660), y) +ifneq ($(CONFIG_ARCH_MSM8998), y) ifeq ($(CONFIG_IPA_OFFLOAD), y) CONFIG_ENABLE_SMMU_S1_TRANSLATION := y endif endif - -ifeq ($(CONFIG_ARCH_TRINKET), y) -ifeq ($(CONFIG_IPA_OFFLOAD), y) -CONFIG_ENABLE_SMMU_S1_TRANSLATION := y -endif endif - -ifeq ($(CONFIG_ARCH_SM6150), y) -ifeq ($(CONFIG_IPA_OFFLOAD), y) -CONFIG_ENABLE_SMMU_S1_TRANSLATION := y endif endif @@ -549,9 +535,15 @@ CONFIG_FEATURE_HTC_CREDIT_HISTORY := y #Flag to enable MTRACE feature CONFIG_TRACE_RECORD_FEATURE := y +#Flag to enable p2p debug feature +CONFIG_WLAN_FEATURE_P2P_DEBUG := y + #Flag to enable DFS Master feature CONFIG_WLAN_DFS_MASTER_ENABLE := y +#Flag to enable/disable MTRACE feature +CONFIG_ENABLE_MTRACE_LOG := y + #Flag to enable nud tracking feature CONFIG_WLAN_NUD_TRACKING := y @@ -564,6 +556,10 @@ CONFIG_DISABLE_CHANNEL_LIST :=y #Flag to enable beacon receive feature CONFIG_WLAN_BCN_RECV_FEATURE := y +#Flag to enable SAR Safety Feature +CONFIG_SAR_SAFETY_FEATURE := y + + CONFIG_WIFI_POS_CONVERGED := y ifneq ($(CONFIG_WIFI_POS_CONVERGED), y) CONFIG_WIFI_POS_LEGACY := y @@ -575,6 +571,9 @@ CONFIG_FEATURE_WLAN_WAPI := y CONFIG_AGEIE_ON_SCAN_RESULTS := y +#Flag to enable FW log parsing support feature +CONFIG_FEATURE_FW_LOG_PARSING := y + CONFIG_PTT_SOCK_SVC_ENABLE := y CONFIG_SOFTAP_CHANNEL_RANGE := y CONFIG_FEATURE_WLAN_SCAN_PNO := y @@ -622,6 +621,9 @@ ifeq ($(CONFIG_LITHIUM), y) CONFIG_FEATURE_UNIT_TEST_SUSPEND := y endif +#Flag to enable hdd memory dump feature +CONFIG_FEATURE_MEMDUMP_ENABLE := y + #Flag to enable/disable WLAN D0-WOW ifeq ($(CONFIG_PCI_MSM), y) ifeq ($(CONFIG_HIF_PCI), y) @@ -659,3 +661,19 @@ CONFIG_FEATURE_BECN_STATS := y ifeq ($(CONFIG_ARCH_QCS405), y) CONFIG_QCACLD_FEATURE_MPTA_HELPER := y endif + +#Enable support to get ANI level +CONFIG_ANI_LEVEL_REQUEST := y + +#Enable OEM DATA feature +CONFIG_FEATURE_OEM_DATA := y + +ifeq ($(CONFIG_ARCH_QCS405), y) +ifeq ($(CONFIG_CNSS_TIMESYNC), y) +CONFIG_FEATURE_WLAN_TIME_SYNC_FTM := y +endif +endif + +ifeq ($(CONFIG_ARCH_SDM660), y) +CONFIG_WLAN_FEATURE_PKT_CAPTURE := y +endif diff --git a/drivers/staging/qcacld-3.0/configs/qcs40x.snoc.perf_defconfig b/drivers/staging/qcacld-3.0/configs/qcs40x.snoc.perf_defconfig index 598ddaf5dd02..1dd63fcb781b 100644 --- a/drivers/staging/qcacld-3.0/configs/qcs40x.snoc.perf_defconfig +++ b/drivers/staging/qcacld-3.0/configs/qcs40x.snoc.perf_defconfig @@ -176,6 +176,11 @@ endif endif CONFIG_ENABLE_SIZE_OPTIMIZE := y +CONFIG_WLAN_FEATURE_ETHTOOL :=y + +ifeq ($(CONFIG_CNSS_TIMESYNC), y) +CONFIG_FEATURE_WLAN_TIME_SYNC_FTM := y +endif # configure log buffer size CONFIG_CFG_NUM_DP_TRACE_RECORD := 1000 diff --git a/drivers/staging/qcacld-3.0/configs/whunt_defconfig b/drivers/staging/qcacld-3.0/configs/whunt_defconfig new file mode 100644 index 000000000000..0a3277616be8 --- /dev/null +++ b/drivers/staging/qcacld-3.0/configs/whunt_defconfig @@ -0,0 +1,7 @@ +#Enable 6 GHz Band +CONFIG_BAND_6GHZ := y + +#Enable 11AX Feature +CONFIG_WLAN_FEATURE_11AX := y + +include $(WLAN_ROOT)/configs/default_defconfig diff --git a/drivers/staging/qcacld-3.0/core/cds/inc/cds_api.h b/drivers/staging/qcacld-3.0/core/cds/inc/cds_api.h index 08ed54650966..b5e16250e886 100644 --- a/drivers/staging/qcacld-3.0/core/cds/inc/cds_api.h +++ b/drivers/staging/qcacld-3.0/core/cds/inc/cds_api.h @@ -406,8 +406,26 @@ bool cds_is_packet_log_enabled(void) { return false; } + +/** + * cds_get_packet_log_buffer_size() - get packet log buffer size + * + * Return: packet log buffer size in MB + */ +static inline +uint8_t cds_get_packet_log_buffer_size(void) +{ + return 0; +} #else bool cds_is_packet_log_enabled(void); + +/** + * cds_get_packet_log_buffer_size() - get packet log buffer size + * + * Return: packet log buffer size in MB + */ +uint8_t cds_get_packet_log_buffer_size(void); #endif uint64_t cds_get_monotonic_boottime(void); diff --git a/drivers/staging/qcacld-3.0/core/cds/inc/cds_config.h b/drivers/staging/qcacld-3.0/core/cds/inc/cds_config.h index f9c2cd9e2b24..8bd9d4f3fa41 100644 --- a/drivers/staging/qcacld-3.0/core/cds/inc/cds_config.h +++ b/drivers/staging/qcacld-3.0/core/cds/inc/cds_config.h @@ -93,6 +93,8 @@ enum active_apf_mode { * @tx_flow_start_queue_offset: Start queue offset in percentage * @is_lpass_enabled: Indicate whether LPASS is enabled or not * @is_nan_enabled: Indicate whether NAN is enabled or not + * @nan_separate_iface_support: Indicate whether separate iface for NAN is + * enabled or not * @bool apf_packet_filter_enable; Indicate apf filter enabled or not * @tx_chain_mask_cck: Tx chain mask enabled or not * @self_gen_frm_pwr: Self gen from power @@ -151,6 +153,7 @@ struct cds_config_info { #endif #ifdef WLAN_FEATURE_NAN bool is_nan_enabled; + bool nan_separate_iface_support; #endif bool apf_packet_filter_enable; bool tx_chain_mask_cck; @@ -172,6 +175,8 @@ struct cds_config_info { bool enable_peer_unmap_conf_support; bool enable_tx_compl_tsf64; bool enable_three_way_coex_config_legacy; + uint32_t num_vdevs; + bool bmiss_skip_full_scan; }; #ifdef WLAN_FEATURE_FILS_SK diff --git a/drivers/staging/qcacld-3.0/core/cds/inc/cds_regdomain.h b/drivers/staging/qcacld-3.0/core/cds/inc/cds_regdomain.h index 50d91f65d5a0..0a4d911231ab 100644 --- a/drivers/staging/qcacld-3.0/core/cds/inc/cds_regdomain.h +++ b/drivers/staging/qcacld-3.0/core/cds/inc/cds_regdomain.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011, 2014-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2011, 2014-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -65,7 +65,7 @@ #include #define MIN_TX_PWR_CAP 8 -#define MAX_TX_PWR_CAP 30 +#define MAX_TX_PWR_CAP 24 #define CTRY_DEFAULT 0 #define CTRY_FLAG 0x8000 diff --git a/drivers/staging/qcacld-3.0/core/cds/inc/cds_sched.h b/drivers/staging/qcacld-3.0/core/cds/inc/cds_sched.h index 3d498a7230aa..eaddcad1fc74 100644 --- a/drivers/staging/qcacld-3.0/core/cds/inc/cds_sched.h +++ b/drivers/staging/qcacld-3.0/core/cds/inc/cds_sched.h @@ -148,6 +148,10 @@ typedef struct _cds_sched_context { /* high throughput required */ bool high_throughput_required; + + /* affinity requied during uplink traffic*/ + bool rx_affinity_required; + uint8_t conf_rx_thread_ul_cpu_mask; #endif } cds_sched_context, *p_cds_sched_context; @@ -235,6 +239,25 @@ struct cds_context { int cds_sched_handle_cpu_hot_plug(void); int cds_sched_handle_throughput_req(bool high_tput_required); +/** + * cds_sched_handle_rx_thread_affinity_req - rx thread affinity req handler + * @high_tput_required: high throughput is required or not + * + * rx thread affinity handler will find online cores and + * will assign proper core based on perf requirement + * + * Return: None + */ +void cds_sched_handle_rx_thread_affinity_req(bool high_throughput); + +/** + * cds_set_rx_thread_ul_cpu_mask() - Rx_thread affinity for UL from INI + * @cpu_affinity_mask: CPU affinity bitmap + * + * Return:None + */ +void cds_set_rx_thread_ul_cpu_mask(uint8_t cpu_affinity_mask); + /** * cds_set_rx_thread_cpu_mask() - Rx_thread affinity from INI * @cpu_affinity_mask: CPU affinity bitmap @@ -312,6 +335,12 @@ void cds_free_ol_rx_pkt(p_cds_sched_context pSchedContext, -------------------------------------------------------------------------*/ void cds_free_ol_rx_pkt_freeq(p_cds_sched_context pSchedContext); #else +static inline void +cds_set_rx_thread_ul_cpu_mask(uint8_t cpu_affinity_mask) {} + +static inline void +cds_sched_handle_rx_thread_affinity_req(bool high_throughput) {} + /** * cds_drop_rxpkt_by_staid() - api to drop pending rx packets for a sta * @pSchedContext: Pointer to the global CDS Sched Context diff --git a/drivers/staging/qcacld-3.0/core/cds/src/cds_api.c b/drivers/staging/qcacld-3.0/core/cds/src/cds_api.c index 40df8dc8097b..4c037a32f1e6 100644 --- a/drivers/staging/qcacld-3.0/core/cds/src/cds_api.c +++ b/drivers/staging/qcacld-3.0/core/cds/src/cds_api.c @@ -345,7 +345,7 @@ static void cds_cdp_cfg_attach(struct cds_config_info *cds_cfg) gp_cds_context->cfg_ctx = cdp_cfg_attach(soc, gp_cds_context->qdf_ctx, (void *)(&cdp_cfg)); if (!gp_cds_context->cfg_ctx) { - WMA_LOGP("%s: failed to init cfg handle", __func__); + WMA_LOGD("%s: failed to init cfg handle", __func__); return; } @@ -1055,7 +1055,7 @@ QDF_STATUS cds_post_disable(void) * - Clean up CE tasklets. */ - cds_info("send deinit sequence to firmware"); + cds_debug("send deinit sequence to firmware"); if (!(cds_is_driver_recovering() || cds_is_driver_in_bad_state())) cds_suspend_target(wma_handle); hif_disable_isr(hif_ctx); @@ -1646,6 +1646,9 @@ QDF_STATUS cds_get_vdev_types(enum QDF_OPMODE mode, uint32_t *type, case QDF_NDI_MODE: *type = WMI_VDEV_TYPE_NDI; break; + case QDF_NAN_DISC_MODE: + *type = WMI_VDEV_TYPE_NAN; + break; default: cds_err("Invalid device mode %d", mode); status = QDF_STATUS_E_INVAL; @@ -1693,6 +1696,24 @@ bool cds_is_packet_log_enabled(void) } return hdd_ctx->config->enablePacketLog; } + +/** + * cds_get_packet_log_buffer_size() - get packet log buffer size + * + * Return: packet log buffer size in MB + */ +uint8_t cds_get_packet_log_buffer_size(void) +{ + struct hdd_context *hdd_ctx; + + hdd_ctx = gp_cds_context->hdd_context; + if ((NULL == hdd_ctx) || (NULL == hdd_ctx->config)) { + cds_alert("Hdd Context is Null"); + return 0; + } + return hdd_ctx->config->pktlog_buf_size; +} + #endif static int cds_force_assert_target_via_pld(qdf_device_t qdf) @@ -2360,7 +2381,7 @@ QDF_STATUS cds_flush_logs(uint32_t is_fatal, is_fatal, indicator, reason_code); if (dump_mac_trace) - qdf_trace_dump_all(p_cds_context->mac_context, 0, 0, 500, 0); + qdf_trace_dump_all(p_cds_context->mac_context, 0, 0, 100, 0); if (WLAN_LOG_INDICATOR_HOST_ONLY == indicator) { cds_wlan_flush_host_logs_for_fatal(); diff --git a/drivers/staging/qcacld-3.0/core/cds/src/cds_regdomain.c b/drivers/staging/qcacld-3.0/core/cds/src/cds_regdomain.c index 1bb50a86128a..f8f55d2a4c8c 100644 --- a/drivers/staging/qcacld-3.0/core/cds/src/cds_regdomain.c +++ b/drivers/staging/qcacld-3.0/core/cds/src/cds_regdomain.c @@ -158,7 +158,7 @@ static const struct country_code_to_reg_dmn g_all_countries[] = { {CTRY_CENTRAL_AFRICA_REPUBLIC, FCC3_WORLD, "CF", "AFRICA REPUBLIC"}, {CTRY_CHAD, ETSI1_WORLD, "TD", "CHAD"}, {CTRY_CHILE, APL23_WORLD, "CL", "CHILE"}, - {CTRY_CHINA, MKK5_MKKA2, "CN", "CHINA"}, + {CTRY_CHINA, APL14_WORLD, "CN", "CHINA"}, {CTRY_CHRISTMAS_ISLAND, FCC3_WORLD, "CX", "CHRISTMAS ISLAND"}, {CTRY_COLOMBIA, FCC3_WORLD, "CO", "COLOMBIA"}, {CTRY_COSTA_RICA, FCC3_WORLD, "CR", "COSTA RICA"}, diff --git a/drivers/staging/qcacld-3.0/core/cds/src/cds_sched.c b/drivers/staging/qcacld-3.0/core/cds/src/cds_sched.c index 62fca2ef8173..99f89c4621f8 100644 --- a/drivers/staging/qcacld-3.0/core/cds/src/cds_sched.c +++ b/drivers/staging/qcacld-3.0/core/cds/src/cds_sched.c @@ -111,6 +111,17 @@ void cds_set_rx_thread_cpu_mask(uint8_t cpu_affinity_mask) sched_context->conf_rx_thread_cpu_mask = cpu_affinity_mask; } +void cds_set_rx_thread_ul_cpu_mask(uint8_t cpu_affinity_mask) +{ + p_cds_sched_context sched_context = get_cds_sched_ctxt(); + + if (!sched_context) { + qdf_err("invalid context"); + return; + } + sched_context->conf_rx_thread_ul_cpu_mask = cpu_affinity_mask; +} + #if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 0)) /** * cds_rx_thread_log_cpu_affinity_change - Log Rx thread affinity change @@ -247,6 +258,63 @@ int cds_sched_handle_cpu_hot_plug(void) return 0; } +void cds_sched_handle_rx_thread_affinity_req(bool high_throughput) +{ + p_cds_sched_context pschedcontext = get_cds_sched_ctxt(); + unsigned long cpus; + struct cpumask new_mask; + unsigned char core_affine_count = 0; + + if (!pschedcontext || !pschedcontext->ol_rx_thread) + return; + + if (cds_is_load_or_unload_in_progress()) { + cds_err("load or unload in progress"); + return; + } + + if (pschedcontext->rx_affinity_required == high_throughput) + return; + + pschedcontext->rx_affinity_required = high_throughput; + cpumask_clear(&new_mask); + + if (!high_throughput) { + /* Attach to all cores, let scheduler decide */ + cpumask_setall(&new_mask); + goto affine_thread; + } + for_each_online_cpu(cpus) { + if (topology_physical_package_id(cpus) > + CDS_MAX_CPU_CLUSTERS) { + cds_err("can handle max %d clusters ", + CDS_MAX_CPU_CLUSTERS); + return; + } + if (pschedcontext->conf_rx_thread_ul_cpu_mask && + (pschedcontext->conf_rx_thread_ul_cpu_mask & + (1 << cpus))) + cpumask_set_cpu(cpus, &new_mask); + + core_affine_count++; + } + +affine_thread: + + cds_rx_thread_log_cpu_affinity_change( + core_affine_count, + (int)pschedcontext->rx_affinity_required, + &pschedcontext->rx_thread_cpu_mask, + &new_mask); + + mutex_lock(&pschedcontext->affinity_lock); + if (!cpumask_equal(&pschedcontext->rx_thread_cpu_mask, &new_mask)) { + cpumask_copy(&pschedcontext->rx_thread_cpu_mask, &new_mask); + set_cpus_allowed_ptr(pschedcontext->ol_rx_thread, &new_mask); + } + mutex_unlock(&pschedcontext->affinity_lock); +} + /** * cds_sched_handle_throughput_req - cpu throughput requirement handler * @high_tput_required: high throughput is required or not @@ -444,6 +512,7 @@ QDF_STATUS cds_sched_open(void *p_cds_context, cds_cpu_before_offline_cb); mutex_init(&pSchedContext->affinity_lock); pSchedContext->high_throughput_required = false; + pSchedContext->rx_affinity_required = false; #endif gp_cds_sched_context = pSchedContext; @@ -756,7 +825,7 @@ static int cds_ol_rx_thread(void *arg) complete (&pSchedContext->ol_suspend_rx_event); } - cds_info("Shutting down OL RX Thread"); + cds_debug("Shutting down OL RX Thread"); shutdown = true; break; } diff --git a/drivers/staging/qcacld-3.0/core/cds/src/cds_utils.c b/drivers/staging/qcacld-3.0/core/cds/src/cds_utils.c index 2de74afa8aaa..9d7090209f1f 100644 --- a/drivers/staging/qcacld-3.0/core/cds/src/cds_utils.c +++ b/drivers/staging/qcacld-3.0/core/cds/src/cds_utils.c @@ -735,6 +735,15 @@ void cds_copy_hlp_info(struct qdf_mac_addr *input_dst_mac, return; } + if (!input_dst_mac) { + cds_debug("HLP destination mac NULL"); + return; + } + + if (!input_src_mac) { + cds_debug("HLP source mac NULL"); + return; + } qdf_copy_macaddr(output_dst_mac, input_dst_mac); qdf_copy_macaddr(output_src_mac, input_src_mac); *output_hlp_data_len = input_hlp_data_len; diff --git a/drivers/staging/qcacld-3.0/core/dp/htt/htt_h2t.c b/drivers/staging/qcacld-3.0/core/dp/htt/htt_h2t.c index 0464e3e5ef7c..b2ca2424951a 100644 --- a/drivers/staging/qcacld-3.0/core/dp/htt/htt_h2t.c +++ b/drivers/staging/qcacld-3.0/core/dp/htt/htt_h2t.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -57,8 +57,13 @@ #ifdef ATH_11AC_TXCOMPACT #define HTT_SEND_HTC_PKT(pdev, pkt) \ do { \ - if (htc_send_pkt(pdev->htc_pdev, &pkt->htc_pkt) == QDF_STATUS_SUCCESS) \ + if (htc_send_pkt(pdev->htc_pdev, &pkt->htc_pkt) == \ + QDF_STATUS_SUCCESS) { \ htt_htc_misc_pkt_list_add(pdev, pkt); \ + } else { \ + qdf_nbuf_free((qdf_nbuf_t)(pkt->htc_pkt.pNetBufContext)); \ + htt_htc_pkt_free(pdev, pkt); \ + } \ } while (0) #else #define HTT_SEND_HTC_PKT(pdev, ppkt) \ @@ -200,8 +205,12 @@ QDF_STATUS htt_h2t_frag_desc_bank_cfg_msg(struct htt_pdev_t *pdev) rc = htc_send_pkt(pdev->htc_pdev, &pkt->htc_pkt); #ifdef ATH_11AC_TXCOMPACT - if (rc == QDF_STATUS_SUCCESS) + if (rc == QDF_STATUS_SUCCESS) { htt_htc_misc_pkt_list_add(pdev, pkt); + } else { + qdf_nbuf_free(msg); + htt_htc_pkt_free(pdev, pkt); + } #endif return rc; @@ -729,8 +738,12 @@ htt_h2t_rx_ring_cfg_msg_hl(struct htt_pdev_t *pdev) SET_HTC_PACKET_NET_BUF_CONTEXT(&pkt->htc_pkt, msg); #ifdef ATH_11AC_TXCOMPACT - if (htc_send_pkt(pdev->htc_pdev, &pkt->htc_pkt) == QDF_STATUS_SUCCESS) + if (htc_send_pkt(pdev->htc_pdev, &pkt->htc_pkt) == QDF_STATUS_SUCCESS) { htt_htc_misc_pkt_list_add(pdev, pkt); + } else { + qdf_nbuf_free(msg); + htt_htc_pkt_free(pdev, pkt); + } #else htc_send_pkt(pdev->htc_pdev, &pkt->htc_pkt); #endif @@ -840,8 +853,12 @@ htt_h2t_dbg_stats_get(struct htt_pdev_t *pdev, SET_HTC_PACKET_NET_BUF_CONTEXT(&pkt->htc_pkt, msg); #ifdef ATH_11AC_TXCOMPACT - if (htc_send_pkt(pdev->htc_pdev, &pkt->htc_pkt) == QDF_STATUS_SUCCESS) + if (htc_send_pkt(pdev->htc_pdev, &pkt->htc_pkt) == QDF_STATUS_SUCCESS) { htt_htc_misc_pkt_list_add(pdev, pkt); + } else { + qdf_nbuf_free(msg); + htt_htc_pkt_free(pdev, pkt); + } #else htc_send_pkt(pdev->htc_pdev, &pkt->htc_pkt); #endif @@ -965,8 +982,12 @@ htt_h2t_aggr_cfg_msg(struct htt_pdev_t *pdev, SET_HTC_PACKET_NET_BUF_CONTEXT(&pkt->htc_pkt, msg); #ifdef ATH_11AC_TXCOMPACT - if (htc_send_pkt(pdev->htc_pdev, &pkt->htc_pkt) == QDF_STATUS_SUCCESS) + if (htc_send_pkt(pdev->htc_pdev, &pkt->htc_pkt) == QDF_STATUS_SUCCESS) { htt_htc_misc_pkt_list_add(pdev, pkt); + } else { + qdf_nbuf_free(msg); + htt_htc_pkt_free(pdev, pkt); + } #else htc_send_pkt(pdev->htc_pdev, &pkt->htc_pkt); #endif diff --git a/drivers/staging/qcacld-3.0/core/dp/htt/htt_internal.h b/drivers/staging/qcacld-3.0/core/dp/htt/htt_internal.h index 972946430d92..fd54f2d2aa6a 100644 --- a/drivers/staging/qcacld-3.0/core/dp/htt/htt_internal.h +++ b/drivers/staging/qcacld-3.0/core/dp/htt/htt_internal.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011, 2014-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2011, 2014-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -160,7 +160,7 @@ struct htt_host_rx_desc_base { * @posted: time-stamp when HTT message is recived * @recvd : 0x48545452584D5367 ('HTTRXMSG') */ -#define HTT_RX_RING_BUFF_DBG_LIST (2 * 1024) +#define HTT_RX_RING_BUFF_DBG_LIST (8 * 1024) struct rx_buf_debug { qdf_dma_addr_t paddr; qdf_nbuf_t nbuf; @@ -1028,6 +1028,19 @@ int htt_rx_mon_amsdu_rx_in_order_pop_ll(htt_pdev_handle pdev, qdf_nbuf_t *head_msdu, qdf_nbuf_t *tail_msdu, uint32_t *replenish_cnt); + +/** + * htt_rx_mon_get_rx_status() - Update information about the rx status, + * which is used later for radiotap updation. + * @pdev: Pointer to pdev handle + * @rx_desc: Pointer to struct htt_host_rx_desc_base + * @rx_status: Return variable updated with rx_status + * + * Return: None + */ +void htt_rx_mon_get_rx_status(htt_pdev_handle pdev, + struct htt_host_rx_desc_base *rx_desc, + struct mon_rx_status *rx_status); #else static inline int htt_rx_mon_amsdu_rx_in_order_pop_ll(htt_pdev_handle pdev, @@ -1038,6 +1051,13 @@ int htt_rx_mon_amsdu_rx_in_order_pop_ll(htt_pdev_handle pdev, { return 0; } + +static inline +void htt_rx_mon_get_rx_status(htt_pdev_handle pdev, + struct htt_host_rx_desc_base *rx_desc, + struct mon_rx_status *rx_status) +{ +} #endif #endif diff --git a/drivers/staging/qcacld-3.0/core/dp/htt/htt_monitor_rx.c b/drivers/staging/qcacld-3.0/core/dp/htt/htt_monitor_rx.c index 25607641d775..75225472f951 100644 --- a/drivers/staging/qcacld-3.0/core/dp/htt/htt_monitor_rx.c +++ b/drivers/staging/qcacld-3.0/core/dp/htt/htt_monitor_rx.c @@ -464,17 +464,9 @@ static uint8_t htt_mon_rx_get_rtap_flags(struct htt_host_rx_desc_base *rx_desc) return rtap_flags; } -/** - * htt_rx_mon_get_rx_status() - Update information about the rx status, - * which is used later for radiotap updation. - * @rx_desc: Pointer to struct htt_host_rx_desc_base - * @rx_status: Return variable updated with rx_status - * - * Return: None - */ -static void htt_rx_mon_get_rx_status(htt_pdev_handle pdev, - struct htt_host_rx_desc_base *rx_desc, - struct mon_rx_status *rx_status) +void htt_rx_mon_get_rx_status(htt_pdev_handle pdev, + struct htt_host_rx_desc_base *rx_desc, + struct mon_rx_status *rx_status) { uint16_t channel_flags = 0; struct mon_channel *ch_info = &pdev->mon_ch_info; @@ -492,6 +484,7 @@ static void htt_rx_mon_get_rx_status(htt_pdev_handle pdev, rx_status->chan_flags = channel_flags; rx_status->ant_signal_db = rx_desc->ppdu_start.rssi_comb; + rx_status->rssi_comb = rx_desc->ppdu_start.rssi_comb; } /** diff --git a/drivers/staging/qcacld-3.0/core/dp/htt/htt_rx.c b/drivers/staging/qcacld-3.0/core/dp/htt/htt_rx.c index 47c82b881d21..22291f0418b7 100644 --- a/drivers/staging/qcacld-3.0/core/dp/htt/htt_rx.c +++ b/drivers/staging/qcacld-3.0/core/dp/htt/htt_rx.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -3095,7 +3095,7 @@ static int htt_rx_ipa_uc_alloc_wdi2_rsc(struct htt_pdev_t *pdev, pdev->ipa_uc_rx_rsc.rx2_ind_ring = qdf_mem_shared_mem_alloc(pdev->osdev, rx_ind_ring_elements * - sizeof(qdf_dma_addr_t)); + sizeof(target_paddr_t)); if (!pdev->ipa_uc_rx_rsc.rx2_ind_ring) { QDF_TRACE(QDF_MODULE_ID_HTT, QDF_TRACE_LEVEL_ERROR, "%s: Unable to allocate memory for IPA rx2 ind ring", diff --git a/drivers/staging/qcacld-3.0/core/dp/htt/htt_t2h.c b/drivers/staging/qcacld-3.0/core/dp/htt/htt_t2h.c index 91a97bd6fd04..031e05b7952c 100644 --- a/drivers/staging/qcacld-3.0/core/dp/htt/htt_t2h.c +++ b/drivers/staging/qcacld-3.0/core/dp/htt/htt_t2h.c @@ -43,6 +43,8 @@ #include #include "pktlog_ac.h" #include +#include +#include /*--- target->host HTT message dispatch function ----------------------------*/ #ifndef DEBUG_CREDIT @@ -1194,6 +1196,71 @@ void htt_t2h_msg_handler_fast(void *context, qdf_nbuf_t *cmpl_msdus, break; } + case HTT_T2H_MSG_TYPE_TX_OFFLOAD_DELIVER_IND: + { + struct htt_tx_offload_deliver_ind_hdr_t + *offload_deliver_msg; + uint8_t vdev_id; + struct ol_txrx_vdev_t *vdev; + bool is_pkt_during_roam = false; + struct ol_txrx_pdev_t *txrx_pdev = pdev->txrx_pdev; + struct ol_txrx_peer_t *peer; + uint8_t bssid[QDF_MAC_ADDR_SIZE]; + uint32_t freq = 0; + + if (!(ucfg_pkt_capture_get_pktcap_mode() & + PKT_CAPTURE_MODE_DATA_ONLY)) + break; + + offload_deliver_msg = + (struct htt_tx_offload_deliver_ind_hdr_t *)msg_word; + is_pkt_during_roam = + (offload_deliver_msg->reserved_2 ? true : false); + + if (qdf_unlikely( + !pdev->cfg.is_full_reorder_offload)) { + break; + } + + /* Is FW sends offload data during roaming */ + if (is_pkt_during_roam) { + vdev_id = HTT_INVALID_VDEV; + freq = + (uint32_t)offload_deliver_msg->reserved_3; + htt_rx_mon_note_capture_channel( + pdev, cds_freq_to_chan(freq)); + } else { + vdev_id = offload_deliver_msg->vdev_id; + vdev = (struct ol_txrx_vdev_t *) + ol_txrx_get_vdev_from_vdev_id(vdev_id); + + if (vdev) { + qdf_spin_lock_bh( + &txrx_pdev->peer_ref_mutex); + peer = TAILQ_FIRST(&vdev->peer_list); + qdf_spin_unlock_bh( + &txrx_pdev->peer_ref_mutex); + if (peer) { + qdf_spin_lock_bh( + &peer->peer_info_lock); + qdf_mem_copy( + bssid, + &peer->mac_addr.raw, + QDF_MAC_ADDR_SIZE); + qdf_spin_unlock_bh( + &peer->peer_info_lock); + } else { + break; + } + } else { + break; + } + } + ucfg_pkt_capture_offload_deliver_indication_handler( + msg_word, + vdev_id, bssid, pdev); + break; + } case HTT_T2H_MSG_TYPE_RX_PN_IND: { u_int16_t peer_id; diff --git a/drivers/staging/qcacld-3.0/core/dp/htt/htt_tx.c b/drivers/staging/qcacld-3.0/core/dp/htt/htt_tx.c index 28ffb4823a2b..e4244c14566e 100644 --- a/drivers/staging/qcacld-3.0/core/dp/htt/htt_tx.c +++ b/drivers/staging/qcacld-3.0/core/dp/htt/htt_tx.c @@ -1,5 +1,6 @@ /* - * Copyright (c) 2011, 2014-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2011, 2014-2018, 2020 The Linux Foundation. + * All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -1063,12 +1064,12 @@ static int htt_tx_ipa_uc_wdi_tx_buf_alloc(struct htt_pdev_t *pdev, unsigned int tx_buffer_count_pwr2; qdf_dma_addr_t buffer_paddr; uint32_t *header_ptr; - qdf_dma_addr_t *ring_vaddr; + target_paddr_t *ring_vaddr; uint16_t idx; qdf_mem_info_t *mem_map_table = NULL, *mem_info = NULL; qdf_shared_mem_t *shared_tx_buffer; - ring_vaddr = (qdf_dma_addr_t *)pdev->ipa_uc_tx_rsc.tx_comp_ring->vaddr; + ring_vaddr = (target_paddr_t *)pdev->ipa_uc_tx_rsc.tx_comp_ring->vaddr; if (qdf_mem_smmu_s1_enabled(pdev->osdev)) { mem_map_table = qdf_mem_map_table_alloc(uc_tx_buf_cnt); if (!mem_map_table) { diff --git a/drivers/staging/qcacld-3.0/core/dp/txrx/ol_rx.c b/drivers/staging/qcacld-3.0/core/dp/txrx/ol_rx.c index cc8abf64fd02..4b65dbbd9609 100644 --- a/drivers/staging/qcacld-3.0/core/dp/txrx/ol_rx.c +++ b/drivers/staging/qcacld-3.0/core/dp/txrx/ol_rx.c @@ -55,6 +55,7 @@ #include #include #include +#include #ifndef OL_RX_INDICATION_MAX_RECORDS #define OL_RX_INDICATION_MAX_RECORDS 2048 @@ -86,7 +87,7 @@ struct ol_rx_ind_record { #ifdef OL_RX_INDICATION_RECORD static uint32_t ol_rx_ind_record_index; -static struct ol_rx_ind_record +struct ol_rx_ind_record ol_rx_indication_record_history[OL_RX_INDICATION_MAX_RECORDS]; /** @@ -1159,8 +1160,8 @@ ol_rx_filter(struct ol_txrx_vdev_t *vdev, #ifdef WLAN_FEATURE_TSF_PLUS #ifdef CONFIG_HL_SUPPORT -static inline void ol_rx_timestamp(struct cdp_cfg *cfg_pdev, - void *rx_desc, qdf_nbuf_t msdu) +void ol_rx_timestamp(struct cdp_cfg *cfg_pdev, + void *rx_desc, qdf_nbuf_t msdu) { struct htt_rx_ppdu_desc_t *rx_ppdu_desc; @@ -1191,8 +1192,8 @@ static inline void ol_rx_timestamp_update(ol_txrx_pdev_handle pdev, } } #else -static inline void ol_rx_timestamp(struct cdp_cfg *cfg_pdev, - void *rx_desc, qdf_nbuf_t msdu) +void ol_rx_timestamp(struct cdp_cfg *cfg_pdev, + void *rx_desc, qdf_nbuf_t msdu) { struct htt_host_rx_desc_base *rx_mpdu_desc = rx_desc; uint32_t tsf64_low32, tsf64_high32; @@ -1264,8 +1265,8 @@ static inline void ol_rx_timestamp_update(ol_txrx_pdev_handle pdev, } #endif #else -static inline void ol_rx_timestamp(struct cdp_cfg *cfg_pdev, - void *rx_desc, qdf_nbuf_t msdu) +void ol_rx_timestamp(struct cdp_cfg *cfg_pdev, + void *rx_desc, qdf_nbuf_t msdu) { } @@ -1556,6 +1557,7 @@ ol_rx_in_order_indication_handler(ol_txrx_pdev_handle pdev, { struct ol_txrx_vdev_t *vdev = NULL; struct ol_txrx_peer_t *peer = NULL; + struct ol_txrx_peer_t *peer_head = NULL; htt_pdev_handle htt_pdev = NULL; int status; qdf_nbuf_t head_msdu = NULL, tail_msdu = NULL; @@ -1564,6 +1566,8 @@ ol_rx_in_order_indication_handler(ol_txrx_pdev_handle pdev, uint32_t msdu_count; uint8_t pktlog_bit; uint32_t filled = 0; + uint8_t bssid[QDF_MAC_ADDR_SIZE] = {0}; + bool offloaded_pkt; if (tid >= OL_TXRX_NUM_EXT_TIDS) { ol_txrx_err("%s: invalid tid, %u\n", __FUNCTION__, tid); @@ -1627,6 +1631,43 @@ ol_rx_in_order_indication_handler(ol_txrx_pdev_handle pdev, /* rx_opt_proc takes a NULL-terminated list of msdu netbufs */ qdf_nbuf_set_next(tail_msdu, NULL); + /* Packet Capture Mode */ + + if ((ucfg_pkt_capture_get_pktcap_mode() & + PKT_CAPTURE_MODE_DATA_ONLY)) { + offloaded_pkt = ucfg_pkt_capture_rx_offloaded_pkt(rx_ind_msg); + if (peer) { + vdev = peer->vdev; + if (peer->vdev) { + qdf_spin_lock_bh(&pdev->peer_ref_mutex); + peer_head = TAILQ_FIRST(&vdev->peer_list); + qdf_spin_unlock_bh(&pdev->peer_ref_mutex); + if (peer_head) { + qdf_spin_lock_bh( + &peer_head->peer_info_lock); + qdf_mem_copy(bssid, + &peer_head->mac_addr.raw, + QDF_MAC_ADDR_SIZE); + qdf_spin_unlock_bh( + &peer_head->peer_info_lock); + + ucfg_pkt_capture_rx_msdu_process( + bssid, head_msdu, + peer->vdev->vdev_id, + htt_pdev); + } + } + } else if (offloaded_pkt) { + ucfg_pkt_capture_rx_msdu_process( + bssid, head_msdu, + HTT_INVALID_VDEV, + htt_pdev); + + ucfg_pkt_capture_rx_drop_offload_pkt(head_msdu); + return; + } + } + /* Pktlog */ ol_rx_send_pktlog_event(pdev, peer, head_msdu, pktlog_bit); diff --git a/drivers/staging/qcacld-3.0/core/dp/txrx/ol_rx.h b/drivers/staging/qcacld-3.0/core/dp/txrx/ol_rx.h index bcc6bab80382..78a06d450587 100644 --- a/drivers/staging/qcacld-3.0/core/dp/txrx/ol_rx.h +++ b/drivers/staging/qcacld-3.0/core/dp/txrx/ol_rx.h @@ -76,4 +76,6 @@ ol_rx_mic_error_handler( void *msdu_desc, qdf_nbuf_t msdu); +void ol_rx_timestamp(struct cdp_cfg *cfg_pdev, void *rx_desc, qdf_nbuf_t msdu); + #endif /* _OL_RX__H_ */ diff --git a/drivers/staging/qcacld-3.0/core/dp/txrx/ol_rx_defrag.c b/drivers/staging/qcacld-3.0/core/dp/txrx/ol_rx_defrag.c index 2e0f81d44bd9..3023375ed896 100644 --- a/drivers/staging/qcacld-3.0/core/dp/txrx/ol_rx_defrag.c +++ b/drivers/staging/qcacld-3.0/core/dp/txrx/ol_rx_defrag.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -58,6 +58,7 @@ #include #include #include /* qdf_system_time */ +#include #define DEFRAG_IEEE80211_ADDR_EQ(a1, a2) \ (!qdf_mem_cmp(a1, a2, IEEE80211_ADDR_LEN)) @@ -306,6 +307,7 @@ ol_rx_frag_indication_handler(ol_txrx_pdev_handle pdev, uint8_t pktlog_bit; uint32_t msdu_count = 0; int ret; + void *rx_desc; if (tid >= OL_TXRX_NUM_EXT_TIDS) { ol_txrx_err("%s: invalid tid, %u\n", __FUNCTION__, tid); @@ -359,6 +361,8 @@ ol_rx_frag_indication_handler(ol_txrx_pdev_handle pdev, OL_RX_ERR_STATISTICS_1(pdev, peer->vdev, peer, rx_mpdu_desc, OL_RX_ERR_NONE_FRAG); ol_rx_send_pktlog_event(pdev, peer, head_msdu, pktlog_bit); + rx_desc = htt_rx_msdu_desc_retrieve(pdev->htt_pdev, head_msdu); + ol_rx_timestamp(pdev->ctrl_pdev, rx_desc, head_msdu); ol_rx_reorder_store_frag(pdev, peer, tid, seq_num, head_msdu); } else { /* invalid frame - discard it */ @@ -650,7 +654,8 @@ ol_rx_defrag(ol_txrx_pdev_handle pdev, struct ieee80211_frame *wh; uint8_t key[DEFRAG_IEEE80211_KEY_LEN]; htt_pdev_handle htt_pdev = pdev->htt_pdev; - + struct ol_txrx_peer_t *peer_head = NULL; + uint8_t bssid[QDF_MAC_ADDR_SIZE]; vdev = peer->vdev; /* bypass defrag for safe mode */ @@ -767,6 +772,33 @@ ol_rx_defrag(ol_txrx_pdev_handle pdev, if (ol_cfg_frame_type(pdev->ctrl_pdev) == wlan_frm_fmt_802_3) ol_rx_defrag_nwifi_to_8023(pdev, msdu); + /* Packet Capture Mode */ + + if ((ucfg_pkt_capture_get_pktcap_mode() & + PKT_CAPTURE_MODE_DATA_ONLY)) { + if (peer) { + if (peer->vdev) { + qdf_spin_lock_bh(&pdev->peer_ref_mutex); + peer_head = TAILQ_FIRST(&vdev->peer_list); + qdf_spin_unlock_bh(&pdev->peer_ref_mutex); + if (peer_head) { + qdf_spin_lock_bh( + &peer_head->peer_info_lock); + qdf_mem_copy(bssid, + &peer_head->mac_addr.raw, + QDF_MAC_ADDR_SIZE); + qdf_spin_unlock_bh( + &peer_head->peer_info_lock); + + ucfg_pkt_capture_rx_msdu_process( + bssid, msdu, + vdev->vdev_id, + htt_pdev); + } + } + } + } + ol_rx_fwd_check(vdev, peer, tid, msdu); } diff --git a/drivers/staging/qcacld-3.0/core/dp/txrx/ol_tx_send.c b/drivers/staging/qcacld-3.0/core/dp/txrx/ol_tx_send.c index 46558e14661f..589b9a45273c 100644 --- a/drivers/staging/qcacld-3.0/core/dp/txrx/ol_tx_send.c +++ b/drivers/staging/qcacld-3.0/core/dp/txrx/ol_tx_send.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -53,7 +53,7 @@ #include #include #include - +#include #ifdef TX_CREDIT_RECLAIM_SUPPORT #define OL_TX_CREDIT_RECLAIM(pdev) \ @@ -614,6 +614,151 @@ void ol_tx_flow_pool_unlock(struct ol_tx_desc_t *tx_desc) } #endif +#ifdef WLAN_FEATURE_PKT_CAPTURE +#define RESERVE_BYTES 100 +/** + * ol_tx_pkt_capture_tx_completion_process(): process tx packets + * for pkt capture mode + * @pdev: device handler + * @tx_desc: tx desc + * @payload: tx data header + * @tid: tid number + * @status: Tx status + * + * Return: none + */ +static void +ol_tx_pkt_capture_tx_completion_process( + ol_txrx_pdev_handle pdev, + struct ol_tx_desc_t *tx_desc, + struct htt_tx_data_hdr_information *payload_hdr, + uint8_t tid, uint8_t status) +{ + qdf_nbuf_t netbuf; + int nbuf_len; + struct qdf_tso_seg_elem_t *tso_seg = NULL; + struct ol_txrx_peer_t *peer; + uint8_t bssid[QDF_MAC_ADDR_SIZE]; + uint8_t pkt_type = 0; + + qdf_assert(tx_desc); + + ol_tx_flow_pool_lock(tx_desc); + /* + * In cases when vdev has gone down and tx completion + * are received, leads to NULL vdev access. + * So, check for NULL before dereferencing it. + */ + if (!tx_desc->vdev) { + ol_tx_flow_pool_unlock(tx_desc); + return; + } + + ol_tx_flow_pool_unlock(tx_desc); + + if (tx_desc->pkt_type == OL_TX_FRM_TSO) { + if (!tx_desc->tso_desc) + return; + + tso_seg = tx_desc->tso_desc; + nbuf_len = tso_seg->seg.total_len; + } else { + int i, extra_frag_len = 0; + + i = QDF_NBUF_CB_TX_NUM_EXTRA_FRAGS(tx_desc->netbuf); + if (i > 0) + extra_frag_len = + QDF_NBUF_CB_TX_EXTRA_FRAG_LEN(tx_desc->netbuf); + nbuf_len = qdf_nbuf_len(tx_desc->netbuf) - extra_frag_len; + } + + qdf_spin_lock_bh(&pdev->peer_ref_mutex); + peer = TAILQ_FIRST(&tx_desc->vdev->peer_list); + qdf_spin_unlock_bh(&pdev->peer_ref_mutex); + if (!peer) + return; + + qdf_spin_lock_bh(&peer->peer_info_lock); + qdf_mem_copy(bssid, &peer->mac_addr.raw, QDF_MAC_ADDR_SIZE); + qdf_spin_unlock_bh(&peer->peer_info_lock); + + netbuf = qdf_nbuf_alloc(NULL, + roundup(nbuf_len + RESERVE_BYTES, 4), + RESERVE_BYTES, 4, false); + if (!netbuf) + return; + + qdf_nbuf_put_tail(netbuf, nbuf_len); + + if (tx_desc->pkt_type == OL_TX_FRM_TSO) { + uint8_t frag_cnt, num_frags = 0; + int frag_len = 0; + uint32_t tcp_seq_num; + uint16_t ip_len; + + qdf_spin_lock_bh(&pdev->tso_seg_pool.tso_mutex); + + if (tso_seg->seg.num_frags > 0) + num_frags = tso_seg->seg.num_frags - 1; + + /*Num of frags in a tso seg cannot be less than 2 */ + if (num_frags < 1) { + qdf_print("ERROR: num of frags in tso segment is %d\n", + (num_frags + 1)); + qdf_nbuf_free(netbuf); + qdf_spin_unlock_bh(&pdev->tso_seg_pool.tso_mutex); + return; + } + + tcp_seq_num = tso_seg->seg.tso_flags.tcp_seq_num; + tcp_seq_num = qdf_cpu_to_be32(tcp_seq_num); + + ip_len = tso_seg->seg.tso_flags.ip_len; + ip_len = qdf_cpu_to_be16(ip_len); + + for (frag_cnt = 0; frag_cnt < num_frags; frag_cnt++) { + qdf_mem_copy(qdf_nbuf_data(netbuf) + frag_len, + tso_seg->seg.tso_frags[frag_cnt].vaddr, + tso_seg->seg.tso_frags[frag_cnt].length); + frag_len += tso_seg->seg.tso_frags[frag_cnt].length; + } + + qdf_spin_unlock_bh(&pdev->tso_seg_pool.tso_mutex); + + qdf_mem_copy((qdf_nbuf_data(netbuf) + IPV4_PKT_LEN_OFFSET), + &ip_len, sizeof(ip_len)); + qdf_mem_copy((qdf_nbuf_data(netbuf) + IPV4_TCP_SEQ_NUM_OFFSET), + &tcp_seq_num, sizeof(tcp_seq_num)); + } else { + qdf_mem_copy(qdf_nbuf_data(netbuf), + qdf_nbuf_data(tx_desc->netbuf), + nbuf_len); + } + + qdf_nbuf_push_head( + netbuf, + sizeof(struct htt_tx_data_hdr_information)); + qdf_mem_copy(qdf_nbuf_data(netbuf), payload_hdr, + sizeof(struct htt_tx_data_hdr_information)); + + ucfg_pkt_capture_tx_completion_process( + tx_desc->vdev_id, + netbuf, pkt_type, + tid, status, + TXRX_PKTCAPTURE_PKT_FORMAT_8023, bssid, + pdev->htt_pdev, payload_hdr->tx_retry_cnt); +} +#else +static void +ol_tx_pkt_capture_tx_completion_process( + ol_txrx_pdev_handle pdev, + struct ol_tx_desc_t *tx_desc, + struct htt_tx_data_hdr_information *payload_hdr, + uint8_t tid, uint8_t status) +{ +} +#endif /* WLAN_FEATURE_PKT_CAPTURE */ + #ifdef WLAN_FEATURE_TSF_PLUS static inline struct htt_tx_compl_ind_append_tx_tstamp *ol_tx_get_txtstamps( u_int32_t *msg_word_header, u_int32_t **msg_word_payload, @@ -866,6 +1011,7 @@ ol_tx_completion_handler(ol_txrx_pdev_handle pdev, uint32_t is_tx_desc_freed = 0; struct htt_tx_compl_ind_append_tx_tstamp *txtstamp_list = NULL; struct htt_tx_compl_ind_append_tx_tsf64 *txtstamp64_list = NULL; + struct htt_tx_data_hdr_information *pkt_capture_txcomp_hdr_list = NULL; u_int32_t *msg_word_header = (u_int32_t *)msg; /*msg_word skip header*/ u_int32_t *msg_word_payload = msg_word_header + 1; @@ -875,9 +1021,12 @@ ol_tx_completion_handler(ol_txrx_pdev_handle pdev, union ol_tx_desc_list_elem_t *tx_desc_last = NULL; ol_tx_desc_list tx_descs; uint64_t tx_tsf64; + uint8_t tid; TAILQ_INIT(&tx_descs); + tid = HTT_TX_COMPL_IND_TID_GET(*msg_word); + ol_tx_delay_compute(pdev, status, desc_ids, num_msdus); if (status == htt_tx_status_ok) { txtstamp_list = ol_tx_get_txtstamps( @@ -887,6 +1036,13 @@ ol_tx_completion_handler(ol_txrx_pdev_handle pdev, msg_word_header, &msg_word_payload, num_msdus); } + if ((ucfg_pkt_capture_get_pktcap_mode() & + PKT_CAPTURE_MODE_DATA_ONLY)) + pkt_capture_txcomp_hdr_list = + ucfg_pkt_capture_tx_get_txcomplete_data_hdr( + msg_word, + num_msdus); + for (i = 0; i < num_msdus; i++) { tx_desc_id = desc_ids[i]; if (tx_desc_id >= pdev->tx_desc.pool_size) { @@ -912,6 +1068,14 @@ ol_tx_completion_handler(ol_txrx_pdev_handle pdev, (u_int64_t)txtstamp_list->timestamp[i] ); + if (pkt_capture_txcomp_hdr_list) { + ol_tx_pkt_capture_tx_completion_process( + pdev, + tx_desc, + &pkt_capture_txcomp_hdr_list[i], + tid, status); + } + QDF_NBUF_UPDATE_TX_PKT_COUNT(netbuf, QDF_NBUF_TX_PKT_FREE); if (QDF_NBUF_CB_GET_PACKET_TYPE(netbuf) == diff --git a/drivers/staging/qcacld-3.0/core/dp/txrx/ol_txrx.c b/drivers/staging/qcacld-3.0/core/dp/txrx/ol_txrx.c index c5233556ea23..70323718ee4a 100644 --- a/drivers/staging/qcacld-3.0/core/dp/txrx/ol_txrx.c +++ b/drivers/staging/qcacld-3.0/core/dp/txrx/ol_txrx.c @@ -2306,6 +2306,8 @@ static void ol_txrx_pdev_pre_detach(struct cdp_pdev *ppdev, int force) OL_RX_REORDER_TRACE_DETACH(pdev); OL_RX_PN_TRACE_DETACH(pdev); + htt_pktlogmod_exit(pdev); + /* * WDI event detach */ @@ -2347,8 +2349,6 @@ static void ol_txrx_pdev_detach(struct cdp_pdev *ppdev, int force) return; } - htt_pktlogmod_exit(pdev); - qdf_spin_lock_bh(&pdev->req_list_spinlock); if (pdev->req_list_depth > 0) ol_txrx_err( @@ -3866,9 +3866,8 @@ int ol_txrx_peer_release_ref(ol_txrx_peer_handle peer, debug_id, qdf_atomic_read(&peer->access_list[debug_id]), peer, rc, - qdf_atomic_read(&peer->fw_create_pending) - == 1 ? - "(No Maps received)" : ""); + qdf_atomic_read(&peer->fw_create_pending) == + 1 ? "(No Maps received)" : ""); ol_txrx_peer_tx_queue_free(pdev, peer); @@ -3892,9 +3891,7 @@ int ol_txrx_peer_release_ref(ol_txrx_peer_handle peer, qdf_spin_unlock_bh(&pdev->peer_ref_mutex); if (!ref_silent) ol_txrx_info_high("[%d][%d]: ref delete peer %pK ref_cnt -> %d", - debug_id, - access_list, - peer, rc); + debug_id, access_list, peer, rc); } return rc; ERR_STATE: @@ -6668,6 +6665,35 @@ static struct cdp_raw_ops ol_ops_raw = { /* EMPTY FOR MCL */ }; +#ifdef WLAN_FEATURE_PKT_CAPTURE +/** + * ol_txrx_pktcapture_record_channel() - Update Channel Information + * for packet capture mode + * @soc: pointer to cdp_soc_t + * @pdev_id: pdev id + * @mon_ch: channel + * + * Return: None + */ +static void +ol_txrx_pktcapture_record_channel(struct cdp_soc_t *soc, + uint8_t pdev_id, int mon_ch) +{ + struct ol_txrx_pdev_t *pdev = cds_get_context(QDF_MODULE_ID_TXRX); + + if (!pdev) { + qdf_print("%s: pdev is NULL\n", __func__); + return; + } + + htt_rx_mon_note_capture_channel(pdev->htt_pdev, mon_ch); +} + +static struct cdp_pktcapture_ops ol_ops_pkt_capture = { + .txrx_pktcapture_record_channel = ol_txrx_pktcapture_record_channel, +}; +#endif /* #ifdef WLAN_FEATURE_PKT_CAPTURE */ + static struct cdp_ops ol_txrx_ops = { .cmn_drv_ops = &ol_ops_cmn, .ctrl_ops = &ol_ops_ctrl, @@ -6692,7 +6718,10 @@ static struct cdp_ops ol_txrx_ops = { .throttle_ops = &ol_ops_throttle, .mob_stats_ops = &ol_ops_mob_stats, .delay_ops = &ol_ops_delay, - .pmf_ops = &ol_ops_pmf + .pmf_ops = &ol_ops_pmf, +#ifdef WLAN_FEATURE_PKT_CAPTURE + .pktcapture_ops = &ol_ops_pkt_capture, +#endif }; /* diff --git a/drivers/staging/qcacld-3.0/core/dp/txrx/ol_txrx_flow_control.c b/drivers/staging/qcacld-3.0/core/dp/txrx/ol_txrx_flow_control.c index d72ed8eb8259..316dd3b2f3c2 100644 --- a/drivers/staging/qcacld-3.0/core/dp/txrx/ol_txrx_flow_control.c +++ b/drivers/staging/qcacld-3.0/core/dp/txrx/ol_txrx_flow_control.c @@ -681,9 +681,7 @@ static void ol_tx_flow_pool_vdev_unmap(struct ol_tx_flow_pool_t *pool, vdev = (struct ol_txrx_vdev_t *)ol_txrx_get_vdev_from_vdev_id(vdev_id); if (!vdev) { - ol_txrx_err( - "%s: invalid vdev_id %d\n", - __func__, vdev_id); + ol_txrx_dbg("invalid vdev_id %d", vdev_id); return; } diff --git a/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_cfg.h b/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_cfg.h index 8689b9224bb4..243973cd68b4 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_cfg.h +++ b/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -90,6 +90,44 @@ struct hdd_context; #define CFG_ENABLE_CONNECTED_SCAN_MAX (1) #define CFG_ENABLE_CONNECTED_SCAN_DEFAULT (1) +/* + * + * mws_coex_pcc_channel_avoid_delay - configures the duration, when WWAN PCC + * (Primary Component Carrier) conflicts with WLAN channel. + * @Min: 0x00 + * @Max: 0xFF + * @Default: 0x3C + * + * It is used to set MWS-COEX WWAN PCC channel avoidance delay + * + * Usage: External + * + * + */ +#define CFG_MWS_COEX_PCC_CHANNEL_AVOID_DELAY "mws_coex_pcc_channel_avoid_delay" +#define CFG_MWS_COEX_PCC_CHANNEL_AVOID_DELAY_DEFAULT (0x3C) +#define CFG_MWS_COEX_PCC_CHANNEL_AVOID_DELAY_MAX (0xFF) +#define CFG_MWS_COEX_PCC_CHANNEL_AVOID_DELAY_MIN (0) + +/* + * + * mws_coex_scc_channel_avoid_delay - configures the duration, when WWAN SCC + * (Secondary Component Carrier) conflicts with WLAN channel. + * @Min: 0x00 + * @Max: 0xFF + * @Default: 0x78 + * + * It is used to set MWS-COEX WWAN SCC channel avoidance delay + * + * Usage: External + * + * + */ +#define CFG_MWS_COEX_SCC_CHANNEL_AVOID_DELAY "mws_coex_scc_channel_avoid_delay" +#define CFG_MWS_COEX_SCC_CHANNEL_AVOID_DELAY_DEFAULT 0x00 +#define CFG_MWS_COEX_SCC_CHANNEL_AVOID_DELAY_MAX 0xFF +#define CFG_MWS_COEX_SCC_CHANNEL_AVOID_DELAY_MIN 0x00 + #ifdef WLAN_NUD_TRACKING /* * @@ -1717,7 +1755,7 @@ enum hdd_dot11_mode { * * RoamRssiDiff - Enable roam based on rssi * @Min: 0 - * @Max: 30 + * @Max: 100 * @Default: 5 * * This INI is used to decide whether to Roam or not based on RSSI. AP1 is the @@ -1736,7 +1774,7 @@ enum hdd_dot11_mode { */ #define CFG_ROAM_RSSI_DIFF_NAME "RoamRssiDiff" #define CFG_ROAM_RSSI_DIFF_MIN (0) -#define CFG_ROAM_RSSI_DIFF_MAX (30) +#define CFG_ROAM_RSSI_DIFF_MAX (100) #define CFG_ROAM_RSSI_DIFF_DEFAULT (5) /* @@ -1903,7 +1941,7 @@ enum hdd_dot11_mode { #define CFG_FORCE_1X1_NAME "gForce1x1Exception" #define CFG_FORCE_1X1_MIN (0) #define CFG_FORCE_1X1_MAX (2) -#define CFG_FORCE_1X1_DEFAULT (2) +#define CFG_FORCE_1X1_DEFAULT (1) /* * @@ -2020,6 +2058,47 @@ enum hdd_dot11_mode { #define CFG_ROAMING_OFFLOAD_MIN (0) #define CFG_ROAMING_OFFLOAD_MAX (1) #define CFG_ROAMING_OFFLOAD_DEFAULT (1) + +/* + * + * roam_triggers - Bitmap of roaming triggers. Setting this to + * zero will disable roaming altogether for the STA interface. + * @Min: 0 + * @Max: 0xFFFFFFFF + * @Default: 0xFFFF + * + * ROAM_TRIGGER_REASON_NONE BIT 0 + * ROAM_TRIGGER_REASON_PER BIT 1 + * ROAM_TRIGGER_REASON_BMISS BIT 2 + * ROAM_TRIGGER_REASON_LOW_RSSI BIT 3 + * ROAM_TRIGGER_REASON_HIGH_RSSI BIT 4 + * ROAM_TRIGGER_REASON_PERIODIC BIT 5 + * ROAM_TRIGGER_REASON_MAWC BIT 6 + * ROAM_TRIGGER_REASON_DENSE BIT 7 + * ROAM_TRIGGER_REASON_BACKGROUND BIT 8 + * ROAM_TRIGGER_REASON_FORCED BIT 9 + * ROAM_TRIGGER_REASON_BTM BIT 10 + * ROAM_TRIGGER_REASON_UNIT_TEST BIT 11 + * ROAM_TRIGGER_REASON_BSS_LOAD BIT 12 + * ROAM_TRIGGER_REASON_DEAUTH BIT 13 + * ROAM_TRIGGER_REASON_IDLE BIT 14 + * ROAM_TRIGGER_REASON_STA_KICKOUT BIT 15 + * ROAM_TRIGGER_EXT_REASON_MAX BIT 16 + * Bitmap corresponds to the enum roam_trigger_reason + * + * Related: none + * + * Supported Feature: Roaming + * + * Usage: Internal + * + * + */ +#define CFG_ROAM_TRIGGER_BITMAP "roam_triggers" +#define CFG_ROAM_TRIGGER_BITMAP_MIN 0 +#define CFG_ROAM_TRIGGER_BITMAP_MAX 0xFFFFFFFF +#define CFG_ROAM_TRIGGER_BITMAP_DEFAULT 0xFFFF + #endif /* @@ -2318,7 +2397,9 @@ enum hdd_dot11_mode { * WMI_ROAM_TRIGGER_REASON_BTM - 10 * WMI_ROAM_TRIGGER_REASON_UNIT_TEST - 11 * WMI_ROAM_TRIGGER_REASON_BSS_LOAD - 12 - * WMI_ROAM_TRIGGER_REASON_MAX - 13 + * WMI_ROAM_TRIGGER_REASON_DEAUTH - 13 + * WMI_ROAM_TRIGGER_REASON_IDLE - 14 + * WMI_ROAM_TRIGGER_REASON_MAX - 15 * * For Ex: 0xDA (PER, LOW_RSSI, HIGH_RSSI, MAWC, DENSE) * @@ -3648,7 +3729,7 @@ enum hdd_dot11_mode { #define CFG_INFRA_STA_KEEP_ALIVE_PERIOD_NAME "gStaKeepAlivePeriod" #define CFG_INFRA_STA_KEEP_ALIVE_PERIOD_MIN (0) #define CFG_INFRA_STA_KEEP_ALIVE_PERIOD_MAX (65535) -#define CFG_INFRA_STA_KEEP_ALIVE_PERIOD_DEFAULT (60) +#define CFG_INFRA_STA_KEEP_ALIVE_PERIOD_DEFAULT (30) /** * enum station_keepalive_method - available keepalive methods for stations @@ -5422,7 +5503,7 @@ enum hdd_link_speed_rpt_type { #define CFG_REPORT_MAX_LINK_SPEED "gReportMaxLinkSpeed" #define CFG_REPORT_MAX_LINK_SPEED_MIN (eHDD_LINK_SPEED_REPORT_ACTUAL) #define CFG_REPORT_MAX_LINK_SPEED_MAX (eHDD_LINK_SPEED_REPORT_MAX_SCALED) -#define CFG_REPORT_MAX_LINK_SPEED_DEFAULT (eHDD_LINK_SPEED_REPORT_MAX_SCALED) +#define CFG_REPORT_MAX_LINK_SPEED_DEFAULT (eHDD_LINK_SPEED_REPORT_ACTUAL) /* * @@ -5648,6 +5729,11 @@ enum hdd_link_speed_rpt_type { #else #define CFG_ENABLE_PACKET_LOG_DEFAULT (0) #endif + +#define CFG_PACKET_LOG_BUFFER_SIZE_NAME "PktlogBufSize" +#define CFG_PACKET_LOG_BUFFER_SIZE_DEFAULT (10) +#define CFG_PACKET_LOG_BUFFER_SIZE_MIN (1) +#define CFG_PACKET_LOG_BUFFER_SIZE_MAX (10) #endif @@ -7032,6 +7118,31 @@ enum hdd_link_speed_rpt_type { #define CFG_TDLS_PEER_KICKOUT_THRESHOLD_MAX (5000) #define CFG_TDLS_PEER_KICKOUT_THRESHOLD_DEFAULT (96) +/* + * + * gTDLSDiscoveryWakeTimeout - TDLS discovery WAKE timeout in ms. + * @Min: 10 + * @Max: 5000 + * @Default: 96 + * + * DUT will wake until this timeout to receive TDLS discovery response + * from peer. If tdls_discovery_wake_timeout is 0x0, the DUT will + * choose autonomously what wake timeout value to use. + * + * + * Related: gEnableTDLSSupport. + * + * Supported Feature: TDLS + * + * Usage: External + * + * + */ +#define CFG_TDLS_DISCOVERY_WAKE_TIMEOUT "gTDLSDiscoveryWakeTimeout" +#define CFG_TDLS_DISCOVERY_WAKE_TIMEOUT_MIN (0) +#define CFG_TDLS_DISCOVERY_WAKE_TIMEOUT_MAX (2000) +#define CFG_TDLS_DISCOVERY_WAKE_TIMEOUT_DEFAULT (200) + #endif /* @@ -8356,6 +8467,72 @@ enum hdd_link_speed_rpt_type { #define CFG_ENABLE_NAN_SUPPORT_DEFAULT (0) #define CFG_ENABLE_NAN_SUPPORT_MIN (0) #define CFG_ENABLE_NAN_SUPPORT_MAX (1) + +/* + * + * nan_separate_iface_support - Separate iface creation for NAN + * @Min: 0 + * @Max: 1 + * @Default: 1 + * + * Value is 1 when Host HDD supports separate iface creation for NAN + * + * Related: None + * + * Supported Feature: NAN + * + * Usage: External + * + * + */ +#define CFG_NAN_SEPARATE_IFACE_SUPP "nan_separate_iface_support" +#define CFG_NAN_SEPARATE_IFACE_SUPP_DEFAULT (1) +#define CFG_NAN_SEPARATE_IFACE_SUPP_MIN (0) +#define CFG_NAN_SEPARATE_IFACE_SUPP_MAX (1) + +/* + * + * gNdpKeepAlivePeriod - To configure duration of how many seconds + * to wait to kickout peer if peer is not reachable. + * + * @Min: 10 + * @Max: 30 + * @Default: 20 + * + * Related: None + * + * Supported Feature: NAN + * + * Usage: External + * + * + */ +#define CFG_NDP_KEEP_ALIVE_PERIOD "gNdpKeepAlivePeriod" +#define CFG_NDP_KEEP_ALIVE_PERIOD_MIN (10) +#define CFG_NDP_KEEP_ALIVE_PERIOD_MAX (30) +#define CFG_NDP_KEEP_ALIVE_PERIOD_DEFAULT (20) + +/* + * + * gSupportMp0Discovery - To support discovery of NAN cluster with + * Master Preference (MP) as 0 when a new device is enabling NAN. + * + * @Min: 0 + * @Max: 1 + * @Default: 0 + * + * Related: None + * + * Supported Feature: NAN + * + * Usage: External + * + * + */ +#define CFG_SUPPORT_MP0_DISCOVERY "gSupportMp0Discovery" +#define CFG_SUPPORT_MP0_DISCOVERY_MIN (0) +#define CFG_SUPPORT_MP0_DISCOVERY_MAX (1) +#define CFG_SUPPORT_MP0_DISCOVERY_DEFAULT (1) #endif #define CFG_ENABLE_SELF_RECOVERY "gEnableSelfRecovery" @@ -10011,14 +10188,18 @@ enum dot11p_mode { * g_sta_sap_scc_on_dfs_chan - Allow STA+SAP SCC on DFS channel with master * mode support disabled. * @Min: 0 - * @Max: 1 + * @Max: 2 * @Default: 0 * * This ini is used to allow STA+SAP SCC on DFS channel with master mode - * support disabled. + * support disabled, the value is defined by enum PM_AP_DFS_MASTER_MODE. * 0 - Disallow STA+SAP SCC on DFS channel * 1 - Allow STA+SAP SCC on DFS channel with master mode disabled - * + * 2 - enhance "1" with below requirement + * a. Allow single SAP (GO) start on DFS channel. + * b. Allow CAC process on DFS channel in single SAP (GO) mode + * c. Allow DFS radar event process in single SAP (GO) mode + * d. Disallow CAC and radar event process in SAP (GO) + STA mode. * Related: None. * * Supported Feature: Non-DBS, DBS @@ -10681,6 +10862,35 @@ enum dot11p_mode { */ #define CFG_ENABLE_DP_TRACE_CONFIG "gDptraceConfig" #define CFG_ENABLE_DP_TRACE_CONFIG_DEFAULT "1, 6, 2, 126" + +/* + * + * dp_proto_event_bitmap - Control for which protocol packet diag event should + * be sent to user space. + * @Min: 0 + * @Max: 0x17 + * @Default: 0x6 + * + * This ini is used to control for which protocol packet diag event should be + * sent to user space. + * + * QDF_NBUF_PKT_TRAC_TYPE_DNS 0x01 + * QDF_NBUF_PKT_TRAC_TYPE_EAPOL 0x02 + * QDF_NBUF_PKT_TRAC_TYPE_DHCP 0x04 + * QDF_NBUF_PKT_TRAC_TYPE_ARP 0x10 + * + * Related: None + * + * Supported Feature: STA, SAP + * + * Usage: Internal + * + * + */ +#define CFG_DP_PROTO_EVENT_BITMAP "dp_proto_event_bitmap" +#define CFG_DP_PROTO_EVENT_BITMAP_MIN (0x0) +#define CFG_DP_PROTO_EVENT_BITMAP_MAX (0x17) +#define CFG_DP_PROTO_EVENT_BITMAP_DEFAULT (0x17) #endif /* @@ -10736,7 +10946,7 @@ enum dot11p_mode { #define CFG_BUG_ON_REINIT_FAILURE_NAME "g_bug_on_reinit_failure" #define CFG_BUG_ON_REINIT_FAILURE_MIN (0) #define CFG_BUG_ON_REINIT_FAILURE_MAX (1) -#define CFG_BUG_ON_REINIT_FAILURE_DEFAULT (1) +#define CFG_BUG_ON_REINIT_FAILURE_DEFAULT (0) /* * @@ -10936,6 +11146,27 @@ enum dot11p_mode { #define CFG_RX_THREAD_CPU_MASK_DEFAULT (0) #endif +/* + * + * RX_THREAD_UL_CPU_AFFINITY_MASK - CPU mask to affine Rx_thread + * + * @Min: 0 + * @Max: 0xFF + * @Default: 0x0 + * + * This ini is used to set Rx_thread CPU affinity for uplink traffic + * + * Supported Feature: Rx_thread + * + * Usage: Internal + * + * + */ +#define CFG_RX_THREAD_UL_CPU_MASK_NAME "RX_THREAD_UL_CPU_AFFINITY_MASK" +#define CFG_RX_THREAD_UL_CPU_MASK_MIN (0) +#define CFG_RX_THREAD_UL_CPU_MASK_MAX (0xFF) +#define CFG_RX_THREAD_UL_CPU_MASK_DEFAULT (0) + /* List of RPS CPU maps for different rx queues registered by WLAN driver * Ref - Kernel/Documentation/networking/scaling.txt * RPS CPU map for a particular RX queue, selects CPU(s) for bottom half @@ -11123,6 +11354,30 @@ enum dot11p_mode { #define CFG_CRASH_FW_TIMEOUT_ENABLE (1) #define CFG_CRASH_FW_TIMEOUT_DEFAULT (1) +/* + * + * rx_wakelock_timeout - Amount of time to hold wakelock for RX unicast packets + * @Min: 0 + * @Max: 100 + * @Default: 50 + * + * This ini item configures the amount of time, in milliseconds, that the driver + * should prevent system power collapse after receiving an RX unicast packet. + * A conigured value of 0 disables the RX Wakelock feature completely. + * + * Related: None. + * + * Supported Feature: RX Wakelock + * + * Usage: Internal/External + * + * + */ +#define CFG_RX_WAKELOCK_TIMEOUT_NAME "rx_wakelock_timeout" +#define CFG_RX_WAKELOCK_TIMEOUT_DEFAULT (50) +#define CFG_RX_WAKELOCK_TIMEOUT_MIN (0) +#define CFG_RX_WAKELOCK_TIMEOUT_MAX (100) + /* * * enable_5g_band_pref - Enable preference for 5G from INI. @@ -13609,6 +13864,31 @@ enum hdd_external_acs_policy { #define CFG_OCE_WAN_WEIGHTAGE_MIN (0) #define CFG_OCE_WAN_WEIGHTAGE_MAX (100) +/* + * + * vendor_roam_score_algorithm - Algorithm to calculate AP score + * @Min: 0 + * @Max: 1 + * @Default: 0 + * + * By default the value is 0 and default roam algorithm will be used. + * When the value is 1, the V2 roaming algorithm will be used: + * For this V2 algo, AP score calculation is based on below equation: + * AP Score = (RSSIfactor * rssiweight(0.65)) + (CUfactor *cuweight(0.35)) + * + * Related: None + * + * Supported Feature: roam score algorithm + * + * Usage: External + * + * + */ +#define CFG_VENDOR_ROAM_SCORE_ALGORITHM_NAME "vendor_roam_score_algorithm" +#define CFG_VENDOR_ROAM_SCORE_ALGORITHM_MIN 0 +#define CFG_VENDOR_ROAM_SCORE_ALGORITHM_MAX 1 +#define CFG_VENDOR_ROAM_SCORE_ALGORITHM_DEFAULT 0 + /* * * best_rssi_threshold - Best Rssi for score calculation @@ -14754,9 +15034,22 @@ enum hdd_external_acs_policy { * * BIT 6: Set this to 1 will send BTM query frame and 0 not sent. * - * BIT 7-31: Reserved + * BIT 7: Roam to BTM candidates based on the roam score instead of BTM + * preferred value * - * Supported Feature: STA + * BIT 8: If AP does not support Neighbor report response, STA should + * request BTM query to get BTM request and check neighbor report exists + * or not. If Neighbor report exists, STA can use this information to update + * cached channel information + * + * BIT 9: When ever roaming is triggered after a successful roam scan a BTM + * query is sends to current connected AP which is 11v capable including the + * preferred candidate list obtained as part of roam scan with preference filled + * based on our internal scoring logic. + * + * BIT 10-31: Reserved + * + * Supported Feature: Roaming * * Usage: External * @@ -14777,7 +15070,7 @@ enum hdd_external_acs_policy { * This ini is used to configure timeout value for waiting BTM request. * Unit: millionsecond * - * Supported Feature: STA + * Supported Feature: Roaming * * Usage: External * @@ -14797,7 +15090,7 @@ enum hdd_external_acs_policy { * * This ini is used to configure maximum attempt for sending BTM query to ESS. * - * Supported Feature: STA + * Supported Feature: Roaming * * Usage: External * @@ -14818,7 +15111,7 @@ enum hdd_external_acs_policy { * This ini is used to configure Stick time after roaming to new AP by BTM. * Unit: seconds * - * Supported Feature: STA + * Supported Feature: Roaming * * Usage: External * @@ -14829,6 +15122,36 @@ enum hdd_external_acs_policy { #define CFG_BTM_STICKY_TIME_MAX (0x0000FFFF) #define CFG_BTM_STICKY_TIME_DEFAULT (300) +/* + * + * btm_query_bitmask - To send BTM query with candidate list on various roam + * scans reasons + * @Min: 0 + * @Max: 0xFFFFFFFF + * @Default: 0x8 + * + * This new ini is introduced to configure the bitmask for various roam scan + * reasons. Fw sends "BTM query with preferred candidate list" only for those + * roam scans which are enable through this bitmask. + + * For Example: + * Bitmask : 0x8 (LOW_RSSI) refer enum WMI_ROAM_TRIGGER_REASON_ID + * Bitmask : 0xDA (PER, LOW_RSSI, HIGH_RSSI, MAWC, DENSE) + * refer enum WMI_ROAM_TRIGGER_REASON_ID + * + * Related: None + * + * Supported Feature: Roaming + * + * Usage: External + * + * + */ +#define CFG_BTM_QUERY_BITMASK_NAME "btm_query_bitmask" +#define CFG_BTM_QUERY_BITMASK_MIN (0) +#define CFG_BTM_QUERY_BITMASK_MAX (0xFFFFFFFF) +#define CFG_BTM_QUERY_BITMASK_DEFAULT (0x8) + /* * * gcmp_enabled - ini to enable/disable GCMP @@ -15254,7 +15577,7 @@ enum hdd_external_acs_policy { /* * * gActionOUIConnect1x1 - Used to specify action OUIs for 1x1 connection - * @Default: 000C43 00 25 42 001018 06 02FFF02C0000 BC 25 42 001018 06 02FF040C0000 BC 25 42 00037F 00 35 6C + * @Default: 000C43 00 25 C2 001018 06 02FFF02C0000 BC 25 42 001018 06 02FF040C0000 BC 25 42 00037F 00 35 6C 001018 06 02FF009C0000 BC 25 48 * Note: User should strictly add new action OUIs at the end of this * default value. * @@ -15262,7 +15585,7 @@ enum hdd_external_acs_policy { * OUI 1 : 000C43 * OUI data Len : 00 * Info Mask : 25 - Check for NSS and Band - * Capabilities: 42 - NSS == 2 && Band == 2G + * Capabilities: C2 - NSS == 2 && Band == 2G || Band == 5G * OUI 2 : 001018 * OUI data Len : 06 * OUI Data : 02FFF02C0000 @@ -15297,7 +15620,7 @@ enum hdd_external_acs_policy { * */ #define CFG_ACTION_OUI_CONNECT_1X1_NAME "gActionOUIConnect1x1" -#define CFG_ACTION_OUI_CONNECT_1X1_DEFAULT "000C43 00 25 42 001018 06 02FFF02C0000 BC 25 42 001018 06 02FF040C0000 BC 25 42 00037F 00 35 6C 001018 06 02FF009C0000 BC 25 48" +#define CFG_ACTION_OUI_CONNECT_1X1_DEFAULT "000C43 00 25 C2 001018 06 02FFF02C0000 BC 25 42 001018 06 02FF040C0000 BC 25 42 00037F 00 35 6C 001018 06 02FF009C0000 BC 25 48" /* * @@ -15490,6 +15813,36 @@ enum hdd_external_acs_policy { #define CFG_ACTION_OUI_DISABLE_AGGRESSIVE_TX_NAME "gActionOUIDisableAggressiveTX" #define CFG_ACTION_OUI_DISABLE_AGGRESSIVE_TX_DEFAULT "FFFFFF 00 2A F85971000000 E0 50 FFFFFF 00 2A 14ABC5000000 E0 50" +/* + * + * gActionOUIDisableAggressiveEDCA - Used to specify action OUIs to control + * EDCA configuration when join the candidate AP + * + * @Default: NULL + * Note: User should strictly add new action OUIs at the end of this + * default value. + * + * This ini is used to specify AP OUIs. The station's EDCA should follow the + * APs' when connecting to those AP, even if the gEnableEdcaParams is set. + * For example, it follows the AP's EDCA whose OUI is 0050F2 with the + * following setting: + * gActionOUIDisableAggressiveEDCA=0050F2 00 01 + * Explain: 0050F2: OUI + * 00: data length is 0 + * 01: info mask, only OUI present in Info mask + * Refer to gEnableActionOUI for more detail about the format. + * + * Related: gEnableEdcaParams, gEnableActionOUI + * + * Supported Feature: Action OUIs + * + * Usage: External + * + * + */ +#define CFG_ACTION_OUI_DISABLE_AGGRESSIVE_EDCA "gActionOUIDisableAggressiveEDCA" +#define CFG_ACTION_OUI_DISABLE_AGGRESSIVE_EDCA_DEFAULT "" + /* End of action oui inis */ @@ -15984,6 +16337,37 @@ enum hdd_external_acs_policy { #define CFG_ROAM_SCORE_DELTA_MIN 0 #define CFG_ROAM_SCORE_DELTA_MAX 100 +/* + * + * min_roam_score_delta - Difference of roam score values between connected + * AP and roam candidate AP. + * @Min: 0 + * @Max: 10000 + * @Default: 1850 + * + * This ini is used during CU and low rssi based roam triggers, consider + * AP as roam candidate only if its roam score is better than connected + * AP score by at least min_roam_score_delta. + * If user configured "roam_score_delta" and "min_roam_score_delta" both, + * then firmware selects roam candidate AP by considering values of both + * INIs. + * Example: If DUT is connected with AP1 and roam candidate AP2 has roam + * score greater than roam_score_delta and min_roam_score_delta then only + * firmware will trigger roaming to AP2. + * + * Related: roam_score_delta + * + * Supported Feature: Roaming + * + * Usage: External + * + * + */ +#define CFG_CAND_MIN_ROAM_SCORE_DELTA "min_roam_score_delta" +#define CFG_CAND_MIN_ROAM_SCORE_DELTA_DEFAULT 1850 +#define CFG_CAND_MIN_ROAM_SCORE_DELTA_MAX 10000 +#define CFG_CAND_MIN_ROAM_SCORE_DELTA_MIN 0 + /* * * roam_score_delta_bitmap - bitmap to enable roam triggers on @@ -16122,6 +16506,26 @@ enum hdd_external_acs_policy { #define CFG_ENABLE_BEACON_RECEPTION_STATS_MAX 1 #define CFG_ENABLE_BEACON_RECEPTION_STATS_DEFAULT 0 +/* + * + * mgmt_retry_max - Maximum Retries for mgmt frames + * @Min: 0 + * @Max: 31 + * @Default: 15 + * + * This ini is used to set maximum retries for mgmt frames + * + * Supported Feature: STA/SAP + * + * Usage: External + * + * + */ +#define CFG_MGMT_RETRY_MAX "mgmt_retry_max" +#define CFG_MGMT_RETRY_MAX_MIN 0 +#define CFG_MGMT_RETRY_MAX_MAX 31 +#define CFG_MGMT_RETRY_MAX_DEFAULT 15 + /* * * btm_disassoc_timer_threshold - Disassociation timer threshold to wait @@ -16267,15 +16671,952 @@ enum hdd_external_acs_policy { #define CFG_IGNORE_FW_REG_OFFLOAD_IND_MAX (1) /* - * Type declarations + * + * ndp_inactivity_timeout - To configure duration of how many seconds + * without TX/RX data traffic, NDI vdev can kickout the connected + * peer(i.e. NDP Termination). + * + * @Min: 0 + * @Max: 180 + * @Default: 60 + * + * Related: None + * + * Supported Feature: NAN + * + * Usage: External + * + * */ +#define CFG_NAN_NDP_INACTIVITY_TIMEOUT "ndp_inactivity_timeout" +#define CFG_NAN_NDP_INACTIVITY_TIMEOUT_DEFAULT (60) +#define CFG_NAN_NDP_INACTIVITY_TIMEOUT_MAX (1800) +#define CFG_NAN_NDP_INACTIVITY_TIMEOUT_MIN (0) -struct hdd_config { - /* Bitmap to track what is explicitly configured */ - DECLARE_BITMAP(bExplicitCfg, MAX_CFG_INI_ITEMS); - - /* Config parameters */ -#ifdef WLAN_NUD_TRACKING +/* + * + * enable_disconnect_roam_offload - Enable/Disable emergency roaming during + * deauth/disassoc + * @Min: 0 - Disabled + * @Max: 1 - Enabled + * @Default: 1 + * + * When this ini is enabled firmware will trigger roam scan and roam to a new ap + * if candidate is found and it will not send the deauth/disassoc frame to + * the host driver. + * If roaming fails after this deauth, then firmware will send + * WMI_ROAM_REASON_DEAUTH event to the host. If roaming is successful, driver + * follows the normal roam synch event path. + * + * Supported Feature: Roaming + * + * Usage: Internal/External + * + * + */ +#define CFG_LFR_ENABLE_DISCONNECT_ROAM "enable_disconnect_roam_offload" +#define CFG_LFR_ENABLE_DISCONNECT_ROAM_MIN (false) +#define CFG_LFR_ENABLE_DISCONNECT_ROAM_MAX (true) +#define CFG_LFR_ENABLE_DISCONNECT_ROAM_DEFAULT (true) + +/* + * + * enable_idle_roam - Enable/Disable idle roaming + * @Min: 0 - Disabled + * @Max: 1 - Enabled + * @Default: 0 + * + * When this ini is enabled firmware will trigger roam scan and roam to a new + * ap if current connected AP rssi falls below the threshold. To consider the + * connection as idle, the following conditions should be met if this ini + * "enable_idle_roam" is enabled: + * 1. User space sends "SET SUSPENDMODE" command with value 0. + * 2. No TX/RX data for idle time configured via ini "idle_roam_inactive_time". + * 3. Connected AP rssi change doesn't exceed a specific delta value. + * (configured via ini idle_roam_rssi_delta) + * 4. Connected AP rssi falls below minimum rssi (configured via ini + * "idle_roam_min_rssi"). + * + * Supported Feature: Roaming + * + * Usage: Internal/External + * + * + */ +#define CFG_LFR_ENABLE_IDLE_ROAM "enable_idle_roam" +#define CFG_LFR_ENABLE_IDLE_ROAM_MIN (false) +#define CFG_LFR_ENABLE_IDLE_ROAM_MAX (true) +#define CFG_LFR_ENABLE_IDLE_ROAM_DEFAULT (false) + +/* + * + * idle_roam_rssi_delta - This threshold is the criteria to decide whether DUT + * is idle or moving. If rssi delta is more than configured thresold then its + * considered as not idle. RSSI delta is entered in dBm. Idle roaming can be + * triggered if the connected AP rssi change exceeds or falls below the + * rssi delta and if other criteria of ini "enable_idle_roam" is met + * @Min: 0 + * @Max: 50 + * @Default: 3 + * + * Related: enable_idle_roam + * + * Supported Feature: Roaming + * + * Usage: Internal/External + * + * + */ +#define CFG_LFR_IDLE_ROAM_RSSI_DELTA "idle_roam_rssi_delta" +#define CFG_LFR_IDLE_ROAM_RSSI_DELTA_MIN (0) +#define CFG_LFR_IDLE_ROAM_RSSI_DELTA_MAX (50) +#define CFG_LFR_IDLE_ROAM_RSSI_DELTA_DEFAULT (3) + +/* + * + * idle_roam_inactive_time - Time duration in millseconds for which the + * connection is idle. + * @Min: 0 + * @Max: 0xFFFFFFFF + * @Default: 10000 + * + * This ini is used to configure the time in seconds for which the connection + * candidate is idle and after which idle roam scan can be triggered if + * other criteria of ini "enable_idle_roam" is met. + * + * Related: enable_idle_roam + * + * Supported Feature: Roaming + * + * Usage: Internal/External + * + * + */ +#define CFG_LFR_IDLE_ROAM_INACTIVE_TIME "idle_roam_inactive_time" +#define CFG_LFR_IDLE_ROAM_INACTIVE_TIME_MIN (0) +#define CFG_LFR_IDLE_ROAM_INACTIVE_TIME_MAX (0xFFFFFFFF) +#define CFG_LFR_IDLE_ROAM_INACTIVE_TIME_DEFAULT (10000) + +/* + * + * idle_data_packet_count - No of tx/rx packets above which the connection is + * not idle. + * @Min: 0 + * @Max: 0xFFFFFFFF + * @Default: 10 + * + * This ini is used to configure the acceptable number of tx/rx packets below + * which the connection is idle. Ex: If idle_data_packet_count is 10 + * and if the tx/rx packet count is less than 10, the connection is + * idle. If there are more than 10 packets, the connection is active one. + * + * Related: enable_idle_roam + * + * Supported Feature: Roaming + * + * Usage: Internal/External + * + * + */ +#define CFG_LFR_IDLE_ROAM_PACKET_COUNT "idle_data_packet_count" +#define CFG_LFR_IDLE_ROAM_PACKET_COUNT_MIN (0) +#define CFG_LFR_IDLE_ROAM_PACKET_COUNT_MAX (0xFFFFFFFF) +#define CFG_LFR_IDLE_ROAM_PACKET_COUNT_DEFAULT (10) + +/* + * + * idle_roam_min_rssi - Minimum RSSI of connected AP, below which + * idle roam scan can be triggered if other criteria of ini "enable_idle_roam" + * is met. + * @Min: -96 + * @Max: 0 + * @Default: -65 + * + * Related: enable_idle_roam + * + * Supported Feature: Roaming + * + * Usage: Internal/External + * + * + */ +#define CFG_LFR_IDLE_ROAM_MIN_RSSI "idle_roam_min_rssi" +#define CFG_LFR_IDLE_ROAM_MIN_RSSI_MIN (-96) +#define CFG_LFR_IDLE_ROAM_MIN_RSSI_MAX (0) +#define CFG_LFR_IDLE_ROAM_MIN_RSSI_DEFAULT (-65) + +/* + * + * idle_roam_band - Band on which idle roam scan will be + * enabled + * @Min: 0 + * @Max: 2 + * @Default: 0 + * + * Value 0 - Allow idle roam on both bands + * Value 1 - Allow idle roam only on 2G band + * Value 2 - Allow idle roam only on 5G band + * + * Related: enable_idle_roam + * + * Supported Feature: Roaming + * + * Usage: Internal/External + * + * + */ +#define CFG_LFR_IDLE_ROAM_BAND "idle_roam_band" +#define CFG_LFR_IDLE_ROAM_BAND_MIN (0) +#define CFG_LFR_IDLE_ROAM_BAND_MAX (2) +#define CFG_LFR_IDLE_ROAM_BAND_DEFAULT (0) + +#ifdef WLAN_ADAPTIVE_11R +/* + * + * adaptive_11r - Enable/disable adaptive 11r feature. + * @Min: 0 + * @Max: 1 + * @Default: 0 + * + * Adaptive 11r feature enables the AP to support FT-AKM without + * configuring the FT-AKM in the network. The AP will advertise non-FT akm + * with a vendor specific IE having Adaptive 11r bit set to 1 in the IE data. + * The AP also advertises the MDE in beacon/probe response. + * + * STA should check the adaptive 11r capability if the AP advertises MDE in + * beacon/probe and adaptive 11r capability in vendor specific IE. If adaptive + * 11r capability is found, STA can advertise the FT equivalent of the non-FT + * AKM and connect with 11r protocol. + * + * Related: None. + * + * Supported Feature: Fast BSS Transition + * + * Usage: External + * + * + */ +#define CFG_ADAPTIVE_11R "enable_adaptive_11r" +#define CFG_ADAPTIVE_11R_MIN (false) +#define CFG_ADAPTIVE_11R_MAX (true) +#define CFG_ADAPTIVE_11R_DEFAULT (false) +#endif + +#if defined(WLAN_SAE_SINGLE_PMK) && defined(WLAN_FEATURE_ROAM_OFFLOAD) +/* + * + * sae_single_pmk_feature_enabled - Enable/disable sae single pmk feature. + * @Min: 0 + * @Max: 1 + * @Default: 0 + * + * This INI is to enable/disable SAE Roaming with same PMK/PMKID feature support + * + * Related: None + * + * Supported Feature: Roaming + * + * Usage: Internal + * + * + */ +#define CFG_SAE_SINGLE_PMK "sae_single_pmk_feature_enabled" +#define CFG_SAE_SINGLE_PMK_MIN (false) +#define CFG_SAE_SINGLE_PMK_MAX (true) +#define CFG_SAE_SINGLE_PMK_DEFAULT (false) +#endif + +/* + * + * bss_load_trigger_5g_rssi_threshold - Current AP minimum RSSI in dBm below + * which roaming can be triggered if BSS load exceeds bss_load_threshold. + * @Min: -120 + * @Max: 0 + * @Default: -70 + * + * If connected AP is in 5Ghz, then consider bss load roam triggered only if + * load % > bss_load_threshold && connected AP rssi is worse than + * bss_load_trigger_5g_rssi_threshold + * + * Related: "bss_load_threshold" + * + * Supported Feature: Roaming + * + * Usage: Internal/External + * + * + */ +#define CFG_BSS_LOAD_TRIG_5G_RSSI_THRES "bss_load_trigger_5g_rssi_threshold" +#define CFG_BSS_LOAD_TRIG_5G_RSSI_THRES_MIN -120 +#define CFG_BSS_LOAD_TRIG_5G_RSSI_THRES_MAX 0 +#define CFG_BSS_LOAD_TRIG_5G_RSSI_THRES_DEFAULT -70 + +/* + * + * bss_load_trigger_2g_rssi_threshold - Current AP minimum RSSI in dBm below + * which roaming can be triggered if BSS load exceeds bss_load_threshold. + * @Min: -120 + * @Max: 0 + * @Default: -60 + * + * If connected AP is in 2Ghz, then consider bss load roam triggered only if + * load % > bss_load_threshold && connected AP rssi is worse than + * bss_load_trigger_2g_rssi_threshold. + * + * Related: "bss_load_threshold" + * + * Supported Feature: Roaming + * + * Usage: Internal/External + * + * + */ +#define CFG_BSS_LOAD_TRIG_2G_RSSI_THRES "bss_load_trigger_2g_rssi_threshold" +#define CFG_BSS_LOAD_TRIG_2G_RSSI_THRES_MIN -120 +#define CFG_BSS_LOAD_TRIG_2G_RSSI_THRES_MAX 0 +#define CFG_BSS_LOAD_TRIG_2G_RSSI_THRES_DEFAULT -60 + +/* + * + * roam_scan_inactivity_time - Device inactivity monitoring time in + * milliseconds for which the device is considered to be inactive with data + * packets count is less than configured roam_inactive_data_count. + * + * @Min: 0 + * @Max: 0xFFFFFFFF + * @Default: 0 + * + * The below three ini values are used to control the roam scan after the + * firmware gets empty roam scan results during periodic roam scans. + * 1. roam_scan_inactivity_time + * 2. roam_inactive_data_count + * 3. roam_scan_period_after_inactivity + * The first two ini "roam_scan_inactivity_time" and "roam_inactive_data_count" + * is frames the criteria to detect if the DUT is inactive. If the device is + * identified to be inactive based on the above two ini, then the value, + * "roam_scan_period_after_inactivity" will be used as periodic roam scan + * duration. + * + * Related: roam_inactive_data_count + * + * Supported Feature: Roaming + * + * Usage: External + * + * + */ +#define CFG_ROAM_SCAN_INACTIVITY_TIME "roam_scan_inactivity_time" +#define CFG_ROAM_SCAN_INACTIVITY_TIME_MIN 0 +#define CFG_ROAM_SCAN_INACTIVITY_TIME_MAX 0xFFFFFFFF +#define CFG_ROAM_SCAN_INACTIVITY_TIME_DEFAULT 0 + +/* + * + * roam_inactive_data_count - Maximum allowed data packets count during + * roam_scan_inactivity_time. + * + * @Min: 0 + * @Max: 0xFFFFFFFF + * @Default: 10 + * + * The DUT is said to be inactive only if the data packets count + * during this roam_scan_inactivity_time is less than the configured + * roam_inactive_data_count. + * + * Related: roam_scan_inactivity_time + * + * Supported Feature: Roaming + * + * Usage: External + * + * + */ +#define CFG_ROAM_INACTIVE_COUNT "roam_inactive_data_count" +#define CFG_ROAM_INACTIVE_COUNT_MIN 0 +#define CFG_ROAM_INACTIVE_COUNT_MAX 0xFFFFFFFF +#define CFG_ROAM_INACTIVE_COUNT_DEFAULT 10 + +/* + * + * roam_scan_period_after_inactivity - Roam scan duration in ms after device is + * out of inactivity state. + * + * @Min: 0 + * @Max: 0xFFFFFFFF + * @Default: 120000 + * + * If there is empty scan results during roam scan, firmware will move to + * roam scan inactive state if roam_scan_inactivity and + * roam_inactive_data_count criteria are met. + * This ini is used to configure the roam scan duration in ms once the + * inactivity is finished and roam scan can be started. + * + * Related: roam_scan_inactivity_time, roam_inactive_data_count + * + * Supported Feature: Roaming + * + * Usage: External + * + * + */ +#define CFG_POST_INACTIVITY_ROAM_SCAN_PERIOD "roam_scan_period_after_inactivity" +#define CFG_POST_INACTIVITY_ROAM_SCAN_PERIOD_MIN 0 +#define CFG_POST_INACTIVITY_ROAM_SCAN_PERIOD_MAX 0xFFFFFFFF +#define CFG_POST_INACTIVITY_ROAM_SCAN_PERIOD_DEFAULT 120000 + +/* + * + * candidate_min_rssi_for_disconnect - Candidate AP minimum RSSI in + * idle roam trigger(in dBm). + * @Min: -120 + * @Max: 0 + * @Default: -70 + * + * Minimum RSSI value of the candidate AP to consider it as candidate for + * roaming when roam trigger is Deauthentication/Disconnection from current + * AP. This value will be sent to firmware over the WMI_ROAM_AP_PROFILE + * wmi command in the roam_min_rssi_param_list tlv. + * + * Related: enable_idle_roam. + * + * Supported Feature: Roaming + * + * Usage: Internal/External + * + * + */ +#define CFG_DISCONNECT_ROAM_TRIGGER_MIN_RSSI "candidate_min_rssi_for_disconnect" +#define CFG_DISCONNECT_ROAM_TRIGGER_MIN_RSSI_MIN -120 +#define CFG_DISCONNECT_ROAM_TRIGGER_MIN_RSSI_MAX 0 +#define CFG_DISCONNECT_ROAM_TRIGGER_MIN_RSSI_DEFAULT -70 + +/* + * + * candidate_min_rssi_for_beacon_miss - Candidate AP minimum RSSI for beacon + * miss roam trigger (in dBm) + * @Min: -120 + * @Max: 0 + * @Default: -70 + * + * Minimum RSSI value of the candidate AP to consider it as candidate for + * roaming when roam trigger is disconnection from current AP due to beacon + * miss. This value will be sent to firmware over the WMI_ROAM_AP_PROFILE + * wmi command in the roam_min_rssi_param_list tlv. + * + * Related: None + * + * Supported Feature: Roaming + * + * Usage: Internal/External + * + * + */ +#define CFG_BMISS_ROAM_MIN_RSSI "candidate_min_rssi_for_beacon_miss" +#define CFG_BMISS_ROAM_MIN_RSSI_MIN -120 +#define CFG_BMISS_ROAM_MIN_RSSI_MAX 0 +#define CFG_BMISS_ROAM_MIN_RSSI_DEFAULT -70 + +/* + * + * idle_roam_score_delta - Roam score delta value in percentage for idle roam. + * @Min: 0 + * @Max: 100 + * @Default: 10 + * + * This ini is used to configure the minimum change in roam score + * value of the AP to consider it as candidate for + * roaming when roam trigger is due to idle state of sta. + * This value will be sent to firmware over the WMI_ROAM_AP_PROFILE wmi + * command in the roam_score_delta_param_list tlv. + * Related: None + * + * Supported Feature: Roaming + * + * Usage: External + * + * + */ +#define CFG_IDLE_ROAM_SCORE_DELTA "idle_roam_score_delta" +#define CFG_IDLE_ROAM_SCORE_DELTA_MIN 0 +#define CFG_IDLE_ROAM_SCORE_DELTA_MAX 100 +#define CFG_IDLE_ROAM_SCORE_DELTA_DEFAULT 10 + +/* + * + * btm_roam_score_delta - Roam score delta value in percentage for BTM triggered + * roaming. + * @Min: 0 + * @Max: 100 + * @Default: 10 + * + * This ini is used to configure the minimum change in roam score + * value of the AP to consider it as candidate when the sta is disconnected + * from the current AP due to BTM kickout. + * This value will be sent to firmware over the WMI_ROAM_AP_PROFILE wmi + * command in the roam_score_delta_param_list tlv. + * + * Related: None + * + * Supported Feature: Roaming + * + * Usage: External + * + * + */ +#define CFG_BTM_ROAM_SCORE_DELTA "btm_roam_score_delta" +#define CFG_BTM_ROAM_SCORE_DELTA_MIN 0 +#define CFG_BTM_ROAM_SCORE_DELTA_MAX 100 +#define CFG_BTM_ROAM_SCORE_DELTA_DEFAULT 10 + +/* + * + * minimum_btm_candidate_score - Consider the AP as roam candidate only if + * its score is greater than minimum_btm_candidate_score. + * @Min: 0 + * @Max: 10000 + * @Default: 1800 + * + * This ini is applicable only for candidate selection during BTM roam trigger. + * For this roam_score_delta_bitmap bit 10 should be set to 1. + * + * Related: None + * + * Supported Feature: Roaming + * + * Usage: External + * + * + */ +#define CFG_MIN_BTM_CANDIDATE_SCORE "minimum_btm_candidate_score" +#define CFG_MIN_BTM_CANDIDATE_SCORE_MIN 0 +#define CFG_MIN_BTM_CANDIDATE_SCORE_MAX 10000 +#define CFG_MIN_BTM_CANDIDATE_SCORE_DEFAULT 1800 + +/* + * + * enable_pending_list_req - Sets Pending channel List Req. + * @Min: 0 + * @Max: 1 + * @Default: 0 + * + * This option enables/disables SCAN_CHAN_LIST_CMDID channel list command to FW + * till the current scan is complete. + * + * Related: None + * + * Supported Feature: STA + * + * Usage: External + * + * + */ +#define CFG_ENABLE_PENDING_CHAN_LIST_REQ "enable_pending_list_req" +#define CFG_ENABLE_PENDING_CHAN_LIST_REQ_MIN 0 +#define CFG_ENABLE_PENDING_CHAN_LIST_REQ_MAX 1 +#define CFG_ENABLE_PENDING_CHAN_LIST_REQ_DEFAULT 0 + +/* + * + * gEnableRingBuffer - Enable Ring Buffer for Bug Report + * @Min: 0 + * @Max: 1 + * @Default: 1 + * + * This ini is used to enable Ring Buffer + * + * Related: None + * + * Supported Feature: STA/SAP + * + * Usage: External + * + * + */ +#define CFG_ENABLE_RING_BUFFER "gEnableRingBuffer" +#define CFG_ENABLE_RING_BUFFER_MIN 0 +#define CFG_ENABLE_RING_BUFFER_MAX 1 +#define CFG_ENABLE_RING_BUFFER_DEFAULT 1 + + +/* + * + * gNumVdevs - max number of VDEVs supported + * @Min: 0x1 + * @Max: 0x4 + * @Default: CFG_TGT_NUM_VDEV + * + * Usage: External + * + */ +#define CFG_NUM_VDEV_ENABLE_NAME "gNumVdevs" +#define CFG_NUM_VDEV_ENABLE_MIN (0x1) +#define CFG_NUM_VDEV_ENABLE_MAX (0x4) +#define CFG_NUM_VDEV_ENABLE_DEFAULT (CFG_TGT_NUM_VDEV) + +#ifdef SAR_SAFETY_FEATURE +/* + * + * gSarSafetyTimeout - Specify SAR safety timeout value in milliseconds + * + * @Min: 120000 + * @Max: 600000 + * Default: 300000 + * + * This ini is used to define SAR safety timeout value in milliseconds. + * This timer is started when the QCA_NL80211_VENDOR_SUBCMD_SET_SAR_LIMITS + * is received first time. + * SAR safety timer will wait for the gSarSafetyTimeout for + * QCA_NL80211_VENDOR_SUBCMD_SET_SAR_LIMITS vendor command and if + * SAR safety timer timeouts host will configure the gSarSafetyIndex + * to the FW. + * + * Usage: External + * + * + */ + +#define CFG_SAR_SAFETY_TIMEOUT "gSarSafetyTimeout" +#define CFG_SAR_SAFETY_TIMEOUT_MIN (120000) +#define CFG_SAR_SAFETY_TIMEOUT_MAX (600000) +#define CFG_SAR_SAFETY_TIMEOUT_DEFAULT (300000) +/* + * + * gSarSafetyUnsolicitedTimeout - Specify SAR safety unsolicited timeout value + * in milliseconds + * + * @Min: 5000 + * @Max: 30000 + * Default: 15000 + * + * This ini is used to define SAR safety unsolicited timeout value in + * milliseconds. This timer is started on first data tx. + * SAR unsolicited timer will wait for the + * gSarSafetyUnsolicitedTimeout for QCA_NL80211_VENDOR_SUBCMD_SET_SAR_LIMITS + * vendor command and if SAR unsolicited timer timeouts host will indicate + * user space with QCA_NL80211_VENDOR_SUBCMD_REQUEST_SAR_LIMITS_EVENT to send + * QCA_NL80211_VENDOR_SUBCMD_SET_SAR_LIMITS vendor command. + * + * Usage: External + * + * + */ +#define CFG_SAR_SAFETY_UNSOLICITED_TIMEOUT "gSarSafetyUnsolicitedTimeout" +#define CFG_SAR_SAFETY_UNSOLICITED_TIMEOUT_MIN (5000) +#define CFG_SAR_SAFETY_UNSOLICITED_TIMEOUT_MAX (30000) +#define CFG_SAR_SAFETY_UNSOLICITED_TIMEOUT_DEFAULT (15000) + +/* + * + * gSarSafetyReqRespTimeout - Specify SAR safety request response timeout value + * in milliseconds + * + * @Min: 500 + * @Max: 3000 + * Default: 1000 + * + * This ini is used to define SAR request-response timeout value + * in milliseconds. SAR request-response timer will wait for the + * gSarSafetyReqRespTimeout for QCA_NL80211_VENDOR_SUBCMD_SET_SAR_LIMITS + * vendor command and if SAR request-response timer timeouts host will + * indicate user space with QCA_NL80211_VENDOR_SUBCMD_REQUEST_SAR_LIMITS_EVENT + * for gSarSafetyReqRespRetry number of times to send + * QCA_NL80211_VENDOR_SUBCMD_SET_SAR_LIMITS vendor command and still if host + * does not get QCA_NL80211_VENDOR_SUBCMD_SET_SAR_LIMITS vendor command, host + * will configure the gSarSafetyIndex to the FW. + * + * Usage: External + * + * + */ +#define CFG_SAR_SAFETY_REQ_RESP_TIMEOUT "gSarSafetyReqRespTimeout" +#define CFG_SAR_SAFETY_REQ_RESP_TIMEOUT_MIN (500) +#define CFG_SAR_SAFETY_REQ_RESP_TIMEOUT_MAX (3000) +#define CFG_SAR_SAFETY_REQ_RESP_TIMEOUT_DEFAULT (1000) + +/* + * + * gSarSafetyReqRespRetry - Specify SAR request response retries value + * + * @Min: 1 + * @Max: 10 + * Default: 5 + * + * This ini is used to define SAR request-response retries value. + * SAR request-response timer will wait for the gSarReqRespTimeout for + * QCA_NL80211_VENDOR_SUBCMD_SET_SAR_LIMITS vendor command and if + * SAR request-response timer timeouts host will indicate user space + * for gSarSafetyReqRespRetry number of times to send + * QCA_NL80211_VENDOR_SUBCMD_SET_SAR_LIMITS vendor command and still if + * host does not get QCA_NL80211_VENDOR_SUBCMD_SET_SAR_LIMITS vendor + * command, host will configure the gSarSafetyIndex to the FW. + * + * Usage: External + * + * + */ +#define CFG_SAR_SAFETY_REQ_RESP_RETRIES "gSarSafetyReqRespRetry" +#define CFG_SAR_SAFETY_REQ_RESP_RETRIES_MIN (1) +#define CFG_SAR_SAFETY_REQ_RESP_RETRIES_MAX (10) +#define CFG_SAR_SAFETY_REQ_RESP_RETRIES_DEFAULT (5) + +/* + * + * gSarSafetyIndex - Specify SAR safety index + * + * @Min: 0 + * @Max: 11 + * Default: 11 + * + * This ini is used to define SAR safety index, when sar safety timer + * timeouts or sar request response timer timeouts for gSarSafetyReqRespRetry + * number of times, host will configure gSarSafetyIndex value to the FW. + * + * Usage: External + * + * + */ +#define CFG_SAR_SAFETY_INDEX "gSarSafetyIndex" +#define CFG_SAR_SAFETY_INDEX_MIN (0) +#define CFG_SAR_SAFETY_INDEX_MAX (11) +#define CFG_SAR_SAFETY_INDEX_DEFAULT (11) + +/* + * + * gSarSafetySleepIndex - Specify SAR Safety sleep index + * + * @Min: 0 + * @Max: 11 + * Default: 11 + * + * This ini is used to define SAR sleep index, when device goes into the + * sleep mode, before going into the sleep mode host configures + * gSarSafetySleepIndex value to the FW. + * + * Usage: External + * + * + */ +#define CFG_SAR_SAFETY_SLEEP_INDEX "gSarSafetySleepIndex" +#define CFG_SAR_SAFETY_SLEEP_INDEX_MIN (0) +#define CFG_SAR_SAFETY_SLEEP_INDEX_MAX (11) +#define CFG_SAR_SAFETY_SLEEP_INDEX_DEFAULT (11) + +/* + * + * gEnableSarSafety - Enable/Disable SAR safety feature + * + * @Min: 0 + * @Max: 1 + * Default: 0 + * + * This ini is used to enable/disable SAR safety feature + * Value 1 of this ini enables SAR safety feature and + * value 0 of this ini disables SAR safety feature + * + * Usage: External + * + * + */ +#define CFG_ENABLE_SAR_SAFETY_FEATURE "gEnableSarSafety" +#define CFG_ENABLE_SAR_SAFETY_FEATURE_MIN (0) +#define CFG_ENABLE_SAR_SAFETY_FEATURE_MAX (1) +#define CFG_ENABLE_SAR_SAFETY_FEATURE_DEFAULT (0) + +/* + * + * gConfigSarSafetySleepIndex - Enable/Disable SAR Safety sleep index + * + * @Min: 0 + * @Max: 1 + * Default: 0 + * + * This Configuration is to decide that before going to + * sleep mode whether to maintain high RF power + * (SAR disable) or to configure SAR sleep mode index + * + * Value 0 for this ini indicates to maintain high + * RF power (SAR disable) + * Value 1 for this ini indicates to configure SAR + * sleep mode index. + * + * Usage: External + * + * + */ +#define CFG_CONFIG_SAR_SAFETY_SLEEP_MODE_INDEX "gConfigSarSafetySleepIndex" +#define CFG_CONFIG_SAR_SAFETY_SLEEP_MODE_INDEX_MIN (0) +#define CFG_CONFIG_SAR_SAFETY_SLEEP_MODE_INDEX_MAX (1) +#define CFG_CONFIG_SAR_SAFETY_SLEEP_MODE_INDEX_DEFAULT (0) +#endif + +#define CFG_PKT_CAPTURE_MODE_MGMT_PKT BIT(0) +#define CFG_PKT_CAPTURE_MODE_DATA_PKT BIT(1) + +/* + * + * packet_capture_mode - Packet capture mode + * @Min: 0 + * @Max: 3 + * Default: 0 - Capture no packets + * + * This ini is used to decide packet capture mode + * + * packet_capture_mode = 0 - Capture no packets + * packet_capture_mode = 1 - Capture management packets only + * packet_capture_mode = 2 - Capture data packets only + * packet_capture_mode = 3 - Capture both data and management packets + * + * Supported Feature: packet capture + * + * Usage: External + * + * + */ +#define CFG_PKT_CAPTURE_MODE "packet_capture_mode" +#define CFG_PKT_CAPTURE_MODE_MIN 0 +#define CFG_PKT_CAPTURE_MODE_MAX (CFG_PKT_CAPTURE_MODE_MGMT_PKT | \ + CFG_PKT_CAPTURE_MODE_DATA_PKT) +#define CFG_PKT_CAPTURE_MODE_DEFAULT 0 + +/* + * + * disable_4way_hs_offload - Enable/Disable 4 way handshake offload to firmware + * @Min: 0 + * @Max: 1 + * @Default: 0 + * + * 0 4-way HS to be handled in firmware + * 1 4-way HS to be handled in supplicant + * + * Related: None + * + * Supported Feature: STA Roaming + * + * Usage: External + * + * + */ +#define CFG_DISABLE_4WAY_HS_OFFLOAD "disable_4way_hs_offload" +#define CFG_DISABLE_4WAY_HS_OFFLOAD_MIN (0) +#define CFG_DISABLE_4WAY_HS_OFFLOAD_MAX (1) +#define CFG_DISABLE_4WAY_HS_OFFLOAD_DEFAULT (0) + +/* + * + * enable_time_sync_ftm - Time Sync FTM feature support + * @Min: 0 + * @Max: 1 + * @Default: 0 - Disable feature + * + * When set to 1 Time Sync FTM feature will be enabled. + * + * Supported Feature: Time Sync FTM + * + * Usage: External + * + * + */ +#define CFG_ENABLE_TIME_SYNC_FTM "enable_time_sync_ftm" +#define CFG_ENABLE_TIME_SYNC_FTM_MIN (0) +#define CFG_ENABLE_TIME_SYNC_FTM_MAX (1) +#define CFG_ENABLE_TIME_SYNC_FTM_DEFAULT (0) + +/* + * + * time_sync_ftm_mode- Time Sync FTM feature Mode configuration + * @Min: 0 - Aggregated Mode + * @Max: 1 - Burst Mode + * @Default: 0 + * + * This ini is applicable only if enable_time_sync_ftm is set to 1. + * + * Supported Feature: Time Sync FTM + * + * Usage: External + * + * + */ +#define CFG_TIME_SYNC_FTM_MODE "time_sync_ftm_mode" +#define CFG_TIME_SYNC_FTM_MODE_MIN (0) +#define CFG_TIME_SYNC_FTM_MODE_MAX (1) +#define CFG_TIME_SYNC_FTM_MODE_DEFAULT (0) + +/* + * + * time_sync_ftm_role- Time Sync FTM feature Role configuration + * @Min: 0 - Slave Role + * @Max: 1 - Master Role + * @Default: 0 + * + * This ini is applicable only if enable_time_sync_ftm is set to 1. + * + * Supported Feature: Time Sync FTM + * + * Usage: External + * + * + */ +#define CFG_TIME_SYNC_FTM_ROLE "time_sync_ftm_role" +#define CFG_TIME_SYNC_FTM_ROLE_MIN (0) +#define CFG_TIME_SYNC_FTM_ROLE_MAX (1) +#define CFG_TIME_SYNC_FTM_ROLE_DEFAULT (0) + +/* + * + * bmiss_skip_full_scan - To decide whether firmware does channel map based + * partial scan or partial scan followed by full scan in case no candidate is + * found in partial scan. + * @Min: 0 + * @Max: 1 + * @Default: 0 + * + * 0 : Based on the channel map , firmware does scan to find new AP. if AP is + * not found then it does a full scan on all valid channels. + * 1 : Firmware does channel map based partial scan only. + * + * Related: None + * + * Supported Feature: Roaming + * + * Usage: External + * + * + */ +#define CFG_BMISS_SKIP_FULL_SCAN "bmiss_skip_full_scan" +#define CFG_BMISS_SKIP_FULL_SCAN_MIN 0 +#define CFG_BMISS_SKIP_FULL_SCAN_MAX 1 +#define CFG_BMISS_SKIP_FULL_SCAN_DEFAULT 0 + +/* + * + * p2p_disable_roam- Disable Roam on sta interface during P2P connection + * @Min: 0 - Roam Enabled on sta interface during P2P connection + * @Max: 1 - Roam Disabled on sta interface during P2P connection + * @Default: 0 + * + * Disable roaming on STA iface to avoid audio glitches on p2p if its connected + * + * Supported Feature: Disable Roam during P2P + * + * Usage: Internal + * + * + */ +#define CFG_P2P_DISABLE_ROAM "p2p_disable_roam" +#define CFG_P2P_DISABLE_ROAM_MIN (0) +#define CFG_P2P_DISABLE_ROAM_MAX (1) +#define CFG_P2P_DISABLE_ROAM_DEFAULT (0) + +/* + * Type declarations + */ + +struct hdd_config { + /* Bitmap to track what is explicitly configured */ + DECLARE_BITMAP(bExplicitCfg, MAX_CFG_INI_ITEMS); + + /* Config parameters */ +#ifdef WLAN_NUD_TRACKING bool enable_nud_tracking; #endif bool enable_connected_scan; @@ -16626,6 +17967,7 @@ struct hdd_config { uint8_t fTDLSPrefOffChanBandwidth; uint8_t enable_tdls_scan; uint32_t tdls_peer_kickout_threshold; + uint32_t tdls_discovery_wake_timeout; #endif uint8_t scanAgingTimeout; uint8_t disableLDPCWithTxbfAP; @@ -16729,6 +18071,7 @@ struct hdd_config { #ifndef REMOVE_PKT_LOG bool enablePacketLog; + uint8_t pktlog_buf_size; #endif #ifdef MSM_PLATFORM @@ -16774,8 +18117,9 @@ struct hdd_config { #ifdef WLAN_FEATURE_ROAM_OFFLOAD bool isRoamOffloadEnabled; + uint32_t roam_triggers; #endif - + bool bmiss_skip_full_scan; uint32_t IpaUcTxBufCount; uint32_t IpaUcTxBufSize; uint32_t IpaUcRxIndRingCount; @@ -16792,6 +18136,9 @@ struct hdd_config { #endif #ifdef WLAN_FEATURE_NAN bool enable_nan_support; + bool nan_separate_iface_support; + uint16_t ndp_keep_alive_period; + bool support_mp0_discovery; #endif bool enableSelfRecovery; #ifdef FEATURE_WLAN_FORCE_SAP_SCC @@ -16862,6 +18209,7 @@ struct hdd_config { uint8_t ce_service_max_rx_ind_flush; uint32_t napi_cpu_affinity_mask; /* CPU affinity mask for rx_thread */ + uint32_t rx_thread_ul_affinity_mask; uint32_t rx_thread_affinity_mask; uint8_t cpu_map_list[CFG_RPS_RX_QUEUE_CPU_MAP_LIST_LEN]; #ifdef FEATURE_WLAN_EXTSCAN @@ -17001,6 +18349,7 @@ struct hdd_config { /* beacon count before channel switch */ uint8_t sap_chanswitch_beacon_cnt; uint8_t sap_chanswitch_mode; + uint32_t rx_wakelock_timeout; uint32_t max_sched_scan_plan_interval; uint32_t max_sched_scan_plan_iterations; #ifdef WLAN_FEATURE_WOW_PULSE @@ -17164,6 +18513,8 @@ struct hdd_config { uint32_t btm_solicited_timeout; uint32_t btm_max_attempt_cnt; uint32_t btm_sticky_time; + uint32_t btm_query_bitmask; + uint32_t btm_trig_min_candidate_score; bool gcmp_enabled; bool is_11k_offload_supported; uint32_t offload_11k_enable_bitmask; @@ -17204,6 +18555,13 @@ struct hdd_config { #ifdef WLAN_FEATURE_ROAM_OFFLOAD uint32_t roam_preauth_retry_count; uint32_t roam_preauth_no_ack_timeout; + bool enable_disconnect_roam_offload; + bool enable_idle_roam; + uint32_t idle_roam_rssi_delta; + uint32_t idle_roam_inactive_time; + uint32_t idle_data_packet_count; + uint32_t idle_roam_band; + int32_t idle_roam_min_rssi; #endif uint32_t num_tx_chains_2g; uint32_t num_tx_chains_5g; @@ -17227,6 +18585,7 @@ struct hdd_config { uint8_t enable_rtt_support; uint32_t roam_score_delta; + uint32_t min_roam_score_delta; uint32_t roam_score_delta_bitmap; bool prefer_btm_query; bool btm_abridge_config; @@ -17235,11 +18594,58 @@ struct hdd_config { bool enable_bss_load_roam_trigger; uint32_t bss_load_threshold; uint32_t bss_load_sample_time; + int32_t bss_load_trigger_rssi_threshold_5ghz; + int32_t bss_load_trigger_rssi_threshold_24ghz; + uint32_t roam_scan_inactivity_time; + uint32_t roam_inactive_data_packet_count; + uint32_t roam_scan_period_after_inactivity; + int32_t disconnect_roam_min_rssi; + int32_t bmiss_roam_min_rssi; + uint32_t btm_roam_score_delta; + uint32_t idle_roam_score_delta; bool enable_beacon_reception_stats; bool ignore_fw_reg_offload_ind; + bool enable_pending_list_req; uint32_t roam_full_scan_period; + uint16_t ndp_inactivity_timeout; + uint8_t mgmt_retry_max; + uint8_t enable_ring_buffer; +#ifdef WLAN_ADAPTIVE_11R + bool enable_adaptive_11r; +#endif +#if defined(WLAN_SAE_SINGLE_PMK) && defined(WLAN_FEATURE_ROAM_OFFLOAD) + bool sae_single_pmk_feature_enabled; +#endif + uint32_t num_vdevs; + bool ShortGI80MhzEnable; + bool ShortGI160MhzEnable; + uint32_t vendor_roam_score_algorithm; + uint32_t dp_proto_event_bitmap; + +#ifdef SAR_SAFETY_FEATURE + uint32_t sar_safety_timeout; + uint32_t sar_safety_unsolicited_timeout; + uint32_t sar_safety_req_resp_timeout; + uint32_t sar_safety_req_resp_retry; + uint32_t sar_safety_index; + uint32_t sar_safety_sleep_index; + bool enable_sar_safety; + bool config_sar_safety_sleep_index; +#endif + uint32_t pkt_capture_mode; + + uint32_t mws_coex_scc_channel_avoid_delay; + uint32_t mws_coex_pcc_channel_avoid_delay; + + bool disable_4way_hs_offload; +#ifdef FEATURE_WLAN_TIME_SYNC_FTM + bool time_sync_ftm_enable; + bool time_sync_ftm_mode; + bool time_sync_ftm_role; +#endif + bool p2p_disable_roam; }; #define VAR_OFFSET(_Struct, _Var) (offsetof(_Struct, _Var)) diff --git a/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_ftm_time_sync.h b/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_ftm_time_sync.h new file mode 100644 index 000000000000..24468fe855ab --- /dev/null +++ b/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_ftm_time_sync.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include "ftm_time_sync_ucfg_api.h" +#include "wlan_hdd_main.h" + +#ifdef FEATURE_WLAN_TIME_SYNC_FTM +/** + * hdd_ftm_time_sync_sta_state_notify() - notify FTM TIME SYNC sta state change + * @adapter: pointer to adapter + * @state: enum ftm_time_sync_sta_state + * + * This function is called by hdd connect and disconnect handler and notifies + * the FTM TIME SYNC component about the sta state. + * + * Return: None + */ +void +hdd_ftm_time_sync_sta_state_notify(struct hdd_adapter *adapter, + enum ftm_time_sync_sta_state state); + +#else + +static inline void +hdd_ftm_time_sync_sta_state_notify(struct hdd_adapter *adapter, + enum ftm_time_sync_sta_state state) +{ +} + +#endif diff --git a/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_main.h b/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_main.h index 2656b7852103..d428c9c9f143 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_main.h +++ b/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_main.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -95,6 +95,7 @@ #include "wlan_hdd_nud_tracking.h" #include "wlan_hdd_twt.h" #include "wma_sar_public_structs.h" +#include "wlan_mlme_ucfg_api.h" /* * Preprocessor definitions and constants @@ -125,6 +126,8 @@ struct hdd_apf_context { }; #endif /* FEATURE_WLAN_APF */ +#define ACS_COMPLETE_TIMEOUT 3000 + /** Number of Tx Queues */ #if defined(QCA_LL_TX_FLOW_CONTROL_V2) || defined(QCA_LL_PDEV_TX_FLOW_CONTROL) #define NUM_TX_QUEUES 5 @@ -325,6 +328,17 @@ enum hdd_driver_flags { #define hdd_info(params...) QDF_TRACE_INFO(QDF_MODULE_ID_HDD, params) #define hdd_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_HDD, params) +#define hdd_nofl_alert(params...) \ + QDF_TRACE_FATAL_NO_FL(QDF_MODULE_ID_HDD, params) +#define hdd_nofl_err(params...) \ + QDF_TRACE_ERROR_NO_FL(QDF_MODULE_ID_HDD, params) +#define hdd_nofl_warn(params...) \ + QDF_TRACE_WARN_NO_FL(QDF_MODULE_ID_HDD, params) +#define hdd_nofl_info(params...) \ + QDF_TRACE_INFO_NO_FL(QDF_MODULE_ID_HDD, params) +#define hdd_nofl_debug(params...) \ + QDF_TRACE_DEBUG_NO_FL(QDF_MODULE_ID_HDD, params) + #define hdd_alert_rl(params...) QDF_TRACE_FATAL_RL(QDF_MODULE_ID_HDD, params) #define hdd_err_rl(params...) QDF_TRACE_ERROR_RL(QDF_MODULE_ID_HDD, params) #define hdd_warn_rl(params...) QDF_TRACE_WARN_RL(QDF_MODULE_ID_HDD, params) @@ -481,6 +495,8 @@ extern struct mutex hdd_init_deinit_lock; #define NUM_TX_RX_HISTOGRAM_MASK (NUM_TX_RX_HISTOGRAM - 1) +#define HDD_NOISE_FLOOR_DBM (-96) + /** * enum hdd_auth_key_mgmt - auth key mgmt protocols * @HDD_AUTH_KEY_MGMT_802_1X: 802.1x @@ -1017,6 +1033,7 @@ enum dhcp_nego_status { * @capability: Capability information of current station * @support_mode: Max supported mode of a station currently * connected to sap + * @assoc_req_ies: Assoc request IEs of the peer station */ struct hdd_station_info { bool in_use; @@ -1062,6 +1079,7 @@ struct hdd_station_info { enum dhcp_nego_status dhcp_nego_status; uint16_t capability; uint8_t support_mode; + struct wlan_ies assoc_req_ies; }; /** @@ -1230,6 +1248,9 @@ struct hdd_context; * @vdev: object manager vdev context * @vdev_lock: lock to protect vdev context access * @event_flags: a bitmap of hdd_adapter_flags + * @acs_complete_event: acs complete event + * @last_disconnect_reason: Last disconnected internal reason code + * as per enum qca_disconnect_reason_codes */ struct hdd_adapter { /* Magic cookie for adapter sanity verification. Note that this @@ -1293,6 +1314,7 @@ struct hdd_adapter { /* QDF event for session close */ qdf_event_t qdf_session_close_event; + qdf_event_t acs_complete_event; /* QDF event for session open */ qdf_event_t qdf_session_open_event; @@ -1416,7 +1438,7 @@ struct hdd_adapter { bool offloads_configured; /* DSCP to UP QoS Mapping */ - enum sme_qos_wmmuptype dscp_to_up_map[WLAN_HDD_MAX_DSCP + 1]; + enum sme_qos_wmmuptype dscp_to_up_map[WLAN_MAX_DSCP + 1]; #ifdef WLAN_FEATURE_LINK_LAYER_STATS bool is_link_layer_stats_set; @@ -1482,6 +1504,7 @@ struct hdd_adapter { #ifdef WLAN_DEBUGFS struct hdd_debugfs_file_info csr_file[HDD_DEBUGFS_FILE_ID_MAX]; #endif /* WLAN_DEBUGFS */ + enum qca_disconnect_reason_codes last_disconnect_reason; }; #define WLAN_HDD_GET_STATION_CTX_PTR(adapter) (&(adapter)->session.station) @@ -1833,6 +1856,7 @@ struct hdd_context { /** P2P Device MAC Address for the adapter */ struct qdf_mac_addr p2p_device_address; + qdf_wake_lock_t rx_wake_lock; qdf_wake_lock_t sap_wake_lock; void *hdd_ipa; @@ -1848,7 +1872,7 @@ struct hdd_context { qdf_spinlock_t bus_bw_timer_lock; struct work_struct bus_bw_work; int cur_vote_level; - spinlock_t bus_bw_lock; + qdf_spinlock_t bus_bw_lock; int cur_rx_level; uint64_t prev_no_rx_offload_pkts; uint64_t prev_rx_offload_pkts; @@ -2059,6 +2083,14 @@ struct hdd_context { unsigned long derived_intf_addr_mask; struct wlan_mlme_chain_cfg fw_chain_cfg; struct sar_limit_cmd_params *sar_cmd_params; + bool nan_seperate_vdev_supported; + +#ifdef SAR_SAFETY_FEATURE + qdf_mc_timer_t sar_safety_timer; + qdf_mc_timer_t sar_safety_unsolicited_timer; + qdf_event_t sar_safety_req_resp_event; +#endif + bool roam_ch_from_fw_supported; }; /** @@ -2158,25 +2190,133 @@ int hdd_validate_channel_and_bandwidth(struct hdd_adapter *adapter, const char *hdd_device_mode_to_string(uint8_t device_mode); +/** + * hdd_get_front_adapter() - Get the first adapter from the adapter list + * @hdd_ctx: pointer to the HDD context + * @current_adapter: pointer to the current adapter + * @out_adapter: double pointer to pass the next adapter + * + * Return: QDF_STATUS + */ QDF_STATUS hdd_get_front_adapter(struct hdd_context *hdd_ctx, struct hdd_adapter **out_adapter); +/** + * hdd_get_next_adapter() - Get the next adapter from the adapter list + * @hdd_ctx: pointer to the HDD context + * @current_adapter: pointer to the current adapter + * @out_adapter: double pointer to pass the next adapter + * + * Return: QDF_STATUS + */ QDF_STATUS hdd_get_next_adapter(struct hdd_context *hdd_ctx, struct hdd_adapter *current_adapter, struct hdd_adapter **out_adapter); +/** + * hdd_get_front_adapter_no_lock() - Get the first adapter from the adapter list + * This API doesnot use any lock in it's implementation. It is the caller's + * directive to ensure concurrency safety. + * @hdd_ctx: pointer to the HDD context + * @out_adapter: double pointer to pass the next adapter + * + * Return: QDF_STATUS + */ +QDF_STATUS hdd_get_front_adapter_no_lock(struct hdd_context *hdd_ctx, + struct hdd_adapter **out_adapter); + +/** + * hdd_get_next_adapter_no_lock() - Get the next adapter from the adapter list + * This API doesnot use any lock in it's implementation. It is the caller's + * directive to ensure concurrency safety. + * @hdd_ctx: pointer to the HDD context + * @current_adapter: pointer to the current adapter + * @out_adapter: double pointer to pass the next adapter + * + * Return: QDF_STATUS + */ +QDF_STATUS hdd_get_next_adapter_no_lock(struct hdd_context *hdd_ctx, + struct hdd_adapter *current_adapter, + struct hdd_adapter **out_adapter); + +/** + * hdd_remove_adapter() - Remove the adapter from the adapter list + * @hdd_ctx: pointer to the HDD context + * @adapter: pointer to the adapter to be removed + * + * Return: QDF_STATUS + */ QDF_STATUS hdd_remove_adapter(struct hdd_context *hdd_ctx, struct hdd_adapter *adapter); +/** + * hdd_remove_front_adapter() - Remove the first adapter from the adapter list + * @hdd_ctx: pointer to the HDD context + * @out_adapter: pointer to the adapter to be removed + * + * Return: QDF_STATUS + */ QDF_STATUS hdd_remove_front_adapter(struct hdd_context *hdd_ctx, struct hdd_adapter **out_adapter); +/** + * hdd_add_adapter_back() - Add an adapter to the adapter list + * @hdd_ctx: pointer to the HDD context + * @adapter: pointer to the adapter to be added + * + * Return: QDF_STATUS + */ QDF_STATUS hdd_add_adapter_back(struct hdd_context *hdd_ctx, struct hdd_adapter *adapter); +/** + * hdd_add_adapter_front() - Add an adapter to the head of the adapter list + * @hdd_ctx: pointer to the HDD context + * @adapter: pointer to the adapter to be added + * + * Return: QDF_STATUS + */ QDF_STATUS hdd_add_adapter_front(struct hdd_context *hdd_ctx, struct hdd_adapter *adapter); +/** + * typedef hdd_adapter_iterate_cb() – Iteration callback function + * @adapter: current adapter of interest + * @context: user context supplied to the iterator + * + * This specifies the type of a callback function to supply to + * hdd_adapter_iterate(). + * + * Return: + * * QDF_STATUS_SUCCESS if further iteration should continue + * * QDF_STATUS_E_ABORTED if further iteration should be aborted + */ +typedef QDF_STATUS (*hdd_adapter_iterate_cb)(struct hdd_adapter *adapter, + void *context); + +/** + * hdd_adapter_iterate() – Safely iterate over all adapters + * @cb: callback function to invoke for each adapter + * @context: user-supplied context to pass to @cb + * + * This function will iterate over all of the adapters known to the system in + * a safe manner, invoking the callback function for each adapter. + * The callback function will be invoked in the same context/thread as the + * caller without any additional locks in force. + * Iteration continues until either the callback has been invoked for all + * adapters or a callback returns a value of QDF_STATUS_E_ABORTED to indicate + * that further iteration should cease. + * + * Return: + * * QDF_STATUS_E_ABORTED if any callback function returns that value + * * QDF_STATUS_E_FAILURE if the callback was not invoked for all adapters due + * to concurrency (i.e. adapter was deleted while iterating) + * * QDF_STATUS_SUCCESS if @cb was invoked for each adapter and none returned + * an error + */ +QDF_STATUS hdd_adapter_iterate(hdd_adapter_iterate_cb cb, + void *context); + /** * hdd_for_each_adapter - adapter iterator macro * @hdd_ctx: the global HDD context @@ -2187,6 +2327,76 @@ QDF_STATUS hdd_add_adapter_front(struct hdd_context *hdd_ctx, adapter; \ hdd_get_next_adapter(hdd_ctx, adapter, &adapter)) +/** + * __hdd_take_ref_and_fetch_front_adapter - Helper macro to lock, fetch front + * adapter, take ref and unlock. + * @hdd_ctx: the global HDD context + * @adapter: an hdd_adapter pointer to use as a cursor + */ +#define __hdd_take_ref_and_fetch_front_adapter(hdd_ctx, adapter) \ + qdf_spin_lock_bh(&hdd_ctx->hdd_adapter_lock), \ + hdd_get_front_adapter_no_lock(hdd_ctx, &adapter), \ + (adapter) ? dev_hold(adapter->dev) : (false), \ + qdf_spin_unlock_bh(&hdd_ctx->hdd_adapter_lock) + +/** + * __hdd_take_ref_and_fetch_next_adapter - Helper macro to lock, fetch next + * adapter, take ref and unlock. + * @hdd_ctx: the global HDD context + * @adapter: an hdd_adapter pointer to use as a cursor + */ +#define __hdd_take_ref_and_fetch_next_adapter(hdd_ctx, adapter) \ + qdf_spin_lock_bh(&hdd_ctx->hdd_adapter_lock), \ + hdd_get_next_adapter_no_lock(hdd_ctx, adapter, &adapter), \ + (adapter) ? dev_hold(adapter->dev) : (false), \ + qdf_spin_unlock_bh(&hdd_ctx->hdd_adapter_lock) + +/** + * __hdd_is_adapter_valid - Helper macro to return true/false for valid adapter. + * @adapter: an hdd_adapter pointer to use as a cursor + */ +#define __hdd_is_adapter_valid(_adapter) !!_adapter + +/** + * hdd_for_each_adapter_dev_held - Adapter iterator with dev_hold called + * @hdd_ctx: the global HDD context + * @adapter: an hdd_adapter pointer to use as a cursor + * + * This iterator will take the reference of the netdev associated with the + * given adapter so as to prevent it from being removed in other context. + * If the control goes inside the loop body then the dev_hold has been invoked. + * + * ***** NOTE ***** + * Before the end of each iteration, dev_put(adapter->dev) must be + * called. Not calling this will keep hold of a reference, thus preventing + * unregister of the netdevice. + * + * Usage example: + * hdd_for_each_adapter_dev_held(hdd_ctx, adapter) { + * + * + * dev_put(adapter->dev) + * } + */ +#define hdd_for_each_adapter_dev_held(hdd_ctx, adapter) \ + for (__hdd_take_ref_and_fetch_front_adapter(hdd_ctx, adapter); \ + __hdd_is_adapter_valid(adapter); \ + __hdd_take_ref_and_fetch_next_adapter(hdd_ctx, adapter)) + +/** + * wlan_hdd_get_adapter_by_vdev_id_from_objmgr() - Fetch adapter from objmgr + * using vdev_id. + * @hdd_ctx: the global HDD context + * @adapter: an hdd_adapter double pointer to store the address of the adapter + * @vdev: the vdev whose corresponding adapter has to be fetched + * + * Return: QDF_STATUS + */ +QDF_STATUS +wlan_hdd_get_adapter_by_vdev_id_from_objmgr(struct hdd_context *hdd_ctx, + struct hdd_adapter **adapter, + struct wlan_objmgr_vdev *vdev); + struct hdd_adapter *hdd_open_adapter(struct hdd_context *hdd_ctx, uint8_t session_type, const char *name, tSirMacAddr macAddr, @@ -2202,6 +2412,31 @@ QDF_STATUS hdd_reset_all_adapters(struct hdd_context *hdd_ctx); QDF_STATUS hdd_start_all_adapters(struct hdd_context *hdd_ctx); struct hdd_adapter *hdd_get_adapter_by_vdev(struct hdd_context *hdd_ctx, uint32_t vdev_id); + +/** + * hdd_adapter_get_by_reference() - Return adapter with the given reference + * @hdd_ctx: hdd context + * @reference: reference for the adapter to get + * + * This function is used to get the adapter with provided reference. + * The adapter reference will be held until being released by calling + * hdd_adapter_put(). + * + * Return: adapter pointer if found + * + */ +struct hdd_adapter *hdd_adapter_get_by_reference(struct hdd_context *hdd_ctx, + struct hdd_adapter *reference); + +/** + * hdd_adapter_put() - Release reference to adapter + * @adapter: adapter reference + * + * Release reference to adapter previously acquired via + * hdd_adapter_get_*() function + */ +void hdd_adapter_put(struct hdd_adapter *adapter); + struct hdd_adapter *hdd_get_adapter_by_macaddr(struct hdd_context *hdd_ctx, tSirMacAddr macAddr); @@ -2344,6 +2579,27 @@ bool wlan_hdd_validate_modules_state(struct hdd_context *hdd_ctx); QDF_STATUS __wlan_hdd_validate_mac_address(struct qdf_mac_addr *mac_addr, const char *func); #ifdef MSM_PLATFORM +/** + * hdd_bus_bw_compute_prev_txrx_stats() - get tx and rx stats + * @adapter: hdd adapter reference + * + * This function get the collected tx and rx stats before starting + * the bus bandwidth timer. + * + * Return: None + */ +void hdd_bus_bw_compute_prev_txrx_stats(struct hdd_adapter *adapter); + +/** + * hdd_bus_bw_compute_reset_prev_txrx_stats() - reset previous tx and rx stats + * @adapter: hdd adapter reference + * + * This function resets the adapter previous tx rx stats. + * + * Return: None + */ +void hdd_bus_bw_compute_reset_prev_txrx_stats(struct hdd_adapter *adapter); + /** * hdd_bus_bw_compute_timer_start() - start the bandwidth timer * @hdd_ctx: the global hdd context @@ -2407,6 +2663,16 @@ void hdd_bus_bandwidth_deinit(struct hdd_context *hdd_ctx); #else +static inline +void hdd_bus_bw_compute_prev_txrx_stats(struct hdd_adapter *adapter) +{ +} + +static inline +void hdd_bus_bw_compute_reset_prev_txrx_stats(struct hdd_adapter *adapter) +{ +} + static inline void hdd_bus_bw_compute_timer_start(struct hdd_context *hdd_ctx) { @@ -3733,4 +3999,82 @@ void hdd_psoc_idle_timer_start(struct hdd_context *hdd_ctx); * Return: None */ void hdd_psoc_idle_timer_stop(struct hdd_context *hdd_ctx); + +#ifdef WLAN_FEATURE_PKT_CAPTURE + +/** + * wlan_hdd_is_session_type_monitor() - check if session type is MONITOR + * @session_type: session type + * + * Return: True - if session type for adapter is monitor, else False + * + */ +bool wlan_hdd_is_session_type_monitor(uint8_t session_type); + +/** + * wlan_hdd_check_mon_concurrency() - check if MONITOR and STA concurrency + * is UP when packet capture mode is enabled. + * + * Return: True - if STA and monitor concurrency is there, else False + * + */ +bool wlan_hdd_check_mon_concurrency(void); + +/** + * wlan_hdd_add_monitor_check() - check for monitor intf and add if needed + * @hdd_ctx: pointer to hdd context + * @adapter: output pointer to hold created monitor adapter + * @type: type of the interface + * @name: name of the interface + * @rtnl_held: True if RTNL lock is held + * @name_assign_type: the name of assign type of the netdev + * + * Return: 0 - on success + * err code - on failure + */ +int wlan_hdd_add_monitor_check(struct hdd_context *hdd_ctx, + struct hdd_adapter **adapter, + enum nl80211_iftype type, const char *name, + bool rtnl_held, unsigned char name_assign_type); + +/** + * wlan_hdd_del_monitor() - delete monitor interface + * @hdd_ctx: pointer to hdd context + * @adapter: adapter to be deleted + * @rtnl_held: rtnl lock held + * + * This function is invoked to delete monitor interface. + * + * Return: None + */ +void wlan_hdd_del_monitor(struct hdd_context *hdd_ctx, + struct hdd_adapter *adapter, bool rtnl_held); +#else +static inline +bool wlan_hdd_is_session_type_monitor(uint8_t session_type) +{ + return false; +} + +static inline +bool wlan_hdd_check_mon_concurrency(void) +{ + return false; +} + +static inline +int wlan_hdd_add_monitor_check(struct hdd_context *hdd_ctx, + struct hdd_adapter **adapter, + enum nl80211_iftype type, const char *name, + bool rtnl_held, unsigned char name_assign_type) +{ + return 0; +} + +static inline +void wlan_hdd_del_monitor(struct hdd_context *hdd_ctx, + struct hdd_adapter *adapter, bool rtnl_held) +{ +} +#endif /* WLAN_FEATURE_PKT_CAPTURE */ #endif /* end #if !defined(WLAN_HDD_MAIN_H) */ diff --git a/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_nan.h b/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_nan.h index 93ec1153fecf..721151d48819 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_nan.h +++ b/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_nan.h @@ -51,6 +51,22 @@ static inline bool wlan_hdd_nan_is_supported(struct hdd_context *hdd_ctx) sme_is_feature_supported_by_fw(NAN); } +/** + * wlan_hdd_nan_separate_iface_supported() - HDD separate iface for NAN support + * query function + * @hdd_ctx: Pointer to hdd context + * + * This function is called to determine to whether separate iface for NAN is + * enabled or not through INI + * + * Return: true if supported by the driver and firmware + */ +static inline bool +wlan_hdd_nan_separate_iface_supported(struct hdd_context *hdd_ctx) +{ + return hdd_ctx->config->nan_separate_iface_support; +} + /** * hdd_nan_populate_cds_config() - Populate NAN cds configuration * @cds_cfg: CDS Configuration @@ -62,6 +78,8 @@ static inline void hdd_nan_populate_cds_config(struct cds_config_info *cds_cfg, struct hdd_context *hdd_ctx) { cds_cfg->is_nan_enabled = hdd_ctx->config->enable_nan_support; + cds_cfg->nan_separate_iface_support = + hdd_ctx->config->nan_separate_iface_support; } /** @@ -95,6 +113,12 @@ static inline bool wlan_hdd_nan_is_supported(struct hdd_context *hdd_ctx) { return false; } +static inline bool +wlan_hdd_nan_separate_iface_supported(struct hdd_context *hdd_ctx) +{ + return false; +} + static inline void hdd_nan_populate_cds_config(struct cds_config_info *cds_cfg, struct hdd_context *hdd_ctx) { diff --git a/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_oemdata.h b/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_oemdata.h index c8cd09d56d16..f4d6b560ae42 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_oemdata.h +++ b/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_oemdata.h @@ -25,6 +25,8 @@ #ifndef __WLAN_HDD_OEM_DATA_H__ #define __WLAN_HDD_OEM_DATA_H__ +#include "wmi_unified_param.h" + struct hdd_context; #ifdef FEATURE_OEM_DATA_SUPPORT @@ -46,7 +48,7 @@ struct hdd_context; #define OEM_CAP_MAX_NUM_CHANNELS 128 /** - * typedef eOemErrorCode - OEM error codes + * enum oem_err_code - OEM error codes * @OEM_ERR_NULL_CONTEXT: %NULL context * @OEM_ERR_APP_NOT_REGISTERED: OEM App is not registered * @OEM_ERR_INVALID_SIGNATURE: Invalid signature @@ -219,4 +221,47 @@ static inline void hdd_update_channel_bw_info(struct hdd_context *hdd_ctx, uint16_t chan, void *hdd_chan_info) {} #endif /* FEATURE_OEM_DATA_SUPPORT */ + +#ifdef FEATURE_OEM_DATA +#define OEM_DATA_MAX_SIZE 1024 +/** + * wlan_hdd_cfg80211_oem_data_handler() - the handler for oem data + * @wiphy: wiphy structure pointer + * @wdev: Wireless device structure pointer + * @data: Pointer to the data received + * @data_len: Length of @data + * + * Return: 0 on success; errno on failure + */ +int wlan_hdd_cfg80211_oem_data_handler(struct wiphy *wiphy, + struct wireless_dev *wdev, + const void *data, int data_len); + +#define FEATURE_OEM_DATA_VENDOR_COMMANDS \ +{ \ + .info.vendor_id = QCA_NL80211_VENDOR_ID, \ + .info.subcmd = QCA_NL80211_VENDOR_SUBCMD_OEM_DATA, \ + .flags = WIPHY_VENDOR_CMD_NEED_WDEV | \ + WIPHY_VENDOR_CMD_NEED_NETDEV | \ + WIPHY_VENDOR_CMD_NEED_RUNNING, \ + .doit = wlan_hdd_cfg80211_oem_data_handler \ +}, +#else +#define FEATURE_OEM_DATA_VENDOR_COMMANDS +#endif + +#ifdef FEATURE_OEM_DATA +/** + * hdd_oem_event_handler_cb() - callback for oem data event + * @oem_event_data: oem data received in the event from the FW + * + * Return: None + */ +void hdd_oem_event_handler_cb(const struct oem_data *oem_event_data); +#else +static inline void hdd_oem_event_handler_cb(void *oem_event_data) +{ +} +#endif + #endif /* __WLAN_HDD_OEM_DATA_H__ */ diff --git a/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_power.h b/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_power.h index fc8f4847c300..e8675af1ed2e 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_power.h +++ b/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_power.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012, 2014-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2012, 2014-2019 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -126,6 +126,18 @@ struct pkt_filter_cfg { #endif +#ifdef FEATURE_ANI_LEVEL_REQUEST +/** + * ani_priv - structure to store the priv data for get ani request + * @num_freq: number of freq received from the FW + * @ani: data received from the FW + */ +struct ani_priv { + uint32_t num_freq; + struct wmi_host_ani_level_event *ani; +}; +#endif + /** * enum suspend_resume_state - Suspend resume state * @HDD_WLAN_EARLY_SUSPEND: Early suspend state. @@ -506,4 +518,20 @@ hdd_wlan_fake_apps_suspend(struct wiphy *wiphy, struct net_device *dev, return 0; } #endif /* WLAN_SUSPEND_RESUME_TEST */ + +#ifdef FEATURE_ANI_LEVEL_REQUEST +/** + * wlan_hdd_get_ani_level() - Wrapper to call API to fetch ani level + * @adapter: pointer to HDD adapter + * @ani: pointer to structure storing ani level for channels + * @parsed_freqs: parsed freqs from the get ani command + * @num_freqs: number of parsed channels + * + * Return: QDF_STATUS + */ +QDF_STATUS wlan_hdd_get_ani_level(struct hdd_adapter *adapter, + struct wmi_host_ani_level_event *ani, + uint32_t *parsed_freqs, + uint8_t num_freqs); +#endif /* FEATURE_ANI_LEVEL_REQUEST */ #endif /* __WLAN_HDD_POWER_H */ diff --git a/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_regulatory.h b/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_regulatory.h index f08a14be1724..d0cc60428597 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_regulatory.h +++ b/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_regulatory.h @@ -32,6 +32,14 @@ struct hdd_context; #define IEEE80211_CHAN_NO_IBSS IEEE80211_CHAN_NO_IR #endif +/** + * hdd_update_regulatory_config() - API to update regulatory config parameters + * @hdd_ctx: HDD context + * + * Return: 0 on success, err on failure + */ +int hdd_update_regulatory_config(struct hdd_context *hdd_ctx); + int hdd_regulatory_init(struct hdd_context *hdd_ctx, struct wiphy *wiphy); void hdd_program_country_code(struct hdd_context *hdd_ctx); void hdd_reset_global_reg_params(void); diff --git a/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_softap_tx_rx.h b/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_softap_tx_rx.h index 17e0ad5e204d..75c007ba05b6 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_softap_tx_rx.h +++ b/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_softap_tx_rx.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2014-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -241,17 +241,15 @@ int hdd_post_dhcp_ind(struct hdd_adapter *adapter, uint8_t sta_id, uint16_t type); /** - * hdd_inspect_dhcp_packet() - Inspect DHCP packet + * hdd_softap_inspect_dhcp_packet() - Inspect DHCP packet * @adapter: pointer to hdd adapter - * @sta_id: peer station ID * @skb: pointer to OS packet (sk_buff) * @dir: direction * * Return: error number */ -int hdd_inspect_dhcp_packet(struct hdd_adapter *adapter, - uint8_t sta_id, - struct sk_buff *skb, - enum qdf_proto_dir dir); +int hdd_softap_inspect_dhcp_packet(struct hdd_adapter *adapter, + struct sk_buff *skb, + enum qdf_proto_dir dir); #endif /* end #if !defined(WLAN_HDD_SOFTAP_TX_RX_H) */ diff --git a/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_tx_rx.h b/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_tx_rx.h index ffc55992befa..0441948f8784 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_tx_rx.h +++ b/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_tx_rx.h @@ -184,12 +184,30 @@ void wlan_hdd_netif_queue_control(struct hdd_adapter *adapter, #ifdef FEATURE_MONITOR_MODE_SUPPORT int hdd_set_mon_rx_cb(struct net_device *dev); + +/** + * hdd_mon_rx_packet_cbk() - Receive callback registered with OL layer. + * @context: pointer to qdf context + * @rxBuf: pointer to rx qdf_nbuf + * + * TL will call this to notify the HDD when one or more packets were + * received for a registered STA. + * + * Return: QDF_STATUS + */ +QDF_STATUS hdd_mon_rx_packet_cbk(void *context, qdf_nbuf_t rxbuf); #else static inline int hdd_set_mon_rx_cb(struct net_device *dev) { return 0; } + +static inline +QDF_STATUS hdd_mon_rx_packet_cbk(void *context, qdf_nbuf_t rxbuf) +{ + return QDF_STATUS_SUCCESS; +} #endif void hdd_send_rps_ind(struct hdd_adapter *adapter); diff --git a/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_wmm.h b/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_wmm.h index 6a5b0b7b6945..7fbe08379e5c 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_wmm.h +++ b/drivers/staging/qcacld-3.0/core/hdd/inc/wlan_hdd_wmm.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2012,2016-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2012, 2016-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -194,8 +194,6 @@ extern const uint8_t hdd_qdisc_ac_to_tl_ac[]; extern const uint8_t hdd_wmm_up_to_ac_map[]; extern const uint8_t hdd_linux_up_to_ac_map[]; -#define WLAN_HDD_MAX_DSCP 0x3f - /** * hdd_wmmps_helper() - Function to set uapsd psb dynamically * @@ -206,6 +204,17 @@ extern const uint8_t hdd_linux_up_to_ac_map[]; */ int hdd_wmmps_helper(struct hdd_adapter *adapter, uint8_t *ptr); +/** + * hdd_send_dscp_up_map_to_fw() - send dscp to up map to FW + * @adapter : [in] pointer to Adapter context + * + * This function will send the WMM DSCP configuration of an + * adapter to FW. + * + * Return: QDF_STATUS enumeration + */ +QDF_STATUS hdd_send_dscp_up_map_to_fw(struct hdd_adapter *adapter); + /** * hdd_wmm_init() - initialize the WMM DSCP configuation * @adapter : [in] pointer to Adapter context diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_apf.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_apf.c index 74a509d179db..fa8c3c5b9b2f 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_apf.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_apf.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -226,8 +226,6 @@ static int hdd_set_reset_apf_offload(struct hdd_context *hdd_ctx, int prog_len; int ret = 0; - hdd_enter(); - if (!hdd_conn_is_connected( WLAN_HDD_GET_STATION_CTX_PTR(adapter))) { hdd_err("Not in Connected state!"); @@ -243,7 +241,7 @@ static int hdd_set_reset_apf_offload(struct hdd_context *hdd_ctx, apf_set_offload.total_length = nla_get_u32(tb[APF_PACKET_SIZE]); if (!apf_set_offload.total_length) { - hdd_debug("APF reset packet filter received"); + hdd_debug("APF reset packet"); goto post_sme; } @@ -267,10 +265,6 @@ static int hdd_set_reset_apf_offload(struct hdd_context *hdd_ctx, nla_memcpy(apf_set_offload.program, tb[APF_PROGRAM], prog_len); apf_set_offload.session_id = adapter->session_id; - hdd_debug("APF set instructions"); - QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_HDD, QDF_TRACE_LEVEL_DEBUG, - apf_set_offload.program, prog_len); - /* Parse and fetch filter Id */ if (!tb[APF_FILTER_ID]) { hdd_err("attr filter id failed"); @@ -288,7 +282,7 @@ static int hdd_set_reset_apf_offload(struct hdd_context *hdd_ctx, apf_set_offload.current_offset = nla_get_u32(tb[APF_CURRENT_OFFSET]); post_sme: - hdd_debug("Posting APF SET/RESET to SME, session_id: %d APF Version: %d filter ID: %d total_length: %d current_length: %d current offset: %d", + hdd_debug("Posting, session_id: %d APF Version: %d filter ID: %d total_len: %d current_len: %d offset: %d", apf_set_offload.session_id, apf_set_offload.version, apf_set_offload.filter_id, apf_set_offload.total_length, apf_set_offload.current_length, @@ -325,8 +319,6 @@ hdd_enable_disable_apf(struct hdd_adapter *adapter, bool apf_enable) { QDF_STATUS status; - hdd_enter(); - status = sme_set_apf_enable_disable(hdd_adapter_get_mac_handle(adapter), adapter->session_id, apf_enable); if (!QDF_IS_STATUS_SUCCESS(status)) { @@ -337,7 +329,6 @@ hdd_enable_disable_apf(struct hdd_adapter *adapter, bool apf_enable) adapter->apf_context.apf_enabled = apf_enable; - hdd_exit(); return 0; } @@ -359,9 +350,6 @@ hdd_apf_write_memory(struct hdd_adapter *adapter, struct nlattr **tb) QDF_STATUS status; int ret = 0; - hdd_enter(); - - write_mem_params.vdev_id = adapter->session_id; if (adapter->apf_context.apf_enabled) { hdd_err("Cannot get/set when APF interpreter is enabled"); @@ -415,7 +403,6 @@ hdd_apf_write_memory(struct hdd_adapter *adapter, struct nlattr **tb) if (write_mem_params.buf) qdf_mem_free(write_mem_params.buf); - hdd_exit(); return ret; } @@ -505,8 +492,6 @@ static int hdd_apf_read_memory(struct hdd_adapter *adapter, struct nlattr **tb) struct sk_buff *skb = NULL; uint8_t *bufptr; - hdd_enter(); - if (context->apf_enabled) { hdd_err("Cannot get/set while interpreter is enabled"); return -EINVAL; @@ -589,7 +574,6 @@ static int hdd_apf_read_memory(struct hdd_adapter *adapter, struct nlattr **tb) context->buf = NULL; } - hdd_exit(); return ret; } diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_assoc.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_assoc.c index c68650630f99..44830bae4ec5 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_assoc.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_assoc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -62,8 +62,12 @@ #include "wlan_ipa_ucfg_api.h" #include "wlan_hdd_scan.h" #include "wlan_hdd_bcn_recv.h" - +#include "wlan_mlme_main.h" #include "wlan_hdd_nud_tracking.h" +#include "wlan_mlme_ucfg_api.h" +#include "wlan_hdd_ftm_time_sync.h" +#include "wlan_pkt_capture_ucfg_api.h" + /* These are needed to recognize WPA and RSN suite types */ #define HDD_WPA_OUI_SIZE 4 #define HDD_RSN_OUI_SIZE 4 @@ -121,12 +125,16 @@ uint8_t ccp_rsn_oui_11[HDD_RSN_OUI_SIZE] = {0x00, 0x0F, 0xAC, 0x11}; uint8_t ccp_rsn_oui_12[HDD_RSN_OUI_SIZE] = {0x50, 0x6F, 0x9A, 0x02}; uint8_t ccp_rsn_oui_0b[HDD_RSN_OUI_SIZE] = {0x00, 0x0F, 0xAC, 0x0B}; uint8_t ccp_rsn_oui_0c[HDD_RSN_OUI_SIZE] = {0x00, 0x0F, 0xAC, 0x0C}; +/* FT-SUITE-B AKM */ +uint8_t ccp_rsn_oui_0d[HDD_RSN_OUI_SIZE] = {0x00, 0x0F, 0xAC, 0x0D}; /* OWE https://tools.ietf.org/html/rfc8110 */ uint8_t ccp_rsn_oui_18[HDD_RSN_OUI_SIZE] = {0x00, 0x0F, 0xAC, 0x12}; #ifdef WLAN_FEATURE_SAE +/* SAE AKM */ uint8_t ccp_rsn_oui_80[HDD_RSN_OUI_SIZE] = {0x00, 0x0F, 0xAC, 0x08}; +/* FT SAE AKM */ uint8_t ccp_rsn_oui_90[HDD_RSN_OUI_SIZE] = {0x00, 0x0F, 0xAC, 0x09}; #endif @@ -259,9 +267,12 @@ void hdd_conn_set_connection_state(struct hdd_adapter *adapter, uint32_t time_buffer_size; /* save the new connection state */ - hdd_debug("Changed conn state from old:%d to new:%d for dev %s", - hdd_sta_ctx->conn_info.connState, conn_state, - adapter->dev->name); + if (conn_state == hdd_sta_ctx->conn_info.connState) + return; + + hdd_nofl_debug("connection state changed %d --> %d for dev %s (vdev %d)", + hdd_sta_ctx->conn_info.connState, conn_state, + adapter->dev->name, adapter->session_id); hdd_tsf_notify_wlan_state_change(adapter, hdd_sta_ctx->conn_info.connState, @@ -413,7 +424,8 @@ void hdd_abort_ongoing_sta_connection(struct hdd_context *hdd_ctx) hdd_debug("Disconnecting STA on vdev: %d", sta_adapter->session_id); status = wlan_hdd_disconnect(sta_adapter, - eCSR_DISCONNECT_REASON_DEAUTH); + eCSR_DISCONNECT_REASON_DEAUTH, + eSIR_MAC_UNSPEC_FAILURE_REASON); if (QDF_IS_STATUS_ERROR(status)) { hdd_err("wlan_hdd_disconnect failed, status: %d", status); @@ -916,7 +928,8 @@ static void hdd_save_bss_info(struct hdd_adapter *adapter, } else { hdd_sta_ctx->conn_info.conn_flag.ht_present = false; } - if (roam_info->reassoc) + if (roam_info->reassoc || + hdd_is_roam_sync_in_progress(roam_info)) hdd_sta_ctx->conn_info.roam_count++; if (roam_info->hs20vendor_ie.present) { hdd_sta_ctx->conn_info.conn_flag.hs20_present = true; @@ -1066,8 +1079,9 @@ hdd_send_ft_assoc_response(struct net_device *dev, unsigned int len = 0; u8 *pFTAssocRsp = NULL; - if (pCsrRoamInfo->nAssocRspLength == 0) { - hdd_debug("assoc rsp length is 0"); + if (pCsrRoamInfo->nAssocRspLength < FT_ASSOC_RSP_IES_OFFSET) { + hdd_debug("Invalid assoc rsp length %d", + pCsrRoamInfo->nAssocRspLength); return; } @@ -1084,15 +1098,20 @@ hdd_send_ft_assoc_response(struct net_device *dev, (unsigned int)pFTAssocRsp[0], (unsigned int)pFTAssocRsp[1]); + /* Send the Assoc Resp, the supplicant needs this for initial Auth. */ + len = pCsrRoamInfo->nAssocRspLength - FT_ASSOC_RSP_IES_OFFSET; + if (len > IW_GENERIC_IE_MAX) { + hdd_err("Invalid Assoc resp length %d", len); + return; + } + wrqu.data.length = len; + /* We need to send the IEs to the supplicant. */ buff = qdf_mem_malloc(IW_GENERIC_IE_MAX); if (buff == NULL) { hdd_err("unable to allocate memory"); return; } - /* Send the Assoc Resp, the supplicant needs this for initial Auth. */ - len = pCsrRoamInfo->nAssocRspLength - FT_ASSOC_RSP_IES_OFFSET; - wrqu.data.length = len; memcpy(buff, pFTAssocRsp, len); wireless_send_event(dev, IWEVASSOCRESPIE, &wrqu, buff); @@ -1376,10 +1395,10 @@ static void hdd_send_association_event(struct net_device *dev, ucfg_p2p_status_connect(adapter->vdev); - hdd_info("%s(vdevid-%d): " MAC_ADDRESS_STR " connected to " - MAC_ADDRESS_STR, dev->name, adapter->session_id, - MAC_ADDR_ARRAY(adapter->mac_addr.bytes), - MAC_ADDR_ARRAY(wrqu.ap_addr.sa_data)); + hdd_nofl_info("%s(vdevid-%d): " MAC_ADDRESS_STR " connected to " + MAC_ADDRESS_STR, dev->name, adapter->session_id, + MAC_ADDR_ARRAY(adapter->mac_addr.bytes), + MAC_ADDR_ARRAY(wrqu.ap_addr.sa_data)); hdd_send_update_beacon_ies_event(adapter, pCsrRoamInfo); /* @@ -1392,6 +1411,10 @@ static void hdd_send_association_event(struct net_device *dev, eCSR_AUTH_TYPE_FT_RSN_PSK) || (roam_profile->AuthType.authType[0] == eCSR_AUTH_TYPE_FT_RSN) + || (roam_profile->AuthType.authType[0] == + eCSR_AUTH_TYPE_FT_SAE) + || (roam_profile->AuthType.authType[0] == + eCSR_AUTH_TYPE_FT_SUITEB_EAP_SHA384) #ifdef FEATURE_WLAN_ESE || (roam_profile->AuthType.authType[0] == eCSR_AUTH_TYPE_CCKM_RSN) @@ -1433,18 +1456,10 @@ static void hdd_send_association_event(struct net_device *dev, pCsrRoamInfo->tdls_prohibited, adapter->vdev); -#ifdef MSM_PLATFORM /* start timer in sta/p2p_cli */ - spin_lock_bh(&hdd_ctx->bus_bw_lock); - adapter->prev_tx_packets = adapter->stats.tx_packets; - adapter->prev_rx_packets = adapter->stats.rx_packets; - cdp_get_intra_bss_fwd_pkts_count( - cds_get_context(QDF_MODULE_ID_SOC), adapter->session_id, - &adapter->prev_fwd_tx_packets, - &adapter->prev_fwd_rx_packets); - spin_unlock_bh(&hdd_ctx->bus_bw_lock); + hdd_bus_bw_compute_prev_txrx_stats(adapter); hdd_bus_bw_compute_timer_start(hdd_ctx); -#endif + ucfg_pkt_capture_record_channel(); } else if (eConnectionState_IbssConnected == /* IBss Associated */ sta_ctx->conn_info.connState) { policy_mgr_update_connection_info(hdd_ctx->psoc, @@ -1455,8 +1470,8 @@ static void hdd_send_association_event(struct net_device *dev, dev->name, adapter->session_id, MAC_ADDR_ARRAY(sta_ctx->conn_info.bssId.bytes)); } else { /* Not Associated */ - hdd_info("%s(vdevid-%d): disconnected", dev->name, - adapter->session_id); + hdd_nofl_info("%s(vdevid-%d): disconnected", dev->name, + adapter->session_id); memset(wrqu.ap_addr.sa_data, '\0', ETH_ALEN); policy_mgr_decr_session_set_pcl(hdd_ctx->psoc, adapter->device_mode, adapter->session_id); @@ -1487,16 +1502,9 @@ static void hdd_send_association_event(struct net_device *dev, false, adapter->vdev); -#ifdef MSM_PLATFORM /* stop timer in sta/p2p_cli */ - spin_lock_bh(&hdd_ctx->bus_bw_lock); - adapter->prev_tx_packets = 0; - adapter->prev_rx_packets = 0; - adapter->prev_fwd_tx_packets = 0; - adapter->prev_fwd_rx_packets = 0; - spin_unlock_bh(&hdd_ctx->bus_bw_lock); + hdd_bus_bw_compute_reset_prev_txrx_stats(adapter); hdd_bus_bw_compute_timer_try_stop(hdd_ctx); -#endif } hdd_ipa_set_tx_flow_info(); @@ -1653,41 +1661,28 @@ QDF_STATUS hdd_roam_deregister_sta(struct hdd_adapter *adapter, uint8_t staid) */ static void hdd_print_bss_info(struct hdd_station_ctx *hdd_sta_ctx) { - uint32_t *cap_info; - - hdd_debug("WIFI DATA LOGGER"); - hdd_debug("channel: %d", - hdd_sta_ctx->conn_info.freq); - hdd_debug("dot11mode: %d", - hdd_sta_ctx->conn_info.dot11Mode); - hdd_debug("AKM: %d", - hdd_sta_ctx->conn_info.last_auth_type); - hdd_debug("ssid: %.*s", - hdd_sta_ctx->conn_info.last_ssid.SSID.length, - hdd_sta_ctx->conn_info.last_ssid.SSID.ssId); - hdd_debug("roam count: %d", - hdd_sta_ctx->conn_info.roam_count); - hdd_debug("ant_info: %d", - hdd_sta_ctx->conn_info.txrate.nss); - hdd_debug("datarate legacy %d", - hdd_sta_ctx->conn_info.txrate.legacy); - hdd_debug("datarate mcs: %d", - hdd_sta_ctx->conn_info.txrate.mcs); - if (hdd_sta_ctx->conn_info.conn_flag.ht_present) { - cap_info = (uint32_t *)&hdd_sta_ctx->conn_info.ht_caps; - hdd_debug("ht caps: %x", *cap_info); - } - if (hdd_sta_ctx->conn_info.conn_flag.vht_present) { - cap_info = (uint32_t *)&hdd_sta_ctx->conn_info.vht_caps; - hdd_debug("vht caps: %x", *cap_info); - } - if (hdd_sta_ctx->conn_info.conn_flag.hs20_present) - hdd_debug("hs20 info: %x", - hdd_sta_ctx->conn_info.hs20vendor_ie.release_num); - hdd_debug("signal: %d", - hdd_sta_ctx->conn_info.signal); - hdd_debug("noise: %d", - hdd_sta_ctx->conn_info.noise); + uint32_t *ht_cap_info; + uint32_t *vht_cap_info; + struct hdd_connection_info *conn_info; + + conn_info = &hdd_sta_ctx->conn_info; + + hdd_nofl_debug("*********** WIFI DATA LOGGER **************"); + hdd_nofl_debug("chan: %d dot11mode %d AKM %d ssid: \"%.*s\" ,roam_count %d nss %d legacy %d mcs %d signal %d noise: %d", + conn_info->freq, conn_info->dot11Mode, + conn_info->last_auth_type, + conn_info->last_ssid.SSID.length, + conn_info->last_ssid.SSID.ssId, conn_info->roam_count, + conn_info->txrate.nss, conn_info->txrate.legacy, + conn_info->txrate.mcs, conn_info->signal, + conn_info->noise); + ht_cap_info = (uint32_t *)&conn_info->ht_caps; + vht_cap_info = (uint32_t *)&conn_info->vht_caps; + hdd_nofl_debug("HT 0x%x VHT 0x%x ht20 info 0x%x", + conn_info->conn_flag.ht_present ? *ht_cap_info : 0, + conn_info->conn_flag.vht_present ? *vht_cap_info : 0, + conn_info->conn_flag.hs20_present ? + conn_info->hs20vendor_ie.release_num : 0); } /** @@ -1719,6 +1714,9 @@ static QDF_STATUS hdd_dis_connect_handler(struct hdd_adapter *adapter, uint8_t sta_id; bool sendDisconInd = true; mac_handle_t mac_handle; + struct wlan_ies disconnect_ies = {0}; + bool from_ap = false; + uint32_t reason_code = 0; if (dev == NULL) { hdd_err("net_dev is released return"); @@ -1769,11 +1767,15 @@ static QDF_STATUS hdd_dis_connect_handler(struct hdd_adapter *adapter, hdd_clear_roam_profile_ie(adapter); hdd_wmm_init(adapter); - hdd_debug("Invoking packetdump deregistration API"); wlan_deregister_txrx_packetdump(); - /* indicate 'disconnect' status to wpa_supplicant... */ hdd_send_association_event(dev, roam_info); + + if (hdd_ctx->config->p2p_disable_roam && + (adapter->device_mode == QDF_P2P_CLIENT_MODE)) { + hdd_debug("enable roam"); + wlan_hdd_enable_roaming(adapter); + } /* indicate disconnected event to nl80211 */ if (roamStatus != eCSR_ROAM_IBSS_LEAVE) { /* @@ -1781,29 +1783,34 @@ static QDF_STATUS hdd_dis_connect_handler(struct hdd_adapter *adapter, * by kernel */ if (sendDisconInd) { + int reason = WLAN_REASON_UNSPECIFIED; + + if (roam_info && roam_info->disconnect_ies) { + disconnect_ies.data = + roam_info->disconnect_ies->data; + disconnect_ies.len = + roam_info->disconnect_ies->len; + } /* * To avoid wpa_supplicant sending "HANGED" CMD * to ICS UI. */ - if (eCSR_ROAM_LOSTLINK == roamStatus) { - if (roam_info->reasonCode == + if (roam_info && eCSR_ROAM_LOSTLINK == roamStatus) { + reason = roam_info->reasonCode; + if (reason == eSIR_MAC_PEER_STA_REQ_LEAVING_BSS_REASON) pr_info("wlan: disconnected due to poor signal, rssi is %d dB\n", roam_info->rxRssi); - wlan_hdd_cfg80211_indicate_disconnect( - dev, false, - roam_info->reasonCode); - } else { - wlan_hdd_cfg80211_indicate_disconnect( - dev, false, - WLAN_REASON_UNSPECIFIED - ); } - - hdd_debug("sent disconnected event to nl80211, reason code %d", - (eCSR_ROAM_LOSTLINK == roamStatus) ? - roam_info->reasonCode : - WLAN_REASON_UNSPECIFIED); + ucfg_mlme_get_discon_reason_n_from_ap(hdd_ctx->psoc, + adapter->session_id, + &from_ap, + &reason_code); + wlan_hdd_cfg80211_indicate_disconnect( + adapter, !from_ap, + reason_code, + disconnect_ies.data, + disconnect_ies.len); } /* update P2P connection status */ @@ -1812,28 +1819,26 @@ static QDF_STATUS hdd_dis_connect_handler(struct hdd_adapter *adapter, hdd_wmm_adapter_clear(adapter); mac_handle = hdd_ctx->mac_handle; + sme_ft_reset(mac_handle, adapter->session_id); sme_reset_key(mac_handle, adapter->session_id); - if (!hdd_remove_beacon_filter(adapter)) { - if (sme_is_beacon_report_started(mac_handle, - adapter->session_id)) { - hdd_beacon_recv_pause_indication((hdd_handle_t)hdd_ctx, - adapter->session_id, - SCAN_EVENT_TYPE_MAX, - true); - } - } + hdd_remove_beacon_filter(adapter); + + if (sme_is_beacon_report_started(mac_handle, adapter->session_id)) { + hdd_debug("Sending beacon pause indication to userspace"); + hdd_beacon_recv_pause_indication((hdd_handle_t)hdd_ctx, + adapter->session_id, + SCAN_EVENT_TYPE_MAX, true); + } if (eCSR_ROAM_IBSS_LEAVE == roamStatus) { uint8_t i; sta_id = sta_ctx->broadcast_staid; vstatus = hdd_roam_deregister_sta(adapter, sta_id); - if (!QDF_IS_STATUS_SUCCESS(vstatus)) { - hdd_err("hdd_roam_deregister_sta() failed for staID %d Status: %d [0x%x]", - sta_id, status, status); + if (QDF_IS_STATUS_ERROR(vstatus)) status = QDF_STATUS_E_FAILURE; - } + if (sta_id < HDD_MAX_ADAPTERS) hdd_ctx->sta_to_adapter[sta_id] = NULL; else @@ -1846,11 +1851,8 @@ static QDF_STATUS hdd_dis_connect_handler(struct hdd_adapter *adapter, sta_id = sta_ctx->conn_info.staId[i]; hdd_debug("Deregister StaID %d", sta_id); vstatus = hdd_roam_deregister_sta(adapter, sta_id); - if (!QDF_IS_STATUS_SUCCESS(vstatus)) { - hdd_err("hdd_roam_deregister_sta() failed to for staID %d Status: %d [0x%x]", - sta_id, status, status); + if (QDF_IS_STATUS_ERROR(vstatus)) status = QDF_STATUS_E_FAILURE; - } /* set the staid and peer mac as 0, all other * reset are done in hdd_connRemoveConnectInfo. */ @@ -1865,8 +1867,6 @@ static QDF_STATUS hdd_dis_connect_handler(struct hdd_adapter *adapter, } } else { sta_id = sta_ctx->conn_info.staId[0]; - hdd_debug("roamResult: %d", roamResult); - /* clear scan cache for Link Lost */ if (eCSR_ROAM_RESULT_DEAUTH_IND == roamResult || eCSR_ROAM_RESULT_DISASSOC_IND == roamResult || @@ -1883,17 +1883,20 @@ static QDF_STATUS hdd_dis_connect_handler(struct hdd_adapter *adapter, else hdd_debug("invalid sta_id %d", sta_id); } + /* Clear saved connection information in HDD */ hdd_conn_remove_connect_info(sta_ctx); /* * eConnectionState_Connecting state mean that connection is in * progress so no need to set state to eConnectionState_NotConnected */ - if ((eConnectionState_Connecting != sta_ctx->conn_info.connState)) { + if (eConnectionState_Connecting != sta_ctx->conn_info.connState) hdd_conn_set_connection_state(adapter, eConnectionState_NotConnected); - hdd_set_roaming_in_progress(false); - } + + /* Clear roaming in progress flag */ + hdd_set_roaming_in_progress(false); + pmo_ucfg_flush_gtk_offload_req(adapter->vdev); if ((QDF_STA_MODE == adapter->device_mode) || @@ -1904,7 +1907,12 @@ static QDF_STATUS hdd_dis_connect_handler(struct hdd_adapter *adapter, } wlan_hdd_clear_link_layer_stats(adapter); - hdd_debug("check for SAP restart"); + if (adapter->device_mode == QDF_STA_MODE) { + /* Inform FTM TIME SYNC about the disconnection with the AP */ + hdd_ftm_time_sync_sta_state_notify( + adapter, FTM_TIME_SYNC_STA_DISCONNECTED); + } + policy_mgr_check_concurrent_intf_and_restart_sap(hdd_ctx->psoc); adapter->hdd_stats.tx_rx_stats.cont_txtimeout_cnt = 0; @@ -2254,7 +2262,7 @@ void hdd_save_gtk_params(struct hdd_adapter *adapter, kek_len = csr_roam_info->fils_join_rsp->kek_len; } - wlan_hdd_save_gtk_offload_params(adapter, NULL, kek, kek_len, + wlan_hdd_save_gtk_offload_params(adapter, NULL, 0, kek, kek_len, csr_roam_info->replay_ctr, true); hdd_debug("Kek len %d", kek_len); @@ -2273,7 +2281,7 @@ void hdd_save_gtk_params(struct hdd_adapter *adapter, kek = csr_roam_info->kek; kek_len = csr_roam_info->kek_len; - wlan_hdd_save_gtk_offload_params(adapter, NULL, kek, kek_len, + wlan_hdd_save_gtk_offload_params(adapter, NULL, 0, kek, kek_len, csr_roam_info->replay_ctr, true); hdd_debug("Kek len %d", kek_len); @@ -2326,8 +2334,9 @@ static void hdd_send_re_assoc_event(struct net_device *dev, goto done; } - if (pCsrRoamInfo->nAssocRspLength == 0) { - hdd_err("Assoc rsp length is 0"); + if (pCsrRoamInfo->nAssocRspLength < FT_ASSOC_RSP_IES_OFFSET) { + hdd_err("Invalid assoc rsp length %d", + pCsrRoamInfo->nAssocRspLength); goto done; } @@ -2360,6 +2369,10 @@ static void hdd_send_re_assoc_event(struct net_device *dev, /* Send the Assoc Resp, the supplicant needs this for initial Auth */ len = pCsrRoamInfo->nAssocRspLength - FT_ASSOC_RSP_IES_OFFSET; + if (len > IW_GENERIC_IE_MAX) { + hdd_err("Invalid Assoc resp length %d", len); + goto done; + } rspRsnLength = len; qdf_mem_copy(rspRsnIe, pFTAssocRsp, len); qdf_mem_zero(rspRsnIe + len, IW_GENERIC_IE_MAX - len); @@ -2391,9 +2404,6 @@ static void hdd_send_re_assoc_event(struct net_device *dev, qdf_mem_copy(buf_ptr, &roam_profile.SSID.ssId[0], roam_profile.SSID.length); ssid_ie_len = 2 + roam_profile.SSID.length; - hdd_debug("SSIDIE:"); - QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_HDD, QDF_TRACE_LEVEL_DEBUG, - buf_ssid_ie, ssid_ie_len); final_req_ie = qdf_mem_malloc(IW_GENERIC_IE_MAX); if (final_req_ie == NULL) { if (bss) @@ -2689,17 +2699,20 @@ void hdd_perform_roam_set_key_complete(struct hdd_adapter *adapter) { QDF_STATUS qdf_ret_status = QDF_STATUS_SUCCESS; struct hdd_station_ctx *sta_ctx = WLAN_HDD_GET_STATION_CTX_PTR(adapter); - struct csr_roam_info roamInfo; + struct csr_roam_info *roam_info; - roamInfo.fAuthRequired = false; - qdf_mem_copy(roamInfo.bssid.bytes, + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return; + roam_info->fAuthRequired = false; + qdf_mem_copy(roam_info->bssid.bytes, sta_ctx->roam_info.bssid, QDF_MAC_ADDR_SIZE); - qdf_mem_copy(roamInfo.peerMac.bytes, + qdf_mem_copy(roam_info->peerMac.bytes, sta_ctx->roam_info.peer_mac, QDF_MAC_ADDR_SIZE); qdf_ret_status = hdd_roam_set_key_complete_handler(adapter, - &roamInfo, + roam_info, sta_ctx->roam_info.roam_id, sta_ctx->roam_info.roam_status, eCSR_ROAM_RESULT_AUTHENTICATED); @@ -2707,6 +2720,7 @@ void hdd_perform_roam_set_key_complete(struct hdd_adapter *adapter) hdd_err("Set Key complete failure"); sta_ctx->roam_info.defer_key_complete = false; + qdf_mem_free(roam_info); } #if defined(WLAN_FEATURE_FILS_SK) && \ @@ -2755,7 +2769,7 @@ hdd_association_completion_handler(struct hdd_adapter *adapter, struct hdd_context *hdd_ctx = WLAN_HDD_GET_CTX(adapter); struct hdd_station_ctx *sta_ctx = WLAN_HDD_GET_STATION_CTX_PTR(adapter); QDF_STATUS qdf_status = QDF_STATUS_E_FAILURE; - uint8_t reqRsnIe[DOT11F_IE_RSN_MAX_LEN]; + uint8_t *reqRsnIe; uint32_t reqRsnLength = DOT11F_IE_RSN_MAX_LEN, ie_len; int ft_carrier_on = false; bool hddDisconInProgress = false; @@ -2781,13 +2795,6 @@ hdd_association_completion_handler(struct hdd_adapter *adapter, */ hdd_reset_scan_reject_params(hdd_ctx, roamStatus, roamResult); - /* - * Enable roaming on other STA iface except this one. - * Firmware dosent support connection on one STA iface while - * roaming on other STA iface - */ - wlan_hdd_enable_roaming(adapter); - /* HDD has initiated disconnect, do not send connect result indication * to kernel as it will be handled by __cfg80211_disconnect. */ @@ -2815,6 +2822,18 @@ hdd_association_completion_handler(struct hdd_adapter *adapter, eConnectionState_Associated); } + if (adapter->device_mode == QDF_P2P_CLIENT_MODE && + hdd_ctx->config->p2p_disable_roam) { + hdd_debug("p2p cli active keep disable roam"); + } else { + /* + * Enable roaming on other STA iface except this one. + * Firmware dosent support connection on one STA iface + * while roaming on other STA iface + */ + wlan_hdd_enable_roaming(adapter); + } + /* Save the connection info from CSR... */ hdd_conn_save_connect_info(adapter, roam_info, eCSR_BSS_TYPE_INFRASTRUCTURE); @@ -2831,8 +2850,6 @@ hdd_association_completion_handler(struct hdd_adapter *adapter, adapter->wapi_info.is_wapi_sta = false; } #endif /* FEATURE_WLAN_WAPI */ - hdd_debug("bss_descr[%d] devicemode[%d]", !!roam_info->pBssDesc, - adapter->device_mode); if ((QDF_STA_MODE == adapter->device_mode) && roam_info->pBssDesc) { ie_len = GET_IE_LEN_IN_BSS(roam_info->pBssDesc->length); @@ -2914,7 +2931,6 @@ hdd_association_completion_handler(struct hdd_adapter *adapter, wlan_hdd_auto_shutdown_enable(hdd_ctx, false); #endif - hdd_debug("check if STA chan ok for DNBS"); if (policy_mgr_is_chan_ok_for_dnbs(hdd_ctx->psoc, sta_ctx->conn_info.operationChannel, &ok)) { @@ -2934,7 +2950,8 @@ hdd_association_completion_handler(struct hdd_adapter *adapter, sme_roam_disconnect( mac_handle, adapter->session_id, - eCSR_DISCONNECT_REASON_UNSPECIFIED); + eCSR_DISCONNECT_REASON_UNSPECIFIED, + eSIR_MAC_UNSPEC_FAILURE_REASON); } return QDF_STATUS_E_FAILURE; } @@ -2944,6 +2961,11 @@ hdd_association_completion_handler(struct hdd_adapter *adapter, QDF_TRACE_DEFAULT_PDEV_ID, QDF_PROTO_TYPE_MGMT, QDF_PROTO_MGMT_ASSOC)); + reqRsnIe = qdf_mem_malloc(sizeof(uint8_t) * + DOT11F_IE_RSN_MAX_LEN); + if (!reqRsnIe) + return QDF_STATUS_E_NOMEM; + /* * For reassoc, the station is already registered, all we need * is to change the state of the STA in TL. @@ -2957,8 +2979,12 @@ hdd_association_completion_handler(struct hdd_adapter *adapter, u8 *pFTAssocReq = NULL; unsigned int assocReqlen = 0; struct ieee80211_channel *chan; - uint8_t rspRsnIe[DOT11F_IE_RSN_MAX_LEN]; uint32_t rspRsnLength = DOT11F_IE_RSN_MAX_LEN; + uint8_t *rspRsnIe = + qdf_mem_malloc(sizeof(uint8_t) * + DOT11F_IE_RSN_MAX_LEN); + if (!rspRsnIe) + return QDF_STATUS_E_NOMEM; /* add bss_id to cfg80211 data base */ bss = @@ -2983,8 +3009,11 @@ hdd_association_completion_handler(struct hdd_adapter *adapter, sme_roam_disconnect( mac_handle, adapter->session_id, - eCSR_DISCONNECT_REASON_UNSPECIFIED); + eCSR_DISCONNECT_REASON_UNSPECIFIED, + eSIR_MAC_UNSPEC_FAILURE_REASON); } + qdf_mem_free(reqRsnIe); + qdf_mem_free(rspRsnIe); return QDF_STATUS_E_FAILURE; } @@ -3007,12 +3036,7 @@ hdd_association_completion_handler(struct hdd_adapter *adapter, roam_info->nAssocRspLength - FT_ASSOC_RSP_IES_OFFSET; - hdd_debug("assocRsplen %d", assocRsplen); - hdd_debug("Assoc Rsp IE dump"); - QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_HDD, - QDF_TRACE_LEVEL_DEBUG, - pFTAssocRsp, - assocRsplen); + hdd_debug("assoc_rsp_len %d", assocRsplen); } else { hdd_debug("AssocRsp is NULL"); assocRsplen = 0; @@ -3029,11 +3053,6 @@ hdd_association_completion_handler(struct hdd_adapter *adapter, */ pFTAssocReq += FT_ASSOC_REQ_IES_OFFSET; - hdd_debug("pFTAssocReq is now at %02x%02x", - (unsigned int) - pFTAssocReq[0], - (unsigned int) - pFTAssocReq[1]); assocReqlen = roam_info->nAssocReqLength - FT_ASSOC_REQ_IES_OFFSET; @@ -3045,22 +3064,20 @@ hdd_association_completion_handler(struct hdd_adapter *adapter, assocReqlen = roam_info->nAssocReqLength; } - - hdd_debug("assocReqlen %d", assocReqlen); - hdd_debug("Assoc/Reassoc Req IE dump"); - QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_HDD, - QDF_TRACE_LEVEL_DEBUG, - pFTAssocReq, - assocReqlen); + hdd_debug("assoc_req_len %d", assocReqlen); } else { hdd_debug("AssocReq is NULL"); assocReqlen = 0; } - if (roam_info->u.pConnectedProfile->AuthType == - eCSR_AUTH_TYPE_FT_RSN - || roam_info->u.pConnectedProfile->AuthType == - eCSR_AUTH_TYPE_FT_RSN_PSK) { + if ((roam_info->u.pConnectedProfile->AuthType == + eCSR_AUTH_TYPE_FT_RSN) || + (roam_info->u.pConnectedProfile->AuthType == + eCSR_AUTH_TYPE_FT_RSN_PSK) || + (roam_info->u.pConnectedProfile->AuthType == + eCSR_AUTH_TYPE_FT_SAE) || + (roam_info->u.pConnectedProfile->AuthType == + eCSR_AUTH_TYPE_FT_SUITEB_EAP_SHA384)) { if (ft_carrier_on) { if (!hddDisconInProgress && roam_info->pBssDesc) { @@ -3168,6 +3185,7 @@ hdd_association_completion_handler(struct hdd_adapter *adapter, * wpa supplicant expecting WPA/RSN IE in * connect result. */ + sme_roam_get_wpa_rsn_req_ie(mac_handle, adapter->session_id, &reqRsnLength, @@ -3229,6 +3247,7 @@ hdd_association_completion_handler(struct hdd_adapter *adapter, WLAN_CONTROL_PATH); } + qdf_mem_free(rspRsnIe); } else { /* * wpa supplicant expecting WPA/RSN IE in connect result @@ -3296,6 +3315,7 @@ hdd_association_completion_handler(struct hdd_adapter *adapter, WLAN_WAKE_ALL_NETIF_QUEUE, WLAN_CONTROL_PATH); } + qdf_mem_free(reqRsnIe); if (!QDF_IS_STATUS_SUCCESS(qdf_status)) { hdd_err("STA register with TL failed status: %d [%08X]", @@ -3305,6 +3325,13 @@ hdd_association_completion_handler(struct hdd_adapter *adapter, qdf_mem_zero(&adapter->hdd_stats.hdd_pmf_stats, sizeof(adapter->hdd_stats.hdd_pmf_stats)); #endif + if (adapter->device_mode == QDF_STA_MODE && + hdd_conn_get_connected_band(sta_ctx) == BAND_5G) { + /* Inform FTM TIME SYNC about the connection with AP */ + hdd_ftm_time_sync_sta_state_notify( + adapter, FTM_TIME_SYNC_STA_CONNECTED); + } + hdd_debug("check for SAP restart"); policy_mgr_check_concurrent_intf_and_restart_sap( hdd_ctx->psoc); @@ -3374,7 +3401,24 @@ hdd_association_completion_handler(struct hdd_adapter *adapter, */ if (eCSR_ROAM_ASSOCIATION_FAILURE == roamStatus && !hddDisconInProgress) { + u8 *assoc_rsp = NULL; + u8 *assoc_req = NULL; + if (roam_info) { + if (roam_info->pbFrames) { + /* Association Request */ + assoc_req = + (u8 *)(roam_info->pbFrames + + roam_info->nBeaconLength); + /* Association Response */ + assoc_rsp = + (u8 *)(roam_info->pbFrames + + roam_info->nBeaconLength + + roam_info->nAssocReqLength); + hdd_debug("assoc_req_len %d assoc resp len %d", + roam_info->nAssocReqLength, + roam_info->nAssocRspLength); + } hdd_err("send connect failure to nl80211: for bssid " MAC_ADDRESS_STR " result: %d and Status: %d reasoncode: %d", @@ -3399,7 +3443,10 @@ hdd_association_completion_handler(struct hdd_adapter *adapter, if (roam_info) hdd_connect_result(dev, roam_info->bssid.bytes, - roam_info, NULL, 0, NULL, 0, + roam_info, assoc_req, + roam_info->nAssocReqLength, + assoc_rsp, + roam_info->nAssocRspLength, WLAN_STATUS_ASSOC_DENIED_UNSPEC, GFP_KERNEL, connect_timeout, @@ -3416,7 +3463,10 @@ hdd_association_completion_handler(struct hdd_adapter *adapter, if (roam_info) hdd_connect_result(dev, roam_info->bssid.bytes, - roam_info, NULL, 0, NULL, 0, + roam_info, assoc_req, + roam_info->nAssocReqLength, + assoc_rsp, + roam_info->nAssocRspLength, roam_info->reasonCode ? roam_info->reasonCode : WLAN_STATUS_UNSPECIFIED_FAILURE, @@ -3452,6 +3502,13 @@ hdd_association_completion_handler(struct hdd_adapter *adapter, if (roamStatus == eCSR_ROAM_ASSOCIATION_FAILURE || roamStatus == eCSR_ROAM_CANCELLED) { ucfg_tdls_notify_connect_failure(hdd_ctx->psoc); + + /* + * Enable roaming on other STA iface except this one. + * Firmware dosent support connection on one STA iface + * while roaming on other STA iface + */ + wlan_hdd_enable_roaming(adapter); } /* @@ -3476,8 +3533,18 @@ hdd_association_completion_handler(struct hdd_adapter *adapter, * eCSR_ROAM_RESULT_SCAN_FOR_SSID_FAILURE that mean HDD is * waiting on disconnect_comp_var so unblock anyone waiting for * disconnect to complete. + * Also add eCSR_ROAM_ASSOCIATION_FAILURE and + * eCSR_ROAM_CANCELLED here to handle the following scenarios: + * + * 1. Connection is in progress, but completes with failure + * before we check the CSR state. + * 2. Connection is in progress. But the connect command is in + * pending queue and is removed from pending queue as part + * of csr_roam_disconnect. */ - if ((roamResult == eCSR_ROAM_RESULT_SCAN_FOR_SSID_FAILURE) && + if ((roamResult == eCSR_ROAM_RESULT_SCAN_FOR_SSID_FAILURE || + roamStatus == eCSR_ROAM_ASSOCIATION_FAILURE || + roamStatus == eCSR_ROAM_CANCELLED) && hddDisconInProgress) complete(&adapter->disconnect_comp_var); } @@ -4570,9 +4637,6 @@ static void hdd_roam_channel_switch_handler(struct hdd_adapter *adapter, struct hdd_context *hdd_ctx = WLAN_HDD_GET_CTX(adapter); mac_handle_t mac_handle = hdd_adapter_get_mac_handle(adapter); - hdd_debug("channel switch for session:%d to channel:%d", - adapter->session_id, roam_info->chan_info.chan_id); - /* Enable Roaming on STA interface which was disabled before CSA */ if (adapter->device_mode == QDF_STA_MODE) sme_start_roaming(mac_handle, adapter->session_id, @@ -4599,13 +4663,13 @@ static void hdd_roam_channel_switch_handler(struct hdd_adapter *adapter, if (QDF_IS_STATUS_ERROR(status)) hdd_err("channel change notification failed"); - hdd_debug("check for SAP restart"); policy_mgr_check_concurrent_intf_and_restart_sap(hdd_ctx->psoc); status = policy_mgr_set_hw_mode_on_channel_switch(hdd_ctx->psoc, adapter->session_id); if (QDF_IS_STATUS_ERROR(status)) hdd_debug("set hw mode change not done"); + } /** @@ -4718,7 +4782,6 @@ hdd_sme_roam_callback(void *pContext, struct csr_roam_info *roam_info, break; case eCSR_ROAM_LOSTLINK: if (roamResult == eCSR_ROAM_RESULT_LOSTLINK) { - hdd_debug("Roaming started due to connection lost"); hdd_debug("Disabling queues"); wlan_hdd_netif_queue_control(adapter, WLAN_STOP_ALL_NETIF_QUEUE_N_CARRIER, @@ -4960,6 +5023,12 @@ hdd_sme_roam_callback(void *pContext, struct csr_roam_info *roam_info, wlan_hdd_sae_callback(adapter, roam_info); break; + case eCSR_ROAM_FIPS_PMK_REQUEST: + /* notify the supplicant of a new candidate */ + qdf_ret_status = wlan_hdd_cfg80211_pmksa_candidate_notify( + adapter, roam_info, 1, false); + break; + default: break; } @@ -5006,6 +5075,9 @@ static void hdd_translate_sae_rsn_to_csr_auth(int8_t auth_suite[4], { if (qdf_mem_cmp(auth_suite, ccp_rsn_oui_80, 4) == 0) *auth_type = eCSR_AUTH_TYPE_SAE; + else if (qdf_mem_cmp(auth_suite, ccp_rsn_oui_90, 4) == 0) + *auth_type = eCSR_AUTH_TYPE_FT_SAE; + } #else static inline void hdd_translate_sae_rsn_to_csr_auth(int8_t auth_suite[4], @@ -5057,11 +5129,14 @@ eCsrAuthType hdd_translate_rsn_to_csr_auth_type(uint8_t auth_suite[4]) } else if (memcmp(auth_suite, ccp_rsn_oui_0c, 4) == 0) { /* Check for Suite B EAP 384 */ auth_type = eCSR_AUTH_TYPE_SUITEB_EAP_SHA384; + } else if (memcmp(auth_suite, ccp_rsn_oui_0d, 4) == 0) { + /* Check for FT Suite B EAP 384 */ + auth_type = eCSR_AUTH_TYPE_FT_SUITEB_EAP_SHA384; } else { hdd_translate_fils_rsn_to_csr_auth(auth_suite, &auth_type); hdd_translate_sae_rsn_to_csr_auth(auth_suite, &auth_type); } - hdd_debug("auth_type: %d", auth_type); + return auth_type; } @@ -5088,7 +5163,7 @@ eCsrAuthType hdd_translate_wpa_to_csr_auth_type(uint8_t auth_suite[4]) { hdd_translate_fils_rsn_to_csr_auth(auth_suite, &auth_type); } - hdd_debug("auth_type: %d", auth_type); + return auth_type; } @@ -5121,7 +5196,6 @@ hdd_translate_rsn_to_csr_encryption_type(uint8_t cipher_suite[4]) else cipher_type = eCSR_ENCRYPT_TYPE_FAILED; - hdd_debug("cipher_type: %d", cipher_type); return cipher_type; } @@ -5150,7 +5224,6 @@ hdd_translate_wpa_to_csr_encryption_type(uint8_t cipher_suite[4]) else cipher_type = eCSR_ENCRYPT_TYPE_FAILED; - hdd_debug("cipher_type: %d", cipher_type); return cipher_type; } @@ -5226,14 +5299,6 @@ static int32_t hdd_process_genie(struct hdd_adapter *adapter, parse_status); return -EINVAL; } - hdd_debug("gp_cipher_suite_present: %d", - dot11RSNIE.gp_cipher_suite_present); - /* Copy out the encryption and authentication types */ - hdd_debug("pairwise cipher suite count: %d", - dot11RSNIE.pwise_cipher_suite_count); - hdd_debug("authentication suite count: %d", - dot11RSNIE.akm_suite_cnt); - /* dot11RSNIE.akm_suite_cnt */ /* Just translate the FIRST one */ *pAuthType = hdd_translate_rsn_to_csr_auth_type( @@ -5269,12 +5334,6 @@ static int32_t hdd_process_genie(struct hdd_adapter *adapter, parse_status); return -EINVAL; } - /* Copy out the encryption and authentication types */ - hdd_debug("WPA unicast cipher suite count: %d", - dot11WPAIE.unicast_cipher_count); - hdd_debug("WPA authentication suite count: %d", - dot11WPAIE.auth_suite_count); - /* dot11WPAIE.auth_suite_count */ /* Just translate the FIRST one */ *pAuthType = hdd_translate_wpa_to_csr_auth_type( @@ -5402,21 +5461,20 @@ int hdd_set_genie_to_csr(struct hdd_adapter *adapter, roam_profile->EncryptionType.encryptionType[0] = mcRSNEncryptType; } + #ifdef WLAN_FEATURE_11W - hdd_debug("RSNMfpRequired = %d, RSNMfpCapable = %d", + hdd_debug("mfp_required = %d, mfp_capable = %d", RSNMfpRequired, RSNMfpCapable); roam_profile->MFPRequired = RSNMfpRequired; roam_profile->MFPCapable = RSNMfpCapable; #endif - hdd_debug("CSR AuthType = %d, EncryptionType = %d mcEncryptionType = %d", - *RSNAuthType, RSNEncryptType, mcRSNEncryptType); } hdd_ctx = WLAN_HDD_GET_CTX(adapter); if (hdd_ctx->force_rsne_override && (security_ie[0] == DOT11F_EID_RSN)) { hdd_warn("Test mode enabled set def Auth and enc type. RSN IE passed in connect req: "); - qdf_trace_hex_dump(QDF_MODULE_ID_HDD, QDF_TRACE_LEVEL_WARN, + qdf_trace_hex_dump(QDF_MODULE_ID_HDD, QDF_TRACE_LEVEL_DEBUG, roam_profile->pRSNReqIE, roam_profile->nRSNReqIELength); @@ -5494,9 +5552,6 @@ int hdd_set_csr_auth_type(struct hdd_adapter *adapter, roam_profile = hdd_roam_profile(adapter); roam_profile->AuthType.numEntries = 1; - hdd_debug("authType = %d RSNAuthType %d wpa_versions %d key_mgmt: 0x%x", - sta_ctx->conn_info.authType, RSNAuthType, - sta_ctx->wpa_versions, key_mgmt); switch (sta_ctx->conn_info.authType) { case eCSR_AUTH_TYPE_OPEN_SYSTEM: @@ -5515,11 +5570,9 @@ int hdd_set_csr_auth_type(struct hdd_adapter *adapter, if ((RSNAuthType == eCSR_AUTH_TYPE_CCKM_WPA) && ((key_mgmt & HDD_AUTH_KEY_MGMT_802_1X) == HDD_AUTH_KEY_MGMT_802_1X)) { - hdd_debug("set authType to CCKM WPA. AKM also 802.1X."); roam_profile->AuthType.authType[0] = eCSR_AUTH_TYPE_CCKM_WPA; } else if (RSNAuthType == eCSR_AUTH_TYPE_CCKM_WPA) { - hdd_debug("Last chance to set authType to CCKM WPA."); roam_profile->AuthType.authType[0] = eCSR_AUTH_TYPE_CCKM_WPA; } else @@ -5543,11 +5596,9 @@ int hdd_set_csr_auth_type(struct hdd_adapter *adapter, if ((RSNAuthType == eCSR_AUTH_TYPE_CCKM_RSN) && ((key_mgmt & HDD_AUTH_KEY_MGMT_802_1X) == HDD_AUTH_KEY_MGMT_802_1X)) { - hdd_debug("set authType to CCKM RSN. AKM also 802.1X."); roam_profile->AuthType.authType[0] = eCSR_AUTH_TYPE_CCKM_RSN; } else if (RSNAuthType == eCSR_AUTH_TYPE_CCKM_RSN) { - hdd_debug("Last chance to set authType to CCKM RSN."); roam_profile->AuthType.authType[0] = eCSR_AUTH_TYPE_CCKM_RSN; } else @@ -5582,8 +5633,6 @@ int hdd_set_csr_auth_type(struct hdd_adapter *adapter, RSNAuthType)) { roam_profile->AuthType.authType[0] = RSNAuthType; - hdd_debug("updated profile authtype as %d", - RSNAuthType); } else if ((RSNAuthType == eCSR_AUTH_TYPE_OWE) && ((key_mgmt & HDD_AUTH_KEY_MGMT_802_1X) @@ -5609,8 +5658,21 @@ int hdd_set_csr_auth_type(struct hdd_adapter *adapter, /* Suite B EAP SHA 384 */ roam_profile->AuthType.authType[0] = eCSR_AUTH_TYPE_SUITEB_EAP_SHA384; + } else if ((RSNAuthType == eCSR_AUTH_TYPE_FT_SAE) && + ((key_mgmt & HDD_AUTH_KEY_MGMT_802_1X) == + HDD_AUTH_KEY_MGMT_802_1X)) { + roam_profile->AuthType.authType[0] = + eCSR_AUTH_TYPE_FT_SAE; + } else if ((RSNAuthType == + eCSR_AUTH_TYPE_FT_SUITEB_EAP_SHA384) && + ((key_mgmt & HDD_AUTH_KEY_MGMT_802_1X) + == HDD_AUTH_KEY_MGMT_802_1X)) { + /* FT Suite-B EAP SHA 384 */ + roam_profile->AuthType.authType[0] = + eCSR_AUTH_TYPE_FT_SUITEB_EAP_SHA384; + } else if ((key_mgmt & HDD_AUTH_KEY_MGMT_802_1X) - == HDD_AUTH_KEY_MGMT_802_1X) { + == HDD_AUTH_KEY_MGMT_802_1X) { roam_profile->AuthType.authType[0] = eCSR_AUTH_TYPE_RSN; } else @@ -5631,7 +5693,12 @@ int hdd_set_csr_auth_type(struct hdd_adapter *adapter, break; case eCSR_AUTH_TYPE_SAE: - roam_profile->AuthType.authType[0] = eCSR_AUTH_TYPE_SAE; + + if (RSNAuthType == eCSR_AUTH_TYPE_FT_SAE) + roam_profile->AuthType.authType[0] = + eCSR_AUTH_TYPE_FT_SAE; + else + roam_profile->AuthType.authType[0] = eCSR_AUTH_TYPE_SAE; break; default: @@ -5643,9 +5710,6 @@ int hdd_set_csr_auth_type(struct hdd_adapter *adapter, break; } - hdd_debug("Set roam Authtype to %d", - roam_profile->AuthType.authType[0]); - return 0; } diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_bcn_recv.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_bcn_recv.c index c596b84788ee..9861007c1f4a 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_bcn_recv.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_bcn_recv.c @@ -29,6 +29,7 @@ #include "wlan_hdd_main.h" #include "wlan_hdd_bcn_recv.h" #include +#include #define SET_BIT(value, mask) ((value) |= (1 << (mask))) @@ -125,15 +126,20 @@ static void hdd_send_bcn_recv_info(hdd_handle_t hdd_handle, struct hdd_context *hdd_ctx = hdd_handle_to_context(hdd_handle); uint32_t data_len; int flags = cds_get_gfp_flags(); + struct hdd_adapter *adapter; if (wlan_hdd_validate_context(hdd_ctx)) return; data_len = get_beacon_report_data_len(beacon_report); + adapter = hdd_get_adapter_by_vdev(hdd_ctx, beacon_report->vdev_id); + if (hdd_validate_adapter(adapter)) + return; + vendor_event = cfg80211_vendor_event_alloc( - hdd_ctx->wiphy, NULL, + hdd_ctx->wiphy, &(adapter->wdev), data_len, QCA_NL80211_VENDOR_SUBCMD_BEACON_REPORTING_INDEX, flags); @@ -306,6 +312,8 @@ static int __wlan_hdd_cfg80211_bcn_rcv_op(struct wiphy *wiphy, uint32_t bcn_report, nth_value = 1; int errno; bool active_report, do_not_resume; + struct wlan_objmgr_vdev *vdev; + enum scm_scan_status scan_req_status; hdd_enter_dev(dev); @@ -323,6 +331,19 @@ static int __wlan_hdd_cfg80211_bcn_rcv_op(struct wiphy *wiphy, return -EINVAL; } + vdev = hdd_objmgr_get_vdev(adapter); + if (!vdev) + return -EINVAL; + + scan_req_status = ucfg_scan_get_pdev_status(wlan_vdev_get_pdev(vdev)); + wlan_objmgr_vdev_release_ref(vdev, WLAN_OSIF_ID); + + if (scan_req_status != SCAN_NOT_IN_PROGRESS) { + hdd_debug("Scan in progress: %d, bcn rpt start OP not allowed", + scan_req_status); + return -EBUSY; + } + errno = wlan_cfg80211_nla_parse(tb, QCA_WLAN_VENDOR_ATTR_BEACON_REPORTING_MAX, @@ -422,7 +443,7 @@ void hdd_beacon_recv_pause_indication(hdd_handle_t hdd_handle, vendor_event = cfg80211_vendor_event_alloc( - hdd_ctx->wiphy, NULL, + hdd_ctx->wiphy, &(adapter->wdev), data_len, QCA_NL80211_VENDOR_SUBCMD_BEACON_REPORTING_INDEX, flags); @@ -491,7 +512,7 @@ void hdd_beacon_recv_pause_indication(hdd_handle_t hdd_handle, * the QCA_WLAN_VENDOR_ATTR_BEACON_REPORTING_AUTO_RESUMES shall not be * set by the driver. */ - if (!is_disconnected || !do_not_resume) + if (!is_disconnected && !do_not_resume) if (nla_put_flag(vendor_event, QCA_WLAN_VENDOR_ATTR_BEACON_REPORTING_AUTO_RESUMES)) { hdd_err("QCA_WLAN_VENDOR_ATTR put fail"); diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_cfg.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_cfg.c index 3f83a10e131f..a0a7b6966a83 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_cfg.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_cfg.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -1586,6 +1586,19 @@ struct reg_table_entry g_registry_table[] = { CFG_BAND_CAPABILITY_MIN, CFG_BAND_CAPABILITY_MAX), + REG_VARIABLE(CFG_MGMT_RETRY_MAX, WLAN_PARAM_Integer, + struct hdd_config, mgmt_retry_max, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_MGMT_RETRY_MAX_DEFAULT, + CFG_MGMT_RETRY_MAX_MIN, + CFG_MGMT_RETRY_MAX_MAX), + + REG_VARIABLE(CFG_ENABLE_RING_BUFFER, WLAN_PARAM_Integer, + struct hdd_config, enable_ring_buffer, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_ENABLE_RING_BUFFER_DEFAULT, + CFG_ENABLE_RING_BUFFER_MIN, + CFG_ENABLE_RING_BUFFER_MAX), /* CFG_QDF_TRACE_ENABLE Parameters */ REG_VARIABLE(CFG_QDF_TRACE_ENABLE_WDI_NAME, WLAN_PARAM_Integer, struct hdd_config, qdf_trace_enable_wdi, @@ -2376,6 +2389,13 @@ struct reg_table_entry g_registry_table[] = { CFG_TDLS_PEER_KICKOUT_THRESHOLD_MIN, CFG_TDLS_PEER_KICKOUT_THRESHOLD_MAX), + REG_VARIABLE(CFG_TDLS_DISCOVERY_WAKE_TIMEOUT, WLAN_PARAM_Integer, + struct hdd_config, tdls_discovery_wake_timeout, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_TDLS_DISCOVERY_WAKE_TIMEOUT_DEFAULT, + CFG_TDLS_DISCOVERY_WAKE_TIMEOUT_MIN, + CFG_TDLS_DISCOVERY_WAKE_TIMEOUT_MAX), + #endif REG_VARIABLE(CFG_SCAN_AGING_PARAM_NAME, WLAN_PARAM_Integer, @@ -2980,6 +3000,13 @@ struct reg_table_entry g_registry_table[] = { CFG_ENABLE_PACKET_LOG_DEFAULT, CFG_ENABLE_PACKET_LOG_MIN, CFG_ENABLE_PACKET_LOG_MAX), + + REG_VARIABLE(CFG_PACKET_LOG_BUFFER_SIZE_NAME, WLAN_PARAM_Integer, + struct hdd_config, pktlog_buf_size, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_PACKET_LOG_BUFFER_SIZE_DEFAULT, + CFG_PACKET_LOG_BUFFER_SIZE_MIN, + CFG_PACKET_LOG_BUFFER_SIZE_MAX), #endif #ifdef WLAN_FEATURE_ROAM_OFFLOAD @@ -2989,7 +3016,22 @@ struct reg_table_entry g_registry_table[] = { CFG_ROAMING_OFFLOAD_DEFAULT, CFG_ROAMING_OFFLOAD_MIN, CFG_ROAMING_OFFLOAD_MAX), + + REG_VARIABLE(CFG_ROAM_TRIGGER_BITMAP, WLAN_PARAM_HexInteger, + struct hdd_config, roam_triggers, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK, + CFG_ROAM_TRIGGER_BITMAP_DEFAULT, + CFG_ROAM_TRIGGER_BITMAP_MIN, + CFG_ROAM_TRIGGER_BITMAP_MAX), #endif + + REG_VARIABLE(CFG_BMISS_SKIP_FULL_SCAN, WLAN_PARAM_Integer, + struct hdd_config, bmiss_skip_full_scan, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_BMISS_SKIP_FULL_SCAN_DEFAULT, + CFG_BMISS_SKIP_FULL_SCAN_MIN, + CFG_BMISS_SKIP_FULL_SCAN_MAX), + #ifdef MSM_PLATFORM REG_VARIABLE(CFG_BUS_BANDWIDTH_HIGH_THRESHOLD, WLAN_PARAM_Integer, struct hdd_config, busBandwidthHighThreshold, @@ -3230,6 +3272,27 @@ struct reg_table_entry g_registry_table[] = { CFG_ENABLE_NAN_SUPPORT_DEFAULT, CFG_ENABLE_NAN_SUPPORT_MIN, CFG_ENABLE_NAN_SUPPORT_MAX), + + REG_VARIABLE(CFG_NAN_SEPARATE_IFACE_SUPP, WLAN_PARAM_Integer, + struct hdd_config, nan_separate_iface_support, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_NAN_SEPARATE_IFACE_SUPP_DEFAULT, + CFG_NAN_SEPARATE_IFACE_SUPP_MIN, + CFG_NAN_SEPARATE_IFACE_SUPP_MAX), + + REG_VARIABLE(CFG_NDP_KEEP_ALIVE_PERIOD, WLAN_PARAM_Integer, + struct hdd_config, ndp_keep_alive_period, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_NDP_KEEP_ALIVE_PERIOD_DEFAULT, + CFG_NDP_KEEP_ALIVE_PERIOD_MIN, + CFG_NDP_KEEP_ALIVE_PERIOD_MAX), + + REG_VARIABLE(CFG_SUPPORT_MP0_DISCOVERY, WLAN_PARAM_Integer, + struct hdd_config, support_mp0_discovery, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_SUPPORT_MP0_DISCOVERY_DEFAULT, + CFG_SUPPORT_MP0_DISCOVERY_MIN, + CFG_SUPPORT_MP0_DISCOVERY_MAX), #endif REG_VARIABLE(CFG_ENABLE_SELF_RECOVERY, WLAN_PARAM_Integer, @@ -4239,6 +4302,13 @@ struct reg_table_entry g_registry_table[] = { struct hdd_config, dp_trace_config, VAR_FLAGS_OPTIONAL, (void *) CFG_ENABLE_DP_TRACE_CONFIG_DEFAULT), + + REG_VARIABLE(CFG_DP_PROTO_EVENT_BITMAP, WLAN_PARAM_HexInteger, + struct hdd_config, dp_proto_event_bitmap, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_DP_PROTO_EVENT_BITMAP_DEFAULT, + CFG_DP_PROTO_EVENT_BITMAP_MIN, + CFG_DP_PROTO_EVENT_BITMAP_MAX), #endif REG_VARIABLE(CFG_ADAPTIVE_SCAN_DWELL_MODE_NAME, WLAN_PARAM_Integer, @@ -4353,6 +4423,13 @@ struct reg_table_entry g_registry_table[] = { CFG_RX_THREAD_CPU_MASK_MIN, CFG_RX_THREAD_CPU_MASK_MAX), + REG_VARIABLE(CFG_RX_THREAD_UL_CPU_MASK_NAME, WLAN_PARAM_HexInteger, + struct hdd_config, rx_thread_ul_affinity_mask, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_RX_THREAD_UL_CPU_MASK_DEFAULT, + CFG_RX_THREAD_UL_CPU_MASK_MIN, + CFG_RX_THREAD_UL_CPU_MASK_MAX), + REG_VARIABLE_STRING(CFG_RPS_RX_QUEUE_CPU_MAP_LIST_NAME, WLAN_PARAM_String, struct hdd_config, cpu_map_list, @@ -4559,6 +4636,12 @@ struct reg_table_entry g_registry_table[] = { CFG_CRASH_FW_TIMEOUT_DEFAULT, CFG_CRASH_FW_TIMEOUT_DISABLE, CFG_CRASH_FW_TIMEOUT_ENABLE), + REG_VARIABLE(CFG_RX_WAKELOCK_TIMEOUT_NAME, WLAN_PARAM_Integer, + struct hdd_config, rx_wakelock_timeout, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_RX_WAKELOCK_TIMEOUT_DEFAULT, + CFG_RX_WAKELOCK_TIMEOUT_MIN, + CFG_RX_WAKELOCK_TIMEOUT_MAX), REG_VARIABLE(CFG_SAP_CH_SWITCH_BEACON_CNT, WLAN_PARAM_Integer, struct hdd_config, sap_chanswitch_beacon_cnt, VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, @@ -5098,6 +5181,14 @@ struct reg_table_entry g_registry_table[] = { (void *) CFG_ACTION_OUI_DISABLE_AGGRESSIVE_TX_DEFAULT), + REG_VARIABLE_STRING(CFG_ACTION_OUI_DISABLE_AGGRESSIVE_EDCA, + WLAN_PARAM_String, + struct hdd_config, + action_oui_str[ACTION_OUI_DISABLE_AGGRESSIVE_EDCA], + VAR_FLAGS_OPTIONAL, + (void *) + CFG_ACTION_OUI_DISABLE_AGGRESSIVE_EDCA_DEFAULT), + REG_VARIABLE(CFG_DTIM_1CHRX_ENABLE_NAME, WLAN_PARAM_Integer, struct hdd_config, enable_dtim_1chrx, VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, @@ -5253,6 +5344,13 @@ struct reg_table_entry g_registry_table[] = { CFG_OCE_WAN_WEIGHTAGE_MIN, CFG_OCE_WAN_WEIGHTAGE_MAX), + REG_VARIABLE(CFG_VENDOR_ROAM_SCORE_ALGORITHM_NAME, WLAN_PARAM_Integer, + struct hdd_config, vendor_roam_score_algorithm, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_VENDOR_ROAM_SCORE_ALGORITHM_DEFAULT, + CFG_VENDOR_ROAM_SCORE_ALGORITHM_MIN, + CFG_VENDOR_ROAM_SCORE_ALGORITHM_MAX), + REG_VARIABLE(CFG_BEST_RSSI_THRESHOLD_NAME, WLAN_PARAM_Integer, struct hdd_config, best_rssi_threshold, VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, @@ -5589,6 +5687,14 @@ struct reg_table_entry g_registry_table[] = { CFG_BTM_STICKY_TIME_MIN, CFG_BTM_STICKY_TIME_MAX), + REG_VARIABLE(CFG_BTM_QUERY_BITMASK_NAME, + WLAN_PARAM_HexInteger, struct hdd_config, + btm_query_bitmask, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_BTM_QUERY_BITMASK_DEFAULT, + CFG_BTM_QUERY_BITMASK_MIN, + CFG_BTM_QUERY_BITMASK_MAX), + REG_VARIABLE(CFG_ENABLE_GCMP_NAME, WLAN_PARAM_Integer, struct hdd_config, gcmp_enabled, VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, @@ -5857,6 +5963,55 @@ struct reg_table_entry g_registry_table[] = { CFG_ROAM_PREAUTH_NO_ACK_TIMEOUT_DEFAULT, CFG_ROAM_PREAUTH_NO_ACK_TIMEOUT_MIN, CFG_ROAM_PREAUTH_NO_ACK_TIMEOUT_MAX), + + REG_VARIABLE(CFG_LFR_ENABLE_DISCONNECT_ROAM, WLAN_PARAM_Integer, + struct hdd_config, enable_disconnect_roam_offload, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_LFR_ENABLE_DISCONNECT_ROAM_DEFAULT, + CFG_LFR_ENABLE_DISCONNECT_ROAM_MIN, + CFG_LFR_ENABLE_DISCONNECT_ROAM_MAX), + + REG_VARIABLE(CFG_LFR_ENABLE_IDLE_ROAM, WLAN_PARAM_Integer, + struct hdd_config, enable_idle_roam, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_LFR_ENABLE_IDLE_ROAM_DEFAULT, + CFG_LFR_ENABLE_IDLE_ROAM_MIN, + CFG_LFR_ENABLE_IDLE_ROAM_MAX), + + REG_VARIABLE(CFG_LFR_IDLE_ROAM_RSSI_DELTA, WLAN_PARAM_Integer, + struct hdd_config, idle_roam_rssi_delta, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_LFR_IDLE_ROAM_RSSI_DELTA_DEFAULT, + CFG_LFR_IDLE_ROAM_RSSI_DELTA_MIN, + CFG_LFR_IDLE_ROAM_RSSI_DELTA_MAX), + + REG_VARIABLE(CFG_LFR_IDLE_ROAM_INACTIVE_TIME, WLAN_PARAM_Integer, + struct hdd_config, idle_roam_inactive_time, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_LFR_IDLE_ROAM_INACTIVE_TIME_DEFAULT, + CFG_LFR_IDLE_ROAM_INACTIVE_TIME_MIN, + CFG_LFR_IDLE_ROAM_INACTIVE_TIME_MAX), + + REG_VARIABLE(CFG_LFR_IDLE_ROAM_PACKET_COUNT, WLAN_PARAM_Integer, + struct hdd_config, idle_data_packet_count, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_LFR_IDLE_ROAM_PACKET_COUNT_DEFAULT, + CFG_LFR_IDLE_ROAM_PACKET_COUNT_MIN, + CFG_LFR_IDLE_ROAM_PACKET_COUNT_MAX), + + REG_VARIABLE(CFG_LFR_IDLE_ROAM_MIN_RSSI, WLAN_PARAM_SignedInteger, + struct hdd_config, idle_roam_min_rssi, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_LFR_IDLE_ROAM_MIN_RSSI_DEFAULT, + CFG_LFR_IDLE_ROAM_MIN_RSSI_MIN, + CFG_LFR_IDLE_ROAM_MIN_RSSI_MAX), + + REG_VARIABLE(CFG_LFR_IDLE_ROAM_BAND, WLAN_PARAM_Integer, + struct hdd_config, idle_roam_band, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_LFR_IDLE_ROAM_BAND_DEFAULT, + CFG_LFR_IDLE_ROAM_BAND_MIN, + CFG_LFR_IDLE_ROAM_BAND_MAX), #endif REG_VARIABLE(CFG_ENABLE_MAC_PROVISION_NAME, WLAN_PARAM_Integer, @@ -5894,6 +6049,13 @@ struct reg_table_entry g_registry_table[] = { CFG_ROAM_SCORE_DELTA_MIN, CFG_ROAM_SCORE_DELTA_MAX), + REG_VARIABLE(CFG_CAND_MIN_ROAM_SCORE_DELTA, WLAN_PARAM_Integer, + struct hdd_config, min_roam_score_delta, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_CAND_MIN_ROAM_SCORE_DELTA_DEFAULT, + CFG_CAND_MIN_ROAM_SCORE_DELTA_MIN, + CFG_CAND_MIN_ROAM_SCORE_DELTA_MAX), + REG_VARIABLE(CFG_ROAM_TRIGGER_DELTA_BITMAP, WLAN_PARAM_Integer, struct hdd_config, roam_score_delta_bitmap, VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, @@ -5951,11 +6113,12 @@ struct reg_table_entry g_registry_table[] = { CFG_BSS_LOAD_THRESHOLD_MAX), REG_VARIABLE(CFG_BSS_LOAD_SAMPLE_TIME, WLAN_PARAM_Integer, - struct hdd_config, bss_load_sample_time, - VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, - CFG_BSS_LOAD_SAMPLE_TIME_DEFAULT, - CFG_BSS_LOAD_SAMPLE_TIME_MIN, - CFG_BSS_LOAD_SAMPLE_TIME_MAX), + struct hdd_config, bss_load_sample_time, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_BSS_LOAD_SAMPLE_TIME_DEFAULT, + CFG_BSS_LOAD_SAMPLE_TIME_MIN, + CFG_BSS_LOAD_SAMPLE_TIME_MAX), + REG_VARIABLE(CFG_ENABLE_RTT_SUPPORT, WLAN_PARAM_Integer, struct hdd_config, enable_rtt_support, VAR_FLAGS_OPTIONAL, @@ -5969,8 +6132,232 @@ struct reg_table_entry g_registry_table[] = { CFG_IGNORE_FW_REG_OFFLOAD_IND_DEFAULT, CFG_IGNORE_FW_REG_OFFLOAD_IND_MIN, CFG_IGNORE_FW_REG_OFFLOAD_IND_MAX), -}; + REG_VARIABLE(CFG_NAN_NDP_INACTIVITY_TIMEOUT, WLAN_PARAM_Integer, + struct hdd_config, ndp_inactivity_timeout, + VAR_FLAGS_OPTIONAL, + CFG_NAN_NDP_INACTIVITY_TIMEOUT_DEFAULT, + CFG_NAN_NDP_INACTIVITY_TIMEOUT_MIN, + CFG_NAN_NDP_INACTIVITY_TIMEOUT_MAX), + +#ifdef WLAN_ADAPTIVE_11R + REG_VARIABLE(CFG_ADAPTIVE_11R, WLAN_PARAM_Integer, + struct hdd_config, enable_adaptive_11r, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_ADAPTIVE_11R_DEFAULT, + CFG_ADAPTIVE_11R_MIN, + CFG_ADAPTIVE_11R_MAX), +#endif + +#if defined(WLAN_SAE_SINGLE_PMK) && defined(WLAN_FEATURE_ROAM_OFFLOAD) + REG_VARIABLE(CFG_SAE_SINGLE_PMK, WLAN_PARAM_Integer, + struct hdd_config, sae_single_pmk_feature_enabled, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_SAE_SINGLE_PMK_DEFAULT, + CFG_SAE_SINGLE_PMK_MIN, + CFG_SAE_SINGLE_PMK_MAX), +#endif + + REG_VARIABLE(CFG_BSS_LOAD_TRIG_5G_RSSI_THRES, WLAN_PARAM_SignedInteger, + struct hdd_config, bss_load_trigger_rssi_threshold_5ghz, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_BSS_LOAD_TRIG_5G_RSSI_THRES_DEFAULT, + CFG_BSS_LOAD_TRIG_5G_RSSI_THRES_MIN, + CFG_BSS_LOAD_TRIG_5G_RSSI_THRES_MAX), + + REG_VARIABLE(CFG_BSS_LOAD_TRIG_2G_RSSI_THRES, WLAN_PARAM_SignedInteger, + struct hdd_config, bss_load_trigger_rssi_threshold_24ghz, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_BSS_LOAD_TRIG_2G_RSSI_THRES_DEFAULT, + CFG_BSS_LOAD_TRIG_2G_RSSI_THRES_MIN, + CFG_BSS_LOAD_TRIG_2G_RSSI_THRES_MAX), + + REG_VARIABLE(CFG_ROAM_SCAN_INACTIVITY_TIME, WLAN_PARAM_Integer, + struct hdd_config, roam_scan_inactivity_time, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_ROAM_SCAN_INACTIVITY_TIME_DEFAULT, + CFG_ROAM_SCAN_INACTIVITY_TIME_MIN, + CFG_ROAM_SCAN_INACTIVITY_TIME_MAX), + + REG_VARIABLE(CFG_ROAM_INACTIVE_COUNT, WLAN_PARAM_Integer, + struct hdd_config, roam_inactive_data_packet_count, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_ROAM_INACTIVE_COUNT_DEFAULT, + CFG_ROAM_INACTIVE_COUNT_MIN, + CFG_ROAM_INACTIVE_COUNT_MAX), + + REG_VARIABLE(CFG_POST_INACTIVITY_ROAM_SCAN_PERIOD, WLAN_PARAM_Integer, + struct hdd_config, roam_scan_period_after_inactivity, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_POST_INACTIVITY_ROAM_SCAN_PERIOD_DEFAULT, + CFG_POST_INACTIVITY_ROAM_SCAN_PERIOD_MIN, + CFG_POST_INACTIVITY_ROAM_SCAN_PERIOD_MAX), + + REG_VARIABLE(CFG_DISCONNECT_ROAM_TRIGGER_MIN_RSSI, + WLAN_PARAM_SignedInteger, + struct hdd_config, disconnect_roam_min_rssi, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_DISCONNECT_ROAM_TRIGGER_MIN_RSSI_DEFAULT, + CFG_DISCONNECT_ROAM_TRIGGER_MIN_RSSI_MIN, + CFG_DISCONNECT_ROAM_TRIGGER_MIN_RSSI_MAX), + + REG_VARIABLE(CFG_BMISS_ROAM_MIN_RSSI, WLAN_PARAM_SignedInteger, + struct hdd_config, bmiss_roam_min_rssi, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_BMISS_ROAM_MIN_RSSI_DEFAULT, + CFG_BMISS_ROAM_MIN_RSSI_MIN, + CFG_BMISS_ROAM_MIN_RSSI_MAX), + + REG_VARIABLE(CFG_IDLE_ROAM_SCORE_DELTA, WLAN_PARAM_Integer, + struct hdd_config, idle_roam_score_delta, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_IDLE_ROAM_SCORE_DELTA_DEFAULT, + CFG_IDLE_ROAM_SCORE_DELTA_MIN, + CFG_IDLE_ROAM_SCORE_DELTA_MAX), + + REG_VARIABLE(CFG_BTM_ROAM_SCORE_DELTA, WLAN_PARAM_Integer, + struct hdd_config, btm_roam_score_delta, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_BTM_ROAM_SCORE_DELTA_DEFAULT, + CFG_BTM_ROAM_SCORE_DELTA_MIN, + CFG_BTM_ROAM_SCORE_DELTA_MAX), + + REG_VARIABLE(CFG_MIN_BTM_CANDIDATE_SCORE, WLAN_PARAM_Integer, + struct hdd_config, btm_trig_min_candidate_score, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_MIN_BTM_CANDIDATE_SCORE_DEFAULT, + CFG_MIN_BTM_CANDIDATE_SCORE_MIN, + CFG_MIN_BTM_CANDIDATE_SCORE_MAX), + + REG_VARIABLE(CFG_ENABLE_PENDING_CHAN_LIST_REQ, WLAN_PARAM_Integer, + struct hdd_config, enable_pending_list_req, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_ENABLE_PENDING_CHAN_LIST_REQ_DEFAULT, + CFG_ENABLE_PENDING_CHAN_LIST_REQ_MIN, + CFG_ENABLE_PENDING_CHAN_LIST_REQ_MAX), + REG_VARIABLE(CFG_NUM_VDEV_ENABLE_NAME, WLAN_PARAM_Integer, + struct hdd_config, num_vdevs, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_NUM_VDEV_ENABLE_DEFAULT, + CFG_NUM_VDEV_ENABLE_MIN, + CFG_NUM_VDEV_ENABLE_MAX), + +#ifdef SAR_SAFETY_FEATURE + REG_VARIABLE(CFG_SAR_SAFETY_TIMEOUT, WLAN_PARAM_Integer, + struct hdd_config, sar_safety_timeout, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_SAR_SAFETY_TIMEOUT_DEFAULT, + CFG_SAR_SAFETY_TIMEOUT_MIN, + CFG_SAR_SAFETY_TIMEOUT_MAX), + + REG_VARIABLE(CFG_SAR_SAFETY_UNSOLICITED_TIMEOUT, WLAN_PARAM_Integer, + struct hdd_config, sar_safety_unsolicited_timeout, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_SAR_SAFETY_UNSOLICITED_TIMEOUT_DEFAULT, + CFG_SAR_SAFETY_UNSOLICITED_TIMEOUT_MIN, + CFG_SAR_SAFETY_UNSOLICITED_TIMEOUT_MAX), + + REG_VARIABLE(CFG_SAR_SAFETY_REQ_RESP_TIMEOUT, WLAN_PARAM_Integer, + struct hdd_config, sar_safety_req_resp_timeout, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_SAR_SAFETY_REQ_RESP_TIMEOUT_DEFAULT, + CFG_SAR_SAFETY_REQ_RESP_TIMEOUT_MIN, + CFG_SAR_SAFETY_REQ_RESP_TIMEOUT_MAX), + + REG_VARIABLE(CFG_SAR_SAFETY_REQ_RESP_RETRIES, WLAN_PARAM_Integer, + struct hdd_config, sar_safety_req_resp_retry, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_SAR_SAFETY_REQ_RESP_RETRIES_DEFAULT, + CFG_SAR_SAFETY_REQ_RESP_RETRIES_MIN, + CFG_SAR_SAFETY_REQ_RESP_RETRIES_MAX), + + REG_VARIABLE(CFG_SAR_SAFETY_INDEX, WLAN_PARAM_Integer, + struct hdd_config, sar_safety_index, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_SAR_SAFETY_INDEX_DEFAULT, + CFG_SAR_SAFETY_INDEX_MIN, + CFG_SAR_SAFETY_INDEX_MAX), + + REG_VARIABLE(CFG_SAR_SAFETY_SLEEP_INDEX, WLAN_PARAM_Integer, + struct hdd_config, sar_safety_sleep_index, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_SAR_SAFETY_SLEEP_INDEX_DEFAULT, + CFG_SAR_SAFETY_SLEEP_INDEX_MIN, + CFG_SAR_SAFETY_SLEEP_INDEX_MAX), + + REG_VARIABLE(CFG_ENABLE_SAR_SAFETY_FEATURE, WLAN_PARAM_Integer, + struct hdd_config, enable_sar_safety, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_ENABLE_SAR_SAFETY_FEATURE_DEFAULT, + CFG_ENABLE_SAR_SAFETY_FEATURE_MIN, + CFG_ENABLE_SAR_SAFETY_FEATURE_MAX), + + REG_VARIABLE(CFG_CONFIG_SAR_SAFETY_SLEEP_MODE_INDEX, WLAN_PARAM_Integer, + struct hdd_config, config_sar_safety_sleep_index, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_CONFIG_SAR_SAFETY_SLEEP_MODE_INDEX_DEFAULT, + CFG_CONFIG_SAR_SAFETY_SLEEP_MODE_INDEX_MIN, + CFG_CONFIG_SAR_SAFETY_SLEEP_MODE_INDEX_MAX), +#endif + +#ifdef WLAN_FEATURE_PKT_CAPTURE + REG_VARIABLE(CFG_PKT_CAPTURE_MODE, WLAN_PARAM_Integer, + struct hdd_config, pkt_capture_mode, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_PKT_CAPTURE_MODE_DEFAULT, + CFG_PKT_CAPTURE_MODE_MIN, + CFG_PKT_CAPTURE_MODE_MAX), +#endif + + REG_VARIABLE(CFG_MWS_COEX_PCC_CHANNEL_AVOID_DELAY, WLAN_PARAM_Integer, + struct hdd_config, mws_coex_pcc_channel_avoid_delay, + VAR_FLAGS_OPTIONAL, + CFG_MWS_COEX_PCC_CHANNEL_AVOID_DELAY_DEFAULT, + CFG_MWS_COEX_PCC_CHANNEL_AVOID_DELAY_MIN, + CFG_MWS_COEX_PCC_CHANNEL_AVOID_DELAY_MAX), + + REG_VARIABLE(CFG_MWS_COEX_SCC_CHANNEL_AVOID_DELAY, WLAN_PARAM_Integer, + struct hdd_config, mws_coex_scc_channel_avoid_delay, + VAR_FLAGS_OPTIONAL, + CFG_MWS_COEX_SCC_CHANNEL_AVOID_DELAY_DEFAULT, + CFG_MWS_COEX_SCC_CHANNEL_AVOID_DELAY_MIN, + CFG_MWS_COEX_SCC_CHANNEL_AVOID_DELAY_MAX), + + REG_VARIABLE(CFG_DISABLE_4WAY_HS_OFFLOAD, WLAN_PARAM_Integer, + struct hdd_config, disable_4way_hs_offload, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_DISABLE_4WAY_HS_OFFLOAD_DEFAULT, + CFG_DISABLE_4WAY_HS_OFFLOAD_MIN, + CFG_DISABLE_4WAY_HS_OFFLOAD_MAX), +#ifdef FEATURE_WLAN_TIME_SYNC_FTM + REG_VARIABLE(CFG_ENABLE_TIME_SYNC_FTM, WLAN_PARAM_Integer, + struct hdd_config, time_sync_ftm_enable, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_ENABLE_TIME_SYNC_FTM_DEFAULT, + CFG_ENABLE_TIME_SYNC_FTM_MIN, + CFG_ENABLE_TIME_SYNC_FTM_MAX), + + REG_VARIABLE(CFG_TIME_SYNC_FTM_MODE, WLAN_PARAM_Integer, + struct hdd_config, time_sync_ftm_mode, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_TIME_SYNC_FTM_MODE_DEFAULT, + CFG_TIME_SYNC_FTM_MODE_MIN, + CFG_TIME_SYNC_FTM_MODE_MAX), + + REG_VARIABLE(CFG_TIME_SYNC_FTM_ROLE, WLAN_PARAM_Integer, + struct hdd_config, time_sync_ftm_role, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_TIME_SYNC_FTM_ROLE_DEFAULT, + CFG_TIME_SYNC_FTM_ROLE_MIN, + CFG_TIME_SYNC_FTM_ROLE_MAX), +#endif + REG_VARIABLE(CFG_P2P_DISABLE_ROAM, WLAN_PARAM_Integer, + struct hdd_config, p2p_disable_roam, + VAR_FLAGS_OPTIONAL | VAR_FLAGS_RANGE_CHECK_ASSUME_DEFAULT, + CFG_P2P_DISABLE_ROAM_DEFAULT, + CFG_P2P_DISABLE_ROAM_MIN, + CFG_P2P_DISABLE_ROAM_MAX), +}; /** * get_next_line() - find and locate the new line pointer @@ -7000,6 +7387,10 @@ static void hdd_cfg_print_action_oui(struct hdd_context *hdd_ctx) hdd_debug("Name = [%s] value = [%s]", CFG_ACTION_OUI_DISABLE_AGGRESSIVE_TX_NAME, config->action_oui_str[ACTION_OUI_DISABLE_AGGRESSIVE_TX]); + + hdd_debug("Name = [%s] value = [%s]", + CFG_ACTION_OUI_DISABLE_AGGRESSIVE_EDCA, + config->action_oui_str[ACTION_OUI_DISABLE_AGGRESSIVE_EDCA]); } /** @@ -7442,6 +7833,8 @@ void hdd_cfg_print(struct hdd_context *hdd_ctx) #ifdef WLAN_FEATURE_ROAM_OFFLOAD hdd_debug("Name = [isRoamOffloadEnabled] Value = [%u]", hdd_ctx->config->isRoamOffloadEnabled); + hdd_debug("Name = [roam_triggers] Value = [%u]", + hdd_ctx->config->roam_triggers); #endif #ifdef WLAN_FEATURE_LPSS @@ -7967,6 +8360,8 @@ void hdd_cfg_print(struct hdd_context *hdd_ctx) hdd_ctx->config->btm_max_attempt_cnt); hdd_debug("Name = [btm_sticky_time] value = [0x%x]", hdd_ctx->config->btm_sticky_time); + hdd_debug("Name = [btm_query_bitmask] value = [0x%x]", + hdd_ctx->config->btm_query_bitmask); hdd_debug("Name = [%s] value = [%d]", CFG_ENABLE_GCMP_NAME, hdd_ctx->config->gcmp_enabled); @@ -8009,6 +8404,43 @@ void hdd_cfg_print(struct hdd_context *hdd_ctx) hdd_debug("Name = [%s] Value = [%u]", CFG_IGNORE_FW_REG_OFFLOAD_IND, hdd_ctx->config->ignore_fw_reg_offload_ind); + hdd_debug("Name = [%s] Value = [%u]", + CFG_NAN_NDP_INACTIVITY_TIMEOUT, + hdd_ctx->config->ndp_inactivity_timeout); + + hdd_debug("Name = [%s] Value = [%u]", + CFG_MGMT_RETRY_MAX, + hdd_ctx->config->mgmt_retry_max); + + hdd_debug("Name = [%s] Value = [%u]", + CFG_ENABLE_PENDING_CHAN_LIST_REQ, + hdd_ctx->config->enable_pending_list_req); + + hdd_debug("Name = [%s] Value = [%u]", + CFG_ENABLE_RING_BUFFER, + hdd_ctx->config->enable_ring_buffer); + hdd_debug("Name = [num_vdevs] value = [0x%x]", + hdd_ctx->config->num_vdevs); + hdd_debug("Name = [%s] Value =[%x]", + CFG_PKT_CAPTURE_MODE, + hdd_ctx->config->pkt_capture_mode); + hdd_debug("Name = [%s] value = [%d]", + CFG_DISABLE_4WAY_HS_OFFLOAD, + hdd_ctx->config->disable_4way_hs_offload); +#ifdef FEATURE_WLAN_TIME_SYNC_FTM + hdd_debug("Name = [%s] Value =[%d]", + CFG_ENABLE_TIME_SYNC_FTM, + hdd_ctx->config->time_sync_ftm_enable); + hdd_debug("Name = [%s] Value =[%d]", + CFG_TIME_SYNC_FTM_MODE, + hdd_ctx->config->time_sync_ftm_mode); + hdd_debug("Name = [%s] Value =[%d]", + CFG_TIME_SYNC_FTM_ROLE, + hdd_ctx->config->time_sync_ftm_role); +#endif + hdd_debug("Name = [%s] value = [%d]", + CFG_P2P_DISABLE_ROAM, + hdd_ctx->config->p2p_disable_roam); } /** @@ -8400,7 +8832,7 @@ QDF_STATUS hdd_set_idle_ps_config(struct hdd_context *hdd_ctx, bool val) hdd_debug("Enter Val %d", val); if (hdd_ctx->imps_enabled == val) { - hdd_info("Already in the requested power state:%d", val); + hdd_nofl_debug("Already in the requested power state:%d", val); return QDF_STATUS_SUCCESS; } @@ -8626,16 +9058,15 @@ static bool hdd_update_vht_cap_in_cfg(struct hdd_context *hdd_ctx) if ((config->dot11Mode == eHDD_DOT11_MODE_AUTO) || (config->dot11Mode == eHDD_DOT11_MODE_11ac_ONLY) || (config->dot11Mode == eHDD_DOT11_MODE_11ac)) { - /* Currently shortGI40Mhz is used for shortGI80Mhz and 160MHz*/ if (sme_cfg_set_int(mac_handle, WNI_CFG_VHT_SHORT_GI_80MHZ, - config->ShortGI40MhzEnable) == QDF_STATUS_E_FAILURE) { + config->ShortGI80MhzEnable) == QDF_STATUS_E_FAILURE) { status = false; hdd_err("Couldn't pass WNI_VHT_SHORT_GI_80MHZ to CFG"); } if (sme_cfg_set_int(mac_handle, WNI_CFG_VHT_SHORT_GI_160_AND_80_PLUS_80MHZ, - config->ShortGI40MhzEnable) == QDF_STATUS_E_FAILURE) { + config->ShortGI160MhzEnable) == QDF_STATUS_E_FAILURE) { status = false; hdd_err("Couldn't pass SHORT_GI_160MHZ to CFG"); } @@ -9191,6 +9622,8 @@ static void hdd_update_bss_score_params(struct hdd_config *config, score_params->weight_cfg.channel_congestion_weightage = config->channel_congestion_weightage; score_params->weight_cfg.oce_wan_weightage = config->oce_wan_weightage; + score_params->weight_cfg.vendor_roam_score_algorithm = + config->vendor_roam_score_algorithm; total_weight = score_params->weight_cfg.rssi_weightage + score_params->weight_cfg.ht_caps_weightage + @@ -9235,6 +9668,8 @@ static void hdd_update_bss_score_params(struct hdd_config *config, hdd_limit_max_per_index_score(config->band_weight_per_index); score_params->roam_score_delta = config->roam_score_delta; + score_params->cand_min_roam_score_delta = + config->min_roam_score_delta; score_params->roam_score_delta_bitmap = config->roam_score_delta_bitmap; score_params->rssi_score.best_rssi_threshold = @@ -9349,6 +9784,38 @@ static void sme_update_beacon_stats(mac_handle_t mac_handle, mac_ctx->enable_beacon_reception_stats = enable_beacon_reception_stats; } +#ifdef WLAN_ADAPTIVE_11R +static void +sme_update_adaptive_11r_cap(tSmeConfigParams *sme_config, + struct hdd_config *ini_config) +{ + sme_config->csrConfig.enable_adaptive_11r = + ini_config->enable_adaptive_11r; +} +#else +static inline void +sme_update_adaptive_11r_cap(tSmeConfigParams *sme_config, + struct hdd_config *ini_config) +{ +} +#endif + +#if defined(WLAN_SAE_SINGLE_PMK) && defined(WLAN_FEATURE_ROAM_OFFLOAD) +static void +sme_update_sae_single_pmk_cfg(tSmeConfigParams *sme_config, + struct hdd_config *ini_config) +{ + sme_config->csrConfig.sae_single_pmk_feature_enabled = + ini_config->sae_single_pmk_feature_enabled; +} +#else +static inline void +sme_update_sae_single_pmk_cfg(tSmeConfigParams *sme_config, + struct hdd_config *ini_config) +{ +} +#endif + /** * hdd_set_sme_config() -initializes the sme configuration parameters * @@ -9616,6 +10083,22 @@ QDF_STATUS hdd_set_sme_config(struct hdd_context *hdd_ctx) #ifdef WLAN_FEATURE_ROAM_OFFLOAD smeConfig->csrConfig.isRoamOffloadEnabled = hdd_ctx->config->isRoamOffloadEnabled; + smeConfig->csrConfig.roam_triggers = + hdd_ctx->config->roam_triggers; + smeConfig->csrConfig.enable_disconnect_roam_offload = + hdd_ctx->config->enable_disconnect_roam_offload; + smeConfig->csrConfig.enable_idle_roam = + hdd_ctx->config->enable_idle_roam; + smeConfig->csrConfig.idle_roam_rssi_delta = + hdd_ctx->config->idle_roam_rssi_delta; + smeConfig->csrConfig.idle_roam_inactive_time = + hdd_ctx->config->idle_roam_inactive_time; + smeConfig->csrConfig.idle_data_packet_count = + hdd_ctx->config->idle_data_packet_count; + smeConfig->csrConfig.idle_roam_band = + hdd_ctx->config->idle_roam_band; + smeConfig->csrConfig.idle_roam_min_rssi = + hdd_ctx->config->idle_roam_min_rssi; #endif smeConfig->csrConfig.conc_custom_rule1 = hdd_ctx->config->conc_custom_rule1; @@ -9840,12 +10323,19 @@ QDF_STATUS hdd_set_sme_config(struct hdd_context *hdd_ctx) hdd_ctx->config->mbo_candidate_rssi_btc_thres; smeConfig->csrConfig.btm_offload_config = hdd_ctx->config->btm_offload_config; + smeConfig->csrConfig.pmkid_modes = hdd_ctx->config->pmkid_modes; + smeConfig->csrConfig.btm_solicited_timeout = hdd_ctx->config->btm_solicited_timeout; smeConfig->csrConfig.btm_max_attempt_cnt = hdd_ctx->config->btm_max_attempt_cnt; smeConfig->csrConfig.btm_sticky_time = hdd_ctx->config->btm_sticky_time; + smeConfig->csrConfig.btm_query_bitmask = + hdd_ctx->config->btm_query_bitmask; + smeConfig->csrConfig.disable_4way_hs_offload = + hdd_ctx->config->disable_4way_hs_offload; + hdd_update_bss_score_params(hdd_ctx->config, &smeConfig->csrConfig.bss_score_params); @@ -9870,7 +10360,33 @@ QDF_STATUS hdd_set_sme_config(struct hdd_context *hdd_ctx) smeConfig->csrConfig.bss_load_threshold = pConfig->bss_load_threshold; smeConfig->csrConfig.bss_load_sample_time = pConfig->bss_load_sample_time; - + smeConfig->csrConfig.bss_load_trigger_rssi_threshold_5ghz = + pConfig->bss_load_trigger_rssi_threshold_5ghz; + smeConfig->csrConfig.bss_load_trigger_rssi_threshold_24ghz = + pConfig->bss_load_trigger_rssi_threshold_24ghz; + + smeConfig->csrConfig.roam_scan_inactivity_time = + pConfig->roam_scan_inactivity_time; + smeConfig->csrConfig.roam_inactive_data_packet_count = + pConfig->roam_inactive_data_packet_count; + smeConfig->csrConfig.roam_scan_period_after_inactivity = + pConfig->roam_scan_period_after_inactivity; + smeConfig->csrConfig.disconnect_roam_min_rssi = + pConfig->disconnect_roam_min_rssi; + smeConfig->csrConfig.bmiss_roam_min_rssi = + pConfig->bmiss_roam_min_rssi; + smeConfig->csrConfig.btm_roam_score_delta = + pConfig->btm_roam_score_delta; + smeConfig->csrConfig.idle_roam_score_delta = + pConfig->idle_roam_score_delta; + smeConfig->csrConfig.btm_trig_min_candidate_score = + pConfig->btm_trig_min_candidate_score; + smeConfig->csrConfig.enable_pending_list_req = + pConfig->enable_pending_list_req; + smeConfig->csrConfig.p2p_disable_roam = + pConfig->p2p_disable_roam; + sme_update_adaptive_11r_cap(smeConfig, pConfig); + sme_update_sae_single_pmk_cfg(smeConfig, pConfig); sme_update_beacon_stats(mac_handle, hdd_ctx->config->enable_beacon_reception_stats); diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_cfg80211.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_cfg80211.c index a74311de1a29..42565905db56 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_cfg80211.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_cfg80211.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -113,6 +113,7 @@ #include "wlan_hdd_coex_config.h" #include "wlan_hdd_hw_capability.h" #include "wlan_hdd_bcn_recv.h" +#include "wlan_hdd_oemdata.h" #define g_mode_rates_size (12) #define a_mode_rates_size (8) @@ -939,6 +940,8 @@ int wlan_hdd_send_hang_reason_event(struct hdd_context *hdd_ctx, { struct sk_buff *vendor_event; enum qca_wlan_vendor_hang_reason hang_reason; + struct hdd_adapter *sta_adapter; + struct wireless_dev *wdev = NULL; hdd_enter(); @@ -947,8 +950,12 @@ int wlan_hdd_send_hang_reason_event(struct hdd_context *hdd_ctx, return -EINVAL; } + sta_adapter = hdd_get_adapter(hdd_ctx, QDF_STA_MODE); + if (sta_adapter) + wdev = &(sta_adapter->wdev); + vendor_event = cfg80211_vendor_event_alloc(hdd_ctx->wiphy, - NULL, + wdev, sizeof(uint32_t), HANG_REASON_INDEX, GFP_KERNEL); @@ -1450,6 +1457,18 @@ static const struct nl80211_vendor_cmd_info wlan_hdd_cfg80211_vendor_events[] = .vendor_id = QCA_NL80211_VENDOR_ID, .subcmd = QCA_NL80211_VENDOR_SUBCMD_ROAM, }, + [QCA_NL80211_VENDOR_SUBCMD_OEM_DATA_INDEX] = { + .vendor_id = QCA_NL80211_VENDOR_ID, + .subcmd = QCA_NL80211_VENDOR_SUBCMD_OEM_DATA, + }, + [QCA_NL80211_VENDOR_SUBCMD_REQUEST_SAR_LIMITS_INDEX] = { + .vendor_id = QCA_NL80211_VENDOR_ID, + .subcmd = QCA_NL80211_VENDOR_SUBCMD_GET_SAR_LIMITS_EVENT, + }, + [QCA_NL80211_VENDOR_SUBCMD_UPDATE_STA_INFO_INDEX] = { + .vendor_id = QCA_NL80211_VENDOR_ID, + .subcmd = QCA_NL80211_VENDOR_SUBCMD_UPDATE_STA_INFO, + } }; /** @@ -1812,7 +1831,6 @@ int wlan_hdd_cfg80211_start_acs(struct hdd_adapter *adapter) qdf_mem_copy(sap_config->self_macaddr.bytes, adapter->mac_addr.bytes, sizeof(struct qdf_mac_addr)); - hdd_info("ACS Started for %s", adapter->dev->name); status = wlansap_acs_chselect( WLAN_HDD_GET_SAP_CTX_PTR(adapter), acs_event_callback, sap_config, adapter->dev); @@ -2411,8 +2429,6 @@ static int __wlan_hdd_cfg80211_do_acs(struct wiphy *wiphy, * config shall be set only from start_acs. */ - hdd_enter_dev(ndev); - if (QDF_GLOBAL_FTM_MODE == hdd_get_conparam()) { hdd_err("Command not allowed in FTM mode"); return -EPERM; @@ -2422,8 +2438,6 @@ static int __wlan_hdd_cfg80211_do_acs(struct wiphy *wiphy, if (ret) return ret; - hdd_debug("current country is %s", hdd_ctx->reg.alpha2); - if (!((adapter->device_mode == QDF_SAP_MODE) || (adapter->device_mode == QDF_P2P_GO_MODE))) { hdd_err("Invalid device mode %d", adapter->device_mode); @@ -2440,6 +2454,7 @@ static int __wlan_hdd_cfg80211_do_acs(struct wiphy *wiphy, return -EINVAL; } else { qdf_atomic_set(&adapter->session.ap.acs_in_progress, 1); + qdf_event_reset(&adapter->acs_complete_event); } ret = wlan_cfg80211_nla_parse(tb, QCA_WLAN_VENDOR_ATTR_ACS_MAX, data, @@ -2457,6 +2472,8 @@ static int __wlan_hdd_cfg80211_do_acs(struct wiphy *wiphy, } hw_mode = nla_get_u8(tb[QCA_WLAN_VENDOR_ATTR_ACS_HW_MODE]); + hdd_nofl_info("ACS request vid %d hw mode %d", adapter->session_id, + hw_mode); if (tb[QCA_WLAN_VENDOR_ATTR_ACS_HT_ENABLED]) ht_enabled = nla_get_flag(tb[QCA_WLAN_VENDOR_ATTR_ACS_HT_ENABLED]); @@ -2469,7 +2486,6 @@ static int __wlan_hdd_cfg80211_do_acs(struct wiphy *wiphy, else ht40_enabled = 0; - hdd_debug("ht40_enabled %d", ht40_enabled); if (tb[QCA_WLAN_VENDOR_ATTR_ACS_VHT_ENABLED]) vht_enabled = nla_get_flag(tb[QCA_WLAN_VENDOR_ATTR_ACS_VHT_ENABLED]); @@ -2511,7 +2527,6 @@ static int __wlan_hdd_cfg80211_do_acs(struct wiphy *wiphy, qdf_mem_zero(&sap_config->acs_cfg, sizeof(struct sap_acs_cfg)); sap_config->acs_cfg.dfs_master_mode = hdd_ctx->config->enableDFSMasterCap; - hdd_debug("channel width =%d", ch_width); if (ch_width == 160) sap_config->acs_cfg.ch_width = CH_WIDTH_160MHZ; else if (ch_width == 80) @@ -2605,7 +2620,6 @@ static int __wlan_hdd_cfg80211_do_acs(struct wiphy *wiphy, } sap_config->acs_cfg.ch_list_count = ch_cnt; } - hdd_debug("get pcl for DO_ACS vendor command"); /* consult policy manager to get PCL */ qdf_status = policy_mgr_get_pcl(hdd_ctx->psoc, PM_SAP_MODE, @@ -2613,19 +2627,6 @@ static int __wlan_hdd_cfg80211_do_acs(struct wiphy *wiphy, &sap_config->acs_cfg.pcl_ch_count, sap_config->acs_cfg.pcl_channels_weight_list, QDF_MAX_NUM_CHAN); - if (qdf_status != QDF_STATUS_SUCCESS) - hdd_err("Get PCL failed"); - - if (sap_config->acs_cfg.pcl_ch_count) { - hdd_debug("ACS config PCL: len: %d", - sap_config->acs_cfg.pcl_ch_count); - for (i = 0; i < sap_config->acs_cfg.pcl_ch_count; i++) - hdd_debug("channel:%d, weight:%d ", - sap_config->acs_cfg. - pcl_channels[i], - sap_config->acs_cfg. - pcl_channels_weight_list[i]); - } if (hw_mode == QCA_ACS_MODE_IEEE80211ANY) policy_mgr_trim_acs_channel_list(hdd_ctx->psoc, @@ -2664,11 +2665,13 @@ static int __wlan_hdd_cfg80211_do_acs(struct wiphy *wiphy, hdd_debug("resetting to 40Mhz in 2.4Ghz"); } - hdd_debug("ACS Config for %s: HW_MODE: %d ACS_BW: %d HT: %d VHT: %d START_CH: %d END_CH: %d band %d", - adapter->dev->name, sap_config->acs_cfg.hw_mode, - sap_config->acs_cfg.ch_width, ht_enabled, vht_enabled, - sap_config->acs_cfg.start_ch, sap_config->acs_cfg.end_ch, - sap_config->acs_cfg.band); + hdd_nofl_debug("ACS Config country %s ch_width %d hw_mode %d ACS_BW: %d HT: %d VHT: %d START_CH: %d END_CH: %d band %d", + hdd_ctx->reg.alpha2, ch_width, + sap_config->acs_cfg.hw_mode, + sap_config->acs_cfg.ch_width, + ht_enabled, vht_enabled, sap_config->acs_cfg.start_ch, + sap_config->acs_cfg.end_ch, + sap_config->acs_cfg.band); host_log_acs_req_event(adapter->dev->name, csr_phy_mode_str(sap_config->acs_cfg.hw_mode), ch_width, ht_enabled, vht_enabled, @@ -2681,13 +2684,7 @@ static int __wlan_hdd_cfg80211_do_acs(struct wiphy *wiphy, sap_config->acs_cfg.is_ht_enabled = ht_enabled; sap_config->acs_cfg.is_vht_enabled = vht_enabled; - if (sap_config->acs_cfg.ch_list_count) { - hdd_debug("ACS channel list: len: %d", - sap_config->acs_cfg.ch_list_count); - for (i = 0; i < sap_config->acs_cfg.ch_list_count; i++) - hdd_debug("%d ", sap_config->acs_cfg.ch_list[i]); - } - + sap_dump_acs_channel(&sap_config->acs_cfg); conc_channel = policy_mgr_mode_specific_get_channel(hdd_ctx->psoc, PM_STA_MODE); if ((hdd_ctx->config->external_acs_policy == @@ -3920,6 +3917,8 @@ roam_control_policy[QCA_ATTR_ROAM_CONTROL_MAX + 1] = { [QCA_ATTR_ROAM_CONTROL_STATUS] = {.type = NLA_U8}, [PARAM_FREQ_LIST_SCHEME] = {.type = NLA_NESTED}, [QCA_ATTR_ROAM_CONTROL_FULL_SCAN_PERIOD] = {.type = NLA_U32}, + [QCA_ATTR_ROAM_CONTROL_CLEAR_ALL] = {.type = NLA_FLAG}, + [QCA_ATTR_ROAM_CONTROL_TRIGGERS] = {.type = NLA_U32}, [QCA_ATTR_ROAM_CONTROL_SELECTION_CRITERIA] = {.type = NLA_NESTED}, [QCA_ATTR_ROAM_CONTROL_SCAN_PERIOD] = {.type = NLA_U32}, }; @@ -3949,8 +3948,8 @@ hdd_send_roam_full_scan_period_to_sme(struct hdd_context *hdd_ctx, QDF_STATUS status; uint32_t full_roam_scan_period_current, full_roam_scan_period_global; - if (full_roam_scan_period < CFG_FULL_ROAM_SCAN_REFRESH_PERIOD_MIN - || full_roam_scan_period > CFG_FAST_TRANSITION_ENABLED_NAME_MAX) { + if (full_roam_scan_period < CFG_FULL_ROAM_SCAN_REFRESH_PERIOD_MIN || + full_roam_scan_period > CFG_FULL_ROAM_SCAN_REFRESH_PERIOD_MAX) { hdd_err("Full roam scan period value %d is out of range (Min: %d Max: %d)", full_roam_scan_period, CFG_FULL_ROAM_SCAN_REFRESH_PERIOD_MIN, @@ -4141,6 +4140,82 @@ hdd_send_roam_scan_period_to_sme(struct hdd_context *hdd_ctx, return status; } +/** + * wlan_hdd_convert_control_roam_trigger_reason_bitmap - Convert the + * vendor specific reason code to internal reason code. + * @trigger_reason_bitmap: Vendor specific roam trigger bitmap + * + * Return: Internal roam trigger bitmap + */ +static uint32_t +wlan_hdd_convert_control_roam_trigger_bitmap(uint32_t trigger_reason_bitmap) +{ + uint32_t drv_trigger_bitmap = 0, all_bitmap; + + /* Enable the complete trigger bitmap when all bits are set in + * the control config bitmap + */ + all_bitmap = (QCA_ROAM_TRIGGER_REASON_BSS_LOAD << 1) - 1; + if (trigger_reason_bitmap == all_bitmap) + return BIT(ROAM_TRIGGER_REASON_MAX) - 1; + + if (trigger_reason_bitmap & QCA_ROAM_TRIGGER_REASON_PER) + drv_trigger_bitmap |= BIT(ROAM_TRIGGER_REASON_PER); + + if (trigger_reason_bitmap & QCA_ROAM_TRIGGER_REASON_BEACON_MISS) + drv_trigger_bitmap |= BIT(ROAM_TRIGGER_REASON_BMISS); + + if (trigger_reason_bitmap & QCA_ROAM_TRIGGER_REASON_POOR_RSSI) + drv_trigger_bitmap |= BIT(ROAM_TRIGGER_REASON_LOW_RSSI); + + if (trigger_reason_bitmap & QCA_ROAM_TRIGGER_REASON_BETTER_RSSI) + drv_trigger_bitmap |= BIT(ROAM_TRIGGER_REASON_HIGH_RSSI); + + if (trigger_reason_bitmap & QCA_ROAM_TRIGGER_REASON_PERIODIC) + drv_trigger_bitmap |= BIT(ROAM_TRIGGER_REASON_PERIODIC); + + if (trigger_reason_bitmap & QCA_ROAM_TRIGGER_REASON_DENSE) + drv_trigger_bitmap |= BIT(ROAM_TRIGGER_REASON_DENSE); + + if (trigger_reason_bitmap & QCA_ROAM_TRIGGER_REASON_BTM) + drv_trigger_bitmap |= BIT(ROAM_TRIGGER_REASON_BTM); + + if (trigger_reason_bitmap & QCA_ROAM_TRIGGER_REASON_BSS_LOAD) + drv_trigger_bitmap |= BIT(ROAM_TRIGGER_REASON_BSS_LOAD); + + return drv_trigger_bitmap; +} + +/** + * hdd_send_roam_triggers_to_sme() - Send roam trigger bitmap to SME + * @hdd_ctx: HDD context + * @vdev_id: vdev id + * @roam_trigger_bitmap: Vendor configured roam trigger bitmap to be configured + * to firmware + * + * Send the roam trigger bitmap received to SME + * + * Return: QDF_STATUS + */ +static QDF_STATUS +hdd_send_roam_triggers_to_sme(struct hdd_context *hdd_ctx, + uint8_t vdev_id, + uint32_t roam_trigger_bitmap) +{ + QDF_STATUS status; + struct roam_triggers triggers; + + triggers.vdev_id = vdev_id; + triggers.trigger_bitmap = + wlan_hdd_convert_control_roam_trigger_bitmap(roam_trigger_bitmap); + + status = sme_set_roam_triggers(hdd_ctx->mac_handle, &triggers); + if (QDF_IS_STATUS_ERROR(status)) + hdd_err("Failed to set roam control trigger bitmap"); + + return status; +} + /** * hdd_set_roam_with_control_config() - Set roam control configuration * @hdd_ctx: HDD context @@ -4186,16 +4261,17 @@ hdd_set_roam_with_control_config(struct hdd_context *hdd_ctx, attr = tb2[QCA_ATTR_ROAM_CONTROL_ENABLE]; if (attr) { - hdd_debug("Parse and send roam control enable/disable"); status = sme_set_roam_config_enable(hdd_ctx->mac_handle, vdev_id, nla_get_u8(attr)); if (QDF_IS_STATUS_ERROR(status)) hdd_err("failed to enable/disable roam control config"); + hdd_debug("Parse and send roam control %s:", + nla_get_u8(attr) ? "Enable" : "Disable"); + attr = tb2[QCA_ATTR_ROAM_CONTROL_SCAN_PERIOD]; if (attr) { - hdd_debug("Parse and send scan period to firmware"); /* Default value received as part of Roam control enable * Set this only if user hasn't configured any value so * far. @@ -4210,7 +4286,6 @@ hdd_set_roam_with_control_config(struct hdd_context *hdd_ctx, attr = tb2[QCA_ATTR_ROAM_CONTROL_FULL_SCAN_PERIOD]; if (attr) { - hdd_debug("Parse and send full scan period to firmware"); value = nla_get_u32(attr); /* Default value received as part of Roam control enable * Set this only if user hasn't configured any value so @@ -4226,7 +4301,6 @@ hdd_set_roam_with_control_config(struct hdd_context *hdd_ctx, } else { attr = tb2[QCA_ATTR_ROAM_CONTROL_SCAN_PERIOD]; if (attr) { - hdd_debug("Parse and send scan period to firmware"); /* User configured value, cache the value directly */ value = nla_get_u32(attr); status = hdd_send_roam_scan_period_to_sme(hdd_ctx, @@ -4238,7 +4312,6 @@ hdd_set_roam_with_control_config(struct hdd_context *hdd_ctx, attr = tb2[QCA_ATTR_ROAM_CONTROL_FULL_SCAN_PERIOD]; if (attr) { - hdd_debug("Parse and send full scan period to firmware"); value = nla_get_u32(attr); /* User configured value, cache the value directly */ status = hdd_send_roam_full_scan_period_to_sme(hdd_ctx, @@ -4253,13 +4326,22 @@ hdd_set_roam_with_control_config(struct hdd_context *hdd_ctx, /* Scoring and roam candidate selection criteria */ attr = tb2[QCA_ATTR_ROAM_CONTROL_SELECTION_CRITERIA]; if (attr) { - hdd_debug("Send candidate selection criteria to firmware"); status = hdd_send_roam_cand_sel_criteria_to_sme(hdd_ctx, vdev_id, attr); if (QDF_IS_STATUS_ERROR(status)) hdd_err("failed to set candidate selection criteria"); } + if (tb2[QCA_ATTR_ROAM_CONTROL_TRIGGERS]) { + value = nla_get_u32(tb2[QCA_ATTR_ROAM_CONTROL_TRIGGERS]); + hdd_debug("Received roam trigger bitmap: 0x%x", value); + status = hdd_send_roam_triggers_to_sme(hdd_ctx, + vdev_id, + value); + if (status) + hdd_err("failed to config roam triggers"); + } + return qdf_status_to_os_return(status); } @@ -4310,8 +4392,10 @@ hdd_roam_control_config_fill_data(struct hdd_context *hdd_ctx, uint8_t vdev_id, uint32_t full_roam_scan_period; config = nla_nest_start(skb, PARAM_ROAM_CONTROL_CONFIG); - if (!config) + if (!config) { + hdd_err("nla nest start failure"); return -EINVAL; + } if (tb[QCA_ATTR_ROAM_CONTROL_STATUS]) { status = sme_get_roam_config_status(hdd_ctx->mac_handle, @@ -4368,7 +4452,6 @@ hdd_send_roam_control_config(struct hdd_context *hdd_ctx, uint16_t skb_len; int status; - hdd_enter(); skb_len = hdd_roam_control_config_buf_size(hdd_ctx, tb); if (!skb_len) { hdd_err("No data requested"); @@ -4386,7 +4469,6 @@ hdd_send_roam_control_config(struct hdd_context *hdd_ctx, if (status) goto fail; - hdd_exit(); return cfg80211_vendor_cmd_reply(skb); fail: @@ -4410,7 +4492,6 @@ static int hdd_get_roam_control_config(struct hdd_context *hdd_ctx, QDF_STATUS status; struct nlattr *tb2[QCA_ATTR_ROAM_CONTROL_MAX + 1]; - hdd_enter(); /* The command must carry PARAM_ROAM_CONTROL_CONFIG */ if (!tb[PARAM_ROAM_CONTROL_CONFIG]) { hdd_err("Attribute CONTROL_CONFIG is not present"); @@ -4433,6 +4514,67 @@ static int hdd_get_roam_control_config(struct hdd_context *hdd_ctx, return qdf_status_to_os_return(status); } +#define ENABLE_ROAM_TRIGGERS_ALL (QCA_ROAM_TRIGGER_REASON_PER | \ + QCA_ROAM_TRIGGER_REASON_BEACON_MISS | \ + QCA_ROAM_TRIGGER_REASON_POOR_RSSI | \ + QCA_ROAM_TRIGGER_REASON_BETTER_RSSI | \ + QCA_ROAM_TRIGGER_REASON_PERIODIC | \ + QCA_ROAM_TRIGGER_REASON_DENSE | \ + QCA_ROAM_TRIGGER_REASON_BTM | \ + QCA_ROAM_TRIGGER_REASON_BSS_LOAD) + +static int +hdd_clear_roam_control_config(struct hdd_context *hdd_ctx, + struct nlattr **tb, + uint8_t vdev_id) +{ + QDF_STATUS status; + struct nlattr *tb2[QCA_ATTR_ROAM_CONTROL_MAX + 1]; + mac_handle_t mac_handle = hdd_ctx->mac_handle; + uint32_t value; + + /* The command must carry PARAM_ROAM_CONTROL_CONFIG */ + if (!tb[PARAM_ROAM_CONTROL_CONFIG]) { + hdd_err("Attribute CONTROL_CONFIG is not present"); + return -EINVAL; + } + + if (wlan_cfg80211_nla_parse_nested(tb2, QCA_ATTR_ROAM_CONTROL_MAX, + tb[PARAM_ROAM_CONTROL_CONFIG], + roam_control_policy)) { + hdd_err("nla_parse failed"); + return -EINVAL; + } + + hdd_debug("Clear the control config done through SET"); + if (tb2[QCA_ATTR_ROAM_CONTROL_CLEAR_ALL]) { + hdd_debug("Disable roam control config done through SET"); + status = sme_set_roam_config_enable(hdd_ctx->mac_handle, + vdev_id, 0); + if (QDF_IS_STATUS_ERROR(status)) { + hdd_err("failed to enable/disable roam control config"); + return qdf_status_to_os_return(status); + } + + value = ENABLE_ROAM_TRIGGERS_ALL; + hdd_debug("Reset roam trigger bitmap to 0x%x", value); + status = hdd_send_roam_triggers_to_sme(hdd_ctx, vdev_id, value); + if (QDF_IS_STATUS_ERROR(status)) { + hdd_err("failed to restore roam trigger bitmap"); + return qdf_status_to_os_return(status); + } + + status = sme_roam_control_restore_default_config(mac_handle, + vdev_id); + if (QDF_IS_STATUS_ERROR(status)) { + hdd_err("failed to config roam control"); + return qdf_status_to_os_return(status); + } + } + + return 0; +} + #undef PARAM_ROAM_CONTROL_CONFIG #undef PARAM_FREQ_LIST_SCHEME_MAX #undef PARAM_FREQ_LIST_SCHEME @@ -4590,6 +4732,11 @@ static int hdd_set_ext_roam_params(struct hdd_context *hdd_ctx, if (ret) goto fail; break; + case QCA_WLAN_VENDOR_ROAMING_SUBCMD_CONTROL_CLEAR: + ret = hdd_clear_roam_control_config(hdd_ctx, tb, session_id); + if (ret) + goto fail; + break; } return 0; @@ -4620,8 +4767,6 @@ __wlan_hdd_cfg80211_set_ext_roam_params(struct wiphy *wiphy, struct roam_ext_params *roam_params = NULL; int ret; - hdd_enter_dev(dev); - if (QDF_GLOBAL_FTM_MODE == hdd_get_conparam()) { hdd_err("Command not allowed in FTM mode"); return -EPERM; @@ -5122,6 +5267,12 @@ static int wlan_hdd_cfg80211_handle_wisa_cmd(struct wiphy *wiphy, #define REMOTE_PAD\ QCA_WLAN_VENDOR_ATTR_GET_STATION_INFO_PAD #endif +#define DISCONNECT_REASON \ + QCA_WLAN_VENDOR_ATTR_GET_STATION_INFO_DRIVER_DISCONNECT_REASON +#define BEACON_IES \ + QCA_WLAN_VENDOR_ATTR_GET_STATION_INFO_BEACON_IES +#define ASSOC_REQ_IES \ + QCA_WLAN_VENDOR_ATTR_GET_STATION_INFO_ASSOC_REQ_IES static const struct nla_policy hdd_get_station_policy[STATION_MAX + 1] = { @@ -5531,9 +5682,10 @@ static int hdd_get_station_info(struct hdd_context *hdd_ctx, struct hdd_adapter *adapter) { struct sk_buff *skb = NULL; - uint8_t *tmp_hs20 = NULL; - uint32_t nl_buf_len; + uint8_t *tmp_hs20 = NULL, *ies = NULL; + uint32_t nl_buf_len, ie_len = 0; struct hdd_station_ctx *hdd_sta_ctx; + QDF_STATUS status; hdd_sta_ctx = WLAN_HDD_GET_STATION_CTX_PTR(adapter); @@ -5548,7 +5700,8 @@ static int hdd_get_station_info(struct hdd_context *hdd_ctx, sizeof(hdd_sta_ctx->cache_conn_info.txrate.nss) + sizeof(hdd_sta_ctx->cache_conn_info.roam_count) + sizeof(hdd_sta_ctx->cache_conn_info.last_auth_type) + - sizeof(hdd_sta_ctx->cache_conn_info.dot11Mode); + sizeof(hdd_sta_ctx->cache_conn_info.dot11Mode) + + sizeof(uint32_t); if (hdd_sta_ctx->cache_conn_info.conn_flag.vht_present) nl_buf_len += sizeof(hdd_sta_ctx->cache_conn_info.vht_caps); if (hdd_sta_ctx->cache_conn_info.conn_flag.ht_present) @@ -5565,7 +5718,11 @@ static int hdd_get_station_info(struct hdd_context *hdd_ctx, if (hdd_sta_ctx->cache_conn_info.conn_flag.vht_op_present) nl_buf_len += sizeof(hdd_sta_ctx-> cache_conn_info.vht_operation); - + status = sme_get_prev_connected_bss_ies(hdd_ctx->mac_handle, + adapter->session_id, + &ies, &ie_len); + if (QDF_IS_STATUS_SUCCESS(status)) + nl_buf_len += ie_len; skb = cfg80211_vendor_cmd_alloc_reply_skb(hdd_ctx->wiphy, nl_buf_len); if (!skb) { @@ -5618,10 +5775,27 @@ static int hdd_get_station_info(struct hdd_context *hdd_ctx, goto fail; } + if (nla_put_u32(skb, DISCONNECT_REASON, + adapter->last_disconnect_reason)) { + hdd_err("Failed to put disconect reason"); + goto fail; + } + + if (ie_len) { + if (nla_put(skb, BEACON_IES, ie_len, ies)) { + hdd_err("Failed to put beacon IEs"); + goto fail; + } + qdf_mem_free(ies); + ie_len = 0; + } + return cfg80211_vendor_cmd_reply(skb); fail: if (skb) kfree_skb(skb); + qdf_mem_free(ies); + ie_len = 0; return -EINVAL; } @@ -5785,7 +5959,8 @@ static int32_t hdd_add_sta_info_sap(struct sk_buff *skb, int8_t rssi, if (!nla_attr) goto fail; - if (nla_put_u8(skb, NL80211_STA_INFO_SIGNAL, rssi)) { + if (nla_put_u8(skb, NL80211_STA_INFO_SIGNAL, + rssi - HDD_NOISE_FLOOR_DBM)) { hdd_err("put fail"); goto fail; } @@ -5981,6 +6156,8 @@ static int hdd_get_cached_station_remote(struct hdd_context *hdd_ctx, (sizeof(stainfo->tx_rate) + NLA_HDRLEN) + (sizeof(stainfo->rx_rate) + NLA_HDRLEN) + (sizeof(stainfo->support_mode) + NLA_HDRLEN); + if (stainfo->assoc_req_ies.len) + nl_buf_len += stainfo->assoc_req_ies.len + NLA_HDRLEN; skb = cfg80211_vendor_cmd_alloc_reply_skb(hdd_ctx->wiphy, nl_buf_len); if (!skb) { @@ -6021,6 +6198,16 @@ static int hdd_get_cached_station_remote(struct hdd_context *hdd_ctx, hdd_err("dot11 mode put fail"); goto fail; } + if (stainfo->assoc_req_ies.len) { + if (nla_put(skb, ASSOC_REQ_IES, stainfo->assoc_req_ies.len, + stainfo->assoc_req_ies.data)) { + hdd_err("Failed to put assoc req IEs"); + goto fail; + } + qdf_mem_free(stainfo->assoc_req_ies.data); + stainfo->assoc_req_ies.data = NULL; + stainfo->assoc_req_ies.len = 0; + } qdf_mem_zero(stainfo, sizeof(*stainfo)); @@ -6028,6 +6215,9 @@ static int hdd_get_cached_station_remote(struct hdd_context *hdd_ctx, fail: if (skb) kfree_skb(skb); + qdf_mem_free(stainfo->assoc_req_ies.data); + stainfo->assoc_req_ies.data = NULL; + stainfo->assoc_req_ies.len = 0; return -EINVAL; } @@ -6594,12 +6784,16 @@ __wlan_hdd_cfg80211_get_logger_supp_feature(struct wiphy *wiphy, return status; features = 0; - - features |= WIFI_LOGGER_PER_PACKET_TX_RX_STATUS_SUPPORTED; - features |= WIFI_LOGGER_CONNECT_EVENT_SUPPORTED; - features |= WIFI_LOGGER_WAKE_LOCK_SUPPORTED; - features |= WIFI_LOGGER_DRIVER_DUMP_SUPPORTED; - features |= WIFI_LOGGER_PACKET_FATE_SUPPORTED; + if (hdd_ctx->config->enable_ring_buffer) { + features |= WIFI_LOGGER_PER_PACKET_TX_RX_STATUS_SUPPORTED; + features |= WIFI_LOGGER_CONNECT_EVENT_SUPPORTED; + features |= WIFI_LOGGER_WAKE_LOCK_SUPPORTED; + features |= WIFI_LOGGER_DRIVER_DUMP_SUPPORTED; + features |= WIFI_LOGGER_PACKET_FATE_SUPPORTED; + hdd_debug("Supported logger features: 0x%0x", features); + } else { + hdd_debug("Ring buffer disabled"); + } reply_skb = cfg80211_vendor_cmd_alloc_reply_skb(wiphy, sizeof(uint32_t) + NLA_HDRLEN + NLMSG_HDRLEN); @@ -6608,7 +6802,6 @@ __wlan_hdd_cfg80211_get_logger_supp_feature(struct wiphy *wiphy, return -ENOMEM; } - hdd_debug("Supported logger features: 0x%0x", features); if (nla_put_u32(reply_skb, QCA_WLAN_VENDOR_ATTR_LOGGER_SUPPORTED, features)) { hdd_err("nla put fail"); @@ -6647,9 +6840,9 @@ wlan_hdd_cfg80211_get_logger_supp_feature(struct wiphy *wiphy, #ifdef WLAN_FEATURE_GTK_OFFLOAD void wlan_hdd_save_gtk_offload_params(struct hdd_adapter *adapter, - uint8_t *kck_ptr, uint8_t *kek_ptr, - uint32_t kek_len, uint8_t *replay_ctr, - bool big_endian) + uint8_t *kck_ptr, uint8_t kck_len, + uint8_t *kek_ptr, uint32_t kek_len, + uint8_t *replay_ctr, bool big_endian) { struct hdd_station_ctx *hdd_sta_ctx; uint8_t *buf; @@ -6665,8 +6858,14 @@ void wlan_hdd_save_gtk_offload_params(struct hdd_adapter *adapter, } hdd_sta_ctx = WLAN_HDD_GET_STATION_CTX_PTR(adapter); - if (kck_ptr) - qdf_mem_copy(gtk_req->kck, kck_ptr, NL80211_KCK_LEN); + if (kck_ptr) { + if (kck_len > sizeof(gtk_req->kck)) { + kck_len = sizeof(gtk_req->kck); + QDF_ASSERT(0); + } + qdf_mem_copy(gtk_req->kck, kck_ptr, kck_len); + gtk_req->kck_len = kck_len; + } if (kek_ptr) { /* paranoia */ @@ -6697,15 +6896,6 @@ void wlan_hdd_save_gtk_offload_params(struct hdd_adapter *adapter, end: qdf_mem_free(gtk_req); } -#else -void wlan_hdd_save_gtk_offload_params(struct hdd_adapter *adapter, - uint8_t *kck_ptr, - uint8_t *kek_ptr, - uint32_t kek_len, - uint8_t *replay_ctr, - bool big_endian) -{ -} #endif #if defined(WLAN_FEATURE_FILS_SK) && defined(WLAN_FEATURE_ROAM_OFFLOAD) @@ -6758,6 +6948,41 @@ wlan_hdd_add_fils_params_roam_auth_event(struct sk_buff *skb, #endif #ifdef WLAN_FEATURE_ROAM_OFFLOAD +void hdd_send_roam_scan_ch_list_event(struct hdd_context *hdd_ctx, + uint16_t buf_len, uint8_t *buf) +{ + struct sk_buff *vendor_event; + uint32_t len, ret; + + if (!hdd_ctx) { + hdd_err_rl("hdd context is null"); + return; + } + + len = nla_total_size(buf_len) + NLMSG_HDRLEN; + vendor_event = + cfg80211_vendor_event_alloc( + hdd_ctx->wiphy, NULL, len, + QCA_NL80211_VENDOR_SUBCMD_UPDATE_STA_INFO_INDEX, + GFP_KERNEL); + + if (!vendor_event) { + hdd_err("cfg80211_vendor_event_alloc failed"); + return; + } + + ret = nla_put(vendor_event, + QCA_WLAN_VENDOR_ATTR_UPDATE_STA_INFO_CONNECT_CHANNELS, + buf_len, buf); + if (ret) { + hdd_err("OEM event put fails status %d", ret); + kfree_skb(vendor_event); + return; + } + + cfg80211_vendor_event(vendor_event, GFP_KERNEL); +} + /** * wlan_hdd_send_roam_auth_event() - Send the roamed and authorized event * @adapter: Pointer to adapter struct @@ -6850,6 +7075,8 @@ int wlan_hdd_send_roam_auth_event(struct hdd_adapter *adapter, uint8_t *bssid, /* if FT or CCKM connection: dont send replay counter */ if (auth_type != eCSR_AUTH_TYPE_FT_RSN && auth_type != eCSR_AUTH_TYPE_FT_RSN_PSK && + auth_type != eCSR_AUTH_TYPE_FT_SAE && + auth_type != eCSR_AUTH_TYPE_FT_SUITEB_EAP_SHA384 && auth_type != eCSR_AUTH_TYPE_CCKM_WPA && auth_type != eCSR_AUTH_TYPE_CCKM_RSN && nla_put(skb, @@ -6863,7 +7090,7 @@ int wlan_hdd_send_roam_auth_event(struct hdd_adapter *adapter, uint8_t *bssid, if (roam_info_ptr->kek_len > SIR_KEK_KEY_LEN_FILS || nla_put(skb, QCA_WLAN_VENDOR_ATTR_ROAM_AUTH_PTK_KCK, - SIR_KCK_KEY_LEN, roam_info_ptr->kck) || + roam_info_ptr->kck_len, roam_info_ptr->kck) || nla_put(skb, QCA_WLAN_VENDOR_ATTR_ROAM_AUTH_PTK_KEK, roam_info_ptr->kek_len, roam_info_ptr->kek)) { @@ -6883,6 +7110,7 @@ int wlan_hdd_send_roam_auth_event(struct hdd_adapter *adapter, uint8_t *bssid, * into power save state. */ wlan_hdd_save_gtk_offload_params(adapter, roam_info_ptr->kck, + roam_info_ptr->kck_len, roam_info_ptr->kek, roam_info_ptr->kek_len, roam_info_ptr->replay_ctr, @@ -6999,6 +7227,9 @@ wlan_hdd_wifi_config_policy[QCA_WLAN_VENDOR_ATTR_CONFIG_MAX + 1] = { [QCA_WLAN_VENDOR_ATTR_CONFIG_SCAN_ENABLE] = {.type = NLA_U8 }, [QCA_WLAN_VENDOR_ATTR_CONFIG_RSN_IE] = {.type = NLA_U8}, [QCA_WLAN_VENDOR_ATTR_CONFIG_GTX] = {.type = NLA_U8}, + [QCA_WLAN_VENDOR_ATTR_DISCONNECT_IES] = { + .type = NLA_BINARY, + .len = SIR_MAC_MAX_ADD_IE_LENGTH + 2}, }; static const struct nla_policy @@ -7361,6 +7592,38 @@ static int hdd_config_scan_default_ies(struct hdd_adapter *adapter, return 0; } +/** + * hdd_config_disconnect_ies() - Configure disconnect IEs + * @adapter: Pointer to HDD adapter + * @attr: array of pointer to struct nlattr + * + * Return: 0 on success; error number otherwise + */ +static int hdd_config_disconnect_ies(struct hdd_adapter *adapter, + const struct nlattr *attr) +{ + struct hdd_context *hdd_ctx = WLAN_HDD_GET_CTX(adapter); + QDF_STATUS status; + + hdd_debug("IE len %u session %u device mode %u", + nla_len(attr), adapter->session_id, adapter->device_mode); + if (!nla_len(attr) || + nla_len(attr) > SIR_MAC_MAX_ADD_IE_LENGTH + 2 || + !wlan_is_ie_valid(nla_data(attr), nla_len(attr))) { + hdd_err("Invalid disconnect IEs"); + return -EINVAL; + } + + status = sme_set_disconnect_ies(hdd_ctx->mac_handle, + adapter->session_id, + nla_data(attr), + nla_len(attr)); + if (QDF_IS_STATUS_ERROR(status)) + hdd_err("Failed to set disconnect_ies"); + + return qdf_status_to_os_return(status); +} + /** * __wlan_hdd_cfg80211_wifi_configuration_set() - Wifi configuration * vendor command @@ -7572,8 +7835,8 @@ __wlan_hdd_cfg80211_wifi_configuration_set(struct wiphy *wiphy, if (tb[QCA_WLAN_VENDOR_ATTR_CONFIG_MGMT_RETRY]) { retry = nla_get_u8(tb[QCA_WLAN_VENDOR_ATTR_CONFIG_MGMT_RETRY]); - retry = retry > CFG_MGMT_RETRY_MAX ? - CFG_MGMT_RETRY_MAX : retry; + retry = retry > MGMT_RETRY_MAX ? + MGMT_RETRY_MAX : retry; param_id = WMI_PDEV_PARAM_MGMT_RETRY_LIMIT; ret_val = wma_cli_set_command(adapter->session_id, param_id, retry, PDEV_CMD); @@ -7979,6 +8242,13 @@ __wlan_hdd_cfg80211_wifi_configuration_set(struct wiphy *wiphy, hdd_err("Failed to set GTX"); } + attr = tb[QCA_WLAN_VENDOR_ATTR_DISCONNECT_IES]; + if (attr) { + ret_val = hdd_config_disconnect_ies(adapter, attr); + if (ret_val) + hdd_err("Failed to set disconnect_ies"); + } + return ret_val; } @@ -8507,12 +8777,12 @@ static int __wlan_hdd_cfg80211_wifi_logger_get_ring_data(struct wiphy *wiphy, * As part of DRIVER ring ID, flush both driver and fw logs. * For other Ring ID's driver doesn't have any rings to flush */ - hdd_info("Bug report triggered by framework"); + hdd_debug("Bug report triggered by framework"); status = cds_flush_logs(WLAN_LOG_TYPE_NON_FATAL, WLAN_LOG_INDICATOR_FRAMEWORK, WLAN_LOG_REASON_CODE_UNUSED, - true, false); + false, false); if (QDF_STATUS_SUCCESS != status) { hdd_err("Failed to trigger bug report"); return -EINVAL; @@ -12233,89 +12503,365 @@ static int wlan_hdd_cfg80211_setband(struct wiphy *wiphy, return ret; } -/** - * wlan_hdd_cfg80211_sar_convert_limit_set() - Convert limit set value - * @nl80211_value: Vendor command attribute value - * @wmi_value: Pointer to return converted WMI return value - * - * Convert NL80211 vendor command value for SAR limit set to WMI value - * Return: 0 on success, -1 on invalid value - */ -static int wlan_hdd_cfg80211_sar_convert_limit_set(u32 nl80211_value, - u32 *wmi_value) -{ - int ret = 0; - - switch (nl80211_value) { - case QCA_WLAN_VENDOR_ATTR_SAR_LIMITS_SELECT_NONE: - *wmi_value = WMI_SAR_FEATURE_OFF; - break; - case QCA_WLAN_VENDOR_ATTR_SAR_LIMITS_SELECT_BDF0: - *wmi_value = WMI_SAR_FEATURE_ON_SET_0; - break; - case QCA_WLAN_VENDOR_ATTR_SAR_LIMITS_SELECT_BDF1: - *wmi_value = WMI_SAR_FEATURE_ON_SET_1; - break; - case QCA_WLAN_VENDOR_ATTR_SAR_LIMITS_SELECT_BDF2: - *wmi_value = WMI_SAR_FEATURE_ON_SET_2; - break; - case QCA_WLAN_VENDOR_ATTR_SAR_LIMITS_SELECT_BDF3: - *wmi_value = WMI_SAR_FEATURE_ON_SET_3; - break; - case QCA_WLAN_VENDOR_ATTR_SAR_LIMITS_SELECT_BDF4: - *wmi_value = WMI_SAR_FEATURE_ON_SET_4; - break; - case QCA_WLAN_VENDOR_ATTR_SAR_LIMITS_SELECT_USER: - *wmi_value = WMI_SAR_FEATURE_ON_USER_DEFINED; - break; - case QCA_WLAN_VENDOR_ATTR_SAR_LIMITS_SELECT_V2_0: - *wmi_value = WMI_SAR_FEATURE_ON_SAR_V2_0; - break; - - default: - ret = -1; - } - return ret; -} - -#ifdef WLAN_FEATURE_SARV1_TO_SARV2 -/** - * hdd_convert_sarv1_to_sarv2() - convert SAR V1 BDF reference to SAR V2 - * @hdd_ctx: The HDD global context - * @tb: The parsed array of netlink attributes - * @sar_limit_cmd: The WMI command to be filled - * - * This feature/function is designed to solve the following problem: - * 1) Userspace application was written to use SARv1 BDF entries - * 2) Product is configured with SAR V2 BDF entries - * - * So if this feature is enabled, and if the firmware is configured - * with SAR V2 support, and if the incoming request is to enable a SAR - * V1 BDF entry, then the WMI command is generated to actually - * configure a SAR V2 BDF entry. - * - * Return: true if conversion was performed and @sar_limit_cmd is - * ready to be sent to firmware. Otherwise false in which case the - * normal parsing logic should be applied. - */ - -static bool -hdd_convert_sarv1_to_sarv2(struct hdd_context *hdd_ctx, - struct nlattr *tb[], - struct sar_limit_cmd_params *sar_limit_cmd) +#ifdef SAR_SAFETY_FEATURE +void hdd_disable_sar(struct hdd_context *hdd_ctx) { - struct nlattr *attr; - uint32_t bdf_index, set; + struct sar_limit_cmd_params *sar_limit_cmd; struct sar_limit_cmd_row *row; + QDF_STATUS status; if (hdd_ctx->sar_version != SAR_VERSION_2) { - hdd_debug("SAR version: %d", hdd_ctx->sar_version); - return false; + hdd_nofl_debug("FW SAR version: %d", hdd_ctx->sar_version); + return; } - attr = tb[QCA_WLAN_VENDOR_ATTR_SAR_LIMITS_SAR_ENABLE]; - if (!attr) - return false; + sar_limit_cmd = qdf_mem_malloc(sizeof(struct sar_limit_cmd_params)); + if (!sar_limit_cmd) + return; + + /* + * Need two rows to hold the per-chain V2 power index + */ + row = qdf_mem_malloc(2 * sizeof(*row)); + if (!row) + goto config_sar_failed; + + sar_limit_cmd->sar_enable = WMI_SAR_FEATURE_OFF; + sar_limit_cmd->commit_limits = 1; + sar_limit_cmd->num_limit_rows = 2; + sar_limit_cmd->sar_limit_row_list = row; + row[0].limit_value = 0; + row[1].limit_value = 0; + row[0].chain_id = 0; + row[1].chain_id = 1; + row[0].validity_bitmap = WMI_SAR_CHAIN_ID_VALID_MASK; + row[1].validity_bitmap = WMI_SAR_CHAIN_ID_VALID_MASK; + + hdd_nofl_debug("Disable the SAR limit index for both the chains"); + + status = sme_set_sar_power_limits(hdd_ctx->mac_handle, sar_limit_cmd); + if (QDF_IS_STATUS_ERROR(status)) { + hdd_nofl_err("Failed to set sar power limits"); + goto config_sar_failed; + } + + /* After SSR, the SAR configuration is lost. As SSR is hidden from + * userland, this command will not come from userspace after a SSR. To + * restore this configuration, save this in hdd context and restore + * after re-init. + */ + hdd_store_sar_config(hdd_ctx, sar_limit_cmd); + return; + +config_sar_failed: + + if (sar_limit_cmd) { + qdf_mem_free(sar_limit_cmd->sar_limit_row_list); + qdf_mem_free(sar_limit_cmd); + } +} + +static void hdd_configure_sar_index(struct hdd_context *hdd_ctx, + uint32_t sar_index) +{ + struct sar_limit_cmd_params *sar_limit_cmd; + struct sar_limit_cmd_row *row; + QDF_STATUS status; + + if (hdd_ctx->sar_version != SAR_VERSION_2) { + hdd_nofl_debug("FW SAR version: %d", hdd_ctx->sar_version); + return; + } + + sar_limit_cmd = qdf_mem_malloc(sizeof(struct sar_limit_cmd_params)); + if (!sar_limit_cmd) + return; + + /* + * Need two rows to hold the per-chain V2 power index + */ + row = qdf_mem_malloc(2 * sizeof(*row)); + if (!row) + goto config_sar_failed; + + sar_limit_cmd->sar_enable = WMI_SAR_FEATURE_ON_SAR_V2_0; + sar_limit_cmd->commit_limits = 1; + sar_limit_cmd->num_limit_rows = 2; + sar_limit_cmd->sar_limit_row_list = row; + row[0].limit_value = sar_index; + row[1].limit_value = sar_index; + row[0].chain_id = 0; + row[1].chain_id = 1; + row[0].validity_bitmap = WMI_SAR_CHAIN_ID_VALID_MASK; + row[1].validity_bitmap = WMI_SAR_CHAIN_ID_VALID_MASK; + + hdd_nofl_debug("Configure POW_Limit Index: %d for both the chains", + row->limit_value); + + status = sme_set_sar_power_limits(hdd_ctx->mac_handle, sar_limit_cmd); + if (QDF_IS_STATUS_ERROR(status)) { + hdd_nofl_err("Failed to set sar power limits"); + goto config_sar_failed; + } + + /* + * After SSR, the SAR configuration is lost. As SSR is hidden from + * userland, this command will not come from userspace after a SSR. To + * restore this configuration, save this in hdd context and restore + * after re-init. + */ + hdd_store_sar_config(hdd_ctx, sar_limit_cmd); + return; + +config_sar_failed: + + if (sar_limit_cmd) { + qdf_mem_free(sar_limit_cmd->sar_limit_row_list); + qdf_mem_free(sar_limit_cmd); + } +} + +void hdd_configure_sar_sleep_index(struct hdd_context *hdd_ctx) +{ + if (!hdd_ctx->config->enable_sar_safety) + return; + + if (hdd_ctx->config->config_sar_safety_sleep_index) { + hdd_nofl_debug("Configure SAR sleep index %d", + hdd_ctx->config->sar_safety_sleep_index); + hdd_configure_sar_index( + hdd_ctx, + hdd_ctx->config->sar_safety_sleep_index); + } else { + hdd_nofl_debug("Disable SAR"); + hdd_disable_sar(hdd_ctx); + } +} + +void hdd_configure_sar_resume_index(struct hdd_context *hdd_ctx) +{ + if (!hdd_ctx->config->enable_sar_safety) + return; + + hdd_nofl_debug("Configure SAR safety index %d on wlan resume", + hdd_ctx->config->sar_safety_index); + hdd_configure_sar_index(hdd_ctx, + hdd_ctx->config->sar_safety_index); +} + +static void hdd_send_sar_unsolicited_event(struct hdd_context *hdd_ctx) +{ + struct sk_buff *vendor_event; + uint32_t len; + + if (!hdd_ctx) { + hdd_err_rl("hdd context is null"); + return; + } + + len = NLMSG_HDRLEN; + vendor_event = + cfg80211_vendor_event_alloc( + hdd_ctx->wiphy, NULL, len, + QCA_NL80211_VENDOR_SUBCMD_REQUEST_SAR_LIMITS_INDEX, + GFP_KERNEL); + + if (!vendor_event) { + hdd_err("cfg80211_vendor_event_alloc failed"); + return; + } + + cfg80211_vendor_event(vendor_event, GFP_KERNEL); +} + +static void hdd_sar_unsolicited_timer_cb(void *user_data) +{ + struct hdd_context *hdd_ctx = (struct hdd_context *)user_data; + uint8_t i = 0; + QDF_STATUS status; + + hdd_nofl_debug("Sar unsolicited timer expired"); + + for (i = 0; i < hdd_ctx->config->sar_safety_req_resp_retry; i++) { + hdd_send_sar_unsolicited_event(hdd_ctx); + status = qdf_wait_for_event_completion( + &hdd_ctx->sar_safety_req_resp_event, + hdd_ctx->config->sar_safety_req_resp_timeout); + if (QDF_IS_STATUS_SUCCESS(status)) + break; + } + + if (i >= hdd_ctx->config->sar_safety_req_resp_retry) + hdd_configure_sar_index(hdd_ctx, + hdd_ctx->config->sar_safety_index); + +} + +static void hdd_sar_safety_timer_cb(void *user_data) +{ + struct hdd_context *hdd_ctx = (struct hdd_context *)user_data; + + hdd_nofl_debug("Sar safety timer expires"); + hdd_configure_sar_index(hdd_ctx, hdd_ctx->config->sar_safety_index); +} + +void wlan_hdd_sar_unsolicited_timer_start(struct hdd_context *hdd_ctx) +{ + if (!hdd_ctx->config->enable_sar_safety) + return; + + if (QDF_TIMER_STATE_RUNNING != + qdf_mc_timer_get_current_state( + &hdd_ctx->sar_safety_unsolicited_timer)) + qdf_mc_timer_start( + &hdd_ctx->sar_safety_unsolicited_timer, + hdd_ctx->config->sar_safety_unsolicited_timeout); +} + +void wlan_hdd_sar_timers_reset(struct hdd_context *hdd_ctx) +{ + if (!hdd_ctx->config->enable_sar_safety) + return; + + if (hdd_ctx->sar_version != SAR_VERSION_2) + return; + + if (QDF_TIMER_STATE_RUNNING == + qdf_mc_timer_get_current_state(&hdd_ctx->sar_safety_timer)) + qdf_mc_timer_stop(&hdd_ctx->sar_safety_timer); + + qdf_mc_timer_start(&hdd_ctx->sar_safety_timer, + hdd_ctx->config->sar_safety_timeout); + + if (QDF_TIMER_STATE_RUNNING == + qdf_mc_timer_get_current_state( + &hdd_ctx->sar_safety_unsolicited_timer)) + qdf_mc_timer_stop(&hdd_ctx->sar_safety_unsolicited_timer); + + qdf_event_set(&hdd_ctx->sar_safety_req_resp_event); +} + +void wlan_hdd_sar_timers_init(struct hdd_context *hdd_ctx) +{ + if (!hdd_ctx->config->enable_sar_safety) + return; + + qdf_mc_timer_init(&hdd_ctx->sar_safety_timer, QDF_TIMER_TYPE_SW, + hdd_sar_safety_timer_cb, hdd_ctx); + + qdf_mc_timer_init(&hdd_ctx->sar_safety_unsolicited_timer, + QDF_TIMER_TYPE_SW, + hdd_sar_unsolicited_timer_cb, hdd_ctx); + + qdf_event_create(&hdd_ctx->sar_safety_req_resp_event); + +} + +void wlan_hdd_sar_timers_deinit(struct hdd_context *hdd_ctx) +{ + if (!hdd_ctx->config->enable_sar_safety) + return; + + if (QDF_TIMER_STATE_RUNNING == + qdf_mc_timer_get_current_state(&hdd_ctx->sar_safety_timer)) + qdf_mc_timer_stop(&hdd_ctx->sar_safety_timer); + + qdf_mc_timer_destroy(&hdd_ctx->sar_safety_timer); + + if (QDF_TIMER_STATE_RUNNING == + qdf_mc_timer_get_current_state( + &hdd_ctx->sar_safety_unsolicited_timer)) + qdf_mc_timer_stop(&hdd_ctx->sar_safety_unsolicited_timer); + + qdf_mc_timer_destroy(&hdd_ctx->sar_safety_unsolicited_timer); + + qdf_event_destroy(&hdd_ctx->sar_safety_req_resp_event); +} +#endif + +/** + * wlan_hdd_cfg80211_sar_convert_limit_set() - Convert limit set value + * @nl80211_value: Vendor command attribute value + * @wmi_value: Pointer to return converted WMI return value + * + * Convert NL80211 vendor command value for SAR limit set to WMI value + * Return: 0 on success, -1 on invalid value + */ +static int wlan_hdd_cfg80211_sar_convert_limit_set(u32 nl80211_value, + u32 *wmi_value) +{ + int ret = 0; + + switch (nl80211_value) { + case QCA_WLAN_VENDOR_ATTR_SAR_LIMITS_SELECT_NONE: + *wmi_value = WMI_SAR_FEATURE_OFF; + break; + case QCA_WLAN_VENDOR_ATTR_SAR_LIMITS_SELECT_BDF0: + *wmi_value = WMI_SAR_FEATURE_ON_SET_0; + break; + case QCA_WLAN_VENDOR_ATTR_SAR_LIMITS_SELECT_BDF1: + *wmi_value = WMI_SAR_FEATURE_ON_SET_1; + break; + case QCA_WLAN_VENDOR_ATTR_SAR_LIMITS_SELECT_BDF2: + *wmi_value = WMI_SAR_FEATURE_ON_SET_2; + break; + case QCA_WLAN_VENDOR_ATTR_SAR_LIMITS_SELECT_BDF3: + *wmi_value = WMI_SAR_FEATURE_ON_SET_3; + break; + case QCA_WLAN_VENDOR_ATTR_SAR_LIMITS_SELECT_BDF4: + *wmi_value = WMI_SAR_FEATURE_ON_SET_4; + break; + case QCA_WLAN_VENDOR_ATTR_SAR_LIMITS_SELECT_USER: + *wmi_value = WMI_SAR_FEATURE_ON_USER_DEFINED; + break; + case QCA_WLAN_VENDOR_ATTR_SAR_LIMITS_SELECT_V2_0: + *wmi_value = WMI_SAR_FEATURE_ON_SAR_V2_0; + break; + + default: + ret = -1; + } + return ret; +} + +#ifdef WLAN_FEATURE_SARV1_TO_SARV2 +/** + * hdd_convert_sarv1_to_sarv2() - convert SAR V1 BDF reference to SAR V2 + * @hdd_ctx: The HDD global context + * @tb: The parsed array of netlink attributes + * @sar_limit_cmd: The WMI command to be filled + * + * This feature/function is designed to solve the following problem: + * 1) Userspace application was written to use SARv1 BDF entries + * 2) Product is configured with SAR V2 BDF entries + * + * So if this feature is enabled, and if the firmware is configured + * with SAR V2 support, and if the incoming request is to enable a SAR + * V1 BDF entry, then the WMI command is generated to actually + * configure a SAR V2 BDF entry. + * + * Return: true if conversion was performed and @sar_limit_cmd is + * ready to be sent to firmware. Otherwise false in which case the + * normal parsing logic should be applied. + */ + +static bool +hdd_convert_sarv1_to_sarv2(struct hdd_context *hdd_ctx, + struct nlattr *tb[], + struct sar_limit_cmd_params *sar_limit_cmd) +{ + struct nlattr *attr; + uint32_t bdf_index, set; + struct sar_limit_cmd_row *row; + + if (hdd_ctx->sar_version != SAR_VERSION_2) { + hdd_debug("SAR version: %d", hdd_ctx->sar_version); + return false; + } + + attr = tb[QCA_WLAN_VENDOR_ATTR_SAR_LIMITS_SAR_ENABLE]; + if (!attr) + return false; bdf_index = nla_get_u32(attr); @@ -12873,6 +13419,8 @@ static int __wlan_hdd_set_sar_power_limits(struct wiphy *wiphy, if (!sar_limit_cmd) return -ENOMEM; + wlan_hdd_sar_timers_reset(hdd_ctx); + /* is special SAR V1 => SAR V2 logic enabled and applicable? */ if (hdd_convert_sarv1_to_sarv2(hdd_ctx, tb, sar_limit_cmd)) goto send_sar_limits; @@ -14996,10 +15544,225 @@ int wlan_hdd_send_mode_change_event(void) nla_nest_end(skb, attr); - cfg80211_vendor_event(skb, GFP_KERNEL); - hdd_exit(); + cfg80211_vendor_event(skb, GFP_KERNEL); + hdd_exit(); + + return err; +} + +/** + * hdd_remove_dsrc_channels () - remove dsrc chanels + * @hdd_ctx: hdd context + * @wiphy: Pointer to wireless phy + * @chan_list: channel list + * @num_channels: number of channels + * + * Return: none + */ +static void hdd_remove_dsrc_channels(struct hdd_context *hdd_ctx, + struct wiphy *wiphy, uint32_t *chan_list, + uint8_t *num_channels) +{ + uint8_t num_chan_temp = 0; + int i; + + for (i = 0; i < *num_channels; i++) { + if (!wlan_reg_is_dsrc_chan(hdd_ctx->pdev, + wlan_reg_freq_to_chan( + hdd_ctx->pdev, + chan_list[i]))) { + chan_list[num_chan_temp] = chan_list[i]; + num_chan_temp++; + } + } + *num_channels = num_chan_temp; +} + +/** + * hdd_remove_passive_channels () - remove passive channels + * @wiphy: Pointer to wireless phy + * @chan_list: channel list + * @num_channels: number of channels + * + * Return: none + */ +static void hdd_remove_passive_channels(struct wiphy *wiphy, + uint32_t *chan_list, + uint8_t *num_channels) +{ + uint8_t num_chan_temp = 0; + int i, j, k; + + for (i = 0; i < *num_channels; i++) + for (j = 0; j < HDD_NUM_NL80211_BANDS; j++) { + if (wiphy->bands[j] == NULL) + continue; + for (k = 0; k < wiphy->bands[j]->n_channels; k++) { + if ((chan_list[i] == + wiphy->bands[j]->channels[k].center_freq) + && (!(wiphy->bands[j]->channels[k].flags & + IEEE80211_CHAN_PASSIVE_SCAN)) + ) { + chan_list[num_chan_temp] = chan_list[i]; + num_chan_temp++; + } + } + } + + *num_channels = num_chan_temp; +} + +/** + * __wlan_hdd_cfg80211_extscan_get_valid_channels () - get valid channels + * @wiphy: Pointer to wireless phy + * @wdev: Pointer to wireless device + * @data: Pointer to data + * @data_len: Data length + * + * Return: none + */ +static int +__wlan_hdd_cfg80211_extscan_get_valid_channels(struct wiphy *wiphy, + struct wireless_dev + *wdev, const void *data, + int data_len) +{ + struct hdd_context *hdd_ctx = wiphy_priv(wiphy); + struct net_device *dev = wdev->netdev; + struct hdd_adapter *adapter = WLAN_HDD_GET_PRIV_PTR(dev); + uint32_t chan_list[WNI_CFG_VALID_CHANNEL_LIST_LEN] = {0}; + uint8_t num_channels = 0, i, buf[256] = {0}; + struct nlattr *tb[QCA_WLAN_VENDOR_ATTR_EXTSCAN_SUBCMD_CONFIG_PARAM_MAX + + 1]; + uint32_t requestId, maxChannels; + tWifiBand wifiBand; + QDF_STATUS status; + struct sk_buff *reply_skb; + int ret, len = 0; + + /* ENTER_DEV() intentionally not used in a frequently invoked API */ + + if (QDF_GLOBAL_FTM_MODE == hdd_get_conparam()) { + hdd_err("Command not allowed in FTM mode"); + return -EPERM; + } + + ret = wlan_hdd_validate_context(hdd_ctx); + if (0 != ret) + return -EINVAL; + + if (wlan_cfg80211_nla_parse(tb, + QCA_WLAN_VENDOR_ATTR_EXTSCAN_SUBCMD_CONFIG_PARAM_MAX, + data, data_len, wlan_hdd_extscan_config_policy)) { + hdd_err("Invalid ATTR"); + return -EINVAL; + } + + /* Parse and fetch request Id */ + if (!tb[QCA_WLAN_VENDOR_ATTR_EXTSCAN_SUBCMD_CONFIG_PARAM_REQUEST_ID]) { + hdd_err("attr request id failed"); + return -EINVAL; + } + requestId = + nla_get_u32(tb + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_SUBCMD_CONFIG_PARAM_REQUEST_ID]); + + /* Parse and fetch wifi band */ + if (!tb + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_GET_VALID_CHANNELS_CONFIG_PARAM_WIFI_BAND]) { + hdd_err("attr wifi band failed"); + return -EINVAL; + } + wifiBand = + nla_get_u32(tb + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_GET_VALID_CHANNELS_CONFIG_PARAM_WIFI_BAND]); + + if (!tb + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_GET_VALID_CHANNELS_CONFIG_PARAM_MAX_CHANNELS]) { + hdd_err("attr max channels failed"); + return -EINVAL; + } + maxChannels = + nla_get_u32(tb + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_GET_VALID_CHANNELS_CONFIG_PARAM_MAX_CHANNELS]); + + if (maxChannels > WNI_CFG_VALID_CHANNEL_LIST_LEN) { + hdd_err("Max channels %d exceeded Valid channel list len %d", + maxChannels, WNI_CFG_VALID_CHANNEL_LIST_LEN); + return -EINVAL; + } + + hdd_debug("Req Id: %u Wifi band: %d Max channels: %d", requestId, + wifiBand, maxChannels); + status = sme_get_valid_channels_by_band(hdd_ctx->mac_handle, + wifiBand, chan_list, + &num_channels); + if (QDF_STATUS_SUCCESS != status) { + hdd_err("sme_get_valid_channels_by_band failed (err=%d)", + status); + return -EINVAL; + } + + num_channels = QDF_MIN(num_channels, maxChannels); + + hdd_remove_dsrc_channels(hdd_ctx, wiphy, chan_list, &num_channels); + if ((QDF_SAP_MODE == adapter->device_mode) || + !strncmp(hdd_get_fwpath(), "ap", 2)) + hdd_remove_passive_channels(wiphy, chan_list, + &num_channels); + + hdd_debug("Number of channels: %d", num_channels); + for (i = 0; i < num_channels; i++) + len += scnprintf(buf + len, sizeof(buf) - len, + "%u ", chan_list[i]); + + hdd_debug("Channels: %s", buf); + + reply_skb = cfg80211_vendor_cmd_alloc_reply_skb(wiphy, sizeof(u32) + + sizeof(u32) * + num_channels + + NLMSG_HDRLEN); + + if (reply_skb) { + if (nla_put_u32(reply_skb, + QCA_WLAN_VENDOR_ATTR_EXTSCAN_RESULTS_NUM_CHANNELS, + num_channels) || + nla_put(reply_skb, + QCA_WLAN_VENDOR_ATTR_EXTSCAN_RESULTS_CHANNELS, + sizeof(u32) * num_channels, chan_list)) { + hdd_err("nla put fail"); + kfree_skb(reply_skb); + return -EINVAL; + } + ret = cfg80211_vendor_cmd_reply(reply_skb); + return ret; + } + + hdd_err("valid channels: buffer alloc fail"); + return -EINVAL; +} + +/** + * wlan_hdd_cfg80211_extscan_get_valid_channels() - get ext scan valid channels + * @wiphy: Pointer to wireless phy + * @wdev: Pointer to wireless device + * @data: Pointer to data + * @data_len: Data length + * + * Return: 0 on success, negative errno on failure + */ +static int wlan_hdd_cfg80211_extscan_get_valid_channels(struct wiphy *wiphy, + struct wireless_dev *wdev, + const void *data, int data_len) +{ + int ret = 0; + + cds_ssr_protect(__func__); + ret = __wlan_hdd_cfg80211_extscan_get_valid_channels(wiphy, wdev, data, + data_len); + cds_ssr_unprotect(__func__); - return err; + return ret; } const struct wiphy_vendor_command hdd_wiphy_vendor_commands[] = { @@ -15011,6 +15774,13 @@ const struct wiphy_vendor_command hdd_wiphy_vendor_commands[] = { .doit = is_driver_dfs_capable }, + { + .info.vendor_id = QCA_NL80211_VENDOR_ID, + .info.subcmd = QCA_NL80211_VENDOR_SUBCMD_EXTSCAN_GET_VALID_CHANNELS, + .flags = WIPHY_VENDOR_CMD_NEED_WDEV | + WIPHY_VENDOR_CMD_NEED_NETDEV | WIPHY_VENDOR_CMD_NEED_RUNNING, + .doit = wlan_hdd_cfg80211_extscan_get_valid_channels + }, #ifdef WLAN_FEATURE_NAN { .info.vendor_id = QCA_NL80211_VENDOR_ID, @@ -15045,13 +15815,6 @@ const struct wiphy_vendor_command hdd_wiphy_vendor_commands[] = { WIPHY_VENDOR_CMD_NEED_NETDEV | WIPHY_VENDOR_CMD_NEED_RUNNING, .doit = wlan_hdd_cfg80211_extscan_stop }, - { - .info.vendor_id = QCA_NL80211_VENDOR_ID, - .info.subcmd = QCA_NL80211_VENDOR_SUBCMD_EXTSCAN_GET_VALID_CHANNELS, - .flags = WIPHY_VENDOR_CMD_NEED_WDEV | - WIPHY_VENDOR_CMD_NEED_NETDEV | WIPHY_VENDOR_CMD_NEED_RUNNING, - .doit = wlan_hdd_cfg80211_extscan_get_valid_channels - }, { .info.vendor_id = QCA_NL80211_VENDOR_ID, .info.subcmd = QCA_NL80211_VENDOR_SUBCMD_EXTSCAN_GET_CAPABILITIES, @@ -15342,6 +16105,8 @@ const struct wiphy_vendor_command hdd_wiphy_vendor_commands[] = { .doit = wlan_hdd_cfg80211_offloaded_packets }, #endif + FEATURE_OEM_DATA_VENDOR_COMMANDS + { .info.vendor_id = QCA_NL80211_VENDOR_ID, .info.subcmd = QCA_NL80211_VENDOR_SUBCMD_MONITOR_RSSI, @@ -16101,6 +16866,29 @@ wlan_hdd_populate_srd_chan_info(struct hdd_context *hdd_ctx, uint32_t index) #endif +#if defined(WLAN_FEATURE_NAN) && \ + (KERNEL_VERSION(4, 14, 0) <= LINUX_VERSION_CODE) +static void wlan_hdd_set_nan_if_mode(struct wiphy *wiphy) +{ + wiphy->interface_modes |= BIT(NL80211_IFTYPE_NAN); +} + +static void wlan_hdd_set_nan_supported_bands(struct wiphy *wiphy) +{ + wiphy->nan_supported_bands = + BIT(NL80211_BAND_2GHZ) | BIT(NL80211_BAND_5GHZ); +} +#else +static void wlan_hdd_set_nan_if_mode(struct wiphy *wiphy) +{ +} + +static void wlan_hdd_set_nan_supported_bands(struct wiphy *wiphy) +{ +} +#endif + + /* * FUNCTION: wlan_hdd_cfg80211_init * This function is called by hdd_wlan_startup() @@ -16183,6 +16971,7 @@ int wlan_hdd_cfg80211_init(struct device *dev, | BIT(NL80211_IFTYPE_AP) | BIT(NL80211_IFTYPE_MONITOR); + wlan_hdd_set_nan_if_mode(wiphy); if (pCfg->advertiseConcurrentOperation) { if (pCfg->enableMCC) { int i; @@ -16361,7 +17150,7 @@ int wlan_hdd_cfg80211_init(struct device *dev, if (pCfg->enable_mac_spoofing) wlan_hdd_cfg80211_scan_randomization_init(wiphy); wlan_hdd_cfg80211_action_frame_randomization_init(wiphy); - + wlan_hdd_set_nan_supported_bands(wiphy); hdd_exit(); return 0; @@ -16439,12 +17228,25 @@ static void wlan_hdd_update_band_cap(struct hdd_context *hdd_ctx) } if (!sme_is_feature_supported_by_fw(DOT11AC)) { - hdd_ctx->wiphy->bands[HDD_NL80211_BAND_2GHZ]-> + if (hdd_ctx->wiphy->bands[HDD_NL80211_BAND_2GHZ]) { + hdd_ctx->wiphy->bands[HDD_NL80211_BAND_2GHZ]-> vht_cap.vht_supported = 0; - hdd_ctx->wiphy->bands[HDD_NL80211_BAND_2GHZ]->vht_cap.cap = 0; - hdd_ctx->wiphy->bands[HDD_NL80211_BAND_5GHZ]-> + hdd_ctx->wiphy->bands[HDD_NL80211_BAND_2GHZ]-> + vht_cap.cap = 0; + } + + if (hdd_ctx->wiphy->bands[HDD_NL80211_BAND_5GHZ]) { + hdd_ctx->wiphy->bands[HDD_NL80211_BAND_5GHZ]-> vht_cap.vht_supported = 0; - hdd_ctx->wiphy->bands[HDD_NL80211_BAND_5GHZ]->vht_cap.cap = 0; + hdd_ctx->wiphy->bands[HDD_NL80211_BAND_5GHZ]-> + vht_cap.cap = 0; + } + } else { + if (hdd_ctx->wiphy->bands[HDD_NL80211_BAND_2GHZ]) { + if (hdd_ctx->config->enableVhtFor24GHzBand) + hdd_ctx->wiphy->bands[HDD_NL80211_BAND_2GHZ]-> + vht_cap.vht_supported = 1; + } } } @@ -16936,11 +17738,6 @@ static int wlan_hdd_change_client_iface_to_new_mode(struct net_device *ndev, hdd_enter(); - if (test_bit(ACS_IN_PROGRESS, &hdd_ctx->g_event_flags)) { - hdd_warn("ACS is in progress, don't change iface!"); - return -EBUSY; - } - wdev = ndev->ieee80211_ptr; hdd_stop_adapter(hdd_ctx, adapter); hdd_deinit_adapter(hdd_ctx, adapter, true); @@ -17025,6 +17822,9 @@ static int __wlan_hdd_cfg80211_change_iface(struct wiphy *wiphy, if (0 != status) return status; + if (wlan_hdd_check_mon_concurrency()) + return -EINVAL; + if (cds_is_fw_down()) { hdd_err("Ignore if FW is already down"); return -EINVAL; @@ -18624,7 +19424,7 @@ bool wlan_hdd_handle_sap_sta_dfs_conc(struct hdd_adapter *adapter, /* sap is on non-dfs channel, nothing to handle */ if (!wlan_reg_is_dfs_ch(hdd_ctx->pdev, hdd_ap_ctx->operating_channel)) { - hdd_info("sap is on non-dfs channel, sta is allowed"); + hdd_debug("sap is on non-dfs channel, sta is allowed"); return true; } /* @@ -18749,8 +19549,6 @@ static int wlan_hdd_cfg80211_connect_start(struct hdd_adapter *adapter, uint8_t channel = 0; mac_handle_t mac_handle; - hdd_enter(); - hdd_ctx = WLAN_HDD_GET_CTX(adapter); hdd_sta_ctx = WLAN_HDD_GET_STATION_CTX_PTR(adapter); @@ -18784,6 +19582,7 @@ static int wlan_hdd_cfg80211_connect_start(struct hdd_adapter *adapter, */ hdd_sta_ctx->conn_info.gtk_installed = false; hdd_sta_ctx->conn_info.ptk_installed = false; + adapter->last_disconnect_reason = 0; roam_profile = hdd_roam_profile(adapter); if (roam_profile) { @@ -18847,7 +19646,6 @@ static int wlan_hdd_cfg80211_connect_start(struct hdd_adapter *adapter, */ qdf_mem_copy(sta_ctx->requested_bssid.bytes, bssid, QDF_MAC_ADDR_SIZE); - hdd_debug("bssid is given by upper layer %pM", bssid); } else if (bssid_hint) { qdf_mem_copy(roam_profile->bssid_hint.bytes, bssid_hint, QDF_MAC_ADDR_SIZE); @@ -18859,36 +19657,23 @@ static int wlan_hdd_cfg80211_connect_start(struct hdd_adapter *adapter, */ qdf_mem_copy(sta_ctx->requested_bssid.bytes, bssid_hint, QDF_MAC_ADDR_SIZE); - hdd_debug("bssid_hint is given by upper layer %pM", - bssid_hint); } - hdd_debug("vdevid %d: Connect to SSID: %.*s operating Channel: %u", - adapter->session_id, - roam_profile->SSIDs.SSIDList->SSID.length, - roam_profile->SSIDs.SSIDList->SSID.ssId, - operatingChannel); - if (hdd_sta_ctx->wpa_versions) { hdd_set_genie_to_csr(adapter, &RSNAuthType); hdd_set_csr_auth_type(adapter, RSNAuthType); } #ifdef FEATURE_WLAN_WAPI if (adapter->wapi_info.wapi_mode) { - hdd_debug("Setting WAPI AUTH Type and Encryption Mode values"); switch (adapter->wapi_info.wapi_auth_mode) { case WAPI_AUTH_MODE_PSK: { - hdd_debug("WAPI AUTH TYPE: PSK: %d", - adapter->wapi_info.wapi_auth_mode); roam_profile->AuthType.authType[0] = eCSR_AUTH_TYPE_WAPI_WAI_PSK; break; } case WAPI_AUTH_MODE_CERT: { - hdd_debug("WAPI AUTH TYPE: CERT: %d", - adapter->wapi_info.wapi_auth_mode); roam_profile->AuthType.authType[0] = eCSR_AUTH_TYPE_WAPI_WAI_CERTIFICATE; break; @@ -18900,7 +19685,6 @@ static int wlan_hdd_cfg80211_connect_start(struct hdd_adapter *adapter, WAPI_AUTH_MODE_PSK || adapter->wapi_info.wapi_auth_mode == WAPI_AUTH_MODE_CERT) { - hdd_debug("WAPI PAIRWISE/GROUP ENCRYPTION: WPI"); roam_profile->AuthType.numEntries = 1; roam_profile->EncryptionType.numEntries = 1; roam_profile->EncryptionType.encryptionType[0] = @@ -19045,9 +19829,8 @@ static int wlan_hdd_cfg80211_connect_start(struct hdd_adapter *adapter, if ((QDF_STATUS_SUCCESS != qdf_status) && (QDF_STA_MODE == adapter->device_mode || QDF_P2P_CLIENT_MODE == adapter->device_mode)) { - hdd_err("sme_roam_connect (session %d) failed with " - "qdf_status %d. -> NotConnected", - adapter->session_id, qdf_status); + hdd_err("Vdev %d connect failed with status %d", + adapter->session_id, qdf_status); /* change back to NotAssociated */ hdd_conn_set_connection_state(adapter, eConnectionState_NotConnected); @@ -19093,7 +19876,6 @@ static int wlan_hdd_cfg80211_connect_start(struct hdd_adapter *adapter, if (status) wlan_hdd_enable_roaming(adapter); - hdd_exit(); return status; } @@ -19116,23 +19898,19 @@ static int wlan_hdd_cfg80211_set_auth_type(struct hdd_adapter *adapter, /*set authentication type */ switch (auth_type) { case NL80211_AUTHTYPE_AUTOMATIC: - hdd_debug("set authentication type to AUTOSWITCH"); sta_ctx->conn_info.authType = eCSR_AUTH_TYPE_AUTOSWITCH; break; case NL80211_AUTHTYPE_OPEN_SYSTEM: case NL80211_AUTHTYPE_FT: - hdd_debug("set authentication type to OPEN"); sta_ctx->conn_info.authType = eCSR_AUTH_TYPE_OPEN_SYSTEM; break; case NL80211_AUTHTYPE_SHARED_KEY: - hdd_debug("set authentication type to SHARED"); sta_ctx->conn_info.authType = eCSR_AUTH_TYPE_SHARED_KEY; break; #ifdef FEATURE_WLAN_ESE case NL80211_AUTHTYPE_NETWORK_EAP: - hdd_debug("set authentication type to CCKM WPA"); sta_ctx->conn_info.authType = eCSR_AUTH_TYPE_CCKM_WPA; break; #endif @@ -19140,12 +19918,10 @@ static int wlan_hdd_cfg80211_set_auth_type(struct hdd_adapter *adapter, (defined(CFG80211_FILS_SK_OFFLOAD_SUPPORT) || \ (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0))) case NL80211_AUTHTYPE_FILS_SK: - hdd_debug("set authentication type to FILS SHARED"); sta_ctx->conn_info.authType = eCSR_AUTH_TYPE_OPEN_SYSTEM; break; #endif case NL80211_AUTHTYPE_SAE: - hdd_debug("set authentication type to SAE"); sta_ctx->conn_info.authType = eCSR_AUTH_TYPE_SAE; break; default: @@ -19344,7 +20120,6 @@ static bool wlan_hdd_is_conn_type_fils(struct cfg80211_connect_params *req) enum eAniAuthType fils_auth_type = wlan_hdd_get_fils_auth_type(req->auth_type); - hdd_debug("Num of AKM suites = %d", num_akm_suites); if (num_akm_suites <= 0) return false; @@ -19352,16 +20127,13 @@ static bool wlan_hdd_is_conn_type_fils(struct cfg80211_connect_params *req) * Auth type will be either be OPEN or FILS type for a FILS connection */ if ((auth_type != NL80211_AUTHTYPE_OPEN_SYSTEM) && - (fils_auth_type == eSIR_DONOT_USE_AUTH_TYPE)) { - hdd_debug("Not a FILS auth type, auth = %d, fils auth = %d", - auth_type, fils_auth_type); + (fils_auth_type == eSIR_DONOT_USE_AUTH_TYPE)) return false; - } - if (!wlan_hdd_is_akm_suite_fils(key_mgmt)) { - hdd_debug("Not a FILS AKM SUITE %d", key_mgmt); + if (!wlan_hdd_is_akm_suite_fils(key_mgmt)) return false; - } + + hdd_debug("Fils Auth %d AKM %d", fils_auth_type, key_mgmt); return true; } @@ -19423,20 +20195,17 @@ static int wlan_hdd_set_akm_suite(struct hdd_adapter *adapter, u32 key_mgmt) case WLAN_AKM_SUITE_PSK_SHA256: case WLAN_AKM_SUITE_FT_PSK: case WLAN_AKM_SUITE_DPP_RSN: - hdd_debug("setting key mgmt type to PSK"); sta_ctx->auth_key_mgmt |= HDD_AUTH_KEY_MGMT_PSK; break; case WLAN_AKM_SUITE_8021X_SHA256: case WLAN_AKM_SUITE_8021X: case WLAN_AKM_SUITE_FT_8021X: - hdd_debug("setting key mgmt type to 8021x"); sta_ctx->auth_key_mgmt |= HDD_AUTH_KEY_MGMT_802_1X; break; #ifdef FEATURE_WLAN_ESE #define WLAN_AKM_SUITE_CCKM 0x00409600 /* Should be in ieee802_11_defs.h */ case WLAN_AKM_SUITE_CCKM: - hdd_debug("setting key mgmt type to CCKM"); sta_ctx->auth_key_mgmt |= HDD_AUTH_KEY_MGMT_CCKM; break; #endif @@ -19444,35 +20213,30 @@ static int wlan_hdd_set_akm_suite(struct hdd_adapter *adapter, u32 key_mgmt) #define WLAN_AKM_SUITE_OSEN 0x506f9a01 /* Should be in ieee802_11_defs.h */ #endif case WLAN_AKM_SUITE_OSEN: - hdd_debug("setting key mgmt type to OSEN"); sta_ctx->auth_key_mgmt |= HDD_AUTH_KEY_MGMT_802_1X; break; #if defined(WLAN_FEATURE_FILS_SK) && \ (defined(CFG80211_FILS_SK_OFFLOAD_SUPPORT) || \ (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0))) case WLAN_AKM_SUITE_FILS_SHA256: - hdd_debug("setting key mgmt type to FILS SHA256"); sta_ctx->auth_key_mgmt |= HDD_AUTH_KEY_MGMT_802_1X; roam_profile->fils_con_info->akm_type = eCSR_AUTH_TYPE_FILS_SHA256; break; case WLAN_AKM_SUITE_FILS_SHA384: - hdd_debug("setting key mgmt type to FILS SHA384"); sta_ctx->auth_key_mgmt |= HDD_AUTH_KEY_MGMT_802_1X; roam_profile->fils_con_info->akm_type = eCSR_AUTH_TYPE_FILS_SHA384; break; case WLAN_AKM_SUITE_FT_FILS_SHA256: - hdd_debug("setting key mgmt type to FILS FT SHA256"); sta_ctx->auth_key_mgmt |= HDD_AUTH_KEY_MGMT_802_1X; roam_profile->fils_con_info->akm_type = eCSR_AUTH_TYPE_FT_FILS_SHA256; break; case WLAN_AKM_SUITE_FT_FILS_SHA384: - hdd_debug("setting key mgmt type to FILS FT SHA384"); sta_ctx->auth_key_mgmt |= HDD_AUTH_KEY_MGMT_802_1X; roam_profile->fils_con_info->akm_type = eCSR_AUTH_TYPE_FT_FILS_SHA384; @@ -19480,28 +20244,31 @@ static int wlan_hdd_set_akm_suite(struct hdd_adapter *adapter, u32 key_mgmt) #endif case WLAN_AKM_SUITE_OWE: - hdd_debug("setting key mgmt type to OWE"); sta_ctx->auth_key_mgmt |= HDD_AUTH_KEY_MGMT_802_1X; break; case WLAN_AKM_SUITE_EAP_SHA256: - hdd_debug("setting key mgmt type to EAP_SHA256"); sta_ctx->auth_key_mgmt |= HDD_AUTH_KEY_MGMT_802_1X; break; case WLAN_AKM_SUITE_EAP_SHA384: - hdd_debug("setting key mgmt type to EAP_SHA384"); sta_ctx->auth_key_mgmt |= HDD_AUTH_KEY_MGMT_802_1X; break; case WLAN_AKM_SUITE_SAE: - hdd_debug("setting key mgmt type to SAE"); + sta_ctx->auth_key_mgmt |= HDD_AUTH_KEY_MGMT_802_1X; + break; + + case WLAN_AKM_SUITE_FT_SAE: + sta_ctx->auth_key_mgmt |= HDD_AUTH_KEY_MGMT_802_1X; + break; + + case WLAN_AKM_SUITE_FT_EAP_SHA_384: sta_ctx->auth_key_mgmt |= HDD_AUTH_KEY_MGMT_802_1X; break; default: hdd_err("Unsupported key mgmt type: %d", key_mgmt); return -EINVAL; - } return 0; } @@ -19526,7 +20293,6 @@ static int wlan_hdd_cfg80211_set_cipher(struct hdd_adapter *adapter, struct csr_roam_profile *roam_profile; if (!cipher) { - hdd_debug("received cipher %d - considering none", cipher); encryptionType = eCSR_ENCRYPT_TYPE_NONE; } else { @@ -19581,13 +20347,11 @@ static int wlan_hdd_cfg80211_set_cipher(struct hdd_adapter *adapter, roam_profile = hdd_roam_profile(adapter); if (ucast) { - hdd_debug("setting unicast cipher type to %d", encryptionType); sta_ctx->conn_info.ucEncryptionType = encryptionType; roam_profile->EncryptionType.numEntries = 1; roam_profile->EncryptionType.encryptionType[0] = encryptionType; } else { - hdd_debug("setting mcast cipher type to %d", encryptionType); sta_ctx->conn_info.mcEncryptionType = encryptionType; roam_profile->mcEncryptionType.numEntries = 1; roam_profile->mcEncryptionType.encryptionType[0] = @@ -19729,18 +20493,16 @@ static int wlan_hdd_cfg80211_set_ie(struct hdd_adapter *adapter, return -EINVAL; } - hdd_debug("IE[0x%X], LEN[%d]", elementId, eLen); - switch (elementId) { case DOT11F_EID_WPA: if (4 > eLen) { /* should have at least OUI which is 4 bytes so extra 2 bytes not needed */ - hdd_err("Invalid WPA IE"); + hdd_err("Invalid vendor ie"); return -EINVAL; } else if (0 == memcmp(&genie[0], "\x00\x50\xf2\x04", 4)) { uint16_t curAddIELen = assoc_add_ie->length; - hdd_debug("Set WPS IE(len %d)", eLen + 2); + hdd_debug("WPS IE(len %d)", eLen + 2); if (SIR_MAC_MAX_ADD_IE_LENGTH < (assoc_add_ie->length + eLen)) { @@ -19765,7 +20527,7 @@ static int wlan_hdd_cfg80211_set_ie(struct hdd_adapter *adapter, QDF_ASSERT(0); return -EINVAL; } - hdd_debug("Set WPA IE (len %d)", eLen + 2); + hdd_debug("WPA IE (len %d)", eLen + 2); memset(security_ie, 0, MAX_WPA_RSN_IE_LEN); memcpy(security_ie, genie - 2, (eLen + 2)); roam_profile->pWPAReqIE = security_ie; @@ -19774,7 +20536,7 @@ static int wlan_hdd_cfg80211_set_ie(struct hdd_adapter *adapter, P2P_OUI_TYPE_SIZE))) { uint16_t curAddIELen = assoc_add_ie->length; - hdd_debug("Set P2P IE(len %d)", eLen + 2); + hdd_debug("P2P IE(len %d)", eLen + 2); if (SIR_MAC_MAX_ADD_IE_LENGTH < (assoc_add_ie->length + eLen)) { @@ -19800,7 +20562,7 @@ static int wlan_hdd_cfg80211_set_ie(struct hdd_adapter *adapter, adapter->device_mode)) { uint16_t curAddIELen = assoc_add_ie->length; - hdd_debug("Set WFD IE(len %d)", eLen + 2); + hdd_debug("WFD IE(len %d)", eLen + 2); if (SIR_MAC_MAX_ADD_IE_LENGTH < (assoc_add_ie->length + eLen)) { @@ -19827,7 +20589,7 @@ static int wlan_hdd_cfg80211_set_ie(struct hdd_adapter *adapter, HS20_OUI_TYPE_SIZE))) { uint16_t curAddIELen = assoc_add_ie->length; - hdd_debug("Set HS20 IE(len %d)", eLen + 2); + hdd_debug("HS20 IE(len %d)", eLen + 2); if (SIR_MAC_MAX_ADD_IE_LENGTH < (assoc_add_ie->length + eLen)) { @@ -19849,7 +20611,7 @@ static int wlan_hdd_cfg80211_set_ie(struct hdd_adapter *adapter, OSEN_OUI_TYPE_SIZE))) { uint16_t curAddIELen = assoc_add_ie->length; - hdd_debug("Set OSEN IE(len %d)", eLen + 2); + hdd_debug("OSEN IE(len %d)", eLen + 2); if (SIR_MAC_MAX_ADD_IE_LENGTH < (assoc_add_ie->length + eLen)) { @@ -19868,7 +20630,7 @@ static int wlan_hdd_cfg80211_set_ie(struct hdd_adapter *adapter, assoc_add_ie->length; } else if ((0 == memcmp(&genie[0], MBO_OUI_TYPE, MBO_OUI_TYPE_SIZE))){ - hdd_debug("Set MBO IE(len %d)", eLen + 2); + hdd_debug("MBO IE(len %d)", eLen + 2); status = wlan_hdd_add_assoc_ie(adapter, genie - 2, eLen + 2); if (status) @@ -19906,7 +20668,7 @@ static int wlan_hdd_cfg80211_set_ie(struct hdd_adapter *adapter, memcpy(security_ie, genie - 2, (eLen + 2)); roam_profile->pRSNReqIE = security_ie; roam_profile->nRSNReqIELength = eLen + 2; /* ie_len; */ - hdd_debug("Set RSN IE(len %d)", eLen + 2); + hdd_debug("RSN IE(len %d)", eLen + 2); break; /* * Appending Extended Capabilities with Interworking bit set @@ -19923,7 +20685,7 @@ static int wlan_hdd_cfg80211_set_ie(struct hdd_adapter *adapter, { uint16_t curAddIELen = assoc_add_ie->length; - hdd_debug("Set Extended CAPS IE(len %d)", eLen + 2); + hdd_debug("Extended CAPS IE(len %d)", eLen + 2); if (SIR_MAC_MAX_ADD_IE_LENGTH < (assoc_add_ie->length + eLen)) { @@ -19988,7 +20750,8 @@ static int wlan_hdd_cfg80211_set_ie(struct hdd_adapter *adapter, #endif case DOT11F_EID_SUPPOPERATINGCLASSES: { - hdd_debug("Set Supported Operating Classes IE(len %d)", eLen + 2); + hdd_debug("Supported Operating Classes IE(len %d)", + eLen + 2); status = wlan_hdd_add_assoc_ie(adapter, genie - 2, eLen + 2); if (status) @@ -19998,7 +20761,7 @@ static int wlan_hdd_cfg80211_set_ie(struct hdd_adapter *adapter, case SIR_MAC_REQUEST_EID_MAX: { if (genie[0] == SIR_FILS_HLP_EXT_EID) { - hdd_debug("Set HLP EXT IE(len %d)", + hdd_debug("HLP EXT IE(len %d)", eLen + 2); wlan_hdd_save_hlp_ie(roam_profile, genie - 2, eLen + 2, @@ -20010,7 +20773,7 @@ static int wlan_hdd_cfg80211_set_ie(struct hdd_adapter *adapter, return status; } else if (genie[0] == SIR_DH_PARAMETER_ELEMENT_EXT_EID) { - hdd_debug("Set DH EXT IE(len %d)", + hdd_debug("DH EXT IE(len %d)", eLen + 2); status = wlan_hdd_add_assoc_ie( adapter, genie - 2, @@ -20024,7 +20787,7 @@ static int wlan_hdd_cfg80211_set_ie(struct hdd_adapter *adapter, } case DOT11F_EID_FRAGMENT_IE: { - hdd_debug("Set Fragment IE(len %d)", eLen + 2); + hdd_debug("Fragment IE(len %d)", eLen + 2); wlan_hdd_save_hlp_ie(roam_profile, genie - 2, eLen + 2, false); @@ -20035,7 +20798,7 @@ static int wlan_hdd_cfg80211_set_ie(struct hdd_adapter *adapter, break; } default: - hdd_err("Set UNKNOWN IE: %X", elementId); + hdd_err("UNKNOWN IE: %X", elementId); /* when Unknown IE is received we break * and continue to the next IE in the buffer */ @@ -20098,11 +20861,8 @@ static int wlan_hdd_cfg80211_set_privacy(struct hdd_adapter *adapter, struct hdd_station_ctx *sta_ctx; struct csr_roam_profile *roam_profile; - hdd_enter(); - sta_ctx = WLAN_HDD_GET_STATION_CTX_PTR(adapter); sta_ctx->wpa_versions = req->crypto.wpa_versions; - hdd_debug("set wpa version to %d", sta_ctx->wpa_versions); roam_profile = hdd_roam_profile(adapter); @@ -20258,108 +21018,118 @@ static void wlan_hdd_cfg80211_clear_privacy(struct hdd_adapter *adapter) wlan_hdd_clear_wapi_privacy(adapter); } -int wlan_hdd_try_disconnect(struct hdd_adapter *adapter) +static int wlan_hdd_wait_for_disconnect(mac_handle_t mac_handle, + struct hdd_adapter *adapter, + uint16_t reason, + tSirMacReasonCodes mac_reason) { + eConnectionState prev_conn_state; + struct hdd_station_ctx *sta_ctx = WLAN_HDD_GET_STATION_CTX_PTR(adapter); + QDF_STATUS status = QDF_STATUS_SUCCESS; + int ret = 0; unsigned long rc; - struct hdd_station_ctx *sta_ctx; - int status, result = 0; - mac_handle_t mac_handle; uint32_t wait_time = WLAN_WAIT_TIME_DISCONNECT; - struct hdd_context *hdd_ctx; - hdd_ctx = WLAN_HDD_GET_CTX(adapter); - sta_ctx = WLAN_HDD_GET_STATION_CTX_PTR(adapter); - mac_handle = hdd_adapter_get_mac_handle(adapter); - if (adapter->device_mode == QDF_STA_MODE) { - hdd_debug("Stop firmware roaming"); - sme_stop_roaming(mac_handle, adapter->session_id, - eCsrForcedDisassoc); + /* Return if already disconnected */ + if (sta_ctx->conn_info.connState == eConnectionState_NotConnected || + sta_ctx->conn_info.connState == eConnectionState_IbssDisconnected) + return 0; + /* If already in disconnecting state just wait for its completion */ + if (sta_ctx->conn_info.connState == eConnectionState_Disconnecting) + goto wait_for_disconnect; + + INIT_COMPLETION(adapter->disconnect_comp_var); + prev_conn_state = sta_ctx->conn_info.connState; + hdd_conn_set_connection_state(adapter, eConnectionState_Disconnecting); + + status = sme_roam_disconnect(mac_handle, adapter->session_id, reason, + mac_reason); + if (status == QDF_STATUS_CMD_NOT_QUEUED && + prev_conn_state == eConnectionState_Connecting) { /* - * If firmware has already started roaming process, driver - * needs to wait for processing of this disconnect request. - * + * Wait here instead of returning directly, this will block the + * next connect command and allow processing of the scan for + * ssid and the previous connect command in CSR. */ - INIT_COMPLETION(adapter->roaming_comp_var); - if (hdd_is_roaming_in_progress(hdd_ctx)) { - rc = wait_for_completion_timeout( - &adapter->roaming_comp_var, - msecs_to_jiffies(WLAN_WAIT_TIME_STOP_ROAM)); - if (!rc) { - hdd_err("roaming comp var timed out session Id: %d", - adapter->session_id); - } - if (adapter->roam_ho_fail) { - INIT_COMPLETION(adapter->disconnect_comp_var); - hdd_conn_set_connection_state(adapter, - eConnectionState_Disconnecting); - } - } + hdd_debug("CSR not connected but scan for SSID is in progress, wait for scan to be aborted or completed."); + } else if (QDF_IS_STATUS_ERROR(status)) { + hdd_debug("SB Disconnect in progress/SME is disconencted/Connect removed from pending queue: status = %d", + status); + /* + * Wait here instead of returning directly. This will block the + * next connect command and allow processing of the disconnect + * in SME. As disconnect is already in progress, wait here for + * WLAN_WAIT_DISCONNECT_ALREADY_IN_PROGRESS instead of + * SME_DISCONNECT_TIMEOUT. + */ + wait_time = WLAN_WAIT_DISCONNECT_ALREADY_IN_PROGRESS; } - if ((QDF_IBSS_MODE == adapter->device_mode) || - (eConnectionState_Associated == sta_ctx->conn_info.connState) || - (eConnectionState_Connecting == sta_ctx->conn_info.connState) || - (eConnectionState_IbssConnected == sta_ctx->conn_info.connState)) { - eConnectionState prev_conn_state; +wait_for_disconnect: + rc = wait_for_completion_timeout(&adapter->disconnect_comp_var, + msecs_to_jiffies(wait_time)); - prev_conn_state = sta_ctx->conn_info.connState; - hdd_conn_set_connection_state(adapter, - eConnectionState_Disconnecting); - /* Issue disconnect to CSR */ - INIT_COMPLETION(adapter->disconnect_comp_var); + if (!rc && QDF_IS_STATUS_SUCCESS(status)) { + hdd_err("Disconnect timed out!!!"); + ret = -ETIMEDOUT; + } - status = sme_roam_disconnect(mac_handle, - adapter->session_id, - eCSR_DISCONNECT_REASON_UNSPECIFIED); + hdd_conn_set_connection_state(adapter, eConnectionState_NotConnected); - if ((status == QDF_STATUS_CMD_NOT_QUEUED) && - prev_conn_state != eConnectionState_Connecting) { - hdd_debug("Already disconnect in progress"); - result = 0; - /* - * Wait here instead of returning directly. This will - * block the connect command and allow processing - * of the disconnect in SME. As disconnect is already - * in progress, wait here for 1 sec instead of 5 sec. - */ - wait_time = WLAN_WAIT_DISCONNECT_ALREADY_IN_PROGRESS; - } else if (status == QDF_STATUS_CMD_NOT_QUEUED) { - /* - * Wait here instead of returning directly, this will - * block the connect command and allow processing - * of the scan for ssid and the previous connect command - * in CSR. - */ - hdd_debug("Already disconnected or connect was in sme/roam pending list and removed by disconnect"); - } else if (0 != status) { - hdd_err("sme_roam_disconnect failure, status: %d", - (int)status); - sta_ctx->sta_debug_state = status; - result = -EINVAL; - goto disconnected; - } - - rc = wait_for_completion_timeout(&adapter->disconnect_comp_var, - msecs_to_jiffies(wait_time)); - if (!rc && (QDF_STATUS_CMD_NOT_QUEUED != status)) { - hdd_err("Sme disconnect event timed out session Id: %d sta_debug_state: %d", - adapter->session_id, sta_ctx->sta_debug_state); - result = -ETIMEDOUT; - } - } else if (eConnectionState_Disconnecting == - sta_ctx->conn_info.connState) { - rc = wait_for_completion_timeout(&adapter->disconnect_comp_var, - msecs_to_jiffies(wait_time)); + return ret; +} + +static void wlan_hdd_wait_for_roaming(mac_handle_t mac_handle, + struct hdd_adapter *adapter) +{ + struct hdd_context *hdd_ctx; + struct hdd_station_ctx *sta_ctx = WLAN_HDD_GET_STATION_CTX_PTR(adapter); + unsigned long rc; + + if (adapter->device_mode != QDF_STA_MODE) + return; + + hdd_ctx = WLAN_HDD_GET_CTX(adapter); + + /* Return if not in connected state */ + if (sta_ctx->conn_info.connState != eConnectionState_Associated) + return; + sme_stop_roaming(mac_handle, adapter->session_id, eCsrForcedDisassoc); + /* + * If firmware has already started roaming process, driver + * needs to wait for processing of this disconnect request. + * + */ + INIT_COMPLETION(adapter->roaming_comp_var); + if (hdd_is_roaming_in_progress(hdd_ctx)) { + rc = wait_for_completion_timeout(&adapter->roaming_comp_var, + msecs_to_jiffies(WLAN_WAIT_TIME_STOP_ROAM)); if (!rc) { - hdd_err("Disconnect event timed out session Id: %d sta_debug_state: %d", - adapter->session_id, sta_ctx->sta_debug_state); - result = -ETIMEDOUT; + hdd_err("roaming_comp_var time out vdev Id: %d", + adapter->session_id); + /* Clear roaming in progress flag */ + hdd_set_roaming_in_progress(false); + } + if (adapter->roam_ho_fail) { + INIT_COMPLETION(adapter->disconnect_comp_var); + hdd_conn_set_connection_state(adapter, + eConnectionState_Disconnecting); } } -disconnected: - hdd_conn_set_connection_state(adapter, eConnectionState_NotConnected); - return result; +} + +int wlan_hdd_try_disconnect(struct hdd_adapter *adapter, + enum eSirMacReasonCodes reason) +{ + mac_handle_t mac_handle; + + mac_handle = hdd_adapter_get_mac_handle(adapter); + wlan_hdd_wait_for_roaming(mac_handle, adapter); + + return wlan_hdd_wait_for_disconnect(mac_handle, adapter, + eCSR_DISCONNECT_REASON_UNSPECIFIED, + reason); } /** @@ -20405,9 +21175,14 @@ static int wlan_hdd_reassoc_bssid_hint(struct hdd_adapter *adapter, qdf_mem_copy(sta_ctx->requested_bssid.bytes, bssid, QDF_MAC_ADDR_SIZE); + hdd_set_roaming_in_progress(true); + status = hdd_reassoc(adapter, bssid, channel, CONNECT_CMD_USERSPACE); - hdd_debug("hdd_reassoc: status: %d", status); + if (QDF_IS_STATUS_ERROR(status)) { + hdd_set_roaming_in_progress(false); + hdd_debug("Failed with status: %d", status); + } } return status; } @@ -20450,9 +21225,8 @@ wlan_hdd_check_ht20_ht40_ind(struct hdd_context *hdd_ctx, !(req->ht_capa.cap_info & IEEE80211_HT_CAP_SUP_WIDTH_20_40)) roam_profile->force_24ghz_in_ht20 = true; - hdd_debug("req->ht_capa.cap_info %x override_ht20_40_24g %d", - req->ht_capa.cap_info, - hdd_ctx->config->override_ht20_40_24g); + if (hdd_ctx->config->override_ht20_40_24g) + hdd_nofl_debug("HT cap %x", req->ht_capa.cap_info); } #else static inline void @@ -20468,6 +21242,35 @@ wlan_hdd_check_ht20_ht40_ind(struct hdd_context *hdd_ctx, } #endif +static inline void hdd_dump_connect_req(struct hdd_adapter *adapter, + struct net_device *ndev, + struct cfg80211_connect_params *req) +{ + uint32_t i; + + hdd_nofl_debug("cfg80211_connect req for %s(vdevid-%d): mode %d freq %d SSID %.*s auth type %d WPA ver %d n_akm %d n_cipher %d grp_cipher %x mfp %d freq hint %d", + ndev->name, adapter->session_id, adapter->device_mode, + req->channel ? req->channel->center_freq : 0, + (int)req->ssid_len, req->ssid, req->auth_type, + req->crypto.wpa_versions, + req->crypto.n_akm_suites, req->crypto.n_ciphers_pairwise, + req->crypto.cipher_group, req->mfp, + req->channel_hint ? req->channel_hint->center_freq : 0); + if (req->bssid) + hdd_nofl_debug("BSSID %pM", req->bssid); + if (req->bssid_hint) + hdd_nofl_debug("BSSID hint %pM", req->bssid_hint); + if (req->prev_bssid) + hdd_nofl_debug("prev BSSID %pM", req->prev_bssid); + + for (i = 0; i < req->crypto.n_akm_suites; i++) + hdd_nofl_debug("akm[%d] = %x", i, req->crypto.akm_suites[i]); + + for (i = 0; i < req->crypto.n_ciphers_pairwise; i++) + hdd_nofl_debug("cipher_pairwise[%d] = %x", i, + req->crypto.ciphers_pairwise[i]); +} + /** * __wlan_hdd_cfg80211_connect() - cfg80211 connect api * @wiphy: Pointer to wiphy @@ -20507,11 +21310,6 @@ static int __wlan_hdd_cfg80211_connect(struct wiphy *wiphy, TRACE_CODE_HDD_CFG80211_CONNECT, adapter->session_id, adapter->device_mode); - hdd_info("%s(vdevid-%d): Device_mode %s(%d)", - ndev->name, adapter->session_id, - hdd_device_mode_to_string(adapter->device_mode), - adapter->device_mode); - if (adapter->device_mode != QDF_STA_MODE && adapter->device_mode != QDF_P2P_CLIENT_MODE) { hdd_err("Device_mode %s(%d) is not supported", @@ -20541,6 +21339,8 @@ static int __wlan_hdd_cfg80211_connect(struct wiphy *wiphy, return -EINVAL; } + hdd_dump_connect_req(adapter, ndev, req); + /* * In STA + STA roaming scenario, connection to same ssid but different * bssid is allowed on both vdevs. So there could be a race where the @@ -20564,13 +21364,12 @@ static int __wlan_hdd_cfg80211_connect(struct wiphy *wiphy, * Check if this is reassoc to same bssid, if reassoc is success, return */ status = wlan_hdd_reassoc_bssid_hint(adapter, req); - if (!status) { - hdd_set_roaming_in_progress(true); + if (!status) return status; - } /* Try disconnecting if already in connected state */ - status = wlan_hdd_try_disconnect(adapter); + status = wlan_hdd_try_disconnect(adapter, + eSIR_MAC_UNSPEC_FAILURE_REASON); if (0 > status) { hdd_err("Failed to disconnect the existing connection"); return -EALREADY; @@ -20584,66 +21383,6 @@ static int __wlan_hdd_cfg80211_connect(struct wiphy *wiphy, return status; } - /* - * Check for max concurrent connections after doing disconnect if any, - * must be called after the invocation of wlan_hdd_cfg80211_set_privacy - * so privacy is already set for the current adapter before it's - * checked against concurrency. - */ - if (req->channel) { - bool ok = false; - - if (req->channel->hw_value && policy_mgr_is_chan_ok_for_dnbs( - hdd_ctx->psoc, - req->channel->hw_value, - &ok)) { - hdd_warn("Unable to get channel:%d eligibility for DNBS", - req->channel->hw_value); - return -EINVAL; - } - /** - * Send connection timedout, so that Android framework does not - * blacklist us. - */ - if (!ok) { - struct ieee80211_channel *chan = - ieee80211_get_channel(wiphy, - wlan_chan_to_freq(req->channel->hw_value)); - struct cfg80211_bss *bss; - - hdd_warn("Channel:%d not OK for DNBS", - req->channel->hw_value); - if (chan) { - bss = hdd_cfg80211_get_bss(wiphy, - chan, - req->bssid, req->ssid, - req->ssid_len); - if (bss) { - cfg80211_assoc_timeout(ndev, bss); - return -ETIMEDOUT; - } - } - return -EINVAL; - } - - if (!policy_mgr_allow_concurrency(hdd_ctx->psoc, - policy_mgr_convert_device_mode_to_qdf_type( - adapter->device_mode), - req->channel->hw_value, HW_MODE_20_MHZ)) { - hdd_warn("This concurrency combination is not allowed"); - status = -ECONNREFUSED; - goto con_chk_failed; - } - } else { - if (!policy_mgr_allow_concurrency(hdd_ctx->psoc, - policy_mgr_convert_device_mode_to_qdf_type( - adapter->device_mode), 0, HW_MODE_20_MHZ)) { - hdd_warn("This concurrency combination is not allowed"); - status = -ECONNREFUSED; - goto con_chk_failed; - } - } - if (req->channel) channel = req->channel->hw_value; else @@ -20654,14 +21393,11 @@ static int __wlan_hdd_cfg80211_connect(struct wiphy *wiphy, status = wlan_hdd_cfg80211_connect_start(adapter, req->ssid, req->ssid_len, req->bssid, bssid_hint, channel, 0); - if (0 > status) { + if (status) { hdd_err("connect failed"); + wlan_hdd_cfg80211_clear_privacy(adapter); } - return status; -con_chk_failed: - wlan_hdd_cfg80211_clear_privacy(adapter); - hdd_exit(); return status; } @@ -20686,113 +21422,6 @@ static int wlan_hdd_cfg80211_connect(struct wiphy *wiphy, return ret; } -int wlan_hdd_disconnect(struct hdd_adapter *adapter, u16 reason) -{ - QDF_STATUS status; - int result = 0; - unsigned long rc; - struct hdd_station_ctx *sta_ctx = WLAN_HDD_GET_STATION_CTX_PTR(adapter); - struct hdd_context *hdd_ctx = WLAN_HDD_GET_CTX(adapter); - eConnectionState prev_conn_state; - mac_handle_t mac_handle; - uint32_t wait_time = WLAN_WAIT_TIME_DISCONNECT; - - hdd_enter(); - - mac_handle = hdd_ctx->mac_handle; - if (adapter->device_mode == QDF_STA_MODE) { - hdd_debug("Stop firmware roaming"); - status = sme_stop_roaming(mac_handle, adapter->session_id, - eCsrForcedDisassoc); - /* - * If firmware has already started roaming process, driver - * needs to wait for processing of this disconnect request. - * - */ - INIT_COMPLETION(adapter->roaming_comp_var); - if (hdd_is_roaming_in_progress(hdd_ctx)) { - rc = wait_for_completion_timeout( - &adapter->roaming_comp_var, - msecs_to_jiffies(WLAN_WAIT_TIME_STOP_ROAM)); - if (!rc) { - hdd_err("roaming comp var timed out session Id: %d", - adapter->session_id); - } - if (adapter->roam_ho_fail) { - INIT_COMPLETION(adapter->disconnect_comp_var); - hdd_debug("Disabling queues"); - wlan_hdd_netif_queue_control(adapter, - WLAN_STOP_ALL_NETIF_QUEUE_N_CARRIER, - WLAN_CONTROL_PATH); - hdd_conn_set_connection_state(adapter, - eConnectionState_Disconnecting); - goto wait_for_disconnect; - } - } - } - - prev_conn_state = sta_ctx->conn_info.connState; - /*stop tx queues */ - hdd_info("Disabling queues"); - wlan_hdd_netif_queue_control(adapter, - WLAN_STOP_ALL_NETIF_QUEUE_N_CARRIER, WLAN_CONTROL_PATH); - hdd_debug("Set HDD connState to eConnectionState_Disconnecting"); - hdd_conn_set_connection_state(adapter, eConnectionState_Disconnecting); - - INIT_COMPLETION(adapter->disconnect_comp_var); - - /* issue disconnect */ - - status = sme_roam_disconnect(mac_handle, - adapter->session_id, reason); - if ((QDF_STATUS_CMD_NOT_QUEUED == status) && - prev_conn_state != eConnectionState_Connecting) { - hdd_debug("status = %d, already disconnected", status); - result = 0; - /* - * Wait here instead of returning directly. This will block the - * next connect command and allow processing of the disconnect - * in SME else we might hit some race conditions leading to SME - * and HDD out of sync. As disconnect is already in progress, - * wait here for 1 sec instead of 5 sec. - */ - wait_time = WLAN_WAIT_DISCONNECT_ALREADY_IN_PROGRESS; - } else if (QDF_STATUS_CMD_NOT_QUEUED == status) { - /* - * Wait here instead of returning directly, this will block the - * next connect command and allow processing of the scan for - * ssid and the previous connect command in CSR. Else we might - * hit some race conditions leading to SME and HDD out of sync. - */ - hdd_debug("Already disconnected or connect was in sme/roam pending list and removed by disconnect"); - } else if (0 != status) { - hdd_err("csr_roam_disconnect failure, status: %d", (int)status); - sta_ctx->sta_debug_state = status; - result = -EINVAL; - goto disconnected; - } -wait_for_disconnect: - rc = wait_for_completion_timeout(&adapter->disconnect_comp_var, - msecs_to_jiffies(wait_time)); - - if (!rc && (QDF_STATUS_CMD_NOT_QUEUED != status)) { - hdd_err("Failed to disconnect, timed out"); - result = -ETIMEDOUT; - } -disconnected: - hdd_conn_set_connection_state(adapter, eConnectionState_NotConnected); -#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0) - /* Sending disconnect event to userspace for kernel version < 3.11 - * is handled by __cfg80211_disconnect call to __cfg80211_disconnected - */ - hdd_debug("Send disconnected event to userspace"); - wlan_hdd_cfg80211_indicate_disconnect(adapter->dev, true, - WLAN_REASON_UNSPECIFIED); -#endif - - return result; -} - /** * hdd_ieee80211_reason_code_to_str() - return string conversion of reason code * @reason: ieee80211 reason code. @@ -20854,11 +21483,232 @@ static const char *hdd_ieee80211_reason_code_to_str(uint16_t reason) CASE_RETURN_STRING(WLAN_REASON_MESH_CHAN_REGULATORY); CASE_RETURN_STRING(WLAN_REASON_MESH_CHAN); default: - return "Unknown"; + return "Unknown"; + } +} +#endif + +/** + * hdd_qca_reason_to_str() - return string conversion of qca reason code + * @reason: enum qca_disconnect_reason_codes + * + * This utility function helps log string conversion of qca reason code. + * + * Return: string conversion of reason code, if match found; + * "Unknown" otherwise. + */ +#ifdef WLAN_DEBUG +static const char * +hdd_qca_reason_to_str(enum qca_disconnect_reason_codes reason) +{ + switch (reason) { + CASE_RETURN_STRING(QCA_DISCONNECT_REASON_INTERNAL_ROAM_FAILURE); + CASE_RETURN_STRING(QCA_DISCONNECT_REASON_EXTERNAL_ROAM_FAILURE); + CASE_RETURN_STRING(QCA_DISCONNECT_REASON_GATEWAY_REACHABILITY_FAILURE); + CASE_RETURN_STRING(QCA_DISCONNECT_REASON_UNSUPPORTED_CHANNEL_CSA); + CASE_RETURN_STRING(QCA_DISCONNECT_REASON_OPER_CHANNEL_DISABLED_INDOOR); + CASE_RETURN_STRING(QCA_DISCONNECT_REASON_OPER_CHANNEL_USER_DISABLED); + CASE_RETURN_STRING(QCA_DISCONNECT_REASON_DEVICE_RECOVERY); + CASE_RETURN_STRING(QCA_DISCONNECT_REASON_KEY_TIMEOUT); + CASE_RETURN_STRING(QCA_DISCONNECT_REASON_OPER_CHANNEL_BAND_CHANGE); + CASE_RETURN_STRING(QCA_DISCONNECT_REASON_IFACE_DOWN); + CASE_RETURN_STRING(QCA_DISCONNECT_REASON_PEER_XRETRY_FAIL); + CASE_RETURN_STRING(QCA_DISCONNECT_REASON_PEER_INACTIVITY); + CASE_RETURN_STRING(QCA_DISCONNECT_REASON_SA_QUERY_TIMEOUT); + CASE_RETURN_STRING(QCA_DISCONNECT_REASON_BEACON_MISS_FAILURE); + CASE_RETURN_STRING(QCA_DISCONNECT_REASON_CHANNEL_SWITCH_FAILURE); + CASE_RETURN_STRING(QCA_DISCONNECT_REASON_USER_TRIGGERED); + case QCA_DISCONNECT_REASON_UNSPECIFIED: + return ""; + default: + return "Unknown"; + } +} +#endif + +/** + * wlan_hdd_sir_mac_to_qca_reason() - Convert to qca internal disconnect reason + * @internal_reason: Mac reason code of type @enum eSirMacReasonCodes + * + * Check if it is internal reason code and convert it to the + * enum qca_disconnect_reason_codes. + * + * Return: Reason code of type enum qca_disconnect_reason_codes + */ +static enum qca_disconnect_reason_codes +wlan_hdd_sir_mac_to_qca_reason(enum eSirMacReasonCodes internal_reason) +{ + enum qca_disconnect_reason_codes reason = + QCA_DISCONNECT_REASON_UNSPECIFIED; + switch (internal_reason) { + case eSIR_MAC_HOST_TRIGGERED_ROAM_FAILURE: + reason = QCA_DISCONNECT_REASON_INTERNAL_ROAM_FAILURE; + break; + case eSIR_MAC_FW_TRIGGERED_ROAM_FAILURE: + reason = QCA_DISCONNECT_REASON_EXTERNAL_ROAM_FAILURE; + break; + case eSIR_MAC_GATEWAY_REACHABILITY_FAILURE: + reason = + QCA_DISCONNECT_REASON_GATEWAY_REACHABILITY_FAILURE; + break; + case eSIR_MAC_UNSUPPORTED_CHANNEL_CSA: + reason = QCA_DISCONNECT_REASON_UNSUPPORTED_CHANNEL_CSA; + break; + case eSIR_MAC_OPER_CHANNEL_DISABLED_INDOOR: + reason = + QCA_DISCONNECT_REASON_OPER_CHANNEL_DISABLED_INDOOR; + break; + case eSIR_MAC_OPER_CHANNEL_USER_DISABLED: + reason = + QCA_DISCONNECT_REASON_OPER_CHANNEL_USER_DISABLED; + break; + case eSIR_MAC_DEVICE_RECOVERY: + reason = QCA_DISCONNECT_REASON_DEVICE_RECOVERY; + break; + case eSIR_MAC_KEY_TIMEOUT: + reason = QCA_DISCONNECT_REASON_KEY_TIMEOUT; + break; + case eSIR_MAC_OPER_CHANNEL_BAND_CHANGE: + reason = QCA_DISCONNECT_REASON_OPER_CHANNEL_BAND_CHANGE; + break; + case eSIR_MAC_IFACE_DOWN: + reason = QCA_DISCONNECT_REASON_IFACE_DOWN; + break; + case eSIR_MAC_PEER_XRETRY_FAIL: + reason = QCA_DISCONNECT_REASON_PEER_XRETRY_FAIL; + break; + case eSIR_MAC_PEER_INACTIVITY: + reason = QCA_DISCONNECT_REASON_PEER_INACTIVITY; + break; + case eSIR_MAC_SA_QUERY_TIMEOUT: + reason = QCA_DISCONNECT_REASON_SA_QUERY_TIMEOUT; + break; + case eSIR_MAC_CHANNEL_SWITCH_FAILED: + reason = QCA_DISCONNECT_REASON_CHANNEL_SWITCH_FAILURE; + break; + case eSIR_MAC_BEACON_MISSED: + reason = QCA_DISCONNECT_REASON_BEACON_MISS_FAILURE; + break; + case eSIR_MAC_USER_TRIGGERED_ROAM_FAILURE: + reason = QCA_DISCONNECT_REASON_USER_TRIGGERED; + break; + default: + hdd_debug("No QCA reason code for mac reason: %u", + internal_reason); + /* Unspecified reason by default */ + } + + return reason; +} + +/** + * wlan_hdd_get_ieee80211_disconnect_reason() - Get ieee80211 disconnect reason + * @adapter: pointer to adapter structure + * @reason: Mac Disconnect reason code as per @enum eSirMacReasonCodes + * + * Reason codes that are greater than eSIR_MAC_REASON_PROP_START are internal + * reason codes. Convert them to qca reason code format and cache in adapter + * and return UNSPECIFIED. + * Rest of the reason codes are valid ieee80211 reason codes. + * + * Return: Reason code of type ieee80211_reasoncode. + */ +static enum ieee80211_reasoncode +wlan_hdd_get_cfg80211_disconnect_reason(struct hdd_adapter *adapter, + enum eSirMacReasonCodes reason) +{ + enum ieee80211_reasoncode ieee80211_reason = WLAN_REASON_UNSPECIFIED; + + /* + * Convert and cache internal reason code in adapter. This can be + * sent to userspace with a vendor event. + */ + if (reason >= eSIR_MAC_REASON_PROP_START) { + adapter->last_disconnect_reason = + wlan_hdd_sir_mac_to_qca_reason(reason); + } else { + ieee80211_reason = (enum ieee80211_reasoncode)reason; + adapter->last_disconnect_reason = + QCA_DISCONNECT_REASON_UNSPECIFIED; } + + return ieee80211_reason; } + +#if defined(CFG80211_DISCONNECTED_V2) || \ +(LINUX_VERSION_CODE >= KERNEL_VERSION(4, 2, 0)) +void +wlan_hdd_cfg80211_indicate_disconnect(struct hdd_adapter *adapter, + bool locally_generated, + enum eSirMacReasonCodes reason, + uint8_t *disconnect_ies, + uint16_t disconnect_ies_len) +{ + enum ieee80211_reasoncode ieee80211_reason; + + ieee80211_reason = wlan_hdd_get_cfg80211_disconnect_reason(adapter, + reason); + hdd_nofl_info("Disconnect reason: %u %s vendor: %u %s LG: %u", + ieee80211_reason, + hdd_ieee80211_reason_code_to_str(ieee80211_reason), + adapter->last_disconnect_reason, + hdd_qca_reason_to_str(adapter->last_disconnect_reason), + locally_generated); + cfg80211_disconnected(adapter->dev, ieee80211_reason, disconnect_ies, + disconnect_ies_len, locally_generated, + GFP_KERNEL); +} +#else +void +wlan_hdd_cfg80211_indicate_disconnect(struct hdd_adapter *adapter, + bool locally_generated, + enum eSirMacReasonCodes reason, + uint8_t *disconnect_ies, + uint16_t disconnect_ies_len) +{ + enum ieee80211_reasoncode ieee80211_reason; + + ieee80211_reason = wlan_hdd_get_cfg80211_disconnect_reason(adapter, + reason); + hdd_nofl_info("Disconnect reason: %u %s vendor: %u %s LG: %u", + ieee80211_reason, + hdd_ieee80211_reason_code_to_str(ieee80211_reason), + adapter->last_disconnect_reason, + hdd_qca_reason_to_str(adapter->last_disconnect_reason), + locally_generated); + cfg80211_disconnected(adapter->dev, ieee80211_reason, disconnect_ies, + disconnect_ies_len, GFP_KERNEL); +} +#endif + +int wlan_hdd_disconnect(struct hdd_adapter *adapter, u16 reason, + tSirMacReasonCodes mac_reason) +{ + int ret; + mac_handle_t mac_handle; + + mac_handle = hdd_adapter_get_mac_handle(adapter); + wlan_hdd_wait_for_roaming(mac_handle, adapter); + + /*stop tx queues */ + hdd_debug("Disabling queues"); + wlan_hdd_netif_queue_control(adapter, + WLAN_STOP_ALL_NETIF_QUEUE_N_CARRIER, WLAN_CONTROL_PATH); + + ret = wlan_hdd_wait_for_disconnect(mac_handle, adapter, reason, + mac_reason); + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 11, 0) + /* Sending disconnect event to userspace for kernel version < 3.11 + * is handled by __cfg80211_disconnect call to __cfg80211_disconnected + */ + wlan_hdd_cfg80211_indicate_disconnect(adapter, true, + mac_reason, NULL, 0); #endif + return ret; +} + /** * hdd_print_netdev_txq_status() - print netdev tx queue status * @dev: Pointer to network device @@ -20903,8 +21753,6 @@ static int __wlan_hdd_cfg80211_disconnect(struct wiphy *wiphy, struct hdd_context *hdd_ctx = WLAN_HDD_GET_CTX(adapter); struct wlan_objmgr_vdev *vdev; - hdd_enter(); - if (QDF_GLOBAL_FTM_MODE == hdd_get_conparam()) { hdd_err("Command not allowed in FTM mode"); return -EINVAL; @@ -20918,10 +21766,6 @@ static int __wlan_hdd_cfg80211_disconnect(struct wiphy *wiphy, adapter->session_id, reason); hdd_print_netdev_txq_status(dev); - hdd_debug("Device_mode %s(%d) reason code(%d)", - hdd_device_mode_to_string(adapter->device_mode), - adapter->device_mode, reason); - status = wlan_hdd_validate_context(hdd_ctx); if (0 != status) @@ -20978,12 +21822,11 @@ static int __wlan_hdd_cfg80211_disconnect(struct wiphy *wiphy, vdev = hdd_objmgr_get_vdev(adapter); if (vdev && - ucfg_scan_get_vdev_status(vdev) != SCAN_NOT_IN_PROGRESS) { - hdd_debug("Disconnect is in progress, Aborting Scan"); + ucfg_scan_get_vdev_status(vdev) != SCAN_NOT_IN_PROGRESS) wlan_abort_scan(hdd_ctx->pdev, INVAL_PDEV_ID, adapter->session_id, INVALID_SCAN_ID, false); - } + wlan_hdd_cleanup_remain_on_channel_ctx(adapter); /* First clean up the tdls peers if any */ hdd_notify_sta_disconnect(adapter->session_id, @@ -20991,10 +21834,10 @@ static int __wlan_hdd_cfg80211_disconnect(struct wiphy *wiphy, if (vdev) hdd_objmgr_put_vdev(vdev); - hdd_info("%s(vdevid-%d): Disconnect from userspace; reason:%d (%s)", - dev->name, adapter->session_id, reason, - hdd_ieee80211_reason_code_to_str(reason)); - status = wlan_hdd_disconnect(adapter, reasonCode); + hdd_nofl_info("%s(vdevid-%d): Received Disconnect reason:%d %s", + dev->name, adapter->session_id, reason, + hdd_ieee80211_reason_code_to_str(reason)); + status = wlan_hdd_disconnect(adapter, reasonCode, reason); if (0 != status) { hdd_err("wlan_hdd_disconnect failed, status: %d", status); hdd_set_disconnect_status(adapter, false); @@ -21237,7 +22080,8 @@ static int __wlan_hdd_cfg80211_join_ibss(struct wiphy *wiphy, } /*Try disconnecting if already in connected state */ - status = wlan_hdd_try_disconnect(adapter); + status = wlan_hdd_try_disconnect(adapter, + eSIR_MAC_UNSPEC_FAILURE_REASON); if (0 > status) { hdd_err("Failed to disconnect the existing IBSS connection"); return -EALREADY; @@ -21361,8 +22205,6 @@ static int __wlan_hdd_cfg80211_leave_ibss(struct wiphy *wiphy, unsigned long rc; tSirUpdateIE updateIE; - hdd_enter(); - if (QDF_GLOBAL_FTM_MODE == hdd_get_conparam()) { hdd_err("Command not allowed in FTM mode"); return -EINVAL; @@ -21412,7 +22254,8 @@ static int __wlan_hdd_cfg80211_leave_ibss(struct wiphy *wiphy, INIT_COMPLETION(adapter->disconnect_comp_var); status = sme_roam_disconnect(mac_handle, adapter->session_id, - eCSR_DISCONNECT_REASON_IBSS_LEAVE); + eCSR_DISCONNECT_REASON_IBSS_LEAVE, + eSIR_MAC_UNSPEC_FAILURE_REASON); if (!QDF_IS_STATUS_SUCCESS(status)) { hdd_err("sme_roam_disconnect failed status: %d", status); @@ -22518,6 +23361,8 @@ int __wlan_hdd_cfg80211_set_rekey_data(struct wiphy *wiphy, wlan_hdd_copy_gtk_kek(gtk_req, data); qdf_mem_copy(gtk_req->kck, data->kck, NL80211_KCK_LEN); + gtk_req->kck_len = NL80211_KCK_LEN; + gtk_req->is_fils_connection = hdd_is_fils_connection(adapter); status = pmo_ucfg_cache_gtk_offload_req(adapter->vdev, gtk_req); if (status != QDF_STATUS_SUCCESS) { @@ -23090,8 +23935,6 @@ int wlan_hdd_change_hw_mode_for_given_chnl(struct hdd_adapter *adapter, struct hdd_context *hdd_ctx = WLAN_HDD_GET_CTX(adapter); hdd_enter(); - if (0 != wlan_hdd_validate_context(hdd_ctx)) - return -EINVAL; status = policy_mgr_reset_connection_update(hdd_ctx->psoc); if (!QDF_IS_STATUS_SUCCESS(status)) @@ -23158,10 +24001,10 @@ static int __wlan_hdd_cfg80211_set_mon_ch(struct wiphy *wiphy, mac_handle_t mac_handle; struct qdf_mac_addr bssid; struct csr_roam_profile roam_profile; - struct ch_params ch_params; - uint8_t sec_ch = 0; int ret; uint16_t chan_num = cds_freq_to_chan(chandef->chan->center_freq); + uint8_t max_fw_bw; + enum phy_ch_width ch_width; hdd_enter(); @@ -23189,26 +24032,31 @@ static int __wlan_hdd_cfg80211_set_mon_ch(struct wiphy *wiphy, qdf_mem_copy(bssid.bytes, adapter->mac_addr.bytes, QDF_MAC_ADDR_SIZE); - ch_params.ch_width = hdd_map_nl_chan_width(chandef->width); - /* - * CDS api expects secondary channel for calculating - * the channel params - */ - if ((ch_params.ch_width == CH_WIDTH_40MHZ) && - (WLAN_REG_IS_24GHZ_CH(chan_num))) { - if (chan_num >= 1 && chan_num <= 5) - sec_ch = chan_num + 4; - else if (chan_num >= 6 && chan_num <= 13) - sec_ch = chan_num - 4; - } - wlan_reg_set_channel_params(hdd_ctx->pdev, chan_num, - sec_ch, &ch_params); + ch_width = hdd_map_nl_chan_width(chandef->width); + + if (ch_width > CH_WIDTH_10MHZ || + (!cds_is_sub_20_mhz_enabled() && ch_width > CH_WIDTH_160MHZ)) { + hdd_err("invalid BW received %d", ch_width); + return -EINVAL; + } + + max_fw_bw = sme_get_vht_ch_width(); + if ((ch_width == CH_WIDTH_160MHZ && + max_fw_bw <= WNI_CFG_VHT_CHANNEL_WIDTH_80MHZ) || + (ch_width == CH_WIDTH_80P80MHZ && + max_fw_bw <= WNI_CFG_VHT_CHANNEL_WIDTH_160MHZ)) { + hdd_err("FW does not support this BW %d max BW supported %d", + ch_width, max_fw_bw); + return -EINVAL; + } + if (wlan_hdd_change_hw_mode_for_given_chnl(adapter, chan_num, POLICY_MGR_UPDATE_REASON_SET_OPER_CHAN)) { hdd_err("Failed to change hw mode"); return -EINVAL; } - status = sme_roam_channel_change_req(mac_handle, bssid, &ch_params, + status = sme_roam_channel_change_req(mac_handle, bssid, + &roam_profile.ch_params, &roam_profile); if (status) { hdd_err("Failed to set sme_RoamChannel for monitor mode status: %d", @@ -23297,10 +24145,9 @@ static void hdd_update_chan_info(struct hdd_context *hdd_ctx, #undef CNT_DIFF #undef MAX_COUNT -#if defined(WLAN_FEATURE_FILS_SK) &&\ - defined(CFG80211_FILS_SK_OFFLOAD_SUPPORT) &&\ - (defined(CFG80211_UPDATE_CONNECT_PARAMS) ||\ - (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 10, 0))) +#ifndef UPDATE_ASSOC_IE +#define UPDATE_ASSOC_IE BIT(0) +#endif #ifndef UPDATE_FILS_ERP_INFO #define UPDATE_FILS_ERP_INFO BIT(1) @@ -23310,62 +24157,43 @@ static void hdd_update_chan_info(struct hdd_context *hdd_ctx, #define UPDATE_FILS_AUTH_TYPE BIT(2) #endif +#if defined(WLAN_FEATURE_FILS_SK) &&\ + defined(CFG80211_FILS_SK_OFFLOAD_SUPPORT) &&\ + (defined(CFG80211_UPDATE_CONNECT_PARAMS) ||\ + (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 10, 0))) + /** - * __wlan_hdd_cfg80211_update_connect_params - update connect params - * @wiphy: Handle to struct wiphy to get handle to module context. - * @dev: Pointer to network device + * hdd_update_connect_params_fils_info() - Update fils parameters based on + * the update_connect_params received from userspace + * @adapter: Pointer to hdd_adapter + * @hdd_ctx: Pointer to hdd_context * @req: Pointer to connect params - * @changed: Bitmap used to indicate the changed params + * @changed: bitmap indicating which parameters have changed * - * Update the connect parameters while connected to a BSS. The updated - * parameters can be used by driver/firmware for subsequent BSS selection - * (roaming) decisions and to form the Authentication/(Re)Association - * Request frames. This call does not request an immediate disassociation - * or reassociation with the current BSS, i.e., this impacts only - * subsequent (re)associations. The bits in changed are defined in enum - * cfg80211_connect_params_changed - * - * Return: zero for success, non-zero for failure + * Return 0 on SUCCESS or error code on FAILURE */ static int -__wlan_hdd_cfg80211_update_connect_params(struct wiphy *wiphy, - struct net_device *dev, - struct cfg80211_connect_params *req, - uint32_t changed) +hdd_update_connect_params_fils_info(struct hdd_adapter *adapter, + struct hdd_context *hdd_ctx, + struct cfg80211_connect_params *req, + uint32_t changed) { - struct csr_roam_profile *roam_profile; uint8_t *buf; - int ret; - enum eAniAuthType auth_type; - struct hdd_adapter *adapter = WLAN_HDD_GET_PRIV_PTR(dev); - struct hdd_context *hdd_ctx = wiphy_priv(wiphy); QDF_STATUS status; - struct cds_fils_connection_info *fils_info; mac_handle_t mac_handle; - - hdd_enter_dev(dev); - - if (wlan_hdd_validate_session_id(adapter->session_id)) - return -EINVAL; - - ret = wlan_hdd_validate_context(hdd_ctx); - if (ret) - return -EINVAL; + struct csr_roam_profile *roam_profile; + struct cds_fils_connection_info *fils_info; + enum eAniAuthType auth_type; roam_profile = hdd_roam_profile(adapter); fils_info = roam_profile->fils_con_info; - + mac_handle = hdd_ctx->mac_handle; if (!fils_info) { hdd_err("No valid FILS conn info"); return -EINVAL; } - if (req->ie_len) - wlan_hdd_cfg80211_set_ie(adapter, req->ie, req->ie_len); - - if (changed) - fils_info->is_fils_connection = true; - + fils_info->is_fils_connection = true; if (changed & UPDATE_FILS_ERP_INFO) { if (!wlan_hdd_fils_data_in_limits(req)) return -EINVAL; @@ -23391,6 +24219,11 @@ __wlan_hdd_cfg80211_update_connect_params(struct wiphy *wiphy, fils_info->sequence_number = req->fils_erp_next_seq_num + 1; fils_info->r_rk_length = req->fils_erp_rrk_len; + if (fils_info->r_rk_length > FILS_MAX_RRK_LENGTH) { + hdd_err("r_rk_length is invalid"); + return -EINVAL; + } + if (req->fils_erp_rrk_len && req->fils_erp_rrk) qdf_mem_copy(fils_info->r_rk, req->fils_erp_rrk, fils_info->r_rk_length); @@ -23416,17 +24249,113 @@ __wlan_hdd_cfg80211_update_connect_params(struct wiphy *wiphy, changed, roam_profile->fils_con_info->is_fils_connection, roam_profile->fils_con_info->key_nai_length); - if (!hdd_ctx->is_fils_roaming_supported) { - hdd_debug("FILS roaming support %d", - hdd_ctx->is_fils_roaming_supported); - return 0; - } - - mac_handle = hdd_ctx->mac_handle; + /* + * Update the FILS config from adapter->roam_profile to + * csr_session + */ status = sme_update_fils_config(mac_handle, adapter->session_id, roam_profile); if (QDF_IS_STATUS_ERROR(status)) - hdd_err("Update FILS connect params to Fw failed %d", status); + hdd_err("Update FILS connect params to csr failed %d", status); + + return 0; +} +#else + +static int +hdd_update_connect_params_fils_info(struct hdd_adapter *adapter, + struct hdd_context *hdd_ctx, + struct cfg80211_connect_params *req, + uint32_t changed) +{ + return -EINVAL; +} + +#endif + +#if defined(CFG80211_UPDATE_CONNECT_PARAMS) ||\ + (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 10, 0)) + +/** + * __wlan_hdd_cfg80211_update_connect_params - update connect params + * @wiphy: Handle to struct wiphy to get handle to module context. + * @dev: Pointer to network device + * @req: Pointer to connect params + * @changed: Bitmap used to indicate the changed params + * + * Update the connect parameters while connected to a BSS. The updated + * parameters can be used by driver/firmware for subsequent BSS selection + * (roaming) decisions and to form the Authentication/(Re)Association + * Request frames. This call does not request an immediate disassociation + * or reassociation with the current BSS, i.e., this impacts only + * subsequent (re)associations. The bits in changed are defined in enum + * cfg80211_connect_params_changed + * + * Return: zero for success, non-zero for failure + */ +static int +__wlan_hdd_cfg80211_update_connect_params(struct wiphy *wiphy, + struct net_device *dev, + struct cfg80211_connect_params *req, + uint32_t changed) +{ + struct csr_roam_profile *roam_profile; + int ret; + struct hdd_adapter *adapter = WLAN_HDD_GET_PRIV_PTR(dev); + struct hdd_context *hdd_ctx = wiphy_priv(wiphy); + QDF_STATUS status; + mac_handle_t mac_handle; + + hdd_enter_dev(dev); + + if (wlan_hdd_validate_session_id(adapter->session_id)) + return -EINVAL; + + ret = wlan_hdd_validate_context(hdd_ctx); + if (ret) + return -EINVAL; + + mac_handle = hdd_ctx->mac_handle; + roam_profile = hdd_roam_profile(adapter); + + if (changed & UPDATE_ASSOC_IE) { + /* + * Validate the elements of the IE and copy it to + * roam_profile in adapter + */ + wlan_hdd_cfg80211_set_ie(adapter, req->ie, req->ie_len); + + /* + * Update this assoc IE received from user space to + * csr_session. RSO command will pick up the assoc + * IEs to be sent to firmware from the csr_session. + */ + sme_update_session_assoc_ie(mac_handle, adapter->session_id, + roam_profile); + } + + if ((changed & UPDATE_FILS_ERP_INFO) || + (changed & UPDATE_FILS_AUTH_TYPE)) { + ret = hdd_update_connect_params_fils_info(adapter, hdd_ctx, + req, changed); + if (ret) + return -EINVAL; + + if (!hdd_ctx->is_fils_roaming_supported) { + hdd_debug("FILS roaming support %d", + hdd_ctx->is_fils_roaming_supported); + return 0; + } + } + + if (changed) { + status = sme_send_rso_connect_params(mac_handle, + adapter->session_id, + roam_profile); + if (QDF_IS_STATUS_ERROR(status)) + hdd_err("Update connect params to fw failed %d", + status); + } return 0; } @@ -23460,6 +24389,24 @@ wlan_hdd_cfg80211_update_connect_params(struct wiphy *wiphy, #if defined(WLAN_FEATURE_SAE) && \ defined(CFG80211_EXTERNAL_AUTH_SUPPORT) +/** + * wlan_hdd_extauth_copy_pmkid() - Copy the pmkid received from the + * external authentication command received from the userspace. + * @params: pointer to auth params + * @pmkid: Pointer to destination pmkid buffer to be filled + * + * The caller should ensure that destination pmkid buffer is not NULL. + * + * Return: None + */ +static void +wlan_hdd_extauth_copy_pmkid(struct cfg80211_external_auth_params *params, + uint8_t *pmkid) +{ + if (params->pmkid) + qdf_mem_copy(pmkid, params->pmkid, PMKID_LEN); +} + /** * __wlan_hdd_cfg80211_external_auth() - Handle external auth * @wiphy: Pointer to wireless phy @@ -23477,6 +24424,8 @@ __wlan_hdd_cfg80211_external_auth(struct wiphy *wiphy, struct hdd_adapter *adapter = WLAN_HDD_GET_PRIV_PTR(dev); int ret; mac_handle_t mac_handle; + uint8_t pmkid[PMKID_LEN] = {0}; + struct qdf_mac_addr peer_mac_addr; if (hdd_get_conparam() == QDF_GLOBAL_FTM_MODE) { hdd_err("Command not allowed in FTM mode"); @@ -23490,11 +24439,14 @@ __wlan_hdd_cfg80211_external_auth(struct wiphy *wiphy, if (ret) return ret; + hdd_debug("external_auth status: %d peer mac: " QDF_MAC_ADDR_STR, + params->status, QDF_MAC_ADDR_ARRAY(params->bssid)); - hdd_debug("external_auth status: %d", params->status); mac_handle = hdd_ctx->mac_handle; - sme_handle_sae_msg(mac_handle, adapter->session_id, params->status); - + qdf_mem_copy(peer_mac_addr.bytes, params->bssid, QDF_MAC_ADDR_SIZE); + wlan_hdd_extauth_copy_pmkid(params, pmkid); + sme_handle_sae_msg(mac_handle, adapter->session_id, params->status, + peer_mac_addr, pmkid); return ret; } @@ -23521,6 +24473,42 @@ wlan_hdd_cfg80211_external_auth(struct wiphy *wiphy, } #endif +#if defined(WLAN_FEATURE_NAN) && \ + (KERNEL_VERSION(4, 9, 0) <= LINUX_VERSION_CODE) +static int +wlan_hdd_cfg80211_start_nan(struct wiphy *wiphy, struct wireless_dev *wdev, + struct cfg80211_nan_conf *conf) +{ + return -EOPNOTSUPP; +} + +static void +wlan_hdd_cfg80211_stop_nan(struct wiphy *wiphy, struct wireless_dev *wdev) +{ +} + +static int wlan_hdd_cfg80211_add_nan_func(struct wiphy *wiphy, + struct wireless_dev *wdev, + struct cfg80211_nan_func *nan_func) +{ + return -EOPNOTSUPP; +} + +static void wlan_hdd_cfg80211_del_nan_func(struct wiphy *wiphy, + struct wireless_dev *wdev, + u64 cookie) +{ +} + +static int wlan_hdd_cfg80211_nan_change_conf(struct wiphy *wiphy, + struct wireless_dev *wdev, + struct cfg80211_nan_conf *conf, + u32 changes) +{ + return -EOPNOTSUPP; +} +#endif + /** * wlan_hdd_chan_info_cb() - channel info callback * @chan_info: struct scan_chan_info @@ -23535,8 +24523,6 @@ static void wlan_hdd_chan_info_cb(struct scan_chan_info *info) struct scan_chan_info *chan; uint8_t idx; - hdd_enter(); - hdd_ctx = cds_get_context(QDF_MODULE_ID_HDD); if (wlan_hdd_validate_context(hdd_ctx) != 0) { hdd_err("hdd_ctx is invalid"); @@ -23565,8 +24551,6 @@ static void wlan_hdd_chan_info_cb(struct scan_chan_info *info) } } - - hdd_exit(); } /** @@ -23819,14 +24803,21 @@ static struct cfg80211_ops wlan_hdd_cfg80211_ops = { defined(CFG80211_ABORT_SCAN) .abort_scan = wlan_hdd_cfg80211_abort_scan, #endif -#if defined(WLAN_FEATURE_FILS_SK) &&\ - defined(CFG80211_FILS_SK_OFFLOAD_SUPPORT) &&\ - (defined(CFG80211_UPDATE_CONNECT_PARAMS) ||\ - (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 10, 0))) +#if defined(CFG80211_UPDATE_CONNECT_PARAMS) || \ + (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 10, 0)) .update_connect_params = wlan_hdd_cfg80211_update_connect_params, #endif #if defined(WLAN_FEATURE_SAE) && \ defined(CFG80211_EXTERNAL_AUTH_SUPPORT) .external_auth = wlan_hdd_cfg80211_external_auth, #endif +#if defined(WLAN_FEATURE_NAN) && \ + (KERNEL_VERSION(4, 9, 0) <= LINUX_VERSION_CODE) + .start_nan = wlan_hdd_cfg80211_start_nan, + .stop_nan = wlan_hdd_cfg80211_stop_nan, + .add_nan_func = wlan_hdd_cfg80211_add_nan_func, + .del_nan_func = wlan_hdd_cfg80211_del_nan_func, + .nan_change_conf = wlan_hdd_cfg80211_nan_change_conf, +#endif + }; diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_cfg80211.h b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_cfg80211.h index d66addd5eccd..7311c61c31b5 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_cfg80211.h +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_cfg80211.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -115,6 +115,14 @@ struct hdd_context; #define WLAN_AKM_SUITE_SAE 0x000FAC08 #endif +#ifndef WLAN_AKM_SUITE_FT_SAE +#define WLAN_AKM_SUITE_FT_SAE 0x000FAC09 +#endif + +#ifndef WLAN_AKM_SUITE_FT_EAP_SHA_384 +#define WLAN_AKM_SUITE_FT_EAP_SHA_384 0x000FAC0D +#endif + #ifdef FEATURE_WLAN_TDLS #define WLAN_IS_TDLS_SETUP_ACTION(action) \ ((SIR_MAC_TDLS_SETUP_REQ <= action) && \ @@ -211,11 +219,11 @@ typedef enum { #define CFG_NON_AGG_RETRY_MAX (31) #define CFG_AGG_RETRY_MAX (31) -#define CFG_MGMT_RETRY_MAX (31) #define CFG_CTRL_RETRY_MAX (31) #define CFG_PROPAGATION_DELAY_MAX (63) #define CFG_PROPAGATION_DELAY_BASE (64) #define CFG_AGG_RETRY_MIN (5) +#define MGMT_RETRY_MAX (31) struct cfg80211_bss * wlan_hdd_cfg80211_update_bss_db(struct hdd_adapter *adapter, @@ -396,11 +404,29 @@ void wlan_hdd_cfg80211_unlink_bss(struct hdd_adapter *adapter, void wlan_hdd_cfg80211_acs_ch_select_evt(struct hdd_adapter *adapter); #ifdef WLAN_FEATURE_ROAM_OFFLOAD +/** + * hdd_send_roam_scan_ch_list_event() - roam scan ch list event to user space + * @hdd_ctx: HDD context + * @buf_len: length of frequency list + * @buf: pointer to buffer of frequency list + * + * Return: None + */ +void hdd_send_roam_scan_ch_list_event(struct hdd_context *hdd_ctx, + uint16_t buf_len, uint8_t *buf); + int wlan_hdd_send_roam_auth_event(struct hdd_adapter *adapter, uint8_t *bssid, uint8_t *req_rsn_ie, uint32_t req_rsn_length, uint8_t *rsp_rsn_ie, uint32_t rsp_rsn_length, struct csr_roam_info *roam_info_ptr); #else +static inline void +hdd_send_roam_scan_ch_list_event(struct hdd_context *hdd_ctx, + uint16_t buf_len, uint8_t *buf) +{ + return; +} + static inline int wlan_hdd_send_roam_auth_event(struct hdd_adapter *adapter, uint8_t *bssid, uint8_t *req_rsn_ie, uint32_t req_rsn_length, uint8_t *rsp_rsn_ie, uint32_t rsp_rsn_length, @@ -425,33 +451,25 @@ int wlan_hdd_cfg80211_update_band(struct hdd_context *hdd_ctx, enum band_info eBand); /** - * wlan_hdd_try_disconnect() - try disconnnect from previous connection + * wlan_hdd_cfg80211_indicate_disconnect() - Indicate disconnnect to userspace * @adapter: Pointer to adapter + * @locally_generated: True if the disconnection is internally generated. + * False if the disconnection is received from peer. + * @reason: Disconnect reason as per @enum eSirMacReasonCodes + * @disconnect_ies: IEs received in Deauth/Disassoc from peer + * @disconnect_ies_len: Length of @disconnect_ies * - * This function is used to disconnect from previous connection + * This function is indicate disconnect to the kernel which thus indicates + * to the userspace. * - * Return: 0 for success, non-zero for failure + * Return: None */ -int wlan_hdd_try_disconnect(struct hdd_adapter *adapter); - -#if defined(CFG80211_DISCONNECTED_V2) || \ -(LINUX_VERSION_CODE >= KERNEL_VERSION(4, 2, 0)) -static inline void wlan_hdd_cfg80211_indicate_disconnect(struct net_device *dev, - bool locally_generated, - int reason) -{ - cfg80211_disconnected(dev, reason, NULL, 0, - locally_generated, GFP_KERNEL); -} -#else -static inline void wlan_hdd_cfg80211_indicate_disconnect(struct net_device *dev, - bool locally_generated, - int reason) -{ - cfg80211_disconnected(dev, reason, NULL, 0, - GFP_KERNEL); -} -#endif +void +wlan_hdd_cfg80211_indicate_disconnect(struct hdd_adapter *adapter, + bool locally_generated, + enum eSirMacReasonCodes reason, + uint8_t *disconnect_ies, + uint16_t disconnect_ies_len); /** * wlan_hdd_inform_bss_frame() - inform bss details to NL80211 @@ -528,23 +546,27 @@ uint8_t hdd_get_sap_operating_band(struct hdd_context *hdd_ctx); /** * wlan_hdd_try_disconnect() - try disconnnect from previous connection * @adapter: Pointer to adapter + * @reason: Mac Disconnect reason code as per @enum eSirMacReasonCodes * * This function is used to disconnect from previous connection * * Return: 0 for success, non-zero for failure */ -int wlan_hdd_try_disconnect(struct hdd_adapter *adapter); +int wlan_hdd_try_disconnect(struct hdd_adapter *adapter, + enum eSirMacReasonCodes reason); /** * wlan_hdd_disconnect() - hdd disconnect api * @adapter: Pointer to adapter - * @reason: Disconnect reason code + * @reason: CSR disconnect reason code as per @enum eCsrRoamDisconnectReason + * @mac_reason: Mac Disconnect reason code as per @enum eSirMacReasonCodes * * This function is used to issue a disconnect request to SME * * Return: 0 for success, non-zero for failure */ -int wlan_hdd_disconnect(struct hdd_adapter *adapter, u16 reason); +int wlan_hdd_disconnect(struct hdd_adapter *adapter, u16 reason, + tSirMacReasonCodes mac_reason); /** * hdd_update_cca_info_cb() - stores congestion value in station context @@ -591,6 +613,7 @@ int wlan_hdd_merge_avoid_freqs(struct ch_avoid_ind_type *destFreqList, */ void hdd_bt_activity_cb(hdd_handle_t hdd_handle, uint32_t bt_activity); +#ifdef WLAN_FEATURE_GTK_OFFLOAD /** * wlan_hdd_save_gtk_offload_params() - Save gtk offload parameters in STA * context for offload operations. @@ -604,11 +627,17 @@ void hdd_bt_activity_cb(hdd_handle_t hdd_handle, uint32_t bt_activity); * Return: None */ void wlan_hdd_save_gtk_offload_params(struct hdd_adapter *adapter, - uint8_t *kck_ptr, - uint8_t *kek_ptr, - uint32_t kek_len, - uint8_t *replay_ctr, - bool big_endian); + uint8_t *kck_ptr, uint8_t kck_len, + uint8_t *kek_ptr, uint32_t kek_len, + uint8_t *replay_ctr, bool big_endian); +#else +void wlan_hdd_save_gtk_offload_params(struct hdd_adapter *adapter, + uint8_t *kck_ptr, uint8_t kck_len, + uint8_t *kek_ptr, uint32_t kek_len, + uint8_t *replay_ctr, bool big_endian) +{} +#endif + /* * wlan_hdd_send_mode_change_event() - API to send hw mode change event to * userspace @@ -653,4 +682,109 @@ void hdd_store_sar_config(struct hdd_context *hdd_ctx, * Return: None */ void wlan_hdd_free_sar_config(struct hdd_context *hdd_ctx); + +#ifdef SAR_SAFETY_FEATURE +/** + * wlan_hdd_sar_unsolicited_timer_start() - Start SAR unsolicited timer + * @hdd_ctx: Pointer to HDD context + * + * This function checks the state of the sar unsolicited timer, if the + * sar_unsolicited_timer is not runnig, it starts the timer. + * + * Return: None + */ +void wlan_hdd_sar_unsolicited_timer_start(struct hdd_context *hdd_ctx); + +/** + * wlan_hdd_sar_safety_timer_reset() - Reset SAR sefety timer + * @hdd_ctx: Pointer to HDD context + * + * This function checks the state of the sar safety timer, if the + * sar_safety_timer is not runnig, it starts the timer else it stops + * the timer and start the timer again. + * + * Return: None + */ +void wlan_hdd_sar_timers_reset(struct hdd_context *hdd_ctx); + +/** + * wlan_hdd_sar_timers_init() - Initialize SAR timers + * @hdd_ctx: Pointer to HDD context + * + * This function initializes sar timers. + * Return: None + */ +void wlan_hdd_sar_timers_init(struct hdd_context *hdd_ctx); + +/** + * wlan_hdd_sar_timers_deinit() - De-initialize SAR timers + * @hdd_ctx: Pointer to HDD context + * + * This function de-initializes sar timers. + * Return: None + */ +void wlan_hdd_sar_timers_deinit(struct hdd_context *hdd_ctx); + +/** + * hdd_disable_sar() - Disable SAR feature to FW + * @hdd_ctx: Pointer to HDD context + * + * This function Disables SAR power index on both the chains + * + * Return: None + */ +void hdd_disable_sar(struct hdd_context *hdd_ctx); + +/** + * hdd_configure_sar_sleep_index() - Configure SAR sleep index to FW + * @hdd_ctx: Pointer to HDD context + * + * This function configures SAR sleep index on both the chains + * + * Return: None + */ +void hdd_configure_sar_sleep_index(struct hdd_context *hdd_ctx); + +/** + * hdd_configure_sar_resume_index() - Configure SAR resume index to FW + * @hdd_ctx: Pointer to HDD context + * + * This function configures SAR resume index on both the chains + * + * Return: None + */ +void hdd_configure_sar_resume_index(struct hdd_context *hdd_ctx); + +#else +static inline void wlan_hdd_sar_unsolicited_timer_start( + struct hdd_context *hdd_ctx) +{ +} + +static inline void wlan_hdd_sar_timers_reset(struct hdd_context *hdd_ctx) +{ +} + +static inline void wlan_hdd_sar_timers_init(struct hdd_context *hdd_ctx) +{ +} + +static inline void wlan_hdd_sar_timers_deinit(struct hdd_context *hdd_ctx) +{ +} + +static inline void hdd_disable_sar(struct hdd_context *hdd_ctx) +{ +} + +static inline void hdd_configure_sar_sleep_index(struct hdd_context *hdd_ctx) +{ +} + +static inline void hdd_configure_sar_resume_index(struct hdd_context *hdd_ctx) +{ +} + +#endif + #endif diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_debugfs_connect.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_debugfs_connect.c index 8cbedd2a2670..37274ac8e949 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_debugfs_connect.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_debugfs_connect.c @@ -227,6 +227,10 @@ uint8_t *hdd_auth_type_str(uint32_t auth_type) return "RSN PSK SHA256"; case eCSR_AUTH_TYPE_RSN_8021X_SHA256: return "RSN 8021X SHA256"; + case eCSR_AUTH_TYPE_FT_SAE: + return "FT SAE"; + case eCSR_AUTH_TYPE_FT_SUITEB_EAP_SHA384: + return "FT Suite B SHA384"; case eCSR_NUM_OF_SUPPORT_AUTH_TYPE: return "NUM OF SUPPORT AUTH TYPE"; case eCSR_AUTH_TYPE_FAILED: diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_debugfs_llstat.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_debugfs_llstat.c index eb2ebd62b781..26d9e9b4fbdd 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_debugfs_llstat.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_debugfs_llstat.c @@ -387,7 +387,7 @@ static ssize_t __wlan_hdd_read_ll_stats_debugfs(struct file *file, /* All the events are received and buffer is populated */ ret = hdd_debugfs_stats_update(buf, count, pos); - hdd_info("%zu characters written into debugfs", ret); + hdd_debug("%zu characters written into debugfs", ret); hdd_exit(); return ret; diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_driver_ops.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_driver_ops.c index 57de127373c1..d2779311036d 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_driver_ops.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_driver_ops.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -267,7 +267,7 @@ int hdd_hif_open(struct device *dev, void *bdev, const struct hif_bus_id *bid, ret = hdd_napi_create(); hdd_debug("hdd_napi_create returned: %d", ret); if (ret == 0) - hdd_warn("NAPI: no instances are created"); + hdd_debug("NAPI: no instances are created"); else if (ret < 0) { hdd_err("NAPI creation error, rc: 0x%x, reinit: %d", ret, reinit); @@ -569,7 +569,7 @@ static void hdd_send_hang_reason(void) enum qdf_hang_reason reason = QDF_REASON_UNSPECIFIED; struct hdd_context *hdd_ctx = cds_get_context(QDF_MODULE_ID_HDD); - if (wlan_hdd_validate_context(hdd_ctx)) + if (!hdd_ctx) return; cds_get_recovery_reason(&reason); @@ -902,7 +902,7 @@ static int __wlan_hdd_bus_suspend_noirq(void) int errno; uint32_t pending_events; - hdd_info("start bus_suspend_noirq"); + hdd_debug("start bus_suspend_noirq"); errno = wlan_hdd_validate_context(hdd_ctx); if (errno) { hdd_err("Invalid HDD context: errno %d", errno); @@ -943,7 +943,7 @@ static int __wlan_hdd_bus_suspend_noirq(void) hdd_ctx->suspend_resume_stats.suspends++; - hdd_info("bus_suspend_noirq done"); + hdd_debug("bus_suspend_noirq done"); return 0; resume_hif_noirq: @@ -1079,7 +1079,7 @@ static int __wlan_hdd_bus_resume_noirq(void) int status; QDF_STATUS qdf_status; - hdd_info("starting bus_resume_noirq"); + hdd_debug("starting bus_resume_noirq"); if (cds_is_driver_recovering()) return 0; @@ -1104,7 +1104,7 @@ static int __wlan_hdd_bus_resume_noirq(void) status = hif_bus_resume_noirq(hif_ctx); QDF_BUG(!status); - hdd_info("bus_resume_noirq done"); + hdd_debug("bus_resume_noirq done"); return status; } diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_ext_scan.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_ext_scan.c index adc27971076b..6f52085bc6c0 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_ext_scan.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_ext_scan.c @@ -30,8 +30,7 @@ #include "cds_utils.h" #include "cds_sched.h" #include - -#define EXTSCAN_PARAM_MAX QCA_WLAN_VENDOR_ATTR_EXTSCAN_SUBCMD_CONFIG_PARAM_MAX +#include "wlan_hdd_scan.h" /* amount of time to wait for a synchronous request/response operation */ #define WLAN_WAIT_TIME_EXTSCAN 1000 @@ -57,86 +56,6 @@ struct hdd_ext_scan_context { }; static struct hdd_ext_scan_context ext_scan_context; -static const struct nla_policy wlan_hdd_extscan_config_policy -[QCA_WLAN_VENDOR_ATTR_EXTSCAN_SUBCMD_CONFIG_PARAM_MAX + 1] = { - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_SUBCMD_CONFIG_PARAM_REQUEST_ID] = { - .type = NLA_U32}, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_GET_VALID_CHANNELS_CONFIG_PARAM_WIFI_BAND] = { - .type = NLA_U32}, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_GET_VALID_CHANNELS_CONFIG_PARAM_MAX_CHANNELS] = { - .type = NLA_U32}, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_CHANNEL_SPEC_CHANNEL] = {.type = NLA_U32}, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_CHANNEL_SPEC_DWELL_TIME] = { - .type = NLA_U32}, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_CHANNEL_SPEC_PASSIVE] = {.type = NLA_U8}, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_CHANNEL_SPEC_CLASS] = {.type = NLA_U8}, - - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_BUCKET_SPEC_INDEX] = {.type = NLA_U8}, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_BUCKET_SPEC_BAND] = {.type = NLA_U8}, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_BUCKET_SPEC_PERIOD] = {.type = NLA_U32}, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_BUCKET_SPEC_REPORT_EVENTS] = { - .type = NLA_U8}, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_BUCKET_SPEC_NUM_CHANNEL_SPECS] = { - .type = NLA_U32}, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_SCAN_CMD_PARAMS_BASE_PERIOD] = { - .type = NLA_U32}, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_SCAN_CMD_PARAMS_MAX_AP_PER_SCAN] = { - .type = NLA_U32}, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_SCAN_CMD_PARAMS_REPORT_THRESHOLD_PERCENT] = { - .type = NLA_U8}, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_SCAN_CMD_PARAMS_REPORT_THRESHOLD_NUM_SCANS] = { - .type = NLA_U8 }, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_SCAN_CMD_PARAMS_NUM_BUCKETS] = { - .type = NLA_U8}, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_GET_CACHED_SCAN_RESULTS_CONFIG_PARAM_FLUSH] = { - .type = NLA_U8}, - - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_GET_CACHED_SCAN_RESULTS_CONFIG_PARAM_MAX] = { - .type = NLA_U32}, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_AP_THRESHOLD_PARAM_BSSID] = { - .type = NLA_UNSPEC, - .len = QDF_MAC_ADDR_SIZE}, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_AP_THRESHOLD_PARAM_RSSI_LOW] = { - .type = NLA_S32}, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_AP_THRESHOLD_PARAM_RSSI_HIGH] = { - .type = NLA_S32}, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_AP_THRESHOLD_PARAM_CHANNEL] = { - .type = NLA_U32}, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_BSSID_HOTLIST_PARAMS_NUM_AP] = { - .type = NLA_U32}, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_SIGNIFICANT_CHANGE_PARAMS_RSSI_SAMPLE_SIZE] = { - .type = NLA_U32}, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_SIGNIFICANT_CHANGE_PARAMS_LOST_AP_SAMPLE_SIZE] = { - .type = NLA_U32}, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_SIGNIFICANT_CHANGE_PARAMS_MIN_BREACHING] = { - .type = NLA_U32}, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_SIGNIFICANT_CHANGE_PARAMS_NUM_AP] = { - .type = NLA_U32}, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_BUCKET_SPEC_MAX_PERIOD] = { - .type = NLA_U32}, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_BUCKET_SPEC_BASE] = { - .type = NLA_U32}, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_BUCKET_SPEC_STEP_COUNT] = { - .type = NLA_U32}, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_SSID_THRESHOLD_PARAM_SSID] = { - .type = NLA_BINARY, - .len = IEEE80211_MAX_SSID_LEN + 1 }, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_SSID_HOTLIST_PARAMS_LOST_SSID_SAMPLE_SIZE] = { - .type = NLA_U32 }, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_SSID_HOTLIST_PARAMS_NUM_SSID] = { - .type = NLA_U32 }, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_SSID_THRESHOLD_PARAM_BAND] = { - .type = NLA_U8 }, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_SSID_THRESHOLD_PARAM_RSSI_LOW] = { - .type = NLA_S32 }, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_SSID_THRESHOLD_PARAM_RSSI_HIGH] = { - .type = NLA_S32 }, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_CONFIGURATION_FLAGS] = { - .type = NLA_U32 }, - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_BSSID_HOTLIST_PARAMS_LOST_AP_SAMPLE_SIZE] = { - .type = NLA_U32}, -}; - static const struct nla_policy wlan_hdd_pno_config_policy[QCA_WLAN_VENDOR_ATTR_PNO_MAX + 1] = { [QCA_WLAN_VENDOR_ATTR_PNO_PASSPOINT_LIST_PARAM_NUM] = { @@ -2333,225 +2252,6 @@ int wlan_hdd_cfg80211_extscan_set_significant_change(struct wiphy *wiphy, return ret; } -/** - * hdd_remove_dsrc_channels () - remove dsrc chanels - * @hdd_ctx: hdd context - * @wiphy: Pointer to wireless phy - * @chan_list: channel list - * @num_channels: number of channels - * - * Return: none - */ -static void hdd_remove_dsrc_channels(struct hdd_context *hdd_ctx, - struct wiphy *wiphy, uint32_t *chan_list, - uint8_t *num_channels) -{ - uint8_t num_chan_temp = 0; - int i; - - for (i = 0; i < *num_channels; i++) { - if (!wlan_reg_is_dsrc_chan(hdd_ctx->pdev, - wlan_reg_freq_to_chan( - hdd_ctx->pdev, - chan_list[i]))) { - chan_list[num_chan_temp] = chan_list[i]; - num_chan_temp++; - } - } - *num_channels = num_chan_temp; -} - -/** - * hdd_remove_passive_channels () - remove passive channels - * @wiphy: Pointer to wireless phy - * @chan_list: channel list - * @num_channels: number of channels - * - * Return: none - */ -static void hdd_remove_passive_channels(struct wiphy *wiphy, - uint32_t *chan_list, - uint8_t *num_channels) -{ - uint8_t num_chan_temp = 0; - int i, j, k; - - for (i = 0; i < *num_channels; i++) - for (j = 0; j < HDD_NUM_NL80211_BANDS; j++) { - if (wiphy->bands[j] == NULL) - continue; - for (k = 0; k < wiphy->bands[j]->n_channels; k++) { - if ((chan_list[i] == - wiphy->bands[j]->channels[k].center_freq) - && (!(wiphy->bands[j]->channels[k].flags & - IEEE80211_CHAN_PASSIVE_SCAN)) - ) { - chan_list[num_chan_temp] = chan_list[i]; - num_chan_temp++; - } - } - } - - *num_channels = num_chan_temp; -} - -/** - * __wlan_hdd_cfg80211_extscan_get_valid_channels () - get valid channels - * @wiphy: Pointer to wireless phy - * @wdev: Pointer to wireless device - * @data: Pointer to data - * @data_len: Data length - * - * Return: none - */ -static int -__wlan_hdd_cfg80211_extscan_get_valid_channels(struct wiphy *wiphy, - struct wireless_dev - *wdev, const void *data, - int data_len) -{ - struct hdd_context *hdd_ctx = wiphy_priv(wiphy); - struct net_device *dev = wdev->netdev; - struct hdd_adapter *adapter = WLAN_HDD_GET_PRIV_PTR(dev); - uint32_t chan_list[WNI_CFG_VALID_CHANNEL_LIST_LEN] = {0}; - uint8_t num_channels = 0, i, buf[256] = {0}; - struct nlattr *tb[QCA_WLAN_VENDOR_ATTR_EXTSCAN_SUBCMD_CONFIG_PARAM_MAX + - 1]; - uint32_t requestId, maxChannels; - tWifiBand wifiBand; - QDF_STATUS status; - struct sk_buff *reply_skb; - int ret, len = 0; - - /* ENTER_DEV() intentionally not used in a frequently invoked API */ - - if (QDF_GLOBAL_FTM_MODE == hdd_get_conparam()) { - hdd_err("Command not allowed in FTM mode"); - return -EPERM; - } - - ret = wlan_hdd_validate_context(hdd_ctx); - if (0 != ret) - return -EINVAL; - - if (!hdd_ctx->config->extscan_enabled) { - hdd_err("extscan not supported"); - return -ENOTSUPP; - } - if (wlan_cfg80211_nla_parse(tb, - QCA_WLAN_VENDOR_ATTR_EXTSCAN_SUBCMD_CONFIG_PARAM_MAX, - data, data_len, wlan_hdd_extscan_config_policy)) { - hdd_err("Invalid ATTR"); - return -EINVAL; - } - - /* Parse and fetch request Id */ - if (!tb[QCA_WLAN_VENDOR_ATTR_EXTSCAN_SUBCMD_CONFIG_PARAM_REQUEST_ID]) { - hdd_err("attr request id failed"); - return -EINVAL; - } - requestId = - nla_get_u32(tb - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_SUBCMD_CONFIG_PARAM_REQUEST_ID]); - - /* Parse and fetch wifi band */ - if (!tb - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_GET_VALID_CHANNELS_CONFIG_PARAM_WIFI_BAND]) { - hdd_err("attr wifi band failed"); - return -EINVAL; - } - wifiBand = - nla_get_u32(tb - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_GET_VALID_CHANNELS_CONFIG_PARAM_WIFI_BAND]); - - if (!tb - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_GET_VALID_CHANNELS_CONFIG_PARAM_MAX_CHANNELS]) { - hdd_err("attr max channels failed"); - return -EINVAL; - } - maxChannels = - nla_get_u32(tb - [QCA_WLAN_VENDOR_ATTR_EXTSCAN_GET_VALID_CHANNELS_CONFIG_PARAM_MAX_CHANNELS]); - - if (maxChannels > WNI_CFG_VALID_CHANNEL_LIST_LEN) { - hdd_err("Max channels %d exceeded Valid channel list len %d", - maxChannels, WNI_CFG_VALID_CHANNEL_LIST_LEN); - return -EINVAL; - } - - hdd_debug("Req Id: %u Wifi band: %d Max channels: %d", requestId, - wifiBand, maxChannels); - status = sme_get_valid_channels_by_band(hdd_ctx->mac_handle, - wifiBand, chan_list, - &num_channels); - if (QDF_STATUS_SUCCESS != status) { - hdd_err("sme_get_valid_channels_by_band failed (err=%d)", - status); - return -EINVAL; - } - - num_channels = QDF_MIN(num_channels, maxChannels); - - hdd_remove_dsrc_channels(hdd_ctx, wiphy, chan_list, &num_channels); - if ((QDF_SAP_MODE == adapter->device_mode) || - !strncmp(hdd_get_fwpath(), "ap", 2)) - hdd_remove_passive_channels(wiphy, chan_list, - &num_channels); - - hdd_debug("Number of channels: %d", num_channels); - for (i = 0; i < num_channels; i++) - len += scnprintf(buf + len, sizeof(buf) - len, - "%u ", chan_list[i]); - - hdd_debug("Channels: %s", buf); - - reply_skb = cfg80211_vendor_cmd_alloc_reply_skb(wiphy, sizeof(u32) + - sizeof(u32) * - num_channels + - NLMSG_HDRLEN); - - if (reply_skb) { - if (nla_put_u32(reply_skb, - QCA_WLAN_VENDOR_ATTR_EXTSCAN_RESULTS_NUM_CHANNELS, - num_channels) || - nla_put(reply_skb, - QCA_WLAN_VENDOR_ATTR_EXTSCAN_RESULTS_CHANNELS, - sizeof(u32) * num_channels, chan_list)) { - hdd_err("nla put fail"); - kfree_skb(reply_skb); - return -EINVAL; - } - ret = cfg80211_vendor_cmd_reply(reply_skb); - return ret; - } - - hdd_err("valid channels: buffer alloc fail"); - return -EINVAL; -} - -/** - * wlan_hdd_cfg80211_extscan_get_valid_channels() - get ext scan valid channels - * @wiphy: Pointer to wireless phy - * @wdev: Pointer to wireless device - * @data: Pointer to data - * @data_len: Data length - * - * Return: 0 on success, negative errno on failure - */ -int wlan_hdd_cfg80211_extscan_get_valid_channels(struct wiphy *wiphy, - struct wireless_dev *wdev, - const void *data, int data_len) -{ - int ret = 0; - - cds_ssr_protect(__func__); - ret = __wlan_hdd_cfg80211_extscan_get_valid_channels(wiphy, wdev, data, - data_len); - cds_ssr_unprotect(__func__); - - return ret; -} - /** * hdd_extscan_update_dwell_time_limits() - update dwell times * @req_msg: Pointer to request message diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_ext_scan.h b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_ext_scan.h index 3c98fe213e92..5268bbe27b47 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_ext_scan.h +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_ext_scan.h @@ -49,11 +49,6 @@ int wlan_hdd_cfg80211_extscan_stop(struct wiphy *wiphy, struct wireless_dev *wdev, const void *data, int data_len); -int wlan_hdd_cfg80211_extscan_get_valid_channels(struct wiphy *wiphy, - struct wireless_dev - *wdev, const void *data, - int data_len); - int wlan_hdd_cfg80211_extscan_get_capabilities(struct wiphy *wiphy, struct wireless_dev *wdev, const void *data, int data_len); diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_ftm.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_ftm.c index 9fc02984e560..368ad2c8795a 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_ftm.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_ftm.c @@ -77,6 +77,7 @@ int hdd_update_cds_config_ftm(struct hdd_context *hdd_ctx) hdd_ctx->config->enablePowersaveOffload; hdd_lpass_populate_cds_config(cds_cfg, hdd_ctx); cds_cfg->sub_20_channel_width = WLAN_SUB_20_CH_WIDTH_NONE; + cds_cfg->num_vdevs = hdd_ctx->config->num_vdevs; cds_init_ini_config(cds_cfg); return 0; diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_ftm_time_sync.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_ftm_time_sync.c new file mode 100644 index 000000000000..a60b871895dc --- /dev/null +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_ftm_time_sync.c @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include "wlan_hdd_ftm_time_sync.h" +#include "ftm_time_sync_ucfg_api.h" + +static ssize_t hdd_ftm_time_sync_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct hdd_station_ctx *hdd_sta_ctx; + struct hdd_adapter *adapter; + ssize_t size = 0; + + struct net_device *net_dev = qdf_container_of(dev, struct net_device, + dev); + + adapter = (struct hdd_adapter *)(netdev_priv(net_dev)); + if (adapter->magic != WLAN_HDD_ADAPTER_MAGIC) + return scnprintf(buf, PAGE_SIZE, "Invalid device\n"); + + hdd_sta_ctx = WLAN_HDD_GET_STATION_CTX_PTR(adapter); + if (adapter->device_mode == QDF_STA_MODE) + return ucfg_ftm_time_sync_show(adapter->vdev, buf); + + return size; +} + +static DEVICE_ATTR(ftm_time_sync, 0400, hdd_ftm_time_sync_show, NULL); + +void +hdd_ftm_time_sync_sta_state_notify(struct hdd_adapter *adapter, + enum ftm_time_sync_sta_state state) +{ + struct hdd_station_ctx *hdd_sta_ctx; + struct wlan_objmgr_psoc *psoc; + struct net_device *net_dev; + + psoc = wlan_vdev_get_psoc(adapter->vdev); + if (!psoc) + return; + + if (!ucfg_is_ftm_time_sync_enable(psoc)) + return; + + net_dev = adapter->dev; + + if (net_dev) { + if (state == FTM_TIME_SYNC_STA_CONNECTED) + device_create_file(&net_dev->dev, + &dev_attr_ftm_time_sync); + else + device_remove_file(&net_dev->dev, + &dev_attr_ftm_time_sync); + } + + hdd_sta_ctx = WLAN_HDD_GET_STATION_CTX_PTR(adapter); + ucfg_ftm_time_sync_update_sta_connect_state( + adapter->vdev, state, + hdd_sta_ctx->conn_info.bssId); +} diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_green_ap.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_green_ap.c index df5b332ae7af..77a149cd136f 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_green_ap.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_green_ap.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -49,14 +49,14 @@ static int hdd_green_ap_check_enable(struct hdd_context *hdd_ctx, status = policy_mgr_mode_specific_num_active_sessions( hdd_ctx->psoc, mode, &num_sessions); - hdd_debug("No. of active sessions for mode: %d is %d", - mode, num_sessions); if (status != QDF_STATUS_SUCCESS) { hdd_err("Failed to get num sessions for mode: %d", mode); return -EINVAL; } else if (num_sessions) { *enable_green_ap = false; + hdd_debug("active sessions for mode: %d is %d disable green AP", + mode, num_sessions); return 0; } } diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_hostapd.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_hostapd.c index 23198f222f45..b808e51fc8ab 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_hostapd.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_hostapd.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -87,6 +87,7 @@ #include #include #include "wlan_action_oui_ucfg_api.h" +#include "ftm_time_sync_ucfg_api.h" #define IS_UP(_dev) \ (((_dev)->flags & (IFF_RUNNING|IFF_UP)) == (IFF_RUNNING|IFF_UP)) @@ -107,12 +108,15 @@ #define SAP_24GHZ_CH_COUNT (14) #define ACS_SCAN_EXPIRY_TIMEOUT_S 4 -/* Defines the BIT position of HT caps is support mode field of stainfo */ -#define HDD_HT_CAPS_PRESENT 0 -/* Defines the BIT position of VHT caps is support mode field of stainfo */ -#define HDD_VHT_CAPS_PRESENT 1 -/* Defines the BIT position of HE caps is support mode field of stainfo */ -#define HDD_HE_CAPS_PRESENT 2 +/* + * Defines the BIT position of 11bg/11abg/11abgn 802.11 support mode field + * of stainfo + */ +#define HDD_80211_MODE_ABGN 0 +/* Defines the BIT position of 11ac support mode field of stainfo */ +#define HDD_80211_MODE_AC 1 +/* Defines the BIT position of 11ax support mode field of stainfo */ +#define HDD_80211_MODE_AX 2 /* * 11B, 11G Rate table include Basic rate and Extended rate @@ -719,7 +723,7 @@ static int __hdd_hostapd_set_mac_address(struct net_device *dev, void *addr) return -EINVAL; } - hdd_info("Changing MAC to " MAC_ADDRESS_STR " of interface %s ", + hdd_debug("Changing MAC to " MAC_ADDRESS_STR " of interface %s ", MAC_ADDR_ARRAY(mac_addr.bytes), dev->name); hdd_update_dynamic_mac(hdd_ctx, &adapter->mac_addr, &mac_addr); @@ -838,18 +842,12 @@ QDF_STATUS hdd_chan_change_notify(struct hdd_adapter *adapter, return QDF_STATUS_E_FAILURE; } - hdd_debug("chan:%d width:%d sec_ch_offset:%d seg0:%d seg1:%d", - chan_change.chan, chan_change.chan_params.ch_width, - chan_change.chan_params.sec_ch_offset, - chan_change.chan_params.center_freq_seg0, - chan_change.chan_params.center_freq_seg1); - freq = cds_chan_to_freq(chan_change.chan); - chan = ieee80211_get_channel(adapter->wdev.wiphy, freq); if (!chan) { - hdd_err("Invalid input frequency for channel conversion"); + hdd_err("Invalid input frequency %d for channel conversion", + freq); return QDF_STATUS_E_FAILURE; } @@ -1275,7 +1273,7 @@ static int get_max_rate_vht(int nss, int ch_width, int sgi, int vht_mcs_map) supported_vht_mcs_rate = supported_vht_mcs_rate_nss2; } else { /* Not Supported */ - hdd_err("nss %d not supported", nss); + hdd_debug("nss %d not supported", nss); return maxrate; } @@ -1456,6 +1454,7 @@ static void hdd_fill_station_info(struct hdd_adapter *adapter, struct hdd_station_info *stainfo; uint8_t i = 0, oldest_disassoc_sta_idx = WLAN_MAX_STA_COUNT + 1; qdf_time_t oldest_disassoc_sta_ts = 0; + bool is_dot11_mode_abgn; if (event->staId >= WLAN_MAX_STA_COUNT) { hdd_err("invalid sta id"); @@ -1502,20 +1501,27 @@ static void hdd_fill_station_info(struct hdd_adapter *adapter, /* expect max_phy_rate report in kbps */ stainfo->max_phy_rate *= 100; + /* + * Connected Peer always supports atleast one of the + * 802.11 mode out of 11bg/11abg/11abgn, hence this field + * should always be true. + */ + is_dot11_mode_abgn = true; + stainfo->support_mode |= is_dot11_mode_abgn << HDD_80211_MODE_ABGN; + if (event->vht_caps.present) { stainfo->vht_present = true; hdd_copy_vht_caps(&stainfo->vht_caps, &event->vht_caps); stainfo->support_mode |= - (stainfo->vht_present << HDD_VHT_CAPS_PRESENT); + (stainfo->vht_present << HDD_80211_MODE_AC); } if (event->ht_caps.present) { stainfo->ht_present = true; hdd_copy_ht_caps(&stainfo->ht_caps, &event->ht_caps); - stainfo->support_mode |= - (stainfo->ht_present << HDD_HT_CAPS_PRESENT); } + stainfo->support_mode |= - (event->he_caps_present << HDD_HE_CAPS_PRESENT); + (event->he_caps_present << HDD_80211_MODE_AX); /* Initialize DHCP info */ stainfo->dhcp_phase = DHCP_PHASE_ACK; @@ -1554,11 +1560,25 @@ static void hdd_fill_station_info(struct hdd_adapter *adapter, i = oldest_disassoc_sta_idx; } if (i < WLAN_MAX_STA_COUNT) { + if (adapter->cache_sta_info[i].assoc_req_ies.data) { + qdf_mem_free( + adapter->cache_sta_info[i].assoc_req_ies.data); + adapter->cache_sta_info[i].assoc_req_ies.data = NULL; + adapter->cache_sta_info[i].assoc_req_ies.len = 0; + } qdf_mem_zero(&adapter->cache_sta_info[i], sizeof(*stainfo)); qdf_mem_copy(&adapter->cache_sta_info[i], stainfo, sizeof(struct hdd_station_info)); - + adapter->cache_sta_info[i].assoc_req_ies.data = + qdf_mem_malloc(event->ies_len); + if (adapter->cache_sta_info[i].assoc_req_ies.data) { + qdf_mem_copy( + adapter->cache_sta_info[i].assoc_req_ies.data, + event->ies, event->ies_len); + adapter->cache_sta_info[i].assoc_req_ies.len = + event->ies_len; + } } else { hdd_debug("reached max staid, stainfo can't be cached"); } @@ -1583,25 +1603,7 @@ static void hdd_fill_station_info(struct hdd_adapter *adapter, stainfo->tx_mcs_map); } -/** - * hdd_stop_sap_due_to_invalid_channel() - to stop sap in case of invalid chnl - * @work: pointer to work structure - * - * Let's say SAP detected RADAR and trying to select the new channel and if no - * valid channel is found due to none of the channels are available or - * regulatory restriction then SAP needs to be stopped. so SAP state-machine - * will create a work to stop the bss - * - * stop bss has to happen through worker thread because radar indication comes - * from FW through mc thread or main host thread and if same thread is used to - * do stopbss then waiting for stopbss to finish operation will halt mc thread - * to freeze which will trigger stopbss timeout. Instead worker thread can do - * the stopbss operation while mc thread waits for stopbss to finish. - * - * Return: none - */ -static void -hdd_stop_sap_due_to_invalid_channel(struct work_struct *work) +void hdd_stop_sap_due_to_invalid_channel(struct work_struct *work) { /* * Extract the adapter from work structure. sap_stop_bss_work @@ -1786,6 +1788,11 @@ QDF_STATUS hdd_hostapd_sap_event_cb(tpSap_Event pSapEvent, sap_config->ch_params.ch_width = pSapEvent->sapevt.sapStartBssCompleteEvent.ch_width; + hdd_nofl_info("AP started vid %d chan %d BW %d", + adapter->session_id, + ap_ctx->operating_channel, + sap_config->ch_params.ch_width); + sap_config->ch_params = ap_ctx->sap_context->ch_params; sap_config->sec_ch = ap_ctx->sap_context->secondary_ch; @@ -1801,6 +1808,9 @@ QDF_STATUS hdd_hostapd_sap_event_cb(tpSap_Event pSapEvent, goto stopbss; } wlansap_get_dfs_ignore_cac(mac_handle, &ignoreCAC); + if (!policy_mgr_get_dfs_master_dynamic_enabled( + hdd_ctx->psoc, adapter->session_id)) + ignoreCAC = true; /* DFS requirement: DO NOT transmit during CAC. */ if (CHANNEL_STATE_DFS != @@ -1955,7 +1965,8 @@ QDF_STATUS hdd_hostapd_sap_event_cb(tpSap_Event pSapEvent, ap_ctx->dfs_cac_block_tx = true; hdd_ctx->dev_dfs_cac_status = DFS_CAC_NEVER_DONE; } - hdd_debug("bss_stop_reason=%d", ap_ctx->bss_stop_reason); + hdd_nofl_info("Ap stopped vid %d reason=%d", + adapter->session_id, ap_ctx->bss_stop_reason); if ((BSS_STOP_DUE_TO_MCC_SCC_SWITCH != ap_ctx->bss_stop_reason) && (BSS_STOP_DUE_TO_VENDOR_CONFIG_CHAN != @@ -2218,26 +2229,13 @@ QDF_STATUS hdd_hostapd_sap_event_cb(tpSap_Event pSapEvent, QDF_TRACE_DEFAULT_PDEV_ID, QDF_PROTO_TYPE_MGMT, QDF_PROTO_MGMT_ASSOC)); -#ifdef MSM_PLATFORM /* start timer in sap/p2p_go */ if (ap_ctx->ap_active == false) { - spin_lock_bh(&hdd_ctx->bus_bw_lock); - adapter->prev_tx_packets = - adapter->stats.tx_packets; - adapter->prev_rx_packets = - adapter->stats.rx_packets; - - cdp_get_intra_bss_fwd_pkts_count( - cds_get_context(QDF_MODULE_ID_SOC), - adapter->session_id, - &adapter->prev_fwd_tx_packets, - &adapter->prev_fwd_rx_packets); - - spin_unlock_bh(&hdd_ctx->bus_bw_lock); + hdd_bus_bw_compute_prev_txrx_stats(adapter); hdd_bus_bw_compute_timer_start(hdd_ctx); } -#endif ap_ctx->ap_active = true; + #ifdef FEATURE_WLAN_AUTO_SHUTDOWN wlan_hdd_auto_shutdown_enable(hdd_ctx, false); #endif @@ -2248,32 +2246,28 @@ QDF_STATUS hdd_hostapd_sap_event_cb(tpSap_Event pSapEvent, HDD_SAP_WAKE_LOCK_DURATION); { struct station_info *sta_info; - uint16_t iesLen = event->iesLen; + uint32_t ies_len = event->ies_len; sta_info = qdf_mem_malloc(sizeof(*sta_info)); if (!sta_info) { hdd_err("Failed to allocate station info"); return QDF_STATUS_E_FAILURE; } - if (iesLen <= MAX_ASSOC_IND_IE_LEN) { - sta_info->assoc_req_ies = - (const u8 *)&event->ies[0]; - sta_info->assoc_req_ies_len = iesLen; + + sta_info->assoc_req_ies = event->ies; + sta_info->assoc_req_ies_len = ies_len; #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 0, 0)) && !defined(WITH_BACKPORTS) - /* - * After Kernel 4.0, it's no longer need to set - * STATION_INFO_ASSOC_REQ_IES flag, as it - * changed to use assoc_req_ies_len length to - * check the existence of request IE. - */ - sta_info->filled |= STATION_INFO_ASSOC_REQ_IES; + /* + * After Kernel 4.0, it's no longer need to set + * STATION_INFO_ASSOC_REQ_IES flag, as it + * changed to use assoc_req_ies_len length to + * check the existence of request IE. + */ + sta_info->filled |= STATION_INFO_ASSOC_REQ_IES; #endif - cfg80211_new_sta(dev, - (const u8 *)&event->staMac.bytes[0], - sta_info, GFP_KERNEL); - } else { - hdd_err("Assoc Ie length is too long"); - } + cfg80211_new_sta(dev, + (const u8 *)&event->staMac.bytes[0], + sta_info, GFP_KERNEL); qdf_mem_free(sta_info); } @@ -2318,9 +2312,14 @@ QDF_STATUS hdd_hostapd_sap_event_cb(tpSap_Event pSapEvent, cache_stainfo->rx_rate = disassoc_comp->rx_rate; cache_stainfo->reason_code = disassoc_comp->reason_code; cache_stainfo->disassoc_ts = qdf_system_ticks(); + hdd_debug("Cache_stainfo rssi %d txrate %d rxrate %d reason_code %d", + cache_stainfo->rssi, + cache_stainfo->tx_rate, + cache_stainfo->rx_rate, + cache_stainfo->reason_code); } - hdd_info(" disassociated " MAC_ADDRESS_STR, - MAC_ADDR_ARRAY(wrqu.addr.sa_data)); + hdd_nofl_info("SAP disassociated " MAC_ADDRESS_STR, + MAC_ADDR_ARRAY(wrqu.addr.sa_data)); qdf_status = qdf_event_set(&hostapd_state->qdf_sta_disassoc_event); if (!QDF_IS_STATUS_SUCCESS(qdf_status)) @@ -2382,10 +2381,20 @@ QDF_STATUS hdd_hostapd_sap_event_cb(tpSap_Event pSapEvent, WIFI_POWER_EVENT_WAKELOCK_SAP); qdf_wake_lock_timeout_acquire(&hdd_ctx->sap_wake_lock, HDD_SAP_CLIENT_DISCONNECT_WAKE_LOCK_DURATION); - cfg80211_del_sta(dev, - (const u8 *)&pSapEvent->sapevt. - sapStationDisassocCompleteEvent.staMac. - bytes[0], GFP_KERNEL); + + /* + * Don't indicate delete station event if P2P GO and + * SSR in progress. Since supplicant will change mode + * fail and down during this time. + */ + if ((adapter->device_mode != QDF_P2P_GO_MODE) || + (!cds_is_driver_recovering())) { + cfg80211_del_sta(dev, + (const u8 *)&pSapEvent->sapevt. + sapStationDisassocCompleteEvent.staMac. + bytes[0], GFP_KERNEL); + hdd_debug("indicate sta deletion event"); + } /* Update the beacon Interval if it is P2P GO */ qdf_status = policy_mgr_change_mcc_go_beacon_interval( @@ -2405,18 +2414,13 @@ QDF_STATUS hdd_hostapd_sap_event_cb(tpSap_Event pSapEvent, NULL, adapter->device_mode); } -#ifdef MSM_PLATFORM + /*stop timer in sap/p2p_go */ if (ap_ctx->ap_active == false) { - spin_lock_bh(&hdd_ctx->bus_bw_lock); - adapter->prev_tx_packets = 0; - adapter->prev_rx_packets = 0; - adapter->prev_fwd_tx_packets = 0; - adapter->prev_fwd_rx_packets = 0; - spin_unlock_bh(&hdd_ctx->bus_bw_lock); + hdd_bus_bw_compute_reset_prev_txrx_stats(adapter); hdd_bus_bw_compute_timer_try_stop(hdd_ctx); } -#endif + hdd_green_ap_del_sta(hdd_ctx); break; @@ -2492,7 +2496,6 @@ QDF_STATUS hdd_hostapd_sap_event_cb(tpSap_Event pSapEvent, return QDF_STATUS_SUCCESS; case eSAP_CHANNEL_CHANGE_EVENT: - hdd_debug("Received eSAP_CHANNEL_CHANGE_EVENT event"); if (hostapd_state->bss_state != BSS_STOP) { /* Prevent suspend for new channel */ hdd_hostapd_channel_prevent_suspend(adapter, @@ -2565,8 +2568,6 @@ QDF_STATUS hdd_hostapd_sap_event_cb(tpSap_Event pSapEvent, return hdd_handle_acs_scan_event(pSapEvent, adapter); case eSAP_ACS_CHANNEL_SELECTED: - hdd_debug("ACS Completed for wlan%d", - adapter->dev->ifindex); clear_bit(ACS_PENDING, &adapter->event_flags); clear_bit(ACS_IN_PROGRESS, &hdd_ctx->g_event_flags); ap_ctx->sap_config.acs_cfg.pri_ch = @@ -2579,8 +2580,14 @@ QDF_STATUS hdd_hostapd_sap_event_cb(tpSap_Event pSapEvent, pSapEvent->sapevt.sap_ch_selected.vht_seg1_center_ch; ap_ctx->sap_config.acs_cfg.ch_width = pSapEvent->sapevt.sap_ch_selected.ch_width; + hdd_nofl_info("ACS Completed vid %d chan %d BW %d", + adapter->session_id, + ap_ctx->sap_config.acs_cfg.pri_ch, + ap_ctx->sap_config.acs_cfg.ch_width); + wlan_hdd_cfg80211_acs_ch_select_evt(adapter); qdf_atomic_set(&adapter->session.ap.acs_in_progress, 0); + qdf_event_set(&adapter->acs_complete_event); return QDF_STATUS_SUCCESS; case eSAP_ECSA_CHANGE_CHAN_IND: hdd_debug("Channel change indication from peer for channel %d", @@ -2603,8 +2610,6 @@ QDF_STATUS hdd_hostapd_sap_event_cb(tpSap_Event pSapEvent, case eSAP_STOP_BSS_DUE_TO_NO_CHNL: hdd_debug("Stop sap session[%d]", adapter->session_id); - INIT_WORK(&adapter->sap_stop_bss_work, - hdd_stop_sap_due_to_invalid_channel); schedule_work(&adapter->sap_stop_bss_work); return QDF_STATUS_SUCCESS; @@ -2661,8 +2666,8 @@ QDF_STATUS hdd_hostapd_sap_event_cb(tpSap_Event pSapEvent, /* reclaim all resources allocated to the BSS */ qdf_status = hdd_softap_stop_bss(adapter); if (!QDF_IS_STATUS_SUCCESS(qdf_status)) { - hdd_warn("hdd_softap_stop_bss failed %d", - qdf_status); + hdd_debug("hdd_softap_stop_bss failed %d", + qdf_status); if (ucfg_ipa_is_enabled()) { ucfg_ipa_uc_disconnect_ap(hdd_ctx->pdev, adapter->dev); @@ -3136,7 +3141,7 @@ QDF_STATUS wlan_hdd_get_channel_for_sap_restart( * Need to take care of 3 port cases with 2 STA iface in future. */ intf_ch = wlansap_check_cc_intf(hdd_ap_ctx->sap_context); - hdd_info("intf_ch: %d", intf_ch); + hdd_debug("intf_ch: %d", intf_ch); if (QDF_MCC_TO_SCC_SWITCH_FORCE_PREFERRED_WITHOUT_DISCONNECTION != hdd_ctx->config->WlanMccToSccSwitchMode) { if (QDF_IS_STATUS_ERROR( @@ -3157,8 +3162,8 @@ QDF_STATUS wlan_hdd_get_channel_for_sap_restart( return QDF_STATUS_E_FAILURE; } - hdd_info("SAP restart orig chan: %d, new chan: %d", - hdd_ap_ctx->sap_config.channel, intf_ch); + hdd_debug("SAP restart orig chan: %d, new chan: %d", + hdd_ap_ctx->sap_config.channel, intf_ch); ch_params.ch_width = CH_WIDTH_MAX; hdd_ap_ctx->bss_stop_reason = BSS_STOP_DUE_TO_MCC_SCC_SWITCH; if (hdd_ap_ctx->sap_context) @@ -3174,7 +3179,7 @@ QDF_STATUS wlan_hdd_get_channel_for_sap_restart( *channel = intf_ch; - hdd_info("SAP channel change with CSA/ECSA"); + hdd_debug("SAP channel change with CSA/ECSA"); hdd_sap_restart_chan_switch_cb(psoc, vdev_id, intf_ch, ch_params.ch_width, false); @@ -6360,7 +6365,7 @@ QDF_STATUS hdd_init_ap_mode(struct hdd_adapter *adapter, bool reinit) hdd_enter(); - hdd_info("SSR in progress: %d", reinit); + hdd_debug("SSR in progress: %d", reinit); qdf_atomic_init(&adapter->session.ap.acs_in_progress); sapContext = hdd_hostapd_init_sap_session(adapter, reinit); @@ -7387,7 +7392,7 @@ static void wlan_hdd_set_sap_hwmode(struct hdd_adapter *adapter) wlan_hdd_check_11ax_support(pBeacon, pConfig); - hdd_info("SAP hw_mode: %d", pConfig->SapHw_mode); + hdd_debug("SAP hw_mode: %d", pConfig->SapHw_mode); } /** @@ -7613,8 +7618,9 @@ static int wlan_hdd_setup_driver_overrides(struct hdd_adapter *ap_adapter) return 0; } -void hdd_check_and_disconnect_sta_on_invalid_channel( - struct hdd_context *hdd_ctx) +void +hdd_check_and_disconnect_sta_on_invalid_channel(struct hdd_context *hdd_ctx, + tSirMacReasonCodes reason) { struct hdd_adapter *sta_adapter; uint8_t sta_chan; @@ -7642,7 +7648,7 @@ void hdd_check_and_disconnect_sta_on_invalid_channel( hdd_err("chan %d not valid, issue disconnect", sta_chan); /* Issue Disconnect request */ - wlan_hdd_disconnect(sta_adapter, eCSR_DISCONNECT_REASON_DEAUTH); + wlan_hdd_disconnect(sta_adapter, eCSR_DISCONNECT_REASON_DEAUTH, reason); } #ifdef DISABLE_CHANNEL_LIST @@ -7701,7 +7707,7 @@ int wlan_hdd_restore_channels(struct hdd_context *hdd_ctx, if (!cache_chann || !cache_chann->num_channels) { qdf_mutex_release(&hdd_ctx->cache_channel_lock); - hdd_err("channel list is NULL or num channels are zero"); + hdd_nofl_debug("channel list is NULL or num channels are zero"); return -EINVAL; } @@ -7737,8 +7743,13 @@ int wlan_hdd_restore_channels(struct hdd_context *hdd_ctx, status = sme_update_channel_list(hdd_ctx->mac_handle); if (status) hdd_err("Can't Restore channel list"); + else + /* + * Free the cache channels when the + * disabled channels are restored + */ + wlan_hdd_free_cache_channels(hdd_ctx); hdd_exit(); - return 0; } @@ -7768,7 +7779,7 @@ int wlan_hdd_disable_channels(struct hdd_context *hdd_ctx) if (!cache_chann || !cache_chann->num_channels) { qdf_mutex_release(&hdd_ctx->cache_channel_lock); - hdd_err("channel list is NULL or num channels are zero"); + hdd_nofl_debug("channel list is NULL or num channels are zero"); return -EINVAL; } @@ -7851,7 +7862,7 @@ int wlan_hdd_cfg80211_start_bss(struct hdd_adapter *adapter, struct hdd_hostapd_state *hostapd_state; mac_handle_t mac_handle; int32_t i; - struct hdd_config *iniConfig; + struct hdd_config *iniConfig = NULL; struct hdd_context *hdd_ctx = WLAN_HDD_GET_CTX(adapter); tSmeConfigParams *sme_config; bool MFPCapable = false; @@ -7943,7 +7954,8 @@ int wlan_hdd_cfg80211_start_bss(struct hdd_adapter *adapter, /* check if STA is on indoor channel*/ if (policy_mgr_is_force_scc(hdd_ctx->psoc)) hdd_check_and_disconnect_sta_on_invalid_channel( - hdd_ctx); + hdd_ctx, + eSIR_MAC_OPER_CHANNEL_DISABLED_INDOOR); } pBeacon = adapter->session.ap.beacon; @@ -8060,10 +8072,7 @@ int wlan_hdd_cfg80211_start_bss(struct hdd_adapter *adapter, goto error; } - if (iniConfig->ignoreCAC || - ((iniConfig->WlanMccToSccSwitchMode != - QDF_MCC_TO_SCC_SWITCH_DISABLE) && - iniConfig->sta_sap_scc_on_dfs_chan)) + if (iniConfig->ignoreCAC) ignore_cac = 1; wlansap_set_dfs_ignore_cac(mac_handle, ignore_cac); @@ -8524,6 +8533,9 @@ int wlan_hdd_cfg80211_start_bss(struct hdd_adapter *adapter, /* Check and restart SAP if it is on unsafe channel */ hdd_unsafe_channel_restart_sap(hdd_ctx); + ucfg_ftm_time_sync_update_bss_state(adapter->vdev, + FTM_TIME_SYNC_BSS_STARTED); + hdd_set_connection_in_progress(false); ret = 0; @@ -8542,8 +8554,13 @@ int wlan_hdd_cfg80211_start_bss(struct hdd_adapter *adapter, wlansap_reset_sap_config_add_ie(pConfig, eUPDATE_IE_ALL); free: - /* Enable Roaming after start bss in case of failure/success */ - wlan_hdd_enable_roaming(adapter); + if (iniConfig && iniConfig->p2p_disable_roam && + (adapter->device_mode == QDF_P2P_GO_MODE)) { + hdd_debug("p2p go mode, keep disable roam"); + } else { + /* Enable Roaming after start bss in case of failure/success */ + wlan_hdd_enable_roaming(adapter); + } qdf_mem_free(sme_config); return ret; } @@ -8692,6 +8709,7 @@ static int __wlan_hdd_cfg80211_stop_ap(struct wiphy *wiphy, if (!QDF_IS_STATUS_SUCCESS(qdf_status)) { hdd_err("qdf wait for single_event failed!!"); + hdd_sap_indicate_disconnect_for_sta(adapter); QDF_ASSERT(0); } } @@ -8709,6 +8727,12 @@ static int __wlan_hdd_cfg80211_stop_ap(struct wiphy *wiphy, hdd_green_ap_start_state_mc(hdd_ctx, adapter->device_mode, false); + if (hdd_ctx->config->p2p_disable_roam && + (adapter->device_mode == QDF_P2P_GO_MODE)) { + hdd_debug("p2p go disconnected enable roam"); + wlan_hdd_enable_roaming(adapter); + } + if (adapter->session.ap.beacon) { qdf_mem_free(adapter->session.ap.beacon); adapter->session.ap.beacon = NULL; @@ -8752,6 +8776,8 @@ static int __wlan_hdd_cfg80211_stop_ap(struct wiphy *wiphy, hdd_destroy_acs_timer(adapter); ucfg_p2p_status_stop_bss(adapter->vdev); + ucfg_ftm_time_sync_update_bss_state(adapter->vdev, + FTM_TIME_SYNC_BSS_STOPPED); hdd_exit(); @@ -8938,6 +8964,7 @@ static int __wlan_hdd_cfg80211_start_ap(struct wiphy *wiphy, adapter, hdd_device_mode_to_string(adapter->device_mode), adapter->device_mode, cds_is_sub_20_mhz_enabled()); + hdd_nofl_info("Request to start AP vid %d", adapter->session_id); if (policy_mgr_is_hw_mode_change_in_progress(hdd_ctx->psoc)) { status = policy_mgr_wait_for_connection_update( hdd_ctx->psoc); @@ -8990,11 +9017,14 @@ static int __wlan_hdd_cfg80211_start_ap(struct wiphy *wiphy, /* if sta_sap_scc_on_dfs_chan ini is set, DFS master capability is * assumed disabled in the driver. */ - if ((reg_get_channel_state(hdd_ctx->pdev, channel) == - CHANNEL_STATE_DFS) && sta_sap_scc_on_dfs_chan && !sta_cnt) { - hdd_err("SAP not allowed on DFS channel!!"); + if ((wlan_reg_get_channel_state(hdd_ctx->pdev, channel) == + CHANNEL_STATE_DFS) && !sta_cnt && sta_sap_scc_on_dfs_chan && + !policy_mgr_get_dfs_master_dynamic_enabled( + hdd_ctx->psoc, adapter->session_id)) { + hdd_err("SAP not allowed on DFS channel if no dfs master capability!!"); return -EINVAL; } + if (!reg_is_etsi13_srd_chan_allowed_master_mode(hdd_ctx->pdev) && reg_is_etsi13_srd_chan(hdd_ctx->pdev, channel)) { hdd_err("SAP not allowed on SRD channel."); @@ -9342,8 +9372,10 @@ void hdd_sap_indicate_disconnect_for_sta(struct hdd_adapter *adapter) adapter); if (qdf_is_macaddr_broadcast( - &adapter->sta_info[sta_id].sta_mac)) + &adapter->sta_info[sta_id].sta_mac)) { + hdd_softap_deregister_sta(adapter, sta_id); continue; + } sap_event.sapHddEventCode = eSAP_STA_DISASSOC_EVENT; qdf_mem_copy( diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_hostapd.h b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_hostapd.h index 0d7af0d0675a..fae0e5ea7df4 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_hostapd.h +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_hostapd.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -237,13 +237,34 @@ int wlan_hdd_disable_channels(struct hdd_context *hdd_ctx); * hdd_check_and_disconnect_sta_on_invalid_channel() - Disconnect STA if it is * on invalid channel * @hdd_ctx: pointer to hdd context + * @reason: Mac Disconnect reason code as per @enum eSirMacReasonCodes * * STA should be disconnected before starting the SAP if it is on indoor * channel. * * Return: void */ -void hdd_check_and_disconnect_sta_on_invalid_channel( - struct hdd_context *hdd_ctx); +void +hdd_check_and_disconnect_sta_on_invalid_channel(struct hdd_context *hdd_ctx, + tSirMacReasonCodes reason); + +/** + * hdd_stop_sap_due_to_invalid_channel() - to stop sap in case of invalid chnl + * @work: pointer to work structure + * + * Let's say SAP detected RADAR and trying to select the new channel and if no + * valid channel is found due to none of the channels are available or + * regulatory restriction then SAP needs to be stopped. so SAP state-machine + * will create a work to stop the bss + * + * stop bss has to happen through worker thread because radar indication comes + * from FW through mc thread or main host thread and if same thread is used to + * do stopbss then waiting for stopbss to finish operation will halt mc thread + * to freeze which will trigger stopbss timeout. Instead worker thread can do + * the stopbss operation while mc thread waits for stopbss to finish. + * + * Return: none + */ +void hdd_stop_sap_due_to_invalid_channel(struct work_struct *work); #endif /* end #if !defined(WLAN_HDD_HOSTAPD_H) */ diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_ioctl.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_ioctl.c index 89c5a1064651..86445835a2f9 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_ioctl.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_ioctl.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -52,6 +52,7 @@ */ #define SIZE_OF_SETROAMMODE 11 /* size of SETROAMMODE */ #define SIZE_OF_GETROAMMODE 11 /* size of GETROAMMODE */ +#define SIZE_OF_SETSUSPENDMODE 14 /* * Size of GETCOUNTRYREV output = (sizeof("GETCOUNTRYREV") = 14) + one (space) + @@ -1399,12 +1400,10 @@ hdd_parse_channellist(const uint8_t *pValue, uint8_t *pChannelList, inPtr = strpbrk(inPtr, " "); /* no channel list after the number of channels argument */ if (NULL == inPtr) { - if (0 != j) { - *pNumChannels = j; + if ((j != 0) && (j == *pNumChannels)) return 0; - } else { - return -EINVAL; - } + else + goto cnt_mismatch; } /* remove empty space */ @@ -1416,12 +1415,10 @@ hdd_parse_channellist(const uint8_t *pValue, uint8_t *pChannelList, * argument and spaces */ if ('\0' == *inPtr) { - if (0 != j) { - *pNumChannels = j; + if ((j != 0) && (j == *pNumChannels)) return 0; - } else { - return -EINVAL; - } + else + goto cnt_mismatch; } v = sscanf(inPtr, "%31s ", buf); @@ -1441,6 +1438,11 @@ hdd_parse_channellist(const uint8_t *pValue, uint8_t *pChannelList, } return 0; + +cnt_mismatch: + hdd_debug("Mismatch in ch cnt: %d and num of ch: %d", *pNumChannels, j); + *pNumChannels = 0; + return -EINVAL; } /** @@ -3562,6 +3564,46 @@ static int drv_cmd_set_roam_mode(struct hdd_adapter *adapter, return ret; } +static int drv_cmd_set_suspend_mode(struct hdd_adapter *adapter, + struct hdd_context *hdd_ctx, + uint8_t *command, + uint8_t command_len, + struct hdd_priv_data *priv_data) +{ + int errno; + uint8_t *value = command; + QDF_STATUS status; + uint8_t idle_monitor; + + if (QDF_STA_MODE != adapter->device_mode) { + hdd_debug("Non-STA interface"); + return 0; + } + + /* Move pointer to ahead of SETSUSPENDMODE */ + value = value + SIZE_OF_SETSUSPENDMODE + 1; + + /* Convert the value from ascii to integer */ + errno = kstrtou8(value, 10, &idle_monitor); + if (errno < 0) { + /* + * If the input value is greater than max value of datatype, + * then also kstrtou8 fails + */ + hdd_err("Range validation failed"); + return -EINVAL; + } + + hdd_debug("idle_monitor:%d", idle_monitor); + status = ucfg_pmo_tgt_psoc_send_idle_roam_suspend_mode(hdd_ctx->psoc, + idle_monitor); + if (QDF_IS_STATUS_ERROR(status)) { + hdd_debug("Send suspend mode to fw failed"); + return -EINVAL; + } + return 0; +} + static int drv_cmd_get_roam_mode(struct hdd_adapter *adapter, struct hdd_context *hdd_ctx, uint8_t *command, @@ -3713,6 +3755,140 @@ static int drv_cmd_set_roam_scan_channels(struct hdd_adapter *adapter, return hdd_parse_set_roam_scan_channels(adapter, command); } +#ifdef WLAN_FEATURE_ROAM_OFFLOAD +static bool is_roam_ch_from_fw_supported(struct hdd_context *hdd_ctx) +{ + return hdd_ctx->roam_ch_from_fw_supported; +} + +struct roam_ch_priv { + struct roam_scan_ch_resp roam_ch; +}; + +void hdd_get_roam_scan_ch_cb(hdd_handle_t hdd_handle, + struct roam_scan_ch_resp *roam_ch, + void *context) +{ + struct osif_request *request; + struct roam_ch_priv *priv; + uint8_t *event = NULL, i = 0; + uint32_t *freq = NULL, len; + struct hdd_context *hdd_ctx = hdd_handle_to_context(hdd_handle); + + hdd_debug("roam scan ch list event received : vdev_id:%d command resp: %d", + roam_ch->vdev_id, roam_ch->command_resp); + /** + * If command response is set in the response message, then it is + * getroamscanchannels command response else this event is asyncronous + * event raised by firmware. + */ + if (!roam_ch->command_resp) { + len = roam_ch->num_channels * sizeof(roam_ch->chan_list[0]); + event = (uint8_t *)qdf_mem_malloc(len); + if (!event) { + hdd_err("Failed to alloc event response buf vdev_id: %d", + roam_ch->vdev_id); + return; + } + freq = (uint32_t *)event; + for (i = 0; i < roam_ch->num_channels && + i < WNI_CFG_VALID_CHANNEL_LIST_LEN; i++) { + freq[i] = roam_ch->chan_list[i]; + } + + hdd_send_roam_scan_ch_list_event(hdd_ctx, len, event); + qdf_mem_free(event); + return; + } + + request = osif_request_get(context); + if (!request) { + hdd_err("Obsolete request"); + return; + } + priv = osif_request_priv(request); + + priv->roam_ch.num_channels = roam_ch->num_channels; + for (i = 0; i < priv->roam_ch.num_channels && + i < WNI_CFG_VALID_CHANNEL_LIST_LEN; i++) + priv->roam_ch.chan_list[i] = roam_ch->chan_list[i]; + + osif_request_complete(request); + osif_request_put(request); +} + +static uint32_t +hdd_get_roam_chan_from_fw(struct hdd_adapter *adapter, + uint8_t *chan_list, uint8_t *num_channels) +{ + QDF_STATUS status = QDF_STATUS_E_INVAL; + struct hdd_context *hdd_ctx; + int ret, i; + void *cookie; + struct osif_request *request; + struct roam_ch_priv *priv; + struct roam_scan_ch_resp *p_roam_ch; + struct hdd_station_ctx *hdd_sta_ctx; + static const struct osif_request_params params = { + .priv_size = sizeof(*priv) + + sizeof(priv->roam_ch.chan_list[0]) * + WNI_CFG_VALID_CHANNEL_LIST_LEN, + .timeout_ms = WLAN_WAIT_TIME_STATS, + }; + + hdd_ctx = WLAN_HDD_GET_CTX(adapter); + hdd_sta_ctx = WLAN_HDD_GET_STATION_CTX_PTR(adapter); + request = osif_request_alloc(¶ms); + if (!request) { + hdd_err("Request allocation failure"); + return -ENOMEM; + } + + priv = osif_request_priv(request); + p_roam_ch = &priv->roam_ch; + /** channel list starts after response structure*/ + priv->roam_ch.chan_list = (uint32_t *)(p_roam_ch + 1); + cookie = osif_request_cookie(request); + status = sme_get_roam_scan_ch(hdd_ctx->mac_handle, + adapter->session_id, cookie); + + if (QDF_IS_STATUS_ERROR(status)) { + hdd_err("Unable to retrieve roam channels"); + ret = qdf_status_to_os_return(status); + goto cleanup; + } + + ret = osif_request_wait_for_response(request); + if (ret) { + hdd_err("SME timed out while retrieving raom channels"); + goto cleanup; + } + + *num_channels = priv->roam_ch.num_channels; + for (i = 0; i < *num_channels && + i < WNI_CFG_VALID_CHANNEL_LIST_LEN; i++) + chan_list[i] = wlan_reg_freq_to_chan( + hdd_ctx->pdev, priv->roam_ch.chan_list[i]); + +cleanup: + osif_request_put(request); + + return ret; +} +#else +static bool is_roam_ch_from_fw_supported(struct hdd_context *hdd_ctx) +{ + return false; +} + +static uint32_t +hdd_get_roam_chan_from_fw(struct hdd_adapter *adapter, + uint8_t *chan_list, uint8_t *num_channels) +{ + return QDF_STATUS_E_INVAL; +} +#endif + static int drv_cmd_get_roam_scan_channels(struct hdd_adapter *adapter, struct hdd_context *hdd_ctx, uint8_t *command, @@ -3726,6 +3902,18 @@ static int drv_cmd_get_roam_scan_channels(struct hdd_adapter *adapter, char extra[128] = { 0 }; int len; + if (is_roam_ch_from_fw_supported(hdd_ctx)) { + ret = hdd_get_roam_chan_from_fw(adapter, ChannelList, + &numChannels); + if (ret == QDF_STATUS_SUCCESS) { + goto fill_ch_resp; + } else { + hdd_err("failed to get roam scan channel list from FW"); + ret = -EFAULT; + goto exit; + } + } + if (QDF_STATUS_SUCCESS != sme_get_roam_scan_channel_list(hdd_ctx->mac_handle, ChannelList, @@ -3736,6 +3924,7 @@ static int drv_cmd_get_roam_scan_channels(struct hdd_adapter *adapter, goto exit; } +fill_ch_resp: qdf_mtrace(QDF_MODULE_ID_HDD, QDF_MODULE_ID_HDD, TRACE_CODE_HDD_GETROAMSCANCHANNELS_IOCTL, adapter->session_id, numChannels); @@ -4334,7 +4523,7 @@ static int drv_cmd_get_scan_home_away_time(struct hdd_adapter *adapter, { int ret = 0; uint16_t val; - char extra[32]; + char extra[32] = {0}; uint8_t len = 0; QDF_STATUS status; @@ -4346,7 +4535,6 @@ static int drv_cmd_get_scan_home_away_time(struct hdd_adapter *adapter, hdd_debug("vdev_id: %u, scan home away time: %u", adapter->session_id, val); - len = scnprintf(extra, sizeof(extra), "%s %d", command, val); len = QDF_MIN(priv_data->total_len, len + 1); @@ -6541,7 +6729,7 @@ static int hdd_driver_rxfilter_command_handler(uint8_t *command, ret = hdd_set_rx_filter(adapter, action, 0x01); break; default: - hdd_warn("Unsupported RXFILTER type %d", type); + hdd_debug("Unsupported RXFILTER type %d", type); break; } @@ -7341,13 +7529,11 @@ static int hdd_parse_disable_chan_cmd(struct hdd_adapter *adapter, uint8_t *ptr) hdd_debug("Number of channel to disable are: %d", temp_int); if (!temp_int) { - if (!wlan_hdd_restore_channels(hdd_ctx, false)) { - /* - * Free the cache channels only when the command is - * received with num channels as 0 - */ - wlan_hdd_free_cache_channels(hdd_ctx); - } + /* + * Restore and Free the cache channels when the command is + * received with num channels as 0 + */ + wlan_hdd_restore_channels(hdd_ctx, false); return 0; } @@ -7456,7 +7642,8 @@ static int hdd_parse_disable_chan_cmd(struct hdd_adapter *adapter, uint8_t *ptr) /* Disable the channels received in command SET_DISABLE_CHANNEL_LIST */ if (!is_command_repeated && hdd_ctx->original_channels) { wlan_hdd_disable_channels(hdd_ctx); - hdd_check_and_disconnect_sta_on_invalid_channel(hdd_ctx); + hdd_check_and_disconnect_sta_on_invalid_channel(hdd_ctx, + eSIR_MAC_OPER_CHANNEL_USER_DISABLED); } hdd_exit(); @@ -7566,6 +7753,175 @@ static int drv_cmd_get_disable_chan_list(struct hdd_adapter *adapter, return 0; } #endif + +#ifdef FEATURE_ANI_LEVEL_REQUEST +static int drv_cmd_get_ani_level(struct hdd_adapter *adapter, + struct hdd_context *hdd_ctx, + uint8_t *command, + uint8_t command_len, + struct hdd_priv_data *priv_data) +{ + char *extra; + int copied_length = 0, j, temp_int, ret = 0; + uint8_t *param, num_freqs, num_recv_channels; + uint32_t parsed_freqs[MAX_NUM_FREQS_FOR_ANI_LEVEL]; + struct wmi_host_ani_level_event ani[MAX_NUM_FREQS_FOR_ANI_LEVEL]; + size_t user_size = priv_data->total_len; + + hdd_debug("Received Command to get ANI level"); + + param = strnchr(command, strlen(command), ' '); + + /* No argument after the command */ + if (!param) + return -EINVAL; + + /* No space after the command */ + else if (SPACE_ASCII_VALUE != *param) + return -EINVAL; + + param++; + + /* Removing empty spaces*/ + while ((SPACE_ASCII_VALUE == *param) && ('\0' != *param)) + param++; + + /*no argument followed by spaces */ + if ('\0' == *param) + return -EINVAL; + + /* Getting the first argument ie the number of channels */ + if (sscanf(param, "%d ", &temp_int) != 1) { + hdd_err("Cannot get number of freq from input"); + return -EINVAL; + } + + if (temp_int < 0 || temp_int > MAX_NUM_FREQS_FOR_ANI_LEVEL) { + hdd_err("Invalid Number of channel received"); + return -EINVAL; + } + + hdd_debug("Number of freq to fetch ANI level are: %d", temp_int); + + if (!temp_int) + return 0; + + num_freqs = temp_int; + + for (j = 0; j < num_freqs; j++) { + /* + * Param pointing to the beginning of first space + * after number of channels. + */ + param = strpbrk(param, " "); + /*no channel list after the number of channels argument*/ + if (!param) { + hdd_err("Invalid No of freq provided in the list"); + ret = -EINVAL; + goto parse_failed; + } + + param++; + + /* Removing empty space */ + while ((SPACE_ASCII_VALUE == *param) && ('\0' != *param)) + param++; + + if ('\0' == *param) { + hdd_err("No freq is provided in the list"); + ret = -EINVAL; + goto parse_failed; + } + + if (sscanf(param, "%d ", &temp_int) != 1) { + hdd_err("Cannot read freq number"); + ret = -EINVAL; + goto parse_failed; + } + + hdd_debug("channel_freq[%d] = %d", j, temp_int); + parsed_freqs[j] = temp_int; + } + + /* Extra arguments check */ + param = strpbrk(param, " "); + if (param) { + while ((SPACE_ASCII_VALUE == *param) && ('\0' != *param)) + param++; + + if ('\0' != *param) { + hdd_err("Invalid argument received"); + ret = -EINVAL; + goto parse_failed; + } + } + + qdf_mem_zero(ani, sizeof(ani)); + hdd_debug("num_freq: %d", num_freqs); + if (QDF_IS_STATUS_ERROR(wlan_hdd_get_ani_level(adapter, ani, + parsed_freqs, + num_freqs))) { + hdd_err("Unable to retrieve ani level"); + return -EINVAL; + } + + extra = qdf_mem_malloc(user_size); + if (!extra) { + hdd_err("memory allocation failed"); + ret = -ENOMEM; + goto parse_failed; + } + + /* + * Find the number of channels that are populated. If freq is not + * filled then stop count there + */ + for (num_recv_channels = 0; + (num_recv_channels < num_freqs && + ani[num_recv_channels].chan_freq); num_recv_channels++) + ; + + for (j = 0; j < num_recv_channels; j++) { + /* Sanity check for ANI level validity */ + if (ani[j].ani_level > MAX_ANI_LEVEL) + continue; + + copied_length += scnprintf(extra + copied_length, + user_size - copied_length, "%d:%d\n", + ani[j].chan_freq, ani[j].ani_level); + } + + if (copied_length == 0) { + hdd_err("ANI level not fetched"); + ret = -EINVAL; + goto free; + } + + hdd_debug("data: %s", extra); + + if (copy_to_user(priv_data->buf, extra, copied_length + 1)) { + hdd_err("failed to copy data to user buffer"); + ret = -EFAULT; + goto free; + } + +free: + qdf_mem_free(extra); + +parse_failed: + return ret; +} + +#else +static int drv_cmd_get_ani_level(struct hdd_adapter *adapter, + struct hdd_context *hdd_ctx, + uint8_t *command, + uint8_t command_len, + struct hdd_priv_data *priv_data) +{ + return 0; +} +#endif /* * The following table contains all supported WLAN HDD * IOCTL driver commands and the handler for each of them. @@ -7579,7 +7935,7 @@ static const struct hdd_drv_cmd hdd_drv_cmds[] = { {"COUNTRY", drv_cmd_country, true}, {"SETCOUNTRYREV", drv_cmd_country, true}, {"GETCOUNTRYREV", drv_cmd_get_country, false}, - {"SETSUSPENDMODE", drv_cmd_dummy, false}, + {"SETSUSPENDMODE", drv_cmd_set_suspend_mode, true}, {"SET_AP_WPS_P2P_IE", drv_cmd_dummy, false}, {"SETROAMTRIGGER", drv_cmd_set_roam_trigger, true}, {"GETROAMTRIGGER", drv_cmd_get_roam_trigger, false}, @@ -7679,6 +8035,7 @@ static const struct hdd_drv_cmd hdd_drv_cmds[] = { {"GETANTENNAMODE", drv_cmd_get_antenna_mode, false}, {"SET_DISABLE_CHANNEL_LIST", drv_cmd_set_disable_chan_list, true}, {"GET_DISABLE_CHANNEL_LIST", drv_cmd_get_disable_chan_list, false}, + {"GET_ANI_LEVEL", drv_cmd_get_ani_level, false}, {"STOP", drv_cmd_dummy, false}, /* Deprecated commands */ {"RXFILTER-START", drv_cmd_dummy, false}, diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_ioctl.h b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_ioctl.h index 27708e0f4e24..7073b44ba4e5 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_ioctl.h +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_ioctl.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2014, 2017-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2014, 2017-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -28,6 +28,32 @@ extern struct sock *cesium_nl_srv_sock; int hdd_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd); int wlan_hdd_set_mc_rate(struct hdd_adapter *adapter, int targetRate); +#ifdef WLAN_FEATURE_ROAM_OFFLOAD +/** + * hdd_get_roam_scan_ch_cb() - roam scan channel list callback handler + * @hdd_handle: Pointer to hdd context + * @roam_ch: pointer to roam scan ch event data + * @context: cookie + * + * Callback function to processes roam scan chaanel list event. If + * command response field in the response message is set that means + * event received as a response of GETROAMSCANCHANNELS command else + * event was rasied by firmware upon disconnection. + * + * Return: none + */ +void hdd_get_roam_scan_ch_cb(hdd_handle_t hdd_handle, + struct roam_scan_ch_resp *roam_ch, + void *context); +#else +static inline void +hdd_get_roam_scan_ch_cb(hdd_handle_t hdd_handle, + void *roam_ch, + void *context) +{ +} +#endif + /** * hdd_update_smps_antenna_mode() - set smps and antenna mode * @hdd_ctx: Pointer to hdd context diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_ipa.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_ipa.c index 0c31bbe3c4eb..c1dbbaf33bd6 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_ipa.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_ipa.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -388,7 +388,6 @@ void hdd_ipa_send_nbuf_to_network(qdf_nbuf_t nbuf, qdf_netdev_t dev) struct hdd_adapter *adapter = (struct hdd_adapter *) netdev_priv(dev); int result; unsigned int cpu_index; - uint8_t staid; uint32_t enabled; if (hdd_validate_adapter(adapter)) { @@ -403,12 +402,7 @@ void hdd_ipa_send_nbuf_to_network(qdf_nbuf_t nbuf, qdf_netdev_t dev) if (adapter->device_mode == QDF_SAP_MODE) { /* Send DHCP Indication to FW */ - struct qdf_mac_addr *src_mac = - (struct qdf_mac_addr *)(nbuf->data + - QDF_NBUF_SRC_MAC_OFFSET); - if (QDF_STATUS_SUCCESS == - hdd_softap_get_sta_id(adapter, src_mac, &staid)) - hdd_inspect_dhcp_packet(adapter, staid, nbuf, QDF_RX); + hdd_softap_inspect_dhcp_packet(adapter, nbuf, QDF_RX); } /* @@ -451,10 +445,14 @@ void hdd_ipa_send_nbuf_to_network(qdf_nbuf_t nbuf, qdf_netdev_t dev) QDF_RX)); result = hdd_ipa_aggregated_rx_ind(nbuf); - if (result == NET_RX_SUCCESS) + if (result == NET_RX_SUCCESS) { ++adapter->hdd_stats.tx_rx_stats.rx_delivered[cpu_index]; - else + } else { ++adapter->hdd_stats.tx_rx_stats.rx_refused[cpu_index]; + DPTRACE(qdf_dp_log_proto_pkt_info(NULL, NULL, 0, 0, QDF_RX, + QDF_TRACE_DEFAULT_MSDU_ID, + QDF_TX_RX_STATUS_DROP)); + } /* * Restore PF_WAKE_UP_IDLE flag in the task structure diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_main.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_main.c index bba26b39946c..e4d878a0b878 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_main.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -71,6 +71,9 @@ #include #include #include +#ifdef WLAN_FEATURE_ETHTOOL +#include +#endif #ifdef MSM_PLATFORM #include #endif @@ -144,6 +147,9 @@ #include "wlan_ocb_ucfg_api.h" #include #include +#include "wlan_osif_priv.h" +#include "wlan_pkt_capture_ucfg_api.h" +#include "ftm_time_sync_ucfg_api.h" #ifdef MODULE #define WLAN_MODULE_NAME module_name(THIS_MODULE) @@ -287,7 +293,12 @@ static const struct category_info cinfo[MAX_SUPPORTED_CATEGORY] = { [QDF_MODULE_ID_OCB] = {QDF_TRACE_LEVEL_ALL}, [QDF_MODULE_ID_IPA] = {QDF_TRACE_LEVEL_ALL}, [QDF_MODULE_ID_ACTION_OUI] = {QDF_TRACE_LEVEL_ALL}, + [QDF_MODULE_ID_WIFIPOS] = {QDF_TRACE_LEVEL_ALL}, [QDF_MODULE_ID_TARGET] = {QDF_TRACE_LEVEL_ALL}, + [QDF_MODULE_ID_CP_STATS] = {QDF_TRACE_LEVEL_ALL}, + [QDF_MODULE_ID_NAN] = {QDF_TRACE_LEVEL_ALL}, + [QDF_MODULE_ID_PKT_CAPTURE] = {QDF_TRACE_LEVEL_ALL}, + [QDF_MODULE_ID_FTM_TIME_SYNC] = {QDF_TRACE_LEVEL_ALL}, }; int limit_off_chan_tbl[HDD_MAX_AC][HDD_MAX_OFF_CHAN_ENTRIES] = { @@ -1077,18 +1088,18 @@ void hdd_update_macaddr(struct hdd_context *hdd_ctx, qdf_mem_copy(hdd_ctx->provisioned_mac_addr[0].bytes, hw_macaddr.bytes, QDF_MAC_ADDR_SIZE); hdd_ctx->num_provisioned_addr++; - hdd_info("hdd_ctx->provisioned_mac_addr[0]: " - MAC_ADDRESS_STR, - MAC_ADDR_ARRAY(hdd_ctx-> + hdd_debug("hdd_ctx->provisioned_mac_addr[0]: " + MAC_ADDRESS_STR, + MAC_ADDR_ARRAY(hdd_ctx-> provisioned_mac_addr[0].bytes)); } else { qdf_mem_copy(hdd_ctx->derived_mac_addr[0].bytes, hw_macaddr.bytes, QDF_MAC_ADDR_SIZE); hdd_ctx->num_derived_addr++; - hdd_info("hdd_ctx->derived_mac_addr[0]: " - MAC_ADDRESS_STR, - MAC_ADDR_ARRAY(hdd_ctx->derived_mac_addr[0].bytes)); + hdd_debug("hdd_ctx->derived_mac_addr[0]: " + MAC_ADDRESS_STR, + MAC_ADDR_ARRAY(hdd_ctx->derived_mac_addr[0].bytes)); } for (i = hdd_ctx->num_derived_addr; i < (QDF_MAX_CONCURRENCY_PERSONA - hdd_ctx->num_provisioned_addr); @@ -1109,9 +1120,9 @@ void hdd_update_macaddr(struct hdd_context *hdd_ctx, /* Set locally administered bit */ hdd_ctx->derived_mac_addr[i].bytes[0] |= 0x02; hdd_ctx->derived_mac_addr[i].bytes[3] = macaddr_b3; - hdd_err("hdd_ctx->derived_mac_addr[%d]: " - MAC_ADDRESS_STR, i, - MAC_ADDR_ARRAY(hdd_ctx->derived_mac_addr[i].bytes)); + hdd_debug("hdd_ctx->derived_mac_addr[%d]: " + MAC_ADDRESS_STR, i, + MAC_ADDR_ARRAY(hdd_ctx->derived_mac_addr[i].bytes)); hdd_ctx->num_derived_addr++; } } @@ -1140,6 +1151,7 @@ static int hdd_update_tdls_config(struct hdd_context *hdd_ctx) config->tdls_pre_off_chan_num = cfg->fTDLSPrefOffChanNum; config->tdls_pre_off_chan_bw = cfg->fTDLSPrefOffChanBandwidth; config->tdls_peer_kickout_threshold = cfg->tdls_peer_kickout_threshold; + config->tdls_discovery_wake_timeout = cfg->tdls_discovery_wake_timeout; config->delayed_trig_framint = cfg->DelayedTriggerFrmInt; config->tdls_feature_flags = ((cfg->fEnableTDLSOffChannel ? 1 << TDLS_FEATURE_OFF_CHANNEL : 0) | @@ -1234,7 +1246,7 @@ static void hdd_update_tgt_services(struct hdd_context *hdd_ctx, config->MAWCEnabled &= cfg->is_fw_mawc_capable; hdd_update_tdls_config(hdd_ctx); sme_update_tgt_services(hdd_ctx->mac_handle, cfg); - + hdd_ctx->roam_ch_from_fw_supported = cfg->is_roam_scan_ch_to_host; } /** @@ -1736,6 +1748,7 @@ static void hdd_update_tgt_vht_cap(struct hdd_context *hdd_ctx, hdd_err("could not get GI 80 & 160"); value = 0; } + pconfig->ShortGI160MhzEnable = cfg->vht_short_gi_160; /* set the Guard interval 160MHz */ if (value && !cfg->vht_short_gi_160) { status = sme_cfg_set_int(mac_handle, @@ -1763,6 +1776,7 @@ static void hdd_update_tgt_vht_cap(struct hdd_context *hdd_ctx, } } + pconfig->ShortGI80MhzEnable = cfg->vht_short_gi_80; if (cfg->vht_short_gi_80 & WMI_VHT_CAP_SGI_80MHZ) band_5g->vht_cap.cap |= IEEE80211_VHT_CAP_SHORT_GI_80; if (cfg->vht_short_gi_160 & WMI_VHT_CAP_SGI_160MHZ) @@ -2167,6 +2181,7 @@ int hdd_update_tgt_cfg(hdd_handle_t hdd_handle, struct wma_tgt_cfg *cfg) } hdd_ctx->curr_band = hdd_ctx->config->nBandCapability; + hdd_ctx->psoc->soc_nif.user_config.band_capability = hdd_ctx->curr_band; if (!cds_is_driver_recovering() || cds_is_driver_in_bad_state()) { hdd_ctx->reg.reg_domain = cfg->reg_domain; @@ -2189,11 +2204,11 @@ int hdd_update_tgt_cfg(hdd_handle_t hdd_handle, struct wma_tgt_cfg *cfg) qdf_mem_copy(&hdd_ctx->hw_bd_info, &cfg->hw_bd_info, sizeof(cfg->hw_bd_info)); - if (cfg->max_intf_count > CSR_ROAM_SESSION_MAX) { + if (cfg->max_intf_count > WLAN_MAX_VDEVS) { hdd_err("fw max vdevs (%u) > host max vdevs (%u); using %u", - cfg->max_intf_count, CSR_ROAM_SESSION_MAX, - CSR_ROAM_SESSION_MAX); - hdd_ctx->max_intf_count = CSR_ROAM_SESSION_MAX; + cfg->max_intf_count, WLAN_MAX_VDEVS, + WLAN_MAX_VDEVS); + hdd_ctx->max_intf_count = WLAN_MAX_VDEVS; } else { hdd_ctx->max_intf_count = cfg->max_intf_count; } @@ -2202,13 +2217,14 @@ int hdd_update_tgt_cfg(hdd_handle_t hdd_handle, struct wma_tgt_cfg *cfg) hdd_lpass_target_config(hdd_ctx, cfg); hdd_ctx->ap_arpns_support = cfg->ap_arpns_support; + hdd_update_tgt_services(hdd_ctx, &cfg->services); hdd_update_tgt_ht_cap(hdd_ctx, &cfg->ht_cap); hdd_update_tgt_vht_cap(hdd_ctx, &cfg->vht_cap); if (cfg->services.en_11ax) { - hdd_info("11AX: 11ax is enabled - update HDD config"); + hdd_debug("11AX: 11ax is enabled - update HDD config"); hdd_update_tgt_he_cap(hdd_ctx, cfg); } hdd_update_tgt_twt_cap(hdd_ctx, cfg); @@ -2229,7 +2245,7 @@ int hdd_update_tgt_cfg(hdd_handle_t hdd_handle, struct wma_tgt_cfg *cfg) hdd_update_hw_dbs_capable(hdd_ctx); hdd_ctx->dynamic_nss_chains_support = cfg->dynamic_nss_chains_support; - + hdd_ctx->nan_seperate_vdev_supported = cfg->nan_seperate_vdev_support; hdd_ctx->config->fine_time_meas_cap &= cfg->fine_time_measurement_cap; hdd_ctx->fine_time_meas_cap_target = cfg->fine_time_measurement_cap; hdd_debug("fine_time_meas_cap: 0x%x", @@ -2463,6 +2479,76 @@ static int hdd_mon_open(struct net_device *dev) } #endif +#ifdef WLAN_FEATURE_PKT_CAPTURE +/** + * __hdd_pktcapture_open() - HDD Open function + * @dev: Pointer to net_device structure + * + * This is called in response to ifconfig up + * + * Return: 0 for success; non-zero for failure + */ +static int __hdd_pktcapture_open(struct net_device *dev) +{ + int ret; + struct hdd_adapter *adapter = WLAN_HDD_GET_PRIV_PTR(dev); + struct hdd_context *hdd_ctx = WLAN_HDD_GET_CTX(adapter); + struct hdd_adapter *sta_adapter; + + hdd_enter_dev(dev); + + ret = wlan_hdd_validate_context(hdd_ctx); + if (ret) + return ret; + + sta_adapter = hdd_get_adapter(hdd_ctx, QDF_STA_MODE); + if (!sta_adapter) { + hdd_err("No station interface found"); + return -EINVAL; + } + + adapter->vdev = hdd_objmgr_get_vdev(sta_adapter); + if (!adapter->vdev) + return -EINVAL; + + hdd_mon_mode_ether_setup(dev); + + ret = ucfg_pkt_capture_register_callbacks(adapter->vdev, + hdd_mon_rx_packet_cbk, + adapter); + if (ret) { + hdd_objmgr_put_vdev(sta_adapter->vdev); + return ret; + } + + ret = ucfg_pkt_capture_enable_ops(adapter->vdev); + if (!ret) + set_bit(DEVICE_IFACE_OPENED, &adapter->event_flags); + + return ret; +} + +/** + * hdd_pktcapture_open() - Wrapper function for __hdd_pktcapture_open to + * protect it from SSR + * @dev: Pointer to net_device structure + * + * This is called in response to ifconfig up + * + * Return: 0 for success; non-zero for failure + */ +static int hdd_pktcapture_open(struct net_device *net_dev) +{ + int ret; + + cds_ssr_protect(__func__); + ret = __hdd_pktcapture_open(net_dev); + cds_ssr_unprotect(__func__); + + return ret; +} +#endif + static QDF_STATUS wlan_hdd_update_dbs_scan_and_fw_mode_config(void) { @@ -2546,6 +2632,7 @@ int hdd_start_adapter(struct hdd_adapter *adapter) case QDF_OCB_MODE: case QDF_STA_MODE: case QDF_MONITOR_MODE: + case QDF_NAN_DISC_MODE: ret = hdd_start_station_adapter(adapter); if (ret) goto err_start_adapter; @@ -2663,7 +2750,7 @@ void hdd_update_hw_sw_info(struct hdd_context *hdd_ctx) buf = qdf_mem_malloc(WE_MAX_STR_LEN); if (buf) { buf_len = hdd_wlan_get_version(hdd_ctx, WE_MAX_STR_LEN, buf); - hdd_info("%s", buf); + hdd_nofl_debug("%s", buf); qdf_mem_free(buf); } } @@ -2995,11 +3082,11 @@ int hdd_wlan_start_modules(struct hdd_context *hdd_ctx, bool reinit) switch (hdd_ctx->driver_status) { case DRIVER_MODULES_UNINITIALIZED: - hdd_info("Wlan transitioning (UNINITIALIZED -> CLOSED)"); + hdd_nofl_debug("Wlan transitioning (UNINITIALIZED -> CLOSED)"); unint = true; /* Fall through dont add break here */ case DRIVER_MODULES_CLOSED: - hdd_info("Wlan transitioning (CLOSED -> ENABLED)"); + hdd_nofl_debug("Wlan transitioning (CLOSED -> ENABLED)"); hdd_debug_domain_set(QDF_DEBUG_DOMAIN_ACTIVE); @@ -3067,6 +3154,10 @@ int hdd_wlan_start_modules(struct hdd_context *hdd_ctx, bool reinit) cds_set_rx_thread_cpu_mask( hdd_ctx->config->rx_thread_affinity_mask); + if (hdd_ctx->config->rx_thread_ul_affinity_mask) + cds_set_rx_thread_ul_cpu_mask( + hdd_ctx->config->rx_thread_ul_affinity_mask); + /* initialize components configurations after psoc open */ ret = hdd_update_components_config(hdd_ctx); if (ret) { @@ -3137,7 +3228,7 @@ int hdd_wlan_start_modules(struct hdd_context *hdd_ctx, bool reinit) } hdd_ctx->driver_status = DRIVER_MODULES_ENABLED; - hdd_info("Wlan transitioned (now ENABLED)"); + hdd_nofl_debug("Wlan transitioned (now ENABLED)"); hdd_ctx->start_modules_in_progress = false; @@ -3411,10 +3502,12 @@ static int __hdd_stop(struct net_device *dev) mac_handle = hdd_ctx->mac_handle; - hdd_debug("Disabling Auto Power save timer"); - sme_ps_disable_auto_ps_timer( - mac_handle, - adapter->session_id); + if (!wlan_hdd_is_session_type_monitor(adapter->device_mode)) { + hdd_debug("Disabling Auto Power save timer"); + sme_ps_disable_auto_ps_timer( + mac_handle, + adapter->session_id); + } /* * Disable TX on the interface, after this hard_start_xmit() will not @@ -3431,6 +3524,12 @@ static int __hdd_stop(struct net_device *dev) if (adapter->device_mode == QDF_STA_MODE) hdd_lpass_notify_stop(hdd_ctx); + if (wlan_hdd_is_session_type_monitor(adapter->device_mode)) { + ucfg_pkt_capture_deregister_callbacks(adapter->vdev); + hdd_objmgr_put_vdev(adapter->vdev); + adapter->vdev = NULL; + } + /* * NAN data interface is different in some sense. The traffic on NDI is * bursty in nature and depends on the need to transfer. The service @@ -3649,8 +3748,9 @@ static int __hdd_set_mac_address(struct net_device *dev, void *addr) if (QDF_IS_STATUS_ERROR(qdf_ret_status)) return -EINVAL; - hdd_info("Changing MAC to " MAC_ADDRESS_STR " of the interface %s ", - MAC_ADDR_ARRAY(mac_addr.bytes), dev->name); + hdd_nofl_debug("Changing MAC to " + MAC_ADDRESS_STR " of the interface %s ", + MAC_ADDR_ARRAY(mac_addr.bytes), dev->name); hdd_update_dynamic_mac(hdd_ctx, &adapter->mac_addr, &mac_addr); memcpy(&adapter->mac_addr, psta_mac_addr->sa_data, ETH_ALEN); @@ -3690,8 +3790,8 @@ static uint8_t *wlan_hdd_get_derived_intf_addr(struct hdd_context *hdd_ctx) if (i < 0 || i >= hdd_ctx->num_derived_addr) return NULL; qdf_atomic_set_bit(i, &hdd_ctx->derived_intf_addr_mask); - hdd_info("Assigning MAC from derived list" MAC_ADDRESS_STR, - MAC_ADDR_ARRAY(hdd_ctx->derived_mac_addr[i].bytes)); + hdd_nofl_debug("Assigning MAC from derived list" MAC_ADDRESS_STR, + MAC_ADDR_ARRAY(hdd_ctx->derived_mac_addr[i].bytes)); /* Copy the mac in dynamic mac list at first free position */ for (j = 0; j < QDF_MAX_CONCURRENCY_PERSONA; j++) { @@ -3721,8 +3821,8 @@ static uint8_t *wlan_hdd_get_provisioned_intf_addr(struct hdd_context *hdd_ctx) if (i < 0 || i >= hdd_ctx->num_provisioned_addr) return NULL; qdf_atomic_set_bit(i, &hdd_ctx->provisioned_intf_addr_mask); - hdd_info("Assigning MAC from provisioned list" MAC_ADDRESS_STR, - MAC_ADDR_ARRAY(hdd_ctx->provisioned_mac_addr[i].bytes)); + hdd_debug("Assigning MAC from provisioned list" MAC_ADDRESS_STR, + MAC_ADDR_ARRAY(hdd_ctx->provisioned_mac_addr[i].bytes)); /* Copy the mac in dynamic mac list at first free position */ for (j = 0; j < QDF_MAX_CONCURRENCY_PERSONA; j++) { @@ -3781,17 +3881,17 @@ void wlan_hdd_release_intf_addr(struct hdd_context *hdd_ctx, mac_pos_in_mask, &hdd_ctx-> provisioned_intf_addr_mask); - hdd_info("Releasing MAC from provisioned list"); - hdd_info( - MAC_ADDRESS_STR, - MAC_ADDR_ARRAY(releaseAddr)); + hdd_debug("Releasing MAC from provisioned list"); + hdd_debug( + MAC_ADDRESS_STR, + MAC_ADDR_ARRAY(releaseAddr)); } else { qdf_atomic_clear_bit( mac_pos_in_mask, &hdd_ctx-> derived_intf_addr_mask); - hdd_info("Releasing MAC from derived list"); - hdd_info(MAC_ADDRESS_STR, - MAC_ADDR_ARRAY(releaseAddr)); + hdd_debug("Releasing MAC from derived list"); + hdd_debug(MAC_ADDRESS_STR, + MAC_ADDR_ARRAY(releaseAddr)); } qdf_zero_macaddr(&hdd_ctx-> dynamic_mac_list[i].dynamic_mac); @@ -3829,33 +3929,31 @@ static void __hdd_set_multicast_list(struct net_device *dev) hdd_enter_dev(dev); if (QDF_GLOBAL_FTM_MODE == hdd_get_conparam()) - goto out; + return; errno = wlan_hdd_validate_context(hdd_ctx); if (errno) - goto out; + return; errno = hdd_validate_adapter(adapter); if (errno) - goto out; + return; if (hdd_ctx->driver_status == DRIVER_MODULES_CLOSED) { - hdd_err("%s: Driver module is closed", __func__); - goto out; + hdd_debug("%s: Driver module is closed", __func__); + return; } mc_list_request = qdf_mem_malloc(sizeof(*mc_list_request)); if (!mc_list_request) { hdd_err("Cannot allocate mc_list_request"); - goto out; + return; } /* Delete already configured multicast address list */ - if (adapter->mc_addr_list.mc_cnt > 0) { - hdd_debug("clear previously configured MC address list"); + if (adapter->mc_addr_list.mc_cnt > 0) hdd_disable_and_flush_mc_addr_list(adapter, pmo_mc_list_change_notify); - } if (dev->flags & IFF_ALLMULTI) { hdd_debug("allow all multicast frames"); @@ -3872,8 +3970,6 @@ static void __hdd_set_multicast_list(struct net_device *dev) goto free_req; } netdev_for_each_mc_addr(ha, dev) { - hdd_debug("ha_addr[%d] "MAC_ADDRESS_STR, - i, MAC_ADDR_ARRAY(ha->addr)); if (i == mc_count) break; memset(&(mc_list_request->mc_addr[i].bytes), @@ -3893,8 +3989,8 @@ static void __hdd_set_multicast_list(struct net_device *dev) errno = hdd_cache_mc_addr_list(mc_list_request); if (errno) { - hdd_err("Failed to cache MC address list for vdev %u; errno:%d", - adapter->session_id, errno); + hdd_debug("Failed to cache MC address list for vdev %u; errno:%d", + adapter->session_id, errno); goto free_req; } @@ -3902,9 +3998,6 @@ static void __hdd_set_multicast_list(struct net_device *dev) free_req: qdf_mem_free(mc_list_request); - -out: - hdd_exit(); } @@ -3922,6 +4015,44 @@ static void hdd_set_multicast_list(struct net_device *dev) } #endif +#ifdef WLAN_FEATURE_ETHTOOL +static int hdd_ethtool_get_ts_info(struct net_device *dev, + struct ethtool_ts_info *info) +{ + info->so_timestamping = + SOF_TIMESTAMPING_RX_SOFTWARE | + SOF_TIMESTAMPING_SOFTWARE | + SOF_TIMESTAMPING_TX_SOFTWARE | + SOF_TIMESTAMPING_TX_HARDWARE | + SOF_TIMESTAMPING_RX_HARDWARE | + SOF_TIMESTAMPING_RAW_HARDWARE; + /* phc index is required only if ptp clock supported */ + info->phc_index = -1; + info->tx_types = + (1 << HWTSTAMP_TX_OFF) | + (1 << HWTSTAMP_TX_ON); + info->rx_filters = + (1 << HWTSTAMP_FILTER_NONE) | + (1 << HWTSTAMP_FILTER_ALL); + + return 0; +} + +static const struct ethtool_ops ethtool_drv_ops = { + .get_drvinfo = cfg80211_get_drvinfo, + .get_ts_info = hdd_ethtool_get_ts_info, +}; + +static void hdd_set_ethtool_ops(struct net_device *dev) +{ + dev->ethtool_ops = ðtool_drv_ops; +} +#else +static void hdd_set_ethtool_ops(struct net_device *dev) +{ +} +#endif + static const struct net_device_ops wlan_drv_ops = { .ndo_open = hdd_open, .ndo_stop = hdd_stop, @@ -3964,11 +4095,30 @@ void hdd_set_station_ops(struct net_device *dev) } #endif +#ifdef WLAN_FEATURE_PKT_CAPTURE +/* Packet Capture mode net_device_ops, doesnot Tx and most of operations. */ +static const struct net_device_ops wlan_pktcapture_drv_ops = { + .ndo_open = hdd_pktcapture_open, + .ndo_stop = hdd_stop, + .ndo_get_stats = hdd_get_stats, +}; + +static void hdd_set_pktcapture_ops(struct net_device *dev) +{ + dev->netdev_ops = &wlan_pktcapture_drv_ops; +} +#else +static void hdd_set_pktcapture_ops(struct net_device *dev) +{ +} +#endif + /** * hdd_alloc_station_adapter() - allocate the station hdd adapter * @hdd_ctx: global hdd context * @mac_addr: mac address to assign to the interface * @name: User-visible name of the interface + * @session_type: interface type to be created * * hdd adapter pointer would point to the netdev->priv space, this function * would retrieve the pointer, and setup the hdd adapter configuration. @@ -3977,7 +4127,8 @@ void hdd_set_station_ops(struct net_device *dev) */ static struct hdd_adapter * hdd_alloc_station_adapter(struct hdd_context *hdd_ctx, tSirMacAddr mac_addr, - unsigned char name_assign_type, const char *name) + unsigned char name_assign_type, const char *name, + uint8_t session_type) { struct net_device *dev; struct hdd_adapter *adapter; @@ -3989,7 +4140,8 @@ hdd_alloc_station_adapter(struct hdd_context *hdd_ctx, tSirMacAddr mac_addr, #if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 17, 0)) || defined(WITH_BACKPORTS) name_assign_type, #endif - (cds_get_conparam() == QDF_GLOBAL_MONITOR_MODE ? + ((cds_get_conparam() == QDF_GLOBAL_MONITOR_MODE || + wlan_hdd_is_session_type_monitor(session_type)) ? hdd_mon_mode_ether_setup : ether_setup), NUM_TX_QUEUES); @@ -4034,7 +4186,11 @@ hdd_alloc_station_adapter(struct hdd_context *hdd_ctx, tSirMacAddr mac_addr, dev->features |= NETIF_F_RXCSUM; hdd_set_tso_flags(hdd_ctx, dev); - hdd_set_station_ops(adapter->dev); + + if (wlan_hdd_is_session_type_monitor(session_type)) + hdd_set_pktcapture_ops(adapter->dev); + else + hdd_set_station_ops(adapter->dev); hdd_dev_setup_destructor(dev); dev->ieee80211_ptr = &adapter->wdev; @@ -4195,6 +4351,21 @@ int hdd_vdev_ready(struct hdd_adapter *adapter) return qdf_status_to_os_return(status); } +static void hdd_cleanup_cached_sta_info(struct hdd_adapter *adapter) +{ + uint16_t sta_id; + struct wlan_ies *ies; + + for (sta_id = 0; sta_id < WLAN_MAX_STA_COUNT; sta_id++) { + ies = &adapter->cache_sta_info[sta_id].assoc_req_ies; + if (ies->data && ies->len) { + qdf_mem_free(ies->data); + ies->data = NULL; + ies->len = 0; + } + } +} + int hdd_vdev_destroy(struct hdd_adapter *adapter) { QDF_STATUS status; @@ -4204,11 +4375,11 @@ int hdd_vdev_destroy(struct hdd_adapter *adapter) struct wlan_objmgr_vdev *vdev; vdev_id = adapter->session_id; - hdd_info("destroying vdev %d", vdev_id); + hdd_nofl_debug("destroying vdev %d", vdev_id); /* vdev created sanity check */ if (!test_bit(SME_SESSION_OPENED, &adapter->event_flags)) { - hdd_err("vdev %u does not exist", vdev_id); + hdd_nofl_debug("vdev %u does not exist", vdev_id); return -EINVAL; } @@ -4220,6 +4391,8 @@ int hdd_vdev_destroy(struct hdd_adapter *adapter) status = ucfg_reg_11d_vdev_delete_update(vdev); + hdd_cleanup_cached_sta_info(adapter); + /* Disable Scan and abort any pending scans for this vdev */ ucfg_scan_set_vdev_del_in_progress(vdev); hdd_objmgr_put_vdev(vdev); @@ -4245,15 +4418,16 @@ int hdd_vdev_destroy(struct hdd_adapter *adapter) if (adapter->device_mode == QDF_NDI_MODE) hdd_ndp_session_end_handler(adapter); - if (status == QDF_STATUS_E_TIMEOUT) + if (status == QDF_STATUS_E_TIMEOUT) { hdd_err("timed out waiting for sme close session"); - else if (adapter->qdf_session_close_event.force_set) { - ucfg_mlme_force_objmgr_vdev_peer_cleanup(vdev_id); + sme_cleanup_session(hdd_ctx->mac_handle, vdev_id); + } else if (adapter->qdf_session_close_event.force_set) { hdd_info("SSR occurred during sme close session"); - } - else + ucfg_mlme_force_objmgr_vdev_peer_cleanup(vdev_id); + } else { hdd_err("failed to wait for sme close session; status:%u", status); + } } release_vdev: @@ -4265,7 +4439,7 @@ int hdd_vdev_destroy(struct hdd_adapter *adapter) return errno; } - hdd_info("vdev %d destroyed successfully", vdev_id); + hdd_nofl_debug("vdev %d destroyed successfully", vdev_id); return 0; } @@ -4411,6 +4585,26 @@ hdd_store_nss_chains_cfg_in_vdev(struct hdd_adapter *adapter) sme_store_nss_chains_cfg_in_vdev(adapter->vdev, &vdev_ini_cfg); } +#ifdef WLAN_FEATURE_NAN +static void hdd_configure_nan_support_mp0_discovery(struct hdd_adapter *adapter) +{ + struct hdd_context *hdd_ctx = WLAN_HDD_GET_CTX(adapter); + + if (QDF_NAN_DISC_MODE == adapter->device_mode) { + sme_cli_set_command( + adapter->session_id, + WMI_VDEV_PARAM_ALLOW_NAN_INITIAL_DISCOVERY_OF_MP0_CLUSTER, + hdd_ctx->config->support_mp0_discovery, + VDEV_CMD); + } +} +#else +static inline void hdd_configure_nan_support_mp0_discovery( + struct hdd_adapter *adapter) +{ +} +#endif + int hdd_vdev_create(struct hdd_adapter *adapter, csr_roam_complete_cb callback, void *ctx) { @@ -4420,7 +4614,7 @@ int hdd_vdev_create(struct hdd_adapter *adapter, struct sme_session_params sme_session_params = {0}; struct wlan_objmgr_vdev *vdev; - hdd_info("creating new vdev"); + hdd_nofl_debug("creating new vdev"); /* do vdev create via objmgr */ hdd_ctx = WLAN_HDD_GET_CTX(adapter); @@ -4510,7 +4704,9 @@ int hdd_vdev_create(struct hdd_adapter *adapter, /* store the ini and dynamic nss chain params to the vdev object */ hdd_store_nss_chains_cfg_in_vdev(adapter); - hdd_info("vdev %d created successfully", adapter->session_id); + hdd_nofl_debug("vdev %d created successfully", adapter->session_id); + + hdd_configure_nan_support_mp0_discovery(adapter); return 0; @@ -4551,7 +4747,7 @@ QDF_STATUS hdd_init_station_mode(struct hdd_adapter *adapter) qdf_mem_set(sta_ctx->conn_info.staId, sizeof(sta_ctx->conn_info.staId), HDD_WLAN_INVALID_STA_ID); - + sme_roam_reset_configs(mac_handle, adapter->session_id); /* set fast roaming capability in sme session */ status = sme_config_fast_roaming(mac_handle, adapter->session_id, true); @@ -4661,9 +4857,11 @@ void hdd_deinit_adapter(struct hdd_context *hdd_ctx, switch (adapter->device_mode) { case QDF_STA_MODE: case QDF_P2P_CLIENT_MODE: + case QDF_MONITOR_MODE: case QDF_P2P_DEVICE_MODE: case QDF_IBSS_MODE: case QDF_NDI_MODE: + case QDF_NAN_DISC_MODE: { hdd_deinit_station_mode(hdd_ctx, adapter, rtnl_held); break; @@ -4964,7 +5162,7 @@ static int hdd_configure_chain_mask(struct hdd_adapter *adapter) return 0; error: - hdd_err("WMI PDEV set param failed %d", ret_val); + hdd_debug("WMI PDEV set param failed %d", ret_val); return -EINVAL; } @@ -5158,8 +5356,7 @@ int hdd_set_fw_params(struct hdd_adapter *adapter) goto error; } - if (hdd_configure_chain_mask(adapter)) - goto error; + hdd_configure_chain_mask(adapter); } else { #define HDD_DTIM_1CHAIN_RX_ID 0x5 #define HDD_SMPS_PARAM_VALUE_S 29 @@ -5184,8 +5381,7 @@ int hdd_set_fw_params(struct hdd_adapter *adapter) #undef HDD_DTIM_1CHAIN_RX_ID #undef HDD_SMPS_PARAM_VALUE_S - if (hdd_configure_chain_mask(adapter)) - goto error; + hdd_configure_chain_mask(adapter); } ret = sme_cli_set_command(adapter->session_id, @@ -5286,6 +5482,27 @@ static void hdd_reset_locally_admin_bit(struct hdd_context *hdd_ctx, MAC_ADDRESS_STR, MAC_ADDR_ARRAY(macAddr)); } + +#if defined(WLAN_FEATURE_NAN) && \ + (KERNEL_VERSION(4, 9, 0) <= LINUX_VERSION_CODE) +/** + * wlan_hdd_set_nan_if_type() - Set the NAN iftype + * @adapter: pointer to HDD adapter + * + * Set the NL80211_IFTYPE_NAN to wdev iftype. + * + * Return: None + */ +static void wlan_hdd_set_nan_if_type(struct hdd_adapter *adapter) +{ + adapter->wdev.iftype = NL80211_IFTYPE_NAN; +} +#else +static void wlan_hdd_set_nan_if_type(struct hdd_adapter *adapter) +{ +} +#endif + /** * hdd_open_adapter() - open and setup the hdd adatper * @hdd_ctx: global hdd context @@ -5309,7 +5526,7 @@ struct hdd_adapter *hdd_open_adapter(struct hdd_context *hdd_ctx, uint8_t sessio struct hdd_adapter *adapter = NULL; QDF_STATUS status = QDF_STATUS_E_FAILURE; - if (hdd_ctx->current_intf_count >= hdd_ctx->max_intf_count) { + if (hdd_ctx->current_intf_count >= WLAN_MAX_VDEVS) { /* * Max limit reached on the number of vdevs configured by the * host. Return error @@ -5359,9 +5576,10 @@ struct hdd_adapter *hdd_open_adapter(struct hdd_context *hdd_ctx, uint8_t sessio case QDF_OCB_MODE: case QDF_NDI_MODE: case QDF_MONITOR_MODE: + case QDF_NAN_DISC_MODE: adapter = hdd_alloc_station_adapter(hdd_ctx, macAddr, name_assign_type, - iface_name); + iface_name, session_type); if (NULL == adapter) { hdd_err("failed to allocate adapter for session %d", @@ -5375,6 +5593,8 @@ struct hdd_adapter *hdd_open_adapter(struct hdd_context *hdd_ctx, uint8_t sessio adapter->wdev.iftype = NL80211_IFTYPE_P2P_DEVICE; else if (QDF_MONITOR_MODE == session_type) adapter->wdev.iftype = NL80211_IFTYPE_MONITOR; + else if (QDF_NAN_DISC_MODE == session_type) + wlan_hdd_set_nan_if_type(adapter); else adapter->wdev.iftype = NL80211_IFTYPE_STATION; @@ -5459,7 +5679,7 @@ struct hdd_adapter *hdd_open_adapter(struct hdd_context *hdd_ctx, uint8_t sessio case QDF_FTM_MODE: adapter = hdd_alloc_station_adapter(hdd_ctx, macAddr, name_assign_type, - iface_name); + iface_name, session_type); if (NULL == adapter) { hdd_err("Failed to allocate adapter for FTM mode"); return NULL; @@ -5486,8 +5706,11 @@ struct hdd_adapter *hdd_open_adapter(struct hdd_context *hdd_ctx, uint8_t sessio hdd_init_completion(adapter); INIT_WORK(&adapter->scan_block_work, wlan_hdd_cfg80211_scan_block_cb); + INIT_WORK(&adapter->sap_stop_bss_work, + hdd_stop_sap_due_to_invalid_channel); qdf_list_create(&adapter->blocked_scan_request_q, WLAN_MAX_SCAN_COUNT); qdf_mutex_create(&adapter->blocked_scan_request_q_lock); + qdf_event_create(&adapter->acs_complete_event); if (QDF_STATUS_SUCCESS == status) { /* Add it to the hdd's session list. */ @@ -5521,12 +5744,13 @@ struct hdd_adapter *hdd_open_adapter(struct hdd_context *hdd_ctx, uint8_t sessio hdd_err("Interface %s wow debug_fs init failed", netdev_name(adapter->dev)); - hdd_info("%s interface created. iftype: %d", netdev_name(adapter->dev), - session_type); + hdd_debug("%s interface created. iftype: %d", netdev_name(adapter->dev), + session_type); if (adapter->device_mode == QDF_STA_MODE) wlan_hdd_debugfs_csr_init(adapter); + hdd_set_ethtool_ops(adapter->dev); return adapter; err_free_netdev: @@ -5552,6 +5776,7 @@ QDF_STATUS hdd_close_adapter(struct hdd_context *hdd_ctx, struct hdd_adapter *ad qdf_list_destroy(&adapter->blocked_scan_request_q); qdf_mutex_destroy(&adapter->blocked_scan_request_q_lock); + qdf_event_destroy(&adapter->acs_complete_event); /* cleanup adapter */ policy_mgr_clear_concurrency_mode(hdd_ctx->psoc, @@ -5670,6 +5895,7 @@ QDF_STATUS hdd_stop_adapter_ext(struct hdd_context *hdd_ctx, tsap_config_t *sap_config; mac_handle_t mac_handle; struct wlan_objmgr_vdev *vdev; + enum eSirMacReasonCodes reason = eSIR_MAC_IFACE_DOWN; hdd_enter(); @@ -5705,6 +5931,7 @@ QDF_STATUS hdd_stop_adapter_ext(struct hdd_context *hdd_ctx, case QDF_IBSS_MODE: case QDF_P2P_DEVICE_MODE: case QDF_NDI_MODE: + case QDF_NAN_DISC_MODE: if ((QDF_NDI_MODE == adapter->device_mode) || hdd_conn_is_connected( WLAN_HDD_GET_STATION_CTX_PTR(adapter)) || @@ -5712,22 +5939,28 @@ QDF_STATUS hdd_stop_adapter_ext(struct hdd_context *hdd_ctx, WLAN_HDD_GET_STATION_CTX_PTR(adapter))) { INIT_COMPLETION(adapter->disconnect_comp_var); roam_profile = hdd_roam_profile(adapter); + if (cds_is_driver_recovering()) + reason = eSIR_MAC_DEVICE_RECOVERY; + /* For NDI do not use roam_profile */ if (QDF_NDI_MODE == adapter->device_mode) qdf_ret_status = sme_roam_disconnect( mac_handle, adapter->session_id, - eCSR_DISCONNECT_REASON_NDI_DELETE); + eCSR_DISCONNECT_REASON_NDI_DELETE, + reason); else if (roam_profile->BSSType == eCSR_BSS_TYPE_START_IBSS) qdf_ret_status = sme_roam_disconnect( mac_handle, adapter->session_id, - eCSR_DISCONNECT_REASON_IBSS_LEAVE); + eCSR_DISCONNECT_REASON_IBSS_LEAVE, + reason); else if (QDF_STA_MODE == adapter->device_mode) { rc = wlan_hdd_disconnect( adapter, - eCSR_DISCONNECT_REASON_DEAUTH); + eCSR_DISCONNECT_REASON_DEAUTH, + reason); if (rc != 0 && ucfg_ipa_is_enabled()) { hdd_err("STA disconnect failed"); ucfg_ipa_uc_cleanup_sta(hdd_ctx->pdev, @@ -5737,7 +5970,8 @@ QDF_STATUS hdd_stop_adapter_ext(struct hdd_context *hdd_ctx, qdf_ret_status = sme_roam_disconnect( mac_handle, adapter->session_id, - eCSR_DISCONNECT_REASON_UNSPECIFIED); + eCSR_DISCONNECT_REASON_UNSPECIFIED, + reason); } /* success implies disconnect command got * queued up successfully @@ -5769,7 +6003,7 @@ QDF_STATUS hdd_stop_adapter_ext(struct hdd_context *hdd_ctx, adapter->session_id, NULL, true); if (QDF_IS_STATUS_ERROR(qdf_ret_status)) - hdd_err("Cannot flush PMKIDCache"); + hdd_debug("Cannot flush PMKIDCache"); #ifdef WLAN_OPEN_SOURCE cancel_work_sync(&adapter->ipv4_notifier_work); @@ -5814,8 +6048,19 @@ QDF_STATUS hdd_stop_adapter_ext(struct hdd_context *hdd_ctx, break; case QDF_MONITOR_MODE: + if (wlan_hdd_is_session_type_monitor(QDF_MONITOR_MODE)) { + adapter = hdd_get_adapter(hdd_ctx, QDF_MONITOR_MODE); + + if (adapter->vdev) { + ucfg_pkt_capture_deregister_callbacks( + adapter->vdev); + hdd_objmgr_put_vdev(adapter->vdev); + adapter->vdev = NULL; + } + } wlan_hdd_scan_abort(adapter); hdd_deregister_tx_flow_control(adapter); + sme_delete_mon_session(mac_handle, adapter->session_id); hdd_vdev_destroy(adapter); break; @@ -5842,7 +6087,13 @@ QDF_STATUS hdd_stop_adapter_ext(struct hdd_context *hdd_ctx, cds_flush_work(&adapter->sap_stop_bss_work); /* Any softap specific cleanup here... */ - qdf_atomic_set(&adapter->session.ap.acs_in_progress, 0); + if (qdf_atomic_read(&adapter->session.ap.acs_in_progress)) { + hdd_info("ACS in progress, wait for complete"); + qdf_wait_for_event_completion( + &adapter->acs_complete_event, + ACS_COMPLETE_TIMEOUT); + } + wlan_hdd_undo_acs(adapter); if (adapter->device_mode == QDF_P2P_GO_MODE) wlan_hdd_cleanup_remain_on_channel_ctx(adapter); @@ -6049,7 +6300,6 @@ QDF_STATUS hdd_reset_all_adapters(struct hdd_context *hdd_ctx) struct hdd_adapter *adapter; struct hdd_station_ctx *sta_ctx; struct qdf_mac_addr peerMacAddr; - int sta_id; struct wlan_objmgr_vdev *vdev; hdd_enter(); @@ -6082,20 +6332,19 @@ QDF_STATUS hdd_reset_all_adapters(struct hdd_context *hdd_ctx) &adapter->acs_pending_work); clear_bit(ACS_PENDING, &adapter->event_flags); } - - if (test_bit(SOFTAP_BSS_STARTED, - &adapter->event_flags)) { - hdd_sap_indicate_disconnect_for_sta(adapter); - clear_bit(SOFTAP_BSS_STARTED, - &adapter->event_flags); - } - } else { wlan_hdd_netif_queue_control(adapter, WLAN_STOP_ALL_NETIF_QUEUE_N_CARRIER, WLAN_CONTROL_PATH); } + if ((adapter->device_mode == QDF_P2P_GO_MODE || + adapter->device_mode == QDF_SAP_MODE) && + test_bit(SOFTAP_BSS_STARTED, &adapter->event_flags)) { + hdd_sap_indicate_disconnect_for_sta(adapter); + clear_bit(SOFTAP_BSS_STARTED, &adapter->event_flags); + } + hdd_reset_scan_operation(hdd_ctx, adapter); hdd_deinit_tx_rx(adapter); @@ -6129,17 +6378,6 @@ QDF_STATUS hdd_reset_all_adapters(struct hdd_context *hdd_ctx) qdf_copy_macaddr(&peerMacAddr, &sta_ctx->conn_info.bssId); - } else if (adapter->device_mode == QDF_P2P_GO_MODE) { - clear_bit(SOFTAP_BSS_STARTED, &adapter->event_flags); - for (sta_id = 0; sta_id < WLAN_MAX_STA_COUNT; sta_id++) { - if (adapter->sta_info[sta_id].in_use) { - hdd_debug("[SSR] deregister STA with ID %d", - sta_id); - hdd_softap_deregister_sta(adapter, - sta_id); - adapter->sta_info[sta_id].in_use = 0; - } - } } hdd_nud_ignore_tracking(adapter, true); @@ -6754,13 +6992,35 @@ int wlan_hdd_set_mon_chan(struct hdd_adapter *adapter, uint32_t chan, QDF_STATUS status; struct qdf_mac_addr bssid; struct csr_roam_profile roam_profile; - struct ch_params ch_params; + enum phy_ch_width ch_width; + uint8_t max_fw_bw; if (QDF_GLOBAL_MONITOR_MODE != hdd_get_conparam()) { hdd_err("Not supported, device is not in monitor mode"); return -EINVAL; } + /* Verify the BW before accepting this request */ + ch_width = bandwidth; + + if (ch_width > CH_WIDTH_10MHZ || + (!cds_is_sub_20_mhz_enabled() && ch_width > CH_WIDTH_160MHZ)) { + hdd_err("invalid BW received %d", ch_width); + return -EINVAL; + } + + max_fw_bw = sme_get_vht_ch_width(); + + hdd_debug("max fw BW %d ch width %d", max_fw_bw, ch_width); + if ((ch_width == CH_WIDTH_160MHZ && + max_fw_bw <= WNI_CFG_VHT_CHANNEL_WIDTH_80MHZ) || + (ch_width == CH_WIDTH_80P80MHZ && + max_fw_bw <= WNI_CFG_VHT_CHANNEL_WIDTH_160MHZ)) { + hdd_err("FW does not support this BW %d max BW supported %d", + ch_width, max_fw_bw); + return -EINVAL; + } + /* Validate Channel */ if (!WLAN_REG_IS_24GHZ_CH(chan) && !WLAN_REG_IS_5GHZ_CH(chan)) { hdd_err("Channel %d Not supported", chan); @@ -6798,12 +7058,6 @@ int wlan_hdd_set_mon_chan(struct hdd_adapter *adapter, uint32_t chan, qdf_mem_copy(bssid.bytes, adapter->mac_addr.bytes, QDF_MAC_ADDR_SIZE); - ch_params.ch_width = bandwidth; - wlan_reg_set_channel_params(hdd_ctx->pdev, chan, 0, &ch_params); - if (ch_params.ch_width == CH_WIDTH_INVALID) { - hdd_err("Invalid capture channel or bandwidth for a country"); - return -EINVAL; - } if (wlan_hdd_change_hw_mode_for_given_chnl(adapter, chan, POLICY_MGR_UPDATE_REASON_SET_OPER_CHAN)) { hdd_err("Failed to change hw mode"); @@ -6811,7 +7065,7 @@ int wlan_hdd_set_mon_chan(struct hdd_adapter *adapter, uint32_t chan, } status = sme_roam_channel_change_req(hdd_ctx->mac_handle, - bssid, &ch_params, + bssid, &roam_profile.ch_params, &roam_profile); if (status) { hdd_err("Status: %d Failed to set sme_roam Channel for monitor mode", @@ -6888,6 +7142,7 @@ QDF_STATUS hdd_start_all_adapters(struct hdd_context *hdd_ctx) case QDF_STA_MODE: case QDF_P2P_CLIENT_MODE: case QDF_P2P_DEVICE_MODE: + case QDF_NAN_DISC_MODE: connState = (WLAN_HDD_GET_STATION_CTX_PTR(adapter)) ->conn_info.connState; @@ -6916,8 +7171,9 @@ QDF_STATUS hdd_start_all_adapters(struct hdd_context *hdd_ctx) /* indicate disconnected event to nl80211 */ wlan_hdd_cfg80211_indicate_disconnect( - adapter->dev, false, - WLAN_REASON_UNSPECIFIED); + adapter, true, + eSIR_MAC_DEVICE_RECOVERY, + NULL, 0); } else if (eConnectionState_Connecting == connState) { /* * Indicate connect failure to supplicant if we @@ -6948,6 +7204,15 @@ QDF_STATUS hdd_start_all_adapters(struct hdd_context *hdd_ctx) hdd_delete_sta(adapter); break; case QDF_MONITOR_MODE: + if (wlan_hdd_is_session_type_monitor( + QDF_MONITOR_MODE) && + ucfg_pkt_capture_get_mode(hdd_ctx->psoc)) { + ucfg_pkt_capture_register_callbacks( + adapter->vdev, + hdd_mon_rx_packet_cbk, + adapter); + break; + } hdd_start_station_adapter(adapter); hdd_set_mon_rx_cb(adapter->dev); wlan_hdd_set_mon_chan(adapter, adapter->mon_chan, @@ -7019,6 +7284,48 @@ QDF_STATUS hdd_get_next_adapter(struct hdd_context *hdd_ctx, return status; } +QDF_STATUS hdd_get_front_adapter_no_lock(struct hdd_context *hdd_ctx, + struct hdd_adapter **out_adapter) +{ + QDF_STATUS status; + qdf_list_node_t *node; + + *out_adapter = NULL; + + status = qdf_list_peek_front(&hdd_ctx->hdd_adapters, &node); + + if (QDF_IS_STATUS_ERROR(status)) + return status; + + *out_adapter = qdf_container_of(node, struct hdd_adapter, node); + + return QDF_STATUS_SUCCESS; +} + +QDF_STATUS hdd_get_next_adapter_no_lock(struct hdd_context *hdd_ctx, + struct hdd_adapter *current_adapter, + struct hdd_adapter **out_adapter) +{ + QDF_STATUS status; + qdf_list_node_t *node; + + if (!current_adapter) + return QDF_STATUS_E_INVAL; + + *out_adapter = NULL; + + status = qdf_list_peek_next(&hdd_ctx->hdd_adapters, + ¤t_adapter->node, + &node); + + if (QDF_IS_STATUS_ERROR(status)) + return status; + + *out_adapter = qdf_container_of(node, struct hdd_adapter, node); + + return status; +} + QDF_STATUS hdd_remove_adapter(struct hdd_context *hdd_ctx, struct hdd_adapter *adapter) { @@ -7075,6 +7382,49 @@ QDF_STATUS hdd_add_adapter_front(struct hdd_context *hdd_ctx, return status; } +QDF_STATUS hdd_adapter_iterate(hdd_adapter_iterate_cb cb, void *context) +{ + struct hdd_context *hdd_ctx; + struct hdd_adapter *cache[HDD_MAX_ADAPTERS]; + struct hdd_adapter *adapter; + uint32_t n_cache = 0; + QDF_STATUS ret = QDF_STATUS_SUCCESS; + QDF_STATUS status; + int i; + + hdd_ctx = cds_get_context(QDF_MODULE_ID_HDD); + if (unlikely(!hdd_ctx)) { + hdd_err("HDD context is Null"); + return QDF_STATUS_E_FAILURE; + } + + qdf_spin_lock_bh(&hdd_ctx->hdd_adapter_lock); + for (hdd_get_front_adapter_no_lock(hdd_ctx, &adapter); adapter; + hdd_get_next_adapter_no_lock(hdd_ctx, adapter, &adapter)) { + cache[n_cache++] = adapter; + } + qdf_spin_unlock_bh(&hdd_ctx->hdd_adapter_lock); + + for (i = 0; i < n_cache - 1; i++) { + adapter = hdd_adapter_get_by_reference(hdd_ctx, cache[i]); + if (!adapter) { + /* + * detected remove while iterating + * concurrency failure + */ + ret = QDF_STATUS_E_FAILURE; + continue; + } + + status = cb(adapter, context); + hdd_adapter_put(adapter); + if (status != QDF_STATUS_SUCCESS) + return status; + } + + return ret; +} + struct hdd_adapter *hdd_get_adapter_by_rand_macaddr( struct hdd_context *hdd_ctx, tSirMacAddr mac_addr) { @@ -7144,6 +7494,26 @@ hdd_get_adapter_by_sme_session_id(struct hdd_context *hdd_ctx, return NULL; } +struct hdd_adapter *hdd_adapter_get_by_reference(struct hdd_context *hdd_ctx, + struct hdd_adapter *reference) +{ + struct hdd_adapter *adapter; + + hdd_for_each_adapter(hdd_ctx, adapter) { + if (adapter == reference) { + dev_hold(adapter->dev); + break; + } + } + + return adapter; +} + +void hdd_adapter_put(struct hdd_adapter *adapter) +{ + dev_put(adapter->dev); +} + struct hdd_adapter *hdd_get_adapter_by_iface_name(struct hdd_context *hdd_ctx, const char *iface_name) { @@ -7405,7 +7775,6 @@ void hdd_set_disconnect_status(struct hdd_adapter *adapter, bool status) qdf_mutex_acquire(&adapter->disconnection_status_lock); adapter->disconnection_in_progress = status; qdf_mutex_release(&adapter->disconnection_status_lock); - hdd_debug("setting disconnection status: %d", status); } /** @@ -7537,14 +7906,40 @@ static int hdd_init_netlink_services(struct hdd_context *hdd_ctx) } /** - * hdd_context_deinit() - Deinitialize HDD context - * @hdd_ctx: HDD context. + * hdd_rx_wake_lock_destroy() - Destroy RX wakelock + * @hdd_ctx: HDD context. * - * Deinitialize HDD context along with all the feature specific contexts but - * do not free hdd context itself. Caller of this API is supposed to free - * HDD context. + * Destroy RX wakelock. * - * return: 0 on success and errno on failure. + * Return: None. + */ +static void hdd_rx_wake_lock_destroy(struct hdd_context *hdd_ctx) +{ + qdf_wake_lock_destroy(&hdd_ctx->rx_wake_lock); +} + +/** + * hdd_rx_wake_lock_create() - Create RX wakelock + * @hdd_ctx: HDD context. + * + * Create RX wakelock. + * + * Return: None. + */ +static void hdd_rx_wake_lock_create(struct hdd_context *hdd_ctx) +{ + qdf_wake_lock_create(&hdd_ctx->rx_wake_lock, "qcom_rx_wakelock"); +} + +/** + * hdd_context_deinit() - Deinitialize HDD context + * @hdd_ctx: HDD context. + * + * Deinitialize HDD context along with all the feature specific contexts but + * do not free hdd context itself. Caller of this API is supposed to free + * HDD context. + * + * return: 0 on success and errno on failure. */ static int hdd_context_deinit(struct hdd_context *hdd_ctx) { @@ -7554,6 +7949,8 @@ static int hdd_context_deinit(struct hdd_context *hdd_ctx) hdd_sap_context_destroy(hdd_ctx); + hdd_rx_wake_lock_destroy(hdd_ctx); + hdd_scan_context_destroy(hdd_ctx); qdf_list_destroy(&hdd_ctx->hdd_adapters); @@ -7571,6 +7968,8 @@ static int hdd_context_deinit(struct hdd_context *hdd_ctx) */ static void hdd_context_destroy(struct hdd_context *hdd_ctx) { + wlan_hdd_sar_timers_deinit(hdd_ctx); + cds_set_context(QDF_MODULE_ID_HDD, NULL); wlan_hdd_deinit_tx_rx_histogram(hdd_ctx); @@ -7684,6 +8083,7 @@ static void hdd_wlan_exit(struct hdd_context *hdd_ctx) */ hdd_abort_mac_scan_all_adapters(hdd_ctx); hdd_abort_sched_scan_all_adapters(hdd_ctx); + hdd_stop_all_adapters(hdd_ctx); hdd_deinit_all_adapters(hdd_ctx, false); } @@ -7732,8 +8132,6 @@ static void hdd_wlan_exit(struct hdd_context *hdd_ctx) driver_status = hdd_objmgr_release_and_destroy_psoc(hdd_ctx); if (driver_status) hdd_err("Psoc delete failed"); - - hdd_context_destroy(hdd_ctx); } void __hdd_wlan_exit(void) @@ -8113,6 +8511,17 @@ static void hdd_pld_request_bus_bandwidth(struct hdd_context *hdd_ctx, hdd_set_rps_cpu_mask(hdd_ctx); } + if (hdd_ctx->config->rx_thread_ul_affinity_mask) { + if (next_vote_level == PLD_BUS_WIDTH_HIGH && + (tx_packets > + hdd_ctx->config->busBandwidthHighThreshold) && + (rx_packets > + hdd_ctx->config->busBandwidthLowThreshold)) + cds_sched_handle_rx_thread_affinity_req(true); + else if (next_vote_level != PLD_BUS_WIDTH_HIGH) + cds_sched_handle_rx_thread_affinity_req(false); + } + if (hdd_ctx->config->napi_cpu_affinity_mask) hdd_napi_apply_throughput_policy(hdd_ctx, tx_packets, @@ -8279,8 +8688,9 @@ static void __hdd_bus_bw_work_handler(struct work_struct *work) adapter->prev_rx_packets); if (adapter->device_mode == QDF_SAP_MODE || - adapter->device_mode == QDF_P2P_GO_MODE || - adapter->device_mode == QDF_IBSS_MODE) { + adapter->device_mode == QDF_P2P_GO_MODE || + adapter->device_mode == QDF_IBSS_MODE || + adapter->device_mode == QDF_NDI_MODE) { ret = cdp_get_intra_bss_fwd_pkts_count( cds_get_context(QDF_MODULE_ID_SOC), @@ -8302,12 +8712,12 @@ static void __hdd_bus_bw_work_handler(struct work_struct *work) total_rx += adapter->stats.rx_packets; total_tx += adapter->stats.tx_packets; - spin_lock_bh(&hdd_ctx->bus_bw_lock); + qdf_spin_lock_bh(&hdd_ctx->bus_bw_lock); adapter->prev_tx_packets = adapter->stats.tx_packets; adapter->prev_rx_packets = adapter->stats.rx_packets; adapter->prev_fwd_tx_packets = fwd_tx_packets; adapter->prev_fwd_rx_packets = fwd_rx_packets; - spin_unlock_bh(&hdd_ctx->bus_bw_lock); + qdf_spin_unlock_bh(&hdd_ctx->bus_bw_lock); connected = true; } @@ -8388,7 +8798,7 @@ int hdd_bus_bandwidth_init(struct hdd_context *hdd_ctx) { hdd_enter(); - spin_lock_init(&hdd_ctx->bus_bw_lock); + qdf_spinlock_create(&hdd_ctx->bus_bw_lock); INIT_WORK(&hdd_ctx->bus_bw_work, hdd_bus_bw_work_handler); hdd_ctx->bus_bw_timer_running = false; qdf_spinlock_create(&hdd_ctx->bus_bw_timer_lock); @@ -8408,10 +8818,37 @@ void hdd_bus_bandwidth_deinit(struct hdd_context *hdd_ctx) qdf_timer_free(&hdd_ctx->bus_bw_timer); qdf_spinlock_destroy(&hdd_ctx->bus_bw_timer_lock); + qdf_spinlock_destroy(&hdd_ctx->bus_bw_lock); hdd_exit(); } +void hdd_bus_bw_compute_prev_txrx_stats(struct hdd_adapter *adapter) +{ + struct hdd_context *hdd_ctx = WLAN_HDD_GET_CTX(adapter); + + qdf_spin_lock_bh(&hdd_ctx->bus_bw_lock); + adapter->prev_tx_packets = adapter->stats.tx_packets; + adapter->prev_rx_packets = adapter->stats.rx_packets; + cdp_get_intra_bss_fwd_pkts_count(cds_get_context(QDF_MODULE_ID_SOC), + adapter->session_id, + &adapter->prev_fwd_tx_packets, + &adapter->prev_fwd_rx_packets); + qdf_spin_unlock_bh(&hdd_ctx->bus_bw_lock); +} + +void hdd_bus_bw_compute_reset_prev_txrx_stats(struct hdd_adapter *adapter) +{ + struct hdd_context *hdd_ctx = WLAN_HDD_GET_CTX(adapter); + + qdf_spin_lock_bh(&hdd_ctx->bus_bw_lock); + adapter->prev_tx_packets = 0; + adapter->prev_rx_packets = 0; + adapter->prev_fwd_tx_packets = 0; + adapter->prev_fwd_rx_packets = 0; + qdf_spin_unlock_bh(&hdd_ctx->bus_bw_lock); +} + #endif /* MSM_PLATFORM */ /** @@ -9193,6 +9630,25 @@ static inline void hdd_lte_coex_restart_sap(struct hdd_adapter *adapter, } #endif /* defined(FEATURE_WLAN_CH_AVOID) */ +QDF_STATUS +wlan_hdd_get_adapter_by_vdev_id_from_objmgr(struct hdd_context *hdd_ctx, + struct hdd_adapter **adapter, + struct wlan_objmgr_vdev *vdev) +{ + *adapter = NULL; + if (!hdd_ctx) + return QDF_STATUS_E_INVAL; + + if (!vdev || !vdev->vdev_nif.osdev) { + hdd_err("null vdev object"); + return QDF_STATUS_E_INVAL; + } + + *adapter = vdev->vdev_nif.osdev->legacy_osif_priv; + + return QDF_STATUS_SUCCESS; +} + /** * hdd_indicate_mgmt_frame() - Wrapper to indicate management frame to * user space @@ -9208,9 +9664,12 @@ void hdd_indicate_mgmt_frame(tSirSmeMgmtFrameInd *frame_ind) { struct hdd_context *hdd_ctx = NULL; struct hdd_adapter *adapter = NULL; - int i; + int i, num_adapters; + uint8_t vdev_id[WLAN_MAX_VDEVS]; struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)frame_ind->frameBuf; + QDF_STATUS status; + struct wlan_objmgr_vdev *vdev; hdd_ctx = cds_get_context(QDF_MODULE_ID_HDD); if (wlan_hdd_validate_context(hdd_ctx)) @@ -9229,17 +9688,43 @@ void hdd_indicate_mgmt_frame(tSirSmeMgmtFrameInd *frame_ind) break; } } else if (SME_SESSION_ID_BROADCAST == frame_ind->sessionId) { - hdd_for_each_adapter(hdd_ctx, adapter) { - if ((NULL != adapter) && - (WLAN_HDD_ADAPTER_MAGIC == adapter->magic)) { - __hdd_indicate_mgmt_frame(adapter, - frame_ind->frame_len, - frame_ind->frameBuf, - frame_ind->frameType, - frame_ind->rxChan, - frame_ind->rxRssi); + num_adapters = 0; + hdd_for_each_adapter_dev_held(hdd_ctx, adapter) { + vdev_id[num_adapters] = adapter->session_id; + num_adapters++; + /* dev_put has to be done here */ + dev_put(adapter->dev); + } + + adapter = NULL; + + for (i = 0; i < num_adapters; i++) { + vdev = wlan_objmgr_get_vdev_by_id_from_psoc( + hdd_ctx->psoc, + vdev_id[i], + WLAN_OSIF_ID); + + if (!vdev) + continue; + + status = wlan_hdd_get_adapter_by_vdev_id_from_objmgr( + hdd_ctx, &adapter, vdev); + + if (QDF_IS_STATUS_ERROR(status) || !adapter) { + wlan_objmgr_vdev_release_ref(vdev, + WLAN_OSIF_ID); + continue; } + + __hdd_indicate_mgmt_frame(adapter, + frame_ind->frame_len, + frame_ind->frameBuf, + frame_ind->frameType, + frame_ind->rxChan, + frame_ind->rxRssi); + wlan_objmgr_vdev_release_ref(vdev, WLAN_OSIF_ID); } + adapter = NULL; } else { adapter = hdd_get_adapter_by_sme_session_id(hdd_ctx, @@ -9467,6 +9952,8 @@ static int hdd_context_init(struct hdd_context *hdd_ctx) if (ret) goto list_destroy; + hdd_rx_wake_lock_create(hdd_ctx); + ret = hdd_sap_context_init(hdd_ctx); if (ret) goto scan_destroy; @@ -9490,6 +9977,7 @@ static int hdd_context_init(struct hdd_context *hdd_ctx) scan_destroy: hdd_scan_context_destroy(hdd_ctx); + hdd_rx_wake_lock_destroy(hdd_ctx); list_destroy: qdf_list_destroy(&hdd_ctx->hdd_adapters); @@ -9626,7 +10114,7 @@ int hdd_trigger_psoc_idle_restart(struct hdd_context *hdd_ctx) if (hdd_ctx->driver_status == DRIVER_MODULES_ENABLED) { mutex_unlock(&hdd_ctx->iface_change_lock); hdd_psoc_idle_timer_stop(hdd_ctx); - hdd_info("Driver modules already Enabled"); + hdd_nofl_debug("Driver modules already Enabled"); return 0; } @@ -9773,6 +10261,8 @@ static struct hdd_context *hdd_context_create(struct device *dev) cds_set_context(QDF_MODULE_ID_HDD, hdd_ctx); + wlan_hdd_sar_timers_init(hdd_ctx); + hdd_exit(); return hdd_ctx; @@ -10069,6 +10559,18 @@ static int hdd_open_interfaces(struct hdd_context *hdd_ctx, bool rtnl_held) if (ret) goto err_close_adapters; + if (hdd_ctx->nan_seperate_vdev_supported && + wlan_hdd_nan_separate_iface_supported(hdd_ctx)) { + adapter = hdd_open_adapter(hdd_ctx, QDF_NAN_DISC_MODE, "wifi-aware%d", + wlan_hdd_get_intf_addr(hdd_ctx, + QDF_NAN_DISC_MODE), + NET_NAME_UNKNOWN, rtnl_held); + if (!adapter) { + hdd_err("Failed to create nan interface"); + goto err_close_adapters; + } + } + /* Open 802.11p Interface */ if (hdd_ctx->config->dot11p_mode == WLAN_HDD_11P_CONCURRENT) { ret = hdd_open_ocb_interface(hdd_ctx, rtnl_held); @@ -10262,8 +10764,10 @@ static int hdd_update_cds_config(struct hdd_context *hdd_ctx) cds_cfg->delay_before_vdev_stop = hdd_ctx->config->delay_before_vdev_stop; + cds_cfg->num_vdevs = hdd_ctx->config->num_vdevs; cds_cfg->enable_peer_unmap_conf_support = hdd_ctx->config->enable_peer_unmap_conf_support; + cds_cfg->bmiss_skip_full_scan = hdd_ctx->config->bmiss_skip_full_scan; hdd_ra_populate_cds_config(cds_cfg, hdd_ctx); cds_cfg->enable_tx_compl_tsf64 = @@ -10272,6 +10776,7 @@ static int hdd_update_cds_config(struct hdd_context *hdd_ctx) hdd_ctx->config->enable_three_way_coex_config_legacy; hdd_txrx_populate_cds_config(cds_cfg, hdd_ctx); hdd_nan_populate_cds_config(cds_cfg, hdd_ctx); + hdd_lpass_populate_cds_config(cds_cfg, hdd_ctx); cds_init_ini_config(cds_cfg); return 0; @@ -10875,6 +11380,7 @@ static int hdd_set_ani_enabled(struct hdd_context *hdd_ctx) static int hdd_pre_enable_configure(struct hdd_context *hdd_ctx) { int ret; + uint8_t max_retry = 0; QDF_STATUS status; void *soc = cds_get_context(QDF_MODULE_ID_SOC); @@ -10916,6 +11422,14 @@ static int hdd_pre_enable_configure(struct hdd_context *hdd_ctx) goto out; } + max_retry = hdd_ctx->config->mgmt_retry_max; + ret = sme_cli_set_command(0, WMI_PDEV_PARAM_MGMT_RETRY_LIMIT, max_retry, + PDEV_CMD); + if (0 != ret) { + hdd_err("WMI_PDEV_PARAM_MGMT_RETRY_LIMIT failed %d", ret); + goto out; + } + ret = hdd_set_smart_chainmask_enabled(hdd_ctx); if (ret) goto out; @@ -11171,6 +11685,21 @@ static int hdd_init_mws_coex(struct hdd_context *hdd_ctx) hdd_warn("Unable to send MWS-COEX 4G quick FTDM policy"); return ret; } + + ret = sme_cli_set_command( + 0, WMI_PDEV_PARAM_MWSCOEX_PCC_CHAVD_DELAY, + hdd_ctx->config->mws_coex_pcc_channel_avoid_delay, + PDEV_CMD); + if (ret) + return ret; + + ret = sme_cli_set_command( + 0, WMI_PDEV_PARAM_MWSCOEX_SCC_CHAVD_DELAY, + hdd_ctx->config->mws_coex_scc_channel_avoid_delay, + PDEV_CMD); + if (ret) + return ret; + return ret; } #else @@ -11732,7 +12261,7 @@ int hdd_wlan_stop_modules(struct hdd_context *hdd_ctx, bool ftm_mode) hdd_debug("Modules already closed"); goto done; case DRIVER_MODULES_ENABLED: - hdd_info("Wlan transitioning (CLOSED <- ENABLED)"); + hdd_debug("Wlan transitioning (CLOSED <- ENABLED)"); if (hdd_get_conparam() == QDF_GLOBAL_FTM_MODE) break; @@ -11847,7 +12376,7 @@ int hdd_wlan_stop_modules(struct hdd_context *hdd_ctx, bool ftm_mode) /* Once the firmware sequence is completed reset this flag */ hdd_ctx->imps_enabled = false; hdd_ctx->driver_status = DRIVER_MODULES_CLOSED; - hdd_info("Wlan transitioned (now CLOSED)"); + hdd_debug("Wlan transitioned (now CLOSED)"); done: hdd_ctx->stop_modules_in_progress = false; @@ -11964,6 +12493,8 @@ void hdd_dp_trace_init(struct hdd_config *config) uint8_t num_entries = 0; uint32_t bw_compute_interval; + qdf_dp_set_proto_event_bitmap(config->dp_proto_event_bitmap); + if (!config->enable_dp_trace) { hdd_err("dp trace is disabled from ini"); return; @@ -12358,6 +12889,10 @@ int hdd_register_cb(struct hdd_context *hdd_ctx) if (!QDF_IS_STATUS_SUCCESS(status)) hdd_err("Register tx queue callback failed"); + sme_set_oem_data_event_handler_cb(mac_handle, hdd_oem_event_handler_cb); + + sme_set_roam_scan_ch_event_cb(mac_handle, hdd_get_roam_scan_ch_cb); + hdd_exit(); return ret; @@ -12384,6 +12919,9 @@ void hdd_deregister_cb(struct hdd_context *hdd_ctx) } mac_handle = hdd_ctx->mac_handle; + + sme_reset_oem_data_event_handler_cb(mac_handle); + sme_deregister_tx_queue_cb(mac_handle); sme_reset_link_layer_stats_ind_cb(mac_handle); @@ -12477,10 +13015,8 @@ void wlan_hdd_disable_roaming(struct hdd_adapter *cur_adapter) struct csr_roam_profile *roam_profile; struct hdd_station_ctx *sta_ctx; - if (!policy_mgr_is_sta_active_connection_exists(hdd_ctx->psoc)) { - hdd_debug("No active sta session"); + if (!policy_mgr_is_sta_active_connection_exists(hdd_ctx->psoc)) return; - } hdd_for_each_adapter(hdd_ctx, adapter) { roam_profile = hdd_roam_profile(adapter); @@ -12504,10 +13040,8 @@ void wlan_hdd_enable_roaming(struct hdd_adapter *cur_adapter) struct csr_roam_profile *roam_profile; struct hdd_station_ctx *sta_ctx; - if (!policy_mgr_is_sta_active_connection_exists(hdd_ctx->psoc)) { - hdd_debug("No active sta session"); + if (!policy_mgr_is_sta_active_connection_exists(hdd_ctx->psoc)) return; - } hdd_for_each_adapter(hdd_ctx, adapter) { roam_profile = hdd_roam_profile(adapter); @@ -13352,8 +13886,20 @@ static QDF_STATUS hdd_component_init(void) if (QDF_IS_STATUS_ERROR(status)) goto oui_deinit; + status = ucfg_pkt_capture_init(); + if (QDF_IS_STATUS_ERROR(status)) + goto mlme_deinit; + + status = ucfg_ftm_time_sync_init(); + if (QDF_IS_STATUS_ERROR(status)) + goto pkt_capture_deinit; + return QDF_STATUS_SUCCESS; +pkt_capture_deinit: + ucfg_pkt_capture_deinit(); +mlme_deinit: + ucfg_mlme_deinit(); oui_deinit: ucfg_action_oui_deinit(); ipa_deinit: @@ -13378,6 +13924,8 @@ static QDF_STATUS hdd_component_init(void) static void hdd_component_deinit(void) { /* deinitialize non-converged components */ + ucfg_ftm_time_sync_deinit(); + ucfg_pkt_capture_deinit(); ucfg_mlme_deinit(); ucfg_action_oui_deinit(); ipa_deinit(); @@ -13503,14 +14051,14 @@ static void hdd_driver_unload(void) cds_set_driver_loaded(false); cds_set_unload_in_progress(true); - if (!cds_wait_for_external_threads_completion(__func__)) - hdd_warn("External threads are still active attempting " - "driver unload anyway"); - if (hdd_ctx) hdd_psoc_idle_timer_stop(hdd_ctx); wlan_hdd_unregister_driver(); + + if (hdd_ctx) + hdd_context_destroy(hdd_ctx); + pld_deinit(); wlan_hdd_state_ctrl_param_destroy(); hdd_set_conparam(0); @@ -14190,6 +14738,56 @@ static int hdd_update_pmo_config(struct hdd_context *hdd_ctx) return qdf_status_to_os_return(status); } +/** + * hdd_update_pkt_capture_config - Update packet capture config parameters + * @hdd_ctx: HDD context + * + * Return: 0 on success / error on failure + */ +static int hdd_update_pkt_capture_config(struct hdd_context *hdd_ctx) +{ + struct pkt_capture_cfg pkt_capture_cfg = {0}; + QDF_STATUS status; + + pkt_capture_cfg.pkt_capture_mode = hdd_ctx->config->pkt_capture_mode; + + status = ucfg_pkt_capture_psoc_config(hdd_ctx->psoc, &pkt_capture_cfg); + if (QDF_IS_STATUS_ERROR(status)) + hdd_err("packet capture config failed"); + + return qdf_status_to_os_return(status); +} + +#ifdef FEATURE_WLAN_TIME_SYNC_FTM +/** + * hdd_update_time_sync_ftm_config - Update time sync ftm config parameters + * @hdd_ctx: HDD context + * + * Return: 0 on success / error on failure + */ +static int hdd_update_time_sync_ftm_config(struct hdd_context *hdd_ctx) +{ + struct ftm_time_sync_cfg ftm_time_sync_cfg = {0}; + QDF_STATUS status; + + ftm_time_sync_cfg.enable = hdd_ctx->config->time_sync_ftm_enable; + ftm_time_sync_cfg.mode = hdd_ctx->config->time_sync_ftm_mode; + ftm_time_sync_cfg.role = hdd_ctx->config->time_sync_ftm_role; + + status = ucfg_ftm_time_sync_psoc_config(hdd_ctx->psoc, + &ftm_time_sync_cfg); + if (QDF_IS_STATUS_ERROR(status)) + hdd_err("ftm time sync config failed"); + + return qdf_status_to_os_return(status); +} +#else +static inline int hdd_update_time_sync_ftm_config(struct hdd_context *hdd_ctx) +{ + return 0; +} +#endif + #ifdef FEATURE_WLAN_SCAN_PNO static inline void hdd_update_pno_config(struct pno_user_cfg *pno_cfg, struct hdd_config *cfg) @@ -14517,6 +15115,18 @@ int hdd_update_components_config(struct hdd_context *hdd_ctx) return ret; ret = hdd_update_dfs_config(hdd_ctx); + if (ret) + return ret; + + ret = hdd_update_regulatory_config(hdd_ctx); + if (ret) + return ret; + + ret = hdd_update_pkt_capture_config(hdd_ctx); + if (ret) + return ret; + + ret = hdd_update_time_sync_ftm_config(hdd_ctx); return ret; } @@ -14609,129 +15219,164 @@ bool hdd_is_roaming_in_progress(struct hdd_context *hdd_ctx) return false; } - hdd_debug("roaming_in_progress = %d", hdd_ctx->roaming_in_progress); + if (hdd_ctx->roaming_in_progress) + hdd_debug("Roaming is in progress"); return hdd_ctx->roaming_in_progress; } /** - * hdd_is_connection_in_progress() - check if connection is in - * progress - * @session_id: session id - * @reason: scan reject reason + * struct hdd_is_connection_in_progress_priv - adapter connection info + * @out_vdev_id: id of vdev where connection is occurring + * @out_reason: scan reject reason + */ +struct hdd_is_connection_in_progress_priv { + uint8_t out_vdev_id; + enum scan_reject_states out_reason; + bool connection_in_progress; +}; + +/** + * hdd_is_connection_in_progress_iterator() - Check adapter connection based + * on device mode + * @adapter: current adapter of interest + * @context: user context supplied * - * Go through each adapter and check if Connection is in progress + * Check if connection is in progress for the current adapter according to the + * device mode * - * Return: true if connection is in progress else false + * Return: + * * QDF_STATUS_SUCCESS if iteration should continue + * * QDF_STATUS_E_ABORTED if iteration should be aborted */ -bool hdd_is_connection_in_progress(uint8_t *session_id, - enum scan_reject_states *reason) +static QDF_STATUS hdd_is_connection_in_progress_iterator( + struct hdd_adapter *adapter, + void *ctx) { - struct hdd_station_ctx *hdd_sta_ctx = NULL; - struct hdd_adapter *adapter = NULL; + struct hdd_station_ctx *hdd_sta_ctx; uint8_t sta_id = 0; - uint8_t *sta_mac = NULL; + uint8_t *sta_mac; struct hdd_context *hdd_ctx; mac_handle_t mac_handle; + struct hdd_is_connection_in_progress_priv *context = ctx; hdd_ctx = cds_get_context(QDF_MODULE_ID_HDD); if (!hdd_ctx) { hdd_err("HDD context is NULL"); - return false; + return QDF_STATUS_E_ABORTED; } mac_handle = hdd_ctx->mac_handle; - hdd_for_each_adapter(hdd_ctx, adapter) { - hdd_debug("Adapter with device mode %s(%d) exists", - hdd_device_mode_to_string(adapter->device_mode), - adapter->device_mode); - if (((QDF_STA_MODE == adapter->device_mode) - || (QDF_P2P_CLIENT_MODE == adapter->device_mode) - || (QDF_P2P_DEVICE_MODE == adapter->device_mode)) - && (eConnectionState_Connecting == - (WLAN_HDD_GET_STATION_CTX_PTR(adapter))-> - conn_info.connState)) { - hdd_debug("%pK(%d) Connection is in progress", - WLAN_HDD_GET_STATION_CTX_PTR(adapter), - adapter->session_id); - if (session_id && reason) { - *session_id = adapter->session_id; - *reason = CONNECTION_IN_PROGRESS; - } - return true; - } - /* - * sme_neighbor_middle_of_roaming is for LFR2 - * hdd_is_roaming_in_progress is for LFR3 - */ - if (((QDF_STA_MODE == adapter->device_mode) && - sme_neighbor_middle_of_roaming( - mac_handle, - adapter->session_id)) || - hdd_is_roaming_in_progress(hdd_ctx)) { - hdd_debug("%pK(%d) Reassociation in progress", - WLAN_HDD_GET_STATION_CTX_PTR(adapter), - adapter->session_id); - if (session_id && reason) { - *session_id = adapter->session_id; - *reason = REASSOC_IN_PROGRESS; - } - return true; + if (((QDF_STA_MODE == adapter->device_mode) + || (QDF_P2P_CLIENT_MODE == adapter->device_mode) + || (QDF_P2P_DEVICE_MODE == adapter->device_mode)) + && (eConnectionState_Connecting == + (WLAN_HDD_GET_STATION_CTX_PTR(adapter))-> + conn_info.connState)) { + hdd_debug("%pK(%d) mode %d Connection is in progress", + WLAN_HDD_GET_STATION_CTX_PTR(adapter), + adapter->session_id, adapter->device_mode); + + context->out_vdev_id = adapter->session_id; + context->out_reason = CONNECTION_IN_PROGRESS; + context->connection_in_progress = true; + + return QDF_STATUS_E_ABORTED; + } + /* + * sme_neighbor_middle_of_roaming is for LFR2 + * hdd_is_roaming_in_progress is for LFR3 + */ + if (((QDF_STA_MODE == adapter->device_mode) && + sme_neighbor_middle_of_roaming( + mac_handle, + adapter->session_id)) || + hdd_is_roaming_in_progress(hdd_ctx)) { + hdd_debug("%pK(%d) mode %d Reassociation in progress", + WLAN_HDD_GET_STATION_CTX_PTR(adapter), + adapter->session_id, adapter->device_mode); + + context->out_vdev_id = adapter->session_id; + context->out_reason = REASSOC_IN_PROGRESS; + context->connection_in_progress = true; + return QDF_STATUS_E_ABORTED; + } + + if ((QDF_STA_MODE == adapter->device_mode) || + (QDF_P2P_CLIENT_MODE == adapter->device_mode) || + (QDF_P2P_DEVICE_MODE == adapter->device_mode)) { + hdd_sta_ctx = + WLAN_HDD_GET_STATION_CTX_PTR(adapter); + if ((eConnectionState_Associated == + hdd_sta_ctx->conn_info.connState) + && sme_is_sta_key_exchange_in_progress( + mac_handle, adapter->session_id)) { + sta_mac = (uint8_t *)&(adapter->mac_addr.bytes[0]); + hdd_debug("client " QDF_MAC_ADDR_STR + " is in middle of WPS/EAPOL exchange.", + QDF_MAC_ADDR_ARRAY(sta_mac)); + + context->out_vdev_id = adapter->session_id; + context->out_reason = EAPOL_IN_PROGRESS; + context->connection_in_progress = true; + + return QDF_STATUS_E_ABORTED; + } + } else if ((QDF_SAP_MODE == adapter->device_mode) || + (QDF_P2P_GO_MODE == adapter->device_mode)) { + for (sta_id = 0; sta_id < WLAN_MAX_STA_COUNT; sta_id++) { + if (!((adapter->sta_info[sta_id].in_use) + && (OL_TXRX_PEER_STATE_CONN == + adapter->sta_info[sta_id].peer_state))) + continue; + + sta_mac = (uint8_t *) + &(adapter->sta_info[sta_id]. + sta_mac.bytes[0]); + hdd_debug("client " QDF_MAC_ADDR_STR + " of SAP/GO is in middle of WPS/EAPOL exchange", + QDF_MAC_ADDR_ARRAY(sta_mac)); + + context->out_vdev_id = adapter->session_id; + context->out_reason = SAP_EAPOL_IN_PROGRESS; + context->connection_in_progress = true; + return QDF_STATUS_E_ABORTED; } - if ((QDF_STA_MODE == adapter->device_mode) || - (QDF_P2P_CLIENT_MODE == adapter->device_mode) || - (QDF_P2P_DEVICE_MODE == adapter->device_mode)) { - hdd_sta_ctx = - WLAN_HDD_GET_STATION_CTX_PTR(adapter); - if ((eConnectionState_Associated == - hdd_sta_ctx->conn_info.connState) - && sme_is_sta_key_exchange_in_progress( - mac_handle, adapter->session_id)) { - sta_mac = (uint8_t *) - &(adapter->mac_addr.bytes[0]); - hdd_debug("client " MAC_ADDRESS_STR - " is in middle of WPS/EAPOL exchange.", - MAC_ADDR_ARRAY(sta_mac)); - if (session_id && reason) { - *session_id = adapter->session_id; - *reason = EAPOL_IN_PROGRESS; - } - return true; - } - } else if ((QDF_SAP_MODE == adapter->device_mode) || - (QDF_P2P_GO_MODE == adapter->device_mode)) { - for (sta_id = 0; sta_id < WLAN_MAX_STA_COUNT; - sta_id++) { - if (!((adapter->sta_info[sta_id].in_use) - && (OL_TXRX_PEER_STATE_CONN == - adapter->sta_info[sta_id].peer_state))) - continue; - - sta_mac = (uint8_t *) - &(adapter->sta_info[sta_id]. - sta_mac.bytes[0]); - hdd_debug("client " MAC_ADDRESS_STR - " of SAP/GO is in middle of WPS/EAPOL exchange", - MAC_ADDR_ARRAY(sta_mac)); - if (session_id && reason) { - *session_id = adapter->session_id; - *reason = SAP_EAPOL_IN_PROGRESS; - } - return true; - } - if (hdd_ctx->connection_in_progress) { - hdd_debug("AP/GO: connection is in progress"); - if (session_id && reason) { - *reason = SAP_CONNECTION_IN_PROGRESS; - *session_id = adapter->session_id; - } - return true; - } + + if (hdd_ctx->connection_in_progress) { + hdd_debug("AP/GO: vdev %d connection is in progress", + adapter->session_id); + context->out_reason = SAP_CONNECTION_IN_PROGRESS; + context->out_vdev_id = adapter->session_id; + context->connection_in_progress = true; + return QDF_STATUS_E_ABORTED; } } - return false; + return QDF_STATUS_SUCCESS; +} + +bool hdd_is_connection_in_progress(uint8_t *out_vdev_id, + enum scan_reject_states *out_reason) +{ + struct hdd_is_connection_in_progress_priv hdd_conn; + hdd_adapter_iterate_cb cb; + + hdd_conn.out_vdev_id = 0; + hdd_conn.out_reason = SCAN_REJECT_DEFAULT; + hdd_conn.connection_in_progress = false; + + cb = hdd_is_connection_in_progress_iterator; + + hdd_adapter_iterate(cb, &hdd_conn); + + if (hdd_conn.connection_in_progress && out_vdev_id && out_reason) { + *out_vdev_id = hdd_conn.out_vdev_id; + *out_reason = hdd_conn.out_reason; + } + + return hdd_conn.connection_in_progress; } /** @@ -14856,6 +15501,9 @@ void hdd_check_and_restart_sap_with_non_dfs_acs(void) test_bit(SOFTAP_BSS_STARTED, &ap_adapter->event_flags) && wlan_reg_is_dfs_ch(hdd_ctx->pdev, ap_adapter->session.ap.operating_channel)) { + if (policy_mgr_get_dfs_master_dynamic_enabled( + hdd_ctx->psoc, ap_adapter->session_id)) + return; hdd_warn("STA-AP Mode DFS not supported, Switch SAP channel to Non DFS"); @@ -15373,6 +16021,195 @@ void hdd_hidden_ssid_enable_roaming(hdd_handle_t hdd_handle, uint8_t vdev_id) wlan_hdd_enable_roaming(adapter); } +#ifdef WLAN_FEATURE_PKT_CAPTURE + +/** + * wlan_hdd_is_session_type_monitor() - check if session type is MONITOR + * @session_type: session type + * + * Return: True - if session type for adapter is monitor, else False + * + */ +bool wlan_hdd_is_session_type_monitor(uint8_t session_type) +{ + struct hdd_context *hdd_ctx = cds_get_context(QDF_MODULE_ID_HDD); + + if (!hdd_ctx) { + cds_err("HDD context is NULL"); + return false; + } + + if (ucfg_pkt_capture_get_mode(hdd_ctx->psoc) && + cds_get_conparam() != QDF_GLOBAL_MONITOR_MODE && + session_type == QDF_MONITOR_MODE) + return true; + else + return false; +} + +/** + * wlan_hdd_check_mon_concurrency() - check if MONITOR and STA concurrency + * is UP when packet capture mode is enabled. + * @void + * + * Return: True - if STA and monitor concurrency is there, else False + * + */ +bool wlan_hdd_check_mon_concurrency(void) +{ + struct hdd_context *hdd_ctx = cds_get_context(QDF_MODULE_ID_HDD); + + if (!hdd_ctx) { + hdd_err("HDD context is null"); + return -EINVAL; + } + + if (ucfg_pkt_capture_get_mode(hdd_ctx->psoc)) { + if (policy_mgr_get_concurrency_mode(hdd_ctx->psoc) == + (QDF_STA_MASK | QDF_MONITOR_MASK)) { + hdd_err("STA + MON mode is UP"); + return true; + } + } + return false; +} + +/** + * wlan_hdd_del_monitor() - delete monitor interface + * @hdd_ctx: pointer to hdd context + * @adapter: adapter to be deleted + * @rtnl_held: rtnl lock held + * + * This function is invoked to delete monitor interface. + * + * Return: None + */ +void wlan_hdd_del_monitor(struct hdd_context *hdd_ctx, + struct hdd_adapter *adapter, bool rtnl_held) +{ + ucfg_pkt_capture_deregister_callbacks(adapter->vdev); + wlan_hdd_release_intf_addr(hdd_ctx, adapter->mac_addr.bytes); + hdd_stop_adapter(hdd_ctx, adapter); + hdd_close_adapter(hdd_ctx, adapter, true); + + if (adapter->vdev) { + hdd_objmgr_put_vdev(adapter->vdev); + adapter->vdev = NULL; + } + + hdd_open_p2p_interface(hdd_ctx, rtnl_held); +} + +/** + * wlan_hdd_add_monitor_check() - check for monitor intf and add if needed + * @hdd_ctx: pointer to hdd context + * @adapter: output pointer to hold created monitor adapter + * @type: type of the interface + * @name: name of the interface + * @rtnl_held: True if RTNL lock is held + * @name_assign_type: the name of assign type of the netdev + * + * Return: 0 - on success + * err code - on failure + */ +int +wlan_hdd_add_monitor_check(struct hdd_context *hdd_ctx, + struct hdd_adapter **adapter, + enum nl80211_iftype type, const char *name, + bool rtnl_held, unsigned char name_assign_type) +{ + struct hdd_adapter *sta_adapter; + struct hdd_adapter *mon_adapter; + uint32_t mode; + uint8_t num_open_session = 0; + QDF_STATUS status; + + if (!ucfg_pkt_capture_get_mode(hdd_ctx->psoc)) + return 0; + + /* + * If add interface request is for monitor mode, then it can run in + * parallel with only one station interface. + * If there is no existing station interface return error + */ + if (type != NL80211_IFTYPE_MONITOR) + return 0; + + status = policy_mgr_mode_specific_num_open_sessions(hdd_ctx->psoc, + QDF_MONITOR_MODE, + &num_open_session); + if (QDF_IS_STATUS_ERROR(status)) + return -EINVAL; + + if (num_open_session) { + hdd_err("monitor mode already exists, only one is possible"); + return -EBUSY; + } + + /* Ensure there is only one station interface */ + status = policy_mgr_mode_specific_num_open_sessions(hdd_ctx->psoc, + QDF_STA_MODE, + &num_open_session); + if (QDF_IS_STATUS_ERROR(status)) + return -EINVAL; + + if (num_open_session != 1) { + hdd_err("cannot add monitor mode, due to %u sta interfaces", + num_open_session); + return -EINVAL; + } + + sta_adapter = hdd_get_adapter(hdd_ctx, QDF_STA_MODE); + if (!sta_adapter) { + hdd_err("No station adapter"); + return -EINVAL; + } + + status = policy_mgr_mode_specific_num_open_sessions(hdd_ctx->psoc, + QDF_SAP_MODE, + &num_open_session); + if (QDF_IS_STATUS_ERROR(status)) + return -EINVAL; + + if (num_open_session) { + hdd_err("cannot add monitor mode, due to SAP concurrency"); + return -EINVAL; + } + + /* delete p2p interface */ + for (mode = QDF_P2P_CLIENT_MODE; mode <= QDF_P2P_DEVICE_MODE; mode++) { + struct hdd_adapter *adapter; + + if (mode == QDF_FTM_MODE || + mode == QDF_MONITOR_MODE || + mode == QDF_IBSS_MODE) + continue; + + adapter = hdd_get_adapter(hdd_ctx, mode); + if (adapter) { + wlan_hdd_release_intf_addr(hdd_ctx, + adapter->mac_addr.bytes); + hdd_stop_adapter(hdd_ctx, adapter); + hdd_deinit_adapter(hdd_ctx, adapter, true); + hdd_close_adapter(hdd_ctx, adapter, rtnl_held); + } + } + + mon_adapter = hdd_open_adapter(hdd_ctx, QDF_MONITOR_MODE, name, + wlan_hdd_get_intf_addr( + hdd_ctx, + QDF_MONITOR_MODE), + name_assign_type, rtnl_held); + if (!mon_adapter) { + hdd_err("hdd_open_adapter failed"); + hdd_open_p2p_interface(hdd_ctx, rtnl_held); + return -EINVAL; + } + + *adapter = mon_adapter; + return 0; +} +#endif /* WLAN_FEATURE_PKT_CAPTURE */ /* Register the module init/exit functions */ module_init(hdd_module_init); module_exit(hdd_module_exit); diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_nan_datapath.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_nan_datapath.c index 185b13fac512..2c03c9caa083 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_nan_datapath.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_nan_datapath.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -36,6 +36,7 @@ #include "os_if_nan.h" #include "wlan_nan_api.h" #include "nan_public_structs.h" +#include /** * hdd_ndp_print_ini_config()- Print nan datapath specific INI configuration @@ -372,7 +373,7 @@ static int __wlan_hdd_cfg80211_process_ndp_cmd(struct wiphy *wiphy, } if (!WLAN_HDD_IS_NDP_ENABLED(hdd_ctx)) { - hdd_err_rl("NAN datapath is not enabled"); + hdd_debug("NAN datapath is not enabled"); return -EPERM; } /* NAN data path coexists only with STA interface */ @@ -646,13 +647,28 @@ int hdd_ndi_delete(uint8_t vdev_id, char *iface_name, uint16_t transaction_id) return ret; } +#ifdef WLAN_FEATURE_NAN +static void hdd_nan_config_keep_alive_period(uint8_t vdev_id, + struct hdd_context *hdd_ctx) +{ + sme_cli_set_command(vdev_id, WMI_VDEV_PARAM_NDP_KEEPALIVE_TIMEOUT, + hdd_ctx->config->ndp_keep_alive_period, VDEV_CMD); +} +#else +static inline void hdd_nan_config_keep_alive_period( + uint8_t vdev_id, + struct hdd_context *hdd_ctx) +{ +} +#endif + void hdd_ndi_drv_ndi_create_rsp_handler(uint8_t vdev_id, struct nan_datapath_inf_create_rsp *ndi_rsp) { struct hdd_context *hdd_ctx; struct hdd_adapter *adapter; struct hdd_station_ctx *sta_ctx; - struct csr_roam_info roam_info = {0}; + struct csr_roam_info *roam_info; struct bss_description tmp_bss_descp = {0}; struct qdf_mac_addr bc_mac_addr = QDF_MAC_ADDR_BCAST_INIT; uint8_t sta_id; @@ -681,6 +697,10 @@ void hdd_ndi_drv_ndi_create_rsp_handler(uint8_t vdev_id, return; } + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return; + if (ndi_rsp->status == QDF_STATUS_SUCCESS) { hdd_alert("NDI interface successfully created"); os_if_nan_set_ndp_create_transaction_id(adapter->vdev, 0); @@ -689,6 +709,13 @@ void hdd_ndi_drv_ndi_create_rsp_handler(uint8_t vdev_id, wlan_hdd_netif_queue_control(adapter, WLAN_START_ALL_NETIF_QUEUE_N_CARRIER, WLAN_CONTROL_PATH); + + sme_cli_set_command(vdev_id, + WMI_VDEV_PARAM_NDP_INACTIVITY_TIMEOUT, + hdd_ctx->config->ndp_inactivity_timeout, + VDEV_CMD); + + hdd_nan_config_keep_alive_period(vdev_id, hdd_ctx); } else { hdd_alert("NDI interface creation failed with reason %d", ndi_rsp->reason /* create_reason */); @@ -696,9 +723,10 @@ void hdd_ndi_drv_ndi_create_rsp_handler(uint8_t vdev_id, sta_ctx->broadcast_staid = sta_id; hdd_save_peer(sta_ctx, sta_id, &bc_mac_addr); - hdd_roam_register_sta(adapter, &roam_info, sta_id, + hdd_roam_register_sta(adapter, roam_info, sta_id, &bc_mac_addr, &tmp_bss_descp); hdd_ctx->sta_to_adapter[sta_id] = adapter; + qdf_mem_free(roam_info); } void hdd_ndi_close(uint8_t vdev_id) @@ -789,7 +817,7 @@ int hdd_ndp_new_peer_handler(uint8_t vdev_id, uint16_t sta_id, struct hdd_adapter *adapter; struct hdd_station_ctx *sta_ctx; struct bss_description tmp_bss_descp = {0}; - struct csr_roam_info roam_info = {0}; + struct csr_roam_info *roam_info; hdd_enter(); @@ -822,23 +850,29 @@ int hdd_ndp_new_peer_handler(uint8_t vdev_id, uint16_t sta_id, return -EPERM; } + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return -ENOMEM; + /* this function is called for each new peer */ - hdd_roam_register_sta(adapter, &roam_info, sta_id, - peer_mac_addr, &tmp_bss_descp); + hdd_roam_register_sta(adapter, roam_info, sta_id, + peer_mac_addr, &tmp_bss_descp); hdd_ctx->sta_to_adapter[sta_id] = adapter; /* perform following steps for first new peer ind */ if (fist_peer) { hdd_info("Set ctx connection state to connected"); + hdd_bus_bw_compute_prev_txrx_stats(adapter); + hdd_bus_bw_compute_timer_start(hdd_ctx); sta_ctx->conn_info.connState = eConnectionState_NdiConnected; - hdd_wmm_connect(adapter, &roam_info, eCSR_BSS_TYPE_NDI); + hdd_wmm_connect(adapter, roam_info, eCSR_BSS_TYPE_NDI); wlan_hdd_netif_queue_control(adapter, WLAN_WAKE_ALL_NETIF_QUEUE, WLAN_CONTROL_PATH); } + qdf_mem_free(roam_info); hdd_exit(); return 0; } - /** * hdd_ndp_peer_departed_handler() - Handle NDP peer departed indication * @adapter: pointer to adapter context @@ -890,6 +924,8 @@ void hdd_ndp_peer_departed_handler(uint8_t vdev_id, uint16_t sta_id, hdd_info("Stop netif tx queues."); wlan_hdd_netif_queue_control(adapter, WLAN_STOP_ALL_NETIF_QUEUE, WLAN_CONTROL_PATH); + hdd_bus_bw_compute_reset_prev_txrx_stats(adapter); + hdd_bus_bw_compute_timer_try_stop(hdd_ctx); } hdd_exit(); diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_nud_tracking.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_nud_tracking.c index ca589861543a..d4145f858a04 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_nud_tracking.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_nud_tracking.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018, 2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -68,8 +68,15 @@ void hdd_nud_flush_work(struct hdd_adapter *adapter) void hdd_nud_deinit_tracking(struct hdd_adapter *adapter) { - hdd_debug("DeInitialize the NUD tracking"); - qdf_destroy_work(NULL, &adapter->nud_tracking.nud_event_work); + struct hdd_context *hdd_ctx; + + hdd_ctx = WLAN_HDD_GET_CTX(adapter); + + if (adapter->device_mode == QDF_STA_MODE && + hdd_ctx->config->enable_nud_tracking) { + hdd_debug("DeInitialize the NUD tracking"); + qdf_destroy_work(NULL, &adapter->nud_tracking.nud_event_work); + } } void hdd_nud_ignore_tracking(struct hdd_adapter *adapter, bool ignoring) @@ -277,7 +284,8 @@ static void __hdd_nud_failure_work(void *data) hdd_debug("Disconnecting STA with session id: %d", adapter->session_id); /* Issue Disconnect */ - status = wlan_hdd_disconnect(adapter, eCSR_DISCONNECT_REASON_DEAUTH); + status = wlan_hdd_disconnect(adapter, eCSR_DISCONNECT_REASON_DEAUTH, + eSIR_MAC_GATEWAY_REACHABILITY_FAILURE); if (0 != status) { hdd_err("wlan_hdd_disconnect failed, status: %d", status); hdd_set_disconnect_status(adapter, false); diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_object_manager.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_object_manager.c index 8e52a0dc9653..71526833626e 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_object_manager.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_object_manager.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -327,7 +327,7 @@ struct wlan_objmgr_vdev *__hdd_objmgr_get_vdev(struct hdd_adapter *adapter, qdf_spin_unlock_bh(&adapter->vdev_lock); if (!vdev) - hdd_err("VDEV is NULL (via %s)", func); + hdd_debug("VDEV is NULL (via %s)", func); return vdev; } diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_oemdata.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_oemdata.c index 40f32e20f382..0356f7f55759 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_oemdata.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_oemdata.c @@ -16,8 +16,6 @@ * PERFORMANCE OF THIS SOFTWARE. */ -#ifdef FEATURE_OEM_DATA_SUPPORT - /** * DOC: wlan_hdd_oemdata.c * @@ -25,6 +23,7 @@ * */ +#if defined(FEATURE_OEM_DATA_SUPPORT) || defined(FEATURE_OEM_DATA) #include #include #include @@ -37,7 +36,9 @@ #include "wma.h" #include "sme_api.h" #include "wlan_nlink_srv.h" +#include "wlan_hdd_oemdata.h" +#ifdef FEATURE_OEM_DATA_SUPPORT #ifdef CNSS_GENL #include #endif @@ -361,7 +362,7 @@ static QDF_STATUS oem_process_data_req_msg(int oem_data_len, char *oem_data) oem_data_req.data_len = oem_data_len; qdf_mem_copy(oem_data_req.data, oem_data, oem_data_len); - status = sme_oem_data_req(p_hdd_ctx->mac_handle, &oem_data_req); + status = sme_oem_req_cmd(p_hdd_ctx->mac_handle, &oem_data_req); qdf_mem_free(oem_data_req.data); oem_data_req.data = NULL; @@ -1127,3 +1128,118 @@ int oem_deactivate_service(void) #endif #endif + +#ifdef FEATURE_OEM_DATA +static const struct nla_policy +oem_data_attr_policy[QCA_WLAN_VENDOR_ATTR_OEM_DATA_PARAMS_MAX + 1] = { + [QCA_WLAN_VENDOR_ATTR_OEM_DATA_CMD_DATA] = { + .type = NLA_BINARY, + .len = OEM_DATA_MAX_SIZE + }, +}; + +void hdd_oem_event_handler_cb(const struct oem_data *oem_event_data) +{ + struct sk_buff *vendor_event; + uint32_t len; + int ret; + struct hdd_context *hdd_ctx = cds_get_context(QDF_MODULE_ID_HDD); + + hdd_enter(); + + ret = wlan_hdd_validate_context(hdd_ctx); + if (ret) + return; + + len = nla_total_size(oem_event_data->data_len) + NLMSG_HDRLEN; + vendor_event = + cfg80211_vendor_event_alloc( + hdd_ctx->wiphy, NULL, len, + QCA_NL80211_VENDOR_SUBCMD_OEM_DATA_INDEX, + GFP_KERNEL); + + if (!vendor_event) { + hdd_err("cfg80211_vendor_event_alloc failed"); + return; + } + + ret = nla_put(vendor_event, QCA_WLAN_VENDOR_ATTR_OEM_DATA_CMD_DATA, + oem_event_data->data_len, oem_event_data->data); + if (ret) { + hdd_err("OEM event put fails status %d", ret); + kfree_skb(vendor_event); + return; + } + + cfg80211_vendor_event(vendor_event, GFP_KERNEL); + + hdd_exit(); +} + +/** + * __wlan_hdd_cfg80211_oem_data_handler() - the handler for oem data + * @wiphy: wiphy structure pointer + * @wdev: Wireless device structure pointer + * @data: Pointer to the data received + * @data_len: Length of @data + * + * Return: 0 on success; errno on failure + */ +static int +__wlan_hdd_cfg80211_oem_data_handler(struct wiphy *wiphy, + struct wireless_dev *wdev, + const void *data, int data_len) +{ + struct net_device *dev = wdev->netdev; + QDF_STATUS status; + int ret; + struct oem_data oem_data = {0}; + struct hdd_adapter *adapter = WLAN_HDD_GET_PRIV_PTR(dev); + struct hdd_context *hdd_ctx = WLAN_HDD_GET_CTX(adapter); + struct nlattr *tb[QCA_WLAN_VENDOR_ATTR_OEM_DATA_PARAMS_MAX + 1]; + + ret = wlan_hdd_validate_context(hdd_ctx); + if (ret) + return ret; + + if (wlan_cfg80211_nla_parse(tb, + QCA_WLAN_VENDOR_ATTR_OEM_DATA_PARAMS_MAX, + data, data_len, oem_data_attr_policy)) { + hdd_err("Invalid attributes"); + return -EINVAL; + } + + if (!tb[QCA_WLAN_VENDOR_ATTR_OEM_DATA_CMD_DATA]) { + hdd_err("oem data is missing!"); + return -EINVAL; + } + + oem_data.data_len = + nla_len(tb[QCA_WLAN_VENDOR_ATTR_OEM_DATA_CMD_DATA]); + if (!oem_data.data_len) { + hdd_err("oem data len is 0!"); + return -EINVAL; + } + + oem_data.vdev_id = adapter->session_id; + oem_data.data = nla_data(tb[QCA_WLAN_VENDOR_ATTR_OEM_DATA_CMD_DATA]); + + status = sme_oem_data_cmd(hdd_ctx->mac_handle, &oem_data); + + return qdf_status_to_os_return(status); +} + +int wlan_hdd_cfg80211_oem_data_handler(struct wiphy *wiphy, + struct wireless_dev *wdev, + const void *data, int data_len) +{ + int ret; + + cds_ssr_protect(__func__); + ret = __wlan_hdd_cfg80211_oem_data_handler(wiphy, wdev, + data, data_len); + cds_ssr_unprotect(__func__); + return ret; +} +#endif +#endif diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_p2p.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_p2p.c index d1e3cbbcc44d..9f4467270833 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_p2p.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_p2p.c @@ -644,6 +644,9 @@ struct wireless_dev *__wlan_hdd_add_virtual_intf(struct wiphy *wiphy, if (0 != ret) return ERR_PTR(ret); + if (wlan_hdd_check_mon_concurrency()) + return ERR_PTR(-EINVAL); + qdf_mtrace(QDF_MODULE_ID_HDD, QDF_MODULE_ID_HDD, TRACE_CODE_HDD_ADD_VIRTUAL_INTF, NO_SESSION, type); /* @@ -670,13 +673,22 @@ struct wireless_dev *__wlan_hdd_add_virtual_intf(struct wiphy *wiphy, wlan_abort_scan(hdd_ctx->pdev, INVAL_PDEV_ID, adapter->session_id, INVALID_SCAN_ID, false); - hdd_debug("Abort Scan while adding virtual interface"); } if (vdev) hdd_objmgr_put_vdev(vdev); } + adapter = NULL; + ret = wlan_hdd_add_monitor_check(hdd_ctx, &adapter, type, name, + true, name_assign_type); + if (ret) + return ERR_PTR(-EINVAL); + if (adapter) { + hdd_exit(); + return adapter->dev->ieee80211_ptr; + } + if (session_type == QDF_SAP_MODE) { struct wireless_dev *sap_dev; bool allow_add_sap = wlan_hdd_allow_sap_add(hdd_ctx, name, @@ -857,6 +869,9 @@ int __wlan_hdd_del_virtual_intf(struct wiphy *wiphy, struct wireless_dev *wdev) if (adapter->device_mode == QDF_SAP_MODE && wlan_sap_is_pre_cac_active(hdd_ctx->mac_handle)) { hdd_clean_up_pre_cac_interface(hdd_ctx); + } else if (wlan_hdd_is_session_type_monitor( + adapter->device_mode)) { + wlan_hdd_del_monitor(hdd_ctx, adapter, TRUE); } else { wlan_hdd_release_intf_addr(hdd_ctx, adapter->mac_addr.bytes); @@ -1319,6 +1334,8 @@ int wlan_hdd_set_mcc_p2p_quota(struct hdd_adapter *adapter, int32_t ret = 0; uint32_t concurrent_state; struct hdd_context *hdd_ctx; + uint32_t sta_cli_bit_mask = QDF_STA_MASK | QDF_P2P_CLIENT_MASK; + uint32_t sta_go_bit_mask = QDF_STA_MASK | QDF_P2P_GO_MASK; if (!adapter) { hdd_err("Invalid adapter"); @@ -1336,9 +1353,8 @@ int wlan_hdd_set_mcc_p2p_quota(struct hdd_adapter *adapter, * Check if concurrency mode is active. * Need to modify this code to support MCC modes other than STA/P2P */ - if ((concurrent_state == - (QDF_STA_MASK | QDF_P2P_CLIENT_MASK)) || - (concurrent_state == (QDF_STA_MASK | QDF_P2P_GO_MASK))) { + if (((concurrent_state & sta_cli_bit_mask) == sta_cli_bit_mask) || + ((concurrent_state & sta_go_bit_mask) == sta_go_bit_mask)) { hdd_info("STA & P2P are both enabled"); /* @@ -1355,7 +1371,6 @@ int wlan_hdd_set_mcc_p2p_quota(struct hdd_adapter *adapter, set_value = set_first_connection_operating_channel( hdd_ctx, set_value, adapter->device_mode); - set_value = set_second_connection_operating_channel( hdd_ctx, set_value, adapter->session_id); @@ -1378,6 +1393,8 @@ void wlan_hdd_set_mcc_latency(struct hdd_adapter *adapter, int set_value) { uint32_t concurrent_state; struct hdd_context *hdd_ctx; + uint32_t sta_cli_bit_mask = QDF_STA_MASK | QDF_P2P_CLIENT_MASK; + uint32_t sta_go_bit_mask = QDF_STA_MASK | QDF_P2P_GO_MASK; if (!adapter) { hdd_err("Invalid adapter"); @@ -1396,9 +1413,8 @@ void wlan_hdd_set_mcc_latency(struct hdd_adapter *adapter, int set_value) * Check if concurrency mode is active. * Need to modify this code to support MCC modes other than STA/P2P */ - if ((concurrent_state == - (QDF_STA_MASK | QDF_P2P_CLIENT_MASK)) || - (concurrent_state == (QDF_STA_MASK | QDF_P2P_GO_MASK))) { + if (((concurrent_state & sta_cli_bit_mask) == sta_cli_bit_mask) || + ((concurrent_state & sta_go_bit_mask) == sta_go_bit_mask)) { hdd_info("STA & P2P are both enabled"); /* * The channel number and latency are formatted in diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_power.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_power.c index 035fc259398f..2b84849c1f1a 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_power.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_power.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -77,6 +77,8 @@ #include "wlan_ipa_ucfg_api.h" #include #include "wlan_p2p_ucfg_api.h" +#include "wlan_osif_request_manager.h" +#include "wlan_pkt_capture_ucfg_api.h" /* Preprocessor definitions and constants */ #ifdef QCA_WIFI_NAPIER_EMULATION @@ -373,6 +375,13 @@ void hdd_enable_ns_offload(struct hdd_adapter *adapter, ns_req->trigger = trigger; ns_req->count = 0; + /* check if offload cache and send is required or not */ + status = ucfg_pmo_ns_offload_check(psoc, trigger, adapter->session_id); + if (QDF_IS_STATUS_ERROR(status)) { + hdd_info("NS offload is not required"); + goto free_req; + } + /* Unicast Addresses */ errno = hdd_fill_ipv6_uc_addr(in6_dev, ns_req->ipv6_addr, ns_req->ipv6_addr_type, ns_req->scope, @@ -420,9 +429,19 @@ void hdd_disable_ns_offload(struct hdd_adapter *adapter, enum pmo_offload_trigger trigger) { QDF_STATUS status; + struct hdd_context *hdd_ctx = WLAN_HDD_GET_CTX(adapter); hdd_enter(); + + status = ucfg_pmo_ns_offload_check(hdd_ctx->psoc, trigger, + adapter->session_id); + if (status != QDF_STATUS_SUCCESS) { + hdd_err("Flushing of NS offload not required"); + goto out; + } + status = pmo_ucfg_flush_ns_offload_req(adapter->vdev); + if (status != QDF_STATUS_SUCCESS) { hdd_err("Failed to flush NS Offload"); goto out; @@ -864,18 +883,20 @@ void hdd_enable_arp_offload(struct hdd_adapter *adapter, struct pmo_arp_req *arp_req; struct in_ifaddr *ifa; - hdd_enter(); - arp_req = qdf_mem_malloc(sizeof(*arp_req)); - if (!arp_req) { - hdd_err("cannot allocate arp_req"); - goto out; - } + if (!arp_req) + return; arp_req->psoc = psoc; arp_req->vdev_id = adapter->session_id; arp_req->trigger = trigger; + status = ucfg_pmo_check_arp_offload(psoc, trigger, adapter->session_id); + if (QDF_IS_STATUS_ERROR(status)) { + hdd_info("ARP offload not required"); + goto free_req; + } + ifa = hdd_get_ipv4_local_interface(adapter); if (!ifa || !ifa->ifa_local) { hdd_info("IP Address is not assigned"); @@ -901,21 +922,25 @@ void hdd_enable_arp_offload(struct hdd_adapter *adapter, free_req: qdf_mem_free(arp_req); - -out: - hdd_exit(); } void hdd_disable_arp_offload(struct hdd_adapter *adapter, enum pmo_offload_trigger trigger) { QDF_STATUS status; + struct hdd_context *hdd_ctx = WLAN_HDD_GET_CTX(adapter); + + status = ucfg_pmo_check_arp_offload(hdd_ctx->psoc, trigger, + adapter->session_id); + if (status != QDF_STATUS_SUCCESS) { + hdd_debug("Flushing of ARP offload not required"); + return; + } - hdd_enter(); status = pmo_ucfg_flush_arp_offload_req(adapter->vdev); if (status != QDF_STATUS_SUCCESS) { hdd_err("Failed to flush arp Offload"); - goto out; + return; } status = pmo_ucfg_disable_arp_offload_in_fwr(adapter->vdev, @@ -925,8 +950,6 @@ void hdd_disable_arp_offload(struct hdd_adapter *adapter, PMO_OFFLOAD_DISABLE); else hdd_info("fail to disable arp offload"); -out: - hdd_exit(); } void hdd_enable_mc_addr_filtering(struct hdd_adapter *adapter, @@ -935,22 +958,18 @@ void hdd_enable_mc_addr_filtering(struct hdd_adapter *adapter, struct hdd_context *hdd_ctx = WLAN_HDD_GET_CTX(adapter); QDF_STATUS status; - hdd_enter(); - if (wlan_hdd_validate_context(hdd_ctx)) - goto out; + return; if (!hdd_adapter_is_connected_sta(adapter)) - goto out; + return; status = pmo_ucfg_enable_mc_addr_filtering_in_fwr(hdd_ctx->psoc, adapter->session_id, trigger); if (QDF_IS_STATUS_ERROR(status)) - hdd_err("failed to enable mc list; status:%d", status); + hdd_debug("failed to enable mc list; status:%d", status); -out: - hdd_exit(); } void hdd_disable_mc_addr_filtering(struct hdd_adapter *adapter, @@ -959,31 +978,24 @@ void hdd_disable_mc_addr_filtering(struct hdd_adapter *adapter, struct hdd_context *hdd_ctx = WLAN_HDD_GET_CTX(adapter); QDF_STATUS status; - hdd_enter(); - if (wlan_hdd_validate_context(hdd_ctx)) - goto out; + return; if (!hdd_adapter_is_connected_sta(adapter)) - goto out; + return; status = pmo_ucfg_disable_mc_addr_filtering_in_fwr(hdd_ctx->psoc, adapter->session_id, trigger); if (QDF_IS_STATUS_ERROR(status)) hdd_err("failed to disable mc list; status:%d", status); - -out: - hdd_exit(); } int hdd_cache_mc_addr_list(struct pmo_mc_addr_list_params *mc_list_config) { QDF_STATUS status; - hdd_enter(); status = pmo_ucfg_cache_mc_addr_list(mc_list_config); - hdd_exit(); return qdf_status_to_os_return(status); } @@ -994,8 +1006,6 @@ void hdd_disable_and_flush_mc_addr_list(struct hdd_adapter *adapter, struct hdd_context *hdd_ctx = WLAN_HDD_GET_CTX(adapter); QDF_STATUS status; - hdd_enter(); - if (!hdd_adapter_is_connected_sta(adapter)) goto flush_mc_list; @@ -1004,17 +1014,13 @@ void hdd_disable_and_flush_mc_addr_list(struct hdd_adapter *adapter, adapter->session_id, trigger); if (QDF_IS_STATUS_ERROR(status)) - hdd_err("failed to disable mc list; status:%d", status); + hdd_debug("failed to disable mc list; status:%d", status); flush_mc_list: status = pmo_ucfg_flush_mc_addr_list(hdd_ctx->psoc, adapter->session_id); if (QDF_IS_STATUS_ERROR(status)) hdd_err("failed to flush mc list; status:%d", status); - - hdd_exit(); - - return; } /** @@ -1094,6 +1100,9 @@ hdd_suspend_wlan(void) return -EAGAIN; hdd_ctx->hdd_wlan_suspended = true; + + hdd_configure_sar_sleep_index(hdd_ctx); + hdd_wlan_suspend_resume_event(HDD_WLAN_EARLY_SUSPEND); return 0; @@ -1152,6 +1161,8 @@ static int hdd_resume_wlan(void) if (QDF_IS_STATUS_ERROR(status)) return qdf_status_to_os_return(status); + hdd_configure_sar_resume_index(hdd_ctx); + return 0; } @@ -1242,6 +1253,7 @@ static void hdd_purge_all_pdev_cmd(struct hdd_context *hdd_ctx) QDF_STATUS hdd_wlan_shutdown(void) { struct hdd_context *hdd_ctx; + struct hdd_adapter *adapter; void *soc = cds_get_context(QDF_MODULE_ID_SOC); hdd_info("WLAN driver shutting down!"); @@ -1274,6 +1286,11 @@ QDF_STATUS hdd_wlan_shutdown(void) } #endif + if (ucfg_pkt_capture_get_mode(hdd_ctx->psoc)) { + adapter = hdd_get_adapter(hdd_ctx, QDF_MONITOR_MODE); + if (adapter) + ucfg_pkt_capture_resume_mon_thread(adapter->vdev); + } /* * After SSR, FW clear its txrx stats. In host, * as adapter is intact so those counts are still @@ -1629,6 +1646,7 @@ static int __wlan_hdd_cfg80211_resume_wlan(struct wiphy *wiphy) { struct hdd_context *hdd_ctx = wiphy_priv(wiphy); QDF_STATUS status = QDF_STATUS_SUCCESS; + struct hdd_adapter *adapter; int exit_code; p_cds_sched_context cds_sched_context = get_cds_sched_ctxt(); @@ -1646,13 +1664,8 @@ static int __wlan_hdd_cfg80211_resume_wlan(struct wiphy *wiphy) goto exit_with_code; } - exit_code = wlan_hdd_validate_context(hdd_ctx); - if (exit_code) { - hdd_err("Invalid HDD context"); - goto exit_with_code; - } - mutex_lock(&hdd_ctx->iface_change_lock); + if (hdd_ctx->driver_status != DRIVER_MODULES_ENABLED) { mutex_unlock(&hdd_ctx->iface_change_lock); hdd_debug("Driver is not enabled; Skipping resume"); @@ -1673,6 +1686,14 @@ static int __wlan_hdd_cfg80211_resume_wlan(struct wiphy *wiphy) scheduler_resume(); hdd_ctx->is_scheduler_suspended = false; } + /* Resume all components registered to pmo */ + status = ucfg_pmo_resume_all_components(hdd_ctx->psoc, + QDF_SYSTEM_SUSPEND); + if (status != QDF_STATUS_SUCCESS) { + exit_code = 0; + goto exit_with_code; + } + #ifdef QCA_CONFIG_SMP /* Resume tlshim Rx thread */ if (hdd_ctx->is_ol_rx_thread_suspended) { @@ -1680,6 +1701,11 @@ static int __wlan_hdd_cfg80211_resume_wlan(struct wiphy *wiphy) hdd_ctx->is_ol_rx_thread_suspended = false; } #endif + if (ucfg_pkt_capture_get_mode(hdd_ctx->psoc)) { + adapter = hdd_get_adapter(hdd_ctx, QDF_MONITOR_MODE); + if (adapter) + ucfg_pkt_capture_resume_mon_thread(adapter->vdev); + } qdf_mtrace(QDF_MODULE_ID_HDD, QDF_MODULE_ID_HDD, TRACE_CODE_HDD_CFG80211_RESUME_WLAN, @@ -1807,15 +1833,21 @@ static int __wlan_hdd_cfg80211_suspend_wlan(struct wiphy *wiphy, /* flush any pending powersave timers */ hdd_for_each_adapter(hdd_ctx, adapter) { - wlan_abort_scan(hdd_ctx->pdev, INVAL_PDEV_ID, - adapter->session_id, INVALID_SCAN_ID, false); - if (wlan_hdd_validate_session_id(adapter->session_id)) continue; - sme_ps_timer_flush_sync(mac_handle, adapter->session_id); } + /* + * Suspend all components registered to pmo, abort ongoing scan and + * don't allow new scan any more before scheduler thread suspended. + */ + if (ucfg_pmo_suspend_all_components(hdd_ctx->psoc, + QDF_SYSTEM_SUSPEND)) { + hdd_err("Some components not ready to suspend!"); + return -EAGAIN; + } + /* * Suspend IPA early before proceeding to suspend other entities like * firmware to avoid any race conditions. @@ -1857,6 +1889,12 @@ static int __wlan_hdd_cfg80211_suspend_wlan(struct wiphy *wiphy, } hdd_ctx->is_ol_rx_thread_suspended = true; #endif + if (ucfg_pkt_capture_get_mode(hdd_ctx->psoc)) { + adapter = hdd_get_adapter(hdd_ctx, QDF_MONITOR_MODE); + if (adapter) + if (ucfg_pkt_capture_suspend_mon_thread(adapter->vdev)) + goto resume_pkt_capture_mon_thread; + } qdf_mtrace(QDF_MODULE_ID_HDD, QDF_MODULE_ID_HDD, TRACE_CODE_HDD_CFG80211_SUSPEND_WLAN, @@ -1864,7 +1902,7 @@ static int __wlan_hdd_cfg80211_suspend_wlan(struct wiphy *wiphy, if (hdd_suspend_wlan() < 0) { hdd_err("Failed to suspend WLAN"); - goto resume_all; + goto resume_pkt_capture_mon_thread; } hdd_ctx->is_wiphy_suspended = true; @@ -1874,6 +1912,14 @@ static int __wlan_hdd_cfg80211_suspend_wlan(struct wiphy *wiphy, hdd_exit(); return 0; +resume_pkt_capture_mon_thread: + /* Resume packet capture MON thread */ + if (ucfg_pkt_capture_get_mode(hdd_ctx->psoc)) { + adapter = hdd_get_adapter(hdd_ctx, QDF_MONITOR_MODE); + if (adapter) + ucfg_pkt_capture_resume_mon_thread(adapter->vdev); + } + #ifdef QCA_CONFIG_SMP resume_all: /* Resume tlshim Rx thread */ @@ -2148,6 +2194,7 @@ int wlan_hdd_cfg80211_set_txpower(struct wiphy *wiphy, #ifdef QCA_SUPPORT_CP_STATS static void wlan_hdd_get_tx_power(struct hdd_adapter *adapter, int *dbm) + { wlan_cfg80211_mc_cp_stats_get_tx_power(adapter->vdev, dbm); } @@ -2158,6 +2205,114 @@ static void wlan_hdd_get_tx_power(struct hdd_adapter *adapter, int *dbm) *dbm = adapter->hdd_stats.class_a_stat.max_pwr; } #endif + +#ifdef FEATURE_ANI_LEVEL_REQUEST +static void hdd_get_ani_level_cb(struct wmi_host_ani_level_event *ani, + uint8_t num, void *context) +{ + struct osif_request *request; + struct ani_priv *priv; + uint8_t min_recv_freqs = QDF_MIN(num, MAX_NUM_FREQS_FOR_ANI_LEVEL); + + request = osif_request_get(context); + if (!request) { + hdd_err("Obsolete request"); + return; + } + + /* propagate response back to requesting thread */ + priv = osif_request_priv(request); + priv->ani = qdf_mem_malloc(min_recv_freqs * + sizeof(struct wmi_host_ani_level_event)); + if (!priv->ani) + goto complete; + + priv->num_freq = min_recv_freqs; + qdf_mem_copy(priv->ani, ani, + min_recv_freqs * sizeof(struct wmi_host_ani_level_event)); + +complete: + osif_request_complete(request); + osif_request_put(request); +} + +/** + * wlan_hdd_get_ani_level_dealloc() - Dealloc mem allocated in priv data + * @priv: the priv data + * + * Return: None + */ +static void wlan_hdd_get_ani_level_dealloc(void *priv) +{ + struct ani_priv *ani = priv; + + if (ani->ani) + qdf_mem_free(ani->ani); +} + +QDF_STATUS wlan_hdd_get_ani_level(struct hdd_adapter *adapter, + struct wmi_host_ani_level_event *ani, + uint32_t *parsed_freqs, + uint8_t num_freqs) +{ + struct hdd_context *hdd_ctx = WLAN_HDD_GET_CTX(adapter); + int ret; + QDF_STATUS status; + void *cookie; + struct osif_request *request; + struct ani_priv *priv; + static const struct osif_request_params params = { + .priv_size = sizeof(*priv), + .timeout_ms = 1000, + .dealloc = wlan_hdd_get_ani_level_dealloc, + }; + + if (!hdd_ctx) { + hdd_err("Invalid HDD context"); + return QDF_STATUS_E_INVAL; + } + + request = osif_request_alloc(¶ms); + if (!request) { + hdd_err("Request allocation failure"); + return QDF_STATUS_E_NOMEM; + } + cookie = osif_request_cookie(request); + + status = sme_get_ani_level(hdd_ctx->mac_handle, parsed_freqs, + num_freqs, hdd_get_ani_level_cb, cookie); + + if (QDF_IS_STATUS_ERROR(status)) { + hdd_err("Unable to retrieve ani level"); + goto complete; + } else { + /* request was sent -- wait for the response */ + ret = osif_request_wait_for_response(request); + if (ret) { + hdd_err("SME timed out while retrieving ANI level"); + status = QDF_STATUS_E_TIMEOUT; + goto complete; + } + } + + priv = osif_request_priv(request); + + qdf_mem_copy(ani, priv->ani, sizeof(struct wmi_host_ani_level_event) * + priv->num_freq); + +complete: + /* + * either we never sent a request, we sent a request and + * received a response or we sent a request and timed out. + * regardless we are done with the request. + */ + osif_request_put(request); + + hdd_exit(); + return status; +} +#endif + /** * __wlan_hdd_cfg80211_get_txpower() - get TX power * @wiphy: Pointer to wiphy diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_regulatory.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_regulatory.c index ce74ca22e628..c97fc2cddd5d 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_regulatory.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_regulatory.c @@ -794,7 +794,8 @@ int hdd_reg_set_band(struct net_device *dev, u8 ui_band) status = sme_roam_disconnect( mac_handle, adapter->session_id, - eCSR_DISCONNECT_REASON_UNSPECIFIED); + eCSR_DISCONNECT_REASON_UNSPECIFIED, + eSIR_MAC_OPER_CHANNEL_BAND_CHANGE); if (QDF_STATUS_SUCCESS != status) { hdd_err("sme_roam_disconnect failure, status: %d", @@ -1363,21 +1364,26 @@ static void hdd_regulatory_dyn_cbk(struct wlan_objmgr_psoc *psoc, hdd_ctx->reg.alpha2); } +int hdd_update_regulatory_config(struct hdd_context *hdd_ctx) +{ + struct reg_config_vars config_vars; + + reg_program_config_vars(hdd_ctx, &config_vars); + ucfg_reg_set_config_vars(hdd_ctx->psoc, config_vars); + return 0; +} + int hdd_regulatory_init(struct hdd_context *hdd_ctx, struct wiphy *wiphy) { bool offload_enabled; - struct reg_config_vars config_vars; struct regulatory_channel cur_chan_list[NUM_CHANNELS]; enum country_src cc_src; uint8_t alpha2[REG_ALPHA2_LEN + 1]; - reg_program_config_vars(hdd_ctx, &config_vars); ucfg_reg_register_chan_change_callback(hdd_ctx->psoc, hdd_regulatory_dyn_cbk, NULL); - ucfg_reg_set_config_vars(hdd_ctx->psoc, config_vars); - wiphy->regulatory_flags |= REGULATORY_WIPHY_SELF_MANAGED; /* Check the kernel version for upstream commit aced43ce780dc5 that * has support for processing user cell_base hints when wiphy is diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_scan.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_scan.c index b7d93cd43672..28d0af2afc8a 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_scan.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_scan.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -481,8 +481,6 @@ static int __wlan_hdd_cfg80211_scan(struct wiphy *wiphy, struct scan_params params = {0}; struct wlan_objmgr_vdev *vdev; - hdd_enter(); - if (cds_is_fw_down()) { hdd_err("firmware is down, scan cmd cannot be processed"); return -EINVAL; @@ -518,10 +516,6 @@ static int __wlan_hdd_cfg80211_scan(struct wiphy *wiphy, return 0; } - hdd_debug("Device_mode %s(%d)", - hdd_device_mode_to_string(adapter->device_mode), - adapter->device_mode); - /* * IBSS vdev does not need to scan to establish * IBSS connection. If IBSS vdev need to support scan, @@ -692,7 +686,7 @@ static int __wlan_hdd_cfg80211_scan(struct wiphy *wiphy, error: if (params.default_ie.ptr) qdf_mem_free(params.default_ie.ptr); - hdd_exit(); + return status; } @@ -1295,11 +1289,15 @@ static int __wlan_hdd_cfg80211_sched_scan_start(struct wiphy *wiphy, struct hdd_context *hdd_ctx; struct wlan_objmgr_vdev *vdev; int ret; + enum QDF_GLOBAL_MODE curr_mode; hdd_enter(); - if (QDF_GLOBAL_FTM_MODE == hdd_get_conparam()) { - hdd_err("Command not allowed in FTM mode"); + curr_mode = hdd_get_conparam(); + + if (QDF_GLOBAL_FTM_MODE == curr_mode || + QDF_GLOBAL_MONITOR_MODE == curr_mode) { + hdd_err_rl("Command not allowed in FTM/Monitor mode"); return -EINVAL; } @@ -1410,11 +1408,15 @@ static int __wlan_hdd_cfg80211_sched_scan_stop(struct net_device *dev) { struct hdd_adapter *adapter = WLAN_HDD_GET_PRIV_PTR(dev); int errno; + enum QDF_GLOBAL_MODE curr_mode; hdd_enter(); - if (QDF_GLOBAL_FTM_MODE == hdd_get_conparam()) { - hdd_err_rl("Command not allowed in FTM mode"); + curr_mode = hdd_get_conparam(); + + if (QDF_GLOBAL_FTM_MODE == curr_mode || + QDF_GLOBAL_MONITOR_MODE == curr_mode) { + hdd_err_rl("Command not allowed in FTM/Monitor mode"); return -EINVAL; } diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_scan.h b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_scan.h index bcc874b43be3..63d93d30ed43 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_scan.h +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_scan.h @@ -30,6 +30,8 @@ #include "csr_inside_api.h" #include +#define EXTSCAN_PARAM_MAX QCA_WLAN_VENDOR_ATTR_EXTSCAN_SUBCMD_CONFIG_PARAM_MAX + #define MAX_PENDING_LOG 5 /* (30 Mins) */ @@ -144,5 +146,86 @@ void hdd_reset_scan_reject_params(struct hdd_context *hdd_ctx, * Return: none */ void wlan_hdd_cfg80211_scan_block_cb(struct work_struct *work); + +static const struct nla_policy wlan_hdd_extscan_config_policy +[QCA_WLAN_VENDOR_ATTR_EXTSCAN_SUBCMD_CONFIG_PARAM_MAX + 1] = { + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_SUBCMD_CONFIG_PARAM_REQUEST_ID] = { + .type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_GET_VALID_CHANNELS_CONFIG_PARAM_WIFI_BAND] = { + .type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_GET_VALID_CHANNELS_CONFIG_PARAM_MAX_CHANNELS] = { + .type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_CHANNEL_SPEC_CHANNEL] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_CHANNEL_SPEC_DWELL_TIME] = { + .type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_CHANNEL_SPEC_PASSIVE] = {.type = NLA_U8}, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_CHANNEL_SPEC_CLASS] = {.type = NLA_U8}, + + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_BUCKET_SPEC_INDEX] = {.type = NLA_U8}, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_BUCKET_SPEC_BAND] = {.type = NLA_U8}, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_BUCKET_SPEC_PERIOD] = {.type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_BUCKET_SPEC_REPORT_EVENTS] = { + .type = NLA_U8}, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_BUCKET_SPEC_NUM_CHANNEL_SPECS] = { + .type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_SCAN_CMD_PARAMS_BASE_PERIOD] = { + .type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_SCAN_CMD_PARAMS_MAX_AP_PER_SCAN] = { + .type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_SCAN_CMD_PARAMS_REPORT_THRESHOLD_PERCENT] = { + .type = NLA_U8}, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_SCAN_CMD_PARAMS_REPORT_THRESHOLD_NUM_SCANS] = { + .type = NLA_U8 }, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_SCAN_CMD_PARAMS_NUM_BUCKETS] = { + .type = NLA_U8}, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_GET_CACHED_SCAN_RESULTS_CONFIG_PARAM_FLUSH] = { + .type = NLA_U8}, + + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_GET_CACHED_SCAN_RESULTS_CONFIG_PARAM_MAX] = { + .type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_AP_THRESHOLD_PARAM_BSSID] = { + .type = NLA_UNSPEC, + .len = QDF_MAC_ADDR_SIZE}, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_AP_THRESHOLD_PARAM_RSSI_LOW] = { + .type = NLA_S32}, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_AP_THRESHOLD_PARAM_RSSI_HIGH] = { + .type = NLA_S32}, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_AP_THRESHOLD_PARAM_CHANNEL] = { + .type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_BSSID_HOTLIST_PARAMS_NUM_AP] = { + .type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_SIGNIFICANT_CHANGE_PARAMS_RSSI_SAMPLE_SIZE] = { + .type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_SIGNIFICANT_CHANGE_PARAMS_LOST_AP_SAMPLE_SIZE] = { + .type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_SIGNIFICANT_CHANGE_PARAMS_MIN_BREACHING] = { + .type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_SIGNIFICANT_CHANGE_PARAMS_NUM_AP] = { + .type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_BUCKET_SPEC_MAX_PERIOD] = { + .type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_BUCKET_SPEC_BASE] = { + .type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_BUCKET_SPEC_STEP_COUNT] = { + .type = NLA_U32}, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_SSID_THRESHOLD_PARAM_SSID] = { + .type = NLA_BINARY, + .len = IEEE80211_MAX_SSID_LEN + 1 }, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_SSID_HOTLIST_PARAMS_LOST_SSID_SAMPLE_SIZE] = { + .type = NLA_U32 }, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_SSID_HOTLIST_PARAMS_NUM_SSID] = { + .type = NLA_U32 }, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_SSID_THRESHOLD_PARAM_BAND] = { + .type = NLA_U8 }, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_SSID_THRESHOLD_PARAM_RSSI_LOW] = { + .type = NLA_S32 }, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_SSID_THRESHOLD_PARAM_RSSI_HIGH] = { + .type = NLA_S32 }, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_CONFIGURATION_FLAGS] = { + .type = NLA_U32 }, + [QCA_WLAN_VENDOR_ATTR_EXTSCAN_BSSID_HOTLIST_PARAMS_LOST_AP_SAMPLE_SIZE] = { + .type = NLA_U32}, +}; + #endif /* end #if !defined(WLAN_HDD_SCAN_H) */ diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_softap_tx_rx.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_softap_tx_rx.c index 65a69290f1a4..5f1d26d4b1a0 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_softap_tx_rx.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_softap_tx_rx.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -286,6 +286,8 @@ int hdd_post_dhcp_ind(struct hdd_adapter *adapter, return 0; } +#define DHCP_CLIENT_MAC_ADDR_OFFSET 0x46 + /** * hdd_softap_notify_dhcp_ind() - Notify SAP for DHCP indication for tx desc * @context: pointer to HDD context @@ -309,32 +311,24 @@ static void hdd_softap_notify_dhcp_ind(void *context, struct sk_buff *netbuf) return; } - dest_mac_addr = (struct qdf_mac_addr *)netbuf->data; + dest_mac_addr = (struct qdf_mac_addr *)(netbuf->data + + DHCP_CLIENT_MAC_ADDR_OFFSET); - if (QDF_NBUF_CB_GET_IS_BCAST(netbuf) || - QDF_NBUF_CB_GET_IS_MCAST(netbuf)) { - /* The BC/MC station ID is assigned during BSS - * starting phase. SAP will return the station ID - * used for BC/MC traffic. - */ - sta_id = hdd_ap_ctx->broadcast_sta_id; - } else { - if (QDF_STATUS_SUCCESS != + if (QDF_STATUS_SUCCESS != hdd_softap_get_sta_id(adapter, dest_mac_addr, &sta_id)) { - QDF_TRACE(QDF_MODULE_ID_HDD_SAP_DATA, - QDF_TRACE_LEVEL_INFO_HIGH, - "%s: Failed to find right station", __func__); - return; - } + QDF_TRACE(QDF_MODULE_ID_HDD_SAP_DATA, + QDF_TRACE_LEVEL_INFO_HIGH, + "%s: Failed to find right station", __func__); + return; } + hdd_post_dhcp_ind(adapter, sta_id, WMA_DHCP_STOP_IND); } /** - * hdd_inspect_dhcp_packet() - Inspect DHCP packet + * hdd_softap_inspect_dhcp_packet() - Inspect DHCP packet * @adapter: pointer to hdd adapter - * @sta_id: peer station ID * @skb: pointer to OS packet (sk_buff) * @dir: direction * @@ -359,21 +353,17 @@ static void hdd_softap_notify_dhcp_ind(void *context, struct sk_buff *netbuf) * * Return: error number */ -int hdd_inspect_dhcp_packet(struct hdd_adapter *adapter, - uint8_t sta_id, - struct sk_buff *skb, - enum qdf_proto_dir dir) +int hdd_softap_inspect_dhcp_packet(struct hdd_adapter *adapter, + struct sk_buff *skb, + enum qdf_proto_dir dir) { enum qdf_proto_subtype subtype = QDF_PROTO_INVALID; struct hdd_station_info *hdd_sta_info; + uint8_t sta_id; int errno = 0; + struct qdf_mac_addr *src_mac; + QDF_STATUS status; - //hdd_debug("sta_id=%d, dir=%d", sta_id, dir); - - if (sta_id >= WLAN_MAX_STA_COUNT) { - hdd_err("Invalid sta id: %d", sta_id); - return -EINVAL; - } if (((adapter->device_mode == QDF_SAP_MODE) || (adapter->device_mode == QDF_P2P_GO_MODE)) && @@ -381,6 +371,14 @@ int hdd_inspect_dhcp_packet(struct hdd_adapter *adapter, QDF_NBUF_CB_GET_PACKET_TYPE(skb)) || (dir == QDF_RX && qdf_nbuf_is_ipv4_dhcp_pkt(skb) == true))) { + src_mac = (struct qdf_mac_addr *)(skb->data + + DHCP_CLIENT_MAC_ADDR_OFFSET); + status = hdd_softap_get_sta_id(adapter, src_mac, &sta_id); + if (status != QDF_STATUS_SUCCESS) { + hdd_err("invalid station id"); + return -EINVAL; + } + subtype = qdf_nbuf_get_dhcp_subtype(skb); hdd_sta_info = &adapter->sta_info[sta_id]; @@ -602,8 +600,7 @@ static netdev_tx_t __hdd_softap_hard_start_xmit(struct sk_buff *skb, QDF_NBUF_CB_TX_EXTRA_FRAG_FLAGS_NOTIFY_COMP(skb) = 0; - if (sta_id != ap_ctx->broadcast_sta_id) - hdd_inspect_dhcp_packet(adapter, sta_id, skb, QDF_TX); + hdd_softap_inspect_dhcp_packet(adapter, skb, QDF_TX); hdd_event_eapol_log(skb, QDF_TX); QDF_NBUF_CB_TX_PACKET_TRACK(skb) = QDF_NBUF_TX_PKT_DATA_TRACK; @@ -633,6 +630,7 @@ static netdev_tx_t __hdd_softap_hard_start_xmit(struct sk_buff *skb, goto drop_pkt_and_release_skb; } netif_trans_update(dev); + wlan_hdd_sar_unsolicited_timer_start(adapter->hdd_ctx); return NETDEV_TX_OK; @@ -933,8 +931,8 @@ QDF_STATUS hdd_softap_rx_packet_cbk(void *context, qdf_nbuf_t rx_buf) adapter->sta_info[staid].rx_bytes += skb->len; adapter->sta_info[staid].last_tx_rx_ts = qdf_system_ticks(); - hdd_inspect_dhcp_packet(adapter, staid, - skb, QDF_RX); + hdd_softap_inspect_dhcp_packet(adapter, skb, + QDF_RX); } } @@ -951,6 +949,19 @@ QDF_STATUS hdd_softap_rx_packet_cbk(void *context, qdf_nbuf_t rx_buf) skb->protocol = eth_type_trans(skb, skb->dev); + /* hold configurable wakelock for unicast traffic */ + if (!hdd_is_current_high_throughput(hdd_ctx) && + hdd_ctx->config->rx_wakelock_timeout && + skb->pkt_type != PACKET_BROADCAST && + skb->pkt_type != PACKET_MULTICAST) { + cds_host_diag_log_work(&hdd_ctx->rx_wake_lock, + hdd_ctx->config->rx_wakelock_timeout, + WIFI_POWER_EVENT_WAKELOCK_HOLD_RX); + qdf_wake_lock_timeout_acquire(&hdd_ctx->rx_wake_lock, + hdd_ctx->config-> + rx_wakelock_timeout); + } + /* Remove SKB from internal tracking table before submitting * it to stack */ @@ -968,10 +979,15 @@ QDF_STATUS hdd_softap_rx_packet_cbk(void *context, qdf_nbuf_t rx_buf) hdd_ctx->no_rx_offload_pkt_cnt++; - if (NET_RX_SUCCESS == rxstat) + if (NET_RX_SUCCESS == rxstat) { ++adapter->hdd_stats.tx_rx_stats.rx_delivered[cpu_index]; - else + } else { ++adapter->hdd_stats.tx_rx_stats.rx_refused[cpu_index]; + DPTRACE(qdf_dp_log_proto_pkt_info(NULL, NULL, 0, 0, + QDF_RX, + QDF_TRACE_DEFAULT_MSDU_ID, + QDF_TX_RX_STATUS_DROP)); + } } return QDF_STATUS_SUCCESS; @@ -1009,8 +1025,8 @@ QDF_STATUS hdd_softap_deregister_sta(struct hdd_adapter *adapter, (struct cdp_pdev *)cds_get_context(QDF_MODULE_ID_TXRX), sta_id); if (!QDF_IS_STATUS_SUCCESS(qdf_status)) { - hdd_err("cdp_clear_peer failed for staID %d, Status=%d [0x%08X]", - sta_id, qdf_status, qdf_status); + hdd_debug("cdp_clear_peer failed for staID %d, Status=%d [0x%08X]", + sta_id, qdf_status, qdf_status); } if (adapter->sta_info[sta_id].in_use) { @@ -1022,7 +1038,7 @@ QDF_STATUS hdd_softap_deregister_sta(struct hdd_adapter *adapter, WLAN_IPA_CLIENT_DISCONNECT, adapter->sta_info[sta_id].sta_mac. bytes) != QDF_STATUS_SUCCESS) - hdd_err("WLAN_CLIENT_DISCONNECT event failed"); + hdd_debug("WLAN_CLIENT_DISCONNECT event failed"); } spin_lock_bh(&adapter->sta_info_lock); qdf_mem_zero(&adapter->sta_info[sta_id], @@ -1030,6 +1046,8 @@ QDF_STATUS hdd_softap_deregister_sta(struct hdd_adapter *adapter, spin_unlock_bh(&adapter->sta_info_lock); } + hdd_softap_deinit_tx_rx_sta(adapter, sta_id); + hdd_ctx->sta_to_adapter[sta_id] = NULL; sme_config = qdf_mem_malloc(sizeof(*sme_config)); @@ -1072,7 +1090,7 @@ QDF_STATUS hdd_softap_register_sta(struct hdd_adapter *adapter, * Clean up old entry if it is not cleaned up properly */ if (adapter->sta_info[sta_id].in_use) { - hdd_info("clean up old entry for STA %d", sta_id); + hdd_debug("clean up old entry for STA %d", sta_id); hdd_softap_deregister_sta(adapter, sta_id); } @@ -1102,8 +1120,8 @@ QDF_STATUS hdd_softap_register_sta(struct hdd_adapter *adapter, qdf_status = cdp_peer_register(soc, (struct cdp_pdev *)pdev, &staDesc); if (!QDF_IS_STATUS_SUCCESS(qdf_status)) { - hdd_err("cdp_peer_register() failed to register. Status = %d [0x%08X]", - qdf_status, qdf_status); + hdd_debug("cdp_peer_register() failed to register. Status = %d [0x%08X]", + qdf_status, qdf_status); return qdf_status; } @@ -1117,8 +1135,8 @@ QDF_STATUS hdd_softap_register_sta(struct hdd_adapter *adapter, adapter->sta_info[sta_id].is_qos_enabled = wmm_enabled; if (!auth_required) { - hdd_info("open/shared auth StaId= %d. Changing TL state to AUTHENTICATED at Join time", - adapter->sta_info[sta_id].sta_id); + hdd_debug("open/shared auth StaId= %d. Changing TL state to AUTHENTICATED at Join time", + adapter->sta_info[sta_id].sta_id); /* Connections that do not need Upper layer auth, * transition TL directly to 'Authenticated' state. @@ -1129,8 +1147,8 @@ QDF_STATUS hdd_softap_register_sta(struct hdd_adapter *adapter, adapter->sta_info[sta_id].peer_state = OL_TXRX_PEER_STATE_AUTH; } else { - hdd_info("ULA auth StaId= %d. Changing TL state to CONNECTED at Join time", - adapter->sta_info[sta_id].sta_id); + hdd_debug("ULA auth StaId= %d. Changing TL state to CONNECTED at Join time", + adapter->sta_info[sta_id].sta_id); qdf_status = hdd_change_peer_state(adapter, staDesc.sta_id, OL_TXRX_PEER_STATE_CONN, false); @@ -1225,8 +1243,8 @@ QDF_STATUS hdd_softap_stop_bss(struct hdd_adapter *adapter) if (adapter->sta_info[sta_id].in_use) { qdf_status = hdd_softap_deregister_sta(adapter, sta_id); if (!QDF_IS_STATUS_SUCCESS(qdf_status)) { - hdd_err("Failed to deregister sta Id %d", - sta_id); + hdd_debug("Failed to deregister sta Id %d", + sta_id); } } } @@ -1273,13 +1291,13 @@ QDF_STATUS hdd_softap_change_sta_state(struct hdd_adapter *adapter, if (false == qdf_is_macaddr_equal(&adapter->sta_info[sta_id].sta_mac, sta_mac)) { - hdd_err("Station %u MAC address not matching", sta_id); + hdd_debug("Station %u MAC address not matching", sta_id); return QDF_STATUS_E_FAILURE; } qdf_status = hdd_change_peer_state(adapter, sta_id, state, false); - hdd_info("Station %u changed to state %d", sta_id, state); + hdd_debug("Station %u changed to state %d", sta_id, state); if (QDF_STATUS_SUCCESS == qdf_status) { adapter->sta_info[sta_id].peer_state = diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_stats.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_stats.c index b975446e576f..32b72434b1f6 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_stats.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_stats.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -37,6 +37,7 @@ #include "wlan_reg_services_api.h" #include #include "wlan_cp_stats_mc_ucfg_api.h" +#include "wlan_mlme_ucfg_api.h" #if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 0, 0)) && !defined(WITH_BACKPORTS) #define HDD_INFO_SIGNAL STATION_INFO_SIGNAL @@ -556,8 +557,8 @@ bool hdd_get_interface_info(struct hdd_adapter *adapter, } if (eConnectionState_Connecting == sta_ctx->conn_info.connState) { - hdd_err("Session ID %d, Connection is in progress", - adapter->session_id); + hdd_debug("Session ID %d, Connection is in progress", + adapter->session_id); pInfo->state = WIFI_ASSOCIATING; } if ((eConnectionState_Associated == @@ -619,16 +620,14 @@ static void hdd_link_layer_process_peer_stats(struct hdd_adapter *adapter, struct nlattr *peers; int numRate; - hdd_enter(); - pWifiPeerStat = pData; status = wlan_hdd_validate_context(hdd_ctx); if (0 != status) return; - hdd_debug("LL_STATS_PEER_ALL : numPeers %u, more data = %u", - pWifiPeerStat->numPeers, more_data); + hdd_nofl_debug("LL_STATS_PEER_ALL : numPeers %u, more data = %u", + pWifiPeerStat->numPeers, more_data); /* * Allocate a size of 4096 for the peer stats comprising @@ -708,7 +707,6 @@ static void hdd_link_layer_process_peer_stats(struct hdd_adapter *adapter, } cfg80211_vendor_cmd_reply(vendor_event); - hdd_exit(); } /** @@ -732,8 +730,6 @@ static void hdd_link_layer_process_iface_stats(struct hdd_adapter *adapter, struct hdd_context *hdd_ctx = WLAN_HDD_GET_CTX(adapter); int status; - hdd_enter(); - pWifiIfaceStat = pData; status = wlan_hdd_validate_context(hdd_ctx); @@ -771,7 +767,6 @@ static void hdd_link_layer_process_iface_stats(struct hdd_adapter *adapter, } cfg80211_vendor_cmd_reply(vendor_event); - hdd_exit(); } /** @@ -970,8 +965,6 @@ static void hdd_link_layer_process_radio_stats(struct hdd_adapter *adapter, tSirWifiRadioStat *pWifiRadioStat = pData; struct hdd_context *hdd_ctx = WLAN_HDD_GET_CTX(adapter); - hdd_enter(); - status = wlan_hdd_validate_context(hdd_ctx); if (0 != status) return; @@ -979,7 +972,7 @@ static void hdd_link_layer_process_radio_stats(struct hdd_adapter *adapter, hdd_debug("LL_STATS_RADIO: number of radios: %u", num_radio); for (i = 0; i < num_radio; i++) { - hdd_debug("LL_STATS_RADIO" + hdd_nofl_debug("LL_STATS_RADIO" " radio: %u onTime: %u txTime: %u rxTime: %u" " onTimeScan: %u onTimeNbd: %u" " onTimeGscan: %u onTimeRoamScan: %u" @@ -1009,7 +1002,6 @@ static void hdd_link_layer_process_radio_stats(struct hdd_adapter *adapter, pWifiRadioStat++; } - hdd_exit(); } /** @@ -1117,18 +1109,16 @@ void wlan_hdd_cfg80211_link_layer_stats_callback(void *ctx, int indType, return; } - hdd_debug("Link Layer Indication indType: %d", indType); - switch (indType) { case SIR_HAL_LL_STATS_RESULTS_RSP: { - hdd_debug("LL_STATS RESP paramID = 0x%x, ifaceId = %u, respId= %u , moreResultToFollow = %u, num radio = %u result = %pK", - linkLayerStatsResults->paramId, - linkLayerStatsResults->ifaceId, - linkLayerStatsResults->rspId, - linkLayerStatsResults->moreResultToFollow, - linkLayerStatsResults->num_radio, - linkLayerStatsResults->results); + hdd_nofl_debug("LL_STATS RESP paramID = 0x%x, ifaceId = %u, respId= %u , moreResultToFollow = %u, num radio = %u result = %pK", + linkLayerStatsResults->paramId, + linkLayerStatsResults->ifaceId, + linkLayerStatsResults->rspId, + linkLayerStatsResults->moreResultToFollow, + linkLayerStatsResults->num_radio, + linkLayerStatsResults->results); request = osif_request_get(cookie); if (!request) { @@ -1494,8 +1484,8 @@ __wlan_hdd_cfg80211_ll_stats_get(struct wiphy *wiphy, return -EINVAL; if (!adapter->is_link_layer_stats_set) { - hdd_warn("is_link_layer_stats_set: %d", - adapter->is_link_layer_stats_set); + hdd_nofl_debug("is_link_layer_stats_set: %d", + adapter->is_link_layer_stats_set); return -EINVAL; } @@ -3894,7 +3884,7 @@ int wlan_hdd_get_station_remote(struct wiphy *wiphy, cfg = hddctx->config; - hdd_debug("get peer %pM info", mac); + hdd_debug("Peer %pM", mac); for (i = 0; i < WLAN_MAX_STA_COUNT; i++) { if (!qdf_mem_cmp(adapter->sta_info[i].sta_mac.bytes, @@ -4358,6 +4348,36 @@ static void hdd_fill_fcs_and_mpdu_count(struct hdd_adapter *adapter, } #endif +/** + * hdd_check_and_update_nss() - Check and update NSS as per DBS capability + * @hdd_ctx: HDD Context pointer + * @tx_nss: pointer to variable storing the tx_nss + * @rx_nss: pointer to variable storing the rx_nss + * + * The parameters include the NSS obtained from the FW or static NSS. This NSS + * could be invalid in the case the current HW mode is DBS where the connection + * are 1x1. Rectify these NSS values as per the current HW mode. + * + * Return: none + */ +static void hdd_check_and_update_nss(struct hdd_context *hdd_ctx, + uint8_t *tx_nss, uint8_t *rx_nss) +{ + if ((*tx_nss > 1) && + policy_mgr_is_current_hwmode_dbs(hdd_ctx->psoc) && + !policy_mgr_is_hw_dbs_2x2_capable(hdd_ctx->psoc)) { + hdd_debug("Hw mode is DBS, Reduce tx nss(%d) to 1", *tx_nss); + (*tx_nss)--; + } + + if ((*rx_nss > 1) && + policy_mgr_is_current_hwmode_dbs(hdd_ctx->psoc) && + !policy_mgr_is_hw_dbs_2x2_capable(hdd_ctx->psoc)) { + hdd_debug("Hw mode is DBS, Reduce tx nss(%d) to 1", *rx_nss); + (*rx_nss)--; + } +} + /** * wlan_hdd_get_sta_stats() - get aggregate STA stats * @wiphy: wireless phy @@ -4458,21 +4478,7 @@ static int wlan_hdd_get_sta_stats(struct wiphy *wiphy, tx_nss = adapter->hdd_stats.class_a_stat.tx_nss; rx_nss = adapter->hdd_stats.class_a_stat.rx_nss; - if ((tx_nss > 1) && - policy_mgr_is_current_hwmode_dbs(hdd_ctx->psoc) && - !policy_mgr_is_hw_dbs_2x2_capable(hdd_ctx->psoc)) { - hdd_debug("Hw mode is DBS, Reduce nss(%d) to 1", - tx_nss); - tx_nss--; - } - - if ((rx_nss > 1) && - policy_mgr_is_current_hwmode_dbs(hdd_ctx->psoc) && - !policy_mgr_is_hw_dbs_2x2_capable(hdd_ctx->psoc)) { - hdd_debug("Hw mode is DBS, Reduce nss(%d) to 1", - rx_nss); - rx_nss--; - } + hdd_check_and_update_nss(hdd_ctx, &tx_nss, &rx_nss); if (eHDD_LINK_SPEED_REPORT_ACTUAL == pCfg->reportMaxLinkSpeed) { /* Get current rate flags if report actual */ @@ -4496,23 +4502,31 @@ static int wlan_hdd_get_sta_stats(struct wiphy *wiphy, rx_mcs_index = 0; } - hdd_debug("RSSI %d, RLMS %u, rssi high %d, rssi mid %d, rssi low %d", + hdd_debug("[RSSI %d, RLMS %u, rssi high %d, rssi mid %d, rssi low %d]-" + "[Rate info: TX: %d, RX: %d]-[Rate flags: TX: 0x%x, RX: 0x%x]" + "-[MCS Index: TX: %d, RX: %d]-[NSS: TX: %d, RX: %d]", sinfo->signal, pCfg->reportMaxLinkSpeed, (int)pCfg->linkSpeedRssiHigh, (int)pCfg->linkSpeedRssiMid, - (int)pCfg->linkSpeedRssiLow); - hdd_debug("Rate info: TX: %d, RX: %d", my_tx_rate, my_rx_rate); - hdd_debug("Rate flags: TX: 0x%x, RX: 0x%x", (int)tx_rate_flags, - (int)rx_rate_flags); - hdd_debug("MCS Index: TX: %d, RX: %d", (int)tx_mcs_index, - (int)rx_mcs_index); - hdd_debug("NSS: TX: %d, RX: %d", (int)tx_nss, (int)rx_nss); + (int)pCfg->linkSpeedRssiLow, my_tx_rate, my_rx_rate, + (int)tx_rate_flags, (int)rx_rate_flags, (int)tx_mcs_index, + (int)rx_mcs_index, (int)tx_nss, (int)rx_nss); /* assume basic BW. anything else will override this later */ hdd_set_rate_bw(&sinfo->txrate, HDD_RATE_BW_20); if (eHDD_LINK_SPEED_REPORT_ACTUAL != pCfg->reportMaxLinkSpeed) { - bool tx_rate_calc; - bool rx_rate_calc; + bool tx_rate_calc, rx_rate_calc; + uint8_t tx_nss_max, rx_nss_max; + + /* + * Take static NSS for reporting max rates. NSS from the FW + * is not reliable as it changes as per the environment + * quality. + */ + tx_nss_max = wlan_vdev_mlme_get_nss(adapter->vdev); + rx_nss_max = wlan_vdev_mlme_get_nss(adapter->vdev); + + hdd_check_and_update_nss(hdd_ctx, &tx_nss_max, &rx_nss_max); tx_rate_calc = hdd_report_max_rate(mac_handle, pCfg, &sinfo->txrate, @@ -4520,7 +4534,7 @@ static int wlan_hdd_get_sta_stats(struct wiphy *wiphy, tx_rate_flags, tx_mcs_index, my_tx_rate, - tx_nss); + tx_nss_max); rx_rate_calc = hdd_report_max_rate(mac_handle, pCfg, &sinfo->rxrate, @@ -4528,7 +4542,7 @@ static int wlan_hdd_get_sta_stats(struct wiphy *wiphy, rx_rate_flags, rx_mcs_index, my_rx_rate, - rx_nss); + rx_nss_max); if (!tx_rate_calc || !rx_rate_calc) /* Keep GUI happy */ @@ -4830,9 +4844,6 @@ static int __wlan_hdd_cfg80211_dump_survey(struct wiphy *wiphy, int status; bool filled = false; - hdd_enter_dev(dev); - - hdd_debug("dump survey index: %d", idx); if (idx > QDF_MAX_NUM_CHAN - 1) return -EINVAL; @@ -4865,7 +4876,7 @@ static int __wlan_hdd_cfg80211_dump_survey(struct wiphy *wiphy, if (!filled) return -ENONET; - hdd_exit(); + return 0; } @@ -5892,6 +5903,8 @@ int wlan_hdd_get_station_stats(struct hdd_adapter *adapter) int ret = 0; uint8_t mcs_rate_flags; struct stats_event *stats; + struct mlme_nss_chains *dynamic_cfg; + uint32_t tx_nss, rx_nss; stats = wlan_cfg80211_mc_cp_stats_get_station_stats(adapter->vdev, &ret); @@ -5938,11 +5951,29 @@ int wlan_hdd_get_station_stats(struct hdd_adapter *adapter) adapter->hdd_stats.peer_stats.fcs_count = stats->peer_adv_stats->fcs_count; + dynamic_cfg = mlme_get_dynamic_vdev_config(adapter->vdev); + if (!dynamic_cfg) { + hdd_err("nss chain dynamic config NULL"); + return -EINVAL; + } + + switch (hdd_conn_get_connected_band(&adapter->session.station)) { + case BAND_2G: + tx_nss = dynamic_cfg->tx_nss[NSS_CHAINS_BAND_2GHZ]; + rx_nss = dynamic_cfg->rx_nss[NSS_CHAINS_BAND_2GHZ]; + break; + case BAND_5G: + tx_nss = dynamic_cfg->tx_nss[NSS_CHAINS_BAND_5GHZ]; + rx_nss = dynamic_cfg->rx_nss[NSS_CHAINS_BAND_5GHZ]; + break; + default: + tx_nss = wlan_vdev_mlme_get_nss(adapter->vdev); + rx_nss = wlan_vdev_mlme_get_nss(adapter->vdev); + } + /* save class a stats to legacy location */ - adapter->hdd_stats.class_a_stat.tx_nss = - wlan_vdev_mlme_get_nss(adapter->vdev); - adapter->hdd_stats.class_a_stat.rx_nss = - wlan_vdev_mlme_get_nss(adapter->vdev); + adapter->hdd_stats.class_a_stat.tx_nss = tx_nss; + adapter->hdd_stats.class_a_stat.rx_nss = rx_nss; adapter->hdd_stats.class_a_stat.tx_rate = stats->tx_rate; adapter->hdd_stats.class_a_stat.rx_rate = stats->rx_rate; adapter->hdd_stats.class_a_stat.tx_rx_rate_flags = stats->tx_rate_flags; diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_subnet_detect.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_subnet_detect.c index ae2d2b8b4721..bd3530fa74e3 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_subnet_detect.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_subnet_detect.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -86,7 +86,7 @@ static int __wlan_hdd_cfg80211_set_gateway_params(struct wiphy *wiphy, /* user may have disabled the feature in INI */ if (!hdd_ctx->config->enable_lfr_subnet_detection) { - hdd_info("LFR Subnet Detection disabled in INI"); + hdd_debug("LFR Subnet Detection disabled in INI"); return -ENOTSUPP; } @@ -94,12 +94,12 @@ static int __wlan_hdd_cfg80211_set_gateway_params(struct wiphy *wiphy, * and only in the connected state. */ if (QDF_STA_MODE != adapter->device_mode) { - hdd_err("Received GW param update for non-STA mode adapter"); + hdd_debug("Received GW param update for non-STA mode adapter"); return -ENOTSUPP; } if (!hdd_conn_is_connected(WLAN_HDD_GET_STATION_CTX_PTR(adapter))) { - hdd_err("Received GW param update in disconnected state!"); + hdd_debug("Received GW param update in disconnected state!"); return -ENOTSUPP; } diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_trace.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_trace.c index 22a2438499f6..110b636143ed 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_trace.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_trace.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2017 The Linux Foundation. All rights reserved. + * Copyright (c) 2014-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -42,12 +42,12 @@ static void hdd_trace_dump(void *mac, tp_qdf_trace_record record, uint16_t index) { if (TRACE_CODE_HDD_RX_SME_MSG == record->code) - hdd_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", + hdd_nofl_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", index, record->qtime, record->time, record->session, "RX SME MSG:", get_e_roam_cmd_status_str(record->data), record->data); else - hdd_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", + hdd_nofl_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", index, record->qtime, record->time, record->session, "HDD Event:", hdd_trace_event_string(record->code), record->data); diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_tsf.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_tsf.c index fe648feedac2..1d2752c0f61d 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_tsf.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_tsf.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -1235,7 +1235,7 @@ enum hdd_tsf_op_result hdd_netbuf_timestamp(qdf_nbuf_t netbuf, if (!ret) { hwtstamps.hwtstamp = soc_time; *skb_hwtstamps(netbuf) = hwtstamps; - netbuf->tstamp = 0; + netbuf->tstamp = ktime_set(0, 0); return HDD_TSF_OP_SUCC; } } @@ -1324,7 +1324,7 @@ int hdd_rx_timestamp(qdf_nbuf_t netbuf, uint64_t target_time) return 0; /* reset tstamp when failed */ - netbuf->tstamp = 0; + netbuf->tstamp = ktime_set(0, 0); return -EINVAL; } @@ -1760,7 +1760,7 @@ void wlan_hdd_tsf_init(struct hdd_context *hdd_ctx) status = hdd_tsf_set_gpio(hdd_ctx); if (QDF_STATUS_SUCCESS != status) { - hdd_err("set tsf GPIO failed, status: %d", status); + hdd_debug("set tsf GPIO failed, status: %d", status); goto fail; } diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_tx_rx.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_tx_rx.c index 48dc2aa86bf7..e313350031d4 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_tx_rx.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_tx_rx.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -485,7 +485,7 @@ static void hdd_get_transmit_sta_id(struct hdd_adapter *adapter, */ static void hdd_clear_tx_rx_connectivity_stats(struct hdd_adapter *adapter) { - hdd_info("Clear txrx connectivity stats"); + hdd_debug("Clear txrx connectivity stats"); qdf_mem_zero(&adapter->hdd_stats.hdd_arp_stats, sizeof(adapter->hdd_stats.hdd_arp_stats)); qdf_mem_zero(&adapter->hdd_stats.hdd_dns_stats, @@ -1060,6 +1060,8 @@ static netdev_tx_t __hdd_hard_start_xmit(struct sk_buff *skb, netif_trans_update(dev); + wlan_hdd_sar_unsolicited_timer_start(adapter->hdd_ctx); + return NETDEV_TX_OK; drop_pkt_and_release_skb: @@ -1283,18 +1285,7 @@ QDF_STATUS hdd_deinit_tx_rx(struct hdd_adapter *adapter) } #ifdef FEATURE_MONITOR_MODE_SUPPORT -/** - * hdd_mon_rx_packet_cbk() - Receive callback registered with OL layer. - * @context: [in] pointer to qdf context - * @rxBuf: [in] pointer to rx qdf_nbuf - * - * TL will call this to notify the HDD when one or more packets were - * received for a registered STA. - * - * Return: QDF_STATUS_E_FAILURE if any errors encountered, QDF_STATUS_SUCCESS - * otherwise - */ -static QDF_STATUS hdd_mon_rx_packet_cbk(void *context, qdf_nbuf_t rxbuf) +QDF_STATUS hdd_mon_rx_packet_cbk(void *context, qdf_nbuf_t rxbuf) { struct hdd_adapter *adapter; int rxstat; @@ -1403,6 +1394,66 @@ static bool hdd_is_mcast_replay(struct sk_buff *skb) return false; } +/** + * hdd_is_arp_local() - check if local or non local arp + * @skb: pointer to sk_buff + * + * Return: true if local arp or false otherwise. + */ +static bool hdd_is_arp_local(struct sk_buff *skb) +{ + struct arphdr *arp; + struct in_ifaddr **ifap = NULL; + struct in_ifaddr *ifa = NULL; + struct in_device *in_dev; + unsigned char *arp_ptr; + __be32 tip; + + arp = (struct arphdr *)skb->data; + if (arp->ar_op == htons(ARPOP_REQUEST)) { + in_dev = __in_dev_get_rtnl(skb->dev); + if (in_dev) { + for (ifap = &in_dev->ifa_list; (ifa = *ifap) != NULL; + ifap = &ifa->ifa_next) { + if (!strcmp(skb->dev->name, ifa->ifa_label)) + break; + } + } + + if (ifa && ifa->ifa_local) { + arp_ptr = (unsigned char *)(arp + 1); + arp_ptr += (skb->dev->addr_len + 4 + + skb->dev->addr_len); + memcpy(&tip, arp_ptr, 4); + hdd_debug("ARP packet: local IP: %x dest IP: %x", + ifa->ifa_local, tip); + if (ifa->ifa_local == tip) + return true; + } + } + + return false; +} + +/** + * hdd_is_rx_wake_lock_needed() - check if wake lock is needed + * @skb: pointer to sk_buff + * + * RX wake lock is needed for: + * 1) Unicast data packet OR + * 2) Local ARP data packet + * + * Return: true if wake lock is needed or false otherwise. + */ +static bool hdd_is_rx_wake_lock_needed(struct sk_buff *skb) +{ + if ((skb->pkt_type != PACKET_BROADCAST && + skb->pkt_type != PACKET_MULTICAST) || hdd_is_arp_local(skb)) + return true; + + return false; +} + #ifdef RECEIVE_OFFLOAD /** * hdd_resolve_rx_ol_mode() - Resolve Rx offload method, LRO or GRO @@ -1416,7 +1467,7 @@ static void hdd_resolve_rx_ol_mode(struct hdd_context *hdd_ctx) hdd_ctx->config->gro_enable)) { #ifdef WLAN_DEBUG hdd_ctx->config->lro_enable && hdd_ctx->config->gro_enable ? - hdd_err("Can't enable both LRO and GRO, disabling Rx offload") : + hdd_debug("Can't enable both LRO and GRO, disabling Rx offload") : hdd_debug("LRO and GRO both are disabled"); #endif hdd_ctx->ol_enable = 0; @@ -1739,6 +1790,7 @@ QDF_STATUS hdd_rx_packet_cbk(void *context, qdf_nbuf_t rxBuf) struct hdd_station_ctx *sta_ctx = NULL; unsigned int cpu_index; struct qdf_mac_addr *mac_addr, *dest_mac_addr; + bool wake_lock = false; uint8_t pkt_type = 0; bool track_arp = false; struct wlan_objmgr_vdev *vdev; @@ -1854,6 +1906,21 @@ QDF_STATUS hdd_rx_packet_cbk(void *context, qdf_nbuf_t rxBuf) continue; } + /* hold configurable wakelock for unicast traffic */ + if (!hdd_is_current_high_throughput(hdd_ctx) && + hdd_ctx->config->rx_wakelock_timeout && + sta_ctx->conn_info.uIsAuthenticated) + wake_lock = hdd_is_rx_wake_lock_needed(skb); + + if (wake_lock) { + cds_host_diag_log_work(&hdd_ctx->rx_wake_lock, + hdd_ctx->config->rx_wakelock_timeout, + WIFI_POWER_EVENT_WAKELOCK_HOLD_RX); + qdf_wake_lock_timeout_acquire(&hdd_ctx->rx_wake_lock, + hdd_ctx->config-> + rx_wakelock_timeout); + } + /* Remove SKB from internal tracking table before submitting * it to stack */ @@ -1901,7 +1968,10 @@ QDF_STATUS hdd_rx_packet_cbk(void *context, qdf_nbuf_t rxBuf) hdd_tx_rx_collect_connectivity_stats_info( skb, adapter, PKT_TYPE_RX_REFUSED, &pkt_type); - + DPTRACE(qdf_dp_log_proto_pkt_info(NULL, NULL, 0, 0, + QDF_RX, + QDF_TRACE_DEFAULT_MSDU_ID, + QDF_TX_RX_STATUS_DROP)); } } @@ -2299,7 +2369,8 @@ int hdd_set_mon_rx_cb(struct net_device *dev) } qdf_status = sme_create_mon_session(hdd_ctx->mac_handle, - adapter->mac_addr.bytes); + adapter->mac_addr.bytes, + adapter->session_id); if (QDF_STATUS_SUCCESS != qdf_status) { hdd_err("sme_create_mon_session() failed to register. Status= %d [0x%08X]", qdf_status, qdf_status); @@ -2343,11 +2414,11 @@ void hdd_send_rps_ind(struct hdd_adapter *adapter) hdd_ctxt = WLAN_HDD_GET_CTX(adapter); rps_data.num_queues = NUM_TX_QUEUES; - hdd_info("cpu_map_list '%s'", hdd_ctxt->config->cpu_map_list); + hdd_debug("cpu_map_list '%s'", hdd_ctxt->config->cpu_map_list); /* in case no cpu map list is provided, simply return */ if (!strlen(hdd_ctxt->config->cpu_map_list)) { - hdd_err("no cpu map list found"); + hdd_debug("no cpu map list found"); goto err; } @@ -2365,7 +2436,7 @@ void hdd_send_rps_ind(struct hdd_adapter *adapter) cpu_map_list_len : rps_data.num_queues; for (i = 0; i < rps_data.num_queues; i++) { - hdd_info("cpu_map_list[%d] = 0x%x", + hdd_debug("cpu_map_list[%d] = 0x%x", i, rps_data.cpu_map_list[i]); } @@ -2380,7 +2451,7 @@ void hdd_send_rps_ind(struct hdd_adapter *adapter) return; err: - hdd_err("Wrong RPS configuration. enabling rx_thread"); + hdd_debug("Wrong RPS configuration. enabling rx_thread"); cds_cfg->rps_enabled = false; } diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_wext.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_wext.c index 69566634ca81..01c9215e73fa 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_wext.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_wext.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -2890,7 +2890,7 @@ static int hdd_check_wext_control(enum hdd_wext_control wext_control, hdd_err_rl("Rejecting disabled ioctl %x", info->cmd); return -ENOTSUPP; case hdd_wext_deprecated: - hdd_warn_rl("Using deprecated ioctl %x", info->cmd); + hdd_nofl_debug("Using deprecated ioctl %x", info->cmd); return 0; case hdd_wext_enabled: return 0; diff --git a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_wmm.c b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_wmm.c index 94324407b4ff..165b68fb3f3f 100644 --- a/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_wmm.c +++ b/drivers/staging/qcacld-3.0/core/hdd/src/wlan_hdd_wmm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -54,9 +54,8 @@ #include #include "sme_api.h" -#define WLAN_HDD_MAX_DSCP 0x3f - #define HDD_WMM_UP_TO_AC_MAP_SIZE 8 +#define DSCP(x) x const uint8_t hdd_wmm_up_to_ac_map[] = { SME_AC_BE, @@ -1263,6 +1262,86 @@ static void hdd_wmm_do_implicit_qos(struct work_struct *work) cds_ssr_unprotect(__func__); } +QDF_STATUS hdd_send_dscp_up_map_to_fw(struct hdd_adapter *adapter) +{ + uint32_t *dscp_to_up_map = adapter->dscp_to_up_map; + + /* Send DSCP to TID map table to FW */ + return sme_send_dscp_up_map_to_fw(dscp_to_up_map); +} + +/** + * hdd_fill_dscp_to_up_map() - Fill up dscp_to_up_map table with default values + * @dscp_to_up_map: Array of DSCP-to-UP map + * + * This function will fill up the DSCP-to-UP map table with default values. + * + * Return: QDF_STATUS enumeration + */ +static inline void hdd_fill_dscp_to_up_map( + enum sme_qos_wmmuptype *dscp_to_up_map) +{ + uint8_t dscp; + + /* + * DSCP to User Priority Lookup Table + * By default use the 3 Precedence bits of DSCP as the User Priority + * + * In case of changing the default map values, need to take care of + * hdd_custom_dscp_up_map as well. + */ + for (dscp = 0; dscp <= WLAN_MAX_DSCP; dscp++) + dscp_to_up_map[dscp] = dscp >> 3; + + /* Special case for Expedited Forwarding (DSCP 46) in default mapping */ + dscp_to_up_map[DSCP(46)] = SME_QOS_WMM_UP_VO; +} + +#ifdef WLAN_CUSTOM_DSCP_UP_MAP +/** + * hdd_custom_dscp_up_map() - Customize dscp_to_up_map based on RFC8325 + * @dscp_to_up_map: Array of DSCP-to-UP map + * + * This function will customize the DSCP-to-UP map table based on RFC8325.. + * + * Return: QDF_STATUS enumeration + */ +static inline QDF_STATUS hdd_custom_dscp_up_map( + enum sme_qos_wmmuptype *dscp_to_up_map) +{ + /* + * Customizing few of DSCP to UP mapping based on RFC8325, + * those are different from default hdd_fill_dscp_to_up_map values. + * So, below changes are always relative to hdd_fill_dscp_to_up_map. + */ + dscp_to_up_map[DSCP(10)] = SME_QOS_WMM_UP_BE; + dscp_to_up_map[DSCP(12)] = SME_QOS_WMM_UP_BE; + dscp_to_up_map[DSCP(14)] = SME_QOS_WMM_UP_BE; + dscp_to_up_map[DSCP(16)] = SME_QOS_WMM_UP_BE; + + dscp_to_up_map[DSCP(18)] = SME_QOS_WMM_UP_EE; + dscp_to_up_map[DSCP(20)] = SME_QOS_WMM_UP_EE; + dscp_to_up_map[DSCP(22)] = SME_QOS_WMM_UP_EE; + + dscp_to_up_map[DSCP(24)] = SME_QOS_WMM_UP_CL; + dscp_to_up_map[DSCP(26)] = SME_QOS_WMM_UP_CL; + dscp_to_up_map[DSCP(28)] = SME_QOS_WMM_UP_CL; + dscp_to_up_map[DSCP(30)] = SME_QOS_WMM_UP_CL; + + dscp_to_up_map[DSCP(44)] = SME_QOS_WMM_UP_VO; + + dscp_to_up_map[DSCP(48)] = SME_QOS_WMM_UP_NC; + + return QDF_STATUS_SUCCESS; +} +#else +static inline QDF_STATUS hdd_custom_dscp_up_map( + enum sme_qos_wmmuptype *dscp_to_up_map) +{ + return QDF_STATUS_E_NOSUPPORT; +} +#endif /* WLAN_CUSTOM_DSCP_UP_MAP */ + /** * hdd_wmm_init() - initialize the WMM DSCP configuation * @adapter : [in] pointer to Adapter context @@ -1276,20 +1355,22 @@ static void hdd_wmm_do_implicit_qos(struct work_struct *work) QDF_STATUS hdd_wmm_init(struct hdd_adapter *adapter) { enum sme_qos_wmmuptype *dscp_to_up_map = adapter->dscp_to_up_map; - uint8_t dscp; + struct wlan_objmgr_psoc *psoc = adapter->hdd_ctx->psoc; + QDF_STATUS status = QDF_STATUS_SUCCESS; - hdd_enter(); + if (!psoc) { + hdd_err("Invalid psoc handle"); + return QDF_STATUS_E_FAILURE; + } - /* DSCP to User Priority Lookup Table - * By default use the 3 Precedence bits of DSCP as the User Priority - */ - for (dscp = 0; dscp <= WLAN_HDD_MAX_DSCP; dscp++) - dscp_to_up_map[dscp] = dscp >> 3; + hdd_fill_dscp_to_up_map(dscp_to_up_map); - /* Special case for Expedited Forwarding (DSCP 46) */ - dscp_to_up_map[46] = SME_QOS_WMM_UP_VO; + if (hdd_custom_dscp_up_map(dscp_to_up_map) == QDF_STATUS_SUCCESS) { + /* Send DSCP to TID map table to FW */ + status = hdd_send_dscp_up_map_to_fw(adapter); + } - return QDF_STATUS_SUCCESS; + return status; } /** @@ -1928,7 +2009,6 @@ QDF_STATUS hdd_wmm_connect(struct hdd_adapter *adapter, uint8_t acmMask; mac_handle_t mac_handle; - hdd_enter(); if ((eCSR_BSS_TYPE_INFRASTRUCTURE == eBssType) && roam_info && roam_info->u.pConnectedProfile) { @@ -1989,8 +2069,6 @@ QDF_STATUS hdd_wmm_connect(struct hdd_adapter *adapter, } - hdd_exit(); - return QDF_STATUS_SUCCESS; } diff --git a/drivers/staging/qcacld-3.0/core/mac/inc/ani_global.h b/drivers/staging/qcacld-3.0/core/mac/inc/ani_global.h index 0ba59b975c1f..6fb2b9c6c10d 100644 --- a/drivers/staging/qcacld-3.0/core/mac/inc/ani_global.h +++ b/drivers/staging/qcacld-3.0/core/mac/inc/ani_global.h @@ -815,6 +815,14 @@ struct mgmt_beacon_probe_filter { uint8_t sap_channel[SIR_MAX_SUPPORTED_BSS]; }; +#ifdef FEATURE_ANI_LEVEL_REQUEST +struct ani_level_params { + void (*ani_level_cb)(struct wmi_host_ani_level_event *ani, uint8_t num, + void *context); + void *context; +}; +#endif + /* ------------------------------------------------------------------- */ /* / MAC Sirius parameter structure */ typedef struct sAniSirGlobal { @@ -889,6 +897,11 @@ typedef struct sAniSirGlobal { bool bcn_reception_stats; /* Beacon stats enabled/disabled from ini */ bool enable_beacon_reception_stats; + uint32_t akm_service_bitmap; + bool is_adaptive_11r_roam_supported; +#ifdef FEATURE_ANI_LEVEL_REQUEST + struct ani_level_params ani_params; +#endif } tAniSirGlobal; #ifdef FEATURE_WLAN_TDLS diff --git a/drivers/staging/qcacld-3.0/core/mac/inc/ani_system_defs.h b/drivers/staging/qcacld-3.0/core/mac/inc/ani_system_defs.h index 7efebd2a16c9..85df5538eba9 100644 --- a/drivers/staging/qcacld-3.0/core/mac/inc/ani_system_defs.h +++ b/drivers/staging/qcacld-3.0/core/mac/inc/ani_system_defs.h @@ -71,6 +71,37 @@ typedef enum eAniAuthType { eSIR_DONOT_USE_AUTH_TYPE = SIR_MAX_ENUM_SIZE } tAniAuthType; +enum ani_akm_type { + ANI_AKM_TYPE_NONE, + ANI_AKM_TYPE_RSN, + ANI_AKM_TYPE_RSN_PSK, + ANI_AKM_TYPE_FT_RSN, + ANI_AKM_TYPE_FT_RSN_PSK, + ANI_AKM_TYPE_RSN_PSK_SHA256, + ANI_AKM_TYPE_RSN_8021X_SHA256, +#ifdef WLAN_FEATURE_SAE + ANI_AKM_TYPE_SAE, + ANI_AKM_TYPE_FT_SAE, +#endif + ANI_AKM_TYPE_SUITEB_EAP_SHA256, + ANI_AKM_TYPE_SUITEB_EAP_SHA384, + ANI_AKM_TYPE_FT_SUITEB_EAP_SHA384, + ANI_AKM_TYPE_FILS_SHA256, + ANI_AKM_TYPE_FILS_SHA384, + ANI_AKM_TYPE_FT_FILS_SHA256, + ANI_AKM_TYPE_FT_FILS_SHA384, + ANI_AKM_TYPE_OWE, +#ifdef FEATURE_WLAN_ESE + ANI_AKM_TYPE_CCKM, +#endif + ANI_AKM_TYPE_OSEN, + ANI_AKM_TYPE_DPP_RSN, + ANI_AKM_TYPE_WPA, + ANI_AKM_TYPE_WPA_PSK, + ANI_NUM_OF_SUPPORT_AKM_TYPE, + ANI_AKM_TYPE_UNKNOWN = 0xff, +}; + /* / Encryption type enum used with peer */ typedef enum eAniEdType { eSIR_ED_NONE, diff --git a/drivers/staging/qcacld-3.0/core/mac/inc/qwlan_version.h b/drivers/staging/qcacld-3.0/core/mac/inc/qwlan_version.h index 99ce08638eaf..9592f22640cd 100644 --- a/drivers/staging/qcacld-3.0/core/mac/inc/qwlan_version.h +++ b/drivers/staging/qcacld-3.0/core/mac/inc/qwlan_version.h @@ -32,9 +32,9 @@ #define QWLAN_VERSION_MAJOR 5 #define QWLAN_VERSION_MINOR 2 #define QWLAN_VERSION_PATCH 03 -#define QWLAN_VERSION_EXTRA "V" -#define QWLAN_VERSION_BUILD 14 +#define QWLAN_VERSION_EXTRA "J" +#define QWLAN_VERSION_BUILD 23 -#define QWLAN_VERSIONSTR "5.2.03.14V" +#define QWLAN_VERSIONSTR "5.2.03.23J" #endif /* QWLAN_VERSION_H */ diff --git a/drivers/staging/qcacld-3.0/core/mac/inc/sir_api.h b/drivers/staging/qcacld-3.0/core/mac/inc/sir_api.h index d6355e25a7e6..a517173437f8 100644 --- a/drivers/staging/qcacld-3.0/core/mac/inc/sir_api.h +++ b/drivers/staging/qcacld-3.0/core/mac/inc/sir_api.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -114,8 +114,13 @@ typedef uint8_t tSirVersionString[SIR_VERSION_STRING_LEN]; #define SIR_KRK_KEY_LEN 16 #define SIR_BTK_KEY_LEN 32 #define SIR_KCK_KEY_LEN 16 +#define KCK_192BIT_KEY_LEN 24 +#define KCK_256BIT_KEY_LEN 32 + #define SIR_KEK_KEY_LEN 16 #define SIR_KEK_KEY_LEN_FILS 64 +#define KEK_256BIT_KEY_LEN 32 + #define SIR_REPLAY_CTR_LEN 8 #define SIR_PMK_LEN 48 #define SIR_PMKID_LEN 16 @@ -131,8 +136,39 @@ typedef uint8_t tSirVersionString[SIR_VERSION_STRING_LEN]; #define SIR_UAPSD_FLAG_ACBE (1 << SIR_UAPSD_BITOFFSET_ACBE) #define SIR_UAPSD_GET(ac, mask) (((mask) & (SIR_UAPSD_FLAG_ ## ac)) >> SIR_UAPSD_BITOFFSET_ ## ac) +/* Roam debugging related macro defines */ +#define MAX_ROAM_DEBUG_BUF_SIZE 250 +#define MAX_ROAM_EVENTS_SUPPORTED 5 +#define ROAM_FAILURE_BUF_SIZE 40 +#define TIME_STRING_LEN 24 + +#define ROAM_CHANNEL_BUF_SIZE 300 +#define LINE_STR "=========================================" + +/** + * struct mlme_roam_debug_info - Roam debug information storage structure. + * @trigger: Roam trigger related data + * @scan: Roam scan related data structure. + * @result: Roam result parameters. + * @data_11kv: Neighbor report/BTM parameters. + */ +struct mlme_roam_debug_info { + struct wmi_roam_trigger_info trigger; + struct wmi_roam_scan_data scan; + struct wmi_roam_result result; + struct wmi_neighbor_report_data data_11kv; +}; #endif +/* + * AKM suites supported by firmware for roaming + */ +#define AKM_FT_SAE 0 +#define AKM_FT_SUITEB_SHA384 1 +#define AKM_FT_FILS 2 +#define AKM_SAE 3 +#define AKM_OWE 4 + /** * enum sir_roam_op_code - Operation to be done by the callback. * @SIR_ROAM_SYNCH_PROPAGATION: Propagate the new BSS info after roaming. @@ -216,6 +252,7 @@ struct wlan_mlme_chain_cfg { /** * struct wlan_beacon_report - Beacon info to be send to userspace + * @vdev_id: vdev id * @ssid: ssid present in beacon * @bssid: bssid present in beacon * @frequency: channel frequency in MHz @@ -224,6 +261,7 @@ struct wlan_mlme_chain_cfg { * @boot_time: Boot time when beacon received */ struct wlan_beacon_report { + uint8_t vdev_id; struct wlan_ssid ssid; struct qdf_mac_addr bssid; uint32_t frequency; @@ -440,10 +478,19 @@ typedef struct sSirSmeReadyReq { uint16_t length; uint16_t transactionId; void *csr_roam_synch_cb; + QDF_STATUS (*csr_roam_auth_event_handle_cb)(tpAniSirGlobal mac, + uint8_t vdev_id, + struct qdf_mac_addr bssid); void *pe_roam_synch_cb; void *stop_roaming_cb; QDF_STATUS (*sme_msg_cb)(tpAniSirGlobal mac, struct scheduler_msg *msg); + QDF_STATUS (*pe_disconnect_cb) (tpAniSirGlobal mac, + uint8_t vdev_id, + uint8_t *deauth_disassoc_frame, + uint16_t deauth_disassoc_frame_len, + uint16_t reason_code); + void *csr_roam_pmkid_req_cb; } tSirSmeReadyReq, *tpSirSmeReadyReq; /** @@ -717,6 +764,9 @@ struct fils_ind_elements { }; #endif +/* struct bss_description: bss information as per beacon/probe resp + * @sae_single_pmk_ap: flag to check if AP supports sae roaming with single pmk + */ struct bss_description { /* offset of the ieFields from bssId. */ uint16_t length; @@ -757,6 +807,11 @@ struct bss_description { uint8_t WscIeProbeRsp[WSCIE_PROBE_RSP_LEN]; uint8_t reservedPadding4; uint32_t tsf_delta; + uint32_t adaptive_11r_ap; +#if defined(WLAN_SAE_SINGLE_PMK) && defined(WLAN_FEATURE_ROAM_OFFLOAD) + bool sae_single_pmk_ap; +#endif + #ifdef WLAN_FEATURE_FILS_SK struct fils_ind_elements fils_info_element; #endif @@ -895,6 +950,7 @@ typedef struct sSirSmeTsmIEInd { tSirTsmIE tsmIe; uint8_t sessionId; } tSirSmeTsmIEInd, *tpSirSmeTsmIEInd; + typedef struct sAniTrafStrmMetrics { uint16_t UplinkPktQueueDly; uint16_t UplinkPktQueueDlyHist[4]; @@ -1069,12 +1125,14 @@ typedef struct sSirSmeJoinReq { tAniEdType UCEncryptionType; tAniEdType MCEncryptionType; + enum ani_akm_type akm; #ifdef WLAN_FEATURE_11W tAniEdType MgmtEncryptionType; #endif bool is11Rconnection; + bool is_adaptive_11r_connection; #ifdef FEATURE_WLAN_ESE bool isESEFeatureIniEnabled; bool isESEconnection; @@ -1515,6 +1573,7 @@ typedef struct sSirSmeDisassocInd { tAniStaStatStruct perStaStats; /* STA stats */ uint16_t staId; uint32_t reasonCode; + bool from_ap; } tSirSmeDisassocInd, *tpSirSmeDisassocInd; /* / Definition for Disassociation confirm */ @@ -1580,6 +1639,7 @@ typedef struct sSirSmeDeauthInd { uint16_t staId; uint32_t reasonCode; int8_t rssi; + bool from_ap; } tSirSmeDeauthInd, *tpSirSmeDeauthInd; /* / Definition for stop BSS request message */ @@ -2376,14 +2436,28 @@ struct sir_set_he_bss_color { * struct sir_create_session - Used for creating session in monitor mode * @type: SME host message type. * @msg_len: Length of the message. + * @vdev_id: vdev id * @bss_id: bss_id for creating the session. */ struct sir_create_session { uint16_t type; uint16_t msg_len; + uint8_t vdev_id; struct qdf_mac_addr bss_id; }; +/** + * struct sir_delete_session - Used for deleting session in monitor mode + * @type: SME host message type. + * @msg_len: Length of the message. + * @vdev_id: vdev id. + */ +struct sir_delete_session { + uint16_t type; + uint16_t msg_len; + uint8_t vdev_id; +}; + /* Beacon Interval */ typedef struct sSirChangeBIParams { uint16_t messageType; @@ -2645,6 +2719,20 @@ typedef struct sAniIbssRouteTable { } tAniIbssRouteTable; #ifdef WLAN_FEATURE_ROAM_OFFLOAD +/** + * struct roam_scan_ch_resp - roam scan chan list response to userspace + * @vdev_id: vdev id + * @command_resp: command response or async event + * @ChannelList: list of roam scan channels + * @num_channels: number of roam scan channels + */ +struct roam_scan_ch_resp { + uint16_t vdev_id; + uint16_t num_channels; + uint32_t command_resp; + uint32_t *chan_list; +}; + typedef struct { uint8_t acvo_uapsd:1; uint8_t acvi_uapsd:1; @@ -2660,12 +2748,12 @@ typedef struct { uint32_t authentication; uint8_t encryption; uint8_t mcencryption; + tAniEdType gp_mgmt_cipher_suite; uint8_t ChannelCount; uint8_t ChannelCache[SIR_ROAM_MAX_CHANNELS]; #ifdef WLAN_FEATURE_11W bool mfp_enabled; #endif - } tSirRoamNetworkType; typedef struct SirMobilityDomainInfo { @@ -2766,6 +2854,7 @@ struct roam_ext_params { * @pcl_weightage: PCL weightage * @channel_congestion_weightage: channel congestion weightage * @oce_wan_weightage: OCE WAN metrics weightage + * @vendor_roam_score_algorithm: Preferred vendor roam score algorithm */ struct sir_weight_config { uint8_t rssi_weightage; @@ -2779,6 +2868,7 @@ struct sir_weight_config { uint8_t pcl_weightage; uint8_t channel_congestion_weightage; uint8_t oce_wan_weightage; + uint32_t vendor_roam_score_algorithm; }; struct sir_rssi_cfg_score { @@ -2839,6 +2929,7 @@ struct sir_score_config { uint32_t band_weight_per_index; uint32_t roam_score_delta; uint32_t roam_score_delta_bitmap; + uint32_t cand_min_roam_score_delta; }; /** @@ -2885,6 +2976,14 @@ struct mawc_params { uint8_t mawc_roam_rssi_low_adjust; }; +/** + * struct roam_sync_timeout_timer_info - Info related to roam sync timer + * @vdev_id: Vdev id for which host waiting roam sync ind from fw + */ +struct roam_sync_timeout_timer_info { + uint8_t vdev_id; +}; + typedef struct sSirRoamOffloadScanReq { uint16_t message_type; uint16_t length; @@ -2921,6 +3020,7 @@ typedef struct sSirRoamOffloadScanReq { uint8_t RoamBeaconRssiWeight; eSirDFSRoamScanMode allowDFSChannelRoam; #ifdef WLAN_FEATURE_ROAM_OFFLOAD + struct roam_triggers roam_triggers; uint8_t RoamOffloadEnabled; uint8_t PSK_PMK[SIR_ROAM_SCAN_PSK_SIZE]; uint32_t pmk_len; @@ -2937,6 +3037,11 @@ typedef struct sSirRoamOffloadScanReq { struct pmkid_mode_bits pmkid_modes; uint32_t roam_preauth_retry_count; uint32_t roam_preauth_no_ack_timeout; + bool is_sae_single_pmk; + + /* Idle/Disconnect roam parameters */ + struct wmi_idle_roam_params idle_roam_params; + struct wmi_disconnect_roam_params disconnect_roam_params; #endif struct roam_ext_params roam_params; uint8_t middle_of_roaming; @@ -2959,8 +3064,10 @@ typedef struct sSirRoamOffloadScanReq { uint32_t btm_solicited_timeout; uint32_t btm_max_attempt_cnt; uint32_t btm_sticky_time; + uint32_t btm_query_bitmask; uint32_t rct_validity_timer; uint32_t disassoc_timer_threshold; + uint32_t btm_trig_min_candidate_score; struct wmi_11k_offload_params offload_11k_params; uint32_t ho_delay_for_rx; uint32_t min_delay_btw_roam_scans; @@ -2970,7 +3077,13 @@ typedef struct sSirRoamOffloadScanReq { bool bss_load_trig_enabled; struct wmi_bss_load_config bss_load_config; bool roaming_scan_policy; + uint32_t roam_scan_inactivity_time; + uint32_t roam_inactive_data_packet_count; + uint32_t roam_scan_period_after_inactivity; uint32_t full_roam_scan_period; + struct roam_trigger_min_rssi min_rssi_params[NUM_OF_ROAM_TRIGGERS]; + struct roam_trigger_score_delta score_delta_param[NUM_OF_ROAM_TRIGGERS]; + bool is_adaptive_11r_connection; } tSirRoamOffloadScanReq, *tpSirRoamOffloadScanReq; typedef struct sSirRoamOffloadScanRsp { @@ -3926,7 +4039,8 @@ typedef struct sSirSmeRoamOffloadSynchInd { uint8_t rssi; uint8_t roamReason; uint32_t chan_freq; - uint8_t kck[SIR_KCK_KEY_LEN]; + uint8_t kck[KCK_256BIT_KEY_LEN]; + uint8_t kck_len; uint32_t kek_len; uint8_t kek[SIR_KEK_KEY_LEN_FILS]; uint32_t pmk_len; @@ -3971,6 +4085,29 @@ struct sir_wisa_params { uint8_t vdev_id; }; +/** + * typedef enum wifi_scan_flags - wifi scan flags + * @WIFI_SCAN_FLAG_INTERRUPTED: Indicates that scan results are not complete + * because probes were not sent on some channels + */ +typedef enum { + WIFI_SCAN_FLAG_INTERRUPTED = 1, +} wifi_scan_flags; + +typedef enum { + WIFI_BAND_UNSPECIFIED, + WIFI_BAND_BG = 1, /* 2.4 GHz */ + WIFI_BAND_A = 2, /* 5 GHz without DFS */ + WIFI_BAND_ABG = 3, /* 2.4 GHz + 5 GHz; no DFS */ + WIFI_BAND_A_DFS_ONLY = 4, /* 5 GHz DFS only */ + /* 5 is reserved */ + WIFI_BAND_A_WITH_DFS = 6, /* 5 GHz with DFS */ + WIFI_BAND_ABG_WITH_DFS = 7, /* 2.4 GHz + 5 GHz with DFS */ + + /* Keep it last */ + WIFI_BAND_MAX +} tWifiBand; + #ifdef FEATURE_WLAN_EXTSCAN #define WLAN_EXTSCAN_MAX_CHANNELS 36 @@ -4003,29 +4140,6 @@ typedef enum { eSIR_EXTSCAN_CALLBACK_TYPE_MAX, } tSirExtScanCallbackType; -/** - * typedef enum wifi_scan_flags - wifi scan flags - * @WIFI_SCAN_FLAG_INTERRUPTED: Indicates that scan results are not complete - * because probes were not sent on some channels - */ -typedef enum { - WIFI_SCAN_FLAG_INTERRUPTED = 1, -} wifi_scan_flags; - -typedef enum { - WIFI_BAND_UNSPECIFIED, - WIFI_BAND_BG = 1, /* 2.4 GHz */ - WIFI_BAND_A = 2, /* 5 GHz without DFS */ - WIFI_BAND_ABG = 3, /* 2.4 GHz + 5 GHz; no DFS */ - WIFI_BAND_A_DFS_ONLY = 4, /* 5 GHz DFS only */ - /* 5 is reserved */ - WIFI_BAND_A_WITH_DFS = 6, /* 5 GHz with DFS */ - WIFI_BAND_ABG_WITH_DFS = 7, /* 2.4 GHz + 5 GHz with DFS */ - - /* Keep it last */ - WIFI_BAND_MAX -} tWifiBand; - /** * enum wifi_extscan_event_type - extscan event type * @WIFI_EXTSCAN_RESULTS_AVAILABLE: reported when REPORT_EVENTS_EACH_SCAN is set diff --git a/drivers/staging/qcacld-3.0/core/mac/inc/sir_mac_prot_def.h b/drivers/staging/qcacld-3.0/core/mac/inc/sir_mac_prot_def.h index a9fa895d7741..99b559d8b2e3 100644 --- a/drivers/staging/qcacld-3.0/core/mac/inc/sir_mac_prot_def.h +++ b/drivers/staging/qcacld-3.0/core/mac/inc/sir_mac_prot_def.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -650,7 +650,8 @@ #define SIR_MAX_BEACON_SIZE 512 #define SIR_MAX_PROBE_RESP_SIZE 512 -/* / Status Code (present in Management response frames) enum */ +/* Status Code (present in Management response frames) enum */ +/* (IEEE Std 802.11-2016, 9.4.1.9, Table 9-46) */ typedef enum eSirMacStatusCodes { eSIR_MAC_SUCCESS_STATUS = 0, /* Reserved */ @@ -728,9 +729,8 @@ typedef enum eSirMacStatusCodes { eSIR_MAC_DEST_STA_NOT_QSTA_STATUS = 50, /* The Destination STA is not a QoS STA */ eSIR_MAC_INVALID_LISTEN_INTERVAL_STATUS = 51, /* Association denied because the ListenInterval is too large */ - eSIR_MAC_DSSS_CCK_RATE_MUST_SUPPORT_STATUS = 52, /* FIXME: */ - eSIR_MAC_DSSS_CCK_RATE_NOT_SUPPORT_STATUS = 53, - eSIR_MAC_PSMP_CONTROLLED_ACCESS_ONLY_STATUS = 54, + eSIR_MAC_INVALID_FT_ACTION_FRAME_COUNT = 52, + eSIR_MAC_INVALID_PMKID = 53, #ifdef FEATURE_WLAN_ESE eSIR_MAC_ESE_UNSPECIFIED_QOS_FAILURE_STATUS = 200, /* ESE-Unspecified, QoS related failure in (Re)Assoc response frames */ eSIR_MAC_ESE_TSPEC_REQ_REFUSED_STATUS = 201, /* ESE-TSPEC request refused due to AP's policy configuration in AddTs Rsp, (Re)Assoc Rsp. */ @@ -757,7 +757,7 @@ typedef enum eSirMacReasonCodes { eSIR_MAC_STA_NOT_PRE_AUTHENTICATED_REASON = 9, /* Station requesting (re)association is not authenticated with responding station */ eSIR_MAC_PWR_CAPABILITY_BAD_REASON = 10, /* Disassociated because the information in the Power Capability element is unacceptable */ eSIR_MAC_SPRTD_CHANNELS_BAD_REASON = 11, /* Disassociated because the information in the Supported Channels element is unacceptable */ - /* reserved 12 */ + eSIR_MAC_BSS_TRANSITION_DISASSOC = 12, eSIR_MAC_INVALID_IE_REASON = 13, /* Invalid information element, i.e., an information element defined in this standard for */ /* which the content does not meet the specifications in Clause 7 */ eSIR_MAC_MIC_FAILURE_REASON = 14, /* Message integrity code (MIC) failure */ @@ -793,7 +793,29 @@ typedef enum eSirMacReasonCodes { eSIR_MAC_CIPHER_NOT_SUPPORTED_REASON = 45, /* Peer STA does not support the requested cipher suite */ eSIR_MAC_DISASSOC_DUE_TO_FTHANDOFF_REASON = 46, /* FT reason */ /* reserved 47 - 65535. */ - eSIR_BEACON_MISSED = 65534, /* We invented this to tell beacon missed case */ + + /* + * Internal reason codes: Add any internal reason code just after + * eSIR_MAC_REASON_PROP_START and decrease the value of + * eSIR_MAC_REASON_PROP_START accordingly. + */ + eSIR_MAC_REASON_PROP_START = 65519, + eSIR_MAC_HOST_TRIGGERED_ROAM_FAILURE = 65519, + eSIR_MAC_FW_TRIGGERED_ROAM_FAILURE = 65520, + eSIR_MAC_GATEWAY_REACHABILITY_FAILURE = 65521, + eSIR_MAC_UNSUPPORTED_CHANNEL_CSA = 65522, + eSIR_MAC_OPER_CHANNEL_DISABLED_INDOOR = 65523, + eSIR_MAC_OPER_CHANNEL_USER_DISABLED = 65524, + eSIR_MAC_DEVICE_RECOVERY = 65525, + eSIR_MAC_KEY_TIMEOUT = 65526, + eSIR_MAC_OPER_CHANNEL_BAND_CHANGE = 65527, + eSIR_MAC_IFACE_DOWN = 65528, + eSIR_MAC_PEER_XRETRY_FAIL = 65529, + eSIR_MAC_PEER_INACTIVITY = 65530, + eSIR_MAC_SA_QUERY_TIMEOUT = 65531, + eSIR_MAC_CHANNEL_SWITCH_FAILED = 65532, + eSIR_MAC_BEACON_MISSED = 65533, + eSIR_MAC_USER_TRIGGERED_ROAM_FAILURE = 65534, } tSirMacReasonCodes; /* BA Initiator v/s Recipient */ @@ -1987,6 +2009,7 @@ typedef struct sSirMacAuthFrameBody { uint8_t challengeText[SIR_MAC_AUTH_CHALLENGE_LENGTH]; #ifdef WLAN_FEATURE_FILS_SK tSirMacRsnInfo rsn_ie; + struct mac_ft_ie ft_ie; uint8_t assoc_delay_info; uint8_t session[SIR_FILS_SESSION_LENGTH]; uint8_t wrapped_data_len; diff --git a/drivers/staging/qcacld-3.0/core/mac/inc/wni_api.h b/drivers/staging/qcacld-3.0/core/mac/inc/wni_api.h index c080fe43df5b..14fc74d8989b 100644 --- a/drivers/staging/qcacld-3.0/core/mac/inc/wni_api.h +++ b/drivers/staging/qcacld-3.0/core/mac/inc/wni_api.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -233,6 +233,8 @@ enum eWniMsgTypes { eWNI_SME_HIDDEN_SSID_RESTART_RSP, eWNI_SME_ANTENNA_ISOLATION_RSP, WNI_SME_REGISTER_BCN_REPORT_SEND_CB, + eWNI_SME_MON_DEINIT_SESSION, + eWNI_SME_GET_ROAM_SCAN_CH_LIST_EVENT, eWNI_SME_MSG_TYPES_END }; diff --git a/drivers/staging/qcacld-3.0/core/mac/src/cfg/cfgUtil/dot11f.frms b/drivers/staging/qcacld-3.0/core/mac/src/cfg/cfgUtil/dot11f.frms index 442d965071ad..6c3e2360a0be 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/cfg/cfgUtil/dot11f.frms +++ b/drivers/staging/qcacld-3.0/core/mac/src/cfg/cfgUtil/dot11f.frms @@ -2026,6 +2026,14 @@ IE ESERadMgmtCap (EID_VENDOR_SPECIFIC) OUI (0x00, 0x40, 0x96, 0x01) } +IE BeaconReportStatus (EID_VENDOR_SPECIFIC) OUI (0x00, 0x00, 0x00F, 0x22) +{ + sub_type, 1; + version, 1; + length, 1; + reason_code, 1; +} + IE Vendor1IE (EID_VENDOR_SPECIFIC) OUI (0x00, 0x10, 0x18) { } @@ -3633,6 +3641,7 @@ FRAME AssocRequest // 7.2.3.4 OPTIE RSNOpaque; OPTIE ExtSuppRates; OPTIE MobilityDomain; + OPTIE FTInfo; OPTIE SuppOperatingClasses; OPTIE WAPIOpaque; OPTIE WAPI; @@ -4040,6 +4049,7 @@ FRAME RadioMeasurementReport FF DialogToken; //Measurement Report elements. MANDIE MeasurementReport[1..4]; + OPTIE BeaconReportStatus; } FRAME LinkMeasurementRequest diff --git a/drivers/staging/qcacld-3.0/core/mac/src/dph/dph_hash_table.c b/drivers/staging/qcacld-3.0/core/mac/src/dph/dph_hash_table.c index ced3e663fc10..a34a13484876 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/dph/dph_hash_table.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/dph/dph_hash_table.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -267,8 +267,6 @@ tpDphHashNode dph_init_sta_state(tpAniSirGlobal pMac, tSirMacAddr staAddr, pStaDs->added = 1; pStaDs->encPolicy = ENC_POLICY_NULL; pStaDs->is_disassoc_deauth_in_progress = 0; - pStaDs->last_assoc_received_time = 0; - pStaDs->last_disassoc_deauth_received_time = 0; pStaDs->sta_deletion_in_progress = false; pStaDs->valid = 1; return pStaDs; @@ -405,8 +403,6 @@ QDF_STATUS dph_delete_hash_entry(tpAniSirGlobal pMac, tSirMacAddr staAddr, prev->next = ptr->next; ptr->added = 0; ptr->is_disassoc_deauth_in_progress = 0; - ptr->last_assoc_received_time = 0; - ptr->last_disassoc_deauth_received_time = 0; ptr->sta_deletion_in_progress = false; ptr->next = 0; } else { diff --git a/drivers/staging/qcacld-3.0/core/mac/src/include/dot11f.h b/drivers/staging/qcacld-3.0/core/mac/src/include/dot11f.h index 44a516e977f5..53e899ecb43e 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/include/dot11f.h +++ b/drivers/staging/qcacld-3.0/core/mac/src/include/dot11f.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -26,7 +26,7 @@ * * * This file was automatically generated by 'framesc' - * Mon Mar 25 14:48:07 2019 from the following file(s): + * Sat Feb 8 15:57:31 2020 from the following file(s): * * dot11f.frms * @@ -4302,6 +4302,48 @@ uint32_t dot11f_get_packed_ie_AID( }; /* End extern "C". */ #endif /* C++ */ +/* EID 221 (0xdd) {OUI 0x00, 0x00, 0x0f, 0x22} */ +typedef struct sDot11fIEBeaconReportStatus { + uint8_t present; + uint8_t sub_type; + uint8_t version; + uint8_t length; + uint8_t reason_code; +} tDot11fIEBeaconReportStatus; + +#define DOT11F_EID_BEACONREPORTSTATUS (221) + +/* N.B. These #defines do *not* include the EID & length */ +#define DOT11F_IE_BEACONREPORTSTATUS_MIN_LEN (8) + +#define DOT11F_IE_BEACONREPORTSTATUS_MAX_LEN (8) + +#ifdef __cplusplus +extern "C" { +#endif /* C++ */ +__must_check uint32_t dot11f_unpack_ie_BeaconReportStatus( + tpAniSirGlobal, + uint8_t *, + uint8_t, + tDot11fIEBeaconReportStatus*, + bool); + +uint32_t dot11f_pack_ie_BeaconReportStatus( + tpAniSirGlobal, + tDot11fIEBeaconReportStatus *, + uint8_t *, + uint32_t, + uint32_t*); + +uint32_t dot11f_get_packed_ie_BeaconReportStatus( + tpAniSirGlobal, + tDot11fIEBeaconReportStatus *, + uint32_t*); + +#ifdef __cplusplus +}; /* End extern "C". */ +#endif /* C++ */ + /* EID 4 (0x04) */ typedef struct sDot11fIECFParams { uint8_t present; @@ -9442,6 +9484,7 @@ typedef struct sDot11fAssocRequest{ tDot11fIERSNOpaque RSNOpaque; tDot11fIEExtSuppRates ExtSuppRates; tDot11fIEMobilityDomain MobilityDomain; + tDot11fIEFTInfo FTInfo; tDot11fIESuppOperatingClasses SuppOperatingClasses; tDot11fIEWAPIOpaque WAPIOpaque; tDot11fIEWAPI WAPI; @@ -10313,11 +10356,12 @@ uint32_t dot11f_get_packed_qos_map_configure_size(tpAniSirGlobal pCtx, #endif /* C++ */ typedef struct sDot11fRadioMeasurementReport{ - tDot11fFfCategory Category; - tDot11fFfAction Action; - tDot11fFfDialogToken DialogToken; - uint16_t num_MeasurementReport; - tDot11fIEMeasurementReport MeasurementReport[4]; + tDot11fFfCategory Category; + tDot11fFfAction Action; + tDot11fFfDialogToken DialogToken; + uint16_t num_MeasurementReport; + tDot11fIEMeasurementReport MeasurementReport[4]; + tDot11fIEBeaconReportStatus BeaconReportStatus; } tDot11fRadioMeasurementReport; #define DOT11F_RADIOMEASUREMENTREPORT (24) diff --git a/drivers/staging/qcacld-3.0/core/mac/src/include/dph_global.h b/drivers/staging/qcacld-3.0/core/mac/src/include/dph_global.h index ea1ed1c8cb47..c3bdc1e2a77b 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/include/dph_global.h +++ b/drivers/staging/qcacld-3.0/core/mac/src/include/dph_global.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -241,8 +241,6 @@ typedef struct sDphHashNode { /* key installed for this STA or not in the firmware */ uint8_t is_key_installed; uint8_t is_disassoc_deauth_in_progress; - qdf_time_t last_assoc_received_time; - qdf_time_t last_disassoc_deauth_received_time; uint8_t nss; int8_t del_sta_ctx_rssi; diff --git a/drivers/staging/qcacld-3.0/core/mac/src/include/parser_api.h b/drivers/staging/qcacld-3.0/core/mac/src/include/parser_api.h index c34019ff216c..87af8dc330e0 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/include/parser_api.h +++ b/drivers/staging/qcacld-3.0/core/mac/src/include/parser_api.h @@ -361,6 +361,51 @@ typedef struct sSirAssocReq { tDot11fIEhe_cap he_cap; } tSirAssocReq, *tpSirAssocReq; +#define FTIE_SUBELEM_R1KH_ID 1 +#define FTIE_SUBELEM_GTK 2 +#define FTIE_SUBELEM_R0KH_ID 3 +#define FTIE_SUBELEM_IGTK 4 +#define FTIE_SUBELEM_OCI 5 + +#define FTIE_R1KH_LEN 6 +#define FTIE_R0KH_MAX_LEN 48 + +/** + * struct wlan_sha384_ftinfo_subelem - subelements of FTIE + * @r1kh_id: FT R1 Key holder ID + * @gtk: Ft group temporal key + * @gtk_len: GTK length + * @r0kh_id: FT R0 Key Holder ID + * @igtk: FT IGTK used for 11w + * @igtk_len: IGTK length + */ +struct wlan_sha384_ftinfo_subelem { + tDot11fIER1KH_ID r1kh_id; + uint8_t *gtk; + uint8_t gtk_len; + tDot11fIER0KH_ID r0kh_id; + uint8_t *igtk; + uint8_t igtk_len; +}; + +#define MIC_CONTROL_BYTES 2 +#define MIC_SHA384_BYTES 24 +#define NONCE_BYTES 32 + +/** + * struct wlan_sha384_ftinfo - FTE for sha384 based AKMs + * @mic_control: FTIE mic control field of 2 bytes + * @mic: MIC present in the FTIE assoc Response + * @anonce: Anonce sent by the AP + * @snonce: Snonce field in the FTIE + */ +struct wlan_sha384_ftinfo { + uint8_t mic_control[MIC_CONTROL_BYTES]; + uint8_t mic[MIC_SHA384_BYTES]; + uint8_t anonce[NONCE_BYTES]; + uint8_t snonce[NONCE_BYTES]; +}; + /* / Association Response structure (one day to be replaced by */ /* / tDot11fAssocRequest) */ typedef struct sSirAssocRsp { @@ -376,6 +421,8 @@ typedef struct sSirAssocRsp { tDot11fIEHTCaps HTCaps; tDot11fIEHTInfo HTInfo; tDot11fIEFTInfo FTInfo; + struct wlan_sha384_ftinfo sha384_ft_info; + struct wlan_sha384_ftinfo_subelem sha384_ft_subelem; uint8_t mdie[SIR_MDIE_SIZE]; uint8_t num_RICData; tDot11fIERICDataDesc RICData[2]; @@ -589,8 +636,21 @@ sir_convert_probe_frame2_struct(struct sAniSirGlobal *pMac, uint8_t *frame, QDF_STATUS sir_convert_assoc_req_frame2_struct(struct sAniSirGlobal *pMac, - uint8_t *frame, uint32_t len, - tpSirAssocReq assoc); + uint8_t *frame, uint32_t len, + tpSirAssocReq assoc); + +/** + * wlan_parse_ftie_sha384() - Parse the FT IE if akm uses sha384 KDF + * @frame: Pointer to the association response frame + * @frame_len: Length of the assoc response frame + * @assoc_rsp: Destination assoc response structure in PE to which the FTIE + * needs to be parsed and copied + * + * Return: QDF_STATUS + */ +QDF_STATUS +wlan_parse_ftie_sha384(uint8_t *frame, uint32_t frame_len, + struct sSirAssocRsp *assoc_rsp); QDF_STATUS sir_convert_assoc_resp_frame2_struct(struct sAniSirGlobal *pMac, @@ -1059,9 +1119,26 @@ QDF_STATUS populate_dot11f_rrm_ie(tpAniSirGlobal pMac, tDot11fIERRMEnabledCap *pDot11f, tpPESession psessionEntry); -void populate_mdie(tpAniSirGlobal pMac, - tDot11fIEMobilityDomain * pDot11f, uint8_t mdie[]); -void populate_ft_info(tpAniSirGlobal pMac, tDot11fIEFTInfo *pDot11f); +void populate_mdie(tpAniSirGlobal pMac, tDot11fIEMobilityDomain * pDot11f, + uint8_t mdie[]); + +#ifdef WLAN_FEATURE_FILS_SK +/** + * populate_fils_ft_info() - Populate FTIE into assoc request frame + * @mac: Global mac context + * @ft_info: pointer to assoc request frame FT IE buffer + * @pe_session: pointer to PE session + * + * Return: None + */ +void populate_fils_ft_info(tpAniSirGlobal mac, tDot11fIEFTInfo *ft_info, + tpPESession pe_session); +#else +static inline +void populate_fils_ft_info(tpAniSirGlobal mac, tDot11fIEFTInfo *ft_info, + tpPESession pe_session) +{} +#endif void populate_dot11f_assoc_rsp_rates(tpAniSirGlobal pMac, tDot11fIESuppRates *pSupp, diff --git a/drivers/staging/qcacld-3.0/core/mac/src/include/sir_debug.h b/drivers/staging/qcacld-3.0/core/mac/src/include/sir_debug.h index d294ae229a57..bd87da802acc 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/include/sir_debug.h +++ b/drivers/staging/qcacld-3.0/core/mac/src/include/sir_debug.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2012, 2014-2015, 2017-2018 The Linux Foundation. All + * Copyright (c) 2011-2012, 2014-2015, 2017-2018, 2020 The Linux Foundation. All * rights reserved. * * Permission to use, copy, modify, and/or distribute this software for @@ -50,6 +50,17 @@ #define pe_info(params...) QDF_TRACE_INFO(QDF_MODULE_ID_PE, params) #define pe_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_PE, params) +#define pe_nofl_alert(params...) \ + QDF_TRACE_FATAL_NO_FL(QDF_MODULE_ID_PE, params) +#define pe_nofl_err(params...) \ + QDF_TRACE_ERROR_NO_FL(QDF_MODULE_ID_PE, params) +#define pe_nofl_warn(params...) \ + QDF_TRACE_WARN_NO_FL(QDF_MODULE_ID_PE, params) +#define pe_nofl_info(params...) \ + QDF_TRACE_INFO_NO_FL(QDF_MODULE_ID_PE, params) +#define pe_nofl_debug(params...) \ + QDF_TRACE_DEBUG_NO_FL(QDF_MODULE_ID_PE, params) + #define PE_ENTER() pe_debug("enter") #define PE_EXIT() pe_debug("exit") #endif diff --git a/drivers/staging/qcacld-3.0/core/mac/src/include/sir_params.h b/drivers/staging/qcacld-3.0/core/mac/src/include/sir_params.h index 6f56d64142ea..5ebff37f1483 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/include/sir_params.h +++ b/drivers/staging/qcacld-3.0/core/mac/src/include/sir_params.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -296,7 +296,7 @@ struct sir_mgmt_msg { #define SIR_HAL_SET_TX_POWER_RSP (SIR_HAL_ITC_MSG_TYPES_BEGIN + 71) #define SIR_HAL_GET_TX_POWER_REQ (SIR_HAL_ITC_MSG_TYPES_BEGIN + 72) #define SIR_HAL_GET_TX_POWER_RSP (SIR_HAL_ITC_MSG_TYPES_BEGIN + 73) -#define SIR_HAL_GET_NOISE_RSP (SIR_HAL_ITC_MSG_TYPES_BEGIN + 74) +#define SIR_HAL_WMA_ROAM_SYNC_TIMEOUT (SIR_HAL_ITC_MSG_TYPES_BEGIN + 74) /* Messages to support transmit_halt and transmit_resume */ #define SIR_HAL_TRANSMISSION_CONTROL_IND (SIR_HAL_ITC_MSG_TYPES_BEGIN + 75) @@ -401,6 +401,7 @@ struct sir_mgmt_msg { #define SIR_HAL_TDLS_LINK_TEARDOWN (SIR_HAL_ITC_MSG_TYPES_BEGIN + 137) #endif #define SIR_HAL_ROAM_SCAN_OFFLOAD_REQ (SIR_HAL_ITC_MSG_TYPES_BEGIN + 138) +#define SIR_HAL_ROAM_PRE_AUTH_STATUS_IND (SIR_HAL_ITC_MSG_TYPES_BEGIN + 139) #define SIR_HAL_TRAFFIC_STATS_IND (SIR_HAL_ITC_MSG_TYPES_BEGIN + 141) @@ -694,7 +695,11 @@ struct sir_mgmt_msg { #define SIR_HAL_SEND_PEER_UNMAP_CONF (SIR_HAL_ITC_MSG_TYPES_BEGIN + 411) -#define SIR_HAL_GET_ISOLATION (SIR_HAL_ITC_MSG_TYPES_BEGIN + 412) +#define SIR_HAL_GET_ISOLATION (SIR_HAL_ITC_MSG_TYPES_BEGIN + 412) + +#define SIR_HAL_SET_ROAM_TRIGGERS (SIR_HAL_ITC_MSG_TYPES_BEGIN + 413) + +#define SIR_HAL_ROAM_SCAN_CH_REQ (SIR_HAL_ITC_MSG_TYPES_BEGIN + 414) #define SIR_HAL_MSG_TYPES_END (SIR_HAL_MSG_TYPES_BEGIN + 0x1FF) diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/include/lim_api.h b/drivers/staging/qcacld-3.0/core/mac/src/pe/include/lim_api.h index 26f19714b13c..82df5206875a 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/include/lim_api.h +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/include/lim_api.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -73,7 +73,7 @@ #define GET_LIM_PROCESS_DEFD_MESGS(pMac) (pMac->lim.gLimProcessDefdMsgs) #define SET_LIM_PROCESS_DEFD_MESGS(pMac, val) \ pMac->lim.gLimProcessDefdMsgs = val; \ - pe_debug("%s Defer LIM messages - value %d", __func__, val); + pe_debug("Defer LIM msg %d", val); /* LIM exported function templates */ #define LIM_MIN_BCN_PR_LENGTH 12 @@ -255,13 +255,59 @@ tMgmtFrmDropReason lim_is_pkt_candidate_for_drop(tpAniSirGlobal pMac, uint8_t *pRxPacketInfo, uint32_t subType); #ifdef WLAN_FEATURE_ROAM_OFFLOAD -QDF_STATUS pe_roam_synch_callback(tpAniSirGlobal mac_ctx, - struct sSirSmeRoamOffloadSynchInd *roam_sync_ind_ptr, - tpSirBssDescription bss_desc_ptr, enum sir_roam_op_code reason); +/** + * pe_roam_synch_callback() - Callback registered at wma, gets invoked when + * ROAM SYNCH event is received from firmware + * @mac_ctx: global mac context + * @roam_sync_ind_ptr: Structure with roam synch parameters + * @bss_desc_ptr: bss_description pointer for new bss to which the firmware has + * started roaming + * @reason: Operation to be done by the callback + * + * This is a PE level callback called from WMA to complete the roam synch + * propagation at PE level and also fill the BSS descriptor which will be + * helpful further to complete the roam synch propagation. + * + * Return: QDF_STATUS + */ +QDF_STATUS +pe_roam_synch_callback(tpAniSirGlobal mac_ctx, + struct sSirSmeRoamOffloadSynchInd *roam_sync_ind_ptr, + tpSirBssDescription bss_desc_ptr, + enum sir_roam_op_code reason); + +/** + * pe_disconnect_callback() - Callback to handle deauth event is received + * from firmware + * @mac: pointer to global mac context + * @vdev_id: VDEV in which the event was received + * @deauth_disassoc_frame: Deauth/disassoc frame received from firmware + * @deauth_disassoc_frame_len: Length of @deauth_disassoc_frame + * @reason_code: Fw sent reason code if disassoc/deauth frame is not + * available + * + * Return: QDF_STATUS + */ +QDF_STATUS +pe_disconnect_callback(tpAniSirGlobal mac, uint8_t vdev_id, + uint8_t *deauth_disassoc_frame, + uint16_t deauth_disassoc_frame_len, + uint16_t reason_code); #else -static inline QDF_STATUS pe_roam_synch_callback(tpAniSirGlobal mac_ctx, - struct sSirSmeRoamOffloadSynchInd *roam_sync_ind_ptr, - tpSirBssDescription bss_desc_ptr, enum sir_roam_op_code reason) +static inline QDF_STATUS +pe_roam_synch_callback(tpAniSirGlobal mac, + struct sSirSmeRoamOffloadSynchInd *roam_sync_ind_ptr, + tpSirBssDescription bss_desc_ptr, + enum sir_roam_op_code reason) +{ + return QDF_STATUS_E_NOSUPPORT; +} + +static inline QDF_STATUS +pe_disconnect_callback(tpAniSirGlobal mac, uint8_t vdev_id, + uint8_t *deauth_disassoc_frame, + uint16_t deauth_disassoc_frame_len, + uint16_t reason_code) { return QDF_STATUS_E_NOSUPPORT; } @@ -288,10 +334,21 @@ void lim_update_lost_link_info(tpAniSirGlobal mac, tpPESession session, void lim_mon_init_session(tpAniSirGlobal mac_ptr, struct sir_create_session *msg); +/** + * lim_mon_deinit_session() - delete PE session for monitor mode operation + * @mac_ptr: mac pointer + * @msg: Pointer to struct sir_delete_session type. + * + * Return: NONE + */ +void lim_mon_deinit_session(tpAniSirGlobal mac_ptr, + struct sir_delete_session *msg); + #define limGetQosMode(psessionEntry, pVal) (*(pVal) = (psessionEntry)->limQosEnabled) #define limGetWmeMode(psessionEntry, pVal) (*(pVal) = (psessionEntry)->limWmeEnabled) #define limGetWsmMode(psessionEntry, pVal) (*(pVal) = (psessionEntry)->limWsmEnabled) #define limGet11dMode(psessionEntry, pVal) (*(pVal) = (psessionEntry)->lim11dEnabled) + /* ----------------------------------------------------------------------- */ static inline void lim_get_phy_mode(tpAniSirGlobal pMac, uint32_t *phyMode, tpPESession psessionEntry) diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/include/lim_fils_defs.h b/drivers/staging/qcacld-3.0/core/mac/src/pe/include/lim_fils_defs.h index c109763298b6..9aac37706f2a 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/include/lim_fils_defs.h +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/include/lim_fils_defs.h @@ -28,6 +28,22 @@ /* 12.12.2.5.3 80211-ai draft */ #define PTK_KEY_LABEL "FILS PTK Derivation" +#define FT_PMK_R0_KEY_LABEL "FT-R0" +#define FT_PMK_R0_NAME_KEY_LABEL "FT-R0N" +#define FT_PMK_R1_NAME_KEY_LABEL "FT-R1N" + +#define PMKR0_SCATTER_LIST_ELEM 2 +#define PMKR1_SCATTER_LIST_ELEM 4 + +#define SCTR_LST_ELEM0 0 +#define SCTR_LST_ELEM1 1 +#define SCTR_LST_ELEM2 2 +#define SCTR_LST_ELEM3 3 + +/* Length of "FT-R1N" */ +#define SCTR_LST_R0_LABEL_LEN 6 +#define SCTR_LST_R1_LABEL_LEN 6 + #define MAX_ICK_LEN 48 #define MAX_KEK_LEN 64 #define MAX_TK_LEN 32 @@ -55,8 +71,17 @@ #define TK_LEN_CCMP 16 #define TK_LEN_AES_128_CMAC 32 -#define FILS_SHA256_PKM_LEN 32 -#define FILS_SHA384_PKM_LEN 48 +#define FILS_SHA256_PMK_LEN 32 +#define FILS_SHA384_PMK_LEN 48 + +#define FILS_FT_SHA256_LEN 32 +#define FILS_FT_SHA384_LEN 48 + +#define FILS_FT_MAX_R0_KEY_DATA_LEN 64 + +/* 12.7.1.7.3 802.11ai */ +#define FILS_SHA256_Q_LEN 32 +#define FILS_SHA384_Q_LEN 48 #define PMKID_LEN 16 @@ -176,6 +201,87 @@ struct fils_auth_rsp_info { uint8_t assoc_delay; }; +#define FT_R0KH_ID_MAX_LEN 48 +#define FT_R1KH_ID_LEN 6 +#define FT_NONCE_LEN 32 + +/* MIC Length Specified in Table 12-8- 802.11-2016 Spec */ +#define FT_MIC_LEN 16 +#define FT_GTK_RSC_LEN 8 +#define FT_GTK_KEY_LEN 32 +#define FT_IGTK_KEY_ID_LEN 2 +#define FT_IGTK_IPN_LEN 6 +#define FT_IGTK_KEY_LEN 24 + +/** + * struct mac_ft_gtk_ie - structure to parse the gtk ie + * @present: flag to indicate ie is present + * @key_id: Key-Id + * @reserved: reserved bits + * @key_length: gtk key length + * @rsc: denotes the last TSC or PN sent using the GTK + * @num_key: number of keys + * @key: actual keys + */ +struct mac_ft_gtk_ie { + uint8_t present; + uint16_t key_id:2; + uint16_t reserved:14; + uint8_t key_len; + uint8_t rsc[FT_GTK_RSC_LEN]; + uint8_t num_key; + uint8_t key[FT_GTK_KEY_LEN]; +}; + +/** + * struct mac_ft_gtk_ie - structure to parse the gtk ie + * @present: IE present or not present + * @key_id: 2Byte Key-ID + * @ipn: icorresponds to the last packet number used by broadcaster/multicaster + * @key_len: IGTK key length + * @key: IGTK Key + */ +struct mac_ft_igtk_ie { + uint8_t present; + uint8_t key_id[FT_IGTK_KEY_ID_LEN]; + uint8_t ipn[FT_IGTK_IPN_LEN]; + uint8_t key_len; + uint8_t key[FT_IGTK_KEY_LEN]; +}; + +/** + * struct mac_ft_ie - structure to parse the FT ie from auth frame + * @present: true if IE is present in Auth Frame + * @element_count: number of elements + * @mic: MIC. Will be zero in auth frame sent from AP. (Refer 13.2.4 802.11ai) + * @anonce: Authenticator NONCE. Will be zero in auth frame sent from AP. + * @snonce: Supplicant NONCE. Will be zero in auth frame + * @r1kh_id: R1KH ID. Length of R1KH ID is fixed(6 bytes). + * @r0kh_id_len: Length of R0KH ID + * @r0kh_id: R0KH id + * @gtk_ie: GTK subelement in FTIE + * @igtk_ie: IGTK subelement in FTIE + */ +struct mac_ft_ie { + bool present; + uint8_t element_count; + uint8_t mic[FT_MIC_LEN]; + uint8_t anonce[FT_NONCE_LEN]; + uint8_t snonce[FT_NONCE_LEN]; + uint8_t r1kh_id[FT_R1KH_ID_LEN]; + uint8_t r0kh_id_len; + uint8_t r0kh_id[FT_R0KH_ID_MAX_LEN]; + struct mac_ft_gtk_ie gtk_ie; + struct mac_ft_igtk_ie igtk_ie; +}; + +#define FILS_PMK_LEN 48 +#define FILS_PMK_NAME_LEN 16 +#define FILS_FT_MAX_LEN 48 +#define FILS_FT_PMK_R0_SALT_LEN 16 +#define FILS_MAX_KEY_DATA_LEN \ + (MAX_ICK_LEN + MAX_KEK_LEN + MAX_TK_LEN + FILS_FT_MAX_LEN) + /* * struct pe_fils_session: fils session info used in PE session * @is_fils_connection: whether connection is fils or not @@ -195,6 +301,13 @@ struct fils_auth_rsp_info { * @fils_nonce: fils snonce * @rsn_ie: rsn ie used in auth request * @rsn_ie_len: rsn ie length + * @group_mgmt_cipher_suite_present: Check if group management cipher suite + * is present in the FILS RSN IE + * @ft_ie: structure to store the parsed FTIE from auth response frame + * @pmkr0: PMKR0 + * @pmkr0_len: length of PMKR0 key + * @pmkr0_name: PMK_R0 name derived + * @pmkr1_name: PMKR1 Name derived * @fils_eap_finish_pkt: pointer to eap finish packet * @fils_eap_finish_pkt_len: eap finish packet length * @fils_rmsk: rmsk data pointer @@ -215,6 +328,8 @@ struct fils_auth_rsp_info { * @ap_key_auth_len: ap key data length * @gtk_len: gtk key length * @gtk: pointer to gtk data + * @fils_ft: xx_key data + * @fils_ft_len: xx_key length * @rsc: rsc value * @igtk_len: igtk length * @igtk: igtk data pointer @@ -242,6 +357,12 @@ struct pe_fils_session { uint8_t fils_nonce[SIR_FILS_NONCE_LENGTH]; uint8_t rsn_ie[MAX_IE_LENGTH]; uint8_t rsn_ie_len; + bool group_mgmt_cipher_present; + struct mac_ft_ie ft_ie; + uint8_t pmkr0[FILS_PMK_LEN]; + uint8_t pmkr0_len; + uint8_t pmkr0_name[FILS_PMK_NAME_LEN]; + uint8_t pmkr1_name[FILS_PMK_NAME_LEN]; uint8_t *fils_eap_finish_pkt; uint8_t fils_eap_finish_pkt_len; uint8_t *fils_rmsk; @@ -256,6 +377,8 @@ struct pe_fils_session { uint8_t kek_len; uint8_t tk[MAX_TK_LEN]; uint8_t tk_len; + uint8_t fils_ft[FILS_FT_MAX_LEN]; + uint8_t fils_ft_len; uint8_t key_auth[MAX_KEY_AUTH_DATA_LEN]; uint8_t key_auth_len; uint8_t ap_key_auth_data[MAX_KEY_AUTH_DATA_LEN]; diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/include/lim_process_fils.h b/drivers/staging/qcacld-3.0/core/mac/src/pe/include/lim_process_fils.h index 3e6f9b9ef868..2a424c5c5282 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/include/lim_process_fils.h +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/include/lim_process_fils.h @@ -83,12 +83,15 @@ QDF_STATUS lim_create_fils_rik(uint8_t *rrk, uint8_t rrk_len, /** * lim_update_fils_config()- This API updates fils session info to csr config * from join request. + * @mac_ctx: pointer to mac context * @session: PE session * @sme_join_req: pointer to join request * * Return: None */ -void lim_update_fils_config(tpPESession session, tpSirSmeJoinReq sme_join_req); +void lim_update_fils_config(tpAniSirGlobal mac_ctx, + tpPESession session, + tpSirSmeJoinReq sme_join_req); /** * lim_create_fils_auth_data()- This API creates the fils auth data @@ -132,6 +135,22 @@ void populate_fils_connect_params(tpAniSirGlobal mac_ctx, tpPESession session, tpSirSmeJoinRsp sme_join_rsp); +/** + * lim_update_fils_hlp_data() - Update the hlp data from association + * response frame to PE session. + * @hlp_frm_src_mac: SRC mac address in HLP IE from assoc frame + * @hlp_frm_dst_mac: DST mac address in HLP IE from assoc frame + * @frm_hlp_len: HLP data length + * @frm_hlp_data: Pointer to hlp data + * @pe_session: Pointer to pe_session + * + * Return: None + */ +void lim_update_fils_hlp_data(struct qdf_mac_addr *hlp_frm_src_mac, + struct qdf_mac_addr *hlp_frm_dest_mac, + uint16_t frm_hlp_len, uint8_t *frm_hlp_data, + tpPESession pe_session); + /** * aead_encrypt_assoc_req() - Encrypt FILS IE's in assoc request * @mac_ctx: mac context @@ -232,7 +251,9 @@ static inline bool lim_is_valid_fils_auth_frame(tpAniSirGlobal mac_ctx, } static inline void -lim_update_fils_config(tpPESession session, tpSirSmeJoinReq sme_join_req) +lim_update_fils_config(tpAniSirGlobal mac_ctx, + tpPESession session, + tpSirSmeJoinReq sme_join_req) { } static inline uint32_t lim_create_fils_auth_data(tpAniSirGlobal mac_ctx, @@ -251,6 +272,13 @@ static inline void populate_fils_connect_params(tpAniSirGlobal mac_ctx, tpSirSmeJoinRsp sme_join_rsp) { } +static inline +void lim_update_fils_hlp_data(struct qdf_mac_addr *hlp_frm_src_mac, + struct qdf_mac_addr *hlp_frm_dest_mac, + uint16_t frm_hlp_len, uint8_t *frm_hlp_data, + tpPESession pe_session) +{} + static inline QDF_STATUS aead_encrypt_assoc_req(tpAniSirGlobal mac_ctx, tpPESession pe_session, uint8_t *frame, diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/include/lim_session.h b/drivers/staging/qcacld-3.0/core/mac/src/pe/include/lim_session.h index a5be574f7b64..da1a40b07da1 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/include/lim_session.h +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/include/lim_session.h @@ -117,6 +117,14 @@ struct obss_detection_cfg { uint8_t obss_ht_20mhz_detect_mode; }; +#define ADAPTIVE_11R_STA_IE_LEN 0x0B +#define ADAPTIVE_11R_STA_OUI "\x00\x00\x0f\x22" +#define ADAPTIVE_11R_OUI_LEN 0x04 +#define ADAPTIVE_11R_OUI_SUBTYPE 0x00 +#define ADAPTIVE_11R_OUI_VERSION 0x01 +#define ADAPTIVE_11R_DATA_LEN 0x04 +#define ADAPTIVE_11R_OUI_DATA "\x00\x00\x00\x01" + typedef struct sPESession /* Added to Support BT-AMP */ { /* To check session table is in use or free */ @@ -139,7 +147,6 @@ typedef struct sPESession /* Added to Support BT-AMP */ tLimSmeStates limPrevSmeState; /* Previous SME State */ tLimSystemRole limSystemRole; tSirBssType bssType; - uint8_t operMode; /* AP - 0; STA - 1 ; */ tSirNwType nwType; tpSirSmeStartBssReq pLimStartBssReq; /* handle to smestart bss req */ tpSirSmeJoinReq pLimJoinReq; /* handle to sme join req */ @@ -150,6 +157,8 @@ typedef struct sPESession /* Added to Support BT-AMP */ uint16_t channelChangeReasonCode; uint8_t dot11mode; uint8_t htCapability; + enum ani_akm_type connected_akm; + /* Supported Channel Width Set: 0-20MHz 1 - 40MHz */ uint8_t htSupportedChannelWidthSet; /* Recommended Tx Width Set @@ -304,6 +313,7 @@ typedef struct sPESession /* Added to Support BT-AMP */ enum QDF_OPMODE pePersona; int8_t txMgmtPower; bool is11Rconnection; + bool is_adaptive_11r_connection; #ifdef FEATURE_WLAN_ESE bool isESEconnection; @@ -533,10 +543,6 @@ typedef struct sPESession /* Added to Support BT-AMP */ bool he_with_wep_tkip; #ifdef WLAN_FEATURE_FILS_SK struct pe_fils_session *fils_info; - struct qdf_mac_addr dst_mac; - struct qdf_mac_addr src_mac; - uint16_t hlp_data_len; - uint8_t *hlp_data; #endif /* previous auth frame's sequence number */ uint16_t prev_auth_seq_num; @@ -575,6 +581,8 @@ struct session_params { * @sessionId: session ID is returned here, if session is created. * @numSta: number of stations * @bssType: bss type of new session to do conditional memory allocation. + * @vdev_id: vdev_id + * @opmode: operating mode * * This function returns the session context and the session ID if the session * corresponding to the passed BSSID is found in the PE session table. @@ -584,7 +592,8 @@ struct session_params { tpPESession pe_create_session(tpAniSirGlobal pMac, uint8_t *bssid, uint8_t *sessionId, - uint16_t numSta, tSirBssType bssType); + uint16_t numSta, tSirBssType bssType, + uint8_t vdev_id, enum QDF_OPMODE opmode); /** * pe_find_session_by_bssid() - looks up the PE session given the BSSID. diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/include/rrm_api.h b/drivers/staging/qcacld-3.0/core/mac/src/pe/include/rrm_api.h index d20f4db670f1..1cb926782cd1 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/include/rrm_api.h +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/include/rrm_api.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2012, 2014-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2012, 2014-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -34,6 +34,7 @@ #define RRM_BCN_RPT_NO_BSS_INFO 0 #define RRM_BCN_RPT_MIN_RPT 1 +#define RRM_CH_BUF_LEN 45 uint8_t rrm_get_min_of_max_tx_power(tpAniSirGlobal pMac, int8_t regMax, int8_t apTxPower); diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_api.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_api.c index e32c90698d38..5f914bc4128b 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_api.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_api.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -71,6 +71,7 @@ #include #include #include "wlan_utility.h" +#include "wlan_mlme_main.h" static void __lim_init_bss_vars(tpAniSirGlobal pMac) { @@ -1442,7 +1443,10 @@ void pe_register_callbacks_with_wma(tpAniSirGlobal pMac, status = wma_register_roaming_callbacks( ready_req->csr_roam_synch_cb, - ready_req->pe_roam_synch_cb); + ready_req->csr_roam_auth_event_handle_cb, + ready_req->pe_roam_synch_cb, + ready_req->pe_disconnect_cb, + ready_req->csr_roam_pmkid_req_cb); if (status != QDF_STATUS_SUCCESS) pe_err("Registering roaming callbacks with WMA failed"); } @@ -1682,13 +1686,6 @@ lim_enc_type_matched(tpAniSirGlobal mac_ctx, if (!bcn || !session) return false; - pe_debug("Beacon/Probe:: Privacy: %d WPA Present: %d RSN Present: %d", - bcn->capabilityInfo.privacy, bcn->wpaPresent, bcn->rsnPresent); - pe_debug("session:: Privacy: %d EncyptionType: %d OSEN: %d WPS: %d", - SIR_MAC_GET_PRIVACY(session->limCurrentBssCaps), - session->encryptType, session->isOSENConnection, - session->wps_registration); - /* * This is handled by sending probe req due to IOT issues so * return TRUE @@ -1739,6 +1736,12 @@ lim_enc_type_matched(tpAniSirGlobal mac_ctx, session->wps_registration) return true; + pe_debug("AP:: Privacy %d WPA %d RSN %d, SELF:: Privacy %d Enc %d OSEN %d WPS %d", + bcn->capabilityInfo.privacy, bcn->wpaPresent, bcn->rsnPresent, + SIR_MAC_GET_PRIVACY(session->limCurrentBssCaps), + session->encryptType, session->isOSENConnection, + session->wps_registration); + return false; } @@ -2102,9 +2105,6 @@ lim_roam_fill_bss_descr(tpAniSirGlobal pMac, return QDF_STATUS_E_FAILURE; } - pe_debug("LFR3:Beacon/Prb Rsp: %d", roam_offload_synch_ind_ptr->isBeacon); - QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_PE, QDF_TRACE_LEVEL_DEBUG, - bcn_proberesp_ptr, roam_offload_synch_ind_ptr->beaconProbeRespLength); if (roam_offload_synch_ind_ptr->isBeacon) { if (sir_parse_beacon_ie(pMac, parsed_frm_ptr, &bcn_proberesp_ptr[SIR_MAC_HDR_LEN_3A + @@ -2144,6 +2144,7 @@ lim_roam_fill_bss_descr(tpAniSirGlobal pMac, ie_len = roam_offload_synch_ind_ptr->beaconProbeRespLength - (SIR_MAC_HDR_LEN_3A + SIR_MAC_B_PR_SSID_OFFSET); } + /* * Length of BSS desription is without length of * length itself and length of pointer @@ -2188,17 +2189,22 @@ lim_roam_fill_bss_descr(tpAniSirGlobal pMac, qdf_mem_copy(&bss_desc_ptr->capabilityInfo, &bcn_proberesp_ptr[SIR_MAC_HDR_LEN_3A + SIR_MAC_B_PR_CAPAB_OFFSET], 2); - if (qdf_is_macaddr_zero((struct qdf_mac_addr *)mac_hdr->bssId)) { - pe_debug("bssid is 0 in beacon/probe update it with bssId %pM in sync ind", - roam_offload_synch_ind_ptr->bssid.bytes); - qdf_mem_copy(mac_hdr->bssId, - roam_offload_synch_ind_ptr->bssid.bytes, - sizeof(tSirMacAddr)); - } + /* + * overwrite the BSSID with the firmware provided BSSID as some buggy + * AP's are not sending correct BSSID in probe resp + */ + pe_debug("LFR3:Beacon/Prb Rsp: %d bssid %pM in bcn, bssId %pM in sync ind", + roam_offload_synch_ind_ptr->isBeacon, mac_hdr->bssId, + roam_offload_synch_ind_ptr->bssid.bytes); + + qdf_mem_copy(mac_hdr->bssId, + roam_offload_synch_ind_ptr->bssid.bytes, + sizeof(tSirMacAddr)); qdf_mem_copy((uint8_t *) &bss_desc_ptr->bssId, - (uint8_t *) mac_hdr->bssId, - sizeof(tSirMacAddr)); + (uint8_t *) mac_hdr->bssId, + sizeof(tSirMacAddr)); + bss_desc_ptr->received_time = (uint64_t)qdf_mc_timer_get_system_time(); if (parsed_frm_ptr->mdiePresent) { @@ -2207,11 +2213,8 @@ lim_roam_fill_bss_descr(tpAniSirGlobal pMac, (uint8_t *)parsed_frm_ptr->mdie, SIR_MDIE_SIZE); } - pe_debug("LFR3: BssDescr Info:"); - QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_PE, QDF_TRACE_LEVEL_DEBUG, - bss_desc_ptr->bssId, sizeof(tSirMacAddr)); pe_debug("chan: %d rssi: %d", bss_desc_ptr->channelId, - bss_desc_ptr->rssi); + bss_desc_ptr->rssi); if (ie_len) { qdf_mem_copy(&bss_desc_ptr->ieFields, bcn_proberesp_ptr + @@ -2235,47 +2238,100 @@ lim_roam_fill_bss_descr(tpAniSirGlobal pMac, * * Return: None */ -static void lim_copy_and_free_hlp_data_from_session(tpPESession session_ptr, - roam_offload_synch_ind *roam_sync_ind_ptr) +static void +lim_copy_and_free_hlp_data_from_session(tpPESession session_ptr, + roam_offload_synch_ind + *roam_sync_ind_ptr) { - if (session_ptr->hlp_data && session_ptr->hlp_data_len) { - cds_copy_hlp_info(&session_ptr->dst_mac, - &session_ptr->src_mac, - session_ptr->hlp_data_len, - session_ptr->hlp_data, - &roam_sync_ind_ptr->dst_mac, - &roam_sync_ind_ptr->src_mac, - &roam_sync_ind_ptr->hlp_data_len, - roam_sync_ind_ptr->hlp_data); - qdf_mem_free(session_ptr->hlp_data); - session_ptr->hlp_data = NULL; - session_ptr->hlp_data_len = 0; + if (session_ptr->fils_info->hlp_data && + session_ptr->fils_info->hlp_data_len) { + cds_copy_hlp_info(&session_ptr->fils_info->dst_mac, + &session_ptr->fils_info->src_mac, + session_ptr->fils_info->hlp_data_len, + session_ptr->fils_info->hlp_data, + &roam_sync_ind_ptr->dst_mac, + &roam_sync_ind_ptr->src_mac, + &roam_sync_ind_ptr->hlp_data_len, + roam_sync_ind_ptr->hlp_data); + + qdf_mem_free(session_ptr->fils_info->hlp_data); + session_ptr->fils_info->hlp_data = NULL; + session_ptr->fils_info->hlp_data_len = 0; } } #else -static inline void lim_copy_and_free_hlp_data_from_session( - tpPESession session_ptr, +static inline void +lim_copy_and_free_hlp_data_from_session(tpPESession session_ptr, roam_offload_synch_ind *roam_sync_ind_ptr) {} #endif -/** - * pe_roam_synch_callback() - PE level callback for roam synch propagation - * @mac_ctx: MAC Context - * @roam_sync_ind_ptr: Roam synch indication buffer pointer - * @bss_desc: BSS Descriptor pointer - * @reason: Reason for calling callback which decides the action to be taken. - * - * This is a PE level callback called from WMA to complete the roam synch - * propagation at PE level and also fill the BSS descriptor which will be - * helpful further to complete the roam synch propagation. - * - * Return: Success or Failure status - */ -QDF_STATUS pe_roam_synch_callback(tpAniSirGlobal mac_ctx, - roam_offload_synch_ind *roam_sync_ind_ptr, - tpSirBssDescription bss_desc, enum sir_roam_op_code reason) +#ifdef WLAN_FEATURE_FILS_SK +static void +lim_fill_fils_ft(tpPESession src_session, + tpPESession dst_session) +{ + if (src_session->fils_info && + src_session->fils_info->fils_ft_len) { + dst_session->fils_info->fils_ft_len = + src_session->fils_info->fils_ft_len; + qdf_mem_copy(dst_session->fils_info->fils_ft, + src_session->fils_info->fils_ft, + src_session->fils_info->fils_ft_len); + } +} +#else +static inline void +lim_fill_fils_ft(tpPESession src_session, + tpPESession dst_session) +{} +#endif + +QDF_STATUS +pe_disconnect_callback(tpAniSirGlobal mac, uint8_t vdev_id, + uint8_t *deauth_disassoc_frame, + uint16_t deauth_disassoc_frame_len, + uint16_t reason_code) +{ + tpPESession session; + + session = pe_find_session_by_sme_session_id(mac, vdev_id); + if (!session) { + pe_err("LFR3: Vdev %d doesn't exist", vdev_id); + return QDF_STATUS_E_FAILURE; + } + + if (!((session->limMlmState == eLIM_MLM_LINK_ESTABLISHED_STATE) && + (session->limSmeState != eLIM_SME_WT_DISASSOC_STATE) && + (session->limSmeState != eLIM_SME_WT_DEAUTH_STATE))) { + pe_info("Cannot handle in mlmstate %d sme state %d as vdev_id:%d is not in connected state", + session->limMlmState, session->limSmeState, vdev_id); + return QDF_STATUS_SUCCESS; + } + + if (deauth_disassoc_frame && + deauth_disassoc_frame_len > SIR_MAC_MIN_IE_LEN) { + lim_extract_ies_from_deauth_disassoc(mac, session->peSessionId, + deauth_disassoc_frame, + deauth_disassoc_frame_len); + + reason_code = sir_read_u16(deauth_disassoc_frame + + sizeof(struct wlan_frame_hdr)); + } + + lim_tear_down_link_with_ap(mac, session->peSessionId, + reason_code, + eLIM_PEER_ENTITY_DEAUTH); + + return QDF_STATUS_SUCCESS; +} + +QDF_STATUS +pe_roam_synch_callback(tpAniSirGlobal mac_ctx, + roam_offload_synch_ind *roam_sync_ind_ptr, + tpSirBssDescription bss_desc, + enum sir_roam_op_code reason) { tpPESession session_ptr; tpPESession ft_session_ptr; @@ -2354,8 +2410,9 @@ QDF_STATUS pe_roam_synch_callback(tpAniSirGlobal mac_ctx, status = QDF_STATUS_E_FAILURE; ft_session_ptr = pe_create_session(mac_ctx, bss_desc->bssId, &session_id, mac_ctx->lim.maxStation, - eSIR_INFRASTRUCTURE_MODE); - if (ft_session_ptr == NULL) { + session_ptr->bssType, session_ptr->smeSessionId, + session_ptr->pePersona); + if (!ft_session_ptr) { pe_err("LFR3:Cannot create PE Session"); lim_print_mac_addr(mac_ctx, bss_desc->bssId, LOGE); return status; @@ -2386,6 +2443,10 @@ QDF_STATUS pe_roam_synch_callback(tpAniSirGlobal mac_ctx, /* Next routine may update nss based on dot11Mode */ lim_ft_prepare_add_bss_req(mac_ctx, false, ft_session_ptr, bss_desc); + + if (session_ptr->is11Rconnection) + lim_fill_fils_ft(session_ptr, ft_session_ptr); + roam_sync_ind_ptr->add_bss_params = (tpAddBssParams) ft_session_ptr->ftPEContext.pAddBssReq; add_bss_params = ft_session_ptr->ftPEContext.pAddBssReq; @@ -2435,10 +2496,6 @@ QDF_STATUS pe_roam_synch_callback(tpAniSirGlobal mac_ctx, roam_sync_ind_ptr->reassocRespOffset, mac_ctx->roam.reassocRespLen); - pe_debug("LFR3:the reassoc resp frame data:"); - QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - mac_ctx->roam.pReassocResp, - mac_ctx->roam.reassocRespLen); ft_session_ptr->bRoamSynchInProgress = true; lim_process_assoc_rsp_frame(mac_ctx, mac_ctx->roam.pReassocResp, @@ -2634,33 +2691,44 @@ tMgmtFrmDropReason lim_is_pkt_candidate_for_drop(tpAniSirGlobal pMac, curr_seq_num); return eMGMT_DROP_DUPLICATE_AUTH_FRAME; } - } else if ((subType == SIR_MAC_MGMT_ASSOC_REQ) && - (subType == SIR_MAC_MGMT_DISASSOC) && + } else if ((subType == SIR_MAC_MGMT_ASSOC_REQ) || + (subType == SIR_MAC_MGMT_DISASSOC) || (subType == SIR_MAC_MGMT_DEAUTH)) { - uint16_t assoc_id; - dphHashTableClass *dph_table; - tDphHashNode *sta_ds; + struct peer_mlme_priv_obj *peer_priv; + struct wlan_objmgr_peer *peer; qdf_time_t *timestamp; pHdr = WMA_GET_RX_MAC_HEADER(pRxPacketInfo); psessionEntry = pe_find_session_by_bssid(pMac, pHdr->bssId, &sessionId); if (!psessionEntry) - return eMGMT_DROP_NO_DROP; - dph_table = &psessionEntry->dph.dphHashTable; - sta_ds = dph_lookup_hash_entry(pMac, pHdr->sa, &assoc_id, - dph_table); - if (!sta_ds) { + return eMGMT_DROP_SPURIOUS_FRAME; + + peer = wlan_objmgr_get_peer_by_mac(pMac->psoc, + pHdr->sa, + WLAN_LEGACY_MAC_ID); + if (!peer) { if (subType == SIR_MAC_MGMT_ASSOC_REQ) - return eMGMT_DROP_NO_DROP; - else - return eMGMT_DROP_EXCESSIVE_MGMT_FRAME; + return eMGMT_DROP_NO_DROP; + + return eMGMT_DROP_SPURIOUS_FRAME; } + peer_priv = wlan_objmgr_peer_get_comp_private_obj(peer, + WLAN_UMAC_COMP_MLME); + if (!peer_priv) { + wlan_objmgr_peer_release_ref(peer, WLAN_LEGACY_MAC_ID); + if (subType == SIR_MAC_MGMT_ASSOC_REQ) + return eMGMT_DROP_NO_DROP; + + return eMGMT_DROP_SPURIOUS_FRAME; + } if (subType == SIR_MAC_MGMT_ASSOC_REQ) - timestamp = &sta_ds->last_assoc_received_time; + timestamp = &peer_priv->last_assoc_received_time; else - timestamp = &sta_ds->last_disassoc_deauth_received_time; + timestamp = + &peer_priv->last_disassoc_deauth_received_time; + if (*timestamp > 0 && qdf_system_time_before(qdf_get_system_timestamp(), *timestamp + @@ -2670,10 +2738,12 @@ tMgmtFrmDropReason lim_is_pkt_candidate_for_drop(tpAniSirGlobal pMac, (int)(qdf_get_system_timestamp() - *timestamp), "of last frame. Allow it only after", LIM_DOS_PROTECTION_TIME); + wlan_objmgr_peer_release_ref(peer, WLAN_LEGACY_MAC_ID); return eMGMT_DROP_EXCESSIVE_MGMT_FRAME; } *timestamp = qdf_get_system_timestamp(); + wlan_objmgr_peer_release_ref(peer, WLAN_LEGACY_MAC_ID); } @@ -2752,8 +2822,9 @@ void lim_mon_init_session(tpAniSirGlobal mac_ptr, psession_entry = pe_create_session(mac_ptr, msg->bss_id.bytes, &session_id, mac_ptr->lim.maxStation, - eSIR_MONITOR_MODE); - if (psession_entry == NULL) { + eSIR_MONITOR_MODE, + msg->vdev_id, QDF_MONITOR_MODE); + if (!psession_entry) { pe_err("Monitor mode: Session Can not be created"); lim_print_mac_addr(mac_ptr, msg->bss_id.bytes, LOGE); return; @@ -2761,6 +2832,17 @@ void lim_mon_init_session(tpAniSirGlobal mac_ptr, psession_entry->vhtCapability = 1; } +void lim_mon_deinit_session(tpAniSirGlobal mac_ptr, + struct sir_delete_session *msg) +{ + tpPESession session; + + session = pe_find_session_by_session_id(mac_ptr, msg->vdev_id); + + if (session && session->bssType == eSIR_MONITOR_MODE) + pe_delete_session(mac_ptr, session); +} + /** * lim_update_ext_cap_ie() - Update Extended capabilities IE(if present) * with capabilities of Fine Time measurements(FTM) if set in driver diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_assoc_utils.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_assoc_utils.c index 95c3e55be4af..2235e7200269 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_assoc_utils.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_assoc_utils.c @@ -48,11 +48,13 @@ #include "lim_ibss_peer_mgmt.h" #include "lim_ft_defs.h" #include "lim_session.h" +#include "lim_process_fils.h" #include "qdf_types.h" #include "wma_types.h" #include "lim_types.h" #include "wlan_utility.h" +#include #ifdef FEATURE_WLAN_TDLS #define IS_TDLS_PEER(type) ((type) == STA_ENTRY_TDLS_PEER) @@ -685,13 +687,6 @@ lim_send_del_sta_cnf(tpAniSirGlobal pMac, struct qdf_mac_addr sta_dsaddr, eLIM_LINK_MONITORING_DISASSOC) || (mlmStaContext.cleanupTrigger == eLIM_PROMISCUOUS_MODE_DISASSOC)) { - /** - * Host or LMM driven Disassociation. - * Issue Disassoc Confirm to SME. - */ - pe_debug("Lim Posting DISASSOC_CNF to Sme. Trigger: %d", - mlmStaContext.cleanupTrigger); - qdf_mem_copy((uint8_t *) &mlmDisassocCnf.peerMacAddr, (uint8_t *) sta_dsaddr.bytes, QDF_MAC_ADDR_SIZE); mlmDisassocCnf.resultCode = statusCode; @@ -706,12 +701,6 @@ lim_send_del_sta_cnf(tpAniSirGlobal pMac, struct qdf_mac_addr sta_dsaddr, eLIM_HOST_DEAUTH) || (mlmStaContext.cleanupTrigger == eLIM_LINK_MONITORING_DEAUTH)) { - /** - * Host or LMM driven Deauthentication. - * Issue Deauth Confirm to SME. - */ - pe_debug("Lim Posting DEAUTH_CNF to Sme. Trigger: %d", - mlmStaContext.cleanupTrigger); qdf_copy_macaddr(&mlmDeauthCnf.peer_macaddr, &sta_dsaddr); mlmDeauthCnf.resultCode = statusCode; mlmDeauthCnf.deauthTrigger = mlmStaContext.cleanupTrigger; @@ -724,12 +713,6 @@ lim_send_del_sta_cnf(tpAniSirGlobal pMac, struct qdf_mac_addr sta_dsaddr, } else if ((mlmStaContext.cleanupTrigger == eLIM_PEER_ENTITY_DISASSOC) || (mlmStaContext.cleanupTrigger == eLIM_PEER_ENTITY_DEAUTH)) { - /** - * Received Disassociation/Deauthentication from peer. - * Issue Purge Ind to SME. - */ - pe_debug("Lim Posting PURGE_STA_IND to Sme. Trigger: %d", - mlmStaContext.cleanupTrigger); qdf_mem_copy((uint8_t *) &mlmPurgeStaInd.peerMacAddr, (uint8_t *) sta_dsaddr.bytes, QDF_MAC_ADDR_SIZE); mlmPurgeStaInd.reasonCode = @@ -801,12 +784,6 @@ lim_send_del_sta_cnf(tpAniSirGlobal pMac, struct qdf_mac_addr sta_dsaddr, } } else if (mlmStaContext.cleanupTrigger == eLIM_DUPLICATE_ENTRY) { - /** - * LIM driven Disassociation. - * Issue Disassoc Confirm to SME. - */ - pe_debug("Lim Posting DISASSOC_CNF to Sme. Trigger: %d", - mlmStaContext.cleanupTrigger); qdf_mem_copy((uint8_t *) &mlmDisassocCnf.peerMacAddr, (uint8_t *) sta_dsaddr.bytes, QDF_MAC_ADDR_SIZE); @@ -1467,9 +1444,8 @@ QDF_STATUS lim_populate_vht_mcs_set(tpAniSirGlobal mac_ctx, } } - pe_debug("enable2x2 - %d nss %d vhtRxMCSMap - %x vhtTxMCSMap - %x", - mac_ctx->roam.configParam.enable2x2, nss, - rates->vhtRxMCSMap, rates->vhtTxMCSMap); + pe_debug("RxMCSMap %x TxMCSMap %x", rates->vhtRxMCSMap, + rates->vhtTxMCSMap); if (NULL != session_entry) { session_entry->supported_nss_1x1 = @@ -1485,34 +1461,50 @@ QDF_STATUS lim_populate_vht_mcs_set(tpAniSirGlobal mac_ctx, return QDF_STATUS_E_FAILURE; } -/** - * lim_populate_own_rate_set() - comprises the basic and extended rates read - * from CFG - * @mac_ctx: pointer to global mac structure - * @rates: pointer to supported rates - * @supported_mcs_set: pointer to supported mcs rates - * @basic_only: update only basic rates if set true - * @session_entry: pe session entry - * @vht_caps: pointer to vht capability - * - * This function is called by limProcessAssocRsp() or - * lim_add_staInIBSS() - * - It creates a combined rate set of 12 rates max which - * comprises the basic and extended rates read from CFG - * - It sorts the combined rate Set and copy it in the - * rate array of the pSTA descriptor - * - It sets the erpEnabled bit of the STA descriptor - * ERP bit is set iff the dph PHY mode is 11G and there is at least - * an A rate in the supported or extended rate sets - * - * Return: QDF_STATUS_SUCCESS or QDF_STATUS_E_FAILURE. - */ -QDF_STATUS -lim_populate_own_rate_set(tpAniSirGlobal mac_ctx, - tpSirSupportedRates rates, uint8_t *supported_mcs_set, - uint8_t basic_only, tpPESession session_entry, - struct sDot11fIEVHTCaps *vht_caps, - struct sDot11fIEhe_cap *he_caps) +static void lim_dump_ht_mcs_mask(uint8_t *self_mcs, uint8_t *peer_mcs) +{ + uint32_t len = 0; + uint8_t idx; + uint8_t *buff; + uint32_t buff_len; + + /* + * Buffer of (SIR_MAC_MAX_SUPPORTED_MCS_SET * 5) + 1 to consider the 4 + * char MCS eg 0xff and 1 space after it and 1 to end the string with + * NULL. + */ + buff_len = (SIR_MAC_MAX_SUPPORTED_MCS_SET * 5) + 1; + buff = qdf_mem_malloc(buff_len); + if (!buff) + return; + + if (self_mcs) { + for (idx = 0; idx < SIR_MAC_MAX_SUPPORTED_MCS_SET; idx++) + len += qdf_scnprintf(buff + len, buff_len - len, + "0x%x ", self_mcs[idx]); + + pe_nofl_debug("SELF HT MCS: %s", buff); + } + + if (peer_mcs) { + len = 0; + for (idx = 0; idx < SIR_MAC_MAX_SUPPORTED_MCS_SET; idx++) + len += qdf_scnprintf(buff + len, buff_len - len, + "0x%x ", peer_mcs[idx]); + + pe_nofl_debug("PEER HT MCS: %s", buff); + } + + qdf_mem_free(buff); +} + +QDF_STATUS lim_populate_own_rate_set(tpAniSirGlobal mac_ctx, + tpSirSupportedRates rates, + uint8_t *supported_mcs_set, + uint8_t basic_only, + tpPESession session_entry, + struct sDot11fIEVHTCaps *vht_caps, + struct sDot11fIEhe_cap *he_caps) { tSirMacRateSet temp_rate_set; tSirMacRateSet temp_rate_set2; @@ -1621,9 +1613,7 @@ lim_populate_own_rate_set(tpAniSirGlobal mac_ctx, supported_mcs_set[i]; } - pe_debug("MCS Rate Set Bitmap: "); - for (i = 0; i < SIR_MAC_MAX_SUPPORTED_MCS_SET; i++) - pe_debug("%x ", rates->supportedMCSSet[i]); + lim_dump_ht_mcs_mask(rates->supportedMCSSet, NULL); } lim_populate_vht_mcs_set(mac_ctx, rates, vht_caps, session_entry, session_entry->nss); @@ -1772,9 +1762,8 @@ lim_populate_peer_rate_set(tpAniSirGlobal pMac, pRates->supportedMCSSet[i] &= pSupportedMCSSet[i]; } - pe_debug("MCS Rate Set Bitmap: "); - for (i = 0; i < SIR_MAC_MAX_SUPPORTED_MCS_SET; i++) - pe_debug("%x ", pRates->supportedMCSSet[i]); + + lim_dump_ht_mcs_mask(NULL, pRates->supportedMCSSet); if (pRates->supportedMCSSet[0] == 0) { pe_debug("Incorrect MCS 0 - 7. They must be supported"); @@ -1783,8 +1772,6 @@ lim_populate_peer_rate_set(tpAniSirGlobal pMac, psessionEntry->supported_nss_1x1 = ((pRates->supportedMCSSet[1] != 0) ? false : true); - pe_debug("HT supported nss 1x1: %d", - psessionEntry->supported_nss_1x1); } lim_populate_vht_mcs_set(pMac, pRates, pVHTCaps, psessionEntry, psessionEntry->nss); @@ -1800,7 +1787,8 @@ lim_populate_peer_rate_set(tpAniSirGlobal pMac, } else if (pRates->supportedMCSSet[1] == 0) { psessionEntry->nss = NSS_1x1_MODE; } - pe_debug("nss: %d", psessionEntry->nss); + pe_debug("nss 1x1 %d nss %d", psessionEntry->supported_nss_1x1, + psessionEntry->nss); return QDF_STATUS_SUCCESS; } /*** lim_populate_peer_rate_set() ***/ @@ -2016,12 +2004,8 @@ QDF_STATUS lim_populate_matching_rate_set(tpAniSirGlobal mac_ctx, sta_ds->supportedRates.supportedMCSSet[i] = mcs_set[i] & supported_mcs_set[i]; - pe_debug("lim_populate_matching_rate_set: MCS Rate Set Bitmap" - " from CFG and DPH : "); - for (i = 0; i < SIR_MAC_MAX_SUPPORTED_MCS_SET; i++) { - pe_debug("%x %x ", mcs_set[i], - sta_ds->supportedRates.supportedMCSSet[i]); - } + lim_dump_ht_mcs_mask(mcs_set, + sta_ds->supportedRates.supportedMCSSet); } lim_populate_vht_mcs_set(mac_ctx, &sta_ds->supportedRates, vht_caps, session_entry, session_entry->nss); @@ -2544,6 +2528,20 @@ lim_add_sta(tpAniSirGlobal mac_ctx, add_sta_params->stbc_capable = 0; } + if (session_entry->pePersona == QDF_SAP_MODE || + session_entry->pePersona == QDF_P2P_GO_MODE) { + if (session_entry->parsedAssocReq) { + uint16_t aid = sta_ds->assocId; + /* Get a copy of the already parsed Assoc Request */ + assoc_req = + (tpSirAssocReq) session_entry->parsedAssocReq[aid]; + + add_sta_params->wpa_rsn = assoc_req->rsnPresent; + add_sta_params->wpa_rsn |= + (assoc_req->wpaPresent << 1); + } + } + lim_update_he_stbc_capable(add_sta_params); msg_q.type = WMA_ADD_STA_REQ; @@ -2760,13 +2758,7 @@ lim_add_sta_self(tpAniSirGlobal pMac, uint16_t staIdx, uint8_t updateSta, wlan_cfg_get_int(pMac, WNI_CFG_DOT11_MODE, &selfStaDot11Mode); wlan_cfg_get_int(pMac, WNI_CFG_HT_CAP_INFO_SUPPORTED_CHAN_WIDTH_SET, &selfTxWidth); - pe_debug("cfgDot11Mode: %d selfTxWidth: %d", - (int)selfStaDot11Mode, (int)selfTxWidth); - pe_debug("Roam Channel Bonding Mode %d", - (int)pMac->roam.configParam.uCfgDot11Mode); - sir_copy_mac_addr(staMac, psessionEntry->selfMacAddr); - pe_debug(MAC_ADDRESS_STR ": ", MAC_ADDR_ARRAY(staMac)); pAddStaParams = qdf_mem_malloc(sizeof(tAddStaParams)); if (NULL == pAddStaParams) { pe_err("Unable to allocate memory during ADD_STA"); @@ -2852,38 +2844,16 @@ lim_add_sta_self(tpAniSirGlobal pMac, uint16_t staIdx, uint8_t updateSta, psessionEntry->htConfig.ht_sgi20; pAddStaParams->fShortGI40Mhz = psessionEntry->htConfig.ht_sgi40; - pe_debug("greenFieldCapable: %d maxAmpduDensity: %d " - "maxAmpduSize: %d", - pAddStaParams->greenFieldCapable, - pAddStaParams->maxAmpduDensity, - pAddStaParams->maxAmpduSize); - - pe_debug("fDsssCckMode40Mhz: %d fShortGI20Mhz: %d " - "fShortGI40Mhz: %d lsigTxopProtection: %d", - pAddStaParams->fDsssCckMode40Mhz, - pAddStaParams->fShortGI20Mhz, - pAddStaParams->fShortGI40Mhz, - pAddStaParams->lsigTxopProtection); - - pe_debug("maxAmsduSize: %d txChannelWidth: %d mimoPS: %d rifsMode %d", - pAddStaParams->maxAmsduSize, - pAddStaParams->ch_width, - pAddStaParams->mimoPS, pAddStaParams->rifsMode); } } pAddStaParams->vhtCapable = IS_DOT11_MODE_VHT(selfStaDot11Mode); - if (pAddStaParams->vhtCapable) { + if (pAddStaParams->vhtCapable) pAddStaParams->ch_width = psessionEntry->ch_width; - pe_debug("VHT WIDTH SET %d", pAddStaParams->ch_width); - } pAddStaParams->vhtTxBFCapable = psessionEntry->vht_config.su_beam_formee; pAddStaParams->enable_su_tx_bformer = psessionEntry->vht_config.su_beam_former; - pe_debug("vhtCapable: %d vhtTxBFCapable %d, su_bfer %d", - pAddStaParams->vhtCapable, pAddStaParams->vhtTxBFCapable, - pAddStaParams->enable_su_tx_bformer); /* In 11ac mode, the hardware is capable of supporting 128K AMPDU size */ if (IS_DOT11_MODE_VHT(selfStaDot11Mode)) { @@ -2920,37 +2890,25 @@ lim_add_sta_self(tpAniSirGlobal pMac, uint16_t staIdx, uint8_t updateSta, pAddStaParams->p2pCapableSta = 1; } - pe_debug(" StaIdx: %d updateSta = %d htcapable = %d ", - pAddStaParams->staIdx, pAddStaParams->updateSta, - pAddStaParams->htCapable); - - pe_debug("htLdpcCapable: %d vhtLdpcCapable: %d " - "p2pCapableSta: %d", - pAddStaParams->htLdpcCapable, pAddStaParams->vhtLdpcCapable, - pAddStaParams->p2pCapableSta); - if (psessionEntry->isNonRoamReassoc) { pAddStaParams->nonRoamReassoc = 1; psessionEntry->isNonRoamReassoc = 0; } - pe_debug("sessionid: %d Assoc ID: %d listenInterval = %d " - "shortPreambleSupported: %d", - psessionEntry->smeSessionId, pAddStaParams->assocId, - pAddStaParams->listenInterval, - pAddStaParams->shortPreambleSupported); if (IS_DOT11_MODE_HE(selfStaDot11Mode)) lim_add_self_he_cap(pAddStaParams, psessionEntry); + if (lim_is_fils_connection(psessionEntry)) + pAddStaParams->no_ptk_4_way = true; + msgQ.type = WMA_ADD_STA_REQ; msgQ.reserved = 0; msgQ.bodyptr = pAddStaParams; msgQ.bodyval = 0; - pe_debug(MAC_ADDRESS_STR ":Sessionid %d : " - "Sending WMA_ADD_STA_REQ. (aid %d)", - MAC_ADDR_ARRAY(pAddStaParams->staMac), - pAddStaParams->sessionId, pAddStaParams->assocId); + pe_debug(QDF_MAC_ADDR_STR ": vdev %d Sending WMA_ADD_STA_REQ.LI %d", + QDF_MAC_ADDR_ARRAY(pAddStaParams->staMac), + psessionEntry->smeSessionId, pAddStaParams->listenInterval); MTRACE(mac_trace_msg_tx(pMac, psessionEntry->peSessionId, msgQ.type)); retCode = wma_post_ctrl_msg(pMac, &msgQ); @@ -3211,8 +3169,9 @@ lim_check_and_announce_join_success(tpAniSirGlobal mac_ctx, if (!LIM_IS_STA_ROLE(session_entry)) return; - pe_debug("Received Beacon/PR with matching BSSID:%pM PESessionID %d", - session_entry->bssId, session_entry->peSessionId); + pe_debug("Received Beacon/PR with BSSID:%pM pe session %d vdev %d", + session_entry->bssId, session_entry->peSessionId, + session_entry->smeSessionId); /* Deactivate Join Failure timer */ lim_deactivate_and_change_timer(mac_ctx, eLIM_JOIN_FAIL_TIMER); @@ -3369,9 +3328,6 @@ QDF_STATUS lim_extract_ap_capabilities(tpAniSirGlobal pMac, { qdf_mem_zero((uint8_t *) beaconStruct, sizeof(tSirProbeRespBeacon)); - pe_debug("lim_extract_ap_capabilities: The IE's being received are:"); - QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_PE, QDF_TRACE_LEVEL_DEBUG, - pIE, ieLen); /* Parse the Beacon IE's, Don't try to parse if we dont have anything in IE */ if (ieLen > 0) { if (QDF_STATUS_SUCCESS != @@ -3447,14 +3403,9 @@ lim_del_bss(tpAniSirGlobal pMac, tpDphHashNode pStaDs, uint16_t bssIdx, qdf_mem_copy(pDelBssParams->bssid, psessionEntry->bssId, sizeof(tSirMacAddr)); pDelBssParams->smesessionId = psessionEntry->smeSessionId; - pe_debug("Sessionid %d : Sending HAL_DELETE_BSS_REQ " - "for bss idx: %X BSSID:" MAC_ADDRESS_STR, - pDelBssParams->sessionId, pDelBssParams->bssIdx, - MAC_ADDR_ARRAY(psessionEntry->bssId)); /* we need to defer the message until we get the response back from HAL. */ SET_LIM_PROCESS_DEFD_MESGS(pMac, false); - pe_debug("process_ho_fail = %d", psessionEntry->process_ho_fail); if (psessionEntry->process_ho_fail) msgQ.type = WMA_DELETE_BSS_HO_FAIL_REQ; else @@ -3464,6 +3415,9 @@ lim_del_bss(tpAniSirGlobal pMac, tpDphHashNode pStaDs, uint16_t bssIdx, msgQ.bodyval = 0; MTRACE(mac_trace_msg_tx(pMac, psessionEntry->peSessionId, msgQ.type)); + pe_debug("Sessionid %d : Sending HAL_DELETE_BSS_REQ bss idx: %x BSSID:" QDF_MAC_ADDR_STR, + psessionEntry->peSessionId, pDelBssParams->bssIdx, + QDF_MAC_ADDR_ARRAY(psessionEntry->bssId)); retCode = wma_post_ctrl_msg(pMac, &msgQ); if (QDF_STATUS_SUCCESS != retCode) { @@ -3534,8 +3488,6 @@ static void lim_update_vhtcaps_assoc_resp(tpAniSirGlobal mac_ctx, pAddBssParams->staContext.maxAmpduSize = SIR_MAC_GET_VHT_MAX_AMPDU_EXPO( pAddBssParams->staContext.vht_caps); - - pe_debug("Updating VHT caps in assoc Response"); } /** @@ -3561,7 +3513,6 @@ static void lim_update_vht_oper_assoc_resp(tpAniSirGlobal mac_ctx, pAddBssParams->ch_center_freq_seg1 = vht_oper->chanCenterFreqSeg2; } - pe_debug("Updating VHT Operation in assoc Response"); } #ifdef WLAN_SUPPORT_TWT @@ -3610,7 +3561,6 @@ static inline void lim_set_sta_ctx_twt(tAddStaParams *sta_ctx, * bssDescription bssDescription passed to PE from the SME * @return None */ - QDF_STATUS lim_sta_send_add_bss(tpAniSirGlobal pMac, tpSirAssocRsp pAssocRsp, tpSchBeaconStruct pBeaconStruct, tpSirBssDescription bssDescription, @@ -3642,12 +3592,6 @@ QDF_STATUS lim_sta_send_add_bss(tpAniSirGlobal pMac, tpSirAssocRsp pAssocRsp, qdf_mem_copy(pAddBssParams->selfMacAddr, psessionEntry->selfMacAddr, sizeof(tSirMacAddr)); - pe_debug("sessionid: %d updateEntry: %d limsystemrole: %d", - psessionEntry->smeSessionId, updateEntry, - GET_LIM_SYSTEM_ROLE(psessionEntry)); - - pe_debug("BSSID: " MAC_ADDRESS_STR, MAC_ADDR_ARRAY(pAddBssParams->bssId)); - pAddBssParams->bssType = eSIR_INFRASTRUCTURE_MODE; pAddBssParams->operMode = BSS_OPERATIONAL_MODE_STA; @@ -3691,25 +3635,7 @@ QDF_STATUS lim_sta_send_add_bss(tpAniSirGlobal pMac, tpSirAssocRsp pAssocRsp, pAddBssParams->ht20Coexist = (uint8_t) psessionEntry->beaconParams.ht20Coexist; - pe_debug("BSS Type %d Beacon Interval: %d dtimPeriod: %d " - "cfpCount: %d", pAddBssParams->bssType, - pAddBssParams->beaconInterval, pAddBssParams->dtimPeriod, - pAddBssParams->cfParamSet.cfpCount); - - pe_debug("cfpPeriod: %d cfpMaxDuration: %d cfpDurRemaining: %d " - "numRates: %d", pAddBssParams->cfParamSet.cfpPeriod, - pAddBssParams->cfParamSet.cfpMaxDuration, - pAddBssParams->cfParamSet.cfpDurRemaining, - pAddBssParams->rateSet.numRates); - - pe_debug("nwType:%d shortSlotTimeSupported: %d llaCoexist: %d " - "llbCoexist: %d llgCoexist: %d ht20Coexist: %d", - pAddBssParams->nwType, pAddBssParams->shortSlotTimeSupported, - pAddBssParams->llaCoexist, pAddBssParams->llbCoexist, - pAddBssParams->llgCoexist, pAddBssParams->ht20Coexist); - pAddBssParams->dot11_mode = psessionEntry->dot11mode; - pe_debug("dot11_mode: %d", pAddBssParams->dot11_mode); if (IS_DOT11_MODE_HT(psessionEntry->dot11mode)) chanWidthSupp = lim_get_ht_capability(pMac, @@ -3720,7 +3646,6 @@ QDF_STATUS lim_sta_send_add_bss(tpAniSirGlobal pMac, tpSirAssocRsp pAssocRsp, if (IS_DOT11_MODE_HT(psessionEntry->dot11mode) && (pAssocRsp->HTCaps.present)) { pAddBssParams->htCapable = pAssocRsp->HTCaps.present; - pe_debug("htCapable: %d", pAddBssParams->htCapable); if (pBeaconStruct->HTInfo.present) { pAddBssParams->htOperMode = (tSirMacHTOperatingMode) pAssocRsp->HTInfo.opMode; @@ -3749,23 +3674,10 @@ QDF_STATUS lim_sta_send_add_bss(tpAniSirGlobal pMac, tpSirAssocRsp pAssocRsp, (uint8_t) pAssocRsp->HTInfo. lsigTXOPProtectionFullSupport; pAddBssParams->fRIFSMode = pAssocRsp->HTInfo.rifsMode; - - pe_debug("htOperMode: %d dualCTSProtection: %d txChannelWidth: %d center_freq_0: %d", - pAddBssParams->htOperMode, - pAddBssParams->dualCTSProtection, - pAddBssParams->ch_width, - pAddBssParams->ch_center_freq_seg0); - - pe_debug("llnNonGFCoexist: %d " - "fLsigTXOPProtectionFullSupport: %d fRIFSMode %d", - pAddBssParams->llnNonGFCoexist, - pAddBssParams->fLsigTXOPProtectionFullSupport, - pAddBssParams->fRIFSMode); } } pAddBssParams->currentOperChannel = bssDescription->channelId; - pe_debug("currentOperChannel %d", pAddBssParams->currentOperChannel); if (psessionEntry->vhtCapability && (pAssocRsp->VHTCaps.present)) { pAddBssParams->vhtCapable = pAssocRsp->VHTCaps.present; vht_caps = &pAssocRsp->VHTCaps; @@ -3789,11 +3701,6 @@ QDF_STATUS lim_sta_send_add_bss(tpAniSirGlobal pMac, tpSirAssocRsp pAssocRsp, vht_caps, psessionEntry); } - pe_debug("vhtCapable %d TxChannelWidth %d center_freq_0 %d center_freq_1 %d", - pAddBssParams->vhtCapable, pAddBssParams->ch_width, - pAddBssParams->ch_center_freq_seg0, - pAddBssParams->ch_center_freq_seg1); - if (lim_is_session_he_capable(psessionEntry) && (pAssocRsp->he_cap.present)) { lim_add_bss_he_cap(pAddBssParams, pAssocRsp); @@ -3835,11 +3742,6 @@ QDF_STATUS lim_sta_send_add_bss(tpAniSirGlobal pMac, tpSirAssocRsp pAssocRsp, (uint8_t) pAssocRsp->capabilityInfo.shortPreamble; pAddBssParams->staContext.updateSta = updateEntry; - pe_debug("StaContext: " MAC_ADDRESS_STR - " shortPreambleSupported: %d", - MAC_ADDR_ARRAY(pAddBssParams->staContext.staMac), - pAddBssParams->staContext.shortPreambleSupported); - if (IS_DOT11_MODE_HT(psessionEntry->dot11mode) && pBeaconStruct->HTCaps.present) { pAddBssParams->staContext.us32MaxAmpduDuration = 0; @@ -3848,10 +3750,6 @@ QDF_STATUS lim_sta_send_add_bss(tpAniSirGlobal pMac, tpSirAssocRsp pAssocRsp, (uint8_t) pAssocRsp->HTCaps.greenField; pAddBssParams->staContext.lsigTxopProtection = (uint8_t) pAssocRsp->HTCaps.lsigTXOPProtection; - pe_debug("StaCtx: htCap %d GFcap %d lsigTxopProtn %d", - pAddBssParams->staContext.htCapable, - pAddBssParams->staContext.greenFieldCapable, - pAddBssParams->staContext.lsigTxopProtection); if (psessionEntry->htConfig.ht_tx_stbc) pAddBssParams->staContext.stbc_capable = pAssocRsp->HTCaps.rxSTBC; @@ -3918,13 +3816,6 @@ QDF_STATUS lim_sta_send_add_bss(tpAniSirGlobal pMac, tpSirAssocRsp pAssocRsp, sta_context->vhtTxBFCapable = 0; } - pe_debug("StaCtx: vhtCap %d ChBW %d TxBF %d", - pAddBssParams->staContext.vhtCapable, - pAddBssParams->staContext.ch_width, - sta_context->vhtTxBFCapable); - pe_debug("StaContext su_tx_bfer %d", - sta_context->enable_su_tx_bformer); - pAddBssParams->staContext.mimoPS = (tSirMacHTMIMOPowerSaveState) pAssocRsp->HTCaps.mimoPowerSave; @@ -4000,21 +3891,6 @@ QDF_STATUS lim_sta_send_add_bss(tpAniSirGlobal pMac, tpSirAssocRsp pAssocRsp, pAddBssParams->staContext.rifsMode = pAssocRsp->HTInfo.rifsMode; - pe_debug("StaCtx: ChBW %d mimoPS %d maxAmsduSize %d", - pAddBssParams->staContext.ch_width, - pAddBssParams->staContext.mimoPS, - pAddBssParams->staContext.maxAmsduSize); - - pe_debug("maxAmpduDens %d CckMode40Mhz %d SGI20Mhz %d", - pAddBssParams->staContext.maxAmpduDensity, - pAddBssParams->staContext.fDsssCckMode40Mhz, - pAddBssParams->staContext.fShortGI20Mhz); - - pe_debug("SGI40M %d maxAmpdu %d htLdpc %d vhtLdpc %d", - pAddBssParams->staContext.fShortGI40Mhz, - pAddBssParams->staContext.maxAmpduSize, - pAddBssParams->staContext.htLdpcCapable, - pAddBssParams->staContext.vhtLdpcCapable); } pAddBssParams->staContext.smesessionId = psessionEntry->smeSessionId; @@ -4056,7 +3932,6 @@ QDF_STATUS lim_sta_send_add_bss(tpAniSirGlobal pMac, tpSirAssocRsp pAssocRsp, pAddBssParams->staContext.encryptType = psessionEntry->encryptType; pAddBssParams->maxTxPower = psessionEntry->maxTxPower; - pe_debug("maxTxPower: %d", pAddBssParams->maxTxPower); /* FIXME_GEN4 - Any other value that can be used for initialization? */ pAddBssParams->status = QDF_STATUS_SUCCESS; pAddBssParams->respReqd = true; @@ -4069,8 +3944,6 @@ QDF_STATUS lim_sta_send_add_bss(tpAniSirGlobal pMac, tpSirAssocRsp pAssocRsp, pAddBssParams->bSpectrumMgtEnabled = psessionEntry->spectrumMgtEnabled; pAddBssParams->extSetStaKeyParamValid = 0; - pe_debug("extSetStaKeyParamValid: %d", - pAddBssParams->extSetStaKeyParamValid); #ifdef WLAN_FEATURE_11W if (psessionEntry->limRmfEnabled) { @@ -4097,24 +3970,18 @@ QDF_STATUS lim_sta_send_add_bss(tpAniSirGlobal pMac, tpSirAssocRsp pAssocRsp, pAddBssParams->staContext.vht_caps &= ~(1 << SIR_MAC_VHT_CAP_LDPC_CODING_CAP); - pe_debug("staContext wmmEnabled: %d encryptType: %d " - "p2pCapableSta: %d", - pAddBssParams->staContext.wmmEnabled, - pAddBssParams->staContext.encryptType, - pAddBssParams->staContext.p2pCapableSta); - - pe_debug("bSpectrumMgtEnabled: %d halPersona: %d setting " - "LimMlm state to %d", - pAddBssParams->bSpectrumMgtEnabled, pAddBssParams->halPersona, - psessionEntry->limMlmState); if (psessionEntry->isNonRoamReassoc) pAddBssParams->nonRoamReassoc = 1; pAddBssParams->nss = psessionEntry->nss; - pe_debug("nss value: %d", pAddBssParams->nss); - - /* we need to defer the message until we get the response back from HAL. */ - SET_LIM_PROCESS_DEFD_MESGS(pMac, false); + pe_debug("update %d MxAmpduDen %d mimoPS %d shortSlot %d BI %d DTIM %d enc type %d p2p cab STA %d", + updateEntry, + pAddBssParams->staContext.maxAmpduDensity, + pAddBssParams->staContext.mimoPS, + pAddBssParams->shortSlotTimeSupported, + pAddBssParams->beaconInterval, pAddBssParams->dtimPeriod, + pAddBssParams->staContext.encryptType, + pAddBssParams->staContext.p2pCapableSta); if (cds_is_5_mhz_enabled()) { pAddBssParams->ch_width = CH_WIDTH_5MHZ; pAddBssParams->staContext.ch_width = CH_WIDTH_5MHZ; @@ -4124,14 +3991,17 @@ QDF_STATUS lim_sta_send_add_bss(tpAniSirGlobal pMac, tpSirAssocRsp pAssocRsp, } lim_set_sta_ctx_twt(&pAddBssParams->staContext, psessionEntry); + if (lim_is_fils_connection(psessionEntry)) + pAddBssParams->no_ptk_4_way = true; + + /* we need to defer the message until we get the response back */ + SET_LIM_PROCESS_DEFD_MESGS(pMac, false); + msgQ.type = WMA_ADD_BSS_REQ; /** @ToDo : Update the Global counter to keeptrack of the PE <--> HAL messages*/ msgQ.reserved = 0; msgQ.bodyptr = pAddBssParams; msgQ.bodyval = 0; - - pe_debug("SessionId: %d Sending WMA_ADD_BSS_REQ", - psessionEntry->peSessionId); MTRACE(mac_trace_msg_tx(pMac, psessionEntry->peSessionId, msgQ.type)); retCode = wma_post_ctrl_msg(pMac, &msgQ); @@ -4193,12 +4063,6 @@ QDF_STATUS lim_sta_send_add_bss_pre_assoc(tpAniSirGlobal pMac, uint8_t updateEnt /* Fill in tAddBssParams selfMacAddr */ qdf_mem_copy(pAddBssParams->selfMacAddr, psessionEntry->selfMacAddr, sizeof(tSirMacAddr)); - pe_debug("sessionid: %d updateEntry = %d limsystemrole = %d", - psessionEntry->smeSessionId, updateEntry, - GET_LIM_SYSTEM_ROLE(psessionEntry)); - - pe_debug("BSSID: " MAC_ADDRESS_STR, - MAC_ADDR_ARRAY(pAddBssParams->bssId)); /* Incorrect BSS Type which caused UMA Descriptor to be overwritten on * top of an already established Infra link. This lead to issues in * concurrent data transfer. @@ -4239,27 +4103,10 @@ QDF_STATUS lim_sta_send_add_bss_pre_assoc(tpAniSirGlobal pMac, uint8_t updateEnt pAddBssParams->ht20Coexist = (uint8_t) psessionEntry->beaconParams.ht20Coexist; - pe_debug("BSS Type %d Beacon Interval: %d dtimPeriod: %d " - "cfpCount: %d", pAddBssParams->bssType, - pAddBssParams->beaconInterval, pAddBssParams->dtimPeriod, - pAddBssParams->cfParamSet.cfpCount); - - pe_debug("cfpPeriod: %d cfpMaxDuration: %d cfpDurRemaining: %d" - " numRates: %d", pAddBssParams->cfParamSet.cfpPeriod, - pAddBssParams->cfParamSet.cfpMaxDuration, - pAddBssParams->cfParamSet.cfpDurRemaining, - pAddBssParams->rateSet.numRates); - - pe_debug("nwType:%d shortSlotTimeSupported: %d" - "llaCoexist: %d llbCoexist: %d llgCoexist: %d ht20Coexist: %d", - pAddBssParams->nwType, pAddBssParams->shortSlotTimeSupported, - pAddBssParams->llaCoexist, pAddBssParams->llbCoexist, - pAddBssParams->llgCoexist, pAddBssParams->ht20Coexist); /* Use the advertised capabilities from the received beacon/PR */ if (IS_DOT11_MODE_HT(psessionEntry->dot11mode) && (pBeaconStruct->HTCaps.present)) { pAddBssParams->htCapable = pBeaconStruct->HTCaps.present; - pe_debug("htCapable: %d", pAddBssParams->htCapable); if (pBeaconStruct->HTInfo.present) { pAddBssParams->htOperMode = (tSirMacHTOperatingMode) pBeaconStruct->HTInfo. @@ -4296,25 +4143,10 @@ QDF_STATUS lim_sta_send_add_bss_pre_assoc(tpAniSirGlobal pMac, uint8_t updateEnt lsigTXOPProtectionFullSupport; pAddBssParams->fRIFSMode = pBeaconStruct->HTInfo.rifsMode; - - pe_debug("htOperMode: %d dualCTSProtection: %d txChannelWidthSet: %d center_freq_seg0: %d", - pAddBssParams->htOperMode, - pAddBssParams->dualCTSProtection, - pAddBssParams->txChannelWidthSet, - pAddBssParams->ch_center_freq_seg0); - - pe_debug("llnNonGFCoexist: %d " - "fLsigTXOPProtectionFullSupport: %d fRIFSMode %d", - pAddBssParams->llnNonGFCoexist, - pAddBssParams->fLsigTXOPProtectionFullSupport, - pAddBssParams->fRIFSMode); } } pAddBssParams->currentOperChannel = bssDescription->channelId; - pe_debug("currentOperChannel %d", - pAddBssParams->currentOperChannel); - if (psessionEntry->vhtCapability && (IS_BSS_VHT_CAPABLE(pBeaconStruct->VHTCaps) || IS_BSS_VHT_CAPABLE(pBeaconStruct->vendor_vht_ie.VHTCaps))) { @@ -4356,10 +4188,6 @@ QDF_STATUS lim_sta_send_add_bss_pre_assoc(tpAniSirGlobal pMac, uint8_t updateEnt lim_update_bss_he_capable(pMac, pAddBssParams); lim_add_bss_he_cfg(pAddBssParams, psessionEntry); } - pe_debug("vhtCapable %d vhtTxChannelWidthSet %d center_freq_seg0 - %d, center_freq_seg1 - %d", - pAddBssParams->vhtCapable, pAddBssParams->ch_width, - pAddBssParams->ch_center_freq_seg0, - pAddBssParams->ch_center_freq_seg1); /* * Populate the STA-related parameters here * Note that the STA here refers to the AP @@ -4380,12 +4208,7 @@ QDF_STATUS lim_sta_send_add_bss_pre_assoc(tpAniSirGlobal pMac, uint8_t updateEnt (uint8_t) pBeaconStruct->capabilityInfo.shortPreamble; pAddBssParams->staContext.updateSta = updateEntry; - pe_debug("StaCtx: " MAC_ADDRESS_STR " shortPreamble: %d", - MAC_ADDR_ARRAY(pAddBssParams->staContext.staMac), - pAddBssParams->staContext.shortPreambleSupported); - pAddBssParams->dot11_mode = psessionEntry->dot11mode; - pe_debug("dot11_mode:%d", pAddBssParams->dot11_mode); if (IS_DOT11_MODE_HT(psessionEntry->dot11mode) && (pBeaconStruct->HTCaps.present)) { @@ -4395,10 +4218,6 @@ QDF_STATUS lim_sta_send_add_bss_pre_assoc(tpAniSirGlobal pMac, uint8_t updateEnt (uint8_t) pBeaconStruct->HTCaps.greenField; pAddBssParams->staContext.lsigTxopProtection = (uint8_t) pBeaconStruct->HTCaps.lsigTXOPProtection; - pe_debug("StaCtx: htCap %d GFCap %d lsigTxopProtn %d", - pAddBssParams->staContext.htCapable, - pAddBssParams->staContext.greenFieldCapable, - pAddBssParams->staContext.lsigTxopProtection); if (psessionEntry->vhtCapability && (IS_BSS_VHT_CAPABLE(pBeaconStruct->VHTCaps) || IS_BSS_VHT_CAPABLE( @@ -4424,9 +4243,6 @@ QDF_STATUS lim_sta_send_add_bss_pre_assoc(tpAniSirGlobal pMac, uint8_t updateEnt psessionEntry->vht_config.su_beam_former) pAddBssParams->staContext.enable_su_tx_bformer = 1; - - pe_debug("StaContext: su_tx_bfer %d", - pAddBssParams->staContext.enable_su_tx_bformer); } if (lim_is_session_he_capable(psessionEntry) && pBeaconStruct->he_cap.present) @@ -4443,10 +4259,6 @@ QDF_STATUS lim_sta_send_add_bss_pre_assoc(tpAniSirGlobal pMac, uint8_t updateEnt vht_oper->chanWidth) pAddBssParams->staContext.ch_width = vht_oper->chanWidth + 1; - pe_debug("StaCtx: vhtCap %d ch_bw %d TxBF %d", - pAddBssParams->staContext.vhtCapable, - pAddBssParams->staContext.ch_width, - pAddBssParams->staContext.vhtTxBFCapable); } else { pAddBssParams->staContext.ch_width = CH_WIDTH_20MHZ; @@ -4498,7 +4310,6 @@ QDF_STATUS lim_sta_send_add_bss_pre_assoc(tpAniSirGlobal pMac, uint8_t updateEnt else if (pBeaconStruct->vendor_vht_ie.VHTCaps.present) { vht_caps = &pBeaconStruct->vendor_vht_ie.VHTCaps; - pe_debug("VHT Caps are in vendor Specific IE"); } if (vht_caps != NULL && (psessionEntry->txLdpcIniFeatureEnabled & 0x2)) @@ -4511,21 +4322,6 @@ QDF_STATUS lim_sta_send_add_bss_pre_assoc(tpAniSirGlobal pMac, uint8_t updateEnt if (pBeaconStruct->HTInfo.present) pAddBssParams->staContext.rifsMode = pBeaconStruct->HTInfo.rifsMode; - pe_debug("StaContext ChannelWidth: %d mimoPS: %d maxAmsduSize: %d", - pAddBssParams->staContext.ch_width, - pAddBssParams->staContext.mimoPS, - pAddBssParams->staContext.maxAmsduSize); - - pe_debug("maxAmpduDensity %d Cck40Mhz %d SGI20Mhz %d", - pAddBssParams->staContext.maxAmpduDensity, - pAddBssParams->staContext.fDsssCckMode40Mhz, - pAddBssParams->staContext.fShortGI20Mhz); - - pe_debug("SGI40M %d maxAmpdu %d htLdpc %d vhtLdpc %d", - pAddBssParams->staContext.fShortGI40Mhz, - pAddBssParams->staContext.maxAmpduSize, - pAddBssParams->staContext.htLdpcCapable, - pAddBssParams->staContext.vhtLdpcCapable); } /* * If WMM IE or 802.11E IE is not present @@ -4552,7 +4348,6 @@ QDF_STATUS lim_sta_send_add_bss_pre_assoc(tpAniSirGlobal pMac, uint8_t updateEnt pAddBssParams->staContext.encryptType = psessionEntry->encryptType; pAddBssParams->maxTxPower = psessionEntry->maxTxPower; - pe_debug("maxTxPower: %d", pAddBssParams->maxTxPower); pAddBssParams->status = QDF_STATUS_SUCCESS; pAddBssParams->respReqd = true; @@ -4566,8 +4361,6 @@ QDF_STATUS lim_sta_send_add_bss_pre_assoc(tpAniSirGlobal pMac, uint8_t updateEnt pAddBssParams->bSpectrumMgtEnabled = psessionEntry->spectrumMgtEnabled; pAddBssParams->extSetStaKeyParamValid = 0; - pe_debug("extSetStaKeyParamValid: %d", - pAddBssParams->extSetStaKeyParamValid); #ifdef WLAN_FEATURE_11W if (psessionEntry->limRmfEnabled) { @@ -4577,7 +4370,6 @@ QDF_STATUS lim_sta_send_add_bss_pre_assoc(tpAniSirGlobal pMac, uint8_t updateEnt #endif pAddBssParams->nss = psessionEntry->nss; - pe_debug("nss value: %d", pAddBssParams->nss); /* Set a new state for MLME */ psessionEntry->limMlmState = eLIM_MLM_WT_ADD_BSS_RSP_PREASSOC_STATE; @@ -4586,17 +4378,6 @@ QDF_STATUS lim_sta_send_add_bss_pre_assoc(tpAniSirGlobal pMac, uint8_t updateEnt (pMac, TRACE_CODE_MLM_STATE, psessionEntry->peSessionId, psessionEntry->limMlmState)); - pe_debug("staContext wmmEnabled: %d encryptType: %d " - "p2pCapableSta: %d", - pAddBssParams->staContext.wmmEnabled, - pAddBssParams->staContext.encryptType, - pAddBssParams->staContext.p2pCapableSta); - - pe_debug("bSpectrumMgtEnabled: %d halPersona: %d setting " - "LimMlm state to %d", - pAddBssParams->bSpectrumMgtEnabled, pAddBssParams->halPersona, - psessionEntry->limMlmState); - /* we need to defer the message until we get the response back from HAL. */ SET_LIM_PROCESS_DEFD_MESGS(pMac, false); @@ -4608,6 +4389,9 @@ QDF_STATUS lim_sta_send_add_bss_pre_assoc(tpAniSirGlobal pMac, uint8_t updateEnt pAddBssParams->staContext.ch_width = CH_WIDTH_10MHZ; } + if (lim_is_fils_connection(psessionEntry)) + pAddBssParams->no_ptk_4_way = true; + msgQ.type = WMA_ADD_BSS_REQ; /** @ToDo : Update the Global counter to keeptrack of the PE <--> HAL messages*/ msgQ.reserved = 0; @@ -4924,3 +4708,33 @@ void lim_send_sme_tsm_ie_ind(tpAniSirGlobal pMac, tpPESession psessionEntry, return; } #endif /* FEATURE_WLAN_ESE */ + +void lim_extract_ies_from_deauth_disassoc(tpAniSirGlobal mac_ctx, + uint8_t vdev_id, + uint8_t *deauth_disassoc_frame, + uint16_t deauth_disassoc_frame_len) +{ + struct wlan_objmgr_vdev *vdev; + uint16_t reason_code, ie_offset; + struct wlan_ies ie; + + /* Get the offset of IEs */ + ie_offset = sizeof(struct wlan_frame_hdr) + sizeof(reason_code); + + if (!deauth_disassoc_frame || deauth_disassoc_frame_len <= ie_offset) + return; + + vdev = wlan_objmgr_get_vdev_by_id_from_psoc(mac_ctx->psoc, + vdev_id, + WLAN_LEGACY_MAC_ID); + if (!vdev) { + pe_err("Got NULL vdev obj, returning"); + return; + } + + ie.data = deauth_disassoc_frame + ie_offset; + ie.len = deauth_disassoc_frame_len - ie_offset; + + mlme_set_peer_disconnect_ies(vdev, &ie); + wlan_objmgr_vdev_release_ref(vdev, WLAN_LEGACY_MAC_ID); +} diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_assoc_utils.h b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_assoc_utils.h index 6b11583668dc..6be56cbf10b5 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_assoc_utils.h +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_assoc_utils.h @@ -221,4 +221,21 @@ QDF_STATUS lim_populate_vht_mcs_set(tpAniSirGlobal pMac, tpPESession psessionEntry, uint8_t nss); +/** + * lim_extract_ies_from_deauth_disassoc() - Extract IEs from deauth/disassoc + * + * @session: PE session entry + * @deauth_disassoc_frame: A pointer to the deauth/disconnect frame buffer + * received from WMA. + * @deauth_disassoc_frame_leni: Length of the deauth/disconnect frame. + * + * This function receives deauth/disassoc frame from header. It extracts + * the IEs(tagged params) from the frame and caches in vdev object. + * + * Return: None + */ +void lim_extract_ies_from_deauth_disassoc(tpAniSirGlobal mac_ctx, + uint8_t vdev_id, + uint8_t *deauth_disassoc_frame, + uint16_t deauth_disassoc_frame_len); #endif /* __LIM_ASSOC_UTILS_H */ diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_ft.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_ft.c index 3f6357d2d91b..343b8ff3acd1 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_ft.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_ft.c @@ -70,7 +70,7 @@ void lim_ft_cleanup_all_ft_sessions(tpAniSirGlobal pMac) void lim_ft_cleanup(tpAniSirGlobal pMac, tpPESession psessionEntry) { if (NULL == psessionEntry) { - pe_err("psessionEntry is NULL"); + pe_debug("psessionEntry is NULL"); return; } @@ -472,8 +472,9 @@ void lim_ft_prepare_add_bss_req(tpAniSirGlobal pMac, /** * lim_fill_dot11mode() - to fill 802.11 mode in FT session * @mac_ctx: pointer to mac ctx - * @pftSessionEntry: FT session + * @ft_session: FT session * @psessionEntry: PE session + * @bcn: AP beacon pointer * * This API fills FT session's dot11mode either from pe session or * from CFG depending on the condition. @@ -481,18 +482,49 @@ void lim_ft_prepare_add_bss_req(tpAniSirGlobal pMac, * Return: none */ static void lim_fill_dot11mode(tpAniSirGlobal mac_ctx, - tpPESession pftSessionEntry, tpPESession psessionEntry) + tpPESession ft_session, + tpPESession psessionEntry, + tSchBeaconStruct *bcn) { uint32_t self_dot11_mode; if (psessionEntry->ftPEContext.pFTPreAuthReq && !mac_ctx->roam.configParam.isRoamOffloadEnabled) { - pftSessionEntry->dot11mode = + ft_session->dot11mode = psessionEntry->ftPEContext.pFTPreAuthReq->dot11mode; - } else { - wlan_cfg_get_int(mac_ctx, WNI_CFG_DOT11_MODE, &self_dot11_mode); - pe_debug("selfDot11Mode: %d", self_dot11_mode); - pftSessionEntry->dot11mode = self_dot11_mode; + return; + } + + wlan_cfg_get_int(mac_ctx, WNI_CFG_DOT11_MODE, &self_dot11_mode); + pe_debug("selfDot11Mode: %d", self_dot11_mode); + + if (ft_session->limRFBand == BAND_2G) + ft_session->dot11mode = WNI_CFG_DOT11_MODE_11G; + else + ft_session->dot11mode = WNI_CFG_DOT11_MODE_11A; + + switch (self_dot11_mode) { + case WNI_CFG_DOT11_MODE_11AX: + case WNI_CFG_DOT11_MODE_11AX_ONLY: + if (bcn->he_cap.present) + ft_session->dot11mode = WNI_CFG_DOT11_MODE_11AX; + else if (bcn->VHTCaps.present) + ft_session->dot11mode = WNI_CFG_DOT11_MODE_11AC; + else if (bcn->HTCaps.present) + ft_session->dot11mode = WNI_CFG_DOT11_MODE_11N; + break; + case WNI_CFG_DOT11_MODE_11AC: + case WNI_CFG_DOT11_MODE_11AC_ONLY: + if (bcn->VHTCaps.present) + ft_session->dot11mode = WNI_CFG_DOT11_MODE_11AC; + else if (bcn->HTCaps.present) + ft_session->dot11mode = WNI_CFG_DOT11_MODE_11N; + break; + case WNI_CFG_DOT11_MODE_11N: + case WNI_CFG_DOT11_MODE_11N_ONLY: + if (bcn->HTCaps.present) + ft_session->dot11mode = WNI_CFG_DOT11_MODE_11N; + break; } } #elif defined(WLAN_FEATURE_HOST_ROAM) @@ -501,13 +533,16 @@ static void lim_fill_dot11mode(tpAniSirGlobal mac_ctx, * @mac_ctx: pointer to mac ctx * @pftSessionEntry: FT session * @psessionEntry: PE session + * @bcn: AP beacon pointer * * This API fills FT session's dot11mode either from pe session. * * Return: none */ static void lim_fill_dot11mode(tpAniSirGlobal mac_ctx, - tpPESession pftSessionEntry, tpPESession psessionEntry) + tpPESession pftSessionEntry, + tpPESession psessionEntry, + tSchBeaconStruct *bcn) { pftSessionEntry->dot11mode = psessionEntry->ftPEContext.pFTPreAuthReq->dot11mode; @@ -544,6 +579,7 @@ void lim_fill_ft_session(tpAniSirGlobal pMac, pftSessionEntry->limWsmEnabled = psessionEntry->limWsmEnabled; pftSessionEntry->lim11hEnable = psessionEntry->lim11hEnable; pftSessionEntry->isOSENConnection = psessionEntry->isOSENConnection; + pftSessionEntry->connected_akm = psessionEntry->connected_akm; /* Fields to be filled later */ pftSessionEntry->pLimJoinReq = NULL; @@ -569,7 +605,14 @@ void lim_fill_ft_session(tpAniSirGlobal pMac, pftSessionEntry->ssId.length = pBeaconStruct->ssId.length; qdf_mem_copy(pftSessionEntry->ssId.ssId, pBeaconStruct->ssId.ssId, pftSessionEntry->ssId.length); - lim_fill_dot11mode(pMac, pftSessionEntry, psessionEntry); + + /* Copy The channel Id to the session Table */ + pftSessionEntry->limReassocChannelId = pbssDescription->channelId; + pftSessionEntry->currentOperChannel = pbssDescription->channelId; + + pftSessionEntry->limRFBand = lim_get_rf_band( + pftSessionEntry->currentOperChannel); + lim_fill_dot11mode(pMac, pftSessionEntry, psessionEntry, pBeaconStruct); pe_debug("dot11mode: %d", pftSessionEntry->dot11mode); pftSessionEntry->vhtCapability = @@ -579,13 +622,6 @@ void lim_fill_ft_session(tpAniSirGlobal pMac, (IS_DOT11_MODE_HT(pftSessionEntry->dot11mode) && pBeaconStruct->HTCaps.present); - /* Copy The channel Id to the session Table */ - pftSessionEntry->limReassocChannelId = pbssDescription->channelId; - pftSessionEntry->currentOperChannel = pbssDescription->channelId; - - pftSessionEntry->limRFBand = lim_get_rf_band( - pftSessionEntry->currentOperChannel); - if (pftSessionEntry->limRFBand == BAND_2G) { cbEnabledMode = pMac->roam.configParam.channelBondingMode24GHz; } else { diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_ft_preauth.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_ft_preauth.c index 40368a4651bc..e9dc73cda18a 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_ft_preauth.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_ft_preauth.c @@ -441,8 +441,10 @@ void lim_handle_ft_pre_auth_rsp(tpAniSirGlobal pMac, QDF_STATUS status, pftSessionEntry = pe_create_session(pMac, pbssDescription->bssId, &sessionId, pMac->lim.maxStation, - psessionEntry->bssType); - if (pftSessionEntry == NULL) { + psessionEntry->bssType, + psessionEntry->smeSessionId, + psessionEntry->pePersona); + if (!pftSessionEntry) { pe_err("Session not created for pre-auth 11R AP"); status = QDF_STATUS_E_FAILURE; psessionEntry->ftPEContext.ftPreAuthStatus = status; diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_link_monitoring_algo.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_link_monitoring_algo.c index b0534fad6f68..e7aac4713a10 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_link_monitoring_algo.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_link_monitoring_algo.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -199,6 +199,7 @@ void lim_delete_sta_context(tpAniSirGlobal mac_ctx, tpDeleteStaContext msg = (tpDeleteStaContext) lim_msg->bodyptr; tpPESession session_entry; tpDphHashNode sta_ds; + enum eSirMacReasonCodes reason_code; if (NULL == msg) { pe_err("Invalid body pointer in message"); @@ -213,6 +214,8 @@ void lim_delete_sta_context(tpAniSirGlobal mac_ctx, switch (msg->reasonCode) { case HAL_DEL_STA_REASON_CODE_KEEP_ALIVE: + case HAL_DEL_STA_REASON_CODE_SA_QUERY_TIMEOUT: + case HAL_DEL_STA_REASON_CODE_XRETRY: if (LIM_IS_STA_ROLE(session_entry) && !msg->is_tdls) { if (!((session_entry->limMlmState == eLIM_MLM_LINK_ESTABLISHED_STATE) && @@ -239,9 +242,18 @@ void lim_delete_sta_context(tpAniSirGlobal mac_ctx, lim_send_deauth_mgmt_frame(mac_ctx, eSIR_MAC_DISASSOC_DUE_TO_INACTIVITY_REASON, msg->addr2, session_entry, false); + if (msg->reasonCode == + HAL_DEL_STA_REASON_CODE_SA_QUERY_TIMEOUT) + reason_code = eSIR_MAC_SA_QUERY_TIMEOUT; + else if (msg->reasonCode == + HAL_DEL_STA_REASON_CODE_XRETRY) + reason_code = eSIR_MAC_PEER_XRETRY_FAIL; + else + reason_code = eSIR_MAC_PEER_INACTIVITY; lim_tear_down_link_with_ap(mac_ctx, - session_entry->peSessionId, - eSIR_MAC_DISASSOC_DUE_TO_INACTIVITY_REASON); + session_entry->peSessionId, + reason_code, + eLIM_LINK_MONITORING_DEAUTH); /* only break for STA role (non TDLS) */ break; } @@ -266,10 +278,11 @@ void lim_delete_sta_context(tpAniSirGlobal mac_ctx, return; } lim_send_deauth_mgmt_frame(mac_ctx, - eSIR_MAC_DISASSOC_DUE_TO_INACTIVITY_REASON, + eSIR_MAC_BSS_TRANSITION_DISASSOC, session_entry->bssId, session_entry, false); lim_tear_down_link_with_ap(mac_ctx, session_entry->peSessionId, - eSIR_MAC_UNSPEC_FAILURE_REASON); + eSIR_MAC_BSS_TRANSITION_DISASSOC, + eLIM_LINK_MONITORING_DEAUTH); break; default: @@ -336,26 +349,10 @@ lim_trigger_sta_deletion(tpAniSirGlobal mac_ctx, tpDphHashNode sta_ds, lim_send_sme_disassoc_ind(mac_ctx, sta_ds, session_entry); } /*** end lim_trigger_st_adeletion() ***/ -/** - * lim_tear_down_link_with_ap() - * - ***FUNCTION: - * This function is called when heartbeat (beacon reception) - * fails on STA - * - ***LOGIC: - * - ***ASSUMPTIONS: - * - ***NOTE: - * - * @param pMac - Pointer to Global MAC structure - * @return None - */ - void lim_tear_down_link_with_ap(tpAniSirGlobal pMac, uint8_t sessionId, - tSirMacReasonCodes reasonCode) + tSirMacReasonCodes reasonCode, + enum eLimDisassocTrigger trigger) { tpDphHashNode pStaDs = NULL; @@ -374,7 +371,9 @@ lim_tear_down_link_with_ap(tpAniSirGlobal pMac, uint8_t sessionId, */ psessionEntry->pmmOffloadInfo.bcnmiss = false; - pe_info("No ProbeRsp from AP after HB failure. Tearing down link"); + pe_info("Session %d Vdev %d reason code %d trigger %d", + psessionEntry->peSessionId, psessionEntry->smeSessionId, + reasonCode, trigger); /* Announce loss of link to Roaming algorithm */ /* and cleanup by sending SME_DISASSOC_REQ to SME */ @@ -386,40 +385,47 @@ lim_tear_down_link_with_ap(tpAniSirGlobal pMac, uint8_t sessionId, if (pStaDs != NULL) { tLimMlmDeauthInd mlmDeauthInd; + if ((pStaDs->mlmStaContext.disassocReason == + eSIR_MAC_DEAUTH_LEAVING_BSS_REASON) || + (pStaDs->mlmStaContext.cleanupTrigger == + eLIM_HOST_DEAUTH)) { + pe_err("Host already issued deauth, do nothing"); + return; + } + #ifdef FEATURE_WLAN_TDLS /* Delete all TDLS peers connected before leaving BSS */ lim_delete_tdls_peers(pMac, psessionEntry); #endif pStaDs->mlmStaContext.disassocReason = reasonCode; - pStaDs->mlmStaContext.cleanupTrigger = - eLIM_LINK_MONITORING_DEAUTH; + pStaDs->mlmStaContext.cleanupTrigger = trigger; /* / Issue Deauth Indication to SME. */ qdf_mem_copy((uint8_t *) &mlmDeauthInd.peerMacAddr, pStaDs->staAddr, sizeof(tSirMacAddr)); - /* - * if send_deauth_before_con is enabled and reasoncode is - * Beacon Missed Store the MAC of AP in the flip flop - * buffer. This MAC will be used to send Deauth before - * connection, if we connect to same AP after HB failure. - */ - if (pMac->roam.configParam.send_deauth_before_con && - eSIR_BEACON_MISSED == reasonCode) { - int apCount = pMac->lim.gLimHeartBeatApMacIndex; - - if (pMac->lim.gLimHeartBeatApMacIndex) - pMac->lim.gLimHeartBeatApMacIndex = 0; - else - pMac->lim.gLimHeartBeatApMacIndex = 1; - - pe_debug("HB Failure on MAC " - MAC_ADDRESS_STR" Store it on Index %d", - MAC_ADDR_ARRAY(pStaDs->staAddr), apCount); - - sir_copy_mac_addr(pMac->lim.gLimHeartBeatApMac[apCount], - pStaDs->staAddr); - } + /* + * if send_deauth_before_con is enabled and reasoncode is + * Beacon Missed Store the MAC of AP in the flip flop + * buffer. This MAC will be used to send Deauth before + * connection, if we connect to same AP after HB failure. + */ + if (pMac->roam.configParam.send_deauth_before_con && + eSIR_MAC_BEACON_MISSED == reasonCode) { + int apCount = pMac->lim.gLimHeartBeatApMacIndex; + + if (pMac->lim.gLimHeartBeatApMacIndex) + pMac->lim.gLimHeartBeatApMacIndex = 0; + else + pMac->lim.gLimHeartBeatApMacIndex = 1; + + pe_debug("HB Failure on MAC " + MAC_ADDRESS_STR" Store it on Index %d", + MAC_ADDR_ARRAY(pStaDs->staAddr), apCount); + + sir_copy_mac_addr(pMac->lim.gLimHeartBeatApMac[apCount], + pStaDs->staAddr); + } mlmDeauthInd.reasonCode = (uint8_t) pStaDs->mlmStaContext.disassocReason; @@ -526,14 +532,14 @@ void lim_handle_heart_beat_failure(tpAniSirGlobal mac_ctx, session->dot11mode, NULL, NULL); } } else { - pe_debug("HB missed from AP on DFS channel"); /* * Connected on DFS channel so should not send the * probe request tear down the link directly */ lim_tear_down_link_with_ap(mac_ctx, session->peSessionId, - eSIR_BEACON_MISSED); + eSIR_MAC_BEACON_MISSED, + eLIM_LINK_MONITORING_DEAUTH); } } else { /** @@ -555,3 +561,4 @@ void lim_handle_heart_beat_failure(tpAniSirGlobal mac_ctx, WLAN_WAKE_ALL_NETIF_QUEUE, WLAN_CONTROL_PATH); } + diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_action_frame.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_action_frame.c index 6a7f880f0af2..80f3fc753ba1 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_action_frame.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_action_frame.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -85,16 +85,12 @@ void lim_stop_tx_and_switch_channel(tpAniSirGlobal pMac, uint8_t sessionId) return; } - pe_debug("Channel switch Mode: %d", - psessionEntry->gLimChannelSwitch.switchMode); - if (psessionEntry->gLimChannelSwitch.switchMode == eSIR_CHANSW_MODE_SILENT || psessionEntry->gLimChannelSwitch.switchCount <= SIR_CHANSW_TX_STOP_MAX_COUNT) { /* Freeze the transmission */ lim_frame_transmission_control(pMac, eLIM_TX_ALL, eLIM_STOP_TX); - } else { /* Resume the transmission */ lim_frame_transmission_control(pMac, eLIM_TX_ALL, eLIM_RESUME_TX); @@ -1343,8 +1339,8 @@ __lim_process_radio_measure_request(tpAniSirGlobal pMac, uint8_t *pRxPacketInfo, pBody, frameLen); goto err; } else if (DOT11F_WARNED(nStatus)) { - pe_debug("There were warnings while unpacking a Radio Measure request (0x%08x, %d bytes):", - nStatus, frameLen); + pe_debug("Warnings while unpacking a Radio Measure request (0x%08x, %d bytes):", + nStatus, frameLen); } /* Call rrm function to handle the request. */ @@ -1972,6 +1968,15 @@ void lim_process_action_frame(tpAniSirGlobal mac_ctx, case SIR_MAC_WNM_BSS_TM_QUERY: case SIR_MAC_WNM_BSS_TM_REQUEST: case SIR_MAC_WNM_BSS_TM_RESPONSE: + if (mac_ctx->roam.configParam.p2p_disable_roam && + session && LIM_IS_STA_ROLE(session) && + (policy_mgr_mode_specific_connection_count( + mac_ctx->psoc, PM_P2P_CLIENT_MODE, NULL) || + policy_mgr_mode_specific_connection_count( + mac_ctx->psoc, PM_P2P_GO_MODE, NULL))) { + pe_debug("p2p session active drop BTM frame"); + break; + } case SIR_MAC_WNM_NOTIF_REQUEST: case SIR_MAC_WNM_NOTIF_RESPONSE: rssi = WMA_GET_RX_RSSI_NORMALIZED(rx_pkt_info); diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_assoc_req_frame.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_assoc_req_frame.c index c99d507f8526..53e090b2c997 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_assoc_req_frame.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_assoc_req_frame.c @@ -275,7 +275,8 @@ static bool lim_chk_assoc_req_parse_error(tpAniSirGlobal mac_ctx, if (sub_type == LIM_ASSOC) status = sir_convert_assoc_req_frame2_struct(mac_ctx, frm_body, - frame_len, assoc_req); + frame_len, + assoc_req); else status = sir_convert_reassoc_req_frame2_struct(mac_ctx, frm_body, frame_len, assoc_req); @@ -855,8 +856,8 @@ static bool lim_check_wpa_rsn_ie(tpPESession session, tpAniSirGlobal mac_ctx, */ qdf_mem_zero((uint8_t *) &dot11f_ie_rsn, sizeof(dot11f_ie_rsn)); qdf_mem_zero((uint8_t *) &dot11f_ie_wpa, sizeof(dot11f_ie_wpa)); - pe_err("RSN enabled auth, Re/Assoc req from STA: " - MAC_ADDRESS_STR, MAC_ADDR_ARRAY(hdr->sa)); + pe_debug("RSN enabled auth, Re/Assoc req from STA: " + MAC_ADDRESS_STR, MAC_ADDR_ARRAY(hdr->sa)); if (assoc_req->rsnPresent) { if (!(assoc_req->rsn.length)) { @@ -1852,11 +1853,11 @@ void lim_process_assoc_req_frame(tpAniSirGlobal mac_ctx, uint8_t *rx_pkt_info, hdr = WMA_GET_RX_MAC_HEADER(rx_pkt_info); frame_len = WMA_GET_RX_PAYLOAD_LEN(rx_pkt_info); - pe_debug("Rcvd: %s Req Frame sessionid: %d systemrole: %d MlmState: %d from: " - MAC_ADDRESS_STR, - (LIM_ASSOC == sub_type) ? "Assoc" : "ReAssoc", - session->peSessionId, GET_LIM_SYSTEM_ROLE(session), - session->limMlmState, MAC_ADDR_ARRAY(hdr->sa)); + pe_nofl_debug("Assoc req RX: subtype %d vdev %d sys role %d lim state %d rssi %d from " QDF_MAC_ADDR_STR, + sub_type, session->smeSessionId, GET_LIM_SYSTEM_ROLE(session), + session->limMlmState, + WMA_GET_RX_RSSI_NORMALIZED(rx_pkt_info), + QDF_MAC_ADDR_ARRAY(hdr->sa)); if (LIM_IS_STA_ROLE(session)) { pe_err("Rcvd unexpected ASSOC REQ, sessionid: %d sys sub_type: %d for role: %d from: " diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_assoc_rsp_frame.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_assoc_rsp_frame.c index 2ef646a5e64c..b5ca95daa2fb 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_assoc_rsp_frame.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_assoc_rsp_frame.c @@ -316,7 +316,6 @@ static void lim_update_ric_data(tpAniSirGlobal mac_ctx, pe_err("RIC data not present"); } } else { - pe_debug("Ric is not present"); session_entry->RICDataLen = 0; session_entry->ricData = NULL; } @@ -364,7 +363,6 @@ static void lim_update_ese_tspec(tpAniSirGlobal mac_ctx, } else { session_entry->tspecLen = 0; session_entry->tspecIes = NULL; - pe_debug("Tspec EID *NOT* present in assoc rsp"); } return; } @@ -551,35 +549,14 @@ lim_process_assoc_rsp_frame(tpAniSirGlobal mac_ctx, struct csr_roam_session *roam_session; #endif tSirMacEdcaParamRecord mu_edca_set[MAX_NUM_AC]; + int8_t rssi; - /* Initialize status code to success. */ - if (lim_is_roam_synch_in_progress(session_entry)) - hdr = (tpSirMacMgmtHdr) mac_ctx->roam.pReassocResp; - else - hdr = WMA_GET_RX_MAC_HEADER(rx_pkt_info); #ifdef WLAN_FEATURE_ROAM_OFFLOAD sme_sessionid = session_entry->smeSessionId; #endif assoc_cnf.resultCode = eSIR_SME_SUCCESS; /* Update PE session Id */ assoc_cnf.sessionId = session_entry->peSessionId; - if (hdr == NULL) { - pe_err("LFR3: Reassoc response packet header is NULL"); - return; - } - - pe_debug("received Re/Assoc: %d resp on sessionid: %d systemrole: %d" - " and mlmstate: %d RSSI: %d from "MAC_ADDRESS_STR, subtype, - session_entry->peSessionId, GET_LIM_SYSTEM_ROLE(session_entry), - session_entry->limMlmState, - (uint) abs((int8_t) WMA_GET_RX_RSSI_NORMALIZED(rx_pkt_info)), - MAC_ADDR_ARRAY(hdr->sa)); - - beacon = qdf_mem_malloc(sizeof(tSchBeaconStruct)); - if (NULL == beacon) { - pe_err("Unable to allocate memory"); - return; - } if (LIM_IS_AP_ROLE(session_entry)) { /* @@ -588,16 +565,38 @@ lim_process_assoc_rsp_frame(tpAniSirGlobal mac_ctx, */ pe_err("Should not received Re/Assoc Response in role: %d", GET_LIM_SYSTEM_ROLE(session_entry)); - qdf_mem_free(beacon); return; } + if (lim_is_roam_synch_in_progress(session_entry)) { hdr = (tpSirMacMgmtHdr) mac_ctx->roam.pReassocResp; frame_len = mac_ctx->roam.reassocRespLen - SIR_MAC_HDR_LEN_3A; + rssi = 0; } else { hdr = WMA_GET_RX_MAC_HEADER(rx_pkt_info); frame_len = WMA_GET_RX_PAYLOAD_LEN(rx_pkt_info); + rssi = (uint)abs((int8_t)WMA_GET_RX_RSSI_NORMALIZED(rx_pkt_info)); + } + + if (!hdr) { + pe_err("LFR3: Reassoc response packet header is NULL"); + return; + } + + pe_nofl_info("Assoc rsp RX: subtype %d vdev %d sys role %d lim state %d rssi %d from " QDF_MAC_ADDR_STR, + subtype, session_entry->smeSessionId, + GET_LIM_SYSTEM_ROLE(session_entry), + session_entry->limMlmState, rssi, + QDF_MAC_ADDR_ARRAY(hdr->sa)); + QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_PE, QDF_TRACE_LEVEL_DEBUG, + (uint8_t *)hdr, frame_len + SIR_MAC_HDR_LEN_3A); + + beacon = qdf_mem_malloc(sizeof(tSchBeaconStruct)); + if (!beacon) { + pe_err("Unable to allocate memory"); + return; } + if (((subtype == LIM_ASSOC) && (session_entry->limMlmState != eLIM_MLM_WT_ASSOC_RSP_STATE)) || ((subtype == LIM_REASSOC) && @@ -707,7 +706,13 @@ lim_process_assoc_rsp_frame(tpAniSirGlobal mac_ctx, #ifdef WLAN_FEATURE_ROAM_OFFLOAD roam_session = &mac_ctx->roam.roamSession[sme_sessionid]; - if (assoc_rsp->FTInfo.R0KH_ID.present) { + if (assoc_rsp->sha384_ft_subelem.r0kh_id.present) { + roam_session->ftSmeContext.r0kh_id_len = + assoc_rsp->sha384_ft_subelem.r0kh_id.num_PMK_R0_ID; + qdf_mem_copy(roam_session->ftSmeContext.r0kh_id, + assoc_rsp->sha384_ft_subelem.r0kh_id.PMK_R0_ID, + roam_session->ftSmeContext.r0kh_id_len); + } else if (assoc_rsp->FTInfo.R0KH_ID.present) { roam_session->ftSmeContext.r0kh_id_len = assoc_rsp->FTInfo.R0KH_ID.num_PMK_R0_ID; qdf_mem_copy(roam_session->ftSmeContext.r0kh_id, @@ -716,7 +721,7 @@ lim_process_assoc_rsp_frame(tpAniSirGlobal mac_ctx, } else { roam_session->ftSmeContext.r0kh_id_len = 0; qdf_mem_zero(roam_session->ftSmeContext.r0kh_id, - SIR_ROAM_R0KH_ID_MAX_LEN); + SIR_ROAM_R0KH_ID_MAX_LEN); } #endif @@ -1072,6 +1077,8 @@ lim_process_assoc_rsp_frame(tpAniSirGlobal mac_ctx, } qdf_mem_free(beacon); + qdf_mem_free(assoc_rsp->sha384_ft_subelem.gtk); + qdf_mem_free(assoc_rsp->sha384_ft_subelem.igtk); qdf_mem_free(assoc_rsp); return; } diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_auth_frame.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_auth_frame.c index 51ec06b159e7..96042168aca2 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_auth_frame.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_auth_frame.c @@ -296,8 +296,8 @@ static void lim_process_sae_auth_frame(tpAniSirGlobal mac_ctx, body_ptr = WMA_GET_RX_MPDU_DATA(rx_pkt_info); frame_len = WMA_GET_RX_PAYLOAD_LEN(rx_pkt_info); - pe_debug("Received SAE Auth frame type %d subtype %d", - mac_hdr->fc.type, mac_hdr->fc.subType); + pe_nofl_info("Received SAE Auth frame type %d subtype %d", + mac_hdr->fc.type, mac_hdr->fc.subType); if (pe_session->limMlmState != eLIM_MLM_WT_SAE_AUTH_STATE) pe_err("received SAE auth response in unexpected state %x", @@ -698,8 +698,7 @@ static void lim_process_auth_frame_type2(tpAniSirGlobal mac_ctx, return; } - pe_debug("Alloc new data: %pK peer", auth_node); - lim_print_mac_addr(mac_ctx, mac_hdr->sa, LOGD); + pe_debug("add new auth node: for %pM", mac_hdr->sa); qdf_mem_copy((uint8_t *) auth_node->peerMacAddr, mac_ctx->lim.gpLimMlmAuthReq->peerMacAddr, sizeof(tSirMacAddr)); @@ -1150,11 +1149,6 @@ lim_process_auth_frame(tpAniSirGlobal mac_ctx, uint8_t *rx_pkt_info, curr_seq_num = (mac_hdr->seqControl.seqNumHi << 4) | (mac_hdr->seqControl.seqNumLo); - pe_debug("Sessionid: %d System role: %d limMlmState: %d: Auth response Received BSSID: "MAC_ADDRESS_STR" RSSI: %d", - pe_session->peSessionId, GET_LIM_SYSTEM_ROLE(pe_session), - pe_session->limMlmState, MAC_ADDR_ARRAY(mac_hdr->bssId), - (uint) abs((int8_t) WMA_GET_RX_RSSI_NORMALIZED(rx_pkt_info))); - if (pe_session->prev_auth_seq_num == curr_seq_num && mac_hdr->fc.retry) { pe_debug("auth frame, seq num: %d is already processed, drop it", @@ -1172,7 +1166,13 @@ lim_process_auth_frame(tpAniSirGlobal mac_ctx, uint8_t *rx_pkt_info, return; } auth_alg = *(uint16_t *) body_ptr; - pe_debug("auth_alg %d ", auth_alg); + + pe_nofl_info("Auth RX: vdev %d sys role %d lim_state %d from " QDF_MAC_ADDR_STR " rssi %d auth_alg %d seq %d", + pe_session->smeSessionId, GET_LIM_SYSTEM_ROLE(pe_session), + pe_session->limMlmState, + QDF_MAC_ADDR_ARRAY(mac_hdr->bssId), + WMA_GET_RX_RSSI_NORMALIZED(rx_pkt_info), + auth_alg, curr_seq_num); /* Restore default failure timeout */ if (QDF_P2P_CLIENT_MODE == pe_session->pePersona && @@ -1422,12 +1422,6 @@ lim_process_auth_frame(tpAniSirGlobal mac_ctx, uint8_t *rx_pkt_info, rx_auth_frm_body = rx_auth_frame; - pe_debug("Received Auth frame with type: %d seqnum: %d status: %d %d", - (uint32_t) rx_auth_frm_body->authAlgoNumber, - (uint32_t) rx_auth_frm_body->authTransactionSeqNumber, - (uint32_t) rx_auth_frm_body->authStatusCode, - (uint32_t) mac_ctx->lim.gLimNumPreAuthContexts); - if (!lim_is_valid_fils_auth_frame(mac_ctx, pe_session, rx_auth_frm_body)) { pe_err("Received invalid FILS auth packet"); @@ -1490,15 +1484,56 @@ lim_process_auth_frame(tpAniSirGlobal mac_ctx, uint8_t *rx_pkt_info, qdf_mem_free(plainbody); } +/** + * lim_process_sae_preauth_frame() - Send the WPA3 preauth SAE frame received + * to the user space. + * @mac: Global mac context + * @rx_pkt: Received auth packet + * + * SAE auth frame will be received with no session if its SAE preauth during + * roaming offloaded to the host. Forward this frame to the wpa supplicant. + * + * Return: True if auth algo is SAE else false + */ +static +bool lim_process_sae_preauth_frame(tpAniSirGlobal mac, uint8_t *rx_pkt) +{ + tpSirMacMgmtHdr dot11_hdr; + uint16_t auth_alg, frm_len; + uint8_t *frm_body; + + dot11_hdr = WMA_GET_RX_MAC_HEADER(rx_pkt); + frm_body = WMA_GET_RX_MPDU_DATA(rx_pkt); + frm_len = WMA_GET_RX_PAYLOAD_LEN(rx_pkt); + + if (frm_len < 2) { + pe_debug("LFR3: Invalid auth frame len:%d", frm_len); + return false; + } + + auth_alg = *(uint16_t *)frm_body; + if (auth_alg != eSIR_AUTH_TYPE_SAE) + return false; + + pe_debug("LFR3: SAE auth frame: seq_ctrl:0x%X auth_transaction_num:%d", + ((dot11_hdr->seqControl.seqNumHi << 8) | + (dot11_hdr->seqControl.seqNumLo << 4) | + (dot11_hdr->seqControl.fragNum)), *(uint16_t *)(frm_body + 2)); + + lim_send_sme_mgmt_frame_ind(mac, dot11_hdr->fc.subType, + (uint8_t *)dot11_hdr, + frm_len + sizeof(tSirMacMgmtHdr), 0, + WMA_GET_RX_CH(rx_pkt), NULL, + WMA_GET_RX_RSSI_NORMALIZED(rx_pkt)); + return true; +} + /*---------------------------------------------------------------------- * * Pass the received Auth frame. This is possibly the pre-auth from the * neighbor AP, in the same mobility domain. * This will be used in case of 11r FT. * - * !!!! This is going to be renoved for the next checkin. We will be creating - * the session before sending out the Auth. Thus when auth response - * is received we will have a session in progress. !!!!! ***---------------------------------------------------------------------- */ QDF_STATUS lim_process_auth_frame_no_session(tpAniSirGlobal pMac, uint8_t *pBd, @@ -1512,6 +1547,7 @@ QDF_STATUS lim_process_auth_frame_no_session(tpAniSirGlobal pMac, uint8_t *pBd, tSirMacAuthFrameBody *pRxAuthFrameBody = NULL; QDF_STATUS ret_status = QDF_STATUS_E_FAILURE; int i; + bool sae_auth_frame; pHdr = WMA_GET_RX_MAC_HEADER(pBd); pBody = WMA_GET_RX_MPDU_DATA(pBd); @@ -1521,6 +1557,15 @@ QDF_STATUS lim_process_auth_frame_no_session(tpAniSirGlobal pMac, uint8_t *pBd, MAC_ADDR_ARRAY(pHdr->bssId), (uint) abs((int8_t) WMA_GET_RX_RSSI_NORMALIZED(pBd))); + if (frameLen == 0) { + pe_err("Frame len = 0"); + return QDF_STATUS_E_FAILURE; + } + + sae_auth_frame = lim_process_sae_preauth_frame(pMac, pBd); + if (sae_auth_frame) + return QDF_STATUS_SUCCESS; + /* Auth frame has come on a new BSS, however, we need to find the session * from where the auth-req was sent to the new AP */ @@ -1547,10 +1592,6 @@ QDF_STATUS lim_process_auth_frame_no_session(tpAniSirGlobal pMac, uint8_t *pBd, return QDF_STATUS_E_FAILURE; } - if (frameLen == 0) { - pe_err("Error: Frame len = 0"); - return QDF_STATUS_E_FAILURE; - } lim_print_mac_addr(pMac, pHdr->bssId, LOGD); lim_print_mac_addr(pMac, psessionEntry->ftPEContext.pFTPreAuthReq->preAuthbssId, diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_beacon_frame.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_beacon_frame.c index c1d61e5146f4..1897c527c223 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_beacon_frame.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_beacon_frame.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -68,9 +68,12 @@ lim_process_beacon_frame(tpAniSirGlobal mac_ctx, uint8_t *rx_pkt_info, * beacon counter */ mac_hdr = WMA_GET_RX_MAC_HEADER(rx_pkt_info); - pe_debug("Received Beacon frame with length: %d from", - WMA_GET_RX_MPDU_LEN(rx_pkt_info)); - lim_print_mac_addr(mac_ctx, mac_hdr->sa, LOG2); + + pe_debug("Beacon (len %d): " QDF_MAC_ADDR_STR " RSSI %d", + WMA_GET_RX_MPDU_LEN(rx_pkt_info), + QDF_MAC_ADDR_ARRAY(mac_hdr->sa), + (uint)abs((int8_t) + WMA_GET_RX_RSSI_NORMALIZED(rx_pkt_info))); /* Expect Beacon in any state as Scan is independent of LIM state */ bcn_ptr = qdf_mem_malloc(sizeof(*bcn_ptr)); diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_cfg_updates.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_cfg_updates.c index c72369ba8796..7087d3ca74ee 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_cfg_updates.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_cfg_updates.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -179,8 +179,6 @@ void lim_handle_cf_gparam_update(tpAniSirGlobal pMac, uint32_t cfgId) uint16_t val16; tSirMacHTParametersInfo *pAmpduParamInfo; - pe_debug("Handling CFG parameter id %X update", cfgId); - switch (cfgId) { case WNI_CFG_ASSOCIATION_FAILURE_TIMEOUT: if (pMac->lim.gLimMlmState != eLIM_MLM_WT_ASSOC_RSP_STATE) { @@ -283,8 +281,6 @@ void lim_apply_configuration(tpAniSirGlobal pMac, tpPESession psessionEntry) { uint32_t val = 0, phyMode; - pe_debug("Applying config"); - psessionEntry->limSentCapsChangeNtf = false; lim_get_phy_mode(pMac, &phyMode, psessionEntry); @@ -303,7 +299,6 @@ void lim_apply_configuration(tpAniSirGlobal pMac, tpPESession psessionEntry) as a part of join request for a BT-AMP station */ if (psessionEntry->statypeForBss == STA_ENTRY_SELF) { - pe_debug("Initializing BT-AMP beacon generation"); sch_set_beacon_interval(pMac, psessionEntry); sch_set_fixed_beacon_fields(pMac, psessionEntry); } diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_deauth_frame.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_deauth_frame.c index 6be886272273..0ed23d8e16d0 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_deauth_frame.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_deauth_frame.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -146,25 +146,11 @@ lim_process_deauth_frame(tpAniSirGlobal pMac, uint8_t *pRxPacketInfo, /* Get reasonCode from Deauthentication frame body */ reasonCode = sir_read_u16(pBody); - pe_debug("Received Deauth frame for Addr: " MAC_ADDRESS_STR - "(mlm state = %s, sme state = %d systemrole = %d " - "RSSI = %d) with reason code %d [%s] from " - MAC_ADDRESS_STR, MAC_ADDR_ARRAY(pHdr->da), - lim_mlm_state_str(psessionEntry->limMlmState), - psessionEntry->limSmeState, - GET_LIM_SYSTEM_ROLE(psessionEntry), frame_rssi, - reasonCode, lim_dot11_reason_str(reasonCode), - MAC_ADDR_ARRAY(pHdr->sa)); - - if (pMac->roam.configParam.enable_fatal_event && - (reasonCode != eSIR_MAC_UNSPEC_FAILURE_REASON && - reasonCode != eSIR_MAC_DEAUTH_LEAVING_BSS_REASON && - reasonCode != eSIR_MAC_DISASSOC_LEAVING_BSS_REASON)) { - cds_flush_logs(WLAN_LOG_TYPE_FATAL, - WLAN_LOG_INDICATOR_HOST_DRIVER, - WLAN_LOG_REASON_DISCONNECT, - false, false); - } + pe_nofl_info("Deauth RX: vdev %d from %pM for %pM RSSI = %d reason %d mlm state = %d, sme state = %d systemrole = %d ", + psessionEntry->smeSessionId, pHdr->sa, pHdr->da, frame_rssi, + reasonCode, psessionEntry->limMlmState, + psessionEntry->limSmeState, + GET_LIM_SYSTEM_ROLE(psessionEntry)); lim_diag_event_report(pMac, WLAN_PE_DIAG_DEAUTH_FRAME_EVENT, psessionEntry, 0, reasonCode); @@ -313,9 +299,21 @@ lim_process_deauth_frame(tpAniSirGlobal pMac, uint8_t *pRxPacketInfo, } } + lim_extract_ies_from_deauth_disassoc(pMac, roamSessionId, + (uint8_t *)pHdr, + WMA_GET_RX_MPDU_LEN(pRxPacketInfo)); lim_perform_deauth(pMac, psessionEntry, reasonCode, pHdr->sa, frame_rssi); + if (pMac->roam.configParam.enable_fatal_event && + (reasonCode != eSIR_MAC_UNSPEC_FAILURE_REASON && + reasonCode != eSIR_MAC_DEAUTH_LEAVING_BSS_REASON && + reasonCode != eSIR_MAC_DISASSOC_LEAVING_BSS_REASON)) { + cds_flush_logs(WLAN_LOG_TYPE_FATAL, + WLAN_LOG_INDICATOR_HOST_DRIVER, + WLAN_LOG_REASON_DISCONNECT, + false, false); + } } /*** end lim_process_deauth_frame() ***/ diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_disassoc_frame.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_disassoc_frame.c index 99ca91f7ac7b..750dfd3d4ed9 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_disassoc_frame.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_disassoc_frame.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -145,25 +145,14 @@ lim_process_disassoc_frame(tpAniSirGlobal pMac, uint8_t *pRxPacketInfo, /* Get reasonCode from Disassociation frame body */ reasonCode = sir_read_u16(pBody); - pe_debug("Received Disassoc frame for Addr: " MAC_ADDRESS_STR - "(mlm state=%s, sme state=%d RSSI=%d)," - "with reason code %d [%s] from " MAC_ADDRESS_STR, - MAC_ADDR_ARRAY(pHdr->da), - lim_mlm_state_str(psessionEntry->limMlmState), - psessionEntry->limSmeState, frame_rssi, reasonCode, - lim_dot11_reason_str(reasonCode), MAC_ADDR_ARRAY(pHdr->sa)); + pe_nofl_info("Disassoc RX: vdev %d from %pM for %pM RSSI = %d reason %d mlm state = %d, sme state = %d systemrole = %d ", + psessionEntry->smeSessionId, pHdr->sa, pHdr->da, frame_rssi, + reasonCode, psessionEntry->limMlmState, + psessionEntry->limSmeState, + GET_LIM_SYSTEM_ROLE(psessionEntry)); lim_diag_event_report(pMac, WLAN_PE_DIAG_DISASSOC_FRAME_EVENT, psessionEntry, 0, reasonCode); - if (pMac->roam.configParam.enable_fatal_event && - (reasonCode != eSIR_MAC_UNSPEC_FAILURE_REASON && - reasonCode != eSIR_MAC_DEAUTH_LEAVING_BSS_REASON && - reasonCode != eSIR_MAC_DISASSOC_LEAVING_BSS_REASON)) { - cds_flush_logs(WLAN_LOG_TYPE_FATAL, - WLAN_LOG_INDICATOR_HOST_DRIVER, - WLAN_LOG_REASON_DISCONNECT, - false, false); - } /** * Extract 'associated' context for STA, if any. * This is maintained by DPH and created by LIM. @@ -309,9 +298,21 @@ lim_process_disassoc_frame(tpAniSirGlobal pMac, uint8_t *pRxPacketInfo, } /* if (pStaDs->mlmStaContext.mlmState != eLIM_MLM_LINK_ESTABLISHED_STATE) */ + lim_extract_ies_from_deauth_disassoc(pMac, psessionEntry->peSessionId, + (uint8_t *)pHdr, + WMA_GET_RX_MPDU_LEN(pRxPacketInfo)); lim_perform_disassoc(pMac, frame_rssi, reasonCode, psessionEntry, pHdr->sa); + if (pMac->roam.configParam.enable_fatal_event && + (reasonCode != eSIR_MAC_UNSPEC_FAILURE_REASON && + reasonCode != eSIR_MAC_DEAUTH_LEAVING_BSS_REASON && + reasonCode != eSIR_MAC_DISASSOC_LEAVING_BSS_REASON)) { + cds_flush_logs(WLAN_LOG_TYPE_FATAL, + WLAN_LOG_INDICATOR_HOST_DRIVER, + WLAN_LOG_REASON_DISCONNECT, + false, false); + } } /*** end lim_process_disassoc_frame() ***/ #ifdef FEATURE_WLAN_TDLS diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_fils.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_fils.c index d6903626cc2c..59fde6851252 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_fils.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_fils.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2017-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -42,7 +42,7 @@ static void lim_fils_data_dump(char *type, uint8_t *data, uint32_t len) QDF_TRACE(QDF_MODULE_ID_PE, QDF_TRACE_LEVEL_DEBUG, ("%s : length %d"), type, len); - qdf_trace_hex_dump(QDF_MODULE_ID_PE, QDF_TRACE_LEVEL_INFO, data, len); + qdf_trace_hex_dump(QDF_MODULE_ID_PE, QDF_TRACE_LEVEL_DEBUG, data, len); } #else static void lim_fils_data_dump(char *type, uint8_t *data, uint32_t len) @@ -92,7 +92,32 @@ static uint8_t lim_get_auth_tag_len(enum fils_erp_cryptosuite crypto_suite) * * Return: Crypto type */ -static uint8_t *lim_get_crypto_type(uint8_t akm) +static uint8_t *lim_get_hash_crypto_type(uint8_t akm) +{ + switch (akm) { + case eCSR_AUTH_TYPE_FILS_SHA384: + case eCSR_AUTH_TYPE_FT_FILS_SHA384: + return SHA386_CRYPTO_TYPE; + case eCSR_AUTH_TYPE_FILS_SHA256: + case eCSR_AUTH_TYPE_FT_FILS_SHA256: + default: + return SHA256_CRYPTO_TYPE; + } +} + +/** + * lim_get_hmac_crypto_type()- This API returns crypto type based on akm suite + * used. + * @akm: akm used for authentication + * + * This API is used to get the crypto type when HMAC-hash() needs to + * be generated. + * Eg: PMK = HMAC-Hash(SNonce || ANonce, rMSK [ || DHss ]) + * Here HMAC-Hash will be either hmac(sha256) or hmac(sha384) + * + * Return: Crypto type + */ +static uint8_t *lim_get_hmac_crypto_type(uint8_t akm) { switch (akm) { case eCSR_AUTH_TYPE_FILS_SHA384: @@ -105,6 +130,32 @@ static uint8_t *lim_get_crypto_type(uint8_t akm) } } +/** + * lim_get_Q_length()- This API returns pmk length based on akm used + * @akm: akm used for authentication + * + * [IEEE 802.11ai - 12.7.1.7.3 PMK-R0] + * PMK-R0 = L(R0-Key-Data, 0, Q) + * where Q is 32 if AKM negotiated is 00-0F-AC:16 + * Q is 48 if AKM negotiated is 00-0F-AC:17 + * + * PMK-R0 Derivation is for FT protocol akm only. + * So Value of Q is not applicable for non-FT akm. + * + * Return: Q length + */ +static uint8_t lim_get_Q_length(int akm_type) +{ + switch (akm_type) { + case eCSR_AUTH_TYPE_FT_FILS_SHA256: + return FILS_SHA256_Q_LEN; + case eCSR_AUTH_TYPE_FT_FILS_SHA384: + return FILS_SHA384_Q_LEN; + default: + return 0; + } +} + /** * lim_get_pmk_length()- This API returns pmk length based on akm used * @akm: akm used for authentication @@ -116,12 +167,32 @@ static uint8_t lim_get_pmk_length(int akm_type) switch (akm_type) { case eCSR_AUTH_TYPE_FILS_SHA256: case eCSR_AUTH_TYPE_FT_FILS_SHA256: - return FILS_SHA256_PKM_LEN; + return FILS_SHA256_PMK_LEN; case eCSR_AUTH_TYPE_FILS_SHA384: case eCSR_AUTH_TYPE_FT_FILS_SHA384: - return FILS_SHA384_PKM_LEN; + return FILS_SHA384_PMK_LEN; default: - return FILS_SHA256_PKM_LEN; + return FILS_SHA256_PMK_LEN; + } +} + +/** + * lim_get_fils_ft_length()- This API returns fils_ft length based on akm used + * @akm: akm used for authentication + * + * FILS_FT is the xx key used in derivation of the PMKR0. + * + * Return: PMK length + */ +static uint8_t lim_get_fils_ft_length(int akm_type) +{ + switch (akm_type) { + case eCSR_AUTH_TYPE_FT_FILS_SHA256: + return FILS_FT_SHA256_LEN; + case eCSR_AUTH_TYPE_FT_FILS_SHA384: + return FILS_FT_SHA384_LEN; + default: + return 0; } } @@ -415,21 +486,23 @@ static uint32_t lim_process_fils_eap_tlv(tpPESession pe_session, * * Return: QDF_STATUS */ -static QDF_STATUS lim_generate_key_data(struct pe_fils_session *fils_info, - uint8_t *key_label, uint8_t *data, uint32_t data_len, - uint8_t *key_data, uint32_t key_data_len) +static QDF_STATUS +lim_generate_key_data(struct pe_fils_session *fils_info, + uint8_t *key_label, uint8_t *data, uint32_t data_len, + uint8_t *key_data, uint32_t key_data_len) { QDF_STATUS status; if (!fils_info) return QDF_STATUS_E_FAILURE; - status = lim_get_key_from_prf(lim_get_crypto_type(fils_info->akm), - fils_info->fils_pmk, - fils_info->fils_pmk_len, - key_label, data, data_len, key_data, key_data_len); + status = lim_get_key_from_prf(lim_get_hmac_crypto_type(fils_info->akm), + fils_info->fils_pmk, + fils_info->fils_pmk_len, key_label, data, + data_len, key_data, key_data_len); if (status != QDF_STATUS_SUCCESS) pe_err("failed to generate keydata"); + return status; } @@ -465,12 +538,12 @@ static void lim_generate_ap_key_auth(tpPESession pe_session) qdf_mem_copy(buf, pe_session->selfMacAddr, QDF_MAC_ADDR_SIZE); buf += QDF_MAC_ADDR_SIZE; - if (qdf_get_hmac_hash(lim_get_crypto_type(fils_info->akm), - fils_info->ick, fils_info->ick_len, 1, &addr[0], - &len, fils_info->ap_key_auth_data) < 0) + if (qdf_get_hmac_hash(lim_get_hmac_crypto_type(fils_info->akm), + fils_info->ick, fils_info->ick_len, 1, &addr[0], + &len, fils_info->ap_key_auth_data) < 0) pe_err("failed to generate PMK id"); fils_info->ap_key_auth_len = lim_get_crypto_digest_len( - lim_get_crypto_type(fils_info->akm)); + lim_get_hmac_crypto_type(fils_info->akm)); lim_fils_data_dump("AP Key Auth", fils_info->ap_key_auth_data, fils_info->ap_key_auth_len); } @@ -508,12 +581,12 @@ static void lim_generate_key_auth(tpPESession pe_session) qdf_mem_copy(buf, pe_session->bssId, QDF_MAC_ADDR_SIZE); buf += QDF_MAC_ADDR_SIZE; - if (qdf_get_hmac_hash(lim_get_crypto_type(fils_info->akm), - fils_info->ick, fils_info->ick_len, 1, - &addr[0], &len, fils_info->key_auth) < 0) + if (qdf_get_hmac_hash(lim_get_hmac_crypto_type(fils_info->akm), + fils_info->ick, fils_info->ick_len, 1, + &addr[0], &len, fils_info->key_auth) < 0) pe_err("failed to generate key auth"); fils_info->key_auth_len = lim_get_crypto_digest_len( - lim_get_crypto_type(fils_info->akm)); + lim_get_hmac_crypto_type(fils_info->akm)); lim_fils_data_dump("STA Key Auth", fils_info->key_auth, fils_info->key_auth_len); } @@ -535,10 +608,11 @@ static void lim_get_keys(tpPESession pe_session) uint8_t *data; uint8_t data_len; struct pe_fils_session *fils_info = pe_session->fils_info; - uint8_t key_data[MAX_ICK_LEN + MAX_KEK_LEN + MAX_TK_LEN] = {0}; + uint8_t key_data[FILS_MAX_KEY_DATA_LEN] = {0}; uint8_t key_data_len; uint8_t ick_len; uint8_t kek_len; + uint8_t fils_ft_len = 0; uint8_t tk_len = lim_get_tk_len(pe_session->encryptType); uint8_t *buf; @@ -548,7 +622,22 @@ static void lim_get_keys(tpPESession pe_session) ick_len = lim_get_ick_len(fils_info->akm); kek_len = lim_get_kek_len(fils_info->akm); - key_data_len = ick_len + kek_len + tk_len; + if (pe_session->is11Rconnection) + fils_ft_len = lim_get_fils_ft_length(fils_info->akm); + + /* + * [IEEE 802.11ai - 12.12.2.5.3] + * FILS-Key-Data = PRF-X(PMK, “FILS PTK Derivation”, SPA || AA || + * SNonce || ANonce) + * ICK = L(FILS-Key-Data, 0, ICK_bits) + * KEK = L(FILS-Key-Data, ICK_bits, KEK_bits) + * TK = L(FILS-Key-Data, ICK_bits + KEK_bits, TK_bits) + * When doing FT initial mobility domain association using + * FILS authentication, + * FILS-FT = L(FILS-Key-Data, ICK_bits + KEK_bits + + * TK_bits, FILS-FT_bits) + */ + key_data_len = ick_len + kek_len + tk_len + fils_ft_len; data_len = 2 * SIR_FILS_NONCE_LENGTH + 2 * QDF_MAC_ADDR_SIZE; data = qdf_mem_malloc(data_len); @@ -557,27 +646,47 @@ static void lim_get_keys(tpPESession pe_session) return; } - /* Update data */ + /* data is SPA || AA ||SNonce || ANonce */ buf = data; qdf_mem_copy(buf, pe_session->selfMacAddr, QDF_MAC_ADDR_SIZE); buf += QDF_MAC_ADDR_SIZE; + qdf_mem_copy(buf, pe_session->bssId, QDF_MAC_ADDR_SIZE); buf += QDF_MAC_ADDR_SIZE; + qdf_mem_copy(buf, fils_info->fils_nonce, SIR_FILS_NONCE_LENGTH); buf += SIR_FILS_NONCE_LENGTH; + qdf_mem_copy(buf, fils_info->auth_info.fils_nonce, SIR_FILS_NONCE_LENGTH); + + /* Derive FILS-Key-Data */ lim_generate_key_data(fils_info, key_label, data, data_len, key_data, key_data_len); buf = key_data; + qdf_mem_copy(fils_info->ick, buf, ick_len); fils_info->ick_len = ick_len; buf += ick_len; + qdf_mem_copy(fils_info->kek, buf, kek_len); fils_info->kek_len = kek_len; buf += kek_len; + qdf_mem_copy(fils_info->tk, buf, tk_len); fils_info->tk_len = tk_len; + buf += tk_len; + + /* + * Derive FILS-FT: + * FILS-FT = + * L(FILS-Key-Data, ICK_bits + KEK_bits + TK_bits, FILS-FT_bits) + */ + if (pe_session->is11Rconnection && fils_ft_len) { + qdf_mem_copy(fils_info->fils_ft, buf, fils_ft_len); + fils_info->fils_ft_len = fils_ft_len; + } + qdf_mem_zero(data, data_len); qdf_mem_free(data); } @@ -597,9 +706,9 @@ static void lim_generate_pmkid(tpPESession pe_session) if (!fils_info) return; - qdf_get_hash(lim_get_crypto_type(fils_info->akm), 1, - &fils_info->fils_erp_reauth_pkt, - &fils_info->fils_erp_reauth_pkt_len, hash); + qdf_get_hash(lim_get_hash_crypto_type(fils_info->akm), 1, + &fils_info->fils_erp_reauth_pkt, + &fils_info->fils_erp_reauth_pkt_len, hash); qdf_mem_copy(fils_info->fils_pmkid, hash, PMKID_LEN); lim_fils_data_dump("PMKID", fils_info->fils_pmkid, PMKID_LEN); } @@ -644,9 +753,9 @@ static void lim_generate_pmk(tpPESession pe_session) addr[0] = fils_info->fils_rmsk; len[0] = fils_info->fils_rmsk_len; lim_fils_data_dump("Nonce", nounce, nounce_len); - if (qdf_get_hmac_hash(lim_get_crypto_type(fils_info->akm), nounce, - nounce_len, 1, - &addr[0], &len[0], fils_info->fils_pmk) < 0) + if (qdf_get_hmac_hash(lim_get_hmac_crypto_type(fils_info->akm), nounce, + nounce_len, 1, &addr[0], &len[0], + fils_info->fils_pmk) < 0) pe_err("failed to generate PMK"); } @@ -1006,6 +1115,33 @@ void lim_add_fils_data_to_auth_frame(tpPESession session, lim_fils_data_dump("FILS RSN", fils_info->rsn_ie, fils_info->rsn_ie_len); + /* + * FT-FILS IEEE-802.11ai specification mandates + * MDIE to be sent in auth frame during initial + * mobility domain association + */ + if (session->pLimJoinReq->is11Rconnection) { + struct bss_description *bss_desc; + + bss_desc = &session->pLimJoinReq->bssDescription; + + if (bss_desc->mdiePresent) { + /* Populate MDIE received from AP */ + *body = SIR_MDIE_ELEMENT_ID; + body++; + *body = SIR_MDIE_SIZE; + body++; + qdf_mem_copy(body, &bss_desc->mdie[0], + SIR_MDIE_SIZE); + pe_debug("FILS: mdie = %02x %02x %02x", + bss_desc->mdie[0], bss_desc->mdie[1], + bss_desc->mdie[2]); + body += SIR_MDIE_SIZE; + } else { + pe_err("FT-FILS: MDIE not advertised by AP"); + } + } + /* ***Nounce*** */ /* Add element id */ *body = SIR_MAX_ELEMENT_ID; @@ -1061,6 +1197,231 @@ void lim_add_fils_data_to_auth_frame(tpPESession session, body = body + fils_info->fils_erp_reauth_pkt_len; } +/** + * lim_generate_fils_pmkr0() - Derive PMKR0 and PMKR0-Name from FT-FILS + * key data + * @pe_session: pointer to pe_session + * + * Return: QDF_STATUS + */ +static QDF_STATUS lim_generate_fils_pmkr0(tpPESession pe_session) +{ + uint8_t *key_data, *data_buf; + uint8_t key_label[] = FT_PMK_R0_KEY_LABEL; + uint8_t key_data_len, ssid_length, r0kh_len, mdid_len; + uint8_t *r0_key_data; + uint8_t *hash; + uint8_t r0_key_data_len; + uint8_t pmkr0_len; + uint8_t *buf, *pmkr0_name_salt; + uint8_t *scatter_list[PMKR0_SCATTER_LIST_ELEM]; + uint32_t len[PMKR0_SCATTER_LIST_ELEM]; + uint16_t data_buf_len; + QDF_STATUS status = QDF_STATUS_SUCCESS; + struct pe_fils_session *fils_info = pe_session->fils_info; + struct bss_description *bss_desc = + &pe_session->pLimJoinReq->bssDescription; + + if (!fils_info) + return QDF_STATUS_E_FAILURE; + + ssid_length = pe_session->ssId.length; + r0kh_len = fils_info->ft_ie.r0kh_id_len; + mdid_len = (SIR_MDIE_SIZE - 1); + pmkr0_len = lim_get_Q_length(fils_info->akm); + r0_key_data_len = pmkr0_len + FILS_FT_PMK_R0_SALT_LEN; + + /* + * [IEEE 802.11ai 12.7.1.7.3] + * R0-Key-Data = KDF-Hash-Length(XXKey, "FT-R0", SSIDlength || SSID || + * MDID || R0KHlength || R0KH-ID || S0KH-ID) + * PMK-R0 = L(R0-Key-Data, 0, Q) + * PMK-R0Name-Salt = L(R0-Key-Data, Q, 128) + * Length = Q + 128 + */ + key_data_len = (1 + ssid_length + mdid_len + 1 + r0kh_len + + QDF_MAC_ADDR_SIZE); + pe_debug("FT-FILS: ssid_length:%d MDID len:%d R0KH len:%d key_data len:%d", + ssid_length, mdid_len, r0kh_len, key_data_len); + + data_buf_len = (key_data_len + FILS_FT_MAX_R0_KEY_DATA_LEN + + SHA384_DIGEST_SIZE); + data_buf = qdf_mem_malloc(data_buf_len); + if (!data_buf) + return QDF_STATUS_E_NOMEM; + + key_data = &data_buf[0]; + r0_key_data = &data_buf[key_data_len]; + hash = &data_buf[key_data_len + FILS_FT_MAX_R0_KEY_DATA_LEN]; + + /* + * key_data is (SSIDlength || SSID || MDID || R0KHlength || R0KH-ID || + * S0KH-ID) + */ + buf = key_data; + + *key_data = pe_session->ssId.length; + key_data += 1; + + qdf_mem_copy(key_data, pe_session->ssId.ssId, ssid_length); + key_data += ssid_length; + + qdf_mem_copy(key_data, bss_desc->mdie, mdid_len); + key_data += mdid_len; + + *key_data = r0kh_len; + key_data += 1; + + qdf_mem_copy(key_data, fils_info->ft_ie.r0kh_id, r0kh_len); + key_data += r0kh_len; + + qdf_mem_copy(key_data, pe_session->selfMacAddr, QDF_MAC_ADDR_SIZE); + + pe_debug("FT-FILS: Derive R0-Key-Data"); + status = lim_get_key_from_prf(lim_get_hmac_crypto_type(fils_info->akm), + fils_info->fils_ft, + fils_info->fils_ft_len, key_label, + buf, key_data_len, r0_key_data, + r0_key_data_len); + if (QDF_IS_STATUS_ERROR(status)) + goto free_buf; + + /* PMK-R0 is the first Q bytes of R0-Key-Data */ + qdf_mem_copy(fils_info->pmkr0, r0_key_data, pmkr0_len); + fils_info->pmkr0_len = pmkr0_len; + + /* PMK-R0Name-Salt = L(R0-Key-Data, Q, 128) */ + pmkr0_name_salt = r0_key_data + pmkr0_len; + + /* + * [IEEE 802.11-2016 12.7.1.7.3] + * PMKR0Name = Truncate-128(Hash("FT-R0N" || PMK-R0Name-Salt) + * The Hash function requires the crypto type, number of scatterlist + * parameters, scatterlist, lengths of scatterlist arguments, pointer + * to output hash. + * + * The scatterlist has two arguments - label "FT-R0N" and + * PMK-R0Name-Salt + * + */ + scatter_list[SCTR_LST_ELEM0] = FT_PMK_R0_NAME_KEY_LABEL; + len[SCTR_LST_ELEM0] = SCTR_LST_R0_LABEL_LEN; + scatter_list[SCTR_LST_ELEM1] = pmkr0_name_salt; + len[SCTR_LST_ELEM1] = FILS_FT_PMK_R0_SALT_LEN; + + pe_debug("FT-FILS: Derive PMK-R0 Name"); + if (qdf_get_hash(lim_get_hash_crypto_type(fils_info->akm), + PMKR0_SCATTER_LIST_ELEM, scatter_list, len, + hash) < 0) { + pe_err("FT-FILS: PMK-R0Name derivation failed"); + status = QDF_STATUS_E_FAILURE; + goto free_buf; + } + qdf_mem_copy(fils_info->pmkr0_name, hash, FILS_PMK_NAME_LEN); + +free_buf: + qdf_mem_zero(data_buf, data_buf_len); + qdf_mem_free(data_buf); + + return status; +} + +/** + * lim_generate_fils_pmkr1_name() - Derive PMKR1 and PMKR1-Name from FT-FILS + * key data + * @pe_session: pointer to pe_session + * + * Return: None + */ +static QDF_STATUS lim_generate_fils_pmkr1_name(tpPESession pe_session) +{ + uint8_t *hash; + uint8_t *scatter_list[PMKR1_SCATTER_LIST_ELEM]; + uint32_t len[PMKR1_SCATTER_LIST_ELEM]; + uint8_t *buf; + uint8_t gp_mgmt_cipher_suite[4]; + struct pe_fils_session *fils_info = pe_session->fils_info; + + if (!fils_info) + return QDF_STATUS_E_FAILURE; + + hash = qdf_mem_malloc(SHA384_DIGEST_SIZE); + if (!hash) + return QDF_STATUS_E_NOMEM; + + /* + * [IEEE 802.11-2016 12.7.1.7.4] + * PMKR1Name = Truncate-128(Hash("FT-R1N" || PMKR0Name || + * R1KH-ID || S1KH-ID)) + */ + scatter_list[SCTR_LST_ELEM0] = FT_PMK_R1_NAME_KEY_LABEL; + len[SCTR_LST_ELEM0] = SCTR_LST_R1_LABEL_LEN; + scatter_list[SCTR_LST_ELEM1] = fils_info->pmkr0_name; + len[SCTR_LST_ELEM1] = FILS_PMK_NAME_LEN; + scatter_list[SCTR_LST_ELEM2] = fils_info->ft_ie.r1kh_id; + len[SCTR_LST_ELEM2] = FT_R1KH_ID_LEN; + scatter_list[SCTR_LST_ELEM3] = pe_session->selfMacAddr; + len[SCTR_LST_ELEM3] = QDF_MAC_ADDR_SIZE; + + if (qdf_get_hash(lim_get_hash_crypto_type(fils_info->akm), + PMKR1_SCATTER_LIST_ELEM, scatter_list, len, + hash) < 0) { + qdf_mem_zero(hash, SHA384_DIGEST_SIZE); + qdf_mem_free(hash); + return QDF_STATUS_E_FAILURE; + } + qdf_mem_copy(fils_info->pmkr1_name, hash, FILS_PMK_NAME_LEN); + + if (fils_info->rsn_ie_len) { + if (fils_info->group_mgmt_cipher_present) { + /* + * If 802.11w is enabled, group management cipher + * suite is added at the end of RSN IE after + * PMKID. Since the driver has opaque RSN IE + * saved in fils_session, strip the last 4 bytes + * of the RSN IE to get group mgmt cipher suite. + * Then copy the PMKID followed by the grp mgmt cipher + * suite. + */ + buf = fils_info->rsn_ie + fils_info->rsn_ie_len - 4; + qdf_mem_copy(gp_mgmt_cipher_suite, buf, 4); + buf -= 2; + } else { + buf = fils_info->rsn_ie + fils_info->rsn_ie_len; + } + + /* + * Add PMKID count as 1. PMKID count field is 2 bytes long. + * Copy the PMKR1-Name in the PMKID list at the end of the + * RSN IE. + */ + *buf = 1; + buf += 2; + qdf_mem_copy(buf, fils_info->pmkr1_name, FILS_PMK_NAME_LEN); + if (fils_info->group_mgmt_cipher_present) { + fils_info->rsn_ie_len += FILS_PMK_NAME_LEN; + fils_info->rsn_ie[1] += (FILS_PMK_NAME_LEN); + } else { + fils_info->rsn_ie_len += (2 + FILS_PMK_NAME_LEN); + fils_info->rsn_ie[1] += (2 + FILS_PMK_NAME_LEN); + } + + if (fils_info->group_mgmt_cipher_present) { + buf += FILS_PMK_NAME_LEN; + qdf_mem_copy(buf, gp_mgmt_cipher_suite, 4); + } + } else { + pe_err("FT-FILS: RSN IE not present"); + qdf_mem_zero(hash, SHA384_DIGEST_SIZE); + qdf_mem_free(hash); + return QDF_STATUS_E_FAILURE; + } + + qdf_mem_zero(hash, SHA384_DIGEST_SIZE); + qdf_mem_free(hash); + return QDF_STATUS_SUCCESS; +} + /** * lim_process_fils_auth_frame2()- This API process fils data from auth response * @mac_ctx: mac context @@ -1077,6 +1438,7 @@ bool lim_process_fils_auth_frame2(tpAniSirGlobal mac_ctx, uint32_t ret; bool pmkid_found = false; tDot11fIERSN dot11f_ie_rsn = {0}; + QDF_STATUS status; if (!pe_session->fils_info) return false; @@ -1092,6 +1454,17 @@ bool lim_process_fils_auth_frame2(tpAniSirGlobal mac_ctx, return false; } + /* + * copy FTIE to fils_info and send it over assoc response frame + * for FT-FILS connection + */ + if (pe_session->is11Rconnection && pe_session->fils_info) { + pe_session->fils_info->ft_ie = rx_auth_frm_body->ft_ie; + if (!pe_session->fils_info->ft_ie.present) { + pe_err("FT-FILS: NO FTIE in auth response"); + } + } + for (i = 0; i < dot11f_ie_rsn.pmkid_count; i++) { if (qdf_mem_cmp(dot11f_ie_rsn.pmkid[i], pe_session->fils_info->fils_pmkid, @@ -1110,6 +1483,15 @@ bool lim_process_fils_auth_frame2(tpAniSirGlobal mac_ctx, return false; } lim_get_keys(pe_session); + if (pe_session->is11Rconnection) { + status = lim_generate_fils_pmkr0(pe_session); + if (QDF_IS_STATUS_ERROR(status)) + return false; + + status = lim_generate_fils_pmkr1_name(pe_session); + if (QDF_IS_STATUS_ERROR(status)) + return false; + } lim_generate_key_auth(pe_session); lim_generate_ap_key_auth(pe_session); return true; @@ -1123,11 +1505,14 @@ bool lim_process_fils_auth_frame2(tpAniSirGlobal mac_ctx, * * Return: None */ -void lim_update_fils_config(tpPESession session, - tpSirSmeJoinReq sme_join_req) +void lim_update_fils_config(tpAniSirGlobal mac_ctx, + tpPESession session, + tpSirSmeJoinReq sme_join_req) { struct pe_fils_session *csr_fils_info; struct cds_fils_connection_info *fils_config_info; + tDot11fIERSN dot11f_ie_rsn = {0}; + uint32_t ret; fils_config_info = &sme_join_req->fils_con_info; csr_fils_info = session->fils_info; @@ -1181,6 +1566,26 @@ void lim_update_fils_config(tpPESession session, qdf_mem_copy(csr_fils_info->rsn_ie, sme_join_req->rsnIE.rsnIEdata, sme_join_req->rsnIE.length); + /* + * When AP is MFP capable and STA is also MFP capable, + * the supplicant fills the RSN IE with PMKID count as 0 + * and PMKID as 0, then appends the group management cipher + * suite. This opaque RSN IE is copied into fils_info in pe + * session. For FT-FILS association, STA has to fill the + * PMKR0 derived after authentication response is received from + * the AP. So unpack the RSN IE to find if group management cipher + * suite is present and based on this RSN IE will be constructed in + * lim_generate_fils_pmkr1_name() for FT-FILS connection. + */ + ret = dot11f_unpack_ie_rsn(mac_ctx, csr_fils_info->rsn_ie + 2, + csr_fils_info->rsn_ie_len - 2, + &dot11f_ie_rsn, 0); + if (DOT11F_SUCCEEDED(ret)) { + csr_fils_info->group_mgmt_cipher_present = + dot11f_ie_rsn.gp_mgmt_cipher_suite_present; + } else { + pe_err("FT-FILS: Invalid RSN IE"); + } csr_fils_info->fils_pmk_len = fils_config_info->pmk_len; if (fils_config_info->pmk_len) { @@ -1422,6 +1827,34 @@ static QDF_STATUS lim_parse_kde_elements(tpAniSirGlobal mac_ctx, return QDF_STATUS_SUCCESS; } +void lim_update_fils_hlp_data(struct qdf_mac_addr *hlp_frm_src_mac, + struct qdf_mac_addr *hlp_frm_dest_mac, + uint16_t frm_hlp_len, uint8_t *frm_hlp_data, + tpPESession pe_session) +{ + struct pe_fils_session *pe_fils_info = pe_session->fils_info; + + if (!pe_fils_info) { + pe_err("Not a fils connection"); + return; + } + + if (frm_hlp_data && frm_hlp_len) { + qdf_mem_free(pe_fils_info->hlp_data); + pe_fils_info->hlp_data = qdf_mem_malloc(frm_hlp_len); + if (!pe_fils_info->hlp_data) + return; + + pe_debug("FILS: hlp_data_len:%d", frm_hlp_len); + cds_copy_hlp_info(hlp_frm_dest_mac, hlp_frm_src_mac, + frm_hlp_len, frm_hlp_data, + &pe_fils_info->dst_mac, + &pe_fils_info->src_mac, + &pe_fils_info->hlp_data_len, + pe_fils_info->hlp_data); + } +} + bool lim_verify_fils_params_assoc_rsp(tpAniSirGlobal mac_ctx, tpPESession session_entry, tpSirAssocRsp assoc_rsp, @@ -1479,6 +1912,12 @@ bool lim_verify_fils_params_assoc_rsp(tpAniSirGlobal mac_ctx, pe_err("KDE parsing fails"); goto verify_fils_params_fails; } + + lim_update_fils_hlp_data(&assoc_rsp->dst_mac, + &assoc_rsp->src_mac, + assoc_rsp->hlp_data_len, + assoc_rsp->hlp_data, + session_entry); return true; verify_fils_params_fails: @@ -1845,9 +2284,10 @@ void lim_update_fils_rik(tpPESession pe_session, if ((!lim_is_fils_connection(pe_session) || !pe_fils_info) && (req_buffer->is_fils_connection)) { if (roam_fils_params->rrk_length > FILS_MAX_RRK_LENGTH) { - pe_debug("FILS rrk len(%d) max (%d)", - roam_fils_params->rrk_length, - FILS_MAX_RRK_LENGTH); + if (lim_is_fils_connection(pe_session)) + pe_debug("FILS rrk len(%d) max (%d)", + roam_fils_params->rrk_length, + FILS_MAX_RRK_LENGTH); return; } @@ -1866,14 +2306,20 @@ void lim_update_fils_rik(tpPESession pe_session, } if ((pe_fils_info->fils_rik_len > FILS_MAX_RIK_LENGTH) || !pe_fils_info->fils_rik) { - pe_err("Fils rik len(%d) max %d", pe_fils_info->fils_rik_len, - FILS_MAX_RIK_LENGTH); + if (pe_fils_info->fils_rik) + pe_debug("Fils rik len(%d) max %d", + pe_fils_info->fils_rik_len, + FILS_MAX_RIK_LENGTH); return; } roam_fils_params->rik_length = pe_fils_info->fils_rik_len; qdf_mem_copy(roam_fils_params->rik, pe_fils_info->fils_rik, - roam_fils_params->rik_length); - pe_debug("fils rik len %d", roam_fils_params->rik_length); + roam_fils_params->rik_length); + qdf_mem_copy(roam_fils_params->fils_ft, pe_fils_info->fils_ft, + pe_fils_info->fils_ft_len); + roam_fils_params->fils_ft_len = pe_fils_info->fils_ft_len; + pe_debug("fils rik len %d ft-len:%d", roam_fils_params->rik_length, + pe_fils_info->fils_ft_len); } #endif diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_message_queue.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_message_queue.c index c8602f0da2d5..a62e467894ff 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_message_queue.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_message_queue.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -748,7 +748,6 @@ static void lim_fill_sap_bcn_pkt_meta(struct scan_cache_entry *scan_entry, cds_pkt_t *rx_pkt) { rx_pkt->pkt_meta.channel = scan_entry->channel.chan_idx; - rx_pkt->pkt_meta.mpdu_hdr_len = sizeof(struct ieee80211_frame); rx_pkt->pkt_meta.mpdu_len = scan_entry->raw_frame.len; rx_pkt->pkt_meta.mpdu_data_len = rx_pkt->pkt_meta.mpdu_len - @@ -1014,12 +1013,15 @@ lim_check_mgmt_registered_frames(tpAniSirGlobal mac_ctx, uint8_t *buff_desc, uint16_t frm_len; uint8_t type, sub_type; bool match = false; + tpSirMacActionFrameHdr action_hdr; + uint8_t actionID, category; QDF_STATUS qdf_status; hdr = WMA_GET_RX_MAC_HEADER(buff_desc); fc = hdr->fc; frm_type = (fc.type << 2) | (fc.subType << 4); body = WMA_GET_RX_MPDU_DATA(buff_desc); + action_hdr = (tpSirMacActionFrameHdr) body; frm_len = WMA_GET_RX_PAYLOAD_LEN(buff_desc); qdf_mutex_acquire(&mac_ctx->lim.lim_frame_register_lock); @@ -1067,6 +1069,28 @@ lim_check_mgmt_registered_frames(tpAniSirGlobal mac_ctx, uint8_t *buff_desc, if (match) { QDF_TRACE(QDF_MODULE_ID_PE, QDF_TRACE_LEVEL_DEBUG, FL("rcvd frame match with registered frame params")); + if (mac_ctx->roam.configParam.p2p_disable_roam && + session_entry && LIM_IS_STA_ROLE(session_entry) && + (policy_mgr_mode_specific_connection_count(mac_ctx->psoc, + PM_P2P_CLIENT_MODE, NULL) || + policy_mgr_mode_specific_connection_count(mac_ctx->psoc, + PM_P2P_GO_MODE, NULL))) { + if ((frm_len >= sizeof(*action_hdr)) && action_hdr && + fc.type == SIR_MAC_MGMT_FRAME && + fc.subType == SIR_MAC_MGMT_ACTION) { + actionID = action_hdr->actionID; + category = action_hdr->category; + pe_debug("category: %d action: %d", + category, actionID); + if (category == SIR_MAC_ACTION_WNM && + (actionID == SIR_MAC_WNM_BSS_TM_QUERY || + actionID == SIR_MAC_WNM_BSS_TM_REQUEST || + actionID == SIR_MAC_WNM_BSS_TM_RESPONSE)) { + pe_debug("p2p session active drop BTM frame"); + return match; + } + } + } /* Indicate this to SME */ lim_send_sme_mgmt_frame_ind(mac_ctx, hdr->fc.subType, (uint8_t *) hdr, @@ -1701,6 +1725,11 @@ static void lim_process_messages(tpAniSirGlobal mac_ctx, qdf_mem_free(msg->bodyptr); msg->bodyptr = NULL; break; + case eWNI_SME_MON_DEINIT_SESSION: + lim_mon_deinit_session(mac_ctx, msg->bodyptr); + qdf_mem_free(msg->bodyptr); + msg->bodyptr = NULL; + break; #ifdef FEATURE_WLAN_TDLS case SIR_HAL_TDLS_IND: tdls_ind = (tpSirTdlsInd) msg->bodyptr; diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_mlm_req_messages.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_mlm_req_messages.c index 1485cecb55d1..dca58c9c5557 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_mlm_req_messages.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_mlm_req_messages.c @@ -636,11 +636,8 @@ static void lim_post_join_set_link_state_callback(tpAniSirGlobal mac, } qdf_mem_free(session_cb_param); - pe_debug("Sessionid %d set link state(%d) cb status: %d", - session_entry->peSessionId, session_entry->limMlmState, - status); - if (!status) { + pe_err("failed to find pe session for session id:%d", session_entry->peSessionId); goto failure; @@ -655,12 +652,6 @@ static void lim_post_join_set_link_state_callback(tpAniSirGlobal mac, session_entry->channelChangeReasonCode = LIM_SWITCH_CHANNEL_JOIN; session_entry->pLimMlmReassocRetryReq = NULL; - pe_debug("[lim_process_mlm_join_req]: suspend link success(%d) " - "on sessionid: %d setting channel to: %d with ch_width :%d " - "and maxtxPower: %d", status, session_entry->peSessionId, - session_entry->currentOperChannel, - session_entry->ch_width, - session_entry->maxTxPower); lim_set_channel(mac, session_entry->currentOperChannel, session_entry->ch_center_freq_seg0, session_entry->ch_center_freq_seg1, @@ -717,9 +708,6 @@ lim_process_mlm_post_join_suspend_link(tpAniSirGlobal mac_ctx, session->peSessionId; lnk_state = eSIR_LINK_PREASSOC_STATE; - pe_debug("[lim_process_mlm_join_req]: lnk_state: %d", - lnk_state); - pe_session_param = qdf_mem_malloc(sizeof(struct session_params)); if (pe_session_param) { pe_session_param->session_id = session->peSessionId; @@ -803,27 +791,8 @@ static void lim_process_mlm_join_req(tpAniSirGlobal mac_ctx, uint32_t *msg) /* Hold onto Join request parameters */ session->pLimMlmJoinReq = (tpLimMlmJoinReq) msg; - if (is_lim_session_off_channel(mac_ctx, sessionid)) { - pe_debug("SessionId:%d LimSession is on OffChannel", - sessionid); - /* suspend link */ - pe_debug("Suspend link, sessionid %d is off channel", - sessionid); - lim_process_mlm_post_join_suspend_link(mac_ctx, - QDF_STATUS_SUCCESS, (uint32_t *)session); - } else { - pe_debug("No need to Suspend link"); - /* - * No need to Suspend link as LimSession is not - * off channel, calling - * lim_process_mlm_post_join_suspend_link with - * status as SUCCESS. - */ - pe_debug("SessionId:%d Join req on current chan", - sessionid); - lim_process_mlm_post_join_suspend_link(mac_ctx, + lim_process_mlm_post_join_suspend_link(mac_ctx, QDF_STATUS_SUCCESS, (uint32_t *)session); - } return; } else { /** @@ -1045,12 +1014,11 @@ static void lim_process_mlm_auth_req(tpAniSirGlobal mac_ctx, uint32_t *msg) return; } - pe_debug("Process Auth Req sessionID %d Systemrole %d" - "mlmstate %d from: " MAC_ADDRESS_STR - " with authtype %d", session_id, - GET_LIM_SYSTEM_ROLE(session), session->limMlmState, - MAC_ADDR_ARRAY(mac_ctx->lim.gpLimMlmAuthReq->peerMacAddr), - mac_ctx->lim.gpLimMlmAuthReq->authType); + pe_debug("vdev %d Systemrole %d mlmstate %d from: " QDF_MAC_ADDR_STR "with authtype %d", + session->smeSessionId, GET_LIM_SYSTEM_ROLE(session), + session->limMlmState, + QDF_MAC_ADDR_ARRAY(mac_ctx->lim.gpLimMlmAuthReq->peerMacAddr), + mac_ctx->lim.gpLimMlmAuthReq->authType); sir_copy_mac_addr(curr_bssid, session->bssId); @@ -1249,8 +1217,7 @@ static void lim_process_mlm_assoc_req(tpAniSirGlobal mac_ctx, uint32_t *msg_buf) MTRACE(mac_trace(mac_ctx, TRACE_CODE_MLM_STATE, session_entry->peSessionId, session_entry->limMlmState)); - pe_debug("SessionId:%d Sending Assoc_Req Frame", - session_entry->peSessionId); + pe_debug("vdev %d Sending Assoc_Req Frame", session_entry->smeSessionId); /* Prepare and send Association request frame */ lim_send_assoc_req_mgmt_frame(mac_ctx, mlm_assoc_req, session_entry); @@ -1316,12 +1283,6 @@ lim_process_mlm_disassoc_req_ntf(tpAniSirGlobal mac_ctx, goto end; } - pe_debug("Process DisAssoc Req on sessionID %d Systemrole %d" - "mlmstate %d from: " MAC_ADDRESS_STR, - mlm_disassocreq->sessionId, GET_LIM_SYSTEM_ROLE(session), - session->limMlmState, - MAC_ADDR_ARRAY(mlm_disassocreq->peer_macaddr.bytes)); - qdf_mem_copy(curr_bssid.bytes, session->bssId, QDF_MAC_ADDR_SIZE); switch (GET_LIM_SYSTEM_ROLE(session)) { @@ -1608,10 +1569,6 @@ lim_process_mlm_disassoc_req(tpAniSirGlobal mac_ctx, uint32_t *msg_buf) } mlm_disassoc_req = (tLimMlmDisassocReq *) msg_buf; - pe_debug("Process disassoc req, sessionID %d from: "MAC_ADDRESS_STR, - mlm_disassoc_req->sessionId, - MAC_ADDR_ARRAY(mlm_disassoc_req->peer_macaddr.bytes)); - lim_process_mlm_disassoc_req_ntf(mac_ctx, QDF_STATUS_SUCCESS, (uint32_t *) msg_buf); } @@ -1654,12 +1611,6 @@ lim_process_mlm_deauth_req_ntf(tpAniSirGlobal mac_ctx, qdf_mem_free(mlm_deauth_req); return; } - pe_debug("Process Deauth Req on sessionID %d Systemrole %d" - "mlmstate %d from: " MAC_ADDRESS_STR, - mlm_deauth_req->sessionId, - GET_LIM_SYSTEM_ROLE(session), - session->limMlmState, - MAC_ADDR_ARRAY(mlm_deauth_req->peer_macaddr.bytes)); sir_copy_mac_addr(curr_bssId, session->bssId); switch (GET_LIM_SYSTEM_ROLE(session)) { @@ -1695,11 +1646,6 @@ lim_process_mlm_deauth_req_ntf(tpAniSirGlobal mac_ctx, return; } - pe_debug("send deauth rsp with ret code %d for" MAC_ADDRESS_STR, - eSIR_SME_DEAUTH_STATUS, - MAC_ADDR_ARRAY( - mlm_deauth_req->peer_macaddr.bytes)); - sme_deauth_rsp->messageType = eWNI_SME_DEAUTH_RSP; sme_deauth_rsp->length = @@ -1902,11 +1848,6 @@ lim_process_mlm_deauth_req(tpAniSirGlobal mac_ctx, uint32_t *msg_buf) } mlm_deauth_req = (tLimMlmDeauthReq *) msg_buf; - pe_debug("Process Deauth Req on sessionID %d from: " - MAC_ADDRESS_STR, - mlm_deauth_req->sessionId, - MAC_ADDR_ARRAY(mlm_deauth_req->peer_macaddr.bytes)); - session = pe_find_session_by_session_id(mac_ctx, mlm_deauth_req->sessionId); if (NULL == session) { @@ -2224,47 +2165,53 @@ static void lim_process_periodic_join_probe_req_timer(tpAniSirGlobal mac_ctx) } /** - * lim_process_auth_retry_timer()- function to Retry Auth + * lim_process_auth_retry_timer()- function to Retry Auth when auth timeout + * occurs * @mac_ctx:pointer to global mac * * Return: void */ - static void lim_process_auth_retry_timer(tpAniSirGlobal mac_ctx) { - tpPESession session_entry; + tpPESession session_entry; + tAniAuthType auth_type; + tLimTimers *lim_timers = &mac_ctx->lim.limTimers; + uint16_t vdev_id = + lim_timers->g_lim_periodic_auth_retry_timer.sessionId; + + session_entry = pe_find_session_by_session_id(mac_ctx, vdev_id); - session_entry = - pe_find_session_by_session_id(mac_ctx, - mac_ctx->lim.limTimers.g_lim_periodic_auth_retry_timer.sessionId); if (NULL == session_entry) { - pe_err("session does not exist for given SessionId: %d", - mac_ctx->lim.limTimers. - g_lim_periodic_auth_retry_timer.sessionId); + pe_err("session does not exist for vdev_id: %d", vdev_id); return; } if (tx_timer_running(&mac_ctx->lim.limTimers.gLimAuthFailureTimer) && - (session_entry->limMlmState == eLIM_MLM_WT_AUTH_FRAME2_STATE) && - (LIM_AUTH_ACK_RCD_SUCCESS != mac_ctx->auth_ack_status)) { + (session_entry->limMlmState == eLIM_MLM_WT_AUTH_FRAME2_STATE) && + (LIM_AUTH_ACK_RCD_SUCCESS != mac_ctx->auth_ack_status)) { tSirMacAuthFrameBody auth_frame; - /* * Send the auth retry only in case we have received ack failure * else just restart the retry timer. */ - if (LIM_AUTH_ACK_RCD_FAILURE == mac_ctx->auth_ack_status) { + if (LIM_AUTH_ACK_RCD_FAILURE == mac_ctx->auth_ack_status && + mac_ctx->lim.gpLimMlmAuthReq) { + auth_type = mac_ctx->lim.gpLimMlmAuthReq->authType; + /* Prepare & send Authentication frame */ - auth_frame.authAlgoNumber = - (uint8_t) mac_ctx->lim.gpLimMlmAuthReq->authType; + if (session_entry->sae_pmk_cached && + auth_type == eSIR_AUTH_TYPE_SAE) + auth_frame.authAlgoNumber = eSIR_OPEN_SYSTEM; + else + auth_frame.authAlgoNumber = (uint8_t)auth_type; + auth_frame.authTransactionSeqNumber = SIR_MAC_AUTH_FRAME_1; auth_frame.authStatusCode = 0; pe_debug("Retry Auth"); mac_ctx->auth_ack_status = LIM_AUTH_ACK_NOT_RCD; lim_increase_fils_sequence_number(session_entry); - lim_send_auth_mgmt_frame(mac_ctx, - &auth_frame, + lim_send_auth_mgmt_frame(mac_ctx, &auth_frame, mac_ctx->lim.gpLimMlmAuthReq->peerMacAddr, LIM_NO_WEP_IN_FC, session_entry); } diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_mlm_rsp_messages.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_mlm_rsp_messages.c index e993b0f7ca2b..60f3558139cb 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_mlm_rsp_messages.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_mlm_rsp_messages.c @@ -42,6 +42,7 @@ #include "wlan_policy_mgr_api.h" #include "nan_datapath.h" #include "wlan_reg_services_api.h" +#include "wlan_pkt_capture_ucfg_api.h" #define MAX_SUPPORTED_PEERS_WEP 16 @@ -290,8 +291,6 @@ void lim_process_mlm_join_cnf(tpAniSirGlobal mac_ctx, result_code = ((tLimMlmJoinCnf *) msg)->resultCode; /* Process Join confirm from MLM */ if (result_code == eSIR_SME_SUCCESS) { - pe_debug("***SessionId:%d Joined ESS ***", - join_cnf->sessionId); /* Setup hardware upfront */ if (lim_sta_send_add_bss_pre_assoc(mac_ctx, false, session_entry) == QDF_STATUS_SUCCESS) @@ -336,11 +335,7 @@ static void lim_send_mlm_assoc_req(tpAniSirGlobal mac_ctx, uint32_t tele_bcn = 0; tpSirMacCapabilityInfo cap_info; - /* Successful MAC based authentication. Trigger Association with BSS */ - pe_debug("SessionId: %d Authenticated with BSS", - session_entry->peSessionId); - - if (NULL == session_entry->pLimJoinReq) { + if (!session_entry->pLimJoinReq) { pe_err("Join Request is NULL"); /* No need to Assert. JOIN timeout will handle this error */ return; @@ -395,10 +390,6 @@ static void lim_send_mlm_assoc_req(tpAniSirGlobal mac_ctx, assoc_req->capabilityInfo = caps; cap_info = ((tpSirMacCapabilityInfo) &assoc_req->capabilityInfo); - pe_debug("Capabilities to be used in AssocReq=0x%X," - "privacy bit=%x shortSlotTime %x", caps, - cap_info->privacy, - cap_info->shortSlotTime); /* * If telescopic beaconing is enabled, set listen interval to @@ -560,6 +551,21 @@ void lim_process_mlm_auth_cnf(tpAniSirGlobal mac_ctx, uint32_t *msg) MTRACE(mac_trace(mac_ctx, TRACE_CODE_MLM_STATE, session_entry->peSessionId, session_entry->limMlmState)); + + /* WAR for some IOT issue on specific AP: + * STA failed to connect to SAE AP due to incorrect + * password is used. Then AP will still reject the + * authentication even correct password is used unless + * STA send deauth to AP upon authentication failure. + */ + if (auth_type == eSIR_AUTH_TYPE_SAE) { + pe_debug("Send deauth for SAE auth failure"); + lim_send_deauth_mgmt_frame(mac_ctx, + auth_cnf->protStatusCode, + auth_cnf->peerMacAddr, + session_entry, false); + } + /* * Need to send Join response with * auth failure to Host. @@ -1005,8 +1011,6 @@ static void lim_process_mlm_deauth_ind(tpAniSirGlobal mac_ctx, return; } role = GET_LIM_SYSTEM_ROLE(session); - pe_debug("*** Received Deauthentication from staId=%d role=%d***", - deauth_ind->aid, role); if (role == eLIM_STA_ROLE) { session->limSmeState = eLIM_SME_WT_DEAUTH_STATE; MTRACE(mac_trace(mac_ctx, TRACE_CODE_SME_STATE, @@ -1073,7 +1077,6 @@ void lim_process_mlm_deauth_cnf(tpAniSirGlobal pMac, uint32_t *pMsgBuf) } if (pMlmDeauthCnf->resultCode == eSIR_SME_SUCCESS) { psessionEntry->limSmeState = eLIM_SME_IDLE_STATE; - pe_debug("*** Deauthenticated with BSS ***"); } else psessionEntry->limSmeState = psessionEntry->limPrevSmeState; @@ -1596,8 +1599,6 @@ void lim_process_sta_mlm_del_bss_rsp(tpAniSirGlobal pMac, goto end; } if (QDF_STATUS_SUCCESS == pDelBssParams->status) { - pe_debug("STA received the DEL_BSS_RSP for BSSID: %X", - pDelBssParams->bssIdx); if (lim_set_link_state (pMac, eSIR_LINK_IDLE_STATE, psessionEntry->bssId, psessionEntry->selfMacAddr, NULL, @@ -1618,8 +1619,8 @@ void lim_process_sta_mlm_del_bss_rsp(tpAniSirGlobal pMac, statusCode = eSIR_SME_REFUSED; goto end; } - pe_debug("STA AssocID %d MAC", pStaDs->assocId); - lim_print_mac_addr(pMac, pStaDs->staAddr, LOGD); + pe_debug("STA AssocID %d MAC %pM", pStaDs->assocId, + pStaDs->staAddr); } else { pe_err("DEL BSS failed!"); statusCode = eSIR_SME_STOP_BSS_FAILURE; @@ -1813,8 +1814,8 @@ void lim_process_ap_mlm_del_sta_rsp(tpAniSirGlobal mac_ctx, goto end; } - pe_warn("AP received the DEL_STA_RSP for assocID: %X", - del_sta_params->assocId); + pe_debug("AP received the DEL_STA_RSP for assocID: %X", + del_sta_params->assocId); if ((eLIM_MLM_WT_DEL_STA_RSP_STATE != sta_ds->mlmStaContext.mlmState) && (eLIM_MLM_WT_ASSOC_DEL_STA_RSP_STATE != sta_ds->mlmStaContext.mlmState)) { @@ -2346,9 +2347,6 @@ lim_process_sta_add_bss_rsp_pre_assoc(tpAniSirGlobal mac_ctx, MTRACE(mac_trace(mac_ctx, TRACE_CODE_SME_STATE, session_entry->peSessionId, session_entry->limSmeState)); - pe_debug("SessionId:%d lim_post_mlm_message " - "LIM_MLM_AUTH_REQ with limSmeState: %d", - session_entry->peSessionId, session_entry->limSmeState); lim_post_mlm_message(mac_ctx, LIM_MLM_AUTH_REQ, (uint32_t *) pMlmAuthReq); return; @@ -2456,9 +2454,6 @@ lim_process_sta_mlm_add_bss_rsp(tpAniSirGlobal mac_ctx, session_entry->limMlmState)); /* to know the session started for self or for peer */ session_entry->statypeForBss = STA_ENTRY_PEER; - /* Now, send WMA_ADD_STA_REQ */ - pe_debug("SessionId: %d On STA: ADD_BSS was successful", - session_entry->peSessionId); sta_ds = dph_get_hash_entry(mac_ctx, DPH_STA_HASH_INDEX_PEER, &session_entry->dph.dphHashTable); @@ -2985,10 +2980,6 @@ static void lim_process_switch_channel_join_req( session_entry->limPrevMlmState = session_entry->limMlmState; session_entry->limMlmState = eLIM_MLM_WT_JOIN_BEACON_STATE; - pe_debug("Sessionid %d prev lim state %d new lim state %d " - "systemrole = %d", session_entry->peSessionId, - session_entry->limPrevMlmState, - session_entry->limMlmState, GET_LIM_SYSTEM_ROLE(session_entry)); /* Apply previously set configuration at HW */ lim_apply_configuration(mac_ctx, session_entry); @@ -3033,11 +3024,11 @@ static void lim_process_switch_channel_join_req( /* assign appropriate sessionId to the timer object */ mac_ctx->lim.limTimers.gLimPeriodicJoinProbeReqTimer.sessionId = session_entry->peSessionId; - pe_debug("Sessionid: %d Send Probe req on channel %d ssid:%.*s " - "BSSID: " MAC_ADDRESS_STR, session_entry->peSessionId, - session_entry->currentOperChannel, ssId.length, ssId.ssId, - MAC_ADDR_ARRAY( - session_entry->pLimMlmJoinReq->bssDescription.bssId)); + pe_debug("vdev %d Send Probe req on freq %d %.*s " QDF_MAC_ADDR_STR, + session_entry->smeSessionId, + session_entry->currentOperChannel, ssId.length, ssId.ssId, + QDF_MAC_ADDR_ARRAY( + session_entry->pLimMlmJoinReq->bssDescription.bssId)); /* * We need to wait for probe response, so start join @@ -3140,7 +3131,6 @@ void lim_process_switch_channel_rsp(tpAniSirGlobal pMac, void *body) psessionEntry->chainMask = pChnlParams->chainMask; psessionEntry->smpsMode = pChnlParams->smpsMode; psessionEntry->channelChangeReasonCode = 0xBAD; - pe_debug("channelChangeReasonCode %d", channelChangeReasonCode); switch (channelChangeReasonCode) { case LIM_SWITCH_CHANNEL_REASSOC: lim_process_switch_channel_re_assoc_req(pMac, psessionEntry, status); @@ -3156,13 +3146,11 @@ void lim_process_switch_channel_rsp(tpAniSirGlobal pMac, void *body) * THat way all this response handler does is call the call back * We can get rid of the reason code here. */ - if (pMac->lim.gpchangeChannelCallback) { - pe_debug("Channel changed hence invoke registered call back"); + if (pMac->lim.gpchangeChannelCallback) pMac->lim.gpchangeChannelCallback(pMac, status, pMac->lim. gpchangeChannelData, psessionEntry); - } /* If MCC upgrade/DBS downgrade happended during channel switch, * the policy manager connection table needs to be updated. */ @@ -3172,6 +3160,8 @@ void lim_process_switch_channel_rsp(tpAniSirGlobal pMac, void *body) pe_debug("Send p2p operating channel change conf action frame once first beacon is received on new channel"); psessionEntry->send_p2p_conf_frame = true; } + + ucfg_pkt_capture_record_channel(); break; case LIM_SWITCH_CHANNEL_SAP_DFS: { diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_probe_rsp_frame.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_probe_rsp_frame.c index fb3d0f59b7e0..55bbe01191ca 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_probe_rsp_frame.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_probe_rsp_frame.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -113,8 +113,6 @@ lim_process_probe_rsp_frame(tpAniSirGlobal mac_ctx, uint8_t *rx_Packet_info, pe_err("session_entry is NULL"); return; } - pe_debug("SessionId: %d ProbeRsp Frame is received", - session_entry->peSessionId); probe_rsp = qdf_mem_malloc(sizeof(tSirProbeRespBeacon)); if (NULL == probe_rsp) { @@ -127,10 +125,6 @@ lim_process_probe_rsp_frame(tpAniSirGlobal mac_ctx, uint8_t *rx_Packet_info, header = WMA_GET_RX_MAC_HEADER(rx_Packet_info); - pe_debug("Rx Probe Response with length = %d from "MAC_ADDRESS_STR, - WMA_GET_RX_MPDU_LEN(rx_Packet_info), - MAC_ADDR_ARRAY(header->sa)); - /* Validate IE information before processing Probe Response Frame */ if (lim_validate_ie_information_in_probe_rsp_frame(mac_ctx, rx_Packet_info) != @@ -141,11 +135,11 @@ lim_process_probe_rsp_frame(tpAniSirGlobal mac_ctx, uint8_t *rx_Packet_info, } frame_len = WMA_GET_RX_PAYLOAD_LEN(rx_Packet_info); - QDF_TRACE(QDF_MODULE_ID_PE, QDF_TRACE_LEVEL_DEBUG, - FL("Probe Resp Frame Received: BSSID " - MAC_ADDRESS_STR " (RSSI %d)"), - MAC_ADDR_ARRAY(header->bssId), - (uint) abs((int8_t)WMA_GET_RX_RSSI_NORMALIZED(rx_Packet_info))); + pe_debug("Probe Resp(len %d): " QDF_MAC_ADDR_STR " RSSI %d", + WMA_GET_RX_MPDU_LEN(rx_Packet_info), + QDF_MAC_ADDR_ARRAY(header->bssId), + (uint)abs((int8_t) + WMA_GET_RX_RSSI_NORMALIZED(rx_Packet_info))); /* Get pointer to Probe Response frame body */ body = WMA_GET_RX_MPDU_DATA(rx_Packet_info); /* Enforce Mandatory IEs */ diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_sme_req_messages.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_sme_req_messages.c index bf4cbdc6e9eb..7a226d2e1c6a 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_sme_req_messages.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_sme_req_messages.c @@ -479,6 +479,7 @@ static bool __lim_process_sme_sys_ready_ind(tpAniSirGlobal pMac, uint32_t *pMsgB if (ANI_DRIVER_TYPE(pMac) != QDF_DRIVER_TYPE_MFG) { ready_req->pe_roam_synch_cb = pe_roam_synch_callback; + ready_req->pe_disconnect_cb = pe_disconnect_callback; pe_register_mgmt_rx_frm_callback(pMac); pe_register_callbacks_with_wma(pMac, ready_req); pMac->lim.sme_msg_callback = ready_req->sme_msg_cb; @@ -614,7 +615,6 @@ __lim_handle_sme_start_bss_request(tpAniSirGlobal mac_ctx, uint32_t *msg_buf) NULL, 0, 0); #endif /* FEATURE_WLAN_DIAG_SUPPORT */ - pe_debug("Received START_BSS_REQ"); size = sizeof(tSirSmeStartBssReq); sme_start_bss_req = qdf_mem_malloc(size); if (NULL == sme_start_bss_req) { @@ -651,8 +651,10 @@ __lim_handle_sme_start_bss_request(tpAniSirGlobal mac_ctx, uint32_t *msg_buf) session = pe_create_session(mac_ctx, sme_start_bss_req->bssid.bytes, &session_id, mac_ctx->lim.maxStation, - sme_start_bss_req->bssType); - if (session == NULL) { + sme_start_bss_req->bssType, + sme_start_bss_req->sessionId, + sme_start_bss_req->bssPersona); + if (!session) { pe_warn("Session Can not be created"); ret_code = eSIR_SME_RESOURCES_UNAVAILABLE; goto free; @@ -695,9 +697,6 @@ __lim_handle_sme_start_bss_request(tpAniSirGlobal mac_ctx, uint32_t *msg_buf) /* Store the session related params in newly created session */ session->pLimStartBssReq = sme_start_bss_req; - /* Store SME session Id in sessionTable */ - session->smeSessionId = sme_start_bss_req->sessionId; - session->transactionId = sme_start_bss_req->transactionId; qdf_mem_copy(&(session->htConfig), @@ -716,8 +715,6 @@ __lim_handle_sme_start_bss_request(tpAniSirGlobal mac_ctx, uint32_t *msg_buf) (uint8_t *) &sme_start_bss_req->ssId, (sme_start_bss_req->ssId.length + 1)); - session->bssType = sme_start_bss_req->bssType; - session->nwType = sme_start_bss_req->nwType; session->beaconParams.beaconInterval = @@ -727,11 +724,6 @@ __lim_handle_sme_start_bss_request(tpAniSirGlobal mac_ctx, uint32_t *msg_buf) session->currentOperChannel = sme_start_bss_req->channelId; - /* Store Persona */ - session->pePersona = sme_start_bss_req->bssPersona; - QDF_TRACE(QDF_MODULE_ID_PE, QDF_TRACE_LEVEL_DEBUG, - FL("PE PERSONA=%d"), session->pePersona); - /* Update the phymode */ session->gLimPhyMode = sme_start_bss_req->nwType; @@ -749,9 +741,6 @@ __lim_handle_sme_start_bss_request(tpAniSirGlobal mac_ctx, uint32_t *msg_buf) session->vhtCapability = IS_DOT11_MODE_VHT(session->dot11mode); - pe_debug("HT[%d], VHT[%d]", - session->htCapability, session->vhtCapability); - if (IS_DOT11_MODE_HE(session->dot11mode)) { lim_update_session_he_capable(mac_ctx, session); lim_copy_bss_he_cap(session, sme_start_bss_req); @@ -760,9 +749,8 @@ __lim_handle_sme_start_bss_request(tpAniSirGlobal mac_ctx, uint32_t *msg_buf) session->txLdpcIniFeatureEnabled = sme_start_bss_req->txLdpcIniFeatureEnabled; #ifdef WLAN_FEATURE_11W - session->limRmfEnabled = - sme_start_bss_req->pmfCapable ? 1 : 0; - pe_debug("Session RMF enabled: %d", session->limRmfEnabled); + session->limRmfEnabled = sme_start_bss_req->pmfCapable ? 1 : 0; + pe_debug("RMF enabled: %d", session->limRmfEnabled); #endif qdf_mem_copy((void *)&session->rateSet, @@ -817,8 +805,6 @@ __lim_handle_sme_start_bss_request(tpAniSirGlobal mac_ctx, uint32_t *msg_buf) break; } - pe_debug("persona - %d, nss - %d", - session->pePersona, session->vdev_nss); session->nss = session->vdev_nss; if (!mac_ctx->roam.configParam.enable2x2) session->nss = 1; @@ -856,14 +842,9 @@ __lim_handle_sme_start_bss_request(tpAniSirGlobal mac_ctx, uint32_t *msg_buf) sme_start_bss_req->sec_ch_offset; session->htRecommendedTxWidthSet = (session->htSecondaryChannelOffset) ? 1 : 0; - QDF_TRACE(QDF_MODULE_ID_PE, QDF_TRACE_LEVEL_DEBUG, - FL("cbMode %u"), sme_start_bss_req->cbMode); if (lim_is_session_he_capable(session) || session->vhtCapability || session->htCapability) { chanwidth = sme_start_bss_req->vht_channel_width; - pe_debug("vht_channel_width %u htSupportedChannelWidthSet %d", - sme_start_bss_req->vht_channel_width, - session->htSupportedChannelWidthSet); session->ch_width = chanwidth; if (session->htSupportedChannelWidthSet) { session->ch_center_freq_seg0 = @@ -879,10 +860,7 @@ __lim_handle_sme_start_bss_request(tpAniSirGlobal mac_ctx, uint32_t *msg_buf) if (session->vhtCapability && (session->ch_width > CH_WIDTH_80MHZ)) { session->nss = 1; - pe_debug("nss set to [%d]", session->nss); } - pe_debug("vht su tx bformer %d", - session->vht_config.su_beam_former); /* Delete pre-auth list if any */ lim_delete_pre_auth_list(mac_ctx); @@ -1077,6 +1055,13 @@ __lim_handle_sme_start_bss_request(tpAniSirGlobal mac_ctx, uint32_t *msg_buf) session->limPrevSmeState = session->limSmeState; session->limSmeState = eLIM_SME_WT_START_BSS_STATE; + + pe_debug("Chan %d width %d freq0 %d freq1 %d, dot11mode %d nss %d vendor vht %d", + session->currentOperChannel, session->ch_width, + session->ch_center_freq_seg0, + session->ch_center_freq_seg1, + session->dot11mode, session->vdev_nss, + session->vendor_vht_sap); MTRACE(mac_trace (mac_ctx, TRACE_CODE_SME_STATE, session->peSessionId, @@ -1311,16 +1296,14 @@ __lim_process_sme_join_req(tpAniSirGlobal mac_ctx, uint32_t *msg_buf) */ session = pe_create_session(mac_ctx, bss_desc->bssId, &session_id, mac_ctx->lim.maxStation, - eSIR_INFRASTRUCTURE_MODE); - if (session == NULL) { + eSIR_INFRASTRUCTURE_MODE, + sme_join_req->sessionId, + sme_join_req->staPersona); + if (!session) { pe_err("Session Can not be created"); ret_code = eSIR_SME_RESOURCES_UNAVAILABLE; goto end; - } else { - pe_debug("SessionId:%d New session created", - session_id); } - /* Update the beacon/probe filter in mac_ctx */ lim_set_bcn_probe_filter(mac_ctx, session, &sme_join_req->ssId, @@ -1336,9 +1319,6 @@ __lim_process_sme_join_req(tpAniSirGlobal mac_ctx, uint32_t *msg_buf) /* store the smejoin req handle in session table */ session->pLimJoinReq = sme_join_req; - /* Store SME session Id in sessionTable */ - session->smeSessionId = sme_join_req->sessionId; - /* Store SME transaction Id in session Table */ session->transactionId = sme_join_req->transactionId; @@ -1356,7 +1336,6 @@ __lim_process_sme_join_req(tpAniSirGlobal mac_ctx, uint32_t *msg_buf) /* Copying of bssId is already done, while creating session */ sir_copy_mac_addr(session->selfMacAddr, sme_join_req->selfMacAddr); - session->bssType = sme_join_req->bsstype; session->statypeForBss = STA_ENTRY_PEER; session->limWmeEnabled = sme_join_req->isWMEenabled; @@ -1375,12 +1354,10 @@ __lim_process_sme_join_req(tpAniSirGlobal mac_ctx, uint32_t *msg_buf) SIR_MAC_CISCO_OUI, SIR_MAC_CISCO_OUI_SIZE, ((uint8_t *)&bss_desc->ieFields), ie_len); - if (NULL != vendor_ie) { - pe_debug("Cisco vendor OUI present"); + if (vendor_ie) session->isCiscoVendorAP = true; - } else { + else session->isCiscoVendorAP = false; - } /* Copy the dot 11 mode in to the session table */ @@ -1401,25 +1378,6 @@ __lim_process_sme_join_req(tpAniSirGlobal mac_ctx, uint32_t *msg_buf) * self and peer rates */ session->supported_nss_1x1 = true; - /*Store Persona */ - session->pePersona = sme_join_req->staPersona; - pe_debug("enable Smps: %d mode: %d send action: %d supported nss 1x1: %d pePersona %d cbMode %d", - session->enableHtSmps, - session->htSmpsvalue, - session->send_smps_action, - session->supported_nss_1x1, - session->pePersona, - sme_join_req->cbMode); - - /*Store Persona */ - session->pePersona = sme_join_req->staPersona; - QDF_TRACE(QDF_MODULE_ID_PE, QDF_TRACE_LEVEL_DEBUG, - FL("PE PERSONA=%d cbMode %u nwType: %d dot11mode: %d force_24ghz_in_ht20 %d"), - session->pePersona, sme_join_req->cbMode, - session->nwType, session->dot11mode, - sme_join_req->force_24ghz_in_ht20); - - /* Copy The channel Id to the session Table */ session->currentOperChannel = bss_desc->channelId; session->vhtCapability = @@ -1435,15 +1393,8 @@ __lim_process_sme_join_req(tpAniSirGlobal mac_ctx, uint32_t *msg_buf) sme_join_req->enableVhtpAid; session->enableVhtGid = sme_join_req->enableVhtGid; - pe_debug("vht su bformer [%d]", - session->vht_config.su_beam_former); } - pe_debug("vhtCapability: %d su_beam_formee: %d txbf_csn_value: %d su_tx_bformer %d", - session->vhtCapability, - session->vht_config.su_beam_formee, - session->vht_config.csnof_beamformer_antSup, - session->vht_config.su_beam_former); /*Phy mode */ session->gLimPhyMode = bss_desc->nwType; handle_ht_capabilityand_ht_info(mac_ctx, session); @@ -1503,6 +1454,9 @@ __lim_process_sme_join_req(tpAniSirGlobal mac_ctx, uint32_t *msg_buf) * to connect to, So input is coming from supplicant */ session->is11Rconnection = sme_join_req->is11Rconnection; + session->connected_akm = sme_join_req->akm; + session->is_adaptive_11r_connection = + sme_join_req->is_adaptive_11r_connection; #ifdef FEATURE_WLAN_ESE session->isESEconnection = sme_join_req->isESEconnection; #endif @@ -1514,7 +1468,7 @@ __lim_process_sme_join_req(tpAniSirGlobal mac_ctx, uint32_t *msg_buf) session->txLdpcIniFeatureEnabled = sme_join_req->txLdpcIniFeatureEnabled; - lim_update_fils_config(session, sme_join_req); + lim_update_fils_config(mac_ctx, session, sme_join_req); lim_update_sae_config(session, sme_join_req); if (session->bssType == eSIR_INFRASTRUCTURE_MODE) { session->limSystemRole = eLIM_STA_ROLE; @@ -1580,11 +1534,6 @@ __lim_process_sme_join_req(tpAniSirGlobal mac_ctx, uint32_t *msg_buf) session->nss = sme_join_req->nss; session->nss_forced_1x1 = sme_join_req->nss_forced_1x1; - pe_debug("nss %d, vdev_nss %d, supported_nss_1x1 %d", - session->nss, - session->vdev_nss, - session->supported_nss_1x1); - mlm_join_req->bssDescription.length = session->pLimJoinReq->bssDescription.length; @@ -1622,20 +1571,18 @@ __lim_process_sme_join_req(tpAniSirGlobal mac_ctx, uint32_t *msg_buf) &tx_pwr_attr); session->def_max_tx_pwr = session->maxTxPower; - pe_debug("Reg max %d local power con %d max tx pwr %d", - reg_max, local_power_constraint, session->maxTxPower); + pe_debug("Reg %d local %d session %d join req %d", + reg_max, local_power_constraint, session->maxTxPower, + sme_join_req->powerCap.maxTxPower); - if (sme_join_req->powerCap.maxTxPower > session->maxTxPower) { + if (sme_join_req->powerCap.maxTxPower > session->maxTxPower) sme_join_req->powerCap.maxTxPower = session->maxTxPower; - pe_debug("Update MaxTxPower in join Req to %d", - sme_join_req->powerCap.maxTxPower); - } if (session->gLimCurrentBssUapsd) { session->gUapsdPerAcBitmask = session->pLimJoinReq->uapsdPerAcBitmask; pe_debug("UAPSD flag for all AC - 0x%2x", - session->gUapsdPerAcBitmask); + session->gUapsdPerAcBitmask); /* resetting the dynamic uapsd mask */ session->gUapsdPerAcDeliveryEnableMask = 0; @@ -1682,6 +1629,18 @@ __lim_process_sme_join_req(tpAniSirGlobal mac_ctx, uint32_t *msg_buf) session->spectrumMgtEnabled = true; session->isOSENConnection = sme_join_req->isOSENConnection; + pe_debug("Chan %d width %d freq0 %d freq1 %d, Smps %d: mode %d action %d, nss 1x1 %d vdev_nss %d nss %d cbMode %d dot11mode %d subfer %d subfee %d csn %d is_cisco %d", + session->currentOperChannel, session->ch_width, + session->ch_center_freq_seg0, + session->ch_center_freq_seg1, + session->enableHtSmps, session->htSmpsvalue, + session->send_smps_action, session->supported_nss_1x1, + session->vdev_nss, session->nss, + sme_join_req->cbMode, session->dot11mode, + session->vht_config.su_beam_former, + session->vht_config.su_beam_formee, + session->vht_config.csnof_beamformer_antSup, + session->isCiscoVendorAP); /* Issue LIM_MLM_JOIN_REQ to MLM */ lim_post_mlm_message(mac_ctx, LIM_MLM_JOIN_REQ, @@ -2112,11 +2071,14 @@ static void __lim_process_sme_disassoc_req(tpAniSirGlobal pMac, uint32_t *pMsgBu disassocTrigger = eLIM_HOST_DISASSOC; goto sendDisassoc; } - pe_debug("received DISASSOC_REQ message on sessionid %d Systemrole %d Reason: %u SmeState: %d from: " - MAC_ADDRESS_STR, smesessionId, - GET_LIM_SYSTEM_ROLE(psessionEntry), smeDisassocReq.reasonCode, - pMac->lim.gLimSmeState, - MAC_ADDR_ARRAY(smeDisassocReq.peer_macaddr.bytes)); + pe_debug("vdev %d (session %d) Systemrole %d Reason: %u SmeState: %d limMlmState %d ho fail %d send OTA %d from: " + QDF_MAC_ADDR_STR, psessionEntry->smeSessionId, + psessionEntry->peSessionId, GET_LIM_SYSTEM_ROLE(psessionEntry), + smeDisassocReq.reasonCode, + psessionEntry->limSmeState, psessionEntry->limMlmState, + smeDisassocReq.process_ho_fail, + smeDisassocReq.doNotSendOverTheAir, + QDF_MAC_ADDR_ARRAY(smeDisassocReq.peer_macaddr.bytes)); #ifdef FEATURE_WLAN_DIAG_SUPPORT_LIM /* FEATURE_WLAN_DIAG_SUPPORT */ lim_diag_event_report(pMac, WLAN_PE_DIAG_DISASSOC_REQ_EVENT, psessionEntry, @@ -2127,7 +2089,6 @@ static void __lim_process_sme_disassoc_req(tpAniSirGlobal pMac, uint32_t *pMsgBu psessionEntry->smeSessionId = smesessionId; psessionEntry->transactionId = smetransactionId; - pe_debug("ho_fail: %d ", smeDisassocReq.process_ho_fail); psessionEntry->process_ho_fail = smeDisassocReq.process_ho_fail; switch (GET_LIM_SYSTEM_ROLE(psessionEntry)) { @@ -2135,8 +2096,6 @@ static void __lim_process_sme_disassoc_req(tpAniSirGlobal pMac, uint32_t *pMsgBu switch (psessionEntry->limSmeState) { case eLIM_SME_ASSOCIATED_STATE: case eLIM_SME_LINK_EST_STATE: - pe_debug("Rcvd SME_DISASSOC_REQ in limSmeState: %d ", - psessionEntry->limSmeState); psessionEntry->limPrevSmeState = psessionEntry->limSmeState; psessionEntry->limSmeState = eLIM_SME_WT_DISASSOC_STATE; @@ -2158,7 +2117,6 @@ static void __lim_process_sme_disassoc_req(tpAniSirGlobal pMac, uint32_t *pMsgBu (pMac, TRACE_CODE_SME_STATE, psessionEntry->peSessionId, psessionEntry->limSmeState)); - pe_debug("Rcvd SME_DISASSOC_REQ while in SME_WT_DEAUTH_STATE"); break; case eLIM_SME_WT_DISASSOC_STATE: @@ -2171,12 +2129,10 @@ static void __lim_process_sme_disassoc_req(tpAniSirGlobal pMac, uint32_t *pMsgBu * It will send a disassoc, which is ok. However, we can use the global flag * sendDisassoc to not send disassoc frame. */ - pe_debug("Rcvd SME_DISASSOC_REQ while in SME_WT_DISASSOC_STATE"); break; case eLIM_SME_JOIN_FAILURE_STATE: { /* Already in Disconnected State, return success */ - pe_debug("Rcvd SME_DISASSOC_REQ while in eLIM_SME_JOIN_FAILURE_STATE"); if (pMac->lim.gLimRspReqd) { retCode = eSIR_SME_SUCCESS; disassocTrigger = eLIM_HOST_DISASSOC; @@ -2227,14 +2183,8 @@ static void __lim_process_sme_disassoc_req(tpAniSirGlobal pMac, uint32_t *pMsgBu disassocTrigger = eLIM_HOST_DISASSOC; reasonCode = smeDisassocReq.reasonCode; - if (smeDisassocReq.doNotSendOverTheAir) { - pe_debug("do not send dissoc over the air"); + if (smeDisassocReq.doNotSendOverTheAir) send_disassoc_frame = 0; - } - /* Trigger Disassociation frame to peer MAC entity */ - pe_debug("Sending Disasscoc with disassoc Trigger" - " : %d, reasonCode : %d", - disassocTrigger, reasonCode); pMlmDisassocReq = qdf_mem_malloc(sizeof(tLimMlmDisassocReq)); if (NULL == pMlmDisassocReq) { @@ -2475,11 +2425,11 @@ static void __lim_process_sme_deauth_req(tpAniSirGlobal mac_ctx, deauth_trigger = eLIM_HOST_DEAUTH; goto send_deauth; } - pe_debug("received DEAUTH_REQ sessionid %d Systemrole %d reasoncode %u limSmestate %d from " - MAC_ADDRESS_STR, sme_session_id, - GET_LIM_SYSTEM_ROLE(session_entry), sme_deauth_req.reasonCode, - session_entry->limSmeState, - MAC_ADDR_ARRAY(sme_deauth_req.peer_macaddr.bytes)); + pe_debug("vdev %d (session %d) Systemrole %d reasoncode %u limSmestate %d limMlmState %d from " + QDF_MAC_ADDR_STR, sme_session_id, session_entry->peSessionId, + GET_LIM_SYSTEM_ROLE(session_entry), sme_deauth_req.reasonCode, + session_entry->limSmeState, session_entry->limMlmState, + QDF_MAC_ADDR_ARRAY(sme_deauth_req.peer_macaddr.bytes)); #ifdef FEATURE_WLAN_DIAG_SUPPORT_LIM /* FEATURE_WLAN_DIAG_SUPPORT */ lim_diag_event_report(mac_ctx, WLAN_PE_DIAG_DEAUTH_REQ_EVENT, session_entry, 0, sme_deauth_req.reasonCode); @@ -2520,7 +2470,6 @@ static void __lim_process_sme_deauth_req(tpAniSirGlobal mac_ctx, * was sent for deauth/disassoc frame. */ session_entry->limSmeState = eLIM_SME_WT_DEAUTH_STATE; - pe_debug("Rcvd SME_DEAUTH_REQ while in SME_WT_DEAUTH_STATE"); break; default: /* @@ -3766,7 +3715,6 @@ static void __lim_process_roam_scan_offload_req(tpAniSirGlobal mac_ctx, wma_msg.type = WMA_ROAM_SCAN_OFFLOAD_REQ; wma_msg.bodyptr = req_buffer; - status = wma_post_ctrl_msg(mac_ctx, &wma_msg); if (QDF_STATUS_SUCCESS != status) { pe_err("Posting WMA_ROAM_SCAN_OFFLOAD_REQ failed"); @@ -4154,9 +4102,9 @@ static void __lim_process_sme_register_mgmt_frame_req(tpAniSirGlobal mac_ctx, struct mgmt_frm_reg_info *next = NULL; bool match = false; - pe_debug("registerFrame %d, frameType %d, matchLen %d", - sme_req->registerFrame, sme_req->frameType, - sme_req->matchLen); + pe_nofl_debug("Register Frame: register %d, type %d, match length %d", + sme_req->registerFrame, sme_req->frameType, + sme_req->matchLen); /* First check whether entry exists already */ qdf_mutex_acquire(&mac_ctx->lim.lim_frame_register_lock); qdf_list_peek_front(&mac_ctx->lim.gLimMgmtFrameRegistratinQueue, @@ -4625,10 +4573,8 @@ bool lim_process_sme_req_messages(tpAniSirGlobal pMac, bool bufConsumed = true; /* Set this flag to false within case block of any following message, that doesn't want pMsgBuf to be freed. */ uint32_t *pMsgBuf = pMsg->bodyptr; - pe_debug("LIM Received SME Message %s(%d) Global LimSmeState:%s(%d) Global LimMlmState: %s(%d)", - lim_msg_str(pMsg->type), pMsg->type, - lim_sme_state_str(pMac->lim.gLimSmeState), pMac->lim.gLimSmeState, - lim_mlm_state_str(pMac->lim.gLimMlmState), pMac->lim.gLimMlmState); + pe_nofl_debug("LIM handle SME Msg %s(%d)", + lim_msg_str(pMsg->type), pMsg->type); /* If no insert NOA required then execute the code below */ @@ -4962,12 +4908,11 @@ static void lim_process_sme_channel_change_request(tpAniSirGlobal mac_ctx, session_entry->channelChangeReasonCode = LIM_SWITCH_CHANNEL_OPERATION; - pe_debug("switch old chnl %d to new chnl %d, ch_bw %d, nw_type %d, dot11mode %d", - session_entry->currentOperChannel, - ch_change_req->targetChannel, - ch_change_req->ch_width, - ch_change_req->nw_type, - ch_change_req->dot11mode); + pe_nofl_debug("SAP CSA: %d ---> %d, ch_bw %d, nw_type %d, dot11mode %d", + session_entry->currentOperChannel, + ch_change_req->targetChannel, + ch_change_req->ch_width, ch_change_req->nw_type, + ch_change_req->dot11mode); /* Store the New Channel Params in session_entry */ session_entry->ch_width = ch_change_req->ch_width; diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_tdls.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_tdls.c index d370cf15c78e..fa06e3b325f4 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_tdls.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_process_tdls.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -2658,20 +2658,11 @@ static QDF_STATUS lim_tdls_del_sta(tpAniSirGlobal pMac, pStaDs = dph_lookup_hash_entry(pMac, peerMac.bytes, &peerIdx, &psessionEntry->dph.dphHashTable); - if (pStaDs && pStaDs->staType == STA_ENTRY_TDLS_PEER) { - pe_debug("DEL STA peer MAC: "MAC_ADDRESS_STR, - MAC_ADDR_ARRAY(pStaDs->staAddr)); - - pe_debug("STA type: %x, sta idx: %x resp_reqd: %d", - pStaDs->staType, - pStaDs->staIndex, - resp_reqd); - + if (pStaDs && pStaDs->staType == STA_ENTRY_TDLS_PEER) status = lim_del_sta(pMac, pStaDs, resp_reqd, psessionEntry); - } else { + else pe_debug("TDLS peer "MAC_ADDRESS_STR" not found", MAC_ADDR_ARRAY(peerMac.bytes)); - } return status; } @@ -3135,7 +3126,6 @@ static void lim_check_aid_and_delete_peer(tpAniSirGlobal p_mac, * (with that aid) entry from the hash table and add the aid * in free pool */ - pe_debug("Delete all the TDLS peer connected"); for (i = 0; i < aid_bitmap_size / sizeof(uint32_t); i++) { for (aid = 0; aid < (sizeof(uint32_t) << 3); aid++) { if (!CHECK_BIT(session_entry->peerAIDBitmap[i], aid)) @@ -3161,9 +3151,6 @@ static void lim_check_aid_and_delete_peer(tpAniSirGlobal p_mac, status = lim_tdls_del_sta(p_mac, mac_addr, session_entry, false); - if (status != QDF_STATUS_SUCCESS) - pe_debug("peer " QDF_MAC_ADDR_STR " not found", - QDF_MAC_ADDR_ARRAY(stads->staAddr)); dph_delete_hash_entry(p_mac, stads->staAddr, stads->assocId, @@ -3195,7 +3182,6 @@ void lim_update_tdls_set_state_for_fw(tpPESession session_entry, bool value) QDF_STATUS lim_delete_tdls_peers(tpAniSirGlobal mac_ctx, tpPESession session_entry) { - pe_debug("Enter"); if (NULL == session_entry) { pe_err("NULL session_entry"); @@ -3222,7 +3208,6 @@ QDF_STATUS lim_delete_tdls_peers(tpAniSirGlobal mac_ctx, /* reset the set_state_disable flag */ session_entry->tdls_send_set_state_disable = true; - pe_debug("Exit"); return QDF_STATUS_SUCCESS; } @@ -3251,7 +3236,7 @@ QDF_STATUS lim_process_sme_del_all_tdls_peers(tpAniSirGlobal p_mac, session_entry = pe_find_session_by_bssid(p_mac, msg->bssid.bytes, &session_id); if (NULL == session_entry) { - pe_err("NULL psessionEntry"); + pe_debug("NULL psessionEntry"); return QDF_STATUS_E_FAILURE; } diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_prop_exts_utils.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_prop_exts_utils.c index ddd801fa08fa..3fe7d1d5415d 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_prop_exts_utils.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_prop_exts_utils.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -178,22 +178,45 @@ static void lim_objmgr_update_vdev_nss(struct wlan_objmgr_psoc *psoc, wlan_vdev_obj_unlock(vdev); wlan_objmgr_vdev_release_ref(vdev, WLAN_LEGACY_MAC_ID); } + +#ifdef WLAN_ADAPTIVE_11R /** - * lim_extract_ap_capability() - extract AP's HCF/WME/WSM capability - * @mac_ctx: Pointer to Global MAC structure - * @p_ie: Pointer to starting IE in Beacon/Probe Response - * @ie_len: Length of all IEs combined - * @qos_cap: Bits are set according to capabilities - * @prop_cap: Pointer to prop info IE. - * @uapsd: pointer to uapsd - * @local_constraint: Pointer to local power constraint. - * @session: A pointer to session entry. - * - * This function is called to extract AP's HCF/WME/WSM capability - * from the IEs received from it in Beacon/Probe Response frames + * lim_extract_adaptive_11r_cap() - check if the AP has adaptive 11r + * IE + * @ie: Pointer to the IE + * @ie_len: ie Length * - * Return: None + * Return: True if adaptive 11r IE is present */ +static bool lim_extract_adaptive_11r_cap(uint8_t *ie, uint16_t ie_len) +{ + const uint8_t *adaptive_ie; + uint8_t data; + bool adaptive_11r; + + adaptive_ie = wlan_get_vendor_ie_ptr_from_oui(LIM_ADAPTIVE_11R_OUI, + LIM_ADAPTIVE_11R_OUI_SIZE, + ie, ie_len); + if (!adaptive_ie) + return false; + + if (adaptive_ie[1] < (OUI_LENGTH + 1) || + adaptive_ie[1] > MAX_ADAPTIVE_11R_IE_LEN) + return false; + + data = *(adaptive_ie + OUI_LENGTH + 2); + adaptive_11r = (data & 0x1) ? true : false; + + return adaptive_11r; +} + +#else +static inline bool lim_extract_adaptive_11r_cap(uint8_t *ie, uint16_t ie_len) +{ + return false; +} +#endif + void lim_extract_ap_capability(tpAniSirGlobal mac_ctx, uint8_t *p_ie, uint16_t ie_len, uint8_t *qos_cap, uint16_t *prop_cap, uint8_t *uapsd, @@ -243,11 +266,6 @@ lim_extract_ap_capability(tpAniSirGlobal mac_ctx, uint8_t *p_ie, else mac_ctx->lim.htCapabilityPresentInBeacon = 0; - pe_debug("Bcon: VHTCap.present: %d SU Beamformer: %d BSS_VHT_CAPABLE: %d", - beacon_struct->VHTCaps.present, - beacon_struct->VHTCaps.suBeamFormerCap, - IS_BSS_VHT_CAPABLE(beacon_struct->VHTCaps)); - vht_op = &beacon_struct->VHTOperation; if (IS_BSS_VHT_CAPABLE(beacon_struct->VHTCaps) && vht_op->present && @@ -359,10 +377,6 @@ lim_extract_ap_capability(tpAniSirGlobal mac_ctx, uint8_t *p_ie, session->ch_center_freq_seg1 = 0; } session->ch_width = vht_ch_wd + 1; - pe_debug("cntr_freq0: %d cntr_freq1: %d width: %d", - session->ch_center_freq_seg0, - session->ch_center_freq_seg1, - session->ch_width); if (CH_WIDTH_80MHZ < session->ch_width) { session->vht_config.su_beam_former = 0; session->nss = 1; @@ -429,6 +443,9 @@ lim_extract_ap_capability(tpAniSirGlobal mac_ctx, uint8_t *p_ie, lim_objmgr_update_vdev_nss(mac_ctx->psoc, session->smeSessionId, session->nss); + + session->is_adaptive_11r_connection = + lim_extract_adaptive_11r_cap(p_ie, ie_len); qdf_mem_free(beacon_struct); return; } /****** end lim_extract_ap_capability() ******/ diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_prop_exts_utils.h b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_prop_exts_utils.h index 69026abda0dc..d08f009404f1 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_prop_exts_utils.h +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_prop_exts_utils.h @@ -43,9 +43,29 @@ void limCollectRSSI(tpAniSirGlobal); void limDeleteCurrentBssWdsNode(tpAniSirGlobal); uint32_t limComputeAvg(tpAniSirGlobal, uint32_t, uint32_t); -/* / Function to extract AP's HCF capability from IE fields */ -void lim_extract_ap_capability(tpAniSirGlobal, uint8_t *, uint16_t, uint8_t *, - uint16_t *, uint8_t *, int8_t *, tpPESession); +#define LIM_ADAPTIVE_11R_OUI "\x00\x40\x96\x2C" +#define LIM_ADAPTIVE_11R_OUI_SIZE 4 + +/** + * lim_extract_ap_capability() - extract AP's HCF/WME/WSM capability + * @mac_ctx: Pointer to Global MAC structure + * @p_ie: Pointer to starting IE in Beacon/Probe Response + * @ie_len: Length of all IEs combined + * @qos_cap: Bits are set according to capabilities + * @prop_cap: Pointer to prop info IE. + * @uapsd: pointer to uapsd + * @local_constraint: Pointer to local power constraint. + * @session: A pointer to session entry. + * + * This function is called to extract AP's HCF/WME/WSM capability + * from the IEs received from it in Beacon/Probe Response frames + * + * Return: None + */ +void lim_extract_ap_capability(tpAniSirGlobal mac_ctx, uint8_t *p_ie, + uint16_t ie_len, uint8_t *qos_cap, + uint16_t *prop_cap, uint8_t *uapsd, + int8_t *local_constraint, tpPESession session); ePhyChanBondState lim_get_htcb_state(ePhyChanBondState aniCBMode); diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_reassoc_utils.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_reassoc_utils.c index 236b9642279c..0cad0ea12694 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_reassoc_utils.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_reassoc_utils.c @@ -42,6 +42,7 @@ #include "lim_ibss_peer_mgmt.h" #include "lim_ft_defs.h" #include "lim_session.h" +#include "lim_process_fils.h" #include "qdf_types.h" #include "wma_types.h" @@ -398,6 +399,9 @@ QDF_STATUS lim_add_ft_sta_self(tpAniSirGlobal mac_ctx, uint16_t assoc_id, add_sta_params->assocId = assoc_id; add_sta_params->smesessionId = session_entry->smeSessionId; + if (lim_is_fils_connection(session_entry)) + add_sta_params->no_ptk_4_way = true; + msg_q.type = WMA_ADD_STA_REQ; msg_q.reserved = 0; msg_q.bodyptr = add_sta_params; diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_security_utils.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_security_utils.c index 5328fb7028e5..32e45eded167 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_security_utils.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_security_utils.c @@ -366,9 +366,8 @@ void lim_delete_pre_auth_node(tpAniSirGlobal pMac, tSirMacAddr macAddr) pMac->lim.pLimPreAuthList = pTempNode->next; - pe_debug("first node to delete, Release data entry: %pK id %d peer", - pTempNode, pTempNode->authNodeIdx); - lim_print_mac_addr(pMac, macAddr, LOGD); + pe_debug("fRelease data for %d peer %pM", + pTempNode->authNodeIdx, macAddr); lim_release_pre_auth_node(pMac, pTempNode); return; diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_send_management_frames.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_send_management_frames.c index 073aed08bd34..10a06dbd5f1a 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_send_management_frames.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_send_management_frames.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -57,6 +57,7 @@ #include #include "lim_process_fils.h" #include "wlan_utility.h" +#include /** * @@ -344,7 +345,6 @@ lim_send_probe_req_mgmt_frame(tpAniSirGlobal mac_ctx, if (IS_DOT11_MODE_HE(dot11mode) && NULL != pesession) lim_update_session_he_capable(mac_ctx, pesession); - pe_debug("Populate HE IEs"); populate_dot11f_he_caps(mac_ctx, pesession, &pr.he_cap); if (addn_ielen && additional_ie) { @@ -431,6 +431,10 @@ lim_send_probe_req_mgmt_frame(tpAniSirGlobal mac_ctx, additional_ie, addn_ielen); payload += addn_ielen; } + pe_nofl_debug("Probe req TX: vdev %d seq num %d to " QDF_MAC_ADDR_STR " len %d", + sme_sessionid, mac_ctx->mgmtSeqNum, + QDF_MAC_ADDR_ARRAY(bssid), + (int)sizeof(tSirMacMgmtHdr) + payload); /* If this probe request is sent during P2P Search State, then we need * to send it at OFDM rate. @@ -1402,14 +1406,9 @@ lim_send_assoc_rsp_mgmt_frame(tpAniSirGlobal mac_ctx, status); } - if (subtype == LIM_ASSOC) - pe_debug("*** Sending Assoc Resp status %d aid %d to", - status_code, aid); - else - pe_debug("*** Sending ReAssoc Resp status %d aid %d to", - status_code, aid); - - lim_print_mac_addr(mac_ctx, mac_hdr->da, LOGD); + pe_nofl_debug("Assoc rsp TX: vdev %d subtype %d to %pM seq num %d status %d aid %d", + pe_session->smeSessionId, subtype, mac_hdr->da, + mac_ctx->mgmtSeqNum, status_code, aid); if (addn_ie_len && addn_ie_len <= WNI_CFG_ASSOC_RSP_ADDNIE_DATA_LEN) qdf_mem_copy(frame + sizeof(tSirMacMgmtHdr) + payload, @@ -1608,7 +1607,10 @@ static QDF_STATUS lim_assoc_tx_complete_cnf(void *context, uint16_t reason_code; tpAniSirGlobal mac_ctx = (tpAniSirGlobal)context; - pe_debug("tx_complete= %d", tx_complete); + pe_nofl_info("Assoc req TX %s", + (tx_complete == WMI_MGMT_TX_COMP_TYPE_COMPLETE_OK) ? + "success" : "fail"); + if (tx_complete == WMI_MGMT_TX_COMP_TYPE_COMPLETE_OK) { assoc_ack_status = ACKED; reason_code = QDF_STATUS_SUCCESS; @@ -1624,6 +1626,86 @@ static QDF_STATUS lim_assoc_tx_complete_cnf(void *context, return QDF_STATUS_SUCCESS; } +#ifdef WLAN_ADAPTIVE_11R +/** + * lim_fill_adaptive_11r_ie() - Populate the Vendor secific adaptive 11r + * IE to association request frame + * @pe_session: pointer to PE session + * @ie_buf: buffer to which Adaptive 11r IE will be copied + * @ie_len: length of the Adaptive 11r Vendor specific IE + * + * Return QDF_STATUS + */ +static QDF_STATUS lim_fill_adaptive_11r_ie(tpPESession pe_session, + uint8_t **ie_buf, uint8_t *ie_len) +{ + uint8_t *buf = NULL, *adaptive_11r_ie = NULL; + + if (!pe_session->is_adaptive_11r_connection) + return QDF_STATUS_SUCCESS; + + /* + * Vendor specific Adaptive 11r IE to be advertised in Assoc + * req: + * Type 0xDD + * Length 0x0B + * OUI 0x00 0x00 0x0F + * Type 0x22 + * subtype 0x00 + * Version 0x01 + * Length 0x04 + * Data 0x00 00 00 01(0th bit is 1 means adaptive 11r is + * supported) + */ + adaptive_11r_ie = qdf_mem_malloc(ADAPTIVE_11R_STA_IE_LEN + 2); + if (!adaptive_11r_ie) + return QDF_STATUS_E_FAILURE; + + /* Fill the Vendor IE Type (0xDD) */ + buf = adaptive_11r_ie; + *buf = IE_EID_VENDOR; + buf++; + + /* Fill the Vendor IE length (0x0B) */ + *buf = ADAPTIVE_11R_STA_IE_LEN; + buf++; + + /* + * Fill the Adaptive 11r Vendor specific OUI(0x00 0x00 0x0F 0x22) + */ + qdf_mem_copy(buf, ADAPTIVE_11R_STA_OUI, ADAPTIVE_11R_OUI_LEN); + buf += ADAPTIVE_11R_OUI_LEN; + + /* Fill Adaptive 11r Vendor specific Subtype (0x00) */ + *buf = ADAPTIVE_11R_OUI_SUBTYPE; + buf++; + + /* Fill Adaptive 11r Version (0x01) */ + *buf = ADAPTIVE_11R_OUI_VERSION; + buf++; + + /* Fill Adaptive 11r IE Data length (0x04) */ + *buf = ADAPTIVE_11R_DATA_LEN; + buf++; + + /* Fill Adaptive 11r IE Data (0x00 0x00 0x00 0x01) */ + qdf_mem_copy(buf, ADAPTIVE_11R_OUI_DATA, ADAPTIVE_11R_DATA_LEN); + + *ie_len = ADAPTIVE_11R_STA_IE_LEN + 2; + *ie_buf = adaptive_11r_ie; + + return QDF_STATUS_SUCCESS; +} + +#else +static inline +QDF_STATUS lim_fill_adaptive_11r_ie(tpPESession pe_session, + uint8_t **ie_buf, uint8_t *ie_len) +{ + return QDF_STATUS_SUCCESS; +} +#endif + /** * lim_send_assoc_req_mgmt_frame() - Send association request * @mac_ctx: Handle to MAC context @@ -1649,7 +1731,7 @@ lim_send_assoc_req_mgmt_frame(tpAniSirGlobal mac_ctx, uint8_t qos_enabled, wme_enabled, wsm_enabled; void *packet; QDF_STATUS qdf_status; - uint16_t add_ie_len; + uint16_t add_ie_len, current_len = 0, vendor_ie_len = 0; uint8_t *add_ie; const uint8_t *wps_ie = NULL; uint8_t power_caps = false; @@ -1666,8 +1748,8 @@ lim_send_assoc_req_mgmt_frame(tpAniSirGlobal mac_ctx, uint32_t bcn_ie_len = 0; uint32_t aes_block_size_len = 0; enum rateid min_rid = RATEID_DEFAULT; - uint8_t *mbo_ie = NULL; - uint8_t mbo_ie_len = 0; + uint8_t *mbo_ie = NULL, *vendor_ies = NULL, *adaptive_11r_ie = NULL; + uint8_t mbo_ie_len = 0, adaptive_11r_ie_len = 0; if (NULL == pe_session) { pe_err("pe_session is NULL"); @@ -1832,26 +1914,15 @@ lim_send_assoc_req_mgmt_frame(tpAniSirGlobal mac_ctx, mac_ctx->lim.htCapabilityPresentInBeacon) { pe_debug("Populate HT Caps in Assoc Request"); populate_dot11f_ht_caps(mac_ctx, pe_session, &frm->HTCaps); - QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_PE, QDF_TRACE_LEVEL_DEBUG, - &frm->HTCaps, sizeof(frm->HTCaps)); } else if (pe_session->he_with_wep_tkip) { pe_debug("Populate HT Caps in Assoc Request with WEP/TKIP"); populate_dot11f_ht_caps(mac_ctx, NULL, &frm->HTCaps); } - pe_debug("SupportedChnlWidth: %d, mimoPS: %d, GF: %d, short GI20:%d, shortGI40: %d, dsssCck: %d, AMPDU Param: %x", - frm->HTCaps.supportedChannelWidthSet, - frm->HTCaps.mimoPowerSave, - frm->HTCaps.greenField, frm->HTCaps.shortGI20MHz, - frm->HTCaps.shortGI40MHz, - frm->HTCaps.dsssCckMode40MHz, - frm->HTCaps.maxRxAMPDUFactor); if (pe_session->vhtCapability && pe_session->vhtCapabilityPresentInBeacon) { pe_debug("Populate VHT IEs in Assoc Request"); populate_dot11f_vht_caps(mac_ctx, pe_session, &frm->VHTCaps); - QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_PE, QDF_TRACE_LEVEL_DEBUG, - &frm->VHTCaps, sizeof(frm->VHTCaps)); vht_enabled = true; if (pe_session->enableHtSmps && !pe_session->supported_nss_1x1) { @@ -1906,9 +1977,17 @@ lim_send_assoc_req_mgmt_frame(tpAniSirGlobal mac_ctx, (unsigned int) bssdescr->mdie[2]); populate_mdie(mac_ctx, &frm->MobilityDomain, pe_session->pLimJoinReq->bssDescription.mdie); - } else { - /* No 11r IEs dont send any MDIE */ - pe_debug("MDIE not present"); + + /* + * IEEE80211-ai [13.2.4 FT initial mobility domain association + * over FILS in an RSN] + * Populate FT IE in association request. This FT IE should be + * same as the FT IE received in auth response frame during the + * FT-FILS authentication. + */ + if (lim_is_fils_connection(pe_session)) + populate_fils_ft_info(mac_ctx, &frm->FTInfo, + pe_session); } #ifdef FEATURE_WLAN_ESE @@ -1998,7 +2077,7 @@ lim_send_assoc_req_mgmt_frame(tpAniSirGlobal mac_ctx, mbo_ie, DOT11F_IE_MBO_IE_MAX_LEN); if (QDF_IS_STATUS_ERROR(qdf_status)) { pe_err("Failed to strip MBO IE"); - goto free_mbo_ie; + goto end; } /* Include the EID and length fields */ @@ -2006,6 +2085,39 @@ lim_send_assoc_req_mgmt_frame(tpAniSirGlobal mac_ctx, pe_debug("Stripped MBO IE of length %d", mbo_ie_len); } + qdf_status = lim_fill_adaptive_11r_ie(pe_session, &adaptive_11r_ie, + &adaptive_11r_ie_len); + if (QDF_IS_STATUS_ERROR(qdf_status)) { + pe_err("Failed to fill adaptive 11r IE"); + goto end; + } + + /* + * Strip rest of the vendor IEs and append to the assoc request frame. + * Append the IEs just before MBO IEs as MBO IEs have to be at the + * end of the frame. + */ + if (wlan_get_ie_ptr_from_eid(WLAN_ELEMID_VENDOR, add_ie, add_ie_len)) { + vendor_ies = qdf_mem_malloc(MAX_VENDOR_IES_LEN + 2); + if (vendor_ies) { + current_len = add_ie_len; + qdf_status = lim_strip_ie(mac_ctx, add_ie, &add_ie_len, + WLAN_ELEMID_VENDOR, ONE_BYTE, + NULL, + 0, + vendor_ies, + MAX_VENDOR_IES_LEN); + if (QDF_IS_STATUS_ERROR(qdf_status)) { + pe_err("Failed to strip Vendor IEs"); + goto end; + } + + vendor_ie_len = current_len - add_ie_len; + pe_debug("Stripped vendor IEs of size: %u", + current_len); + } + } + /* * Do unpack to populate the add_ie buffer to frm structure * before packing the frm structure. In this way, the IE ordering @@ -2032,7 +2144,7 @@ lim_send_assoc_req_mgmt_frame(tpAniSirGlobal mac_ctx, } bytes = payload + sizeof(tSirMacMgmtHdr) + - aes_block_size_len + mbo_ie_len; + aes_block_size_len + mbo_ie_len + vendor_ie_len + adaptive_11r_ie_len; qdf_status = cds_packet_alloc((uint16_t) bytes, (void **)&frame, (void **)&packet); @@ -2072,12 +2184,25 @@ lim_send_assoc_req_mgmt_frame(tpAniSirGlobal mac_ctx, pe_warn("Assoc request pack warning (0x%08x)", status); } + /* Copy the vendor IEs to the end of the frame */ + qdf_mem_copy(frame + sizeof(tSirMacMgmtHdr) + payload, + vendor_ies, vendor_ie_len); + payload = payload + vendor_ie_len; + /* Copy the MBO IE to the end of the frame */ qdf_mem_copy(frame + sizeof(tSirMacMgmtHdr) + payload, mbo_ie, mbo_ie_len); payload = payload + mbo_ie_len; - if (pe_session->assocReq != NULL) { + /* + * Copy the Vendor specific Adaptive 11r IE to end of the + * assoc request frame + */ + qdf_mem_copy(frame + sizeof(tSirMacMgmtHdr) + payload, + adaptive_11r_ie, adaptive_11r_ie_len); + payload = payload + adaptive_11r_ie_len; + + if (pe_session->assocReq) { qdf_mem_free(pe_session->assocReq); pe_session->assocReq = NULL; pe_session->assocReqLen = 0; @@ -2088,8 +2213,7 @@ lim_send_assoc_req_mgmt_frame(tpAniSirGlobal mac_ctx, frame, &payload); if (!QDF_IS_STATUS_SUCCESS(qdf_status)) { cds_packet_free((void *)packet); - qdf_mem_free(frm); - return; + goto end; } } @@ -2120,7 +2244,12 @@ lim_send_assoc_req_mgmt_frame(tpAniSirGlobal mac_ctx, MTRACE(qdf_trace(QDF_MODULE_ID_PE, TRACE_CODE_TX_MGMT, pe_session->peSessionId, mac_hdr->fc.subType)); - pe_debug("Sending Association Request length %d to ", bytes); + pe_nofl_info("Assoc req TX: vdev %d to %pM seq num %d", + pe_session->smeSessionId, + pe_session->bssId, mac_ctx->mgmtSeqNum); + QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_PE, QDF_TRACE_LEVEL_DEBUG, + frame, (uint16_t)(sizeof(tSirMacMgmtHdr) + payload)); + min_rid = lim_get_min_session_txrate(pe_session); lim_diag_event_report(mac_ctx, WLAN_PE_DIAG_ASSOC_START_EVENT, pe_session, QDF_STATUS_SUCCESS, QDF_STATUS_SUCCESS); @@ -2143,12 +2272,13 @@ lim_send_assoc_req_mgmt_frame(tpAniSirGlobal mac_ctx, pe_session, SENT_FAIL, QDF_STATUS_E_FAILURE); /* Pkt will be freed up by the callback */ } -free_mbo_ie: - if (mbo_ie) - qdf_mem_free(mbo_ie); end: + qdf_mem_free(vendor_ies); + qdf_mem_free(mbo_ie); + /* Free up buffer allocated for mlm_assoc_req */ + qdf_mem_free(adaptive_11r_ie); qdf_mem_free(mlm_assoc_req); mlm_assoc_req = NULL; qdf_mem_free(frm); @@ -2174,9 +2304,9 @@ static QDF_STATUS lim_auth_tx_complete_cnf(void *context, uint16_t auth_ack_status; uint16_t reason_code; - pe_debug("tx_complete = %d %s", tx_complete, - (tx_complete == WMI_MGMT_TX_COMP_TYPE_COMPLETE_OK) ? - "success" : "fail"); + pe_nofl_info("Auth TX: %s", + (tx_complete == WMI_MGMT_TX_COMP_TYPE_COMPLETE_OK) ? + "success" : "fail"); if (tx_complete == WMI_MGMT_TX_COMP_TYPE_COMPLETE_OK) { mac_ctx->auth_ack_status = LIM_AUTH_ACK_RCD_SUCCESS; auth_ack_status = ACKED; @@ -2247,22 +2377,12 @@ lim_send_auth_mgmt_frame(tpAniSirGlobal mac_ctx, * status code, 128 bytes for challenge text and * 4 bytes each for IV & ICV. */ - pe_debug("Sending encrypted auth frame to " MAC_ADDRESS_STR, - MAC_ADDR_ARRAY(peer_addr)); - body_len = wep_challenge_len + LIM_ENCR_AUTH_INFO_LEN; frame_len = sizeof(tSirMacMgmtHdr) + body_len; goto alloc_packet; } - pe_debug("Sending Auth seq# %d status %d (%d) to " - MAC_ADDRESS_STR, - auth_frame->authTransactionSeqNumber, - auth_frame->authStatusCode, - (auth_frame->authStatusCode == eSIR_MAC_SUCCESS_STATUS), - MAC_ADDR_ARRAY(peer_addr)); - switch (auth_frame->authTransactionSeqNumber) { case SIR_MAC_AUTH_FRAME_1: /* @@ -2291,6 +2411,13 @@ lim_send_auth_mgmt_frame(tpAniSirGlobal mac_ctx, frame_len += (2 + SIR_MDIE_SIZE); } } + + /* include MDIE in FILS authentication frame */ + if (session->pLimJoinReq && + session->pLimJoinReq->is11Rconnection && + auth_frame->authAlgoNumber == SIR_FILS_SK_WITHOUT_PFS && + session->pLimJoinReq->bssDescription.mdiePresent) + frame_len += (2 + SIR_MDIE_SIZE); break; case SIR_MAC_AUTH_FRAME_2: @@ -2389,10 +2516,6 @@ lim_send_auth_mgmt_frame(tpAniSirGlobal mac_ctx, if (wep_challenge_len) { qdf_mem_copy(body, (uint8_t *) auth_frame, body_len); - - pe_debug("Sending Auth seq# 3 to " MAC_ADDRESS_STR, - MAC_ADDR_ARRAY(mac_hdr->da)); - } else { *((uint16_t *) (body)) = sir_swap_u16if_needed(auth_frame->authAlgoNumber); @@ -2435,9 +2558,8 @@ lim_send_auth_mgmt_frame(tpAniSirGlobal mac_ctx, qdf_mem_copy(body, auth_frame->challengeText, SIR_MAC_SAP_AUTH_CHALLENGE_LENGTH); body += SIR_MAC_SAP_AUTH_CHALLENGE_LENGTH; - body_len -= SIR_MAC_SAP_AUTH_CHALLENGE_LENGTH + - SIR_MAC_CHALLENGE_ID_LEN; + SIR_MAC_CHALLENGE_ID_LEN; } } @@ -2468,23 +2590,20 @@ lim_send_auth_mgmt_frame(tpAniSirGlobal mac_ctx, pbssDescription->mdie[0], SIR_MDIE_SIZE); } - } else if (auth_frame->authAlgoNumber == - SIR_FILS_SK_WITHOUT_PFS) { - /* TODO MDIE */ - pe_debug("appending fils Auth data"); + } else if ((auth_frame->authAlgoNumber == + SIR_FILS_SK_WITHOUT_PFS) && + (auth_frame->authTransactionSeqNumber == + SIR_MAC_AUTH_FRAME_1)) { + pe_debug("FILS: appending fils Auth data"); lim_add_fils_data_to_auth_frame(session, body); } - - pe_debug("*** Sending Auth seq# %d status %d (%d) to " - MAC_ADDRESS_STR, - auth_frame->authTransactionSeqNumber, - auth_frame->authStatusCode, - (auth_frame->authStatusCode == - eSIR_MAC_SUCCESS_STATUS), - MAC_ADDR_ARRAY(mac_hdr->da)); } - QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_PE, - QDF_TRACE_LEVEL_DEBUG, + + pe_nofl_info("Auth TX: seq %d seq num %d status %d WEP %d to " QDF_MAC_ADDR_STR, + auth_frame->authTransactionSeqNumber, mac_ctx->mgmtSeqNum, + auth_frame->authStatusCode, mac_hdr->fc.wep, + QDF_MAC_ADDR_ARRAY(mac_hdr->da)); + QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_PE, QDF_TRACE_LEVEL_DEBUG, frame, frame_len); if ((NULL != session->ftPEContext.pFTPreAuthReq) && @@ -2758,7 +2877,9 @@ static QDF_STATUS lim_deauth_tx_complete_cnf_handler(void *context, QDF_STATUS status_code; struct scheduler_msg msg = {0}; - pe_debug("tx_success: %d", tx_success); + pe_info("tx_complete = %s tx_success = %d", + (tx_success == WMI_MGMT_TX_COMP_TYPE_COMPLETE_OK) ? + "success" : "fail", tx_success); if (buf) qdf_nbuf_free(buf); @@ -2773,6 +2894,30 @@ static QDF_STATUS lim_deauth_tx_complete_cnf_handler(void *context, return status_code; } +/** + * lim_append_ies_to_frame() - Append IEs to the frame + * + * @frame: Pointer to the frame buffer that needs to be populated + * @frame_len: Pointer for current frame length + * @ie: pointer for disconnect IEs + * + * This function is called by lim_send_disassoc_mgmt_frame and + * lim_send_deauth_mgmt_frame APIs as part of disconnection. + * Append IEs and update frame length. + * + * Return: None + */ +static void +lim_append_ies_to_frame(uint8_t *frame, uint32_t *frame_len, + struct wlan_ies *ie) +{ + if (!ie || !ie->len || !ie->data) + return; + qdf_mem_copy(frame, ie->data, ie->len); + *frame_len += ie->len; + pe_debug("Appended IEs len: %u", ie->len); +} + /** * \brief This function is called to send Disassociate frame. * @@ -2803,6 +2948,7 @@ lim_send_disassoc_mgmt_frame(tpAniSirGlobal pMac, uint8_t txFlag = 0; uint32_t val = 0; uint8_t smeSessionId = 0; + struct wlan_ies *discon_ie; if (NULL == psessionEntry) { return; @@ -2839,6 +2985,10 @@ lim_send_disassoc_mgmt_frame(tpAniSirGlobal pMac, nBytes = nPayload + sizeof(tSirMacMgmtHdr); + discon_ie = hdd_get_self_disconnect_ies(pMac, smeSessionId); + if (discon_ie && discon_ie->len) + nBytes += discon_ie->len; + qdf_status = cds_packet_alloc((uint16_t) nBytes, (void **)&pFrame, (void **)&pPacket); if (!QDF_IS_STATUS_SUCCESS(qdf_status)) { @@ -2874,11 +3024,15 @@ lim_send_disassoc_mgmt_frame(tpAniSirGlobal pMac, nStatus); } - pe_debug("***Sessionid %d Sending Disassociation frame with " - "reason %u and waitForAck %d to " MAC_ADDRESS_STR " ,From " - MAC_ADDRESS_STR, psessionEntry->peSessionId, nReason, - waitForAck, MAC_ADDR_ARRAY(pMacHdr->da), - MAC_ADDR_ARRAY(psessionEntry->selfMacAddr)); + /* Copy disconnect IEs to the end of the frame */ + lim_append_ies_to_frame(pFrame + sizeof(tSirMacMgmtHdr) + nPayload, + &nPayload, discon_ie); + hdd_free_self_disconnect_ies(pMac, smeSessionId); + + pe_nofl_info("Disassoc TX: vdev %d seq %d reason %u and waitForAck %d to " QDF_MAC_ADDR_STR " From " QDF_MAC_ADDR_STR, + psessionEntry->smeSessionId, pMac->mgmtSeqNum, nReason, + waitForAck, QDF_MAC_ADDR_ARRAY(pMacHdr->da), + QDF_MAC_ADDR_ARRAY(psessionEntry->selfMacAddr)); if ((BAND_5G == lim_get_rf_band(psessionEntry->currentOperChannel)) || (psessionEntry->pePersona == QDF_P2P_CLIENT_MODE) || @@ -2982,6 +3136,7 @@ lim_send_deauth_mgmt_frame(tpAniSirGlobal pMac, tpDphHashNode pStaDs; #endif uint8_t smeSessionId = 0; + struct wlan_ies *discon_ie; if (NULL == psessionEntry) { return; @@ -3017,6 +3172,9 @@ lim_send_deauth_mgmt_frame(tpAniSirGlobal pMac, } nBytes = nPayload + sizeof(tSirMacMgmtHdr); + discon_ie = hdd_get_self_disconnect_ies(pMac, smeSessionId); + if (discon_ie && discon_ie->len) + nBytes += discon_ie->len; qdf_status = cds_packet_alloc((uint16_t) nBytes, (void **)&pFrame, (void **)&pPacket); @@ -3051,19 +3209,23 @@ lim_send_deauth_mgmt_frame(tpAniSirGlobal pMac, pe_warn("There were warnings while packing a De-Authentication (0x%08x)", nStatus); } - pe_debug("***Sessionid %d Sending Deauth frame with " - "reason %u and waitForAck %d to " MAC_ADDRESS_STR - " ,From " MAC_ADDRESS_STR, - psessionEntry->peSessionId, nReason, waitForAck, - MAC_ADDR_ARRAY(pMacHdr->da), - MAC_ADDR_ARRAY(psessionEntry->selfMacAddr)); + + /* Copy disconnect IEs to the end of the frame */ + lim_append_ies_to_frame(pFrame + sizeof(tSirMacMgmtHdr) + nPayload, + &nPayload, discon_ie); + hdd_free_self_disconnect_ies(pMac, smeSessionId); + + pe_nofl_info("Deauth TX: vdev %d seq_num %d reason %u waitForAck %d to " QDF_MAC_ADDR_STR " from " QDF_MAC_ADDR_STR, + psessionEntry->smeSessionId, pMac->mgmtSeqNum, nReason, + waitForAck, + QDF_MAC_ADDR_ARRAY(pMacHdr->da), + QDF_MAC_ADDR_ARRAY(psessionEntry->selfMacAddr)); if ((BAND_5G == lim_get_rf_band(psessionEntry->currentOperChannel)) || (psessionEntry->pePersona == QDF_P2P_CLIENT_MODE) || (psessionEntry->pePersona == QDF_P2P_GO_MODE) - ) { + ) txFlag |= HAL_USE_BD_RATE2_FOR_MANAGEMENT_FRAME; - } txFlag |= HAL_USE_PEER_STA_REQUESTED_MASK; #ifdef FEATURE_WLAN_TDLS @@ -3672,7 +3834,6 @@ lim_send_extended_chan_switch_action_frame(tpAniSirGlobal mac_ctx, ch_spacing = wlan_reg_dmn_get_chanwidth_from_opclass( mac_ctx->scan.countryCodeCurrent, new_channel, new_op_class); - pe_debug("wrapper: ch_spacing %hu", ch_spacing); if ((ch_spacing == 80) || (ch_spacing == 160)) { wide_bw_ie = &session_entry->gLimWiderBWChannelSwitch; @@ -3743,12 +3904,12 @@ lim_send_extended_chan_switch_action_frame(tpAniSirGlobal mac_ctx, txFlag |= HAL_USE_BD_RATE2_FOR_MANAGEMENT_FRAME; } - pe_debug("Send Ext channel Switch to :"MAC_ADDRESS_STR" with swcount %d, swmode %d , newchannel %d newops %d", - MAC_ADDR_ARRAY(mac_hdr->da), - frm.ext_chan_switch_ann_action.switch_count, - frm.ext_chan_switch_ann_action.switch_mode, - frm.ext_chan_switch_ann_action.new_channel, - frm.ext_chan_switch_ann_action.op_class); + pe_debug("ECSA frame to :" QDF_MAC_ADDR_STR " count %d mode %d chan %d op class %d", + QDF_MAC_ADDR_ARRAY(mac_hdr->da), + frm.ext_chan_switch_ann_action.switch_count, + frm.ext_chan_switch_ann_action.switch_mode, + frm.ext_chan_switch_ann_action.new_channel, + frm.ext_chan_switch_ann_action.op_class); MTRACE(qdf_trace(QDF_MODULE_ID_PE, TRACE_CODE_TX_MGMT, session_entry->peSessionId, mac_hdr->fc.subType)); @@ -4319,7 +4480,7 @@ lim_send_radio_measure_report_action_frame(tpAniSirGlobal pMac, tSirMacAddr peer, tpPESession psessionEntry) { - QDF_STATUS statusCode = QDF_STATUS_SUCCESS; + QDF_STATUS status_code = QDF_STATUS_SUCCESS; uint8_t *pFrame; tpSirMacMgmtHdr pMacHdr; uint32_t nBytes, nPayload, nStatus; @@ -4337,15 +4498,13 @@ lim_send_radio_measure_report_action_frame(tpAniSirGlobal pMac, } if (psessionEntry == NULL) { - pe_err("(psession == NULL) in Request to send Beacon Report action frame"); + pe_err("(session not found"); qdf_mem_free(frm); return QDF_STATUS_E_FAILURE; } smeSessionId = psessionEntry->smeSessionId; - pe_debug("dialog_token %d num_report %d is_last_frame %d", - dialog_token, num_report, is_last_frame); frm->Category.category = SIR_MAC_ACTION_RRM; frm->Action.action = SIR_MAC_RRM_RADIO_MEASURE_RPT; @@ -4383,17 +4542,18 @@ lim_send_radio_measure_report_action_frame(tpAniSirGlobal pMac, } } + nStatus = dot11f_get_packed_radio_measurement_report_size(pMac, frm, &nPayload); if (DOT11F_FAILED(nStatus)) { - pe_err("Failed to calculate the packed size for a Radio Measure Report (0x%08x)", - nStatus); + pe_nofl_err("TX: [802.11 RRM] Failed to get packed size for RM Report (0x%08x)", + nStatus); /* We'll fall back on the worst case scenario: */ nPayload = sizeof(tDot11fLinkMeasurementReport); qdf_mem_free(frm); return QDF_STATUS_E_FAILURE; } else if (DOT11F_WARNED(nStatus)) { - pe_warn("There were warnings while calculating the packed size for a Radio Measure Report (0x%08x)", + pe_warn("Warnings while calculating the size for Radio Measure Report (0x%08x)", nStatus); } @@ -4403,7 +4563,7 @@ lim_send_radio_measure_report_action_frame(tpAniSirGlobal pMac, cds_packet_alloc((uint16_t) nBytes, (void **)&pFrame, (void **)&pPacket); if (!QDF_IS_STATUS_SUCCESS(qdf_status)) { - pe_err("Failed to allocate %d bytes for a Radio Measure " + pe_nofl_err("TX: [802.11 RRM] Allocation of %d bytes failed for RM" "Report", nBytes); qdf_mem_free(frm); return QDF_STATUS_E_FAILURE; @@ -4432,19 +4592,26 @@ lim_send_radio_measure_report_action_frame(tpAniSirGlobal pMac, nPayload, &nPayload); if (DOT11F_FAILED(nStatus)) { - pe_err("Failed to pack an Radio Measure Report (0x%08x)", + pe_nofl_err("Failed to pack an Radio Measure Report (0x%08x)", nStatus); /* FIXME - Need to convert to QDF_STATUS */ - statusCode = QDF_STATUS_E_FAILURE; + status_code = QDF_STATUS_E_FAILURE; goto returnAfterError; } else if (DOT11F_WARNED(nStatus)) { - pe_warn("There were warnings while packing Radio Measure Report (0x%08x)", + pe_warn("Warnings while packing Radio Measure Report (0x%08x)", nStatus); } - pe_warn("Sending a Radio Measure Report to"); - lim_print_mac_addr(pMac, peer, LOGW); + pe_debug("Sending Radio Measure Report to %pM", peer); + if (frm->MeasurementReport[0].type == SIR_MAC_RRM_BEACON_TYPE) + pe_nofl_info("TX: %s seq_no:%d dialog_token:%d no. of APs:%d is_last_rpt:%d num_report %d", + frm->MeasurementReport[0].type == SIR_MAC_RRM_BEACON_TYPE ? + "[802.11 BCN_RPT]" : "[802.11 RRM]", + (pMacHdr->seqControl.seqNumHi << HIGH_SEQ_NUM_OFFSET | + pMacHdr->seqControl.seqNumLo), + dialog_token, frm->num_MeasurementReport, + is_last_frame, num_report); if ((BAND_5G == lim_get_rf_band(psessionEntry->currentOperChannel)) || (psessionEntry->pePersona == QDF_P2P_CLIENT_MODE) || @@ -4465,20 +4632,19 @@ lim_send_radio_measure_report_action_frame(tpAniSirGlobal pMac, MTRACE(qdf_trace(QDF_MODULE_ID_PE, TRACE_CODE_TX_COMPLETE, psessionEntry->peSessionId, qdf_status)); if (QDF_STATUS_SUCCESS != qdf_status) { - pe_err("wma_tx_frame FAILED! Status [%d]", qdf_status); - statusCode = QDF_STATUS_E_FAILURE; + pe_nofl_err("TX: [802.11 RRM] Send FAILED! err_status [%d]", + qdf_status); + status_code = QDF_STATUS_E_FAILURE; /* Pkt will be freed up by the callback */ - qdf_mem_free(frm); - return statusCode; - } else { - qdf_mem_free(frm); - return QDF_STATUS_SUCCESS; } + qdf_mem_free(frm); + return status_code; + returnAfterError: qdf_mem_free(frm); cds_packet_free((void *)pPacket); - return statusCode; + return status_code; } #ifdef WLAN_FEATURE_11W diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_send_messages.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_send_messages.c index 903f22c576b3..290423e8f217 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_send_messages.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_send_messages.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -205,9 +205,6 @@ QDF_STATUS lim_send_switch_chnl_params(tpAniSirGlobal pMac, lim_update_chan_he_capable(pMac, pChnlParams); pChnlParams->dot11_mode = pSessionEntry->dot11mode; pChnlParams->nss = pSessionEntry->nss; - pe_debug("dot11mode: %d, vht_capable: %d nss value: %d", - pChnlParams->dot11_mode, pChnlParams->vhtCapable, - pChnlParams->nss); /*Set DFS flag for DFS channel */ if (ch_width == CH_WIDTH_160MHZ) { @@ -261,6 +258,7 @@ QDF_STATUS lim_send_switch_chnl_params(tpAniSirGlobal pMac, return QDF_STATUS_E_FAILURE; } pSessionEntry->ch_switch_in_progress = true; + return QDF_STATUS_SUCCESS; } diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_send_messages.h b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_send_messages.h index 6d3d405be94c..0c0eeeb9e27a 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_send_messages.h +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_send_messages.h @@ -89,6 +89,8 @@ void lim_set_active_edca_params(tpAniSirGlobal pMac, #define DS_PARAM_CHANNEL_MASK 0x0 #define VHTOP_CHWIDTH_MASK 0xFC +#define MAX_VENDOR_IES_LEN 1532 + #ifdef WLAN_FEATURE_11W QDF_STATUS lim_send_exclude_unencrypt_ind(tpAniSirGlobal pMac, bool excludeUnenc, diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_send_sme_rsp_messages.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_send_sme_rsp_messages.c index 3564fe6d662e..b3cf2ea9dd45 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_send_sme_rsp_messages.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_send_sme_rsp_messages.c @@ -265,44 +265,46 @@ static void lim_handle_join_rsp_status(tpAniSirGlobal mac_ctx, #ifdef FEATURE_WLAN_MCC_TO_SCC_SWITCH tSirSmeHTProfile *ht_profile; #endif + if (session_entry->beacon) { + sme_join_rsp->beaconLength = session_entry->bcnLen; + qdf_mem_copy(sme_join_rsp->frames, + session_entry->beacon, + sme_join_rsp->beaconLength); + qdf_mem_free(session_entry->beacon); + session_entry->beacon = NULL; + session_entry->bcnLen = 0; + } + + if (session_entry->assocReq) { + sme_join_rsp->assocReqLength = + session_entry->assocReqLen; + qdf_mem_copy(sme_join_rsp->frames + + sme_join_rsp->beaconLength, + session_entry->assocReq, + sme_join_rsp->assocReqLength); + qdf_mem_free(session_entry->assocReq); + session_entry->assocReq = NULL; + session_entry->assocReqLen = 0; + } + if (session_entry->assocRsp) { + sme_join_rsp->assocRspLength = + session_entry->assocRspLen; + qdf_mem_copy(sme_join_rsp->frames + + sme_join_rsp->beaconLength + + sme_join_rsp->assocReqLength, + session_entry->assocRsp, + sme_join_rsp->assocRspLength); + qdf_mem_free(session_entry->assocRsp); + session_entry->assocRsp = NULL; + session_entry->assocRspLen = 0; + } + + pe_debug("Beacon len %d Assoc Req len %d Assoc Rsp len %d", + sme_join_rsp->beaconLength, sme_join_rsp->assocReqLength, + sme_join_rsp->assocRspLength); + if (result_code == eSIR_SME_SUCCESS) { - if (session_entry->beacon != NULL) { - sme_join_rsp->beaconLength = session_entry->bcnLen; - qdf_mem_copy(sme_join_rsp->frames, - session_entry->beacon, - sme_join_rsp->beaconLength); - qdf_mem_free(session_entry->beacon); - session_entry->beacon = NULL; - session_entry->bcnLen = 0; - pe_debug("Beacon: %d", - sme_join_rsp->beaconLength); - } - if (session_entry->assocReq != NULL) { - sme_join_rsp->assocReqLength = - session_entry->assocReqLen; - qdf_mem_copy(sme_join_rsp->frames + - sme_join_rsp->beaconLength, - session_entry->assocReq, - sme_join_rsp->assocReqLength); - qdf_mem_free(session_entry->assocReq); - session_entry->assocReq = NULL; - session_entry->assocReqLen = 0; - pe_debug("AssocReq: %d", - sme_join_rsp->assocReqLength); - } - if (session_entry->assocRsp != NULL) { - sme_join_rsp->assocRspLength = - session_entry->assocRspLen; - qdf_mem_copy(sme_join_rsp->frames + - sme_join_rsp->beaconLength + - sme_join_rsp->assocReqLength, - session_entry->assocRsp, - sme_join_rsp->assocRspLength); - qdf_mem_free(session_entry->assocRsp); - session_entry->assocRsp = NULL; - session_entry->assocRspLen = 0; - } - if (session_entry->ricData != NULL) { + if (session_entry->ricData) { sme_join_rsp->parsedRicRspLen = session_entry->RICDataLen; qdf_mem_copy(sme_join_rsp->frames + @@ -318,7 +320,7 @@ static void lim_handle_join_rsp_status(tpAniSirGlobal mac_ctx, sme_join_rsp->parsedRicRspLen); } #ifdef FEATURE_WLAN_ESE - if (session_entry->tspecIes != NULL) { + if (session_entry->tspecIes) { sme_join_rsp->tspecIeLen = session_entry->tspecLen; qdf_mem_copy(sme_join_rsp->frames + @@ -336,8 +338,6 @@ static void lim_handle_join_rsp_status(tpAniSirGlobal mac_ctx, } #endif sme_join_rsp->aid = session_entry->limAID; - pe_debug("AssocRsp: %d", - sme_join_rsp->assocRspLength); sme_join_rsp->vht_channel_width = session_entry->ch_width; #ifdef FEATURE_WLAN_MCC_TO_SCC_SWITCH @@ -961,6 +961,14 @@ lim_send_sme_disassoc_ntf(tpAniSirGlobal pMac, (uint32_t *) pMsg); } /*** end lim_send_sme_disassoc_ntf() ***/ +static bool lim_is_disconnect_from_ap(enum eLimDisassocTrigger trigger) +{ + if (trigger == eLIM_PEER_ENTITY_DEAUTH || + trigger == eLIM_PEER_ENTITY_DISASSOC) + return true; + + return false; +} /** ----------------------------------------------------------------- \brief lim_send_sme_disassoc_ind() - sends SME_DISASSOC_IND @@ -1002,6 +1010,10 @@ lim_send_sme_disassoc_ind(tpAniSirGlobal pMac, tpDphHashNode pStaDs, pSirSmeDisassocInd->staId = pStaDs->staIndex; + if (LIM_IS_STA_ROLE(psessionEntry)) + pSirSmeDisassocInd->from_ap = + lim_is_disconnect_from_ap(pStaDs->mlmStaContext.cleanupTrigger); + mmhMsg.type = eWNI_SME_DISASSOC_IND; mmhMsg.bodyptr = pSirSmeDisassocInd; mmhMsg.bodyval = 0; @@ -1068,6 +1080,10 @@ lim_send_sme_deauth_ind(tpAniSirGlobal pMac, tpDphHashNode pStaDs, pStaDs->mlmStaContext.disassocReason) pSirSmeDeauthInd->rssi = pStaDs->del_sta_ctx_rssi; + if (LIM_IS_STA_ROLE(psessionEntry)) + pSirSmeDeauthInd->from_ap = + lim_is_disconnect_from_ap(pStaDs->mlmStaContext.cleanupTrigger); + mmhMsg.type = eWNI_SME_DEAUTH_IND; mmhMsg.bodyptr = pSirSmeDeauthInd; mmhMsg.bodyval = 0; @@ -1819,11 +1835,6 @@ static QDF_STATUS lim_process_csa_wbw_ie(tpAniSirGlobal mac_ctx, ap_new_ch_width = csa_params->new_ch_width + 1; - pe_debug("new channel: %d new_ch_width: %d seg0: %d seg1: %d", - csa_params->channel, ap_new_ch_width, - csa_params->new_ch_freq_seg1, - csa_params->new_ch_freq_seg2); - if ((ap_new_ch_width != CH_WIDTH_80MHZ) && (ap_new_ch_width != CH_WIDTH_160MHZ) && (ap_new_ch_width != CH_WIDTH_80P80MHZ)) { @@ -1922,11 +1933,6 @@ static QDF_STATUS lim_process_csa_wbw_ie(tpAniSirGlobal mac_ctx, chnl_switch_info->newChanWidth = ap_new_ch_width; } prnt_log: - pe_debug("new channel: %d new_ch_width: %d seg0: %d seg1: %d", - csa_params->channel, - chnl_switch_info->newChanWidth, - chnl_switch_info->newCenterChanFreq0, - chnl_switch_info->newCenterChanFreq1); return QDF_STATUS_SUCCESS; } @@ -1951,12 +1957,11 @@ void lim_handle_csa_offload_msg(tpAniSirGlobal mac_ctx, uint16_t aid = 0; uint16_t chan_space = 0; struct ch_params ch_params = {0}; + uint32_t channel_bonding_mode; tLimWiderBWChannelSwitchInfo *chnl_switch_info = NULL; tLimChannelSwitchInfo *lim_ch_switch = NULL; - pe_debug("handle csa offload msg"); - if (!csa_params) { pe_err("limMsgQ body ptr is NULL"); return; @@ -1967,6 +1972,13 @@ void lim_handle_csa_offload_msg(tpAniSirGlobal mac_ctx, pe_err("memalloc fail eWNI_SME_CSA_OFFLOAD_EVENT"); goto err; } + if (WLAN_REG_IS_24GHZ_CH(csa_params->channel)) { + channel_bonding_mode = + mac_ctx->roam.configParam.channelBondingMode24GHz; + } else { + channel_bonding_mode = + mac_ctx->roam.configParam.channelBondingMode5GHz; + } session_entry = pe_find_session_by_bssid(mac_ctx, @@ -2017,26 +2029,20 @@ void lim_handle_csa_offload_msg(tpAniSirGlobal mac_ctx, chnl_switch_info = &session_entry->gLimWiderBWChannelSwitch; - pe_debug("vht: %d ht: %d flag: %x chan: %d, sec_ch_offset %d", + pe_debug("Session %d vdev %d: vht: %d ht: %d cbmode %d", + session_entry->peSessionId, session_entry->smeSessionId, session_entry->vhtCapability, session_entry->htSupportedChannelWidthSet, - csa_params->ies_present_flag, - csa_params->channel, - csa_params->sec_chan_offset); - pe_debug("seg1: %d seg2: %d width: %d country: %s class: %d", - csa_params->new_ch_freq_seg1, - csa_params->new_ch_freq_seg2, - csa_params->new_ch_width, - mac_ctx->scan.countryCodeCurrent, - csa_params->new_op_class); - - if (session_entry->vhtCapability && - session_entry->htSupportedChannelWidthSet) { + channel_bonding_mode); + + session_entry->htSupportedChannelWidthSet = false; + + if (session_entry->vhtCapability && session_entry->htCapability && + channel_bonding_mode) { if ((csa_params->ies_present_flag & lim_wbw_ie_present) && (QDF_STATUS_SUCCESS == lim_process_csa_wbw_ie(mac_ctx, csa_params, chnl_switch_info, session_entry))) { - pe_debug("CSA wide BW IE process successful"); lim_ch_switch->sec_ch_offset = PHY_SINGLE_CHANNEL_CENTERED; if (chnl_switch_info->newChanWidth) { @@ -2047,6 +2053,8 @@ void lim_handle_csa_offload_msg(tpAniSirGlobal mac_ctx, else lim_ch_switch->sec_ch_offset = PHY_DOUBLE_CHANNEL_HIGH_PRIMARY; + session_entry->htSupportedChannelWidthSet = + true; } } else if (csa_params->ies_present_flag & lim_xcsa_ie_present) { @@ -2061,9 +2069,14 @@ void lim_handle_csa_offload_msg(tpAniSirGlobal mac_ctx, if (chan_space == 80) { chnl_switch_info->newChanWidth = CH_WIDTH_80MHZ; + session_entry->htSupportedChannelWidthSet = + true; + } else if (chan_space == 40) { chnl_switch_info->newChanWidth = CH_WIDTH_40MHZ; + session_entry->htSupportedChannelWidthSet = + true; } else { chnl_switch_info->newChanWidth = CH_WIDTH_20MHZ; @@ -2101,6 +2114,7 @@ void lim_handle_csa_offload_msg(tpAniSirGlobal mac_ctx, chnl_switch_info->newCenterChanFreq0 = ch_params.center_freq_seg0; chnl_switch_info->newCenterChanFreq1 = 0; + session_entry->htSupportedChannelWidthSet = true; } session_entry->gLimChannelSwitch.ch_center_freq_seg0 = chnl_switch_info->newCenterChanFreq0; @@ -2109,7 +2123,7 @@ void lim_handle_csa_offload_msg(tpAniSirGlobal mac_ctx, session_entry->gLimChannelSwitch.ch_width = chnl_switch_info->newChanWidth; - } else if (session_entry->htSupportedChannelWidthSet) { + } else if (channel_bonding_mode && session_entry->htCapability) { if (csa_params->ies_present_flag & lim_xcsa_ie_present) { chan_space = @@ -2133,6 +2147,8 @@ void lim_handle_csa_offload_msg(tpAniSirGlobal mac_ctx, ch_params.center_freq_seg0; lim_ch_switch->sec_ch_offset = ch_params.sec_ch_offset; + session_entry->htSupportedChannelWidthSet = + true; } else { lim_ch_switch->ch_width = CH_WIDTH_20MHZ; @@ -2155,14 +2171,20 @@ void lim_handle_csa_offload_msg(tpAniSirGlobal mac_ctx, ch_params.center_freq_seg0; lim_ch_switch->sec_ch_offset = ch_params.sec_ch_offset; + session_entry->htSupportedChannelWidthSet = true; } } - pe_debug("new ch width: %d space: %d", - session_entry->gLimChannelSwitch.ch_width, chan_space); - if ((session_entry->currentOperChannel == csa_params->channel) && - (session_entry->ch_width == - session_entry->gLimChannelSwitch.ch_width)) { + pe_debug("new ch %d width: %d freq0 %d freq1 %d ht width %d", + session_entry->gLimChannelSwitch.primaryChannel, + session_entry->gLimChannelSwitch.ch_width, + session_entry->gLimChannelSwitch.ch_center_freq_seg0, + session_entry->gLimChannelSwitch.ch_center_freq_seg1, + session_entry->gLimChannelSwitch.sec_ch_offset); + + if (session_entry->currentOperChannel == csa_params->channel && + session_entry->ch_width == + session_entry->gLimChannelSwitch.ch_width) { pe_debug("Ignore CSA, no change in ch and bw"); qdf_mem_free(csa_offload_ind); goto err; @@ -2191,7 +2213,6 @@ void lim_handle_csa_offload_msg(tpAniSirGlobal mac_ctx, mmh_msg.type = eWNI_SME_CSA_OFFLOAD_EVENT; mmh_msg.bodyptr = csa_offload_ind; mmh_msg.bodyval = 0; - pe_debug("Sending eWNI_SME_CSA_OFFLOAD_EVENT to SME"); MTRACE(mac_trace_msg_tx (mac_ctx, session_entry->peSessionId, mmh_msg.type)); #ifdef FEATURE_WLAN_DIAG_SUPPORT diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_session.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_session.c index 8127a20783c7..bca6f3666012 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_session.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_session.c @@ -495,23 +495,10 @@ void lim_update_bcn_probe_filter(tpAniSirGlobal mac_ctx, filter->num_sap_sessions); } -/** - * pe_create_session() creates a new PE session given the BSSID - * @param pMac: pointer to global adapter context - * @param bssid: BSSID of the new session - * @param sessionId: session ID is returned here, if session is created. - * @param bssType: station or a - * - * This function returns the session context and the session ID if the session - * corresponding to the passed BSSID is found in the PE session table. - * - * Return: tpPESession: pointer to the session context or NULL if session - * can not be created. - */ - tpPESession pe_create_session(tpAniSirGlobal pMac, uint8_t *bssid, uint8_t *sessionId, - uint16_t numSta, tSirBssType bssType) + uint16_t numSta, tSirBssType bssType, uint8_t vdev_id, + enum QDF_OPMODE opmode) { QDF_STATUS status; uint8_t i; @@ -577,6 +564,8 @@ pe_create_session(tpAniSirGlobal pMac, uint8_t *bssid, uint8_t *sessionId, *sessionId = i; session_ptr->peSessionId = i; session_ptr->bssType = bssType; + session_ptr->pePersona = opmode; + session_ptr->smeSessionId = vdev_id; session_ptr->gLimPhyMode = WNI_CFG_PHY_MODE_11G; /* Initialize CB mode variables when session is created */ session_ptr->htSupportedChannelWidthSet = 0; @@ -595,8 +584,9 @@ pe_create_session(tpAniSirGlobal pMac, uint8_t *bssid, uint8_t *sessionId, session_ptr->is_session_obss_color_collision_det_enabled = pMac->lim.global_obss_color_collision_det_offload; - pe_debug("Create a new PE session: %d BSSID: "MAC_ADDRESS_STR" Max No of STA: %d", - *sessionId, MAC_ADDR_ARRAY(bssid), numSta); + pe_debug("Create PE session: %d opmode %d vdev_id %d BSSID: "QDF_MAC_ADDR_STR" Max No of STA: %d", + *sessionId, opmode, vdev_id, QDF_MAC_ADDR_ARRAY(bssid), + numSta); if (eSIR_INFRA_AP_MODE == bssType || eSIR_IBSS_MODE == bssType) { session_ptr->pSchProbeRspTemplate = @@ -809,14 +799,14 @@ void pe_delete_session(tpAniSirGlobal mac_ctx, tpPESession session) TX_TIMER *timer_ptr; if (!session || (session && !session->valid)) { - pe_err("session is not valid"); + pe_debug("session already deleted or not valid"); return; } - pe_debug("Trying to delete PE session: %d Opmode: %d BssIdx: %d BSSID: "MAC_ADDRESS_STR, - session->peSessionId, session->operMode, - session->bssIdx, - MAC_ADDR_ARRAY(session->bssId)); + pe_debug("Delete PE session: %d opmode: %d vdev_id: %d BSSID: "QDF_MAC_ADDR_STR, + session->peSessionId, session->pePersona, + session->smeSessionId, + QDF_MAC_ADDR_ARRAY(session->bssId)); lim_reset_bcn_probe_filter(mac_ctx, session); @@ -1017,8 +1007,8 @@ tpPESession pe_find_session_by_peer_sta(tpAniSirGlobal pMac, uint8_t *sa, } } - pe_debug("Session lookup fails for Peer StaId:"); - lim_print_mac_addr(pMac, sa, LOGD); + pe_debug("Session lookup fails for Peer StaId: %pM", sa); + return NULL; } diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_session_utils.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_session_utils.c index ab6b5396d104..ca92d566bf84 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_session_utils.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_session_utils.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -32,40 +32,6 @@ #include "lim_session_utils.h" #include "lim_utils.h" -/** - * is_lim_session_off_channel() - checks if any other off channel session exists - * @mac_ctx: Global MAC context. - * @sessionId: PE session ID. - * - * Return: This function returns true if the session Id passed needs to be on - * a different channel than atleast one session already active. - **/ -uint8_t is_lim_session_off_channel(tpAniSirGlobal mac_ctx, uint8_t session_id) -{ - uint8_t i; - - if (session_id >= mac_ctx->lim.maxBssId) { - pe_warn("Invalid session_id: %d", session_id); - return false; - } - - for (i = 0; i < mac_ctx->lim.maxBssId; i++) { - /* Skip the session_id that is to be joined. */ - if (i == session_id) - continue; - /* - * if another session is valid and it is on different channel - * then it is an off channel operation. - */ - if ((mac_ctx->lim.gpSession[i].valid) && - (mac_ctx->lim.gpSession[i].currentOperChannel != - mac_ctx->lim.gpSession[session_id].currentOperChannel)) - return true; - } - return false; - -} - /** * lim_is_chan_switch_running() - check if channel switch is happening * @mac_ctx: Global MAC context. diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_session_utils.h b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_session_utils.h index 9639d270a025..edd49683d29f 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_session_utils.h +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_session_utils.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2015 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2015, 2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -19,7 +19,6 @@ #if !defined(__LIM_SESSION_UTILS_H) #define __LIM_SESSION_UTILS_H -uint8_t is_lim_session_off_channel(tpAniSirGlobal pMac, uint8_t sessionId); uint8_t lim_is_chan_switch_running(tpAniSirGlobal pMac); uint8_t lim_is_in_mcc(tpAniSirGlobal pMac); uint8_t pe_get_current_stas_count(tpAniSirGlobal pMac); diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_timer_utils.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_timer_utils.c index d784baf8eaad..c8f2750cf7b3 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_timer_utils.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_timer_utils.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -666,9 +666,9 @@ void lim_deactivate_and_change_timer(tpAniSirGlobal pMac, uint32_t timerId) pMac->lim.limTimers. g_lim_periodic_auth_retry_timer.sessionId); if (NULL == session_entry) { - pe_err("session does not exist for given SessionId : %d", - pMac->lim.limTimers. - g_lim_periodic_auth_retry_timer.sessionId); + pe_debug("session does not exist for given SessionId : %d", + pMac->lim.limTimers. + g_lim_periodic_auth_retry_timer.sessionId); break; } /* 3/5 of the beacon interval */ diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_trace.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_trace.c index 847dd2e8b24d..2f4786461848 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_trace.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_trace.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -119,7 +119,7 @@ void lim_trace_dump(void *pMac, tp_qdf_trace_record pRecord, switch (pRecord->code) { case TRACE_CODE_MLM_STATE: - pe_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", recIndex, + pe_nofl_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", recIndex, pRecord->qtime, pRecord->time, pRecord->session, "MLM State:", lim_trace_get_mlm_state_string( @@ -127,7 +127,7 @@ void lim_trace_dump(void *pMac, tp_qdf_trace_record pRecord, pRecord->data); break; case TRACE_CODE_SME_STATE: - pe_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", recIndex, + pe_nofl_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", recIndex, pRecord->qtime, pRecord->time, pRecord->session, "SME State:", lim_trace_get_sme_state_string( @@ -135,7 +135,7 @@ void lim_trace_dump(void *pMac, tp_qdf_trace_record pRecord, pRecord->data); break; case TRACE_CODE_TX_MGMT: - pe_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", recIndex, + pe_nofl_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", recIndex, pRecord->qtime, pRecord->time, pRecord->session, "TX Mgmt:", frameSubtypeStr[pRecord->data], pRecord->data); @@ -144,10 +144,10 @@ void lim_trace_dump(void *pMac, tp_qdf_trace_record pRecord, case TRACE_CODE_RX_MGMT: if (LIM_TRACE_MAX_SUBTYPES <= LIM_TRACE_GET_SUBTYPE(pRecord->data)) - pe_debug("Wrong Subtype - %d", + pe_nofl_debug("Wrong Subtype - %d", LIM_TRACE_GET_SUBTYPE(pRecord->data)); else - pe_debug("%04d %012llu %s S%d %-14s %-30s(%d) SN: %d", + pe_nofl_debug("%04d %012llu %s S%d %-14s %-30s(%d) SN: %d", recIndex, pRecord->qtime, pRecord->time, pRecord->session, "RX Mgmt:", frameSubtypeStr[LIM_TRACE_GET_SUBTYPE @@ -156,7 +156,7 @@ void lim_trace_dump(void *pMac, tp_qdf_trace_record pRecord, LIM_TRACE_GET_SSN(pRecord->data)); break; case TRACE_CODE_RX_MGMT_DROP: - pe_debug("%04d %012llu %s S%d %-14s %-30s(%d)", + pe_nofl_debug("%04d %012llu %s S%d %-14s %-30s(%d)", recIndex, pRecord->qtime, pRecord->time, pRecord->session, "Drop RX Mgmt:", __lim_trace_get_mgmt_drop_reason_string( @@ -165,27 +165,27 @@ void lim_trace_dump(void *pMac, tp_qdf_trace_record pRecord, break; case TRACE_CODE_RX_MGMT_TSF: - pe_debug("%04d %012llu %s S%d %-14s %-30s0x%x(%d)", + pe_nofl_debug("%04d %012llu %s S%d %-14s %-30s0x%x(%d)", recIndex, pRecord->qtime, pRecord->time, pRecord->session, "RX Mgmt TSF:", " ", pRecord->data, pRecord->data); break; case TRACE_CODE_TX_COMPLETE: - pe_debug("%04d %012llu %s S%d %-14s %d", recIndex, + pe_nofl_debug("%04d %012llu %s S%d %-14s %d", recIndex, pRecord->qtime, pRecord->time, pRecord->session, "TX Complete", pRecord->data); break; case TRACE_CODE_TX_SME_MSG: - pe_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", recIndex, + pe_nofl_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", recIndex, pRecord->qtime, pRecord->time, pRecord->session, "TX SME Msg:", mac_trace_get_sme_msg_string((uint16_t) pRecord->data), pRecord->data); break; case TRACE_CODE_RX_SME_MSG: - pe_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", recIndex, + pe_nofl_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", recIndex, pRecord->qtime, pRecord->time, pRecord->session, LIM_TRACE_GET_DEFRD_OR_DROPPED( pRecord->data) ? "Def/Drp LIM Msg:" : "RX Sme Msg:", @@ -194,7 +194,7 @@ void lim_trace_dump(void *pMac, tp_qdf_trace_record pRecord, break; case TRACE_CODE_TX_WMA_MSG: - pe_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", recIndex, + pe_nofl_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", recIndex, pRecord->qtime, pRecord->time, pRecord->session, "TX WMA Msg:", mac_trace_get_wma_msg_string((uint16_t) pRecord->data), @@ -202,7 +202,7 @@ void lim_trace_dump(void *pMac, tp_qdf_trace_record pRecord, break; case TRACE_CODE_RX_WMA_MSG: - pe_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", recIndex, + pe_nofl_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", recIndex, pRecord->qtime, pRecord->time, pRecord->session, LIM_TRACE_GET_DEFRD_OR_DROPPED( pRecord->data) ? "Def/Drp LIM Msg:" : "RX WMA Msg:", @@ -211,14 +211,14 @@ void lim_trace_dump(void *pMac, tp_qdf_trace_record pRecord, break; case TRACE_CODE_TX_LIM_MSG: - pe_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", recIndex, + pe_nofl_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", recIndex, pRecord->qtime, pRecord->time, pRecord->session, "TX LIM Msg:", mac_trace_get_lim_msg_string((uint16_t) pRecord->data), pRecord->data); break; case TRACE_CODE_RX_LIM_MSG: - pe_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", recIndex, + pe_nofl_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", recIndex, pRecord->qtime, pRecord->time, pRecord->session, LIM_TRACE_GET_DEFRD_OR_DROPPED( pRecord->data) ? "Def/Drp LIM Msg:" : "RX LIM Msg", @@ -226,14 +226,14 @@ void lim_trace_dump(void *pMac, tp_qdf_trace_record pRecord, pRecord->data); break; case TRACE_CODE_TX_CFG_MSG: - pe_debug("%04d %012llu %s S%d %-14s %-30s(0x%x) ", recIndex, + pe_nofl_debug("%04d %012llu %s S%d %-14s %-30s(0x%x) ", recIndex, pRecord->qtime, pRecord->time, pRecord->session, "TX CFG Msg:", mac_trace_get_cfg_msg_string((uint16_t) pRecord->data), pRecord->data); break; case TRACE_CODE_RX_CFG_MSG: - pe_debug("%04d %012llu %s S%d %-14s %-30s(0x%x) ", recIndex, + pe_nofl_debug("%04d %012llu %s S%d %-14s %-30s(0x%x) ", recIndex, pRecord->qtime, pRecord->time, pRecord->session, LIM_TRACE_GET_DEFRD_OR_DROPPED( pRecord->data) ? "Def/Drp LIM Msg:" : "RX CFG Msg:", @@ -243,14 +243,14 @@ void lim_trace_dump(void *pMac, tp_qdf_trace_record pRecord, break; case TRACE_CODE_TIMER_ACTIVATE: - pe_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", recIndex, + pe_nofl_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", recIndex, pRecord->qtime, pRecord->time, pRecord->session, "Timer Actvtd", __lim_trace_get_timer_string((uint16_t) pRecord->data), pRecord->data); break; case TRACE_CODE_TIMER_DEACTIVATE: - pe_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", recIndex, + pe_nofl_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", recIndex, pRecord->qtime, pRecord->time, pRecord->session, "Timer DeActvtd", __lim_trace_get_timer_string((uint16_t) pRecord->data), @@ -258,14 +258,14 @@ void lim_trace_dump(void *pMac, tp_qdf_trace_record pRecord, break; case TRACE_CODE_INFO_LOG: - pe_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", + pe_nofl_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", recIndex, pRecord->qtime, pRecord->time, pRecord->session, "INFORMATION_LOG", mac_trace_get_info_log_string((uint16_t) pRecord->data), pRecord->data); break; default: - pe_debug("%04d %012llu %s S%d %-14s(%d) (0x%x)", + pe_nofl_debug("%04d %012llu %s S%d %-14s(%d) (0x%x)", recIndex, pRecord->qtime, pRecord->time, pRecord->session, "Unknown Code", pRecord->code, pRecord->data); diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_types.h b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_types.h index 8b9e76059436..a96069598a4b 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_types.h +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_types.h @@ -455,8 +455,21 @@ void lim_process_probe_req_frame_multiple_bss(tpAniSirGlobal, uint8_t *, /* Process Auth frame when we have a session in progress. */ void lim_process_auth_frame(tpAniSirGlobal, uint8_t *, tpPESession); -QDF_STATUS lim_process_auth_frame_no_session(tpAniSirGlobal pMac, uint8_t *, - void *body); + +/** + * lim_process_auth_frame_no_session() - Process auth frame received from AP to + * which we are not connected currently. + * @mac: Pointer to global mac context + * @bd: Pointer to rx auth frame + * @body: Pointer to lim_msg->body_ptr + * + * This is possibly the pre-auth from the neighbor AP, in the same mobility + * domain or pre-authentication reply for WPA3 SAE roaming. + * This will be used in case of 11r FT. + */ +QDF_STATUS lim_process_auth_frame_no_session(tpAniSirGlobal mac, + uint8_t *bd, void *body); + void lim_process_assoc_req_frame(tpAniSirGlobal, uint8_t *, uint8_t, tpPESession); void lim_send_mlm_assoc_ind(tpAniSirGlobal pMac, tpDphHashNode pStaDs, @@ -713,8 +726,21 @@ static inline void lim_update_tdls_set_state_for_fw(tpPESession session_entry, /* / Function that handles heartbeat failure */ void lim_handle_heart_beat_failure(tpAniSirGlobal, tpPESession); -/* / Function that triggers link tear down with AP upon HB failure */ -void lim_tear_down_link_with_ap(tpAniSirGlobal, uint8_t, tSirMacReasonCodes); +/** + * lim_tear_down_link_with_ap() - Tear down link with AP + * @mac: mac context + * @session_id: PE session id + * @reason_code: Disconnect reason code as per emun eSirMacReasonCodes + * @trigger: Disconnect trigger as per enum eLimDisassocTrigger + * + * Function that triggers link tear down with AP upon HB failure + * + * Return: None + */ +void lim_tear_down_link_with_ap(tpAniSirGlobal mac, + uint8_t session_id, + tSirMacReasonCodes reason_code, + enum eLimDisassocTrigger trigger); /* / Function that processes Max retries interrupt from TFP */ void limHandleMaxRetriesInterrupt(uint32_t); diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_utils.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_utils.c index e39c9a0215d6..1de265ae67d9 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_utils.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_utils.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -418,7 +418,7 @@ char *lim_msg_str(uint32_t msgType) case eWNI_SME_HW_MODE_TRANS_IND: return "eWNI_SME_HW_MODE_TRANS_IND"; default: - return "INVALID SME message"; + return "Unknown"; } #endif return ""; @@ -489,7 +489,7 @@ char *lim_result_code_str(tSirResultCodes resultCode) return "eSIR_SME_HAL_SEND_MESSAGE_FAIL"; default: - return "INVALID resultCode"; + return "Unknown resultCode"; } } @@ -847,7 +847,7 @@ uint8_t lim_write_deferred_msg_q(tpAniSirGlobal mac_ctx, cds_flush_logs(WLAN_LOG_TYPE_NON_FATAL, WLAN_LOG_INDICATOR_HOST_DRIVER, WLAN_LOG_REASON_QUEUE_FULL, - true, false); + false, false); } else { mac_ctx->lim.deferredMsgCnt++; } @@ -1016,7 +1016,7 @@ void lim_handle_update_olbc_cache(tpAniSirGlobal mac_ctx) tpPESession psessionEntry = lim_is_ap_session_active(mac_ctx); if (psessionEntry == NULL) { - pe_err(" Session not found"); + pe_debug(" Session not found"); return; } @@ -2020,13 +2020,13 @@ void lim_process_channel_switch_timeout(tpAniSirGlobal pMac) lim_tear_down_link_with_ap(pMac, pMac->lim.limTimers. gLimChannelSwitchTimer.sessionId, - eSIR_MAC_UNSPEC_FAILURE_REASON); + eSIR_MAC_UNSUPPORTED_CHANNEL_CSA, + eLIM_LINK_MONITORING_DISASSOC); return; } } switch (psessionEntry->gLimChannelSwitch.state) { case eLIM_CHANNEL_SWITCH_PRIMARY_ONLY: - pe_warn("CHANNEL_SWITCH_PRIMARY_ONLY"); lim_switch_primary_channel(pMac, psessionEntry->gLimChannelSwitch. primaryChannel, psessionEntry); @@ -2034,7 +2034,6 @@ void lim_process_channel_switch_timeout(tpAniSirGlobal pMac) eLIM_CHANNEL_SWITCH_IDLE; break; case eLIM_CHANNEL_SWITCH_PRIMARY_AND_SECONDARY: - pe_warn("CHANNEL_SWITCH_PRIMARY_AND_SECONDARY"); lim_switch_primary_secondary_channel(pMac, psessionEntry, psessionEntry->gLimChannelSwitch.primaryChannel, psessionEntry->gLimChannelSwitch.ch_center_freq_seg0, @@ -2575,14 +2574,6 @@ void lim_switch_channel_cback(tpAniSirGlobal pMac, QDF_STATUS status, pSirSmeSwitchChInd->chan_params.center_freq_seg1 = psessionEntry->gLimChannelSwitch.ch_center_freq_seg1; - pe_debug("session: %d chan: %d width: %d sec offset: %d seg0: %d seg1: %d", - pSirSmeSwitchChInd->sessionId, - pSirSmeSwitchChInd->newChannelId, - pSirSmeSwitchChInd->chan_params.ch_width, - pSirSmeSwitchChInd->chan_params.sec_ch_offset, - pSirSmeSwitchChInd->chan_params.center_freq_seg0, - pSirSmeSwitchChInd->chan_params.center_freq_seg1); - qdf_mem_copy(pSirSmeSwitchChInd->bssid.bytes, psessionEntry->bssId, QDF_MAC_ADDR_SIZE); mmhMsg.bodyptr = pSirSmeSwitchChInd; @@ -2609,8 +2600,8 @@ void lim_switch_channel_cback(tpAniSirGlobal pMac, QDF_STATUS status, void lim_switch_primary_channel(tpAniSirGlobal pMac, uint8_t newChannel, tpPESession psessionEntry) { - pe_debug("old chnl: %d --> new chnl: %d", - psessionEntry->currentOperChannel, newChannel); + pe_debug("chan: %d --> chan: %d", + psessionEntry->currentOperChannel, newChannel); psessionEntry->currentReqChannel = newChannel; psessionEntry->limRFBand = lim_get_rf_band(newChannel); @@ -2668,13 +2659,13 @@ void lim_switch_primary_secondary_channel(tpAniSirGlobal pMac, /* Store the new primary and secondary channel in session entries if different */ if (psessionEntry->currentOperChannel != newChannel) { - pe_warn("switch old chnl: %d --> new chnl: %d", + pe_warn("chan: %d --> chan: %d", psessionEntry->currentOperChannel, newChannel); psessionEntry->currentOperChannel = newChannel; } if (psessionEntry->htSecondaryChannelOffset != psessionEntry->gLimChannelSwitch.sec_ch_offset) { - pe_warn("switch old sec chnl: %d --> new sec chnl: %d", + pe_warn("HT sec chnl: %d --> HT sec chnl: %d", psessionEntry->htSecondaryChannelOffset, psessionEntry->gLimChannelSwitch.sec_ch_offset); psessionEntry->htSecondaryChannelOffset = @@ -5204,7 +5195,6 @@ lim_prepare_for11h_channel_switch(tpAniSirGlobal pMac, tpPESession psessionEntry } return; } else { - pe_debug("Not in scan state, start channel switch timer"); /** We are safe to switch channel at this point */ lim_stop_tx_and_switch_channel(pMac, psessionEntry->peSessionId); } @@ -5510,9 +5500,8 @@ void lim_handle_heart_beat_failure_timeout(tpAniSirGlobal mac_ctx) * beacon after connection. */ (psession_entry->currentBssBeaconCnt == 0))) { - pe_debug("for session: %d", - psession_entry->peSessionId); - + pe_nofl_info("HB fail session %d", + psession_entry->peSessionId); lim_send_deauth_mgmt_frame(mac_ctx, eSIR_MAC_DISASSOC_DUE_TO_INACTIVITY_REASON, psession_entry->bssId, psession_entry, false); @@ -5523,7 +5512,8 @@ void lim_handle_heart_beat_failure_timeout(tpAniSirGlobal mac_ctx) */ lim_tear_down_link_with_ap(mac_ctx, psession_entry->peSessionId, - eSIR_BEACON_MISSED); + eSIR_MAC_BEACON_MISSED, + eLIM_LINK_MONITORING_DISASSOC); mac_ctx->lim.gLimProbeFailureAfterHBfailedCnt++; } else { pe_err("Unexpected wt-probe-timeout in state"); @@ -6692,7 +6682,7 @@ QDF_STATUS lim_strip_ie(tpAniSirGlobal mac_ctx, int left = *addn_ielen; uint8_t *ptr = addn_ie; uint8_t elem_id; - uint16_t elem_len; + uint16_t elem_len, ie_len, extracted_ie_len = 0; if (NULL == addn_ie) { pe_debug("NULL addn_ie pointer"); @@ -6705,6 +6695,9 @@ QDF_STATUS lim_strip_ie(tpAniSirGlobal mac_ctx, return QDF_STATUS_E_NOMEM; } + if (extracted_ie) + qdf_mem_zero(extracted_ie, eid_max_len + size_of_len_field + 1); + while (left >= 2) { elem_id = ptr[0]; left -= 1; @@ -6735,11 +6728,13 @@ QDF_STATUS lim_strip_ie(tpAniSirGlobal mac_ctx, * take oui IE and store in provided buffer. */ if (NULL != extracted_ie) { - qdf_mem_zero(extracted_ie, - eid_max_len + size_of_len_field + 1); - if (elem_len <= eid_max_len) - qdf_mem_copy(extracted_ie, &ptr[0], - elem_len + size_of_len_field + 1); + ie_len = elem_len + size_of_len_field + 1; + if (ie_len <= eid_max_len - extracted_ie_len) { + qdf_mem_copy( + extracted_ie + extracted_ie_len, + &ptr[0], ie_len); + extracted_ie_len += ie_len; + } } } left -= elem_len; @@ -7594,148 +7589,83 @@ void lim_log_he_cap(tpAniSirGlobal mac, tDot11fIEhe_cap *he_cap) if (!he_cap->present) return; - pe_debug("HE Capabilities:"); - - /* HE MAC capabilities */ - pe_debug("\tHTC-HE conrol: 0x%01x", he_cap->htc_he); - pe_debug("\tTWT Requestor support: 0x%01x", - he_cap->twt_request); - pe_debug("\tTWT Responder support: 0x%01x", - he_cap->twt_responder); - pe_debug("\tFragmentation support: 0x%02x", - he_cap->fragmentation); - pe_debug("\tMax no.of frag MSDUs: 0x%03x", - he_cap->max_num_frag_msdu); - pe_debug("\tMin. frag size: 0x%02x", he_cap->min_frag_size); - pe_debug("\tTrigger MAC pad duration: 0x%02x", - he_cap->trigger_frm_mac_pad); - pe_debug("\tMulti-TID aggr support: 0x%03x", - he_cap->multi_tid_aggr); - pe_debug("\tLink adaptation: 0x%02x", - he_cap->he_link_adaptation); - pe_debug("\tAll ACK support: 0x%01x", he_cap->all_ack); - pe_debug("\tUL MU resp. scheduling: 0x%01x", - he_cap->ul_mu_rsp_sched); - pe_debug("\tA-Buff status report: 0x%01x", he_cap->a_bsr); - pe_debug("\tBroadcast TWT support: 0x%01x", - he_cap->broadcast_twt); - pe_debug("\t32bit BA bitmap support: 0x%01x", - he_cap->ba_32bit_bitmap); - pe_debug("\tMU Cascading support: 0x%01x", - he_cap->mu_cascade); - pe_debug("\tACK enabled Multi-TID: 0x%01x", - he_cap->ack_enabled_multitid); - pe_debug("\tMulti-STA BA in DL MU: 0x%01x", he_cap->dl_mu_ba); - pe_debug("\tOMI A-Control support: 0x%01x", - he_cap->omi_a_ctrl); - pe_debug("\tOFDMA RA support: 0x%01x", he_cap->ofdma_ra); - pe_debug("\tMax A-MPDU Length: 0x%02x", - he_cap->max_ampdu_len); - pe_debug("\tA-MSDU Fragmentation: 0x%01x", - he_cap->amsdu_frag); - pe_debug("\tFlex. TWT sched support: 0x%01x", - he_cap->flex_twt_sched); - pe_debug("\tRx Ctrl frame to MBSS: 0x%01x", - he_cap->rx_ctrl_frame); - pe_debug("\tBSRP A-MPDU Aggregation: 0x%01x", - he_cap->bsrp_ampdu_aggr); - pe_debug("\tQuite Time Period support: 0x%01x", he_cap->qtp); - pe_debug("\tA-BQR support: 0x%01x", he_cap->a_bqr); - pe_debug("\tSR Reponder support: 0x%01x", he_cap->sr_responder); - pe_debug("\tNDP Feedback support: 0x%01x", he_cap->ndp_feedback_supp); - pe_debug("\tOPS support: 0x%01x", he_cap->ops_supp); - pe_debug("\tOPS support: 0x%01x", he_cap->amsdu_in_ampdu); - - /* HE PHY capabilities */ - pe_debug("\tDual band support: 0x%01x", he_cap->dual_band); + pe_nofl_debug("HE Capabilities: htc_he 0x%x twt_req 0x%x twt_res 0x%x fragmentation 0x%x max frag msdu amsdu 0x%x min frag 0x%x", + he_cap->htc_he, he_cap->twt_request, + he_cap->twt_responder, he_cap->fragmentation, + he_cap->max_num_frag_msdu, + he_cap->min_frag_size); + pe_nofl_debug("\ttrig frm mac pad 0x%x multi tid aggr supp 0x%x link adaptaion 0x%x all ack 0x%x trigd_rsp_sched 0x%x a_bsr 0x%x", + he_cap->trigger_frm_mac_pad, + he_cap->multi_tid_aggr, + he_cap->he_link_adaptation, he_cap->all_ack, + he_cap->ul_mu_rsp_sched, he_cap->a_bsr); + pe_nofl_debug("\tBC twt 0x%x ba_32bit_bitmap supp 0x%x mu_cascade 0x%x ack_enabled_multitid 0x%x omi_a_ctrl 0x%x ofdma_ra 0x%x", + he_cap->broadcast_twt, he_cap->ba_32bit_bitmap, + he_cap->mu_cascade, he_cap->ack_enabled_multitid, + he_cap->omi_a_ctrl, he_cap->ofdma_ra); + pe_nofl_debug("\tmax_ampdu_len exp ext 0x%x amsdu_frag 0x%x flex_twt_sched 0x%x rx_ctrl frm 0x%x bsrp_ampdu_aggr 0x%x qtp 0x%x a_bqr 0x%x", + he_cap->max_ampdu_len, he_cap->amsdu_frag, + he_cap->flex_twt_sched, he_cap->rx_ctrl_frame, + he_cap->bsrp_ampdu_aggr, he_cap->qtp, he_cap->a_bqr); + pe_nofl_debug("\tSR Reponder 0x%x ndp_feedback 0x%x ops_supp 0x%x amsdu_in_ampdu 0x%x", + he_cap->sr_responder, + he_cap->ndp_feedback_supp, + he_cap->ops_supp, he_cap->amsdu_in_ampdu); + chan_width = HE_CH_WIDTH_COMBINE(he_cap->chan_width_0, he_cap->chan_width_1, he_cap->chan_width_2, he_cap->chan_width_3, he_cap->chan_width_4, he_cap->chan_width_5, he_cap->chan_width_6); - pe_debug("\tChannel width support: 0x%07x", chan_width); - pe_debug("\tPreamble puncturing Rx: 0x%04x", - he_cap->rx_pream_puncturing); - pe_debug("\tClass of device: 0x%01x", he_cap->device_class); - pe_debug("\tLDPC coding support: 0x%01x", - he_cap->ldpc_coding); - pe_debug("\tLTF and GI for HE PPDUs: 0x%02x", - he_cap->he_1x_ltf_800_gi_ppdu); - pe_debug("\tMidamble Rx MAX NSTS: 0x%02x", - he_cap->midamble_rx_max_nsts); - pe_debug("\tLTF and GI for NDP: 0x%02x", - he_cap->he_4x_ltf_3200_gi_ndp); - pe_debug("\tSTBC Tx support (<= 80MHz): 0x%01x", - he_cap->tx_stbc_lt_80mhz); - pe_debug("\tSTBC Rx support (<= 80MHz): 0x%01x", - he_cap->rx_stbc_lt_80mhz); - pe_debug("\tDoppler support: 0x%02x", he_cap->doppler); - pe_debug("\tUL MU: 0x%02x", he_cap->ul_mu); - pe_debug("\tDCM encoding Tx: 0x%03x", he_cap->dcm_enc_tx); - pe_debug("\tDCM encoding Tx: 0x%03x", he_cap->dcm_enc_rx); - pe_debug("\tHE MU PPDU payload support: 0x%01x", - he_cap->ul_he_mu); - pe_debug("\tSU Beamformer: 0x%01x", he_cap->su_beamformer); - pe_debug("\tSU Beamformee: 0x%01x", he_cap->su_beamformee); - pe_debug("\tMU Beamformer: 0x%01x", he_cap->mu_beamformer); - pe_debug("\tBeamformee STS for <= 80Mhz: 0x%03x", - he_cap->bfee_sts_lt_80); - pe_debug("\tBeamformee STS for > 80Mhz: 0x%03x", - he_cap->bfee_sts_gt_80); - pe_debug("\tNo. of sounding dim <= 80Mhz: 0x%03x", - he_cap->num_sounding_lt_80); - pe_debug("\tNo. of sounding dim > 80Mhz: 0x%03x", - he_cap->num_sounding_gt_80); - pe_debug("\tNg=16 for SU feedback support: 0x%01x", - he_cap->su_feedback_tone16); - pe_debug("\tNg=16 for MU feedback support: 0x%01x", - he_cap->mu_feedback_tone16); - pe_debug("\tCodebook size for SU: 0x%01x", - he_cap->codebook_su); - pe_debug("\tCodebook size for MU: 0x%01x ", - he_cap->codebook_mu); - pe_debug("\tBeamforming trigger w/ Trigger: 0x%01x", - he_cap->beamforming_feedback); - pe_debug("\tHE ER SU PPDU payload: 0x%01x", - he_cap->he_er_su_ppdu); - pe_debug("\tDL MUMIMO on partial BW: 0x%01x", - he_cap->dl_mu_mimo_part_bw); - pe_debug("\tPPET present: 0x%01x", he_cap->ppet_present); - pe_debug("\tSRP based SR-support: 0x%01x", he_cap->srp); - pe_debug("\tPower boost factor: 0x%01x", he_cap->power_boost); - pe_debug("\t4x HE LTF support: 0x%01x", he_cap->he_ltf_800_gi_4x); - pe_debug("\tSTBC Tx support (> 80MHz): 0x%01x", - he_cap->tx_stbc_gt_80mhz); - pe_debug("\tSTBC Rx support (> 80MHz): 0x%01x", - he_cap->rx_stbc_gt_80mhz); - pe_debug("\tMax Nc: 0x%03x", he_cap->max_nc); - pe_debug("\tER 4x HE LTF support: 0x%01x", he_cap->er_he_ltf_800_gi_4x); - pe_debug("\tER 4x HE LTF support: 0x%01x", - he_cap->he_ppdu_20_in_40Mhz_2G); - pe_debug("\tER 4x HE LTF support: 0x%01x", - he_cap->he_ppdu_20_in_160_80p80Mhz); - pe_debug("\tER 4x HE LTF support: 0x%01x", - he_cap->he_ppdu_80_in_160_80p80Mhz); - pe_debug("\tER 4x HE LTF support: 0x%01x", - he_cap->er_1x_he_ltf_gi); - pe_debug("\tER 4x HE LTF support: 0x%01x", - he_cap->midamble_rx_1x_he_ltf); - pe_debug("\tRx MCS map for <= 80 Mhz: 0x%04x", - he_cap->rx_he_mcs_map_lt_80); - pe_debug("\tTx MCS map for <= 80 Mhz: 0x%04x", - he_cap->tx_he_mcs_map_lt_80); - pe_debug("\tRx MCS map for <= 160 Mhz: 0x%04x", - *((uint16_t *)he_cap->rx_he_mcs_map_160)); - pe_debug("\tTx MCS map for <= 160 Mhz: 0x%04x", - *((uint16_t *)he_cap->tx_he_mcs_map_160)); - pe_debug("\tRx MCS map for <= 80+80 Mhz: 0x%04x", - *((uint16_t *)he_cap->rx_he_mcs_map_80_80)); - pe_debug("\tTx MCS map for <= 80+80 Mhz: 0x%04x", - *((uint16_t *)he_cap->tx_he_mcs_map_80_80)); + pe_nofl_debug("\tchan width %d rx_pream_puncturing 0x%x device_class 0x%x ldpc_coding 0x%x 1x_ltf_800_gi_ppdu 0x%x midamble_tx_rx_max_nsts 0x%x", + chan_width, he_cap->rx_pream_puncturing, + he_cap->device_class, + he_cap->ldpc_coding, he_cap->he_1x_ltf_800_gi_ppdu, + he_cap->midamble_rx_max_nsts); + + pe_nofl_debug("\t4x_ltf_3200_gi_ndp 0x%x tb_ppdu_tx_stbc_lt_80mhz 0x%x rx_stbc_lt_80mhz 0x%x doppler 0x%x ul_mu 0x%x dcm_enc_tx 0x%x dcm_enc_rx 0x%x", + he_cap->he_4x_ltf_3200_gi_ndp, + he_cap->tx_stbc_lt_80mhz, + he_cap->rx_stbc_lt_80mhz, he_cap->doppler, he_cap->ul_mu, + he_cap->dcm_enc_tx, he_cap->dcm_enc_rx); + + pe_nofl_debug("\tul_he_mu 0x%x su_bfer 0x%x su_fee 0x%x mu_bfer 0x%x bfee_sts_lt_80 0x%x bfee_sts_gt_80 0x%x num_sd_lt_80 0x%x num_sd_gt_80 0x%x", + he_cap->ul_he_mu, he_cap->su_beamformer, + he_cap->su_beamformee, + he_cap->mu_beamformer, he_cap->bfee_sts_lt_80, + he_cap->bfee_sts_gt_80, he_cap->num_sounding_lt_80, + he_cap->num_sounding_gt_80); + + pe_nofl_debug("\tsu_fb_tone16 0x%x mu_fb_tone16 0x%x codebook_su 0x%x codebook_mu 0x%x bforming_feedback 0x%x he_er_su_ppdu 0x%x dl_mu_mimo_part_bw 0x%x", + he_cap->su_feedback_tone16, he_cap->mu_feedback_tone16, + he_cap->codebook_su, he_cap->codebook_mu, + he_cap->beamforming_feedback, he_cap->he_er_su_ppdu, + he_cap->dl_mu_mimo_part_bw); + + pe_nofl_debug("\tppet_present 0x%x srp 0x%x power_boost 0x%x ltf_800_gi_4x 0x%x max_nc 0x%x", + he_cap->ppet_present, he_cap->srp, + he_cap->power_boost, he_cap->he_ltf_800_gi_4x, + he_cap->max_nc); + + pe_nofl_debug("\ter_ltf_800_gi_4x 0x%x ppdu_20_in_40Mhz_2G 0x%x ppdu_20_in_160_80p80Mhz 0x%x ppdu_80_in_160_80p80Mhz 0x%x er_1x_ltf_gi 0x%x", + he_cap->er_he_ltf_800_gi_4x, + he_cap->he_ppdu_20_in_40Mhz_2G, + he_cap->he_ppdu_20_in_160_80p80Mhz, + he_cap->he_ppdu_80_in_160_80p80Mhz, + he_cap->er_1x_he_ltf_gi); + + pe_nofl_debug("\tmidamble_rx_1x_he_ltf 0x%x rx_he_mcs_map_lt_80 0x%x tx_he_mcs_map_lt_80 0x%x", + he_cap->midamble_rx_1x_he_ltf, + he_cap->rx_he_mcs_map_lt_80, + he_cap->tx_he_mcs_map_lt_80); hdr = (struct ppet_hdr *)&he_cap->ppet; - pe_debug("\t ppe_th:: nss_count: %d, ru_idx_msk: %d", - hdr->nss, hdr->ru_idx_mask); + pe_nofl_debug("\tRx MCS map 160 Mhz: 0x%x Tx MCS map 160 Mhz: 0x%x Rx MCS map 80+80 Mhz: 0x%x Tx MCS map 80+80 Mhz: 0x%x ppe_th:: nss_count: %d, ru_idx_msk: %d", + *((uint16_t *)he_cap->rx_he_mcs_map_160), + *((uint16_t *)he_cap->tx_he_mcs_map_160), + *((uint16_t *)he_cap->rx_he_mcs_map_80_80), + *((uint16_t *)he_cap->tx_he_mcs_map_80_80), + hdr->nss, hdr->ru_idx_mask); QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_PE, QDF_TRACE_LEVEL_DEBUG, &he_cap->ppet, HE_MAX_PPET_SIZE); @@ -7743,16 +7673,14 @@ void lim_log_he_cap(tpAniSirGlobal mac, tDot11fIEhe_cap *he_cap) void lim_log_he_op(tpAniSirGlobal mac, tDot11fIEhe_op *he_ops) { - pe_debug("bss_color: %0x, default_pe_duration: %0x, twt_required: %0x, rts_threshold: %0x, vht_oper_present: %0x", - he_ops->bss_color, he_ops->default_pe, - he_ops->twt_required, he_ops->rts_threshold, - he_ops->vht_oper_present); - pe_debug("\tpartial_bss_color: %0x, MBSSID AP: %0x, Tx BSSID Indicator: %0x, BSS color disabled: %0x", - he_ops->partial_bss_col, he_ops->mbssid_ap, - he_ops->tx_bssid_ind, he_ops->bss_col_disabled); - - pe_debug("he basic mcs nss: 0x%04x", - *((uint16_t *)he_ops->basic_mcs_nss)); + pe_debug("bss_color 0x%x, default_pe_dur 0x%x, twt_req 0x%x, txop_rts_thres 0x%x, vht_op 0x%x", + he_ops->bss_color, he_ops->default_pe, + he_ops->twt_required, he_ops->rts_threshold, + he_ops->vht_oper_present); + pe_debug("\tpart_bss_color 0x%x, mbssid_ap 0x%x, BSS color dis 0x%x basic mcs nss: 0x%x", + he_ops->partial_bss_col, he_ops->mbssid_ap, + he_ops->bss_col_disabled, + *((uint16_t *)he_ops->basic_mcs_nss)); if (he_ops->vht_oper_present) pe_debug("VHT Info not present in HE Operation"); @@ -8036,13 +7964,11 @@ QDF_STATUS lim_populate_he_mcs_set(tpAniSirGlobal mac_ctx, return QDF_STATUS_SUCCESS; } - pe_debug("peer rates lt 80: rx_mcs - 0x%04x tx_mcs - 0x%04x", + pe_debug("PEER: lt 80: rx 0x%04x tx 0x%04x, 160: rx 0x%04x tx 0x%04x, 80+80: rx 0x%04x tx 0x%04x", peer_he_caps->rx_he_mcs_map_lt_80, - peer_he_caps->tx_he_mcs_map_lt_80); - pe_debug("peer rates 160: rx_mcs - 0x%04x tx_mcs - 0x%04x", + peer_he_caps->tx_he_mcs_map_lt_80, (*(uint16_t *)peer_he_caps->rx_he_mcs_map_160), - (*(uint16_t *)peer_he_caps->tx_he_mcs_map_160)); - pe_debug("peer rates 80+80: rx_mcs - 0x%04x tx_mcs - 0x%04x", + (*(uint16_t *)peer_he_caps->tx_he_mcs_map_160), (*(uint16_t *)peer_he_caps->rx_he_mcs_map_80_80), (*(uint16_t *)peer_he_caps->tx_he_mcs_map_80_80)); @@ -8084,14 +8010,11 @@ QDF_STATUS lim_populate_he_mcs_set(tpAniSirGlobal mac_ctx, rates->tx_he_mcs_map_80_80 |= HE_MCS_INV_MSK_4_NSS(1); } - pe_debug("enable2x2 - %d nss %d", - mac_ctx->roam.configParam.enable2x2, nss); - pe_debug("he_rx_lt_80 - 0x%x he_tx_lt_80 0x%x", - rates->rx_he_mcs_map_lt_80, rates->tx_he_mcs_map_lt_80); - pe_debug("he_rx_160 - 0x%x he_tx_160 0x%x", - rates->rx_he_mcs_map_160, rates->tx_he_mcs_map_160); - pe_debug("he_rx_80_80 - 0x%x he_tx_80_80 0x%x", - rates->rx_he_mcs_map_80_80, rates->tx_he_mcs_map_80_80); + pe_debug("lt 80: rx 0x%x tx 0x%x, 160: rx 0x%x tx 0x%x, 80_80: rx 0x%x tx 0x%x", + rates->rx_he_mcs_map_lt_80, rates->tx_he_mcs_map_lt_80, + rates->rx_he_mcs_map_160, rates->tx_he_mcs_map_160, + rates->rx_he_mcs_map_80_80, rates->tx_he_mcs_map_80_80); + return QDF_STATUS_SUCCESS; } #endif @@ -8419,12 +8342,9 @@ void lim_process_ap_ecsa_timeout(void *data) return; } - if (session->gLimChannelSwitch.switchCount) { + if (session->gLimChannelSwitch.switchCount) /* Decrement the beacon switch count */ session->gLimChannelSwitch.switchCount--; - pe_debug("current beacon count %d", - session->gLimChannelSwitch.switchCount); - } /* * Send only g_sap_chanswitch_beacon_cnt beacons with CSA IE Set in @@ -8487,3 +8407,49 @@ void lim_process_ap_ecsa_timeout(void *data) } } +struct wlan_ies * +hdd_get_self_disconnect_ies(tpAniSirGlobal mac_ctx, uint8_t vdev_id) +{ + struct wlan_ies *discon_ie = NULL; + struct wlan_objmgr_vdev *vdev = + wlan_objmgr_get_vdev_by_id_from_psoc(mac_ctx->psoc, + vdev_id, + WLAN_MLME_SB_ID); + if (!vdev) { + pe_err("Got NULL vdev obj, returning"); + return NULL; + } + discon_ie = mlme_get_self_disconnect_ies(vdev); + wlan_objmgr_vdev_release_ref(vdev, WLAN_MLME_SB_ID); + + return discon_ie; +} + +void hdd_free_self_disconnect_ies(tpAniSirGlobal mac_ctx, uint8_t vdev_id) +{ + struct wlan_objmgr_vdev *vdev = + wlan_objmgr_get_vdev_by_id_from_psoc(mac_ctx->psoc, + vdev_id, + WLAN_MLME_SB_ID); + if (!vdev) { + pe_err("Got NULL vdev obj, returning"); + return; + } + mlme_free_self_disconnect_ies(vdev); + wlan_objmgr_vdev_release_ref(vdev, WLAN_MLME_SB_ID); + + return; +} + +bool lim_is_sha384_akm(enum ani_akm_type akm) +{ + switch (akm) { + case ANI_AKM_TYPE_FILS_SHA384: + case ANI_AKM_TYPE_FT_FILS_SHA384: + case ANI_AKM_TYPE_SUITEB_EAP_SHA384: + case ANI_AKM_TYPE_FT_SUITEB_EAP_SHA384: + return true; + default: + return false; + } +} diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_utils.h b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_utils.h index 393fcc2dd237..5b34ab2cb364 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_utils.h +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/lim/lim_utils.h @@ -1472,4 +1472,19 @@ static inline void lim_set_peer_twt_cap(tpPESession session, } #endif +struct wlan_ies * +hdd_get_self_disconnect_ies(tpAniSirGlobal mac_ctx, uint8_t vdev_id); + +void hdd_free_self_disconnect_ies(tpAniSirGlobal mac_ctx, uint8_t vdev_id); + +/** + * lim_is_sha384_akm() - Function to check if the negotiated AKM for the + * current session is based on sha384 key derivation function. + * @mac_ctx: pointer to mac data + * @akm: negotiated AKM for the current session + * + * Return: true if akm is sha384 based kdf or false + */ +bool lim_is_sha384_akm(enum ani_akm_type akm); + #endif /* __LIM_UTILS_H */ diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/rrm/rrm_api.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/rrm/rrm_api.c index 02418175ef20..5a0c655355bf 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/rrm/rrm_api.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/rrm/rrm_api.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -510,6 +510,11 @@ rrm_process_beacon_report_req(tpAniSirGlobal pMac, uint16_t measDuration, maxMeasduration; int8_t maxDuration; uint8_t sign; + uint8_t buf_left, buf_cons; + char ch_buf[RRM_CH_BUF_LEN]; + char *tmp_buf = NULL; + uint16_t ch_ctr = 0, idx_rpt = 0; + uint8_t *ch_lst = NULL; if (pBeaconReq->measurement_request.Beacon.BeaconReporting.present && (pBeaconReq->measurement_request.Beacon.BeaconReporting. @@ -519,7 +524,7 @@ rrm_process_beacon_report_req(tpAniSirGlobal pMac, /* Beacon reporting should not be included in request if number of repetitons is zero. */ /* IEEE Std 802.11k-2008 Table 7-29g and section 11.10.8.1 */ - pe_err("Dropping the request: Reporting condition included in beacon report request and it is not zero"); + pe_nofl_err("RX: [802.11 BCN_RPT] Dropping req: Reporting condition included is not zero"); return eRRM_INCAPABLE; } @@ -545,12 +550,27 @@ rrm_process_beacon_report_req(tpAniSirGlobal pMac, measDuration = pBeaconReq->measurement_request.Beacon.meas_duration; - pe_info("maxDuration = %d sign = %d maxMeasduration = %d measDuration = %d", - maxDuration, sign, maxMeasduration, measDuration); + pe_nofl_info("RX: [802.11 BCN_RPT] seq:%d SSID:%.*s BSSID:%pM Token:%d op_class:%d ch:%d meas_mode:%d meas_duration:%d max_dur: %d sign: %d max_meas_dur: %d", + pMac->rrm.rrmPEContext.prev_rrm_report_seq_num, + pBeaconReq->measurement_request.Beacon.SSID.num_ssid, + pBeaconReq->measurement_request.Beacon.SSID.ssid, + pBeaconReq->measurement_request.Beacon.BSSID, + pBeaconReq->measurement_token, + pBeaconReq->measurement_request.Beacon.regClass, + pBeaconReq->measurement_request.Beacon.channel, + pBeaconReq->measurement_request.Beacon.meas_mode, + measDuration, maxDuration, sign, maxMeasduration); + + if (measDuration == 0 && + pBeaconReq->measurement_request.Beacon.meas_mode != + eSIR_BEACON_TABLE) { + pe_nofl_err("RX: [802.11 BCN_RPT] Invalid measurement duration"); + return eRRM_REFUSED; + } if (maxMeasduration < measDuration) { if (pBeaconReq->durationMandatory) { - pe_err("Dropping the request: duration mandatory and maxduration > measduration"); + pe_nofl_err("RX: [802.11 BCN_RPT] Dropping the req: duration mandatory & maxduration > measduration"); return eRRM_REFUSED; } else measDuration = maxMeasduration; @@ -566,15 +586,19 @@ rrm_process_beacon_report_req(tpAniSirGlobal pMac, pCurrentReq->request.Beacon.last_beacon_report_indication = pBeaconReq->measurement_request.Beacon. last_beacon_report_indication.last_fragment; - pe_debug("Last Beacon Report in request = %d", - pCurrentReq->request.Beacon. - last_beacon_report_indication); + pe_debug("RX: [802.11 BCN_RPT] Last Bcn Report in the req: %d", + pCurrentReq->request.Beacon.last_beacon_report_indication); } else { pCurrentReq->request.Beacon.last_beacon_report_indication = 0; - pe_debug("Last Beacon report not present in request"); + pe_debug("RX: [802.11 BCN_RPT] Last Bcn rpt ind not present"); } if (pBeaconReq->measurement_request.Beacon.RequestedInfo.present) { + if (!pBeaconReq->measurement_request.Beacon.RequestedInfo. + num_requested_eids) { + pe_debug("RX: [802.11 BCN_RPT]: Requested num of EID is 0"); + return eRRM_FAILURE; + } pCurrentReq->request.Beacon.reqIes.pElementIds = qdf_mem_malloc(sizeof(uint8_t) * pBeaconReq->measurement_request.Beacon. @@ -583,6 +607,7 @@ rrm_process_beacon_report_req(tpAniSirGlobal pMac, pe_err("Unable to allocate memory for request IEs buffer"); return eRRM_FAILURE; } + pCurrentReq->request.Beacon.reqIes.num = pBeaconReq->measurement_request.Beacon.RequestedInfo. num_requested_eids; @@ -603,12 +628,9 @@ rrm_process_beacon_report_req(tpAniSirGlobal pMac, } /* Prepare the request to send to SME. */ pSmeBcnReportReq = qdf_mem_malloc(sizeof(tSirBeaconReportReqInd)); - if (NULL == pSmeBcnReportReq) { - pe_err("Unable to allocate memory during Beacon Report Req Ind to SME"); + if (!pSmeBcnReportReq) return eRRM_FAILURE; - } - /* Allocated memory for pSmeBcnReportReq....will be freed by other modulea */ qdf_mem_copy(pSmeBcnReportReq->bssId, pSessionEntry->bssId, sizeof(tSirMacAddr)); @@ -643,8 +665,8 @@ rrm_process_beacon_report_req(tpAniSirGlobal pMac, if (pBeaconReq->measurement_request.Beacon.num_APChannelReport) { uint8_t *ch_lst = pSmeBcnReportReq->channelList.channelNumber; uint8_t len; - uint16_t ch_ctr = 0; + ch_lst = pSmeBcnReportReq->channelList.channelNumber; for (num_APChanReport = 0; num_APChanReport < pBeaconReq->measurement_request.Beacon.num_APChannelReport; @@ -663,6 +685,21 @@ rrm_process_beacon_report_req(tpAniSirGlobal pMac, ch_ctr += len; } } + + if (ch_lst) { + buf_left = sizeof(ch_buf); + tmp_buf = ch_buf; + for (idx_rpt = 0; idx_rpt < ch_ctr; idx_rpt++) { + buf_cons = qdf_snprint(tmp_buf, buf_left, "%d ", + ch_lst[idx_rpt]); + buf_left -= buf_cons; + tmp_buf += buf_cons; + } + + if (ch_ctr) + pe_nofl_info("RX: [802.11 BCN_RPT] Ch-list:%s", ch_buf); + } + /* Send request to SME. */ mmhMsg.type = eWNI_SME_BEACON_REPORT_REQ_IND; mmhMsg.bodyptr = pSmeBcnReportReq; @@ -740,12 +777,14 @@ rrm_fill_beacon_ies(tpAniSirGlobal pMac, } while (BcnNumIes > 0) { - len = *(pBcnIes + 1) + 2; /* element id + length. */ + len = *(pBcnIes + 1); + len += 2; /* element id + length. */ pe_debug("EID = %d, len = %d total = %d", *pBcnIes, *(pBcnIes + 1), len); - if (len <= 2) { - pe_err("RRM: Invalid IE"); + if (BcnNumIes < len || len <= 2) { + pe_err("RRM: Invalid IE len:%d exp_len:%d", + len, BcnNumIes); break; } @@ -753,9 +792,6 @@ rrm_fill_beacon_ies(tpAniSirGlobal pMac, do { if ((!eids) || (*pBcnIes == eids[i])) { if (((*pNumIes) + len) < pIesMaxSize) { - pe_debug("Adding Eid %d, len=%d", - *pBcnIes, len); - qdf_mem_copy(pIes, pBcnIes, len); pIes += len; *pNumIes += len; @@ -838,8 +874,9 @@ rrm_process_beacon_report_xmit(tpAniSirGlobal mac_ctx, session_entry = pe_find_session_by_bssid(mac_ctx, beacon_xmit_ind->bssId, &session_id); - if (NULL == session_entry) { - pe_err("session does not exist for given bssId"); + if (!session_entry) { + pe_err("TX: [802.11 BCN_RPT] Session does not exist for bssId:%pM", + beacon_xmit_ind->bssId); status = QDF_STATUS_E_FAILURE; goto end; } @@ -854,18 +891,18 @@ rrm_process_beacon_report_xmit(tpAniSirGlobal mac_ctx, for (i = 0; i < MAX_BEACON_REPORTS && bss_desc_count < beacon_xmit_ind->numBssDesc; i++) { - beacon_report = - &report[i].report.beaconReport; + beacon_report = &report[i].report.beaconReport; /* * If the scan result is NULL then send report request * with option subelement as NULL. */ - pe_debug("report %d bss %d", i, bss_desc_count); + pe_debug("TX: [802.11 BCN_RPT] report %d bss %d", i, + bss_desc_count); bss_desc = beacon_xmit_ind-> pBssDescription[bss_desc_count]; + /* Prepare the beacon report and send it to the peer.*/ - report[i].token = - beacon_xmit_ind->uDialogToken; + report[i].token = beacon_xmit_ind->uDialogToken; report[i].refused = 0; report[i].incapable = 0; report[i].type = SIR_MAC_RRM_BEACON_TYPE; @@ -894,15 +931,14 @@ rrm_process_beacon_report_xmit(tpAniSirGlobal mac_ctx, bss_desc->bssId, sizeof(tSirMacAddr)); } + pe_debug("TX: [802.11 BCN_RPT] reporting detail requested %d", + curr_req->request.Beacon.reportingDetail); switch (curr_req->request.Beacon.reportingDetail) { case BEACON_REPORTING_DETAIL_NO_FF_IE: /* 0: No need to include any elements. */ - pe_debug("No reporting detail requested"); break; case BEACON_REPORTING_DETAIL_ALL_FF_REQ_IE: /* 1: Include all FFs and Requested Ies. */ - pe_debug("Only requested IEs in reporting detail requested"); - if (!bss_desc) break; @@ -918,7 +954,6 @@ rrm_process_beacon_report_xmit(tpAniSirGlobal mac_ctx, case BEACON_REPORTING_DETAIL_ALL_FF_IE: /* 2: default - Include all FFs and all Ies. */ default: - pe_debug("Default all IEs and FFs"); if (!bss_desc) break; @@ -945,7 +980,7 @@ rrm_process_beacon_report_xmit(tpAniSirGlobal mac_ctx, last_beacon_report_indication) { offset = GET_IE_LEN_IN_BSS( bss_desc->length) - rem_len; - pe_debug("offset %d ie_len %lu rem_len %d frag_id %d", + pe_debug("TX: [802.11 BCN_RPT] offset %d ie_len %lu rem_len %d frag_id %d", offset, GET_IE_LEN_IN_BSS(bss_desc->length), rem_len, frag_id); @@ -958,17 +993,17 @@ rrm_process_beacon_report_xmit(tpAniSirGlobal mac_ctx, false; frag_id = 0; bss_desc_count++; - pe_debug("No remaining IEs"); + pe_debug("TX: [802.11 BCN_RPT] No remaining IEs"); } if (curr_req->request.Beacon. last_beacon_report_indication) { - pe_debug("Setting last beacon report support"); + pe_debug("TX: [802.11 BCN_RPT] Setting last beacon report support"); beacon_report->last_bcn_report_ind_support = 1; } } - pe_debug("Total reports filled %d", i); + pe_debug("TX: [802.11 BCN_RPT] Total reports filled %d", i); num_frames = i / RADIO_REPORTS_MAX_IN_A_FRAME; if (i % RADIO_REPORTS_MAX_IN_A_FRAME) num_frames++; @@ -976,9 +1011,6 @@ rrm_process_beacon_report_xmit(tpAniSirGlobal mac_ctx, for (j = 0; j < num_frames; j++) { num_reports_in_frame = QDF_MIN((i - report_index), RADIO_REPORTS_MAX_IN_A_FRAME); - - pe_debug("Sending Action frame number %d", - num_reports_in_frame); lim_send_radio_measure_report_action_frame(mac_ctx, curr_req->dialog_token, num_reports_in_frame, (j == num_frames - 1) ? true : false, @@ -994,7 +1026,7 @@ rrm_process_beacon_report_xmit(tpAniSirGlobal mac_ctx, qdf_mem_free(beacon_xmit_ind->pBssDescription[counter]); if (beacon_xmit_ind->fMeasureDone) { - pe_debug("Measurement done....cleanup the context"); + pe_debug("Measurement done."); rrm_cleanup(mac_ctx); } @@ -1030,8 +1062,7 @@ static void rrm_process_beacon_request_failure(tpAniSirGlobal pMac, pReport->incapable = 1; break; default: - pe_err("Beacon request processing failed no report sent with status %d", - status); + pe_err("RX [802.11 BCN_RPT] Beacon request processing failed no report sent"); qdf_mem_free(pReport); return; } @@ -1115,6 +1146,7 @@ QDF_STATUS rrm_process_beacon_req(tpAniSirGlobal mac_ctx, tSirMacAddr peer, rrm_cleanup(mac_ctx); } } + return QDF_STATUS_SUCCESS; } @@ -1132,28 +1164,30 @@ QDF_STATUS rrm_process_beacon_req(tpAniSirGlobal mac_ctx, tSirMacAddr peer, */ static QDF_STATUS update_rrm_report(tpAniSirGlobal mac_ctx, - tpSirMacRadioMeasureReport report, + tpSirMacRadioMeasureReport *report, tDot11fRadioMeasurementRequest *rrm_req, uint8_t *num_report, int index) { - if (report == NULL) { + tpSirMacRadioMeasureReport rrm_report; + + if (!*report) { /* * Allocate memory to send reports for * any subsequent requests. */ - report = qdf_mem_malloc(sizeof(*report) * + *report = qdf_mem_malloc(sizeof(tSirMacRadioMeasureReport) * (rrm_req->num_MeasurementRequest - index)); - if (NULL == report) { - pe_err("Unable to allocate memory during RRM Req processing"); + if (!*report) { + pe_err("Fail to alloc mem during RRM Req processing"); return QDF_STATUS_E_NOMEM; } - pe_debug("rrm beacon type incapable of %d report", - *num_report); + pe_debug("rrm beacon type incapable of %d report", *num_report); } - report[*num_report].incapable = 1; - report[*num_report].type = + rrm_report = *report; + rrm_report[*num_report].incapable = 1; + rrm_report[*num_report].type = rrm_req->MeasurementRequest[index].measurement_type; - report[*num_report].token = + rrm_report[*num_report].token = rrm_req->MeasurementRequest[index].measurement_token; (*num_report)++; return QDF_STATUS_SUCCESS; @@ -1185,11 +1219,10 @@ rrm_process_radio_measurement_request(tpAniSirGlobal mac_ctx, if (!rrm_req->num_MeasurementRequest) { report = qdf_mem_malloc(sizeof(tSirMacRadioMeasureReport)); - if (NULL == report) { - pe_err("Unable to allocate memory during RRM Req processing"); + if (!report) return QDF_STATUS_E_NOMEM; - } - pe_err("No requestIes in the measurement request, sending incapable report"); + + pe_err("RX: [802.11 RRM] No requestIes, sending incapable report"); report->incapable = 1; num_report = 1; lim_send_radio_measure_report_action_frame(mac_ctx, @@ -1200,7 +1233,7 @@ rrm_process_radio_measurement_request(tpAniSirGlobal mac_ctx, } /* PF Fix */ if (rrm_req->NumOfRepetitions.repetitions > 0) { - pe_info("number of repetitions %d", + pe_info("RX: [802.11 RRM] number of repetitions %d, sending incapable report", rrm_req->NumOfRepetitions.repetitions); /* * Send a report with incapable bit set. @@ -1235,7 +1268,7 @@ rrm_process_radio_measurement_request(tpAniSirGlobal mac_ctx, break; default: /* Send a report with incapabale bit set. */ - status = update_rrm_report(mac_ctx, report, rrm_req, + status = update_rrm_report(mac_ctx, &report, rrm_req, &num_report, i); if (QDF_STATUS_SUCCESS != status) return status; diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/sch/sch_api.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/sch/sch_api.c index 79f877fd6f3a..d34f3534abe2 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/sch/sch_api.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/sch/sch_api.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -119,9 +119,6 @@ QDF_STATUS sch_send_beacon_req(tpAniSirGlobal pMac, uint8_t *beaconPayload, pMac->sch.schObject.csa_count_offset; beaconParams->ecsa_count_offset = pMac->sch.schObject.ecsa_count_offset; - pe_debug("csa_count_offset %d ecsa_count_offset %d", - beaconParams->csa_count_offset, - beaconParams->ecsa_count_offset); } } @@ -177,8 +174,6 @@ QDF_STATUS sch_send_beacon_req(tpAniSirGlobal pMac, uint8_t *beaconPayload, if (QDF_STATUS_SUCCESS != retCode) pe_err("Posting SEND_BEACON_REQ to HAL failed, reason=%X", retCode); - else - pe_debug("Successfully posted WMA_SEND_BEACON_REQ to HAL"); return retCode; } diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/sch/sch_beacon_gen.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/sch/sch_beacon_gen.c index 35006e2df4bc..8765591aae4b 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/sch/sch_beacon_gen.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/sch/sch_beacon_gen.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -451,7 +451,6 @@ sch_set_fixed_beacon_fields(tpAniSirGlobal mac_ctx, tpPESession session) populate_dot11f_ht_info(mac_ctx, &bcn_2->HTInfo, session); } if (session->vhtCapability) { - pe_debug("Populate VHT IEs in Beacon"); populate_dot11f_vht_caps(mac_ctx, session, &bcn_2->VHTCaps); populate_dot11f_vht_operation(mac_ctx, session, &bcn_2->VHTOperation); @@ -922,6 +921,12 @@ static QDF_STATUS write_beacon_to_memory(tpAniSirGlobal pMac, uint16_t size, /* copy end of beacon only if length > 0 */ if (length > 0) { + if (size + psessionEntry->schBeaconOffsetEnd > + SIR_MAX_BEACON_SIZE) { + pe_err("beacon tmp fail size %d BeaconOffsetEnd %d", + size, psessionEntry->schBeaconOffsetEnd); + return QDF_STATUS_E_FAILURE; + } for (i = 0; i < psessionEntry->schBeaconOffsetEnd; i++) psessionEntry->pSchBeaconFrameBegin[size++] = psessionEntry->pSchBeaconFrameEnd[i]; diff --git a/drivers/staging/qcacld-3.0/core/mac/src/pe/sch/sch_beacon_process.c b/drivers/staging/qcacld-3.0/core/mac/src/pe/sch/sch_beacon_process.c index b50be88b0dbb..c97f752a97f6 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/pe/sch/sch_beacon_process.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/pe/sch/sch_beacon_process.c @@ -45,7 +45,7 @@ #ifdef FEATURE_WLAN_DIAG_SUPPORT #include "host_diag_core_log.h" #endif /* FEATURE_WLAN_DIAG_SUPPORT */ - +#include "wlan_mlme_main.h" #include "wma.h" /** * Number of bytes of variation in beacon length from the last beacon @@ -879,16 +879,12 @@ static void __sch_beacon_process_for_session(tpAniSirGlobal mac_ctx, if (mac_ctx->roam.configParam.allow_tpc_from_ap) { get_local_power_constraint_beacon(bcn, &local_constraint); - pe_debug("ESE localPowerConstraint = %d,", - local_constraint); if (mac_ctx->rrm.rrmPEContext.rrmEnable && bcn->powerConstraintPresent) { local_constraint = regMax; local_constraint -= bcn->localPowerConstraint.localPowerConstraints; - pe_debug("localPowerConstraint = %d,", - local_constraint); } } @@ -901,14 +897,11 @@ static void __sch_beacon_process_for_session(tpAniSirGlobal mac_ctx, maxTxPower = lim_get_max_tx_power(mac_ctx, &tx_pwr_attr); - pe_debug("RegMax = %d, MaxTx pwr = %d", - regMax, maxTxPower); - /* If maxTxPower is increased or decreased */ if (maxTxPower != session->maxTxPower) { - pe_debug( - FL("Local power constraint change, Updating new maxTx power %d from old pwr %d"), - maxTxPower, session->maxTxPower); + pe_debug("Local power constraint change, Updating new maxTx power %d from old pwr %d (regMax %d local %d)", + maxTxPower, session->maxTxPower, regMax, + local_constraint); if (lim_send_set_max_tx_power_req(mac_ctx, maxTxPower, session) == QDF_STATUS_SUCCESS) session->maxTxPower = maxTxPower; @@ -933,10 +926,8 @@ static void __sch_beacon_process_for_session(tpAniSirGlobal mac_ctx, if ((false == mac_ctx->sap.SapDfsInfo.is_dfs_cac_timer_running) && beaconParams.paramChangeBitmap) { - pe_debug("Beacon for session[%d] got changed.", - session->peSessionId); - pe_debug("sending beacon param change bitmap: 0x%x", - beaconParams.paramChangeBitmap); + pe_debug("Beacon for session[%d] got changed param change bitmap: 0x%x", + session->peSessionId, beaconParams.paramChangeBitmap); lim_send_beacon_params(mac_ctx, &beaconParams, session); } @@ -1132,6 +1123,8 @@ void sch_send_beacon_report(struct sAniSirGlobal *mac_ctx, qdf_do_div(qdf_get_monotonic_boottime(), QDF_MC_TIMER_TO_MS_UNIT); + beacon_report.vdev_id = session->smeSessionId; + /* Send report to upper layer */ mac_ctx->lim.sme_bcn_rcv_callback(mac_ctx->hdd_handle, &beacon_report); @@ -1196,20 +1189,30 @@ sch_beacon_edca_process(tpAniSirGlobal pMac, tSirMacEdcaParamSetIE *edca, tpPESession session) { uint8_t i; + struct wlan_objmgr_vdev *vdev; + struct vdev_mlme_priv_obj *vdev_mlme; + bool follow_ap_edca = false; #ifdef FEATURE_WLAN_DIAG_SUPPORT host_log_qos_edca_pkt_type *log_ptr = NULL; #endif /* FEATURE_WLAN_DIAG_SUPPORT */ - pe_debug("Updating parameter set count: Old %d ---> new %d", - session->gLimEdcaParamSetCount, edca->qosInfo.count); - session->gLimEdcaParamSetCount = edca->qosInfo.count; session->gLimEdcaParams[EDCA_AC_BE] = edca->acbe; session->gLimEdcaParams[EDCA_AC_BK] = edca->acbk; session->gLimEdcaParams[EDCA_AC_VI] = edca->acvi; session->gLimEdcaParams[EDCA_AC_VO] = edca->acvo; - if (pMac->roam.configParam.enable_edca_params) { + vdev = wlan_objmgr_get_vdev_by_id_from_psoc(pMac->psoc, + session->smeSessionId, + WLAN_LEGACY_MAC_ID); + if (vdev) { + vdev_mlme = wlan_vdev_mlme_get_priv_obj(vdev); + if (vdev_mlme) + follow_ap_edca = vdev_mlme->follow_ap_edca; + wlan_objmgr_vdev_release_ref(vdev, WLAN_LEGACY_MAC_ID); + } + + if (pMac->roam.configParam.enable_edca_params && !follow_ap_edca) { session->gLimEdcaParams[EDCA_AC_VO].aci.aifsn = pMac->roam.configParam.edca_vo_aifs; session->gLimEdcaParams[EDCA_AC_VI].aci.aifsn = @@ -1271,15 +1274,15 @@ sch_beacon_edca_process(tpAniSirGlobal pMac, tSirMacEdcaParamSetIE *edca, } WLAN_HOST_DIAG_LOG_REPORT(log_ptr); #endif /* FEATURE_WLAN_DIAG_SUPPORT */ - pe_debug("Edsa param enabled in ini %d. Updating Local EDCA Params(gLimEdcaParams) to: ", + pe_debug("Edsa param enabled %d. Updating Local Params to: ", pMac->roam.configParam.enable_edca_params); for (i = 0; i < MAX_NUM_AC; i++) { - pe_debug("AC[%d]: AIFSN: %d, ACM %d, CWmin %d, CWmax %d, TxOp %d", - i, session->gLimEdcaParams[i].aci.aifsn, - session->gLimEdcaParams[i].aci.acm, - session->gLimEdcaParams[i].cw.min, - session->gLimEdcaParams[i].cw.max, - session->gLimEdcaParams[i].txoplimit); + pe_nofl_debug("AC[%d]: AIFSN: %d, ACM %d, CWmin %d, CWmax %d, TxOp %d", + i, session->gLimEdcaParams[i].aci.aifsn, + session->gLimEdcaParams[i].aci.acm, + session->gLimEdcaParams[i].cw.min, + session->gLimEdcaParams[i].cw.max, + session->gLimEdcaParams[i].txoplimit); } return QDF_STATUS_SUCCESS; } diff --git a/drivers/staging/qcacld-3.0/core/mac/src/sys/legacy/src/utils/src/dot11f.c b/drivers/staging/qcacld-3.0/core/mac/src/sys/legacy/src/utils/src/dot11f.c index ea103d9e75ff..e3b3d9133909 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/sys/legacy/src/utils/src/dot11f.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/sys/legacy/src/utils/src/dot11f.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -24,7 +24,7 @@ * * * This file was automatically generated by 'framesc' - * Mon Mar 25 14:48:07 2019 from the following file(s): + * Sat Feb 8 15:57:31 2020 from the following file(s): * * dot11f.frms * @@ -3724,6 +3724,54 @@ uint32_t dot11f_unpack_ie_aid(tpAniSirGlobal pCtx, #define SigIeAID (0x0027) +uint32_t dot11f_unpack_ie_BeaconReportStatus(tpAniSirGlobal pCtx, + uint8_t *pBuf, + uint8_t ielen, + tDot11fIEBeaconReportStatus *pDst, + bool append_ie) +{ + uint32_t status = DOT11F_PARSE_SUCCESS; + (void) pBuf; (void)ielen; /* Shutup the compiler */ + if (pDst->present) + return DOT11F_DUPLICATE_IE; + pDst->present = 1; + if (unlikely(ielen < 1)) { + pDst->present = 0; + return DOT11F_INCOMPLETE_IE; + } + + pDst->sub_type = *pBuf; + pBuf += 1; + ielen -= (uint8_t)1; + if (unlikely(ielen < 1)) { + pDst->present = 0; + return DOT11F_INCOMPLETE_IE; + } + + pDst->version = *pBuf; + pBuf += 1; + ielen -= (uint8_t)1; + if (unlikely(ielen < 1)) { + pDst->present = 0; + return DOT11F_INCOMPLETE_IE; + } + + pDst->length = *pBuf; + pBuf += 1; + ielen -= (uint8_t)1; + if (unlikely(ielen < 1)) { + pDst->present = 0; + return DOT11F_INCOMPLETE_IE; + } + + pDst->reason_code = *pBuf; + (void)pCtx; + return status; +} /* End dot11f_unpack_ie_BeaconReportStatus. */ + +#define SigIeBeaconReportStatus (0x0028) + + uint32_t dot11f_unpack_ie_cf_params(tpAniSirGlobal pCtx, uint8_t *pBuf, uint8_t ielen, @@ -3769,7 +3817,7 @@ uint32_t dot11f_unpack_ie_cf_params(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_cf_params. */ -#define SigIeCFParams (0x0028) +#define SigIeCFParams (0x0029) uint32_t dot11f_unpack_ie_challenge_text(tpAniSirGlobal pCtx, @@ -3794,7 +3842,7 @@ uint32_t dot11f_unpack_ie_challenge_text(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_challenge_text. */ -#define SigIeChallengeText (0x0029) +#define SigIeChallengeText (0x002a) uint32_t dot11f_unpack_ie_chan_switch_ann(tpAniSirGlobal pCtx, @@ -3834,7 +3882,7 @@ uint32_t dot11f_unpack_ie_chan_switch_ann(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_chan_switch_ann. */ -#define SigIeChanSwitchAnn (0x002a) +#define SigIeChanSwitchAnn (0x002b) static const tFFDefn FFS_ChannelSwitchWrapper[] = { @@ -3876,7 +3924,7 @@ uint32_t dot11f_unpack_ie_channel_switch_wrapper(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_channel_switch_wrapper. */ -#define SigIeChannelSwitchWrapper (0x002b) +#define SigIeChannelSwitchWrapper (0x002c) uint32_t dot11f_unpack_ie_country(tpAniSirGlobal pCtx, @@ -3914,10 +3962,10 @@ uint32_t dot11f_unpack_ie_country(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_country. */ -#define SigIeCountry (0x002c) +#define SigIeCountry (0x002d) -#define SigIeDSParams (0x002d) +#define SigIeDSParams (0x002e) uint32_t dot11f_unpack_ie_edca_param_set(tpAniSirGlobal pCtx, @@ -4077,7 +4125,7 @@ uint32_t dot11f_unpack_ie_edca_param_set(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_edca_param_set. */ -#define SigIeEDCAParamSet (0x002e) +#define SigIeEDCAParamSet (0x002f) uint32_t dot11f_unpack_ie_erp_info(tpAniSirGlobal pCtx, @@ -4106,7 +4154,7 @@ uint32_t dot11f_unpack_ie_erp_info(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_erp_info. */ -#define SigIeERPInfo (0x002f) +#define SigIeERPInfo (0x0030) uint32_t dot11f_unpack_ie_ese_cckm_opaque(tpAniSirGlobal pCtx, @@ -4131,7 +4179,7 @@ uint32_t dot11f_unpack_ie_ese_cckm_opaque(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_ese_cckm_opaque. */ -#define SigIeESECckmOpaque (0x0030) +#define SigIeESECckmOpaque (0x0031) uint32_t dot11f_unpack_ie_ese_rad_mgmt_cap(tpAniSirGlobal pCtx, @@ -4166,7 +4214,7 @@ uint32_t dot11f_unpack_ie_ese_rad_mgmt_cap(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_ese_rad_mgmt_cap. */ -#define SigIeESERadMgmtCap (0x0031) +#define SigIeESERadMgmtCap (0x0032) uint32_t dot11f_unpack_ie_ese_traf_strm_met(tpAniSirGlobal pCtx, @@ -4206,7 +4254,7 @@ uint32_t dot11f_unpack_ie_ese_traf_strm_met(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_ese_traf_strm_met. */ -#define SigIeESETrafStrmMet (0x0032) +#define SigIeESETrafStrmMet (0x0033) uint32_t dot11f_unpack_ie_ese_traf_strm_rate_set(tpAniSirGlobal pCtx, @@ -4239,7 +4287,7 @@ uint32_t dot11f_unpack_ie_ese_traf_strm_rate_set(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_ese_traf_strm_rate_set. */ -#define SigIeESETrafStrmRateSet (0x0033) +#define SigIeESETrafStrmRateSet (0x0034) uint32_t dot11f_unpack_ie_ese_txmit_power(tpAniSirGlobal pCtx, @@ -4271,7 +4319,7 @@ uint32_t dot11f_unpack_ie_ese_txmit_power(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_ese_txmit_power. */ -#define SigIeESETxmitPower (0x0034) +#define SigIeESETxmitPower (0x0035) uint32_t dot11f_unpack_ie_ese_version(tpAniSirGlobal pCtx, @@ -4295,7 +4343,8 @@ uint32_t dot11f_unpack_ie_ese_version(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_ese_version. */ -#define SigIeESEVersion (0x0035) +#define SigIeESEVersion (0x0036) + uint32_t dot11f_unpack_ie_ext_cap(tpAniSirGlobal pCtx, uint8_t *pBuf, @@ -4324,7 +4373,7 @@ uint32_t dot11f_unpack_ie_ext_cap(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_ext_cap. */ -#define SigIeExtCap (0x0036) +#define SigIeExtCap (0x0037) uint32_t dot11f_unpack_ie_ext_supp_rates(tpAniSirGlobal pCtx, @@ -4357,7 +4406,7 @@ uint32_t dot11f_unpack_ie_ext_supp_rates(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_ext_supp_rates. */ -#define SigIeExtSuppRates (0x0037) +#define SigIeExtSuppRates (0x0038) uint32_t dot11f_unpack_ie_fh_param_set(tpAniSirGlobal pCtx, @@ -4405,7 +4454,7 @@ uint32_t dot11f_unpack_ie_fh_param_set(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_fh_param_set. */ -#define SigIeFHParamSet (0x0038) +#define SigIeFHParamSet (0x0039) uint32_t dot11f_unpack_ie_fh_params(tpAniSirGlobal pCtx, @@ -4437,7 +4486,7 @@ uint32_t dot11f_unpack_ie_fh_params(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_fh_params. */ -#define SigIeFHParams (0x0039) +#define SigIeFHParams (0x003a) uint32_t dot11f_unpack_ie_fh_patt_table(tpAniSirGlobal pCtx, @@ -4494,7 +4543,7 @@ uint32_t dot11f_unpack_ie_fh_patt_table(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_fh_patt_table. */ -#define SigIeFHPattTable (0x003a) +#define SigIeFHPattTable (0x003b) static const tFFDefn FFS_FTInfo[] = { @@ -4574,7 +4623,7 @@ uint32_t dot11f_unpack_ie_ft_info(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_ft_info. */ -#define SigIeFTInfo (0x003b) +#define SigIeFTInfo (0x003c) uint32_t dot11f_unpack_ie_ht_caps(tpAniSirGlobal pCtx, @@ -4698,7 +4747,7 @@ uint32_t dot11f_unpack_ie_ht_caps(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_ht_caps. */ -#define SigIeHTCaps (0x003c) +#define SigIeHTCaps (0x003d) uint32_t dot11f_unpack_ie_ht_info(tpAniSirGlobal pCtx, @@ -4783,7 +4832,7 @@ uint32_t dot11f_unpack_ie_ht_info(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_ht_info. */ -#define SigIeHTInfo (0x003d) +#define SigIeHTInfo (0x003e) uint32_t dot11f_unpack_ie_ibss_params(tpAniSirGlobal pCtx, @@ -4807,7 +4856,7 @@ uint32_t dot11f_unpack_ie_ibss_params(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_ibss_params. */ -#define SigIeIBSSParams (0x003e) +#define SigIeIBSSParams (0x003f) uint32_t dot11f_unpack_ie_link_identifier(tpAniSirGlobal pCtx, @@ -4847,7 +4896,7 @@ uint32_t dot11f_unpack_ie_link_identifier(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_link_identifier. */ -#define SigIeLinkIdentifier (0x003f) +#define SigIeLinkIdentifier (0x0040) static const tTLVDefn TLVS_MBO_IE[] = { @@ -4910,7 +4959,7 @@ uint32_t dot11f_unpack_ie_MBO_IE(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_MBO_IE. */ -#define SigIeMBO_IE (0x0040) +#define SigIeMBO_IE (0x0041) static const tFFDefn FFS_reportBeacon[] = { @@ -5245,7 +5294,7 @@ uint32_t dot11f_unpack_ie_measurement_report(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_measurement_report. */ -#define SigIeMeasurementReport (0x0041) +#define SigIeMeasurementReport (0x0042) static const tFFDefn FFS_measurement_requestBeacon[] = { @@ -5549,7 +5598,7 @@ uint32_t dot11f_unpack_ie_measurement_request(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_measurement_request. */ -#define SigIeMeasurementRequest (0x0042) +#define SigIeMeasurementRequest (0x0043) uint32_t dot11f_unpack_ie_mobility_domain(tpAniSirGlobal pCtx, @@ -5585,7 +5634,7 @@ uint32_t dot11f_unpack_ie_mobility_domain(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_mobility_domain. */ -#define SigIeMobilityDomain (0x0043) +#define SigIeMobilityDomain (0x0044) static const tFFDefn FFS_NeighborReport[] = { @@ -5707,7 +5756,7 @@ uint32_t dot11f_unpack_ie_neighbor_report(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_neighbor_report. */ -#define SigIeNeighborReport (0x0044) +#define SigIeNeighborReport (0x0045) uint32_t dot11f_unpack_ie_obss_scan_parameters(tpAniSirGlobal pCtx, @@ -5779,7 +5828,7 @@ uint32_t dot11f_unpack_ie_obss_scan_parameters(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_obss_scan_parameters. */ -#define SigIeOBSSScanParameters (0x0045) +#define SigIeOBSSScanParameters (0x0046) uint32_t dot11f_unpack_ie_operating_mode(tpAniSirGlobal pCtx, @@ -5808,7 +5857,7 @@ uint32_t dot11f_unpack_ie_operating_mode(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_operating_mode. */ -#define SigIeOperatingMode (0x0046) +#define SigIeOperatingMode (0x0047) static const tTLVDefn TLVS_P2PAssocReq[] = { @@ -5840,7 +5889,7 @@ uint32_t dot11f_unpack_ie_p2_p_assoc_req(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_p2_p_assoc_req. */ -#define SigIeP2PAssocReq (0x0047) +#define SigIeP2PAssocReq (0x0048) static const tTLVDefn TLVS_P2PAssocRes[] = { @@ -5869,7 +5918,7 @@ uint32_t dot11f_unpack_ie_p2_p_assoc_res(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_p2_p_assoc_res. */ -#define SigIeP2PAssocRes (0x0048) +#define SigIeP2PAssocRes (0x0049) static const tTLVDefn TLVS_P2PBeacon[] = { @@ -5901,7 +5950,7 @@ uint32_t dot11f_unpack_ie_p2_p_beacon(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_p2_p_beacon. */ -#define SigIeP2PBeacon (0x0049) +#define SigIeP2PBeacon (0x004a) static const tTLVDefn TLVS_P2PBeaconProbeRes[] = { @@ -5943,7 +5992,7 @@ uint32_t dot11f_unpack_ie_p2_p_beacon_probe_res(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_p2_p_beacon_probe_res. */ -#define SigIeP2PBeaconProbeRes (0x004a) +#define SigIeP2PBeaconProbeRes (0x004b) static const tTLVDefn TLVS_P2PDeAuth[] = { @@ -5969,7 +6018,7 @@ uint32_t dot11f_unpack_ie_p2_p_de_auth(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_p2_p_de_auth. */ -#define SigIeP2PDeAuth (0x004b) +#define SigIeP2PDeAuth (0x004c) static const tTLVDefn TLVS_P2PDisAssoc[] = { @@ -5995,7 +6044,7 @@ uint32_t dot11f_unpack_ie_p2_p_dis_assoc(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_p2_p_dis_assoc. */ -#define SigIeP2PDisAssoc (0x004c) +#define SigIeP2PDisAssoc (0x004d) uint32_t dot11f_unpack_ie_p2_pie_opaque(tpAniSirGlobal pCtx, @@ -6020,7 +6069,7 @@ uint32_t dot11f_unpack_ie_p2_pie_opaque(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_p2_pie_opaque. */ -#define SigIeP2PIEOpaque (0x004d) +#define SigIeP2PIEOpaque (0x004e) static const tTLVDefn TLVS_P2PProbeReq[] = { @@ -6059,7 +6108,7 @@ uint32_t dot11f_unpack_ie_p2_p_probe_req(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_p2_p_probe_req. */ -#define SigIeP2PProbeReq (0x004e) +#define SigIeP2PProbeReq (0x004f) static const tTLVDefn TLVS_P2PProbeRes[] = { @@ -6098,7 +6147,7 @@ uint32_t dot11f_unpack_ie_p2_p_probe_res(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_p2_p_probe_res. */ -#define SigIeP2PProbeRes (0x004f) +#define SigIeP2PProbeRes (0x0050) uint32_t dot11f_unpack_ie_pti_control(tpAniSirGlobal pCtx, @@ -6130,7 +6179,7 @@ uint32_t dot11f_unpack_ie_pti_control(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_pti_control. */ -#define SigIePTIControl (0x0050) +#define SigIePTIControl (0x0051) uint32_t dot11f_unpack_ie_pu_buffer_status(tpAniSirGlobal pCtx, @@ -6160,7 +6209,7 @@ uint32_t dot11f_unpack_ie_pu_buffer_status(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_pu_buffer_status. */ -#define SigIePUBufferStatus (0x0051) +#define SigIePUBufferStatus (0x0052) uint32_t dot11f_unpack_ie_power_caps(tpAniSirGlobal pCtx, @@ -6192,7 +6241,7 @@ uint32_t dot11f_unpack_ie_power_caps(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_power_caps. */ -#define SigIePowerCaps (0x0052) +#define SigIePowerCaps (0x0053) uint32_t dot11f_unpack_ie_power_constraints(tpAniSirGlobal pCtx, @@ -6216,7 +6265,7 @@ uint32_t dot11f_unpack_ie_power_constraints(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_power_constraints. */ -#define SigIePowerConstraints (0x0053) +#define SigIePowerConstraints (0x0054) uint32_t dot11f_unpack_ie_qbss_load(tpAniSirGlobal pCtx, @@ -6256,7 +6305,7 @@ uint32_t dot11f_unpack_ie_qbss_load(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_qbss_load. */ -#define SigIeQBSSLoad (0x0054) +#define SigIeQBSSLoad (0x0055) uint32_t dot11f_unpack_ie_QCN_IE(tpAniSirGlobal pCtx, @@ -6280,7 +6329,7 @@ uint32_t dot11f_unpack_ie_QCN_IE(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_QCN_IE. */ -#define SigIeQCN_IE (0x0055) +#define SigIeQCN_IE (0x0056) uint32_t dot11f_unpack_ie_QComVendorIE(tpAniSirGlobal pCtx, @@ -6312,7 +6361,7 @@ uint32_t dot11f_unpack_ie_QComVendorIE(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_QComVendorIE. */ -#define SigIeQComVendorIE (0x0056) +#define SigIeQComVendorIE (0x0057) uint32_t dot11f_unpack_ie_qos_caps_ap(tpAniSirGlobal pCtx, @@ -6342,7 +6391,7 @@ uint32_t dot11f_unpack_ie_qos_caps_ap(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_qos_caps_ap. */ -#define SigIeQOSCapsAp (0x0057) +#define SigIeQOSCapsAp (0x0058) uint32_t dot11f_unpack_ie_qos_caps_station(tpAniSirGlobal pCtx, @@ -6374,7 +6423,7 @@ uint32_t dot11f_unpack_ie_qos_caps_station(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_qos_caps_station. */ -#define SigIeQOSCapsStation (0x0058) +#define SigIeQOSCapsStation (0x0059) uint32_t dot11f_unpack_ie_qos_map_set(tpAniSirGlobal pCtx, @@ -6399,7 +6448,7 @@ uint32_t dot11f_unpack_ie_qos_map_set(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_qos_map_set. */ -#define SigIeQosMapSet (0x0059) +#define SigIeQosMapSet (0x005a) uint32_t dot11f_unpack_ie_quiet(tpAniSirGlobal pCtx, @@ -6447,7 +6496,7 @@ uint32_t dot11f_unpack_ie_quiet(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_quiet. */ -#define SigIeQuiet (0x005a) +#define SigIeQuiet (0x005b) uint32_t dot11f_unpack_ie_rcpiie(tpAniSirGlobal pCtx, @@ -6471,7 +6520,7 @@ uint32_t dot11f_unpack_ie_rcpiie(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_rcpiie. */ -#define SigIeRCPIIE (0x005b) +#define SigIeRCPIIE (0x005c) static const tFFDefn FFS_RICDataDesc[] = { @@ -6547,7 +6596,7 @@ uint32_t dot11f_unpack_ie_ric_data_desc(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_ric_data_desc. */ -#define SigIeRICDataDesc (0x005c) +#define SigIeRICDataDesc (0x005d) uint32_t dot11f_unpack_ie_rsn(tpAniSirGlobal pCtx, @@ -6723,7 +6772,7 @@ uint32_t dot11f_unpack_ie_rsn(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_rsn. */ -#define SigIeRSN (0x005d) +#define SigIeRSN (0x005e) uint32_t dot11f_unpack_ie_rsniie(tpAniSirGlobal pCtx, @@ -6747,7 +6796,7 @@ uint32_t dot11f_unpack_ie_rsniie(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_rsniie. */ -#define SigIeRSNIIE (0x005e) +#define SigIeRSNIIE (0x005f) uint32_t dot11f_unpack_ie_rsn_opaque(tpAniSirGlobal pCtx, @@ -6772,7 +6821,7 @@ uint32_t dot11f_unpack_ie_rsn_opaque(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_rsn_opaque. */ -#define SigIeRSNOpaque (0x005f) +#define SigIeRSNOpaque (0x0060) uint32_t dot11f_unpack_ie_supp_channels(tpAniSirGlobal pCtx, @@ -6797,7 +6846,7 @@ uint32_t dot11f_unpack_ie_supp_channels(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_supp_channels. */ -#define SigIeSuppChannels (0x0060) +#define SigIeSuppChannels (0x0061) uint32_t dot11f_unpack_ie_supp_operating_classes(tpAniSirGlobal pCtx, @@ -6822,7 +6871,7 @@ uint32_t dot11f_unpack_ie_supp_operating_classes(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_supp_operating_classes. */ -#define SigIeSuppOperatingClasses (0x0061) +#define SigIeSuppOperatingClasses (0x0062) uint32_t dot11f_unpack_ie_supp_rates(tpAniSirGlobal pCtx, @@ -6855,7 +6904,7 @@ uint32_t dot11f_unpack_ie_supp_rates(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_supp_rates. */ -#define SigIeSuppRates (0x0062) +#define SigIeSuppRates (0x0063) uint32_t dot11f_unpack_ie_tim(tpAniSirGlobal pCtx, @@ -6904,7 +6953,7 @@ uint32_t dot11f_unpack_ie_tim(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_tim. */ -#define SigIeTIM (0x0063) +#define SigIeTIM (0x0064) uint32_t dot11f_unpack_ie_tpc_report(tpAniSirGlobal pCtx, @@ -6936,7 +6985,7 @@ uint32_t dot11f_unpack_ie_tpc_report(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_tpc_report. */ -#define SigIeTPCReport (0x0064) +#define SigIeTPCReport (0x0065) uint32_t dot11f_unpack_ie_tpc_request(tpAniSirGlobal pCtx, @@ -6954,7 +7003,7 @@ uint32_t dot11f_unpack_ie_tpc_request(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_tpc_request. */ -#define SigIeTPCRequest (0x0065) +#define SigIeTPCRequest (0x0066) uint32_t dot11f_unpack_ie_time_advertisement(tpAniSirGlobal pCtx, @@ -6994,7 +7043,7 @@ uint32_t dot11f_unpack_ie_time_advertisement(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_time_advertisement. */ -#define SigIeTimeAdvertisement (0x0066) +#define SigIeTimeAdvertisement (0x0067) uint32_t dot11f_unpack_ie_timeout_interval(tpAniSirGlobal pCtx, @@ -7026,7 +7075,7 @@ uint32_t dot11f_unpack_ie_timeout_interval(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_timeout_interval. */ -#define SigIeTimeoutInterval (0x0067) +#define SigIeTimeoutInterval (0x0068) uint32_t dot11f_unpack_ie_vht_ext_bss_load(tpAniSirGlobal pCtx, @@ -7082,7 +7131,7 @@ uint32_t dot11f_unpack_ie_vht_ext_bss_load(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_vht_ext_bss_load. */ -#define SigIeVHTExtBssLoad (0x0068) +#define SigIeVHTExtBssLoad (0x0069) uint32_t dot11f_unpack_ie_vendor1_ie(tpAniSirGlobal pCtx, @@ -7100,7 +7149,7 @@ uint32_t dot11f_unpack_ie_vendor1_ie(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_vendor1_ie. */ -#define SigIeVendor1IE (0x0069) +#define SigIeVendor1IE (0x006a) uint32_t dot11f_unpack_ie_vendor3_ie(tpAniSirGlobal pCtx, @@ -7118,7 +7167,7 @@ uint32_t dot11f_unpack_ie_vendor3_ie(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_vendor3_ie. */ -#define SigIeVendor3IE (0x006a) +#define SigIeVendor3IE (0x006b) uint32_t dot11f_unpack_ie_wapi(tpAniSirGlobal pCtx, @@ -7233,7 +7282,7 @@ uint32_t dot11f_unpack_ie_wapi(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_wapi. */ -#define SigIeWAPI (0x006b) +#define SigIeWAPI (0x006c) uint32_t dot11f_unpack_ie_wapi_opaque(tpAniSirGlobal pCtx, @@ -7258,7 +7307,7 @@ uint32_t dot11f_unpack_ie_wapi_opaque(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_wapi_opaque. */ -#define SigIeWAPIOpaque (0x006c) +#define SigIeWAPIOpaque (0x006d) uint32_t dot11f_unpack_ie_wfatpc(tpAniSirGlobal pCtx, @@ -7290,7 +7339,7 @@ uint32_t dot11f_unpack_ie_wfatpc(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_wfatpc. */ -#define SigIeWFATPC (0x006d) +#define SigIeWFATPC (0x006e) uint32_t dot11f_unpack_ie_wfdie_opaque(tpAniSirGlobal pCtx, @@ -7315,7 +7364,7 @@ uint32_t dot11f_unpack_ie_wfdie_opaque(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_wfdie_opaque. */ -#define SigIeWFDIEOpaque (0x006e) +#define SigIeWFDIEOpaque (0x006f) uint32_t dot11f_unpack_ie_wmm_caps(tpAniSirGlobal pCtx, @@ -7357,7 +7406,7 @@ uint32_t dot11f_unpack_ie_wmm_caps(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_wmm_caps. */ -#define SigIeWMMCaps (0x006f) +#define SigIeWMMCaps (0x0070) uint32_t dot11f_unpack_ie_wmm_info_ap(tpAniSirGlobal pCtx, @@ -7393,7 +7442,7 @@ uint32_t dot11f_unpack_ie_wmm_info_ap(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_wmm_info_ap. */ -#define SigIeWMMInfoAp (0x0070) +#define SigIeWMMInfoAp (0x0071) uint32_t dot11f_unpack_ie_wmm_info_station(tpAniSirGlobal pCtx, @@ -7433,7 +7482,7 @@ uint32_t dot11f_unpack_ie_wmm_info_station(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_wmm_info_station. */ -#define SigIeWMMInfoStation (0x0071) +#define SigIeWMMInfoStation (0x0072) uint32_t dot11f_unpack_ie_wmm_params(tpAniSirGlobal pCtx, @@ -7605,7 +7654,7 @@ uint32_t dot11f_unpack_ie_wmm_params(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_wmm_params. */ -#define SigIeWMMParams (0x0072) +#define SigIeWMMParams (0x0073) uint32_t dot11f_unpack_ie_wpa(tpAniSirGlobal pCtx, @@ -7714,7 +7763,7 @@ uint32_t dot11f_unpack_ie_wpa(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_wpa. */ -#define SigIeWPA (0x0073) +#define SigIeWPA (0x0074) uint32_t dot11f_unpack_ie_wpa_opaque(tpAniSirGlobal pCtx, @@ -7739,7 +7788,7 @@ uint32_t dot11f_unpack_ie_wpa_opaque(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_wpa_opaque. */ -#define SigIeWPAOpaque (0x0074) +#define SigIeWPAOpaque (0x0075) static const tTLVDefn TLVS_WSC[] = { @@ -7830,7 +7879,7 @@ uint32_t dot11f_unpack_ie_wsc(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_wsc. */ -#define SigIeWSC (0x0075) +#define SigIeWSC (0x0076) static const tTLVDefn TLVS_WscAssocReq[] = { @@ -7862,7 +7911,7 @@ uint32_t dot11f_unpack_ie_wsc_assoc_req(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_wsc_assoc_req. */ -#define SigIeWscAssocReq (0x0076) +#define SigIeWscAssocReq (0x0077) static const tTLVDefn TLVS_WscAssocRes[] = { @@ -7894,7 +7943,7 @@ uint32_t dot11f_unpack_ie_wsc_assoc_res(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_wsc_assoc_res. */ -#define SigIeWscAssocRes (0x0077) +#define SigIeWscAssocRes (0x0078) static const tTLVDefn TLVS_WscBeacon[] = { @@ -7947,7 +7996,7 @@ uint32_t dot11f_unpack_ie_wsc_beacon(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_wsc_beacon. */ -#define SigIeWscBeacon (0x0078) +#define SigIeWscBeacon (0x0079) static const tTLVDefn TLVS_WscBeaconProbeRes[] = { @@ -8025,7 +8074,7 @@ uint32_t dot11f_unpack_ie_wsc_beacon_probe_res(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_wsc_beacon_probe_res. */ -#define SigIeWscBeaconProbeRes (0x0079) +#define SigIeWscBeaconProbeRes (0x007a) uint32_t dot11f_unpack_ie_wsc_ie_opaque(tpAniSirGlobal pCtx, @@ -8050,7 +8099,7 @@ uint32_t dot11f_unpack_ie_wsc_ie_opaque(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_wsc_ie_opaque. */ -#define SigIeWscIEOpaque (0x007a) +#define SigIeWscIEOpaque (0x007b) static const tTLVDefn TLVS_WscProbeReq[] = { @@ -8123,7 +8172,7 @@ uint32_t dot11f_unpack_ie_wsc_probe_req(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_wsc_probe_req. */ -#define SigIeWscProbeReq (0x007b) +#define SigIeWscProbeReq (0x007c) static const tTLVDefn TLVS_WscProbeRes[] = { @@ -8201,7 +8250,7 @@ uint32_t dot11f_unpack_ie_wsc_probe_res(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_wsc_probe_res. */ -#define SigIeWscProbeRes (0x007c) +#define SigIeWscProbeRes (0x007d) static const tTLVDefn TLVS_WscReassocRes[] = { @@ -8233,7 +8282,7 @@ uint32_t dot11f_unpack_ie_wsc_reassoc_res(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_wsc_reassoc_res. */ -#define SigIeWscReassocRes (0x007d) +#define SigIeWscReassocRes (0x007e) uint32_t dot11f_unpack_ie_addba_extn_element(tpAniSirGlobal pCtx, @@ -8261,7 +8310,7 @@ uint32_t dot11f_unpack_ie_addba_extn_element(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_addba_extn_element. */ -#define SigIeaddba_extn_element (0x007e) +#define SigIeaddba_extn_element (0x007f) uint32_t dot11f_unpack_ie_bss_color_change(tpAniSirGlobal pCtx, @@ -8296,7 +8345,7 @@ uint32_t dot11f_unpack_ie_bss_color_change(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_bss_color_change. */ -#define SigIebss_color_change (0x007f) +#define SigIebss_color_change (0x0080) uint32_t dot11f_unpack_ie_dh_parameter_element(tpAniSirGlobal pCtx, @@ -8324,7 +8373,7 @@ uint32_t dot11f_unpack_ie_dh_parameter_element(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_dh_parameter_element. */ -#define SigIedh_parameter_element (0x0080) +#define SigIedh_parameter_element (0x0081) uint32_t dot11f_unpack_ie_esp_information(tpAniSirGlobal pCtx, @@ -8336,7 +8385,7 @@ uint32_t dot11f_unpack_ie_esp_information(tpAniSirGlobal pCtx, uint32_t status = DOT11F_PARSE_SUCCESS; (void) pBuf; (void)ielen; /* Shutup the compiler */ if (pDst->present) - status = DOT11F_DUPLICATE_IE; + return DOT11F_DUPLICATE_IE; pDst->present = 1; pDst->num_data = (uint8_t)(ielen); if (ielen > 96) { @@ -8349,7 +8398,7 @@ uint32_t dot11f_unpack_ie_esp_information(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_esp_information. */ -#define SigIeesp_information (0x0081) +#define SigIeesp_information (0x0082) uint32_t dot11f_unpack_ie_ext_chan_switch_ann(tpAniSirGlobal pCtx, @@ -8361,7 +8410,7 @@ uint32_t dot11f_unpack_ie_ext_chan_switch_ann(tpAniSirGlobal pCtx, uint32_t status = DOT11F_PARSE_SUCCESS; (void) pBuf; (void)ielen; /* Shutup the compiler */ if (pDst->present) - status = DOT11F_DUPLICATE_IE; + return DOT11F_DUPLICATE_IE; pDst->present = 1; if (unlikely(ielen < 1)) { pDst->present = 0; @@ -8397,7 +8446,7 @@ uint32_t dot11f_unpack_ie_ext_chan_switch_ann(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_ext_chan_switch_ann. */ -#define SigIeext_chan_switch_ann (0x0082) +#define SigIeext_chan_switch_ann (0x0083) uint32_t dot11f_unpack_ie_fils_assoc_delay_info(tpAniSirGlobal pCtx, @@ -8409,7 +8458,7 @@ uint32_t dot11f_unpack_ie_fils_assoc_delay_info(tpAniSirGlobal pCtx, uint32_t status = DOT11F_PARSE_SUCCESS; (void) pBuf; (void)ielen; /* Shutup the compiler */ if (pDst->present) - status = DOT11F_DUPLICATE_IE; + return DOT11F_DUPLICATE_IE; pDst->present = 1; if (unlikely(ielen < 1)) { pDst->present = 0; @@ -8421,7 +8470,7 @@ uint32_t dot11f_unpack_ie_fils_assoc_delay_info(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_fils_assoc_delay_info. */ -#define SigIefils_assoc_delay_info (0x0083) +#define SigIefils_assoc_delay_info (0x0084) uint32_t dot11f_unpack_ie_fils_hlp_container(tpAniSirGlobal pCtx, @@ -8457,7 +8506,7 @@ uint32_t dot11f_unpack_ie_fils_hlp_container(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_fils_hlp_container. */ -#define SigIefils_hlp_container (0x0084) +#define SigIefils_hlp_container (0x0085) uint32_t dot11f_unpack_ie_fils_indication(tpAniSirGlobal pCtx, @@ -8495,7 +8544,7 @@ uint32_t dot11f_unpack_ie_fils_indication(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_fils_indication. */ -#define SigIefils_indication (0x0085) +#define SigIefils_indication (0x0086) uint32_t dot11f_unpack_ie_fils_kde(tpAniSirGlobal pCtx, @@ -8523,7 +8572,7 @@ uint32_t dot11f_unpack_ie_fils_kde(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_fils_kde. */ -#define SigIefils_kde (0x0086) +#define SigIefils_kde (0x0087) uint32_t dot11f_unpack_ie_fils_key_confirmation(tpAniSirGlobal pCtx, @@ -8543,7 +8592,7 @@ uint32_t dot11f_unpack_ie_fils_key_confirmation(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_fils_key_confirmation. */ -#define SigIefils_key_confirmation (0x0087) +#define SigIefils_key_confirmation (0x0088) uint32_t dot11f_unpack_ie_fils_nonce(tpAniSirGlobal pCtx, @@ -8567,7 +8616,7 @@ uint32_t dot11f_unpack_ie_fils_nonce(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_fils_nonce. */ -#define SigIefils_nonce (0x0088) +#define SigIefils_nonce (0x0089) uint32_t dot11f_unpack_ie_fils_public_key(tpAniSirGlobal pCtx, @@ -8595,7 +8644,7 @@ uint32_t dot11f_unpack_ie_fils_public_key(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_fils_public_key. */ -#define SigIefils_public_key (0x0089) +#define SigIefils_public_key (0x008a) uint32_t dot11f_unpack_ie_fils_session(tpAniSirGlobal pCtx, @@ -8619,7 +8668,7 @@ uint32_t dot11f_unpack_ie_fils_session(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_fils_session. */ -#define SigIefils_session (0x008a) +#define SigIefils_session (0x008b) uint32_t dot11f_unpack_ie_fils_wrapped_data(tpAniSirGlobal pCtx, @@ -8639,7 +8688,7 @@ uint32_t dot11f_unpack_ie_fils_wrapped_data(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_fils_wrapped_data. */ -#define SigIefils_wrapped_data (0x008b) +#define SigIefils_wrapped_data (0x008c) uint32_t dot11f_unpack_ie_fragment_ie(tpAniSirGlobal pCtx, @@ -8659,7 +8708,7 @@ uint32_t dot11f_unpack_ie_fragment_ie(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_fragment_ie. */ -#define SigIefragment_ie (0x008c) +#define SigIefragment_ie (0x008d) uint32_t dot11f_unpack_ie_he_cap(tpAniSirGlobal pCtx, @@ -8676,7 +8725,7 @@ uint32_t dot11f_unpack_ie_he_cap(tpAniSirGlobal pCtx, uint8_t tmp81__; (void) pBuf; (void)ielen; /* Shutup the compiler */ if (pDst->present) - status = DOT11F_DUPLICATE_IE; + return DOT11F_DUPLICATE_IE; pDst->present = 1; if (unlikely(ielen < 4)) { pDst->present = 0; @@ -8883,7 +8932,7 @@ uint32_t dot11f_unpack_ie_he_cap(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_he_cap. */ -#define SigIehe_cap (0x008d) +#define SigIehe_cap (0x008e) uint32_t dot11f_unpack_ie_he_op(tpAniSirGlobal pCtx, @@ -8896,7 +8945,7 @@ uint32_t dot11f_unpack_ie_he_op(tpAniSirGlobal pCtx, uint32_t tmp82__; (void) pBuf; (void)ielen; /* Shutup the compiler */ if (pDst->present) - status = DOT11F_DUPLICATE_IE; + return DOT11F_DUPLICATE_IE; pDst->present = 1; if (unlikely(ielen < 4)) { pDst->present = 0; @@ -8969,7 +9018,7 @@ uint32_t dot11f_unpack_ie_he_op(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_he_op. */ -#define SigIehe_op (0x008e) +#define SigIehe_op (0x008f) uint32_t dot11f_unpack_ie_hs20vendor_ie(tpAniSirGlobal pCtx, @@ -9026,7 +9075,7 @@ uint32_t dot11f_unpack_ie_hs20vendor_ie(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_hs20vendor_ie. */ -#define SigIehs20vendor_ie (0x008f) +#define SigIehs20vendor_ie (0x0090) uint32_t dot11f_unpack_ie_ht2040_bss_coexistence(tpAniSirGlobal pCtx, @@ -9057,7 +9106,7 @@ uint32_t dot11f_unpack_ie_ht2040_bss_coexistence(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_ht2040_bss_coexistence. */ -#define SigIeht2040_bss_coexistence (0x0090) +#define SigIeht2040_bss_coexistence (0x0091) uint32_t dot11f_unpack_ie_ht2040_bss_intolerant_report(tpAniSirGlobal pCtx, @@ -9090,7 +9139,7 @@ uint32_t dot11f_unpack_ie_ht2040_bss_intolerant_report(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_ht2040_bss_intolerant_report. */ -#define SigIeht2040_bss_intolerant_report (0x0091) +#define SigIeht2040_bss_intolerant_report (0x0092) uint32_t dot11f_unpack_ie_mu_edca_param_set(tpAniSirGlobal pCtx, @@ -9110,7 +9159,7 @@ uint32_t dot11f_unpack_ie_mu_edca_param_set(tpAniSirGlobal pCtx, uint8_t tmp92__; (void) pBuf; (void)ielen; /* Shutup the compiler */ if (pDst->present) - status = DOT11F_DUPLICATE_IE; + return DOT11F_DUPLICATE_IE; pDst->present = 1; if (unlikely(ielen < 1)) { pDst->present = 0; @@ -9242,7 +9291,7 @@ uint32_t dot11f_unpack_ie_mu_edca_param_set(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_mu_edca_param_set. */ -#define SigIemu_edca_param_set (0x0092) +#define SigIemu_edca_param_set (0x0093) uint32_t dot11f_unpack_ie_osen_ie(tpAniSirGlobal pCtx, @@ -9262,7 +9311,7 @@ uint32_t dot11f_unpack_ie_osen_ie(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_osen_ie. */ -#define SigIeosen_ie (0x0093) +#define SigIeosen_ie (0x0094) uint32_t dot11f_unpack_ie_roaming_consortium_sel(tpAniSirGlobal pCtx, @@ -9274,7 +9323,7 @@ uint32_t dot11f_unpack_ie_roaming_consortium_sel(tpAniSirGlobal pCtx, uint32_t status = DOT11F_PARSE_SUCCESS; (void) pBuf; (void)ielen; /* Shutup the compiler */ if (pDst->present) - status = DOT11F_DUPLICATE_IE; + return DOT11F_DUPLICATE_IE; pDst->present = 1; pDst->num_data = (uint8_t)(ielen); DOT11F_MEMCPY(pCtx, pDst->data, pBuf, (ielen)); @@ -9282,7 +9331,7 @@ uint32_t dot11f_unpack_ie_roaming_consortium_sel(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_roaming_consortium_sel. */ -#define SigIeroaming_consortium_sel (0x0094) +#define SigIeroaming_consortium_sel (0x0095) uint32_t dot11f_unpack_ie_sec_chan_offset_ele(tpAniSirGlobal pCtx, @@ -9306,7 +9355,7 @@ uint32_t dot11f_unpack_ie_sec_chan_offset_ele(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_sec_chan_offset_ele. */ -#define SigIesec_chan_offset_ele (0x0095) +#define SigIesec_chan_offset_ele (0x0096) static const tFFDefn FFS_vendor_vht_ie[] = { @@ -9355,7 +9404,7 @@ uint32_t dot11f_unpack_ie_vendor_vht_ie(tpAniSirGlobal pCtx, return status; } /* End dot11f_unpack_ie_vendor_vht_ie. */ -#define SigIevendor_vht_ie (0x0096) +#define SigIevendor_vht_ie (0x0097) static const tFFDefn FFS_AddTSRequest[] = { @@ -9523,6 +9572,9 @@ static const tIEDefn IES_AssocRequest[] = { offsetof(tDot11fIEMobilityDomain, present), 0, "MobilityDomain", 0, 5, 5, SigIeMobilityDomain, {0, 0, 0, 0, 0}, 0, DOT11F_EID_MOBILITYDOMAIN, 0, 0, }, + { offsetof(tDot11fAssocRequest, FTInfo), offsetof(tDot11fIEFTInfo, + present), 0, "FTInfo", 0, 84, 222, SigIeFTInfo, {0, 0, 0, 0, 0}, + 0, DOT11F_EID_FTINFO, 0, 0, }, { offsetof(tDot11fAssocRequest, SuppOperatingClasses), offsetof(tDot11fIESuppOperatingClasses, present), 0, "SuppOperatingClasses", 0, 3, 34, SigIeSuppOperatingClasses, @@ -11243,6 +11295,10 @@ static const tIEDefn IES_RadioMeasurementReport[] = { offsetof(tDot11fRadioMeasurementReport, num_MeasurementReport), "MeasurementReport", 4, 5, 31, SigIeMeasurementReport, {0, 0, 0, 0, 0}, 0, DOT11F_EID_MEASUREMENTREPORT, 0, 1, }, + { offsetof(tDot11fRadioMeasurementReport, BeaconReportStatus), + offsetof(tDot11fIEBeaconReportStatus, present), 0, "BeaconReportStatus", + 0, 10, 10, SigIeBeaconReportStatus, {0, 0, 15, 34, 0}, + 4, DOT11F_EID_BEACONREPORTSTATUS, 0, 0, }, {0, 0, 0, NULL, 0, 0, 0, 0, {0, 0, 0, 0, 0}, 0, 0xff, 0, },}; uint32_t dot11f_unpack_radio_measurement_report(tpAniSirGlobal pCtx, @@ -13322,6 +13378,16 @@ static uint32_t unpack_core(tpAniSirGlobal pCtx, countOffset), append_ie); break; + case SigIeBeaconReportStatus: + status |= + dot11f_unpack_ie_BeaconReportStatus( + pCtx, pBufRemaining, len, + (tDot11fIEBeaconReportStatus *) + (pFrm + pIe->offset + + sizeof(tDot11fIEBeaconReportStatus) * + countOffset), + append_ie); + break; case SigIeCFParams: status |= dot11f_unpack_ie_cf_params( @@ -15743,8 +15809,6 @@ uint32_t dot11f_get_packed_ie_he_op(tpAniSirGlobal pCtx, *pnNeeded += 1; break; } - } else { - break; } if (pIe->mbssid_ap) { switch (pIe->mbssid_ap) { @@ -15752,8 +15816,6 @@ uint32_t dot11f_get_packed_ie_he_op(tpAniSirGlobal pCtx, *pnNeeded += 1; break; } - } else { - break; } break; } @@ -16635,6 +16697,13 @@ static uint32_t get_packed_size_core(tpAniSirGlobal pCtx, (pFrm + pIe->offset + offset * i))-> present; break; + case SigIeBeaconReportStatus: + offset = sizeof(tDot11fIEBeaconReportStatus); + byteCount = 4; + pIePresent = ((tDot11fIEBeaconReportStatus *) + (pFrm + pIe->offset + offset * i))-> + present; + break; case SigIeCFParams: offset = sizeof(tDot11fIECFParams); byteCount = 6; @@ -21453,6 +21522,52 @@ uint32_t dot11f_pack_ie_aid(tpAniSirGlobal pCtx, return DOT11F_PARSE_SUCCESS; } /* End dot11f_pack_ie_aid. */ +uint32_t dot11f_pack_ie_BeaconReportStatus(tpAniSirGlobal pCtx, + tDot11fIEBeaconReportStatus *pSrc, + uint8_t *pBuf, + uint32_t nBuf, + uint32_t *pnConsumed) +{ + uint8_t *pIeLen = 0; + uint32_t nConsumedOnEntry = *pnConsumed; + uint32_t nNeeded = 0U; + nNeeded += 4; + while (pSrc->present) { + if (nNeeded > nBuf) + return DOT11F_BUFFER_OVERFLOW; + *pBuf = 221; + ++pBuf; ++(*pnConsumed); + pIeLen = pBuf; + ++pBuf; ++(*pnConsumed); + *pBuf = 0x0; + ++pBuf; ++(*pnConsumed); + *pBuf = 0x0; + ++pBuf; ++(*pnConsumed); + *pBuf = 0xf; + ++pBuf; ++(*pnConsumed); + *pBuf = 0x22; + ++pBuf; ++(*pnConsumed); + *pBuf = pSrc->sub_type; + *pnConsumed += 1; + pBuf += 1; + *pBuf = pSrc->version; + *pnConsumed += 1; + pBuf += 1; + *pBuf = pSrc->length; + *pnConsumed += 1; + pBuf += 1; + *pBuf = pSrc->reason_code; + *pnConsumed += 1; + /* fieldsEndFlag = 1 */ + break; + } + (void)pCtx; + if (pIeLen) { + *pIeLen = *pnConsumed - nConsumedOnEntry - 2; + } + return DOT11F_PARSE_SUCCESS; +} /* End dot11f_pack_ie_BeaconReportStatus. */ + uint32_t dot11f_pack_ie_cf_params(tpAniSirGlobal pCtx, tDot11fIECFParams *pSrc, uint8_t *pBuf, @@ -26292,8 +26407,6 @@ uint32_t dot11f_pack_ie_he_op(tpAniSirGlobal pCtx, pBuf += 1; break; } - } else { - break; } if (pSrc->mbssid_ap) { switch (pSrc->mbssid_ap) { @@ -26303,8 +26416,6 @@ uint32_t dot11f_pack_ie_he_op(tpAniSirGlobal pCtx, /* fieldsEndFlag = 1 */ break; } - } else { - break; } break; } @@ -28070,6 +28181,14 @@ static uint32_t pack_core(tpAniSirGlobal pCtx, sizeof(tDot11fIEAID) * i), pBufRemaining, nBufRemaining, &len); break; + case SigIeBeaconReportStatus: + status |= + dot11f_pack_ie_BeaconReportStatus( + pCtx, (tDot11fIEBeaconReportStatus *) + (pSrc + pIe->offset + + sizeof(tDot11fIEBeaconReportStatus) * i), + pBufRemaining, nBufRemaining, &len); + break; case SigIeCFParams: status |= dot11f_pack_ie_cf_params( diff --git a/drivers/staging/qcacld-3.0/core/mac/src/sys/legacy/src/utils/src/mac_trace.c b/drivers/staging/qcacld-3.0/core/mac/src/sys/legacy/src/utils/src/mac_trace.c index 2a5e4e73794d..b1fa5fb63435 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/sys/legacy/src/utils/src/mac_trace.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/sys/legacy/src/utils/src/mac_trace.c @@ -364,6 +364,7 @@ uint8_t *mac_trace_get_sme_msg_string(uint16_t sme_msg) CASE_RETURN_STRING(eWNI_SME_SET_ANTENNA_MODE_RESP); CASE_RETURN_STRING(eWNI_SME_TSF_EVENT); CASE_RETURN_STRING(eWNI_SME_MON_INIT_SESSION); + CASE_RETURN_STRING(eWNI_SME_MON_DEINIT_SESSION); CASE_RETURN_STRING(eWNI_SME_PDEV_SET_HT_VHT_IE); CASE_RETURN_STRING(eWNI_SME_SET_VDEV_IES_PER_BAND); CASE_RETURN_STRING(eWNI_SME_SEND_DISASSOC_FRAME); @@ -421,8 +422,6 @@ uint8_t *mac_trace_get_wma_msg_string(uint16_t wma_msg) CASE_RETURN_STRING(WMA_CHNL_SWITCH_REQ); CASE_RETURN_STRING(WMA_ADD_TS_REQ); CASE_RETURN_STRING(WMA_DEL_TS_REQ); - CASE_RETURN_STRING(WMA_EXIT_PS_REQ); - CASE_RETURN_STRING(WMA_ENTER_PS_REQ); CASE_RETURN_STRING(WMA_MISSED_BEACON_IND); CASE_RETURN_STRING(WMA_SWITCH_CHANNEL_RSP); @@ -483,6 +482,7 @@ uint8_t *mac_trace_get_wma_msg_string(uint16_t wma_msg) CASE_RETURN_STRING(WMA_AGGR_QOS_REQ); CASE_RETURN_STRING(WMA_AGGR_QOS_RSP); CASE_RETURN_STRING(WMA_ROAM_SCAN_OFFLOAD_REQ); + CASE_RETURN_STRING(WMA_ROAM_PRE_AUTH_STATUS); #ifdef WLAN_FEATURE_PACKET_FILTERING CASE_RETURN_STRING(WMA_8023_MULTICAST_LIST_REQ); CASE_RETURN_STRING(WMA_RECEIVE_FILTER_SET_FILTER_REQ); @@ -580,6 +580,7 @@ uint8_t *mac_trace_get_wma_msg_string(uint16_t wma_msg) #ifdef WLAN_FEATURE_11W CASE_RETURN_STRING(WMA_EXCLUDE_UNENCRYPTED_IND); #endif + CASE_RETURN_STRING(WMA_ROAM_SYNC_TIMEOUT); CASE_RETURN_STRING(WMA_SET_MAX_TX_POWER_RSP); CASE_RETURN_STRING(WMA_SET_DTIM_PERIOD); CASE_RETURN_STRING(WMA_SET_MAX_TX_POWER_PER_BAND_REQ); diff --git a/drivers/staging/qcacld-3.0/core/mac/src/sys/legacy/src/utils/src/parser_api.c b/drivers/staging/qcacld-3.0/core/mac/src/sys/legacy/src/utils/src/parser_api.c index 7cd5b53d927f..d8cac206e072 100644 --- a/drivers/staging/qcacld-3.0/core/mac/src/sys/legacy/src/utils/src/parser_api.c +++ b/drivers/staging/qcacld-3.0/core/mac/src/sys/legacy/src/utils/src/parser_api.c @@ -127,15 +127,14 @@ int find_ie_location(tpAniSirGlobal pMac, tpSirRSNie pRsnIe, uint8_t EID) bytesLeft = pRsnIe->length; while (1) { - if (EID == pRsnIe->rsnIEdata[idx]) { + if (EID == pRsnIe->rsnIEdata[idx]) /* Found it */ return idx; - } else if (EID != pRsnIe->rsnIEdata[idx] && - /* & if no more IE, */ - bytesLeft <= (uint16_t) (ieLen)) { - pe_debug("No IE (%d) in find_ie_location", EID); + if (EID != pRsnIe->rsnIEdata[idx] && + /* & if no more IE, */ + bytesLeft <= (uint16_t) (ieLen)) return ret_val; - } + bytesLeft -= ieLen; ieLen = pRsnIe->rsnIEdata[idx + 1] + 2; idx += ieLen; @@ -675,8 +674,6 @@ populate_dot11f_ht_caps(tpAniSirGlobal pMac, if (psessionEntry) { disable_high_ht_mcs_2x2 = pMac->roam.configParam.disable_high_ht_mcs_2x2; - pe_debug("disable HT high MCS INI param[%d]", - disable_high_ht_mcs_2x2); if (psessionEntry->nss == NSS_1x1_MODE) { pDot11f->supportedMCSSet[1] = 0; } else if (IS_24G_CH(psessionEntry->currentOperChannel) && @@ -851,18 +848,15 @@ static void lim_log_qos_map_set(tpAniSirGlobal pMac, tSirQosMapSet *pQosMapSet) pe_debug("num of dscp exceptions: %d", pQosMapSet->num_dscp_exceptions); - for (i = 0; i < pQosMapSet->num_dscp_exceptions; i++) { - pe_debug("dscp value: %d", - pQosMapSet->dscp_exceptions[i][0]); - pe_debug("User priority value: %d", - pQosMapSet->dscp_exceptions[i][1]); - } - for (i = 0; i < 8; i++) { - pe_debug("dscp low for up %d: %d", i, - pQosMapSet->dscp_range[i][0]); - pe_debug("dscp high for up %d: %d", i, - pQosMapSet->dscp_range[i][1]); - } + for (i = 0; i < pQosMapSet->num_dscp_exceptions; i++) + pe_nofl_debug("dscp value: %d, User priority value: %d", + pQosMapSet->dscp_exceptions[i][0], + pQosMapSet->dscp_exceptions[i][1]); + + for (i = 0; i < 8; i++) + pe_nofl_debug("For up %d: dscp low: %d, dscp high: %d", i, + pQosMapSet->dscp_range[i][0], + pQosMapSet->dscp_range[i][1]); } QDF_STATUS @@ -1174,13 +1168,10 @@ populate_dot11f_ext_cap(tpAniSirGlobal pMac, pe_debug("11MC support enabled"); pDot11f->num_bytes = DOT11F_IE_EXTCAP_MAX_LEN; } else { - if (eLIM_AP_ROLE != psessionEntry->limSystemRole) { - pe_debug("11MC support enabled"); + if (eLIM_AP_ROLE != psessionEntry->limSystemRole) pDot11f->num_bytes = DOT11F_IE_EXTCAP_MAX_LEN; - } else { - pe_debug("11MC support disabled"); + else pDot11f->num_bytes = DOT11F_IE_EXTCAP_MIN_LEN; - } } p_ext_cap = (struct s_ext_cap *)pDot11f->bytes; @@ -2984,6 +2975,108 @@ static inline void fils_convert_assoc_rsp_frame2_struct(tDot11fAssocResponse { } #endif +QDF_STATUS wlan_parse_ftie_sha384(uint8_t *frame, uint32_t frame_len, + struct sSirAssocRsp *assoc_rsp) +{ + const uint8_t *ie, *ie_end, *pos; + uint8_t ie_len; + struct wlan_sha384_ftinfo_subelem *ft_subelem; + + ie = wlan_get_ie_ptr_from_eid(DOT11F_EID_FTINFO, frame, frame_len); + if (!ie) { + pe_err("FT IE not present"); + return QDF_STATUS_E_FAILURE; + } + + if (!ie[1]) { + pe_err("FT IE length is zero"); + return QDF_STATUS_E_FAILURE; + } + + ie_len = ie[1]; + if (ie_len < sizeof(struct wlan_sha384_ftinfo)) { + pe_err("Invalid FTIE len:%d", ie_len); + return QDF_STATUS_E_FAILURE; + } + + pos = ie + 2; + qdf_mem_copy(&assoc_rsp->sha384_ft_info, pos, + sizeof(struct wlan_sha384_ftinfo)); + ie_end = ie + ie_len; + pos += sizeof(struct wlan_sha384_ftinfo); + ft_subelem = &assoc_rsp->sha384_ft_subelem; + qdf_mem_zero(ft_subelem, sizeof(*ft_subelem)); + + while (ie_end - pos >= 2) { + uint8_t id, len; + + id = *pos++; + len = *pos++; + if (len < 1) { + pe_err("Invalid FT subelem length"); + return QDF_STATUS_E_FAILURE; + } + + switch (id) { + case FTIE_SUBELEM_R1KH_ID: + if (len != FTIE_R1KH_LEN) { + pe_err("Invalid R1KH-ID length: %d", len); + return QDF_STATUS_E_FAILURE; + } + ft_subelem->r1kh_id.present = 1; + qdf_mem_copy(ft_subelem->r1kh_id.PMK_R1_ID, + pos, FTIE_R1KH_LEN); + break; + case FTIE_SUBELEM_GTK: + if (ft_subelem->gtk) { + qdf_mem_zero(ft_subelem->gtk, + ft_subelem->gtk_len); + ft_subelem->gtk_len = 0; + qdf_mem_free(ft_subelem->gtk); + } + + ft_subelem->gtk = qdf_mem_malloc(len); + if (!ft_subelem->gtk) + return QDF_STATUS_E_NOMEM; + + qdf_mem_copy(ft_subelem->gtk, pos, len); + ft_subelem->gtk_len = len; + break; + case FTIE_SUBELEM_R0KH_ID: + if (len < 1 || len > FTIE_R0KH_MAX_LEN) { + pe_err("Invalid R0KH-ID length: %d", len); + return QDF_STATUS_E_FAILURE; + } + ft_subelem->r0kh_id.present = 1; + ft_subelem->r0kh_id.num_PMK_R0_ID = len; + qdf_mem_copy(ft_subelem->r0kh_id.PMK_R0_ID, + pos, len); + break; + case FTIE_SUBELEM_IGTK: + if (ft_subelem->igtk) { + qdf_mem_zero(ft_subelem->igtk, + ft_subelem->igtk_len); + ft_subelem->igtk_len = 0; + qdf_mem_free(ft_subelem->igtk); + } + ft_subelem->igtk = qdf_mem_malloc(len); + if (!ft_subelem->igtk) + return QDF_STATUS_E_NOMEM; + + qdf_mem_copy(ft_subelem->igtk, pos, len); + ft_subelem->igtk_len = len; + break; + default: + pe_debug("Unknown subelem id %d len:%d", + id, len); + break; + } + pos += len; + } + + return QDF_STATUS_SUCCESS; +} + QDF_STATUS sir_convert_assoc_resp_frame2_struct(tpAniSirGlobal pMac, tpPESession session_entry, @@ -3737,8 +3830,7 @@ sir_parse_beacon_ie(tpAniSirGlobal pMac, qdf_mem_free(pBies); return QDF_STATUS_E_FAILURE; } else if (DOT11F_WARNED(status)) { - pe_debug("There were warnings while unpacking Beacon IEs (0x%08x, %d bytes):", - status, nPayload); + pe_debug("warnings (0x%08x, %d bytes):", status, nPayload); } /* & "transliterate" from a 'tDot11fBeaconIEs' to a 'tSirProbeRespBeacon'... */ if (!pBies->SSID.present) { @@ -4383,6 +4475,69 @@ sir_convert_beacon_frame2_struct(tpAniSirGlobal pMac, } /* End sir_convert_beacon_frame2_struct. */ #ifdef WLAN_FEATURE_FILS_SK + +/* update_ftie_in_fils_conf() - API to update fils info from auth + * response packet from AP + * @auth: auth packet pointer received from AP + * @auth_frame: data structure needs to be updated + * + * Return: None + */ +static void +update_ftie_in_fils_conf(tDot11fAuthentication *auth, + tpSirMacAuthFrameBody auth_frame) +{ + /** + * Copy the FTIE sent by the AP in the auth request frame. + * This is required for FT-FILS connection. + * This FTIE will be sent in Assoc request frame without + * any modification. + */ + if (auth->FTInfo.present) { + pe_debug("FT-FILS: r0kh_len:%d r1kh_present:%d", + auth->FTInfo.R0KH_ID.num_PMK_R0_ID, + auth->FTInfo.R1KH_ID.present); + + auth_frame->ft_ie.present = 1; + if (auth->FTInfo.R1KH_ID.present) { + qdf_mem_copy(auth_frame->ft_ie.r1kh_id, + auth->FTInfo.R1KH_ID.PMK_R1_ID, + FT_R1KH_ID_LEN); + } + + if (auth->FTInfo.R0KH_ID.present) { + qdf_mem_copy(auth_frame->ft_ie.r0kh_id, + auth->FTInfo.R0KH_ID.PMK_R0_ID, + auth->FTInfo.R0KH_ID.num_PMK_R0_ID); + auth_frame->ft_ie.r0kh_id_len = + auth->FTInfo.R0KH_ID.num_PMK_R0_ID; + } + + if (auth_frame->ft_ie.gtk_ie.present) { + pe_debug("FT-FILS: GTK present"); + qdf_mem_copy(&auth_frame->ft_ie.gtk_ie, + &auth->FTInfo.GTK, + sizeof(struct mac_ft_gtk_ie)); + } + + if (auth_frame->ft_ie.igtk_ie.present) { + pe_debug("FT-FILS: IGTK present"); + qdf_mem_copy(&auth_frame->ft_ie.igtk_ie, + &auth->FTInfo.IGTK, + sizeof(struct mac_ft_igtk_ie)); + } + + qdf_mem_copy(auth_frame->ft_ie.anonce, auth->FTInfo.Anonce, + FT_NONCE_LEN); + qdf_mem_copy(auth_frame->ft_ie.snonce, auth->FTInfo.Snonce, + FT_NONCE_LEN); + + qdf_mem_copy(auth_frame->ft_ie.mic, auth->FTInfo.MIC, + FT_MIC_LEN); + auth_frame->ft_ie.element_count = auth->FTInfo.IECount; + } +} + /* sir_update_auth_frame2_struct_fils_conf: API to update fils info from auth * packet type 2 * @auth: auth packet pointer received from AP @@ -4390,8 +4545,9 @@ sir_convert_beacon_frame2_struct(tpAniSirGlobal pMac, * * Return: None */ -static void sir_update_auth_frame2_struct_fils_conf(tDot11fAuthentication *auth, - tpSirMacAuthFrameBody auth_frame) +static void +sir_update_auth_frame2_struct_fils_conf(tDot11fAuthentication *auth, + tpSirMacAuthFrameBody auth_frame) { if (auth->AuthAlgo.algo != SIR_FILS_SK_WITHOUT_PFS) return; @@ -4420,6 +4576,9 @@ static void sir_update_auth_frame2_struct_fils_conf(tDot11fAuthentication *auth, auth->RSNOpaque.num_data); auth_frame->rsn_ie.length = auth->RSNOpaque.num_data; } + + update_ftie_in_fils_conf(auth, auth_frame); + } #else static void sir_update_auth_frame2_struct_fils_conf(tDot11fAuthentication *auth, @@ -5993,13 +6152,54 @@ void populate_mdie(tpAniSirGlobal pMac, } -void populate_ft_info(tpAniSirGlobal pMac, tDot11fIEFTInfo *pDot11f) +#ifdef WLAN_FEATURE_FILS_SK +void populate_fils_ft_info(tpAniSirGlobal mac, tDot11fIEFTInfo *ft_info, + tpPESession pe_session) { - pDot11f->present = 1; - pDot11f->IECount = 0; /* TODO: put valid data during reassoc. */ - /* All other info is zero. */ + struct pe_fils_session *ft_fils_info = pe_session->fils_info; + + if (!ft_fils_info) + return; + + if (!ft_fils_info->ft_ie.present) { + ft_info->present = 0; + pe_err("FT IE doesn't exist"); + return; + } + ft_info->IECount = ft_fils_info->ft_ie.element_count; + + qdf_mem_copy(ft_info->MIC, ft_fils_info->ft_ie.mic, + FT_MIC_LEN); + + qdf_mem_copy(ft_info->Anonce, ft_fils_info->ft_ie.anonce, + FT_NONCE_LEN); + + qdf_mem_copy(ft_info->Snonce, ft_fils_info->ft_ie.snonce, + FT_NONCE_LEN); + + if (ft_fils_info->ft_ie.r0kh_id_len > 0) { + ft_info->R0KH_ID.present = 1; + qdf_mem_copy(ft_info->R0KH_ID.PMK_R0_ID, + ft_fils_info->ft_ie.r0kh_id, + ft_fils_info->ft_ie.r0kh_id_len); + ft_info->R0KH_ID.num_PMK_R0_ID = + ft_fils_info->ft_ie.r0kh_id_len; + } + + ft_info->R1KH_ID.present = 1; + qdf_mem_copy(ft_info->R1KH_ID.PMK_R1_ID, + ft_fils_info->ft_ie.r1kh_id, + FT_R1KH_ID_LEN); + + qdf_mem_copy(&ft_info->GTK, &ft_fils_info->ft_ie.gtk_ie, + sizeof(struct mac_ft_gtk_ie)); + qdf_mem_copy(&ft_info->IGTK, &ft_fils_info->ft_ie.igtk_ie, + sizeof(struct mac_ft_igtk_ie)); + + ft_info->present = 1; } +#endif void populate_dot11f_assoc_rsp_rates(tpAniSirGlobal pMac, tDot11fIESuppRates *pSupp, @@ -6337,8 +6537,6 @@ QDF_STATUS populate_dot11f_he_caps(tpAniSirGlobal mac_ctx, tpPESession session, he_cap->ppet.ppe_threshold.num_ppe_th = 0; } - lim_log_he_cap(mac_ctx, he_cap); - return QDF_STATUS_SUCCESS; } diff --git a/drivers/staging/qcacld-3.0/core/pld/inc/pld_common.h b/drivers/staging/qcacld-3.0/core/pld/inc/pld_common.h index 8f3a91fb6cc3..285ac6094c9c 100644 --- a/drivers/staging/qcacld-3.0/core/pld/inc/pld_common.h +++ b/drivers/staging/qcacld-3.0/core/pld/inc/pld_common.h @@ -279,6 +279,18 @@ enum pld_recovery_reason { PLD_REASON_LINK_DOWN }; +#ifdef FEATURE_WLAN_TIME_SYNC_FTM +/** + * enum pld_wlan_time_sync_trigger_type - WLAN time sync trigger type + * @PLD_TRIGGER_POSITIVE_EDGE: Positive edge trigger + * @PLD_TRIGGER_NEGATIVE_EDGE: Negative edge trigger + */ +enum pld_wlan_time_sync_trigger_type { + PLD_TRIGGER_POSITIVE_EDGE, + PLD_TRIGGER_NEGATIVE_EDGE +}; +#endif /* FEATURE_WLAN_TIME_SYNC_FTM */ + /** * struct pld_driver_ops - driver callback functions * @probe: required operation, will be called when device is detected @@ -360,6 +372,13 @@ void pld_is_pci_link_down(struct device *dev); int pld_shadow_control(struct device *dev, bool enable); void pld_schedule_recovery_work(struct device *dev, enum pld_recovery_reason reason); + +#ifdef FEATURE_WLAN_TIME_SYNC_FTM +int pld_get_audio_wlan_timestamp(struct device *dev, + enum pld_wlan_time_sync_trigger_type type, + uint64_t *ts); +#endif /* FEATURE_WLAN_TIME_SYNC_FTM */ + #ifdef CONFIG_CNSS_UTILS /** * pld_set_wlan_unsafe_channel() - Set unsafe channel diff --git a/drivers/staging/qcacld-3.0/core/pld/src/pld_common.c b/drivers/staging/qcacld-3.0/core/pld/src/pld_common.c index 801fa48a9119..b054dc8980d2 100644 --- a/drivers/staging/qcacld-3.0/core/pld/src/pld_common.c +++ b/drivers/staging/qcacld-3.0/core/pld/src/pld_common.c @@ -1657,3 +1657,39 @@ int pld_idle_restart(struct device *dev, return errno; } + +#ifdef FEATURE_WLAN_TIME_SYNC_FTM +/** + * pld_get_audio_wlan_timestamp() - Get audio timestamp + * @dev: device pointer + * @type: trigger type + * @ts: audio timestamp + * + * This API can be used to get audio timestamp. + * + * Return: 0 if trigger to get audio timestamp is successful + * Non zero failure code for errors + */ +int pld_get_audio_wlan_timestamp(struct device *dev, + enum pld_wlan_time_sync_trigger_type type, + uint64_t *ts) +{ + int ret = 0; + enum pld_bus_type bus_type; + + bus_type = pld_get_bus_type(dev); + switch (bus_type) { + case PLD_BUS_TYPE_SNOC: + ret = pld_snoc_get_audio_wlan_timestamp(dev, type, ts); + break; + case PLD_BUS_TYPE_PCIE: + case PLD_BUS_TYPE_SDIO: + case PLD_BUS_TYPE_USB: + break; + default: + ret = -EINVAL; + break; + } + return ret; +} +#endif /* FEATURE_WLAN_TIME_SYNC_FTM */ diff --git a/drivers/staging/qcacld-3.0/core/pld/src/pld_snoc.h b/drivers/staging/qcacld-3.0/core/pld/src/pld_snoc.h index 53084a06ed25..7728dafd8f45 100644 --- a/drivers/staging/qcacld-3.0/core/pld/src/pld_snoc.h +++ b/drivers/staging/qcacld-3.0/core/pld/src/pld_snoc.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -146,6 +146,17 @@ static inline int pld_snoc_is_fw_rejuvenate(void) { return 0; } + +#ifdef FEATURE_WLAN_TIME_SYNC_FTM +static inline int +pld_snoc_get_audio_wlan_timestamp(struct device *dev, + enum pld_wlan_time_sync_trigger_type type, + uint64_t *ts) +{ + return 0; +} +#endif /* FEATURE_WLAN_TIME_SYNC_FTM */ + #else int pld_snoc_register_driver(void); void pld_snoc_unregister_driver(void); @@ -155,6 +166,37 @@ int pld_snoc_wlan_enable(struct device *dev, int pld_snoc_wlan_disable(struct device *dev, enum pld_driver_mode mode); int pld_snoc_get_soc_info(struct device *dev, struct pld_soc_info *info); +#ifdef FEATURE_WLAN_TIME_SYNC_FTM +/** + * pld_snoc_get_audio_wlan_timestamp() - Get audio timestamp + * @dev: device + * @type: trigger type + * @ts: timestamp + * + * Return audio timestamp to the ts. + * + * Return: 0 for success + * Non zero failure code for errors + */ +static inline int +pld_snoc_get_audio_wlan_timestamp(struct device *dev, + enum pld_wlan_time_sync_trigger_type type, + uint64_t *ts) +{ + enum wlan_time_sync_trigger_type edge_type; + + if (!dev) + return -ENODEV; + + if (type == PLD_TRIGGER_POSITIVE_EDGE) + edge_type = CNSS_POSITIVE_EDGE_TRIGGER; + else + edge_type = CNSS_NEGATIVE_EDGE_TRIGGER; + + return cnss_get_audio_wlan_timestamp(dev, edge_type, ts); +} +#endif /* FEATURE_WLAN_TIME_SYNC_FTM */ + static inline int pld_snoc_ce_request_irq(struct device *dev, unsigned int ce_id, irqreturn_t (*handler)(int, void *), diff --git a/drivers/staging/qcacld-3.0/core/sap/inc/sap_api.h b/drivers/staging/qcacld-3.0/core/sap/inc/sap_api.h index 71547ad0111f..ff843173b84f 100644 --- a/drivers/staging/qcacld-3.0/core/sap/inc/sap_api.h +++ b/drivers/staging/qcacld-3.0/core/sap/inc/sap_api.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -50,6 +50,8 @@ extern "C" { #define MAX_ACL_MAC_ADDRESS 32 #define AUTO_CHANNEL_SELECT 0 #define MAX_ASSOC_IND_IE_LEN 255 +#define MAX_ASSOC_REQ_IE_LEN 2000 +#define ASSOC_REQ_IE_OFFSET 4 /* defines for WPS config states */ #define SAP_WPS_DISABLED 0 @@ -263,8 +265,8 @@ typedef struct sap_StationAssocReassocCompleteEvent_s { eStationType staType; uint8_t staId; uint8_t status; - uint8_t ies[MAX_ASSOC_IND_IE_LEN]; - uint16_t iesLen; + uint8_t *ies; + uint32_t ies_len; uint32_t statusCode; eSapAuthType SapAuthType; bool wmmEnabled; @@ -1543,6 +1545,17 @@ QDF_STATUS wlansap_filter_ch_based_acs(struct sap_context *sap_ctx, */ uint8_t wlansap_get_safe_channel_from_pcl_and_acs_range(struct sap_context *sap_ctx); + +/** + * sap_dump_acs_channel() - dump acs channel list + * @acs_cfg: acs config + * + * This function dump acs channel list + * + * Return: void. + */ +void sap_dump_acs_channel(struct sap_acs_cfg *acs_cfg); + #ifdef __cplusplus } #endif diff --git a/drivers/staging/qcacld-3.0/core/sap/src/sap_api_link_cntl.c b/drivers/staging/qcacld-3.0/core/sap/src/sap_api_link_cntl.c index df743766c120..599886787df8 100644 --- a/drivers/staging/qcacld-3.0/core/sap/src/sap_api_link_cntl.c +++ b/drivers/staging/qcacld-3.0/core/sap/src/sap_api_link_cntl.c @@ -253,8 +253,6 @@ QDF_STATUS wlansap_pre_start_bss_acs_scan_callback(tHalHandle hal_handle, sap_config_acs_result(hal_handle, sap_ctx, sap_ctx->acs_cfg->ht_sec_ch); - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO_HIGH, - FL("Channel selected = %d"), sap_ctx->channel); sap_ctx->sap_state = eSAP_ACS_CHANNEL_SELECTED; sap_ctx->sap_status = eSAP_STATUS_SUCCESS; close_session: @@ -298,9 +296,9 @@ wlansap_roam_process_ch_change_success(tpAniSirGlobal mac_ctx, * Channel change is successful. If the new channel is a DFS channel, * then we will to perform channel availability check for 60 seconds */ - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO_MED, - FL("sapdfs: changing target channel to [%d]"), - mac_ctx->sap.SapDfsInfo.target_channel); + sap_nofl_debug("sapdfs: SAP CSA: freq to [%d] state %d", + mac_ctx->sap.SapDfsInfo.target_channel, + sap_ctx->fsm_state); sap_ctx->channel = mac_ctx->sap.SapDfsInfo.target_channel; /* @@ -337,8 +335,6 @@ wlansap_roam_process_ch_change_success(tpAniSirGlobal mac_ctx, /* check if currently selected channel is a DFS channel */ if (is_ch_dfs && sap_ctx->pre_cac_complete) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO_MED, FL( - "sapdfs: SAP_STOPPING => SAP_STARTING, on pre cac")); /* Start beaconing on the new pre cac channel */ wlansap_start_beacon_req(sap_ctx); sap_ctx->fsm_state = SAP_STARTING; @@ -350,22 +346,17 @@ wlansap_roam_process_ch_change_success(tpAniSirGlobal mac_ctx, } else if (is_ch_dfs) { if ((false == mac_ctx->sap.SapDfsInfo.ignore_cac) && (eSAP_DFS_DO_NOT_SKIP_CAC == - mac_ctx->sap.SapDfsInfo.cac_state)) { + mac_ctx->sap.SapDfsInfo.cac_state) && + policy_mgr_get_dfs_master_dynamic_enabled( + mac_ctx->psoc, + sap_ctx->sessionId)) { sap_ctx->fsm_state = SAP_INIT; - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO_MED, - "%s: %d: sapdfs: from state SAP_STOPPING => DISCONNECTED with ignore cac false on sapctx[%pK]", - __func__, __LINE__, sap_ctx); /* DFS Channel */ sap_event.event = eSAP_DFS_CHANNEL_CAC_START; sap_event.params = csr_roam_info; sap_event.u1 = 0; sap_event.u2 = 0; } else { - QDF_TRACE(QDF_MODULE_ID_SAP, - QDF_TRACE_LEVEL_INFO_MED, - "%s: %d: sapdfs: from state SAP_STOPPING => SAP_STARTING with ignore cac true on sapctx[%pK]", - __func__, __LINE__, sap_ctx); - /* Start beaconing on the new channel */ wlansap_start_beacon_req(sap_ctx); sap_ctx->fsm_state = SAP_STARTING; @@ -376,9 +367,6 @@ wlansap_roam_process_ch_change_success(tpAniSirGlobal mac_ctx, sap_event.u2 = eCSR_ROAM_RESULT_INFRA_STARTED; } } else { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO_MED, - "%s: %d: sapdfs: from state SAP_STOPPING => SAP_STARTING on sapctx[%pK]", - __func__, __LINE__, sap_ctx); /* non-DFS channel */ sap_ctx->fsm_state = SAP_STARTING; mac_ctx->sap.SapDfsInfo.sap_radar_found_status = false; @@ -776,7 +764,6 @@ wlansap_roam_callback(void *ctx, struct csr_roam_info *csr_roam_info, tHalHandle hal; tpAniSirGlobal mac_ctx = NULL; uint8_t intf; - bool sta_sap_scc_on_dfs_chan; if (QDF_IS_STATUS_ERROR(wlansap_context_get(ctx))) return QDF_STATUS_E_FAILURE; @@ -795,9 +782,6 @@ wlansap_roam_callback(void *ctx, struct csr_roam_info *csr_roam_info, FL("roam_status = %d, roam_result = %d"), roam_status, roam_result); - sta_sap_scc_on_dfs_chan = - policy_mgr_is_sta_sap_scc_allowed_on_dfs_chan(mac_ctx->psoc); - switch (roam_status) { case eCSR_ROAM_INFRA_IND: QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO_HIGH, @@ -880,7 +864,8 @@ wlansap_roam_callback(void *ctx, struct csr_roam_info *csr_roam_info, "Received Radar Indication on sap ch %d, session %d", sap_ctx->channel, sap_ctx->sessionId); - if (sta_sap_scc_on_dfs_chan) { + if (!policy_mgr_get_dfs_master_dynamic_enabled( + mac_ctx->psoc, sap_ctx->sessionId)) { QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, FL("Ignore the Radar indication")); @@ -1184,7 +1169,8 @@ wlansap_roam_callback(void *ctx, struct csr_roam_info *csr_roam_info, break; case eCSR_ROAM_RESULT_DFS_RADAR_FOUND_IND: - if (sta_sap_scc_on_dfs_chan) + if (!policy_mgr_get_dfs_master_dynamic_enabled( + mac_ctx->psoc, sap_ctx->sessionId)) break; wlansap_roam_process_dfs_radar_found(mac_ctx, sap_ctx, &qdf_ret_status); diff --git a/drivers/staging/qcacld-3.0/core/sap/src/sap_ch_select.c b/drivers/staging/qcacld-3.0/core/sap/src/sap_ch_select.c index 5562e049dff1..ec8b0a544b75 100644 --- a/drivers/staging/qcacld-3.0/core/sap/src/sap_ch_select.c +++ b/drivers/staging/qcacld-3.0/core/sap/src/sap_ch_select.c @@ -468,9 +468,6 @@ static bool sap_chan_sel_init(tHalHandle halHandle, bool sta_sap_scc_on_dfs_chan = policy_mgr_is_sta_sap_scc_allowed_on_dfs_chan(pMac->psoc); - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO_HIGH, "In %s", - __func__); - pSpectInfoParams->numSpectChans = pMac->scan.base_channels.numChannels; @@ -632,8 +629,8 @@ uint32_t sapweight_rssi_count(struct sap_context *sap_ctx, int8_t rssi, rssicountWeight = rssiWeight + countWeight; QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO_HIGH, - "In %s, rssiWeight=%d, countWeight=%d, rssicountWeight=%d", - __func__, rssiWeight, countWeight, rssicountWeight); + "rssiWeight=%d, countWeight=%d, rssicountWeight=%d", + rssiWeight, countWeight, rssicountWeight); return rssicountWeight; } @@ -685,12 +682,8 @@ static uint32_t sap_weight_channel_noise_floor(struct sap_context *sap_ctx, ACS_WEIGHT_CFG_TO_LOCAL(sap_ctx->auto_channel_select_weight, softap_nf_weight_cfg); - if (channel_stat == NULL || channel_stat->channelfreq == 0) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, - "In %s, sanity check failed return max weight", - __func__); + if (channel_stat == NULL || channel_stat->channelfreq == 0) return softap_nf_weight_local; - } noise_floor_weight = (channel_stat->noise_floor == 0) ? 0 : (ACS_WEIGHT_COMPUTE( @@ -706,8 +699,8 @@ static uint32_t sap_weight_channel_noise_floor(struct sap_context *sap_ctx, noise_floor_weight = 0; QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO_HIGH, - "In %s, nf=%d, nfwc=%d, nfwl=%d, nfw=%d", - __func__, channel_stat->noise_floor, + "nf=%d, nfwc=%d, nfwl=%d, nfw=%d", + channel_stat->noise_floor, softap_nf_weight_cfg, softap_nf_weight_local, noise_floor_weight); @@ -739,12 +732,8 @@ static uint32_t sap_weight_channel_free(struct sap_context *sap_ctx, ACS_WEIGHT_CFG_TO_LOCAL(sap_ctx->auto_channel_select_weight, softap_channel_free_weight_cfg); - if (channel_stat == NULL || channel_stat->channelfreq == 0) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, - "In %s, sanity check failed return max weight", - __func__); + if (channel_stat == NULL || channel_stat->channelfreq == 0) return softap_channel_free_weight_local; - } rx_clear_count = channel_stat->rx_clear_count - channel_stat->tx_frame_count - @@ -766,8 +755,8 @@ static uint32_t sap_weight_channel_free(struct sap_context *sap_ctx, channel_free_weight = softap_channel_free_weight_local; QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO_HIGH, - "In %s, rcc=%d, cc=%d, tc=%d, rc=%d, cfwc=%d, cfwl=%d, cfw=%d", - __func__, rx_clear_count, cycle_count, + "rcc=%d, cc=%d, tc=%d, rc=%d, cfwc=%d, cfwl=%d, cfw=%d", + rx_clear_count, cycle_count, channel_stat->tx_frame_count, channel_stat->rx_frame_count, softap_channel_free_weight_cfg, @@ -800,12 +789,8 @@ static uint32_t sap_weight_channel_txpwr_range(struct sap_context *sap_ctx, ACS_WEIGHT_CFG_TO_LOCAL(sap_ctx->auto_channel_select_weight, softap_txpwr_range_weight_cfg); - if (channel_stat == NULL || channel_stat->channelfreq == 0) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, - "In %s, sanity check failed return max weight", - __func__); + if (channel_stat == NULL || channel_stat->channelfreq == 0) return softap_txpwr_range_weight_local; - } txpwr_weight_low_speed = (channel_stat->chan_tx_pwr_range == 0) ? 0 : (ACS_WEIGHT_COMPUTE( @@ -819,8 +804,8 @@ static uint32_t sap_weight_channel_txpwr_range(struct sap_context *sap_ctx, txpwr_weight_low_speed = softap_txpwr_range_weight_local; QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO_HIGH, - "In %s, tpr=%d, tprwc=%d, tprwl=%d, tprw=%d", - __func__, channel_stat->chan_tx_pwr_range, + "tpr=%d, tprwc=%d, tprwl=%d, tprw=%d", + channel_stat->chan_tx_pwr_range, softap_txpwr_range_weight_cfg, softap_txpwr_range_weight_local, txpwr_weight_low_speed); @@ -852,12 +837,8 @@ static uint32_t sap_weight_channel_txpwr_tput(struct sap_context *sap_ctx, ACS_WEIGHT_CFG_TO_LOCAL(sap_ctx->auto_channel_select_weight, softap_txpwr_tput_weight_cfg); - if (channel_stat == NULL || channel_stat->channelfreq == 0) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, - "In %s, sanity check failed return max weight", - __func__); + if (channel_stat == NULL || channel_stat->channelfreq == 0) return softap_txpwr_tput_weight_local; - } txpwr_weight_high_speed = (channel_stat->chan_tx_pwr_throughput == 0) ? 0 : (ACS_WEIGHT_COMPUTE( @@ -871,8 +852,8 @@ static uint32_t sap_weight_channel_txpwr_tput(struct sap_context *sap_ctx, txpwr_weight_high_speed = softap_txpwr_tput_weight_local; QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO_HIGH, - "In %s, tpt=%d, tptwc=%d, tptwl=%d, tptw=%d", - __func__, channel_stat->chan_tx_pwr_throughput, + "tpt=%d, tptwc=%d, tptwl=%d, tptw=%d", + channel_stat->chan_tx_pwr_throughput, softap_txpwr_tput_weight_cfg, softap_txpwr_tput_weight_local, txpwr_weight_high_speed); @@ -2438,8 +2419,6 @@ uint8_t sap_select_channel(tHalHandle hal, struct sap_context *sap_ctx, tpAniSirGlobal mac_ctx; mac_ctx = PMAC_STRUCT(hal); - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO_HIGH, - "In %s, Running SAP Ch Select", __func__); /* * If ACS weight is not enabled on noise_floor/channel_free/tx_power, diff --git a/drivers/staging/qcacld-3.0/core/sap/src/sap_fsm.c b/drivers/staging/qcacld-3.0/core/sap/src/sap_fsm.c index 30d1a0d1a1bb..fa178e9e2fad 100644 --- a/drivers/staging/qcacld-3.0/core/sap/src/sap_fsm.c +++ b/drivers/staging/qcacld-3.0/core/sap/src/sap_fsm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -302,9 +302,6 @@ static uint8_t sap_get_bonding_channels(struct sap_context *sapContext, else return 0; - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, - FL("cbmode: %d, channel: %d"), chanBondState, channel); - switch (chanBondState) { case PHY_SINGLE_CHANNEL_CENTERED: numChannel = 1; @@ -463,14 +460,14 @@ static void sap_get_cac_dur_dfs_region(struct sap_context *sap_ctx, *cac_duration_ms = DEFAULT_CAC_TIMEOUT; if (*dfs_region != DFS_ETSI_REG) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO, + QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, FL("sapdfs: default cac duration")); return; } if (sap_is_channel_bonding_etsi_weather_channel(sap_ctx)) { *cac_duration_ms = ETSI_WEATHER_CH_CAC_TIMEOUT; - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO, + QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, FL("sapdfs: bonding_etsi_weather_channel")); return; } @@ -480,7 +477,7 @@ static void sap_get_cac_dur_dfs_region(struct sap_context *sap_ctx, for (i = 0; i < num_channels; i++) { if (IS_ETSI_WEATHER_CH(channels[i])) { *cac_duration_ms = ETSI_WEATHER_CH_CAC_TIMEOUT; - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO, + QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, FL("sapdfs: ch=%d is etsi weather channel"), channels[i]); return; @@ -550,7 +547,7 @@ void sap_dfs_set_current_channel(void *ctx) if (wlan_reg_is_dfs_ch(pdev, sap_ctx->channel)) ic_flagext |= IEEE80211_CHAN_DFS; - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO, + QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, FL("freq=%d, channel=%d, seg0=%d, seg1=%d, flags=0x%x, ext flags=0x%x"), ic_freq, ic_ieee, vht_seg0, vht_seg1, ic_flags, ic_flagext); @@ -919,6 +916,9 @@ sap_validate_chan(struct sap_context *sap_context, "%s: Override ch %d to %d due to CC Intf", __func__, sap_context->channel, con_ch); sap_context->channel = con_ch; + if (WLAN_REG_IS_24GHZ_CH(con_ch)) + sap_context->ch_params.ch_width = + CH_WIDTH_20MHZ; wlan_reg_set_channel_params(mac_ctx->pdev, sap_context->channel, 0, &sap_context->ch_params); @@ -944,10 +944,6 @@ sap_validate_chan(struct sap_context *sap_context, #ifdef FEATURE_WLAN_MCC_TO_SCC_SWITCH if (sap_context->cc_switch_mode != QDF_MCC_TO_SCC_SWITCH_DISABLE) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO, - FL("check for overlap: chan:%d mode:%d"), - sap_context->channel, - sap_context->csr_roamProfile.phyMode); con_ch = sme_check_concurrent_channel_overlap(h_hal, sap_context->channel, sap_context->csr_roamProfile.phyMode, @@ -981,10 +977,13 @@ sap_validate_chan(struct sap_context *sap_context, (!wlan_reg_is_dfs_ch(mac_ctx->pdev, con_ch) || sta_sap_scc_on_dfs_chan)) { QDF_TRACE(QDF_MODULE_ID_SAP, - QDF_TRACE_LEVEL_ERROR, + QDF_TRACE_LEVEL_DEBUG, "%s: Override ch %d to %d due to CC Intf", __func__, sap_context->channel, con_ch); sap_context->channel = con_ch; + if (WLAN_REG_IS_24GHZ_CH(con_ch)) + sap_context->ch_params.ch_width = + CH_WIDTH_20MHZ; wlan_reg_set_channel_params(mac_ctx->pdev, sap_context->channel, 0, &sap_context->ch_params); @@ -1144,8 +1143,6 @@ QDF_STATUS sap_channel_sel(struct sap_context *sap_context) sap_context->channelList = channel_list; sap_context->num_of_channel = num_of_channels; /* Set requestType to Full scan */ - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO_HIGH, - FL("calling ucfg_scan_start")); #ifdef FEATURE_WLAN_AP_AP_ACS_OPTIMIZE if (sap_context->acs_cfg->skip_scan_status == eSAP_DO_NEW_ACS_SCAN) @@ -1178,10 +1175,6 @@ QDF_STATUS sap_channel_sel(struct sap_context *sap_context) qdf_ret_status = QDF_STATUS_E_FAILURE; goto release_vdev_ref; } else { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO_HIGH, - FL("return sme_ScanReq, scanID=%d, Ch=%d"), - scan_id, - sap_context->channel); host_log_acs_scan_start(scan_id, vdev_id); } #ifdef FEATURE_WLAN_AP_AP_ACS_OPTIMIZE @@ -1198,17 +1191,6 @@ QDF_STATUS sap_channel_sel(struct sap_context *sap_context) } #endif - /* - * If scan failed, get default channel and advance state - * machine as success with default channel - * - * Have to wait for the call back to be called to get the - * channel cannot advance state machine here as said above - */ - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO_HIGH, - FL("before exiting sap_channel_sel channel=%d"), - sap_context->channel); - qdf_ret_status = QDF_STATUS_SUCCESS; release_vdev_ref: @@ -1458,7 +1440,7 @@ QDF_STATUS sap_signal_hdd_event(struct sap_context *sap_ctx, switch (sap_hddevent) { case eSAP_STA_ASSOC_IND: if (!csr_roaminfo) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, + QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, FL("Invalid CSR Roam Info")); return QDF_STATUS_E_INVAL; } @@ -1548,7 +1530,7 @@ QDF_STATUS sap_signal_hdd_event(struct sap_context *sap_ctx, case eSAP_STA_REASSOC_EVENT: if (!csr_roaminfo) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, + QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, FL("Invalid CSR Roam Info")); return QDF_STATUS_E_INVAL; } @@ -1570,27 +1552,19 @@ QDF_STATUS sap_signal_hdd_event(struct sap_context *sap_ctx, &csr_roaminfo->peerMac); reassoc_complete->staId = csr_roaminfo->staId; reassoc_complete->statusCode = csr_roaminfo->statusCode; - reassoc_complete->iesLen = csr_roaminfo->rsnIELen; - qdf_mem_copy(reassoc_complete->ies, csr_roaminfo->prsnIE, - csr_roaminfo->rsnIELen); - -#ifdef FEATURE_WLAN_WAPI - if (csr_roaminfo->wapiIELen) { - uint8_t len = reassoc_complete->iesLen; - - reassoc_complete->iesLen += csr_roaminfo->wapiIELen; - qdf_mem_copy(&reassoc_complete->ies[len], - csr_roaminfo->pwapiIE, - csr_roaminfo->wapiIELen); + + if (csr_roaminfo->assocReqLength < ASSOC_REQ_IE_OFFSET) { + QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, + FL("Invalid assoc request length:%d"), + csr_roaminfo->assocReqLength); + return QDF_STATUS_E_INVAL; } -#endif - if (csr_roaminfo->addIELen) { - uint8_t len = reassoc_complete->iesLen; + reassoc_complete->ies_len = (csr_roaminfo->assocReqLength - + ASSOC_REQ_IE_OFFSET); + reassoc_complete->ies = (csr_roaminfo->assocReqPtr + + ASSOC_REQ_IE_OFFSET); - reassoc_complete->iesLen += csr_roaminfo->addIELen; - qdf_mem_copy(&reassoc_complete->ies[len], - csr_roaminfo->paddIE, - csr_roaminfo->addIELen); + if (csr_roaminfo->addIELen) { if (wlan_get_vendor_ie_ptr_from_oui( SIR_MAC_P2P_OUI, SIR_MAC_P2P_OUI_SIZE, csr_roaminfo->paddIE, csr_roaminfo->addIELen)) { @@ -1645,7 +1619,7 @@ QDF_STATUS sap_signal_hdd_event(struct sap_context *sap_ctx, case eSAP_STA_DISASSOC_EVENT: if (!csr_roaminfo) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, + QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, FL("Invalid CSR Roam Info")); return QDF_STATUS_E_INVAL; } @@ -1672,7 +1646,7 @@ QDF_STATUS sap_signal_hdd_event(struct sap_context *sap_ctx, case eSAP_STA_SET_KEY_EVENT: if (!csr_roaminfo) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, + QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, FL("Invalid CSR Roam Info")); return QDF_STATUS_E_INVAL; } @@ -1687,7 +1661,7 @@ QDF_STATUS sap_signal_hdd_event(struct sap_context *sap_ctx, case eSAP_STA_MIC_FAILURE_EVENT: if (!csr_roaminfo) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, + QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, FL("Invalid CSR Roam Info")); return QDF_STATUS_E_INVAL; } @@ -1718,7 +1692,7 @@ QDF_STATUS sap_signal_hdd_event(struct sap_context *sap_ctx, case eSAP_WPS_PBC_PROBE_REQ_EVENT: if (!csr_roaminfo) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, + QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, FL("Invalid CSR Roam Info")); return QDF_STATUS_E_INVAL; } @@ -1751,7 +1725,7 @@ QDF_STATUS sap_signal_hdd_event(struct sap_context *sap_ctx, case eSAP_MAX_ASSOC_EXCEEDED: if (!csr_roaminfo) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, + QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, FL("Invalid CSR Roam Info")); return QDF_STATUS_E_INVAL; } @@ -1787,7 +1761,7 @@ QDF_STATUS sap_signal_hdd_event(struct sap_context *sap_ctx, case eSAP_ECSA_CHANGE_CHAN_IND: if (!csr_roaminfo) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, + QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, FL("Invalid CSR Roam Info")); return QDF_STATUS_E_INVAL; } @@ -2015,6 +1989,7 @@ static QDF_STATUS sap_cac_end_notify(tHalHandle hHal, uint8_t intf; tpAniSirGlobal pMac = PMAC_STRUCT(hHal); QDF_STATUS qdf_status = QDF_STATUS_E_FAILURE; + uint8_t chan; /* * eSAP_DFS_CHANNEL_CAC_END: @@ -2036,8 +2011,8 @@ static QDF_STATUS sap_cac_end_notify(tHalHandle hHal, sap_context = pMac->sap.sapCtxList[intf].sap_context; /* Don't check CAC for non-dfs channel */ profile = &sap_context->csr_roamProfile; - if (!wlan_reg_is_dfs_ch(pMac->pdev, - profile->operationChannel)) + chan = profile->operationChannel; + if (!wlan_reg_chan_has_dfs_attribute(pMac->pdev, chan)) continue; /* If this is an end notification of a pre cac, the @@ -2469,8 +2444,7 @@ static QDF_STATUS sap_fsm_state_starting(struct sap_context *sap_ctx, * Transition from SAP_STARTING to SAP_STARTED * (both without substates) */ - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO_HIGH, - FL("from state channel = %d %s => %s ch_width %d"), + sap_debug("Chan %d %s => %s ch_width %d", sap_ctx->channel, "SAP_STARTING", "SAP_STARTED", sap_ctx->ch_params.ch_width); sap_ctx->fsm_state = SAP_STARTED; @@ -2479,13 +2453,6 @@ static QDF_STATUS sap_fsm_state_starting(struct sap_context *sap_ctx, qdf_status = sap_signal_hdd_event(sap_ctx, roam_info, eSAP_START_BSS_EVENT, (void *) eSAP_STATUS_SUCCESS); - - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO_HIGH, - FL("ap_ctx->ch_params.ch_width %d, channel %d"), - sap_ctx->ch_params.ch_width, - reg_get_channel_state(mac_ctx->pdev, - sap_ctx->channel)); - /* * The upper layers have been informed that AP is up and * running, however, the AP is still not beaconing, until @@ -2516,7 +2483,10 @@ static QDF_STATUS sap_fsm_state_starting(struct sap_context *sap_ctx, if ((false == sap_dfs_info->ignore_cac) && (eSAP_DFS_DO_NOT_SKIP_CAC == sap_dfs_info->cac_state) && - !sap_ctx->pre_cac_complete) { + !sap_ctx->pre_cac_complete && + policy_mgr_get_dfs_master_dynamic_enabled( + mac_ctx->psoc, + sap_ctx->sessionId)) { QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO_HIGH, FL("start cac timer")); @@ -2712,10 +2682,6 @@ sap_fsm_state_stopping(struct sap_context *sap_ctx, eSAP_STOP_BSS_EVENT, (void *)eSAP_STATUS_SUCCESS); } else if (msg == eWNI_SME_CHANNEL_CHANGE_REQ) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO_MED, - FL("sapdfs: Send channel change request on sapctx[%pK]"), - sap_ctx); - sap_get_cac_dur_dfs_region(sap_ctx, &sap_ctx->csr_roamProfile.cac_duration_ms, &sap_ctx->csr_roamProfile.dfs_regdomain); @@ -2725,9 +2691,6 @@ sap_fsm_state_stopping(struct sap_context *sap_ctx, */ qdf_status = wlansap_channel_change_request(sap_ctx, mac_ctx->sap.SapDfsInfo.target_channel); - - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO, - FL("Sending DFS eWNI_SME_CHANNEL_CHANGE_REQ")); } else if (msg == eWNI_SME_CHANNEL_CHANGE_RSP) { QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO, FL("in state %s, event msg %d result %d"), @@ -2782,9 +2745,7 @@ QDF_STATUS sap_fsm(struct sap_context *sap_ctx, ptWLAN_SAPEvent sap_event) mac_ctx = PMAC_STRUCT(hal); - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, - FL("sap_ctx=%pK, state_var=%d, msg=0x%x"), - sap_ctx, state_var, msg); + sap_debug("state=%d handle event=%d", state_var, msg); switch (state_var) { case SAP_INIT: @@ -3211,6 +3172,30 @@ QDF_STATUS sap_is_peer_mac_allowed(struct sap_context *sapContext, return QDF_STATUS_SUCCESS; } +void sap_dump_acs_channel(struct sap_acs_cfg *acs_cfg) +{ + uint32_t buf_len = 0, len = 0, i; + uint8_t *chan_buff = NULL; + + /* + * Buffer of (num channl * 5) + 1 to consider the 4 char freq + * and 1 space after it for each channel and 1 to end the string + * with NULL. + */ + buf_len = (acs_cfg->ch_list_count * 5) + 1; + chan_buff = qdf_mem_malloc(buf_len); + if (!chan_buff) + return; + + for (i = 0; i < acs_cfg->ch_list_count; i++) + len += qdf_scnprintf(chan_buff + len, buf_len - len, + " %d", acs_cfg->ch_list[i]); + + sap_nofl_debug("ACS freq list[%d]:%s", + acs_cfg->ch_list_count, chan_buff); + qdf_mem_free(chan_buff); +} + #ifdef SOFTAP_CHANNEL_RANGE /** * sap_get_channel_list() - get the list of channels @@ -3248,21 +3233,15 @@ static QDF_STATUS sap_get_channel_list(struct sap_context *sap_ctx, start_ch_num = sap_ctx->acs_cfg->start_ch; end_ch_num = sap_ctx->acs_cfg->end_ch; ch_width = sap_ctx->acs_cfg->ch_width; - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO, - FL("startChannel %d, EndChannel %d, ch_width %d, HW:%d"), - start_ch_num, end_ch_num, ch_width, - sap_ctx->acs_cfg->hw_mode); + sap_debug("startChannel %d, EndChannel %d, ch_width %d, HW:%d", + start_ch_num, end_ch_num, ch_width, + sap_ctx->acs_cfg->hw_mode); wlansap_extend_to_acs_range(hal, &start_ch_num, &end_ch_num, &band_start_ch, &band_end_ch); - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO, - FL("expanded startChannel %d,EndChannel %d"), - start_ch_num, end_ch_num); - - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO, - FL("band_start_ch %d, band_end_ch %d"), - band_start_ch, band_end_ch); + sap_debug("expanded startChannel %d,EndChannel %d band_start_ch %d, band_end_ch %d", + start_ch_num, end_ch_num, band_start_ch, band_end_ch); sme_cfg_get_int(hal, WNI_CFG_ENABLE_LTE_COEX, &en_lte_coex); @@ -3373,24 +3352,16 @@ static QDF_STATUS sap_get_channel_list(struct sap_context *sap_ctx, list[ch_count] = WLAN_REG_CH_NUM(loop_count); ch_count++; - QDF_TRACE(QDF_MODULE_ID_SAP, - QDF_TRACE_LEVEL_INFO, - FL("%d %d added to ACS ch range"), - ch_count, ch); + sap_debug("%d %d added to ACS ch range", ch_count, ch); } else { - QDF_TRACE(QDF_MODULE_ID_SAP, - QDF_TRACE_LEVEL_INFO_HIGH, - FL("%d %d skipped from ACS ch range"), - ch_count, ch); + sap_debug("%d %d skipped from ACS ch range", + ch_count, ch); } } else { list[ch_count] = WLAN_REG_CH_NUM(loop_count); ch_count++; - QDF_TRACE(QDF_MODULE_ID_SAP, - QDF_TRACE_LEVEL_INFO, - FL("%d %d added to ACS ch range"), - ch_count, ch); + sap_debug("%d %d added to ACS ch range", ch_count, ch); } #else list[ch_count] = WLAN_REG_CH_NUM(loop_count); @@ -3398,15 +3369,13 @@ static QDF_STATUS sap_get_channel_list(struct sap_context *sap_ctx, #endif } if (0 == ch_count) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - FL("No active channels present for the current region")); + sap_info("No active channels present for the current region"); /* * LTE COEX: channel range outside the restricted 2.4GHz * band limits */ if (en_lte_coex && (start_ch_num > band_end_ch)) - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_FATAL, - FL("SAP can't be started as due to LTE COEX")); + sap_info("SAP can't be started as due to LTE COEX"); } /* return the channel list and number of channels to scan */ @@ -3420,11 +3389,10 @@ static QDF_STATUS sap_get_channel_list(struct sap_context *sap_ctx, } for (loop_count = 0; loop_count < ch_count; loop_count++) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, - FL("channel number: %d"), list[loop_count]); sap_ctx->acs_cfg->ch_list[loop_count] = list[loop_count]; } sap_ctx->acs_cfg->ch_list_count = ch_count; + sap_dump_acs_channel(sap_ctx->acs_cfg); return QDF_STATUS_SUCCESS; } diff --git a/drivers/staging/qcacld-3.0/core/sap/src/sap_internal.h b/drivers/staging/qcacld-3.0/core/sap/src/sap_internal.h index dee3ddb14914..a0703c32ab69 100644 --- a/drivers/staging/qcacld-3.0/core/sap/src/sap_internal.h +++ b/drivers/staging/qcacld-3.0/core/sap/src/sap_internal.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -66,6 +66,31 @@ extern "C" { #define SAP_CHAN_PREFERRED_INDOOR 1 #define SAP_CHAN_PREFERRED_OUTDOOR 2 +/*SAP Specific logging*/ + +#define sap_alert(params...) QDF_TRACE_FATAL(QDF_MODULE_ID_SAP, params) +#define sap_err(params...) QDF_TRACE_ERROR(QDF_MODULE_ID_SAP, params) +#define sap_warn(params...) QDF_TRACE_WARN(QDF_MODULE_ID_SAP, params) +#define sap_info(params...) QDF_TRACE_INFO(QDF_MODULE_ID_SAP, params) +#define sap_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_SAP, params) + +#define sap_nofl_alert(params...) \ + QDF_TRACE_FATAL_NO_FL(QDF_MODULE_ID_SAP, params) +#define sap_nofl_err(params...) \ + QDF_TRACE_ERROR_NO_FL(QDF_MODULE_ID_SAP, params) +#define sap_nofl_warn(params...) \ + QDF_TRACE_WARN_NO_FL(QDF_MODULE_ID_SAP, params) +#define sap_nofl_info(params...) \ + QDF_TRACE_INFO_NO_FL(QDF_MODULE_ID_SAP, params) +#define sap_nofl_debug(params...) \ + QDF_TRACE_DEBUG_NO_FL(QDF_MODULE_ID_SAP, params) + +#define sap_alert_rl(params...) QDF_TRACE_FATAL_RL(QDF_MODULE_ID_SAP, params) +#define sap_err_rl(params...) QDF_TRACE_ERROR_RL(QDF_MODULE_ID_SAP, params) +#define sap_warn_rl(params...) QDF_TRACE_WARN_RL(QDF_MODULE_ID_SAP, params) +#define sap_info_rl(params...) QDF_TRACE_INFO_RL(QDF_MODULE_ID_SAP, params) +#define sap_debug_rl(params...) QDF_TRACE_DEBUG_RL(QDF_MODULE_ID_SAP, params) + /*---------------------------------------------------------------------------- * Typedefs * -------------------------------------------------------------------------*/ diff --git a/drivers/staging/qcacld-3.0/core/sap/src/sap_module.c b/drivers/staging/qcacld-3.0/core/sap/src/sap_module.c index 8c7d5280ec6e..df4c0de2a07f 100644 --- a/drivers/staging/qcacld-3.0/core/sap/src/sap_module.c +++ b/drivers/staging/qcacld-3.0/core/sap/src/sap_module.c @@ -101,8 +101,7 @@ QDF_STATUS wlansap_global_init(void) uint32_t i; if (QDF_IS_STATUS_ERROR(qdf_mutex_create(&sap_context_lock))) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "failed to init sap_context_lock"); + sap_err("failed to init sap_context_lock"); return QDF_STATUS_E_FAULT; } @@ -111,8 +110,7 @@ QDF_STATUS wlansap_global_init(void) qdf_atomic_init(&sap_ctx_ref_count[i]); } - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, - "%s: sap global context initialized", __func__); + sap_debug("sap global context initialized"); return QDF_STATUS_SUCCESS; } @@ -130,21 +128,18 @@ QDF_STATUS wlansap_global_deinit(void) for (i = 0; i < SAP_MAX_NUM_SESSION; i++) { if (gp_sap_ctx[i]) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "we could be leaking context:%d", i); + sap_err("we could be leaking context:%d", i); } gp_sap_ctx[i] = NULL; qdf_atomic_init(&sap_ctx_ref_count[i]); } if (QDF_IS_STATUS_ERROR(qdf_mutex_destroy(&sap_context_lock))) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "failed to destroy sap_context_lock"); + sap_err("failed to destroy sap_context_lock"); return QDF_STATUS_E_FAULT; } - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, - "%s: sap global context deinitialized", __func__); + sap_debug("sap global context deinitialized"); return QDF_STATUS_SUCCESS; } @@ -167,16 +162,13 @@ static QDF_STATUS wlansap_save_context(struct sap_context *ctx) gp_sap_ctx[i] = ctx; qdf_atomic_inc(&sap_ctx_ref_count[i]); qdf_mutex_release(&sap_context_lock); - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, - "%s: sap context saved at index: %d", - __func__, i); + sap_debug("sap context saved at index: %d", i); return QDF_STATUS_SUCCESS; } } qdf_mutex_release(&sap_context_lock); - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: failed to save sap context", __func__); + sap_err("failed to save sap context"); return QDF_STATUS_E_FAILURE; } @@ -204,8 +196,7 @@ QDF_STATUS wlansap_context_get(struct sap_context *ctx) } qdf_mutex_release(&sap_context_lock); - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, - "%s: sap session is not valid", __func__); + sap_debug("sap session is not valid"); return QDF_STATUS_E_FAILURE; } @@ -235,10 +226,7 @@ void wlansap_context_put(struct sap_context *ctx) } qdf_mem_free(ctx); gp_sap_ctx[i] = NULL; - QDF_TRACE(QDF_MODULE_ID_SAP, - QDF_TRACE_LEVEL_DEBUG, - "%s: sap session freed: %d", - __func__, i); + sap_debug("sap session freed: %d", i); } qdf_mutex_release(&sap_context_lock); return; @@ -256,23 +244,20 @@ struct sap_context *sap_create_ctx(void) sap_ctx = qdf_mem_malloc(sizeof(*sap_ctx)); if (NULL == sap_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid SAP pointer from p_cds_gctx", __func__); + sap_err("Invalid SAP pointer from p_cds_gctx"); return NULL; } /* Clean up SAP control block, initialize all values */ - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, FL("Enter")); /* Save the SAP context pointer */ status = wlansap_save_context(sap_ctx); if (QDF_IS_STATUS_ERROR(status)) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: failed to save SAP context", __func__); + sap_err("failed to save SAP context"); qdf_mem_free(sap_ctx); return NULL; } - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, FL("Exit")); + sap_debug("Exit"); return sap_ctx; } /* sap_create_ctx */ @@ -289,8 +274,7 @@ QDF_STATUS sap_init_ctx(struct sap_context *sap_ctx, "wlansap_start invoked successfully"); if (NULL == sap_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid SAP pointer", __func__); + sap_err("Invalid SAP pointer"); return QDF_STATUS_E_FAULT; } @@ -321,16 +305,14 @@ QDF_STATUS sap_init_ctx(struct sap_context *sap_ctx, hal = (tHalHandle) CDS_GET_HAL_CB(); if (!hal) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid HAL pointer", __func__); + sap_err("Invalid HAL pointer"); return QDF_STATUS_E_INVAL; } pmac = PMAC_STRUCT(hal); qdf_ret_status = sap_set_session_param(hal, sap_ctx, session_id); if (QDF_STATUS_SUCCESS != qdf_ret_status) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "In %s calling sap_set_session_param status = %d", - __func__, qdf_ret_status); + sap_err("Calling sap_set_session_param status = %d", + qdf_ret_status); return QDF_STATUS_E_FAILURE; } if (sap_ctx->acs_ch_list_protect) { @@ -362,19 +344,16 @@ QDF_STATUS sap_deinit_ctx(struct sap_context *sap_ctx) tpAniSirGlobal pmac; /* Sanity check - Extract SAP control block */ - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, - "wlansap_stop invoked successfully "); + sap_debug("wlansap_stop invoked successfully "); if (NULL == sap_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid SAP pointer", __func__); + sap_err("Invalid SAP pointer"); return QDF_STATUS_E_FAULT; } hal = CDS_GET_HAL_CB(); pmac = (tpAniSirGlobal) hal; if (NULL == pmac) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid MAC context", __func__); + sap_err("Invalid MAC context"); return QDF_STATUS_E_FAULT; } ucfg_scan_unregister_requester(pmac->psoc, sap_ctx->req_id); @@ -401,18 +380,15 @@ QDF_STATUS sap_destroy_ctx(struct sap_context *sap_ctx) "sap_destroy_ctx invoked"); if (NULL == sap_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid SAP pointer", __func__); + sap_err("Invalid SAP pointer"); return QDF_STATUS_E_FAULT; } /* Cleanup SAP control block */ - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, FL("Enter")); /* * wlansap_context_put will release actual sap_ctx memory * allocated during sap_create_ctx */ wlansap_context_put(sap_ctx); - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, FL("Exit")); return QDF_STATUS_SUCCESS; } /* sap_destroy_ctx */ @@ -452,8 +428,7 @@ bool wlansap_is_channel_leaking_in_nol(struct sap_context *sap_ctx, handle = CDS_GET_HAL_CB(); mac_ctx = PMAC_STRUCT(handle); if (!mac_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid mac pointer", __func__); + sap_err("Invalid mac pointer"); return QDF_STATUS_E_FAULT; } if (QDF_IS_STATUS_ERROR(wlansap_mark_leaking_channel(mac_ctx->pdev, @@ -474,8 +449,7 @@ uint16_t wlansap_check_cc_intf(struct sap_context *sap_ctx) hHal = (tHalHandle) CDS_GET_HAL_CB(); if (NULL == hHal) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid MAC context from p_cds_gctx", __func__); + sap_err("Invalid MAC context from p_cds_gctx"); return 0; } intf_ch = sme_check_concurrent_channel_overlap(hHal, sap_ctx->channel, @@ -507,14 +481,12 @@ wlansap_set_scan_acs_channel_params(tsap_config_t *pconfig, QDF_STATUS status = QDF_STATUS_SUCCESS; if (NULL == pconfig) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid pconfig passed ", __func__); + sap_err("Invalid pconfig passed "); return QDF_STATUS_E_FAULT; } if (NULL == psap_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid pconfig passed ", __func__); + sap_err("Invalid pconfig passed "); return QDF_STATUS_E_FAULT; } @@ -566,8 +538,7 @@ wlansap_set_scan_acs_channel_params(tsap_config_t *pconfig, struct csr_roam_profile *wlan_sap_get_roam_profile(struct sap_context *sap_ctx) { if (!sap_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - FL("Invalid SAP pointer from ctx")); + sap_err("Invalid SAP pointer from ctx"); return NULL; } return &sap_ctx->csr_roamProfile; @@ -576,8 +547,7 @@ struct csr_roam_profile *wlan_sap_get_roam_profile(struct sap_context *sap_ctx) eCsrPhyMode wlan_sap_get_phymode(struct sap_context *sap_ctx) { if (!sap_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - FL("Invalid SAP pointer from ctx")); + sap_err("Invalid SAP pointer from ctx"); return 0; } return sap_ctx->csr_roamProfile.phyMode; @@ -586,8 +556,7 @@ eCsrPhyMode wlan_sap_get_phymode(struct sap_context *sap_ctx) uint32_t wlan_sap_get_vht_ch_width(struct sap_context *sap_ctx) { if (!sap_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - FL("Invalid SAP pointer")); + sap_err("Invalid SAP pointer"); return 0; } @@ -598,8 +567,7 @@ void wlan_sap_set_vht_ch_width(struct sap_context *sap_ctx, uint32_t vht_channel_width) { if (!sap_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - FL("Invalid SAP pointer")); + sap_err("Invalid SAP pointer"); return; } @@ -809,14 +777,11 @@ void wlansap_set_stop_bss_inprogress(struct sap_context *sap_ctx, bool in_progress) { if (!sap_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid SAP pointer from ctx", __func__); + sap_err("Invalid SAP pointer from ctx"); return; } - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, - "%s: Set stop_bss_in_progress to %d", - __func__, in_progress); + sap_debug("Set stop_bss_in_progress to %d", in_progress); sap_ctx->stop_bss_in_progress = in_progress; } @@ -826,8 +791,7 @@ QDF_STATUS wlansap_stop_bss(struct sap_context *sap_ctx) QDF_STATUS qdf_status; if (NULL == sap_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid SAP pointer", __func__); + sap_err("Invalid SAP pointer"); return QDF_STATUS_E_FAULT; } @@ -846,8 +810,7 @@ QDF_STATUS wlansap_set_acl_mode(struct sap_context *sap_ctx, eSapMacAddrACL mode) { if (NULL == sap_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid SAP pointer", __func__); + sap_err("Invalid SAP pointer"); return QDF_STATUS_E_FAULT; } @@ -859,8 +822,7 @@ QDF_STATUS wlansap_get_acl_mode(struct sap_context *sap_ctx, eSapMacAddrACL *mode) { if (NULL == sap_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid SAP pointer", __func__); + sap_err("Invalid SAP pointer"); return QDF_STATUS_E_FAULT; } @@ -873,8 +835,7 @@ QDF_STATUS wlansap_get_acl_accept_list(struct sap_context *sap_ctx, uint8_t *nAcceptList) { if (NULL == sap_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid SAP pointer", __func__); + sap_err("Invalid SAP pointer"); return QDF_STATUS_E_FAULT; } @@ -889,8 +850,7 @@ QDF_STATUS wlansap_get_acl_deny_list(struct sap_context *sap_ctx, uint8_t *nDenyList) { if (NULL == sap_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid SAP pointer from p_cds_gctx", __func__); + sap_err("Invalid SAP pointer from p_cds_gctx"); return QDF_STATUS_E_FAULT; } @@ -976,16 +936,14 @@ QDF_STATUS wlansap_modify_acl(struct sap_context *sap_ctx, uint8_t staWLIndex, staBLIndex; if (NULL == sap_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid SAP Context", __func__); + sap_err("Invalid SAP Context"); return QDF_STATUS_E_FAULT; } if (qdf_mem_cmp(sap_ctx->bssid.bytes, peer_sta_mac, QDF_MAC_ADDR_SIZE) == 0) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "requested peer mac is" MAC_ADDRESS_STR - "our own SAP BSSID. Do not blacklist or whitelist this BSSID", - MAC_ADDR_ARRAY(peer_sta_mac)); + sap_err("requested peer mac is" MAC_ADDRESS_STR + "our own SAP BSSID. Do not blacklist or whitelist this BSSID", + MAC_ADDR_ARRAY(peer_sta_mac)); return QDF_STATUS_E_FAULT; } QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO_LOW, @@ -1011,11 +969,10 @@ QDF_STATUS wlansap_modify_acl(struct sap_context *sap_ctx, peer_sta_mac, &staBLIndex); if (sta_white_list && sta_black_list) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "Peer mac " MAC_ADDRESS_STR - " found in white and black lists." - "Initial lists passed incorrect. Cannot execute this command.", - MAC_ADDR_ARRAY(peer_sta_mac)); + sap_err("Peer mac " MAC_ADDRESS_STR + " found in white and black lists." + "Initial lists passed incorrect. Cannot execute this command.", + MAC_ADDR_ARRAY(peer_sta_mac)); return QDF_STATUS_E_FAILURE; } @@ -1028,34 +985,26 @@ QDF_STATUS wlansap_modify_acl(struct sap_context *sap_ctx, /* error check */ /* if list is already at max, return failure */ if (sap_ctx->nAcceptMac == MAX_ACL_MAC_ADDRESS) { - QDF_TRACE(QDF_MODULE_ID_SAP, - QDF_TRACE_LEVEL_ERROR, - "White list is already maxed out. Cannot accept " - MAC_ADDRESS_STR, - MAC_ADDR_ARRAY(peer_sta_mac)); + sap_err("White list is already maxed out. Cannot accept " + MAC_ADDRESS_STR, + MAC_ADDR_ARRAY(peer_sta_mac)); return QDF_STATUS_E_FAILURE; } if (sta_white_list) { /* Do nothing if already present in white list. Just print a warning */ - QDF_TRACE(QDF_MODULE_ID_SAP, - QDF_TRACE_LEVEL_WARN, - "MAC address already present in white list " - MAC_ADDRESS_STR, - MAC_ADDR_ARRAY(peer_sta_mac)); + sap_warn("MAC address already present in white list " + MAC_ADDRESS_STR, + MAC_ADDR_ARRAY(peer_sta_mac)); return QDF_STATUS_SUCCESS; } if (sta_black_list) { /* remove it from black list before adding to the white list */ - QDF_TRACE(QDF_MODULE_ID_SAP, - QDF_TRACE_LEVEL_WARN, - "STA present in black list so first remove from it"); + sap_warn("STA present in black list so first remove from it"); sap_remove_mac_from_acl(sap_ctx->denyMacList, &sap_ctx->nDenyMac, staBLIndex); } - QDF_TRACE(QDF_MODULE_ID_SAP, - QDF_TRACE_LEVEL_INFO, - "... Now add to the white list"); + sap_info("... Now add to the white list"); sap_add_mac_to_acl(sap_ctx->acceptMacList, &sap_ctx->nAcceptMac, peer_sta_mac); @@ -1069,9 +1018,7 @@ QDF_STATUS wlansap_modify_acl(struct sap_context *sap_ctx, struct csr_del_sta_params delStaParams; - QDF_TRACE(QDF_MODULE_ID_SAP, - QDF_TRACE_LEVEL_INFO, - "Delete from white list"); + sap_info("Delete from white list"); sap_remove_mac_from_acl(sap_ctx->acceptMacList, &sap_ctx->nAcceptMac, staWLIndex); @@ -1087,16 +1034,13 @@ QDF_STATUS wlansap_modify_acl(struct sap_context *sap_ctx, sap_ctx->nAcceptMac, sap_ctx->nDenyMac); } else { - QDF_TRACE(QDF_MODULE_ID_SAP, - QDF_TRACE_LEVEL_WARN, - "MAC address to be deleted is not present in the white list " - MAC_ADDRESS_STR, - MAC_ADDR_ARRAY(peer_sta_mac)); + sap_warn("MAC address to be deleted is not present in the white list " + MAC_ADDRESS_STR, + MAC_ADDR_ARRAY(peer_sta_mac)); return QDF_STATUS_E_FAILURE; } } else { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "Invalid cmd type passed"); + sap_err("Invalid cmd type passed"); return QDF_STATUS_E_FAILURE; } break; @@ -1108,27 +1052,21 @@ QDF_STATUS wlansap_modify_acl(struct sap_context *sap_ctx, /* error check */ /* if list is already at max, return failure */ if (sap_ctx->nDenyMac == MAX_ACL_MAC_ADDRESS) { - QDF_TRACE(QDF_MODULE_ID_SAP, - QDF_TRACE_LEVEL_ERROR, - "Black list is already maxed out. Cannot accept " - MAC_ADDRESS_STR, - MAC_ADDR_ARRAY(peer_sta_mac)); + sap_err("Black list is already maxed out. Cannot accept " + MAC_ADDRESS_STR, + MAC_ADDR_ARRAY(peer_sta_mac)); return QDF_STATUS_E_FAILURE; } if (sta_black_list) { /* Do nothing if already present in white list */ - QDF_TRACE(QDF_MODULE_ID_SAP, - QDF_TRACE_LEVEL_WARN, - "MAC address already present in black list " - MAC_ADDRESS_STR, - MAC_ADDR_ARRAY(peer_sta_mac)); + sap_warn("MAC address already present in black list " + MAC_ADDRESS_STR, + MAC_ADDR_ARRAY(peer_sta_mac)); return QDF_STATUS_SUCCESS; } if (sta_white_list) { /* remove it from white list before adding to the black list */ - QDF_TRACE(QDF_MODULE_ID_SAP, - QDF_TRACE_LEVEL_WARN, - "Present in white list so first remove from it"); + sap_warn("Present in white list so first remove from it"); sap_remove_mac_from_acl(sap_ctx->acceptMacList, &sap_ctx->nAcceptMac, staWLIndex); @@ -1139,9 +1077,7 @@ QDF_STATUS wlansap_modify_acl(struct sap_context *sap_ctx, (SIR_MAC_MGMT_DEAUTH >> 4), &delStaParams); wlansap_deauth_sta(sap_ctx, &delStaParams); - QDF_TRACE(QDF_MODULE_ID_SAP, - QDF_TRACE_LEVEL_INFO, - "... Now add to black list"); + sap_info("... Now add to black list"); sap_add_mac_to_acl(sap_ctx->denyMacList, &sap_ctx->nDenyMac, peer_sta_mac); QDF_TRACE(QDF_MODULE_ID_SAP, @@ -1151,9 +1087,7 @@ QDF_STATUS wlansap_modify_acl(struct sap_context *sap_ctx, sap_ctx->nDenyMac); } else if (cmd == DELETE_STA_FROM_ACL) { if (sta_black_list) { - QDF_TRACE(QDF_MODULE_ID_SAP, - QDF_TRACE_LEVEL_INFO, - "Delete from black list"); + sap_info("Delete from black list"); sap_remove_mac_from_acl(sap_ctx->denyMacList, &sap_ctx->nDenyMac, staBLIndex); @@ -1163,24 +1097,20 @@ QDF_STATUS wlansap_modify_acl(struct sap_context *sap_ctx, sap_ctx->nAcceptMac, sap_ctx->nDenyMac); } else { - QDF_TRACE(QDF_MODULE_ID_SAP, - QDF_TRACE_LEVEL_WARN, - "MAC address to be deleted is not present in the black list " - MAC_ADDRESS_STR, - MAC_ADDR_ARRAY(peer_sta_mac)); + sap_warn("MAC address to be deleted is not present in the black list " + MAC_ADDRESS_STR, + MAC_ADDR_ARRAY(peer_sta_mac)); return QDF_STATUS_E_FAILURE; } } else { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "Invalid cmd type passed"); + sap_err("Invalid cmd type passed"); return QDF_STATUS_E_FAILURE; } break; default: { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "Invalid list type passed %d", list_type); + sap_err("Invalid list type passed %d", list_type); return QDF_STATUS_E_FAILURE; } } @@ -1199,8 +1129,7 @@ QDF_STATUS wlansap_disassoc_sta(struct sap_context *sap_ctx, struct csr_del_sta_params *p_del_sta_params) { if (NULL == sap_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid SAP pointer", __func__); + sap_err("Invalid SAP pointer"); return QDF_STATUS_E_FAULT; } @@ -1217,8 +1146,7 @@ QDF_STATUS wlansap_deauth_sta(struct sap_context *sap_ctx, QDF_STATUS qdf_status = QDF_STATUS_E_FAULT; if (NULL == sap_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid SAP pointer", __func__); + sap_err("Invalid SAP pointer"); return qdf_status; } @@ -1250,8 +1178,7 @@ wlansap_update_csa_channel_params(struct sap_context *sap_context, hal = CDS_GET_HAL_CB(); if (!hal) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid hal pointer from p_cds_gctx", __func__); + sap_err("Invalid hal pointer from p_cds_gctx"); return QDF_STATUS_E_FAULT; } @@ -1370,32 +1297,28 @@ QDF_STATUS wlansap_set_channel_change_with_csa(struct sap_context *sapContext, bool sta_sap_scc_on_dfs_chan; if (NULL == sapContext) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid SAP pointer", __func__); + sap_err("Invalid SAP pointer"); return QDF_STATUS_E_FAULT; } hHal = CDS_GET_HAL_CB(); if (NULL == hHal) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid HAL pointer from p_cds_gctx", __func__); + sap_err("Invalid HAL pointer from p_cds_gctx"); return QDF_STATUS_E_FAULT; } pMac = PMAC_STRUCT(hHal); if (strict && !policy_mgr_is_safe_channel(pMac->psoc, targetChannel)) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%u is unsafe channel", targetChannel); + sap_err("%u is unsafe channel", targetChannel); return QDF_STATUS_E_FAULT; } - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO, - "%s: sap chan:%d target:%d conn on 5GHz:%d, csa_reason:%s(%d)", - __func__, sapContext->channel, targetChannel, - policy_mgr_is_any_mode_active_on_band_along_with_session( - pMac->psoc, sapContext->sessionId, POLICY_MGR_BAND_5), - sap_get_csa_reason_str(sapContext->csa_reason), - sapContext->csa_reason); + sap_nofl_debug("SAP CSA: %d ---> %d conn on 5GHz:%d, csa_reason:%s(%d) strict %d vdev %d", + sapContext->channel, targetChannel, + policy_mgr_is_any_mode_active_on_band_along_with_session( + pMac->psoc, sapContext->sessionId, POLICY_MGR_BAND_5), + sap_get_csa_reason_str(sapContext->csa_reason), + sapContext->csa_reason, strict, sapContext->sessionId); sta_sap_scc_on_dfs_chan = policy_mgr_is_sta_sap_scc_allowed_on_dfs_chan(pMac->psoc); @@ -1420,10 +1343,8 @@ QDF_STATUS wlansap_set_channel_change_with_csa(struct sap_context *sapContext, valid = wlan_sap_validate_channel_switch(hHal, targetChannel, sapContext); if (!valid) { - QDF_TRACE(QDF_MODULE_ID_SAP, - QDF_TRACE_LEVEL_ERROR, - FL("Channel switch to %u is not allowed due to concurrent channel interference"), - targetChannel); + sap_err("Channel switch to %u is not allowed due to concurrent channel interference", + targetChannel); return QDF_STATUS_E_FAULT; } } @@ -1462,12 +1383,10 @@ QDF_STATUS wlansap_set_channel_change_with_csa(struct sap_context *sapContext, * user input is used for the bandwidth */ if (target_bw != CH_WIDTH_MAX) { - QDF_TRACE(QDF_MODULE_ID_SAP, - QDF_TRACE_LEVEL_INFO, - "%s: target bw:%d new width:%d", - __func__, target_bw, - pMac->sap.SapDfsInfo. - new_ch_params.ch_width); + sap_nofl_debug("SAP CSA: target bw:%d new width:%d", + target_bw, + pMac->sap.SapDfsInfo. + new_ch_params.ch_width); pMac->sap.SapDfsInfo.new_ch_params.ch_width = pMac->sap.SapDfsInfo.new_chanWidth = QDF_MIN(pMac->sap.SapDfsInfo. @@ -1508,24 +1427,17 @@ QDF_STATUS wlansap_set_channel_change_with_csa(struct sap_context *sapContext, sap_fsm(sapContext, &sapEvent); } else { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Failed to request Channel Change, since SAP is not in SAP_STARTED state", - __func__); + sap_err("Failed to request Channel Change, since SAP is not in SAP_STARTED state"); return QDF_STATUS_E_FAULT; } } else { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Channel = %d is not valid in the current" - "regulatory domain", __func__, targetChannel); + sap_err("Channel = %d is not valid in the current" + "regulatory domain", targetChannel); return QDF_STATUS_E_FAULT; } - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO_HIGH, - "%s: Posted eSAP_CHANNEL_SWITCH_ANNOUNCEMENT_START successfully to sap_fsm for Channel = %d", - __func__, targetChannel); - return QDF_STATUS_SUCCESS; } @@ -1538,16 +1450,12 @@ QDF_STATUS wlansap_set_key_sta(struct sap_context *sap_ctx, uint32_t roamId = INVALID_ROAM_ID; if (!sap_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid SAP pointer", - __func__); + sap_err("Invalid SAP pointer"); return QDF_STATUS_E_FAULT; } hHal = CDS_GET_HAL_CB(); if (NULL == hHal) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid HAL pointer", - __func__); + sap_err("Invalid HAL pointer"); return QDF_STATUS_E_FAULT; } qdf_ret_status = @@ -1569,24 +1477,21 @@ QDF_STATUS wlan_sap_getstation_ie_information(struct sap_context *sap_ctx, uint32_t ie_len = 0; if (NULL == sap_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - FL("Invalid SAP pointer")); + sap_err("Invalid SAP pointer"); return QDF_STATUS_E_FAULT; } if (len) { ie_len = *len; *len = sap_ctx->nStaWPARSnReqIeLength; - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO, - FL("WPAIE len : %x"), *len); + sap_info("WPAIE len : %x", *len); if ((buf) && (ie_len >= sap_ctx->nStaWPARSnReqIeLength)) { qdf_mem_copy(buf, sap_ctx->pStaWpaRsnReqIE, sap_ctx->nStaWPARSnReqIeLength); - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO, - FL("WPAIE: %02x:%02x:%02x:%02x:%02x:%02x"), - buf[0], buf[1], buf[2], buf[3], buf[4], - buf[5]); + sap_info("WPAIE: %02x:%02x:%02x:%02x:%02x:%02x", + buf[0], buf[1], buf[2], buf[3], buf[4], + buf[5]); qdf_status = QDF_STATUS_SUCCESS; } } @@ -1598,8 +1503,7 @@ QDF_STATUS wlan_sap_update_next_channel(struct sap_context *sap_ctx, enum phy_ch_width chan_bw) { if (!sap_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid SAP pointer", __func__); + sap_err("Invalid SAP pointer"); return QDF_STATUS_E_FAULT; } @@ -1615,20 +1519,17 @@ QDF_STATUS wlan_sap_set_pre_cac_status(struct sap_context *sap_ctx, tpAniSirGlobal mac_ctx = PMAC_STRUCT(handle); if (!mac_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid mac pointer", __func__); + sap_err("Invalid mac pointer"); return QDF_STATUS_E_FAULT; } if (!sap_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid SAP pointer", __func__); + sap_err("Invalid SAP pointer"); return QDF_STATUS_E_FAULT; } sap_ctx->is_pre_cac_on = status; - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, - "%s: is_pre_cac_on:%d", __func__, sap_ctx->is_pre_cac_on); + sap_debug("is_pre_cac_on:%d", sap_ctx->is_pre_cac_on); return QDF_STATUS_SUCCESS; } @@ -1637,8 +1538,7 @@ QDF_STATUS wlan_sap_set_chan_before_pre_cac(struct sap_context *sap_ctx, uint8_t chan_before_pre_cac) { if (!sap_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid SAP pointer", __func__); + sap_err("Invalid SAP pointer"); return QDF_STATUS_E_FAULT; } @@ -1650,16 +1550,14 @@ QDF_STATUS wlan_sap_set_pre_cac_complete_status(struct sap_context *sap_ctx, bool status) { if (!sap_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid SAP pointer", __func__); + sap_err("Invalid SAP pointer"); return QDF_STATUS_E_FAULT; } sap_ctx->pre_cac_complete = status; - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, - "%s: pre cac complete status:%d session:%d", - __func__, status, sap_ctx->sessionId); + sap_debug("pre cac complete status:%d session:%d", status, + sap_ctx->sessionId); return QDF_STATUS_SUCCESS; } @@ -1734,15 +1632,12 @@ QDF_STATUS wlansap_register_mgmt_frame(struct sap_context *sap_ctx, QDF_STATUS qdf_ret_status = QDF_STATUS_E_FAILURE; if (NULL == sap_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid SAP pointer from pCtx", - __func__); + sap_err("Invalid SAP pointer from pCtx"); return QDF_STATUS_E_FAULT; } hHal = CDS_GET_HAL_CB(); if (NULL == hHal) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - FL("hal pointer null")); + sap_err("hal pointer null"); return QDF_STATUS_E_FAULT; } @@ -1754,8 +1649,7 @@ QDF_STATUS wlansap_register_mgmt_frame(struct sap_context *sap_ctx, return QDF_STATUS_SUCCESS; } - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "Failed to Register MGMT frame"); + sap_err("Failed to Register MGMT frame"); return QDF_STATUS_E_FAULT; } @@ -1769,15 +1663,12 @@ QDF_STATUS wlansap_de_register_mgmt_frame(struct sap_context *sap_ctx, QDF_STATUS qdf_ret_status = QDF_STATUS_E_FAILURE; if (NULL == sap_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid SAP pointer from pCtx", - __func__); + sap_err("Invalid SAP pointer from pCtx"); return QDF_STATUS_E_FAULT; } hHal = CDS_GET_HAL_CB(); if (NULL == hHal) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - FL("hal pointer null")); + sap_err("hal pointer null"); return QDF_STATUS_E_FAULT; } @@ -1789,8 +1680,7 @@ QDF_STATUS wlansap_de_register_mgmt_frame(struct sap_context *sap_ctx, return QDF_STATUS_SUCCESS; } - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "Failed to Deregister MGMT frame"); + sap_err("Failed to Deregister MGMT frame"); return QDF_STATUS_E_FAULT; } @@ -1809,9 +1699,8 @@ void wlansap_get_sec_channel(uint8_t sec_ch_offset, default: *sec_channel = 0; } - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, - "%s: sec channel offset %d, sec channel %d", - __func__, sec_ch_offset, *sec_channel); + sap_debug("sec channel offset %d, sec channel %d", + sec_ch_offset, *sec_channel); } QDF_STATUS wlansap_channel_change_request(struct sap_context *sapContext, @@ -1824,21 +1713,18 @@ QDF_STATUS wlansap_channel_change_request(struct sap_context *sapContext, struct ch_params *ch_params; if (!target_channel) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: channel 0 requested", __func__); + sap_err("channel 0 requested"); return QDF_STATUS_E_FAULT; } if (NULL == sapContext) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid SAP pointer", __func__); + sap_err("Invalid SAP pointer"); return QDF_STATUS_E_FAULT; } hHal = CDS_GET_HAL_CB(); if (NULL == hHal) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid HAL pointer from p_cds_gctx", __func__); + sap_err("Invalid HAL pointer from p_cds_gctx"); return QDF_STATUS_E_FAULT; } mac_ctx = PMAC_STRUCT(hHal); @@ -1853,16 +1739,11 @@ QDF_STATUS wlansap_channel_change_request(struct sap_context *sapContext, (phy_mode == eCSR_DOT11_MODE_11a)) phy_mode = eCSR_DOT11_MODE_11g; - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, - "%s: phy_mode: %d, target_channel: %d new phy_mode: %d", - __func__, sapContext->csr_roamProfile.phyMode, - target_channel, phy_mode); sapContext->csr_roamProfile.phyMode = phy_mode; if (sapContext->csr_roamProfile.ChannelInfo.numOfChannels == 0 || sapContext->csr_roamProfile.ChannelInfo.ChannelList == NULL) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - FL("Invalid channel list")); + sap_err("Invalid channel list"); return QDF_STATUS_E_FAULT; } sapContext->csr_roamProfile.ChannelInfo.ChannelList[0] = target_channel; @@ -1893,11 +1774,10 @@ QDF_STATUS wlansap_channel_change_request(struct sap_context *sapContext, qdf_ret_status = sme_roam_channel_change_req(hHal, sapContext->bssid, ch_params, &sapContext->csr_roamProfile); - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO, - "%s: chan:%d phy_mode %d width:%d offset:%d seg0:%d seg1:%d", - __func__, sapContext->channel, phy_mode, ch_params->ch_width, - ch_params->sec_ch_offset, ch_params->center_freq_seg0, - ch_params->center_freq_seg1); + sap_info("chan:%d phy_mode %d width:%d offset:%d seg0:%d seg1:%d", + sapContext->channel, phy_mode, ch_params->ch_width, + ch_params->sec_ch_offset, ch_params->center_freq_seg0, + ch_params->center_freq_seg1); if (qdf_ret_status == QDF_STATUS_SUCCESS) { sap_signal_hdd_event(sapContext, NULL, @@ -1917,15 +1797,13 @@ QDF_STATUS wlansap_start_beacon_req(struct sap_context *sap_ctx) tpAniSirGlobal pMac = NULL; if (NULL == sap_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid SAP pointer", __func__); + sap_err("Invalid SAP pointer"); return QDF_STATUS_E_FAULT; } hHal = CDS_GET_HAL_CB(); if (NULL == hHal) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid HAL pointer", __func__); + sap_err("Invalid HAL pointer"); return QDF_STATUS_E_FAULT; } pMac = PMAC_STRUCT(hHal); @@ -1954,15 +1832,13 @@ QDF_STATUS wlansap_dfs_send_csa_ie_request(struct sap_context *sap_ctx) tpAniSirGlobal pMac = NULL; if (NULL == sap_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid SAP pointer", __func__); + sap_err("Invalid SAP pointer"); return QDF_STATUS_E_FAULT; } hHal = CDS_GET_HAL_CB(); if (NULL == hHal) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid HAL pointer", __func__); + sap_err("Invalid HAL pointer"); return QDF_STATUS_E_FAULT; } pMac = PMAC_STRUCT(hHal); @@ -1973,12 +1849,11 @@ QDF_STATUS wlansap_dfs_send_csa_ie_request(struct sap_context *sap_ctx) pMac->sap.SapDfsInfo.target_channel, 0, &pMac->sap.SapDfsInfo.new_ch_params); - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO, - "%s: chan:%d req:%d width:%d off:%d", - __func__, pMac->sap.SapDfsInfo.target_channel, - pMac->sap.SapDfsInfo.csaIERequired, - pMac->sap.SapDfsInfo.new_ch_params.ch_width, - pMac->sap.SapDfsInfo.new_ch_params.sec_ch_offset); + sap_info("chan:%d req:%d width:%d off:%d", + pMac->sap.SapDfsInfo.target_channel, + pMac->sap.SapDfsInfo.csaIERequired, + pMac->sap.SapDfsInfo.new_ch_params.ch_width, + pMac->sap.SapDfsInfo.new_ch_params.sec_ch_offset); qdf_ret_status = sme_roam_csa_ie_request(hHal, sap_ctx->bssid, @@ -2021,8 +1896,7 @@ QDF_STATUS wlansap_get_dfs_ignore_cac(tHalHandle hHal, uint8_t *pIgnore_cac) if (NULL != hHal) { pMac = PMAC_STRUCT(hHal); } else { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid hHal pointer", __func__); + sap_err("Invalid hHal pointer"); return QDF_STATUS_E_FAULT; } @@ -2058,8 +1932,7 @@ QDF_STATUS wlansap_set_dfs_ignore_cac(tHalHandle hHal, uint8_t ignore_cac) if (NULL != hHal) { pMac = PMAC_STRUCT(hHal); } else { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid hHal pointer", __func__); + sap_err("Invalid hHal pointer"); return QDF_STATUS_E_FAULT; } @@ -2088,8 +1961,7 @@ wlansap_set_dfs_restrict_japan_w53(tHalHandle hHal, uint8_t disable_Dfs_W53) if (NULL != hHal) { pMac = PMAC_STRUCT(hHal); } else { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid hHal pointer", __func__); + sap_err("Invalid hHal pointer"); return QDF_STATUS_E_FAULT; } @@ -2108,9 +1980,7 @@ wlansap_set_dfs_restrict_japan_w53(tHalHandle hHal, uint8_t disable_Dfs_W53) status = QDF_STATUS_SUCCESS; } else { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - FL - ("Regdomain not japan, set disable JP W53 not valid")); + sap_err("Regdomain not japan, set disable JP W53 not valid"); status = QDF_STATUS_E_FAULT; } @@ -2121,8 +1991,7 @@ wlansap_set_dfs_restrict_japan_w53(tHalHandle hHal, uint8_t disable_Dfs_W53) bool sap_is_auto_channel_select(struct sap_context *sapcontext) { if (NULL == sapcontext) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid SAP pointer", __func__); + sap_err("Invalid SAP pointer"); return false; } return sapcontext->channel == AUTO_CHANNEL_SELECT; @@ -2146,9 +2015,7 @@ wlan_sap_set_channel_avoidance(tHalHandle hal, bool sap_channel_avoidance) if (NULL != hal) { mac_ctx = PMAC_STRUCT(hal); } else { - QDF_TRACE(QDF_MODULE_ID_SAP, - QDF_TRACE_LEVEL_ERROR, - FL("hal or mac_ctx pointer NULL")); + sap_err("hal or mac_ctx pointer NULL"); return QDF_STATUS_E_FAULT; } mac_ctx->sap.sap_channel_avoidance = sap_channel_avoidance; @@ -2183,8 +2050,7 @@ wlansap_set_dfs_preferred_channel_location(tHalHandle hHal, if (NULL != hHal) { pMac = PMAC_STRUCT(hHal); } else { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid hHal pointer", __func__); + sap_err("Invalid hHal pointer"); return QDF_STATUS_E_FAULT; } @@ -2207,9 +2073,7 @@ wlansap_set_dfs_preferred_channel_location(tHalHandle hHal, status = QDF_STATUS_SUCCESS; } else { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - FL - ("sapdfs:NOT JAPAN REG, Invalid Set preferred chans location")); + sap_err("sapdfs:NOT JAPAN REG, Invalid Set preferred chans location"); status = QDF_STATUS_E_FAULT; } @@ -2246,8 +2110,7 @@ QDF_STATUS wlansap_set_dfs_target_chnl(tHalHandle hHal, uint8_t target_channel) if (NULL != hHal) { pMac = PMAC_STRUCT(hHal); } else { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid hHal pointer", __func__); + sap_err("Invalid hHal pointer"); return QDF_STATUS_E_FAULT; } if (target_channel > 0) { @@ -2281,15 +2144,12 @@ wlansap_update_sap_config_add_ie(tsap_config_t *pConfig, bufferLength = additionIELength; pBuffer = qdf_mem_malloc(bufferLength); if (NULL == pBuffer) { - QDF_TRACE(QDF_MODULE_ID_SAP, - QDF_TRACE_LEVEL_ERROR, - FL("Could not allocate the buffer ")); + sap_err("Could not allocate the buffer "); return QDF_STATUS_E_NOMEM; } qdf_mem_copy(pBuffer, pAdditionIEBuffer, bufferLength); bufferValid = true; - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO, - FL("update_type: %d"), updateType); + sap_info("update_type: %d", updateType); qdf_trace_hex_dump(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO, pBuffer, bufferLength); } @@ -2305,8 +2165,7 @@ wlansap_update_sap_config_add_ie(tsap_config_t *pConfig, } else { pConfig->probeRespBcnIEsLen = 0; pConfig->pProbeRespBcnIEsBuffer = NULL; - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO, - FL("No Probe Resp beacone IE received in set beacon")); + sap_info("No Probe Resp beacone IE received in set beacon"); } break; case eUPDATE_IE_PROBE_RESP: @@ -2318,8 +2177,7 @@ wlansap_update_sap_config_add_ie(tsap_config_t *pConfig, } else { pConfig->probeRespIEsBufferLen = 0; pConfig->pProbeRespIEsBuffer = NULL; - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO, - FL("No Probe Response IE received in set beacon")); + sap_info("No Probe Response IE received in set beacon"); } break; case eUPDATE_IE_ASSOC_RESP: @@ -2331,13 +2189,11 @@ wlansap_update_sap_config_add_ie(tsap_config_t *pConfig, } else { pConfig->assocRespIEsLen = 0; pConfig->pAssocRespIEsBuffer = NULL; - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO, - FL("No Assoc Response IE received in set beacon")); + sap_info("No Assoc Response IE received in set beacon"); } break; default: - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO, - FL("No matching buffer type %d"), updateType); + sap_info("No matching buffer type %d", updateType); if (pBuffer != NULL) qdf_mem_free(pBuffer); break; @@ -2350,8 +2206,7 @@ QDF_STATUS wlansap_reset_sap_config_add_ie(tsap_config_t *pConfig, eUpdateIEsType updateType) { if (NULL == pConfig) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid Config pointer", __func__); + sap_err("Invalid Config pointer"); return QDF_STATUS_E_FAULT; } @@ -2386,8 +2241,7 @@ wlansap_reset_sap_config_add_ie(tsap_config_t *pConfig, eUpdateIEsType updateTyp default: if (eUPDATE_IE_ALL != updateType) - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - FL("Invalid buffer type %d"), updateType); + sap_err("Invalid buffer type %d", updateType); break; } return QDF_STATUS_SUCCESS; @@ -2423,8 +2277,7 @@ void wlansap_extend_to_acs_range(tHalHandle hal, uint8_t *startChannelNum, mac_ctx = PMAC_STRUCT(hal); if (!mac_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid mac_ctx", __func__); + sap_err("Invalid mac_ctx"); return; } if (*startChannelNum <= 14 && *endChannelNum <= 14) { @@ -2481,8 +2334,7 @@ QDF_STATUS wlan_sap_set_vendor_acs(struct sap_context *sap_context, bool is_vendor_acs) { if (!sap_context) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid SAP pointer", __func__); + sap_err("Invalid SAP pointer"); return QDF_STATUS_E_FAULT; } sap_context->vendor_acs_dfs_lte_enabled = is_vendor_acs; @@ -2498,15 +2350,13 @@ QDF_STATUS wlansap_set_dfs_nol(struct sap_context *sap_ctx, tpAniSirGlobal mac = NULL; if (!sap_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid SAP pointer", __func__); + sap_err("Invalid SAP pointer"); return QDF_STATUS_E_FAULT; } hal = CDS_GET_HAL_CB(); if (!hal) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid HAL pointer", __func__); + sap_err("Invalid HAL pointer"); return QDF_STATUS_E_FAULT; } @@ -2515,23 +2365,19 @@ QDF_STATUS wlansap_set_dfs_nol(struct sap_context *sap_ctx, if (conf == eSAP_DFS_NOL_CLEAR) { struct wlan_objmgr_pdev *pdev; - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: clear the DFS NOL", __func__); + sap_err("clear the DFS NOL"); pdev = mac->pdev; if (!pdev) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: null pdev", __func__); + sap_err("null pdev"); return QDF_STATUS_E_FAULT; } utils_dfs_clear_nol_channels(pdev); } else if (conf == eSAP_DFS_NOL_RANDOMIZE) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Randomize the DFS NOL", __func__); + sap_err("Randomize the DFS NOL"); } else { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: unsupport type %d", __func__, conf); + sap_err("unsupport type %d", conf); } return QDF_STATUS_SUCCESS; @@ -2572,10 +2418,7 @@ void wlansap_populate_del_sta_params(const uint8_t *mac, else pDelStaParams->subtype = (SIR_MAC_MGMT_DEAUTH >> 4); - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, - FL( - "Delete STA with RC:%hu subtype:%hhu MAC::" - MAC_ADDRESS_STR), + sap_debug("Delete STA with RC:%hu subtype:%hhu MAC::" MAC_ADDRESS_STR, pDelStaParams->reason_code, pDelStaParams->subtype, MAC_ADDR_ARRAY(pDelStaParams->peerMacAddr.bytes)); } @@ -2590,16 +2433,14 @@ QDF_STATUS wlansap_acs_chselect(struct sap_context *sap_context, tpAniSirGlobal pmac = NULL; if (NULL == sap_context) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid SAP pointer", __func__); + sap_err("Invalid SAP pointer"); return QDF_STATUS_E_FAULT; } h_hal = (tHalHandle)CDS_GET_HAL_CB(); if (NULL == h_hal) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid MAC context", __func__); + sap_err("Invalid MAC context"); return QDF_STATUS_E_FAULT; } @@ -2641,9 +2482,7 @@ QDF_STATUS wlansap_acs_chselect(struct sap_context *sap_context, qdf_status = sap_channel_sel(sap_context); if (QDF_STATUS_E_ABORTED == qdf_status) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "In %s,DFS not supported in the current operating mode", - __func__); + sap_err("DFS not supported in the current operating mode"); return QDF_STATUS_E_FAILURE; } else if (QDF_STATUS_E_CANCELED == qdf_status) { /* @@ -2651,19 +2490,14 @@ QDF_STATUS wlansap_acs_chselect(struct sap_context *sap_context, * failed or ACS is overridden due to other constrainst * So send selected channel to HDD */ - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - FL("Scan Req Failed/ACS Overridden")); - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - FL("Selected channel = %d"), - sap_context->channel); + sap_err("Scan Req Failed/ACS Overridden"); + sap_err("Selected channel = %d", sap_context->channel); return sap_signal_hdd_event(sap_context, NULL, eSAP_ACS_CHANNEL_SELECTED, (void *) eSAP_STATUS_SUCCESS); - } else if (QDF_STATUS_SUCCESS == qdf_status) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_INFO_HIGH, - FL("Successfully Issued a Pre Start Bss Scan Request")); } + return qdf_status; } @@ -2720,24 +2554,20 @@ QDF_STATUS wlansap_set_tx_leakage_threshold(tHalHandle hal, tpAniSirGlobal mac; if (NULL == hal) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid hal pointer", __func__); + sap_err("Invalid hal pointer"); return QDF_STATUS_E_FAULT; } mac = PMAC_STRUCT(hal); tgt_dfs_set_tx_leakage_threshold(mac->pdev, tx_leakage_threshold); - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, - "%s: leakage_threshold %d", __func__, - tx_leakage_threshold); + sap_debug(" leakage_threshold %d", tx_leakage_threshold); return QDF_STATUS_SUCCESS; } QDF_STATUS wlansap_set_invalid_session(struct sap_context *sap_ctx) { if (NULL == sap_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - FL("Invalid SAP pointer")); + sap_err("Invalid SAP pointer"); return QDF_STATUS_E_FAILURE; } @@ -2752,15 +2582,13 @@ void wlansap_cleanup_cac_timer(struct sap_context *sap_ctx) tpAniSirGlobal pmac; if (!sap_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - FL("Invalid SAP context")); + sap_err("Invalid SAP context"); return; } hal = CDS_GET_HAL_CB(); if (!hal) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - FL("Invalid hal pointer")); + sap_err("Invalid hal pointer"); return; } @@ -2771,8 +2599,7 @@ void wlansap_cleanup_cac_timer(struct sap_context *sap_ctx) pmac->sap.SapDfsInfo.is_dfs_cac_timer_running = 0; qdf_mc_timer_destroy( &pmac->sap.SapDfsInfo.sap_dfs_cac_timer); - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - FL("sapdfs, force cleanup running dfs cac timer")); + sap_err("sapdfs, force cleanup running dfs cac timer"); } } @@ -2783,17 +2610,9 @@ wlansap_is_channel_present_in_acs_list(uint8_t ch, { uint8_t i; - for (i = 0; i < ch_count; i++) { - if (ch_list[i] == ch) { - /* - * channel was given by hostpad for ACS, and is present - * in PCL. - */ - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, - FL("channel present in acs cfg channel list %d"), ch); + for (i = 0; i < ch_count; i++) + if (ch_list[i] == ch) return true; - } - } return false; } @@ -2807,8 +2626,7 @@ QDF_STATUS wlansap_filter_ch_based_acs(struct sap_context *sap_ctx, if (!sap_ctx || !ch_list || !ch_cnt || !sap_ctx->acs_cfg->master_ch_list) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - FL("NULL parameters")); + sap_err("NULL parameters"); return QDF_STATUS_E_FAULT; } @@ -2844,15 +2662,13 @@ wlansap_get_safe_channel(struct sap_context *sap_ctx) QDF_STATUS status; if (!sap_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - FL("NULL parameters")); + sap_err("NULL parameters"); return INVALID_CHANNEL_ID; } hal = CDS_GET_HAL_CB(); if (!hal) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid HAL pointer", __func__); + sap_err("Invalid HAL pointer"); return QDF_STATUS_E_FAULT; } @@ -2863,8 +2679,7 @@ wlansap_get_safe_channel(struct sap_context *sap_ctx) pcl.pcl_list, &pcl.pcl_len); if (QDF_IS_STATUS_ERROR(status)) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - FL("Error in getting valid channels")); + sap_err("Error in getting valid channels"); return INVALID_CHANNEL_ID; } @@ -2872,8 +2687,7 @@ wlansap_get_safe_channel(struct sap_context *sap_ctx) pcl.pcl_list, &pcl.pcl_len); if (QDF_IS_STATUS_ERROR(status)) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - FL("failed to filter ch from acs %d"), status); + sap_err("failed to filter ch from acs %d", status); return INVALID_CHANNEL_ID; } @@ -2883,14 +2697,12 @@ wlansap_get_safe_channel(struct sap_context *sap_ctx) &pcl.pcl_len, PM_SAP_MODE); if (QDF_IS_STATUS_ERROR(status)) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - FL("get valid channel: %d failed"), status); + sap_err("get valid channel: %d failed", status); return INVALID_CHANNEL_ID; } if (pcl.pcl_len) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, - FL("select %d from valid channel list"), + sap_debug("select %d from valid channel list", pcl.pcl_list[0]); return pcl.pcl_list[0]; } @@ -2925,15 +2737,13 @@ wlansap_get_safe_channel_from_pcl_and_acs_range(struct sap_context *sap_ctx) QDF_STATUS status; if (!sap_ctx) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - FL("NULL parameter")); + sap_err("NULL parameter"); return INVALID_CHANNEL_ID; } hal = CDS_GET_HAL_CB(); if (!hal) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - "%s: Invalid HAL pointer", __func__); + sap_err("Invalid HAL pointer"); return QDF_STATUS_E_FAULT; } @@ -2944,8 +2754,7 @@ wlansap_get_safe_channel_from_pcl_and_acs_range(struct sap_context *sap_ctx) pcl.weight_list, QDF_ARRAY_SIZE(pcl.weight_list), false); if (QDF_IS_STATUS_ERROR(status)) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - FL("Get PCL failed")); + sap_err("Get PCL failed"); return INVALID_CHANNEL_ID; } @@ -2954,22 +2763,18 @@ wlansap_get_safe_channel_from_pcl_and_acs_range(struct sap_context *sap_ctx) pcl.pcl_list, &pcl.pcl_len); if (QDF_IS_STATUS_ERROR(status)) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_ERROR, - FL("failed filter ch from acs %d"), status); + sap_err("failed filter ch from acs %d", status); return INVALID_CHANNEL_ID; } if (pcl.pcl_len) { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, - FL("select %d from valid channel list"), + sap_debug("select %d from valid channel list", pcl.pcl_list[0]); return pcl.pcl_list[0]; } - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, - FL("no safe channel from PCL found in ACS range")); + sap_debug("no safe channel from PCL found in ACS range"); } else { - QDF_TRACE(QDF_MODULE_ID_SAP, QDF_TRACE_LEVEL_DEBUG, - FL("pcl length is zero!")); + sap_debug("pcl length is zero!"); } /* diff --git a/drivers/staging/qcacld-3.0/core/sme/inc/csr_api.h b/drivers/staging/qcacld-3.0/core/sme/inc/csr_api.h index 781de103d26d..62c2fc51e57f 100644 --- a/drivers/staging/qcacld-3.0/core/sme/inc/csr_api.h +++ b/drivers/staging/qcacld-3.0/core/sme/inc/csr_api.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -33,6 +33,9 @@ #define CSR_INVALID_SCANRESULT_HANDLE (NULL) #define CSR_NUM_WLM_LATENCY_LEVEL 4 +#define CFG_PMKID_MODES_OKC (0x1) +#define CFG_PMKID_MODES_PMKSA_CACHING (0x2) + typedef enum { /* never used */ eCSR_AUTH_TYPE_NONE, @@ -67,6 +70,8 @@ typedef enum { eCSR_AUTH_TYPE_OWE, eCSR_AUTH_TYPE_SUITEB_EAP_SHA256, eCSR_AUTH_TYPE_SUITEB_EAP_SHA384, + eCSR_AUTH_TYPE_FT_SAE, + eCSR_AUTH_TYPE_FT_SUITEB_EAP_SHA384, eCSR_NUM_OF_SUPPORT_AUTH_TYPE, eCSR_AUTH_TYPE_FAILED = 0xff, eCSR_AUTH_TYPE_UNKNOWN = eCSR_AUTH_TYPE_FAILED, @@ -478,6 +483,7 @@ typedef enum { eCSR_ROAM_SAE_COMPUTE, /* LFR3 Roam sync complete */ eCSR_ROAM_SYNCH_COMPLETE, + eCSR_ROAM_FIPS_PMK_REQUEST, } eRoamCmdStatus; /* comment inside indicates what roaming callback gets */ @@ -915,6 +921,7 @@ typedef struct tagCsrRoamHTProfile { uint8_t apChanWidth; } tCsrRoamHTProfile; #endif + typedef struct tagCsrRoamConnectedProfile { tSirMacSSid SSID; bool handoffPermitted; @@ -929,6 +936,9 @@ typedef struct tagCsrRoamConnectedProfile { tCsrEncryptionList EncryptionInfo; eCsrEncryptionType mcEncryptionType; tCsrEncryptionList mcEncryptionInfo; + /* group management cipher suite used for 11w */ + tAniEdType mgmt_encryption_type; + uint8_t country_code[WNI_CFG_COUNTRY_CODE_LEN]; uint32_t vht_channel_width; tCsrKeys Keys; /* @@ -1205,6 +1215,14 @@ typedef struct tagCsrConfigParam { uint32_t roam_preauth_retry_count; uint32_t roam_preauth_no_ack_timeout; bool isRoamOffloadEnabled; + uint32_t roam_triggers; + bool enable_disconnect_roam_offload; + bool enable_idle_roam; + uint32_t idle_roam_rssi_delta; + uint32_t idle_roam_inactive_time; + uint32_t idle_data_packet_count; + uint32_t idle_roam_band; + int32_t idle_roam_min_rssi; #endif bool obssEnabled; uint8_t conc_custom_rule1; @@ -1300,9 +1318,12 @@ typedef struct tagCsrConfigParam { uint8_t oce_feature_bitmap; struct csr_mbo_thresholds mbo_thresholds; uint32_t btm_offload_config; + uint32_t pmkid_modes; uint32_t btm_solicited_timeout; uint32_t btm_max_attempt_cnt; uint32_t btm_sticky_time; + uint32_t btm_query_bitmask; + uint32_t btm_trig_min_candidate_score; uint32_t offload_11k_enable_bitmask; bool wep_tkip_in_he; struct csr_neighbor_report_offload_params neighbor_report_offload; @@ -1313,6 +1334,24 @@ typedef struct tagCsrConfigParam { bool enable_bss_load_roam_trigger; uint32_t bss_load_threshold; uint32_t bss_load_sample_time; + int32_t bss_load_trigger_rssi_threshold_5ghz; + int32_t bss_load_trigger_rssi_threshold_24ghz; + uint32_t roam_scan_inactivity_time; + uint32_t roam_inactive_data_packet_count; + uint32_t roam_scan_period_after_inactivity; + int32_t disconnect_roam_min_rssi; + int32_t bmiss_roam_min_rssi; + uint32_t btm_roam_score_delta; + uint32_t idle_roam_score_delta; +#ifdef WLAN_ADAPTIVE_11R + bool enable_adaptive_11r; +#endif +#if defined(WLAN_SAE_SINGLE_PMK) && defined(WLAN_FEATURE_ROAM_OFFLOAD) + bool sae_single_pmk_feature_enabled; +#endif + bool enable_pending_list_req; + bool disable_4way_hs_offload; + bool p2p_disable_roam; } tCsrConfigParam; /* Tush */ @@ -1320,6 +1359,11 @@ typedef struct tagCsrUpdateConfigParam { tCsr11dinfo Csr11dinfo; } tCsrUpdateConfigParam; #ifdef WLAN_FEATURE_ROAM_OFFLOAD +typedef void (*sme_get_raom_scan_ch_Callback)( + hdd_handle_t hdd_handle, + struct roam_scan_ch_resp *roam_ch, + void *context); + #define csr_roamIsRoamOffloadEnabled(pMac) \ (pMac->roam.configParam.isRoamOffloadEnabled) #define DEFAULT_REASSOC_FAILURE_TIMEOUT 1000 @@ -1412,7 +1456,8 @@ struct csr_roam_info { #ifdef WLAN_FEATURE_ROAM_OFFLOAD uint8_t roamSynchInProgress; uint8_t synchAuthStatus; - uint8_t kck[SIR_KCK_KEY_LEN]; + uint8_t kck[KCK_256BIT_KEY_LEN]; + uint8_t kck_len; uint8_t kek[SIR_KEK_KEY_LEN_FILS]; uint8_t kek_len; uint32_t pmk_len; @@ -1465,6 +1510,7 @@ struct csr_roam_info { struct sir_sae_info *sae_info; #endif uint16_t roam_reason; + struct wlan_ies *disconnect_ies; }; typedef struct tagCsrFreqScanInfo { @@ -1506,6 +1552,8 @@ typedef struct sSirSmeAssocIndToUpperLayerCnf { /* Extended capabilities of STA */ uint8_t ecsa_capable; + uint32_t ies_len; + uint8_t *ies; tDot11fIEHTCaps ht_caps; tDot11fIEVHTCaps vht_caps; tSirMacCapabilityInfo capability_info; @@ -1707,10 +1755,45 @@ typedef QDF_STATUS (*csr_session_close_cb)(uint8_t session_id); #ifdef WLAN_FEATURE_SAE #define CSR_IS_AUTH_TYPE_SAE(auth_type) \ (eCSR_AUTH_TYPE_SAE == auth_type) + +#define CSR_IS_AKM_FT_SAE(auth_type) \ + (eCSR_AUTH_TYPE_FT_SAE == (auth_type)) + +#define CSR_IS_FW_FT_SAE_SUPPORTED(fw_akm_bitmap) \ + (((fw_akm_bitmap) & (1 << AKM_FT_SAE)) ? true : false) + +#define CSR_IS_FW_SAE_ROAM_SUPPORTED(fw_akm_bitmap) \ + (((fw_akm_bitmap) & (1 << AKM_SAE)) ? true : false) + #else #define CSR_IS_AUTH_TYPE_SAE(auth_type) (false) + +#define CSR_IS_AKM_FT_SAE(auth_type) (false) + +#define CSR_IS_FW_FT_SAE_SUPPORTED(fw_akm_bitmap) (false) +#define CSR_IS_FW_SAE_ROAM_SUPPORTED(fw_akm_bitmap) (false) #endif +#define CSR_IS_FW_OWE_ROAM_SUPPORTED(fw_akm_bitmap) \ + (((fw_akm_bitmap) & (1 << AKM_OWE)) ? true : false) + +#define CSR_IS_AKM_FT_SUITEB_SHA384(auth_type) \ + (eCSR_AUTH_TYPE_FT_SUITEB_EAP_SHA384 == (auth_type)) + +#define CSR_IS_AKM_FILS(auth_type) \ + ((eCSR_AUTH_TYPE_FILS_SHA256 == auth_type) || \ + (eCSR_AUTH_TYPE_FILS_SHA384 == auth_type)) + +#define CSR_IS_AKM_FT_FILS(auth_type) \ + ((eCSR_AUTH_TYPE_FT_FILS_SHA256 == (auth_type)) || \ + (eCSR_AUTH_TYPE_FT_FILS_SHA384 == (auth_type))) + +#define CSR_IS_FW_FT_SUITEB_SUPPORTED(fw_akm_bitmap) \ + (((fw_akm_bitmap) & (1 << AKM_FT_SUITEB_SHA384)) ? true : false) + +#define CSR_IS_FW_FT_FILS_SUPPORTED(fw_akm_bitmap) \ + (((fw_akm_bitmap) & (1 << AKM_FT_FILS)) ? true : false) + QDF_STATUS csr_set_channels(tpAniSirGlobal pMac, tCsrConfigParam *pParam); /* enum to string conversion for debug output */ @@ -1786,4 +1869,24 @@ csr_get_channel_status(tpAniSirGlobal mac, uint32_t channel_id); * Return: none */ void csr_clear_channel_status(tpAniSirGlobal mac); + +typedef void (*csr_ani_callback)(int8_t *ani, void *context); + +#ifdef WLAN_FEATURE_11W +/** + * csr_update_pmf_cap_from_connected_profile() - Update pmf cap from profile + * @profile: connected profile + * @filter: scan filter + * + * Return: None + */ +void +csr_update_pmf_cap_from_connected_profile(tCsrRoamConnectedProfile *profile, + struct scan_filter *filter); +#else +static inline void +csr_update_pmf_cap_from_connected_profile(tCsrRoamConnectedProfile *profile, + struct scan_filter *filter) +{} +#endif #endif diff --git a/drivers/staging/qcacld-3.0/core/sme/inc/csr_internal.h b/drivers/staging/qcacld-3.0/core/sme/inc/csr_internal.h index 5eee9c552dff..ddf9aa6d02a9 100644 --- a/drivers/staging/qcacld-3.0/core/sme/inc/csr_internal.h +++ b/drivers/staging/qcacld-3.0/core/sme/inc/csr_internal.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -332,7 +332,7 @@ struct roam_cmd { bool fStopWds; tSirMacAddr peerMac; tSirMacReasonCodes reason; - eCsrRoamDisconnectReason disconnect_reason; + tSirMacReasonCodes disconnect_reason; }; struct setkey_cmd { @@ -396,7 +396,6 @@ struct csr_neighbor_roamconfig { int32_t nhi_rssi_scan_rssi_ub; uint32_t full_roam_scan_period; bool enable_scoring_for_roam; - uint8_t roam_rssi_diff; }; /* @@ -540,6 +539,14 @@ struct csr_config { uint8_t allowDFSChannelRoam; #ifdef WLAN_FEATURE_ROAM_OFFLOAD bool isRoamOffloadEnabled; + uint32_t roam_triggers; + bool enable_disconnect_roam_offload; + bool enable_idle_roam; + uint32_t idle_roam_rssi_delta; + uint32_t idle_roam_inactive_time; + uint32_t idle_data_packet_count; + uint32_t idle_roam_band; + int32_t idle_roam_min_rssi; #endif bool obssEnabled; bool ignore_peer_erp_info; @@ -613,9 +620,12 @@ struct csr_config { uint8_t oce_feature_bitmap; struct csr_mbo_thresholds mbo_thresholds; uint32_t btm_offload_config; + uint32_t pmkid_modes; uint32_t btm_solicited_timeout; uint32_t btm_max_attempt_cnt; uint32_t btm_sticky_time; + uint32_t btm_query_bitmask; + uint32_t btm_trig_min_candidate_score; uint32_t offload_11k_enable_bitmask; bool wep_tkip_in_he; struct csr_neighbor_report_offload_params neighbor_report_offload; @@ -627,6 +637,25 @@ struct csr_config { uint32_t bss_load_threshold; uint32_t bss_load_sample_time; bool roaming_scan_policy; + int32_t bss_load_trigger_rssi_threshold_5ghz; + int32_t bss_load_trigger_rssi_threshold_24ghz; + uint32_t roam_scan_inactivity_time; + uint32_t roam_inactive_data_packet_count; + uint32_t roam_scan_period_after_inactivity; + int32_t disconnect_roam_min_rssi; + int32_t bmiss_roam_min_rssi; + uint32_t btm_roam_score_delta; + uint32_t idle_roam_score_delta; + uint32_t btm_min_candidate_score; +#ifdef WLAN_ADAPTIVE_11R + bool enable_adaptive_11r; +#endif +#if defined(WLAN_SAE_SINGLE_PMK) && defined(WLAN_FEATURE_ROAM_OFFLOAD) + bool sae_single_pmk_feature_enabled; +#endif + bool enable_pending_list_req; + bool disable_4way_hs_offload; + bool p2p_disable_roam; }; struct csr_channel_powerinfo { @@ -704,6 +733,7 @@ struct csr_scanstruct { bool fcc_constraint; uint8_t max_scan_count; bool defer_update_channel_list; + bool pending_channel_list_req; wlan_scan_requester requester_id; }; @@ -835,11 +865,33 @@ struct csr_disconnect_stats { uint32_t peer_kickout; }; +/** + * struct sme_pmk_info - SAE Roaming using single pmk info + * @pmk: pmk + * @pmk_len: pmk length + */ +struct sme_pmk_info { + uint8_t pmk[SIR_ROAM_SCAN_PSK_SIZE]; + size_t pmk_len; +}; + +/** + * struct csr_sae_single_pmk_info - SAE Roaming using single pmk configurations + * structure + * @sae_single_pmk_ap: Current connected AP has VSIE or not + * @pmk_info: pmk information + */ +struct csr_sae_single_pmk_info { + bool sae_single_pmk_ap; + struct sme_pmk_info pmk_info; +}; + /** * struct csr_roam_session - CSR per-vdev context * @vdev_id: ID of the vdev for which this entry is applicable * @is_bcn_recv_start: Allow to process bcn recv indication * @beacon_report_do_not_resume: Do not resume the beacon reporting after scan + * @single_pmk_info: Details for sae roaming using single pmk */ struct csr_roam_session { uint8_t sessionId; /* Session ID */ @@ -856,6 +908,7 @@ struct csr_roam_session { struct rsn_caps rsn_caps; tCsrRoamConnectedProfile connectedProfile; struct csr_roam_connectedinfo connectedInfo; + struct csr_roam_connectedinfo prev_assoc_ap_info; struct csr_roam_profile *pCurRoamProfile; tSirBssDescription *pConnectBssDesc; uint16_t NumPmkidCache; /* valid number of pmkid in the cache*/ @@ -971,7 +1024,11 @@ struct csr_roam_session { bool is_fils_connection; uint16_t fils_seq_num; bool discon_in_progress; + bool is_adaptive_11r_connection; struct csr_disconnect_stats disconnect_stats; +#if defined(WLAN_SAE_SINGLE_PMK) && defined(WLAN_FEATURE_ROAM_OFFLOAD) + struct csr_sae_single_pmk_info single_pmk_info; +#endif }; struct csr_roamstruct { diff --git a/drivers/staging/qcacld-3.0/core/sme/inc/csr_neighbor_roam.h b/drivers/staging/qcacld-3.0/core/sme/inc/csr_neighbor_roam.h index a43a8bc7bd2a..0fe7bbfe4ff1 100644 --- a/drivers/staging/qcacld-3.0/core/sme/inc/csr_neighbor_roam.h +++ b/drivers/staging/qcacld-3.0/core/sme/inc/csr_neighbor_roam.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -43,6 +43,7 @@ typedef enum { /* Parameters that are obtained from CFG */ typedef struct sCsrNeighborRoamCfgParams { + uint32_t roam_trigger_bitmap; uint8_t maxNeighborRetries; uint32_t neighborScanPeriod; uint32_t neighbor_scan_min_period; @@ -70,6 +71,9 @@ typedef struct sCsrNeighborRoamCfgParams { uint8_t roam_rssi_diff; uint16_t roam_scan_home_away_time; uint8_t roam_scan_n_probes; + uint32_t roam_scan_inactivity_time; + uint32_t roam_inactive_data_packet_count; + uint32_t roam_scan_period_after_inactivity; } tCsrNeighborRoamCfgParams, *tpCsrNeighborRoamCfgParams; #define CSR_NEIGHBOR_ROAM_INVALID_CHANNEL_INDEX 255 @@ -342,6 +346,11 @@ void csr_roam_reset_roam_params(tpAniSirGlobal mac_ptr); #define REASON_DRIVER_ENABLED 43 #define REASON_ROAM_FULL_SCAN_PERIOD_CHANGED 44 #define REASON_SCORING_CRITERIA_CHANGED 45 +#define REASON_SUPPLICANT_INIT_ROAMING 46 +#define REASON_SUPPLICANT_DE_INIT_ROAMING 47 +#define REASON_DRIVER_DISABLED 48 +#define REASON_ROAM_CONTROL_CONFIG_RESTORED 49 +#define REASON_ROAM_CONTROL_CONFIG_ENABLED 50 #if defined(WLAN_FEATURE_HOST_ROAM) || defined(WLAN_FEATURE_ROAM_OFFLOAD) QDF_STATUS csr_roam_offload_scan(tpAniSirGlobal pMac, uint8_t sessionId, @@ -401,6 +410,92 @@ QDF_STATUS csr_roam_read_tsf(tpAniSirGlobal pMac, uint8_t *pTimestamp, QDF_STATUS csr_roam_synch_callback(tpAniSirGlobal mac, roam_offload_synch_ind *roam_synch_data, tpSirBssDescription bss_desc_ptr, enum sir_roam_op_code reason); + +/* + * csr_roam_send_rso_cmd() - API to send RSO command to PE + * @mac_ctx: Pointer to global MAC structure + * @vdev_id: Session ID + * @request_buf: Pointer to tSirRoamOffloadScanReq + * + * Return: QDF_STATUS + */ +QDF_STATUS csr_roam_send_rso_cmd(tpAniSirGlobal mac_ctx, uint8_t vdev_id, + tSirRoamOffloadScanReq *request_buf); + +/** + * csr_roam_auth_offload_callback() - Registered CSR Callback function to handle + * WPA3 roam pre-auth event from firmware. + * @mac_ctx: Global mac context pointer + * @vdev_id: Vdev id + * @bssid: candidate AP bssid + */ +QDF_STATUS +csr_roam_auth_offload_callback(tpAniSirGlobal mac_ctx, uint8_t vdev_id, + struct qdf_mac_addr bssid); + +/** + * csr_fast_reassoc() - invokes FAST REASSOC command + * @hal: handle returned by mac_open + * @profile: current connected profile + * @bssid: bssid to look for in scan cache + * @channel: channel on which reassoc should be send + * @vdev_id: vdev id + * @connected_bssid: bssid of currently connected profile + * + * Return: QDF_STATUS + */ +QDF_STATUS csr_fast_reassoc(tHalHandle hal, struct csr_roam_profile *profile, + const tSirMacAddr bssid, int channel, + uint8_t vdev_id, const tSirMacAddr connected_bssid); + +/** + * csr_process_roam_auth_offload_callback() - API to trigger the + * WPA3 pre-auth event for candidate AP received from firmware. + * @vdev_id: vdev id + * @roam_bssid: Candidate BSSID to roam + * + * This function calls the hdd_sme_roam_callback with reason + * eCSR_ROAM_SAE_COMPUTE to trigger SAE auth to supplicant. + */ +QDF_STATUS +csr_process_roam_auth_offload_callback(tpAniSirGlobal mac_ctx, + uint8_t vdev_id, + struct qdf_mac_addr roam_bssid); + +#ifdef WLAN_FEATURE_FIPS +/** + * csr_roam_pmkid_req_callback() - Registered CSR Callback function to handle + * roam event from firmware for pmkid generation fallback. + * @vdev_id: Vdev id + * @bss_list: candidate AP bssid list + */ +QDF_STATUS +csr_roam_pmkid_req_callback(uint8_t vdev_id, + struct roam_pmkid_req_event *bss_list); + +/** + * csr_process_roam_pmkid_req_callback() - API to trigger the pmkid + * generation fallback event for candidate AP received from firmware. + * @mac_ctx: Global mac context pointer + * @vdev_id: Vdev id + * @roam_bsslist: roam candidate AP bssid list + * + * This function calls the hdd_sme_roam_callback with reason + * eCSR_ROAM_FIPS_PMK_REQUEST to trigger pmkid generation in supplicant. + */ +QDF_STATUS +csr_process_roam_pmkid_req_callback(tpAniSirGlobal mac_ctx, + uint8_t vdev_id, + struct roam_pmkid_req_event *roam_bsslist); +#else +static inline QDF_STATUS +csr_roam_pmkid_req_callback(uint8_t vdev_id, + struct roam_pmkid_req_event *bss_list) +{ + return QDF_STATUS_SUCCESS; +} +#endif /* WLAN_FEATURE_FIPS */ + #else static inline QDF_STATUS csr_roam_synch_callback(tpAniSirGlobal mac, roam_offload_synch_ind *roam_synch_data, @@ -408,6 +503,44 @@ static inline QDF_STATUS csr_roam_synch_callback(tpAniSirGlobal mac, { return QDF_STATUS_E_NOSUPPORT; } + +static inline QDF_STATUS +csr_roam_auth_offload_callback(tpAniSirGlobal mac_ctx, + uint8_t vdev_id, + struct qdf_mac_addr bssid) +{ + return QDF_STATUS_E_NOSUPPORT; +} + +static inline +QDF_STATUS csr_fast_reassoc(tHalHandle hal, struct csr_roam_profile *profile, + const tSirMacAddr bssid, int channel, + uint8_t vdev_id, const tSirMacAddr connected_bssid) +{ + return QDF_STATUS_SUCCESS; +} + +static inline QDF_STATUS +csr_process_roam_auth_offload_callback(tpAniSirGlobal mac_ctx, + uint8_t vdev_id, + struct qdf_mac_addr roam_bssid) +{ + return QDF_STATUS_E_NOSUPPORT; +} + +static inline QDF_STATUS +csr_roam_send_rso_cmd(tpAniSirGlobal mac_ctx, uint8_t vdev_id, + tSirRoamOffloadScanReq *request_buf) +{ + return QDF_STATUS_E_NOSUPPORT; +} + +static inline QDF_STATUS +csr_roam_pmkid_req_callback(uint8_t vdev_id, + struct roam_pmkid_req_event *bss_list) +{ + return QDF_STATUS_E_NOSUPPORT; +} #endif void csr_neighbor_roam_state_transition(tpAniSirGlobal mac_ctx, uint8_t newstate, uint8_t session); diff --git a/drivers/staging/qcacld-3.0/core/sme/inc/csr_support.h b/drivers/staging/qcacld-3.0/core/sme/inc/csr_support.h index a076aa192502..92f626c7a6e1 100644 --- a/drivers/staging/qcacld-3.0/core/sme/inc/csr_support.h +++ b/drivers/staging/qcacld-3.0/core/sme/inc/csr_support.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2019 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -39,7 +39,7 @@ #define CSR_RSN_OUI_SIZE (4) #define CSR_RSN_VERSION_SUPPORTED (1) -#define CSR_RSN_MAX_AUTH_SUITES (4) +#define CSR_RSN_MAX_AUTH_SUITES (5) #define CSR_RSN_MAX_CYPHERS (5) #define CSR_RSN_MAX_UNICAST_CYPHERS (5) #define CSR_RSN_MAX_MULTICAST_CYPHERS (1) @@ -200,7 +200,7 @@ typedef struct tagCsrWapiIe { typedef struct tagRoamingTimerInfo { tpAniSirGlobal pMac; - uint8_t sessionId; + uint8_t vdev_id; } tCsrTimerInfo; #define CSR_IS_11A_BSS(pBssDesc) (eSIR_11A_NW_TYPE == (pBssDesc)->nwType) diff --git a/drivers/staging/qcacld-3.0/core/sme/inc/sme_api.h b/drivers/staging/qcacld-3.0/core/sme/inc/sme_api.h index 3e75aae8e5e5..9ed71c32bc3a 100644 --- a/drivers/staging/qcacld-3.0/core/sme/inc/sme_api.h +++ b/drivers/staging/qcacld-3.0/core/sme/inc/sme_api.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -43,6 +43,7 @@ #include "scheduler_api.h" #include "wlan_serialization_legacy_api.h" #include "wmi_unified.h" +#include "wmi_unified_param.h" /*-------------------------------------------------------------------------- Preprocessor definitions and constants @@ -59,6 +60,17 @@ #define sme_info(params...) QDF_TRACE_INFO(QDF_MODULE_ID_SME, params) #define sme_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_SME, params) +#define sme_nofl_alert(params...) \ + QDF_TRACE_FATAL_NO_FL(QDF_MODULE_ID_SME, params) +#define sme_nofl_err(params...) \ + QDF_TRACE_ERROR_NO_FL(QDF_MODULE_ID_SME, params) +#define sme_nofl_warn(params...) \ + QDF_TRACE_WARN_NO_FL(QDF_MODULE_ID_SME, params) +#define sme_nofl_info(params...) \ + QDF_TRACE_INFO_NO_FL(QDF_MODULE_ID_SME, params) +#define sme_nofl_debug(params...) \ + QDF_TRACE_DEBUG_NO_FL(QDF_MODULE_ID_SME, params) + #define sme_alert_rl(params...) QDF_TRACE_FATAL_RL(QDF_MODULE_ID_SME, params) #define sme_err_rl(params...) QDF_TRACE_ERROR_RL(QDF_MODULE_ID_SME, params) #define sme_warn_rl(params...) QDF_TRACE_WARN_RL(QDF_MODULE_ID_SME, params) @@ -343,6 +355,16 @@ QDF_STATUS sme_open_session(tHalHandle hal, struct sme_session_params *params); * Other status means SME is failed to open the session. */ QDF_STATUS sme_close_session(tHalHandle hal, uint8_t sessionId); + +/** + * sme_cleanup_session() - clean up sme session info for vdev + * @mac_handle: mac handle + * @vdev_id: vdev id + * + * Return: none + */ +void sme_cleanup_session(mac_handle_t mac_handle, uint8_t vdev_id); + void sme_set_curr_device_mode(tHalHandle hHal, enum QDF_OPMODE currDeviceMode); QDF_STATUS sme_update_roam_params(tHalHandle hHal, uint8_t session_id, @@ -456,11 +478,13 @@ QDF_STATUS sme_roam_connect_to_last_profile(tHalHandle hHal, uint8_t sessionId); * @hal: HAL context * @session: SME session identifier * @reason: Reason to disconnect + * @mac_reason: Reason to disconnect as per enum eSirMacReasonCodes * * Return: QDF Status success or failure */ QDF_STATUS sme_roam_disconnect(tHalHandle hal, uint8_t session, - eCsrRoamDisconnectReason reason); + eCsrRoamDisconnectReason reason, + tSirMacReasonCodes mac_reason); void sme_dhcp_done_ind(tHalHandle hal, uint8_t session_id); QDF_STATUS sme_roam_stop_bss(tHalHandle hHal, uint8_t sessionId); @@ -483,6 +507,30 @@ QDF_STATUS sme_roam_set_pmkid_cache(tHalHandle hHal, uint8_t sessionId, bool update_entire_cache); #ifdef WLAN_FEATURE_ROAM_OFFLOAD +/** + * sme_set_roam_scan_ch_event_cb() - Register roam scan ch callback + * @mac_handle: Opaque handle to the MAC context + * @cb: callback to be registered + * + * Return: QDF_STATUS + */ +QDF_STATUS +sme_set_roam_scan_ch_event_cb(mac_handle_t mac_handle, + sme_get_raom_scan_ch_Callback cb); + +/** + * sme_get_roam_scan_ch() sme api to get roam scan channel list + * @hal: hal handle + * @vdev_id: vdev id + * @pcontext: pointer to cookie + * + * This API is used to get roam scan channels form firmware. + * + * Return: QDF_STATUS + */ +QDF_STATUS sme_get_roam_scan_ch(tHalHandle hal, uint8_t vdev_id, + void *pcontext); + /** * sme_get_pmk_info(): A wrapper function to request CSR to save PMK * @hal: Global structure @@ -496,6 +544,20 @@ void sme_get_pmk_info(tHalHandle hal, uint8_t session_id, QDF_STATUS sme_roam_set_psk_pmk(tHalHandle hHal, uint8_t sessionId, uint8_t *pPSK_PMK, size_t pmk_len); +#else +static inline QDF_STATUS +sme_get_roam_scan_ch(tHalHandle hal, uint8_t vdev_id, + void *pcontext) +{ + return QDF_STATUS_E_FAILURE; +} + +static inline QDF_STATUS +sme_set_roam_scan_ch_event_cb(mac_handle_t mac_handle, + void *cb) +{ + return QDF_STATUS_E_FAILURE; +} #endif /** @@ -554,6 +616,7 @@ QDF_STATUS sme_get_rssi(tHalHandle hHal, QDF_STATUS sme_get_snr(tHalHandle hHal, tCsrSnrCallback callback, uint8_t staId, struct qdf_mac_addr bssId, void *pContext); + #ifdef FEATURE_WLAN_ESE QDF_STATUS sme_get_tsm_stats(tHalHandle hHal, tCsrTsmStatsCallback callback, @@ -673,8 +736,29 @@ QDF_STATUS sme_get_wcnss_software_version(tHalHandle hHal, uint8_t *pVersion, uint32_t versionBufferSize); QDF_STATUS sme_get_wcnss_hardware_version(tHalHandle hHal, uint8_t *pVersion, uint32_t versionBufferSize); + +#ifdef FEATURE_OEM_DATA +/** + * sme_oem_data_cmd() - the wrapper to send oem data cmd to wma + * @mac_handle: Opaque handle to the global MAC context. + * @oem_data: the pointer of oem data + * + * Return: QDF_STATUS + */ +QDF_STATUS sme_oem_data_cmd(mac_handle_t mac_handle, + struct oem_data *oem_data); +#endif + #ifdef FEATURE_OEM_DATA_SUPPORT -QDF_STATUS sme_oem_data_req(tHalHandle hHal, struct oem_data_req *); +/** + * sme_oem_req_cmd() - send oem request cmd to WMA + * @mac_handle: Opaque handle to the global MAC context + * @oem_req: OEM data request + * + * Return: QDF_STATUS + */ +QDF_STATUS sme_oem_req_cmd(mac_handle_t mac_handle, + struct oem_data_req *oem_req); QDF_STATUS sme_oem_update_capability(tHalHandle hHal, struct sme_oem_capability *cap); QDF_STATUS sme_oem_get_capability(tHalHandle hHal, @@ -1048,6 +1132,7 @@ QDF_STATUS sme_send_rate_update_ind(tHalHandle hHal, tSirRateUpdateInd *rateUpdateParams); QDF_STATUS sme_roam_del_pmkid_from_cache(tHalHandle hHal, uint8_t sessionId, tPmkidCacheInfo *pmksa, bool flush_cache); + void sme_get_command_q_status(tHalHandle hHal); QDF_STATUS sme_enable_rmc(tHalHandle hHal, uint32_t sessionId); @@ -1057,6 +1142,24 @@ QDF_STATUS sme_request_ibss_peer_info(tHalHandle hHal, void *pUserData, pIbssPeerInfoCb peerInfoCbk, bool allPeerInfoReqd, uint8_t staIdx); QDF_STATUS sme_send_cesium_enable_ind(tHalHandle hHal, uint32_t sessionId); +#ifdef WLAN_SEND_DSCP_UP_MAP_TO_FW +/** + * sme_send_dscp_up_map_to_fw() - send DSCP-to-UP map values to fw + * @dscp_to_up_map: array of DSCP-to-UP map values + * + * Used to send DSCP-to-UP map values to fw + * + * Return QDF_STATUS + */ +QDF_STATUS sme_send_dscp_up_map_to_fw(uint32_t *dscp_to_up_map); +#else +static inline +QDF_STATUS sme_send_dscp_up_map_to_fw(uint32_t *dscp_to_up_map) +{ + return QDF_STATUS_SUCCESS; +} +#endif + /** * sme_set_wlm_latency_level_ind() - Used to set the latency level to fw * @hal @@ -1195,10 +1298,11 @@ QDF_STATUS sme_update_dfs_scan_mode(tHalHandle hHal, uint8_t allowDFSChannelRoam); uint8_t sme_get_dfs_scan_mode(tHalHandle hHal); -#ifdef FEATURE_WLAN_EXTSCAN QDF_STATUS sme_get_valid_channels_by_band(tHalHandle hHal, uint8_t wifiBand, uint32_t *aValidChannels, uint8_t *pNumChannels); + +#ifdef FEATURE_WLAN_EXTSCAN QDF_STATUS sme_ext_scan_get_capabilities(tHalHandle hHal, tSirGetExtScanCapabilitiesReqParams *pReq); QDF_STATUS sme_ext_scan_start(tHalHandle hHal, @@ -1683,7 +1787,27 @@ sme_apf_read_work_memory(tHalHandle hal, #endif /* FEATURE_WLAN_APF */ uint32_t sme_get_wni_dot11_mode(tHalHandle hal); -QDF_STATUS sme_create_mon_session(tHalHandle hal_handle, uint8_t *bssid); + +/** + * sme_create_mon_session() - post message to create PE session for monitormode + * operation + * @hal_handle: Handle to the HAL + * @bssid: pointer to bssid + * @vdev_id: vdev id + * + * Return: QDF_STATUS_SUCCESS on success, non-zero error code on failure. + */ +QDF_STATUS sme_create_mon_session(tHalHandle hal_handle, + uint8_t *bssid, uint8_t vdev_id); +/** + * sme_delete_mon_session() - post message to delete PE session for mon_mode + * operation + * @mac_handle: Opaque handle to the global MAC context + * @vdev_id: sme session id + * + * Return: QDF_STATUS_SUCCESS on success, non-zero error code on failure. + */ +QDF_STATUS sme_delete_mon_session(mac_handle_t mac_handle, uint8_t vdev_id); QDF_STATUS sme_set_adaptive_dwelltime_config(tHalHandle hal, struct adaptive_dwelltime_params *dwelltime_params); @@ -2160,17 +2284,6 @@ QDF_STATUS sme_set_bt_activity_info_cb(mac_handle_t mac_handle, QDF_STATUS sme_set_smps_cfg(uint32_t vdev_id, uint32_t param_id, uint32_t param_val); -/** - * sme_get_peer_stats() - sme api to post peer info request - * @mac: mac handle - * @req: peer info request struct send to wma - * - * Return: QDF_STATUS_SUCCESS or non-zero on failure - */ - -QDF_STATUS sme_get_peer_stats(tpAniSirGlobal mac, - struct sir_peer_info_req req); - /** * sme_get_peer_info() - sme api to get peer info * @hal: hal handle for getting global mac struct @@ -2345,31 +2458,61 @@ QDF_STATUS sme_set_del_pmkid_cache(tHalHandle hal, uint8_t session_id, /** * sme_send_hlp_ie_info() - API to send HLP IE info to fw * @hal: HAL handle for device - * @session_id: Session id + * @vdev_id: vdev id * @profile: CSR Roam profile * @if_addr: IP address * * This API is used to send HLP IE info along with IP address * to fw if LFR3 is enabled. * - * Return: QDF_STATUS + * Return: None */ -void sme_send_hlp_ie_info(tHalHandle hal, uint8_t session_id, +void sme_send_hlp_ie_info(mac_handle_t hal, uint8_t vdev_id, struct csr_roam_profile *profile, uint32_t if_addr); +/** + * sme_update_session_assoc_ie() - Updates the assoc IEs to csr_roam_session + * @hal: Opaque handle to the global MAC context + * @vdev_id: vdev id + * @src_profile: Pointer to Roam profile in HDD + * + * This API is used to copy the assoc IE sent from user space to + * csr_roam_session + * + * Return: None + */ +void sme_update_session_assoc_ie(mac_handle_t hal, + uint8_t vdev_id, + struct csr_roam_profile *src_profile); + +/** + * sme_send_rso_connect_params() - Updates the assoc IEs to csr_roam_session + * @mac_handle: Opaque handle to the global MAC context + * @vdev_id: vdev id + * @src_profile: CSR Roam profile + * + * When the user space updates the assoc IEs or FILS auth type or FILS ERP info, + * host driver needs to send these updated parameters to firmware via + * RSO update command. + * + * Return: None + */ +QDF_STATUS sme_send_rso_connect_params(mac_handle_t mac_handle, + uint8_t vdev_id, + struct csr_roam_profile *src_profile); + #if defined(WLAN_FEATURE_FILS_SK) /** * sme_update_fils_config - Update FILS config to CSR roam session * @hal: HAL handle for device - * @session_id: session id + * @vdev_id: vdev id * @src_profile: Source profile having latest FILS config * - * API to update FILS config to roam csr session and update the same - * to fw if LFR3 is enabled. + * API to update FILS config to roam csr session. * * Return: QDF_STATUS */ -QDF_STATUS sme_update_fils_config(tHalHandle hal, uint8_t session_id, +QDF_STATUS sme_update_fils_config(tHalHandle hal, uint8_t vdev_id, struct csr_roam_profile *src_profile); /** @@ -2381,7 +2524,7 @@ QDF_STATUS sme_update_fils_config(tHalHandle hal, uint8_t session_id, void sme_free_join_rsp_fils_params(struct csr_roam_info *roam_info); #else static inline QDF_STATUS sme_update_fils_config(tHalHandle hal, - uint8_t session_id, + uint8_t vdev_id, struct csr_roam_profile *src_profile) { return QDF_STATUS_SUCCESS; @@ -2522,17 +2665,26 @@ QDF_STATUS sme_send_mgmt_tx(tHalHandle hal, uint8_t session_id, #ifdef WLAN_FEATURE_SAE /** * sme_handle_sae_msg() - Sends SAE message received from supplicant - * @hal: The handle returned by mac_open + * @mac_handle: The handle returned by mac_open * @session_id: session id * @sae_status: status of SAE authentication + * @peer_mac_addr: mac address of the peer to be authenticated + * @pmkid: PMKID derived at the end of SAE authentication * * Return: QDF_STATUS */ -QDF_STATUS sme_handle_sae_msg(tHalHandle hal, uint8_t session_id, - uint8_t sae_status); +QDF_STATUS sme_handle_sae_msg(mac_handle_t mac_handle, + uint8_t session_id, + uint8_t sae_status, + struct qdf_mac_addr peer_mac_addr, + const uint8_t *pmkid); + #else -static inline QDF_STATUS sme_handle_sae_msg(tHalHandle hal, uint8_t session_id, - uint8_t sae_status) +QDF_STATUS sme_handle_sae_msg(mac_handle_t mac_handle, + uint8_t session_id, + uint8_t sae_status, + struct qdf_mac_addr peer_mac_addr, + const uint8_t *pmkid) { return QDF_STATUS_SUCCESS; } @@ -2942,4 +3094,127 @@ uint16_t sme_get_full_roam_scan_period_global(mac_handle_t mac_handle); QDF_STATUS sme_get_full_roam_scan_period(mac_handle_t mac_handle, uint8_t vdev_id, uint32_t *full_roam_scan_period); + +/** + * sme_set_roam_triggers() - Send roam trigger bitmap to WMA + * @mac_handle: Opaque handle to the MAC context + * @triggers: Carries pointer of the object containing vdev id and + * roam_trigger_bitmap. + * + * Send the roam trigger bitmap received to WMA/WMI. WMI converts + * the bitmap to firmware compatible bitmap as per reasons + * defined @WMI_ROAM_TRIGGER_REASON_ID + * + * Return: QDF_STATUS + */ +QDF_STATUS sme_set_roam_triggers(mac_handle_t mac_handle, + struct roam_triggers *triggers); + +/** + * sme_roam_control_restore_default_config - Restore roam config to default + * @mac_handle: Opaque handle to the global MAC context + * @vdev_id: vdev Identifier + * + * Restore enable_scoring_for_roam, emptyScanRefreshPeriod, + * full_roam_scan_period to their default values and send RSO command to + * firmware with the updated values. + * + * Return: Success or failure + */ +QDF_STATUS sme_roam_control_restore_default_config(mac_handle_t mac_handle, + uint8_t vdev_id); + +/** + * sme_roam_reset_configs() - API to reset roam configurations + * @mac_handle: Opaque handle to the global MAC context + * @vdev_id: vdev Identifier + * + * Return: void + */ +void sme_roam_reset_configs(mac_handle_t mac_handle, uint8_t vdev_id); + +/** + * sme_set_disconnect_ies() - set disconnect IEs + * @mac_handle: handle returned by mac_open + * @vdev_id: vdev id + * @ie_data: Disconnect IE data + * @ie_len: Disconnect IE length + * + * Return: QDF_STATUS + */ +QDF_STATUS sme_set_disconnect_ies(mac_handle_t mac_handle, uint8_t vdev_id, + uint8_t *ie_data, uint16_t ie_len); + +#ifdef FEATURE_ANI_LEVEL_REQUEST +/* + * sme_get_ani_level() - + * A wrapper function that client calls to register a callback to get ani level + * + * @mac_handle - pointer to mac handle + * @freqs - frequencies for which ANI level has to be fetched + * @num_freqs - number of frequencies + * @callback - SME sends back the ani level using the callback + * @context - user context to be passed back along with the callback + * + * Return: QDF_STATUS + */ +QDF_STATUS sme_get_ani_level(mac_handle_t mac_handle, uint32_t *freqs, + uint8_t num_freqs, void (*callback)( + struct wmi_host_ani_level_event *ani, uint8_t num, + void *context), void *context); +#endif /* FEATURE_ANI_LEVEL_REQUEST */ + +#ifdef FEATURE_OEM_DATA +/** + * sme_set_oem_data_event_handler_cb() - Register oem data event handler + * callback + * @mac_handle: Opaque handle to the MAC context + * @oem_data_event_handler_cb: callback to be registered + * + * Return: QDF_STATUS + */ +QDF_STATUS sme_set_oem_data_event_handler_cb( + mac_handle_t mac_handle, + void (*oem_data_event_handler_cb) + (const struct oem_data *oem_event_data)); + +/** + * sme_reset_oem_data_event_handler_cb() - De-register oem data event handler + * @mac_handle: Handler return by mac_open + * + * This function De-registers the OEM data event handler callback to SME + * + * Return: None + */ +void sme_reset_oem_data_event_handler_cb(mac_handle_t mac_handle); +#else +static inline QDF_STATUS sme_set_oem_data_event_handler_cb( + mac_handle_t mac_handle, + void (*oem_data_event_handler_cb) + (void *oem_event_data)) +{ + return QDF_STATUS_SUCCESS; +} + +static inline void sme_reset_oem_data_event_handler_cb(mac_handle_t mac_handle) +{ +} + +#endif + +/** + * sme_get_prev_connected_bss_ies() - Get the previous connected AP IEs + * @mac_handle: The handle returned by mac_open. + * @vdev_id: vdev id + * @ies: IEs of the disconnected AP. Currently to carry beacon IEs. + * @ie_len: Length of the @ies + * + * This API extracts the IEs from the previous connected AP info and update + * them to the ies and ie_len. + * + * Return: QDF_STATUS + */ +QDF_STATUS sme_get_prev_connected_bss_ies(mac_handle_t mac_handle, + uint8_t vdev_id, + uint8_t **ies, uint32_t *ie_len); #endif /* #if !defined( __SME_API_H ) */ diff --git a/drivers/staging/qcacld-3.0/core/sme/inc/sme_inside.h b/drivers/staging/qcacld-3.0/core/sme/inc/sme_inside.h index 912df5448dd0..4343eb0e61d6 100644 --- a/drivers/staging/qcacld-3.0/core/sme/inc/sme_inside.h +++ b/drivers/staging/qcacld-3.0/core/sme/inc/sme_inside.h @@ -237,6 +237,14 @@ QDF_STATUS csr_roam_send_set_key_cmd(tpAniSirGlobal mac_ctx, QDF_STATUS csr_is_valid_channel(tpAniSirGlobal pMac, uint8_t chnNum); QDF_STATUS sme_acquire_global_lock(tSmeStruct *psSme); + +/** + * sme_get_vht_ch_width() - SME API to get the max supported FW chan width + * + * Return: Max channel width supported by FW (eg. 20, 40, 80, 160, 80+80) + */ +uint32_t sme_get_vht_ch_width(void); + QDF_STATUS sme_release_global_lock(tSmeStruct *psSme); QDF_STATUS csr_process_add_sta_session_rsp(tpAniSirGlobal pMac, uint8_t *pMsg); diff --git a/drivers/staging/qcacld-3.0/core/sme/inc/sme_internal.h b/drivers/staging/qcacld-3.0/core/sme/inc/sme_internal.h index 3cd874802d2b..bf7f34f3eada 100644 --- a/drivers/staging/qcacld-3.0/core/sme/inc/sme_internal.h +++ b/drivers/staging/qcacld-3.0/core/sme/inc/sme_internal.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -38,6 +38,7 @@ #include "sme_power_save.h" #include "nan_api.h" #include "wmi_unified.h" +#include "wmi_unified_param.h" struct wmi_twt_enable_complete_event_param; /*-------------------------------------------------------------------------- @@ -346,6 +347,14 @@ typedef struct tagSmeStruct { beacon_report_cb beacon_report_cb; beacon_pause_cb beacon_pause_cb; #endif +#ifdef FEATURE_OEM_DATA + void (*oem_data_event_handler_cb) + (const struct oem_data *oem_event_data); +#endif +#ifdef WLAN_FEATURE_ROAM_OFFLOAD + sme_get_raom_scan_ch_Callback roam_scan_ch_callback; + void *roam_scan_ch_get_context; +#endif } tSmeStruct, *tpSmeStruct; #endif /* #if !defined( __SMEINTERNAL_H ) */ diff --git a/drivers/staging/qcacld-3.0/core/sme/inc/sme_qos_api.h b/drivers/staging/qcacld-3.0/core/sme/inc/sme_qos_api.h index de71f94feb7c..da4c3914f623 100644 --- a/drivers/staging/qcacld-3.0/core/sme/inc/sme_qos_api.h +++ b/drivers/staging/qcacld-3.0/core/sme/inc/sme_qos_api.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2014-2019 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -133,6 +133,8 @@ enum sme_qos_statustype { }; +#define WLAN_MAX_DSCP 0x3f + /* * Enumeration of the various User priority (UP) types * From 802.1D/802.11e/WMM specifications (all refer to same table) diff --git a/drivers/staging/qcacld-3.0/core/sme/src/common/sme_api.c b/drivers/staging/qcacld-3.0/core/sme/src/common/sme_api.c index 8183b441f48b..87db2389b215 100644 --- a/drivers/staging/qcacld-3.0/core/sme/src/common/sme_api.c +++ b/drivers/staging/qcacld-3.0/core/sme/src/common/sme_api.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -63,7 +63,8 @@ static tSelfRecoveryStats g_self_recovery_stats; static QDF_STATUS init_sme_cmd_list(tpAniSirGlobal pMac); -static void sme_disconnect_connected_sessions(tpAniSirGlobal pMac); +static void sme_disconnect_connected_sessions(tpAniSirGlobal pMac, + enum eSirMacReasonCodes reason); static QDF_STATUS sme_handle_generic_change_country_code(tpAniSirGlobal pMac, void *pMsgBuf); @@ -91,6 +92,11 @@ QDF_STATUS sme_acquire_global_lock(tSmeStruct *psSme) return status; } +uint32_t sme_get_vht_ch_width(void) +{ + return wma_get_vht_ch_width(); +} + void sme_store_nss_chains_cfg_in_vdev(struct wlan_objmgr_vdev *vdev, struct mlme_nss_chains *vdev_ini_cfg) @@ -619,14 +625,11 @@ QDF_STATUS sme_ser_cmd_callback(struct wlan_serialization_command *cmd, switch (reason) { case WLAN_SER_CB_ACTIVATE_CMD: - sme_debug("WLAN_SER_CB_ACTIVATE_CMD callback"); status = sme_ser_handle_active_cmd(cmd); break; case WLAN_SER_CB_CANCEL_CMD: - sme_debug("WLAN_SER_CB_CANCEL_CMD callback"); break; case WLAN_SER_CB_RELEASE_MEM_CMD: - sme_debug("WLAN_SER_CB_RELEASE_MEM_CMD callback"); if (cmd->vdev) wlan_objmgr_vdev_release_ref(cmd->vdev, WLAN_LEGACY_SME_ID); @@ -634,7 +637,6 @@ QDF_STATUS sme_ser_cmd_callback(struct wlan_serialization_command *cmd, csr_release_command_buffer(mac_ctx, sme_cmd); break; case WLAN_SER_CB_ACTIVE_CMD_TIMEOUT: - sme_debug("WLAN_SER_CB_ACTIVE_CMD_TIMEOUT callback"); break; default: sme_debug("STOP: unknown reason code"); @@ -1224,6 +1226,9 @@ QDF_STATUS sme_hdd_ready_ind(tHalHandle hHal) msg->csr_roam_synch_cb = csr_roam_synch_callback; msg->sme_msg_cb = sme_process_msg_callback; msg->stop_roaming_cb = sme_stop_roaming; + msg->csr_roam_auth_event_handle_cb = + csr_roam_auth_offload_callback; + msg->csr_roam_pmkid_req_cb = csr_roam_pmkid_req_callback; status = u_mac_post_ctrl_msg(hHal, (tSirMbMsg *)msg); if (QDF_IS_STATUS_ERROR(status)) { @@ -1353,12 +1358,16 @@ static QDF_STATUS dfs_msg_processor(tpAniSirGlobal mac, struct scheduler_msg *msg) { QDF_STATUS status = QDF_STATUS_SUCCESS; - struct csr_roam_info roam_info = { 0 }; + struct csr_roam_info *roam_info; tSirSmeCSAIeTxCompleteRsp *csa_ie_tx_complete_rsp; uint32_t session_id = 0; eRoamCmdStatus roam_status; eCsrRoamResult roam_result; + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return QDF_STATUS_E_NOMEM; + switch (msg->type) { case eWNI_SME_DFS_RADAR_FOUND: { @@ -1375,14 +1384,12 @@ static QDF_STATUS dfs_msg_processor(tpAniSirGlobal mac, (tSirSmeCSAIeTxCompleteRsp *) msg->bodyptr; if (!csa_ie_tx_complete_rsp) { sme_err("eWNI_SME_DFS_CSAIE_TX_COMPLETE_IND null msg"); + qdf_mem_free(roam_info); return QDF_STATUS_E_FAILURE; } session_id = csa_ie_tx_complete_rsp->sessionId; roam_status = eCSR_ROAM_DFS_CHAN_SW_NOTIFY; roam_result = eCSR_ROAM_RESULT_DFS_CHANSW_UPDATE_SUCCESS; - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - "eWNI_SME_DFS_CSAIE_TX_COMPLETE_IND session=%d", - session_id); break; } case eWNI_SME_DFS_CAC_COMPLETE: @@ -1398,14 +1405,16 @@ static QDF_STATUS dfs_msg_processor(tpAniSirGlobal mac, default: { sme_err("Invalid DFS message: 0x%x", msg->type); + qdf_mem_free(roam_info); status = QDF_STATUS_E_FAILURE; return status; } } /* Indicate Radar Event to SAP */ - csr_roam_call_callback(mac, session_id, &roam_info, 0, + csr_roam_call_callback(mac, session_id, roam_info, 0, roam_status, roam_result); + qdf_mem_free(roam_info); return status; } @@ -1420,17 +1429,23 @@ sme_unprotected_mgmt_frm_ind(tpAniSirGlobal mac, tpSirSmeUnprotMgmtFrameInd pSmeMgmtFrm) { QDF_STATUS status = QDF_STATUS_SUCCESS; - struct csr_roam_info roam_info = { 0 }; + struct csr_roam_info *roam_info; uint32_t SessionId = pSmeMgmtFrm->sessionId; - roam_info.nFrameLength = pSmeMgmtFrm->frameLen; - roam_info.pbFrames = pSmeMgmtFrm->frameBuf; - roam_info.frameType = pSmeMgmtFrm->frameType; + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return QDF_STATUS_E_NOMEM; + + roam_info->nFrameLength = pSmeMgmtFrm->frameLen; + roam_info->pbFrames = pSmeMgmtFrm->frameBuf; + roam_info->frameType = pSmeMgmtFrm->frameType; /* forward the mgmt frame to HDD */ - csr_roam_call_callback(mac, SessionId, &roam_info, 0, + csr_roam_call_callback(mac, SessionId, roam_info, 0, eCSR_ROAM_UNPROT_MGMT_FRAME_IND, 0); + qdf_mem_free(roam_info); + return status; } #endif @@ -1481,7 +1496,7 @@ static QDF_STATUS sme_extended_change_channel_ind(tpAniSirGlobal mac_ctx, struct sir_sme_ext_cng_chan_ind *ext_chan_ind; QDF_STATUS status = QDF_STATUS_SUCCESS; uint32_t session_id = 0; - struct csr_roam_info roamInfo = {0}; + struct csr_roam_info *roam_info; eRoamCmdStatus roam_status; eCsrRoamResult roam_result; @@ -1490,16 +1505,20 @@ static QDF_STATUS sme_extended_change_channel_ind(tpAniSirGlobal mac_ctx, sme_err("ext_chan_ind is NULL"); return QDF_STATUS_E_FAILURE; } + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return QDF_STATUS_E_NOMEM; session_id = ext_chan_ind->session_id; - roamInfo.target_channel = ext_chan_ind->new_channel; + roam_info->target_channel = ext_chan_ind->new_channel; roam_status = eCSR_ROAM_EXT_CHG_CHNL_IND; roam_result = eCSR_ROAM_EXT_CHG_CHNL_UPDATE_IND; sme_debug("sapdfs: Received eWNI_SME_EXT_CHANGE_CHANNEL_IND for session id [%d]", session_id); /* Indicate Ext Channel Change event to SAP */ - csr_roam_call_callback(mac_ctx, session_id, &roamInfo, 0, - roam_status, roam_result); + csr_roam_call_callback(mac_ctx, session_id, roam_info, 0, + roam_status, roam_result); + qdf_mem_free(roam_info); return status; } @@ -1665,15 +1684,20 @@ static QDF_STATUS sme_tsm_ie_ind(tpAniSirGlobal mac, tSirSmeTsmIEInd *pSmeTsmIeInd) { QDF_STATUS status = QDF_STATUS_SUCCESS; - struct csr_roam_info roam_info = { 0 }; + struct csr_roam_info *roam_info; uint32_t SessionId = pSmeTsmIeInd->sessionId; - roam_info.tsmIe.tsid = pSmeTsmIeInd->tsmIe.tsid; - roam_info.tsmIe.state = pSmeTsmIeInd->tsmIe.state; - roam_info.tsmIe.msmt_interval = pSmeTsmIeInd->tsmIe.msmt_interval; + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return QDF_STATUS_E_NOMEM; + + roam_info->tsmIe.tsid = pSmeTsmIeInd->tsmIe.tsid; + roam_info->tsmIe.state = pSmeTsmIeInd->tsmIe.state; + roam_info->tsmIe.msmt_interval = pSmeTsmIeInd->tsmIe.msmt_interval; /* forward the tsm ie information to HDD */ - csr_roam_call_callback(mac, SessionId, &roam_info, 0, + csr_roam_call_callback(mac, SessionId, roam_info, 0, eCSR_ROAM_TSM_IE_IND, 0); + qdf_mem_free(roam_info); return status; } @@ -2028,6 +2052,113 @@ static QDF_STATUS sme_process_antenna_mode_resp(tpAniSirGlobal mac, return QDF_STATUS_SUCCESS; } +#ifdef WLAN_FEATURE_ROAM_OFFLOAD +QDF_STATUS sme_set_roam_scan_ch_event_cb(mac_handle_t mac_handle, + sme_get_raom_scan_ch_Callback cb) +{ + QDF_STATUS qdf_status; + tpAniSirGlobal mac = PMAC_STRUCT(mac_handle); + + qdf_status = sme_acquire_global_lock(&mac->sme); + if (QDF_IS_STATUS_ERROR(qdf_status)) + return qdf_status; + + mac->sme.roam_scan_ch_callback = cb; + sme_release_global_lock(&mac->sme); + + return qdf_status; +} + +static void +sme_process_roam_scan_ch_list_resp(tpAniSirGlobal mac, + struct roam_scan_ch_resp *roam_ch) +{ + sme_get_raom_scan_ch_Callback callback = + mac->sme.roam_scan_ch_callback; + + if (!roam_ch) + return; + + if (callback) + callback(mac->hdd_handle, roam_ch, + mac->sme.roam_scan_ch_get_context); +} + +/* + * sme_update_roam_offload_enabled() - enable/disable roam offload feaure + * It is used at in the REG_DYNAMIC_VARIABLE macro definition of + * + * hHal - The handle returned by mac_open. + * nRoamOffloadEnabled - The bool to update with + * Return QDF_STATUS_SUCCESS - SME update config successfully. + * Other status means SME is failed to update. + */ + +QDF_STATUS sme_update_roam_offload_enabled(tHalHandle hHal, + bool nRoamOffloadEnabled) +{ + tpAniSirGlobal pMac = PMAC_STRUCT(hHal); + QDF_STATUS status = QDF_STATUS_SUCCESS; + + status = sme_acquire_global_lock(&pMac->sme); + if (QDF_IS_STATUS_SUCCESS(status)) { + QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, + "%s: LFR3:gRoamOffloadEnabled is changed from %d to %d", + __func__, pMac->roam.configParam.isRoamOffloadEnabled, + nRoamOffloadEnabled); + pMac->roam.configParam.isRoamOffloadEnabled = + nRoamOffloadEnabled; + sme_release_global_lock(&pMac->sme); + } + + return status; +} + +/** + * sme_update_roam_key_mgmt_offload_enabled() - enable/disable key mgmt offload + * This is a synchronous call + * @hal_ctx: The handle returned by mac_open. + * @session_id: Session Identifier + * @key_mgmt_offload_enabled: key mgmt enable/disable flag + * @pmkid_modes: PMKID modes of PMKSA caching and OKC + * Return: QDF_STATUS_SUCCESS - SME updated config successfully. + * Other status means SME is failed to update. + */ + +QDF_STATUS +sme_update_roam_key_mgmt_offload_enabled(tHalHandle hal_ctx, + uint8_t session_id, + bool key_mgmt_offload_enabled, + struct pmkid_mode_bits *pmkid_modes) +{ + tpAniSirGlobal mac_ctx = PMAC_STRUCT(hal_ctx); + QDF_STATUS status = QDF_STATUS_SUCCESS; + + status = sme_acquire_global_lock(&mac_ctx->sme); + if (QDF_IS_STATUS_SUCCESS(status)) { + if (CSR_IS_SESSION_VALID(mac_ctx, session_id)) { + QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, + "%s: LFR3: key_mgmt_offload_enabled changed to %d", + __func__, key_mgmt_offload_enabled); + status = csr_roam_set_key_mgmt_offload(mac_ctx, + session_id, + key_mgmt_offload_enabled, + pmkid_modes); + } else + status = QDF_STATUS_E_INVAL; + sme_release_global_lock(&mac_ctx->sme); + } + + return status; +} +#else +static inline void +sme_process_roam_scan_ch_list_resp(tpAniSirGlobal mac, + void *roam_ch) +{ +} +#endif + QDF_STATUS sme_process_msg(tpAniSirGlobal pMac, struct scheduler_msg *pMsg) { QDF_STATUS status = QDF_STATUS_E_FAILURE; @@ -2402,6 +2533,10 @@ QDF_STATUS sme_process_msg(tpAniSirGlobal pMac, struct scheduler_msg *pMsg) sme_err("Empty message for: %d", pMsg->type); } break; + case eWNI_SME_GET_ROAM_SCAN_CH_LIST_EVENT: + sme_process_roam_scan_ch_list_resp(pMac, pMsg->bodyptr); + qdf_mem_free(pMsg->bodyptr); + break; default: if ((pMsg->type >= eWNI_SME_MSG_TYPES_BEGIN) @@ -3270,7 +3405,8 @@ QDF_STATUS sme_roam_connect_to_last_profile(tHalHandle hHal, uint8_t sessionId) } QDF_STATUS sme_roam_disconnect(tHalHandle hal, uint8_t session_id, - eCsrRoamDisconnectReason reason) + eCsrRoamDisconnectReason reason, + tSirMacReasonCodes mac_reason) { QDF_STATUS status = QDF_STATUS_E_FAILURE; tpAniSirGlobal mac_ctx = PMAC_STRUCT(hal); @@ -3282,7 +3418,8 @@ QDF_STATUS sme_roam_disconnect(tHalHandle hal, uint8_t session_id, if (QDF_IS_STATUS_SUCCESS(status)) { if (CSR_IS_SESSION_VALID(mac_ctx, session_id)) status = csr_roam_disconnect(mac_ctx, session_id, - reason); + reason, + mac_reason); else status = QDF_STATUS_E_INVAL; sme_release_global_lock(&mac_ctx->sme); @@ -3623,6 +3760,36 @@ void sme_get_pmk_info(tHalHandle hal, uint8_t session_id, #endif #ifdef WLAN_FEATURE_ROAM_OFFLOAD +QDF_STATUS sme_get_roam_scan_ch(tHalHandle hal, uint8_t vdev_id, + void *pcontext) +{ + struct scheduler_msg msg = {0}; + QDF_STATUS status = QDF_STATUS_E_FAILURE; + tpAniSirGlobal mac = PMAC_STRUCT(hal); + + status = sme_acquire_global_lock(&mac->sme); + if (QDF_IS_STATUS_ERROR(status)) + return QDF_STATUS_E_FAILURE; + + msg.type = WMA_ROAM_SCAN_CH_REQ; + msg.bodyval = vdev_id; + mac->sme.roam_scan_ch_get_context = pcontext; + + if (scheduler_post_message(QDF_MODULE_ID_SME, + QDF_MODULE_ID_WMA, + QDF_MODULE_ID_WMA, + &msg)) { + sme_err("Posting message %d failed", + WMA_ROAM_SCAN_CH_REQ); + mac->sme.roam_scan_ch_get_context = NULL; + sme_release_global_lock(&mac->sme); + return QDF_STATUS_E_FAILURE; + } + + sme_release_global_lock(&mac->sme); + return QDF_STATUS_SUCCESS; +} + /* * \fn sme_roam_set_psk_pmk * \brief a wrapper function to request CSR to save PSK/PMK @@ -4754,14 +4921,8 @@ QDF_STATUS sme_get_wcnss_hardware_version(tHalHandle hHal, } #ifdef FEATURE_OEM_DATA_SUPPORT -/** - * sme_oem_data_req() - send oem data request to WMA - * @hal: HAL handle - * @hdd_oem_req: OEM data request from HDD - * - * Return: QDF_STATUS - */ -QDF_STATUS sme_oem_data_req(tHalHandle hal, struct oem_data_req *hdd_oem_req) +QDF_STATUS sme_oem_req_cmd(mac_handle_t mac_handle, + struct oem_data_req *oem_req) { QDF_STATUS status = QDF_STATUS_SUCCESS; struct oem_data_req *oem_data_req; @@ -4780,7 +4941,7 @@ QDF_STATUS sme_oem_data_req(tHalHandle hal, struct oem_data_req *hdd_oem_req) return QDF_STATUS_E_NOMEM; } - oem_data_req->data_len = hdd_oem_req->data_len; + oem_data_req->data_len = oem_req->data_len; oem_data_req->data = qdf_mem_malloc(oem_data_req->data_len); if (!oem_data_req->data) { sme_err("mem alloc failed"); @@ -4788,10 +4949,10 @@ QDF_STATUS sme_oem_data_req(tHalHandle hal, struct oem_data_req *hdd_oem_req) return QDF_STATUS_E_NOMEM; } - qdf_mem_copy(oem_data_req->data, hdd_oem_req->data, + qdf_mem_copy(oem_data_req->data, oem_req->data, oem_data_req->data_len); - status = wma_start_oem_data_req(wma_handle, oem_data_req); + status = wma_start_oem_req_cmd(wma_handle, oem_data_req); if (!QDF_IS_STATUS_SUCCESS(status)) sme_err("Post oem data request msg fail"); @@ -4808,6 +4969,29 @@ QDF_STATUS sme_oem_data_req(tHalHandle hal, struct oem_data_req *hdd_oem_req) } #endif /*FEATURE_OEM_DATA_SUPPORT */ +#ifdef FEATURE_OEM_DATA +QDF_STATUS sme_oem_data_cmd(mac_handle_t mac_handle, + struct oem_data *oem_data) +{ + QDF_STATUS status; + void *wma_handle; + + SME_ENTER(); + wma_handle = cds_get_context(QDF_MODULE_ID_WMA); + if (!wma_handle) { + sme_err("wma_handle is NULL"); + return QDF_STATUS_E_FAILURE; + } + + status = wma_start_oem_data_cmd(wma_handle, oem_data); + if (!QDF_IS_STATUS_SUCCESS(status)) + sme_err("fail to call wma_start_oem_data_cmd."); + + SME_EXIT(); + return status; +} +#endif + QDF_STATUS sme_open_session(tHalHandle hal, struct sme_session_params *params) { QDF_STATUS status = QDF_STATUS_E_INVAL; @@ -5089,6 +5273,18 @@ sme_nss_chains_update(mac_handle_t mac_handle, return status; } +void sme_cleanup_session(mac_handle_t mac_handle, uint8_t vdev_id) +{ + QDF_STATUS status; + struct sAniSirGlobal *mac = MAC_CONTEXT(mac_handle); + + status = sme_acquire_global_lock(&mac->sme); + if (QDF_IS_STATUS_ERROR(status)) + return; + csr_cleanup_session(mac, vdev_id); + sme_release_global_lock(&mac->sme); +} + /* * sme_change_mcc_beacon_interval() - * To update P2P-GO beaconInterval. This function should be called after @@ -5913,7 +6109,8 @@ sme_handle_generic_change_country_code(tpAniSirGlobal mac_ctx, mac_ctx->reg_hint_src = SOURCE_UNKNOWN; - sme_disconnect_connected_sessions(mac_ctx); + sme_disconnect_connected_sessions(mac_ctx, + eSIR_MAC_UNSPEC_FAILURE_REASON); return QDF_STATUS_SUCCESS; } @@ -5935,7 +6132,8 @@ QDF_STATUS sme_update_channel_list(tHalHandle hal) csr_apply_channel_power_info_wrapper(mac_ctx); csr_scan_filter_results(mac_ctx); - sme_disconnect_connected_sessions(mac_ctx); + sme_disconnect_connected_sessions(mac_ctx, + eSIR_MAC_OPER_CHANNEL_USER_DISABLED); sme_release_global_lock(&mac_ctx->sme); } @@ -5956,17 +6154,20 @@ sme_search_in_base_ch_lst(tpAniSirGlobal mac_ctx, uint8_t curr_ch) return false; } + /** * sme_disconnect_connected_sessions() - Disconnect STA and P2P client session * if channel is not supported - * @mac_ctx: mac global context + * @mac_ctx: mac global context + * @reason: Mac Disconnect reason code as per @enum eSirMacReasonCodes * * If new country code does not support the channel on which STA/P2P client * is connetced, it sends the disconnect to the AP/P2P GO * * Return: void */ -static void sme_disconnect_connected_sessions(tpAniSirGlobal mac_ctx) +static void sme_disconnect_connected_sessions(tpAniSirGlobal mac_ctx, + enum eSirMacReasonCodes reason) { uint8_t session_id, found = false; uint8_t curr_ch; @@ -5984,7 +6185,8 @@ static void sme_disconnect_connected_sessions(tpAniSirGlobal mac_ctx) if (!found) { sme_debug("Disconnect Session: %d", session_id); csr_roam_disconnect(mac_ctx, session_id, - eCSR_DISCONNECT_REASON_UNSPECIFIED); + eCSR_DISCONNECT_REASON_UNSPECIFIED, + reason); } } } @@ -6117,15 +6319,9 @@ QDF_STATUS sme_set_freq_band(tHalHandle hHal, uint8_t sessionId, */ QDF_STATUS sme_get_freq_band(tHalHandle hHal, enum band_info *pBand) { - QDF_STATUS status = QDF_STATUS_E_FAILURE; tpAniSirGlobal pMac = PMAC_STRUCT(hHal); - status = sme_acquire_global_lock(&pMac->sme); - if (QDF_IS_STATUS_SUCCESS(status)) { - *pBand = csr_get_current_band(hHal); - sme_release_global_lock(&pMac->sme); - } - return status; + return ucfg_reg_get_band(pMac->pdev, pBand); } /* @@ -6761,17 +6957,47 @@ QDF_STATUS sme_update_roam_rssi_diff(mac_handle_t mac_handle, uint8_t vdev_id, return status; } -#ifdef WLAN_FEATURE_FILS_SK -QDF_STATUS sme_update_fils_config(tHalHandle hal, uint8_t session_id, - struct csr_roam_profile *src_profile) +void sme_update_session_assoc_ie(mac_handle_t hal, + uint8_t vdev_id, + struct csr_roam_profile *src_profile) +{ + tpAniSirGlobal mac = PMAC_STRUCT(hal); + struct csr_roam_session *session = CSR_GET_SESSION(mac, vdev_id); + + if (!session) { + sme_err("Session: %d not found", vdev_id); + return; + } + + qdf_mem_free(session->pAddIEAssoc); + session->pAddIEAssoc = NULL; + session->nAddIEAssocLength = 0; + + if (!src_profile->nAddIEAssocLength) { + sme_debug("Assoc IE len 0"); + return; + } + + session->pAddIEAssoc = qdf_mem_malloc(src_profile->nAddIEAssocLength); + if (!session->pAddIEAssoc) + return; + + session->nAddIEAssocLength = src_profile->nAddIEAssocLength; + qdf_mem_copy(session->pAddIEAssoc, src_profile->pAddIEAssoc, + src_profile->nAddIEAssocLength); +} + +QDF_STATUS sme_send_rso_connect_params(mac_handle_t hal, + uint8_t vdev_id, + struct csr_roam_profile *src_profile) { tpAniSirGlobal mac = PMAC_STRUCT(hal); QDF_STATUS status = QDF_STATUS_SUCCESS; tpCsrNeighborRoamControlInfo neighbor_roam_info = - &mac->roam.neighborRoamInfo[session_id]; + &mac->roam.neighborRoamInfo[vdev_id]; - if (session_id >= CSR_ROAM_SESSION_MAX) { - sme_err("Invalid sme session id: %d", session_id); + if (vdev_id >= CSR_ROAM_SESSION_MAX) { + sme_err("Invalid sme vdev_id: %d", vdev_id); return QDF_STATUS_E_INVAL; } @@ -6784,16 +7010,15 @@ QDF_STATUS sme_update_fils_config(tHalHandle hal, uint8_t session_id, (neighbor_roam_info->neighborRoamState != eCSR_NEIGHBOR_ROAM_STATE_CONNECTED)) { sme_info("Fast roam is disabled or not connected(%d)", - neighbor_roam_info->neighborRoamState); + neighbor_roam_info->neighborRoamState); return QDF_STATUS_E_PERM; } - csr_update_fils_config(mac, session_id, src_profile); if (csr_roamIsRoamOffloadEnabled(mac)) { status = sme_acquire_global_lock(&mac->sme); if (QDF_IS_STATUS_SUCCESS(status)) { sme_debug("Updating fils config to fw"); - csr_roam_offload_scan(mac, session_id, + csr_roam_offload_scan(mac, vdev_id, ROAM_SCAN_OFFLOAD_UPDATE_CFG, REASON_FILS_PARAMS_CHANGED); sme_release_global_lock(&mac->sme); @@ -6808,7 +7033,19 @@ QDF_STATUS sme_update_fils_config(tHalHandle hal, uint8_t session_id, return status; } -void sme_send_hlp_ie_info(tHalHandle hal, uint8_t session_id, +#ifdef WLAN_FEATURE_FILS_SK +QDF_STATUS sme_update_fils_config(mac_handle_t mac_handle, uint8_t vdev_id, + struct csr_roam_profile *src_profile) +{ + QDF_STATUS status = QDF_STATUS_SUCCESS; + tpAniSirGlobal mac = MAC_CONTEXT(mac_handle); + + csr_update_fils_config(mac, vdev_id, src_profile); + + return status; +} + +void sme_send_hlp_ie_info(tHalHandle hal, uint8_t vdev_id, struct csr_roam_profile *profile, uint32_t if_addr) { int i; @@ -6816,9 +7053,9 @@ void sme_send_hlp_ie_info(tHalHandle hal, uint8_t session_id, QDF_STATUS status; struct hlp_params *params; tpAniSirGlobal mac = PMAC_STRUCT(hal); - struct csr_roam_session *session = CSR_GET_SESSION(mac, session_id); + struct csr_roam_session *session = CSR_GET_SESSION(mac, vdev_id); tpCsrNeighborRoamControlInfo neighbor_roam_info = - &mac->roam.neighborRoamInfo[session_id]; + &mac->roam.neighborRoamInfo[vdev_id]; if (!session) { sme_err("session NULL"); @@ -6846,7 +7083,7 @@ void sme_send_hlp_ie_info(tHalHandle hal, uint8_t session_id, return; } - params->vdev_id = session_id; + params->vdev_id = vdev_id; params->hlp_ie_len = profile->hlp_ie_len + SIR_IPV4_ADDR_LEN; for (i = 0; i < SIR_IPV4_ADDR_LEN; i++) @@ -6882,16 +7119,12 @@ void sme_free_join_rsp_fils_params(struct csr_roam_info *roam_info) { struct fils_join_rsp_params *roam_fils_params; - if (!roam_info) { - sme_err("FILS Roam Info NULL"); + if (!roam_info) return; - } roam_fils_params = roam_info->fils_join_rsp; - if (!roam_fils_params) { - sme_err("FILS Roam Param NULL"); + if (!roam_fils_params) return; - } if (roam_fils_params->fils_pmk) qdf_mem_free(roam_fils_params->fils_pmk); @@ -6902,7 +7135,7 @@ void sme_free_join_rsp_fils_params(struct csr_roam_info *roam_info) } #else -inline void sme_send_hlp_ie_info(tHalHandle hal, uint8_t session_id, +inline void sme_send_hlp_ie_info(tHalHandle hal, uint8_t vdev_id, struct csr_roam_profile *profile, uint32_t if_addr) {} #endif @@ -7032,10 +7265,15 @@ QDF_STATUS sme_set_roam_scan_control(tHalHandle hHal, uint8_t sessionId, specific_channel_info = &neighbor_roam_info->cfgParams.specific_chan_info; csr_flush_cfg_bg_scan_roam_channel_list(specific_channel_info); - if (pMac->roam.configParam.isRoamOffloadScanEnabled) + if (pMac->roam.configParam.isRoamOffloadScanEnabled) { csr_roam_offload_scan(pMac, sessionId, ROAM_SCAN_OFFLOAD_UPDATE_CFG, REASON_FLUSH_CHANNEL_LIST); + + csr_roam_offload_scan(pMac, sessionId, + ROAM_SCAN_OFFLOAD_UPDATE_CFG, + REASON_CHANNEL_LIST_CHANGED); + } } pMac->roam.configParam.nRoamScanControl = roamScanControl; sme_release_global_lock(&pMac->sme); @@ -7177,21 +7415,20 @@ QDF_STATUS sme_update_is_mawc_ini_feature_enabled(tHalHandle hHal, * Return QDF_STATUS_SUCCESS on success * Other status on failure */ -QDF_STATUS sme_stop_roaming(tHalHandle hal, uint8_t session_id, uint8_t reason) +QDF_STATUS sme_stop_roaming(tHalHandle hal, uint8_t vdev_id, uint8_t reason) { - struct scheduler_msg wma_msg = {0}; QDF_STATUS status; tSirRoamOffloadScanReq *req; tpAniSirGlobal mac_ctx = PMAC_STRUCT(hal); tpCsrNeighborRoamControlInfo roam_info; struct csr_roam_session *session; - if (!CSR_IS_SESSION_VALID(mac_ctx, session_id)) { + if (!CSR_IS_SESSION_VALID(mac_ctx, vdev_id)) { sme_err("incorrect session/vdev ID"); return QDF_STATUS_E_INVAL; } - session = CSR_GET_SESSION(mac_ctx, session_id); + session = CSR_GET_SESSION(mac_ctx, vdev_id); /* * set the driver_disabled_roaming flag to true even if roaming @@ -7202,12 +7439,12 @@ QDF_STATUS sme_stop_roaming(tHalHandle hal, uint8_t session_id, uint8_t reason) session->pCurRoamProfile->csrPersona == QDF_STA_MODE) { session->pCurRoamProfile->driver_disabled_roaming = true; sme_debug("driver_disabled_roaming set for session %d", - session_id); + vdev_id); } - roam_info = &mac_ctx->roam.neighborRoamInfo[session_id]; + roam_info = &mac_ctx->roam.neighborRoamInfo[vdev_id]; if (!roam_info->b_roam_scan_offload_started) { - sme_debug("Roaming already disabled for session %d", session_id); + sme_debug("Roaming already disabled for session %d", vdev_id); return QDF_STATUS_SUCCESS; } req = qdf_mem_malloc(sizeof(*req)); @@ -7221,8 +7458,8 @@ QDF_STATUS sme_stop_roaming(tHalHandle hal, uint8_t session_id, uint8_t reason) req->reason = REASON_ROAM_STOP_ALL; else req->reason = REASON_SME_ISSUED; - req->sessionId = session_id; - if (csr_neighbor_middle_of_roaming(mac_ctx, session_id)) + req->sessionId = vdev_id; + if (csr_neighbor_middle_of_roaming(mac_ctx, vdev_id)) req->middle_of_roaming = 1; else csr_roam_reset_roam_params(mac_ctx); @@ -7230,15 +7467,12 @@ QDF_STATUS sme_stop_roaming(tHalHandle hal, uint8_t session_id, uint8_t reason) /* Disable offload_11k_params and btm_offload_config for current vdev */ req->offload_11k_params.offload_11k_bitmask = 0; req->btm_offload_config = 0; - req->offload_11k_params.vdev_id = session_id; + req->offload_11k_params.vdev_id = vdev_id; - wma_msg.type = WMA_ROAM_SCAN_OFFLOAD_REQ; - wma_msg.bodyptr = req; - - status = wma_post_ctrl_msg(mac_ctx, &wma_msg); - if (QDF_STATUS_SUCCESS != status) { - sme_err("WMA_ROAM_SCAN_OFFLOAD_REQ failed, session_id: %d", - session_id); + status = csr_roam_send_rso_cmd(mac_ctx, vdev_id, req); + if (QDF_IS_STATUS_ERROR(status)) { + sme_err("WMA_ROAM_SCAN_OFFLOAD_REQ failed, vdev_id: %d", + vdev_id); qdf_mem_zero(req, sizeof(*req)); qdf_mem_free(req); return QDF_STATUS_E_FAULT; @@ -7870,7 +8104,7 @@ sme_modify_roam_cand_sel_criteria(mac_handle_t mac_handle, if (QDF_IS_STATUS_ERROR(status)) return status; - if (csr_roamIsRoamOffloadEnabled(mac)) { + if (!csr_roamIsRoamOffloadEnabled(mac)) { status = QDF_STATUS_E_INVAL; goto out; } @@ -7887,39 +8121,137 @@ sme_modify_roam_cand_sel_criteria(mac_handle_t mac_handle, return status; } -/* - * sme_set_neighbor_scan_min_chan_time() - - * Update nNeighborScanMinChanTime - * This function is called through dynamic setConfig callback function - * to configure gNeighborScanChannelMinTime - * Usage: adb shell iwpriv wlan0 setConfig - * gNeighborScanChannelMinTime=[0 .. 60] +/** + * sme_restore_default_roaming_params() - Restore neighbor roam config + * @mac: mac context + * @roam_info: Neighbor roam info pointer to be populated * - * hHal - HAL handle for device - * nNeighborScanMinChanTime - Channel minimum dwell time - * sessionId - Session Identifier - * Return Success or failure + * Restore neighbor roam info request params with lfr config params + * + * Return: None */ -QDF_STATUS sme_set_neighbor_scan_min_chan_time(tHalHandle hHal, - const uint16_t - nNeighborScanMinChanTime, - uint8_t sessionId) +static void +sme_restore_default_roaming_params(tpAniSirGlobal mac, + tCsrNeighborRoamControlInfo *roam_info) +{ + struct csr_config *roam_config = &mac->roam.configParam; + + roam_info->cfgParams.enable_scoring_for_roam = + roam_config->bss_score_params.enable_scoring_for_roam; + roam_info->cfgParams.emptyScanRefreshPeriod = + roam_config->neighborRoamConfig.nEmptyScanRefreshPeriod; + roam_info->cfgParams.full_roam_scan_period = + roam_config->neighborRoamConfig.full_roam_scan_period; + roam_info->cfgParams.maxChannelScanTime = + roam_config->neighborRoamConfig.nNeighborScanMaxChanTime; + roam_info->cfgParams.neighborScanPeriod = + roam_config->neighborRoamConfig.nNeighborScanTimerPeriod; + roam_info->cfgParams.neighborLookupThreshold = + roam_config->neighborRoamConfig.nNeighborLookupRssiThreshold; + roam_info->cfgParams.roam_rssi_diff = roam_config->RoamRssiDiff; + roam_info->cfgParams.roam_scan_home_away_time = + roam_config->nRoamScanHomeAwayTime; + roam_info->cfgParams.roam_scan_n_probes = + roam_config->nProbes; + roam_info->cfgParams.roam_scan_inactivity_time = + roam_config->roam_scan_inactivity_time; + roam_info->cfgParams.roam_inactive_data_packet_count = + roam_config->roam_inactive_data_packet_count; + roam_info->cfgParams.roam_scan_period_after_inactivity = + roam_config->roam_scan_period_after_inactivity; +} + +void sme_roam_reset_configs(mac_handle_t mac_handle, uint8_t vdev_id) { - tpAniSirGlobal pMac = PMAC_STRUCT(hHal); - QDF_STATUS status = QDF_STATUS_SUCCESS; + tpAniSirGlobal mac = PMAC_STRUCT(mac_handle); + tCsrNeighborRoamControlInfo *neighbor_roam_info; - if (sessionId >= CSR_ROAM_SESSION_MAX) { - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_ERROR, - FL("Invalid sme session id: %d"), sessionId); + neighbor_roam_info = &mac->roam.neighborRoamInfo[vdev_id]; + sme_restore_default_roaming_params(mac, neighbor_roam_info); +} + +QDF_STATUS sme_roam_control_restore_default_config(mac_handle_t mac_handle, + uint8_t vdev_id) +{ + tpAniSirGlobal mac = PMAC_STRUCT(mac_handle); + QDF_STATUS status; + tpCsrNeighborRoamControlInfo neighbor_roam_info; + tCsrChannelInfo *chan_info; + + if (!CSR_IS_SESSION_VALID(mac, vdev_id)) { + sme_err("Invalid vdev_id: %d", vdev_id); return QDF_STATUS_E_INVAL; } - status = sme_acquire_global_lock(&pMac->sme); - if (QDF_IS_STATUS_SUCCESS(status)) { - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - "LFR runtime successfully set channel min dwell time to %d - old value is %d - roam state is %s", - nNeighborScanMinChanTime, - pMac->roam.configParam.neighborRoamConfig. + status = sme_acquire_global_lock(&mac->sme); + if (QDF_IS_STATUS_ERROR(status)) + return status; + + if (!mac->roam.configParam.isRoamOffloadScanEnabled) { + sme_err("roam_scan_offload_enabled is not supported"); + status = QDF_STATUS_E_INVAL; + goto out; + } + + mac->roam.configParam.nRoamScanControl = false; + + neighbor_roam_info = &mac->roam.neighborRoamInfo[vdev_id]; + + chan_info = &neighbor_roam_info->cfgParams.pref_chan_info; + csr_flush_cfg_bg_scan_roam_channel_list(chan_info); + + chan_info = &neighbor_roam_info->cfgParams.specific_chan_info; + csr_flush_cfg_bg_scan_roam_channel_list(chan_info); + + sme_restore_default_roaming_params(mac, neighbor_roam_info); + + /* Flush static and dynamic channels in ROAM scan list in firmware */ + csr_roam_offload_scan(mac, vdev_id, + ROAM_SCAN_OFFLOAD_UPDATE_CFG, + REASON_FLUSH_CHANNEL_LIST); + csr_roam_offload_scan(mac, vdev_id, + ROAM_SCAN_OFFLOAD_UPDATE_CFG, + REASON_SCORING_CRITERIA_CHANGED); + +out: + sme_release_global_lock(&mac->sme); + + return status; +} + +/* + * sme_set_neighbor_scan_min_chan_time() - + * Update nNeighborScanMinChanTime + * This function is called through dynamic setConfig callback function + * to configure gNeighborScanChannelMinTime + * Usage: adb shell iwpriv wlan0 setConfig + * gNeighborScanChannelMinTime=[0 .. 60] + * + * hHal - HAL handle for device + * nNeighborScanMinChanTime - Channel minimum dwell time + * sessionId - Session Identifier + * Return Success or failure + */ +QDF_STATUS sme_set_neighbor_scan_min_chan_time(tHalHandle hHal, + const uint16_t + nNeighborScanMinChanTime, + uint8_t sessionId) +{ + tpAniSirGlobal pMac = PMAC_STRUCT(hHal); + QDF_STATUS status = QDF_STATUS_SUCCESS; + + if (sessionId >= CSR_ROAM_SESSION_MAX) { + QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_ERROR, + FL("Invalid sme session id: %d"), sessionId); + return QDF_STATUS_E_INVAL; + } + + status = sme_acquire_global_lock(&pMac->sme); + if (QDF_IS_STATUS_SUCCESS(status)) { + QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, + "LFR runtime successfully set channel min dwell time to %d - old value is %d - roam state is %s", + nNeighborScanMinChanTime, + pMac->roam.configParam.neighborRoamConfig. nNeighborScanMinChanTime, mac_trace_get_neighbour_roam_state(pMac->roam. neighborRoamInfo @@ -8330,10 +8662,30 @@ void sme_dump_chan_list(tCsrChannelInfo *chan_info) } } - sme_debug("No.of frequencies: %u, frequency list: %s", i, channel_list); + sme_debug("frequency list [%u]: %s", i, channel_list); qdf_mem_free(channel_list); } +static uint8_t +csr_append_pref_chan_list(tCsrChannelInfo *chan_info, uint8_t *channel_list, + uint8_t num_chan) +{ + uint8_t i = 0; + + for (i = 0; i < chan_info->numOfChannels; i++) { + if (csr_is_channel_present_in_list( + channel_list, num_chan, chan_info->ChannelList[i])) + continue; + + if (num_chan >= SIR_ROAM_MAX_CHANNELS) + break; + + channel_list[num_chan++] = chan_info->ChannelList[i]; + } + + return num_chan; +} + /** * sme_update_roam_scan_channel_list() - to update scan channel list * @mac_handle: Opaque handle to the global MAC context @@ -8354,7 +8706,7 @@ sme_update_roam_scan_channel_list(mac_handle_t mac_handle, uint8_t vdev_id, { QDF_STATUS status = QDF_STATUS_SUCCESS; tpAniSirGlobal mac = PMAC_STRUCT(mac_handle); - uint8_t *channel_list; + uint8_t *channel_list, pref_chan_cnt = 0; channel_list = qdf_mem_malloc(SIR_MAX_SUPPORTED_CHANNEL_LIST); if (!channel_list) @@ -8371,9 +8723,15 @@ sme_update_roam_scan_channel_list(mac_handle_t mac_handle, uint8_t vdev_id, status = QDF_STATUS_E_INVAL; goto out; } + + pref_chan_cnt = csr_append_pref_chan_list(chan_info, channel_list, + num_chan); + num_chan = pref_chan_cnt; + csr_flush_cfg_bg_scan_roam_channel_list(chan_info); csr_create_bg_scan_roam_channel_list(mac, chan_info, channel_list, num_chan); + sme_debug("New channels:"); sme_dump_chan_list(chan_info); sme_debug("Updated roam scan channels - roam state is %d", @@ -8490,6 +8848,12 @@ sme_update_roam_scan_freq_list(mac_handle_t mac_handle, uint8_t vdev_id, } neighbor_roam_info = &mac->roam.neighborRoamInfo[vdev_id]; + if (neighbor_roam_info->cfgParams.specific_chan_info.numOfChannels) { + sme_err("Specific channel list is already configured"); + sme_release_global_lock(&mac->sme); + return QDF_STATUS_E_INVAL; + } + if (freq_list_type == QCA_PREFERRED_SCAN_FREQ_LIST) { sme_debug("Preferred frequency list: "); channel_info = &neighbor_roam_info->cfgParams.pref_chan_info; @@ -8521,12 +8885,14 @@ QDF_STATUS sme_get_roam_scan_channel_list(tHalHandle hHal, uint8_t *pChannelList, uint8_t *pNumChannels, uint8_t sessionId) { - int i = 0; + int i = 0, chan_cnt = 0; uint8_t *pOutPtr = pChannelList; tpAniSirGlobal pMac = PMAC_STRUCT(hHal); tpCsrNeighborRoamControlInfo pNeighborRoamInfo = NULL; + struct csr_channel *occupied_ch_lst = + &pMac->scan.occupiedChannels[sessionId]; QDF_STATUS status = QDF_STATUS_SUCCESS; - tCsrChannelInfo *specific_chan_info; + tCsrChannelInfo *chan_info; if (sessionId >= CSR_ROAM_SESSION_MAX) { QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_ERROR, @@ -8538,21 +8904,45 @@ QDF_STATUS sme_get_roam_scan_channel_list(tHalHandle hHal, status = sme_acquire_global_lock(&pMac->sme); if (!QDF_IS_STATUS_SUCCESS(status)) return status; - specific_chan_info = &pNeighborRoamInfo->cfgParams.specific_chan_info; - if (!specific_chan_info->ChannelList) { - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_WARN, - FL("Roam Scan channel list is NOT yet initialized")); - *pNumChannels = 0; - sme_release_global_lock(&pMac->sme); - return status; - } - *pNumChannels = specific_chan_info->numOfChannels; - for (i = 0; i < (*pNumChannels); i++) - pOutPtr[i] = - pNeighborRoamInfo->cfgParams.specific_chan_info.ChannelList[i]; + chan_info = &pNeighborRoamInfo->cfgParams.specific_chan_info; + if (chan_info->numOfChannels) { + *pNumChannels = chan_info->numOfChannels; + for (chan_cnt = 0; chan_cnt < (*pNumChannels) && + chan_cnt < WNI_CFG_VALID_CHANNEL_LIST_LEN; chan_cnt++) + pOutPtr[chan_cnt] = chan_info->ChannelList[chan_cnt]; + + *pNumChannels = chan_cnt; + } else { + chan_info = &pNeighborRoamInfo->cfgParams.pref_chan_info; + if (chan_info->numOfChannels) { + *pNumChannels = chan_info->numOfChannels; + for (chan_cnt = 0; chan_cnt < (*pNumChannels) && + chan_cnt < WNI_CFG_VALID_CHANNEL_LIST_LEN; + chan_cnt++) + pOutPtr[chan_cnt] = + chan_info->ChannelList[chan_cnt]; + } + + if (occupied_ch_lst->numChannels) { + for (i = 0; i < occupied_ch_lst->numChannels && + chan_cnt < WNI_CFG_VALID_CHANNEL_LIST_LEN; i++) { + if (csr_is_channel_present_in_list( + pOutPtr, chan_cnt, + occupied_ch_lst->channelList[i])) + continue; + pOutPtr[chan_cnt++] = + occupied_ch_lst->channelList[i]; + } + } + *pNumChannels = chan_cnt; + if (!(chan_info->numOfChannels || + occupied_ch_lst->numChannels)) { + sme_err("Roam Scan channel list is NOT yet initialized"); + status = QDF_STATUS_E_INVAL; + } + } - pOutPtr[i] = '\0'; sme_release_global_lock(&pMac->sme); return status; } @@ -8681,41 +9071,6 @@ QDF_STATUS sme_get_link_speed(tHalHandle hHal, tSirLinkSpeedInfo *lsReq, return status; } -QDF_STATUS sme_get_peer_stats(tpAniSirGlobal mac, - struct sir_peer_info_req req) -{ - QDF_STATUS qdf_status; - struct scheduler_msg message = {0}; - - qdf_status = sme_acquire_global_lock(&mac->sme); - if (!QDF_IS_STATUS_SUCCESS(qdf_status)) { - sme_debug("Failed to get Lock"); - return qdf_status; - } - /* serialize the req through MC thread */ - message.bodyptr = qdf_mem_malloc(sizeof(req)); - if (NULL == message.bodyptr) { - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_ERROR, - "%s: Memory allocation failed.", __func__); - sme_release_global_lock(&mac->sme); - return QDF_STATUS_E_NOMEM; - } - qdf_mem_copy(message.bodyptr, &req, sizeof(req)); - message.type = WMA_GET_PEER_INFO; - message.reserved = 0; - qdf_status = scheduler_post_message(QDF_MODULE_ID_SME, - QDF_MODULE_ID_WMA, - QDF_MODULE_ID_WMA, &message); - if (!QDF_IS_STATUS_SUCCESS(qdf_status)) { - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_ERROR, - "%s: Post get peer info msg fail", __func__); - qdf_mem_free(message.bodyptr); - qdf_status = QDF_STATUS_E_FAILURE; - } - sme_release_global_lock(&mac->sme); - return qdf_status; -} - QDF_STATUS sme_get_peer_info(tHalHandle hal, struct sir_peer_info_req req, void *context, void (*callbackfn)(struct sir_peer_info_resp *param, @@ -9230,6 +9585,25 @@ QDF_STATUS sme_send_cesium_enable_ind(tHalHandle hHal, uint32_t sessionId) return status; } +#ifdef WLAN_SEND_DSCP_UP_MAP_TO_FW +QDF_STATUS sme_send_dscp_up_map_to_fw(uint32_t *dscp_to_up_map) +{ + QDF_STATUS status; + void *wma = cds_get_context(QDF_MODULE_ID_WMA); + + if (!wma) { + sme_err("wma is NULL"); + return QDF_STATUS_E_FAILURE; + } + + status = wma_send_dscp_up_map_to_fw(wma, dscp_to_up_map); + if (!QDF_IS_STATUS_SUCCESS(status)) + sme_err("%s: failed to send dscp_up_map to FW", __func__); + + return status; +} +#endif + QDF_STATUS sme_set_wlm_latency_level(tHalHandle hal, uint16_t session_id, uint16_t latency_level) { @@ -10383,41 +10757,44 @@ static QDF_STATUS sme_process_channel_change_resp(tpAniSirGlobal pMac, uint16_t msg_type, void *pMsgBuf) { QDF_STATUS status = QDF_STATUS_SUCCESS; - struct csr_roam_info proam_info = { 0 }; + struct csr_roam_info *roam_info; eCsrRoamResult roamResult; tpSwitchChannelParams pChnlParams = (tpSwitchChannelParams) pMsgBuf; uint32_t SessionId = pChnlParams->peSessionId; - proam_info.channelChangeRespEvent = - (tSirChanChangeResponse *) + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return QDF_STATUS_E_NOMEM; + + roam_info->channelChangeRespEvent = qdf_mem_malloc(sizeof(tSirChanChangeResponse)); - if (NULL == proam_info.channelChangeRespEvent) { + if (!roam_info->channelChangeRespEvent) { status = QDF_STATUS_E_NOMEM; - sme_err("Channel Change Event Allocation Failed: %d\n", status); + qdf_mem_free(roam_info); return status; } if (msg_type == eWNI_SME_CHANNEL_CHANGE_RSP) { - proam_info.channelChangeRespEvent->sessionId = SessionId; - proam_info.channelChangeRespEvent->newChannelNumber = + roam_info->channelChangeRespEvent->sessionId = SessionId; + roam_info->channelChangeRespEvent->newChannelNumber = pChnlParams->channelNumber; if (pChnlParams->status == QDF_STATUS_SUCCESS) { QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, "sapdfs: Received success eWNI_SME_CHANNEL_CHANGE_RSP for sessionId[%d]", SessionId); - proam_info.channelChangeRespEvent->channelChangeStatus = + roam_info->channelChangeRespEvent->channelChangeStatus = 1; roamResult = eCSR_ROAM_RESULT_CHANNEL_CHANGE_SUCCESS; } else { QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, "sapdfs: Received failure eWNI_SME_CHANNEL_CHANGE_RSP for sessionId[%d]", SessionId); - proam_info.channelChangeRespEvent->channelChangeStatus = + roam_info->channelChangeRespEvent->channelChangeStatus = 0; roamResult = eCSR_ROAM_RESULT_CHANNEL_CHANGE_FAILURE; } - csr_roam_call_callback(pMac, SessionId, &proam_info, 0, + csr_roam_call_callback(pMac, SessionId, roam_info, 0, eCSR_ROAM_SET_CHANNEL_RSP, roamResult); } else { @@ -10425,7 +10802,8 @@ static QDF_STATUS sme_process_channel_change_resp(tpAniSirGlobal pMac, sme_err("Invalid Channel Change Resp Message: %d", status); } - qdf_mem_free(proam_info.channelChangeRespEvent); + qdf_mem_free(roam_info->channelChangeRespEvent); + qdf_mem_free(roam_info); return status; } @@ -11002,24 +11380,15 @@ QDF_STATUS sme_update_dsc_pto_up_mapping(tHalHandle hHal, sme_release_global_lock(&pMac->sme); return QDF_STATUS_E_FAILURE; } + for (i = 0; i < SME_QOS_WMM_UP_MAX; i++) { for (j = pSession->QosMapSet.dscp_range[i][0]; - j <= pSession->QosMapSet.dscp_range[i][1]; - j++) { - if ((pSession->QosMapSet.dscp_range[i][0] == 255) - && (pSession->QosMapSet.dscp_range[i][1] == - 255)) { - QDF_TRACE(QDF_MODULE_ID_SME, - QDF_TRACE_LEVEL_DEBUG, - FL("User Priority %d isn't used"), i); - break; - } else { + j <= pSession->QosMapSet.dscp_range[i][1] && + j <= WLAN_MAX_DSCP; j++) dscpmapping[j] = i; - } - } } for (i = 0; i < pSession->QosMapSet.num_dscp_exceptions; i++) - if (pSession->QosMapSet.dscp_exceptions[i][0] != 255) + if (pSession->QosMapSet.dscp_exceptions[i][0] <= WLAN_MAX_DSCP) dscpmapping[pSession->QosMapSet.dscp_exceptions[i][0]] = pSession->QosMapSet.dscp_exceptions[i][1]; @@ -11056,7 +11425,6 @@ QDF_STATUS sme_abort_roam_scan(tHalHandle hHal, uint8_t sessionId) return status; } -#ifdef FEATURE_WLAN_EXTSCAN /** * sme_get_valid_channels_by_band() - to fetch valid channels filtered by band * @hHal: HAL context @@ -11174,6 +11542,7 @@ QDF_STATUS sme_get_valid_channels_by_band(tHalHandle hHal, return status; } +#ifdef FEATURE_WLAN_EXTSCAN /* * sme_ext_scan_get_capabilities() - * SME API to fetch extscan capabilities @@ -12153,75 +12522,6 @@ QDF_STATUS sme_beacon_debug_stats_req( } #endif -#ifdef WLAN_FEATURE_ROAM_OFFLOAD -/* - * sme_update_roam_offload_enabled() - enable/disable roam offload feaure - * It is used at in the REG_DYNAMIC_VARIABLE macro definition of - * - * hHal - The handle returned by mac_open. - * nRoamOffloadEnabled - The bool to update with - * Return QDF_STATUS_SUCCESS - SME update config successfully. - * Other status means SME is failed to update. - */ - -QDF_STATUS sme_update_roam_offload_enabled(tHalHandle hHal, - bool nRoamOffloadEnabled) -{ - tpAniSirGlobal pMac = PMAC_STRUCT(hHal); - QDF_STATUS status = QDF_STATUS_SUCCESS; - - status = sme_acquire_global_lock(&pMac->sme); - if (QDF_IS_STATUS_SUCCESS(status)) { - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - "%s: LFR3:gRoamOffloadEnabled is changed from %d to %d", - __func__, pMac->roam.configParam.isRoamOffloadEnabled, - nRoamOffloadEnabled); - pMac->roam.configParam.isRoamOffloadEnabled = - nRoamOffloadEnabled; - sme_release_global_lock(&pMac->sme); - } - - return status; -} - -/** - * sme_update_roam_key_mgmt_offload_enabled() - enable/disable key mgmt offload - * This is a synchronous call - * @hal_ctx: The handle returned by mac_open. - * @session_id: Session Identifier - * @key_mgmt_offload_enabled: key mgmt enable/disable flag - * @pmkid_modes: PMKID modes of PMKSA caching and OKC - * Return: QDF_STATUS_SUCCESS - SME updated config successfully. - * Other status means SME is failed to update. - */ - -QDF_STATUS sme_update_roam_key_mgmt_offload_enabled(tHalHandle hal_ctx, - uint8_t session_id, - bool key_mgmt_offload_enabled, - struct pmkid_mode_bits *pmkid_modes) -{ - tpAniSirGlobal mac_ctx = PMAC_STRUCT(hal_ctx); - QDF_STATUS status = QDF_STATUS_SUCCESS; - - status = sme_acquire_global_lock(&mac_ctx->sme); - if (QDF_IS_STATUS_SUCCESS(status)) { - if (CSR_IS_SESSION_VALID(mac_ctx, session_id)) { - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - "%s: LFR3: key_mgmt_offload_enabled changed to %d", - __func__, key_mgmt_offload_enabled); - status = csr_roam_set_key_mgmt_offload(mac_ctx, - session_id, - key_mgmt_offload_enabled, - pmkid_modes); - } else - status = QDF_STATUS_E_INVAL; - sme_release_global_lock(&mac_ctx->sme); - } - - return status; -} -#endif - /* * sme_get_temperature() - * SME API to get the pdev temperature @@ -13802,9 +14102,14 @@ void sme_update_tgt_services(tHalHandle hal, struct wma_tgt_services *cfg) cfg->is_fils_roaming_supported; mac_ctx->is_11k_offload_supported = cfg->is_11k_offload_supported; - sme_debug("pmf_offload: %d fils_roam support %d 11k_offload %d", + mac_ctx->akm_service_bitmap = cfg->akm_service_bitmap; + mac_ctx->is_adaptive_11r_roam_supported = + cfg->is_adaptive_11r_roam_supported; + sme_debug("pmf_offload: %d fils_roam support %d 11k_offload %d akm_service_bitmap:%d adapt_11r:%d", mac_ctx->pmf_offload, mac_ctx->is_fils_roaming_supported, - mac_ctx->is_11k_offload_supported); + mac_ctx->is_11k_offload_supported, + mac_ctx->akm_service_bitmap, + mac_ctx->is_adaptive_11r_roam_supported); mac_ctx->bcn_reception_stats = cfg->bcn_reception_stats; } @@ -13963,17 +14268,17 @@ QDF_STATUS sme_handle_bcn_recv_start(mac_handle_t mac_handle, QDF_STATUS status; int ret; - if (!CSR_IS_SESSION_VALID(mac_ctx, vdev_id)) { - sme_err("CSR session not valid: %d", vdev_id); - return QDF_STATUS_E_FAILURE; - } - session = CSR_GET_SESSION(mac_ctx, vdev_id); if (!session) { sme_err("vdev_id %d not found", vdev_id); return QDF_STATUS_E_FAILURE; } + if (!CSR_IS_SESSION_VALID(mac_ctx, vdev_id)) { + sme_err("CSR session not valid: %d", vdev_id); + return QDF_STATUS_E_FAILURE; + } + status = sme_acquire_global_lock(&mac_ctx->sme); if (QDF_IS_STATUS_SUCCESS(status)) { if (session->is_bcn_recv_start) { @@ -14386,15 +14691,8 @@ uint32_t sme_get_wni_dot11_mode(tHalHandle hal) mac_ctx->roam.configParam.uCfgDot11Mode); } -/** - * sme_create_mon_session() - post message to create PE session for monitormode - * operation - * @hal_handle: Handle to the HAL - * @bssid: pointer to bssid - * - * Return: QDF_STATUS_SUCCESS on success, non-zero error code on failure. - */ -QDF_STATUS sme_create_mon_session(tHalHandle hal_handle, tSirMacAddr bss_id) +QDF_STATUS sme_create_mon_session(tHalHandle hal_handle, + tSirMacAddr bss_id, uint8_t vdev_id) { QDF_STATUS status = QDF_STATUS_E_FAILURE; struct sir_create_session *msg; @@ -14404,8 +14702,25 @@ QDF_STATUS sme_create_mon_session(tHalHandle hal_handle, tSirMacAddr bss_id) msg->type = eWNI_SME_MON_INIT_SESSION; msg->msg_len = sizeof(*msg); qdf_mem_copy(msg->bss_id.bytes, bss_id, QDF_MAC_ADDR_SIZE); + msg->vdev_id = vdev_id; + status = umac_send_mb_message_to_mac(msg); + } + return status; +} + +QDF_STATUS sme_delete_mon_session(mac_handle_t mac_handle, uint8_t vdev_id) +{ + QDF_STATUS status = QDF_STATUS_E_FAILURE; + struct sir_delete_session *msg; + + msg = qdf_mem_malloc(sizeof(*msg)); + if (msg) { + msg->type = eWNI_SME_MON_DEINIT_SESSION; + msg->vdev_id = vdev_id; + msg->msg_len = sizeof(*msg); status = umac_send_mb_message_to_mac(msg); } + return status; } @@ -15360,84 +15675,27 @@ QDF_STATUS sme_fast_reassoc(tHalHandle hal, struct csr_roam_profile *profile, const tSirMacAddr bssid, int channel, uint8_t vdev_id, const tSirMacAddr connected_bssid) { - QDF_STATUS status; - struct wma_roam_invoke_cmd *fastreassoc; - struct scheduler_msg msg = {0}; - tpAniSirGlobal mac_ctx = PMAC_STRUCT(hal); - struct csr_roam_session *session; - struct csr_roam_profile *roam_profile; + QDF_STATUS status = QDF_STATUS_E_FAILURE; + tpAniSirGlobal mac = PMAC_STRUCT(hal); - session = CSR_GET_SESSION(mac_ctx, vdev_id); - if (!session || !session->pCurRoamProfile) { - sme_err("session %d not found", vdev_id); + if (!mac) return QDF_STATUS_E_FAILURE; + if (!CSR_IS_SESSION_VALID(mac, vdev_id)) { + sme_err("Invalid vdev_id: %d", vdev_id); + return QDF_STATUS_E_INVAL; } - roam_profile = session->pCurRoamProfile; - if (roam_profile->driver_disabled_roaming) { - sme_debug("roaming status in driver %d", - roam_profile->driver_disabled_roaming); + if (QDF_IS_STATUS_ERROR(sme_acquire_global_lock(&mac->sme))) return QDF_STATUS_E_FAILURE; - } - fastreassoc = qdf_mem_malloc(sizeof(*fastreassoc)); - if (NULL == fastreassoc) { - sme_err("qdf_mem_malloc failed for fastreassoc"); - return QDF_STATUS_E_NOMEM; - } - /* if both are same then set the flag */ - if (!qdf_mem_cmp(connected_bssid, bssid, ETH_ALEN)) { - fastreassoc->is_same_bssid = true; - sme_debug("bssid same, bssid[%pM]", bssid); - } - fastreassoc->vdev_id = vdev_id; - fastreassoc->bssid[0] = bssid[0]; - fastreassoc->bssid[1] = bssid[1]; - fastreassoc->bssid[2] = bssid[2]; - fastreassoc->bssid[3] = bssid[3]; - fastreassoc->bssid[4] = bssid[4]; - fastreassoc->bssid[5] = bssid[5]; - - status = sme_get_beacon_frm(hal, profile, bssid, - &fastreassoc->frame_buf, - &fastreassoc->frame_len, - &channel); - - if (!channel) { - sme_err("channel retrieval from BSS desc fails!"); - qdf_mem_free(fastreassoc); - return QDF_STATUS_E_FAULT; - } - fastreassoc->channel = channel; - if (QDF_STATUS_SUCCESS != status) { - sme_warn("sme_get_beacon_frm failed"); - fastreassoc->frame_buf = NULL; - fastreassoc->frame_len = 0; - } - - if (csr_is_auth_type_ese(mac_ctx->roam.roamSession[vdev_id]. - connectedProfile.AuthType)) { - sme_debug("Beacon is not required for ESE"); - if (fastreassoc->frame_len) { - qdf_mem_free(fastreassoc->frame_buf); - fastreassoc->frame_buf = NULL; - fastreassoc->frame_len = 0; - } - } + status = csr_fast_reassoc(hal, profile, bssid, channel, vdev_id, + connected_bssid); - msg.type = eWNI_SME_ROAM_INVOKE; - msg.reserved = 0; - msg.bodyptr = fastreassoc; - status = scheduler_post_message(QDF_MODULE_ID_SME, - QDF_MODULE_ID_PE, - QDF_MODULE_ID_PE, &msg); - if (QDF_STATUS_SUCCESS != status) { - sme_err("Not able to post ROAM_INVOKE_CMD message to PE"); - qdf_mem_free(fastreassoc); - } + sme_release_global_lock(&mac->sme); return status; } + #endif QDF_STATUS sme_set_del_pmkid_cache(tHalHandle hal, uint8_t session_id, @@ -15457,8 +15715,10 @@ QDF_STATUS sme_set_del_pmkid_cache(tHalHandle hal, uint8_t session_id, pmk_cache->session_id = session_id; - if (!pmk_cache_info) + if (!pmk_cache_info) { + pmk_cache->is_flush_all = true; goto send_flush_cmd; + } if (!pmk_cache_info->ssid_len) { pmk_cache->cat_flag = WMI_PMK_CACHE_CAT_FLAG_BSSID; @@ -16348,39 +16608,102 @@ int sme_get_sec20chan_freq_mhz(struct wlan_objmgr_vdev *vdev, #ifdef WLAN_FEATURE_SAE QDF_STATUS sme_handle_sae_msg(tHalHandle hal, uint8_t session_id, - uint8_t sae_status) + uint8_t sae_status, struct qdf_mac_addr peer_mac_addr, + const uint8_t *pmkid) { QDF_STATUS qdf_status = QDF_STATUS_SUCCESS; tpAniSirGlobal mac = PMAC_STRUCT(hal); struct sir_sae_msg *sae_msg; struct scheduler_msg sch_msg = {0}; + struct wmi_roam_auth_status_params *params; + struct csr_roam_session *csr_session; qdf_status = sme_acquire_global_lock(&mac->sme); - if (QDF_IS_STATUS_SUCCESS(qdf_status)) { + if (QDF_IS_STATUS_ERROR(qdf_status)) + return qdf_status; + + csr_session = CSR_GET_SESSION(mac, session_id); + if (!csr_session) { + sme_err("session %d not found", session_id); + qdf_status = QDF_STATUS_E_FAILURE; + goto error; + } + + /* Update the status to SME in below cases + * 1. SAP mode: Always + * 2. STA mode: When the device is not in joined state + * + * If the device is in joined state, send the status to WMA which + * is meant for roaming. + */ + if ((csr_session->pCurRoamProfile && + csr_session->pCurRoamProfile->csrPersona == QDF_SAP_MODE) || + !CSR_IS_ROAM_JOINED(mac, session_id)) { sae_msg = qdf_mem_malloc(sizeof(*sae_msg)); if (!sae_msg) { qdf_status = QDF_STATUS_E_NOMEM; sme_err("SAE: memory allocation failed"); - } else { - sae_msg->message_type = eWNI_SME_SEND_SAE_MSG; - sae_msg->length = sizeof(*sae_msg); - sae_msg->session_id = session_id; - sae_msg->sae_status = sae_status; - sme_debug("SAE: sae_status %d session_id %d", - sae_msg->sae_status, - sae_msg->session_id); - - sch_msg.type = eWNI_SME_SEND_SAE_MSG; - sch_msg.bodyptr = sae_msg; - - qdf_status = - scheduler_post_message(QDF_MODULE_ID_SME, - QDF_MODULE_ID_PE, - QDF_MODULE_ID_PE, - &sch_msg); + goto error; + } + sae_msg->message_type = eWNI_SME_SEND_SAE_MSG; + sae_msg->length = sizeof(*sae_msg); + sae_msg->session_id = session_id; + sae_msg->sae_status = sae_status; + sme_debug("SAE: sae_status %d session_id %d", + sae_msg->sae_status, sae_msg->session_id); + + sch_msg.type = eWNI_SME_SEND_SAE_MSG; + sch_msg.bodyptr = sae_msg; + + qdf_status = scheduler_post_message(QDF_MODULE_ID_SME, + QDF_MODULE_ID_PE, + QDF_MODULE_ID_PE, + &sch_msg); + if (QDF_IS_STATUS_ERROR(qdf_status)) { + qdf_mem_free(sae_msg); + goto error; + } + } else { + /* + * For WPA3 SAE roaming, external auth offload is enabled. The + * firmware will send preauth start event after candidate + * selection. The supplicant will perform the SAE authentication + * and will send the auth status, PMKID in the external auth + * cmd. + * + * csr roam state is CSR_ROAM_STATE_JOINED. So this SAE + * external auth event is for wpa3 roam pre-auth offload. + * + * Post the preauth status to WMA. + */ + params = qdf_mem_malloc(sizeof(*params)); + if (!params) { + qdf_status = QDF_STATUS_E_NOMEM; + goto error; + } + + params->vdev_id = session_id; + params->preauth_status = sae_status; + qdf_copy_macaddr(¶ms->bssid, &peer_mac_addr); + + qdf_mem_zero(params->pmkid, PMKID_LEN); + if (pmkid) + qdf_mem_copy(params->pmkid, pmkid, PMKID_LEN); + + sch_msg.type = WMA_ROAM_PRE_AUTH_STATUS; + sch_msg.bodyptr = params; + + qdf_status = scheduler_post_message(QDF_MODULE_ID_SME, + QDF_MODULE_ID_WMA, + QDF_MODULE_ID_WMA, + &sch_msg); + if (QDF_IS_STATUS_ERROR(qdf_status)) { + sme_err("WMA_ROAM_PRE_AUTH_STATUS cmd posting failed"); + qdf_mem_free(params); } - sme_release_global_lock(&mac->sme); } +error: + sme_release_global_lock(&mac->sme); return qdf_status; } @@ -16566,24 +16889,26 @@ static void sme_scan_event_handler(struct wlan_objmgr_vdev *vdev, void *arg) { struct sAniSirGlobal *mac = arg; - struct csr_roam_session *session; + uint8_t vdev_id; if (!mac) { sme_err("Invalid mac context"); return; } - if (!CSR_IS_SESSION_VALID(mac, vdev->vdev_objmgr.vdev_id)) { - sme_err("Invalid vdev_id: %d", vdev->vdev_objmgr.vdev_id); + if (!mac->sme.beacon_pause_cb) return; - } - session = CSR_GET_SESSION(mac, vdev->vdev_objmgr.vdev_id); + if (event->type != SCAN_EVENT_TYPE_STARTED) + return; - if (event->type == SCAN_EVENT_TYPE_STARTED) { - if (mac->sme.beacon_pause_cb) - mac->sme.beacon_pause_cb(mac->hdd_handle, - vdev->vdev_objmgr.vdev_id, event->type, false); + for (vdev_id = 0 ; vdev_id < CSR_ROAM_SESSION_MAX ; vdev_id++) { + if (CSR_IS_SESSION_VALID(mac, vdev_id) && + sme_is_beacon_report_started(MAC_HANDLE(mac), vdev_id)) { + sme_debug("Send pause ind for vdev_id : %d", vdev_id); + mac->sme.beacon_pause_cb(mac->hdd_handle, vdev_id, + event->type, false); + } } } @@ -16649,8 +16974,15 @@ QDF_STATUS sme_set_roam_config_enable(mac_handle_t mac_handle, uint8_t roam_control_enable) { tpAniSirGlobal mac = PMAC_STRUCT(mac_handle); + tCsrNeighborRoamControlInfo *neighbor_roam_info; + tCsrNeighborRoamCfgParams *cfg_params; QDF_STATUS status; + if (!mac->roam.configParam.isRoamOffloadScanEnabled) { + sme_err("Roam offload scan not enabled"); + return QDF_STATUS_E_INVAL; + } + if (!CSR_IS_SESSION_VALID(mac, vdev_id)) { sme_err("Invalid vdev_id: %d", vdev_id); return QDF_STATUS_E_INVAL; @@ -16661,8 +16993,19 @@ QDF_STATUS sme_set_roam_config_enable(mac_handle_t mac_handle, sme_err("Failed to acquire sme lock; status: %d", status); return status; } - mac->roam.neighborRoamInfo[vdev_id].roam_control_enable = - !!roam_control_enable; + neighbor_roam_info = &mac->roam.neighborRoamInfo[vdev_id]; + + neighbor_roam_info->roam_control_enable = !!roam_control_enable; + if (roam_control_enable) { + cfg_params = &neighbor_roam_info->cfgParams; + cfg_params->roam_scan_period_after_inactivity = 0; + cfg_params->roam_inactive_data_packet_count = 0; + cfg_params->roam_scan_inactivity_time = 0; + + csr_roam_offload_scan(mac, vdev_id, + ROAM_SCAN_OFFLOAD_UPDATE_CFG, + REASON_ROAM_CONTROL_CONFIG_ENABLED); + } sme_release_global_lock(&mac->sme); return status; @@ -16724,3 +17067,176 @@ sme_get_full_roam_scan_period(mac_handle_t mac_handle, uint8_t vdev_id, return status; } + +QDF_STATUS sme_set_roam_triggers(mac_handle_t mac_handle, + struct roam_triggers *triggers) +{ + QDF_STATUS status; + tpAniSirGlobal mac = PMAC_STRUCT(mac_handle); + struct scheduler_msg message = {0}; + struct roam_triggers *roam_trigger_data; + tCsrNeighborRoamControlInfo *neighbor_roam_info; + + /* per contract must make a copy of the params when messaging */ + roam_trigger_data = qdf_mem_malloc(sizeof(*roam_trigger_data)); + if (!roam_trigger_data) + return QDF_STATUS_E_NOMEM; + + *roam_trigger_data = *triggers; + + neighbor_roam_info = &mac->roam.neighborRoamInfo[triggers->vdev_id]; + neighbor_roam_info->cfgParams.roam_trigger_bitmap = + roam_trigger_data->trigger_bitmap; + status = sme_acquire_global_lock(&mac->sme); + if (QDF_IS_STATUS_ERROR(status)) { + qdf_mem_free(roam_trigger_data); + return status; + } + + /* Serialize the req through MC thread */ + message.bodyptr = roam_trigger_data; + message.type = SIR_HAL_SET_ROAM_TRIGGERS; + status = scheduler_post_message(QDF_MODULE_ID_SME, + QDF_MODULE_ID_WMA, + QDF_MODULE_ID_WMA, + &message); + sme_release_global_lock(&mac->sme); + if (QDF_IS_STATUS_ERROR(status)) { + sme_err("failed to post ROAM_TRIGGERS msg"); + qdf_mem_free(roam_trigger_data); + } + + return status; +} + +QDF_STATUS sme_set_disconnect_ies(mac_handle_t mac_handle, uint8_t vdev_id, + uint8_t *ie_data, uint16_t ie_len) +{ + tpAniSirGlobal mac_ctx = PMAC_STRUCT(mac_handle); + struct wlan_objmgr_vdev *vdev; + struct wlan_ies ie; + + if (!ie_data || !ie_len) { + sme_debug("Got NULL disconnect IEs"); + return QDF_STATUS_E_INVAL; + } + + vdev = wlan_objmgr_get_vdev_by_id_from_psoc(mac_ctx->psoc, + vdev_id, + WLAN_LEGACY_SME_ID); + if (!vdev) { + sme_err("Got NULL vdev obj, returning"); + return QDF_STATUS_E_FAILURE; + } + + ie.data = ie_data; + ie.len = ie_len; + + mlme_set_self_disconnect_ies(vdev, &ie); + + wlan_objmgr_vdev_release_ref(vdev, WLAN_LEGACY_SME_ID); + return QDF_STATUS_SUCCESS; +} + +#ifdef FEATURE_ANI_LEVEL_REQUEST +QDF_STATUS sme_get_ani_level(mac_handle_t mac_handle, uint32_t *freqs, + uint8_t num_freqs, void (*callback)( + struct wmi_host_ani_level_event *ani, uint8_t num, + void *context), void *context) +{ + QDF_STATUS status = QDF_STATUS_E_FAILURE; + tpAniSirGlobal mac = PMAC_STRUCT(mac_handle); + void *wma_handle; + + wma_handle = cds_get_context(QDF_MODULE_ID_WMA); + if (!wma_handle) { + sme_err("wma handle is NULL"); + return QDF_STATUS_E_FAILURE; + } + + mac->ani_params.ani_level_cb = callback; + mac->ani_params.context = context; + + status = wma_send_ani_level_request(wma_handle, freqs, num_freqs); + return status; +} +#endif /* FEATURE_ANI_LEVEL_REQUEST */ + +#ifdef FEATURE_OEM_DATA +QDF_STATUS sme_set_oem_data_event_handler_cb( + mac_handle_t mac_handle, + void (*oem_data_event_handler_cb) + (const struct oem_data *oem_event_data)) +{ + tpAniSirGlobal mac = PMAC_STRUCT(mac_handle); + QDF_STATUS qdf_status; + + qdf_status = sme_acquire_global_lock(&mac->sme); + if (QDF_IS_STATUS_SUCCESS(qdf_status)) { + mac->sme.oem_data_event_handler_cb = oem_data_event_handler_cb; + sme_release_global_lock(&mac->sme); + } + return qdf_status; +} + +void sme_reset_oem_data_event_handler_cb(mac_handle_t mac_handle) +{ + tpAniSirGlobal pmac; + QDF_STATUS qdf_status; + + if (!mac_handle) { + sme_err("mac_handle is not valid"); + return; + } + pmac = PMAC_STRUCT(mac_handle); + + qdf_status = sme_acquire_global_lock(&pmac->sme); + if (QDF_IS_STATUS_SUCCESS(qdf_status)) { + pmac->sme.oem_data_event_handler_cb = NULL; + sme_release_global_lock(&pmac->sme); + } +} +#endif + +QDF_STATUS sme_get_prev_connected_bss_ies(mac_handle_t mac_handle, + uint8_t vdev_id, + uint8_t **ies, uint32_t *ie_len) +{ + struct csr_roam_session *session; + struct sAniSirGlobal *mac = MAC_CONTEXT(mac_handle); + QDF_STATUS status = QDF_STATUS_SUCCESS; + uint32_t len; + uint8_t *beacon_ie; + + session = CSR_GET_SESSION(mac, vdev_id); + if (!session) { + sme_err("session not found"); + return QDF_STATUS_E_INVAL; + } + + status = sme_acquire_global_lock(&mac->sme); + if (QDF_IS_STATUS_ERROR(status)) { + sme_err("Failed to acquire sme lock; status: %d", status); + return status; + } + + len = session->prev_assoc_ap_info.nBeaconLength; + if (!len) { + sme_debug("No IEs to return"); + status = QDF_STATUS_E_INVAL; + goto end; + } + beacon_ie = qdf_mem_malloc(len); + if (!beacon_ie) { + sme_err("Failed to alloc mem for beacon IEs"); + status = QDF_STATUS_E_NOMEM; + goto end; + } + qdf_mem_copy(beacon_ie, session->prev_assoc_ap_info.pbFrames, len); + + *ie_len = len; + *ies = beacon_ie; +end: + sme_release_global_lock(&mac->sme); + return status; +} diff --git a/drivers/staging/qcacld-3.0/core/sme/src/common/sme_power_save.c b/drivers/staging/qcacld-3.0/core/sme/src/common/sme_power_save.c index 51ca317fda61..d3234a451853 100644 --- a/drivers/staging/qcacld-3.0/core/sme/src/common/sme_power_save.c +++ b/drivers/staging/qcacld-3.0/core/sme/src/common/sme_power_save.c @@ -143,7 +143,6 @@ static QDF_STATUS sme_ps_enable_ps_req_params(tpAniSirGlobal mac_ctx, uint32_t session_id) { struct sEnablePsParams *enable_ps_req_params; - QDF_STATUS status = QDF_STATUS_SUCCESS; struct ps_global_info *ps_global_info = &mac_ctx->sme.ps_global_info; struct ps_params *ps_param = &ps_global_info->ps_params[session_id]; enum ps_state ps_state; @@ -165,13 +164,12 @@ static QDF_STATUS sme_ps_enable_ps_req_params(tpAniSirGlobal mac_ctx, ps_state = LEGACY_POWER_SAVE_MODE; } enable_ps_req_params->sessionid = session_id; + wma_enable_sta_ps_mode(enable_ps_req_params); + qdf_mem_free(enable_ps_req_params); + sme_debug("Powersave Enable sent to FW"); - status = sme_post_ps_msg_to_wma(WMA_ENTER_PS_REQ, enable_ps_req_params); - if (!QDF_IS_STATUS_SUCCESS(status)) - return QDF_STATUS_E_FAILURE; - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - FL("Message WMA_ENTER_PS_REQ Successfully sent to WMA")); ps_param->ps_state = ps_state; + return QDF_STATUS_SUCCESS; } @@ -186,7 +184,6 @@ static QDF_STATUS sme_ps_disable_ps_req_params(tpAniSirGlobal mac_ctx, uint32_t session_id) { struct sDisablePsParams *disable_ps_req_params; - QDF_STATUS status = QDF_STATUS_SUCCESS; disable_ps_req_params = qdf_mem_malloc(sizeof(*disable_ps_req_params)); if (NULL == disable_ps_req_params) { @@ -196,13 +193,11 @@ static QDF_STATUS sme_ps_disable_ps_req_params(tpAniSirGlobal mac_ctx, disable_ps_req_params->psSetting = eSIR_ADDON_NOTHING; disable_ps_req_params->sessionid = session_id; - - status = sme_post_ps_msg_to_wma(WMA_EXIT_PS_REQ, disable_ps_req_params); - if (!QDF_IS_STATUS_SUCCESS(status)) - return QDF_STATUS_E_FAILURE; - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - FL("Message WMA_EXIT_PS_REQ Successfully sent to WMA")); + wma_disable_sta_ps_mode(disable_ps_req_params); + qdf_mem_free(disable_ps_req_params); + sme_debug("Powersave disable sent to FW"); sme_set_ps_state(mac_ctx, session_id, FULL_POWER_MODE); + return QDF_STATUS_SUCCESS; } @@ -405,7 +400,6 @@ QDF_STATUS sme_ps_timer_flush_sync(tHalHandle hal, uint8_t session_id) enum ps_state ps_state; QDF_TIMER_STATE tstate; struct sEnablePsParams *req; - t_wma_handle *wma; QDF_BUG(session_id < CSR_ROAM_SESSION_MAX); if (session_id >= CSR_ROAM_SESSION_MAX) @@ -426,12 +420,6 @@ QDF_STATUS sme_ps_timer_flush_sync(tHalHandle hal, uint8_t session_id) qdf_mc_timer_stop(&ps_parm->auto_ps_enable_timer); - wma = cds_get_context(QDF_MODULE_ID_WMA); - if (!wma) { - sme_err("wma is null"); - return QDF_STATUS_E_INVAL; - } - req = qdf_mem_malloc(sizeof(*req)); if (!req) { sme_err("out of memory"); @@ -450,7 +438,7 @@ QDF_STATUS sme_ps_timer_flush_sync(tHalHandle hal, uint8_t session_id) } req->sessionid = session_id; - wma_enable_sta_ps_mode(wma, req); + wma_enable_sta_ps_mode(req); qdf_mem_free(req); ps_parm->ps_state = ps_state; diff --git a/drivers/staging/qcacld-3.0/core/sme/src/common/sme_trace.c b/drivers/staging/qcacld-3.0/core/sme/src/common/sme_trace.c index b5200a64d6d2..d0df7ff9d6c2 100644 --- a/drivers/staging/qcacld-3.0/core/sme/src/common/sme_trace.c +++ b/drivers/staging/qcacld-3.0/core/sme/src/common/sme_trace.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -179,28 +179,28 @@ static void sme_trace_dump(void *mac_ctx, tp_qdf_trace_record record, { switch (record->code) { case TRACE_CODE_SME_COMMAND: - sme_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", + sme_nofl_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", rec_index, record->qtime, record->time, record->session, "SME COMMAND:", sme_trace_get_command_string(record->data), record->data); break; case TRACE_CODE_SME_TX_WMA_MSG: - sme_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", + sme_nofl_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", rec_index, record->qtime, record->time, record->session, "TX WMA Msg:", mac_trace_get_wma_msg_string((uint16_t)record->data), record->data); break; case TRACE_CODE_SME_RX_WMA_MSG: - sme_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", + sme_nofl_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", rec_index, record->qtime, record->time, record->session, "RX WMA Msg:", mac_trace_get_sme_msg_string((uint16_t)record->data), record->data); break; default: - sme_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", + sme_nofl_debug("%04d %012llu %s S%d %-14s %-30s(0x%x)", rec_index, record->qtime, record->time, record->session, "RX HDD MSG:", sme_trace_get_rx_msg_string(record->code), diff --git a/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_api_roam.c b/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_api_roam.c index 604fb7a2e4f5..97dc2b419830 100644 --- a/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_api_roam.c +++ b/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_api_roam.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -56,6 +56,10 @@ #include #include #include "wlan_mlme_main.h" +#include "wlan_policy_mgr_i.h" +#include "wlan_scan_utils_api.h" +#include +#include "wlan_pkt_capture_ucfg_api.h" #define MAX_PWR_FCC_CHAN_12 8 #define MAX_PWR_FCC_CHAN_13 2 @@ -75,6 +79,10 @@ #define CSR_MIN_GLOBAL_STAT_QUERY_PERIOD 500 /* ms */ #define CSR_MIN_GLOBAL_STAT_QUERY_PERIOD_IN_BMPS 2000 /* ms */ #define CSR_MIN_TL_STAT_QUERY_PERIOD 500 /* ms */ + +#define CSR_SINGLE_PMK_OUI "\x00\x40\x96\x03" +#define CSR_SINGLE_PMK_OUI_SIZE 4 + /* Flag to send/do not send disassoc frame over the air */ #define CSR_DONT_SEND_DISASSOC_OVER_THE_AIR 1 #define RSSI_HACK_BMPS (-40) @@ -418,10 +426,10 @@ static bool csr_roam_is_same_profile_keys(tpAniSirGlobal pMac, struct csr_roam_profile *pProfile2); static QDF_STATUS csr_roam_start_roaming_timer(tpAniSirGlobal pMac, - uint32_t sessionId, + uint32_t vdev_id, uint32_t interval); static QDF_STATUS csr_roam_stop_roaming_timer(tpAniSirGlobal pMac, - uint32_t sessionId); + uint32_t vdev_id); static void csr_roam_roaming_timer_handler(void *pv); #ifdef WLAN_FEATURE_ROAM_OFFLOAD static void csr_roam_roaming_offload_timer_action(tpAniSirGlobal mac_ctx, @@ -1030,6 +1038,37 @@ static void csr_add_social_channels(tpAniSirGlobal mac, } #endif +/** + * csr_scan_event_handler() - callback for scan event + * @vdev: wlan objmgr vdev pointer + * @event: scan event + * @arg: global mac context pointer + * + * Return: void + */ +static void csr_scan_event_handler(struct wlan_objmgr_vdev *vdev, + struct scan_event *event, + void *arg) +{ + bool success = false; + QDF_STATUS lock_status; + tpAniSirGlobal pMac = arg; + + if (!pMac) + return; + + if (!util_is_scan_completed(event, &success)) + return; + + lock_status = sme_acquire_global_lock(&pMac->sme); + if (QDF_IS_STATUS_ERROR(lock_status)) + return; + + if (pMac->scan.pending_channel_list_req) + csr_update_channel_list(pMac); + sme_release_global_lock(&pMac->sme); +} + QDF_STATUS csr_update_channel_list(tpAniSirGlobal pMac) { tSirUpdateChanList *pChanList; @@ -1045,6 +1084,10 @@ QDF_STATUS csr_update_channel_list(tpAniSirGlobal pMac) uint16_t cnt = 0; uint8_t channel; bool is_unsafe_chan; + enum scm_scan_status scan_status; + QDF_STATUS lock_status; + bool is_5mhz_enabled; + bool is_10mhz_enabled; qdf_device_t qdf_ctx = cds_get_context(QDF_MODULE_ID_QDF_DEVICE); if (!qdf_ctx) { @@ -1052,6 +1095,23 @@ QDF_STATUS csr_update_channel_list(tpAniSirGlobal pMac) return QDF_STATUS_E_FAILURE; } + lock_status = sme_acquire_global_lock(&pMac->sme); + if (QDF_IS_STATUS_ERROR(lock_status)) + return lock_status; + + if (pMac->roam.configParam.enable_pending_list_req) { + scan_status = ucfg_scan_get_pdev_status(pMac->pdev); + if (scan_status == SCAN_IS_ACTIVE || + scan_status == SCAN_IS_ACTIVE_AND_PENDING) { + pMac->scan.pending_channel_list_req = true; + sme_release_global_lock(&pMac->sme); + sme_debug("scan in progress postpone channel list req "); + return QDF_STATUS_SUCCESS; + } + pMac->scan.pending_channel_list_req = false; + } + sme_release_global_lock(&pMac->sme); + pld_get_wlan_unsafe_channel(qdf_ctx->dev, unsafe_chan, &unsafe_chan_cnt, sizeof(unsafe_chan)); @@ -1069,6 +1129,13 @@ QDF_STATUS csr_update_channel_list(tpAniSirGlobal pMac) return QDF_STATUS_E_NOMEM; } + is_5mhz_enabled = cds_is_5_mhz_enabled(); + if (is_5mhz_enabled) + sme_nofl_debug("quarter_rate enabled"); + is_10mhz_enabled = cds_is_10_mhz_enabled(); + if (is_10mhz_enabled) + sme_nofl_debug("half_rate enabled"); + for (i = 0; i < pScan->base_channels.numChannels; i++) { struct csr_sta_roam_policy_params *roam_policy = &pMac->roam.configParam.sta_roam_policy; @@ -1154,18 +1221,11 @@ QDF_STATUS csr_update_channel_list(tpAniSirGlobal pMac) else pChanList->chanParam[num_channel].dfsSet = true; - if (cds_is_5_mhz_enabled()) - pChanList->chanParam[num_channel].quarter_rate - = 1; - else if (cds_is_10_mhz_enabled()) - pChanList->chanParam[num_channel].half_rate = 1; - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - "channel:%d, pwr=%d, DFS=%d qrate %d hrate %d ", - pChanList->chanParam[num_channel].chanId, - pChanList->chanParam[num_channel].pwr, - pChanList->chanParam[num_channel].dfsSet, - pChanList->chanParam[num_channel].quarter_rate, - pChanList->chanParam[num_channel].half_rate); + + pChanList->chanParam[num_channel].quarter_rate = + is_5mhz_enabled; + pChanList->chanParam[num_channel].half_rate = + is_10mhz_enabled; num_channel++; } } @@ -1251,6 +1311,14 @@ QDF_STATUS csr_start(tpAniSirGlobal pMac) pMac->psoc, "CSR", csr_scan_callback, pMac); ucfg_scan_set_enable(pMac->psoc, true); + + if (pMac->roam.configParam.enable_pending_list_req) { + status = ucfg_scan_register_event_handler(pMac->pdev, + csr_scan_event_handler, pMac); + + if (QDF_IS_STATUS_ERROR(status)) + sme_err("scan event registration failed "); + } } while (0); return status; } @@ -1259,6 +1327,10 @@ QDF_STATUS csr_stop(tpAniSirGlobal pMac) { uint32_t sessionId; + if (pMac->roam.configParam.enable_pending_list_req) + ucfg_scan_unregister_event_handler(pMac->pdev, + csr_scan_event_handler, + pMac); ucfg_scan_set_enable(pMac->psoc, false); ucfg_scan_unregister_requester(pMac->psoc, pMac->scan.requester_id); @@ -1393,11 +1465,11 @@ static QDF_STATUS csr_roam_open(tpAniSirGlobal pMac) for (i = 0; i < CSR_ROAM_SESSION_MAX; i++) { pSession = CSR_GET_SESSION(pMac, i); pSession->roamingTimerInfo.pMac = pMac; - pSession->roamingTimerInfo.sessionId = + pSession->roamingTimerInfo.vdev_id = CSR_SESSION_ID_INVALID; } pMac->roam.WaitForKeyTimerInfo.pMac = pMac; - pMac->roam.WaitForKeyTimerInfo.sessionId = + pMac->roam.WaitForKeyTimerInfo.vdev_id = CSR_SESSION_ID_INVALID; status = qdf_mc_timer_init(&pMac->roam.hTimerWaitForKey, QDF_TIMER_TYPE_SW, @@ -1623,12 +1695,12 @@ void csr_roam_substate_change(tpAniSirGlobal pMac, sessionId); return; } - sme_debug("CSR RoamSubstate: [ %s <== %s ]", - mac_trace_getcsr_roam_sub_state(NewSubstate), - mac_trace_getcsr_roam_sub_state(pMac->roam. - curSubState[sessionId])); if (pMac->roam.curSubState[sessionId] == NewSubstate) return; + sme_nofl_debug("CSR RoamSubstate: [ %s <== %s ]", + mac_trace_getcsr_roam_sub_state(NewSubstate), + mac_trace_getcsr_roam_sub_state(pMac->roam. + curSubState[sessionId])); spin_lock(&pMac->roam.roam_state_lock); pMac->roam.curSubState[sessionId] = NewSubstate; spin_unlock(&pMac->roam.roam_state_lock); @@ -1640,22 +1712,23 @@ enum csr_roam_state csr_roam_state_change(tpAniSirGlobal pMac, { enum csr_roam_state PreviousState; - sme_debug("CSR RoamState[%hu]: [ %s <== %s ]", sessionId, - mac_trace_getcsr_roam_state(NewRoamState), - mac_trace_getcsr_roam_state(pMac->roam.curState[sessionId])); PreviousState = pMac->roam.curState[sessionId]; + if (NewRoamState == pMac->roam.curState[sessionId]) + return PreviousState; + + sme_nofl_debug("CSR RoamState[%hu]: [ %s <== %s ]", sessionId, + mac_trace_getcsr_roam_state(NewRoamState), + mac_trace_getcsr_roam_state(pMac->roam.curState[sessionId])); + /* Whenever we transition OUT of the Roaming state, + * clear the Roaming substate. + */ + if (CSR_IS_ROAM_JOINING(pMac, sessionId)) { + csr_roam_substate_change(pMac, eCSR_ROAM_SUBSTATE_NONE, + sessionId); + } - if (NewRoamState != pMac->roam.curState[sessionId]) { - /* Whenever we transition OUT of the Roaming state, - * clear the Roaming substate. - */ - if (CSR_IS_ROAM_JOINING(pMac, sessionId)) { - csr_roam_substate_change(pMac, eCSR_ROAM_SUBSTATE_NONE, - sessionId); - } + pMac->roam.curState[sessionId] = NewRoamState; - pMac->roam.curState[sessionId] = NewRoamState; - } return PreviousState; } @@ -1664,7 +1737,6 @@ void csr_assign_rssi_for_category(tpAniSirGlobal pMac, int8_t bestApRssi, { int i; - sme_debug("best AP RSSI: %d cat offset: %d", bestApRssi, catOffset); if (catOffset) { pMac->roam.configParam.bCatRssiOffset = catOffset; for (i = 0; i < CSR_NUM_RSSI_CAT; i++) { @@ -1858,7 +1930,6 @@ QDF_STATUS csr_create_bg_scan_roam_channel_list(tpAniSirGlobal pMac, return status; } - #ifdef FEATURE_WLAN_ESE /** * csr_create_roam_scan_channel_list() - create roam scan channel list @@ -2062,8 +2133,8 @@ static void csr_send_ese_adjacent_ap_rep_ind(tpAniSirGlobal pMac, struct csr_roam_session *pSession) { uint32_t roamTS2 = 0; - struct csr_roam_info roamInfo; tpPESession pSessionEntry = NULL; + struct csr_roam_info *roam_info; uint8_t sessionId = CSR_SESSION_ID_INVALID; if (NULL == pSession) { @@ -2071,25 +2142,30 @@ static void csr_send_ese_adjacent_ap_rep_ind(tpAniSirGlobal pMac, return; } + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return; roamTS2 = qdf_mc_timer_get_system_time(); - roamInfo.tsmRoamDelay = roamTS2 - pSession->roamTS1; + roam_info->tsmRoamDelay = roamTS2 - pSession->roamTS1; sme_debug("Bssid(" MAC_ADDRESS_STR ") Roaming Delay(%u ms)", MAC_ADDR_ARRAY(pSession->connectedProfile.bssid.bytes), - roamInfo.tsmRoamDelay); + roam_info->tsmRoamDelay); pSessionEntry = pe_find_session_by_bssid(pMac, pSession->connectedProfile.bssid.bytes, &sessionId); if (NULL == pSessionEntry) { sme_err("session %d not found", sessionId); + qdf_mem_free(roam_info); return; } pSessionEntry->eseContext.tsm.tsmMetrics.RoamingDly - = roamInfo.tsmRoamDelay; + = roam_info->tsmRoamDelay; - csr_roam_call_callback(pMac, pSession->sessionId, &roamInfo, + csr_roam_call_callback(pMac, pSession->sessionId, roam_info, 0, eCSR_ROAM_ESE_ADJ_AP_REPORT_IND, 0); + qdf_mem_free(roam_info); } /** @@ -2731,7 +2807,7 @@ static inline void csr_start_bss_copy_he_cap(tSirSmeStartBssReq *req, #endif /** - * csr_set_11k_offload_config_param() - Update 11k neighbor report config + * csr_update_11k_offload_config_param() - Update 11k neighbor report config * * @csr_config: pointer to csr_config in MAC context * @pParam: pointer to config params from HDD @@ -2739,7 +2815,7 @@ static inline void csr_start_bss_copy_he_cap(tSirSmeStartBssReq *req, * Return: none */ static -void csr_set_11k_offload_config_param(struct csr_config *csr_config, +void csr_update_11k_offload_config_param(struct csr_config *csr_config, tCsrConfigParam *param) { csr_config->offload_11k_enable_bitmask = @@ -2811,6 +2887,34 @@ static void csr_get_roam_preauth_config_param(tCsrConfigParam *pparam, } #endif +#ifdef WLAN_ADAPTIVE_11R +static void +csr_update_adaptive_11r_config_param(tpAniSirGlobal mac, tCsrConfigParam *param) +{ + mac->roam.configParam.enable_adaptive_11r = + param->enable_adaptive_11r; +} +#else +static void +csr_update_adaptive_11r_config_param(tpAniSirGlobal mac, tCsrConfigParam *param) +{ +} +#endif + +#if defined(WLAN_SAE_SINGLE_PMK) && defined(WLAN_FEATURE_ROAM_OFFLOAD) +static void +csr_update_sae_single_pmk_cfg_param(tpAniSirGlobal mac, tCsrConfigParam *param) +{ + mac->roam.configParam.sae_single_pmk_feature_enabled = + param->sae_single_pmk_feature_enabled; +} +#else +static void +csr_update_sae_single_pmk_cfg_param(tpAniSirGlobal mac, tCsrConfigParam *param) +{ +} +#endif + QDF_STATUS csr_change_default_config_param(tpAniSirGlobal pMac, tCsrConfigParam *pParam) { @@ -3030,66 +3134,7 @@ QDF_STATUS csr_change_default_config_param(tpAniSirGlobal pMac, qdf_mem_copy(&pMac->roam.configParam.neighborRoamConfig, &pParam->neighborRoamConfig, sizeof(tCsrNeighborRoamConfigParams)); - sme_debug("nNeighborScanTimerPerioid: %d", - pMac->roam.configParam.neighborRoamConfig. - nNeighborScanTimerPeriod); - sme_debug("neighbor_scan_min_timer_period: %d", - pMac->roam.configParam.neighborRoamConfig. - neighbor_scan_min_timer_period); - sme_debug("nNeighborLookupRssiThreshold: %d", - pMac->roam.configParam.neighborRoamConfig. - nNeighborLookupRssiThreshold); - sme_debug("rssi_thresh_offset_5g: %d", - pMac->roam.configParam.neighborRoamConfig.rssi_thresh_offset_5g); - sme_debug("nOpportunisticThresholdDiff: %d", - pMac->roam.configParam.neighborRoamConfig. - nOpportunisticThresholdDiff); - sme_debug("nRoamRescanRssiDiff: %d", - pMac->roam.configParam.neighborRoamConfig. - nRoamRescanRssiDiff); - sme_debug("nNeighborScanMinChanTime: %d", - pMac->roam.configParam.neighborRoamConfig. - nNeighborScanMinChanTime); - sme_debug("nNeighborScanMaxChanTime: %d", - pMac->roam.configParam.neighborRoamConfig. - nNeighborScanMaxChanTime); - sme_debug("nMaxNeighborRetries: %d", - pMac->roam.configParam.neighborRoamConfig. - nMaxNeighborRetries); - sme_debug("nNeighborResultsRefreshPeriod: %d", - pMac->roam.configParam.neighborRoamConfig. - nNeighborResultsRefreshPeriod); - sme_debug("nEmptyScanRefreshPeriod: %d", - pMac->roam.configParam.neighborRoamConfig. - nEmptyScanRefreshPeriod); - { - int i; - - sme_debug("Num of Channels in CFG Channel List: %d", - pMac->roam.configParam.neighborRoamConfig. - neighborScanChanList.numChannels); - for (i = 0; - i < - pMac->roam.configParam.neighborRoamConfig. - neighborScanChanList.numChannels; i++) { - sme_debug("%d ", - pMac->roam.configParam. - neighborRoamConfig.neighborScanChanList. - channelList[i]); - } - } - sme_debug("nRoamBmissFirstBcnt: %d", - pMac->roam.configParam.neighborRoamConfig. - nRoamBmissFirstBcnt); - sme_debug("nRoamBmissFinalBcnt: %d", - pMac->roam.configParam.neighborRoamConfig. - nRoamBmissFinalBcnt); - sme_debug("nRoamBeaconRssiWeight: %d", - pMac->roam.configParam.neighborRoamConfig. - nRoamBeaconRssiWeight); - sme_debug("full_scan_period: %u", - pMac->roam.configParam.neighborRoamConfig. - full_roam_scan_period); + pMac->roam.configParam.addTSWhenACMIsOff = pParam->addTSWhenACMIsOff; pMac->scan.fEnableBypass11d = pParam->fEnableBypass11d; @@ -3098,6 +3143,7 @@ QDF_STATUS csr_change_default_config_param(tpAniSirGlobal pMac, pMac->roam.configParam.fScanTwice = pParam->fScanTwice; pMac->scan.fFirstScanOnly2GChnl = pParam->fFirstScanOnly2GChnl; pMac->scan.max_scan_count = pParam->max_scan_count; + /* This parameter is not available in cfg and not passed from * upper layers. Instead it is initialized here This parametere * is used in concurrency to determine if there are concurrent @@ -3158,6 +3204,22 @@ QDF_STATUS csr_change_default_config_param(tpAniSirGlobal pMac, #ifdef WLAN_FEATURE_ROAM_OFFLOAD pMac->roam.configParam.isRoamOffloadEnabled = pParam->isRoamOffloadEnabled; + pMac->roam.configParam.roam_triggers = + pParam->roam_triggers; + pMac->roam.configParam.enable_disconnect_roam_offload = + pParam->enable_disconnect_roam_offload; + pMac->roam.configParam.enable_idle_roam = + pParam->enable_idle_roam; + pMac->roam.configParam.idle_roam_rssi_delta = + pParam->idle_roam_rssi_delta; + pMac->roam.configParam.idle_roam_inactive_time = + pParam->idle_roam_inactive_time; + pMac->roam.configParam.idle_data_packet_count = + pParam->idle_data_packet_count; + pMac->roam.configParam.idle_roam_band = + pParam->idle_roam_band; + pMac->roam.configParam.idle_roam_min_rssi = + pParam->idle_roam_min_rssi; #endif pMac->roam.configParam.obssEnabled = pParam->obssEnabled; pMac->roam.configParam.vendor_vht_sap = @@ -3367,12 +3429,17 @@ QDF_STATUS csr_change_default_config_param(tpAniSirGlobal pMac, sizeof(struct sir_score_config)); pMac->roam.configParam.btm_offload_config = pParam->btm_offload_config; + pMac->roam.configParam.pmkid_modes = pParam->pmkid_modes; pMac->roam.configParam.btm_solicited_timeout = pParam->btm_solicited_timeout; pMac->roam.configParam.btm_max_attempt_cnt = pParam->btm_max_attempt_cnt; pMac->roam.configParam.btm_sticky_time = pParam->btm_sticky_time; + pMac->roam.configParam.btm_query_bitmask = + pParam->btm_query_bitmask; + pMac->roam.configParam.btm_trig_min_candidate_score = + pParam->btm_trig_min_candidate_score; pMac->roam.configParam.btm_validity_timer = pParam->btm_validity_timer; @@ -3384,10 +3451,37 @@ QDF_STATUS csr_change_default_config_param(tpAniSirGlobal pMac, pParam->bss_load_threshold; pMac->roam.configParam.bss_load_sample_time = pParam->bss_load_sample_time; - + pMac->roam.configParam.bss_load_trigger_rssi_threshold_5ghz = + pParam->bss_load_trigger_rssi_threshold_5ghz; + pMac->roam.configParam.bss_load_trigger_rssi_threshold_24ghz = + pParam->bss_load_trigger_rssi_threshold_24ghz; + + pMac->roam.configParam.roam_scan_inactivity_time = + pParam->roam_scan_inactivity_time; + pMac->roam.configParam.roam_inactive_data_packet_count = + pParam->roam_inactive_data_packet_count; + pMac->roam.configParam.roam_scan_period_after_inactivity = + pParam->roam_scan_period_after_inactivity; + pMac->roam.configParam.disconnect_roam_min_rssi = + pParam->disconnect_roam_min_rssi; + pMac->roam.configParam.bmiss_roam_min_rssi = + pParam->bmiss_roam_min_rssi; + pMac->roam.configParam.btm_roam_score_delta = + pParam->btm_roam_score_delta; + pMac->roam.configParam.idle_roam_score_delta = + pParam->idle_roam_score_delta; + pMac->roam.configParam.disable_4way_hs_offload = + pParam->disable_4way_hs_offload; + + csr_update_adaptive_11r_config_param(pMac, pParam); + csr_update_sae_single_pmk_cfg_param(pMac, pParam); csr_update_he_config_param(pMac, pParam); - csr_set_11k_offload_config_param(&pMac->roam.configParam, + csr_update_11k_offload_config_param(&pMac->roam.configParam, pParam); + pMac->roam.configParam.enable_pending_list_req = + pParam->enable_pending_list_req; + pMac->roam.configParam.p2p_disable_roam = + pParam->p2p_disable_roam; } return status; } @@ -3424,6 +3518,33 @@ void csr_get_11k_offload_config_param(struct csr_config *csr_config, max_neighbor_report_req_cap; } +#ifdef WLAN_ADAPTIVE_11R +static void +csr_get_adaptive_11r_config(tpAniSirGlobal mac, tCsrConfigParam *param) +{ + param->enable_adaptive_11r = mac->roam.configParam.enable_adaptive_11r; +} +#else +static inline void +csr_get_adaptive_11r_config(tpAniSirGlobal mac, tCsrConfigParam *param) +{ +} +#endif + +#if defined(WLAN_SAE_SINGLE_PMK) && defined(WLAN_FEATURE_ROAM_OFFLOAD) +static void +csr_get_sae_single_pmk_config(tpAniSirGlobal mac, tCsrConfigParam *param) +{ + param->sae_single_pmk_feature_enabled = + mac->roam.configParam.sae_single_pmk_feature_enabled; +} +#else +static inline void +csr_get_sae_single_pmk_config(tpAniSirGlobal mac, tCsrConfigParam *param) +{ +} +#endif + QDF_STATUS csr_get_config_param(tpAniSirGlobal pMac, tCsrConfigParam *pParam) { int i; @@ -3513,15 +3634,6 @@ QDF_STATUS csr_get_config_param(tpAniSirGlobal pMac, tCsrConfigParam *pParam) qdf_mem_copy(&pParam->neighborRoamConfig, &cfg_params->neighborRoamConfig, sizeof(tCsrNeighborRoamConfigParams)); - sme_debug("Num of Channels in CFG Channel List: %d", - cfg_params->neighborRoamConfig. - neighborScanChanList.numChannels); - for (i = 0; i < cfg_params->neighborRoamConfig. - neighborScanChanList.numChannels; i++) { - sme_debug("%d ", - cfg_params->neighborRoamConfig. - neighborScanChanList.channelList[i]); - } #ifdef FEATURE_WLAN_MCC_TO_SCC_SWITCH pParam->cc_switch_mode = cfg_params->cc_switch_mode; @@ -3547,6 +3659,15 @@ QDF_STATUS csr_get_config_param(tpAniSirGlobal pMac, tCsrConfigParam *pParam) pParam->initial_scan_no_dfs_chnl = cfg_params->initial_scan_no_dfs_chnl; #ifdef WLAN_FEATURE_ROAM_OFFLOAD pParam->isRoamOffloadEnabled = cfg_params->isRoamOffloadEnabled; + pParam->roam_triggers = cfg_params->roam_triggers; + pParam->enable_disconnect_roam_offload = + cfg_params->enable_disconnect_roam_offload; + pParam->enable_idle_roam = cfg_params->enable_idle_roam; + pParam->idle_roam_rssi_delta = cfg_params->idle_roam_rssi_delta; + pParam->idle_roam_inactive_time = cfg_params->idle_roam_inactive_time; + pParam->idle_data_packet_count = cfg_params->idle_data_packet_count; + pParam->idle_roam_band = cfg_params->idle_roam_band; + pParam->idle_roam_min_rssi = cfg_params->idle_roam_min_rssi; #endif pParam->enable_dot11p = pMac->enable_dot11p; csr_set_channels(pMac, pParam); @@ -3702,11 +3823,16 @@ QDF_STATUS csr_get_config_param(tpAniSirGlobal pMac, tCsrConfigParam *pParam) &pMac->roam.configParam.bss_score_params, sizeof(struct sir_score_config)); pParam->btm_offload_config = pMac->roam.configParam.btm_offload_config; + pParam->pmkid_modes = pMac->roam.configParam.pmkid_modes; pParam->btm_solicited_timeout = pMac->roam.configParam.btm_solicited_timeout; pParam->btm_max_attempt_cnt = pMac->roam.configParam.btm_max_attempt_cnt; pParam->btm_sticky_time = pMac->roam.configParam.btm_sticky_time; + pParam->btm_query_bitmask = + pMac->roam.configParam.btm_query_bitmask; + pParam->btm_trig_min_candidate_score = + pMac->roam.configParam.btm_trig_min_candidate_score; pParam->mbo_thresholds.mbo_candidate_rssi_thres = pMac->roam.configParam.mbo_thresholds. @@ -3731,6 +3857,30 @@ QDF_STATUS csr_get_config_param(tpAniSirGlobal pMac, tCsrConfigParam *pParam) pMac->roam.configParam.bss_load_threshold; pParam->bss_load_sample_time = pMac->roam.configParam.bss_load_sample_time; + pParam->bss_load_trigger_rssi_threshold_5ghz = + pMac->roam.configParam.bss_load_trigger_rssi_threshold_5ghz; + pParam->bss_load_trigger_rssi_threshold_24ghz = + pMac->roam.configParam.bss_load_trigger_rssi_threshold_24ghz; + + pParam->roam_scan_inactivity_time = + pMac->roam.configParam.roam_scan_inactivity_time; + pParam->roam_inactive_data_packet_count = + pMac->roam.configParam.roam_inactive_data_packet_count; + pParam->roam_scan_period_after_inactivity = + pMac->roam.configParam.roam_scan_period_after_inactivity; + pParam->disconnect_roam_min_rssi = + pMac->roam.configParam.disconnect_roam_min_rssi; + pParam->bmiss_roam_min_rssi = + pMac->roam.configParam.bmiss_roam_min_rssi; + pParam->btm_roam_score_delta = + pMac->roam.configParam.btm_roam_score_delta; + pParam->idle_roam_score_delta = + pMac->roam.configParam.idle_roam_score_delta; + pParam->disable_4way_hs_offload = + pMac->roam.configParam.disable_4way_hs_offload; + + csr_get_adaptive_11r_config(pMac, pParam); + csr_get_sae_single_pmk_config(pMac, pParam); csr_get_he_config_param(pParam, pMac); csr_get_11k_offload_config_param(&pMac->roam.configParam, pParam); @@ -3742,6 +3892,9 @@ QDF_STATUS csr_get_config_param(tpAniSirGlobal pMac, tCsrConfigParam *pParam) pMac->roam.configParam.wlm_latency_flags[i]; } + pParam->enable_pending_list_req = + pMac->roam.configParam.enable_pending_list_req; + pParam->p2p_disable_roam = pMac->roam.configParam.p2p_disable_roam; return QDF_STATUS_SUCCESS; } @@ -4396,24 +4549,23 @@ static void csr_dump_connection_stats(tpAniSirGlobal mac_ctx, diag_enc_type_from_csr_type(conn_profile->EncryptionType); conn_stats.result_code = (u2 == eCSR_ROAM_RESULT_ASSOCIATED) ? 1 : 0; conn_stats.reason_code = 0; - sme_debug("+---------CONNECTION INFO START------------+"); - sme_debug("connection stats for session-id: %d", session->sessionId); - sme_debug("ssid: %.*s", conn_stats.ssid_len, conn_stats.ssid); - sme_debug("bssid: %pM", conn_stats.bssid); - sme_debug("rssi: %d dBm", conn_stats.rssi); - sme_debug("channel: %d", conn_stats.operating_channel); - sme_debug("dot11Mode: %s", - csr_get_dot11_mode_str(conn_stats.dot11mode)); - sme_debug("channel bw: %s", - csr_get_ch_width_str(conn_stats.chnl_bw)); - sme_debug("Qos enable: %d", conn_stats.qos_capability); - sme_debug("Auth-type: %s", - csr_get_auth_type_str(conn_stats.auth_type)); - sme_debug("Encry-type: %s", - csr_get_encr_type_str(conn_stats.encryption_type)); - sme_debug("is associated?: %s", - (conn_stats.result_code ? "yes" : "no")); - sme_debug("+---------CONNECTION INFO END------------+"); + sme_nofl_debug("+---------CONNECTION INFO START------------+"); + sme_nofl_debug("VDEV-ID: %d self_mac:%pM", session->sessionId, + session->selfMacAddr.bytes); + sme_nofl_debug("ssid: %.*s bssid: %pM RSSI: %d dBm", + conn_stats.ssid_len, conn_stats.ssid, + conn_stats.bssid, conn_stats.rssi); + sme_nofl_debug("Channel : %d channel_bw: %s dot11Mode: %s", + conn_stats.operating_channel, + csr_get_ch_width_str(conn_stats.chnl_bw), + csr_get_dot11_mode_str(conn_stats.dot11mode)); + sme_nofl_debug("AKM: %s Encry-type: %s", + csr_get_auth_type_str(conn_profile->AuthType), + csr_get_encr_type_str(conn_stats.encryption_type)); + sme_nofl_debug("Qos enable: %d | Associated: %s", + conn_stats.qos_capability, + (conn_stats.result_code ? "yes" : "no")); + sme_nofl_debug("+---------CONNECTION INFO END------------+"); WLAN_HOST_DIAG_EVENT_REPORT(&conn_stats, EVENT_WLAN_CONN_STATS_V2); } @@ -4530,9 +4682,8 @@ QDF_STATUS csr_roam_call_callback(tpAniSirGlobal pMac, uint32_t sessionId, * to 0 if unknown. eSIR_BEACON_MISSED reason code is * not recognizable so that we set to 0 instead. */ - roam_info->reasonCode = - (roam_info->reasonCode == eSIR_BEACON_MISSED) ? - 0 : roam_info->reasonCode; + if (roam_info->reasonCode == eSIR_MAC_BEACON_MISSED) + roam_info->reasonCode = 0; } status = pSession->callback(pSession->pContext, roam_info, roamId, u1, u2); @@ -4687,9 +4838,9 @@ QDF_STATUS csr_roam_issue_disassociate(tpAniSirGlobal pMac, uint32_t sessionId, sizeof(struct qdf_mac_addr)); } - sme_debug("CSR Attempting to Disassociate Bssid=" MAC_ADDRESS_STR - " subState: %s reason: %d", MAC_ADDR_ARRAY(bssId.bytes), - mac_trace_getcsr_roam_sub_state(NewSubstate), reasonCode); + sme_debug("Disassociate Bssid " MAC_ADDRESS_STR " subState: %s reason: %d", + MAC_ADDR_ARRAY(bssId.bytes), + mac_trace_getcsr_roam_sub_state(NewSubstate), reasonCode); csr_roam_substate_change(pMac, NewSubstate, sessionId); @@ -4844,7 +4995,7 @@ QDF_STATUS csr_roam_issue_deauth(tpAniSirGlobal pMac, uint32_t sessionId, qdf_mem_copy(bssId.bytes, pSession->pConnectBssDesc->bssId, sizeof(struct qdf_mac_addr)); } - sme_debug("CSR Attempting to Deauth Bssid= " MAC_ADDRESS_STR, + sme_debug("Deauth to Bssid " MAC_ADDRESS_STR, MAC_ADDR_ARRAY(bssId.bytes)); csr_roam_substate_change(pMac, NewSubstate, sessionId); @@ -5001,6 +5152,7 @@ QDF_STATUS csr_roam_prepare_bss_config(tpAniSirGlobal pMac, pBssConfig->authType = eSIR_AUTO_SWITCH; break; case eCSR_AUTH_TYPE_SAE: + case eCSR_AUTH_TYPE_FT_SAE: pBssConfig->authType = eSIR_AUTH_TYPE_SAE; break; } @@ -5145,6 +5297,7 @@ QDF_STATUS csr_roam_prepare_bss_config_from_profile( pBssConfig->authType = eSIR_AUTO_SWITCH; break; case eCSR_AUTH_TYPE_SAE: + case eCSR_AUTH_TYPE_FT_SAE: pBssConfig->authType = eSIR_AUTH_TYPE_SAE; break; } @@ -5822,6 +5975,74 @@ QDF_STATUS csr_roam_set_bss_config_cfg(tpAniSirGlobal pMac, uint32_t sessionId, return QDF_STATUS_SUCCESS; } +/** + * csr_check_for_hidden_ssid_match() - Check if the current connected SSID + * is hidden ssid and if it matches with the roamed AP ssid. + * @mac: Global mac context pointer + * @session: csr session pointer + * @roamed_bss_desc: pointer to bss descriptor of roamed bss + * @roamed_bss_ies: Roamed AP beacon/probe IEs pointer + * + * Return: True if the SSID is hidden and matches with roamed SSID else false + */ +static bool +csr_check_for_hidden_ssid_match(tpAniSirGlobal mac, + struct csr_roam_session *session, + tSirBssDescription *roamed_bss_desc, + tDot11fBeaconIEs *roamed_bss_ies) +{ + QDF_STATUS status; + bool is_null_ssid_match = false; + tDot11fBeaconIEs *connected_profile_ies = NULL; + + if (!session || !roamed_bss_ies) + return false; + + status = csr_get_parsed_bss_description_ies(mac, + session->pConnectBssDesc, + &connected_profile_ies); + if (QDF_IS_STATUS_ERROR(status)) { + sme_err("Unable to get IES"); + goto error; + } + + if (!csr_is_nullssid(connected_profile_ies->SSID.ssid, + connected_profile_ies->SSID.num_ssid)) + goto error; + + /* + * After roam synch indication is received, the driver compares + * the SSID of the current AP and SSID of the roamed AP. If + * there is a mismatch, driver issues disassociate to current + * connected AP. This causes data path queues to be stopped and + * M2 to the roamed AP from userspace will fail if EAPOL is + * offloaded to userspace. The SSID of the current AP is + * parsed from the beacon IEs stored in the connected bss + * description. In hidden ssid case the SSID IE has 0 length + * and the host receives unicast probe with SSID of the + * AP in the roam synch indication. So SSID mismatch happens + * and validation fails. So fetch if the connected bss + * description has hidden ssid, fill the ssid from the + * csr_session connected_profile structure which will + * have the SSID. + */ + if (!roamed_bss_ies->SSID.present) + goto error; + + if (roamed_bss_ies->SSID.num_ssid != + session->connectedProfile.SSID.length) + goto error; + + is_null_ssid_match = !qdf_mem_cmp(session->connectedProfile.SSID.ssId, + roamed_bss_ies->SSID.ssid, + roamed_bss_ies->SSID.num_ssid); +error: + if (connected_profile_ies) + qdf_mem_free(connected_profile_ies); + + return is_null_ssid_match; +} + static QDF_STATUS csr_roam_stop_network(tpAniSirGlobal mac, uint32_t sessionId, struct csr_roam_profile *roam_profile, @@ -5831,6 +6052,7 @@ QDF_STATUS csr_roam_stop_network(tpAniSirGlobal mac, uint32_t sessionId, QDF_STATUS status; struct bss_config_param *pBssConfig; struct csr_roam_session *pSession = CSR_GET_SESSION(mac, sessionId); + bool ssid_match; if (!pSession) { sme_err("session %d not found", sessionId); @@ -5872,10 +6094,16 @@ QDF_STATUS csr_roam_stop_network(tpAniSirGlobal mac, uint32_t sessionId, * (roaming to a new SSID)... * Not worry about WDS connection for now */ + ssid_match = + csr_check_for_hidden_ssid_match(mac, pSession, + pBssDesc, pIes); + if (!ssid_match) + ssid_match = csr_is_ssid_equal( + mac, pSession->pConnectBssDesc, + pBssDesc, pIes); + if (pBssDesc && - (csr_is_ibss_bss_desc(pBssDesc) || - !csr_is_ssid_equal(mac, pSession->pConnectBssDesc, - pBssDesc, pIes))) + (csr_is_ibss_bss_desc(pBssDesc) || !ssid_match)) status = csr_roam_issue_disassociate(mac, sessionId, substate, false); else if (pBssDesc) @@ -6037,12 +6265,16 @@ QDF_STATUS csr_roam_should_roam(tpAniSirGlobal pMac, uint32_t sessionId, tSirBssDescription *pBssDesc, uint32_t roamId) { QDF_STATUS status = QDF_STATUS_SUCCESS; - struct csr_roam_info roamInfo; + struct csr_roam_info *roam_info; - qdf_mem_zero(&roamInfo, sizeof(struct csr_roam_info)); - roamInfo.pBssDesc = pBssDesc; - status = csr_roam_call_callback(pMac, sessionId, &roamInfo, roamId, - eCSR_ROAM_SHOULD_ROAM, eCSR_ROAM_RESULT_NONE); + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return QDF_STATUS_E_NOMEM; + roam_info->pBssDesc = pBssDesc; + status = csr_roam_call_callback(pMac, sessionId, roam_info, roamId, + eCSR_ROAM_SHOULD_ROAM, + eCSR_ROAM_RESULT_NONE); + qdf_mem_free(roam_info); return status; } @@ -6074,6 +6306,7 @@ static void csr_roam_assign_default_param(tpAniSirGlobal pMac, break; case eCSR_AUTH_TYPE_SAE: + case eCSR_AUTH_TYPE_FT_SAE: pCommand->u.roamCmd.roamProfile.negotiatedAuthType = eCSR_AUTH_TYPE_SAE; break; @@ -6095,7 +6328,7 @@ static void csr_roam_assign_default_param(tpAniSirGlobal pMac, * @roam_bss_entry: The next BSS to join * @csr_result_info: Result of join * @csr_scan_result: Global scan result - * @session_id: SME Session ID + * @vdev_id: SME Session ID * @roam_id: Roaming ID * @roam_state: Current roaming state * @bss_list: BSS List @@ -6105,14 +6338,31 @@ static void csr_roam_assign_default_param(tpAniSirGlobal pMac, static bool csr_roam_select_bss(tpAniSirGlobal mac_ctx, tListElem **roam_bss_entry, tCsrScanResultInfo **csr_result_info, struct tag_csrscan_result **csr_scan_result, - uint32_t session_id, uint32_t roam_id, + uint32_t vdev_id, uint32_t roam_id, enum csr_join_state *roam_state, struct scan_result_list *bss_list) { uint8_t conc_channel = 0; + uint32_t temp_vdev_id; bool status = false; struct tag_csrscan_result *scan_result = NULL; tCsrScanResultInfo *result = NULL; + enum QDF_OPMODE op_mode; + struct wlan_objmgr_vdev *vdev; + enum policy_mgr_con_mode mode; + uint8_t chan_id; + QDF_STATUS qdf_status; + + vdev = wlan_objmgr_get_vdev_by_id_from_pdev(mac_ctx->pdev, + vdev_id, + WLAN_LEGACY_SME_ID); + if (!vdev) { + sme_err("Vdev ref error"); + return true; + } + op_mode = wlan_vdev_mlme_get_opmode(vdev); + + wlan_objmgr_vdev_release_ref(vdev, WLAN_LEGACY_SME_ID); while (*roam_bss_entry) { scan_result = GET_BASE_ADDR(*roam_bss_entry, struct @@ -6124,6 +6374,41 @@ static bool csr_roam_select_bss(tpAniSirGlobal mac_ctx, * sessions exempted */ result = &scan_result->Result; + /* + * Ignore the BSS if any other vdev is already connected + * to it. + */ + qdf_status = csr_roam_get_session_id_from_bssid(mac_ctx, + (struct qdf_mac_addr *) + &result->BssDescriptor.bssId, &temp_vdev_id); + if (QDF_IS_STATUS_SUCCESS(qdf_status)) { + sme_info("vdev_id %d already connected to %pM. select next bss for vdev_id %d", + temp_vdev_id, result->BssDescriptor.bssId, + vdev_id); + *roam_state = eCsrStopRoamingDueToConcurrency; + status = true; + *roam_bss_entry = csr_ll_next(&bss_list->List, + *roam_bss_entry, + LL_ACCESS_LOCK); + continue; + } + + chan_id = result->BssDescriptor.channelId; + mode = policy_mgr_convert_device_mode_to_qdf_type(op_mode); + /* If concurrency is not allowed select next bss */ + if (!policy_mgr_is_concurrency_allowed(mac_ctx->psoc, + mode, + chan_id, + HW_MODE_20_MHZ)) { + sme_err("Concurrency not allowed for this channel %d bssid %pM, selecting next", + chan_id, result->BssDescriptor.bssId); + *roam_state = eCsrStopRoamingDueToConcurrency; + status = true; + *roam_bss_entry = csr_ll_next(&bss_list->List, + *roam_bss_entry, + LL_ACCESS_LOCK); + continue; + } /* * check if channel is allowed for current hw mode, if not fetch @@ -6143,7 +6428,7 @@ static bool csr_roam_select_bss(tpAniSirGlobal mac_ctx, } if (policy_mgr_concurrent_open_sessions_running(mac_ctx->psoc) && !csr_is_valid_mc_concurrent_session(mac_ctx, - session_id, &result->BssDescriptor)) { + vdev_id, &result->BssDescriptor)) { conc_channel = csr_get_concurrent_operation_channel( mac_ctx); sme_debug("csr Conc Channel: %d", conc_channel); @@ -6162,7 +6447,7 @@ static bool csr_roam_select_bss(tpAniSirGlobal mac_ctx, /* Ok to roam this */ if (!conc_channel && QDF_IS_STATUS_SUCCESS(csr_roam_should_roam(mac_ctx, - session_id, &result->BssDescriptor, roam_id))) { + vdev_id, &result->BssDescriptor, roam_id))) { status = false; break; } @@ -6581,7 +6866,6 @@ QDF_STATUS csr_process_ft_reassoc_roam_command(tpAniSirGlobal pMac, * csr_roam_trigger_reassociate() - Helper function to trigger reassociate * @mac_ctx: pointer to mac context * @cmd: sme command - * @roam_info: Roaming infor structure * @session_ptr: session pointer * @session_id: session id * @@ -6589,13 +6873,18 @@ QDF_STATUS csr_process_ft_reassoc_roam_command(tpAniSirGlobal pMac, * * Return: QDF_STATUS for success or failure. */ -static QDF_STATUS csr_roam_trigger_reassociate( -tpAniSirGlobal mac_ctx, tSmeCmd *cmd, struct csr_roam_info *roam_info, - struct csr_roam_session *session_ptr, - uint32_t session_id) +static QDF_STATUS +csr_roam_trigger_reassociate(tpAniSirGlobal mac_ctx, tSmeCmd *cmd, + struct csr_roam_session *session_ptr, + uint32_t session_id) { tDot11fBeaconIEs *pIes = NULL; QDF_STATUS status = QDF_STATUS_SUCCESS; + struct csr_roam_info *roam_info; + + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return QDF_STATUS_E_NOMEM; if (session_ptr->pConnectBssDesc) { status = csr_get_parsed_bss_description_ies(mac_ctx, @@ -6638,6 +6927,7 @@ tpAniSirGlobal mac_ctx, tSmeCmd *cmd, struct csr_roam_info *roam_info, sme_err("reassoc to same AP failed as connected BSS is NULL"); status = QDF_STATUS_E_FAILURE; } + qdf_mem_free(roam_info); return status; } @@ -6678,13 +6968,65 @@ bool csr_allow_concurrent_sta_connections(tpAniSirGlobal mac, return false; } +#ifdef QCA_SUPPORT_CP_STATS +static void csr_get_peer_rssi_cb(struct stats_event *ev, void *cookie) +{ + tpAniSirGlobal mac = (tpAniSirGlobal)cookie; + + if (!mac) + return; + if (!ev->peer_stats) { + sme_debug("%s no peer stats\n", __func__); + return; + } + mac->peer_rssi = ev->peer_stats->peer_rssi; + mac->peer_txrate = ev->peer_stats->tx_rate; + mac->peer_rxrate = ev->peer_stats->rx_rate; +} + +static void csr_get_peer_rssi(tpAniSirGlobal mac, uint32_t session_id, + struct qdf_mac_addr peer_mac) +{ + struct wlan_objmgr_vdev *vdev; + struct request_info info = {0}; + QDF_STATUS status; + + vdev = wlan_objmgr_get_vdev_by_id_from_psoc( + mac->psoc, + session_id, + WLAN_LEGACY_SME_ID); + if (vdev) { + info.cookie = mac; + info.u.get_peer_rssi_cb = csr_get_peer_rssi_cb; + info.vdev_id = wlan_vdev_get_id(vdev); + info.pdev_id = wlan_objmgr_pdev_get_pdev_id( + wlan_vdev_get_pdev(vdev)); + qdf_mem_copy(info.peer_mac_addr, &peer_mac, QDF_MAC_ADDR_SIZE); + status = ucfg_mc_cp_stats_send_stats_request( + vdev, + TYPE_PEER_STATS, + &info); + + sme_debug("peer_mac" QDF_MAC_ADDR_STR, + QDF_MAC_ADDR_ARRAY(peer_mac.bytes)); + if (QDF_IS_STATUS_ERROR(status)) + sme_err("stats req failed: %d", status); + wlan_objmgr_vdev_release_ref(vdev, WLAN_LEGACY_SME_ID); + } +} +#else +static void csr_get_peer_rssi(tpAniSirGlobal mac, uint32_t session_id, + struct qdf_mac_addr peer_mac) +{ +} +#endif QDF_STATUS csr_roam_process_command(tpAniSirGlobal pMac, tSmeCmd *pCommand) { - struct csr_roam_info roamInfo; QDF_STATUS lock_status, status = QDF_STATUS_SUCCESS; uint32_t sessionId = pCommand->sessionId; struct csr_roam_session *pSession = CSR_GET_SESSION(pMac, sessionId); + struct qdf_mac_addr peer_mac; if (!pSession) { sme_err("session %d not found", sessionId); @@ -6742,8 +7084,8 @@ QDF_STATUS csr_roam_process_command(tpAniSirGlobal pMac, tSmeCmd *pCommand) break; case eCsrHddIssuedReassocToSameAP: case eCsrSmeIssuedReassocToSameAP: - status = csr_roam_trigger_reassociate(pMac, pCommand, &roamInfo, - pSession, sessionId); + status = csr_roam_trigger_reassociate(pMac, pCommand, + pSession, sessionId); break; case eCsrCapsChange: sme_err("received eCsrCapsChange "); @@ -6772,6 +7114,11 @@ QDF_STATUS csr_roam_process_command(tpAniSirGlobal pMac, tSmeCmd *pCommand) sessionId); sme_debug("Disassociate issued with reason: %d", pCommand->u.roamCmd.reason); + + qdf_mem_copy(&peer_mac, &pCommand->u.roamCmd.peerMac, + QDF_MAC_ADDR_SIZE); + csr_get_peer_rssi(pMac, sessionId, peer_mac); + status = csr_send_mb_disassoc_req_msg(pMac, sessionId, pCommand->u.roamCmd.peerMac, pCommand->u.roamCmd.reason); @@ -6782,6 +7129,14 @@ QDF_STATUS csr_roam_process_command(tpAniSirGlobal pMac, tSmeCmd *pCommand) sessionId); csr_roam_substate_change(pMac, eCSR_ROAM_SUBSTATE_DEAUTH_REQ, sessionId); + + sme_debug("Deauth issued with reason: %d", + pCommand->u.roamCmd.reason); + + qdf_mem_copy(&peer_mac, &pCommand->u.roamCmd.peerMac, + QDF_MAC_ADDR_SIZE); + csr_get_peer_rssi(pMac, sessionId, peer_mac); + status = csr_send_mb_deauth_req_msg(pMac, sessionId, pCommand->u.roamCmd.peerMac, pCommand->u.roamCmd.reason); @@ -6944,13 +7299,15 @@ static QDF_STATUS csr_roam_save_params(tpAniSirGlobal mac_ctx, uint8_t *pIeBuf; if ((eCSR_AUTH_TYPE_RSN == auth_type) || - (eCSR_AUTH_TYPE_FT_RSN == auth_type) || - (eCSR_AUTH_TYPE_FT_RSN_PSK == auth_type) || + (eCSR_AUTH_TYPE_FT_RSN == auth_type) || + (eCSR_AUTH_TYPE_FT_RSN_PSK == auth_type) || + (eCSR_AUTH_TYPE_FT_SAE == auth_type) || + (eCSR_AUTH_TYPE_FT_SUITEB_EAP_SHA384 == auth_type) || #if defined WLAN_FEATURE_11W - (eCSR_AUTH_TYPE_RSN_PSK_SHA256 == auth_type) || - (eCSR_AUTH_TYPE_RSN_8021X_SHA256 == auth_type) || + (eCSR_AUTH_TYPE_RSN_PSK_SHA256 == auth_type) || + (eCSR_AUTH_TYPE_RSN_8021X_SHA256 == auth_type) || #endif - (eCSR_AUTH_TYPE_RSN_PSK == auth_type)) { + (eCSR_AUTH_TYPE_RSN_PSK == auth_type)) { if (ie_local->RSN.present) { tDot11fIERSN *rsnie = &ie_local->RSN; /* @@ -7127,6 +7484,8 @@ static QDF_STATUS csr_roam_save_security_rsp_ie(tpAniSirGlobal pMac, (eCSR_AUTH_TYPE_RSN_PSK == authType) || (eCSR_AUTH_TYPE_FT_RSN == authType) || (eCSR_AUTH_TYPE_FT_RSN_PSK == authType) + || (eCSR_AUTH_TYPE_FT_SAE == authType) + || (eCSR_AUTH_TYPE_FT_SUITEB_EAP_SHA384 == authType) #ifdef FEATURE_WLAN_WAPI || (eCSR_AUTH_TYPE_WAPI_WAI_PSK == authType) || (eCSR_AUTH_TYPE_WAPI_WAI_CERTIFICATE == authType) @@ -7340,18 +7699,22 @@ static void csr_roam_process_results_default(tpAniSirGlobal mac_ctx, { uint32_t session_id = cmd->sessionId; struct csr_roam_session *session; - struct csr_roam_info roam_info; + struct csr_roam_info *roam_info; QDF_STATUS status; struct bss_info bss_info; + struct csr_roam_connectedinfo *prev_connect_info = NULL; if (!CSR_IS_SESSION_VALID(mac_ctx, session_id)) { sme_err("Invalid session id %d", session_id); return; } + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return; session = CSR_GET_SESSION(mac_ctx, session_id); - sme_debug("receives no association indication; FILS %d", - session->is_fils_connection); + prev_connect_info = &session->prev_assoc_ap_info; + sme_debug("Assoc ref count: %d", session->bRefAssocStartCnt); if (CSR_IS_INFRASTRUCTURE(&session->connectedProfile)) { @@ -7375,10 +7738,9 @@ static void csr_roam_process_results_default(tpAniSirGlobal mac_ctx, csr_set_default_dot11_mode(mac_ctx); } - qdf_mem_zero(&roam_info, sizeof(struct csr_roam_info)); /* Copy FILS sequence number used to be updated to userspace */ if (session->is_fils_connection) - csr_update_fils_seq_number(session, &roam_info); + csr_update_fils_seq_number(session, roam_info); switch (cmd->u.roamCmd.roamReason) { /* @@ -7392,14 +7754,23 @@ static void csr_roam_process_results_default(tpAniSirGlobal mac_ctx, case eCsrSmeIssuedDisassocForHandoff: csr_roam_state_change(mac_ctx, eCSR_ROAMING_STATE_IDLE, session_id); - roam_info.pBssDesc = cmd->u.roamCmd.pLastRoamBss; - roam_info.pProfile = &cmd->u.roamCmd.roamProfile; - roam_info.statusCode = session->joinFailStatusCode.statusCode; - roam_info.reasonCode = session->joinFailStatusCode.reasonCode; - qdf_mem_copy(&roam_info.bssid, - &session->joinFailStatusCode.bssId, - sizeof(struct qdf_mac_addr)); + roam_info->pBssDesc = cmd->u.roamCmd.pLastRoamBss; + roam_info->pProfile = &cmd->u.roamCmd.roamProfile; + roam_info->statusCode = session->joinFailStatusCode.statusCode; + roam_info->reasonCode = session->joinFailStatusCode.reasonCode; + qdf_mem_copy(&roam_info->bssid, + &session->joinFailStatusCode.bssId, + sizeof(struct qdf_mac_addr)); + if (prev_connect_info->pbFrames) { + roam_info->nAssocReqLength = + prev_connect_info->nAssocReqLength; + roam_info->nAssocRspLength = + prev_connect_info->nAssocRspLength; + roam_info->nBeaconLength = + prev_connect_info->nBeaconLength; + roam_info->pbFrames = prev_connect_info->pbFrames; + } /* * If Join fails while Handoff is in progress, indicate * disassociated event to supplicant to reconnect @@ -7412,14 +7783,16 @@ static void csr_roam_process_results_default(tpAniSirGlobal mac_ctx, session->bRefAssocStartCnt--; if (eCsrJoinFailureDueToConcurrency == res) csr_roam_call_callback(mac_ctx, session_id, - &roam_info, cmd->u.roamCmd.roamId, - eCSR_ROAM_ASSOCIATION_COMPLETION, - eCSR_ROAM_RESULT_ASSOC_FAIL_CON_CHANNEL); + roam_info, + cmd->u.roamCmd.roamId, + eCSR_ROAM_ASSOCIATION_COMPLETION, + eCSR_ROAM_RESULT_ASSOC_FAIL_CON_CHANNEL); else csr_roam_call_callback(mac_ctx, session_id, - &roam_info, cmd->u.roamCmd.roamId, - eCSR_ROAM_ASSOCIATION_COMPLETION, - eCSR_ROAM_RESULT_FAILURE); + roam_info, + cmd->u.roamCmd.roamId, + eCSR_ROAM_ASSOCIATION_COMPLETION, + eCSR_ROAM_RESULT_FAILURE); } else { /* * bRefAssocStartCnt is not incremented when @@ -7428,9 +7801,10 @@ static void csr_roam_process_results_default(tpAniSirGlobal mac_ctx, * else case by sending assoc failure */ csr_roam_call_callback(mac_ctx, session_id, - &roam_info, cmd->u.roamCmd.roamId, - eCSR_ROAM_ASSOCIATION_FAILURE, - eCSR_ROAM_RESULT_FAILURE); + roam_info, + cmd->u.roamCmd.roamId, + eCSR_ROAM_ASSOCIATION_FAILURE, + eCSR_ROAM_RESULT_FAILURE); } sme_debug("roam(reason %d) failed", cmd->u.roamCmd.roamReason); #ifndef WLAN_MDM_CODE_REDUCTION_OPT @@ -7503,28 +7877,29 @@ static void csr_roam_process_results_default(tpAniSirGlobal mac_ctx, break; case eCsrForcedDisassocSta: case eCsrForcedDeauthSta: - roam_info.rssi = mac_ctx->peer_rssi; - roam_info.tx_rate = mac_ctx->peer_txrate; - roam_info.rx_rate = mac_ctx->peer_rxrate; + roam_info->rssi = mac_ctx->peer_rssi; + roam_info->tx_rate = mac_ctx->peer_txrate; + roam_info->rx_rate = mac_ctx->peer_rxrate; csr_roam_state_change(mac_ctx, eCSR_ROAMING_STATE_JOINED, session_id); session = CSR_GET_SESSION(mac_ctx, session_id); if (CSR_IS_SESSION_VALID(mac_ctx, session_id) && CSR_IS_INFRA_AP(&session->connectedProfile)) { - roam_info.u.pConnectedProfile = + roam_info->u.pConnectedProfile = &session->connectedProfile; - qdf_mem_copy(roam_info.peerMac.bytes, - cmd->u.roamCmd.peerMac, - sizeof(tSirMacAddr)); - roam_info.reasonCode = eCSR_ROAM_RESULT_FORCED; + qdf_mem_copy(roam_info->peerMac.bytes, + cmd->u.roamCmd.peerMac, + sizeof(tSirMacAddr)); + roam_info->reasonCode = eCSR_ROAM_RESULT_FORCED; /* Update the MAC reason code */ - roam_info.disassoc_reason = cmd->u.roamCmd.reason; - roam_info.statusCode = eSIR_SME_SUCCESS; + roam_info->disassoc_reason = cmd->u.roamCmd.reason; + roam_info->statusCode = eSIR_SME_SUCCESS; status = csr_roam_call_callback(mac_ctx, session_id, - &roam_info, cmd->u.roamCmd.roamId, - eCSR_ROAM_LOSTLINK, - eCSR_ROAM_RESULT_FORCED); + roam_info, + cmd->u.roamCmd.roamId, + eCSR_ROAM_LOSTLINK, + eCSR_ROAM_RESULT_FORCED); } break; default: @@ -7532,6 +7907,7 @@ static void csr_roam_process_results_default(tpAniSirGlobal mac_ctx, eCSR_ROAMING_STATE_IDLE, session_id); break; } + qdf_mem_free(roam_info); } /** @@ -7549,7 +7925,7 @@ static void csr_roam_process_start_bss_success(tpAniSirGlobal mac_ctx, struct csr_roam_profile *profile = &cmd->u.roamCmd.roamProfile; struct csr_roam_session *session; tSirBssDescription *bss_desc = NULL; - struct csr_roam_info roam_info; + struct csr_roam_info *roam_info; tSirSmeStartBssRsp *start_bss_rsp = NULL; eRoamCmdStatus roam_status; eCsrRoamResult roam_result; @@ -7581,7 +7957,9 @@ static void csr_roam_process_start_bss_success(tpAniSirGlobal mac_ctx, sme_debug("receives start BSS ok indication"); status = QDF_STATUS_E_FAILURE; start_bss_rsp = (tSirSmeStartBssRsp *) context; - qdf_mem_zero(&roam_info, sizeof(struct csr_roam_info)); + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return; if (CSR_IS_IBSS(profile)) session->connectState = eCSR_ASSOC_STATE_TYPE_IBSS_DISCONNECTED; else if (CSR_IS_INFRA_AP(profile)) @@ -7598,9 +7976,9 @@ static void csr_roam_process_start_bss_success(tpAniSirGlobal mac_ctx, session_id); csr_roam_save_ndi_connected_info(mac_ctx, session_id, profile, bss_desc); - roam_info.u.pConnectedProfile = &session->connectedProfile; - qdf_mem_copy(&roam_info.bssid, &bss_desc->bssId, - sizeof(struct qdf_mac_addr)); + roam_info->u.pConnectedProfile = &session->connectedProfile; + qdf_mem_copy(&roam_info->bssid, &bss_desc->bssId, + sizeof(struct qdf_mac_addr)); } else { csr_roam_state_change(mac_ctx, eCSR_ROAMING_STATE_JOINED, session_id); @@ -7608,10 +7986,12 @@ static void csr_roam_process_start_bss_success(tpAniSirGlobal mac_ctx, (csr_get_parsed_bss_description_ies(mac_ctx, bss_desc, &ies_ptr))) { sme_warn("cannot parse IBSS IEs"); - roam_info.pBssDesc = bss_desc; - csr_roam_call_callback(mac_ctx, session_id, &roam_info, - cmd->u.roamCmd.roamId, eCSR_ROAM_IBSS_IND, - eCSR_ROAM_RESULT_IBSS_START_FAILED); + roam_info->pBssDesc = bss_desc; + csr_roam_call_callback(mac_ctx, session_id, roam_info, + cmd->u.roamCmd.roamId, + eCSR_ROAM_IBSS_IND, + eCSR_ROAM_RESULT_IBSS_START_FAILED); + qdf_mem_free(roam_info); return; } } @@ -7623,8 +8003,8 @@ static void csr_roam_process_start_bss_success(tpAniSirGlobal mac_ctx, csr_roam_free_connected_info(mac_ctx, &session->connectedInfo); csr_roam_save_connected_information(mac_ctx, session_id, profile, bss_desc, ies_ptr); - qdf_mem_copy(&roam_info.bssid, &bss_desc->bssId, - sizeof(struct qdf_mac_addr)); + qdf_mem_copy(&roam_info->bssid, &bss_desc->bssId, + sizeof(struct qdf_mac_addr)); /* We are done with the IEs so free it */ qdf_mem_free(ies_ptr); #ifdef FEATURE_WLAN_DIAG_SUPPORT_CSR @@ -7691,7 +8071,7 @@ static void csr_roam_process_start_bss_success(tpAniSirGlobal mac_ctx, profile->negotiatedUCEncryptionType || eCSR_ENCRYPT_TYPE_AES == profile->negotiatedUCEncryptionType)) { - roam_info.fAuthRequired = true; + roam_info->fAuthRequired = true; } } /* @@ -7707,13 +8087,13 @@ static void csr_roam_process_start_bss_success(tpAniSirGlobal mac_ctx, roam_status = eCSR_ROAM_INFRA_IND; roam_result = eCSR_ROAM_RESULT_INFRA_STARTED; } - roam_info.staId = (uint8_t) start_bss_rsp->staId; + roam_info->staId = (uint8_t)start_bss_rsp->staId; if (CSR_IS_NDI(profile)) { csr_roam_update_ndp_return_params(mac_ctx, - eCsrStartBssSuccess, - &roam_status, - &roam_result, - &roam_info); + eCsrStartBssSuccess, + &roam_status, + &roam_result, + roam_info); } /* * Only tell upper layer is we start the BSS because Vista @@ -7721,13 +8101,13 @@ static void csr_roam_process_start_bss_success(tpAniSirGlobal mac_ctx, * start the BSS ourself, handler of eSIR_SME_JOINED_NEW_BSS * will trigger the connection start indication in Vista */ - roam_info.statusCode = session->joinFailStatusCode.statusCode; - roam_info.reasonCode = session->joinFailStatusCode.reasonCode; + roam_info->statusCode = session->joinFailStatusCode.statusCode; + roam_info->reasonCode = session->joinFailStatusCode.reasonCode; /* We start the IBSS (didn't find any matched IBSS out there) */ - roam_info.pBssDesc = bss_desc; + roam_info->pBssDesc = bss_desc; if (bss_desc) - qdf_mem_copy(roam_info.bssid.bytes, bss_desc->bssId, - sizeof(struct qdf_mac_addr)); + qdf_mem_copy(roam_info->bssid.bytes, bss_desc->bssId, + sizeof(struct qdf_mac_addr)); if (!IS_FEATURE_SUPPORTED_BY_FW(SLM_SESSIONIZATION) && (csr_is_concurrent_session_running(mac_ctx))) { mac_ctx->roam.configParam.doBMPSWorkaround = 1; @@ -7739,11 +8119,11 @@ static void csr_roam_process_start_bss_success(tpAniSirGlobal mac_ctx, != QDF_MCC_TO_SCC_SWITCH_DISABLE) csr_roam_copy_ht_profile(dst_profile, src_profile); #endif - csr_roam_call_callback(mac_ctx, session_id, &roam_info, - cmd->u.roamCmd.roamId, - roam_status, roam_result); + csr_roam_call_callback(mac_ctx, session_id, roam_info, + cmd->u.roamCmd.roamId, + roam_status, roam_result); } - + qdf_mem_free(roam_info); } #ifdef WLAN_FEATURE_FILS_SK @@ -7880,7 +8260,7 @@ static void csr_process_fils_join_rsp(tpAniSirGlobal mac_ctx, roam_info->fils_join_rsp->tk_len, roam_info->fils_join_rsp->tk, 0); if (!QDF_IS_STATUS_SUCCESS(status)) { - sme_err("Set context for unicast fail"); + sme_debug("Set context for unicast fail"); goto process_fils_join_rsp_fail; } return; @@ -7929,7 +8309,7 @@ static void csr_roam_process_join_res(tpAniSirGlobal mac_ctx, #endif tCsrRoamConnectedProfile *conn_profile = NULL; tDot11fBeaconIEs *ies_ptr = NULL; - struct csr_roam_info roam_info; + struct csr_roam_info *roam_info; struct ps_global_info *ps_global_info = &mac_ctx->sme.ps_global_info; tSirSmeJoinRsp *join_rsp = (tSirSmeJoinRsp *) context; uint32_t len; @@ -7946,15 +8326,7 @@ static void csr_roam_process_join_res(tpAniSirGlobal mac_ctx, } session = CSR_GET_SESSION(mac_ctx, session_id); - qdf_mem_zero(&roam_info, sizeof(roam_info)); conn_profile = &session->connectedProfile; - if (eCsrReassocSuccess == res) { - roam_info.reassoc = true; - ind_qos = SME_QOS_CSR_REASSOC_COMPLETE; - } else { - roam_info.reassoc = false; - ind_qos = SME_QOS_CSR_ASSOC_COMPLETE; - } sme_debug("receives association indication"); /* always free the memory here */ if (session->pWpaRsnRspIE) { @@ -7973,6 +8345,18 @@ static void csr_roam_process_join_res(tpAniSirGlobal mac_ctx, session->maxRetryCount = 0; csr_roam_stop_join_retry_timer(mac_ctx, session_id); #endif + + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return; + if (eCsrReassocSuccess == res) { + roam_info->reassoc = true; + ind_qos = SME_QOS_CSR_REASSOC_COMPLETE; + } else { + roam_info->reassoc = false; + ind_qos = SME_QOS_CSR_ASSOC_COMPLETE; + } + /* * Reset remain_in_power_active_till_dhcp as * it might have been set by last failed secured connection. @@ -7992,8 +8376,8 @@ static void csr_roam_process_join_res(tpAniSirGlobal mac_ctx, cmd->u.roamCmd.roamReason)) { bss_desc = session->pConnectBssDesc; if (bss_desc) - qdf_mem_copy(&roam_info.bssid, &bss_desc->bssId, - sizeof(struct qdf_mac_addr)); + qdf_mem_copy(&roam_info->bssid, &bss_desc->bssId, + sizeof(struct qdf_mac_addr)); } else { if (cmd->u.roamCmd.pRoamBssEntry) { scan_res = GET_BASE_ADDR(cmd->u.roamCmd.pRoamBssEntry, @@ -8002,20 +8386,21 @@ static void csr_roam_process_join_res(tpAniSirGlobal mac_ctx, bss_desc = &scan_res->Result.BssDescriptor; ies_ptr = (tDot11fBeaconIEs *) (scan_res->Result.pvIes); - qdf_mem_copy(&roam_info.bssid, &bss_desc->bssId, - sizeof(struct qdf_mac_addr)); + qdf_mem_copy(&roam_info->bssid, + &bss_desc->bssId, + sizeof(struct qdf_mac_addr)); } } } if (bss_desc) { - roam_info.staId = STA_INVALID_IDX; + roam_info->staId = STA_INVALID_IDX; csr_roam_save_connected_information(mac_ctx, session_id, profile, bss_desc, ies_ptr); /* Save WPA/RSN IE */ csr_roam_save_security_rsp_ie(mac_ctx, session_id, profile->negotiatedAuthType, bss_desc, ies_ptr); #ifdef FEATURE_WLAN_ESE - roam_info.isESEAssoc = conn_profile->isESEAssoc; + roam_info->isESEAssoc = conn_profile->isESEAssoc; #endif /* @@ -8077,12 +8462,13 @@ static void csr_roam_process_join_res(tpAniSirGlobal mac_ctx, eSIR_TX_RX, 0, 0, NULL, 0); } else if (CSR_IS_AUTH_TYPE_FILS(profile->negotiatedAuthType) && join_rsp->is_fils_connection) { - roam_info.is_fils_connection = true; + roam_info->is_fils_connection = true; csr_process_fils_join_rsp(mac_ctx, profile, session_id, - &roam_info, bss_desc, join_rsp); + roam_info, bss_desc, + join_rsp); } else { /* Need to wait for supplicant authtication */ - roam_info.fAuthRequired = true; + roam_info->fAuthRequired = true; /* * Set the substate to WaitForKey in case * authentiation is needed @@ -8107,7 +8493,7 @@ static void csr_roam_process_join_res(tpAniSirGlobal mac_ctx, CSR_WAIT_FOR_KEY_TIMEOUT_PERIOD; /* Save session_id in case of timeout */ - mac_ctx->roam.WaitForKeyTimerInfo.sessionId = + mac_ctx->roam.WaitForKeyTimerInfo.vdev_id = (uint8_t) session_id; /* * This time should be long enough for the rest @@ -8163,37 +8549,37 @@ static void csr_roam_process_join_res(tpAniSirGlobal mac_ctx, session->connectedInfo.nTspecIeLength = join_rsp->tspecIeLen; #endif - roam_info.nAssocReqLength = + roam_info->nAssocReqLength = join_rsp->assocReqLength; - roam_info.nAssocRspLength = + roam_info->nAssocRspLength = join_rsp->assocRspLength; - roam_info.nBeaconLength = + roam_info->nBeaconLength = join_rsp->beaconLength; - roam_info.pbFrames = + roam_info->pbFrames = session->connectedInfo.pbFrames; } } if (cmd->u.roamCmd.fReassoc) - roam_info.fReassocReq = - roam_info.fReassocRsp = true; + roam_info->fReassocReq = + roam_info->fReassocRsp = true; conn_profile->vht_channel_width = join_rsp->vht_channel_width; session->connectedInfo.staId = - (uint8_t) join_rsp->staId; - roam_info.staId = (uint8_t) join_rsp->staId; - roam_info.timingMeasCap = join_rsp->timingMeasCap; - roam_info.chan_info.nss = join_rsp->nss; - roam_info.chan_info.rate_flags = + (uint8_t)join_rsp->staId; + roam_info->staId = (uint8_t)join_rsp->staId; + roam_info->timingMeasCap = join_rsp->timingMeasCap; + roam_info->chan_info.nss = join_rsp->nss; + roam_info->chan_info.rate_flags = join_rsp->max_rate_flags; - roam_info.chan_info.ch_width = + roam_info->chan_info.ch_width = join_rsp->vht_channel_width; #ifdef FEATURE_WLAN_TDLS - roam_info.tdls_prohibited = join_rsp->tdls_prohibited; - roam_info.tdls_chan_swit_prohibited = + roam_info->tdls_prohibited = join_rsp->tdls_prohibited; + roam_info->tdls_chan_swit_prohibited = join_rsp->tdls_chan_swit_prohibited; sme_debug("tdls:prohibit: %d chan_swit_prohibit: %d", - roam_info.tdls_prohibited, - roam_info.tdls_chan_swit_prohibited); + roam_info->tdls_prohibited, + roam_info->tdls_chan_swit_prohibited); #endif #ifdef FEATURE_WLAN_MCC_TO_SCC_SWITCH src_profile = &join_rsp->HTProfile; @@ -8203,22 +8589,22 @@ static void csr_roam_process_join_res(tpAniSirGlobal mac_ctx, csr_roam_copy_ht_profile(dst_profile, src_profile); #endif - roam_info.vht_caps = join_rsp->vht_caps; - roam_info.ht_caps = join_rsp->ht_caps; - roam_info.hs20vendor_ie = join_rsp->hs20vendor_ie; - roam_info.ht_operation = join_rsp->ht_operation; - roam_info.vht_operation = join_rsp->vht_operation; + roam_info->vht_caps = join_rsp->vht_caps; + roam_info->ht_caps = join_rsp->ht_caps; + roam_info->hs20vendor_ie = join_rsp->hs20vendor_ie; + roam_info->ht_operation = join_rsp->ht_operation; + roam_info->vht_operation = join_rsp->vht_operation; } else { if (cmd->u.roamCmd.fReassoc) { - roam_info.fReassocReq = - roam_info.fReassocRsp = true; - roam_info.nAssocReqLength = + roam_info->fReassocReq = + roam_info->fReassocRsp = true; + roam_info->nAssocReqLength = session->connectedInfo.nAssocReqLength; - roam_info.nAssocRspLength = + roam_info->nAssocRspLength = session->connectedInfo.nAssocRspLength; - roam_info.nBeaconLength = + roam_info->nBeaconLength = session->connectedInfo.nBeaconLength; - roam_info.pbFrames = + roam_info->pbFrames = session->connectedInfo.pbFrames; } } @@ -8231,7 +8617,7 @@ static void csr_roam_process_join_res(tpAniSirGlobal mac_ctx, cmd->u.roamCmd.roamReason) || (eCsrSmeIssuedReassocToSameAP == cmd->u.roamCmd.roamReason)) - roam_info.staId = session->connectedInfo.staId; + roam_info->staId = session->connectedInfo.staId; #ifndef WLAN_MDM_CODE_REDUCTION_OPT /* @@ -8241,10 +8627,10 @@ static void csr_roam_process_join_res(tpAniSirGlobal mac_ctx, sme_qos_csr_event_ind(mac_ctx, (uint8_t) session_id, ind_qos, &assoc_info); #endif - roam_info.pBssDesc = bss_desc; - roam_info.statusCode = + roam_info->pBssDesc = bss_desc; + roam_info->statusCode = session->joinFailStatusCode.statusCode; - roam_info.reasonCode = + roam_info->reasonCode = session->joinFailStatusCode.reasonCode; #ifndef WLAN_MDM_CODE_REDUCTION_OPT acm_mask = sme_qos_get_acm_mask(mac_ctx, bss_desc, NULL); @@ -8264,7 +8650,7 @@ static void csr_roam_process_join_res(tpAniSirGlobal mac_ctx, sme_ps_start_uapsd(MAC_HANDLE(mac_ctx), session_id); } conn_profile->dot11Mode = session->bssParams.uCfgDot11Mode; - roam_info.u.pConnectedProfile = conn_profile; + roam_info->u.pConnectedProfile = conn_profile; if (session->bRefAssocStartCnt > 0) { session->bRefAssocStartCnt--; @@ -8273,10 +8659,10 @@ static void csr_roam_process_join_res(tpAniSirGlobal mac_ctx, (csr_is_concurrent_session_running(mac_ctx))) { mac_ctx->roam.configParam.doBMPSWorkaround = 1; } - csr_roam_call_callback(mac_ctx, session_id, &roam_info, - cmd->u.roamCmd.roamId, - eCSR_ROAM_ASSOCIATION_COMPLETION, - eCSR_ROAM_RESULT_ASSOCIATED); + csr_roam_call_callback(mac_ctx, session_id, roam_info, + cmd->u.roamCmd.roamId, + eCSR_ROAM_ASSOCIATION_COMPLETION, + eCSR_ROAM_RESULT_ASSOCIATED); } qdf_copy_macaddr(&bss_info.bssid, &conn_profile->bssid); @@ -8312,7 +8698,8 @@ static void csr_roam_process_join_res(tpAniSirGlobal mac_ctx, #endif csr_roam_link_up(mac_ctx, conn_profile->bssid); } - sme_free_join_rsp_fils_params(&roam_info); + sme_free_join_rsp_fils_params(roam_info); + qdf_mem_free(roam_info); } /** @@ -8332,7 +8719,7 @@ static bool csr_roam_process_results(tpAniSirGlobal mac_ctx, tSmeCmd *cmd, { bool release_cmd = true; tSirBssDescription *bss_desc = NULL; - struct csr_roam_info roam_info; + struct csr_roam_info *roam_info; uint32_t session_id = cmd->sessionId; struct csr_roam_session *session = CSR_GET_SESSION(mac_ctx, session_id); struct csr_roam_profile *profile = &cmd->u.roamCmd.roamProfile; @@ -8346,7 +8733,11 @@ static bool csr_roam_process_results(tpAniSirGlobal mac_ctx, tSmeCmd *cmd, return false; } - sme_debug("Processing ROAM results..."); + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return false; + + sme_debug("Result %d", res); switch (res) { case eCsrJoinSuccess: case eCsrReassocSuccess: @@ -8365,7 +8756,6 @@ static bool csr_roam_process_results(tpAniSirGlobal mac_ctx, tSmeCmd *cmd, } #endif start_bss_rsp = (tSirSmeStartBssRsp *)context; - qdf_mem_zero(&roam_info, sizeof(roam_info)); roam_status = eCSR_ROAM_IBSS_IND; roam_result = eCSR_ROAM_RESULT_IBSS_STARTED; if (CSR_IS_INFRA_AP(profile)) { @@ -8374,18 +8764,20 @@ static bool csr_roam_process_results(tpAniSirGlobal mac_ctx, tSmeCmd *cmd, } if (CSR_IS_NDI(profile)) { csr_roam_update_ndp_return_params(mac_ctx, - eCsrStartBssFailure, - &roam_status, &roam_result, &roam_info); + eCsrStartBssFailure, + &roam_status, + &roam_result, + roam_info); } if (context) bss_desc = (tSirBssDescription *) context; else bss_desc = NULL; - roam_info.pBssDesc = bss_desc; - csr_roam_call_callback(mac_ctx, session_id, &roam_info, - cmd->u.roamCmd.roamId, roam_status, - roam_result); + roam_info->pBssDesc = bss_desc; + csr_roam_call_callback(mac_ctx, session_id, roam_info, + cmd->u.roamCmd.roamId, roam_status, + roam_result); csr_set_default_dot11_mode(mac_ctx); break; case eCsrSilentlyStopRoaming: @@ -8398,26 +8790,27 @@ static bool csr_roam_process_results(tpAniSirGlobal mac_ctx, tSmeCmd *cmd, session_id); csr_roam_substate_change(mac_ctx, eCSR_ROAM_SUBSTATE_NONE, session_id); - qdf_mem_zero(&roam_info, sizeof(struct csr_roam_info)); - roam_info.pBssDesc = session->pConnectBssDesc; - if (roam_info.pBssDesc) - qdf_mem_copy(&roam_info.bssid, - &roam_info.pBssDesc->bssId, - sizeof(struct qdf_mac_addr)); + qdf_mem_zero(roam_info, sizeof(*roam_info)); + roam_info->pBssDesc = session->pConnectBssDesc; + if (roam_info->pBssDesc) + qdf_mem_copy(&roam_info->bssid, + &roam_info->pBssDesc->bssId, + sizeof(struct qdf_mac_addr)); /* * Since there is no change in the current state, simply pass * back no result otherwise HDD may be mistakenly mark to * disconnected state. */ - csr_roam_call_callback(mac_ctx, session_id, &roam_info, - cmd->u.roamCmd.roamId, - eCSR_ROAM_IBSS_IND, eCSR_ROAM_RESULT_NONE); + csr_roam_call_callback(mac_ctx, session_id, roam_info, + cmd->u.roamCmd.roamId, + eCSR_ROAM_IBSS_IND, + eCSR_ROAM_RESULT_NONE); break; case eCsrSilentlyStopRoamingSaveState: /* We are here because we try to connect to the same AP */ /* No message to PE */ sme_debug("receives silently stop roaming indication"); - qdf_mem_zero(&roam_info, sizeof(roam_info)); + qdf_mem_zero(roam_info, sizeof(*roam_info)); /* to aviod resetting the substate to NONE */ mac_ctx->roam.curState[session_id] = eCSR_ROAMING_STATE_JOINED; @@ -8425,29 +8818,29 @@ static bool csr_roam_process_results(tpAniSirGlobal mac_ctx, tSmeCmd *cmd, * No need to change substate to wai_for_key because there * is no state change */ - roam_info.pBssDesc = session->pConnectBssDesc; - if (roam_info.pBssDesc) - qdf_mem_copy(&roam_info.bssid, - &roam_info.pBssDesc->bssId, - sizeof(struct qdf_mac_addr)); - roam_info.statusCode = session->joinFailStatusCode.statusCode; - roam_info.reasonCode = session->joinFailStatusCode.reasonCode; - roam_info.nBeaconLength = session->connectedInfo.nBeaconLength; - roam_info.nAssocReqLength = + roam_info->pBssDesc = session->pConnectBssDesc; + if (roam_info->pBssDesc) + qdf_mem_copy(&roam_info->bssid, + &roam_info->pBssDesc->bssId, + sizeof(struct qdf_mac_addr)); + roam_info->statusCode = session->joinFailStatusCode.statusCode; + roam_info->reasonCode = session->joinFailStatusCode.reasonCode; + roam_info->nBeaconLength = session->connectedInfo.nBeaconLength; + roam_info->nAssocReqLength = session->connectedInfo.nAssocReqLength; - roam_info.nAssocRspLength = + roam_info->nAssocRspLength = session->connectedInfo.nAssocRspLength; - roam_info.pbFrames = session->connectedInfo.pbFrames; - roam_info.staId = session->connectedInfo.staId; - roam_info.u.pConnectedProfile = &session->connectedProfile; - if (0 == roam_info.staId) + roam_info->pbFrames = session->connectedInfo.pbFrames; + roam_info->staId = session->connectedInfo.staId; + roam_info->u.pConnectedProfile = &session->connectedProfile; + if (0 == roam_info->staId) QDF_ASSERT(0); session->bRefAssocStartCnt--; - csr_roam_call_callback(mac_ctx, session_id, &roam_info, - cmd->u.roamCmd.roamId, - eCSR_ROAM_ASSOCIATION_COMPLETION, - eCSR_ROAM_RESULT_ASSOCIATED); + csr_roam_call_callback(mac_ctx, session_id, roam_info, + cmd->u.roamCmd.roamId, + eCSR_ROAM_ASSOCIATION_COMPLETION, + eCSR_ROAM_RESULT_ASSOCIATED); csr_roam_completion(mac_ctx, session_id, NULL, cmd, eCSR_ROAM_RESULT_ASSOCIATED, true); break; @@ -8463,22 +8856,26 @@ static bool csr_roam_process_results(tpAniSirGlobal mac_ctx, tSmeCmd *cmd, break; case eCsrStopBssSuccess: if (CSR_IS_NDI(profile)) { - qdf_mem_zero(&roam_info, sizeof(roam_info)); + qdf_mem_zero(roam_info, sizeof(*roam_info)); csr_roam_update_ndp_return_params(mac_ctx, res, - &roam_status, &roam_result, &roam_info); - csr_roam_call_callback(mac_ctx, session_id, &roam_info, - cmd->u.roamCmd.roamId, - roam_status, roam_result); + &roam_status, + &roam_result, + roam_info); + csr_roam_call_callback(mac_ctx, session_id, roam_info, + cmd->u.roamCmd.roamId, + roam_status, roam_result); } break; case eCsrStopBssFailure: if (CSR_IS_NDI(profile)) { - qdf_mem_zero(&roam_info, sizeof(roam_info)); + qdf_mem_zero(roam_info, sizeof(*roam_info)); csr_roam_update_ndp_return_params(mac_ctx, res, - &roam_status, &roam_result, &roam_info); - csr_roam_call_callback(mac_ctx, session_id, &roam_info, - cmd->u.roamCmd.roamId, - roam_status, roam_result); + &roam_status, + &roam_result, + roam_info); + csr_roam_call_callback(mac_ctx, session_id, roam_info, + cmd->u.roamCmd.roamId, + roam_status, roam_result); } break; case eCsrJoinFailure: @@ -8488,6 +8885,7 @@ static bool csr_roam_process_results(tpAniSirGlobal mac_ctx, tSmeCmd *cmd, csr_roam_process_results_default(mac_ctx, cmd, context, res); break; } + qdf_mem_free(roam_info); return release_cmd; } @@ -8890,9 +9288,7 @@ QDF_STATUS csr_roam_issue_connect(tpAniSirGlobal pMac, uint32_t sessionId, /* We need to free the BssList when the command is done */ pCommand->u.roamCmd.fReleaseBssList = true; pCommand->u.roamCmd.fUpdateCurRoamProfile = true; - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - FL("CSR PERSONA=%d"), - pCommand->u.roamCmd.roamProfile.csrPersona); + status = csr_queue_sme_command(pMac, pCommand, fImediate); if (!QDF_IS_STATUS_SUCCESS(status)) { sme_err("fail to send message status: %d", status); @@ -9041,9 +9437,9 @@ static void csr_roam_print_candidate_aps(tScanResultHandle results) while (entry) { bss_desc = GET_BASE_ADDR(entry, struct tag_csrscan_result, Link); - sme_debug("BSSID" MAC_ADDRESS_STR "score is %d", - MAC_ADDR_ARRAY(bss_desc->Result.BssDescriptor.bssId), - bss_desc->bss_score); + sme_nofl_debug(QDF_MAC_ADDR_STR " score: %d", + QDF_MAC_ADDR_ARRAY(bss_desc->Result.BssDescriptor.bssId), + bss_desc->bss_score); entry = csr_ll_next(&bss_list->List, entry, LL_ACCESS_NOLOCK); @@ -9084,11 +9480,10 @@ QDF_STATUS csr_roam_connect(tpAniSirGlobal pMac, uint32_t sessionId, pSession->join_bssid_count = 0; pSession->discon_in_progress = false; pSession->is_fils_connection = csr_is_fils_connection(pProfile); - sme_debug( - "called BSSType = %s (%d) authtype = %d encryType = %d", - sme_bss_type_to_string(pProfile->BSSType), - pProfile->BSSType, pProfile->AuthType.authType[0], - pProfile->EncryptionType.encryptionType[0]); + sme_debug("Persona %d authtype %d encryType %d mc_encType %d", + pProfile->csrPersona, pProfile->AuthType.authType[0], + pProfile->EncryptionType.encryptionType[0], + pProfile->mcEncryptionType.encryptionType[0]); csr_roam_cancel_roaming(pMac, sessionId); csr_scan_abort_mac_scan(pMac, sessionId, INVAL_SCAN_ID); csr_roam_remove_duplicate_command(pMac, sessionId, NULL, eCsrHddIssued); @@ -9098,7 +9493,8 @@ QDF_STATUS csr_roam_connect(tpAniSirGlobal pMac, uint32_t sessionId, !csr_is_ssid_in_list(&pSession->connectedProfile.SSID, &pProfile->SSIDs)) csr_roam_issue_disassociate_cmd(pMac, sessionId, - eCSR_DISCONNECT_REASON_UNSPECIFIED); + eCSR_DISCONNECT_REASON_UNSPECIFIED, + eSIR_MAC_UNSPEC_FAILURE_REASON); /* * If roamSession.connectState is disconnecting that mean * disconnect was received with scan for ssid in progress @@ -9166,7 +9562,6 @@ QDF_STATUS csr_roam_connect(tpAniSirGlobal pMac, uint32_t sessionId, goto end; } status = csr_scan_get_result(pMac, pScanFilter, &hBSSList); - sme_debug("csr_scan_get_result Status: %d", status); csr_roam_print_candidate_aps(hBSSList); if (QDF_IS_STATUS_SUCCESS(status)) { /* check if set hw mode needs to be done */ @@ -9243,8 +9638,6 @@ QDF_STATUS csr_roam_connect(tpAniSirGlobal pMac, uint32_t sessionId, sme_err("CSR failed to issue SSID scan cmd with status: 0x%08X", status); fCallCallback = true; - } else { - sme_debug("SSID scan requested"); } } } else { @@ -9425,21 +9818,8 @@ static QDF_STATUS csr_roam_join_last_profile(tpAniSirGlobal pMac, return status; } -QDF_STATUS csr_roam_reconnect(tpAniSirGlobal pMac, uint32_t sessionId) -{ - QDF_STATUS status = QDF_STATUS_E_FAILURE; - - if (csr_is_conn_state_connected(pMac, sessionId)) { - status = csr_roam_issue_disassociate_cmd(pMac, sessionId, - eCSR_DISCONNECT_REASON_UNSPECIFIED); - if (QDF_IS_STATUS_SUCCESS(status)) - status = csr_roam_join_last_profile(pMac, sessionId); - } - return status; -} - -QDF_STATUS csr_roam_connect_to_last_profile(tpAniSirGlobal pMac, - uint32_t sessionId) +QDF_STATUS csr_roam_connect_to_last_profile(tpAniSirGlobal pMac, + uint32_t sessionId) { QDF_STATUS status = QDF_STATUS_E_FAILURE; @@ -9469,6 +9849,8 @@ QDF_STATUS csr_roam_process_disassoc_deauth(tpAniSirGlobal pMac, /* change state to 'Roaming'... */ csr_roam_state_change(pMac, eCSR_ROAMING_STATE_JOINING, sessionId); + mlme_set_discon_reason_n_from_ap(pMac->psoc, pCommand->sessionId, false, + pCommand->u.roamCmd.disconnect_reason); if (csr_is_conn_state_ibss(pMac, sessionId)) { /* If we are in an IBSS, then stop the IBSS... */ status = @@ -9578,7 +9960,8 @@ QDF_STATUS csr_prepare_disconnect_command(tpAniSirGlobal mac, QDF_STATUS csr_roam_issue_disassociate_cmd(tpAniSirGlobal pMac, uint32_t sessionId, - eCsrRoamDisconnectReason reason) + eCsrRoamDisconnectReason reason, + tSirMacReasonCodes mac_reason) { QDF_STATUS status = QDF_STATUS_SUCCESS; tSmeCmd *pCommand; @@ -9598,9 +9981,8 @@ QDF_STATUS csr_roam_issue_disassociate_cmd(tpAniSirGlobal pMac, } pCommand->command = eSmeCommandRoam; pCommand->sessionId = (uint8_t) sessionId; - sme_debug( - "Disassociate reason: %d, sessionId: %d", - reason, sessionId); + sme_debug("Disassociate reason: %d, vdev_id: %d", + reason, sessionId); switch (reason) { case eCSR_DISCONNECT_REASON_MIC_ERROR: pCommand->u.roamCmd.roamReason = @@ -9637,7 +10019,7 @@ QDF_STATUS csr_roam_issue_disassociate_cmd(tpAniSirGlobal pMac, default: break; } - pCommand->u.roamCmd.disconnect_reason = reason; + pCommand->u.roamCmd.disconnect_reason = mac_reason; status = csr_queue_sme_command(pMac, pCommand, true); if (!QDF_IS_STATUS_SUCCESS(status)) sme_err("fail to send message status: %d", status); @@ -9673,9 +10055,10 @@ QDF_STATUS csr_roam_issue_stop_bss_cmd(tpAniSirGlobal pMac, uint32_t sessionId, } QDF_STATUS csr_roam_disconnect_internal(tpAniSirGlobal pMac, uint32_t sessionId, - eCsrRoamDisconnectReason reason) + eCsrRoamDisconnectReason reason, + tSirMacReasonCodes mac_reason) { - QDF_STATUS status = QDF_STATUS_SUCCESS; + QDF_STATUS status = QDF_STATUS_E_FAILURE; struct csr_roam_session *pSession = CSR_GET_SESSION(pMac, sessionId); if (!pSession) { @@ -9693,10 +10076,9 @@ QDF_STATUS csr_roam_disconnect_internal(tpAniSirGlobal pMac, uint32_t sessionId, || csr_is_bss_type_ibss(pSession->connectedProfile.BSSType) || csr_is_roam_command_waiting_for_session(pMac, sessionId) || CSR_IS_CONN_NDI(&pSession->connectedProfile)) { - sme_debug("called"); status = csr_roam_issue_disassociate_cmd(pMac, sessionId, - reason); - } else { + reason, mac_reason); + } else if (pSession->scan_info.profile) { pMac->roam.roamSession[sessionId].connectState = eCSR_ASSOC_STATE_TYPE_INFRA_DISCONNECTING; csr_scan_abort_mac_scan(pMac, sessionId, INVAL_SCAN_ID); @@ -9704,11 +10086,13 @@ QDF_STATUS csr_roam_disconnect_internal(tpAniSirGlobal pMac, uint32_t sessionId, sme_debug("Disconnect cmd not queued, Roam command is not present return with status: %d", status); } + return status; } QDF_STATUS csr_roam_disconnect(tpAniSirGlobal mac_ctx, uint32_t session_id, - eCsrRoamDisconnectReason reason) + eCsrRoamDisconnectReason reason, + tSirMacReasonCodes mac_reason) { struct csr_roam_session *session = CSR_GET_SESSION(mac_ctx, session_id); @@ -9722,7 +10106,8 @@ QDF_STATUS csr_roam_disconnect(tpAniSirGlobal mac_ctx, uint32_t session_id, csr_roam_remove_duplicate_command(mac_ctx, session_id, NULL, eCsrForcedDisassoc); - return csr_roam_disconnect_internal(mac_ctx, session_id, reason); + return csr_roam_disconnect_internal(mac_ctx, session_id, reason, + mac_reason); } QDF_STATUS csr_roam_save_connected_information(tpAniSirGlobal pMac, @@ -9744,7 +10129,6 @@ QDF_STATUS csr_roam_save_connected_information(tpAniSirGlobal pMac, return QDF_STATUS_E_FAILURE; } - sme_debug("session id: %d", sessionId); pConnectProfile = &pSession->connectedProfile; if (pConnectProfile->pAddIEAssoc) { qdf_mem_free(pConnectProfile->pAddIEAssoc); @@ -9766,6 +10150,8 @@ QDF_STATUS csr_roam_save_connected_information(tpAniSirGlobal pMac, pConnectProfile->mcEncryptionType = pProfile->negotiatedMCEncryptionType; pConnectProfile->mcEncryptionInfo = pProfile->mcEncryptionType; + pConnectProfile->mgmt_encryption_type = + pProfile->mgmt_encryption_type; pConnectProfile->BSSType = pProfile->BSSType; pConnectProfile->modifyProfileFields.uapsd_mask = pProfile->uapsd_mask; @@ -9851,7 +10237,19 @@ QDF_STATUS csr_roam_save_connected_information(tpAniSirGlobal pMac, proxy_arp_service; } - if (NULL == pIes) + qdf_mem_zero(pConnectProfile->country_code, + WNI_CFG_COUNTRY_CODE_LEN); + if (pIesTemp->Country.present) { + qdf_mem_copy(pConnectProfile->country_code, + pIesTemp->Country.country, + WNI_CFG_COUNTRY_CODE_LEN); + sme_debug("Storing country in connected info, %c%c 0x%x", + pConnectProfile->country_code[0], + pConnectProfile->country_code[1], + pConnectProfile->country_code[2]); + } + + if (!pIes) /* Free memory if it allocated locally */ qdf_mem_free(pIesTemp); } @@ -9910,33 +10308,54 @@ static void csr_roam_join_rsp_processor(tpAniSirGlobal pMac, { tListElem *pEntry = NULL; tSmeCmd *pCommand = NULL; + mac_handle_t mac_handle = MAC_HANDLE(pMac); struct csr_roam_session *session_ptr; + struct csr_roam_connectedinfo *prev_connect_info; + tPmkidCacheInfo pmksa_entry; + uint32_t len = 0, roamId = 0, reason_code = 0; + bool is_dis_pending; - if (pSmeJoinRsp) { - session_ptr = CSR_GET_SESSION(pMac, pSmeJoinRsp->sessionId); - } else { - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_ERROR, - FL("Sme Join Response is NULL")); + if (!pSmeJoinRsp) { + sme_err("Sme Join Response is NULL"); return; } + + session_ptr = CSR_GET_SESSION(pMac, pSmeJoinRsp->sessionId); if (!session_ptr) { - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_ERROR, - ("session %d not found"), pSmeJoinRsp->sessionId); + sme_err("session %d not found", pSmeJoinRsp->sessionId); return; } + + prev_connect_info = &session_ptr->prev_assoc_ap_info; /* The head of the active list is the request we sent */ pEntry = csr_nonscan_active_ll_peek_head(pMac, LL_ACCESS_LOCK); if (pEntry) pCommand = GET_BASE_ADDR(pEntry, tSmeCmd, Link); - sme_debug("is_fils_connection %d", pSmeJoinRsp->is_fils_connection); + if (pSmeJoinRsp->is_fils_connection) + sme_debug("Fils connection"); /* Copy Sequence Number last used for FILS assoc failure case */ if (session_ptr->is_fils_connection) session_ptr->fils_seq_num = pSmeJoinRsp->fils_seq_num; + len = pSmeJoinRsp->assocReqLength + + pSmeJoinRsp->assocRspLength + pSmeJoinRsp->beaconLength; + if (prev_connect_info->pbFrames) + csr_roam_free_connected_info(pMac, prev_connect_info); + + prev_connect_info->pbFrames = qdf_mem_malloc(len); + if (prev_connect_info->pbFrames) { + qdf_mem_copy(prev_connect_info->pbFrames, pSmeJoinRsp->frames, + len); + prev_connect_info->nAssocReqLength = + pSmeJoinRsp->assocReqLength; + prev_connect_info->nAssocRspLength = + pSmeJoinRsp->assocRspLength; + prev_connect_info->nBeaconLength = pSmeJoinRsp->beaconLength; + } + if (eSIR_SME_SUCCESS == pSmeJoinRsp->statusCode) { - if (pCommand - && eCsrSmeIssuedAssocToSimilarAP == + if (pCommand && eCsrSmeIssuedAssocToSimilarAP == pCommand->u.roamCmd.roamReason) { #ifndef WLAN_MDM_CODE_REDUCTION_OPT sme_qos_csr_event_ind(pMac, pSmeJoinRsp->sessionId, @@ -9944,10 +10363,7 @@ static void csr_roam_join_rsp_processor(tpAniSirGlobal pMac, #endif } - session_ptr->supported_nss_1x1 = - pSmeJoinRsp->supported_nss_1x1; - sme_debug("SME session supported nss: %d", - session_ptr->supported_nss_1x1); + session_ptr->supported_nss_1x1 = pSmeJoinRsp->supported_nss_1x1; /* * The join bssid count can be reset as soon as @@ -9956,84 +10372,86 @@ static void csr_roam_join_rsp_processor(tpAniSirGlobal pMac, */ session_ptr->join_bssid_count = 0; csr_roam_complete(pMac, eCsrJoinSuccess, (void *)pSmeJoinRsp, - pSmeJoinRsp->sessionId); - } else { - uint32_t roamId = 0; - bool is_dis_pending; + pSmeJoinRsp->sessionId); - /* The head of the active list is the request we sent - * Try to get back the same profile and roam again - */ - if (pCommand) - roamId = pCommand->u.roamCmd.roamId; - session_ptr->joinFailStatusCode.statusCode = - pSmeJoinRsp->statusCode; - session_ptr->joinFailStatusCode.reasonCode = - pSmeJoinRsp->protStatusCode; - sme_warn("SmeJoinReq failed with statusCode= 0x%08X [%d]", - pSmeJoinRsp->statusCode, pSmeJoinRsp->statusCode); - /* If Join fails while Handoff is in progress, indicate - * disassociated event to supplicant to reconnect - */ - if (csr_roam_is_handoff_in_progress(pMac, - pSmeJoinRsp->sessionId)) { - csr_roam_call_callback(pMac, pSmeJoinRsp->sessionId, - NULL, roamId, - eCSR_ROAM_DISASSOCIATED, - eCSR_ROAM_RESULT_FORCED); - /* Should indicate neighbor roam algorithm about the - * connect failure here - */ - csr_neighbor_roam_indicate_connect(pMac, - pSmeJoinRsp->sessionId, - QDF_STATUS_E_FAILURE); - } - /* - * if userspace has issued disconnection, - * driver should not continue connecting + return; + } + /* The head of the active list is the request we sent + * Try to get back the same profile and roam again + */ + if (pCommand) + roamId = pCommand->u.roamCmd.roamId; + reason_code = pSmeJoinRsp->protStatusCode; + session_ptr->joinFailStatusCode.reasonCode = reason_code; + session_ptr->joinFailStatusCode.statusCode = pSmeJoinRsp->statusCode; + sme_warn("SmeJoinReq failed with status_code= 0x%08X [%d] reason:%d", + pSmeJoinRsp->statusCode, pSmeJoinRsp->statusCode, + reason_code); + /* + * Delete the PMKID of the BSSID for which the assoc reject is + * received from the AP due to invalid PMKID reason. + * This will avoid the driver trying to connect to same AP with + * the same stale PMKID if multiple connection attempts to different + * bss fail and supplicant issues connect request back to the same + * AP. + */ + if (reason_code == eSIR_MAC_INVALID_PMKID) { + sme_warn("Assoc reject from BSSID:%pM due to invalid PMKID", + session_ptr->joinFailStatusCode.bssId); + qdf_mem_copy(&pmksa_entry.BSSID.bytes, + &session_ptr->joinFailStatusCode.bssId, + sizeof(tSirMacAddr)); + sme_roam_del_pmkid_from_cache(mac_handle, session_ptr->sessionId, + &pmksa_entry, false); + } + /* If Join fails while Handoff is in progress, indicate + * disassociated event to supplicant to reconnect + */ + if (csr_roam_is_handoff_in_progress(pMac, pSmeJoinRsp->sessionId)) { + csr_roam_call_callback(pMac, pSmeJoinRsp->sessionId, NULL, + roamId, eCSR_ROAM_DISASSOCIATED, + eCSR_ROAM_RESULT_FORCED); + /* Should indicate neighbor roam algorithm about the + * connect failure here */ - is_dis_pending = is_disconnect_pending(pMac, - session_ptr->sessionId); - if (pCommand && (session_ptr->join_bssid_count < - CSR_MAX_BSSID_COUNT) && !is_dis_pending) - csr_roam(pMac, pCommand); - else { - /* - * When the upper layers issue a connect command, there - * is a roam command with reason eCsrHddIssued that - * gets enqueued and an associated timer for the SME - * command timeout is started which is currently 120 - * seconds. This command would be dequeued only upon - * successful connections. In case of join failures, if - * there are too many BSS in the cache, and if we fail - * Join requests with all of them, there is a chance of - * timing out the above timer. - */ - if (session_ptr->join_bssid_count >= - CSR_MAX_BSSID_COUNT) - QDF_TRACE(QDF_MODULE_ID_SME, - QDF_TRACE_LEVEL_ERROR, - "Excessive Join Req Failures"); + csr_neighbor_roam_indicate_connect(pMac, pSmeJoinRsp->sessionId, + QDF_STATUS_E_FAILURE); + } - if (is_dis_pending) - QDF_TRACE(QDF_MODULE_ID_SME, - QDF_TRACE_LEVEL_ERROR, - "disconnect is pending, complete roam"); + /* + * if userspace has issued disconnection, driver should not continue + * connecting + */ + is_dis_pending = is_disconnect_pending(pMac, session_ptr->sessionId); + if (pCommand && !is_dis_pending && + session_ptr->join_bssid_count < CSR_MAX_BSSID_COUNT) { + csr_roam(pMac, pCommand); + return; + } - if (session_ptr->bRefAssocStartCnt) - session_ptr->bRefAssocStartCnt--; + /* + * When the upper layers issue a connect command, there is a roam + * command with reason eCsrHddIssued that gets enqueued and an + * associated timer for the SME command timeout is started which is + * currently 120 seconds. This command would be dequeued only upon + * successful connections. In case of join failures, if there are too + * many BSS in the cache, and if we fail Join requests with all of them, + * there is a chance of timing out the above timer. + */ + if (session_ptr->join_bssid_count >= CSR_MAX_BSSID_COUNT) + sme_err("Excessive Join Req Failures"); - session_ptr->join_bssid_count = 0; + if (is_dis_pending) + sme_err("disconnect is pending, complete roam"); - csr_roam_call_callback(pMac, session_ptr->sessionId, - NULL, roamId, - eCSR_ROAM_ASSOCIATION_COMPLETION, - eCSR_ROAM_RESULT_NOT_ASSOCIATED); + if (session_ptr->bRefAssocStartCnt) + session_ptr->bRefAssocStartCnt--; - csr_roam_complete(pMac, eCsrNothingToJoin, NULL, - pSmeJoinRsp->sessionId); - } - } /*else: ( eSIR_SME_SUCCESS == pSmeJoinRsp->statusCode ) */ + session_ptr->join_bssid_count = 0; + csr_roam_call_callback(pMac, session_ptr->sessionId, NULL, roamId, + eCSR_ROAM_ASSOCIATION_COMPLETION, + eCSR_ROAM_RESULT_NOT_ASSOCIATED); + csr_roam_complete(pMac, eCsrNothingToJoin, NULL, pSmeJoinRsp->sessionId); } static QDF_STATUS csr_roam_issue_join(tpAniSirGlobal pMac, uint32_t sessionId, @@ -10044,9 +10462,6 @@ static QDF_STATUS csr_roam_issue_join(tpAniSirGlobal pMac, uint32_t sessionId, { QDF_STATUS status; - sme_debug("Attempting to Join Bssid= " MAC_ADDRESS_STR, - MAC_ADDR_ARRAY(pSirBssDesc->bssId)); - /* Set the roaming substate to 'join attempt'... */ csr_roam_substate_change(pMac, eCSR_ROAM_SUBSTATE_JOIN_REQ, sessionId); /* attempt to Join this BSS... */ @@ -10060,7 +10475,7 @@ csr_roam_reissue_roam_command(tpAniSirGlobal pMac, uint8_t session_id) { tListElem *pEntry; tSmeCmd *pCommand; - struct csr_roam_info roamInfo; + struct csr_roam_info *roam_info; uint32_t sessionId; struct csr_roam_session *pSession; @@ -10102,12 +10517,14 @@ csr_roam_reissue_roam_command(tpAniSirGlobal pMac, uint8_t session_id) } return; } - qdf_mem_zero(&roamInfo, sizeof(struct csr_roam_info)); - roamInfo.pBssDesc = pCommand->u.roamCmd.pLastRoamBss; - roamInfo.statusCode = pSession->joinFailStatusCode.statusCode; - roamInfo.reasonCode = pSession->joinFailStatusCode.reasonCode; + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return; + roam_info->pBssDesc = pCommand->u.roamCmd.pLastRoamBss; + roam_info->statusCode = pSession->joinFailStatusCode.statusCode; + roam_info->reasonCode = pSession->joinFailStatusCode.reasonCode; pSession->connectState = eCSR_ASSOC_STATE_TYPE_INFRA_DISCONNECTED; - csr_roam_call_callback(pMac, sessionId, &roamInfo, + csr_roam_call_callback(pMac, sessionId, roam_info, pCommand->u.roamCmd.roamId, eCSR_ROAM_INFRA_IND, eCSR_ROAM_RESULT_INFRA_DISASSOCIATED); @@ -10117,6 +10534,7 @@ csr_roam_reissue_roam_command(tpAniSirGlobal pMac, uint8_t session_id) sme_err("Failed to reissue stop_bss command for WDS"); csr_roam_complete(pMac, eCsrNothingToJoin, NULL, session_id); } + qdf_mem_free(roam_info); } bool csr_is_roam_command_waiting_for_session(tpAniSirGlobal pMac, @@ -10211,8 +10629,6 @@ csr_roaming_state_config_cnf_processor(tpAniSirGlobal mac_ctx, return; } - /* we have active entry */ - sme_debug("Cfg sequence complete"); /* * Successfully set the configuration parameters for the new Bss. * Attempt to join the roaming Bss @@ -10345,8 +10761,6 @@ static void csr_roam_roaming_state_reassoc_rsp_processor(tpAniSirGlobal pMac, { enum csr_roamcomplete_result result; tpCsrNeighborRoamControlInfo pNeighborRoamInfo = NULL; - struct csr_roam_info roamInfo; - uint32_t roamId = 0; struct csr_roam_session *csr_session; if (pSmeJoinRsp->sessionId >= CSR_ROAM_SESSION_MAX) { @@ -10397,7 +10811,7 @@ static void csr_roam_roaming_state_reassoc_rsp_processor(tpAniSirGlobal pMac, cds_flush_logs(WLAN_LOG_TYPE_FATAL, WLAN_LOG_INDICATOR_HOST_DRIVER, WLAN_LOG_REASON_ROAM_FAIL, - true, false); + false, false); if ((eSIR_SME_FT_REASSOC_TIMEOUT_FAILURE == pSmeJoinRsp->statusCode) || (eSIR_SME_FT_REASSOC_FAILURE == @@ -10406,12 +10820,20 @@ static void csr_roam_roaming_state_reassoc_rsp_processor(tpAniSirGlobal pMac, pSmeJoinRsp->statusCode)) { /* Inform HDD to turn off FT flag in HDD */ if (pNeighborRoamInfo) { - qdf_mem_zero(&roamInfo, sizeof(roamInfo)); + struct csr_roam_info *roam_info; + uint32_t roam_id = 0; + + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return; + mlme_set_discon_reason_n_from_ap(pMac->psoc, + pSmeJoinRsp->sessionId, false, + eSIR_MAC_HOST_TRIGGERED_ROAM_FAILURE); csr_roam_call_callback(pMac, - pSmeJoinRsp->sessionId, - &roamInfo, roamId, - eCSR_ROAM_FT_REASSOC_FAILED, - eCSR_ROAM_RESULT_SUCCESS); + pSmeJoinRsp->sessionId, + roam_info, roam_id, + eCSR_ROAM_FT_REASSOC_FAILED, + eCSR_ROAM_RESULT_SUCCESS); /* * Since the above callback sends a disconnect * to HDD, we should clean-up our state @@ -10424,6 +10846,7 @@ static void csr_roam_roaming_state_reassoc_rsp_processor(tpAniSirGlobal pMac, */ csr_roam_complete(pMac, eCsrJoinFailure, NULL, pSmeJoinRsp->sessionId); + qdf_mem_free(roam_info); return; } } @@ -10739,6 +11162,8 @@ void csr_roam_roaming_state_disassoc_rsp_processor(tpAniSirGlobal pMac, csr_scan_result_purge(pMac, hBSSList); POST_ROAM_FAILURE: + mlme_set_discon_reason_n_from_ap(pMac->psoc, sessionId, false, + eSIR_MAC_HOST_TRIGGERED_ROAM_FAILURE); csr_post_roam_failure(pMac, sessionId, roamInfo, pScanFilter, pCurRoamProfile); } /* else if ( CSR_IS_ROAM_SUBSTATE_DISASSOC_HO( pMac ) ) */ @@ -10776,7 +11201,6 @@ static void csr_roam_roaming_state_deauth_rsp_processor(tpAniSirGlobal pMac, { tSirResultCodes statusCode; /* No one is sending eWNI_SME_DEAUTH_REQ to PE. */ - sme_debug("is no-op"); statusCode = csr_get_de_auth_rsp_status_code(pSmeRsp); pMac->roam.deauthRspStatus = statusCode; if (CSR_IS_ROAM_SUBSTATE_DEAUTH_REQ(pMac, pSmeRsp->sessionId)) { @@ -10788,10 +11212,6 @@ static void csr_roam_roaming_state_deauth_rsp_processor(tpAniSirGlobal pMac, /* */ sme_debug( "CSR SmeDeauthReq disassociated Successfully"); - } else { - sme_warn( - "SmeDeauthReq failed with statusCode= 0x%08X", - statusCode); } /* We are not done yet. Get the data and continue roaming */ csr_roam_reissue_roam_command(pMac, pSmeRsp->sessionId); @@ -10836,10 +11256,13 @@ csr_roam_send_disconnect_done_indication(tpAniSirGlobal mac_ctx, tSirSmeRsp (struct sir_sme_discon_done_ind *)(msg_ptr); struct csr_roam_info roam_info; struct csr_roam_session *session; + struct wlan_objmgr_vdev *vdev; + uint8_t vdev_id; sme_debug("DISCONNECT_DONE_IND RC:%d", discon_ind->reason_code); + vdev_id = discon_ind->session_id; - if (CSR_IS_SESSION_VALID(mac_ctx, discon_ind->session_id)) { + if (CSR_IS_SESSION_VALID(mac_ctx, vdev_id)) { roam_info.reasonCode = discon_ind->reason_code; roam_info.statusCode = eSIR_SME_STA_NOT_ASSOCIATED; qdf_mem_copy(roam_info.peerMac.bytes, discon_ind->peer_mac, @@ -10849,25 +11272,43 @@ csr_roam_send_disconnect_done_indication(tpAniSirGlobal mac_ctx, tSirSmeRsp roam_info.tx_rate = mac_ctx->peer_txrate; roam_info.rx_rate = mac_ctx->peer_rxrate; roam_info.disassoc_reason = discon_ind->reason_code; - - csr_roam_call_callback(mac_ctx, discon_ind->session_id, + vdev = wlan_objmgr_get_vdev_by_id_from_psoc(mac_ctx->psoc, + vdev_id, + WLAN_LEGACY_SME_ID); + if (vdev) + roam_info.disconnect_ies = + mlme_get_peer_disconnect_ies(vdev); + + csr_roam_call_callback(mac_ctx, vdev_id, &roam_info, 0, eCSR_ROAM_LOSTLINK, eCSR_ROAM_RESULT_DISASSOC_IND); - session = CSR_GET_SESSION(mac_ctx, discon_ind->session_id); - if (session && - !CSR_IS_INFRA_AP(&session->connectedProfile)) + if (vdev) { + mlme_free_peer_disconnect_ies(vdev); + wlan_objmgr_vdev_release_ref(vdev, WLAN_LEGACY_SME_ID); + } + session = CSR_GET_SESSION(mac_ctx, vdev_id); + if (!CSR_IS_INFRA_AP(&session->connectedProfile)) csr_roam_state_change(mac_ctx, eCSR_ROAMING_STATE_IDLE, - discon_ind->session_id); + vdev_id); + + if (CSR_IS_INFRASTRUCTURE(&session->connectedProfile)) { + csr_free_roam_profile(mac_ctx, vdev_id); + csr_free_connect_bss_desc(mac_ctx, vdev_id); + csr_roam_free_connect_profile( + &session->connectedProfile); + csr_roam_free_connected_info(mac_ctx, + &session->connectedInfo); + } } else { - sme_err("Inactive session %d", discon_ind->session_id); + sme_err("Inactive vdev_id %d", vdev_id); } /* * Release WM status change command as eWNI_SME_DISCONNECT_DONE_IND * has been sent to HDD and there is nothing else left to do. */ - csr_roam_wm_status_change_complete(mac_ctx, discon_ind->session_id); + csr_roam_wm_status_change_complete(mac_ctx, vdev_id); } @@ -10891,10 +11332,6 @@ void csr_roaming_state_msg_processor(tpAniSirGlobal pMac, void *pMsgBuf) struct csr_roam_info *roam_info; pSmeRsp = (tSirSmeRsp *) pMsgBuf; - sme_debug("Message %d[0x%04X] received in substate %s", - pSmeRsp->messageType, pSmeRsp->messageType, - mac_trace_getcsr_roam_sub_state( - pMac->roam.curSubState[pSmeRsp->sessionId])); switch (pSmeRsp->messageType) { @@ -11029,14 +11466,11 @@ void csr_roam_joined_state_msg_processor(tpAniSirGlobal pMac, void *pMsgBuf) { struct csr_roam_session *pSession; tSirSmeAssocIndToUpperLayerCnf *pUpperLayerAssocCnf; - struct csr_roam_info roamInfo; - struct csr_roam_info *roam_info = NULL; + struct csr_roam_info *roam_info; uint32_t sessionId; QDF_STATUS status; sme_debug("ASSOCIATION confirmation can be given to upper layer "); - qdf_mem_zero(&roamInfo, sizeof(struct csr_roam_info)); - roam_info = &roamInfo; pUpperLayerAssocCnf = (tSirSmeAssocIndToUpperLayerCnf *) pMsgBuf; status = csr_roam_get_session_id_from_bssid(pMac, @@ -11047,6 +11481,16 @@ void csr_roam_joined_state_msg_processor(tpAniSirGlobal pMac, void *pMsgBuf) if (!pSession) { sme_err("session %d not found", sessionId); + if (pUpperLayerAssocCnf->ies) + qdf_mem_free(pUpperLayerAssocCnf->ies); + return; + } + + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) { + sme_err("roam_info not allocated"); + if (pUpperLayerAssocCnf->ies) + qdf_mem_free(pUpperLayerAssocCnf->ies); return; } /* send the status code as Success */ @@ -11103,6 +11547,13 @@ void csr_roam_joined_state_msg_processor(tpAniSirGlobal pMac, void *pMsgBuf) pUpperLayerAssocCnf->he_caps_present; if (CSR_IS_INFRA_AP(roam_info->u.pConnectedProfile)) { + if (pUpperLayerAssocCnf->ies_len > 0) { + roam_info->assocReqLength = + pUpperLayerAssocCnf->ies_len; + roam_info->assocReqPtr = + pUpperLayerAssocCnf->ies; + } + pMac->roam.roamSession[sessionId].connectState = eCSR_ASSOC_STATE_TYPE_INFRA_CONNECTED; roam_info->fReassocReq = @@ -11112,6 +11563,9 @@ void csr_roam_joined_state_msg_processor(tpAniSirGlobal pMac, void *pMsgBuf) eCSR_ROAM_INFRA_IND, eCSR_ROAM_RESULT_INFRA_ASSOCIATION_CNF); } + if (pUpperLayerAssocCnf->ies) + qdf_mem_free(pUpperLayerAssocCnf->ies); + qdf_mem_free(roam_info); } break; default: @@ -11922,17 +12376,128 @@ static QDF_STATUS csr_send_reset_ap_caps_changed(tpAniSirGlobal pMac, return status; } +#ifdef FEATURE_WLAN_ESE +/** + * csr_convert_ese_akm_to_ani() - Convert eCsrAuthType ESE akm value to + * equivalent enum ani_akm_type value + * @akm_type: value of type enum ani_akm_type + * + * Return: ani_akm_type value corresponding + */ +static enum ani_akm_type csr_convert_ese_akm_to_ani(eCsrAuthType akm_type) +{ + switch (akm_type) { + case eCSR_AUTH_TYPE_CCKM_RSN: + return ANI_AKM_TYPE_CCKM; + default: + return ANI_AKM_TYPE_UNKNOWN; + } +} +#else +static inline enum +ani_akm_type csr_convert_ese_akm_to_ani(eCsrAuthType akm_type) +{ + return ANI_AKM_TYPE_UNKNOWN; +} +#endif + +#ifdef WLAN_FEATURE_SAE +/** + * csr_convert_sae_akm_to_ani() - Convert eCsrAuthType SAE akm value to + * equivalent enum ani_akm_type value + * @akm_type: value of type enum ani_akm_type + * + * Return: ani_akm_type value corresponding + */ +static enum ani_akm_type csr_convert_sae_akm_to_ani(eCsrAuthType akm_type) +{ + switch (akm_type) { + case eCSR_AUTH_TYPE_SAE: + return ANI_AKM_TYPE_SAE; + case eCSR_AUTH_TYPE_FT_SAE: + return ANI_AKM_TYPE_FT_SAE; + default: + return ANI_AKM_TYPE_UNKNOWN; + } +} +#else +static inline +enum ani_akm_type csr_convert_sae_akm_to_ani(eCsrAuthType akm_type) +{ + return ANI_AKM_TYPE_UNKNOWN; +} +#endif + +/** + * csr_convert_csr_to_ani_akm_type() - Convert eCsrAuthType value to equivalent + * enum ani_akm_type value + * @akm_type: value of type enum ani_akm_type + * + * Return: ani_akm_type value corresponding + */ +static enum ani_akm_type csr_convert_csr_to_ani_akm_type(eCsrAuthType akm_type) +{ + enum ani_akm_type ani_akm; + + switch (akm_type) { + case eCSR_AUTH_TYPE_NONE: + return ANI_AKM_TYPE_NONE; + case eCSR_AUTH_TYPE_WPA: + return ANI_AKM_TYPE_WPA; + case eCSR_AUTH_TYPE_WPA_PSK: + return ANI_AKM_TYPE_WPA_PSK; + case eCSR_AUTH_TYPE_RSN: + return ANI_AKM_TYPE_RSN; + case eCSR_AUTH_TYPE_RSN_PSK: + return ANI_AKM_TYPE_RSN_PSK; + case eCSR_AUTH_TYPE_FT_RSN: + return ANI_AKM_TYPE_FT_RSN; + case eCSR_AUTH_TYPE_FT_RSN_PSK: + return ANI_AKM_TYPE_FT_RSN_PSK; + case eCSR_AUTH_TYPE_RSN_PSK_SHA256: + return ANI_AKM_TYPE_RSN_PSK_SHA256; + case eCSR_AUTH_TYPE_RSN_8021X_SHA256: + return ANI_AKM_TYPE_RSN_8021X_SHA256; + case eCSR_AUTH_TYPE_FILS_SHA256: + return ANI_AKM_TYPE_FILS_SHA256; + case eCSR_AUTH_TYPE_FILS_SHA384: + return ANI_AKM_TYPE_FILS_SHA384; + case eCSR_AUTH_TYPE_FT_FILS_SHA256: + return ANI_AKM_TYPE_FT_FILS_SHA256; + case eCSR_AUTH_TYPE_FT_FILS_SHA384: + return ANI_AKM_TYPE_FT_FILS_SHA384; + case eCSR_AUTH_TYPE_DPP_RSN: + return ANI_AKM_TYPE_DPP_RSN; + case eCSR_AUTH_TYPE_OWE: + return ANI_AKM_TYPE_OWE; + case eCSR_AUTH_TYPE_SUITEB_EAP_SHA256: + return ANI_AKM_TYPE_SUITEB_EAP_SHA256; + case eCSR_AUTH_TYPE_SUITEB_EAP_SHA384: + return ANI_AKM_TYPE_SUITEB_EAP_SHA384; + case eCSR_AUTH_TYPE_FT_SUITEB_EAP_SHA384: + return ANI_AKM_TYPE_FT_SUITEB_EAP_SHA384; + default: + ani_akm = ANI_AKM_TYPE_UNKNOWN; + } + + if (ani_akm == ANI_AKM_TYPE_UNKNOWN) + ani_akm = csr_convert_sae_akm_to_ani(akm_type); + + if (ani_akm == ANI_AKM_TYPE_UNKNOWN) + ani_akm = csr_convert_ese_akm_to_ani(akm_type); + + return ani_akm; +} + static void csr_roam_chk_lnk_assoc_ind(tpAniSirGlobal mac_ctx, tSirSmeRsp *msg_ptr) { struct csr_roam_session *session; uint32_t sessionId = CSR_SESSION_ID_INVALID; QDF_STATUS status; - struct csr_roam_info *roam_info_ptr = NULL; + struct csr_roam_info *roam_info; tSirSmeAssocInd *pAssocInd; - struct csr_roam_info roam_info; - qdf_mem_zero(&roam_info, sizeof(roam_info)); sme_debug("Receive WNI_SME_ASSOC_IND from SME"); pAssocInd = (tSirSmeAssocInd *) msg_ptr; status = csr_roam_get_session_id_from_bssid(mac_ctx, @@ -11947,67 +12512,72 @@ csr_roam_chk_lnk_assoc_ind(tpAniSirGlobal mac_ctx, tSirSmeRsp *msg_ptr) sme_err("session %d not found", sessionId); return; } - roam_info_ptr = &roam_info; + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return; /* Required for indicating the frames to upper layer */ - roam_info_ptr->assocReqLength = pAssocInd->assocReqLength; - roam_info_ptr->assocReqPtr = pAssocInd->assocReqPtr; - roam_info_ptr->beaconPtr = pAssocInd->beaconPtr; - roam_info_ptr->beaconLength = pAssocInd->beaconLength; - roam_info_ptr->statusCode = eSIR_SME_SUCCESS; - roam_info_ptr->u.pConnectedProfile = &session->connectedProfile; - roam_info_ptr->staId = (uint8_t) pAssocInd->staId; - roam_info_ptr->rsnIELen = (uint8_t) pAssocInd->rsnIE.length; - roam_info_ptr->prsnIE = pAssocInd->rsnIE.rsnIEdata; + roam_info->assocReqLength = pAssocInd->assocReqLength; + roam_info->assocReqPtr = pAssocInd->assocReqPtr; + roam_info->beaconPtr = pAssocInd->beaconPtr; + roam_info->beaconLength = pAssocInd->beaconLength; + roam_info->statusCode = eSIR_SME_SUCCESS; + roam_info->u.pConnectedProfile = &session->connectedProfile; + roam_info->staId = (uint8_t)pAssocInd->staId; + roam_info->rsnIELen = (uint8_t)pAssocInd->rsnIE.length; + roam_info->prsnIE = pAssocInd->rsnIE.rsnIEdata; #ifdef FEATURE_WLAN_WAPI - roam_info_ptr->wapiIELen = (uint8_t) pAssocInd->wapiIE.length; - roam_info_ptr->pwapiIE = pAssocInd->wapiIE.wapiIEdata; + roam_info->wapiIELen = (uint8_t)pAssocInd->wapiIE.length; + roam_info->pwapiIE = pAssocInd->wapiIE.wapiIEdata; #endif - roam_info_ptr->addIELen = (uint8_t) pAssocInd->addIE.length; - roam_info_ptr->paddIE = pAssocInd->addIE.addIEdata; - qdf_mem_copy(roam_info_ptr->peerMac.bytes, + roam_info->addIELen = (uint8_t)pAssocInd->addIE.length; + roam_info->paddIE = pAssocInd->addIE.addIEdata; + qdf_mem_copy(roam_info->peerMac.bytes, pAssocInd->peerMacAddr, sizeof(tSirMacAddr)); - qdf_mem_copy(roam_info_ptr->bssid.bytes, + qdf_mem_copy(roam_info->bssid.bytes, pAssocInd->bssId, sizeof(struct qdf_mac_addr)); - roam_info_ptr->wmmEnabledSta = pAssocInd->wmmEnabledSta; - roam_info_ptr->timingMeasCap = pAssocInd->timingMeasCap; - roam_info_ptr->ecsa_capable = pAssocInd->ecsa_capable; - qdf_mem_copy(&roam_info_ptr->chan_info, + roam_info->wmmEnabledSta = pAssocInd->wmmEnabledSta; + roam_info->timingMeasCap = pAssocInd->timingMeasCap; + roam_info->ecsa_capable = pAssocInd->ecsa_capable; + qdf_mem_copy(&roam_info->chan_info, &pAssocInd->chan_info, sizeof(tSirSmeChanInfo)); if (pAssocInd->HTCaps.present) - qdf_mem_copy(&roam_info_ptr->ht_caps, + qdf_mem_copy(&roam_info->ht_caps, &pAssocInd->HTCaps, sizeof(tDot11fIEHTCaps)); if (pAssocInd->VHTCaps.present) - qdf_mem_copy(&roam_info_ptr->vht_caps, + qdf_mem_copy(&roam_info->vht_caps, &pAssocInd->VHTCaps, sizeof(tDot11fIEVHTCaps)); - roam_info_ptr->capability_info = pAssocInd->capability_info; - roam_info_ptr->he_caps_present = pAssocInd->he_caps_present; - if (CSR_IS_INFRA_AP(roam_info_ptr->u.pConnectedProfile)) { + roam_info->capability_info = pAssocInd->capability_info; + roam_info->he_caps_present = pAssocInd->he_caps_present; + + if (CSR_IS_INFRA_AP(roam_info->u.pConnectedProfile)) { if (session->pCurRoamProfile && CSR_IS_ENC_TYPE_STATIC( session->pCurRoamProfile->negotiatedUCEncryptionType)) { /* NO keys... these key parameters don't matter. */ - csr_roam_issue_set_context_req(mac_ctx, sessionId, - session->pCurRoamProfile->negotiatedUCEncryptionType, - session->pConnectBssDesc, - &(roam_info_ptr->peerMac.bytes), - false, true, eSIR_TX_RX, 0, 0, NULL, 0); - roam_info_ptr->fAuthRequired = false; + csr_roam_issue_set_context_req(mac_ctx, + sessionId, + session->pCurRoamProfile-> + negotiatedUCEncryptionType, + session->pConnectBssDesc, + &roam_info->peerMac.bytes, + false, true, eSIR_TX_RX, 0, 0, NULL, 0); + roam_info->fAuthRequired = false; } else { - roam_info_ptr->fAuthRequired = true; + roam_info->fAuthRequired = true; } status = csr_roam_call_callback(mac_ctx, sessionId, - roam_info_ptr, 0, eCSR_ROAM_INFRA_IND, + roam_info, 0, eCSR_ROAM_INFRA_IND, eCSR_ROAM_RESULT_INFRA_ASSOCIATION_IND); if (!QDF_IS_STATUS_SUCCESS(status)) /* Refused due to Mac filtering */ - roam_info_ptr->statusCode = eSIR_SME_ASSOC_REFUSED; + roam_info->statusCode = eSIR_SME_ASSOC_REFUSED; } /* Send Association completion message to PE */ @@ -12016,12 +12586,14 @@ csr_roam_chk_lnk_assoc_ind(tpAniSirGlobal mac_ctx, tSirSmeRsp *msg_ptr) * send a message to CSR itself just to avoid the EAPOL frames going * OTA before association response */ - if (CSR_IS_INFRA_AP(roam_info_ptr->u.pConnectedProfile) - && (roam_info_ptr->statusCode != eSIR_SME_ASSOC_REFUSED)) { - roam_info_ptr->fReassocReq = pAssocInd->reassocReq; + if (CSR_IS_INFRA_AP(roam_info->u.pConnectedProfile) && + roam_info->statusCode != eSIR_SME_ASSOC_REFUSED) { + roam_info->fReassocReq = pAssocInd->reassocReq; status = csr_send_assoc_ind_to_upper_layer_cnf_msg(mac_ctx, pAssocInd, status, sessionId); } + + qdf_mem_free(roam_info); } /* @@ -12100,10 +12672,11 @@ csr_roam_chk_lnk_disassoc_ind(tpAniSirGlobal mac_ctx, tSirSmeRsp *msg_ptr) return; } - sme_err("DISASSOCIATION from peer =" MAC_ADDRESS_STR "reason: %d status: %d session: %d", - MAC_ADDR_ARRAY(pDisassocInd->peer_macaddr.bytes), - pDisassocInd->reasonCode, - pDisassocInd->statusCode, sessionId); + sme_nofl_info("disassoc from peer " MAC_ADDRESS_STR + "reason: %d status: %d vid: %d", + MAC_ADDR_ARRAY(pDisassocInd->peer_macaddr.bytes), + pDisassocInd->reasonCode, + pDisassocInd->statusCode, sessionId); /* * If we are in neighbor preauth done state then on receiving * disassoc or deauth we dont roam instead we just disassoc @@ -12131,7 +12704,7 @@ csr_roam_chk_lnk_disassoc_ind(tpAniSirGlobal mac_ctx, tSirSmeRsp *msg_ptr) return; } - /* Update the disconnect stats */ + /* Update the disconnect stats */ session->disconnect_stats.disconnection_cnt++; session->disconnect_stats.disassoc_by_peer++; @@ -12168,11 +12741,10 @@ csr_roam_chk_lnk_deauth_ind(tpAniSirGlobal mac_ctx, tSirSmeRsp *msg_ptr) uint32_t sessionId = CSR_SESSION_ID_INVALID; QDF_STATUS status; tSirSmeDeauthInd *pDeauthInd; - struct csr_roam_info roam_info; - qdf_mem_zero(&roam_info, sizeof(roam_info)); - sme_debug("DEAUTHENTICATION Indication from MAC"); pDeauthInd = (tpSirSmeDeauthInd) msg_ptr; + sme_debug("DEAUTH Indication from MAC for vdev_id %d bssid %pM", + pDeauthInd->sessionId, pDeauthInd->bssid.bytes); status = csr_roam_get_session_id_from_bssid(mac_ctx, &pDeauthInd->bssid, &sessionId); @@ -12222,7 +12794,7 @@ csr_roam_chk_lnk_deauth_ind(tpAniSirGlobal mac_ctx, tSirSmeRsp *msg_ptr) session->disconnect_stats.disconnection_cnt++; session->disconnect_stats.deauth_by_peer++; break; - case eSIR_BEACON_MISSED: + case eSIR_MAC_BEACON_MISSED: session->disconnect_stats.disconnection_cnt++; session->disconnect_stats.bmiss++; break; @@ -12251,7 +12823,7 @@ csr_roam_chk_lnk_swt_ch_ind(tpAniSirGlobal mac_ctx, tSirSmeRsp *msg_ptr) uint16_t ie_len; QDF_STATUS status; tpSirSmeSwitchChannelInd pSwitchChnInd; - struct csr_roam_info roamInfo; + struct csr_roam_info *roam_info; tSirMacDsParamSetIE *ds_params_ie; tDot11fIEHTInfo *ht_info_ie; @@ -12299,26 +12871,29 @@ csr_roam_chk_lnk_swt_ch_ind(tpAniSirGlobal mac_ctx, tSirSmeRsp *msg_ptr) } } - qdf_mem_zero(&roamInfo, sizeof(struct csr_roam_info)); - roamInfo.chan_info.chan_id = pSwitchChnInd->newChannelId; - roamInfo.chan_info.ch_width = pSwitchChnInd->chan_params.ch_width; - roamInfo.chan_info.sec_ch_offset = + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return; + roam_info->chan_info.chan_id = pSwitchChnInd->newChannelId; + roam_info->chan_info.ch_width = pSwitchChnInd->chan_params.ch_width; + roam_info->chan_info.sec_ch_offset = pSwitchChnInd->chan_params.sec_ch_offset; - roamInfo.chan_info.band_center_freq1 = + roam_info->chan_info.band_center_freq1 = pSwitchChnInd->chan_params.center_freq_seg0; - roamInfo.chan_info.band_center_freq2 = + roam_info->chan_info.band_center_freq2 = pSwitchChnInd->chan_params.center_freq_seg1; if (CSR_IS_PHY_MODE_11ac(mac_ctx->roam.configParam.phyMode)) - roamInfo.mode = SIR_SME_PHY_MODE_VHT; + roam_info->mode = SIR_SME_PHY_MODE_VHT; else if (CSR_IS_PHY_MODE_11n(mac_ctx->roam.configParam.phyMode)) - roamInfo.mode = SIR_SME_PHY_MODE_HT; + roam_info->mode = SIR_SME_PHY_MODE_HT; else - roamInfo.mode = SIR_SME_PHY_MODE_LEGACY; + roam_info->mode = SIR_SME_PHY_MODE_LEGACY; - status = csr_roam_call_callback(mac_ctx, sessionId, &roamInfo, 0, + status = csr_roam_call_callback(mac_ctx, sessionId, roam_info, 0, eCSR_ROAM_STA_CHANNEL_SWITCH, eCSR_ROAM_RESULT_NONE); + qdf_mem_free(roam_info); } static void @@ -12327,28 +12902,31 @@ csr_roam_chk_lnk_deauth_rsp(tpAniSirGlobal mac_ctx, tSirSmeRsp *msg_ptr) struct csr_roam_session *session; uint32_t sessionId = CSR_SESSION_ID_INVALID; QDF_STATUS status; - struct csr_roam_info *roam_info_ptr = NULL; + struct csr_roam_info *roam_info; tSirSmeDeauthRsp *pDeauthRsp = (tSirSmeDeauthRsp *) msg_ptr; - struct csr_roam_info roam_info; - qdf_mem_zero(&roam_info, sizeof(roam_info)); + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return; sme_debug("eWNI_SME_DEAUTH_RSP from SME"); sessionId = pDeauthRsp->sessionId; - if (!CSR_IS_SESSION_VALID(mac_ctx, sessionId)) + if (!CSR_IS_SESSION_VALID(mac_ctx, sessionId)) { + qdf_mem_free(roam_info); return; + } session = CSR_GET_SESSION(mac_ctx, sessionId); if (CSR_IS_INFRA_AP(&session->connectedProfile)) { - roam_info_ptr = &roam_info; - roam_info_ptr->u.pConnectedProfile = &session->connectedProfile; - qdf_copy_macaddr(&roam_info_ptr->peerMac, + roam_info->u.pConnectedProfile = &session->connectedProfile; + qdf_copy_macaddr(&roam_info->peerMac, &pDeauthRsp->peer_macaddr); - roam_info_ptr->reasonCode = eCSR_ROAM_RESULT_FORCED; - roam_info_ptr->statusCode = pDeauthRsp->statusCode; + roam_info->reasonCode = eCSR_ROAM_RESULT_FORCED; + roam_info->statusCode = pDeauthRsp->statusCode; status = csr_roam_call_callback(mac_ctx, sessionId, - roam_info_ptr, 0, + roam_info, 0, eCSR_ROAM_LOSTLINK, eCSR_ROAM_RESULT_FORCED); } + qdf_mem_free(roam_info); } static void @@ -12357,32 +12935,35 @@ csr_roam_chk_lnk_disassoc_rsp(tpAniSirGlobal mac_ctx, tSirSmeRsp *msg_ptr) struct csr_roam_session *session; uint32_t sessionId = CSR_SESSION_ID_INVALID; QDF_STATUS status; - struct csr_roam_info *roam_info_ptr = NULL; - struct csr_roam_info roam_info; + struct csr_roam_info *roam_info; /* * session id is invalid here so cant use it to access the array * curSubstate as index */ tSirSmeDisassocRsp *pDisassocRsp = (tSirSmeDisassocRsp *) msg_ptr; - qdf_mem_zero(&roam_info, sizeof(roam_info)); + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return; sme_debug("eWNI_SME_DISASSOC_RSP from SME "); sessionId = pDisassocRsp->sessionId; - if (!CSR_IS_SESSION_VALID(mac_ctx, sessionId)) + if (!CSR_IS_SESSION_VALID(mac_ctx, sessionId)) { + qdf_mem_free(roam_info); return; + } session = CSR_GET_SESSION(mac_ctx, sessionId); if (CSR_IS_INFRA_AP(&session->connectedProfile)) { - roam_info_ptr = &roam_info; - roam_info_ptr->u.pConnectedProfile = &session->connectedProfile; - qdf_copy_macaddr(&roam_info_ptr->peerMac, + roam_info->u.pConnectedProfile = &session->connectedProfile; + qdf_copy_macaddr(&roam_info->peerMac, &pDisassocRsp->peer_macaddr); - roam_info_ptr->reasonCode = eCSR_ROAM_RESULT_FORCED; - roam_info_ptr->statusCode = pDisassocRsp->statusCode; + roam_info->reasonCode = eCSR_ROAM_RESULT_FORCED; + roam_info->statusCode = pDisassocRsp->statusCode; status = csr_roam_call_callback(mac_ctx, sessionId, - roam_info_ptr, 0, + roam_info, 0, eCSR_ROAM_LOSTLINK, eCSR_ROAM_RESULT_FORCED); } + qdf_mem_free(roam_info); } #ifdef FEATURE_WLAN_DIAG_SUPPORT_CSR @@ -12419,28 +13000,28 @@ csr_roam_chk_lnk_mic_fail_ind(tpAniSirGlobal mac_ctx, tSirSmeRsp *msg_ptr) { uint32_t sessionId = CSR_SESSION_ID_INVALID; QDF_STATUS status; - struct csr_roam_info *roam_info_ptr = NULL; - struct csr_roam_info roam_info; + struct csr_roam_info *roam_info; tpSirSmeMicFailureInd pMicInd = (tpSirSmeMicFailureInd) msg_ptr; eCsrRoamResult result = eCSR_ROAM_RESULT_MIC_ERROR_UNICAST; - qdf_mem_zero(&roam_info, sizeof(roam_info)); + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return; status = csr_roam_get_session_id_from_bssid(mac_ctx, &pMicInd->bssId, &sessionId); if (QDF_IS_STATUS_SUCCESS(status)) { - qdf_mem_zero(&roam_info, sizeof(struct csr_roam_info)); - roam_info.u.pMICFailureInfo = &pMicInd->info; - roam_info_ptr = &roam_info; + roam_info->u.pMICFailureInfo = &pMicInd->info; if (pMicInd->info.multicast) result = eCSR_ROAM_RESULT_MIC_ERROR_GROUP; else result = eCSR_ROAM_RESULT_MIC_ERROR_UNICAST; - csr_roam_call_callback(mac_ctx, sessionId, roam_info_ptr, 0, + csr_roam_call_callback(mac_ctx, sessionId, roam_info, 0, eCSR_ROAM_MIC_ERROR_IND, result); } #ifdef FEATURE_WLAN_DIAG_SUPPORT_CSR csr_roam_diag_mic_fail(mac_ctx, sessionId); #endif /* FEATURE_WLAN_DIAG_SUPPORT_CSR */ + qdf_mem_free(roam_info); } static void @@ -12448,21 +13029,23 @@ csr_roam_chk_lnk_pbs_probe_req_ind(tpAniSirGlobal mac_ctx, tSirSmeRsp *msg_ptr) { uint32_t sessionId = CSR_SESSION_ID_INVALID; QDF_STATUS status; - struct csr_roam_info roam_info; + struct csr_roam_info *roam_info; tpSirSmeProbeReqInd pProbeReqInd = (tpSirSmeProbeReqInd) msg_ptr; - qdf_mem_zero(&roam_info, sizeof(roam_info)); + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return; sme_debug("WPS PBC Probe request Indication from SME"); status = csr_roam_get_session_id_from_bssid(mac_ctx, &pProbeReqInd->bssid, &sessionId); if (QDF_IS_STATUS_SUCCESS(status)) { - qdf_mem_zero(&roam_info, sizeof(struct csr_roam_info)); - roam_info.u.pWPSPBCProbeReq = &pProbeReqInd->WPSPBCProbeReq; - csr_roam_call_callback(mac_ctx, sessionId, &roam_info, + roam_info->u.pWPSPBCProbeReq = &pProbeReqInd->WPSPBCProbeReq; + csr_roam_call_callback(mac_ctx, sessionId, roam_info, 0, eCSR_ROAM_WPS_PBC_PROBE_REQ_IND, eCSR_ROAM_RESULT_WPS_PBC_PROBE_REQ_IND); } + qdf_mem_free(roam_info); } #ifdef FEATURE_WLAN_DIAG_SUPPORT_CSR @@ -12502,16 +13085,17 @@ csr_roam_chk_lnk_wm_status_change_ntf(tpAniSirGlobal mac_ctx, struct csr_roam_session *session; uint32_t sessionId = CSR_SESSION_ID_INVALID; QDF_STATUS status; - struct csr_roam_info *roam_info_ptr = NULL; + struct csr_roam_info *roam_info; tSirSmeWmStatusChangeNtf *pStatusChangeMsg; - struct csr_roam_info roam_info; tSirSmeApNewCaps *pApNewCaps; eCsrRoamResult result = eCSR_ROAM_RESULT_NONE; tSirMacAddr Broadcastaddr = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; tSirSmeNewBssInfo *pNewBss; eRoamCmdStatus roamStatus = eCSR_ROAM_FAILED; - qdf_mem_zero(&roam_info, sizeof(roam_info)); + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return; pStatusChangeMsg = (tSirSmeWmStatusChangeNtf *) msg_ptr; switch (pStatusChangeMsg->statusChangeCode) { case eSIR_SME_IBSS_ACTIVE: @@ -12522,16 +13106,15 @@ csr_roam_chk_lnk_wm_status_change_ntf(tpAniSirGlobal mac_ctx, if (!session) { sme_err("session %d not found", sessionId); - return; + goto out; } session->connectState = eCSR_ASSOC_STATE_TYPE_IBSS_CONNECTED; if (session->pConnectBssDesc) { - qdf_mem_copy(&roam_info.bssid, + qdf_mem_copy(&roam_info->bssid, session->pConnectBssDesc->bssId, sizeof(struct qdf_mac_addr)); - roam_info.u.pConnectedProfile = + roam_info->u.pConnectedProfile = &session->connectedProfile; - roam_info_ptr = &roam_info; } else { sme_err("CSR: connected BSS is empty"); } @@ -12545,7 +13128,7 @@ csr_roam_chk_lnk_wm_status_change_ntf(tpAniSirGlobal mac_ctx, session = CSR_GET_SESSION(mac_ctx, sessionId); if (!session) { sme_err("session %d not found", sessionId); - return; + goto out; } session->connectState = eCSR_ASSOC_STATE_TYPE_IBSS_DISCONNECTED; @@ -12564,7 +13147,7 @@ csr_roam_chk_lnk_wm_status_change_ntf(tpAniSirGlobal mac_ctx, if (!session) { sme_err("session %d not found", sessionId); - return; + goto out; } /* update the connection state information */ pNewBss = &pStatusChangeMsg->statusChangeInfo.newBssInfo; @@ -12586,9 +13169,8 @@ csr_roam_chk_lnk_wm_status_change_ntf(tpAniSirGlobal mac_ctx, } result = eCSR_ROAM_RESULT_IBSS_COALESCED; roamStatus = eCSR_ROAM_IBSS_IND; - qdf_mem_copy(&roam_info.bssid, &pNewBss->bssId, + qdf_mem_copy(&roam_info->bssid, &pNewBss->bssId, sizeof(struct qdf_mac_addr)); - roam_info_ptr = &roam_info; /* This BSSID is the real BSSID, save it */ if (session->pConnectBssDesc) qdf_mem_copy(session->pConnectBssDesc->bssId, @@ -12618,7 +13200,8 @@ csr_roam_chk_lnk_wm_status_change_ntf(tpAniSirGlobal mac_ctx, mac_ctx->roam.curSubState[sessionId]))) { sme_warn("Calling csr_roam_disconnect_internal"); csr_roam_disconnect_internal(mac_ctx, sessionId, - eCSR_DISCONNECT_REASON_UNSPECIFIED); + eCSR_DISCONNECT_REASON_UNSPECIFIED, + eSIR_MAC_UNSPEC_FAILURE_REASON); } else { sme_warn("Skipping the new scan as CSR is in state: %s and sub-state: %s", mac_trace_getcsr_roam_state( @@ -12643,9 +13226,11 @@ csr_roam_chk_lnk_wm_status_change_ntf(tpAniSirGlobal mac_ctx, break; } /* end switch on statusChangeCode */ if (eCSR_ROAM_RESULT_NONE != result) { - csr_roam_call_callback(mac_ctx, sessionId, roam_info_ptr, 0, + csr_roam_call_callback(mac_ctx, sessionId, roam_info, 0, roamStatus, result); } +out: + qdf_mem_free(roam_info); } static void @@ -12654,9 +13239,8 @@ csr_roam_chk_lnk_ibss_new_peer_ind(tpAniSirGlobal mac_ctx, tSirSmeRsp *msg_ptr) struct csr_roam_session *session; uint32_t sessionId = CSR_SESSION_ID_INVALID; QDF_STATUS status; - struct csr_roam_info *roam_info_ptr = NULL; + struct csr_roam_info *roam_info = NULL; tSmeIbssPeerInd *pIbssPeerInd = (tSmeIbssPeerInd *) msg_ptr; - struct csr_roam_info roam_info; #ifdef FEATURE_WLAN_DIAG_SUPPORT_CSR host_log_ibss_pkt_type *pIbssLog; @@ -12670,7 +13254,6 @@ csr_roam_chk_lnk_ibss_new_peer_ind(tpAniSirGlobal mac_ctx, tSirSmeRsp *msg_ptr) } #endif /* FEATURE_WLAN_DIAG_SUPPORT_CSR */ - qdf_mem_zero(&roam_info, sizeof(roam_info)); sessionId = csr_find_ibss_session(mac_ctx); if (CSR_SESSION_ID_INVALID == sessionId) return; @@ -12687,41 +13270,37 @@ csr_roam_chk_lnk_ibss_new_peer_ind(tpAniSirGlobal mac_ctx, tSirSmeRsp *msg_ptr) sme_warn("CSR: connected BSS is empty"); goto callback_and_free; } - qdf_copy_macaddr(&roam_info.peerMac, &pIbssPeerInd->peer_addr); - qdf_mem_copy(&roam_info.bssid, session->pConnectBssDesc->bssId, + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + goto callback_and_free; + qdf_copy_macaddr(&roam_info->peerMac, &pIbssPeerInd->peer_addr); + qdf_mem_copy(&roam_info->bssid, session->pConnectBssDesc->bssId, sizeof(struct qdf_mac_addr)); if (pIbssPeerInd->mesgLen > sizeof(tSmeIbssPeerInd)) { - roam_info.pbFrames = qdf_mem_malloc((pIbssPeerInd->mesgLen - + roam_info->pbFrames = qdf_mem_malloc((pIbssPeerInd->mesgLen - sizeof(tSmeIbssPeerInd))); - if (NULL == roam_info.pbFrames) { + if (!roam_info->pbFrames) { status = QDF_STATUS_E_NOMEM; } else { status = QDF_STATUS_SUCCESS; - roam_info.nBeaconLength = pIbssPeerInd->mesgLen - + roam_info->nBeaconLength = pIbssPeerInd->mesgLen - sizeof(tSmeIbssPeerInd); - qdf_mem_copy(roam_info.pbFrames, - ((uint8_t *) pIbssPeerInd) + - sizeof(tSmeIbssPeerInd), - roam_info.nBeaconLength); + qdf_mem_copy(roam_info->pbFrames, + ((uint8_t *)pIbssPeerInd) + + sizeof(tSmeIbssPeerInd), + roam_info->nBeaconLength); } - roam_info.staId = (uint8_t) pIbssPeerInd->staId; - roam_info.pBssDesc = qdf_mem_malloc( + roam_info->staId = (uint8_t)pIbssPeerInd->staId; + roam_info->pBssDesc = qdf_mem_malloc( session->pConnectBssDesc->length); - if (NULL == roam_info.pBssDesc) { + if (!roam_info->pBssDesc) { status = QDF_STATUS_E_NOMEM; - if (roam_info.pbFrames) - qdf_mem_free(roam_info.pbFrames); - if (roam_info.pBssDesc) - qdf_mem_free(roam_info.pBssDesc); } else { status = QDF_STATUS_SUCCESS; - qdf_mem_copy(roam_info.pBssDesc, + qdf_mem_copy(roam_info->pBssDesc, session->pConnectBssDesc, session->pConnectBssDesc->length); - roam_info_ptr = &roam_info; } - } else { - roam_info_ptr = &roam_info; } if ((eCSR_ENCRYPT_TYPE_NONE == session->connectedProfile.EncryptionType)) { @@ -12735,16 +13314,15 @@ csr_roam_chk_lnk_ibss_new_peer_ind(tpAniSirGlobal mac_ctx, tSirSmeRsp *msg_ptr) callback_and_free: /* send up the sec type for the new peer */ - if (roam_info_ptr) - roam_info_ptr->u.pConnectedProfile = &session->connectedProfile; - csr_roam_call_callback(mac_ctx, sessionId, roam_info_ptr, 0, + if (roam_info) + roam_info->u.pConnectedProfile = &session->connectedProfile; + csr_roam_call_callback(mac_ctx, sessionId, roam_info, 0, eCSR_ROAM_CONNECT_STATUS_UPDATE, eCSR_ROAM_RESULT_IBSS_NEW_PEER); - if (roam_info_ptr) { - if (roam_info.pbFrames) - qdf_mem_free(roam_info.pbFrames); - if (roam_info.pBssDesc) - qdf_mem_free(roam_info.pBssDesc); + if (roam_info) { + qdf_mem_free(roam_info->pbFrames); + qdf_mem_free(roam_info->pBssDesc); + qdf_mem_free(roam_info); } } @@ -12753,14 +13331,16 @@ csr_roam_chk_lnk_ibss_peer_departed_ind(tpAniSirGlobal mac_ctx, tSirSmeRsp *msg_ptr) { uint32_t sessionId = CSR_SESSION_ID_INVALID; - struct csr_roam_info roam_info; + struct csr_roam_info *roam_info; tSmeIbssPeerInd *pIbssPeerInd; if (NULL == msg_ptr) { sme_err("IBSS peer ind. message is NULL"); return; } - qdf_mem_zero(&roam_info, sizeof(roam_info)); + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return; pIbssPeerInd = (tSmeIbssPeerInd *) msg_ptr; sessionId = csr_find_ibss_session(mac_ctx); if (CSR_SESSION_ID_INVALID != sessionId) { @@ -12779,12 +13359,13 @@ csr_roam_chk_lnk_ibss_peer_departed_ind(tpAniSirGlobal mac_ctx, } #endif /* FEATURE_WLAN_DIAG_SUPPORT_CSR */ sme_debug("CSR: Peer departed notification from LIM"); - roam_info.staId = (uint8_t) pIbssPeerInd->staId; - qdf_copy_macaddr(&roam_info.peerMac, &pIbssPeerInd->peer_addr); - csr_roam_call_callback(mac_ctx, sessionId, &roam_info, 0, + roam_info->staId = (uint8_t)pIbssPeerInd->staId; + qdf_copy_macaddr(&roam_info->peerMac, &pIbssPeerInd->peer_addr); + csr_roam_call_callback(mac_ctx, sessionId, roam_info, 0, eCSR_ROAM_CONNECT_STATUS_UPDATE, eCSR_ROAM_RESULT_IBSS_PEER_DEPARTED); } + qdf_mem_free(roam_info); } #ifdef FEATURE_WLAN_DIAG_SUPPORT_CSR @@ -12829,8 +13410,7 @@ csr_roam_chk_lnk_set_ctx_rsp(tpAniSirGlobal mac_ctx, tSirSmeRsp *msg_ptr) struct csr_roam_session *session; uint32_t sessionId = CSR_SESSION_ID_INVALID; QDF_STATUS status; - struct csr_roam_info *roam_info_ptr = NULL; - struct csr_roam_info roam_info; + struct csr_roam_info *roam_info; eCsrRoamResult result = eCSR_ROAM_RESULT_NONE; tSirSmeSetContextRsp *pRsp = (tSirSmeSetContextRsp *) msg_ptr; @@ -12840,11 +13420,14 @@ csr_roam_chk_lnk_set_ctx_rsp(tpAniSirGlobal mac_ctx, tSirSmeRsp *msg_ptr) return; } - qdf_mem_zero(&roam_info, sizeof(roam_info)); + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return; sessionId = pRsp->sessionId; session = CSR_GET_SESSION(mac_ctx, sessionId); if (!session) { sme_err("session %d not found", sessionId); + qdf_mem_free(roam_info); return; } #ifdef FEATURE_WLAN_DIAG_SUPPORT_CSR @@ -12863,7 +13446,7 @@ csr_roam_chk_lnk_set_ctx_rsp(tpAniSirGlobal mac_ctx, tSirSmeRsp *msg_ptr) session->connectedProfile.bssid); } if (eSIR_SME_SUCCESS == pRsp->statusCode) { - qdf_copy_macaddr(&roam_info.peerMac, &pRsp->peer_macaddr); + qdf_copy_macaddr(&roam_info->peerMac, &pRsp->peer_macaddr); /* Make sure we install the GTK before indicating to HDD as * authenticated. This is to prevent broadcast packets go out * after PTK and before GTK. @@ -12886,10 +13469,11 @@ csr_roam_chk_lnk_set_ctx_rsp(tpAniSirGlobal mac_ctx, tSirSmeRsp *msg_ptr) msg = qdf_mem_malloc(sizeof( struct sme_obss_ht40_scanind_msg)); - if (NULL == msg) { - sme_err("Malloc failed"); + if (!msg) { + qdf_mem_free(roam_info); return; } + msg->msg_type = eWNI_SME_HT40_OBSS_SCAN_IND; msg->length = sizeof(struct sme_obss_ht40_scanind_msg); @@ -12901,7 +13485,6 @@ csr_roam_chk_lnk_set_ctx_rsp(tpAniSirGlobal mac_ctx, tSirSmeRsp *msg_ptr) } else { result = eCSR_ROAM_RESULT_NONE; } - roam_info_ptr = &roam_info; } else { result = eCSR_ROAM_RESULT_FAILURE; sme_err( @@ -12911,7 +13494,7 @@ csr_roam_chk_lnk_set_ctx_rsp(tpAniSirGlobal mac_ctx, tSirSmeRsp *msg_ptr) MAC_ADDR_ARRAY(pRsp->peer_macaddr.bytes)); } /* keeping roam_id = 0 as nobody is using roam_id for set_key */ - csr_roam_call_callback(mac_ctx, sessionId, &roam_info, + csr_roam_call_callback(mac_ctx, sessionId, roam_info, 0, eCSR_ROAM_SET_KEY_COMPLETE, result); /* Indicate SME_QOS that the SET_KEY is completed, so that SME_QOS * can go ahead and initiate the TSPEC if any are pending @@ -12927,6 +13510,7 @@ csr_roam_chk_lnk_set_ctx_rsp(tpAniSirGlobal mac_ctx, tSirSmeRsp *msg_ptr) session->isPrevApInfoValid = false; } #endif + qdf_mem_free(roam_info); return; } @@ -12936,18 +13520,21 @@ csr_roam_chk_lnk_max_assoc_exceeded(tpAniSirGlobal mac_ctx, tSirSmeRsp *msg_ptr) { uint32_t sessionId = CSR_SESSION_ID_INVALID; tSmeMaxAssocInd *pSmeMaxAssocInd; - struct csr_roam_info roam_info; + struct csr_roam_info *roam_info; - qdf_mem_zero(&roam_info, sizeof(roam_info)); + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return; pSmeMaxAssocInd = (tSmeMaxAssocInd *) msg_ptr; sme_debug( "max assoc have been reached, new peer cannot be accepted"); sessionId = pSmeMaxAssocInd->sessionId; - roam_info.sessionId = sessionId; - qdf_copy_macaddr(&roam_info.peerMac, &pSmeMaxAssocInd->peer_mac); - csr_roam_call_callback(mac_ctx, sessionId, &roam_info, 0, + roam_info->sessionId = sessionId; + qdf_copy_macaddr(&roam_info->peerMac, &pSmeMaxAssocInd->peer_mac); + csr_roam_call_callback(mac_ctx, sessionId, roam_info, 0, eCSR_ROAM_INFRA_IND, eCSR_ROAM_RESULT_MAX_ASSOC_EXCEEDED); + qdf_mem_free(roam_info); } void csr_purge_pdev_all_ser_cmd_list_sync(tpAniSirGlobal mac_ctx, @@ -13101,7 +13688,7 @@ bool csr_roam_complete_roaming(tpAniSirGlobal pMac, uint32_t sessionId, * detinguish it. For missed beacon, LIM set reason to * be eSIR_BEACON_MISSED */ - if (eSIR_BEACON_MISSED == pSession->roamingStatusCode) { + if (eSIR_MAC_BEACON_MISSED == pSession->roamingStatusCode) { roamResult = eCSR_ROAM_RESULT_LOSTLINK; } else if (eCsrLostlinkRoamingDisassoc == pSession->roamingReason) { @@ -13169,11 +13756,11 @@ void csr_roam_roaming_timer_handler(void *pv) { tCsrTimerInfo *pInfo = (tCsrTimerInfo *) pv; tpAniSirGlobal pMac = pInfo->pMac; - uint32_t sessionId = pInfo->sessionId; - struct csr_roam_session *pSession = CSR_GET_SESSION(pMac, sessionId); + uint32_t vdev_id = pInfo->vdev_id; + struct csr_roam_session *pSession = CSR_GET_SESSION(pMac, vdev_id); if (!pSession) { - sme_err(" session %d not found ", sessionId); + sme_err(" session %d not found ", vdev_id); return; } @@ -13198,33 +13785,51 @@ void csr_roam_roaming_timer_handler(void *pv) void csr_roam_roaming_offload_timeout_handler(void *timer_data) { tCsrTimerInfo *timer_info = (tCsrTimerInfo *) timer_data; + struct scheduler_msg wma_msg = {0}; + struct roam_sync_timeout_timer_info *req; + QDF_STATUS status; if (timer_info) { - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - "LFR3:roaming offload timer expired, session: %d", - timer_info->sessionId); + sme_debug("LFR3:roaming offload timer expired, session: %d", + timer_info->vdev_id); + } else { - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_ERROR, - "Invalid Session"); + sme_err("Invalid Session"); + return; + } + + req = qdf_mem_malloc(sizeof(*req)); + if (!req) + return; + + req->vdev_id = timer_info->vdev_id; + wma_msg.type = WMA_ROAM_SYNC_TIMEOUT; + wma_msg.bodyptr = req; + + status = scheduler_post_message(QDF_MODULE_ID_SME, QDF_MODULE_ID_WMA, + QDF_MODULE_ID_WMA, &wma_msg); + if (!QDF_IS_STATUS_SUCCESS(status)) { + sme_err("Post roam offload timer fails, session id: %d", + timer_info->vdev_id); + qdf_mem_free(req); return; } - csr_roam_disconnect(timer_info->pMac, timer_info->sessionId, - eCSR_DISCONNECT_REASON_UNSPECIFIED); } -QDF_STATUS csr_roam_start_roaming_timer(tpAniSirGlobal pMac, uint32_t sessionId, +QDF_STATUS csr_roam_start_roaming_timer(tpAniSirGlobal pMac, + uint32_t vdev_id, uint32_t interval) { QDF_STATUS status; - struct csr_roam_session *pSession = CSR_GET_SESSION(pMac, sessionId); + struct csr_roam_session *pSession = CSR_GET_SESSION(pMac, vdev_id); if (!pSession) { - sme_err("session %d not found", sessionId); + sme_err("session %d not found", vdev_id); return QDF_STATUS_E_FAILURE; } sme_debug("csrScanStartRoamingTimer"); - pSession->roamingTimerInfo.sessionId = (uint8_t) sessionId; + pSession->roamingTimerInfo.vdev_id = (uint8_t)vdev_id; status = qdf_mc_timer_start(&pSession->hTimerRoaming, interval / QDF_MC_TIMER_TO_MS_UNIT); @@ -13232,10 +13837,10 @@ QDF_STATUS csr_roam_start_roaming_timer(tpAniSirGlobal pMac, uint32_t sessionId, } QDF_STATUS csr_roam_stop_roaming_timer(tpAniSirGlobal pMac, - uint32_t sessionId) + uint32_t vdev_id) { return qdf_mc_timer_stop - (&pMac->roam.roamSession[sessionId].hTimerRoaming); + (&pMac->roam.roamSession[vdev_id].hTimerRoaming); } void csr_roam_wait_for_key_time_out_handler(void *pv) @@ -13243,7 +13848,7 @@ void csr_roam_wait_for_key_time_out_handler(void *pv) tCsrTimerInfo *pInfo = (tCsrTimerInfo *) pv; tpAniSirGlobal pMac = pInfo->pMac; struct csr_roam_session *pSession = CSR_GET_SESSION(pMac, - pInfo->sessionId); + pInfo->vdev_id); QDF_STATUS status = QDF_STATUS_E_FAILURE; if (pSession == NULL) { @@ -13253,20 +13858,20 @@ void csr_roam_wait_for_key_time_out_handler(void *pv) sme_debug("WaitForKey timer expired in state: %s sub-state: %s", mac_trace_get_neighbour_roam_state(pMac->roam. - neighborRoamInfo[pInfo->sessionId]. + neighborRoamInfo[pInfo->vdev_id]. neighborRoamState), mac_trace_getcsr_roam_sub_state(pMac->roam. - curSubState[pInfo->sessionId])); + curSubState[pInfo->vdev_id])); spin_lock(&pMac->roam.roam_state_lock); - if (CSR_IS_WAIT_FOR_KEY(pMac, pInfo->sessionId)) { + if (CSR_IS_WAIT_FOR_KEY(pMac, pInfo->vdev_id)) { /* Change the substate so command queue is unblocked. */ - if (CSR_ROAM_SESSION_MAX > pInfo->sessionId) - pMac->roam.curSubState[pInfo->sessionId] = + if (CSR_ROAM_SESSION_MAX > pInfo->vdev_id) + pMac->roam.curSubState[pInfo->vdev_id] = eCSR_ROAM_SUBSTATE_NONE; spin_unlock(&pMac->roam.roam_state_lock); if (csr_neighbor_roam_is_handoff_in_progress(pMac, - pInfo->sessionId)) { + pInfo->vdev_id)) { /* * Enable heartbeat timer when hand-off is in progress * and Key Wait timer expired. @@ -13278,13 +13883,14 @@ void csr_roam_wait_for_key_time_out_handler(void *pv) } sme_debug("SME pre-auth state timeout"); - if (csr_is_conn_state_connected_infra(pMac, pInfo->sessionId)) { + if (csr_is_conn_state_connected_infra(pMac, pInfo->vdev_id)) { csr_roam_link_up(pMac, pSession->connectedProfile.bssid); status = sme_acquire_global_lock(&pMac->sme); if (QDF_IS_STATUS_SUCCESS(status)) { - csr_roam_disconnect(pMac, pInfo->sessionId, - eCSR_DISCONNECT_REASON_UNSPECIFIED); + csr_roam_disconnect(pMac, pInfo->vdev_id, + eCSR_DISCONNECT_REASON_UNSPECIFIED, + eSIR_MAC_KEY_TIMEOUT); sme_release_global_lock(&pMac->sme); } } else { @@ -13297,6 +13903,94 @@ void csr_roam_wait_for_key_time_out_handler(void *pv) } #ifdef WLAN_FEATURE_ROAM_OFFLOAD +QDF_STATUS csr_fast_reassoc(tHalHandle hal, struct csr_roam_profile *profile, + const tSirMacAddr bssid, int channel, + uint8_t vdev_id, const tSirMacAddr connected_bssid) +{ + QDF_STATUS status; + struct wma_roam_invoke_cmd *fastreassoc; + struct scheduler_msg msg = {0}; + tpAniSirGlobal mac_ctx = PMAC_STRUCT(hal); + struct csr_roam_session *session; + struct csr_roam_profile *roam_profile; + + session = CSR_GET_SESSION(mac_ctx, vdev_id); + if (!session || !session->pCurRoamProfile) { + sme_err("session %d not found", vdev_id); + return QDF_STATUS_E_FAILURE; + } + + if (!csr_is_conn_state_connected(mac_ctx, vdev_id)) { + sme_debug("Not in connected state, Roam Invoke not sent"); + return QDF_STATUS_E_FAILURE; + } + + roam_profile = session->pCurRoamProfile; + if (roam_profile->driver_disabled_roaming) { + sme_debug("roaming status in driver %d", + roam_profile->driver_disabled_roaming); + return QDF_STATUS_E_FAILURE; + } + fastreassoc = qdf_mem_malloc(sizeof(*fastreassoc)); + if (NULL == fastreassoc) { + sme_err("qdf_mem_malloc failed for fastreassoc"); + return QDF_STATUS_E_NOMEM; + } + /* if both are same then set the flag */ + if (!qdf_mem_cmp(connected_bssid, bssid, ETH_ALEN)) { + fastreassoc->is_same_bssid = true; + sme_debug("bssid same, bssid[%pM]", bssid); + } + fastreassoc->vdev_id = vdev_id; + fastreassoc->bssid[0] = bssid[0]; + fastreassoc->bssid[1] = bssid[1]; + fastreassoc->bssid[2] = bssid[2]; + fastreassoc->bssid[3] = bssid[3]; + fastreassoc->bssid[4] = bssid[4]; + fastreassoc->bssid[5] = bssid[5]; + + status = sme_get_beacon_frm(hal, profile, bssid, + &fastreassoc->frame_buf, + &fastreassoc->frame_len, + &channel); + + if (!channel) { + sme_err("channel retrieval from BSS desc fails!"); + qdf_mem_free(fastreassoc); + return QDF_STATUS_E_FAULT; + } + + fastreassoc->channel = channel; + if (QDF_STATUS_SUCCESS != status) { + sme_warn("sme_get_beacon_frm failed"); + fastreassoc->frame_buf = NULL; + fastreassoc->frame_len = 0; + } + + if (csr_is_auth_type_ese(mac_ctx->roam.roamSession[vdev_id]. + connectedProfile.AuthType)) { + sme_debug("Beacon is not required for ESE"); + if (fastreassoc->frame_len) { + qdf_mem_free(fastreassoc->frame_buf); + fastreassoc->frame_buf = NULL; + fastreassoc->frame_len = 0; + } + } + + msg.type = eWNI_SME_ROAM_INVOKE; + msg.reserved = 0; + msg.bodyptr = fastreassoc; + status = scheduler_post_message(QDF_MODULE_ID_SME, + QDF_MODULE_ID_PE, + QDF_MODULE_ID_PE, &msg); + if (QDF_STATUS_SUCCESS != status) { + sme_err("Not able to post ROAM_INVOKE_CMD message to PE"); + qdf_mem_free(fastreassoc); + } + + return status; +} + /** * csr_roam_roaming_offload_timer_action() - API to start/stop the timer * @mac_ctx: MAC Context @@ -13309,17 +14003,18 @@ void csr_roam_wait_for_key_time_out_handler(void *pv) * Return: None */ void csr_roam_roaming_offload_timer_action( - tpAniSirGlobal mac_ctx, uint32_t interval, uint8_t session_id, + tpAniSirGlobal mac_ctx, uint32_t interval, uint8_t vdev_id, uint8_t action) { struct csr_roam_session *csr_session = CSR_GET_SESSION(mac_ctx, - session_id); + vdev_id); + QDF_TIMER_STATE tstate; QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - ("LFR3: timer action %d, session %d, intvl %d"), - action, session_id, interval); + ("LFR3: timer action %d, vdev_id %d, intvl %d"), + action, vdev_id, interval); if (mac_ctx) { - csr_session = CSR_GET_SESSION(mac_ctx, session_id); + csr_session = CSR_GET_SESSION(mac_ctx, vdev_id); } else { QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_ERROR, ("LFR3: Invalid MAC Context")); @@ -13327,13 +14022,25 @@ void csr_roam_roaming_offload_timer_action( } if (!csr_session) { QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_ERROR, - ("LFR3: session %d not found"), session_id); + ("LFR3: session %d not found"), vdev_id); return; } - csr_session->roamingTimerInfo.sessionId = (uint8_t) session_id; - if (action == ROAMING_OFFLOAD_TIMER_START) - qdf_mc_timer_start(&csr_session->roaming_offload_timer, - interval / QDF_MC_TIMER_TO_MS_UNIT); + csr_session->roamingTimerInfo.vdev_id = (uint8_t)vdev_id; + + tstate = + qdf_mc_timer_get_current_state(&csr_session->roaming_offload_timer); + + if (action == ROAMING_OFFLOAD_TIMER_START) { + /* + * If timer is already running then re-start timer in order to + * process new ROAM_START with fresh timer. + */ + if (tstate == QDF_TIMER_STATE_RUNNING) + qdf_mc_timer_stop(&csr_session->roaming_offload_timer); + qdf_mc_timer_start(&csr_session->roaming_offload_timer, + interval / QDF_MC_TIMER_TO_MS_UNIT); + } + if (action == ROAMING_OFFLOAD_TIMER_STOP) qdf_mc_timer_stop(&csr_session->roaming_offload_timer); @@ -13347,18 +14054,18 @@ static QDF_STATUS csr_roam_start_wait_for_key_timer( #ifdef WLAN_DEBUG tpCsrNeighborRoamControlInfo pNeighborRoamInfo = &pMac->roam.neighborRoamInfo[pMac->roam.WaitForKeyTimerInfo. - sessionId]; + vdev_id]; #endif if (csr_neighbor_roam_is_handoff_in_progress(pMac, pMac->roam.WaitForKeyTimerInfo. - sessionId)) { + vdev_id)) { /* Disable heartbeat timer when hand-off is in progress */ sme_debug("disabling HB timer in state: %s sub-state: %s", mac_trace_get_neighbour_roam_state( pNeighborRoamInfo->neighborRoamState), mac_trace_getcsr_roam_sub_state( pMac->roam.curSubState[pMac->roam. - WaitForKeyTimerInfo.sessionId])); + WaitForKeyTimerInfo.vdev_id])); cfg_set_int(pMac, WNI_CFG_HEART_BEAT_THRESHOLD, 0); } sme_debug("csrScanStartWaitForKeyTimer"); @@ -13373,7 +14080,7 @@ QDF_STATUS csr_roam_stop_wait_for_key_timer(tpAniSirGlobal pMac) #ifdef WLAN_DEBUG tpCsrNeighborRoamControlInfo pNeighborRoamInfo = &pMac->roam.neighborRoamInfo[pMac->roam.WaitForKeyTimerInfo. - sessionId]; + vdev_id]; #endif sme_debug("WaitForKey timer stopped in state: %s sub-state: %s", @@ -13382,10 +14089,9 @@ QDF_STATUS csr_roam_stop_wait_for_key_timer(tpAniSirGlobal pMac) mac_trace_getcsr_roam_sub_state(pMac->roam. curSubState[pMac->roam. WaitForKeyTimerInfo. - sessionId])); + vdev_id])); if (csr_neighbor_roam_is_handoff_in_progress(pMac, - pMac->roam.WaitForKeyTimerInfo. - sessionId)) { + pMac->roam.WaitForKeyTimerInfo.vdev_id)) { /* * Enable heartbeat timer when hand-off is in progress * and Key Wait timer got stopped for some reason @@ -13443,22 +14149,26 @@ QDF_STATUS csr_roam_lost_link(tpAniSirGlobal pMac, uint32_t sessionId, tSirSmeDeauthInd *pDeauthIndMsg = NULL; tSirSmeDisassocInd *pDisassocIndMsg = NULL; eCsrRoamResult result = eCSR_ROAM_RESULT_LOSTLINK; - struct csr_roam_info roamInfo; struct csr_roam_session *pSession = CSR_GET_SESSION(pMac, sessionId); + struct csr_roam_info *roam_info; + bool from_ap = false; if (!pSession) { sme_err("session: %d not found", sessionId); return QDF_STATUS_E_FAILURE; } - qdf_mem_zero(&roamInfo, sizeof(struct csr_roam_info)); + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return QDF_STATUS_E_NOMEM; + if (eWNI_SME_DISASSOC_IND == type) { result = eCSR_ROAM_RESULT_DISASSOC_IND; pDisassocIndMsg = (tSirSmeDisassocInd *) pSirMsg; pSession->roamingStatusCode = pDisassocIndMsg->statusCode; pSession->joinFailStatusCode.reasonCode = pDisassocIndMsg->reasonCode; - - qdf_copy_macaddr(&roamInfo.peerMac, + from_ap = pDisassocIndMsg->from_ap; + qdf_copy_macaddr(&roam_info->peerMac, &pDisassocIndMsg->peer_macaddr); } else if (eWNI_SME_DEAUTH_IND == type) { result = eCSR_ROAM_RESULT_DEAUTH_IND; @@ -13466,8 +14176,8 @@ QDF_STATUS csr_roam_lost_link(tpAniSirGlobal pMac, uint32_t sessionId, pSession->roamingStatusCode = pDeauthIndMsg->statusCode; pSession->joinFailStatusCode.reasonCode = pDeauthIndMsg->reasonCode; - - qdf_copy_macaddr(&roamInfo.peerMac, + from_ap = pDeauthIndMsg->from_ap; + qdf_copy_macaddr(&roam_info->peerMac, &pDeauthIndMsg->peer_macaddr); } else { @@ -13475,14 +14185,12 @@ QDF_STATUS csr_roam_lost_link(tpAniSirGlobal pMac, uint32_t sessionId, result = eCSR_ROAM_RESULT_NONE; pSession->joinFailStatusCode.reasonCode = 1; } + mlme_set_discon_reason_n_from_ap(pMac->psoc, sessionId, from_ap, + pSession->joinFailStatusCode.reasonCode); - if (type == eWNI_SME_DISASSOC_IND || type == eWNI_SME_DEAUTH_IND) { - struct sir_peer_info_req req; + if (type == eWNI_SME_DISASSOC_IND || type == eWNI_SME_DEAUTH_IND) + csr_get_peer_rssi(pMac, sessionId, roam_info->peerMac); - req.sessionid = sessionId; - req.peer_macaddr = roamInfo.peerMac; - sme_get_peer_stats(pMac, req); - } csr_roam_call_callback(pMac, sessionId, NULL, 0, eCSR_ROAM_LOSTLINK_DETECTED, result); @@ -13492,25 +14200,26 @@ QDF_STATUS csr_roam_lost_link(tpAniSirGlobal pMac, uint32_t sessionId, status = csr_send_mb_deauth_cnf_msg(pMac, pDeauthIndMsg); /* prepare to tell HDD to disconnect */ - qdf_mem_zero(&roamInfo, sizeof(struct csr_roam_info)); - roamInfo.statusCode = (tSirResultCodes) pSession->roamingStatusCode; - roamInfo.reasonCode = pSession->joinFailStatusCode.reasonCode; + qdf_mem_zero(roam_info, sizeof(*roam_info)); + roam_info->statusCode = (tSirResultCodes) pSession->roamingStatusCode; + roam_info->reasonCode = pSession->joinFailStatusCode.reasonCode; if (eWNI_SME_DISASSOC_IND == type) { /* staMacAddr */ - qdf_copy_macaddr(&roamInfo.peerMac, + qdf_copy_macaddr(&roam_info->peerMac, &pDisassocIndMsg->peer_macaddr); - roamInfo.staId = (uint8_t) pDisassocIndMsg->staId; - roamInfo.reasonCode = pDisassocIndMsg->reasonCode; + roam_info->staId = (uint8_t)pDisassocIndMsg->staId; + roam_info->reasonCode = pDisassocIndMsg->reasonCode; } else if (eWNI_SME_DEAUTH_IND == type) { /* staMacAddr */ - qdf_copy_macaddr(&roamInfo.peerMac, + qdf_copy_macaddr(&roam_info->peerMac, &pDeauthIndMsg->peer_macaddr); - roamInfo.staId = (uint8_t) pDeauthIndMsg->staId; - roamInfo.reasonCode = pDeauthIndMsg->reasonCode; - roamInfo.rxRssi = pDeauthIndMsg->rssi; + roam_info->staId = (uint8_t)pDeauthIndMsg->staId; + roam_info->reasonCode = pDeauthIndMsg->reasonCode; + roam_info->rxRssi = pDeauthIndMsg->rssi; } - sme_debug("roamInfo.staId: %d", roamInfo.staId); + sme_debug("roamInfo.staId: %d", roam_info->staId); /* Dont initiate internal driver based roaming after disconnection*/ + qdf_mem_free(roam_info); return status; } @@ -15002,6 +15711,70 @@ csr_roam_diag_set_pmkid(struct csr_roam_session *pSession) } #endif /* FEATURE_WLAN_DIAG_SUPPORT_CSR */ +#ifdef WLAN_FEATURE_ROAM_OFFLOAD +/** + * csr_update_session_psk_pmk - API to update PMK in csr session + * @pSession: pointer to session + * @pmksa: pointer to PMKSA struct + * + * Return : None + */ +static void +csr_update_session_psk_pmk(struct csr_roam_session *session, + tPmkidCacheInfo *pmksa) +{ + /* For SAE authentication, pmk will be sent over the + * set PMKSA vendor command. The set PMKSA command is sent + * after SAE authentication is complete, before association + * completion itself. So csr_roam_session will not be having + * any parameters at this point. This pmk received is not + * updated to csr session and when RSO update command is sent, + * empty pmk will be sent, resulting in SAE roming failure. So + * copy the pmk into csr session so that correct pmk will be + * sent in RSO command. + */ + + qdf_mem_copy(session->psk_pmk, pmksa->pmk, pmksa->pmk_len); + session->pmk_len = pmksa->pmk_len; +} +#else +static inline void +csr_update_session_psk_pmk(struct csr_roam_session *session, + tPmkidCacheInfo *pmksa) +{} +#endif + +#if defined(WLAN_SAE_SINGLE_PMK) && defined(WLAN_FEATURE_ROAM_OFFLOAD) +/** + * csr_update_sae_single_pmk_info - API to update Single PMK Info in csr session + * @pSession: pointer to session + * @pmksa: pointer to PMKSA struct + * + * Return : None + */ +static void +csr_update_sae_single_pmk_info(struct csr_roam_session *session, + tPmkidCacheInfo *pmksa) +{ + if (!session || !session->pCurRoamProfile || !pmksa) { + sme_debug("Invalid session, current profile or pmksa"); + return; + } + + if (session->pCurRoamProfile->AuthType.authType[0] == + eCSR_AUTH_TYPE_SAE && session->single_pmk_info.sae_single_pmk_ap) { + qdf_mem_copy(session->single_pmk_info.pmk_info.pmk, + pmksa->pmk, pmksa->pmk_len); + session->single_pmk_info.pmk_info.pmk_len = pmksa->pmk_len; + } +} +#else +static inline void +csr_update_sae_single_pmk_info(struct csr_roam_session *session, + tPmkidCacheInfo *pmksa) +{ +} +#endif /** * csr_update_pmk_cache - API to update PMK cache * @pSession: pointer to session @@ -15033,9 +15806,13 @@ static void csr_update_pmk_cache(struct csr_roam_session *session, session->PmkidCacheInfo[cache_idx].PMKID, pmksa->PMKID, CSR_RSN_PMKID_SIZE); - if (pmksa->pmk_len) + if (pmksa->pmk_len) { qdf_mem_copy(session->PmkidCacheInfo[cache_idx].pmk, - pmksa->pmk, pmksa->pmk_len); + pmksa->pmk, pmksa->pmk_len); + + csr_update_session_psk_pmk(session, pmksa); + csr_update_sae_single_pmk_info(session, pmksa); + } session->PmkidCacheInfo[cache_idx].pmk_len = pmksa->pmk_len; @@ -15113,6 +15890,50 @@ static void csr_mem_zero_psk_pmk(struct csr_roam_session *session) } #endif +#if defined(WLAN_SAE_SINGLE_PMK) && defined(WLAN_FEATURE_ROAM_OFFLOAD) +void csr_clear_sae_single_pmk(tpAniSirGlobal pMac, uint8_t vdev_id, + tPmkidCacheInfo *pmk_cache) +{ + struct csr_roam_session *session = CSR_GET_SESSION(pMac, vdev_id); + tPmkidCacheInfo *pmk_to_del; + uint8_t i; + + if (!session) { + sme_err("session %d not found", vdev_id); + return; + } + + if (!pmk_cache) { + sme_debug("Flush sae_single_pmk info"); + qdf_mem_zero(&session->single_pmk_info.pmk_info, + sizeof(session->single_pmk_info.pmk_info)); + return; + } + + for (i = 0; i < session->NumPmkidCache; i++) { + pmk_to_del = &session->PmkidCacheInfo[i]; + if (qdf_is_macaddr_equal(&pmk_cache->BSSID, + &pmk_to_del->BSSID)) { + sme_debug("Match found BSSID: " MAC_ADDRESS_STR " to cached BSSID:" + MAC_ADDRESS_STR, + MAC_ADDR_ARRAY(pmk_cache->BSSID.bytes), + MAC_ADDR_ARRAY(pmk_to_del->BSSID.bytes)); + if (pmk_to_del->pmk_len != + session->single_pmk_info.pmk_info.pmk_len) { + sme_debug("Invalid pmk len"); + return; + } else if (!qdf_mem_cmp( + &session->single_pmk_info.pmk_info.pmk, + pmk_to_del->pmk, pmk_to_del->pmk_len)) { + sme_debug("Clear sae_single_pmk info"); + qdf_mem_zero(&session->single_pmk_info.pmk_info, + sizeof(session->single_pmk_info.pmk_info)); + } + } + } +} +#endif + QDF_STATUS csr_roam_del_pmkid_from_cache(tpAniSirGlobal pMac, uint32_t sessionId, tPmkidCacheInfo *pmksa, @@ -15140,12 +15961,15 @@ QDF_STATUS csr_roam_del_pmkid_from_cache(tpAniSirGlobal pMac, /* Flush the entire cache */ qdf_mem_zero(pSession->PmkidCacheInfo, sizeof(tPmkidCacheInfo) * CSR_MAX_PMKID_ALLOWED); + csr_clear_sae_single_pmk(pMac, sessionId, NULL); pSession->NumPmkidCache = 0; pSession->curr_cache_idx = 0; csr_mem_zero_psk_pmk(pSession); return QDF_STATUS_SUCCESS; } + csr_clear_sae_single_pmk(pMac, sessionId, pmksa); + /* !flush_cache - so look up in the cache */ for (Index = 0; Index < CSR_MAX_PMKID_ALLOWED; Index++) { cached_pmksa = &pSession->PmkidCacheInfo[Index]; @@ -15575,10 +16399,6 @@ static void csr_set_mgmt_enc_type(struct csr_roam_profile *profile, tDot11fBeaconIEs *ies, tSirSmeJoinReq *csr_join_req) { - sme_debug("mgmt encryption type %d MFPe %d MFPr %d", - profile->mgmt_encryption_type, - profile->MFPEnabled, profile->MFPRequired); - if (profile->MFPEnabled) csr_join_req->MgmtEncryptionType = profile->mgmt_encryption_type; @@ -15629,9 +16449,10 @@ static void csr_update_fils_connection_info(struct csr_roam_profile *profile, #ifdef WLAN_FEATURE_SAE /* - * csr_update_sae_config: Copy SAE info to join request - * @profile: pointer to profile + * csr_update_sae_config() - Copy SAE info to join request * @csr_join_req: csr join request + * @mac: mac context + * @session: sme session * * Return: None */ @@ -15647,9 +16468,11 @@ static void csr_update_sae_config(tSirSmeJoinReq *csr_join_req, csr_join_req->sae_pmk_cached = csr_lookup_pmkid_using_bssid(mac, session, &pmkid_cache, &index); - sme_debug("pmk_cached %d for BSSID=" MAC_ADDRESS_STR, - csr_join_req->sae_pmk_cached, - MAC_ADDR_ARRAY(csr_join_req->bssDescription.bssId)); + if (!csr_join_req->sae_pmk_cached) + return; + + sme_debug("Found for BSSID=" QDF_MAC_ADDR_STR, + QDF_MAC_ADDR_ARRAY(csr_join_req->bssDescription.bssId)); } #else static void csr_update_sae_config(tSirSmeJoinReq *csr_join_req, @@ -15698,42 +16521,6 @@ static uint8_t csr_get_nss_supported_by_sta_and_ap(tDot11fIEVHTCaps *vht_caps, return 1; } -/** - * csr_dump_vendor_ies() - Dumps all the vendor IEs - * @ie: ie buffer - * @ie_len: length of ie buffer - * - * This function dumps the vendor IEs present in the AP's IE buffer - * - * Return: none - */ -static -void csr_dump_vendor_ies(uint8_t *ie, uint16_t ie_len) -{ - int32_t left = ie_len; - uint8_t *ptr = ie; - uint8_t elem_id, elem_len; - - while (left >= 2) { - elem_id = ptr[0]; - elem_len = ptr[1]; - left -= 2; - if (elem_len > left) { - sme_err("Invalid IEs eid: %d elem_len: %d left: %d", - elem_id, elem_len, left); - return; - } - if (elem_id == SIR_MAC_EID_VENDOR) { - sme_debug("Dumping Vendor IE of len %d", elem_len); - QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_PE, - QDF_TRACE_LEVEL_DEBUG, - &ptr[2], elem_len); - } - left -= elem_len; - ptr += (elem_len + 2); - } -} - /** * csr_check_vendor_ap_3_present() - Check if Vendor AP 3 is present * @mac_ctx: Pointer to Global MAC structure @@ -15789,6 +16576,58 @@ static bool csr_enable_twt(tpAniSirGlobal mac_ctx, tDot11fBeaconIEs *ie) return false; } +#ifdef WLAN_ADAPTIVE_11R +/** + * csr_get_adaptive_11r_enabled() - Function to check if adaptive 11r + * ini is enabled or disabled + * @mac: pointer to mac context + * + * Return: true if adaptive 11r is enabled + */ +static bool +csr_get_adaptive_11r_enabled(tpAniSirGlobal mac) +{ + return mac->roam.configParam.enable_adaptive_11r; +} +#else +static inline bool +csr_get_adaptive_11r_enabled(tpAniSirGlobal mac) +{ + return false; +} +#endif + +#if defined(WLAN_SAE_SINGLE_PMK) && defined(WLAN_FEATURE_ROAM_OFFLOAD) +/** + * csr_update_sae_single_pmk_ap_cap() - Function to update sae single pmk ap ie + * @session: scr session + * @akm: AKM type + * @config_param: csr config + * @bss_description: bss description + * + * Return: true if sae single pmk feature is enabled + */ +static void +csr_update_sae_single_pmk_ap_cap(struct csr_roam_session *session, + eCsrAuthType akm, + struct csr_config *config_param, + tSirBssDescription *bss_description) +{ + if (akm == eCSR_AUTH_TYPE_SAE && + config_param->sae_single_pmk_feature_enabled) + session->single_pmk_info.sae_single_pmk_ap = + bss_description->sae_single_pmk_ap; +} +#else +static inline void +csr_update_sae_single_pmk_ap_cap(struct csr_roam_session *session, + eCsrAuthType akm, + struct csr_config *config_param, + tSirBssDescription *bss_description) +{ +} +#endif + /** * The communication between HDD and LIM is thru mailbox (MB). * Both sides will access the data structure "tSirSmeJoinReq". @@ -15828,6 +16667,9 @@ QDF_STATUS csr_send_join_req_msg(tpAniSirGlobal pMac, uint32_t sessionId, struct vdev_type_nss *vdev_type_nss; struct action_oui_search_attr vendor_ap_search_attr; tDot11fIEVHTCaps *vht_caps = NULL; + struct wlan_objmgr_vdev *vdev; + struct vdev_mlme_priv_obj *vdev_mlme; + eCsrAuthType akm; if (!pSession) { sme_err("session %d not found", sessionId); @@ -15908,13 +16750,14 @@ QDF_STATUS csr_send_join_req_msg(tpAniSirGlobal pMac, uint32_t sessionId, } qdf_mem_copy(&csr_join_req->selfMacAddr, &pSession->selfMacAddr, sizeof(tSirMacAddr)); - sme_err("vdevid-%d: Connecting to ssid:%.*s bssid: "MAC_ADDRESS_STR" rssi: %d channel: %d country_code: %c%c", - sessionId, csr_join_req->ssId.length, - csr_join_req->ssId.ssId, - MAC_ADDR_ARRAY(pBssDescription->bssId), - pBssDescription->rssi, pBssDescription->channelId, - pMac->scan.countryCodeCurrent[0], - pMac->scan.countryCodeCurrent[1]); + sme_nofl_info("vdev-%d: Connecting to %.*s " MAC_ADDRESS_STR + " rssi: %d channel: %d CC: %c%c", + sessionId, csr_join_req->ssId.length, + csr_join_req->ssId.ssId, + MAC_ADDR_ARRAY(pBssDescription->bssId), + pBssDescription->rssi, pBssDescription->channelId, + pMac->scan.countryCodeCurrent[0], + pMac->scan.countryCodeCurrent[1]); /* bsstype */ dwTmp = csr_translate_bsstype_to_mac_type (pProfile->BSSType); @@ -15924,6 +16767,13 @@ QDF_STATUS csr_send_join_req_msg(tpAniSirGlobal pMac, uint32_t sessionId, csr_translate_to_wni_cfg_dot11_mode(pMac, pSession->bssParams. uCfgDot11Mode); + akm = pProfile->negotiatedAuthType; + csr_join_req->akm = csr_convert_csr_to_ani_akm_type(akm); + + csr_update_sae_single_pmk_ap_cap(pSession, akm, + &pMac->roam.configParam, + pBssDescription); + if (pBssDescription->channelId <= 14 && false == pMac->roam.configParam.enableVhtFor24GHz && WNI_CFG_DOT11_MODE_11AC == ucDot11Mode) { @@ -15959,10 +16809,6 @@ QDF_STATUS csr_send_join_req_msg(tpAniSirGlobal pMac, uint32_t sessionId, ieLen = csr_get_ielen_from_bss_description(pBssDescription); - /* Dump the Vendor Specific IEs*/ - csr_dump_vendor_ies((uint8_t *)&pBssDescription->ieFields[0], - ieLen); - /* Fill the Vendor AP search params */ vendor_ap_search_attr.ie_data = (uint8_t *)&pBssDescription->ieFields[0]; @@ -15978,6 +16824,24 @@ QDF_STATUS csr_send_join_req_msg(tpAniSirGlobal pMac, uint32_t sessionId, vendor_ap_search_attr.enable_5g = IS_5G_CH(pBssDescription->channelId); + is_vendor_ap_present = ucfg_action_oui_search(pMac->psoc, + &vendor_ap_search_attr, + ACTION_OUI_DISABLE_AGGRESSIVE_EDCA); + + vdev = wlan_objmgr_get_vdev_by_id_from_psoc(pMac->psoc, + sessionId, + WLAN_LEGACY_MAC_ID); + if (vdev) { + vdev_mlme = wlan_vdev_mlme_get_priv_obj(vdev); + if (vdev_mlme) { + if (is_vendor_ap_present) + vdev_mlme->follow_ap_edca = true; + else + vdev_mlme->follow_ap_edca = false; + } + wlan_objmgr_vdev_release_ref(vdev, WLAN_LEGACY_MAC_ID); + } + is_vendor_ap_present = ucfg_action_oui_search(pMac->psoc, &vendor_ap_search_attr, @@ -16058,10 +16922,6 @@ QDF_STATUS csr_send_join_req_msg(tpAniSirGlobal pMac, uint32_t sessionId, csr_join_req->nss = pSession->nss; csr_join_req->nss_forced_1x1 = pSession->nss_forced_1x1; csr_join_req->dot11mode = (uint8_t) ucDot11Mode; - sme_debug("dot11mode=%d, uCfgDot11Mode=%d nss=%d", - csr_join_req->dot11mode, - pSession->bssParams.uCfgDot11Mode, - csr_join_req->nss); #ifdef FEATURE_WLAN_MCC_TO_SCC_SWITCH csr_join_req->cc_switch_mode = pMac->roam.configParam.cc_switch_mode; @@ -16071,9 +16931,6 @@ QDF_STATUS csr_send_join_req_msg(tpAniSirGlobal pMac, uint32_t sessionId, csr_join_req->cbMode = (uint8_t) pSession->bssParams.cbMode; csr_join_req->force_24ghz_in_ht20 = pProfile->force_24ghz_in_ht20; - sme_debug("CSR PERSONA: %d CSR CbMode: %d force 24gh ht20 %d", - pProfile->csrPersona, pSession->bssParams.cbMode, - csr_join_req->force_24ghz_in_ht20); pSession->uapsd_mask = pProfile->uapsd_mask; status = csr_get_rate_set(pMac, pProfile, @@ -16106,6 +16963,16 @@ QDF_STATUS csr_send_join_req_msg(tpAniSirGlobal pMac, uint32_t sessionId, csr_join_req->operationalRateSet.numRates = 0; csr_join_req->extendedRateSet.numRates = 0; } + + if (pBssDescription->adaptive_11r_ap) + pSession->is_adaptive_11r_connection = + csr_get_adaptive_11r_enabled(pMac); + else + pSession->is_adaptive_11r_connection = false; + + csr_join_req->is_adaptive_11r_connection = + pSession->is_adaptive_11r_connection; + /* rsnIE */ if (csr_is_profile_wpa(pProfile)) { /* Insert the Wpa IE into the join request */ @@ -16674,7 +17541,6 @@ QDF_STATUS csr_send_join_req_msg(tpAniSirGlobal pMac, uint32_t sessionId, } if (pProfile->csrPersona == QDF_STA_MODE) { - sme_debug("Invoking packetdump register API"); wlan_register_txrx_packetdump(); packetdump_timer_status = qdf_mc_timer_start( &pMac->roam.packetdump_timer, @@ -16682,15 +17548,13 @@ QDF_STATUS csr_send_join_req_msg(tpAniSirGlobal pMac, uint32_t sessionId, QDF_MC_TIMER_TO_SEC_UNIT)/ QDF_MC_TIMER_TO_MS_UNIT); if (!QDF_IS_STATUS_SUCCESS(packetdump_timer_status)) - sme_err("cannot start packetdump timer status: %d", - packetdump_timer_status); + sme_debug("cannot start packetdump timer status: %d", + packetdump_timer_status); } #ifndef WLAN_MDM_CODE_REDUCTION_OPT if (eWNI_SME_JOIN_REQ == messageType) { /* Notify QoS module that join happening */ pSession->join_bssid_count++; - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - "BSSID Count: %d", pSession->join_bssid_count); sme_qos_csr_event_ind(pMac, (uint8_t) sessionId, SME_QOS_CSR_JOIN_REQ, NULL); } else if (eWNI_SME_REASSOC_REQ == messageType) @@ -17158,6 +18022,21 @@ QDF_STATUS csr_send_assoc_ind_to_upper_layer_cnf_msg(tpAniSirGlobal pMac, pMsg->vht_caps = pAssocInd->VHTCaps; pMsg->capability_info = pAssocInd->capability_info; pMsg->he_caps_present = pAssocInd->he_caps_present; + if (pAssocInd->assocReqPtr) { + if (pAssocInd->assocReqLength < MAX_ASSOC_REQ_IE_LEN) { + pMsg->ies = qdf_mem_malloc( + pAssocInd->assocReqLength); + if (pMsg->ies == NULL) { + qdf_mem_free(pMsg); + return QDF_STATUS_E_NOMEM; + } + pMsg->ies_len = pAssocInd->assocReqLength; + qdf_mem_copy(pMsg->ies , pAssocInd->assocReqPtr, + pMsg->ies_len); + } else { + sme_err("Assoc Ie length is too long"); + } + } msgQ.type = eWNI_SME_UPPER_LAYER_ASSOC_CNF; msgQ.bodyptr = pMsg; msgQ.bodyval = 0; @@ -17438,19 +18317,23 @@ static QDF_STATUS csr_roam_session_opened(tpAniSirGlobal pMac, uint32_t sessionId) { QDF_STATUS status = QDF_STATUS_SUCCESS; - struct csr_roam_info roam_info; + struct csr_roam_info *roam_info; - qdf_mem_zero(&roam_info, sizeof(struct csr_roam_info)); + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return QDF_STATUS_E_NOMEM; if (QDF_IS_STATUS_ERROR(qdf_status)) { - status = csr_roam_call_callback(pMac, sessionId, &roam_info, 0, + status = csr_roam_call_callback(pMac, sessionId, roam_info, 0, eCSR_ROAM_SESSION_OPENED, eCSR_ROAM_RESULT_FAILURE); } else { - status = csr_roam_call_callback(pMac, sessionId, &roam_info, 0, + status = csr_roam_call_callback(pMac, sessionId, roam_info, 0, eCSR_ROAM_SESSION_OPENED, eCSR_ROAM_RESULT_SUCCESS); } + + qdf_mem_free(roam_info); return status; } @@ -17964,6 +18847,8 @@ void csr_cleanup_session(tpAniSirGlobal pMac, uint32_t sessionId) csr_flush_roam_scan_chan_lists(pMac, sessionId); csr_roam_free_connect_profile(&pSession->connectedProfile); csr_roam_free_connected_info(pMac, &pSession->connectedInfo); + csr_roam_free_connected_info(pMac, + &pSession->prev_assoc_ap_info); qdf_mc_timer_destroy(&pSession->hTimerRoaming); qdf_mc_timer_destroy(&pSession->roaming_offload_timer); #ifdef FEATURE_WLAN_BTAMP_UT_RF @@ -17980,10 +18865,8 @@ QDF_STATUS csr_roam_close_session(tpAniSirGlobal mac_ctx, QDF_STATUS status = QDF_STATUS_SUCCESS; struct csr_roam_session *session; - if (!CSR_IS_SESSION_VALID(mac_ctx, session_id)) { - sme_debug("session %d not found", session_id); + if (!CSR_IS_SESSION_VALID(mac_ctx, session_id)) return QDF_STATUS_E_INVAL; - } session = CSR_GET_SESSION(mac_ctx, session_id); /* Vdev going down stop roaming */ @@ -18014,10 +18897,8 @@ static void csr_init_session(tpAniSirGlobal pMac, uint32_t sessionId) { struct csr_roam_session *pSession = CSR_GET_SESSION(pMac, sessionId); - if (!pSession) { - sme_err("session %d not found", sessionId); + if (!pSession) return; - } pSession->sessionActive = false; pSession->sessionId = CSR_SESSION_ID_INVALID; @@ -18028,6 +18909,8 @@ static void csr_init_session(tpAniSirGlobal pMac, uint32_t sessionId) csr_free_roam_profile(pMac, sessionId); csr_roam_free_connect_profile(&pSession->connectedProfile); csr_roam_free_connected_info(pMac, &pSession->connectedInfo); + csr_roam_free_connected_info(pMac, + &pSession->prev_assoc_ap_info); csr_free_connect_bss_desc(pMac, sessionId); qdf_mem_zero(&pSession->selfMacAddr, sizeof(struct qdf_mac_addr)); if (pSession->pWpaRsnReqIE) { @@ -18698,6 +19581,22 @@ QDF_STATUS csr_get_statistics(tpAniSirGlobal pMac, #endif /* QCA_SUPPORT_CP_STATS */ #ifdef WLAN_FEATURE_ROAM_OFFLOAD +QDF_STATUS csr_roam_send_rso_cmd(tpAniSirGlobal mac_ctx, uint8_t session_id, + tSirRoamOffloadScanReq *request_buf) +{ + QDF_STATUS status; + + request_buf->message_type = eWNI_SME_ROAM_SCAN_OFFLOAD_REQ; + request_buf->length = sizeof(*request_buf); + + status = umac_send_mb_message_to_mac(request_buf); + if (status != QDF_STATUS_SUCCESS) { + sme_err("Send RSO from CSR failed"); + return status; + } + return QDF_STATUS_SUCCESS; +} + /** * csr_roam_set_key_mgmt_offload() - enable/disable key mgmt offload * @mac_ctx: mac context. @@ -18753,10 +19652,73 @@ void csr_update_roam_scan_ese_params(tSirRoamOffloadScanReq *req_buf, } } #else -static inline -void csr_update_roam_scan_ese_params(tSirRoamOffloadScanReq *req_buf, - struct csr_roam_session *session) +static inline +void csr_update_roam_scan_ese_params(tSirRoamOffloadScanReq *req_buf, + struct csr_roam_session *session) +{ +} +#endif + +#ifdef WLAN_ADAPTIVE_11R +static void +csr_update_roam_req_adaptive_11r(struct csr_roam_session *session, + tSirRoamOffloadScanReq *req_buf) +{ + req_buf->is_adaptive_11r_connection = + session->is_adaptive_11r_connection; +} +#else +static void +csr_update_roam_req_adaptive_11r(struct csr_roam_session *session, + tSirRoamOffloadScanReq *req_buf) +{ + req_buf->is_adaptive_11r_connection = false; +} +#endif + +#if defined(WLAN_SAE_SINGLE_PMK) && defined(WLAN_FEATURE_ROAM_OFFLOAD) +/** + * csr_fill_sae_single_pmk_info() - updates req msg with sae single pmk info + * @mac_ctx: Mac context + * @req_buf: out param, roam offload scan request packet + * @session: csr session + * + * Return: true in case of success + */ +static bool +csr_fill_sae_single_pmk_info(tpAniSirGlobal mac_ctx, + tSirRoamOffloadScanReq *req_buf, + struct csr_roam_session *session) +{ + if (!mac_ctx || !req_buf) { + sme_debug("Invalid session or req buff"); + return false; + } + + if (session->single_pmk_info.pmk_info.pmk_len && + session->single_pmk_info.sae_single_pmk_ap && + mac_ctx->roam.configParam.sae_single_pmk_feature_enabled) { + /* Update sae same pmk info in rso */ + qdf_mem_copy(req_buf->PSK_PMK, + session->single_pmk_info.pmk_info.pmk, + sizeof(req_buf->PSK_PMK)); + req_buf->pmk_len = session->single_pmk_info.pmk_info.pmk_len; + + req_buf->is_sae_single_pmk = + session->single_pmk_info.sae_single_pmk_ap; + + return true; + } + + return false; +} +#else +static bool +csr_fill_sae_single_pmk_info(tpAniSirGlobal mac_ctx, + tSirRoamOffloadScanReq *req_buf, + struct csr_roam_session *session) { + return false; } #endif @@ -18774,9 +19736,39 @@ csr_update_roam_scan_offload_request(tpAniSirGlobal mac_ctx, tSirRoamOffloadScanReq *req_buf, struct csr_roam_session *session) { - qdf_mem_copy(req_buf->PSK_PMK, session->psk_pmk, - sizeof(req_buf->PSK_PMK)); - req_buf->pmk_len = session->pmk_len; + tCsrNeighborRoamControlInfo *neighbor_roam_info; + uint32_t pmkid_modes = mac_ctx->roam.configParam.pmkid_modes; + + req_buf->RoamOffloadEnabled = csr_roamIsRoamOffloadEnabled(mac_ctx); + /* Roam Offload piggybacks upon the Roam Scan offload command. */ + if (!req_buf->RoamOffloadEnabled) { + sme_debug("LFR3: LFR3 INI is disabled"); + return; + } + + neighbor_roam_info = + &mac_ctx->roam.neighborRoamInfo[session->sessionId]; + req_buf->roam_triggers.vdev_id = session->sessionId; + req_buf->roam_triggers.trigger_bitmap = + neighbor_roam_info->cfgParams.roam_trigger_bitmap; + + req_buf->RoamKeyMgmtOffloadEnabled = session->RoamKeyMgmtOffloadEnabled; + req_buf->pmkid_modes.fw_okc = + (pmkid_modes & CFG_PMKID_MODES_OKC) ? 1 : 0; + req_buf->pmkid_modes.fw_pmksa_cache = + (pmkid_modes & CFG_PMKID_MODES_PMKSA_CACHING) ? 1 : 0; + + qdf_mem_copy(&req_buf->roam_params, + &mac_ctx->roam.configParam.roam_params, + sizeof(req_buf->roam_params)); + + /* Check whether to send psk_pmk or sae_single pmk info */ + if (!csr_fill_sae_single_pmk_info(mac_ctx, req_buf, session)) { + qdf_mem_copy(req_buf->PSK_PMK, session->psk_pmk, + sizeof(req_buf->PSK_PMK)); + req_buf->pmk_len = session->pmk_len; + } + req_buf->R0KH_ID_Length = session->ftSmeContext.r0kh_id_len; qdf_mem_copy(req_buf->R0KH_ID, session->ftSmeContext.r0kh_id, @@ -18798,6 +19790,8 @@ csr_update_roam_scan_offload_request(tpAniSirGlobal mac_ctx, req_buf->roam_force_rssi_trigger = mac_ctx->roam.configParam.roam_force_rssi_trigger; + csr_update_roam_req_adaptive_11r(session, req_buf); + /* fill bss load triggered roam related configs */ req_buf->bss_load_trig_enabled = mac_ctx->roam.configParam.enable_bss_load_roam_trigger; @@ -18806,7 +19800,58 @@ csr_update_roam_scan_offload_request(tpAniSirGlobal mac_ctx, req_buf->bss_load_config.bss_load_sample_time = mac_ctx->roam.configParam.bss_load_sample_time; req_buf->bss_load_config.vdev_id = session->sessionId; - + req_buf->bss_load_config.rssi_threshold_5ghz = + (mac_ctx->roam.configParam.bss_load_trigger_rssi_threshold_5ghz - + WMA_NOISE_FLOOR_DBM_DEFAULT); + req_buf->bss_load_config.rssi_threshold_5ghz &= 0x000000ff; + req_buf->bss_load_config.rssi_threshold_24ghz = + (mac_ctx->roam.configParam.bss_load_trigger_rssi_threshold_24ghz - + WMA_NOISE_FLOOR_DBM_DEFAULT); + req_buf->bss_load_config.rssi_threshold_24ghz &= 0x000000ff; + + req_buf->min_rssi_params[DEAUTH_MIN_RSSI].min_rssi = + (mac_ctx->roam.configParam.disconnect_roam_min_rssi - + WMA_NOISE_FLOOR_DBM_DEFAULT); + req_buf->min_rssi_params[DEAUTH_MIN_RSSI].min_rssi &= 0x000000ff; + req_buf->min_rssi_params[DEAUTH_MIN_RSSI].trigger_reason = + ROAM_TRIGGER_REASON_DEAUTH; + + req_buf->min_rssi_params[BMISS_MIN_RSSI].min_rssi = + (mac_ctx->roam.configParam.bmiss_roam_min_rssi - + WMA_NOISE_FLOOR_DBM_DEFAULT); + req_buf->min_rssi_params[BMISS_MIN_RSSI].min_rssi &= 0x000000ff; + req_buf->min_rssi_params[BMISS_MIN_RSSI].trigger_reason = + ROAM_TRIGGER_REASON_BMISS; + + req_buf->score_delta_param[IDLE_ROAM_TRIGGER].roam_score_delta = + mac_ctx->roam.configParam.idle_roam_score_delta; + req_buf->score_delta_param[IDLE_ROAM_TRIGGER].trigger_reason = + ROAM_TRIGGER_REASON_IDLE; + + req_buf->score_delta_param[BTM_ROAM_TRIGGER].roam_score_delta = + mac_ctx->roam.configParam.btm_roam_score_delta; + req_buf->score_delta_param[BTM_ROAM_TRIGGER].trigger_reason = + ROAM_TRIGGER_REASON_BTM; + + req_buf->disconnect_roam_params.enable = + mac_ctx->roam.configParam.enable_disconnect_roam_offload; + req_buf->disconnect_roam_params.vdev_id = session->sessionId; + + req_buf->idle_roam_params.vdev_id = session->sessionId; + req_buf->idle_roam_params.enable = + mac_ctx->roam.configParam.enable_idle_roam; + req_buf->idle_roam_params.conn_ap_rssi_delta = + mac_ctx->roam.configParam.idle_roam_rssi_delta; + req_buf->idle_roam_params.inactive_time = + mac_ctx->roam.configParam.idle_roam_inactive_time; + req_buf->idle_roam_params.data_pkt_count = + mac_ctx->roam.configParam.idle_data_packet_count; + req_buf->idle_roam_params.band = + mac_ctx->roam.configParam.idle_roam_band; + req_buf->idle_roam_params.conn_ap_min_rssi = + (mac_ctx->roam.configParam.idle_roam_min_rssi - + WMA_NOISE_FLOOR_DBM_DEFAULT); + req_buf->idle_roam_params.conn_ap_min_rssi &= 0x000000ff; if (wlan_cfg_get_int(mac_ctx, WNI_CFG_REASSOCIATION_FAILURE_TIMEOUT, (uint32_t *) &req_buf->ReassocFailureTimeout) @@ -18824,6 +19869,78 @@ csr_update_roam_scan_offload_request(tpAniSirGlobal mac_ctx, req_buf->AcUapsd.acvi_uapsd = SIR_UAPSD_GET(ACVI, session->uapsd_mask); req_buf->AcUapsd.acvo_uapsd = SIR_UAPSD_GET(ACVO, session->uapsd_mask); } + +#ifdef WLAN_FEATURE_FIPS +QDF_STATUS +csr_process_roam_pmkid_req_callback(tpAniSirGlobal mac_ctx, + uint8_t vdev_id, + struct roam_pmkid_req_event *src_lst) +{ + struct csr_roam_info *roam_info; + struct csr_roam_session *session = CSR_GET_SESSION(mac_ctx, vdev_id); + struct qdf_mac_addr *dst_list; + QDF_STATUS status; + uint32_t num_entries, i; + + if (!session) + return QDF_STATUS_E_NULL_VALUE; + + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return QDF_STATUS_E_NOMEM; + + num_entries = src_lst->num_entries; + for (i = 0; i < num_entries; i++) { + dst_list = &src_lst->ap_bssid[i]; + qdf_copy_macaddr(&roam_info->bssid, dst_list); + + status = csr_roam_call_callback(mac_ctx, vdev_id, roam_info, + 0, eCSR_ROAM_FIPS_PMK_REQUEST, + eCSR_ROAM_RESULT_NONE); + if (QDF_IS_STATUS_ERROR(status)) { + sme_err("%s: Trigger pmkid fallback failed", __func__); + qdf_mem_free(roam_info); + return status; + } + } + qdf_mem_free(roam_info); + + return QDF_STATUS_SUCCESS; +} + +QDF_STATUS +csr_roam_pmkid_req_callback(uint8_t vdev_id, + struct roam_pmkid_req_event *src_lst) +{ + QDF_STATUS status; + tpAniSirGlobal mac_ctx; + + mac_ctx = cds_get_context(QDF_MODULE_ID_PE); + if (!mac_ctx) { + sme_err("%s: NULL mac ptr", __func__); + QDF_ASSERT(0); + return -EINVAL; + } + + status = sme_acquire_global_lock(&mac_ctx->sme); + if (!QDF_IS_STATUS_SUCCESS(status)) { + sme_err("%s: Locking failed, bailing out", __func__); + return status; + } + + status = csr_process_roam_pmkid_req_callback(mac_ctx, vdev_id, + src_lst); + sme_release_global_lock(&mac_ctx->sme); + + return status; +} +#endif /* WLAN_FEATURE_FIPS */ +#else +static inline void +csr_update_roam_scan_offload_request(tpAniSirGlobal mac_ctx, + tSirRoamOffloadScanReq *req_buf, + struct csr_roam_session *session) +{} #endif /* WLAN_FEATURE_ROAM_OFFLOAD */ #if defined(WLAN_FEATURE_HOST_ROAM) || defined(WLAN_FEATURE_ROAM_OFFLOAD) @@ -18900,10 +20017,14 @@ csr_populate_roam_chan_list(tpAniSirGlobal mac_ctx, for (i = 0; i < src->numOfChannels; i++) { if (csr_is_channel_present_in_list(dst->ChannelCache, num_channels, - *ch_lst)) + *ch_lst)) { + ch_lst++; continue; - if (!csr_check_band_channel_match(band, *ch_lst)) + } + if (!csr_check_band_channel_match(band, *ch_lst)) { + ch_lst++; continue; + } /* Allow DFS channels only if the DFS roaming is enabled */ if ((!mac_ctx->roam.configParam.allowDFSChannelRoam || (mac_ctx->roam.configParam.sta_roam_policy.dfs_mode == @@ -19007,9 +20128,6 @@ csr_fetch_ch_lst_from_occupied_lst(tpAniSirGlobal mac_ctx, return; } - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - "Num of channels before filtering=%d", - mac_ctx->scan.occupiedChannels[session_id].numChannels); pld_get_wlan_unsafe_channel(qdf_ctx->dev, unsafe_chan, &unsafe_chan_cnt, sizeof(unsafe_chan)); @@ -19046,14 +20164,6 @@ csr_fetch_ch_lst_from_occupied_lst(tpAniSirGlobal mac_ctx, } req_buf->ConnectedNetwork.ChannelCache[num_channels++] = *ch_lst; - if (*ch_lst) - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - "DFSRoam=%d, ChnlState=%d, Chnl=%d, num_ch=%d", - mac_ctx->roam.configParam.allowDFSChannelRoam, - wlan_reg_get_channel_state(mac_ctx->pdev, - *ch_lst), - *ch_lst, - num_channels); ch_lst++; } req_buf->ConnectedNetwork.ChannelCount = num_channels; @@ -19191,13 +20301,47 @@ csr_add_ch_lst_from_roam_scan_list(tpAniSirGlobal mac_ctx, sme_err("Failed to copy channels to roam list"); return status; } - sme_debug("Added to roam chan list:"); sme_dump_chan_list(pref_chan_info); req_buf->ChannelCacheType = CHANNEL_LIST_DYNAMIC; return QDF_STATUS_SUCCESS; } +#ifdef WLAN_FEATURE_11W +/** + * csr_rso_command_fill_11w_params() - Fill the 11w related parameters + * into the roam buffer + * @mac_ctx: Global mac context buffer + * @rso_req: RSO command buffer to be filled + * + * Return: None + */ +static void +csr_rso_command_fill_11w_params(tpAniSirGlobal mac_ctx, + uint8_t session_id, + tSirRoamOffloadScanReq *rso_req) +{ + tSirRoamNetworkType *network_cfg = &rso_req->ConnectedNetwork; + tCsrRoamConnectedProfile session_connected_profile = + mac_ctx->roam.roamSession[session_id].connectedProfile; + tAniEdType group_mgmt_cipher; + + network_cfg->mfp_enabled = session_connected_profile.MFPEnabled; + group_mgmt_cipher = session_connected_profile.mgmt_encryption_type; + if (network_cfg->mfp_enabled) + network_cfg->gp_mgmt_cipher_suite = group_mgmt_cipher; + else + network_cfg->gp_mgmt_cipher_suite = eSIR_ED_NONE; +} + +#else +static inline +void csr_rso_command_fill_11w_params(tpAniSirGlobal mac_ctx, + uint8_t session_id, + tSirRoamOffloadScanReq *rso_req) +{} +#endif + /** * csr_create_roam_scan_offload_request() - init roam offload scan request * @@ -19289,10 +20433,9 @@ csr_create_roam_scan_offload_request(tpAniSirGlobal mac_ctx, connectedProfile.mcEncryptionType; /* Copy the RSN capabilities in roam offload request from session*/ req_buf->rsn_caps = session->rsn_caps; -#ifdef WLAN_FEATURE_11W - req_buf->ConnectedNetwork.mfp_enabled = - mac_ctx->roam.roamSession[session_id].connectedProfile.MFPEnabled; -#endif + + csr_rso_command_fill_11w_params(mac_ctx, session_id, req_buf); + req_buf->delay_before_vdev_stop = roam_info->cfgParams.delay_before_vdev_stop; req_buf->OpportunisticScanThresholdDiff = @@ -19314,8 +20457,15 @@ csr_create_roam_scan_offload_request(tpAniSirGlobal mac_ctx, roam_info->cfgParams.maxChannelScanTime; req_buf->EmptyRefreshScanPeriod = roam_info->cfgParams.emptyScanRefreshPeriod; + req_buf->roam_scan_inactivity_time = + roam_info->cfgParams.roam_scan_inactivity_time; + req_buf->roam_inactive_data_packet_count = + roam_info->cfgParams.roam_inactive_data_packet_count; + req_buf->roam_scan_period_after_inactivity = + roam_info->cfgParams.roam_scan_period_after_inactivity; req_buf->full_roam_scan_period = roam_info->cfgParams.full_roam_scan_period; + req_buf->RoamBmissFirstBcnt = roam_info->cfgParams.nRoamBmissFirstBcnt; req_buf->RoamBmissFinalBcnt = @@ -19325,13 +20475,6 @@ csr_create_roam_scan_offload_request(tpAniSirGlobal mac_ctx, qdf_mem_copy(&req_buf->mawc_roam_params, &mac_ctx->roam.configParam.csr_mawc_config, sizeof(req_buf->mawc_roam_params)); - sme_debug("MAWC:global=%d,roam=%d,traffic=%d,ap_rssi=%d,high=%d,low=%d", - req_buf->mawc_roam_params.mawc_enabled, - req_buf->mawc_roam_params.mawc_roam_enabled, - req_buf->mawc_roam_params.mawc_roam_traffic_threshold, - req_buf->mawc_roam_params.mawc_roam_ap_rssi_threshold, - req_buf->mawc_roam_params.mawc_roam_rssi_high_adjust, - req_buf->mawc_roam_params.mawc_roam_rssi_low_adjust); #ifdef FEATURE_WLAN_ESE req_buf->IsESEAssoc = csr_roam_is_ese_assoc(mac_ctx, session_id) && @@ -19340,12 +20483,13 @@ csr_create_roam_scan_offload_request(tpAniSirGlobal mac_ctx, (csr_is_auth_type_ese(req_buf-> ConnectedNetwork.authentication))); req_buf->is_11r_assoc = roam_info->is11rAssoc; - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - "IsEseAssoc: %d is_11r_assoc: %d middle of roaming: %d ese_neighbor_list_recvd: %d cur no of chan: %d", - req_buf->IsESEAssoc, req_buf->is_11r_assoc, - req_buf->middle_of_roaming, - ese_neighbor_list_recvd, - curr_ch_lst_info->numOfChannels); + + if (req_buf->IsESEAssoc || req_buf->is_11r_assoc || + req_buf->middle_of_roaming) + sme_debug("IsEseAssoc: %d is_11r_assoc: %d middle of roaming: %d ese_neighbor_list_recvd: %d cur no of chan: %d", + req_buf->IsESEAssoc, req_buf->is_11r_assoc, + req_buf->middle_of_roaming, ese_neighbor_list_recvd, + curr_ch_lst_info->numOfChannels); #endif if (!CSR_IS_ROAM_INTRA_BAND_ENABLED(mac_ctx)) { @@ -19368,6 +20512,9 @@ csr_create_roam_scan_offload_request(tpAniSirGlobal mac_ctx, qdf_mem_free(req_buf); return NULL; } + } else if (reason == REASON_FLUSH_CHANNEL_LIST) { + req_buf->ChannelCacheType = CHANNEL_LIST_STATIC; + req_buf->ConnectedNetwork.ChannelCount = 0; } else { csr_fetch_ch_lst_from_occupied_lst(mac_ctx, session_id, reason, req_buf, @@ -19394,12 +20541,12 @@ csr_create_roam_scan_offload_request(tpAniSirGlobal mac_ctx, } #endif } - if (req_buf->ConnectedNetwork.ChannelCount == 0) { + if (req_buf->ConnectedNetwork.ChannelCount == 0 && + reason != REASON_FLUSH_CHANNEL_LIST) { /* Maintain the Valid Channels List */ status = csr_fetch_valid_ch_lst(mac_ctx, req_buf, session_id); if (!QDF_IS_STATUS_SUCCESS(status)) { - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_ERROR, - "Fetch channel list fail"); + sme_err("Fetch channel list fail"); qdf_mem_free(req_buf); return NULL; } @@ -19414,8 +20561,7 @@ csr_create_roam_scan_offload_request(tpAniSirGlobal mac_ctx, } else break; } - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - FL("ChnlCacheType:%d, No of Chnls:%d,Channels: %s"), + sme_debug("ChnlCacheType:%d, No of Chnls:%d,Channels: %s", req_buf->ChannelCacheType, req_buf->ConnectedNetwork.ChannelCount, ch_cache_str); @@ -19434,10 +20580,10 @@ csr_create_roam_scan_offload_request(tpAniSirGlobal mac_ctx, * where RFS is the RF Switching time. It is twice RFS to consider the * time to go off channel and return to the home channel. */ - if (req_buf->HomeAwayTime < (req_buf->NeighborScanChannelMaxTime + + if (req_buf->HomeAwayTime < + (req_buf->NeighborScanChannelMaxTime + (2 * CSR_ROAM_SCAN_CHANNEL_SWITCH_TIME))) { - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - "Invalid config, Home away time(%d) is less than (twice RF switching time + channel max time)(%d). Hence enforcing home away time to disable (0)", + sme_debug("Disable Home away time(%d) as it is less than (2*RF switching time + channel max time)(%d)", req_buf->HomeAwayTime, (req_buf->NeighborScanChannelMaxTime + (2 * CSR_ROAM_SCAN_CHANNEL_SWITCH_TIME))); @@ -19478,32 +20624,17 @@ csr_create_roam_scan_offload_request(tpAniSirGlobal mac_ctx, mac_ctx->roam.configParam.btm_max_attempt_cnt; req_buf->btm_sticky_time = mac_ctx->roam.configParam.btm_sticky_time; + req_buf->btm_query_bitmask = + mac_ctx->roam.configParam.btm_query_bitmask; + req_buf->btm_trig_min_candidate_score = + mac_ctx->roam.configParam.btm_trig_min_candidate_score; + req_buf->rct_validity_timer = mac_ctx->roam.configParam.btm_validity_timer; req_buf->disassoc_timer_threshold = mac_ctx->roam.configParam.btm_disassoc_timer_threshold; -#ifdef WLAN_FEATURE_ROAM_OFFLOAD - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - FL("HomeAwayTime=%d EarlyStopFeature Enable=%d, MinThresh=%d, MaxThresh=%d PMK len=%d disallow_dur=%d rssi_chan_pen=%d num_disallowed_aps=%d"), - req_buf->HomeAwayTime, - req_buf->early_stop_scan_enable, - req_buf->early_stop_scan_min_threshold, - req_buf->early_stop_scan_max_threshold, - req_buf->pmk_len, - req_buf->lca_config_params.disallow_duration, - req_buf->lca_config_params.rssi_channel_penalization, - req_buf->lca_config_params.num_disallowed_aps); - req_buf->RoamOffloadEnabled = csr_roamIsRoamOffloadEnabled(mac_ctx); - req_buf->RoamKeyMgmtOffloadEnabled = session->RoamKeyMgmtOffloadEnabled; - req_buf->pmkid_modes = session->pmkid_modes; - /* Roam Offload piggybacks upon the Roam Scan offload command. */ - if (req_buf->RoamOffloadEnabled) - csr_update_roam_scan_offload_request(mac_ctx, req_buf, session); - qdf_mem_copy(&req_buf->roam_params, - &mac_ctx->roam.configParam.roam_params, - sizeof(req_buf->roam_params)); -#endif + csr_update_roam_scan_offload_request(mac_ctx, req_buf, session); return req_buf; } @@ -19535,7 +20666,6 @@ static void csr_update_11k_offload_params(tpAniSirGlobal mac_ctx, csr_config->offload_11k_enable_bitmask; } else { params->offload_11k_bitmask = 0; - sme_debug("11k offload disabled in RSO"); return; } @@ -19604,8 +20734,6 @@ static void csr_update_11k_offload_params(tpAniSirGlobal mac_ctx, qdf_mem_copy(params->neighbor_report_params.ssid.mac_ssid, session->connectedProfile.SSID.ssId, session->connectedProfile.SSID.length); - - sme_debug("Updated 11k offload params to RSO"); } QDF_STATUS csr_invoke_neighbor_report_request(uint8_t session_id, @@ -19834,31 +20962,6 @@ static bool csr_is_RSO_cmd_allowed(tpAniSirGlobal mac_ctx, return ret_val; } -/* - * csr_roam_send_rso_cmd() - API to send RSO command to PE - * @mac_ctx: Pointer to global MAC structure - * @session_id: Session ID - * @request_buf: Pointer to tSirRoamOffloadScanReq - * - * Return: QDF_STATUS - */ -static QDF_STATUS csr_roam_send_rso_cmd(tpAniSirGlobal mac_ctx, - uint8_t session_id, - tSirRoamOffloadScanReq *request_buf) -{ - QDF_STATUS status; - - request_buf->message_type = eWNI_SME_ROAM_SCAN_OFFLOAD_REQ; - request_buf->length = sizeof(*request_buf); - - status = umac_send_mb_message_to_mac(request_buf); - if (QDF_STATUS_SUCCESS != status) { - sme_err("Send RSO from CSR failed"); - return status; - } - return QDF_STATUS_SUCCESS; -} - /** * csr_append_assoc_ies() - Append specific IE to assoc IE's buffer * @mac_ctx: Pointer to global mac context @@ -20297,6 +21400,8 @@ static void csr_update_score_params(tpAniSirGlobal mac_ctx, req_score_params->pcl_weightage = weight_config->pcl_weightage; req_score_params->oce_wan_weightage = weight_config->oce_wan_weightage; + req_score_params->vendor_roam_score_algorithm = + weight_config->vendor_roam_score_algorithm; req_score_params->bw_index_score = bss_score_params->bandwidth_weight_per_index; @@ -20308,6 +21413,8 @@ static void csr_update_score_params(tpAniSirGlobal mac_ctx, bss_score_params->roam_score_delta; req_score_params->roam_trigger_bitmap = bss_score_params->roam_score_delta_bitmap; + req_score_params->cand_min_roam_score_delta = + bss_score_params->cand_min_roam_score_delta; req_rssi_score->best_rssi_threshold = rssi_score->best_rssi_threshold; req_rssi_score->good_rssi_threshold = rssi_score->good_rssi_threshold; @@ -20356,15 +21463,33 @@ uint8_t csr_get_roam_enabled_sta_sessionid(tpAniSirGlobal mac_ctx) session->pCurRoamProfile->csrPersona != QDF_STA_MODE) continue; roam_info = &mac_ctx->roam.neighborRoamInfo[i]; - if (roam_info->b_roam_scan_offload_started) { - sme_debug("Roaming enabled on iface, session: %d", i); + if (roam_info->b_roam_scan_offload_started) return i; - } } return CSR_SESSION_ID_INVALID; } +#ifdef WLAN_ADAPTIVE_11R +static bool +csr_is_adaptive_11r_roam_supported(tpAniSirGlobal mac_ctx, + struct csr_roam_session *session) +{ + if (session->is_adaptive_11r_connection) + return mac_ctx->is_adaptive_11r_roam_supported; + + return true; +} +#else +static bool +csr_is_adaptive_11r_roam_supported(tpAniSirGlobal mac_ctx, + struct csr_roam_session *session) + +{ + return true; +} +#endif + /** * csr_roam_offload_scan() - populates roam offload scan request and sends to * WMA @@ -20389,11 +21514,13 @@ csr_roam_offload_scan(tpAniSirGlobal mac_ctx, uint8_t session_id, &mac_ctx->roam.neighborRoamInfo[session_id]; struct roam_ext_params *roam_params_dst; struct roam_ext_params *roam_params_src; - uint8_t i, temp_session_id; + uint8_t temp_session_id; uint8_t op_channel; bool prev_roaming_state; + eCsrAuthType roam_profile_akm = eCSR_AUTH_TYPE_UNKNOWN; + uint32_t fw_akm_bitmap; - sme_debug("RSO Command %d, Session id %d, Reason %d", command, + sme_debug("RSO Command %d, vdev %d, Reason %d", command, session_id, reason); if (NULL == session) { QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_ERROR, @@ -20401,9 +21528,13 @@ csr_roam_offload_scan(tpAniSirGlobal mac_ctx, uint8_t session_id, return QDF_STATUS_E_FAILURE; } - if (!csr_is_conn_state_connected(mac_ctx, session_id) && - command == ROAM_SCAN_OFFLOAD_UPDATE_CFG) { - sme_debug("Session not in connected state, RSO not sent"); + if (roam_info->neighborRoamState != + eCSR_NEIGHBOR_ROAM_STATE_CONNECTED && + (command == ROAM_SCAN_OFFLOAD_UPDATE_CFG || + command == ROAM_SCAN_OFFLOAD_START || + command == ROAM_SCAN_OFFLOAD_RESTART)) { + sme_debug("Session not in connected state, RSO not sent and state=%d ", + roam_info->neighborRoamState); return QDF_STATUS_E_FAILURE; } @@ -20456,30 +21587,74 @@ csr_roam_offload_scan(tpAniSirGlobal mac_ctx, uint8_t session_id, return QDF_STATUS_E_FAILURE; } - /* Roaming is not supported currently for FILS akm */ - if (session->pCurRoamProfile && CSR_IS_AUTH_TYPE_FILS( - session->pCurRoamProfile->AuthType.authType[0]) && + if (session->pCurRoamProfile) + roam_profile_akm = + session->pCurRoamProfile->AuthType.authType[0]; + else + sme_info("Roam profile is NULL"); + + if (CSR_IS_AKM_FILS(roam_profile_akm) && !mac_ctx->is_fils_roaming_supported) { sme_info("FILS Roaming not suppprted by fw"); return QDF_STATUS_SUCCESS; } + if (!csr_is_adaptive_11r_roam_supported(mac_ctx, session)) { + sme_info("Adaptive 11r Roaming not suppprted by fw"); + return QDF_STATUS_SUCCESS; + } + + fw_akm_bitmap = mac_ctx->akm_service_bitmap; + /* Roaming is not supported currently for OWE akm */ - if (session->pCurRoamProfile && - (session->pCurRoamProfile->AuthType.authType[0] == - eCSR_AUTH_TYPE_OWE)) { + if (roam_profile_akm == eCSR_AUTH_TYPE_OWE && + !CSR_IS_FW_OWE_ROAM_SUPPORTED(fw_akm_bitmap)) { sme_info("OWE Roaming not suppprted by fw"); return QDF_STATUS_SUCCESS; } - /* Roaming is not supported currently for SAE authentication */ - if (session->pCurRoamProfile && - CSR_IS_AUTH_TYPE_SAE( - session->pCurRoamProfile->AuthType.authType[0])) { + /* Roaming is not supported for SAE authentication */ + if (CSR_IS_AUTH_TYPE_SAE(roam_profile_akm) && + !CSR_IS_FW_SAE_ROAM_SUPPORTED(fw_akm_bitmap)) { sme_info("Roaming not suppprted for SAE connection"); return QDF_STATUS_SUCCESS; } + /* + * If fw doesn't advertise FT SAE, FT-FILS or FT-Suite-B capability, + * don't support roaming to that profile + */ + if (CSR_IS_AKM_FT_SAE(roam_profile_akm)) { + if (!CSR_IS_FW_FT_SAE_SUPPORTED(fw_akm_bitmap)) { + sme_info("Roaming not suppprted for FT SAE akm"); + return QDF_STATUS_SUCCESS; + } + } + + if (CSR_IS_AKM_FT_SUITEB_SHA384(roam_profile_akm)) { + if (!CSR_IS_FW_FT_SUITEB_SUPPORTED(fw_akm_bitmap)) { + sme_info("Roaming not suppprted for FT Suite-B akm"); + return QDF_STATUS_SUCCESS; + } + } + + if (CSR_IS_AKM_FT_FILS(roam_profile_akm)) { + if (!CSR_IS_FW_FT_FILS_SUPPORTED(fw_akm_bitmap)) { + sme_info("Roaming not suppprted for FT FILS akm"); + return QDF_STATUS_SUCCESS; + } + } + + if (mac_ctx->roam.configParam.p2p_disable_roam && + (command == ROAM_SCAN_OFFLOAD_START || + command == ROAM_SCAN_OFFLOAD_UPDATE_CFG) && + (policy_mgr_mode_specific_connection_count(mac_ctx->psoc, + PM_P2P_CLIENT_MODE, NULL) || + policy_mgr_mode_specific_connection_count(mac_ctx->psoc, + PM_P2P_GO_MODE, NULL))) { + sme_info("roaming not supported for active p2p connection"); + return QDF_STATUS_E_FAILURE; + } /* * The Dynamic Config Items Update may happen even if the state is in * INIT. It is important to ensure that the command is passed down to @@ -20538,7 +21713,6 @@ csr_roam_offload_scan(tpAniSirGlobal mac_ctx, uint8_t session_id, (-1); req_buf->rssi_thresh_offset_5g = roam_info->cfgParams.rssi_thresh_offset_5g; - sme_debug("5g offset threshold: %d", req_buf->rssi_thresh_offset_5g); qdf_mem_copy(roam_params_dst, roam_params_src, sizeof(*roam_params_dst)); /* @@ -20547,58 +21721,12 @@ csr_roam_offload_scan(tpAniSirGlobal mac_ctx, uint8_t session_id, */ if (roam_params_src->rssi_diff) req_buf->RoamRssiDiff = roam_params_src->rssi_diff; - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - "num_bssid_avoid_list: %d num_ssid_allowed_list: %d num_bssid_favored: %d raise_rssi_thresh_5g: %d drop_rssi_thresh_5g: %d raise_rssi_type_5g: %d raise_factor_5g: %d drop_rssi_type_5g: %d drop_factor_5g: %d max_raise_rssi_5g: %d max_drop_rssi_5g: %d rssi_diff: %d alert_rssi_threshold: %d", - roam_params_dst->num_bssid_avoid_list, - roam_params_dst->num_ssid_allowed_list, - roam_params_dst->num_bssid_favored, - roam_params_dst->raise_rssi_thresh_5g, - roam_params_dst->drop_rssi_thresh_5g, - roam_params_dst->raise_rssi_type_5g, - roam_params_dst->raise_factor_5g, - roam_params_dst->drop_rssi_type_5g, - roam_params_dst->drop_factor_5g, - roam_params_dst->max_raise_rssi_5g, - roam_params_dst->max_drop_rssi_5g, - req_buf->RoamRssiDiff, roam_params_dst->alert_rssi_threshold); /* Set initial dense roam status */ if (mac_ctx->scan.roam_candidate_count[session_id] > roam_params_dst->dense_min_aps_cnt) roam_params_dst->initial_dense_status = true; - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - "dense_rssi_thresh_offset: %d, dense_min_aps_cnt:%d, traffic_threshold:%d, " - "initial_dense_status:%d, candidate count:%d", - roam_params_dst->dense_rssi_thresh_offset, - roam_params_dst->dense_min_aps_cnt, - roam_params_dst->traffic_threshold, - roam_params_dst->initial_dense_status, - mac_ctx->scan.roam_candidate_count[session_id]); - sme_debug("BG Scan Bad RSSI:%d, bitmap:0x%x Offset for 2G to 5G Roam %d", - roam_params_dst->bg_scan_bad_rssi_thresh, - roam_params_dst->bg_scan_client_bitmap, - roam_params_dst->roam_bad_rssi_thresh_offset_2g); - - for (i = 0; i < roam_params_dst->num_bssid_avoid_list; i++) { - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - "Blacklist Bssid:"MAC_ADDRESS_STR")", - MAC_ADDR_ARRAY(roam_params_dst->bssid_avoid_list[i]. - bytes)); - } - for (i = 0; i < roam_params_dst->num_ssid_allowed_list; i++) { - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - "Whitelist: %.*s", - roam_params_dst->ssid_allowed_list[i].length, - roam_params_dst->ssid_allowed_list[i].ssId); - } - for (i = 0; i < roam_params_dst->num_bssid_favored; i++) { - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - "Preferred Bssid:"MAC_ADDRESS_STR") score: %d", - MAC_ADDR_ARRAY(roam_params_dst->bssid_favored[i].bytes), - roam_params_dst->bssid_favored_factor[i]); - } - op_channel = session->connectedProfile.operationChannel; req_buf->hi_rssi_scan_max_count = roam_info->cfgParams.hi_rssi_scan_max_count; @@ -20617,12 +21745,6 @@ csr_roam_offload_scan(tpAniSirGlobal mac_ctx, uint8_t session_id, else req_buf->hi_rssi_scan_rssi_delta = roam_info->cfgParams.hi_rssi_scan_rssi_delta; - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - "hi_rssi:delta=%d, max_count=%d, delay=%d, ub=%d", - req_buf->hi_rssi_scan_rssi_delta, - req_buf->hi_rssi_scan_max_count, - req_buf->hi_rssi_scan_delay, - req_buf->hi_rssi_scan_rssi_ub); if (command != ROAM_SCAN_OFFLOAD_STOP) { req_buf->assoc_ie.length = session->nAddIEAssocLength; @@ -20643,18 +21765,12 @@ csr_roam_offload_scan(tpAniSirGlobal mac_ctx, uint8_t session_id, else if (command == ROAM_SCAN_OFFLOAD_STOP) csr_update_11k_offload_params(mac_ctx, session, req_buf, FALSE); - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - "Assoc IE buffer:"); - QDF_TRACE_HEX_DUMP(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - req_buf->assoc_ie.addIEdata, req_buf->assoc_ie.length); - prev_roaming_state = roam_info->b_roam_scan_offload_started; if (ROAM_SCAN_OFFLOAD_START == command) roam_info->b_roam_scan_offload_started = true; else if (ROAM_SCAN_OFFLOAD_STOP == command) roam_info->b_roam_scan_offload_started = false; policy_mgr_set_pcl_for_existing_combo(mac_ctx->psoc, PM_STA_MODE); - if (!QDF_IS_STATUS_SUCCESS( csr_roam_send_rso_cmd(mac_ctx, session_id, req_buf))) { QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_ERROR, @@ -20943,7 +22059,6 @@ void csr_release_command(tpAniSirGlobal mac_ctx, tSmeCmd *sme_cmd) qdf_mem_zero(&cmd_info, sizeof(struct wlan_serialization_queued_cmd_info)); - sme_debug("filled cmd_id = %d", sme_cmd->cmd_id); cmd_info.cmd_id = sme_cmd->cmd_id; cmd_info.req_type = WLAN_SER_CANCEL_NON_SCAN_CMD; cmd_info.cmd_type = csr_get_cmd_type(sme_cmd); @@ -20953,19 +22068,15 @@ void csr_release_command(tpAniSirGlobal mac_ctx, tSmeCmd *sme_cmd) cmd.cmd_type = cmd_info.cmd_type; cmd.vdev = cmd_info.vdev; if (wlan_serialization_is_cmd_present_in_active_queue( - mac_ctx->psoc, &cmd)) { - sme_debug("Releasing active cmd_id[%d] cmd_type[%d]", - cmd_info.cmd_id, cmd_info.cmd_type); + mac_ctx->psoc, &cmd)) wlan_serialization_remove_cmd(&cmd_info); - } else if (wlan_serialization_is_cmd_present_in_pending_queue( - mac_ctx->psoc, &cmd)) { - sme_debug("Releasing pending cmd_id[%d] cmd_type[%d]", - cmd_info.cmd_id, cmd_info.cmd_type); + else if (wlan_serialization_is_cmd_present_in_pending_queue( + mac_ctx->psoc, &cmd)) wlan_serialization_cancel_request(&cmd_info); - } else { + else sme_debug("can't find cmd_id[%d] cmd_type[%d]", - cmd_info.cmd_id, cmd_info.cmd_type); - } + cmd_info.cmd_id, cmd_info.cmd_type); + if (cmd_info.vdev) wlan_objmgr_vdev_release_ref(cmd_info.vdev, WLAN_LEGACY_SME_ID); } @@ -21100,13 +22211,11 @@ QDF_STATUS csr_set_serialization_params_to_cmd(tpAniSirGlobal mac_ctx, */ sme_cmd->cmd_id = csr_get_monotonous_number(mac_ctx); cmd->cmd_id = sme_cmd->cmd_id; - sme_debug("cmd_id = %d", cmd->cmd_id); cmd->cmd_type = csr_get_cmd_type(sme_cmd); - sme_debug("filled cmd_type[%d] cmd_id[%d]", - cmd->cmd_type, cmd->cmd_id); if (cmd->cmd_type == WLAN_SER_CMD_MAX) { - sme_err("serialization enum not found"); + sme_err("serialization enum not found for sme_cmd type %d", + sme_cmd->command); return status; } cmd->vdev = wlan_objmgr_get_vdev_by_id_from_psoc(mac_ctx->psoc, @@ -21167,7 +22276,6 @@ QDF_STATUS csr_queue_sme_command(tpAniSirGlobal mac_ctx, tSmeCmd *sme_cmd, vdev = cmd.vdev; ser_cmd_status = wlan_serialization_request(&cmd); - sme_debug("wlan_serialization_request status:%d", ser_cmd_status); switch (ser_cmd_status) { case WLAN_SER_CMD_PENDING: @@ -21175,13 +22283,9 @@ QDF_STATUS csr_queue_sme_command(tpAniSirGlobal mac_ctx, tSmeCmd *sme_cmd, /* Command posted to active/pending list */ status = QDF_STATUS_SUCCESS; break; - case WLAN_SER_CMD_DENIED_LIST_FULL: - case WLAN_SER_CMD_DENIED_RULES_FAILED: - case WLAN_SER_CMD_DENIED_UNSPECIFIED: - status = QDF_STATUS_E_FAILURE; - goto error; default: - QDF_ASSERT(0); + sme_err("Failed to queue command %d with status:%d", + sme_cmd->command, ser_cmd_status); status = QDF_STATUS_E_FAILURE; goto error; } @@ -21385,8 +22489,6 @@ QDF_STATUS csr_roam_channel_change_req(tpAniSirGlobal pMac, qdf_mem_copy(&pMsg->extended_rateset, ¶m.extendedRateSet, sizeof(pMsg->extended_rateset)); - sme_debug("target_chan %d ch_width %d dot11mode %d", - pMsg->targetChannel, pMsg->ch_width, pMsg->dot11mode); status = umac_send_mb_message_to_mac(pMsg); return status; @@ -21704,12 +22806,13 @@ void csr_process_ho_fail_ind(tpAniSirGlobal mac_ctx, void *pMsgBuf) QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_ERROR, "LFR3:Issue Disconnect on session %d", sessionId); csr_roam_disconnect(mac_ctx, sessionId, - eCSR_DISCONNECT_REASON_ROAM_HO_FAIL); + eCSR_DISCONNECT_REASON_ROAM_HO_FAIL, + eSIR_MAC_FW_TRIGGERED_ROAM_FAILURE); if (mac_ctx->roam.configParam.enable_fatal_event) cds_flush_logs(WLAN_LOG_TYPE_FATAL, WLAN_LOG_INDICATOR_HOST_DRIVER, WLAN_LOG_REASON_ROAM_HO_FAILURE, - true, false); + false, false); } #endif /* WLAN_FEATURE_ROAM_OFFLOAD */ @@ -21735,8 +22838,7 @@ csr_update_op_class_array(tpAniSirGlobal mac_ctx, uint8_t num_channels = channel_info->numChannels; uint8_t ch_bandwidth; - sme_debug("Num of %s channels, %d", - ch_name, num_channels); + sme_debug("Num %s channels, %d", ch_name, num_channels); for (idx = 0; idx < num_channels && *i < (REG_MAX_SUPP_OPER_CLASSES - 1); idx++) { @@ -21746,8 +22848,6 @@ csr_update_op_class_array(tpAniSirGlobal mac_ctx, mac_ctx->scan.countryCodeCurrent, channel_info->channelList[idx], ch_bandwidth); - sme_debug("for chan %d, op class: %d", - channel_info->channelList[idx], class); found = false; for (j = 0; j < REG_MAX_SUPP_OPER_CLASSES - 1; @@ -21803,11 +22903,6 @@ static void csr_init_operating_classes(tHalHandle hHal) } } - sme_debug("Number of unique supported op classes %d", - numClasses); - for (i = 0; i < numClasses; i++) - sme_debug("supported opClasses[%d] = %d", i, opClasses[i]); - /* Set the ordered list of op classes in regdomain * for use by other modules */ @@ -22164,7 +23259,7 @@ void csr_process_set_hw_mode(tpAniSirGlobal mac, tSmeCmd *command) "Malloc fail: Fail to send response to SME"); return; } - sme_err("Sending set HW fail response to SME"); + sme_debug("Sending set HW fail response to SME"); param->status = SET_HW_MODE_STATUS_ECANCELED; param->cfgd_hw_mode_index = 0; param->num_vdev_mac_entries = 0; @@ -22445,6 +23540,60 @@ void csr_update_fils_erp_seq_num(struct csr_roam_profile *roam_info, {} #endif +#if defined(WLAN_SAE_SINGLE_PMK) && defined(WLAN_FEATURE_ROAM_OFFLOAD) +/** + * csr_is_sae_single_pmk_vsie_ap() - check if the Roamed AP supports sae + * roaming using single pmk connection + * with same pmk or not + * @bss_des: bss descriptor + * + * Return: True if same pmk IE is present + */ +static bool csr_is_sae_single_pmk_vsie_ap(struct bss_description *bss_des) +{ + uint16_t ie_len; + const uint8_t *vendor_ie; + + if (!bss_des) { + sme_debug("Invalid bss description"); + return false; + } + ie_len = csr_get_ielen_from_bss_description(bss_des); + + vendor_ie = + wlan_get_vendor_ie_ptr_from_oui(CSR_SINGLE_PMK_OUI, + CSR_SINGLE_PMK_OUI_SIZE, + (uint8_t *)bss_des->ieFields, + ie_len); + + if (!vendor_ie) + return false; + + sme_debug("AP supports sae single pmk feature"); + + return true; +} + +/** + * csr_check_and_set_sae_single_pmk_cap() - check if the Roamed AP support + * roaming using single pmk with single pmk or not + * @session: Session + * + * Return: True if same pmk IE is present + */ +static void +csr_check_and_set_sae_single_pmk_cap(struct csr_roam_session *session) +{ + session->single_pmk_info.sae_single_pmk_ap = + csr_is_sae_single_pmk_vsie_ap(session->pConnectBssDesc); +} +#else +static inline void +csr_check_and_set_sae_single_pmk_cap(struct csr_roam_session *session) +{ +} +#endif + #ifdef WLAN_FEATURE_ROAM_OFFLOAD static QDF_STATUS csr_process_roam_sync_callback(tpAniSirGlobal mac_ctx, roam_offload_synch_ind *roam_synch_data, @@ -22466,6 +23615,8 @@ static QDF_STATUS csr_process_roam_sync_callback(tpAniSirGlobal mac_ctx, tSirSmeHTProfile *src_profile = NULL; tCsrRoamHTProfile *dst_profile = NULL; #endif + tpCsrNeighborRoamControlInfo neigh_roam_info = + &mac_ctx->roam.neighborRoamInfo[session_id]; if (!session) { sme_err("LFR3: Session not found"); @@ -22482,6 +23633,7 @@ static QDF_STATUS csr_process_roam_sync_callback(tpAniSirGlobal mac_ctx, csr_roam_roaming_offload_timer_action(mac_ctx, 0, session_id, ROAMING_OFFLOAD_TIMER_STOP); if (session->discon_in_progress || + neigh_roam_info->last_sent_cmd == ROAM_SCAN_OFFLOAD_STOP || !CSR_IS_ROAM_JOINED(mac_ctx, session_id)) { QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, FL("LFR3: Session not in connected state or disconnect is in progress %d"), @@ -22514,7 +23666,8 @@ static QDF_STATUS csr_process_roam_sync_callback(tpAniSirGlobal mac_ctx, /* Userspace roam request failed, disconnect with current AP */ sme_debug("LFR3: roam invoke from user-space fail, dis cur AP"); csr_roam_disconnect(mac_ctx, session_id, - eCSR_DISCONNECT_REASON_DEAUTH); + eCSR_DISCONNECT_REASON_DEAUTH, + eSIR_MAC_USER_TRIGGERED_ROAM_FAILURE); return status; case SIR_ROAM_SYNCH_PROPAGATION: break; @@ -22539,6 +23692,9 @@ static QDF_STATUS csr_process_roam_sync_callback(tpAniSirGlobal mac_ctx, mac_ctx->psoc); mac_ctx->sme.set_connection_info_cb(false); session->roam_synch_in_progress = false; + ucfg_pkt_capture_record_channel(); + + csr_check_and_set_sae_single_pmk_cap(session); if (WLAN_REG_IS_5GHZ_CH(bss_desc->channelId)) { session->disable_hi_rssi = true; @@ -22664,7 +23820,7 @@ static QDF_STATUS csr_process_roam_sync_callback(tpAniSirGlobal mac_ctx, session_id); ps_global_info->remain_in_power_active_till_dhcp = true; - mac_ctx->roam.WaitForKeyTimerInfo.sessionId = session_id; + mac_ctx->roam.WaitForKeyTimerInfo.vdev_id = session_id; if (!QDF_IS_STATUS_SUCCESS(csr_roam_start_wait_for_key_timer( mac_ctx, CSR_WAIT_FOR_KEY_TIMEOUT_PERIOD)) ) { @@ -22796,9 +23952,10 @@ static QDF_STATUS csr_process_roam_sync_callback(tpAniSirGlobal mac_ctx, } roam_info->roamSynchInProgress = true; roam_info->synchAuthStatus = roam_synch_data->authStatus; + roam_info->kck_len = roam_synch_data->kck_len; roam_info->kek_len = roam_synch_data->kek_len; roam_info->pmk_len = roam_synch_data->pmk_len; - qdf_mem_copy(roam_info->kck, roam_synch_data->kck, SIR_KCK_KEY_LEN); + qdf_mem_copy(roam_info->kck, roam_synch_data->kck, roam_info->kck_len); qdf_mem_copy(roam_info->kek, roam_synch_data->kek, roam_info->kek_len); if (roam_synch_data->pmk_len) @@ -22826,7 +23983,7 @@ static QDF_STATUS csr_process_roam_sync_callback(tpAniSirGlobal mac_ctx, /* fetch 4 LSB to get roam reason */ roam_info->roam_reason = roam_synch_data->roamReason & ROAM_REASON_MASK; - sme_info("Update roam reason : %d", roam_info->roam_reason); + sme_debug("Update roam reason : %d", roam_info->roam_reason); csr_copy_fils_join_rsp_roam_info(roam_info, roam_synch_data); csr_roam_call_callback(mac_ctx, session_id, roam_info, 0, @@ -22887,4 +24044,61 @@ QDF_STATUS csr_roam_synch_callback(tpAniSirGlobal mac_ctx, return status; } + +QDF_STATUS +csr_process_roam_auth_offload_callback(tpAniSirGlobal mac_ctx, + uint8_t vdev_id, + struct qdf_mac_addr roam_bssid) +{ + struct csr_roam_info *roam_info; + struct sir_sae_info sae_info; + struct csr_roam_session *session = CSR_GET_SESSION(mac_ctx, vdev_id); + + if (!session) { + sme_err("WPA3 Preauth event with invalid session id:%d", + vdev_id); + return QDF_STATUS_E_FAILURE; + } + + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return QDF_STATUS_E_FAILURE; + + sae_info.msg_len = sizeof(sae_info); + sae_info.vdev_id = vdev_id; + + sae_info.ssid.length = session->connectedProfile.SSID.length; + qdf_mem_copy(sae_info.ssid.ssId, session->connectedProfile.SSID.ssId, + sae_info.ssid.length); + + qdf_mem_copy(sae_info.peer_mac_addr.bytes, + roam_bssid.bytes, QDF_MAC_ADDR_SIZE); + + roam_info->sae_info = &sae_info; + + csr_roam_call_callback(mac_ctx, vdev_id, roam_info, 0, + eCSR_ROAM_SAE_COMPUTE, eCSR_ROAM_RESULT_NONE); + + qdf_mem_free(roam_info); + + return QDF_STATUS_SUCCESS; +} + +QDF_STATUS +csr_roam_auth_offload_callback(tpAniSirGlobal mac_ctx, + uint8_t vdev_id, struct qdf_mac_addr bssid) +{ + QDF_STATUS status; + + status = sme_acquire_global_lock(&mac_ctx->sme); + if (!QDF_IS_STATUS_SUCCESS(status)) + return status; + + status = csr_process_roam_auth_offload_callback(mac_ctx, vdev_id, bssid); + + sme_release_global_lock(&mac_ctx->sme); + + return status; + +} #endif diff --git a/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_api_scan.c b/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_api_scan.c index ca2cb60724ac..003568a731fc 100644 --- a/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_api_scan.c +++ b/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_api_scan.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -377,8 +377,6 @@ static void csr_add_to_occupied_channels(tpAniSirGlobal pMac, num_occupied_ch, ch); if (QDF_IS_STATUS_SUCCESS(status)) { occupied_ch->numChannels++; - sme_debug("Added channel %d to the list (count=%d)", - ch, occupied_ch->numChannels); if (occupied_ch->numChannels > CSR_BG_SCAN_OCCUPIED_CHANNEL_LIST_LEN) occupied_ch->numChannels = @@ -1244,7 +1242,7 @@ static void csr_handle_nxt_cmd(tpAniSirGlobal mac_ctx, } if (QDF_STATUS_E_FAILURE == ret) { - sme_err("conn update fail %d", chan); + sme_debug("conn update fail %d", chan); csr_scan_handle_search_for_ssid_failure(mac_ctx, session_id); } else if ((QDF_STATUS_E_NOSUPPORT == ret) || @@ -1652,21 +1650,15 @@ static void csr_save_tx_power_to_cfg(tpAniSirGlobal pMac, tDblLinkList *pList, ch_pwr_set->firstChanNum = (tSirMacChanNum) (ch_set->firstChannel + (idx * ch_set->interChannelOffset)); - sme_debug( - "Setting Channel Number %d", - ch_pwr_set->firstChanNum); ch_pwr_set->numChannels = 1; ch_pwr_set->maxTxPower = QDF_MIN(ch_set->txPower, pMac->roam.configParam.nTxPowerCap); - sme_debug( - "Setting Max Transmit Power %d", - ch_pwr_set->maxTxPower); cbLen += sizeof(tSirMacChanInfo); ch_pwr_set++; } } else { - if (cbLen >= dataLen) { + if (cbLen + sizeof(tSirMacChanInfo) >= dataLen) { /* this entry will overflow our allocation */ sme_err( "Buffer overflow, start %d, num %d, offset %d", @@ -1676,15 +1668,9 @@ static void csr_save_tx_power_to_cfg(tpAniSirGlobal pMac, tDblLinkList *pList, break; } ch_pwr_set->firstChanNum = ch_set->firstChannel; - sme_debug("Setting Channel Number %d", - ch_pwr_set->firstChanNum); ch_pwr_set->numChannels = ch_set->numChannels; ch_pwr_set->maxTxPower = QDF_MIN(ch_set->txPower, pMac->roam.configParam.nTxPowerCap); - sme_debug( - "Setting Max Tx Power %d, nTxPower %d", - ch_pwr_set->maxTxPower, - pMac->roam.configParam.nTxPowerCap); cbLen += sizeof(tSirMacChanInfo); ch_pwr_set++; } @@ -1701,7 +1687,7 @@ static void csr_set_cfg_country_code(tpAniSirGlobal pMac, uint8_t *countryCode) uint8_t cc[WNI_CFG_COUNTRY_CODE_LEN]; /* v_REGDOMAIN_t DomainId */ - sme_debug("Setting Country Code in Cfg %s", countryCode); + sme_debug("Set Country in Cfg %s", countryCode); qdf_mem_copy(cc, countryCode, WNI_CFG_COUNTRY_CODE_LEN); /* @@ -2222,6 +2208,10 @@ static enum wlan_auth_type csr_covert_auth_type_new(eCsrAuthType auth) return WLAN_AUTH_TYPE_SUITEB_EAP_SHA384; case eCSR_AUTH_TYPE_SAE: return WLAN_AUTH_TYPE_SAE; + case eCSR_AUTH_TYPE_FT_SAE: + return WLAN_AUTH_TYPE_FT_SAE; + case eCSR_AUTH_TYPE_FT_SUITEB_EAP_SHA384: + return WLAN_AUTH_TYPE_FT_SUITEB_EAP_SHA384; case eCSR_NUM_OF_SUPPORT_AUTH_TYPE: default: return WLAN_AUTH_TYPE_OPEN_SYSTEM; @@ -2281,6 +2271,10 @@ static eCsrAuthType csr_covert_auth_type_old(enum wlan_auth_type auth) return eCSR_AUTH_TYPE_SUITEB_EAP_SHA384; case WLAN_AUTH_TYPE_SAE: return eCSR_AUTH_TYPE_SAE; + case WLAN_AUTH_TYPE_FT_SAE: + return eCSR_AUTH_TYPE_FT_SAE; + case WLAN_AUTH_TYPE_FT_SUITEB_EAP_SHA384: + return eCSR_AUTH_TYPE_FT_SUITEB_EAP_SHA384; case WLAN_NUM_OF_SUPPORT_AUTH_TYPE: default: return eCSR_AUTH_TYPE_OPEN_SYSTEM; @@ -2438,6 +2432,31 @@ static enum wlan_phymode csr_convert_dotllmod_phymode(eCsrPhyMode dotllmode) return con_phy_mode; } +#ifdef WLAN_ADAPTIVE_11R +/** + * csr_update_adaptive_11r_scan_filter - Copy adaptive 11r ini to scan + * module + * @mac_ctx: Pointer to mac_context + * @scan_filter: Scan filter to be sent to scan module + * + * Return: None + */ +static void +csr_update_adaptive_11r_scan_filter(tpAniSirGlobal mac_ctx, + struct scan_filter *filter) +{ + filter->enable_adaptive_11r = + mac_ctx->roam.configParam.enable_adaptive_11r; +} +#else +static inline void +csr_update_adaptive_11r_scan_filter(tpAniSirGlobal mac_ctx, + struct scan_filter *filter) +{ + filter->enable_adaptive_11r = false; +} +#endif + static QDF_STATUS csr_prepare_scan_filter(tpAniSirGlobal mac_ctx, tCsrScanResultFilter *pFilter, struct scan_filter *filter) { @@ -2546,6 +2565,9 @@ static QDF_STATUS csr_prepare_scan_filter(tpAniSirGlobal mac_ctx, filter->bss_scoring_required = true; else filter->bss_scoring_required = false; + + csr_update_adaptive_11r_scan_filter(mac_ctx, filter); + if (!pFilter->BSSIDs.numOfBSSIDs) { if (policy_mgr_map_concurrency_mode( &pFilter->csrPersona, &new_mode)) { @@ -2614,6 +2636,30 @@ static void csr_update_bss_with_fils_data(tpAniSirGlobal mac_ctx, { } #endif +#if defined(WLAN_SAE_SINGLE_PMK) && defined(WLAN_FEATURE_ROAM_OFFLOAD) +/** + * csr_fill_single_pmk_ap_cap_from_scan_entry() - WAP3_SPMK VSIE from scan + * entry + * @bss_desc: BSS Descriptor + * @scan_entry: scan entry + * + * Return: None + */ +static void +csr_fill_single_pmk_ap_cap_from_scan_entry(struct bss_description *bss_desc, + struct scan_cache_entry *scan_entry) +{ + bss_desc->sae_single_pmk_ap = util_scan_entry_single_pmk(scan_entry); +} + +#else +static inline void +csr_fill_single_pmk_ap_cap_from_scan_entry(struct bss_description *bss_desc, + struct scan_cache_entry *scan_entry) +{ +} +#endif + static QDF_STATUS csr_fill_bss_from_scan_entry(tpAniSirGlobal mac_ctx, struct scan_cache_entry *scan_entry, struct tag_csrscan_result **p_result) @@ -2715,6 +2761,8 @@ static QDF_STATUS csr_fill_bss_from_scan_entry(tpAniSirGlobal mac_ctx, IEEE80211_FC0_SUBTYPE_PROBE_RESP); bss_desc->seq_ctrl = hdr->seqControl; bss_desc->tsf_delta = scan_entry->tsf_delta; + bss_desc->adaptive_11r_ap = scan_entry->adaptive_11r_ap; + csr_fill_single_pmk_ap_cap_from_scan_entry(bss_desc, scan_entry); qdf_mem_copy((uint8_t *) &bss_desc->ieFields, ie_ptr, ie_len); @@ -3141,6 +3189,28 @@ void csr_remove_bssid_from_scan_list(tpAniSirGlobal mac_ctx, csr_flush_bssid(mac_ctx, bssid); } +static void csr_dump_occupied_chan_list(struct csr_channel *occupied_ch) +{ + uint8_t idx; + uint32_t buff_len; + char *chan_buff; + uint32_t len = 0; + + buff_len = (occupied_ch->numChannels * 5) + 1; + chan_buff = qdf_mem_malloc(buff_len); + if (!chan_buff) + return; + + for (idx = 0; idx < occupied_ch->numChannels; idx++) + len += qdf_scnprintf(chan_buff + len, buff_len - len, " %d", + occupied_ch->channelList[idx]); + + sme_nofl_debug("Occupied chan list[%d]:%s", + occupied_ch->numChannels, chan_buff); + + qdf_mem_free(chan_buff); +} + void csr_init_occupied_channels_list(tpAniSirGlobal mac_ctx, uint8_t sessionId) { @@ -3169,15 +3239,6 @@ void csr_init_occupied_channels_list(tpAniSirGlobal mac_ctx, return; } - if (!csr_neighbor_roam_is_new_connected_profile(mac_ctx, sessionId)) { - /* - * Do not flush occupied list since current roam profile matches - * previous - */ - sme_debug("Current roam profile matches prev"); - return; - } - profile = &mac_ctx->roam.roamSession[sessionId].connectedProfile; if (!profile) return; @@ -3199,6 +3260,7 @@ void csr_init_occupied_channels_list(tpAniSirGlobal mac_ctx, filter->ssid_list[0].length = profile->SSID.length; qdf_mem_copy(filter->ssid_list[0].ssid, profile->SSID.ssId, profile->SSID.length); + csr_update_pmf_cap_from_connected_profile(profile, filter); pdev = wlan_objmgr_get_pdev_by_id(mac_ctx->psoc, 0, WLAN_LEGACY_MAC_ID); @@ -3221,11 +3283,12 @@ void csr_init_occupied_channels_list(tpAniSirGlobal mac_ctx, if (list) sme_debug("num_entries %d", qdf_list_size(list)); if (!list || (list && !qdf_list_size(list))) { - sme_err("get scan result failed"); wlan_objmgr_pdev_release_ref(pdev, WLAN_LEGACY_MAC_ID); qdf_mem_free(filter); if (list) ucfg_scan_purge_results(list); + csr_dump_occupied_chan_list( + &mac_ctx->scan.occupiedChannels[sessionId]); return; } @@ -3243,6 +3306,7 @@ void csr_init_occupied_channels_list(tpAniSirGlobal mac_ctx, cur_lst = next_lst; next_lst = NULL; } + csr_dump_occupied_chan_list(&mac_ctx->scan.occupiedChannels[sessionId]); qdf_mem_free(filter); ucfg_scan_purge_results(list); diff --git a/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_host_scan_roam.c b/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_host_scan_roam.c index 8c3cc20adfba..975db9dc9e6f 100644 --- a/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_host_scan_roam.c +++ b/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_host_scan_roam.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -519,9 +519,6 @@ void csr_neighbor_roam_free_roamable_bss_list(tpAniSirGlobal mac_ctx, { tpCsrNeighborRoamBSSInfo result = NULL; - sme_debug("Emptying the BSS list. Current count: %d", - csr_ll_count(llist)); - /* * Pick up the head, remove and free the node till * the list becomes empty @@ -608,7 +605,7 @@ tpCsrNeighborRoamBSSInfo csr_neighbor_roam_next_roamable_ap( void csr_neighbor_roam_request_handoff(tpAniSirGlobal mac_ctx, uint8_t session_id) { - struct csr_roam_info roam_info; + struct csr_roam_info *roam_info; tpCsrNeighborRoamControlInfo neighbor_roam_info = &mac_ctx->roam.neighborRoamInfo[session_id]; tCsrNeighborRoamBSSInfo handoff_node; @@ -636,11 +633,13 @@ void csr_neighbor_roam_request_handoff(tpAniSirGlobal mac_ctx, FL("HANDOFF CANDIDATE BSSID "MAC_ADDRESS_STR), MAC_ADDR_ARRAY(handoff_node.pBssDescription->bssId)); - qdf_mem_zero(&roam_info, sizeof(struct csr_roam_info)); - csr_roam_call_callback(mac_ctx, session_id, &roam_info, roamid, + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return; + csr_roam_call_callback(mac_ctx, session_id, roam_info, roamid, eCSR_ROAM_FT_START, eCSR_ROAM_RESULT_SUCCESS); - qdf_mem_zero(&roam_info, sizeof(struct csr_roam_info)); + qdf_mem_zero(roam_info, sizeof(*roam_info)); csr_neighbor_roam_state_transition(mac_ctx, eCSR_NEIGHBOR_ROAM_STATE_REASSOCIATING, session_id); @@ -661,6 +660,7 @@ void csr_neighbor_roam_request_handoff(tpAniSirGlobal mac_ctx, QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_ERROR, FL("csr_roam_copy_connected_profile failed %d"), status); + qdf_mem_free(roam_info); return; } qdf_mem_copy(neighbor_roam_info->csrNeighborRoamProfile.BSSIDs.bssid, @@ -670,22 +670,25 @@ void csr_neighbor_roam_request_handoff(tpAniSirGlobal mac_ctx, sme_debug("csr_roamHandoffRequested: disassociating with current AP"); - if (!QDF_IS_STATUS_SUCCESS - (csr_roam_issue_disassociate_cmd - (mac_ctx, session_id, - eCSR_DISCONNECT_REASON_HANDOFF))) { + if (!QDF_IS_STATUS_SUCCESS(csr_roam_issue_disassociate_cmd( + mac_ctx, + session_id, + eCSR_DISCONNECT_REASON_HANDOFF, + eSIR_MAC_UNSPEC_FAILURE_REASON))) { sme_warn("csr_roamHandoffRequested: fail to issue disassoc"); + qdf_mem_free(roam_info); return; } /* notify HDD for handoff, providing the BSSID too */ - roam_info.reasonCode = eCsrRoamReasonBetterAP; + roam_info->reasonCode = eCsrRoamReasonBetterAP; - qdf_mem_copy(roam_info.bssid.bytes, + qdf_mem_copy(roam_info->bssid.bytes, handoff_node.pBssDescription->bssId, sizeof(struct qdf_mac_addr)); - csr_roam_call_callback(mac_ctx, session_id, &roam_info, 0, + csr_roam_call_callback(mac_ctx, session_id, roam_info, 0, eCSR_ROAM_ROAMING_START, eCSR_ROAM_RESULT_NONE); + qdf_mem_free(roam_info); } diff --git a/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_inside_api.h b/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_inside_api.h index e12f63c74817..9e6280a75c1a 100644 --- a/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_inside_api.h +++ b/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_inside_api.h @@ -86,10 +86,11 @@ #define CSR_ACTIVE_SCAN_LIST_CMD_TIMEOUT (1000*30) #endif /* *************************************************************************** - * The MAX BSSID Count should be lower than the command timeout value and it - * can be of a fraction of 1/3 to 1/2 of the total command timeout value. + * The MAX BSSID Count should be lower than the command timeout value. + * As in some case auth timeout can take upto 5 sec (in case of SAE auth) try + * (command timeout/5000 - 1) candidates. * ***************************************************************************/ -#define CSR_MAX_BSSID_COUNT (SME_ACTIVE_LIST_CMD_TIMEOUT_VALUE/3000) - 2 +#define CSR_MAX_BSSID_COUNT (SME_ACTIVE_LIST_CMD_TIMEOUT_VALUE/5000) - 1 #define CSR_CUSTOM_CONC_GO_BI 100 extern uint8_t csr_wpa_oui[][CSR_WPA_OUI_SIZE]; bool csr_is_supported_channel(tpAniSirGlobal pMac, uint8_t channelId); @@ -334,10 +335,12 @@ eRoamCmdStatus csr_get_roam_complete_status(tpAniSirGlobal pMac, uint32_t sessionId); /* pBand can be NULL if caller doesn't need to get it */ QDF_STATUS csr_roam_issue_disassociate_cmd(tpAniSirGlobal pMac, - uint32_t sessionId, - eCsrRoamDisconnectReason reason); + uint32_t sessionId, + eCsrRoamDisconnectReason reason, + tSirMacReasonCodes mac_reason); QDF_STATUS csr_roam_disconnect_internal(tpAniSirGlobal pMac, uint32_t sessionId, - eCsrRoamDisconnectReason reason); + eCsrRoamDisconnectReason reason, + tSirMacReasonCodes mac_reason); /* pCommand may be NULL */ void csr_roam_remove_duplicate_command(tpAniSirGlobal pMac, uint32_t sessionId, tSmeCmd *pCommand, @@ -719,14 +722,6 @@ QDF_STATUS csr_roam_reassoc(tpAniSirGlobal pMac, uint32_t sessionId, tCsrRoamModifyProfileFields modProfileFields, uint32_t *pRoamId); -/* - * csr_roam_reconnect() - - * To disconnect and reconnect with the same profile - * - * Return QDF_STATUS. It returns fail if currently not connected - */ -QDF_STATUS csr_roam_reconnect(tpAniSirGlobal pMac, uint32_t sessionId); - /* * csr_roam_set_pmkid_cache() - * return the PMKID candidate list @@ -870,16 +865,18 @@ QDF_STATUS csr_apply_channel_and_power_list(tpAniSirGlobal pMac); QDF_STATUS csr_roam_connect_to_last_profile(tpAniSirGlobal pMac, uint32_t sessionId); -/* - * csr_roam_disconnect() - - * To disconnect from a network +/** + * csr_roam_disconnect() - To disconnect from a network + * @mac: pointer to mac context + * @session_id: Session ID + * @reason: CSR disconnect reason code as per @enum eCsrRoamDisconnectReason + * @mac_reason: Mac Disconnect reason code as per @enum eSirMacReasonCodes * - * Reason -- To indicate the reason for disconnecting. Currently, only - * eCSR_DISCONNECT_REASON_MIC_ERROR is meanful. * Return QDF_STATUS */ QDF_STATUS csr_roam_disconnect(tpAniSirGlobal pMac, uint32_t sessionId, - eCsrRoamDisconnectReason reason); + eCsrRoamDisconnectReason reason, + tSirMacReasonCodes mac_reason); /* This function is used to stop a BSS. It is similar of csr_roamIssueDisconnect * but this function doesn't have any logic other than blindly trying to stop @@ -985,8 +982,6 @@ QDF_STATUS csr_dequeue_roam_command(tpAniSirGlobal pMac, enum csr_roam_reason reason, uint8_t session_id); void csr_init_occupied_channels_list(tpAniSirGlobal pMac, uint8_t sessionId); -bool csr_neighbor_roam_is_new_connected_profile(tpAniSirGlobal pMac, - uint8_t sessionId); bool csr_neighbor_roam_connected_profile_match(tpAniSirGlobal pMac, uint8_t sessionId, struct tag_csrscan_result @@ -1004,6 +999,26 @@ QDF_STATUS csr_roam_del_pmkid_from_cache(tpAniSirGlobal pMac, tPmkidCacheInfo *pmksa, bool flush_cache); +#if defined(WLAN_SAE_SINGLE_PMK) && defined(WLAN_FEATURE_ROAM_OFFLOAD) +/** + * csr_clear_sae_single_pmk - API to clear single_pmk_info cache + * @pMac: Mac context + * @vdev_id: session id + * @pmksa: pmk info + * + * Return : None + */ +void csr_clear_sae_single_pmk(tpAniSirGlobal pMac, uint8_t vdev_id, + tPmkidCacheInfo *pmksa); + +#else +static inline void +csr_clear_sae_single_pmk(tpAniSirGlobal pMac, uint8_t vdev_id, + tPmkidCacheInfo *pmksa) +{ +} +#endif + bool csr_elected_country_info(tpAniSirGlobal pMac); void csr_add_vote_for_country_info(tpAniSirGlobal pMac, uint8_t *pCountryCode); void csr_clear_votes_for_country_info(tpAniSirGlobal pMac); diff --git a/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_neighbor_roam.c b/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_neighbor_roam.c index f9437242de47..2aa1ef80a737 100644 --- a/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_neighbor_roam.c +++ b/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_neighbor_roam.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -60,8 +60,7 @@ void csr_neighbor_roam_state_transition(tpAniSirGlobal mac_ctx, mac_ctx->roam.neighborRoamInfo[session].prevNeighborRoamState = mac_ctx->roam.neighborRoamInfo[session].neighborRoamState; mac_ctx->roam.neighborRoamInfo[session].neighborRoamState = newstate; - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - FL("Sessionid (%d) NeighborRoam transition from %s to %s"), + sme_nofl_debug("NeighborRoam transition: vdev %d %s --> %s", session, csr_neighbor_roam_state_to_string( mac_ctx->roam.neighborRoamInfo[session].prevNeighborRoamState), csr_neighbor_roam_state_to_string(newstate)); @@ -334,6 +333,18 @@ static void csr_neighbor_roam_reset_init_state_control_info(tpAniSirGlobal pMac, csr_neighbor_roam_reset_report_scan_state_control_info(pMac, sessionId); } +#ifdef WLAN_FEATURE_11W +void +csr_update_pmf_cap_from_connected_profile(tCsrRoamConnectedProfile *profile, + struct scan_filter *filter) +{ + if (profile->MFPCapable || profile->MFPEnabled) + filter->pmf_cap = WLAN_PMF_CAPABLE; + if (profile->MFPRequired) + filter->pmf_cap = WLAN_PMF_REQUIRED; +} +#endif + /** * csr_neighbor_roam_prepare_scan_profile_filter() * @@ -722,45 +733,6 @@ static bool csr_neighbor_roam_is_ssid_and_security_match(tpAniSirGlobal pMac, } -bool csr_neighbor_roam_is_new_connected_profile(tpAniSirGlobal pMac, - uint8_t sessionId) -{ - tpCsrNeighborRoamControlInfo pNeighborRoamInfo = - &pMac->roam.neighborRoamInfo[sessionId]; - tCsrRoamConnectedProfile *pCurrProfile = NULL; - tCsrRoamConnectedProfile *pPrevProfile = NULL; - tDot11fBeaconIEs *pIes = NULL; - tSirBssDescription *pBssDesc = NULL; - bool fNew = true; - - if (!(pMac->roam.roamSession && CSR_IS_SESSION_VALID(pMac, sessionId))) - return fNew; - - pCurrProfile = &pMac->roam.roamSession[sessionId].connectedProfile; - if (!pCurrProfile) - return fNew; - - pPrevProfile = &pNeighborRoamInfo->prevConnProfile; - if (!pPrevProfile) - return fNew; - - pBssDesc = pPrevProfile->pBssDesc; - if (pBssDesc) { - if (QDF_IS_STATUS_SUCCESS( - csr_get_parsed_bss_description_ies(pMac, pBssDesc, &pIes)) - && csr_neighbor_roam_is_ssid_and_security_match(pMac, - pCurrProfile, pBssDesc, pIes)) { - fNew = false; - } - if (pIes) - qdf_mem_free(pIes); - } - - sme_debug("roam profile match: %d", !fNew); - - return fNew; -} - bool csr_neighbor_roam_connected_profile_match(tpAniSirGlobal pMac, uint8_t sessionId, struct tag_csrscan_result @@ -800,14 +772,34 @@ void csr_roam_reset_roam_params(tpAniSirGlobal mac_ctx) * clear all the whitelist parameters and remaining * needs to be retained across connections. */ - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - FL("Roaming parameters are reset")); roam_params = &mac_ctx->roam.configParam.roam_params; roam_params->num_ssid_allowed_list = 0; qdf_mem_zero(&roam_params->ssid_allowed_list, sizeof(tSirMacSSid) * MAX_SSID_ALLOWED_LIST); } +#if defined(WLAN_FEATURE_HOST_ROAM) || defined(WLAN_FEATURE_ROAM_OFFLOAD) +static void csr_roam_restore_default_config(tpAniSirGlobal mac_ctx, + uint8_t vdev_id) +{ + struct roam_triggers triggers; + + sme_set_roam_config_enable(MAC_HANDLE(mac_ctx), vdev_id, 0); + + triggers.vdev_id = vdev_id; + triggers.trigger_bitmap = mac_ctx->roam.configParam.roam_triggers; + sme_debug("Reset roam trigger bitmap to 0x%x", triggers.trigger_bitmap); + sme_set_roam_triggers(MAC_HANDLE(mac_ctx), &triggers); + sme_roam_control_restore_default_config(MAC_HANDLE(mac_ctx), + vdev_id); +} +#else +static void csr_roam_restore_default_config(tpAniSirGlobal mac_ctx, + uint8_t vdev_id) +{ +} +#endif + /** * csr_neighbor_roam_indicate_disconnect() - To indicate disconnect * @pMac: The handle returned by mac_open @@ -845,12 +837,7 @@ QDF_STATUS csr_neighbor_roam_indicate_disconnect(tpAniSirGlobal pMac, */ csr_roam_free_connect_profile(pPrevProfile); csr_roam_copy_connect_profile(pMac, sessionId, pPrevProfile); - /* - * clear the roaming parameters that are per connection. - * For a new connection, they have to be programmed again. - */ - if (!csr_neighbor_middle_of_roaming(pMac, sessionId)) - csr_roam_reset_roam_params(pMac); + if (NULL != pSession) { roam_session = &pMac->roam.roamSession[sessionId]; if (NULL != pSession->pCurRoamProfile && (QDF_STA_MODE != @@ -939,6 +926,16 @@ QDF_STATUS csr_neighbor_roam_indicate_disconnect(tpAniSirGlobal pMac, pNeighborRoamInfo->uOsRequestedHandoff = 0; break; } + + /* + * clear the roaming parameters that are per connection. + * For a new connection, they have to be programmed again. + */ + if (!csr_neighbor_middle_of_roaming(pMac, sessionId)) { + csr_roam_reset_roam_params(pMac); + csr_roam_restore_default_config(pMac, sessionId); + } + /*Inform the Firmware to STOP Scanning as the host has a disconnect. */ if (csr_roam_is_sta_mode(pMac, sessionId)) { csr_roam_offload_scan(pMac, sessionId, ROAM_SCAN_OFFLOAD_STOP, @@ -994,6 +991,22 @@ static void csr_neighbor_roam_info_ctx_init( ngbr_roam_info->cfgParams.nRoamBmissFinalBcnt; ngbr_roam_info->currentRoamBeaconRssiWeight = ngbr_roam_info->cfgParams.nRoamBeaconRssiWeight; + /* + * Restore the inactivity params only if roam_control is not + * enabled. If roam_control is enabled, the params will be restored + * through sme_restore_default_roaming_params() while disabling + * the same. + */ + if (!ngbr_roam_info->roam_control_enable) { + ngbr_roam_info->cfgParams.enable_scoring_for_roam = + pMac->roam.configParam.bss_score_params.enable_scoring_for_roam; + ngbr_roam_info->cfgParams.roam_scan_inactivity_time = + pMac->roam.configParam.roam_scan_inactivity_time; + ngbr_roam_info->cfgParams.roam_inactive_data_packet_count = + pMac->roam.configParam.roam_inactive_data_packet_count; + ngbr_roam_info->cfgParams.roam_scan_period_after_inactivity = + pMac->roam.configParam.roam_scan_period_after_inactivity; + } /* * Now we can clear the preauthDone that @@ -1011,8 +1024,6 @@ static void csr_neighbor_roam_info_ctx_init( ngbr_roam_info->is11rAssoc = true; } else ngbr_roam_info->is11rAssoc = false; - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - FL("11rAssoc is = %d"), ngbr_roam_info->is11rAssoc); #ifdef FEATURE_WLAN_ESE /* Based on the auth scheme tell if we are 11r */ @@ -1022,9 +1033,6 @@ static void csr_neighbor_roam_info_ctx_init( ngbr_roam_info->isESEAssoc = true; } else ngbr_roam_info->isESEAssoc = false; - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - FL("isESEAssoc is = %d ft = %d"), - ngbr_roam_info->isESEAssoc, init_ft_flag); #endif /* If "FastRoamEnabled" ini is enabled */ if (csr_roam_is_fast_roam_enabled(pMac, session_id)) @@ -1052,9 +1060,6 @@ static void csr_neighbor_roam_info_ctx_init( #ifdef WLAN_FEATURE_ROAM_OFFLOAD if (session->roam_synch_in_progress) { if (pMac->roam.pReassocResp != NULL) { - QDF_TRACE(QDF_MODULE_ID_SME, - QDF_TRACE_LEVEL_DEBUG, - "Free Reassoc Rsp"); qdf_mem_free(pMac->roam.pReassocResp); pMac->roam.pReassocResp = NULL; } @@ -1096,7 +1101,7 @@ QDF_STATUS csr_neighbor_roam_indicate_connect( &pMac->roam.neighborRoamInfo[session_id]; struct csr_roam_session *session = &pMac->roam.roamSession[session_id]; #ifdef WLAN_FEATURE_ROAM_OFFLOAD - struct csr_roam_info roamInfo; + struct csr_roam_info *roam_info; #endif QDF_STATUS status = QDF_STATUS_SUCCESS; @@ -1106,16 +1111,16 @@ QDF_STATUS csr_neighbor_roam_indicate_connect( return QDF_STATUS_E_FAILURE; } - sme_debug("Connect ind. received with session id %d in state %s", + sme_debug("Connect ind, vdev id %d in state %s", session_id, mac_trace_get_neighbour_roam_state( ngbr_roam_info->neighborRoamState)); /* Bail out if this is NOT a STA persona */ if (pMac->roam.roamSession[session_id].pCurRoamProfile->csrPersona != QDF_STA_MODE) { - sme_err("Ignoring Connect ind received from a non STA. session_id: %d, csrPersonna %d", - session_id, - (int)session->pCurRoamProfile->csrPersona); + sme_debug("Ignoring Connect ind received from a non STA. session_id: %d, csrPersonna %d", + session_id, + (int)session->pCurRoamProfile->csrPersona); return QDF_STATUS_SUCCESS; } /* if a concurrent session is running */ @@ -1130,18 +1135,21 @@ QDF_STATUS csr_neighbor_roam_indicate_connect( if (session->roam_synch_in_progress && (eSIR_ROAM_AUTH_STATUS_AUTHENTICATED == session->roam_synch_data->authStatus)) { - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - "LFR3:csr_neighbor_roam_indicate_connect"); - qdf_copy_macaddr(&roamInfo.peerMac, - &session->connectedProfile.bssid); - roamInfo.roamSynchInProgress = + sme_debug("LFR3: Authenticated"); + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return QDF_STATUS_E_NOMEM; + qdf_copy_macaddr(&roam_info->peerMac, + &session->connectedProfile.bssid); + roam_info->roamSynchInProgress = session->roam_synch_in_progress; - csr_roam_call_callback(pMac, session_id, &roamInfo, 0, - eCSR_ROAM_SET_KEY_COMPLETE, - eCSR_ROAM_RESULT_AUTHENTICATED); + csr_roam_call_callback(pMac, session_id, roam_info, 0, + eCSR_ROAM_SET_KEY_COMPLETE, + eCSR_ROAM_RESULT_AUTHENTICATED); csr_neighbor_roam_reset_init_state_control_info(pMac, - session_id); + session_id); csr_neighbor_roam_info_ctx_init(pMac, session_id); + qdf_mem_free(roam_info); return status; } #endif @@ -1284,9 +1292,8 @@ QDF_STATUS csr_neighbor_roam_init(tpAniSirGlobal pMac, uint8_t sessionId) pNeighborRoamInfo->cfgParams.full_roam_scan_period = pMac->roam.configParam.neighborRoamConfig. full_roam_scan_period; - pNeighborRoamInfo->cfgParams.enable_scoring_for_roam = - pMac->roam.configParam.neighborRoamConfig. - enable_scoring_for_roam; + pNeighborRoamInfo->cfgParams.roam_trigger_bitmap = + pMac->roam.configParam.roam_triggers; specific_chan_info = &pNeighborRoamInfo->cfgParams.specific_chan_info; specific_chan_info->numOfChannels = @@ -1325,8 +1332,7 @@ QDF_STATUS csr_neighbor_roam_init(tpAniSirGlobal pMac, uint8_t sessionId) pMac->roam.configParam.neighborRoamConfig. nhi_rssi_scan_rssi_ub; pNeighborRoamInfo->cfgParams.roam_rssi_diff = - pMac->roam.configParam.neighborRoamConfig. - roam_rssi_diff; + pMac->roam.configParam.RoamRssiDiff; qdf_zero_macaddr(&pNeighborRoamInfo->currAPbssid); pNeighborRoamInfo->currentNeighborLookupThreshold = diff --git a/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_roam_preauth.c b/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_roam_preauth.c index de7798f62638..11bef8df4ba6 100644 --- a/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_roam_preauth.c +++ b/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_roam_preauth.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -581,7 +581,7 @@ void csr_roam_ft_pre_auth_rsp_processor(tpAniSirGlobal mac_ctx, tpSirFTPreAuthRsp preauth_rsp) { QDF_STATUS status = QDF_STATUS_SUCCESS; - struct csr_roam_info roam_info; + struct csr_roam_info *roam_info; eCsrAuthType conn_Auth_type; uint32_t session_id = preauth_rsp->smeSessionId; struct csr_roam_session *csr_session = CSR_GET_SESSION(mac_ctx, @@ -623,6 +623,10 @@ void csr_roam_ft_pre_auth_rsp_processor(tpAniSirGlobal mac_ctx, status); return; } + + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return; qdf_mem_copy((void *)&csr_session->ftSmeContext.preAuthbssId, (void *)preauth_rsp->preAuthbssId, sizeof(struct qdf_mac_addr)); @@ -632,26 +636,28 @@ void csr_roam_ft_pre_auth_rsp_processor(tpAniSirGlobal mac_ctx, #ifdef FEATURE_WLAN_ESE if (csr_roam_is_ese_assoc(mac_ctx, preauth_rsp->smeSessionId)) { - csr_roam_read_tsf(mac_ctx, (uint8_t *) roam_info.timestamp, - preauth_rsp->smeSessionId); - qdf_mem_copy((void *)&roam_info.bssid, - (void *)preauth_rsp->preAuthbssId, - sizeof(struct qdf_mac_addr)); + csr_roam_read_tsf(mac_ctx, (uint8_t *)&roam_info->timestamp, + preauth_rsp->smeSessionId); + qdf_mem_copy((void *)&roam_info->bssid, + (void *)preauth_rsp->preAuthbssId, + sizeof(struct qdf_mac_addr)); csr_roam_call_callback(mac_ctx, preauth_rsp->smeSessionId, - &roam_info, 0, eCSR_ROAM_CCKM_PREAUTH_NOTIFY, - 0); + roam_info, 0, + eCSR_ROAM_CCKM_PREAUTH_NOTIFY, 0); } #endif if (csr_roam_is_fast_roam_enabled(mac_ctx, preauth_rsp->smeSessionId)) { /* Save the bssid from the received response */ - qdf_mem_copy((void *)&roam_info.bssid, - (void *)preauth_rsp->preAuthbssId, - sizeof(struct qdf_mac_addr)); + qdf_mem_copy((void *)&roam_info->bssid, + (void *)preauth_rsp->preAuthbssId, + sizeof(struct qdf_mac_addr)); csr_roam_call_callback(mac_ctx, preauth_rsp->smeSessionId, - &roam_info, 0, eCSR_ROAM_PMK_NOTIFY, 0); + roam_info, 0, eCSR_ROAM_PMK_NOTIFY, 0); } + qdf_mem_free(roam_info); + /* If its an Open Auth, FT IEs are not provided by supplicant */ /* Hence populate them here */ conn_Auth_type = diff --git a/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_util.c b/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_util.c index 44a67c9045fc..3ef157164401 100644 --- a/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_util.c +++ b/drivers/staging/qcacld-3.0/core/sme/src/csr/csr_util.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -53,6 +53,9 @@ uint8_t csr_wpa_oui[][CSR_WPA_OUI_SIZE] = { #endif /* FEATURE_WLAN_ESE */ }; +#define FT_PSK_IDX 4 +#define FT_8021X_IDX 3 + /* * PLEASE DO NOT ADD THE #IFDEF IN BELOW TABLE, * IF STILL REQUIRE THEN PLEASE ADD NULL ENTRIES @@ -126,6 +129,12 @@ uint8_t csr_rsn_oui[][CSR_RSN_OUI_SIZE] = { {0x00, 0x00, 0x00, 0x00}, {0x00, 0x00, 0x00, 0x00}, #endif +#define ENUM_OSEN 21 + /* OSEN RSN */ + {0x50, 0x6F, 0x9A, 0x01}, +#define ENUM_FT_SUITEB_SHA384 22 + /* FT Suite-B SHA384 */ + {0x00, 0x0F, 0xAC, 0x0D}, /* define new oui here, update #define CSR_OUI_***_INDEX */ }; @@ -294,6 +303,7 @@ const char *get_e_roam_cmd_status_str(eRoamCmdStatus val) CASE_RETURN_STR(eCSR_ROAM_NAPI_OFF); CASE_RETURN_STR(eCSR_ROAM_CHANNEL_COMPLETE_IND); CASE_RETURN_STR(eCSR_ROAM_SAE_COMPUTE); + CASE_RETURN_STR(eCSR_ROAM_FIPS_PMK_REQUEST); default: return "unknown"; } @@ -1035,8 +1045,6 @@ uint16_t csr_check_concurrent_channel_overlap(tpAniSirGlobal mac_ctx, uint16_t sap_lfreq, sap_hfreq, intf_lfreq, intf_hfreq, sap_cch = 0; QDF_STATUS status; - sme_debug("sap_ch: %d sap_phymode: %d", sap_ch, sap_phymode); - if (mac_ctx->roam.configParam.cc_switch_mode == QDF_MCC_TO_SCC_SWITCH_DISABLE) return 0; @@ -1090,9 +1098,6 @@ uint16_t csr_check_concurrent_channel_overlap(tpAniSirGlobal mac_ctx, session, &sap_ch, &sap_hbw, &sap_cfreq, &intf_ch, &intf_hbw, &intf_cfreq); - sme_debug("%d: sap_ch:%d sap_hbw:%d sap_cfreq:%d intf_ch:%d intf_hbw:%d, intf_cfreq:%d", - i, sap_ch, sap_hbw, sap_cfreq, - intf_ch, intf_hbw, intf_cfreq); } if (intf_ch && ((intf_ch > 14 && sap_ch > 14) || (intf_ch <= 14 && sap_ch <= 14))) @@ -1100,8 +1105,8 @@ uint16_t csr_check_concurrent_channel_overlap(tpAniSirGlobal mac_ctx, } sme_debug("intf_ch:%d sap_ch:%d cc_switch_mode:%d, dbs:%d", - intf_ch, sap_ch, cc_switch_mode, - policy_mgr_is_dbs_enable(mac_ctx->psoc)); + intf_ch, sap_ch, cc_switch_mode, + policy_mgr_is_dbs_enable(mac_ctx->psoc)); if (intf_ch && sap_ch != intf_ch && !policy_mgr_is_force_scc(mac_ctx->psoc)) { @@ -1110,12 +1115,13 @@ uint16_t csr_check_concurrent_channel_overlap(tpAniSirGlobal mac_ctx, intf_lfreq = intf_cfreq - intf_hbw; intf_hfreq = intf_cfreq + intf_hbw; - sme_err("SAP: OCH: %03d OCF: %d CCH: %03d CF: %d BW: %d LF: %d HF: %d INTF: OCH: %03d OCF: %d CCH: %03d CF: %d BW: %d LF: %d HF: %d", - sap_ch, cds_chan_to_freq(sap_ch), - cds_freq_to_chan(sap_cfreq), sap_cfreq, sap_hbw * 2, - sap_lfreq, sap_hfreq, intf_ch, - cds_chan_to_freq(intf_ch), cds_freq_to_chan(intf_cfreq), - intf_cfreq, intf_hbw * 2, intf_lfreq, intf_hfreq); + sme_debug("SAP: OCH: %03d OCF: %d CCH: %03d CF: %d BW: %d LF: %d HF: %d INTF: OCH: %03d OCF: %d CCH: %03d CF: %d BW: %d LF: %d HF: %d", + sap_ch, cds_chan_to_freq(sap_ch), + cds_freq_to_chan(sap_cfreq), sap_cfreq, sap_hbw * 2, + sap_lfreq, sap_hfreq, intf_ch, + cds_chan_to_freq(intf_ch), + cds_freq_to_chan(intf_cfreq), + intf_cfreq, intf_hbw * 2, intf_lfreq, intf_hfreq); if (!(((sap_lfreq > intf_lfreq && sap_lfreq < intf_hfreq) || (sap_hfreq > intf_lfreq && sap_hfreq < intf_hfreq)) || @@ -1154,8 +1160,8 @@ uint16_t csr_check_concurrent_channel_overlap(tpAniSirGlobal mac_ctx, if (intf_ch == sap_ch) intf_ch = 0; - sme_err("##Concurrent Channels %s Interfering", - intf_ch == 0 ? "Not" : "Are"); + sme_debug("##Concurrent Channels %s Interfering", + intf_ch == 0 ? "Not" : "Are"); return intf_ch; } #endif @@ -1755,7 +1761,6 @@ uint32_t csr_translate_to_wni_cfg_dot11_mode(tpAniSirGlobal pMac, switch (csrDot11Mode) { case eCSR_CFG_DOT11_MODE_AUTO: - sme_debug("eCSR_CFG_DOT11_MODE_AUTO"); if (IS_FEATURE_SUPPORTED_BY_FW(DOT11AX)) ret = WNI_CFG_DOT11_MODE_11AX; else if (IS_FEATURE_SUPPORTED_BY_FW(DOT11AC)) @@ -2306,9 +2311,11 @@ bool csr_is_profile_rsn(struct csr_roam_profile *pProfile) case eCSR_AUTH_TYPE_OWE: case eCSR_AUTH_TYPE_SUITEB_EAP_SHA256: case eCSR_AUTH_TYPE_SUITEB_EAP_SHA384: + case eCSR_AUTH_TYPE_FT_SUITEB_EAP_SHA384: fRSNProfile = true; break; case eCSR_AUTH_TYPE_SAE: + case eCSR_AUTH_TYPE_FT_SAE: fRSNProfile = true; break; @@ -2588,7 +2595,7 @@ static bool csr_validate_sta_bcn_intrvl(tpAniSirGlobal mac_ctx, * MCC should not be enabled so making it * false to enforce on same channel */ - sme_err("*** MCC with SAP+STA sessions ****"); + sme_debug("*** MCC with SAP+STA sessions ****"); *status = QDF_STATUS_SUCCESS; return true; } @@ -2748,6 +2755,10 @@ bool csr_is_auth_type11r(tpAniSirGlobal mac, eCsrAuthType auth_type, break; case eCSR_AUTH_TYPE_FT_RSN_PSK: case eCSR_AUTH_TYPE_FT_RSN: + case eCSR_AUTH_TYPE_FT_SAE: + case eCSR_AUTH_TYPE_FT_SUITEB_EAP_SHA384: + case eCSR_AUTH_TYPE_FT_FILS_SHA256: + case eCSR_AUTH_TYPE_FT_FILS_SHA384: return true; default: break; @@ -3144,6 +3155,24 @@ static bool csr_is_auth_suiteb_eap_384(tpAniSirGlobal mac, csr_rsn_oui[ENUM_SUITEB_EAP384], oui); } +/* + * csr_is_auth_ft_suiteb_eap_384() - check whether oui is SuiteB EAP384 + * @mac: Global MAC context + * @all_suites: pointer to all supported akm suites + * @suite_count: all supported akm suites count + * @oui: Oui needs to be matched + * + * Return: True if OUI is FT SuiteB EAP384, false otherwise + */ +static +bool csr_is_auth_ft_suiteb_eap_384(tpAniSirGlobal mac, + uint8_t all_suites[][CSR_RSN_OUI_SIZE], + uint8_t suite_count, uint8_t oui[]) +{ + return csr_is_oui_match(mac, all_suites, suite_count, + csr_rsn_oui[ENUM_FT_SUITEB_SHA384], oui); +} + #ifdef WLAN_FEATURE_SAE /* * csr_is_auth_wpa_sae() - check whether oui is SAE @@ -3158,8 +3187,31 @@ static bool csr_is_auth_wpa_sae(tpAniSirGlobal mac, uint8_t all_suites[][CSR_RSN_OUI_SIZE], uint8_t suite_count, uint8_t oui[]) { - return csr_is_oui_match - (mac, all_suites, suite_count, csr_rsn_oui[ENUM_SAE], oui); + bool is_sae_auth; + + is_sae_auth = (csr_is_oui_match(mac, all_suites, suite_count, + csr_rsn_oui[ENUM_SAE], oui)); + return is_sae_auth; +} + +/* + * csr_is_auth_ft_sae() - check whether oui is SAE + * @mac: Global MAC context + * @all_suites: pointer to all supported akm suites + * @suite_count: all supported akm suites count + * @oui: Oui needs to be matched + * + * Return: True if OUI is FT-SAE, false otherwise + */ +static bool csr_is_auth_ft_sae(tpAniSirGlobal mac, + uint8_t all_suites[][CSR_RSN_OUI_SIZE], + uint8_t suite_count, uint8_t oui[]) +{ + bool is_ft_sae_auth; + + is_ft_sae_auth = csr_is_oui_match(mac, all_suites, suite_count, + csr_rsn_oui[ENUM_FT_SAE], oui); + return is_ft_sae_auth; } #endif @@ -3316,7 +3368,8 @@ static void csr_is_fils_auth(tpAniSirGlobal mac_ctx, #ifdef WLAN_FEATURE_SAE /** - * csr_check_sae_auth() - update negotiated auth if matches to SAE auth type + * csr_check_sae_auth() - update negotiated auth and oui if matches to SAE auth + * type * @mac_ctx: pointer to mac context * @authsuites: auth suites * @c_auth_suites: auth suites count @@ -3327,17 +3380,28 @@ static void csr_is_fils_auth(tpAniSirGlobal mac_ctx, * * Return: None */ -static void csr_check_sae_auth(tpAniSirGlobal mac_ctx, - uint8_t authsuites[][CSR_RSN_OUI_SIZE], uint8_t c_auth_suites, - uint8_t authentication[], tCsrAuthList *auth_type, - uint8_t index, eCsrAuthType *neg_authtype) +static void +csr_check_sae_auth(tpAniSirGlobal mac_ctx, + uint8_t authsuites[][CSR_RSN_OUI_SIZE], + uint8_t c_auth_suites, + uint8_t authentication[], tCsrAuthList *auth_type, + uint8_t index, eCsrAuthType *neg_authtype) { if ((*neg_authtype == eCSR_AUTH_TYPE_UNKNOWN) && - csr_is_auth_wpa_sae(mac_ctx, authsuites, - c_auth_suites, authentication)) { + csr_is_auth_ft_sae(mac_ctx, authsuites, c_auth_suites, + authentication)) { + if (eCSR_AUTH_TYPE_FT_SAE == auth_type->authType[index]) + *neg_authtype = eCSR_AUTH_TYPE_FT_SAE; + else if (eCSR_AUTH_TYPE_OPEN_SYSTEM == auth_type->authType[index]) + *neg_authtype = eCSR_AUTH_TYPE_OPEN_SYSTEM; + } + + if ((*neg_authtype == eCSR_AUTH_TYPE_UNKNOWN) && + csr_is_auth_wpa_sae(mac_ctx, authsuites, + c_auth_suites, authentication)) { if (eCSR_AUTH_TYPE_SAE == auth_type->authType[index]) *neg_authtype = eCSR_AUTH_TYPE_SAE; - if (eCSR_AUTH_TYPE_OPEN_SYSTEM == auth_type->authType[index]) + else if (eCSR_AUTH_TYPE_OPEN_SYSTEM == auth_type->authType[index]) *neg_authtype = eCSR_AUTH_TYPE_OPEN_SYSTEM; } sme_debug("negotiated auth type is %d", *neg_authtype); @@ -3366,6 +3430,7 @@ static void csr_check_sae_auth(tpAniSirGlobal mac_ctx, * @negotiated_mccipher: negotiated multicast cipher * @gp_mgmt_cipher: group management cipher * @mgmt_encryption_type: group management encryption type + * @adaptive_11r: is adaptive 11r connection * * This routine will get all RSN information * @@ -3381,7 +3446,8 @@ static bool csr_get_rsn_information(tpAniSirGlobal mac_ctx, eCsrAuthType *negotiated_authtype, eCsrEncryptionType *negotiated_mccipher, uint8_t *gp_mgmt_cipher, - tAniEdType *mgmt_encryption_type) + tAniEdType *mgmt_encryption_type, + bool adaptive_11r) { bool acceptable_cipher = false; bool group_mgmt_acceptable_cipher = false; @@ -3501,29 +3567,78 @@ static bool csr_get_rsn_information(tpAniSirGlobal mac_ctx, neg_authtype = eCSR_AUTH_TYPE_CCKM_RSN; } #endif - if ((neg_authtype == eCSR_AUTH_TYPE_UNKNOWN) - && csr_is_auth_rsn(mac_ctx, authsuites, - c_auth_suites, authentication)) { + if (neg_authtype == eCSR_AUTH_TYPE_UNKNOWN && + csr_is_auth_rsn(mac_ctx, authsuites, + c_auth_suites, authentication)) { + /* + * For adaptive 11r connection send FT-802.1X akm in + * association request + */ + if (adaptive_11r && + eCSR_AUTH_TYPE_FT_RSN == auth_type->authType[i]) { + neg_authtype = eCSR_AUTH_TYPE_FT_RSN; + qdf_mem_copy(authentication, + csr_rsn_oui[FT_8021X_IDX], + CSR_WPA_OUI_SIZE); + } + if (eCSR_AUTH_TYPE_RSN == auth_type->authType[i]) neg_authtype = eCSR_AUTH_TYPE_RSN; } - if ((neg_authtype == eCSR_AUTH_TYPE_UNKNOWN) - && csr_is_auth_rsn_psk(mac_ctx, authsuites, + if (neg_authtype == eCSR_AUTH_TYPE_UNKNOWN && + csr_is_auth_rsn_psk(mac_ctx, authsuites, c_auth_suites, authentication)) { + /* + * For adaptive 11r connection send FT-PSK akm in + * association request + */ + if (adaptive_11r && + eCSR_AUTH_TYPE_FT_RSN_PSK == auth_type->authType[i]) { + neg_authtype = eCSR_AUTH_TYPE_FT_RSN_PSK; + qdf_mem_copy(authentication, + csr_rsn_oui[FT_PSK_IDX], + CSR_WPA_OUI_SIZE); + } + if (eCSR_AUTH_TYPE_RSN_PSK == auth_type->authType[i]) neg_authtype = eCSR_AUTH_TYPE_RSN_PSK; } #ifdef WLAN_FEATURE_11W - if ((neg_authtype == eCSR_AUTH_TYPE_UNKNOWN) - && csr_is_auth_rsn_psk_sha256(mac_ctx, authsuites, - c_auth_suites, authentication)) { + if (neg_authtype == eCSR_AUTH_TYPE_UNKNOWN && + csr_is_auth_rsn_psk_sha256(mac_ctx, authsuites, + c_auth_suites, authentication)) { + /* + * For adaptive 11r connection send AP advertises only + * PSK AKM. STA can choose FT-PSK akm in association + * request if FT capable. + */ + if (adaptive_11r && + eCSR_AUTH_TYPE_FT_RSN_PSK == auth_type->authType[i]) { + neg_authtype = eCSR_AUTH_TYPE_FT_RSN_PSK; + qdf_mem_copy(authentication, + csr_rsn_oui[FT_PSK_IDX], + CSR_WPA_OUI_SIZE); + } + if (eCSR_AUTH_TYPE_RSN_PSK_SHA256 == auth_type->authType[i]) neg_authtype = eCSR_AUTH_TYPE_RSN_PSK_SHA256; } if ((neg_authtype == eCSR_AUTH_TYPE_UNKNOWN) && - csr_is_auth_rsn8021x_sha256(mac_ctx, authsuites, - c_auth_suites, authentication)) { + csr_is_auth_rsn8021x_sha256(mac_ctx, + authsuites, c_auth_suites, + authentication)) { + /* + * For adaptive 11r connection send FT-802.1x akm in + * association request + */ + if (adaptive_11r && + eCSR_AUTH_TYPE_FT_RSN == auth_type->authType[i]) { + neg_authtype = eCSR_AUTH_TYPE_FT_RSN; + qdf_mem_copy(authentication, + csr_rsn_oui[FT_8021X_IDX], + CSR_WPA_OUI_SIZE); + } if (eCSR_AUTH_TYPE_RSN_8021X_SHA256 == auth_type->authType[i]) neg_authtype = eCSR_AUTH_TYPE_RSN_8021X_SHA256; @@ -3549,6 +3664,15 @@ static bool csr_get_rsn_information(tpAniSirGlobal mac_ctx, auth_type->authType[i]) neg_authtype = eCSR_AUTH_TYPE_SUITEB_EAP_SHA384; } + if ((neg_authtype == eCSR_AUTH_TYPE_UNKNOWN) && + csr_is_auth_ft_suiteb_eap_384(mac_ctx, authsuites, + c_auth_suites, + authentication)) { + if (eCSR_AUTH_TYPE_FT_SUITEB_EAP_SHA384 == + auth_type->authType[i]) + neg_authtype = + eCSR_AUTH_TYPE_FT_SUITEB_EAP_SHA384; + } /* * The 1st auth type in the APs RSN IE, to match stations @@ -3699,10 +3823,10 @@ static bool csr_is_rsn_match(tpAniSirGlobal mac_ctx, tCsrAuthList *pAuthType, * settings in the profile. */ fRSNMatch = csr_get_rsn_information(mac_ctx, pAuthType, enType, - pEnMcType, &pIes->RSN, - NULL, NULL, NULL, NULL, - pNegotiatedAuthType, - pNegotiatedMCCipher, NULL, NULL); + pEnMcType, &pIes->RSN, NULL, NULL, + NULL, NULL, pNegotiatedAuthType, + pNegotiatedMCCipher, NULL, NULL, + false); #ifdef WLAN_FEATURE_11W /* If all the filter matches then finally checks for PMF capabilities */ if (fRSNMatch) @@ -3991,7 +4115,8 @@ uint8_t csr_construct_rsn_ie(tpAniSirGlobal pMac, uint32_t sessionId, MulticastCypher, AuthSuite, &RSNCapabilities, &negAuthType, NULL, gp_mgmt_cipher_suite, - &pProfile->mgmt_encryption_type); + &pProfile->mgmt_encryption_type, + session->is_adaptive_11r_connection); if (!fRSNMatch) break; @@ -6208,7 +6333,6 @@ bool csr_is_set_key_allowed(tpAniSirGlobal pMac, uint32_t sessionId) * The current work-around is to process setcontext_rsp no matter * what the state is. */ - sme_debug("is not what it intends to. Must be revisit or removed"); if ((NULL == pSession) || (csr_is_conn_state_disconnected(pMac, sessionId) && (pSession->pCurRoamProfile != NULL) diff --git a/drivers/staging/qcacld-3.0/core/sme/src/qos/sme_qos.c b/drivers/staging/qcacld-3.0/core/sme/src/qos/sme_qos.c index 4aa4299b1f4e..8f3bc8f5f170 100644 --- a/drivers/staging/qcacld-3.0/core/sme/src/qos/sme_qos.c +++ b/drivers/staging/qcacld-3.0/core/sme/src/qos/sme_qos.c @@ -901,9 +901,7 @@ QDF_STATUS sme_qos_csr_event_ind(tpAniSirGlobal pMac, { QDF_STATUS status = QDF_STATUS_E_FAILURE; - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - "%s: %d: On Session %d Event %d received from CSR", - __func__, __LINE__, sessionId, ind); + sme_debug("On Session %d Event %d received from CSR", sessionId, ind); switch (ind) { case SME_QOS_CSR_ASSOC_COMPLETE: /* expecting assoc info in pEvent_info */ @@ -961,14 +959,11 @@ QDF_STATUS sme_qos_csr_event_ind(tpAniSirGlobal pMac, break; default: /* Err msg */ - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_ERROR, - "%s: %d: On Session %d Unknown Event %d received from CSR", - __func__, __LINE__, sessionId, ind); + sme_err("On Session %d Unknown Event %d received from CSR", + sessionId, ind); break; } - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - "%s: %d: On Session %d processed Event %d with status %d", - __func__, __LINE__, sessionId, ind, status); + return status; } @@ -4949,21 +4944,15 @@ static QDF_STATUS sme_qos_process_join_req_ev(tpAniSirGlobal pMac, uint8_t struct sme_qos_sessioninfo *pSession; sme_QosEdcaAcType ac; - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - "%s: %d: invoked on session %d", - __func__, __LINE__, sessionId); pSession = &sme_qos_cb.sessionInfo[sessionId]; if (pSession->handoffRequested) { - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - "%s: %d: no need for state transition, should already be in handoff state", - __func__, __LINE__); + sme_debug("No need for state transition, should already be in handoff state"); if ((pSession->ac_info[0].curr_state != SME_QOS_HANDOFF) || (pSession->ac_info[1].curr_state != SME_QOS_HANDOFF) || (pSession->ac_info[2].curr_state != SME_QOS_HANDOFF) || (pSession->ac_info[3].curr_state != SME_QOS_HANDOFF)) - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_ERROR, - FL("curr_state is not HANDOFF, session %d"), - sessionId); + sme_err("curr_state is not HANDOFF, session %d", + sessionId); /* buffer the existing flows to be renewed after handoff is * done */ @@ -5815,10 +5804,10 @@ static void sme_qos_state_transition(uint8_t sessionId, pACInfo = &pSession->ac_info[ac]; pACInfo->prev_state = pACInfo->curr_state; pACInfo->curr_state = new_state; - QDF_TRACE(QDF_MODULE_ID_SME, QDF_TRACE_LEVEL_DEBUG, - "%s: %d: On session %d new state=%d, old state=%d, for AC=%d", - __func__, __LINE__, - sessionId, pACInfo->curr_state, pACInfo->prev_state, ac); + if (pACInfo->curr_state != pACInfo->prev_state) + sme_debug("On session %d new %d old %d, for AC %d", + sessionId, pACInfo->curr_state, + pACInfo->prev_state, ac); } /** diff --git a/drivers/staging/qcacld-3.0/core/sme/src/rrm/sme_rrm.c b/drivers/staging/qcacld-3.0/core/sme/src/rrm/sme_rrm.c index 9548e5512afd..2501fd443efe 100644 --- a/drivers/staging/qcacld-3.0/core/sme/src/rrm/sme_rrm.c +++ b/drivers/staging/qcacld-3.0/core/sme/src/rrm/sme_rrm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -278,7 +278,7 @@ static QDF_STATUS sme_ese_send_beacon_req_scan_results( uint8_t bss_counter = 0; tCsrScanResultInfo *cur_result = NULL; tpRrmSMEContext rrm_ctx = &mac_ctx->rrm.rrmSmeContext; - struct csr_roam_info roam_info; + struct csr_roam_info *roam_info; tSirEseBcnReportRsp bcn_rpt_rsp; tpSirEseBcnReportRsp bcn_report = &bcn_rpt_rsp; tpCsrEseBeaconReqParams cur_meas_req = NULL; @@ -295,6 +295,10 @@ static QDF_STATUS sme_ese_send_beacon_req_scan_results( return QDF_STATUS_E_FAILURE; } + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return QDF_STATUS_E_NOMEM; + if (result_arr) cur_result = result_arr[bss_counter]; @@ -382,15 +386,17 @@ static QDF_STATUS sme_ese_send_beacon_req_scan_results( bcn_report->numBss, j, bss_counter, bcn_report->flag); - roam_info.pEseBcnReportRsp = bcn_report; - status = csr_roam_call_callback(mac_ctx, session_id, &roam_info, - 0, eCSR_ROAM_ESE_BCN_REPORT_IND, 0); + roam_info->pEseBcnReportRsp = bcn_report; + status = csr_roam_call_callback(mac_ctx, session_id, roam_info, + 0, eCSR_ROAM_ESE_BCN_REPORT_IND, + 0); /* Free the memory allocated to IE */ for (i = 0; i < j; i++) if (bcn_report->bcnRepBssInfo[i].pBuf) qdf_mem_free(bcn_report->bcnRepBssInfo[i].pBuf); } while (cur_result); + qdf_mem_free(roam_info); return status; } @@ -768,7 +774,7 @@ static QDF_STATUS sme_rrm_issue_scan_req(tpAniSirGlobal mac_ctx) sme_err("sme session ID not found for bssid= "MAC_ADDRESS_STR, MAC_ADDR_ARRAY(sme_rrm_ctx->sessionBssId.bytes)); status = QDF_STATUS_E_FAILURE; - goto free_ch_lst; + goto send_ind; } if ((sme_rrm_ctx->currentIndex) >= @@ -796,7 +802,7 @@ static QDF_STATUS sme_rrm_issue_scan_req(tpAniSirGlobal mac_ctx) if (!req) { sme_debug("Failed to allocate memory"); status = QDF_STATUS_E_NOMEM; - goto free_ch_lst; + goto send_ind; } vdev = wlan_objmgr_get_vdev_by_id_from_psoc( @@ -807,7 +813,7 @@ static QDF_STATUS sme_rrm_issue_scan_req(tpAniSirGlobal mac_ctx) sme_err("VDEV is null %d", session_id); status = QDF_STATUS_E_INVAL; qdf_mem_free(req); - goto free_ch_lst; + goto send_ind; } ucfg_scan_init_default_params(vdev, req); req->scan_req.scan_id = ucfg_scan_get_scan_id(mac_ctx->psoc); @@ -891,7 +897,7 @@ static QDF_STATUS sme_rrm_issue_scan_req(tpAniSirGlobal mac_ctx) status = ucfg_scan_start(req); wlan_objmgr_vdev_release_ref(vdev, WLAN_LEGACY_SME_ID); if (QDF_IS_STATUS_ERROR(status)) - goto free_ch_lst; + goto send_ind; return status; } else if (eSIR_BEACON_TABLE == scan_type) { @@ -925,23 +931,55 @@ static QDF_STATUS sme_rrm_issue_scan_req(tpAniSirGlobal mac_ctx) sme_rrm_ctx->currentIndex], true); goto free_ch_lst; } - } else { - sme_err("Unknown beacon report req mode(%d)", scan_type); - /* - * Indicate measurement completion to PE - * If this is not done, pCurrentReq pointer will not be freed - * and PE will not handle subsequent Beacon requests - */ - sme_rrm_send_beacon_report_xmit_ind(mac_ctx, NULL, true, 0); - goto free_ch_lst; } + sme_err("Unknown beacon report req mode(%d)", scan_type); + /* + * Indicate measurement completion to PE + * If this is not done, pCurrentReq pointer will not be freed + * and PE will not handle subsequent Beacon requests + */ +send_ind: + sme_rrm_send_beacon_report_xmit_ind(mac_ctx, NULL, true, 0); free_ch_lst: qdf_mem_free(sme_rrm_ctx->channelList.ChannelList); sme_rrm_ctx->channelList.ChannelList = NULL; return status; } +static QDF_STATUS sme_rrm_fill_scan_channels(uint8_t *country, + tpRrmSMEContext sme_rrm_context, + uint8_t reg_class, + uint32_t num_channels) +{ + uint32_t num_chan = 0; + uint32_t i; + + /* List all the channels in the requested RC */ + wlan_reg_dmn_print_channels_in_opclass(country, reg_class); + + for (i = 0; i < num_channels; i++) { + if (wlan_reg_dmn_get_opclass_from_channel(country, + sme_rrm_context->channelList.ChannelList[i], + BWALL) == + reg_class) { + sme_rrm_context->channelList. + ChannelList[num_chan] = + sme_rrm_context->channelList.ChannelList[i]; + num_chan++; + } + } + sme_rrm_context->channelList.numOfChannels = num_chan; + if (sme_rrm_context->channelList.numOfChannels == 0) { + qdf_mem_free(sme_rrm_context->channelList.ChannelList); + sme_rrm_context->channelList.ChannelList = NULL; + sme_err("No channels populated with requested operation class and current country, Hence abort the rrm operation"); + return QDF_STATUS_E_FAILURE; + } + + return QDF_STATUS_SUCCESS; +} + /** * sme_rrm_process_beacon_report_req_ind() -Process beacon report request * @pMac:- Global Mac structure @@ -960,15 +998,45 @@ QDF_STATUS sme_rrm_process_beacon_report_req_ind(tpAniSirGlobal pMac, tpSirBeaconReportReqInd pBeaconReq = (tpSirBeaconReportReqInd) pMsgBuf; tpRrmSMEContext pSmeRrmContext = &pMac->rrm.rrmSmeContext; uint32_t len = 0, i = 0; + uint8_t country[WNI_CFG_COUNTRY_CODE_LEN]; + uint32_t session_id; + struct csr_roam_session *session; + QDF_STATUS status; - sme_debug("Received Beacon report request ind Channel = %d", - pBeaconReq->channelInfo.channelNum); + status = csr_roam_get_session_id_from_bssid(pMac, (struct qdf_mac_addr *) + pBeaconReq->bssId, + &session_id); + if (QDF_IS_STATUS_ERROR(status)) { + sme_err("sme session ID not found for bssid"); + goto cleanup; + } + + session = CSR_GET_SESSION(pMac, session_id); + if (!session) { + sme_err("Invalid session id %d", session_id); + status = QDF_STATUS_E_FAILURE; + goto cleanup; + } + + qdf_mem_zero(country, WNI_CFG_COUNTRY_CODE_LEN); + if (session->connectedProfile.country_code[0]) + qdf_mem_copy(country, session->connectedProfile.country_code, + WNI_CFG_COUNTRY_CODE_LEN); + else + country[2] = OP_CLASS_GLOBAL; + + + sme_debug("Request Reg class %d, AP's country code %c%c 0x%x Channel %d", + pBeaconReq->channelInfo.regulatoryClass, + country[0], country[1], country[2], + pBeaconReq->channelInfo.channelNum); if (pBeaconReq->channelList.numChannels > SIR_ESE_MAX_MEAS_IE_REQS) { sme_err("Beacon report request numChannels:%u exceeds max num channels", pBeaconReq->channelList.numChannels); - return QDF_STATUS_E_INVAL; + status = QDF_STATUS_E_INVAL; + goto cleanup; } /* section 11.10.8.1 (IEEE Std 802.11k-2008) */ @@ -983,13 +1051,23 @@ QDF_STATUS sme_rrm_process_beacon_report_req_ind(tpAniSirGlobal pMac, pSmeRrmContext->channelList.ChannelList = NULL; } pSmeRrmContext->channelList.ChannelList = qdf_mem_malloc(len); - if (pSmeRrmContext->channelList.ChannelList == NULL) { - sme_err("qdf_mem_malloc failed"); - return QDF_STATUS_E_NOMEM; + if (!pSmeRrmContext->channelList.ChannelList) { + status = QDF_STATUS_E_NOMEM; + goto cleanup; } + csr_get_cfg_valid_channels(pMac, pSmeRrmContext->channelList. - ChannelList, &len); - pSmeRrmContext->channelList.numOfChannels = (uint8_t) len; + ChannelList, &len); + + if (pBeaconReq->channelInfo.regulatoryClass) { + if (sme_rrm_fill_scan_channels(country, pSmeRrmContext, + pBeaconReq->channelInfo. + regulatoryClass, len) != + QDF_STATUS_SUCCESS) + goto cleanup; + } else { + pSmeRrmContext->channelList.numOfChannels = len; + } } else { len = 0; pSmeRrmContext->channelList.numOfChannels = 0; @@ -1008,9 +1086,9 @@ QDF_STATUS sme_rrm_process_beacon_report_req_ind(tpAniSirGlobal pMac, pSmeRrmContext->channelList.ChannelList = NULL; } pSmeRrmContext->channelList.ChannelList = qdf_mem_malloc(len); - if (pSmeRrmContext->channelList.ChannelList == NULL) { - sme_err("qdf_mem_malloc failed"); - return QDF_STATUS_E_NOMEM; + if (!pSmeRrmContext->channelList.ChannelList) { + status = QDF_STATUS_E_NOMEM; + goto cleanup; } if (pBeaconReq->channelInfo.channelNum != 255) { @@ -1063,11 +1141,25 @@ QDF_STATUS sme_rrm_process_beacon_report_req_ind(tpAniSirGlobal pMac, (uint8_t *) &pBeaconReq->measurementDuration, SIR_ESE_MAX_MEAS_IE_REQS); - sme_debug("token: %d regClass: %d randnIntvl: %d msgSource: %d", - pSmeRrmContext->token, pSmeRrmContext->regClass, - pSmeRrmContext->randnIntvl, pSmeRrmContext->msgSource); + sme_debug("token: %d randnIntvl: %d msgSource: %d", + pSmeRrmContext->token, pSmeRrmContext->randnIntvl, + pSmeRrmContext->msgSource); return sme_rrm_issue_scan_req(pMac); + +cleanup: + if (pBeaconReq->msgSource == eRRM_MSG_SOURCE_11K) { + /* Copy session bssid */ + qdf_mem_copy(pSmeRrmContext->sessionBssId.bytes, + pBeaconReq->bssId, sizeof(tSirMacAddr)); + + /* copy measurement bssid */ + qdf_mem_copy(pSmeRrmContext->bssId, pBeaconReq->macaddrBssid, + sizeof(tSirMacAddr)); + sme_rrm_send_beacon_report_xmit_ind(pMac, NULL, true, 0); + } + + return status; } /** @@ -1432,7 +1524,7 @@ static void rrm_iter_meas_timer_handle(void *userData) { tpAniSirGlobal pMac = (tpAniSirGlobal) userData; - sme_warn("Randomization timer expired...send on next channel"); + sme_debug("Randomization timer expired...send on next channel"); /* Issue a scan req for next channel. */ sme_rrm_issue_scan_req(pMac); } diff --git a/drivers/staging/qcacld-3.0/core/wma/inc/wma.h b/drivers/staging/qcacld-3.0/core/wma/inc/wma.h index 2ac5866c782d..686f1a922d36 100644 --- a/drivers/staging/qcacld-3.0/core/wma/inc/wma.h +++ b/drivers/staging/qcacld-3.0/core/wma/inc/wma.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -44,6 +44,7 @@ #include "wlan_objmgr_psoc_obj.h" #include #include +#include "wmi_unified_param.h" /* Platform specific configuration for max. no. of fragments */ #define QCA_OL_11AC_TX_MAX_FRAGS 2 @@ -92,6 +93,17 @@ #define wma_debug(params...) QDF_TRACE_DEBUG(QDF_MODULE_ID_WMA, params) #define wma_err_rl(params...) QDF_TRACE_ERROR_RL(QDF_MODULE_ID_WMA, params) +#define wma_nofl_alert(params...) \ + QDF_TRACE_FATAL_NO_FL(QDF_MODULE_ID_WMA, params) +#define wma_nofl_err(params...) \ + QDF_TRACE_ERROR_NO_FL(QDF_MODULE_ID_WMA, params) +#define wma_nofl_warn(params...) \ + QDF_TRACE_WARN_NO_FL(QDF_MODULE_ID_WMA, params) +#define wma_nofl_info(params...) \ + QDF_TRACE_INFO_NO_FL(QDF_MODULE_ID_WMA, params) +#define wma_nofl_debug(params...) \ + QDF_TRACE_DEBUG_NO_FL(QDF_MODULE_ID_WMA, params) + #define WMA_DEBUG_ALWAYS #ifdef WMA_DEBUG_ALWAYS @@ -281,6 +293,8 @@ enum ds_mode { #define WMA_DEAUTH_RECV_WAKE_LOCK_DURATION WAKELOCK_DURATION_RECOMMENDED #define WMA_DISASSOC_RECV_WAKE_LOCK_DURATION WAKELOCK_DURATION_RECOMMENDED #define WMA_ROAM_HO_WAKE_LOCK_DURATION (500) /* in msec */ +#define WMA_ROAM_PREAUTH_WAKE_LOCK_DURATION (2 * 1000) + #ifdef FEATURE_WLAN_AUTO_SHUTDOWN #define WMA_AUTO_SHUTDOWN_WAKE_LOCK_DURATION WAKELOCK_DURATION_RECOMMENDED #endif @@ -1052,6 +1066,7 @@ struct wma_valid_channels { * @wow_ap_assoc_lost_wl: wow wake lock for assoc lost req * @wow_auto_shutdown_wl: wow wake lock for shutdown req * @roam_ho_wl: wake lock for roam handoff req + * @roam_preauth_wl: wake lock for roam preauth status * @wow_nack: wow negative ack flag * @is_wow_bus_suspended: is wow bus suspended flag * @wma_scan_comp_timer: scan completion timer @@ -1063,6 +1078,8 @@ struct wma_valid_channels { * @RArateLimitInterval: RA rate limit interval * @is_lpass_enabled: Flag to indicate if LPASS feature is enabled or not * @is_nan_enabled: Flag to indicate if NaN feature is enabled or not + * @nan_separate_iface_support: Flag to indicate whether separate iface for NAN + * is enabled or not * @staMaxLIModDtim: station max listen interval * @staModDtim: station mode DTIM * @staDynamicDtim: station dynamic DTIM @@ -1096,6 +1113,8 @@ struct wma_valid_channels { * event in the serialized MC thread context with a timer. * @csr_roam_synch_cb: CSR callback for firmware Roam Sync events * @pe_roam_synch_cb: pe callback for firmware Roam Sync events + * @csr_roam_auth_event_handle_cb: CSR callback for target authentication + * offload event. * @wmi_cmd_rsp_wake_lock: wmi command response wake lock * @wmi_cmd_rsp_runtime_lock: wmi command response bus lock * @apf_enabled: Is APF enabled in firmware? @@ -1135,7 +1154,7 @@ struct wma_valid_channels { typedef struct { void *wmi_handle; void *cds_context; - void *mac_context; + tAniSirGlobal *mac_context; struct wlan_objmgr_psoc *psoc; struct wlan_objmgr_pdev *pdev; qdf_event_t wma_resume_event; @@ -1202,6 +1221,7 @@ typedef struct { qdf_wake_lock_t wow_ap_assoc_lost_wl; qdf_wake_lock_t wow_auto_shutdown_wl; qdf_wake_lock_t roam_ho_wl; + qdf_wake_lock_t roam_preauth_wl; int wow_nack; qdf_atomic_t is_wow_bus_suspended; qdf_mc_timer_t wma_scan_comp_timer; @@ -1217,6 +1237,7 @@ typedef struct { #endif #ifdef WLAN_FEATURE_NAN bool is_nan_enabled; + bool nan_separate_iface_support; #endif uint8_t staMaxLIModDtim; uint8_t staModDtim; @@ -1243,10 +1264,20 @@ typedef struct { roam_offload_synch_ind *roam_synch_data, tpSirBssDescription bss_desc_ptr, enum sir_roam_op_code reason); + QDF_STATUS (*csr_roam_auth_event_handle_cb)(tpAniSirGlobal mac, + uint8_t vdev_id, + struct qdf_mac_addr bssid); QDF_STATUS (*pe_roam_synch_cb)(tpAniSirGlobal mac, roam_offload_synch_ind *roam_synch_data, tpSirBssDescription bss_desc_ptr, enum sir_roam_op_code reason); + QDF_STATUS (*pe_disconnect_cb) (tpAniSirGlobal mac, + uint8_t vdev_id, + uint8_t *deauth_disassoc_frame, + uint16_t deauth_disassoc_frame_len, + uint16_t reason_code); + QDF_STATUS (*csr_roam_pmkid_req_cb)(uint8_t vdev_id, + struct roam_pmkid_req_event *bss_list); qdf_wake_lock_t wmi_cmd_rsp_wake_lock; qdf_runtime_lock_t wmi_cmd_rsp_runtime_lock; bool apf_enabled; @@ -1279,6 +1310,7 @@ typedef struct { qdf_atomic_t critical_events_in_flight; bool enable_tx_compl_tsf64; bool enable_three_way_coex_config_legacy; + bool bmiss_skip_full_scan; } t_wma_handle, *tp_wma_handle; extern void cds_wma_complete_cback(void); @@ -1954,8 +1986,27 @@ WLAN_PHY_MODE wma_chan_phy_mode(u8 chan, enum phy_ch_width chan_width, u8 dot11_mode); #ifdef FEATURE_OEM_DATA_SUPPORT -QDF_STATUS wma_start_oem_data_req(tp_wma_handle wma_handle, - struct oem_data_req *oem_req); +/** + * wma_start_oem_req_cmd() - send oem request command to fw + * @wma_handle: wma handle + * @oem_data_req: the pointer of oem req buf + * + * Return: QDF status + */ +QDF_STATUS wma_start_oem_req_cmd(tp_wma_handle wma_handle, + struct oem_data_req *oem_data_req); +#endif + +#ifdef FEATURE_OEM_DATA +/** + * wma_start_oem_data_cmd() - send oem data command to fw + * @wma_handle: wma handle + * @oem_data: the pointer of oem data buf + * + * Return: QDF status + */ +QDF_STATUS wma_start_oem_data_cmd(tp_wma_handle wma_handle, + struct oem_data *oem_data); #endif QDF_STATUS wma_enable_disable_caevent_ind(tp_wma_handle wma_handle, @@ -2097,6 +2148,25 @@ void wma_vdev_update_pause_bitmap(uint8_t vdev_id, uint16_t value) iface->pause_bitmap = value; } +/** + * wma_host_to_fw_phymode() - convert host to fw phymode + * @host_phymode: phymode to convert + * + * Return: one of the values defined in enum WMI_HOST_WLAN_PHY_MODE; + * or WMI_HOST_MODE_UNKNOWN if the conversion fails + */ +WMI_HOST_WLAN_PHY_MODE +wma_host_to_fw_phymode(enum wlan_phymode host_phymode); + +/** + * wma_fw_to_host_phymode() - convert fw to host phymode + * @phymode: phymode to convert + * + * Return: one of the values defined in enum wlan_phymode; + * or WLAN_PHYMODE_AUTO if the conversion fails + */ +enum wlan_phymode wma_fw_to_host_phymode(WMI_HOST_WLAN_PHY_MODE phymode); + /** * wma_vdev_get_pause_bitmap() - Get vdev pause bitmap * @vdev_id: the Id of the vdev to configure @@ -2186,6 +2256,18 @@ QDF_STATUS wma_vdev_get_cfg_int(int cfg_id, int *value) return wlan_cfg_get_int(mac, cfg_id, value); } +/** + * wma_handle_roam_sync_timeout() - Update roaming status at wma layer + * @wma_handle: wma handle + * @info: Info for roaming start timer + * + * This function gets called in case of roaming offload timer get expired + * + * Return: None + */ +void wma_handle_roam_sync_timeout(tp_wma_handle wma_handle, + struct roam_sync_timeout_timer_info *info); + /** * wma_vdev_get_dtim_period - Get dtim period value from mlme * @vdev_id: vdev index number @@ -2328,6 +2410,24 @@ void wma_vdev_clear_pause_bit(uint8_t vdev_id, wmi_tx_pause_type bit_pos) QDF_STATUS wma_process_roaming_config(tp_wma_handle wma_handle, tSirRoamOffloadScanReq *roam_req); +#ifdef WLAN_FEATURE_ROAM_OFFLOAD +/** + * wma_send_roam_preauth_status() - Send the preauth status to wmi + * @handle: WMA handle + * @roam_req: Pointer to wmi_roam_auth_status_params from sae + * + * Return: None + */ +void +wma_send_roam_preauth_status(tp_wma_handle wma_handle, + struct wmi_roam_auth_status_params *params); +#else +static inline void +wma_send_roam_preauth_status(tp_wma_handle wma_handle, + struct wmi_roam_auth_status_params *params) +{} +#endif + #ifdef WMI_INTERFACE_EVENT_LOGGING static inline void wma_print_wmi_cmd_log(uint32_t count, qdf_abstract_print *print, @@ -2553,4 +2653,17 @@ void wma_check_and_set_wake_timer(uint32_t time); */ void wma_force_objmgr_vdev_peer_cleanup(tp_wma_handle wma, uint8_t vdev_id); +#ifdef FEATURE_ANI_LEVEL_REQUEST +/** + * wma_send_ani_level_request() - Send get ani level cmd to WMI + * @wma_handle: wma handle. + * @freqs: pointer to channels for which ANI level has to be retrieved + * @num_freqs: number of channels in the above parameter + * + * Return: QDF_STATUS + */ +QDF_STATUS wma_send_ani_level_request(tp_wma_handle wma_handle, + uint32_t *freqs, uint8_t num_freqs); +#endif /* FEATURE_ANI_LEVEL_REQUEST */ #endif + diff --git a/drivers/staging/qcacld-3.0/core/wma/inc/wma_api.h b/drivers/staging/qcacld-3.0/core/wma/inc/wma_api.h index 0e11072b577e..2565e4f23921 100644 --- a/drivers/staging/qcacld-3.0/core/wma/inc/wma_api.h +++ b/drivers/staging/qcacld-3.0/core/wma/inc/wma_api.h @@ -172,6 +172,10 @@ struct wma_txrx_node *wma_get_interface_by_vdev_id(uint8_t vdev_id); QDF_STATUS wma_get_connection_info(uint8_t vdev_id, struct policy_mgr_vdev_entry_info *conn_table_entry); +#ifdef WLAN_FEATURE_PKT_CAPTURE +int wma_get_rmf_status(uint8_t vdev_id); +#endif + bool wma_is_vdev_up(uint8_t vdev_id); void *wma_get_beacon_buffer_by_vdev_id(uint8_t vdev_id, uint32_t *buffer_size); diff --git a/drivers/staging/qcacld-3.0/core/wma/inc/wma_if.h b/drivers/staging/qcacld-3.0/core/wma/inc/wma_if.h index 80d8552f29a6..c39cb7cba47c 100644 --- a/drivers/staging/qcacld-3.0/core/wma/inc/wma_if.h +++ b/drivers/staging/qcacld-3.0/core/wma/inc/wma_if.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2011-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2011-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -206,6 +206,7 @@ typedef struct sAniProbeRspStruct { * @nss: Return the number of spatial streams supported * @stbc_capable: stbc capable * @max_amsdu_num: Maximum number of MSDUs in a tx aggregate frame + * @no_ptk_4_way: Do not need 4-way handshake * * This structure contains parameter required for * add sta request of upper layer. @@ -313,6 +314,7 @@ typedef struct { uint8_t twt_requestor; uint8_t twt_responder; #endif + bool no_ptk_4_way; } tAddStaParams, *tpAddStaParams; /** @@ -441,6 +443,7 @@ typedef struct sLimMlmSetKeysReq { * @he_capable: HE Capability * @cac_duration_ms: cac duration in milliseconds * @dfs_regdomain: dfs region + * @no_ptk_4_way: Do not need 4-way handshake */ typedef struct { tSirMacAddr bssId; @@ -521,6 +524,7 @@ typedef struct { #endif uint32_t cac_duration_ms; uint32_t dfs_regdomain; + bool no_ptk_4_way; } tAddBssParams, *tpAddBssParams; /** @@ -585,7 +589,9 @@ typedef enum eDelStaReasonCode { HAL_DEL_STA_REASON_CODE_TIM_BASED = 0x2, HAL_DEL_STA_REASON_CODE_RA_BASED = 0x3, HAL_DEL_STA_REASON_CODE_UNKNOWN_A2 = 0x4, - HAL_DEL_STA_REASON_CODE_BTM_DISASSOC_IMMINENT = 0x5 + HAL_DEL_STA_REASON_CODE_BTM_DISASSOC_IMMINENT = 0x5, + HAL_DEL_STA_REASON_CODE_SA_QUERY_TIMEOUT = 0x6, + HAL_DEL_STA_REASON_CODE_XRETRY = 0x7, } tDelStaReasonCode; typedef enum eSmpsModeValue { @@ -1549,4 +1555,14 @@ struct roam_blacklist_event { struct roam_blacklist_timeout roam_blacklist[]; }; +/* + * struct roam_pmkid_req_event - Pmkid event with entries destination structure + * @num_entries: total entries sent over the event + * @ap_bssid: bssid list + */ +struct roam_pmkid_req_event { + uint32_t num_entries; + struct qdf_mac_addr ap_bssid[]; +}; + #endif /* _HALMSGAPI_H_ */ diff --git a/drivers/staging/qcacld-3.0/core/wma/inc/wma_internal.h b/drivers/staging/qcacld-3.0/core/wma/inc/wma_internal.h index 2af362cb6a1a..f18d77cf0d64 100644 --- a/drivers/staging/qcacld-3.0/core/wma/inc/wma_internal.h +++ b/drivers/staging/qcacld-3.0/core/wma/inc/wma_internal.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -204,6 +204,71 @@ void wma_process_roam_synch_fail(WMA_HANDLE handle, int wma_roam_synch_event_handler(void *handle, uint8_t *event, uint32_t len); +#ifdef WLAN_FEATURE_FIPS +/** + * wma_register_pmkid_req_event_handler() - Register pmkid request event handler + * @wma_handle: wma_handle + * + * This function register pmkid request event handler. + */ +void wma_register_pmkid_req_event_handler(tp_wma_handle wma_handle); + +/** + * wma_roam_pmkid_request_event_handler() - Handles roam pmkid request event + * @handle: wma_handle + * @event: pmkid request event data pointer + * @len: length of the data + * + * Handles pmkid request event from firmware which is triggered after roam + * candidate selection. + */ +int wma_roam_pmkid_request_event_handler(void *handle, + uint8_t *event, + uint32_t len); +#else +static inline void +wma_register_pmkid_req_event_handler(tp_wma_handle wma_handle) +{ +} + +static inline int +wma_roam_pmkid_request_event_handler(void *handle, + uint8_t *event, + uint32_t len) +{ + return 0; +} +#endif /* WLAN_FEATURE_FIPS */ + +/** + * wma_roam_auth_offload_event_handler() - Handle LFR-3.0 Roam authentication + * offload event. + * @handle: wma_handle + * @event: rso auth offload event data pointer + * @len: length of the data + * + * Handles roam authentication offload event from firmware which is triggered + * after roam candidate selection. + */ +int wma_roam_auth_offload_event_handler(WMA_HANDLE handle, uint8_t *event, + uint32_t len); + +/** + * wma_roam_stats_event_handler() - Handle the WMI_ROAM_STATS_EVENTID + * from target + * @handle: wma_handle + * @event: roam debug stats event data pointer + * @len: length of the data + * + * This function handles the roam debug stats from the target and logs it + * to kmsg. This WMI_ROAM_STATS_EVENTID event is received whenever roam + * scan trigger happens or when neighbor report is sent by the firmware. + * + * Return: Success or Failure status + */ +int wma_roam_stats_event_handler(WMA_HANDLE handle, uint8_t *event, + uint32_t len); + /** * wma_roam_synch_frame_event_handler() - roam synch frame event handler * @handle: wma handle @@ -223,6 +288,21 @@ static inline int wma_mlme_roam_synch_event_handler_cb(void *handle, { return 0; } + +static inline int +wma_roam_pmkid_request_event_handler(void *handle, + uint8_t *event, + uint32_t len) +{ + return 0; +} + +static inline int +wma_roam_stats_event_handler(WMA_HANDLE handle, uint8_t *event, + uint32_t len) +{ + return 0; +} #endif /** @@ -239,10 +319,44 @@ QDF_STATUS wma_update_channel_list(WMA_HANDLE handle, tSirUpdateChanList *chan_list); #ifdef WLAN_FEATURE_ROAM_OFFLOAD +/** + * wma_roam_scan_chan_event_handler() - roam scan ch list event handler + * @handle: wma handle + * @event: pointer to event buf + * @len: length of event + * + * Return: Success or Failure status + */ +int wma_roam_scan_chan_event_handler(WMA_HANDLE handle, uint8_t *event, + uint32_t len); + +/** + * wma_get_roam_scan_ch() - API to get roam scan ch list from fw + * @wma: wma handle + * @vdev_id: vdev id + * + * Return: none + */ +QDF_STATUS wma_get_roam_scan_ch(tp_wma_handle wma, + uint8_t vdev_id); + QDF_STATUS wma_roam_scan_fill_self_caps(tp_wma_handle wma_handle, roam_offload_param * roam_offload_params, tSirRoamOffloadScanReq *roam_req); +#else +static inline QDF_STATUS wma_get_roam_scan_ch(tp_wma_handle wma, + uint8_t vdev_id) +{ + return QDF_STATUS_E_FAILURE; +} + +static inline int +wma_roam_scan_chan_event_handler(WMA_HANDLE handle, uint8_t *event, + uint32_t len) +{ + return -EINVAL; +} #endif QDF_STATUS wma_roam_scan_offload_mode(tp_wma_handle wma_handle, @@ -267,11 +381,9 @@ QDF_STATUS wma_roam_scan_mawc_params(tp_wma_handle wma_handle, QDF_STATUS wma_roam_scan_offload_rssi_thresh(tp_wma_handle wma_handle, tSirRoamOffloadScanReq *roam_req); -QDF_STATUS wma_roam_scan_offload_scan_period(tp_wma_handle wma_handle, - uint32_t scan_period, - uint32_t scan_age, - uint32_t vdev_id, - uint32_t roam_full_scan_period); +QDF_STATUS +wma_roam_scan_offload_scan_period(tp_wma_handle wma_handle, + tSirRoamOffloadScanReq *roam_req); QDF_STATUS wma_roam_scan_offload_rssi_change(tp_wma_handle wma_handle, uint32_t vdev_id, @@ -680,7 +792,13 @@ void wma_hidden_ssid_vdev_restart(tp_wma_handle wma_handle, * wma_power.c functions declarations */ -void wma_enable_sta_ps_mode(tp_wma_handle wma, tpEnablePsParams ps_req); +/** + * wma_enable_sta_ps_mode() - enable sta powersave params in fw + * @ps_req: power save request + * + * Return: none + */ +void wma_enable_sta_ps_mode(tpEnablePsParams ps_req); QDF_STATUS wma_unified_set_sta_ps_param(wmi_unified_t wmi_handle, uint32_t vdev_id, uint32_t param, @@ -703,7 +821,7 @@ void wma_set_tx_power(WMA_HANDLE handle, void wma_set_max_tx_power(WMA_HANDLE handle, tMaxTxPowerParams *tx_pwr_params); -void wma_disable_sta_ps_mode(tp_wma_handle wma, tpDisablePsParams ps_req); +void wma_disable_sta_ps_mode(tpDisablePsParams ps_req); void wma_enable_uapsd_mode(tp_wma_handle wma, tpEnableUapsdParams ps_req); @@ -1464,4 +1582,40 @@ int wma_roam_scan_stats_event_handler(void *handle, uint8_t *event, */ int wma_cold_boot_cal_event_handler(void *wma_ctx, uint8_t *event_buff, uint32_t len); + +#ifdef FEATURE_OEM_DATA +/** + * wma_oem_event_handler() - oem data event handler + * @wma_ctx: wma handle + * @event_buff: event data + * @len: length of event buffer + * + * Return: Success or Failure status + */ +int wma_oem_event_handler(void *wma_ctx, uint8_t *event_buff, uint32_t len); +#endif + +/** + * wma_set_roam_triggers() - Send roam trigger bitmap to WMI + * @wma_handle: wma handle + * @triggers: Carries vdev id and roam trigger bitmap. + * + * Return: Success or Failure status + */ +QDF_STATUS wma_set_roam_triggers(tp_wma_handle wma_handle, + struct roam_triggers *triggers); + +/** + * wma_get_ani_level_evt_handler - event handler to fetch ani level + * @handle: the wma handle + * @event_buf: buffer with event + * @len: buffer length + * + * This function receives ani level from firmware and passes the event + * to upper layer + * + * Return: 0 on success + */ +int wma_get_ani_level_evt_handler(void *handle, uint8_t *event_buf, + uint32_t len); #endif diff --git a/drivers/staging/qcacld-3.0/core/wma/inc/wma_tgt_cfg.h b/drivers/staging/qcacld-3.0/core/wma/inc/wma_tgt_cfg.h index 1be3fd8f8657..a1f38149e898 100644 --- a/drivers/staging/qcacld-3.0/core/wma/inc/wma_tgt_cfg.h +++ b/drivers/staging/qcacld-3.0/core/wma/inc/wma_tgt_cfg.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -42,6 +42,9 @@ * @twt_requestor: TWT requestor capability * @twt_responder: TWT responder capability * @bcn_reception_stats: Beacon Reception stats capability + * @akm_service_bitmap: bitmap of FT akm supported by firmware + * @is_adaptive_11r_roam_supported: Adaptive 11r target capability + * @is_roam_scan_ch_to_host: Firmware support for roam scan ch query */ struct wma_tgt_services { uint32_t sta_power_save; @@ -73,6 +76,9 @@ struct wma_tgt_services { bool twt_requestor; bool twt_responder; bool bcn_reception_stats; + uint32_t akm_service_bitmap; + bool is_adaptive_11r_roam_supported; + bool is_roam_scan_ch_to_host; }; /** @@ -224,5 +230,6 @@ struct wma_tgt_cfg { struct board_info hw_bd_info; enum sar_version sar_version; bool dynamic_nss_chains_support; + bool nan_seperate_vdev_support; }; #endif /* WMA_TGT_CFG_H */ diff --git a/drivers/staging/qcacld-3.0/core/wma/inc/wma_types.h b/drivers/staging/qcacld-3.0/core/wma/inc/wma_types.h index 9fb9536cd4b0..967d5e3d1c94 100644 --- a/drivers/staging/qcacld-3.0/core/wma/inc/wma_types.h +++ b/drivers/staging/qcacld-3.0/core/wma/inc/wma_types.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2012-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2012-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -161,9 +161,6 @@ #define WMA_MISSED_BEACON_IND SIR_HAL_MISSED_BEACON_IND -#define WMA_ENTER_PS_REQ SIR_HAL_ENTER_PS_REQ -#define WMA_EXIT_PS_REQ SIR_HAL_EXIT_PS_REQ - #define WMA_HIDDEN_SSID_RESTART_RSP SIR_HAL_HIDDEN_SSID_RESTART_RSP #define WMA_SWITCH_CHANNEL_RSP SIR_HAL_SWITCH_CHANNEL_RSP #define WMA_P2P_NOA_ATTR_IND SIR_HAL_P2P_NOA_ATTR_IND @@ -192,6 +189,8 @@ #define WMA_TSM_STATS_RSP SIR_HAL_TSM_STATS_RSP #endif +#define WMA_ROAM_SCAN_CH_REQ SIR_HAL_ROAM_SCAN_CH_REQ + #define WMA_HT40_OBSS_SCAN_IND SIR_HAL_HT40_OBSS_SCAN_IND #define WMA_SET_MIMOPS_REQ SIR_HAL_SET_MIMOPS_REQ @@ -207,6 +206,7 @@ #define WMA_ENABLE_UAPSD_REQ SIR_HAL_ENABLE_UAPSD_REQ #define WMA_DISABLE_UAPSD_REQ SIR_HAL_DISABLE_UAPSD_REQ +#define WMA_ROAM_SYNC_TIMEOUT SIR_HAL_WMA_ROAM_SYNC_TIMEOUT /* / PE <-> HAL statistics messages */ #define WMA_GET_STATISTICS_REQ SIR_HAL_GET_STATISTICS_REQ #define WMA_GET_STATISTICS_RSP SIR_HAL_GET_STATISTICS_RSP @@ -254,6 +254,7 @@ #endif #define WMA_ROAM_SCAN_OFFLOAD_REQ SIR_HAL_ROAM_SCAN_OFFLOAD_REQ +#define WMA_ROAM_PRE_AUTH_STATUS SIR_HAL_ROAM_PRE_AUTH_STATUS_IND #ifdef WLAN_FEATURE_ROAM_OFFLOAD #define WMA_ROAM_OFFLOAD_SYNCH_IND SIR_HAL_ROAM_OFFLOAD_SYNCH_IND @@ -466,6 +467,7 @@ #ifdef WLAN_MWS_INFO_DEBUGFS #define WMA_GET_MWS_COEX_INFO_REQ SIR_HAL_GET_MWS_COEX_INFO_REQ #endif +#define WMA_SET_ROAM_TRIGGERS SIR_HAL_SET_ROAM_TRIGGERS /* Bit 6 will be used to control BD rate for Management frames */ #define HAL_USE_BD_RATE2_FOR_MANAGEMENT_FRAME 0x40 @@ -691,6 +693,25 @@ QDF_STATUS u_mac_post_ctrl_msg(void *pSirGlobal, tSirMbMsg *pMb); QDF_STATUS wma_set_idle_ps_config(void *wma_ptr, uint32_t idle_ps); QDF_STATUS wma_get_snr(tAniGetSnrReq *psnr_req); +#ifdef WLAN_SEND_DSCP_UP_MAP_TO_FW +/** + * wma_send_dscp_up_map_to_fw() - send DSCP-to-UP map values to FW + * @wma_ptr: wma handle + * @dscp_to_up_map: array of DSCP-to-UP map values + * + * Use to send DSCP-to-UP map values to FW + * + * Return: QDF_STATUS + */ +QDF_STATUS wma_send_dscp_up_map_to_fw(void *wma_ptr, uint32_t *dscp_to_up_map); +#else +static inline +QDF_STATUS wma_send_dscp_up_map_to_fw(void *wma_ptr, uint32_t *dscp_to_up_map) +{ + return QDF_STATUS_SUCCESS; +} +#endif + /** * wma_set_wlm_latency_level() - set latency level to FW * @wma_ptr: wma handle @@ -758,20 +779,38 @@ QDF_STATUS wma_register_roaming_callbacks( roam_offload_synch_ind *roam_synch_data, tpSirBssDescription bss_desc_ptr, enum sir_roam_op_code reason), + QDF_STATUS (*csr_roam_auth_event_handle_cb)(tpAniSirGlobal mac, + uint8_t vdev_id, struct qdf_mac_addr bssid), QDF_STATUS (*pe_roam_synch_cb)(tpAniSirGlobal mac, roam_offload_synch_ind *roam_synch_data, tpSirBssDescription bss_desc_ptr, - enum sir_roam_op_code reason)); + enum sir_roam_op_code reason), + QDF_STATUS (*pe_disconnect_cb) (tpAniSirGlobal mac, + uint8_t vdev_id, + uint8_t *deauth_disassoc_frame, + uint16_t deauth_disassoc_frame_len, + uint16_t reason_code), + QDF_STATUS (*csr_roam_pmkid_req_cb)(uint8_t vdev_id, + struct roam_pmkid_req_event *bss_list)); #else static inline QDF_STATUS wma_register_roaming_callbacks( QDF_STATUS (*csr_roam_synch_cb)(tpAniSirGlobal mac, roam_offload_synch_ind *roam_synch_data, tpSirBssDescription bss_desc_ptr, enum sir_roam_op_code reason), + QDF_STATUS (*csr_roam_auth_event_handle_cb)(tpAniSirGlobal mac, + uint8_t vdev_id, struct qdf_mac_addr bssid), QDF_STATUS (*pe_roam_synch_cb)(tpAniSirGlobal mac, roam_offload_synch_ind *roam_synch_data, tpSirBssDescription bss_desc_ptr, - enum sir_roam_op_code reason)) + enum sir_roam_op_code reason), + QDF_STATUS (*pe_disconnect_cb) (tpAniSirGlobal mac, + uint8_t vdev_id, + uint8_t *deauth_disassoc_frame, + uint16_t deauth_disassoc_frame_len, + uint16_t reason_code), + QDF_STATUS (*csr_roam_pmkid_req_cb)(uint8_t vdev_id, + struct roam_pmkid_req_event *bss_list)) { return QDF_STATUS_E_NOSUPPORT; } diff --git a/drivers/staging/qcacld-3.0/core/wma/src/wma_data.c b/drivers/staging/qcacld-3.0/core/wma/src/wma_data.c index 7db95212e840..bfa16edf75d7 100644 --- a/drivers/staging/qcacld-3.0/core/wma/src/wma_data.c +++ b/drivers/staging/qcacld-3.0/core/wma/src/wma_data.c @@ -77,6 +77,7 @@ #include "wlan_lmac_if_api.h" #include #include +#include "wlan_pkt_capture_ucfg_api.h" struct wma_search_rate { int32_t rate; @@ -861,8 +862,7 @@ static void wma_data_tx_ack_work_handler(void *ack_work) /* Call the Ack Cb registered by UMAC */ if (ack_cb) - ack_cb((tpAniSirGlobal) (wma_handle->mac_context), NULL, - work->status, NULL); + ack_cb(wma_handle->mac_context, NULL, work->status, NULL); else WMA_LOGE("Data Tx Ack Cb is NULL"); @@ -1196,8 +1196,6 @@ void wma_set_linkstate(tp_wma_handle wma, tpLinkStateParams params) params->state, params->selfMacAddr); if ((params->state != eSIR_LINK_PREASSOC_STATE) && (params->state != eSIR_LINK_DOWN_STATE)) { - WMA_LOGD("%s: unsupported link state %d", - __func__, params->state); params->status = false; goto out; } @@ -2745,7 +2743,9 @@ QDF_STATUS wma_tx_packet(void *wma_context, void *tx_frame, uint16_t frmLen, } else { chanfreq = 0; } + if (pMac->fEnableDebugLog & 0x1) { + if ((pFc->type == SIR_MAC_MGMT_FRAME) && (pFc->subType != SIR_MAC_MGMT_PROBE_REQ) && (pFc->subType != SIR_MAC_MGMT_PROBE_RSP)) { @@ -2800,11 +2800,17 @@ QDF_STATUS wma_tx_packet(void *wma_context, void *tx_frame, uint16_t frmLen, WLAN_MGMT_NB_ID); } - status = wlan_mgmt_txrx_mgmt_frame_tx(peer, - (tpAniSirGlobal)wma_handle->mac_context, - (qdf_nbuf_t)tx_frame, - NULL, tx_frm_ota_comp_cb, - WLAN_UMAC_COMP_MLME, &mgmt_param); + if (ucfg_pkt_capture_get_pktcap_mode()) { + ucfg_pkt_capture_mgmt_tx(wma_handle->pdev, + tx_frame, + wma_handle->interfaces[vdev_id].mhz, + mgmt_param.tx_param.preamble_type); + } + + status = wlan_mgmt_txrx_mgmt_frame_tx(peer, wma_handle->mac_context, + (qdf_nbuf_t)tx_frame, + NULL, tx_frm_ota_comp_cb, + WLAN_UMAC_COMP_MLME, &mgmt_param); wlan_objmgr_peer_release_ref(peer, WLAN_MGMT_NB_ID); if (status != QDF_STATUS_SUCCESS) { diff --git a/drivers/staging/qcacld-3.0/core/wma/src/wma_dev_if.c b/drivers/staging/qcacld-3.0/core/wma/src/wma_dev_if.c index 33ea4e49bc30..23f9df127c75 100644 --- a/drivers/staging/qcacld-3.0/core/wma/src/wma_dev_if.c +++ b/drivers/staging/qcacld-3.0/core/wma/src/wma_dev_if.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2018, 2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -213,6 +213,9 @@ static enum wlan_op_mode wma_get_txrx_vdev_type(uint32_t type) case WMI_VDEV_TYPE_NDI: vdev_type = wlan_op_mode_ndi; break; + case WMI_VDEV_TYPE_NAN: + vdev_type = wlan_op_mode_nan; + break; default: WMA_LOGE("Invalid vdev type %u", type); vdev_type = wlan_op_mode_unknown; @@ -756,6 +759,7 @@ static void wma_remove_objmgr_peer(tp_wma_handle wma, uint8_t vdev_id, struct wlan_objmgr_peer *obj_peer; struct wlan_objmgr_vdev *obj_vdev; struct wlan_objmgr_pdev *obj_pdev; + struct wma_txrx_node *iface = &wma->interfaces[vdev_id]; uint8_t pdev_id = 0; psoc = wma->psoc; @@ -772,16 +776,18 @@ static void wma_remove_objmgr_peer(tp_wma_handle wma, uint8_t vdev_id, } obj_pdev = wlan_vdev_get_pdev(obj_vdev); pdev_id = wlan_objmgr_pdev_get_pdev_id(obj_pdev); + + qdf_spin_lock_bh(&iface->peer_lock); obj_peer = wlan_objmgr_get_peer(psoc, pdev_id, peer_addr, WLAN_LEGACY_WMA_ID); if (obj_peer) { wlan_objmgr_peer_obj_delete(obj_peer); /* Unref to decrement ref happened in find_peer */ wlan_objmgr_peer_release_ref(obj_peer, WLAN_LEGACY_WMA_ID); - WMA_LOGD("Peer %pM deleted", peer_addr); } else { WMA_LOGE("Peer %pM not found", peer_addr); } + qdf_spin_unlock_bh(&iface->peer_lock); wlan_objmgr_vdev_release_ref(obj_vdev, WLAN_LEGACY_WMA_ID); } @@ -893,6 +899,75 @@ QDF_STATUS wma_vdev_detach(tp_wma_handle wma_handle, return status; } +static void wma_sap_peer_send_phymode(struct wlan_objmgr_vdev *vdev, + void *object, void *arg) +{ + struct wlan_objmgr_peer *peer = object; + enum wlan_phymode old_peer_phymode; + enum wlan_phymode new_phymode; + tSirNwType nw_type; + uint32_t fw_phymode; + uint32_t max_ch_width_supported; + tp_wma_handle wma; + uint8_t *peer_mac_addr; + uint8_t vdev_id; + struct wma_txrx_node *intr; + + if (wlan_peer_get_peer_type(peer) == WLAN_PEER_SELF) + return; + + wma = cds_get_context(QDF_MODULE_ID_WMA); + + if(!wma) { + wma_err("wma handle NULL"); + return; + } + + intr = wma->interfaces; + old_peer_phymode = wlan_peer_get_phymode(peer); + vdev_id = wlan_vdev_get_id(vdev); + + peer_mac_addr = wlan_peer_get_macaddr(peer); + + if (WLAN_REG_IS_24GHZ_CH_FREQ(intr[vdev_id].mhz)) { + if (intr[vdev_id].chanmode == WMI_HOST_MODE_11B) + nw_type = eSIR_11B_NW_TYPE; + else + nw_type = eSIR_11G_NW_TYPE; + } else { + nw_type = eSIR_11A_NW_TYPE; + } + fw_phymode = wma_peer_phymode(nw_type, STA_ENTRY_PEER, + IS_WLAN_PHYMODE_HT(old_peer_phymode), + intr[vdev_id].chan_width, + IS_WLAN_PHYMODE_VHT(old_peer_phymode), + IS_WLAN_PHYMODE_HE(old_peer_phymode)); + + new_phymode = wma_fw_to_host_phymode(fw_phymode); + wlan_peer_set_phymode(peer, new_phymode); + + wma_set_peer_param(wma, peer_mac_addr, WMI_PEER_PHYMODE, + fw_phymode, vdev_id); + + max_ch_width_supported = + wmi_get_ch_width_from_phy_mode(wma->wmi_handle, fw_phymode); + wma_set_peer_param(wma, peer_mac_addr, WMI_PEER_CHWIDTH, + max_ch_width_supported, vdev_id); + + wma_debug("nw_type %d old phymode %d new phymode %d bw %d macaddr "QDF_MAC_ADDR_STR, + nw_type, old_peer_phymode, new_phymode, + max_ch_width_supported, QDF_MAC_ADDR_ARRAY(peer_mac_addr)); +} + +static void +wma_update_peer_phymode_sap(struct wlan_objmgr_vdev *vdev) +{ + wlan_objmgr_iterate_peerobj_list(vdev, + wma_sap_peer_send_phymode, + NULL, + WLAN_LEGACY_WMA_ID); +} + /** * wma_vdev_start_rsp() - send vdev start response to upper layer * @wma: wma handle @@ -1052,6 +1127,7 @@ int wma_vdev_start_resp_handler(void *handle, uint8_t *cmd_param_info, int err; wmi_host_channel_width chanwidth; target_resource_config *wlan_res_cfg; + struct wlan_objmgr_vdev *vdev; struct wlan_objmgr_psoc *psoc = wma->psoc; #ifdef FEATURE_AP_MCC_CH_AVOIDANCE tpAniSirGlobal mac_ctx = cds_get_context(QDF_MODULE_ID_PE); @@ -1071,8 +1147,6 @@ int wma_vdev_start_resp_handler(void *handle, uint8_t *cmd_param_info, } #endif /* FEATURE_AP_MCC_CH_AVOIDANCE */ - WMA_LOGD("%s: Enter", __func__); - wlan_res_cfg = lmac_get_tgt_res_cfg(psoc); if (!wlan_res_cfg) { WMA_LOGE("%s: Wlan resource config is NULL", __func__); @@ -1094,7 +1168,6 @@ int wma_vdev_start_resp_handler(void *handle, uint8_t *cmd_param_info, wma->psoc, false); return -EINVAL; } - if (resp_event->vdev_id >= wma->max_bssid) { WMA_LOGE("Invalid vdev id received from firmware"); return -EINVAL; @@ -1172,7 +1245,6 @@ int wma_vdev_start_resp_handler(void *handle, uint8_t *cmd_param_info, if (req_msg->msg_type == WMA_CHNL_SWITCH_REQ) { tpSwitchChannelParams params = (tpSwitchChannelParams) req_msg->user_data; - if (!params) { WMA_LOGE("%s: channel switch params is NULL for vdev %d", __func__, resp_event->vdev_id); @@ -1194,30 +1266,38 @@ int wma_vdev_start_resp_handler(void *handle, uint8_t *cmd_param_info, false; } - if ((QDF_IS_STATUS_SUCCESS(resp_event->status) && - (resp_event->resp_type == WMI_VDEV_RESTART_RESP_EVENT) && - ((iface->type == WMI_VDEV_TYPE_STA) || - (iface->type == WMI_VDEV_TYPE_MONITOR))) || - ((resp_event->resp_type == WMI_VDEV_START_RESP_EVENT) && - (iface->type == WMI_VDEV_TYPE_MONITOR))) { - /* for CSA case firmware expects phymode before ch_wd */ - err = wma_set_peer_param(wma, iface->bssid, - WMI_PEER_PHYMODE, iface->chanmode, - resp_event->vdev_id); - WMA_LOGD("%s:vdev_id %d chanmode %d status %d", - __func__, resp_event->vdev_id, - iface->chanmode, err); + if (QDF_IS_STATUS_SUCCESS(resp_event->status) && + resp_event->resp_type == WMI_VDEV_RESTART_RESP_EVENT && + iface->type == WMI_VDEV_TYPE_AP) { + vdev = wlan_objmgr_get_vdev_by_id_from_psoc(wma->psoc, + resp_event->vdev_id, WLAN_LEGACY_WMA_ID); + if (vdev) { + wma_update_peer_phymode_sap(vdev); + wlan_objmgr_vdev_release_ref(vdev, + WLAN_LEGACY_WMA_ID); + } + } + if (QDF_IS_STATUS_SUCCESS(resp_event->status) && + wma_is_vdev_valid(resp_event->vdev_id) && + (iface->type == WMI_VDEV_TYPE_MONITOR || + (iface->type == WMI_VDEV_TYPE_STA && + resp_event->resp_type == WMI_VDEV_RESTART_RESP_EVENT))) { + /* FW expects chanmode before chanwidth*/ + err = wma_set_peer_param(wma, iface->bssid, + WMI_PEER_PHYMODE, + iface->chanmode, + resp_event->vdev_id); chanwidth = - wmi_get_ch_width_from_phy_mode(wma->wmi_handle, - iface->chanmode); + wmi_get_ch_width_from_phy_mode( + wma->wmi_handle, + iface->chanmode); err = wma_set_peer_param(wma, iface->bssid, WMI_PEER_CHWIDTH, chanwidth, resp_event->vdev_id); - WMA_LOGD("%s:vdev_id %d chanwidth %d status %d", - __func__, resp_event->vdev_id, - chanwidth, err); - + wma_debug("vdev_id %d chanwidth %d chanmode %d", + resp_event->vdev_id, chanwidth, + iface->chanmode); param.vdev_id = resp_event->vdev_id; param.assoc_id = iface->aid; status = wma_send_vdev_up_to_fw(wma, ¶m, @@ -1226,18 +1306,19 @@ int wma_vdev_start_resp_handler(void *handle, uint8_t *cmd_param_info, WMA_LOGE("%s:vdev_up failed vdev_id %d", __func__, resp_event->vdev_id); wma_vdev_set_mlme_state(wma, - resp_event->vdev_id, WLAN_VDEV_S_STOP); + resp_event->vdev_id, + WLAN_VDEV_S_STOP); policy_mgr_set_do_hw_mode_change_flag( wma->psoc, false); } else { wma_vdev_set_mlme_state(wma, - resp_event->vdev_id, WLAN_VDEV_S_RUN); + resp_event->vdev_id, + WLAN_VDEV_S_RUN); if (iface->beacon_filter_enabled) wma_add_beacon_filter(wma, - &iface->beacon_filter); + &iface->beacon_filter); } } - wma_send_msg_high_priority(wma, WMA_SWITCH_CHANNEL_RSP, (void *)params, 0); } else if (req_msg->msg_type == WMA_ADD_BSS_REQ) { @@ -1287,9 +1368,6 @@ bool wma_is_vdev_valid(uint32_t vdev_id) return false; } - WMA_LOGD("%s: vdev_id: %d, vdev_active: %d", __func__, vdev_id, - wma_handle->interfaces[vdev_id].vdev_active); - return wma_handle->interfaces[vdev_id].vdev_active; } @@ -1644,11 +1722,6 @@ static int wma_get_obj_mgr_peer_type(tp_wma_handle wma, uint8_t vdev_id, { uint32_t obj_peer_type = 0; - WMA_LOGD("vdev id %d vdev type %d vdev subtype %d peer addr %pM vdev addr %pM", - vdev_id, wma->interfaces[vdev_id].type, - wma->interfaces[vdev_id].sub_type, peer_addr, - wma->interfaces[vdev_id].addr); - if (wma_peer_type == WMI_PEER_TYPE_TDLS) return WLAN_PEER_TDLS; @@ -1722,9 +1795,6 @@ static struct wlan_objmgr_peer *wma_create_objmgr_peer(tp_wma_handle wma, obj_peer = wlan_objmgr_peer_obj_create(obj_vdev, obj_peer_type, peer_addr); wlan_objmgr_vdev_release_ref(obj_vdev, WLAN_LEGACY_WMA_ID); - if (obj_peer) - WMA_LOGD("Peer %pM added successfully! Type: %d", peer_addr, - obj_peer_type); return obj_peer; @@ -1807,9 +1877,6 @@ QDF_STATUS wma_create_peer(tp_wma_handle wma, struct cdp_pdev *pdev, wlan_objmgr_peer_obj_delete(obj_peer); goto err; } - WMA_LOGD("%s: vdev %pK is attaching peer:%pK peer_addr %pM to vdev_id %d, peer_count - %d", - __func__, vdev, peer, peer_addr, vdev_id, - wma->interfaces[vdev_id].peer_count); if (roam_synch_in_progress) { WMA_LOGD("%s: LFR3: Created peer %pK with peer_addr %pM vdev_id %d, peer_count - %d", @@ -1844,11 +1911,8 @@ QDF_STATUS wma_create_peer(tp_wma_handle wma, struct cdp_pdev *pdev, DEBUG_INVALID_PEER_ID, peer_addr, peer, 0, 0); cdp_peer_setup(dp_soc, vdev, peer); - WMA_LOGD("%s: Initialized peer with peer_addr %pM vdev_id %d", - __func__, peer_addr, vdev_id); - mac_addr_raw = cdp_get_vdev_mac_addr(dp_soc, vdev); - if (mac_addr_raw == NULL) { + if (!mac_addr_raw) { WMA_LOGE("%s: peer mac addr is NULL", __func__); return QDF_STATUS_E_FAULT; } @@ -3089,7 +3153,6 @@ int wma_peer_assoc_conf_handler(void *handle, uint8_t *cmd_param_info, uint8_t macaddr[IEEE80211_ADDR_LEN]; int status = 0; - WMA_LOGD(FL("Enter")); param_buf = (WMI_PEER_ASSOC_CONF_EVENTID_param_tlvs *) cmd_param_info; if (!param_buf) { WMA_LOGE("Invalid peer assoc conf event buffer"); @@ -3147,10 +3210,6 @@ int wma_peer_assoc_conf_handler(void *handle, uint8_t *cmd_param_info, /* peer assoc conf event means the cmd succeeds */ params->status = QDF_STATUS_SUCCESS; - WMA_LOGD(FL("Send ADD BSS RSP: opermode: %d update_bss: %d nw_type: %d bssid: %pM staIdx %d status %d"), - params->operMode, - params->updateBss, params->nwType, params->bssId, - params->staContext.staIdx, params->status); wma_send_msg_high_priority(wma, WMA_ADD_BSS_RSP, (void *)params, 0); } else { @@ -3907,8 +3966,7 @@ wma_vdev_set_bss_params(tp_wma_handle wma, int vdev_id, if (!maxTxPower) WMA_LOGW("Setting Tx power limit to 0"); - WMA_LOGD("Set maxTx pwr [WMI_VDEV_PARAM_TX_PWRLIMIT] to %d", - maxTxPower); + wma_debug("Set maxTx pwr to %d", maxTxPower); ret = wma_vdev_set_param(wma->wmi_handle, vdev_id, WMI_VDEV_PARAM_TX_PWRLIMIT, maxTxPower); @@ -4512,6 +4570,9 @@ static void wma_add_bss_sta_mode(tp_wma_handle wma, tpAddBssParams add_bss) else WMA_LOGD("Sent PKT_PWR_SAVE_5G_EBT cmd to target, val = %x, status = %d", pps_val, status); + + add_bss->staContext.no_ptk_4_way = add_bss->no_ptk_4_way; + status = wma_send_peer_assoc(wma, add_bss->nwType, &add_bss->staContext); if (QDF_IS_STATUS_ERROR(status)) { @@ -4901,7 +4962,8 @@ static void wma_add_tdls_sta(tp_wma_handle wma, tpAddStaParams add_sta) goto send_rsp; } - if (wma_is_roam_synch_in_progress(wma, add_sta->smesessionId)) { + if (wma_is_roam_synch_in_progress(wma, add_sta->smesessionId) || + wma->interfaces[add_sta->smesessionId].roaming_in_progress) { WMA_LOGE("%s: roaming in progress, reject add sta!", __func__); add_sta->status = QDF_STATUS_E_PERM; goto send_rsp; @@ -5170,7 +5232,6 @@ static void wma_add_sta_req_sta_mode(tp_wma_handle wma, tpAddStaParams params) if (wmi_service_enabled(wma->wmi_handle, wmi_service_peer_assoc_conf)) { - WMA_LOGD(FL("WMI_SERVICE_PEER_ASSOC_CONF is enabled")); peer_assoc_cnf = true; msg = wma_fill_hold_req(wma, params->smesessionId, WMA_ADD_STA_REQ, WMA_PEER_ASSOC_CNF_START, @@ -5190,6 +5251,8 @@ static void wma_add_sta_req_sta_mode(tp_wma_handle wma, tpAddStaParams params) WMA_LOGD(FL("WMI_SERVICE_PEER_ASSOC_CONF not enabled")); } + ((tAddStaParams *)iface->addBssStaContext)->no_ptk_4_way = + params->no_ptk_4_way; ret = wma_send_peer_assoc(wma, iface->nwType, (tAddStaParams *) iface->addBssStaContext); @@ -5253,8 +5316,6 @@ static void wma_add_sta_req_sta_mode(tp_wma_handle wma, tpAddStaParams params) } qdf_atomic_set(&iface->bss_status, WMA_BSS_STATUS_STARTED); - WMA_LOGD("%s: STA mode (type %d subtype %d) BSS is started", - __func__, iface->type, iface->sub_type); /* Sta is now associated, configure various params */ /* Send SMPS force command to FW to send the required @@ -5288,8 +5349,7 @@ static void wma_add_sta_req_sta_mode(tp_wma_handle wma, tpAddStaParams params) WMA_VHT_PPS_DELIM_CRC_FAIL, 1); if (wmi_service_enabled(wma->wmi_handle, wmi_service_listen_interval_offload_support)) { - WMA_LOGD("%s: listen interval offload enabled, setting params", - __func__); + wma_debug("listen interval offload enabled, setting params"); status = wma_vdev_set_param(wma->wmi_handle, params->smesessionId, WMI_VDEV_PARAM_MAX_LI_OF_MODDTIM, @@ -5328,10 +5388,9 @@ static void wma_add_sta_req_sta_mode(tp_wma_handle wma, tpAddStaParams params) return; params->status = status; - WMA_LOGD(FL("statype %d vdev_id %d aid %d bssid %pM staIdx %d status %d"), - params->staType, params->smesessionId, - params->assocId, params->bssId, params->staIdx, - params->status); + wma_debug("vdev_id %d aid %d staid %d sta mac " QDF_MAC_ADDR_STR " status %d", + params->smesessionId, params->assocId, params->staIdx, + QDF_MAC_ADDR_ARRAY(params->bssId), params->status); /* Don't send a response during roam sync operation */ if (!wma_is_roam_synch_in_progress(wma, params->smesessionId)) wma_send_msg_high_priority(wma, WMA_ADD_STA_RSP, @@ -5545,11 +5604,7 @@ void wma_add_sta(tp_wma_handle wma, tpAddStaParams add_sta) return; } - WMA_LOGD("%s: add_sta->sessionId = %d.", __func__, - add_sta->smesessionId); - WMA_LOGD("%s: add_sta->bssId = %x:%x:%x:%x:%x:%x", __func__, - add_sta->bssId[0], add_sta->bssId[1], add_sta->bssId[2], - add_sta->bssId[3], add_sta->bssId[4], add_sta->bssId[5]); + wma_debug("Vdev %d BSSID %pM", add_sta->smesessionId, add_sta->bssId); if (wma_is_vdev_in_ap_mode(wma, add_sta->smesessionId)) oper_mode = BSS_OPERATIONAL_MODE_AP; @@ -5958,7 +6013,7 @@ void wma_delete_bss(tp_wma_handle wma, tpDeleteBssParams params) wma_wait_tx_complete(wma, params->smesessionId); if (cdp_get_tx_pending(soc, pdev)) { - WMA_LOGW(FL("Outstanding msdu packets before VDEV_STOP : %d"), + WMA_LOGD(FL("Outstanding msdu packets before VDEV_STOP : %d"), cdp_get_tx_pending(soc, pdev)); } @@ -6103,6 +6158,21 @@ int wma_fill_beacon_interval_reset_req(tp_wma_handle wma, uint8_t vdev_id, return 0; } +#ifdef WLAN_SEND_DSCP_UP_MAP_TO_FW +QDF_STATUS wma_send_dscp_up_map_to_fw(void *wma_ptr, uint32_t *dscp_to_up_map) +{ + QDF_STATUS ret; + tp_wma_handle wma = (tp_wma_handle)wma_ptr; + + ret = wmi_unified_send_dscp_tid_map_cmd(wma->wmi_handle, + dscp_to_up_map); + if (QDF_IS_STATUS_ERROR(ret)) + WMA_LOGE("Failed to send dscp_up_map to FW"); + + return ret; +} +#endif + QDF_STATUS wma_set_wlm_latency_level(void *wma_ptr, struct wlm_latency_level_param *latency_params) { diff --git a/drivers/staging/qcacld-3.0/core/wma/src/wma_features.c b/drivers/staging/qcacld-3.0/core/wma/src/wma_features.c index c26f5fc330e5..8d29c547b1fa 100644 --- a/drivers/staging/qcacld-3.0/core/wma/src/wma_features.c +++ b/drivers/staging/qcacld-3.0/core/wma/src/wma_features.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2018 The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -1351,6 +1351,32 @@ static int wma_nan_rsp_event_handler(void *handle, uint8_t *event_buf, } #endif /* WLAN_FEATURE_NAN */ +static uint8_t * +wma_parse_ch_switch_wrapper_ie(uint8_t *ch_wr_ie, uint8_t sub_ele_id) +{ + uint8_t len = 0, sub_ele_len = 0; + struct ie_header *ele; + + ele = (struct ie_header *)ch_wr_ie; + if (ele->ie_id != WLAN_ELEMID_CHAN_SWITCH_WRAP || + ele->ie_len == 0) + return NULL; + + len = ele->ie_len; + ele = (struct ie_header *)(ch_wr_ie + sizeof(struct ie_header)); + + while (len > 0) { + sub_ele_len = sizeof(struct ie_header) + ele->ie_len; + len -= sub_ele_len; + if (ele->ie_id == sub_ele_id) + return (uint8_t *)ele; + + ele = (struct ie_header *)((uint8_t *)ele + sub_ele_len); + } + + return NULL; +} + /** * wma_csa_offload_handler() - CSA event handler * @handle: wma handle @@ -1430,12 +1456,31 @@ int wma_csa_offload_handler(void *handle, uint8_t *event, uint32_t len) csa_offload_event->new_ch_width = wb_ie->new_ch_width; csa_offload_event->new_ch_freq_seg1 = wb_ie->new_ch_freq_seg1; csa_offload_event->new_ch_freq_seg2 = wb_ie->new_ch_freq_seg2; + } else if (csa_event->ies_present_flag & + WMI_CSWRAP_IE_EXTENDED_PRESENT) { + wb_ie = (struct ieee80211_ie_wide_bw_switch *) + wma_parse_ch_switch_wrapper_ie( + (uint8_t *)&csa_event->cswrap_ie_extended, + WLAN_ELEMID_WIDE_BAND_CHAN_SWITCH); + if (wb_ie) { + csa_offload_event->new_ch_width = wb_ie->new_ch_width; + csa_offload_event->new_ch_freq_seg1 = + wb_ie->new_ch_freq_seg1; + csa_offload_event->new_ch_freq_seg2 = + wb_ie->new_ch_freq_seg2; + csa_event->ies_present_flag |= WMI_WBW_IE_PRESENT; + } } csa_offload_event->ies_present_flag = csa_event->ies_present_flag; - WMA_LOGD("CSA: New Channel = %d BSSID:%pM", - csa_offload_event->channel, csa_offload_event->bssId); + WMA_LOGD("CSA: BSSID %pM chan %d flag 0x%x width = %d freq1 = %d freq2 = %d op class = %d", + csa_offload_event->bssId, csa_offload_event->channel, + csa_event->ies_present_flag, + csa_offload_event->new_ch_width, + csa_offload_event->new_ch_freq_seg1, + csa_offload_event->new_ch_freq_seg2, + csa_offload_event->new_op_class); cur_chan = cds_freq_to_chan(intr[vdev_id].mhz); /* @@ -1534,17 +1579,10 @@ int wma_oem_data_response_handler(void *handle, return 0; } -/** - * wma_start_oem_data_req() - start OEM data request to target - * @wma_handle: wma handle - * @oem_data_req: start request params - * - * Return: QDF_STATUS - */ -QDF_STATUS wma_start_oem_data_req(tp_wma_handle wma_handle, - struct oem_data_req *oem_data_req) +QDF_STATUS wma_start_oem_req_cmd(tp_wma_handle wma_handle, + struct oem_data_req *oem_data_req) { - int ret = 0; + QDF_STATUS ret; WMA_LOGD(FL("Send OEM Data Request to target")); @@ -1559,9 +1597,10 @@ QDF_STATUS wma_start_oem_data_req(tp_wma_handle wma_handle, return QDF_STATUS_E_INVAL; } + /* legacy api, for oem data request case */ ret = wmi_unified_start_oem_data_cmd(wma_handle->wmi_handle, - oem_data_req->data_len, - oem_data_req->data); + oem_data_req->data_len, + oem_data_req->data); if (!QDF_IS_STATUS_SUCCESS(ret)) WMA_LOGE(FL("wmi cmd send failed")); @@ -1570,6 +1609,34 @@ QDF_STATUS wma_start_oem_data_req(tp_wma_handle wma_handle, } #endif /* FEATURE_OEM_DATA_SUPPORT */ +#ifdef FEATURE_OEM_DATA +QDF_STATUS wma_start_oem_data_cmd(tp_wma_handle wma_handle, + struct oem_data *oem_data) +{ + QDF_STATUS ret; + + wma_debug("Send OEM Data to target"); + + if (!oem_data || !oem_data->data) { + wma_err("oem_data is null"); + return QDF_STATUS_E_INVAL; + } + + if (!wma_handle || !wma_handle->wmi_handle) { + wma_err("WMA - closed"); + return QDF_STATUS_E_INVAL; + } + + /* common api, for oem data command case */ + ret = wmi_unified_start_oemv2_data_cmd(wma_handle->wmi_handle, + oem_data); + if (!QDF_IS_STATUS_SUCCESS(ret)) + wma_err("call start wmi cmd failed"); + + return ret; +} +#endif + #if !defined(REMOVE_PKT_LOG) /** * wma_pktlog_wmi_send_cmd() - send pktlog enable/disable command to target @@ -1656,6 +1723,8 @@ static const u8 *wma_wow_wake_reason_str(A_INT32 wake_reason) return "IOAC_TIMER_EVENT"; case WOW_REASON_ROAM_HO: return "ROAM_HO"; + case WOW_REASON_ROAM_PREAUTH_START: + return "ROAM_PREAUTH_START_EVENT"; case WOW_REASON_DFS_PHYERR_RADADR_EVENT: return "DFS_PHYERR_RADADR_EVENT"; case WOW_REASON_BEACON_RECV: @@ -1708,6 +1777,8 @@ static const u8 *wma_wow_wake_reason_str(A_INT32 wake_reason) return "SAP_OBSS_DETECTION"; case WOW_REASON_BSS_COLOR_COLLISION_DETECT: return "BSS_COLOR_COLLISION_DETECT"; + case WOW_REASON_ROAM_PMKID_REQUEST: + return "ROAM_PMKID_REQUEST"; default: return "unknown"; } @@ -1801,6 +1872,12 @@ static void wma_print_wow_stats(t_wma_handle *wma, vdev = wlan_objmgr_get_vdev_by_id_from_psoc(wma->psoc, wake_info->vdev_id, WLAN_LEGACY_WMA_ID); + if (!vdev) { + WMA_LOGE("%s, vdev_id: %d, failed to get vdev from psoc", + __func__, wake_info->vdev_id); + return; + } + ucfg_mc_cp_stats_get_vdev_wake_lock_stats(vdev, &stats); wlan_objmgr_vdev_release_ref(vdev, WLAN_LEGACY_WMA_ID); wma_wow_stats_display(&stats); @@ -2023,6 +2100,12 @@ static int wow_get_wmi_eventid(int32_t reason, uint32_t tag) case WOW_REASON_11D_SCAN: event_id = WMI_11D_NEW_COUNTRY_EVENTID; break; + case WOW_ROAM_PREAUTH_START_EVENT: + event_id = WMI_ROAM_PREAUTH_STATUS_CMDID; + break; + case WOW_REASON_ROAM_PMKID_REQUEST: + event_id = WMI_ROAM_PMKID_REQUEST_EVENTID; + break; default: WMA_LOGD(FL("No Event Id for WOW reason %s(%d)"), wma_wow_wake_reason_str(reason), reason); @@ -2061,6 +2144,7 @@ static bool is_piggybacked_event(int32_t reason) case WOW_REASON_NAN_DATA: case WOW_REASON_TDLS_CONN_TRACKER_EVENT: case WOW_REASON_ROAM_HO: + case WOW_REASON_ROAM_PMKID_REQUEST: return true; default: return false; @@ -2254,7 +2338,7 @@ static void wma_log_pkt_eapol(uint8_t *data, uint32_t length) pkt_len = *(uint16_t *)(data + EAPOL_PKT_LEN_OFFSET); key_len = *(uint16_t *)(data + EAPOL_KEY_LEN_OFFSET); - WMA_LOGA("Pkt_len: %u, Key_len: %u", + WMA_LOGD("Pkt_len: %u, Key_len: %u", qdf_cpu_to_be16(pkt_len), qdf_cpu_to_be16(key_len)); } @@ -2268,7 +2352,7 @@ static void wma_log_pkt_dhcp(uint8_t *data, uint32_t length) pkt_len = *(uint16_t *)(data + DHCP_PKT_LEN_OFFSET); trans_id = *(uint32_t *)(data + DHCP_TRANSACTION_ID_OFFSET); - WMA_LOGA("Pkt_len: %u, Transaction_id: %u", + WMA_LOGD("Pkt_len: %u, Transaction_id: %u", qdf_cpu_to_be16(pkt_len), qdf_cpu_to_be16(trans_id)); } @@ -2281,7 +2365,7 @@ static void wma_log_pkt_icmpv4(uint8_t *data, uint32_t length) pkt_len = *(uint16_t *)(data + IPV4_PKT_LEN_OFFSET); seq_num = *(uint16_t *)(data + ICMP_SEQ_NUM_OFFSET); - WMA_LOGA("Pkt_len: %u, Seq_num: %u", + WMA_LOGD("Pkt_len: %u, Seq_num: %u", qdf_cpu_to_be16(pkt_len), qdf_cpu_to_be16(seq_num)); } @@ -2294,7 +2378,7 @@ static void wma_log_pkt_icmpv6(uint8_t *data, uint32_t length) pkt_len = *(uint16_t *)(data + IPV6_PKT_LEN_OFFSET); seq_num = *(uint16_t *)(data + ICMPV6_SEQ_NUM_OFFSET); - WMA_LOGA("Pkt_len: %u, Seq_num: %u", + WMA_LOGD("Pkt_len: %u, Seq_num: %u", qdf_cpu_to_be16(pkt_len), qdf_cpu_to_be16(seq_num)); } @@ -2308,14 +2392,14 @@ static void wma_log_pkt_ipv4(uint8_t *data, uint32_t length) pkt_len = *(uint16_t *)(data + IPV4_PKT_LEN_OFFSET); ip_addr = (char *)(data + IPV4_SRC_ADDR_OFFSET); - WMA_LOGA("src addr %d:%d:%d:%d", ip_addr[0], ip_addr[1], + WMA_LOGD("src addr %d:%d:%d:%d", ip_addr[0], ip_addr[1], ip_addr[2], ip_addr[3]); ip_addr = (char *)(data + IPV4_DST_ADDR_OFFSET); - WMA_LOGA("dst addr %d:%d:%d:%d", ip_addr[0], ip_addr[1], + WMA_LOGD("dst addr %d:%d:%d:%d", ip_addr[0], ip_addr[1], ip_addr[2], ip_addr[3]); src_port = *(uint16_t *)(data + IPV4_SRC_PORT_OFFSET); dst_port = *(uint16_t *)(data + IPV4_DST_PORT_OFFSET); - WMA_LOGA("Pkt_len: %u, src_port: %u, dst_port: %u", + WMA_LOGI("Pkt_len: %u, src_port: %u, dst_port: %u", qdf_cpu_to_be16(pkt_len), qdf_cpu_to_be16(src_port), qdf_cpu_to_be16(dst_port)); @@ -2346,7 +2430,7 @@ static void wma_log_pkt_ipv6(uint8_t *data, uint32_t length) ip_addr[15]); src_port = *(uint16_t *)(data + IPV6_SRC_PORT_OFFSET); dst_port = *(uint16_t *)(data + IPV6_DST_PORT_OFFSET); - WMA_LOGA("Pkt_len: %u, src_port: %u, dst_port: %u", + WMA_LOGI("Pkt_len: %u, src_port: %u, dst_port: %u", qdf_cpu_to_be16(pkt_len), qdf_cpu_to_be16(src_port), qdf_cpu_to_be16(dst_port)); @@ -2360,7 +2444,7 @@ static void wma_log_pkt_tcpv4(uint8_t *data, uint32_t length) return; seq_num = *(uint32_t *)(data + IPV4_TCP_SEQ_NUM_OFFSET); - WMA_LOGA("TCP_seq_num: %u", qdf_cpu_to_be16(seq_num)); + WMA_LOGD("TCP_seq_num: %u", qdf_cpu_to_be16(seq_num)); } static void wma_log_pkt_tcpv6(uint8_t *data, uint32_t length) @@ -2371,7 +2455,7 @@ static void wma_log_pkt_tcpv6(uint8_t *data, uint32_t length) return; seq_num = *(uint32_t *)(data + IPV6_TCP_SEQ_NUM_OFFSET); - WMA_LOGA("TCP_seq_num: %u", qdf_cpu_to_be16(seq_num)); + WMA_LOGD("TCP_seq_num: %u", qdf_cpu_to_be16(seq_num)); } #ifdef QCA_SUPPORT_CP_STATS @@ -2662,6 +2746,10 @@ static void wma_acquire_wow_wakelock(t_wma_handle *wma, int wake_reason) wl = &wma->roam_ho_wl; ms = WMA_ROAM_HO_WAKE_LOCK_DURATION; break; + case WOW_REASON_ROAM_PREAUTH_START: + wl = &wma->roam_preauth_wl; + ms = WMA_ROAM_PREAUTH_WAKE_LOCK_DURATION; + break; default: return; } @@ -2981,7 +3069,11 @@ static int wma_wake_event_piggybacked( wma_send_msg(wma, SIR_LIM_DELETE_STA_CONTEXT_IND, del_sta_ctx, 0); break; - + case WOW_REASON_ROAM_PMKID_REQUEST: + WMA_LOGD("Host woken up because of PMKID request event"); + errno = wma_roam_pmkid_request_event_handler(wma, pb_event, + pb_event_len); + break; default: WMA_LOGE("Wake reason %s(%u) is not a piggybacked event", wma_wow_wake_reason_str(wake_reason), wake_reason); @@ -5755,9 +5847,7 @@ int wma_chan_info_event_handler(void *handle, uint8_t *event_buf, tpAniSirGlobal mac = NULL; struct lim_channel_status *channel_status; - WMA_LOGD("%s: Enter", __func__); - - if (wma != NULL && wma->cds_context != NULL) + if (wma && wma->cds_context) mac = (tpAniSirGlobal)cds_get_context(QDF_MODULE_ID_PE); if (!mac) { @@ -5765,7 +5855,7 @@ int wma_chan_info_event_handler(void *handle, uint8_t *event_buf, return -EINVAL; } - WMA_LOGD("%s: monitor:%d", __func__, mac->snr_monitor_enabled); + if (mac->snr_monitor_enabled && mac->chan_info_cb) { param_buf = (WMI_CHAN_INFO_EVENTID_param_tlvs *)event_buf; @@ -5803,13 +5893,10 @@ int wma_chan_info_event_handler(void *handle, uint8_t *event_buf, WMA_LOGE(FL("Mem alloc fail")); return -ENOMEM; } - WMA_LOGD(FL("freq=%d nf=%d rxcnt=%u cyccnt=%u tx_r=%d tx_t=%d"), - event->freq, - event->noise_floor, - event->rx_clear_count, - event->cycle_count, - event->chan_tx_pwr_range, - event->chan_tx_pwr_tp); + wma_debug("freq %d nf %d rxcnt %u cyccnt %u tx_r %d tx_t %d", + event->freq, event->noise_floor, + event->rx_clear_count, event->cycle_count, + event->chan_tx_pwr_range, event->chan_tx_pwr_tp); channel_status->channelfreq = event->freq; channel_status->noise_floor = event->noise_floor; @@ -6093,3 +6180,50 @@ int wma_vdev_bss_color_collision_info_handler(void *handle, return 0; } + +#ifdef FEATURE_ANI_LEVEL_REQUEST +int wma_get_ani_level_evt_handler(void *handle, uint8_t *event_buf, + uint32_t len) +{ + tp_wma_handle wma = (tp_wma_handle)handle; + struct wmi_host_ani_level_event *ani = NULL; + uint32_t num_freqs = 0; + QDF_STATUS status; + tpAniSirGlobal pmac; + int ret = 0; + + pmac = (tpAniSirGlobal)cds_get_context(QDF_MODULE_ID_PE); + if (!pmac || !wma) { + WMA_LOGE(FL("Invalid pmac or wma")); + return -EINVAL; + } + + status = wmi_unified_extract_ani_level(wma->wmi_handle, event_buf, + &ani, &num_freqs); + + if (QDF_IS_STATUS_ERROR(status)) { + WMA_LOGE("%s: Failed to extract ani level", __func__); + return -EINVAL; + } + + if (!pmac->ani_params.ani_level_cb) { + WMA_LOGE(FL("Invalid ani_level_cb")); + ret = -EINVAL; + goto free; + } + + pmac->ani_params.ani_level_cb(ani, num_freqs, + pmac->ani_params.context); + +free: + qdf_mem_free(ani); + return ret; +} +#else +int wma_get_ani_level_evt_handler(void *handle, uint8_t *event_buf, + uint32_t len) +{ + return 0; +} +#endif + diff --git a/drivers/staging/qcacld-3.0/core/wma/src/wma_main.c b/drivers/staging/qcacld-3.0/core/wma/src/wma_main.c index bf1c10ca550f..c46e37bb6434 100644 --- a/drivers/staging/qcacld-3.0/core/wma/src/wma_main.c +++ b/drivers/staging/qcacld-3.0/core/wma/src/wma_main.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -91,6 +91,11 @@ #include "wlan_cp_stats_mc_ucfg_api.h" #include "init_cmd_api.h" #include "wma_coex.h" +#include + +#ifdef WLAN_FEATURE_PKT_CAPTURE +#include "wlan_pkt_capture_ucfg_api.h" +#endif #define WMA_LOG_COMPLETION_TIMER 3000 /* 3 seconds */ #define WMI_TLV_HEADROOM 128 @@ -262,12 +267,13 @@ static void wma_reset_rx_decap_mode(target_resource_config *tgt_cfg) * Return: none */ static void wma_set_default_tgt_config(tp_wma_handle wma_handle, - target_resource_config *tgt_cfg) + target_resource_config *tgt_cfg, + struct cds_config_info *cds_cfg) { uint8_t no_of_peers_supported; qdf_mem_zero(tgt_cfg, sizeof(target_resource_config)); - tgt_cfg->num_vdevs = CFG_TGT_NUM_VDEV; + tgt_cfg->num_vdevs = cds_cfg->num_vdevs; tgt_cfg->num_peers = CFG_TGT_NUM_PEERS + CFG_TGT_NUM_VDEV + 2; tgt_cfg->num_offload_peers = CFG_TGT_NUM_OFFLOAD_PEERS; tgt_cfg->num_offload_reorder_buffs = CFG_TGT_NUM_OFFLOAD_REORDER_BUFFS; @@ -996,10 +1002,8 @@ static void wma_process_cli_set_cmd(tp_wma_handle wma, struct target_psoc_info *tgt_hdl; struct sir_set_tx_rx_aggregation_size aggr; - WMA_LOGD("wmihandle %pK", wma->wmi_handle); qdf_mem_zero(&aggr, sizeof(aggr)); - - if (NULL == pMac) { + if (!pMac) { WMA_LOGE("%s: Failed to get pMac", __func__); return; } @@ -1834,6 +1838,33 @@ int wma_process_fw_event_handler(void *ctx, void *htc_packet, uint8_t rx_ctx) } #ifdef WLAN_FEATURE_NAN +/** + * wma_nan_set_separate_iface_support() - set separate_iface_support flag in WMA handle + * @wma_handle: Pointer to wma handle + * @cds_cfg: Pointer to CDS Configuration + * + * Return: none + */ +static void wma_nan_set_separate_iface_support(tp_wma_handle wma_handle, + struct cds_config_info *cds_cfg) +{ + wma_handle->nan_separate_iface_support = + cds_cfg->nan_separate_iface_support; +} + +/** + * wma_get_separate_iface_support() - get separate_iface_support flag in + * WMA handle + * @wma_handle: Pointer to wma handle + * @cds_cfg: Pointer to CDS Configuration + * + * Return: flag value + */ +static bool wma_get_separate_iface_support(tp_wma_handle wma_handle) +{ + return wma_handle->nan_separate_iface_support; +} + /** * wma_set_nan_enable() - set nan enable flag in WMA handle * @wma_handle: Pointer to wma handle @@ -1847,10 +1878,19 @@ static void wma_set_nan_enable(tp_wma_handle wma_handle, wma_handle->is_nan_enabled = cds_cfg->is_nan_enabled; } #else +static void wma_nan_set_separate_iface_support(tp_wma_handle wma_handle, + struct cds_config_info *cds_cfg) +{ +} +static bool wma_get_separate_iface_support(tp_wma_handle wma_handle) +{ + return false; +} static void wma_set_nan_enable(tp_wma_handle wma_handle, struct cds_config_info *cds_cfg) { } + #endif /** @@ -3150,6 +3190,23 @@ void wma_get_phy_mode_cb(uint8_t chan, uint32_t chan_width, uint32_t *phy_mode) *phy_mode = wma_chan_phy_mode(chan, chan_width, dot11_mode); } +#ifdef WLAN_FEATURE_PKT_CAPTURE +static void +wma_register_pkt_capture_callbacks(tp_wma_handle wma_handle) +{ + struct pkt_capture_callbacks cb_obj = {0}; + + cb_obj.get_rmf_status = wma_get_rmf_status; + + ucfg_pkt_capture_register_wma_callbacks(wma_handle->psoc, &cb_obj); +} +#else +static inline void +wma_register_pkt_capture_callbacks(tp_wma_handle wma_handle) +{ +} +#endif + /** * wma_open() - Allocate wma context and initialize it. * @cds_context: cds context @@ -3236,6 +3293,8 @@ QDF_STATUS wma_open(struct wlan_objmgr_psoc *psoc, "wlan_auto_shutdown_wl"); qdf_wake_lock_create(&wma_handle->roam_ho_wl, "wlan_roam_ho_wl"); + qdf_wake_lock_create(&wma_handle->roam_preauth_wl, + "wlan_roam_preauth_wl"); } qdf_status = wlan_objmgr_psoc_try_get_ref(psoc, WLAN_LEGACY_WMA_ID); @@ -3306,7 +3365,8 @@ QDF_STATUS wma_open(struct wlan_objmgr_psoc *psoc, wma_handle->enable_three_way_coex_config_legacy = cds_cfg->enable_three_way_coex_config_legacy; - + wma_handle->bmiss_skip_full_scan = + cds_cfg->bmiss_skip_full_scan; /* Register Converged Event handlers */ init_deinit_register_tgt_psoc_ev_handlers(psoc); @@ -3325,7 +3385,7 @@ QDF_STATUS wma_open(struct wlan_objmgr_psoc *psoc, goto err_wma_handle; } - wma_set_default_tgt_config(wma_handle, wlan_res_cfg); + wma_set_default_tgt_config(wma_handle, wlan_res_cfg, cds_cfg); wma_handle->tx_chain_mask_cck = cds_cfg->tx_chain_mask_cck; wma_handle->self_gen_frm_pwr = cds_cfg->self_gen_frm_pwr; @@ -3362,6 +3422,8 @@ QDF_STATUS wma_open(struct wlan_objmgr_psoc *psoc, wma_handle->is_lpass_enabled = cds_cfg->is_lpass_enabled; #endif wma_set_nan_enable(wma_handle, cds_cfg); + wma_nan_set_separate_iface_support(wma_handle, cds_cfg); + wma_handle->interfaces = qdf_mem_malloc(sizeof(struct wma_txrx_node) * wma_handle->max_bssid); if (!wma_handle->interfaces) { @@ -3549,6 +3611,13 @@ QDF_STATUS wma_open(struct wlan_objmgr_psoc *psoc, wma_cold_boot_cal_event_handler, WMA_RX_WORK_CTX); +#ifdef FEATURE_OEM_DATA + wmi_unified_register_event_handler(wma_handle->wmi_handle, + wmi_oem_data_event_id, + wma_oem_event_handler, + WMA_RX_WORK_CTX); +#endif + #ifdef WLAN_FEATURE_LINK_LAYER_STATS /* Register event handler for processing Link Layer Stats * response from the FW @@ -3626,6 +3695,20 @@ QDF_STATUS wma_open(struct wlan_objmgr_psoc *psoc, wmi_roam_synch_frame_event_id, wma_roam_synch_frame_event_handler, WMA_RX_SERIALIZER_CTX); + wmi_unified_register_event_handler(wma_handle->wmi_handle, + wmi_roam_auth_offload_event_id, + wma_roam_auth_offload_event_handler, + WMA_RX_SERIALIZER_CTX); + + wma_register_pmkid_req_event_handler(wma_handle); + wmi_unified_register_event_handler(wma_handle->wmi_handle, + wmi_roam_stats_event_id, + wma_roam_stats_event_handler, + WMA_RX_SERIALIZER_CTX); + wmi_unified_register_event_handler(wma_handle->wmi_handle, + wmi_roam_scan_chan_list_id, + wma_roam_scan_chan_event_handler, + WMA_RX_SERIALIZER_CTX); #endif /* WLAN_FEATURE_ROAM_OFFLOAD */ wmi_unified_register_event_handler(wma_handle->wmi_handle, wmi_rssi_breach_event_id, @@ -3685,6 +3768,10 @@ QDF_STATUS wma_open(struct wlan_objmgr_psoc *psoc, wma_pdev_div_info_evt_handler, WMA_RX_WORK_CTX); + wmi_unified_register_event_handler(wma_handle->wmi_handle, + wmi_get_ani_level_event_id, + wma_get_ani_level_evt_handler, + WMA_RX_WORK_CTX); wma_register_debug_callback(); wifi_pos_register_get_phy_mode_cb(wma_handle->psoc, @@ -3704,6 +3791,7 @@ QDF_STATUS wma_open(struct wlan_objmgr_psoc *psoc, pmo_register_get_beacon_interval_callback(wma_handle->psoc, wma_vdev_get_beacon_interval); wma_cbacks.wma_get_connection_info = wma_get_connection_info; + wma_register_pkt_capture_callbacks(wma_handle); qdf_status = policy_mgr_register_wma_cb(wma_handle->psoc, &wma_cbacks); if (!QDF_IS_STATUS_SUCCESS(qdf_status)) { WMA_LOGE("Failed to register wma cb with Policy Manager"); @@ -3771,6 +3859,7 @@ QDF_STATUS wma_open(struct wlan_objmgr_psoc *psoc, qdf_wake_lock_destroy(&wma_handle->wow_ap_assoc_lost_wl); qdf_wake_lock_destroy(&wma_handle->wow_auto_shutdown_wl); qdf_wake_lock_destroy(&wma_handle->roam_ho_wl); + qdf_wake_lock_destroy(&wma_handle->roam_preauth_wl); } err_free_wma_handle: cds_free_context(QDF_MODULE_ID_WMA, wma_handle); @@ -4473,7 +4562,7 @@ QDF_STATUS wma_start(void) goto end; } } else { - WMA_LOGE("Target does not support cesium network"); + WMA_LOGD("Target does not support cesium network"); } qdf_status = wma_tx_attach(wma_handle); @@ -4791,6 +4880,7 @@ QDF_STATUS wma_close(void) qdf_wake_lock_destroy(&wma_handle->wow_ap_assoc_lost_wl); qdf_wake_lock_destroy(&wma_handle->wow_auto_shutdown_wl); qdf_wake_lock_destroy(&wma_handle->roam_ho_wl); + qdf_wake_lock_destroy(&wma_handle->roam_preauth_wl); } /* unregister Firmware debug log */ @@ -5008,6 +5098,25 @@ static inline void wma_update_target_services(struct wmi_unified *wmi_handle, wmi_service_11k_neighbour_report_support)) cfg->is_11k_offload_supported = true; + if (wmi_service_enabled(wmi_handle, wmi_service_wpa3_ft_sae_support)) + cfg->akm_service_bitmap |= (1 << AKM_FT_SAE); + + if (wmi_service_enabled(wmi_handle, + wmi_service_wpa3_ft_suite_b_support)) + cfg->akm_service_bitmap |= (1 << AKM_FT_SUITEB_SHA384); + + if (wmi_service_enabled(wmi_handle,wmi_service_ft_fils)) + cfg->akm_service_bitmap |= (1 << AKM_FT_FILS); + + if (wmi_service_enabled(wmi_handle, wmi_service_owe_roam_support)) + cfg->akm_service_bitmap |= (1 << AKM_OWE); + + if (wmi_service_enabled(wmi_handle, wmi_service_sae_roam_support)) + cfg->akm_service_bitmap |= (1 << AKM_SAE); + + if (wmi_service_enabled(wmi_handle, wmi_service_adaptive_11r_support)) + cfg->is_adaptive_11r_roam_supported = true; + if (wmi_service_enabled(wmi_handle, wmi_service_twt_requestor)) cfg->twt_requestor = true; if (wmi_service_enabled(wmi_handle, wmi_service_twt_responder)) @@ -5016,6 +5125,9 @@ static inline void wma_update_target_services(struct wmi_unified *wmi_handle, cfg->bcn_reception_stats = true; if (wmi_service_enabled(wmi_handle, wmi_service_vdev_latency_config)) g_fw_wlan_feat_caps |= (1 << VDEV_LATENCY_CONFIG); + if (wmi_service_enabled(wmi_handle, + wmi_roam_scan_chan_list_to_host_support)) + cfg->is_roam_scan_ch_to_host = true; } /** @@ -5703,6 +5815,13 @@ static int wma_update_hdd_cfg(tp_wma_handle wma_handle) for (i = 0; i < tgt_hdl->info.total_mac_phy_cnt; i++) wma_fill_chain_cfg(&tgt_cfg, tgt_hdl, i); + if (wmi_service_enabled(wma_handle->wmi_handle, wmi_service_nan_vdev)) + tgt_cfg.nan_seperate_vdev_support = true; + + wlan_res_cfg->nan_separate_iface_support = + tgt_cfg.nan_seperate_vdev_support && + wma_get_separate_iface_support(wma_handle); + ret = wma_handle->tgt_cfg_update_cb(hdd_ctx, &tgt_cfg); if (ret) return -EINVAL; @@ -6827,6 +6946,15 @@ int wma_rx_service_ready_ext_event(void *handle, uint8_t *event, wlan_res_cfg->three_way_coex_config_legacy_en = false; } + if (ucfg_is_ftm_time_sync_enable(wma_handle->psoc) && + wmi_service_enabled(wmi_handle, wmi_service_time_sync_ftm)) { + wlan_res_cfg->time_sync_ftm = true; + ucfg_ftm_time_sync_set_enable(wma_handle->psoc, true); + } else { + wlan_res_cfg->time_sync_ftm = false; + ucfg_ftm_time_sync_set_enable(wma_handle->psoc, false); + } + return 0; } @@ -8204,16 +8332,6 @@ static QDF_STATUS wma_mc_process_msg(struct scheduler_msg *msg) qdf_mem_free(msg->bodyptr); break; #endif /* REMOVE_PKT_LOG */ - case WMA_ENTER_PS_REQ: - wma_enable_sta_ps_mode(wma_handle, - (tpEnablePsParams) msg->bodyptr); - qdf_mem_free(msg->bodyptr); - break; - case WMA_EXIT_PS_REQ: - wma_disable_sta_ps_mode(wma_handle, - (tpDisablePsParams) msg->bodyptr); - qdf_mem_free(msg->bodyptr); - break; case WMA_ENABLE_UAPSD_REQ: wma_enable_uapsd_mode(wma_handle, (tpEnableUapsdParams) msg->bodyptr); @@ -8303,6 +8421,16 @@ static QDF_STATUS wma_mc_process_msg(struct scheduler_msg *msg) (tSirRoamOffloadScanReq *) msg->bodyptr); break; + case WMA_ROAM_SYNC_TIMEOUT: + wma_handle_roam_sync_timeout(wma_handle, msg->bodyptr); + qdf_mem_free(msg->bodyptr); + break; + + case WMA_ROAM_PRE_AUTH_STATUS: + wma_send_roam_preauth_status(wma_handle, msg->bodyptr); + qdf_mem_free(msg->bodyptr); + break; + case WMA_RATE_UPDATE_IND: wma_process_rate_update_indicate(wma_handle, (tSirRateUpdateInd *) msg->bodyptr); @@ -8786,6 +8914,13 @@ static QDF_STATUS wma_mc_process_msg(struct scheduler_msg *msg) qdf_mem_free(msg->bodyptr); break; #endif + case WMA_SET_ROAM_TRIGGERS: + wma_set_roam_triggers(wma_handle, msg->bodyptr); + qdf_mem_free(msg->bodyptr); + break; + case WMA_ROAM_SCAN_CH_REQ: + wma_get_roam_scan_ch(wma_handle, msg->bodyval); + break; default: WMA_LOGD("Unhandled WMA message of type %d", msg->type); if (msg->bodyptr) @@ -8904,15 +9039,16 @@ QDF_STATUS wma_send_pdev_set_pcl_cmd(tp_wma_handle wma_handle, WLAN_REG_IS_5GHZ_CH(msg->chan_weights.saved_chan_list[i])) msg->chan_weights.weighed_valid_list[i] = WEIGHT_OF_DISALLOWED_CHANNELS; - WMA_LOGD("%s: chan:%d weight[%d]=%d", __func__, - msg->chan_weights.saved_chan_list[i], i, - msg->chan_weights.weighed_valid_list[i]); } if (!QDF_IS_STATUS_SUCCESS(status)) { WMA_LOGE("%s: Error in creating weighed pcl", __func__); return status; } + wma_debug("Dump channel list send to wmi"); + policy_mgr_dump_channel_list(msg->chan_weights.saved_num_chan, + msg->chan_weights.saved_chan_list, + msg->chan_weights.weighed_valid_list); if (wmi_unified_pdev_set_pcl_cmd(wma_handle->wmi_handle, &msg->chan_weights)) @@ -9317,3 +9453,11 @@ QDF_STATUS wma_config_bmiss_bcnt_params(uint32_t vdev_id, uint32_t first_cnt, return status; } +#ifdef FEATURE_ANI_LEVEL_REQUEST +QDF_STATUS wma_send_ani_level_request(tp_wma_handle wma_handle, + uint32_t *freqs, uint8_t num_freqs) +{ + return wmi_unified_ani_level_cmd_send(wma_handle->wmi_handle, freqs, + num_freqs); +} +#endif diff --git a/drivers/staging/qcacld-3.0/core/wma/src/wma_mgmt.c b/drivers/staging/qcacld-3.0/core/wma/src/wma_mgmt.c index 44bc9393f517..19a3f47956e3 100644 --- a/drivers/staging/qcacld-3.0/core/wma/src/wma_mgmt.c +++ b/drivers/staging/qcacld-3.0/core/wma/src/wma_mgmt.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -73,6 +73,7 @@ #include #include "wma_twt.h" #include +#include "wlan_pkt_capture_ucfg_api.h" #include /** @@ -275,7 +276,7 @@ int wma_beacon_swba_handler(void *handle, uint8_t *event, uint32_t len) return -EINVAL; } - WMA_LOGD("vdev_map = %d", vdev_map); + wma_debug("vdev_map = %d", vdev_map); for (; vdev_map && vdev_id < wma->max_bssid; vdev_id++, vdev_map >>= 1) { if (!(vdev_map & 0x1)) @@ -327,7 +328,6 @@ int wma_peer_sta_kickout_event_handler(void *handle, u8 *event, u32 len) tpSirIbssPeerInactivityInd p_inactivity; void *soc = cds_get_context(QDF_MODULE_ID_SOC); - WMA_LOGD("%s: Enter", __func__); param_buf = (WMI_PEER_STA_KICKOUT_EVENTID_param_tlvs *) event; kickout_event = param_buf->fixed_param; pdev = cds_get_context(QDF_MODULE_ID_TXRX); @@ -347,9 +347,9 @@ int wma_peer_sta_kickout_event_handler(void *handle, u8 *event, u32 len) return -EINVAL; } - WMA_LOGA("%s: PEER:[%pM], ADDR:[%pN], INTERFACE:%d, peer_id:%d, reason:%d", - __func__, macaddr, wma->interfaces[vdev_id].addr, vdev_id, - peer_id, kickout_event->reason); + wma_nofl_info("STA kickout for %pM, on mac %pM, vdev %d, reason:%d", + macaddr, wma->interfaces[vdev_id].addr, + vdev_id, kickout_event->reason); if (wma->interfaces[vdev_id].roaming_in_progress) { WMA_LOGE("Ignore STA kick out since roaming is in progress"); return -EINVAL; @@ -392,32 +392,6 @@ int wma_peer_sta_kickout_event_handler(void *handle, u8 *event, u32 len) (void *)del_sta_ctx, 0); goto exit_handler; #endif /* FEATURE_WLAN_TDLS */ - case WMI_PEER_STA_KICKOUT_REASON_XRETRY: - if (wma->interfaces[vdev_id].type == WMI_VDEV_TYPE_STA && - (wma->interfaces[vdev_id].sub_type == 0 || - wma->interfaces[vdev_id].sub_type == - WMI_UNIFIED_VDEV_SUBTYPE_P2P_CLIENT) && - !qdf_mem_cmp(wma->interfaces[vdev_id].bssid, - macaddr, IEEE80211_ADDR_LEN)) { - wma_sta_kickout_event(HOST_STA_KICKOUT_REASON_XRETRY, - vdev_id, macaddr); - /* - * KICKOUT event is for current station-AP connection. - * Treat it like final beacon miss. Station may not have - * missed beacons but not able to transmit frames to AP - * for a long time. Must disconnect to get out of - * this sticky situation. - * In future implementation, roaming module will also - * handle this event and perform a scan. - */ - WMA_LOGW("%s: WMI_PEER_STA_KICKOUT_REASON_XRETRY event for STA", - __func__); - wma_beacon_miss_handler(wma, vdev_id, - kickout_event->rssi); - goto exit_handler; - } - break; - case WMI_PEER_STA_KICKOUT_REASON_UNSPECIFIED: /* * Default legacy value used by original firmware implementation @@ -447,6 +421,7 @@ int wma_peer_sta_kickout_event_handler(void *handle, u8 *event, u32 len) } break; + case WMI_PEER_STA_KICKOUT_REASON_XRETRY: case WMI_PEER_STA_KICKOUT_REASON_INACTIVITY: /* * Handle SA query kickout is same as inactivity kickout. @@ -473,16 +448,22 @@ int wma_peer_sta_kickout_event_handler(void *handle, u8 *event, u32 len) qdf_mem_copy(del_sta_ctx->addr2, macaddr, IEEE80211_ADDR_LEN); qdf_mem_copy(del_sta_ctx->bssId, wma->interfaces[vdev_id].addr, IEEE80211_ADDR_LEN); - del_sta_ctx->reasonCode = HAL_DEL_STA_REASON_CODE_KEEP_ALIVE; + if (kickout_event->reason == + WMI_PEER_STA_KICKOUT_REASON_SA_QUERY_TIMEOUT) + del_sta_ctx->reasonCode = + HAL_DEL_STA_REASON_CODE_SA_QUERY_TIMEOUT; + else if (kickout_event->reason == + WMI_PEER_STA_KICKOUT_REASON_XRETRY) + del_sta_ctx->reasonCode = HAL_DEL_STA_REASON_CODE_XRETRY; + else + del_sta_ctx->reasonCode = HAL_DEL_STA_REASON_CODE_KEEP_ALIVE; del_sta_ctx->rssi = kickout_event->rssi + WMA_TGT_NOISE_FLOOR_DBM; - wma_sta_kickout_event(HOST_STA_KICKOUT_REASON_KEEP_ALIVE, - vdev_id, macaddr); + wma_sta_kickout_event(del_sta_ctx->reasonCode, vdev_id, macaddr); wma_send_msg(wma, SIR_LIM_DELETE_STA_CONTEXT_IND, (void *)del_sta_ctx, 0); wma_lost_link_info_handler(wma, vdev_id, kickout_event->rssi + WMA_TGT_NOISE_FLOOR_DBM); exit_handler: - WMA_LOGD("%s: Exit", __func__); return 0; } @@ -518,8 +499,6 @@ int wma_unified_bcntx_status_event_handler(void *handle, resp_event = param_buf->fixed_param; - WMA_LOGD("%s", __func__); - if (resp_event->vdev_id >= wma->max_bssid) { WMA_LOGE("%s: received invalid vdev_id %d", __func__, resp_event->vdev_id); @@ -672,7 +651,7 @@ void wma_set_vdev_mgmt_rate(tp_wma_handle wma, uint8_t vdev_id) band = CDS_BAND_ALL; if ((cfg_val == WNI_CFG_RATE_FOR_TX_MGMT_STADEF) || !wma_verify_rate_code(cfg_val, band)) { - WMA_LOGD("default WNI_CFG_RATE_FOR_TX_MGMT, ignore"); + wma_nofl_debug("default WNI_CFG_RATE_FOR_TX_MGMT, ignore"); } else { ret = wma_vdev_set_param( wma->wmi_handle, @@ -693,7 +672,7 @@ void wma_set_vdev_mgmt_rate(tp_wma_handle wma, uint8_t vdev_id) band = CDS_BAND_2GHZ; if ((cfg_val == WNI_CFG_RATE_FOR_TX_MGMT_2G_STADEF) || !wma_verify_rate_code(cfg_val, band)) { - WMA_LOGD("use default 2G MGMT rate."); + wma_nofl_debug("use default 2G MGMT rate."); per_band_mgmt_tx_rate &= ~(1 << TX_MGMT_RATE_2G_ENABLE_OFFSET); } else { @@ -711,7 +690,7 @@ void wma_set_vdev_mgmt_rate(tp_wma_handle wma, uint8_t vdev_id) band = CDS_BAND_5GHZ; if ((cfg_val == WNI_CFG_RATE_FOR_TX_MGMT_5G_STADEF) || !wma_verify_rate_code(cfg_val, band)) { - WMA_LOGD("use default 5G MGMT rate."); + wma_nofl_debug("use default 5G MGMT rate."); per_band_mgmt_tx_rate &= ~(1 << TX_MGMT_RATE_5G_ENABLE_OFFSET); } else { @@ -775,9 +754,9 @@ void wma_set_sap_keepalive(tp_wma_handle wma, uint8_t vdev_id) if (QDF_IS_STATUS_ERROR(status)) WMA_LOGE("Failed to Set MAX UNRESPONSIVE TIME"); - WMA_LOGD("%s:vdev_id:%d min_inactive_time: %u max_inactive_time: %u max_unresponsive_time: %u", - __func__, vdev_id, - min_inactive_time, max_inactive_time, max_unresponsive_time); + wma_debug("vdev_id:%d min_inactive_time: %u max_inactive_time: %u max_unresponsive_time: %u", + vdev_id, min_inactive_time, max_inactive_time, + max_unresponsive_time); } /** @@ -796,8 +775,6 @@ void wma_set_sta_sa_query_param(tp_wma_handle wma, struct sAniSirGlobal *mac = cds_get_context(QDF_MODULE_ID_PE); uint32_t max_retries, retry_interval; - WMA_LOGD(FL("Enter:")); - if (!mac) { WMA_LOGE(FL("mac context is NULL")); return; @@ -819,8 +796,6 @@ void wma_set_sta_sa_query_param(tp_wma_handle wma, vdev_id, max_retries, retry_interval); - - WMA_LOGD(FL("Exit :")); } /** @@ -844,8 +819,6 @@ void wma_set_sta_keep_alive(tp_wma_handle wma, uint8_t vdev_id, { struct sta_params params; - WMA_LOGD("%s: Enter", __func__); - if (!wma) { WMA_LOGE("%s: wma handle is NULL", __func__); return; @@ -866,7 +839,6 @@ void wma_set_sta_keep_alive(tp_wma_handle wma, uint8_t vdev_id, wmi_unified_set_sta_keep_alive_cmd(wma->wmi_handle, ¶ms); - WMA_LOGD("%s: Exit", __func__); } /** @@ -905,7 +877,7 @@ int wma_vdev_install_key_complete_event_handler(void *handle, /* * Do nothing for now. Completion of set key is already indicated to lim */ - WMA_LOGD("%s: WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID", __func__); + wma_debug("WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID"); return 0; } /* @@ -1005,7 +977,7 @@ static void wma_mask_tx_ht_rate(tp_wma_handle wma, uint8_t *mcs_set) } if (mcs_limit & CFG_CTRL_MASK) { - WMA_LOGD("%s: set mcs_limit %x", __func__, mcs_limit); + wma_debug("set mcs_limit %x", mcs_limit); mcs_limit &= CFG_DATA_MASK; for (i = 0, j = 0; i < MAX_SUPPORTED_RATES;) { @@ -1039,34 +1011,32 @@ static void wma_mask_tx_ht_rate(tp_wma_handle wma, uint8_t *mcs_set) * Return: one of the 11ax values defined in enum wlan_phymode; * or WLAN_PHYMODE_AUTO if the input is not an 11ax phymode */ -static enum wlan_phymode wma_fw_to_host_phymode_11ac(WLAN_PHY_MODE phymode) +static enum wlan_phymode wma_fw_to_host_phymode_11ac(WMI_HOST_WLAN_PHY_MODE phymode) { switch (phymode) { default: return WLAN_PHYMODE_AUTO; -#if SUPPORT_11AX - case MODE_11AX_HE20: + case WMI_HOST_MODE_11AX_HE20: return WLAN_PHYMODE_11AC_VHT20; - case MODE_11AX_HE40: + case WMI_HOST_MODE_11AX_HE40: return WLAN_PHYMODE_11AC_VHT40; - case MODE_11AX_HE80: + case WMI_HOST_MODE_11AX_HE80: return WLAN_PHYMODE_11AC_VHT80; - case MODE_11AX_HE80_80: + case WMI_HOST_MODE_11AX_HE80_80: return WLAN_PHYMODE_11AC_VHT80_80; - case MODE_11AX_HE160: + case WMI_HOST_MODE_11AX_HE160: return WLAN_PHYMODE_11AC_VHT160; - case MODE_11AX_HE20_2G: + case WMI_HOST_MODE_11AX_HE20_2G: return WLAN_PHYMODE_11AC_VHT20; - case MODE_11AX_HE40_2G: + case WMI_HOST_MODE_11AX_HE40_2G: return WLAN_PHYMODE_11AC_VHT40; - case MODE_11AX_HE80_2G: + case WMI_HOST_MODE_11AX_HE80_2G: return WLAN_PHYMODE_11AC_VHT80; -#endif } return WLAN_PHYMODE_AUTO; } #else -static enum wlan_phymode wma_fw_to_host_phymode_11ac(WLAN_PHY_MODE phymode) +static enum wlan_phymode wma_fw_to_host_phymode_11ac(WMI_HOST_WLAN_PHY_MODE phymode) { return WLAN_PHYMODE_AUTO; } @@ -1081,31 +1051,27 @@ static enum wlan_phymode wma_fw_to_host_phymode_11ac(WLAN_PHY_MODE phymode) * Return: one of the 160 mhz values defined in enum wlan_phymode; * or WLAN_PHYMODE_AUTO if the input is not a 160 mhz phymode */ -static enum wlan_phymode wma_fw_to_host_phymode_160(WLAN_PHY_MODE phymode) +static enum wlan_phymode +wma_fw_to_host_phymode_160(WMI_HOST_WLAN_PHY_MODE phymode) { switch (phymode) { default: return WLAN_PHYMODE_AUTO; - case MODE_11AC_VHT80_80: + case WMI_HOST_MODE_11AC_VHT80_80: return WLAN_PHYMODE_11AC_VHT80_80; - case MODE_11AC_VHT160: + case WMI_HOST_MODE_11AC_VHT160: return WLAN_PHYMODE_11AC_VHT160; } } #else -static enum wlan_phymode wma_fw_to_host_phymode_160(WLAN_PHY_MODE phymode) +static enum wlan_phymode +wma_fw_to_host_phymode_160(WMI_HOST_WLAN_PHY_MODE phymode) { return WLAN_PHYMODE_AUTO; } #endif -/** - * wma_fw_to_host_phymode() - convert fw to host phymode - * @phymode: phymode to convert - * - * Return: one of the values defined in enum wlan_phymode; - * or WLAN_PHYMODE_AUTO if the conversion fails - */ -static enum wlan_phymode wma_fw_to_host_phymode(WLAN_PHY_MODE phymode) + +enum wlan_phymode wma_fw_to_host_phymode(WMI_HOST_WLAN_PHY_MODE phymode) { enum wlan_phymode host_phymode; switch (phymode) { @@ -1114,34 +1080,34 @@ static enum wlan_phymode wma_fw_to_host_phymode(WLAN_PHY_MODE phymode) if (host_phymode != WLAN_PHYMODE_AUTO) return host_phymode; return wma_fw_to_host_phymode_11ac(phymode); - case MODE_11A: + case WMI_HOST_MODE_11A: return WLAN_PHYMODE_11A; - case MODE_11G: + case WMI_HOST_MODE_11G: return WLAN_PHYMODE_11G; - case MODE_11B: + case WMI_HOST_MODE_11B: return WLAN_PHYMODE_11B; - case MODE_11GONLY: - return WLAN_PHYMODE_11G; - case MODE_11NA_HT20: + case WMI_HOST_MODE_11GONLY: + return WLAN_PHYMODE_11G_ONLY; + case WMI_HOST_MODE_11NA_HT20: return WLAN_PHYMODE_11NA_HT20; - case MODE_11NG_HT20: + case WMI_HOST_MODE_11NG_HT20: return WLAN_PHYMODE_11NG_HT20; - case MODE_11NA_HT40: + case WMI_HOST_MODE_11NA_HT40: return WLAN_PHYMODE_11NA_HT40; - case MODE_11NG_HT40: + case WMI_HOST_MODE_11NG_HT40: return WLAN_PHYMODE_11NG_HT40; - case MODE_11AC_VHT20: + case WMI_HOST_MODE_11AC_VHT20: return WLAN_PHYMODE_11AC_VHT20; - case MODE_11AC_VHT40: + case WMI_HOST_MODE_11AC_VHT40: return WLAN_PHYMODE_11AC_VHT40; - case MODE_11AC_VHT80: - return WLAN_PHYMODE_11AC_VHT80; - case MODE_11AC_VHT20_2G: - return WLAN_PHYMODE_11AC_VHT20; - case MODE_11AC_VHT40_2G: - return WLAN_PHYMODE_11AC_VHT40; - case MODE_11AC_VHT80_2G: + case WMI_HOST_MODE_11AC_VHT80: return WLAN_PHYMODE_11AC_VHT80; + case WMI_HOST_MODE_11AC_VHT20_2G: + return WLAN_PHYMODE_11AC_VHT20_2G; + case WMI_HOST_MODE_11AC_VHT40_2G: + return WLAN_PHYMODE_11AC_VHT40_2G; + case WMI_HOST_MODE_11AC_VHT80_2G: + return WLAN_PHYMODE_11AC_VHT80_2G; } } @@ -1150,24 +1116,26 @@ static enum wlan_phymode wma_fw_to_host_phymode(WLAN_PHY_MODE phymode) * wma_host_to_fw_phymode_160() - convert host to fw phymode for 160 mhz * @host_phymode: phymode to convert * - * Return: one of the 160 mhz values defined in enum WLAN_PHY_MODE; - * or MODE_UNKNOWN if the input is not a 160 mhz phymode + * Return: one of the 160 mhz values defined in enum WMI_HOST_WLAN_PHY_MODE; + * or WMI_HOST_MODE_UNKNOWN if the input is not a 160 mhz phymode */ -static WLAN_PHY_MODE wma_host_to_fw_phymode_160(enum wlan_phymode host_phymode) +static WMI_HOST_WLAN_PHY_MODE +wma_host_to_fw_phymode_160(enum wlan_phymode host_phymode) { switch (host_phymode) { case WLAN_PHYMODE_11AC_VHT80_80: - return MODE_11AC_VHT80_80; + return WMI_HOST_MODE_11AC_VHT80_80; case WLAN_PHYMODE_11AC_VHT160: - return MODE_11AC_VHT160; + return WMI_HOST_MODE_11AC_VHT160; default: - return MODE_UNKNOWN; + return WMI_HOST_MODE_UNKNOWN; } } #else -static WLAN_PHY_MODE wma_host_to_fw_phymode_160(enum wlan_phymode host_phymode) +static WMI_HOST_WLAN_PHY_MODE +wma_host_to_fw_phymode_160(enum wlan_phymode host_phymode) { - return MODE_UNKNOWN; + return WMI_HOST_MODE_UNKNOWN; } #endif @@ -1176,68 +1144,84 @@ static WLAN_PHY_MODE wma_host_to_fw_phymode_160(enum wlan_phymode host_phymode) * wma_host_to_fw_phymode_11ax() - convert host to fw phymode for 11ax phymode * @host_phymode: phymode to convert * - * Return: one of the 11ax values defined in enum WLAN_PHY_MODE; - * or MODE_UNKNOWN if the input is not an 11ax phymode + * Return: one of the 11ax values defined in enum WMI_HOST_WLAN_PHY_MODE; + * or WMI_HOST_MODE_UNKNOWN if the input is not an 11ax phymode */ -static WLAN_PHY_MODE wma_host_to_fw_phymode_11ax(enum wlan_phymode host_phymode) +static WMI_HOST_WLAN_PHY_MODE +wma_host_to_fw_phymode_11ax(enum wlan_phymode host_phymode) { switch (host_phymode) { case WLAN_PHYMODE_11AXA_HE20: - return MODE_11AX_HE20; + return WMI_HOST_MODE_11AX_HE20; case WLAN_PHYMODE_11AXA_HE40: - return MODE_11AX_HE40; + return WMI_HOST_MODE_11AX_HE40; case WLAN_PHYMODE_11AXA_HE80: - return MODE_11AX_HE80; + return WMI_HOST_MODE_11AX_HE80; case WLAN_PHYMODE_11AXA_HE80_80: - return MODE_11AX_HE80_80; + return WMI_HOST_MODE_11AX_HE80_80; case WLAN_PHYMODE_11AXA_HE160: - return MODE_11AX_HE160; + return WMI_HOST_MODE_11AX_HE160; + case WLAN_PHYMODE_11AXG_HE20: + return WMI_HOST_MODE_11AX_HE20_2G; + case WLAN_PHYMODE_11AXG_HE40: + case WLAN_PHYMODE_11AXG_HE40PLUS: + case WLAN_PHYMODE_11AXG_HE40MINUS: + return WMI_HOST_MODE_11AX_HE40_2G; + case WLAN_PHYMODE_11AXG_HE80: + return WMI_HOST_MODE_11AX_HE80_2G; default: - return MODE_UNKNOWN; + return WMI_HOST_MODE_UNKNOWN; } } #else -static WLAN_PHY_MODE wma_host_to_fw_phymode_11ax(enum wlan_phymode host_phymode) +static WMI_HOST_WLAN_PHY_MODE +wma_host_to_fw_phymode_11ax(enum wlan_phymode host_phymode) { - return MODE_UNKNOWN; + return WMI_HOST_MODE_UNKNOWN; } #endif -/** - * wma_host_to_fw_phymode() - convert host to fw phymode - * @host_phymode: phymode to convert - * - * Return: one of the values defined in enum WLAN_PHY_MODE; - * or MODE_UNKNOWN if the conversion fails - */ -static WLAN_PHY_MODE wma_host_to_fw_phymode(enum wlan_phymode host_phymode) +WMI_HOST_WLAN_PHY_MODE +wma_host_to_fw_phymode(enum wlan_phymode host_phymode) { - WLAN_PHY_MODE fw_phymode; + WMI_HOST_WLAN_PHY_MODE fw_phymode; switch (host_phymode) { case WLAN_PHYMODE_11A: - return MODE_11A; + return WMI_HOST_MODE_11A; case WLAN_PHYMODE_11G: - return MODE_11G; + return WMI_HOST_MODE_11G; case WLAN_PHYMODE_11B: - return MODE_11B; + return WMI_HOST_MODE_11B; + case WLAN_PHYMODE_11G_ONLY: + return WMI_HOST_MODE_11GONLY; case WLAN_PHYMODE_11NA_HT20: - return MODE_11NA_HT20; + return WMI_HOST_MODE_11NA_HT20; case WLAN_PHYMODE_11NG_HT20: - return MODE_11NG_HT20; + return WMI_HOST_MODE_11NG_HT20; case WLAN_PHYMODE_11NA_HT40: - return MODE_11NA_HT40; + return WMI_HOST_MODE_11NA_HT40; case WLAN_PHYMODE_11NG_HT40: - return MODE_11NG_HT40; + case WLAN_PHYMODE_11NG_HT40PLUS: + case WLAN_PHYMODE_11NG_HT40MINUS: + return WMI_HOST_MODE_11NG_HT40; case WLAN_PHYMODE_11AC_VHT20: - return MODE_11AC_VHT20; + return WMI_HOST_MODE_11AC_VHT20; case WLAN_PHYMODE_11AC_VHT40: - return MODE_11AC_VHT40; + return WMI_HOST_MODE_11AC_VHT40; case WLAN_PHYMODE_11AC_VHT80: - return MODE_11AC_VHT80; + return WMI_HOST_MODE_11AC_VHT80; + case WLAN_PHYMODE_11AC_VHT20_2G: + return WMI_HOST_MODE_11AC_VHT20_2G; + case WLAN_PHYMODE_11AC_VHT40PLUS_2G: + case WLAN_PHYMODE_11AC_VHT40MINUS_2G: + case WLAN_PHYMODE_11AC_VHT40_2G: + return WMI_HOST_MODE_11AC_VHT40_2G; + case WLAN_PHYMODE_11AC_VHT80_2G: + return WMI_HOST_MODE_11AC_VHT80_2G; default: fw_phymode = wma_host_to_fw_phymode_160(host_phymode); - if (fw_phymode != MODE_UNKNOWN) + if (fw_phymode != WMI_HOST_MODE_UNKNOWN) return fw_phymode; return wma_host_to_fw_phymode_11ax(host_phymode); } @@ -1253,7 +1237,7 @@ static WLAN_PHY_MODE wma_host_to_fw_phymode(enum wlan_phymode host_phymode) */ static void wma_objmgr_set_peer_mlme_phymode(tp_wma_handle wma, uint8_t *mac_addr, - WLAN_PHY_MODE phymode) + WMI_HOST_WLAN_PHY_MODE phymode) { uint8_t pdev_id; struct wlan_objmgr_peer *peer; @@ -1262,10 +1246,8 @@ static void wma_objmgr_set_peer_mlme_phymode(tp_wma_handle wma, pdev_id = wlan_objmgr_pdev_get_pdev_id(wma->pdev); peer = wlan_objmgr_get_peer(psoc, pdev_id, mac_addr, WLAN_LEGACY_WMA_ID); - if (!peer) { - WMA_LOGE(FL("peer object null")); + if (!peer) return; - } wlan_peer_obj_lock(peer); wlan_peer_set_phymode(peer, wma_fw_to_host_phymode(phymode)); @@ -1434,7 +1416,8 @@ QDF_STATUS wma_send_peer_assoc(tp_wma_handle wma, if (params->uAPSD) { cmd->peer_flags |= WMI_PEER_APSD; - WMA_LOGD("Set WMI_PEER_APSD: uapsd Mask %d", params->uAPSD); + wma_nofl_debug("Set WMI_PEER_APSD: uapsd Mask %d", + params->uAPSD); } if (params->htCapable) { @@ -1501,9 +1484,10 @@ QDF_STATUS wma_send_peer_assoc(tp_wma_handle wma, || params->encryptType == eSIR_ED_WPI #endif /* FEATURE_WLAN_WAPI */ ) { - cmd->peer_flags |= WMI_PEER_NEED_PTK_4_WAY; - WMA_LOGD("Acquire set key wake lock for %d ms", - WMA_VDEV_SET_KEY_WAKELOCK_TIMEOUT); + if (!params->no_ptk_4_way) + cmd->peer_flags |= WMI_PEER_NEED_PTK_4_WAY; + wma_nofl_debug("Acquire set key wake lock for %d ms", + WMA_VDEV_SET_KEY_WAKELOCK_TIMEOUT); wma_acquire_wakelock(&intr->vdev_set_key_wakelock, WMA_VDEV_SET_KEY_WAKELOCK_TIMEOUT); } @@ -1562,11 +1546,9 @@ QDF_STATUS wma_send_peer_assoc(tp_wma_handle wma, */ if (intr->tx_streams < 2) { cmd->peer_vht_caps &= ~(1 << SIR_MAC_VHT_CAP_TXSTBC); - WMA_LOGD("Num tx_streams: %d, Disabled txSTBC", - intr->tx_streams); + wma_nofl_debug("Num tx_streams: %d, Disabled txSTBC", + intr->tx_streams); } - WMA_LOGD("peer_nss %d peer_ht_rates.num_rates %d ", cmd->peer_nss, - peer_ht_rates.num_rates); cmd->vht_capable = params->vhtCapable; if (params->vhtCapable) { @@ -1584,9 +1566,9 @@ QDF_STATUS wma_send_peer_assoc(tp_wma_handle wma, } } - WMA_LOGD(FL("rx_max_rate: %d, rx_mcs: %x, tx_max_rate: %d, tx_mcs: %x"), - cmd->rx_max_rate, cmd->rx_mcs_set, cmd->tx_max_rate, - cmd->tx_mcs_set); + wma_debug("rx_max_rate %d, rx_mcs %x, tx_max_rate %d, tx_mcs: %x num rates %d`", + cmd->rx_max_rate, cmd->rx_mcs_set, cmd->tx_max_rate, + cmd->tx_mcs_set, peer_ht_rates.num_rates); /* * Limit nss to max number of rf chain supported by target @@ -1599,15 +1581,6 @@ QDF_STATUS wma_send_peer_assoc(tp_wma_handle wma, intr->nss = cmd->peer_nss; cmd->peer_phymode = phymode; - WMA_LOGD("%s: vdev_id %d associd %d peer_flags %x rate_caps %x peer_caps %x", - __func__, cmd->vdev_id, cmd->peer_associd, cmd->peer_flags, - cmd->peer_rate_caps, cmd->peer_caps); - WMA_LOGD("%s:listen_intval %d ht_caps %x max_mpdu %d nss %d phymode %d", - __func__, cmd->peer_listen_intval, cmd->peer_ht_caps, - cmd->peer_max_mpdu, cmd->peer_nss, cmd->peer_phymode); - WMA_LOGD("%s: peer_mpdu_density %d encr_type %d cmd->peer_vht_caps %x", - __func__, cmd->peer_mpdu_density, params->encryptType, - cmd->peer_vht_caps); status = wmi_unified_peer_assoc_send(wma->wmi_handle, cmd); @@ -1674,7 +1647,8 @@ void wma_update_protection_mode(tp_wma_handle wma, uint8_t vdev_id, if (QDF_IS_STATUS_ERROR(ret)) WMA_LOGE("Failed to send wmi protection mode cmd"); else - WMA_LOGD("Updated protection mode %d to target", prot_mode); + wma_nofl_debug("Updated protection mode %d to target", + prot_mode); } void @@ -1714,8 +1688,8 @@ wma_update_bss_color(tp_wma_handle wma, uint8_t vdev_id, WMI_HEOPS_COLOR_SET(dword_he_ops, bcn_params->bss_color); WMI_HEOPS_BSSCOLORDISABLE_SET(dword_he_ops, bcn_params->bss_color_disabled); - WMA_LOGD("vdev: %d, update bss color, HE_OPS: 0x%x", - vdev_id, dword_he_ops); + wma_nofl_debug("vdev: %d, update bss color, HE_OPS: 0x%x", + vdev_id, dword_he_ops); ret = wma_vdev_set_param(wma->wmi_handle, vdev_id, WMI_VDEV_PARAM_BSS_COLOR, dword_he_ops); if (QDF_IS_STATUS_ERROR(ret)) @@ -1876,6 +1850,26 @@ static void wma_set_peer_unicast_cipher(tp_wma_handle wma, wlan_objmgr_peer_release_ref(peer, WLAN_LEGACY_WMA_ID); } +/** + * wma_skip_bip_key_set() - skip the BIP key step or not + * @wma_handle: wma handle + * @iface: txrx node + * @key_cipher: key cipher + * + * if target not support the BIP key cipher, skip the set key command. + * + * Return: true to skip set key to target, otherwise set key to target + */ +static bool +wma_skip_bip_key_set(tp_wma_handle wma_handle, uint32_t key_cipher) +{ + if ((key_cipher == WMI_CIPHER_AES_GMAC) && + !wmi_service_enabled(wma_handle->wmi_handle, + wmi_service_gmac_offload_support)) + return true; + return false; +} + /** * wma_setup_install_key_cmd() - set key parameters * @wma_handle: wma handle @@ -1903,6 +1897,7 @@ static QDF_STATUS wma_setup_install_key_cmd(tp_wma_handle wma_handle, uint32_t pn[4] = {0, 0, 0, 0}; uint8_t peer_id; struct cdp_peer *peer; + bool skip_set_key; if ((key_params->key_type == eSIR_ED_NONE && key_params->key_len) || (key_params->key_type != eSIR_ED_NONE && @@ -2099,8 +2094,11 @@ static QDF_STATUS wma_setup_install_key_cmd(tp_wma_handle wma_handle, /* Set PN check & security type in data path */ cdp_set_pn_check(soc, txrx_vdev, peer, sec_type, pn); - status = wmi_unified_setup_install_key_cmd(wma_handle->wmi_handle, - ¶ms); + skip_set_key = wma_skip_bip_key_set(wma_handle, params.key_cipher); + if (!skip_set_key) + status = wmi_unified_setup_install_key_cmd( + wma_handle->wmi_handle, ¶ms); + if (!key_params->unicast) { /* Its GTK release the wake lock */ WMA_LOGD("Release set key wake lock"); @@ -2331,8 +2329,8 @@ void wma_adjust_ibss_heart_beat_timer(tp_wma_handle wma, if (new_timer_value_sec == cdp_set_ibss_vdev_heart_beat_timer(soc, vdev, new_timer_value_sec)) { - WMA_LOGD("timer value %d stays same, no need to notify target", - new_timer_value_sec); + wma_nofl_debug("timer value %d stays same, no need to notify target", + new_timer_value_sec); return; } @@ -2346,8 +2344,8 @@ void wma_adjust_ibss_heart_beat_timer(tp_wma_handle wma, return; } - WMA_LOGD("Set IBSS link monitor timer: peer_num = %d timer_value = %d", - new_peer_num, new_timer_value_ms); + wma_nofl_debug("Set IBSS link monitor timer: peer_num = %d timer_value = %d", + new_peer_num, new_timer_value_ms); } #endif /* QCA_IBSS_SUPPORT */ @@ -2664,7 +2662,7 @@ static int wmi_unified_probe_rsp_tmpl_send(tp_wma_handle wma, struct ieee80211_frame *wh; struct wmi_probe_resp_params params; - WMA_LOGD(FL("Send probe response template for vdev %d"), vdev_id); + wma_debug("Send probe response template for vdev %d", vdev_id); /* * Make the TSF offset negative so probe response in the same @@ -2706,7 +2704,7 @@ static QDF_STATUS wma_unified_bcn_tmpl_send(tp_wma_handle wma, uint64_t adjusted_tsf_le; struct ieee80211_frame *wh; - WMA_LOGD("Send beacon template for vdev %d", vdev_id); + wma_nofl_debug("Send beacon template for vdev %d", vdev_id); if (bcn_info->p2pIeOffset) { p2p_ie = bcn_info->beacon + bcn_info->p2pIeOffset; @@ -2795,8 +2793,6 @@ static QDF_STATUS wma_store_bcn_tmpl(tp_wma_handle wma, uint8_t vdev_id, SIR_MAX_BEACON_SIZE - sizeof(uint32_t))); return QDF_STATUS_E_INVAL; } - WMA_LOGD("%s: Storing received beacon template buf to local buffer", - __func__); qdf_spin_lock_bh(&bcn->lock); /* @@ -2967,7 +2963,7 @@ void wma_send_probe_rsp_tmpl(tp_wma_handle wma, if (wmi_service_enabled(wma->wmi_handle, wmi_service_beacon_offload)) { - WMA_LOGD("Beacon Offload Enabled Sending Unified command"); + wma_nofl_debug("Beacon Offload Enabled Sending Unified command"); if (wmi_unified_probe_rsp_tmpl_send(wma, vdev_id, probe_rsp_info) < 0) { WMA_LOGE(FL("wmi_unified_probe_rsp_tmpl_send Failed ")); @@ -2995,7 +2991,7 @@ void wma_send_beacon(tp_wma_handle wma, tpSendbeaconParams bcn_info) struct sAniBeaconStruct *beacon; struct vdev_up_params param = {0}; - WMA_LOGD("Beacon update reason %d", bcn_info->reason); + wma_nofl_debug("Beacon update reason %d", bcn_info->reason); beacon = (struct sAniBeaconStruct *) (bcn_info->beacon); vdev = wma_find_vdev_by_addr(wma, beacon->macHdr.sa, &vdev_id); if (!vdev) { @@ -3006,7 +3002,6 @@ void wma_send_beacon(tp_wma_handle wma, tpSendbeaconParams bcn_info) if (wmi_service_enabled(wma->wmi_handle, wmi_service_beacon_offload)) { - WMA_LOGD("Beacon Offload Enabled Sending Unified command"); status = wma_unified_bcn_tmpl_send(wma, vdev_id, bcn_info, 4); if (QDF_IS_STATUS_ERROR(status)) { WMA_LOGE("%s : wmi_unified_bcn_tmpl_send Failed ", @@ -3016,8 +3011,8 @@ void wma_send_beacon(tp_wma_handle wma, tpSendbeaconParams bcn_info) if (bcn_info->p2pIeOffset) { p2p_ie = bcn_info->beacon + bcn_info->p2pIeOffset; - WMA_LOGD("%s: p2pIe is present - vdev_id %hu, p2p_ie = %pK, p2p ie len = %hu", - __func__, vdev_id, p2p_ie, p2p_ie[1]); + wma_debug("p2pIe is present - vdev_id %hu, p2p_ie = %pK, p2p ie len = %hu", + vdev_id, p2p_ie, p2p_ie[1]); if (wma_p2p_go_set_beacon_ie(wma, vdev_id, p2p_ie) < 0) { WMA_LOGE("%s : wmi_unified_bcn_tmpl_send Failed ", @@ -3068,7 +3063,7 @@ void wma_send_beacon(tp_wma_handle wma, tpSendbeaconParams bcn_info) void wma_set_keepalive_req(tp_wma_handle wma, tSirKeepAliveReq *keepalive) { - WMA_LOGD("KEEPALIVE:PacketType:%d", keepalive->packetType); + wma_nofl_debug("KEEPALIVE:PacketType:%d", keepalive->packetType); wma_set_sta_keep_alive(wma, keepalive->sessionId, keepalive->packetType, keepalive->timePeriod, @@ -3187,8 +3182,8 @@ static int wma_process_mgmt_tx_completion(tp_wma_handle wma_handle, return -EINVAL; } - WMA_LOGD("%s: status: %s wmi_desc_id: %d", __func__, - wma_get_status_str(status), desc_id); + wma_debug("status: %s wmi_desc_id: %d", + wma_get_status_str(status), desc_id); pdev = wma_handle->pdev; if (pdev == NULL) { @@ -3220,6 +3215,26 @@ static int wma_process_mgmt_tx_completion(tp_wma_handle wma_handle, return 0; } +/** + * wma_extract_mgmt_offload_event_params() - Extract mgmt event params + * @params: Management offload event params + * @hdr: Management header to extract + * + * Return: None + */ +static void wma_extract_mgmt_offload_event_params( + struct mgmt_offload_event_params *params, + wmi_mgmt_hdr *hdr) +{ + params->tsf_l32 = hdr->tsf_l32; + params->chan_freq = hdr->chan_freq; + params->rate_kbps = hdr->rate_kbps; + params->rssi = hdr->rssi; + params->buf_len = hdr->buf_len; + params->tx_status = hdr->tx_status; + params->tx_retry_cnt = hdr->tx_retry_cnt; +} + /** * wma_mgmt_tx_completion_handler() - wma mgmt Tx completion event handler * @handle: wma handle @@ -3234,7 +3249,7 @@ int wma_mgmt_tx_completion_handler(void *handle, uint8_t *cmpl_event_params, { tp_wma_handle wma_handle = (tp_wma_handle)handle; WMI_MGMT_TX_COMPLETION_EVENTID_param_tlvs *param_buf; - wmi_mgmt_tx_compl_event_fixed_param *cmpl_params; + wmi_mgmt_tx_compl_event_fixed_param *cmpl_params; param_buf = (WMI_MGMT_TX_COMPLETION_EVENTID_param_tlvs *) cmpl_event_params; @@ -3244,8 +3259,21 @@ int wma_mgmt_tx_completion_handler(void *handle, uint8_t *cmpl_event_params, } cmpl_params = param_buf->fixed_param; - wma_process_mgmt_tx_completion(wma_handle, - cmpl_params->desc_id, cmpl_params->status); + if ((ucfg_pkt_capture_get_pktcap_mode() & + PKT_CAPTURE_MODE_MGMT_ONLY) && param_buf->mgmt_hdr) { + struct mgmt_offload_event_params params = {0}; + + wma_extract_mgmt_offload_event_params( + ¶ms, + (wmi_mgmt_hdr *)param_buf->mgmt_hdr); + ucfg_pkt_capture_mgmt_tx_completion(wma_handle->pdev, + cmpl_params->desc_id, + cmpl_params->status, + ¶ms); + } + + wma_process_mgmt_tx_completion(wma_handle, cmpl_params->desc_id, + cmpl_params->status); return 0; } @@ -3305,9 +3333,22 @@ int wma_mgmt_tx_bundle_completion_handler(void *handle, uint8_t *buf, return -EINVAL; } - for (i = 0; i < num_reports; i++) + for (i = 0; i < num_reports; i++) { + if ((ucfg_pkt_capture_get_pktcap_mode() & + PKT_CAPTURE_MODE_MGMT_ONLY) && param_buf->mgmt_hdr) { + struct mgmt_offload_event_params params = {0}; + + wma_extract_mgmt_offload_event_params( + ¶ms, + &((wmi_mgmt_hdr *)param_buf->mgmt_hdr)[i]); + ucfg_pkt_capture_mgmt_tx_completion( + wma_handle->pdev, desc_ids[i], + status[i], ¶ms); + } + wma_process_mgmt_tx_completion(wma_handle, - desc_ids[i], status[i]); + desc_ids[i], status[i]); + } return 0; } @@ -3361,8 +3402,8 @@ void wma_process_update_opmode(tp_wma_handle wma_handle, ch_width = wmi_get_ch_width_from_phy_mode(wma_handle->wmi_handle, fw_phymode); - WMA_LOGD("%s: ch_width: %d, fw phymode: %d", __func__, - ch_width, fw_phymode); + wma_debug("ch_width: %d, fw phymode: %d", + ch_width, fw_phymode); if (ch_width < update_vht_opmode->opMode) { WMA_LOGE("%s: Invalid peer bw update %d, self bw %d", __func__, update_vht_opmode->opMode, @@ -3370,7 +3411,7 @@ void wma_process_update_opmode(tp_wma_handle wma_handle, return; } - WMA_LOGD("%s: opMode = %d", __func__, update_vht_opmode->opMode); + wma_debug("opMode = %d", update_vht_opmode->opMode); wma_set_peer_param(wma_handle, update_vht_opmode->peer_mac, WMI_PEER_CHWIDTH, update_vht_opmode->opMode, update_vht_opmode->smesessionId); @@ -3405,7 +3446,7 @@ void wma_process_update_rx_nss(tp_wma_handle wma_handle, intr->nss = (uint8_t)rx_nss; update_rx_nss->rxNss = (uint32_t)rx_nss; - WMA_LOGD("%s: Rx Nss = %d", __func__, update_rx_nss->rxNss); + wma_debug("Rx Nss = %d", update_rx_nss->rxNss); wma_set_peer_param(wma_handle, update_rx_nss->peer_mac, WMI_PEER_NSS, update_rx_nss->rxNss, @@ -3422,7 +3463,7 @@ void wma_process_update_rx_nss(tp_wma_handle wma_handle, void wma_process_update_membership(tp_wma_handle wma_handle, tUpdateMembership *membership) { - WMA_LOGD("%s: membership = %x ", __func__, membership->membership); + wma_debug("membership = %x ", membership->membership); wma_set_peer_param(wma_handle, membership->peer_mac, WMI_PEER_MEMBERSHIP, membership->membership, @@ -3439,7 +3480,7 @@ void wma_process_update_membership(tp_wma_handle wma_handle, void wma_process_update_userpos(tp_wma_handle wma_handle, tUpdateUserPos *userpos) { - WMA_LOGD("%s: userPos = %x ", __func__, userpos->userPos); + wma_debug("userPos = %x ", userpos->userPos); wma_set_peer_param(wma_handle, userpos->peer_mac, WMI_PEER_USERPOS, userpos->userPos, @@ -3471,8 +3512,8 @@ QDF_STATUS wma_set_cts2self_for_p2p_go(void *wma_handle, return QDF_STATUS_E_FAILURE; } - WMA_LOGD("Successfully Set CTS2SELF for p2p GO %d", - cts2self_for_p2p_go); + wma_nofl_debug("Successfully Set CTS2SELF for p2p GO %d", + cts2self_for_p2p_go); return QDF_STATUS_SUCCESS; } @@ -3749,7 +3790,8 @@ int wma_process_bip(tp_wma_handle wma_handle, if (iface->key.key_cipher == WMI_CIPHER_AES_CMAC) { mmie_size = cds_get_mmie_size(); - } else if (iface->key.key_cipher == WMI_CIPHER_AES_GMAC) { + } else if (iface->key.key_cipher == WMI_CIPHER_AES_GMAC || + iface->key.key_cipher == WMI_CIPHER_BIP_GMAC_256) { mmie_size = cds_get_gmac_mmie_size(); } else { WMA_LOGE(FL("Invalid key cipher %d"), iface->key.key_cipher); @@ -3769,7 +3811,7 @@ int wma_process_bip(tp_wma_handle wma_handle, return -EINVAL; } - WMA_LOGD(FL("key_cipher %d key_id %d"), iface->key.key_cipher, key_id); + wma_debug("key_cipher %d key_id %d", iface->key.key_cipher, key_id); switch (iface->key.key_cipher) { case WMI_CIPHER_AES_CMAC: @@ -3785,17 +3827,18 @@ int wma_process_bip(tp_wma_handle wma_handle, if (cds_is_mmie_valid(iface->key.key, iface->key.key_id[key_id - WMA_IGTK_KEY_INDEX_4].ipn, (uint8_t *) wh, efrm)) { - WMA_LOGD(FL("Protected BC/MC frame MMIE validation successful")); + wma_debug("Protected BC/MC frame MMIE validation successful"); /* Remove MMIE */ qdf_nbuf_trim_tail(wbuf, cds_get_mmie_size()); } else { - WMA_LOGD(FL("BC/MC MIC error or MMIE not present, dropping the frame")); + wma_debug("BC/MC MIC error or MMIE not present, dropping the frame"); return -EINVAL; } } break; case WMI_CIPHER_AES_GMAC: + case WMI_CIPHER_BIP_GMAC_256: if (wmi_service_enabled(wma_handle->wmi_handle, wmi_service_gmac_offload_support)) { /* @@ -3803,18 +3846,18 @@ int wma_process_bip(tp_wma_handle wma_handle, * performed in firmware, host just need to trim the * mmie. */ - WMA_LOGD(FL("Trim GMAC MMIE")); + wma_debug("Trim GMAC MMIE"); qdf_nbuf_trim_tail(wbuf, cds_get_gmac_mmie_size()); } else { if (cds_is_gmac_mmie_valid(iface->key.key, iface->key.key_id[key_id - WMA_IGTK_KEY_INDEX_4].ipn, (uint8_t *) wh, efrm, iface->key.key_length)) { - WMA_LOGD(FL("Protected BC/MC frame GMAC MMIE validation successful")); + wma_debug("Protected BC/MC frame GMAC MMIE validation successful"); /* Remove MMIE */ qdf_nbuf_trim_tail(wbuf, cds_get_gmac_mmie_size()); } else { - WMA_LOGD(FL("BC/MC GMAC MIC error or MMIE not present, dropping the frame")); + wma_debug("BC/MC GMAC MIC error or MMIE not present, dropping the frame"); return -EINVAL; } } @@ -3973,7 +4016,8 @@ wma_get_peer_pmf_status(tp_wma_handle wma, uint8_t *peer_mac) } is_pmf_enabled = mlme_get_peer_pmf_status(peer); wlan_objmgr_peer_release_ref(peer, WLAN_LEGACY_WMA_ID); - WMA_LOGD("get is_pmf_enabled %d for %pM", is_pmf_enabled, peer_mac); + wma_nofl_debug("get is_pmf_enabled %d for %pM", + is_pmf_enabled, peer_mac); return is_pmf_enabled; } @@ -4090,7 +4134,7 @@ int wma_form_rx_packet(qdf_nbuf_t buf, if (!mgmt_rx_params) { limit_prints_invalid_len++; if (limit_prints_invalid_len == RATE_LIMIT) { - WMA_LOGD(FL("mgmt rx params is NULL")); + wma_debug("mgmt rx params is NULL"); limit_prints_invalid_len = 0; } qdf_nbuf_free(buf); @@ -4101,7 +4145,7 @@ int wma_form_rx_packet(qdf_nbuf_t buf, if (cds_is_load_or_unload_in_progress()) { limit_prints_load_unload++; if (limit_prints_load_unload == RATE_LIMIT) { - WMA_LOGD(FL("Load/Unload in progress")); + wma_debug("Load/Unload in progress"); limit_prints_load_unload = 0; } qdf_nbuf_free(buf); @@ -4112,7 +4156,7 @@ int wma_form_rx_packet(qdf_nbuf_t buf, if (cds_is_driver_recovering()) { limit_prints_recovery++; if (limit_prints_recovery == RATE_LIMIT) { - WMA_LOGD(FL("Recovery in progress")); + wma_debug("Recovery in progress"); limit_prints_recovery = 0; } qdf_nbuf_free(buf); @@ -4123,7 +4167,7 @@ int wma_form_rx_packet(qdf_nbuf_t buf, if (cds_is_driver_in_bad_state()) { limit_prints_recovery++; if (limit_prints_recovery == RATE_LIMIT) { - WMA_LOGD(FL("Driver in bad state")); + wma_debug("Driver in bad state"); limit_prints_recovery = 0; } qdf_nbuf_free(buf); @@ -4390,7 +4434,6 @@ static int wma_mgmt_rx_process(void *handle, uint8_t *data, status = mgmt_txrx_rx_handler(psoc, wbuf, mgmt_rx_params); if (status != QDF_STATUS_SUCCESS) { - wma_err_rl("Failed to process mgmt rx frame"); qdf_mem_free(mgmt_rx_params); return -EINVAL; } @@ -4435,6 +4478,8 @@ QDF_STATUS wma_de_register_mgmt_frm_client(void) * wma_register_roaming_callbacks() - Register roaming callbacks * @csr_roam_synch_cb: CSR roam synch callback routine pointer * @pe_roam_synch_cb: PE roam synch callback routine pointer + * @csr_roam_auth_event_handle_cb: CSR callback routine pointer + * @csr_roam_pmkid_req_cb: CSR roam pmkid callback routine pointer * * Register the SME and PE callback routines with WMA for * handling roaming @@ -4446,10 +4491,21 @@ QDF_STATUS wma_register_roaming_callbacks( roam_offload_synch_ind *roam_synch_data, tpSirBssDescription bss_desc_ptr, enum sir_roam_op_code reason), + QDF_STATUS (*csr_roam_auth_event_handle_cb)(tpAniSirGlobal mac, + uint8_t vdev_id, + struct qdf_mac_addr bssid), + QDF_STATUS (*pe_roam_synch_cb)(tpAniSirGlobal mac, roam_offload_synch_ind *roam_synch_data, tpSirBssDescription bss_desc_ptr, - enum sir_roam_op_code reason)) + enum sir_roam_op_code reason), + QDF_STATUS (*pe_disconnect_cb) (tpAniSirGlobal mac, + uint8_t vdev_id, + uint8_t *deauth_disassoc_frame, + uint16_t deauth_disassoc_frame_len, + uint16_t reason_code), + QDF_STATUS (*csr_roam_pmkid_req_cb)(uint8_t vdev_id, + struct roam_pmkid_req_event *bss_list)) { tp_wma_handle wma = cds_get_context(QDF_MODULE_ID_WMA); @@ -4459,8 +4515,12 @@ QDF_STATUS wma_register_roaming_callbacks( return QDF_STATUS_E_FAILURE; } wma->csr_roam_synch_cb = csr_roam_synch_cb; + wma->csr_roam_auth_event_handle_cb = csr_roam_auth_event_handle_cb; wma->pe_roam_synch_cb = pe_roam_synch_cb; - WMA_LOGD("Registered roam synch callbacks with WMA successfully"); + wma->pe_disconnect_cb = pe_disconnect_cb; + wma_debug("Registered roam synch callbacks with WMA successfully"); + + wma->csr_roam_pmkid_req_cb = csr_roam_pmkid_req_cb; return QDF_STATUS_SUCCESS; } #endif diff --git a/drivers/staging/qcacld-3.0/core/wma/src/wma_power.c b/drivers/staging/qcacld-3.0/core/wma/src/wma_power.c index a5f3b71ac1e1..0ff622d4ecf2 100644 --- a/drivers/staging/qcacld-3.0/core/wma/src/wma_power.c +++ b/drivers/staging/qcacld-3.0/core/wma/src/wma_power.c @@ -735,17 +735,17 @@ static enum powersave_qpower_mode wma_get_qpower_config(tp_wma_handle wma) switch (wma->powersave_mode) { case PS_QPOWER_NODEEPSLEEP: case PS_QPOWER_DEEPSLEEP: - WMA_LOGI("QPOWER is enabled in power save mode %d", - wma->powersave_mode); + WMA_LOGD("QPOWER is enabled in power save mode %d", + wma->powersave_mode); return QPOWER_ENABLED; case PS_DUTY_CYCLING_QPOWER: - WMA_LOGI("DUTY cycling QPOWER is enabled in power save mode %d", - wma->powersave_mode); + WMA_LOGD("DUTY cycling QPOWER is enabled in power save mode %d", + wma->powersave_mode); return QPOWER_DUTY_CYCLING; default: - WMA_LOGI("QPOWER is disabled in power save mode %d", - wma->powersave_mode); + WMA_LOGD("QPOWER is disabled in power save mode %d", + wma->powersave_mode); return QPOWER_DISABLED; } } @@ -757,13 +757,27 @@ static enum powersave_qpower_mode wma_get_qpower_config(tp_wma_handle wma) * * Return: none */ -void wma_enable_sta_ps_mode(tp_wma_handle wma, tpEnablePsParams ps_req) +void wma_enable_sta_ps_mode(tpEnablePsParams ps_req) { uint32_t vdev_id = ps_req->sessionid; QDF_STATUS ret; - enum powersave_qpower_mode qpower_config = wma_get_qpower_config(wma); - struct wma_txrx_node *iface = &wma->interfaces[vdev_id]; + enum powersave_qpower_mode qpower_config; + struct wma_txrx_node *iface; + t_wma_handle *wma_handle; + + wma_handle = cds_get_context(QDF_MODULE_ID_WMA); + if (!wma_handle) { + wma_err("wma handle is null"); + return; + } + + iface = &wma_handle->interfaces[vdev_id]; + if (!iface) { + WMA_LOGE("%s: vdev is NULL for vdev_%d", __func__, vdev_id); + return; + } + qpower_config = wma_get_qpower_config(wma_handle); if (!iface->handle) { WMA_LOGE("vdev id %d is not active", vdev_id); return; @@ -774,14 +788,14 @@ void wma_enable_sta_ps_mode(tp_wma_handle wma, tpEnablePsParams ps_req) WMA_LOGD("Qpower is disabled"); } WMA_LOGD("Enable Sta Mode Ps vdevId %d", vdev_id); - ret = wma_unified_set_sta_ps_param(wma->wmi_handle, vdev_id, + ret = wma_unified_set_sta_ps_param(wma_handle->wmi_handle, vdev_id, WMI_STA_PS_PARAM_UAPSD, 0); if (QDF_IS_STATUS_ERROR(ret)) { WMA_LOGE("Set Uapsd param 0 Failed vdevId %d", vdev_id); return; } - ret = wma_set_force_sleep(wma, vdev_id, false, + ret = wma_set_force_sleep(wma_handle, vdev_id, false, qpower_config, true); if (QDF_IS_STATUS_ERROR(ret)) { WMA_LOGE("Enable Sta Ps Failed vdevId %d", vdev_id); @@ -794,7 +808,7 @@ void wma_enable_sta_ps_mode(tp_wma_handle wma, tpEnablePsParams ps_req) if (uapsd_val != iface->uapsd_cached_val) { WMA_LOGD("Enable Uapsd vdevId %d Mask %d", vdev_id, uapsd_val); - ret = wma_unified_set_sta_ps_param(wma->wmi_handle, + ret = wma_unified_set_sta_ps_param(wma_handle->wmi_handle, vdev_id, WMI_STA_PS_PARAM_UAPSD, uapsd_val); @@ -815,7 +829,7 @@ void wma_enable_sta_ps_mode(tp_wma_handle wma, tpEnablePsParams ps_req) WMA_LOGD("Qpower is disabled"); } WMA_LOGD("Enable Forced Sleep vdevId %d", vdev_id); - ret = wma_set_force_sleep(wma, vdev_id, true, + ret = wma_set_force_sleep(wma_handle, vdev_id, true, qpower_config, true); if (QDF_IS_STATUS_ERROR(ret)) { @@ -825,14 +839,14 @@ void wma_enable_sta_ps_mode(tp_wma_handle wma, tpEnablePsParams ps_req) } } - if (wma->ito_repeat_count) { + if (wma_handle->ito_repeat_count) { WMA_LOGI("Set ITO count to %d for vdevId %d", - wma->ito_repeat_count, vdev_id); + wma_handle->ito_repeat_count, vdev_id); - ret = wma_unified_set_sta_ps_param(wma->wmi_handle, + ret = wma_unified_set_sta_ps_param(wma_handle->wmi_handle, vdev_id, WMI_STA_PS_PARAM_MAX_RESET_ITO_COUNT_ON_TIM_NO_TXRX, - wma->ito_repeat_count); + wma_handle->ito_repeat_count); if (QDF_IS_STATUS_ERROR(ret)) { WMA_LOGE("Set ITO count failed vdevId %d Error %d", vdev_id, ret); @@ -851,16 +865,25 @@ void wma_enable_sta_ps_mode(tp_wma_handle wma, tpEnablePsParams ps_req) * * Return: none */ -void wma_disable_sta_ps_mode(tp_wma_handle wma, tpDisablePsParams ps_req) +void wma_disable_sta_ps_mode(tpDisablePsParams ps_req) { QDF_STATUS ret; uint32_t vdev_id = ps_req->sessionid; - struct wma_txrx_node *iface = &wma->interfaces[vdev_id]; + struct wma_txrx_node *iface; + t_wma_handle *wma_handle; + + wma_handle = cds_get_context(QDF_MODULE_ID_WMA); + if (!wma_handle) { + wma_err("wma handle is null"); + return; + } + + iface = &wma_handle->interfaces[vdev_id]; WMA_LOGD("Disable Sta Mode Ps vdevId %d", vdev_id); /* Disable Sta Mode Power save */ - ret = wmi_unified_set_sta_ps(wma->wmi_handle, vdev_id, false); + ret = wmi_unified_set_sta_ps(wma_handle->wmi_handle, vdev_id, false); if (QDF_IS_STATUS_ERROR(ret)) { WMA_LOGE("Disable Sta Mode Ps Failed vdevId %d", vdev_id); return; @@ -870,7 +893,7 @@ void wma_disable_sta_ps_mode(tp_wma_handle wma, tpDisablePsParams ps_req) /* Disable UAPSD incase if additional Req came */ if (eSIR_ADDON_DISABLE_UAPSD == ps_req->psSetting) { WMA_LOGD("Disable Uapsd vdevId %d", vdev_id); - ret = wma_unified_set_sta_ps_param(wma->wmi_handle, vdev_id, + ret = wma_unified_set_sta_ps_param(wma_handle->wmi_handle, vdev_id, WMI_STA_PS_PARAM_UAPSD, 0); if (QDF_IS_STATUS_ERROR(ret)) { WMA_LOGE("Disable Uapsd Failed vdevId %d", vdev_id); diff --git a/drivers/staging/qcacld-3.0/core/wma/src/wma_scan_roam.c b/drivers/staging/qcacld-3.0/core/wma/src/wma_scan_roam.c index 1043c85ccee3..b84e61b2a2bc 100644 --- a/drivers/staging/qcacld-3.0/core/wma/src/wma_scan_roam.c +++ b/drivers/staging/qcacld-3.0/core/wma/src/wma_scan_roam.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2013-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2013-2020 The Linux Foundation. All rights reserved. * * Permission to use, copy, modify, and/or distribute this software for * any purpose with or without fee is hereby granted, provided that the @@ -105,6 +105,61 @@ enum extscan_report_events_type { #define WMA_EXTSCAN_MAX_HOTLIST_ENTRIES 10 #endif +static inline wmi_host_channel_width +wma_map_phy_ch_bw_to_wmi_channel_width(enum phy_ch_width ch_width) +{ + switch (ch_width) { + case CH_WIDTH_20MHZ: + return WMI_HOST_CHAN_WIDTH_20; + case CH_WIDTH_40MHZ: + return WMI_HOST_CHAN_WIDTH_40; + case CH_WIDTH_80MHZ: + return WMI_HOST_CHAN_WIDTH_80; + case CH_WIDTH_160MHZ: + return WMI_HOST_CHAN_WIDTH_160; + case CH_WIDTH_5MHZ: + return WMI_HOST_CHAN_WIDTH_5; + case CH_WIDTH_10MHZ: + return WMI_HOST_CHAN_WIDTH_10; + default: + return WMI_HOST_CHAN_WIDTH_20; + } +} + +#define WMA_MAX_CHAN_INFO_LOG 192 + +/** + * wma_scan_chanlist_dump() - Dump scan channel list info + * @chan_list: scan channel list + * + * Return: void + */ +static void wma_scan_chanlist_dump(tSirUpdateChanList *chan_list) +{ + uint32_t i; + uint8_t info[WMA_MAX_CHAN_INFO_LOG]; + uint32_t len = 0; + tSirUpdateChanParam *chan; + int ret; + + wma_debug("Total chan %d", chan_list->numChan); + for (i = 0; i < chan_list->numChan; i++) { + chan = &chan_list->chanParam[i]; + ret = qdf_scnprintf(info + len, sizeof(info) - len, + " %d[%d][%d]", chan->chanId, chan->pwr, + chan->dfsSet); + if (ret <= 0) + break; + len += ret; + if (len >= (sizeof(info) - 20)) { + wma_nofl_debug("Chan[TXPwr][DFS]:%s", info); + len = 0; + } + } + if (len) + wma_nofl_debug("Chan[TXPwr][DFS]:%s", info); +} + /** * wma_update_channel_list() - update channel list * @handle: wma handle @@ -122,6 +177,7 @@ QDF_STATUS wma_update_channel_list(WMA_HANDLE handle, int i; struct scan_chan_list_params scan_ch_param = {0}; wmi_channel_param *tchan_info; + struct ch_params ch_params = {0}; scan_ch_param.chan_info = qdf_mem_malloc(sizeof(wmi_channel) * chan_list->numChan); @@ -134,9 +190,11 @@ QDF_STATUS wma_update_channel_list(WMA_HANDLE handle, WMA_LOGD("no of channels = %d", chan_list->numChan); tchan_info = scan_ch_param.chan_info; scan_ch_param.num_scan_chans = chan_list->numChan; + scan_ch_param.max_bw_support_present = true; wma_handle->saved_chan.num_channels = chan_list->numChan; WMA_LOGD("ht %d, vht %d, vht_24 %d", chan_list->ht_en, chan_list->vht_en, chan_list->vht_24_en); + wma_scan_chanlist_dump(chan_list); for (i = 0; i < chan_list->numChan; ++i) { tchan_info->mhz = @@ -147,12 +205,6 @@ QDF_STATUS wma_update_channel_list(WMA_HANDLE handle, wma_handle->saved_chan.channel_list[i] = chan_list->chanParam[i].chanId; - WMA_LOGD("chan[%d] = freq:%u chan:%d DFS:%d tx power:%d", - i, tchan_info->mhz, - chan_list->chanParam[i].chanId, - chan_list->chanParam[i].dfsSet, - chan_list->chanParam[i].pwr); - if (chan_list->chanParam[i].dfsSet) { WMI_SET_CHANNEL_FLAG(tchan_info, WMI_CHAN_FLAG_PASSIVE); @@ -188,6 +240,15 @@ QDF_STATUS wma_update_channel_list(WMA_HANDLE handle, WMI_SET_CHANNEL_REG_POWER(tchan_info, chan_list->chanParam[i].pwr); + + ch_params.ch_width = CH_WIDTH_160MHZ; + wlan_reg_set_channel_params(wma_handle->pdev, + chan_list->chanParam[i].chanId, 0, + &ch_params); + WMI_SET_CHANNEL_MAX_BANDWIDTH(tchan_info, + wma_map_phy_ch_bw_to_wmi_channel_width( + ch_params.ch_width)); + tchan_info++; } @@ -251,10 +312,8 @@ static void wma_roam_scan_fill_fils_params(tp_wma_handle wma_handle, { struct roam_fils_params *dst_fils_params, *src_fils_params; - if (!params || !roam_req || !roam_req->is_fils_connection) { - WMA_LOGD("wma_roam_scan_fill_fils_params- NULL"); + if (!params || !roam_req || !roam_req->is_fils_connection) return; - } src_fils_params = &roam_req->roam_fils_params; dst_fils_params = ¶ms->roam_fils_params; @@ -274,6 +333,10 @@ static void wma_roam_scan_fill_fils_params(tp_wma_handle wma_handle, qdf_mem_copy(dst_fils_params->rik, src_fils_params->rik, dst_fils_params->rik_length); + dst_fils_params->fils_ft_len = src_fils_params->fils_ft_len; + qdf_mem_copy(dst_fils_params->fils_ft, src_fils_params->fils_ft, + dst_fils_params->fils_ft_len); + dst_fils_params->realm_len = src_fils_params->realm_len; qdf_mem_copy(dst_fils_params->realm, src_fils_params->realm, dst_fils_params->realm_len); @@ -287,9 +350,77 @@ static inline void wma_roam_scan_fill_fils_params( { } #endif +/** + * wma_roam_scan_offload_set_params() - Set roam scan offload params + * @wma_handle: pointer to wma context + * @params: pointer to roam scan offload params + * @roam_req: roam request param + * + * Get roam scan offload parameters from roam req and prepare to fill + * WMI_ROAM_SCAN_MODE TLV + * + * Return: None + */ +#ifdef WLAN_FEATURE_ROAM_OFFLOAD +static void wma_roam_scan_offload_set_params( + tp_wma_handle wma_handle, + struct roam_offload_scan_params *params, + tSirRoamOffloadScanReq *roam_req) +{ + params->auth_mode = WMI_AUTH_NONE; + if (!roam_req) + return; + params->auth_mode = e_csr_auth_type_to_rsn_authmode + (roam_req->ConnectedNetwork.authentication, + roam_req->ConnectedNetwork.encryption); + + params->roam_offload_enabled = roam_req->RoamOffloadEnabled; + params->roam_offload_params.ho_delay_for_rx = + roam_req->ho_delay_for_rx; + params->roam_offload_params.roam_preauth_retry_count = + roam_req->roam_preauth_retry_count; + params->roam_offload_params.roam_preauth_no_ack_timeout = + roam_req->roam_preauth_no_ack_timeout; + params->prefer_5ghz = roam_req->Prefer5GHz; + params->roam_rssi_cat_gap = roam_req->RoamRssiCatGap; + params->select_5ghz_margin = roam_req->Select5GHzMargin; + params->reassoc_failure_timeout = + roam_req->ReassocFailureTimeout; + params->rokh_id_length = roam_req->R0KH_ID_Length; + qdf_mem_copy(params->rokh_id, roam_req->R0KH_ID, + WMI_ROAM_R0KH_ID_MAX_LEN); + qdf_mem_copy(params->krk, roam_req->KRK, WMI_KRK_KEY_LEN); + qdf_mem_copy(params->btk, roam_req->BTK, WMI_BTK_KEY_LEN); + qdf_mem_copy(params->psk_pmk, roam_req->PSK_PMK, + roam_req->pmk_len); + params->pmk_len = roam_req->pmk_len; + params->roam_key_mgmt_offload_enabled = + roam_req->RoamKeyMgmtOffloadEnabled; + wma_roam_scan_fill_self_caps(wma_handle, + ¶ms->roam_offload_params, roam_req); + params->is_adaptive_11r = roam_req->is_adaptive_11r_connection; + params->fw_okc = roam_req->pmkid_modes.fw_okc; + params->fw_pmksa_cache = roam_req->pmkid_modes.fw_pmksa_cache; + params->is_sae_same_pmk = roam_req->is_sae_single_pmk; + wma_debug("qos_caps %d, qos_enabled %d, ho_delay_for_rx %d, roam_scan_mode %d roam_preauth: retrycount %d, no_ack_timeout %d SAE Single PMK:%d", + params->roam_offload_params.qos_caps, + params->roam_offload_params.qos_enabled, + params->roam_offload_params.ho_delay_for_rx, params->mode, + params->roam_offload_params.roam_preauth_retry_count, + params->roam_offload_params.roam_preauth_no_ack_timeout, + params->is_sae_same_pmk); +} +#else +static void wma_roam_scan_offload_set_params( + tp_wma_handle wma_handle, + struct roam_offload_scan_params *params, + tSirRoamOffloadScanReq *roam_req) +{} +#endif + /** * wma_roam_scan_offload_mode() - send roam scan mode request to fw - * @wma_handle: wma handle + * @wma_handle: pointer to wma context * @scan_cmd_fp: start scan command ptr * @roam_req: roam request param * @mode: mode @@ -314,49 +445,13 @@ QDF_STATUS wma_roam_scan_offload_mode(tp_wma_handle wma_handle, WMA_LOGE("%s: Failed to allocate scan params", __func__); return QDF_STATUS_E_NOMEM; } -#ifdef WLAN_FEATURE_ROAM_OFFLOAD - params->auth_mode = WMI_AUTH_NONE; - if (roam_req) - params->auth_mode = e_csr_auth_type_to_rsn_authmode - (roam_req->ConnectedNetwork.authentication, - roam_req->ConnectedNetwork.encryption); - WMA_LOGD("%s : auth mode = %d", __func__, params->auth_mode); -#endif /* WLAN_FEATURE_ROAM_OFFLOAD */ params->is_roam_req_valid = 0; params->mode = mode; params->vdev_id = vdev_id; if (roam_req) { params->is_roam_req_valid = 1; -#ifdef WLAN_FEATURE_ROAM_OFFLOAD - params->roam_offload_enabled = roam_req->RoamOffloadEnabled; - params->roam_offload_params.ho_delay_for_rx = - roam_req->ho_delay_for_rx; - params->roam_offload_params.roam_preauth_retry_count = - roam_req->roam_preauth_retry_count; - params->roam_offload_params.roam_preauth_no_ack_timeout = - roam_req->roam_preauth_no_ack_timeout; - params->prefer_5ghz = roam_req->Prefer5GHz; - params->roam_rssi_cat_gap = roam_req->RoamRssiCatGap; - params->select_5ghz_margin = roam_req->Select5GHzMargin; - params->reassoc_failure_timeout = - roam_req->ReassocFailureTimeout; - params->rokh_id_length = roam_req->R0KH_ID_Length; - qdf_mem_copy(params->rokh_id, roam_req->R0KH_ID, - WMI_ROAM_R0KH_ID_MAX_LEN); - qdf_mem_copy(params->krk, roam_req->KRK, WMI_KRK_KEY_LEN); - qdf_mem_copy(params->btk, roam_req->BTK, WMI_BTK_KEY_LEN); - qdf_mem_copy(params->psk_pmk, roam_req->PSK_PMK, - WMI_ROAM_SCAN_PSK_SIZE); - params->pmk_len = roam_req->pmk_len; - params->roam_key_mgmt_offload_enabled = - roam_req->RoamKeyMgmtOffloadEnabled; - wma_roam_scan_fill_self_caps(wma_handle, - ¶ms->roam_offload_params, roam_req); - params->fw_okc = roam_req->pmkid_modes.fw_okc; - params->fw_pmksa_cache = roam_req->pmkid_modes.fw_pmksa_cache; - params->rct_validity_timer = roam_req->rct_validity_timer; -#endif + params->min_delay_btw_roam_scans = roam_req->min_delay_btw_roam_scans; params->roam_trigger_reason_bitmask = @@ -378,19 +473,12 @@ QDF_STATUS wma_roam_scan_offload_mode(tp_wma_handle wma_handle, wma_roam_scan_fill_fils_params(wma_handle, params, roam_req); } + wma_debug("min_delay_btw_roam_scans %d, roam_tri_reason_bitmask %d", + params->min_delay_btw_roam_scans, + params->roam_trigger_reason_bitmask); - WMA_LOGD(FL("qos_caps: %d, qos_enabled: %d, ho_delay_for_rx: %d, roam_scan_mode: %d"), - params->roam_offload_params.qos_caps, - params->roam_offload_params.qos_enabled, - params->roam_offload_params.ho_delay_for_rx, params->mode); - - WMA_LOGD(FL("min_delay_btw_roam_scans:%d, roam_tri_reason_bitmask:%d"), - params->min_delay_btw_roam_scans, - params->roam_trigger_reason_bitmask); - - WMA_LOGD(FL("roam_preauth_retry_count: %d, roam_preauth_no_ack_timeout: %d"), - params->roam_offload_params.roam_preauth_retry_count, - params->roam_offload_params.roam_preauth_no_ack_timeout); + wma_roam_scan_offload_set_params(wma_handle, params, + roam_req); status = wmi_unified_roam_scan_offload_mode_cmd(wma_handle->wmi_handle, scan_cmd_fp, params); @@ -399,7 +487,6 @@ QDF_STATUS wma_roam_scan_offload_mode(tp_wma_handle wma_handle, if (QDF_IS_STATUS_ERROR(status)) return status; - WMA_LOGD("%s: WMA --> WMI_ROAM_SCAN_MODE", __func__); return status; } @@ -486,9 +573,6 @@ QDF_STATUS wma_roam_scan_offload_rssi_thresh(tp_wma_handle wma_handle, params.good_rssi_threshold = (good_rssi_threshold - WMA_NOISE_FLOOR_DBM_DEFAULT) & 0x000000ff; - WMA_LOGD("WMA --> good_rssi_threshold=%d", - params.good_rssi_threshold); - if (roam_req->early_stop_scan_enable) { params.roam_earlystop_thres_min = roam_req->early_stop_scan_min_threshold - @@ -503,11 +587,11 @@ QDF_STATUS wma_roam_scan_offload_rssi_thresh(tp_wma_handle wma_handle, params.rssi_thresh_offset_5g = roam_req->rssi_thresh_offset_5g; - WMA_LOGD("early_stop_thresholds en=%d, min=%d, max=%d", - roam_req->early_stop_scan_enable, - params.roam_earlystop_thres_min, - params.roam_earlystop_thres_max); - WMA_LOGD("rssi_thresh_offset_5g = %d", params.rssi_thresh_offset_5g); + wma_debug("good_rssi_threshold %d, early_stop_thresholds en=%d, min=%d, max=%d roam_scan_rssi_thresh=%d, roam_rssi_thresh_diff=%d", + params.good_rssi_threshold, roam_req->early_stop_scan_enable, + params.roam_earlystop_thres_min, + params.roam_earlystop_thres_max, rssi_thresh, + rssi_thresh_diff); status = wmi_unified_roam_scan_offload_rssi_thresh_cmd( wma_handle->wmi_handle, ¶ms); @@ -516,43 +600,54 @@ QDF_STATUS wma_roam_scan_offload_rssi_thresh(tp_wma_handle wma_handle, return status; } - WMA_LOGD(FL("roam_scan_rssi_thresh=%d, roam_rssi_thresh_diff=%d"), - rssi_thresh, rssi_thresh_diff); - WMA_LOGD( - FL("hirssi_scan max_count=%d, delta=%d, hirssi_upper_bound=%d"), - hirssi_scan_max_count, hirssi_scan_delta, hirssi_upper_bound); - WMA_LOGD( - FL("dense_rssi_thresh_offset=%d, dense_min_aps_cnt=%d, traffic_threshold=%d initial_dense_status=%d"), - roam_params->dense_rssi_thresh_offset, - roam_params->dense_min_aps_cnt, - roam_params->traffic_threshold, - roam_params->initial_dense_status); - WMA_LOGD(FL("BG Scan Bad RSSI:%d, bitmap:0x%x Offset for 2G to 5G Roam:%d"), - roam_params->bg_scan_bad_rssi_thresh, - roam_params->bg_scan_client_bitmap, - roam_params->roam_bad_rssi_thresh_offset_2g); + wma_debug("hirssi max cnt %d, delta %d, hirssi upper bound %d dense rssi thresh offset %d, dense min aps cnt %d, traffic_threshold %d dense_status=%d", + hirssi_scan_max_count, hirssi_scan_delta, hirssi_upper_bound, + roam_params->dense_rssi_thresh_offset, + roam_params->dense_min_aps_cnt, + roam_params->traffic_threshold, + roam_params->initial_dense_status); + wma_debug("BG Scan Bad RSSI:%d, bitmap:0x%x Offset for 2G to 5G Roam:%d", + roam_params->bg_scan_bad_rssi_thresh, + roam_params->bg_scan_client_bitmap, + roam_params->roam_bad_rssi_thresh_offset_2g); return status; } /** * wma_roam_scan_offload_scan_period() - set roam offload scan period * @wma_handle: wma handle - * @scan_period: scan period - * @scan_age: scan age - * @vdev_id: vdev id + * @roam_req: Pointer to roam_offload_scan_req * * Send WMI_ROAM_SCAN_PERIOD parameters to fw. * * Return: QDF status */ -QDF_STATUS wma_roam_scan_offload_scan_period(tp_wma_handle wma_handle, - uint32_t scan_period, - uint32_t scan_age, - uint32_t vdev_id, - uint32_t full_roam_scan_period) +QDF_STATUS +wma_roam_scan_offload_scan_period(tp_wma_handle wma_handle, + tSirRoamOffloadScanReq *roam_req) { + uint8_t vdev_id; + struct roam_scan_period_params scan_period_params; + + vdev_id = roam_req->sessionId; + if (!wma_is_vdev_valid(vdev_id)) { + WMA_LOGE("%s: Invalid vdev id:%d", __func__, vdev_id); + return QDF_STATUS_E_FAILURE; + } + + scan_period_params.vdev_id = vdev_id; + scan_period_params.scan_period = roam_req->EmptyRefreshScanPeriod; + scan_period_params.scan_age = (3 * roam_req->EmptyRefreshScanPeriod); + scan_period_params.full_scan_period = roam_req->full_roam_scan_period; + scan_period_params.roam_scan_inactivity_time = + roam_req->roam_scan_inactivity_time; + scan_period_params.roam_inactive_data_packet_count = + roam_req->roam_inactive_data_packet_count; + scan_period_params.roam_scan_period_after_inactivity = + roam_req->roam_scan_period_after_inactivity; + return wmi_unified_roam_scan_offload_scan_period(wma_handle->wmi_handle, - scan_period, scan_age, vdev_id, full_roam_scan_period); + &scan_period_params); } /** @@ -604,23 +699,36 @@ QDF_STATUS wma_roam_scan_offload_chan_list(tp_wma_handle wma_handle, { QDF_STATUS status; int i; - uint32_t *chan_list_mhz; - - if (chan_count == 0) { - WMA_LOGD("%s : invalid number of channels %d", __func__, - chan_count); - return QDF_STATUS_E_EMPTY; - } - chan_list_mhz = qdf_mem_malloc(chan_count * sizeof(*chan_list_mhz)); - if (chan_list_mhz == NULL) { - WMA_LOGE("%s : Memory allocation failed", __func__); - return QDF_STATUS_E_NOMEM; + uint32_t *chan_list_mhz = NULL, buf_len = 0, len = 0; + uint8_t *chan_buff = NULL; + + if (chan_count) { + chan_list_mhz = + qdf_mem_malloc(chan_count * sizeof(*chan_list_mhz)); + if (!chan_list_mhz) { + WMA_LOGE("%s : Memory allocation failed", __func__); + return QDF_STATUS_E_NOMEM; + } + /* + * Buffer of (num channl * 5) + 1 to consider the 4 char freq + * and 1 space after it for each channel and 1 to end the string + * with NULL. + */ + buf_len = (chan_count * 5) + 1; + chan_buff = qdf_mem_malloc(buf_len); } for (i = 0; ((i < chan_count) && (i < SIR_ROAM_MAX_CHANNELS)); i++) { chan_list_mhz[i] = cds_chan_to_freq(chan_list[i]); - WMA_LOGD("%d,", chan_list_mhz[i]); + if (chan_buff) + len += qdf_scnprintf(chan_buff + len, buf_len - len, + " %d", chan_list_mhz[i]); + } + + if (chan_buff) { + wma_debug("Freq list[%d]:%s", chan_count, chan_buff); + qdf_mem_free(chan_buff); } status = wmi_unified_roam_scan_offload_chan_list_cmd( @@ -695,10 +803,22 @@ A_UINT32 e_csr_auth_type_to_rsn_authmode(eCsrAuthType authtype, return WMI_AUTH_RSNA_FILS_SHA256; case eCSR_AUTH_TYPE_FILS_SHA384: return WMI_AUTH_RSNA_FILS_SHA384; + case eCSR_AUTH_TYPE_FT_FILS_SHA256: + return WMI_AUTH_FT_RSNA_FILS_SHA256; + case eCSR_AUTH_TYPE_FT_FILS_SHA384: + return WMI_AUTH_FT_RSNA_FILS_SHA384; case eCSR_AUTH_TYPE_SUITEB_EAP_SHA256: return WMI_AUTH_RSNA_SUITE_B_8021X_SHA256; case eCSR_AUTH_TYPE_SUITEB_EAP_SHA384: return WMI_AUTH_RSNA_SUITE_B_8021X_SHA384; + case eCSR_AUTH_TYPE_OWE: + return WMI_AUTH_WPA3_OWE; + case eCSR_AUTH_TYPE_SAE: + return WMI_AUTH_WPA3_SAE; + case eCSR_AUTH_TYPE_FT_SAE: + return WMI_AUTH_FT_RSNA_SAE; + case eCSR_AUTH_TYPE_FT_SUITEB_EAP_SHA384: + return WMI_AUTH_FT_RSNA_SUITE_B_8021X_SHA384; default: return WMI_AUTH_NONE; } @@ -741,6 +861,36 @@ A_UINT32 e_csr_encryption_type_to_rsn_cipherset(eCsrEncryptionType encr) } } +/** + * wma_convert_gp_mgmt_cipher_to_target_cipher_type() - map csr ani group mgmt + * enc type to RSN cipher + * @encr: CSR Encryption + * + * Map CSR's group management cipher type into RSN cipher types used by firmware + * + * Return: WMI RSN cipher + */ +static uint32_t +wma_convert_gp_mgmt_cipher_to_target_cipher_type(tAniEdType cipher_type) +{ + switch (cipher_type) { + /* BIP-CMAC-128 (00:0f:ac: 0x06) */ + case eSIR_ED_AES_128_CMAC: + return WMI_CIPHER_AES_CMAC; + + /* BIP-GMAC-128 (00:0f:ac: 0x0b) */ + case eSIR_ED_AES_GMAC_128: + return WMI_CIPHER_AES_GMAC; + + /* BIP-GMAC-256(00:0f:ac: 0x0c)*/ + case eSIR_ED_AES_GMAC_256: + return WMI_CIPHER_BIP_GMAC_256; + case eSIR_ED_NONE: + default: + return WMI_CIPHER_NONE; + } +} + #ifdef WLAN_FEATURE_ROAM_OFFLOAD /** * wma_roam_scan_get_cckm_mode() - Get the CCKM auth mode @@ -785,41 +935,47 @@ static void wma_roam_scan_fill_ap_profile(tSirRoamOffloadScanReq *roam_req, profile->rsn_mcastcipherset = WMI_CIPHER_NONE; profile->rsn_mcastmgmtcipherset = WMI_CIPHER_NONE; profile->rssi_threshold = WMA_ROAM_RSSI_DIFF_DEFAULT; - } else { - profile->ssid.length = - roam_req->ConnectedNetwork.ssId.length; - qdf_mem_copy(profile->ssid.mac_ssid, - roam_req->ConnectedNetwork.ssId.ssId, - profile->ssid.length); + + return; + } + + profile->ssid.length = roam_req->ConnectedNetwork.ssId.length; + qdf_mem_copy(profile->ssid.mac_ssid, + roam_req->ConnectedNetwork.ssId.ssId, + profile->ssid.length); + profile->rsn_authmode = + e_csr_auth_type_to_rsn_authmode( + roam_req->ConnectedNetwork.authentication, + roam_req->ConnectedNetwork.encryption); + rsn_authmode = profile->rsn_authmode; + + if (rsn_authmode == WMI_AUTH_CCKM_WPA || + rsn_authmode == WMI_AUTH_CCKM_RSNA) profile->rsn_authmode = - e_csr_auth_type_to_rsn_authmode( - roam_req->ConnectedNetwork.authentication, + wma_roam_scan_get_cckm_mode(roam_req, rsn_authmode); + + /* Pairwise cipher suite */ + profile->rsn_ucastcipherset = + e_csr_encryption_type_to_rsn_cipherset( roam_req->ConnectedNetwork.encryption); - rsn_authmode = profile->rsn_authmode; - - if ((rsn_authmode == WMI_AUTH_CCKM_WPA) || - (rsn_authmode == WMI_AUTH_CCKM_RSNA)) - profile->rsn_authmode = - wma_roam_scan_get_cckm_mode( - roam_req, rsn_authmode); - profile->rsn_ucastcipherset = - e_csr_encryption_type_to_rsn_cipherset( - roam_req->ConnectedNetwork.encryption); - profile->rsn_mcastcipherset = - e_csr_encryption_type_to_rsn_cipherset( - roam_req->ConnectedNetwork.mcencryption); - profile->rsn_mcastmgmtcipherset = - profile->rsn_mcastcipherset; - profile->rssi_threshold = roam_req->RoamRssiDiff; - if (roam_req->rssi_abs_thresh) - profile->rssi_abs_thresh = - roam_req->rssi_abs_thresh - - WMA_NOISE_FLOOR_DBM_DEFAULT; + + /* Group cipher suite */ + profile->rsn_mcastcipherset = + e_csr_encryption_type_to_rsn_cipherset( + roam_req->ConnectedNetwork.mcencryption); + + /* Group management cipher suite */ + profile->rsn_mcastmgmtcipherset = + wma_convert_gp_mgmt_cipher_to_target_cipher_type( + roam_req->ConnectedNetwork.gp_mgmt_cipher_suite); + + profile->rssi_threshold = roam_req->RoamRssiDiff; + if (roam_req->rssi_abs_thresh) + profile->rssi_abs_thresh = roam_req->rssi_abs_thresh; #ifdef WLAN_FEATURE_11W - if (roam_req->ConnectedNetwork.mfp_enabled) - profile->flags |= WMI_AP_PROFILE_FLAG_PMF; + if (roam_req->ConnectedNetwork.mfp_enabled) + profile->flags |= WMI_AP_PROFILE_FLAG_PMF; #endif - } } /** @@ -984,18 +1140,6 @@ void wma_roam_scan_fill_scan_params(tp_wma_handle wma_handle, WMI_SCAN_ADD_DS_IE_IN_PROBE_REQ; if (roam_req != NULL) { /* Parameters updated after association is complete */ - WMA_LOGD("%s: NeighborScanChannelMinTime: %d NeighborScanChannelMaxTime: %d", - __func__, - roam_req->NeighborScanChannelMinTime, - roam_req->NeighborScanChannelMaxTime); - WMA_LOGD("%s: NeighborScanTimerPeriod: %d " - "neighbor_scan_min_timer_period %d " - "HomeAwayTime: %d nProbes: %d", - __func__, - roam_req->NeighborScanTimerPeriod, - roam_req->neighbor_scan_min_timer_period, - roam_req->HomeAwayTime, roam_req->nProbes); - /* * roam_req->NeighborScanChannelMaxTime = SCAN_CHANNEL_TIME * roam_req->HomeAwayTime = SCAN_HOME_AWAY_TIME @@ -1124,16 +1268,15 @@ void wma_roam_scan_fill_scan_params(tp_wma_handle wma_handle, scan_params->n_probes = 0; } - WMA_LOGD("%s: Rome roam scan parameters: dwell_time_active = %d, dwell_time_passive = %d", - __func__, scan_params->dwell_time_active, - scan_params->dwell_time_passive); - WMA_LOGD("%s: min_rest_time = %d, max_rest_time = %d, repeat_probe_time = %d n_probes = %d", - __func__, scan_params->min_rest_time, - scan_params->max_rest_time, - scan_params->repeat_probe_time, scan_params->n_probes); - WMA_LOGD("%s: max_scan_time = %d, idle_time = %d, burst_duration = %d, scan_ctrl_flags = 0x%x", - __func__, scan_params->max_scan_time, scan_params->idle_time, - scan_params->burst_duration, scan_params->scan_ctrl_flags); + wma_debug("Rome roam scan parameters: dwell time: active %d passive %d, minrest %d max rest %d repeat probe time %d n_probes %d", + scan_params->dwell_time_active, + scan_params->dwell_time_passive, scan_params->min_rest_time, + scan_params->max_rest_time, scan_params->repeat_probe_time, + scan_params->n_probes); + + wma_debug("max_scan_time %d, idle_time %d, burst_duration %d, scan_ctrl_flags 0x%x", + scan_params->max_scan_time, scan_params->idle_time, + scan_params->burst_duration, scan_params->scan_ctrl_flags); } /** @@ -1154,6 +1297,17 @@ static QDF_STATUS wma_roam_scan_offload_ap_profile(tp_wma_handle wma_handle, ap_profile.vdev_id = roam_req->sessionId; wma_roam_scan_fill_ap_profile(roam_req, &ap_profile.profile); ap_profile.param = roam_req->score_params; + + ap_profile.min_rssi_params[DEAUTH_MIN_RSSI] = + roam_req->min_rssi_params[DEAUTH_MIN_RSSI]; + ap_profile.min_rssi_params[BMISS_MIN_RSSI] = + roam_req->min_rssi_params[BMISS_MIN_RSSI]; + + ap_profile.score_delta_param[IDLE_ROAM_TRIGGER] = + roam_req->score_delta_param[IDLE_ROAM_TRIGGER]; + ap_profile.score_delta_param[BTM_ROAM_TRIGGER] = + roam_req->score_delta_param[BTM_ROAM_TRIGGER]; + return wmi_unified_send_roam_scan_offload_ap_cmd(wma_handle->wmi_handle, &ap_profile); } @@ -1252,12 +1406,14 @@ static QDF_STATUS wma_roam_scan_filter(tp_wma_handle wma_handle, roam_params->ssid_allowed_list[i].length); params->ssid_allowed_list[i].length = roam_params->ssid_allowed_list[i].length; - WMA_LOGD("%s: SSID length=%d", __func__, - params->ssid_allowed_list[i].length); - qdf_trace_hex_dump(QDF_MODULE_ID_WMA, QDF_TRACE_LEVEL_DEBUG, - (uint8_t *)params->ssid_allowed_list[i].mac_ssid, - params->ssid_allowed_list[i].length); + wma_debug("SSID %d: %.*s", i, + params->ssid_allowed_list[i].length, + params->ssid_allowed_list[i].mac_ssid); } + + for (i = 0; i < params->num_bssid_black_list; i++) + wma_debug("Blacklist bssid[%d]:" QDF_MAC_ADDR_STR, i, + QDF_MAC_ADDR_ARRAY(params->bssid_avoid_list[i].bytes)); qdf_mem_copy(params->bssid_favored, roam_params->bssid_favored, MAX_BSSID_FAVORED * sizeof(struct qdf_mac_addr)); qdf_mem_copy(params->bssid_favored_factor, @@ -1267,6 +1423,11 @@ static QDF_STATUS wma_roam_scan_filter(tp_wma_handle wma_handle, MAX_RSSI_AVOID_BSSID_LIST * sizeof(struct rssi_disallow_bssid)); + for (i = 0; i < params->num_bssid_preferred_list; i++) + wma_debug("Preferred Bssid[%d]:"QDF_MAC_ADDR_STR" score: %d", i, + QDF_MAC_ADDR_ARRAY(params->bssid_favored[i].bytes), + params->bssid_favored_factor[i]); + if (params->lca_disallow_config_present) { params->disallow_duration = lca_config_params->disallow_duration; @@ -1274,6 +1435,10 @@ static QDF_STATUS wma_roam_scan_filter(tp_wma_handle wma_handle, = lca_config_params->rssi_channel_penalization; params->num_disallowed_aps = lca_config_params->num_disallowed_aps; + wma_debug("disallow_dur %d rssi_chan_pen %d num_disallowed_aps %d", + params->disallow_duration, + params->rssi_channel_penalization, + params->num_disallowed_aps); } status = wmi_unified_roam_scan_filter_cmd(wma_handle->wmi_handle, params); @@ -1367,10 +1532,14 @@ static QDF_STATUS wma_roam_scan_btm_offload(tp_wma_handle wma_handle, params->btm_max_attempt_cnt = roam_req->btm_max_attempt_cnt; params->btm_sticky_time = roam_req->btm_sticky_time; params->disassoc_timer_threshold = roam_req->disassoc_timer_threshold; + params->btm_candidate_min_score = + roam_req->btm_trig_min_candidate_score; - WMA_LOGD("%s: Sending BTM offload to FW for vdev %u btm_offload_config %u", - __func__, params->vdev_id, params->btm_offload_config); + WMA_LOGD("%s: vdev %u btm_offload:%u btm_candidate_min_score:%d", + __func__, params->vdev_id, params->btm_offload_config, + params->btm_candidate_min_score); + params->btm_query_bitmask = roam_req->btm_query_bitmask; status = wmi_unified_send_btm_config(wma_handle->wmi_handle, params); qdf_mem_free(params); @@ -1452,6 +1621,113 @@ QDF_STATUS wma_send_offload_11k_params(WMA_HANDLE handle, return status; } +#ifdef WLAN_FEATURE_ROAM_OFFLOAD +/** + * wma_send_disconnect_roam_params() - Send the disconnect roam parameters + * to wmi + * @handle: WMA handle + * @roam_req: Pointer to roam_offload_scan_req sent from CSR + * + * Return: None + */ +static void +wma_send_disconnect_roam_params(tp_wma_handle wma_handle, + tSirRoamOffloadScanReq *roam_req) +{ + QDF_STATUS status; + struct wmi_disconnect_roam_params *params = + &roam_req->disconnect_roam_params; + + if (!wma_handle || !wma_handle->wmi_handle) { + WMA_LOGE("WMA is closed, cannot send disconnect roam params"); + return; + } + + switch (roam_req->Command) { + case ROAM_SCAN_OFFLOAD_START: + case ROAM_SCAN_OFFLOAD_UPDATE_CFG: + if (!params->enable) + return; + break; + case ROAM_SCAN_OFFLOAD_STOP: + params->enable = false; + break; + default: + break; + } + + status = wmi_unified_send_disconnect_roam_params(wma_handle->wmi_handle, + params); + if (QDF_IS_STATUS_ERROR(status)) + WMA_LOGE("failed to send disconnect roam parameters"); +} + +/** + * wma_send_idle_roam_params() - Send the idle roam parameters to wmi + * @handle: WMA handle + * @roam_req: Pointer to roam_offload_scan_req sent from CSR + * + * Return: None + */ +static void +wma_send_idle_roam_params(tp_wma_handle wma_handle, + tSirRoamOffloadScanReq *roam_req) +{ + QDF_STATUS status; + + if (!wma_handle || !wma_handle->wmi_handle) { + WMA_LOGE("WMA is closed, cannot send idle roam params"); + return; + } + + switch (roam_req->Command) { + case ROAM_SCAN_OFFLOAD_START: + case ROAM_SCAN_OFFLOAD_UPDATE_CFG: + if (!roam_req->idle_roam_params.enable) + return; + break; + case ROAM_SCAN_OFFLOAD_STOP: + roam_req->idle_roam_params.enable = false; + break; + default: + break; + } + + status = wmi_unified_send_idle_roam_params(wma_handle->wmi_handle, + &roam_req->idle_roam_params); + if (QDF_IS_STATUS_ERROR(status)) + WMA_LOGE("failed to send idle roam parameters"); +} + +void +wma_send_roam_preauth_status(tp_wma_handle wma_handle, + struct wmi_roam_auth_status_params *params) +{ + QDF_STATUS status; + + if (!wma_handle || !wma_handle->wmi_handle) { + WMA_LOGE("WMA is closed, cannot send roam prauth status"); + return; + } + + status = wmi_unified_send_roam_preauth_status(wma_handle->wmi_handle, + params); + if (QDF_IS_STATUS_ERROR(status)) + WMA_LOGE("failed to send disconnect roam preauth status"); +} + +#else +static inline void +wma_send_disconnect_roam_params(tp_wma_handle wma_handle, + tSirRoamOffloadScanReq *roam_req) +{} + +static inline void +wma_send_idle_roam_params(tp_wma_handle wma_handle, + tSirRoamOffloadScanReq *roam_req) +{} +#endif + /** * wma_process_roaming_config() - process roam request * @wma_handle: wma handle @@ -1486,9 +1762,11 @@ QDF_STATUS wma_process_roaming_config(tp_wma_handle wma_handle, qdf_mem_free(roam_req); return QDF_STATUS_E_PERM; } - WMA_LOGD("%s: RSO Command:%d, reason:%d session ID %d en %d", __func__, - roam_req->Command, roam_req->reason, roam_req->sessionId, - roam_req->RoamScanOffloadEnabled); + wma_debug("RSO Command:%d, reason %d vdev %d enable %d 11k bitmask %d", + roam_req->Command, roam_req->reason, roam_req->sessionId, + roam_req->RoamScanOffloadEnabled, + roam_req->offload_11k_params.offload_11k_bitmask); + wma_handle->interfaces[roam_req->sessionId].roaming_in_progress = false; switch (roam_req->Command) { case ROAM_SCAN_OFFLOAD_START: @@ -1505,6 +1783,7 @@ QDF_STATUS wma_process_roaming_config(tp_wma_handle wma_handle, */ wma_handle->suitable_ap_hb_failure = false; + wma_set_roam_triggers(wma_handle, &roam_req->roam_triggers); qdf_status = wma_roam_scan_offload_rssi_thresh(wma_handle, roam_req); if (qdf_status != QDF_STATUS_SUCCESS) @@ -1523,10 +1802,8 @@ QDF_STATUS wma_process_roaming_config(tp_wma_handle wma_handle, if (roam_req->EmptyRefreshScanPeriod > 0) { qdf_status = wma_roam_scan_offload_scan_period(wma_handle, - roam_req->EmptyRefreshScanPeriod, - roam_req->EmptyRefreshScanPeriod * 3, - roam_req->sessionId, - roam_req->full_roam_scan_period); + roam_req); + if (qdf_status != QDF_STATUS_SUCCESS) break; @@ -1620,6 +1897,9 @@ QDF_STATUS wma_process_roaming_config(tp_wma_handle wma_handle, bss_load_cfg = &roam_req->bss_load_config; wma_send_roam_bss_load_config(wma_handle, bss_load_cfg); } + + wma_send_disconnect_roam_params(wma_handle, roam_req); + wma_send_idle_roam_params(wma_handle, roam_req); break; case ROAM_SCAN_OFFLOAD_STOP: @@ -1711,6 +1991,21 @@ QDF_STATUS wma_process_roaming_config(tp_wma_handle wma_handle, } } + wma_send_disconnect_roam_params(wma_handle, roam_req); + wma_send_idle_roam_params(wma_handle, roam_req); + + /* + * Disable all roaming triggers if RSO stop is as part of + * disconnect + */ + if (mode == WMI_ROAM_SCAN_MODE_NONE) { + struct roam_triggers roam_triggers; + + roam_triggers.vdev_id = roam_req->sessionId; + roam_triggers.trigger_bitmap = 0; + wma_set_roam_triggers(wma_handle, &roam_triggers); + } + if (roam_req->reason == REASON_OS_REQUESTED_ROAMING_NOW) { struct scheduler_msg cds_msg = {0}; @@ -1776,18 +2071,6 @@ QDF_STATUS wma_process_roaming_config(tp_wma_handle wma_handle, case ROAM_SCAN_OFFLOAD_UPDATE_CFG: wma_handle->suitable_ap_hb_failure = false; - if (roam_req->RoamScanOffloadEnabled) { - wma_roam_scan_fill_scan_params(wma_handle, pMac, - roam_req, &scan_params); - qdf_status = - wma_roam_scan_offload_mode( - wma_handle, &scan_params, roam_req, - WMI_ROAM_SCAN_MODE_NONE, - roam_req->sessionId); - if (qdf_status != QDF_STATUS_SUCCESS) - break; - } - qdf_status = wma_roam_scan_bmiss_cnt(wma_handle, roam_req->RoamBmissFirstBcnt, roam_req->RoamBmissFinalBcnt, @@ -1827,11 +2110,8 @@ QDF_STATUS wma_process_roaming_config(tp_wma_handle wma_handle, if (roam_req->EmptyRefreshScanPeriod > 0) { qdf_status = wma_roam_scan_offload_scan_period( - wma_handle, - roam_req->EmptyRefreshScanPeriod, - roam_req->EmptyRefreshScanPeriod * 3, - roam_req->sessionId, - roam_req->full_roam_scan_period); + wma_handle, + roam_req); if (qdf_status != QDF_STATUS_SUCCESS) break; @@ -1870,6 +2150,9 @@ QDF_STATUS wma_process_roaming_config(tp_wma_handle wma_handle, roam_req, mode, roam_req->sessionId); + wma_send_disconnect_roam_params(wma_handle, roam_req); + wma_send_idle_roam_params(wma_handle, roam_req); + break; default: @@ -2133,9 +2416,12 @@ static int wma_fill_roam_synch_buffer(tp_wma_handle wma, wmi_roam_synch_event_fixed_param *synch_event; wmi_channel *chan; wmi_key_material *key; + wmi_key_material_ext *key_ft; struct wma_txrx_node *iface = NULL; wmi_roam_fils_synch_tlv_param *fils_info; int status = -EINVAL; + uint8_t kck_len; + uint8_t kek_len; synch_event = param_buf->fixed_param; roam_synch_ind_ptr->roamedVdevId = synch_event->vdev_id; @@ -2151,8 +2437,8 @@ static int wma_fill_roam_synch_buffer(tp_wma_handle wma, roam_synch_ind_ptr->rssi, roam_synch_ind_ptr->isBeacon); if (!QDF_IS_STATUS_SUCCESS( - wma->csr_roam_synch_cb((tpAniSirGlobal)wma->mac_context, - roam_synch_ind_ptr, NULL, SIR_ROAMING_DEREGISTER_STA))) { + wma->csr_roam_synch_cb(wma->mac_context, roam_synch_ind_ptr, + NULL, SIR_ROAMING_DEREGISTER_STA))) { WMA_LOGE("LFR3: CSR Roam synch cb failed"); wma_free_roam_synch_frame_ind(iface); return status; @@ -2195,7 +2481,9 @@ static int wma_fill_roam_synch_buffer(tp_wma_handle wma, chan = (wmi_channel *) param_buf->chan; roam_synch_ind_ptr->chan_freq = chan->mhz; key = (wmi_key_material *) param_buf->key; - if (key != NULL) { + key_ft = param_buf->key_ext; + if (key) { + roam_synch_ind_ptr->kck_len = SIR_KCK_KEY_LEN; qdf_mem_copy(roam_synch_ind_ptr->kck, key->kck, SIR_KCK_KEY_LEN); roam_synch_ind_ptr->kek_len = SIR_KEK_KEY_LEN; @@ -2203,7 +2491,32 @@ static int wma_fill_roam_synch_buffer(tp_wma_handle wma, SIR_KEK_KEY_LEN); qdf_mem_copy(roam_synch_ind_ptr->replay_ctr, key->replay_counter, SIR_REPLAY_CTR_LEN); + } else if (key_ft) { + /* + * For AKM 00:0F:AC (FT suite-B-SHA384) + * KCK-bits:192 KEK-bits:256 + * Firmware sends wmi_key_material_ext tlv now only if + * auth is FT Suite-B SHA-384 auth. If further new suites + * are added, add logic to get kck, kek bits based on + * akm protocol + */ + kck_len = KCK_192BIT_KEY_LEN; + kek_len = KEK_256BIT_KEY_LEN; + + roam_synch_ind_ptr->kek_len = kek_len; + qdf_mem_copy(roam_synch_ind_ptr->kek, + key_ft->key_buffer, kek_len); + + roam_synch_ind_ptr->kck_len = kck_len; + qdf_mem_copy(roam_synch_ind_ptr->kck, + (key_ft->key_buffer + kek_len), + kck_len); + + qdf_mem_copy(roam_synch_ind_ptr->replay_ctr, + (key_ft->key_buffer + kek_len + kck_len), + SIR_REPLAY_CTR_LEN); } + if (param_buf->hw_mode_transition_fixed_param) wma_process_pdev_hw_mode_trans_ind(wma, param_buf->hw_mode_transition_fixed_param, @@ -2580,18 +2893,17 @@ int wma_roam_synch_event_handler(void *handle, uint8_t *event, goto cleanup_label; } qdf_mem_zero(bss_desc_ptr, sizeof(tSirBssDescription) + ie_len); - if (QDF_IS_STATUS_ERROR(wma->pe_roam_synch_cb( - (tpAniSirGlobal)wma->mac_context, - roam_synch_ind_ptr, bss_desc_ptr, - SIR_ROAM_SYNCH_PROPAGATION))) { + if (QDF_IS_STATUS_ERROR(wma->pe_roam_synch_cb(wma->mac_context, + roam_synch_ind_ptr, bss_desc_ptr, + SIR_ROAM_SYNCH_PROPAGATION))) { WMA_LOGE("LFR3: PE roam synch cb failed"); status = -EBUSY; goto cleanup_label; } wma_roam_update_vdev(wma, roam_synch_ind_ptr); - wma->csr_roam_synch_cb((tpAniSirGlobal)wma->mac_context, - roam_synch_ind_ptr, bss_desc_ptr, SIR_ROAM_SYNCH_PROPAGATION); + wma->csr_roam_synch_cb(wma->mac_context, roam_synch_ind_ptr, + bss_desc_ptr, SIR_ROAM_SYNCH_PROPAGATION); wma_process_roam_synch_complete(wma, synch_event->vdev_id); /* update freq and channel width */ @@ -2609,26 +2921,33 @@ int wma_roam_synch_event_handler(void *handle, uint8_t *event, * results in firmware assert. */ channel = cds_freq_to_chan(wma->interfaces[synch_event->vdev_id].mhz); - wma_get_phy_mode_cb(channel, - wma->interfaces[synch_event->vdev_id].chan_width, - &wma->interfaces[synch_event->vdev_id].chanmode); + if (param_buf->chan) { + wma->interfaces[synch_event->vdev_id].chanmode = + WMI_GET_CHANNEL_MODE(param_buf->chan); + } else { + wma_get_phy_mode_cb( + channel, + wma->interfaces[synch_event->vdev_id].chan_width, + &wma->interfaces[synch_event->vdev_id].chanmode); + } - wma->csr_roam_synch_cb((tpAniSirGlobal)wma->mac_context, - roam_synch_ind_ptr, bss_desc_ptr, SIR_ROAM_SYNCH_COMPLETE); + wma->csr_roam_synch_cb(wma->mac_context, roam_synch_ind_ptr, + bss_desc_ptr, SIR_ROAM_SYNCH_COMPLETE); wma->interfaces[synch_event->vdev_id].roam_synch_delay = qdf_get_system_timestamp() - roam_synch_received; WMA_LOGD("LFR3: roam_synch_delay:%d", wma->interfaces[synch_event->vdev_id].roam_synch_delay); - wma->csr_roam_synch_cb((tpAniSirGlobal)wma->mac_context, - roam_synch_ind_ptr, bss_desc_ptr, SIR_ROAM_SYNCH_NAPI_OFF); + wma->csr_roam_synch_cb(wma->mac_context, roam_synch_ind_ptr, + bss_desc_ptr, SIR_ROAM_SYNCH_NAPI_OFF); status = 0; cleanup_label: if (status != 0) { if (roam_synch_ind_ptr) - wma->csr_roam_synch_cb((tpAniSirGlobal)wma->mac_context, - roam_synch_ind_ptr, NULL, SIR_ROAMING_ABORT); + wma->csr_roam_synch_cb(wma->mac_context, + roam_synch_ind_ptr, NULL, + SIR_ROAMING_ABORT); roam_req = qdf_mem_malloc(sizeof(tSirRoamOffloadScanReq)); if (roam_req && synch_event) { roam_req->Command = ROAM_SCAN_OFFLOAD_STOP; @@ -2647,147 +2966,895 @@ int wma_roam_synch_event_handler(void *handle, uint8_t *event, wma->interfaces[synch_event->vdev_id].roam_synch_in_progress = false; - return status; + return status; +} + +int wma_roam_synch_frame_event_handler(void *handle, uint8_t *event, + uint32_t len) +{ + WMI_ROAM_SYNCH_FRAME_EVENTID_param_tlvs *param_buf = NULL; + wmi_roam_synch_frame_event_fixed_param *synch_frame_event = NULL; + tp_wma_handle wma = (tp_wma_handle) handle; + A_UINT32 vdev_id; + struct wma_txrx_node *iface = NULL; + int status = -EINVAL; + + WMA_LOGD("LFR3:Synch Frame event"); + if (!event) { + WMA_LOGE("event param null"); + return status; + } + + param_buf = (WMI_ROAM_SYNCH_FRAME_EVENTID_param_tlvs *) event; + if (!param_buf) { + WMA_LOGE("received null buf from target"); + return status; + } + + synch_frame_event = param_buf->fixed_param; + if (!synch_frame_event) { + WMA_LOGE("received null event data from target"); + return status; + } + + if (synch_frame_event->vdev_id >= wma->max_bssid) { + WMA_LOGE("received invalid vdev_id %d", + synch_frame_event->vdev_id); + return status; + } + + if (synch_frame_event->bcn_probe_rsp_len > + param_buf->num_bcn_probe_rsp_frame || + synch_frame_event->reassoc_req_len > + param_buf->num_reassoc_req_frame || + synch_frame_event->reassoc_rsp_len > + param_buf->num_reassoc_rsp_frame) { + WMA_LOGE("fixed/actual len err: bcn:%d/%d req:%d/%d rsp:%d/%d", + synch_frame_event->bcn_probe_rsp_len, + param_buf->num_bcn_probe_rsp_frame, + synch_frame_event->reassoc_req_len, + param_buf->num_reassoc_req_frame, + synch_frame_event->reassoc_rsp_len, + param_buf->num_reassoc_rsp_frame); + return status; + } + + vdev_id = synch_frame_event->vdev_id; + iface = &wma->interfaces[vdev_id]; + + if (wma_is_roam_synch_in_progress(wma, vdev_id)) { + WMA_LOGE("Ignoring this event as it is unexpected"); + wma_free_roam_synch_frame_ind(iface); + return status; + } + WMA_LOGD("LFR3: Received ROAM_SYNCH_FRAME_EVENT"); + + WMA_LOGD("synch frame payload: LEN bcn:%d, req:%d, rsp:%d morefrag: %d", + synch_frame_event->bcn_probe_rsp_len, + synch_frame_event->reassoc_req_len, + synch_frame_event->reassoc_rsp_len, + synch_frame_event->more_frag); + + if (synch_frame_event->bcn_probe_rsp_len) { + iface->roam_synch_frame_ind.bcn_probe_rsp_len = + synch_frame_event->bcn_probe_rsp_len; + iface->roam_synch_frame_ind.is_beacon = + synch_frame_event->is_beacon; + + if (iface->roam_synch_frame_ind.bcn_probe_rsp) + qdf_mem_free(iface->roam_synch_frame_ind. + bcn_probe_rsp); + iface->roam_synch_frame_ind.bcn_probe_rsp = + qdf_mem_malloc(iface->roam_synch_frame_ind. + bcn_probe_rsp_len); + if (!iface->roam_synch_frame_ind.bcn_probe_rsp) { + WMA_LOGE("failed to allocate memory for bcn_probe_rsp"); + QDF_ASSERT(iface->roam_synch_frame_ind. + bcn_probe_rsp != NULL); + status = -ENOMEM; + wma_free_roam_synch_frame_ind(iface); + return status; + } + qdf_mem_copy(iface->roam_synch_frame_ind. + bcn_probe_rsp, + param_buf->bcn_probe_rsp_frame, + iface->roam_synch_frame_ind.bcn_probe_rsp_len); + } + + if (synch_frame_event->reassoc_req_len) { + iface->roam_synch_frame_ind.reassoc_req_len = + synch_frame_event->reassoc_req_len; + + if (iface->roam_synch_frame_ind.reassoc_req) + qdf_mem_free(iface->roam_synch_frame_ind.reassoc_req); + iface->roam_synch_frame_ind.reassoc_req = + qdf_mem_malloc(iface->roam_synch_frame_ind. + reassoc_req_len); + if (!iface->roam_synch_frame_ind.reassoc_req) { + WMA_LOGE("failed to allocate memory for reassoc_req"); + QDF_ASSERT(iface->roam_synch_frame_ind. + reassoc_req != NULL); + status = -ENOMEM; + wma_free_roam_synch_frame_ind(iface); + return status; + } + qdf_mem_copy(iface->roam_synch_frame_ind.reassoc_req, + param_buf->reassoc_req_frame, + iface->roam_synch_frame_ind.reassoc_req_len); + } + + if (synch_frame_event->reassoc_rsp_len) { + iface->roam_synch_frame_ind.reassoc_rsp_len = + synch_frame_event->reassoc_rsp_len; + + if (iface->roam_synch_frame_ind.reassoc_rsp) + qdf_mem_free(iface->roam_synch_frame_ind.reassoc_rsp); + + iface->roam_synch_frame_ind.reassoc_rsp = + qdf_mem_malloc(iface->roam_synch_frame_ind. + reassoc_rsp_len); + if (!iface->roam_synch_frame_ind.reassoc_rsp) { + WMA_LOGE("failed to allocate memory for reassoc_req"); + QDF_ASSERT(iface->roam_synch_frame_ind. + reassoc_rsp != NULL); + status = -ENOMEM; + wma_free_roam_synch_frame_ind(iface); + return status; + } + qdf_mem_copy(iface->roam_synch_frame_ind.reassoc_rsp, + param_buf->reassoc_rsp_frame, + iface->roam_synch_frame_ind.reassoc_rsp_len); + } + return 0; +} + +int wma_roam_auth_offload_event_handler(WMA_HANDLE handle, uint8_t *event, + uint32_t len) +{ + QDF_STATUS status; + tp_wma_handle wma = (tp_wma_handle) handle; + tpAniSirGlobal mac_ctx; + wmi_roam_preauth_start_event_fixed_param *rso_auth_start_ev; + WMI_ROAM_PREAUTH_START_EVENTID_param_tlvs *param_buf; + struct qdf_mac_addr ap_bssid; + uint8_t vdev_id; + + if (!event) { + wma_err_rl("received null event from target"); + return -EINVAL; + } + + param_buf = (WMI_ROAM_PREAUTH_START_EVENTID_param_tlvs *) event; + if (!param_buf) { + wma_err_rl("received null buf from target"); + return -EINVAL; + } + + rso_auth_start_ev = param_buf->fixed_param; + if (!rso_auth_start_ev) { + wma_err_rl("received null event data from target"); + return -EINVAL; + } + + if (rso_auth_start_ev->vdev_id > wma->max_bssid) { + wma_err_rl("received invalid vdev_id %d", + rso_auth_start_ev->vdev_id); + return -EINVAL; + } + + mac_ctx = cds_get_context(QDF_MODULE_ID_PE); + if (!mac_ctx) { + wma_err("NULL mac ptr"); + QDF_ASSERT(0); + return -EINVAL; + } + + cds_host_diag_log_work(&wma->roam_preauth_wl, + WMA_ROAM_PREAUTH_WAKE_LOCK_DURATION, + WIFI_POWER_EVENT_WAKELOCK_WOW); + qdf_wake_lock_timeout_acquire(&wma->roam_ho_wl, + WMA_ROAM_HO_WAKE_LOCK_DURATION); + + WMI_MAC_ADDR_TO_CHAR_ARRAY(&rso_auth_start_ev->candidate_ap_bssid, + ap_bssid.bytes); + if (qdf_is_macaddr_zero(&ap_bssid) || + qdf_is_macaddr_broadcast(&ap_bssid) || + qdf_is_macaddr_group(&ap_bssid)) { + wma_err_rl("Invalid bssid"); + return -EINVAL; + } + + vdev_id = rso_auth_start_ev->vdev_id; + wma_debug("Received Roam auth offload event for bss:%pM vdev_id:%d", + ap_bssid.bytes, vdev_id); + + status = wma->csr_roam_auth_event_handle_cb(mac_ctx, vdev_id, ap_bssid); + if (QDF_IS_STATUS_ERROR(status)) { + wma_err_rl("Trigger pre-auth failed"); + return -EINVAL; + } + + return 0; +} + +#ifdef WLAN_FEATURE_ROAM_OFFLOAD +static char *wma_get_roam_trigger_str(uint32_t roam_scan_trigger) +{ + switch (roam_scan_trigger) { + case WMI_ROAM_TRIGGER_REASON_PER: + return "PER"; + case WMI_ROAM_TRIGGER_REASON_BMISS: + return "BEACON MISS"; + case WMI_ROAM_TRIGGER_REASON_LOW_RSSI: + return "LOW RSSI"; + case WMI_ROAM_TRIGGER_REASON_HIGH_RSSI: + return "HIGH RSSI"; + case WMI_ROAM_TRIGGER_REASON_PERIODIC: + return "PERIODIC SCAN"; + case WMI_ROAM_TRIGGER_REASON_MAWC: + return "MAWC"; + case WMI_ROAM_TRIGGER_REASON_DENSE: + return "DENSE ENVIRONMENT"; + case WMI_ROAM_TRIGGER_REASON_BACKGROUND: + return "BACKGROUND SCAN"; + case WMI_ROAM_TRIGGER_REASON_FORCED: + return "FORCED SCAN"; + case WMI_ROAM_TRIGGER_REASON_BTM: + return "BTM TRIGGER"; + case WMI_ROAM_TRIGGER_REASON_UNIT_TEST: + return "TEST COMMMAND"; + case WMI_ROAM_TRIGGER_REASON_BSS_LOAD: + return "HIGH BSS LOAD"; + case WMI_ROAM_TRIGGER_REASON_DEAUTH: + return "DEAUTH RECEIVED"; + case WMI_ROAM_TRIGGER_REASON_IDLE: + return "IDLE STATE SCAN"; + case WMI_ROAM_TRIGGER_REASON_NONE: + return "NONE"; + default: + return "UNKNOWN"; + } +} + +static void wma_get_converted_timestamp(uint32_t timestamp, char *time) +{ + uint32_t hr, mins, secs; + + secs = timestamp / 1000; + mins = secs / 60; + hr = mins / 60; + scnprintf(time, TIME_STRING_LEN, "[%02d:%02d:%02d.%06u]", + (hr % 24), (mins % 60), (secs % 60), + (timestamp % 1000) * 1000); +} + +static char *wma_get_roam_fail_reason_str(uint32_t result) +{ + switch (result) { + case WMI_ROAM_FAIL_REASON_NO_SCAN_START: + return "SCAN NOT STARTED"; + case WMI_ROAM_FAIL_REASON_NO_AP_FOUND: + return "NO AP FOUND"; + case WMI_ROAM_FAIL_REASON_NO_CAND_AP_FOUND: + return "NO CANDIDATE FOUND"; + case WMI_ROAM_FAIL_REASON_HOST: + return "HOST ABORTED"; + case WMI_ROAM_FAIL_REASON_AUTH_SEND: + return "Send AUTH Failed"; + case WMI_ROAM_FAIL_REASON_AUTH_RECV: + return "Received AUTH with FAILURE Status"; + case WMI_ROAM_FAIL_REASON_NO_AUTH_RESP: + return "No Auth response from AP"; + case WMI_ROAM_FAIL_REASON_REASSOC_SEND: + return "Send Re-assoc request failed"; + case WMI_ROAM_FAIL_REASON_REASSOC_RECV: + return "Received Re-Assoc resp with Failure status"; + case WMI_ROAM_FAIL_REASON_NO_REASSOC_RESP: + return "No Re-assoc response from AP"; + case WMI_ROAM_FAIL_REASON_EAPOL_M1_TIMEOUT: + return "EAPOL M1 timed out"; + case WMI_ROAM_FAIL_REASON_MLME: + return "MLME error"; + case WMI_ROAM_FAIL_REASON_INTERNAL_ABORT: + return "Fw aborted roam"; + case WMI_ROAM_FAIL_REASON_SCAN_START: + return "Unable to start roam scan"; + case WMI_ROAM_FAIL_REASON_AUTH_NO_ACK: + return "No ACK for Auth req"; + case WMI_ROAM_FAIL_REASON_AUTH_INTERNAL_DROP: + return "Auth req dropped internally"; + case WMI_ROAM_FAIL_REASON_REASSOC_NO_ACK: + return "No ACK for Re-assoc req"; + case WMI_ROAM_FAIL_REASON_REASSOC_INTERNAL_DROP: + return "Re-assoc dropped internally"; + case WMI_ROAM_FAIL_REASON_EAPOL_M2_SEND: + return "Unable to send M2 frame"; + case WMI_ROAM_FAIL_REASON_EAPOL_M2_INTERNAL_DROP: + return "M2 Frame dropped internally"; + case WMI_ROAM_FAIL_REASON_EAPOL_M2_NO_ACK: + return "No ACK for M2 frame"; + case WMI_ROAM_FAIL_REASON_EAPOL_M3_TIMEOUT: + return "EAPOL M3 timed out"; + case WMI_ROAM_FAIL_REASON_EAPOL_M4_SEND: + return "Unable to send M4 frame"; + case WMI_ROAM_FAIL_REASON_EAPOL_M4_INTERNAL_DROP: + return "M4 frame dropped internally"; + case WMI_ROAM_FAIL_REASON_EAPOL_M4_NO_ACK: + return "No ACK for M4 frame"; + default: + return "Unknown"; + } +} + +static char *wma_get_sub_reason_str(uint32_t sub_reason) +{ + switch (sub_reason) { + case WMI_ROAM_TRIGGER_SUB_REASON_PERIODIC_TIMER: + return "PERIODIC TIMER"; + case WMI_ROAM_TRIGGER_SUB_REASON_INACTIVITY_TIMER: + return "INACTIVITY TIMER"; + case WMI_ROAM_TRIGGER_SUB_REASON_BTM_DI_TIMER: + return "BTM DISASSOC TIMER"; + case WMI_ROAM_TRIGGER_SUB_REASON_FULL_SCAN: + return "FULL SCAN"; + case WMI_ROAM_TRIGGER_SUB_REASON_LOW_RSSI_PERIODIC: + return "LOW RSSI PERIODIC SCAN"; + case WMI_ROAM_TRIGGER_SUB_REASON_CU_PERIODIC: + return "CU PERIODIC SCAN"; + default: + return "NONE"; + } +} + +/** + * wma_get_trigger_detail_str - Return roam trigger string from the + * enum WMI_ROAM_TRIGGER_REASON + * @roam_info: Pointer to the roam trigger info + * @buf: Destination buffer to write the reason string + * + * Return: None + */ +static void +wma_get_trigger_detail_str(struct wmi_roam_trigger_info *roam_info, char *buf) +{ + uint16_t buf_cons, buf_left = MAX_ROAM_DEBUG_BUF_SIZE; + char *temp = buf; + + buf_cons = qdf_snprint(temp, buf_left, "Reason: \"%s\" ", + wma_get_roam_trigger_str(roam_info->trigger_reason)); + temp += buf_cons; + buf_left -= buf_cons; + + if (roam_info->trigger_sub_reason) { + buf_cons = qdf_snprint( + temp, buf_left, "Sub-Reason: %s", + wma_get_sub_reason_str(roam_info->trigger_sub_reason)); + temp += buf_cons; + buf_left -= buf_cons; + } + + switch (roam_info->trigger_reason) { + case WMI_ROAM_TRIGGER_REASON_PER: + case WMI_ROAM_TRIGGER_REASON_BMISS: + case WMI_ROAM_TRIGGER_REASON_HIGH_RSSI: + case WMI_ROAM_TRIGGER_REASON_PERIODIC: + case WMI_ROAM_TRIGGER_REASON_MAWC: + case WMI_ROAM_TRIGGER_REASON_DENSE: + case WMI_ROAM_TRIGGER_REASON_BACKGROUND: + case WMI_ROAM_TRIGGER_REASON_IDLE: + case WMI_ROAM_TRIGGER_REASON_FORCED: + case WMI_ROAM_TRIGGER_REASON_UNIT_TEST: + return; + case WMI_ROAM_TRIGGER_REASON_BTM: + buf_cons = qdf_snprint(temp, buf_left, + "Req_mode: %d Disassoc_timer: %d", + roam_info->btm_trig_data.btm_request_mode, + roam_info->btm_trig_data.disassoc_timer); + temp += buf_cons; + buf_left -= buf_cons; + + buf_cons = qdf_snprint(temp, buf_left, + "validity_interval: %d candidate_list_cnt: %d resp_status: %d", + roam_info->btm_trig_data.validity_interval, + roam_info->btm_trig_data.candidate_list_count, + roam_info->btm_trig_data.btm_resp_status); + buf_left -= buf_cons; + temp += buf_cons; + return; + case WMI_ROAM_TRIGGER_REASON_BSS_LOAD: + buf_cons = qdf_snprint(temp, buf_left, "CU: %d %% ", + roam_info->cu_trig_data.cu_load); + temp += buf_cons; + buf_left -= buf_cons; + return; + case WMI_ROAM_TRIGGER_REASON_DEAUTH: + buf_cons = qdf_snprint(temp, buf_left, "Type: %d Reason: %d ", + roam_info->deauth_trig_data.type, + roam_info->deauth_trig_data.reason); + temp += buf_cons; + buf_left -= buf_cons; + return; + case WMI_ROAM_TRIGGER_REASON_LOW_RSSI: + buf_cons = qdf_snprint(temp, buf_left, "Low_rssi_threshold: %d", + roam_info->rssi_trig_data.threshold); + temp += buf_cons; + buf_left -= buf_cons; + return; + default: + return; + } +} + + +/** + * wma_rso_print_trigger_info - Roam trigger related details + * @data: Pointer to the roam trigger data + * @vdev_id: Vdev ID + * + * Prints the vdev, roam trigger reason, time of the day at which roaming + * was triggered. + * + * Return: None + */ +static void +wma_rso_print_trigger_info(struct wmi_roam_trigger_info *data, uint8_t vdev_id) +{ + char *buf; + char time[TIME_STRING_LEN]; + + buf = qdf_mem_malloc(MAX_ROAM_DEBUG_BUF_SIZE); + if (!buf) + return; + + wma_get_trigger_detail_str(data, buf); + wma_get_converted_timestamp(data->timestamp, time); + WMA_LOGI("%s [ROAM_TRIGGER]: VDEV[%d] %s", time, vdev_id, buf); + + qdf_mem_free(buf); +} + +/** + * wma_log_roam_scan_candidates - Print roam scan candidate AP info + * @ap: Pointer to the candidate AP list + * @num_entries: Number of candidate APs + * + * Print the RSSI, CU load, Cu score, RSSI score, total score, BSSID + * and time stamp at which the candidate was found details. + * + * Return: None + */ +static void +wma_log_roam_scan_candidates(struct wmi_roam_candidate_info *ap, + uint8_t num_entries) +{ + uint16_t i; + char time[TIME_STRING_LEN]; + + WMA_LOGD("%40s%40s", LINE_STR, LINE_STR); + WMA_LOGI("%13s %16s %8s %4s %4s %5s/%3s %3s/%3s %7s", + "AP BSSID", "TSTAMP", "CH", "TY", "ETP", "RSSI", + "SCR", "CU%", "SCR", "TOT_SCR"); + WMA_LOGD("%40s%40s", LINE_STR, LINE_STR); + + if (num_entries > MAX_ROAM_CANDIDATE_AP) + num_entries = MAX_ROAM_CANDIDATE_AP; + + for (i = 0; i < num_entries; i++) { + wma_get_converted_timestamp(ap->timestamp, time); + WMA_LOGI(QDF_MAC_ADDR_STR " %17s %4d %-4s %4d %3d/%-4d %2d/%-4d %5d", + QDF_MAC_ADDR_ARRAY(ap->bssid.bytes), time, ap->freq, + ((ap->type == 0) ? "C_AP" : + ((ap->type == 2) ? "R_AP" : "P_AP")), + ap->etp, ap->rssi, ap->rssi_score, ap->cu_load, + ap->cu_score, ap->total_score); + ap++; + } +} + +/** + * wma_rso_print_scan_info - Print the roam scan details and candidate AP + * details + * @scan: Pointer to the received tlv after sanitization + * @vdev_id: vdev id + * @trigger: Roam scan trigger reason + * @timestamp: Host timestamp in millisecs + * + * Prints the roam scan details with time of the day when the scan was + * triggered and roam candidate AP with score details + * + * Return: None + */ +static void +wma_rso_print_scan_info(struct wmi_roam_scan_data *scan, uint8_t vdev_id, + uint32_t trigger, uint32_t timestamp) +{ + uint16_t num_ch = scan->num_chan; + uint16_t buf_cons = 0, buf_left = ROAM_CHANNEL_BUF_SIZE; + uint8_t i; + char *buf, *buf1, *tmp; + char time[TIME_STRING_LEN]; + + buf = qdf_mem_malloc(ROAM_CHANNEL_BUF_SIZE); + if (!buf) + return; + + tmp = buf; + /* For partial scans, print the channel info */ + if (!scan->type) { + buf_cons = qdf_snprint(tmp, buf_left, "{"); + buf_left -= buf_cons; + tmp += buf_cons; + + for (i = 0; i < num_ch; i++) { + buf_cons = qdf_snprint(tmp, buf_left, "%d ", + scan->chan_freq[i]); + buf_left -= buf_cons; + tmp += buf_cons; + } + buf_cons = qdf_snprint(tmp, buf_left, "}"); + buf_left -= buf_cons; + tmp += buf_cons; + } + + buf1 = qdf_mem_malloc(ROAM_FAILURE_BUF_SIZE); + if (!buf1) { + qdf_mem_free(buf); + return; + } + + if (WMI_ROAM_TRIGGER_REASON_LOW_RSSI == trigger) { + qdf_snprint(buf1, ROAM_FAILURE_BUF_SIZE, + "next_rssi_threshold: %d dBm", + scan->next_rssi_threshold); + } + + wma_get_converted_timestamp(timestamp, time); + WMA_LOGI("%s [ROAM_SCAN]: VDEV[%d] Scan_type: %s %s %s", + time, vdev_id, (scan->type ? "FULL" : "PARTIAL"), + buf1, buf); + wma_log_roam_scan_candidates(scan->ap, scan->num_ap); + + qdf_mem_free(buf); + qdf_mem_free(buf1); +} + +/** + * wma_rso_print_roam_result - Print roam result related info + * @res: Roam result strucure pointer + * @vdev_id: Vdev id + * + * Print roam result and failure reason if roaming failed. + * + * Return: None + */ +static void +wma_rso_print_roam_result(struct wmi_roam_result *res, + uint8_t vdev_id) +{ + char *buf; + char time[TIME_STRING_LEN]; + + buf = qdf_mem_malloc(ROAM_FAILURE_BUF_SIZE); + if (!buf) + return; + + if (!res->status) + qdf_snprint(buf, ROAM_FAILURE_BUF_SIZE, "Reason: %s", + wma_get_roam_fail_reason_str(res->fail_reason)); + + wma_get_converted_timestamp(res->timestamp, time); + WMA_LOGI("%s [ROAM_RESULT]: VDEV[%d] %s %s", + time, vdev_id, (res->status) ? "SUCCESS" : "FAILED", buf); + + qdf_mem_free(buf); +} + +/** + * wma_rso_print_11kv_info - Print neighbor report/BTM related data + * @neigh_rpt: Pointer to the extracted TLV structure + * @vdev_id: Vdev id + * + * Return: none + */ +static void +wma_rso_print_11kv_info(struct wmi_neighbor_report_data *neigh_rpt, + uint8_t vdev_id) +{ + char time[TIME_STRING_LEN], time1[TIME_STRING_LEN]; + char *buf, *tmp; + uint8_t type = neigh_rpt->req_type, i; + uint16_t buf_left = ROAM_CHANNEL_BUF_SIZE, buf_cons; + uint8_t num_ch = neigh_rpt->num_freq; + + if (!type) + return; + + buf = qdf_mem_malloc(ROAM_CHANNEL_BUF_SIZE); + if (!buf) + return; + + tmp = buf; + if (num_ch) { + buf_cons = qdf_snprint(tmp, buf_left, "{ "); + buf_left -= buf_cons; + tmp += buf_cons; + + for (i = 0; i < num_ch; i++) { + buf_cons = qdf_snprint(tmp, buf_left, "%d ", + neigh_rpt->freq[i]); + buf_left -= buf_cons; + tmp += buf_cons; + } + + buf_cons = qdf_snprint(tmp, buf_left, "}"); + buf_left -= buf_cons; + tmp += buf_cons; + } + wma_get_converted_timestamp(neigh_rpt->req_time, time); + WMA_LOGI("%s [%s] VDEV[%d]", time, + (type == 1) ? "BTM_QUERY" : "NEIGH_RPT_REQ", vdev_id); + + if (neigh_rpt->resp_time) { + wma_get_converted_timestamp(neigh_rpt->resp_time, time1); + WMA_LOGI("%s [%s] VDEV[%d] %s", time1, + (type == 1) ? "BTM_REQ" : "NEIGH_RPT_RSP", vdev_id, + (num_ch > 0) ? buf : "NO Ch update"); + } else { + WMA_LOGI("%s No response received from AP", + (type == 1) ? "BTM" : "NEIGH_RPT"); + } + qdf_mem_free(buf); +} + +int wma_roam_scan_chan_event_handler(WMA_HANDLE handle, + uint8_t *event, uint32_t len) +{ + tp_wma_handle wma = (tp_wma_handle)handle; + WMI_ROAM_SCAN_CHANNEL_LIST_EVENTID_param_tlvs *param_buf; + wmi_roam_scan_channel_list_event_fixed_param *fixed_param; + uint8_t vdev_id, i = 0, num_ch = 0; + struct roam_scan_ch_resp *resp; + struct scheduler_msg sme_msg = {0}; + + param_buf = (WMI_ROAM_SCAN_CHANNEL_LIST_EVENTID_param_tlvs *)event; + if (!param_buf) { + wma_err_rl("NULL event received from target"); + return -EINVAL; + } + + fixed_param = param_buf->fixed_param; + if (!fixed_param) { + wma_err_rl(" NULL fixed param"); + return -EINVAL; + } + + vdev_id = fixed_param->vdev_id; + if (vdev_id >= wma->max_bssid) { + wma_err_rl("Invalid vdev_id %d", vdev_id); + return -EINVAL; + } + + num_ch = (param_buf->num_channel_list < + WNI_CFG_VALID_CHANNEL_LIST_LEN) ? + param_buf->num_channel_list : + WNI_CFG_VALID_CHANNEL_LIST_LEN; + + resp = qdf_mem_malloc(sizeof(struct roam_scan_ch_resp) + + num_ch * sizeof(param_buf->channel_list[0])); + if (!resp) { + wma_err_rl("Failed to alloc resp message"); + return -EINVAL; + } + + resp->chan_list = (uint32_t *)(resp + 1); + resp->vdev_id = vdev_id; + resp->command_resp = fixed_param->command_response; + resp->num_channels = param_buf->num_channel_list; + + for (i = 0; i < num_ch; i++) + resp->chan_list[i] = param_buf->channel_list[i]; + + sme_msg.type = eWNI_SME_GET_ROAM_SCAN_CH_LIST_EVENT; + sme_msg.bodyptr = resp; + + if (scheduler_post_message(QDF_MODULE_ID_WMA, + QDF_MODULE_ID_SME, + QDF_MODULE_ID_SME, &sme_msg)) { + WMA_LOGE(FL("Failed to post msg to SME")); + qdf_mem_free(sme_msg.bodyptr); + return -EINVAL; + } + + return 0; } -int wma_roam_synch_frame_event_handler(void *handle, uint8_t *event, - uint32_t len) +int wma_roam_stats_event_handler(WMA_HANDLE handle, uint8_t *event, + uint32_t len) { - WMI_ROAM_SYNCH_FRAME_EVENTID_param_tlvs *param_buf = NULL; - wmi_roam_synch_frame_event_fixed_param *synch_frame_event = NULL; tp_wma_handle wma = (tp_wma_handle) handle; - A_UINT32 vdev_id; - struct wma_txrx_node *iface = NULL; - int status = -EINVAL; + WMI_ROAM_STATS_EVENTID_param_tlvs *param_buf; + wmi_roam_stats_event_fixed_param *fixed_param; + struct mlme_roam_debug_info *roam_info = NULL; + uint8_t vdev_id, i; + uint8_t num_tlv = 0, num_chan = 0, num_ap = 0, num_rpt = 0; + uint32_t rem_len; + QDF_STATUS status; - WMA_LOGD("LFR3:Synch Frame event"); - if (!event) { - WMA_LOGE("event param null"); - return status; + param_buf = (WMI_ROAM_STATS_EVENTID_param_tlvs *)event; + if (!param_buf) { + wma_err_rl("NULL event received from target"); + goto err; } - param_buf = (WMI_ROAM_SYNCH_FRAME_EVENTID_param_tlvs *) event; - if (!param_buf) { - WMA_LOGE("received null buf from target"); - return status; + fixed_param = param_buf->fixed_param; + if (!fixed_param) { + wma_err_rl(" NULL fixed param"); + goto err; } - synch_frame_event = param_buf->fixed_param; - if (!synch_frame_event) { - WMA_LOGE("received null event data from target"); - return status; + vdev_id = fixed_param->vdev_id; + if (vdev_id >= wma->max_bssid) { + wma_err_rl("Invalid vdev_id %d", vdev_id); + goto err; } - if (synch_frame_event->vdev_id >= wma->max_bssid) { - WMA_LOGE("received invalid vdev_id %d", - synch_frame_event->vdev_id); - return status; + num_tlv = fixed_param->roam_scan_trigger_count; + if (num_tlv > MAX_ROAM_SCAN_STATS_TLV) { + wma_err_rl("Limiting roam triggers to 5"); + num_tlv = MAX_ROAM_SCAN_STATS_TLV; } - if (synch_frame_event->bcn_probe_rsp_len > - param_buf->num_bcn_probe_rsp_frame || - synch_frame_event->reassoc_req_len > - param_buf->num_reassoc_req_frame || - synch_frame_event->reassoc_rsp_len > - param_buf->num_reassoc_rsp_frame) { - WMA_LOGE("fixed/actual len err: bcn:%d/%d req:%d/%d rsp:%d/%d", - synch_frame_event->bcn_probe_rsp_len, - param_buf->num_bcn_probe_rsp_frame, - synch_frame_event->reassoc_req_len, - param_buf->num_reassoc_req_frame, - synch_frame_event->reassoc_rsp_len, - param_buf->num_reassoc_rsp_frame); - return status; + rem_len = WMI_SVC_MSG_MAX_SIZE - sizeof(*fixed_param); + if (rem_len < num_tlv * sizeof(wmi_roam_trigger_reason)) { + wma_err_rl("Invalid roam trigger data"); + goto err; } - vdev_id = synch_frame_event->vdev_id; - iface = &wma->interfaces[vdev_id]; + rem_len -= num_tlv * sizeof(wmi_roam_trigger_reason); + if (rem_len < num_tlv * sizeof(wmi_roam_scan_info)) { + wma_err_rl("Invalid roam scan data"); + goto err; + } - if (wma_is_roam_synch_in_progress(wma, vdev_id)) { - WMA_LOGE("Ignoring this event as it is unexpected"); - wma_free_roam_synch_frame_ind(iface); - return status; + rem_len -= num_tlv * sizeof(wmi_roam_scan_info); + if (rem_len < num_tlv * sizeof(wmi_roam_result)) { + wma_err_rl("Invalid roam result data"); + goto err; } - WMA_LOGD("LFR3: Received ROAM_SYNCH_FRAME_EVENT"); - WMA_LOGD("synch frame payload: LEN bcn:%d, req:%d, rsp:%d morefrag: %d", - synch_frame_event->bcn_probe_rsp_len, - synch_frame_event->reassoc_req_len, - synch_frame_event->reassoc_rsp_len, - synch_frame_event->more_frag); + rem_len -= num_tlv * sizeof(wmi_roam_result); + if (rem_len < (num_tlv * sizeof(wmi_roam_neighbor_report_info))) { + wma_err_rl("Invalid roam neighbor report data"); + goto err; + } - if (synch_frame_event->bcn_probe_rsp_len) { - iface->roam_synch_frame_ind.bcn_probe_rsp_len = - synch_frame_event->bcn_probe_rsp_len; - iface->roam_synch_frame_ind.is_beacon = - synch_frame_event->is_beacon; + rem_len -= num_tlv * sizeof(wmi_roam_neighbor_report_info); + if (rem_len < (param_buf->num_roam_scan_chan_info * + sizeof(wmi_roam_scan_channel_info))) { + wma_err_rl("Invalid roam chan data num_tlv:%d", + param_buf->num_roam_scan_chan_info); + goto err; + } - if (iface->roam_synch_frame_ind.bcn_probe_rsp) - qdf_mem_free(iface->roam_synch_frame_ind. - bcn_probe_rsp); - iface->roam_synch_frame_ind.bcn_probe_rsp = - qdf_mem_malloc(iface->roam_synch_frame_ind. - bcn_probe_rsp_len); - if (!iface->roam_synch_frame_ind.bcn_probe_rsp) { - WMA_LOGE("failed to allocate memory for bcn_probe_rsp"); - QDF_ASSERT(iface->roam_synch_frame_ind. - bcn_probe_rsp != NULL); - status = -ENOMEM; - wma_free_roam_synch_frame_ind(iface); - return status; - } - qdf_mem_copy(iface->roam_synch_frame_ind. - bcn_probe_rsp, - param_buf->bcn_probe_rsp_frame, - iface->roam_synch_frame_ind.bcn_probe_rsp_len); + rem_len -= param_buf->num_roam_scan_chan_info * + sizeof(wmi_roam_scan_channel_info); + + if (rem_len < (param_buf->num_roam_ap_info * + sizeof(wmi_roam_ap_info))) { + wma_err_rl("Invalid roam ap data num_tlv:%d", + param_buf->num_roam_ap_info); + goto err; } - if (synch_frame_event->reassoc_req_len) { - iface->roam_synch_frame_ind.reassoc_req_len = - synch_frame_event->reassoc_req_len; + rem_len -= param_buf->num_roam_ap_info * sizeof(wmi_roam_ap_info); + if (rem_len < (param_buf->num_roam_neighbor_report_chan_info * + sizeof(wmi_roam_neighbor_report_channel_info))) { + wma_err_rl("Invalid roam neigb rpt chan data num_tlv:%d", + param_buf->num_roam_neighbor_report_chan_info); + goto err; + } - if (iface->roam_synch_frame_ind.reassoc_req) - qdf_mem_free(iface->roam_synch_frame_ind.reassoc_req); - iface->roam_synch_frame_ind.reassoc_req = - qdf_mem_malloc(iface->roam_synch_frame_ind. - reassoc_req_len); - if (!iface->roam_synch_frame_ind.reassoc_req) { - WMA_LOGE("failed to allocate memory for reassoc_req"); - QDF_ASSERT(iface->roam_synch_frame_ind. - reassoc_req != NULL); - status = -ENOMEM; - wma_free_roam_synch_frame_ind(iface); - return status; + if (!num_tlv) { + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return -ENOMEM; + + status = wmi_unified_extract_roam_11kv_stats( + wma->wmi_handle, event, + &roam_info->data_11kv, 0, 0); + if (QDF_IS_STATUS_ERROR(status)) { + WMA_LOGE("%s: Roam 11kv stats extract failed vdev %d", + __func__, vdev_id); + qdf_mem_free(roam_info); + goto err; } - qdf_mem_copy(iface->roam_synch_frame_ind.reassoc_req, - param_buf->reassoc_req_frame, - iface->roam_synch_frame_ind.reassoc_req_len); + + if (roam_info->data_11kv.present) + wma_rso_print_11kv_info(&roam_info->data_11kv, vdev_id); + + qdf_mem_free(roam_info); + return 0; } - if (synch_frame_event->reassoc_rsp_len) { - iface->roam_synch_frame_ind.reassoc_rsp_len = - synch_frame_event->reassoc_rsp_len; + for (i = 0; i < num_tlv; i++) { + roam_info = qdf_mem_malloc(sizeof(*roam_info)); + if (!roam_info) + return -ENOMEM; - if (iface->roam_synch_frame_ind.reassoc_rsp) - qdf_mem_free(iface->roam_synch_frame_ind.reassoc_rsp); + /* + * Roam Trigger id and that specific roam trigger related + * details. + */ + status = wmi_unified_extract_roam_trigger_stats( + wma->wmi_handle, event, + &roam_info->trigger, i); + if (QDF_IS_STATUS_ERROR(status)) { + WMA_LOGE("%s: Extract roam trigger stats failed vdev%d", + __func__, vdev_id); + qdf_mem_free(roam_info); + return -EINVAL; + } - iface->roam_synch_frame_ind.reassoc_rsp = - qdf_mem_malloc(iface->roam_synch_frame_ind. - reassoc_rsp_len); - if (!iface->roam_synch_frame_ind.reassoc_rsp) { - WMA_LOGE("failed to allocate memory for reassoc_req"); - QDF_ASSERT(iface->roam_synch_frame_ind. - reassoc_rsp != NULL); - status = -ENOMEM; - wma_free_roam_synch_frame_ind(iface); - return status; + /* Roam scan related details - Scan channel, scan type .. */ + status = wmi_unified_extract_roam_scan_stats( + wma->wmi_handle, event, &roam_info->scan, i, + num_chan, num_ap); + if (QDF_IS_STATUS_ERROR(status)) { + WMA_LOGE("%s: Roam scan stats extract failed vdev %d", + __func__, vdev_id); + qdf_mem_free(roam_info); + return -EINVAL; } - qdf_mem_copy(iface->roam_synch_frame_ind.reassoc_rsp, - param_buf->reassoc_rsp_frame, - iface->roam_synch_frame_ind.reassoc_rsp_len); + num_chan += roam_info->scan.num_chan; + num_ap += roam_info->scan.num_ap; + + /* Roam result - Success/Failure status, failure reason */ + status = wmi_unified_extract_roam_result_stats( + wma->wmi_handle, event, + &roam_info->result, i); + if (QDF_IS_STATUS_ERROR(status)) { + WMA_LOGE("%s: Roam result stats extract failed vdev %d", + __func__, vdev_id); + qdf_mem_free(roam_info); + return -EINVAL; + } + + /* BTM req/resp or Neighbor report/response info */ + status = wmi_unified_extract_roam_11kv_stats( + wma->wmi_handle, event, + &roam_info->data_11kv, i, num_rpt); + if (QDF_IS_STATUS_ERROR(status)) { + WMA_LOGE("%s: Roam 11kv stats extract failed vdev %d", + __func__, vdev_id); + qdf_mem_free(roam_info); + return -EINVAL; + } + num_rpt += roam_info->data_11kv.num_freq; + + if (roam_info->trigger.present) + wma_rso_print_trigger_info(&roam_info->trigger, + vdev_id); + + if (roam_info->scan.present && roam_info->trigger.present) + wma_rso_print_scan_info(&roam_info->scan, vdev_id, + roam_info->trigger.trigger_reason, + roam_info->trigger.timestamp); + + if (roam_info->result.present) + wma_rso_print_roam_result(&roam_info->result, vdev_id); + + if (roam_info->data_11kv.present) + wma_rso_print_11kv_info(&roam_info->data_11kv, vdev_id); + + qdf_mem_free(roam_info); } + return 0; + +err: + return -EINVAL; } +#endif #define RSN_CAPS_SHIFT 16 /** @@ -3149,7 +4216,6 @@ void wma_set_channel(tp_wma_handle wma, tpSwitchChannelParams params) void *soc = cds_get_context(QDF_MODULE_ID_SOC); uint16_t beacon_interval_ori; - WMA_LOGD("%s: Enter", __func__); if (!wma_find_vdev_by_addr(wma, params->selfStaMacAddr, &vdev_id)) { WMA_LOGP("%s: Failed to find vdev id for %pM", __func__, params->selfStaMacAddr); @@ -3183,9 +4249,6 @@ void wma_set_channel(tp_wma_handle wma, tpSwitchChannelParams params) req.dot11_mode = params->dot11_mode; wma_update_vdev_he_capable(&req, params); - WMA_LOGI(FL("vht_capable: %d, dot11_mode: %d"), - req.vht_capable, req.dot11_mode); - status = policy_mgr_get_current_hw_mode(wma->psoc, &hw_mode); if (!QDF_IS_STATUS_SUCCESS(status)) WMA_LOGE("policy_mgr_get_current_hw_mode failed"); @@ -5205,6 +6268,7 @@ void wma_roam_better_ap_handler(tp_wma_handle wma, uint32_t vdev_id) { struct scheduler_msg cds_msg = {0}; tSirSmeCandidateFoundInd *candidate_ind; + QDF_STATUS status; candidate_ind = qdf_mem_malloc(sizeof(tSirSmeCandidateFoundInd)); if (!candidate_ind) { @@ -5223,17 +6287,12 @@ void wma_roam_better_ap_handler(tp_wma_handle wma, uint32_t vdev_id) cds_msg.type = eWNI_SME_CANDIDATE_FOUND_IND; cds_msg.bodyptr = candidate_ind; cds_msg.callback = sme_mc_process_handler; - QDF_TRACE(QDF_MODULE_ID_WMA, QDF_TRACE_LEVEL_INFO, - FL("posting candidate ind to SME")); + wma_debug("Posting candidate ind to SME, vdev %d", vdev_id); - if (QDF_STATUS_SUCCESS != scheduler_post_message(QDF_MODULE_ID_WMA, - QDF_MODULE_ID_SME, - QDF_MODULE_ID_SCAN, - &cds_msg)) { + status = scheduler_post_message(QDF_MODULE_ID_WMA, QDF_MODULE_ID_SME, + QDF_MODULE_ID_SCAN, &cds_msg); + if (QDF_IS_STATUS_ERROR(status)) qdf_mem_free(candidate_ind); - QDF_TRACE(QDF_MODULE_ID_WMA, QDF_TRACE_LEVEL_ERROR, - FL("Failed to post candidate ind to SME")); - } } /** @@ -5261,6 +6320,54 @@ static void wma_handle_btm_disassoc_imminent_msg(tp_wma_handle wma_handle, (void *)del_sta_ctx, 0); } +/* + * wma_invalid_roam_reason_handler() - Handle Invalid roam notification + * @wma: wma handle + * @vdev_id: vdev id + * @op_code: Operation to be done by the callback + * + * This function calls pe and csr callbacks with proper op_code + * + * Return: None + */ +static void wma_invalid_roam_reason_handler(tp_wma_handle wma_handle, + uint32_t vdev_id, + uint32_t notif) +{ + roam_offload_synch_ind *roam_synch_data = NULL; + enum sir_roam_op_code op_code; + + if (notif == WMI_ROAM_NOTIF_ROAM_START) { + wma_handle->interfaces[vdev_id].roaming_in_progress = true; + op_code = SIR_ROAMING_START; + } else if (notif == WMI_ROAM_NOTIF_ROAM_ABORT) { + wma_handle->interfaces[vdev_id].roaming_in_progress = false; + op_code = SIR_ROAMING_ABORT; + } else { + WMA_LOGD(FL("Invalid notif %d"), notif); + return; + } + + roam_synch_data = qdf_mem_malloc(sizeof(*roam_synch_data)); + if (!roam_synch_data) + return; + + roam_synch_data->roamedVdevId = vdev_id; + wma_handle->pe_roam_synch_cb(wma_handle->mac_context, roam_synch_data, + NULL, op_code); + wma_handle->csr_roam_synch_cb(wma_handle->mac_context, roam_synch_data, + NULL, op_code); + + qdf_mem_free(roam_synch_data); +} + +void wma_handle_roam_sync_timeout(tp_wma_handle wma_handle, + struct roam_sync_timeout_timer_info *info) +{ + wma_invalid_roam_reason_handler(wma_handle, info->vdev_id, + WMI_ROAM_NOTIF_ROAM_ABORT); +} + /** * wma_roam_event_callback() - roam event callback * @handle: wma handle @@ -5278,7 +6385,7 @@ int wma_roam_event_callback(WMA_HANDLE handle, uint8_t *event_buf, WMI_ROAM_EVENTID_param_tlvs *param_buf; wmi_roam_event_fixed_param *wmi_event; struct sSirSmeRoamOffloadSynchInd *roam_synch_data; - enum sir_roam_op_code op_code = {0}; + uint8_t *frame = NULL; param_buf = (WMI_ROAM_EVENTID_param_tlvs *) event_buf; if (!param_buf) { @@ -5348,29 +6455,8 @@ int wma_roam_event_callback(WMA_HANDLE handle, uint8_t *event_buf, break; #endif case WMI_ROAM_REASON_INVALID: - roam_synch_data = qdf_mem_malloc(sizeof(*roam_synch_data)); - if (NULL == roam_synch_data) { - WMA_LOGE("Memory unavailable for roam synch data"); - return -ENOMEM; - } - if (wmi_event->notif == WMI_ROAM_NOTIF_ROAM_START) { - op_code = SIR_ROAMING_START; - wma_handle->interfaces[wmi_event->vdev_id]. - roaming_in_progress = true; - } - if (wmi_event->notif == WMI_ROAM_NOTIF_ROAM_ABORT) { - op_code = SIR_ROAMING_ABORT; - wma_handle->interfaces[wmi_event->vdev_id]. - roaming_in_progress = false; - } - roam_synch_data->roamedVdevId = wmi_event->vdev_id; - wma_handle->pe_roam_synch_cb( - (tpAniSirGlobal)wma_handle->mac_context, - roam_synch_data, NULL, op_code); - wma_handle->csr_roam_synch_cb( - (tpAniSirGlobal)wma_handle->mac_context, - roam_synch_data, NULL, op_code); - qdf_mem_free(roam_synch_data); + wma_invalid_roam_reason_handler(wma_handle, wmi_event->vdev_id, + wmi_event->notif); break; case WMI_ROAM_REASON_RSO_STATUS: wma_rso_cmd_status_event_handler(wmi_event); @@ -5382,11 +6468,22 @@ int wma_roam_event_callback(WMA_HANDLE handle, uint8_t *event_buf, return -ENOMEM; } roam_synch_data->roamedVdevId = wmi_event->vdev_id; - wma_handle->csr_roam_synch_cb( - (tpAniSirGlobal)wma_handle->mac_context, - roam_synch_data, NULL, SIR_ROAMING_INVOKE_FAIL); + wma_handle->csr_roam_synch_cb(wma_handle->mac_context, + roam_synch_data, NULL, + SIR_ROAMING_INVOKE_FAIL); qdf_mem_free(roam_synch_data); break; + case WMI_ROAM_REASON_DEAUTH: + WMA_LOGD("%s: Received disconnect roam event reason:%d", + __func__, wmi_event->notif_params); + + if (wmi_event->notif_params1) + frame = param_buf->deauth_disassoc_frame; + wma_handle->pe_disconnect_cb(wma_handle->mac_context, + wmi_event->vdev_id, + frame, wmi_event->notif_params1, + wmi_event->notif_params); + break; default: WMA_LOGD("%s:Unhandled Roam Event %x for vdevid %x", __func__, wmi_event->reason, wmi_event->vdev_id); @@ -5675,3 +6772,160 @@ int wma_handle_btm_blacklist_event(void *handle, uint8_t *cmd_param_info, wma_send_msg(wma, WMA_ROAM_BLACKLIST_MSG, (void *)dst_list, 0); return 0; } + +#ifdef WLAN_FEATURE_ROAM_OFFLOAD +QDF_STATUS wma_get_roam_scan_ch(tp_wma_handle wma, + uint8_t vdev_id) +{ + QDF_STATUS status = 0; + struct roam_scan_ch_resp *roam_ch; + struct scheduler_msg sme_msg = {0}; + + if (!wma_is_vdev_valid(vdev_id)) { + wma_err("vdev_id: %d is not active", vdev_id); + return QDF_STATUS_E_INVAL; + } + + status = wmi_unified_get_roam_scan_ch_list(wma->wmi_handle, vdev_id); + if (QDF_IS_STATUS_SUCCESS(status)) + return status; + + roam_ch = qdf_mem_malloc(sizeof(struct roam_scan_ch_resp)); + + if (!roam_ch) { + wma_err("Failed to alloc resp"); + return QDF_STATUS_E_INVAL; + } + + roam_ch->command_resp = 1; + roam_ch->num_channels = 0; + roam_ch->chan_list = NULL; + roam_ch->vdev_id = vdev_id; + sme_msg.type = eWNI_SME_GET_ROAM_SCAN_CH_LIST_EVENT; + sme_msg.bodyptr = roam_ch; + + if (scheduler_post_message(QDF_MODULE_ID_WMA, + QDF_MODULE_ID_SME, + QDF_MODULE_ID_SME, &sme_msg)) { + wma_err("Failed to post msg to SME"); + qdf_mem_free(roam_ch); + return -EINVAL; + } + + return status; +} + +QDF_STATUS wma_set_roam_triggers(tp_wma_handle wma, + struct roam_triggers *triggers) +{ + if (!wma_is_vdev_valid(triggers->vdev_id)) + return QDF_STATUS_E_INVAL; + + return wmi_unified_set_roam_triggers(wma->wmi_handle, triggers); +} + +#ifdef WLAN_FEATURE_FIPS +void wma_register_pmkid_req_event_handler(tp_wma_handle wma_handle) +{ + if (!wma_handle) { + wma_err("%s: pmkid req wma_handle is NULL", __func__); + return; + } + + wmi_unified_register_event_handler(wma_handle->wmi_handle, + wmi_roam_pmkid_request_event_id, + wma_roam_pmkid_request_event_handler, + WMA_RX_SERIALIZER_CTX); +} + +int wma_roam_pmkid_request_event_handler(void *handle, uint8_t *event, + uint32_t len) +{ + WMI_ROAM_PMKID_REQUEST_EVENTID_param_tlvs *param_buf; + wmi_roam_pmkid_request_event_fixed_param *roam_pmkid_req_ev; + wmi_roam_pmkid_request_tlv_param *src_list; + tp_wma_handle wma = (tp_wma_handle)handle; + struct roam_pmkid_req_event *dst_list; + struct qdf_mac_addr *roam_bsslist; + uint32_t num_entries, i; + QDF_STATUS status; + + if (!event) { + wma_err("%s: received null event from target", __func__); + return -EINVAL; + } + + param_buf = (WMI_ROAM_PMKID_REQUEST_EVENTID_param_tlvs *)event; + if (!param_buf) { + wma_err("%s: received null buf from target", __func__); + return -EINVAL; + } + + roam_pmkid_req_ev = param_buf->fixed_param; + if (!roam_pmkid_req_ev) { + wma_err("%s: received null event data from target", __func__); + return -EINVAL; + } + + if (roam_pmkid_req_ev->vdev_id >= wma->max_bssid) { + wma_err("%s: received invalid vdev_id %d", + __func__, roam_pmkid_req_ev->vdev_id); + return -EINVAL; + } + + num_entries = param_buf->num_pmkid_request; + if (num_entries > MAX_RSSI_AVOID_BSSID_LIST) { + wma_err("%s: num bssid entries:%d exceeds maximum value", + __func__, num_entries); + return -EINVAL; + } + + src_list = param_buf->pmkid_request; + if (len < (sizeof(*roam_pmkid_req_ev) + + (num_entries * sizeof(*src_list)))) { + wma_err("%s: Invalid length:%d", __func__, len); + return -EINVAL; + } + + dst_list = qdf_mem_malloc(sizeof(struct roam_pmkid_req_event) + + (sizeof(struct qdf_mac_addr) * num_entries)); + if (!dst_list) + return -ENOMEM; + + for (i = 0; i < num_entries; i++) { + roam_bsslist = &dst_list->ap_bssid[i]; + WMI_MAC_ADDR_TO_CHAR_ARRAY(&src_list->bssid, + roam_bsslist->bytes); + if (qdf_is_macaddr_zero(roam_bsslist) || + qdf_is_macaddr_broadcast(roam_bsslist) || + qdf_is_macaddr_group(roam_bsslist)) { + wma_err("%s: Invalid bssid", __func__); + qdf_mem_free(dst_list); + return -EINVAL; + } + WMA_LOGD("%s:Received pmkid fallback for bssid: %pM vdev_id:%d", + __func__, roam_bsslist->bytes, + roam_pmkid_req_ev->vdev_id); + src_list++; + } + dst_list->num_entries = num_entries; + + status = wma->csr_roam_pmkid_req_cb(roam_pmkid_req_ev->vdev_id, + dst_list); + if (QDF_IS_STATUS_ERROR(status)) { + wma_err("%s: Pmkid request failed", __func__); + qdf_mem_free(dst_list); + return -EINVAL; + } + + qdf_mem_free(dst_list); + return 0; +} +#endif /* WLAN_FEATURE_FIPS */ +#else +inline QDF_STATUS +wma_set_roam_triggers(tp_wma_handle wma, struct roam_triggers *triggers) +{ + return QDF_STATUS_E_NOSUPPORT; +} +#endif diff --git a/drivers/staging/qcacld-3.0/core/wma/src/wma_utils.c b/drivers/staging/qcacld-3.0/core/wma/src/wma_utils.c index 69580af31edf..ef1c21ae6b84 100644 --- a/drivers/staging/qcacld-3.0/core/wma/src/wma_utils.c +++ b/drivers/staging/qcacld-3.0/core/wma/src/wma_utils.c @@ -168,10 +168,6 @@ static inline uint16_t wma_mcs_rate_match(uint16_t match_rate, bool *is_sgi, uint16_t nss2_rate, uint16_t nss2_srate) { - WMA_LOGD("%s match_rate: %d, %d %d %d %d", - __func__, match_rate, nss1_rate, nss1_srate, nss2_rate, - nss2_srate); - if (match_rate == nss1_rate) { *nss = 1; return nss1_rate; @@ -195,8 +191,8 @@ uint8_t wma_get_mcs_idx(uint16_t maxRate, uint8_t rate_flags, uint16_t match_rate = 0; bool is_sgi = false; - WMA_LOGD("%s rate:%d rate_flgs: 0x%x, nss: %d", - __func__, maxRate, rate_flags, *nss); + wma_debug("Rates from FW: rate:%d rate_flgs: 0x%x, nss: %d", + maxRate, rate_flags, *nss); *mcsRateFlag = rate_flags; *mcsRateFlag &= ~TX_RATE_SGI; @@ -277,8 +273,8 @@ uint8_t wma_get_mcs_idx(uint16_t maxRate, uint8_t rate_flags, if (match_rate && is_sgi == true) *mcsRateFlag |= TX_RATE_SGI; - WMA_LOGD("%s - match_rate: %d index: %d rate_flag: 0x%x is_sgi: %d", - __func__, match_rate, index, *mcsRateFlag, is_sgi); + wma_debug("Matched rate: %d index: %d rate_flag: 0x%x is_sgi: %d", + match_rate, index, *mcsRateFlag, is_sgi); return match_rate ? index : INVALID_MCS_IDX; } @@ -1549,12 +1545,6 @@ static int wma_unified_radio_tx_power_level_stats_event_handler(void *handle, return -EINVAL; } - WMA_LOGD("%s: tot_num_tx_pwr_lvls: %u num_tx_pwr_lvls: %u pwr_lvl_offset: %u radio_id: %u", - __func__, fixed_param->total_num_tx_power_levels, - fixed_param->num_tx_power_levels, - fixed_param->power_level_offset, - fixed_param->radio_id); - if (fixed_param->num_tx_power_levels > ((WMI_SVC_MSG_MAX_SIZE - sizeof(*fixed_param)) / sizeof(uint32_t)) || fixed_param->num_tx_power_levels > @@ -1635,11 +1625,12 @@ static int wma_unified_radio_tx_power_level_stats_event_handler(void *handle, link_stats_results->moreResultToFollow = 0; link_stats_results->nr_received++; } - - WMA_LOGD("%s: moreResultToFollow: %u nr: %u nr_received: %u", - __func__, link_stats_results->moreResultToFollow, - link_stats_results->num_radio, - link_stats_results->nr_received); + WMA_LOGD("num tx pwr lvls %u num tx pwr lvls %u pwr lvl offset %u radio_id %u moretofollow: %u nr_received: %u", + fixed_param->total_num_tx_power_levels, + fixed_param->num_tx_power_levels, + fixed_param->power_level_offset, fixed_param->radio_id, + link_stats_results->moreResultToFollow, + link_stats_results->nr_received); /* If still data to receive, return from here */ if (link_stats_results->moreResultToFollow) @@ -1771,23 +1762,20 @@ static int wma_unified_link_radio_stats_event_handler(void *handle, return -EINVAL; } - WMA_LOGD("Radio stats Fixed Param:"); - WMA_LOGD("req_id: %u num_radio: %u more_radio_events: %u", + WMA_LOGD("Radio stats Fixed Param: req_id: %u num_radio: %u more_radio_events: %u", fixed_param->request_id, fixed_param->num_radio, fixed_param->more_radio_events); - WMA_LOGD("Radio Info: radio_id: %u on_time: %u tx_time: %u rx_time: %u on_time_scan: %u", - radio_stats->radio_id, radio_stats->on_time, - radio_stats->tx_time, radio_stats->rx_time, - radio_stats->on_time_scan); - WMA_LOGD("on_time_nbd: %u on_time_gscan: %u on_time_roam_scan: %u", - radio_stats->on_time_nbd, - radio_stats->on_time_gscan, radio_stats->on_time_roam_scan); - WMA_LOGD("on_time_pno_scan: %u on_time_hs20: %u num_channels: %u", - radio_stats->on_time_pno_scan, radio_stats->on_time_hs20, - radio_stats->num_channels); - WMA_LOGD("on_time_host_scan: %u, on_time_lpi_scan: %u", - radio_stats->on_time_host_scan, radio_stats->on_time_lpi_scan); + WMA_LOGD("Radio Info: radio_id: %u on_time: %u tx_time: %u rx_time: %u on_time_scan: %u on_time_nbd: %u on_time_gscan: %u on_time_roam_scan: %u", + radio_stats->radio_id, radio_stats->on_time, + radio_stats->tx_time, radio_stats->rx_time, + radio_stats->on_time_scan, radio_stats->on_time_nbd, + radio_stats->on_time_gscan, radio_stats->on_time_roam_scan); + + WMA_LOGD("on_time_pno_scan: %u on_time_hs20: %u num_channels: %u on_time_host_scan: %u, on_time_lpi_scan: %u", + radio_stats->on_time_pno_scan, radio_stats->on_time_hs20, + radio_stats->num_channels, radio_stats->on_time_host_scan, + radio_stats->on_time_lpi_scan); link_stats_results->paramId = WMI_LINK_STATS_RADIO; link_stats_results->rspId = fixed_param->request_id; @@ -1846,11 +1834,10 @@ static int wma_unified_link_radio_stats_event_handler(void *handle, next_chan_offset = WMI_TLV_HDR_SIZE; WMA_LOGD("Channel Stats Info"); for (count = 0; count < radio_stats->num_channels; count++) { - WMA_LOGD("channel_width %u center_freq %u center_freq0 %u", - channel_stats->channel_width, + WMA_LOGD("freq %u width %u freq0 %u freq1 %u awake time %u cca busy time %u", channel_stats->center_freq, - channel_stats->center_freq0); - WMA_LOGD("center_freq1 %u radio_awake_time %u cca_busy_time %u", + channel_stats->channel_width, + channel_stats->center_freq0, channel_stats->center_freq1, channel_stats->radio_awake_time, channel_stats->cca_busy_time); @@ -4269,6 +4256,21 @@ int8_t wma_get_mac_id_of_vdev(uint32_t vdev_id) return -EINVAL; } +#ifdef WLAN_FEATURE_PKT_CAPTURE +int wma_get_rmf_status(uint8_t vdev_id) +{ + struct wma_txrx_node *iface; + + iface = wma_get_interface_by_vdev_id(vdev_id); + if (!iface) { + WMA_LOGE("Unable to get wma interface"); + return -EINVAL; + } + + return iface->rmfEnabled; +} +#endif + /** * wma_update_intf_hw_mode_params() - Update WMA params * @vdev_id: VDEV id whose params needs to be updated @@ -4644,15 +4646,31 @@ static void wma_set_roam_offload_flag(tp_wma_handle wma, uint8_t vdev_id, { QDF_STATUS status; uint32_t flag = 0; + tpAniSirGlobal mac_ctx; - if (is_set) + if (is_set) { flag = WMI_ROAM_FW_OFFLOAD_ENABLE_FLAG | WMI_ROAM_BMISS_FINAL_SCAN_ENABLE_FLAG; + /* + * If WMI_ROAM_BMISS_FINAL_SCAN_ENABLE_FLAG is set, then + * WMI_ROAM_BMISS_FINAL_SCAN_TYPE_FLAG decides whether firmware + * does channel map based partial scan or partial scan followed + * by full scan in case no candidate is found in partial scan. + */ + if (wma->bmiss_skip_full_scan) + flag |= WMI_ROAM_BMISS_FINAL_SCAN_TYPE_FLAG; - WMA_LOGD("%s: vdev_id:%d, is_set:%d, flag:%d, roam_offload_enabled:%d", - __func__, vdev_id, is_set, flag, - wma->interfaces[vdev_id].roam_offload_enabled); + /* + * If 4-way HS offload is disabled then let supplicant handle + * 4way HS and firmware will still do LFR3.0 till reassoc phase. + */ + mac_ctx = (tpAniSirGlobal)cds_get_context(QDF_MODULE_ID_PE); + if (mac_ctx && + mac_ctx->roam.configParam.disable_4way_hs_offload) + flag |= WMI_VDEV_PARAM_SKIP_ROAM_EAPOL_4WAY_HANDSHAKE; + } + wma_debug("vdev_id:%d, is_set:%d, flag:%d", vdev_id, is_set, flag); status = wma_vdev_set_param(wma->wmi_handle, vdev_id, WMI_VDEV_PARAM_ROAM_FW_OFFLOAD, flag); if (QDF_IS_STATUS_ERROR(status)) @@ -4678,9 +4696,6 @@ static void wma_update_roam_offload_flag(tp_wma_handle wma, uint8_t vdev_id, uint32_t list[MAX_NUMBER_OF_CONC_CONNECTIONS]; uint8_t count; - WMA_LOGD("%s: vdev_id:%d, is_connected:%d", __func__, - vdev_id, is_connected); - iface = &wma->interfaces[vdev_id]; if ((iface->type != WMI_VDEV_TYPE_STA) || @@ -4744,6 +4759,9 @@ QDF_STATUS wma_send_vdev_up_to_fw(t_wma_handle *wma, return QDF_STATUS_SUCCESS; } + if (!wma_is_vdev_valid(params->vdev_id)) + return QDF_STATUS_E_FAILURE; + wma_update_roam_offload_flag(wma, params->vdev_id, true); status = wmi_unified_vdev_up_send(wma->wmi_handle, bssid, params); wma_release_wakelock(&vdev->vdev_start_wakelock); @@ -5077,3 +5095,50 @@ int wma_cold_boot_cal_event_handler(void *wma_ctx, uint8_t *event_buff, return 0; } + +#ifdef FEATURE_OEM_DATA +int wma_oem_event_handler(void *wma_ctx, uint8_t *event_buff, uint32_t len) +{ + WMI_OEM_DATA_EVENTID_param_tlvs *param_buf; + tpAniSirGlobal pmac = + (tpAniSirGlobal)cds_get_context(QDF_MODULE_ID_PE); + wmi_oem_data_event_fixed_param *event; + struct oem_data oem_event_data; + + if (!pmac) { + wma_err("NULL mac handle"); + return -EINVAL; + } + + if (!pmac->sme.oem_data_event_handler_cb) { + wma_err("oem data handler cb is not registered"); + return -EINVAL; + } + + param_buf = + (WMI_OEM_DATA_EVENTID_param_tlvs *)event_buff; + if (!param_buf) { + wma_err("Invalid oem data Event"); + return -EINVAL; + } + + event = param_buf->fixed_param; + if (!event) { + wma_err("Invalid fixed param in oem data Event"); + return -EINVAL; + } + + if (event->data_len > param_buf->num_data) { + wma_err("Invalid data len %d num_data %d", event->data_len, + param_buf->num_data); + return -EINVAL; + } + + oem_event_data.data_len = event->data_len; + oem_event_data.data = param_buf->data; + + pmac->sme.oem_data_event_handler_cb(&oem_event_data); + + return QDF_STATUS_SUCCESS; +} +#endif diff --git a/drivers/thermal/thermal_core.c b/drivers/thermal/thermal_core.c index c54585fb9dcc..d76d4cf9435a 100755 --- a/drivers/thermal/thermal_core.c +++ b/drivers/thermal/thermal_core.c @@ -88,9 +88,13 @@ static atomic_t temp_state = ATOMIC_INIT(0); static char boost_buf[128]; #ifdef CONFIG_THERMAL_SUSPEND_RESUME -static int prev_sconfig = 10; +static int prev_sconfig = -1; static int suspend_sconfig = -1; +static int lock_enable = 0; +static int lock_sconfig = -1; module_param(suspend_sconfig, int, 0644); +module_param(lock_enable, int, 0644); +module_param(lock_sconfig, int, 0644); #endif static struct thermal_governor *__find_governor(const char *name) @@ -2712,7 +2716,11 @@ thermal_sconfig_store(struct device *dev, int val = -1; rv = kstrtoint(buf, 10, &val); - atomic_set(&switch_mode, val); + + if(lock_enable) + atomic_set(&switch_mode, lock_sconfig); + else + atomic_set(&switch_mode, val); if (rv) return rv; diff --git a/drivers/tty/serial/msm_geni_serial.c b/drivers/tty/serial/msm_geni_serial.c index 343577ece945..84f9b5b031e0 100644 --- a/drivers/tty/serial/msm_geni_serial.c +++ b/drivers/tty/serial/msm_geni_serial.c @@ -114,7 +114,7 @@ #define UART_CORE2X_VOTE (10000) #define UART_CONSOLE_CORE2X_VOTE (960) -#define WAKEBYTE_TIMEOUT_MSEC (100) +#define WAKEBYTE_TIMEOUT_MSEC (2000) #define WAIT_XFER_MAX_ITER (50) #define WAIT_XFER_MAX_TIMEOUT_US (10000) #define WAIT_XFER_MIN_TIMEOUT_US (9000) @@ -130,6 +130,15 @@ #define DMA_RX_BUF_SIZE (2048) #define UART_CONSOLE_RX_WM (2) + +struct msm_geni_serial_ver_info { + int hw_major_ver; + int hw_minor_ver; + int hw_step_ver; + int m_fw_ver; + int s_fw_ver; +}; + struct msm_geni_serial_port { struct uart_port uport; char name[20]; @@ -166,6 +175,7 @@ struct msm_geni_serial_port { int ioctl_count; int edge_count; bool manual_flow; + struct msm_geni_serial_ver_info ver_info; u32 cur_tx_remaining; }; @@ -190,6 +200,7 @@ static int msm_geni_serial_poll_bit(struct uart_port *uport, static void msm_geni_serial_stop_rx(struct uart_port *uport); static int msm_geni_serial_runtime_resume(struct device *dev); static int msm_geni_serial_runtime_suspend(struct device *dev); +static int msm_geni_serial_get_ver_info(struct uart_port *uport); static atomic_t uart_line_id = ATOMIC_INIT(0); @@ -320,7 +331,7 @@ static void wait_for_transfers_inflight(struct uart_port *uport) static int vote_clock_on(struct uart_port *uport) { struct msm_geni_serial_port *port = GET_DEV_PORT(uport); - int usage_count = atomic_read(&uport->dev->power.usage_count); + int usage_count; int ret = 0; ret = msm_geni_serial_power_on(uport); @@ -329,15 +340,18 @@ static int vote_clock_on(struct uart_port *uport) return ret; } port->ioctl_count++; - IPC_LOG_MSG(port->ipc_log_pwr, "%s%s ioctl %d usage_count %d\n", - __func__, current->comm, port->ioctl_count, usage_count); + usage_count = atomic_read(&uport->dev->power.usage_count); + IPC_LOG_MSG(port->ipc_log_pwr, + "%s :%s ioctl:%d usage_count:%d edge-Count:%d\n", + __func__, current->comm, port->ioctl_count, + usage_count, port->edge_count); return 0; } static int vote_clock_off(struct uart_port *uport) { struct msm_geni_serial_port *port = GET_DEV_PORT(uport); - int usage_count = atomic_read(&uport->dev->power.usage_count); + int usage_count; if (!pm_runtime_enabled(uport->dev)) { dev_err(uport->dev, "RPM not available.Can't enable clocks\n"); @@ -354,7 +368,8 @@ static int vote_clock_off(struct uart_port *uport) wait_for_transfers_inflight(uport); port->ioctl_count--; msm_geni_serial_power_off(uport); - IPC_LOG_MSG(port->ipc_log_pwr, "%s%s ioctl %d usage_count %d\n", + usage_count = atomic_read(&uport->dev->power.usage_count); + IPC_LOG_MSG(port->ipc_log_pwr, "%s:%s ioctl:%d usage_count:%d\n", __func__, current->comm, port->ioctl_count, usage_count); return 0; }; @@ -389,7 +404,8 @@ static void msm_geni_serial_break_ctl(struct uart_port *uport, int ctl) if (!uart_console(uport) && device_pending_suspend(uport)) { IPC_LOG_MSG(port->ipc_log_misc, - "%s.Device is suspended.\n", __func__); + "%s.Device is suspended, %s\n", + __func__, current->comm); return; } @@ -412,9 +428,14 @@ static unsigned int msm_geni_serial_get_mctrl(struct uart_port *uport) { u32 geni_ios = 0; unsigned int mctrl = TIOCM_DSR | TIOCM_CAR; + struct msm_geni_serial_port *port = GET_DEV_PORT(uport); - if (device_pending_suspend(uport)) + if (!uart_console(uport) && device_pending_suspend(uport)) { + IPC_LOG_MSG(port->ipc_log_misc, + "%s.Device is suspended, %s\n", + __func__, current->comm); return TIOCM_DSR | TIOCM_CAR | TIOCM_CTS; + } geni_ios = geni_read_reg_nolog(uport->membase, SE_GENI_IOS); if (!(geni_ios & IO2_DATA_IN)) @@ -436,7 +457,8 @@ static void msm_geni_serial_set_mctrl(struct uart_port *uport, if (device_pending_suspend(uport)) { IPC_LOG_MSG(port->ipc_log_misc, - "%s.Device is suspended.\n", __func__); + "%s.Device is suspended, %s: mctrl=0x%x\n", + __func__, current->comm, mctrl); return; } if (!(mctrl & TIOCM_RTS)) { @@ -449,8 +471,10 @@ static void msm_geni_serial_set_mctrl(struct uart_port *uport, SE_UART_MANUAL_RFR); /* Write to flow control must complete before return to client*/ mb(); - IPC_LOG_MSG(port->ipc_log_misc, "%s: Manual_rfr 0x%x\n", - __func__, uart_manual_rfr); + IPC_LOG_MSG(port->ipc_log_misc, + "%s:%s, mctrl=0x%x, manual_rfr=0x%x, flow=%s\n", + __func__, current->comm, mctrl, uart_manual_rfr, + (port->manual_flow ? "OFF" : "ON")); } static const char *msm_geni_serial_get_type(struct uart_port *uport) @@ -916,6 +940,7 @@ static void msm_geni_serial_start_tx(struct uart_port *uport) struct msm_geni_serial_port *msm_port = GET_DEV_PORT(uport); unsigned int geni_status; unsigned int geni_ios; + static unsigned int ios_log_limit; if (!uart_console(uport) && !pm_runtime_active(uport->dev)) { IPC_LOG_MSG(msm_port->ipc_log_misc, @@ -958,9 +983,11 @@ static void msm_geni_serial_start_tx(struct uart_port *uport) return; check_flow_ctrl: geni_ios = geni_read_reg_nolog(uport->membase, SE_GENI_IOS); - if (!(geni_ios & IO2_DATA_IN)) + if (++ios_log_limit % 5 == 0) { IPC_LOG_MSG(msm_port->ipc_log_misc, "%s: ios: 0x%08x\n", - __func__, geni_ios); + __func__, geni_ios); + ios_log_limit = 0; + } exit_start_tx: if (!uart_console(uport)) msm_geni_serial_power_off(uport); @@ -1095,9 +1122,10 @@ static void start_rx_sequencer(struct uart_port *uport) * go through. */ mb(); - geni_status = geni_read_reg_nolog(uport->membase, SE_GENI_STATUS); exit_start_rx_sequencer: - IPC_LOG_MSG(port->ipc_log_misc, "%s 0x%x\n", __func__, geni_status); + geni_status = geni_read_reg_nolog(uport->membase, SE_GENI_STATUS); + IPC_LOG_MSG(port->ipc_log_misc, "%s: 0x%x, dma_dbg:0x%x\n", __func__, + geni_status, geni_read_reg(uport->membase, SE_DMA_DEBUG_REG0)); } static void msm_geni_serial_start_rx(struct uart_port *uport) @@ -1195,6 +1223,8 @@ static void stop_rx_sequencer(struct uart_port *uport) DMA_RX_BUF_SIZE); port->rx_dma = (dma_addr_t)NULL; } + geni_status = geni_read_reg_nolog(uport->membase, SE_GENI_STATUS); + IPC_LOG_MSG(port->ipc_log_misc, "%s: 0x%x\n", __func__, geni_status); } static void msm_geni_serial_stop_rx(struct uart_port *uport) @@ -1777,16 +1807,6 @@ static int msm_geni_serial_startup(struct uart_port *uport) } } - if (unlikely(get_se_proto(uport->membase) != UART)) { - dev_err(uport->dev, "%s: Invalid FW %d loaded.\n", - __func__, get_se_proto(uport->membase)); - ret = -ENXIO; - goto exit_startup; - } - IPC_LOG_MSG(msm_port->ipc_log_misc, "%s: FW Ver:0x%x%x\n", - __func__, - get_se_m_fw(uport->membase), get_se_s_fw(uport->membase)); - get_tx_fifo_size(msm_port); if (!msm_port->port_setup) { if (msm_geni_serial_port_setup(uport)) @@ -2112,6 +2132,23 @@ static ssize_t msm_geni_serial_xfer_mode_store(struct device *dev, static DEVICE_ATTR(xfer_mode, 0644, msm_geni_serial_xfer_mode_show, msm_geni_serial_xfer_mode_store); +static ssize_t ver_info_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct platform_device *pdev = to_platform_device(dev); + struct msm_geni_serial_port *port = platform_get_drvdata(pdev); + ssize_t ret = 0; + int len = (sizeof(struct msm_geni_serial_ver_info) * 2); + + ret = snprintf(buf, len, "FW ver=0x%x%x, HW ver=%d.%d.%d\n", + port->ver_info.m_fw_ver, port->ver_info.m_fw_ver, + port->ver_info.hw_major_ver, port->ver_info.hw_minor_ver, + port->ver_info.hw_step_ver); + + return ret; +} +static DEVICE_ATTR_RO(ver_info); + #if defined(CONFIG_SERIAL_CORE_CONSOLE) || defined(CONFIG_CONSOLE_POLL) static int __init msm_geni_console_setup(struct console *co, char *options) { @@ -2409,6 +2446,43 @@ static const struct of_device_id msm_geni_device_tbl[] = { {}, }; +static int msm_geni_serial_get_ver_info(struct uart_port *uport) +{ + int hw_ver, ret = 0; + struct msm_geni_serial_port *msm_port = GET_DEV_PORT(uport); + + se_geni_clks_on(&msm_port->serial_rsc); + /* Basic HW and FW info */ + if (unlikely(get_se_proto(uport->membase) != UART)) { + dev_err(uport->dev, "%s: Invalid FW %d loaded.\n", + __func__, get_se_proto(uport->membase)); + ret = -ENXIO; + goto exit_ver_info; + } + + msm_port->ver_info.m_fw_ver = get_se_m_fw(uport->membase); + msm_port->ver_info.s_fw_ver = get_se_s_fw(uport->membase); + IPC_LOG_MSG(msm_port->ipc_log_misc, "%s: FW Ver:0x%x%x\n", + __func__, + msm_port->ver_info.m_fw_ver, msm_port->ver_info.s_fw_ver); + + hw_ver = geni_se_qupv3_hw_version(msm_port->wrapper_dev, + &msm_port->ver_info.hw_major_ver, + &msm_port->ver_info.hw_minor_ver, + &msm_port->ver_info.hw_step_ver); + if (hw_ver) + dev_err(uport->dev, "%s:Err getting HW version %d\n", + __func__, hw_ver); + else + IPC_LOG_MSG(msm_port->ipc_log_misc, "%s: HW Ver:%x.%x.%x\n", + __func__, msm_port->ver_info.hw_major_ver, + msm_port->ver_info.hw_minor_ver, + msm_port->ver_info.hw_step_ver); +exit_ver_info: + se_geni_clks_off(&msm_port->serial_rsc); + return ret; +} + static int msm_geni_serial_probe(struct platform_device *pdev) { int ret = 0; @@ -2620,8 +2694,12 @@ static int msm_geni_serial_probe(struct platform_device *pdev) line, uport->fifosize, is_console); device_create_file(uport->dev, &dev_attr_loopback); device_create_file(uport->dev, &dev_attr_xfer_mode); + device_create_file(uport->dev, &dev_attr_ver_info); msm_geni_serial_debug_init(uport, is_console); dev_port->port_setup = false; + ret = msm_geni_serial_get_ver_info(uport); + if (ret) + goto exit_geni_serial_probe; return uart_add_one_port(drv, uport); exit_geni_serial_probe: @@ -2854,4 +2932,3 @@ module_exit(msm_geni_serial_exit); MODULE_DESCRIPTION("Serial driver for GENI based QTI serial cores"); MODULE_LICENSE("GPL v2"); MODULE_ALIAS("tty:msm_geni_geni_serial"); - diff --git a/drivers/tty/serial/msm_serial_hs.c b/drivers/tty/serial/msm_serial_hs.c index d099b32d40cb..a2522c6d781b 100644 --- a/drivers/tty/serial/msm_serial_hs.c +++ b/drivers/tty/serial/msm_serial_hs.c @@ -61,7 +61,6 @@ #include #include #include -#include #include #include @@ -2790,7 +2789,6 @@ static int uartdm_init_port(struct uart_port *uport) struct msm_hs_port *msm_uport = UARTDM_TO_MSM(uport); struct msm_hs_tx *tx = &msm_uport->tx; struct msm_hs_rx *rx = &msm_uport->rx; - struct sched_param param = { .sched_priority = 1 }; init_waitqueue_head(&rx->wait); init_waitqueue_head(&tx->wait); @@ -2805,8 +2803,6 @@ static int uartdm_init_port(struct uart_port *uport) MSM_HS_ERR("%s(): error creating task", __func__); goto exit_lh_init; } - sched_setscheduler(rx->task, SCHED_FIFO, ¶m); - kthread_init_work(&rx->kwork, msm_serial_hs_rx_work); kthread_init_worker(&tx->kworker); @@ -2816,7 +2812,6 @@ static int uartdm_init_port(struct uart_port *uport) MSM_HS_ERR("%s(): error creating task", __func__); goto exit_lh_init; } - sched_setscheduler(tx->task, SCHED_FIFO, ¶m); kthread_init_work(&tx->kwork, msm_serial_hs_tx_work); @@ -3331,7 +3326,6 @@ static void msm_serial_hs_rt_init(struct uart_port *uport) msm_uport->pm_state = MSM_HS_PM_SUSPENDED; mutex_unlock(&msm_uport->mtx); pm_runtime_enable(uport->dev); - tty_port_set_policy(&uport->state->port, SCHED_FIFO, 1); } static int msm_hs_runtime_suspend(struct device *dev) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 9aa8cb3b01d1..66e0112d9983 100755 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -1283,6 +1283,8 @@ static int dwc3_probe(struct platform_device *pdev) "snps,usb3-u1u2-disable"); dwc->usb2_l1_disable = device_property_read_bool(dev, "snps,usb2-l1-disable"); + dwc->normal_eps_in_gsi_mode = device_property_read_bool(dev, + "normal-eps-in-gsi-mode"); if (dwc->enable_bus_suspend) { pm_runtime_set_autosuspend_delay(dev, 500); pm_runtime_use_autosuspend(dev); @@ -1670,4 +1672,3 @@ MODULE_ALIAS("platform:dwc3"); MODULE_AUTHOR("Felipe Balbi "); MODULE_LICENSE("GPL v2"); MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver"); - diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 3cfd2c67e2ab..fc61099a5a77 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -44,6 +44,7 @@ #define DWC3_EP0_BOUNCE_SIZE 512 #define DWC3_ENDPOINTS_NUM 32 #define DWC3_XHCI_RESOURCES_NUM 2 +#define MAX_ERROR_RECOVERY_TRIES 3 #define DWC3_SCRATCHBUF_SIZE 4096 /* each buffer is assumed to be 4KiB */ #define DWC3_EVENT_BUFFERS_SIZE 4096 @@ -620,6 +621,7 @@ struct dwc3_ep_events { * @dbg_ep_events_ts: timestamp for previous event counters * @fifo_depth: allocated TXFIFO depth * @ep_cfg_init_params: Used by GSI EP to save EP_CFG init_cmd params + * @gsi_db_reg_addr: Address of GSI DB register mapped to this EP */ struct dwc3_ep { struct usb_ep endpoint; @@ -676,6 +678,7 @@ struct dwc3_ep { struct timespec dbg_ep_events_ts; int fifo_depth; struct dwc3_gadget_ep_cmd_params ep_cfg_init_params; + void __iomem *gsi_db_reg_addr; }; enum dwc3_phy { @@ -989,6 +992,8 @@ struct dwc3_scratchpad_array { * @create_reg_debugfs: create debugfs entry to allow dwc3 register dump * @xhci_imod_value: imod value to use with xhci * @core_id: usb core id to differentiate different controller + * @normal_eps_in_gsi_mode: if true, two normal EPS (1 In, 1 Out) can be used in + * GSI mode */ struct dwc3 { struct usb_ctrlrequest *ctrl_req; @@ -1190,6 +1195,8 @@ struct dwc3 { bool create_reg_debugfs; u32 xhci_imod_value; int core_id; + int retries_on_error; + bool normal_eps_in_gsi_mode; }; /* -------------------------------------------------------------------------- */ @@ -1440,4 +1447,3 @@ extern int dwc3_notify_event(struct dwc3 *dwc3, unsigned int event, unsigned int value); #endif /* __DRIVERS_USB_DWC3_CORE_H */ - diff --git a/drivers/usb/dwc3/dwc3-msm.c b/drivers/usb/dwc3/dwc3-msm.c index 10ce8d9b30f3..6bce3c775b9f 100644 --- a/drivers/usb/dwc3/dwc3-msm.c +++ b/drivers/usb/dwc3/dwc3-msm.c @@ -1,4 +1,5 @@ -/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -71,6 +72,12 @@ static int cpu_to_affin; module_param(cpu_to_affin, int, S_IRUGO|S_IWUSR); MODULE_PARM_DESC(cpu_to_affin, "affin usb irq to this cpu"); +/* Interrupt moderation for normal endpoints */ +static unsigned int dwc3_gadget_imod_val; +module_param(dwc3_gadget_imod_val, int, 0644); +MODULE_PARM_DESC(dwc3_gadget_imod_val, + "Interrupt moderation in usecs for normal EPs"); + /* XHCI registers */ #define USB3_HCSPARAMS1 (0x4) #define USB3_HCCPARAMS2 (0x1c) @@ -120,6 +127,12 @@ MODULE_PARM_DESC(cpu_to_affin, "affin usb irq to this cpu"); #define GSI_RING_BASE_ADDR_L(n) ((QSCRATCH_REG_OFFSET + 0x130) + (n*4)) #define GSI_RING_BASE_ADDR_H(n) ((QSCRATCH_REG_OFFSET + 0x144) + (n*4)) +#define IMOD(n) ((QSCRATCH_REG_OFFSET + 0x170) + (n*4)) +#define IMOD_EE_EN_MASK BIT(12) +#define IMOD_EE_CNT_MASK 0x7FF + +#define USEC_CNT (QSCRATCH_REG_OFFSET + 0x180) + #define GSI_IF_STS (QSCRATCH_REG_OFFSET + 0x1A4) #define GSI_WR_CTRL_STATE_MASK BIT(15) @@ -203,7 +216,7 @@ static const char * const gsi_op_strings[] = { "ENABLE_GSI", "UPDATE_XFER", "RING_DB", "END_XFER", "GET_CH_INFO", "GET_XFER_IDX", "PREPARE_TRBS", "FREE_TRBS", "SET_CLR_BLOCK_DBL", "CHECK_FOR_SUSP", - "EP_DISABLE" }; + "EP_DISABLE", "EP_UPDATE_DB" }; /* Input bits to state machine (mdwc->inputs) */ @@ -312,6 +325,8 @@ struct dwc3_msm { u64 dummy_gsi_db; dma_addr_t dummy_gsi_db_dma; + u64 *dummy_gevntcnt; + dma_addr_t dummy_gevntcnt_dma; }; #define USB_HSPHY_3P3_VOL_MIN 3050000 /* uV */ @@ -864,6 +879,7 @@ static void gsi_get_channel_info(struct usb_ep *ep, int last_trb_index = 0; struct dwc3 *dwc = dep->dwc; struct usb_gsi_request *request = ch_info->ch_req; + struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); /* Provide physical USB addresses for DEPCMD and GEVENTCNT registers */ ch_info->depcmd_low_addr = (u32)(dwc->reg_phys + @@ -898,14 +914,28 @@ static void gsi_get_channel_info(struct usb_ep *ep, /* Store last 16 bits of LINK TRB address as per GSI hw requirement */ ch_info->last_trb_addr = (dwc3_trb_dma_offset(dep, &dep->trb_pool[last_trb_index - 1]) & 0x0000FFFF); - ch_info->gevntcount_low_addr = (u32)(dwc->reg_phys + - DWC3_GEVNTCOUNT(ep->ep_intr_num)); - ch_info->gevntcount_hi_addr = 0; + dev_dbg(dwc->dev, "depcmd_laddr=%x last_trb_addr=%x\n", + ch_info->depcmd_low_addr, ch_info->last_trb_addr); - dev_dbg(dwc->dev, - "depcmd_laddr=%x last_trb_addr=%x gevtcnt_laddr=%x gevtcnt_haddr=%x", - ch_info->depcmd_low_addr, ch_info->last_trb_addr, - ch_info->gevntcount_low_addr, ch_info->gevntcount_hi_addr); + /* + * Check if NORMAL EP is used with GSI. In that case USB driver + * processes events and GSI shouldn't access GEVNTCOUNT(0) register. + */ + if (ep->ep_intr_num) { + ch_info->gevntcount_low_addr = (u32)(dwc->reg_phys + + DWC3_GEVNTCOUNT(ep->ep_intr_num)); + ch_info->gevntcount_hi_addr = 0; + dev_dbg(dwc->dev, "gevtcnt_laddr=%x gevtcnt_haddr=%x\n", + ch_info->gevntcount_low_addr, ch_info->gevntcount_hi_addr); + } else { + ch_info->gevntcount_low_addr = (u32)mdwc->dummy_gevntcnt_dma; + ch_info->gevntcount_hi_addr = + (u32)((u64)mdwc->dummy_gevntcnt_dma >> 32); + dev_dbg(dwc->dev, "Dummy GEVNTCNT Addr %pK: %llx %x (LSB)\n", + mdwc->dummy_gevntcnt, + (unsigned long long)mdwc->dummy_gevntcnt_dma, + (u32)mdwc->dummy_gevntcnt_dma); + } } /* @@ -929,8 +959,15 @@ static int gsi_startxfer_for_ep(struct usb_ep *ep) } memset(¶ms, 0, sizeof(params)); - params.param0 = GSI_TRB_ADDR_BIT_53_MASK | GSI_TRB_ADDR_BIT_55_MASK; - params.param0 |= (ep->ep_intr_num << 16); + /* + * Check if NORMAL EP is used with GSI. In that case USB driver + * updates GSI doorbell and USB GSI wrapper h/w isn't involved. + */ + if (ep->ep_intr_num) { + params.param0 = GSI_TRB_ADDR_BIT_53_MASK | + GSI_TRB_ADDR_BIT_55_MASK; + params.param0 |= (ep->ep_intr_num << 16); + } params.param1 = lower_32_bits(dwc3_trb_dma_offset(dep, &dep->trb_pool[0])); cmd = DWC3_DEPCMD_STARTTRANSFER; @@ -957,7 +994,18 @@ static void gsi_store_ringbase_dbl_info(struct usb_ep *ep, struct dwc3_ep *dep = to_dwc3_ep(ep); struct dwc3 *dwc = dep->dwc; struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); - int n = ep->ep_intr_num - 1; + int n; + + /* + * Check if NORMAL EP is used with GSI. In that case USB driver + * updates GSI doorbell and USB GSI wrapper h/w isn't involved. + */ + if (!ep->ep_intr_num) { + dev_dbg(mdwc->dev, "%s: is no-op for normal EP\n", __func__); + return; + } + + n = ep->ep_intr_num - 1; dwc3_msm_write_reg(mdwc->base, GSI_RING_BASE_ADDR_L(n), dwc3_trb_dma_offset(dep, &dep->trb_pool[0])); @@ -991,6 +1039,21 @@ static void gsi_store_ringbase_dbl_info(struct usb_ep *ep, dwc3_msm_read_reg(mdwc->base, GSI_DBL_ADDR_L(n))); } +static void dwc3_msm_gsi_db_update(struct dwc3_ep *dep, dma_addr_t offset) +{ + struct dwc3 *dwc = dep->dwc; + struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); + + if (!dep->gsi_db_reg_addr) { + dev_err(mdwc->dev, "Failed to update GSI DBL\n"); + return; + } + + writel_relaxed(offset, dep->gsi_db_reg_addr); + dev_dbg(mdwc->dev, "Writing TRB addr: %pa to %pK\n", + &offset, dep->gsi_db_reg_addr); +} + /* * Rings Doorbell for GSI Channel * @@ -1016,6 +1079,8 @@ static void gsi_ring_db(struct usb_ep *ep, struct usb_gsi_request *request) return; } + dep->gsi_db_reg_addr = gsi_dbl_address_lsb; + gsi_dbl_address_msb = devm_ioremap_nocache(mdwc->dev, request->db_reg_phs_addr_msb, sizeof(u32)); if (!gsi_dbl_address_msb) { @@ -1399,6 +1464,15 @@ static void gsi_enable(struct usb_ep *ep) struct dwc3 *dwc = dep->dwc; struct dwc3_msm *mdwc = dev_get_drvdata(dwc->dev->parent); + /* + * Check if NORMAL EP is used with GSI. In that case USB driver + * updates GSI doorbell and USB GSI wrapper h/w isn't involved. + */ + if (!ep->ep_intr_num) { + dev_dbg(mdwc->dev, "%s: is no-op for normal EP\n", __func__); + return; + } + dwc3_msm_write_reg_field(mdwc->base, GSI_GENERAL_CFG_REG, GSI_CLK_EN_MASK, 1); dwc3_msm_write_reg_field(mdwc->base, @@ -1435,6 +1509,12 @@ static void gsi_set_clear_dbell(struct usb_ep *ep, else gsi_enable_ep_events(ep); + /* Nothing to be done if NORMAL EP is used with GSI */ + if (!ep->ep_intr_num) { + dev_dbg(mdwc->dev, "%s: is no-op for normal EP\n", __func__); + return; + } + dwc3_msm_write_reg_field(mdwc->base, GSI_GENERAL_CFG_REG, BLOCK_GSI_WR_GO_MASK, block_db); } @@ -1490,6 +1570,7 @@ static int dwc3_msm_gsi_ep_op(struct usb_ep *ep, struct gsi_channel_info *ch_info; bool block_db; unsigned long flags; + dma_addr_t offset; dbg_log_string("%s(%d):%s", ep->name, ep->ep_num, gsi_op_to_string(op)); @@ -1555,6 +1636,10 @@ static int dwc3_msm_gsi_ep_op(struct usb_ep *ep, case GSI_EP_OP_DISABLE: ret = ep->ops->disable(ep); break; + case GSI_EP_OP_UPDATE_DB: + offset = *(dma_addr_t *)op_data; + dwc3_msm_gsi_db_update(dep, offset); + break; default: dev_err(mdwc->dev, "%s: Invalid opcode GSI EP\n", __func__); } @@ -1783,7 +1868,7 @@ static int msm_dwc3_usbdev_notify(struct notifier_block *self, } mdwc->hc_died = true; - queue_delayed_work(system_freezable_wq, &mdwc->sm_work, 0); + schedule_delayed_work(&mdwc->sm_work, 0); return 0; } @@ -1950,8 +2035,13 @@ static void dwc3_msm_notify_event(struct dwc3 *dwc, unsigned int event, reg |= DWC3_GCTL_CORESOFTRESET; dwc3_msm_write_reg(mdwc->base, DWC3_GCTL, reg); - /* restart USB which performs full reset and reconnect */ - schedule_work(&mdwc->restart_usb_work); + /* + * If the core could not recover after MAX_ERROR_RECOVERY_TRIES, + * skip the restart USB work and keep the core in softreset + * state. + */ + if (dwc->retries_on_error < MAX_ERROR_RECOVERY_TRIES) + schedule_work(&mdwc->restart_usb_work); break; case DWC3_CONTROLLER_RESET_EVENT: dev_dbg(mdwc->dev, "DWC3_CONTROLLER_RESET_EVENT received\n"); @@ -2065,6 +2155,19 @@ static void dwc3_msm_notify_event(struct dwc3 *dwc, unsigned int event, dev_err(dwc->dev, "failed to map dummy doorbell buffer\n"); mdwc->dummy_gsi_db_dma = (dma_addr_t)NULL; } + + /* + * Set-up dummy GEVNTCOUNT address to be passed on to GSI for + * normal (non HW-accelerated) EPs. + */ + mdwc->dummy_gevntcnt = + kzalloc(sizeof(*mdwc->dummy_gevntcnt), GFP_KERNEL); + if (!mdwc->dummy_gevntcnt) { + mdwc->dummy_gevntcnt_dma = (dma_addr_t)NULL; + break; + } + + mdwc->dummy_gevntcnt_dma = virt_to_phys(mdwc->dummy_gevntcnt); break; case DWC3_GSI_EVT_BUF_SETUP: dev_dbg(mdwc->dev, "DWC3_GSI_EVT_BUF_SETUP\n"); @@ -2138,6 +2241,10 @@ static void dwc3_msm_notify_event(struct dwc3 *dwc, unsigned int event, dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma); } + if (mdwc->dummy_gevntcnt_dma) { + mdwc->dummy_gevntcnt_dma = (dma_addr_t)NULL; + kfree(mdwc->dummy_gevntcnt); + } if (mdwc->dummy_gsi_db_dma) { dma_unmap_single(dwc->sysdev, mdwc->dummy_gsi_db_dma, sizeof(mdwc->dummy_gsi_db), @@ -2801,7 +2908,7 @@ static void dwc3_ext_event_notify(struct dwc3_msm *mdwc) clear_bit(B_SUSPEND, &mdwc->inputs); } - queue_delayed_work(system_freezable_wq, &mdwc->sm_work, 0); + schedule_delayed_work(&mdwc->sm_work, 0); } static void dwc3_resume_work(struct work_struct *w) @@ -2998,6 +3105,7 @@ static int dwc3_cpu_notifier_cb(struct notifier_block *nfb, } static void dwc3_otg_sm_work(struct work_struct *w); +static int get_psy_type(struct dwc3_msm *mdwc); static int dwc3_msm_get_clk_gdsc(struct dwc3_msm *mdwc) { @@ -3163,6 +3271,8 @@ static void check_for_sdp_connection(struct work_struct *w) } } +#define DP_PULSE_WIDTH_MSEC 200 + static int dwc3_msm_vbus_notifier(struct notifier_block *nb, unsigned long event, void *ptr) { @@ -3175,6 +3285,14 @@ static int dwc3_msm_vbus_notifier(struct notifier_block *nb, return NOTIFY_DONE; mdwc->vbus_active = event; + + if (get_psy_type(mdwc) == POWER_SUPPLY_TYPE_USB_CDP && + mdwc->vbus_active) { + dev_dbg(mdwc->dev, "Connected to CDP, pull DP up\n"); + usb_phy_drive_dp_pulse(mdwc->hs_phy, DP_PULSE_WIDTH_MSEC); + } + + if (dwc->is_drd && !mdwc->in_restart) queue_work(mdwc->dwc3_wq, &mdwc->resume_work); @@ -3813,6 +3931,9 @@ static int dwc3_msm_probe(struct platform_device *pdev) mdwc->pm_qos_latency = 0; } + of_property_read_u32(node, "qcom,gadget-imod-val", + &dwc3_gadget_imod_val); + mdwc->no_vbus_vote_type_c = of_property_read_bool(node, "qcom,no-vbus-vote-with-type-C"); @@ -3853,7 +3974,7 @@ static int dwc3_msm_probe(struct platform_device *pdev) dwc3_msm_id_notifier(&mdwc->id_nb, true, mdwc->extcon_id); else if (!pval.intval) { /* USB cable is not connected */ - queue_delayed_work(system_freezable_wq, &mdwc->sm_work, 0); + schedule_delayed_work(&mdwc->sm_work, 0); } else { if (pval.intval > 0) dev_info(mdwc->dev, "charger detection in progress\n"); @@ -4320,9 +4441,22 @@ static int dwc3_otg_start_peripheral(struct dwc3_msm *mdwc, int on) msm_dwc3_perf_vote_update(mdwc, true); schedule_delayed_work(&mdwc->perf_vote_work, msecs_to_jiffies(1000 * PM_QOS_SAMPLE_SEC)); + if (dwc3_gadget_imod_val > 0) { + dwc3_msm_write_reg(mdwc->base, USEC_CNT, 0x7D); + dwc3_msm_write_reg_field(mdwc->base, IMOD(0), + IMOD_EE_CNT_MASK, + dwc3_gadget_imod_val); + dwc3_msm_write_reg_field(mdwc->base, IMOD(0), + IMOD_EE_EN_MASK, 0x1); + } } else { dev_dbg(mdwc->dev, "%s: turn off gadget %s\n", __func__, dwc->gadget.name); + dwc3_msm_write_reg_field(mdwc->base, IMOD(0), + IMOD_EE_EN_MASK, 0x0); + dwc3_msm_write_reg_field(mdwc->base, IMOD(0), + IMOD_EE_CNT_MASK, 0x0); + dwc3_msm_write_reg(mdwc->base, USEC_CNT, 0x0); cancel_delayed_work_sync(&mdwc->perf_vote_work); msm_dwc3_perf_vote_update(mdwc, false); pm_qos_remove_request(&mdwc->pm_qos_req_dma); @@ -4644,7 +4778,7 @@ static void dwc3_otg_sm_work(struct work_struct *w) } if (work) - queue_delayed_work(system_freezable_wq, &mdwc->sm_work, delay); + schedule_delayed_work(&mdwc->sm_work, delay); ret: return; diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 8424341304ae..b64da2565d84 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -152,27 +152,28 @@ int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) /** * dwc3_ep_inc_trb() - Increment a TRB index. + * @dep - DWC3 endpoint * @index - Pointer to the TRB index to increment. * * The index should never point to the link TRB. After incrementing, * if it is point to the link TRB, wrap around to the beginning. The * link TRB is always at the last TRB entry. */ -static void dwc3_ep_inc_trb(u8 *index) +static void dwc3_ep_inc_trb(struct dwc3_ep *dep, u8 *index) { (*index)++; - if (*index == (DWC3_TRB_NUM - 1)) + if (*index == (dep->num_trbs - 1)) *index = 0; } void dwc3_ep_inc_enq(struct dwc3_ep *dep) { - dwc3_ep_inc_trb(&dep->trb_enqueue); + dwc3_ep_inc_trb(dep, &dep->trb_enqueue); } void dwc3_ep_inc_deq(struct dwc3_ep *dep) { - dwc3_ep_inc_trb(&dep->trb_dequeue); + dwc3_ep_inc_trb(dep, &dep->trb_dequeue); } /* @@ -744,6 +745,21 @@ static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep) dwc3_gadget_giveback(dep, req, -ESHUTDOWN); } + + if (dep->number == 1 && dwc->ep0state != EP0_SETUP_PHASE) { + unsigned int dir; + + dbg_log_string("CTRLPEND %d", dwc->ep0state); + dir = !!dwc->ep0_expect_in; + if (dwc->ep0state == EP0_DATA_PHASE) + dwc3_ep0_end_control_data(dwc, dwc->eps[dir]); + else + dwc3_ep0_end_control_data(dwc, dwc->eps[!dir]); + + dwc->eps[0]->trb_enqueue = 0; + dwc->eps[1]->trb_enqueue = 0; + } + dbg_log_string("DONE for %s(%d)", dep->name, dep->number); } @@ -1952,6 +1968,11 @@ static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend) reg1 |= DWC3_GEVNTSIZ_INTMASK; dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg1); + /* + * Reset the err_evt_seen so that the interrupts on + * next connect/session is processed correctly. + */ + dwc->err_evt_seen = false; dwc->pullups_connected = false; __dwc3_gadget_ep_disable(dwc->eps[0]); @@ -2388,8 +2409,8 @@ static const struct usb_gadget_ops dwc3_gadget_ops = { /* -------------------------------------------------------------------------- */ -#define NUM_GSI_OUT_EPS 1 -#define NUM_GSI_IN_EPS 2 +#define NUM_GSI_OUT_EPS(dwc) (dwc->normal_eps_in_gsi_mode ? 2 : 1) +#define NUM_GSI_IN_EPS(dwc) (dwc->normal_eps_in_gsi_mode ? 3 : 2) static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc, u8 num, u32 direction) @@ -2397,13 +2418,13 @@ static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc, struct dwc3_ep *dep; u8 i, gsi_ep_count, gsi_ep_index = 0; - gsi_ep_count = NUM_GSI_OUT_EPS + NUM_GSI_IN_EPS; + gsi_ep_count = NUM_GSI_OUT_EPS(dwc) + NUM_GSI_IN_EPS(dwc); /* OUT GSI EPs based on direction field */ if (gsi_ep_count && !direction) - gsi_ep_count = NUM_GSI_OUT_EPS; + gsi_ep_count = NUM_GSI_OUT_EPS(dwc); /* IN GSI EPs */ else if (gsi_ep_count && direction) - gsi_ep_count = NUM_GSI_IN_EPS; + gsi_ep_count = NUM_GSI_IN_EPS(dwc); for (i = 0; i < num; i++) { u8 epnum = (i << 1) | (direction ? 1 : 0); @@ -2422,9 +2443,12 @@ static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc, if ((gsi_ep_index < gsi_ep_count) && (i > (num - 1 - gsi_ep_count))) { gsi_ep_index++; - /* For GSI EPs, name eps as "gsi-epin" or "gsi-epout" */ - snprintf(dep->name, sizeof(dep->name), "%s", - (epnum & 1) ? "gsi-epin" : "gsi-epout"); + /* + * For GSI EPs, name eps as "gsi-epin" or + * "gsi-epout" + */ + snprintf(dep->name, sizeof(dep->name), "%s%d", + (epnum & 1) ? "gsi-epin" : "gsi-epout", epnum >> 1); /* Set ep type as GSI */ dep->endpoint.ep_type = EP_TYPE_GSI; } else { @@ -2705,6 +2729,23 @@ static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep, return 1; } +static void dwc3_gsi_ep_transfer_complete(struct dwc3 *dwc, struct dwc3_ep *dep) +{ + struct usb_ep *ep = &dep->endpoint; + struct dwc3_trb *trb; + dma_addr_t offset; + + /* + * Doorbell needs to be rung with the next TRB that is going to be + * processed by hardware. + * So, if 'n'th TRB got completed then ring doorbell with (n+1) TRB. + */ + dwc3_ep_inc_trb(dep, &dep->trb_dequeue); + trb = &dep->trb_pool[dep->trb_dequeue]; + offset = dwc3_trb_dma_offset(dep, trb); + usb_gsi_ep_op(ep, (void *)&offset, GSI_EP_OP_UPDATE_DB); +} + static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc, struct dwc3_ep *dep, const struct dwc3_event_depevt *event) { @@ -2716,6 +2757,15 @@ static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc, if (event->status & DEPEVT_STATUS_BUSERR) status = -ECONNRESET; + /* + * Check if NORMAL EP is used with GSI. + * In that case dwc3 driver recevies EP events from hardware and + * updates GSI doorbell with completed TRB. + */ + if (dep->endpoint.ep_type == EP_TYPE_GSI) { + dwc3_gsi_ep_transfer_complete(dwc, dep); + return; + } clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status); if (clean_busy && (!dep->endpoint.desc || is_xfer_complete || @@ -3171,6 +3221,8 @@ static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) speed = reg & DWC3_DSTS_CONNECTSPD; dwc->speed = speed; + /* Reset the retry on erratic error event count */ + dwc->retries_on_error = 0; dwc3_update_ram_clk_sel(dwc, speed); switch (speed) { @@ -3545,7 +3597,7 @@ static void dwc3_gadget_interrupt(struct dwc3 *dwc, break; case DWC3_DEVICE_EVENT_ERRATIC_ERROR: dwc3_trace(trace_dwc3_gadget, "Erratic Error"); - dbg_event(0xFF, "ERROR", 0); + dbg_event(0xFF, "ERROR", dwc->retries_on_error); dwc->dbg_gadget_events.erratic_error++; break; case DWC3_DEVICE_EVENT_CMD_CMPL: @@ -3634,6 +3686,7 @@ static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc) if (dwc3_notify_event(dwc, DWC3_CONTROLLER_ERROR_EVENT, 0)) dwc->err_evt_seen = 0; + dwc->retries_on_error++; break; } @@ -3868,7 +3921,6 @@ int dwc3_gadget_init(struct dwc3 *dwc) dwc->gadget.speed = USB_SPEED_UNKNOWN; dwc->gadget.sg_supported = true; dwc->gadget.name = "dwc3-gadget"; - dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG; dwc->gadget.l1_supported = !dwc->usb2_l1_disable; /* diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c index aab4972c649a..9e3cfae241a1 100755 --- a/drivers/usb/gadget/composite.c +++ b/drivers/usb/gadget/composite.c @@ -2478,7 +2478,6 @@ void composite_suspend(struct usb_gadget *gadget) cdev->suspended = 1; spin_unlock_irqrestore(&cdev->lock, flags); - usb_gadget_set_selfpowered(gadget); usb_gadget_vbus_draw(gadget, 2); } @@ -2700,4 +2699,3 @@ EXPORT_SYMBOL_GPL(usb_composite_overwrite_options); MODULE_LICENSE("GPL"); MODULE_AUTHOR("David Brownell"); - diff --git a/drivers/usb/gadget/function/f_fs.c b/drivers/usb/gadget/function/f_fs.c index fc701f5b42bb..dc7ae5b62ab8 100755 --- a/drivers/usb/gadget/function/f_fs.c +++ b/drivers/usb/gadget/function/f_fs.c @@ -1302,6 +1302,9 @@ static int ffs_aio_cancel(struct kiocb *kiocb) ENTER(); + ffs_log("enter:state %d setup_state %d flag %lu", epfile->ffs->state, + epfile->ffs->setup_state, epfile->ffs->flags); + spin_lock_irqsave(&epfile->ffs->eps_lock, flags); if (likely(io_data && io_data->ep && io_data->req)) diff --git a/drivers/usb/gadget/function/f_gsi.c b/drivers/usb/gadget/function/f_gsi.c index 56ab0508e70b..ca1a1cdbf377 100644 --- a/drivers/usb/gadget/function/f_gsi.c +++ b/drivers/usb/gadget/function/f_gsi.c @@ -776,9 +776,6 @@ static void ipa_data_path_enable(struct gsi_data_port *d_port) GSI_EP_OP_STORE_DBL_INFO); } - usb_gsi_ep_op(d_port->in_ep, &d_port->in_request, - GSI_EP_OP_ENABLE_GSI); - usb_gsi_ep_op(d_port->in_ep, &d_port->in_request, GSI_EP_OP_ENABLE_GSI); diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c index d5e31954f489..f3b7a4e42393 100644 --- a/drivers/usb/host/xhci-mem.c +++ b/drivers/usb/host/xhci-mem.c @@ -1532,15 +1532,15 @@ int xhci_endpoint_init(struct xhci_hcd *xhci, /* Allow 3 retries for everything but isoc, set CErr = 3 */ if (!usb_endpoint_xfer_isoc(&ep->desc)) err_count = 3; - /* Some devices get this wrong */ - if (usb_endpoint_xfer_bulk(&ep->desc) && udev->speed == USB_SPEED_HIGH) - max_packet = 512; - - if (usb_endpoint_xfer_bulk(&ep->desc) && udev->speed == USB_SPEED_FULL - && max_packet < 8) - max_packet = 8; - - + /* HS bulk max packet should be 512, FS bulk supports 8, 16, 32 or 64 */ + if (usb_endpoint_xfer_bulk(&ep->desc)) { + if (udev->speed == USB_SPEED_HIGH) + max_packet = 512; + if (udev->speed == USB_SPEED_FULL) { + max_packet = rounddown_pow_of_two(max_packet); + max_packet = clamp_val(max_packet, 8, 64); + } + } /* xHCI 1.0 and 1.1 indicates that ctrl ep avg TRB Length should be 8 */ if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version >= 0x100) avg_trb_len = 8; diff --git a/drivers/usb/phy/phy-msm-qusb-v2.c b/drivers/usb/phy/phy-msm-qusb-v2.c index c44d0a521863..a40b8ccbdfd0 100644 --- a/drivers/usb/phy/phy-msm-qusb-v2.c +++ b/drivers/usb/phy/phy-msm-qusb-v2.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2014-2018, 2020, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/drivers/usb/phy/phy-msm-qusb.c b/drivers/usb/phy/phy-msm-qusb.c index 53836d7a8760..9d6636606cad 100644 --- a/drivers/usb/phy/phy-msm-qusb.c +++ b/drivers/usb/phy/phy-msm-qusb.c @@ -1027,8 +1027,8 @@ static int qusb_phy_probe(struct platform_device *pdev) if (IS_ERR(qphy->iface_clk)) { ret = PTR_ERR(qphy->iface_clk); qphy->iface_clk = NULL; - if (ret == -EPROBE_DEFER) - return ret; + if (ret == -EPROBE_DEFER) + return ret; dev_err(dev, "couldn't get iface_clk(%d)\n", ret); } } diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 2510a750bef7..f9ee30e8238c 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -47,6 +47,10 @@ if FB || SGI_NEWPORT_CONSOLE endif -source "drivers/video/klapse/Kconfig" +config KLAPSE + bool CONFIG_KLAPSE + default n + help + A simple rgb dynamic lapsing module similar to LineageOS' livedisplay endmenu diff --git a/drivers/video/Makefile b/drivers/video/Makefile index ba2dbd005a2a..84711014b3db 100644 --- a/drivers/video/Makefile +++ b/drivers/video/Makefile @@ -12,4 +12,4 @@ obj-$(CONFIG_VIDEOMODE_HELPERS) += display_timing.o videomode.o ifeq ($(CONFIG_OF),y) obj-$(CONFIG_VIDEOMODE_HELPERS) += of_display_timing.o of_videomode.o endif -obj-$(CONFIG_KLAPSE) += klapse/ +obj-$(CONFIG_KLAPSE) += klapse/klapse.o diff --git a/drivers/video/backlight/backlight.c b/drivers/video/backlight/backlight.c index 1d7add9e1b7a..8c835f16af82 100644 --- a/drivers/video/backlight/backlight.c +++ b/drivers/video/backlight/backlight.c @@ -24,7 +24,6 @@ static struct list_head backlight_dev_list; static struct mutex backlight_dev_list_mutex; static struct blocking_notifier_head backlight_notifier; -static int bl_event; static const char *const backlight_types[] = { [BACKLIGHT_RAW] = "raw", @@ -120,7 +119,6 @@ static void backlight_generate_event(struct backlight_device *bd, envp[1] = NULL; kobject_uevent_env(&bd->dev.kobj, KOBJ_CHANGE, envp); sysfs_notify(&bd->dev.kobj, NULL, "actual_brightness"); - sysfs_notify(&bd->dev.kobj, NULL, "brightness"); } static ssize_t bl_power_show(struct device *dev, struct device_attribute *attr, @@ -182,22 +180,7 @@ int backlight_device_set_brightness(struct backlight_device *bd, if (brightness > bd->props.max_brightness) rc = -EINVAL; else { - if ((!bd->use_count && brightness) || (bd->use_count && !brightness)) { - pr_info("%s: set brightness to %lu\n", __func__, brightness); - if (!bd->use_count) - bd->use_count++; - else - bd->use_count--; - } - pr_debug("set brightness to %lu\n", brightness); - if (!brightness) { - bl_event = BACKLIGHT_OFF; - blocking_notifier_call_chain(&backlight_notifier, BACKLIGHT_UPDATED, &bl_event); - } else if (bl_event != BACKLIGHT_ON) { - bl_event = BACKLIGHT_ON; - blocking_notifier_call_chain(&backlight_notifier, BACKLIGHT_UPDATED, &bl_event); - } bd->props.brightness = brightness; rc = backlight_update_status(bd); } @@ -308,47 +291,12 @@ static void bl_device_release(struct device *dev) kfree(bd); } -static ssize_t brightness_clone_show(struct device *dev, - struct device_attribute *attr, char *buf) -{ - struct backlight_device *bd = to_backlight_device(dev); - - return snprintf(buf, PAGE_SIZE, "%d\n", bd->props.brightness_clone); -} - -static ssize_t brightness_clone_store(struct device *dev, - struct device_attribute *attr, const char *buf, size_t count) -{ - int rc; - struct backlight_device *bd = to_backlight_device(dev); - unsigned long brightness; - char *envp[2]; - - rc = kstrtoul(buf, 0, &brightness); - if (rc) - return rc; - - bd->props.brightness_clone = (brightness <= bd->thermal_brightness_limit) ? - brightness : - bd->thermal_brightness_limit; - - envp[0] = "SOURCE=sysfs"; - envp[1] = NULL; - kobject_uevent_env(&bd->dev.kobj, KOBJ_CHANGE, envp); - sysfs_notify(&bd->dev.kobj, NULL, "brightness_clone"); - - return count; -} - -static DEVICE_ATTR_RW(brightness_clone); - static struct attribute *bl_device_attrs[] = { &dev_attr_bl_power.attr, &dev_attr_brightness.attr, &dev_attr_actual_brightness.attr, &dev_attr_max_brightness.attr, &dev_attr_type.attr, - &dev_attr_brightness_clone.attr, NULL, }; ATTRIBUTE_GROUPS(bl_device); diff --git a/fs/dcache.c b/fs/dcache.c index 7ad76361e261..e1abf9c02aba 100644 --- a/fs/dcache.c +++ b/fs/dcache.c @@ -82,7 +82,7 @@ * dentry1->d_lock * dentry2->d_lock */ -int sysctl_vfs_cache_pressure __read_mostly = 50; +int sysctl_vfs_cache_pressure __read_mostly = 100; EXPORT_SYMBOL_GPL(sysctl_vfs_cache_pressure); __cacheline_aligned_in_smp DEFINE_SEQLOCK(rename_lock); diff --git a/fs/drop_caches.c b/fs/drop_caches.c index 15f65b3f4f2b..280460fef066 100644 --- a/fs/drop_caches.c +++ b/fs/drop_caches.c @@ -8,8 +8,6 @@ #include #include #include -#include -#include #include "internal.h" /* A global variable is a bit ugly, but it keeps the code simple */ @@ -47,18 +45,6 @@ static void drop_pagecache_sb(struct super_block *sb, void *unused) iput(toput_inode); } -void mm_drop_caches(int val) -{ - if (val & 1) { - iterate_supers(drop_pagecache_sb, NULL); - count_vm_event(DROP_PAGECACHE); - } - if (val & 2) { - drop_slab(); - count_vm_event(DROP_SLAB); - } -} - int drop_caches_sysctl_handler(struct ctl_table *table, int write, void __user *buffer, size_t *length, loff_t *ppos) { @@ -70,8 +56,14 @@ int drop_caches_sysctl_handler(struct ctl_table *table, int write, if (write) { static int stfu; - mm_drop_caches(sysctl_drop_caches); - + if (sysctl_drop_caches & 1) { + iterate_supers(drop_pagecache_sb, NULL); + count_vm_event(DROP_PAGECACHE); + } + if (sysctl_drop_caches & 2) { + drop_slab(); + count_vm_event(DROP_SLAB); + } if (!stfu) { pr_info("%s (%d): drop_caches: %d\n", current->comm, task_pid_nr(current), @@ -81,45 +73,3 @@ int drop_caches_sysctl_handler(struct ctl_table *table, int write, } return 0; } - -static void drop_caches_now(struct work_struct *work); -static DECLARE_WORK(drop_caches_now_work, drop_caches_now); - -static void drop_caches_now(struct work_struct *work) -{ - /* sleep for 200ms */ - msleep(200); - /* sync */ - emergency_sync(); - /* echo "1" > /proc/sys/vm/drop_caches */ - iterate_supers(drop_pagecache_sb, NULL); -} - -static int fb_notifier(struct notifier_block *self, - unsigned long event, void *data) -{ - struct fb_event *evdata = (struct fb_event *)data; - - if ((event == FB_EVENT_BLANK) && evdata && evdata->data) { - int blank = *(int *)evdata->data; - - if (blank == FB_BLANK_POWERDOWN) { - schedule_work_on(0, &drop_caches_now_work); - return NOTIFY_OK; - } - return NOTIFY_OK; - } - return NOTIFY_DONE; -} - -static struct notifier_block fb_notifier_block = { - .notifier_call = fb_notifier, - .priority = -1, -}; - -static int __init drop_caches_init(void) -{ - fb_register_client(&fb_notifier_block); - return 0; -} -late_initcall(drop_caches_init); diff --git a/fs/ext4/page-io.c b/fs/ext4/page-io.c index 5bce451b8f96..c1b02899cfc2 100644 --- a/fs/ext4/page-io.c +++ b/fs/ext4/page-io.c @@ -479,11 +479,9 @@ int ext4_bio_write_page(struct ext4_io_submit *io, if (io->io_bio) gfp_flags = GFP_NOWAIT | __GFP_NOWARN; retry_encrypt: - if (!fscrypt_using_hardware_encryption(inode)) { + if (!fscrypt_using_hardware_encryption(inode)) data_page = fscrypt_encrypt_page(inode, page, PAGE_SIZE, 0, page->index, gfp_flags); - } - if (IS_ERR(data_page)) { ret = PTR_ERR(data_page); if (ret == -ENOMEM && diff --git a/fs/f2fs/data.c b/fs/f2fs/data.c index df9ecda869e1..20402f4cd1fe 100644 --- a/fs/f2fs/data.c +++ b/fs/f2fs/data.c @@ -2389,11 +2389,8 @@ static int f2fs_write_cache_pages(struct address_space *mapping, ret = 0; if (wbc->sync_mode == WB_SYNC_ALL) { cond_resched(); -#if (CONFIG_HZ > 100) - congestion_wait(BLK_RW_ASYNC, 2); -#else - congestion_wait(BLK_RW_ASYNC, 1); -#endif + congestion_wait(BLK_RW_ASYNC, + HZ/50); goto retry_write; } continue; diff --git a/fs/f2fs/f2fs.h b/fs/f2fs/f2fs.h index 69f2ee9947a5..3ce399d9133e 100755 --- a/fs/f2fs/f2fs.h +++ b/fs/f2fs/f2fs.h @@ -192,7 +192,6 @@ enum { #define DEF_MID_DISCARD_ISSUE_TIME 500 /* 500 ms, if device busy */ #define DEF_MAX_DISCARD_ISSUE_TIME 60000 /* 60 s, if no candidates */ #define DEF_DISCARD_URGENT_UTIL 80 /* do more discard over 80% */ -#define DEF_MAX_DISCARD_URGENT_ISSUE_TIME 10000 /* 10 s, if no candidates on high utilization */ #define DEF_CP_INTERVAL 60 /* 60 secs */ #define DEF_IDLE_INTERVAL 5 /* 5 secs */ #define DEF_DISABLE_INTERVAL 5 /* 5 secs */ @@ -1277,7 +1276,6 @@ struct f2fs_sb_info { unsigned int cur_victim_sec; /* current victim section num */ unsigned int gc_mode; /* current GC state */ unsigned int next_victim_seg[2]; /* next segment in victim section */ - unsigned int rapid_gc; /* is rapid GC running */ /* for skip statistic */ unsigned long long skipped_atomic_files[2]; /* FG_GC and BG_GC */ unsigned long long skipped_gc_rwsem; /* FG_GC only */ @@ -1345,8 +1343,6 @@ struct f2fs_sb_info { /* Precomputed FS UUID checksum for seeding other checksums */ __u32 s_chksum_seed; - - struct list_head list; }; struct f2fs_private_dio { @@ -3241,11 +3237,6 @@ void f2fs_clear_radix_tree_dirty_tag(struct page *page); */ int f2fs_start_gc_thread(struct f2fs_sb_info *sbi); void f2fs_stop_gc_thread(struct f2fs_sb_info *sbi); -void f2fs_gc_sbi_list_add(struct f2fs_sb_info *sbi); -void f2fs_gc_sbi_list_del(struct f2fs_sb_info *sbi); -void __init f2fs_init_rapid_gc(void); -void __exit f2fs_destroy_rapid_gc(void); - block_t f2fs_start_bidx_of_node(unsigned int node_ofs, struct inode *inode); int f2fs_gc(struct f2fs_sb_info *sbi, bool sync, bool background, unsigned int segno); diff --git a/fs/f2fs/gc.c b/fs/f2fs/gc.c index 2b553389b843..41a60aaf42e9 100644 --- a/fs/f2fs/gc.c +++ b/fs/f2fs/gc.c @@ -13,9 +13,6 @@ #include #include #include -#include -#include -#include #include "f2fs.h" #include "node.h" @@ -23,39 +20,14 @@ #include "gc.h" #include -#define TRIGGER_RAPID_GC (!screen_on && power_supply_is_system_supplied()) -static bool screen_on = true; -static LIST_HEAD(gc_sbi_list); -static DEFINE_MUTEX(gc_wakelock_mutex); -static DEFINE_MUTEX(gc_sbi_mutex); -static struct wakeup_source gc_wakelock; - -static inline void rapid_gc_set_wakelock(void) -{ - struct f2fs_sb_info *sbi; - unsigned int set = 0; - - mutex_lock(&gc_wakelock_mutex); - list_for_each_entry(sbi, &gc_sbi_list, list) { - set |= sbi->rapid_gc; - } - - if (set && !gc_wakelock.active) { - pr_info("F2FS-fs: Catching wakelock for rapid GC"); - __pm_stay_awake(&gc_wakelock); - } else if (!set && gc_wakelock.active) { - pr_info("F2FS-fs: Unlocking wakelock for rapid GC"); - __pm_relax(&gc_wakelock); - } - mutex_unlock(&gc_wakelock_mutex); -} - static int gc_thread_func(void *data) { struct f2fs_sb_info *sbi = data; struct f2fs_gc_kthread *gc_th = sbi->gc_thread; wait_queue_head_t *wq = &sbi->gc_thread->gc_wait_queue_head; - unsigned int wait_ms = gc_th->min_sleep_time; + unsigned int wait_ms; + + wait_ms = gc_th->min_sleep_time; set_freezable(); do { @@ -64,18 +36,6 @@ static int gc_thread_func(void *data) gc_th->gc_wake, msecs_to_jiffies(wait_ms)); - sbi->rapid_gc = TRIGGER_RAPID_GC ? 1 : 0; - if (sbi->rapid_gc) { - rapid_gc_set_wakelock(); - // Use 1 instead of 0 to allow thread interrupts - wait_ms = 1; - sbi->gc_mode = GC_URGENT; - } else { - rapid_gc_set_wakelock(); - wait_ms = gc_th->min_sleep_time; - sbi->gc_mode = GC_NORMAL; - } - /* give it a try one time */ if (gc_th->gc_wake) gc_th->gc_wake = 0; @@ -88,10 +48,8 @@ static int gc_thread_func(void *data) break; if (sbi->sb->s_writers.frozen >= SB_FREEZE_WRITE) { - if (!sbi->rapid_gc) { - increase_sleep_time(gc_th, &wait_ms); - stat_other_skip_bggc_count(sbi); - } + increase_sleep_time(gc_th, &wait_ms); + stat_other_skip_bggc_count(sbi); continue; } @@ -118,9 +76,8 @@ static int gc_thread_func(void *data) * invalidated soon after by user update or deletion. * So, I'd like to wait some time to collect dirty segments. */ - if (sbi->gc_mode == GC_URGENT || sbi->rapid_gc) { - if (!sbi->rapid_gc) - wait_ms = gc_th->urgent_sleep_time; + if (sbi->gc_mode == GC_URGENT) { + wait_ms = gc_th->urgent_sleep_time; mutex_lock(&sbi->gc_mutex); goto do_gc; } @@ -145,21 +102,8 @@ static int gc_thread_func(void *data) stat_inc_bggc_count(sbi); /* if return value is not zero, no victim was selected */ - if (f2fs_gc(sbi, sbi->rapid_gc || test_opt(sbi, FORCE_FG_GC), true, NULL_SEGNO)) { + if (f2fs_gc(sbi, test_opt(sbi, FORCE_FG_GC), true, NULL_SEGNO)) wait_ms = gc_th->no_gc_sleep_time; - sbi->rapid_gc = false; - rapid_gc_set_wakelock(); - sbi->gc_mode = GC_NORMAL; - f2fs_info(sbi, "No more rapid GC victim found, " - "sleeping for %u ms", wait_ms); - - /* - * Rapid GC would have cleaned hundreds of segments - * that would not be read again anytime soon. - */ - mm_drop_caches(3); - f2fs_info(sbi, "dropped caches"); - } trace_f2fs_background_gc(sbi->sb, wait_ms, prefree_segments(sbi), free_segments(sbi)); @@ -179,9 +123,6 @@ int f2fs_start_gc_thread(struct f2fs_sb_info *sbi) dev_t dev = sbi->sb->s_bdev->bd_dev; int err = 0; - if (sbi->gc_thread != NULL) - goto out; - gc_th = f2fs_kmalloc(sbi, sizeof(struct f2fs_gc_kthread), GFP_KERNEL); if (!gc_th) { err = -ENOMEM; @@ -193,7 +134,6 @@ int f2fs_start_gc_thread(struct f2fs_sb_info *sbi) gc_th->max_sleep_time = DEF_GC_THREAD_MAX_SLEEP_TIME; gc_th->no_gc_sleep_time = DEF_GC_THREAD_NOGC_SLEEP_TIME; - sbi->gc_mode = GC_NORMAL; gc_th->gc_wake= 0; sbi->gc_thread = gc_th; @@ -205,8 +145,6 @@ int f2fs_start_gc_thread(struct f2fs_sb_info *sbi) kvfree(gc_th); sbi->gc_thread = NULL; } - set_task_ioprio(sbi->gc_thread->f2fs_gc_task, - IOPRIO_PRIO_VALUE(IOPRIO_CLASS_IDLE, 0)); out: return err; } @@ -214,139 +152,13 @@ int f2fs_start_gc_thread(struct f2fs_sb_info *sbi) void f2fs_stop_gc_thread(struct f2fs_sb_info *sbi) { struct f2fs_gc_kthread *gc_th = sbi->gc_thread; - sbi->rapid_gc = false; if (!gc_th) return; kthread_stop(gc_th->f2fs_gc_task); kvfree(gc_th); - sbi->gc_mode = GC_NORMAL; sbi->gc_thread = NULL; } -/* Trigger rapid GC when invalid block is higher than 3% */ -#define RAPID_GC_LIMIT_INVALID_BLOCK 3 - -static void f2fs_start_rapid_gc(void) -{ - struct f2fs_sb_info *sbi; - block_t invalid_blocks; - - mutex_lock(&gc_sbi_mutex); - list_for_each_entry(sbi, &gc_sbi_list, list) { - invalid_blocks = sbi->user_block_count - - written_block_count(sbi) - - free_user_blocks(sbi); - if (invalid_blocks > - ((long)((sbi->user_block_count - written_block_count(sbi)) * - RAPID_GC_LIMIT_INVALID_BLOCK) / 100)) { - f2fs_start_gc_thread(sbi); - sbi->gc_thread->gc_wake = 1; - wake_up_interruptible_all(&sbi->gc_thread->gc_wait_queue_head); - wake_up_discard_thread(sbi, true); - } else { - f2fs_info(sbi, "Invalid blocks lower than %d%%," - "skipping rapid GC (%u / (%u - %u))", - RAPID_GC_LIMIT_INVALID_BLOCK, - invalid_blocks, - sbi->user_block_count, - written_block_count(sbi)); - } - } - mutex_unlock(&gc_sbi_mutex); -} - -static void f2fs_stop_rapid_gc(void) -{ - struct f2fs_sb_info *sbi; - - mutex_lock(&gc_sbi_mutex); - list_for_each_entry(sbi, &gc_sbi_list, list) { - f2fs_stop_gc_thread(sbi); - } - mutex_unlock(&gc_sbi_mutex); - - rapid_gc_set_wakelock(); -} - -void f2fs_gc_sbi_list_add(struct f2fs_sb_info *sbi) -{ - mutex_lock(&gc_sbi_mutex); - list_add_tail(&sbi->list, &gc_sbi_list); - mutex_unlock(&gc_sbi_mutex); -} - -void f2fs_gc_sbi_list_del(struct f2fs_sb_info *sbi) -{ - mutex_lock(&gc_sbi_mutex); - list_del(&sbi->list); - mutex_unlock(&gc_sbi_mutex); -} - -static struct work_struct rapid_gc_fb_worker; -static void rapid_gc_fb_work(struct work_struct *work) -{ - if (screen_on) { - f2fs_stop_rapid_gc(); - } else { - /* - * Start all GC threads exclusively from here - * since the phone screen would turn on when - * a charger is connected - */ - if (TRIGGER_RAPID_GC) - f2fs_start_rapid_gc(); - } -} - -static int msm_drm_notifier_callback(struct notifier_block *self, - unsigned long event, void *data) -{ - struct msm_drm_notifier *evdata = data; - int *blank; - - if (event != MSM_DRM_EVENT_BLANK) - goto out; - - if (!evdata || !evdata->data || evdata->id != MSM_DRM_PRIMARY_DISPLAY) - goto out; - - blank = evdata->data; - switch (*blank) { - case MSM_DRM_BLANK_POWERDOWN: - if (!screen_on) - goto out; - screen_on = false; - queue_work(system_power_efficient_wq, &rapid_gc_fb_worker); - break; - case MSM_DRM_BLANK_UNBLANK: - if (screen_on) - goto out; - screen_on = true; - queue_work(system_power_efficient_wq, &rapid_gc_fb_worker); - break; - } - -out: - return NOTIFY_OK; -} - -static struct notifier_block fb_notifier_block = { - .notifier_call = msm_drm_notifier_callback, -}; - -void __init f2fs_init_rapid_gc(void) -{ - INIT_WORK(&rapid_gc_fb_worker, rapid_gc_fb_work); - wakeup_source_init(&gc_wakelock, "f2fs_rapid_gc_wakelock"); - msm_drm_register_client(&fb_notifier_block); -} - -void __exit f2fs_destroy_rapid_gc(void) -{ - msm_drm_unregister_client(&fb_notifier_block); - wakeup_source_trash(&gc_wakelock); -} - static int select_gc_type(struct f2fs_sb_info *sbi, int gc_type) { int gc_mode = (gc_type == BG_GC) ? GC_CB : GC_GREEDY; @@ -1426,12 +1238,11 @@ int f2fs_gc(struct f2fs_sb_info *sbi, bool sync, .ilist = LIST_HEAD_INIT(gc_list.ilist), .iroot = RADIX_TREE_INIT(GFP_NOFS), }; - struct super_block *sb = sbi->sb; unsigned long long last_skipped = sbi->skipped_atomic_files[FG_GC]; unsigned long long first_skipped; unsigned int skipped_round = 0, round = 0; - trace_f2fs_gc_begin(sb, sync, background, + trace_f2fs_gc_begin(sbi->sb, sync, background, get_pages(sbi, F2FS_DIRTY_NODES), get_pages(sbi, F2FS_DIRTY_DENTS), get_pages(sbi, F2FS_DIRTY_IMETA), @@ -1444,7 +1255,7 @@ int f2fs_gc(struct f2fs_sb_info *sbi, bool sync, sbi->skipped_gc_rwsem = 0; first_skipped = last_skipped; gc_more: - if (unlikely(!(sb->s_flags & MS_ACTIVE))) { + if (unlikely(!(sbi->sb->s_flags & MS_ACTIVE))) { ret = -EINVAL; goto stop; } @@ -1519,7 +1330,7 @@ int f2fs_gc(struct f2fs_sb_info *sbi, bool sync, SIT_I(sbi)->last_victim[ALLOC_NEXT] = 0; SIT_I(sbi)->last_victim[FLUSH_DEVICE] = init_segno; - trace_f2fs_gc_end(sb, ret, total_freed, sec_freed, + trace_f2fs_gc_end(sbi->sb, ret, total_freed, sec_freed, get_pages(sbi, F2FS_DIRTY_NODES), get_pages(sbi, F2FS_DIRTY_DENTS), get_pages(sbi, F2FS_DIRTY_IMETA), @@ -1534,13 +1345,6 @@ int f2fs_gc(struct f2fs_sb_info *sbi, bool sync, if (sync && !ret) ret = sec_freed ? 0 : -EAGAIN; - - if (gc_type == FG_GC && down_read_trylock(&sb->s_umount)) { - writeback_inodes_sb(sb, WB_REASON_SYNC); - sync_inodes_sb(sb); - up_read(&sb->s_umount); - } - return ret; } diff --git a/fs/f2fs/gc.h b/fs/f2fs/gc.h index 2bd53eecf398..bbac9d3787bd 100644 --- a/fs/f2fs/gc.h +++ b/fs/f2fs/gc.h @@ -13,7 +13,7 @@ #define DEF_GC_THREAD_URGENT_SLEEP_TIME 500 /* 500 ms */ #define DEF_GC_THREAD_MIN_SLEEP_TIME 30000 /* milliseconds */ #define DEF_GC_THREAD_MAX_SLEEP_TIME 60000 -#define DEF_GC_THREAD_NOGC_SLEEP_TIME 1800000 /* wait 30 min */ +#define DEF_GC_THREAD_NOGC_SLEEP_TIME 300000 /* wait 5 min */ #define LIMIT_INVALID_BLOCK 40 /* percentage over total user space */ #define LIMIT_FREE_BLOCK 40 /* percentage over invalid + free space */ diff --git a/fs/f2fs/segment.c b/fs/f2fs/segment.c index ebd50f7148af..4431e6aae3d9 100755 --- a/fs/f2fs/segment.c +++ b/fs/f2fs/segment.c @@ -1075,10 +1075,10 @@ static void __init_discard_policy(struct f2fs_sb_info *sbi, dpolicy->ordered = true; if (utilization(sbi) > DEF_DISCARD_URGENT_UTIL) { dpolicy->granularity = 1; - dpolicy->max_interval = DEF_MAX_DISCARD_URGENT_ISSUE_TIME; + dpolicy->max_interval = DEF_MIN_DISCARD_ISSUE_TIME; } } else if (discard_type == DPOLICY_FORCE) { - dpolicy->min_interval = 1; + dpolicy->min_interval = DEF_MIN_DISCARD_ISSUE_TIME; dpolicy->mid_interval = DEF_MID_DISCARD_ISSUE_TIME; dpolicy->max_interval = DEF_MAX_DISCARD_ISSUE_TIME; dpolicy->io_aware = false; @@ -1689,8 +1689,7 @@ static int issue_discard_thread(void *data) wait_event_interruptible_timeout(*q, kthread_should_stop() || freezing(current) || dcc->discard_wake, - msecs_to_jiffies((sbi->gc_mode == GC_URGENT) ? - 1 : wait_ms)); + msecs_to_jiffies(wait_ms)); if (dcc->discard_wake) dcc->discard_wake = 0; diff --git a/fs/f2fs/super.c b/fs/f2fs/super.c index bc989221f23f..356fa56835d9 100755 --- a/fs/f2fs/super.c +++ b/fs/f2fs/super.c @@ -1088,7 +1088,6 @@ static void f2fs_put_super(struct super_block *sb) * above failed with error. */ f2fs_destroy_stats(sbi); - f2fs_gc_sbi_list_del(sbi); /* destroy f2fs internal modules */ f2fs_destroy_node_manager(sbi); @@ -1436,6 +1435,7 @@ static void default_options(struct f2fs_sb_info *sbi) F2FS_OPTION(sbi).s_resuid = make_kuid(&init_user_ns, F2FS_DEF_RESUID); F2FS_OPTION(sbi).s_resgid = make_kgid(&init_user_ns, F2FS_DEF_RESGID); + set_opt(sbi, BG_GC); set_opt(sbi, INLINE_XATTR); set_opt(sbi, INLINE_DATA); set_opt(sbi, INLINE_DENTRY); @@ -3333,8 +3333,6 @@ static int f2fs_fill_super(struct super_block *sb, void *data, int silent) goto free_stats; } - f2fs_gc_sbi_list_add(sbi); - /* read root inode and dentry */ root = f2fs_iget(sb, F2FS_ROOT_INO(sbi)); if (IS_ERR(root)) { @@ -3487,7 +3485,6 @@ static int f2fs_fill_super(struct super_block *sb, void *data, int silent) iput(sbi->node_inode); sbi->node_inode = NULL; free_stats: - f2fs_gc_sbi_list_del(sbi); f2fs_destroy_stats(sbi); free_nm: f2fs_destroy_node_manager(sbi); @@ -3627,8 +3624,6 @@ static int __init init_f2fs_fs(void) err = f2fs_init_post_read_processing(); if (err) goto free_root_stats; - f2fs_init_rapid_gc(); - return 0; free_root_stats: @@ -3654,7 +3649,6 @@ static int __init init_f2fs_fs(void) static void __exit exit_f2fs_fs(void) { - f2fs_destroy_rapid_gc(); f2fs_destroy_post_read_processing(); f2fs_destroy_root_stats(); unregister_filesystem(&f2fs_fs_type); diff --git a/fs/f2fs/sysfs.c b/fs/f2fs/sysfs.c index 5af4ed2d068c..29b2f370cead 100644 --- a/fs/f2fs/sysfs.c +++ b/fs/f2fs/sysfs.c @@ -19,6 +19,7 @@ static struct proc_dir_entry *f2fs_proc_root; /* Sysfs support for f2fs */ enum { + GC_THREAD, /* struct f2fs_gc_thread */ SM_INFO, /* struct f2fs_sm_info */ DCC_INFO, /* struct discard_cmd_control */ NM_INFO, /* struct f2fs_nm_info */ @@ -42,7 +43,9 @@ struct f2fs_attr { static unsigned char *__struct_ptr(struct f2fs_sb_info *sbi, int struct_type) { - if (struct_type == SM_INFO) + if (struct_type == GC_THREAD) + return (unsigned char *)sbi->gc_thread; + else if (struct_type == SM_INFO) return (unsigned char *)SM_I(sbi); else if (struct_type == DCC_INFO) return (unsigned char *)SM_I(sbi)->dcc_info; @@ -267,6 +270,20 @@ static ssize_t __sbi_store(struct f2fs_attr *a, if (!strcmp(a->attr.name, "trim_sections")) return -EINVAL; + if (!strcmp(a->attr.name, "gc_urgent")) { + if (t >= 1) { + sbi->gc_mode = GC_URGENT; + if (sbi->gc_thread) { + sbi->gc_thread->gc_wake = 1; + wake_up_interruptible_all( + &sbi->gc_thread->gc_wait_queue_head); + wake_up_discard_thread(sbi, true); + } + } else { + sbi->gc_mode = GC_NORMAL; + } + return count; + } if (!strcmp(a->attr.name, "gc_idle")) { if (t == GC_IDLE_CB) sbi->gc_mode = GC_IDLE_CB; @@ -294,7 +311,19 @@ static ssize_t f2fs_sbi_store(struct f2fs_attr *a, struct f2fs_sb_info *sbi, const char *buf, size_t count) { - return __sbi_store(a, sbi, buf, count); + ssize_t ret; + bool gc_entry = (!strcmp(a->attr.name, "gc_urgent") || + a->struct_type == GC_THREAD); + + if (gc_entry) { + if (!down_read_trylock(&sbi->sb->s_umount)) + return -EAGAIN; + } + ret = __sbi_store(a, sbi, buf, count); + if (gc_entry) + up_read(&sbi->sb->s_umount); + + return ret; } static ssize_t f2fs_attr_show(struct kobject *kobj, @@ -382,6 +411,13 @@ static struct f2fs_attr f2fs_attr_##_name = { \ .id = _id, \ } +F2FS_RW_ATTR(GC_THREAD, f2fs_gc_kthread, gc_urgent_sleep_time, + urgent_sleep_time); +F2FS_RW_ATTR(GC_THREAD, f2fs_gc_kthread, gc_min_sleep_time, min_sleep_time); +F2FS_RW_ATTR(GC_THREAD, f2fs_gc_kthread, gc_max_sleep_time, max_sleep_time); +F2FS_RW_ATTR(GC_THREAD, f2fs_gc_kthread, gc_no_gc_sleep_time, no_gc_sleep_time); +F2FS_RW_ATTR(F2FS_SBI, f2fs_sb_info, gc_idle, gc_mode); +F2FS_RW_ATTR(F2FS_SBI, f2fs_sb_info, gc_urgent, gc_mode); F2FS_RW_ATTR(SM_INFO, f2fs_sm_info, reclaim_segments, rec_prefree_segments); F2FS_RW_ATTR(DCC_INFO, discard_cmd_control, max_small_discards, max_discards); F2FS_RW_ATTR(DCC_INFO, discard_cmd_control, discard_granularity, discard_granularity); @@ -403,6 +439,7 @@ F2FS_RW_ATTR(F2FS_SBI, f2fs_sb_info, cp_interval, interval_time[CP_TIME]); F2FS_RW_ATTR(F2FS_SBI, f2fs_sb_info, idle_interval, interval_time[REQ_TIME]); F2FS_RW_ATTR(F2FS_SBI, f2fs_sb_info, discard_idle_interval, interval_time[DISCARD_TIME]); +F2FS_RW_ATTR(F2FS_SBI, f2fs_sb_info, gc_idle_interval, interval_time[GC_TIME]); F2FS_RW_ATTR(F2FS_SBI, f2fs_sb_info, umount_discard_timeout, interval_time[UMOUNT_DISCARD_TIMEOUT]); F2FS_RW_ATTR(F2FS_SBI, f2fs_sb_info, iostat_enable, iostat_enable); @@ -437,6 +474,12 @@ F2FS_FEATURE_RO_ATTR(sb_checksum, FEAT_SB_CHECKSUM); #define ATTR_LIST(name) (&f2fs_attr_##name.attr) static struct attribute *f2fs_attrs[] = { + ATTR_LIST(gc_urgent_sleep_time), + ATTR_LIST(gc_min_sleep_time), + ATTR_LIST(gc_max_sleep_time), + ATTR_LIST(gc_no_gc_sleep_time), + ATTR_LIST(gc_idle), + ATTR_LIST(gc_urgent), ATTR_LIST(reclaim_segments), ATTR_LIST(max_small_discards), ATTR_LIST(discard_granularity), @@ -456,6 +499,7 @@ static struct attribute *f2fs_attrs[] = { ATTR_LIST(cp_interval), ATTR_LIST(idle_interval), ATTR_LIST(discard_idle_interval), + ATTR_LIST(gc_idle_interval), ATTR_LIST(umount_discard_timeout), ATTR_LIST(iostat_enable), ATTR_LIST(readdir_ra), @@ -659,7 +703,7 @@ int __init f2fs_init_sysfs(void) { int ret; - kobject_set_name(&f2fs_kset.kobj, "f2fs_dev"); + kobject_set_name(&f2fs_kset.kobj, "f2fs"); f2fs_kset.kobj.parent = fs_kobj; ret = kset_register(&f2fs_kset); if (ret) @@ -670,7 +714,7 @@ int __init f2fs_init_sysfs(void) if (ret) kset_unregister(&f2fs_kset); else - f2fs_proc_root = proc_mkdir("fs/f2fs_dev", NULL); + f2fs_proc_root = proc_mkdir("fs/f2fs", NULL); return ret; } @@ -678,7 +722,7 @@ void f2fs_exit_sysfs(void) { kobject_put(&f2fs_feat); kset_unregister(&f2fs_kset); - remove_proc_entry("fs/f2fs_dev", NULL); + remove_proc_entry("fs/f2fs", NULL); f2fs_proc_root = NULL; } diff --git a/fs/proc/cmdline.c b/fs/proc/cmdline.c index c8568498bfbf..cbd82dff7e81 100644 --- a/fs/proc/cmdline.c +++ b/fs/proc/cmdline.c @@ -2,13 +2,10 @@ #include #include #include -#include - -static char new_command_line[COMMAND_LINE_SIZE]; static int cmdline_proc_show(struct seq_file *m, void *v) { - seq_printf(m, "%s\n", new_command_line); + seq_printf(m, "%s\n", saved_command_line); return 0; } @@ -24,36 +21,8 @@ static const struct file_operations cmdline_proc_fops = { .release = single_release, }; -static void remove_flag(char *cmd, const char *flag) -{ - char *start_addr, *end_addr; - - /* Ensure all instances of a flag are removed */ - while ((start_addr = strstr(cmd, flag))) { - end_addr = strchr(start_addr, ' '); - if (end_addr) - memmove(start_addr, end_addr + 1, strlen(end_addr)); - else - *(max(cmd, start_addr - 1)) = '\0'; - } -} - -static void remove_safetynet_flags(char *cmd) -{ - remove_flag(cmd, "androidboot.verifiedbootstate="); - remove_flag(cmd, "androidboot.veritymode="); -} - static int __init proc_cmdline_init(void) { - strcpy(new_command_line, saved_command_line); - - /* - * Remove various flags from command line seen by userspace in order to - * pass SafetyNet CTS check. - */ - remove_safetynet_flags(new_command_line); - proc_create("cmdline", 0, NULL, &cmdline_proc_fops); return 0; } diff --git a/fs/sync.c b/fs/sync.c index 40d0285b98d6..b3faa068c9df 100644 --- a/fs/sync.c +++ b/fs/sync.c @@ -196,7 +196,6 @@ int vfs_fsync_range(struct file *file, loff_t start, loff_t end, int datasync) if (!fsync_enabled) return 0; - if (!file->f_op->fsync) return -EINVAL; if (!datasync && (inode->i_state & I_DIRTY_TIME)) { diff --git a/include/crypto/acompress.h b/include/crypto/acompress.h deleted file mode 100644 index e328b52425a8..000000000000 --- a/include/crypto/acompress.h +++ /dev/null @@ -1,269 +0,0 @@ -/* - * Asynchronous Compression operations - * - * Copyright (c) 2016, Intel Corporation - * Authors: Weigang Li - * Giovanni Cabiddu - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) - * any later version. - * - */ -#ifndef _CRYPTO_ACOMP_H -#define _CRYPTO_ACOMP_H -#include - -#define CRYPTO_ACOMP_ALLOC_OUTPUT 0x00000001 - -/** - * struct acomp_req - asynchronous (de)compression request - * - * @base: Common attributes for asynchronous crypto requests - * @src: Source Data - * @dst: Destination data - * @slen: Size of the input buffer - * @dlen: Size of the output buffer and number of bytes produced - * @flags: Internal flags - * @__ctx: Start of private context data - */ -struct acomp_req { - struct crypto_async_request base; - struct scatterlist *src; - struct scatterlist *dst; - unsigned int slen; - unsigned int dlen; - u32 flags; - void *__ctx[] CRYPTO_MINALIGN_ATTR; -}; - -/** - * struct crypto_acomp - user-instantiated objects which encapsulate - * algorithms and core processing logic - * - * @compress: Function performs a compress operation - * @decompress: Function performs a de-compress operation - * @dst_free: Frees destination buffer if allocated inside the - * algorithm - * @reqsize: Context size for (de)compression requests - * @base: Common crypto API algorithm data structure - */ -struct crypto_acomp { - int (*compress)(struct acomp_req *req); - int (*decompress)(struct acomp_req *req); - void (*dst_free)(struct scatterlist *dst); - unsigned int reqsize; - struct crypto_tfm base; -}; - -/** - * struct acomp_alg - asynchronous compression algorithm - * - * @compress: Function performs a compress operation - * @decompress: Function performs a de-compress operation - * @dst_free: Frees destination buffer if allocated inside the algorithm - * @init: Initialize the cryptographic transformation object. - * This function is used to initialize the cryptographic - * transformation object. This function is called only once at - * the instantiation time, right after the transformation context - * was allocated. In case the cryptographic hardware has some - * special requirements which need to be handled by software, this - * function shall check for the precise requirement of the - * transformation and put any software fallbacks in place. - * @exit: Deinitialize the cryptographic transformation object. This is a - * counterpart to @init, used to remove various changes set in - * @init. - * - * @reqsize: Context size for (de)compression requests - * @base: Common crypto API algorithm data structure - */ -struct acomp_alg { - int (*compress)(struct acomp_req *req); - int (*decompress)(struct acomp_req *req); - void (*dst_free)(struct scatterlist *dst); - int (*init)(struct crypto_acomp *tfm); - void (*exit)(struct crypto_acomp *tfm); - unsigned int reqsize; - struct crypto_alg base; -}; - -/** - * DOC: Asynchronous Compression API - * - * The Asynchronous Compression API is used with the algorithms of type - * CRYPTO_ALG_TYPE_ACOMPRESS (listed as type "acomp" in /proc/crypto) - */ - -/** - * crypto_alloc_acomp() -- allocate ACOMPRESS tfm handle - * @alg_name: is the cra_name / name or cra_driver_name / driver name of the - * compression algorithm e.g. "deflate" - * @type: specifies the type of the algorithm - * @mask: specifies the mask for the algorithm - * - * Allocate a handle for a compression algorithm. The returned struct - * crypto_acomp is the handle that is required for any subsequent - * API invocation for the compression operations. - * - * Return: allocated handle in case of success; IS_ERR() is true in case - * of an error, PTR_ERR() returns the error code. - */ -struct crypto_acomp *crypto_alloc_acomp(const char *alg_name, u32 type, - u32 mask); - -static inline struct crypto_tfm *crypto_acomp_tfm(struct crypto_acomp *tfm) -{ - return &tfm->base; -} - -static inline struct acomp_alg *__crypto_acomp_alg(struct crypto_alg *alg) -{ - return container_of(alg, struct acomp_alg, base); -} - -static inline struct crypto_acomp *__crypto_acomp_tfm(struct crypto_tfm *tfm) -{ - return container_of(tfm, struct crypto_acomp, base); -} - -static inline struct acomp_alg *crypto_acomp_alg(struct crypto_acomp *tfm) -{ - return __crypto_acomp_alg(crypto_acomp_tfm(tfm)->__crt_alg); -} - -static inline unsigned int crypto_acomp_reqsize(struct crypto_acomp *tfm) -{ - return tfm->reqsize; -} - -static inline void acomp_request_set_tfm(struct acomp_req *req, - struct crypto_acomp *tfm) -{ - req->base.tfm = crypto_acomp_tfm(tfm); -} - -static inline struct crypto_acomp *crypto_acomp_reqtfm(struct acomp_req *req) -{ - return __crypto_acomp_tfm(req->base.tfm); -} - -/** - * crypto_free_acomp() -- free ACOMPRESS tfm handle - * - * @tfm: ACOMPRESS tfm handle allocated with crypto_alloc_acomp() - */ -static inline void crypto_free_acomp(struct crypto_acomp *tfm) -{ - crypto_destroy_tfm(tfm, crypto_acomp_tfm(tfm)); -} - -static inline int crypto_has_acomp(const char *alg_name, u32 type, u32 mask) -{ - type &= ~CRYPTO_ALG_TYPE_MASK; - type |= CRYPTO_ALG_TYPE_ACOMPRESS; - mask |= CRYPTO_ALG_TYPE_MASK; - - return crypto_has_alg(alg_name, type, mask); -} - -/** - * acomp_request_alloc() -- allocates asynchronous (de)compression request - * - * @tfm: ACOMPRESS tfm handle allocated with crypto_alloc_acomp() - * - * Return: allocated handle in case of success or NULL in case of an error - */ -struct acomp_req *acomp_request_alloc(struct crypto_acomp *tfm); - -/** - * acomp_request_free() -- zeroize and free asynchronous (de)compression - * request as well as the output buffer if allocated - * inside the algorithm - * - * @req: request to free - */ -void acomp_request_free(struct acomp_req *req); - -/** - * acomp_request_set_callback() -- Sets an asynchronous callback - * - * Callback will be called when an asynchronous operation on a given - * request is finished. - * - * @req: request that the callback will be set for - * @flgs: specify for instance if the operation may backlog - * @cmlp: callback which will be called - * @data: private data used by the caller - */ -static inline void acomp_request_set_callback(struct acomp_req *req, - u32 flgs, - crypto_completion_t cmpl, - void *data) -{ - req->base.complete = cmpl; - req->base.data = data; - req->base.flags = flgs; -} - -/** - * acomp_request_set_params() -- Sets request parameters - * - * Sets parameters required by an acomp operation - * - * @req: asynchronous compress request - * @src: pointer to input buffer scatterlist - * @dst: pointer to output buffer scatterlist. If this is NULL, the - * acomp layer will allocate the output memory - * @slen: size of the input buffer - * @dlen: size of the output buffer. If dst is NULL, this can be used by - * the user to specify the maximum amount of memory to allocate - */ -static inline void acomp_request_set_params(struct acomp_req *req, - struct scatterlist *src, - struct scatterlist *dst, - unsigned int slen, - unsigned int dlen) -{ - req->src = src; - req->dst = dst; - req->slen = slen; - req->dlen = dlen; - - if (!req->dst) - req->flags |= CRYPTO_ACOMP_ALLOC_OUTPUT; -} - -/** - * crypto_acomp_compress() -- Invoke asynchronous compress operation - * - * Function invokes the asynchronous compress operation - * - * @req: asynchronous compress request - * - * Return: zero on success; error code in case of error - */ -static inline int crypto_acomp_compress(struct acomp_req *req) -{ - struct crypto_acomp *tfm = crypto_acomp_reqtfm(req); - - return tfm->compress(req); -} - -/** - * crypto_acomp_decompress() -- Invoke asynchronous decompress operation - * - * Function invokes the asynchronous decompress operation - * - * @req: asynchronous compress request - * - * Return: zero on success; error code in case of error - */ -static inline int crypto_acomp_decompress(struct acomp_req *req) -{ - struct crypto_acomp *tfm = crypto_acomp_reqtfm(req); - - return tfm->decompress(req); -} - -#endif diff --git a/include/crypto/internal/acompress.h b/include/crypto/internal/acompress.h deleted file mode 100644 index 1de2b5af12d7..000000000000 --- a/include/crypto/internal/acompress.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Asynchronous Compression operations - * - * Copyright (c) 2016, Intel Corporation - * Authors: Weigang Li - * Giovanni Cabiddu - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) - * any later version. - * - */ -#ifndef _CRYPTO_ACOMP_INT_H -#define _CRYPTO_ACOMP_INT_H -#include - -/* - * Transform internal helpers. - */ -static inline void *acomp_request_ctx(struct acomp_req *req) -{ - return req->__ctx; -} - -static inline void *acomp_tfm_ctx(struct crypto_acomp *tfm) -{ - return tfm->base.__crt_ctx; -} - -static inline void acomp_request_complete(struct acomp_req *req, - int err) -{ - req->base.complete(&req->base, err); -} - -static inline const char *acomp_alg_name(struct crypto_acomp *tfm) -{ - return crypto_acomp_tfm(tfm)->__crt_alg->cra_name; -} - -static inline struct acomp_req *__acomp_request_alloc(struct crypto_acomp *tfm) -{ - struct acomp_req *req; - - req = kzalloc(sizeof(*req) + crypto_acomp_reqsize(tfm), GFP_KERNEL); - if (likely(req)) - acomp_request_set_tfm(req, tfm); - return req; -} - -static inline void __acomp_request_free(struct acomp_req *req) -{ - kzfree(req); -} - -/** - * crypto_register_acomp() -- Register asynchronous compression algorithm - * - * Function registers an implementation of an asynchronous - * compression algorithm - * - * @alg: algorithm definition - * - * Return: zero on success; error code in case of error - */ -int crypto_register_acomp(struct acomp_alg *alg); - -/** - * crypto_unregister_acomp() -- Unregister asynchronous compression algorithm - * - * Function unregisters an implementation of an asynchronous - * compression algorithm - * - * @alg: algorithm definition - * - * Return: zero on success; error code in case of error - */ -int crypto_unregister_acomp(struct acomp_alg *alg); - -#endif diff --git a/include/crypto/internal/scompress.h b/include/crypto/internal/scompress.h deleted file mode 100644 index 3fda3c5655a0..000000000000 --- a/include/crypto/internal/scompress.h +++ /dev/null @@ -1,136 +0,0 @@ -/* - * Synchronous Compression operations - * - * Copyright 2015 LG Electronics Inc. - * Copyright (c) 2016, Intel Corporation - * Author: Giovanni Cabiddu - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the Free - * Software Foundation; either version 2 of the License, or (at your option) - * any later version. - * - */ -#ifndef _CRYPTO_SCOMP_INT_H -#define _CRYPTO_SCOMP_INT_H -#include - -#define SCOMP_SCRATCH_SIZE 131072 - -struct crypto_scomp { - struct crypto_tfm base; -}; - -/** - * struct scomp_alg - synchronous compression algorithm - * - * @alloc_ctx: Function allocates algorithm specific context - * @free_ctx: Function frees context allocated with alloc_ctx - * @compress: Function performs a compress operation - * @decompress: Function performs a de-compress operation - * @init: Initialize the cryptographic transformation object. - * This function is used to initialize the cryptographic - * transformation object. This function is called only once at - * the instantiation time, right after the transformation context - * was allocated. In case the cryptographic hardware has some - * special requirements which need to be handled by software, this - * function shall check for the precise requirement of the - * transformation and put any software fallbacks in place. - * @exit: Deinitialize the cryptographic transformation object. This is a - * counterpart to @init, used to remove various changes set in - * @init. - * @base: Common crypto API algorithm data structure - */ -struct scomp_alg { - void *(*alloc_ctx)(struct crypto_scomp *tfm); - void (*free_ctx)(struct crypto_scomp *tfm, void *ctx); - int (*compress)(struct crypto_scomp *tfm, const u8 *src, - unsigned int slen, u8 *dst, unsigned int *dlen, - void *ctx); - int (*decompress)(struct crypto_scomp *tfm, const u8 *src, - unsigned int slen, u8 *dst, unsigned int *dlen, - void *ctx); - struct crypto_alg base; -}; - -static inline struct scomp_alg *__crypto_scomp_alg(struct crypto_alg *alg) -{ - return container_of(alg, struct scomp_alg, base); -} - -static inline struct crypto_scomp *__crypto_scomp_tfm(struct crypto_tfm *tfm) -{ - return container_of(tfm, struct crypto_scomp, base); -} - -static inline struct crypto_tfm *crypto_scomp_tfm(struct crypto_scomp *tfm) -{ - return &tfm->base; -} - -static inline void crypto_free_scomp(struct crypto_scomp *tfm) -{ - crypto_destroy_tfm(tfm, crypto_scomp_tfm(tfm)); -} - -static inline struct scomp_alg *crypto_scomp_alg(struct crypto_scomp *tfm) -{ - return __crypto_scomp_alg(crypto_scomp_tfm(tfm)->__crt_alg); -} - -static inline void *crypto_scomp_alloc_ctx(struct crypto_scomp *tfm) -{ - return crypto_scomp_alg(tfm)->alloc_ctx(tfm); -} - -static inline void crypto_scomp_free_ctx(struct crypto_scomp *tfm, - void *ctx) -{ - return crypto_scomp_alg(tfm)->free_ctx(tfm, ctx); -} - -static inline int crypto_scomp_compress(struct crypto_scomp *tfm, - const u8 *src, unsigned int slen, - u8 *dst, unsigned int *dlen, void *ctx) -{ - return crypto_scomp_alg(tfm)->compress(tfm, src, slen, dst, dlen, ctx); -} - -static inline int crypto_scomp_decompress(struct crypto_scomp *tfm, - const u8 *src, unsigned int slen, - u8 *dst, unsigned int *dlen, - void *ctx) -{ - return crypto_scomp_alg(tfm)->decompress(tfm, src, slen, dst, dlen, - ctx); -} - -int crypto_init_scomp_ops_async(struct crypto_tfm *tfm); -struct acomp_req *crypto_acomp_scomp_alloc_ctx(struct acomp_req *req); -void crypto_acomp_scomp_free_ctx(struct acomp_req *req); - -/** - * crypto_register_scomp() -- Register synchronous compression algorithm - * - * Function registers an implementation of a synchronous - * compression algorithm - * - * @alg: algorithm definition - * - * Return: zero on success; error code in case of error - */ -int crypto_register_scomp(struct scomp_alg *alg); - -/** - * crypto_unregister_scomp() -- Unregister synchronous compression algorithm - * - * Function unregisters an implementation of a synchronous - * compression algorithm - * - * @alg: algorithm definition - * - * Return: zero on success; error code in case of error - */ -int crypto_unregister_scomp(struct scomp_alg *alg); - -#endif diff --git a/include/dsp/apr_elliptic.h b/include/dsp/apr_elliptic.h deleted file mode 100644 index 6aafb4600331..000000000000 --- a/include/dsp/apr_elliptic.h +++ /dev/null @@ -1,47 +0,0 @@ -#pragma once - -#include -#include -#include -#include - -#define ELLIPTIC_SET_PARAMS_SIZE 115 -#define ELLIPTIC_ULTRASOUND_MODULE_TX 0x0F010201 -#define ELLIPTIC_ULTRASOUND_MODULE_RX 0x0FF10202 -#define ULTRASOUND_OPCODE 0x0FF10204 - -/* This need to be updated for all platforms */ -#define ELLIPTIC_PORT_ID SLIMBUS_2_TX - -/** Sequence of Elliptic Labs Ultrasound module parameters */ -struct afe_ultrasound_set_params_t { - uint32_t payload[ELLIPTIC_SET_PARAMS_SIZE]; -} __packed; - -struct afe_ultrasound_config_command { - struct apr_hdr hdr; - struct afe_port_cmd_set_param_v2 param; - struct afe_port_param_data_v2 pdata; - struct afe_ultrasound_set_params_t prot_config; -} __packed; - -/** Sequence of Elliptic Labs Ultrasound module parameters */ - -/** Elliptic APR public */ - -int32_t ultrasound_apr_set_parameter(int32_t port_id, uint32_t param_id, - u8 *user_params, int32_t length); - -int32_t elliptic_process_apr_payload(uint32_t *payload); - -int elliptic_notify_gain_change_msg(int component_id, int gaindb); - -typedef struct afe_ultrasound_state { - void **ptr_apr; - atomic_t *ptr_status; - atomic_t *ptr_state; - wait_queue_head_t *ptr_wait; - int timeout_ms; -} afe_ultrasound_state_t; - -extern afe_ultrasound_state_t elus_afe; diff --git a/include/elliptic/elliptic_data_io.h b/include/elliptic/elliptic_data_io.h deleted file mode 100644 index db087b1cae21..000000000000 --- a/include/elliptic/elliptic_data_io.h +++ /dev/null @@ -1,156 +0,0 @@ -/** -* Copyright Elliptic Labs 2015-2016 -* Copyright (C) 2019 XiaoMi, Inc. -* -*/ - -#pragma once - -#include -#include -#include -#include -#include -#include -#include - -#define ELLIPTIC_DATA_IO_AP_TO_DSP 0 -#define ELLIPTIC_DATA_IO_DSP_TO_AP 1 - -#define ELLIPTIC_DATA_IO_READ_OK 0 -#define ELLIPTIC_DATA_IO_READ_BUSY 1 -#define ELLIPTIC_DATA_IO_READ_CANCEL 2 - -#define ELLIPTIC_MSG_BUF_SIZE 512 - -/* wake source timeout in ms*/ -#define ELLIPTIC_WAKEUP_TIMEOUT 250 - -#define ELLIPTIC_DATA_FIFO_SIZE (PAGE_SIZE) - -#define ULTRASOUND_RX_PORT_ID 0 -#define ULTRASOUND_TX_PORT_ID 1 - -/* Elliptic Labs UltraSound Module */ -#define ELLIPTIC_ULTRASOUND_DISABLE 0 -#define ELLIPTIC_ULTRASOUND_ENABLE 1 -#define ELLIPTIC_ULTRASOUND_SET_PARAMS 2 -#define ELLIPTIC_ULTRASOUND_GET_PARAMS 3 -#define ELLIPTIC_ULTRASOUND_RAMP_DOWN 4 - -/** Param ID definition */ -#define ELLIPTIC_ULTRASOUND_PARAM_ID_ENGINE_DATA 3 -#define ELLIPTIC_ULTRASOUND_PARAM_ID_CALIBRATION_DATA 11 -#define ELLIPTIC_ULTRASOUND_PARAM_ID_ENGINE_VERSION 12 -#define ELLIPTIC_ULTRASOUND_PARAM_ID_BUILD_BRANCH 14 -#define ELLIPTIC_ULTRASOUND_PARAM_ID_CALIBRATION_V2_DATA 15 -#define ELLIPTIC_ULTRASOUND_PARAM_ID_SENSORHUB 16 -#define ELLIPTIC_ULTRASOUND_PARAM_ID_DIAGNOSTICS_DATA 17 -#define ELLIPTIC_ULTRASOUND_PARAM_ID_TAG 18 -#define ELLIPTIC_ULTRASOUND_PARAM_ID_ML_DATA 19 - -#define ELLIPTIC_DATA_READ_BUSY 0 -#define ELLIPTIC_DATA_READ_OK 1 -#define ELLIPTIC_DATA_READ_CANCEL 2 - -#define ELLIPTIC_ALL_DEVICES -1 -#define ELLIPTIC_DEVICE_0 0 -#define ELLIPTIC_DEVICE_1 1 - -enum elliptic_message_id { - ELLIPTIC_MESSAGE_PAYLOAD, /* Input to AP*/ - ELLIPTIC_MESSAGE_RAW, /* Output from AP*/ - ELLIPTIC_MESSAGE_CALIBRATION, - ELLIPTIC_MESSAGE_CALIBRATION_V2, - ELLIPTIC_MESSAGE_DIAGNOSTICS, - ELLIPTIC_MAX_MESSAGE_IDS -}; - -typedef enum { - ELLIPTIC_DATA_PUSH_FROM_KERNEL, - ELLIPTIC_DATA_PUSH_FROM_USERSPACE -} elliptic_data_push_t; - -struct elliptic_data { - /* wake lock timeout */ - unsigned int wakeup_timeout; - - /* members for top half interrupt handling */ - struct kfifo fifo_isr; - spinlock_t fifo_isr_spinlock; - wait_queue_head_t fifo_isr_not_empty; - struct mutex user_buffer_lock; - - /* buffer to swap data from isr fifo to userspace */ - uint8_t isr_swap_buffer[ELLIPTIC_MSG_BUF_SIZE]; - - atomic_t abort_io; - - /* debug counters, reset between open/close */ - uint32_t isr_fifo_discard; - - /* debug counters, persistent */ - uint32_t isr_fifo_discard_total; - uint32_t userspace_read_total; - uint32_t isr_write_total; - -}; - -/* Elliptic IO module API (implemented by IO module)*/ - -int elliptic_data_io_initialize(void); -int elliptic_data_io_cleanup(void); - -int32_t elliptic_data_io_write(uint32_t message_id, const char *data, - size_t data_size); - -int32_t elliptic_data_io_transact(uint32_t message_id, const char *data, - size_t data_size, char *output_data, size_t output_data_size); - - -/* Elliptic driver API (implemented by main driver)*/ -int elliptic_data_initialize(struct elliptic_data *, - size_t max_queue_size, unsigned int wakeup_timeout, int id); - -int elliptic_data_cleanup(struct elliptic_data *); - -void elliptic_data_reset_debug_counters(struct elliptic_data *); -void elliptic_data_update_debug_counters(struct elliptic_data *); -void elliptic_data_print_debug_counters(struct elliptic_data *); - -/* Called from elliptic device read */ -size_t elliptic_data_pop(struct elliptic_data *, - char __user *buffer, size_t buffer_size); - -/* Used for cancelling a blocking read */ -void elliptic_data_cancel(struct elliptic_data *); - -/* Called from IO module*/ -int elliptic_data_push(int deviceid, const char *buffer, size_t buffer_size, elliptic_data_push_t); - -/* Writes to io module and user space control */ -int32_t elliptic_data_write(uint32_t message_id, - const char *data, size_t data_size); - -/* Opens port */ -int elliptic_open_port(int portid); - -/* Closes port */ -int elliptic_close_port(int portid); - -/* Opens port */ -int elliptic_io_open_port(int portid); - -/* Closes port */ -int elliptic_io_close_port(int portid); - -/* Create device node for userspace io driver*/ -int elliptic_userspace_io_driver_init(void); -void elliptic_userspace_io_driver_exit(void); - -/* Create device node for userspace io driver*/ -int elliptic_userspace_ctrl_driver_init(void); -void elliptic_userspace_ctrl_driver_exit(void); -int32_t elliptic_userspace_ctrl_write(uint32_t message_id, - const char *data, size_t data_size); - diff --git a/include/elliptic/elliptic_mixer_controls.h b/include/elliptic/elliptic_mixer_controls.h deleted file mode 100644 index 9d2cef302ff0..000000000000 --- a/include/elliptic/elliptic_mixer_controls.h +++ /dev/null @@ -1,180 +0,0 @@ -#pragma once -#include -#include -#include -#include - - -#define ELLIPTIC_OBJ_ID_CALIBRATION_DATA 1 -#define ELLIPTIC_OBJ_ID_VERSION_INFO 2 -#define ELLIPTIC_OBJ_ID_BRANCH_INFO 3 -#define ELLIPTIC_OBJ_ID_CALIBRATION_V2_DATA 4 -#define ELLIPTIC_OBJ_ID_DIAGNOSTICS_DATA 5 -#define ELLIPTIC_OBJ_ID_TAG_INFO 6 -#define ELLIPTIC_OBJ_ID_ML_DATA 7 - -#define ELLIPTIC_SYSTEM_CONFIGURATION_SIZE 96 -#define ELLIPTIC_CALIBRATION_DATA_SIZE 64 -#define ELLIPTIC_CALIBRATION_V2_DATA_SIZE 448 -#define ELLIPTIC_DIAGNOSTICS_DATA_SIZE 448 -#define ELLIPTIC_DIAGNOSTICS_U32_DATA_VALUES (ELLIPTIC_DIAGNOSTICS_DATA_SIZE>>2) -#define ELLIPTIC_VERSION_INFO_SIZE 16 -#define ELLIPTIC_BRANCH_INFO_SIZE 32 -#define ELLIPTIC_BRANCH_INFO_MAX_SIZE 128 -#define ELLIPTIC_TAG_INFO_SIZE 32 -#define ELLIPTIC_ML_DATA_SIZE 432 - -#define ELLIPTIC_ULTRASOUND_DISABLE 0 -#define ELLIPTIC_ULTRASOUND_ENABLE 1 -#define ELLIPTIC_ULTRASOUND_SET_PARAMS 2 -#define ELLIPTIC_ULTRASOUND_GET_PARAMS 3 -#define ELLIPTIC_ULTRASOUND_RAMP_DOWN 4 - -/** register */ -#define ELLIPTIC_CALIBRATION 1 -/** bits */ -#define ELLIPTIC_CALIBRATION_STATE 0 -#define ELLIPTIC_CALIBRATION_PROFILE 1 -#define ELLIPTIC_ULTRASOUND_GAIN 2 - -/** custom settings */ -#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_COUNT 16 -#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_MAX_VALUE 0x7FFFFFFF - - -/** register */ -#define ELLIPTIC_SYSTEM_CONFIGURATION 0 -/** bits */ -#define ELLIPTIC_SYSTEM_CONFIGURATION_LATENCY 0 -#define ELLIPTIC_SYSTEM_CONFIGURATION_SENSITIVITY 1 -#define ELLIPTIC_SYSTEM_CONFIGURATION_SPEAKER_SCALING 2 -#define ELLIPTIC_SYSTEM_CONFIGURATION_MICROPHONE_INDEX 3 -#define ELLIPTIC_SYSTEM_CONFIGURATION_OPERATION_MODE 4 -#define ELLIPTIC_SYSTEM_CONFIGURATION_OPERATION_MODE_FLAGS 5 -#define ELLIPTIC_SYSTEM_CONFIGURATION_LOG_LEVEL 6 -#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_0 7 -#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_1 8 -#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_2 9 -#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_3 10 -#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_4 11 -#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_5 12 -#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_6 13 -#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_7 14 -#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_8 15 -#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_9 16 -#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_10 17 -#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_11 18 -#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_12 19 -#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_13 20 -#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_14 21 -#define ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_15 22 - -#define ELLIPTIC_SYSTEM_CONFIGURATION_SUSPEND 23 -#define ELLIPTIC_SYSTEM_CONFIGURATION_INPUT_ENABLED 24 -#define ELLIPTIC_SYSTEM_CONFIGURATION_OUTPUT_ENABLED 25 -#define ELLIPTIC_SYSTEM_CONFIGURATION_EXTERNAL_EVENT 26 -#define ELLIPTIC_SYSTEM_CONFIGURATION_CALIBRATION_METHOD 27 -#define ELLIPTIC_SYSTEM_CONFIGURATION_DEBUG_MODE 28 -#define ELLIPTIC_SYSTEM_CONFIGURATION_NUMBER_OF_RUNS 29 -#define ELLIPTIC_SYSTEM_CONFIGURATION_CONTEXT 30 - -#define ELLIPTIC_SYSTEM_CONFIGURATION_MAX_CONTEXT_VALUE 0x7FFFFFFF - - -struct elliptic_engine_version_info { - uint32_t major; - uint32_t minor; - uint32_t build; - uint32_t revision; -}; - -struct elliptic_shared_data_block { - uint32_t object_id; - size_t size; - void *buffer; -}; - -struct elliptic_shared_data_block *elliptic_get_shared_obj(uint32_t - object_id); - -unsigned int elliptic_add_platform_controls(void *platform); - -void elliptic_set_calibration_data(uint8_t *calib_data, size_t size); - -enum elliptic_system_configuration_parameter_type { - - ESCPT_SPEAKER_SCALING = 1, - ESCPT_CHANNEL_SENSITIVITY, - ESCPT_LATENCY, - ESCPT_MICROPHONE_INDEX, - ESCPT_OPERATION_MODE, - ESCPT_OPERATION_MODE_FLAGS, - ESCPT_COMPONENT_GAIN_CHANGE, - ESCPT_CALIBRATION_STATE, - ESCPT_ENGINE_VERSION, - ESCPT_CALIBRATION_PROFILE, - ESCPT_ULTRASOUND_GAIN, - ESCPT_LOG_LEVEL, - ESCPT_BUILD_BRANCH, //13 - - ESCPT_FSELECTION, - ESCPT_ENGINE_DIAGNOSTICS, - ESCPT_ENGINE_CUSTOM_SETTING_0, - ESCPT_ENGINE_CUSTOM_SETTING_1, - ESCPT_ENGINE_CUSTOM_SETTING_2, - ESCPT_ENGINE_CUSTOM_SETTING_3, - ESCPT_ENGINE_CUSTOM_SETTING_4, - ESCPT_ENGINE_CUSTOM_SETTING_5, - ESCPT_ENGINE_CUSTOM_SETTING_6, - ESCPT_ENGINE_CUSTOM_SETTING_7, - ESCPT_ENGINE_CUSTOM_SETTING_8, - ESCPT_ENGINE_CUSTOM_SETTING_9, - ESCPT_ENGINE_CUSTOM_SETTING_10, - ESCPT_ENGINE_CUSTOM_SETTING_11, - ESCPT_ENGINE_CUSTOM_SETTING_12, - ESCPT_ENGINE_CUSTOM_SETTING_13, - ESCPT_ENGINE_CUSTOM_SETTING_14, - ESCPT_ENGINE_CUSTOM_SETTING_15, - ESCPT_SUSPEND, // 32 - ESCPT_INPUT_ENABLED, - ESCPT_OUTPUT_ENABLED, - ESCPT_EXTERNAL_EVENT, - ESCPT_ENGINE_TAG, //36 - ESCPT_CALIBRATION_METHOD, - ESCPT_DEBUG_MODE, - ESCPT_NUMBER_OF_RUNS, - ESCPT_CONTEXT, -}; - -struct elliptic_system_configuration_parameters_cache { - int32_t speaker_scaling[2]; - int32_t sensitivity; - int32_t latency; - int32_t microphone_index; - int32_t operation_mode; - int32_t operation_mode_flags; - int32_t component_gain_change; - int32_t calibration_state; - int32_t engine_version; - int32_t calibration_profile; - int32_t ultrasound_gain; - int32_t log_level; - int32_t custom_settings[ELLIPTIC_SYSTEM_CONFIGURATION_CUSTOM_SETTING_COUNT]; - int32_t engine_suspend; - int32_t input_enabled; - int32_t output_enabled; - int32_t external_event; - int32_t calibration_method; - int32_t debug_mode; - int32_t number_of_runs; - int32_t context; -}; - - -int elliptic_trigger_version_msg(void); - -int elliptic_trigger_branch_msg(void); - -int elliptic_trigger_tag_msg(void); - -int elliptic_trigger_diagnostics_msg(void); diff --git a/include/linux/backlight.h b/include/linux/backlight.h index 6c4d9046a3e7..d5ff4c30f233 100644 --- a/include/linux/backlight.h +++ b/include/linux/backlight.h @@ -44,12 +44,6 @@ enum backlight_type { enum backlight_notification { BACKLIGHT_REGISTERED, BACKLIGHT_UNREGISTERED, - BACKLIGHT_UPDATED, -}; - -enum backlight_brightness { - BACKLIGHT_OFF, - BACKLIGHT_ON, }; struct backlight_device; @@ -74,7 +68,6 @@ struct backlight_ops { struct backlight_properties { /* Current User requested brightness (0 - max_brightness) */ int brightness; - int brightness_clone; /* Maximal value for brightness (read-only) */ int max_brightness; /* Current FB Power mode (0: full on, 1..3: power saving diff --git a/include/linux/crypto.h b/include/linux/crypto.h index 0fb74874b354..81339e184ae7 100644 --- a/include/linux/crypto.h +++ b/include/linux/crypto.h @@ -51,8 +51,6 @@ #define CRYPTO_ALG_TYPE_SKCIPHER 0x00000005 #define CRYPTO_ALG_TYPE_GIVCIPHER 0x00000006 #define CRYPTO_ALG_TYPE_KPP 0x00000008 -#define CRYPTO_ALG_TYPE_ACOMPRESS 0x0000000a -#define CRYPTO_ALG_TYPE_SCOMPRESS 0x0000000b #define CRYPTO_ALG_TYPE_RNG 0x0000000c #define CRYPTO_ALG_TYPE_AKCIPHER 0x0000000d #define CRYPTO_ALG_TYPE_DIGEST 0x0000000e @@ -63,7 +61,6 @@ #define CRYPTO_ALG_TYPE_HASH_MASK 0x0000000e #define CRYPTO_ALG_TYPE_AHASH_MASK 0x0000000e #define CRYPTO_ALG_TYPE_BLKCIPHER_MASK 0x0000000c -#define CRYPTO_ALG_TYPE_ACOMPRESS_MASK 0x0000000e #define CRYPTO_ALG_LARVAL 0x00000010 #define CRYPTO_ALG_DEAD 0x00000020 diff --git a/include/linux/device.h b/include/linux/device.h index efc4955264a9..5ab43f42b0c0 100644 --- a/include/linux/device.h +++ b/include/linux/device.h @@ -861,9 +861,6 @@ struct device { bool offline_disabled:1; bool offline:1; - - struct list_head iommu_map_list; - struct mutex iommu_map_lock; }; static inline struct device *kobj_to_dev(struct kobject *kobj) diff --git a/include/linux/hrtimer.h b/include/linux/hrtimer.h index 9523c6030ffe..2869fb1f85a5 100644 --- a/include/linux/hrtimer.h +++ b/include/linux/hrtimer.h @@ -419,12 +419,18 @@ extern u64 hrtimer_get_next_event(void); extern bool hrtimer_active(const struct hrtimer *timer); -/* - * Helper function to check, whether the timer is on one of the queues +/** + * hrtimer_is_queued = check, whether the timer is on one of the queues + * @timer: Timer to check + * + * Returns: True if the timer is queued, false otherwise + * + * The function can be used lockless, but it gives only a current snapshot. */ -static inline int hrtimer_is_queued(struct hrtimer *timer) +static inline bool hrtimer_is_queued(struct hrtimer *timer) { - return timer->state & HRTIMER_STATE_ENQUEUED; + /* The READ_ONCE pairs with the update functions of timer->state */ + return !!(READ_ONCE(timer->state) & HRTIMER_STATE_ENQUEUED); } /* diff --git a/include/linux/input/ft5x46_ts.h b/include/linux/input/ft5x46_ts.h index 49c399fd35fa..df04e0b97af2 100644 --- a/include/linux/input/ft5x46_ts.h +++ b/include/linux/input/ft5x46_ts.h @@ -144,12 +144,6 @@ struct ft5x46_data { int touchs; int keys; - int dbclick_count; -#ifdef CONFIG_TOUCHSCREEN_XIAOMI_TOUCHFEATURE_SENSOR - bool palm_enabled; - bool palm_sensor_changed; - struct class *tp_class; -#endif #ifdef CONFIG_DRM struct notifier_block drm_notifier; #endif diff --git a/include/linux/input/synaptics_dsx_force.h b/include/linux/input/synaptics_dsx_force.h index 9ea2a976fe56..b8466f754209 100644 --- a/include/linux/input/synaptics_dsx_force.h +++ b/include/linux/input/synaptics_dsx_force.h @@ -116,7 +116,6 @@ struct synaptics_dsx_config_info { const char *chip_id_name; unsigned char *tp_ids; const char *fw_name; - const char *clicknum_file_name; struct synaptics_dsx_panel_power_seq panel_power_seq; struct synaptics_dsx_factory_param *factory_param; }; @@ -186,9 +185,6 @@ struct synaptics_dsx_board_data { unsigned int reset_active_ms; unsigned int byte_delay_us; unsigned int block_delay_us; - unsigned int palm_rx_channel; - unsigned int palm_rx_area; - unsigned int palm_tx_disable; bool cut_off_power; bool power_ctrl; bool panel_is_incell; diff --git a/include/linux/lz4.h b/include/linux/lz4.h index 1b0f8ca0f9c8..6b784c59f321 100644 --- a/include/linux/lz4.h +++ b/include/linux/lz4.h @@ -1,717 +1,87 @@ -/* LZ4 Kernel Interface +#ifndef __LZ4_H__ +#define __LZ4_H__ +/* + * LZ4 Kernel Interface * * Copyright (C) 2013, LG Electronics, Kyungsik Lee - * Copyright (C) 2016, Sven Schmidt <4sschmid@informatik.uni-hamburg.de> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. - * - * This file is based on the original header file - * for LZ4 - Fast LZ compression algorithm. - * - * LZ4 - Fast LZ compression algorithm - * Copyright (C) 2011-2016, Yann Collet. - * BSD 2-Clause License (http://www.opensource.org/licenses/bsd-license.php) - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following disclaimer - * in the documentation and/or other materials provided with the - * distribution. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * You can contact the author at : - * - LZ4 homepage : http://www.lz4.org - * - LZ4 source repository : https://github.com/lz4/lz4 */ +#define LZ4_MEM_COMPRESS (16384) +#define LZ4HC_MEM_COMPRESS (262144 + (2 * sizeof(unsigned char *))) -#ifndef __LZ4_H__ -#define __LZ4_H__ - -#include -#include /* memset, memcpy */ - -/*-************************************************************************ - * CONSTANTS - **************************************************************************/ /* - * LZ4_MEMORY_USAGE : - * Memory usage formula : N->2^N Bytes - * (examples : 10 -> 1KB; 12 -> 4KB ; 16 -> 64KB; 20 -> 1MB; etc.) - * Increasing memory usage improves compression ratio - * Reduced memory usage can improve speed, due to cache effect - * Default value is 14, for 16KB, which nicely fits into Intel x86 L1 cache + * lz4_compressbound() + * Provides the maximum size that LZ4 may output in a "worst case" scenario + * (input data not compressible) */ -#define LZ4_MEMORY_USAGE 14 - -#define LZ4_MAX_INPUT_SIZE 0x7E000000 /* 2 113 929 216 bytes */ -#define LZ4_COMPRESSBOUND(isize) (\ - (unsigned int)(isize) > (unsigned int)LZ4_MAX_INPUT_SIZE \ - ? 0 \ - : (isize) + ((isize)/255) + 16) - -#define LZ4_ACCELERATION_DEFAULT 1 -#define LZ4_HASHLOG (LZ4_MEMORY_USAGE-2) -#define LZ4_HASHTABLESIZE (1 << LZ4_MEMORY_USAGE) -#define LZ4_HASH_SIZE_U32 (1 << LZ4_HASHLOG) - -#define LZ4HC_MIN_CLEVEL 3 -#define LZ4HC_DEFAULT_CLEVEL 9 -#define LZ4HC_MAX_CLEVEL 16 - -#define LZ4HC_DICTIONARY_LOGSIZE 16 -#define LZ4HC_MAXD (1<= LZ4_compressBound(inputSize). - * It also runs faster, so it's a recommended setting. - * If the function cannot compress 'source' into a more limited 'dest' budget, - * compression stops *immediately*, and the function result is zero. - * As a consequence, 'dest' content is not valid. - * - * Return: Number of bytes written into buffer 'dest' - * (necessarily <= maxOutputSize) or 0 if compression fails - */ -int LZ4_compress_default(const char *source, char *dest, int inputSize, - int maxOutputSize, void *wrkmem); - -/** - * LZ4_compress_fast() - As LZ4_compress_default providing an acceleration param - * @source: source address of the original data - * @dest: output buffer address of the compressed data - * @inputSize: size of the input data. Max supported value is LZ4_MAX_INPUT_SIZE - * @maxOutputSize: full or partial size of buffer 'dest' - * which must be already allocated - * @acceleration: acceleration factor - * @wrkmem: address of the working memory. - * This requires 'workmem' of LZ4_MEM_COMPRESS. - * - * Same as LZ4_compress_default(), but allows to select an "acceleration" - * factor. The larger the acceleration value, the faster the algorithm, - * but also the lesser the compression. It's a trade-off. It can be fine tuned, - * with each successive value providing roughly +~3% to speed. - * An acceleration value of "1" is the same as regular LZ4_compress_default() - * Values <= 0 will be replaced by LZ4_ACCELERATION_DEFAULT, which is 1. - * - * Return: Number of bytes written into buffer 'dest' - * (necessarily <= maxOutputSize) or 0 if compression fails - */ -int LZ4_compress_fast(const char *source, char *dest, int inputSize, - int maxOutputSize, int acceleration, void *wrkmem); - -/** - * LZ4_compress_destSize() - Compress as much data as possible - * from source to dest - * @source: source address of the original data - * @dest: output buffer address of the compressed data - * @sourceSizePtr: will be modified to indicate how many bytes where read - * from 'source' to fill 'dest'. New value is necessarily <= old value. - * @targetDestSize: Size of buffer 'dest' which must be already allocated - * @wrkmem: address of the working memory. - * This requires 'workmem' of LZ4_MEM_COMPRESS. - * - * Reverse the logic, by compressing as much data as possible - * from 'source' buffer into already allocated buffer 'dest' - * of size 'targetDestSize'. - * This function either compresses the entire 'source' content into 'dest' - * if it's large enough, or fill 'dest' buffer completely with as much data as - * possible from 'source'. - * - * Return: Number of bytes written into 'dest' (necessarily <= targetDestSize) - * or 0 if compression fails - */ -int LZ4_compress_destSize(const char *source, char *dest, int *sourceSizePtr, - int targetDestSize, void *wrkmem); - /* - * lz4_compress() - For backward compatibility, see LZ4_compress_default - * @src: source address of the original data - * @src_len: size of the original data - * @dst: output buffer address of the compressed data. This requires 'dst' - * of size LZ4_COMPRESSBOUND - * @dst_len: is the output size, which is returned after compress done - * @workmem: address of the working memory. - * - * Return: Success if return 0, Error if return < 0 - */ -int lz4_compress(const unsigned char *src, size_t src_len, unsigned char *dst, - size_t *dst_len, void *wrkmem); - -/*-************************************************************************ - * Decompression Functions - **************************************************************************/ - -/** - * LZ4_decompress_fast() - Decompresses data from 'source' into 'dest' - * @source: source address of the compressed data - * @dest: output buffer address of the uncompressed data - * which must be already allocated with 'originalSize' bytes - * @originalSize: is the original and therefore uncompressed size - * - * Decompresses data from 'source' into 'dest'. - * This function fully respect memory boundaries for properly formed - * compressed data. - * It is a bit faster than LZ4_decompress_safe(). - * However, it does not provide any protection against intentionally - * modified data stream (malicious input). - * Use this function in trusted environment only - * (data to decode comes from a trusted source). - * - * Return: number of bytes read from the source buffer - * or a negative result if decompression fails. - */ -int LZ4_decompress_fast(const char *source, char *dest, int originalSize); - -/** - * LZ4_decompress_safe() - Decompression protected against buffer overflow - * @source: source address of the compressed data - * @dest: output buffer address of the uncompressed data - * which must be already allocated - * @compressedSize: is the precise full size of the compressed block - * @maxDecompressedSize: is the size of 'dest' buffer - * - * Decompresses data fom 'source' into 'dest'. - * If the source stream is detected malformed, the function will - * stop decoding and return a negative result. - * This function is protected against buffer overflow exploits, - * including malicious data packets. It never writes outside output buffer, - * nor reads outside input buffer. - * - * Return: number of bytes decompressed into destination buffer - * (necessarily <= maxDecompressedSize) - * or a negative result in case of error - */ -int LZ4_decompress_safe(const char *source, char *dest, int compressedSize, - int maxDecompressedSize); - -/** - * LZ4_decompress_safe_partial() - Decompress a block of size 'compressedSize' - * at position 'source' into buffer 'dest' - * @source: source address of the compressed data - * @dest: output buffer address of the decompressed data which must be - * already allocated - * @compressedSize: is the precise full size of the compressed block. - * @targetOutputSize: the decompression operation will try - * to stop as soon as 'targetOutputSize' has been reached - * @maxDecompressedSize: is the size of destination buffer - * - * This function decompresses a compressed block of size 'compressedSize' - * at position 'source' into destination buffer 'dest' - * of size 'maxDecompressedSize'. - * The function tries to stop decompressing operation as soon as - * 'targetOutputSize' has been reached, reducing decompression time. - * This function never writes outside of output buffer, - * and never reads outside of input buffer. - * It is therefore protected against malicious data packets. - * - * Return: the number of bytes decoded in the destination buffer - * (necessarily <= maxDecompressedSize) - * or a negative result in case of error - * - */ -int LZ4_decompress_safe_partial(const char *source, char *dest, - int compressedSize, int targetOutputSize, int maxDecompressedSize); + * lz4_compress() + * src : source address of the original data + * src_len : size of the original data + * dst : output buffer address of the compressed data + * This requires 'dst' of size LZ4_COMPRESSBOUND. + * dst_len : is the output size, which is returned after compress done + * workmem : address of the working memory. + * This requires 'workmem' of size LZ4_MEM_COMPRESS. + * return : Success if return 0 + * Error if return (< 0) + * note : Destination buffer and workmem must be already allocated with + * the defined size. + */ +int lz4_compress(const unsigned char *src, size_t src_len, + unsigned char *dst, size_t *dst_len, void *wrkmem); + + /* + * lz4hc_compress() + * src : source address of the original data + * src_len : size of the original data + * dst : output buffer address of the compressed data + * This requires 'dst' of size LZ4_COMPRESSBOUND. + * dst_len : is the output size, which is returned after compress done + * workmem : address of the working memory. + * This requires 'workmem' of size LZ4HC_MEM_COMPRESS. + * return : Success if return 0 + * Error if return (< 0) + * note : Destination buffer and workmem must be already allocated with + * the defined size. + */ +int lz4hc_compress(const unsigned char *src, size_t src_len, + unsigned char *dst, size_t *dst_len, void *wrkmem); /* - * lz4_decompress_unknownoutputsize() - For backwards compatibility, - * see LZ4_decompress_safe - * @src: source address of the compressed data - * @src_len: is the input size, therefore the compressed size - * @dest: output buffer address of the decompressed data - * which must be already allocated - * @dest_len: is the max size of the destination buffer, which is - * returned with actual size of decompressed data after decompress done - * - * Return: Success if return 0, Error if return (< 0) - */ -int lz4_decompress_unknownoutputsize(const unsigned char *src, size_t src_len, - unsigned char *dest, size_t *dest_len); - -/** - * lz4_decompress() - For backwards cocmpatibility, see LZ4_decompress_fast - * @src: source address of the compressed data - * @src_len: is the input size, which is returned after decompress done - * @dest: output buffer address of the decompressed data, - * which must be already allocated - * @actual_dest_len: is the size of uncompressed data, supposing it's known - * - * Return: Success if return 0, Error if return (< 0) + * lz4_decompress() + * src : source address of the compressed data + * src_len : is the input size, whcih is returned after decompress done + * dest : output buffer address of the decompressed data + * actual_dest_len: is the size of uncompressed data, supposing it's known + * return : Success if return 0 + * Error if return (< 0) + * note : Destination buffer must be already allocated. + * slightly faster than lz4_decompress_unknownoutputsize() */ int lz4_decompress(const unsigned char *src, size_t *src_len, - unsigned char *dest, size_t actual_dest_len); - -/*-************************************************************************ - * LZ4 HC Compression - **************************************************************************/ - -/** - * LZ4_compress_HC() - Compress data from `src` into `dst`, using HC algorithm - * @src: source address of the original data - * @dst: output buffer address of the compressed data - * @srcSize: size of the input data. Max supported value is LZ4_MAX_INPUT_SIZE - * @dstCapacity: full or partial size of buffer 'dst', - * which must be already allocated - * @compressionLevel: Recommended values are between 4 and 9, although any - * value between 1 and LZ4HC_MAX_CLEVEL will work. - * Values >LZ4HC_MAX_CLEVEL behave the same as 16. - * @wrkmem: address of the working memory. - * This requires 'wrkmem' of size LZ4HC_MEM_COMPRESS. - * - * Compress data from 'src' into 'dst', using the more powerful - * but slower "HC" algorithm. Compression is guaranteed to succeed if - * `dstCapacity >= LZ4_compressBound(srcSize) - * - * Return : the number of bytes written into 'dst' or 0 if compression fails. - */ -int LZ4_compress_HC(const char *src, char *dst, int srcSize, int dstCapacity, - int compressionLevel, void *wrkmem); - -/** - * lz4hc_compress() - For backwards compatibility, see LZ4_compress_HC - * @src: source address of the original data - * @src_len: size of the original data - * @dst: output buffer address of the compressed data. This requires 'dst' - * of size LZ4_COMPRESSBOUND. - * @dst_len: is the output size, which is returned after compress done - * @wrkmem: address of the working memory. - * This requires 'workmem' of size LZ4HC_MEM_COMPRESS. - * - * Return : Success if return 0, Error if return (< 0) - */ -int lz4hc_compress(const unsigned char *src, size_t src_len, unsigned char *dst, - size_t *dst_len, void *wrkmem); - -/** - * LZ4_resetStreamHC() - Init an allocated 'LZ4_streamHC_t' structure - * @streamHCPtr: pointer to the 'LZ4_streamHC_t' structure - * @compressionLevel: Recommended values are between 4 and 9, although any - * value between 1 and LZ4HC_MAX_CLEVEL will work. - * Values >LZ4HC_MAX_CLEVEL behave the same as 16. - * - * An LZ4_streamHC_t structure can be allocated once - * and re-used multiple times. - * Use this function to init an allocated `LZ4_streamHC_t` structure - * and start a new compression. - */ -void LZ4_resetStreamHC(LZ4_streamHC_t *streamHCPtr, int compressionLevel); - -/** - * LZ4_loadDictHC() - Load a static dictionary into LZ4_streamHC - * @streamHCPtr: pointer to the LZ4HC_stream_t - * @dictionary: dictionary to load - * @dictSize: size of dictionary - * - * Use this function to load a static dictionary into LZ4HC_stream. - * Any previous data will be forgotten, only 'dictionary' - * will remain in memory. - * Loading a size of 0 is allowed. - * - * Return : dictionary size, in bytes (necessarily <= 64 KB) - */ -int LZ4_loadDictHC(LZ4_streamHC_t *streamHCPtr, const char *dictionary, - int dictSize); - -/** - * LZ4_compress_HC_continue() - Compress 'src' using data from previously - * compressed blocks as a dictionary using the HC algorithm - * @streamHCPtr: Pointer to the previous 'LZ4_streamHC_t' structure - * @src: source address of the original data - * @dst: output buffer address of the compressed data, - * which must be already allocated - * @srcSize: size of the input data. Max supported value is LZ4_MAX_INPUT_SIZE - * @maxDstSize: full or partial size of buffer 'dest' - * which must be already allocated - * - * These functions compress data in successive blocks of any size, using - * previous blocks as dictionary. One key assumption is that previous - * blocks (up to 64 KB) remain read-accessible while - * compressing next blocks. There is an exception for ring buffers, - * which can be smaller than 64 KB. - * Ring buffers scenario is automatically detected and handled by - * LZ4_compress_HC_continue(). - * Before starting compression, state must be properly initialized, - * using LZ4_resetStreamHC(). - * A first "fictional block" can then be designated as - * initial dictionary, using LZ4_loadDictHC() (Optional). - * Then, use LZ4_compress_HC_continue() - * to compress each successive block. Previous memory blocks - * (including initial dictionary when present) must remain accessible - * and unmodified during compression. - * 'dst' buffer should be sized to handle worst case scenarios, using - * LZ4_compressBound(), to ensure operation success. - * If, for any reason, previous data blocks can't be preserved unmodified - * in memory during next compression block, - * you must save it to a safer memory space, using LZ4_saveDictHC(). - * Return value of LZ4_saveDictHC() is the size of dictionary - * effectively saved into 'safeBuffer'. - * - * Return: Number of bytes written into buffer 'dst' or 0 if compression fails - */ -int LZ4_compress_HC_continue(LZ4_streamHC_t *streamHCPtr, const char *src, - char *dst, int srcSize, int maxDstSize); - -/** - * LZ4_saveDictHC() - Save static dictionary from LZ4HC_stream - * @streamHCPtr: pointer to the 'LZ4HC_stream_t' structure - * @safeBuffer: buffer to save dictionary to, must be already allocated - * @maxDictSize: size of 'safeBuffer' - * - * If previously compressed data block is not guaranteed - * to remain available at its memory location, - * save it into a safer place (char *safeBuffer). - * Note : you don't need to call LZ4_loadDictHC() afterwards, - * dictionary is immediately usable, you can therefore call - * LZ4_compress_HC_continue(). - * - * Return : saved dictionary size in bytes (necessarily <= maxDictSize), - * or 0 if error. - */ -int LZ4_saveDictHC(LZ4_streamHC_t *streamHCPtr, char *safeBuffer, - int maxDictSize); - -/*-********************************************* - * Streaming Compression Functions - ***********************************************/ - -/** - * LZ4_resetStream() - Init an allocated 'LZ4_stream_t' structure - * @LZ4_stream: pointer to the 'LZ4_stream_t' structure - * - * An LZ4_stream_t structure can be allocated once - * and re-used multiple times. - * Use this function to init an allocated `LZ4_stream_t` structure - * and start a new compression. - */ -void LZ4_resetStream(LZ4_stream_t *LZ4_stream); - -/** - * LZ4_loadDict() - Load a static dictionary into LZ4_stream - * @streamPtr: pointer to the LZ4_stream_t - * @dictionary: dictionary to load - * @dictSize: size of dictionary - * - * Use this function to load a static dictionary into LZ4_stream. - * Any previous data will be forgotten, only 'dictionary' - * will remain in memory. - * Loading a size of 0 is allowed. - * - * Return : dictionary size, in bytes (necessarily <= 64 KB) - */ -int LZ4_loadDict(LZ4_stream_t *streamPtr, const char *dictionary, - int dictSize); - -/** - * LZ4_saveDict() - Save static dictionary from LZ4_stream - * @streamPtr: pointer to the 'LZ4_stream_t' structure - * @safeBuffer: buffer to save dictionary to, must be already allocated - * @dictSize: size of 'safeBuffer' - * - * If previously compressed data block is not guaranteed - * to remain available at its memory location, - * save it into a safer place (char *safeBuffer). - * Note : you don't need to call LZ4_loadDict() afterwards, - * dictionary is immediately usable, you can therefore call - * LZ4_compress_fast_continue(). - * - * Return : saved dictionary size in bytes (necessarily <= dictSize), - * or 0 if error. - */ -int LZ4_saveDict(LZ4_stream_t *streamPtr, char *safeBuffer, int dictSize); - -/** - * LZ4_compress_fast_continue() - Compress 'src' using data from previously - * compressed blocks as a dictionary - * @streamPtr: Pointer to the previous 'LZ4_stream_t' structure - * @src: source address of the original data - * @dst: output buffer address of the compressed data, - * which must be already allocated - * @srcSize: size of the input data. Max supported value is LZ4_MAX_INPUT_SIZE - * @maxDstSize: full or partial size of buffer 'dest' - * which must be already allocated - * @acceleration: acceleration factor - * - * Compress buffer content 'src', using data from previously compressed blocks - * as dictionary to improve compression ratio. - * Important : Previous data blocks are assumed to still - * be present and unmodified ! - * If maxDstSize >= LZ4_compressBound(srcSize), - * compression is guaranteed to succeed, and runs faster. - * - * Return: Number of bytes written into buffer 'dst' or 0 if compression fails - */ -int LZ4_compress_fast_continue(LZ4_stream_t *streamPtr, const char *src, - char *dst, int srcSize, int maxDstSize, int acceleration); - -/** - * LZ4_setStreamDecode() - Instruct where to find dictionary - * @LZ4_streamDecode: the 'LZ4_streamDecode_t' structure - * @dictionary: dictionary to use - * @dictSize: size of dictionary - * - * Use this function to instruct where to find the dictionary. - * Setting a size of 0 is allowed (same effect as reset). - * - * Return: 1 if OK, 0 if error - */ -int LZ4_setStreamDecode(LZ4_streamDecode_t *LZ4_streamDecode, - const char *dictionary, int dictSize); - -/** - * LZ4_decompress_fast_continue() - Decompress blocks in streaming mode - * @LZ4_streamDecode: the 'LZ4_streamDecode_t' structure - * @source: source address of the compressed data - * @dest: output buffer address of the uncompressed data - * which must be already allocated - * @compressedSize: is the precise full size of the compressed block - * @maxDecompressedSize: is the size of 'dest' buffer - * - * These decoding function allows decompression of multiple blocks - * in "streaming" mode. - * Previously decoded blocks *must* remain available at the memory position - * where they were decoded (up to 64 KB) - * In the case of a ring buffers, decoding buffer must be either : - * - Exactly same size as encoding buffer, with same update rule - * (block boundaries at same positions) In which case, - * the decoding & encoding ring buffer can have any size, - * including very small ones ( < 64 KB). - * - Larger than encoding buffer, by a minimum of maxBlockSize more bytes. - * maxBlockSize is implementation dependent. - * It's the maximum size you intend to compress into a single block. - * In which case, encoding and decoding buffers do not need - * to be synchronized, and encoding ring buffer can have any size, - * including small ones ( < 64 KB). - * - _At least_ 64 KB + 8 bytes + maxBlockSize. - * In which case, encoding and decoding buffers do not need to be - * synchronized, and encoding ring buffer can have any size, - * including larger than decoding buffer. W - * Whenever these conditions are not possible, save the last 64KB of decoded - * data into a safe buffer, and indicate where it is saved - * using LZ4_setStreamDecode() - * - * Return: number of bytes decompressed into destination buffer - * (necessarily <= maxDecompressedSize) - * or a negative result in case of error - */ -int LZ4_decompress_safe_continue(LZ4_streamDecode_t *LZ4_streamDecode, - const char *source, char *dest, int compressedSize, - int maxDecompressedSize); - -/** - * LZ4_decompress_fast_continue() - Decompress blocks in streaming mode - * @LZ4_streamDecode: the 'LZ4_streamDecode_t' structure - * @source: source address of the compressed data - * @dest: output buffer address of the uncompressed data - * which must be already allocated with 'originalSize' bytes - * @originalSize: is the original and therefore uncompressed size - * - * These decoding function allows decompression of multiple blocks - * in "streaming" mode. - * Previously decoded blocks *must* remain available at the memory position - * where they were decoded (up to 64 KB) - * In the case of a ring buffers, decoding buffer must be either : - * - Exactly same size as encoding buffer, with same update rule - * (block boundaries at same positions) In which case, - * the decoding & encoding ring buffer can have any size, - * including very small ones ( < 64 KB). - * - Larger than encoding buffer, by a minimum of maxBlockSize more bytes. - * maxBlockSize is implementation dependent. - * It's the maximum size you intend to compress into a single block. - * In which case, encoding and decoding buffers do not need - * to be synchronized, and encoding ring buffer can have any size, - * including small ones ( < 64 KB). - * - _At least_ 64 KB + 8 bytes + maxBlockSize. - * In which case, encoding and decoding buffers do not need to be - * synchronized, and encoding ring buffer can have any size, - * including larger than decoding buffer. W - * Whenever these conditions are not possible, save the last 64KB of decoded - * data into a safe buffer, and indicate where it is saved - * using LZ4_setStreamDecode() - * - * Return: number of bytes decompressed into destination buffer - * (necessarily <= maxDecompressedSize) - * or a negative result in case of error - */ -int LZ4_decompress_fast_continue(LZ4_streamDecode_t *LZ4_streamDecode, - const char *source, char *dest, int originalSize); - -/** - * LZ4_decompress_safe_usingDict() - Same as LZ4_setStreamDecode() - * followed by LZ4_decompress_safe_continue() - * @source: source address of the compressed data - * @dest: output buffer address of the uncompressed data - * which must be already allocated - * @compressedSize: is the precise full size of the compressed block - * @maxDecompressedSize: is the size of 'dest' buffer - * @dictStart: pointer to the start of the dictionary in memory - * @dictSize: size of dictionary - * - * These decoding function works the same as - * a combination of LZ4_setStreamDecode() followed by - * LZ4_decompress_safe_continue() - * It is stand-alone, and don'tn eed a LZ4_streamDecode_t structure. - * - * Return: number of bytes decompressed into destination buffer - * (necessarily <= maxDecompressedSize) - * or a negative result in case of error - */ -int LZ4_decompress_safe_usingDict(const char *source, char *dest, - int compressedSize, int maxDecompressedSize, const char *dictStart, - int dictSize); + unsigned char *dest, size_t actual_dest_len); -/** - * LZ4_decompress_fast_usingDict() - Same as LZ4_setStreamDecode() - * followed by LZ4_decompress_fast_continue() - * @source: source address of the compressed data - * @dest: output buffer address of the uncompressed data - * which must be already allocated with 'originalSize' bytes - * @originalSize: is the original and therefore uncompressed size - * @dictStart: pointer to the start of the dictionary in memory - * @dictSize: size of dictionary - * - * These decoding function works the same as - * a combination of LZ4_setStreamDecode() followed by - * LZ4_decompress_safe_continue() - * It is stand-alone, and don'tn eed a LZ4_streamDecode_t structure. - * - * Return: number of bytes decompressed into destination buffer - * (necessarily <= maxDecompressedSize) - * or a negative result in case of error +/* + * lz4_decompress_unknownoutputsize() + * src : source address of the compressed data + * src_len : is the input size, therefore the compressed size + * dest : output buffer address of the decompressed data + * dest_len: is the max size of the destination buffer, which is + * returned with actual size of decompressed data after + * decompress done + * return : Success if return 0 + * Error if return (< 0) + * note : Destination buffer must be already allocated. */ -int LZ4_decompress_fast_usingDict(const char *source, char *dest, - int originalSize, const char *dictStart, int dictSize); - +int lz4_decompress_unknownoutputsize(const unsigned char *src, size_t src_len, + unsigned char *dest, size_t *dest_len); #endif diff --git a/include/linux/mm.h b/include/linux/mm.h index b8f1d4337614..cbb1c054909f 100644 --- a/include/linux/mm.h +++ b/include/linux/mm.h @@ -2486,7 +2486,6 @@ extern int sysctl_drop_caches; int drop_caches_sysctl_handler(struct ctl_table *, int, void __user *, size_t *, loff_t *); #endif -void mm_drop_caches(int val); void drop_slab(void); void drop_slab_node(int nid); diff --git a/include/linux/msm_dma_iommu_mapping.h b/include/linux/msm_dma_iommu_mapping.h index f09dc48ac9e5..44dabb1809f2 100644 --- a/include/linux/msm_dma_iommu_mapping.h +++ b/include/linux/msm_dma_iommu_mapping.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2015-2016, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -18,11 +18,6 @@ #include #include -struct msm_iommu_data { - struct list_head map_list; - struct mutex lock; -}; - #ifdef CONFIG_QCOM_LAZY_MAPPING /* * This function is not taking a reference to the dma_buf here. It is expected @@ -30,37 +25,52 @@ struct msm_iommu_data { * and unmapping. */ int msm_dma_map_sg_attrs(struct device *dev, struct scatterlist *sg, int nents, - enum dma_data_direction dir, struct dma_buf *dmabuf, + enum dma_data_direction dir, struct dma_buf *dma_buf, unsigned long attrs); +/* + * This function takes an extra reference to the dma_buf. + * What this means is that calling msm_dma_unmap_sg will not result in buffer's + * iommu mapping being removed, which means that subsequent calls to lazy map + * will simply re-use the existing iommu mapping. + * The iommu unmapping of the buffer will occur when the ION buffer is + * destroyed. + * Using lazy mapping can provide a performance benefit because subsequent + * mappings are faster. + * + * The limitation of using this API are that all subsequent iommu mappings + * must be the same as the original mapping, ie they must map the same part of + * the buffer with the same dma data direction. Also there can't be multiple + * mappings of different parts of the buffer. + */ static inline int msm_dma_map_sg_lazy(struct device *dev, struct scatterlist *sg, int nents, enum dma_data_direction dir, - struct dma_buf *dmabuf) + struct dma_buf *dma_buf) { - return msm_dma_map_sg_attrs(dev, sg, nents, dir, dmabuf, 0); + return msm_dma_map_sg_attrs(dev, sg, nents, dir, dma_buf, 0); } static inline int msm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, enum dma_data_direction dir, - struct dma_buf *dmabuf) + struct dma_buf *dma_buf) { unsigned long attrs; attrs = DMA_ATTR_NO_DELAYED_UNMAP; - return msm_dma_map_sg_attrs(dev, sg, nents, dir, dmabuf, attrs); + return msm_dma_map_sg_attrs(dev, sg, nents, dir, dma_buf, attrs); } -void msm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, - enum dma_data_direction dir, struct dma_buf *dmabuf); +void msm_dma_unmap_sg(struct device *dev, struct scatterlist *sgl, int nents, + enum dma_data_direction dir, struct dma_buf *dma_buf); -void msm_dma_unmap_all_for_dev(struct device *dev); +int msm_dma_unmap_all_for_dev(struct device *dev); /* * Below is private function only to be called by framework (ION) and not by * clients. */ -void msm_dma_buf_freed(struct msm_iommu_data *data); +void msm_dma_buf_freed(void *buffer); #else /*CONFIG_QCOM_LAZY_MAPPING*/ diff --git a/include/linux/msm_ep_pcie.h b/include/linux/msm_ep_pcie.h index 5c5e51f9d12b..a1d2a17820e0 100644 --- a/include/linux/msm_ep_pcie.h +++ b/include/linux/msm_ep_pcie.h @@ -1,4 +1,4 @@ -/* Copyright (c) 2015, 2017, 2019, The Linux Foundation. All rights reserved. +/* Copyright (c) 2015, 2017, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -112,7 +112,7 @@ struct ep_pcie_hw { u32 num_entries); int (*get_msi_config)(struct ep_pcie_msi_config *cfg); int (*trigger_msi)(u32 idx); - int (*wakeup_host)(enum ep_pcie_event event); + int (*wakeup_host)(void); int (*enable_endpoint)(enum ep_pcie_options opt); int (*disable_endpoint)(void); int (*config_db_routing)(struct ep_pcie_db_config chdb_cfg, @@ -230,13 +230,12 @@ int ep_pcie_trigger_msi(struct ep_pcie_hw *phandle, u32 idx); /* * ep_pcie_wakeup_host - wake up the host. * @phandle: PCIe endpoint HW driver handle - * @event: PCIe event of ep_pcie_event type * * This function asserts WAKE GPIO to wake up the host. * * Return: 0 on success, negative value on error */ -int ep_pcie_wakeup_host(struct ep_pcie_hw *phandle, enum ep_pcie_event event); +int ep_pcie_wakeup_host(struct ep_pcie_hw *phandle); /* * ep_pcie_enable_endpoint - enable PCIe endpoint. diff --git a/include/linux/msm_mhi_dev.h b/include/linux/msm_mhi_dev.h index 8d6afd9ded21..160568759990 100644 --- a/include/linux/msm_mhi_dev.h +++ b/include/linux/msm_mhi_dev.h @@ -172,7 +172,7 @@ int mhi_dev_open_channel(uint32_t chan_id, /** * mhi_dev_close_channel() - Channel close for a given client. */ -void mhi_dev_close_channel(struct mhi_dev_client *handle_client); +int mhi_dev_close_channel(struct mhi_dev_client *handle_client); /** * mhi_dev_read_channel() - Channel read for a given client diff --git a/include/linux/power_supply.h b/include/linux/power_supply.h index 1eccf25fe821..65e223d609e9 100644 --- a/include/linux/power_supply.h +++ b/include/linux/power_supply.h @@ -4,7 +4,7 @@ * Copyright © 2007 Anton Vorontsov * Copyright © 2004 Szabolcs Gyurko * Copyright © 2003 Ian Molton - * Copyright © 2019 XiaoMi, Inc. + * Copyright (C) 2018 XiaoMi, Inc. * * Modified: 2004, Oct Szabolcs Gyurko * @@ -277,14 +277,11 @@ enum power_supply_property { POWER_SUPPLY_PROP_CTM_CURRENT_MAX, POWER_SUPPLY_PROP_HW_CURRENT_MAX, POWER_SUPPLY_PROP_REAL_TYPE, - POWER_SUPPLY_PROP_HVDCP3_TYPE, - POWER_SUPPLY_PROP_QUICK_CHARGE_TYPE, POWER_SUPPLY_PROP_DC_ADAPTER, POWER_SUPPLY_PROP_PR_SWAP, POWER_SUPPLY_PROP_CC_STEP, POWER_SUPPLY_PROP_CC_STEP_SEL, POWER_SUPPLY_PROP_SW_JEITA_ENABLED, - POWER_SUPPLY_PROP_DYNAMIC_FV_ENABLED, POWER_SUPPLY_PROP_PD_VOLTAGE_MAX, POWER_SUPPLY_PROP_PD_VOLTAGE_MIN, POWER_SUPPLY_PROP_SDP_CURRENT_MAX, diff --git a/include/linux/sched/topology.h b/include/linux/sched/topology.h deleted file mode 100644 index 4f1159f76f92..000000000000 --- a/include/linux/sched/topology.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef _LINUX_SCHED_TOPOLOGY_H -#define _LINUX_SCHED_TOPOLOGY_H - -#include - -#endif /* _LINUX_SCHED_TOPOLOGY_H */ diff --git a/include/net/tcp.h b/include/net/tcp.h index 1b385c154f10..92a5e8396401 100644 --- a/include/net/tcp.h +++ b/include/net/tcp.h @@ -725,14 +725,11 @@ u32 __tcp_select_window(struct sock *sk); void tcp_send_window_probe(struct sock *sk); -/* TCP uses 32bit jiffies to save some space. - * Note that this is different from tcp_time_stamp, which - * historically has been the same until linux-4.13. - */ -#define tcp_jiffies32 ((u32)jiffies) - -/* Generator for TCP TS option (RFC 7323) - * Currently tied to 'jiffies' but will soon be driven by 1 ms clock. +/* TCP timestamps are only 32-bits, this causes a slight + * complication on 64-bit systems since we store a snapshot + * of jiffies in the buffer control blocks below. We decided + * to use only the low 32-bits of jiffies and hide the ugly + * casts with the following macro. */ #define tcp_time_stamp ((__u32)(jiffies)) diff --git a/include/sound/adsp_err.h b/include/sound/adsp_err.h deleted file mode 100644 index 68fd61e59633..000000000000 --- a/include/sound/adsp_err.h +++ /dev/null @@ -1,116 +0,0 @@ -/* - * Copyright (c) 2015, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef __ADSP_ERR__ -#define __ADSP_ERR__ - -#include -#include - - -/* ERROR STRING */ -/* Success. The operation completed with no errors. */ -#define ADSP_EOK_STR "ADSP_EOK" -/* General failure. */ -#define ADSP_EFAILED_STR "ADSP_EFAILED" -/* Bad operation parameter. */ -#define ADSP_EBADPARAM_STR "ADSP_EBADPARAM" -/* Unsupported routine or operation. */ -#define ADSP_EUNSUPPORTED_STR "ADSP_EUNSUPPORTED" -/* Unsupported version. */ -#define ADSP_EVERSION_STR "ADSP_EVERSION" -/* Unexpected problem encountered. */ -#define ADSP_EUNEXPECTED_STR "ADSP_EUNEXPECTED" -/* Unhandled problem occurred. */ -#define ADSP_EPANIC_STR "ADSP_EPANIC" -/* Unable to allocate resource. */ -#define ADSP_ENORESOURCE_STR "ADSP_ENORESOURCE" -/* Invalid handle. */ -#define ADSP_EHANDLE_STR "ADSP_EHANDLE" -/* Operation is already processed. */ -#define ADSP_EALREADY_STR "ADSP_EALREADY" -/* Operation is not ready to be processed. */ -#define ADSP_ENOTREADY_STR "ADSP_ENOTREADY" -/* Operation is pending completion. */ -#define ADSP_EPENDING_STR "ADSP_EPENDING" -/* Operation could not be accepted or processed. */ -#define ADSP_EBUSY_STR "ADSP_EBUSY" -/* Operation aborted due to an error. */ -#define ADSP_EABORTED_STR "ADSP_EABORTED" -/* Operation preempted by a higher priority. */ -#define ADSP_EPREEMPTED_STR "ADSP_EPREEMPTED" -/* Operation requests intervention to complete. */ -#define ADSP_ECONTINUE_STR "ADSP_ECONTINUE" -/* Operation requests immediate intervention to complete. */ -#define ADSP_EIMMEDIATE_STR "ADSP_EIMMEDIATE" -/* Operation is not implemented. */ -#define ADSP_ENOTIMPL_STR "ADSP_ENOTIMPL" -/* Operation needs more data or resources. */ -#define ADSP_ENEEDMORE_STR "ADSP_ENEEDMORE" -/* Operation does not have memory. */ -#define ADSP_ENOMEMORY_STR "ADSP_ENOMEMORY" -/* Item does not exist. */ -#define ADSP_ENOTEXIST_STR "ADSP_ENOTEXIST" -/* Unexpected error code. */ -#define ADSP_ERR_MAX_STR "ADSP_ERR_MAX" - - -struct adsp_err_code { - int lnx_err_code; - char *adsp_err_str; -}; - - -static struct adsp_err_code adsp_err_code_info[ADSP_ERR_MAX+1] = { - { 0, ADSP_EOK_STR}, - { -ENOTRECOVERABLE, ADSP_EFAILED_STR}, - { -EINVAL, ADSP_EBADPARAM_STR}, - { -ENOSYS, ADSP_EUNSUPPORTED_STR}, - { -ENOPROTOOPT, ADSP_EVERSION_STR}, - { -ENOTRECOVERABLE, ADSP_EUNEXPECTED_STR}, - { -ENOTRECOVERABLE, ADSP_EPANIC_STR}, - { -ENOSPC, ADSP_ENORESOURCE_STR}, - { -EBADR, ADSP_EHANDLE_STR}, - { -EALREADY, ADSP_EALREADY_STR}, - { -EPERM, ADSP_ENOTREADY_STR}, - { -EINPROGRESS, ADSP_EPENDING_STR}, - { -EBUSY, ADSP_EBUSY_STR}, - { -ECANCELED, ADSP_EABORTED_STR}, - { -EAGAIN, ADSP_EPREEMPTED_STR}, - { -EAGAIN, ADSP_ECONTINUE_STR}, - { -EAGAIN, ADSP_EIMMEDIATE_STR}, - { -EAGAIN, ADSP_ENOTIMPL_STR}, - { -ENODATA, ADSP_ENEEDMORE_STR}, - { -EADV, ADSP_ERR_MAX_STR}, - { -ENOMEM, ADSP_ENOMEMORY_STR}, - { -ENODEV, ADSP_ENOTEXIST_STR}, - { -EADV, ADSP_ERR_MAX_STR}, -}; - -static inline int adsp_err_get_lnx_err_code(u32 adsp_error) -{ - if (adsp_error > ADSP_ERR_MAX) - return adsp_err_code_info[ADSP_ERR_MAX].lnx_err_code; - else - return adsp_err_code_info[adsp_error].lnx_err_code; -} - -static inline char *adsp_err_get_err_str(u32 adsp_error) -{ - if (adsp_error > ADSP_ERR_MAX) - return adsp_err_code_info[ADSP_ERR_MAX].adsp_err_str; - else - return adsp_err_code_info[adsp_error].adsp_err_str; -} - -#endif diff --git a/include/sound/apr_audio-v2.h b/include/sound/apr_audio-v2.h deleted file mode 100644 index 89e9066e677b..000000000000 --- a/include/sound/apr_audio-v2.h +++ /dev/null @@ -1,7840 +0,0 @@ -/* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved. -* -* This program is free software; you can redistribute it and/or modify -* it under the terms of the GNU General Public License version 2 and -* only version 2 as published by the Free Software Foundation. -* -* This program is distributed in the hope that it will be useful, -* but WITHOUT ANY WARRANTY; without even the implied warranty of -* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -* GNU General Public License for more details. -*/ - - -#ifndef _APR_AUDIO_V2_H_ -#define _APR_AUDIO_V2_H_ - -#include - -/* size of header needed for passing data out of band */ -#define APR_CMD_OB_HDR_SZ 12 - -/* size of header needed for getting data */ -#define APR_CMD_GET_HDR_SZ 16 - -struct param_outband { - size_t size; - void *kvaddr; - phys_addr_t paddr; -}; - -#define ADSP_ADM_VERSION 0x00070000 - -#define ADM_CMD_SHARED_MEM_MAP_REGIONS 0x00010322 -#define ADM_CMDRSP_SHARED_MEM_MAP_REGIONS 0x00010323 -#define ADM_CMD_SHARED_MEM_UNMAP_REGIONS 0x00010324 - -#define ADM_CMD_MATRIX_MAP_ROUTINGS_V5 0x00010325 -#define ADM_CMD_STREAM_DEVICE_MAP_ROUTINGS_V5 0x0001033D -/* Enumeration for an audio Rx matrix ID.*/ -#define ADM_MATRIX_ID_AUDIO_RX 0 - -#define ADM_MATRIX_ID_AUDIO_TX 1 - -#define ADM_MATRIX_ID_COMPRESSED_AUDIO_RX 2 -/* Enumeration for an audio Tx matrix ID.*/ -#define ADM_MATRIX_ID_AUDIOX 1 - -#define ADM_MAX_COPPS 5 - -/* make sure this matches with msm_audio_calibration */ -#define SP_V2_NUM_MAX_SPKR 2 - -/* Session map node structure. -* Immediately following this structure are num_copps -* entries of COPP IDs. The COPP IDs are 16 bits, so -* there might be a padding 16-bit field if num_copps -* is odd. -*/ -struct adm_session_map_node_v5 { - u16 session_id; -/* Handle of the ASM session to be routed. Supported values: 1 -* to 8. -*/ - - - u16 num_copps; - /* Number of COPPs to which this session is to be routed. - Supported values: 0 < num_copps <= ADM_MAX_COPPS. - */ -} __packed; - -/* Payload of the #ADM_CMD_MATRIX_MAP_ROUTINGS_V5 command. -* Immediately following this structure are num_sessions of the session map -* node payload (adm_session_map_node_v5). -*/ - -struct adm_cmd_matrix_map_routings_v5 { - struct apr_hdr hdr; - - u32 matrix_id; -/* Specifies whether the matrix ID is Audio Rx (0) or Audio Tx -* (1). Use the ADM_MATRIX_ID_AUDIO_RX or ADM_MATRIX_ID_AUDIOX -* macros to set this field. -*/ - u32 num_sessions; - /* Number of sessions being updated by this command (optional).*/ -} __packed; - -/* This command allows a client to open a COPP/Voice Proc. TX module -* and sets up the device session: Matrix -> COPP -> AFE on the RX -* and AFE -> COPP -> Matrix on the TX. This enables PCM data to -* be transferred to/from the endpoint (AFEPortID). -* -* @return -* #ADM_CMDRSP_DEVICE_OPEN_V5 with the resulting status and -* COPP ID. -*/ -#define ADM_CMD_DEVICE_OPEN_V5 0x00010326 - -/* Definition for a low latency stream session. */ -#define ADM_LOW_LATENCY_DEVICE_SESSION 0x2000 - -/* Definition for a ultra low latency stream session. */ -#define ADM_ULTRA_LOW_LATENCY_DEVICE_SESSION 0x4000 - -/* Definition for a legacy device session. */ -#define ADM_LEGACY_DEVICE_SESSION 0 - -/* Indicates that endpoint_id_2 is to be ignored.*/ -#define ADM_CMD_COPP_OPEN_END_POINT_ID_2_IGNORE 0xFFFF - -#define ADM_CMD_COPP_OPEN_MODE_OF_OPERATION_RX_PATH_COPP 1 - -#define ADM_CMD_COPP_OPEN_MODE_OF_OPERATIONX_PATH_LIVE_COPP 2 - -#define ADM_CMD_COPP_OPEN_MODE_OF_OPERATIONX_PATH_NON_LIVE_COPP 3 - -/* Indicates that an audio COPP is to send/receive a mono PCM - * stream to/from - * END_POINT_ID_1. - */ -#define ADM_CMD_COPP_OPEN_CHANNEL_CONFIG_MONO 1 - -/* Indicates that an audio COPP is to send/receive a - * stereo PCM stream to/from END_POINT_ID_1. - */ -#define ADM_CMD_COPP_OPEN_CHANNEL_CONFIG_STEREO 2 - -/* Sample rate is 8000 Hz.*/ -#define ADM_CMD_COPP_OPEN_SAMPLE_RATE_8K 8000 - -/* Sample rate is 16000 Hz.*/ -#define ADM_CMD_COPP_OPEN_SAMPLE_RATE_16K 16000 - -/* Sample rate is 48000 Hz.*/ -#define ADM_CMD_COPP_OPEN_SAMPLE_RATE_48K 48000 - -/* Definition for a COPP live input flag bitmask.*/ -#define ADM_BIT_MASK_COPP_LIVE_INPUT_FLAG (0x0001U) - -/* Definition for a COPP live shift value bitmask.*/ -#define ADM_SHIFT_COPP_LIVE_INPUT_FLAG 0 - -/* Definition for the COPP ID bitmask.*/ -#define ADM_BIT_MASK_COPP_ID (0x0000FFFFUL) - -/* Definition for the COPP ID shift value.*/ -#define ADM_SHIFT_COPP_ID 0 - -/* Definition for the service ID bitmask.*/ -#define ADM_BIT_MASK_SERVICE_ID (0x00FF0000UL) - -/* Definition for the service ID shift value.*/ -#define ADM_SHIFT_SERVICE_ID 16 - -/* Definition for the domain ID bitmask.*/ -#define ADM_BIT_MASK_DOMAIN_ID (0xFF000000UL) - -/* Definition for the domain ID shift value.*/ -#define ADM_SHIFT_DOMAIN_ID 24 - -/* ADM device open command payload of the - #ADM_CMD_DEVICE_OPEN_V5 command. -*/ -struct adm_cmd_device_open_v5 { - struct apr_hdr hdr; - u16 flags; -/* Reserved for future use. Clients must set this field - * to zero. - */ - - u16 mode_of_operation; -/* Specifies whether the COPP must be opened on the Tx or Rx - * path. Use the ADM_CMD_COPP_OPEN_MODE_OF_OPERATION_* macros for - * supported values and interpretation. - * Supported values: - * - 0x1 -- Rx path COPP - * - 0x2 -- Tx path live COPP - * - 0x3 -- Tx path nonlive COPP - * Live connections cause sample discarding in the Tx device - * matrix if the destination output ports do not pull them - * fast enough. Nonlive connections queue the samples - * indefinitely. - */ - - u16 endpoint_id_1; -/* Logical and physical endpoint ID of the audio path. - * If the ID is a voice processor Tx block, it receives near - * samples. Supported values: Any pseudoport, AFE Rx port, - * or AFE Tx port For a list of valid IDs, refer to - * @xhyperref{Q4,[Q4]}. - * Q4 = Hexagon Multimedia: AFE Interface Specification - */ - - u16 endpoint_id_2; -/* Logical and physical endpoint ID 2 for a voice processor - * Tx block. - * This is not applicable to audio COPP. - * Supported values: - * - AFE Rx port - * - 0xFFFF -- Endpoint 2 is unavailable and the voice - * processor Tx - * block ignores this endpoint - * When the voice processor Tx block is created on the audio - * record path, - * it can receive far-end samples from an AFE Rx port if the - * voice call - * is active. The ID of the AFE port is provided in this - * field. - * For a list of valid IDs, refer @xhyperref{Q4,[Q4]}. - */ - - u32 topology_id; - /* Audio COPP topology ID; 32-bit GUID. */ - - u16 dev_num_channel; -/* Number of channels the audio COPP sends to/receives from - * the endpoint. - * Supported values: 1 to 8. - * The value is ignored for the voice processor Tx block, - * where channel - * configuration is derived from the topology ID. - */ - - u16 bit_width; -/* Bit width (in bits) that the audio COPP sends to/receives - * from the - * endpoint. The value is ignored for the voice processing - * Tx block, - * where the PCM width is 16 bits. - */ - - u32 sample_rate; -/* Sampling rate at which the audio COPP/voice processor - * Tx block - * interfaces with the endpoint. - * Supported values for voice processor Tx: 8000, 16000, - * 48000 Hz - * Supported values for audio COPP: >0 and <=192 kHz - */ - - u8 dev_channel_mapping[8]; -/* Array of channel mapping of buffers that the audio COPP - * sends to the endpoint. Channel[i] mapping describes channel - * I inside the buffer, where 0 < i < dev_num_channel. - * This value is relevent only for an audio Rx COPP. - * For the voice processor block and Tx audio block, this field - * is set to zero and is ignored. - */ -} __packed; - -/* - * This command allows the client to close a COPP and disconnect - * the device session. - */ -#define ADM_CMD_DEVICE_CLOSE_V5 0x00010327 - -/* Sets one or more parameters to a COPP. -*/ -#define ADM_CMD_SET_PP_PARAMS_V5 0x00010328 - -/* Payload of the #ADM_CMD_SET_PP_PARAMS_V5 command. - * If the data_payload_addr_lsw and data_payload_addr_msw element - * are NULL, a series of adm_param_datastructures immediately - * follows, whose total size is data_payload_size bytes. - */ -struct adm_cmd_set_pp_params_v5 { - struct apr_hdr hdr; - u32 payload_addr_lsw; - /* LSW of parameter data payload address.*/ - u32 payload_addr_msw; - /* MSW of parameter data payload address.*/ - - u32 mem_map_handle; -/* Memory map handle returned by ADM_CMD_SHARED_MEM_MAP_REGIONS - * command */ -/* If mem_map_handle is zero implies the message is in - * the payload */ - - u32 payload_size; -/* Size in bytes of the variable payload accompanying this - * message or - * in shared memory. This is used for parsing the parameter - * payload. - */ -} __packed; - -/* Payload format for COPP parameter data. - * Immediately following this structure are param_size bytes - * of parameter - * data. - */ -struct adm_param_data_v5 { - u32 module_id; - /* Unique ID of the module. */ - u32 param_id; - /* Unique ID of the parameter. */ - u16 param_size; - /* Data size of the param_id/module_id combination. - This value is a - multiple of 4 bytes. */ - u16 reserved; - /* Reserved for future enhancements. - * This field must be set to zero. - */ -} __packed; - -/* set customized mixing on matrix mixer */ -#define ADM_CMD_SET_PSPD_MTMX_STRTR_PARAMS_V5 0x00010344 -struct adm_cmd_set_pspd_mtmx_strtr_params_v5 { - struct apr_hdr hdr; - /* LSW of parameter data payload address.*/ - u32 payload_addr_lsw; - /* MSW of parameter data payload address.*/ - u32 payload_addr_msw; - /* Memory map handle returned by ADM_CMD_SHARED_MEM_MAP_REGIONS */ - /* command. If mem_map_handle is zero implies the message is in */ - /* the payload */ - u32 mem_map_handle; - /* Size in bytes of the variable payload accompanying this */ - /* message or in shared memory. This is used for parsing the */ - /* parameter payload. */ - u32 payload_size; - u16 direction; - u16 sessionid; - u16 deviceid; - u16 reserved; -} __packed; - -/* Defined specifically for in-band use, includes params */ -struct adm_cmd_set_pp_params_inband_v5 { - struct apr_hdr hdr; - /* LSW of parameter data payload address.*/ - u32 payload_addr_lsw; - /* MSW of parameter data payload address.*/ - u32 payload_addr_msw; - /* Memory map handle returned by ADM_CMD_SHARED_MEM_MAP_REGIONS */ - /* command. If mem_map_handle is zero implies the message is in */ - /* the payload */ - u32 mem_map_handle; - /* Size in bytes of the variable payload accompanying this */ - /* message or in shared memory. This is used for parsing the */ - /* parameter payload. */ - u32 payload_size; - /* Parameters passed for in band payload */ - struct adm_param_data_v5 params; -} __packed; - -/* Returns the status and COPP ID to an #ADM_CMD_DEVICE_OPEN_V5 command. - */ -#define ADM_CMDRSP_DEVICE_OPEN_V5 0x00010329 - -/* Payload of the #ADM_CMDRSP_DEVICE_OPEN_V5 message, - * which returns the - * status and COPP ID to an #ADM_CMD_DEVICE_OPEN_V5 command. - */ -struct adm_cmd_rsp_device_open_v5 { - u32 status; - /* Status message (error code).*/ - - u16 copp_id; - /* COPP ID: Supported values: 0 <= copp_id < ADM_MAX_COPPS*/ - - u16 reserved; - /* Reserved. This field must be set to zero.*/ -} __packed; - -/* This command allows a query of one COPP parameter. -*/ -#define ADM_CMD_GET_PP_PARAMS_V5 0x0001032A - -/* Payload an #ADM_CMD_GET_PP_PARAMS_V5 command. -*/ -struct adm_cmd_get_pp_params_v5 { - struct apr_hdr hdr; - u32 data_payload_addr_lsw; - /* LSW of parameter data payload address.*/ - - u32 data_payload_addr_msw; - /* MSW of parameter data payload address.*/ - - /* If the mem_map_handle is non zero, - * on ACK, the ParamData payloads begin at - * the address specified (out-of-band). - */ - - u32 mem_map_handle; - /* Memory map handle returned - * by ADM_CMD_SHARED_MEM_MAP_REGIONS command. - * If the mem_map_handle is 0, it implies that - * the ACK's payload will contain the ParamData (in-band). - */ - - u32 module_id; - /* Unique ID of the module. */ - - u32 param_id; - /* Unique ID of the parameter. */ - - u16 param_max_size; - /* Maximum data size of the parameter - *ID/module ID combination. This - * field is a multiple of 4 bytes. - */ - u16 reserved; - /* Reserved for future enhancements. - * This field must be set to zero. - */ -} __packed; - -/* Returns parameter values - * in response to an #ADM_CMD_GET_PP_PARAMS_V5 command. - */ -#define ADM_CMDRSP_GET_PP_PARAMS_V5 0x0001032B - -/* Payload of the #ADM_CMDRSP_GET_PP_PARAMS_V5 message, - * which returns parameter values in response - * to an #ADM_CMD_GET_PP_PARAMS_V5 command. - * Immediately following this - * structure is the adm_param_data_v5 - * structure containing the pre/postprocessing - * parameter data. For an in-band - * scenario, the variable payload depends - * on the size of the parameter. -*/ -struct adm_cmd_rsp_get_pp_params_v5 { - u32 status; - /* Status message (error code).*/ -} __packed; - -/* Structure for holding soft stepping volume parameters. */ - -/* - * Payload of the #ASM_PARAM_ID_SOFT_VOL_STEPPING_PARAMETERS - * parameters used by the Volume Control module. - */ - -struct audproc_softvolume_params { - u32 period; - u32 step; - u32 rampingcurve; -} __packed; - -struct audproc_volume_ctrl_master_gain { - struct adm_cmd_set_pp_params_v5 params; - struct adm_param_data_v5 data; - /* Linear gain in Q13 format. */ - uint16_t master_gain; - /* Clients must set this field to zero. */ - uint16_t reserved; -} __packed; - -struct audproc_soft_step_volume_params { - struct adm_cmd_set_pp_params_v5 params; - struct adm_param_data_v5 data; -/* - * Period in milliseconds. - * Supported values: 0 to 15000 - */ - uint32_t period; -/* - * Step in microseconds. - * Supported values: 0 to 15000000 - */ - uint32_t step; -/* - * Ramping curve type. - * Supported values: - * - #AUDPROC_PARAM_SVC_RAMPINGCURVE_LINEAR - * - #AUDPROC_PARAM_SVC_RAMPINGCURVE_EXP - * - #AUDPROC_PARAM_SVC_RAMPINGCURVE_LOG - */ - uint32_t ramping_curve; -} __packed; - -struct audproc_enable_param_t { - struct adm_cmd_set_pp_params_inband_v5 pp_params; - /* - * Specifies whether the Audio processing module is enabled. - * This parameter is generic/common parameter to configure or - * determine the state of any audio processing module. - - * @values 0 : Disable 1: Enable - */ - uint32_t enable; -}; - -/* - * Allows a client to control the gains on various session-to-COPP paths. - */ -#define ADM_CMD_MATRIX_RAMP_GAINS_V5 0x0001032C - -/* Indicates that the target gain in the - * current adm_session_copp_gain_v5 - * structure is to be applied to all - * the session-to-COPP paths that exist for - * the specified session. - */ -#define ADM_CMD_MATRIX_RAMP_GAINS_COPP_ID_ALL_CONNECTED_COPPS 0xFFFF - -/* Indicates that the target gain is - * to be immediately applied to the - * specified session-to-COPP path, - * without a ramping fashion. - */ -#define ADM_CMD_MATRIX_RAMP_GAINS_RAMP_DURATION_IMMEDIATE 0x0000 - -/* Enumeration for a linear ramping curve.*/ -#define ADM_CMD_MATRIX_RAMP_GAINS_RAMP_CURVE_LINEAR 0x0000 - -/* Payload of the #ADM_CMD_MATRIX_RAMP_GAINS_V5 command. - * Immediately following this structure are num_gains of the - * adm_session_copp_gain_v5structure. - */ -struct adm_cmd_matrix_ramp_gains_v5 { - u32 matrix_id; -/* Specifies whether the matrix ID is Audio Rx (0) or Audio Tx (1). - * Use the ADM_MATRIX_ID_AUDIO_RX or ADM_MATRIX_ID_AUDIOX - * macros to set this field. -*/ - - u16 num_gains; - /* Number of gains being applied. */ - - u16 reserved_for_align; - /* Reserved. This field must be set to zero.*/ -} __packed; - -/* Session-to-COPP path gain structure, used by the - * #ADM_CMD_MATRIX_RAMP_GAINS_V5 command. - * This structure specifies the target - * gain (per channel) that must be applied - * to a particular session-to-COPP path in - * the audio matrix. The structure can - * also be used to apply the gain globally - * to all session-to-COPP paths that - * exist for the given session. - * The aDSP uses device channel mapping to - * determine which channel gains to - * use from this command. For example, - * if the device is configured as stereo, - * the aDSP uses only target_gain_ch_1 and - * target_gain_ch_2, and it ignores - * the others. - */ -struct adm_session_copp_gain_v5 { - u16 session_id; -/* Handle of the ASM session. - * Supported values: 1 to 8. - */ - - u16 copp_id; -/* Handle of the COPP. Gain will be applied on the Session ID - * COPP ID path. - */ - - u16 ramp_duration; -/* Duration (in milliseconds) of the ramp over - * which target gains are - * to be applied. Use - * #ADM_CMD_MATRIX_RAMP_GAINS_RAMP_DURATION_IMMEDIATE - * to indicate that gain must be applied immediately. - */ - - u16 step_duration; -/* Duration (in milliseconds) of each step in the ramp. - * This parameter is ignored if ramp_duration is equal to - * #ADM_CMD_MATRIX_RAMP_GAINS_RAMP_DURATION_IMMEDIATE. - * Supported value: 1 - */ - - u16 ramp_curve; -/* Type of ramping curve. - * Supported value: #ADM_CMD_MATRIX_RAMP_GAINS_RAMP_CURVE_LINEAR - */ - - u16 reserved_for_align; - /* Reserved. This field must be set to zero. */ - - u16 target_gain_ch_1; - /* Target linear gain for channel 1 in Q13 format; */ - - u16 target_gain_ch_2; - /* Target linear gain for channel 2 in Q13 format; */ - - u16 target_gain_ch_3; - /* Target linear gain for channel 3 in Q13 format; */ - - u16 target_gain_ch_4; - /* Target linear gain for channel 4 in Q13 format; */ - - u16 target_gain_ch_5; - /* Target linear gain for channel 5 in Q13 format; */ - - u16 target_gain_ch_6; - /* Target linear gain for channel 6 in Q13 format; */ - - u16 target_gain_ch_7; - /* Target linear gain for channel 7 in Q13 format; */ - - u16 target_gain_ch_8; - /* Target linear gain for channel 8 in Q13 format; */ -} __packed; - -/* Allows to set mute/unmute on various session-to-COPP paths. - * For every session-to-COPP path (stream-device interconnection), - * mute/unmute can be set individually on the output channels. - */ -#define ADM_CMD_MATRIX_MUTE_V5 0x0001032D - -/* Indicates that mute/unmute in the - * current adm_session_copp_mute_v5structure - * is to be applied to all the session-to-COPP - * paths that exist for the specified session. - */ -#define ADM_CMD_MATRIX_MUTE_COPP_ID_ALL_CONNECTED_COPPS 0xFFFF - -/* Payload of the #ADM_CMD_MATRIX_MUTE_V5 command*/ -struct adm_cmd_matrix_mute_v5 { - u32 matrix_id; -/* Specifies whether the matrix ID is Audio Rx (0) or Audio Tx (1). - * Use the ADM_MATRIX_ID_AUDIO_RX or ADM_MATRIX_ID_AUDIOX - * macros to set this field. - */ - - u16 session_id; -/* Handle of the ASM session. - * Supported values: 1 to 8. - */ - - u16 copp_id; -/* Handle of the COPP. - * Use ADM_CMD_MATRIX_MUTE_COPP_ID_ALL_CONNECTED_COPPS - * to indicate that mute/unmute must be applied to - * all the COPPs connected to session_id. - * Supported values: - * - 0xFFFF -- Apply mute/unmute to all connected COPPs - * - Other values -- Valid COPP ID - */ - - u8 mute_flag_ch_1; - /* Mute flag for channel 1 is set to unmute (0) or mute (1). */ - - u8 mute_flag_ch_2; - /* Mute flag for channel 2 is set to unmute (0) or mute (1). */ - - u8 mute_flag_ch_3; - /* Mute flag for channel 3 is set to unmute (0) or mute (1). */ - - u8 mute_flag_ch_4; - /* Mute flag for channel 4 is set to unmute (0) or mute (1). */ - - u8 mute_flag_ch_5; - /* Mute flag for channel 5 is set to unmute (0) or mute (1). */ - - u8 mute_flag_ch_6; - /* Mute flag for channel 6 is set to unmute (0) or mute (1). */ - - u8 mute_flag_ch_7; - /* Mute flag for channel 7 is set to unmute (0) or mute (1). */ - - u8 mute_flag_ch_8; - /* Mute flag for channel 8 is set to unmute (0) or mute (1). */ - - u16 ramp_duration; -/* Period (in milliseconds) over which the soft mute/unmute will be - * applied. - * Supported values: 0 (Default) to 0xFFFF - * The default of 0 means mute/unmute will be applied immediately. - */ - - u16 reserved_for_align; - /* Clients must set this field to zero.*/ -} __packed; - -#define ASM_PARAM_ID_AAC_STEREO_MIX_COEFF_SELECTION_FLAG_V2 (0x00010DD8) - -struct asm_aac_stereo_mix_coeff_selection_param_v2 { - struct apr_hdr hdr; - u32 param_id; - u32 param_size; - u32 aac_stereo_mix_coeff_flag; -} __packed; - -/* Allows a client to connect the desired stream to - * the desired AFE port through the stream router - * - * This command allows the client to connect specified session to - * specified AFE port. This is used for compressed streams only - * opened using the #ASM_STREAM_CMD_OPEN_WRITE_COMPRESSED or - * #ASM_STREAM_CMD_OPEN_READ_COMPRESSED command. - * - * @prerequisites - * Session ID and AFE Port ID must be valid. - * #ASM_STREAM_CMD_OPEN_WRITE_COMPRESSED or - * #ASM_STREAM_CMD_OPEN_READ_COMPRESSED - * must have been called on this session. - */ - -#define ADM_CMD_CONNECT_AFE_PORT_V5 0x0001032E -#define ADM_CMD_DISCONNECT_AFE_PORT_V5 0x0001032F -/* Enumeration for the Rx stream router ID.*/ -#define ADM_STRTR_ID_RX 0 -/* Enumeration for the Tx stream router ID.*/ -#define ADM_STRTR_IDX 1 - -/* Payload of the #ADM_CMD_CONNECT_AFE_PORT_V5 command.*/ -struct adm_cmd_connect_afe_port_v5 { - struct apr_hdr hdr; - u8 mode; -/* ID of the stream router (RX/TX). Use the - * ADM_STRTR_ID_RX or ADM_STRTR_IDX macros - * to set this field. - */ - - u8 session_id; - /* Session ID of the stream to connect */ - - u16 afe_port_id; - /* Port ID of the AFE port to connect to.*/ - u32 num_channels; -/* Number of device channels - * Supported values: 2(Audio Sample Packet), - * 8 (HBR Audio Stream Sample Packet) - */ - - u32 sampling_rate; -/* Device sampling rate -* Supported values: Any -*/ -} __packed; - - -/* adsp_adm_api.h */ - - -/* Port ID. Update afe_get_port_index - * when a new port is added here. */ -#define PRIMARY_I2S_RX 0 -#define PRIMARY_I2S_TX 1 -#define SECONDARY_I2S_RX 4 -#define SECONDARY_I2S_TX 5 -#define MI2S_RX 6 -#define MI2S_TX 7 -#define HDMI_RX 8 -#define RSVD_2 9 -#define RSVD_3 10 -#define DIGI_MIC_TX 11 -#define VOICE2_PLAYBACK_TX 0x8002 -#define VOICE_RECORD_RX 0x8003 -#define VOICE_RECORD_TX 0x8004 -#define VOICE_PLAYBACK_TX 0x8005 - -/* Slimbus Multi channel port id pool */ -#define SLIMBUS_0_RX 0x4000 -#define SLIMBUS_0_TX 0x4001 -#define SLIMBUS_1_RX 0x4002 -#define SLIMBUS_1_TX 0x4003 -#define SLIMBUS_2_RX 0x4004 -#define SLIMBUS_2_TX 0x4005 -#define SLIMBUS_3_RX 0x4006 -#define SLIMBUS_3_TX 0x4007 -#define SLIMBUS_4_RX 0x4008 -#define SLIMBUS_4_TX 0x4009 -#define SLIMBUS_5_RX 0x400a -#define SLIMBUS_5_TX 0x400b -#define SLIMBUS_6_RX 0x400c -#define SLIMBUS_6_TX 0x400d -#define SLIMBUS_PORT_LAST SLIMBUS_6_TX -#define INT_BT_SCO_RX 0x3000 -#define INT_BT_SCO_TX 0x3001 -#define INT_BT_A2DP_RX 0x3002 -#define INT_FM_RX 0x3004 -#define INT_FM_TX 0x3005 -#define RT_PROXY_PORT_001_RX 0x2000 -#define RT_PROXY_PORT_001_TX 0x2001 - -#define AFE_PORT_INVALID 0xFFFF -#define SLIMBUS_INVALID AFE_PORT_INVALID - -#define AFE_PORT_CMD_START 0x000100ca - -#define AFE_EVENT_RTPORT_START 0 -#define AFE_EVENT_RTPORT_STOP 1 -#define AFE_EVENT_RTPORT_LOW_WM 2 -#define AFE_EVENT_RTPORT_HI_WM 3 - -#define ADSP_AFE_VERSION 0x00200000 - -/* Size of the range of port IDs for the audio interface. */ -#define AFE_PORT_ID_AUDIO_IF_PORT_RANGE_SIZE 0xF - -/* Size of the range of port IDs for internal BT-FM ports. */ -#define AFE_PORT_ID_INTERNAL_BT_FM_RANGE_SIZE 0x6 - -/* Size of the range of port IDs for SLIMbus® - * multichannel - * ports. - */ -#define AFE_PORT_ID_SLIMBUS_RANGE_SIZE 0xA - -/* Size of the range of port IDs for real-time proxy ports. */ -#define AFE_PORT_ID_RT_PROXY_PORT_RANGE_SIZE 0x2 - -/* Size of the range of port IDs for pseudoports. */ -#define AFE_PORT_ID_PSEUDOPORT_RANGE_SIZE 0x5 - -/* Start of the range of port IDs for the audio interface. */ -#define AFE_PORT_ID_AUDIO_IF_PORT_RANGE_START 0x1000 - -/* End of the range of port IDs for the audio interface. */ -#define AFE_PORT_ID_AUDIO_IF_PORT_RANGE_END \ - (AFE_PORT_ID_AUDIO_IF_PORT_RANGE_START +\ - AFE_PORT_ID_AUDIO_IF_PORT_RANGE_SIZE - 1) - -/* Start of the range of port IDs for real-time proxy ports. */ -#define AFE_PORT_ID_RT_PROXY_PORT_RANGE_START 0x2000 - -/* End of the range of port IDs for real-time proxy ports. */ -#define AFE_PORT_ID_RT_PROXY_PORT_RANGE_END \ - (AFE_PORT_ID_RT_PROXY_PORT_RANGE_START +\ - AFE_PORT_ID_RT_PROXY_PORT_RANGE_SIZE-1) - -/* Start of the range of port IDs for internal BT-FM devices. */ -#define AFE_PORT_ID_INTERNAL_BT_FM_RANGE_START 0x3000 - -/* End of the range of port IDs for internal BT-FM devices. */ -#define AFE_PORT_ID_INTERNAL_BT_FM_RANGE_END \ - (AFE_PORT_ID_INTERNAL_BT_FM_RANGE_START +\ - AFE_PORT_ID_INTERNAL_BT_FM_RANGE_SIZE-1) - -/* Start of the range of port IDs for SLIMbus devices. */ -#define AFE_PORT_ID_SLIMBUS_RANGE_START 0x4000 - -/* End of the range of port IDs for SLIMbus devices. */ -#define AFE_PORT_ID_SLIMBUS_RANGE_END \ - (AFE_PORT_ID_SLIMBUS_RANGE_START +\ - AFE_PORT_ID_SLIMBUS_RANGE_SIZE-1) - -/* Start of the range of port IDs for pseudoports. */ -#define AFE_PORT_ID_PSEUDOPORT_RANGE_START 0x8001 - -/* End of the range of port IDs for pseudoports. */ -#define AFE_PORT_ID_PSEUDOPORT_RANGE_END \ - (AFE_PORT_ID_PSEUDOPORT_RANGE_START +\ - AFE_PORT_ID_PSEUDOPORT_RANGE_SIZE-1) - -#define AFE_PORT_ID_PRIMARY_MI2S_RX 0x1000 -#define AFE_PORT_ID_PRIMARY_MI2S_TX 0x1001 -#define AFE_PORT_ID_SECONDARY_MI2S_RX 0x1002 -#define AFE_PORT_ID_SECONDARY_MI2S_TX 0x1003 -#define AFE_PORT_ID_TERTIARY_MI2S_RX 0x1004 -#define AFE_PORT_ID_TERTIARY_MI2S_TX 0x1005 -#define AFE_PORT_ID_QUATERNARY_MI2S_RX 0x1006 -#define AFE_PORT_ID_QUATERNARY_MI2S_TX 0x1007 -#define AUDIO_PORT_ID_I2S_RX 0x1008 -#define AFE_PORT_ID_DIGITAL_MIC_TX 0x1009 -#define AFE_PORT_ID_PRIMARY_PCM_RX 0x100A -#define AFE_PORT_ID_PRIMARY_PCM_TX 0x100B -#define AFE_PORT_ID_SECONDARY_PCM_RX 0x100C -#define AFE_PORT_ID_SECONDARY_PCM_TX 0x100D -#define AFE_PORT_ID_MULTICHAN_HDMI_RX 0x100E -#define AFE_PORT_ID_SECONDARY_MI2S_RX_SD1 0x1010 -#define AFE_PORT_ID_SPDIF_RX 0x5000 -#define AFE_PORT_ID_RT_PROXY_PORT_001_RX 0x2000 -#define AFE_PORT_ID_RT_PROXY_PORT_001_TX 0x2001 -#define AFE_PORT_ID_INTERNAL_BT_SCO_RX 0x3000 -#define AFE_PORT_ID_INTERNAL_BT_SCO_TX 0x3001 -#define AFE_PORT_ID_INTERNAL_BT_A2DP_RX 0x3002 -#define AFE_PORT_ID_INTERNAL_FM_RX 0x3004 -#define AFE_PORT_ID_INTERNAL_FM_TX 0x3005 -/* SLIMbus Rx port on channel 0. */ -#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_RX 0x4000 -/* SLIMbus Tx port on channel 0. */ -#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_0_TX 0x4001 -/* SLIMbus Rx port on channel 1. */ -#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_RX 0x4002 -/* SLIMbus Tx port on channel 1. */ -#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_1_TX 0x4003 -/* SLIMbus Rx port on channel 2. */ -#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_RX 0x4004 -/* SLIMbus Tx port on channel 2. */ -#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_2_TX 0x4005 -/* SLIMbus Rx port on channel 3. */ -#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_RX 0x4006 -/* SLIMbus Tx port on channel 3. */ -#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_3_TX 0x4007 -/* SLIMbus Rx port on channel 4. */ -#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_RX 0x4008 -/* SLIMbus Tx port on channel 4. */ -#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_4_TX 0x4009 -/* SLIMbus Rx port on channel 5. */ -#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_RX 0x400a -/* SLIMbus Tx port on channel 5. */ -#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_5_TX 0x400b -/* SLIMbus Rx port on channel 6. */ -#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_RX 0x400c -/* SLIMbus Tx port on channel 6. */ -#define AFE_PORT_ID_SLIMBUS_MULTI_CHAN_6_TX 0x400d - -/* Generic pseudoport 1. */ -#define AFE_PORT_ID_PSEUDOPORT_01 0x8001 -/* Generic pseudoport 2. */ -#define AFE_PORT_ID_PSEUDOPORT_02 0x8002 - -/* @xreflabel{hdr:AfePortIdPrimaryAuxPcmTx} - Primary Aux PCM Tx port ID. -*/ -#define AFE_PORT_ID_PRIMARY_PCM_TX 0x100B -/* Pseudoport that corresponds to the voice Rx path. - * For recording, the voice Rx path samples are written to this - * port and consumed by the audio path. - */ - -#define AFE_PORT_ID_VOICE_RECORD_RX 0x8003 - -/* Pseudoport that corresponds to the voice Tx path. - * For recording, the voice Tx path samples are written to this - * port and consumed by the audio path. - */ - -#define AFE_PORT_ID_VOICE_RECORD_TX 0x8004 -/* Pseudoport that corresponds to in-call voice delivery samples. - * During in-call audio delivery, the audio path delivers samples - * to this port from where the voice path delivers them on the - * Rx path. - */ -#define AFE_PORT_ID_VOICE2_PLAYBACK_TX 0x8002 -#define AFE_PORT_ID_VOICE_PLAYBACK_TX 0x8005 -#define AFE_PORT_ID_INVALID 0xFFFF - -#define AAC_ENC_MODE_AAC_LC 0x02 -#define AAC_ENC_MODE_AAC_P 0x05 -#define AAC_ENC_MODE_EAAC_P 0x1D - -#define AFE_PSEUDOPORT_CMD_START 0x000100cf -struct afe_pseudoport_start_command { - struct apr_hdr hdr; - u16 port_id; /* Pseudo Port 1 = 0x8000 */ - /* Pseudo Port 2 = 0x8001 */ - /* Pseudo Port 3 = 0x8002 */ - u16 timing; /* FTRT = 0 , AVTimer = 1, */ -} __packed; - -#define AFE_PSEUDOPORT_CMD_STOP 0x000100d0 -struct afe_pseudoport_stop_command { - struct apr_hdr hdr; - u16 port_id; /* Pseudo Port 1 = 0x8000 */ - /* Pseudo Port 2 = 0x8001 */ - /* Pseudo Port 3 = 0x8002 */ - u16 reserved; -} __packed; - - -#define AFE_MODULE_SIDETONE_IIR_FILTER 0x00010202 -#define AFE_PARAM_ID_ENABLE 0x00010203 - -/* Payload of the #AFE_PARAM_ID_ENABLE - * parameter, which enables or - * disables any module. - * The fixed size of this structure is four bytes. - */ - -struct afe_mod_enable_param { - u16 enable; - /* Enables (1) or disables (0) the module. */ - - u16 reserved; - /* This field must be set to zero. - */ -} __packed; - -/* ID of the configuration parameter used by the - * #AFE_MODULE_SIDETONE_IIR_FILTER module. - */ -#define AFE_PARAM_ID_SIDETONE_IIR_FILTER_CONFIG 0x00010204 - -struct afe_sidetone_iir_filter_config_params { - u16 num_biquad_stages; -/* Number of stages. - * Supported values: Minimum of 5 and maximum of 10 - */ - - u16 pregain; -/* Pregain for the compensating filter response. - * Supported values: Any number in Q13 format - */ -} __packed; - -#define AFE_MODULE_LOOPBACK 0x00010205 -#define AFE_PARAM_ID_LOOPBACK_GAIN_PER_PATH 0x00010206 - -/* Payload of the #AFE_PARAM_ID_LOOPBACK_GAIN_PER_PATH parameter, - * which gets/sets loopback gain of a port to an Rx port. - * The Tx port ID of the loopback is part of the set_param command. - */ - -/* Payload of the #AFE_PORT_CMD_SET_PARAM_V2 command's - * configuration/calibration settings for the AFE port. - */ -struct afe_port_cmd_set_param_v2 { - u16 port_id; -/* Port interface and direction (Rx or Tx) to start. - */ - - u16 payload_size; -/* Actual size of the payload in bytes. - * This is used for parsing the parameter payload. - * Supported values: > 0 - */ - -u32 payload_address_lsw; -/* LSW of 64 bit Payload address. - * Address should be 32-byte, - * 4kbyte aligned and must be contiguous memory. - */ - -u32 payload_address_msw; -/* MSW of 64 bit Payload address. - * In case of 32-bit shared memory address, - * this field must be set to zero. - * In case of 36-bit shared memory address, - * bit-4 to bit-31 must be set to zero. - * Address should be 32-byte, 4kbyte aligned - * and must be contiguous memory. - */ - -u32 mem_map_handle; -/* Memory map handle returned by - * AFE_SERVICE_CMD_SHARED_MEM_MAP_REGIONS commands. - * Supported Values: - * - NULL -- Message. The parameter data is in-band. - * - Non-NULL -- The parameter data is Out-band.Pointer to - * the physical address - * in shared memory of the payload data. - * An optional field is available if parameter - * data is in-band: - * afe_param_data_v2 param_data[...]. - * For detailed payload content, see the - * afe_port_param_data_v2 structure. - */ -} __packed; - -#define AFE_PORT_CMD_SET_PARAM_V2 0x000100EF - -struct afe_port_param_data_v2 { - u32 module_id; -/* ID of the module to be configured. - * Supported values: Valid module ID - */ - -u32 param_id; -/* ID of the parameter corresponding to the supported parameters - * for the module ID. - * Supported values: Valid parameter ID - */ - -u16 param_size; -/* Actual size of the data for the - * module_id/param_id pair. The size is a - * multiple of four bytes. - * Supported values: > 0 - */ - -u16 reserved; -/* This field must be set to zero. - */ -} __packed; - -struct afe_loopback_gain_per_path_param { - struct apr_hdr hdr; - struct afe_port_cmd_set_param_v2 param; - struct afe_port_param_data_v2 pdata; - u16 rx_port_id; -/* Rx port of the loopback. */ - -u16 gain; -/* Loopback gain per path of the port. - * Supported values: Any number in Q13 format - */ -} __packed; - -/* Parameter ID used to configure and enable/disable the - * loopback path. The difference with respect to the existing - * API, AFE_PORT_CMD_LOOPBACK, is that it allows Rx port to be - * configured as source port in loopback path. Port-id in - * AFE_PORT_CMD_SET_PARAM cmd is the source port whcih can be - * Tx or Rx port. In addition, we can configure the type of - * routing mode to handle different use cases. - */ -#define AFE_PARAM_ID_LOOPBACK_CONFIG 0x0001020B -#define AFE_API_VERSION_LOOPBACK_CONFIG 0x1 - -enum afe_loopback_routing_mode { - LB_MODE_DEFAULT = 1, - /* Regular loopback from source to destination port */ - LB_MODE_SIDETONE, - /* Sidetone feed from Tx source to Rx destination port */ - LB_MODE_EC_REF_VOICE_AUDIO, - /* Echo canceller reference, voice + audio + DTMF */ - LB_MODE_EC_REF_VOICE - /* Echo canceller reference, voice alone */ -} __packed; - -/* Payload of the #AFE_PARAM_ID_LOOPBACK_CONFIG , - * which enables/disables one AFE loopback. - */ -struct afe_loopback_cfg_v1 { - struct apr_hdr hdr; - struct afe_port_cmd_set_param_v2 param; - struct afe_port_param_data_v2 pdata; - u32 loopback_cfg_minor_version; -/* Minor version used for tracking the version of the RMC module - * configuration interface. - * Supported values: #AFE_API_VERSION_LOOPBACK_CONFIG - */ - u16 dst_port_id; - /* Destination Port Id. */ - u16 routing_mode; -/* Specifies data path type from src to dest port. - * Supported values: - * #LB_MODE_DEFAULT - * #LB_MODE_SIDETONE - * #LB_MODE_EC_REF_VOICE_AUDIO - * #LB_MODE_EC_REF_VOICE_A - * #LB_MODE_EC_REF_VOICE - */ - - u16 enable; -/* Specifies whether to enable (1) or - * disable (0) an AFE loopback. - */ - u16 reserved; -/* Reserved for 32-bit alignment. This field must be set to 0. - */ - -} __packed; - -#define AFE_MODULE_SPEAKER_PROTECTION 0x00010209 -#define AFE_PARAM_ID_SPKR_PROT_CONFIG 0x0001020a -#define AFE_API_VERSION_SPKR_PROT_CONFIG 0x1 -#define AFE_SPKR_PROT_EXCURSIONF_LEN 512 -struct afe_spkr_prot_cfg_param_v1 { - u32 spkr_prot_minor_version; -/* - * Minor version used for tracking the version of the - * speaker protection module configuration interface. - * Supported values: #AFE_API_VERSION_SPKR_PROT_CONFIG - */ - -int16_t win_size; -/* Analysis and synthesis window size (nWinSize). - * Supported values: 1024, 512, 256 samples - */ - -int16_t margin; -/* Allowable margin for excursion prediction, - * in L16Q15 format. This is a - * control parameter to allow - * for overestimation of peak excursion. - */ - -int16_t spkr_exc_limit; -/* Speaker excursion limit, in L16Q15 format.*/ - -int16_t spkr_resonance_freq; -/* Resonance frequency of the speaker; used - * to define a frequency range - * for signal modification. - * - * Supported values: 0 to 2000 Hz */ - -int16_t limhresh; -/* Threshold of the hard limiter; used to - * prevent overshooting beyond a - * signal level that was set by the limiter - * prior to speaker protection. - * Supported values: 0 to 32767 - */ - -int16_t hpf_cut_off_freq; -/* High pass filter cutoff frequency. - * Supported values: 100, 200, 300 Hz - */ - -int16_t hpf_enable; -/* Specifies whether the high pass filter - * is enabled (0) or disabled (1). - */ - -int16_t reserved; -/* This field must be set to zero. */ - -int32_t amp_gain; -/* Amplifier gain in L32Q15 format. - * This is the RMS voltage at the - * loudspeaker when a 0dBFS tone - * is played in the digital domain. - */ - -int16_t excursionf[AFE_SPKR_PROT_EXCURSIONF_LEN]; -/* Array of the excursion transfer function. - * The peak excursion of the - * loudspeaker diaphragm is - * measured in millimeters for 1 Vrms Sine - * tone at all FFT bin frequencies. - * Supported values: Q15 format - */ -} __packed; - - -#define AFE_SERVICE_CMD_REGISTER_RT_PORT_DRIVER 0x000100E0 - -/* Payload of the #AFE_SERVICE_CMD_REGISTER_RT_PORT_DRIVER - * command, which registers a real-time port driver - * with the AFE service. - */ -struct afe_service_cmd_register_rt_port_driver { - struct apr_hdr hdr; - u16 port_id; -/* Port ID with which the real-time driver exchanges data - * (registers for events). - * Supported values: #AFE_PORT_ID_RT_PROXY_PORT_RANGE_START to - * #AFE_PORT_ID_RT_PROXY_PORT_RANGE_END - */ - - u16 reserved; - /* This field must be set to zero. */ -} __packed; - -#define AFE_SERVICE_CMD_UNREGISTER_RT_PORT_DRIVER 0x000100E1 - -/* Payload of the #AFE_SERVICE_CMD_UNREGISTER_RT_PORT_DRIVER - * command, which unregisters a real-time port driver from - * the AFE service. - */ -struct afe_service_cmd_unregister_rt_port_driver { - struct apr_hdr hdr; - u16 port_id; -/* Port ID from which the real-time - * driver unregisters for events. - * Supported values: #AFE_PORT_ID_RT_PROXY_PORT_RANGE_START to - * #AFE_PORT_ID_RT_PROXY_PORT_RANGE_END - */ - - u16 reserved; - /* This field must be set to zero. */ -} __packed; - -#define AFE_EVENT_RT_PROXY_PORT_STATUS 0x00010105 -#define AFE_EVENTYPE_RT_PROXY_PORT_START 0 -#define AFE_EVENTYPE_RT_PROXY_PORT_STOP 1 -#define AFE_EVENTYPE_RT_PROXY_PORT_LOW_WATER_MARK 2 -#define AFE_EVENTYPE_RT_PROXY_PORT_HIGH_WATER_MARK 3 -#define AFE_EVENTYPE_RT_PROXY_PORT_INVALID 0xFFFF - -/* Payload of the #AFE_EVENT_RT_PROXY_PORT_STATUS - * message, which sends an event from the AFE service - * to a registered client. - */ -struct afe_event_rt_proxy_port_status { - u16 port_id; -/* Port ID to which the event is sent. - * Supported values: #AFE_PORT_ID_RT_PROXY_PORT_RANGE_START to - * #AFE_PORT_ID_RT_PROXY_PORT_RANGE_END - */ - - u16 eventype; -/* Type of event. - * Supported values: - * - #AFE_EVENTYPE_RT_PROXY_PORT_START - * - #AFE_EVENTYPE_RT_PROXY_PORT_STOP - * - #AFE_EVENTYPE_RT_PROXY_PORT_LOW_WATER_MARK - * - #AFE_EVENTYPE_RT_PROXY_PORT_HIGH_WATER_MARK - */ -} __packed; - -#define AFE_PORT_DATA_CMD_RT_PROXY_PORT_WRITE_V2 0x000100ED - -struct afe_port_data_cmd_rt_proxy_port_write_v2 { - struct apr_hdr hdr; - u16 port_id; -/* Tx (mic) proxy port ID with which the real-time - * driver exchanges data. - * Supported values: #AFE_PORT_ID_RT_PROXY_PORT_RANGE_START to - * #AFE_PORT_ID_RT_PROXY_PORT_RANGE_END - */ - - u16 reserved; - /* This field must be set to zero. */ - - u32 buffer_address_lsw; -/* LSW Address of the buffer containing the - * data from the real-time source - * device on a client. - */ - - u32 buffer_address_msw; -/* MSW Address of the buffer containing the - * data from the real-time source - * device on a client. - */ - - u32 mem_map_handle; -/* A memory map handle encapsulating shared memory - * attributes is returned if - * AFE_SERVICE_CMD_SHARED_MEM_MAP_REGIONS - * command is successful. - * Supported Values: - * - Any 32 bit value - */ - - u32 available_bytes; -/* Number of valid bytes available - * in the buffer (including all - * channels: number of bytes per - * channel = availableBytesumChannels). - * Supported values: > 0 - * - * This field must be equal to the frame - * size specified in the #AFE_PORT_AUDIO_IF_CONFIG - * command that was sent to configure this - * port. - */ -} __packed; - -#define AFE_PORT_DATA_CMD_RT_PROXY_PORT_READ_V2 0x000100EE - -/* Payload of the - * #AFE_PORT_DATA_CMD_RT_PROXY_PORT_READ_V2 command, which - * delivers an empty buffer to the AFE service. On - * acknowledgment, data is filled in the buffer. - */ -struct afe_port_data_cmd_rt_proxy_port_read_v2 { - struct apr_hdr hdr; - u16 port_id; -/* Rx proxy port ID with which the real-time - * driver exchanges data. - * Supported values: #AFE_PORT_ID_RT_PROXY_PORT_RANGE_START to - * #AFE_PORT_ID_RT_PROXY_PORT_RANGE_END - * (This must be an Rx (speaker) port.) - */ - - u16 reserved; - /* This field must be set to zero. */ - - u32 buffer_address_lsw; -/* LSW Address of the buffer containing the data sent from the AFE - * service to a real-time sink device on the client. - */ - - - u32 buffer_address_msw; -/* MSW Address of the buffer containing the data sent from the AFE - * service to a real-time sink device on the client. - */ - - u32 mem_map_handle; -/* A memory map handle encapsulating shared memory attributes is - * returned if AFE_SERVICE_CMD_SHARED_MEM_MAP_REGIONS command is - * successful. - * Supported Values: - * - Any 32 bit value - */ - - u32 available_bytes; -/* Number of valid bytes available in the buffer (including all - * channels). - * Supported values: > 0 - * This field must be equal to the frame size specified in the - * #AFE_PORT_AUDIO_IF_CONFIG command that was sent to configure - * this port. - */ -} __packed; - -/* This module ID is related to device configuring like I2S,PCM, - * HDMI, SLIMBus etc. This module supports follwing parameter ids. - * - #AFE_PARAM_ID_I2S_CONFIG - * - #AFE_PARAM_ID_PCM_CONFIG - * - #AFE_PARAM_ID_DIGI_MIC_CONFIG - * - #AFE_PARAM_ID_HDMI_CONFIG - * - #AFE_PARAM_ID_INTERNAL_BT_FM_CONFIG - * - #AFE_PARAM_ID_SLIMBUS_CONFIG - * - #AFE_PARAM_ID_RT_PROXY_CONFIG - */ - -#define AFE_MODULE_AUDIO_DEV_INTERFACE 0x0001020C -#define AFE_PORT_SAMPLE_RATE_8K 8000 -#define AFE_PORT_SAMPLE_RATE_16K 16000 -#define AFE_PORT_SAMPLE_RATE_48K 48000 -#define AFE_PORT_SAMPLE_RATE_96K 96000 -#define AFE_PORT_SAMPLE_RATE_192K 192000 -#define AFE_LINEAR_PCM_DATA 0x0 -#define AFE_NON_LINEAR_DATA 0x1 -#define AFE_LINEAR_PCM_DATA_PACKED_60958 0x2 -#define AFE_NON_LINEAR_DATA_PACKED_60958 0x3 - -/* This param id is used to configure I2S interface */ -#define AFE_PARAM_ID_I2S_CONFIG 0x0001020D -#define AFE_API_VERSION_I2S_CONFIG 0x1 -/* Enumeration for setting the I2S configuration - * channel_mode parameter to - * serial data wire number 1-3 (SD3). - */ -#define AFE_PORT_I2S_SD0 0x1 -#define AFE_PORT_I2S_SD1 0x2 -#define AFE_PORT_I2S_SD2 0x3 -#define AFE_PORT_I2S_SD3 0x4 -#define AFE_PORT_I2S_QUAD01 0x5 -#define AFE_PORT_I2S_QUAD23 0x6 -#define AFE_PORT_I2S_6CHS 0x7 -#define AFE_PORT_I2S_8CHS 0x8 -#define AFE_PORT_I2S_MONO 0x0 -#define AFE_PORT_I2S_STEREO 0x1 -#define AFE_PORT_CONFIG_I2S_WS_SRC_EXTERNAL 0x0 -#define AFE_PORT_CONFIG_I2S_WS_SRC_INTERNAL 0x1 - -/* Payload of the #AFE_PARAM_ID_I2S_CONFIG - * command's (I2S configuration - * parameter). - */ -struct afe_param_id_i2s_cfg { - u32 i2s_cfg_minor_version; -/* Minor version used for tracking the version of the I2S - * configuration interface. - * Supported values: #AFE_API_VERSION_I2S_CONFIG - */ - - u16 bit_width; -/* Bit width of the sample. - * Supported values: 16, 24 - */ - - u16 channel_mode; -/* I2S lines and multichannel operation. - * Supported values: - * - #AFE_PORT_I2S_SD0 - * - #AFE_PORT_I2S_SD1 - * - #AFE_PORT_I2S_SD2 - * - #AFE_PORT_I2S_SD3 - * - #AFE_PORT_I2S_QUAD01 - * - #AFE_PORT_I2S_QUAD23 - * - #AFE_PORT_I2S_6CHS - * - #AFE_PORT_I2S_8CHS - */ - - u16 mono_stereo; -/* Specifies mono or stereo. This applies only when - * a single I2S line is used. - * Supported values: - * - #AFE_PORT_I2S_MONO - * - #AFE_PORT_I2S_STEREO - */ - - u16 ws_src; -/* Word select source: internal or external. - * Supported values: - * - #AFE_PORT_CONFIG_I2S_WS_SRC_EXTERNAL - * - #AFE_PORT_CONFIG_I2S_WS_SRC_INTERNAL - */ - - u32 sample_rate; -/* Sampling rate of the port. - * Supported values: - * - #AFE_PORT_SAMPLE_RATE_8K - * - #AFE_PORT_SAMPLE_RATE_16K - * - #AFE_PORT_SAMPLE_RATE_48K - * - #AFE_PORT_SAMPLE_RATE_96K - * - #AFE_PORT_SAMPLE_RATE_192K - */ - - u16 data_format; -/* data format - * Supported values: - * - #LINEAR_PCM_DATA - * - #NON_LINEAR_DATA - * - #LINEAR_PCM_DATA_PACKED_IN_60958 - * - #NON_LINEAR_DATA_PACKED_IN_60958 - */ - u16 reserved; - /* This field must be set to zero. */ -} __packed; - -/* - * This param id is used to configure PCM interface - */ - -#define AFE_API_VERSION_SPDIF_CONFIG 0x1 -#define AFE_API_VERSION_SPDIF_CH_STATUS_CONFIG 0x1 -#define AFE_API_VERSION_SPDIF_CLK_CONFIG 0x1 -#define AFE_CH_STATUS_A 1 -#define AFE_CH_STATUS_B 2 - -#define AFE_PARAM_ID_SPDIF_CONFIG 0x00010244 -#define AFE_PARAM_ID_CH_STATUS_CONFIG 0x00010245 -#define AFE_PARAM_ID_SPDIF_CLK_CONFIG 0x00010246 - -#define AFE_PORT_CLK_ROOT_LPAPLL 0x3 -#define AFE_PORT_CLK_ROOT_LPAQ6PLL 0x4 - -struct afe_param_id_spdif_cfg { -/* Minor version used for tracking the version of the SPDIF - * configuration interface. - * Supported values: #AFE_API_VERSION_SPDIF_CONFIG - */ - u32 spdif_cfg_minor_version; - -/* Sampling rate of the port. - * Supported values: - * - #AFE_PORT_SAMPLE_RATE_22_05K - * - #AFE_PORT_SAMPLE_RATE_32K - * - #AFE_PORT_SAMPLE_RATE_44_1K - * - #AFE_PORT_SAMPLE_RATE_48K - * - #AFE_PORT_SAMPLE_RATE_96K - * - #AFE_PORT_SAMPLE_RATE_176_4K - * - #AFE_PORT_SAMPLE_RATE_192K - */ - u32 sample_rate; - -/* data format - * Supported values: - * - #AFE_LINEAR_PCM_DATA - * - #AFE_NON_LINEAR_DATA - */ - u16 data_format; -/* Number of channels supported by the port - * - PCM - 1, Compressed Case - 2 - */ - u16 num_channels; -/* Bit width of the sample. - * Supported values: 16, 24 - */ - u16 bit_width; -/* This field must be set to zero. */ - u16 reserved; -} __packed; - -struct afe_param_id_spdif_ch_status_cfg { - u32 ch_status_cfg_minor_version; -/* Minor version used for tracking the version of channel - * status configuration. Current supported version is 1 - */ - - u32 status_type; -/* Indicate if the channel status is for channel A or B - * Supported values: - * - #AFE_CH_STATUS_A - * - #AFE_CH_STATUS_B - */ - - u8 status_bits[24]; -/* Channel status - 192 bits for channel - * Byte ordering as defined by IEC60958-3 - */ - - u8 status_mask[24]; -/* Channel status with mask bits 1 will be applied. - * Byte ordering as defined by IEC60958-3 - */ -} __packed; - -struct afe_param_id_spdif_clk_cfg { - u32 clk_cfg_minor_version; -/* Minor version used for tracking the version of SPDIF - * interface clock configuration. Current supported version - * is 1 - */ - - u32 clk_value; -/* Specifies the clock frequency in Hz to set - * Supported values: - * 0 - Disable the clock - * 2 (byphase) * 32 (60958 subframe size) * sampling rate * 2 - * (channels A and B) - */ - - u32 clk_root; -/* Specifies SPDIF root clk source - * Supported Values: - * - #AFE_PORT_CLK_ROOT_LPAPLL - * - #AFE_PORT_CLK_ROOT_LPAQ6PLL - */ -} __packed; - -struct afe_spdif_clk_config_command { - struct apr_hdr hdr; - struct afe_port_cmd_set_param_v2 param; - struct afe_port_param_data_v2 pdata; - struct afe_param_id_spdif_clk_cfg clk_cfg; -} __packed; - -struct afe_spdif_chstatus_config_command { - struct apr_hdr hdr; - struct afe_port_cmd_set_param_v2 param; - struct afe_port_param_data_v2 pdata; - struct afe_param_id_spdif_ch_status_cfg ch_status; -} __packed; - -struct afe_spdif_port_config { - struct afe_param_id_spdif_cfg cfg; - struct afe_param_id_spdif_ch_status_cfg ch_status; -} __packed; - -#define AFE_PARAM_ID_PCM_CONFIG 0x0001020E -#define AFE_API_VERSION_PCM_CONFIG 0x1 -/* Enumeration for the auxiliary PCM synchronization signal - * provided by an external source. - */ - -#define AFE_PORT_PCM_SYNC_SRC_EXTERNAL 0x0 -/* Enumeration for the auxiliary PCM synchronization signal - * provided by an internal source. - */ -#define AFE_PORT_PCM_SYNC_SRC_INTERNAL 0x1 -/* Enumeration for the PCM configuration aux_mode parameter, - * which configures the auxiliary PCM interface to use - * short synchronization. - */ -#define AFE_PORT_PCM_AUX_MODE_PCM 0x0 -/* - * Enumeration for the PCM configuration aux_mode parameter, - * which configures the auxiliary PCM interface to use long - * synchronization. - */ -#define AFE_PORT_PCM_AUX_MODE_AUX 0x1 -/* - * Enumeration for setting the PCM configuration frame to 8. - */ -#define AFE_PORT_PCM_BITS_PER_FRAME_8 0x0 -/* - * Enumeration for setting the PCM configuration frame to 16. - */ -#define AFE_PORT_PCM_BITS_PER_FRAME_16 0x1 - -/* Enumeration for setting the PCM configuration frame to 32.*/ -#define AFE_PORT_PCM_BITS_PER_FRAME_32 0x2 - -/* Enumeration for setting the PCM configuration frame to 64.*/ -#define AFE_PORT_PCM_BITS_PER_FRAME_64 0x3 - -/* Enumeration for setting the PCM configuration frame to 128.*/ -#define AFE_PORT_PCM_BITS_PER_FRAME_128 0x4 - -/* Enumeration for setting the PCM configuration frame to 256.*/ -#define AFE_PORT_PCM_BITS_PER_FRAME_256 0x5 - -/* Enumeration for setting the PCM configuration - * quantype parameter to A-law with no padding. - */ -#define AFE_PORT_PCM_ALAW_NOPADDING 0x0 - -/* Enumeration for setting the PCM configuration quantype - * parameter to mu-law with no padding. - */ -#define AFE_PORT_PCM_MULAW_NOPADDING 0x1 -/* Enumeration for setting the PCM configuration quantype - * parameter to linear with no padding. - */ -#define AFE_PORT_PCM_LINEAR_NOPADDING 0x2 -/* Enumeration for setting the PCM configuration quantype - * parameter to A-law with padding. - */ -#define AFE_PORT_PCM_ALAW_PADDING 0x3 -/* Enumeration for setting the PCM configuration quantype - * parameter to mu-law with padding. - */ -#define AFE_PORT_PCM_MULAW_PADDING 0x4 -/* Enumeration for setting the PCM configuration quantype - * parameter to linear with padding. - */ -#define AFE_PORT_PCM_LINEAR_PADDING 0x5 -/* Enumeration for disabling the PCM configuration - * ctrl_data_out_enable parameter. - * The PCM block is the only master. - */ -#define AFE_PORT_PCM_CTRL_DATA_OE_DISABLE 0x0 -/* - * Enumeration for enabling the PCM configuration - * ctrl_data_out_enable parameter. The PCM block shares - * the signal with other masters. - */ -#define AFE_PORT_PCM_CTRL_DATA_OE_ENABLE 0x1 - -/* Payload of the #AFE_PARAM_ID_PCM_CONFIG command's - * (PCM configuration parameter). - */ - -struct afe_param_id_pcm_cfg { - u32 pcm_cfg_minor_version; -/* Minor version used for tracking the version of the AUX PCM - * configuration interface. - * Supported values: #AFE_API_VERSION_PCM_CONFIG - */ - - u16 aux_mode; -/* PCM synchronization setting. - * Supported values: - * - #AFE_PORT_PCM_AUX_MODE_PCM - * - #AFE_PORT_PCM_AUX_MODE_AUX - */ - - u16 sync_src; -/* Synchronization source. - * Supported values: - * - #AFE_PORT_PCM_SYNC_SRC_EXTERNAL - * - #AFE_PORT_PCM_SYNC_SRC_INTERNAL - */ - - u16 frame_setting; -/* Number of bits per frame. - * Supported values: - * - #AFE_PORT_PCM_BITS_PER_FRAME_8 - * - #AFE_PORT_PCM_BITS_PER_FRAME_16 - * - #AFE_PORT_PCM_BITS_PER_FRAME_32 - * - #AFE_PORT_PCM_BITS_PER_FRAME_64 - * - #AFE_PORT_PCM_BITS_PER_FRAME_128 - * - #AFE_PORT_PCM_BITS_PER_FRAME_256 - */ - - u16 quantype; -/* PCM quantization type. - * Supported values: - * - #AFE_PORT_PCM_ALAW_NOPADDING - * - #AFE_PORT_PCM_MULAW_NOPADDING - * - #AFE_PORT_PCM_LINEAR_NOPADDING - * - #AFE_PORT_PCM_ALAW_PADDING - * - #AFE_PORT_PCM_MULAW_PADDING - * - #AFE_PORT_PCM_LINEAR_PADDING - */ - - u16 ctrl_data_out_enable; -/* Specifies whether the PCM block shares the data-out - * signal to the drive with other masters. - * Supported values: - * - #AFE_PORT_PCM_CTRL_DATA_OE_DISABLE - * - #AFE_PORT_PCM_CTRL_DATA_OE_ENABLE - */ - u16 reserved; - /* This field must be set to zero. */ - - u32 sample_rate; -/* Sampling rate of the port. - * Supported values: - * - #AFE_PORT_SAMPLE_RATE_8K - * - #AFE_PORT_SAMPLE_RATE_16K - */ - - u16 bit_width; -/* Bit width of the sample. - * Supported values: 16 - */ - - u16 num_channels; -/* Number of channels. - * Supported values: 1 to 4 - */ - - u16 slot_number_mapping[4]; -/* Specifies the slot number for the each channel in - * multi channel scenario. - * Supported values: 1 to 32 - */ -} __packed; - -/* - * This param id is used to configure DIGI MIC interface - */ -#define AFE_PARAM_ID_DIGI_MIC_CONFIG 0x0001020F -/* This version information is used to handle the new - * additions to the config interface in future in backward - * compatible manner. - */ -#define AFE_API_VERSION_DIGI_MIC_CONFIG 0x1 - -/* Enumeration for setting the digital mic configuration - * channel_mode parameter to left 0. - */ - -#define AFE_PORT_DIGI_MIC_MODE_LEFT0 0x1 - -/*Enumeration for setting the digital mic configuration - * channel_mode parameter to right 0. - */ - - -#define AFE_PORT_DIGI_MIC_MODE_RIGHT0 0x2 - -/* Enumeration for setting the digital mic configuration - * channel_mode parameter to left 1. - */ - -#define AFE_PORT_DIGI_MIC_MODE_LEFT1 0x3 - -/* Enumeration for setting the digital mic configuration - * channel_mode parameter to right 1. - */ - -#define AFE_PORT_DIGI_MIC_MODE_RIGHT1 0x4 - -/* Enumeration for setting the digital mic configuration - * channel_mode parameter to stereo 0. - */ -#define AFE_PORT_DIGI_MIC_MODE_STEREO0 0x5 - -/* Enumeration for setting the digital mic configuration - * channel_mode parameter to stereo 1. - */ - - -#define AFE_PORT_DIGI_MIC_MODE_STEREO1 0x6 - -/* Enumeration for setting the digital mic configuration - * channel_mode parameter to quad. - */ - -#define AFE_PORT_DIGI_MIC_MODE_QUAD 0x7 - -/* Payload of the #AFE_PARAM_ID_DIGI_MIC_CONFIG command's - * (DIGI MIC configuration - * parameter). - */ -struct afe_param_id_digi_mic_cfg { - u32 digi_mic_cfg_minor_version; -/* Minor version used for tracking the version of the DIGI Mic - * configuration interface. - * Supported values: #AFE_API_VERSION_DIGI_MIC_CONFIG - */ - - u16 bit_width; -/* Bit width of the sample. - * Supported values: 16 - */ - - u16 channel_mode; -/* Digital mic and multichannel operation. - * Supported values: - * - #AFE_PORT_DIGI_MIC_MODE_LEFT0 - * - #AFE_PORT_DIGI_MIC_MODE_RIGHT0 - * - #AFE_PORT_DIGI_MIC_MODE_LEFT1 - * - #AFE_PORT_DIGI_MIC_MODE_RIGHT1 - * - #AFE_PORT_DIGI_MIC_MODE_STEREO0 - * - #AFE_PORT_DIGI_MIC_MODE_STEREO1 - * - #AFE_PORT_DIGI_MIC_MODE_QUAD - */ - - u32 sample_rate; -/* Sampling rate of the port. - * Supported values: - * - #AFE_PORT_SAMPLE_RATE_8K - * - #AFE_PORT_SAMPLE_RATE_16K - * - #AFE_PORT_SAMPLE_RATE_48K - */ -} __packed; - -/* -* This param id is used to configure HDMI interface -*/ -#define AFE_PARAM_ID_HDMI_CONFIG 0x00010210 - -/* This version information is used to handle the new -* additions to the config interface in future in backward -* compatible manner. -*/ -#define AFE_API_VERSION_HDMI_CONFIG 0x1 - -/* Payload of the #AFE_PARAM_ID_HDMI_CONFIG command, - * which configures a multichannel HDMI audio interface. - */ -struct afe_param_id_hdmi_multi_chan_audio_cfg { - u32 hdmi_cfg_minor_version; -/* Minor version used for tracking the version of the HDMI - * configuration interface. - * Supported values: #AFE_API_VERSION_HDMI_CONFIG - */ - -u16 datatype; -/* data type - * Supported values: - * - #LINEAR_PCM_DATA - * - #NON_LINEAR_DATA - * - #LINEAR_PCM_DATA_PACKED_IN_60958 - * - #NON_LINEAR_DATA_PACKED_IN_60958 - */ - -u16 channel_allocation; -/* HDMI channel allocation information for programming an HDMI - * frame. The default is 0 (Stereo). - * - * This information is defined in the HDMI standard, CEA 861-D - * (refer to @xhyperref{S1,[S1]}). The number of channels is also - * inferred from this parameter. -*/ - - -u32 sample_rate; -/* Sampling rate of the port. - * Supported values: - * - #AFE_PORT_SAMPLE_RATE_8K - * - #AFE_PORT_SAMPLE_RATE_16K - * - #AFE_PORT_SAMPLE_RATE_48K - * - #AFE_PORT_SAMPLE_RATE_96K - * - 22050, 44100, 176400 for compressed streams - */ - - u16 bit_width; -/* Bit width of the sample. - * Supported values: 16, 24 - */ - u16 reserved; - /* This field must be set to zero. */ -} __packed; - -/* -* This param id is used to configure BT or FM(RIVA) interface -*/ -#define AFE_PARAM_ID_INTERNAL_BT_FM_CONFIG 0x00010211 - -/* This version information is used to handle the new -* additions to the config interface in future in backward -* compatible manner. -*/ -#define AFE_API_VERSION_INTERNAL_BT_FM_CONFIG 0x1 - -/* Payload of the #AFE_PARAM_ID_INTERNAL_BT_FM_CONFIG - * command's BT voice/BT audio/FM configuration parameter. - */ -struct afe_param_id_internal_bt_fm_cfg { - u32 bt_fm_cfg_minor_version; -/* Minor version used for tracking the version of the BT and FM - * configuration interface. - * Supported values: #AFE_API_VERSION_INTERNAL_BT_FM_CONFIG - */ - - u16 num_channels; -/* Number of channels. - * Supported values: 1 to 2 - */ - - u16 bit_width; -/* Bit width of the sample. - * Supported values: 16 - */ - - u32 sample_rate; -/* Sampling rate of the port. - * Supported values: - * - #AFE_PORT_SAMPLE_RATE_8K (only for BTSCO) - * - #AFE_PORT_SAMPLE_RATE_16K (only for BTSCO) - * - #AFE_PORT_SAMPLE_RATE_48K (FM and A2DP) - */ -} __packed; - -/* This param id is used to configure SLIMBUS interface using - * shared channel approach. - */ - - -#define AFE_PARAM_ID_SLIMBUS_CONFIG 0x00010212 - -/* This version information is used to handle the new -* additions to the config interface in future in backward -* compatible manner. -*/ -#define AFE_API_VERSION_SLIMBUS_CONFIG 0x1 - -/* Enumeration for setting SLIMbus device ID 1. -*/ -#define AFE_SLIMBUS_DEVICE_1 0x0 - -/* Enumeration for setting SLIMbus device ID 2. -*/ -#define AFE_SLIMBUS_DEVICE_2 0x1 - -/* Enumeration for setting the SLIMbus data formats. -*/ -#define AFE_SB_DATA_FORMAT_NOT_INDICATED 0x0 - -/* Enumeration for setting the maximum number of streams per - * device. - */ - -#define AFE_PORT_MAX_AUDIO_CHAN_CNT 0x8 - -/* Payload of the #AFE_PORT_CMD_SLIMBUS_CONFIG command's SLIMbus - * port configuration parameter. - */ - -struct afe_param_id_slimbus_cfg { - u32 sb_cfg_minor_version; -/* Minor version used for tracking the version of the SLIMBUS - * configuration interface. - * Supported values: #AFE_API_VERSION_SLIMBUS_CONFIG - */ - - u16 slimbus_dev_id; -/* SLIMbus hardware device ID, which is required to handle - * multiple SLIMbus hardware blocks. - * Supported values: - #AFE_SLIMBUS_DEVICE_1 - #AFE_SLIMBUS_DEVICE_2 - */ - - - u16 bit_width; -/* Bit width of the sample. - * Supported values: 16, 24 - */ - - u16 data_format; -/* Data format supported by the SLIMbus hardware. The default is - * 0 (#AFE_SB_DATA_FORMAT_NOT_INDICATED), which indicates the - * hardware does not perform any format conversions before the data - * transfer. - */ - - - u16 num_channels; -/* Number of channels. - * Supported values: 1 to #AFE_PORT_MAX_AUDIO_CHAN_CNT - */ - - u8 shared_ch_mapping[AFE_PORT_MAX_AUDIO_CHAN_CNT]; -/* Mapping of shared channel IDs (128 to 255) to which the - * master port is to be connected. - * Shared_channel_mapping[i] represents the shared channel assigned - * for audio channel i in multichannel audio data. - */ - - u32 sample_rate; -/* Sampling rate of the port. - * Supported values: - * - #AFE_PORT_SAMPLE_RATE_8K - * - #AFE_PORT_SAMPLE_RATE_16K - * - #AFE_PORT_SAMPLE_RATE_48K - * - #AFE_PORT_SAMPLE_RATE_96K - * - #AFE_PORT_SAMPLE_RATE_192K - */ -} __packed; - -/* -* This param id is used to configure Real Time Proxy interface. -*/ -#define AFE_PARAM_ID_RT_PROXY_CONFIG 0x00010213 - -/* This version information is used to handle the new -* additions to the config interface in future in backward -* compatible manner. -*/ -#define AFE_API_VERSION_RT_PROXY_CONFIG 0x1 - -/* Payload of the #AFE_PARAM_ID_RT_PROXY_CONFIG - * command (real-time proxy port configuration parameter). - */ -struct afe_param_id_rt_proxy_port_cfg { - u32 rt_proxy_cfg_minor_version; -/* Minor version used for tracking the version of rt-proxy - * config interface. - */ - - u16 bit_width; -/* Bit width of the sample. - * Supported values: 16 - */ - - u16 interleaved; -/* Specifies whether the data exchanged between the AFE - * interface and real-time port is interleaved. - * Supported values: - 0 -- Non-interleaved (samples from each - * channel are contiguous in the buffer) - 1 -- Interleaved - * (corresponding samples from each input channel are interleaved - * within the buffer) - */ - - - u16 frame_size; - /* Size of the frames that are used for PCM exchanges with this - * port. - * Supported values: > 0, in bytes - * For example, 5 ms buffers of 16 bits and 16 kHz stereo samples - * is 5 ms * 16 samples/ms * 2 bytes/sample * 2 channels = 320 - * bytes. - */ - u16 jitter_allowance; -/* Configures the amount of jitter that the port will allow. - * Supported values: > 0 - * For example, if +/-10 ms of jitter is anticipated in the timing - * of sending frames to the port, and the configuration is 16 kHz - * mono with 16-bit samples, this field is 10 ms * 16 samples/ms * 2 - * bytes/sample = 320. - */ - - u16 low_water_mark; -/* Low watermark in bytes (including all channels). - * Supported values: - * - 0 -- Do not send any low watermark events - * - > 0 -- Low watermark for triggering an event - * If the number of bytes in an internal circular buffer is lower - * than this low_water_mark parameter, a LOW_WATER_MARK event is - * sent to applications (via the #AFE_EVENT_RT_PROXY_PORT_STATUS - * event). - * Use of watermark events is optional for debugging purposes. - */ - - u16 high_water_mark; -/* High watermark in bytes (including all channels). - * Supported values: - * - 0 -- Do not send any high watermark events - * - > 0 -- High watermark for triggering an event - * If the number of bytes in an internal circular buffer exceeds - * TOTAL_CIRC_BUF_SIZE minus high_water_mark, a high watermark event - * is sent to applications (via the #AFE_EVENT_RT_PROXY_PORT_STATUS - * event). - * The use of watermark events is optional and for debugging - * purposes. - */ - - - u32 sample_rate; -/* Sampling rate of the port. - * Supported values: - * - #AFE_PORT_SAMPLE_RATE_8K - * - #AFE_PORT_SAMPLE_RATE_16K - * - #AFE_PORT_SAMPLE_RATE_48K - */ - - u16 num_channels; -/* Number of channels. - * Supported values: 1 to #AFE_PORT_MAX_AUDIO_CHAN_CNT - */ - - u16 reserved; - /* For 32 bit alignment. */ -} __packed; - - -/* This param id is used to configure the Pseudoport interface */ - -#define AFE_PARAM_ID_PSEUDO_PORT_CONFIG 0x00010219 - -/* Version information used to handle future additions to the configuration - * interface (for backward compatibility). - */ -#define AFE_API_VERSION_PSEUDO_PORT_CONFIG 0x1 - -/* Enumeration for setting the timing_mode parameter to faster than real - * time. - */ -#define AFE_PSEUDOPORT_TIMING_MODE_FTRT 0x0 - -/* Enumeration for setting the timing_mode parameter to real time using - * timers. - */ -#define AFE_PSEUDOPORT_TIMING_MODE_TIMER 0x1 - -/* Payload of the AFE_PARAM_ID_PSEUDO_PORT_CONFIG parameter used by - AFE_MODULE_AUDIO_DEV_INTERFACE. -*/ -struct afe_param_id_pseudo_port_cfg { - u32 pseud_port_cfg_minor_version; - /* - * Minor version used for tracking the version of the pseudoport - * configuration interface. - */ - - u16 bit_width; - /* Bit width of the sample at values 16, 24 */ - - u16 num_channels; - /* Number of channels at values 1 to 8 */ - - u16 data_format; - /* Non-linear data format supported by the pseudoport (for future use). - * At values #AFE_LINEAR_PCM_DATA - */ - - u16 timing_mode; - /* Indicates whether the pseudoport synchronizes to the clock or - * operates faster than real time. - * at values - * - #AFE_PSEUDOPORT_TIMING_MODE_FTRT - * - #AFE_PSEUDOPORT_TIMING_MODE_TIMER @tablebulletend - */ - - u32 sample_rate; - /* Sample rate at which the pseudoport will run. - * at values - * - #AFE_PORT_SAMPLE_RATE_8K - * - #AFE_PORT_SAMPLE_RATE_32K - * - #AFE_PORT_SAMPLE_RATE_48K - * - #AFE_PORT_SAMPLE_RATE_96K - * - #AFE_PORT_SAMPLE_RATE_192K @tablebulletend - */ -} __packed; - -#define AFE_PARAM_ID_DEVICE_HW_DELAY 0x00010243 -#define AFE_API_VERSION_DEVICE_HW_DELAY 0x1 - -struct afe_param_id_device_hw_delay_cfg { - uint32_t device_hw_delay_minor_version; - uint32_t delay_in_us; -} __packed; - -#define AFE_PARAM_ID_SET_TOPOLOGY 0x0001025A -#define AFE_API_VERSION_TOPOLOGY_V1 0x1 - -struct afe_param_id_set_topology_cfg { - /* - * Minor version used for tracking afe topology id configuration. - * @values #AFE_API_VERSION_TOPOLOGY_V1 - */ - u32 minor_version; - /* - * Id of the topology for the afe session. - * @values Any valid AFE topology ID - */ - u32 topology_id; -} __packed; - -union afe_port_config { - struct afe_param_id_pcm_cfg pcm; - struct afe_param_id_i2s_cfg i2s; - struct afe_param_id_hdmi_multi_chan_audio_cfg hdmi_multi_ch; - struct afe_param_id_slimbus_cfg slim_sch; - struct afe_param_id_rt_proxy_port_cfg rtproxy; - struct afe_param_id_internal_bt_fm_cfg int_bt_fm; - struct afe_param_id_pseudo_port_cfg pseudo_port; - struct afe_param_id_device_hw_delay_cfg hw_delay; - struct afe_param_id_spdif_cfg spdif; - struct afe_param_id_set_topology_cfg topology; -} __packed; - -struct afe_audioif_config_command_no_payload { - struct apr_hdr hdr; - struct afe_port_cmd_set_param_v2 param; -} __packed; - -struct afe_audioif_config_command { - struct apr_hdr hdr; - struct afe_port_cmd_set_param_v2 param; - struct afe_port_param_data_v2 pdata; - union afe_port_config port; -} __packed; - -#define AFE_PORT_CMD_DEVICE_START 0x000100E5 - -/* Payload of the #AFE_PORT_CMD_DEVICE_START.*/ -struct afe_port_cmd_device_start { - struct apr_hdr hdr; - u16 port_id; -/* Port interface and direction (Rx or Tx) to start. An even - * number represents the Rx direction, and an odd number represents - * the Tx direction. - */ - - - u16 reserved; -/* Reserved for 32-bit alignment. This field must be set to 0.*/ - -} __packed; - -#define AFE_PORT_CMD_DEVICE_STOP 0x000100E6 - -/* Payload of the #AFE_PORT_CMD_DEVICE_STOP. -*/ -struct afe_port_cmd_device_stop { - struct apr_hdr hdr; - u16 port_id; -/* Port interface and direction (Rx or Tx) to start. An even - * number represents the Rx direction, and an odd number represents - * the Tx direction. - */ - - u16 reserved; -/* Reserved for 32-bit alignment. This field must be set to 0.*/ -} __packed; - -#define AFE_SERVICE_CMD_SHARED_MEM_MAP_REGIONS 0x000100EA - -/* Memory map regions command payload used by the - * #AFE_SERVICE_CMD_SHARED_MEM_MAP_REGIONS . - * This structure allows clients to map multiple shared memory - * regions in a single command. Following this structure are - * num_regions of afe_service_shared_map_region_payload. - */ -struct afe_service_cmd_shared_mem_map_regions { - struct apr_hdr hdr; -u16 mem_pool_id; -/* Type of memory on which this memory region is mapped. - * Supported values: - * - #ADSP_MEMORY_MAP_EBI_POOL - * - #ADSP_MEMORY_MAP_SMI_POOL - * - #ADSP_MEMORY_MAP_SHMEM8_4K_POOL - * - Other values are reserved - * - * The memory pool ID implicitly defines the characteristics of the - * memory. Characteristics may include alignment type, permissions, - * etc. - * - * ADSP_MEMORY_MAP_EBI_POOL is External Buffer Interface type memory - * ADSP_MEMORY_MAP_SMI_POOL is Shared Memory Interface type memory - * ADSP_MEMORY_MAP_SHMEM8_4K_POOL is shared memory, byte - * addressable, and 4 KB aligned. - */ - - - u16 num_regions; -/* Number of regions to map. - * Supported values: - * - Any value greater than zero - */ - - u32 property_flag; -/* Configures one common property for all the regions in the - * payload. - * - * Supported values: - 0x00000000 to 0x00000001 - * - * b0 - bit 0 indicates physical or virtual mapping 0 Shared memory - * address provided in afe_service_shared_map_region_payloadis a - * physical address. The shared memory needs to be mapped( hardware - * TLB entry) and a software entry needs to be added for internal - * book keeping. - * - * 1 Shared memory address provided in - * afe_service_shared_map_region_payloadis a virtual address. The - * shared memory must not be mapped (since hardware TLB entry is - * already available) but a software entry needs to be added for - * internal book keeping. This can be useful if two services with in - * ADSP is communicating via APR. They can now directly communicate - * via the Virtual address instead of Physical address. The virtual - * regions must be contiguous. num_regions must be 1 in this case. - * - * b31-b1 - reserved bits. must be set to zero - */ - - -} __packed; -/* Map region payload used by the - * afe_service_shared_map_region_payloadstructure. - */ -struct afe_service_shared_map_region_payload { - u32 shm_addr_lsw; -/* least significant word of starting address in the memory - * region to map. It must be contiguous memory, and it must be 4 KB - * aligned. - * Supported values: - Any 32 bit value - */ - - - u32 shm_addr_msw; -/* most significant word of startng address in the memory region - * to map. For 32 bit shared memory address, this field must be set - * to zero. For 36 bit shared memory address, bit31 to bit 4 must be - * set to zero - * - * Supported values: - For 32 bit shared memory address, this field - * must be set to zero. - For 36 bit shared memory address, bit31 to - * bit 4 must be set to zero - For 64 bit shared memory address, any - * 32 bit value - */ - - - u32 mem_size_bytes; -/* Number of bytes in the region. The aDSP will always map the - * regions as virtual contiguous memory, but the memory size must be - * in multiples of 4 KB to avoid gaps in the virtually contiguous - * mapped memory. - * - * Supported values: - multiples of 4KB - */ - -} __packed; - -#define AFE_SERVICE_CMDRSP_SHARED_MEM_MAP_REGIONS 0x000100EB -struct afe_service_cmdrsp_shared_mem_map_regions { - u32 mem_map_handle; -/* A memory map handle encapsulating shared memory attributes is - * returned iff AFE_SERVICE_CMD_SHARED_MEM_MAP_REGIONS command is - * successful. In the case of failure , a generic APR error response - * is returned to the client. - * - * Supported Values: - Any 32 bit value - */ - -} __packed; -#define AFE_SERVICE_CMD_SHARED_MEM_UNMAP_REGIONS 0x000100EC -/* Memory unmap regions command payload used by the - * #AFE_SERVICE_CMD_SHARED_MEM_UNMAP_REGIONS - * - * This structure allows clients to unmap multiple shared memory - * regions in a single command. - */ - - -struct afe_service_cmd_shared_mem_unmap_regions { - struct apr_hdr hdr; -u32 mem_map_handle; -/* memory map handle returned by - * AFE_SERVICE_CMD_SHARED_MEM_MAP_REGIONS commands - * - * Supported Values: - * - Any 32 bit value - */ -} __packed; - -#define AFE_PORT_CMD_GET_PARAM_V2 0x000100F0 - -/* Payload of the #AFE_PORT_CMD_GET_PARAM_V2 command, - * which queries for one post/preprocessing parameter of a - * stream. - */ -struct afe_port_cmd_get_param_v2 { - u16 port_id; -/* Port interface and direction (Rx or Tx) to start. */ - - u16 payload_size; -/* Maximum data size of the parameter ID/module ID combination. - * This is a multiple of four bytes - * Supported values: > 0 - */ - - u32 payload_address_lsw; -/* LSW of 64 bit Payload address. Address should be 32-byte, - * 4kbyte aligned and must be contig memory. - */ - - - u32 payload_address_msw; -/* MSW of 64 bit Payload address. In case of 32-bit shared - * memory address, this field must be set to zero. In case of 36-bit - * shared memory address, bit-4 to bit-31 must be set to zero. - * Address should be 32-byte, 4kbyte aligned and must be contiguous - * memory. - */ - - u32 mem_map_handle; -/* Memory map handle returned by - * AFE_SERVICE_CMD_SHARED_MEM_MAP_REGIONS commands. - * Supported Values: - NULL -- Message. The parameter data is - * in-band. - Non-NULL -- The parameter data is Out-band.Pointer to - * - the physical address in shared memory of the payload data. - * For detailed payload content, see the afe_port_param_data_v2 - * structure - */ - - - u32 module_id; -/* ID of the module to be queried. - * Supported values: Valid module ID - */ - - u32 param_id; -/* ID of the parameter to be queried. - * Supported values: Valid parameter ID - */ -} __packed; - -#define AFE_PORT_CMDRSP_GET_PARAM_V2 0x00010106 - -/* Payload of the #AFE_PORT_CMDRSP_GET_PARAM_V2 message, which - * responds to an #AFE_PORT_CMD_GET_PARAM_V2 command. - * - * Immediately following this structure is the parameters structure - * (afe_port_param_data) containing the response(acknowledgment) - * parameter payload. This payload is included for an in-band - * scenario. For an address/shared memory-based set parameter, this - * payload is not needed. - */ - - -struct afe_port_cmdrsp_get_param_v2 { - u32 status; -} __packed; - -#define AFE_PARAM_ID_LPASS_CORE_SHARED_CLOCK_CONFIG 0x0001028C -#define AFE_API_VERSION_LPASS_CORE_SHARED_CLK_CONFIG 0x1 -/* - * Payload of the AFE_PARAM_ID_LPASS_CORE_SHARED_CLOCK_CONFIG parameter used by - * AFE_MODULE_AUDIO_DEV_INTERFACE. -*/ -struct afe_param_id_lpass_core_shared_clk_cfg { - u32 lpass_core_shared_clk_cfg_minor_version; -/* - * Minor version used for lpass core shared clock configuration - * Supported value: AFE_API_VERSION_LPASS_CORE_SHARED_CLK_CONFIG - */ - u32 enable; -/* - * Specifies whether the lpass core shared clock is - * enabled (1) or disabled (0). - */ -} __packed; - -struct afe_lpass_core_shared_clk_config_command { - struct apr_hdr hdr; - struct afe_port_cmd_set_param_v2 param; - struct afe_port_param_data_v2 pdata; - struct afe_param_id_lpass_core_shared_clk_cfg clk_cfg; -} __packed; - -/* adsp_afe_service_commands.h */ - -#define ADSP_MEMORY_MAP_EBI_POOL 0 - -#define ADSP_MEMORY_MAP_SMI_POOL 1 -#define ADSP_MEMORY_MAP_IMEM_POOL 2 -#define ADSP_MEMORY_MAP_SHMEM8_4K_POOL 3 -/* -* Definition of virtual memory flag -*/ -#define ADSP_MEMORY_MAP_VIRTUAL_MEMORY 1 - -/* -* Definition of physical memory flag -*/ -#define ADSP_MEMORY_MAP_PHYSICAL_MEMORY 0 - -#define NULL_POPP_TOPOLOGY 0x00010C68 -#define NULL_COPP_TOPOLOGY 0x00010312 -#define DEFAULT_COPP_TOPOLOGY 0x00010BE3 -#define DEFAULT_POPP_TOPOLOGY 0x00010BE4 -#define COMPRESSED_PASSTHROUGH_DEFAULT_TOPOLOGY 0x0001076B -#define VPM_TX_SM_ECNS_COPP_TOPOLOGY 0x00010F71 -#define VPM_TX_DM_FLUENCE_COPP_TOPOLOGY 0x00010F72 -#define VPM_TX_QMIC_FLUENCE_COPP_TOPOLOGY 0x00010F75 -#define VPM_TX_DM_RFECNS_COPP_TOPOLOGY 0x00010F86 -#define ADM_CMD_COPP_OPEN_TOPOLOGY_ID_DTS_HPX 0x10015002 - -/* Memory map regions command payload used by the - * #ASM_CMD_SHARED_MEM_MAP_REGIONS ,#ADM_CMD_SHARED_MEM_MAP_REGIONS - * commands. - * - * This structure allows clients to map multiple shared memory - * regions in a single command. Following this structure are - * num_regions of avs_shared_map_region_payload. - */ - - -struct avs_cmd_shared_mem_map_regions { - struct apr_hdr hdr; - u16 mem_pool_id; -/* Type of memory on which this memory region is mapped. - * - * Supported values: - #ADSP_MEMORY_MAP_EBI_POOL - - * #ADSP_MEMORY_MAP_SMI_POOL - #ADSP_MEMORY_MAP_IMEM_POOL - * (unsupported) - #ADSP_MEMORY_MAP_SHMEM8_4K_POOL - Other values - * are reserved - * - * The memory ID implicitly defines the characteristics of the - * memory. Characteristics may include alignment type, permissions, - * etc. - * - * SHMEM8_4K is shared memory, byte addressable, and 4 KB aligned. - */ - - - u16 num_regions; - /* Number of regions to map.*/ - - u32 property_flag; -/* Configures one common property for all the regions in the - * payload. No two regions in the same memory map regions cmd can - * have differnt property. Supported values: - 0x00000000 to - * 0x00000001 - * - * b0 - bit 0 indicates physical or virtual mapping 0 shared memory - * address provided in avs_shared_map_regions_payload is physical - * address. The shared memory needs to be mapped( hardware TLB - * entry) - * - * and a software entry needs to be added for internal book keeping. - * - * 1 Shared memory address provided in MayPayload[usRegions] is - * virtual address. The shared memory must not be mapped (since - * hardware TLB entry is already available) but a software entry - * needs to be added for internal book keeping. This can be useful - * if two services with in ADSP is communicating via APR. They can - * now directly communicate via the Virtual address instead of - * Physical address. The virtual regions must be contiguous. - * - * b31-b1 - reserved bits. must be set to zero - */ - -} __packed; - -struct avs_shared_map_region_payload { - u32 shm_addr_lsw; -/* least significant word of shared memory address of the memory - * region to map. It must be contiguous memory, and it must be 4 KB - * aligned. - */ - - u32 shm_addr_msw; -/* most significant word of shared memory address of the memory - * region to map. For 32 bit shared memory address, this field must - * tbe set to zero. For 36 bit shared memory address, bit31 to bit 4 - * must be set to zero - */ - - u32 mem_size_bytes; -/* Number of bytes in the region. - * - * The aDSP will always map the regions as virtual contiguous - * memory, but the memory size must be in multiples of 4 KB to avoid - * gaps in the virtually contiguous mapped memory. - */ - -} __packed; - -struct avs_cmd_shared_mem_unmap_regions { - struct apr_hdr hdr; - u32 mem_map_handle; -/* memory map handle returned by ASM_CMD_SHARED_MEM_MAP_REGIONS - * , ADM_CMD_SHARED_MEM_MAP_REGIONS, commands - */ - -} __packed; - -/* Memory map command response payload used by the - * #ASM_CMDRSP_SHARED_MEM_MAP_REGIONS - * ,#ADM_CMDRSP_SHARED_MEM_MAP_REGIONS - */ - - -struct avs_cmdrsp_shared_mem_map_regions { - u32 mem_map_handle; -/* A memory map handle encapsulating shared memory attributes is - * returned - */ - -} __packed; - -/*adsp_audio_memmap_api.h*/ - -/* ASM related data structures */ -struct asm_wma_cfg { - u16 format_tag; - u16 ch_cfg; - u32 sample_rate; - u32 avg_bytes_per_sec; - u16 block_align; - u16 valid_bits_per_sample; - u32 ch_mask; - u16 encode_opt; - u16 adv_encode_opt; - u32 adv_encode_opt2; - u32 drc_peak_ref; - u32 drc_peak_target; - u32 drc_ave_ref; - u32 drc_ave_target; -} __packed; - -struct asm_wmapro_cfg { - u16 format_tag; - u16 ch_cfg; - u32 sample_rate; - u32 avg_bytes_per_sec; - u16 block_align; - u16 valid_bits_per_sample; - u32 ch_mask; - u16 encode_opt; - u16 adv_encode_opt; - u32 adv_encode_opt2; - u32 drc_peak_ref; - u32 drc_peak_target; - u32 drc_ave_ref; - u32 drc_ave_target; -} __packed; - -struct asm_aac_cfg { - u16 format; - u16 aot; - u16 ep_config; - u16 section_data_resilience; - u16 scalefactor_data_resilience; - u16 spectral_data_resilience; - u16 ch_cfg; - u16 reserved; - u32 sample_rate; -} __packed; - -struct asm_amrwbplus_cfg { - u32 size_bytes; - u32 version; - u32 num_channels; - u32 amr_band_mode; - u32 amr_dtx_mode; - u32 amr_frame_fmt; - u32 amr_lsf_idx; -} __packed; - -struct asm_flac_cfg { - u32 sample_rate; - u32 ext_sample_rate; - u32 min_frame_size; - u32 max_frame_size; - u16 stream_info_present; - u16 min_blk_size; - u16 max_blk_size; - u16 ch_cfg; - u16 sample_size; - u16 md5_sum; -}; - -struct asm_softpause_params { - u32 enable; - u32 period; - u32 step; - u32 rampingcurve; -} __packed; - -struct asm_softvolume_params { - u32 period; - u32 step; - u32 rampingcurve; -} __packed; - -#define ASM_END_POINT_DEVICE_MATRIX 0 - -#define PCM_CHANNEL_NULL 0 - -/* Front left channel. */ -#define PCM_CHANNEL_FL 1 - -/* Front right channel. */ -#define PCM_CHANNEL_FR 2 - -/* Front center channel. */ -#define PCM_CHANNEL_FC 3 - -/* Left surround channel.*/ -#define PCM_CHANNEL_LS 4 - -/* Right surround channel.*/ -#define PCM_CHANNEL_RS 5 - -/* Low frequency effect channel. */ -#define PCM_CHANNEL_LFE 6 - -/* Center surround channel; Rear center channel. */ -#define PCM_CHANNEL_CS 7 - -/* Left back channel; Rear left channel. */ -#define PCM_CHANNEL_LB 8 - -/* Right back channel; Rear right channel. */ -#define PCM_CHANNEL_RB 9 - -/* Top surround channel. */ -#define PCM_CHANNELS 10 - -/* Center vertical height channel.*/ -#define PCM_CHANNEL_CVH 11 - -/* Mono surround channel.*/ -#define PCM_CHANNEL_MS 12 - -/* Front left of center. */ -#define PCM_CHANNEL_FLC 13 - -/* Front right of center. */ -#define PCM_CHANNEL_FRC 14 - -/* Rear left of center. */ -#define PCM_CHANNEL_RLC 15 - -/* Rear right of center. */ -#define PCM_CHANNEL_RRC 16 - -#define PCM_FORMAT_MAX_NUM_CHANNEL 8 - -#define ASM_MEDIA_FMT_MULTI_CHANNEL_PCM_V2 0x00010DA5 - -#define ASM_MEDIA_FMT_EVRCB_FS 0x00010BEF - -#define ASM_MEDIA_FMT_EVRCWB_FS 0x00010BF0 - -#define ASM_MAX_EQ_BANDS 12 - -#define ASM_DATA_CMD_MEDIA_FMT_UPDATE_V2 0x00010D98 - -struct asm_data_cmd_media_fmt_update_v2 { -u32 fmt_blk_size; - /* Media format block size in bytes.*/ -} __packed; - -struct asm_multi_channel_pcm_fmt_blk_v2 { - struct apr_hdr hdr; - struct asm_data_cmd_media_fmt_update_v2 fmt_blk; - - u16 num_channels; - /* Number of channels. Supported values: 1 to 8 */ - u16 bits_per_sample; -/* Number of bits per sample per channel. * Supported values: - * 16, 24 * When used for playback, the client must send 24-bit - * samples packed in 32-bit words. The 24-bit samples must be placed - * in the most significant 24 bits of the 32-bit word. When used for - * recording, the aDSP sends 24-bit samples packed in 32-bit words. - * The 24-bit samples are placed in the most significant 24 bits of - * the 32-bit word. - */ - - - u32 sample_rate; -/* Number of samples per second (in Hertz). - * Supported values: 2000 to 48000 - */ - - u16 is_signed; - /* Flag that indicates the samples are signed (1). */ - - u16 reserved; - /* reserved field for 32 bit alignment. must be set to zero. */ - - u8 channel_mapping[8]; -/* Channel array of size 8. - * Supported values: - * - #PCM_CHANNEL_L - * - #PCM_CHANNEL_R - * - #PCM_CHANNEL_C - * - #PCM_CHANNEL_LS - * - #PCM_CHANNEL_RS - * - #PCM_CHANNEL_LFE - * - #PCM_CHANNEL_CS - * - #PCM_CHANNEL_LB - * - #PCM_CHANNEL_RB - * - #PCM_CHANNELS - * - #PCM_CHANNEL_CVH - * - #PCM_CHANNEL_MS - * - #PCM_CHANNEL_FLC - * - #PCM_CHANNEL_FRC - * - #PCM_CHANNEL_RLC - * - #PCM_CHANNEL_RRC - * - * Channel[i] mapping describes channel I. Each element i of the - * array describes channel I inside the buffer where 0 @le I < - * num_channels. An unused channel is set to zero. - */ -} __packed; - -struct asm_stream_cmd_set_encdec_param { - u32 param_id; - /* ID of the parameter. */ - - u32 param_size; -/* Data size of this parameter, in bytes. The size is a multiple - * of 4 bytes. - */ - -} __packed; - -struct asm_enc_cfg_blk_param_v2 { - u32 frames_per_buf; -/* Number of encoded frames to pack into each buffer. - * - * @note1hang This is only guidance information for the aDSP. The - * number of encoded frames put into each buffer (specified by the - * client) is less than or equal to this number. - */ - - u32 enc_cfg_blk_size; -/* Size in bytes of the encoder configuration block that follows - * this member. - */ - -} __packed; - -/* @brief Dolby Digital Plus end point configuration structure - */ -struct asm_dec_ddp_endp_param_v2 { - struct apr_hdr hdr; - struct asm_stream_cmd_set_encdec_param encdec; - int endp_param_value; -} __packed; - -/* @brief Multichannel PCM encoder configuration structure used - * in the #ASM_STREAM_CMD_OPEN_READ_V2 command. - */ - -struct asm_multi_channel_pcm_enc_cfg_v2 { - struct apr_hdr hdr; - struct asm_stream_cmd_set_encdec_param encdec; - struct asm_enc_cfg_blk_param_v2 encblk; - uint16_t num_channels; -/*< Number of PCM channels. - * - * Supported values: - 0 -- Native mode - 1 -- 8 Native mode - * indicates that encoding must be performed with the number of - * channels at the input. - */ - - uint16_t bits_per_sample; -/*< Number of bits per sample per channel. - * Supported values: 16, 24 - */ - - uint32_t sample_rate; -/*< Number of samples per second (in Hertz). - * - * Supported values: 0, 8000 to 48000 A value of 0 indicates the - * native sampling rate. Encoding is performed at the input sampling - * rate. - */ - - uint16_t is_signed; -/*< Specifies whether the samples are signed (1). Currently, - * only signed samples are supported. - */ - - uint16_t reserved; -/*< reserved field for 32 bit alignment. must be set to zero.*/ - - - uint8_t channel_mapping[8]; -} __packed; - -#define ASM_MEDIA_FMT_MP3 0x00010BE9 -#define ASM_MEDIA_FMT_AAC_V2 0x00010DA6 - -/* @xreflabel - * {hdr:AsmMediaFmtDolbyAac} Media format ID for the - * Dolby AAC decoder. This format ID is be used if the client wants - * to use the Dolby AAC decoder to decode MPEG2 and MPEG4 AAC - * contents. - */ - -#define ASM_MEDIA_FMT_DOLBY_AAC 0x00010D86 - -/* Enumeration for the audio data transport stream AAC format. */ -#define ASM_MEDIA_FMT_AAC_FORMAT_FLAG_ADTS 0 - -/* Enumeration for low overhead audio stream AAC format. */ -#define ASM_MEDIA_FMT_AAC_FORMAT_FLAG_LOAS 1 - -/* Enumeration for the audio data interchange format - * AAC format. - */ -#define ASM_MEDIA_FMT_AAC_FORMAT_FLAG_ADIF 2 - -/* Enumeration for the raw AAC format. */ -#define ASM_MEDIA_FMT_AAC_FORMAT_FLAG_RAW 3 - -#define ASM_MEDIA_FMT_AAC_AOT_LC 2 -#define ASM_MEDIA_FMT_AAC_AOT_SBR 5 -#define ASM_MEDIA_FMT_AAC_AOT_PS 29 -#define ASM_MEDIA_FMT_AAC_AOT_BSAC 22 - -struct asm_aac_fmt_blk_v2 { - struct apr_hdr hdr; - struct asm_data_cmd_media_fmt_update_v2 fmt_blk; - - u16 aac_fmt_flag; -/* Bitstream format option. - * Supported values: - * - #ASM_MEDIA_FMT_AAC_FORMAT_FLAG_ADTS - * - #ASM_MEDIA_FMT_AAC_FORMAT_FLAG_LOAS - * - #ASM_MEDIA_FMT_AAC_FORMAT_FLAG_ADIF - * - #ASM_MEDIA_FMT_AAC_FORMAT_FLAG_RAW - */ - - u16 audio_objype; -/* Audio Object Type (AOT) present in the AAC stream. - * Supported values: - * - #ASM_MEDIA_FMT_AAC_AOT_LC - * - #ASM_MEDIA_FMT_AAC_AOT_SBR - * - #ASM_MEDIA_FMT_AAC_AOT_BSAC - * - #ASM_MEDIA_FMT_AAC_AOT_PS - * - Otherwise -- Not supported - */ - - u16 channel_config; -/* Number of channels present in the AAC stream. - * Supported values: - * - 1 -- Mono - * - 2 -- Stereo - * - 6 -- 5.1 content - */ - - u16 total_size_of_PCE_bits; -/* greater or equal to zero. * -In case of RAW formats and - * channel config = 0 (PCE), client can send * the bit stream - * containing PCE immediately following this structure * (in-band). - * -This number does not include bits included for 32 bit alignment. - * -If zero, then the PCE info is assumed to be available in the - * audio -bit stream & not in-band. - */ - - u32 sample_rate; -/* Number of samples per second (in Hertz). - * - * Supported values: 8000, 11025, 12000, 16000, 22050, 24000, 32000, - * 44100, 48000 - * - * This field must be equal to the sample rate of the AAC-LC - * decoder's output. - For MP4 or 3GP containers, this is indicated - * by the samplingFrequencyIndex field in the AudioSpecificConfig - * element. - For ADTS format, this is indicated by the - * samplingFrequencyIndex in the ADTS fixed header. - For ADIF - * format, this is indicated by the samplingFrequencyIndex in the - * program_config_element present in the ADIF header. - */ - -} __packed; - -struct asm_aac_enc_cfg_v2 { - struct apr_hdr hdr; - struct asm_stream_cmd_set_encdec_param encdec; - struct asm_enc_cfg_blk_param_v2 encblk; - - u32 bit_rate; - /* Encoding rate in bits per second. */ - u32 enc_mode; -/* Encoding mode. - * Supported values: - * - #ASM_MEDIA_FMT_AAC_AOT_LC - * - #ASM_MEDIA_FMT_AAC_AOT_SBR - * - #ASM_MEDIA_FMT_AAC_AOT_PS - */ - u16 aac_fmt_flag; -/* AAC format flag. - * Supported values: - * - #ASM_MEDIA_FMT_AAC_FORMAT_FLAG_ADTS - * - #ASM_MEDIA_FMT_AAC_FORMAT_FLAG_RAW - */ - u16 channel_cfg; -/* Number of channels to encode. - * Supported values: - * - 0 -- Native mode - * - 1 -- Mono - * - 2 -- Stereo - * - Other values are not supported. - * @note1hang The eAAC+ encoder mode supports only stereo. - * Native mode indicates that encoding must be performed with the - * number of channels at the input. - * The number of channels must not change during encoding. - */ - - u32 sample_rate; -/* Number of samples per second. - * Supported values: - 0 -- Native mode - For other values, - * Native mode indicates that encoding must be performed with the - * sampling rate at the input. - * The sampling rate must not change during encoding. - */ - -} __packed; - -struct asm_flac_fmt_blk_v2 { - struct apr_hdr hdr; - struct asm_data_cmd_media_fmt_update_v2 fmtblk; - - u16 is_stream_info_present; -/* Specifies whether stream information is present in the FLAC format - * block. - * - * Supported values: - * - 0 -- Stream information is not present in this message - * - 1 -- Stream information is present in this message - * - * When set to 1, the FLAC bitstream was successfully parsed by the - * client, and other fields in the FLAC format block can be read by the - * decoder to get metadata stream information. - */ - - u16 num_channels; -/* Number of channels for decoding. - * Supported values: 1 to 2 - */ - - u16 min_blk_size; -/* Minimum block size (in samples) used in the stream. It must be less - * than or equal to max_blk_size. - */ - - u16 max_blk_size; -/* Maximum block size (in samples) used in the stream. If the - * minimum block size equals the maximum block size, a fixed block - * size stream is implied. - */ - - u16 md5_sum[8]; -/* MD5 signature array of the unencoded audio data. This allows the - * decoder to determine if an error exists in the audio data, even when - * the error does not result in an invalid bitstream. - */ - - u32 sample_rate; -/* Number of samples per second. - * Supported values: 8000 to 48000 Hz - */ - - u32 min_frame_size; -/* Minimum frame size used in the stream. - * Supported values: - * - > 0 bytes - * - 0 -- The value is unknown - */ - - u32 max_frame_size; -/* Maximum frame size used in the stream. - * Supported values: - * -- > 0 bytes - * -- 0 . The value is unknown - */ - - u16 sample_size; -/* Bits per sample.Supported values: 8, 16 */ - - u16 reserved; -/* Clients must set this field to zero - */ - -} __packed; - -#define ASM_MEDIA_FMT_AMRNB_FS 0x00010BEB - -/* Enumeration for 4.75 kbps AMR-NB Encoding mode. */ -#define ASM_MEDIA_FMT_AMRNB_FS_ENCODE_MODE_MR475 0 - -/* Enumeration for 5.15 kbps AMR-NB Encoding mode. */ -#define ASM_MEDIA_FMT_AMRNB_FS_ENCODE_MODE_MR515 1 - -/* Enumeration for 5.90 kbps AMR-NB Encoding mode. */ -#define ASM_MEDIA_FMT_AMRNB_FS_ENCODE_MODE_MMR59 2 - -/* Enumeration for 6.70 kbps AMR-NB Encoding mode. */ -#define ASM_MEDIA_FMT_AMRNB_FS_ENCODE_MODE_MMR67 3 - -/* Enumeration for 7.40 kbps AMR-NB Encoding mode. */ -#define ASM_MEDIA_FMT_AMRNB_FS_ENCODE_MODE_MMR74 4 - -/* Enumeration for 7.95 kbps AMR-NB Encoding mode. */ -#define ASM_MEDIA_FMT_AMRNB_FS_ENCODE_MODE_MMR795 5 - -/* Enumeration for 10.20 kbps AMR-NB Encoding mode. */ -#define ASM_MEDIA_FMT_AMRNB_FS_ENCODE_MODE_MMR102 6 - -/* Enumeration for 12.20 kbps AMR-NB Encoding mode. */ -#define ASM_MEDIA_FMT_AMRNB_FS_ENCODE_MODE_MMR122 7 - -/* Enumeration for AMR-NB Discontinuous Transmission mode off. */ -#define ASM_MEDIA_FMT_AMRNB_FS_DTX_MODE_OFF 0 - -/* Enumeration for AMR-NB DTX mode VAD1. */ -#define ASM_MEDIA_FMT_AMRNB_FS_DTX_MODE_VAD1 1 - -/* Enumeration for AMR-NB DTX mode VAD2. */ -#define ASM_MEDIA_FMT_AMRNB_FS_DTX_MODE_VAD2 2 - -/* Enumeration for AMR-NB DTX mode auto. - */ -#define ASM_MEDIA_FMT_AMRNB_FS_DTX_MODE_AUTO 3 - -struct asm_amrnb_enc_cfg { - struct apr_hdr hdr; - struct asm_stream_cmd_set_encdec_param encdec; - struct asm_enc_cfg_blk_param_v2 encblk; - - u16 enc_mode; -/* AMR-NB encoding rate. - * Supported values: - * Use the ASM_MEDIA_FMT_AMRNB_FS_ENCODE_MODE_* - * macros - */ - - u16 dtx_mode; -/* Specifies whether DTX mode is disabled or enabled. - * Supported values: - * - #ASM_MEDIA_FMT_AMRNB_FS_DTX_MODE_OFF - * - #ASM_MEDIA_FMT_AMRNB_FS_DTX_MODE_VAD1 - */ -} __packed; - -#define ASM_MEDIA_FMT_AMRWB_FS 0x00010BEC - -/* Enumeration for 6.6 kbps AMR-WB Encoding mode. */ -#define ASM_MEDIA_FMT_AMRWB_FS_ENCODE_MODE_MR66 0 - -/* Enumeration for 8.85 kbps AMR-WB Encoding mode. */ -#define ASM_MEDIA_FMT_AMRWB_FS_ENCODE_MODE_MR885 1 - -/* Enumeration for 12.65 kbps AMR-WB Encoding mode. */ -#define ASM_MEDIA_FMT_AMRWB_FS_ENCODE_MODE_MR1265 2 - -/* Enumeration for 14.25 kbps AMR-WB Encoding mode. */ -#define ASM_MEDIA_FMT_AMRWB_FS_ENCODE_MODE_MR1425 3 - -/* Enumeration for 15.85 kbps AMR-WB Encoding mode. */ -#define ASM_MEDIA_FMT_AMRWB_FS_ENCODE_MODE_MR1585 4 - -/* Enumeration for 18.25 kbps AMR-WB Encoding mode. */ -#define ASM_MEDIA_FMT_AMRWB_FS_ENCODE_MODE_MR1825 5 - -/* Enumeration for 19.85 kbps AMR-WB Encoding mode. */ -#define ASM_MEDIA_FMT_AMRWB_FS_ENCODE_MODE_MR1985 6 - -/* Enumeration for 23.05 kbps AMR-WB Encoding mode. */ -#define ASM_MEDIA_FMT_AMRWB_FS_ENCODE_MODE_MR2305 7 - -/* Enumeration for 23.85 kbps AMR-WB Encoding mode. - */ -#define ASM_MEDIA_FMT_AMRWB_FS_ENCODE_MODE_MR2385 8 - -struct asm_amrwb_enc_cfg { - struct apr_hdr hdr; - struct asm_stream_cmd_set_encdec_param encdec; - struct asm_enc_cfg_blk_param_v2 encblk; - - u16 enc_mode; -/* AMR-WB encoding rate. - * Suupported values: - * Use the ASM_MEDIA_FMT_AMRWB_FS_ENCODE_MODE_* - * macros - */ - - u16 dtx_mode; -/* Specifies whether DTX mode is disabled or enabled. - * Supported values: - * - #ASM_MEDIA_FMT_AMRNB_FS_DTX_MODE_OFF - * - #ASM_MEDIA_FMT_AMRNB_FS_DTX_MODE_VAD1 - */ -} __packed; - -#define ASM_MEDIA_FMT_V13K_FS 0x00010BED - -/* Enumeration for 14.4 kbps V13K Encoding mode. */ -#define ASM_MEDIA_FMT_V13K_FS_ENCODE_MODE_MR1440 0 - -/* Enumeration for 12.2 kbps V13K Encoding mode. */ -#define ASM_MEDIA_FMT_V13K_FS_ENCODE_MODE_MR1220 1 - -/* Enumeration for 11.2 kbps V13K Encoding mode. */ -#define ASM_MEDIA_FMT_V13K_FS_ENCODE_MODE_MR1120 2 - -/* Enumeration for 9.0 kbps V13K Encoding mode. */ -#define ASM_MEDIA_FMT_V13K_FS_ENCODE_MODE_MR90 3 - -/* Enumeration for 7.2 kbps V13K eEncoding mode. */ -#define ASM_MEDIA_FMT_V13K_FS_ENCODE_MODE_MR720 4 - -/* Enumeration for 1/8 vocoder rate.*/ -#define ASM_MEDIA_FMT_VOC_ONE_EIGHTH_RATE 1 - -/* Enumeration for 1/4 vocoder rate. */ -#define ASM_MEDIA_FMT_VOC_ONE_FOURTH_RATE 2 - -/* Enumeration for 1/2 vocoder rate. */ -#define ASM_MEDIA_FMT_VOC_HALF_RATE 3 - -/* Enumeration for full vocoder rate. - */ -#define ASM_MEDIA_FMT_VOC_FULL_RATE 4 - -struct asm_v13k_enc_cfg { - struct apr_hdr hdr; - struct asm_stream_cmd_set_encdec_param encdec; - struct asm_enc_cfg_blk_param_v2 encblk; - u16 max_rate; -/* Maximum allowed encoder frame rate. - * Supported values: - * - #ASM_MEDIA_FMT_VOC_ONE_EIGHTH_RATE - * - #ASM_MEDIA_FMT_VOC_ONE_FOURTH_RATE - * - #ASM_MEDIA_FMT_VOC_HALF_RATE - * - #ASM_MEDIA_FMT_VOC_FULL_RATE - */ - - u16 min_rate; -/* Minimum allowed encoder frame rate. - * Supported values: - * - #ASM_MEDIA_FMT_VOC_ONE_EIGHTH_RATE - * - #ASM_MEDIA_FMT_VOC_ONE_FOURTH_RATE - * - #ASM_MEDIA_FMT_VOC_HALF_RATE - * - #ASM_MEDIA_FMT_VOC_FULL_RATE - */ - - u16 reduced_rate_cmd; -/* Reduced rate command, used to change - * the average bitrate of the V13K - * vocoder. - * Supported values: - * - #ASM_MEDIA_FMT_V13K_FS_ENCODE_MODE_MR1440 (Default) - * - #ASM_MEDIA_FMT_V13K_FS_ENCODE_MODE_MR1220 - * - #ASM_MEDIA_FMT_V13K_FS_ENCODE_MODE_MR1120 - * - #ASM_MEDIA_FMT_V13K_FS_ENCODE_MODE_MR90 - * - #ASM_MEDIA_FMT_V13K_FS_ENCODE_MODE_MR720 - */ - - u16 rate_mod_cmd; -/* Rate modulation command. Default = 0. - *- If bit 0=1, rate control is enabled. - *- If bit 1=1, the maximum number of consecutive full rate - * frames is limited with numbers supplied in - * bits 2 to 10. - *- If bit 1=0, the minimum number of non-full rate frames - * in between two full rate frames is forced to - * the number supplied in bits 2 to 10. In both cases, if necessary, - * half rate is used to substitute full rate. - Bits 15 to 10 are - * reserved and must all be set to zero. - */ - -} __packed; - -#define ASM_MEDIA_FMT_EVRC_FS 0x00010BEE - -/* EVRC encoder configuration structure used in the - * #ASM_STREAM_CMD_OPEN_READ_V2 command. - */ -struct asm_evrc_enc_cfg { - struct apr_hdr hdr; - struct asm_stream_cmd_set_encdec_param encdec; - struct asm_enc_cfg_blk_param_v2 encblk; - u16 max_rate; -/* Maximum allowed encoder frame rate. - * Supported values: - * - #ASM_MEDIA_FMT_VOC_ONE_EIGHTH_RATE - * - #ASM_MEDIA_FMT_VOC_ONE_FOURTH_RATE - * - #ASM_MEDIA_FMT_VOC_HALF_RATE - * - #ASM_MEDIA_FMT_VOC_FULL_RATE - */ - - u16 min_rate; -/* Minimum allowed encoder frame rate. - * Supported values: - * - #ASM_MEDIA_FMT_VOC_ONE_EIGHTH_RATE - * - #ASM_MEDIA_FMT_VOC_ONE_FOURTH_RATE - * - #ASM_MEDIA_FMT_VOC_HALF_RATE - * - #ASM_MEDIA_FMT_VOC_FULL_RATE - */ - - u16 rate_mod_cmd; -/* Rate modulation command. Default: 0. - * - If bit 0=1, rate control is enabled. - * - If bit 1=1, the maximum number of consecutive full rate frames - * is limited with numbers supplied in bits 2 to 10. - * - * - If bit 1=0, the minimum number of non-full rate frames in - * between two full rate frames is forced to the number supplied in - * bits 2 to 10. In both cases, if necessary, half rate is used to - * substitute full rate. - * - * - Bits 15 to 10 are reserved and must all be set to zero. - */ - - u16 reserved; - /* Reserved. Clients must set this field to zero. */ -} __packed; - -#define ASM_MEDIA_FMT_WMA_V10PRO_V2 0x00010DA7 - -struct asm_wmaprov10_fmt_blk_v2 { - struct apr_hdr hdr; - struct asm_data_cmd_media_fmt_update_v2 fmtblk; - - u16 fmtag; -/* WMA format type. - * Supported values: - * - 0x162 -- WMA 9 Pro - * - 0x163 -- WMA 9 Pro Lossless - * - 0x166 -- WMA 10 Pro - * - 0x167 -- WMA 10 Pro Lossless - */ - - u16 num_channels; -/* Number of channels encoded in the input stream. - * Supported values: 1 to 8 - */ - - u32 sample_rate; -/* Number of samples per second (in Hertz). - * Supported values: 11025, 16000, 22050, 32000, 44100, 48000, - * 88200, 96000 - */ - - u32 avg_bytes_per_sec; -/* Bitrate expressed as the average bytes per second. - * Supported values: 2000 to 96000 - */ - - u16 blk_align; -/* Size of the bitstream packet size in bytes. WMA Pro files - * have a payload of one block per bitstream packet. - * Supported values: @le 13376 - */ - - u16 bits_per_sample; -/* Number of bits per sample in the encoded WMA stream. - * Supported values: 16, 24 - */ - - u32 channel_mask; -/* Bit-packed double word (32-bits) that indicates the - * recommended speaker positions for each source channel. - */ - - u16 enc_options; -/* Bit-packed word with values that indicate whether certain - * features of the bitstream are used. - * Supported values: - 0x0001 -- ENCOPT3_PURE_LOSSLESS - 0x0006 -- - * ENCOPT3_FRM_SIZE_MOD - 0x0038 -- ENCOPT3_SUBFRM_DIV - 0x0040 -- - * ENCOPT3_WRITE_FRAMESIZE_IN_HDR - 0x0080 -- - * ENCOPT3_GENERATE_DRC_PARAMS - 0x0100 -- ENCOPT3_RTMBITS - */ - - - u16 usAdvancedEncodeOpt; - /* Advanced encoding option. */ - - u32 advanced_enc_options2; - /* Advanced encoding option 2. */ - -} __packed; - -#define ASM_MEDIA_FMT_WMA_V9_V2 0x00010DA8 -struct asm_wmastdv9_fmt_blk_v2 { - struct apr_hdr hdr; - struct asm_data_cmd_media_fmt_update_v2 fmtblk; - u16 fmtag; -/* WMA format tag. - * Supported values: 0x161 (WMA 9 standard) - */ - - u16 num_channels; -/* Number of channels in the stream. - * Supported values: 1, 2 - */ - - u32 sample_rate; -/* Number of samples per second (in Hertz). - * Supported values: 48000 - */ - - u32 avg_bytes_per_sec; - /* Bitrate expressed as the average bytes per second. */ - - u16 blk_align; -/* Block align. All WMA files with a maximum packet size of - * 13376 are supported. - */ - - - u16 bits_per_sample; -/* Number of bits per sample in the output. - * Supported values: 16 - */ - - u32 channel_mask; -/* Channel mask. - * Supported values: - * - 3 -- Stereo (front left/front right) - * - 4 -- Mono (center) - */ - - u16 enc_options; - /* Options used during encoding. */ - - u16 reserved; - -} __packed; - -#define ASM_MEDIA_FMT_WMA_V8 0x00010D91 - -struct asm_wmastdv8_enc_cfg { - struct apr_hdr hdr; - struct asm_stream_cmd_set_encdec_param encdec; - struct asm_enc_cfg_blk_param_v2 encblk; - u32 bit_rate; - /* Encoding rate in bits per second. */ - - u32 sample_rate; -/* Number of samples per second. - * - * Supported values: - * - 0 -- Native mode - * - Other Supported values are 22050, 32000, 44100, and 48000. - * - * Native mode indicates that encoding must be performed with the - * sampling rate at the input. - * The sampling rate must not change during encoding. - */ - - u16 channel_cfg; -/* Number of channels to encode. - * Supported values: - * - 0 -- Native mode - * - 1 -- Mono - * - 2 -- Stereo - * - Other values are not supported. - * - * Native mode indicates that encoding must be performed with the - * number of channels at the input. - * The number of channels must not change during encoding. - */ - - u16 reserved; - /* Reserved. Clients must set this field to zero.*/ - } __packed; - -#define ASM_MEDIA_FMT_AMR_WB_PLUS_V2 0x00010DA9 - -struct asm_amrwbplus_fmt_blk_v2 { - struct apr_hdr hdr; - struct asm_data_cmd_media_fmt_update_v2 fmtblk; - u32 amr_frame_fmt; -/* AMR frame format. - * Supported values: - * - 6 -- Transport Interface Format (TIF) - * - Any other value -- File storage format (FSF) - * - * TIF stream contains 2-byte header for each frame within the - * superframe. FSF stream contains one 2-byte header per superframe. - */ - -} __packed; - -#define ASM_MEDIA_FMT_AC3_DEC 0x00010BF6 -#define ASM_MEDIA_FMT_EAC3_DEC 0x00010C3C -#define ASM_MEDIA_FMT_DTS 0x00010D88 -#define ASM_MEDIA_FMT_MP2 0x00010DE9 -#define ASM_MEDIA_FMT_FLAC 0x00010C16 - - -/* Media format ID for adaptive transform acoustic coding. This - * ID is used by the #ASM_STREAM_CMD_OPEN_WRITE_COMPRESSED command - * only. - */ - -#define ASM_MEDIA_FMT_ATRAC 0x00010D89 - -/* Media format ID for metadata-enhanced audio transmission. - * This ID is used by the #ASM_STREAM_CMD_OPEN_WRITE_COMPRESSED - * command only. - */ - -#define ASM_MEDIA_FMT_MAT 0x00010D8A - -/* adsp_media_fmt.h */ - -#define ASM_DATA_CMD_WRITE_V2 0x00010DAB - -struct asm_data_cmd_write_v2 { - struct apr_hdr hdr; - u32 buf_addr_lsw; -/* The 64 bit address msw-lsw should be a valid, mapped address. - * 64 bit address should be a multiple of 32 bytes - */ - - u32 buf_addr_msw; -/* The 64 bit address msw-lsw should be a valid, mapped address. - * 64 bit address should be a multiple of 32 bytes. - * -Address of the buffer containing the data to be decoded. - * The buffer should be aligned to a 32 byte boundary. - * -In the case of 32 bit Shared memory address, msw field must - * -be set to zero. - * -In the case of 36 bit shared memory address, bit 31 to bit 4 - * -of msw must be set to zero. - */ - u32 mem_map_handle; -/* memory map handle returned by DSP through - * ASM_CMD_SHARED_MEM_MAP_REGIONS command - */ - u32 buf_size; -/* Number of valid bytes available in the buffer for decoding. The - * first byte starts at buf_addr. - */ - - u32 seq_id; - /* Optional buffer sequence ID. */ - - u32 timestamp_lsw; -/* Lower 32 bits of the 64-bit session time in microseconds of the - * first buffer sample. - */ - - u32 timestamp_msw; -/* Upper 32 bits of the 64-bit session time in microseconds of the - * first buffer sample. - */ - - u32 flags; -/* Bitfield of flags. - * Supported values for bit 31: - * - 1 -- Valid timestamp. - * - 0 -- Invalid timestamp. - * - Use #ASM_BIT_MASKIMESTAMP_VALID_FLAG as the bitmask and - * #ASM_SHIFTIMESTAMP_VALID_FLAG as the shift value to set this bit. - * Supported values for bit 30: - * - 1 -- Last buffer. - * - 0 -- Not the last buffer. - * - * Supported values for bit 29: - * - 1 -- Continue the timestamp from the previous buffer. - * - 0 -- Timestamp of the current buffer is not related - * to the timestamp of the previous buffer. - * - Use #ASM_BIT_MASKS_CONTINUE_FLAG and #ASM_SHIFTS_CONTINUE_FLAG - * to set this bit. - * - * Supported values for bit 4: - * - 1 -- End of the frame. - * - 0 -- Not the end of frame, or this information is not known. - * - Use #ASM_BIT_MASK_EOF_FLAG as the bitmask and #ASM_SHIFT_EOF_FLAG - * as the shift value to set this bit. - * - * All other bits are reserved and must be set to 0. - * - * If bit 31=0 and bit 29=1: The timestamp of the first sample in - * this buffer continues from the timestamp of the last sample in - * the previous buffer. If there is no previous buffer (i.e., this - * is the first buffer sent after opening the stream or after a - * flush operation), or if the previous buffer does not have a valid - * timestamp, the samples in the current buffer also do not have a - * valid timestamp. They are played out as soon as possible. - * - * - * If bit 31=0 and bit 29=0: No timestamp is associated with the - * first sample in this buffer. The samples are played out as soon - * as possible. - * - * - * If bit 31=1 and bit 29 is ignored: The timestamp specified in - * this payload is honored. - * - * - * If bit 30=0: Not the last buffer in the stream. This is useful - * in removing trailing samples. - * - * - * For bit 4: The client can set this flag for every buffer sent in - * which the last byte is the end of a frame. If this flag is set, - * the buffer can contain data from multiple frames, but it should - * always end at a frame boundary. Restrictions allow the aDSP to - * detect an end of frame without requiring additional processing. - */ - -} __packed; - -#define ASM_DATA_CMD_READ_V2 0x00010DAC - -struct asm_data_cmd_read_v2 { - struct apr_hdr hdr; - u32 buf_addr_lsw; -/* the 64 bit address msw-lsw should be a valid mapped address - * and should be a multiple of 32 bytes - */ - - - u32 buf_addr_msw; -/* the 64 bit address msw-lsw should be a valid mapped address - * and should be a multiple of 32 bytes. -* - Address of the buffer where the DSP puts the encoded data, -* potentially, at an offset specified by the uOffset field in -* ASM_DATA_EVENT_READ_DONE structure. The buffer should be aligned -* to a 32 byte boundary. -*- In the case of 32 bit Shared memory address, msw field must -*- be set to zero. -*- In the case of 36 bit shared memory address, bit 31 to bit -*- 4 of msw must be set to zero. -*/ - u32 mem_map_handle; -/* memory map handle returned by DSP through - * ASM_CMD_SHARED_MEM_MAP_REGIONS command. - */ - - u32 buf_size; -/* Number of bytes available for the aDSP to write. The aDSP - * starts writing from buf_addr. - */ - - u32 seq_id; - /* Optional buffer sequence ID. - */ -} __packed; - -#define ASM_DATA_CMD_EOS 0x00010BDB -#define ASM_DATA_EVENT_RENDERED_EOS 0x00010C1C -#define ASM_DATA_EVENT_EOS 0x00010BDD - -#define ASM_DATA_EVENT_WRITE_DONE_V2 0x00010D99 -struct asm_data_event_write_done_v2 { - u32 buf_addr_lsw; - /* lsw of the 64 bit address */ - u32 buf_addr_msw; - /* msw of the 64 bit address. address given by the client in - * ASM_DATA_CMD_WRITE_V2 command. - */ - u32 mem_map_handle; - /* memory map handle in the ASM_DATA_CMD_WRITE_V2 */ - - u32 status; -/* Status message (error code) that indicates whether the - * referenced buffer has been successfully consumed. - * Supported values: Refer to @xhyperref{Q3,[Q3]} - */ -} __packed; - -#define ASM_DATA_EVENT_READ_DONE_V2 0x00010D9A - -/* Definition of the frame metadata flag bitmask.*/ -#define ASM_BIT_MASK_FRAME_METADATA_FLAG (0x40000000UL) - -/* Definition of the frame metadata flag shift value. */ -#define ASM_SHIFT_FRAME_METADATA_FLAG 30 - -struct asm_data_event_read_done_v2 { - u32 status; -/* Status message (error code). - * Supported values: Refer to @xhyperref{Q3,[Q3]} - */ - -u32 buf_addr_lsw; -/* 64 bit address msw-lsw is a valid, mapped address. 64 bit - * address is a multiple of 32 bytes. - */ - -u32 buf_addr_msw; -/* 64 bit address msw-lsw is a valid, mapped address. 64 bit -* address is a multiple of 32 bytes. -* -* -Same address provided by the client in ASM_DATA_CMD_READ_V2 -* -In the case of 32 bit Shared memory address, msw field is set to -* zero. -* -In the case of 36 bit shared memory address, bit 31 to bit 4 -* -of msw is set to zero. -*/ - -u32 mem_map_handle; -/* memory map handle in the ASM_DATA_CMD_READ_V2 */ - -u32 enc_framesotal_size; -/* Total size of the encoded frames in bytes. - * Supported values: >0 - */ - -u32 offset; -/* Offset (from buf_addr) to the first byte of the first encoded - * frame. All encoded frames are consecutive, starting from this - * offset. - * Supported values: > 0 - */ - -u32 timestamp_lsw; -/* Lower 32 bits of the 64-bit session time in microseconds of - * the first sample in the buffer. If Bit 5 of mode_flags flag of - * ASM_STREAM_CMD_OPEN_READ_V2 is 1 then the 64 bit timestamp is - * absolute capture time otherwise it is relative session time. The - * absolute timestamp doesnt reset unless the system is reset. - */ - - -u32 timestamp_msw; -/* Upper 32 bits of the 64-bit session time in microseconds of - * the first sample in the buffer. - */ - - -u32 flags; -/* Bitfield of flags. Bit 30 indicates whether frame metadata is - * present. If frame metadata is present, num_frames consecutive - * instances of @xhyperref{hdr:FrameMetaData,Frame metadata} start - * at the buffer address. - * Supported values for bit 31: - * - 1 -- Timestamp is valid. - * - 0 -- Timestamp is invalid. - * - Use #ASM_BIT_MASKIMESTAMP_VALID_FLAG and - * #ASM_SHIFTIMESTAMP_VALID_FLAG to set this bit. - * - * Supported values for bit 30: - * - 1 -- Frame metadata is present. - * - 0 -- Frame metadata is absent. - * - Use #ASM_BIT_MASK_FRAME_METADATA_FLAG and - * #ASM_SHIFT_FRAME_METADATA_FLAG to set this bit. - * - * All other bits are reserved; the aDSP sets them to 0. - */ - -u32 num_frames; -/* Number of encoded frames in the buffer. */ - -u32 seq_id; -/* Optional buffer sequence ID. */ -} __packed; - -struct asm_data_read_buf_metadata_v2 { - u32 offset; -/* Offset from buf_addr in #ASM_DATA_EVENT_READ_DONE_PAYLOAD to - * the frame associated with this metadata. - * Supported values: > 0 - */ - -u32 frm_size; -/* Size of the encoded frame in bytes. - * Supported values: > 0 - */ - -u32 num_encoded_pcm_samples; -/* Number of encoded PCM samples (per channel) in the frame - * associated with this metadata. - * Supported values: > 0 - */ - -u32 timestamp_lsw; -/* Lower 32 bits of the 64-bit session time in microseconds of the - * first sample for this frame. - * If Bit 5 of mode_flags flag of ASM_STREAM_CMD_OPEN_READ_V2 is 1 - * then the 64 bit timestamp is absolute capture time otherwise it - * is relative session time. The absolute timestamp doesnt reset - * unless the system is reset. - */ - - -u32 timestamp_msw; -/* Lower 32 bits of the 64-bit session time in microseconds of the - * first sample for this frame. - */ - -u32 flags; -/* Frame flags. - * Supported values for bit 31: - * - 1 -- Time stamp is valid - * - 0 -- Time stamp is not valid - * - All other bits are reserved; the aDSP sets them to 0. -*/ -} __packed; - -/* Notifies the client of a change in the data sampling rate or - * Channel mode. This event is raised by the decoder service. The - * event is enabled through the mode flags of - * #ASM_STREAM_CMD_OPEN_WRITE_V2 or - * #ASM_STREAM_CMD_OPEN_READWRITE_V2. - The decoder detects a change - * in the output sampling frequency or the number/positioning of - * output channels, or if it is the first frame decoded.The new - * sampling frequency or the new channel configuration is - * communicated back to the client asynchronously. - */ - -#define ASM_DATA_EVENT_SR_CM_CHANGE_NOTIFY 0x00010C65 - -/* Payload of the #ASM_DATA_EVENT_SR_CM_CHANGE_NOTIFY event. - * This event is raised when the following conditions are both true: - * - The event is enabled through the mode_flags of - * #ASM_STREAM_CMD_OPEN_WRITE_V2 or - * #ASM_STREAM_CMD_OPEN_READWRITE_V2. - The decoder detects a change - * in either the output sampling frequency or the number/positioning - * of output channels, or if it is the first frame decoded. - * This event is not raised (even if enabled) if the decoder is - * MIDI, because - */ - - -struct asm_data_event_sr_cm_change_notify { - u32 sample_rate; -/* New sampling rate (in Hertz) after detecting a change in the - * bitstream. - * Supported values: 2000 to 48000 - */ - - u16 num_channels; -/* New number of channels after detecting a change in the - * bitstream. - * Supported values: 1 to 8 - */ - - - u16 reserved; - /* Reserved for future use. This field must be set to 0.*/ - - u8 channel_mapping[8]; - -} __packed; - -/* Notifies the client of a data sampling rate or channel mode - * change. This event is raised by the encoder service. - * This event is raised when : - * - Native mode encoding was requested in the encoder - * configuration (i.e., the channel number was 0), the sample rate - * was 0, or both were 0. - * - * - The input data frame at the encoder is the first one, or the - * sampling rate/channel mode is different from the previous input - * data frame. - * - */ -#define ASM_DATA_EVENT_ENC_SR_CM_CHANGE_NOTIFY 0x00010BDE - -struct asm_data_event_enc_sr_cm_change_notify { - u32 sample_rate; -/* New sampling rate (in Hertz) after detecting a change in the - * input data. - * Supported values: 2000 to 48000 - */ - - - u16 num_channels; -/* New number of channels after detecting a change in the input - * data. Supported values: 1 to 8 - */ - - - u16 bits_per_sample; -/* New bits per sample after detecting a change in the input - * data. - * Supported values: 16, 24 - */ - - - u8 channel_mapping[8]; - -} __packed; -#define ASM_DATA_CMD_IEC_60958_FRAME_RATE 0x00010D87 - - -/* Payload of the #ASM_DATA_CMD_IEC_60958_FRAME_RATE command, - * which is used to indicate the IEC 60958 frame rate of a given - * packetized audio stream. - */ - -struct asm_data_cmd_iec_60958_frame_rate { - u32 frame_rate; -/* IEC 60958 frame rate of the incoming IEC 61937 packetized stream. - * Supported values: Any valid frame rate - */ -} __packed; - -/* adsp_asm_data_commands.h*/ -#define ASM_SVC_CMD_GET_STREAM_HANDLES 0x00010C0B - -#define ASM_SVC_CMDRSP_GET_STREAM_HANDLES 0x00010C1B - -/* Definition of the stream ID bitmask.*/ -#define ASM_BIT_MASK_STREAM_ID (0x000000FFUL) - -/* Definition of the stream ID shift value.*/ -#define ASM_SHIFT_STREAM_ID 0 - -/* Definition of the session ID bitmask.*/ -#define ASM_BIT_MASK_SESSION_ID (0x0000FF00UL) - -/* Definition of the session ID shift value.*/ -#define ASM_SHIFT_SESSION_ID 8 - -/* Definition of the service ID bitmask.*/ -#define ASM_BIT_MASK_SERVICE_ID (0x00FF0000UL) - -/* Definition of the service ID shift value.*/ -#define ASM_SHIFT_SERVICE_ID 16 - -/* Definition of the domain ID bitmask.*/ -#define ASM_BIT_MASK_DOMAIN_ID (0xFF000000UL) - -/* Definition of the domain ID shift value.*/ -#define ASM_SHIFT_DOMAIN_ID 24 - -/* Payload of the #ASM_SVC_CMDRSP_GET_STREAM_HANDLES message, - * which returns a list of currently active stream handles. - * Immediately following this structure are num_handles of uint32 - * stream handles. - */ - - -struct asm_svc_cmdrsp_get_stream_handles { - u32 num_handles; - /* Number of active stream handles. */ -} __packed; - -#define ASM_CMD_SHARED_MEM_MAP_REGIONS 0x00010D92 -#define ASM_CMDRSP_SHARED_MEM_MAP_REGIONS 0x00010D93 -#define ASM_CMD_SHARED_MEM_UNMAP_REGIONS 0x00010D94 - -/* adsp_asm_service_commands.h */ - -#define ASM_MAX_SESSION_ID (8) - -/* Maximum number of sessions.*/ -#define ASM_MAX_NUM_SESSIONS ASM_MAX_SESSION_ID - -/* Maximum number of streams per session.*/ -#define ASM_MAX_STREAMS_PER_SESSION (8) -#define ASM_SESSION_CMD_RUN_V2 0x00010DAA -#define ASM_SESSION_CMD_RUN_STARTIME_RUN_IMMEDIATE 0 -#define ASM_SESSION_CMD_RUN_STARTIME_RUN_AT_ABSOLUTEIME 1 -#define ASM_SESSION_CMD_RUN_STARTIME_RUN_AT_RELATIVEIME 2 -#define ASM_SESSION_CMD_RUN_STARTIME_RUN_WITH_DELAY 3 - -#define ASM_BIT_MASK_RUN_STARTIME (0x00000003UL) - -/* Bit shift value used to specify the start time for the - * ASM_SESSION_CMD_RUN_V2 command. - */ -#define ASM_SHIFT_RUN_STARTIME 0 -struct asm_session_cmd_run_v2 { - struct apr_hdr hdr; - u32 flags; -/* Specifies whether to run immediately or at a specific - * rendering time or with a specified delay. Run with delay is - * useful for delaying in case of ASM loopback opened through - * ASM_STREAM_CMD_OPEN_LOOPBACK_V2. Use #ASM_BIT_MASK_RUN_STARTIME - * and #ASM_SHIFT_RUN_STARTIME to set this 2-bit flag. - * - * - *Bits 0 and 1 can take one of four possible values: - * - *- #ASM_SESSION_CMD_RUN_STARTIME_RUN_IMMEDIATE - *- #ASM_SESSION_CMD_RUN_STARTIME_RUN_AT_ABSOLUTEIME - *- #ASM_SESSION_CMD_RUN_STARTIME_RUN_AT_RELATIVEIME - *- #ASM_SESSION_CMD_RUN_STARTIME_RUN_WITH_DELAY - * - *All other bits are reserved; clients must set them to zero. - */ - - u32 time_lsw; -/* Lower 32 bits of the time in microseconds used to align the - * session origin time. When bits 0-1 of flags is - * ASM_SESSION_CMD_RUN_START_RUN_WITH_DELAY, time lsw is the lsw of - * the delay in us. For ASM_SESSION_CMD_RUN_START_RUN_WITH_DELAY, - * maximum value of the 64 bit delay is 150 ms. - */ - - u32 time_msw; -/* Upper 32 bits of the time in microseconds used to align the - * session origin time. When bits 0-1 of flags is - * ASM_SESSION_CMD_RUN_START_RUN_WITH_DELAY, time msw is the msw of - * the delay in us. For ASM_SESSION_CMD_RUN_START_RUN_WITH_DELAY, - * maximum value of the 64 bit delay is 150 ms. - */ - -} __packed; - -#define ASM_SESSION_CMD_PAUSE 0x00010BD3 -#define ASM_SESSION_CMD_SUSPEND 0x00010DEC -#define ASM_SESSION_CMD_GET_SESSIONTIME_V3 0x00010D9D -#define ASM_SESSION_CMD_REGISTER_FOR_RX_UNDERFLOW_EVENTS 0x00010BD5 - -struct asm_session_cmd_rgstr_rx_underflow { - struct apr_hdr hdr; - u16 enable_flag; -/* Specifies whether a client is to receive events when an Rx - * session underflows. - * Supported values: - * - 0 -- Do not send underflow events - * - 1 -- Send underflow events - */ - u16 reserved; - /* Reserved. This field must be set to zero.*/ -} __packed; - -#define ASM_SESSION_CMD_REGISTER_FORX_OVERFLOW_EVENTS 0x00010BD6 - -struct asm_session_cmd_regx_overflow { - struct apr_hdr hdr; - u16 enable_flag; -/* Specifies whether a client is to receive events when a Tx -* session overflows. - * Supported values: - * - 0 -- Do not send overflow events - * - 1 -- Send overflow events - */ - - u16 reserved; - /* Reserved. This field must be set to zero.*/ -} __packed; - -#define ASM_SESSION_EVENT_RX_UNDERFLOW 0x00010C17 -#define ASM_SESSION_EVENTX_OVERFLOW 0x00010C18 -#define ASM_SESSION_CMDRSP_GET_SESSIONTIME_V3 0x00010D9E - -struct asm_session_cmdrsp_get_sessiontime_v3 { - u32 status; - /* Status message (error code). - * Supported values: Refer to @xhyperref{Q3,[Q3]} - */ - - u32 sessiontime_lsw; - /* Lower 32 bits of the current session time in microseconds.*/ - - u32 sessiontime_msw; - /* Upper 32 bits of the current session time in microseconds.*/ - - u32 absolutetime_lsw; -/* Lower 32 bits in micro seconds of the absolute time at which - * the * sample corresponding to the above session time gets - * rendered * to hardware. This absolute time may be slightly in the - * future or past. - */ - - - u32 absolutetime_msw; -/* Upper 32 bits in micro seconds of the absolute time at which - * the * sample corresponding to the above session time gets - * rendered to * hardware. This absolute time may be slightly in the - * future or past. - */ - -} __packed; - -#define ASM_SESSION_CMD_ADJUST_SESSION_CLOCK_V2 0x00010D9F - -struct asm_session_cmd_adjust_session_clock_v2 { - struct apr_hdr hdr; -u32 adjustime_lsw; -/* Lower 32 bits of the signed 64-bit quantity that specifies the - * adjustment time in microseconds to the session clock. - * - * Positive values indicate advancement of the session clock. - * Negative values indicate delay of the session clock. - */ - - - u32 adjustime_msw; -/* Upper 32 bits of the signed 64-bit quantity that specifies - * the adjustment time in microseconds to the session clock. - * Positive values indicate advancement of the session clock. - * Negative values indicate delay of the session clock. - */ - -} __packed; - -#define ASM_SESSION_CMDRSP_ADJUST_SESSION_CLOCK_V2 0x00010DA0 - -struct asm_session_cmdrsp_adjust_session_clock_v2 { - u32 status; -/* Status message (error code). - * Supported values: Refer to @xhyperref{Q3,[Q3]} - * An error means the session clock is not adjusted. In this case, - * the next two fields are irrelevant. - */ - - - u32 actual_adjustime_lsw; -/* Lower 32 bits of the signed 64-bit quantity that specifies - * the actual adjustment in microseconds performed by the aDSP. - * A positive value indicates advancement of the session clock. A - * negative value indicates delay of the session clock. - */ - - - u32 actual_adjustime_msw; -/* Upper 32 bits of the signed 64-bit quantity that specifies - * the actual adjustment in microseconds performed by the aDSP. - * A positive value indicates advancement of the session clock. A - * negative value indicates delay of the session clock. - */ - - - u32 cmd_latency_lsw; -/* Lower 32 bits of the unsigned 64-bit quantity that specifies - * the amount of time in microseconds taken to perform the session - * clock adjustment. - */ - - - u32 cmd_latency_msw; -/* Upper 32 bits of the unsigned 64-bit quantity that specifies - * the amount of time in microseconds taken to perform the session - * clock adjustment. - */ - -} __packed; - -#define ASM_SESSION_CMD_GET_PATH_DELAY_V2 0x00010DAF -#define ASM_SESSION_CMDRSP_GET_PATH_DELAY_V2 0x00010DB0 - -struct asm_session_cmdrsp_get_path_delay_v2 { - u32 status; -/* Status message (error code). Whether this get delay operation - * is successful or not. Delay value is valid only if status is - * success. - * Supported values: Refer to @xhyperref{Q5,[Q5]} - */ - - u32 audio_delay_lsw; - /* Upper 32 bits of the aDSP delay in microseconds. */ - - u32 audio_delay_msw; - /* Lower 32 bits of the aDSP delay in microseconds. */ - -} __packed; - -/* adsp_asm_session_command.h*/ -#define ASM_STREAM_CMD_OPEN_WRITE_V2 0x00010D8F -#define ASM_STREAM_CMD_OPEN_WRITE_V3 0x00010DB3 - -#define ASM_LOW_LATENCY_STREAM_SESSION 0x10000000 - -#define ASM_ULTRA_LOW_LATENCY_STREAM_SESSION 0x20000000 - -#define ASM_LEGACY_STREAM_SESSION 0 - - -struct asm_stream_cmd_open_write_v3 { - struct apr_hdr hdr; - uint32_t mode_flags; -/* Mode flags that configure the stream to notify the client - * whenever it detects an SR/CM change at the input to its POPP. - * Supported values for bits 0 to 1: - * - Reserved; clients must set them to zero. - * Supported values for bit 2: - * - 0 -- SR/CM change notification event is disabled. - * - 1 -- SR/CM change notification event is enabled. - * - Use #ASM_BIT_MASK_SR_CM_CHANGE_NOTIFY_FLAG and - * #ASM_SHIFT_SR_CM_CHANGE_NOTIFY_FLAG to set or get this bit. - * - * Supported values for bit 31: - * - 0 -- Stream to be opened in on-Gapless mode. - * - 1 -- Stream to be opened in Gapless mode. In Gapless mode, - * successive streams must be opened with same session ID but - * different stream IDs. - * - * - Use #ASM_BIT_MASK_GAPLESS_MODE_FLAG and - * #ASM_SHIFT_GAPLESS_MODE_FLAG to set or get this bit. - * - * - * @note1hang MIDI and DTMF streams cannot be opened in Gapless mode. - */ - - uint16_t sink_endpointype; -/*< Sink point type. - * Supported values: - * - 0 -- Device matrix - * - Other values are reserved. - * - * The device matrix is the gateway to the hardware ports. - */ - - uint16_t bits_per_sample; -/*< Number of bits per sample processed by ASM modules. - * Supported values: 16 and 24 bits per sample - */ - - uint32_t postprocopo_id; -/*< Specifies the topology (order of processing) of - * postprocessing algorithms. None means no postprocessing. - * Supported values: - * - #ASM_STREAM_POSTPROCOPO_ID_DEFAULT - * - #ASM_STREAM_POSTPROCOPO_ID_MCH_PEAK_VOL - * - #ASM_STREAM_POSTPROCOPO_ID_NONE - * - * This field can also be enabled through SetParams flags. - */ - - uint32_t dec_fmt_id; -/*< Configuration ID of the decoder media format. - * - * Supported values: - * - #ASM_MEDIA_FMT_MULTI_CHANNEL_PCM_V2 - * - #ASM_MEDIA_FMT_ADPCM - * - #ASM_MEDIA_FMT_MP3 - * - #ASM_MEDIA_FMT_AAC_V2 - * - #ASM_MEDIA_FMT_DOLBY_AAC - * - #ASM_MEDIA_FMT_AMRNB_FS - * - #ASM_MEDIA_FMT_AMRWB_FS - * - #ASM_MEDIA_FMT_AMR_WB_PLUS_V2 - * - #ASM_MEDIA_FMT_V13K_FS - * - #ASM_MEDIA_FMT_EVRC_FS - * - #ASM_MEDIA_FMT_EVRCB_FS - * - #ASM_MEDIA_FMT_EVRCWB_FS - * - #ASM_MEDIA_FMT_SBC - * - #ASM_MEDIA_FMT_WMA_V10PRO_V2 - * - #ASM_MEDIA_FMT_WMA_V9_V2 - * - #ASM_MEDIA_FMT_AC3_DEC - * - #ASM_MEDIA_FMT_EAC3_DEC - * - #ASM_MEDIA_FMT_G711_ALAW_FS - * - #ASM_MEDIA_FMT_G711_MLAW_FS - * - #ASM_MEDIA_FMT_G729A_FS - * - #ASM_MEDIA_FMT_FR_FS - * - #ASM_MEDIA_FMT_VORBIS - * - #ASM_MEDIA_FMT_FLAC - * - #ASM_MEDIA_FMT_EXAMPLE - */ -} __packed; - -#define ASM_STREAM_CMD_OPEN_READ_V2 0x00010D8C - -#define ASM_STREAM_CMD_OPEN_READ_V3 0x00010DB4 - -/* Definition of the timestamp type flag bitmask */ -#define ASM_BIT_MASKIMESTAMPYPE_FLAG (0x00000020UL) - -/* Definition of the timestamp type flag shift value. */ -#define ASM_SHIFTIMESTAMPYPE_FLAG 5 - -/* Relative timestamp is identified by this value.*/ -#define ASM_RELATIVEIMESTAMP 0 - -/* Absolute timestamp is identified by this value.*/ -#define ASM_ABSOLUTEIMESTAMP 1 - -/* Bit value for Low Latency Tx stream subfield */ -#define ASM_LOW_LATENCY_TX_STREAM_SESSION 1 - -/* Bit shift for the stream_perf_mode subfield. */ -#define ASM_SHIFT_STREAM_PERF_MODE_FLAG_IN_OPEN_READ 29 - -struct asm_stream_cmd_open_read_v3 { - struct apr_hdr hdr; - u32 mode_flags; -/* Mode flags that indicate whether meta information per encoded - * frame is to be provided. - * Supported values for bit 4: - * - * - 0 -- Return data buffer contains all encoded frames only; it - * does not contain frame metadata. - * - * - 1 -- Return data buffer contains an array of metadata and - * encoded frames. - * - * - Use #ASM_BIT_MASK_META_INFO_FLAG as the bitmask and - * #ASM_SHIFT_META_INFO_FLAG as the shift value for this bit. - * - * - * Supported values for bit 5: - * - * - ASM_RELATIVEIMESTAMP -- ASM_DATA_EVENT_READ_DONE_V2 will have - * - relative time-stamp. - * - ASM_ABSOLUTEIMESTAMP -- ASM_DATA_EVENT_READ_DONE_V2 will - * - have absolute time-stamp. - * - * - Use #ASM_BIT_MASKIMESTAMPYPE_FLAG as the bitmask and - * #ASM_SHIFTIMESTAMPYPE_FLAG as the shift value for this bit. - * - * All other bits are reserved; clients must set them to zero. - */ - - u32 src_endpointype; -/* Specifies the endpoint providing the input samples. - * Supported values: - * - 0 -- Device matrix - * - All other values are reserved; clients must set them to zero. - * Otherwise, an error is returned. - * The device matrix is the gateway from the tunneled Tx ports. - */ - - u32 preprocopo_id; -/* Specifies the topology (order of processing) of preprocessing - * algorithms. None means no preprocessing. - * Supported values: - * - #ASM_STREAM_PREPROCOPO_ID_DEFAULT - * - #ASM_STREAM_PREPROCOPO_ID_NONE - * - * This field can also be enabled through SetParams flags. - */ - - u32 enc_cfg_id; -/* Media configuration ID for encoded output. - * Supported values: - * - #ASM_MEDIA_FMT_MULTI_CHANNEL_PCM_V2 - * - #ASM_MEDIA_FMT_AAC_V2 - * - #ASM_MEDIA_FMT_AMRNB_FS - * - #ASM_MEDIA_FMT_AMRWB_FS - * - #ASM_MEDIA_FMT_V13K_FS - * - #ASM_MEDIA_FMT_EVRC_FS - * - #ASM_MEDIA_FMT_EVRCB_FS - * - #ASM_MEDIA_FMT_EVRCWB_FS - * - #ASM_MEDIA_FMT_SBC - * - #ASM_MEDIA_FMT_G711_ALAW_FS - * - #ASM_MEDIA_FMT_G711_MLAW_FS - * - #ASM_MEDIA_FMT_G729A_FS - * - #ASM_MEDIA_FMT_EXAMPLE - * - #ASM_MEDIA_FMT_WMA_V8 - */ - - u16 bits_per_sample; -/* Number of bits per sample processed by ASM modules. - * Supported values: 16 and 24 bits per sample - */ - - u16 reserved; -/* Reserved for future use. This field must be set to zero.*/ -} __packed; - -#define ASM_POPP_OUTPUT_SR_NATIVE_RATE 0 - -/* Enumeration for the maximum sampling rate at the POPP output.*/ -#define ASM_POPP_OUTPUT_SR_MAX_RATE 48000 - -#define ASM_STREAM_CMD_OPEN_READWRITE_V2 0x00010D8D -#define ASM_STREAM_CMD_OPEN_READWRITE_V2 0x00010D8D -#define ASM_STREAM_CMD_OPEN_READ_V2 0x00010D8C - -struct asm_stream_cmd_open_readwrite_v2 { - struct apr_hdr hdr; - u32 mode_flags; -/* Mode flags. - * Supported values for bit 2: - * - 0 -- SR/CM change notification event is disabled. - * - 1 -- SR/CM change notification event is enabled. Use - * #ASM_BIT_MASK_SR_CM_CHANGE_NOTIFY_FLAG and - * #ASM_SHIFT_SR_CM_CHANGE_NOTIFY_FLAG to set or - * getting this flag. - * - * Supported values for bit 4: - * - 0 -- Return read data buffer contains all encoded frames only; it - * does not contain frame metadata. - * - 1 -- Return read data buffer contains an array of metadata and - * encoded frames. - * - * All other bits are reserved; clients must set them to zero. - */ - - u32 postprocopo_id; -/* Specifies the topology (order of processing) of postprocessing - * algorithms. None means no postprocessing. - * - * Supported values: - * - #ASM_STREAM_POSTPROCOPO_ID_DEFAULT - * - #ASM_STREAM_POSTPROCOPO_ID_MCH_PEAK_VOL - * - #ASM_STREAM_POSTPROCOPO_ID_NONE - */ - - u32 dec_fmt_id; -/* Specifies the media type of the input data. PCM indicates that - * no decoding must be performed, e.g., this is an NT encoder - * session. - * Supported values: - * - #ASM_MEDIA_FMT_MULTI_CHANNEL_PCM_V2 - * - #ASM_MEDIA_FMT_ADPCM - * - #ASM_MEDIA_FMT_MP3 - * - #ASM_MEDIA_FMT_AAC_V2 - * - #ASM_MEDIA_FMT_DOLBY_AAC - * - #ASM_MEDIA_FMT_AMRNB_FS - * - #ASM_MEDIA_FMT_AMRWB_FS - * - #ASM_MEDIA_FMT_V13K_FS - * - #ASM_MEDIA_FMT_EVRC_FS - * - #ASM_MEDIA_FMT_EVRCB_FS - * - #ASM_MEDIA_FMT_EVRCWB_FS - * - #ASM_MEDIA_FMT_SBC - * - #ASM_MEDIA_FMT_WMA_V10PRO_V2 - * - #ASM_MEDIA_FMT_WMA_V9_V2 - * - #ASM_MEDIA_FMT_AMR_WB_PLUS_V2 - * - #ASM_MEDIA_FMT_AC3_DEC - * - #ASM_MEDIA_FMT_G711_ALAW_FS - * - #ASM_MEDIA_FMT_G711_MLAW_FS - * - #ASM_MEDIA_FMT_G729A_FS - * - #ASM_MEDIA_FMT_EXAMPLE - */ - - u32 enc_cfg_id; -/* Specifies the media type for the output of the stream. PCM - * indicates that no encoding must be performed, e.g., this is an NT - * decoder session. - * Supported values: - * - #ASM_MEDIA_FMT_MULTI_CHANNEL_PCM_V2 - * - #ASM_MEDIA_FMT_AAC_V2 - * - #ASM_MEDIA_FMT_AMRNB_FS - * - #ASM_MEDIA_FMT_AMRWB_FS - * - #ASM_MEDIA_FMT_V13K_FS - * - #ASM_MEDIA_FMT_EVRC_FS - * - #ASM_MEDIA_FMT_EVRCB_FS - * - #ASM_MEDIA_FMT_EVRCWB_FS - * - #ASM_MEDIA_FMT_SBC - * - #ASM_MEDIA_FMT_G711_ALAW_FS - * - #ASM_MEDIA_FMT_G711_MLAW_FS - * - #ASM_MEDIA_FMT_G729A_FS - * - #ASM_MEDIA_FMT_EXAMPLE - * - #ASM_MEDIA_FMT_WMA_V8 - */ - - u16 bits_per_sample; -/* Number of bits per sample processed by ASM modules. - * Supported values: 16 and 24 bits per sample - */ - - u16 reserved; -/* Reserved for future use. This field must be set to zero.*/ - -} __packed; - -#define ASM_STREAM_CMD_OPEN_LOOPBACK_V2 0x00010D8E -struct asm_stream_cmd_open_loopback_v2 { - struct apr_hdr hdr; - u32 mode_flags; -/* Mode flags. - * Bit 0-31: reserved; client should set these bits to 0 - */ - u16 src_endpointype; - /* Endpoint type. 0 = Tx Matrix */ - u16 sink_endpointype; - /* Endpoint type. 0 = Rx Matrix */ - u32 postprocopo_id; -/* Postprocessor topology ID. Specifies the topology of - * postprocessing algorithms. - */ - - u16 bits_per_sample; -/* The number of bits per sample processed by ASM modules - * Supported values: 16 and 24 bits per sample - */ - u16 reserved; -/* Reserved for future use. This field must be set to zero. */ -} __packed; - -#define ASM_STREAM_CMD_CLOSE 0x00010BCD -#define ASM_STREAM_CMD_FLUSH 0x00010BCE - - -#define ASM_STREAM_CMD_FLUSH_READBUFS 0x00010C09 -#define ASM_STREAM_CMD_SET_PP_PARAMS_V2 0x00010DA1 - -struct asm_stream_cmd_set_pp_params_v2 { - u32 data_payload_addr_lsw; -/* LSW of parameter data payload address. Supported values: any. */ - u32 data_payload_addr_msw; -/* MSW of Parameter data payload address. Supported values: any. - * - Must be set to zero for in-band data. - * - In the case of 32 bit Shared memory address, msw field must be - * - set to zero. - * - In the case of 36 bit shared memory address, bit 31 to bit 4 of - * msw - * - * - must be set to zero. - */ - u32 mem_map_handle; -/* Supported Values: Any. -* memory map handle returned by DSP through -* ASM_CMD_SHARED_MEM_MAP_REGIONS -* command. -* if mmhandle is NULL, the ParamData payloads are within the -* message payload (in-band). -* If mmhandle is non-NULL, the ParamData payloads begin at the -* address specified in the address msw and lsw (out-of-band). -*/ - - u32 data_payload_size; -/* Size in bytes of the variable payload accompanying the -message, or in shared memory. This field is used for parsing the -parameter payload. */ - -} __packed; - - -struct asm_stream_param_data_v2 { - u32 module_id; - /* Unique module ID. */ - - u32 param_id; - /* Unique parameter ID. */ - - u16 param_size; -/* Data size of the param_id/module_id combination. This is - * a multiple of 4 bytes. - */ - - u16 reserved; -/* Reserved for future enhancements. This field must be set to - * zero. - */ - -} __packed; - -#define ASM_STREAM_CMD_GET_PP_PARAMS_V2 0x00010DA2 - -struct asm_stream_cmd_get_pp_params_v2 { - u32 data_payload_addr_lsw; - /* LSW of the parameter data payload address. */ - u32 data_payload_addr_msw; -/* MSW of the parameter data payload address. - * - Size of the shared memory, if specified, shall be large enough - * to contain the whole ParamData payload, including Module ID, - * Param ID, Param Size, and Param Values - * - Must be set to zero for in-band data - * - In the case of 32 bit Shared memory address, msw field must be - * set to zero. - * - In the case of 36 bit shared memory address, bit 31 to bit 4 of - * msw must be set to zero. - */ - - u32 mem_map_handle; -/* Supported Values: Any. -* memory map handle returned by DSP through ASM_CMD_SHARED_MEM_MAP_REGIONS -* command. -* if mmhandle is NULL, the ParamData payloads in the ACK are within the -* message payload (in-band). -* If mmhandle is non-NULL, the ParamData payloads in the ACK begin at the -* address specified in the address msw and lsw. -* (out-of-band). -*/ - - u32 module_id; - /* Unique module ID. */ - - u32 param_id; - /* Unique parameter ID. */ - - u16 param_max_size; -/* Maximum data size of the module_id/param_id combination. This - * is a multiple of 4 bytes. - */ - - - u16 reserved; -/* Reserved for backward compatibility. Clients must set this -* field to zero. -*/ - -} __packed; - -#define ASM_STREAM_CMD_SET_ENCDEC_PARAM 0x00010C10 - -#define ASM_PARAM_ID_ENCDEC_BITRATE 0x00010C13 - -struct asm_bitrate_param { - u32 bitrate; -/* Maximum supported bitrate. Only the AAC encoder is supported.*/ - -} __packed; - -#define ASM_PARAM_ID_ENCDEC_ENC_CFG_BLK_V2 0x00010DA3 -#define ASM_PARAM_ID_AAC_SBR_PS_FLAG 0x00010C63 - -/* Flag to turn off both SBR and PS processing, if they are - * present in the bitstream. - */ - -#define ASM_AAC_SBR_OFF_PS_OFF (2) - -/* Flag to turn on SBR but turn off PS processing,if they are - * present in the bitstream. - */ - -#define ASM_AAC_SBR_ON_PS_OFF (1) - -/* Flag to turn on both SBR and PS processing, if they are - * present in the bitstream (default behavior). - */ - - -#define ASM_AAC_SBR_ON_PS_ON (0) - -/* Structure for an AAC SBR PS processing flag. */ - -/* Payload of the #ASM_PARAM_ID_AAC_SBR_PS_FLAG parameter in the - * #ASM_STREAM_CMD_SET_ENCDEC_PARAM command. - */ -struct asm_aac_sbr_ps_flag_param { - struct apr_hdr hdr; - struct asm_stream_cmd_set_encdec_param encdec; - struct asm_enc_cfg_blk_param_v2 encblk; - - u32 sbr_ps_flag; -/* Control parameter to enable or disable SBR/PS processing in - * the AAC bitstream. Use the following macros to set this field: - * - #ASM_AAC_SBR_OFF_PS_OFF -- Turn off both SBR and PS - * processing, if they are present in the bitstream. - * - #ASM_AAC_SBR_ON_PS_OFF -- Turn on SBR processing, but not PS - * processing, if they are present in the bitstream. - * - #ASM_AAC_SBR_ON_PS_ON -- Turn on both SBR and PS processing, - * if they are present in the bitstream (default behavior). - * - All other values are invalid. - * Changes are applied to the next decoded frame. - */ -} __packed; - -#define ASM_PARAM_ID_AAC_DUAL_MONO_MAPPING 0x00010C64 - -/* First single channel element in a dual mono bitstream.*/ -#define ASM_AAC_DUAL_MONO_MAP_SCE_1 (1) - -/* Second single channel element in a dual mono bitstream.*/ -#define ASM_AAC_DUAL_MONO_MAP_SCE_2 (2) - -/* Structure for AAC decoder dual mono channel mapping. */ - - -struct asm_aac_dual_mono_mapping_param { - struct apr_hdr hdr; - struct asm_stream_cmd_set_encdec_param encdec; - u16 left_channel_sce; - u16 right_channel_sce; - -} __packed; - -#define ASM_STREAM_CMDRSP_GET_PP_PARAMS_V2 0x00010DA4 - -struct asm_stream_cmdrsp_get_pp_params_v2 { - u32 status; -} __packed; - -#define ASM_PARAM_ID_AC3_KARAOKE_MODE 0x00010D73 - -/* Enumeration for both vocals in a karaoke stream.*/ -#define AC3_KARAOKE_MODE_NO_VOCAL (0) - -/* Enumeration for only the left vocal in a karaoke stream.*/ -#define AC3_KARAOKE_MODE_LEFT_VOCAL (1) - -/* Enumeration for only the right vocal in a karaoke stream.*/ -#define AC3_KARAOKE_MODE_RIGHT_VOCAL (2) - -/* Enumeration for both vocal channels in a karaoke stream.*/ -#define AC3_KARAOKE_MODE_BOTH_VOCAL (3) -#define ASM_PARAM_ID_AC3_DRC_MODE 0x00010D74 -/* Enumeration for the Custom Analog mode.*/ -#define AC3_DRC_MODE_CUSTOM_ANALOG (0) - -/* Enumeration for the Custom Digital mode.*/ -#define AC3_DRC_MODE_CUSTOM_DIGITAL (1) -/* Enumeration for the Line Out mode (light compression).*/ -#define AC3_DRC_MODE_LINE_OUT (2) - -/* Enumeration for the RF remodulation mode (heavy compression).*/ -#define AC3_DRC_MODE_RF_REMOD (3) -#define ASM_PARAM_ID_AC3_DUAL_MONO_MODE 0x00010D75 - -/* Enumeration for playing dual mono in stereo mode.*/ -#define AC3_DUAL_MONO_MODE_STEREO (0) - -/* Enumeration for playing left mono.*/ -#define AC3_DUAL_MONO_MODE_LEFT_MONO (1) - -/* Enumeration for playing right mono.*/ -#define AC3_DUAL_MONO_MODE_RIGHT_MONO (2) - -/* Enumeration for mixing both dual mono channels and playing them.*/ -#define AC3_DUAL_MONO_MODE_MIXED_MONO (3) -#define ASM_PARAM_ID_AC3_STEREO_DOWNMIX_MODE 0x00010D76 - -/* Enumeration for using the Downmix mode indicated in the bitstream. */ - -#define AC3_STEREO_DOWNMIX_MODE_AUTO_DETECT (0) - -/* Enumeration for Surround Compatible mode (preserves the - * surround information). - */ - -#define AC3_STEREO_DOWNMIX_MODE_LT_RT (1) -/* Enumeration for Mono Compatible mode (if the output is to be - * further downmixed to mono). - */ - -#define AC3_STEREO_DOWNMIX_MODE_LO_RO (2) - -/* ID of the AC3 PCM scale factor parameter in the - * #ASM_STREAM_CMD_SET_ENCDEC_PARAM command. - */ -#define ASM_PARAM_ID_AC3_PCM_SCALEFACTOR 0x00010D78 - -/* ID of the AC3 DRC boost scale factor parameter in the - * #ASM_STREAM_CMD_SET_ENCDEC_PARAM command. - */ -#define ASM_PARAM_ID_AC3_DRC_BOOST_SCALEFACTOR 0x00010D79 - -/* ID of the AC3 DRC cut scale factor parameter in the - * #ASM_STREAM_CMD_SET_ENCDEC_PARAM command. - */ -#define ASM_PARAM_ID_AC3_DRC_CUT_SCALEFACTOR 0x00010D7A - -/* Structure for AC3 Generic Parameter. */ - -/* Payload of the AC3 parameters in the - * #ASM_STREAM_CMD_SET_ENCDEC_PARAM command. - */ -struct asm_ac3_generic_param { - struct apr_hdr hdr; - struct asm_stream_cmd_set_encdec_param encdec; - struct asm_enc_cfg_blk_param_v2 encblk; - u32 generic_parameter; -/* AC3 generic parameter. Select from one of the following - * possible values. - * - * For #ASM_PARAM_ID_AC3_KARAOKE_MODE, supported values are: - * - AC3_KARAOKE_MODE_NO_VOCAL - * - AC3_KARAOKE_MODE_LEFT_VOCAL - * - AC3_KARAOKE_MODE_RIGHT_VOCAL - * - AC3_KARAOKE_MODE_BOTH_VOCAL - * - * For #ASM_PARAM_ID_AC3_DRC_MODE, supported values are: - * - AC3_DRC_MODE_CUSTOM_ANALOG - * - AC3_DRC_MODE_CUSTOM_DIGITAL - * - AC3_DRC_MODE_LINE_OUT - * - AC3_DRC_MODE_RF_REMOD - * - * For #ASM_PARAM_ID_AC3_DUAL_MONO_MODE, supported values are: - * - AC3_DUAL_MONO_MODE_STEREO - * - AC3_DUAL_MONO_MODE_LEFT_MONO - * - AC3_DUAL_MONO_MODE_RIGHT_MONO - * - AC3_DUAL_MONO_MODE_MIXED_MONO - * - * For #ASM_PARAM_ID_AC3_STEREO_DOWNMIX_MODE, supported values are: - * - AC3_STEREO_DOWNMIX_MODE_AUTO_DETECT - * - AC3_STEREO_DOWNMIX_MODE_LT_RT - * - AC3_STEREO_DOWNMIX_MODE_LO_RO - * - * For #ASM_PARAM_ID_AC3_PCM_SCALEFACTOR, supported values are - * 0 to 1 in Q31 format. - * - * For #ASM_PARAM_ID_AC3_DRC_BOOST_SCALEFACTOR, supported values are - * 0 to 1 in Q31 format. - * - * For #ASM_PARAM_ID_AC3_DRC_CUT_SCALEFACTOR, supported values are - * 0 to 1 in Q31 format. - */ -} __packed; - -/* Enumeration for Raw mode (no downmixing), which specifies - * that all channels in the bitstream are to be played out as is - * without any downmixing. (Default) - */ - -#define WMAPRO_CHANNEL_MASK_RAW (-1) - -/* Enumeration for setting the channel mask to 0. The 7.1 mode - * (Home Theater) is assigned. - */ - - -#define WMAPRO_CHANNEL_MASK_ZERO 0x0000 - -/* Speaker layout mask for one channel (Home Theater, mono). - * - Speaker front center - */ -#define WMAPRO_CHANNEL_MASK_1_C 0x0004 - -/* Speaker layout mask for two channels (Home Theater, stereo). - * - Speaker front left - * - Speaker front right - */ -#define WMAPRO_CHANNEL_MASK_2_L_R 0x0003 - -/* Speaker layout mask for three channels (Home Theater). - * - Speaker front left - * - Speaker front right - * - Speaker front center - */ -#define WMAPRO_CHANNEL_MASK_3_L_C_R 0x0007 - -/* Speaker layout mask for two channels (stereo). - * - Speaker back left - * - Speaker back right - */ -#define WMAPRO_CHANNEL_MASK_2_Bl_Br 0x0030 - -/* Speaker layout mask for four channels. - * - Speaker front left - * - Speaker front right - * - Speaker back left - * - Speaker back right -*/ -#define WMAPRO_CHANNEL_MASK_4_L_R_Bl_Br 0x0033 - -/* Speaker layout mask for four channels (Home Theater). - * - Speaker front left - * - Speaker front right - * - Speaker front center - * - Speaker back center -*/ -#define WMAPRO_CHANNEL_MASK_4_L_R_C_Bc_HT 0x0107 -/* Speaker layout mask for five channels. - * - Speaker front left - * - Speaker front right - * - Speaker front center - * - Speaker back left - * - Speaker back right - */ -#define WMAPRO_CHANNEL_MASK_5_L_C_R_Bl_Br 0x0037 - -/* Speaker layout mask for five channels (5 mode, Home Theater). - * - Speaker front left - * - Speaker front right - * - Speaker front center - * - Speaker side left - * - Speaker side right - */ -#define WMAPRO_CHANNEL_MASK_5_L_C_R_Sl_Sr_HT 0x0607 -/* Speaker layout mask for six channels (5.1 mode). - * - Speaker front left - * - Speaker front right - * - Speaker front center - * - Speaker low frequency - * - Speaker back left - * - Speaker back right - */ -#define WMAPRO_CHANNEL_MASK_5DOT1_L_C_R_Bl_Br_SLF 0x003F -/* Speaker layout mask for six channels (5.1 mode, Home Theater). - * - Speaker front left - * - Speaker front right - * - Speaker front center - * - Speaker low frequency - * - Speaker side left - * - Speaker side right - */ -#define WMAPRO_CHANNEL_MASK_5DOT1_L_C_R_Sl_Sr_SLF_HT 0x060F -/* Speaker layout mask for six channels (5.1 mode, no LFE). - * - Speaker front left - * - Speaker front right - * - Speaker front center - * - Speaker back left - * - Speaker back right - * - Speaker back center - */ -#define WMAPRO_CHANNEL_MASK_5DOT1_L_C_R_Bl_Br_Bc 0x0137 -/* Speaker layout mask for six channels (5.1 mode, Home Theater, - * no LFE). - * - Speaker front left - * - Speaker front right - * - Speaker front center - * - Speaker back center - * - Speaker side left - * - Speaker side right - */ -#define WMAPRO_CHANNEL_MASK_5DOT1_L_C_R_Sl_Sr_Bc_HT 0x0707 - -/* Speaker layout mask for seven channels (6.1 mode). - * - Speaker front left - * - Speaker front right - * - Speaker front center - * - Speaker low frequency - * - Speaker back left - * - Speaker back right - * - Speaker back center - */ -#define WMAPRO_CHANNEL_MASK_6DOT1_L_C_R_Bl_Br_Bc_SLF 0x013F - -/* Speaker layout mask for seven channels (6.1 mode, Home - * Theater). - * - Speaker front left - * - Speaker front right - * - Speaker front center - * - Speaker low frequency - * - Speaker back center - * - Speaker side left - * - Speaker side right -*/ -#define WMAPRO_CHANNEL_MASK_6DOT1_L_C_R_Sl_Sr_Bc_SLF_HT 0x070F - -/* Speaker layout mask for seven channels (6.1 mode, no LFE). - * - Speaker front left - * - Speaker front right - * - Speaker front center - * - Speaker back left - * - Speaker back right - * - Speaker front left of center - * - Speaker front right of center -*/ -#define WMAPRO_CHANNEL_MASK_6DOT1_L_C_R_Bl_Br_SFLOC_SFROC 0x00F7 - -/* Speaker layout mask for seven channels (6.1 mode, Home - * Theater, no LFE). - * - Speaker front left - * - Speaker front right - * - Speaker front center - * - Speaker side left - * - Speaker side right - * - Speaker front left of center - * - Speaker front right of center -*/ -#define WMAPRO_CHANNEL_MASK_6DOT1_L_C_R_Sl_Sr_SFLOC_SFROC_HT 0x0637 - -/* Speaker layout mask for eight channels (7.1 mode). - * - Speaker front left - * - Speaker front right - * - Speaker front center - * - Speaker back left - * - Speaker back right - * - Speaker low frequency - * - Speaker front left of center - * - Speaker front right of center - */ -#define WMAPRO_CHANNEL_MASK_7DOT1_L_C_R_Bl_Br_SLF_SFLOC_SFROC \ - 0x00FF - -/* Speaker layout mask for eight channels (7.1 mode, Home Theater). - * - Speaker front left - * - Speaker front right - * - Speaker front center - * - Speaker side left - * - Speaker side right - * - Speaker low frequency - * - Speaker front left of center - * - Speaker front right of center - * -*/ -#define WMAPRO_CHANNEL_MASK_7DOT1_L_C_R_Sl_Sr_SLF_SFLOC_SFROC_HT \ - 0x063F - -#define ASM_PARAM_ID_DEC_OUTPUT_CHAN_MAP 0x00010D82 - -/* Maximum number of decoder output channels.*/ -#define MAX_CHAN_MAP_CHANNELS 16 - -/* Structure for decoder output channel mapping. */ - -/* Payload of the #ASM_PARAM_ID_DEC_OUTPUT_CHAN_MAP parameter in the - * #ASM_STREAM_CMD_SET_ENCDEC_PARAM command. - */ -struct asm_dec_out_chan_map_param { - struct apr_hdr hdr; - struct asm_stream_cmd_set_encdec_param encdec; - u32 num_channels; -/* Number of decoder output channels. - * Supported values: 0 to #MAX_CHAN_MAP_CHANNELS - * - * A value of 0 indicates native channel mapping, which is valid - * only for NT mode. This means the output of the decoder is to be - * preserved as is. - */ - u8 channel_mapping[MAX_CHAN_MAP_CHANNELS]; -} __packed; - -#define ASM_STREAM_CMD_OPEN_WRITE_COMPRESSED 0x00010D84 - -/* Bitmask for the IEC 61937 enable flag.*/ -#define ASM_BIT_MASK_IEC_61937_STREAM_FLAG (0x00000001UL) - -/* Shift value for the IEC 61937 enable flag.*/ -#define ASM_SHIFT_IEC_61937_STREAM_FLAG 0 - -/* Bitmask for the IEC 60958 enable flag.*/ -#define ASM_BIT_MASK_IEC_60958_STREAM_FLAG (0x00000002UL) - -/* Shift value for the IEC 60958 enable flag.*/ -#define ASM_SHIFT_IEC_60958_STREAM_FLAG 1 - -/* Payload format for open write compressed comand */ - -/* Payload format for the #ASM_STREAM_CMD_OPEN_WRITE_COMPRESSED - * comand, which opens a stream for a given session ID and stream ID - * to be rendered in the compressed format. - */ - -struct asm_stream_cmd_open_write_compressed { - struct apr_hdr hdr; - u32 flags; -/* Mode flags that configure the stream for a specific format. - * Supported values: - * - Bit 0 -- IEC 61937 compatibility - * - 0 -- Stream is not in IEC 61937 format - * - 1 -- Stream is in IEC 61937 format - * - Bit 1 -- IEC 60958 compatibility - * - 0 -- Stream is not in IEC 60958 format - * - 1 -- Stream is in IEC 60958 format - * - Bits 2 to 31 -- 0 (Reserved) - * - * For the same stream, bit 0 cannot be set to 0 and bit 1 cannot - * be set to 1. A compressed stream connot have IEC 60958 - * packetization applied without IEC 61937 packetization. - * @note1hang Currently, IEC 60958 packetized input streams are not - * supported. - */ - - - u32 fmt_id; -/* Specifies the media type of the HDMI stream to be opened. - * Supported values: - * - #ASM_MEDIA_FMT_AC3_DEC - * - #ASM_MEDIA_FMT_EAC3_DEC - * - #ASM_MEDIA_FMT_DTS - * - #ASM_MEDIA_FMT_ATRAC - * - #ASM_MEDIA_FMT_MAT - * - * @note1hang This field must be set to a valid media type even if - * IEC 61937 packetization is not performed by the aDSP. - */ - -} __packed; - - -/* - Indicates the number of samples per channel to be removed from the - beginning of the stream. -*/ -#define ASM_DATA_CMD_REMOVE_INITIAL_SILENCE 0x00010D67 -/* - Indicates the number of samples per channel to be removed from - the end of the stream. -*/ -#define ASM_DATA_CMD_REMOVE_TRAILING_SILENCE 0x00010D68 -struct asm_data_cmd_remove_silence { - struct apr_hdr hdr; - u32 num_samples_to_remove; - /**< Number of samples per channel to be removed. - - @values 0 to (2@sscr{32}-1) */ -} __packed; - -#define ASM_STREAM_CMD_OPEN_READ_COMPRESSED 0x00010D95 - -struct asm_stream_cmd_open_read_compressed { - struct apr_hdr hdr; - u32 mode_flags; -/* Mode flags that indicate whether meta information per encoded - * frame is to be provided. - * Supported values for bit 4: - * - 0 -- Return data buffer contains all encoded frames only; it does - * not contain frame metadata. - * - 1 -- Return data buffer contains an array of metadata and encoded - * frames. - * - Use #ASM_BIT_MASK_META_INFO_FLAG to set the bitmask and - * #ASM_SHIFT_META_INFO_FLAG to set the shift value for this bit. - * All other bits are reserved; clients must set them to zero. - */ - - u32 frames_per_buf; -/* Indicates the number of frames that need to be returned per - * read buffer - * Supported values: should be greater than 0 - */ - -} __packed; - -/* adsp_asm_stream_commands.h*/ - - -/* adsp_asm_api.h (no changes)*/ -#define ASM_STREAM_POSTPROCOPO_ID_DEFAULT \ - 0x00010BE4 -#define ASM_STREAM_POSTPROCOPO_ID_PEAKMETER \ - 0x00010D83 -#define ASM_STREAM_POSTPROCOPO_ID_NONE \ - 0x00010C68 -#define ASM_STREAM_POSTPROCOPO_ID_MCH_PEAK_VOL \ - 0x00010D8B -#define ASM_STREAM_PREPROCOPO_ID_DEFAULT \ - ASM_STREAM_POSTPROCOPO_ID_DEFAULT -#define ASM_STREAM_PREPROCOPO_ID_NONE \ - ASM_STREAM_POSTPROCOPO_ID_NONE -#define ADM_CMD_COPP_OPENOPOLOGY_ID_NONE_AUDIO_COPP \ - 0x00010312 -#define ADM_CMD_COPP_OPENOPOLOGY_ID_SPEAKER_MONO_AUDIO_COPP \ - 0x00010313 -#define ADM_CMD_COPP_OPENOPOLOGY_ID_SPEAKER_STEREO_AUDIO_COPP \ - 0x00010314 -#define ADM_CMD_COPP_OPENOPOLOGY_ID_SPEAKER_STEREO_IIR_AUDIO_COPP\ - 0x00010704 -#define ADM_CMD_COPP_OPENOPOLOGY_ID_SPEAKER_MONO_AUDIO_COPP_MBDRCV2\ - 0x0001070D -#define ADM_CMD_COPP_OPENOPOLOGY_ID_SPEAKER_STEREO_AUDIO_COPP_MBDRCV2\ - 0x0001070E -#define ADM_CMD_COPP_OPENOPOLOGY_ID_SPEAKER_STEREO_IIR_AUDIO_COPP_MBDRCV2\ - 0x0001070F -#define ADM_CMD_COPP_OPENOPOLOGY_ID_SPEAKER_MCH_PEAK_VOL \ - 0x0001031B -#define ADM_CMD_COPP_OPENOPOLOGY_ID_MIC_MONO_AUDIO_COPP 0x00010315 -#define ADM_CMD_COPP_OPENOPOLOGY_ID_MIC_STEREO_AUDIO_COPP 0x00010316 -#define AUDPROC_COPPOPOLOGY_ID_MCHAN_IIR_AUDIO 0x00010715 -#define ADM_CMD_COPP_OPENOPOLOGY_ID_DEFAULT_AUDIO_COPP 0x00010BE3 -#define ADM_CMD_COPP_OPENOPOLOGY_ID_PEAKMETER_AUDIO_COPP 0x00010317 -#define AUDPROC_MODULE_ID_AIG 0x00010716 -#define AUDPROC_PARAM_ID_AIG_ENABLE 0x00010717 -#define AUDPROC_PARAM_ID_AIG_CONFIG 0x00010718 - -struct Audio_AigParam { - uint16_t mode; -/*< Mode word for enabling AIG/SIG mode . - * Byte offset: 0 - */ - int16_t staticGainL16Q12; -/*< Static input gain when aigMode is set to 1. - * Byte offset: 2 - */ - int16_t initialGainDBL16Q7; -/*module id - * data variable payload containing the pre/postprocessing module id - * values. For an in-band scenario, the variable payload depends on the size - * of the parameter. - */ -struct adm_cmd_rsp_get_pp_topo_module_list_t { - /* Status message (error code). */ - uint32_t status; -} __packed; - -struct audproc_topology_module_id_info_t { - uint32_t num_modules; -} __packed; - -/* end_addtogroup audio_pp_module_ids */ - -/* @ingroup audio_pp_module_ids - * ID of the Volume Control module pre/postprocessing block. - * This module supports the following parameter IDs: - * - #ASM_PARAM_ID_VOL_CTRL_MASTER_GAIN - * - #ASM_PARAM_ID_VOL_CTRL_LR_CHANNEL_GAIN - * - #ASM_PARAM_ID_VOL_CTRL_MUTE_CONFIG - * - #ASM_PARAM_ID_SOFT_VOL_STEPPING_PARAMETERS - * - #ASM_PARAM_ID_SOFT_PAUSE_PARAMETERS - * - #ASM_PARAM_ID_MULTICHANNEL_GAIN - * - #ASM_PARAM_ID_MULTICHANNEL_MUTE - */ -#define ASM_MODULE_ID_VOL_CTRL 0x00010BFE -#define ASM_MODULE_ID_VOL_CTRL2 0x00010910 -#define AUDPROC_MODULE_ID_VOL_CTRL ASM_MODULE_ID_VOL_CTRL - -/* @addtogroup audio_pp_param_ids */ -/* ID of the master gain parameter used by the #ASM_MODULE_ID_VOL_CTRL - * module. - * @messagepayload - * @structure{asm_volume_ctrl_master_gain} - * @tablespace - * @inputtable{Audio_Postproc_ASM_PARAM_ID_VOL_CTRL_MASTER_GAIN.tex} - */ -#define ASM_PARAM_ID_VOL_CTRL_MASTER_GAIN 0x00010BFF -#define AUDPROC_PARAM_ID_VOL_CTRL_MASTER_GAIN ASM_PARAM_ID_VOL_CTRL_MASTER_GAIN - -/* ID of the left/right channel gain parameter used by the - * #ASM_MODULE_ID_VOL_CTRL module. - * @messagepayload - * @structure{asm_volume_ctrl_lr_chan_gain} - * @tablespace - * @inputtable{Audio_Postproc_ASM_PARAM_ID_VOL_CTRL_LR_CHANNEL_GAIN.tex} - */ -#define ASM_PARAM_ID_VOL_CTRL_LR_CHANNEL_GAIN 0x00010C00 - -/* ID of the mute configuration parameter used by the - * #ASM_MODULE_ID_VOL_CTRL module. - * @messagepayload - * @structure{asm_volume_ctrl_mute_config} - * @tablespace - * @inputtable{Audio_Postproc_ASM_PARAM_ID_VOL_CTRL_MUTE_CONFIG.tex} - */ -#define ASM_PARAM_ID_VOL_CTRL_MUTE_CONFIG 0x00010C01 - -/* ID of the soft stepping volume parameters used by the - * #ASM_MODULE_ID_VOL_CTRL module. - * @messagepayload - * @structure{asm_soft_step_volume_params} - * @tablespace - * @inputtable{Audio_Postproc_ASM_PARAM_ID_SOFT_VOL_STEPPING_PARAMET - * ERS.tex} - */ -#define ASM_PARAM_ID_SOFT_VOL_STEPPING_PARAMETERS 0x00010C29 -#define AUDPROC_PARAM_ID_SOFT_VOL_STEPPING_PARAMETERS\ - ASM_PARAM_ID_SOFT_VOL_STEPPING_PARAMETERS - -/* ID of the soft pause parameters used by the #ASM_MODULE_ID_VOL_CTRL - * module. - */ -#define ASM_PARAM_ID_SOFT_PAUSE_PARAMETERS 0x00010D6A - -/* ID of the multiple-channel volume control parameters used by the - * #ASM_MODULE_ID_VOL_CTRL module. - */ -#define ASM_PARAM_ID_MULTICHANNEL_GAIN 0x00010713 - -/* ID of the multiple-channel mute configuration parameters used by the - * #ASM_MODULE_ID_VOL_CTRL module. - */ - -#define ASM_PARAM_ID_MULTICHANNEL_MUTE 0x00010714 - -/* Structure for the master gain parameter for a volume control - * module. - */ - - -/* @brief Payload of the #ASM_PARAM_ID_VOL_CTRL_MASTER_GAIN - * parameter used by the Volume Control module. - */ - - - -struct asm_volume_ctrl_master_gain { - struct apr_hdr hdr; - struct asm_stream_cmd_set_pp_params_v2 param; - struct asm_stream_param_data_v2 data; - uint16_t master_gain; - /*< Linear gain in Q13 format. */ - - uint16_t reserved; - /*< Clients must set this field to zero. - */ -} __packed; - - -/* Structure for the left/right channel gain parameter for a - * volume control module. - */ - - -/* @brief Payload of the #ASM_PARAM_ID_VOL_CTRL_LR_CHANNEL_GAIN - * parameters used by the Volume Control module. - */ - - - -struct asm_volume_ctrl_lr_chan_gain { - struct apr_hdr hdr; - struct asm_stream_cmd_set_pp_params_v2 param; - struct asm_stream_param_data_v2 data; - - uint16_t l_chan_gain; - /*< Linear gain in Q13 format for the left channel. */ - - uint16_t r_chan_gain; - /*< Linear gain in Q13 format for the right channel.*/ -} __packed; - - -/* Structure for the mute configuration parameter for a - volume control module. */ - - -/* @brief Payload of the #ASM_PARAM_ID_VOL_CTRL_MUTE_CONFIG - * parameter used by the Volume Control module. - */ - - -struct asm_volume_ctrl_mute_config { - struct apr_hdr hdr; - struct asm_stream_cmd_set_pp_params_v2 param; - struct asm_stream_param_data_v2 data; - uint32_t mute_flag; -/*< Specifies whether mute is disabled (0) or enabled (nonzero).*/ - -} __packed; - -/* - * Supported parameters for a soft stepping linear ramping curve. - */ -#define ASM_PARAM_SVC_RAMPINGCURVE_LINEAR 0 - -/* - * Exponential ramping curve. - */ -#define ASM_PARAM_SVC_RAMPINGCURVE_EXP 1 - -/* - * Logarithmic ramping curve. - */ -#define ASM_PARAM_SVC_RAMPINGCURVE_LOG 2 - -/* Structure for holding soft stepping volume parameters. */ - - -/* Payload of the #ASM_PARAM_ID_SOFT_VOL_STEPPING_PARAMETERS - * parameters used by the Volume Control module. - */ -struct asm_soft_step_volume_params { - struct apr_hdr hdr; - struct asm_stream_cmd_set_pp_params_v2 param; - struct asm_stream_param_data_v2 data; - uint32_t period; -/*< Period in milliseconds. - * Supported values: 0 to 15000 - */ - - uint32_t step; -/*< Step in microseconds. - * Supported values: 0 to 15000000 - */ - - uint32_t ramping_curve; -/*< Ramping curve type. - * Supported values: - * - #ASM_PARAM_SVC_RAMPINGCURVE_LINEAR - * - #ASM_PARAM_SVC_RAMPINGCURVE_EXP - * - #ASM_PARAM_SVC_RAMPINGCURVE_LOG - */ -} __packed; - - -/* Structure for holding soft pause parameters. */ - - -/* Payload of the #ASM_PARAM_ID_SOFT_PAUSE_PARAMETERS - * parameters used by the Volume Control module. - */ - - -struct asm_soft_pause_params { - struct apr_hdr hdr; - struct asm_stream_cmd_set_pp_params_v2 param; - struct asm_stream_param_data_v2 data; - uint32_t enable_flag; -/*< Specifies whether soft pause is disabled (0) or enabled - * (nonzero). - */ - - - - uint32_t period; -/*< Period in milliseconds. - * Supported values: 0 to 15000 - */ - - uint32_t step; -/*< Step in microseconds. - * Supported values: 0 to 15000000 - */ - - uint32_t ramping_curve; -/*< Ramping curve. - * Supported values: - * - #ASM_PARAM_SVC_RAMPINGCURVE_LINEAR - * - #ASM_PARAM_SVC_RAMPINGCURVE_EXP - * - #ASM_PARAM_SVC_RAMPINGCURVE_LOG - */ -} __packed; - - -/* Maximum number of channels.*/ -#define VOLUME_CONTROL_MAX_CHANNELS 8 - -/* Structure for holding one channel type - gain pair. */ - - -/* Payload of the #ASM_PARAM_ID_MULTICHANNEL_GAIN channel - * type/gain pairs used by the Volume Control module. \n \n This - * structure immediately follows the - * asm_volume_ctrl_multichannel_gain structure. - */ - - -struct asm_volume_ctrl_channelype_gain_pair { - struct apr_hdr hdr; - struct asm_stream_cmd_set_pp_params_v2 param; - struct asm_stream_param_data_v2 data; - uint8_t channelype; -/*< Channel type for which the gain setting is to be applied. - * Supported values: - * - #PCM_CHANNEL_L - * - #PCM_CHANNEL_R - * - #PCM_CHANNEL_C - * - #PCM_CHANNEL_LS - * - #PCM_CHANNEL_RS - * - #PCM_CHANNEL_LFE - * - #PCM_CHANNEL_CS - * - #PCM_CHANNEL_LB - * - #PCM_CHANNEL_RB - * - #PCM_CHANNELS - * - #PCM_CHANNEL_CVH - * - #PCM_CHANNEL_MS - * - #PCM_CHANNEL_FLC - * - #PCM_CHANNEL_FRC - * - #PCM_CHANNEL_RLC - * - #PCM_CHANNEL_RRC - */ - - uint8_t reserved1; - /*< Clients must set this field to zero. */ - - uint8_t reserved2; - /*< Clients must set this field to zero. */ - - uint8_t reserved3; - /*< Clients must set this field to zero. */ - - uint32_t gain; -/*< Gain value for this channel in Q28 format. - * Supported values: Any - */ -} __packed; - - -/* Structure for the multichannel gain command */ - - -/* Payload of the #ASM_PARAM_ID_MULTICHANNEL_GAIN - * parameters used by the Volume Control module. - */ - - -struct asm_volume_ctrl_multichannel_gain { - struct apr_hdr hdr; - struct asm_stream_cmd_set_pp_params_v2 param; - struct asm_stream_param_data_v2 data; - uint32_t num_channels; -/*< Number of channels for which gain values are provided. Any - * channels present in the data for which gain is not provided are - * set to unity gain. - * Supported values: 1 to 8 - */ - - - struct asm_volume_ctrl_channelype_gain_pair - gain_data[VOLUME_CONTROL_MAX_CHANNELS]; - /*< Array of channel type/gain pairs.*/ -} __packed; - - -/* Structure for holding one channel type - mute pair. */ - - -/* Payload of the #ASM_PARAM_ID_MULTICHANNEL_MUTE channel - * type/mute setting pairs used by the Volume Control module. \n \n - * This structure immediately follows the - * asm_volume_ctrl_multichannel_mute structure. - */ - - -struct asm_volume_ctrl_channelype_mute_pair { - struct apr_hdr hdr; - struct asm_stream_cmd_set_pp_params_v2 param; - struct asm_stream_param_data_v2 data; - uint8_t channelype; -/*< Channel type for which the mute setting is to be applied. - * Supported values: - * - #PCM_CHANNEL_L - * - #PCM_CHANNEL_R - * - #PCM_CHANNEL_C - * - #PCM_CHANNEL_LS - * - #PCM_CHANNEL_RS - * - #PCM_CHANNEL_LFE - * - #PCM_CHANNEL_CS - * - #PCM_CHANNEL_LB - * - #PCM_CHANNEL_RB - * - #PCM_CHANNELS - * - #PCM_CHANNEL_CVH - * - #PCM_CHANNEL_MS - * - #PCM_CHANNEL_FLC - * - #PCM_CHANNEL_FRC - * - #PCM_CHANNEL_RLC - * - #PCM_CHANNEL_RRC - */ - - uint8_t reserved1; - /*< Clients must set this field to zero. */ - - uint8_t reserved2; - /*< Clients must set this field to zero. */ - - uint8_t reserved3; - /*< Clients must set this field to zero. */ - - uint32_t mute; -/*< Mute setting for this channel. - * Supported values: - * - 0 = Unmute - * - Nonzero = Mute - */ -} __packed; - - -/* Structure for the multichannel mute command */ - - -/* @brief Payload of the #ASM_PARAM_ID_MULTICHANNEL_MUTE - * parameters used by the Volume Control module. - */ - - -struct asm_volume_ctrl_multichannel_mute { - struct apr_hdr hdr; - struct asm_stream_cmd_set_pp_params_v2 param; - struct asm_stream_param_data_v2 data; - uint32_t num_channels; -/*< Number of channels for which mute configuration is - * provided. Any channels present in the data for which mute - * configuration is not provided are set to unmute. - * Supported values: 1 to 8 - */ - -struct asm_volume_ctrl_channelype_mute_pair - mute_data[VOLUME_CONTROL_MAX_CHANNELS]; - /*< Array of channel type/mute setting pairs.*/ -} __packed; -/* end_addtogroup audio_pp_param_ids */ - -/* audio_pp_module_ids - * ID of the IIR Tuning Filter module. - * This module supports the following parameter IDs: - * - #ASM_PARAM_ID_IIRUNING_FILTER_ENABLE_CONFIG - * - #ASM_PARAM_ID_IIRUNING_FILTER_PRE_GAIN - * - #ASM_PARAM_ID_IIRUNING_FILTER_CONFIG_PARAMS - */ -#define ASM_MODULE_ID_IIRUNING_FILTER 0x00010C02 - -/* @addtogroup audio_pp_param_ids */ -/* ID of the IIR tuning filter enable parameter used by the - * #ASM_MODULE_ID_IIRUNING_FILTER module. - * @messagepayload - * @structure{asm_iiruning_filter_enable} - * @tablespace - * @inputtable{Audio_Postproc_ASM_PARAM_ID_IIRUNING_FILTER_ENABLE_CO - * NFIG.tex} - */ -#define ASM_PARAM_ID_IIRUNING_FILTER_ENABLE_CONFIG 0x00010C03 - -/* ID of the IIR tuning filter pregain parameter used by the - * #ASM_MODULE_ID_IIRUNING_FILTER module. - */ -#define ASM_PARAM_ID_IIRUNING_FILTER_PRE_GAIN 0x00010C04 - -/* ID of the IIR tuning filter configuration parameters used by the - * #ASM_MODULE_ID_IIRUNING_FILTER module. - */ -#define ASM_PARAM_ID_IIRUNING_FILTER_CONFIG_PARAMS 0x00010C05 - -/* Structure for an enable configuration parameter for an - * IIR tuning filter module. - */ - - -/* @brief Payload of the #ASM_PARAM_ID_IIRUNING_FILTER_ENABLE_CONFIG - * parameter used by the IIR Tuning Filter module. - */ -struct asm_iiruning_filter_enable { - uint32_t enable_flag; -/*< Specifies whether the IIR tuning filter is disabled (0) or - * enabled (1). - */ -} __packed; - -/* Structure for the pregain parameter for an IIR tuning filter module. */ - - -/* Payload of the #ASM_PARAM_ID_IIRUNING_FILTER_PRE_GAIN - * parameters used by the IIR Tuning Filter module. - */ -struct asm_iiruning_filter_pregain { - uint16_t pregain; - /*< Linear gain in Q13 format. */ - - uint16_t reserved; - /*< Clients must set this field to zero.*/ -} __packed; - -/* Structure for the configuration parameter for an IIR tuning filter - * module. - */ - - -/* @brief Payload of the #ASM_PARAM_ID_IIRUNING_FILTER_CONFIG_PARAMS - * parameters used by the IIR Tuning Filter module. \n - * \n - * This structure is followed by the IIR filter coefficients: \n - * - Sequence of int32_t FilterCoeffs \n - * Five coefficients for each band. Each coefficient is in int32_t format, in - * the order of b0, b1, b2, a1, a2. - * - Sequence of int16_t NumShiftFactor \n - * One int16_t per band. The numerator shift factor is related to the Q - * factor of the filter coefficients. - * - Sequence of uint16_t PanSetting \n - * One uint16_t per band, indicating if the filter is applied to left (0), - * right (1), or both (2) channels. - */ -struct asm_iir_filter_config_params { - uint16_t num_biquad_stages; -/*< Number of bands. - * Supported values: 0 to 20 - */ - - uint16_t reserved; - /*< Clients must set this field to zero.*/ -} __packed; - -/* audio_pp_module_ids - * ID of the Multiband Dynamic Range Control (MBDRC) module on the Tx/Rx - * paths. - * This module supports the following parameter IDs: - * - #ASM_PARAM_ID_MBDRC_ENABLE - * - #ASM_PARAM_ID_MBDRC_CONFIG_PARAMS - */ -#define ASM_MODULE_ID_MBDRC 0x00010C06 - -/* audio_pp_param_ids */ -/* ID of the MBDRC enable parameter used by the #ASM_MODULE_ID_MBDRC module. - * @messagepayload - * @structure{asm_mbdrc_enable} - * @tablespace - * @inputtable{Audio_Postproc_ASM_PARAM_ID_MBDRC_ENABLE.tex} - */ -#define ASM_PARAM_ID_MBDRC_ENABLE 0x00010C07 - -/* ID of the MBDRC configuration parameters used by the - * #ASM_MODULE_ID_MBDRC module. - * @messagepayload - * @structure{asm_mbdrc_config_params} - * @tablespace - * @inputtable{Audio_Postproc_ASM_PARAM_ID_MBDRC_CONFIG_PARAMS.tex} - * - * @parspace Sub-band DRC configuration parameters - * @structure{asm_subband_drc_config_params} - * @tablespace - * @inputtable{Audio_Postproc_ASM_PARAM_ID_MBDRC_CONFIG_PARAMS_subband_DRC.tex} - * - * @keep{6} - * To obtain legacy ADRC from MBDRC, use the calibration tool to: - * - * - Enable MBDRC (EnableFlag = TRUE) - * - Set number of bands to 1 (uiNumBands = 1) - * - Enable the first MBDRC band (DrcMode[0] = DRC_ENABLED = 1) - * - Clear the first band mute flag (MuteFlag[0] = 0) - * - Set the first band makeup gain to unity (compMakeUpGain[0] = 0x2000) - * - Use the legacy ADRC parameters to calibrate the rest of the MBDRC - * parameters. - */ -#define ASM_PARAM_ID_MBDRC_CONFIG_PARAMS 0x00010C08 - -/* end_addtogroup audio_pp_param_ids */ - -/* audio_pp_module_ids - * ID of the MMBDRC module version 2 pre/postprocessing block. - * This module differs from the original MBDRC (#ASM_MODULE_ID_MBDRC) in - * the length of the filters used in each sub-band. - * This module supports the following parameter ID: - * - #ASM_PARAM_ID_MBDRC_CONFIG_PARAMS_IMPROVED_FILTBANK_V2 - */ -#define ASM_MODULE_ID_MBDRCV2 0x0001070B - -/* @addtogroup audio_pp_param_ids */ -/* ID of the configuration parameters used by the - * #ASM_MODULE_ID_MBDRCV2 module for the improved filter structure - * of the MBDRC v2 pre/postprocessing block. - * The update to this configuration structure from the original - * MBDRC is the number of filter coefficients in the filter - * structure. The sequence for is as follows: - * - 1 band = 0 FIR coefficient + 1 mute flag + uint16_t padding - * - 2 bands = 141 FIR coefficients + 2 mute flags + uint16_t padding - * - 3 bands = 141+81 FIR coefficients + 3 mute flags + uint16_t padding - * - 4 bands = 141+81+61 FIR coefficients + 4 mute flags + uint16_t - * padding - * - 5 bands = 141+81+61+61 FIR coefficients + 5 mute flags + - * uint16_t padding - * This block uses the same parameter structure as - * #ASM_PARAM_ID_MBDRC_CONFIG_PARAMS. - */ -#define ASM_PARAM_ID_MBDRC_CONFIG_PARAMS_IMPROVED_FILTBANK_V2 \ - 0x0001070C - -/* Structure for the enable parameter for an MBDRC module. */ - - -/* Payload of the #ASM_PARAM_ID_MBDRC_ENABLE parameter used by the - * MBDRC module. - */ -struct asm_mbdrc_enable { - uint32_t enable_flag; -/*< Specifies whether MBDRC is disabled (0) or enabled (nonzero).*/ -} __packed; - -/* Structure for the configuration parameters for an MBDRC module. */ - - -/* Payload of the #ASM_PARAM_ID_MBDRC_CONFIG_PARAMS - * parameters used by the MBDRC module. \n \n Following this - * structure is the payload for sub-band DRC configuration - * parameters (asm_subband_drc_config_params). This sub-band - * structure must be repeated for each band. - */ - - -struct asm_mbdrc_config_params { - uint16_t num_bands; -/*< Number of bands. - * Supported values: 1 to 5 - */ - - int16_t limiterhreshold; -/*< Threshold in decibels for the limiter output. - * Supported values: -72 to 18 \n - * Recommended value: 3994 (-0.22 db in Q3.12 format) - */ - - int16_t limiter_makeup_gain; -/*< Makeup gain in decibels for the limiter output. - * Supported values: -42 to 42 \n - * Recommended value: 256 (0 dB in Q7.8 format) - */ - - int16_t limiter_gc; -/*< Limiter gain recovery coefficient. - * Supported values: 0.5 to 0.99 \n - * Recommended value: 32440 (0.99 in Q15 format) - */ - - int16_t limiter_delay; -/*< Limiter delay in samples. - * Supported values: 0 to 10 \n - * Recommended value: 262 (0.008 samples in Q15 format) - */ - - int16_t limiter_max_wait; -/*< Maximum limiter waiting time in samples. - * Supported values: 0 to 10 \n - * Recommended value: 262 (0.008 samples in Q15 format) - */ -} __packed; - -/* DRC configuration structure for each sub-band of an MBDRC module. */ - - -/* Payload of the #ASM_PARAM_ID_MBDRC_CONFIG_PARAMS DRC - * configuration parameters for each sub-band in the MBDRC module. - * After this DRC structure is configured for valid bands, the next - * MBDRC setparams expects the sequence of sub-band MBDRC filter - * coefficients (the length depends on the number of bands) plus the - * mute flag for that band plus uint16_t padding. - * - * @keep{10} - * The filter coefficient and mute flag are of type int16_t: - * - FIR coefficient = int16_t firFilter - * - Mute flag = int16_t fMuteFlag - * - * The sequence is as follows: - * - 1 band = 0 FIR coefficient + 1 mute flag + uint16_t padding - * - 2 bands = 97 FIR coefficients + 2 mute flags + uint16_t padding - * - 3 bands = 97+33 FIR coefficients + 3 mute flags + uint16_t padding - * - 4 bands = 97+33+33 FIR coefficients + 4 mute flags + uint16_t padding - * - 5 bands = 97+33+33+33 FIR coefficients + 5 mute flags + uint16_t padding - * - * For improved filterbank, the sequence is as follows: - * - 1 band = 0 FIR coefficient + 1 mute flag + uint16_t padding - * - 2 bands = 141 FIR coefficients + 2 mute flags + uint16_t padding - * - 3 bands = 141+81 FIR coefficients + 3 mute flags + uint16_t padding - * - 4 bands = 141+81+61 FIR coefficients + 4 mute flags + uint16_t padding - * - 5 bands = 141+81+61+61 FIR coefficients + 5 mute flags + uint16_t padding - */ -struct asm_subband_drc_config_params { - int16_t drc_stereo_linked_flag; -/*< Specifies whether all stereo channels have the same applied - * dynamics (1) or if they process their dynamics independently (0). - * Supported values: - * - 0 -- Not linked - * - 1 -- Linked - */ - - int16_t drc_mode; -/*< Specifies whether DRC mode is bypassed for sub-bands. - * Supported values: - * - 0 -- Disabled - * - 1 -- Enabled - */ - - int16_t drc_down_sample_level; -/*< DRC down sample level. - * Supported values: @ge 1 - */ - - int16_t drc_delay; -/*< DRC delay in samples. - * Supported values: 0 to 1200 - */ - - uint16_t drc_rmsime_avg_const; -/*< RMS signal energy time-averaging constant. - * Supported values: 0 to 2^16-1 - */ - - uint16_t drc_makeup_gain; -/*< DRC makeup gain in decibels. - * Supported values: 258 to 64917 - */ - /* Down expander settings */ - int16_t down_expdrhreshold; -/*< Down expander threshold. - * Supported Q7 format values: 1320 to up_cmpsrhreshold - */ - - int16_t down_expdr_slope; -/*< Down expander slope. - * Supported Q8 format values: -32768 to 0. - */ - - uint32_t down_expdr_attack; -/*< Down expander attack constant. - * Supported Q31 format values: 196844 to 2^31. - */ - - uint32_t down_expdr_release; -/*< Down expander release constant. - * Supported Q31 format values: 19685 to 2^31 - */ - - uint16_t down_expdr_hysteresis; -/*< Down expander hysteresis constant. - * Supported Q14 format values: 1 to 32690 - */ - - uint16_t reserved; - /*< Clients must set this field to zero. */ - - int32_t down_expdr_min_gain_db; -/*< Down expander minimum gain. - * Supported Q23 format values: -805306368 to 0. - */ - - /* Up compressor settings */ - - int16_t up_cmpsrhreshold; -/*< Up compressor threshold. - * Supported Q7 format values: down_expdrhreshold to - * down_cmpsrhreshold. - */ - - uint16_t up_cmpsr_slope; -/*< Up compressor slope. - * Supported Q16 format values: 0 to 64881. - */ - - uint32_t up_cmpsr_attack; -/*< Up compressor attack constant. - * Supported Q31 format values: 196844 to 2^31. - */ - - uint32_t up_cmpsr_release; -/*< Up compressor release constant. - * Supported Q31 format values: 19685 to 2^31. - */ - - uint16_t up_cmpsr_hysteresis; -/*< Up compressor hysteresis constant. - * Supported Q14 format values: 1 to 32690. - */ - - /* Down compressor settings */ - - int16_t down_cmpsrhreshold; -/*< Down compressor threshold. - * Supported Q7 format values: up_cmpsrhreshold to 11560. - */ - - uint16_t down_cmpsr_slope; -/*< Down compressor slope. - * Supported Q16 format values: 0 to 64881. - */ - - uint16_t reserved1; -/*< Clients must set this field to zero. */ - - uint32_t down_cmpsr_attack; -/*< Down compressor attack constant. - * Supported Q31 format values: 196844 to 2^31. - */ - - uint32_t down_cmpsr_release; -/*< Down compressor release constant. - * Supported Q31 format values: 19685 to 2^31. - */ - - uint16_t down_cmpsr_hysteresis; -/*< Down compressor hysteresis constant. - * Supported Q14 values: 1 to 32690. - */ - - uint16_t reserved2; -/*< Clients must set this field to zero.*/ -} __packed; - -#define ASM_MODULE_ID_EQUALIZER 0x00010C27 -#define ASM_PARAM_ID_EQUALIZER_PARAMETERS 0x00010C28 - -#define ASM_MAX_EQ_BANDS 12 - -struct asm_eq_per_band_params { - uint32_t band_idx; -/*< Band index. - * Supported values: 0 to 11 - */ - - uint32_t filterype; -/*< Type of filter. - * Supported values: - * - #ASM_PARAM_EQYPE_NONE - * - #ASM_PARAM_EQ_BASS_BOOST - * - #ASM_PARAM_EQ_BASS_CUT - * - #ASM_PARAM_EQREBLE_BOOST - * - #ASM_PARAM_EQREBLE_CUT - * - #ASM_PARAM_EQ_BAND_BOOST - * - #ASM_PARAM_EQ_BAND_CUT - */ - - uint32_t center_freq_hz; - /*< Filter band center frequency in Hertz. */ - - int32_t filter_gain; -/*< Filter band initial gain. - * Supported values: +12 to -12 dB in 1 dB increments - */ - - int32_t q_factor; -/*< Filter band quality factor expressed as a Q8 number, i.e., a - * fixed-point number with q factor of 8. For example, 3000/(2^8). - */ -} __packed; - -struct asm_eq_params { - struct apr_hdr hdr; - struct asm_stream_cmd_set_pp_params_v2 param; - struct asm_stream_param_data_v2 data; - uint32_t enable_flag; -/*< Specifies whether the equalizer module is disabled (0) or enabled - * (nonzero). - */ - - uint32_t num_bands; -/*< Number of bands. - * Supported values: 1 to 12 - */ - struct asm_eq_per_band_params eq_bands[ASM_MAX_EQ_BANDS]; - -} __packed; - -/* No equalizer effect.*/ -#define ASM_PARAM_EQYPE_NONE 0 - -/* Bass boost equalizer effect.*/ -#define ASM_PARAM_EQ_BASS_BOOST 1 - -/*Bass cut equalizer effect.*/ -#define ASM_PARAM_EQ_BASS_CUT 2 - -/* Treble boost equalizer effect */ -#define ASM_PARAM_EQREBLE_BOOST 3 - -/* Treble cut equalizer effect.*/ -#define ASM_PARAM_EQREBLE_CUT 4 - -/* Band boost equalizer effect.*/ -#define ASM_PARAM_EQ_BAND_BOOST 5 - -/* Band cut equalizer effect.*/ -#define ASM_PARAM_EQ_BAND_CUT 6 - -/* Voice get & set params */ -#define VOICE_CMD_SET_PARAM 0x0001133D -#define VOICE_CMD_GET_PARAM 0x0001133E -#define VOICE_EVT_GET_PARAM_ACK 0x00011008 - - -/** ID of the Bass Boost module. - This module supports the following parameter IDs: - - #AUDPROC_PARAM_ID_BASS_BOOST_ENABLE - - #AUDPROC_PARAM_ID_BASS_BOOST_MODE - - #AUDPROC_PARAM_ID_BASS_BOOST_STRENGTH -*/ -#define AUDPROC_MODULE_ID_BASS_BOOST 0x000108A1 -/** ID of the Bass Boost enable parameter used by - AUDPROC_MODULE_ID_BASS_BOOST. -*/ -#define AUDPROC_PARAM_ID_BASS_BOOST_ENABLE 0x000108A2 -/** ID of the Bass Boost mode parameter used by - AUDPROC_MODULE_ID_BASS_BOOST. -*/ -#define AUDPROC_PARAM_ID_BASS_BOOST_MODE 0x000108A3 -/** ID of the Bass Boost strength parameter used by - AUDPROC_MODULE_ID_BASS_BOOST. -*/ -#define AUDPROC_PARAM_ID_BASS_BOOST_STRENGTH 0x000108A4 - -/** ID of the Virtualizer module. This module supports the - following parameter IDs: - - #AUDPROC_PARAM_ID_VIRTUALIZER_ENABLE - - #AUDPROC_PARAM_ID_VIRTUALIZER_STRENGTH - - #AUDPROC_PARAM_ID_VIRTUALIZER_OUT_TYPE - - #AUDPROC_PARAM_ID_VIRTUALIZER_GAIN_ADJUST -*/ -#define AUDPROC_MODULE_ID_VIRTUALIZER 0x000108A5 -/** ID of the Virtualizer enable parameter used by - AUDPROC_MODULE_ID_VIRTUALIZER. -*/ -#define AUDPROC_PARAM_ID_VIRTUALIZER_ENABLE 0x000108A6 -/** ID of the Virtualizer strength parameter used by - AUDPROC_MODULE_ID_VIRTUALIZER. -*/ -#define AUDPROC_PARAM_ID_VIRTUALIZER_STRENGTH 0x000108A7 -/** ID of the Virtualizer out type parameter used by - AUDPROC_MODULE_ID_VIRTUALIZER. -*/ -#define AUDPROC_PARAM_ID_VIRTUALIZER_OUT_TYPE 0x000108A8 -/** ID of the Virtualizer out type parameter used by - AUDPROC_MODULE_ID_VIRTUALIZER. -*/ -#define AUDPROC_PARAM_ID_VIRTUALIZER_GAIN_ADJUST 0x000108A9 - -/** ID of the Reverb module. This module supports the following - parameter IDs: - - #AUDPROC_PARAM_ID_REVERB_ENABLE - - #AUDPROC_PARAM_ID_REVERB_MODE - - #AUDPROC_PARAM_ID_REVERB_PRESET - - #AUDPROC_PARAM_ID_REVERB_WET_MIX - - #AUDPROC_PARAM_ID_REVERB_GAIN_ADJUST - - #AUDPROC_PARAM_ID_REVERB_ROOM_LEVEL - - #AUDPROC_PARAM_ID_REVERB_ROOM_HF_LEVEL - - #AUDPROC_PARAM_ID_REVERB_DECAY_TIME - - #AUDPROC_PARAM_ID_REVERB_DECAY_HF_RATIO - - #AUDPROC_PARAM_ID_REVERB_REFLECTIONS_LEVEL - - #AUDPROC_PARAM_ID_REVERB_REFLECTIONS_DELAY - - #AUDPROC_PARAM_ID_REVERB_LEVEL - - #AUDPROC_PARAM_ID_REVERB_DELAY - - #AUDPROC_PARAM_ID_REVERB_DIFFUSION - - #AUDPROC_PARAM_ID_REVERB_DENSITY -*/ -#define AUDPROC_MODULE_ID_REVERB 0x000108AA -/** ID of the Reverb enable parameter used by - AUDPROC_MODULE_ID_REVERB. -*/ -#define AUDPROC_PARAM_ID_REVERB_ENABLE 0x000108AB -/** ID of the Reverb mode parameter used by - AUDPROC_MODULE_ID_REVERB. -*/ -#define AUDPROC_PARAM_ID_REVERB_MODE 0x000108AC -/** ID of the Reverb preset parameter used by - AUDPROC_MODULE_ID_REVERB. -*/ -#define AUDPROC_PARAM_ID_REVERB_PRESET 0x000108AD -/** ID of the Reverb wet mix parameter used by - AUDPROC_MODULE_ID_REVERB. -*/ -#define AUDPROC_PARAM_ID_REVERB_WET_MIX 0x000108AE -/** ID of the Reverb gain adjust parameter used by - AUDPROC_MODULE_ID_REVERB. -*/ -#define AUDPROC_PARAM_ID_REVERB_GAIN_ADJUST 0x000108AF -/** ID of the Reverb room level parameter used by - AUDPROC_MODULE_ID_REVERB. -*/ -#define AUDPROC_PARAM_ID_REVERB_ROOM_LEVEL 0x000108B0 -/** ID of the Reverb room hf level parameter used by - AUDPROC_MODULE_ID_REVERB. -*/ -#define AUDPROC_PARAM_ID_REVERB_ROOM_HF_LEVEL 0x000108B1 -/** ID of the Reverb decay time parameter used by - AUDPROC_MODULE_ID_REVERB. -*/ -#define AUDPROC_PARAM_ID_REVERB_DECAY_TIME 0x000108B2 -/** ID of the Reverb decay hf ratio parameter used by - AUDPROC_MODULE_ID_REVERB. -*/ -#define AUDPROC_PARAM_ID_REVERB_DECAY_HF_RATIO 0x000108B3 -/** ID of the Reverb reflections level parameter used by - AUDPROC_MODULE_ID_REVERB. -*/ -#define AUDPROC_PARAM_ID_REVERB_REFLECTIONS_LEVEL 0x000108B4 -/** ID of the Reverb reflections delay parameter used by - AUDPROC_MODULE_ID_REVERB. -*/ -#define AUDPROC_PARAM_ID_REVERB_REFLECTIONS_DELAY 0x000108B5 -/** ID of the Reverb level parameter used by - AUDPROC_MODULE_ID_REVERB. -*/ -#define AUDPROC_PARAM_ID_REVERB_LEVEL 0x000108B6 -/** ID of the Reverb delay parameter used by - AUDPROC_MODULE_ID_REVERB. -*/ -#define AUDPROC_PARAM_ID_REVERB_DELAY 0x000108B7 -/** ID of the Reverb diffusion parameter used by - AUDPROC_MODULE_ID_REVERB. -*/ -#define AUDPROC_PARAM_ID_REVERB_DIFFUSION 0x000108B8 -/** ID of the Reverb density parameter used by - AUDPROC_MODULE_ID_REVERB. -*/ -#define AUDPROC_PARAM_ID_REVERB_DENSITY 0x000108B9 - -/** ID of the Popless Equalizer module. This module supports the - following parameter IDs: - - #AUDPROC_PARAM_ID_EQ_ENABLE - - #AUDPROC_PARAM_ID_EQ_CONFIG - - #AUDPROC_PARAM_ID_EQ_NUM_BANDS - - #AUDPROC_PARAM_ID_EQ_BAND_LEVELS - - #AUDPROC_PARAM_ID_EQ_BAND_LEVEL_RANGE - - #AUDPROC_PARAM_ID_EQ_BAND_FREQS - - #AUDPROC_PARAM_ID_EQ_SINGLE_BAND_FREQ_RANGE - - #AUDPROC_PARAM_ID_EQ_SINGLE_BAND_FREQ - - #AUDPROC_PARAM_ID_EQ_BAND_INDEX - - #AUDPROC_PARAM_ID_EQ_PRESET_ID - - #AUDPROC_PARAM_ID_EQ_NUM_PRESETS - - #AUDPROC_PARAM_ID_EQ_GET_PRESET_NAME -*/ -#define AUDPROC_MODULE_ID_POPLESS_EQUALIZER 0x000108BA -/** ID of the Popless Equalizer enable parameter used by - AUDPROC_MODULE_ID_POPLESS_EQUALIZER. -*/ -#define AUDPROC_PARAM_ID_EQ_ENABLE 0x000108BB -/** ID of the Popless Equalizer config parameter used by - AUDPROC_MODULE_ID_POPLESS_EQUALIZER. -*/ -#define AUDPROC_PARAM_ID_EQ_CONFIG 0x000108BC -/** ID of the Popless Equalizer number of bands parameter used - by AUDPROC_MODULE_ID_POPLESS_EQUALIZER. This param ID is - used for get param only. -*/ -#define AUDPROC_PARAM_ID_EQ_NUM_BANDS 0x000108BD -/** ID of the Popless Equalizer band levels parameter used by - AUDPROC_MODULE_ID_POPLESS_EQUALIZER. This param ID is - used for get param only. -*/ -#define AUDPROC_PARAM_ID_EQ_BAND_LEVELS 0x000108BE -/** ID of the Popless Equalizer band level range parameter used - by AUDPROC_MODULE_ID_POPLESS_EQUALIZER. This param ID is - used for get param only. -*/ -#define AUDPROC_PARAM_ID_EQ_BAND_LEVEL_RANGE 0x000108BF -/** ID of the Popless Equalizer band frequencies parameter used - by AUDPROC_MODULE_ID_POPLESS_EQUALIZER. This param ID is - used for get param only. -*/ -#define AUDPROC_PARAM_ID_EQ_BAND_FREQS 0x000108C0 -/** ID of the Popless Equalizer single band frequency range - parameter used by AUDPROC_MODULE_ID_POPLESS_EQUALIZER. - This param ID is used for get param only. -*/ -#define AUDPROC_PARAM_ID_EQ_SINGLE_BAND_FREQ_RANGE 0x000108C1 -/** ID of the Popless Equalizer single band frequency parameter - used by AUDPROC_MODULE_ID_POPLESS_EQUALIZER. This param ID - is used for set param only. -*/ -#define AUDPROC_PARAM_ID_EQ_SINGLE_BAND_FREQ 0x000108C2 -/** ID of the Popless Equalizer band index parameter used by - AUDPROC_MODULE_ID_POPLESS_EQUALIZER. -*/ -#define AUDPROC_PARAM_ID_EQ_BAND_INDEX 0x000108C3 -/** ID of the Popless Equalizer preset id parameter used by - AUDPROC_MODULE_ID_POPLESS_EQUALIZER. This param ID is used - for get param only. -*/ -#define AUDPROC_PARAM_ID_EQ_PRESET_ID 0x000108C4 -/** ID of the Popless Equalizer number of presets parameter used - by AUDPROC_MODULE_ID_POPLESS_EQUALIZER. This param ID is used - for get param only. -*/ -#define AUDPROC_PARAM_ID_EQ_NUM_PRESETS 0x000108C5 -/** ID of the Popless Equalizer preset name parameter used by - AUDPROC_MODULE_ID_POPLESS_EQUALIZER. This param ID is used - for get param only. -*/ -#define AUDPROC_PARAM_ID_EQ_PRESET_NAME 0x000108C6 - -/* Set Q6 topologies */ -#define ASM_CMD_ADD_TOPOLOGIES 0x00010DBE -#define ADM_CMD_ADD_TOPOLOGIES 0x00010335 -#define AFE_CMD_ADD_TOPOLOGIES 0x000100f8 -/* structure used for both ioctls */ -struct cmd_set_topologies { - struct apr_hdr hdr; - u32 payload_addr_lsw; - /* LSW of parameter data payload address.*/ - u32 payload_addr_msw; - /* MSW of parameter data payload address.*/ - u32 mem_map_handle; - /* Memory map handle returned by mem map command */ - u32 payload_size; - /* Size in bytes of the variable payload in shared memory */ -} __packed; - -/* This module represents the Rx processing of Feedback speaker protection. - * It contains the excursion control, thermal protection, - * analog clip manager features in it. - * This module id will support following param ids. - * - AFE_PARAM_ID_FBSP_MODE_RX_CFG - */ - -#define AFE_MODULE_FB_SPKR_PROT_RX 0x0001021C -#define AFE_MODULE_FB_SPKR_PROT_V2_RX 0x0001025F - -#define AFE_PARAM_ID_FBSP_MODE_RX_CFG 0x0001021D -#define AFE_PARAM_ID_FBSP_PTONE_RAMP_CFG 0x00010260 - -struct asm_fbsp_mode_rx_cfg { - uint32_t minor_version; - uint32_t mode; -} __packed; - -/* This module represents the VI processing of feedback speaker protection. - * It will receive Vsens and Isens from codec and generates necessary - * parameters needed by Rx processing. - * This module id will support following param ids. - * - AFE_PARAM_ID_SPKR_CALIB_VI_PROC_CFG - * - AFE_PARAM_ID_CALIB_RES_CFG - * - AFE_PARAM_ID_FEEDBACK_PATH_CFG - */ - -#define AFE_MODULE_FB_SPKR_PROT_VI_PROC 0x00010226 -#define AFE_MODULE_FB_SPKR_PROT_VI_PROC_V2 0x0001026A - -#define AFE_PARAM_ID_SPKR_CALIB_VI_PROC_CFG 0x0001022A -#define AFE_PARAM_ID_SPKR_CALIB_VI_PROC_CFG_V2 0x0001026B - -struct asm_spkr_calib_vi_proc_cfg { - uint32_t minor_version; - uint32_t operation_mode; - uint32_t r0_t0_selection_flag[SP_V2_NUM_MAX_SPKR]; - int32_t r0_cali_q24[SP_V2_NUM_MAX_SPKR]; - int16_t t0_cali_q6[SP_V2_NUM_MAX_SPKR]; - uint32_t quick_calib_flag; -} __packed; - -#define AFE_PARAM_ID_CALIB_RES_CFG 0x0001022B -#define AFE_PARAM_ID_CALIB_RES_CFG_V2 0x0001026E - -struct asm_calib_res_cfg { - uint32_t minor_version; - int32_t r0_cali_q24[SP_V2_NUM_MAX_SPKR]; - uint32_t th_vi_ca_state; -} __packed; - -#define AFE_PARAM_ID_FEEDBACK_PATH_CFG 0x0001022C -#define AFE_MODULE_FEEDBACK 0x00010257 - -struct asm_feedback_path_cfg { - uint32_t minor_version; - int32_t dst_portid; - int32_t num_channels; - int32_t chan_info[4]; -} __packed; - -#define AFE_PARAM_ID_MODE_VI_PROC_CFG 0x00010227 - -struct asm_mode_vi_proc_cfg { - uint32_t minor_version; - uint32_t cal_mode; -} __packed; - -union afe_spkr_prot_config { - struct asm_fbsp_mode_rx_cfg mode_rx_cfg; - struct asm_spkr_calib_vi_proc_cfg vi_proc_cfg; - struct asm_feedback_path_cfg feedback_path_cfg; - struct asm_mode_vi_proc_cfg mode_vi_proc_cfg; -} __packed; - -struct afe_spkr_prot_config_command { - struct apr_hdr hdr; - struct afe_port_cmd_set_param_v2 param; - struct afe_port_param_data_v2 pdata; - union afe_spkr_prot_config prot_config; -} __packed; - -struct afe_spkr_prot_get_vi_calib { - struct apr_hdr hdr; - struct afe_port_cmd_get_param_v2 get_param; - struct afe_port_param_data_v2 pdata; - struct asm_calib_res_cfg res_cfg; -} __packed; - -struct afe_spkr_prot_calib_get_resp { - uint32_t status; - struct afe_port_param_data_v2 pdata; - struct asm_calib_res_cfg res_cfg; -} __packed; - - -#define AFE_MODULE_DSM_RX 0x10001062 -#define AFE_MODULE_DSM_TX 0x10001063 - -#define AFE_PARAM_ID_ENABLE_DSM_TX 0x10001064 -#define AFE_PARAM_ID_ENABLE_DSM_RX 0x10001065 -#define AFE_PARAM_ID_DSM_RX_CFG 0x10001066 -#define AFE_PARAM_ID_DSM_TX_CFG 0x10001067 - -struct afe_dsm_set_command { - struct apr_hdr hdr; - struct afe_port_cmd_set_param_v2 param; - struct afe_port_param_data_v2 pdata; - int32_t payload[0]; -} __packed; - -struct afe_dsm_get_command { - struct apr_hdr hdr; - struct afe_port_cmd_get_param_v2 param; - struct afe_port_param_data_v2 pdata; - int32_t payload[0]; -} __packed; - - -/* SRS TRUMEDIA start */ -/* topology */ -#define SRS_TRUMEDIA_TOPOLOGY_ID 0x00010D90 -/* module */ -#define SRS_TRUMEDIA_MODULE_ID 0x10005010 -/* parameters */ -#define SRS_TRUMEDIA_PARAMS 0x10005011 -#define SRS_TRUMEDIA_PARAMS_WOWHD 0x10005012 -#define SRS_TRUMEDIA_PARAMS_CSHP 0x10005013 -#define SRS_TRUMEDIA_PARAMS_HPF 0x10005014 -#define SRS_TRUMEDIA_PARAMS_AEQ 0x10005015 -#define SRS_TRUMEDIA_PARAMS_HL 0x10005016 -#define SRS_TRUMEDIA_PARAMS_GEQ 0x10005017 - -#define SRS_ID_GLOBAL 0x00000001 -#define SRS_ID_WOWHD 0x00000002 -#define SRS_ID_CSHP 0x00000003 -#define SRS_ID_HPF 0x00000004 -#define SRS_ID_AEQ 0x00000005 -#define SRS_ID_HL 0x00000006 -#define SRS_ID_GEQ 0x00000007 - -#define SRS_CMD_UPLOAD 0x7FFF0000 -#define SRS_PARAM_OFFSET_MASK 0x3FFF0000 -#define SRS_PARAM_VALUE_MASK 0x0000FFFF - -struct srs_trumedia_params_GLOBAL { - uint8_t v1; - uint8_t v2; - uint8_t v3; - uint8_t v4; - uint8_t v5; - uint8_t v6; - uint8_t v7; - uint8_t v8; - uint16_t v9; -} __packed; - -struct srs_trumedia_params_WOWHD { - uint32_t v1; - uint16_t v2; - uint16_t v3; - uint16_t v4; - uint16_t v5; - uint16_t v6; - uint16_t v7; - uint16_t v8; - uint16_t v____A1; - uint32_t v9; - uint16_t v10; - uint16_t v11; - uint32_t v12[16]; - uint32_t v13[16]; - uint32_t v14[16]; - uint32_t v15[16]; - uint32_t v16; - uint16_t v17; - uint16_t v18; -} __packed; - -struct srs_trumedia_params_CSHP { - uint32_t v1; - uint16_t v2; - uint16_t v3; - uint16_t v4; - uint16_t v5; - uint16_t v6; - uint16_t v____A1; - uint32_t v7; - uint16_t v8; - uint16_t v9; - uint32_t v10[16]; -} __packed; - -struct srs_trumedia_params_HPF { - uint32_t v1; - uint32_t v2[26]; -} __packed; - -struct srs_trumedia_params_AEQ { - uint32_t v1; - uint16_t v2; - uint16_t v3; - uint16_t v4; - uint16_t v____A1; - uint32_t v5[74]; - uint32_t v6[74]; - uint16_t v7[2048]; -} __packed; - -struct srs_trumedia_params_HL { - uint16_t v1; - uint16_t v2; - uint16_t v3; - uint16_t v____A1; - int32_t v4; - uint32_t v5; - uint16_t v6; - uint16_t v____A2; - uint32_t v7; -} __packed; - -struct srs_trumedia_params_GEQ { - int16_t v1[10]; -} __packed; -struct srs_trumedia_params { - struct srs_trumedia_params_GLOBAL global; - struct srs_trumedia_params_WOWHD wowhd; - struct srs_trumedia_params_CSHP cshp; - struct srs_trumedia_params_HPF hpf; - struct srs_trumedia_params_AEQ aeq; - struct srs_trumedia_params_HL hl; - struct srs_trumedia_params_GEQ geq; -} __packed; -/* SRS TruMedia end */ - -#define AUDPROC_PARAM_ID_ENABLE 0x00010904 -#define ASM_STREAM_POSTPROC_TOPO_ID_SA_PLUS 0x1000FFFF -/* DTS Eagle */ -#define AUDPROC_MODULE_ID_DTS_HPX_PREMIX 0x0001077C -#define AUDPROC_MODULE_ID_DTS_HPX_POSTMIX 0x0001077B -#define ASM_STREAM_POSTPROC_TOPO_ID_DTS_HPX 0x00010DED -#define ASM_STREAM_POSTPROC_TOPO_ID_HPX_PLUS 0x10015000 -#define ASM_STREAM_POSTPROC_TOPO_ID_HPX_MASTER 0x10015001 -struct asm_dts_eagle_param { - struct apr_hdr hdr; - struct asm_stream_cmd_set_pp_params_v2 param; - struct asm_stream_param_data_v2 data; -} __packed; - -struct asm_dts_eagle_param_get { - struct apr_hdr hdr; - struct asm_stream_cmd_get_pp_params_v2 param; -} __packed; - -/* LSM Specific */ -#define VW_FEAT_DIM (39) - -#define APRV2_IDS_SERVICE_ID_ADSP_LSM_V (0xD) -#define APRV2_IDS_DOMAIN_ID_ADSP_V (0x4) -#define APRV2_IDS_DOMAIN_ID_APPS_V (0x5) - -#define LSM_SESSION_CMD_SHARED_MEM_MAP_REGIONS (0x00012A7F) -#define LSM_SESSION_CMDRSP_SHARED_MEM_MAP_REGIONS (0x00012A80) -#define LSM_SESSION_CMD_SHARED_MEM_UNMAP_REGIONS (0x00012A81) -#define LSM_SESSION_CMD_OPEN_TX (0x00012A82) -#define LSM_SESSION_CMD_CLOSE_TX (0x00012A88) -#define LSM_SESSION_CMD_SET_PARAMS (0x00012A83) -#define LSM_SESSION_CMD_SET_PARAMS_V2 (0x00012A8F) -#define LSM_SESSION_CMD_REGISTER_SOUND_MODEL (0x00012A84) -#define LSM_SESSION_CMD_DEREGISTER_SOUND_MODEL (0x00012A85) -#define LSM_SESSION_CMD_START (0x00012A86) -#define LSM_SESSION_CMD_STOP (0x00012A87) -#define LSM_SESSION_CMD_EOB (0x00012A89) -#define LSM_SESSION_CMD_READ (0x00012A8A) -#define LSM_SESSION_CMD_OPEN_TX_V2 (0x00012A8B) -#define LSM_CMD_ADD_TOPOLOGIES (0x00012A8C) - -#define LSM_SESSION_EVENT_DETECTION_STATUS (0x00012B00) -#define LSM_SESSION_EVENT_DETECTION_STATUS_V2 (0x00012B01) -#define LSM_DATA_EVENT_READ_DONE (0x00012B02) -#define LSM_DATA_EVENT_STATUS (0x00012B03) - -#define LSM_MODULE_ID_VOICE_WAKEUP (0x00012C00) -#define LSM_PARAM_ID_ENDPOINT_DETECT_THRESHOLD (0x00012C01) -#define LSM_PARAM_ID_OPERATION_MODE (0x00012C02) -#define LSM_PARAM_ID_GAIN (0x00012C03) -#define LSM_PARAM_ID_CONNECT_TO_PORT (0x00012C04) -#define LSM_PARAM_ID_FEATURE_COMPENSATION_DATA (0x00012C07) -#define LSM_PARAM_ID_MIN_CONFIDENCE_LEVELS (0x00012C07) -#define LSM_MODULE_ID_LAB (0x00012C08) -#define LSM_PARAM_ID_LAB_ENABLE (0x00012C09) -#define LSM_PARAM_ID_LAB_CONFIG (0x00012C0A) -#define LSM_MODULE_ID_FRAMEWORK (0x00012C0E) - -/* HW MAD specific */ -#define AFE_MODULE_HW_MAD (0x00010230) -#define AFE_PARAM_ID_HW_MAD_CFG (0x00010231) -#define AFE_PARAM_ID_HW_MAD_CTRL (0x00010232) -#define AFE_PARAM_ID_SLIMBUS_SLAVE_PORT_CFG (0x00010233) - -/* SW MAD specific */ -#define AFE_MODULE_SW_MAD (0x0001022D) -#define AFE_PARAM_ID_SW_MAD_CFG (0x0001022E) -#define AFE_PARAM_ID_SVM_MODEL (0x0001022F) - -/* Commands/Params to pass the codec/slimbus data to DSP */ -#define AFE_SVC_CMD_SET_PARAM (0x000100f3) -#define AFE_MODULE_CDC_DEV_CFG (0x00010234) -#define AFE_PARAM_ID_CDC_SLIMBUS_SLAVE_CFG (0x00010235) -#define AFE_PARAM_ID_CDC_REG_CFG (0x00010236) -#define AFE_PARAM_ID_CDC_REG_CFG_INIT (0x00010237) - -#define AFE_MAX_CDC_REGISTERS_TO_CONFIG (20) - -/* AANC Port Config Specific */ -#define AFE_PARAM_ID_AANC_PORT_CONFIG (0x00010215) -#define AFE_API_VERSION_AANC_PORT_CONFIG (0x1) -#define AANC_TX_MIC_UNUSED (0) -#define AANC_TX_VOICE_MIC (1) -#define AANC_TX_ERROR_MIC (2) -#define AANC_TX_NOISE_MIC (3) -#define AFE_PORT_MAX_CHANNEL_CNT (8) -#define AFE_MODULE_AANC (0x00010214) -#define AFE_PARAM_ID_CDC_AANC_VERSION (0x0001023A) -#define AFE_API_VERSION_CDC_AANC_VERSION (0x1) -#define AANC_HW_BLOCK_VERSION_1 (1) -#define AANC_HW_BLOCK_VERSION_2 (2) - -/*Clip bank selection*/ -#define AFE_API_VERSION_CLIP_BANK_SEL_CFG 0x1 -#define AFE_CLIP_MAX_BANKS 4 -#define AFE_PARAM_ID_CLIP_BANK_SEL_CFG 0x00010242 - -struct afe_param_aanc_port_cfg { - /* Minor version used for tracking the version of the module's - * source port configuration. - */ - uint32_t aanc_port_cfg_minor_version; - - /* Sampling rate of the source Tx port. 8k - 192k*/ - uint32_t tx_port_sample_rate; - - /* Channel mapping for the Tx port signal carrying Noise (X), - * Error (E), and Voice (V) signals. - */ - uint8_t tx_port_channel_map[AFE_PORT_MAX_CHANNEL_CNT]; - - /* Number of channels on the source Tx port. */ - uint16_t tx_port_num_channels; - - /* Port ID of the Rx path reference signal. */ - uint16_t rx_path_ref_port_id; - - /* Sampling rate of the reference port. 8k - 192k*/ - uint32_t ref_port_sample_rate; -} __packed; - -struct afe_param_id_cdc_aanc_version { - /* Minor version used for tracking the version of the module's - * hw version - */ - uint32_t cdc_aanc_minor_version; - - /* HW version. */ - uint32_t aanc_hw_version; -} __packed; - -struct afe_param_id_clip_bank_sel { - /* Minor version used for tracking the version of the module's - * hw version - */ - uint32_t minor_version; - - /* Number of banks to be read */ - uint32_t num_banks; - - uint32_t bank_map[AFE_CLIP_MAX_BANKS]; -} __packed; - -/* ERROR CODES */ -/* Success. The operation completed with no errors. */ -#define ADSP_EOK 0x00000000 -/* General failure. */ -#define ADSP_EFAILED 0x00000001 -/* Bad operation parameter. */ -#define ADSP_EBADPARAM 0x00000002 -/* Unsupported routine or operation. */ -#define ADSP_EUNSUPPORTED 0x00000003 -/* Unsupported version. */ -#define ADSP_EVERSION 0x00000004 -/* Unexpected problem encountered. */ -#define ADSP_EUNEXPECTED 0x00000005 -/* Unhandled problem occurred. */ -#define ADSP_EPANIC 0x00000006 -/* Unable to allocate resource. */ -#define ADSP_ENORESOURCE 0x00000007 -/* Invalid handle. */ -#define ADSP_EHANDLE 0x00000008 -/* Operation is already processed. */ -#define ADSP_EALREADY 0x00000009 -/* Operation is not ready to be processed. */ -#define ADSP_ENOTREADY 0x0000000A -/* Operation is pending completion. */ -#define ADSP_EPENDING 0x0000000B -/* Operation could not be accepted or processed. */ -#define ADSP_EBUSY 0x0000000C -/* Operation aborted due to an error. */ -#define ADSP_EABORTED 0x0000000D -/* Operation preempted by a higher priority. */ -#define ADSP_EPREEMPTED 0x0000000E -/* Operation requests intervention to complete. */ -#define ADSP_ECONTINUE 0x0000000F -/* Operation requests immediate intervention to complete. */ -#define ADSP_EIMMEDIATE 0x00000010 -/* Operation is not implemented. */ -#define ADSP_ENOTIMPL 0x00000011 -/* Operation needs more data or resources. */ -#define ADSP_ENEEDMORE 0x00000012 -/* Operation does not have memory. */ -#define ADSP_ENOMEMORY 0x00000014 -/* Item does not exist. */ -#define ADSP_ENOTEXIST 0x00000015 -/* Max count for adsp error code sent to HLOS*/ -#define ADSP_ERR_MAX (ADSP_ENOTEXIST + 1) -/* Operation is finished. */ -#define ADSP_ETERMINATED 0x00011174 - -/*bharath, adsp_error_codes.h */ - -/* LPASS clock for I2S Interface */ - -/* Supported OSR clock values */ -#define Q6AFE_LPASS_OSR_CLK_12_P288_MHZ 0xBB8000 -#define Q6AFE_LPASS_OSR_CLK_8_P192_MHZ 0x7D0000 -#define Q6AFE_LPASS_OSR_CLK_6_P144_MHZ 0x5DC000 -#define Q6AFE_LPASS_OSR_CLK_4_P096_MHZ 0x3E8000 -#define Q6AFE_LPASS_OSR_CLK_3_P072_MHZ 0x2EE000 -#define Q6AFE_LPASS_OSR_CLK_2_P048_MHZ 0x1F4000 -#define Q6AFE_LPASS_OSR_CLK_1_P536_MHZ 0x177000 -#define Q6AFE_LPASS_OSR_CLK_1_P024_MHZ 0xFA000 -#define Q6AFE_LPASS_OSR_CLK_768_kHZ 0xBB800 -#define Q6AFE_LPASS_OSR_CLK_512_kHZ 0x7D000 -#define Q6AFE_LPASS_OSR_CLK_DISABLE 0x0 - -/* Supported Bit clock values */ -#define Q6AFE_LPASS_IBIT_CLK_12_P288_MHZ 0xBB8000 -#define Q6AFE_LPASS_IBIT_CLK_8_P192_MHZ 0x7D0000 -#define Q6AFE_LPASS_IBIT_CLK_6_P144_MHZ 0x5DC000 -#define Q6AFE_LPASS_IBIT_CLK_4_P096_MHZ 0x3E8000 -#define Q6AFE_LPASS_IBIT_CLK_3_P072_MHZ 0x2EE000 -#define Q6AFE_LPASS_IBIT_CLK_2_P048_MHZ 0x1F4000 -#define Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ 0x177000 -#define Q6AFE_LPASS_IBIT_CLK_1_P024_MHZ 0xFA000 -#define Q6AFE_LPASS_IBIT_CLK_768_KHZ 0xBB800 -#define Q6AFE_LPASS_IBIT_CLK_512_KHZ 0x7D000 -#define Q6AFE_LPASS_IBIT_CLK_256_KHZ 0x3E800 -#define Q6AFE_LPASS_IBIT_CLK_DISABLE 0x0 - -/* Supported LPASS CLK sources */ -#define Q6AFE_LPASS_CLK_SRC_EXTERNAL 0 -#define Q6AFE_LPASS_CLK_SRC_INTERNAL 1 - -/* Supported LPASS CLK root*/ -#define Q6AFE_LPASS_CLK_ROOT_DEFAULT 0 - -enum afe_lpass_clk_mode { - Q6AFE_LPASS_MODE_BOTH_INVALID, - Q6AFE_LPASS_MODE_CLK1_VALID, - Q6AFE_LPASS_MODE_CLK2_VALID, - Q6AFE_LPASS_MODE_BOTH_VALID, -} __packed; - -struct afe_clk_cfg { -/* Minor version used for tracking the version of the I2S - * configuration interface. - * Supported values: #AFE_API_VERSION_I2S_CONFIG - */ - u32 i2s_cfg_minor_version; - -/* clk value 1 in MHz. */ - u32 clk_val1; - -/* clk value 2 in MHz. */ - u32 clk_val2; - -/* clk_src - * #Q6AFE_LPASS_CLK_SRC_EXTERNAL - * #Q6AFE_LPASS_CLK_SRC_INTERNAL - */ - - u16 clk_src; - -/* clk_root -0 for default */ - u16 clk_root; - -/* clk_set_mode - * #Q6AFE_LPASS_MODE_BOTH_INVALID - * #Q6AFE_LPASS_MODE_CLK1_VALID - * #Q6AFE_LPASS_MODE_CLK2_VALID - * #Q6AFE_LPASS_MODE_BOTH_VALID - */ - u16 clk_set_mode; - -/* This param id is used to configure I2S clk */ - u16 reserved; -} __packed; - -/* This param id is used to configure I2S clk */ -#define AFE_PARAM_ID_LPAIF_CLK_CONFIG 0x00010238 - - -struct afe_lpass_clk_config_command { - struct apr_hdr hdr; - struct afe_port_cmd_set_param_v2 param; - struct afe_port_param_data_v2 pdata; - struct afe_clk_cfg clk_cfg; -} __packed; - -enum afe_lpass_digital_clk_src { - Q6AFE_LPASS_DIGITAL_ROOT_INVALID, - Q6AFE_LPASS_DIGITAL_ROOT_PRI_MI2S_OSR, - Q6AFE_LPASS_DIGITAL_ROOT_SEC_MI2S_OSR, - Q6AFE_LPASS_DIGITAL_ROOT_TER_MI2S_OSR, - Q6AFE_LPASS_DIGITAL_ROOT_QUAD_MI2S_OSR, - Q6AFE_LPASS_DIGITAL_ROOT_CDC_ROOT_CLK, -} __packed; - -/* This param id is used to configure internal clk */ -#define AFE_PARAM_ID_INTERNAL_DIGIATL_CDC_CLK_CONFIG 0x00010239 - -struct afe_digital_clk_cfg { -/* Minor version used for tracking the version of the I2S - * configuration interface. - * Supported values: #AFE_API_VERSION_I2S_CONFIG - */ - u32 i2s_cfg_minor_version; - -/* clk value in MHz. */ - u32 clk_val; - -/* INVALID - * PRI_MI2S_OSR - * SEC_MI2S_OSR - * TER_MI2S_OSR - * QUAD_MI2S_OSR - * DIGT_CDC_ROOT - */ - u16 clk_root; - -/* This field must be set to zero. */ - u16 reserved; -} __packed; - - -struct afe_lpass_digital_clk_config_command { - struct apr_hdr hdr; - struct afe_port_cmd_set_param_v2 param; - struct afe_port_param_data_v2 pdata; - struct afe_digital_clk_cfg clk_cfg; -} __packed; - -/* - * Opcode for AFE to start DTMF. - */ -#define AFE_PORTS_CMD_DTMF_CTL 0x00010102 - -/** DTMF payload.*/ -struct afe_dtmf_generation_command { - struct apr_hdr hdr; - - /* - * Duration of the DTMF tone in ms. - * -1 -> continuous, - * 0 -> disable - */ - int64_t duration_in_ms; - - /* - * The DTMF high tone frequency. - */ - uint16_t high_freq; - - /* - * The DTMF low tone frequency. - */ - uint16_t low_freq; - - /* - * The DTMF volume setting - */ - uint16_t gain; - - /* - * The number of ports to enable/disable on. - */ - uint16_t num_ports; - - /* - * The Destination ports - array . - * For DTMF on multiple ports, portIds needs to - * be populated numPorts times. - */ - uint16_t port_ids; - - /* - * variable for 32 bit alignment of APR packet. - */ - uint16_t reserved; -} __packed; - -enum afe_config_type { - AFE_SLIMBUS_SLAVE_PORT_CONFIG, - AFE_SLIMBUS_SLAVE_CONFIG, - AFE_CDC_REGISTERS_CONFIG, - AFE_AANC_VERSION, - AFE_CDC_CLIP_REGISTERS_CONFIG, - AFE_CLIP_BANK_SEL, - AFE_MAX_CONFIG_TYPES, -}; - -struct afe_param_slimbus_slave_port_cfg { - uint32_t minor_version; - uint16_t slimbus_dev_id; - uint16_t slave_dev_pgd_la; - uint16_t slave_dev_intfdev_la; - uint16_t bit_width; - uint16_t data_format; - uint16_t num_channels; - uint16_t slave_port_mapping[AFE_PORT_MAX_AUDIO_CHAN_CNT]; -} __packed; - -struct afe_param_cdc_slimbus_slave_cfg { - uint32_t minor_version; - uint32_t device_enum_addr_lsw; - uint32_t device_enum_addr_msw; - uint16_t tx_slave_port_offset; - uint16_t rx_slave_port_offset; -} __packed; - -struct afe_param_cdc_reg_cfg { - uint32_t minor_version; - uint32_t reg_logical_addr; - uint32_t reg_field_type; - uint32_t reg_field_bit_mask; - uint16_t reg_bit_width; - uint16_t reg_offset_scale; -} __packed; - -struct afe_param_cdc_reg_cfg_data { - uint32_t num_registers; - struct afe_param_cdc_reg_cfg *reg_data; -} __packed; - -struct afe_svc_cmd_set_param { - uint32_t payload_size; - uint32_t payload_address_lsw; - uint32_t payload_address_msw; - uint32_t mem_map_handle; -} __packed; - -struct afe_param_hw_mad_ctrl { - uint32_t minor_version; - uint16_t mad_type; - uint16_t mad_enable; -} __packed; - -struct afe_cmd_hw_mad_ctrl { - struct apr_hdr hdr; - struct afe_port_cmd_set_param_v2 param; - struct afe_port_param_data_v2 pdata; - struct afe_param_hw_mad_ctrl payload; -} __packed; - -struct afe_cmd_hw_mad_slimbus_slave_port_cfg { - struct apr_hdr hdr; - struct afe_port_cmd_set_param_v2 param; - struct afe_port_param_data_v2 pdata; - struct afe_param_slimbus_slave_port_cfg sb_port_cfg; -} __packed; - -struct afe_cmd_sw_mad_enable { - struct apr_hdr hdr; - struct afe_port_cmd_set_param_v2 param; - struct afe_port_param_data_v2 pdata; -} __packed; - -struct afe_param_cdc_reg_cfg_payload { - struct afe_port_param_data_v2 common; - struct afe_param_cdc_reg_cfg reg_cfg; -} __packed; - -/* - * reg_data's size can be up to AFE_MAX_CDC_REGISTERS_TO_CONFIG - */ -struct afe_svc_cmd_cdc_reg_cfg { - struct apr_hdr hdr; - struct afe_svc_cmd_set_param param; - struct afe_param_cdc_reg_cfg_payload reg_data[0]; -} __packed; - -struct afe_svc_cmd_init_cdc_reg_cfg { - struct apr_hdr hdr; - struct afe_svc_cmd_set_param param; - struct afe_port_param_data_v2 init; -} __packed; - -struct afe_svc_cmd_sb_slave_cfg { - struct apr_hdr hdr; - struct afe_svc_cmd_set_param param; - struct afe_port_param_data_v2 pdata; - struct afe_param_cdc_slimbus_slave_cfg sb_slave_cfg; -} __packed; - -struct afe_svc_cmd_cdc_aanc_version { - struct apr_hdr hdr; - struct afe_svc_cmd_set_param param; - struct afe_port_param_data_v2 pdata; - struct afe_param_id_cdc_aanc_version version; -} __packed; - -struct afe_port_cmd_set_aanc_param { - struct apr_hdr hdr; - struct afe_port_cmd_set_param_v2 param; - struct afe_port_param_data_v2 pdata; - union { - struct afe_param_aanc_port_cfg aanc_port_cfg; - struct afe_mod_enable_param mod_enable; - } __packed data; -} __packed; - -struct afe_port_cmd_set_aanc_acdb_table { - struct apr_hdr hdr; - struct afe_port_cmd_set_param_v2 param; -} __packed; - -/* Dolby DAP topology */ -#define DOLBY_ADM_COPP_TOPOLOGY_ID 0x0001033B -#define DS2_ADM_COPP_TOPOLOGY_ID 0x1301033B - -/* RMS value from DSP */ -#define RMS_MODULEID_APPI_PASSTHRU 0x10009011 -#define RMS_PARAM_FIRST_SAMPLE 0x10009012 -#define RMS_PAYLOAD_LEN 4 - -/* Customized mixing in matix mixer */ -#define MTMX_MODULE_ID_DEFAULT_CHMIXER 0x00010341 -#define DEFAULT_CHMIXER_PARAM_ID_COEFF 0x00010342 -#define CUSTOM_STEREO_PAYLOAD_SIZE 9 -#define CUSTOM_STEREO_CMD_PARAM_SIZE 24 -#define CUSTOM_STEREO_NUM_OUT_CH 0x0002 -#define CUSTOM_STEREO_NUM_IN_CH 0x0002 -#define CUSTOM_STEREO_INDEX_PARAM 0x0002 -#define Q14_GAIN_ZERO_POINT_FIVE 0x2000 -#define Q14_GAIN_UNITY 0x4000 - -struct afe_svc_cmd_set_clip_bank_selection { - struct apr_hdr hdr; - struct afe_svc_cmd_set_param param; - struct afe_port_param_data_v2 pdata; - struct afe_param_id_clip_bank_sel bank_sel; -} __packed; - -/* Ultrasound supported formats */ -#define US_POINT_EPOS_FORMAT_V2 0x0001272D -#define US_RAW_FORMAT_V2 0x0001272C -#define US_PROX_FORMAT_V4 0x0001273B -#define US_RAW_SYNC_FORMAT 0x0001272F -#define US_GES_SYNC_FORMAT 0x00012730 - -#define AFE_MODULE_GROUP_DEVICE 0x00010254 -#define AFE_PARAM_ID_GROUP_DEVICE_CFG 0x00010255 -#define AFE_PARAM_ID_GROUP_DEVICE_ENABLE 0x00010256 -#define AFE_GROUP_DEVICE_ID_SECONDARY_MI2S_RX 0x1102 - -/* Payload of the #AFE_PARAM_ID_GROUP_DEVICE_CFG - * parameter, which configures max of 8 AFE ports - * into a group. - * The fixed size of this structure is sixteen bytes. - */ -struct afe_group_device_group_cfg { - u32 minor_version; - u16 group_id; - u16 num_channels; - u16 port_id[8]; -} __packed; - - -/* Payload of the #AFE_PARAM_ID_GROUP_DEVICE_ENABLE - * parameter, which enables or - * disables any module. - * The fixed size of this structure is four bytes. - */ - -struct afe_group_device_enable { - u16 group_id; - /* valid value is AFE_GROUP_DEVICE_ID_SECONDARY_MI2S_RX */ - u16 enable; -/* Enables (1) or disables (0) the module. */ -} __packed; - -struct afe_port_group_create { - struct apr_hdr hdr; - struct afe_svc_cmd_set_param param; - struct afe_port_param_data_v2 pdata; - union { - struct afe_group_device_group_cfg group_cfg; - struct afe_group_device_enable group_enable; - } __packed data; -} __packed; - -/* Command for Matrix or Stream Router */ -#define ASM_SESSION_CMD_SET_MTMX_STRTR_PARAMS_V2 0x00010DCE -/* Module for AVSYNC */ -#define ASM_SESSION_MTMX_STRTR_MODULE_ID_AVSYNC 0x00010DC6 - -/* Parameter used by #ASM_SESSION_MTMX_STRTR_MODULE_ID_AVSYNC to specify the - * render window start value. This parameter is supported only for a Set - * command (not a Get command) in the Rx direction - * (#ASM_SESSION_CMD_SET_MTMX_STRTR_PARAMS_V2). - * Render window start is a value (session time minus timestamp, or ST-TS) - * below which frames are held, and after which frames are immediately - * rendered. - */ -#define ASM_SESSION_MTMX_STRTR_PARAM_RENDER_WINDOW_START_V2 0x00010DD1 - -/* Parameter used by #ASM_SESSION_MTMX_STRTR_MODULE_ID_AVSYNC to specify the - * render window end value. This parameter is supported only for a Set - * command (not a Get command) in the Rx direction - * (#ASM_SESSION_CMD_SET_MTMX_STRTR_PARAMS_V2). Render window end is a value - * (session time minus timestamp) above which frames are dropped, and below - * which frames are immediately rendered. - */ -#define ASM_SESSION_MTMX_STRTR_PARAM_RENDER_WINDOW_END_V2 0x00010DD2 - -/* Generic payload of the window parameters in the - * #ASM_SESSION_MTMX_STRTR_MODULE_ID_AVSYNC module. - * This payload is supported only for a Set command - * (not a Get command) on the Rx path. - */ -struct asm_session_mtmx_strtr_param_window_v2_t { - u32 window_lsw; - /* Lower 32 bits of the render window start value. */ - - u32 window_msw; - /* Upper 32 bits of the render window start value. - - * The 64-bit number formed by window_lsw and window_msw specifies a - * signed 64-bit window value in microseconds. The sign extension is - * necessary. This value is used by the following parameter IDs: - * #ASM_SESSION_MTMX_STRTR_PARAM_RENDER_WINDOW_START_V2 - * #ASM_SESSION_MTMX_STRTR_PARAM_RENDER_WINDOW_END_V2 - * #ASM_SESSION_MTMX_STRTR_PARAM_STAT_WINDOW_START_V2 - * #ASM_SESSION_MTMX_STRTR_PARAM_STAT_WINDOW_END_V2 - * The value depends on which parameter ID is used. - * The aDSP honors the windows at a granularity of 1 ms. - */ -}; - -struct asm_session_cmd_set_mtmx_strstr_params_v2 { - uint32_t data_payload_addr_lsw; - /* Lower 32 bits of the 64-bit data payload address. */ - - uint32_t data_payload_addr_msw; - /* Upper 32 bits of the 64-bit data payload address. - * If the address is not sent (NULL), the message is in the payload. - * If the address is sent (non-NULL), the parameter data payloads - * begin at the specified address. - */ - - uint32_t mem_map_handle; - /* Unique identifier for an address. This memory map handle is returned - * by the aDSP through the #ASM_CMD_SHARED_MEM_MAP_REGIONS command. - * values - * - NULL -- Parameter data payloads are within the message payload - * (in-band). - * - Non-NULL -- Parameter data payloads begin at the address specified - * in the data_payload_addr_lsw and data_payload_addr_msw fields - * (out-of-band). - */ - - uint32_t data_payload_size; - /* Actual size of the variable payload accompanying the message, or in - * shared memory. This field is used for parsing the parameter payload. - * values > 0 bytes - */ - - uint32_t direction; - /* Direction of the entity (matrix mixer or stream router) on which - * the parameter is to be set. - * values - * - 0 -- Rx (for Rx stream router or Rx matrix mixer) - * - 1 -- Tx (for Tx stream router or Tx matrix mixer) - */ -}; - -struct asm_mtmx_strtr_params { - struct apr_hdr hdr; - struct asm_session_cmd_set_mtmx_strstr_params_v2 param; - struct asm_stream_param_data_v2 data; - u32 window_lsw; - u32 window_msw; -} __packed; -#define AUDPROC_MODULE_ID_RESAMPLER 0x00010719 - -enum { - LEGACY_PCM = 0, - COMPRESSED_PASSTHROUGH, - COMPRESSED_PASSTHROUGH_CONVERT, -}; - -#define AUDPROC_MODULE_ID_COMPRESSED_MUTE 0x00010770 -#define AUDPROC_PARAM_ID_COMPRESSED_MUTE 0x00010771 - -struct adm_set_compressed_device_mute { - struct adm_cmd_set_pp_params_v5 command; - struct adm_param_data_v5 params; - u32 mute_on; -} __packed; - -#define AUDPROC_MODULE_ID_COMPRESSED_LATENCY 0x0001076E -#define AUDPROC_PARAM_ID_COMPRESSED_LATENCY 0x0001076F - -struct adm_set_compressed_device_latency { - struct adm_cmd_set_pp_params_v5 command; - struct adm_param_data_v5 params; - u32 latency; -} __packed; -#endif /*_APR_AUDIO_V2_H_ */ diff --git a/include/trace/events/sched.h b/include/trace/events/sched.h index d1974c69e7ce..be3d8b29405b 100644 --- a/include/trace/events/sched.h +++ b/include/trace/events/sched.h @@ -1418,6 +1418,7 @@ TRACE_EVENT(sched_contrib_scale_f, extern unsigned int sysctl_sched_use_walt_cpu_util; extern unsigned int sysctl_sched_use_walt_task_util; extern unsigned int sched_ravg_window; +extern unsigned int walt_disabled; #endif /* diff --git a/include/uapi/linux/coresight-stm.h b/include/uapi/linux/coresight-stm.h index fac630e1acdf..bdedcbbe68fd 100644 --- a/include/uapi/linux/coresight-stm.h +++ b/include/uapi/linux/coresight-stm.h @@ -29,4 +29,3 @@ enum { }; #endif - diff --git a/include/uapi/linux/cryptouser.h b/include/uapi/linux/cryptouser.h index 11d21fce14d6..79b5ded2001a 100644 --- a/include/uapi/linux/cryptouser.h +++ b/include/uapi/linux/cryptouser.h @@ -46,7 +46,6 @@ enum crypto_attr_type_t { CRYPTOCFGA_REPORT_CIPHER, /* struct crypto_report_cipher */ CRYPTOCFGA_REPORT_AKCIPHER, /* struct crypto_report_akcipher */ CRYPTOCFGA_REPORT_KPP, /* struct crypto_report_kpp */ - CRYPTOCFGA_REPORT_ACOMP, /* struct crypto_report_acomp */ __CRYPTOCFGA_MAX #define CRYPTOCFGA_MAX (__CRYPTOCFGA_MAX - 1) @@ -113,9 +112,5 @@ struct crypto_report_kpp { char type[CRYPTO_MAX_NAME]; }; -struct crypto_report_acomp { - char type[CRYPTO_MAX_NAME]; -}; - #define CRYPTO_REPORT_MAXSIZE (sizeof(struct crypto_user_alg) + \ sizeof(struct crypto_report_blkcipher)) diff --git a/include/uapi/media/cam_isp.h b/include/uapi/media/cam_isp.h index 425f4d1e3b3a..50d95c4da9d8 100644 --- a/include/uapi/media/cam_isp.h +++ b/include/uapi/media/cam_isp.h @@ -4,7 +4,7 @@ #include "cam_defs.h" #include "cam_isp_vfe.h" #include "cam_isp_ife.h" - +#include "cam_cpas.h" /* ISP driver name */ #define CAM_ISP_DEV_NAME "cam-isp" @@ -84,14 +84,22 @@ #define CAM_ISP_DSP_MODE_ROUND 2 /* ISP Generic Cmd Buffer Blob types */ -#define CAM_ISP_GENERIC_BLOB_TYPE_HFR_CONFIG 0 -#define CAM_ISP_GENERIC_BLOB_TYPE_CLOCK_CONFIG 1 -#define CAM_ISP_GENERIC_BLOB_TYPE_BW_CONFIG 2 -#define CAM_ISP_GENERIC_BLOB_TYPE_FPS_CONFIG 3 -#define CAM_ISP_GENERIC_BLOB_TYPE_UBWC_CONFIG 4 -#define CAM_ISP_GENERIC_BLOB_TYPE_CSID_CLOCK_CONFIG 5 -#define CAM_ISP_GENERIC_BLOB_TYPE_FE_CONFIG 6 -#define CAM_ISP_GENERIC_BLOB_TYPE_BW_CONFIG_V2 7 +#define CAM_ISP_GENERIC_BLOB_TYPE_HFR_CONFIG 0 +#define CAM_ISP_GENERIC_BLOB_TYPE_CLOCK_CONFIG 1 +#define CAM_ISP_GENERIC_BLOB_TYPE_BW_CONFIG 2 +#define CAM_ISP_GENERIC_BLOB_TYPE_UBWC_CONFIG 3 +#define CAM_ISP_GENERIC_BLOB_TYPE_CSID_CLOCK_CONFIG 4 +#define CAM_ISP_GENERIC_BLOB_TYPE_FE_CONFIG 5 +#define CAM_ISP_GENERIC_BLOB_TYPE_BW_CONFIG_V2 6 +#define CAM_ISP_GENERIC_BLOB_TYPE_INIT_FRAME_DROP 10 +#define CAM_ISP_GENERIC_BLOB_TYPE_SENSOR_DIMENSION_CONFIG 11 +#define CAM_ISP_GENERIC_BLOB_TYPE_FPS_CONFIG 12 + +/* Per Path Usage Data */ +#define CAM_ISP_USAGE_INVALID 0 +#define CAM_ISP_USAGE_LEFT_PX 1 +#define CAM_ISP_USAGE_RIGHT_PX 2 +#define CAM_ISP_USAGE_RDI 3 /* Query devices */ /** @@ -363,7 +371,6 @@ struct cam_isp_csid_clock_config { * @cam_bw_bps: Bandwidth vote for CAMNOC * @ext_bw_bps: Bandwidth vote for path-to-DDR after CAMNOC */ - struct cam_isp_bw_vote { uint32_t resource_id; uint32_t reserved; @@ -380,7 +387,6 @@ struct cam_isp_bw_vote { * @right_pix_vote: Bandwidth vote for right ISP * @rdi_vote: RDI bandwidth requirements */ - struct cam_isp_bw_config { uint32_t usage_type; uint32_t num_rdi; @@ -408,6 +414,19 @@ struct cam_isp_bw_config_ab { uint64_t rdi_vote_ab[1]; } __attribute__((packed)); +/** + * struct cam_isp_bw_config_v2 - Bandwidth configuration + * + * @usage_type: Usage type (Single/Dual) + * @num_paths: Number of axi data paths + * @axi_path Per path vote info + */ +struct cam_isp_bw_config_v2 { + uint32_t usage_type; + uint32_t num_paths; + struct cam_axi_per_path_bw_vote axi_path[1]; +} __attribute__((packed)); + /** * struct cam_fe_config - Fetch Engine configuration * @@ -448,14 +467,34 @@ struct cam_fe_config { } __attribute__((packed)); /** - * struct cam_isp_fps_config - ISP usecase fps param + * struct cam_isp_sensor_path_dimension * - * @fps : usecase fps + * @width expected width + * @height expected height + * @measure_enabled flag to indicate if pixel measurement is to be enabled */ -struct cam_isp_fps_config { - uint32_t fps; +struct cam_isp_sensor_dimension { + uint32_t width; + uint32_t height; + uint32_t measure_enabled; } __attribute__((packed)); +/** + * struct cam_isp_sensor_config - Sensor Dimension configuration + * + * @pix_path: expected ppp path configuration + * @pix_path: expected ipp path configuration + * @rdi_path: expected rdi path configuration + * @hbi: HBI value + * @vbi: VBI value + */ +struct cam_isp_sensor_config { + struct cam_isp_sensor_dimension ppp_path; + struct cam_isp_sensor_dimension ipp_path; + struct cam_isp_sensor_dimension rdi_path[4]; + uint32_t hbi; + uint32_t vbi; +} __attribute__((packed)); /* Acquire Device/HW v2 */ @@ -482,6 +521,15 @@ struct cam_isp_acquire_hw_info { uint64_t data; }; +/** + * struct cam_fps_config - FPS blob support + * + * @fps: FPS value + */ +struct cam_fps_config { + uint32_t fps; +} __attribute__((packed)); + #define CAM_ISP_ACQUIRE_COMMON_VER0 0x1000 #define CAM_ISP_ACQUIRE_COMMON_SIZE_VER0 0x0 @@ -490,5 +538,14 @@ struct cam_isp_acquire_hw_info { #define CAM_ISP_ACQUIRE_OUT_VER0 0x3000 -#endif /* __UAPI_CAM_ISP_H__ */ +/** + * struct cam_isp_init_frame_drop_config - init frame drop configuration + * + * @init_frame_drop: Initial number of frames needs to drop + */ +struct cam_isp_init_frame_drop_config { + uint32_t init_frame_drop; +} __attribute__((packed)); + +#endif /* __UAPI_CAM_ISP_H__ */ diff --git a/include/uapi/sound/compress_params.h b/include/uapi/sound/compress_params.h index 92a94e15b33b..20431fef76a2 100644 --- a/include/uapi/sound/compress_params.h +++ b/include/uapi/sound/compress_params.h @@ -409,10 +409,18 @@ struct snd_dec_aptx { __u32 nap; }; +/** struct snd_dec_pcm - codec options for PCM format + * @num_channels: Number of channels + * @ch_map: Channel map for the above corresponding channels + */ +struct snd_dec_pcm { + __u32 num_channels; + __u8 ch_map[MAX_PCM_DECODE_CHANNELS]; +} __attribute__((packed, aligned(4))); + struct snd_dec_amrwb_plus { __u32 bit_stream_fmt; }; - union snd_codec_options { struct snd_enc_wma wma; struct snd_enc_vorbis vorbis; @@ -425,6 +433,7 @@ union snd_codec_options { struct snd_dec_alac alac; struct snd_dec_ape ape; struct snd_dec_aptx aptx_dec; + struct snd_dec_pcm pcm_dec; struct snd_dec_amrwb_plus amrwbplus; }; @@ -525,4 +534,3 @@ struct snd_codec_metadata { }; #endif - diff --git a/include/video/adf_memblock.h~118d4ca773be226aba92180bb87a55438fbf1acf b/include/video/adf_memblock.h similarity index 100% rename from include/video/adf_memblock.h~118d4ca773be226aba92180bb87a55438fbf1acf rename to include/video/adf_memblock.h diff --git a/include/video/adf_memblock.h~HEAD b/include/video/adf_memblock.h~HEAD deleted file mode 100644 index 6256e0eebcc9..000000000000 --- a/include/video/adf_memblock.h~HEAD +++ /dev/null @@ -1,20 +0,0 @@ -/* - * Copyright (C) 2013 Google, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef _VIDEO_ADF_MEMBLOCK_H_ -#define _VIDEO_ADF_MEMBLOCK_H_ - -struct dma_buf *adf_memblock_export(phys_addr_t base, size_t size, int flags); - -#endif /* _VIDEO_ADF_MEMBLOCK_H_ */ diff --git a/init/Kconfig b/init/Kconfig index 361b2cc3a318..6b5e69a360aa 100644 --- a/init/Kconfig +++ b/init/Kconfig @@ -1448,15 +1448,6 @@ config SCHED_TUNE If unsure, say N. -config DYNAMIC_STUNE_BOOST - bool "Dynamic SchedTune boosting support" - depends on SCHED_TUNE && CGROUP_SCHEDTUNE - help - This option extends the SchedTune framework and provides APIs to - activate and reset SchedTune boosting from anywhere in the kernel. - - If unsure, say N. - config DEFAULT_USE_ENERGY_AWARE bool "Default to enabling the Energy Aware Scheduler feature" default n diff --git a/kernel/cpu.c b/kernel/cpu.c index c23b6f2ac228..767a96a5f365 100644 --- a/kernel/cpu.c +++ b/kernel/cpu.c @@ -1310,7 +1310,7 @@ int freeze_secondary_cpus(int primary) */ cpumask_clear(frozen_cpus); - pr_debug("Disabling non-boot CPUs ...\n"); + pr_info("Disabling non-boot CPUs ...\n"); for_each_online_cpu(cpu) { if (cpu == primary) continue; @@ -1360,7 +1360,7 @@ void enable_nonboot_cpus(void) if (cpumask_empty(frozen_cpus)) goto out; - pr_debug("Enabling non-boot CPUs ...\n"); + pr_info("Enabling non-boot CPUs ...\n"); arch_enable_nonboot_cpus_begin(); @@ -1369,7 +1369,7 @@ void enable_nonboot_cpus(void) error = _cpu_up(cpu, 1, CPUHP_ONLINE); trace_suspend_resume(TPS("CPU_ON"), cpu, false); if (!error) { - pr_debug("CPU%d is up\n", cpu); + pr_info("CPU%d is up\n", cpu); cpu_device = get_cpu_device(cpu); if (!cpu_device) pr_err("%s: failed to get cpu%d device\n", @@ -2270,6 +2270,21 @@ EXPORT_SYMBOL(__cpu_active_mask); struct cpumask __cpu_isolated_mask __read_mostly; EXPORT_SYMBOL(__cpu_isolated_mask); +/* + * This assumes that half of the CPUs are little and that they have lower + * CPU numbers than the big CPUs (e.g., on an 8-core system, CPUs 0-3 would be + * little and CPUs 4-7 would be big). + */ +#define LITTLE_CPU_MASK ((1UL << (NR_CPUS / 2)) - 1) +#define BIG_CPU_MASK (((1UL << NR_CPUS) - 1) & ~LITTLE_CPU_MASK) +static const unsigned long little_cluster_cpus = LITTLE_CPU_MASK; +const struct cpumask *const cpu_lp_mask = to_cpumask(&little_cluster_cpus); +EXPORT_SYMBOL(cpu_lp_mask); + +static const unsigned long big_cluster_cpus = BIG_CPU_MASK; +const struct cpumask *const cpu_perf_mask = to_cpumask(&big_cluster_cpus); +EXPORT_SYMBOL(cpu_perf_mask); + void init_cpu_present(const struct cpumask *src) { cpumask_copy(&__cpu_present_mask, src); diff --git a/kernel/fork.c b/kernel/fork.c index 4d0273f72e0d..04e239cdcfaa 100644 --- a/kernel/fork.c +++ b/kernel/fork.c @@ -79,7 +79,6 @@ #include #include #include -#include #include #include @@ -897,7 +896,6 @@ static inline void __mmput(struct mm_struct *mm) } if (mm->binfmt) module_put(mm->binfmt->module); - simple_lmk_mm_freed(mm); mmdrop(mm); } diff --git a/kernel/locking/spinlock_debug.c b/kernel/locking/spinlock_debug.c index 6558fbd47c01..8ab57cce761a 100644 --- a/kernel/locking/spinlock_debug.c +++ b/kernel/locking/spinlock_debug.c @@ -66,6 +66,11 @@ static void spin_dump(raw_spinlock_t *lock, const char *msg) owner ? owner->comm : "", owner ? task_pid_nr(owner) : -1, READ_ONCE(lock->owner_cpu)); +#ifdef CONFIG_DEBUG_SPINLOCK_BITE_ON_BUG + msm_trigger_wdog_bite(); +#elif defined(CONFIG_DEBUG_SPINLOCK_PANIC_ON_BUG) + BUG(); +#endif dump_stack(); } diff --git a/kernel/power/Kconfig b/kernel/power/Kconfig index cf6b60b968f6..fac423faa397 100644 --- a/kernel/power/Kconfig +++ b/kernel/power/Kconfig @@ -340,12 +340,3 @@ config PM_GENERIC_DOMAINS_OF config CPU_PM bool - -config BOEFFLA_WL_BLOCKER - bool "Boeffla generic wakelock blocker driver" - depends on PM - default N -config BOEFFLA_WL_BLOCKER - bool "Boeffla generic wakelock blocker driver" - depends on PM - default N diff --git a/kernel/power/process.c b/kernel/power/process.c index da708d943328..9a12c835b6c2 100644 --- a/kernel/power/process.c +++ b/kernel/power/process.c @@ -193,26 +193,6 @@ int freeze_kernel_threads(void) return error; } -void thaw_fingerprintd(void) -{ - struct task_struct *p; - - pm_freezing = false; - pm_nosig_freezing = false; - - read_lock(&tasklist_lock); - for_each_process(p) { - if (!memcmp(p->comm, "fingerprintd", 13)) { - __thaw_task(p); - break; - } - } - read_unlock(&tasklist_lock); - - pm_freezing = true; - pm_nosig_freezing = true; -} - void thaw_processes(void) { struct task_struct *g, *p; diff --git a/kernel/power/suspend.c b/kernel/power/suspend.c index 37f04cf1a0df..2d0c99b3f34c 100644 --- a/kernel/power/suspend.c +++ b/kernel/power/suspend.c @@ -54,8 +54,6 @@ void freeze_set_ops(const struct platform_freeze_ops *ops) unlock_system_sleep(); } -extern void thaw_fingerprintd(void); - static void freeze_begin(void) { suspend_freeze_state = FREEZE_STATE_NONE; @@ -410,8 +408,6 @@ static int suspend_enter(suspend_state_t state, bool *wakeup) enable_nonboot_cpus(); Platform_wake: - thaw_fingerprintd(); - platform_resume_noirq(state); dpm_resume_noirq(PMSG_RESUME); diff --git a/kernel/sched/cpufreq_schedutil.c b/kernel/sched/cpufreq_schedutil.c index 13957aa8edcd..cfe4f40d5819 100644 --- a/kernel/sched/cpufreq_schedutil.c +++ b/kernel/sched/cpufreq_schedutil.c @@ -28,7 +28,6 @@ struct sugov_tunables { unsigned int hispeed_load; unsigned int hispeed_freq; bool pl; - bool iowait_boost_enable; }; struct sugov_policy { @@ -140,13 +139,7 @@ static void sugov_update_commit(struct sugov_policy *sg_policy, u64 time, if (sg_policy->next_freq == next_freq) return; - if (sugov_up_down_rate_limit(sg_policy, time, next_freq)) { - /* Don't cache a raw freq that didn't become next_freq */ - sg_policy->cached_raw_freq = 0; - return; - } - - if (sg_policy->next_freq == next_freq) + if (sugov_up_down_rate_limit(sg_policy, time, next_freq)) return; sg_policy->next_freq = next_freq; @@ -161,7 +154,7 @@ static void sugov_update_commit(struct sugov_policy *sg_policy, u64 time, trace_cpu_frequency(next_freq, smp_processor_id()); } else { sg_policy->work_in_progress = true; - irq_work_queue(&sg_policy->irq_work); + sched_irq_work_queue(&sg_policy->irq_work); } } @@ -221,11 +214,6 @@ static void sugov_get_util(unsigned long *util, unsigned long *max, int cpu) static void sugov_set_iowait_boost(struct sugov_cpu *sg_cpu, u64 time, unsigned int flags) { - struct sugov_policy *sg_policy = sg_cpu->sg_policy; - - if (!sg_policy->tunables->iowait_boost_enable) - return; - if (flags & SCHED_CPUFREQ_IOWAIT) { sg_cpu->iowait_boost = sg_cpu->iowait_boost_max; } else if (sg_cpu->iowait_boost) { @@ -331,8 +319,8 @@ static void sugov_walt_adjust(struct sugov_cpu *sg_cpu, unsigned long *util, if (is_hiload && nl >= mult_frac(cpu_util, NL_RATIO, 100)) *util = *max; - if (sg_policy->tunables->pl && sg_cpu->walt_load.pl > *util) - *util = (*util + sg_cpu->walt_load.pl) / 2; + if (sg_policy->tunables->pl) + *util = max(*util, sg_cpu->walt_load.pl); } #ifdef CONFIG_NO_HZ_COMMON @@ -373,8 +361,6 @@ static void sugov_update_single(struct update_util_data *hook, u64 time, raw_spin_lock(&sg_policy->update_lock); if (flags & SCHED_CPUFREQ_RT_DL) { - /* clear cache when it's bypassed */ - sg_policy->cached_raw_freq = 0; next_f = policy->cpuinfo.max_freq; } else { sugov_get_util(&util, &max, sg_cpu->cpu); @@ -402,11 +388,8 @@ static void sugov_update_single(struct update_util_data *hook, u64 time, * Do not reduce the frequency if the CPU has not been idle * recently, as the reduction is likely to be premature then. */ - if (busy && next_f < sg_policy->next_freq) { + if (busy && next_f < sg_policy->next_freq) next_f = sg_policy->next_freq; - /* clear cache when it's bypassed */ - sg_policy->cached_raw_freq = 0; - } } sugov_update_commit(sg_policy, time, next_f); @@ -437,11 +420,8 @@ static unsigned int sugov_next_freq_shared(struct sugov_cpu *sg_cpu, u64 time) j_sg_cpu->iowait_boost = 0; continue; } - if (j_sg_cpu->flags & SCHED_CPUFREQ_RT_DL) { - /* clear cache when it's bypassed */ - sg_policy->cached_raw_freq = 0; + if (j_sg_cpu->flags & SCHED_CPUFREQ_RT_DL) return policy->cpuinfo.max_freq; - } j_util = j_sg_cpu->util; j_max = j_sg_cpu->max; @@ -497,13 +477,10 @@ static void sugov_update_shared(struct update_util_data *hook, u64 time, sg_cpu->walt_load.pl, flags); if (sugov_should_update_freq(sg_policy, time)) { - if (flags & SCHED_CPUFREQ_RT_DL) { + if (flags & SCHED_CPUFREQ_RT_DL) next_f = sg_policy->policy->cpuinfo.max_freq; - /* clear cache when it's bypassed */ - sg_policy->cached_raw_freq = 0; - } else { + else next_f = sugov_next_freq_shared(sg_cpu, time); - } sugov_update_commit(sg_policy, time, next_f); } @@ -690,27 +667,6 @@ static ssize_t pl_store(struct gov_attr_set *attr_set, const char *buf, if (kstrtobool(buf, &tunables->pl)) return -EINVAL; - return count; -} - -static ssize_t iowait_boost_enable_show(struct gov_attr_set *attr_set, - char *buf) -{ - struct sugov_tunables *tunables = to_sugov_tunables(attr_set); - - return sprintf(buf, "%u\n", tunables->iowait_boost_enable); -} - -static ssize_t iowait_boost_enable_store(struct gov_attr_set *attr_set, - const char *buf, size_t count) -{ - struct sugov_tunables *tunables = to_sugov_tunables(attr_set); - bool enable; - - if (kstrtobool(buf, &enable)) - return -EINVAL; - - tunables->iowait_boost_enable = enable; return count; } @@ -720,7 +676,6 @@ static struct governor_attr down_rate_limit_us = __ATTR_RW(down_rate_limit_us); static struct governor_attr hispeed_load = __ATTR_RW(hispeed_load); static struct governor_attr hispeed_freq = __ATTR_RW(hispeed_freq); static struct governor_attr pl = __ATTR_RW(pl); -static struct governor_attr iowait_boost_enable = __ATTR_RW(iowait_boost_enable); static struct attribute *sugov_attributes[] = { &up_rate_limit_us.attr, @@ -728,7 +683,6 @@ static struct attribute *sugov_attributes[] = { &hispeed_load.attr, &hispeed_freq.attr, &pl.attr, - &iowait_boost_enable.attr, NULL }; @@ -923,8 +877,6 @@ static int sugov_init(struct cpufreq_policy *policy) tunables->hispeed_load = DEFAULT_HISPEED_LOAD; tunables->hispeed_freq = 0; - tunables->iowait_boost_enable = false; - policy->governor_data = sg_policy; sg_policy->tunables = tunables; stale_ns = sched_ravg_window + (sched_ravg_window >> 3); @@ -1074,5 +1026,4 @@ static int __init sugov_register(void) { return cpufreq_register_governor(&schedutil_gov); } -core_initcall(sugov_register); - +fs_initcall(sugov_register); diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c index d3c2a1f032b6..dc669e370ee5 100755 --- a/kernel/sched/fair.c +++ b/kernel/sched/fair.c @@ -3390,7 +3390,6 @@ update_cfs_rq_load_avg(u64 now, struct cfs_rq *cfs_rq, bool update_freq) */ #define UPDATE_TG 0x1 #define SKIP_AGE_LOAD 0x2 -#define SKIP_CPUFREQ 0x4 /* Update task and its cfs_rq load average */ static inline void update_load_avg(struct sched_entity *se, int flags) @@ -3412,7 +3411,7 @@ static inline void update_load_avg(struct sched_entity *se, int flags) cfs_rq->curr == se, NULL); } - decayed = update_cfs_rq_load_avg(now, cfs_rq, !(flags & SKIP_CPUFREQ)); + decayed = update_cfs_rq_load_avg(now, cfs_rq, true); decayed |= propagate_entity_load_avg(se); if (decayed && (flags & UPDATE_TG)) @@ -3570,7 +3569,6 @@ update_cfs_rq_load_avg(u64 now, struct cfs_rq *cfs_rq, bool update_freq) #define UPDATE_TG 0x0 #define SKIP_AGE_LOAD 0x0 -#define SKIP_CPUFREQ 0x0 static inline void update_load_avg(struct sched_entity *se, int not_used1) { @@ -3796,8 +3794,6 @@ static __always_inline void return_cfs_rq_runtime(struct cfs_rq *cfs_rq); static void dequeue_entity(struct cfs_rq *cfs_rq, struct sched_entity *se, int flags) { - int update_flags; - /* * Update run-time statistics of the 'current'. */ @@ -3811,12 +3807,7 @@ dequeue_entity(struct cfs_rq *cfs_rq, struct sched_entity *se, int flags) * - For group entity, update its weight to reflect the new share * of its group cfs_rq. */ - update_flags = UPDATE_TG; - - if (flags & DEQUEUE_IDLE) - update_flags |= SKIP_CPUFREQ; - - update_load_avg(se, update_flags); + update_load_avg(se, UPDATE_TG); dequeue_entity_load_avg(cfs_rq, se); update_stats_dequeue(cfs_rq, se, flags); @@ -5109,9 +5100,6 @@ static void dequeue_task_fair(struct rq *rq, struct task_struct *p, int flags) struct sched_entity *se = &p->se; int task_sleep = flags & DEQUEUE_SLEEP; - if (task_sleep && rq->nr_running == 1) - flags |= DEQUEUE_IDLE; - for_each_sched_entity(se) { cfs_rq = cfs_rq_of(se); dequeue_entity(cfs_rq, se, flags); @@ -5143,8 +5131,6 @@ static void dequeue_task_fair(struct rq *rq, struct task_struct *p, int flags) } for_each_sched_entity(se) { - int update_flags; - cfs_rq = cfs_rq_of(se); cfs_rq->h_nr_running--; walt_dec_cfs_rq_stats(cfs_rq, p); @@ -5152,12 +5138,7 @@ static void dequeue_task_fair(struct rq *rq, struct task_struct *p, int flags) if (cfs_rq_throttled(cfs_rq)) break; - update_flags = UPDATE_TG; - - if (flags & DEQUEUE_IDLE) - update_flags |= SKIP_CPUFREQ; - - update_load_avg(se, update_flags); + update_load_avg(se, UPDATE_TG); update_cfs_shares(se); } diff --git a/kernel/sched/sched.h b/kernel/sched/sched.h index 7f6d8ae020a1..4278cf6a459d 100755 --- a/kernel/sched/sched.h +++ b/kernel/sched/sched.h @@ -1491,7 +1491,6 @@ extern const u32 sched_prio_to_wmult[40]; #define DEQUEUE_SLEEP 0x01 #define DEQUEUE_SAVE 0x02 /* matches ENQUEUE_RESTORE */ #define DEQUEUE_MOVE 0x04 /* matches ENQUEUE_MOVE */ -#define DEQUEUE_IDLE 0x80 /* The last dequeue before IDLE */ #define ENQUEUE_WAKEUP 0x01 #define ENQUEUE_RESTORE 0x02 diff --git a/kernel/sched/tune.c b/kernel/sched/tune.c index 20893cdcb62d..92fcb9240a61 100644 --- a/kernel/sched/tune.c +++ b/kernel/sched/tune.c @@ -300,7 +300,7 @@ schedtune_accept_deltas(int nrg_delta, int cap_delta, * implementation especially for the computation of the per-CPU boost * value */ -#define BOOSTGROUPS_COUNT 6 +#define BOOSTGROUPS_COUNT 5 /* Array of configured boostgroups */ static struct schedtune *allocated_group[BOOSTGROUPS_COUNT] = { diff --git a/kernel/time/alarmtimer.c b/kernel/time/alarmtimer.c index 3684e061cbc7..1c2dc98ba63d 100644 --- a/kernel/time/alarmtimer.c +++ b/kernel/time/alarmtimer.c @@ -278,8 +278,10 @@ static int alarmtimer_suspend(struct device *dev) if (min.tv64 == 0) return 0; - if (ktime_to_ns(min) < NSEC_PER_SEC / 2) - __pm_wakeup_event(ws, MSEC_PER_SEC / 2); + if (ktime_to_ns(min) < 2 * NSEC_PER_SEC) { + __pm_wakeup_event(ws, 2 * MSEC_PER_SEC); + return -EBUSY; + } /* Setup an rtc timer to fire that far in the future */ rtc_timer_cancel(rtc, &rtctimer); diff --git a/kernel/time/ntp.c b/kernel/time/ntp.c index fce8ea4a5c94..4bdb59604526 100644 --- a/kernel/time/ntp.c +++ b/kernel/time/ntp.c @@ -559,7 +559,7 @@ static void sync_cmos_clock(struct work_struct *work) if (!fail || fail == -ENODEV) next.tv_sec = 659; else - next.tv_sec = 10; + next.tv_sec = 0; if (next.tv_nsec >= NSEC_PER_SEC) { next.tv_sec++; diff --git a/lib/decompress_unlz4.c b/lib/decompress_unlz4.c index 1b0baf3008ea..036fc882cd72 100644 --- a/lib/decompress_unlz4.c +++ b/lib/decompress_unlz4.c @@ -72,7 +72,7 @@ STATIC inline int INIT unlz4(u8 *input, long in_len, error("NULL input pointer and missing fill function"); goto exit_1; } else { - inp = large_malloc(LZ4_compressBound(uncomp_chunksize)); + inp = large_malloc(lz4_compressbound(uncomp_chunksize)); if (!inp) { error("Could not allocate input buffer"); goto exit_1; @@ -136,7 +136,7 @@ STATIC inline int INIT unlz4(u8 *input, long in_len, inp += 4; size -= 4; } else { - if (chunksize > LZ4_compressBound(uncomp_chunksize)) { + if (chunksize > lz4_compressbound(uncomp_chunksize)) { error("chunk length is longer than allocated"); goto exit_2; } @@ -152,14 +152,11 @@ STATIC inline int INIT unlz4(u8 *input, long in_len, out_len -= dest_len; } else dest_len = out_len; - - ret = LZ4_decompress_fast(inp, outp, dest_len); - chunksize = ret; + ret = lz4_decompress(inp, &chunksize, outp, dest_len); #else dest_len = uncomp_chunksize; - - ret = LZ4_decompress_safe(inp, outp, chunksize, dest_len); - dest_len = ret; + ret = lz4_decompress_unknownoutputsize(inp, chunksize, outp, + &dest_len); #endif if (ret < 0) { error("Decoding failed"); diff --git a/lib/lz4/Makefile b/lib/lz4/Makefile index f7b113271d13..8085d04e9309 100644 --- a/lib/lz4/Makefile +++ b/lib/lz4/Makefile @@ -1,5 +1,3 @@ -ccflags-y += -O3 - obj-$(CONFIG_LZ4_COMPRESS) += lz4_compress.o obj-$(CONFIG_LZ4HC_COMPRESS) += lz4hc_compress.o obj-$(CONFIG_LZ4_DECOMPRESS) += lz4_decompress.o diff --git a/lib/lz4/lz4_compress.c b/lib/lz4/lz4_compress.c index 668400bd38ee..28321d8f75ef 100644 --- a/lib/lz4/lz4_compress.c +++ b/lib/lz4/lz4_compress.c @@ -1,16 +1,19 @@ /* * LZ4 - Fast LZ compression algorithm - * Copyright (C) 2011 - 2016, Yann Collet. - * BSD 2 - Clause License (http://www.opensource.org/licenses/bsd - license.php) + * Copyright (C) 2011-2012, Yann Collet. + * BSD 2-Clause License (http://www.opensource.org/licenses/bsd-license.php) + * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following disclaimer * in the documentation and/or other materials provided with the * distribution. + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -22,939 +25,417 @@ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * * You can contact the author at : - * - LZ4 homepage : http://www.lz4.org - * - LZ4 source repository : https://github.com/lz4/lz4 + * - LZ4 homepage : http://fastcompression.blogspot.com/p/lz4.html + * - LZ4 source repository : http://code.google.com/p/lz4/ * - * Changed for kernel usage by: - * Sven Schmidt <4sschmid@informatik.uni-hamburg.de> + * Changed for kernel use by: + * Chanho Min */ -/*-************************************ - * Dependencies - **************************************/ -#include -#include "lz4defs.h" #include #include +#include #include - -static const int LZ4_minLength = (MFLIMIT + 1); -static const int LZ4_64Klimit = ((64 * KB) + (MFLIMIT - 1)); - -/*-****************************** - * Compression functions - ********************************/ -static FORCE_INLINE U32 LZ4_hash4( - U32 sequence, - tableType_t const tableType) -{ - if (tableType == byU16) - return ((sequence * 2654435761U) - >> ((MINMATCH * 8) - (LZ4_HASHLOG + 1))); - else - return ((sequence * 2654435761U) - >> ((MINMATCH * 8) - LZ4_HASHLOG)); -} - -static FORCE_INLINE U32 LZ4_hash5( - U64 sequence, - tableType_t const tableType) -{ - const U32 hashLog = (tableType == byU16) - ? LZ4_HASHLOG + 1 - : LZ4_HASHLOG; - -#if LZ4_LITTLE_ENDIAN - static const U64 prime5bytes = 889523592379ULL; - - return (U32)(((sequence << 24) * prime5bytes) >> (64 - hashLog)); -#else - static const U64 prime8bytes = 11400714785074694791ULL; - - return (U32)(((sequence >> 24) * prime8bytes) >> (64 - hashLog)); -#endif -} - -static FORCE_INLINE U32 LZ4_hashPosition( - const void *p, - tableType_t const tableType) -{ -#if LZ4_ARCH64 - if (tableType == byU32) - return LZ4_hash5(LZ4_read_ARCH(p), tableType); -#endif - - return LZ4_hash4(LZ4_read32(p), tableType); -} - -static void LZ4_putPositionOnHash( - const BYTE *p, - U32 h, - void *tableBase, - tableType_t const tableType, - const BYTE *srcBase) -{ - switch (tableType) { - case byPtr: - { - const BYTE **hashTable = (const BYTE **)tableBase; - - hashTable[h] = p; - return; - } - case byU32: - { - U32 *hashTable = (U32 *) tableBase; - - hashTable[h] = (U32)(p - srcBase); - return; - } - case byU16: - { - U16 *hashTable = (U16 *) tableBase; - - hashTable[h] = (U16)(p - srcBase); - return; - } - } -} - -static FORCE_INLINE void LZ4_putPosition( - const BYTE *p, - void *tableBase, - tableType_t tableType, - const BYTE *srcBase) -{ - U32 const h = LZ4_hashPosition(p, tableType); - - LZ4_putPositionOnHash(p, h, tableBase, tableType, srcBase); -} - -static const BYTE *LZ4_getPositionOnHash( - U32 h, - void *tableBase, - tableType_t tableType, - const BYTE *srcBase) -{ - if (tableType == byPtr) { - const BYTE **hashTable = (const BYTE **) tableBase; - - return hashTable[h]; - } - - if (tableType == byU32) { - const U32 * const hashTable = (U32 *) tableBase; - - return hashTable[h] + srcBase; - } - - { - /* default, to ensure a return */ - const U16 * const hashTable = (U16 *) tableBase; - - return hashTable[h] + srcBase; - } -} - -static FORCE_INLINE const BYTE *LZ4_getPosition( - const BYTE *p, - void *tableBase, - tableType_t tableType, - const BYTE *srcBase) -{ - U32 const h = LZ4_hashPosition(p, tableType); - - return LZ4_getPositionOnHash(h, tableBase, tableType, srcBase); -} - +#include "lz4defs.h" /* - * LZ4_compress_generic() : - * inlined, to ensure branches are decided at compilation time + * LZ4_compressCtx : + * ----------------- + * Compress 'isize' bytes from 'source' into an output buffer 'dest' of + * maximum size 'maxOutputSize'. * If it cannot achieve it, compression + * will stop, and result of the function will be zero. + * return : the number of bytes written in buffer 'dest', or 0 if the + * compression fails */ -static FORCE_INLINE int LZ4_compress_generic( - LZ4_stream_t_internal * const dictPtr, - const char * const source, - char * const dest, - const int inputSize, - const int maxOutputSize, - const limitedOutput_directive outputLimited, - const tableType_t tableType, - const dict_directive dict, - const dictIssue_directive dictIssue, - const U32 acceleration) +static inline int lz4_compressctx(void *ctx, + const char *source, + char *dest, + int isize, + int maxoutputsize) { - const BYTE *ip = (const BYTE *) source; - const BYTE *base; - const BYTE *lowLimit; - const BYTE * const lowRefLimit = ip - dictPtr->dictSize; - const BYTE * const dictionary = dictPtr->dictionary; - const BYTE * const dictEnd = dictionary + dictPtr->dictSize; - const size_t dictDelta = dictEnd - (const BYTE *)source; - const BYTE *anchor = (const BYTE *) source; - const BYTE * const iend = ip + inputSize; - const BYTE * const mflimit = iend - MFLIMIT; - const BYTE * const matchlimit = iend - LASTLITERALS; - - BYTE *op = (BYTE *) dest; - BYTE * const olimit = op + maxOutputSize; - - U32 forwardH; - size_t refDelta = 0; - - /* Init conditions */ - if ((U32)inputSize > (U32)LZ4_MAX_INPUT_SIZE) { - /* Unsupported inputSize, too large (or negative) */ - return 0; - } - - switch (dict) { - case noDict: - default: - base = (const BYTE *)source; - lowLimit = (const BYTE *)source; - break; - case withPrefix64k: - base = (const BYTE *)source - dictPtr->currentOffset; - lowLimit = (const BYTE *)source - dictPtr->dictSize; - break; - case usingExtDict: - base = (const BYTE *)source - dictPtr->currentOffset; - lowLimit = (const BYTE *)source; - break; - } - - if ((tableType == byU16) - && (inputSize >= LZ4_64Klimit)) { - /* Size too large (not within 64K limit) */ - return 0; - } - - if (inputSize < LZ4_minLength) { - /* Input too small, no compression (all literals) */ + HTYPE *hashtable = (HTYPE *)ctx; + const u8 *ip = (u8 *)source; +#if LZ4_ARCH64 + const BYTE * const base = ip; +#else + const int base = 0; +#endif + const u8 *anchor = ip; + const u8 *const iend = ip + isize; + const u8 *const mflimit = iend - MFLIMIT; + #define MATCHLIMIT (iend - LASTLITERALS) + + u8 *op = (u8 *) dest; + u8 *const oend = op + maxoutputsize; + int length; + const int skipstrength = SKIPSTRENGTH; + u32 forwardh; + int lastrun; + + /* Init */ + if (isize < MINLENGTH) goto _last_literals; - } + + memset((void *)hashtable, 0, LZ4_MEM_COMPRESS); /* First Byte */ - LZ4_putPosition(ip, dictPtr->hashTable, tableType, base); + hashtable[LZ4_HASH_VALUE(ip)] = ip - base; ip++; - forwardH = LZ4_hashPosition(ip, tableType); + forwardh = LZ4_HASH_VALUE(ip); /* Main Loop */ - for ( ; ; ) { - const BYTE *match; - BYTE *token; + for (;;) { + int findmatchattempts = (1U << skipstrength) + 3; + const u8 *forwardip = ip; + const u8 *ref; + u8 *token; /* Find a match */ - { - const BYTE *forwardIp = ip; - unsigned int step = 1; - unsigned int searchMatchNb = acceleration << LZ4_SKIPTRIGGER; - - do { - U32 const h = forwardH; - - ip = forwardIp; - forwardIp += step; - step = (searchMatchNb++ >> LZ4_SKIPTRIGGER); - - if (unlikely(forwardIp > mflimit)) - goto _last_literals; - - match = LZ4_getPositionOnHash(h, - dictPtr->hashTable, - tableType, base); - - if (dict == usingExtDict) { - if (match < (const BYTE *)source) { - refDelta = dictDelta; - lowLimit = dictionary; - } else { - refDelta = 0; - lowLimit = (const BYTE *)source; - } } - - forwardH = LZ4_hashPosition(forwardIp, - tableType); - - LZ4_putPositionOnHash(ip, h, dictPtr->hashTable, - tableType, base); - } while (((dictIssue == dictSmall) - ? (match < lowRefLimit) - : 0) - || ((tableType == byU16) - ? 0 - : (match + MAX_DISTANCE < ip)) - || (LZ4_read32(match + refDelta) - != LZ4_read32(ip))); - } + do { + u32 h = forwardh; + int step = findmatchattempts++ >> skipstrength; + ip = forwardip; + forwardip = ip + step; + + if (unlikely(forwardip > mflimit)) + goto _last_literals; + + forwardh = LZ4_HASH_VALUE(forwardip); + ref = base + hashtable[h]; + hashtable[h] = ip - base; + } while ((ref < ip - MAX_DISTANCE) || (A32(ref) != A32(ip))); /* Catch up */ - while (((ip > anchor) & (match + refDelta > lowLimit)) - && (unlikely(ip[-1] == match[refDelta - 1]))) { + while ((ip > anchor) && (ref > (u8 *)source) && + unlikely(ip[-1] == ref[-1])) { ip--; - match--; + ref--; } - /* Encode Literals */ - { - unsigned const int litLength = (unsigned int)(ip - anchor); - - token = op++; - - if ((outputLimited) && - /* Check output buffer overflow */ - (unlikely(op + litLength + - (2 + 1 + LASTLITERALS) + - (litLength / 255) > olimit))) - return 0; - - if (litLength >= RUN_MASK) { - int len = (int)litLength - RUN_MASK; - - *token = (RUN_MASK << ML_BITS); - - for (; len >= 255; len -= 255) - *op++ = 255; - *op++ = (BYTE)len; - } else - *token = (BYTE)(litLength << ML_BITS); + /* Encode Literal length */ + length = (int)(ip - anchor); + token = op++; + /* check output limit */ + if (unlikely(op + length + (2 + 1 + LASTLITERALS) + + (length >> 8) > oend)) + return 0; - /* Copy Literals */ - LZ4_wildCopy(op, anchor, op + litLength); - op += litLength; - } + if (length >= (int)RUN_MASK) { + int len; + *token = (RUN_MASK << ML_BITS); + len = length - RUN_MASK; + for (; len > 254 ; len -= 255) + *op++ = 255; + *op++ = (u8)len; + } else + *token = (length << ML_BITS); + /* Copy Literals */ + LZ4_BLINDCOPY(anchor, op, length); _next_match: /* Encode Offset */ - LZ4_writeLE16(op, (U16)(ip - match)); - op += 2; - - /* Encode MatchLength */ - { - unsigned int matchCode; + LZ4_WRITE_LITTLEENDIAN_16(op, (u16)(ip - ref)); - if ((dict == usingExtDict) - && (lowLimit == dictionary)) { - const BYTE *limit; - - match += refDelta; - limit = ip + (dictEnd - match); - - if (limit > matchlimit) - limit = matchlimit; - - matchCode = LZ4_count(ip + MINMATCH, - match + MINMATCH, limit); - - ip += MINMATCH + matchCode; - - if (ip == limit) { - unsigned const int more = LZ4_count(ip, - (const BYTE *)source, - matchlimit); - - matchCode += more; - ip += more; - } - } else { - matchCode = LZ4_count(ip + MINMATCH, - match + MINMATCH, matchlimit); - ip += MINMATCH + matchCode; + /* Start Counting */ + ip += MINMATCH; + /* MinMatch verified */ + ref += MINMATCH; + anchor = ip; + while (likely(ip < MATCHLIMIT - (STEPSIZE - 1))) { + #if LZ4_ARCH64 + u64 diff = A64(ref) ^ A64(ip); + #else + u32 diff = A32(ref) ^ A32(ip); + #endif + if (!diff) { + ip += STEPSIZE; + ref += STEPSIZE; + continue; } - - if (outputLimited && - /* Check output buffer overflow */ - (unlikely(op + - (1 + LASTLITERALS) + - (matchCode >> 8) > olimit))) - return 0; - - if (matchCode >= ML_MASK) { - *token += ML_MASK; - matchCode -= ML_MASK; - LZ4_write32(op, 0xFFFFFFFF); - - while (matchCode >= 4 * 255) { - op += 4; - LZ4_write32(op, 0xFFFFFFFF); - matchCode -= 4 * 255; - } - - op += matchCode / 255; - *op++ = (BYTE)(matchCode % 255); - } else - *token += (BYTE)(matchCode); + ip += LZ4_NBCOMMONBYTES(diff); + goto _endcount; } - - anchor = ip; + #if LZ4_ARCH64 + if ((ip < (MATCHLIMIT - 3)) && (A32(ref) == A32(ip))) { + ip += 4; + ref += 4; + } + #endif + if ((ip < (MATCHLIMIT - 1)) && (A16(ref) == A16(ip))) { + ip += 2; + ref += 2; + } + if ((ip < MATCHLIMIT) && (*ref == *ip)) + ip++; +_endcount: + /* Encode MatchLength */ + length = (int)(ip - anchor); + /* Check output limit */ + if (unlikely(op + (1 + LASTLITERALS) + (length >> 8) > oend)) + return 0; + if (length >= (int)ML_MASK) { + *token += ML_MASK; + length -= ML_MASK; + for (; length > 509 ; length -= 510) { + *op++ = 255; + *op++ = 255; + } + if (length > 254) { + length -= 255; + *op++ = 255; + } + *op++ = (u8)length; + } else + *token += length; /* Test end of chunk */ - if (ip > mflimit) + if (ip > mflimit) { + anchor = ip; break; + } /* Fill table */ - LZ4_putPosition(ip - 2, dictPtr->hashTable, tableType, base); + hashtable[LZ4_HASH_VALUE(ip-2)] = ip - 2 - base; /* Test next position */ - match = LZ4_getPosition(ip, dictPtr->hashTable, - tableType, base); - - if (dict == usingExtDict) { - if (match < (const BYTE *)source) { - refDelta = dictDelta; - lowLimit = dictionary; - } else { - refDelta = 0; - lowLimit = (const BYTE *)source; - } - } - - LZ4_putPosition(ip, dictPtr->hashTable, tableType, base); - - if (((dictIssue == dictSmall) ? (match >= lowRefLimit) : 1) - && (match + MAX_DISTANCE >= ip) - && (LZ4_read32(match + refDelta) == LZ4_read32(ip))) { + ref = base + hashtable[LZ4_HASH_VALUE(ip)]; + hashtable[LZ4_HASH_VALUE(ip)] = ip - base; + if ((ref > ip - (MAX_DISTANCE + 1)) && (A32(ref) == A32(ip))) { token = op++; *token = 0; goto _next_match; } /* Prepare next loop */ - forwardH = LZ4_hashPosition(++ip, tableType); + anchor = ip++; + forwardh = LZ4_HASH_VALUE(ip); } _last_literals: /* Encode Last Literals */ - { - size_t const lastRun = (size_t)(iend - anchor); - - if ((outputLimited) && - /* Check output buffer overflow */ - ((op - (BYTE *)dest) + lastRun + 1 + - ((lastRun + 255 - RUN_MASK) / 255) > (U32)maxOutputSize)) - return 0; - - if (lastRun >= RUN_MASK) { - size_t accumulator = lastRun - RUN_MASK; - *op++ = RUN_MASK << ML_BITS; - for (; accumulator >= 255; accumulator -= 255) - *op++ = 255; - *op++ = (BYTE) accumulator; - } else { - *op++ = (BYTE)(lastRun << ML_BITS); - } - - memcpy(op, anchor, lastRun); + lastrun = (int)(iend - anchor); + if (((char *)op - dest) + lastrun + 1 + + ((lastrun + 255 - RUN_MASK) / 255) > (u32)maxoutputsize) + return 0; - op += lastRun; - } + if (lastrun >= (int)RUN_MASK) { + *op++ = (RUN_MASK << ML_BITS); + lastrun -= RUN_MASK; + for (; lastrun > 254 ; lastrun -= 255) + *op++ = 255; + *op++ = (u8)lastrun; + } else + *op++ = (lastrun << ML_BITS); + memcpy(op, anchor, iend - anchor); + op += iend - anchor; /* End */ - return (int) (((char *)op) - dest); -} - -static int LZ4_compress_fast_extState( - void *state, - const char *source, - char *dest, - int inputSize, - int maxOutputSize, - int acceleration) -{ - LZ4_stream_t_internal *ctx = &((LZ4_stream_t *)state)->internal_donotuse; -#if LZ4_ARCH64 - const tableType_t tableType = byU32; -#else - const tableType_t tableType = byPtr; -#endif - - LZ4_resetStream((LZ4_stream_t *)state); - - if (acceleration < 1) - acceleration = LZ4_ACCELERATION_DEFAULT; - - if (maxOutputSize >= LZ4_COMPRESSBOUND(inputSize)) { - if (inputSize < LZ4_64Klimit) - return LZ4_compress_generic(ctx, source, - dest, inputSize, 0, - noLimit, byU16, noDict, - noDictIssue, acceleration); - else - return LZ4_compress_generic(ctx, source, - dest, inputSize, 0, - noLimit, tableType, noDict, - noDictIssue, acceleration); - } else { - if (inputSize < LZ4_64Klimit) - return LZ4_compress_generic(ctx, source, - dest, inputSize, - maxOutputSize, limitedOutput, byU16, noDict, - noDictIssue, acceleration); - else - return LZ4_compress_generic(ctx, source, - dest, inputSize, - maxOutputSize, limitedOutput, tableType, noDict, - noDictIssue, acceleration); - } -} - -int LZ4_compress_fast(const char *source, char *dest, int inputSize, - int maxOutputSize, int acceleration, void *wrkmem) -{ - return LZ4_compress_fast_extState(wrkmem, source, dest, inputSize, - maxOutputSize, acceleration); + return (int)(((char *)op) - dest); } -EXPORT_SYMBOL(LZ4_compress_fast); -int LZ4_compress_default(const char *source, char *dest, int inputSize, - int maxOutputSize, void *wrkmem) +static inline int lz4_compress64kctx(void *ctx, + const char *source, + char *dest, + int isize, + int maxoutputsize) { - return LZ4_compress_fast(source, dest, inputSize, - maxOutputSize, LZ4_ACCELERATION_DEFAULT, wrkmem); -} -EXPORT_SYMBOL(LZ4_compress_default); - -/*-****************************** - * *_destSize() variant - ********************************/ -static int LZ4_compress_destSize_generic( - LZ4_stream_t_internal * const ctx, - const char * const src, - char * const dst, - int * const srcSizePtr, - const int targetDstSize, - const tableType_t tableType) -{ - const BYTE *ip = (const BYTE *) src; - const BYTE *base = (const BYTE *) src; - const BYTE *lowLimit = (const BYTE *) src; - const BYTE *anchor = ip; - const BYTE * const iend = ip + *srcSizePtr; - const BYTE * const mflimit = iend - MFLIMIT; - const BYTE * const matchlimit = iend - LASTLITERALS; - - BYTE *op = (BYTE *) dst; - BYTE * const oend = op + targetDstSize; - BYTE * const oMaxLit = op + targetDstSize - 2 /* offset */ - - 8 /* because 8 + MINMATCH == MFLIMIT */ - 1 /* token */; - BYTE * const oMaxMatch = op + targetDstSize - - (LASTLITERALS + 1 /* token */); - BYTE * const oMaxSeq = oMaxLit - 1 /* token */; - - U32 forwardH; - - /* Init conditions */ - /* Impossible to store anything */ - if (targetDstSize < 1) - return 0; - /* Unsupported input size, too large (or negative) */ - if ((U32)*srcSizePtr > (U32)LZ4_MAX_INPUT_SIZE) - return 0; - /* Size too large (not within 64K limit) */ - if ((tableType == byU16) && (*srcSizePtr >= LZ4_64Klimit)) - return 0; - /* Input too small, no compression (all literals) */ - if (*srcSizePtr < LZ4_minLength) + u16 *hashtable = (u16 *)ctx; + const u8 *ip = (u8 *) source; + const u8 *anchor = ip; + const u8 *const base = ip; + const u8 *const iend = ip + isize; + const u8 *const mflimit = iend - MFLIMIT; + #define MATCHLIMIT (iend - LASTLITERALS) + + u8 *op = (u8 *) dest; + u8 *const oend = op + maxoutputsize; + int len, length; + const int skipstrength = SKIPSTRENGTH; + u32 forwardh; + int lastrun; + + /* Init */ + if (isize < MINLENGTH) goto _last_literals; + memset((void *)hashtable, 0, LZ4_MEM_COMPRESS); + /* First Byte */ - *srcSizePtr = 0; - LZ4_putPosition(ip, ctx->hashTable, tableType, base); - ip++; forwardH = LZ4_hashPosition(ip, tableType); + ip++; + forwardh = LZ4_HASH64K_VALUE(ip); /* Main Loop */ - for ( ; ; ) { - const BYTE *match; - BYTE *token; + for (;;) { + int findmatchattempts = (1U << skipstrength) + 3; + const u8 *forwardip = ip; + const u8 *ref; + u8 *token; /* Find a match */ - { - const BYTE *forwardIp = ip; - unsigned int step = 1; - unsigned int searchMatchNb = 1 << LZ4_SKIPTRIGGER; - - do { - U32 h = forwardH; - - ip = forwardIp; - forwardIp += step; - step = (searchMatchNb++ >> LZ4_SKIPTRIGGER); - - if (unlikely(forwardIp > mflimit)) - goto _last_literals; - - match = LZ4_getPositionOnHash(h, ctx->hashTable, - tableType, base); - forwardH = LZ4_hashPosition(forwardIp, - tableType); - LZ4_putPositionOnHash(ip, h, - ctx->hashTable, tableType, - base); - - } while (((tableType == byU16) - ? 0 - : (match + MAX_DISTANCE < ip)) - || (LZ4_read32(match) != LZ4_read32(ip))); - } + do { + u32 h = forwardh; + int step = findmatchattempts++ >> skipstrength; + ip = forwardip; + forwardip = ip + step; + + if (forwardip > mflimit) + goto _last_literals; + + forwardh = LZ4_HASH64K_VALUE(forwardip); + ref = base + hashtable[h]; + hashtable[h] = (u16)(ip - base); + } while (A32(ref) != A32(ip)); /* Catch up */ - while ((ip > anchor) - && (match > lowLimit) - && (unlikely(ip[-1] == match[-1]))) { + while ((ip > anchor) && (ref > (u8 *)source) + && (ip[-1] == ref[-1])) { ip--; - match--; + ref--; } /* Encode Literal length */ - { - unsigned int litLength = (unsigned int)(ip - anchor); + length = (int)(ip - anchor); + token = op++; + /* Check output limit */ + if (unlikely(op + length + (2 + 1 + LASTLITERALS) + + (length >> 8) > oend)) + return 0; + if (length >= (int)RUN_MASK) { + *token = (RUN_MASK << ML_BITS); + len = length - RUN_MASK; + for (; len > 254 ; len -= 255) + *op++ = 255; + *op++ = (u8)len; + } else + *token = (length << ML_BITS); - token = op++; - if (op + ((litLength + 240) / 255) - + litLength > oMaxLit) { - /* Not enough space for a last match */ - op--; - goto _last_literals; - } - if (litLength >= RUN_MASK) { - unsigned int len = litLength - RUN_MASK; - *token = (RUN_MASK<= 255; len -= 255) - *op++ = 255; - *op++ = (BYTE)len; - } else - *token = (BYTE)(litLength << ML_BITS); - - /* Copy Literals */ - LZ4_wildCopy(op, anchor, op + litLength); - op += litLength; - } + /* Copy Literals */ + LZ4_BLINDCOPY(anchor, op, length); _next_match: /* Encode Offset */ - LZ4_writeLE16(op, (U16)(ip - match)); op += 2; + LZ4_WRITE_LITTLEENDIAN_16(op, (u16)(ip - ref)); - /* Encode MatchLength */ - { - size_t matchLength = LZ4_count(ip + MINMATCH, - match + MINMATCH, matchlimit); + /* Start Counting */ + ip += MINMATCH; + /* MinMatch verified */ + ref += MINMATCH; + anchor = ip; - if (op + ((matchLength + 240)/255) > oMaxMatch) { - /* Match description too long : reduce it */ - matchLength = (15 - 1) + (oMaxMatch - op) * 255; + while (ip < MATCHLIMIT - (STEPSIZE - 1)) { + #if LZ4_ARCH64 + u64 diff = A64(ref) ^ A64(ip); + #else + u32 diff = A32(ref) ^ A32(ip); + #endif + + if (!diff) { + ip += STEPSIZE; + ref += STEPSIZE; + continue; } - ip += MINMATCH + matchLength; - - if (matchLength >= ML_MASK) { - *token += ML_MASK; - matchLength -= ML_MASK; - while (matchLength >= 255) { - matchLength -= 255; - *op++ = 255; - } - *op++ = (BYTE)matchLength; - } else - *token += (BYTE)(matchLength); + ip += LZ4_NBCOMMONBYTES(diff); + goto _endcount; + } + #if LZ4_ARCH64 + if ((ip < (MATCHLIMIT - 3)) && (A32(ref) == A32(ip))) { + ip += 4; + ref += 4; + } + #endif + if ((ip < (MATCHLIMIT - 1)) && (A16(ref) == A16(ip))) { + ip += 2; + ref += 2; } + if ((ip < MATCHLIMIT) && (*ref == *ip)) + ip++; +_endcount: - anchor = ip; + /* Encode MatchLength */ + len = (int)(ip - anchor); + /* Check output limit */ + if (unlikely(op + (1 + LASTLITERALS) + (len >> 8) > oend)) + return 0; + if (len >= (int)ML_MASK) { + *token += ML_MASK; + len -= ML_MASK; + for (; len > 509 ; len -= 510) { + *op++ = 255; + *op++ = 255; + } + if (len > 254) { + len -= 255; + *op++ = 255; + } + *op++ = (u8)len; + } else + *token += len; - /* Test end of block */ - if (ip > mflimit) - break; - if (op > oMaxSeq) + /* Test end of chunk */ + if (ip > mflimit) { + anchor = ip; break; + } /* Fill table */ - LZ4_putPosition(ip - 2, ctx->hashTable, tableType, base); + hashtable[LZ4_HASH64K_VALUE(ip-2)] = (u16)(ip - 2 - base); /* Test next position */ - match = LZ4_getPosition(ip, ctx->hashTable, tableType, base); - LZ4_putPosition(ip, ctx->hashTable, tableType, base); - - if ((match + MAX_DISTANCE >= ip) - && (LZ4_read32(match) == LZ4_read32(ip))) { - token = op++; *token = 0; + ref = base + hashtable[LZ4_HASH64K_VALUE(ip)]; + hashtable[LZ4_HASH64K_VALUE(ip)] = (u16)(ip - base); + if (A32(ref) == A32(ip)) { + token = op++; + *token = 0; goto _next_match; } /* Prepare next loop */ - forwardH = LZ4_hashPosition(++ip, tableType); + anchor = ip++; + forwardh = LZ4_HASH64K_VALUE(ip); } _last_literals: /* Encode Last Literals */ - { - size_t lastRunSize = (size_t)(iend - anchor); - - if (op + 1 /* token */ - + ((lastRunSize + 240) / 255) /* litLength */ - + lastRunSize /* literals */ > oend) { - /* adapt lastRunSize to fill 'dst' */ - lastRunSize = (oend - op) - 1; - lastRunSize -= (lastRunSize + 240) / 255; - } - ip = anchor + lastRunSize; - - if (lastRunSize >= RUN_MASK) { - size_t accumulator = lastRunSize - RUN_MASK; - - *op++ = RUN_MASK << ML_BITS; - for (; accumulator >= 255; accumulator -= 255) - *op++ = 255; - *op++ = (BYTE) accumulator; - } else { - *op++ = (BYTE)(lastRunSize<= LZ4_COMPRESSBOUND(*srcSizePtr)) { - /* compression success is guaranteed */ - return LZ4_compress_fast_extState( - state, src, dst, *srcSizePtr, - targetDstSize, 1); - } else { - if (*srcSizePtr < LZ4_64Klimit) - return LZ4_compress_destSize_generic( - &state->internal_donotuse, - src, dst, srcSizePtr, - targetDstSize, byU16); - else - return LZ4_compress_destSize_generic( - &state->internal_donotuse, - src, dst, srcSizePtr, - targetDstSize, tableType); - } -} - - -int LZ4_compress_destSize( - const char *src, - char *dst, - int *srcSizePtr, - int targetDstSize, - void *wrkmem) -{ - return LZ4_compress_destSize_extState(wrkmem, src, dst, srcSizePtr, - targetDstSize); -} -EXPORT_SYMBOL(LZ4_compress_destSize); - -/*-****************************** - * Streaming functions - ********************************/ -void LZ4_resetStream(LZ4_stream_t *LZ4_stream) -{ - memset(LZ4_stream, 0, sizeof(LZ4_stream_t)); -} - -int LZ4_loadDict(LZ4_stream_t *LZ4_dict, - const char *dictionary, int dictSize) -{ - LZ4_stream_t_internal *dict = &LZ4_dict->internal_donotuse; - const BYTE *p = (const BYTE *)dictionary; - const BYTE * const dictEnd = p + dictSize; - const BYTE *base; - - if ((dict->initCheck) - || (dict->currentOffset > 1 * GB)) { - /* Uninitialized structure, or reuse overflow */ - LZ4_resetStream(LZ4_dict); - } - - if (dictSize < (int)HASH_UNIT) { - dict->dictionary = NULL; - dict->dictSize = 0; + lastrun = (int)(iend - anchor); + if (op + lastrun + 1 + (lastrun - RUN_MASK + 255) / 255 > oend) return 0; - } - - if ((dictEnd - p) > 64 * KB) - p = dictEnd - 64 * KB; - dict->currentOffset += 64 * KB; - base = p - dict->currentOffset; - dict->dictionary = p; - dict->dictSize = (U32)(dictEnd - p); - dict->currentOffset += dict->dictSize; - - while (p <= dictEnd - HASH_UNIT) { - LZ4_putPosition(p, dict->hashTable, byU32, base); - p += 3; - } - - return dict->dictSize; -} -EXPORT_SYMBOL(LZ4_loadDict); - -static void LZ4_renormDictT(LZ4_stream_t_internal *LZ4_dict, - const BYTE *src) -{ - if ((LZ4_dict->currentOffset > 0x80000000) || - ((uptrval)LZ4_dict->currentOffset > (uptrval)src)) { - /* address space overflow */ - /* rescale hash table */ - U32 const delta = LZ4_dict->currentOffset - 64 * KB; - const BYTE *dictEnd = LZ4_dict->dictionary + LZ4_dict->dictSize; - int i; - - for (i = 0; i < LZ4_HASH_SIZE_U32; i++) { - if (LZ4_dict->hashTable[i] < delta) - LZ4_dict->hashTable[i] = 0; - else - LZ4_dict->hashTable[i] -= delta; - } - LZ4_dict->currentOffset = 64 * KB; - if (LZ4_dict->dictSize > 64 * KB) - LZ4_dict->dictSize = 64 * KB; - LZ4_dict->dictionary = dictEnd - LZ4_dict->dictSize; - } -} - -int LZ4_saveDict(LZ4_stream_t *LZ4_dict, char *safeBuffer, int dictSize) -{ - LZ4_stream_t_internal * const dict = &LZ4_dict->internal_donotuse; - const BYTE * const previousDictEnd = dict->dictionary + dict->dictSize; - - if ((U32)dictSize > 64 * KB) { - /* useless to define a dictionary > 64 * KB */ - dictSize = 64 * KB; - } - if ((U32)dictSize > dict->dictSize) - dictSize = dict->dictSize; - - memmove(safeBuffer, previousDictEnd - dictSize, dictSize); - - dict->dictionary = (const BYTE *)safeBuffer; - dict->dictSize = (U32)dictSize; - - return dictSize; + if (lastrun >= (int)RUN_MASK) { + *op++ = (RUN_MASK << ML_BITS); + lastrun -= RUN_MASK; + for (; lastrun > 254 ; lastrun -= 255) + *op++ = 255; + *op++ = (u8)lastrun; + } else + *op++ = (lastrun << ML_BITS); + memcpy(op, anchor, iend - anchor); + op += iend - anchor; + /* End */ + return (int)(((char *)op) - dest); } -EXPORT_SYMBOL(LZ4_saveDict); -int LZ4_compress_fast_continue(LZ4_stream_t *LZ4_stream, const char *source, - char *dest, int inputSize, int maxOutputSize, int acceleration) +int lz4_compress(const unsigned char *src, size_t src_len, + unsigned char *dst, size_t *dst_len, void *wrkmem) { - LZ4_stream_t_internal *streamPtr = &LZ4_stream->internal_donotuse; - const BYTE * const dictEnd = streamPtr->dictionary - + streamPtr->dictSize; - - const BYTE *smallest = (const BYTE *) source; - - if (streamPtr->initCheck) { - /* Uninitialized structure detected */ - return 0; - } - - if ((streamPtr->dictSize > 0) && (smallest > dictEnd)) - smallest = dictEnd; - - LZ4_renormDictT(streamPtr, smallest); - - if (acceleration < 1) - acceleration = LZ4_ACCELERATION_DEFAULT; + int ret = -1; + int out_len = 0; - /* Check overlapping input/dictionary space */ - { - const BYTE *sourceEnd = (const BYTE *) source + inputSize; + if (src_len < LZ4_64KLIMIT) + out_len = lz4_compress64kctx(wrkmem, src, dst, src_len, + lz4_compressbound(src_len)); + else + out_len = lz4_compressctx(wrkmem, src, dst, src_len, + lz4_compressbound(src_len)); - if ((sourceEnd > streamPtr->dictionary) - && (sourceEnd < dictEnd)) { - streamPtr->dictSize = (U32)(dictEnd - sourceEnd); - if (streamPtr->dictSize > 64 * KB) - streamPtr->dictSize = 64 * KB; - if (streamPtr->dictSize < 4) - streamPtr->dictSize = 0; - streamPtr->dictionary = dictEnd - streamPtr->dictSize; - } - } + if (out_len < 0) + goto exit; - /* prefix mode : source data follows dictionary */ - if (dictEnd == (const BYTE *)source) { - int result; - - if ((streamPtr->dictSize < 64 * KB) && - (streamPtr->dictSize < streamPtr->currentOffset)) { - result = LZ4_compress_generic( - streamPtr, source, dest, inputSize, - maxOutputSize, limitedOutput, byU32, - withPrefix64k, dictSmall, acceleration); - } else { - result = LZ4_compress_generic( - streamPtr, source, dest, inputSize, - maxOutputSize, limitedOutput, byU32, - withPrefix64k, noDictIssue, acceleration); - } - streamPtr->dictSize += (U32)inputSize; - streamPtr->currentOffset += (U32)inputSize; - return result; - } + *dst_len = out_len; - /* external dictionary mode */ - { - int result; - - if ((streamPtr->dictSize < 64 * KB) && - (streamPtr->dictSize < streamPtr->currentOffset)) { - result = LZ4_compress_generic( - streamPtr, source, dest, inputSize, - maxOutputSize, limitedOutput, byU32, - usingExtDict, dictSmall, acceleration); - } else { - result = LZ4_compress_generic( - streamPtr, source, dest, inputSize, - maxOutputSize, limitedOutput, byU32, - usingExtDict, noDictIssue, acceleration); - } - streamPtr->dictionary = (const BYTE *)source; - streamPtr->dictSize = (U32)inputSize; - streamPtr->currentOffset += (U32)inputSize; - return result; - } -} -EXPORT_SYMBOL(LZ4_compress_fast_continue); - -/*-****************************** - * For backwards compatibility - ********************************/ -int lz4_compress(const unsigned char *src, size_t src_len, unsigned char *dst, - size_t *dst_len, void *wrkmem) { - *dst_len = LZ4_compress_default(src, dst, src_len, - LZ4_COMPRESSBOUND(src_len), wrkmem); - - /* - * Prior lz4_compress will return -1 in case of error - * and 0 on success - * while new LZ4_compress_fast/default - * returns 0 in case of error - * and the output length on success - */ - if (!*dst_len) - return -1; - else - return 0; + return 0; +exit: + return ret; } EXPORT_SYMBOL(lz4_compress); diff --git a/lib/lz4/lz4_decompress.c b/lib/lz4/lz4_decompress.c index b5e00a19a7b4..6d940c72b5fc 100644 --- a/lib/lz4/lz4_decompress.c +++ b/lib/lz4/lz4_decompress.c @@ -1,16 +1,25 @@ /* + * LZ4 Decompressor for Linux kernel + * + * Copyright (C) 2013, LG Electronics, Kyungsik Lee + * + * Based on LZ4 implementation by Yann Collet. + * * LZ4 - Fast LZ compression algorithm - * Copyright (C) 2011 - 2016, Yann Collet. - * BSD 2 - Clause License (http://www.opensource.org/licenses/bsd - license.php) + * Copyright (C) 2011-2012, Yann Collet. + * BSD 2-Clause License (http://www.opensource.org/licenses/bsd-license.php) + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following disclaimer * in the documentation and/or other materials provided with the * distribution. + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -22,529 +31,313 @@ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * You can contact the author at : - * - LZ4 homepage : http://www.lz4.org - * - LZ4 source repository : https://github.com/lz4/lz4 * - * Changed for kernel usage by: - * Sven Schmidt <4sschmid@informatik.uni-hamburg.de> + * You can contact the author at : + * - LZ4 homepage : http://fastcompression.blogspot.com/p/lz4.html + * - LZ4 source repository : http://code.google.com/p/lz4/ */ -/*-************************************ - * Dependencies - **************************************/ -#include -#include "lz4defs.h" -#include +#ifndef STATIC #include #include +#endif +#include + #include -/*-***************************** - * Decompression functions - *******************************/ -/* LZ4_decompress_generic() : - * This generic decompression function cover all use cases. - * It shall be instantiated several times, using different sets of directives - * Note that it is important this generic function is really inlined, - * in order to remove useless branches during compilation optimization. - */ -static FORCE_INLINE int LZ4_decompress_generic( - const char * const source, - char * const dest, - int inputSize, - /* - * If endOnInput == endOnInputSize, - * this value is the max size of Output Buffer. - */ - int outputSize, - /* endOnOutputSize, endOnInputSize */ - int endOnInput, - /* full, partial */ - int partialDecoding, - /* only used if partialDecoding == partial */ - int targetOutputSize, - /* noDict, withPrefix64k, usingExtDict */ - int dict, - /* == dest when no prefix */ - const BYTE * const lowPrefix, - /* only if dict == usingExtDict */ - const BYTE * const dictStart, - /* note : = 0 if noDict */ - const size_t dictSize - ) +#include "lz4defs.h" + +static const int dec32table[] = {0, 3, 2, 3, 0, 0, 0, 0}; +#if LZ4_ARCH64 +static const int dec64table[] = {0, 0, 0, -1, 0, 1, 2, 3}; +#endif + +static int lz4_uncompress(const char *source, char *dest, int osize) { - /* Local Variables */ const BYTE *ip = (const BYTE *) source; - const BYTE * const iend = ip + inputSize; - + const BYTE *ref; BYTE *op = (BYTE *) dest; - BYTE * const oend = op + outputSize; + BYTE * const oend = op + osize; BYTE *cpy; - BYTE *oexit = op + targetOutputSize; - const BYTE * const lowLimit = lowPrefix - dictSize; - - const BYTE * const dictEnd = (const BYTE *)dictStart + dictSize; - const unsigned int dec32table[] = { 0, 1, 2, 1, 4, 4, 4, 4 }; - const int dec64table[] = { 0, 0, 0, -1, 0, 1, 2, 3 }; + unsigned token; + size_t length; - const int safeDecode = (endOnInput == endOnInputSize); - const int checkOffset = ((safeDecode) && (dictSize < (int)(64 * KB))); - - /* Special cases */ - /* targetOutputSize too high => decode everything */ - if ((partialDecoding) && (oexit > oend - MFLIMIT)) - oexit = oend - MFLIMIT; - - /* Empty output buffer */ - if ((endOnInput) && (unlikely(outputSize == 0))) - return ((inputSize == 1) && (*ip == 0)) ? 0 : -1; - - if ((!endOnInput) && (unlikely(outputSize == 0))) - return (*ip == 0 ? 1 : -1); - - /* Main Loop : decode sequences */ while (1) { - size_t length; - const BYTE *match; - size_t offset; - - /* get literal length */ - unsigned int const token = *ip++; - - length = token>>ML_BITS; + /* get runlength */ + token = *ip++; + length = (token >> ML_BITS); if (length == RUN_MASK) { - unsigned int s; + size_t len; - do { - s = *ip++; - length += s; - } while (likely(endOnInput - ? ip < iend - RUN_MASK - : 1) & (s == 255)); - - if ((safeDecode) - && unlikely( - (size_t)(op + length) < (size_t)(op))) { - /* overflow detection */ + len = *ip++; + for (; len == 255; length += 255) + len = *ip++; + if (unlikely(length > (size_t)(length + len))) goto _output_error; - } - if ((safeDecode) - && unlikely( - (size_t)(ip + length) < (size_t)(ip))) { - /* overflow detection */ - goto _output_error; - } + length += len; } /* copy literals */ cpy = op + length; - if (((endOnInput) && ((cpy > (partialDecoding ? oexit : oend - MFLIMIT)) - || (ip + length > iend - (2 + 1 + LASTLITERALS)))) - || ((!endOnInput) && (cpy > oend - WILDCOPYLENGTH))) { - if (partialDecoding) { - if (cpy > oend) { - /* - * Error : - * write attempt beyond end of output buffer - */ - goto _output_error; - } - if ((endOnInput) - && (ip + length > iend)) { - /* - * Error : - * read attempt beyond - * end of input buffer - */ - goto _output_error; - } - } else { - if ((!endOnInput) - && (cpy != oend)) { - /* - * Error : - * block decoding must - * stop exactly there - */ - goto _output_error; - } - if ((endOnInput) - && ((ip + length != iend) - || (cpy > oend))) { - /* - * Error : - * input must be consumed - */ - goto _output_error; - } - } + if (unlikely(cpy > oend - COPYLENGTH)) { + /* + * Error: not enough place for another match + * (min 4) + 5 literals + */ + if (cpy != oend) + goto _output_error; memcpy(op, ip, length); ip += length; - op += length; - /* Necessarily EOF, due to parsing restrictions */ - break; + break; /* EOF */ } - - LZ4_wildCopy(op, ip, cpy); - ip += length; + LZ4_WILDCOPY(ip, op, cpy); + ip -= (op - cpy); op = cpy; /* get offset */ - offset = LZ4_readLE16(ip); + LZ4_READ_LITTLEENDIAN_16(ref, cpy, ip); ip += 2; - match = op - offset; - if ((checkOffset) && (unlikely(match < lowLimit))) { - /* Error : offset outside buffers */ + /* Error: offset create reference outside destination buffer */ + if (unlikely(ref < (BYTE *const) dest)) goto _output_error; - } - - /* costs ~1%; silence an msan warning when offset == 0 */ - LZ4_write32(op, (U32)offset); /* get matchlength */ length = token & ML_MASK; if (length == ML_MASK) { - unsigned int s; - - do { - s = *ip++; - - if ((endOnInput) && (ip > iend - LASTLITERALS)) - goto _output_error; - - length += s; - } while (s == 255); - - if ((safeDecode) - && unlikely( - (size_t)(op + length) < (size_t)op)) { - /* overflow detection */ + for (; *ip == 255; length += 255) + ip++; + if (unlikely(length > (size_t)(length + *ip))) goto _output_error; - } - } - - length += MINMATCH; - - /* check external dictionary */ - if ((dict == usingExtDict) && (match < lowPrefix)) { - if (unlikely(op + length > oend - LASTLITERALS)) { - /* doesn't respect parsing restriction */ - goto _output_error; - } - - if (length <= (size_t)(lowPrefix - match)) { - /* - * match can be copied as a single segment - * from external dictionary - */ - memmove(op, dictEnd - (lowPrefix - match), - length); - op += length; - } else { - /* - * match encompass external - * dictionary and current block - */ - size_t const copySize = (size_t)(lowPrefix - match); - size_t const restSize = length - copySize; - - memcpy(op, dictEnd - copySize, copySize); - op += copySize; - - if (restSize > (size_t)(op - lowPrefix)) { - /* overlap copy */ - BYTE * const endOfMatch = op + restSize; - const BYTE *copyFrom = lowPrefix; - - while (op < endOfMatch) - *op++ = *copyFrom++; - } else { - memcpy(op, lowPrefix, restSize); - op += restSize; - } - } - - continue; + length += *ip++; } - /* copy match within block */ - cpy = op + length; - - if (unlikely(offset < 8)) { - const int dec64 = dec64table[offset]; - - op[0] = match[0]; - op[1] = match[1]; - op[2] = match[2]; - op[3] = match[3]; - match += dec32table[offset]; - memcpy(op + 4, match, 4); - match -= dec64; + /* copy repeated sequence */ + if (unlikely((op - ref) < STEPSIZE)) { +#if LZ4_ARCH64 + int dec64 = dec64table[op - ref]; +#else + const int dec64 = 0; +#endif + op[0] = ref[0]; + op[1] = ref[1]; + op[2] = ref[2]; + op[3] = ref[3]; + op += 4; + ref += 4; + ref -= dec32table[op-ref]; + PUT4(ref, op); + op += STEPSIZE - 4; + ref -= dec64; } else { - LZ4_copy8(op, match); - match += 8; + LZ4_COPYSTEP(ref, op); } + cpy = op + length - (STEPSIZE - 4); + if (cpy > (oend - COPYLENGTH)) { - op += 8; - - if (unlikely(cpy > oend - 12)) { - BYTE * const oCopyLimit = oend - (WILDCOPYLENGTH - 1); - - if (cpy > oend - LASTLITERALS) { - /* - * Error : last LASTLITERALS bytes - * must be literals (uncompressed) - */ + /* Error: request to write beyond destination buffer */ + if (cpy > oend) goto _output_error; - } - - if (op < oCopyLimit) { - LZ4_wildCopy(op, match, oCopyLimit); - match += oCopyLimit - op; - op = oCopyLimit; - } - +#if LZ4_ARCH64 + if ((ref + COPYLENGTH) > oend) +#else + if ((ref + COPYLENGTH) > oend || + (op + COPYLENGTH) > oend) +#endif + goto _output_error; + LZ4_SECURECOPY(ref, op, (oend - COPYLENGTH)); while (op < cpy) - *op++ = *match++; - } else { - LZ4_copy8(op, match); - - if (length > 16) - LZ4_wildCopy(op + 8, match + 8, cpy); + *op++ = *ref++; + op = cpy; + /* + * Check EOF (should never happen, since last 5 bytes + * are supposed to be literals) + */ + if (op == oend) + goto _output_error; + continue; } - + LZ4_SECURECOPY(ref, op, cpy); op = cpy; /* correction */ } - /* end of decoding */ - if (endOnInput) { - /* Nb of output bytes decoded */ - return (int) (((char *)op) - dest); - } else { - /* Nb of input bytes read */ - return (int) (((const char *)ip) - source); - } + return (int) (((char *)ip) - source); - /* Overflow error detected */ + /* write overflow error detected */ _output_error: return -1; } -int LZ4_decompress_safe(const char *source, char *dest, - int compressedSize, int maxDecompressedSize) +static int lz4_uncompress_unknownoutputsize(const char *source, char *dest, + int isize, size_t maxoutputsize) { - return LZ4_decompress_generic(source, dest, compressedSize, - maxDecompressedSize, endOnInputSize, full, 0, - noDict, (BYTE *)dest, NULL, 0); -} + const BYTE *ip = (const BYTE *) source; + const BYTE *const iend = ip + isize; + const BYTE *ref; -int LZ4_decompress_safe_partial(const char *source, char *dest, - int compressedSize, int targetOutputSize, int maxDecompressedSize) -{ - return LZ4_decompress_generic(source, dest, compressedSize, - maxDecompressedSize, endOnInputSize, partial, - targetOutputSize, noDict, (BYTE *)dest, NULL, 0); -} -int LZ4_decompress_fast(const char *source, char *dest, int originalSize) -{ - return LZ4_decompress_generic(source, dest, 0, originalSize, - endOnOutputSize, full, 0, withPrefix64k, - (BYTE *)(dest - 64 * KB), NULL, 64 * KB); -} - -int LZ4_setStreamDecode(LZ4_streamDecode_t *LZ4_streamDecode, - const char *dictionary, int dictSize) -{ - LZ4_streamDecode_t_internal *lz4sd = (LZ4_streamDecode_t_internal *) LZ4_streamDecode; + BYTE *op = (BYTE *) dest; + BYTE * const oend = op + maxoutputsize; + BYTE *cpy; - lz4sd->prefixSize = (size_t) dictSize; - lz4sd->prefixEnd = (const BYTE *) dictionary + dictSize; - lz4sd->externalDict = NULL; - lz4sd->extDictSize = 0; - return 1; -} + /* Main Loop */ + while (ip < iend) { -/* - * *_continue() : - * These decoding functions allow decompression of multiple blocks - * in "streaming" mode. - * Previously decoded blocks must still be available at the memory - * position where they were decoded. - * If it's not possible, save the relevant part of - * decoded data into a safe buffer, - * and indicate where it stands using LZ4_setStreamDecode() - */ -int LZ4_decompress_safe_continue(LZ4_streamDecode_t *LZ4_streamDecode, - const char *source, char *dest, int compressedSize, int maxOutputSize) -{ - LZ4_streamDecode_t_internal *lz4sd = &LZ4_streamDecode->internal_donotuse; - int result; - - if (lz4sd->prefixEnd == (BYTE *)dest) { - result = LZ4_decompress_generic(source, dest, - compressedSize, - maxOutputSize, - endOnInputSize, full, 0, - usingExtDict, lz4sd->prefixEnd - lz4sd->prefixSize, - lz4sd->externalDict, - lz4sd->extDictSize); - - if (result <= 0) - return result; - - lz4sd->prefixSize += result; - lz4sd->prefixEnd += result; - } else { - lz4sd->extDictSize = lz4sd->prefixSize; - lz4sd->externalDict = lz4sd->prefixEnd - lz4sd->extDictSize; - result = LZ4_decompress_generic(source, dest, - compressedSize, maxOutputSize, - endOnInputSize, full, 0, - usingExtDict, (BYTE *)dest, - lz4sd->externalDict, lz4sd->extDictSize); - if (result <= 0) - return result; - lz4sd->prefixSize = result; - lz4sd->prefixEnd = (BYTE *)dest + result; - } + unsigned token; + size_t length; - return result; -} + /* get runlength */ + token = *ip++; + length = (token >> ML_BITS); + if (length == RUN_MASK) { + int s = 255; + while ((ip < iend) && (s == 255)) { + s = *ip++; + if (unlikely(length > (size_t)(length + s))) + goto _output_error; + length += s; + } + } + /* copy literals */ + cpy = op + length; + if ((cpy > oend - COPYLENGTH) || + (ip + length > iend - COPYLENGTH)) { + + if (cpy > oend) + goto _output_error;/* writes beyond buffer */ + + if (ip + length != iend) + goto _output_error;/* + * Error: LZ4 format requires + * to consume all input + * at this stage + */ + memcpy(op, ip, length); + op += length; + break;/* Necessarily EOF, due to parsing restrictions */ + } + LZ4_WILDCOPY(ip, op, cpy); + ip -= (op - cpy); + op = cpy; -int LZ4_decompress_fast_continue(LZ4_streamDecode_t *LZ4_streamDecode, - const char *source, char *dest, int originalSize) -{ - LZ4_streamDecode_t_internal *lz4sd = &LZ4_streamDecode->internal_donotuse; - int result; - - if (lz4sd->prefixEnd == (BYTE *)dest) { - result = LZ4_decompress_generic(source, dest, 0, originalSize, - endOnOutputSize, full, 0, - usingExtDict, - lz4sd->prefixEnd - lz4sd->prefixSize, - lz4sd->externalDict, lz4sd->extDictSize); - - if (result <= 0) - return result; - - lz4sd->prefixSize += originalSize; - lz4sd->prefixEnd += originalSize; - } else { - lz4sd->extDictSize = lz4sd->prefixSize; - lz4sd->externalDict = lz4sd->prefixEnd - lz4sd->extDictSize; - result = LZ4_decompress_generic(source, dest, 0, originalSize, - endOnOutputSize, full, 0, - usingExtDict, (BYTE *)dest, - lz4sd->externalDict, lz4sd->extDictSize); - if (result <= 0) - return result; - lz4sd->prefixSize = originalSize; - lz4sd->prefixEnd = (BYTE *)dest + originalSize; - } + /* get offset */ + LZ4_READ_LITTLEENDIAN_16(ref, cpy, ip); + ip += 2; + if (ref < (BYTE * const) dest) + goto _output_error; + /* + * Error : offset creates reference + * outside of destination buffer + */ - return result; -} + /* get matchlength */ + length = (token & ML_MASK); + if (length == ML_MASK) { + while (ip < iend) { + int s = *ip++; + if (unlikely(length > (size_t)(length + s))) + goto _output_error; + length += s; + if (s == 255) + continue; + break; + } + } -/* - * Advanced decoding functions : - * *_usingDict() : - * These decoding functions work the same as "_continue" ones, - * the dictionary must be explicitly provided within parameters - */ -static FORCE_INLINE int LZ4_decompress_usingDict_generic(const char *source, - char *dest, int compressedSize, int maxOutputSize, int safe, - const char *dictStart, int dictSize) -{ - if (dictSize == 0) - return LZ4_decompress_generic(source, dest, - compressedSize, maxOutputSize, safe, full, 0, - noDict, (BYTE *)dest, NULL, 0); - if (dictStart + dictSize == dest) { - if (dictSize >= (int)(64 * KB - 1)) - return LZ4_decompress_generic(source, dest, - compressedSize, maxOutputSize, safe, full, 0, - withPrefix64k, (BYTE *)dest - 64 * KB, NULL, 0); - return LZ4_decompress_generic(source, dest, compressedSize, - maxOutputSize, safe, full, 0, noDict, - (BYTE *)dest - dictSize, NULL, 0); + /* copy repeated sequence */ + if (unlikely((op - ref) < STEPSIZE)) { +#if LZ4_ARCH64 + int dec64 = dec64table[op - ref]; +#else + const int dec64 = 0; +#endif + op[0] = ref[0]; + op[1] = ref[1]; + op[2] = ref[2]; + op[3] = ref[3]; + op += 4; + ref += 4; + ref -= dec32table[op - ref]; + PUT4(ref, op); + op += STEPSIZE - 4; + ref -= dec64; + } else { + LZ4_COPYSTEP(ref, op); + } + cpy = op + length - (STEPSIZE-4); + if (cpy > oend - COPYLENGTH) { + if (cpy > oend) + goto _output_error; /* write outside of buf */ +#if LZ4_ARCH64 + if ((ref + COPYLENGTH) > oend) +#else + if ((ref + COPYLENGTH) > oend || + (op + COPYLENGTH) > oend) +#endif + goto _output_error; + LZ4_SECURECOPY(ref, op, (oend - COPYLENGTH)); + while (op < cpy) + *op++ = *ref++; + op = cpy; + /* + * Check EOF (should never happen, since last 5 bytes + * are supposed to be literals) + */ + if (op == oend) + goto _output_error; + continue; + } + LZ4_SECURECOPY(ref, op, cpy); + op = cpy; /* correction */ } - return LZ4_decompress_generic(source, dest, compressedSize, - maxOutputSize, safe, full, 0, usingExtDict, - (BYTE *)dest, (const BYTE *)dictStart, dictSize); -} + /* end of decoding */ + return (int) (((char *) op) - dest); -int LZ4_decompress_safe_usingDict(const char *source, char *dest, - int compressedSize, int maxOutputSize, - const char *dictStart, int dictSize) -{ - return LZ4_decompress_usingDict_generic(source, dest, - compressedSize, maxOutputSize, 1, dictStart, dictSize); + /* write overflow error detected */ +_output_error: + return -1; } -int LZ4_decompress_fast_usingDict(const char *source, char *dest, - int originalSize, const char *dictStart, int dictSize) +int lz4_decompress(const unsigned char *src, size_t *src_len, + unsigned char *dest, size_t actual_dest_len) { - return LZ4_decompress_usingDict_generic(source, dest, 0, - originalSize, 0, dictStart, dictSize); -} + int ret = -1; + int input_len = 0; -/*-****************************** - * For backwards compatibility - ********************************/ -int lz4_decompress_unknownoutputsize(const unsigned char *src, - size_t src_len, unsigned char *dest, size_t *dest_len) { - *dest_len = LZ4_decompress_safe(src, dest, - src_len, *dest_len); - - /* - * Prior lz4_decompress_unknownoutputsize will return - * 0 for success and a negative result for error - * new LZ4_decompress_safe returns - * - the length of data read on success - * - and also a negative result on error - * meaning when result > 0, we just return 0 here - */ - if (src_len > 0) - return 0; - else - return -1; -} + input_len = lz4_uncompress(src, dest, actual_dest_len); + if (input_len < 0) + goto exit_0; + *src_len = input_len; -int lz4_decompress(const unsigned char *src, size_t *src_len, - unsigned char *dest, size_t actual_dest_len) { - *src_len = LZ4_decompress_fast(src, dest, actual_dest_len); - - /* - * Prior lz4_decompress will return - * 0 for success and a negative result for error - * new LZ4_decompress_fast returns - * - the length of data read on success - * - and also a negative result on error - * meaning when result > 0, we just return 0 here - */ - if (*src_len > 0) - return 0; - else - return -1; + return 0; +exit_0: + return ret; } +#ifndef STATIC +EXPORT_SYMBOL(lz4_decompress); +#endif +int lz4_decompress_unknownoutputsize(const unsigned char *src, size_t src_len, + unsigned char *dest, size_t *dest_len) +{ + int ret = -1; + int out_len = 0; + + out_len = lz4_uncompress_unknownoutputsize(src, dest, src_len, + *dest_len); + if (out_len < 0) + goto exit_0; + *dest_len = out_len; + + return 0; +exit_0: + return ret; +} #ifndef STATIC -EXPORT_SYMBOL(LZ4_decompress_safe); -EXPORT_SYMBOL(LZ4_decompress_safe_partial); -EXPORT_SYMBOL(LZ4_decompress_fast); -EXPORT_SYMBOL(LZ4_setStreamDecode); -EXPORT_SYMBOL(LZ4_decompress_safe_continue); -EXPORT_SYMBOL(LZ4_decompress_fast_continue); -EXPORT_SYMBOL(LZ4_decompress_safe_usingDict); -EXPORT_SYMBOL(LZ4_decompress_fast_usingDict); EXPORT_SYMBOL(lz4_decompress_unknownoutputsize); -EXPORT_SYMBOL(lz4_decompress); MODULE_LICENSE("Dual BSD/GPL"); -MODULE_DESCRIPTION("LZ4 decompressor"); +MODULE_DESCRIPTION("LZ4 Decompressor"); #endif diff --git a/lib/lz4/lz4defs.h b/lib/lz4/lz4defs.h index 00a0b58a0871..c79d7ea8a38e 100644 --- a/lib/lz4/lz4defs.h +++ b/lib/lz4/lz4defs.h @@ -1,227 +1,157 @@ -#ifndef __LZ4DEFS_H__ -#define __LZ4DEFS_H__ - /* - * lz4defs.h -- common and architecture specific defines for the kernel usage - - * LZ4 - Fast LZ compression algorithm - * Copyright (C) 2011-2016, Yann Collet. - * BSD 2-Clause License (http://www.opensource.org/licenses/bsd-license.php) - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above - * copyright notice, this list of conditions and the following disclaimer - * in the documentation and/or other materials provided with the - * distribution. - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * You can contact the author at : - * - LZ4 homepage : http://www.lz4.org - * - LZ4 source repository : https://github.com/lz4/lz4 + * lz4defs.h -- architecture specific defines + * + * Copyright (C) 2013, LG Electronics, Kyungsik Lee * - * Changed for kernel usage by: - * Sven Schmidt <4sschmid@informatik.uni-hamburg.de> + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. */ -#include -#include /* memset, memcpy */ - -#define FORCE_INLINE __always_inline - -/*-************************************ - * Basic Types - **************************************/ -#include - -typedef uint8_t BYTE; -typedef uint16_t U16; -typedef uint32_t U32; -typedef int32_t S32; -typedef uint64_t U64; -typedef uintptr_t uptrval; - -/*-************************************ - * Architecture specifics - **************************************/ +/* + * Detects 64 bits mode + */ #if defined(CONFIG_64BIT) #define LZ4_ARCH64 1 #else #define LZ4_ARCH64 0 #endif -#if defined(__LITTLE_ENDIAN) -#define LZ4_LITTLE_ENDIAN 1 -#else -#define LZ4_LITTLE_ENDIAN 0 +/* + * Architecture-specific macros + */ +#define BYTE u8 +typedef struct _U16_S { u16 v; } U16_S; +typedef struct _U32_S { u32 v; } U32_S; +typedef struct _U64_S { u64 v; } U64_S; +#if defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) + +#define A16(x) (((U16_S *)(x))->v) +#define A32(x) (((U32_S *)(x))->v) +#define A64(x) (((U64_S *)(x))->v) + +#define PUT4(s, d) (A32(d) = A32(s)) +#define PUT8(s, d) (A64(d) = A64(s)) + +#define LZ4_READ_LITTLEENDIAN_16(d, s, p) \ + (d = s - A16(p)) + +#define LZ4_WRITE_LITTLEENDIAN_16(p, v) \ + do { \ + A16(p) = v; \ + p += 2; \ + } while (0) +#else /* CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS */ + +#define A64(x) get_unaligned((u64 *)&(((U16_S *)(x))->v)) +#define A32(x) get_unaligned((u32 *)&(((U16_S *)(x))->v)) +#define A16(x) get_unaligned((u16 *)&(((U16_S *)(x))->v)) + +#define PUT4(s, d) \ + put_unaligned(get_unaligned((const u32 *) s), (u32 *) d) +#define PUT8(s, d) \ + put_unaligned(get_unaligned((const u64 *) s), (u64 *) d) + +#define LZ4_READ_LITTLEENDIAN_16(d, s, p) \ + (d = s - get_unaligned_le16(p)) + +#define LZ4_WRITE_LITTLEENDIAN_16(p, v) \ + do { \ + put_unaligned_le16(v, (u16 *)(p)); \ + p += 2; \ + } while (0) #endif -/*-************************************ - * Constants - **************************************/ -#define MINMATCH 4 - -#define WILDCOPYLENGTH 8 -#define LASTLITERALS 5 -#define MFLIMIT (WILDCOPYLENGTH + MINMATCH) - -/* Increase this value ==> compression run slower on incompressible data */ -#define LZ4_SKIPTRIGGER 6 - -#define HASH_UNIT sizeof(size_t) - -#define KB (1 << 10) -#define MB (1 << 20) -#define GB (1U << 30) - -#define MAXD_LOG 16 -#define MAX_DISTANCE ((1 << MAXD_LOG) - 1) -#define STEPSIZE sizeof(size_t) - -#define ML_BITS 4 -#define ML_MASK ((1U << ML_BITS) - 1) +#define COPYLENGTH 8 +#define ML_BITS 4 +#define ML_MASK ((1U << ML_BITS) - 1) #define RUN_BITS (8 - ML_BITS) #define RUN_MASK ((1U << RUN_BITS) - 1) - -/*-************************************ - * Reading and writing into memory - **************************************/ -static FORCE_INLINE U16 LZ4_read16(const void *ptr) -{ - return get_unaligned((const U16 *)ptr); -} - -static FORCE_INLINE U32 LZ4_read32(const void *ptr) -{ - return get_unaligned((const U32 *)ptr); -} - -static FORCE_INLINE size_t LZ4_read_ARCH(const void *ptr) -{ - return get_unaligned((const size_t *)ptr); -} - -static FORCE_INLINE void LZ4_write16(void *memPtr, U16 value) -{ - put_unaligned(value, (U16 *)memPtr); -} - -static FORCE_INLINE void LZ4_write32(void *memPtr, U32 value) -{ - put_unaligned(value, (U32 *)memPtr); -} - -static FORCE_INLINE U16 LZ4_readLE16(const void *memPtr) -{ - return get_unaligned_le16(memPtr); -} - -static FORCE_INLINE void LZ4_writeLE16(void *memPtr, U16 value) -{ - return put_unaligned_le16(value, memPtr); -} - -static FORCE_INLINE void LZ4_copy8(void *dst, const void *src) -{ -#if LZ4_ARCH64 - U64 a = get_unaligned((const U64 *)src); - - put_unaligned(a, (U64 *)dst); -#else - U32 a = get_unaligned((const U32 *)src); - U32 b = get_unaligned((const U32 *)src + 1); - - put_unaligned(a, (U32 *)dst); - put_unaligned(b, (U32 *)dst + 1); -#endif -} - -/* - * customized variant of memcpy, - * which can overwrite up to 7 bytes beyond dstEnd - */ -static FORCE_INLINE void LZ4_wildCopy(void *dstPtr, - const void *srcPtr, void *dstEnd) -{ - BYTE *d = (BYTE *)dstPtr; - const BYTE *s = (const BYTE *)srcPtr; - BYTE *const e = (BYTE *)dstEnd; - - do { - LZ4_copy8(d, s); - d += 8; - s += 8; - } while (d < e); -} - -static FORCE_INLINE unsigned int LZ4_NbCommonBytes(register size_t val) -{ -#if LZ4_LITTLE_ENDIAN - return __ffs(val) >> 3; +#define MEMORY_USAGE 14 +#define MINMATCH 4 +#define SKIPSTRENGTH 6 +#define LASTLITERALS 5 +#define MFLIMIT (COPYLENGTH + MINMATCH) +#define MINLENGTH (MFLIMIT + 1) +#define MAXD_LOG 16 +#define MAXD (1 << MAXD_LOG) +#define MAXD_MASK (u32)(MAXD - 1) +#define MAX_DISTANCE (MAXD - 1) +#define HASH_LOG (MAXD_LOG - 1) +#define HASHTABLESIZE (1 << HASH_LOG) +#define MAX_NB_ATTEMPTS 256 +#define OPTIMAL_ML (int)((ML_MASK-1)+MINMATCH) +#define LZ4_64KLIMIT ((1<<16) + (MFLIMIT - 1)) +#define HASHLOG64K ((MEMORY_USAGE - 2) + 1) +#define HASH64KTABLESIZE (1U << HASHLOG64K) +#define LZ4_HASH_VALUE(p) (((A32(p)) * 2654435761U) >> \ + ((MINMATCH * 8) - (MEMORY_USAGE-2))) +#define LZ4_HASH64K_VALUE(p) (((A32(p)) * 2654435761U) >> \ + ((MINMATCH * 8) - HASHLOG64K)) +#define HASH_VALUE(p) (((A32(p)) * 2654435761U) >> \ + ((MINMATCH * 8) - HASH_LOG)) + +#if LZ4_ARCH64/* 64-bit */ +#define STEPSIZE 8 + +#define LZ4_COPYSTEP(s, d) \ + do { \ + PUT8(s, d); \ + d += 8; \ + s += 8; \ + } while (0) + +#define LZ4_COPYPACKET(s, d) LZ4_COPYSTEP(s, d) + +#define LZ4_SECURECOPY(s, d, e) \ + do { \ + if (d < e) { \ + LZ4_WILDCOPY(s, d, e); \ + } \ + } while (0) +#define HTYPE u32 + +#ifdef __BIG_ENDIAN +#define LZ4_NBCOMMONBYTES(val) (__builtin_clzll(val) >> 3) #else - return (BITS_PER_LONG - 1 - __fls(val)) >> 3; +#define LZ4_NBCOMMONBYTES(val) (__builtin_ctzll(val) >> 3) #endif -} - -static FORCE_INLINE unsigned int LZ4_count( - const BYTE *pIn, - const BYTE *pMatch, - const BYTE *pInLimit) -{ - const BYTE *const pStart = pIn; - - while (likely(pIn < pInLimit - (STEPSIZE - 1))) { - size_t const diff = LZ4_read_ARCH(pMatch) ^ LZ4_read_ARCH(pIn); - - if (!diff) { - pIn += STEPSIZE; - pMatch += STEPSIZE; - continue; - } - - pIn += LZ4_NbCommonBytes(diff); - - return (unsigned int)(pIn - pStart); - } - -#if LZ4_ARCH64 - if ((pIn < (pInLimit - 3)) - && (LZ4_read32(pMatch) == LZ4_read32(pIn))) { - pIn += 4; - pMatch += 4; - } -#endif - - if ((pIn < (pInLimit - 1)) - && (LZ4_read16(pMatch) == LZ4_read16(pIn))) { - pIn += 2; - pMatch += 2; - } - if ((pIn < pInLimit) && (*pMatch == *pIn)) - pIn++; +#else /* 32-bit */ +#define STEPSIZE 4 - return (unsigned int)(pIn - pStart); -} +#define LZ4_COPYSTEP(s, d) \ + do { \ + PUT4(s, d); \ + d += 4; \ + s += 4; \ + } while (0) -typedef enum { noLimit = 0, limitedOutput = 1 } limitedOutput_directive; -typedef enum { byPtr, byU32, byU16 } tableType_t; +#define LZ4_COPYPACKET(s, d) \ + do { \ + LZ4_COPYSTEP(s, d); \ + LZ4_COPYSTEP(s, d); \ + } while (0) -typedef enum { noDict = 0, withPrefix64k, usingExtDict } dict_directive; -typedef enum { noDictIssue = 0, dictSmall } dictIssue_directive; +#define LZ4_SECURECOPY LZ4_WILDCOPY +#define HTYPE const u8* -typedef enum { endOnOutputSize = 0, endOnInputSize = 1 } endCondition_directive; -typedef enum { full = 0, partial = 1 } earlyEnd_directive; +#ifdef __BIG_ENDIAN +#define LZ4_NBCOMMONBYTES(val) (__builtin_clz(val) >> 3) +#else +#define LZ4_NBCOMMONBYTES(val) (__builtin_ctz(val) >> 3) +#endif #endif + +#define LZ4_WILDCOPY(s, d, e) \ + do { \ + LZ4_COPYPACKET(s, d); \ + } while (d < e) + +#define LZ4_BLINDCOPY(s, d, l) \ + do { \ + u8 *e = (d) + l; \ + LZ4_WILDCOPY(s, d, e); \ + d = e; \ + } while (0) diff --git a/lib/lz4/lz4hc_compress.c b/lib/lz4/lz4hc_compress.c index e1fbf1561e55..6b2e046a9c61 100644 --- a/lib/lz4/lz4hc_compress.c +++ b/lib/lz4/lz4hc_compress.c @@ -1,17 +1,19 @@ /* * LZ4 HC - High Compression Mode of LZ4 - * Copyright (C) 2011-2015, Yann Collet. + * Copyright (C) 2011-2012, Yann Collet. + * BSD 2-Clause License (http://www.opensource.org/licenses/bsd-license.php) * - * BSD 2 - Clause License (http://www.opensource.org/licenses/bsd - license.php) * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are * met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above * copyright notice, this list of conditions and the following disclaimer * in the documentation and/or other materials provided with the * distribution. + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -23,361 +25,323 @@ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * * You can contact the author at : - * - LZ4 homepage : http://www.lz4.org - * - LZ4 source repository : https://github.com/lz4/lz4 + * - LZ4 homepage : http://fastcompression.blogspot.com/p/lz4.html + * - LZ4 source repository : http://code.google.com/p/lz4/ * - * Changed for kernel usage by: - * Sven Schmidt <4sschmid@informatik.uni-hamburg.de> + * Changed for kernel use by: + * Chanho Min */ -/*-************************************ - * Dependencies - **************************************/ -#include -#include "lz4defs.h" #include #include -#include /* memset */ - -/* ************************************* - * Local Constants and types - ***************************************/ - -#define OPTIMAL_ML (int)((ML_MASK - 1) + MINMATCH) - -#define HASH_FUNCTION(i) (((i) * 2654435761U) \ - >> ((MINMATCH*8) - LZ4HC_HASH_LOG)) -#define DELTANEXTU16(p) chainTable[(U16)(p)] /* faster */ +#include +#include +#include "lz4defs.h" -static U32 LZ4HC_hashPtr(const void *ptr) -{ - return HASH_FUNCTION(LZ4_read32(ptr)); -} +struct lz4hc_data { + const u8 *base; + HTYPE hashtable[HASHTABLESIZE]; + u16 chaintable[MAXD]; + const u8 *nexttoupdate; +} __attribute__((__packed__)); -/************************************** - * HC Compression - **************************************/ -static void LZ4HC_init(LZ4HC_CCtx_internal *hc4, const BYTE *start) +static inline int lz4hc_init(struct lz4hc_data *hc4, const u8 *base) { - memset((void *)hc4->hashTable, 0, sizeof(hc4->hashTable)); - memset(hc4->chainTable, 0xFF, sizeof(hc4->chainTable)); - hc4->nextToUpdate = 64 * KB; - hc4->base = start - 64 * KB; - hc4->end = start; - hc4->dictBase = start - 64 * KB; - hc4->dictLimit = 64 * KB; - hc4->lowLimit = 64 * KB; + memset((void *)hc4->hashtable, 0, sizeof(hc4->hashtable)); + memset(hc4->chaintable, 0xFF, sizeof(hc4->chaintable)); + +#if LZ4_ARCH64 + hc4->nexttoupdate = base + 1; +#else + hc4->nexttoupdate = base; +#endif + hc4->base = base; + return 1; } /* Update chains up to ip (excluded) */ -static FORCE_INLINE void LZ4HC_Insert(LZ4HC_CCtx_internal *hc4, - const BYTE *ip) +static inline void lz4hc_insert(struct lz4hc_data *hc4, const u8 *ip) { - U16 * const chainTable = hc4->chainTable; - U32 * const hashTable = hc4->hashTable; + u16 *chaintable = hc4->chaintable; + HTYPE *hashtable = hc4->hashtable; +#if LZ4_ARCH64 const BYTE * const base = hc4->base; - U32 const target = (U32)(ip - base); - U32 idx = hc4->nextToUpdate; - - while (idx < target) { - U32 const h = LZ4HC_hashPtr(base + idx); - size_t delta = idx - hashTable[h]; +#else + const int base = 0; +#endif + while (hc4->nexttoupdate < ip) { + const u8 *p = hc4->nexttoupdate; + size_t delta = p - (hashtable[HASH_VALUE(p)] + base); if (delta > MAX_DISTANCE) delta = MAX_DISTANCE; + chaintable[(size_t)(p) & MAXD_MASK] = (u16)delta; + hashtable[HASH_VALUE(p)] = (p) - base; + hc4->nexttoupdate++; + } +} - DELTANEXTU16(idx) = (U16)delta; - - hashTable[h] = idx; - idx++; +static inline size_t lz4hc_commonlength(const u8 *p1, const u8 *p2, + const u8 *const matchlimit) +{ + const u8 *p1t = p1; + + while (p1t < matchlimit - (STEPSIZE - 1)) { +#if LZ4_ARCH64 + u64 diff = A64(p2) ^ A64(p1t); +#else + u32 diff = A32(p2) ^ A32(p1t); +#endif + if (!diff) { + p1t += STEPSIZE; + p2 += STEPSIZE; + continue; + } + p1t += LZ4_NBCOMMONBYTES(diff); + return p1t - p1; } +#if LZ4_ARCH64 + if ((p1t < (matchlimit-3)) && (A32(p2) == A32(p1t))) { + p1t += 4; + p2 += 4; + } +#endif - hc4->nextToUpdate = target; + if ((p1t < (matchlimit - 1)) && (A16(p2) == A16(p1t))) { + p1t += 2; + p2 += 2; + } + if ((p1t < matchlimit) && (*p2 == *p1t)) + p1t++; + return p1t - p1; } -static FORCE_INLINE int LZ4HC_InsertAndFindBestMatch( - LZ4HC_CCtx_internal *hc4, /* Index table will be updated */ - const BYTE *ip, - const BYTE * const iLimit, - const BYTE **matchpos, - const int maxNbAttempts) +static inline int lz4hc_insertandfindbestmatch(struct lz4hc_data *hc4, + const u8 *ip, const u8 *const matchlimit, const u8 **matchpos) { - U16 * const chainTable = hc4->chainTable; - U32 * const HashTable = hc4->hashTable; + u16 *const chaintable = hc4->chaintable; + HTYPE *const hashtable = hc4->hashtable; + const u8 *ref; +#if LZ4_ARCH64 const BYTE * const base = hc4->base; - const BYTE * const dictBase = hc4->dictBase; - const U32 dictLimit = hc4->dictLimit; - const U32 lowLimit = (hc4->lowLimit + 64 * KB > (U32)(ip - base)) - ? hc4->lowLimit - : (U32)(ip - base) - (64 * KB - 1); - U32 matchIndex; - int nbAttempts = maxNbAttempts; - size_t ml = 0; +#else + const int base = 0; +#endif + int nbattempts = MAX_NB_ATTEMPTS; + size_t repl = 0, ml = 0; + u16 delta = 0; /* HC4 match finder */ - LZ4HC_Insert(hc4, ip); - matchIndex = HashTable[LZ4HC_hashPtr(ip)]; - - while ((matchIndex >= lowLimit) - && (nbAttempts)) { - nbAttempts--; - if (matchIndex >= dictLimit) { - const BYTE * const match = base + matchIndex; - - if (*(match + ml) == *(ip + ml) - && (LZ4_read32(match) == LZ4_read32(ip))) { - size_t const mlt = LZ4_count(ip + MINMATCH, - match + MINMATCH, iLimit) + MINMATCH; + lz4hc_insert(hc4, ip); + ref = hashtable[HASH_VALUE(ip)] + base; + + /* potential repetition */ + if (ref >= ip-4) { + /* confirmed */ + if (A32(ref) == A32(ip)) { + delta = (u16)(ip-ref); + repl = ml = lz4hc_commonlength(ip + MINMATCH, + ref + MINMATCH, matchlimit) + MINMATCH; + *matchpos = ref; + } + ref -= (size_t)chaintable[(size_t)(ref) & MAXD_MASK]; + } + while ((ref >= ip - MAX_DISTANCE) && nbattempts) { + nbattempts--; + if (*(ref + ml) == *(ip + ml)) { + if (A32(ref) == A32(ip)) { + size_t mlt = + lz4hc_commonlength(ip + MINMATCH, + ref + MINMATCH, matchlimit) + MINMATCH; if (mlt > ml) { ml = mlt; - *matchpos = match; - } - } - } else { - const BYTE * const match = dictBase + matchIndex; - - if (LZ4_read32(match) == LZ4_read32(ip)) { - size_t mlt; - const BYTE *vLimit = ip - + (dictLimit - matchIndex); - - if (vLimit > iLimit) - vLimit = iLimit; - mlt = LZ4_count(ip + MINMATCH, - match + MINMATCH, vLimit) + MINMATCH; - if ((ip + mlt == vLimit) - && (vLimit < iLimit)) - mlt += LZ4_count(ip + mlt, - base + dictLimit, - iLimit); - if (mlt > ml) { - /* virtual matchpos */ - ml = mlt; - *matchpos = base + matchIndex; + *matchpos = ref; } } } - matchIndex -= DELTANEXTU16(matchIndex); + ref -= (size_t)chaintable[(size_t)(ref) & MAXD_MASK]; + } + + /* Complete table */ + if (repl) { + const BYTE *ptr = ip; + const BYTE *end; + end = ip + repl - (MINMATCH-1); + /* Pre-Load */ + while (ptr < end - delta) { + chaintable[(size_t)(ptr) & MAXD_MASK] = delta; + ptr++; + } + do { + chaintable[(size_t)(ptr) & MAXD_MASK] = delta; + /* Head of chain */ + hashtable[HASH_VALUE(ptr)] = (ptr) - base; + ptr++; + } while (ptr < end); + hc4->nexttoupdate = end; } return (int)ml; } -static FORCE_INLINE int LZ4HC_InsertAndGetWiderMatch( - LZ4HC_CCtx_internal *hc4, - const BYTE * const ip, - const BYTE * const iLowLimit, - const BYTE * const iHighLimit, - int longest, - const BYTE **matchpos, - const BYTE **startpos, - const int maxNbAttempts) +static inline int lz4hc_insertandgetwidermatch(struct lz4hc_data *hc4, + const u8 *ip, const u8 *startlimit, const u8 *matchlimit, int longest, + const u8 **matchpos, const u8 **startpos) { - U16 * const chainTable = hc4->chainTable; - U32 * const HashTable = hc4->hashTable; + u16 *const chaintable = hc4->chaintable; + HTYPE *const hashtable = hc4->hashtable; +#if LZ4_ARCH64 const BYTE * const base = hc4->base; - const U32 dictLimit = hc4->dictLimit; - const BYTE * const lowPrefixPtr = base + dictLimit; - const U32 lowLimit = (hc4->lowLimit + 64 * KB > (U32)(ip - base)) - ? hc4->lowLimit - : (U32)(ip - base) - (64 * KB - 1); - const BYTE * const dictBase = hc4->dictBase; - U32 matchIndex; - int nbAttempts = maxNbAttempts; - int delta = (int)(ip - iLowLimit); +#else + const int base = 0; +#endif + const u8 *ref; + int nbattempts = MAX_NB_ATTEMPTS; + int delta = (int)(ip - startlimit); /* First Match */ - LZ4HC_Insert(hc4, ip); - matchIndex = HashTable[LZ4HC_hashPtr(ip)]; - - while ((matchIndex >= lowLimit) - && (nbAttempts)) { - nbAttempts--; - if (matchIndex >= dictLimit) { - const BYTE *matchPtr = base + matchIndex; - - if (*(iLowLimit + longest) - == *(matchPtr - delta + longest)) { - if (LZ4_read32(matchPtr) == LZ4_read32(ip)) { - int mlt = MINMATCH + LZ4_count( - ip + MINMATCH, - matchPtr + MINMATCH, - iHighLimit); - int back = 0; - - while ((ip + back > iLowLimit) - && (matchPtr + back > lowPrefixPtr) - && (ip[back - 1] == matchPtr[back - 1])) - back--; - - mlt -= back; - - if (mlt > longest) { - longest = (int)mlt; - *matchpos = matchPtr + back; - *startpos = ip + back; + lz4hc_insert(hc4, ip); + ref = hashtable[HASH_VALUE(ip)] + base; + + while ((ref >= ip - MAX_DISTANCE) && (ref >= hc4->base) + && (nbattempts)) { + nbattempts--; + if (*(startlimit + longest) == *(ref - delta + longest)) { + if (A32(ref) == A32(ip)) { + const u8 *reft = ref + MINMATCH; + const u8 *ipt = ip + MINMATCH; + const u8 *startt = ip; + + while (ipt < matchlimit-(STEPSIZE - 1)) { + #if LZ4_ARCH64 + u64 diff = A64(reft) ^ A64(ipt); + #else + u32 diff = A32(reft) ^ A32(ipt); + #endif + + if (!diff) { + ipt += STEPSIZE; + reft += STEPSIZE; + continue; } + ipt += LZ4_NBCOMMONBYTES(diff); + goto _endcount; } - } - } else { - const BYTE * const matchPtr = dictBase + matchIndex; - - if (LZ4_read32(matchPtr) == LZ4_read32(ip)) { - size_t mlt; - int back = 0; - const BYTE *vLimit = ip + (dictLimit - matchIndex); - - if (vLimit > iHighLimit) - vLimit = iHighLimit; - - mlt = LZ4_count(ip + MINMATCH, - matchPtr + MINMATCH, vLimit) + MINMATCH; - - if ((ip + mlt == vLimit) && (vLimit < iHighLimit)) - mlt += LZ4_count(ip + mlt, base + dictLimit, - iHighLimit); - while ((ip + back > iLowLimit) - && (matchIndex + back > lowLimit) - && (ip[back - 1] == matchPtr[back - 1])) - back--; - - mlt -= back; - - if ((int)mlt > longest) { - longest = (int)mlt; - *matchpos = base + matchIndex + back; - *startpos = ip + back; + #if LZ4_ARCH64 + if ((ipt < (matchlimit - 3)) + && (A32(reft) == A32(ipt))) { + ipt += 4; + reft += 4; + } + ipt += 2; + #endif + if ((ipt < (matchlimit - 1)) + && (A16(reft) == A16(ipt))) { + reft += 2; + } + if ((ipt < matchlimit) && (*reft == *ipt)) + ipt++; +_endcount: + reft = ref; + + while ((startt > startlimit) + && (reft > hc4->base) + && (startt[-1] == reft[-1])) { + startt--; + reft--; + } + + if ((ipt - startt) > longest) { + longest = (int)(ipt - startt); + *matchpos = reft; + *startpos = startt; } } } - - matchIndex -= DELTANEXTU16(matchIndex); + ref -= (size_t)chaintable[(size_t)(ref) & MAXD_MASK]; } - return longest; } -static FORCE_INLINE int LZ4HC_encodeSequence( - const BYTE **ip, - BYTE **op, - const BYTE **anchor, - int matchLength, - const BYTE * const match, - limitedOutput_directive limitedOutputBuffer, - BYTE *oend) +static inline int lz4_encodesequence(const u8 **ip, u8 **op, const u8 **anchor, + int ml, const u8 *ref) { - int length; - BYTE *token; + int length, len; + u8 *token; /* Encode Literal length */ length = (int)(*ip - *anchor); token = (*op)++; - - if ((limitedOutputBuffer) - && ((*op + (length>>8) - + length + (2 + 1 + LASTLITERALS)) > oend)) { - /* Check output limit */ - return 1; - } if (length >= (int)RUN_MASK) { - int len; - - *token = (RUN_MASK< 254 ; len -= 255) *(*op)++ = 255; - *(*op)++ = (BYTE)len; + *(*op)++ = (u8)len; } else - *token = (BYTE)(length<>8) - + (1 + LASTLITERALS) > oend)) { - /* Check output limit */ - return 1; - } - - if (length >= (int)ML_MASK) { + len = (int)(ml - MINMATCH); + if (len >= (int)ML_MASK) { *token += ML_MASK; - length -= ML_MASK; - - for (; length > 509 ; length -= 510) { + len -= ML_MASK; + for (; len > 509 ; len -= 510) { *(*op)++ = 255; *(*op)++ = 255; } - - if (length > 254) { - length -= 255; + if (len > 254) { + len -= 255; *(*op)++ = 255; } - - *(*op)++ = (BYTE)length; + *(*op)++ = (u8)len; } else - *token += (BYTE)(length); + *token += len; /* Prepare next loop */ - *ip += matchLength; + *ip += ml; *anchor = *ip; return 0; } -static int LZ4HC_compress_generic( - LZ4HC_CCtx_internal *const ctx, - const char * const source, - char * const dest, - int const inputSize, - int const maxOutputSize, - int compressionLevel, - limitedOutput_directive limit - ) +static int lz4_compresshcctx(struct lz4hc_data *ctx, + const char *source, + char *dest, + int isize) { - const BYTE *ip = (const BYTE *) source; - const BYTE *anchor = ip; - const BYTE * const iend = ip + inputSize; - const BYTE * const mflimit = iend - MFLIMIT; - const BYTE * const matchlimit = (iend - LASTLITERALS); + const u8 *ip = (const u8 *)source; + const u8 *anchor = ip; + const u8 *const iend = ip + isize; + const u8 *const mflimit = iend - MFLIMIT; + const u8 *const matchlimit = (iend - LASTLITERALS); - BYTE *op = (BYTE *) dest; - BYTE * const oend = op + maxOutputSize; + u8 *op = (u8 *)dest; - unsigned int maxNbAttempts; int ml, ml2, ml3, ml0; - const BYTE *ref = NULL; - const BYTE *start2 = NULL; - const BYTE *ref2 = NULL; - const BYTE *start3 = NULL; - const BYTE *ref3 = NULL; - const BYTE *start0; - const BYTE *ref0; - - /* init */ - if (compressionLevel > LZ4HC_MAX_CLEVEL) - compressionLevel = LZ4HC_MAX_CLEVEL; - if (compressionLevel < 1) - compressionLevel = LZ4HC_DEFAULT_CLEVEL; - maxNbAttempts = 1 << (compressionLevel - 1); - ctx->end += inputSize; + const u8 *ref = NULL; + const u8 *start2 = NULL; + const u8 *ref2 = NULL; + const u8 *start3 = NULL; + const u8 *ref3 = NULL; + const u8 *start0; + const u8 *ref0; + int lastrun; ip++; /* Main Loop */ while (ip < mflimit) { - ml = LZ4HC_InsertAndFindBestMatch(ctx, ip, - matchlimit, (&ref), maxNbAttempts); + ml = lz4hc_insertandfindbestmatch(ctx, ip, matchlimit, (&ref)); if (!ml) { ip++; continue; @@ -387,59 +351,51 @@ static int LZ4HC_compress_generic( start0 = ip; ref0 = ref; ml0 = ml; - -_Search2: - if (ip + ml < mflimit) - ml2 = LZ4HC_InsertAndGetWiderMatch(ctx, - ip + ml - 2, ip + 0, - matchlimit, ml, &ref2, - &start2, maxNbAttempts); +_search2: + if (ip+ml < mflimit) + ml2 = lz4hc_insertandgetwidermatch(ctx, ip + ml - 2, + ip + 1, matchlimit, ml, &ref2, &start2); else ml2 = ml; - + /* No better match */ if (ml2 == ml) { - /* No better match */ - if (LZ4HC_encodeSequence(&ip, &op, - &anchor, ml, ref, limit, oend)) - return 0; + lz4_encodesequence(&ip, &op, &anchor, ml, ref); continue; } if (start0 < ip) { + /* empirical */ if (start2 < ip + ml0) { - /* empirical */ ip = start0; ref = ref0; ml = ml0; } } - - /* Here, start0 == ip */ + /* + * Here, start0==ip + * First Match too small : removed + */ if ((start2 - ip) < 3) { - /* First Match too small : removed */ ml = ml2; ip = start2; ref = ref2; - goto _Search2; + goto _search2; } -_Search3: +_search3: /* - * Currently we have : - * ml2 > ml1, and - * ip1 + 3 <= ip2 (usually < ip1 + ml1) - */ + * Currently we have : + * ml2 > ml1, and + * ip1+3 <= ip2 (usually < ip1+ml1) + */ if ((start2 - ip) < OPTIMAL_ML) { int correction; int new_ml = ml; - if (new_ml > OPTIMAL_ML) new_ml = OPTIMAL_ML; if (ip + new_ml > start2 + ml2 - MINMATCH) new_ml = (int)(start2 - ip) + ml2 - MINMATCH; - correction = new_ml - (int)(start2 - ip); - if (correction > 0) { start2 += correction; ref2 += correction; @@ -447,44 +403,39 @@ static int LZ4HC_compress_generic( } } /* - * Now, we have start2 = ip + new_ml, - * with new_ml = min(ml, OPTIMAL_ML = 18) + * Now, we have start2 = ip+new_ml, + * with new_ml=min(ml, OPTIMAL_ML=18) */ - if (start2 + ml2 < mflimit) - ml3 = LZ4HC_InsertAndGetWiderMatch(ctx, - start2 + ml2 - 3, start2, - matchlimit, ml2, &ref3, &start3, - maxNbAttempts); + ml3 = lz4hc_insertandgetwidermatch(ctx, + start2 + ml2 - 3, start2, matchlimit, + ml2, &ref3, &start3); else ml3 = ml2; + /* No better match : 2 sequences to encode */ if (ml3 == ml2) { - /* No better match : 2 sequences to encode */ /* ip & ref are known; Now for ml */ - if (start2 < ip + ml) + if (start2 < ip+ml) ml = (int)(start2 - ip); + /* Now, encode 2 sequences */ - if (LZ4HC_encodeSequence(&ip, &op, &anchor, - ml, ref, limit, oend)) - return 0; + lz4_encodesequence(&ip, &op, &anchor, ml, ref); ip = start2; - if (LZ4HC_encodeSequence(&ip, &op, &anchor, - ml2, ref2, limit, oend)) - return 0; + lz4_encodesequence(&ip, &op, &anchor, ml2, ref2); continue; } + /* Not enough space for match 2 : remove it */ if (start3 < ip + ml + 3) { - /* Not enough space for match 2 : remove it */ + /* + * can write Seq1 immediately ==> Seq2 is removed, + * so Seq3 becomes Seq1 + */ if (start3 >= (ip + ml)) { - /* can write Seq1 immediately - * ==> Seq2 is removed, - * so Seq3 becomes Seq1 - */ if (start2 < ip + ml) { - int correction = (int)(ip + ml - start2); - + int correction = + (int)(ip + ml - start2); start2 += correction; ref2 += correction; ml2 -= correction; @@ -495,38 +446,35 @@ static int LZ4HC_compress_generic( } } - if (LZ4HC_encodeSequence(&ip, &op, &anchor, - ml, ref, limit, oend)) - return 0; - ip = start3; + lz4_encodesequence(&ip, &op, &anchor, ml, ref); + ip = start3; ref = ref3; - ml = ml3; + ml = ml3; start0 = start2; ref0 = ref2; ml0 = ml2; - goto _Search2; + goto _search2; } start2 = start3; ref2 = ref3; ml2 = ml3; - goto _Search3; + goto _search3; } /* - * OK, now we have 3 ascending matches; - * let's write at least the first one - * ip & ref are known; Now for ml - */ + * OK, now we have 3 ascending matches; let's write at least + * the first one ip & ref are known; Now for ml + */ if (start2 < ip + ml) { if ((start2 - ip) < (int)ML_MASK) { int correction; - if (ml > OPTIMAL_ML) ml = OPTIMAL_ML; if (ip + ml > start2 + ml2 - MINMATCH) - ml = (int)(start2 - ip) + ml2 - MINMATCH; + ml = (int)(start2 - ip) + ml2 + - MINMATCH; correction = ml - (int)(start2 - ip); if (correction > 0) { start2 += correction; @@ -536,9 +484,7 @@ static int LZ4HC_compress_generic( } else ml = (int)(start2 - ip); } - if (LZ4HC_encodeSequence(&ip, &op, &anchor, ml, - ref, limit, oend)) - return 0; + lz4_encodesequence(&ip, &op, &anchor, ml, ref); ip = start2; ref = ref2; @@ -548,245 +494,46 @@ static int LZ4HC_compress_generic( ref2 = ref3; ml2 = ml3; - goto _Search3; + goto _search3; } /* Encode Last Literals */ - { - int lastRun = (int)(iend - anchor); - - if ((limit) - && (((char *)op - dest) + lastRun + 1 - + ((lastRun + 255 - RUN_MASK)/255) - > (U32)maxOutputSize)) { - /* Check output limit */ - return 0; - } - if (lastRun >= (int)RUN_MASK) { - *op++ = (RUN_MASK< 254 ; lastRun -= 255) - *op++ = 255; - *op++ = (BYTE) lastRun; - } else - *op++ = (BYTE)(lastRun<= (int)RUN_MASK) { + *op++ = (RUN_MASK << ML_BITS); + lastrun -= RUN_MASK; + for (; lastrun > 254 ; lastrun -= 255) + *op++ = 255; + *op++ = (u8) lastrun; + } else + *op++ = (lastrun << ML_BITS); + memcpy(op, anchor, iend - anchor); + op += iend - anchor; /* End */ return (int) (((char *)op) - dest); } -static int LZ4_compress_HC_extStateHC( - void *state, - const char *src, - char *dst, - int srcSize, - int maxDstSize, - int compressionLevel) -{ - LZ4HC_CCtx_internal *ctx = &((LZ4_streamHC_t *)state)->internal_donotuse; - - if (((size_t)(state)&(sizeof(void *) - 1)) != 0) { - /* Error : state is not aligned - * for pointers (32 or 64 bits) - */ - return 0; - } - - LZ4HC_init(ctx, (const BYTE *)src); - - if (maxDstSize < LZ4_compressBound(srcSize)) - return LZ4HC_compress_generic(ctx, src, dst, - srcSize, maxDstSize, compressionLevel, limitedOutput); - else - return LZ4HC_compress_generic(ctx, src, dst, - srcSize, maxDstSize, compressionLevel, noLimit); -} - -int LZ4_compress_HC(const char *src, char *dst, int srcSize, - int maxDstSize, int compressionLevel, void *wrkmem) -{ - return LZ4_compress_HC_extStateHC(wrkmem, src, dst, - srcSize, maxDstSize, compressionLevel); -} -EXPORT_SYMBOL(LZ4_compress_HC); - -/************************************** - * Streaming Functions - **************************************/ -void LZ4_resetStreamHC(LZ4_streamHC_t *LZ4_streamHCPtr, int compressionLevel) -{ - LZ4_streamHCPtr->internal_donotuse.base = NULL; - LZ4_streamHCPtr->internal_donotuse.compressionLevel = (unsigned int)compressionLevel; -} - -int LZ4_loadDictHC(LZ4_streamHC_t *LZ4_streamHCPtr, - const char *dictionary, - int dictSize) -{ - LZ4HC_CCtx_internal *ctxPtr = &LZ4_streamHCPtr->internal_donotuse; - - if (dictSize > 64 * KB) { - dictionary += dictSize - 64 * KB; - dictSize = 64 * KB; - } - LZ4HC_init(ctxPtr, (const BYTE *)dictionary); - if (dictSize >= 4) - LZ4HC_Insert(ctxPtr, (const BYTE *)dictionary + (dictSize - 3)); - ctxPtr->end = (const BYTE *)dictionary + dictSize; - return dictSize; -} -EXPORT_SYMBOL(LZ4_loadDictHC); - -/* compression */ - -static void LZ4HC_setExternalDict( - LZ4HC_CCtx_internal *ctxPtr, - const BYTE *newBlock) -{ - if (ctxPtr->end >= ctxPtr->base + 4) { - /* Referencing remaining dictionary content */ - LZ4HC_Insert(ctxPtr, ctxPtr->end - 3); - } - - /* - * Only one memory segment for extDict, - * so any previous extDict is lost at this stage - */ - ctxPtr->lowLimit = ctxPtr->dictLimit; - ctxPtr->dictLimit = (U32)(ctxPtr->end - ctxPtr->base); - ctxPtr->dictBase = ctxPtr->base; - ctxPtr->base = newBlock - ctxPtr->dictLimit; - ctxPtr->end = newBlock; - /* match referencing will resume from there */ - ctxPtr->nextToUpdate = ctxPtr->dictLimit; -} -EXPORT_SYMBOL(LZ4HC_setExternalDict); - -static int LZ4_compressHC_continue_generic( - LZ4_streamHC_t *LZ4_streamHCPtr, - const char *source, - char *dest, - int inputSize, - int maxOutputSize, - limitedOutput_directive limit) -{ - LZ4HC_CCtx_internal *ctxPtr = &LZ4_streamHCPtr->internal_donotuse; - - /* auto - init if forgotten */ - if (ctxPtr->base == NULL) - LZ4HC_init(ctxPtr, (const BYTE *) source); - - /* Check overflow */ - if ((size_t)(ctxPtr->end - ctxPtr->base) > 2 * GB) { - size_t dictSize = (size_t)(ctxPtr->end - ctxPtr->base) - - ctxPtr->dictLimit; - if (dictSize > 64 * KB) - dictSize = 64 * KB; - LZ4_loadDictHC(LZ4_streamHCPtr, - (const char *)(ctxPtr->end) - dictSize, (int)dictSize); - } - - /* Check if blocks follow each other */ - if ((const BYTE *)source != ctxPtr->end) - LZ4HC_setExternalDict(ctxPtr, (const BYTE *)source); - - /* Check overlapping input/dictionary space */ - { - const BYTE *sourceEnd = (const BYTE *) source + inputSize; - const BYTE * const dictBegin = ctxPtr->dictBase + ctxPtr->lowLimit; - const BYTE * const dictEnd = ctxPtr->dictBase + ctxPtr->dictLimit; - - if ((sourceEnd > dictBegin) - && ((const BYTE *)source < dictEnd)) { - if (sourceEnd > dictEnd) - sourceEnd = dictEnd; - ctxPtr->lowLimit = (U32)(sourceEnd - ctxPtr->dictBase); - - if (ctxPtr->dictLimit - ctxPtr->lowLimit < 4) - ctxPtr->lowLimit = ctxPtr->dictLimit; - } - } - - return LZ4HC_compress_generic(ctxPtr, source, dest, - inputSize, maxOutputSize, ctxPtr->compressionLevel, limit); -} - -int LZ4_compress_HC_continue( - LZ4_streamHC_t *LZ4_streamHCPtr, - const char *source, - char *dest, - int inputSize, - int maxOutputSize) -{ - if (maxOutputSize < LZ4_compressBound(inputSize)) - return LZ4_compressHC_continue_generic(LZ4_streamHCPtr, - source, dest, inputSize, maxOutputSize, limitedOutput); - else - return LZ4_compressHC_continue_generic(LZ4_streamHCPtr, - source, dest, inputSize, maxOutputSize, noLimit); -} -EXPORT_SYMBOL(LZ4_compress_HC_continue); - -/* dictionary saving */ - -int LZ4_saveDictHC( - LZ4_streamHC_t *LZ4_streamHCPtr, - char *safeBuffer, - int dictSize) +int lz4hc_compress(const unsigned char *src, size_t src_len, + unsigned char *dst, size_t *dst_len, void *wrkmem) { - LZ4HC_CCtx_internal *const streamPtr = &LZ4_streamHCPtr->internal_donotuse; - int const prefixSize = (int)(streamPtr->end - - (streamPtr->base + streamPtr->dictLimit)); + int ret = -1; + int out_len = 0; - if (dictSize > 64 * KB) - dictSize = 64 * KB; - if (dictSize < 4) - dictSize = 0; - if (dictSize > prefixSize) - dictSize = prefixSize; + struct lz4hc_data *hc4 = (struct lz4hc_data *)wrkmem; + lz4hc_init(hc4, (const u8 *)src); + out_len = lz4_compresshcctx((struct lz4hc_data *)hc4, (const u8 *)src, + (char *)dst, (int)src_len); - memmove(safeBuffer, streamPtr->end - dictSize, dictSize); + if (out_len < 0) + goto exit; - { - U32 const endIndex = (U32)(streamPtr->end - streamPtr->base); - - streamPtr->end = (const BYTE *)safeBuffer + dictSize; - streamPtr->base = streamPtr->end - endIndex; - streamPtr->dictLimit = endIndex - dictSize; - streamPtr->lowLimit = endIndex - dictSize; - - if (streamPtr->nextToUpdate < streamPtr->dictLimit) - streamPtr->nextToUpdate = streamPtr->dictLimit; - } - return dictSize; -} -EXPORT_SYMBOL(LZ4_saveDictHC); + *dst_len = out_len; + return 0; -/*-****************************** - * For backwards compatibility - ********************************/ -int lz4hc_compress(const unsigned char *src, size_t src_len, - unsigned char *dst, size_t *dst_len, void *wrkmem) -{ - *dst_len = LZ4_compress_HC(src, dst, src_len, - *dst_len, LZ4HC_DEFAULT_CLEVEL, wrkmem); - - /* - * Prior lz4hc_compress will return -1 in case of error - * and 0 on success - * while new LZ4_compress_HC - * returns 0 in case of error - * and the output length on success - */ - if (!*dst_len) - return -1; - else - return 0; +exit: + return ret; } EXPORT_SYMBOL(lz4hc_compress); MODULE_LICENSE("Dual BSD/GPL"); -MODULE_DESCRIPTION("LZ4 HC compressor"); +MODULE_DESCRIPTION("LZ4HC compressor"); diff --git a/mm/compaction.c b/mm/compaction.c index de2218a5f1b9..4959b2a1aeb7 100644 --- a/mm/compaction.c +++ b/mm/compaction.c @@ -1694,7 +1694,7 @@ static enum compact_result compact_zone_order(struct zone *zone, int order, return ret; } -int sysctl_extfrag_threshold = 750; +int sysctl_extfrag_threshold = 500; /** * try_to_compact_pages - Direct compact to satisfy a high-order allocation diff --git a/mm/page-writeback.c b/mm/page-writeback.c index ad8b80dfa80d..21a12577b287 100644 --- a/mm/page-writeback.c +++ b/mm/page-writeback.c @@ -87,7 +87,7 @@ int vm_highmem_is_dirtyable; /* * The generator of dirty data starts writeback at this percentage */ -int vm_dirty_ratio = 80; +int vm_dirty_ratio = 20; /* * vm_dirty_bytes starts at 0 (disabled) so that it is a function of diff --git a/mm/vmscan.c b/mm/vmscan.c index 7d7d1a928ea4..b3c44fc17861 100644 --- a/mm/vmscan.c +++ b/mm/vmscan.c @@ -47,7 +47,6 @@ #include #include #include -#include #include #include @@ -3327,8 +3326,6 @@ static int balance_pgdat(pg_data_t *pgdat, int order, int classzone_idx) sc.reclaim_idx = classzone_idx; - simple_lmk_decide_reclaim(sc.priority); - /* * If the number of buffer_heads exceeds the maximum allowed * then consider reclaiming from all zones. This has a dual @@ -3459,7 +3456,6 @@ static void kswapd_try_to_sleep(pg_data_t *pgdat, int alloc_order, int reclaim_o * succeed. */ if (prepare_kswapd_sleep(pgdat, reclaim_order, classzone_idx)) { - simple_lmk_stop_reclaim(); /* * Compaction records what page blocks it recently failed to * isolate pages from and skips them in the future scanning. @@ -3496,7 +3492,6 @@ static void kswapd_try_to_sleep(pg_data_t *pgdat, int alloc_order, int reclaim_o */ if (!remaining && prepare_kswapd_sleep(pgdat, reclaim_order, classzone_idx)) { - simple_lmk_stop_reclaim(); trace_mm_vmscan_kswapd_sleep(pgdat->node_id); /* diff --git a/mm/vmstat.c b/mm/vmstat.c index e8a855287001..67c229324086 100644 --- a/mm/vmstat.c +++ b/mm/vmstat.c @@ -1699,7 +1699,7 @@ static void vmstat_shepherd(struct work_struct *w) } put_online_cpus(); - queue_delayed_work(system_power_efficient_wq, &shepherd, + schedule_delayed_work(&shepherd, round_jiffies_relative(sysctl_stat_interval)); } @@ -1712,7 +1712,7 @@ static void __init start_shepherd_timer(void) vmstat_update); vmstat_wq = alloc_workqueue("vmstat", WQ_FREEZABLE|WQ_MEM_RECLAIM, 0); - queue_delayed_work(system_power_efficient_wq, &shepherd, + schedule_delayed_work(&shepherd, round_jiffies_relative(sysctl_stat_interval)); } diff --git a/net/ipc_router/ipc_router_security.c b/net/ipc_router/ipc_router_security.c index 1359d642b182..33a34bb4f56d 100644 --- a/net/ipc_router/ipc_router_security.c +++ b/net/ipc_router/ipc_router_security.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2014,2016 The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2014,2016,2020, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/net/ipv4/af_inet.c b/net/ipv4/af_inet.c index 275ef1354670..a72639889642 100644 --- a/net/ipv4/af_inet.c +++ b/net/ipv4/af_inet.c @@ -89,7 +89,6 @@ #include #include #include -#include #include @@ -415,9 +414,6 @@ int inet_release(struct socket *sock) if (sk) { long timeout; -#ifdef CONFIG_NETFILTER_XT_MATCH_QTAGUID - qtaguid_untag(sock, true); -#endif /* Applications forget to leave groups before exiting */ ip_mc_drop_socket(sk); diff --git a/net/ipv4/tcp_westwood.c b/net/ipv4/tcp_westwood.c index ff556c0e7b92..4b03a2e2a050 100644 --- a/net/ipv4/tcp_westwood.c +++ b/net/ipv4/tcp_westwood.c @@ -43,8 +43,8 @@ struct westwood { }; /* TCP Westwood functions and constants */ -#define TCP_WESTWOOD_RTT_MIN (HZ/18) /* 55.55ms */ -#define TCP_WESTWOOD_INIT_RTT (18*HZ) /* maybe too conservative?! */ +#define TCP_WESTWOOD_RTT_MIN (HZ/20) /* 50ms */ +#define TCP_WESTWOOD_INIT_RTT (20*HZ) /* maybe too conservative?! */ /* * @tcp_westwood_create @@ -68,7 +68,7 @@ static void tcp_westwood_init(struct sock *sk) w->cumul_ack = 0; w->reset_rtt_min = 1; w->rtt_min = w->rtt = TCP_WESTWOOD_INIT_RTT; - w->rtt_win_sx = tcp_jiffies32; + w->rtt_win_sx = tcp_time_stamp; w->snd_una = tcp_sk(sk)->snd_una; w->first_ack = 1; } @@ -116,7 +116,7 @@ static void tcp_westwood_pkts_acked(struct sock *sk, static void westwood_update_window(struct sock *sk) { struct westwood *w = inet_csk_ca(sk); - s32 delta = tcp_jiffies32 - w->rtt_win_sx; + s32 delta = tcp_time_stamp - w->rtt_win_sx; /* Initialize w->snd_una with the first acked sequence number in order * to fix mismatch between tp->snd_una and w->snd_una for the first @@ -140,7 +140,7 @@ static void westwood_update_window(struct sock *sk) westwood_filter(w, delta); w->bk = 0; - w->rtt_win_sx = tcp_jiffies32; + w->rtt_win_sx = tcp_time_stamp; } } diff --git a/net/wireless/util.c b/net/wireless/util.c index 204a1a1988ad..a43d62e5bef1 100644 --- a/net/wireless/util.c +++ b/net/wireless/util.c @@ -1764,3 +1764,54 @@ void cfg80211_send_layer2_update(struct net_device *dev, const u8 *addr) netif_rx_ni(skb); } EXPORT_SYMBOL(cfg80211_send_layer2_update); + +bool cfg80211_is_gratuitous_arp_unsolicited_na(struct sk_buff *skb) +{ + const struct ethhdr *eth = (void *)skb->data; + const struct { + struct arphdr hdr; + u8 ar_sha[ETH_ALEN]; + u8 ar_sip[4]; + u8 ar_tha[ETH_ALEN]; + u8 ar_tip[4]; + } __packed *arp; + const struct ipv6hdr *ipv6; + const struct icmp6hdr *icmpv6; + + switch (eth->h_proto) { + case cpu_to_be16(ETH_P_ARP): + /* can't say - but will probably be dropped later anyway */ + if (!pskb_may_pull(skb, sizeof(*eth) + sizeof(*arp))) + return false; + + arp = (void *)(eth + 1); + + if ((arp->hdr.ar_op == cpu_to_be16(ARPOP_REPLY) || + arp->hdr.ar_op == cpu_to_be16(ARPOP_REQUEST)) && + !memcmp(arp->ar_sip, arp->ar_tip, sizeof(arp->ar_sip))) + return true; + break; + case cpu_to_be16(ETH_P_IPV6): + /* can't say - but will probably be dropped later anyway */ + if (!pskb_may_pull(skb, sizeof(*eth) + sizeof(*ipv6) + + sizeof(*icmpv6))) + return false; + + ipv6 = (void *)(eth + 1); + icmpv6 = (void *)(ipv6 + 1); + + if (icmpv6->icmp6_type == NDISC_NEIGHBOUR_ADVERTISEMENT && + !memcmp(&ipv6->saddr, &ipv6->daddr, sizeof(ipv6->saddr))) + return true; + break; + default: + /* + * no need to support other protocols, proxy service isn't + * specified for any others + */ + break; + } + + return false; +} +EXPORT_SYMBOL(cfg80211_is_gratuitous_arp_unsolicited_na); diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index fca738029ffe..a70b4d9ea3f7 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -314,6 +314,12 @@ cmd_dt_S_dtb= \ $(obj)/%.dtb.S: $(obj)/%.dtb $(call cmd,dt_S_dtb) +ifneq ($(DTC_EXT),) +DTC = $(DTC_EXT) +else +DTC = $(objtree)/scripts/dtc/dtc +endif + quiet_cmd_dtc = DTC $@ cmd_dtc = mkdir -p $(dir ${dtc-tmp}) ; \ $(CPP) $(dtc_cpp_flags) -x assembler-with-cpp -o $(dtc-tmp) $< ; \ diff --git a/scripts/dtc/Makefile b/scripts/dtc/Makefile index 2a48022c41e7..2eb4aec040f4 100644 --- a/scripts/dtc/Makefile +++ b/scripts/dtc/Makefile @@ -1,7 +1,9 @@ # scripts/dtc makefile hostprogs-y := dtc +ifeq ($(DTC_EXT),) always := $(hostprogs-y) +endif dtc-objs := dtc.o flattree.o fstree.o data.o livetree.o treesource.o \ srcpos.o checks.o util.o diff --git a/scripts/dtc/libfdt/fdt.c b/scripts/dtc/libfdt/fdt.c index 7855a1787763..9af0733d1837 100644 --- a/scripts/dtc/libfdt/fdt.c +++ b/scripts/dtc/libfdt/fdt.c @@ -71,6 +71,20 @@ int fdt_check_header(const void *fdt) return -FDT_ERR_BADMAGIC; } + if (fdt_off_dt_struct(fdt) > (UINT_MAX - fdt_size_dt_struct(fdt))) + return FDT_ERR_BADOFFSET; + + if (fdt_off_dt_strings(fdt) > (UINT_MAX - fdt_size_dt_strings(fdt))) + return FDT_ERR_BADOFFSET; + + if ((fdt_off_dt_struct(fdt) + fdt_size_dt_struct(fdt)) + > fdt_totalsize(fdt)) + return FDT_ERR_BADOFFSET; + + if ((fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt)) + > fdt_totalsize(fdt)) + return FDT_ERR_BADOFFSET; + return 0; } diff --git a/scripts/dtc/libfdt/fdt_rw.c b/scripts/dtc/libfdt/fdt_rw.c index 9b829051e444..26d5755a97d3 100644 --- a/scripts/dtc/libfdt/fdt_rw.c +++ b/scripts/dtc/libfdt/fdt_rw.c @@ -407,7 +407,7 @@ int fdt_del_node(void *fdt, int nodeoffset) static void fdt_packblocks_(const char *old, char *new, int mem_rsv_size, int struct_size) { - int mem_rsv_off, struct_off, strings_off; + uint32_t mem_rsv_off, struct_off, strings_off; mem_rsv_off = FDT_ALIGN(sizeof(struct fdt_header), 8); struct_off = mem_rsv_off + mem_rsv_size; diff --git a/scripts/gcc-wrapper.py b/scripts/gcc-wrapper.py deleted file mode 100755 index 3d1d6fbcaa04..000000000000 --- a/scripts/gcc-wrapper.py +++ /dev/null @@ -1,95 +0,0 @@ -#! /usr/bin/env python2 -# -*- coding: utf-8 -*- - -# Copyright (c) 2011-2017, The Linux Foundation. All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# * Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# * Neither the name of The Linux Foundation nor -# the names of its contributors may be used to endorse or promote -# products derived from this software without specific prior written -# permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -# NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR -# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; -# OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR -# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -# Invoke gcc, looking for warnings, and causing a failure if there are -# non-whitelisted warnings. - -import errno -import re -import os -import sys -import subprocess - -# Note that gcc uses unicode, which may depend on the locale. TODO: -# force LANG to be set to en_US.UTF-8 to get consistent warnings. - -allowed_warnings = set([ - ]) - -# Capture the name of the object file, can find it. -ofile = None - -warning_re = re.compile(r'''(.*/|)([^/]+\.[a-z]+:\d+):(\d+:)? warning:''') -def interpret_warning(line): - """Decode the message from gcc. The messages we care about have a filename, and a warning""" - line = line.rstrip('\n') - m = warning_re.match(line) - if m and m.group(2) not in allowed_warnings: - print >> sys.stderr, "error, forbidden warning:", m.group(2) - - # If there is a warning, remove any object if it exists. - if ofile: - try: - os.remove(ofile) - except OSError: - pass - sys.exit(1) - -def run_gcc(): - args = sys.argv[1:] - # Look for -o - try: - i = args.index('-o') - global ofile - ofile = args[i+1] - except (ValueError, IndexError): - pass - - compiler = sys.argv[0] - - try: - proc = subprocess.Popen(args, stderr=subprocess.PIPE) - for line in proc.stderr: - print >> sys.stderr, line, - interpret_warning(line) - - result = proc.wait() - except OSError as e: - result = e.errno - if result == errno.ENOENT: - print >> sys.stderr, args[0] + ':',e.strerror - print >> sys.stderr, 'Is your PATH set correctly?' - else: - print >> sys.stderr, ' '.join(args), str(e) - - return result - -if __name__ == '__main__': - status = run_gcc() - sys.exit(status) diff --git a/scripts/setlocalversion b/scripts/setlocalversion index e6c5c9ce7f9c..aa28c3f29809 100755 --- a/scripts/setlocalversion +++ b/scripts/setlocalversion @@ -106,7 +106,7 @@ scm_version() # Are there uncommitted changes? # These are represented by + after the changeset id. case "$hgid" in - *+|*+\ *) printf '%s';; + *+|*+\ *) printf '%s' -dirty ;; esac # All done with mercurial @@ -175,6 +175,7 @@ else # LOCALVERSION= is not specified if test "${LOCALVERSION+set}" != "set"; then scm=$(scm_version --short) + res="$res${scm:++}" fi fi diff --git a/security/selinux/avc.c b/security/selinux/avc.c index 84d9a2e2bbaf..f11a4abe18fc 100644 --- a/security/selinux/avc.c +++ b/security/selinux/avc.c @@ -867,7 +867,7 @@ static int avc_update_node(u32 event, u32 perms, u8 driver, u8 xperm, u32 ssid, if (orig->ae.xp_node) { rc = avc_xperms_populate(node, orig->ae.xp_node); if (rc) { - kmem_cache_free(avc_node_cachep, node); + avc_node_kill(node); goto out_unlock; } } diff --git a/security/selinux/include/classmap.h b/security/selinux/include/classmap.h index 963ff8009dcc..1764b221d545 100644 --- a/security/selinux/include/classmap.h +++ b/security/selinux/include/classmap.h @@ -105,7 +105,7 @@ struct security_class_mapping secclass_map[] = { { COMMON_IPC_PERMS, NULL } }, { "netlink_route_socket", { COMMON_SOCK_PERMS, - "nlmsg_read", "nlmsg_write", NULL } }, + "nlmsg_read", "nlmsg_write", "nlmsg_readpriv", NULL } }, { "netlink_tcpdiag_socket", { COMMON_SOCK_PERMS, "nlmsg_read", "nlmsg_write", NULL } }, diff --git a/security/selinux/include/security.h b/security/selinux/include/security.h index b8e98c111b2f..576d5a8c9238 100644 --- a/security/selinux/include/security.h +++ b/security/selinux/include/security.h @@ -74,6 +74,7 @@ enum { }; #define POLICYDB_CAPABILITY_MAX (__POLICYDB_CAPABILITY_MAX - 1) +extern int selinux_android_netlink_route; extern int selinux_policycap_netpeer; extern int selinux_policycap_openperm; extern int selinux_policycap_alwaysnetwork; @@ -262,6 +263,7 @@ extern struct vfsmount *selinuxfs_mount; extern void selnl_notify_setenforce(int val); extern void selnl_notify_policyload(u32 seqno); extern int selinux_nlmsg_lookup(u16 sclass, u16 nlmsg_type, u32 *perm); +extern void selinux_nlmsg_init(void); #endif /* _SELINUX_SECURITY_H_ */ diff --git a/security/selinux/nlmsgtab.c b/security/selinux/nlmsgtab.c index 2ca9cde939d4..697785cec7f6 100644 --- a/security/selinux/nlmsgtab.c +++ b/security/selinux/nlmsgtab.c @@ -193,3 +193,27 @@ int selinux_nlmsg_lookup(u16 sclass, u16 nlmsg_type, u32 *perm) return err; } + +static void nlmsg_set_getlink_perm(u32 perm) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(nlmsg_route_perms); i++) { + if (nlmsg_route_perms[i].nlmsg_type == RTM_GETLINK) { + nlmsg_route_perms[i].perm = perm; + break; + } + } +} + +/** + * Use nlmsg_readpriv as the permission for RTM_GETLINK messages if the + * netlink_route_getlink policy capability is set. Otherwise use nlmsg_read. + */ +void selinux_nlmsg_init(void) +{ + if (selinux_android_netlink_route) + nlmsg_set_getlink_perm(NETLINK_ROUTE_SOCKET__NLMSG_READPRIV); + else + nlmsg_set_getlink_perm(NETLINK_ROUTE_SOCKET__NLMSG_READ); +} diff --git a/security/selinux/ss/policydb.c b/security/selinux/ss/policydb.c index af9cc839856f..62518b031e5e 100644 --- a/security/selinux/ss/policydb.c +++ b/security/selinux/ss/policydb.c @@ -2332,6 +2332,10 @@ int policydb_read(struct policydb *p, void *fp) p->reject_unknown = !!(le32_to_cpu(buf[1]) & REJECT_UNKNOWN); p->allow_unknown = !!(le32_to_cpu(buf[1]) & ALLOW_UNKNOWN); + if ((le32_to_cpu(buf[1]) & POLICYDB_CONFIG_ANDROID_NETLINK_ROUTE)) { + p->android_netlink_route = 1; + } + if (p->policyvers >= POLICYDB_VERSION_POLCAP) { rc = ebitmap_read(&p->policycaps, fp); if (rc) diff --git a/security/selinux/ss/policydb.h b/security/selinux/ss/policydb.h index 725d5945a97e..0d511cf3c1e9 100644 --- a/security/selinux/ss/policydb.h +++ b/security/selinux/ss/policydb.h @@ -227,6 +227,7 @@ struct genfs { /* The policy database */ struct policydb { int mls_enabled; + int android_netlink_route; /* symbol tables */ struct symtab symtab[SYM_NUM]; @@ -313,6 +314,7 @@ extern int policydb_write(struct policydb *p, void *fp); #define PERM_SYMTAB_SIZE 32 #define POLICYDB_CONFIG_MLS 1 +#define POLICYDB_CONFIG_ANDROID_NETLINK_ROUTE (1 << 31) /* the config flags related to unknown classes/perms are bits 2 and 3 */ #define REJECT_UNKNOWN 0x00000002 diff --git a/security/selinux/ss/services.c b/security/selinux/ss/services.c index a6b097098aba..b96d4466de4c 100644 --- a/security/selinux/ss/services.c +++ b/security/selinux/ss/services.c @@ -70,6 +70,7 @@ #include "ebitmap.h" #include "audit.h" +int selinux_android_netlink_route; int selinux_policycap_netpeer; int selinux_policycap_openperm; int selinux_policycap_alwaysnetwork; @@ -1990,6 +1991,9 @@ static void security_load_policycaps(void) POLICYDB_CAPABILITY_OPENPERM); selinux_policycap_alwaysnetwork = ebitmap_get_bit(&policydb.policycaps, POLICYDB_CAPABILITY_ALWAYSNETWORK); + + selinux_android_netlink_route = policydb.android_netlink_route; + selinux_nlmsg_init(); } static int security_preserve_bools(struct policydb *p); diff --git a/sound/soc/msm/Kconfig b/sound/soc/msm/Kconfig deleted file mode 100644 index 1f2f3d545eb8..000000000000 --- a/sound/soc/msm/Kconfig +++ /dev/null @@ -1,261 +0,0 @@ -menu "MSM SoC Audio support" - -config SND_SOC_MSM_HOSTLESS_PCM - tristate - -config SND_SOC_MSM_QDSP6V2_INTF - bool "SoC Q6 audio driver for APQ8084" - help - To add support for SoC audio on APQ8084. - This will enable all the platform specific - interactions towards DSP. It includes asm, - adm and afe interfaces on the DSP. - -config SND_SOC_QDSP6V2 - tristate "SoC ALSA audio driver for QDSP6V2" - select SND_SOC_MSM_QDSP6V2_INTF - help - To add support for MSM QDSP6V2 Soc Audio. - This will enable sound soc platform specific - audio drivers. This includes q6asm, q6adm, - q6afe interfaces to DSP using apr. - -config SND_SOC_QDSP_DEBUG - bool "QDSP Audio Driver Debug Feature" - help - Configuration to enable debugging utilities for - QDSP6 based audio drivers. One debugging utility - is inducing kernel panic upon encountering critical - errors from DSP audio modules - -config DOLBY_DAP - bool "Enable Dolby DAP" - depends on SND_SOC_MSM_QDSP6V2_INTF - help - To add support for dolby DAP post processing. - This support is to configure the post processing parameters - to DSP. The configuration includes sending the end point - device, end point dependent post processing parameters and - the various posrt processing parameters - -config DOLBY_LICENSE - bool "Enable Dolby LICENSE" - depends on SND_SOC_MSM_QDSP6V2_INTF - help - To add support for dolby DAP post processing, - and retain DAP set license functionality only. - This is required by Dolby GEF implementation which needs - nothing but dolby license validation functionality in driver. - -config DTS_SRS_TM - bool "Enable DTS SRS" - depends on SND_SOC_MSM_QDSP6V2_INTF - help - To add support for DTS SRS post processing. - This support is to configure the post processing - parameters to DSP. The configuration includes sending - tuning parameters of various modules. - -config QTI_PP - bool "Enable QTI PP" - depends on SND_SOC_MSM_QDSP6V2_INTF - help - To add support for default QTI post processing. - This support is to configure the post processing - parameters to DSP. The configuration includes sending - tuning parameters of various modules such as equalizer, - customized mixing. - -config SND_SOC_CPE - tristate "CPE drivers" - depends on SND_SOC_WCD_CPE - help - To add support for Codec Processing Engine. This support - is to enable CPE block on the codec and this config needs - to be added to codecs that contain the CPE hardware block. - The configuration includes the cpe lsm driver to enable - listen on codec. - -config SND_SOC_APQ8084 - tristate "SoC Machine driver for APQ8084 boards" - depends on ARCH_APQ8084 - select SND_SOC_QDSP6V2 - select SND_SOC_MSM_STUB - select SND_SOC_MSM_HOSTLESS_PCM - select SND_SOC_WCD9330 - select SND_SOC_WCD9320 - select SND_DYNAMIC_MINORS - select DOLBY_DAP - select DTS_SRS_TM - select QTI_PP - select SND_SOC_CPE - select DOLBY_DS2 - select SND_HWDEP - help - To add support for SoC audio on APQ8084. - This will enable sound soc drivers which - interfaces with DSP, also it will enable - the machine drivers and the corresponding - DAI-links. - -config SND_SOC_MSM8994 - tristate "SoC Machine driver for MSM8994 boards" - depends on ARCH_MSM8994 - select SND_SOC_QDSP6V2 - select SND_SOC_MSM_STUB - select SND_SOC_MSM_HOSTLESS_PCM - select SND_DYNAMIC_MINORS - select MSM_QDSP6_APRV2 - select MSM_QDSP6V2_CODECS - select SND_SOC_WCD9330 - select SND_SOC_MSM_HDMI_CODEC_RX - select QTI_PP - select DTS_SRS_TM - select SND_SOC_CPE - select MSM_ULTRASOUND - select DOLBY_DS2 - select SND_HWDEP - help - To add support for SoC audio on MSM8994. - This will enable sound soc drivers which - interfaces with DSP, also it will enable - the machine drivers and the corresponding - DAI-links. - -config SND_SOC_MSM8996 - tristate "SoC Machine driver for MSM8996 boards" - depends on ARCH_MSM8996 - select SND_SOC_QDSP6V2 - select SND_SOC_MSM_STUB - select SND_SOC_MSM_HOSTLESS_PCM - select SND_DYNAMIC_MINORS - select MSM_QDSP6_APRV2 - select MSM_QDSP6V2_CODECS - select SND_SOC_WCD9330 - select SND_SOC_WCD9335 - select SND_SOC_WSA881X - select SND_SOC_MSM_HDMI_CODEC_RX - select DTS_SRS_TM - select QTI_PP - select SND_SOC_CPE - select MSM_ULTRASOUND - select DOLBY_DS2 - select SND_HWDEP - help - To add support for SoC audio on MSM8996. - This will enable sound soc drivers which - interfaces with DSP, also it will enable - the machine driver and the corresponding - DAI-links - -config SND_SOC_MSM8X16 - tristate "SoC Machine driver for MSM8916" - depends on ARCH_MSM8953 || ARCH_MSM8937 - select SND_SOC_QDSP6V2 - select SND_SOC_MSM_STUB - select SND_SOC_MSM_HOSTLESS_PCM - select SND_DYNAMIC_MINORS - select MSM_QDSP6_APRV2 - select MSM_QDSP6V2_CODECS - select SND_SOC_WCD9330 - select SND_SOC_WCD9335 - select SND_SOC_MSM8X16_WCD - select SND_SOC_WSA881X_ANALOG - select SND_SOC_WSA881X - select MFD_CORE - select QTI_PP - select DTS_SRS_TM - select DOLBY_DAP - select DOLBY_DS2 - select SND_SOC_CPE - select SND_SOC_WCD_CPE - select SND_SOC_MSM_HDMI_DBA_CODEC_RX - select SND_HWDEP - help - To add support for SoC audio on MSM8996. - This will enable sound soc drivers which - interfaces with DSP, also it will enable - the machine driver and the corresponding - DAI-links - -config SND_SOC_MDM9650 - tristate "SoC Machine driver for MDM9650 or SDX20 boards" - depends on ARCH_MDM9650 || ARCH_SDX20 - select SND_SOC_QDSP6V2 - select SND_SOC_MSM_STUB - select SND_SOC_MSM_HOSTLESS_PCM - select SND_DYNAMIC_MINORS - select MSM_QDSP6_APRV3_GLINK - select MSM_QDSP6V2_CODECS - select SND_SOC_WCD9335 - select SND_SOC_WSA881X - select SND_SOC_TLV320AIC3X - select SND_HWDEP - help - To add support for SoC audio on MDM9650 or SDX20. - This will enable sound soc drivers which - interfaces with DSP, also it will enable - the machine driver and the corresponding - DAI-links - -config SND_SOC_MDM9607 - tristate "SoC Machine driver for MDM9607 boards" - depends on ARCH_MDM9607 - select SND_SOC_QDSP6V2 - select SND_SOC_MSM_STUB - select SND_SOC_WCD9330 - select SND_SOC_WCD9306 - select SND_SOC_MSM_HOSTLESS_PCM - select SND_DYNAMIC_MINORS - select MSM_QDSP6_APRV3 - select MSM_QDSP6V2_CODECS - select SND_HWDEP - help - To add support for SoC audio on MDM9607 boards. - This will enable sound soc drivers which - interfaces with DSP, also it will enable - the machine drivers and the corresponding - DAI-links. - -config SND_SOC_MSM8909 - tristate "SoC Machine driver for MSM8909 boards" - depends on ARCH_MSM8909 - select SND_SOC_QDSP6V2 - select SND_SOC_MSM_STUB - select SND_SOC_MSM_HOSTLESS_PCM - select SND_DYNAMIC_MINORS - select MSM_QDSP6_APRV3 - select MSM_QDSP6V2_CODECS - select SND_SOC_MSM8X16_WCD - select SND_SOC_WSA881X_ANALOG - select SND_SOC_WSA881X - select SND_SOC_WCD9335 - select SND_SOC_CPE - select SND_HWDEP - select QTI_PP - help - To add support for SoC audio on MSM8909 boards. - This will enable sound soc drivers which - interfaces with DSP, also it will enable - the machine drivers and the corresponding - DAI-links. - -config SND_SOC_MDM9640 - tristate "SoC Machine driver for MDM9640 boards" - depends on ARCH_MDM9640 - select SND_SOC_QDSP6V2 - select SND_SOC_MSM_STUB - select SND_SOC_WCD9330 - select SND_SOC_MSM_HOSTLESS_PCM - select SND_DYNAMIC_MINORS - select MSM_QDSP6_APRV3 - select MSM_QDSP6V2_CODECS - select SND_HWDEP - help - To add support for SoC audio on MDM9640 boards. - This will enable sound soc drivers which - interfaces with DSP, also it will enable - the machine drivers and the corresponding - DAI-links. - -endmenu diff --git a/techpack/audio/asoc/codecs/Makefile b/techpack/audio/asoc/codecs/Makefile index e76d2141bc58..8a6f8d420071 100644 --- a/techpack/audio/asoc/codecs/Makefile +++ b/techpack/audio/asoc/codecs/Makefile @@ -18,7 +18,7 @@ obj-$(CONFIG_SND_SOC_WCD9335) += snd-soc-wcd9335.o obj-$(CONFIG_SND_SOC_WCD_CPE) += snd-soc-wcd-cpe.o obj-$(CONFIG_SND_SOC_WCD934X) += wcd934x/ obj-$(CONFIG_SND_SOC_TAS2557) += tas2557/ -obj-$(CONFIG_SND_SOC_TAS2559) += tas2559/ +obj-$(CONFIG_SND_SOC_TAS2559) += tas2559/ obj-$(CONFIG_SND_SOC_SDM660_CDC) += sdm660_cdc/ obj-$(CONFIG_SND_SOC_MSM_SDW) += msm_sdw/ diff --git a/techpack/audio/asoc/codecs/tas2557/Makefile b/techpack/audio/asoc/codecs/tas2557/Makefile old mode 100755 new mode 100644 diff --git a/techpack/audio/asoc/codecs/tas2557/tas2557-codec.c b/techpack/audio/asoc/codecs/tas2557/tas2557-codec.c index 8974135bdf88..e4e194f4107d 100644 --- a/techpack/audio/asoc/codecs/tas2557/tas2557-codec.c +++ b/techpack/audio/asoc/codecs/tas2557/tas2557-codec.c @@ -1,7 +1,6 @@ /* ** ============================================================================= ** Copyright (c) 2016 Texas Instruments Inc. -** Copyright (C) 2019 XiaoMi, Inc. ** ** This program is free software; you can redistribute it and/or modify it under ** the terms of the GNU General Public License as published by the Free Software @@ -45,6 +44,7 @@ #include #include #include +#include #include "tas2557-core.h" #include "tas2557-codec.h" diff --git a/techpack/audio/asoc/codecs/tas2557/tas2557-codec.h b/techpack/audio/asoc/codecs/tas2557/tas2557-codec.h old mode 100755 new mode 100644 index 20babdde5025..8e20270c6b92 --- a/techpack/audio/asoc/codecs/tas2557/tas2557-codec.h +++ b/techpack/audio/asoc/codecs/tas2557/tas2557-codec.h @@ -1,7 +1,6 @@ /* ** ============================================================================= ** Copyright (c) 2016 Texas Instruments Inc. -** Copyright (C) 2019 XiaoMi, Inc. ** ** This program is free software; you can redistribute it and/or modify it under ** the terms of the GNU General Public License as published by the Free Software diff --git a/techpack/audio/asoc/codecs/tas2557/tas2557-core.c b/techpack/audio/asoc/codecs/tas2557/tas2557-core.c index dbf65315c7bc..476390b7991d 100644 --- a/techpack/audio/asoc/codecs/tas2557/tas2557-core.c +++ b/techpack/audio/asoc/codecs/tas2557/tas2557-core.c @@ -1,7 +1,6 @@ /* ** ============================================================================= ** Copyright (c) 2016 Texas Instruments Inc. -** Copyright (C) 2019 XiaoMi, Inc. ** ** This program is free software; you can redistribute it and/or modify it under ** the terms of the GNU General Public License as published by the Free Software @@ -312,8 +311,7 @@ static void failsafe(struct tas2557_priv *pTAS2557) pTAS2557->mnErrCode |= ERROR_FAILSAFE; if (hrtimer_active(&pTAS2557->mtimer)) hrtimer_cancel(&pTAS2557->mtimer); - if(pTAS2557->mnRestart < RESTART_MAX) - { + if (pTAS2557->mnRestart < RESTART_MAX) { pTAS2557->mnRestart ++; msleep(100); dev_err(pTAS2557->dev, "I2C COMM error, restart SmartAmp.\n"); @@ -517,10 +515,10 @@ int tas2557_enable(struct tas2557_priv *pTAS2557, bool bEnable) pFWName = TAS2557_DEFAULT_FW_NAME; nResult = request_firmware_nowait(THIS_MODULE, 1, pFWName, - pTAS2557->dev, GFP_KERNEL, pTAS2557, tas2557_fw_ready); - if(nResult < 0) + pTAS2557->dev, GFP_KERNEL, pTAS2557, tas2557_fw_ready); + if (nResult < 0) goto end; - dev_err(pTAS2557->dev, "%s, firmware is loaded\n", __func__); + dev_dbg(pTAS2557->dev, "%s, firmware is loaded\n", __func__); } /* check safe guard*/ @@ -573,9 +571,7 @@ int tas2557_enable(struct tas2557_priv *pTAS2557, bool bEnable) goto end; pTAS2557->mbPowerUp = true; - if(config_24bit_flag) - { -//set_configuration_for_24bit + if (config_24bit_flag) { config_24bit = set_configuration_for_24bit(pTAS2557); tas2557_set_config(pTAS2557, config_24bit); config_24bit_flag = 0; @@ -1474,7 +1470,7 @@ static int tas2557_load_configuration(struct tas2557_priv *pTAS2557, dev_dbg(pTAS2557->dev, "%s: %d\n", __func__, nConfiguration); - if((nConfiguration == 4)||(nConfiguration == 10)) + if (nConfiguration == 4 || nConfiguration == 10) set_calibration_E1s_E8 = nConfiguration; if ((!pTAS2557->mpFirmware->mpPrograms) || diff --git a/techpack/audio/asoc/codecs/tas2557/tas2557-core.h b/techpack/audio/asoc/codecs/tas2557/tas2557-core.h old mode 100755 new mode 100644 index aa0987381658..5081d5bb4364 --- a/techpack/audio/asoc/codecs/tas2557/tas2557-core.h +++ b/techpack/audio/asoc/codecs/tas2557/tas2557-core.h @@ -1,7 +1,6 @@ /* ** ============================================================================= ** Copyright (c) 2016 Texas Instruments Inc. -** Copyright (C) 2019 XiaoMi, Inc. ** ** This program is free software; you can redistribute it and/or modify it under ** the terms of the GNU General Public License as published by the Free Software diff --git a/techpack/audio/asoc/codecs/tas2557/tas2557-misc.c b/techpack/audio/asoc/codecs/tas2557/tas2557-misc.c index 15d62c3dcb31..dfad8f06d850 100644 --- a/techpack/audio/asoc/codecs/tas2557/tas2557-misc.c +++ b/techpack/audio/asoc/codecs/tas2557/tas2557-misc.c @@ -1,7 +1,6 @@ /* ** ============================================================================= ** Copyright (c) 2016 Texas Instruments Inc. -** Copyright (C) 2019 XiaoMi, Inc. ** ** This program is free software; you can redistribute it and/or modify it under ** the terms of the GNU General Public License as published by the Free Software @@ -463,6 +462,7 @@ static ssize_t tas2557_file_write(struct file *file, const char *buf, size_t cou pFWName = TAS2557_PG1P0_FW_NAME; else break; + if (pTAS2557->mnSpkType == VENDOR_ID_GOER) pFWName = TAS2557_GOER_FW_NAME; else if (pTAS2557->mnSpkType == VENDOR_ID_AAC) @@ -494,77 +494,10 @@ static ssize_t tas2557_file_write(struct file *file, const char *buf, size_t cou return count; } -static long tas2557_file_unlocked_ioctl(struct file *file, unsigned int cmd, unsigned long arg) -{ - struct tas2557_priv *pTAS2557 = file->private_data; - int ret = 0; - - mutex_lock(&pTAS2557->file_lock); - - switch (cmd) { - case SMARTPA_SPK_DAC_VOLUME: - { - } - break; - - case SMARTPA_SPK_POWER_ON: - { - tas2557_enable(pTAS2557, true); - } - break; - - case SMARTPA_SPK_POWER_OFF: - { - tas2557_enable(pTAS2557, false); - } - break; - - case SMARTPA_SPK_SWITCH_PROGRAM: - { - if ((pTAS2557->mpFirmware->mnConfigurations > 0) - && (pTAS2557->mpFirmware->mnPrograms > 0)) - tas2557_set_program(pTAS2557, arg, -1); - } - break; - - case SMARTPA_SPK_SWITCH_CONFIGURATION: - { - if ((pTAS2557->mpFirmware->mnConfigurations > 0) - && (pTAS2557->mpFirmware->mnPrograms > 0)) - tas2557_set_config(pTAS2557, arg); - } - break; - - case SMARTPA_SPK_SWITCH_CALIBRATION: - { - if ((pTAS2557->mpFirmware->mnConfigurations > 0) - && (pTAS2557->mpFirmware->mnPrograms > 0)) - tas2557_set_calibration(pTAS2557, arg); - } - break; - - case SMARTPA_SPK_SET_SAMPLERATE: - { - tas2557_set_sampling_rate(pTAS2557, arg); - } - break; - - case SMARTPA_SPK_SET_BITRATE: - { - tas2557_set_bit_rate(pTAS2557, arg); - } - break; - } - - mutex_unlock(&pTAS2557->file_lock); - return ret; -} - static const struct file_operations fops = { .owner = THIS_MODULE, .read = tas2557_file_read, .write = tas2557_file_write, - .unlocked_ioctl = tas2557_file_unlocked_ioctl, .open = tas2557_file_open, .release = tas2557_file_release, }; diff --git a/techpack/audio/asoc/codecs/tas2557/tas2557-misc.h b/techpack/audio/asoc/codecs/tas2557/tas2557-misc.h old mode 100755 new mode 100644 index 99a240c168ed..81b4fb288d94 --- a/techpack/audio/asoc/codecs/tas2557/tas2557-misc.h +++ b/techpack/audio/asoc/codecs/tas2557/tas2557-misc.h @@ -1,7 +1,6 @@ /* ** ============================================================================= ** Copyright (c) 2016 Texas Instruments Inc. -** Copyright (C) 2019 XiaoMi, Inc. ** ** This program is free software; you can redistribute it and/or modify it under ** the terms of the GNU General Public License as published by the Free Software @@ -41,17 +40,6 @@ #define TIAUDIO_CMD_SPEAKER 11 #define TIAUDIO_CMD_FW_RELOAD 12 -#define TAS2557_MAGIC_NUMBER 0x32353537 /* '2557' */ - -#define SMARTPA_SPK_DAC_VOLUME _IOWR(TAS2557_MAGIC_NUMBER, 1, unsigned long) -#define SMARTPA_SPK_POWER_ON _IOWR(TAS2557_MAGIC_NUMBER, 2, unsigned long) -#define SMARTPA_SPK_POWER_OFF _IOWR(TAS2557_MAGIC_NUMBER, 3, unsigned long) -#define SMARTPA_SPK_SWITCH_PROGRAM _IOWR(TAS2557_MAGIC_NUMBER, 4, unsigned long) -#define SMARTPA_SPK_SWITCH_CONFIGURATION _IOWR(TAS2557_MAGIC_NUMBER, 5, unsigned long) -#define SMARTPA_SPK_SWITCH_CALIBRATION _IOWR(TAS2557_MAGIC_NUMBER, 6, unsigned long) -#define SMARTPA_SPK_SET_SAMPLERATE _IOWR(TAS2557_MAGIC_NUMBER, 7, unsigned long) -#define SMARTPA_SPK_SET_BITRATE _IOWR(TAS2557_MAGIC_NUMBER, 8, unsigned long) - int tas2557_register_misc(struct tas2557_priv *pTAS2557); int tas2557_deregister_misc(struct tas2557_priv *pTAS2557); diff --git a/techpack/audio/asoc/codecs/tas2557/tas2557-regmap.c b/techpack/audio/asoc/codecs/tas2557/tas2557-regmap.c index e596fb4472f4..55ec7672c557 100644 --- a/techpack/audio/asoc/codecs/tas2557/tas2557-regmap.c +++ b/techpack/audio/asoc/codecs/tas2557/tas2557-regmap.c @@ -1,7 +1,6 @@ /* ** ============================================================================= ** Copyright (c) 2016 Texas Instruments Inc. -** Copyright (C) 2019 XiaoMi, Inc. ** ** This program is free software; you can redistribute it and/or modify it under ** the terms of the GNU General Public License as published by the Free Software @@ -68,7 +67,7 @@ static int tas2557_change_book_page( { int nResult = 0; - if ((pTAS2557->mnCurrentBook == nBook) + if ((pTAS2557->mnCurrentBook == nBook) && pTAS2557->mnCurrentPage == nPage) goto end; @@ -136,7 +135,7 @@ static int tas2557_dev_read( TAS2557_PAGE_REG(nRegister)); } - nResult = tas2557_change_book_page(pTAS2557, + nResult = tas2557_change_book_page(pTAS2557, TAS2557_BOOK_ID(nRegister), TAS2557_PAGE_ID(nRegister)); if (nResult >= 0) { @@ -391,7 +390,7 @@ static void irq_work_routine(struct work_struct *work) mutex_lock(&pTAS2557->file_lock); #endif - if(pTAS2557->mnErrCode & ERROR_FAILSAFE) + if (pTAS2557->mnErrCode & ERROR_FAILSAFE) goto program; if (pTAS2557->mbRuntimeSuspend) { @@ -901,7 +900,6 @@ static struct i2c_driver tas2557_i2c_driver = { #if defined(CONFIG_OF) .of_match_table = of_match_ptr(tas2557_of_match), #endif - .probe_type = PROBE_PREFER_ASYNCHRONOUS, }, .probe = tas2557_i2c_probe, .remove = tas2557_i2c_remove, @@ -914,4 +912,4 @@ MODULE_AUTHOR("Texas Instruments Inc."); MODULE_DESCRIPTION("TAS2557 I2C Smart Amplifier driver"); MODULE_LICENSE("GPL v2"); -#endif \ No newline at end of file +#endif diff --git a/techpack/audio/asoc/codecs/tas2557/tas2557.h b/techpack/audio/asoc/codecs/tas2557/tas2557.h index fb5bf866f8b0..e46bedc9fbab 100644 --- a/techpack/audio/asoc/codecs/tas2557/tas2557.h +++ b/techpack/audio/asoc/codecs/tas2557/tas2557.h @@ -1,7 +1,6 @@ /* ** ============================================================================= ** Copyright (c) 2016 Texas Instruments Inc. -** Copyright (C) 2019 XiaoMi, Inc. ** ** This program is free software; you can redistribute it and/or modify it under ** the terms of the GNU General Public License as published by the Free Software diff --git a/techpack/audio/asoc/codecs/tas2557/tiload.c b/techpack/audio/asoc/codecs/tas2557/tiload.c old mode 100755 new mode 100644 index 7d4bc19f650e..4cf0ddfa1879 --- a/techpack/audio/asoc/codecs/tas2557/tiload.c +++ b/techpack/audio/asoc/codecs/tas2557/tiload.c @@ -1,7 +1,6 @@ /* ** ============================================================================= ** Copyright (c) 2016 Texas Instruments Inc. -** Copyright (C) 2019 XiaoMi, Inc. ** ** This program is free software; you can redistribute it and/or modify it under ** the terms of the GNU General Public License as published by the Free Software diff --git a/techpack/audio/asoc/codecs/tas2557/tiload.h b/techpack/audio/asoc/codecs/tas2557/tiload.h old mode 100755 new mode 100644 index d97fc8fb29f5..7468acfa3964 --- a/techpack/audio/asoc/codecs/tas2557/tiload.h +++ b/techpack/audio/asoc/codecs/tas2557/tiload.h @@ -1,7 +1,6 @@ /* ** ============================================================================= ** Copyright (c) 2016 Texas Instruments Inc. -** Copyright (C) 2019 XiaoMi, Inc. ** ** This program is free software; you can redistribute it and/or modify it under ** the terms of the GNU General Public License as published by the Free Software diff --git a/techpack/audio/asoc/codecs/tas2559/Makefile b/techpack/audio/asoc/codecs/tas2559/Makefile old mode 100755 new mode 100644 index f46f2990aee7..d3c8535bf0c5 --- a/techpack/audio/asoc/codecs/tas2559/Makefile +++ b/techpack/audio/asoc/codecs/tas2559/Makefile @@ -1,5 +1,6 @@ ccflags-y += -DCONFIG_TAS2559_CODEC ccflags-y += -DCONFIG_TAS2559_MISC +ccflags-y += -DDEBUG snd-soc-tas2559-objs := tas2559-core.o tas2559-regmap.o tas2559-codec.o tas2559-misc.o tiload.o obj-$(CONFIG_SND_SOC_TAS2559) += snd-soc-tas2559.o diff --git a/techpack/audio/asoc/codecs/tas2559/tas2559-codec.c b/techpack/audio/asoc/codecs/tas2559/tas2559-codec.c old mode 100755 new mode 100644 index eece36dcccfe..27a1172f5c44 --- a/techpack/audio/asoc/codecs/tas2559/tas2559-codec.c +++ b/techpack/audio/asoc/codecs/tas2559/tas2559-codec.c @@ -1,7 +1,6 @@ /* ** ============================================================================= ** Copyright (c) 2016 Texas Instruments Inc. -** Copyright (C) 2019 XiaoMi, Inc. ** ** This program is free software; you can redistribute it and/or modify it under ** the terms of the GNU General Public License as published by the Free Software diff --git a/techpack/audio/asoc/codecs/tas2559/tas2559-codec.h b/techpack/audio/asoc/codecs/tas2559/tas2559-codec.h old mode 100755 new mode 100644 index 200edd21481b..17093a5f73e4 --- a/techpack/audio/asoc/codecs/tas2559/tas2559-codec.h +++ b/techpack/audio/asoc/codecs/tas2559/tas2559-codec.h @@ -1,7 +1,6 @@ /* ** ============================================================================= ** Copyright (c) 2016 Texas Instruments Inc. -** Copyright (C) 2019 XiaoMi, Inc. ** ** This program is free software; you can redistribute it and/or modify it under ** the terms of the GNU General Public License as published by the Free Software diff --git a/techpack/audio/asoc/codecs/tas2559/tas2559-core.c b/techpack/audio/asoc/codecs/tas2559/tas2559-core.c index 6d579e1cf4fb..8a8ddff6465b 100644 --- a/techpack/audio/asoc/codecs/tas2559/tas2559-core.c +++ b/techpack/audio/asoc/codecs/tas2559/tas2559-core.c @@ -1,7 +1,6 @@ /* ** ============================================================================= ** Copyright (c) 2016 Texas Instruments Inc. -** Copyright (C) 2019 XiaoMi, Inc. ** ** This program is free software; you can redistribute it and/or modify it under ** the terms of the GNU General Public License as published by the Free Software @@ -724,7 +723,7 @@ int tas2559_set_VBoost(struct tas2559_priv *pTAS2559, int vboost, bool bPowerOn) } if (bPowerOn) { - dev_dbg(pTAS2559->dev, "%s, will load VBoost state next time before power on\n", __func__); + dev_info(pTAS2559->dev, "%s, will load VBoost state next time before power on\n", __func__); pTAS2559->mbLoadVBoostPrePowerUp = true; pTAS2559->mnVBoostNewState = vboost; goto end; @@ -1327,7 +1326,7 @@ int tas2559_set_sampling_rate(struct tas2559_priv *pTAS2559, unsigned int nSampl pConfiguration = &(pTAS2559->mpFirmware->mpConfigurations[pTAS2559->mnCurrentConfiguration]); if (pConfiguration->mnSamplingRate == nSamplingRate) { - dev_dbg(pTAS2559->dev, "Sampling rate for current configuration matches: %d\n", + dev_info(pTAS2559->dev, "Sampling rate for current configuration matches: %d\n", nSamplingRate); nResult = 0; goto end; @@ -1341,7 +1340,7 @@ int tas2559_set_sampling_rate(struct tas2559_priv *pTAS2559, unsigned int nSampl if ((pConfiguration->mnSamplingRate == nSamplingRate) && (pConfiguration->mnProgram == pTAS2559->mnCurrentProgram)) { - dev_dbg(pTAS2559->dev, + dev_info(pTAS2559->dev, "Found configuration: %s, with compatible sampling rate %d\n", pConfiguration->mpName, nSamplingRate); nResult = tas2559_load_configuration(pTAS2559, nConfiguration, false); @@ -1359,14 +1358,14 @@ int tas2559_set_sampling_rate(struct tas2559_priv *pTAS2559, unsigned int nSampl static void fw_print_header(struct tas2559_priv *pTAS2559, struct TFirmware *pFirmware) { - dev_dbg(pTAS2559->dev, "FW Size = %d", pFirmware->mnFWSize); - dev_dbg(pTAS2559->dev, "Checksum = 0x%04X", pFirmware->mnChecksum); - dev_dbg(pTAS2559->dev, "PPC Version = 0x%04X", pFirmware->mnPPCVersion); - dev_dbg(pTAS2559->dev, "FW Version = 0x%04X", pFirmware->mnFWVersion); - dev_dbg(pTAS2559->dev, "Driver Version= 0x%04X", pFirmware->mnDriverVersion); - dev_dbg(pTAS2559->dev, "Timestamp = %d", pFirmware->mnTimeStamp); - dev_dbg(pTAS2559->dev, "DDC Name = %s", pFirmware->mpDDCName); - dev_dbg(pTAS2559->dev, "Description = %s", pFirmware->mpDescription); + dev_info(pTAS2559->dev, "FW Size = %d", pFirmware->mnFWSize); + dev_info(pTAS2559->dev, "Checksum = 0x%04X", pFirmware->mnChecksum); + dev_info(pTAS2559->dev, "PPC Version = 0x%04X", pFirmware->mnPPCVersion); + dev_info(pTAS2559->dev, "FW Version = 0x%04X", pFirmware->mnFWVersion); + dev_info(pTAS2559->dev, "Driver Version= 0x%04X", pFirmware->mnDriverVersion); + dev_info(pTAS2559->dev, "Timestamp = %d", pFirmware->mnTimeStamp); + dev_info(pTAS2559->dev, "DDC Name = %s", pFirmware->mpDDCName); + dev_info(pTAS2559->dev, "Description = %s", pFirmware->mpDescription); } static inline unsigned int fw_convert_number(unsigned char *pData) @@ -2400,7 +2399,7 @@ static int tas2559_load_configuration(struct tas2559_priv *pTAS2559, if ((!pTAS2559->mbLoadConfigurationPrePowerUp) && (nConfiguration == pTAS2559->mnCurrentConfiguration) && (!bLoadSame)) { - dev_dbg(pTAS2559->dev, "Configuration %d is already loaded\n", + dev_info(pTAS2559->dev, "Configuration %d is already loaded\n", nConfiguration); nResult = 0; goto end; @@ -2566,7 +2565,7 @@ static int tas2559_load_calibration(struct tas2559_priv *pTAS2559, char *pFileNa set_fs(KERNEL_DS); nFile = sys_open(pFileName, O_RDONLY, 0); - dev_dbg(pTAS2559->dev, "TAS2559 calibration file = %s, handle = %d\n", + dev_info(pTAS2559->dev, "TAS2559 calibration file = %s, handle = %d\n", pFileName, nFile); if (nFile >= 0) { @@ -2584,13 +2583,13 @@ static int tas2559_load_calibration(struct tas2559_priv *pTAS2559, char *pFileNa goto end; tas2559_clear_firmware(pTAS2559->mpCalFirmware); - dev_dbg(pTAS2559->dev, "TAS2559 calibration file size = %d\n", nSize); + dev_info(pTAS2559->dev, "TAS2559 calibration file size = %d\n", nSize); nResult = fw_parse(pTAS2559, pTAS2559->mpCalFirmware, pBuffer, nSize); if (nResult) dev_err(pTAS2559->dev, "TAS2559 calibration file is corrupt\n"); else - dev_dbg(pTAS2559->dev, "TAS2559 calibration: %d calibrations\n", + dev_info(pTAS2559->dev, "TAS2559 calibration: %d calibrations\n", pTAS2559->mpCalFirmware->mnCalibrations); end: @@ -2612,7 +2611,7 @@ void tas2559_fw_ready(const struct firmware *pFW, void *pContext) #ifdef CONFIG_TAS2559_MISC mutex_lock(&pTAS2559->file_lock); #endif - dev_dbg(pTAS2559->dev, "%s:\n", __func__); + dev_info(pTAS2559->dev, "%s:\n", __func__); if (unlikely(!pFW) || unlikely(!pFW->data)) { dev_err(pTAS2559->dev, "%s firmware is not loaded.\n", @@ -2648,7 +2647,7 @@ void tas2559_fw_ready(const struct firmware *pFW, void *pContext) } if (nProgram >= pTAS2559->mpFirmware->mnPrograms) { - dev_dbg(pTAS2559->dev, + dev_info(pTAS2559->dev, "no previous program, set to default\n"); nProgram = 0; } @@ -2707,10 +2706,10 @@ int tas2559_set_program(struct tas2559_priv *pTAS2559, if (pTAS2559->mpFirmware->mpConfigurations[nConfiguration].mnProgram == nProgram) { if (nSampleRate == 0) { bFound = true; - dev_dbg(pTAS2559->dev, "find default configuration %d\n", nConfiguration); + dev_info(pTAS2559->dev, "find default configuration %d\n", nConfiguration); } else if (nSampleRate == pTAS2559->mpFirmware->mpConfigurations[nConfiguration].mnSamplingRate) { bFound = true; - dev_dbg(pTAS2559->dev, "find matching configuration %d\n", nConfiguration); + dev_info(pTAS2559->dev, "find matching configuration %d\n", nConfiguration); } else { nConfiguration++; } @@ -2739,7 +2738,7 @@ int tas2559_set_program(struct tas2559_priv *pTAS2559, pProgram = &(pTAS2559->mpFirmware->mpPrograms[nProgram]); if (pTAS2559->mbPowerUp) { - dev_dbg(pTAS2559->dev, + dev_info(pTAS2559->dev, "device powered up, power down to load program %d (%s)\n", nProgram, pProgram->mpName); @@ -2765,7 +2764,7 @@ int tas2559_set_program(struct tas2559_priv *pTAS2559, if (nResult < 0) goto end; - dev_dbg(pTAS2559->dev, "load program %d (%s)\n", nProgram, pProgram->mpName); + dev_info(pTAS2559->dev, "load program %d (%s)\n", nProgram, pProgram->mpName); nResult = tas2559_load_data(pTAS2559, &(pProgram->mData), TAS2559_BLOCK_PGM_DEV_A); if (nResult < 0) goto end; @@ -2783,7 +2782,7 @@ int tas2559_set_program(struct tas2559_priv *pTAS2559, goto end; if (pTAS2559->mbPowerUp) { - dev_dbg(pTAS2559->dev, "%s, load VBoost before power on %d\n", __func__, pTAS2559->mnVBoostState); + dev_info(pTAS2559->dev, "%s, load VBoost before power on %d\n", __func__, pTAS2559->mnVBoostState); nResult = tas2559_set_VBoost(pTAS2559, pTAS2559->mnVBoostState, false); if (nResult < 0) goto end; @@ -2850,7 +2849,7 @@ int tas2559_set_calibration(struct tas2559_priv *pTAS2559, int nCalibration) } if (nCalibration == 0x00FF) { - dev_dbg(pTAS2559->dev, "load new calibration file %s\n", TAS2559_CAL_NAME); + dev_info(pTAS2559->dev, "load new calibration file %s\n", TAS2559_CAL_NAME); nResult = tas2559_load_calibration(pTAS2559, TAS2559_CAL_NAME); if (nResult < 0) { diff --git a/techpack/audio/asoc/codecs/tas2559/tas2559-core.h b/techpack/audio/asoc/codecs/tas2559/tas2559-core.h old mode 100755 new mode 100644 index 73dad713221a..5afbf91ba605 --- a/techpack/audio/asoc/codecs/tas2559/tas2559-core.h +++ b/techpack/audio/asoc/codecs/tas2559/tas2559-core.h @@ -1,7 +1,6 @@ /* ** ============================================================================= ** Copyright (c) 2016 Texas Instruments Inc. -** Copyright (C) 2019 XiaoMi, Inc. ** ** This program is free software; you can redistribute it and/or modify it under ** the terms of the GNU General Public License as published by the Free Software diff --git a/techpack/audio/asoc/codecs/tas2559/tas2559-misc.c b/techpack/audio/asoc/codecs/tas2559/tas2559-misc.c old mode 100755 new mode 100644 index 937bd1e94616..4bd458ad87b3 --- a/techpack/audio/asoc/codecs/tas2559/tas2559-misc.c +++ b/techpack/audio/asoc/codecs/tas2559/tas2559-misc.c @@ -1,7 +1,6 @@ /* ** ============================================================================= ** Copyright (c) 2016 Texas Instruments Inc. -** Copyright (C) 2019 XiaoMi, Inc. ** ** This program is free software; you can redistribute it and/or modify it under ** the terms of the GNU General Public License as published by the Free Software @@ -196,6 +195,7 @@ static ssize_t tas2559_file_read(struct file *file, char *buf, size_t count, lof ret = copy_to_user(buf, p_kBuf, count); if (ret != 0) { + /* Failed to copy all the data, exit */ dev_err(pTAS2559->dev, "copy to user fail %d\n", ret); } @@ -338,8 +338,10 @@ static ssize_t tas2559_file_write(struct file *file, const char *buf, size_t cou p_kBuf = kzalloc(count, GFP_KERNEL); - if (p_kBuf == NULL) + if (p_kBuf == NULL) { + dev_err(pTAS2559->dev, "write no mem\n"); goto err; + } ret = copy_from_user(p_kBuf, buf, count); @@ -395,6 +397,13 @@ static ssize_t tas2559_file_write(struct file *file, const char *buf, size_t cou dev_err(pTAS2559->dev, "read len fail.\n"); break; + + case TIAUDIO_CMD_DEBUG_ON: { + if (count == 2) + g_logEnable = p_kBuf[1]; + + pTAS2559->mnDBGCmd = 0; + } break; case TIAUDIO_CMD_PROGRAM: { diff --git a/techpack/audio/asoc/codecs/tas2559/tas2559-misc.h b/techpack/audio/asoc/codecs/tas2559/tas2559-misc.h old mode 100755 new mode 100644 index 746c69c5c795..eba659f7483b --- a/techpack/audio/asoc/codecs/tas2559/tas2559-misc.h +++ b/techpack/audio/asoc/codecs/tas2559/tas2559-misc.h @@ -1,7 +1,6 @@ /* ** ============================================================================= ** Copyright (c) 2016 Texas Instruments Inc. -** Copyright (C) 2019 XiaoMi, Inc. ** ** This program is free software; you can redistribute it and/or modify it under ** the terms of the GNU General Public License as published by the Free Software @@ -32,16 +31,17 @@ #define TIAUDIO_CMD_REG_WITE 1 #define TIAUDIO_CMD_REG_READ 2 -#define TIAUDIO_CMD_PROGRAM 3 -#define TIAUDIO_CMD_CONFIGURATION 4 -#define TIAUDIO_CMD_FW_TIMESTAMP 5 -#define TIAUDIO_CMD_CALIBRATION 6 -#define TIAUDIO_CMD_SAMPLERATE 7 -#define TIAUDIO_CMD_BITRATE 8 -#define TIAUDIO_CMD_DACVOLUME 9 -#define TIAUDIO_CMD_SPEAKER 10 -#define TIAUDIO_CMD_FW_RELOAD 11 -#define TIAUDIO_CMD_MUTE 12 +#define TIAUDIO_CMD_DEBUG_ON 3 +#define TIAUDIO_CMD_PROGRAM 4 +#define TIAUDIO_CMD_CONFIGURATION 5 +#define TIAUDIO_CMD_FW_TIMESTAMP 6 +#define TIAUDIO_CMD_CALIBRATION 7 +#define TIAUDIO_CMD_SAMPLERATE 8 +#define TIAUDIO_CMD_BITRATE 9 +#define TIAUDIO_CMD_DACVOLUME 10 +#define TIAUDIO_CMD_SPEAKER 11 +#define TIAUDIO_CMD_FW_RELOAD 12 +#define TIAUDIO_CMD_MUTE 13 #define TAS2559_MAGIC_NUMBER 0xe0 diff --git a/techpack/audio/asoc/codecs/tas2559/tas2559-regmap.c b/techpack/audio/asoc/codecs/tas2559/tas2559-regmap.c index b11ce923efd5..8bb8706ff039 100644 --- a/techpack/audio/asoc/codecs/tas2559/tas2559-regmap.c +++ b/techpack/audio/asoc/codecs/tas2559/tas2559-regmap.c @@ -1,7 +1,6 @@ /* ** ============================================================================= ** Copyright (c) 2016 Texas Instruments Inc. -** Copyright (C) 2019 XiaoMi, Inc. ** ** This program is free software; you can redistribute it and/or modify it under ** the terms of the GNU General Public License as published by the Free Software @@ -916,7 +915,7 @@ static void timer_work_routine(struct work_struct *work) dev_dbg(pTAS2559->dev, "check : avg=%d\n", nAvg); if (nAvg < -6) { - /* if Die temperature is below -6 degree C */ + /* if Die temperature is below -6 degree C */ if (pTAS2559->mnDevCurrentGain != LOW_TEMPERATURE_GAIN) { nResult = tas2559_set_DAC_gain(pTAS2559, DevBoth, LOW_TEMPERATURE_GAIN); diff --git a/techpack/audio/asoc/codecs/tas2559/tas2559.h b/techpack/audio/asoc/codecs/tas2559/tas2559.h old mode 100755 new mode 100644 index c70f807c02ad..ec1aeaf45856 --- a/techpack/audio/asoc/codecs/tas2559/tas2559.h +++ b/techpack/audio/asoc/codecs/tas2559/tas2559.h @@ -1,7 +1,6 @@ /* ** ============================================================================= ** Copyright (c) 2016 Texas Instruments Inc. -** Copyright (C) 2019 XiaoMi, Inc. ** ** This program is free software; you can redistribute it and/or modify it under ** the terms of the GNU General Public License as published by the Free Software diff --git a/techpack/audio/asoc/codecs/tas2559/tas2560.h b/techpack/audio/asoc/codecs/tas2559/tas2560.h old mode 100755 new mode 100644 index 6a9afede772e..2405f8a7bfae --- a/techpack/audio/asoc/codecs/tas2559/tas2560.h +++ b/techpack/audio/asoc/codecs/tas2559/tas2560.h @@ -1,7 +1,6 @@ /* ** ============================================================================= ** Copyright (c) 2016 Texas Instruments Inc. -** Copyright (C) 2019 XiaoMi, Inc. ** ** This program is free software; you can redistribute it and/or modify it under ** the terms of the GNU General Public License as published by the Free Software diff --git a/techpack/audio/asoc/codecs/tas2559/tiload.c b/techpack/audio/asoc/codecs/tas2559/tiload.c index c40ebeb5f801..d896388d5654 100644 --- a/techpack/audio/asoc/codecs/tas2559/tiload.c +++ b/techpack/audio/asoc/codecs/tas2559/tiload.c @@ -1,7 +1,6 @@ /* ** ============================================================================= ** Copyright (c) 2016 Texas Instruments Inc. -** Copyright (C) 2019 XiaoMi, Inc. ** ** This program is free software; you can redistribute it and/or modify it under ** the terms of the GNU General Public License as published by the Free Software @@ -39,6 +38,9 @@ #include "tiload.h" +/* enable debug prints in the driver */ +/*#define DEBUG*/ + static struct cdev *tiload_cdev; static int tiload_major; /* Dynamic allocation of Mjr No. */ static int tiload_opened; /* Dynamic allocation of Mjr No. */ @@ -48,6 +50,7 @@ static unsigned int magic_num; static char gPage; static char gBook; +/******************************** Debug section *****************************/ /*---------------------------------------------------------------------------- @@ -155,7 +158,7 @@ static ssize_t tiload_read(struct file *filp, char __user *buf, kfree(rd_data); return -EINVAL; } - kfree(rd_data); + kfree(rd_data); return size; } @@ -185,9 +188,10 @@ static ssize_t tiload_write(struct file *filp, const char __user *buf, } wr_data = kmalloc(MAX_LENGTH + 1, GFP_KERNEL | GFP_DMA); - if (wr_data == NULL) + if(wr_data == NULL) { + dev_err(pTAS2559->dev, "kmalloc fail \n"); return -EINVAL; - + } pData = wr_data; /* copy buffer from user space */ size = copy_from_user(wr_data, buf, count); diff --git a/techpack/audio/asoc/codecs/tas2559/tiload.h b/techpack/audio/asoc/codecs/tas2559/tiload.h old mode 100755 new mode 100644 index 364b733b23fa..6ddeee04dec6 --- a/techpack/audio/asoc/codecs/tas2559/tiload.h +++ b/techpack/audio/asoc/codecs/tas2559/tiload.h @@ -1,7 +1,6 @@ /* ** ============================================================================= ** Copyright (c) 2016 Texas Instruments Inc. -** Copyright (C) 2019 XiaoMi, Inc. ** ** This program is free software; you can redistribute it and/or modify it under ** the terms of the GNU General Public License as published by the Free Software diff --git a/techpack/audio/asoc/codecs/wcd-dsp-mgr.c b/techpack/audio/asoc/codecs/wcd-dsp-mgr.c index 7f9b0bf4895a..e2e4e62c1196 100644 --- a/techpack/audio/asoc/codecs/wcd-dsp-mgr.c +++ b/techpack/audio/asoc/codecs/wcd-dsp-mgr.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. - * Copyright (C) 2019 XiaoMi, Inc. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -86,7 +86,6 @@ static char *wdsp_get_cmpnt_type_string(enum wdsp_cmpnt_type); #define WDSP_SSR_STATUS_READY \ (WDSP_SSR_STATUS_WDSP_READY | WDSP_SSR_STATUS_CDC_READY) #define WDSP_SSR_READY_WAIT_TIMEOUT (10 * HZ) -#define WDSP_FW_LOAD_RETRY_COUNT 5 enum wdsp_ssr_type { @@ -386,7 +385,6 @@ static int wdsp_download_segments(struct wdsp_mgr_priv *wdsp, enum wdsp_event_type pre, post; long status; int ret; - int retry_cnt; ctl = WDSP_GET_COMPONENT(wdsp, WDSP_CMPNT_CONTROL); @@ -405,7 +403,9 @@ static int wdsp_download_segments(struct wdsp_mgr_priv *wdsp, ret = wdsp_get_segment_list(ctl->cdev, wdsp->img_fname, type, wdsp->seg_list, &wdsp->base_addr); + pr_info("%s: downloading wdsp firmware: %s.\n", __func__, wdsp->img_fname); + if (ret < 0 || list_empty(wdsp->seg_list)) { WDSP_ERR(wdsp, "Error %d to get image segments for type %d", @@ -418,23 +418,11 @@ static int wdsp_download_segments(struct wdsp_mgr_priv *wdsp, /* Notify all components that image is about to be downloaded */ wdsp_broadcast_event_upseq(wdsp, pre, NULL); - /* - * Go through the list of segments and download one by one. - * For each segment that fails to dlownload retry for - * WDSP_FW_LOAD_RETRY_COUNT times - */ + /* Go through the list of segments and download one by one */ list_for_each_entry(seg, wdsp->seg_list, list) { - retry_cnt = WDSP_FW_LOAD_RETRY_COUNT; - do { - ret = wdsp_load_each_segment(wdsp, seg); - } while (ret < 0 && --retry_cnt > 0); - - if (ret < 0) { - WDSP_ERR(wdsp, - "Failed to download, error %d\n", - ret); + ret = wdsp_load_each_segment(wdsp, seg); + if (ret) goto dload_error; - } } /* Flush the list before setting status and notifying components */ @@ -449,24 +437,7 @@ static int wdsp_download_segments(struct wdsp_mgr_priv *wdsp, dload_error: wdsp_flush_segment_list(wdsp->seg_list); - - /* - * code sections are downloaded at driver load and during SSR. - * Even if code section download fails, do not treat this - * as error to allow retry of code section download upon - * enable_dsp request. Since status flag is not set upon - * code section download failure, enable_dsp can check this - * and retry. - */ - if (type == WDSP_ELF_FLAG_RE) { - /* Notify all components that image is downloaded */ - wdsp_broadcast_event_downseq(wdsp, post, NULL); - ret = 0; - } else { - wdsp_broadcast_event_downseq(wdsp, - WDSP_EVENT_DLOAD_FAILED, NULL); - } - + wdsp_broadcast_event_downseq(wdsp, WDSP_EVENT_DLOAD_FAILED, NULL); return ret; } @@ -517,27 +488,17 @@ static int wdsp_enable_dsp(struct wdsp_mgr_priv *wdsp) { int ret; - /* - * Acquire SSR mutex lock to make sure enablement of DSP - * does not race with SSR handling. - */ - WDSP_MGR_MUTEX_LOCK(wdsp, wdsp->ssr_mutex); - /* Make sure wdsp is in good state */ if (!WDSP_STATUS_IS_SET(wdsp, WDSP_STATUS_CODE_DLOADED)) { WDSP_ERR(wdsp, "WDSP in invalid state 0x%x", wdsp->status); - /* - * Since DSP state indicates that code sections are - * not downloaded. Try to download them again now. - */ - ret = wdsp_init_and_dload_code_sections(wdsp); - if (ret < 0) { - WDSP_ERR(wdsp, "Retry code dload failed %d", - ret); - goto done; - } + return -EINVAL; } + /* + * Acquire SSR mutex lock to make sure enablement of DSP + * does not race with SSR handling. + */ + WDSP_MGR_MUTEX_LOCK(wdsp, wdsp->ssr_mutex); /* Download the read-write sections of image */ ret = wdsp_download_segments(wdsp, WDSP_ELF_FLAG_WRITE); if (ret < 0) { @@ -1243,7 +1204,8 @@ static int wdsp_mgr_parse_dt_entries(struct wdsp_mgr_priv *wdsp) ret = of_property_read_string(dev->of_node, "qcom,img-filename", &wdsp->img_fname); - wdsp->img_fname = "cpe_intl"; + + wdsp->img_fname = "cpe_intl"; pr_info("%s: using global wdsp fw: %s.\n", __func__, wdsp->img_fname); if (ret < 0) { diff --git a/techpack/audio/asoc/codecs/wcd-mbhc-adc.c b/techpack/audio/asoc/codecs/wcd-mbhc-adc.c index e7eb064ecde6..81f2f7b88012 100644 --- a/techpack/audio/asoc/codecs/wcd-mbhc-adc.c +++ b/techpack/audio/asoc/codecs/wcd-mbhc-adc.c @@ -1,5 +1,5 @@ /* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. - * Copyright (C) 2019 XiaoMi, Inc. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -10,7 +10,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#define DEBUG #include #include #include diff --git a/techpack/audio/asoc/codecs/wcd-mbhc-v2.c b/techpack/audio/asoc/codecs/wcd-mbhc-v2.c index bfc471b12ad8..fb4b9fba8cee 100644 --- a/techpack/audio/asoc/codecs/wcd-mbhc-v2.c +++ b/techpack/audio/asoc/codecs/wcd-mbhc-v2.c @@ -1,5 +1,5 @@ /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. - * Copyright (C) 2019 XiaoMi, Inc. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -10,7 +10,6 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#define DEBUG #include #include #include @@ -36,6 +35,12 @@ #include "wcd-mbhc-v2-api.h" #include +#define SUBPCB_ID_NONE 0 +#define SUBPCB_ID_OLD 1 +#define SUBPCB_ID_NEW 2 + +int subpcb_id_state; + void wcd_mbhc_jack_report(struct wcd_mbhc *mbhc, struct snd_soc_jack *jack, int status, int mask) { @@ -217,7 +222,6 @@ static int wcd_event_notify(struct notifier_block *self, unsigned long val, bool micbias2 = false; bool micbias1 = false; - pr_debug("%s: event %s (%d)\n", __func__, wcd_mbhc_get_event_string(event), event); if (mbhc->mbhc_cb->micbias_enable_status) { @@ -840,6 +844,8 @@ static void wcd_mbhc_swch_irq_handler(struct wcd_mbhc *mbhc) bool micbias1 = false; struct snd_soc_codec *codec = mbhc->codec; enum snd_jack_types jack_type; + struct usbc_ana_audio_config *config = + &mbhc->mbhc_cfg->usbc_analog_cfg; dev_dbg(codec->dev, "%s: enter\n", __func__); WCD_MBHC_RSC_LOCK(mbhc); @@ -950,6 +956,11 @@ static void wcd_mbhc_swch_irq_handler(struct wcd_mbhc *mbhc) WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_ELECT_DETECTION_TYPE, 1); WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_ELECT_SCHMT_ISRC, 0); mbhc->extn_cable_hph_rem = false; + + if (config->usbc_en1_gpio_p) { + msm_cdc_pinctrl_select_sleep_state(config->usbc_en1_gpio_p); + pr_info("wcd_mbhc_swch_irq_handler: switch L/R to usb \n"); + } wcd_mbhc_report_plug(mbhc, 0, jack_type); } else if (!detection_type) { @@ -1491,21 +1502,13 @@ static int wcd_mbhc_usb_c_analog_setup_gpios(struct wcd_mbhc *mbhc, WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_MIC_CLAMP_CTL, 2); mbhc->mbhc_cfg->enable_dual_adc_gpio(mbhc->mbhc_cfg->dual_adc_gpio_node, 0); -#ifdef CONFIG_AUDIO_UART_DEBUG - if (get_hw_version_platform() == HARDWARE_PLATFORM_POLARIS) { - if (get_hw_version_major() == 0) - msm_cdc_pinctrl_select_active_state(config->uart_audio_switch_gpio_p); - else - msm_cdc_pinctrl_select_sleep_state(config->uart_audio_switch_gpio_p); - } -#endif - - /*using hardware auto switch gnd and mic if support*/ - if (config->euro_us_hw_switch_gpio_p) { + /* using hardware auto switch gnd and mic if support */ + if (config->euro_us_hw_switch_gpio_p && (subpcb_id_state == SUBPCB_ID_OLD)) { msm_cdc_pinctrl_select_active_state(config->euro_us_hw_switch_gpio_p); msleep(200); pr_info("hardware auto switch enable\n"); } + if (config->usbc_en1_gpio_p) rc = msm_cdc_pinctrl_select_active_state( config->usbc_en1_gpio_p); @@ -1522,18 +1525,10 @@ static int wcd_mbhc_usb_c_analog_setup_gpios(struct wcd_mbhc *mbhc, msm_cdc_pinctrl_select_sleep_state( config->usbc_force_gpio_p); - if (config->euro_us_hw_switch_gpio_p) { + if (config->euro_us_hw_switch_gpio_p && (subpcb_id_state == SUBPCB_ID_OLD)) { msm_cdc_pinctrl_select_sleep_state(config->euro_us_hw_switch_gpio_p); pr_info("hardware auto switch disable\n"); } -#ifdef CONFIG_AUDIO_UART_DEBUG - if (get_hw_version_platform() == HARDWARE_PLATFORM_POLARIS) { - if (get_hw_version_major() == 0) - msm_cdc_pinctrl_select_sleep_state(config->uart_audio_switch_gpio_p); - else - msm_cdc_pinctrl_select_active_state(config->uart_audio_switch_gpio_p); - } -#endif mbhc->mbhc_cfg->enable_dual_adc_gpio(mbhc->mbhc_cfg->dual_adc_gpio_node, 1); @@ -1548,6 +1543,7 @@ static int wcd_mbhc_usb_c_analog_setup_gpios(struct wcd_mbhc *mbhc, } mbhc->usbc_mode = POWER_SUPPLY_TYPEC_NONE; + WCD_MBHC_REG_UPDATE_BITS(WCD_MBHC_MIC_CLAMP_CTL, 0); if (mbhc->mbhc_cfg->swap_gnd_mic) mbhc->mbhc_cfg->swap_gnd_mic(mbhc->codec, false); } @@ -1702,6 +1698,7 @@ int wcd_mbhc_start(struct wcd_mbhc *mbhc, struct wcd_mbhc_config *mbhc_cfg) struct usbc_ana_audio_config *config; struct snd_soc_codec *codec; struct snd_soc_card *card; + int subpcb_id; const char *usb_c_dt = "qcom,msm-mbhc-usbc-audio-supported"; if (!mbhc || !mbhc_cfg) @@ -1775,6 +1772,40 @@ int wcd_mbhc_start(struct wcd_mbhc *mbhc, struct wcd_mbhc_config *mbhc_cfg) goto err; } + if (of_find_property(card->dev->of_node, + "qcom,subpcb-id-gpio", + NULL)) { + rc = wcd_mbhc_init_gpio(mbhc, mbhc_cfg, + "qcom,subpcb-id-gpio", + &config->subpcb_id_gpio, + &config->subpcb_id_gpio_p); + if (rc) + goto err; + config->subpcb_id_gpio = of_get_named_gpio( + card->dev->of_node, "qcom,subpcb-id-gpio-num", 0); + + if (!gpio_is_valid(config->subpcb_id_gpio)) { + pr_err("subpcb_id_gpio is invalid\n"); + goto err; + } + subpcb_id = gpio_get_value_cansleep(config->subpcb_id_gpio); + pr_info("subpcb_id_gpio = %d, value1 = %d\n", + config->subpcb_id_gpio, subpcb_id); + + if (subpcb_id == 0) + subpcb_id_state = SUBPCB_ID_NEW; + else + subpcb_id_state = SUBPCB_ID_OLD; + + msm_cdc_pinctrl_select_active_state( + config->subpcb_id_gpio_p); + + subpcb_id = gpio_get_value_cansleep(config->subpcb_id_gpio); + pr_info("subpcb_id_gpio = %d, value2 = %d\n", + config->subpcb_id_gpio, subpcb_id); + + } + dev_dbg(mbhc->codec->dev, "%s: calling usb_c_analog_init\n", __func__); /* init PMI notifier */ diff --git a/techpack/audio/asoc/codecs/wcd-mbhc-v2.h b/techpack/audio/asoc/codecs/wcd-mbhc-v2.h index 014133a66709..af4fcdc939a3 100644 --- a/techpack/audio/asoc/codecs/wcd-mbhc-v2.h +++ b/techpack/audio/asoc/codecs/wcd-mbhc-v2.h @@ -1,5 +1,5 @@ /* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. - * Copyright (C) 2019 XiaoMi, Inc. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -414,11 +414,13 @@ struct usbc_ana_audio_config { int usbc_force_gpio; int euro_us_hw_switch_gpio; int uart_audio_switch_gpio; + int subpcb_id_gpio; struct device_node *usbc_en1_gpio_p; /* used by pinctrl API */ struct device_node *usbc_en2_gpio_p; /* used by pinctrl API */ struct device_node *usbc_force_gpio_p; /* used by pinctrl API */ struct device_node *euro_us_hw_switch_gpio_p; /* used by pinctrl API */ struct device_node *uart_audio_switch_gpio_p; /* used by pinctrl API */ + struct device_node *subpcb_id_gpio_p; /* used by pinctrl API */ }; struct wcd_mbhc_config { diff --git a/techpack/audio/asoc/codecs/wcd-spi.c b/techpack/audio/asoc/codecs/wcd-spi.c index c9f172f1678a..20b358e0fd30 100644 --- a/techpack/audio/asoc/codecs/wcd-spi.c +++ b/techpack/audio/asoc/codecs/wcd-spi.c @@ -1,6 +1,5 @@ /* * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. - * Copyright (C) 2019 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -27,7 +26,6 @@ #include #include #include -#include #include "wcd-spi-registers.h" /* Byte manipulations */ @@ -700,15 +698,8 @@ static int wcd_spi_clk_ctrl(struct spi_device *spi, */ if (test_bit(WCD_SPI_CLK_STATE_ENABLED, &wcd_spi->status_mask)) goto done; - else if (wcd_spi->clk_users == 1) { + else if (wcd_spi->clk_users == 1) ret = wcd_spi_clk_enable(spi); - if ((get_hw_version_platform() == HARDWARE_PLATFORM_PERSEUS) && - (get_hw_version_major() == 2) && - (get_hw_version_minor() == 0)) { - if (ret != 0) - wcd_spi->clk_users = 0; - } - } } else { wcd_spi->clk_users--; diff --git a/techpack/audio/asoc/codecs/wcd934x/wcd934x-mbhc.c b/techpack/audio/asoc/codecs/wcd934x/wcd934x-mbhc.c index 0510bc8b3c86..f67c59c0654a 100644 --- a/techpack/audio/asoc/codecs/wcd934x/wcd934x-mbhc.c +++ b/techpack/audio/asoc/codecs/wcd934x/wcd934x-mbhc.c @@ -1,5 +1,4 @@ /* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. - * Copyright (C) 2019 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -987,14 +986,13 @@ int tavil_mbhc_get_impedance(struct wcd934x_mbhc *wcd934x_mbhc, } EXPORT_SYMBOL(tavil_mbhc_get_impedance); - int tavil_mb_pull_down(struct snd_soc_codec *codec, bool active, int value) { - int oldv = 0; + int old_value = 0; if (active) { - oldv = snd_soc_read(codec, WCD934X_ANA_MICB2); + old_value = snd_soc_read(codec, WCD934X_ANA_MICB2); snd_soc_update_bits(codec, WCD934X_ANA_MBHC_ELECT, 0x80, 0x00); snd_soc_update_bits(codec, WCD934X_ANA_MICB2, 0xC0, 0xC0); @@ -1004,11 +1002,10 @@ int tavil_mb_pull_down(struct snd_soc_codec *codec, bool active, 0x80, 0x80); } - return oldv; + return old_value; } EXPORT_SYMBOL(tavil_mb_pull_down); - /* * tavil_mbhc_hs_detect: starts mbhc insertion/removal functionality * @codec: handle to snd_soc_codec * diff --git a/techpack/audio/asoc/codecs/wcd934x/wcd934x-mbhc.h b/techpack/audio/asoc/codecs/wcd934x/wcd934x-mbhc.h index f1330863a2e3..4ae904bf5e37 100644 --- a/techpack/audio/asoc/codecs/wcd934x/wcd934x-mbhc.h +++ b/techpack/audio/asoc/codecs/wcd934x/wcd934x-mbhc.h @@ -1,6 +1,5 @@ /* * Copyright (c) 2015-2017, The Linux Foundation. All rights reserved. - * Copyright (C) 2019 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -48,10 +47,8 @@ extern int tavil_mbhc_post_ssr_init(struct wcd934x_mbhc *mbhc, struct snd_soc_codec *codec); extern int tavil_mbhc_get_impedance(struct wcd934x_mbhc *wcd934x_mbhc, uint32_t *zl, uint32_t *zr); - extern int tavil_mb_pull_down(struct snd_soc_codec *codec, bool active, int value); - #else static inline int tavil_mbhc_init(struct wcd934x_mbhc **mbhc, struct snd_soc_codec *codec, @@ -85,13 +82,11 @@ static inline int tavil_mbhc_get_impedance(struct wcd934x_mbhc *wcd934x_mbhc, return -EINVAL; } - static inline int tavil_mb_pull_down(struct snd_soc_codec *codec, bool active, int value) { return 0; } - #endif #endif /* __WCD934X_MBHC_H__ */ diff --git a/techpack/audio/asoc/codecs/wcd934x/wcd934x-regmap.c b/techpack/audio/asoc/codecs/wcd934x/wcd934x-regmap.c index 30fc9bdcdac7..89e9436f572a 100644 --- a/techpack/audio/asoc/codecs/wcd934x/wcd934x-regmap.c +++ b/techpack/audio/asoc/codecs/wcd934x/wcd934x-regmap.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved. - * Copyright (C) 2019 XiaoMi, Inc. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/techpack/audio/asoc/codecs/wcd934x/wcd934x.c b/techpack/audio/asoc/codecs/wcd934x/wcd934x.c index f3e45e83bf87..13d9b141577b 100644 --- a/techpack/audio/asoc/codecs/wcd934x/wcd934x.c +++ b/techpack/audio/asoc/codecs/wcd934x/wcd934x.c @@ -1,5 +1,5 @@ /* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. - * Copyright (C) 2019 XiaoMi, Inc. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -51,8 +51,6 @@ #include "../wcdcal-hwdep.h" #include "wcd934x-dsd.h" -#define CONFIG_SOUND_CONTROL - #define WCD934X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000 |\ @@ -161,12 +159,6 @@ enum { POWER_RESUME, }; -#ifdef CONFIG_SOUND_CONTROL -static struct snd_soc_codec *sound_control_codec_ptr; -static int custom_hp_left = 0; -static int custom_hp_right = 0; -#endif - static int dig_core_collapse_enable = 1; module_param(dig_core_collapse_enable, int, 0664); MODULE_PARM_DESC(dig_core_collapse_enable, "enable/disable power gating"); @@ -1470,13 +1462,6 @@ static int slim_rx_mux_put(struct snd_kcontrol *kcontrol, snd_soc_dapm_mux_update_power(widget->dapm, kcontrol, rx_port_value, e, update); -#ifdef CONFIG_SOUND_CONTROL - snd_soc_write(sound_control_codec_ptr, WCD934X_CDC_RX1_RX_VOL_MIX_CTL, custom_hp_left); - snd_soc_write(sound_control_codec_ptr, WCD934X_CDC_RX2_RX_VOL_MIX_CTL, custom_hp_right); - snd_soc_write(sound_control_codec_ptr, WCD934X_CDC_RX1_RX_VOL_CTL, custom_hp_left); - snd_soc_write(sound_control_codec_ptr, WCD934X_CDC_RX2_RX_VOL_CTL, custom_hp_right); -#endif - return 0; err: mutex_unlock(&tavil_p->codec_mutex); @@ -5638,10 +5623,28 @@ static int tavil_compander_put(struct snd_kcontrol *kcontrol, /* Set Gain Source Select based on compander enable/disable */ snd_soc_update_bits(codec, WCD934X_HPH_L_EN, 0x20, (value ? 0x00:0x20)); + + /* Disable Compander Clock */ + snd_soc_update_bits(codec, WCD934X_CDC_RX1_RX_PATH_CFG0, 0x02, 0x00); + snd_soc_update_bits(codec, WCD934X_CDC_COMPANDER1_CTL0, 0x04, 0x04); + snd_soc_update_bits(codec, WCD934X_CDC_COMPANDER1_CTL0, 0x02, 0x02); + snd_soc_update_bits(codec, WCD934X_CDC_COMPANDER1_CTL0, 0x02, 0x00); + snd_soc_update_bits(codec, WCD934X_CDC_COMPANDER1_CTL0, 0x01, 0x00); + snd_soc_update_bits(codec, WCD934X_CDC_COMPANDER1_CTL0, 0x04, 0x00); + break; case COMPANDER_2: snd_soc_update_bits(codec, WCD934X_HPH_R_EN, 0x20, (value ? 0x00:0x20)); + + /* Disable Compander Clock */ + snd_soc_update_bits(codec, WCD934X_CDC_RX2_RX_PATH_CFG0, 0x02, 0x00); + snd_soc_update_bits(codec, WCD934X_CDC_COMPANDER2_CTL0, 0x04, 0x04); + snd_soc_update_bits(codec, WCD934X_CDC_COMPANDER2_CTL0, 0x02, 0x02); + snd_soc_update_bits(codec, WCD934X_CDC_COMPANDER2_CTL0, 0x02, 0x00); + snd_soc_update_bits(codec, WCD934X_CDC_COMPANDER2_CTL0, 0x01, 0x00); + snd_soc_update_bits(codec, WCD934X_CDC_COMPANDER2_CTL0, 0x04, 0x00); + break; case COMPANDER_3: case COMPANDER_4: @@ -6145,6 +6148,7 @@ static int tavil_rx_hph_mode_put(struct snd_kcontrol *kcontrol, tavil->hph_mode = mode_val; return 0; } + static int codec_version_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { @@ -6173,7 +6177,7 @@ static int codec_version_get(struct snd_kcontrol *kcontrol, __func__, wcd9xxx->version); } - return 0; + return 0; } static const char * const rx_hph_mode_mux_text[] = { @@ -6223,6 +6227,7 @@ static const char * const tavil_ear_spkr_pa_gain_text[] = { "G_DEFAULT", "G_0_DB", "G_1_DB", "G_2_DB", "G_3_DB", "G_4_DB", "G_5_DB", "G_6_DB" }; + static const char *const codec_version_text[] = {"Unknown", "WCD9340_v1.0", "WCD9341_v1.0", "WCD9340_v1.1", "WCD9341_v1.1"}; static const struct soc_enum codec_version[] = { SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(codec_version_text), codec_version_text), @@ -6311,12 +6316,10 @@ static const struct snd_kcontrol_new tavil_snd_controls[] = { SOC_SINGLE_SX_TLV("RX0 Digital Volume", WCD934X_CDC_RX0_RX_VOL_CTL, 0, -84, 40, digital_gain), /* -84dB min - 40dB max */ -#ifndef CONFIG_SOUND_CONTROL SOC_SINGLE_SX_TLV("RX1 Digital Volume", WCD934X_CDC_RX1_RX_VOL_CTL, 0, -84, 40, digital_gain), SOC_SINGLE_SX_TLV("RX2 Digital Volume", WCD934X_CDC_RX2_RX_VOL_CTL, 0, -84, 40, digital_gain), -#endif SOC_SINGLE_SX_TLV("RX3 Digital Volume", WCD934X_CDC_RX3_RX_VOL_CTL, 0, -84, 40, digital_gain), SOC_SINGLE_SX_TLV("RX4 Digital Volume", WCD934X_CDC_RX4_RX_VOL_CTL, @@ -6327,12 +6330,10 @@ static const struct snd_kcontrol_new tavil_snd_controls[] = { 0, -84, 40, digital_gain), SOC_SINGLE_SX_TLV("RX0 Mix Digital Volume", WCD934X_CDC_RX0_RX_VOL_MIX_CTL, 0, -84, 40, digital_gain), -#ifndef CONFIG_SOUND_CONTROL SOC_SINGLE_SX_TLV("RX1 Mix Digital Volume", WCD934X_CDC_RX1_RX_VOL_MIX_CTL, 0, -84, 40, digital_gain), SOC_SINGLE_SX_TLV("RX2 Mix Digital Volume", WCD934X_CDC_RX2_RX_VOL_MIX_CTL, 0, -84, 40, digital_gain), -#endif SOC_SINGLE_SX_TLV("RX3 Mix Digital Volume", WCD934X_CDC_RX3_RX_VOL_MIX_CTL, 0, -84, 40, digital_gain), SOC_SINGLE_SX_TLV("RX4 Mix Digital Volume", @@ -6522,7 +6523,7 @@ static const struct snd_kcontrol_new tavil_snd_controls[] = { SOC_ENUM_EXT("AMIC_5_6 PWR MODE", amic_pwr_lvl_enum, tavil_amic_pwr_lvl_get, tavil_amic_pwr_lvl_put), SOC_ENUM_EXT("Codec Version", codec_version, - codec_version_get, NULL ), + codec_version_get, NULL), }; static int tavil_dec_enum_put(struct snd_kcontrol *kcontrol, @@ -10154,114 +10155,6 @@ static int tavil_post_reset_cb(struct wcd9xxx *wcd9xxx) return ret; } -#ifdef CONFIG_SOUND_CONTROL -static ssize_t headphone_gain_show(struct kobject *kobj, - struct kobj_attribute *attr, char *buf) -{ - return snprintf(buf, PAGE_SIZE, "%d %d\n", - snd_soc_read(sound_control_codec_ptr, WCD934X_CDC_RX1_RX_VOL_CTL), - snd_soc_read(sound_control_codec_ptr, WCD934X_CDC_RX2_RX_VOL_CTL) - ); -} - -static ssize_t headphone_gain_store(struct kobject *kobj, - struct kobj_attribute *attr, const char *buf, size_t count) -{ - - int input_l, input_r; - - sscanf(buf, "%d %d", &input_l, &input_r); - - if (input_l < -84 || input_l > 20) - input_l = 0; - - if (input_r < -84 || input_r > 20) - input_r = 0; - - custom_hp_left = input_l; - custom_hp_right = input_r; - - snd_soc_write(sound_control_codec_ptr, WCD934X_CDC_RX1_RX_VOL_MIX_CTL, input_l); - snd_soc_write(sound_control_codec_ptr, WCD934X_CDC_RX2_RX_VOL_MIX_CTL, input_r); - snd_soc_write(sound_control_codec_ptr, WCD934X_CDC_RX1_RX_VOL_CTL, input_l); - snd_soc_write(sound_control_codec_ptr, WCD934X_CDC_RX2_RX_VOL_CTL, input_r); - - return count; -} - -static struct kobj_attribute headphone_gain_attribute = - __ATTR(headphone_gain, 0664, - headphone_gain_show, - headphone_gain_store); - -static ssize_t mic_gain_show(struct kobject *kobj, - struct kobj_attribute *attr, char *buf) -{ - return snprintf(buf, PAGE_SIZE, "%d\n", - snd_soc_read(sound_control_codec_ptr, WCD934X_CDC_TX7_TX_VOL_CTL)); -} - -static ssize_t mic_gain_store(struct kobject *kobj, - struct kobj_attribute *attr, const char *buf, size_t count) -{ - int input; - - sscanf(buf, "%d", &input); - - if (input < -10 || input > 20) - input = 0; - - snd_soc_write(sound_control_codec_ptr, WCD934X_CDC_TX7_TX_VOL_CTL, input); - - return count; -} - -static struct kobj_attribute mic_gain_attribute = - __ATTR(mic_gain, 0664, - mic_gain_show, - mic_gain_store); - -static ssize_t earpiece_gain_show(struct kobject *kobj, - struct kobj_attribute *attr, char *buf) -{ - return snprintf(buf, PAGE_SIZE, "%d\n", - snd_soc_read(sound_control_codec_ptr, WCD934X_CDC_RX0_RX_VOL_CTL)); -} - -static ssize_t earpiece_gain_store(struct kobject *kobj, - struct kobj_attribute *attr, const char *buf, size_t count) -{ - int input; - - sscanf(buf, "%d", &input); - - if (input < -10 || input > 20) - input = 0; - - snd_soc_write(sound_control_codec_ptr, WCD934X_CDC_RX0_RX_VOL_CTL, input); - - return count; -} - -static struct kobj_attribute earpiece_gain_attribute = - __ATTR(earpiece_gain, 0664, - earpiece_gain_show, - earpiece_gain_store); - -static struct attribute *sound_control_attrs[] = { - &headphone_gain_attribute.attr, - &mic_gain_attribute.attr, - &earpiece_gain_attribute.attr, - NULL, -}; - -static struct attribute_group sound_control_attr_group = { - .attrs = sound_control_attrs, -}; - -static struct kobject *sound_control_kobj; -#endif - static int tavil_soc_codec_probe(struct snd_soc_codec *codec) { struct wcd9xxx *control; @@ -10271,10 +10164,6 @@ static int tavil_soc_codec_probe(struct snd_soc_codec *codec) int i, ret; void *ptr = NULL; -#ifdef CONFIG_SOUND_CONTROL - sound_control_codec_ptr = codec; -#endif - control = dev_get_drvdata(codec->dev->parent); dev_info(codec->dev, "%s()\n", __func__); @@ -11184,18 +11073,6 @@ static int tavil_probe(struct platform_device *pdev) } schedule_work(&tavil->tavil_add_child_devices_work); -#ifdef CONFIG_SOUND_CONTROL - sound_control_kobj = kobject_create_and_add("sound_control", kernel_kobj); - if (sound_control_kobj == NULL) { - pr_warn("%s kobject create failed!\n", __func__); - } - - ret = sysfs_create_group(sound_control_kobj, &sound_control_attr_group); - if (ret) { - pr_warn("%s sysfs file create failed!\n", __func__); - } -#endif - return ret; err_cdc_reg: diff --git a/techpack/audio/asoc/codecs/wcd9xxx-common-v2.c b/techpack/audio/asoc/codecs/wcd9xxx-common-v2.c index 478c0c6d72e6..934519c9adee 100644 --- a/techpack/audio/asoc/codecs/wcd9xxx-common-v2.c +++ b/techpack/audio/asoc/codecs/wcd9xxx-common-v2.c @@ -794,6 +794,7 @@ static void wcd_clsh_state_hph_ear(struct snd_soc_codec *codec, wcd_clsh_set_gain_path(codec, mode); wcd_clsh_set_flyback_mode(codec, mode); wcd_clsh_set_buck_mode(codec, mode); + wcd_clsh_set_hph_mode(codec, mode); } } else { if (req_state == WCD_CLSH_STATE_EAR) { diff --git a/techpack/audio/asoc/codecs/wcd_cpe_services.c b/techpack/audio/asoc/codecs/wcd_cpe_services.c index fc8242a91275..e584cf05a6ef 100644 --- a/techpack/audio/asoc/codecs/wcd_cpe_services.c +++ b/techpack/audio/asoc/codecs/wcd_cpe_services.c @@ -654,7 +654,7 @@ static void cpe_notify_cmi_client(struct cpe_info *t_info, u8 *payload, hdr = CMI_GET_HEADER(payload); service = CMI_HDR_GET_SERVICE(hdr); - notif.event = CPE_SVC_CMI_MSG; + notif.event = CMI_API_MSG; notif.result = result; notif.message = payload; @@ -1170,7 +1170,7 @@ static enum cpe_process_result cpe_boot_complete( } pr_debug("%s: boot complete\n", __func__); - return CPE_SVC_SUCCESS; + return CPE_PROC_SUCCESS; } static enum cpe_process_result cpe_process_send_msg( diff --git a/techpack/audio/asoc/codecs/wsa881x.c b/techpack/audio/asoc/codecs/wsa881x.c index 5d0a15a7b8fc..d2a3938a5a2c 100644 --- a/techpack/audio/asoc/codecs/wsa881x.c +++ b/techpack/audio/asoc/codecs/wsa881x.c @@ -389,7 +389,7 @@ static ssize_t wsa881x_swrslave_reg_show(char __user *ubuf, size_t count, continue; swr_read(dbgwsa881x->swr_slave, devnum, i, ®_val, 1); - len = snprintf(tmp_buf, sizeof(tmp_buf), "0x%.3x: 0x%.2x\n", i, + len = snprintf(tmp_buf, 25, "0x%.3x: 0x%.2x\n", i, (reg_val & 0xFF)); if ((total + len) >= count - 1) break; diff --git a/techpack/audio/asoc/elliptic/elliptic.c b/techpack/audio/asoc/elliptic/elliptic.c index aa38a6e33112..08bce9758a75 100644 --- a/techpack/audio/asoc/elliptic/elliptic.c +++ b/techpack/audio/asoc/elliptic/elliptic.c @@ -1,6 +1,5 @@ /** * Copyright Elliptic Labs -* Copyright (C) 2019 XiaoMi, Inc. * */ /* #define DEBUG */ diff --git a/techpack/audio/asoc/elliptic/elliptic_device.h b/techpack/audio/asoc/elliptic/elliptic_device.h index cd113c5cad69..78159257cead 100644 --- a/techpack/audio/asoc/elliptic/elliptic_device.h +++ b/techpack/audio/asoc/elliptic/elliptic_device.h @@ -1,6 +1,5 @@ /** * Copyright Elliptic Labs - * Copyright (C) 2019 XiaoMi, Inc. * */ diff --git a/techpack/audio/asoc/elliptic/io_modules/msm/elliptic_data_msm_io.c b/techpack/audio/asoc/elliptic/io_modules/msm/elliptic_data_msm_io.c index 96444ea14a4d..defe5b6713f5 100644 --- a/techpack/audio/asoc/elliptic/io_modules/msm/elliptic_data_msm_io.c +++ b/techpack/audio/asoc/elliptic/io_modules/msm/elliptic_data_msm_io.c @@ -1,6 +1,5 @@ /** * Copyright Elliptic Labs - * Copyright (C) 2019 XiaoMi, Inc. * */ diff --git a/techpack/audio/asoc/elliptic/io_modules/userspace/elliptic_data_userspace_ctrl.c b/techpack/audio/asoc/elliptic/io_modules/userspace/elliptic_data_userspace_ctrl.c index ff069655bd68..466de4e48d59 100644 --- a/techpack/audio/asoc/elliptic/io_modules/userspace/elliptic_data_userspace_ctrl.c +++ b/techpack/audio/asoc/elliptic/io_modules/userspace/elliptic_data_userspace_ctrl.c @@ -1,6 +1,5 @@ /** * Copyright Elliptic Labs - * Copyright (C) 2019 XiaoMi, Inc. * */ diff --git a/techpack/audio/asoc/elliptic/io_modules/userspace/elliptic_data_userspace_io.c b/techpack/audio/asoc/elliptic/io_modules/userspace/elliptic_data_userspace_io.c index d33d1fb1251e..b4dde372b685 100644 --- a/techpack/audio/asoc/elliptic/io_modules/userspace/elliptic_data_userspace_io.c +++ b/techpack/audio/asoc/elliptic/io_modules/userspace/elliptic_data_userspace_io.c @@ -1,6 +1,5 @@ /** * Copyright Elliptic Labs - * Copyright (C) 2019 XiaoMi, Inc. * */ diff --git a/techpack/audio/asoc/elliptic/io_modules/userspace_test/Makefile b/techpack/audio/asoc/elliptic/io_modules/userspace_test/Makefile deleted file mode 100644 index 907ddc20a1d9..000000000000 --- a/techpack/audio/asoc/elliptic/io_modules/userspace_test/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -# TODO: add config parameter for which io module to build -#obj-y += elliptic_data_io.o diff --git a/techpack/audio/asoc/elliptic/io_modules/userspace_test/elliptic_data_io.c b/techpack/audio/asoc/elliptic/io_modules/userspace_test/elliptic_data_io.c deleted file mode 100644 index 596fddc22b34..000000000000 --- a/techpack/audio/asoc/elliptic/io_modules/userspace_test/elliptic_data_io.c +++ /dev/null @@ -1,123 +0,0 @@ -/** - * Copyright Elliptic Labs - * Copyright (C) 2019 XiaoMi, Inc. - * - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "elliptic_data_io.h" -#include "elliptic_device.h" - - -#define USE_IRQ 11 - -static struct task_struct *simulating_task; -static atomic_t cancel; - -struct elliptic_data_io_state -{ -}; -#define BUFFER_SIZE 128 - -static int32_t output_buffer[BUFFER_SIZE]; - -irqreturn_t irq_handler(int irq, void *dev_id) { - int result; - - result = elliptic_data_push(ELLIPTIC_ALL_DEVICES, (const char*)output_buffer, BUFFER_SIZE * sizeof(int32_t)); - return 0; -} - - -static void fill_buffer(int32_t *buffer, size_t len, int32_t value) -{ - size_t i; - - for (i = 0; i < len; ++i) - buffer[i] = value; -} - - -int simulating_thread(void *context) -{ - static int32_t count; - int result; - - count = 0; - msleep(100); - - pr_debug("%s\n", __func__); - while (atomic_read(&cancel) == 0) - { - if (kthread_should_stop()) - do_exit(0); - - fill_buffer(output_buffer, BUFFER_SIZE, count); - - ++count; - if (result != 0) - { - pr_warn("failed to push data\n"); - } - asm("int $0x3B"); // Corresponding to irq 11 - msleep(0); - } - return 0; -} - -int32_t elliptic_data_io_write(uint32_t message_id, const char *data, - size_t data_size) { - return 0; - } - -int32_t elliptic_data_io_transact(uint32_t message_id, const char *data, - size_t data_size, char *output_data, size_t output_data_size) { - return 0; -} - - -void elliptic_data_io_cancel(struct elliptic_data *elliptic_data) -{ - atomic_set(&elliptic_data->abort_io, 1); - wake_up_interruptible(&elliptic_data->fifo_isr_not_empty); -} - - -int elliptic_data_io_initialize() -{ - pr_debug("%s\n", __func__); - atomic_set(&cancel, 0); - simulating_task = kthread_run(&simulating_thread, NULL, "el_simulating_thread"); - - - if (request_irq(USE_IRQ, irq_handler, IRQF_SHARED, "my_device", (void *)(irq_handler))) { - printk(KERN_INFO "my_device: cannot register IRQ "); - return -1; - } - - return 0; -} - -int elliptic_data_io_cleanup() -{ - free_irq(USE_IRQ, (void *)(irq_handler)); - kthread_stop(simulating_task); - atomic_set(&cancel, 1); - msleep(200); - return 0; -} \ No newline at end of file diff --git a/techpack/audio/asoc/msm-audio-effects-q6-v2.c b/techpack/audio/asoc/msm-audio-effects-q6-v2.c index c195746e5af6..53428ebf4eed 100644 --- a/techpack/audio/asoc/msm-audio-effects-q6-v2.c +++ b/techpack/audio/asoc/msm-audio-effects-q6-v2.c @@ -82,7 +82,7 @@ int msm_audio_effects_enable_extn(struct audio_client *ac, if (effects->virtualizer.enable_flag) q6asm_send_audio_effects_params(ac, (char *)&updt_params[0], params_length); - memset(updt_params, 0, sizeof(updt_params)); + memset(updt_params, 0, MAX_ENABLE_CMD_SIZE); params_length = 0; updt_params[0] = AUDPROC_MODULE_ID_BASS_BOOST; updt_params[1] = AUDPROC_PARAM_ID_ENABLE; @@ -92,7 +92,7 @@ int msm_audio_effects_enable_extn(struct audio_client *ac, if (effects->bass_boost.enable_flag) q6asm_send_audio_effects_params(ac, (char *)&updt_params[0], params_length); - memset(updt_params, 0, sizeof(updt_params)); + memset(updt_params, 0, MAX_ENABLE_CMD_SIZE); params_length = 0; updt_params[0] = AUDPROC_MODULE_ID_POPLESS_EQUALIZER; updt_params[1] = AUDPROC_PARAM_ID_ENABLE; diff --git a/techpack/audio/asoc/msm-dai-fe.c b/techpack/audio/asoc/msm-dai-fe.c index 4140d47dda9c..04232456191d 100644 --- a/techpack/audio/asoc/msm-dai-fe.c +++ b/techpack/audio/asoc/msm-dai-fe.c @@ -1,5 +1,5 @@ /* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. - * Copyright (C) 2019 XiaoMi, Inc. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/techpack/audio/asoc/msm-dai-q6-v2.c b/techpack/audio/asoc/msm-dai-q6-v2.c index 7785420bf752..2ab7da5e3d15 100644 --- a/techpack/audio/asoc/msm-dai-q6-v2.c +++ b/techpack/audio/asoc/msm-dai-q6-v2.c @@ -33,6 +33,8 @@ #define MSM_DAI_QUAT_AUXPCM_DT_DEV_ID 4 #define MSM_DAI_QUIN_AUXPCM_DT_DEV_ID 5 +#define MSM_DAI_TWS_CHANNEL_MODE_ONE 1 +#define MSM_DAI_TWS_CHANNEL_MODE_TWO 2 #define spdif_clock_value(rate) (2*rate*32*2) #define CHANNEL_STATUS_SIZE 24 @@ -2378,6 +2380,12 @@ static const struct soc_enum afe_input_bit_format_enum[] = { SOC_ENUM_SINGLE_EXT(3, afe_input_bit_format_text), }; +static const char *const tws_chs_mode_text[] = {"Zero", "One", "Two"}; + +static const struct soc_enum tws_chs_mode_enum[] = { + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(tws_chs_mode_text), tws_chs_mode_text), +}; + static int msm_dai_q6_afe_input_channel_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { @@ -2406,6 +2414,61 @@ static int msm_dai_q6_afe_input_channel_put(struct snd_kcontrol *kcontrol, return 0; } +static int msm_dai_q6_tws_channel_mode_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dai *dai = kcontrol->private_data; + struct msm_dai_q6_dai_data *dai_data = NULL; + + if (dai) + dai_data = dev_get_drvdata(dai->dev); + + if (dai_data) { + ucontrol->value.integer.value[0] = + dai_data->enc_config.mono_mode; + pr_debug("%s:tws channel mode = %d\n", + __func__, dai_data->enc_config.mono_mode); + } + + return 0; +} + +static int msm_dai_q6_tws_channel_mode_put(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + struct snd_soc_dai *dai = kcontrol->private_data; + struct msm_dai_q6_dai_data *dai_data = NULL; + int ret = 0; + + if (dai) + dai_data = dev_get_drvdata(dai->dev); + + if (dai_data && (dai_data->enc_config.format == ENC_FMT_APTX)) { + if (test_bit(STATUS_PORT_STARTED, dai_data->status_mask)) { + ret = afe_set_tws_channel_mode(dai->id, + ucontrol->value.integer.value[0]); + if (ret < 0) { + pr_err("%s: channel mode setting failed for TWS\n", + __func__); + goto exit; + } else { + pr_debug("%s: updating tws channel mode : %d\n", + __func__, dai_data->enc_config.mono_mode); + } + } + if (ucontrol->value.integer.value[0] == + MSM_DAI_TWS_CHANNEL_MODE_ONE || + ucontrol->value.integer.value[0] == + MSM_DAI_TWS_CHANNEL_MODE_TWO) + dai_data->enc_config.mono_mode = + ucontrol->value.integer.value[0]; + else + return -EINVAL; + } +exit: + return ret; +} + static int msm_dai_q6_afe_input_bit_format_get( struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) @@ -2514,6 +2577,9 @@ static const struct snd_kcontrol_new afe_enc_config_controls[] = { 0, 0, 1, 0, msm_dai_q6_afe_scrambler_mode_get, msm_dai_q6_afe_scrambler_mode_put), + SOC_ENUM_EXT("TWS Channel Mode", tws_chs_mode_enum[0], + msm_dai_q6_tws_channel_mode_get, + msm_dai_q6_tws_channel_mode_put) }; static int msm_dai_q6_afe_dec_cfg_info(struct snd_kcontrol *kcontrol, @@ -2746,6 +2812,9 @@ static int msm_dai_q6_dai_probe(struct snd_soc_dai *dai) rc = snd_ctl_add(dai->component->card->snd_card, snd_ctl_new1(&afe_enc_config_controls[3], dai_data)); + rc = snd_ctl_add(dai->component->card->snd_card, + snd_ctl_new1(&afe_enc_config_controls[4], + dai)); rc = snd_ctl_add(dai->component->card->snd_card, snd_ctl_new1(&avd_drift_config_controls[2], dai)); diff --git a/techpack/audio/asoc/msm-pcm-loopback-v2.c b/techpack/audio/asoc/msm-pcm-loopback-v2.c index 3b6b3a840eab..61318050162f 100644 --- a/techpack/audio/asoc/msm-pcm-loopback-v2.c +++ b/techpack/audio/asoc/msm-pcm-loopback-v2.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2013-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -137,6 +137,7 @@ static int msm_loopback_session_mute_put(struct snd_kcontrol *kcontrol, goto done; } + mutex_lock(&loopback_session_lock); pr_debug("%s: mute=%d\n", __func__, mute); hfp_tx_mute = mute; for (n = 0; n < LOOPBACK_SESSION_MAX; n++) { @@ -149,6 +150,7 @@ static int msm_loopback_session_mute_put(struct snd_kcontrol *kcontrol, pr_err("%s: Send mute command failed rc=%d\n", __func__, ret); } + mutex_unlock(&loopback_session_lock); done: return ret; } @@ -351,6 +353,7 @@ static void stop_pcm(struct msm_pcm_loopback *pcm) if (pcm->audio_client == NULL) return; + mutex_lock(&loopback_session_lock); q6asm_cmd(pcm->audio_client, CMD_CLOSE); if (pcm->playback_substream != NULL) { @@ -365,6 +368,7 @@ static void stop_pcm(struct msm_pcm_loopback *pcm) } q6asm_audio_client_free(pcm->audio_client); pcm->audio_client = NULL; + mutex_unlock(&loopback_session_lock); } static int msm_pcm_close(struct snd_pcm_substream *substream) @@ -495,12 +499,15 @@ static int msm_pcm_volume_ctl_put(struct snd_kcontrol *kcontrol, rc = -ENODEV; goto exit; } + mutex_lock(&loopback_session_lock); prtd = substream->runtime->private_data; if (!prtd) { rc = -ENODEV; + mutex_unlock(&loopback_session_lock); goto exit; } rc = pcm_loopback_set_volume(prtd, volume); + mutex_unlock(&loopback_session_lock); exit: return rc; @@ -521,12 +528,15 @@ static int msm_pcm_volume_ctl_get(struct snd_kcontrol *kcontrol, rc = -ENODEV; goto exit; } + mutex_lock(&loopback_session_lock); prtd = substream->runtime->private_data; if (!prtd) { rc = -ENODEV; + mutex_unlock(&loopback_session_lock); goto exit; } ucontrol->value.integer.value[0] = prtd->volume; + mutex_unlock(&loopback_session_lock); exit: return rc; diff --git a/techpack/audio/asoc/msm-pcm-q6-noirq.c b/techpack/audio/asoc/msm-pcm-q6-noirq.c old mode 100644 new mode 100755 index 386b52a65fcc..48e5a1e20623 --- a/techpack/audio/asoc/msm-pcm-q6-noirq.c +++ b/techpack/audio/asoc/msm-pcm-q6-noirq.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -577,6 +577,7 @@ static int msm_pcm_prepare(struct snd_pcm_substream *substream) static int msm_pcm_close(struct snd_pcm_substream *substream) { + struct msm_plat_data *pdata = NULL; struct snd_pcm_runtime *runtime = substream->runtime; struct snd_soc_pcm_runtime *soc_prtd = substream->private_data; struct msm_audio *prtd = runtime->private_data; @@ -585,6 +586,21 @@ static int msm_pcm_close(struct snd_pcm_substream *substream) int dir = 0; int ret = 0; + if (!soc_prtd) { + pr_debug("%s private_data not found\n", + __func__); + return 0; + } + + pdata = (struct msm_plat_data *) + dev_get_drvdata(soc_prtd->platform->dev); + if (!pdata) { + pr_err("%s: pdata not found\n", __func__); + return -ENODEV; + } + + mutex_lock(&pdata->lock); + if (ac) { if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) dir = IN; @@ -619,6 +635,7 @@ static int msm_pcm_close(struct snd_pcm_substream *substream) SNDRV_PCM_STREAM_CAPTURE); kfree(prtd); runtime->private_data = NULL; + mutex_unlock(&pdata->lock); return 0; } @@ -643,8 +660,10 @@ static int msm_pcm_volume_ctl_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_pcm_volume *vol = snd_kcontrol_chip(kcontrol); + struct msm_plat_data *pdata = NULL; struct snd_pcm_substream *substream = vol->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream; + struct snd_soc_pcm_runtime *soc_prtd = NULL; struct msm_audio *prtd; pr_debug("%s\n", __func__); @@ -652,13 +671,24 @@ static int msm_pcm_volume_ctl_get(struct snd_kcontrol *kcontrol, pr_err("%s substream not found\n", __func__); return -ENODEV; } - if (!substream->runtime) { - pr_debug("%s substream runtime not found\n", __func__); + soc_prtd = substream->private_data; + if (!substream->runtime || !soc_prtd) { + pr_debug("%s substream runtime or private_data not found\n", + __func__); return 0; } + + pdata = (struct msm_plat_data *) + dev_get_drvdata(soc_prtd->platform->dev); + if (!pdata) { + pr_err("%s: pdata not found\n", __func__); + return -ENODEV; + } + mutex_lock(&pdata->lock); prtd = substream->runtime->private_data; if (prtd) ucontrol->value.integer.value[0] = prtd->volume; + mutex_unlock(&pdata->lock); return 0; } @@ -667,8 +697,10 @@ static int msm_pcm_volume_ctl_put(struct snd_kcontrol *kcontrol, { int rc = 0; struct snd_pcm_volume *vol = snd_kcontrol_chip(kcontrol); + struct msm_plat_data *pdata = NULL; struct snd_pcm_substream *substream = vol->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream; + struct snd_soc_pcm_runtime *soc_prtd = NULL; struct msm_audio *prtd; int volume = ucontrol->value.integer.value[0]; @@ -677,15 +709,25 @@ static int msm_pcm_volume_ctl_put(struct snd_kcontrol *kcontrol, pr_err("%s substream not found\n", __func__); return -ENODEV; } - if (!substream->runtime) { - pr_err("%s substream runtime not found\n", __func__); + soc_prtd = substream->private_data; + if (!substream->runtime || !soc_prtd) { + pr_debug("%s substream runtime or private_data not found\n", + __func__); return 0; } + pdata = (struct msm_plat_data *) + dev_get_drvdata(soc_prtd->platform->dev); + if (!pdata) { + pr_err("%s: pdata not found\n", __func__); + return -ENODEV; + } + mutex_lock(&pdata->lock); prtd = substream->runtime->private_data; if (prtd) { rc = msm_pcm_set_volume(prtd, volume); prtd->volume = volume; } + mutex_unlock(&pdata->lock); return rc; } @@ -1228,6 +1270,8 @@ static int msm_pcm_probe(struct platform_device *pdev) pdata->perf_mode = perf_mode; + mutex_init(&pdata->lock); + dev_set_drvdata(&pdev->dev, pdata); dev_dbg(&pdev->dev, "%s: dev name %s\n", @@ -1248,6 +1292,7 @@ static int msm_pcm_remove(struct platform_device *pdev) dev_dbg(&pdev->dev, "Pull mode remove\n"); pdata = dev_get_drvdata(&pdev->dev); + mutex_destroy(&pdata->lock); devm_kfree(&pdev->dev, pdata); snd_soc_unregister_platform(&pdev->dev); return 0; diff --git a/techpack/audio/asoc/msm-pcm-q6-v2.c b/techpack/audio/asoc/msm-pcm-q6-v2.c old mode 100644 new mode 100755 index 559d91a2291d..cda6b4ccd982 --- a/techpack/audio/asoc/msm-pcm-q6-v2.c +++ b/techpack/audio/asoc/msm-pcm-q6-v2.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -836,6 +837,14 @@ static int msm_pcm_playback_close(struct snd_pcm_substream *substream) pr_debug("%s: cmd_pending 0x%lx\n", __func__, prtd->cmd_pending); + pdata = (struct msm_plat_data *) + dev_get_drvdata(soc_prtd->platform->dev); + if (!pdata) { + pr_err("%s: platform data is NULL\n", __func__); + return -EINVAL; + } + + mutex_lock(&pdata->lock); if (prtd->audio_client) { dir = IN; @@ -843,8 +852,6 @@ static int msm_pcm_playback_close(struct snd_pcm_substream *substream) * Unvote to downgrade the Rx thread priority from * RT Thread for Low-Latency use case. */ - pdata = (struct msm_plat_data *) - dev_get_drvdata(soc_prtd->platform->dev); if (pdata) { if (pdata->perf_mode == LOW_LATENCY_PCM_MODE) apr_end_rx_rt(prtd->audio_client->apr); @@ -878,6 +885,7 @@ static int msm_pcm_playback_close(struct snd_pcm_substream *substream) msm_adsp_clean_mixer_ctl_pp_event_queue(soc_prtd); kfree(prtd); runtime->private_data = NULL; + mutex_unlock(&pdata->lock); return 0; } @@ -971,9 +979,20 @@ static int msm_pcm_capture_close(struct snd_pcm_substream *substream) struct snd_pcm_runtime *runtime = substream->runtime; struct snd_soc_pcm_runtime *soc_prtd = substream->private_data; struct msm_audio *prtd = runtime->private_data; + struct msm_plat_data *pdata; int dir = OUT; pr_debug("%s\n", __func__); + + pdata = (struct msm_plat_data *) + dev_get_drvdata(soc_prtd->platform->dev); + if (!pdata) { + pr_err("%s: platform data is NULL\n", __func__); + return -EINVAL; + } + + mutex_lock(&pdata->lock); + if (prtd->audio_client) { q6asm_cmd(prtd->audio_client, CMD_CLOSE); q6asm_audio_client_buf_free_contiguous(dir, @@ -985,6 +1004,7 @@ static int msm_pcm_capture_close(struct snd_pcm_substream *substream) SNDRV_PCM_STREAM_CAPTURE); kfree(prtd); runtime->private_data = NULL; + mutex_unlock(&pdata->lock); return 0; } @@ -1123,10 +1143,10 @@ static int msm_pcm_adsp_stream_cmd_put(struct snd_kcontrol *kcontrol, if (!pdata) { pr_err("%s pdata is NULL\n", __func__); - ret = -ENODEV; - goto done; + return -ENODEV; } + mutex_lock(&pdata->lock); substream = pdata->pcm[kcontrol->private_value]-> streams[SNDRV_PCM_STREAM_PLAYBACK].substream; if (!substream) { @@ -1185,6 +1205,7 @@ static int msm_pcm_adsp_stream_cmd_put(struct snd_kcontrol *kcontrol, pr_err("%s: failed to send stream event cmd, err = %d\n", __func__, ret); done: + mutex_unlock(&pdata->lock); return ret; } @@ -1322,8 +1343,10 @@ static int msm_pcm_volume_ctl_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { struct snd_pcm_volume *vol = snd_kcontrol_chip(kcontrol); + struct msm_plat_data *pdata = NULL; struct snd_pcm_substream *substream = vol->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream; + struct snd_soc_pcm_runtime *soc_prtd = NULL; struct msm_audio *prtd; pr_debug("%s\n", __func__); @@ -1331,13 +1354,23 @@ static int msm_pcm_volume_ctl_get(struct snd_kcontrol *kcontrol, pr_err("%s substream not found\n", __func__); return -ENODEV; } - if (!substream->runtime) { - pr_debug("%s substream runtime not found\n", __func__); + soc_prtd = substream->private_data; + if (!substream->runtime || !soc_prtd) { + pr_debug("%s substream runtime or private_data not found\n", + __func__); return 0; } + pdata = (struct msm_plat_data *) + dev_get_drvdata(soc_prtd->platform->dev); + if (!pdata) { + pr_err("%s: pdata not found\n", __func__); + return -ENODEV; + } + mutex_lock(&pdata->lock); prtd = substream->runtime->private_data; if (prtd) ucontrol->value.integer.value[0] = prtd->volume; + mutex_unlock(&pdata->lock); return 0; } @@ -1348,6 +1381,8 @@ static int msm_pcm_volume_ctl_put(struct snd_kcontrol *kcontrol, struct snd_pcm_volume *vol = snd_kcontrol_chip(kcontrol); struct snd_pcm_substream *substream = vol->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream; + struct snd_soc_pcm_runtime *soc_prtd = NULL; + struct msm_plat_data *pdata = NULL; struct msm_audio *prtd; int volume = ucontrol->value.integer.value[0]; @@ -1360,11 +1395,27 @@ static int msm_pcm_volume_ctl_put(struct snd_kcontrol *kcontrol, pr_err("%s substream runtime not found\n", __func__); return 0; } + + soc_prtd = substream->private_data; + if (!soc_prtd) { + pr_err("%s: soc_prtd is NULL\n", __func__); + return -ENODEV; + } + + pdata = (struct msm_plat_data *) + dev_get_drvdata(soc_prtd->platform->dev); + if (!pdata) { + pr_err("%s: platform data is NULL\n", __func__); + return -EINVAL; + } + + mutex_lock(&pdata->lock); prtd = substream->runtime->private_data; if (prtd) { rc = msm_pcm_set_volume(prtd, volume); prtd->volume = volume; } + mutex_unlock(&pdata->lock); return rc; } @@ -1423,9 +1474,11 @@ static int msm_pcm_compress_ctl_get(struct snd_kcontrol *kcontrol, pr_debug("%s substream runtime not found\n", __func__); return 0; } + mutex_lock(&pdata->lock); prtd = substream->runtime->private_data; if (prtd) ucontrol->value.integer.value[0] = prtd->compress_enable; + mutex_unlock(&pdata->lock); return 0; } @@ -1455,12 +1508,14 @@ static int msm_pcm_compress_ctl_put(struct snd_kcontrol *kcontrol, pr_err("%s substream runtime not found\n", __func__); return 0; } + mutex_lock(&pdata->lock); prtd = substream->runtime->private_data; if (prtd) { pr_debug("%s: setting compress flag to 0x%x\n", __func__, compress); prtd->compress_enable = compress; } + mutex_unlock(&pdata->lock); return rc; } @@ -1527,15 +1582,32 @@ static int msm_pcm_chmap_ctl_put(struct snd_kcontrol *kcontrol, struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol); unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); struct snd_pcm_substream *substream; + struct snd_soc_pcm_runtime *soc_prtd = NULL; + struct msm_plat_data *pdata = NULL; struct msm_audio *prtd; pr_debug("%s", __func__); substream = snd_pcm_chmap_substream(info, idx); if (!substream) return -ENODEV; + if (!substream->runtime) return 0; + soc_prtd = substream->private_data; + if (!soc_prtd) { + pr_err("%s: soc_prtd is NULL\n", __func__); + return -ENODEV; + } + + pdata = (struct msm_plat_data *) + dev_get_drvdata(soc_prtd->platform->dev); + if (!pdata) { + pr_err("%s: platform data is NULL\n", __func__); + return -EINVAL; + } + + mutex_lock(&pdata->lock); prtd = substream->runtime->private_data; if (prtd) { prtd->set_channel_map = true; @@ -1543,6 +1615,7 @@ static int msm_pcm_chmap_ctl_put(struct snd_kcontrol *kcontrol, prtd->channel_map[i] = (char)(ucontrol->value.integer.value[i]); } + mutex_unlock(&pdata->lock); return 0; } @@ -1553,17 +1626,34 @@ static int msm_pcm_chmap_ctl_get(struct snd_kcontrol *kcontrol, struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol); unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id); struct snd_pcm_substream *substream; + struct snd_soc_pcm_runtime *soc_prtd = NULL; + struct msm_plat_data *pdata = NULL; struct msm_audio *prtd; pr_debug("%s", __func__); substream = snd_pcm_chmap_substream(info, idx); if (!substream) return -ENODEV; + memset(ucontrol->value.integer.value, 0, sizeof(ucontrol->value.integer.value)); if (!substream->runtime) return 0; /* no channels set */ + soc_prtd = substream->private_data; + if (!soc_prtd) { + pr_err("%s: soc_prtd is NULL\n", __func__); + return -ENODEV; + } + + pdata = (struct msm_plat_data *) + dev_get_drvdata(soc_prtd->platform->dev); + if (!pdata) { + pr_err("%s: platform data is NULL\n", __func__); + return -EINVAL; + } + + mutex_lock(&pdata->lock); prtd = substream->runtime->private_data; if (prtd && prtd->set_channel_map == true) { @@ -1575,6 +1665,7 @@ static int msm_pcm_chmap_ctl_get(struct snd_kcontrol *kcontrol, ucontrol->value.integer.value[i] = 0; } + mutex_unlock(&pdata->lock); return 0; } @@ -1975,7 +2066,7 @@ static int msm_pcm_probe(struct platform_device *pdev) } else { pdata->perf_mode = LEGACY_PCM_MODE; } - + mutex_init(&pdata->lock); dev_set_drvdata(&pdev->dev, pdata); @@ -1990,6 +2081,7 @@ static int msm_pcm_remove(struct platform_device *pdev) struct msm_plat_data *pdata; pdata = dev_get_drvdata(&pdev->dev); + mutex_destroy(&pdata->lock); kfree(pdata); snd_soc_unregister_platform(&pdev->dev); return 0; diff --git a/techpack/audio/asoc/msm-pcm-q6-v2.h b/techpack/audio/asoc/msm-pcm-q6-v2.h index 810a0082d5b3..43fee549709d 100644 --- a/techpack/audio/asoc/msm-pcm-q6-v2.h +++ b/techpack/audio/asoc/msm-pcm-q6-v2.h @@ -126,6 +126,7 @@ struct output_meta_data_st { struct msm_plat_data { int perf_mode; struct snd_pcm *pcm[MSM_FRONTEND_DAI_MAX]; + struct mutex lock; }; #endif /*_MSM_PCM_H*/ diff --git a/techpack/audio/asoc/msm-pcm-routing-v2.c b/techpack/audio/asoc/msm-pcm-routing-v2.c index 4e460f30417b..2554adfdbe06 100644 --- a/techpack/audio/asoc/msm-pcm-routing-v2.c +++ b/techpack/audio/asoc/msm-pcm-routing-v2.c @@ -1,5 +1,5 @@ -/* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. - * Copyright (C) 2019 XiaoMi, Inc. +/* Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -84,8 +84,6 @@ static uint32_t voc_session_id = ALL_SESSION_VSID; static int msm_route_ext_ec_ref; static int voice_ext_ec_ref; static int voip_ext_ec_ref; -static int wakeup_ext_ec_ref = 0; -static int voip_ext_ec_common_ref = 0; static bool is_custom_stereo_on; static bool is_ds2_on; static bool swap_ch; @@ -1806,13 +1804,14 @@ static int msm_routing_get_audio_mixer(struct snd_kcontrol *kcontrol, struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value; - if (test_bit(mc->shift, &msm_bedais[mc->reg].fe_sessions[0])) + if (test_bit(mc->rshift, &msm_bedais[mc->shift].fe_sessions[0])) ucontrol->value.integer.value[0] = 1; else ucontrol->value.integer.value[0] = 0; - pr_debug("%s: reg %x shift %x val %ld\n", __func__, mc->reg, mc->shift, - ucontrol->value.integer.value[0]); + pr_debug("%s: shift %x rshift %x val %ld\n", __func__, + mc->shift, mc->rshift, + ucontrol->value.integer.value[0]); return 0; } @@ -1827,13 +1826,13 @@ static int msm_routing_put_audio_mixer(struct snd_kcontrol *kcontrol, struct snd_soc_dapm_update *update = NULL; if (ucontrol->value.integer.value[0] && - msm_pcm_routing_route_is_set(mc->reg, mc->shift) == false) { - msm_pcm_routing_process_audio(mc->reg, mc->shift, 1); + msm_pcm_routing_route_is_set(mc->shift, mc->rshift) == false) { + msm_pcm_routing_process_audio(mc->shift, mc->rshift, 1); snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, 1, update); } else if (!ucontrol->value.integer.value[0] && - msm_pcm_routing_route_is_set(mc->reg, mc->shift) == true) { - msm_pcm_routing_process_audio(mc->reg, mc->shift, 0); + msm_pcm_routing_route_is_set(mc->shift, mc->rshift) == true) { + msm_pcm_routing_process_audio(mc->shift, mc->rshift, 0); snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, 0, update); } @@ -1847,12 +1846,13 @@ static int msm_routing_get_listen_mixer(struct snd_kcontrol *kcontrol, struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value; - if (test_bit(mc->shift, &msm_bedais[mc->reg].fe_sessions[0])) + if (test_bit(mc->rshift, &msm_bedais[mc->shift].fe_sessions[0])) ucontrol->value.integer.value[0] = 1; else ucontrol->value.integer.value[0] = 0; - pr_debug("%s: reg %x shift %x val %ld\n", __func__, mc->reg, mc->shift, + pr_debug("%s: shift %x rshift %x val %ld\n", __func__, + mc->shift, mc->rshift, ucontrol->value.integer.value[0]); return 0; @@ -1867,17 +1867,19 @@ static int msm_routing_put_listen_mixer(struct snd_kcontrol *kcontrol, (struct soc_mixer_control *)kcontrol->private_value; struct snd_soc_dapm_update *update = NULL; - pr_debug("%s: reg %x shift %x val %ld\n", __func__, mc->reg, mc->shift, + pr_debug("%s: shift %x rshift %x val %ld\n", __func__, + mc->shift, mc->rshift, ucontrol->value.integer.value[0]); if (ucontrol->value.integer.value[0]) { - if (msm_pcm_routing_route_is_set(mc->reg, mc->shift) == false) - msm_pcm_routing_process_audio(mc->reg, mc->shift, 1); + if (msm_pcm_routing_route_is_set(mc->shift, mc->rshift) + == false) + msm_pcm_routing_process_audio(mc->shift, mc->rshift, 1); snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, 1, update); } else if (!ucontrol->value.integer.value[0]) { - if (msm_pcm_routing_route_is_set(mc->reg, mc->shift) == true) - msm_pcm_routing_process_audio(mc->reg, mc->shift, 0); + if (msm_pcm_routing_route_is_set(mc->shift, mc->rshift) == true) + msm_pcm_routing_process_audio(mc->shift, mc->rshift, 0); snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, 0, update); } @@ -1962,14 +1964,15 @@ static int msm_routing_get_voice_mixer(struct snd_kcontrol *kcontrol, mutex_lock(&routing_lock); - if (test_bit(mc->shift, &msm_bedais[mc->reg].fe_sessions[0])) + if (test_bit(mc->rshift, &msm_bedais[mc->shift].fe_sessions[0])) ucontrol->value.integer.value[0] = 1; else ucontrol->value.integer.value[0] = 0; mutex_unlock(&routing_lock); - pr_debug("%s: reg %x shift %x val %ld\n", __func__, mc->reg, mc->shift, + pr_debug("%s: shift %x rshift %x val %ld\n", __func__, + mc->shift, mc->rshift, ucontrol->value.integer.value[0]); return 0; @@ -1985,11 +1988,11 @@ static int msm_routing_put_voice_mixer(struct snd_kcontrol *kcontrol, struct snd_soc_dapm_update *update = NULL; if (ucontrol->value.integer.value[0]) { - msm_pcm_routing_process_voice(mc->reg, mc->shift, 1); + msm_pcm_routing_process_voice(mc->shift, mc->rshift, 1); snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, 1, update); } else { - msm_pcm_routing_process_voice(mc->reg, mc->shift, 0); + msm_pcm_routing_process_voice(mc->shift, mc->rshift, 0); snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, 0, update); } @@ -2005,14 +2008,15 @@ static int msm_routing_get_voice_stub_mixer(struct snd_kcontrol *kcontrol, mutex_lock(&routing_lock); - if (test_bit(mc->shift, &msm_bedais[mc->reg].fe_sessions[0])) + if (test_bit(mc->rshift, &msm_bedais[mc->shift].fe_sessions[0])) ucontrol->value.integer.value[0] = 1; else ucontrol->value.integer.value[0] = 0; mutex_unlock(&routing_lock); - pr_debug("%s: reg %x shift %x val %ld\n", __func__, mc->reg, mc->shift, + pr_debug("%s: shift %x rshift %x val %ld\n", __func__, + mc->shift, mc->rshift, ucontrol->value.integer.value[0]); return 0; @@ -2029,21 +2033,22 @@ static int msm_routing_put_voice_stub_mixer(struct snd_kcontrol *kcontrol, if (ucontrol->value.integer.value[0]) { mutex_lock(&routing_lock); - set_bit(mc->shift, &msm_bedais[mc->reg].fe_sessions[0]); + set_bit(mc->rshift, &msm_bedais[mc->shift].fe_sessions[0]); mutex_unlock(&routing_lock); snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, 1, update); } else { mutex_lock(&routing_lock); - clear_bit(mc->shift, &msm_bedais[mc->reg].fe_sessions[0]); + clear_bit(mc->rshift, &msm_bedais[mc->shift].fe_sessions[0]); mutex_unlock(&routing_lock); snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, 0, update); } - pr_debug("%s: reg %x shift %x val %ld\n", __func__, mc->reg, mc->shift, + pr_debug("%s: shift %x rshift %x val %ld\n", __func__, + mc->shift, mc->rshift, ucontrol->value.integer.value[0]); return 1; @@ -2737,8 +2742,8 @@ static int msm_routing_get_port_mixer(struct snd_kcontrol *kcontrol, struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value; - idx = mc->shift/(sizeof(msm_bedais[mc->reg].port_sessions[0]) * 8); - shift = mc->shift%(sizeof(msm_bedais[mc->reg].port_sessions[0]) * 8); + idx = mc->rshift/(sizeof(msm_bedais[mc->shift].port_sessions[0]) * 8); + shift = mc->rshift%(sizeof(msm_bedais[mc->shift].port_sessions[0]) * 8); if (idx >= BE_DAI_PORT_SESSIONS_IDX_MAX) { pr_err("%s: Invalid idx = %d\n", __func__, idx); @@ -2746,12 +2751,13 @@ static int msm_routing_get_port_mixer(struct snd_kcontrol *kcontrol, } if (test_bit(shift, - (unsigned long *)&msm_bedais[mc->reg].port_sessions[idx])) + (unsigned long *)&msm_bedais[mc->shift].port_sessions[idx])) ucontrol->value.integer.value[0] = 1; else ucontrol->value.integer.value[0] = 0; - pr_debug("%s: reg %x shift %x val %ld\n", __func__, mc->reg, mc->shift, + pr_debug("%s: shift %x rshift %x val %ld\n", __func__, + mc->shift, mc->rshift, ucontrol->value.integer.value[0]); return 0; @@ -2764,28 +2770,28 @@ static int msm_routing_put_port_mixer(struct snd_kcontrol *kcontrol, struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value; - idx = mc->shift/(sizeof(msm_bedais[mc->reg].port_sessions[0]) * 8); - shift = mc->shift%(sizeof(msm_bedais[mc->reg].port_sessions[0]) * 8); + idx = mc->rshift/(sizeof(msm_bedais[mc->shift].port_sessions[0]) * 8); + shift = mc->rshift%(sizeof(msm_bedais[mc->shift].port_sessions[0]) * 8); if (idx >= BE_DAI_PORT_SESSIONS_IDX_MAX) { pr_err("%s: Invalid idx = %d\n", __func__, idx); return -EINVAL; } - pr_debug("%s: reg 0x%x shift 0x%x val %ld idx %d reminder shift %d\n", - __func__, mc->reg, mc->shift, + pr_debug("%s: shift 0x%x rshift 0x%x val %ld idx %d reminder shift %d\n", + __func__, mc->shift, mc->rshift, ucontrol->value.integer.value[0], idx, shift); if (ucontrol->value.integer.value[0]) { - afe_loopback(1, msm_bedais[mc->reg].port_id, - msm_bedais[mc->shift].port_id); + afe_loopback(1, msm_bedais[mc->shift].port_id, + msm_bedais[mc->rshift].port_id); set_bit(shift, - (unsigned long *)&msm_bedais[mc->reg].port_sessions[idx]); + (unsigned long *)&msm_bedais[mc->shift].port_sessions[idx]); } else { - afe_loopback(0, msm_bedais[mc->reg].port_id, - msm_bedais[mc->shift].port_id); + afe_loopback(0, msm_bedais[mc->shift].port_id, + msm_bedais[mc->rshift].port_id); clear_bit(shift, - (unsigned long *)&msm_bedais[mc->reg].port_sessions[idx]); + (unsigned long *)&msm_bedais[mc->shift].port_sessions[idx]); } return 1; @@ -3580,16 +3586,9 @@ static const struct snd_kcontrol_new ec_ref_param_controls[] = { static int msm_routing_ec_ref_rx_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { - struct snd_soc_dapm_widget_list *wlist = - dapm_kcontrol_get_wlist(kcontrol); - struct snd_soc_dapm_widget *widget = wlist->widgets[0]; - pr_debug("%s: ec_ref_rx = %d", __func__, msm_route_ec_ref_rx); mutex_lock(&routing_lock); - if (!strncmp(widget->name, "AUDIO_REF_EC_UL10 MUX", strlen("AUDIO_REF_EC_UL10 MUX"))) - ucontrol->value.integer.value[0] = voip_ext_ec_common_ref; - else - ucontrol->value.integer.value[0] = wakeup_ext_ec_ref; + ucontrol->value.integer.value[0] = msm_route_ec_ref_rx; mutex_unlock(&routing_lock); return 0; } @@ -3602,14 +3601,13 @@ static int msm_routing_ec_ref_rx_put(struct snd_kcontrol *kcontrol, snd_soc_dapm_kcontrol_widget(kcontrol); struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; struct snd_soc_dapm_update *update = NULL; - bool state = true; + mutex_lock(&routing_lock); switch (ucontrol->value.integer.value[0]) { case 0: msm_route_ec_ref_rx = 0; ec_ref_port_id = AFE_PORT_INVALID; - state = false; break; case 1: msm_route_ec_ref_rx = 1; @@ -3704,27 +3702,14 @@ static int msm_routing_ec_ref_rx_put(struct snd_kcontrol *kcontrol, pr_err("%s EC ref rx %ld not valid\n", __func__, ucontrol->value.integer.value[0]); ec_ref_port_id = AFE_PORT_INVALID; - state = false; break; } - + adm_ec_ref_rx_id(ec_ref_port_id); pr_debug("%s: msm_route_ec_ref_rx = %d\n", - __func__, msm_route_ec_ref_rx); - - if (!strncmp(widget->name, "AUDIO_REF_EC_UL10 MUX", strlen("AUDIO_REF_EC_UL10 MUX"))) - voip_ext_ec_common_ref = msm_route_ec_ref_rx; - else - wakeup_ext_ec_ref = msm_route_ec_ref_rx; - - if (state || (!state && wakeup_ext_ec_ref == 0 && voip_ext_ec_common_ref == 0)) { - pr_info("%s: update state!\n", __func__); - adm_ec_ref_rx_id(ec_ref_port_id); - mutex_unlock(&routing_lock); - snd_soc_dapm_mux_update_power(widget->dapm, kcontrol, + __func__, msm_route_ec_ref_rx); + mutex_unlock(&routing_lock); + snd_soc_dapm_mux_update_power(widget->dapm, kcontrol, msm_route_ec_ref_rx, e, update); - } else { - mutex_unlock(&routing_lock); - } return 0; } @@ -3818,11 +3803,10 @@ static const struct snd_kcontrol_new ext_ec_ref_mux_ul29 = static int msm_routing_ext_ec_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol) { - struct snd_soc_dapm_widget_list *wlist = - dapm_kcontrol_get_wlist(kcontrol); + struct snd_soc_dapm_widget_list *wlist = dapm_kcontrol_get_wlist(kcontrol); struct snd_soc_dapm_widget *widget = wlist->widgets[0]; - pr_info("%s: ext_ec_ref_rx = %x\n", __func__, msm_route_ext_ec_ref); + pr_debug("%s: ext_ec_ref_rx = %x\n", __func__, msm_route_ext_ec_ref); mutex_lock(&routing_lock); if (!strncmp(widget->name, "VOC_EXT_EC MUX", strlen("VOC_EXT_EC MUX"))) @@ -3852,7 +3836,7 @@ static int msm_routing_ext_ec_put(struct snd_kcontrol *kcontrol, mutex_lock(&routing_lock); msm_route_ext_ec_ref = ucontrol->value.integer.value[0]; - pr_info("%s: %s, value %d\n", __func__, widget->name, msm_route_ext_ec_ref); + pr_debug("%s: %s, value %d\n", __func__, widget->name, msm_route_ext_ec_ref); switch (msm_route_ext_ec_ref) { case EXT_EC_REF_PRI_MI2S_TX: @@ -3923,7582 +3907,9784 @@ static const struct snd_kcontrol_new voip_ext_ec_mux = msm_routing_ext_ec_get, msm_routing_ext_ec_put); static const struct snd_kcontrol_new pri_i2s_rx_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_PRI_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_PRI_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_PRI_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_PRI_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_PRI_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_PRI_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_PRI_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_PRI_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_PRI_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_PRI_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_PRI_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_PRI_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_PRI_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_PRI_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_PRI_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_PRI_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia17", MSM_BACKEND_DAI_PRI_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia17", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia18", MSM_BACKEND_DAI_PRI_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia19", MSM_BACKEND_DAI_PRI_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia28", MSM_BACKEND_DAI_PRI_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia29", MSM_BACKEND_DAI_PRI_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new sec_i2s_rx_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_SEC_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_SEC_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_SEC_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_SEC_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_SEC_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_SEC_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_SEC_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_SEC_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_SEC_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_SEC_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_SEC_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_SEC_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_SEC_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_SEC_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_SEC_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_SEC_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia17", MSM_BACKEND_DAI_SEC_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia17", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia18", MSM_BACKEND_DAI_SEC_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia19", MSM_BACKEND_DAI_SEC_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia28", MSM_BACKEND_DAI_SEC_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia29", MSM_BACKEND_DAI_SEC_I2S_RX, + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new spdif_rx_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_SPDIF_RX, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SPDIF_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_SPDIF_RX, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SPDIF_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_SPDIF_RX, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SPDIF_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_SPDIF_RX, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_SPDIF_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_SPDIF_RX, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_SPDIF_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_SPDIF_RX, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_SPDIF_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_SPDIF_RX, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_SPDIF_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_SPDIF_RX, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_SPDIF_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_SPDIF_RX, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_SPDIF_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_SPDIF_RX, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_SPDIF_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_SPDIF_RX, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_SPDIF_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_SPDIF_RX, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_SPDIF_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_SPDIF_RX, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_SPDIF_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_SPDIF_RX, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_SPDIF_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_SPDIF_RX, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_SPDIF_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_SPDIF_RX, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_SPDIF_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia17", MSM_BACKEND_DAI_SPDIF_RX, + SOC_DOUBLE_EXT("MultiMedia17", SND_SOC_NOPM, + MSM_BACKEND_DAI_SPDIF_RX, MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia18", MSM_BACKEND_DAI_SPDIF_RX, + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_SPDIF_RX, MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia19", MSM_BACKEND_DAI_SPDIF_RX, + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_SPDIF_RX, MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia28", MSM_BACKEND_DAI_SPDIF_RX, + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_SPDIF_RX, MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia29", MSM_BACKEND_DAI_SPDIF_RX, + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_SPDIF_RX, MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new slimbus_2_rx_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_SLIMBUS_2_RX, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_2_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_SLIMBUS_2_RX, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_2_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_SLIMBUS_2_RX, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_2_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_SLIMBUS_2_RX, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_2_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_SLIMBUS_2_RX, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_2_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_SLIMBUS_2_RX, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_2_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_SLIMBUS_2_RX, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_2_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_SLIMBUS_2_RX, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_2_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_SLIMBUS_2_RX, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_2_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_SLIMBUS_2_RX, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_2_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_SLIMBUS_2_RX, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_2_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_SLIMBUS_2_RX, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_2_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_SLIMBUS_2_RX, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_2_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_SLIMBUS_2_RX, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_2_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_SLIMBUS_2_RX, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_2_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_SLIMBUS_2_RX, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_2_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new slimbus_5_rx_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_SLIMBUS_5_RX, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_SLIMBUS_5_RX, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_SLIMBUS_5_RX, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_SLIMBUS_5_RX, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_SLIMBUS_5_RX, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_SLIMBUS_5_RX, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_SLIMBUS_5_RX, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_SLIMBUS_5_RX, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_SLIMBUS_5_RX, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_SLIMBUS_5_RX, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_SLIMBUS_5_RX, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_SLIMBUS_5_RX, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_SLIMBUS_5_RX, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_SLIMBUS_5_RX, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_SLIMBUS_5_RX, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_SLIMBUS_5_RX, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia17", MSM_BACKEND_DAI_SLIMBUS_5_RX, + SOC_DOUBLE_EXT("MultiMedia17", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_RX, MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia18", MSM_BACKEND_DAI_SLIMBUS_5_RX, + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_RX, MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia19", MSM_BACKEND_DAI_SLIMBUS_5_RX, + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_RX, MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia28", MSM_BACKEND_DAI_SLIMBUS_5_RX, + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_RX, MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia29", MSM_BACKEND_DAI_SLIMBUS_5_RX, + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_RX, MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new slimbus_rx_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia17", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("MultiMedia17", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia18", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia19", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia28", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia29", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new mi2s_rx_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia17", MSM_BACKEND_DAI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia17", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia18", MSM_BACKEND_DAI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia19", MSM_BACKEND_DAI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia28", MSM_BACKEND_DAI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia29", MSM_BACKEND_DAI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new quaternary_mi2s_rx_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia17", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia17", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia18", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia19", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia28", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia29", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new quinary_mi2s_rx_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia17", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia17", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia18", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia19", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia28", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia29", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new tertiary_mi2s_rx_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia17", MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia17", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia18", MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia19", MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia28", MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia29", MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new secondary_mi2s_rx2_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_SECONDARY_MI2S_RX_SD1, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX_SD1, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new secondary_mi2s_rx_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia17", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia17", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia18", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia19", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia28", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia29", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new primary_mi2s_rx_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia17", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia17", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia18", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia19", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia28", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia29", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new int0_mi2s_rx_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_INT0_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_INT0_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_INT0_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_INT0_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_INT0_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_INT0_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_INT0_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_INT0_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_INT0_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_INT0_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_INT0_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_INT0_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_INT0_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_INT0_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_INT0_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_INT0_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new int4_mi2s_rx_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_INT4_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_INT4_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_INT4_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_INT4_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_INT4_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_INT4_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_INT4_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_INT4_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_INT4_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_INT4_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_INT4_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_INT4_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_INT4_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_INT4_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_INT4_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_INT4_MI2S_RX, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new hdmi_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_HDMI_RX, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_HDMI_RX, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_HDMI_RX, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_HDMI_RX, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_HDMI_RX, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_HDMI_RX, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_HDMI_RX, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_HDMI_RX, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_HDMI_RX, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_HDMI_RX, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_HDMI_RX, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_HDMI_RX, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_HDMI_RX, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_HDMI_RX, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_HDMI_RX, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_HDMI_RX, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia17", MSM_BACKEND_DAI_HDMI_RX, + SOC_DOUBLE_EXT("MultiMedia17", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia18", MSM_BACKEND_DAI_HDMI_RX, + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia19", MSM_BACKEND_DAI_HDMI_RX, + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia28", MSM_BACKEND_DAI_HDMI_RX, + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia29", MSM_BACKEND_DAI_HDMI_RX, + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new display_port_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_DISPLAY_PORT_RX, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_DISPLAY_PORT_RX, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_DISPLAY_PORT_RX, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_DISPLAY_PORT_RX, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_DISPLAY_PORT_RX, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_DISPLAY_PORT_RX, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_DISPLAY_PORT_RX, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_DISPLAY_PORT_RX, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_DISPLAY_PORT_RX, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_DISPLAY_PORT_RX, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_DISPLAY_PORT_RX, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_DISPLAY_PORT_RX, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_DISPLAY_PORT_RX, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_DISPLAY_PORT_RX, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_DISPLAY_PORT_RX, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_DISPLAY_PORT_RX, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; /* incall music delivery mixer */ static const struct snd_kcontrol_new incall_music_delivery_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_VOICE_PLAYBACK_TX, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VOICE_PLAYBACK_TX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_VOICE_PLAYBACK_TX, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_VOICE_PLAYBACK_TX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_VOICE_PLAYBACK_TX, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_VOICE_PLAYBACK_TX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_VOICE_PLAYBACK_TX, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_VOICE_PLAYBACK_TX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new incall_music2_delivery_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new slimbus_4_rx_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_SLIMBUS_4_RX, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_4_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_SLIMBUS_4_RX, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_4_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_SLIMBUS_4_RX, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_4_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_SLIMBUS_4_RX, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_4_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new slimbus_6_rx_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_SLIMBUS_6_RX, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_SLIMBUS_6_RX, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_SLIMBUS_6_RX, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_SLIMBUS_6_RX, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_SLIMBUS_6_RX, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_SLIMBUS_6_RX, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_SLIMBUS_6_RX, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_SLIMBUS_6_RX, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_SLIMBUS_6_RX, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_SLIMBUS_6_RX, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_SLIMBUS_6_RX, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_SLIMBUS_6_RX, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_SLIMBUS_6_RX, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_SLIMBUS_6_RX, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_SLIMBUS_6_RX, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_SLIMBUS_6_RX, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new slimbus_7_rx_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_SLIMBUS_7_RX, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_SLIMBUS_7_RX, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_SLIMBUS_7_RX, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_SLIMBUS_7_RX, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_SLIMBUS_7_RX, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_SLIMBUS_7_RX, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_SLIMBUS_7_RX, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_SLIMBUS_7_RX, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_SLIMBUS_7_RX, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_SLIMBUS_7_RX, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_SLIMBUS_7_RX, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_SLIMBUS_7_RX, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_SLIMBUS_7_RX, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_SLIMBUS_7_RX, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_SLIMBUS_7_RX, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_SLIMBUS_7_RX, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new usb_audio_rx_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_USB_RX, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_USB_RX, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_USB_RX, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_USB_RX, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_USB_RX, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_USB_RX, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_USB_RX, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_USB_RX, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_USB_RX, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_USB_RX, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_USB_RX, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_USB_RX, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_USB_RX, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_USB_RX, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_USB_RX, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_USB_RX, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new int_bt_sco_rx_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_INT_BT_SCO_RX, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_INT_BT_SCO_RX, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_INT_BT_SCO_RX, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_INT_BT_SCO_RX, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_INT_BT_SCO_RX, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_INT_BT_SCO_RX, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_INT_BT_SCO_RX, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_INT_BT_SCO_RX, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_INT_BT_SCO_RX, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_INT_BT_SCO_RX, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_INT_BT_SCO_RX, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_INT_BT_SCO_RX, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_INT_BT_SCO_RX, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_INT_BT_SCO_RX, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_INT_BT_SCO_RX, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_INT_BT_SCO_RX, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia17", MSM_BACKEND_DAI_INT_BT_SCO_RX, + SOC_DOUBLE_EXT("MultiMedia17", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia18", MSM_BACKEND_DAI_INT_BT_SCO_RX, + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia19", MSM_BACKEND_DAI_INT_BT_SCO_RX, + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia28", MSM_BACKEND_DAI_INT_BT_SCO_RX, + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia29", MSM_BACKEND_DAI_INT_BT_SCO_RX, + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new int_bt_a2dp_rx_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_INT_BT_A2DP_RX, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_A2DP_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_INT_BT_A2DP_RX, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_A2DP_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_INT_BT_A2DP_RX, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_A2DP_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_INT_BT_A2DP_RX, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_A2DP_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_INT_BT_A2DP_RX, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_A2DP_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_INT_BT_A2DP_RX, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_A2DP_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_INT_BT_A2DP_RX, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_A2DP_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_INT_BT_A2DP_RX, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_A2DP_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_INT_BT_A2DP_RX, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_A2DP_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_INT_BT_A2DP_RX, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_A2DP_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_INT_BT_A2DP_RX, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_A2DP_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_INT_BT_A2DP_RX, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_A2DP_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_INT_BT_A2DP_RX, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_A2DP_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_INT_BT_A2DP_RX, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_A2DP_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_INT_BT_A2DP_RX, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_A2DP_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_INT_BT_A2DP_RX, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_A2DP_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new int_fm_rx_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_INT_FM_RX, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_INT_FM_RX, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_INT_FM_RX, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_INT_FM_RX, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_INT_FM_RX, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_INT_FM_RX, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_INT_FM_RX, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_INT_FM_RX, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_INT_FM_RX, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_INT_FM_RX, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_INT_FM_RX, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_INT_FM_RX, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_INT_FM_RX, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_INT_FM_RX, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_INT_FM_RX, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_INT_FM_RX, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia17", MSM_BACKEND_DAI_INT_FM_RX, + SOC_DOUBLE_EXT("MultiMedia17", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia18", MSM_BACKEND_DAI_INT_FM_RX, + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia19", MSM_BACKEND_DAI_INT_FM_RX, + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia28", MSM_BACKEND_DAI_INT_FM_RX, + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia29", MSM_BACKEND_DAI_INT_FM_RX, + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_RX, MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new afe_pcm_rx_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_AFE_PCM_RX, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_AFE_PCM_RX, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_AFE_PCM_RX, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_AFE_PCM_RX, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_AFE_PCM_RX, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_AFE_PCM_RX, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_AFE_PCM_RX, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_AFE_PCM_RX, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_AFE_PCM_RX, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_AFE_PCM_RX, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_AFE_PCM_RX, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_AFE_PCM_RX, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_AFE_PCM_RX, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_AFE_PCM_RX, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_AFE_PCM_RX, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_AFE_PCM_RX, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia17", MSM_BACKEND_DAI_AFE_PCM_RX, + SOC_DOUBLE_EXT("MultiMedia17", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia18", MSM_BACKEND_DAI_AFE_PCM_RX, + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia19", MSM_BACKEND_DAI_AFE_PCM_RX, + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia28", MSM_BACKEND_DAI_AFE_PCM_RX, + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia29", MSM_BACKEND_DAI_AFE_PCM_RX, + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new auxpcm_rx_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia17", MSM_BACKEND_DAI_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia17", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia18", MSM_BACKEND_DAI_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia19", MSM_BACKEND_DAI_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia28", MSM_BACKEND_DAI_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia29", MSM_BACKEND_DAI_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new sec_auxpcm_rx_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_SEC_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_SEC_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_SEC_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_SEC_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_SEC_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_SEC_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_SEC_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_SEC_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_SEC_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_SEC_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_SEC_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_SEC_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_SEC_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_SEC_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_SEC_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_SEC_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia17", MSM_BACKEND_DAI_SEC_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia17", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia18", MSM_BACKEND_DAI_SEC_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia18", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia19", MSM_BACKEND_DAI_SEC_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia19", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia28", MSM_BACKEND_DAI_SEC_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia28", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia29", MSM_BACKEND_DAI_SEC_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia29", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new tert_auxpcm_rx_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_TERT_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_TERT_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_TERT_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_TERT_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_TERT_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_TERT_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_TERT_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_TERT_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_TERT_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_TERT_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_TERT_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_TERT_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_TERT_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_TERT_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_TERT_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_TERT_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new quat_auxpcm_rx_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new quin_auxpcm_rx_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new pri_tdm_rx_0_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new pri_tdm_rx_1_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new pri_tdm_rx_2_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new pri_tdm_rx_3_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new pri_tdm_tx_0_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_PRI_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_PRI_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_PRI_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_PRI_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_PRI_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_PRI_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_PRI_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_PRI_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_PRI_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_PRI_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_PRI_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_PRI_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_PRI_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_PRI_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_PRI_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_PRI_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new sec_tdm_rx_0_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new sec_tdm_rx_1_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new sec_tdm_rx_2_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new sec_tdm_rx_3_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new sec_tdm_tx_0_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_SEC_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_SEC_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_SEC_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_SEC_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_SEC_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_SEC_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_SEC_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_SEC_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_SEC_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_SEC_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_SEC_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_SEC_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_SEC_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_SEC_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_SEC_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_SEC_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new tert_tdm_rx_0_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new tert_tdm_tx_0_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_TERT_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_TERT_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_TERT_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_TERT_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_TERT_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_TERT_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_TERT_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_TERT_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_TERT_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_TERT_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_TERT_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_TERT_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_TERT_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_TERT_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_TERT_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_TERT_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new tert_tdm_rx_1_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new tert_tdm_rx_2_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new tert_tdm_rx_3_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new tert_tdm_rx_4_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_TERT_TDM_RX_4, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_TERT_TDM_RX_4, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_TERT_TDM_RX_4, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_TERT_TDM_RX_4, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_TERT_TDM_RX_4, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_TERT_TDM_RX_4, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_TERT_TDM_RX_4, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_TERT_TDM_RX_4, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_TERT_TDM_RX_4, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_TERT_TDM_RX_4, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_TERT_TDM_RX_4, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_TERT_TDM_RX_4, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_TERT_TDM_RX_4, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_TERT_TDM_RX_4, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_TERT_TDM_RX_4, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_TERT_TDM_RX_4, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_4, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new quat_tdm_rx_0_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia20", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia21", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia22", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia22", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new quat_tdm_tx_0_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_QUAT_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_QUAT_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_QUAT_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_QUAT_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_QUAT_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_QUAT_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_QUAT_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_QUAT_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_QUAT_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_QUAT_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_QUAT_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_QUAT_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_QUAT_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_QUAT_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_QUAT_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_QUAT_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new quat_tdm_rx_1_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia20", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia21", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia22", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia22", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new quat_tdm_rx_2_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia20", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia21", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia22", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia22", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new quat_tdm_rx_3_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia20", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia21", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia21", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA21, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia22", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia22", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA22, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new quin_tdm_rx_0_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia20", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new quin_tdm_tx_0_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_QUIN_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_QUIN_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_QUIN_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_QUIN_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_QUIN_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_QUIN_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_QUIN_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_QUIN_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_QUIN_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_QUIN_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_QUIN_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_QUIN_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_QUIN_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_QUIN_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_QUIN_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_QUIN_TDM_TX_0, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new quin_tdm_rx_1_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia20", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new quin_tdm_rx_2_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia20", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new quin_tdm_rx_3_mixer_controls[] = { - SOC_SINGLE_EXT("MultiMedia1", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia2", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia3", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia4", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia4", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia5", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia5", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia6", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia6", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia7", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia7", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA7, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia8", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia8", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia9", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia9", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia10", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia10", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia11", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia11", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA11, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia12", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia12", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA12, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia13", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia13", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA13, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia14", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia14", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA14, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia15", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia15", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA15, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia16", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia16", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MultiMedia20", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("MultiMedia20", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new mmul1_mixer_controls[] = { - SOC_SINGLE_EXT("PRI_TX", MSM_BACKEND_DAI_PRI_I2S_TX, + SOC_DOUBLE_EXT("PRI_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MI2S_TX", MSM_BACKEND_DAI_MI2S_TX, + SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_PRI_MI2S_TX, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INT2_MI2S_TX", MSM_BACKEND_DAI_INT2_MI2S_TX, + SOC_DOUBLE_EXT("INT2_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT2_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INT3_MI2S_TX", MSM_BACKEND_DAI_INT3_MI2S_TX, + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_SECONDARY_MI2S_TX, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SLIM_0_TX", MSM_BACKEND_DAI_SLIMBUS_0_TX, + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_AUXPCM_TX, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_UL_TX", MSM_BACKEND_DAI_SEC_AUXPCM_TX, + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_AUXPCM_UL_TX", MSM_BACKEND_DAI_TERT_AUXPCM_TX, + SOC_DOUBLE_EXT("TERT_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_AUXPCM_UL_TX", MSM_BACKEND_DAI_QUAT_AUXPCM_TX, + SOC_DOUBLE_EXT("QUAT_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_AUXPCM_UL_TX", MSM_BACKEND_DAI_QUIN_AUXPCM_TX, + SOC_DOUBLE_EXT("QUIN_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_INT_BT_SCO_TX, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_INT_FM_TX, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_TX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_AFE_PCM_TX, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("VOC_REC_DL", MSM_BACKEND_DAI_INCALL_RECORD_RX, + SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_RX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("VOC_REC_UL", MSM_BACKEND_DAI_INCALL_RECORD_TX, + SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_TX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SLIM_4_TX", MSM_BACKEND_DAI_SLIMBUS_4_TX, + SOC_DOUBLE_EXT("SLIM_4_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_4_TX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SLIM_6_TX", MSM_BACKEND_DAI_SLIMBUS_6_TX, + SOC_DOUBLE_EXT("SLIM_6_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_TX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_MI2S_TX", MSM_BACKEND_DAI_QUINARY_MI2S_TX, + SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_0", MSM_BACKEND_DAI_PRI_TDM_TX_0, + SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_1", MSM_BACKEND_DAI_PRI_TDM_TX_1, + SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_2", MSM_BACKEND_DAI_PRI_TDM_TX_2, + SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_3", MSM_BACKEND_DAI_PRI_TDM_TX_3, + SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_0", MSM_BACKEND_DAI_SEC_TDM_TX_0, + SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_1", MSM_BACKEND_DAI_SEC_TDM_TX_1, + SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_2", MSM_BACKEND_DAI_SEC_TDM_TX_2, + SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_3", MSM_BACKEND_DAI_SEC_TDM_TX_3, + SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_0", MSM_BACKEND_DAI_TERT_TDM_TX_0, + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_1", MSM_BACKEND_DAI_TERT_TDM_TX_1, + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_2", MSM_BACKEND_DAI_TERT_TDM_TX_2, + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_3", MSM_BACKEND_DAI_TERT_TDM_TX_3, + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_0", MSM_BACKEND_DAI_QUAT_TDM_TX_0, + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_1", MSM_BACKEND_DAI_QUAT_TDM_TX_1, + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_2", MSM_BACKEND_DAI_QUAT_TDM_TX_2, + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_3", MSM_BACKEND_DAI_QUAT_TDM_TX_3, + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_0", MSM_BACKEND_DAI_QUIN_TDM_TX_0, + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_1", MSM_BACKEND_DAI_QUIN_TDM_TX_1, + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_2", MSM_BACKEND_DAI_QUIN_TDM_TX_2, + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_3", MSM_BACKEND_DAI_QUIN_TDM_TX_3, + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SLIM_7_TX", MSM_BACKEND_DAI_SLIMBUS_7_TX, + SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_TX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SLIM_8_TX", MSM_BACKEND_DAI_SLIMBUS_8_TX, + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_8_TX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("USB_AUDIO_TX", MSM_BACKEND_DAI_USB_TX, + SOC_DOUBLE_EXT("USB_AUDIO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_TX, MSM_FRONTEND_DAI_MULTIMEDIA1, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new mmul2_mixer_controls[] = { - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_INT_FM_TX, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_TX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MI2S_TX", MSM_BACKEND_DAI_MI2S_TX, + SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_PRI_MI2S_TX, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_SECONDARY_MI2S_TX, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INT2_MI2S_TX", MSM_BACKEND_DAI_INT2_MI2S_TX, + SOC_DOUBLE_EXT("INT2_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT2_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INT3_MI2S_TX", MSM_BACKEND_DAI_INT3_MI2S_TX, + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SLIM_0_TX", MSM_BACKEND_DAI_SLIMBUS_0_TX, + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SLIM_6_TX", MSM_BACKEND_DAI_SLIMBUS_6_TX, + SOC_DOUBLE_EXT("SLIM_6_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_TX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SLIM_1_TX", MSM_BACKEND_DAI_SLIMBUS_1_TX, + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_MI2S_TX", MSM_BACKEND_DAI_QUINARY_MI2S_TX, + SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_0", MSM_BACKEND_DAI_PRI_TDM_TX_0, + SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_1", MSM_BACKEND_DAI_PRI_TDM_TX_1, + SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_2", MSM_BACKEND_DAI_PRI_TDM_TX_2, + SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_3", MSM_BACKEND_DAI_PRI_TDM_TX_3, + SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_0", MSM_BACKEND_DAI_SEC_TDM_TX_0, + SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_1", MSM_BACKEND_DAI_SEC_TDM_TX_1, + SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_2", MSM_BACKEND_DAI_SEC_TDM_TX_2, + SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_3", MSM_BACKEND_DAI_SEC_TDM_TX_3, + SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_0", MSM_BACKEND_DAI_TERT_TDM_TX_0, + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_1", MSM_BACKEND_DAI_TERT_TDM_TX_1, + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_2", MSM_BACKEND_DAI_TERT_TDM_TX_2, + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_3", MSM_BACKEND_DAI_TERT_TDM_TX_3, + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_0", MSM_BACKEND_DAI_QUAT_TDM_TX_0, + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_1", MSM_BACKEND_DAI_QUAT_TDM_TX_1, + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_2", MSM_BACKEND_DAI_QUAT_TDM_TX_2, + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_3", MSM_BACKEND_DAI_QUAT_TDM_TX_3, + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_0", MSM_BACKEND_DAI_QUIN_TDM_TX_0, + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_1", MSM_BACKEND_DAI_QUIN_TDM_TX_1, + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_2", MSM_BACKEND_DAI_QUIN_TDM_TX_2, + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_3", MSM_BACKEND_DAI_QUIN_TDM_TX_3, + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SLIM_8_TX", MSM_BACKEND_DAI_SLIMBUS_8_TX, + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_8_TX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("USB_AUDIO_TX", MSM_BACKEND_DAI_USB_TX, + SOC_DOUBLE_EXT("USB_AUDIO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_TX, MSM_FRONTEND_DAI_MULTIMEDIA2, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new mmul3_mixer_controls[] = { - SOC_SINGLE_EXT("SLIM_0_TX", MSM_BACKEND_DAI_SLIMBUS_0_TX, + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_INT_FM_TX, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_TX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MI2S_TX", MSM_BACKEND_DAI_MI2S_TX, + SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_AFE_PCM_TX, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_INT_BT_SCO_TX, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("AUX_PCM_TX", MSM_BACKEND_DAI_AUXPCM_TX, + SOC_DOUBLE_EXT("AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_TX", MSM_BACKEND_DAI_SEC_AUXPCM_TX, + SOC_DOUBLE_EXT("SEC_AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_AUX_PCM_TX", MSM_BACKEND_DAI_TERT_AUXPCM_TX, + SOC_DOUBLE_EXT("TERT_AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_AUX_PCM_TX", MSM_BACKEND_DAI_QUAT_AUXPCM_TX, + SOC_DOUBLE_EXT("QUAT_AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_AUX_PCM_TX", MSM_BACKEND_DAI_QUIN_AUXPCM_TX, + SOC_DOUBLE_EXT("QUIN_AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_PRI_MI2S_TX, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INT2_MI2S_TX", MSM_BACKEND_DAI_INT2_MI2S_TX, + SOC_DOUBLE_EXT("INT2_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT2_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INT3_MI2S_TX", MSM_BACKEND_DAI_INT3_MI2S_TX, + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_0", MSM_BACKEND_DAI_PRI_TDM_TX_0, + SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_1", MSM_BACKEND_DAI_PRI_TDM_TX_1, + SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_2", MSM_BACKEND_DAI_PRI_TDM_TX_2, + SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_3", MSM_BACKEND_DAI_PRI_TDM_TX_3, + SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_0", MSM_BACKEND_DAI_SEC_TDM_TX_0, + SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_1", MSM_BACKEND_DAI_SEC_TDM_TX_1, + SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_2", MSM_BACKEND_DAI_SEC_TDM_TX_2, + SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_3", MSM_BACKEND_DAI_SEC_TDM_TX_3, + SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_0", MSM_BACKEND_DAI_TERT_TDM_TX_0, + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_1", MSM_BACKEND_DAI_TERT_TDM_TX_1, + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_2", MSM_BACKEND_DAI_TERT_TDM_TX_2, + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_3", MSM_BACKEND_DAI_TERT_TDM_TX_3, + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_0", MSM_BACKEND_DAI_QUAT_TDM_TX_0, + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_1", MSM_BACKEND_DAI_QUAT_TDM_TX_1, + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_2", MSM_BACKEND_DAI_QUAT_TDM_TX_2, + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_3", MSM_BACKEND_DAI_QUAT_TDM_TX_3, + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_0", MSM_BACKEND_DAI_QUIN_TDM_TX_0, + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_1", MSM_BACKEND_DAI_QUIN_TDM_TX_1, + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_2", MSM_BACKEND_DAI_QUIN_TDM_TX_2, + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_3", MSM_BACKEND_DAI_QUIN_TDM_TX_3, + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA3, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new mmul4_mixer_controls[] = { - SOC_SINGLE_EXT("SLIM_0_TX", MSM_BACKEND_DAI_SLIMBUS_0_TX, + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_PRI_MI2S_TX, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_INT_FM_TX, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_TX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_INT_BT_SCO_TX, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_AFE_PCM_TX, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("VOC_REC_DL", MSM_BACKEND_DAI_INCALL_RECORD_RX, + SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_RX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("VOC_REC_UL", MSM_BACKEND_DAI_INCALL_RECORD_TX, + SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_TX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_0", MSM_BACKEND_DAI_TERT_TDM_TX_0, + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_0", MSM_BACKEND_DAI_PRI_TDM_TX_0, + SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_1", MSM_BACKEND_DAI_PRI_TDM_TX_1, + SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_2", MSM_BACKEND_DAI_PRI_TDM_TX_2, + SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_3", MSM_BACKEND_DAI_PRI_TDM_TX_3, + SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_0", MSM_BACKEND_DAI_SEC_TDM_TX_0, + SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_1", MSM_BACKEND_DAI_SEC_TDM_TX_1, + SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_2", MSM_BACKEND_DAI_SEC_TDM_TX_2, + SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_3", MSM_BACKEND_DAI_SEC_TDM_TX_3, + SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_1", MSM_BACKEND_DAI_TERT_TDM_TX_1, + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_2", MSM_BACKEND_DAI_TERT_TDM_TX_2, + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_3", MSM_BACKEND_DAI_TERT_TDM_TX_3, + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_0", MSM_BACKEND_DAI_QUAT_TDM_TX_0, + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_1", MSM_BACKEND_DAI_QUAT_TDM_TX_1, + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_2", MSM_BACKEND_DAI_QUAT_TDM_TX_2, + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_3", MSM_BACKEND_DAI_QUAT_TDM_TX_3, + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_0", MSM_BACKEND_DAI_QUIN_TDM_TX_0, + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_1", MSM_BACKEND_DAI_QUIN_TDM_TX_1, + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_2", MSM_BACKEND_DAI_QUIN_TDM_TX_2, + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_3", MSM_BACKEND_DAI_QUIN_TDM_TX_3, + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_SECONDARY_MI2S_TX, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INT2_MI2S_TX", MSM_BACKEND_DAI_INT2_MI2S_TX, + SOC_DOUBLE_EXT("INT2_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT2_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INT3_MI2S_TX", MSM_BACKEND_DAI_INT3_MI2S_TX, + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("USB_AUDIO_TX", MSM_BACKEND_DAI_USB_TX, + SOC_DOUBLE_EXT("USB_AUDIO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_TX, MSM_FRONTEND_DAI_MULTIMEDIA4, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new mmul5_mixer_controls[] = { - SOC_SINGLE_EXT("SLIM_0_TX", MSM_BACKEND_DAI_SLIMBUS_0_TX, + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_INT_FM_TX, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_TX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MI2S_TX", MSM_BACKEND_DAI_MI2S_TX, + SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_AFE_PCM_TX, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_INT_BT_SCO_TX, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_AUXPCM_TX, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_TX", MSM_BACKEND_DAI_SEC_AUXPCM_TX, + SOC_DOUBLE_EXT("SEC_AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_AUX_PCM_TX", MSM_BACKEND_DAI_TERT_AUXPCM_TX, + SOC_DOUBLE_EXT("TERT_AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_AUX_PCM_TX", MSM_BACKEND_DAI_QUAT_AUXPCM_TX, + SOC_DOUBLE_EXT("QUAT_AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_AUX_PCM_TX", MSM_BACKEND_DAI_QUIN_AUXPCM_TX, + SOC_DOUBLE_EXT("QUIN_AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_PRI_MI2S_TX, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INT2_MI2S_TX", MSM_BACKEND_DAI_INT2_MI2S_TX, + SOC_DOUBLE_EXT("INT2_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT2_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INT3_MI2S_TX", MSM_BACKEND_DAI_INT3_MI2S_TX, + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_0", MSM_BACKEND_DAI_PRI_TDM_TX_0, + SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_1", MSM_BACKEND_DAI_PRI_TDM_TX_1, + SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_2", MSM_BACKEND_DAI_PRI_TDM_TX_2, + SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_3", MSM_BACKEND_DAI_PRI_TDM_TX_3, + SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_0", MSM_BACKEND_DAI_SEC_TDM_TX_0, + SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_1", MSM_BACKEND_DAI_SEC_TDM_TX_1, + SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_2", MSM_BACKEND_DAI_SEC_TDM_TX_2, + SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_3", MSM_BACKEND_DAI_SEC_TDM_TX_3, + SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_0", MSM_BACKEND_DAI_TERT_TDM_TX_0, + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_1", MSM_BACKEND_DAI_TERT_TDM_TX_1, + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_2", MSM_BACKEND_DAI_TERT_TDM_TX_2, + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_3", MSM_BACKEND_DAI_TERT_TDM_TX_3, + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_0", MSM_BACKEND_DAI_QUAT_TDM_TX_0, + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_1", MSM_BACKEND_DAI_QUAT_TDM_TX_1, + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_2", MSM_BACKEND_DAI_QUAT_TDM_TX_2, + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_3", MSM_BACKEND_DAI_QUAT_TDM_TX_3, + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_0", MSM_BACKEND_DAI_QUIN_TDM_TX_0, + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_1", MSM_BACKEND_DAI_QUIN_TDM_TX_1, + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_2", MSM_BACKEND_DAI_QUIN_TDM_TX_2, + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_3", MSM_BACKEND_DAI_QUIN_TDM_TX_3, + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_SECONDARY_MI2S_TX, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SLIM_7_TX", MSM_BACKEND_DAI_SLIMBUS_7_TX, + SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_TX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SLIM_8_TX", MSM_BACKEND_DAI_SLIMBUS_8_TX, + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_8_TX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("USB_AUDIO_TX", MSM_BACKEND_DAI_USB_TX, + SOC_DOUBLE_EXT("USB_AUDIO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_TX, MSM_FRONTEND_DAI_MULTIMEDIA5, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new mmul6_mixer_controls[] = { - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_INT_FM_TX, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_TX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SLIM_0_TX", MSM_BACKEND_DAI_SLIMBUS_0_TX, + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_PRI_MI2S_TX, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_SECONDARY_MI2S_TX, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INT2_MI2S_TX", MSM_BACKEND_DAI_INT2_MI2S_TX, + SOC_DOUBLE_EXT("INT2_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT2_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INT3_MI2S_TX", MSM_BACKEND_DAI_INT3_MI2S_TX, + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_MI2S_TX", MSM_BACKEND_DAI_QUINARY_MI2S_TX, + SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_AUXPCM_TX, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_UL_TX", MSM_BACKEND_DAI_SEC_AUXPCM_TX, + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_AUXPCM_UL_TX", MSM_BACKEND_DAI_TERT_AUXPCM_TX, + SOC_DOUBLE_EXT("TERT_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_AUXPCM_UL_TX", MSM_BACKEND_DAI_QUAT_AUXPCM_TX, + SOC_DOUBLE_EXT("QUAT_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_0", MSM_BACKEND_DAI_PRI_TDM_TX_0, + SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_1", MSM_BACKEND_DAI_PRI_TDM_TX_1, + SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_2", MSM_BACKEND_DAI_PRI_TDM_TX_2, + SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_3", MSM_BACKEND_DAI_PRI_TDM_TX_3, + SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_0", MSM_BACKEND_DAI_SEC_TDM_TX_0, + SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_1", MSM_BACKEND_DAI_SEC_TDM_TX_1, + SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_2", MSM_BACKEND_DAI_SEC_TDM_TX_2, + SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_3", MSM_BACKEND_DAI_SEC_TDM_TX_3, + SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_0", MSM_BACKEND_DAI_TERT_TDM_TX_0, + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_1", MSM_BACKEND_DAI_TERT_TDM_TX_1, + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_2", MSM_BACKEND_DAI_TERT_TDM_TX_2, + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_3", MSM_BACKEND_DAI_TERT_TDM_TX_3, + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_0", MSM_BACKEND_DAI_QUAT_TDM_TX_0, + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_1", MSM_BACKEND_DAI_QUAT_TDM_TX_1, + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_2", MSM_BACKEND_DAI_QUAT_TDM_TX_2, + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_3", MSM_BACKEND_DAI_QUAT_TDM_TX_3, + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_0", MSM_BACKEND_DAI_QUIN_TDM_TX_0, + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_1", MSM_BACKEND_DAI_QUIN_TDM_TX_1, + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_2", MSM_BACKEND_DAI_QUIN_TDM_TX_2, + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_3", MSM_BACKEND_DAI_QUIN_TDM_TX_3, + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("USB_AUDIO_TX", MSM_BACKEND_DAI_USB_TX, + SOC_DOUBLE_EXT("USB_AUDIO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_TX, MSM_FRONTEND_DAI_MULTIMEDIA6, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new mmul8_mixer_controls[] = { - SOC_SINGLE_EXT("SLIM_0_TX", MSM_BACKEND_DAI_SLIMBUS_0_TX, + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_PRI_MI2S_TX, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_SECONDARY_MI2S_TX, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INT2_MI2S_TX", MSM_BACKEND_DAI_INT2_MI2S_TX, + SOC_DOUBLE_EXT("INT2_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT2_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INT3_MI2S_TX", MSM_BACKEND_DAI_INT3_MI2S_TX, + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_INT_FM_TX, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_TX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_INT_BT_SCO_TX, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_AFE_PCM_TX, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("VOC_REC_DL", MSM_BACKEND_DAI_INCALL_RECORD_RX, + SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_RX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("VOC_REC_UL", MSM_BACKEND_DAI_INCALL_RECORD_TX, + SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_TX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SLIM_6_TX", MSM_BACKEND_DAI_SLIMBUS_6_TX, + SOC_DOUBLE_EXT("SLIM_6_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_TX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_0", MSM_BACKEND_DAI_PRI_TDM_TX_0, + SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_1", MSM_BACKEND_DAI_PRI_TDM_TX_1, + SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_2", MSM_BACKEND_DAI_PRI_TDM_TX_2, + SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_3", MSM_BACKEND_DAI_PRI_TDM_TX_3, + SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_0", MSM_BACKEND_DAI_SEC_TDM_TX_0, + SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_1", MSM_BACKEND_DAI_SEC_TDM_TX_1, + SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_2", MSM_BACKEND_DAI_SEC_TDM_TX_2, + SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_3", MSM_BACKEND_DAI_SEC_TDM_TX_3, + SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_0", MSM_BACKEND_DAI_TERT_TDM_TX_0, + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_1", MSM_BACKEND_DAI_TERT_TDM_TX_1, + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_2", MSM_BACKEND_DAI_TERT_TDM_TX_2, + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_3", MSM_BACKEND_DAI_TERT_TDM_TX_3, + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_0", MSM_BACKEND_DAI_QUAT_TDM_TX_0, + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_1", MSM_BACKEND_DAI_QUAT_TDM_TX_1, + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_2", MSM_BACKEND_DAI_QUAT_TDM_TX_2, + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_3", MSM_BACKEND_DAI_QUAT_TDM_TX_3, + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_0", MSM_BACKEND_DAI_QUIN_TDM_TX_0, + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_1", MSM_BACKEND_DAI_QUIN_TDM_TX_1, + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_2", MSM_BACKEND_DAI_QUIN_TDM_TX_2, + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_3", MSM_BACKEND_DAI_QUIN_TDM_TX_3, + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SLIM_7_TX", MSM_BACKEND_DAI_SLIMBUS_7_TX, + SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_TX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("USB_AUDIO_TX", MSM_BACKEND_DAI_USB_TX, + SOC_DOUBLE_EXT("USB_AUDIO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_TX, MSM_FRONTEND_DAI_MULTIMEDIA8, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new mmul16_mixer_controls[] = { - SOC_SINGLE_EXT("SLIM_0_TX", MSM_BACKEND_DAI_SLIMBUS_0_TX, + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_PRI_MI2S_TX, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_SECONDARY_MI2S_TX, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INT2_MI2S_TX", MSM_BACKEND_DAI_INT2_MI2S_TX, + SOC_DOUBLE_EXT("INT2_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT2_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INT3_MI2S_TX", MSM_BACKEND_DAI_INT3_MI2S_TX, + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_INT_FM_TX, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_TX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_INT_BT_SCO_TX, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_AFE_PCM_TX, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("VOC_REC_DL", MSM_BACKEND_DAI_INCALL_RECORD_RX, + SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_RX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("VOC_REC_UL", MSM_BACKEND_DAI_INCALL_RECORD_TX, + SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_TX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SLIM_6_TX", MSM_BACKEND_DAI_SLIMBUS_6_TX, + SOC_DOUBLE_EXT("SLIM_6_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_TX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_0", MSM_BACKEND_DAI_PRI_TDM_TX_0, + SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_1", MSM_BACKEND_DAI_PRI_TDM_TX_1, + SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_2", MSM_BACKEND_DAI_PRI_TDM_TX_2, + SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_3", MSM_BACKEND_DAI_PRI_TDM_TX_3, + SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_0", MSM_BACKEND_DAI_SEC_TDM_TX_0, + SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_1", MSM_BACKEND_DAI_SEC_TDM_TX_1, + SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_2", MSM_BACKEND_DAI_SEC_TDM_TX_2, + SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_3", MSM_BACKEND_DAI_SEC_TDM_TX_3, + SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_0", MSM_BACKEND_DAI_TERT_TDM_TX_0, + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_1", MSM_BACKEND_DAI_TERT_TDM_TX_1, + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_2", MSM_BACKEND_DAI_TERT_TDM_TX_2, + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_3", MSM_BACKEND_DAI_TERT_TDM_TX_3, + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_0", MSM_BACKEND_DAI_QUAT_TDM_TX_0, + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_1", MSM_BACKEND_DAI_QUAT_TDM_TX_1, + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_2", MSM_BACKEND_DAI_QUAT_TDM_TX_2, + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_3", MSM_BACKEND_DAI_QUAT_TDM_TX_3, + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SLIM_7_TX", MSM_BACKEND_DAI_SLIMBUS_7_TX, + SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_TX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("USB_AUDIO_TX", MSM_BACKEND_DAI_USB_TX, + SOC_DOUBLE_EXT("USB_AUDIO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_TX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MI2S_TX", MSM_BACKEND_DAI_MI2S_TX, + SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("AUX_PCM_TX", MSM_BACKEND_DAI_AUXPCM_TX, + SOC_DOUBLE_EXT("AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_TX", MSM_BACKEND_DAI_SEC_AUXPCM_TX, + SOC_DOUBLE_EXT("SEC_AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_AUX_PCM_TX", MSM_BACKEND_DAI_QUAT_AUXPCM_TX, + SOC_DOUBLE_EXT("QUAT_AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA16, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new mmul9_mixer_controls[] = { - SOC_SINGLE_EXT("SLIM_0_TX", MSM_BACKEND_DAI_SLIMBUS_0_TX, + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_PRI_MI2S_TX, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_INT_FM_TX, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_TX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_INT_BT_SCO_TX, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_AFE_PCM_TX, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("VOC_REC_DL", MSM_BACKEND_DAI_INCALL_RECORD_RX, + SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_RX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("VOC_REC_UL", MSM_BACKEND_DAI_INCALL_RECORD_TX, + SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_TX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SLIM_6_TX", MSM_BACKEND_DAI_SLIMBUS_6_TX, + SOC_DOUBLE_EXT("SLIM_6_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_TX, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_0", MSM_BACKEND_DAI_TERT_TDM_TX_0, + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_1", MSM_BACKEND_DAI_TERT_TDM_TX_1, + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_2", MSM_BACKEND_DAI_TERT_TDM_TX_2, + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_3", MSM_BACKEND_DAI_TERT_TDM_TX_3, + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_0", MSM_BACKEND_DAI_QUAT_TDM_TX_0, + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_1", MSM_BACKEND_DAI_QUAT_TDM_TX_1, + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_2", MSM_BACKEND_DAI_QUAT_TDM_TX_2, + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_3", MSM_BACKEND_DAI_QUAT_TDM_TX_3, + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_0", MSM_BACKEND_DAI_QUIN_TDM_TX_0, + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_1", MSM_BACKEND_DAI_QUIN_TDM_TX_1, + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_2", MSM_BACKEND_DAI_QUIN_TDM_TX_2, + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_3", MSM_BACKEND_DAI_QUIN_TDM_TX_3, + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA9, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new mmul10_mixer_controls[] = { - SOC_SINGLE_EXT("SLIM_0_TX", MSM_BACKEND_DAI_SLIMBUS_0_TX, + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_PRI_MI2S_TX, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_INT_FM_TX, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_TX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_INT_BT_SCO_TX, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_AFE_PCM_TX, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("VOC_REC_DL", MSM_BACKEND_DAI_INCALL_RECORD_RX, + SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_RX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("VOC_REC_UL", MSM_BACKEND_DAI_INCALL_RECORD_TX, + SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_TX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SLIM_6_TX", MSM_BACKEND_DAI_SLIMBUS_6_TX, + SOC_DOUBLE_EXT("SLIM_6_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_TX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SLIM_7_TX", MSM_BACKEND_DAI_SLIMBUS_7_TX, + SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_TX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_0", MSM_BACKEND_DAI_TERT_TDM_TX_0, + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_1", MSM_BACKEND_DAI_TERT_TDM_TX_1, + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_2", MSM_BACKEND_DAI_TERT_TDM_TX_2, + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_3", MSM_BACKEND_DAI_TERT_TDM_TX_3, + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_0", MSM_BACKEND_DAI_QUAT_TDM_TX_0, + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_1", MSM_BACKEND_DAI_QUAT_TDM_TX_1, + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_2", MSM_BACKEND_DAI_QUAT_TDM_TX_2, + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_3", MSM_BACKEND_DAI_QUAT_TDM_TX_3, + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("USB_AUDIO_TX", MSM_BACKEND_DAI_USB_TX, + SOC_DOUBLE_EXT("USB_AUDIO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_TX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("MI2S_TX", MSM_BACKEND_DAI_MI2S_TX, + SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("AUX_PCM_TX", MSM_BACKEND_DAI_AUXPCM_TX, + SOC_DOUBLE_EXT("AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_TX", MSM_BACKEND_DAI_SEC_AUXPCM_TX, + SOC_DOUBLE_EXT("SEC_AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_AUX_PCM_TX", MSM_BACKEND_DAI_TERT_AUXPCM_TX, + SOC_DOUBLE_EXT("TERT_AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_AUX_PCM_TX", MSM_BACKEND_DAI_QUAT_AUXPCM_TX, + SOC_DOUBLE_EXT("QUAT_AUX_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INT2_MI2S_TX", MSM_BACKEND_DAI_INT2_MI2S_TX, + SOC_DOUBLE_EXT("INT2_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT2_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INT3_MI2S_TX", MSM_BACKEND_DAI_INT3_MI2S_TX, + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA10, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new mmul17_mixer_controls[] = { - SOC_SINGLE_EXT("SLIM_0_TX", MSM_BACKEND_DAI_SLIMBUS_0_TX, + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_PRI_MI2S_TX, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INT3_MI2S_TX", MSM_BACKEND_DAI_INT3_MI2S_TX, + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_INT_FM_TX, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_TX, MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_INT_BT_SCO_TX, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_AFE_PCM_TX, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("VOC_REC_DL", MSM_BACKEND_DAI_INCALL_RECORD_RX, + SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_RX, MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("VOC_REC_UL", MSM_BACKEND_DAI_INCALL_RECORD_TX, + SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_TX, MSM_FRONTEND_DAI_MULTIMEDIA17, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new mmul18_mixer_controls[] = { - SOC_SINGLE_EXT("SLIM_0_TX", MSM_BACKEND_DAI_SLIMBUS_0_TX, + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_PRI_MI2S_TX, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INT3_MI2S_TX", MSM_BACKEND_DAI_INT3_MI2S_TX, + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_INT_FM_TX, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_TX, MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_INT_BT_SCO_TX, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_AFE_PCM_TX, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("VOC_REC_DL", MSM_BACKEND_DAI_INCALL_RECORD_RX, + SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_RX, MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("VOC_REC_UL", MSM_BACKEND_DAI_INCALL_RECORD_TX, + SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_TX, MSM_FRONTEND_DAI_MULTIMEDIA18, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new mmul19_mixer_controls[] = { - SOC_SINGLE_EXT("SLIM_0_TX", MSM_BACKEND_DAI_SLIMBUS_0_TX, + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_PRI_MI2S_TX, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INT3_MI2S_TX", MSM_BACKEND_DAI_INT3_MI2S_TX, + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_INT_FM_TX, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_TX, MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_INT_BT_SCO_TX, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_AFE_PCM_TX, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("VOC_REC_DL", MSM_BACKEND_DAI_INCALL_RECORD_RX, + SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_RX, MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("VOC_REC_UL", MSM_BACKEND_DAI_INCALL_RECORD_TX, + SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_TX, MSM_FRONTEND_DAI_MULTIMEDIA19, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new mmul20_mixer_controls[] = { - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_PRI_MI2S_TX, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_SECONDARY_MI2S_TX, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_MI2S_TX", MSM_BACKEND_DAI_QUINARY_MI2S_TX, + SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_0", MSM_BACKEND_DAI_PRI_TDM_TX_0, + SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_1", MSM_BACKEND_DAI_PRI_TDM_TX_1, + SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_2", MSM_BACKEND_DAI_PRI_TDM_TX_2, + SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_3", MSM_BACKEND_DAI_PRI_TDM_TX_3, + SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_0", MSM_BACKEND_DAI_SEC_TDM_TX_0, + SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_1", MSM_BACKEND_DAI_SEC_TDM_TX_1, + SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_2", MSM_BACKEND_DAI_SEC_TDM_TX_2, + SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_3", MSM_BACKEND_DAI_SEC_TDM_TX_3, + SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_0", MSM_BACKEND_DAI_TERT_TDM_TX_0, + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_1", MSM_BACKEND_DAI_TERT_TDM_TX_1, + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_2", MSM_BACKEND_DAI_TERT_TDM_TX_2, + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_3", MSM_BACKEND_DAI_TERT_TDM_TX_3, + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_0", MSM_BACKEND_DAI_QUAT_TDM_TX_0, + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_1", MSM_BACKEND_DAI_QUAT_TDM_TX_1, + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_2", MSM_BACKEND_DAI_QUAT_TDM_TX_2, + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_3", MSM_BACKEND_DAI_QUAT_TDM_TX_3, + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_0", MSM_BACKEND_DAI_QUIN_TDM_TX_0, + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_0, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_1", MSM_BACKEND_DAI_QUIN_TDM_TX_1, + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_1, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_2", MSM_BACKEND_DAI_QUIN_TDM_TX_2, + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_2, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_3", MSM_BACKEND_DAI_QUIN_TDM_TX_3, + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_TX_3, MSM_FRONTEND_DAI_MULTIMEDIA20, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new mmul28_mixer_controls[] = { - SOC_SINGLE_EXT("SLIM_0_TX", MSM_BACKEND_DAI_SLIMBUS_0_TX, + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_PRI_MI2S_TX, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INT3_MI2S_TX", MSM_BACKEND_DAI_INT3_MI2S_TX, + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_INT_FM_TX, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_TX, MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_INT_BT_SCO_TX, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_AFE_PCM_TX, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("VOC_REC_DL", MSM_BACKEND_DAI_INCALL_RECORD_RX, + SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_RX, MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("VOC_REC_UL", MSM_BACKEND_DAI_INCALL_RECORD_TX, + SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_TX, MSM_FRONTEND_DAI_MULTIMEDIA28, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new mmul29_mixer_controls[] = { - SOC_SINGLE_EXT("SLIM_0_TX", MSM_BACKEND_DAI_SLIMBUS_0_TX, + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_PRI_MI2S_TX, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INT3_MI2S_TX", MSM_BACKEND_DAI_INT3_MI2S_TX, + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_INT_FM_TX, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_FM_TX, MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_INT_BT_SCO_TX, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_AFE_PCM_TX, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("VOC_REC_DL", MSM_BACKEND_DAI_INCALL_RECORD_RX, + SOC_DOUBLE_EXT("VOC_REC_DL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_RX, MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), - SOC_SINGLE_EXT("VOC_REC_UL", MSM_BACKEND_DAI_INCALL_RECORD_TX, + SOC_DOUBLE_EXT("VOC_REC_UL", SND_SOC_NOPM, + MSM_BACKEND_DAI_INCALL_RECORD_TX, MSM_FRONTEND_DAI_MULTIMEDIA29, 1, 0, msm_routing_get_audio_mixer, msm_routing_put_audio_mixer), }; static const struct snd_kcontrol_new pri_rx_voice_mixer_controls[] = { - SOC_SINGLE_EXT("Voip", MSM_BACKEND_DAI_PRI_I2S_RX, + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode1", MSM_BACKEND_DAI_PRI_I2S_RX, + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode2", MSM_BACKEND_DAI_PRI_I2S_RX, + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("DTMF", MSM_BACKEND_DAI_PRI_I2S_RX, + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QCHAT", MSM_BACKEND_DAI_PRI_I2S_RX, + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_RX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), }; static const struct snd_kcontrol_new sec_i2s_rx_voice_mixer_controls[] = { - SOC_SINGLE_EXT("Voip", MSM_BACKEND_DAI_SEC_I2S_RX, + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("DTMF", MSM_BACKEND_DAI_SEC_I2S_RX, + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QCHAT", MSM_BACKEND_DAI_SEC_I2S_RX, + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), }; static const struct snd_kcontrol_new sec_mi2s_rx_voice_mixer_controls[] = { - SOC_SINGLE_EXT("Voip", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("Voice Stub", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("Voice Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("Voice2 Stub", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("Voice2 Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("DTMF", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QCHAT", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode1", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode2", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), }; static const struct snd_kcontrol_new slimbus_rx_voice_mixer_controls[] = { - SOC_SINGLE_EXT("Voip", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("DTMF", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QCHAT", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode1", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode2", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), }; static const struct snd_kcontrol_new slimbus_6_rx_voice_mixer_controls[] = { - SOC_SINGLE_EXT("Voip", MSM_BACKEND_DAI_SLIMBUS_6_RX, + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, +MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("DTMF", MSM_BACKEND_DAI_SLIMBUS_6_RX, + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, +MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QCHAT", MSM_BACKEND_DAI_SLIMBUS_6_RX, + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, +MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode1", MSM_BACKEND_DAI_SLIMBUS_6_RX, + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, +MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode2", MSM_BACKEND_DAI_SLIMBUS_6_RX, + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, +MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), }; static const struct snd_kcontrol_new usb_audio_rx_voice_mixer_controls[] = { - SOC_SINGLE_EXT("Voip", MSM_BACKEND_DAI_USB_RX, + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("DTMF", MSM_BACKEND_DAI_USB_RX, + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QCHAT", MSM_BACKEND_DAI_USB_RX, + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode1", MSM_BACKEND_DAI_USB_RX, + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode2", MSM_BACKEND_DAI_USB_RX, + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_RX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), }; static const struct snd_kcontrol_new display_port_rx_voice_mixer_controls[] = { - SOC_SINGLE_EXT("Voip", MSM_BACKEND_DAI_DISPLAY_PORT_RX, + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, +MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("DTMF", MSM_BACKEND_DAI_DISPLAY_PORT_RX, + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, +MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QCHAT", MSM_BACKEND_DAI_DISPLAY_PORT_RX, + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, +MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode1", MSM_BACKEND_DAI_DISPLAY_PORT_RX, + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, +MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode2", MSM_BACKEND_DAI_DISPLAY_PORT_RX, + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, +MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), }; static const struct snd_kcontrol_new bt_sco_rx_voice_mixer_controls[] = { - SOC_SINGLE_EXT("Voip", MSM_BACKEND_DAI_INT_BT_SCO_RX, + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("DTMF", MSM_BACKEND_DAI_INT_BT_SCO_RX, + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QCHAT", MSM_BACKEND_DAI_INT_BT_SCO_RX, + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode1", MSM_BACKEND_DAI_INT_BT_SCO_RX, + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode2", MSM_BACKEND_DAI_INT_BT_SCO_RX, + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), }; static const struct snd_kcontrol_new mi2s_rx_voice_mixer_controls[] = { - SOC_SINGLE_EXT("Voip", MSM_BACKEND_DAI_MI2S_RX, + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("Voice Stub", MSM_BACKEND_DAI_MI2S_RX, + SOC_DOUBLE_EXT("Voice Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("Voice2 Stub", MSM_BACKEND_DAI_MI2S_RX, + SOC_DOUBLE_EXT("Voice2 Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("DTMF", MSM_BACKEND_DAI_MI2S_RX, + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QCHAT", MSM_BACKEND_DAI_MI2S_RX, + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode1", MSM_BACKEND_DAI_MI2S_RX, + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode2", MSM_BACKEND_DAI_MI2S_RX, + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), }; static const struct snd_kcontrol_new pri_mi2s_rx_voice_mixer_controls[] = { - SOC_SINGLE_EXT("Voip", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, +MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("Voice Stub", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("Voice Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("Voice2 Stub", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("Voice2 Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("DTMF", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QCHAT", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, +MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode1", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, +MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode2", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, +MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), }; static const struct snd_kcontrol_new int0_mi2s_rx_voice_mixer_controls[] = { - SOC_SINGLE_EXT("Voip", MSM_BACKEND_DAI_INT0_MI2S_RX, + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, +MSM_BACKEND_DAI_INT0_MI2S_RX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("DTMF", MSM_BACKEND_DAI_INT0_MI2S_RX, + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, +MSM_BACKEND_DAI_INT0_MI2S_RX, MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QCHAT", MSM_BACKEND_DAI_INT0_MI2S_RX, + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, +MSM_BACKEND_DAI_INT0_MI2S_RX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode1", MSM_BACKEND_DAI_INT0_MI2S_RX, + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, +MSM_BACKEND_DAI_INT0_MI2S_RX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode2", MSM_BACKEND_DAI_INT0_MI2S_RX, + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, +MSM_BACKEND_DAI_INT0_MI2S_RX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), }; static const struct snd_kcontrol_new int4_mi2s_rx_voice_mixer_controls[] = { - SOC_SINGLE_EXT("Voip", MSM_BACKEND_DAI_INT4_MI2S_RX, + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("DTMF", MSM_BACKEND_DAI_INT4_MI2S_RX, + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QCHAT", MSM_BACKEND_DAI_INT4_MI2S_RX, + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode1", MSM_BACKEND_DAI_INT4_MI2S_RX, + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode2", MSM_BACKEND_DAI_INT4_MI2S_RX, + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), }; static const struct snd_kcontrol_new tert_mi2s_rx_voice_mixer_controls[] = { - SOC_SINGLE_EXT("Voip", MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("Voice Stub", MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + SOC_DOUBLE_EXT("Voice Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("Voice2 Stub", MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + SOC_DOUBLE_EXT("Voice2 Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("DTMF", MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QCHAT", MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode1", MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode2", MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), }; static const struct snd_kcontrol_new quat_mi2s_rx_voice_mixer_controls[] = { - SOC_SINGLE_EXT("Voip", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("Voice Stub", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("Voice Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("Voice2 Stub", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("Voice2 Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("DTMF", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QCHAT", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode1", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode2", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), }; static const struct snd_kcontrol_new quin_mi2s_rx_voice_mixer_controls[] = { - SOC_SINGLE_EXT("Voip", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("Voice Stub", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("Voice Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("Voice2 Stub", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("Voice2 Stub", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("DTMF", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QCHAT", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode1", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode2", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), }; static const struct snd_kcontrol_new afe_pcm_rx_voice_mixer_controls[] = { - SOC_SINGLE_EXT("Voip", MSM_BACKEND_DAI_AFE_PCM_RX, + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("DTMF", MSM_BACKEND_DAI_AFE_PCM_RX, + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QCHAT", MSM_BACKEND_DAI_AFE_PCM_RX, + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode1", MSM_BACKEND_DAI_AFE_PCM_RX, + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode2", MSM_BACKEND_DAI_AFE_PCM_RX, + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), }; static const struct snd_kcontrol_new aux_pcm_rx_voice_mixer_controls[] = { - SOC_SINGLE_EXT("Voip", MSM_BACKEND_DAI_AUXPCM_RX, + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("DTMF", MSM_BACKEND_DAI_AUXPCM_RX, + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QCHAT", MSM_BACKEND_DAI_AUXPCM_RX, + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode1", MSM_BACKEND_DAI_AUXPCM_RX, + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode2", MSM_BACKEND_DAI_AUXPCM_RX, + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), }; static const struct snd_kcontrol_new sec_aux_pcm_rx_voice_mixer_controls[] = { - SOC_SINGLE_EXT("Voip", MSM_BACKEND_DAI_SEC_AUXPCM_RX, + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, +MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("DTMF", MSM_BACKEND_DAI_SEC_AUXPCM_RX, + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, +MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QCHAT", MSM_BACKEND_DAI_SEC_AUXPCM_RX, + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, +MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode1", MSM_BACKEND_DAI_SEC_AUXPCM_RX, + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, +MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode2", MSM_BACKEND_DAI_SEC_AUXPCM_RX, + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, +MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), }; static const struct snd_kcontrol_new tert_aux_pcm_rx_voice_mixer_controls[] = { - SOC_SINGLE_EXT("Voip", MSM_BACKEND_DAI_TERT_AUXPCM_RX, + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, +MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("DTMF", MSM_BACKEND_DAI_TERT_AUXPCM_RX, + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, +MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QCHAT", MSM_BACKEND_DAI_TERT_AUXPCM_RX, + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, +MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode1", MSM_BACKEND_DAI_TERT_AUXPCM_RX, + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, +MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode2", MSM_BACKEND_DAI_TERT_AUXPCM_RX, + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, +MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), }; static const struct snd_kcontrol_new quat_aux_pcm_rx_voice_mixer_controls[] = { - SOC_SINGLE_EXT("Voip", MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, +MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("DTMF", MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, +MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QCHAT", MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, +MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode1", MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, +MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode2", MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, +MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), }; static const struct snd_kcontrol_new quin_aux_pcm_rx_voice_mixer_controls[] = { - SOC_SINGLE_EXT("Voip", MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, +MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("DTMF", MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, +MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QCHAT", MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, +MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode1", MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, +MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode2", MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, +MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), }; static const struct snd_kcontrol_new hdmi_rx_voice_mixer_controls[] = { - SOC_SINGLE_EXT("Voip", MSM_BACKEND_DAI_HDMI_RX, + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("DTMF", MSM_BACKEND_DAI_HDMI_RX, + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QCHAT", MSM_BACKEND_DAI_HDMI_RX, + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode1", MSM_BACKEND_DAI_HDMI_RX, + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode2", MSM_BACKEND_DAI_HDMI_RX, + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), }; static const struct snd_kcontrol_new slimbus_7_rx_voice_mixer_controls[] = { - SOC_SINGLE_EXT("Voip", MSM_BACKEND_DAI_SLIMBUS_7_RX, + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, +MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("DTMF", MSM_BACKEND_DAI_SLIMBUS_7_RX, + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, +MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QCHAT", MSM_BACKEND_DAI_SLIMBUS_7_RX, + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, +MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode1", MSM_BACKEND_DAI_SLIMBUS_7_RX, + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, +MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode2", MSM_BACKEND_DAI_SLIMBUS_7_RX, + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, +MSM_BACKEND_DAI_SLIMBUS_7_RX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), }; static const struct snd_kcontrol_new slimbus_8_rx_voice_mixer_controls[] = { - SOC_SINGLE_EXT("Voip", MSM_BACKEND_DAI_SLIMBUS_8_RX, + SOC_DOUBLE_EXT("Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_8_RX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("DTMF", MSM_BACKEND_DAI_SLIMBUS_8_RX, + SOC_DOUBLE_EXT("DTMF", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_8_RX, MSM_FRONTEND_DAI_DTMF_RX, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QCHAT", MSM_BACKEND_DAI_SLIMBUS_8_RX, + SOC_DOUBLE_EXT("QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_8_RX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode1", MSM_BACKEND_DAI_SLIMBUS_8_RX, + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_8_RX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode2", MSM_BACKEND_DAI_SLIMBUS_8_RX, + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_8_RX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), }; static const struct snd_kcontrol_new quat_tdm_rx_2_voice_mixer_controls[] = { - SOC_SINGLE_EXT("VoiceMMode1", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), }; static const struct snd_kcontrol_new stub_rx_mixer_controls[] = { - SOC_SINGLE_EXT("VoiceMMode1", MSM_BACKEND_DAI_EXTPROC_RX, + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_EXTPROC_RX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode2", MSM_BACKEND_DAI_EXTPROC_RX, + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_EXTPROC_RX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), }; static const struct snd_kcontrol_new slimbus_1_rx_mixer_controls[] = { - SOC_SINGLE_EXT("VoiceMMode1", MSM_BACKEND_DAI_SLIMBUS_1_RX, + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_RX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode2", MSM_BACKEND_DAI_SLIMBUS_1_RX, + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_RX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), }; static const struct snd_kcontrol_new slimbus_3_rx_mixer_controls[] = { - SOC_SINGLE_EXT("VoiceMMode1", MSM_BACKEND_DAI_SLIMBUS_3_RX, + SOC_DOUBLE_EXT("VoiceMMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_RX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("VoiceMMode2", MSM_BACKEND_DAI_SLIMBUS_3_RX, + SOC_DOUBLE_EXT("VoiceMMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_RX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), }; static const struct snd_kcontrol_new tx_voicemmode1_mixer_controls[] = { - SOC_SINGLE_EXT("PRI_TX_MMode1", MSM_BACKEND_DAI_PRI_I2S_TX, + SOC_DOUBLE_EXT("PRI_TX_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("MI2S_TX_MMode1", MSM_BACKEND_DAI_MI2S_TX, + SOC_DOUBLE_EXT("MI2S_TX_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("SLIM_0_TX_MMode1", + SOC_DOUBLE_EXT("SLIM_0_TX_MMode1", SND_SOC_NOPM, MSM_BACKEND_DAI_SLIMBUS_0_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("INT_BT_SCO_TX_MMode1", + SOC_DOUBLE_EXT("INT_BT_SCO_TX_MMode1", SND_SOC_NOPM, MSM_BACKEND_DAI_INT_BT_SCO_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX_MMode1", + SOC_DOUBLE_EXT("AFE_PCM_TX_MMode1", SND_SOC_NOPM, MSM_BACKEND_DAI_AFE_PCM_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("AUX_PCM_TX_MMode1", + SOC_DOUBLE_EXT("AUX_PCM_TX_MMode1", SND_SOC_NOPM, MSM_BACKEND_DAI_AUXPCM_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_TX_MMode1", + SOC_DOUBLE_EXT("SEC_AUX_PCM_TX_MMode1", SND_SOC_NOPM, MSM_BACKEND_DAI_SEC_AUXPCM_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("TERT_AUX_PCM_TX_MMode1", + SOC_DOUBLE_EXT("TERT_AUX_PCM_TX_MMode1", SND_SOC_NOPM, MSM_BACKEND_DAI_TERT_AUXPCM_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QUAT_AUX_PCM_TX_MMode1", + SOC_DOUBLE_EXT("QUAT_AUX_PCM_TX_MMode1", SND_SOC_NOPM, MSM_BACKEND_DAI_QUAT_AUXPCM_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QUIN_AUX_PCM_TX_MMode1", + SOC_DOUBLE_EXT("QUIN_AUX_PCM_TX_MMode1", SND_SOC_NOPM, MSM_BACKEND_DAI_QUIN_AUXPCM_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("PRI_MI2S_TX_MMode1", + SOC_DOUBLE_EXT("PRI_MI2S_TX_MMode1", SND_SOC_NOPM, MSM_BACKEND_DAI_PRI_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX_MMode1", + SOC_DOUBLE_EXT("TERT_MI2S_TX_MMode1", SND_SOC_NOPM, MSM_BACKEND_DAI_TERTIARY_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("INT3_MI2S_TX_MMode1", + SOC_DOUBLE_EXT("INT3_MI2S_TX_MMode1", SND_SOC_NOPM, MSM_BACKEND_DAI_INT3_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("SLIM_7_TX_MMode1", + SOC_DOUBLE_EXT("SLIM_7_TX_MMode1", SND_SOC_NOPM, MSM_BACKEND_DAI_SLIMBUS_7_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("SLIM_8_TX_MMode1", + SOC_DOUBLE_EXT("SLIM_8_TX_MMode1", SND_SOC_NOPM, MSM_BACKEND_DAI_SLIMBUS_8_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("USB_AUDIO_TX_MMode1", MSM_BACKEND_DAI_USB_TX, + SOC_DOUBLE_EXT("USB_AUDIO_TX_MMode1", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_0_MMode1", + SOC_DOUBLE_EXT("QUAT_TDM_TX_0_MMode1", SND_SOC_NOPM, MSM_BACKEND_DAI_QUAT_TDM_TX_0, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX_MMode1", + SOC_DOUBLE_EXT("QUAT_MI2S_TX_MMode1", SND_SOC_NOPM, MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QUIN_MI2S_TX_MMode1", + SOC_DOUBLE_EXT("QUIN_MI2S_TX_MMode1", SND_SOC_NOPM, MSM_BACKEND_DAI_QUINARY_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE1, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), }; static const struct snd_kcontrol_new tx_voicemmode2_mixer_controls[] = { - SOC_SINGLE_EXT("PRI_TX_MMode2", MSM_BACKEND_DAI_PRI_I2S_TX, + SOC_DOUBLE_EXT("PRI_TX_MMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("MI2S_TX_MMode2", MSM_BACKEND_DAI_MI2S_TX, + SOC_DOUBLE_EXT("MI2S_TX_MMode2", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("SLIM_0_TX_MMode2", + SOC_DOUBLE_EXT("SLIM_0_TX_MMode2", SND_SOC_NOPM, MSM_BACKEND_DAI_SLIMBUS_0_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("INT_BT_SCO_TX_MMode2", + SOC_DOUBLE_EXT("INT_BT_SCO_TX_MMode2", SND_SOC_NOPM, MSM_BACKEND_DAI_INT_BT_SCO_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX_MMode2", + SOC_DOUBLE_EXT("AFE_PCM_TX_MMode2", SND_SOC_NOPM, MSM_BACKEND_DAI_AFE_PCM_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("AUX_PCM_TX_MMode2", + SOC_DOUBLE_EXT("AUX_PCM_TX_MMode2", SND_SOC_NOPM, MSM_BACKEND_DAI_AUXPCM_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_TX_MMode2", + SOC_DOUBLE_EXT("SEC_AUX_PCM_TX_MMode2", SND_SOC_NOPM, MSM_BACKEND_DAI_SEC_AUXPCM_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("TERT_AUX_PCM_TX_MMode2", + SOC_DOUBLE_EXT("TERT_AUX_PCM_TX_MMode2", SND_SOC_NOPM, MSM_BACKEND_DAI_TERT_AUXPCM_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QUAT_AUX_PCM_TX_MMode2", + SOC_DOUBLE_EXT("QUAT_AUX_PCM_TX_MMode2", SND_SOC_NOPM, MSM_BACKEND_DAI_QUAT_AUXPCM_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QUIN_AUX_PCM_TX_MMode2", + SOC_DOUBLE_EXT("QUIN_AUX_PCM_TX_MMode2", SND_SOC_NOPM, MSM_BACKEND_DAI_QUIN_AUXPCM_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("PRI_MI2S_TX_MMode2", + SOC_DOUBLE_EXT("PRI_MI2S_TX_MMode2", SND_SOC_NOPM, MSM_BACKEND_DAI_PRI_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX_MMode2", + SOC_DOUBLE_EXT("TERT_MI2S_TX_MMode2", SND_SOC_NOPM, MSM_BACKEND_DAI_TERTIARY_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("INT3_MI2S_TX_MMode2", + SOC_DOUBLE_EXT("INT3_MI2S_TX_MMode2", SND_SOC_NOPM, MSM_BACKEND_DAI_INT3_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("SLIM_7_TX_MMode2", + SOC_DOUBLE_EXT("SLIM_7_TX_MMode2", SND_SOC_NOPM, MSM_BACKEND_DAI_SLIMBUS_7_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("SLIM_8_TX_MMode2", + SOC_DOUBLE_EXT("SLIM_8_TX_MMode2", SND_SOC_NOPM, MSM_BACKEND_DAI_SLIMBUS_8_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("USB_AUDIO_TX_MMode2", + SOC_DOUBLE_EXT("USB_AUDIO_TX_MMode2", SND_SOC_NOPM, MSM_BACKEND_DAI_USB_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX_MMode2", + SOC_DOUBLE_EXT("QUAT_MI2S_TX_MMode2", SND_SOC_NOPM, MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QUIN_MI2S_TX_MMode2", + SOC_DOUBLE_EXT("QUIN_MI2S_TX_MMode2", SND_SOC_NOPM, MSM_BACKEND_DAI_QUINARY_MI2S_TX, MSM_FRONTEND_DAI_VOICEMMODE2, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), }; static const struct snd_kcontrol_new tx_voip_mixer_controls[] = { - SOC_SINGLE_EXT("PRI_TX_Voip", MSM_BACKEND_DAI_PRI_I2S_TX, + SOC_DOUBLE_EXT("PRI_TX_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_TX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("MI2S_TX_Voip", MSM_BACKEND_DAI_MI2S_TX, + SOC_DOUBLE_EXT("MI2S_TX_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_TX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("SLIM_0_TX_Voip", MSM_BACKEND_DAI_SLIMBUS_0_TX, + SOC_DOUBLE_EXT("SLIM_0_TX_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX_Voip", MSM_BACKEND_DAI_INT_BT_SCO_TX, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX_Voip", MSM_BACKEND_DAI_AFE_PCM_TX, + SOC_DOUBLE_EXT("AFE_PCM_TX_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("AUX_PCM_TX_Voip", MSM_BACKEND_DAI_AUXPCM_TX, + SOC_DOUBLE_EXT("AUX_PCM_TX_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_TX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_TX_Voip", MSM_BACKEND_DAI_SEC_AUXPCM_TX, + SOC_DOUBLE_EXT("SEC_AUX_PCM_TX_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("TERT_AUX_PCM_TX_Voip", MSM_BACKEND_DAI_TERT_AUXPCM_TX, + SOC_DOUBLE_EXT("TERT_AUX_PCM_TX_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_TX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QUAT_AUX_PCM_TX_Voip", MSM_BACKEND_DAI_QUAT_AUXPCM_TX, + SOC_DOUBLE_EXT("QUAT_AUX_PCM_TX_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_TX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QUIN_AUX_PCM_TX_Voip", MSM_BACKEND_DAI_QUIN_AUXPCM_TX, + SOC_DOUBLE_EXT("QUIN_AUX_PCM_TX_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_TX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("PRI_MI2S_TX_Voip", MSM_BACKEND_DAI_PRI_MI2S_TX, + SOC_DOUBLE_EXT("PRI_MI2S_TX_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX_Voip", MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + SOC_DOUBLE_EXT("TERT_MI2S_TX_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("INT3_MI2S_TX_Voip", MSM_BACKEND_DAI_INT3_MI2S_TX, + SOC_DOUBLE_EXT("INT3_MI2S_TX_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("SLIM_7_TX_Voip", MSM_BACKEND_DAI_SLIMBUS_7_TX, + SOC_DOUBLE_EXT("SLIM_7_TX_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_TX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("SLIM_8_TX_Voip", MSM_BACKEND_DAI_SLIMBUS_8_TX, + SOC_DOUBLE_EXT("SLIM_8_TX_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_8_TX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("USB_AUDIO_TX_Voip", MSM_BACKEND_DAI_USB_TX, + SOC_DOUBLE_EXT("USB_AUDIO_TX_Voip", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_TX, MSM_FRONTEND_DAI_VOIP, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), }; static const struct snd_kcontrol_new tx_voice_stub_mixer_controls[] = { - SOC_SINGLE_EXT("STUB_TX_HL", MSM_BACKEND_DAI_EXTPROC_TX, + SOC_DOUBLE_EXT("STUB_TX_HL", SND_SOC_NOPM, + MSM_BACKEND_DAI_EXTPROC_TX, MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_INT_BT_SCO_TX, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("SLIM_1_TX", MSM_BACKEND_DAI_SLIMBUS_1_TX, + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("STUB_1_TX_HL", MSM_BACKEND_DAI_EXTPROC_EC_TX, + SOC_DOUBLE_EXT("STUB_1_TX_HL", SND_SOC_NOPM, + MSM_BACKEND_DAI_EXTPROC_EC_TX, MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("MI2S_TX", MSM_BACKEND_DAI_MI2S_TX, + SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_TX, MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_PRI_MI2S_TX, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("INT3_MI2S_TX", MSM_BACKEND_DAI_INT3_MI2S_TX, + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_AUXPCM_TX, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_TX, MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_UL_TX", MSM_BACKEND_DAI_SEC_AUXPCM_TX, + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("TERT_AUXPCM_UL_TX", MSM_BACKEND_DAI_TERT_AUXPCM_TX, + SOC_DOUBLE_EXT("TERT_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_TX, MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("QUAT_AUXPCM_UL_TX", MSM_BACKEND_DAI_QUAT_AUXPCM_TX, + SOC_DOUBLE_EXT("QUAT_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_TX, MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("QUIN_AUXPCM_UL_TX", MSM_BACKEND_DAI_QUIN_AUXPCM_TX, + SOC_DOUBLE_EXT("QUIN_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_TX, MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("SLIM_0_TX", MSM_BACKEND_DAI_SLIMBUS_0_TX, + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("SLIM_3_TX", MSM_BACKEND_DAI_SLIMBUS_3_TX, + SOC_DOUBLE_EXT("SLIM_3_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_TX, MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_AFE_PCM_TX, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("SLIM_7_TX", MSM_BACKEND_DAI_SLIMBUS_7_TX, + SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_TX, MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("SLIM_8_TX", MSM_BACKEND_DAI_SLIMBUS_8_TX, + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_8_TX, MSM_FRONTEND_DAI_VOICE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), }; static const struct snd_kcontrol_new tx_voice2_stub_mixer_controls[] = { - SOC_SINGLE_EXT("STUB_TX_HL", MSM_BACKEND_DAI_EXTPROC_TX, + SOC_DOUBLE_EXT("STUB_TX_HL", SND_SOC_NOPM, + MSM_BACKEND_DAI_EXTPROC_TX, MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("SLIM_1_TX", MSM_BACKEND_DAI_SLIMBUS_1_TX, + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("STUB_1_TX_HL", MSM_BACKEND_DAI_EXTPROC_EC_TX, + SOC_DOUBLE_EXT("STUB_1_TX_HL", SND_SOC_NOPM, + MSM_BACKEND_DAI_EXTPROC_EC_TX, MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_AUXPCM_TX, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_TX, MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_UL_TX", MSM_BACKEND_DAI_SEC_AUXPCM_TX, + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("TERT_AUXPCM_UL_TX", MSM_BACKEND_DAI_TERT_AUXPCM_TX, + SOC_DOUBLE_EXT("TERT_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_TX, MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("QUAT_AUXPCM_UL_TX", MSM_BACKEND_DAI_QUAT_AUXPCM_TX, + SOC_DOUBLE_EXT("QUAT_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_TX, MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("QUIN_AUXPCM_UL_TX", MSM_BACKEND_DAI_QUIN_AUXPCM_TX, + SOC_DOUBLE_EXT("QUIN_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_TX, MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("SLIM_0_TX", MSM_BACKEND_DAI_SLIMBUS_0_TX, + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("SLIM_3_TX", MSM_BACKEND_DAI_SLIMBUS_3_TX, + SOC_DOUBLE_EXT("SLIM_3_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_TX, MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_AFE_PCM_TX, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_PRI_MI2S_TX, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("SLIM_7_TX", MSM_BACKEND_DAI_SLIMBUS_7_TX, + SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_TX, MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("SLIM_8_TX", MSM_BACKEND_DAI_SLIMBUS_8_TX, + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_8_TX, MSM_FRONTEND_DAI_VOICE2_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), }; static const struct snd_kcontrol_new tx_volte_stub_mixer_controls[] = { - SOC_SINGLE_EXT("STUB_TX_HL", MSM_BACKEND_DAI_EXTPROC_TX, + SOC_DOUBLE_EXT("STUB_TX_HL", SND_SOC_NOPM, + MSM_BACKEND_DAI_EXTPROC_TX, MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("SLIM_1_TX", MSM_BACKEND_DAI_SLIMBUS_1_TX, + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("STUB_1_TX_HL", MSM_BACKEND_DAI_EXTPROC_EC_TX, + SOC_DOUBLE_EXT("STUB_1_TX_HL", SND_SOC_NOPM, + MSM_BACKEND_DAI_EXTPROC_EC_TX, MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_AUXPCM_TX, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_TX, MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_UL_TX", MSM_BACKEND_DAI_SEC_AUXPCM_TX, + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("TERT_AUXPCM_UL_TX", MSM_BACKEND_DAI_TERT_AUXPCM_TX, + SOC_DOUBLE_EXT("TERT_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_TX, MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("QUAT_AUXPCM_UL_TX", MSM_BACKEND_DAI_QUAT_AUXPCM_TX, + SOC_DOUBLE_EXT("QUAT_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_TX, MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("QUIN_AUXPCM_UL_TX", MSM_BACKEND_DAI_QUIN_AUXPCM_TX, + SOC_DOUBLE_EXT("QUIN_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_TX, MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("SLIM_0_TX", MSM_BACKEND_DAI_SLIMBUS_0_TX, + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("SLIM_3_TX", MSM_BACKEND_DAI_SLIMBUS_3_TX, + SOC_DOUBLE_EXT("SLIM_3_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_TX, MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_AFE_PCM_TX, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_PRI_MI2S_TX, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("SLIM_7_TX", MSM_BACKEND_DAI_SLIMBUS_7_TX, + SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_TX, MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), - SOC_SINGLE_EXT("SLIM_8_TX", MSM_BACKEND_DAI_SLIMBUS_8_TX, + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_8_TX, MSM_FRONTEND_DAI_VOLTE_STUB, 1, 0, msm_routing_get_voice_stub_mixer, msm_routing_put_voice_stub_mixer), }; static const struct snd_kcontrol_new tx_qchat_mixer_controls[] = { - SOC_SINGLE_EXT("PRI_TX_QCHAT", MSM_BACKEND_DAI_PRI_I2S_TX, + SOC_DOUBLE_EXT("PRI_TX_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_I2S_TX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("SLIM_0_TX_QCHAT", MSM_BACKEND_DAI_SLIMBUS_0_TX, + SOC_DOUBLE_EXT("SLIM_0_TX_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX_QCHAT", - MSM_BACKEND_DAI_INT_BT_SCO_TX, MSM_FRONTEND_DAI_QCHAT, 1, 0, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_TX, + MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX_QCHAT", MSM_BACKEND_DAI_AFE_PCM_TX, + SOC_DOUBLE_EXT("AFE_PCM_TX_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_TX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("AUX_PCM_TX_QCHAT", MSM_BACKEND_DAI_AUXPCM_TX, + SOC_DOUBLE_EXT("AUX_PCM_TX_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_TX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_TX_QCHAT", MSM_BACKEND_DAI_SEC_AUXPCM_TX, + SOC_DOUBLE_EXT("SEC_AUX_PCM_TX_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_TX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("TERT_AUX_PCM_TX_QCHAT", MSM_BACKEND_DAI_TERT_AUXPCM_TX, + SOC_DOUBLE_EXT("TERT_AUX_PCM_TX_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_TX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QUAT_AUX_PCM_TX_QCHAT", MSM_BACKEND_DAI_QUAT_AUXPCM_TX, + SOC_DOUBLE_EXT("QUAT_AUX_PCM_TX_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_TX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("QUIN_AUX_PCM_TX_QCHAT", MSM_BACKEND_DAI_QUIN_AUXPCM_TX, + SOC_DOUBLE_EXT("QUIN_AUX_PCM_TX_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_TX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("MI2S_TX_QCHAT", MSM_BACKEND_DAI_MI2S_TX, + SOC_DOUBLE_EXT("MI2S_TX_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_TX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("PRI_MI2S_TX_QCHAT", MSM_BACKEND_DAI_PRI_MI2S_TX, + SOC_DOUBLE_EXT("PRI_MI2S_TX_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_TX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX_QCHAT", MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + SOC_DOUBLE_EXT("TERT_MI2S_TX_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("INT3_MI2S_TX_QCHAT", MSM_BACKEND_DAI_INT3_MI2S_TX, + SOC_DOUBLE_EXT("INT3_MI2S_TX_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("SLIM_7_TX_QCHAT", MSM_BACKEND_DAI_SLIMBUS_7_TX, + SOC_DOUBLE_EXT("SLIM_7_TX_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_7_TX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("SLIM_8_TX_QCHAT", MSM_BACKEND_DAI_SLIMBUS_8_TX, + SOC_DOUBLE_EXT("SLIM_8_TX_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_8_TX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), - SOC_SINGLE_EXT("USB_AUDIO_TX_QCHAT", MSM_BACKEND_DAI_USB_TX, + SOC_DOUBLE_EXT("USB_AUDIO_TX_QCHAT", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_TX, MSM_FRONTEND_DAI_QCHAT, 1, 0, msm_routing_get_voice_mixer, msm_routing_put_voice_mixer), }; static const struct snd_kcontrol_new int0_mi2s_rx_port_mixer_controls[] = { - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_INT0_MI2S_RX, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_INT0_MI2S_RX, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_INT0_MI2S_RX, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_INT0_MI2S_RX, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_MI2S_TX", MSM_BACKEND_DAI_INT0_MI2S_RX, + SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, MSM_BACKEND_DAI_QUINARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INT3_MI2S_TX", MSM_BACKEND_DAI_INT0_MI2S_RX, + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, MSM_BACKEND_DAI_INT3_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_INT0_MI2S_RX, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_INT0_MI2S_RX, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SLIM_7_TX", MSM_BACKEND_DAI_INT0_MI2S_RX, + SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, MSM_BACKEND_DAI_SLIMBUS_7_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SLIM_8_TX", MSM_BACKEND_DAI_INT0_MI2S_RX, + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT0_MI2S_RX, MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new int4_mi2s_rx_port_mixer_controls[] = { - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_INT4_MI2S_RX, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_INT4_MI2S_RX, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_INT4_MI2S_RX, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_INT4_MI2S_RX, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_MI2S_TX", MSM_BACKEND_DAI_INT4_MI2S_RX, + SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, MSM_BACKEND_DAI_QUINARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INT3_MI2S_TX", MSM_BACKEND_DAI_INT4_MI2S_RX, + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, MSM_BACKEND_DAI_INT3_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_INT4_MI2S_RX, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_INT4_MI2S_RX, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SLIM_7_TX", MSM_BACKEND_DAI_INT4_MI2S_RX, + SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, MSM_BACKEND_DAI_SLIMBUS_7_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SLIM_8_TX", MSM_BACKEND_DAI_INT4_MI2S_RX, + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT4_MI2S_RX, MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new sbus_0_rx_port_mixer_controls[] = { - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SLIM_0_TX", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SLIM_1_TX", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_BACKEND_DAI_SLIMBUS_1_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SLIM_7_TX", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_BACKEND_DAI_SLIMBUS_7_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SLIM_8_TX", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_UL_TX", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_AUXPCM_UL_TX", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("TERT_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_BACKEND_DAI_TERT_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_AUXPCM_UL_TX", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("QUAT_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_BACKEND_DAI_QUAT_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_AUXPCM_UL_TX", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("QUIN_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_BACKEND_DAI_QUIN_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("MI2S_TX", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_BACKEND_DAI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_MI2S_TX", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_BACKEND_DAI_QUINARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("PRI_MI2S_RX", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("PRI_MI2S_RX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_BACKEND_DAI_PRI_MI2S_RX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_MI2S_RX", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("SEC_MI2S_RX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_BACKEND_DAI_SECONDARY_MI2S_RX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_MI2S_RX", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("TERT_MI2S_RX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_BACKEND_DAI_TERTIARY_MI2S_RX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_RX", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("QUAT_MI2S_RX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_MI2S_RX", MSM_BACKEND_DAI_SLIMBUS_0_RX, + SOC_DOUBLE_EXT("QUIN_MI2S_RX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_RX, MSM_BACKEND_DAI_QUINARY_MI2S_RX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new aux_pcm_rx_port_mixer_controls[] = { - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_AUXPCM_RX, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SLIM_0_TX", MSM_BACKEND_DAI_AUXPCM_RX, + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SLIM_1_TX", MSM_BACKEND_DAI_AUXPCM_RX, + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_BACKEND_DAI_SLIMBUS_1_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_UL_TX", MSM_BACKEND_DAI_AUXPCM_RX, + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_0", MSM_BACKEND_DAI_AUXPCM_RX, + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_AUXPCM_RX, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AUXPCM_RX, MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new sec_auxpcm_rx_port_mixer_controls[] = { - SOC_SINGLE_EXT("SEC_AUX_PCM_UL_TX", MSM_BACKEND_DAI_SEC_AUXPCM_RX, + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SLIM_0_TX", MSM_BACKEND_DAI_SEC_AUXPCM_RX, + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_SEC_AUXPCM_RX, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_SEC_AUXPCM_RX, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_AUXPCM_RX, MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new tert_auxpcm_rx_port_mixer_controls[] = { - SOC_SINGLE_EXT("TERT_AUXPCM_UL_TX", MSM_BACKEND_DAI_TERT_AUXPCM_RX, + SOC_DOUBLE_EXT("TERT_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_BACKEND_DAI_TERT_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SLIM_0_TX", MSM_BACKEND_DAI_TERT_AUXPCM_RX, + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_TERT_AUXPCM_RX, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_AUXPCM_RX, MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new quat_auxpcm_rx_port_mixer_controls[] = { - SOC_SINGLE_EXT("QUAT_AUXPCM_UL_TX", MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + SOC_DOUBLE_EXT("QUAT_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_BACKEND_DAI_QUAT_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SLIM_0_TX", MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_QUAT_AUXPCM_RX, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_AUXPCM_RX, MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new quin_auxpcm_rx_port_mixer_controls[] = { - SOC_SINGLE_EXT("QUIN_AUXPCM_UL_TX", MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + SOC_DOUBLE_EXT("QUIN_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_BACKEND_DAI_QUIN_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SLIM_0_TX", MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_QUIN_AUXPCM_RX, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_AUXPCM_RX, MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new sbus_1_rx_port_mixer_controls[] = { - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_SLIMBUS_1_RX, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_RX, MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_SLIMBUS_1_RX, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_RX, MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_SLIMBUS_1_RX, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_RX, MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_UL_TX", MSM_BACKEND_DAI_SLIMBUS_1_RX, + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_RX, MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_AUXPCM_UL_TX", MSM_BACKEND_DAI_SLIMBUS_1_RX, + SOC_DOUBLE_EXT("TERT_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_RX, MSM_BACKEND_DAI_TERT_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_AUXPCM_UL_TX", MSM_BACKEND_DAI_SLIMBUS_1_RX, + SOC_DOUBLE_EXT("QUAT_AUXPCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_RX, MSM_BACKEND_DAI_QUAT_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new sbus_3_rx_port_mixer_controls[] = { - SOC_SINGLE_EXT("INTERNAL_BT_SCO_RX", MSM_BACKEND_DAI_SLIMBUS_3_RX, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_RX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_RX, MSM_BACKEND_DAI_INT_BT_SCO_RX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("MI2S_TX", MSM_BACKEND_DAI_SLIMBUS_3_RX, + SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_RX, MSM_BACKEND_DAI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AFE_PCM_RX", MSM_BACKEND_DAI_SLIMBUS_3_RX, + SOC_DOUBLE_EXT("AFE_PCM_RX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_RX, MSM_BACKEND_DAI_AFE_PCM_RX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AUX_PCM_RX", MSM_BACKEND_DAI_SLIMBUS_3_RX, + SOC_DOUBLE_EXT("AUX_PCM_RX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_RX, MSM_BACKEND_DAI_AUXPCM_RX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SLIM_0_RX", MSM_BACKEND_DAI_SLIMBUS_3_RX, + SOC_DOUBLE_EXT("SLIM_0_RX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_RX, MSM_BACKEND_DAI_SLIMBUS_0_RX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new sbus_6_rx_port_mixer_controls[] = { - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_SLIMBUS_6_RX, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SLIM_0_TX", MSM_BACKEND_DAI_SLIMBUS_6_RX, + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SLIM_1_TX", MSM_BACKEND_DAI_SLIMBUS_6_RX, + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_BACKEND_DAI_SLIMBUS_1_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SLIM_7_TX", MSM_BACKEND_DAI_SLIMBUS_6_RX, + SOC_DOUBLE_EXT("SLIM_7_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_BACKEND_DAI_SLIMBUS_7_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SLIM_8_TX", MSM_BACKEND_DAI_SLIMBUS_6_RX, + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_SLIMBUS_6_RX, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_UL_TX", MSM_BACKEND_DAI_SLIMBUS_6_RX, + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("MI2S_TX", MSM_BACKEND_DAI_SLIMBUS_6_RX, + SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_BACKEND_DAI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_SLIMBUS_6_RX, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_SLIMBUS_6_RX, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_SLIMBUS_6_RX, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_SLIMBUS_6_RX, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_6_RX, MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new bt_sco_rx_port_mixer_controls[] = { - SOC_SINGLE_EXT("SLIM_1_TX", MSM_BACKEND_DAI_INT_BT_SCO_RX, + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_BACKEND_DAI_SLIMBUS_1_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SLIM_0_TX", MSM_BACKEND_DAI_INT_BT_SCO_RX, + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT_BT_SCO_RX, MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new afe_pcm_rx_port_mixer_controls[] = { - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_AFE_PCM_RX, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SLIM_1_TX", MSM_BACKEND_DAI_AFE_PCM_RX, + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_AFE_PCM_RX, MSM_BACKEND_DAI_SLIMBUS_1_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new hdmi_rx_port_mixer_controls[] = { - SOC_SINGLE_EXT("MI2S_TX", MSM_BACKEND_DAI_HDMI_RX, + SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_HDMI_RX, MSM_BACKEND_DAI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new display_port_rx_port_mixer_controls[] = { - SOC_SINGLE_EXT("MI2S_TX", MSM_BACKEND_DAI_DISPLAY_PORT_RX, + SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_DISPLAY_PORT_RX, MSM_BACKEND_DAI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new sec_i2s_rx_port_mixer_controls[] = { - SOC_SINGLE_EXT("MI2S_TX", MSM_BACKEND_DAI_SEC_I2S_RX, + SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_I2S_RX, MSM_BACKEND_DAI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new mi2s_rx_port_mixer_controls[] = { - SOC_SINGLE_EXT("SLIM_1_TX", MSM_BACKEND_DAI_MI2S_RX, + SOC_DOUBLE_EXT("SLIM_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, MSM_BACKEND_DAI_SLIMBUS_1_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("MI2S_TX", MSM_BACKEND_DAI_MI2S_RX, + SOC_DOUBLE_EXT("MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_MI2S_RX, MSM_BACKEND_DAI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new primary_mi2s_rx_port_mixer_controls[] = { - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_MI2S_TX", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_BACKEND_DAI_QUINARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SLIM_0_TX", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SLIM_8_TX", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_UL_TX", MSM_BACKEND_DAI_PRI_MI2S_RX, + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_MI2S_RX, MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new usb_rx_port_mixer_controls[] = { - SOC_SINGLE_EXT("USB_AUDIO_TX", MSM_BACKEND_DAI_USB_RX, + SOC_DOUBLE_EXT("USB_AUDIO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_USB_RX, MSM_BACKEND_DAI_USB_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new quat_mi2s_rx_port_mixer_controls[] = { - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SLIM_0_TX", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_MI2S_TX", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_BACKEND_DAI_QUINARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SLIM_8_TX", MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_RX, MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new quin_mi2s_rx_port_mixer_controls[] = { - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SLIM_0_TX", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_MI2S_TX", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_BACKEND_DAI_QUINARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SLIM_8_TX", MSM_BACKEND_DAI_QUINARY_MI2S_RX, + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUINARY_MI2S_RX, MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new pri_tdm_rx_0_port_mixer_controls[] = { - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_UL_TX", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_0", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_BACKEND_DAI_PRI_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_1", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_BACKEND_DAI_PRI_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_2", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_BACKEND_DAI_PRI_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_3", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_BACKEND_DAI_PRI_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_0", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_1", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_2", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_3", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_0", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_1", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_2", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_3", MSM_BACKEND_DAI_PRI_TDM_RX_0, + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_0, MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new pri_tdm_rx_1_port_mixer_controls[] = { - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_UL_TX", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_0", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_BACKEND_DAI_PRI_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_1", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_BACKEND_DAI_PRI_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_2", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_BACKEND_DAI_PRI_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_3", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_BACKEND_DAI_PRI_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_0", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_1", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_2", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_3", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_0", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_1", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_2", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_3", MSM_BACKEND_DAI_PRI_TDM_RX_1, + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_1, MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new pri_tdm_rx_2_port_mixer_controls[] = { - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_UL_TX", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_0", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_BACKEND_DAI_PRI_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_1", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_BACKEND_DAI_PRI_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_2", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_BACKEND_DAI_PRI_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_3", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_BACKEND_DAI_PRI_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_0", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_1", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_2", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_3", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_0", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_1", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_2", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_3", MSM_BACKEND_DAI_PRI_TDM_RX_2, + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_2, MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new pri_tdm_rx_3_port_mixer_controls[] = { - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_UL_TX", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_0", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("PRI_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_BACKEND_DAI_PRI_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_1", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("PRI_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_BACKEND_DAI_PRI_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_2", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("PRI_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_BACKEND_DAI_PRI_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("PRI_TDM_TX_3", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("PRI_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_BACKEND_DAI_PRI_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_0", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_1", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_2", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_3", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_0", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_1", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_2", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_3", MSM_BACKEND_DAI_PRI_TDM_RX_3, + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_PRI_TDM_RX_3, MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new sec_tdm_rx_0_port_mixer_controls[] = { - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_UL_TX", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_0", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_BACKEND_DAI_SEC_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_1", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_BACKEND_DAI_SEC_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_2", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_BACKEND_DAI_SEC_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_3", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_BACKEND_DAI_SEC_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_0", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_1", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_2", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_3", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_0", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_1", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_2", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_3", MSM_BACKEND_DAI_SEC_TDM_RX_0, + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_0, MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new sec_tdm_rx_1_port_mixer_controls[] = { - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_UL_TX", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_0", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_BACKEND_DAI_SEC_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_1", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_BACKEND_DAI_SEC_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_2", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_BACKEND_DAI_SEC_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_3", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_BACKEND_DAI_SEC_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_0", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_1", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_2", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_3", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_0", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_1", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_2", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_3", MSM_BACKEND_DAI_SEC_TDM_RX_1, + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_1, MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new sec_tdm_rx_2_port_mixer_controls[] = { - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_UL_TX", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_0", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_BACKEND_DAI_SEC_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_1", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_BACKEND_DAI_SEC_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_2", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_BACKEND_DAI_SEC_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_3", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_BACKEND_DAI_SEC_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_0", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_1", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_2", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_3", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_0", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_1", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_2", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_3", MSM_BACKEND_DAI_SEC_TDM_RX_2, + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_2, MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new sec_tdm_rx_3_port_mixer_controls[] = { - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_UL_TX", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_0", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("SEC_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_BACKEND_DAI_SEC_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_1", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("SEC_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_BACKEND_DAI_SEC_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_2", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("SEC_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_BACKEND_DAI_SEC_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_TDM_TX_3", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("SEC_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_BACKEND_DAI_SEC_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_0", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_1", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_2", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_3", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_0", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_1", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_2", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_3", MSM_BACKEND_DAI_SEC_TDM_RX_3, + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_SEC_TDM_RX_3, MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new tert_tdm_rx_0_port_mixer_controls[] = { - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_UL_TX", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_0", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_1", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_2", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_3", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_0", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_1", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_2", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_3", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_0", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_1", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_2", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_3", MSM_BACKEND_DAI_TERT_TDM_RX_0, + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_0, MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new tert_tdm_rx_1_port_mixer_controls[] = { - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_UL_TX", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_0", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_1", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_2", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_3", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_0", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_1", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_2", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_3", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_0", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_1", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_2", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_3", MSM_BACKEND_DAI_TERT_TDM_RX_1, + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_1, MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new tert_tdm_rx_2_port_mixer_controls[] = { - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_UL_TX", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_0", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_1", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_2", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_3", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_0", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_1", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_2", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_3", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_0", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_1", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_2", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_3", MSM_BACKEND_DAI_TERT_TDM_RX_2, + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_2, MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new tert_tdm_rx_3_port_mixer_controls[] = { - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_UL_TX", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_0", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_1", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_2", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_3", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_0", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_1", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_2", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_3", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_0", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_1", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_2", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_3", MSM_BACKEND_DAI_TERT_TDM_RX_3, + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERT_TDM_RX_3, MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new quat_tdm_rx_0_port_mixer_controls[] = { - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_UL_TX", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_0", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_1", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_2", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_3", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_0", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_1", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_2", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_3", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_0", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_1", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_2", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_3", MSM_BACKEND_DAI_QUAT_TDM_RX_0, + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_0, MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new quat_tdm_rx_1_port_mixer_controls[] = { - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_UL_TX", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_0", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_1", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_2", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_3", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_0", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_1", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_2", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_3", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_0", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_1", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_2", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_3", MSM_BACKEND_DAI_QUAT_TDM_RX_1, + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_1, MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new quat_tdm_rx_2_port_mixer_controls[] = { - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_UL_TX", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_0", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_1", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_2", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_3", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_0", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_1", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_2", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_3", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_0", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_1", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_2", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_3", MSM_BACKEND_DAI_QUAT_TDM_RX_2, + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_2, MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new quat_tdm_rx_3_port_mixer_controls[] = { - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_UL_TX", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_0", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_1", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_2", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_3", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_0", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_1", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_2", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_3", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_0", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_1", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_2", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_3", MSM_BACKEND_DAI_QUAT_TDM_RX_3, + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUAT_TDM_RX_3, MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new quin_tdm_rx_0_port_mixer_controls[] = { - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_UL_TX", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_0", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_1", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_2", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_3", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_0", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_1", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_2", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_3", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_0", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_1", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_2", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_3", MSM_BACKEND_DAI_QUIN_TDM_RX_0, + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_0, MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new quin_tdm_rx_1_port_mixer_controls[] = { - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_UL_TX", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_0", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_1", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_2", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_3", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_0", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_1", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_2", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_3", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_0", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_1", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_2", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_3", MSM_BACKEND_DAI_QUIN_TDM_RX_1, + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_1, MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new quin_tdm_rx_2_port_mixer_controls[] = { - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_UL_TX", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_0", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_1", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_2", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_3", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_0", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_1", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_2", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_3", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_0", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_1", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_2", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_3", MSM_BACKEND_DAI_QUIN_TDM_RX_2, + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_2, MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new quin_tdm_rx_3_port_mixer_controls[] = { - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_BT_SCO_TX", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("INTERNAL_BT_SCO_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_BACKEND_DAI_INT_BT_SCO_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AFE_PCM_TX", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("AFE_PCM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_BACKEND_DAI_AFE_PCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_AUX_PCM_UL_TX", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("SEC_AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_BACKEND_DAI_SEC_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_0", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("TERT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_BACKEND_DAI_TERT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_1", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("TERT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_BACKEND_DAI_TERT_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_2", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("TERT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_BACKEND_DAI_TERT_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_TDM_TX_3", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("TERT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_BACKEND_DAI_TERT_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_0", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("QUAT_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_BACKEND_DAI_QUAT_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_1", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("QUAT_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_BACKEND_DAI_QUAT_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_2", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("QUAT_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_BACKEND_DAI_QUAT_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_TDM_TX_3", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("QUAT_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_BACKEND_DAI_QUAT_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_0", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("QUIN_TDM_TX_0", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_BACKEND_DAI_QUIN_TDM_TX_0, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_1", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("QUIN_TDM_TX_1", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_BACKEND_DAI_QUIN_TDM_TX_1, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_2", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("QUIN_TDM_TX_2", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_BACKEND_DAI_QUIN_TDM_TX_2, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_TDM_TX_3", MSM_BACKEND_DAI_QUIN_TDM_RX_3, + SOC_DOUBLE_EXT("QUIN_TDM_TX_3", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUIN_TDM_RX_3, MSM_BACKEND_DAI_QUIN_TDM_TX_3, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new tert_mi2s_rx_port_mixer_controls[] = { - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SLIM_0_TX", MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_MI2S_TX", MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, MSM_BACKEND_DAI_QUINARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SLIM_8_TX", MSM_BACKEND_DAI_TERTIARY_MI2S_RX, + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_RX, MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new sec_mi2s_rx_port_mixer_controls[] = { - SOC_SINGLE_EXT("PRI_MI2S_TX", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("PRI_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_BACKEND_DAI_PRI_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SEC_MI2S_TX", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("SEC_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_BACKEND_DAI_SECONDARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_BACKEND_DAI_TERTIARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("QUIN_MI2S_TX", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("QUIN_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_BACKEND_DAI_QUINARY_MI2S_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SLIM_0_TX", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("SLIM_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_BACKEND_DAI_SLIMBUS_0_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("INTERNAL_FM_TX", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("INTERNAL_FM_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_BACKEND_DAI_INT_FM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("SLIM_8_TX", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("SLIM_8_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_BACKEND_DAI_SLIMBUS_8_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), - SOC_SINGLE_EXT("AUX_PCM_UL_TX", MSM_BACKEND_DAI_SECONDARY_MI2S_RX, + SOC_DOUBLE_EXT("AUX_PCM_UL_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SECONDARY_MI2S_RX, MSM_BACKEND_DAI_AUXPCM_TX, 1, 0, msm_routing_get_port_mixer, msm_routing_put_port_mixer), }; static const struct snd_kcontrol_new lsm1_mixer_controls[] = { - SOC_SINGLE_EXT("SLIMBUS_0_TX", MSM_BACKEND_DAI_SLIMBUS_0_TX, + SOC_DOUBLE_EXT("SLIMBUS_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("SLIMBUS_1_TX", MSM_BACKEND_DAI_SLIMBUS_1_TX, + SOC_DOUBLE_EXT("SLIMBUS_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("SLIMBUS_3_TX", MSM_BACKEND_DAI_SLIMBUS_3_TX, + SOC_DOUBLE_EXT("SLIMBUS_3_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_TX, MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("SLIMBUS_4_TX", MSM_BACKEND_DAI_SLIMBUS_4_TX, + SOC_DOUBLE_EXT("SLIMBUS_4_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_4_TX, MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("SLIMBUS_5_TX", MSM_BACKEND_DAI_SLIMBUS_5_TX, + SOC_DOUBLE_EXT("SLIMBUS_5_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_TX, MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("INT3_MI2S_TX", MSM_BACKEND_DAI_INT3_MI2S_TX, + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, MSM_FRONTEND_DAI_LSM1, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), }; static const struct snd_kcontrol_new lsm2_mixer_controls[] = { - SOC_SINGLE_EXT("SLIMBUS_0_TX", MSM_BACKEND_DAI_SLIMBUS_0_TX, + SOC_DOUBLE_EXT("SLIMBUS_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("SLIMBUS_1_TX", MSM_BACKEND_DAI_SLIMBUS_1_TX, + SOC_DOUBLE_EXT("SLIMBUS_1_TX", + SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("SLIMBUS_3_TX", MSM_BACKEND_DAI_SLIMBUS_3_TX, + SOC_DOUBLE_EXT("SLIMBUS_3_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_TX, MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("SLIMBUS_4_TX", MSM_BACKEND_DAI_SLIMBUS_4_TX, + SOC_DOUBLE_EXT("SLIMBUS_4_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_4_TX, MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("SLIMBUS_5_TX", MSM_BACKEND_DAI_SLIMBUS_5_TX, + SOC_DOUBLE_EXT("SLIMBUS_5_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_TX, MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("INT3_MI2S_TX", MSM_BACKEND_DAI_INT3_MI2S_TX, + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, MSM_FRONTEND_DAI_LSM2, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), }; static const struct snd_kcontrol_new lsm3_mixer_controls[] = { - SOC_SINGLE_EXT("SLIMBUS_0_TX", MSM_BACKEND_DAI_SLIMBUS_0_TX, + SOC_DOUBLE_EXT("SLIMBUS_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("SLIMBUS_1_TX", MSM_BACKEND_DAI_SLIMBUS_1_TX, + SOC_DOUBLE_EXT("SLIMBUS_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("SLIMBUS_3_TX", MSM_BACKEND_DAI_SLIMBUS_3_TX, + SOC_DOUBLE_EXT("SLIMBUS_3_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_TX, MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("SLIMBUS_4_TX", MSM_BACKEND_DAI_SLIMBUS_4_TX, + SOC_DOUBLE_EXT("SLIMBUS_4_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_4_TX, MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("SLIMBUS_5_TX", MSM_BACKEND_DAI_SLIMBUS_5_TX, + SOC_DOUBLE_EXT("SLIMBUS_5_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_TX, MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("INT3_MI2S_TX", MSM_BACKEND_DAI_INT3_MI2S_TX, + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, MSM_FRONTEND_DAI_LSM3, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), }; static const struct snd_kcontrol_new lsm4_mixer_controls[] = { - SOC_SINGLE_EXT("SLIMBUS_0_TX", MSM_BACKEND_DAI_SLIMBUS_0_TX, + SOC_DOUBLE_EXT("SLIMBUS_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("SLIMBUS_1_TX", MSM_BACKEND_DAI_SLIMBUS_1_TX, + SOC_DOUBLE_EXT("SLIMBUS_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("SLIMBUS_3_TX", MSM_BACKEND_DAI_SLIMBUS_3_TX, + SOC_DOUBLE_EXT("SLIMBUS_3_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_TX, MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("SLIMBUS_4_TX", MSM_BACKEND_DAI_SLIMBUS_4_TX, + SOC_DOUBLE_EXT("SLIMBUS_4_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_4_TX, MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("SLIMBUS_5_TX", MSM_BACKEND_DAI_SLIMBUS_5_TX, + SOC_DOUBLE_EXT("SLIMBUS_5_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_TX, MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("INT3_MI2S_TX", MSM_BACKEND_DAI_INT3_MI2S_TX, + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, MSM_FRONTEND_DAI_LSM4, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), }; static const struct snd_kcontrol_new lsm5_mixer_controls[] = { - SOC_SINGLE_EXT("SLIMBUS_0_TX", MSM_BACKEND_DAI_SLIMBUS_0_TX, + SOC_DOUBLE_EXT("SLIMBUS_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("SLIMBUS_1_TX", MSM_BACKEND_DAI_SLIMBUS_1_TX, + SOC_DOUBLE_EXT("SLIMBUS_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("SLIMBUS_3_TX", MSM_BACKEND_DAI_SLIMBUS_3_TX, + SOC_DOUBLE_EXT("SLIMBUS_3_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_TX, MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("SLIMBUS_4_TX", MSM_BACKEND_DAI_SLIMBUS_4_TX, + SOC_DOUBLE_EXT("SLIMBUS_4_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_4_TX, MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("SLIMBUS_5_TX", MSM_BACKEND_DAI_SLIMBUS_5_TX, + SOC_DOUBLE_EXT("SLIMBUS_5_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_TX, MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("INT3_MI2S_TX", MSM_BACKEND_DAI_INT3_MI2S_TX, + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, MSM_FRONTEND_DAI_LSM5, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), }; static const struct snd_kcontrol_new lsm6_mixer_controls[] = { - SOC_SINGLE_EXT("SLIMBUS_0_TX", MSM_BACKEND_DAI_SLIMBUS_0_TX, + SOC_DOUBLE_EXT("SLIMBUS_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("SLIMBUS_1_TX", MSM_BACKEND_DAI_SLIMBUS_1_TX, + SOC_DOUBLE_EXT("SLIMBUS_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("SLIMBUS_3_TX", MSM_BACKEND_DAI_SLIMBUS_3_TX, + SOC_DOUBLE_EXT("SLIMBUS_3_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_TX, MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("SLIMBUS_4_TX", MSM_BACKEND_DAI_SLIMBUS_4_TX, + SOC_DOUBLE_EXT("SLIMBUS_4_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_4_TX, MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("SLIMBUS_5_TX", MSM_BACKEND_DAI_SLIMBUS_5_TX, + SOC_DOUBLE_EXT("SLIMBUS_5_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_TX, MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("INT3_MI2S_TX", MSM_BACKEND_DAI_INT3_MI2S_TX, + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, MSM_FRONTEND_DAI_LSM6, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), }; static const struct snd_kcontrol_new lsm7_mixer_controls[] = { - SOC_SINGLE_EXT("SLIMBUS_0_TX", MSM_BACKEND_DAI_SLIMBUS_0_TX, + SOC_DOUBLE_EXT("SLIMBUS_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("SLIMBUS_1_TX", MSM_BACKEND_DAI_SLIMBUS_1_TX, + SOC_DOUBLE_EXT("SLIMBUS_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("SLIMBUS_3_TX", MSM_BACKEND_DAI_SLIMBUS_3_TX, + SOC_DOUBLE_EXT("SLIMBUS_3_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_TX, MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("SLIMBUS_4_TX", MSM_BACKEND_DAI_SLIMBUS_4_TX, + SOC_DOUBLE_EXT("SLIMBUS_4_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_4_TX, MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("SLIMBUS_5_TX", MSM_BACKEND_DAI_SLIMBUS_5_TX, + SOC_DOUBLE_EXT("SLIMBUS_5_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_TX, MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("INT3_MI2S_TX", MSM_BACKEND_DAI_INT3_MI2S_TX, + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, MSM_FRONTEND_DAI_LSM7, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), }; static const struct snd_kcontrol_new lsm8_mixer_controls[] = { - SOC_SINGLE_EXT("SLIMBUS_0_TX", MSM_BACKEND_DAI_SLIMBUS_0_TX, + SOC_DOUBLE_EXT("SLIMBUS_0_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_0_TX, MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("SLIMBUS_1_TX", MSM_BACKEND_DAI_SLIMBUS_1_TX, + SOC_DOUBLE_EXT("SLIMBUS_1_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_1_TX, MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("SLIMBUS_3_TX", MSM_BACKEND_DAI_SLIMBUS_3_TX, + SOC_DOUBLE_EXT("SLIMBUS_3_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_3_TX, MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("SLIMBUS_4_TX", MSM_BACKEND_DAI_SLIMBUS_4_TX, + SOC_DOUBLE_EXT("SLIMBUS_4_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_4_TX, MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("SLIMBUS_5_TX", MSM_BACKEND_DAI_SLIMBUS_5_TX, + SOC_DOUBLE_EXT("SLIMBUS_5_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_SLIMBUS_5_TX, MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("TERT_MI2S_TX", MSM_BACKEND_DAI_TERTIARY_MI2S_TX, + SOC_DOUBLE_EXT("TERT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_TERTIARY_MI2S_TX, MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("QUAT_MI2S_TX", MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, + SOC_DOUBLE_EXT("QUAT_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_QUATERNARY_MI2S_TX, MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), - SOC_SINGLE_EXT("INT3_MI2S_TX", MSM_BACKEND_DAI_INT3_MI2S_TX, + SOC_DOUBLE_EXT("INT3_MI2S_TX", SND_SOC_NOPM, + MSM_BACKEND_DAI_INT3_MI2S_TX, MSM_FRONTEND_DAI_LSM8, 1, 0, msm_routing_get_listen_mixer, msm_routing_put_listen_mixer), }; @@ -11962,15 +14148,18 @@ static int msm_routing_put_lsm_app_type_cfg_control( struct snd_ctl_elem_value *ucontrol) { int i = 0, j; - int num_app_types = ucontrol->value.integer.value[i++]; + int num_app_types; - memset(lsm_app_type_cfg, 0, MAX_APP_TYPES* - sizeof(struct msm_pcm_routing_app_type_data)); - if (num_app_types > MAX_APP_TYPES) { + if (ucontrol->value.integer.value[0] > MAX_APP_TYPES) { pr_err("%s: number of app types exceed the max supported\n", __func__); return -EINVAL; } + + num_app_types = ucontrol->value.integer.value[i++]; + memset(lsm_app_type_cfg, 0, MAX_APP_TYPES* + sizeof(struct msm_pcm_routing_app_type_data)); + for (j = 0; j < num_app_types; j++) { lsm_app_type_cfg[j].app_type = ucontrol->value.integer.value[i++]; @@ -12578,49 +14767,49 @@ static const char * const int4_mi2s_rx_vi_fb_tx_stereo_mux_text[] = { "ZERO", "INT5_MI2S_TX" }; -static const int slim0_rx_vi_fb_tx_lch_value[] = { +static const int const slim0_rx_vi_fb_tx_lch_value[] = { MSM_BACKEND_DAI_MAX, MSM_BACKEND_DAI_SLIMBUS_4_TX }; -static const int slim0_rx_vi_fb_tx_rch_value[] = { +static const int const slim0_rx_vi_fb_tx_rch_value[] = { MSM_BACKEND_DAI_MAX, MSM_BACKEND_DAI_SLIMBUS_4_TX }; -static const int mi2s_rx_vi_fb_tx_value[] = { +static const int const mi2s_rx_vi_fb_tx_value[] = { MSM_BACKEND_DAI_MAX, MSM_BACKEND_DAI_SENARY_MI2S_TX }; -static const int int4_mi2s_rx_vi_fb_tx_mono_ch_value[] = { +static const int const int4_mi2s_rx_vi_fb_tx_mono_ch_value[] = { MSM_BACKEND_DAI_MAX, MSM_BACKEND_DAI_INT5_MI2S_TX }; -static const int int4_mi2s_rx_vi_fb_tx_stereo_ch_value[] = { +static const int const int4_mi2s_rx_vi_fb_tx_stereo_ch_value[] = { MSM_BACKEND_DAI_MAX, MSM_BACKEND_DAI_INT5_MI2S_TX }; static const struct soc_enum slim0_rx_vi_fb_lch_mux_enum = - SOC_VALUE_ENUM_DOUBLE(0, MSM_BACKEND_DAI_SLIMBUS_0_RX, 0, 0, + SOC_VALUE_ENUM_DOUBLE(SND_SOC_NOPM, MSM_BACKEND_DAI_SLIMBUS_0_RX, 0, 0, ARRAY_SIZE(slim0_rx_vi_fb_tx_lch_mux_text), slim0_rx_vi_fb_tx_lch_mux_text, slim0_rx_vi_fb_tx_lch_value); static const struct soc_enum slim0_rx_vi_fb_rch_mux_enum = - SOC_VALUE_ENUM_DOUBLE(0, MSM_BACKEND_DAI_SLIMBUS_0_RX, 0, 0, + SOC_VALUE_ENUM_DOUBLE(SND_SOC_NOPM, MSM_BACKEND_DAI_SLIMBUS_0_RX, 0, 0, ARRAY_SIZE(slim0_rx_vi_fb_tx_rch_mux_text), slim0_rx_vi_fb_tx_rch_mux_text, slim0_rx_vi_fb_tx_rch_value); static const struct soc_enum mi2s_rx_vi_fb_mux_enum = - SOC_VALUE_ENUM_DOUBLE(0, MSM_BACKEND_DAI_PRI_MI2S_RX, 0, 0, + SOC_VALUE_ENUM_DOUBLE(SND_SOC_NOPM, MSM_BACKEND_DAI_PRI_MI2S_RX, 0, 0, ARRAY_SIZE(mi2s_rx_vi_fb_tx_mux_text), mi2s_rx_vi_fb_tx_mux_text, mi2s_rx_vi_fb_tx_value); static const struct soc_enum int4_mi2s_rx_vi_fb_mono_ch_mux_enum = - SOC_VALUE_ENUM_DOUBLE(0, MSM_BACKEND_DAI_INT4_MI2S_RX, 0, 0, + SOC_VALUE_ENUM_DOUBLE(SND_SOC_NOPM, MSM_BACKEND_DAI_INT4_MI2S_RX, 0, 0, ARRAY_SIZE(int4_mi2s_rx_vi_fb_tx_mono_mux_text), int4_mi2s_rx_vi_fb_tx_mono_mux_text, int4_mi2s_rx_vi_fb_tx_mono_ch_value); static const struct soc_enum int4_mi2s_rx_vi_fb_stereo_ch_mux_enum = - SOC_VALUE_ENUM_DOUBLE(0, MSM_BACKEND_DAI_INT4_MI2S_RX, 0, 0, + SOC_VALUE_ENUM_DOUBLE(SND_SOC_NOPM, MSM_BACKEND_DAI_INT4_MI2S_RX, 0, 0, ARRAY_SIZE(int4_mi2s_rx_vi_fb_tx_stereo_mux_text), int4_mi2s_rx_vi_fb_tx_stereo_mux_text, int4_mi2s_rx_vi_fb_tx_stereo_ch_value); diff --git a/techpack/audio/asoc/sdm845.c b/techpack/audio/asoc/sdm845.c index 688aced7466f..ff095a32e896 100644 --- a/techpack/audio/asoc/sdm845.c +++ b/techpack/audio/asoc/sdm845.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved. - * Copyright (C) 2019 XiaoMi, Inc. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -2958,36 +2958,36 @@ static int msm_qos_ctl_put(struct snd_kcontrol *kcontrol, } static int ultrasound_power_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) + struct snd_ctl_elem_value *ucontrol) { - ucontrol->value.integer.value[0] = ultrasound_power_state; - return 0; + ucontrol->value.integer.value[0] = ultrasound_power_state; + return 0; } static int ultrasound_power_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) + struct snd_ctl_elem_value *ucontrol) { - struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); - struct snd_soc_card *card = codec->component.card; - struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); - int ret; + struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol); + struct snd_soc_card *card = codec->component.card; + struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); + int ret; - ultrasound_power_state = ucontrol->value.integer.value[0]; - pr_debug("%s: ultrasound power %d\n", __func__, ultrasound_power_state); + ultrasound_power_state = ucontrol->value.integer.value[0]; + pr_debug("%s: ultrasound power %d\n", __func__, ultrasound_power_state); - if (ultrasound_power_state == 1) { - if (pdata->us_p_power) - ret = regulator_enable(pdata->us_p_power); - if (pdata->us_n_power) - ret = regulator_enable(pdata->us_n_power); - } else { - if (pdata->us_p_power) - ret = regulator_disable(pdata->us_p_power); - if (pdata->us_n_power) - ret = regulator_disable(pdata->us_n_power); - } + if (ultrasound_power_state == 1) { + if (pdata->us_p_power) + ret = regulator_enable(pdata->us_p_power); + if (pdata->us_n_power) + ret = regulator_enable(pdata->us_n_power); + } else { + if (pdata->us_p_power) + ret = regulator_disable(pdata->us_p_power); + if (pdata->us_n_power) + ret = regulator_disable(pdata->us_n_power); + } - return 0; + return 0; } static int usbhs_direction_get(struct snd_kcontrol *kcontrol, @@ -3004,15 +3004,18 @@ static int usbhs_direction_get(struct snd_kcontrol *kcontrol, card = codec->component.card; if (card) { pdata = snd_soc_card_get_drvdata(card); - if (pdata){ + if (pdata) { if (pdata->usbc_en2_gpio_p) { - ucontrol->value.integer.value[0] = gpio_get_value_cansleep(pdata->usbc_en2_gpio); + ucontrol->value.integer.value[0] = + gpio_get_value_cansleep(pdata->usbc_en2_gpio); } else if (pdata->usbc_en2_gpio > 0) { - ucontrol->value.integer.value[0] = gpio_get_value_cansleep(pdata->usbc_en2_gpio); + ucontrol->value.integer.value[0] = + gpio_get_value_cansleep(pdata->usbc_en2_gpio); } } } } + return 0; } @@ -3025,6 +3028,8 @@ static const struct snd_kcontrol_new msm_snd_controls[] = { msm_slim_tx_ch_get, msm_slim_tx_ch_put), SOC_ENUM_EXT("SLIM_1_TX Channels", slim_1_tx_chs, msm_slim_tx_ch_get, msm_slim_tx_ch_put), + SOC_ENUM_EXT("SLIM_3_TX Channels", slim_3_tx_chs, + msm_slim_tx_ch_get, msm_slim_tx_ch_put), SOC_ENUM_EXT("SLIM_5_RX Channels", slim_5_rx_chs, msm_slim_rx_ch_get, msm_slim_rx_ch_put), SOC_ENUM_EXT("SLIM_6_RX Channels", slim_6_rx_chs, @@ -3047,6 +3052,8 @@ static const struct snd_kcontrol_new msm_snd_controls[] = { slim_rx_bit_format_get, slim_rx_bit_format_put), SOC_ENUM_EXT("SLIM_0_TX Format", slim_0_tx_format, slim_tx_bit_format_get, slim_tx_bit_format_put), + SOC_ENUM_EXT("SLIM_3_TX Format", slim_3_tx_format, + slim_tx_bit_format_get, slim_tx_bit_format_put), SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format, usb_audio_rx_format_get, usb_audio_rx_format_put), SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format, @@ -3059,6 +3066,8 @@ static const struct snd_kcontrol_new msm_snd_controls[] = { slim_rx_sample_rate_get, slim_rx_sample_rate_put), SOC_ENUM_EXT("SLIM_0_TX SampleRate", slim_0_tx_sample_rate, slim_tx_sample_rate_get, slim_tx_sample_rate_put), + SOC_ENUM_EXT("SLIM_3_TX SampleRate", slim_3_tx_sample_rate, + slim_tx_sample_rate_get, slim_tx_sample_rate_put), SOC_ENUM_EXT("SLIM_5_RX SampleRate", slim_5_rx_sample_rate, slim_rx_sample_rate_get, slim_rx_sample_rate_put), SOC_ENUM_EXT("SLIM_6_RX SampleRate", slim_6_rx_sample_rate, @@ -3265,15 +3274,9 @@ static const struct snd_kcontrol_new msm_snd_controls[] = { SOC_ENUM_EXT("Ultrasound Power", ultrasound_power, ultrasound_power_get, ultrasound_power_put), SOC_SINGLE_EXT("USB Headset Direction", 0, 0, UINT_MAX, 0, - usbhs_direction_get, NULL), + usbhs_direction_get, NULL), SOC_SINGLE_MULTI_EXT("TDM Slot Map", SND_SOC_NOPM, 0, 255, 0, 4, NULL, tdm_slot_map_put), - SOC_ENUM_EXT("SLIM_3_TX Channels", slim_3_tx_chs, - msm_slim_tx_ch_get, msm_slim_tx_ch_put), - SOC_ENUM_EXT("SLIM_3_TX Format", slim_3_tx_format, - slim_tx_bit_format_get, slim_tx_bit_format_put), - SOC_ENUM_EXT("SLIM_3_TX SampleRate", slim_3_tx_sample_rate, - slim_tx_sample_rate_get, slim_tx_sample_rate_put), }; static int msm_snd_enable_codec_ext_clk(struct snd_soc_codec *codec, @@ -3372,15 +3375,6 @@ static int msm_hifi_ctrl_event(struct snd_soc_dapm_widget *w, return 0; } -/* -static int external_amic2_sel_get(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) -{ - ucontrol->value.integer.value[0] = amic2_sel_state; - return 0; -} -*/ - static void external_enable_dual_adc_gpio(struct device_node *np, bool val) { if (!np) @@ -3395,8 +3389,17 @@ static void external_enable_dual_adc_gpio(struct device_node *np, bool val) } } +/* +static int external_amic2_sel_get(struct snd_kcontrol *kcontrol, + struct snd_ctl_elem_value *ucontrol) +{ + ucontrol->value.integer.value[0] = amic2_sel_state; + return 0; +} +*/ + static int external_amic2_sel_put(struct snd_kcontrol *kcontrol, - struct snd_ctl_elem_value *ucontrol) + struct snd_ctl_elem_value *ucontrol) { struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kcontrol); struct snd_soc_card *card = dapm->card; @@ -3451,13 +3454,13 @@ static const struct snd_soc_dapm_widget msm_dapm_widgets[] = { SND_SOC_DAPM_MIC("Headset Mic2", NULL), }; -static const struct snd_soc_dapm_widget sdm845_polaris_dapm_widgets[] = { +static const struct snd_soc_dapm_widget sdm845_xiaomi_dapm_widgets[] = { SND_SOC_DAPM_MUX("External AMIC2 Mux", SND_SOC_NOPM, 0, 0, &ext_amc2_mux), SND_SOC_DAPM_INPUT("AMIC2_EXT_0"), SND_SOC_DAPM_INPUT("AMIC2_EXT_1"), }; -static const struct snd_soc_dapm_route sdm845_polaris_dapm_routes[] = { +static const struct snd_soc_dapm_route sdm845_xiaomi_dapm_routes[] = { {"AMIC2", NULL, "External AMIC2 Mux"}, {"External AMIC2 Mux", "default", "AMIC2_EXT_0"}, {"External AMIC2 Mux", "Dual_ADC", "AMIC2_EXT_1"}, @@ -3887,11 +3890,11 @@ static bool msm_usbc_swap_gnd_mic(struct snd_soc_codec *codec, bool active) { int value = 0; bool ret = 0; + int old_value; struct snd_soc_card *card = codec->component.card; struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card); struct pinctrl_state *en2_pinctrl_active; struct pinctrl_state *en2_pinctrl_sleep; - int oldv; if (!pdata->usbc_en2_gpio_p) { if (active) { @@ -3942,8 +3945,17 @@ static bool msm_usbc_swap_gnd_mic(struct snd_soc_codec *codec, bool active) /* if active and usbc_en2_gpio_p defined, swap using usbc_en2_gpio_p */ if (active) { dev_dbg(codec->dev, "%s: enter\n", __func__); - oldv = tavil_mb_pull_down(codec, true, 0); - if (pdata->usbc_en2_gpio_p) { + old_value = tavil_mb_pull_down(codec, true, 0); + if (wcd_mbhc_cfg.usbc_analog_cfg.euro_us_hw_switch_gpio_p) { + value = gpio_get_value_cansleep(pdata->usbc_en2_gpio); + if (value) + msm_cdc_pinctrl_select_sleep_state(wcd_mbhc_cfg. + usbc_analog_cfg.euro_us_hw_switch_gpio_p); + else + msm_cdc_pinctrl_select_active_state(wcd_mbhc_cfg. + usbc_analog_cfg.euro_us_hw_switch_gpio_p); + } + else if (pdata->usbc_en2_gpio_p) { value = gpio_get_value_cansleep(pdata->usbc_en2_gpio); if (value) pinctrl_select_state(pdata->usbc_en2_gpio_p, @@ -3955,8 +3967,8 @@ static bool msm_usbc_swap_gnd_mic(struct snd_soc_codec *codec, bool active) value = gpio_get_value_cansleep(pdata->usbc_en2_gpio); gpio_set_value_cansleep(pdata->usbc_en2_gpio, !value); } - tavil_mb_pull_down(codec, false, oldv); - pr_info("%s: swap select switch %d to %d\n", __func__, + tavil_mb_pull_down(codec, false, old_value); + pr_debug("%s: swap select switch %d to %d\n", __func__, value, !value); ret = true; } else { @@ -4222,16 +4234,16 @@ static int msm_audrx_init(struct snd_soc_pcm_runtime *rtd) ARRAY_SIZE(wcd_audio_paths)); if (get_hw_version_platform() == HARDWARE_PLATFORM_POLARIS || - get_hw_version_platform() == HARDWARE_PLATFORM_DIPPERN || - get_hw_version_platform() == HARDWARE_PLATFORM_URSA || - get_hw_version_platform() == HARDWARE_PLATFORM_EQUULEUS || - get_hw_version_platform() == HARDWARE_PLATFORM_PERSEUS) { + get_hw_version_platform() == HARDWARE_PLATFORM_DIPPERN || + get_hw_version_platform() == HARDWARE_PLATFORM_URSA || + get_hw_version_platform() == HARDWARE_PLATFORM_EQUULEUS || + get_hw_version_platform() == HARDWARE_PLATFORM_PERSEUS) { pr_info("add the External AMIC2 Mux\n"); - snd_soc_dapm_new_controls(dapm, sdm845_polaris_dapm_widgets, - ARRAY_SIZE(sdm845_polaris_dapm_widgets)); + snd_soc_dapm_new_controls(dapm, sdm845_xiaomi_dapm_widgets, + ARRAY_SIZE(sdm845_xiaomi_dapm_widgets)); - snd_soc_dapm_add_routes(dapm, sdm845_polaris_dapm_routes, - ARRAY_SIZE(sdm845_polaris_dapm_routes)); + snd_soc_dapm_add_routes(dapm, sdm845_xiaomi_dapm_routes, + ARRAY_SIZE(sdm845_xiaomi_dapm_routes)); } snd_soc_dapm_ignore_suspend(dapm, "Handset Mic"); @@ -7007,16 +7019,16 @@ static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev) sizeof(msm_mi2s_be_dai_links)); total_links += ARRAY_SIZE(msm_mi2s_be_dai_links); - if ((get_hw_version_platform() == HARDWARE_PLATFORM_DIPPERN) || - (get_hw_version_platform() == HARDWARE_PLATFORM_URSA) || - (get_hw_version_platform() == HARDWARE_PLATFORM_EQUULEUS) || - (get_hw_version_platform() == HARDWARE_PLATFORM_PERSEUS)) { + if (get_hw_version_platform() == HARDWARE_PLATFORM_DIPPERN || + get_hw_version_platform() == HARDWARE_PLATFORM_URSA || + get_hw_version_platform() == HARDWARE_PLATFORM_EQUULEUS || + get_hw_version_platform() == HARDWARE_PLATFORM_PERSEUS) { memcpy(msm_tavil_snd_card_dai_links + total_links, msm_quat_mi2s_tas2557_dai_links, sizeof(msm_quat_mi2s_tas2557_dai_links)); total_links += ARRAY_SIZE(msm_quat_mi2s_tas2557_dai_links); - } else if ((get_hw_version_platform() == HARDWARE_PLATFORM_POLARIS) || - (get_hw_version_platform() == HARDWARE_PLATFORM_BERYLLIUM)) { + } else if (get_hw_version_platform() == HARDWARE_PLATFORM_POLARIS || + get_hw_version_platform() == HARDWARE_PLATFORM_BERYLLIUM) { memcpy(msm_tavil_snd_card_dai_links + total_links, msm_quat_mi2s_tas2559_dai_links, sizeof(msm_quat_mi2s_tas2559_dai_links)); @@ -7514,7 +7526,6 @@ static int msm_asoc_machine_probe(struct platform_device *pdev) if (ret) dev_err(&pdev->dev, "msm_prepare_us_euro failed (%d)\n", ret); - } /* Parse pinctrl info from devicetree */ diff --git a/techpack/audio/dsp/avtimer.c b/techpack/audio/dsp/avtimer.c index 10a2964c3609..a2e745a53ff6 100644 --- a/techpack/audio/dsp/avtimer.c +++ b/techpack/audio/dsp/avtimer.c @@ -93,6 +93,13 @@ static int32_t aprv2_core_fn_q(struct apr_client_data *data, void *priv) } payload1 = data->payload; + + if (data->payload_size < 2 * sizeof(uint32_t)) { + pr_err("%s: payload has invalid size %d\n", + __func__, data->payload_size); + return -EINVAL; + } + switch (payload1[0]) { case AVCS_CMD_REMOTE_AVTIMER_RELEASE_REQUEST: pr_debug("%s: Cmd = TIMER RELEASE status[0x%x]\n", @@ -118,6 +125,11 @@ static int32_t aprv2_core_fn_q(struct apr_client_data *data, void *priv) } case AVCS_CMD_RSP_REMOTE_AVTIMER_VOTE_REQUEST: + if (data->payload_size < sizeof(uint32_t)) { + pr_err("%s: payload has invalid size %d\n", + __func__, data->payload_size); + return -EINVAL; + } payload1 = data->payload; pr_debug("%s: RSP_REMOTE_AVTIMER_VOTE_REQUEST handle %x\n", __func__, payload1[0]); diff --git a/techpack/audio/dsp/q6adm.c b/techpack/audio/dsp/q6adm.c index 17e2abfc9e6b..33bd95895cdf 100644 --- a/techpack/audio/dsp/q6adm.c +++ b/techpack/audio/dsp/q6adm.c @@ -1,5 +1,4 @@ /* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. - * Copyright (C) 2019 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -1574,7 +1573,8 @@ static int32_t adm_callback(struct apr_client_data *data, void *priv) idx = ADM_GET_PARAMETER_LENGTH * copp_idx; if ((payload[0] == 0) && (data->payload_size > (4 * sizeof(*payload))) && - (data->payload_size - 4 >= + (data->payload_size - + (4 * sizeof(*payload)) >= payload[3]) && (ARRAY_SIZE(adm_get_parameters) > idx) && @@ -1615,9 +1615,12 @@ static int32_t adm_callback(struct apr_client_data *data, void *priv) pr_err(":err = 0x%x\n", payload[0]); } else if (data->payload_size >= (2 * sizeof(uint32_t))) { - if (payload[1] > + if ((payload[1] > ((ADM_GET_TOPO_MODULE_LIST_LENGTH / - sizeof(uint32_t)) - 1)) { + sizeof(uint32_t)) - 1)) || + ((data->payload_size - + (2 * sizeof(uint32_t))) < + (payload[1] * sizeof(uint32_t)))) { pr_err("%s: ADM_CMDRSP_GET_PP_TOPO_MODULE_LIST", __func__); pr_err(":size = %d\n", payload[1]); diff --git a/techpack/audio/dsp/q6afe.c b/techpack/audio/dsp/q6afe.c index bfaebc10234f..57b2f4285c26 100644 --- a/techpack/audio/dsp/q6afe.c +++ b/techpack/audio/dsp/q6afe.c @@ -1,5 +1,5 @@ /* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved. - * Copyright (C) 2019 XiaoMi, Inc. + * Copyright (C) 2018 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -21,12 +21,12 @@ #include #include #include +#include #include #include #include #include #include "adsp_err.h" -#include #define WAKELOCK_TIMEOUT 5000 enum { @@ -385,11 +385,12 @@ static int32_t afe_callback(struct apr_client_data *data, void *priv) wake_up(&this_afe.wait[data->token]); else return -EINVAL; -} else if (data->opcode == ULTRASOUND_OPCODE) { + } else if (data->opcode == ULTRASOUND_OPCODE) { if (data->payload != NULL) elliptic_process_apr_payload(data->payload); else pr_err("[ELUS]: payload is invalid"); + } else if (data->payload_size) { uint32_t *payload; uint16_t port_id = 0; @@ -1132,7 +1133,6 @@ static int afe_spk_prot_prepare(int src_port, int dst_port, int param_id, return ret; } -/* ELUS Begin */ afe_ultrasound_state_t elus_afe = { .ptr_apr = &this_afe.apr, .ptr_status = &this_afe.status, @@ -1141,7 +1141,6 @@ afe_ultrasound_state_t elus_afe = { .timeout_ms = TIMEOUT_MS, }; EXPORT_SYMBOL(elus_afe); -/* ELUS End */ static void afe_send_cal_spkr_prot_tx(int port_id) { @@ -3022,7 +3021,7 @@ static int q6afe_send_enc_config(u16 port_id, union afe_enc_config_data *cfg, u32 format, union afe_port_config afe_config, u16 afe_in_channels, u16 afe_in_bit_width, - u32 scrambler_mode) + u32 scrambler_mode, u32 mono_mode) { struct afe_audioif_config_command config; int index; @@ -3178,8 +3177,22 @@ static int q6afe_send_enc_config(u16 port_id, goto exit; } + if (format == ASM_MEDIA_FMT_APTX) { + config.param.payload_size = + payload_size + sizeof(config.port.channel_mode_param); + pr_debug("%s:sending CAPI_V2_PARAM_ID_APTX_ENC_SWITCH_TO_MONO mode= %d to DSP payload\n", + __func__, mono_mode); + config.pdata.param_id = CAPI_V2_PARAM_ID_APTX_ENC_SWITCH_TO_MONO; + config.pdata.param_size = sizeof(config.port.channel_mode_param); + config.port.channel_mode_param.channel_mode = mono_mode; + ret = afe_apr_send_pkt(&config, &this_afe.wait[index]); + if (ret) { + pr_err("%s: CAPI_V2_PARAM_ID_APTX_ENC_SWITCH_TO_MONO for port 0x%x failed %d\n", + __func__, port_id, ret); + } + } if (format == ASM_MEDIA_FMT_LDAC && - cfg->ldac_config.abr_config.is_abr_enabled) { + cfg->ldac_config.abr_config.is_abr_enabled) { config.param.payload_size = payload_size + sizeof(config.port.map_param); pr_debug("%s:sending AFE_ENCODER_PARAM_ID_BIT_RATE_LEVEL_MAP to DSP payload = %d\n", @@ -3252,10 +3265,61 @@ static int q6afe_send_enc_config(u16 port_id, return ret; } +int afe_set_tws_channel_mode(u16 port_id, u32 channel_mode) +{ + struct aptx_channel_mode_param_t channel_mode_param; + int ret = 0; + int index = 0; + + pr_debug("%s: enter\n", __func__); + index = q6audio_get_port_index(port_id); + if (index < 0 || index >= AFE_MAX_PORTS) { + pr_err("%s: AFE port index[%d] invalid!\n", + __func__, index); + return -EINVAL; + } + + ret = q6audio_validate_port(port_id); + if (ret < 0) { + pr_err("%s: port id: 0x%x ret %d\n", __func__, port_id, ret); + return -EINVAL; + } + + channel_mode_param.hdr.hdr_field = APR_HDR_FIELD(APR_MSG_TYPE_SEQ_CMD, + APR_HDR_LEN(APR_HDR_SIZE), APR_PKT_VER); + channel_mode_param.hdr.pkt_size = sizeof(channel_mode_param); + channel_mode_param.hdr.src_port = 0; + channel_mode_param.hdr.dest_port = 0; + channel_mode_param.hdr.token = index; + + channel_mode_param.hdr.opcode = AFE_PORT_CMD_SET_PARAM_V2; + channel_mode_param.param.payload_size = sizeof(channel_mode_param) - sizeof(struct apr_hdr) + - sizeof(channel_mode_param.param); + + channel_mode_param.param.payload_address_lsw = 0x00; + channel_mode_param.param.payload_address_msw = 0x00; + channel_mode_param.param.mem_map_handle = 0x00; + channel_mode_param.param.port_id = q6audio_get_port_id(port_id); + channel_mode_param.pdata.module_id = AFE_MODULE_ID_ENCODER; + channel_mode_param.pdata.param_id = CAPI_V2_PARAM_ID_APTX_ENC_SWITCH_TO_MONO; + channel_mode_param.pdata.param_size = sizeof(channel_mode_param.channel_mode); + + channel_mode_param.channel_mode = channel_mode; + + ret = afe_apr_send_pkt(&channel_mode_param, &this_afe.wait[index]); + + if (ret) + pr_err("%s: AFE set channel mode cfg for port 0x%x failed %d\n", + __func__, port_id, ret); + + return ret; +} +EXPORT_SYMBOL(afe_set_tws_channel_mode); + static int __afe_port_start(u16 port_id, union afe_port_config *afe_config, u32 rate, u16 afe_in_channels, u16 afe_in_bit_width, union afe_enc_config_data *enc_cfg, - u32 codec_format, u32 scrambler_mode, + u32 codec_format, u32 scrambler_mode, u32 mono_mode, struct afe_dec_config *dec_cfg) { struct afe_audioif_config_command config; @@ -3523,7 +3587,7 @@ static int __afe_port_start(u16 port_id, union afe_port_config *afe_config, codec_format, *afe_config, afe_in_channels, afe_in_bit_width, - scrambler_mode); + scrambler_mode, mono_mode); if (ret) { pr_err("%s: AFE encoder config for port 0x%x failed %d\n", __func__, port_id, ret); @@ -3588,7 +3652,7 @@ int afe_port_start(u16 port_id, union afe_port_config *afe_config, u32 rate) { return __afe_port_start(port_id, afe_config, rate, - 0, 0, NULL, ASM_MEDIA_FMT_NONE, 0, NULL); + 0, 0, NULL, ASM_MEDIA_FMT_NONE, 0, 0, NULL); } EXPORT_SYMBOL(afe_port_start); @@ -3617,11 +3681,12 @@ int afe_port_start_v2(u16 port_id, union afe_port_config *afe_config, ret = __afe_port_start(port_id, afe_config, rate, afe_in_channels, afe_in_bit_width, &enc_cfg->data, enc_cfg->format, - enc_cfg->scrambler_mode, dec_cfg); + enc_cfg->scrambler_mode, + enc_cfg->mono_mode, dec_cfg); else if (dec_cfg != NULL) ret = __afe_port_start(port_id, afe_config, rate, afe_in_channels, afe_in_bit_width, - NULL, dec_cfg->format, 0, dec_cfg); + NULL, dec_cfg->format, 0, 0, dec_cfg); return ret; } diff --git a/techpack/audio/dsp/q6audio-v2.c b/techpack/audio/dsp/q6audio-v2.c index 2d334ee13e7e..c7170dd41c19 100644 --- a/techpack/audio/dsp/q6audio-v2.c +++ b/techpack/audio/dsp/q6audio-v2.c @@ -1,5 +1,4 @@ /* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved. - * Copyright (C) 2019 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/techpack/audio/dsp/rtac.c b/techpack/audio/dsp/rtac.c index baa33c7e449e..e2d1ad77804d 100644 --- a/techpack/audio/dsp/rtac.c +++ b/techpack/audio/dsp/rtac.c @@ -1,4 +1,4 @@ -/* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. +/* Copyright (c) 2012-2018,2020 The Linux Foundation. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and diff --git a/techpack/audio/include/dsp/q6afe-v2.h b/techpack/audio/include/dsp/q6afe-v2.h index 81bbd4be5ce4..28805553f18f 100644 --- a/techpack/audio/include/dsp/q6afe-v2.h +++ b/techpack/audio/include/dsp/q6afe-v2.h @@ -1,5 +1,4 @@ /* Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. - * Copyright (C) 2019 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -319,6 +318,7 @@ int afe_rt_proxy_port_read(phys_addr_t buf_addr_p, void afe_set_cal_mode(u16 port_id, enum afe_cal_mode afe_cal_mode); int afe_port_start(u16 port_id, union afe_port_config *afe_config, u32 rate); +int afe_set_tws_channel_mode(u16 port_id, u32 channel_mode); int afe_port_start_v2(u16 port_id, union afe_port_config *afe_config, u32 rate, u16 afe_in_channels, u16 afe_in_bit_width, struct afe_enc_config *enc_config, diff --git a/techpack/audio/ipc/wcd-dsp-glink.c b/techpack/audio/ipc/wcd-dsp-glink.c index 96773307b767..a2dbe3661f6c 100644 --- a/techpack/audio/ipc/wcd-dsp-glink.c +++ b/techpack/audio/ipc/wcd-dsp-glink.c @@ -1,5 +1,4 @@ /* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. - * Copyright (C) 2019 XiaoMi, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 and @@ -90,14 +89,6 @@ struct wdsp_glink_ch { /* Wait for ch connect state before sending any command */ wait_queue_head_t ch_connect_wait; - /* - * Used to check if both local disconnect and remote disconnect - * states are notified before freeing channel resources - */ - int ch_close_state; - /* Wait for ch local and remote disconnect before channel free */ - wait_queue_head_t ch_free_wait; - /* * Glink channel configuration. This has to be the last * member of the strucuture as it has variable size @@ -146,7 +137,6 @@ static void wdsp_glink_free_tx_buf_work(struct work_struct *work) tx_buf = container_of(work, struct wdsp_glink_tx_buf, free_tx_work); - vfree(tx_buf); } @@ -173,10 +163,8 @@ static void wdsp_glink_free_tx_buf(const void *priv, const void *pkt_priv) ch = (struct wdsp_glink_ch *)priv; wpriv = ch->wpriv; /* Work queue to free tx pkt */ - if (wpriv && wpriv->work_queue) { - INIT_WORK(&tx_buf->free_tx_work, wdsp_glink_free_tx_buf_work); - queue_work(wpriv->work_queue, &tx_buf->free_tx_work); - } + INIT_WORK(&tx_buf->free_tx_work, wdsp_glink_free_tx_buf_work); + queue_work(wpriv->work_queue, &tx_buf->free_tx_work); } /* @@ -380,7 +368,7 @@ static void wdsp_glink_notify_state(void *handle, const void *priv, ch->ch_cfg.name); wake_up(&ch->ch_connect_wait); - ch->ch_close_state = 0; + mutex_unlock(&ch->mutex); } else if (event == GLINK_LOCAL_DISCONNECTED) { /* * Don't use dev_dbg here as dev may not be valid if channel @@ -388,21 +376,23 @@ static void wdsp_glink_notify_state(void *handle, const void *priv, */ pr_debug("%s: channel: %s disconnected locally\n", __func__, ch->ch_cfg.name); - ch->ch_close_state = ch->ch_close_state | GLINK_LOCAL_DISCONNECTED; - wake_up(&ch->ch_free_wait); + mutex_unlock(&ch->mutex); + + if (ch->free_mem) { + kfree(ch); + ch = NULL; + } } else if (event == GLINK_REMOTE_DISCONNECTED) { dev_dbg(wpriv->dev, "%s: remote channel: %s disconnected remotely\n", __func__, ch->ch_cfg.name); + mutex_unlock(&ch->mutex); /* * If remote disconnect happens, local side also has * to close the channel as per glink design in a * separate work_queue. */ queue_work(wpriv->work_queue, &ch->lcl_ch_cls_wrk); - ch->ch_close_state = ch->ch_close_state | GLINK_REMOTE_DISCONNECTED; - wake_up(&ch->ch_free_wait); } - mutex_unlock(&ch->mutex); } /* @@ -649,8 +639,6 @@ static int wdsp_glink_ch_info_init(struct wdsp_glink_priv *wpriv, goto err_ch_mem; } ch[i]->channel_state = GLINK_LOCAL_DISCONNECTED; - ch[i]->ch_close_state = (GLINK_LOCAL_DISCONNECTED | - GLINK_REMOTE_DISCONNECTED); memcpy(&ch[i]->ch_cfg, payload, ch_cfg_size); payload += ch_cfg_size; @@ -671,11 +659,9 @@ static int wdsp_glink_ch_info_init(struct wdsp_glink_priv *wpriv, mutex_init(&ch[i]->mutex); ch[i]->wpriv = wpriv; - INIT_WORK(&ch[i]->lcl_ch_open_wrk, wdsp_glink_lcl_ch_open_wrk); INIT_WORK(&ch[i]->lcl_ch_cls_wrk, wdsp_glink_lcl_ch_cls_wrk); init_waitqueue_head(&ch[i]->ch_connect_wait); - init_waitqueue_head(&ch[i]->ch_free_wait); } INIT_WORK(&wpriv->ch_open_cls_wrk, wdsp_glink_ch_open_cls_wrk); @@ -1085,38 +1071,34 @@ static int wdsp_glink_release(struct inode *inode, struct file *file) if (wpriv->glink_state.handle) glink_unregister_link_state_cb(wpriv->glink_state.handle); - /* - * Wait for channel local and remote disconnect state notifications - * before freeing channel memory. - */ - for (i = 0; i < wpriv->no_of_channels; i++) { - if (wpriv->ch && wpriv->ch[i]) { - ret = wait_event_timeout(wpriv->ch[i]->ch_free_wait, - (wpriv->ch[i]->ch_close_state == - (GLINK_LOCAL_DISCONNECTED | GLINK_REMOTE_DISCONNECTED)), - msecs_to_jiffies(TIMEOUT_MS)); - if (!ret) { - pr_err("%s: glink channel %s is failed to notify states properly %d\n", - __func__, wpriv->ch[i]->ch_cfg.name, - wpriv->ch[i]->ch_close_state); - ret = -EINVAL; - goto done; - } - } - } flush_workqueue(wpriv->work_queue); destroy_workqueue(wpriv->work_queue); - wpriv->work_queue = NULL; - for (i = 0; i < wpriv->no_of_channels; i++) { - if (wpriv->ch && wpriv->ch[i]) { - kfree(wpriv->ch[i]); - wpriv->ch[i] = NULL; + /* + * Clean up glink channel memory in channel state + * callback only if close channels are called from here. + */ + if (wpriv->ch) { + for (i = 0; i < wpriv->no_of_channels; i++) { + if (wpriv->ch[i]) { + wpriv->ch[i]->free_mem = true; + /* + * Channel handle NULL means channel is already + * closed. Free the channel memory here itself. + */ + if (!wpriv->ch[i]->handle) { + kfree(wpriv->ch[i]); + wpriv->ch[i] = NULL; + } else { + wdsp_glink_close_ch(wpriv->ch[i]); + } + } } + + kfree(wpriv->ch); + wpriv->ch = NULL; } - kfree(wpriv->ch); - wpriv->ch = NULL; mutex_destroy(&wpriv->glink_mutex); mutex_destroy(&wpriv->rsp_mutex);